diff --git a/.clang-format b/.clang-format index e9361226e3..9b3aa8b721 100644 --- a/.clang-format +++ b/.clang-format @@ -1,6 +1 @@ -BraceWrapping: - AfterClass: true - AfterControlStatement: false - AfterFunction: true -BreakBeforeBraces: Custom -UseTab: Always \ No newline at end of file +BasedOnStyle: LLVM diff --git a/.gitignore b/.gitignore index 9a72f29e87..2f562fe025 100644 --- a/.gitignore +++ b/.gitignore @@ -129,3 +129,6 @@ cstool/cstool # android android-ndk-* + +# cmake +cmake-build-debug \ No newline at end of file diff --git a/CMakeLists.txt b/CMakeLists.txt index e6cced70e2..724616c3d2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -29,7 +29,7 @@ option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON) option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON) option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON) option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF) -option(CAPSTONE_INSTALL "Generate install target" OFF) +option(CAPSTONE_INSTALL "Generate install target" ON) set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV) set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV) @@ -89,6 +89,7 @@ set(SOURCES_ENGINE MCInst.c MCInstrDesc.c MCRegisterInfo.c + MCInstPrinter.c SStream.c utils.c ) @@ -101,6 +102,7 @@ set(HEADERS_ENGINE MCInst.h MCInstrDesc.h MCRegisterInfo.h + MCInstPrinter.h SStream.h utils.h ) @@ -201,21 +203,14 @@ if (CAPSTONE_MIPS_SUPPORT) arch/Mips/MipsDisassembler.h arch/Mips/MipsGenAsmWriter.inc arch/Mips/MipsGenDisassemblerTables.inc - arch/Mips/MipsGenInstrInfo.inc - arch/Mips/MipsGenRegisterInfo.inc - arch/Mips/MipsGenSubtargetInfo.inc - arch/Mips/MipsInstPrinter.h + arch/Mips/MipsInstPrinter.h arch/Mips/MipsMapping.h - arch/Mips/MipsMappingInsn.inc - ) + ) set(HEADERS_MIPS arch/Mips/MipsDisassembler.h arch/Mips/MipsGenAsmWriter.inc arch/Mips/MipsGenDisassemblerTables.inc - arch/Mips/MipsGenInstrInfo.inc - arch/Mips/MipsGenRegisterInfo.inc - arch/Mips/MipsGenSubtargetInfo.inc - arch/Mips/MipsInstPrinter.h + arch/Mips/MipsInstPrinter.h arch/Mips/MipsMapping.h ) set(TEST_SOURCES ${TEST_SOURCES} test_mips.c) @@ -606,7 +601,7 @@ if (CAPSTONE_BUILD_TESTS) if (CAPSTONE_ARM_SUPPORT) set(ARM_REGRESS_TEST test_arm_regression.c) STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST}) - add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}") + add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}" sync/logger.h) target_link_libraries(${ARM_REGRESS_BIN} ${default-target}) add_test(NAME "capstone_${ARM_REGRESS_BIN}" COMMAND ${ARM_REGRESS_BIN}) endif() diff --git a/MCInstPrinter.c b/MCInstPrinter.c new file mode 100644 index 0000000000..8c6ecc552f --- /dev/null +++ b/MCInstPrinter.c @@ -0,0 +1,115 @@ +// +// Created by Phosphorus15 on 2021/5/14. +// +#include "MCInstPrinter.h" +#include "MCInst.h" +#include "sync/logger.h" + +static bool MCInstPrinter_matchAliasCondition( + const MCInst *MI, unsigned *OpIdx, const PatternsForOpcode *OpToPatterns, + const AliasPattern *Patterns, const AliasPatternCond *Conds, + const AliasPatternCond *Cond, bool *OrPredicateResult) { + // FIXME so here's on problem we ought to detect feature bits here + if (Cond->Kind == AliasPatternCond_K_Feature || + Cond->Kind == AliasPatternCond_K_NegFeature) + return true; // STI->getFeatureBits().test(C.Value); + // For feature tests where just one feature is required in a list, set the + // predicate result bit to whether the expression will return true, and only + // return the real result at the end of list marker. + if (Cond->Kind == AliasPatternCond_K_OrFeature) { + // *OrPredicateResult |= STI->getFeatureBits().test(C.Value); + return true; + } + if (Cond->Kind == AliasPatternCond_K_OrNegFeature) { + // *OrPredicateResult |= !(STI->getFeatureBits().test(C.Value)); + return true; + } + if (Cond->Kind == AliasPatternCond_K_EndOrFeatures) { + bool Res = *OrPredicateResult; + *OrPredicateResult = false; + return Res; + } + + const MCOperand *Opnd = MCInst_getOperand(MI, *OpIdx); + *OpIdx = *OpIdx + 1; + switch (Cond->Kind) { + case AliasPatternCond_K_Imm: + // Operand must be a specific immediate. + return MCOperand_isImm(Opnd) && MCOperand_getImm(Opnd) == Cond->Value; + case AliasPatternCond_K_Reg: + // Operand must be a specific register. + return MCOperand_isReg(Opnd) && MCOperand_getReg(Opnd) == Cond->Value; + case AliasPatternCond_K_TiedReg: + // Operand must match the register of another operand. + return MCOperand_isReg(Opnd) && + MCOperand_getReg(Opnd) == + MCOperand_getReg(MCInst_getOperand(MI, Cond->Value)); + case AliasPatternCond_K_RegClass: + // Operand must be a register in this class. Value is a register class id. + return MCOperand_isReg(Opnd) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, Cond->Value), + MCOperand_getReg(Opnd)); + case AliasPatternCond_K_Custom: + // Operand must match some custom criteria. + // TODO might affect something return M.ValidateMCOperand(Opnd, + // *STI, C.Value); + return false; + case AliasPatternCond_K_Ignore: + // Operand can be anything. + return true; + case AliasPatternCond_K_Feature: + case AliasPatternCond_K_NegFeature: + case AliasPatternCond_K_OrFeature: + case AliasPatternCond_K_OrNegFeature: + case AliasPatternCond_K_EndOrFeatures: + 0x0; + // llvm_unreachable("handled earlier"); + } +} + +const char *MCInstPrinter_matchAliasPatterns( + const MCInst *MI, const PatternsForOpcode *OpToPatterns, + const AliasPattern *Patterns, const AliasPatternCond *Conds, + const char *AsmStrings[], unsigned len) { + // Binary search by opcode. Return false if there are no aliases for this + // opcode. + PatternsForOpcode *It = + Binary_Search(OpToPatterns, MCInst_getOpcode(MI), len); + debugln("binary search result %p, with opcode %d", It, MCInst_getOpcode(MI)); + if (It == NULL || It->Opcode != MCInst_getOpcode(MI)) + return NULL; + + // Try all patterns for this opcode. + uint32_t AsmStrOffset = ~0U; + + for (unsigned i = It->PatternStart; i < It->PatternStart + It->NumPatterns; + i++) { + const AliasPattern Pattern = Patterns[i]; + if (MCInst_getNumOperands(MI) != Pattern.NumOperands) + return NULL; + unsigned OpIdx = 0; + bool OrPredicateResult = false; + bool fallThrough = true; + for (unsigned j = Pattern.AliasCondStart; + j < Pattern.AliasCondStart + Pattern.NumConds; j++) { + fallThrough &= MCInstPrinter_matchAliasCondition( + MI, &OpIdx, OpToPatterns, Patterns, Conds, &Conds[j], + &OrPredicateResult); + if (!fallThrough) + break; + } + if (fallThrough) { + AsmStrOffset = Pattern.AsmStrOffset; + break; + } + } + + debugln("end matching with offset %d", AsmStrOffset); + // If no alias matched, don't print an alias. + if (AsmStrOffset == ~0U) + return NULL; + debugln("string with final offset %s", + (const char *)((*AsmStrings) + AsmStrOffset)); + return (const char *)((*AsmStrings) + AsmStrOffset); +} \ No newline at end of file diff --git a/MCInstPrinter.h b/MCInstPrinter.h new file mode 100644 index 0000000000..5cbcc61216 --- /dev/null +++ b/MCInstPrinter.h @@ -0,0 +1,73 @@ +// +// Created by Phosphorus15 on 2021/5/14. +// + +#ifndef CAPSTONE_MCINSTPRINTER_H +#define CAPSTONE_MCINSTPRINTER_H + +#include "MCInst.h" +#include "capstone/platform.h" +#include "stdlib.h" + +// TODO we'll need this later +const MCRegisterInfo *MRI; + +typedef enum CondKind { + AliasPatternCond_K_Feature, // Match only if a feature is enabled. + AliasPatternCond_K_NegFeature, // Match only if a feature is disabled. + AliasPatternCond_K_OrFeature, // Match only if one of a set of features is + // enabled. + AliasPatternCond_K_OrNegFeature, // Match only if one of a set of features is + // disabled. + AliasPatternCond_K_EndOrFeatures, // Note end of list of K_Or(Neg)?Features. + AliasPatternCond_K_Ignore, // Match any operand. + AliasPatternCond_K_Reg, // Match a specific register. + AliasPatternCond_K_TiedReg, // Match another already matched register. + AliasPatternCond_K_Imm, // Match a specific immediate. + AliasPatternCond_K_RegClass, // Match registers in a class. + AliasPatternCond_K_Custom, // Call custom matcher by index. +} CondKind; + +typedef struct PatternsForOpcode { + uint32_t Opcode; + uint16_t PatternStart; + uint16_t NumPatterns; +} PatternsForOpcode; + +typedef struct AliasPattern { + uint32_t AsmStrOffset; + uint32_t AliasCondStart; + uint8_t NumOperands; + uint8_t NumConds; +} AliasPattern; + +typedef struct AliasPatternCond { + CondKind Kind; + uint32_t Value; +} AliasPatternCond; + +static int cmp_less(const void *l, const void *r) { + return ((signed)((const PatternsForOpcode *)l)->Opcode) - + ((signed)((const PatternsForOpcode *)r)->Opcode); +} + +// Binary Search Implementation - let's use bsearch for now +static PatternsForOpcode *Binary_Search(const PatternsForOpcode *OpToPatterns, + const unsigned opcode, unsigned len) { + return bsearch((void *)&opcode, (void *)OpToPatterns, len, + sizeof(PatternsForOpcode), cmp_less); +} + +// TODO I'm not sure if this is complete, refer to lib/MC/MCInstPrinter.cpp in +// llvm-project +static bool MCInstPrinter_matchAliasCondition( + const MCInst *MI, unsigned *OpIdx, const PatternsForOpcode *OpToPatterns, + const AliasPattern *Patterns, const AliasPatternCond *Conds, + const AliasPatternCond *Cond, bool *OrPredicateResult); + +const char *MCInstPrinter_matchAliasPatterns( + const MCInst *MI, const PatternsForOpcode *OpToPatterns, + const AliasPattern *Patterns, const AliasPatternCond *Conds, + const char *AsmStrings[], unsigned len); + +#endif // CAPSTONE_MCINSTPRINTER_H diff --git a/Makefile b/Makefile index ff84faa51c..e242a2e17a 100644 --- a/Makefile +++ b/Makefile @@ -305,7 +305,7 @@ endif LIBOBJ = -LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o +LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInstPrinter.o LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF) LIBOBJ += $(OBJDIR)/MCInst.o diff --git a/MathExtras.h b/MathExtras.h index e9f18689ba..e463d64c3e 100644 --- a/MathExtras.h +++ b/MathExtras.h @@ -35,18 +35,18 @@ /// Hi_32 - This function returns the high 32 bits of a 64 bit value. static inline uint32_t Hi_32(uint64_t Value) { - return (uint32_t)(Value >> 32); + return (uint32_t) (Value >> 32); } /// Lo_32 - This function returns the low 32 bits of a 64 bit value. static inline uint32_t Lo_32(uint64_t Value) { - return (uint32_t)(Value); + return (uint32_t) (Value); } /// isUIntN - Checks if an unsigned integer fits into the given (dynamic) /// bit width. static inline bool isUIntN(unsigned N, uint64_t x) { - return x == (x & (~0ULL >> (64 - N))); + return x == (x & (~0ULL >> (64 - N))); } /// isIntN - Checks if an signed integer fits into the given (dynamic) @@ -59,33 +59,33 @@ static inline bool isUIntN(unsigned N, uint64_t x) { /// starting at the least significant bit with the remainder zero (32 bit /// version). Ex. isMask_32(0x0000FFFFU) == true. static inline bool isMask_32(uint32_t Value) { - return Value && ((Value + 1) & Value) == 0; + return Value && ((Value + 1) & Value) == 0; } /// isMask_64 - This function returns true if the argument is a sequence of ones /// starting at the least significant bit with the remainder zero (64 bit /// version). static inline bool isMask_64(uint64_t Value) { - return Value && ((Value + 1) & Value) == 0; + return Value && ((Value + 1) & Value) == 0; } /// isShiftedMask_32 - This function returns true if the argument contains a /// sequence of ones with the remainder zero (32 bit version.) /// Ex. isShiftedMask_32(0x0000FF00U) == true. static inline bool isShiftedMask_32(uint32_t Value) { - return isMask_32((Value - 1) | Value); + return isMask_32((Value - 1) | Value); } /// isShiftedMask_64 - This function returns true if the argument contains a /// sequence of ones with the remainder zero (64 bit version.) static inline bool isShiftedMask_64(uint64_t Value) { - return isMask_64((Value - 1) | Value); + return isMask_64((Value - 1) | Value); } /// isPowerOf2_32 - This function returns true if the argument is a power of /// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.) static inline bool isPowerOf2_32(uint32_t Value) { - return Value && !(Value & (Value - 1)); + return Value && !(Value & (Value - 1)); } /// CountLeadingZeros_32 - this function performs the platform optimal form of @@ -93,28 +93,28 @@ static inline bool isPowerOf2_32(uint32_t Value) { /// bit. Ex. CountLeadingZeros_32(0x00F000FF) == 8. /// Returns 32 if the word is zero. static inline unsigned CountLeadingZeros_32(uint32_t Value) { - unsigned Count; // result + unsigned Count; // result #if __GNUC__ >= 4 - // PowerPC is defined for __builtin_clz(0) + // PowerPC is defined for __builtin_clz(0) #if !defined(__ppc__) && !defined(__ppc64__) - if (!Value) return 32; + if (!Value) return 32; #endif - Count = __builtin_clz(Value); + Count = __builtin_clz(Value); #else - unsigned Shift; - if (!Value) return 32; - Count = 0; - // bisection method for count leading zeros - for (Shift = 32 >> 1; Shift; Shift >>= 1) { - uint32_t Tmp = Value >> Shift; - if (Tmp) { - Value = Tmp; - } else { - Count |= Shift; - } - } + unsigned Shift; + if (!Value) return 32; + Count = 0; + // bisection method for count leading zeros + for (Shift = 32 >> 1; Shift; Shift >>= 1) { + uint32_t Tmp = Value >> Shift; + if (Tmp) { + Value = Tmp; + } else { + Count |= Shift; + } + } #endif - return Count; + return Count; } /// CountLeadingOnes_32 - this function performs the operation of @@ -122,7 +122,7 @@ static inline unsigned CountLeadingZeros_32(uint32_t Value) { /// bit. Ex. CountLeadingOnes_32(0xFF0FFF00) == 8. /// Returns 32 if the word is all ones. static inline unsigned CountLeadingOnes_32(uint32_t Value) { - return CountLeadingZeros_32(~Value); + return CountLeadingZeros_32(~Value); } /// CountLeadingZeros_64 - This function performs the platform optimal form @@ -130,49 +130,49 @@ static inline unsigned CountLeadingOnes_32(uint32_t Value) { /// one bit (64 bit edition.) /// Returns 64 if the word is zero. static inline unsigned CountLeadingZeros_64(uint64_t Value) { - unsigned Count; // result + unsigned Count; // result #if __GNUC__ >= 4 - // PowerPC is defined for __builtin_clzll(0) + // PowerPC is defined for __builtin_clzll(0) #if !defined(__ppc__) && !defined(__ppc64__) - if (!Value) return 64; + if (!Value) return 64; #endif - Count = __builtin_clzll(Value); + Count = __builtin_clzll(Value); #else #ifndef _MSC_VER - unsigned Shift; - if (sizeof(long) == sizeof(int64_t)) - { - if (!Value) return 64; - Count = 0; - // bisection method for count leading zeros - for (Shift = 64 >> 1; Shift; Shift >>= 1) { - uint64_t Tmp = Value >> Shift; - if (Tmp) { - Value = Tmp; - } else { - Count |= Shift; - } - } - } - else + unsigned Shift; + if (sizeof(long) == sizeof(int64_t)) + { + if (!Value) return 64; + Count = 0; + // bisection method for count leading zeros + for (Shift = 64 >> 1; Shift; Shift >>= 1) { + uint64_t Tmp = Value >> Shift; + if (Tmp) { + Value = Tmp; + } else { + Count |= Shift; + } + } + } + else #endif - { - // get hi portion - uint32_t Hi = Hi_32(Value); - - // if some bits in hi portion - if (Hi) { - // leading zeros in hi portion plus all bits in lo portion - Count = CountLeadingZeros_32(Hi); - } else { - // get lo portion - uint32_t Lo = Lo_32(Value); - // same as 32 bit value - Count = CountLeadingZeros_32(Lo)+32; - } - } + { + // get hi portion + uint32_t Hi = Hi_32(Value); + + // if some bits in hi portion + if (Hi) { + // leading zeros in hi portion plus all bits in lo portion + Count = CountLeadingZeros_32(Hi); + } else { + // get lo portion + uint32_t Lo = Lo_32(Value); + // same as 32 bit value + Count = CountLeadingZeros_32(Lo)+32; + } + } #endif - return Count; + return Count; } /// CountLeadingOnes_64 - This function performs the operation @@ -180,7 +180,7 @@ static inline unsigned CountLeadingZeros_64(uint64_t Value) { /// zero bit (64 bit edition.) /// Returns 64 if the word is all ones. static inline unsigned CountLeadingOnes_64(uint64_t Value) { - return CountLeadingZeros_64(~Value); + return CountLeadingZeros_64(~Value); } /// CountTrailingZeros_32 - this function performs the platform optimal form of @@ -189,17 +189,17 @@ static inline unsigned CountLeadingOnes_64(uint64_t Value) { /// Returns 32 if the word is zero. static inline unsigned CountTrailingZeros_32(uint32_t Value) { #if __GNUC__ >= 4 - return Value ? __builtin_ctz(Value) : 32; + return Value ? __builtin_ctz(Value) : 32; #else - static const unsigned Mod37BitPosition[] = { - 32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, - 4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, - 5, 20, 8, 19, 18 - }; - // Replace "-Value" by "1+~Value" in the following commented code to avoid - // MSVC warning C4146 - // return Mod37BitPosition[(-Value & Value) % 37]; - return Mod37BitPosition[((1 + ~Value) & Value) % 37]; + static const unsigned Mod37BitPosition[] = { + 32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, + 4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, + 5, 20, 8, 19, 18 + }; + // Replace "-Value" by "1+~Value" in the following commented code to avoid + // MSVC warning C4146 + // return Mod37BitPosition[(-Value & Value) % 37]; + return Mod37BitPosition[((1 + ~Value) & Value) % 37]; #endif } @@ -208,7 +208,7 @@ static inline unsigned CountTrailingZeros_32(uint32_t Value) { /// bit. Ex. CountTrailingOnes_32(0x00FF00FF) == 8. /// Returns 32 if the word is all ones. static inline unsigned CountTrailingOnes_32(uint32_t Value) { - return CountTrailingZeros_32(~Value); + return CountTrailingZeros_32(~Value); } /// CountTrailingZeros_64 - This function performs the platform optimal form @@ -217,19 +217,19 @@ static inline unsigned CountTrailingOnes_32(uint32_t Value) { /// Returns 64 if the word is zero. static inline unsigned CountTrailingZeros_64(uint64_t Value) { #if __GNUC__ >= 4 - return Value ? __builtin_ctzll(Value) : 64; + return Value ? __builtin_ctzll(Value) : 64; #else - static const unsigned Mod67Position[] = { - 64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54, - 4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55, - 47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27, - 29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56, - 7, 48, 35, 6, 34, 33, 0 - }; - // Replace "-Value" by "1+~Value" in the following commented code to avoid - // MSVC warning C4146 - // return Mod67Position[(-Value & Value) % 67]; - return Mod67Position[((1 + ~Value) & Value) % 67]; + static const unsigned Mod67Position[] = { + 64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54, + 4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55, + 47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27, + 29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56, + 7, 48, 35, 6, 34, 33, 0 + }; + // Replace "-Value" by "1+~Value" in the following commented code to avoid + // MSVC warning C4146 + // return Mod67Position[(-Value & Value) % 67]; + return Mod67Position[((1 + ~Value) & Value) % 67]; #endif } @@ -238,7 +238,7 @@ static inline unsigned CountTrailingZeros_64(uint64_t Value) { /// zero bit (64 bit edition.) /// Returns 64 if the word is all ones. static inline unsigned CountTrailingOnes_64(uint64_t Value) { - return CountTrailingZeros_64(~Value); + return CountTrailingZeros_64(~Value); } /// CountPopulation_32 - this function counts the number of set bits in a value. @@ -246,11 +246,11 @@ static inline unsigned CountTrailingOnes_64(uint64_t Value) { /// Returns 0 if the word is zero. static inline unsigned CountPopulation_32(uint32_t Value) { #if __GNUC__ >= 4 - return __builtin_popcount(Value); + return __builtin_popcount(Value); #else - uint32_t v = Value - ((Value >> 1) & 0x55555555); - v = (v & 0x33333333) + ((v >> 2) & 0x33333333); - return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24; + uint32_t v = Value - ((Value >> 1) & 0x55555555); + v = (v & 0x33333333) + ((v >> 2) & 0x33333333); + return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24; #endif } @@ -258,12 +258,12 @@ static inline unsigned CountPopulation_32(uint32_t Value) { /// (64 bit edition.) static inline unsigned CountPopulation_64(uint64_t Value) { #if __GNUC__ >= 4 - return __builtin_popcountll(Value); + return __builtin_popcountll(Value); #else - uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL); - v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL); - v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL; - return (uint64_t)((v * 0x0101010101010101ULL) >> 56); + uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL); + v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL); + v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL; + return (uint64_t)((v * 0x0101010101010101ULL) >> 56); #endif } @@ -271,59 +271,59 @@ static inline unsigned CountPopulation_64(uint64_t Value) { /// -1 if the value is zero. (32 bit edition.) /// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2 static inline unsigned Log2_32(uint32_t Value) { - return 31 - CountLeadingZeros_32(Value); + return 31 - CountLeadingZeros_32(Value); } /// Log2_64 - This function returns the floor log base 2 of the specified value, /// -1 if the value is zero. (64 bit edition.) static inline unsigned Log2_64(uint64_t Value) { - return 63 - CountLeadingZeros_64(Value); + return 63 - CountLeadingZeros_64(Value); } /// Log2_32_Ceil - This function returns the ceil log base 2 of the specified /// value, 32 if the value is zero. (32 bit edition). /// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3 static inline unsigned Log2_32_Ceil(uint32_t Value) { - return 32-CountLeadingZeros_32(Value-1); + return 32 - CountLeadingZeros_32(Value - 1); } /// Log2_64_Ceil - This function returns the ceil log base 2 of the specified /// value, 64 if the value is zero. (64 bit edition.) static inline unsigned Log2_64_Ceil(uint64_t Value) { - return 64-CountLeadingZeros_64(Value-1); + return 64 - CountLeadingZeros_64(Value - 1); } /// GreatestCommonDivisor64 - Return the greatest common divisor of the two /// values using Euclid's algorithm. static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) { - while (B) { - uint64_t T = B; - B = A % B; - A = T; - } - return A; + while (B) { + uint64_t T = B; + B = A % B; + A = T; + } + return A; } /// BitsToDouble - This function takes a 64-bit integer and returns the bit /// equivalent double. static inline double BitsToDouble(uint64_t Bits) { - union { - uint64_t L; - double D; - } T; - T.L = Bits; - return T.D; + union { + uint64_t L; + double D; + } T; + T.L = Bits; + return T.D; } /// BitsToFloat - This function takes a 32-bit integer and returns the bit /// equivalent float. static inline float BitsToFloat(uint32_t Bits) { - union { - uint32_t I; - float F; - } T; - T.I = Bits; - return T.F; + union { + uint32_t I; + float F; + } T; + T.I = Bits; + return T.F; } /// DoubleToBits - This function takes a double and returns the bit @@ -331,12 +331,12 @@ static inline float BitsToFloat(uint32_t Bits) { /// changes the bits of NaNs on some hosts, notably x86, so this /// routine cannot be used if these bits are needed. static inline uint64_t DoubleToBits(double Double) { - union { - uint64_t L; - double D; - } T; - T.D = Double; - return T.L; + union { + uint64_t L; + double D; + } T; + T.D = Double; + return T.L; } /// FloatToBits - This function takes a float and returns the bit @@ -344,35 +344,35 @@ static inline uint64_t DoubleToBits(double Double) { /// changes the bits of NaNs on some hosts, notably x86, so this /// routine cannot be used if these bits are needed. static inline uint32_t FloatToBits(float Float) { - union { - uint32_t I; - float F; - } T; - T.F = Float; - return T.I; + union { + uint32_t I; + float F; + } T; + T.F = Float; + return T.I; } /// MinAlign - A and B are either alignments or offsets. Return the minimum /// alignment that may be assumed after adding the two together. static inline uint64_t MinAlign(uint64_t A, uint64_t B) { - // The largest power of 2 that divides both A and B. - // - // Replace "-Value" by "1+~Value" in the following commented code to avoid - // MSVC warning C4146 - // return (A | B) & -(A | B); - return (A | B) & (1 + ~(A | B)); + // The largest power of 2 that divides both A and B. + // + // Replace "-Value" by "1+~Value" in the following commented code to avoid + // MSVC warning C4146 + // return (A | B) & -(A | B); + return (A | B) & (1 + ~(A | B)); } /// NextPowerOf2 - Returns the next power of two (in 64-bits) /// that is strictly greater than A. Returns zero on overflow. static inline uint64_t NextPowerOf2(uint64_t A) { - A |= (A >> 1); - A |= (A >> 2); - A |= (A >> 4); - A |= (A >> 8); - A |= (A >> 16); - A |= (A >> 32); - return A + 1; + A |= (A >> 1); + A |= (A >> 2); + A |= (A >> 4); + A |= (A >> 8); + A |= (A >> 16); + A |= (A >> 32); + return A + 1; } /// Returns the next integer (mod 2**64) that is greater than or equal to @@ -385,33 +385,33 @@ static inline uint64_t NextPowerOf2(uint64_t A) { /// RoundUpToAlignment(~0LL, 8) = 0 /// \endcode static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) { - return ((Value + Align - 1) / Align) * Align; + return ((Value + Align - 1) / Align) * Align; } /// Returns the offset to the next integer (mod 2**64) that is greater than /// or equal to \p Value and is a multiple of \p Align. \p Align must be /// non-zero. static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) { - return RoundUpToAlignment(Value, Align) - Value; + return RoundUpToAlignment(Value, Align) - Value; } /// abs64 - absolute value of a 64-bit int. Not all environments support /// "abs" on whatever their name for the 64-bit int type is. The absolute /// value of the largest negative number is undefined, as with "abs". static inline int64_t abs64(int64_t x) { - return (x < 0) ? -x : x; + return (x < 0) ? -x : x; } /// \brief Sign extend number in the bottom B bits of X to a 32-bit int. /// Requires 0 < B <= 32. static inline int32_t SignExtend32(uint32_t X, unsigned B) { - return (int32_t)(X << (32 - B)) >> (32 - B); + return (int32_t) (X << (32 - B)) >> (32 - B); } /// \brief Sign extend number in the bottom B bits of X to a 64-bit int. /// Requires 0 < B <= 64. static inline int64_t SignExtend64(uint64_t X, unsigned B) { - return (int64_t)(X << (64 - B)) >> (64 - B); + return (int64_t) (X << (64 - B)) >> (64 - B); } /// \brief Count number of 0's from the most significant bit to the least @@ -421,22 +421,40 @@ static inline int64_t SignExtend64(uint64_t X, unsigned B) { /// /// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are /// valid arguments. -static inline unsigned int countLeadingZeros(int x) -{ - int i; - const unsigned bits = sizeof(x) * 8; - unsigned count = bits; - - if (x < 0) { - return 0; - } - for (i = bits; --i; ) { - if (x == 0) break; - count--; - x >>= 1; - } - - return count; +static inline unsigned int countLeadingZeros(int x) { + int i; + const unsigned bits = sizeof(x) * 8; + unsigned count = bits; + + if (x < 0) { + return 0; + } + for (i = bits; --i;) { + if (x == 0) break; + count--; + x >>= 1; + } + + return count; +} + +static inline unsigned int countTrailingZeros(int x) { + int i; + const unsigned bits = sizeof(x) * 8 - 1; + unsigned count = 0; + + if (x < 0) { + return 0; + } + for (i = bits; --i;) { + if (x % 2 == 0) count++; + else break; + } + + // considering it is signed integer + if (count == bits - 1 && x > 0) count++; + + return count; } #endif diff --git a/arch/AArch64/AArch64AddressingModes.h b/arch/AArch64/AArch64AddressingModes.h index 946b460731..6ff0c84abc 100644 --- a/arch/AArch64/AArch64AddressingModes.h +++ b/arch/AArch64/AArch64AddressingModes.h @@ -25,79 +25,107 @@ // Shifts // typedef enum AArch64_AM_ShiftExtendType { - AArch64_AM_InvalidShiftExtend = -1, - AArch64_AM_LSL = 0, - AArch64_AM_LSR, - AArch64_AM_ASR, - AArch64_AM_ROR, - AArch64_AM_MSL, - - AArch64_AM_UXTB, - AArch64_AM_UXTH, - AArch64_AM_UXTW, - AArch64_AM_UXTX, - - AArch64_AM_SXTB, - AArch64_AM_SXTH, - AArch64_AM_SXTW, - AArch64_AM_SXTX, + AArch64_AM_InvalidShiftExtend = -1, + AArch64_AM_LSL = 0, + AArch64_AM_LSR, + AArch64_AM_ASR, + AArch64_AM_ROR, + AArch64_AM_MSL, + + AArch64_AM_UXTB, + AArch64_AM_UXTH, + AArch64_AM_UXTW, + AArch64_AM_UXTX, + + AArch64_AM_SXTB, + AArch64_AM_SXTH, + AArch64_AM_SXTW, + AArch64_AM_SXTX, } AArch64_AM_ShiftExtendType; /// getShiftName - Get the string encoding for the shift type. -static inline const char *AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST) -{ - switch (ST) { - default: return NULL; // never reach - case AArch64_AM_LSL: return "lsl"; - case AArch64_AM_LSR: return "lsr"; - case AArch64_AM_ASR: return "asr"; - case AArch64_AM_ROR: return "ror"; - case AArch64_AM_MSL: return "msl"; - case AArch64_AM_UXTB: return "uxtb"; - case AArch64_AM_UXTH: return "uxth"; - case AArch64_AM_UXTW: return "uxtw"; - case AArch64_AM_UXTX: return "uxtx"; - case AArch64_AM_SXTB: return "sxtb"; - case AArch64_AM_SXTH: return "sxth"; - case AArch64_AM_SXTW: return "sxtw"; - case AArch64_AM_SXTX: return "sxtx"; - } +static inline const char * +AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST) { + switch (ST) { + default: + return NULL; // never reach + case AArch64_AM_LSL: + return "lsl"; + case AArch64_AM_LSR: + return "lsr"; + case AArch64_AM_ASR: + return "asr"; + case AArch64_AM_ROR: + return "ror"; + case AArch64_AM_MSL: + return "msl"; + case AArch64_AM_UXTB: + return "uxtb"; + case AArch64_AM_UXTH: + return "uxth"; + case AArch64_AM_UXTW: + return "uxtw"; + case AArch64_AM_UXTX: + return "uxtx"; + case AArch64_AM_SXTB: + return "sxtb"; + case AArch64_AM_SXTH: + return "sxth"; + case AArch64_AM_SXTW: + return "sxtw"; + case AArch64_AM_SXTX: + return "sxtx"; + } } /// getShiftType - Extract the shift type. -static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm) -{ - switch ((Imm >> 6) & 0x7) { - default: return AArch64_AM_InvalidShiftExtend; - case 0: return AArch64_AM_LSL; - case 1: return AArch64_AM_LSR; - case 2: return AArch64_AM_ASR; - case 3: return AArch64_AM_ROR; - case 4: return AArch64_AM_MSL; - } +static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm) { + switch ((Imm >> 6) & 0x7) { + default: + return AArch64_AM_InvalidShiftExtend; + case 0: + return AArch64_AM_LSL; + case 1: + return AArch64_AM_LSR; + case 2: + return AArch64_AM_ASR; + case 3: + return AArch64_AM_ROR; + case 4: + return AArch64_AM_MSL; + } } /// getShiftValue - Extract the shift value. -static inline unsigned AArch64_AM_getShiftValue(unsigned Imm) -{ - return Imm & 0x3f; -} - -static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, unsigned Imm) -{ - // assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); - unsigned STEnc = 0; - - switch (ST) { - default: // llvm_unreachable("Invalid shift requested"); - case AArch64_AM_LSL: STEnc = 0; break; - case AArch64_AM_LSR: STEnc = 1; break; - case AArch64_AM_ASR: STEnc = 2; break; - case AArch64_AM_ROR: STEnc = 3; break; - case AArch64_AM_MSL: STEnc = 4; break; - } - - return (STEnc << 6) | (Imm & 0x3f); +static inline unsigned AArch64_AM_getShiftValue(unsigned Imm) { + return Imm & 0x3f; +} + +static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, + unsigned Imm) { + // assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); + unsigned STEnc = 0; + + switch (ST) { + default: // llvm_unreachable("Invalid shift requested"); + case AArch64_AM_LSL: + STEnc = 0; + break; + case AArch64_AM_LSR: + STEnc = 1; + break; + case AArch64_AM_ASR: + STEnc = 2; + break; + case AArch64_AM_ROR: + STEnc = 3; + break; + case AArch64_AM_MSL: + STEnc = 4; + break; + } + + return (STEnc << 6) | (Imm & 0x3f); } //===----------------------------------------------------------------------===// @@ -105,31 +133,38 @@ static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, u // /// getArithShiftValue - get the arithmetic shift value. -static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm) -{ - return Imm & 0x7; +static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm) { + return Imm & 0x7; } /// getExtendType - Extract the extend type for operands of arithmetic ops. -static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm) -{ - // assert((Imm & 0x7) == Imm && "invalid immediate!"); - switch (Imm) { - default: // llvm_unreachable("Compiler bug!"); - case 0: return AArch64_AM_UXTB; - case 1: return AArch64_AM_UXTH; - case 2: return AArch64_AM_UXTW; - case 3: return AArch64_AM_UXTX; - case 4: return AArch64_AM_SXTB; - case 5: return AArch64_AM_SXTH; - case 6: return AArch64_AM_SXTW; - case 7: return AArch64_AM_SXTX; - } -} - -static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm) -{ - return AArch64_AM_getExtendType((Imm >> 3) & 0x7); +static inline AArch64_AM_ShiftExtendType +AArch64_AM_getExtendType(unsigned Imm) { + // assert((Imm & 0x7) == Imm && "invalid immediate!"); + switch (Imm) { + default: // llvm_unreachable("Compiler bug!"); + case 0: + return AArch64_AM_UXTB; + case 1: + return AArch64_AM_UXTH; + case 2: + return AArch64_AM_UXTW; + case 3: + return AArch64_AM_UXTX; + case 4: + return AArch64_AM_SXTB; + case 5: + return AArch64_AM_SXTH; + case 6: + return AArch64_AM_SXTW; + case 7: + return AArch64_AM_SXTX; + } +} + +static inline AArch64_AM_ShiftExtendType +AArch64_AM_getArithExtendType(unsigned Imm) { + return AArch64_AM_getExtendType((Imm >> 3) & 0x7); } /// Mapping from extend bits to required operation: @@ -141,19 +176,35 @@ static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned /// 101 ==> sxth /// 110 ==> sxtw /// 111 ==> sxtx -static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET) -{ - switch (ET) { - default: // llvm_unreachable("Invalid extend type requested"); - case AArch64_AM_UXTB: return 0; break; - case AArch64_AM_UXTH: return 1; break; - case AArch64_AM_UXTW: return 2; break; - case AArch64_AM_UXTX: return 3; break; - case AArch64_AM_SXTB: return 4; break; - case AArch64_AM_SXTH: return 5; break; - case AArch64_AM_SXTW: return 6; break; - case AArch64_AM_SXTX: return 7; break; - } +static inline unsigned +AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET) { + switch (ET) { + default: // llvm_unreachable("Invalid extend type requested"); + case AArch64_AM_UXTB: + return 0; + break; + case AArch64_AM_UXTH: + return 1; + break; + case AArch64_AM_UXTW: + return 2; + break; + case AArch64_AM_UXTX: + return 3; + break; + case AArch64_AM_SXTB: + return 4; + break; + case AArch64_AM_SXTH: + return 5; + break; + case AArch64_AM_SXTW: + return 6; + break; + case AArch64_AM_SXTX: + return 7; + break; + } } /// getArithExtendImm - Encode the extend type and shift amount for an @@ -161,209 +212,208 @@ static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType E /// imm: 3-bit extend amount /// {5-3} = shifter /// {2-0} = imm3 -static inline unsigned AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm) -{ - // assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!"); - return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7); +static inline unsigned +AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm) { + // assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!"); + return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7); } /// getMemDoShift - Extract the "do shift" flag value for load/store /// instructions. -static inline bool AArch64_AM_getMemDoShift(unsigned Imm) -{ - return (Imm & 0x1) != 0; +static inline bool AArch64_AM_getMemDoShift(unsigned Imm) { + return (Imm & 0x1) != 0; } /// getExtendType - Extract the extend type for the offset operand of /// loads/stores. -static inline AArch64_AM_ShiftExtendType AArch64_AM_getMemExtendType(unsigned Imm) -{ - return AArch64_AM_getExtendType((Imm >> 1) & 0x7); +static inline AArch64_AM_ShiftExtendType +AArch64_AM_getMemExtendType(unsigned Imm) { + return AArch64_AM_getExtendType((Imm >> 1) & 0x7); } -static inline uint64_t ror(uint64_t elt, unsigned size) -{ - return ((elt & 1) << (size-1)) | (elt >> 1); +static inline uint64_t ror(uint64_t elt, unsigned size) { + return ((elt & 1) << (size - 1)) | (elt >> 1); } /// processLogicalImmediate - Determine if an immediate value can be encoded /// as the immediate operand of a logical instruction for the given register /// size. If so, return true with "encoding" set to the encoded value in /// the form N:immr:imms. -static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t *Encoding) -{ - unsigned Size, Immr, N; - uint32_t CTO, I; - uint64_t Mask, NImms; - - if (Imm == 0ULL || Imm == ~0ULL || - (RegSize != 64 && (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) { - return false; - } - - // First, determine the element size. - Size = RegSize; - do { - uint64_t Mask; - - Size /= 2; - Mask = (1ULL << Size) - 1; - if ((Imm & Mask) != ((Imm >> Size) & Mask)) { - Size *= 2; - break; - } - } while (Size > 2); - - // Second, determine the rotation to make the element be: 0^m 1^n. - Mask = ((uint64_t)-1LL) >> (64 - Size); - Imm &= Mask; - - if (isShiftedMask_64(Imm)) { - I = CountTrailingZeros_32(Imm); - // assert(I < 64 && "undefined behavior"); - CTO = CountTrailingOnes_32(Imm >> I); - } else { - unsigned CLO; - - Imm |= ~Mask; - if (!isShiftedMask_64(~Imm)) - return false; - - CLO = CountLeadingOnes_32(Imm); - I = 64 - CLO; - CTO = CLO + CountTrailingOnes_32(Imm) - (64 - Size); - } - - // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n - // to our target value, where I is the number of RORs to go the opposite - // direction. - // assert(Size > I && "I should be smaller than element size"); - Immr = (Size - I) & (Size - 1); - - // If size has a 1 in the n'th bit, create a value that has zeroes in - // bits [0, n] and ones above that. - NImms = ~(Size-1) << 1; - - // Or the CTO value into the low bits, which must be below the Nth bit - // bit mentioned above. - NImms |= (CTO-1); - - // Extract the seventh bit and toggle it to create the N field. - N = ((NImms >> 6) & 1) ^ 1; - - *Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f); - - return true; +static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, + unsigned RegSize, + uint64_t *Encoding) { + unsigned Size, Immr, N; + uint32_t CTO, I; + uint64_t Mask, NImms; + + if (Imm == 0ULL || Imm == ~0ULL || + (RegSize != 64 && + (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) { + return false; + } + + // First, determine the element size. + Size = RegSize; + do { + uint64_t Mask; + + Size /= 2; + Mask = (1ULL << Size) - 1; + if ((Imm & Mask) != ((Imm >> Size) & Mask)) { + Size *= 2; + break; + } + } while (Size > 2); + + // Second, determine the rotation to make the element be: 0^m 1^n. + Mask = ((uint64_t)-1LL) >> (64 - Size); + Imm &= Mask; + + if (isShiftedMask_64(Imm)) { + I = CountTrailingZeros_32(Imm); + // assert(I < 64 && "undefined behavior"); + CTO = CountTrailingOnes_32(Imm >> I); + } else { + unsigned CLO; + + Imm |= ~Mask; + if (!isShiftedMask_64(~Imm)) + return false; + + CLO = CountLeadingOnes_32(Imm); + I = 64 - CLO; + CTO = CLO + CountTrailingOnes_32(Imm) - (64 - Size); + } + + // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n + // to our target value, where I is the number of RORs to go the opposite + // direction. + // assert(Size > I && "I should be smaller than element size"); + Immr = (Size - I) & (Size - 1); + + // If size has a 1 in the n'th bit, create a value that has zeroes in + // bits [0, n] and ones above that. + NImms = ~(Size - 1) << 1; + + // Or the CTO value into the low bits, which must be below the Nth bit + // bit mentioned above. + NImms |= (CTO - 1); + + // Extract the seventh bit and toggle it to create the N field. + N = ((NImms >> 6) & 1) ^ 1; + + *Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f); + + return true; } /// isLogicalImmediate - Return true if the immediate is valid for a logical /// immediate instruction of the given register size. Return false otherwise. -static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) -{ - uint64_t encoding; - return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); +static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) { + uint64_t encoding; + return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); } /// encodeLogicalImmediate - Return the encoded immediate value for a logical /// immediate instruction of the given register size. -static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm, unsigned regSize) -{ - uint64_t encoding = 0; +static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm, + unsigned regSize) { + uint64_t encoding = 0; - bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); - // assert(res && "invalid logical immediate"); - (void)res; + bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); + // assert(res && "invalid logical immediate"); + (void)res; - return encoding; + return encoding; } /// decodeLogicalImmediate - Decode a logical immediate value in the form /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the /// integer value it represents with regSize bits. -static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned regSize) -{ - // Extract the N, imms, and immr fields. - unsigned N = (val >> 12) & 1; - unsigned immr = (val >> 6) & 0x3f; - unsigned imms = val & 0x3f; - unsigned i, size, R, S; - uint64_t pattern; +static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, + unsigned regSize) { + // Extract the N, imms, and immr fields. + unsigned N = (val >> 12) & 1; + unsigned immr = (val >> 6) & 0x3f; + unsigned imms = val & 0x3f; + unsigned i, size, R, S; + uint64_t pattern; - // assert((regSize == 64 || N == 0) && "undefined logical immediate encoding"); - int len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f)); + // assert((regSize == 64 || N == 0) && "undefined logical immediate + // encoding"); + int len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f)); - // assert(len >= 0 && "undefined logical immediate encoding"); - size = (1 << len); - R = immr & (size - 1); - S = imms & (size - 1); + // assert(len >= 0 && "undefined logical immediate encoding"); + size = (1 << len); + R = immr & (size - 1); + S = imms & (size - 1); - // assert(S != size - 1 && "undefined logical immediate encoding"); - pattern = (1ULL << (S + 1)) - 1; + // assert(S != size - 1 && "undefined logical immediate encoding"); + pattern = (1ULL << (S + 1)) - 1; - for (i = 0; i < R; ++i) - pattern = ror(pattern, size); + for (i = 0; i < R; ++i) + pattern = ror(pattern, size); - // Replicate the pattern to fill the regSize. - while (size != regSize) { - pattern |= (pattern << size); - size *= 2; - } + // Replicate the pattern to fill the regSize. + while (size != regSize) { + pattern |= (pattern << size); + size *= 2; + } - return pattern; + return pattern; } /// isValidDecodeLogicalImmediate - Check to see if the logical immediate value /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) /// is a valid encoding for an integer value with regSize bits. -static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize) -{ - unsigned size, S; - int len; - // Extract the N and imms fields needed for checking. - unsigned N = (val >> 12) & 1; - unsigned imms = val & 0x3f; - - if (regSize == 32 && N != 0) // undefined logical immediate encoding - return false; - len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f)); - if (len < 0) // undefined logical immediate encoding - return false; - size = (1 << len); - S = imms & (size - 1); - if (S == size - 1) // undefined logical immediate encoding - return false; - - return true; +static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, + unsigned regSize) { + unsigned size, S; + int len; + // Extract the N and imms fields needed for checking. + unsigned N = (val >> 12) & 1; + unsigned imms = val & 0x3f; + + if (regSize == 32 && N != 0) // undefined logical immediate encoding + return false; + len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f)); + if (len < 0) // undefined logical immediate encoding + return false; + size = (1 << len); + S = imms & (size - 1); + if (S == size - 1) // undefined logical immediate encoding + return false; + + return true; } //===----------------------------------------------------------------------===// // Floating-point Immediates // -static inline float AArch64_AM_getFPImmFloat(unsigned Imm) -{ - // We expect an 8-bit binary encoding of a floating-point number here. - union { - uint32_t I; - float F; - } FPUnion; +static inline float AArch64_AM_getFPImmFloat(unsigned Imm) { + // We expect an 8-bit binary encoding of a floating-point number here. + union { + uint32_t I; + float F; + } FPUnion; - uint8_t Sign = (Imm >> 7) & 0x1; - uint8_t Exp = (Imm >> 4) & 0x7; - uint8_t Mantissa = Imm & 0xf; + uint8_t Sign = (Imm >> 7) & 0x1; + uint8_t Exp = (Imm >> 4) & 0x7; + uint8_t Mantissa = Imm & 0xf; - // 8-bit FP iEEEE Float Encoding - // abcd efgh aBbbbbbc defgh000 00000000 00000000 - // - // where B = NOT(b); + // 8-bit FP iEEEE Float Encoding + // abcd efgh aBbbbbbc defgh000 00000000 00000000 + // + // where B = NOT(b); - FPUnion.I = 0; - FPUnion.I |= ((uint32_t)Sign) << 31; - FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; - FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; - FPUnion.I |= (Exp & 0x3) << 23; - FPUnion.I |= Mantissa << 19; + FPUnion.I = 0; + FPUnion.I |= ((uint32_t)Sign) << 31; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; + FPUnion.I |= (Exp & 0x3) << 23; + FPUnion.I |= Mantissa << 19; - return FPUnion.F; + return FPUnion.F; } //===--------------------------------------------------------------------===// @@ -371,575 +421,525 @@ static inline float AArch64_AM_getFPImmFloat(unsigned Imm) //===--------------------------------------------------------------------===// // 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh -static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm) -{ - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xffffff00ffffff00ULL) == 0); +static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm) { + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + ((Imm & 0xffffff00ffffff00ULL) == 0); } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm) -{ - return (Imm & 0xffULL); +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm) { + return (Imm & 0xffULL); } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm) -{ - uint64_t EncVal = Imm; +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm) { + uint64_t EncVal = Imm; - return (EncVal << 32) | EncVal; + return (EncVal << 32) | EncVal; } // 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 -static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm) -{ - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xffff00ffffff00ffULL) == 0); +static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm) { + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + ((Imm & 0xffff00ffffff00ffULL) == 0); } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm) -{ - return (Imm & 0xff00ULL) >> 8; +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm) { + return (Imm & 0xff00ULL) >> 8; } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm) -{ - uint64_t EncVal = Imm; - return (EncVal << 40) | (EncVal << 8); +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm) { + uint64_t EncVal = Imm; + return (EncVal << 40) | (EncVal << 8); } // 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 -static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm) -{ - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xff00ffffff00ffffULL) == 0); +static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm) { + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + ((Imm & 0xff00ffffff00ffffULL) == 0); } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm) -{ - return (Imm & 0xff0000ULL) >> 16; +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm) { + return (Imm & 0xff0000ULL) >> 16; } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm) -{ - uint64_t EncVal = Imm; - return (EncVal << 48) | (EncVal << 16); +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm) { + uint64_t EncVal = Imm; + return (EncVal << 48) | (EncVal << 16); } // abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 -static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm) -{ - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0x00ffffff00ffffffULL) == 0); +static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm) { + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + ((Imm & 0x00ffffff00ffffffULL) == 0); } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm) -{ - return (Imm & 0xff000000ULL) >> 24; +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm) { + return (Imm & 0xff000000ULL) >> 24; } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm) -{ - uint64_t EncVal = Imm; - return (EncVal << 56) | (EncVal << 24); +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm) { + uint64_t EncVal = Imm; + return (EncVal << 56) | (EncVal << 24); } // 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh -static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm) -{ - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) && - ((Imm & 0xff00ff00ff00ff00ULL) == 0); +static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm) { + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) && + ((Imm & 0xff00ff00ff00ff00ULL) == 0); } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm) -{ - return (Imm & 0xffULL); +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm) { + return (Imm & 0xffULL); } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm) -{ - uint64_t EncVal = Imm; - return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal; +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm) { + uint64_t EncVal = Imm; + return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal; } // abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 -static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm) -{ - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) && - ((Imm & 0x00ff00ff00ff00ffULL) == 0); +static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm) { + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) && + ((Imm & 0x00ff00ff00ff00ffULL) == 0); } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm) -{ - return (Imm & 0xff00ULL) >> 8; +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm) { + return (Imm & 0xff00ULL) >> 8; } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm) -{ - uint64_t EncVal = Imm; - return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8); +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm) { + uint64_t EncVal = Imm; + return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8); } // 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF -static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm) -{ - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL); +static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm) { + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL); } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm) -{ - return (Imm & 0xff00ULL) >> 8; +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm) { + return (Imm & 0xff00ULL) >> 8; } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm) -{ - uint64_t EncVal = Imm; - return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL; +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm) { + uint64_t EncVal = Imm; + return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL; } // 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF -static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm) -{ - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL); +static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm) { + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL); } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm) -{ - uint64_t EncVal = Imm; - return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL; +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm) { + uint64_t EncVal = Imm; + return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL; } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm) -{ - return (Imm & 0x00ff0000ULL) >> 16; +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm) { + return (Imm & 0x00ff0000ULL) >> 16; } // abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh -static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm) -{ - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm >> 48) == (Imm & 0x0000ffffULL)) && - ((Imm >> 56) == (Imm & 0x000000ffULL)); +static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm) { + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + ((Imm >> 48) == (Imm & 0x0000ffffULL)) && + ((Imm >> 56) == (Imm & 0x000000ffULL)); } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm) -{ - return (Imm & 0xffULL); +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm) { + return (Imm & 0xffULL); } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm) -{ - uint64_t EncVal = Imm; - EncVal |= (EncVal << 8); - EncVal |= (EncVal << 16); - EncVal |= (EncVal << 32); +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm) { + uint64_t EncVal = Imm; + EncVal |= (EncVal << 8); + EncVal |= (EncVal << 16); + EncVal |= (EncVal << 32); - return EncVal; + return EncVal; } // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh // cmode: 1110, op: 1 -static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm) -{ - uint64_t ByteA = Imm & 0xff00000000000000ULL; - uint64_t ByteB = Imm & 0x00ff000000000000ULL; - uint64_t ByteC = Imm & 0x0000ff0000000000ULL; - uint64_t ByteD = Imm & 0x000000ff00000000ULL; - uint64_t ByteE = Imm & 0x00000000ff000000ULL; - uint64_t ByteF = Imm & 0x0000000000ff0000ULL; - uint64_t ByteG = Imm & 0x000000000000ff00ULL; - uint64_t ByteH = Imm & 0x00000000000000ffULL; - - return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) && - (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) && - (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) && - (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) && - (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) && - (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) && - (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) && - (ByteH == 0ULL || ByteH == 0x00000000000000ffULL); -} - -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm) -{ - uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0; - uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0; - uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0; - uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0; - uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0; - uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0; - uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0; - uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0; - - uint8_t EncVal = BitA; - - EncVal <<= 1; - EncVal |= BitB; - EncVal <<= 1; - EncVal |= BitC; - EncVal <<= 1; - EncVal |= BitD; - EncVal <<= 1; - EncVal |= BitE; - EncVal <<= 1; - EncVal |= BitF; - EncVal <<= 1; - EncVal |= BitG; - EncVal <<= 1; - EncVal |= BitH; - - return EncVal; -} - -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm) -{ - uint64_t EncVal = 0; - - if (Imm & 0x80) - EncVal |= 0xff00000000000000ULL; - - if (Imm & 0x40) - EncVal |= 0x00ff000000000000ULL; - - if (Imm & 0x20) - EncVal |= 0x0000ff0000000000ULL; - - if (Imm & 0x10) - EncVal |= 0x000000ff00000000ULL; - - if (Imm & 0x08) - EncVal |= 0x00000000ff000000ULL; - - if (Imm & 0x04) - EncVal |= 0x0000000000ff0000ULL; - - if (Imm & 0x02) - EncVal |= 0x000000000000ff00ULL; - - if (Imm & 0x01) - EncVal |= 0x00000000000000ffULL; - - return EncVal; +static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm) { + uint64_t ByteA = Imm & 0xff00000000000000ULL; + uint64_t ByteB = Imm & 0x00ff000000000000ULL; + uint64_t ByteC = Imm & 0x0000ff0000000000ULL; + uint64_t ByteD = Imm & 0x000000ff00000000ULL; + uint64_t ByteE = Imm & 0x00000000ff000000ULL; + uint64_t ByteF = Imm & 0x0000000000ff0000ULL; + uint64_t ByteG = Imm & 0x000000000000ff00ULL; + uint64_t ByteH = Imm & 0x00000000000000ffULL; + + return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) && + (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) && + (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) && + (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) && + (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) && + (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) && + (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) && + (ByteH == 0ULL || ByteH == 0x00000000000000ffULL); +} + +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm) { + uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0; + uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0; + uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0; + uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0; + uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0; + uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0; + uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0; + uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0; + + uint8_t EncVal = BitA; + + EncVal <<= 1; + EncVal |= BitB; + EncVal <<= 1; + EncVal |= BitC; + EncVal <<= 1; + EncVal |= BitD; + EncVal <<= 1; + EncVal |= BitE; + EncVal <<= 1; + EncVal |= BitF; + EncVal <<= 1; + EncVal |= BitG; + EncVal <<= 1; + EncVal |= BitH; + + return EncVal; +} + +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm) { + uint64_t EncVal = 0; + + if (Imm & 0x80) + EncVal |= 0xff00000000000000ULL; + + if (Imm & 0x40) + EncVal |= 0x00ff000000000000ULL; + + if (Imm & 0x20) + EncVal |= 0x0000ff0000000000ULL; + + if (Imm & 0x10) + EncVal |= 0x000000ff00000000ULL; + + if (Imm & 0x08) + EncVal |= 0x00000000ff000000ULL; + + if (Imm & 0x04) + EncVal |= 0x0000000000ff0000ULL; + + if (Imm & 0x02) + EncVal |= 0x000000000000ff00ULL; + + if (Imm & 0x01) + EncVal |= 0x00000000000000ffULL; + + return EncVal; } // aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00 -static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm) -{ - uint64_t BString = (Imm & 0x7E000000ULL) >> 25; +static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm) { + uint64_t BString = (Imm & 0x7E000000ULL) >> 25; - return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - (BString == 0x1f || BString == 0x20) && - ((Imm & 0x0007ffff0007ffffULL) == 0); + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && + (BString == 0x1f || BString == 0x20) && + ((Imm & 0x0007ffff0007ffffULL) == 0); } -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm) -{ - uint8_t BitA = (Imm & 0x80000000ULL) != 0; - uint8_t BitB = (Imm & 0x20000000ULL) != 0; - uint8_t BitC = (Imm & 0x01000000ULL) != 0; - uint8_t BitD = (Imm & 0x00800000ULL) != 0; - uint8_t BitE = (Imm & 0x00400000ULL) != 0; - uint8_t BitF = (Imm & 0x00200000ULL) != 0; - uint8_t BitG = (Imm & 0x00100000ULL) != 0; - uint8_t BitH = (Imm & 0x00080000ULL) != 0; +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm) { + uint8_t BitA = (Imm & 0x80000000ULL) != 0; + uint8_t BitB = (Imm & 0x20000000ULL) != 0; + uint8_t BitC = (Imm & 0x01000000ULL) != 0; + uint8_t BitD = (Imm & 0x00800000ULL) != 0; + uint8_t BitE = (Imm & 0x00400000ULL) != 0; + uint8_t BitF = (Imm & 0x00200000ULL) != 0; + uint8_t BitG = (Imm & 0x00100000ULL) != 0; + uint8_t BitH = (Imm & 0x00080000ULL) != 0; - uint8_t EncVal = BitA; - EncVal <<= 1; - EncVal |= BitB; - EncVal <<= 1; - EncVal |= BitC; - EncVal <<= 1; - EncVal |= BitD; - EncVal <<= 1; - EncVal |= BitE; - EncVal <<= 1; - EncVal |= BitF; - EncVal <<= 1; - EncVal |= BitG; - EncVal <<= 1; - EncVal |= BitH; + uint8_t EncVal = BitA; + EncVal <<= 1; + EncVal |= BitB; + EncVal <<= 1; + EncVal |= BitC; + EncVal <<= 1; + EncVal |= BitD; + EncVal <<= 1; + EncVal |= BitE; + EncVal <<= 1; + EncVal |= BitF; + EncVal <<= 1; + EncVal |= BitG; + EncVal <<= 1; + EncVal |= BitH; - return EncVal; + return EncVal; } -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm) -{ - uint64_t EncVal = 0; +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm) { + uint64_t EncVal = 0; - if (Imm & 0x80) - EncVal |= 0x80000000ULL; + if (Imm & 0x80) + EncVal |= 0x80000000ULL; - if (Imm & 0x40) - EncVal |= 0x3e000000ULL; - else - EncVal |= 0x40000000ULL; + if (Imm & 0x40) + EncVal |= 0x3e000000ULL; + else + EncVal |= 0x40000000ULL; - if (Imm & 0x20) - EncVal |= 0x01000000ULL; + if (Imm & 0x20) + EncVal |= 0x01000000ULL; - if (Imm & 0x10) - EncVal |= 0x00800000ULL; + if (Imm & 0x10) + EncVal |= 0x00800000ULL; - if (Imm & 0x08) - EncVal |= 0x00400000ULL; + if (Imm & 0x08) + EncVal |= 0x00400000ULL; - if (Imm & 0x04) - EncVal |= 0x00200000ULL; + if (Imm & 0x04) + EncVal |= 0x00200000ULL; - if (Imm & 0x02) - EncVal |= 0x00100000ULL; + if (Imm & 0x02) + EncVal |= 0x00100000ULL; - if (Imm & 0x01) - EncVal |= 0x00080000ULL; + if (Imm & 0x01) + EncVal |= 0x00080000ULL; - return (EncVal << 32) | EncVal; + return (EncVal << 32) | EncVal; } // aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00 -static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm) -{ - uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54; - return ((BString == 0xff || BString == 0x100) && - ((Imm & 0x0000ffffffffffffULL) == 0)); -} - -static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm) -{ - uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0; - uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0; - uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0; - uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0; - uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0; - uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0; - uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0; - uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0; - - uint8_t EncVal = BitA; - EncVal <<= 1; - EncVal |= BitB; - EncVal <<= 1; - EncVal |= BitC; - EncVal <<= 1; - EncVal |= BitD; - EncVal <<= 1; - EncVal |= BitE; - EncVal <<= 1; - EncVal |= BitF; - EncVal <<= 1; - EncVal |= BitG; - EncVal <<= 1; - EncVal |= BitH; - - return EncVal; -} - -static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm) -{ - uint64_t EncVal = 0; - if (Imm & 0x80) - EncVal |= 0x8000000000000000ULL; - - if (Imm & 0x40) - EncVal |= 0x3fc0000000000000ULL; - else - EncVal |= 0x4000000000000000ULL; - - if (Imm & 0x20) - EncVal |= 0x0020000000000000ULL; - - if (Imm & 0x10) - EncVal |= 0x0010000000000000ULL; - - if (Imm & 0x08) - EncVal |= 0x0008000000000000ULL; - - if (Imm & 0x04) - EncVal |= 0x0004000000000000ULL; - - if (Imm & 0x02) - EncVal |= 0x0002000000000000ULL; - - if (Imm & 0x01) - EncVal |= 0x0001000000000000ULL; - - return (EncVal << 32) | EncVal; +static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm) { + uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54; + return ((BString == 0xff || BString == 0x100) && + ((Imm & 0x0000ffffffffffffULL) == 0)); +} + +static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm) { + uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0; + uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0; + uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0; + uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0; + uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0; + uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0; + uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0; + uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0; + + uint8_t EncVal = BitA; + EncVal <<= 1; + EncVal |= BitB; + EncVal <<= 1; + EncVal |= BitC; + EncVal <<= 1; + EncVal |= BitD; + EncVal <<= 1; + EncVal |= BitE; + EncVal <<= 1; + EncVal |= BitF; + EncVal <<= 1; + EncVal |= BitG; + EncVal <<= 1; + EncVal |= BitH; + + return EncVal; +} + +static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm) { + uint64_t EncVal = 0; + if (Imm & 0x80) + EncVal |= 0x8000000000000000ULL; + + if (Imm & 0x40) + EncVal |= 0x3fc0000000000000ULL; + else + EncVal |= 0x4000000000000000ULL; + + if (Imm & 0x20) + EncVal |= 0x0020000000000000ULL; + + if (Imm & 0x10) + EncVal |= 0x0010000000000000ULL; + + if (Imm & 0x08) + EncVal |= 0x0008000000000000ULL; + + if (Imm & 0x04) + EncVal |= 0x0004000000000000ULL; + + if (Imm & 0x02) + EncVal |= 0x0002000000000000ULL; + + if (Imm & 0x01) + EncVal |= 0x0001000000000000ULL; + + return (EncVal << 32) | EncVal; } /// Returns true if Imm is the concatenation of a repeating pattern of type T. -static inline bool AArch64_AM_isSVEMaskOfIdenticalElements8(int64_t Imm) -{ -#define _VECSIZE (sizeof(int64_t)/sizeof(int8_t)) - unsigned int i; - union { - int64_t Whole; - int8_t Parts[_VECSIZE]; - } Vec; - - Vec.Whole = Imm; - - for(i = 1; i < _VECSIZE; i++) { - if (Vec.Parts[i] != Vec.Parts[0]) - return false; - } +static inline bool AArch64_AM_isSVEMaskOfIdenticalElements8(int64_t Imm) { +#define _VECSIZE (sizeof(int64_t) / sizeof(int8_t)) + unsigned int i; + union { + int64_t Whole; + int8_t Parts[_VECSIZE]; + } Vec; + + Vec.Whole = Imm; + + for (i = 1; i < _VECSIZE; i++) { + if (Vec.Parts[i] != Vec.Parts[0]) + return false; + } #undef _VECSIZE - return true; + return true; } -static inline bool AArch64_AM_isSVEMaskOfIdenticalElements16(int64_t Imm) -{ -#define _VECSIZE (sizeof(int64_t)/sizeof(int16_t)) - unsigned int i; - union { - int64_t Whole; - int16_t Parts[_VECSIZE]; - } Vec; +static inline bool AArch64_AM_isSVEMaskOfIdenticalElements16(int64_t Imm) { +#define _VECSIZE (sizeof(int64_t) / sizeof(int16_t)) + unsigned int i; + union { + int64_t Whole; + int16_t Parts[_VECSIZE]; + } Vec; - Vec.Whole = Imm; + Vec.Whole = Imm; - for(i = 1; i < _VECSIZE; i++) { - if (Vec.Parts[i] != Vec.Parts[0]) - return false; - } + for (i = 1; i < _VECSIZE; i++) { + if (Vec.Parts[i] != Vec.Parts[0]) + return false; + } #undef _VECSIZE - return true; + return true; } -static inline bool AArch64_AM_isSVEMaskOfIdenticalElements32(int64_t Imm) -{ -#define _VECSIZE (sizeof(int64_t)/sizeof(int32_t)) - unsigned int i; - union { - int64_t Whole; - int32_t Parts[_VECSIZE]; - } Vec; +static inline bool AArch64_AM_isSVEMaskOfIdenticalElements32(int64_t Imm) { +#define _VECSIZE (sizeof(int64_t) / sizeof(int32_t)) + unsigned int i; + union { + int64_t Whole; + int32_t Parts[_VECSIZE]; + } Vec; - Vec.Whole = Imm; + Vec.Whole = Imm; - for(i = 1; i < _VECSIZE; i++) { - if (Vec.Parts[i] != Vec.Parts[0]) - return false; - } + for (i = 1; i < _VECSIZE; i++) { + if (Vec.Parts[i] != Vec.Parts[0]) + return false; + } #undef _VECSIZE - return true; + return true; } -static inline bool AArch64_AM_isSVEMaskOfIdenticalElements64(int64_t Imm) -{ - return true; +static inline bool AArch64_AM_isSVEMaskOfIdenticalElements64(int64_t Imm) { + return true; } -static inline bool isSVECpyImm8(int64_t Imm) -{ - bool IsImm8 = (int8_t)Imm == Imm; +static inline bool isSVECpyImm8(int64_t Imm) { + bool IsImm8 = (int8_t)Imm == Imm; - return IsImm8 || (uint8_t)Imm == Imm; + return IsImm8 || (uint8_t)Imm == Imm; } -static inline bool isSVECpyImm16(int64_t Imm) -{ - bool IsImm8 = (int8_t)Imm == Imm; - bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; +static inline bool isSVECpyImm16(int64_t Imm) { + bool IsImm8 = (int8_t)Imm == Imm; + bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; - return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm; + return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm; } -static inline bool isSVECpyImm32(int64_t Imm) -{ - bool IsImm8 = (int8_t)Imm == Imm; - bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; +static inline bool isSVECpyImm32(int64_t Imm) { + bool IsImm8 = (int8_t)Imm == Imm; + bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; - return IsImm8 || IsImm16; + return IsImm8 || IsImm16; } -static inline bool isSVECpyImm64(int64_t Imm) -{ - bool IsImm8 = (int8_t)Imm == Imm; - bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; +static inline bool isSVECpyImm64(int64_t Imm) { + bool IsImm8 = (int8_t)Imm == Imm; + bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; - return IsImm8 || IsImm16; + return IsImm8 || IsImm16; } /// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent. -static inline bool AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) -{ - union { - int64_t D; - int32_t S[2]; - int16_t H[4]; - int8_t B[8]; - } Vec = {Imm}; +static inline bool +AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) { + union { + int64_t D; + int32_t S[2]; + int16_t H[4]; + int8_t B[8]; + } Vec = {Imm}; - if (isSVECpyImm64(Vec.D)) - return false; + if (isSVECpyImm64(Vec.D)) + return false; - if (AArch64_AM_isSVEMaskOfIdenticalElements32(Imm) && - isSVECpyImm32(Vec.S[0])) - return false; + if (AArch64_AM_isSVEMaskOfIdenticalElements32(Imm) && isSVECpyImm32(Vec.S[0])) + return false; - if (AArch64_AM_isSVEMaskOfIdenticalElements16(Imm) && - isSVECpyImm16(Vec.H[0])) - return false; + if (AArch64_AM_isSVEMaskOfIdenticalElements16(Imm) && isSVECpyImm16(Vec.H[0])) + return false; - if (AArch64_AM_isSVEMaskOfIdenticalElements8(Imm) && - isSVECpyImm8(Vec.B[0])) - return false; + if (AArch64_AM_isSVEMaskOfIdenticalElements8(Imm) && isSVECpyImm8(Vec.B[0])) + return false; - return isLogicalImmediate(Vec.D, 64); + return isLogicalImmediate(Vec.D, 64); } -inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) -{ - int Shift; +inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { + int Shift; - for (Shift = 0; Shift <= RegWidth - 16; Shift += 16) - if ((Value & ~(0xffffULL << Shift)) == 0) - return true; + for (Shift = 0; Shift <= RegWidth - 16; Shift += 16) + if ((Value & ~(0xffffULL << Shift)) == 0) + return true; - return false; + return false; } -inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) -{ - if (RegWidth == 32) - Value &= 0xffffffffULL; +inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { + if (RegWidth == 32) + Value &= 0xffffffffULL; - // "lsl #0" takes precedence: in practice this only affects "#0, lsl #0". - if (Value == 0 && Shift != 0) - return false; + // "lsl #0" takes precedence: in practice this only affects "#0, lsl #0". + if (Value == 0 && Shift != 0) + return false; - return (Value & ~(0xffffULL << Shift)) == 0; + return (Value & ~(0xffffULL << Shift)) == 0; } -inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) -{ - // MOVZ takes precedence over MOVN. - if (isAnyMOVZMovAlias(Value, RegWidth)) - return false; +inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift, + int RegWidth) { + // MOVZ takes precedence over MOVN. + if (isAnyMOVZMovAlias(Value, RegWidth)) + return false; - Value = ~Value; - if (RegWidth == 32) - Value &= 0xffffffffULL; + Value = ~Value; + if (RegWidth == 32) + Value &= 0xffffffffULL; - return isMOVZMovAlias(Value, Shift, RegWidth); + return isMOVZMovAlias(Value, Shift, RegWidth); } -inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth) -{ - if (isAnyMOVZMovAlias(Value, RegWidth)) - return true; +inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { + if (isAnyMOVZMovAlias(Value, RegWidth)) + return true; - // It's not a MOVZ, but it might be a MOVN. - Value = ~Value; - if (RegWidth == 32) - Value &= 0xffffffffULL; + // It's not a MOVZ, but it might be a MOVN. + Value = ~Value; + if (RegWidth == 32) + Value &= 0xffffffffULL; - return isAnyMOVZMovAlias(Value, RegWidth); + return isAnyMOVZMovAlias(Value, RegWidth); } #endif diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c index 6aaef64329..d9e0226c4b 100644 --- a/arch/AArch64/AArch64BaseInfo.c +++ b/arch/AArch64/AArch64BaseInfo.c @@ -16,9 +16,9 @@ #ifdef CAPSTONE_HAS_ARM64 -#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) -#pragma warning(disable:4996) // disable MSVC's warning on strcpy() -#pragma warning(disable:28719) // disable MSVC's warning on strcpy() +#if defined(WIN32) || defined(WIN64) || defined(_WIN32) || defined(_WIN64) +#pragma warning(disable : 4996) // disable MSVC's warning on strcpy() +#pragma warning(disable : 28719) // disable MSVC's warning on strcpy() #endif #include "../../utils.h" @@ -32,46 +32,46 @@ // return a string representing the number X // NOTE: result must be big enough to contain the data -static void utostr(uint64_t X, bool isNeg, char *result) -{ - char Buffer[22]; - char *BufPtr = Buffer + 21; +static void utostr(uint64_t X, bool isNeg, char *result) { + char Buffer[22]; + char *BufPtr = Buffer + 21; - Buffer[21] = '\0'; - if (X == 0) *--BufPtr = '0'; // Handle special case... + Buffer[21] = '\0'; + if (X == 0) + *--BufPtr = '0'; // Handle special case... - while (X) { - *--BufPtr = X % 10 + '0'; - X /= 10; - } + while (X) { + *--BufPtr = X % 10 + '0'; + X /= 10; + } - if (isNeg) *--BufPtr = '-'; // Add negative sign... + if (isNeg) + *--BufPtr = '-'; // Add negative sign... - // suppose that result is big enough - strncpy(result, BufPtr, sizeof(Buffer)); + // suppose that result is big enough + strncpy(result, BufPtr, sizeof(Buffer)); } // NOTE: result must be big enough to contain the result -void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result) -{ - // assert(Bits < 0x10000); - char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32]; - int dummy; - uint32_t Op0 = (Bits >> 14) & 0x3; - uint32_t Op1 = (Bits >> 11) & 0x7; - uint32_t CRn = (Bits >> 7) & 0xf; - uint32_t CRm = (Bits >> 3) & 0xf; - uint32_t Op2 = Bits & 0x7; - - utostr(Op0, false, Op0Str); - utostr(Op1, false, Op1Str); - utostr(Op2, false, Op2Str); - utostr(CRn, false, CRnStr); - utostr(CRm, false, CRmStr); - - dummy = cs_snprintf(result, 128, "s%s_%s_c%s_c%s_%s", - Op0Str, Op1Str, CRnStr, CRmStr, Op2Str); - (void)dummy; +void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result) { + // assert(Bits < 0x10000); + char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32]; + int dummy; + uint32_t Op0 = (Bits >> 14) & 0x3; + uint32_t Op1 = (Bits >> 11) & 0x7; + uint32_t CRn = (Bits >> 7) & 0xf; + uint32_t CRm = (Bits >> 3) & 0xf; + uint32_t Op2 = Bits & 0x7; + + utostr(Op0, false, Op0Str); + utostr(Op1, false, Op1Str); + utostr(Op2, false, Op2Str); + utostr(CRn, false, CRnStr); + utostr(CRm, false, CRmStr); + + dummy = cs_snprintf(result, 128, "s%s_%s_c%s_c%s_%s", Op0Str, Op1Str, CRnStr, + CRmStr, Op2Str); + (void)dummy; } #endif diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h index eeb7301d80..5af6994990 100644 --- a/arch/AArch64/AArch64BaseInfo.h +++ b/arch/AArch64/AArch64BaseInfo.h @@ -20,261 +20,417 @@ #ifndef CS_LLVM_AARCH64_BASEINFO_H #define CS_LLVM_AARCH64_BASEINFO_H +#include "AArch64Mapping.h" #include #include -#include "AArch64Mapping.h" #ifndef __cplusplus -#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) +#if defined(WIN32) || defined(WIN64) || defined(_WIN32) || defined(_WIN64) #define inline /* inline */ #endif #endif -inline static unsigned getWRegFromXReg(unsigned Reg) -{ - switch (Reg) { - default: break; - case ARM64_REG_X0: return ARM64_REG_W0; - case ARM64_REG_X1: return ARM64_REG_W1; - case ARM64_REG_X2: return ARM64_REG_W2; - case ARM64_REG_X3: return ARM64_REG_W3; - case ARM64_REG_X4: return ARM64_REG_W4; - case ARM64_REG_X5: return ARM64_REG_W5; - case ARM64_REG_X6: return ARM64_REG_W6; - case ARM64_REG_X7: return ARM64_REG_W7; - case ARM64_REG_X8: return ARM64_REG_W8; - case ARM64_REG_X9: return ARM64_REG_W9; - case ARM64_REG_X10: return ARM64_REG_W10; - case ARM64_REG_X11: return ARM64_REG_W11; - case ARM64_REG_X12: return ARM64_REG_W12; - case ARM64_REG_X13: return ARM64_REG_W13; - case ARM64_REG_X14: return ARM64_REG_W14; - case ARM64_REG_X15: return ARM64_REG_W15; - case ARM64_REG_X16: return ARM64_REG_W16; - case ARM64_REG_X17: return ARM64_REG_W17; - case ARM64_REG_X18: return ARM64_REG_W18; - case ARM64_REG_X19: return ARM64_REG_W19; - case ARM64_REG_X20: return ARM64_REG_W20; - case ARM64_REG_X21: return ARM64_REG_W21; - case ARM64_REG_X22: return ARM64_REG_W22; - case ARM64_REG_X23: return ARM64_REG_W23; - case ARM64_REG_X24: return ARM64_REG_W24; - case ARM64_REG_X25: return ARM64_REG_W25; - case ARM64_REG_X26: return ARM64_REG_W26; - case ARM64_REG_X27: return ARM64_REG_W27; - case ARM64_REG_X28: return ARM64_REG_W28; - case ARM64_REG_FP: return ARM64_REG_W29; - case ARM64_REG_LR: return ARM64_REG_W30; - case ARM64_REG_SP: return ARM64_REG_WSP; - case ARM64_REG_XZR: return ARM64_REG_WZR; - } - - // For anything else, return it unchanged. - return Reg; +inline static unsigned getWRegFromXReg(unsigned Reg) { + switch (Reg) { + default: + break; + case ARM64_REG_X0: + return ARM64_REG_W0; + case ARM64_REG_X1: + return ARM64_REG_W1; + case ARM64_REG_X2: + return ARM64_REG_W2; + case ARM64_REG_X3: + return ARM64_REG_W3; + case ARM64_REG_X4: + return ARM64_REG_W4; + case ARM64_REG_X5: + return ARM64_REG_W5; + case ARM64_REG_X6: + return ARM64_REG_W6; + case ARM64_REG_X7: + return ARM64_REG_W7; + case ARM64_REG_X8: + return ARM64_REG_W8; + case ARM64_REG_X9: + return ARM64_REG_W9; + case ARM64_REG_X10: + return ARM64_REG_W10; + case ARM64_REG_X11: + return ARM64_REG_W11; + case ARM64_REG_X12: + return ARM64_REG_W12; + case ARM64_REG_X13: + return ARM64_REG_W13; + case ARM64_REG_X14: + return ARM64_REG_W14; + case ARM64_REG_X15: + return ARM64_REG_W15; + case ARM64_REG_X16: + return ARM64_REG_W16; + case ARM64_REG_X17: + return ARM64_REG_W17; + case ARM64_REG_X18: + return ARM64_REG_W18; + case ARM64_REG_X19: + return ARM64_REG_W19; + case ARM64_REG_X20: + return ARM64_REG_W20; + case ARM64_REG_X21: + return ARM64_REG_W21; + case ARM64_REG_X22: + return ARM64_REG_W22; + case ARM64_REG_X23: + return ARM64_REG_W23; + case ARM64_REG_X24: + return ARM64_REG_W24; + case ARM64_REG_X25: + return ARM64_REG_W25; + case ARM64_REG_X26: + return ARM64_REG_W26; + case ARM64_REG_X27: + return ARM64_REG_W27; + case ARM64_REG_X28: + return ARM64_REG_W28; + case ARM64_REG_FP: + return ARM64_REG_W29; + case ARM64_REG_LR: + return ARM64_REG_W30; + case ARM64_REG_SP: + return ARM64_REG_WSP; + case ARM64_REG_XZR: + return ARM64_REG_WZR; + } + + // For anything else, return it unchanged. + return Reg; } -inline static unsigned getXRegFromWReg(unsigned Reg) -{ - switch (Reg) { - case ARM64_REG_W0: return ARM64_REG_X0; - case ARM64_REG_W1: return ARM64_REG_X1; - case ARM64_REG_W2: return ARM64_REG_X2; - case ARM64_REG_W3: return ARM64_REG_X3; - case ARM64_REG_W4: return ARM64_REG_X4; - case ARM64_REG_W5: return ARM64_REG_X5; - case ARM64_REG_W6: return ARM64_REG_X6; - case ARM64_REG_W7: return ARM64_REG_X7; - case ARM64_REG_W8: return ARM64_REG_X8; - case ARM64_REG_W9: return ARM64_REG_X9; - case ARM64_REG_W10: return ARM64_REG_X10; - case ARM64_REG_W11: return ARM64_REG_X11; - case ARM64_REG_W12: return ARM64_REG_X12; - case ARM64_REG_W13: return ARM64_REG_X13; - case ARM64_REG_W14: return ARM64_REG_X14; - case ARM64_REG_W15: return ARM64_REG_X15; - case ARM64_REG_W16: return ARM64_REG_X16; - case ARM64_REG_W17: return ARM64_REG_X17; - case ARM64_REG_W18: return ARM64_REG_X18; - case ARM64_REG_W19: return ARM64_REG_X19; - case ARM64_REG_W20: return ARM64_REG_X20; - case ARM64_REG_W21: return ARM64_REG_X21; - case ARM64_REG_W22: return ARM64_REG_X22; - case ARM64_REG_W23: return ARM64_REG_X23; - case ARM64_REG_W24: return ARM64_REG_X24; - case ARM64_REG_W25: return ARM64_REG_X25; - case ARM64_REG_W26: return ARM64_REG_X26; - case ARM64_REG_W27: return ARM64_REG_X27; - case ARM64_REG_W28: return ARM64_REG_X28; - case ARM64_REG_W29: return ARM64_REG_FP; - case ARM64_REG_W30: return ARM64_REG_LR; - case ARM64_REG_WSP: return ARM64_REG_SP; - case ARM64_REG_WZR: return ARM64_REG_XZR; - } - - // For anything else, return it unchanged. - return Reg; +inline static unsigned getXRegFromWReg(unsigned Reg) { + switch (Reg) { + case ARM64_REG_W0: + return ARM64_REG_X0; + case ARM64_REG_W1: + return ARM64_REG_X1; + case ARM64_REG_W2: + return ARM64_REG_X2; + case ARM64_REG_W3: + return ARM64_REG_X3; + case ARM64_REG_W4: + return ARM64_REG_X4; + case ARM64_REG_W5: + return ARM64_REG_X5; + case ARM64_REG_W6: + return ARM64_REG_X6; + case ARM64_REG_W7: + return ARM64_REG_X7; + case ARM64_REG_W8: + return ARM64_REG_X8; + case ARM64_REG_W9: + return ARM64_REG_X9; + case ARM64_REG_W10: + return ARM64_REG_X10; + case ARM64_REG_W11: + return ARM64_REG_X11; + case ARM64_REG_W12: + return ARM64_REG_X12; + case ARM64_REG_W13: + return ARM64_REG_X13; + case ARM64_REG_W14: + return ARM64_REG_X14; + case ARM64_REG_W15: + return ARM64_REG_X15; + case ARM64_REG_W16: + return ARM64_REG_X16; + case ARM64_REG_W17: + return ARM64_REG_X17; + case ARM64_REG_W18: + return ARM64_REG_X18; + case ARM64_REG_W19: + return ARM64_REG_X19; + case ARM64_REG_W20: + return ARM64_REG_X20; + case ARM64_REG_W21: + return ARM64_REG_X21; + case ARM64_REG_W22: + return ARM64_REG_X22; + case ARM64_REG_W23: + return ARM64_REG_X23; + case ARM64_REG_W24: + return ARM64_REG_X24; + case ARM64_REG_W25: + return ARM64_REG_X25; + case ARM64_REG_W26: + return ARM64_REG_X26; + case ARM64_REG_W27: + return ARM64_REG_X27; + case ARM64_REG_W28: + return ARM64_REG_X28; + case ARM64_REG_W29: + return ARM64_REG_FP; + case ARM64_REG_W30: + return ARM64_REG_LR; + case ARM64_REG_WSP: + return ARM64_REG_SP; + case ARM64_REG_WZR: + return ARM64_REG_XZR; + } + + // For anything else, return it unchanged. + return Reg; } -inline static unsigned getBRegFromDReg(unsigned Reg) -{ - switch (Reg) { - case ARM64_REG_D0: return ARM64_REG_B0; - case ARM64_REG_D1: return ARM64_REG_B1; - case ARM64_REG_D2: return ARM64_REG_B2; - case ARM64_REG_D3: return ARM64_REG_B3; - case ARM64_REG_D4: return ARM64_REG_B4; - case ARM64_REG_D5: return ARM64_REG_B5; - case ARM64_REG_D6: return ARM64_REG_B6; - case ARM64_REG_D7: return ARM64_REG_B7; - case ARM64_REG_D8: return ARM64_REG_B8; - case ARM64_REG_D9: return ARM64_REG_B9; - case ARM64_REG_D10: return ARM64_REG_B10; - case ARM64_REG_D11: return ARM64_REG_B11; - case ARM64_REG_D12: return ARM64_REG_B12; - case ARM64_REG_D13: return ARM64_REG_B13; - case ARM64_REG_D14: return ARM64_REG_B14; - case ARM64_REG_D15: return ARM64_REG_B15; - case ARM64_REG_D16: return ARM64_REG_B16; - case ARM64_REG_D17: return ARM64_REG_B17; - case ARM64_REG_D18: return ARM64_REG_B18; - case ARM64_REG_D19: return ARM64_REG_B19; - case ARM64_REG_D20: return ARM64_REG_B20; - case ARM64_REG_D21: return ARM64_REG_B21; - case ARM64_REG_D22: return ARM64_REG_B22; - case ARM64_REG_D23: return ARM64_REG_B23; - case ARM64_REG_D24: return ARM64_REG_B24; - case ARM64_REG_D25: return ARM64_REG_B25; - case ARM64_REG_D26: return ARM64_REG_B26; - case ARM64_REG_D27: return ARM64_REG_B27; - case ARM64_REG_D28: return ARM64_REG_B28; - case ARM64_REG_D29: return ARM64_REG_B29; - case ARM64_REG_D30: return ARM64_REG_B30; - case ARM64_REG_D31: return ARM64_REG_B31; - } - - // For anything else, return it unchanged. - return Reg; +inline static unsigned getBRegFromDReg(unsigned Reg) { + switch (Reg) { + case ARM64_REG_D0: + return ARM64_REG_B0; + case ARM64_REG_D1: + return ARM64_REG_B1; + case ARM64_REG_D2: + return ARM64_REG_B2; + case ARM64_REG_D3: + return ARM64_REG_B3; + case ARM64_REG_D4: + return ARM64_REG_B4; + case ARM64_REG_D5: + return ARM64_REG_B5; + case ARM64_REG_D6: + return ARM64_REG_B6; + case ARM64_REG_D7: + return ARM64_REG_B7; + case ARM64_REG_D8: + return ARM64_REG_B8; + case ARM64_REG_D9: + return ARM64_REG_B9; + case ARM64_REG_D10: + return ARM64_REG_B10; + case ARM64_REG_D11: + return ARM64_REG_B11; + case ARM64_REG_D12: + return ARM64_REG_B12; + case ARM64_REG_D13: + return ARM64_REG_B13; + case ARM64_REG_D14: + return ARM64_REG_B14; + case ARM64_REG_D15: + return ARM64_REG_B15; + case ARM64_REG_D16: + return ARM64_REG_B16; + case ARM64_REG_D17: + return ARM64_REG_B17; + case ARM64_REG_D18: + return ARM64_REG_B18; + case ARM64_REG_D19: + return ARM64_REG_B19; + case ARM64_REG_D20: + return ARM64_REG_B20; + case ARM64_REG_D21: + return ARM64_REG_B21; + case ARM64_REG_D22: + return ARM64_REG_B22; + case ARM64_REG_D23: + return ARM64_REG_B23; + case ARM64_REG_D24: + return ARM64_REG_B24; + case ARM64_REG_D25: + return ARM64_REG_B25; + case ARM64_REG_D26: + return ARM64_REG_B26; + case ARM64_REG_D27: + return ARM64_REG_B27; + case ARM64_REG_D28: + return ARM64_REG_B28; + case ARM64_REG_D29: + return ARM64_REG_B29; + case ARM64_REG_D30: + return ARM64_REG_B30; + case ARM64_REG_D31: + return ARM64_REG_B31; + } + + // For anything else, return it unchanged. + return Reg; } -inline static unsigned getDRegFromBReg(unsigned Reg) -{ - switch (Reg) { - case ARM64_REG_B0: return ARM64_REG_D0; - case ARM64_REG_B1: return ARM64_REG_D1; - case ARM64_REG_B2: return ARM64_REG_D2; - case ARM64_REG_B3: return ARM64_REG_D3; - case ARM64_REG_B4: return ARM64_REG_D4; - case ARM64_REG_B5: return ARM64_REG_D5; - case ARM64_REG_B6: return ARM64_REG_D6; - case ARM64_REG_B7: return ARM64_REG_D7; - case ARM64_REG_B8: return ARM64_REG_D8; - case ARM64_REG_B9: return ARM64_REG_D9; - case ARM64_REG_B10: return ARM64_REG_D10; - case ARM64_REG_B11: return ARM64_REG_D11; - case ARM64_REG_B12: return ARM64_REG_D12; - case ARM64_REG_B13: return ARM64_REG_D13; - case ARM64_REG_B14: return ARM64_REG_D14; - case ARM64_REG_B15: return ARM64_REG_D15; - case ARM64_REG_B16: return ARM64_REG_D16; - case ARM64_REG_B17: return ARM64_REG_D17; - case ARM64_REG_B18: return ARM64_REG_D18; - case ARM64_REG_B19: return ARM64_REG_D19; - case ARM64_REG_B20: return ARM64_REG_D20; - case ARM64_REG_B21: return ARM64_REG_D21; - case ARM64_REG_B22: return ARM64_REG_D22; - case ARM64_REG_B23: return ARM64_REG_D23; - case ARM64_REG_B24: return ARM64_REG_D24; - case ARM64_REG_B25: return ARM64_REG_D25; - case ARM64_REG_B26: return ARM64_REG_D26; - case ARM64_REG_B27: return ARM64_REG_D27; - case ARM64_REG_B28: return ARM64_REG_D28; - case ARM64_REG_B29: return ARM64_REG_D29; - case ARM64_REG_B30: return ARM64_REG_D30; - case ARM64_REG_B31: return ARM64_REG_D31; - } - - // For anything else, return it unchanged. - return Reg; +inline static unsigned getDRegFromBReg(unsigned Reg) { + switch (Reg) { + case ARM64_REG_B0: + return ARM64_REG_D0; + case ARM64_REG_B1: + return ARM64_REG_D1; + case ARM64_REG_B2: + return ARM64_REG_D2; + case ARM64_REG_B3: + return ARM64_REG_D3; + case ARM64_REG_B4: + return ARM64_REG_D4; + case ARM64_REG_B5: + return ARM64_REG_D5; + case ARM64_REG_B6: + return ARM64_REG_D6; + case ARM64_REG_B7: + return ARM64_REG_D7; + case ARM64_REG_B8: + return ARM64_REG_D8; + case ARM64_REG_B9: + return ARM64_REG_D9; + case ARM64_REG_B10: + return ARM64_REG_D10; + case ARM64_REG_B11: + return ARM64_REG_D11; + case ARM64_REG_B12: + return ARM64_REG_D12; + case ARM64_REG_B13: + return ARM64_REG_D13; + case ARM64_REG_B14: + return ARM64_REG_D14; + case ARM64_REG_B15: + return ARM64_REG_D15; + case ARM64_REG_B16: + return ARM64_REG_D16; + case ARM64_REG_B17: + return ARM64_REG_D17; + case ARM64_REG_B18: + return ARM64_REG_D18; + case ARM64_REG_B19: + return ARM64_REG_D19; + case ARM64_REG_B20: + return ARM64_REG_D20; + case ARM64_REG_B21: + return ARM64_REG_D21; + case ARM64_REG_B22: + return ARM64_REG_D22; + case ARM64_REG_B23: + return ARM64_REG_D23; + case ARM64_REG_B24: + return ARM64_REG_D24; + case ARM64_REG_B25: + return ARM64_REG_D25; + case ARM64_REG_B26: + return ARM64_REG_D26; + case ARM64_REG_B27: + return ARM64_REG_D27; + case ARM64_REG_B28: + return ARM64_REG_D28; + case ARM64_REG_B29: + return ARM64_REG_D29; + case ARM64_REG_B30: + return ARM64_REG_D30; + case ARM64_REG_B31: + return ARM64_REG_D31; + } + + // For anything else, return it unchanged. + return Reg; } // // Enums corresponding to AArch64 condition codes // The CondCodes constants map directly to the 4-bit encoding of the // condition field for predicated instructions. -typedef enum AArch64CC_CondCode { // Meaning (integer) Meaning (floating-point) - AArch64CC_EQ = 0x0, // Equal Equal - AArch64CC_NE = 0x1, // Not equal Not equal, or unordered - AArch64CC_HS = 0x2, // Unsigned higher or same >, ==, or unordered - AArch64CC_LO = 0x3, // Unsigned lower Less than - AArch64CC_MI = 0x4, // Minus, negative Less than - AArch64CC_PL = 0x5, // Plus, positive or zero >, ==, or unordered - AArch64CC_VS = 0x6, // Overflow Unordered - AArch64CC_VC = 0x7, // No overflow Not unordered - AArch64CC_HI = 0x8, // Unsigned higher Greater than, or unordered - AArch64CC_LS = 0x9, // Unsigned lower or same Less than or equal - AArch64CC_GE = 0xa, // Greater than or equal Greater than or equal - AArch64CC_LT = 0xb, // Less than Less than, or unordered - AArch64CC_GT = 0xc, // Greater than Greater than - AArch64CC_LE = 0xd, // Less than or equal <, ==, or unordered - AArch64CC_AL = 0xe, // Always (unconditional) Always (unconditional) - AArch64CC_NV = 0xf, // Always (unconditional) Always (unconditional) - // Note the NV exists purely to disassemble 0b1111. Execution is "always". - AArch64CC_Invalid +typedef enum AArch64CC_CondCode { // Meaning (integer) Meaning + // (floating-point) + AArch64CC_EQ = 0x0, // Equal Equal + AArch64CC_NE = 0x1, // Not equal Not equal, or unordered + AArch64CC_HS = 0x2, // Unsigned higher or same >, ==, or unordered + AArch64CC_LO = 0x3, // Unsigned lower Less than + AArch64CC_MI = 0x4, // Minus, negative Less than + AArch64CC_PL = 0x5, // Plus, positive or zero >, ==, or unordered + AArch64CC_VS = 0x6, // Overflow Unordered + AArch64CC_VC = 0x7, // No overflow Not unordered + AArch64CC_HI = 0x8, // Unsigned higher Greater than, or unordered + AArch64CC_LS = 0x9, // Unsigned lower or same Less than or equal + AArch64CC_GE = 0xa, // Greater than or equal Greater than or equal + AArch64CC_LT = 0xb, // Less than Less than, or unordered + AArch64CC_GT = 0xc, // Greater than Greater than + AArch64CC_LE = 0xd, // Less than or equal <, ==, or unordered + AArch64CC_AL = 0xe, // Always (unconditional) Always (unconditional) + AArch64CC_NV = 0xf, // Always (unconditional) Always (unconditional) + // Note the NV exists purely to disassemble 0b1111. Execution is "always". + AArch64CC_Invalid } AArch64CC_CondCode; -inline static AArch64CC_CondCode getInvertedCondCode(AArch64CC_CondCode Code) -{ - // To reverse a condition it's necessary to only invert the low bit: - return (AArch64CC_CondCode)((unsigned)Code ^ 0x1); +inline static AArch64CC_CondCode getInvertedCondCode(AArch64CC_CondCode Code) { + // To reverse a condition it's necessary to only invert the low bit: + return (AArch64CC_CondCode)((unsigned)Code ^ 0x1); } -inline static const char *getCondCodeName(AArch64CC_CondCode CC) -{ - switch (CC) { - default: return NULL; // never reach - case AArch64CC_EQ: return "eq"; - case AArch64CC_NE: return "ne"; - case AArch64CC_HS: return "hs"; - case AArch64CC_LO: return "lo"; - case AArch64CC_MI: return "mi"; - case AArch64CC_PL: return "pl"; - case AArch64CC_VS: return "vs"; - case AArch64CC_VC: return "vc"; - case AArch64CC_HI: return "hi"; - case AArch64CC_LS: return "ls"; - case AArch64CC_GE: return "ge"; - case AArch64CC_LT: return "lt"; - case AArch64CC_GT: return "gt"; - case AArch64CC_LE: return "le"; - case AArch64CC_AL: return "al"; - case AArch64CC_NV: return "nv"; - } +inline static const char *getCondCodeName(AArch64CC_CondCode CC) { + switch (CC) { + default: + return NULL; // never reach + case AArch64CC_EQ: + return "eq"; + case AArch64CC_NE: + return "ne"; + case AArch64CC_HS: + return "hs"; + case AArch64CC_LO: + return "lo"; + case AArch64CC_MI: + return "mi"; + case AArch64CC_PL: + return "pl"; + case AArch64CC_VS: + return "vs"; + case AArch64CC_VC: + return "vc"; + case AArch64CC_HI: + return "hi"; + case AArch64CC_LS: + return "ls"; + case AArch64CC_GE: + return "ge"; + case AArch64CC_LT: + return "lt"; + case AArch64CC_GT: + return "gt"; + case AArch64CC_LE: + return "le"; + case AArch64CC_AL: + return "al"; + case AArch64CC_NV: + return "nv"; + } } /// Given a condition code, return NZCV flags that would satisfy that condition. /// The flag bits are in the format expected by the ccmp instructions. /// Note that many different flag settings can satisfy a given condition code, /// this function just returns one of them. -inline static unsigned getNZCVToSatisfyCondCode(AArch64CC_CondCode Code) -{ - // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. - enum { N = 8, Z = 4, C = 2, V = 1 }; - switch (Code) { - default: // llvm_unreachable("Unknown condition code"); - case AArch64CC_EQ: return Z; // Z == 1 - case AArch64CC_NE: return 0; // Z == 0 - case AArch64CC_HS: return C; // C == 1 - case AArch64CC_LO: return 0; // C == 0 - case AArch64CC_MI: return N; // N == 1 - case AArch64CC_PL: return 0; // N == 0 - case AArch64CC_VS: return V; // V == 1 - case AArch64CC_VC: return 0; // V == 0 - case AArch64CC_HI: return C; // C == 1 && Z == 0 - case AArch64CC_LS: return 0; // C == 0 || Z == 1 - case AArch64CC_GE: return 0; // N == V - case AArch64CC_LT: return N; // N != V - case AArch64CC_GT: return 0; // Z == 0 && N == V - case AArch64CC_LE: return Z; // Z == 1 || N != V - } +inline static unsigned getNZCVToSatisfyCondCode(AArch64CC_CondCode Code) { + // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. + enum { N = 8, Z = 4, C = 2, V = 1 }; + switch (Code) { + default: // llvm_unreachable("Unknown condition code"); + case AArch64CC_EQ: + return Z; // Z == 1 + case AArch64CC_NE: + return 0; // Z == 0 + case AArch64CC_HS: + return C; // C == 1 + case AArch64CC_LO: + return 0; // C == 0 + case AArch64CC_MI: + return N; // N == 1 + case AArch64CC_PL: + return 0; // N == 0 + case AArch64CC_VS: + return V; // V == 1 + case AArch64CC_VC: + return 0; // V == 0 + case AArch64CC_HI: + return C; // C == 1 && Z == 0 + case AArch64CC_LS: + return 0; // C == 0 || Z == 1 + case AArch64CC_GE: + return 0; // N == V + case AArch64CC_LT: + return N; // N != V + case AArch64CC_GT: + return 0; // Z == 0 && N == V + case AArch64CC_LE: + return Z; // Z == 1 || N != V + } } /// Instances of this class can perform bidirectional mapping from random @@ -289,183 +445,196 @@ inline static unsigned getNZCVToSatisfyCondCode(AArch64CC_CondCode Code) /// might even be optimal to just reorder the tables for the common instructions /// rather than changing the algorithm. typedef struct A64NamedImmMapper_Mapping { - const char *Name; - uint32_t Value; + const char *Name; + uint32_t Value; } A64NamedImmMapper_Mapping; typedef struct A64NamedImmMapper { - const A64NamedImmMapper_Mapping *Pairs; - size_t NumPairs; - uint32_t TooBigImm; + const A64NamedImmMapper_Mapping *Pairs; + size_t NumPairs; + uint32_t TooBigImm; } A64NamedImmMapper; typedef struct A64SysRegMapper { - const A64NamedImmMapper_Mapping *SysRegPairs; - const A64NamedImmMapper_Mapping *InstPairs; - size_t NumInstPairs; + const A64NamedImmMapper_Mapping *SysRegPairs; + const A64NamedImmMapper_Mapping *InstPairs; + size_t NumInstPairs; } A64SysRegMapper; typedef enum A64SE_ShiftExtSpecifiers { - A64SE_Invalid = -1, - A64SE_LSL, - A64SE_MSL, - A64SE_LSR, - A64SE_ASR, - A64SE_ROR, - - A64SE_UXTB, - A64SE_UXTH, - A64SE_UXTW, - A64SE_UXTX, - - A64SE_SXTB, - A64SE_SXTH, - A64SE_SXTW, - A64SE_SXTX + A64SE_Invalid = -1, + A64SE_LSL, + A64SE_MSL, + A64SE_LSR, + A64SE_ASR, + A64SE_ROR, + + A64SE_UXTB, + A64SE_UXTH, + A64SE_UXTW, + A64SE_UXTX, + + A64SE_SXTB, + A64SE_SXTH, + A64SE_SXTW, + A64SE_SXTX } A64SE_ShiftExtSpecifiers; typedef enum A64Layout_VectorLayout { - A64Layout_Invalid = -1, - A64Layout_VL_8B, - A64Layout_VL_4H, - A64Layout_VL_2S, - A64Layout_VL_1D, - - A64Layout_VL_16B, - A64Layout_VL_8H, - A64Layout_VL_4S, - A64Layout_VL_2D, - - // Bare layout for the 128-bit vector - // (only show ".b", ".h", ".s", ".d" without vector number) - A64Layout_VL_B, - A64Layout_VL_H, - A64Layout_VL_S, - A64Layout_VL_D + A64Layout_Invalid = -1, + A64Layout_VL_8B, + A64Layout_VL_4H, + A64Layout_VL_2S, + A64Layout_VL_1D, + + A64Layout_VL_16B, + A64Layout_VL_8H, + A64Layout_VL_4S, + A64Layout_VL_2D, + + // Bare layout for the 128-bit vector + // (only show ".b", ".h", ".s", ".d" without vector number) + A64Layout_VL_B, + A64Layout_VL_H, + A64Layout_VL_S, + A64Layout_VL_D } A64Layout_VectorLayout; -inline static const char *AArch64VectorLayoutToString(A64Layout_VectorLayout Layout) -{ - switch (Layout) { - default: return NULL; // never reach - case A64Layout_VL_8B: return ".8b"; - case A64Layout_VL_4H: return ".4h"; - case A64Layout_VL_2S: return ".2s"; - case A64Layout_VL_1D: return ".1d"; - case A64Layout_VL_16B: return ".16b"; - case A64Layout_VL_8H: return ".8h"; - case A64Layout_VL_4S: return ".4s"; - case A64Layout_VL_2D: return ".2d"; - case A64Layout_VL_B: return ".b"; - case A64Layout_VL_H: return ".h"; - case A64Layout_VL_S: return ".s"; - case A64Layout_VL_D: return ".d"; - } +inline static const char * +AArch64VectorLayoutToString(A64Layout_VectorLayout Layout) { + switch (Layout) { + default: + return NULL; // never reach + case A64Layout_VL_8B: + return ".8b"; + case A64Layout_VL_4H: + return ".4h"; + case A64Layout_VL_2S: + return ".2s"; + case A64Layout_VL_1D: + return ".1d"; + case A64Layout_VL_16B: + return ".16b"; + case A64Layout_VL_8H: + return ".8h"; + case A64Layout_VL_4S: + return ".4s"; + case A64Layout_VL_2D: + return ".2d"; + case A64Layout_VL_B: + return ".b"; + case A64Layout_VL_H: + return ".h"; + case A64Layout_VL_S: + return ".s"; + case A64Layout_VL_D: + return ".d"; + } } -inline static A64Layout_VectorLayout AArch64StringToVectorLayout(char *LayoutStr) -{ - if (!strcmp(LayoutStr, ".8b")) - return A64Layout_VL_8B; +inline static A64Layout_VectorLayout +AArch64StringToVectorLayout(char *LayoutStr) { + if (!strcmp(LayoutStr, ".8b")) + return A64Layout_VL_8B; - if (!strcmp(LayoutStr, ".4h")) - return A64Layout_VL_4H; + if (!strcmp(LayoutStr, ".4h")) + return A64Layout_VL_4H; - if (!strcmp(LayoutStr, ".2s")) - return A64Layout_VL_2S; + if (!strcmp(LayoutStr, ".2s")) + return A64Layout_VL_2S; - if (!strcmp(LayoutStr, ".1d")) - return A64Layout_VL_1D; + if (!strcmp(LayoutStr, ".1d")) + return A64Layout_VL_1D; - if (!strcmp(LayoutStr, ".16b")) - return A64Layout_VL_16B; + if (!strcmp(LayoutStr, ".16b")) + return A64Layout_VL_16B; - if (!strcmp(LayoutStr, ".8h")) - return A64Layout_VL_8H; + if (!strcmp(LayoutStr, ".8h")) + return A64Layout_VL_8H; - if (!strcmp(LayoutStr, ".4s")) - return A64Layout_VL_4S; + if (!strcmp(LayoutStr, ".4s")) + return A64Layout_VL_4S; - if (!strcmp(LayoutStr, ".2d")) - return A64Layout_VL_2D; + if (!strcmp(LayoutStr, ".2d")) + return A64Layout_VL_2D; - if (!strcmp(LayoutStr, ".b")) - return A64Layout_VL_B; + if (!strcmp(LayoutStr, ".b")) + return A64Layout_VL_B; - if (!strcmp(LayoutStr, ".s")) - return A64Layout_VL_S; + if (!strcmp(LayoutStr, ".s")) + return A64Layout_VL_S; - if (!strcmp(LayoutStr, ".d")) - return A64Layout_VL_D; + if (!strcmp(LayoutStr, ".d")) + return A64Layout_VL_D; - return A64Layout_Invalid; + return A64Layout_Invalid; } /// Target Operand Flag enum. enum TOF { - //===------------------------------------------------------------------===// - // AArch64 Specific MachineOperand flags. - - MO_NO_FLAG, - - MO_FRAGMENT = 0xf, - - /// MO_PAGE - A symbol operand with this flag represents the pc-relative - /// offset of the 4K page containing the symbol. This is used with the - /// ADRP instruction. - MO_PAGE = 1, - - /// MO_PAGEOFF - A symbol operand with this flag represents the offset of - /// that symbol within a 4K page. This offset is added to the page address - /// to produce the complete address. - MO_PAGEOFF = 2, - - /// MO_G3 - A symbol operand with this flag (granule 3) represents the high - /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction - MO_G3 = 3, - - /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits - /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction - MO_G2 = 4, - - /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits - /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction - MO_G1 = 5, - - /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits - /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction - MO_G0 = 6, - - /// MO_HI12 - This flag indicates that a symbol operand represents the bits - /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- - /// by-12-bits instruction. - MO_HI12 = 7, - - /// MO_GOT - This flag indicates that a symbol operand represents the - /// address of the GOT entry for the symbol, rather than the address of - /// the symbol itself. - MO_GOT = 0x10, - - /// MO_NC - Indicates whether the linker is expected to check the symbol - /// reference for overflow. For example in an ADRP/ADD pair of relocations - /// the ADRP usually does check, but not the ADD. - MO_NC = 0x20, - - /// MO_TLS - Indicates that the operand being accessed is some kind of - /// thread-local symbol. On Darwin, only one type of thread-local access - /// exists (pre linker-relaxation), but on ELF the TLSModel used for the - /// referee will affect interpretation. - MO_TLS = 0x40, - - /// MO_DLLIMPORT - On a symbol operand, this represents that the reference - /// to the symbol is for an import stub. This is used for DLL import - /// storage class indication on Windows. - MO_DLLIMPORT = 0x80, + //===------------------------------------------------------------------===// + // AArch64 Specific MachineOperand flags. + + MO_NO_FLAG, + + MO_FRAGMENT = 0xf, + + /// MO_PAGE - A symbol operand with this flag represents the pc-relative + /// offset of the 4K page containing the symbol. This is used with the + /// ADRP instruction. + MO_PAGE = 1, + + /// MO_PAGEOFF - A symbol operand with this flag represents the offset of + /// that symbol within a 4K page. This offset is added to the page address + /// to produce the complete address. + MO_PAGEOFF = 2, + + /// MO_G3 - A symbol operand with this flag (granule 3) represents the high + /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction + MO_G3 = 3, + + /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits + /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction + MO_G2 = 4, + + /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits + /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction + MO_G1 = 5, + + /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits + /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction + MO_G0 = 6, + + /// MO_HI12 - This flag indicates that a symbol operand represents the bits + /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- + /// by-12-bits instruction. + MO_HI12 = 7, + + /// MO_GOT - This flag indicates that a symbol operand represents the + /// address of the GOT entry for the symbol, rather than the address of + /// the symbol itself. + MO_GOT = 0x10, + + /// MO_NC - Indicates whether the linker is expected to check the symbol + /// reference for overflow. For example in an ADRP/ADD pair of relocations + /// the ADRP usually does check, but not the ADD. + MO_NC = 0x20, + + /// MO_TLS - Indicates that the operand being accessed is some kind of + /// thread-local symbol. On Darwin, only one type of thread-local access + /// exists (pre linker-relaxation), but on ELF the TLSModel used for the + /// referee will affect interpretation. + MO_TLS = 0x40, + + /// MO_DLLIMPORT - On a symbol operand, this represents that the reference + /// to the symbol is for an import stub. This is used for DLL import + /// storage class indication on Windows. + MO_DLLIMPORT = 0x80, }; typedef struct SysAlias { - const char *Name; - uint16_t Encoding; + const char *Name; + uint16_t Encoding; } SysAlias; #define AT SysAlias @@ -480,27 +649,27 @@ typedef struct SysAlias { #define SVEPREDPAT SysAlias typedef struct SysAliasReg { - const char *Name; - uint16_t Encoding; - bool NeedsReg; + const char *Name; + uint16_t Encoding; + bool NeedsReg; } SysAliasReg; #define IC SysAliasReg #define TLBI SysAliasReg typedef struct SysAliasSysReg { - const char *Name; - uint16_t Encoding; - bool Readable; - bool Writeable; + const char *Name; + uint16_t Encoding; + bool Readable; + bool Writeable; } SysAliasSysReg; #define SysReg SysAliasSysReg typedef struct ExactFPImm { - const char *Name; - int Enum; - const char *Repr; + const char *Name; + int Enum; + const char *Repr; } ExactFPImm; const AT *lookupATByEncoding(uint16_t Encoding); diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c index be80098402..906163cbf7 100644 --- a/arch/AArch64/AArch64Disassembler.c +++ b/arch/AArch64/AArch64Disassembler.c @@ -18,7 +18,7 @@ #ifdef CAPSTONE_HAS_ARM64 -#include // DEBUG +#include // DEBUG #include #include "../../cs_priv.h" @@ -37,1956 +37,123 @@ // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address, - const void *Decoder, int Bits); -static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr, - const void *Decoder, int ElementWidth); -static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder); -static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder); +static bool Check(DecodeStatus *Out, DecodeStatus In) { + switch (In) { + default: // never reach + return true; -static bool Check(DecodeStatus *Out, DecodeStatus In) -{ - switch (In) { - default: // never reach - return true; + case MCDisassembler_Success: + // Out stays the same. + return true; - case MCDisassembler_Success: - // Out stays the same. - return true; + case MCDisassembler_SoftFail: + *Out = In; + return true; - case MCDisassembler_SoftFail: - *Out = In; - return true; - - case MCDisassembler_Fail: - *Out = In; - return false; - } - // llvm_unreachable("Invalid DecodeStatus!"); + case MCDisassembler_Fail: + *Out = In; + return false; + } + // llvm_unreachable("Invalid DecodeStatus!"); } // Hacky: enable all features for disassembler -uint64_t AArch64_getFeatureBits(int feature) -{ - // enable all features - return (uint64_t)-1; +uint64_t AArch64_getFeatureBits(int feature) { + // enable all features + return (uint64_t)-1; } -#define GET_SUBTARGETINFO_ENUM -#include "AArch64GenSubtargetInfo.inc" - -#include "AArch64GenDisassemblerTables.inc" - -#define GET_INSTRINFO_ENUM -#include "AArch64GenInstrInfo.inc" - -#define GET_REGINFO_ENUM -#define GET_REGINFO_MC_DESC -#include "AArch64GenRegisterInfo.inc" - #define Success MCDisassembler_Success #define Fail MCDisassembler_Fail #define SoftFail MCDisassembler_SoftFail -static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI, - const uint8_t *code, size_t code_len, - uint16_t *Size, - uint64_t Address, MCRegisterInfo *MRI) -{ - uint32_t insn; - DecodeStatus result; - size_t i; - - if (code_len < 4) { - // not enough data - *Size = 0; - return MCDisassembler_Fail; - } - - if (MI->flat_insn->detail) { - memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm64)+sizeof(cs_arm64)); - for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++) - MI->flat_insn->detail->arm64.operands[i].vector_index = -1; - } - - if (MODE_IS_BIG_ENDIAN(ud->mode)) - insn = (code[3] << 0) | (code[2] << 8) | - (code[1] << 16) | ((uint32_t) code[0] << 24); - else - insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | - (code[1] << 8) | (code[0] << 0); - - // Calling the auto-generated decoder function. - result = decodeInstruction_4(DecoderTable32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - - return result; - } - - // invalid code - MCInst_clear(MI); - *Size = 0; - - return MCDisassembler_Fail; -} - -bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info) -{ - DecodeStatus status = _getInstruction((cs_struct *)ud, instr, - code, code_len, - size, - address, (MCRegisterInfo *)info); - - return status == MCDisassembler_Success; -} - -static const unsigned FPR128DecoderTable[] = { - AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, - AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, - AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, - AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, - AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, - AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, - AArch64_Q30, AArch64_Q31 -}; - -static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = FPR128DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - if (RegNo > 15) - return Fail; - - return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); -} - -static const unsigned FPR64DecoderTable[] = { - AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, - AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, - AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, - AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, - AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, - AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, - AArch64_D30, AArch64_D31 -}; - -static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = FPR64DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned FPR32DecoderTable[] = { - AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, - AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, - AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, - AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, - AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, - AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, - AArch64_S30, AArch64_S31 -}; - -static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = FPR32DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned FPR16DecoderTable[] = { - AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, - AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, - AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, - AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, - AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, - AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, - AArch64_H30, AArch64_H31 -}; - -static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = FPR16DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned FPR8DecoderTable[] = { - AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, - AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, - AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, - AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, - AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, - AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, - AArch64_B30, AArch64_B31 -}; - -static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = FPR8DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned GPR64DecoderTable[] = { - AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, - AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, - AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, - AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, - AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, - AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, - AArch64_LR, AArch64_XZR -}; - -static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 30) - return Fail; - - Register = GPR64DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = GPR64DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = GPR64DecoderTable[RegNo]; - if (Register == AArch64_XZR) - Register = AArch64_SP; - - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned GPR32DecoderTable[] = { - AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, - AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, - AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, - AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, - AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, - AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, - AArch64_W30, AArch64_WZR -}; - -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = GPR32DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = GPR32DecoderTable[RegNo]; - if (Register == AArch64_WZR) - Register = AArch64_WSP; - - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned ZPRDecoderTable[] = { - AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, - AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, - AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, - AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15, - AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19, - AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, - AArch64_Z24, AArch64_Z25, AArch64_Z26, AArch64_Z27, - AArch64_Z28, AArch64_Z29, AArch64_Z30, AArch64_Z31 -}; - -static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = ZPRDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - if (RegNo > 15) - return Fail; - - return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - if (RegNo > 7) - return Fail; - - return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); -} - -static const unsigned ZZDecoderTable[] = { - AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, - AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, - AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, - AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, - AArch64_Z16_Z17, AArch64_Z17_Z18, AArch64_Z18_Z19, AArch64_Z19_Z20, - AArch64_Z20_Z21, AArch64_Z21_Z22, AArch64_Z22_Z23, AArch64_Z23_Z24, - AArch64_Z24_Z25, AArch64_Z25_Z26, AArch64_Z26_Z27, AArch64_Z27_Z28, - AArch64_Z28_Z29, AArch64_Z29_Z30, AArch64_Z30_Z31, AArch64_Z31_Z0 -}; - -static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = ZZDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned ZZZDecoderTable[] = { - AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, - AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, - AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, - AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, - AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, - AArch64_Z15_Z16_Z17, AArch64_Z16_Z17_Z18, AArch64_Z17_Z18_Z19, - AArch64_Z18_Z19_Z20, AArch64_Z19_Z20_Z21, AArch64_Z20_Z21_Z22, - AArch64_Z21_Z22_Z23, AArch64_Z22_Z23_Z24, AArch64_Z23_Z24_Z25, - AArch64_Z24_Z25_Z26, AArch64_Z25_Z26_Z27, AArch64_Z26_Z27_Z28, - AArch64_Z27_Z28_Z29, AArch64_Z28_Z29_Z30, AArch64_Z29_Z30_Z31, - AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1 -}; - -static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = ZZZDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned ZZZZDecoderTable[] = { - AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, - AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, - AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, - AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, - AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, - AArch64_Z15_Z16_Z17_Z18, AArch64_Z16_Z17_Z18_Z19, AArch64_Z17_Z18_Z19_Z20, - AArch64_Z18_Z19_Z20_Z21, AArch64_Z19_Z20_Z21_Z22, AArch64_Z20_Z21_Z22_Z23, - AArch64_Z21_Z22_Z23_Z24, AArch64_Z22_Z23_Z24_Z25, AArch64_Z23_Z24_Z25_Z26, - AArch64_Z24_Z25_Z26_Z27, AArch64_Z25_Z26_Z27_Z28, AArch64_Z26_Z27_Z28_Z29, - AArch64_Z27_Z28_Z29_Z30, AArch64_Z28_Z29_Z30_Z31, AArch64_Z29_Z30_Z31_Z0, - AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2 -}; - -static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = ZZZZDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned PPRDecoderTable[] = { - AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, - AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, - AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11, - AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15 -}; - -static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 15) - return Fail; - - Register = PPRDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - if (RegNo > 7) - return Fail; - - // Just reuse the PPR decode table - return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); -} - -static const unsigned VectorDecoderTable[] = { - AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, - AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, - AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, - AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, - AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, - AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, - AArch64_Q30, AArch64_Q31 -}; - -static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = VectorDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned QQDecoderTable[] = { - AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, - AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, - AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, - AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, - AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, - AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, - AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, - AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0 -}; - -static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = QQDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned QQQDecoderTable[] = { - AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, - AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, - AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, - AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, - AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, - AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, - AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, - AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, - AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, - AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, - AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1 -}; - -static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = QQQDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned QQQQDecoderTable[] = { - AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, - AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, - AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, - AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, - AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, - AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, - AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, - AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, - AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, - AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, - AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2 -}; - -static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = QQQQDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned DDDecoderTable[] = { - AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, - AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, - AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, - AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, - AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, - AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, - AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, - AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0 -}; - -static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = DDDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned DDDDecoderTable[] = { - AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, - AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, - AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, - AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, - AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, - AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, - AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, - AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, - AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, - AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, - AArch64_D30_D31_D0, AArch64_D31_D0_D1 -}; - -static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = DDDDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static const unsigned DDDDDecoderTable[] = { - AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, - AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, - AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, - AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, - AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, - AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, - AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, - AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, - AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, - AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, - AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2 -}; - -static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return Fail; - - Register = DDDDDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - // scale{5} is asserted as 1 in tblgen. - Imm |= 0x20; - MCOperand_CreateImm0(Inst, 64 - Imm); - - return Success; -} - -static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, 64 - Imm); - - return Success; -} - -static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - int64_t ImmVal = Imm; - - // Sign-extend 19-bit immediate. - if (ImmVal & (1 << (19 - 1))) - ImmVal |= ~((1LL << 19) - 1); - - MCOperand_CreateImm0(Inst, ImmVal); - - return Success; -} - -static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, (Imm >> 1) & 1); - MCOperand_CreateImm0(Inst, Imm & 1); - - return Success; -} - -static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, Imm); - - // Every system register in the encoding space is valid with the syntax - // S____, so decoding system registers always succeeds. - return Success; -} - -static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, Imm); - - return Success; -} - -static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - // This decoder exists to add the dummy Lane operand to the MCInst, which must - // be 1 in assembly but has no other real manifestation. - unsigned Rd = fieldFromInstruction_4(Insn, 0, 5); - unsigned Rn = fieldFromInstruction_4(Insn, 5, 5); - unsigned IsToVec = fieldFromInstruction_4(Insn, 16, 1); - - if (IsToVec) { - DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); - DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); - } else { - DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); - DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); - } - - // Add the lane - MCOperand_CreateImm0(Inst, 1); - - return Success; -} - -static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm, - unsigned Add) -{ - MCOperand_CreateImm0(Inst, Add - Imm); - - return Success; +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require) { + // extended from original arm module + return Require; } -static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm, - unsigned Add) -{ - MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1)); - - return Success; -} - -static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftRImm(Inst, Imm, 64); -} - -static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); -} - -static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftRImm(Inst, Imm, 32); -} - -static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); -} - -static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftRImm(Inst, Imm, 16); -} - -static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); -} - -static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftRImm(Inst, Imm, 8); -} - -static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftLImm(Inst, Imm, 64); -} - -static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftLImm(Inst, Imm, 32); -} - -static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftLImm(Inst, Imm, 16); -} - -static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - return DecodeVecShiftLImm(Inst, Imm, 8); -} - -static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, const void *Decoder) -{ - unsigned Rd = fieldFromInstruction_4(insn, 0, 5); - unsigned Rn = fieldFromInstruction_4(insn, 5, 5); - unsigned Rm = fieldFromInstruction_4(insn, 16, 5); - unsigned shiftHi = fieldFromInstruction_4(insn, 22, 2); - unsigned shiftLo = fieldFromInstruction_4(insn, 10, 6); - unsigned shift = (shiftHi << 6) | shiftLo; - - switch (MCInst_getOpcode(Inst)) { - default: - return Fail; - - case AArch64_ADDWrs: - case AArch64_ADDSWrs: - case AArch64_SUBWrs: - case AArch64_SUBSWrs: - // if shift == '11' then ReservedValue() - if (shiftHi == 0x3) - return Fail; - // Deliberate fallthrough - - case AArch64_ANDWrs: - case AArch64_ANDSWrs: - case AArch64_BICWrs: - case AArch64_BICSWrs: - case AArch64_ORRWrs: - case AArch64_ORNWrs: - case AArch64_EORWrs: - case AArch64_EONWrs: { - // if sf == '0' and imm6<5> == '1' then ReservedValue() - if (shiftLo >> 5 == 1) - return Fail; - - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - } - - case AArch64_ADDXrs: - case AArch64_ADDSXrs: - case AArch64_SUBXrs: - case AArch64_SUBSXrs: - // if shift == '11' then ReservedValue() - if (shiftHi == 0x3) - return Fail; - // Deliberate fallthrough - - case AArch64_ANDXrs: - case AArch64_ANDSXrs: - case AArch64_BICXrs: - case AArch64_BICSXrs: - case AArch64_ORRXrs: - case AArch64_ORNXrs: - case AArch64_EORXrs: - case AArch64_EONXrs: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); - break; - } - - MCOperand_CreateImm0(Inst, shift); - - return Success; -} - -static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) -{ - unsigned Rd = fieldFromInstruction_4(insn, 0, 5); - unsigned imm = fieldFromInstruction_4(insn, 5, 16); - unsigned shift = fieldFromInstruction_4(insn, 21, 2); - - shift <<= 4; - - switch (MCInst_getOpcode(Inst)) { - default: - return Fail; - - case AArch64_MOVZWi: - case AArch64_MOVNWi: - case AArch64_MOVKWi: - if (shift & (1U << 5)) - return Fail; - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - break; - - case AArch64_MOVZXi: - case AArch64_MOVNXi: - case AArch64_MOVKXi: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - break; - } - - if (MCInst_getOpcode(Inst) == AArch64_MOVKWi || - MCInst_getOpcode(Inst) == AArch64_MOVKXi) - MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0)); - - MCOperand_CreateImm0(Inst, imm); - MCOperand_CreateImm0(Inst, shift); - - return Success; -} - -static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, const void *Decoder) -{ - unsigned Rt = fieldFromInstruction_4(insn, 0, 5); - unsigned Rn = fieldFromInstruction_4(insn, 5, 5); - unsigned offset = fieldFromInstruction_4(insn, 10, 12); - - switch (MCInst_getOpcode(Inst)) { - default: - return Fail; - - case AArch64_PRFMui: - // Rt is an immediate in prefetch. - MCOperand_CreateImm0(Inst, Rt); - break; - - case AArch64_STRBBui: - case AArch64_LDRBBui: - case AArch64_LDRSBWui: - case AArch64_STRHHui: - case AArch64_LDRHHui: - case AArch64_LDRSHWui: - case AArch64_STRWui: - case AArch64_LDRWui: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDRSBXui: - case AArch64_LDRSHXui: - case AArch64_LDRSWui: - case AArch64_STRXui: - case AArch64_LDRXui: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDRQui: - case AArch64_STRQui: - DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDRDui: - case AArch64_STRDui: - DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDRSui: - case AArch64_STRSui: - DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDRHui: - case AArch64_STRHui: - DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDRBui: - case AArch64_STRBui: - DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); - break; - } - - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - - //if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) - MCOperand_CreateImm0(Inst, offset); - - return Success; -} - -static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, const void *Decoder) -{ - bool IsLoad, IsIndexed, IsFP; - unsigned Rt = fieldFromInstruction_4(insn, 0, 5); - unsigned Rn = fieldFromInstruction_4(insn, 5, 5); - int64_t offset = fieldFromInstruction_4(insn, 12, 9); - - // offset is a 9-bit signed immediate, so sign extend it to - // fill the unsigned. - if (offset & (1 << (9 - 1))) - offset |= ~((1LL << 9) - 1); - - // First operand is always the writeback to the address register, if needed. - switch (MCInst_getOpcode(Inst)) { - default: - break; - - case AArch64_LDRSBWpre: - case AArch64_LDRSHWpre: - case AArch64_STRBBpre: - case AArch64_LDRBBpre: - case AArch64_STRHHpre: - case AArch64_LDRHHpre: - case AArch64_STRWpre: - case AArch64_LDRWpre: - case AArch64_LDRSBWpost: - case AArch64_LDRSHWpost: - case AArch64_STRBBpost: - case AArch64_LDRBBpost: - case AArch64_STRHHpost: - case AArch64_LDRHHpost: - case AArch64_STRWpost: - case AArch64_LDRWpost: - case AArch64_LDRSBXpre: - case AArch64_LDRSHXpre: - case AArch64_STRXpre: - case AArch64_LDRSWpre: - case AArch64_LDRXpre: - case AArch64_LDRSBXpost: - case AArch64_LDRSHXpost: - case AArch64_STRXpost: - case AArch64_LDRSWpost: - case AArch64_LDRXpost: - case AArch64_LDRQpre: - case AArch64_STRQpre: - case AArch64_LDRQpost: - case AArch64_STRQpost: - case AArch64_LDRDpre: - case AArch64_STRDpre: - case AArch64_LDRDpost: - case AArch64_STRDpost: - case AArch64_LDRSpre: - case AArch64_STRSpre: - case AArch64_LDRSpost: - case AArch64_STRSpost: - case AArch64_LDRHpre: - case AArch64_STRHpre: - case AArch64_LDRHpost: - case AArch64_STRHpost: - case AArch64_LDRBpre: - case AArch64_STRBpre: - case AArch64_LDRBpost: - case AArch64_STRBpost: - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - break; - } - - switch (MCInst_getOpcode(Inst)) { - default: - return Fail; - - case AArch64_PRFUMi: - // Rt is an immediate in prefetch. - MCOperand_CreateImm0(Inst, Rt); - break; - - case AArch64_STURBBi: - case AArch64_LDURBBi: - case AArch64_LDURSBWi: - case AArch64_STURHHi: - case AArch64_LDURHHi: - case AArch64_LDURSHWi: - case AArch64_STURWi: - case AArch64_LDURWi: - case AArch64_LDTRSBWi: - case AArch64_LDTRSHWi: - case AArch64_STTRWi: - case AArch64_LDTRWi: - case AArch64_STTRHi: - case AArch64_LDTRHi: - case AArch64_LDTRBi: - case AArch64_STTRBi: - case AArch64_LDRSBWpre: - case AArch64_LDRSHWpre: - case AArch64_STRBBpre: - case AArch64_LDRBBpre: - case AArch64_STRHHpre: - case AArch64_LDRHHpre: - case AArch64_STRWpre: - case AArch64_LDRWpre: - case AArch64_LDRSBWpost: - case AArch64_LDRSHWpost: - case AArch64_STRBBpost: - case AArch64_LDRBBpost: - case AArch64_STRHHpost: - case AArch64_LDRHHpost: - case AArch64_STRWpost: - case AArch64_LDRWpost: - case AArch64_STLURBi: - case AArch64_STLURHi: - case AArch64_STLURWi: - case AArch64_LDAPURBi: - case AArch64_LDAPURSBWi: - case AArch64_LDAPURHi: - case AArch64_LDAPURSHWi: - case AArch64_LDAPURi: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDURSBXi: - case AArch64_LDURSHXi: - case AArch64_LDURSWi: - case AArch64_STURXi: - case AArch64_LDURXi: - case AArch64_LDTRSBXi: - case AArch64_LDTRSHXi: - case AArch64_LDTRSWi: - case AArch64_STTRXi: - case AArch64_LDTRXi: - case AArch64_LDRSBXpre: - case AArch64_LDRSHXpre: - case AArch64_STRXpre: - case AArch64_LDRSWpre: - case AArch64_LDRXpre: - case AArch64_LDRSBXpost: - case AArch64_LDRSHXpost: - case AArch64_STRXpost: - case AArch64_LDRSWpost: - case AArch64_LDRXpost: - case AArch64_LDAPURSWi: - case AArch64_LDAPURSHXi: - case AArch64_LDAPURSBXi: - case AArch64_STLURXi: - case AArch64_LDAPURXi: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDURQi: - case AArch64_STURQi: - case AArch64_LDRQpre: - case AArch64_STRQpre: - case AArch64_LDRQpost: - case AArch64_STRQpost: - DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDURDi: - case AArch64_STURDi: - case AArch64_LDRDpre: - case AArch64_STRDpre: - case AArch64_LDRDpost: - case AArch64_STRDpost: - DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDURSi: - case AArch64_STURSi: - case AArch64_LDRSpre: - case AArch64_STRSpre: - case AArch64_LDRSpost: - case AArch64_STRSpost: - DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDURHi: - case AArch64_STURHi: - case AArch64_LDRHpre: - case AArch64_STRHpre: - case AArch64_LDRHpost: - case AArch64_STRHpost: - DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_LDURBi: - case AArch64_STURBi: - case AArch64_LDRBpre: - case AArch64_STRBpre: - case AArch64_LDRBpost: - case AArch64_STRBpost: - DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); - break; - } - - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - MCOperand_CreateImm0(Inst, offset); - - IsLoad = fieldFromInstruction_4(insn, 22, 1) != 0; - IsIndexed = fieldFromInstruction_4(insn, 10, 2) != 0; - IsFP = fieldFromInstruction_4(insn, 26, 1) != 0; - - // Cannot write back to a transfer register (but xzr != sp). - if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) - return SoftFail; - - return Success; -} - -static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, const void *Decoder) -{ - unsigned Rt = fieldFromInstruction_4(insn, 0, 5); - unsigned Rn = fieldFromInstruction_4(insn, 5, 5); - unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5); - unsigned Rs = fieldFromInstruction_4(insn, 16, 5); - unsigned Opcode = MCInst_getOpcode(Inst); - - switch (Opcode) { - default: - return Fail; - - case AArch64_STLXRW: - case AArch64_STLXRB: - case AArch64_STLXRH: - case AArch64_STXRW: - case AArch64_STXRB: - case AArch64_STXRH: - DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); - // FALLTHROUGH - case AArch64_LDARW: - case AArch64_LDARB: - case AArch64_LDARH: - case AArch64_LDAXRW: - case AArch64_LDAXRB: - case AArch64_LDAXRH: - case AArch64_LDXRW: - case AArch64_LDXRB: - case AArch64_LDXRH: - case AArch64_STLRW: - case AArch64_STLRB: - case AArch64_STLRH: - case AArch64_STLLRW: - case AArch64_STLLRB: - case AArch64_STLLRH: - case AArch64_LDLARW: - case AArch64_LDLARB: - case AArch64_LDLARH: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_STLXRX: - case AArch64_STXRX: - DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); - // FALLTHROUGH - case AArch64_LDARX: - case AArch64_LDAXRX: - case AArch64_LDXRX: - case AArch64_STLRX: - case AArch64_LDLARX: - case AArch64_STLLRX: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); - break; - - case AArch64_STLXPW: - case AArch64_STXPW: - DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); - // FALLTHROUGH - case AArch64_LDAXPW: - case AArch64_LDXPW: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); - break; - - case AArch64_STLXPX: - case AArch64_STXPX: - DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); - // FALLTHROUGH - case AArch64_LDAXPX: - case AArch64_LDXPX: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); - break; - } - - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - - // You shouldn't load to the same register twice in an instruction... - if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW || - Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) && - Rt == Rt2) - return SoftFail; - - return Success; -} - -static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) -{ - unsigned Rt = fieldFromInstruction_4(insn, 0, 5); - unsigned Rn = fieldFromInstruction_4(insn, 5, 5); - unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5); - int32_t offset = fieldFromInstruction_4(insn, 15, 7); - bool IsLoad = fieldFromInstruction_4(insn, 22, 1) != 0; - unsigned Opcode = MCInst_getOpcode(Inst); - bool NeedsDisjointWritebackTransfer = false; - - // offset is a 7-bit signed immediate, so sign extend it to - // fill the unsigned. - if (offset & (1 << (7 - 1))) - offset |= ~((1LL << 7) - 1); - - // First operand is always writeback of base register. - switch (Opcode) { - default: - break; - - case AArch64_LDPXpost: - case AArch64_STPXpost: - case AArch64_LDPSWpost: - case AArch64_LDPXpre: - case AArch64_STPXpre: - case AArch64_LDPSWpre: - case AArch64_LDPWpost: - case AArch64_STPWpost: - case AArch64_LDPWpre: - case AArch64_STPWpre: - case AArch64_LDPQpost: - case AArch64_STPQpost: - case AArch64_LDPQpre: - case AArch64_STPQpre: - case AArch64_LDPDpost: - case AArch64_STPDpost: - case AArch64_LDPDpre: - case AArch64_STPDpre: - case AArch64_LDPSpost: - case AArch64_STPSpost: - case AArch64_LDPSpre: - case AArch64_STPSpre: - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - break; - } - - switch (Opcode) { - default: - return Fail; - - case AArch64_LDPXpost: - case AArch64_STPXpost: - case AArch64_LDPSWpost: - case AArch64_LDPXpre: - case AArch64_STPXpre: - case AArch64_LDPSWpre: - NeedsDisjointWritebackTransfer = true; - // Fallthrough - case AArch64_LDNPXi: - case AArch64_STNPXi: - case AArch64_LDPXi: - case AArch64_STPXi: - case AArch64_LDPSWi: - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); - break; - - case AArch64_LDPWpost: - case AArch64_STPWpost: - case AArch64_LDPWpre: - case AArch64_STPWpre: - NeedsDisjointWritebackTransfer = true; - // Fallthrough - case AArch64_LDNPWi: - case AArch64_STNPWi: - case AArch64_LDPWi: - case AArch64_STPWi: - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); - break; - - case AArch64_LDNPQi: - case AArch64_STNPQi: - case AArch64_LDPQpost: - case AArch64_STPQpost: - case AArch64_LDPQi: - case AArch64_STPQi: - case AArch64_LDPQpre: - case AArch64_STPQpre: - DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); - DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); - break; - - case AArch64_LDNPDi: - case AArch64_STNPDi: - case AArch64_LDPDpost: - case AArch64_STPDpost: - case AArch64_LDPDi: - case AArch64_STPDi: - case AArch64_LDPDpre: - case AArch64_STPDpre: - DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); - DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); - break; - - case AArch64_LDNPSi: - case AArch64_STNPSi: - case AArch64_LDPSpost: - case AArch64_STPSpost: - case AArch64_LDPSi: - case AArch64_STPSi: - case AArch64_LDPSpre: - case AArch64_STPSpre: - DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); - DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); - break; - } - - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - MCOperand_CreateImm0(Inst, offset); - - // You shouldn't load to the same register twice in an instruction... - if (IsLoad && Rt == Rt2) - return SoftFail; - - // ... or do any operation that writes-back to a transfer register. But note - // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. - if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) - return SoftFail; - - return Success; -} - -static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, const void *Decoder) -{ - unsigned Rd, Rn, Rm; - unsigned extend = fieldFromInstruction_4(insn, 10, 6); - unsigned shift = extend & 0x7; - - if (shift > 4) - return Fail; - - Rd = fieldFromInstruction_4(insn, 0, 5); - Rn = fieldFromInstruction_4(insn, 5, 5); - Rm = fieldFromInstruction_4(insn, 16, 5); - - switch (MCInst_getOpcode(Inst)) { - default: - return Fail; - - case AArch64_ADDWrx: - case AArch64_SUBWrx: - DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - - case AArch64_ADDSWrx: - case AArch64_SUBSWrx: - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - - case AArch64_ADDXrx: - case AArch64_SUBXrx: - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - - case AArch64_ADDSXrx: - case AArch64_SUBSXrx: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - - case AArch64_ADDXrx64: - case AArch64_SUBXrx64: - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); - break; - - case AArch64_SUBSXrx64: - case AArch64_ADDSXrx64: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); - break; - } - - MCOperand_CreateImm0(Inst, extend); - - return Success; -} - -static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, const void *Decoder) -{ - unsigned Rd = fieldFromInstruction_4(insn, 0, 5); - unsigned Rn = fieldFromInstruction_4(insn, 5, 5); - unsigned Datasize = fieldFromInstruction_4(insn, 31, 1); - unsigned imm; - - if (Datasize) { - if (MCInst_getOpcode(Inst) == AArch64_ANDSXri) - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - else - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); - - DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); - - imm = fieldFromInstruction_4(insn, 10, 13); - if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) - return Fail; - } else { - if (MCInst_getOpcode(Inst) == AArch64_ANDSWri) - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - else - DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); - - DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); - - imm = fieldFromInstruction_4(insn, 10, 12); - if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32)) - return Fail; - } - - MCOperand_CreateImm0(Inst, imm); - - return Success; -} - -static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) -{ - unsigned Rd = fieldFromInstruction_4(insn, 0, 5); - unsigned cmode = fieldFromInstruction_4(insn, 12, 4); - unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5; - imm |= fieldFromInstruction_4(insn, 5, 5); - - if (MCInst_getOpcode(Inst) == AArch64_MOVID) - DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); - else - DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); - - MCOperand_CreateImm0(Inst, imm); - - switch (MCInst_getOpcode(Inst)) { - default: - break; - - case AArch64_MOVIv4i16: - case AArch64_MOVIv8i16: - case AArch64_MVNIv4i16: - case AArch64_MVNIv8i16: - case AArch64_MOVIv2i32: - case AArch64_MOVIv4i32: - case AArch64_MVNIv2i32: - case AArch64_MVNIv4i32: - MCOperand_CreateImm0(Inst, (cmode & 6) << 2); - break; - - case AArch64_MOVIv2s_msl: - case AArch64_MOVIv4s_msl: - case AArch64_MVNIv2s_msl: - case AArch64_MVNIv4s_msl: - MCOperand_CreateImm0(Inst, cmode & 1 ? 0x110 : 0x108); - break; - } - - return Success; -} - -static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, const void *Decoder) -{ - unsigned Rd = fieldFromInstruction_4(insn, 0, 5); - unsigned cmode = fieldFromInstruction_4(insn, 12, 4); - unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5; - imm |= fieldFromInstruction_4(insn, 5, 5); - - // Tied operands added twice. - DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); - DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); - - MCOperand_CreateImm0(Inst, imm); - MCOperand_CreateImm0(Inst, (cmode & 6) << 2); - - return Success; -} - -static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) -{ - unsigned Rd = fieldFromInstruction_4(insn, 0, 5); - int64_t imm = fieldFromInstruction_4(insn, 5, 19) << 2; - imm |= fieldFromInstruction_4(insn, 29, 2); - - // Sign-extend the 21-bit immediate. - if (imm & (1 << (21 - 1))) - imm |= ~((1LL << 21) - 1); - - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - //if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) - MCOperand_CreateImm0(Inst, imm); - - return Success; -} - -static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) -{ - unsigned Rd = fieldFromInstruction_4(insn, 0, 5); - unsigned Rn = fieldFromInstruction_4(insn, 5, 5); - unsigned Imm = fieldFromInstruction_4(insn, 10, 14); - unsigned S = fieldFromInstruction_4(insn, 29, 1); - unsigned Datasize = fieldFromInstruction_4(insn, 31, 1); - - unsigned ShifterVal = (Imm >> 12) & 3; - unsigned ImmVal = Imm & 0xFFF; - - if (ShifterVal != 0 && ShifterVal != 1) - return Fail; - - if (Datasize) { - if (Rd == 31 && !S) - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); - else - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - } else { - if (Rd == 31 && !S) - DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); - else - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - - DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); - } - - //if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) - MCOperand_CreateImm0(Inst, ImmVal); - MCOperand_CreateImm0(Inst, 12 * ShifterVal); - - return Success; -} - -static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) -{ - int64_t imm = fieldFromInstruction_4(insn, 0, 26); - - // Sign-extend the 26-bit immediate. - if (imm & (1 << (26 - 1))) - imm |= ~((1LL << 26) - 1); - - // if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4)) - MCOperand_CreateImm0(Inst, imm); - - return Success; -} - -static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, const void *Decoder) -{ - uint32_t op1 = fieldFromInstruction_4(insn, 16, 3); - uint32_t op2 = fieldFromInstruction_4(insn, 5, 3); - uint32_t crm = fieldFromInstruction_4(insn, 8, 4); - uint32_t pstate_field = (op1 << 3) | op2; - - if ((pstate_field == AArch64PState_PAN || - pstate_field == AArch64PState_UAO) && crm > 1) - return Fail; - - MCOperand_CreateImm0(Inst, pstate_field); - MCOperand_CreateImm0(Inst, crm); - - if (lookupPStateByEncoding(pstate_field)) - return Success; - - return Fail; -} - -static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) -{ - uint32_t Rt = fieldFromInstruction_4(insn, 0, 5); - uint32_t bit = fieldFromInstruction_4(insn, 31, 1) << 5; - uint64_t dst = fieldFromInstruction_4(insn, 5, 14); - - bit |= fieldFromInstruction_4(insn, 19, 5); - - // Sign-extend 14-bit immediate. - if (dst & (1 << (14 - 1))) - dst |= ~((1LL << 14) - 1); - - if (fieldFromInstruction_4(insn, 31, 1) == 0) - DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); - else - DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); - - MCOperand_CreateImm0(Inst, bit); - - //if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4)) - MCOperand_CreateImm0(Inst, dst); - - return Success; -} - -static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder) -{ - unsigned Register; - - // Register number must be even (see CASP instruction) - if (RegNo & 0x1) - return Fail; - - Register = AArch64MCRegisterClasses[RegClassID].RegsBegin[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return Success; -} - -static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Addr, const void *Decoder) -{ - return DecodeGPRSeqPairsClassRegisterClass(Inst, - AArch64_WSeqPairsClassRegClassID, RegNo, Addr, Decoder); -} - -static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Addr, const void *Decoder) -{ - return DecodeGPRSeqPairsClassRegisterClass(Inst, - AArch64_XSeqPairsClassRegClassID, RegNo, Addr, Decoder); -} - -static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Addr, const void *Decoder) -{ - unsigned Zdn = fieldFromInstruction_4(insn, 0, 5); - unsigned imm = fieldFromInstruction_4(insn, 5, 13); - - if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) - return Fail; - - // The same (tied) operand is added twice to the instruction. - DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); - if (MCInst_getOpcode(Inst) != AArch64_DUPM_ZI) - DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); - - MCOperand_CreateImm0(Inst, imm); +#define GET_SUBTARGETINFO_ENUM +#include "AArch64GenSubtargetInfo.inc" +#include "CapstoneAArch64Module.h" - return Success; -} +static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI, + const uint8_t *code, size_t code_len, + uint16_t *Size, uint64_t Address, + MCRegisterInfo *MRI) { + uint32_t insn; + DecodeStatus result; + size_t i; -static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address, - const void *Decoder, int Bits) -{ - if (Imm & ~((1LL << Bits) - 1)) - return Fail; + MI->MRI = MRI; - // Imm is a signed immediate, so sign extend it. - if (Imm & (1 << (Bits - 1))) - Imm |= ~((1LL << Bits) - 1); + if (code_len < 4) { + // not enough data + *Size = 0; + return MCDisassembler_Fail; + } - MCOperand_CreateImm0(Inst, Imm); + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, + offsetof(cs_detail, arm64) + sizeof(cs_arm64)); + for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++) + MI->flat_insn->detail->arm64.operands[i].vector_index = -1; + } - return Success; -} + if (MODE_IS_BIG_ENDIAN(ud->mode)) + insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | + ((uint32_t)code[0] << 24); + else + insn = ((uint32_t)code[3] << 24) | (code[2] << 16) | (code[1] << 8) | + (code[0] << 0); -// Decode 8-bit signed/unsigned immediate for a given element width. -static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr, - const void *Decoder, int ElementWidth) -{ - unsigned Val = (uint8_t)Imm; - unsigned Shift = (Imm & 0x100) ? 8 : 0; + // Calling the auto-generated decoder function. + result = decodeInstruction_4(DecoderTable32, MI, insn, Address, 0, 0); + if (result != MCDisassembler_Fail && MI->Opcode) { + *Size = 4; - if (ElementWidth == 8 && Shift) - return Fail; + return result; + } - MCOperand_CreateImm0(Inst, Val); - MCOperand_CreateImm0(Inst, Shift); + result = decodeInstruction_4(DecoderTableFallback32, MI, insn, Address, 0, 0); + if (result == MCDisassembler_Success) { + *Size = 4; - return Success; -} + return result; + } -// Decode uimm4 ranged from 1-16. -static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, Imm + 1); + // invalid code + MCInst_clear(MI); + *Size = 0; - return Success; + return MCDisassembler_Fail; } -void AArch64_init(MCRegisterInfo *MRI) -{ - /* - InitMCRegisterInfo(AArch64RegDesc, 661, - RA, PC, - AArch64MCRegisterClasses, 100, - AArch64RegUnitRoots, 115, AArch64RegDiffLists, - AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, - AArch64SubRegIdxLists, 100, - AArch64SubRegIdxRanges, AArch64RegEncodingTable); - */ - - MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 661, - 0, 0, - AArch64MCRegisterClasses, 100, - 0, 0, AArch64RegDiffLists, - 0, - AArch64SubRegIdxLists, 100, - 0); +bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info) { + DecodeStatus status = _getInstruction((cs_struct *)ud, instr, code, code_len, + size, address, (MCRegisterInfo *)info); + + return status == MCDisassembler_Success; +} + +void AArch64_init(MCRegisterInfo *MRI) { + /* + InitMCRegisterInfo(AArch64RegDesc, 661, + RA, PC, + AArch64MCRegisterClasses, 100, + AArch64RegUnitRoots, 115, AArch64RegDiffLists, + AArch64LaneMaskLists, AArch64RegStrings, + AArch64RegClassStrings, AArch64SubRegIdxLists, 100, AArch64SubRegIdxRanges, + AArch64RegEncodingTable); + */ + MCRegisterInfo_InitMCRegisterInfo( + MRI, AArch64RegDesc, ARR_SIZE(AArch64RegDesc), 0, 0, + AArch64MCRegisterClasses, ARR_SIZE(AArch64MCRegisterClasses), 0, 0, + AArch64RegDiffLists, 0, AArch64SubRegIdxLists, + ARR_SIZE(AArch64SubRegIdxLists), 0); } #endif diff --git a/arch/AArch64/AArch64Disassembler.h b/arch/AArch64/AArch64Disassembler.h index 2816cbbc5c..9bfe9a5bbd 100644 --- a/arch/AArch64/AArch64Disassembler.h +++ b/arch/AArch64/AArch64Disassembler.h @@ -4,14 +4,15 @@ #ifndef CS_AARCH64_DISASSEMBLER_H #define CS_AARCH64_DISASSEMBLER_H -#include "capstone/capstone.h" -#include "../../MCRegisterInfo.h" #include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "capstone/capstone.h" void AArch64_init(MCRegisterInfo *MRI); bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); + MCInst *instr, uint16_t *size, uint64_t address, + void *info); uint64_t AArch64_getFeatureBits(int feature); diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc index 15633f7e30..18fec7ed74 100644 --- a/arch/AArch64/AArch64GenAsmWriter.inc +++ b/arch/AArch64/AArch64GenAsmWriter.inc @@ -11,9845 +11,15057 @@ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O) -{ +static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, - /* 9 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '0', 9, 0, - /* 20 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, - /* 31 */ 'l', 'd', '1', 9, 0, - /* 36 */ 't', 'r', 'n', '1', 9, 0, - /* 42 */ 'z', 'i', 'p', '1', 9, 0, - /* 48 */ 'u', 'z', 'p', '1', 9, 0, - /* 54 */ 'd', 'c', 'p', 's', '1', 9, 0, - /* 61 */ 's', 'm', '3', 's', 's', '1', 9, 0, - /* 69 */ 's', 't', '1', 9, 0, - /* 74 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, - /* 83 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '1', 9, 0, - /* 94 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, - /* 105 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '1', 9, 0, - /* 116 */ 'r', 'a', 'x', '1', 9, 0, - /* 122 */ 'r', 'e', 'v', '3', '2', 9, 0, - /* 129 */ 'l', 'd', '2', 9, 0, - /* 134 */ 's', 'h', 'a', '5', '1', '2', 'h', '2', 9, 0, - /* 144 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, - /* 154 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, - /* 162 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, - /* 170 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, - /* 180 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, - /* 188 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, - /* 196 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, - /* 204 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, - /* 212 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, - /* 220 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, - /* 228 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, - /* 236 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, - /* 244 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, - /* 252 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, - /* 260 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, - /* 270 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, - /* 278 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, - /* 286 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, - /* 294 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, - /* 304 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, - /* 312 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, - /* 320 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, - /* 328 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, - /* 337 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, - /* 346 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, - /* 355 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, - /* 364 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, - /* 374 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, - /* 384 */ 't', 'r', 'n', '2', 9, 0, - /* 390 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, - /* 398 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, - /* 406 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, - /* 414 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, - /* 424 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, - /* 435 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, - /* 444 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, - /* 453 */ 'z', 'i', 'p', '2', 9, 0, - /* 459 */ 'u', 'z', 'p', '2', 9, 0, - /* 465 */ 'd', 'c', 'p', 's', '2', 9, 0, - /* 472 */ 's', 't', '2', 9, 0, - /* 477 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, - /* 485 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, - /* 493 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, - /* 501 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, - /* 509 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '2', 9, 0, - /* 520 */ 'l', 'd', '3', 9, 0, - /* 525 */ 'e', 'o', 'r', '3', 9, 0, - /* 531 */ 'd', 'c', 'p', 's', '3', 9, 0, - /* 538 */ 's', 't', '3', 9, 0, - /* 543 */ 'r', 'e', 'v', '6', '4', 9, 0, - /* 550 */ 'l', 'd', '4', 9, 0, - /* 555 */ 's', 't', '4', 9, 0, - /* 560 */ 's', 'e', 't', 'f', '1', '6', 9, 0, - /* 568 */ 'r', 'e', 'v', '1', '6', 9, 0, - /* 575 */ 's', 'e', 't', 'f', '8', 9, 0, - /* 582 */ 's', 'm', '3', 't', 't', '1', 'a', 9, 0, - /* 591 */ 's', 'm', '3', 't', 't', '2', 'a', 9, 0, - /* 600 */ 'b', 'r', 'a', 'a', 9, 0, - /* 606 */ 'l', 'd', 'r', 'a', 'a', 9, 0, - /* 613 */ 'b', 'l', 'r', 'a', 'a', 9, 0, - /* 620 */ 's', 'a', 'b', 'a', 9, 0, - /* 626 */ 'u', 'a', 'b', 'a', 9, 0, - /* 632 */ 'p', 'a', 'c', 'd', 'a', 9, 0, - /* 639 */ 'l', 'd', 'a', 'd', 'd', 'a', 9, 0, - /* 647 */ 'f', 'a', 'd', 'd', 'a', 9, 0, - /* 654 */ 'a', 'u', 't', 'd', 'a', 9, 0, - /* 661 */ 'p', 'a', 'c', 'g', 'a', 9, 0, - /* 668 */ 'p', 'a', 'c', 'i', 'a', 9, 0, - /* 675 */ 'a', 'u', 't', 'i', 'a', 9, 0, - /* 682 */ 'b', 'r', 'k', 'a', 9, 0, - /* 688 */ 'f', 'c', 'm', 'l', 'a', 9, 0, - /* 695 */ 'f', 'm', 'l', 'a', 9, 0, - /* 701 */ 'f', 'n', 'm', 'l', 'a', 9, 0, - /* 708 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 9, 0, - /* 717 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 9, 0, - /* 726 */ 'b', 'r', 'k', 'p', 'a', 9, 0, - /* 733 */ 'c', 'a', 's', 'p', 'a', 9, 0, - /* 740 */ 's', 'w', 'p', 'a', 9, 0, - /* 746 */ 'f', 'e', 'x', 'p', 'a', 9, 0, - /* 753 */ 'l', 'd', 'c', 'l', 'r', 'a', 9, 0, - /* 761 */ 'l', 'd', 'e', 'o', 'r', 'a', 9, 0, - /* 769 */ 's', 'r', 's', 'r', 'a', 9, 0, - /* 776 */ 'u', 'r', 's', 'r', 'a', 9, 0, - /* 783 */ 's', 's', 'r', 'a', 9, 0, - /* 789 */ 'u', 's', 'r', 'a', 9, 0, - /* 795 */ 'c', 'a', 's', 'a', 9, 0, - /* 801 */ 'l', 'd', 's', 'e', 't', 'a', 9, 0, - /* 809 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, - /* 817 */ 'c', 'l', 'a', 's', 't', 'a', 9, 0, - /* 825 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 9, 0, - /* 834 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 9, 0, - /* 843 */ 'p', 'a', 'c', 'd', 'z', 'a', 9, 0, - /* 851 */ 'a', 'u', 't', 'd', 'z', 'a', 9, 0, - /* 859 */ 'p', 'a', 'c', 'i', 'z', 'a', 9, 0, - /* 867 */ 'a', 'u', 't', 'i', 'z', 'a', 9, 0, - /* 875 */ 'l', 'd', '1', 'b', 9, 0, - /* 881 */ 'l', 'd', 'f', 'f', '1', 'b', 9, 0, - /* 889 */ 'l', 'd', 'n', 'f', '1', 'b', 9, 0, - /* 897 */ 'l', 'd', 'n', 't', '1', 'b', 9, 0, - /* 905 */ 's', 't', 'n', 't', '1', 'b', 9, 0, - /* 913 */ 's', 't', '1', 'b', 9, 0, - /* 919 */ 's', 'm', '3', 't', 't', '1', 'b', 9, 0, - /* 928 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, - /* 936 */ 'l', 'd', '2', 'b', 9, 0, - /* 942 */ 's', 't', '2', 'b', 9, 0, - /* 948 */ 's', 'm', '3', 't', 't', '2', 'b', 9, 0, - /* 957 */ 'l', 'd', '3', 'b', 9, 0, - /* 963 */ 's', 't', '3', 'b', 9, 0, - /* 969 */ 'l', 'd', '4', 'b', 9, 0, - /* 975 */ 's', 't', '4', 'b', 9, 0, - /* 981 */ 'l', 'd', 'a', 'd', 'd', 'a', 'b', 9, 0, - /* 990 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'b', 9, 0, - /* 1000 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'b', 9, 0, - /* 1010 */ 's', 'w', 'p', 'a', 'b', 9, 0, - /* 1017 */ 'b', 'r', 'a', 'b', 9, 0, - /* 1023 */ 'l', 'd', 'r', 'a', 'b', 9, 0, - /* 1030 */ 'b', 'l', 'r', 'a', 'b', 9, 0, - /* 1037 */ 'l', 'd', 'c', 'l', 'r', 'a', 'b', 9, 0, - /* 1046 */ 'l', 'd', 'e', 'o', 'r', 'a', 'b', 9, 0, - /* 1055 */ 'c', 'a', 's', 'a', 'b', 9, 0, - /* 1062 */ 'l', 'd', 's', 'e', 't', 'a', 'b', 9, 0, - /* 1071 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'b', 9, 0, - /* 1081 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'b', 9, 0, - /* 1091 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, - /* 1100 */ 's', 'q', 'd', 'e', 'c', 'b', 9, 0, - /* 1108 */ 'u', 'q', 'd', 'e', 'c', 'b', 9, 0, - /* 1116 */ 's', 'q', 'i', 'n', 'c', 'b', 9, 0, - /* 1124 */ 'u', 'q', 'i', 'n', 'c', 'b', 9, 0, - /* 1132 */ 'p', 'a', 'c', 'd', 'b', 9, 0, - /* 1139 */ 'l', 'd', 'a', 'd', 'd', 'b', 9, 0, - /* 1147 */ 'a', 'u', 't', 'd', 'b', 9, 0, - /* 1154 */ 'p', 'r', 'f', 'b', 9, 0, - /* 1160 */ 'p', 'a', 'c', 'i', 'b', 9, 0, - /* 1167 */ 'a', 'u', 't', 'i', 'b', 9, 0, - /* 1174 */ 'b', 'r', 'k', 'b', 9, 0, - /* 1180 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'b', 9, 0, - /* 1190 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, - /* 1201 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, - /* 1212 */ 's', 'w', 'p', 'a', 'l', 'b', 9, 0, - /* 1220 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'b', 9, 0, - /* 1230 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'b', 9, 0, - /* 1240 */ 'c', 'a', 's', 'a', 'l', 'b', 9, 0, - /* 1248 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'b', 9, 0, - /* 1258 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, - /* 1269 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, - /* 1280 */ 'l', 'd', 'a', 'd', 'd', 'l', 'b', 9, 0, - /* 1289 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'b', 9, 0, - /* 1299 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'b', 9, 0, - /* 1309 */ 's', 'w', 'p', 'l', 'b', 9, 0, - /* 1316 */ 'l', 'd', 'c', 'l', 'r', 'l', 'b', 9, 0, - /* 1325 */ 'l', 'd', 'e', 'o', 'r', 'l', 'b', 9, 0, - /* 1334 */ 'c', 'a', 's', 'l', 'b', 9, 0, - /* 1341 */ 'l', 'd', 's', 'e', 't', 'l', 'b', 9, 0, - /* 1350 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'b', 9, 0, - /* 1360 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'b', 9, 0, - /* 1370 */ 'd', 'm', 'b', 9, 0, - /* 1375 */ 'l', 'd', 's', 'm', 'i', 'n', 'b', 9, 0, - /* 1384 */ 'l', 'd', 'u', 'm', 'i', 'n', 'b', 9, 0, - /* 1393 */ 'b', 'r', 'k', 'p', 'b', 9, 0, - /* 1400 */ 's', 'w', 'p', 'b', 9, 0, - /* 1406 */ 'l', 'd', '1', 'r', 'q', 'b', 9, 0, - /* 1414 */ 'l', 'd', '1', 'r', 'b', 9, 0, - /* 1421 */ 'l', 'd', 'a', 'r', 'b', 9, 0, - /* 1428 */ 'l', 'd', 'l', 'a', 'r', 'b', 9, 0, - /* 1436 */ 'l', 'd', 'r', 'b', 9, 0, - /* 1442 */ 'l', 'd', 'c', 'l', 'r', 'b', 9, 0, - /* 1450 */ 's', 't', 'l', 'l', 'r', 'b', 9, 0, - /* 1458 */ 's', 't', 'l', 'r', 'b', 9, 0, - /* 1465 */ 'l', 'd', 'e', 'o', 'r', 'b', 9, 0, - /* 1473 */ 'l', 'd', 'a', 'p', 'r', 'b', 9, 0, - /* 1481 */ 'l', 'd', 't', 'r', 'b', 9, 0, - /* 1488 */ 's', 't', 'r', 'b', 9, 0, - /* 1494 */ 's', 't', 't', 'r', 'b', 9, 0, - /* 1501 */ 'l', 'd', 'u', 'r', 'b', 9, 0, - /* 1508 */ 's', 't', 'l', 'u', 'r', 'b', 9, 0, - /* 1516 */ 'l', 'd', 'a', 'p', 'u', 'r', 'b', 9, 0, - /* 1525 */ 's', 't', 'u', 'r', 'b', 9, 0, - /* 1532 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, - /* 1540 */ 'l', 'd', 'x', 'r', 'b', 9, 0, - /* 1547 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, - /* 1555 */ 's', 't', 'x', 'r', 'b', 9, 0, - /* 1562 */ 'l', 'd', '1', 's', 'b', 9, 0, - /* 1569 */ 'l', 'd', 'f', 'f', '1', 's', 'b', 9, 0, - /* 1578 */ 'l', 'd', 'n', 'f', '1', 's', 'b', 9, 0, - /* 1587 */ 'c', 'a', 's', 'b', 9, 0, - /* 1593 */ 'd', 's', 'b', 9, 0, - /* 1598 */ 'i', 's', 'b', 9, 0, - /* 1603 */ 'f', 'm', 's', 'b', 9, 0, - /* 1609 */ 'f', 'n', 'm', 's', 'b', 9, 0, - /* 1616 */ 'l', 'd', '1', 'r', 's', 'b', 9, 0, - /* 1624 */ 'l', 'd', 'r', 's', 'b', 9, 0, - /* 1631 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, - /* 1639 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, - /* 1647 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'b', 9, 0, - /* 1657 */ 't', 's', 'b', 9, 0, - /* 1662 */ 'l', 'd', 's', 'e', 't', 'b', 9, 0, - /* 1670 */ 'c', 'n', 't', 'b', 9, 0, - /* 1676 */ 'c', 'l', 'a', 's', 't', 'b', 9, 0, - /* 1684 */ 's', 'x', 't', 'b', 9, 0, - /* 1690 */ 'u', 'x', 't', 'b', 9, 0, - /* 1696 */ 'f', 's', 'u', 'b', 9, 0, - /* 1702 */ 's', 'h', 's', 'u', 'b', 9, 0, - /* 1709 */ 'u', 'h', 's', 'u', 'b', 9, 0, - /* 1716 */ 'f', 'm', 's', 'u', 'b', 9, 0, - /* 1723 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, - /* 1731 */ 's', 'q', 's', 'u', 'b', 9, 0, - /* 1738 */ 'u', 'q', 's', 'u', 'b', 9, 0, - /* 1745 */ 'r', 'e', 'v', 'b', 9, 0, - /* 1751 */ 'l', 'd', 's', 'm', 'a', 'x', 'b', 9, 0, - /* 1760 */ 'l', 'd', 'u', 'm', 'a', 'x', 'b', 9, 0, - /* 1769 */ 'p', 'a', 'c', 'd', 'z', 'b', 9, 0, - /* 1777 */ 'a', 'u', 't', 'd', 'z', 'b', 9, 0, - /* 1785 */ 'p', 'a', 'c', 'i', 'z', 'b', 9, 0, - /* 1793 */ 'a', 'u', 't', 'i', 'z', 'b', 9, 0, - /* 1801 */ 's', 'h', 'a', '1', 'c', 9, 0, - /* 1808 */ 's', 'b', 'c', 9, 0, - /* 1813 */ 'a', 'd', 'c', 9, 0, - /* 1818 */ 'b', 'i', 'c', 9, 0, - /* 1823 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, - /* 1831 */ 'a', 'e', 's', 'm', 'c', 9, 0, - /* 1838 */ 'c', 's', 'i', 'n', 'c', 9, 0, - /* 1845 */ 'h', 'v', 'c', 9, 0, - /* 1850 */ 's', 'v', 'c', 9, 0, - /* 1855 */ 'l', 'd', '1', 'd', 9, 0, - /* 1861 */ 'l', 'd', 'f', 'f', '1', 'd', 9, 0, - /* 1869 */ 'l', 'd', 'n', 'f', '1', 'd', 9, 0, - /* 1877 */ 'l', 'd', 'n', 't', '1', 'd', 9, 0, - /* 1885 */ 's', 't', 'n', 't', '1', 'd', 9, 0, - /* 1893 */ 's', 't', '1', 'd', 9, 0, - /* 1899 */ 'l', 'd', '2', 'd', 9, 0, - /* 1905 */ 's', 't', '2', 'd', 9, 0, - /* 1911 */ 'l', 'd', '3', 'd', 9, 0, - /* 1917 */ 's', 't', '3', 'd', 9, 0, - /* 1923 */ 'l', 'd', '4', 'd', 9, 0, - /* 1929 */ 's', 't', '4', 'd', 9, 0, - /* 1935 */ 'f', 'm', 'a', 'd', 9, 0, - /* 1941 */ 'f', 'n', 'm', 'a', 'd', 9, 0, - /* 1948 */ 'f', 't', 'm', 'a', 'd', 9, 0, - /* 1955 */ 'f', 'a', 'b', 'd', 9, 0, - /* 1961 */ 's', 'a', 'b', 'd', 9, 0, - /* 1967 */ 'u', 'a', 'b', 'd', 9, 0, - /* 1973 */ 'x', 'p', 'a', 'c', 'd', 9, 0, - /* 1980 */ 's', 'q', 'd', 'e', 'c', 'd', 9, 0, - /* 1988 */ 'u', 'q', 'd', 'e', 'c', 'd', 9, 0, - /* 1996 */ 's', 'q', 'i', 'n', 'c', 'd', 9, 0, - /* 2004 */ 'u', 'q', 'i', 'n', 'c', 'd', 9, 0, - /* 2012 */ 'f', 'c', 'a', 'd', 'd', 9, 0, - /* 2019 */ 'l', 'd', 'a', 'd', 'd', 9, 0, - /* 2026 */ 'f', 'a', 'd', 'd', 9, 0, - /* 2032 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, - /* 2040 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, - /* 2048 */ 's', 'h', 'a', 'd', 'd', 9, 0, - /* 2055 */ 'u', 'h', 'a', 'd', 'd', 9, 0, - /* 2062 */ 'f', 'm', 'a', 'd', 'd', 9, 0, - /* 2069 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, - /* 2077 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, - /* 2085 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, - /* 2093 */ 'p', 'r', 'f', 'd', 9, 0, - /* 2099 */ 'n', 'a', 'n', 'd', 9, 0, - /* 2105 */ 'l', 'd', '1', 'r', 'q', 'd', 9, 0, - /* 2113 */ 'l', 'd', '1', 'r', 'd', 9, 0, - /* 2120 */ 'a', 's', 'r', 'd', 9, 0, - /* 2126 */ 'a', 'e', 's', 'd', 9, 0, - /* 2132 */ 'c', 'n', 't', 'd', 9, 0, - /* 2138 */ 's', 'm', '4', 'e', 9, 0, - /* 2144 */ 's', 'p', 'l', 'i', 'c', 'e', 9, 0, - /* 2152 */ 'f', 'a', 'c', 'g', 'e', 9, 0, - /* 2159 */ 'f', 'c', 'm', 'g', 'e', 9, 0, - /* 2166 */ 'c', 'm', 'p', 'g', 'e', 9, 0, - /* 2173 */ 'f', 's', 'c', 'a', 'l', 'e', 9, 0, - /* 2181 */ 'w', 'h', 'i', 'l', 'e', 'l', 'e', 9, 0, - /* 2190 */ 'f', 'c', 'm', 'l', 'e', 9, 0, - /* 2197 */ 'c', 'm', 'p', 'l', 'e', 9, 0, - /* 2204 */ 'f', 'c', 'm', 'n', 'e', 9, 0, - /* 2211 */ 'c', 't', 'e', 'r', 'm', 'n', 'e', 9, 0, - /* 2220 */ 'c', 'm', 'p', 'n', 'e', 9, 0, - /* 2227 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, - /* 2235 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, - /* 2243 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, - /* 2251 */ 'f', 'c', 'm', 'p', 'e', 9, 0, - /* 2258 */ 'a', 'e', 's', 'e', 9, 0, - /* 2264 */ 'p', 'f', 'a', 'l', 's', 'e', 9, 0, - /* 2272 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, - /* 2281 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, - /* 2290 */ 'p', 't', 'r', 'u', 'e', 9, 0, - /* 2297 */ 'b', 'i', 'f', 9, 0, - /* 2302 */ 'r', 'm', 'i', 'f', 9, 0, - /* 2308 */ 's', 'c', 'v', 't', 'f', 9, 0, - /* 2315 */ 'u', 'c', 'v', 't', 'f', 9, 0, - /* 2322 */ 'f', 'n', 'e', 'g', 9, 0, - /* 2328 */ 's', 'q', 'n', 'e', 'g', 9, 0, - /* 2335 */ 'c', 's', 'n', 'e', 'g', 9, 0, - /* 2342 */ 's', 'h', 'a', '1', 'h', 9, 0, - /* 2349 */ 'l', 'd', '1', 'h', 9, 0, - /* 2355 */ 'l', 'd', 'f', 'f', '1', 'h', 9, 0, - /* 2363 */ 'l', 'd', 'n', 'f', '1', 'h', 9, 0, - /* 2371 */ 'l', 'd', 'n', 't', '1', 'h', 9, 0, - /* 2379 */ 's', 't', 'n', 't', '1', 'h', 9, 0, - /* 2387 */ 's', 't', '1', 'h', 9, 0, - /* 2393 */ 's', 'h', 'a', '5', '1', '2', 'h', 9, 0, - /* 2402 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, - /* 2410 */ 'l', 'd', '2', 'h', 9, 0, - /* 2416 */ 's', 't', '2', 'h', 9, 0, - /* 2422 */ 'l', 'd', '3', 'h', 9, 0, - /* 2428 */ 's', 't', '3', 'h', 9, 0, - /* 2434 */ 'l', 'd', '4', 'h', 9, 0, - /* 2440 */ 's', 't', '4', 'h', 9, 0, - /* 2446 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, - /* 2455 */ 'l', 'd', 'a', 'd', 'd', 'a', 'h', 9, 0, - /* 2464 */ 's', 'q', 'r', 'd', 'm', 'l', 'a', 'h', 9, 0, - /* 2474 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'h', 9, 0, - /* 2484 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'h', 9, 0, - /* 2494 */ 's', 'w', 'p', 'a', 'h', 9, 0, - /* 2501 */ 'l', 'd', 'c', 'l', 'r', 'a', 'h', 9, 0, - /* 2510 */ 'l', 'd', 'e', 'o', 'r', 'a', 'h', 9, 0, - /* 2519 */ 'c', 'a', 's', 'a', 'h', 9, 0, - /* 2526 */ 'l', 'd', 's', 'e', 't', 'a', 'h', 9, 0, - /* 2535 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'h', 9, 0, - /* 2545 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'h', 9, 0, - /* 2555 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, - /* 2564 */ 's', 'q', 'd', 'e', 'c', 'h', 9, 0, - /* 2572 */ 'u', 'q', 'd', 'e', 'c', 'h', 9, 0, - /* 2580 */ 's', 'q', 'i', 'n', 'c', 'h', 9, 0, - /* 2588 */ 'u', 'q', 'i', 'n', 'c', 'h', 9, 0, - /* 2596 */ 'l', 'd', 'a', 'd', 'd', 'h', 9, 0, - /* 2604 */ 'p', 'r', 'f', 'h', 9, 0, - /* 2610 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'h', 9, 0, - /* 2620 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, - /* 2631 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, - /* 2642 */ 's', 'w', 'p', 'a', 'l', 'h', 9, 0, - /* 2650 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'h', 9, 0, - /* 2660 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'h', 9, 0, - /* 2670 */ 'c', 'a', 's', 'a', 'l', 'h', 9, 0, - /* 2678 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'h', 9, 0, - /* 2688 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, - /* 2699 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, - /* 2710 */ 'l', 'd', 'a', 'd', 'd', 'l', 'h', 9, 0, - /* 2719 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'h', 9, 0, - /* 2729 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'h', 9, 0, - /* 2739 */ 's', 'w', 'p', 'l', 'h', 9, 0, - /* 2746 */ 'l', 'd', 'c', 'l', 'r', 'l', 'h', 9, 0, - /* 2755 */ 'l', 'd', 'e', 'o', 'r', 'l', 'h', 9, 0, - /* 2764 */ 'c', 'a', 's', 'l', 'h', 9, 0, - /* 2771 */ 'l', 'd', 's', 'e', 't', 'l', 'h', 9, 0, - /* 2780 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, - /* 2789 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, - /* 2799 */ 's', 'm', 'u', 'l', 'h', 9, 0, - /* 2806 */ 'u', 'm', 'u', 'l', 'h', 9, 0, - /* 2813 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'h', 9, 0, - /* 2823 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'h', 9, 0, - /* 2833 */ 'l', 'd', 's', 'm', 'i', 'n', 'h', 9, 0, - /* 2842 */ 'l', 'd', 'u', 'm', 'i', 'n', 'h', 9, 0, - /* 2851 */ 's', 'w', 'p', 'h', 9, 0, - /* 2857 */ 'l', 'd', '1', 'r', 'q', 'h', 9, 0, - /* 2865 */ 'l', 'd', '1', 'r', 'h', 9, 0, - /* 2872 */ 'l', 'd', 'a', 'r', 'h', 9, 0, - /* 2879 */ 'l', 'd', 'l', 'a', 'r', 'h', 9, 0, - /* 2887 */ 'l', 'd', 'r', 'h', 9, 0, - /* 2893 */ 'l', 'd', 'c', 'l', 'r', 'h', 9, 0, - /* 2901 */ 's', 't', 'l', 'l', 'r', 'h', 9, 0, - /* 2909 */ 's', 't', 'l', 'r', 'h', 9, 0, - /* 2916 */ 'l', 'd', 'e', 'o', 'r', 'h', 9, 0, - /* 2924 */ 'l', 'd', 'a', 'p', 'r', 'h', 9, 0, - /* 2932 */ 'l', 'd', 't', 'r', 'h', 9, 0, - /* 2939 */ 's', 't', 'r', 'h', 9, 0, - /* 2945 */ 's', 't', 't', 'r', 'h', 9, 0, - /* 2952 */ 'l', 'd', 'u', 'r', 'h', 9, 0, - /* 2959 */ 's', 't', 'l', 'u', 'r', 'h', 9, 0, - /* 2967 */ 'l', 'd', 'a', 'p', 'u', 'r', 'h', 9, 0, - /* 2976 */ 's', 't', 'u', 'r', 'h', 9, 0, - /* 2983 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, - /* 2991 */ 'l', 'd', 'x', 'r', 'h', 9, 0, - /* 2998 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, - /* 3006 */ 's', 't', 'x', 'r', 'h', 9, 0, - /* 3013 */ 'l', 'd', '1', 's', 'h', 9, 0, - /* 3020 */ 'l', 'd', 'f', 'f', '1', 's', 'h', 9, 0, - /* 3029 */ 'l', 'd', 'n', 'f', '1', 's', 'h', 9, 0, - /* 3038 */ 'c', 'a', 's', 'h', 9, 0, - /* 3044 */ 's', 'q', 'r', 'd', 'm', 'l', 's', 'h', 9, 0, - /* 3054 */ 'l', 'd', '1', 'r', 's', 'h', 9, 0, - /* 3062 */ 'l', 'd', 'r', 's', 'h', 9, 0, - /* 3069 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, - /* 3077 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, - /* 3085 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'h', 9, 0, - /* 3095 */ 'l', 'd', 's', 'e', 't', 'h', 9, 0, - /* 3103 */ 'c', 'n', 't', 'h', 9, 0, - /* 3109 */ 's', 'x', 't', 'h', 9, 0, - /* 3115 */ 'u', 'x', 't', 'h', 9, 0, - /* 3121 */ 'r', 'e', 'v', 'h', 9, 0, - /* 3127 */ 'l', 'd', 's', 'm', 'a', 'x', 'h', 9, 0, - /* 3136 */ 'l', 'd', 'u', 'm', 'a', 'x', 'h', 9, 0, - /* 3145 */ 'x', 'p', 'a', 'c', 'i', 9, 0, - /* 3152 */ 'p', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, - /* 3161 */ 's', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, - /* 3170 */ 'u', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, - /* 3179 */ 'c', 'm', 'h', 'i', 9, 0, - /* 3185 */ 'c', 'm', 'p', 'h', 'i', 9, 0, - /* 3192 */ 's', 'l', 'i', 9, 0, - /* 3197 */ 'm', 'v', 'n', 'i', 9, 0, - /* 3203 */ 's', 'r', 'i', 9, 0, - /* 3208 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, - /* 3216 */ 'm', 'o', 'v', 'i', 9, 0, - /* 3222 */ 'b', 'r', 'k', 9, 0, - /* 3227 */ 'm', 'o', 'v', 'k', 9, 0, - /* 3233 */ 's', 'a', 'b', 'a', 'l', 9, 0, - /* 3240 */ 'u', 'a', 'b', 'a', 'l', 9, 0, - /* 3247 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 9, 0, - /* 3256 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, - /* 3265 */ 's', 'm', 'l', 'a', 'l', 9, 0, - /* 3272 */ 'u', 'm', 'l', 'a', 'l', 9, 0, - /* 3279 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 9, 0, - /* 3289 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 9, 0, - /* 3299 */ 'c', 'a', 's', 'p', 'a', 'l', 9, 0, - /* 3307 */ 's', 'w', 'p', 'a', 'l', 9, 0, - /* 3314 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 9, 0, - /* 3323 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 9, 0, - /* 3332 */ 'c', 'a', 's', 'a', 'l', 9, 0, - /* 3339 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 9, 0, - /* 3348 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 9, 0, - /* 3358 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 9, 0, - /* 3368 */ 't', 'b', 'l', 9, 0, - /* 3373 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, - /* 3381 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, - /* 3389 */ 's', 's', 'u', 'b', 'l', 9, 0, - /* 3396 */ 'u', 's', 'u', 'b', 'l', 9, 0, - /* 3403 */ 's', 'a', 'b', 'd', 'l', 9, 0, - /* 3410 */ 'u', 'a', 'b', 'd', 'l', 9, 0, - /* 3417 */ 'l', 'd', 'a', 'd', 'd', 'l', 9, 0, - /* 3425 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, - /* 3433 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, - /* 3441 */ 's', 'a', 'd', 'd', 'l', 9, 0, - /* 3448 */ 'u', 'a', 'd', 'd', 'l', 9, 0, - /* 3455 */ 'f', 'c', 's', 'e', 'l', 9, 0, - /* 3462 */ 'f', 't', 's', 's', 'e', 'l', 9, 0, - /* 3470 */ 's', 'q', 's', 'h', 'l', 9, 0, - /* 3477 */ 'u', 'q', 's', 'h', 'l', 9, 0, - /* 3484 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, - /* 3492 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, - /* 3500 */ 's', 'r', 's', 'h', 'l', 9, 0, - /* 3507 */ 'u', 'r', 's', 'h', 'l', 9, 0, - /* 3514 */ 's', 's', 'h', 'l', 9, 0, - /* 3520 */ 'u', 's', 'h', 'l', 9, 0, - /* 3526 */ 's', 's', 'h', 'l', 'l', 9, 0, - /* 3533 */ 'u', 's', 'h', 'l', 'l', 9, 0, - /* 3540 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, - /* 3549 */ 'p', 'm', 'u', 'l', 'l', 9, 0, - /* 3556 */ 's', 'm', 'u', 'l', 'l', 9, 0, - /* 3563 */ 'u', 'm', 'u', 'l', 'l', 9, 0, - /* 3570 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 9, 0, - /* 3579 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 9, 0, - /* 3588 */ 'a', 'd', 'd', 'p', 'l', 9, 0, - /* 3595 */ 'c', 'a', 's', 'p', 'l', 9, 0, - /* 3602 */ 's', 'w', 'p', 'l', 9, 0, - /* 3608 */ 'l', 'd', 'c', 'l', 'r', 'l', 9, 0, - /* 3616 */ 'l', 'd', 'e', 'o', 'r', 'l', 9, 0, - /* 3624 */ 'c', 'a', 's', 'l', 9, 0, - /* 3630 */ 'b', 's', 'l', 9, 0, - /* 3635 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, - /* 3644 */ 's', 'm', 'l', 's', 'l', 9, 0, - /* 3651 */ 'u', 'm', 'l', 's', 'l', 9, 0, - /* 3658 */ 's', 'y', 's', 'l', 9, 0, - /* 3664 */ 'l', 'd', 's', 'e', 't', 'l', 9, 0, - /* 3672 */ 'f', 'c', 'v', 't', 'l', 9, 0, - /* 3679 */ 'f', 'm', 'u', 'l', 9, 0, - /* 3685 */ 'f', 'n', 'm', 'u', 'l', 9, 0, - /* 3692 */ 'p', 'm', 'u', 'l', 9, 0, - /* 3698 */ 'f', 't', 's', 'm', 'u', 'l', 9, 0, - /* 3706 */ 'a', 'd', 'd', 'v', 'l', 9, 0, - /* 3713 */ 'r', 'd', 'v', 'l', 9, 0, - /* 3719 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 9, 0, - /* 3728 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 9, 0, - /* 3737 */ 's', 'h', 'a', '1', 'm', 9, 0, - /* 3744 */ 's', 'b', 'f', 'm', 9, 0, - /* 3750 */ 'u', 'b', 'f', 'm', 9, 0, - /* 3756 */ 'p', 'r', 'f', 'm', 9, 0, - /* 3762 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, - /* 3770 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, - /* 3778 */ 'd', 'u', 'p', 'm', 9, 0, - /* 3784 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, - /* 3792 */ 'p', 'r', 'f', 'u', 'm', 9, 0, - /* 3799 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, - /* 3807 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, - /* 3815 */ 'f', 'm', 'i', 'n', 9, 0, - /* 3821 */ 'l', 'd', 's', 'm', 'i', 'n', 9, 0, - /* 3829 */ 'l', 'd', 'u', 'm', 'i', 'n', 9, 0, - /* 3837 */ 'b', 'r', 'k', 'n', 9, 0, - /* 3843 */ 'c', 'c', 'm', 'n', 9, 0, - /* 3849 */ 'e', 'o', 'n', 9, 0, - /* 3854 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, - /* 3862 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, - /* 3870 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, - /* 3879 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, - /* 3888 */ 'o', 'r', 'n', 9, 0, - /* 3893 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, - /* 3901 */ 'f', 'c', 'v', 't', 'n', 9, 0, - /* 3908 */ 's', 'q', 'x', 't', 'n', 9, 0, - /* 3915 */ 'u', 'q', 'x', 't', 'n', 9, 0, - /* 3922 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, - /* 3931 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, - /* 3941 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, - /* 3949 */ 'm', 'o', 'v', 'n', 9, 0, - /* 3955 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, - /* 3963 */ 'w', 'h', 'i', 'l', 'e', 'l', 'o', 9, 0, - /* 3972 */ 'p', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, - /* 3981 */ 's', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, - /* 3990 */ 'u', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, - /* 3999 */ 'c', 'm', 'p', 'l', 'o', 9, 0, - /* 4006 */ 'f', 'c', 'm', 'u', 'o', 9, 0, - /* 4013 */ 's', 'h', 'a', '1', 'p', 9, 0, - /* 4020 */ 's', 'q', 'd', 'e', 'c', 'p', 9, 0, - /* 4028 */ 'u', 'q', 'd', 'e', 'c', 'p', 9, 0, - /* 4036 */ 's', 'q', 'i', 'n', 'c', 'p', 9, 0, - /* 4044 */ 'u', 'q', 'i', 'n', 'c', 'p', 9, 0, - /* 4052 */ 'f', 'a', 'd', 'd', 'p', 9, 0, - /* 4059 */ 'l', 'd', 'p', 9, 0, - /* 4064 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, - /* 4072 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, - /* 4080 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, - /* 4088 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, - /* 4096 */ 'f', 'c', 'c', 'm', 'p', 9, 0, - /* 4103 */ 'f', 'c', 'm', 'p', 9, 0, - /* 4109 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, - /* 4118 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, - /* 4127 */ 'l', 'd', 'n', 'p', 9, 0, - /* 4133 */ 'f', 'm', 'i', 'n', 'p', 9, 0, - /* 4140 */ 's', 'm', 'i', 'n', 'p', 9, 0, - /* 4147 */ 'u', 'm', 'i', 'n', 'p', 9, 0, - /* 4154 */ 's', 't', 'n', 'p', 9, 0, - /* 4160 */ 'a', 'd', 'r', 'p', 9, 0, - /* 4166 */ 'c', 'a', 's', 'p', 9, 0, - /* 4172 */ 'c', 'n', 't', 'p', 9, 0, - /* 4178 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, - /* 4186 */ 's', 't', 'p', 9, 0, - /* 4191 */ 'f', 'd', 'u', 'p', 9, 0, - /* 4197 */ 's', 'w', 'p', 9, 0, - /* 4202 */ 'l', 'd', 'a', 'x', 'p', 9, 0, - /* 4209 */ 'f', 'm', 'a', 'x', 'p', 9, 0, - /* 4216 */ 's', 'm', 'a', 'x', 'p', 9, 0, - /* 4223 */ 'u', 'm', 'a', 'x', 'p', 9, 0, - /* 4230 */ 'l', 'd', 'x', 'p', 9, 0, - /* 4236 */ 's', 't', 'l', 'x', 'p', 9, 0, - /* 4243 */ 's', 't', 'x', 'p', 9, 0, - /* 4249 */ 'f', 'c', 'm', 'e', 'q', 9, 0, - /* 4256 */ 'c', 't', 'e', 'r', 'm', 'e', 'q', 9, 0, - /* 4265 */ 'c', 'm', 'p', 'e', 'q', 9, 0, - /* 4272 */ 'l', 'd', '1', 'r', 9, 0, - /* 4278 */ 'l', 'd', '2', 'r', 9, 0, - /* 4284 */ 'l', 'd', '3', 'r', 9, 0, - /* 4290 */ 'l', 'd', '4', 'r', 9, 0, - /* 4296 */ 'l', 'd', 'a', 'r', 9, 0, - /* 4302 */ 'l', 'd', 'l', 'a', 'r', 9, 0, - /* 4309 */ 'x', 'a', 'r', 9, 0, - /* 4314 */ 'f', 's', 'u', 'b', 'r', 9, 0, - /* 4321 */ 'a', 'd', 'r', 9, 0, - /* 4326 */ 'l', 'd', 'r', 9, 0, - /* 4331 */ 'r', 'd', 'f', 'f', 'r', 9, 0, - /* 4338 */ 'w', 'r', 'f', 'f', 'r', 9, 0, - /* 4345 */ 's', 'r', 's', 'h', 'r', 9, 0, - /* 4352 */ 'u', 'r', 's', 'h', 'r', 9, 0, - /* 4359 */ 's', 's', 'h', 'r', 9, 0, - /* 4365 */ 'u', 's', 'h', 'r', 9, 0, - /* 4371 */ 'b', 'l', 'r', 9, 0, - /* 4376 */ 'l', 'd', 'c', 'l', 'r', 9, 0, - /* 4383 */ 's', 't', 'l', 'l', 'r', 9, 0, - /* 4390 */ 'l', 's', 'l', 'r', 9, 0, - /* 4396 */ 's', 't', 'l', 'r', 9, 0, - /* 4402 */ 'l', 'd', 'e', 'o', 'r', 9, 0, - /* 4409 */ 'n', 'o', 'r', 9, 0, - /* 4414 */ 'r', 'o', 'r', 9, 0, - /* 4419 */ 'l', 'd', 'a', 'p', 'r', 9, 0, - /* 4426 */ 'o', 'r', 'r', 9, 0, - /* 4431 */ 'a', 's', 'r', 'r', 9, 0, - /* 4437 */ 'l', 's', 'r', 'r', 9, 0, - /* 4443 */ 'a', 's', 'r', 9, 0, - /* 4448 */ 'l', 's', 'r', 9, 0, - /* 4453 */ 'm', 's', 'r', 9, 0, - /* 4458 */ 'i', 'n', 's', 'r', 9, 0, - /* 4464 */ 'l', 'd', 't', 'r', 9, 0, - /* 4470 */ 's', 't', 'r', 9, 0, - /* 4475 */ 's', 't', 't', 'r', 9, 0, - /* 4481 */ 'e', 'x', 't', 'r', 9, 0, - /* 4487 */ 'l', 'd', 'u', 'r', 9, 0, - /* 4493 */ 's', 't', 'l', 'u', 'r', 9, 0, - /* 4500 */ 'l', 'd', 'a', 'p', 'u', 'r', 9, 0, - /* 4508 */ 's', 't', 'u', 'r', 9, 0, - /* 4514 */ 'f', 'd', 'i', 'v', 'r', 9, 0, - /* 4521 */ 's', 'd', 'i', 'v', 'r', 9, 0, - /* 4528 */ 'u', 'd', 'i', 'v', 'r', 9, 0, - /* 4535 */ 'l', 'd', 'a', 'x', 'r', 9, 0, - /* 4542 */ 'l', 'd', 'x', 'r', 9, 0, - /* 4548 */ 's', 't', 'l', 'x', 'r', 9, 0, - /* 4555 */ 's', 't', 'x', 'r', 9, 0, - /* 4561 */ 'c', 'a', 's', 9, 0, - /* 4566 */ 'b', 'r', 'k', 'a', 's', 9, 0, - /* 4573 */ 'b', 'r', 'k', 'p', 'a', 's', 9, 0, - /* 4581 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, - /* 4589 */ 'f', 'a', 'b', 's', 9, 0, - /* 4595 */ 's', 'q', 'a', 'b', 's', 9, 0, - /* 4602 */ 'b', 'r', 'k', 'b', 's', 9, 0, - /* 4609 */ 'b', 'r', 'k', 'p', 'b', 's', 9, 0, - /* 4617 */ 's', 'u', 'b', 's', 9, 0, - /* 4623 */ 's', 'b', 'c', 's', 9, 0, - /* 4629 */ 'a', 'd', 'c', 's', 9, 0, - /* 4635 */ 'b', 'i', 'c', 's', 9, 0, - /* 4641 */ 'a', 'd', 'd', 's', 9, 0, - /* 4647 */ 'n', 'a', 'n', 'd', 's', 9, 0, - /* 4654 */ 'p', 't', 'r', 'u', 'e', 's', 9, 0, - /* 4662 */ 'c', 'm', 'h', 's', 9, 0, - /* 4668 */ 'c', 'm', 'p', 'h', 's', 9, 0, - /* 4675 */ 'c', 'l', 's', 9, 0, - /* 4680 */ 'w', 'h', 'i', 'l', 'e', 'l', 's', 9, 0, - /* 4689 */ 'f', 'm', 'l', 's', 9, 0, - /* 4695 */ 'f', 'n', 'm', 'l', 's', 9, 0, - /* 4702 */ 'c', 'm', 'p', 'l', 's', 9, 0, - /* 4709 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, - /* 4717 */ 'i', 'n', 's', 9, 0, - /* 4722 */ 'b', 'r', 'k', 'n', 's', 9, 0, - /* 4729 */ 'o', 'r', 'n', 's', 9, 0, - /* 4735 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, - /* 4743 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, - /* 4751 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, - /* 4759 */ 'r', 'd', 'f', 'f', 'r', 's', 9, 0, - /* 4767 */ 'm', 'r', 's', 9, 0, - /* 4772 */ 'e', 'o', 'r', 's', 9, 0, - /* 4778 */ 'n', 'o', 'r', 's', 9, 0, - /* 4784 */ 'o', 'r', 'r', 's', 9, 0, - /* 4790 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, - /* 4799 */ 's', 'y', 's', 9, 0, - /* 4804 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, - /* 4812 */ 'f', 'j', 'c', 'v', 't', 'z', 's', 9, 0, - /* 4821 */ 'c', 'o', 'm', 'p', 'a', 'c', 't', 9, 0, - /* 4830 */ 'r', 'e', 't', 9, 0, - /* 4835 */ 'l', 'd', 's', 'e', 't', 9, 0, - /* 4842 */ 'f', 'a', 'c', 'g', 't', 9, 0, - /* 4849 */ 'f', 'c', 'm', 'g', 't', 9, 0, - /* 4856 */ 'c', 'm', 'p', 'g', 't', 9, 0, - /* 4863 */ 'r', 'b', 'i', 't', 9, 0, - /* 4869 */ 'w', 'h', 'i', 'l', 'e', 'l', 't', 9, 0, - /* 4878 */ 'h', 'l', 't', 9, 0, - /* 4883 */ 'f', 'c', 'm', 'l', 't', 9, 0, - /* 4890 */ 'c', 'm', 'p', 'l', 't', 9, 0, - /* 4897 */ 'c', 'n', 't', 9, 0, - /* 4902 */ 'h', 'i', 'n', 't', 9, 0, - /* 4908 */ 's', 'd', 'o', 't', 9, 0, - /* 4914 */ 'u', 'd', 'o', 't', 9, 0, - /* 4920 */ 'c', 'n', 'o', 't', 9, 0, - /* 4926 */ 'f', 's', 'q', 'r', 't', 9, 0, - /* 4933 */ 'p', 't', 'e', 's', 't', 9, 0, - /* 4940 */ 'p', 'f', 'i', 'r', 's', 't', 9, 0, - /* 4948 */ 'c', 'm', 't', 's', 't', 9, 0, - /* 4955 */ 'f', 'c', 'v', 't', 9, 0, - /* 4961 */ 'p', 'n', 'e', 'x', 't', 9, 0, - /* 4968 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, - /* 4976 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, - /* 4984 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, - /* 4992 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, - /* 5000 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, - /* 5008 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, - /* 5016 */ 'f', 'a', 'd', 'd', 'v', 9, 0, - /* 5023 */ 's', 'a', 'd', 'd', 'v', 9, 0, - /* 5030 */ 'u', 'a', 'd', 'd', 'v', 9, 0, - /* 5037 */ 'a', 'n', 'd', 'v', 9, 0, - /* 5043 */ 'r', 'e', 'v', 9, 0, - /* 5048 */ 'f', 'd', 'i', 'v', 9, 0, - /* 5054 */ 's', 'd', 'i', 'v', 9, 0, - /* 5060 */ 'u', 'd', 'i', 'v', 9, 0, - /* 5066 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, - /* 5074 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, - /* 5082 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, - /* 5091 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, - /* 5100 */ 'f', 'm', 'i', 'n', 'v', 9, 0, - /* 5107 */ 's', 'm', 'i', 'n', 'v', 9, 0, - /* 5114 */ 'u', 'm', 'i', 'n', 'v', 9, 0, - /* 5121 */ 'c', 's', 'i', 'n', 'v', 9, 0, - /* 5128 */ 'f', 'm', 'o', 'v', 9, 0, - /* 5134 */ 's', 'm', 'o', 'v', 9, 0, - /* 5140 */ 'u', 'm', 'o', 'v', 9, 0, - /* 5146 */ 'e', 'o', 'r', 'v', 9, 0, - /* 5152 */ 'f', 'm', 'a', 'x', 'v', 9, 0, - /* 5159 */ 's', 'm', 'a', 'x', 'v', 9, 0, - /* 5166 */ 'u', 'm', 'a', 'x', 'v', 9, 0, - /* 5173 */ 'l', 'd', '1', 'w', 9, 0, - /* 5179 */ 'l', 'd', 'f', 'f', '1', 'w', 9, 0, - /* 5187 */ 'l', 'd', 'n', 'f', '1', 'w', 9, 0, - /* 5195 */ 'l', 'd', 'n', 't', '1', 'w', 9, 0, - /* 5203 */ 's', 't', 'n', 't', '1', 'w', 9, 0, - /* 5211 */ 's', 't', '1', 'w', 9, 0, - /* 5217 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, - /* 5225 */ 'l', 'd', '2', 'w', 9, 0, - /* 5231 */ 's', 't', '2', 'w', 9, 0, - /* 5237 */ 'l', 'd', '3', 'w', 9, 0, - /* 5243 */ 's', 't', '3', 'w', 9, 0, - /* 5249 */ 'l', 'd', '4', 'w', 9, 0, - /* 5255 */ 's', 't', '4', 'w', 9, 0, - /* 5261 */ 's', 's', 'u', 'b', 'w', 9, 0, - /* 5268 */ 'u', 's', 'u', 'b', 'w', 9, 0, - /* 5275 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, - /* 5284 */ 's', 'q', 'd', 'e', 'c', 'w', 9, 0, - /* 5292 */ 'u', 'q', 'd', 'e', 'c', 'w', 9, 0, - /* 5300 */ 's', 'q', 'i', 'n', 'c', 'w', 9, 0, - /* 5308 */ 'u', 'q', 'i', 'n', 'c', 'w', 9, 0, - /* 5316 */ 's', 'a', 'd', 'd', 'w', 9, 0, - /* 5323 */ 'u', 'a', 'd', 'd', 'w', 9, 0, - /* 5330 */ 'p', 'r', 'f', 'w', 9, 0, - /* 5336 */ 'l', 'd', '1', 'r', 'q', 'w', 9, 0, - /* 5344 */ 'l', 'd', '1', 'r', 'w', 9, 0, - /* 5351 */ 'l', 'd', '1', 's', 'w', 9, 0, - /* 5358 */ 'l', 'd', 'f', 'f', '1', 's', 'w', 9, 0, - /* 5367 */ 'l', 'd', 'n', 'f', '1', 's', 'w', 9, 0, - /* 5376 */ 'l', 'd', 'p', 's', 'w', 9, 0, - /* 5383 */ 'l', 'd', '1', 'r', 's', 'w', 9, 0, - /* 5391 */ 'l', 'd', 'r', 's', 'w', 9, 0, - /* 5398 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, - /* 5406 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, - /* 5414 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'w', 9, 0, - /* 5424 */ 'c', 'n', 't', 'w', 9, 0, - /* 5430 */ 's', 'x', 't', 'w', 9, 0, - /* 5436 */ 'u', 'x', 't', 'w', 9, 0, - /* 5442 */ 'r', 'e', 'v', 'w', 9, 0, - /* 5448 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, - /* 5456 */ 'b', 'c', 'a', 'x', 9, 0, - /* 5462 */ 'f', 'm', 'a', 'x', 9, 0, - /* 5468 */ 'l', 'd', 's', 'm', 'a', 'x', 9, 0, - /* 5476 */ 'l', 'd', 'u', 'm', 'a', 'x', 9, 0, - /* 5484 */ 't', 'b', 'x', 9, 0, - /* 5489 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, - /* 5498 */ 'i', 'n', 'd', 'e', 'x', 9, 0, - /* 5505 */ 'c', 'l', 'r', 'e', 'x', 9, 0, - /* 5512 */ 'm', 'o', 'v', 'p', 'r', 'f', 'x', 9, 0, - /* 5521 */ 'f', 'm', 'u', 'l', 'x', 9, 0, - /* 5528 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, - /* 5536 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, - /* 5544 */ 's', 'm', '4', 'e', 'k', 'e', 'y', 9, 0, - /* 5553 */ 'f', 'c', 'p', 'y', 9, 0, - /* 5559 */ 'b', 'r', 'a', 'a', 'z', 9, 0, - /* 5566 */ 'b', 'l', 'r', 'a', 'a', 'z', 9, 0, - /* 5574 */ 'b', 'r', 'a', 'b', 'z', 9, 0, - /* 5581 */ 'b', 'l', 'r', 'a', 'b', 'z', 9, 0, - /* 5589 */ 'c', 'b', 'z', 9, 0, - /* 5594 */ 't', 'b', 'z', 9, 0, - /* 5599 */ 'c', 'l', 'z', 9, 0, - /* 5604 */ 'c', 'b', 'n', 'z', 9, 0, - /* 5610 */ 't', 'b', 'n', 'z', 9, 0, - /* 5616 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, - /* 5624 */ 'm', 'o', 'v', 'z', 9, 0, - /* 5630 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, - /* 5644 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, - /* 5675 */ 'b', '.', 0, - /* 5678 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 5702 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 5727 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, - /* 5750 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, - /* 5773 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, - /* 5795 */ 'p', 'a', 'c', 'i', 'a', '1', '7', '1', '6', 0, - /* 5805 */ 'a', 'u', 't', 'i', 'a', '1', '7', '1', '6', 0, - /* 5815 */ 'p', 'a', 'c', 'i', 'b', '1', '7', '1', '6', 0, - /* 5825 */ 'a', 'u', 't', 'i', 'b', '1', '7', '1', '6', 0, - /* 5835 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 5848 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 5855 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 5865 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, - /* 5875 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 5890 */ 'e', 'r', 'e', 't', 'a', 'a', 0, - /* 5897 */ 'e', 'r', 'e', 't', 'a', 'b', 0, - /* 5904 */ 'x', 'p', 'a', 'c', 'l', 'r', 'i', 0, - /* 5912 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, - /* 5926 */ 'p', 'a', 'c', 'i', 'a', 's', 'p', 0, - /* 5934 */ 'a', 'u', 't', 'i', 'a', 's', 'p', 0, - /* 5942 */ 'p', 'a', 'c', 'i', 'b', 's', 'p', 0, - /* 5950 */ 'a', 'u', 't', 'i', 'b', 's', 'p', 0, - /* 5958 */ 's', 'e', 't', 'f', 'f', 'r', 0, - /* 5965 */ 'd', 'r', 'p', 's', 0, - /* 5970 */ 'e', 'r', 'e', 't', 0, - /* 5975 */ 'c', 'f', 'i', 'n', 'v', 0, - /* 5981 */ 'p', 'a', 'c', 'i', 'a', 'z', 0, - /* 5988 */ 'a', 'u', 't', 'i', 'a', 'z', 0, - /* 5995 */ 'p', 'a', 'c', 'i', 'b', 'z', 0, - /* 6002 */ 'a', 'u', 't', 'i', 'b', 'z', 0, + /* 0 */ 's', + 'h', + 'a', + '1', + 's', + 'u', + '0', + 9, + 0, + /* 9 */ 's', + 'h', + 'a', + '5', + '1', + '2', + 's', + 'u', + '0', + 9, + 0, + /* 20 */ 's', + 'h', + 'a', + '2', + '5', + '6', + 's', + 'u', + '0', + 9, + 0, + /* 31 */ 'l', + 'd', + '1', + 9, + 0, + /* 36 */ 't', + 'r', + 'n', + '1', + 9, + 0, + /* 42 */ 'z', + 'i', + 'p', + '1', + 9, + 0, + /* 48 */ 'u', + 'z', + 'p', + '1', + 9, + 0, + /* 54 */ 'd', + 'c', + 'p', + 's', + '1', + 9, + 0, + /* 61 */ 's', + 'm', + '3', + 's', + 's', + '1', + 9, + 0, + /* 69 */ 's', + 't', + '1', + 9, + 0, + /* 74 */ 's', + 'h', + 'a', + '1', + 's', + 'u', + '1', + 9, + 0, + /* 83 */ 's', + 'h', + 'a', + '5', + '1', + '2', + 's', + 'u', + '1', + 9, + 0, + /* 94 */ 's', + 'h', + 'a', + '2', + '5', + '6', + 's', + 'u', + '1', + 9, + 0, + /* 105 */ 's', + 'm', + '3', + 'p', + 'a', + 'r', + 't', + 'w', + '1', + 9, + 0, + /* 116 */ 'r', + 'a', + 'x', + '1', + 9, + 0, + /* 122 */ 'r', + 'e', + 'v', + '3', + '2', + 9, + 0, + /* 129 */ 'l', + 'd', + '2', + 9, + 0, + /* 134 */ 's', + 'h', + 'a', + '5', + '1', + '2', + 'h', + '2', + 9, + 0, + /* 144 */ 's', + 'h', + 'a', + '2', + '5', + '6', + 'h', + '2', + 9, + 0, + /* 154 */ 's', + 'a', + 'b', + 'a', + 'l', + '2', + 9, + 0, + /* 162 */ 'u', + 'a', + 'b', + 'a', + 'l', + '2', + 9, + 0, + /* 170 */ 's', + 'q', + 'd', + 'm', + 'l', + 'a', + 'l', + '2', + 9, + 0, + /* 180 */ 's', + 'm', + 'l', + 'a', + 'l', + '2', + 9, + 0, + /* 188 */ 'u', + 'm', + 'l', + 'a', + 'l', + '2', + 9, + 0, + /* 196 */ 's', + 's', + 'u', + 'b', + 'l', + '2', + 9, + 0, + /* 204 */ 'u', + 's', + 'u', + 'b', + 'l', + '2', + 9, + 0, + /* 212 */ 's', + 'a', + 'b', + 'd', + 'l', + '2', + 9, + 0, + /* 220 */ 'u', + 'a', + 'b', + 'd', + 'l', + '2', + 9, + 0, + /* 228 */ 's', + 'a', + 'd', + 'd', + 'l', + '2', + 9, + 0, + /* 236 */ 'u', + 'a', + 'd', + 'd', + 'l', + '2', + 9, + 0, + /* 244 */ 's', + 's', + 'h', + 'l', + 'l', + '2', + 9, + 0, + /* 252 */ 'u', + 's', + 'h', + 'l', + 'l', + '2', + 9, + 0, + /* 260 */ 's', + 'q', + 'd', + 'm', + 'u', + 'l', + 'l', + '2', + 9, + 0, + /* 270 */ 'p', + 'm', + 'u', + 'l', + 'l', + '2', + 9, + 0, + /* 278 */ 's', + 'm', + 'u', + 'l', + 'l', + '2', + 9, + 0, + /* 286 */ 'u', + 'm', + 'u', + 'l', + 'l', + '2', + 9, + 0, + /* 294 */ 's', + 'q', + 'd', + 'm', + 'l', + 's', + 'l', + '2', + 9, + 0, + /* 304 */ 's', + 'm', + 'l', + 's', + 'l', + '2', + 9, + 0, + /* 312 */ 'u', + 'm', + 'l', + 's', + 'l', + '2', + 9, + 0, + /* 320 */ 'f', + 'c', + 'v', + 't', + 'l', + '2', + 9, + 0, + /* 328 */ 'r', + 's', + 'u', + 'b', + 'h', + 'n', + '2', + 9, + 0, + /* 337 */ 'r', + 'a', + 'd', + 'd', + 'h', + 'n', + '2', + 9, + 0, + /* 346 */ 's', + 'q', + 's', + 'h', + 'r', + 'n', + '2', + 9, + 0, + /* 355 */ 'u', + 'q', + 's', + 'h', + 'r', + 'n', + '2', + 9, + 0, + /* 364 */ 's', + 'q', + 'r', + 's', + 'h', + 'r', + 'n', + '2', + 9, + 0, + /* 374 */ 'u', + 'q', + 'r', + 's', + 'h', + 'r', + 'n', + '2', + 9, + 0, + /* 384 */ 't', + 'r', + 'n', + '2', + 9, + 0, + /* 390 */ 'f', + 'c', + 'v', + 't', + 'n', + '2', + 9, + 0, + /* 398 */ 's', + 'q', + 'x', + 't', + 'n', + '2', + 9, + 0, + /* 406 */ 'u', + 'q', + 'x', + 't', + 'n', + '2', + 9, + 0, + /* 414 */ 's', + 'q', + 's', + 'h', + 'r', + 'u', + 'n', + '2', + 9, + 0, + /* 424 */ 's', + 'q', + 'r', + 's', + 'h', + 'r', + 'u', + 'n', + '2', + 9, + 0, + /* 435 */ 's', + 'q', + 'x', + 't', + 'u', + 'n', + '2', + 9, + 0, + /* 444 */ 'f', + 'c', + 'v', + 't', + 'x', + 'n', + '2', + 9, + 0, + /* 453 */ 'z', + 'i', + 'p', + '2', + 9, + 0, + /* 459 */ 'u', + 'z', + 'p', + '2', + 9, + 0, + /* 465 */ 'd', + 'c', + 'p', + 's', + '2', + 9, + 0, + /* 472 */ 's', + 't', + '2', + 9, + 0, + /* 477 */ 's', + 's', + 'u', + 'b', + 'w', + '2', + 9, + 0, + /* 485 */ 'u', + 's', + 'u', + 'b', + 'w', + '2', + 9, + 0, + /* 493 */ 's', + 'a', + 'd', + 'd', + 'w', + '2', + 9, + 0, + /* 501 */ 'u', + 'a', + 'd', + 'd', + 'w', + '2', + 9, + 0, + /* 509 */ 's', + 'm', + '3', + 'p', + 'a', + 'r', + 't', + 'w', + '2', + 9, + 0, + /* 520 */ 'l', + 'd', + '3', + 9, + 0, + /* 525 */ 'e', + 'o', + 'r', + '3', + 9, + 0, + /* 531 */ 'd', + 'c', + 'p', + 's', + '3', + 9, + 0, + /* 538 */ 's', + 't', + '3', + 9, + 0, + /* 543 */ 'r', + 'e', + 'v', + '6', + '4', + 9, + 0, + /* 550 */ 'l', + 'd', + '4', + 9, + 0, + /* 555 */ 's', + 't', + '4', + 9, + 0, + /* 560 */ 's', + 'e', + 't', + 'f', + '1', + '6', + 9, + 0, + /* 568 */ 'r', + 'e', + 'v', + '1', + '6', + 9, + 0, + /* 575 */ 's', + 'e', + 't', + 'f', + '8', + 9, + 0, + /* 582 */ 's', + 'm', + '3', + 't', + 't', + '1', + 'a', + 9, + 0, + /* 591 */ 's', + 'm', + '3', + 't', + 't', + '2', + 'a', + 9, + 0, + /* 600 */ 'b', + 'r', + 'a', + 'a', + 9, + 0, + /* 606 */ 'l', + 'd', + 'r', + 'a', + 'a', + 9, + 0, + /* 613 */ 'b', + 'l', + 'r', + 'a', + 'a', + 9, + 0, + /* 620 */ 's', + 'a', + 'b', + 'a', + 9, + 0, + /* 626 */ 'u', + 'a', + 'b', + 'a', + 9, + 0, + /* 632 */ 'p', + 'a', + 'c', + 'd', + 'a', + 9, + 0, + /* 639 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'a', + 9, + 0, + /* 647 */ 'f', + 'a', + 'd', + 'd', + 'a', + 9, + 0, + /* 654 */ 'a', + 'u', + 't', + 'd', + 'a', + 9, + 0, + /* 661 */ 'p', + 'a', + 'c', + 'g', + 'a', + 9, + 0, + /* 668 */ 'p', + 'a', + 'c', + 'i', + 'a', + 9, + 0, + /* 675 */ 'a', + 'u', + 't', + 'i', + 'a', + 9, + 0, + /* 682 */ 'b', + 'r', + 'k', + 'a', + 9, + 0, + /* 688 */ 'f', + 'c', + 'm', + 'l', + 'a', + 9, + 0, + /* 695 */ 'f', + 'm', + 'l', + 'a', + 9, + 0, + /* 701 */ 'f', + 'n', + 'm', + 'l', + 'a', + 9, + 0, + /* 708 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'a', + 9, + 0, + /* 717 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'a', + 9, + 0, + /* 726 */ 'b', + 'r', + 'k', + 'p', + 'a', + 9, + 0, + /* 733 */ 'c', + 'a', + 's', + 'p', + 'a', + 9, + 0, + /* 740 */ 's', + 'w', + 'p', + 'a', + 9, + 0, + /* 746 */ 'f', + 'e', + 'x', + 'p', + 'a', + 9, + 0, + /* 753 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'a', + 9, + 0, + /* 761 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'a', + 9, + 0, + /* 769 */ 's', + 'r', + 's', + 'r', + 'a', + 9, + 0, + /* 776 */ 'u', + 'r', + 's', + 'r', + 'a', + 9, + 0, + /* 783 */ 's', + 's', + 'r', + 'a', + 9, + 0, + /* 789 */ 'u', + 's', + 'r', + 'a', + 9, + 0, + /* 795 */ 'c', + 'a', + 's', + 'a', + 9, + 0, + /* 801 */ 'l', + 'd', + 's', + 'e', + 't', + 'a', + 9, + 0, + /* 809 */ 'f', + 'r', + 'i', + 'n', + 't', + 'a', + 9, + 0, + /* 817 */ 'c', + 'l', + 'a', + 's', + 't', + 'a', + 9, + 0, + /* 825 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'a', + 9, + 0, + /* 834 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'a', + 9, + 0, + /* 843 */ 'p', + 'a', + 'c', + 'd', + 'z', + 'a', + 9, + 0, + /* 851 */ 'a', + 'u', + 't', + 'd', + 'z', + 'a', + 9, + 0, + /* 859 */ 'p', + 'a', + 'c', + 'i', + 'z', + 'a', + 9, + 0, + /* 867 */ 'a', + 'u', + 't', + 'i', + 'z', + 'a', + 9, + 0, + /* 875 */ 'l', + 'd', + '1', + 'b', + 9, + 0, + /* 881 */ 'l', + 'd', + 'f', + 'f', + '1', + 'b', + 9, + 0, + /* 889 */ 'l', + 'd', + 'n', + 'f', + '1', + 'b', + 9, + 0, + /* 897 */ 'l', + 'd', + 'n', + 't', + '1', + 'b', + 9, + 0, + /* 905 */ 's', + 't', + 'n', + 't', + '1', + 'b', + 9, + 0, + /* 913 */ 's', + 't', + '1', + 'b', + 9, + 0, + /* 919 */ 's', + 'm', + '3', + 't', + 't', + '1', + 'b', + 9, + 0, + /* 928 */ 'c', + 'r', + 'c', + '3', + '2', + 'b', + 9, + 0, + /* 936 */ 'l', + 'd', + '2', + 'b', + 9, + 0, + /* 942 */ 's', + 't', + '2', + 'b', + 9, + 0, + /* 948 */ 's', + 'm', + '3', + 't', + 't', + '2', + 'b', + 9, + 0, + /* 957 */ 'l', + 'd', + '3', + 'b', + 9, + 0, + /* 963 */ 's', + 't', + '3', + 'b', + 9, + 0, + /* 969 */ 'l', + 'd', + '4', + 'b', + 9, + 0, + /* 975 */ 's', + 't', + '4', + 'b', + 9, + 0, + /* 981 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'a', + 'b', + 9, + 0, + /* 990 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'a', + 'b', + 9, + 0, + /* 1000 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'a', + 'b', + 9, + 0, + /* 1010 */ 's', + 'w', + 'p', + 'a', + 'b', + 9, + 0, + /* 1017 */ 'b', + 'r', + 'a', + 'b', + 9, + 0, + /* 1023 */ 'l', + 'd', + 'r', + 'a', + 'b', + 9, + 0, + /* 1030 */ 'b', + 'l', + 'r', + 'a', + 'b', + 9, + 0, + /* 1037 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'a', + 'b', + 9, + 0, + /* 1046 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'a', + 'b', + 9, + 0, + /* 1055 */ 'c', + 'a', + 's', + 'a', + 'b', + 9, + 0, + /* 1062 */ 'l', + 'd', + 's', + 'e', + 't', + 'a', + 'b', + 9, + 0, + /* 1071 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'a', + 'b', + 9, + 0, + /* 1081 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'a', + 'b', + 9, + 0, + /* 1091 */ 'c', + 'r', + 'c', + '3', + '2', + 'c', + 'b', + 9, + 0, + /* 1100 */ 's', + 'q', + 'd', + 'e', + 'c', + 'b', + 9, + 0, + /* 1108 */ 'u', + 'q', + 'd', + 'e', + 'c', + 'b', + 9, + 0, + /* 1116 */ 's', + 'q', + 'i', + 'n', + 'c', + 'b', + 9, + 0, + /* 1124 */ 'u', + 'q', + 'i', + 'n', + 'c', + 'b', + 9, + 0, + /* 1132 */ 'p', + 'a', + 'c', + 'd', + 'b', + 9, + 0, + /* 1139 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'b', + 9, + 0, + /* 1147 */ 'a', + 'u', + 't', + 'd', + 'b', + 9, + 0, + /* 1154 */ 'p', + 'r', + 'f', + 'b', + 9, + 0, + /* 1160 */ 'p', + 'a', + 'c', + 'i', + 'b', + 9, + 0, + /* 1167 */ 'a', + 'u', + 't', + 'i', + 'b', + 9, + 0, + /* 1174 */ 'b', + 'r', + 'k', + 'b', + 9, + 0, + /* 1180 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'a', + 'l', + 'b', + 9, + 0, + /* 1190 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'a', + 'l', + 'b', + 9, + 0, + /* 1201 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'a', + 'l', + 'b', + 9, + 0, + /* 1212 */ 's', + 'w', + 'p', + 'a', + 'l', + 'b', + 9, + 0, + /* 1220 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'a', + 'l', + 'b', + 9, + 0, + /* 1230 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'a', + 'l', + 'b', + 9, + 0, + /* 1240 */ 'c', + 'a', + 's', + 'a', + 'l', + 'b', + 9, + 0, + /* 1248 */ 'l', + 'd', + 's', + 'e', + 't', + 'a', + 'l', + 'b', + 9, + 0, + /* 1258 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'a', + 'l', + 'b', + 9, + 0, + /* 1269 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'a', + 'l', + 'b', + 9, + 0, + /* 1280 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'l', + 'b', + 9, + 0, + /* 1289 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'l', + 'b', + 9, + 0, + /* 1299 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'l', + 'b', + 9, + 0, + /* 1309 */ 's', + 'w', + 'p', + 'l', + 'b', + 9, + 0, + /* 1316 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'l', + 'b', + 9, + 0, + /* 1325 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'l', + 'b', + 9, + 0, + /* 1334 */ 'c', + 'a', + 's', + 'l', + 'b', + 9, + 0, + /* 1341 */ 'l', + 'd', + 's', + 'e', + 't', + 'l', + 'b', + 9, + 0, + /* 1350 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'l', + 'b', + 9, + 0, + /* 1360 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'l', + 'b', + 9, + 0, + /* 1370 */ 'd', + 'm', + 'b', + 9, + 0, + /* 1375 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'b', + 9, + 0, + /* 1384 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'b', + 9, + 0, + /* 1393 */ 'b', + 'r', + 'k', + 'p', + 'b', + 9, + 0, + /* 1400 */ 's', + 'w', + 'p', + 'b', + 9, + 0, + /* 1406 */ 'l', + 'd', + '1', + 'r', + 'q', + 'b', + 9, + 0, + /* 1414 */ 'l', + 'd', + '1', + 'r', + 'b', + 9, + 0, + /* 1421 */ 'l', + 'd', + 'a', + 'r', + 'b', + 9, + 0, + /* 1428 */ 'l', + 'd', + 'l', + 'a', + 'r', + 'b', + 9, + 0, + /* 1436 */ 'l', + 'd', + 'r', + 'b', + 9, + 0, + /* 1442 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'b', + 9, + 0, + /* 1450 */ 's', + 't', + 'l', + 'l', + 'r', + 'b', + 9, + 0, + /* 1458 */ 's', + 't', + 'l', + 'r', + 'b', + 9, + 0, + /* 1465 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'b', + 9, + 0, + /* 1473 */ 'l', + 'd', + 'a', + 'p', + 'r', + 'b', + 9, + 0, + /* 1481 */ 'l', + 'd', + 't', + 'r', + 'b', + 9, + 0, + /* 1488 */ 's', + 't', + 'r', + 'b', + 9, + 0, + /* 1494 */ 's', + 't', + 't', + 'r', + 'b', + 9, + 0, + /* 1501 */ 'l', + 'd', + 'u', + 'r', + 'b', + 9, + 0, + /* 1508 */ 's', + 't', + 'l', + 'u', + 'r', + 'b', + 9, + 0, + /* 1516 */ 'l', + 'd', + 'a', + 'p', + 'u', + 'r', + 'b', + 9, + 0, + /* 1525 */ 's', + 't', + 'u', + 'r', + 'b', + 9, + 0, + /* 1532 */ 'l', + 'd', + 'a', + 'x', + 'r', + 'b', + 9, + 0, + /* 1540 */ 'l', + 'd', + 'x', + 'r', + 'b', + 9, + 0, + /* 1547 */ 's', + 't', + 'l', + 'x', + 'r', + 'b', + 9, + 0, + /* 1555 */ 's', + 't', + 'x', + 'r', + 'b', + 9, + 0, + /* 1562 */ 'l', + 'd', + '1', + 's', + 'b', + 9, + 0, + /* 1569 */ 'l', + 'd', + 'f', + 'f', + '1', + 's', + 'b', + 9, + 0, + /* 1578 */ 'l', + 'd', + 'n', + 'f', + '1', + 's', + 'b', + 9, + 0, + /* 1587 */ 'c', + 'a', + 's', + 'b', + 9, + 0, + /* 1593 */ 'd', + 's', + 'b', + 9, + 0, + /* 1598 */ 'i', + 's', + 'b', + 9, + 0, + /* 1603 */ 'f', + 'm', + 's', + 'b', + 9, + 0, + /* 1609 */ 'f', + 'n', + 'm', + 's', + 'b', + 9, + 0, + /* 1616 */ 'l', + 'd', + '1', + 'r', + 's', + 'b', + 9, + 0, + /* 1624 */ 'l', + 'd', + 'r', + 's', + 'b', + 9, + 0, + /* 1631 */ 'l', + 'd', + 't', + 'r', + 's', + 'b', + 9, + 0, + /* 1639 */ 'l', + 'd', + 'u', + 'r', + 's', + 'b', + 9, + 0, + /* 1647 */ 'l', + 'd', + 'a', + 'p', + 'u', + 'r', + 's', + 'b', + 9, + 0, + /* 1657 */ 't', + 's', + 'b', + 9, + 0, + /* 1662 */ 'l', + 'd', + 's', + 'e', + 't', + 'b', + 9, + 0, + /* 1670 */ 'c', + 'n', + 't', + 'b', + 9, + 0, + /* 1676 */ 'c', + 'l', + 'a', + 's', + 't', + 'b', + 9, + 0, + /* 1684 */ 's', + 'x', + 't', + 'b', + 9, + 0, + /* 1690 */ 'u', + 'x', + 't', + 'b', + 9, + 0, + /* 1696 */ 'f', + 's', + 'u', + 'b', + 9, + 0, + /* 1702 */ 's', + 'h', + 's', + 'u', + 'b', + 9, + 0, + /* 1709 */ 'u', + 'h', + 's', + 'u', + 'b', + 9, + 0, + /* 1716 */ 'f', + 'm', + 's', + 'u', + 'b', + 9, + 0, + /* 1723 */ 'f', + 'n', + 'm', + 's', + 'u', + 'b', + 9, + 0, + /* 1731 */ 's', + 'q', + 's', + 'u', + 'b', + 9, + 0, + /* 1738 */ 'u', + 'q', + 's', + 'u', + 'b', + 9, + 0, + /* 1745 */ 'r', + 'e', + 'v', + 'b', + 9, + 0, + /* 1751 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'b', + 9, + 0, + /* 1760 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'b', + 9, + 0, + /* 1769 */ 'p', + 'a', + 'c', + 'd', + 'z', + 'b', + 9, + 0, + /* 1777 */ 'a', + 'u', + 't', + 'd', + 'z', + 'b', + 9, + 0, + /* 1785 */ 'p', + 'a', + 'c', + 'i', + 'z', + 'b', + 9, + 0, + /* 1793 */ 'a', + 'u', + 't', + 'i', + 'z', + 'b', + 9, + 0, + /* 1801 */ 's', + 'h', + 'a', + '1', + 'c', + 9, + 0, + /* 1808 */ 's', + 'b', + 'c', + 9, + 0, + /* 1813 */ 'a', + 'd', + 'c', + 9, + 0, + /* 1818 */ 'b', + 'i', + 'c', + 9, + 0, + /* 1823 */ 'a', + 'e', + 's', + 'i', + 'm', + 'c', + 9, + 0, + /* 1831 */ 'a', + 'e', + 's', + 'm', + 'c', + 9, + 0, + /* 1838 */ 'c', + 's', + 'i', + 'n', + 'c', + 9, + 0, + /* 1845 */ 'h', + 'v', + 'c', + 9, + 0, + /* 1850 */ 's', + 'v', + 'c', + 9, + 0, + /* 1855 */ 'l', + 'd', + '1', + 'd', + 9, + 0, + /* 1861 */ 'l', + 'd', + 'f', + 'f', + '1', + 'd', + 9, + 0, + /* 1869 */ 'l', + 'd', + 'n', + 'f', + '1', + 'd', + 9, + 0, + /* 1877 */ 'l', + 'd', + 'n', + 't', + '1', + 'd', + 9, + 0, + /* 1885 */ 's', + 't', + 'n', + 't', + '1', + 'd', + 9, + 0, + /* 1893 */ 's', + 't', + '1', + 'd', + 9, + 0, + /* 1899 */ 'l', + 'd', + '2', + 'd', + 9, + 0, + /* 1905 */ 's', + 't', + '2', + 'd', + 9, + 0, + /* 1911 */ 'l', + 'd', + '3', + 'd', + 9, + 0, + /* 1917 */ 's', + 't', + '3', + 'd', + 9, + 0, + /* 1923 */ 'l', + 'd', + '4', + 'd', + 9, + 0, + /* 1929 */ 's', + 't', + '4', + 'd', + 9, + 0, + /* 1935 */ 'f', + 'm', + 'a', + 'd', + 9, + 0, + /* 1941 */ 'f', + 'n', + 'm', + 'a', + 'd', + 9, + 0, + /* 1948 */ 'f', + 't', + 'm', + 'a', + 'd', + 9, + 0, + /* 1955 */ 'f', + 'a', + 'b', + 'd', + 9, + 0, + /* 1961 */ 's', + 'a', + 'b', + 'd', + 9, + 0, + /* 1967 */ 'u', + 'a', + 'b', + 'd', + 9, + 0, + /* 1973 */ 'x', + 'p', + 'a', + 'c', + 'd', + 9, + 0, + /* 1980 */ 's', + 'q', + 'd', + 'e', + 'c', + 'd', + 9, + 0, + /* 1988 */ 'u', + 'q', + 'd', + 'e', + 'c', + 'd', + 9, + 0, + /* 1996 */ 's', + 'q', + 'i', + 'n', + 'c', + 'd', + 9, + 0, + /* 2004 */ 'u', + 'q', + 'i', + 'n', + 'c', + 'd', + 9, + 0, + /* 2012 */ 'f', + 'c', + 'a', + 'd', + 'd', + 9, + 0, + /* 2019 */ 'l', + 'd', + 'a', + 'd', + 'd', + 9, + 0, + /* 2026 */ 'f', + 'a', + 'd', + 'd', + 9, + 0, + /* 2032 */ 's', + 'r', + 'h', + 'a', + 'd', + 'd', + 9, + 0, + /* 2040 */ 'u', + 'r', + 'h', + 'a', + 'd', + 'd', + 9, + 0, + /* 2048 */ 's', + 'h', + 'a', + 'd', + 'd', + 9, + 0, + /* 2055 */ 'u', + 'h', + 'a', + 'd', + 'd', + 9, + 0, + /* 2062 */ 'f', + 'm', + 'a', + 'd', + 'd', + 9, + 0, + /* 2069 */ 'f', + 'n', + 'm', + 'a', + 'd', + 'd', + 9, + 0, + /* 2077 */ 'u', + 's', + 'q', + 'a', + 'd', + 'd', + 9, + 0, + /* 2085 */ 's', + 'u', + 'q', + 'a', + 'd', + 'd', + 9, + 0, + /* 2093 */ 'p', + 'r', + 'f', + 'd', + 9, + 0, + /* 2099 */ 'n', + 'a', + 'n', + 'd', + 9, + 0, + /* 2105 */ 'l', + 'd', + '1', + 'r', + 'q', + 'd', + 9, + 0, + /* 2113 */ 'l', + 'd', + '1', + 'r', + 'd', + 9, + 0, + /* 2120 */ 'a', + 's', + 'r', + 'd', + 9, + 0, + /* 2126 */ 'a', + 'e', + 's', + 'd', + 9, + 0, + /* 2132 */ 'c', + 'n', + 't', + 'd', + 9, + 0, + /* 2138 */ 's', + 'm', + '4', + 'e', + 9, + 0, + /* 2144 */ 's', + 'p', + 'l', + 'i', + 'c', + 'e', + 9, + 0, + /* 2152 */ 'f', + 'a', + 'c', + 'g', + 'e', + 9, + 0, + /* 2159 */ 'f', + 'c', + 'm', + 'g', + 'e', + 9, + 0, + /* 2166 */ 'c', + 'm', + 'p', + 'g', + 'e', + 9, + 0, + /* 2173 */ 'f', + 's', + 'c', + 'a', + 'l', + 'e', + 9, + 0, + /* 2181 */ 'w', + 'h', + 'i', + 'l', + 'e', + 'l', + 'e', + 9, + 0, + /* 2190 */ 'f', + 'c', + 'm', + 'l', + 'e', + 9, + 0, + /* 2197 */ 'c', + 'm', + 'p', + 'l', + 'e', + 9, + 0, + /* 2204 */ 'f', + 'c', + 'm', + 'n', + 'e', + 9, + 0, + /* 2211 */ 'c', + 't', + 'e', + 'r', + 'm', + 'n', + 'e', + 9, + 0, + /* 2220 */ 'c', + 'm', + 'p', + 'n', + 'e', + 9, + 0, + /* 2227 */ 'f', + 'r', + 'e', + 'c', + 'p', + 'e', + 9, + 0, + /* 2235 */ 'u', + 'r', + 'e', + 'c', + 'p', + 'e', + 9, + 0, + /* 2243 */ 'f', + 'c', + 'c', + 'm', + 'p', + 'e', + 9, + 0, + /* 2251 */ 'f', + 'c', + 'm', + 'p', + 'e', + 9, + 0, + /* 2258 */ 'a', + 'e', + 's', + 'e', + 9, + 0, + /* 2264 */ 'p', + 'f', + 'a', + 'l', + 's', + 'e', + 9, + 0, + /* 2272 */ 'f', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 9, + 0, + /* 2281 */ 'u', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 9, + 0, + /* 2290 */ 'p', + 't', + 'r', + 'u', + 'e', + 9, + 0, + /* 2297 */ 'b', + 'i', + 'f', + 9, + 0, + /* 2302 */ 'r', + 'm', + 'i', + 'f', + 9, + 0, + /* 2308 */ 's', + 'c', + 'v', + 't', + 'f', + 9, + 0, + /* 2315 */ 'u', + 'c', + 'v', + 't', + 'f', + 9, + 0, + /* 2322 */ 'f', + 'n', + 'e', + 'g', + 9, + 0, + /* 2328 */ 's', + 'q', + 'n', + 'e', + 'g', + 9, + 0, + /* 2335 */ 'c', + 's', + 'n', + 'e', + 'g', + 9, + 0, + /* 2342 */ 's', + 'h', + 'a', + '1', + 'h', + 9, + 0, + /* 2349 */ 'l', + 'd', + '1', + 'h', + 9, + 0, + /* 2355 */ 'l', + 'd', + 'f', + 'f', + '1', + 'h', + 9, + 0, + /* 2363 */ 'l', + 'd', + 'n', + 'f', + '1', + 'h', + 9, + 0, + /* 2371 */ 'l', + 'd', + 'n', + 't', + '1', + 'h', + 9, + 0, + /* 2379 */ 's', + 't', + 'n', + 't', + '1', + 'h', + 9, + 0, + /* 2387 */ 's', + 't', + '1', + 'h', + 9, + 0, + /* 2393 */ 's', + 'h', + 'a', + '5', + '1', + '2', + 'h', + 9, + 0, + /* 2402 */ 'c', + 'r', + 'c', + '3', + '2', + 'h', + 9, + 0, + /* 2410 */ 'l', + 'd', + '2', + 'h', + 9, + 0, + /* 2416 */ 's', + 't', + '2', + 'h', + 9, + 0, + /* 2422 */ 'l', + 'd', + '3', + 'h', + 9, + 0, + /* 2428 */ 's', + 't', + '3', + 'h', + 9, + 0, + /* 2434 */ 'l', + 'd', + '4', + 'h', + 9, + 0, + /* 2440 */ 's', + 't', + '4', + 'h', + 9, + 0, + /* 2446 */ 's', + 'h', + 'a', + '2', + '5', + '6', + 'h', + 9, + 0, + /* 2455 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'a', + 'h', + 9, + 0, + /* 2464 */ 's', + 'q', + 'r', + 'd', + 'm', + 'l', + 'a', + 'h', + 9, + 0, + /* 2474 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'a', + 'h', + 9, + 0, + /* 2484 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'a', + 'h', + 9, + 0, + /* 2494 */ 's', + 'w', + 'p', + 'a', + 'h', + 9, + 0, + /* 2501 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'a', + 'h', + 9, + 0, + /* 2510 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'a', + 'h', + 9, + 0, + /* 2519 */ 'c', + 'a', + 's', + 'a', + 'h', + 9, + 0, + /* 2526 */ 'l', + 'd', + 's', + 'e', + 't', + 'a', + 'h', + 9, + 0, + /* 2535 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'a', + 'h', + 9, + 0, + /* 2545 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'a', + 'h', + 9, + 0, + /* 2555 */ 'c', + 'r', + 'c', + '3', + '2', + 'c', + 'h', + 9, + 0, + /* 2564 */ 's', + 'q', + 'd', + 'e', + 'c', + 'h', + 9, + 0, + /* 2572 */ 'u', + 'q', + 'd', + 'e', + 'c', + 'h', + 9, + 0, + /* 2580 */ 's', + 'q', + 'i', + 'n', + 'c', + 'h', + 9, + 0, + /* 2588 */ 'u', + 'q', + 'i', + 'n', + 'c', + 'h', + 9, + 0, + /* 2596 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'h', + 9, + 0, + /* 2604 */ 'p', + 'r', + 'f', + 'h', + 9, + 0, + /* 2610 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'a', + 'l', + 'h', + 9, + 0, + /* 2620 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'a', + 'l', + 'h', + 9, + 0, + /* 2631 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'a', + 'l', + 'h', + 9, + 0, + /* 2642 */ 's', + 'w', + 'p', + 'a', + 'l', + 'h', + 9, + 0, + /* 2650 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'a', + 'l', + 'h', + 9, + 0, + /* 2660 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'a', + 'l', + 'h', + 9, + 0, + /* 2670 */ 'c', + 'a', + 's', + 'a', + 'l', + 'h', + 9, + 0, + /* 2678 */ 'l', + 'd', + 's', + 'e', + 't', + 'a', + 'l', + 'h', + 9, + 0, + /* 2688 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'a', + 'l', + 'h', + 9, + 0, + /* 2699 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'a', + 'l', + 'h', + 9, + 0, + /* 2710 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'l', + 'h', + 9, + 0, + /* 2719 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'l', + 'h', + 9, + 0, + /* 2729 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'l', + 'h', + 9, + 0, + /* 2739 */ 's', + 'w', + 'p', + 'l', + 'h', + 9, + 0, + /* 2746 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'l', + 'h', + 9, + 0, + /* 2755 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'l', + 'h', + 9, + 0, + /* 2764 */ 'c', + 'a', + 's', + 'l', + 'h', + 9, + 0, + /* 2771 */ 'l', + 'd', + 's', + 'e', + 't', + 'l', + 'h', + 9, + 0, + /* 2780 */ 's', + 'q', + 'd', + 'm', + 'u', + 'l', + 'h', + 9, + 0, + /* 2789 */ 's', + 'q', + 'r', + 'd', + 'm', + 'u', + 'l', + 'h', + 9, + 0, + /* 2799 */ 's', + 'm', + 'u', + 'l', + 'h', + 9, + 0, + /* 2806 */ 'u', + 'm', + 'u', + 'l', + 'h', + 9, + 0, + /* 2813 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'l', + 'h', + 9, + 0, + /* 2823 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'l', + 'h', + 9, + 0, + /* 2833 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'h', + 9, + 0, + /* 2842 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'h', + 9, + 0, + /* 2851 */ 's', + 'w', + 'p', + 'h', + 9, + 0, + /* 2857 */ 'l', + 'd', + '1', + 'r', + 'q', + 'h', + 9, + 0, + /* 2865 */ 'l', + 'd', + '1', + 'r', + 'h', + 9, + 0, + /* 2872 */ 'l', + 'd', + 'a', + 'r', + 'h', + 9, + 0, + /* 2879 */ 'l', + 'd', + 'l', + 'a', + 'r', + 'h', + 9, + 0, + /* 2887 */ 'l', + 'd', + 'r', + 'h', + 9, + 0, + /* 2893 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'h', + 9, + 0, + /* 2901 */ 's', + 't', + 'l', + 'l', + 'r', + 'h', + 9, + 0, + /* 2909 */ 's', + 't', + 'l', + 'r', + 'h', + 9, + 0, + /* 2916 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'h', + 9, + 0, + /* 2924 */ 'l', + 'd', + 'a', + 'p', + 'r', + 'h', + 9, + 0, + /* 2932 */ 'l', + 'd', + 't', + 'r', + 'h', + 9, + 0, + /* 2939 */ 's', + 't', + 'r', + 'h', + 9, + 0, + /* 2945 */ 's', + 't', + 't', + 'r', + 'h', + 9, + 0, + /* 2952 */ 'l', + 'd', + 'u', + 'r', + 'h', + 9, + 0, + /* 2959 */ 's', + 't', + 'l', + 'u', + 'r', + 'h', + 9, + 0, + /* 2967 */ 'l', + 'd', + 'a', + 'p', + 'u', + 'r', + 'h', + 9, + 0, + /* 2976 */ 's', + 't', + 'u', + 'r', + 'h', + 9, + 0, + /* 2983 */ 'l', + 'd', + 'a', + 'x', + 'r', + 'h', + 9, + 0, + /* 2991 */ 'l', + 'd', + 'x', + 'r', + 'h', + 9, + 0, + /* 2998 */ 's', + 't', + 'l', + 'x', + 'r', + 'h', + 9, + 0, + /* 3006 */ 's', + 't', + 'x', + 'r', + 'h', + 9, + 0, + /* 3013 */ 'l', + 'd', + '1', + 's', + 'h', + 9, + 0, + /* 3020 */ 'l', + 'd', + 'f', + 'f', + '1', + 's', + 'h', + 9, + 0, + /* 3029 */ 'l', + 'd', + 'n', + 'f', + '1', + 's', + 'h', + 9, + 0, + /* 3038 */ 'c', + 'a', + 's', + 'h', + 9, + 0, + /* 3044 */ 's', + 'q', + 'r', + 'd', + 'm', + 'l', + 's', + 'h', + 9, + 0, + /* 3054 */ 'l', + 'd', + '1', + 'r', + 's', + 'h', + 9, + 0, + /* 3062 */ 'l', + 'd', + 'r', + 's', + 'h', + 9, + 0, + /* 3069 */ 'l', + 'd', + 't', + 'r', + 's', + 'h', + 9, + 0, + /* 3077 */ 'l', + 'd', + 'u', + 'r', + 's', + 'h', + 9, + 0, + /* 3085 */ 'l', + 'd', + 'a', + 'p', + 'u', + 'r', + 's', + 'h', + 9, + 0, + /* 3095 */ 'l', + 'd', + 's', + 'e', + 't', + 'h', + 9, + 0, + /* 3103 */ 'c', + 'n', + 't', + 'h', + 9, + 0, + /* 3109 */ 's', + 'x', + 't', + 'h', + 9, + 0, + /* 3115 */ 'u', + 'x', + 't', + 'h', + 9, + 0, + /* 3121 */ 'r', + 'e', + 'v', + 'h', + 9, + 0, + /* 3127 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'h', + 9, + 0, + /* 3136 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'h', + 9, + 0, + /* 3145 */ 'x', + 'p', + 'a', + 'c', + 'i', + 9, + 0, + /* 3152 */ 'p', + 'u', + 'n', + 'p', + 'k', + 'h', + 'i', + 9, + 0, + /* 3161 */ 's', + 'u', + 'n', + 'p', + 'k', + 'h', + 'i', + 9, + 0, + /* 3170 */ 'u', + 'u', + 'n', + 'p', + 'k', + 'h', + 'i', + 9, + 0, + /* 3179 */ 'c', + 'm', + 'h', + 'i', + 9, + 0, + /* 3185 */ 'c', + 'm', + 'p', + 'h', + 'i', + 9, + 0, + /* 3192 */ 's', + 'l', + 'i', + 9, + 0, + /* 3197 */ 'm', + 'v', + 'n', + 'i', + 9, + 0, + /* 3203 */ 's', + 'r', + 'i', + 9, + 0, + /* 3208 */ 'f', + 'r', + 'i', + 'n', + 't', + 'i', + 9, + 0, + /* 3216 */ 'm', + 'o', + 'v', + 'i', + 9, + 0, + /* 3222 */ 'b', + 'r', + 'k', + 9, + 0, + /* 3227 */ 'm', + 'o', + 'v', + 'k', + 9, + 0, + /* 3233 */ 's', + 'a', + 'b', + 'a', + 'l', + 9, + 0, + /* 3240 */ 'u', + 'a', + 'b', + 'a', + 'l', + 9, + 0, + /* 3247 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'a', + 'l', + 9, + 0, + /* 3256 */ 's', + 'q', + 'd', + 'm', + 'l', + 'a', + 'l', + 9, + 0, + /* 3265 */ 's', + 'm', + 'l', + 'a', + 'l', + 9, + 0, + /* 3272 */ 'u', + 'm', + 'l', + 'a', + 'l', + 9, + 0, + /* 3279 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'a', + 'l', + 9, + 0, + /* 3289 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'a', + 'l', + 9, + 0, + /* 3299 */ 'c', + 'a', + 's', + 'p', + 'a', + 'l', + 9, + 0, + /* 3307 */ 's', + 'w', + 'p', + 'a', + 'l', + 9, + 0, + /* 3314 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'a', + 'l', + 9, + 0, + /* 3323 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'a', + 'l', + 9, + 0, + /* 3332 */ 'c', + 'a', + 's', + 'a', + 'l', + 9, + 0, + /* 3339 */ 'l', + 'd', + 's', + 'e', + 't', + 'a', + 'l', + 9, + 0, + /* 3348 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'a', + 'l', + 9, + 0, + /* 3358 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'a', + 'l', + 9, + 0, + /* 3368 */ 't', + 'b', + 'l', + 9, + 0, + /* 3373 */ 's', + 'm', + 's', + 'u', + 'b', + 'l', + 9, + 0, + /* 3381 */ 'u', + 'm', + 's', + 'u', + 'b', + 'l', + 9, + 0, + /* 3389 */ 's', + 's', + 'u', + 'b', + 'l', + 9, + 0, + /* 3396 */ 'u', + 's', + 'u', + 'b', + 'l', + 9, + 0, + /* 3403 */ 's', + 'a', + 'b', + 'd', + 'l', + 9, + 0, + /* 3410 */ 'u', + 'a', + 'b', + 'd', + 'l', + 9, + 0, + /* 3417 */ 'l', + 'd', + 'a', + 'd', + 'd', + 'l', + 9, + 0, + /* 3425 */ 's', + 'm', + 'a', + 'd', + 'd', + 'l', + 9, + 0, + /* 3433 */ 'u', + 'm', + 'a', + 'd', + 'd', + 'l', + 9, + 0, + /* 3441 */ 's', + 'a', + 'd', + 'd', + 'l', + 9, + 0, + /* 3448 */ 'u', + 'a', + 'd', + 'd', + 'l', + 9, + 0, + /* 3455 */ 'f', + 'c', + 's', + 'e', + 'l', + 9, + 0, + /* 3462 */ 'f', + 't', + 's', + 's', + 'e', + 'l', + 9, + 0, + /* 3470 */ 's', + 'q', + 's', + 'h', + 'l', + 9, + 0, + /* 3477 */ 'u', + 'q', + 's', + 'h', + 'l', + 9, + 0, + /* 3484 */ 's', + 'q', + 'r', + 's', + 'h', + 'l', + 9, + 0, + /* 3492 */ 'u', + 'q', + 'r', + 's', + 'h', + 'l', + 9, + 0, + /* 3500 */ 's', + 'r', + 's', + 'h', + 'l', + 9, + 0, + /* 3507 */ 'u', + 'r', + 's', + 'h', + 'l', + 9, + 0, + /* 3514 */ 's', + 's', + 'h', + 'l', + 9, + 0, + /* 3520 */ 'u', + 's', + 'h', + 'l', + 9, + 0, + /* 3526 */ 's', + 's', + 'h', + 'l', + 'l', + 9, + 0, + /* 3533 */ 'u', + 's', + 'h', + 'l', + 'l', + 9, + 0, + /* 3540 */ 's', + 'q', + 'd', + 'm', + 'u', + 'l', + 'l', + 9, + 0, + /* 3549 */ 'p', + 'm', + 'u', + 'l', + 'l', + 9, + 0, + /* 3556 */ 's', + 'm', + 'u', + 'l', + 'l', + 9, + 0, + /* 3563 */ 'u', + 'm', + 'u', + 'l', + 'l', + 9, + 0, + /* 3570 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 'l', + 9, + 0, + /* 3579 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 'l', + 9, + 0, + /* 3588 */ 'a', + 'd', + 'd', + 'p', + 'l', + 9, + 0, + /* 3595 */ 'c', + 'a', + 's', + 'p', + 'l', + 9, + 0, + /* 3602 */ 's', + 'w', + 'p', + 'l', + 9, + 0, + /* 3608 */ 'l', + 'd', + 'c', + 'l', + 'r', + 'l', + 9, + 0, + /* 3616 */ 'l', + 'd', + 'e', + 'o', + 'r', + 'l', + 9, + 0, + /* 3624 */ 'c', + 'a', + 's', + 'l', + 9, + 0, + /* 3630 */ 'b', + 's', + 'l', + 9, + 0, + /* 3635 */ 's', + 'q', + 'd', + 'm', + 'l', + 's', + 'l', + 9, + 0, + /* 3644 */ 's', + 'm', + 'l', + 's', + 'l', + 9, + 0, + /* 3651 */ 'u', + 'm', + 'l', + 's', + 'l', + 9, + 0, + /* 3658 */ 's', + 'y', + 's', + 'l', + 9, + 0, + /* 3664 */ 'l', + 'd', + 's', + 'e', + 't', + 'l', + 9, + 0, + /* 3672 */ 'f', + 'c', + 'v', + 't', + 'l', + 9, + 0, + /* 3679 */ 'f', + 'm', + 'u', + 'l', + 9, + 0, + /* 3685 */ 'f', + 'n', + 'm', + 'u', + 'l', + 9, + 0, + /* 3692 */ 'p', + 'm', + 'u', + 'l', + 9, + 0, + /* 3698 */ 'f', + 't', + 's', + 'm', + 'u', + 'l', + 9, + 0, + /* 3706 */ 'a', + 'd', + 'd', + 'v', + 'l', + 9, + 0, + /* 3713 */ 'r', + 'd', + 'v', + 'l', + 9, + 0, + /* 3719 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 'l', + 9, + 0, + /* 3728 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 'l', + 9, + 0, + /* 3737 */ 's', + 'h', + 'a', + '1', + 'm', + 9, + 0, + /* 3744 */ 's', + 'b', + 'f', + 'm', + 9, + 0, + /* 3750 */ 'u', + 'b', + 'f', + 'm', + 9, + 0, + /* 3756 */ 'p', + 'r', + 'f', + 'm', + 9, + 0, + /* 3762 */ 'f', + 'm', + 'i', + 'n', + 'n', + 'm', + 9, + 0, + /* 3770 */ 'f', + 'm', + 'a', + 'x', + 'n', + 'm', + 9, + 0, + /* 3778 */ 'd', + 'u', + 'p', + 'm', + 9, + 0, + /* 3784 */ 'f', + 'r', + 'i', + 'n', + 't', + 'm', + 9, + 0, + /* 3792 */ 'p', + 'r', + 'f', + 'u', + 'm', + 9, + 0, + /* 3799 */ 'r', + 's', + 'u', + 'b', + 'h', + 'n', + 9, + 0, + /* 3807 */ 'r', + 'a', + 'd', + 'd', + 'h', + 'n', + 9, + 0, + /* 3815 */ 'f', + 'm', + 'i', + 'n', + 9, + 0, + /* 3821 */ 'l', + 'd', + 's', + 'm', + 'i', + 'n', + 9, + 0, + /* 3829 */ 'l', + 'd', + 'u', + 'm', + 'i', + 'n', + 9, + 0, + /* 3837 */ 'b', + 'r', + 'k', + 'n', + 9, + 0, + /* 3843 */ 'c', + 'c', + 'm', + 'n', + 9, + 0, + /* 3849 */ 'e', + 'o', + 'n', + 9, + 0, + /* 3854 */ 's', + 'q', + 's', + 'h', + 'r', + 'n', + 9, + 0, + /* 3862 */ 'u', + 'q', + 's', + 'h', + 'r', + 'n', + 9, + 0, + /* 3870 */ 's', + 'q', + 'r', + 's', + 'h', + 'r', + 'n', + 9, + 0, + /* 3879 */ 'u', + 'q', + 'r', + 's', + 'h', + 'r', + 'n', + 9, + 0, + /* 3888 */ 'o', + 'r', + 'n', + 9, + 0, + /* 3893 */ 'f', + 'r', + 'i', + 'n', + 't', + 'n', + 9, + 0, + /* 3901 */ 'f', + 'c', + 'v', + 't', + 'n', + 9, + 0, + /* 3908 */ 's', + 'q', + 'x', + 't', + 'n', + 9, + 0, + /* 3915 */ 'u', + 'q', + 'x', + 't', + 'n', + 9, + 0, + /* 3922 */ 's', + 'q', + 's', + 'h', + 'r', + 'u', + 'n', + 9, + 0, + /* 3931 */ 's', + 'q', + 'r', + 's', + 'h', + 'r', + 'u', + 'n', + 9, + 0, + /* 3941 */ 's', + 'q', + 'x', + 't', + 'u', + 'n', + 9, + 0, + /* 3949 */ 'm', + 'o', + 'v', + 'n', + 9, + 0, + /* 3955 */ 'f', + 'c', + 'v', + 't', + 'x', + 'n', + 9, + 0, + /* 3963 */ 'w', + 'h', + 'i', + 'l', + 'e', + 'l', + 'o', + 9, + 0, + /* 3972 */ 'p', + 'u', + 'n', + 'p', + 'k', + 'l', + 'o', + 9, + 0, + /* 3981 */ 's', + 'u', + 'n', + 'p', + 'k', + 'l', + 'o', + 9, + 0, + /* 3990 */ 'u', + 'u', + 'n', + 'p', + 'k', + 'l', + 'o', + 9, + 0, + /* 3999 */ 'c', + 'm', + 'p', + 'l', + 'o', + 9, + 0, + /* 4006 */ 'f', + 'c', + 'm', + 'u', + 'o', + 9, + 0, + /* 4013 */ 's', + 'h', + 'a', + '1', + 'p', + 9, + 0, + /* 4020 */ 's', + 'q', + 'd', + 'e', + 'c', + 'p', + 9, + 0, + /* 4028 */ 'u', + 'q', + 'd', + 'e', + 'c', + 'p', + 9, + 0, + /* 4036 */ 's', + 'q', + 'i', + 'n', + 'c', + 'p', + 9, + 0, + /* 4044 */ 'u', + 'q', + 'i', + 'n', + 'c', + 'p', + 9, + 0, + /* 4052 */ 'f', + 'a', + 'd', + 'd', + 'p', + 9, + 0, + /* 4059 */ 'l', + 'd', + 'p', + 9, + 0, + /* 4064 */ 's', + 'a', + 'd', + 'a', + 'l', + 'p', + 9, + 0, + /* 4072 */ 'u', + 'a', + 'd', + 'a', + 'l', + 'p', + 9, + 0, + /* 4080 */ 's', + 'a', + 'd', + 'd', + 'l', + 'p', + 9, + 0, + /* 4088 */ 'u', + 'a', + 'd', + 'd', + 'l', + 'p', + 9, + 0, + /* 4096 */ 'f', + 'c', + 'c', + 'm', + 'p', + 9, + 0, + /* 4103 */ 'f', + 'c', + 'm', + 'p', + 9, + 0, + /* 4109 */ 'f', + 'm', + 'i', + 'n', + 'n', + 'm', + 'p', + 9, + 0, + /* 4118 */ 'f', + 'm', + 'a', + 'x', + 'n', + 'm', + 'p', + 9, + 0, + /* 4127 */ 'l', + 'd', + 'n', + 'p', + 9, + 0, + /* 4133 */ 'f', + 'm', + 'i', + 'n', + 'p', + 9, + 0, + /* 4140 */ 's', + 'm', + 'i', + 'n', + 'p', + 9, + 0, + /* 4147 */ 'u', + 'm', + 'i', + 'n', + 'p', + 9, + 0, + /* 4154 */ 's', + 't', + 'n', + 'p', + 9, + 0, + /* 4160 */ 'a', + 'd', + 'r', + 'p', + 9, + 0, + /* 4166 */ 'c', + 'a', + 's', + 'p', + 9, + 0, + /* 4172 */ 'c', + 'n', + 't', + 'p', + 9, + 0, + /* 4178 */ 'f', + 'r', + 'i', + 'n', + 't', + 'p', + 9, + 0, + /* 4186 */ 's', + 't', + 'p', + 9, + 0, + /* 4191 */ 'f', + 'd', + 'u', + 'p', + 9, + 0, + /* 4197 */ 's', + 'w', + 'p', + 9, + 0, + /* 4202 */ 'l', + 'd', + 'a', + 'x', + 'p', + 9, + 0, + /* 4209 */ 'f', + 'm', + 'a', + 'x', + 'p', + 9, + 0, + /* 4216 */ 's', + 'm', + 'a', + 'x', + 'p', + 9, + 0, + /* 4223 */ 'u', + 'm', + 'a', + 'x', + 'p', + 9, + 0, + /* 4230 */ 'l', + 'd', + 'x', + 'p', + 9, + 0, + /* 4236 */ 's', + 't', + 'l', + 'x', + 'p', + 9, + 0, + /* 4243 */ 's', + 't', + 'x', + 'p', + 9, + 0, + /* 4249 */ 'f', + 'c', + 'm', + 'e', + 'q', + 9, + 0, + /* 4256 */ 'c', + 't', + 'e', + 'r', + 'm', + 'e', + 'q', + 9, + 0, + /* 4265 */ 'c', + 'm', + 'p', + 'e', + 'q', + 9, + 0, + /* 4272 */ 'l', + 'd', + '1', + 'r', + 9, + 0, + /* 4278 */ 'l', + 'd', + '2', + 'r', + 9, + 0, + /* 4284 */ 'l', + 'd', + '3', + 'r', + 9, + 0, + /* 4290 */ 'l', + 'd', + '4', + 'r', + 9, + 0, + /* 4296 */ 'l', + 'd', + 'a', + 'r', + 9, + 0, + /* 4302 */ 'l', + 'd', + 'l', + 'a', + 'r', + 9, + 0, + /* 4309 */ 'x', + 'a', + 'r', + 9, + 0, + /* 4314 */ 'f', + 's', + 'u', + 'b', + 'r', + 9, + 0, + /* 4321 */ 'a', + 'd', + 'r', + 9, + 0, + /* 4326 */ 'l', + 'd', + 'r', + 9, + 0, + /* 4331 */ 'r', + 'd', + 'f', + 'f', + 'r', + 9, + 0, + /* 4338 */ 'w', + 'r', + 'f', + 'f', + 'r', + 9, + 0, + /* 4345 */ 's', + 'r', + 's', + 'h', + 'r', + 9, + 0, + /* 4352 */ 'u', + 'r', + 's', + 'h', + 'r', + 9, + 0, + /* 4359 */ 's', + 's', + 'h', + 'r', + 9, + 0, + /* 4365 */ 'u', + 's', + 'h', + 'r', + 9, + 0, + /* 4371 */ 'b', + 'l', + 'r', + 9, + 0, + /* 4376 */ 'l', + 'd', + 'c', + 'l', + 'r', + 9, + 0, + /* 4383 */ 's', + 't', + 'l', + 'l', + 'r', + 9, + 0, + /* 4390 */ 'l', + 's', + 'l', + 'r', + 9, + 0, + /* 4396 */ 's', + 't', + 'l', + 'r', + 9, + 0, + /* 4402 */ 'l', + 'd', + 'e', + 'o', + 'r', + 9, + 0, + /* 4409 */ 'n', + 'o', + 'r', + 9, + 0, + /* 4414 */ 'r', + 'o', + 'r', + 9, + 0, + /* 4419 */ 'l', + 'd', + 'a', + 'p', + 'r', + 9, + 0, + /* 4426 */ 'o', + 'r', + 'r', + 9, + 0, + /* 4431 */ 'a', + 's', + 'r', + 'r', + 9, + 0, + /* 4437 */ 'l', + 's', + 'r', + 'r', + 9, + 0, + /* 4443 */ 'a', + 's', + 'r', + 9, + 0, + /* 4448 */ 'l', + 's', + 'r', + 9, + 0, + /* 4453 */ 'm', + 's', + 'r', + 9, + 0, + /* 4458 */ 'i', + 'n', + 's', + 'r', + 9, + 0, + /* 4464 */ 'l', + 'd', + 't', + 'r', + 9, + 0, + /* 4470 */ 's', + 't', + 'r', + 9, + 0, + /* 4475 */ 's', + 't', + 't', + 'r', + 9, + 0, + /* 4481 */ 'e', + 'x', + 't', + 'r', + 9, + 0, + /* 4487 */ 'l', + 'd', + 'u', + 'r', + 9, + 0, + /* 4493 */ 's', + 't', + 'l', + 'u', + 'r', + 9, + 0, + /* 4500 */ 'l', + 'd', + 'a', + 'p', + 'u', + 'r', + 9, + 0, + /* 4508 */ 's', + 't', + 'u', + 'r', + 9, + 0, + /* 4514 */ 'f', + 'd', + 'i', + 'v', + 'r', + 9, + 0, + /* 4521 */ 's', + 'd', + 'i', + 'v', + 'r', + 9, + 0, + /* 4528 */ 'u', + 'd', + 'i', + 'v', + 'r', + 9, + 0, + /* 4535 */ 'l', + 'd', + 'a', + 'x', + 'r', + 9, + 0, + /* 4542 */ 'l', + 'd', + 'x', + 'r', + 9, + 0, + /* 4548 */ 's', + 't', + 'l', + 'x', + 'r', + 9, + 0, + /* 4555 */ 's', + 't', + 'x', + 'r', + 9, + 0, + /* 4561 */ 'c', + 'a', + 's', + 9, + 0, + /* 4566 */ 'b', + 'r', + 'k', + 'a', + 's', + 9, + 0, + /* 4573 */ 'b', + 'r', + 'k', + 'p', + 'a', + 's', + 9, + 0, + /* 4581 */ 'f', + 'c', + 'v', + 't', + 'a', + 's', + 9, + 0, + /* 4589 */ 'f', + 'a', + 'b', + 's', + 9, + 0, + /* 4595 */ 's', + 'q', + 'a', + 'b', + 's', + 9, + 0, + /* 4602 */ 'b', + 'r', + 'k', + 'b', + 's', + 9, + 0, + /* 4609 */ 'b', + 'r', + 'k', + 'p', + 'b', + 's', + 9, + 0, + /* 4617 */ 's', + 'u', + 'b', + 's', + 9, + 0, + /* 4623 */ 's', + 'b', + 'c', + 's', + 9, + 0, + /* 4629 */ 'a', + 'd', + 'c', + 's', + 9, + 0, + /* 4635 */ 'b', + 'i', + 'c', + 's', + 9, + 0, + /* 4641 */ 'a', + 'd', + 'd', + 's', + 9, + 0, + /* 4647 */ 'n', + 'a', + 'n', + 'd', + 's', + 9, + 0, + /* 4654 */ 'p', + 't', + 'r', + 'u', + 'e', + 's', + 9, + 0, + /* 4662 */ 'c', + 'm', + 'h', + 's', + 9, + 0, + /* 4668 */ 'c', + 'm', + 'p', + 'h', + 's', + 9, + 0, + /* 4675 */ 'c', + 'l', + 's', + 9, + 0, + /* 4680 */ 'w', + 'h', + 'i', + 'l', + 'e', + 'l', + 's', + 9, + 0, + /* 4689 */ 'f', + 'm', + 'l', + 's', + 9, + 0, + /* 4695 */ 'f', + 'n', + 'm', + 'l', + 's', + 9, + 0, + /* 4702 */ 'c', + 'm', + 'p', + 'l', + 's', + 9, + 0, + /* 4709 */ 'f', + 'c', + 'v', + 't', + 'm', + 's', + 9, + 0, + /* 4717 */ 'i', + 'n', + 's', + 9, + 0, + /* 4722 */ 'b', + 'r', + 'k', + 'n', + 's', + 9, + 0, + /* 4729 */ 'o', + 'r', + 'n', + 's', + 9, + 0, + /* 4735 */ 'f', + 'c', + 'v', + 't', + 'n', + 's', + 9, + 0, + /* 4743 */ 'f', + 'r', + 'e', + 'c', + 'p', + 's', + 9, + 0, + /* 4751 */ 'f', + 'c', + 'v', + 't', + 'p', + 's', + 9, + 0, + /* 4759 */ 'r', + 'd', + 'f', + 'f', + 'r', + 's', + 9, + 0, + /* 4767 */ 'm', + 'r', + 's', + 9, + 0, + /* 4772 */ 'e', + 'o', + 'r', + 's', + 9, + 0, + /* 4778 */ 'n', + 'o', + 'r', + 's', + 9, + 0, + /* 4784 */ 'o', + 'r', + 'r', + 's', + 9, + 0, + /* 4790 */ 'f', + 'r', + 's', + 'q', + 'r', + 't', + 's', + 9, + 0, + /* 4799 */ 's', + 'y', + 's', + 9, + 0, + /* 4804 */ 'f', + 'c', + 'v', + 't', + 'z', + 's', + 9, + 0, + /* 4812 */ 'f', + 'j', + 'c', + 'v', + 't', + 'z', + 's', + 9, + 0, + /* 4821 */ 'c', + 'o', + 'm', + 'p', + 'a', + 'c', + 't', + 9, + 0, + /* 4830 */ 'r', + 'e', + 't', + 9, + 0, + /* 4835 */ 'l', + 'd', + 's', + 'e', + 't', + 9, + 0, + /* 4842 */ 'f', + 'a', + 'c', + 'g', + 't', + 9, + 0, + /* 4849 */ 'f', + 'c', + 'm', + 'g', + 't', + 9, + 0, + /* 4856 */ 'c', + 'm', + 'p', + 'g', + 't', + 9, + 0, + /* 4863 */ 'r', + 'b', + 'i', + 't', + 9, + 0, + /* 4869 */ 'w', + 'h', + 'i', + 'l', + 'e', + 'l', + 't', + 9, + 0, + /* 4878 */ 'h', + 'l', + 't', + 9, + 0, + /* 4883 */ 'f', + 'c', + 'm', + 'l', + 't', + 9, + 0, + /* 4890 */ 'c', + 'm', + 'p', + 'l', + 't', + 9, + 0, + /* 4897 */ 'c', + 'n', + 't', + 9, + 0, + /* 4902 */ 'h', + 'i', + 'n', + 't', + 9, + 0, + /* 4908 */ 's', + 'd', + 'o', + 't', + 9, + 0, + /* 4914 */ 'u', + 'd', + 'o', + 't', + 9, + 0, + /* 4920 */ 'c', + 'n', + 'o', + 't', + 9, + 0, + /* 4926 */ 'f', + 's', + 'q', + 'r', + 't', + 9, + 0, + /* 4933 */ 'p', + 't', + 'e', + 's', + 't', + 9, + 0, + /* 4940 */ 'p', + 'f', + 'i', + 'r', + 's', + 't', + 9, + 0, + /* 4948 */ 'c', + 'm', + 't', + 's', + 't', + 9, + 0, + /* 4955 */ 'f', + 'c', + 'v', + 't', + 9, + 0, + /* 4961 */ 'p', + 'n', + 'e', + 'x', + 't', + 9, + 0, + /* 4968 */ 'f', + 'c', + 'v', + 't', + 'a', + 'u', + 9, + 0, + /* 4976 */ 's', + 'q', + 's', + 'h', + 'l', + 'u', + 9, + 0, + /* 4984 */ 'f', + 'c', + 'v', + 't', + 'm', + 'u', + 9, + 0, + /* 4992 */ 'f', + 'c', + 'v', + 't', + 'n', + 'u', + 9, + 0, + /* 5000 */ 'f', + 'c', + 'v', + 't', + 'p', + 'u', + 9, + 0, + /* 5008 */ 'f', + 'c', + 'v', + 't', + 'z', + 'u', + 9, + 0, + /* 5016 */ 'f', + 'a', + 'd', + 'd', + 'v', + 9, + 0, + /* 5023 */ 's', + 'a', + 'd', + 'd', + 'v', + 9, + 0, + /* 5030 */ 'u', + 'a', + 'd', + 'd', + 'v', + 9, + 0, + /* 5037 */ 'a', + 'n', + 'd', + 'v', + 9, + 0, + /* 5043 */ 'r', + 'e', + 'v', + 9, + 0, + /* 5048 */ 'f', + 'd', + 'i', + 'v', + 9, + 0, + /* 5054 */ 's', + 'd', + 'i', + 'v', + 9, + 0, + /* 5060 */ 'u', + 'd', + 'i', + 'v', + 9, + 0, + /* 5066 */ 's', + 'a', + 'd', + 'd', + 'l', + 'v', + 9, + 0, + /* 5074 */ 'u', + 'a', + 'd', + 'd', + 'l', + 'v', + 9, + 0, + /* 5082 */ 'f', + 'm', + 'i', + 'n', + 'n', + 'm', + 'v', + 9, + 0, + /* 5091 */ 'f', + 'm', + 'a', + 'x', + 'n', + 'm', + 'v', + 9, + 0, + /* 5100 */ 'f', + 'm', + 'i', + 'n', + 'v', + 9, + 0, + /* 5107 */ 's', + 'm', + 'i', + 'n', + 'v', + 9, + 0, + /* 5114 */ 'u', + 'm', + 'i', + 'n', + 'v', + 9, + 0, + /* 5121 */ 'c', + 's', + 'i', + 'n', + 'v', + 9, + 0, + /* 5128 */ 'f', + 'm', + 'o', + 'v', + 9, + 0, + /* 5134 */ 's', + 'm', + 'o', + 'v', + 9, + 0, + /* 5140 */ 'u', + 'm', + 'o', + 'v', + 9, + 0, + /* 5146 */ 'e', + 'o', + 'r', + 'v', + 9, + 0, + /* 5152 */ 'f', + 'm', + 'a', + 'x', + 'v', + 9, + 0, + /* 5159 */ 's', + 'm', + 'a', + 'x', + 'v', + 9, + 0, + /* 5166 */ 'u', + 'm', + 'a', + 'x', + 'v', + 9, + 0, + /* 5173 */ 'l', + 'd', + '1', + 'w', + 9, + 0, + /* 5179 */ 'l', + 'd', + 'f', + 'f', + '1', + 'w', + 9, + 0, + /* 5187 */ 'l', + 'd', + 'n', + 'f', + '1', + 'w', + 9, + 0, + /* 5195 */ 'l', + 'd', + 'n', + 't', + '1', + 'w', + 9, + 0, + /* 5203 */ 's', + 't', + 'n', + 't', + '1', + 'w', + 9, + 0, + /* 5211 */ 's', + 't', + '1', + 'w', + 9, + 0, + /* 5217 */ 'c', + 'r', + 'c', + '3', + '2', + 'w', + 9, + 0, + /* 5225 */ 'l', + 'd', + '2', + 'w', + 9, + 0, + /* 5231 */ 's', + 't', + '2', + 'w', + 9, + 0, + /* 5237 */ 'l', + 'd', + '3', + 'w', + 9, + 0, + /* 5243 */ 's', + 't', + '3', + 'w', + 9, + 0, + /* 5249 */ 'l', + 'd', + '4', + 'w', + 9, + 0, + /* 5255 */ 's', + 't', + '4', + 'w', + 9, + 0, + /* 5261 */ 's', + 's', + 'u', + 'b', + 'w', + 9, + 0, + /* 5268 */ 'u', + 's', + 'u', + 'b', + 'w', + 9, + 0, + /* 5275 */ 'c', + 'r', + 'c', + '3', + '2', + 'c', + 'w', + 9, + 0, + /* 5284 */ 's', + 'q', + 'd', + 'e', + 'c', + 'w', + 9, + 0, + /* 5292 */ 'u', + 'q', + 'd', + 'e', + 'c', + 'w', + 9, + 0, + /* 5300 */ 's', + 'q', + 'i', + 'n', + 'c', + 'w', + 9, + 0, + /* 5308 */ 'u', + 'q', + 'i', + 'n', + 'c', + 'w', + 9, + 0, + /* 5316 */ 's', + 'a', + 'd', + 'd', + 'w', + 9, + 0, + /* 5323 */ 'u', + 'a', + 'd', + 'd', + 'w', + 9, + 0, + /* 5330 */ 'p', + 'r', + 'f', + 'w', + 9, + 0, + /* 5336 */ 'l', + 'd', + '1', + 'r', + 'q', + 'w', + 9, + 0, + /* 5344 */ 'l', + 'd', + '1', + 'r', + 'w', + 9, + 0, + /* 5351 */ 'l', + 'd', + '1', + 's', + 'w', + 9, + 0, + /* 5358 */ 'l', + 'd', + 'f', + 'f', + '1', + 's', + 'w', + 9, + 0, + /* 5367 */ 'l', + 'd', + 'n', + 'f', + '1', + 's', + 'w', + 9, + 0, + /* 5376 */ 'l', + 'd', + 'p', + 's', + 'w', + 9, + 0, + /* 5383 */ 'l', + 'd', + '1', + 'r', + 's', + 'w', + 9, + 0, + /* 5391 */ 'l', + 'd', + 'r', + 's', + 'w', + 9, + 0, + /* 5398 */ 'l', + 'd', + 't', + 'r', + 's', + 'w', + 9, + 0, + /* 5406 */ 'l', + 'd', + 'u', + 'r', + 's', + 'w', + 9, + 0, + /* 5414 */ 'l', + 'd', + 'a', + 'p', + 'u', + 'r', + 's', + 'w', + 9, + 0, + /* 5424 */ 'c', + 'n', + 't', + 'w', + 9, + 0, + /* 5430 */ 's', + 'x', + 't', + 'w', + 9, + 0, + /* 5436 */ 'u', + 'x', + 't', + 'w', + 9, + 0, + /* 5442 */ 'r', + 'e', + 'v', + 'w', + 9, + 0, + /* 5448 */ 'c', + 'r', + 'c', + '3', + '2', + 'x', + 9, + 0, + /* 5456 */ 'b', + 'c', + 'a', + 'x', + 9, + 0, + /* 5462 */ 'f', + 'm', + 'a', + 'x', + 9, + 0, + /* 5468 */ 'l', + 'd', + 's', + 'm', + 'a', + 'x', + 9, + 0, + /* 5476 */ 'l', + 'd', + 'u', + 'm', + 'a', + 'x', + 9, + 0, + /* 5484 */ 't', + 'b', + 'x', + 9, + 0, + /* 5489 */ 'c', + 'r', + 'c', + '3', + '2', + 'c', + 'x', + 9, + 0, + /* 5498 */ 'i', + 'n', + 'd', + 'e', + 'x', + 9, + 0, + /* 5505 */ 'c', + 'l', + 'r', + 'e', + 'x', + 9, + 0, + /* 5512 */ 'm', + 'o', + 'v', + 'p', + 'r', + 'f', + 'x', + 9, + 0, + /* 5521 */ 'f', + 'm', + 'u', + 'l', + 'x', + 9, + 0, + /* 5528 */ 'f', + 'r', + 'e', + 'c', + 'p', + 'x', + 9, + 0, + /* 5536 */ 'f', + 'r', + 'i', + 'n', + 't', + 'x', + 9, + 0, + /* 5544 */ 's', + 'm', + '4', + 'e', + 'k', + 'e', + 'y', + 9, + 0, + /* 5553 */ 'f', + 'c', + 'p', + 'y', + 9, + 0, + /* 5559 */ 'b', + 'r', + 'a', + 'a', + 'z', + 9, + 0, + /* 5566 */ 'b', + 'l', + 'r', + 'a', + 'a', + 'z', + 9, + 0, + /* 5574 */ 'b', + 'r', + 'a', + 'b', + 'z', + 9, + 0, + /* 5581 */ 'b', + 'l', + 'r', + 'a', + 'b', + 'z', + 9, + 0, + /* 5589 */ 'c', + 'b', + 'z', + 9, + 0, + /* 5594 */ 't', + 'b', + 'z', + 9, + 0, + /* 5599 */ 'c', + 'l', + 'z', + 9, + 0, + /* 5604 */ 'c', + 'b', + 'n', + 'z', + 9, + 0, + /* 5610 */ 't', + 'b', + 'n', + 'z', + 9, + 0, + /* 5616 */ 'f', + 'r', + 'i', + 'n', + 't', + 'z', + 9, + 0, + /* 5624 */ 'm', + 'o', + 'v', + 'z', + 9, + 0, + /* 5630 */ '.', + 't', + 'l', + 's', + 'd', + 'e', + 's', + 'c', + 'c', + 'a', + 'l', + 'l', + 32, + 0, + /* 5644 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'P', + 'a', + 't', + 'c', + 'h', + 'a', + 'b', + 'l', + 'e', + 32, + 'R', + 'E', + 'T', + '.', + 0, + /* 5675 */ 'b', + '.', + 0, + /* 5678 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'y', + 'p', + 'e', + 'd', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 5702 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'C', + 'u', + 's', + 't', + 'o', + 'm', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 5727 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'n', + 't', + 'e', + 'r', + '.', + 0, + /* 5750 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'a', + 'i', + 'l', + 32, + 'C', + 'a', + 'l', + 'l', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 5773 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 5795 */ 'p', + 'a', + 'c', + 'i', + 'a', + '1', + '7', + '1', + '6', + 0, + /* 5805 */ 'a', + 'u', + 't', + 'i', + 'a', + '1', + '7', + '1', + '6', + 0, + /* 5815 */ 'p', + 'a', + 'c', + 'i', + 'b', + '1', + '7', + '1', + '6', + 0, + /* 5825 */ 'a', + 'u', + 't', + 'i', + 'b', + '1', + '7', + '1', + '6', + 0, + /* 5835 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'E', + 'N', + 'D', + 0, + /* 5848 */ 'B', + 'U', + 'N', + 'D', + 'L', + 'E', + 0, + /* 5855 */ 'D', + 'B', + 'G', + '_', + 'V', + 'A', + 'L', + 'U', + 'E', + 0, + /* 5865 */ 'D', + 'B', + 'G', + '_', + 'L', + 'A', + 'B', + 'E', + 'L', + 0, + /* 5875 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'S', + 'T', + 'A', + 'R', + 'T', + 0, + /* 5890 */ 'e', + 'r', + 'e', + 't', + 'a', + 'a', + 0, + /* 5897 */ 'e', + 'r', + 'e', + 't', + 'a', + 'b', + 0, + /* 5904 */ 'x', + 'p', + 'a', + 'c', + 'l', + 'r', + 'i', + 0, + /* 5912 */ '#', + 32, + 'F', + 'E', + 'n', + 't', + 'r', + 'y', + 32, + 'c', + 'a', + 'l', + 'l', + 0, + /* 5926 */ 'p', + 'a', + 'c', + 'i', + 'a', + 's', + 'p', + 0, + /* 5934 */ 'a', + 'u', + 't', + 'i', + 'a', + 's', + 'p', + 0, + /* 5942 */ 'p', + 'a', + 'c', + 'i', + 'b', + 's', + 'p', + 0, + /* 5950 */ 'a', + 'u', + 't', + 'i', + 'b', + 's', + 'p', + 0, + /* 5958 */ 's', + 'e', + 't', + 'f', + 'f', + 'r', + 0, + /* 5965 */ 'd', + 'r', + 'p', + 's', + 0, + /* 5970 */ 'e', + 'r', + 'e', + 't', + 0, + /* 5975 */ 'c', + 'f', + 'i', + 'n', + 'v', + 0, + /* 5981 */ 'p', + 'a', + 'c', + 'i', + 'a', + 'z', + 0, + /* 5988 */ 'a', + 'u', + 't', + 'i', + 'a', + 'z', + 0, + /* 5995 */ 'p', + 'a', + 'c', + 'i', + 'b', + 'z', + 0, + /* 6002 */ 'a', + 'u', + 't', + 'i', + 'b', + 'z', + 0, }; #endif static const uint32_t OpInfo0[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 5856U, // DBG_VALUE - 5866U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 5849U, // BUNDLE - 5876U, // LIFETIME_START - 5836U, // LIFETIME_END - 0U, // STACKMAP - 5913U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 5728U, // PATCHABLE_FUNCTION_ENTER - 5645U, // PATCHABLE_RET - 5774U, // PATCHABLE_FUNCTION_EXIT - 5751U, // PATCHABLE_TAIL_CALL - 5703U, // PATCHABLE_EVENT_CALL - 5679U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDE - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SSUBO - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_BSWAP - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 12783U, // ABS_ZPmZ_B - 20975U, // ABS_ZPmZ_D - 2181591535U, // ABS_ZPmZ_H - 37359U, // ABS_ZPmZ_S - 68202991U, // ABSv16i8 - 2248200687U, // ABSv1i64 - 68727279U, // ABSv2i32 - 2216735215U, // ABSv2i64 - 69775855U, // ABSv4i16 - 2217783791U, // ABSv4i32 - 70824431U, // ABSv8i16 - 2218832367U, // ABSv8i8 - 100717078U, // ADCSWr - 100717078U, // ADCSXr - 100714262U, // ADCWr - 100714262U, // ADCXr - 2216210145U, // ADDHNv2i64_v2i32 - 2284904787U, // ADDHNv2i64_v4i32 - 69775073U, // ADDHNv4i32_v4i16 - 137945427U, // ADDHNv4i32_v8i16 - 2282807635U, // ADDHNv8i16_v16i8 - 2218831585U, // ADDHNv8i16_v8i8 - 100716037U, // ADDPL_XXI - 68202454U, // ADDPv16i8 - 2216210390U, // ADDPv2i32 - 2216734678U, // ADDPv2i64 - 2214645718U, // ADDPv2i64p - 69775318U, // ADDPv4i16 - 70299606U, // ADDPv4i32 - 2218307542U, // ADDPv8i16 - 2218831830U, // ADDPv8i8 - 100717090U, // ADDSWri - 0U, // ADDSWrr - 100717090U, // ADDSWrs - 100717090U, // ADDSWrx - 100717090U, // ADDSXri - 0U, // ADDSXrr - 100717090U, // ADDSXrs - 100717090U, // ADDSXrx - 100717090U, // ADDSXrx64 - 100716155U, // ADDVL_XXI - 67163034U, // ADDVv16i8v - 67163034U, // ADDVv4i16v - 2214646682U, // ADDVv4i32v - 67163034U, // ADDVv8i16v - 2214646682U, // ADDVv8i8v - 100714463U, // ADDWri - 0U, // ADDWrr - 100714463U, // ADDWrs - 100714463U, // ADDWrx - 100714463U, // ADDXri - 0U, // ADDXrr - 100714463U, // ADDXrs - 100714463U, // ADDXrx - 100714463U, // ADDXrx64 - 167782367U, // ADD_ZI_B - 201344991U, // ADD_ZI_D - 239626207U, // ADD_ZI_H - 268470239U, // ADD_ZI_S - 302000095U, // ADD_ZPmZ_B - 302008287U, // ADD_ZPmZ_D - 2186307551U, // ADD_ZPmZ_H - 302024671U, // ADD_ZPmZ_S - 167782367U, // ADD_ZZZ_B - 201344991U, // ADD_ZZZ_D - 2387109855U, // ADD_ZZZ_H - 268470239U, // ADD_ZZZ_S - 0U, // ADDlowTLS - 68200415U, // ADDv16i8 - 100714463U, // ADDv1i64 - 2216208351U, // ADDv2i32 - 2216732639U, // ADDv2i64 - 69773279U, // ADDv4i16 - 70297567U, // ADDv4i32 - 2218305503U, // ADDv8i16 - 2218829791U, // ADDv8i8 - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 2248200418U, // ADR - 335597633U, // ADRP - 207114466U, // ADR_LSL_ZZZ_D_0 - 207114466U, // ADR_LSL_ZZZ_D_1 - 207114466U, // ADR_LSL_ZZZ_D_2 - 207114466U, // ADR_LSL_ZZZ_D_3 - 274239714U, // ADR_LSL_ZZZ_S_0 - 274239714U, // ADR_LSL_ZZZ_S_1 - 274239714U, // ADR_LSL_ZZZ_S_2 - 274239714U, // ADR_LSL_ZZZ_S_3 - 207114466U, // ADR_SXTW_ZZZ_D_0 - 207114466U, // ADR_SXTW_ZZZ_D_1 - 207114466U, // ADR_SXTW_ZZZ_D_2 - 207114466U, // ADR_SXTW_ZZZ_D_3 - 207114466U, // ADR_UXTW_ZZZ_D_0 - 207114466U, // ADR_UXTW_ZZZ_D_1 - 207114466U, // ADR_UXTW_ZZZ_D_2 - 207114466U, // ADR_UXTW_ZZZ_D_3 - 135325775U, // AESDrr - 135325907U, // AESErr - 68200224U, // AESIMCrr - 0U, // AESIMCrrTied - 68200232U, // AESMCrr - 0U, // AESMCrrTied - 100717097U, // ANDSWri - 0U, // ANDSWrr - 100717097U, // ANDSWrs - 100717097U, // ANDSXri - 0U, // ANDSXrr - 100717097U, // ANDSXrs - 302002729U, // ANDS_PPzPP - 302044078U, // ANDV_VPZ_B - 302044078U, // ANDV_VPZ_D - 302044078U, // ANDV_VPZ_H - 302044078U, // ANDV_VPZ_S - 100714549U, // ANDWri - 0U, // ANDWrr - 100714549U, // ANDWrs - 100714549U, // ANDXri - 0U, // ANDXrr - 100714549U, // ANDXrs - 302000181U, // AND_PPzPP - 201345077U, // AND_ZI - 302000181U, // AND_ZPmZ_B - 302008373U, // AND_ZPmZ_D - 2186307637U, // AND_ZPmZ_H - 302024757U, // AND_ZPmZ_S - 201345077U, // AND_ZZZ - 68200501U, // ANDv16i8 - 2218829877U, // ANDv8i8 - 302000201U, // ASRD_ZPmI_B - 302008393U, // ASRD_ZPmI_D - 2186307657U, // ASRD_ZPmI_H - 302024777U, // ASRD_ZPmI_S - 302002512U, // ASRR_ZPmZ_B - 302010704U, // ASRR_ZPmZ_D - 2186309968U, // ASRR_ZPmZ_H - 302027088U, // ASRR_ZPmZ_S - 100716892U, // ASRVWr - 100716892U, // ASRVXr - 302002524U, // ASR_WIDE_ZPmZ_B - 2186309980U, // ASR_WIDE_ZPmZ_H - 302027100U, // ASR_WIDE_ZPmZ_S - 167784796U, // ASR_WIDE_ZZZ_B - 2387112284U, // ASR_WIDE_ZZZ_H - 268472668U, // ASR_WIDE_ZZZ_S - 302002524U, // ASR_ZPmI_B - 302010716U, // ASR_ZPmI_D - 2186309980U, // ASR_ZPmI_H - 302027100U, // ASR_ZPmI_S - 302002524U, // ASR_ZPmZ_B - 302010716U, // ASR_ZPmZ_D - 2186309980U, // ASR_ZPmZ_H - 302027100U, // ASR_ZPmZ_S - 167784796U, // ASR_ZZI_B - 201347420U, // ASR_ZZI_D - 239628636U, // ASR_ZZI_H - 268472668U, // ASR_ZZI_S - 2248196751U, // AUTDA - 2248197244U, // AUTDB - 6341460U, // AUTDZA - 6342386U, // AUTDZB - 2248196772U, // AUTIA - 5806U, // AUTIA1716 - 5935U, // AUTIASP - 5989U, // AUTIAZ - 2248197264U, // AUTIB - 5826U, // AUTIB1716 - 5951U, // AUTIBSP - 6003U, // AUTIBZ - 6341476U, // AUTIZA - 6342402U, // AUTIZB - 66415U, // B - 68203857U, // BCAX - 369151650U, // BFMWri - 369151650U, // BFMXri - 0U, // BICSWrr - 100717084U, // BICSWrs - 0U, // BICSXrr - 100717084U, // BICSXrs - 302002716U, // BICS_PPzPP - 0U, // BICWrr - 100714267U, // BICWrs - 0U, // BICXrr - 100714267U, // BICXrs - 301999899U, // BIC_PPzPP - 301999899U, // BIC_ZPmZ_B - 302008091U, // BIC_ZPmZ_D - 2186307355U, // BIC_ZPmZ_H - 302024475U, // BIC_ZPmZ_S - 201344795U, // BIC_ZZZ - 68200219U, // BICv16i8 - 404285211U, // BICv2i32 - 405333787U, // BICv4i16 - 405858075U, // BICv4i32 - 406382363U, // BICv8i16 - 2218829595U, // BICv8i8 - 68200698U, // BIFv16i8 - 2218830074U, // BIFv8i8 - 135328513U, // BITv16i8 - 2285957889U, // BITv8i8 - 68906U, // BL - 6344980U, // BLR - 2248196710U, // BLRAA - 6346175U, // BLRAAZ - 2248197127U, // BLRAB - 6346190U, // BLRABZ - 6344926U, // BR - 2248196697U, // BRAA - 6346168U, // BRAAZ - 2248197114U, // BRAB - 6346183U, // BRABZ - 76951U, // BRK - 302002647U, // BRKAS_PPzP - 8875U, // BRKA_PPmP - 301998763U, // BRKA_PPzP - 302002683U, // BRKBS_PPzP - 9367U, // BRKB_PPmP - 301999255U, // BRKB_PPzP - 302002803U, // BRKNS_PPzP - 302001918U, // BRKN_PPzP - 302002654U, // BRKPAS_PPzPP - 301998807U, // BRKPA_PPzPP - 302002690U, // BRKPBS_PPzPP - 301999474U, // BRKPB_PPzPP - 135327279U, // BSLv16i8 - 2285956655U, // BSLv8i8 - 87596U, // Bcc - 2516673568U, // CASAB - 2516675032U, // CASAH - 2516673753U, // CASALB - 2516675183U, // CASALH - 2516675845U, // CASALW - 2516675845U, // CASALX - 2516673308U, // CASAW - 2516673308U, // CASAX - 2516674100U, // CASB - 2516675551U, // CASH - 2516673847U, // CASLB - 2516675277U, // CASLH - 2516676137U, // CASLW - 2516676137U, // CASLX - 101604U, // CASPALW - 109796U, // CASPALX - 99038U, // CASPAW - 107230U, // CASPAX - 101900U, // CASPLW - 110092U, // CASPLX - 102471U, // CASPW - 110663U, // CASPX - 2516677074U, // CASW - 2516677074U, // CASX - 436262373U, // CBNZW - 436262373U, // CBNZX - 436262358U, // CBZW - 436262358U, // CBZX - 100716292U, // CCMNWi - 100716292U, // CCMNWr - 100716292U, // CCMNXi - 100716292U, // CCMNXr - 100716546U, // CCMPWi - 100716546U, // CCMPWr - 100716546U, // CCMPXi - 100716546U, // CCMPXr - 5976U, // CFINV - 302039858U, // CLASTA_RPZ_B - 302039858U, // CLASTA_RPZ_D - 302039858U, // CLASTA_RPZ_H - 302039858U, // CLASTA_RPZ_S - 302039858U, // CLASTA_VPZ_B - 302039858U, // CLASTA_VPZ_D - 302039858U, // CLASTA_VPZ_H - 302039858U, // CLASTA_VPZ_S - 301998898U, // CLASTA_ZPZ_B - 302007090U, // CLASTA_ZPZ_D - 2387632946U, // CLASTA_ZPZ_H - 302023474U, // CLASTA_ZPZ_S - 302040717U, // CLASTB_RPZ_B - 302040717U, // CLASTB_RPZ_D - 302040717U, // CLASTB_RPZ_H - 302040717U, // CLASTB_RPZ_S - 302040717U, // CLASTB_VPZ_B - 302040717U, // CLASTB_VPZ_D - 302040717U, // CLASTB_VPZ_H - 302040717U, // CLASTB_VPZ_S - 301999757U, // CLASTB_ZPZ_B - 302007949U, // CLASTB_ZPZ_D - 2387633805U, // CLASTB_ZPZ_H - 302024333U, // CLASTB_ZPZ_S - 6346114U, // CLREX - 2248200772U, // CLSWr - 2248200772U, // CLSXr - 12868U, // CLS_ZPmZ_B - 21060U, // CLS_ZPmZ_D - 2181591620U, // CLS_ZPmZ_H - 37444U, // CLS_ZPmZ_S - 68203076U, // CLSv16i8 - 68727364U, // CLSv2i32 - 69775940U, // CLSv4i16 - 2217783876U, // CLSv4i32 - 70824516U, // CLSv8i16 - 2218832452U, // CLSv8i8 - 2248201696U, // CLZWr - 2248201696U, // CLZXr - 13792U, // CLZ_ZPmZ_B - 21984U, // CLZ_ZPmZ_D - 2181592544U, // CLZ_ZPmZ_H - 38368U, // CLZ_ZPmZ_S - 68204000U, // CLZv16i8 - 68728288U, // CLZv2i32 - 69776864U, // CLZv4i16 - 2217784800U, // CLZv4i32 - 70825440U, // CLZv8i16 - 2218833376U, // CLZv8i8 - 68202651U, // CMEQv16i8 - 68202651U, // CMEQv16i8rz - 100716699U, // CMEQv1i64 - 2248200347U, // CMEQv1i64rz - 2216210587U, // CMEQv2i32 - 68726939U, // CMEQv2i32rz - 2216734875U, // CMEQv2i64 - 2216734875U, // CMEQv2i64rz - 69775515U, // CMEQv4i16 - 69775515U, // CMEQv4i16rz - 70299803U, // CMEQv4i32 - 2217783451U, // CMEQv4i32rz - 2218307739U, // CMEQv8i16 - 70824091U, // CMEQv8i16rz - 2218832027U, // CMEQv8i8 - 2218832027U, // CMEQv8i8rz - 68200561U, // CMGEv16i8 - 68200561U, // CMGEv16i8rz - 100714609U, // CMGEv1i64 - 2248198257U, // CMGEv1i64rz - 2216208497U, // CMGEv2i32 - 68724849U, // CMGEv2i32rz - 2216732785U, // CMGEv2i64 - 2216732785U, // CMGEv2i64rz - 69773425U, // CMGEv4i16 - 69773425U, // CMGEv4i16rz - 70297713U, // CMGEv4i32 - 2217781361U, // CMGEv4i32rz - 2218305649U, // CMGEv8i16 - 70822001U, // CMGEv8i16rz - 2218829937U, // CMGEv8i8 - 2218829937U, // CMGEv8i8rz - 68203251U, // CMGTv16i8 - 68203251U, // CMGTv16i8rz - 100717299U, // CMGTv1i64 - 2248200947U, // CMGTv1i64rz - 2216211187U, // CMGTv2i32 - 68727539U, // CMGTv2i32rz - 2216735475U, // CMGTv2i64 - 2216735475U, // CMGTv2i64rz - 69776115U, // CMGTv4i16 - 69776115U, // CMGTv4i16rz - 70300403U, // CMGTv4i32 - 2217784051U, // CMGTv4i32rz - 2218308339U, // CMGTv8i16 - 70824691U, // CMGTv8i16rz - 2218832627U, // CMGTv8i8 - 2218832627U, // CMGTv8i8rz - 68201580U, // CMHIv16i8 - 100715628U, // CMHIv1i64 - 2216209516U, // CMHIv2i32 - 2216733804U, // CMHIv2i64 - 69774444U, // CMHIv4i16 - 70298732U, // CMHIv4i32 - 2218306668U, // CMHIv8i16 - 2218830956U, // CMHIv8i8 - 68203063U, // CMHSv16i8 - 100717111U, // CMHSv1i64 - 2216210999U, // CMHSv2i32 - 2216735287U, // CMHSv2i64 - 69775927U, // CMHSv4i16 - 70300215U, // CMHSv4i32 - 2218308151U, // CMHSv8i16 - 2218832439U, // CMHSv8i8 - 68200592U, // CMLEv16i8rz - 2248198288U, // CMLEv1i64rz - 68724880U, // CMLEv2i32rz - 2216732816U, // CMLEv2i64rz - 69773456U, // CMLEv4i16rz - 2217781392U, // CMLEv4i32rz - 70822032U, // CMLEv8i16rz - 2218829968U, // CMLEv8i8rz - 68203285U, // CMLTv16i8rz - 2248200981U, // CMLTv1i64rz - 68727573U, // CMLTv2i32rz - 2216735509U, // CMLTv2i64rz - 69776149U, // CMLTv4i16rz - 2217784085U, // CMLTv4i32rz - 70824725U, // CMLTv8i16rz - 2218832661U, // CMLTv8i8rz - 302002346U, // CMPEQ_PPzZI_B - 302010538U, // CMPEQ_PPzZI_D - 2622517418U, // CMPEQ_PPzZI_H - 302026922U, // CMPEQ_PPzZI_S - 302002346U, // CMPEQ_PPzZZ_B - 302010538U, // CMPEQ_PPzZZ_D - 2622517418U, // CMPEQ_PPzZZ_H - 302026922U, // CMPEQ_PPzZZ_S - 302002346U, // CMPEQ_WIDE_PPzZZ_B - 2622517418U, // CMPEQ_WIDE_PPzZZ_H - 302026922U, // CMPEQ_WIDE_PPzZZ_S - 302000247U, // CMPGE_PPzZI_B - 302008439U, // CMPGE_PPzZI_D - 2622515319U, // CMPGE_PPzZI_H - 302024823U, // CMPGE_PPzZI_S - 302000247U, // CMPGE_PPzZZ_B - 302008439U, // CMPGE_PPzZZ_D - 2622515319U, // CMPGE_PPzZZ_H - 302024823U, // CMPGE_PPzZZ_S - 302000247U, // CMPGE_WIDE_PPzZZ_B - 2622515319U, // CMPGE_WIDE_PPzZZ_H - 302024823U, // CMPGE_WIDE_PPzZZ_S - 302002937U, // CMPGT_PPzZI_B - 302011129U, // CMPGT_PPzZI_D - 2622518009U, // CMPGT_PPzZI_H - 302027513U, // CMPGT_PPzZI_S - 302002937U, // CMPGT_PPzZZ_B - 302011129U, // CMPGT_PPzZZ_D - 2622518009U, // CMPGT_PPzZZ_H - 302027513U, // CMPGT_PPzZZ_S - 302002937U, // CMPGT_WIDE_PPzZZ_B - 2622518009U, // CMPGT_WIDE_PPzZZ_H - 302027513U, // CMPGT_WIDE_PPzZZ_S - 302001266U, // CMPHI_PPzZI_B - 302009458U, // CMPHI_PPzZI_D - 2622516338U, // CMPHI_PPzZI_H - 302025842U, // CMPHI_PPzZI_S - 302001266U, // CMPHI_PPzZZ_B - 302009458U, // CMPHI_PPzZZ_D - 2622516338U, // CMPHI_PPzZZ_H - 302025842U, // CMPHI_PPzZZ_S - 302001266U, // CMPHI_WIDE_PPzZZ_B - 2622516338U, // CMPHI_WIDE_PPzZZ_H - 302025842U, // CMPHI_WIDE_PPzZZ_S - 302002749U, // CMPHS_PPzZI_B - 302010941U, // CMPHS_PPzZI_D - 2622517821U, // CMPHS_PPzZI_H - 302027325U, // CMPHS_PPzZI_S - 302002749U, // CMPHS_PPzZZ_B - 302010941U, // CMPHS_PPzZZ_D - 2622517821U, // CMPHS_PPzZZ_H - 302027325U, // CMPHS_PPzZZ_S - 302002749U, // CMPHS_WIDE_PPzZZ_B - 2622517821U, // CMPHS_WIDE_PPzZZ_H - 302027325U, // CMPHS_WIDE_PPzZZ_S - 302000278U, // CMPLE_PPzZI_B - 302008470U, // CMPLE_PPzZI_D - 2622515350U, // CMPLE_PPzZI_H - 302024854U, // CMPLE_PPzZI_S - 302000278U, // CMPLE_WIDE_PPzZZ_B - 2622515350U, // CMPLE_WIDE_PPzZZ_H - 302024854U, // CMPLE_WIDE_PPzZZ_S - 302002080U, // CMPLO_PPzZI_B - 302010272U, // CMPLO_PPzZI_D - 2622517152U, // CMPLO_PPzZI_H - 302026656U, // CMPLO_PPzZI_S - 302002080U, // CMPLO_WIDE_PPzZZ_B - 2622517152U, // CMPLO_WIDE_PPzZZ_H - 302026656U, // CMPLO_WIDE_PPzZZ_S - 302002783U, // CMPLS_PPzZI_B - 302010975U, // CMPLS_PPzZI_D - 2622517855U, // CMPLS_PPzZI_H - 302027359U, // CMPLS_PPzZI_S - 302002783U, // CMPLS_WIDE_PPzZZ_B - 2622517855U, // CMPLS_WIDE_PPzZZ_H - 302027359U, // CMPLS_WIDE_PPzZZ_S - 302002971U, // CMPLT_PPzZI_B - 302011163U, // CMPLT_PPzZI_D - 2622518043U, // CMPLT_PPzZI_H - 302027547U, // CMPLT_PPzZI_S - 302002971U, // CMPLT_WIDE_PPzZZ_B - 2622518043U, // CMPLT_WIDE_PPzZZ_H - 302027547U, // CMPLT_WIDE_PPzZZ_S - 302000301U, // CMPNE_PPzZI_B - 302008493U, // CMPNE_PPzZI_D - 2622515373U, // CMPNE_PPzZI_H - 302024877U, // CMPNE_PPzZI_S - 302000301U, // CMPNE_PPzZZ_B - 302008493U, // CMPNE_PPzZZ_D - 2622515373U, // CMPNE_PPzZZ_H - 302024877U, // CMPNE_PPzZZ_S - 302000301U, // CMPNE_WIDE_PPzZZ_B - 2622515373U, // CMPNE_WIDE_PPzZZ_H - 302024877U, // CMPNE_WIDE_PPzZZ_S - 0U, // CMP_SWAP_128 - 0U, // CMP_SWAP_16 - 0U, // CMP_SWAP_32 - 0U, // CMP_SWAP_64 - 0U, // CMP_SWAP_8 - 68203349U, // CMTSTv16i8 - 100717397U, // CMTSTv1i64 - 2216211285U, // CMTSTv2i32 - 2216735573U, // CMTSTv2i64 - 69776213U, // CMTSTv4i16 - 70300501U, // CMTSTv4i32 - 2218308437U, // CMTSTv8i16 - 2218832725U, // CMTSTv8i8 - 13113U, // CNOT_ZPmZ_B - 21305U, // CNOT_ZPmZ_D - 2181591865U, // CNOT_ZPmZ_H - 37689U, // CNOT_ZPmZ_S - 503367303U, // CNTB_XPiI - 503367765U, // CNTD_XPiI - 503368736U, // CNTH_XPiI - 302043213U, // CNTP_XPP_B - 302043213U, // CNTP_XPP_D - 302043213U, // CNTP_XPP_H - 302043213U, // CNTP_XPP_S - 503371057U, // CNTW_XPiI - 13090U, // CNT_ZPmZ_B - 21282U, // CNT_ZPmZ_D - 2181591842U, // CNT_ZPmZ_H - 37666U, // CNT_ZPmZ_S - 68203298U, // CNTv16i8 - 2218832674U, // CNTv8i8 - 302011094U, // COMPACT_ZPZ_D - 302027478U, // COMPACT_ZPZ_S - 13747U, // CPY_ZPmI_B - 21939U, // CPY_ZPmI_D - 2181592499U, // CPY_ZPmI_H - 38323U, // CPY_ZPmI_S - 13747U, // CPY_ZPmR_B - 21939U, // CPY_ZPmR_D - 34108851U, // CPY_ZPmR_H - 38323U, // CPY_ZPmR_S - 13747U, // CPY_ZPmV_B - 21939U, // CPY_ZPmV_D - 34108851U, // CPY_ZPmV_H - 38323U, // CPY_ZPmV_S - 302003635U, // CPY_ZPzI_B - 302011827U, // CPY_ZPzI_D - 2622518707U, // CPY_ZPzI_H - 302028211U, // CPY_ZPzI_S - 67163146U, // CPYi16 - 2214646794U, // CPYi32 - 67163146U, // CPYi64 - 2214646794U, // CPYi8 - 100713377U, // CRC32Brr - 100713540U, // CRC32CBrr - 100715004U, // CRC32CHrr - 100717724U, // CRC32CWrr - 100717938U, // CRC32CXrr - 100714851U, // CRC32Hrr - 100717666U, // CRC32Wrr - 100717897U, // CRC32Xrr - 100715905U, // CSELWr - 100715905U, // CSELXr - 100714287U, // CSINCWr - 100714287U, // CSINCXr - 100717570U, // CSINVWr - 100717570U, // CSINVXr - 100714784U, // CSNEGWr - 100714784U, // CSNEGXr - 2248200353U, // CTERMEQ_WW - 2248200353U, // CTERMEQ_XX - 2248198308U, // CTERMNE_WW - 2248198308U, // CTERMNE_XX - 0U, // CompilerBarrier - 73783U, // DCPS1 - 74194U, // DCPS2 - 74260U, // DCPS3 - 536921167U, // DECB_XPiI - 536922047U, // DECD_XPiI - 536889279U, // DECD_ZPiI - 536922631U, // DECH_XPiI - 6842887U, // DECH_ZPiI - 2315308983U, // DECP_XP_B - 2348863415U, // DECP_XP_D - 2717962167U, // DECP_XP_H - 2415972279U, // DECP_XP_S - 2147504055U, // DECP_ZP_D - 604532663U, // DECP_ZP_H - 2147520439U, // DECP_ZP_S - 536925351U, // DECW_XPiI - 536908967U, // DECW_ZPiI - 116059U, // DMB - 5966U, // DRPS - 116282U, // DSB - 637554371U, // DUPM_ZI - 671101025U, // DUP_ZI_B - 704663649U, // DUP_ZI_D - 7368801U, // DUP_ZI_H - 738234465U, // DUP_ZI_S - 2248159329U, // DUP_ZR_B - 2248167521U, // DUP_ZR_D - 611872865U, // DUP_ZR_H - 2248183905U, // DUP_ZR_S - 167784545U, // DUP_ZZI_B - 201347169U, // DUP_ZZI_D - 776499297U, // DUP_ZZI_H - 127073U, // DUP_ZZI_Q - 268472417U, // DUP_ZZI_S - 2249240673U, // DUPv16i8gpr - 2215686241U, // DUPv16i8lane - 2249764961U, // DUPv2i32gpr - 2216210529U, // DUPv2i32lane - 2250289249U, // DUPv2i64gpr - 69251169U, // DUPv2i64lane - 2250813537U, // DUPv4i16gpr - 69775457U, // DUPv4i16lane - 2251337825U, // DUPv4i32gpr - 2217783393U, // DUPv4i32lane - 2251862113U, // DUPv8i16gpr - 70824033U, // DUPv8i16lane - 2252386401U, // DUPv8i8gpr - 2218831969U, // DUPv8i8lane - 0U, // EONWrr - 100716298U, // EONWrs - 0U, // EONXrr - 100716298U, // EONXrs - 68198926U, // EOR3 - 302002853U, // EORS_PPzPP - 302044187U, // EORV_VPZ_B - 302044187U, // EORV_VPZ_D - 302044187U, // EORV_VPZ_H - 302044187U, // EORV_VPZ_S - 100716853U, // EORWri - 0U, // EORWrr - 100716853U, // EORWrs - 100716853U, // EORXri - 0U, // EORXrr - 100716853U, // EORXrs - 302002485U, // EOR_PPzPP - 201347381U, // EOR_ZI - 302002485U, // EOR_ZPmZ_B - 302010677U, // EOR_ZPmZ_D - 2186309941U, // EOR_ZPmZ_H - 302027061U, // EOR_ZPmZ_S - 201347381U, // EOR_ZZZ - 68202805U, // EORv16i8 - 2218832181U, // EORv8i8 - 5971U, // ERET - 5891U, // ERETAA - 5898U, // ERETAB - 100716930U, // EXTRWrri - 100716930U, // EXTRXrri - 167785316U, // EXT_ZZI - 68203364U, // EXTv16i8 - 2218832740U, // EXTv8i8 - 0U, // F128CSEL - 100714404U, // FABD16 - 100714404U, // FABD32 - 100714404U, // FABD64 - 302008228U, // FABD_ZPmZ_D - 2186307492U, // FABD_ZPmZ_H - 302024612U, // FABD_ZPmZ_S - 2216208292U, // FABDv2f32 - 2216732580U, // FABDv2f64 - 69773220U, // FABDv4f16 - 70297508U, // FABDv4f32 - 2218305444U, // FABDv8f16 - 2248200686U, // FABSDr - 2248200686U, // FABSHr - 2248200686U, // FABSSr - 20974U, // FABS_ZPmZ_D - 2181591534U, // FABS_ZPmZ_H - 37358U, // FABS_ZPmZ_S - 68727278U, // FABSv2f32 - 2216735214U, // FABSv2f64 - 69775854U, // FABSv4f16 - 2217783790U, // FABSv4f32 - 70824430U, // FABSv8f16 - 100714601U, // FACGE16 - 100714601U, // FACGE32 - 100714601U, // FACGE64 - 302008425U, // FACGE_PPzZZ_D - 2622515305U, // FACGE_PPzZZ_H - 302024809U, // FACGE_PPzZZ_S - 2216208489U, // FACGEv2f32 - 2216732777U, // FACGEv2f64 - 69773417U, // FACGEv4f16 - 70297705U, // FACGEv4f32 - 2218305641U, // FACGEv8f16 - 100717291U, // FACGT16 - 100717291U, // FACGT32 - 100717291U, // FACGT64 - 302011115U, // FACGT_PPzZZ_D - 2622517995U, // FACGT_PPzZZ_H - 302027499U, // FACGT_PPzZZ_S - 2216211179U, // FACGTv2f32 - 2216735467U, // FACGTv2f64 - 69776107U, // FACGTv4f16 - 70300395U, // FACGTv4f32 - 2218308331U, // FACGTv8f16 - 302039688U, // FADDA_VPZ_D - 302039688U, // FADDA_VPZ_H - 302039688U, // FADDA_VPZ_S - 100714475U, // FADDDrr - 100714475U, // FADDHrr - 2216210389U, // FADDPv2f32 - 2216734677U, // FADDPv2f64 - 2214645717U, // FADDPv2i16p - 67162069U, // FADDPv2i32p - 2214645717U, // FADDPv2i64p - 69775317U, // FADDPv4f16 - 70299605U, // FADDPv4f32 - 2218307541U, // FADDPv8f16 - 100714475U, // FADDSrr - 302044057U, // FADDV_VPZ_D - 302044057U, // FADDV_VPZ_H - 302044057U, // FADDV_VPZ_S - 302008299U, // FADD_ZPmI_D - 2186307563U, // FADD_ZPmI_H - 302024683U, // FADD_ZPmI_S - 302008299U, // FADD_ZPmZ_D - 2186307563U, // FADD_ZPmZ_H - 302024683U, // FADD_ZPmZ_S - 201345003U, // FADD_ZZZ_D - 2387109867U, // FADD_ZZZ_H - 268470251U, // FADD_ZZZ_S - 2216208363U, // FADDv2f32 - 2216732651U, // FADDv2f64 - 69773291U, // FADDv4f16 - 70297579U, // FADDv4f32 - 2218305515U, // FADDv8f16 - 302008285U, // FCADD_ZPmZ_D - 2186307549U, // FCADD_ZPmZ_H - 302024669U, // FCADD_ZPmZ_S - 2216208349U, // FCADDv2f32 - 2216732637U, // FCADDv2f64 - 69773277U, // FCADDv4f16 - 70297565U, // FCADDv4f32 - 2218305501U, // FCADDv8f16 - 100716545U, // FCCMPDrr - 100714692U, // FCCMPEDrr - 100714692U, // FCCMPEHrr - 100714692U, // FCCMPESrr - 100716545U, // FCCMPHrr - 100716545U, // FCCMPSrr - 100716698U, // FCMEQ16 - 100716698U, // FCMEQ32 - 100716698U, // FCMEQ64 - 302010522U, // FCMEQ_PPzZ0_D - 2622517402U, // FCMEQ_PPzZ0_H - 302026906U, // FCMEQ_PPzZ0_S - 302010522U, // FCMEQ_PPzZZ_D - 2622517402U, // FCMEQ_PPzZZ_H - 302026906U, // FCMEQ_PPzZZ_S - 100716698U, // FCMEQv1i16rz - 100716698U, // FCMEQv1i32rz - 100716698U, // FCMEQv1i64rz - 2216210586U, // FCMEQv2f32 - 2216734874U, // FCMEQv2f64 - 2216210586U, // FCMEQv2i32rz - 69251226U, // FCMEQv2i64rz - 69775514U, // FCMEQv4f16 - 70299802U, // FCMEQv4f32 - 2217259162U, // FCMEQv4i16rz - 70299802U, // FCMEQv4i32rz - 2218307738U, // FCMEQv8f16 - 2218307738U, // FCMEQv8i16rz - 100714608U, // FCMGE16 - 100714608U, // FCMGE32 - 100714608U, // FCMGE64 - 302008432U, // FCMGE_PPzZ0_D - 2622515312U, // FCMGE_PPzZ0_H - 302024816U, // FCMGE_PPzZ0_S - 302008432U, // FCMGE_PPzZZ_D - 2622515312U, // FCMGE_PPzZZ_H - 302024816U, // FCMGE_PPzZZ_S - 100714608U, // FCMGEv1i16rz - 100714608U, // FCMGEv1i32rz - 100714608U, // FCMGEv1i64rz - 2216208496U, // FCMGEv2f32 - 2216732784U, // FCMGEv2f64 - 2216208496U, // FCMGEv2i32rz - 69249136U, // FCMGEv2i64rz - 69773424U, // FCMGEv4f16 - 70297712U, // FCMGEv4f32 - 2217257072U, // FCMGEv4i16rz - 70297712U, // FCMGEv4i32rz - 2218305648U, // FCMGEv8f16 - 2218305648U, // FCMGEv8i16rz - 100717298U, // FCMGT16 - 100717298U, // FCMGT32 - 100717298U, // FCMGT64 - 302011122U, // FCMGT_PPzZ0_D - 2622518002U, // FCMGT_PPzZ0_H - 302027506U, // FCMGT_PPzZ0_S - 302011122U, // FCMGT_PPzZZ_D - 2622518002U, // FCMGT_PPzZZ_H - 302027506U, // FCMGT_PPzZZ_S - 100717298U, // FCMGTv1i16rz - 100717298U, // FCMGTv1i32rz - 100717298U, // FCMGTv1i64rz - 2216211186U, // FCMGTv2f32 - 2216735474U, // FCMGTv2f64 - 2216211186U, // FCMGTv2i32rz - 69251826U, // FCMGTv2i64rz - 69776114U, // FCMGTv4f16 - 70300402U, // FCMGTv4f32 - 2217259762U, // FCMGTv4i16rz - 70300402U, // FCMGTv4i32rz - 2218308338U, // FCMGTv8f16 - 2218308338U, // FCMGTv8i16rz - 302006961U, // FCMLA_ZPmZZ_D - 2186306225U, // FCMLA_ZPmZZ_H - 302023345U, // FCMLA_ZPmZZ_S - 243294897U, // FCMLA_ZZZI_H - 2952823473U, // FCMLA_ZZZI_S - 2283332273U, // FCMLAv2f32 - 2283856561U, // FCMLAv2f64 - 136897201U, // FCMLAv4f16 - 136897201U, // FCMLAv4f16_indexed - 137421489U, // FCMLAv4f32 - 137421489U, // FCMLAv4f32_indexed - 2285429425U, // FCMLAv8f16 - 2285429425U, // FCMLAv8f16_indexed - 302008463U, // FCMLE_PPzZ0_D - 2622515343U, // FCMLE_PPzZ0_H - 302024847U, // FCMLE_PPzZ0_S - 100714639U, // FCMLEv1i16rz - 100714639U, // FCMLEv1i32rz - 100714639U, // FCMLEv1i64rz - 2216208527U, // FCMLEv2i32rz - 69249167U, // FCMLEv2i64rz - 2217257103U, // FCMLEv4i16rz - 70297743U, // FCMLEv4i32rz - 2218305679U, // FCMLEv8i16rz - 302011156U, // FCMLT_PPzZ0_D - 2622518036U, // FCMLT_PPzZ0_H - 302027540U, // FCMLT_PPzZ0_S - 100717332U, // FCMLTv1i16rz - 100717332U, // FCMLTv1i32rz - 100717332U, // FCMLTv1i64rz - 2216211220U, // FCMLTv2i32rz - 69251860U, // FCMLTv2i64rz - 2217259796U, // FCMLTv4i16rz - 70300436U, // FCMLTv4i32rz - 2218308372U, // FCMLTv8i16rz - 302008477U, // FCMNE_PPzZ0_D - 2622515357U, // FCMNE_PPzZ0_H - 302024861U, // FCMNE_PPzZ0_S - 302008477U, // FCMNE_PPzZZ_D - 2622515357U, // FCMNE_PPzZZ_H - 302024861U, // FCMNE_PPzZZ_S - 8966152U, // FCMPDri - 2248200200U, // FCMPDrr - 8964300U, // FCMPEDri - 2248198348U, // FCMPEDrr - 8964300U, // FCMPEHri - 2248198348U, // FCMPEHrr - 8964300U, // FCMPESri - 2248198348U, // FCMPESrr - 8966152U, // FCMPHri - 2248200200U, // FCMPHrr - 8966152U, // FCMPSri - 2248200200U, // FCMPSrr - 302010279U, // FCMUO_PPzZZ_D - 2622517159U, // FCMUO_PPzZZ_H - 302026663U, // FCMUO_PPzZZ_S - 21938U, // FCPY_ZPmI_D - 34108850U, // FCPY_ZPmI_H - 38322U, // FCPY_ZPmI_S - 100715904U, // FCSELDrrr - 100715904U, // FCSELHrrr - 100715904U, // FCSELSrrr - 2248200678U, // FCVTASUWDr - 2248200678U, // FCVTASUWHr - 2248200678U, // FCVTASUWSr - 2248200678U, // FCVTASUXDr - 2248200678U, // FCVTASUXHr - 2248200678U, // FCVTASUXSr - 2248200678U, // FCVTASv1f16 - 2248200678U, // FCVTASv1i32 - 2248200678U, // FCVTASv1i64 - 68727270U, // FCVTASv2f32 - 2216735206U, // FCVTASv2f64 - 69775846U, // FCVTASv4f16 - 2217783782U, // FCVTASv4f32 - 70824422U, // FCVTASv8f16 - 2248201065U, // FCVTAUUWDr - 2248201065U, // FCVTAUUWHr - 2248201065U, // FCVTAUUWSr - 2248201065U, // FCVTAUUXDr - 2248201065U, // FCVTAUUXHr - 2248201065U, // FCVTAUUXSr - 2248201065U, // FCVTAUv1f16 - 2248201065U, // FCVTAUv1i32 - 2248201065U, // FCVTAUv1i64 - 68727657U, // FCVTAUv2f32 - 2216735593U, // FCVTAUv2f64 - 69776233U, // FCVTAUv4f16 - 2217784169U, // FCVTAUv4f32 - 70824809U, // FCVTAUv8f16 - 2248201052U, // FCVTDHr - 2248201052U, // FCVTDSr - 2248201052U, // FCVTHDr - 2248201052U, // FCVTHSr - 69250649U, // FCVTLv2i32 - 70299225U, // FCVTLv4i16 - 2216730945U, // FCVTLv4i32 - 70295873U, // FCVTLv8i16 - 2248200806U, // FCVTMSUWDr - 2248200806U, // FCVTMSUWHr - 2248200806U, // FCVTMSUWSr - 2248200806U, // FCVTMSUXDr - 2248200806U, // FCVTMSUXHr - 2248200806U, // FCVTMSUXSr - 2248200806U, // FCVTMSv1f16 - 2248200806U, // FCVTMSv1i32 - 2248200806U, // FCVTMSv1i64 - 68727398U, // FCVTMSv2f32 - 2216735334U, // FCVTMSv2f64 - 69775974U, // FCVTMSv4f16 - 2217783910U, // FCVTMSv4f32 - 70824550U, // FCVTMSv8f16 - 2248201081U, // FCVTMUUWDr - 2248201081U, // FCVTMUUWHr - 2248201081U, // FCVTMUUWSr - 2248201081U, // FCVTMUUXDr - 2248201081U, // FCVTMUUXHr - 2248201081U, // FCVTMUUXSr - 2248201081U, // FCVTMUv1f16 - 2248201081U, // FCVTMUv1i32 - 2248201081U, // FCVTMUv1i64 - 68727673U, // FCVTMUv2f32 - 2216735609U, // FCVTMUv2f64 - 69776249U, // FCVTMUv4f16 - 2217784185U, // FCVTMUv4f32 - 70824825U, // FCVTMUv8f16 - 2248200832U, // FCVTNSUWDr - 2248200832U, // FCVTNSUWHr - 2248200832U, // FCVTNSUWSr - 2248200832U, // FCVTNSUXDr - 2248200832U, // FCVTNSUXHr - 2248200832U, // FCVTNSUXSr - 2248200832U, // FCVTNSv1f16 - 2248200832U, // FCVTNSv1i32 - 2248200832U, // FCVTNSv1i64 - 68727424U, // FCVTNSv2f32 - 2216735360U, // FCVTNSv2f64 - 69776000U, // FCVTNSv4f16 - 2217783936U, // FCVTNSv4f32 - 70824576U, // FCVTNSv8f16 - 2248201089U, // FCVTNUUWDr - 2248201089U, // FCVTNUUWHr - 2248201089U, // FCVTNUUWSr - 2248201089U, // FCVTNUUXDr - 2248201089U, // FCVTNUUXHr - 2248201089U, // FCVTNUUXSr - 2248201089U, // FCVTNUv1f16 - 2248201089U, // FCVTNUv1i32 - 2248201089U, // FCVTNUv1i64 - 68727681U, // FCVTNUv2f32 - 2216735617U, // FCVTNUv2f64 - 69776257U, // FCVTNUv4f16 - 2217784193U, // FCVTNUv4f32 - 70824833U, // FCVTNUv8f16 - 2216210238U, // FCVTNv2i32 - 2217258814U, // FCVTNv4i16 - 2284904839U, // FCVTNv4i32 - 2285429127U, // FCVTNv8i16 - 2248200848U, // FCVTPSUWDr - 2248200848U, // FCVTPSUWHr - 2248200848U, // FCVTPSUWSr - 2248200848U, // FCVTPSUXDr - 2248200848U, // FCVTPSUXHr - 2248200848U, // FCVTPSUXSr - 2248200848U, // FCVTPSv1f16 - 2248200848U, // FCVTPSv1i32 - 2248200848U, // FCVTPSv1i64 - 68727440U, // FCVTPSv2f32 - 2216735376U, // FCVTPSv2f64 - 69776016U, // FCVTPSv4f16 - 2217783952U, // FCVTPSv4f32 - 70824592U, // FCVTPSv8f16 - 2248201097U, // FCVTPUUWDr - 2248201097U, // FCVTPUUWHr - 2248201097U, // FCVTPUUWSr - 2248201097U, // FCVTPUUXDr - 2248201097U, // FCVTPUUXHr - 2248201097U, // FCVTPUUXSr - 2248201097U, // FCVTPUv1f16 - 2248201097U, // FCVTPUv1i32 - 2248201097U, // FCVTPUv1i64 - 68727689U, // FCVTPUv2f32 - 2216735625U, // FCVTPUv2f64 - 69776265U, // FCVTPUv4f16 - 2217784201U, // FCVTPUv4f32 - 70824841U, // FCVTPUv8f16 - 2248201052U, // FCVTSDr - 2248201052U, // FCVTSHr - 2248200052U, // FCVTXNv1i64 - 2216210292U, // FCVTXNv2f32 - 2284904893U, // FCVTXNv4f32 - 100717253U, // FCVTZSSWDri - 100717253U, // FCVTZSSWHri - 100717253U, // FCVTZSSWSri - 100717253U, // FCVTZSSXDri - 100717253U, // FCVTZSSXHri - 100717253U, // FCVTZSSXSri - 2248200901U, // FCVTZSUWDr - 2248200901U, // FCVTZSUWHr - 2248200901U, // FCVTZSUWSr - 2248200901U, // FCVTZSUXDr - 2248200901U, // FCVTZSUXHr - 2248200901U, // FCVTZSUXSr - 21189U, // FCVTZS_ZPmZ_DtoD - 37573U, // FCVTZS_ZPmZ_DtoS - 21189U, // FCVTZS_ZPmZ_HtoD - 2181591749U, // FCVTZS_ZPmZ_HtoH - 37573U, // FCVTZS_ZPmZ_HtoS - 21189U, // FCVTZS_ZPmZ_StoD - 37573U, // FCVTZS_ZPmZ_StoS - 100717253U, // FCVTZSd - 100717253U, // FCVTZSh - 100717253U, // FCVTZSs - 2248200901U, // FCVTZSv1f16 - 2248200901U, // FCVTZSv1i32 - 2248200901U, // FCVTZSv1i64 - 68727493U, // FCVTZSv2f32 - 2216735429U, // FCVTZSv2f64 - 2216211141U, // FCVTZSv2i32_shift - 2216735429U, // FCVTZSv2i64_shift - 69776069U, // FCVTZSv4f16 - 2217784005U, // FCVTZSv4f32 - 69776069U, // FCVTZSv4i16_shift - 70300357U, // FCVTZSv4i32_shift - 70824645U, // FCVTZSv8f16 - 2218308293U, // FCVTZSv8i16_shift - 100717457U, // FCVTZUSWDri - 100717457U, // FCVTZUSWHri - 100717457U, // FCVTZUSWSri - 100717457U, // FCVTZUSXDri - 100717457U, // FCVTZUSXHri - 100717457U, // FCVTZUSXSri - 2248201105U, // FCVTZUUWDr - 2248201105U, // FCVTZUUWHr - 2248201105U, // FCVTZUUWSr - 2248201105U, // FCVTZUUXDr - 2248201105U, // FCVTZUUXHr - 2248201105U, // FCVTZUUXSr - 21393U, // FCVTZU_ZPmZ_DtoD - 37777U, // FCVTZU_ZPmZ_DtoS - 21393U, // FCVTZU_ZPmZ_HtoD - 2181591953U, // FCVTZU_ZPmZ_HtoH - 37777U, // FCVTZU_ZPmZ_HtoS - 21393U, // FCVTZU_ZPmZ_StoD - 37777U, // FCVTZU_ZPmZ_StoS - 100717457U, // FCVTZUd - 100717457U, // FCVTZUh - 100717457U, // FCVTZUs - 2248201105U, // FCVTZUv1f16 - 2248201105U, // FCVTZUv1i32 - 2248201105U, // FCVTZUv1i64 - 68727697U, // FCVTZUv2f32 - 2216735633U, // FCVTZUv2f64 - 2216211345U, // FCVTZUv2i32_shift - 2216735633U, // FCVTZUv2i64_shift - 69776273U, // FCVTZUv4f16 - 2217784209U, // FCVTZUv4f32 - 69776273U, // FCVTZUv4i16_shift - 70300561U, // FCVTZUv4i32_shift - 70824849U, // FCVTZUv8f16 - 2218308497U, // FCVTZUv8i16_shift - 2181591900U, // FCVT_ZPmZ_DtoH - 37724U, // FCVT_ZPmZ_DtoS - 21340U, // FCVT_ZPmZ_HtoD - 37724U, // FCVT_ZPmZ_HtoS - 21340U, // FCVT_ZPmZ_StoD - 2181591900U, // FCVT_ZPmZ_StoH - 100717497U, // FDIVDrr - 100717497U, // FDIVHrr - 302010787U, // FDIVR_ZPmZ_D - 2186310051U, // FDIVR_ZPmZ_H - 302027171U, // FDIVR_ZPmZ_S - 100717497U, // FDIVSrr - 302011321U, // FDIV_ZPmZ_D - 2186310585U, // FDIV_ZPmZ_H - 302027705U, // FDIV_ZPmZ_S - 2216211385U, // FDIVv2f32 - 2216735673U, // FDIVv2f64 - 69776313U, // FDIVv4f16 - 70300601U, // FDIVv4f32 - 2218308537U, // FDIVv8f16 - 838881376U, // FDUP_ZI_D - 9465952U, // FDUP_ZI_H - 838897760U, // FDUP_ZI_S - 2348827371U, // FEXPA_ZZ_D - 608723691U, // FEXPA_ZZ_H - 2415952619U, // FEXPA_ZZ_S - 2248200909U, // FJCVTZS - 100714511U, // FMADDDrrr - 100714511U, // FMADDHrrr - 100714511U, // FMADDSrrr - 302008208U, // FMAD_ZPmZZ_D - 2186307472U, // FMAD_ZPmZZ_H - 302024592U, // FMAD_ZPmZZ_S - 100717911U, // FMAXDrr - 100717911U, // FMAXHrr - 100716219U, // FMAXNMDrr - 100716219U, // FMAXNMHrr - 2216210455U, // FMAXNMPv2f32 - 2216734743U, // FMAXNMPv2f64 - 2214645783U, // FMAXNMPv2i16p - 67162135U, // FMAXNMPv2i32p - 2214645783U, // FMAXNMPv2i64p - 69775383U, // FMAXNMPv4f16 - 70299671U, // FMAXNMPv4f32 - 2218307607U, // FMAXNMPv8f16 - 100716219U, // FMAXNMSrr - 302044132U, // FMAXNMV_VPZ_D - 302044132U, // FMAXNMV_VPZ_H - 302044132U, // FMAXNMV_VPZ_S - 67163108U, // FMAXNMVv4i16v - 2214646756U, // FMAXNMVv4i32v - 67163108U, // FMAXNMVv8i16v - 302010043U, // FMAXNM_ZPmI_D - 2186309307U, // FMAXNM_ZPmI_H - 302026427U, // FMAXNM_ZPmI_S - 302010043U, // FMAXNM_ZPmZ_D - 2186309307U, // FMAXNM_ZPmZ_H - 302026427U, // FMAXNM_ZPmZ_S - 2216210107U, // FMAXNMv2f32 - 2216734395U, // FMAXNMv2f64 - 69775035U, // FMAXNMv4f16 - 70299323U, // FMAXNMv4f32 - 2218307259U, // FMAXNMv8f16 - 2216210546U, // FMAXPv2f32 - 2216734834U, // FMAXPv2f64 - 2214645874U, // FMAXPv2i16p - 67162226U, // FMAXPv2i32p - 2214645874U, // FMAXPv2i64p - 69775474U, // FMAXPv4f16 - 70299762U, // FMAXPv4f32 - 2218307698U, // FMAXPv8f16 - 100717911U, // FMAXSrr - 302044193U, // FMAXV_VPZ_D - 302044193U, // FMAXV_VPZ_H - 302044193U, // FMAXV_VPZ_S - 67163169U, // FMAXVv4i16v - 2214646817U, // FMAXVv4i32v - 67163169U, // FMAXVv8i16v - 302011735U, // FMAX_ZPmI_D - 2186310999U, // FMAX_ZPmI_H - 302028119U, // FMAX_ZPmI_S - 302011735U, // FMAX_ZPmZ_D - 2186310999U, // FMAX_ZPmZ_H - 302028119U, // FMAX_ZPmZ_S - 2216211799U, // FMAXv2f32 - 2216736087U, // FMAXv2f64 - 69776727U, // FMAXv4f16 - 70301015U, // FMAXv4f32 - 2218308951U, // FMAXv8f16 - 100716264U, // FMINDrr - 100716264U, // FMINHrr - 100716211U, // FMINNMDrr - 100716211U, // FMINNMHrr - 2216210446U, // FMINNMPv2f32 - 2216734734U, // FMINNMPv2f64 - 2214645774U, // FMINNMPv2i16p - 67162126U, // FMINNMPv2i32p - 2214645774U, // FMINNMPv2i64p - 69775374U, // FMINNMPv4f16 - 70299662U, // FMINNMPv4f32 - 2218307598U, // FMINNMPv8f16 - 100716211U, // FMINNMSrr - 302044123U, // FMINNMV_VPZ_D - 302044123U, // FMINNMV_VPZ_H - 302044123U, // FMINNMV_VPZ_S - 67163099U, // FMINNMVv4i16v - 2214646747U, // FMINNMVv4i32v - 67163099U, // FMINNMVv8i16v - 302010035U, // FMINNM_ZPmI_D - 2186309299U, // FMINNM_ZPmI_H - 302026419U, // FMINNM_ZPmI_S - 302010035U, // FMINNM_ZPmZ_D - 2186309299U, // FMINNM_ZPmZ_H - 302026419U, // FMINNM_ZPmZ_S - 2216210099U, // FMINNMv2f32 - 2216734387U, // FMINNMv2f64 - 69775027U, // FMINNMv4f16 - 70299315U, // FMINNMv4f32 - 2218307251U, // FMINNMv8f16 - 2216210470U, // FMINPv2f32 - 2216734758U, // FMINPv2f64 - 2214645798U, // FMINPv2i16p - 67162150U, // FMINPv2i32p - 2214645798U, // FMINPv2i64p - 69775398U, // FMINPv4f16 - 70299686U, // FMINPv4f32 - 2218307622U, // FMINPv8f16 - 100716264U, // FMINSrr - 302044141U, // FMINV_VPZ_D - 302044141U, // FMINV_VPZ_H - 302044141U, // FMINV_VPZ_S - 67163117U, // FMINVv4i16v - 2214646765U, // FMINVv4i32v - 67163117U, // FMINVv8i16v - 302010088U, // FMIN_ZPmI_D - 2186309352U, // FMIN_ZPmI_H - 302026472U, // FMIN_ZPmI_S - 302010088U, // FMIN_ZPmZ_D - 2186309352U, // FMIN_ZPmZ_H - 302026472U, // FMIN_ZPmZ_S - 2216210152U, // FMINv2f32 - 2216734440U, // FMINv2f64 - 69775080U, // FMINv4f16 - 70299368U, // FMINv4f32 - 2218307304U, // FMINv8f16 - 302006968U, // FMLA_ZPmZZ_D - 2186306232U, // FMLA_ZPmZZ_H - 302023352U, // FMLA_ZPmZZ_S - 3019915960U, // FMLA_ZZZI_D - 612393656U, // FMLA_ZZZI_H - 2952823480U, // FMLA_ZZZI_S - 369189560U, // FMLAv1i16_indexed - 369189560U, // FMLAv1i32_indexed - 369189560U, // FMLAv1i64_indexed - 2283332280U, // FMLAv2f32 - 2283856568U, // FMLAv2f64 - 2283332280U, // FMLAv2i32_indexed - 2283856568U, // FMLAv2i64_indexed - 136897208U, // FMLAv4f16 - 137421496U, // FMLAv4f32 - 136897208U, // FMLAv4i16_indexed - 137421496U, // FMLAv4i32_indexed - 2285429432U, // FMLAv8f16 - 2285429432U, // FMLAv8i16_indexed - 302010962U, // FMLS_ZPmZZ_D - 2186310226U, // FMLS_ZPmZZ_H - 302027346U, // FMLS_ZPmZZ_S - 3019919954U, // FMLS_ZZZI_D - 612397650U, // FMLS_ZZZI_H - 2952827474U, // FMLS_ZZZI_S - 369193554U, // FMLSv1i16_indexed - 369193554U, // FMLSv1i32_indexed - 369193554U, // FMLSv1i64_indexed - 2283336274U, // FMLSv2f32 - 2283860562U, // FMLSv2f64 - 2283336274U, // FMLSv2i32_indexed - 2283860562U, // FMLSv2i64_indexed - 136901202U, // FMLSv4f16 - 137425490U, // FMLSv4f32 - 136901202U, // FMLSv4i16_indexed - 137425490U, // FMLSv4i32_indexed - 2285433426U, // FMLSv8f16 - 2285433426U, // FMLSv8i16_indexed - 0U, // FMOVD0 - 67163145U, // FMOVDXHighr - 2248201225U, // FMOVDXr - 838915081U, // FMOVDi - 2248201225U, // FMOVDr - 0U, // FMOVH0 - 2248201225U, // FMOVHWr - 2248201225U, // FMOVHXr - 838915081U, // FMOVHi - 2248201225U, // FMOVHr - 0U, // FMOVS0 - 2248201225U, // FMOVSWr - 838915081U, // FMOVSi - 2248201225U, // FMOVSr - 2248201225U, // FMOVWHr - 2248201225U, // FMOVWSr - 2258154505U, // FMOVXDHighr - 2248201225U, // FMOVXDr - 2248201225U, // FMOVXHr - 840479753U, // FMOVv2f32_ns - 841004041U, // FMOVv2f64_ns - 841528329U, // FMOVv4f16_ns - 842052617U, // FMOVv4f32_ns - 842576905U, // FMOVv8f16_ns - 302007876U, // FMSB_ZPmZZ_D - 2186307140U, // FMSB_ZPmZZ_H - 302024260U, // FMSB_ZPmZZ_S - 100714165U, // FMSUBDrrr - 100714165U, // FMSUBHrrr - 100714165U, // FMSUBSrrr - 100716128U, // FMULDrr - 100716128U, // FMULHrr - 100716128U, // FMULSrr - 100717970U, // FMULX16 - 100717970U, // FMULX32 - 100717970U, // FMULX64 - 302011794U, // FMULX_ZPmZ_D - 2186311058U, // FMULX_ZPmZ_H - 302028178U, // FMULX_ZPmZ_S - 100717970U, // FMULXv1i16_indexed - 100717970U, // FMULXv1i32_indexed - 100717970U, // FMULXv1i64_indexed - 2216211858U, // FMULXv2f32 - 2216736146U, // FMULXv2f64 - 2216211858U, // FMULXv2i32_indexed - 2216736146U, // FMULXv2i64_indexed - 69776786U, // FMULXv4f16 - 70301074U, // FMULXv4f32 - 69776786U, // FMULXv4i16_indexed - 70301074U, // FMULXv4i32_indexed - 2218309010U, // FMULXv8f16 - 2218309010U, // FMULXv8i16_indexed - 302009952U, // FMUL_ZPmI_D - 2186309216U, // FMUL_ZPmI_H - 302026336U, // FMUL_ZPmI_S - 302009952U, // FMUL_ZPmZ_D - 2186309216U, // FMUL_ZPmZ_H - 302026336U, // FMUL_ZPmZ_S - 201346656U, // FMUL_ZZZI_D - 2387111520U, // FMUL_ZZZI_H - 268471904U, // FMUL_ZZZI_S - 201346656U, // FMUL_ZZZ_D - 2387111520U, // FMUL_ZZZ_H - 268471904U, // FMUL_ZZZ_S - 100716128U, // FMULv1i16_indexed - 100716128U, // FMULv1i32_indexed - 100716128U, // FMULv1i64_indexed - 2216210016U, // FMULv2f32 - 2216734304U, // FMULv2f64 - 2216210016U, // FMULv2i32_indexed - 2216734304U, // FMULv2i64_indexed - 69774944U, // FMULv4f16 - 70299232U, // FMULv4f32 - 69774944U, // FMULv4i16_indexed - 70299232U, // FMULv4i32_indexed - 2218307168U, // FMULv8f16 - 2218307168U, // FMULv8i16_indexed - 2248198419U, // FNEGDr - 2248198419U, // FNEGHr - 2248198419U, // FNEGSr - 18707U, // FNEG_ZPmZ_D - 2181589267U, // FNEG_ZPmZ_H - 35091U, // FNEG_ZPmZ_S - 68725011U, // FNEGv2f32 - 2216732947U, // FNEGv2f64 - 69773587U, // FNEGv4f16 - 2217781523U, // FNEGv4f32 - 70822163U, // FNEGv8f16 - 100714518U, // FNMADDDrrr - 100714518U, // FNMADDHrrr - 100714518U, // FNMADDSrrr - 302008214U, // FNMAD_ZPmZZ_D - 2186307478U, // FNMAD_ZPmZZ_H - 302024598U, // FNMAD_ZPmZZ_S - 302006974U, // FNMLA_ZPmZZ_D - 2186306238U, // FNMLA_ZPmZZ_H - 302023358U, // FNMLA_ZPmZZ_S - 302010968U, // FNMLS_ZPmZZ_D - 2186310232U, // FNMLS_ZPmZZ_H - 302027352U, // FNMLS_ZPmZZ_S - 302007882U, // FNMSB_ZPmZZ_D - 2186307146U, // FNMSB_ZPmZZ_H - 302024266U, // FNMSB_ZPmZZ_S - 100714172U, // FNMSUBDrrr - 100714172U, // FNMSUBHrrr - 100714172U, // FNMSUBSrrr - 100716134U, // FNMULDrr - 100716134U, // FNMULHrr - 100716134U, // FNMULSrr - 2348828852U, // FRECPE_ZZ_D - 608725172U, // FRECPE_ZZ_H - 2415954100U, // FRECPE_ZZ_S - 2248198324U, // FRECPEv1f16 - 2248198324U, // FRECPEv1i32 - 2248198324U, // FRECPEv1i64 - 68724916U, // FRECPEv2f32 - 2216732852U, // FRECPEv2f64 - 69773492U, // FRECPEv4f16 - 2217781428U, // FRECPEv4f32 - 70822068U, // FRECPEv8f16 - 100717192U, // FRECPS16 - 100717192U, // FRECPS32 - 100717192U, // FRECPS64 - 201347720U, // FRECPS_ZZZ_D - 2387112584U, // FRECPS_ZZZ_H - 268472968U, // FRECPS_ZZZ_S - 2216211080U, // FRECPSv2f32 - 2216735368U, // FRECPSv2f64 - 69776008U, // FRECPSv4f16 - 70300296U, // FRECPSv4f32 - 2218308232U, // FRECPSv8f16 - 21913U, // FRECPX_ZPmZ_D - 2181592473U, // FRECPX_ZPmZ_H - 38297U, // FRECPX_ZPmZ_S - 2248201625U, // FRECPXv1f16 - 2248201625U, // FRECPXv1i32 - 2248201625U, // FRECPXv1i64 - 2248196906U, // FRINTADr - 2248196906U, // FRINTAHr - 2248196906U, // FRINTASr - 17194U, // FRINTA_ZPmZ_D - 2181587754U, // FRINTA_ZPmZ_H - 33578U, // FRINTA_ZPmZ_S - 68723498U, // FRINTAv2f32 - 2216731434U, // FRINTAv2f64 - 69772074U, // FRINTAv4f16 - 2217780010U, // FRINTAv4f32 - 70820650U, // FRINTAv8f16 - 2248199305U, // FRINTIDr - 2248199305U, // FRINTIHr - 2248199305U, // FRINTISr - 19593U, // FRINTI_ZPmZ_D - 2181590153U, // FRINTI_ZPmZ_H - 35977U, // FRINTI_ZPmZ_S - 68725897U, // FRINTIv2f32 - 2216733833U, // FRINTIv2f64 - 69774473U, // FRINTIv4f16 - 2217782409U, // FRINTIv4f32 - 70823049U, // FRINTIv8f16 - 2248199881U, // FRINTMDr - 2248199881U, // FRINTMHr - 2248199881U, // FRINTMSr - 20169U, // FRINTM_ZPmZ_D - 2181590729U, // FRINTM_ZPmZ_H - 36553U, // FRINTM_ZPmZ_S - 68726473U, // FRINTMv2f32 - 2216734409U, // FRINTMv2f64 - 69775049U, // FRINTMv4f16 - 2217782985U, // FRINTMv4f32 - 70823625U, // FRINTMv8f16 - 2248199990U, // FRINTNDr - 2248199990U, // FRINTNHr - 2248199990U, // FRINTNSr - 20278U, // FRINTN_ZPmZ_D - 2181590838U, // FRINTN_ZPmZ_H - 36662U, // FRINTN_ZPmZ_S - 68726582U, // FRINTNv2f32 - 2216734518U, // FRINTNv2f64 - 69775158U, // FRINTNv4f16 - 2217783094U, // FRINTNv4f32 - 70823734U, // FRINTNv8f16 - 2248200275U, // FRINTPDr - 2248200275U, // FRINTPHr - 2248200275U, // FRINTPSr - 20563U, // FRINTP_ZPmZ_D - 2181591123U, // FRINTP_ZPmZ_H - 36947U, // FRINTP_ZPmZ_S - 68726867U, // FRINTPv2f32 - 2216734803U, // FRINTPv2f64 - 69775443U, // FRINTPv4f16 - 2217783379U, // FRINTPv4f32 - 70824019U, // FRINTPv8f16 - 2248201633U, // FRINTXDr - 2248201633U, // FRINTXHr - 2248201633U, // FRINTXSr - 21921U, // FRINTX_ZPmZ_D - 2181592481U, // FRINTX_ZPmZ_H - 38305U, // FRINTX_ZPmZ_S - 68728225U, // FRINTXv2f32 - 2216736161U, // FRINTXv2f64 - 69776801U, // FRINTXv4f16 - 2217784737U, // FRINTXv4f32 - 70825377U, // FRINTXv8f16 - 2248201713U, // FRINTZDr - 2248201713U, // FRINTZHr - 2248201713U, // FRINTZSr - 22001U, // FRINTZ_ZPmZ_D - 2181592561U, // FRINTZ_ZPmZ_H - 38385U, // FRINTZ_ZPmZ_S - 68728305U, // FRINTZv2f32 - 2216736241U, // FRINTZv2f64 - 69776881U, // FRINTZv4f16 - 2217784817U, // FRINTZv4f32 - 70825457U, // FRINTZv8f16 - 2348828897U, // FRSQRTE_ZZ_D - 608725217U, // FRSQRTE_ZZ_H - 2415954145U, // FRSQRTE_ZZ_S - 2248198369U, // FRSQRTEv1f16 - 2248198369U, // FRSQRTEv1i32 - 2248198369U, // FRSQRTEv1i64 - 68724961U, // FRSQRTEv2f32 - 2216732897U, // FRSQRTEv2f64 - 69773537U, // FRSQRTEv4f16 - 2217781473U, // FRSQRTEv4f32 - 70822113U, // FRSQRTEv8f16 - 100717239U, // FRSQRTS16 - 100717239U, // FRSQRTS32 - 100717239U, // FRSQRTS64 - 201347767U, // FRSQRTS_ZZZ_D - 2387112631U, // FRSQRTS_ZZZ_H - 268473015U, // FRSQRTS_ZZZ_S - 2216211127U, // FRSQRTSv2f32 - 2216735415U, // FRSQRTSv2f64 - 69776055U, // FRSQRTSv4f16 - 70300343U, // FRSQRTSv4f32 - 2218308279U, // FRSQRTSv8f16 - 302008446U, // FSCALE_ZPmZ_D - 2186307710U, // FSCALE_ZPmZ_H - 302024830U, // FSCALE_ZPmZ_S - 2248201023U, // FSQRTDr - 2248201023U, // FSQRTHr - 2248201023U, // FSQRTSr - 21311U, // FSQRT_ZPmZ_D - 2181591871U, // FSQRT_ZPmZ_H - 37695U, // FSQRT_ZPmZ_S - 68727615U, // FSQRTv2f32 - 2216735551U, // FSQRTv2f64 - 69776191U, // FSQRTv4f16 - 2217784127U, // FSQRTv4f32 - 70824767U, // FSQRTv8f16 - 100714145U, // FSUBDrr - 100714145U, // FSUBHrr - 302010587U, // FSUBR_ZPmI_D - 2186309851U, // FSUBR_ZPmI_H - 302026971U, // FSUBR_ZPmI_S - 302010587U, // FSUBR_ZPmZ_D - 2186309851U, // FSUBR_ZPmZ_H - 302026971U, // FSUBR_ZPmZ_S - 100714145U, // FSUBSrr - 302007969U, // FSUB_ZPmI_D - 2186307233U, // FSUB_ZPmI_H - 302024353U, // FSUB_ZPmI_S - 302007969U, // FSUB_ZPmZ_D - 2186307233U, // FSUB_ZPmZ_H - 302024353U, // FSUB_ZPmZ_S - 201344673U, // FSUB_ZZZ_D - 2387109537U, // FSUB_ZZZ_H - 268469921U, // FSUB_ZZZ_S - 2216208033U, // FSUBv2f32 - 2216732321U, // FSUBv2f64 - 69772961U, // FSUBv4f16 - 70297249U, // FSUBv4f32 - 2218305185U, // FSUBv8f16 - 201344925U, // FTMAD_ZZI_D - 2387109789U, // FTMAD_ZZI_H - 268470173U, // FTMAD_ZZI_S - 201346675U, // FTSMUL_ZZZ_D - 2387111539U, // FTSMUL_ZZZ_H - 268471923U, // FTSMUL_ZZZ_S - 201346439U, // FTSSEL_ZZZ_D - 2387111303U, // FTSSEL_ZZZ_H - 268471687U, // FTSSEL_ZZZ_S - 883032940U, // GLD1B_D_IMM_REAL - 379716460U, // GLD1B_D_REAL - 379716460U, // GLD1B_D_SXTW_REAL - 379716460U, // GLD1B_D_UXTW_REAL - 815932268U, // GLD1B_S_IMM_REAL - 379724652U, // GLD1B_S_SXTW_REAL - 379724652U, // GLD1B_S_UXTW_REAL - 883033920U, // GLD1D_IMM_REAL - 379717440U, // GLD1D_REAL - 379717440U, // GLD1D_SCALED_REAL - 379717440U, // GLD1D_SXTW_REAL - 379717440U, // GLD1D_SXTW_SCALED_REAL - 379717440U, // GLD1D_UXTW_REAL - 379717440U, // GLD1D_UXTW_SCALED_REAL - 3030518062U, // GLD1H_D_IMM_REAL - 379717934U, // GLD1H_D_REAL - 379717934U, // GLD1H_D_SCALED_REAL - 379717934U, // GLD1H_D_SXTW_REAL - 379717934U, // GLD1H_D_SXTW_SCALED_REAL - 379717934U, // GLD1H_D_UXTW_REAL - 379717934U, // GLD1H_D_UXTW_SCALED_REAL - 2963417390U, // GLD1H_S_IMM_REAL - 379726126U, // GLD1H_S_SXTW_REAL - 379726126U, // GLD1H_S_SXTW_SCALED_REAL - 379726126U, // GLD1H_S_UXTW_REAL - 379726126U, // GLD1H_S_UXTW_SCALED_REAL - 883033627U, // GLD1SB_D_IMM_REAL - 379717147U, // GLD1SB_D_REAL - 379717147U, // GLD1SB_D_SXTW_REAL - 379717147U, // GLD1SB_D_UXTW_REAL - 815932955U, // GLD1SB_S_IMM_REAL - 379725339U, // GLD1SB_S_SXTW_REAL - 379725339U, // GLD1SB_S_UXTW_REAL - 3030518726U, // GLD1SH_D_IMM_REAL - 379718598U, // GLD1SH_D_REAL - 379718598U, // GLD1SH_D_SCALED_REAL - 379718598U, // GLD1SH_D_SXTW_REAL - 379718598U, // GLD1SH_D_SXTW_SCALED_REAL - 379718598U, // GLD1SH_D_UXTW_REAL - 379718598U, // GLD1SH_D_UXTW_SCALED_REAL - 2963418054U, // GLD1SH_S_IMM_REAL - 379726790U, // GLD1SH_S_SXTW_REAL - 379726790U, // GLD1SH_S_SXTW_SCALED_REAL - 379726790U, // GLD1SH_S_UXTW_REAL - 379726790U, // GLD1SH_S_UXTW_SCALED_REAL - 883037416U, // GLD1SW_D_IMM_REAL - 379720936U, // GLD1SW_D_REAL - 379720936U, // GLD1SW_D_SCALED_REAL - 379720936U, // GLD1SW_D_SXTW_REAL - 379720936U, // GLD1SW_D_SXTW_SCALED_REAL - 379720936U, // GLD1SW_D_UXTW_REAL - 379720936U, // GLD1SW_D_UXTW_SCALED_REAL - 883037238U, // GLD1W_D_IMM_REAL - 379720758U, // GLD1W_D_REAL - 379720758U, // GLD1W_D_SCALED_REAL - 379720758U, // GLD1W_D_SXTW_REAL - 379720758U, // GLD1W_D_SXTW_SCALED_REAL - 379720758U, // GLD1W_D_UXTW_REAL - 379720758U, // GLD1W_D_UXTW_SCALED_REAL - 815936566U, // GLD1W_IMM_REAL - 379728950U, // GLD1W_SXTW_REAL - 379728950U, // GLD1W_SXTW_SCALED_REAL - 379728950U, // GLD1W_UXTW_REAL - 379728950U, // GLD1W_UXTW_SCALED_REAL - 883032946U, // GLDFF1B_D_IMM_REAL - 379716466U, // GLDFF1B_D_REAL - 379716466U, // GLDFF1B_D_SXTW_REAL - 379716466U, // GLDFF1B_D_UXTW_REAL - 815932274U, // GLDFF1B_S_IMM_REAL - 379724658U, // GLDFF1B_S_SXTW_REAL - 379724658U, // GLDFF1B_S_UXTW_REAL - 883033926U, // GLDFF1D_IMM_REAL - 379717446U, // GLDFF1D_REAL - 379717446U, // GLDFF1D_SCALED_REAL - 379717446U, // GLDFF1D_SXTW_REAL - 379717446U, // GLDFF1D_SXTW_SCALED_REAL - 379717446U, // GLDFF1D_UXTW_REAL - 379717446U, // GLDFF1D_UXTW_SCALED_REAL - 3030518068U, // GLDFF1H_D_IMM_REAL - 379717940U, // GLDFF1H_D_REAL - 379717940U, // GLDFF1H_D_SCALED_REAL - 379717940U, // GLDFF1H_D_SXTW_REAL - 379717940U, // GLDFF1H_D_SXTW_SCALED_REAL - 379717940U, // GLDFF1H_D_UXTW_REAL - 379717940U, // GLDFF1H_D_UXTW_SCALED_REAL - 2963417396U, // GLDFF1H_S_IMM_REAL - 379726132U, // GLDFF1H_S_SXTW_REAL - 379726132U, // GLDFF1H_S_SXTW_SCALED_REAL - 379726132U, // GLDFF1H_S_UXTW_REAL - 379726132U, // GLDFF1H_S_UXTW_SCALED_REAL - 883033634U, // GLDFF1SB_D_IMM_REAL - 379717154U, // GLDFF1SB_D_REAL - 379717154U, // GLDFF1SB_D_SXTW_REAL - 379717154U, // GLDFF1SB_D_UXTW_REAL - 815932962U, // GLDFF1SB_S_IMM_REAL - 379725346U, // GLDFF1SB_S_SXTW_REAL - 379725346U, // GLDFF1SB_S_UXTW_REAL - 3030518733U, // GLDFF1SH_D_IMM_REAL - 379718605U, // GLDFF1SH_D_REAL - 379718605U, // GLDFF1SH_D_SCALED_REAL - 379718605U, // GLDFF1SH_D_SXTW_REAL - 379718605U, // GLDFF1SH_D_SXTW_SCALED_REAL - 379718605U, // GLDFF1SH_D_UXTW_REAL - 379718605U, // GLDFF1SH_D_UXTW_SCALED_REAL - 2963418061U, // GLDFF1SH_S_IMM_REAL - 379726797U, // GLDFF1SH_S_SXTW_REAL - 379726797U, // GLDFF1SH_S_SXTW_SCALED_REAL - 379726797U, // GLDFF1SH_S_UXTW_REAL - 379726797U, // GLDFF1SH_S_UXTW_SCALED_REAL - 883037423U, // GLDFF1SW_D_IMM_REAL - 379720943U, // GLDFF1SW_D_REAL - 379720943U, // GLDFF1SW_D_SCALED_REAL - 379720943U, // GLDFF1SW_D_SXTW_REAL - 379720943U, // GLDFF1SW_D_SXTW_SCALED_REAL - 379720943U, // GLDFF1SW_D_UXTW_REAL - 379720943U, // GLDFF1SW_D_UXTW_SCALED_REAL - 883037244U, // GLDFF1W_D_IMM_REAL - 379720764U, // GLDFF1W_D_REAL - 379720764U, // GLDFF1W_D_SCALED_REAL - 379720764U, // GLDFF1W_D_SXTW_REAL - 379720764U, // GLDFF1W_D_SXTW_SCALED_REAL - 379720764U, // GLDFF1W_D_UXTW_REAL - 379720764U, // GLDFF1W_D_UXTW_SCALED_REAL - 815936572U, // GLDFF1W_IMM_REAL - 379728956U, // GLDFF1W_SXTW_REAL - 379728956U, // GLDFF1W_SXTW_SCALED_REAL - 379728956U, // GLDFF1W_UXTW_REAL - 379728956U, // GLDFF1W_UXTW_SCALED_REAL - 152359U, // HINT - 78607U, // HLT - 75574U, // HVC - 536921183U, // INCB_XPiI - 536922063U, // INCD_XPiI - 536889295U, // INCD_ZPiI - 536922647U, // INCH_XPiI - 6842903U, // INCH_ZPiI - 2315308999U, // INCP_XP_B - 2348863431U, // INCP_XP_D - 2717962183U, // INCP_XP_H - 2415972295U, // INCP_XP_S - 2147504071U, // INCP_ZP_D - 604532679U, // INCP_ZP_H - 2147520455U, // INCP_ZP_S - 536925367U, // INCW_XPiI - 536908983U, // INCW_ZPiI - 100676987U, // INDEX_II_B - 100685179U, // INDEX_II_D - 242775419U, // INDEX_II_H - 100701563U, // INDEX_II_S - 100676987U, // INDEX_IR_B - 100685179U, // INDEX_IR_D - 242775419U, // INDEX_IR_H - 100701563U, // INDEX_IR_S - 100676987U, // INDEX_RI_B - 100685179U, // INDEX_RI_D - 242775419U, // INDEX_RI_H - 100701563U, // INDEX_RI_S - 100676987U, // INDEX_RR_B - 100685179U, // INDEX_RR_D - 242775419U, // INDEX_RR_H - 100701563U, // INDEX_RR_S - 2516595051U, // INSR_ZR_B - 2516603243U, // INSR_ZR_D - 615018859U, // INSR_ZR_H - 2516619627U, // INSR_ZR_S - 2516595051U, // INSR_ZV_B - 2516603243U, // INSR_ZV_D - 615018859U, // INSR_ZV_H - 2516619627U, // INSR_ZV_S - 3065049710U, // INSvi16gpr - 951120494U, // INSvi16lane - 3065573998U, // INSvi32gpr - 3099128430U, // INSvi32lane - 3063476846U, // INSvi64gpr - 949547630U, // INSvi64lane - 3066098286U, // INSvi8gpr - 3099652718U, // INSvi8lane - 116287U, // ISB - 302039859U, // LASTA_RPZ_B - 302039859U, // LASTA_RPZ_D - 302039859U, // LASTA_RPZ_H - 302039859U, // LASTA_RPZ_S - 302039859U, // LASTA_VPZ_B - 302039859U, // LASTA_VPZ_D - 302039859U, // LASTA_VPZ_H - 302039859U, // LASTA_VPZ_S - 302040718U, // LASTB_RPZ_B - 302040718U, // LASTB_RPZ_D - 302040718U, // LASTB_RPZ_H - 302040718U, // LASTB_RPZ_S - 302040718U, // LASTB_VPZ_B - 302040718U, // LASTB_VPZ_D - 302040718U, // LASTB_VPZ_H - 302040718U, // LASTB_VPZ_S - 379741036U, // LD1B - 379716460U, // LD1B_D - 379716460U, // LD1B_D_IMM_REAL - 379749228U, // LD1B_H - 379749228U, // LD1B_H_IMM_REAL - 379741036U, // LD1B_IMM_REAL - 379724652U, // LD1B_S - 379724652U, // LD1B_S_IMM_REAL - 379717440U, // LD1D - 379717440U, // LD1D_IMM_REAL - 172064U, // LD1Fourv16b - 13287456U, // LD1Fourv16b_POST - 188448U, // LD1Fourv1d - 13828128U, // LD1Fourv1d_POST - 204832U, // LD1Fourv2d - 13320224U, // LD1Fourv2d_POST - 221216U, // LD1Fourv2s - 13860896U, // LD1Fourv2s_POST - 237600U, // LD1Fourv4h - 13877280U, // LD1Fourv4h_POST - 253984U, // LD1Fourv4s - 13369376U, // LD1Fourv4s_POST - 270368U, // LD1Fourv8b - 13910048U, // LD1Fourv8b_POST - 286752U, // LD1Fourv8h - 13402144U, // LD1Fourv8h_POST - 379750702U, // LD1H - 379717934U, // LD1H_D - 379717934U, // LD1H_D_IMM_REAL - 379750702U, // LD1H_IMM_REAL - 379726126U, // LD1H_S - 379726126U, // LD1H_S_IMM_REAL - 172064U, // LD1Onev16b - 14336032U, // LD1Onev16b_POST - 188448U, // LD1Onev1d - 14876704U, // LD1Onev1d_POST - 204832U, // LD1Onev2d - 14368800U, // LD1Onev2d_POST - 221216U, // LD1Onev2s - 14909472U, // LD1Onev2s_POST - 237600U, // LD1Onev4h - 14925856U, // LD1Onev4h_POST - 253984U, // LD1Onev4s - 14417952U, // LD1Onev4s_POST - 270368U, // LD1Onev8b - 14958624U, // LD1Onev8b_POST - 286752U, // LD1Onev8h - 14450720U, // LD1Onev8h_POST - 379716999U, // LD1RB_D_IMM - 379749767U, // LD1RB_H_IMM - 379741575U, // LD1RB_IMM - 379725191U, // LD1RB_S_IMM - 379717698U, // LD1RD_IMM - 379718450U, // LD1RH_D_IMM - 379751218U, // LD1RH_IMM - 379726642U, // LD1RH_S_IMM - 379741567U, // LD1RQ_B - 379741567U, // LD1RQ_B_IMM - 379717690U, // LD1RQ_D - 379717690U, // LD1RQ_D_IMM - 379751210U, // LD1RQ_H - 379751210U, // LD1RQ_H_IMM - 379729113U, // LD1RQ_W - 379729113U, // LD1RQ_W_IMM - 379717201U, // LD1RSB_D_IMM - 379749969U, // LD1RSB_H_IMM - 379725393U, // LD1RSB_S_IMM - 379718639U, // LD1RSH_D_IMM - 379726831U, // LD1RSH_S_IMM - 379720968U, // LD1RSW_IMM - 379720929U, // LD1RW_D_IMM - 379729121U, // LD1RW_IMM - 176305U, // LD1Rv16b - 15388849U, // LD1Rv16b_POST - 192689U, // LD1Rv1d - 14880945U, // LD1Rv1d_POST - 209073U, // LD1Rv2d - 14897329U, // LD1Rv2d_POST - 225457U, // LD1Rv2s - 15962289U, // LD1Rv2s_POST - 241841U, // LD1Rv4h - 16502961U, // LD1Rv4h_POST - 258225U, // LD1Rv4s - 15995057U, // LD1Rv4s_POST - 274609U, // LD1Rv8b - 15487153U, // LD1Rv8b_POST - 290993U, // LD1Rv8h - 16552113U, // LD1Rv8h_POST - 379717147U, // LD1SB_D - 379717147U, // LD1SB_D_IMM_REAL - 379749915U, // LD1SB_H - 379749915U, // LD1SB_H_IMM_REAL - 379725339U, // LD1SB_S - 379725339U, // LD1SB_S_IMM_REAL - 379718598U, // LD1SH_D - 379718598U, // LD1SH_D_IMM_REAL - 379726790U, // LD1SH_S - 379726790U, // LD1SH_S_IMM_REAL - 379720936U, // LD1SW_D - 379720936U, // LD1SW_D_IMM_REAL - 172064U, // LD1Threev16b - 16957472U, // LD1Threev16b_POST - 188448U, // LD1Threev1d - 17498144U, // LD1Threev1d_POST - 204832U, // LD1Threev2d - 16990240U, // LD1Threev2d_POST - 221216U, // LD1Threev2s - 17530912U, // LD1Threev2s_POST - 237600U, // LD1Threev4h - 17547296U, // LD1Threev4h_POST - 253984U, // LD1Threev4s - 17039392U, // LD1Threev4s_POST - 270368U, // LD1Threev8b - 17580064U, // LD1Threev8b_POST - 286752U, // LD1Threev8h - 17072160U, // LD1Threev8h_POST - 172064U, // LD1Twov16b - 13811744U, // LD1Twov16b_POST - 188448U, // LD1Twov1d - 14352416U, // LD1Twov1d_POST - 204832U, // LD1Twov2d - 13844512U, // LD1Twov2d_POST - 221216U, // LD1Twov2s - 14385184U, // LD1Twov2s_POST - 237600U, // LD1Twov4h - 14401568U, // LD1Twov4h_POST - 253984U, // LD1Twov4s - 13893664U, // LD1Twov4s_POST - 270368U, // LD1Twov8b - 14434336U, // LD1Twov8b_POST - 286752U, // LD1Twov8h - 13926432U, // LD1Twov8h_POST - 379728950U, // LD1W - 379720758U, // LD1W_D - 379720758U, // LD1W_D_IMM_REAL - 379728950U, // LD1W_IMM_REAL - 18128928U, // LD1i16 - 18661408U, // LD1i16_POST - 18145312U, // LD1i32 - 19202080U, // LD1i32_POST - 18161696U, // LD1i64 - 19742752U, // LD1i64_POST - 18178080U, // LD1i8 - 20283424U, // LD1i8_POST - 379741097U, // LD2B - 379741097U, // LD2B_IMM - 379717484U, // LD2D - 379717484U, // LD2D_IMM - 379750763U, // LD2H - 379750763U, // LD2H_IMM - 176311U, // LD2Rv16b - 16437431U, // LD2Rv16b_POST - 192695U, // LD2Rv1d - 14356663U, // LD2Rv1d_POST - 209079U, // LD2Rv2d - 14373047U, // LD2Rv2d_POST - 225463U, // LD2Rv2s - 14913719U, // LD2Rv2s_POST - 241847U, // LD2Rv4h - 15978679U, // LD2Rv4h_POST - 258231U, // LD2Rv4s - 14946487U, // LD2Rv4s_POST - 274615U, // LD2Rv8b - 16535735U, // LD2Rv8b_POST - 290999U, // LD2Rv8h - 16027831U, // LD2Rv8h_POST - 172162U, // LD2Twov16b - 13811842U, // LD2Twov16b_POST - 204930U, // LD2Twov2d - 13844610U, // LD2Twov2d_POST - 221314U, // LD2Twov2s - 14385282U, // LD2Twov2s_POST - 237698U, // LD2Twov4h - 14401666U, // LD2Twov4h_POST - 254082U, // LD2Twov4s - 13893762U, // LD2Twov4s_POST - 270466U, // LD2Twov8b - 14434434U, // LD2Twov8b_POST - 286850U, // LD2Twov8h - 13926530U, // LD2Twov8h_POST - 379729002U, // LD2W - 379729002U, // LD2W_IMM - 18129026U, // LD2i16 - 19185794U, // LD2i16_POST - 18145410U, // LD2i32 - 19726466U, // LD2i32_POST - 18161794U, // LD2i64 - 20791426U, // LD2i64_POST - 18178178U, // LD2i8 - 18710658U, // LD2i8_POST - 379741118U, // LD3B - 379741118U, // LD3B_IMM - 379717496U, // LD3D - 379717496U, // LD3D_IMM - 379750775U, // LD3H - 379750775U, // LD3H_IMM - 176317U, // LD3Rv16b - 21156029U, // LD3Rv16b_POST - 192701U, // LD3Rv1d - 17502397U, // LD3Rv1d_POST - 209085U, // LD3Rv2d - 17518781U, // LD3Rv2d_POST - 225469U, // LD3Rv2s - 21729469U, // LD3Rv2s_POST - 241853U, // LD3Rv4h - 22270141U, // LD3Rv4h_POST - 258237U, // LD3Rv4s - 21762237U, // LD3Rv4s_POST - 274621U, // LD3Rv8b - 21254333U, // LD3Rv8b_POST - 291005U, // LD3Rv8h - 22319293U, // LD3Rv8h_POST - 172553U, // LD3Threev16b - 16957961U, // LD3Threev16b_POST - 205321U, // LD3Threev2d - 16990729U, // LD3Threev2d_POST - 221705U, // LD3Threev2s - 17531401U, // LD3Threev2s_POST - 238089U, // LD3Threev4h - 17547785U, // LD3Threev4h_POST - 254473U, // LD3Threev4s - 17039881U, // LD3Threev4s_POST - 270857U, // LD3Threev8b - 17580553U, // LD3Threev8b_POST - 287241U, // LD3Threev8h - 17072649U, // LD3Threev8h_POST - 379729014U, // LD3W - 379729014U, // LD3W_IMM - 18129417U, // LD3i16 - 22856201U, // LD3i16_POST - 18145801U, // LD3i32 - 23396873U, // LD3i32_POST - 18162185U, // LD3i64 - 23937545U, // LD3i64_POST - 18178569U, // LD3i8 - 24478217U, // LD3i8_POST - 379741130U, // LD4B - 379741130U, // LD4B_IMM - 379717508U, // LD4D - 379717508U, // LD4D_IMM - 172583U, // LD4Fourv16b - 13287975U, // LD4Fourv16b_POST - 205351U, // LD4Fourv2d - 13320743U, // LD4Fourv2d_POST - 221735U, // LD4Fourv2s - 13861415U, // LD4Fourv2s_POST - 238119U, // LD4Fourv4h - 13877799U, // LD4Fourv4h_POST - 254503U, // LD4Fourv4s - 13369895U, // LD4Fourv4s_POST - 270887U, // LD4Fourv8b - 13910567U, // LD4Fourv8b_POST - 287271U, // LD4Fourv8h - 13402663U, // LD4Fourv8h_POST - 379750787U, // LD4H - 379750787U, // LD4H_IMM - 176323U, // LD4Rv16b - 15913155U, // LD4Rv16b_POST - 192707U, // LD4Rv1d - 13832387U, // LD4Rv1d_POST - 209091U, // LD4Rv2d - 13848771U, // LD4Rv2d_POST - 225475U, // LD4Rv2s - 14389443U, // LD4Rv2s_POST - 241859U, // LD4Rv4h - 14930115U, // LD4Rv4h_POST - 258243U, // LD4Rv4s - 14422211U, // LD4Rv4s_POST - 274627U, // LD4Rv8b - 16011459U, // LD4Rv8b_POST - 291011U, // LD4Rv8h - 14979267U, // LD4Rv8h_POST - 379729026U, // LD4W - 379729026U, // LD4W_IMM - 18129447U, // LD4i16 - 19710503U, // LD4i16_POST - 18145831U, // LD4i32 - 20775463U, // LD4i32_POST - 18162215U, // LD4i64 - 24986151U, // LD4i64_POST - 18178599U, // LD4i8 - 19235367U, // LD4i8_POST - 973169622U, // LDADDAB - 973171096U, // LDADDAH - 973169821U, // LDADDALB - 973171251U, // LDADDALH - 973171888U, // LDADDALW - 973171888U, // LDADDALX - 973169280U, // LDADDAW - 973169280U, // LDADDAX - 973169780U, // LDADDB - 973171237U, // LDADDH - 973169921U, // LDADDLB - 973171351U, // LDADDLH - 973172058U, // LDADDLW - 973172058U, // LDADDLX - 973170660U, // LDADDW - 973170660U, // LDADDX - 2253964738U, // LDAPRB - 2253966189U, // LDAPRH - 2253967684U, // LDAPRW - 2253967684U, // LDAPRX - 106481133U, // LDAPURBi - 106482584U, // LDAPURHi - 106481264U, // LDAPURSBWi - 106481264U, // LDAPURSBXi - 106482702U, // LDAPURSHWi - 106482702U, // LDAPURSHXi - 106485031U, // LDAPURSWi - 106484117U, // LDAPURXi - 106484117U, // LDAPURi - 2253964686U, // LDARB - 2253966137U, // LDARH - 2253967561U, // LDARW - 2253967561U, // LDARX - 2248200299U, // LDAXPW - 2248200299U, // LDAXPX - 2253964797U, // LDAXRB - 2253966248U, // LDAXRH - 2253967800U, // LDAXRW - 2253967800U, // LDAXRX - 973169678U, // LDCLRAB - 973171142U, // LDCLRAH - 973169861U, // LDCLRALB - 973171291U, // LDCLRALH - 973171955U, // LDCLRALW - 973171955U, // LDCLRALX - 973169394U, // LDCLRAW - 973169394U, // LDCLRAX - 973170083U, // LDCLRB - 973171534U, // LDCLRH - 973169957U, // LDCLRLB - 973171387U, // LDCLRLH - 973172249U, // LDCLRLW - 973172249U, // LDCLRLX - 973173017U, // LDCLRW - 973173017U, // LDCLRX - 973169687U, // LDEORAB - 973171151U, // LDEORAH - 973169871U, // LDEORALB - 973171301U, // LDEORALH - 973171964U, // LDEORALW - 973171964U, // LDEORALX - 973169402U, // LDEORAW - 973169402U, // LDEORAX - 973170106U, // LDEORB - 973171557U, // LDEORH - 973169966U, // LDEORLB - 973171396U, // LDEORLH - 973172257U, // LDEORLW - 973172257U, // LDEORLX - 973173043U, // LDEORW - 973173043U, // LDEORX - 379716466U, // LDFF1B_D_REAL - 379749234U, // LDFF1B_H_REAL - 379741042U, // LDFF1B_REAL - 379724658U, // LDFF1B_S_REAL - 379717446U, // LDFF1D_REAL - 379717940U, // LDFF1H_D_REAL - 379750708U, // LDFF1H_REAL - 379726132U, // LDFF1H_S_REAL - 379717154U, // LDFF1SB_D_REAL - 379749922U, // LDFF1SB_H_REAL - 379725346U, // LDFF1SB_S_REAL - 379718605U, // LDFF1SH_D_REAL - 379726797U, // LDFF1SH_S_REAL - 379720943U, // LDFF1SW_D_REAL - 379720764U, // LDFF1W_D_REAL - 379728956U, // LDFF1W_REAL - 2253964693U, // LDLARB - 2253966144U, // LDLARH - 2253967567U, // LDLARW - 2253967567U, // LDLARX - 379716474U, // LDNF1B_D_IMM_REAL - 379749242U, // LDNF1B_H_IMM_REAL - 379741050U, // LDNF1B_IMM_REAL - 379724666U, // LDNF1B_S_IMM_REAL - 379717454U, // LDNF1D_IMM_REAL - 379717948U, // LDNF1H_D_IMM_REAL - 379750716U, // LDNF1H_IMM_REAL - 379726140U, // LDNF1H_S_IMM_REAL - 379717163U, // LDNF1SB_D_IMM_REAL - 379749931U, // LDNF1SB_H_IMM_REAL - 379725355U, // LDNF1SB_S_IMM_REAL - 379718614U, // LDNF1SH_D_IMM_REAL - 379726806U, // LDNF1SH_S_IMM_REAL - 379720952U, // LDNF1SW_D_IMM_REAL - 379720772U, // LDNF1W_D_IMM_REAL - 379728964U, // LDNF1W_IMM_REAL - 2248200224U, // LDNPDi - 2248200224U, // LDNPQi - 2248200224U, // LDNPSi - 2248200224U, // LDNPWi - 2248200224U, // LDNPXi - 379741058U, // LDNT1B_ZRI - 379741058U, // LDNT1B_ZRR - 379717462U, // LDNT1D_ZRI - 379717462U, // LDNT1D_ZRR - 379750724U, // LDNT1H_ZRI - 379750724U, // LDNT1H_ZRR - 379728972U, // LDNT1W_ZRI - 379728972U, // LDNT1W_ZRR - 2248200156U, // LDPDi - 2516676572U, // LDPDpost - 2516676572U, // LDPDpre - 2248200156U, // LDPQi - 2516676572U, // LDPQpost - 2516676572U, // LDPQpre - 2248201473U, // LDPSWi - 2516677889U, // LDPSWpost - 2516677889U, // LDPSWpre - 2248200156U, // LDPSi - 2516676572U, // LDPSpost - 2516676572U, // LDPSpre - 2248200156U, // LDPWi - 2516676572U, // LDPWpost - 2516676572U, // LDPWpre - 2248200156U, // LDPXi - 2516676572U, // LDPXpost - 2516676572U, // LDPXpre - 106480223U, // LDRAAindexed - 374956639U, // LDRAAwriteback - 106480640U, // LDRABindexed - 374957056U, // LDRABwriteback - 374957469U, // LDRBBpost - 374957469U, // LDRBBpre - 106481053U, // LDRBBroW - 106481053U, // LDRBBroX - 106481053U, // LDRBBui - 374960359U, // LDRBpost - 374960359U, // LDRBpre - 106483943U, // LDRBroW - 106483943U, // LDRBroX - 106483943U, // LDRBui - 436261095U, // LDRDl - 374960359U, // LDRDpost - 374960359U, // LDRDpre - 106483943U, // LDRDroW - 106483943U, // LDRDroX - 106483943U, // LDRDui - 374958920U, // LDRHHpost - 374958920U, // LDRHHpre - 106482504U, // LDRHHroW - 106482504U, // LDRHHroX - 106482504U, // LDRHHui - 374960359U, // LDRHpost - 374960359U, // LDRHpre - 106483943U, // LDRHroW - 106483943U, // LDRHroX - 106483943U, // LDRHui - 436261095U, // LDRQl - 374960359U, // LDRQpost - 374960359U, // LDRQpre - 106483943U, // LDRQroW - 106483943U, // LDRQroX - 106483943U, // LDRQui - 374957657U, // LDRSBWpost - 374957657U, // LDRSBWpre - 106481241U, // LDRSBWroW - 106481241U, // LDRSBWroX - 106481241U, // LDRSBWui - 374957657U, // LDRSBXpost - 374957657U, // LDRSBXpre - 106481241U, // LDRSBXroW - 106481241U, // LDRSBXroX - 106481241U, // LDRSBXui - 374959095U, // LDRSHWpost - 374959095U, // LDRSHWpre - 106482679U, // LDRSHWroW - 106482679U, // LDRSHWroX - 106482679U, // LDRSHWui - 374959095U, // LDRSHXpost - 374959095U, // LDRSHXpre - 106482679U, // LDRSHXroW - 106482679U, // LDRSHXroX - 106482679U, // LDRSHXui - 436262160U, // LDRSWl - 374961424U, // LDRSWpost - 374961424U, // LDRSWpre - 106485008U, // LDRSWroW - 106485008U, // LDRSWroX - 106485008U, // LDRSWui - 436261095U, // LDRSl - 374960359U, // LDRSpost - 374960359U, // LDRSpre - 106483943U, // LDRSroW - 106483943U, // LDRSroX - 106483943U, // LDRSui - 436261095U, // LDRWl - 374960359U, // LDRWpost - 374960359U, // LDRWpre - 106483943U, // LDRWroW - 106483943U, // LDRWroX - 106483943U, // LDRWui - 436261095U, // LDRXl - 374960359U, // LDRXpost - 374960359U, // LDRXpre - 106483943U, // LDRXroW - 106483943U, // LDRXroX - 106483943U, // LDRXui - 106803431U, // LDR_PXI - 106803431U, // LDR_ZXI - 973169703U, // LDSETAB - 973171167U, // LDSETAH - 973169889U, // LDSETALB - 973171319U, // LDSETALH - 973171980U, // LDSETALW - 973171980U, // LDSETALX - 973169442U, // LDSETAW - 973169442U, // LDSETAX - 973170303U, // LDSETB - 973171736U, // LDSETH - 973169982U, // LDSETLB - 973171412U, // LDSETLH - 973172305U, // LDSETLW - 973172305U, // LDSETLX - 973173476U, // LDSETW - 973173476U, // LDSETX - 973169712U, // LDSMAXAB - 973171176U, // LDSMAXAH - 973169899U, // LDSMAXALB - 973171329U, // LDSMAXALH - 973171989U, // LDSMAXALW - 973171989U, // LDSMAXALX - 973169466U, // LDSMAXAW - 973169466U, // LDSMAXAX - 973170392U, // LDSMAXB - 973171768U, // LDSMAXH - 973169991U, // LDSMAXLB - 973171454U, // LDSMAXLH - 973172360U, // LDSMAXLW - 973172360U, // LDSMAXLX - 973174109U, // LDSMAXW - 973174109U, // LDSMAXX - 973169631U, // LDSMINAB - 973171115U, // LDSMINAH - 973169831U, // LDSMINALB - 973171261U, // LDSMINALH - 973171920U, // LDSMINALW - 973171920U, // LDSMINALX - 973169349U, // LDSMINAW - 973169349U, // LDSMINAX - 973170016U, // LDSMINB - 973171474U, // LDSMINH - 973169930U, // LDSMINLB - 973171360U, // LDSMINLH - 973172211U, // LDSMINLW - 973172211U, // LDSMINLX - 973172462U, // LDSMINW - 973172462U, // LDSMINX - 106481098U, // LDTRBi - 106482549U, // LDTRHi - 106481248U, // LDTRSBWi - 106481248U, // LDTRSBXi - 106482686U, // LDTRSHWi - 106482686U, // LDTRSHXi - 106485015U, // LDTRSWi - 106484081U, // LDTRWi - 106484081U, // LDTRXi - 973169722U, // LDUMAXAB - 973171186U, // LDUMAXAH - 973169910U, // LDUMAXALB - 973171340U, // LDUMAXALH - 973171999U, // LDUMAXALW - 973171999U, // LDUMAXALX - 973169475U, // LDUMAXAW - 973169475U, // LDUMAXAX - 973170401U, // LDUMAXB - 973171777U, // LDUMAXH - 973170001U, // LDUMAXLB - 973171464U, // LDUMAXLH - 973172369U, // LDUMAXLW - 973172369U, // LDUMAXLX - 973174117U, // LDUMAXW - 973174117U, // LDUMAXX - 973169641U, // LDUMINAB - 973171125U, // LDUMINAH - 973169842U, // LDUMINALB - 973171272U, // LDUMINALH - 973171930U, // LDUMINALW - 973171930U, // LDUMINALX - 973169358U, // LDUMINAW - 973169358U, // LDUMINAX - 973170025U, // LDUMINB - 973171483U, // LDUMINH - 973169940U, // LDUMINLB - 973171370U, // LDUMINLH - 973172220U, // LDUMINLW - 973172220U, // LDUMINLX - 973172470U, // LDUMINW - 973172470U, // LDUMINX - 106481118U, // LDURBBi - 106484104U, // LDURBi - 106484104U, // LDURDi - 106482569U, // LDURHHi - 106484104U, // LDURHi - 106484104U, // LDURQi - 106481256U, // LDURSBWi - 106481256U, // LDURSBXi - 106482694U, // LDURSHWi - 106482694U, // LDURSHXi - 106485023U, // LDURSWi - 106484104U, // LDURSi - 106484104U, // LDURWi - 106484104U, // LDURXi - 2248200327U, // LDXPW - 2248200327U, // LDXPX - 2253964805U, // LDXRB - 2253966256U, // LDXRH - 2253967807U, // LDXRW - 2253967807U, // LDXRX - 0U, // LOADgot - 302002471U, // LSLR_ZPmZ_B - 302010663U, // LSLR_ZPmZ_D - 2186309927U, // LSLR_ZPmZ_H - 302027047U, // LSLR_ZPmZ_S - 100716088U, // LSLVWr - 100716088U, // LSLVXr - 302001720U, // LSL_WIDE_ZPmZ_B - 2186309176U, // LSL_WIDE_ZPmZ_H - 302026296U, // LSL_WIDE_ZPmZ_S - 167783992U, // LSL_WIDE_ZZZ_B - 2387111480U, // LSL_WIDE_ZZZ_H - 268471864U, // LSL_WIDE_ZZZ_S - 302001720U, // LSL_ZPmI_B - 302009912U, // LSL_ZPmI_D - 2186309176U, // LSL_ZPmI_H - 302026296U, // LSL_ZPmI_S - 302001720U, // LSL_ZPmZ_B - 302009912U, // LSL_ZPmZ_D - 2186309176U, // LSL_ZPmZ_H - 302026296U, // LSL_ZPmZ_S - 167783992U, // LSL_ZZI_B - 201346616U, // LSL_ZZI_D - 239627832U, // LSL_ZZI_H - 268471864U, // LSL_ZZI_S - 302002518U, // LSRR_ZPmZ_B - 302010710U, // LSRR_ZPmZ_D - 2186309974U, // LSRR_ZPmZ_H - 302027094U, // LSRR_ZPmZ_S - 100716897U, // LSRVWr - 100716897U, // LSRVXr - 302002529U, // LSR_WIDE_ZPmZ_B - 2186309985U, // LSR_WIDE_ZPmZ_H - 302027105U, // LSR_WIDE_ZPmZ_S - 167784801U, // LSR_WIDE_ZZZ_B - 2387112289U, // LSR_WIDE_ZZZ_H - 268472673U, // LSR_WIDE_ZZZ_S - 302002529U, // LSR_ZPmI_B - 302010721U, // LSR_ZPmI_D - 2186309985U, // LSR_ZPmI_H - 302027105U, // LSR_ZPmI_S - 302002529U, // LSR_ZPmZ_B - 302010721U, // LSR_ZPmZ_D - 2186309985U, // LSR_ZPmZ_H - 302027105U, // LSR_ZPmZ_S - 167784801U, // LSR_ZZI_B - 201347425U, // LSR_ZZI_D - 239628641U, // LSR_ZZI_H - 268472673U, // LSR_ZZI_S - 100714512U, // MADDWrrr - 100714512U, // MADDXrrr - 302000017U, // MAD_ZPmZZ_B - 302008209U, // MAD_ZPmZZ_D - 2186307473U, // MAD_ZPmZZ_H - 302024593U, // MAD_ZPmZZ_S - 301998771U, // MLA_ZPmZZ_B - 302006963U, // MLA_ZPmZZ_D - 2186306227U, // MLA_ZPmZZ_H - 302023347U, // MLA_ZPmZZ_S - 135324339U, // MLAv16i8 - 2283332275U, // MLAv2i32 - 2283332275U, // MLAv2i32_indexed - 136897203U, // MLAv4i16 - 136897203U, // MLAv4i16_indexed - 137421491U, // MLAv4i32 - 137421491U, // MLAv4i32_indexed - 2285429427U, // MLAv8i16 - 2285429427U, // MLAv8i16_indexed - 2285953715U, // MLAv8i8 - 302002771U, // MLS_ZPmZZ_B - 302010963U, // MLS_ZPmZZ_D - 2186310227U, // MLS_ZPmZZ_H - 302027347U, // MLS_ZPmZZ_S - 135328339U, // MLSv16i8 - 2283336275U, // MLSv2i32 - 2283336275U, // MLSv2i32_indexed - 136901203U, // MLSv4i16 - 136901203U, // MLSv4i16_indexed - 137425491U, // MLSv4i32 - 137425491U, // MLSv4i32_indexed - 2285433427U, // MLSv8i16 - 2285433427U, // MLSv8i16_indexed - 2285957715U, // MLSv8i8 - 1006685329U, // MOVID - 3188763793U, // MOVIv16b_ns - 1008774289U, // MOVIv2d_ns - 3189288081U, // MOVIv2i32 - 3189288081U, // MOVIv2s_msl - 3190336657U, // MOVIv4i16 - 3190860945U, // MOVIv4i32 - 3190860945U, // MOVIv4s_msl - 3191909521U, // MOVIv8b_ns - 3191385233U, // MOVIv8i16 - 402705564U, // MOVKWi - 402705564U, // MOVKXi - 3187724142U, // MOVNWi - 3187724142U, // MOVNXi - 13705U, // MOVPRFX_ZPmZ_B - 21897U, // MOVPRFX_ZPmZ_D - 2181592457U, // MOVPRFX_ZPmZ_H - 38281U, // MOVPRFX_ZPmZ_S - 302003593U, // MOVPRFX_ZPzZ_B - 302011785U, // MOVPRFX_ZPzZ_D - 2622518665U, // MOVPRFX_ZPzZ_H - 302028169U, // MOVPRFX_ZPzZ_S - 2449847689U, // MOVPRFX_ZZ - 3187725817U, // MOVZWi - 3187725817U, // MOVZXi - 0U, // MOVaddr - 0U, // MOVaddrBA - 0U, // MOVaddrCP - 0U, // MOVaddrEXT - 0U, // MOVaddrJT - 0U, // MOVaddrTLS - 0U, // MOVbaseTLS - 0U, // MOVi32imm - 0U, // MOVi64imm - 1073795744U, // MRS - 301999685U, // MSB_ZPmZZ_B - 302007877U, // MSB_ZPmZZ_D - 2186307141U, // MSB_ZPmZZ_H - 302024261U, // MSB_ZPmZZ_S - 381286U, // MSR - 389478U, // MSRpstateImm1 - 389478U, // MSRpstateImm4 - 100714166U, // MSUBWrrr - 100714166U, // MSUBXrrr - 167784033U, // MUL_ZI_B - 201346657U, // MUL_ZI_D - 239627873U, // MUL_ZI_H - 268471905U, // MUL_ZI_S - 302001761U, // MUL_ZPmZ_B - 302009953U, // MUL_ZPmZ_D - 2186309217U, // MUL_ZPmZ_H - 302026337U, // MUL_ZPmZ_S - 68202081U, // MULv16i8 - 2216210017U, // MULv2i32 - 2216210017U, // MULv2i32_indexed - 69774945U, // MULv4i16 - 69774945U, // MULv4i16_indexed - 70299233U, // MULv4i32 - 70299233U, // MULv4i32_indexed - 2218307169U, // MULv8i16 - 2218307169U, // MULv8i16_indexed - 2218831457U, // MULv8i8 - 3189288062U, // MVNIv2i32 - 3189288062U, // MVNIv2s_msl - 3190336638U, // MVNIv4i16 - 3190860926U, // MVNIv4i32 - 3190860926U, // MVNIv4s_msl - 3191385214U, // MVNIv8i16 - 302002728U, // NANDS_PPzPP - 302000180U, // NAND_PPzPP - 10516U, // NEG_ZPmZ_B - 18708U, // NEG_ZPmZ_D - 2181589268U, // NEG_ZPmZ_H - 35092U, // NEG_ZPmZ_S - 68200724U, // NEGv16i8 - 2248198420U, // NEGv1i64 - 68725012U, // NEGv2i32 - 2216732948U, // NEGv2i64 - 69773588U, // NEGv4i16 - 2217781524U, // NEGv4i32 - 70822164U, // NEGv8i16 - 2218830100U, // NEGv8i8 - 302002859U, // NORS_PPzPP - 302002490U, // NOR_PPzPP - 13114U, // NOT_ZPmZ_B - 21306U, // NOT_ZPmZ_D - 2181591866U, // NOT_ZPmZ_H - 37690U, // NOT_ZPmZ_S - 68203322U, // NOTv16i8 - 2218832698U, // NOTv8i8 - 302002810U, // ORNS_PPzPP - 0U, // ORNWrr - 100716337U, // ORNWrs - 0U, // ORNXrr - 100716337U, // ORNXrs - 302001969U, // ORN_PPzPP - 68202289U, // ORNv16i8 - 2218831665U, // ORNv8i8 - 302002865U, // ORRS_PPzPP - 100716875U, // ORRWri - 0U, // ORRWrr - 100716875U, // ORRWrs - 100716875U, // ORRXri - 0U, // ORRXrr - 100716875U, // ORRXrs - 302002507U, // ORR_PPzPP - 201347403U, // ORR_ZI - 302002507U, // ORR_ZPmZ_B - 302010699U, // ORR_ZPmZ_D - 2186309963U, // ORR_ZPmZ_H - 302027083U, // ORR_ZPmZ_S - 201347403U, // ORR_ZZZ - 68202827U, // ORRv16i8 - 404287819U, // ORRv2i32 - 405336395U, // ORRv4i16 - 405860683U, // ORRv4i32 - 406384971U, // ORRv8i16 - 2218832203U, // ORRv8i8 - 302044188U, // ORV_VPZ_B - 302044188U, // ORV_VPZ_D - 302044188U, // ORV_VPZ_H - 302044188U, // ORV_VPZ_S - 2248196729U, // PACDA - 2248197229U, // PACDB - 6341452U, // PACDZA - 6342378U, // PACDZB - 100713110U, // PACGA - 2248196765U, // PACIA - 5796U, // PACIA1716 - 5927U, // PACIASP - 5982U, // PACIAZ - 2248197257U, // PACIB - 5816U, // PACIB1716 - 5943U, // PACIBSP - 5996U, // PACIBZ - 6341468U, // PACIZA - 6342394U, // PACIZB - 6301913U, // PFALSE - 70820111U, // PMULLv16i8 - 1132506590U, // PMULLv1i64 - 1166057743U, // PMULLv2i64 - 2218307038U, // PMULLv8i8 - 68202093U, // PMULv16i8 - 2218831469U, // PMULv8i8 - 302003042U, // PNEXT_B - 302011234U, // PNEXT_D - 2387637090U, // PNEXT_H - 302027618U, // PNEXT_S - 3079537795U, // PRFB_D_PZI - 246285443U, // PRFB_D_SCALED - 2393769091U, // PRFB_D_SXTW_SCALED - 246285443U, // PRFB_D_UXTW_SCALED - 246285443U, // PRFB_PRI - 2393769091U, // PRFB_PRR - 3080062083U, // PRFB_S_PZI - 246285443U, // PRFB_S_SXTW_SCALED - 2393769091U, // PRFB_S_UXTW_SCALED - 1200490542U, // PRFD_D_PZI - 246286382U, // PRFD_D_SCALED - 2393770030U, // PRFD_D_SXTW_SCALED - 246286382U, // PRFD_D_UXTW_SCALED - 246286382U, // PRFD_PRI - 2393770030U, // PRFD_PRR - 1201014830U, // PRFD_S_PZI - 246286382U, // PRFD_S_SXTW_SCALED - 2393770030U, // PRFD_S_UXTW_SCALED - 1234045485U, // PRFH_D_PZI - 246286893U, // PRFH_D_SCALED - 2393770541U, // PRFH_D_SXTW_SCALED - 246286893U, // PRFH_D_UXTW_SCALED - 246286893U, // PRFH_PRI - 2393770541U, // PRFH_PRR - 1234569773U, // PRFH_S_PZI - 246286893U, // PRFH_S_SXTW_SCALED - 2393770541U, // PRFH_S_UXTW_SCALED - 436612781U, // PRFMl - 106835629U, // PRFMroW - 106835629U, // PRFMroX - 106835629U, // PRFMui - 246289619U, // PRFS_PRR - 106835665U, // PRFUMi - 1267602643U, // PRFW_D_PZI - 2393773267U, // PRFW_D_SCALED - 246289619U, // PRFW_D_SXTW_SCALED - 2393773267U, // PRFW_D_UXTW_SCALED - 246289619U, // PRFW_PRI - 1268126931U, // PRFW_S_PZI - 246289619U, // PRFW_S_SXTW_SCALED - 2393773267U, // PRFW_S_UXTW_SCALED - 2315629382U, // PTEST_PP - 2650812975U, // PTRUES_B - 2650821167U, // PTRUES_D - 26767919U, // PTRUES_H - 2650837551U, // PTRUES_S - 2650810611U, // PTRUE_B - 2650818803U, // PTRUE_D - 26765555U, // PTRUE_H - 2650835187U, // PTRUE_S - 27290705U, // PUNPKHI_PP - 27291525U, // PUNPKLO_PP - 2216210144U, // RADDHNv2i64_v2i32 - 2284904786U, // RADDHNv2i64_v4i32 - 69775072U, // RADDHNv4i32_v4i16 - 137945426U, // RADDHNv4i32_v8i16 - 2282807634U, // RADDHNv8i16_v16i8 - 2218831584U, // RADDHNv8i16_v8i8 - 2216730741U, // RAX1 - 2248200960U, // RBITWr - 2248200960U, // RBITXr - 13056U, // RBIT_ZPmZ_B - 21248U, // RBIT_ZPmZ_D - 2181591808U, // RBIT_ZPmZ_H - 37632U, // RBIT_ZPmZ_S - 68203264U, // RBITv16i8 - 2218832640U, // RBITv8i8 - 302002840U, // RDFFRS_PPz - 6303980U, // RDFFR_P - 302002412U, // RDFFR_PPz - 2248199810U, // RDVLI_XI - 6345439U, // RET - 5892U, // RETAA - 5899U, // RETAB - 0U, // RET_ReallyLR - 2248196665U, // REV16Wr - 2248196665U, // REV16Xr - 68198969U, // REV16v16i8 - 2218828345U, // REV16v8i8 - 2248196219U, // REV32Xr - 68198523U, // REV32v16i8 - 69771387U, // REV32v4i16 - 70819963U, // REV32v8i16 - 2218827899U, // REV32v8i8 - 68198944U, // REV64v16i8 - 68723232U, // REV64v2i32 - 69771808U, // REV64v4i16 - 2217779744U, // REV64v4i32 - 70820384U, // REV64v8i16 - 2218828320U, // REV64v8i8 - 18130U, // REVB_ZPmZ_D - 2181588690U, // REVB_ZPmZ_H - 34514U, // REVB_ZPmZ_S - 19506U, // REVH_ZPmZ_D - 35890U, // REVH_ZPmZ_S - 21827U, // REVW_ZPmZ_D - 2248201140U, // REVWr - 2248201140U, // REVXr - 2315269044U, // REV_PP_B - 2348831668U, // REV_PP_D - 608727988U, // REV_PP_H - 2415956916U, // REV_PP_S - 2315269044U, // REV_ZZ_B - 2348831668U, // REV_ZZ_D - 608727988U, // REV_ZZ_H - 2415956916U, // REV_ZZ_S - 100714751U, // RMIF - 100716863U, // RORVWr - 100716863U, // RORVXr - 2282807663U, // RSHRNv16i8_shift - 2216210209U, // RSHRNv2i32_shift - 69775137U, // RSHRNv4i16_shift - 2284904815U, // RSHRNv4i32_shift - 137945455U, // RSHRNv8i16_shift - 2218831649U, // RSHRNv8i8_shift - 2216210136U, // RSUBHNv2i64_v2i32 - 2284904777U, // RSUBHNv2i64_v4i32 - 69775064U, // RSUBHNv4i32_v4i16 - 137945417U, // RSUBHNv4i32_v8i16 - 2282807625U, // RSUBHNv8i16_v16i8 - 2218831576U, // RSUBHNv8i16_v8i8 - 137945243U, // SABALv16i8_v8i16 - 2283859106U, // SABALv2i32_v2i64 - 137424034U, // SABALv4i16_v4i32 - 136372379U, // SABALv4i32_v2i64 - 2284904603U, // SABALv8i16_v4i32 - 2285431970U, // SABALv8i8_v8i16 - 135324269U, // SABAv16i8 - 2283332205U, // SABAv2i32 - 136897133U, // SABAv4i16 - 137421421U, // SABAv4i32 - 2285429357U, // SABAv8i16 - 2285953645U, // SABAv8i8 - 70820053U, // SABDLv16i8_v8i16 - 2216734028U, // SABDLv2i32_v2i64 - 70298956U, // SABDLv4i16_v4i32 - 69247189U, // SABDLv4i32_v2i64 - 2217779413U, // SABDLv8i16_v4i32 - 2218306892U, // SABDLv8i8_v8i16 - 302000042U, // SABD_ZPmZ_B - 302008234U, // SABD_ZPmZ_D - 2186307498U, // SABD_ZPmZ_H - 302024618U, // SABD_ZPmZ_S - 68200362U, // SABDv16i8 - 2216208298U, // SABDv2i32 - 69773226U, // SABDv4i16 - 70297514U, // SABDv4i32 - 2218305450U, // SABDv8i16 - 2218829738U, // SABDv8i8 - 137949153U, // SADALPv16i8_v8i16 - 162066401U, // SADALPv2i32_v1i64 - 135852001U, // SADALPv4i16_v2i32 - 2283859937U, // SADALPv4i32_v2i64 - 137424865U, // SADALPv8i16_v4i32 - 2284384225U, // SADALPv8i8_v4i16 - 70823921U, // SADDLPv16i8_v8i16 - 94941169U, // SADDLPv2i32_v1i64 - 68726769U, // SADDLPv4i16_v2i32 - 2216734705U, // SADDLPv4i32_v2i64 - 70299633U, // SADDLPv8i16_v4i32 - 2217258993U, // SADDLPv8i8_v4i16 - 67163083U, // SADDLVv16i8v - 67163083U, // SADDLVv4i16v - 2214646731U, // SADDLVv4i32v - 67163083U, // SADDLVv8i16v - 2214646731U, // SADDLVv8i8v - 70820069U, // SADDLv16i8_v8i16 - 2216734066U, // SADDLv2i32_v2i64 - 70298994U, // SADDLv4i16_v4i32 - 69247205U, // SADDLv4i32_v2i64 - 2217779429U, // SADDLv8i16_v4i32 - 2218306930U, // SADDLv8i8_v8i16 - 302044064U, // SADDV_VPZ_B - 302044064U, // SADDV_VPZ_H - 302044064U, // SADDV_VPZ_S - 2218303982U, // SADDWv16i8_v8i16 - 2216735941U, // SADDWv2i32_v2i64 - 70300869U, // SADDWv4i16_v4i32 - 2216731118U, // SADDWv4i32_v2i64 - 70296046U, // SADDWv8i16_v4i32 - 2218308805U, // SADDWv8i8_v8i16 - 100717072U, // SBCSWr - 100717072U, // SBCSXr - 100714257U, // SBCWr - 100714257U, // SBCXr - 100716193U, // SBFMWri - 100716193U, // SBFMXri - 100714757U, // SCVTFSWDri - 100714757U, // SCVTFSWHri - 100714757U, // SCVTFSWSri - 100714757U, // SCVTFSXDri - 100714757U, // SCVTFSXHri - 100714757U, // SCVTFSXSri - 2248198405U, // SCVTFUWDri - 2248198405U, // SCVTFUWHri - 2248198405U, // SCVTFUWSri - 2248198405U, // SCVTFUXDri - 2248198405U, // SCVTFUXHri - 2248198405U, // SCVTFUXSri - 18693U, // SCVTF_ZPmZ_DtoD - 2181589253U, // SCVTF_ZPmZ_DtoH - 35077U, // SCVTF_ZPmZ_DtoS - 2181589253U, // SCVTF_ZPmZ_HtoH - 18693U, // SCVTF_ZPmZ_StoD - 2181589253U, // SCVTF_ZPmZ_StoH - 35077U, // SCVTF_ZPmZ_StoS - 100714757U, // SCVTFd - 100714757U, // SCVTFh - 100714757U, // SCVTFs - 2248198405U, // SCVTFv1i16 - 2248198405U, // SCVTFv1i32 - 2248198405U, // SCVTFv1i64 - 68724997U, // SCVTFv2f32 - 2216732933U, // SCVTFv2f64 - 2216208645U, // SCVTFv2i32_shift - 2216732933U, // SCVTFv2i64_shift - 69773573U, // SCVTFv4f16 - 2217781509U, // SCVTFv4f32 - 69773573U, // SCVTFv4i16_shift - 70297861U, // SCVTFv4i32_shift - 70822149U, // SCVTFv8f16 - 2218305797U, // SCVTFv8i16_shift - 302010794U, // SDIVR_ZPmZ_D - 302027178U, // SDIVR_ZPmZ_S - 100717503U, // SDIVWr - 100717503U, // SDIVXr - 302011327U, // SDIV_ZPmZ_D - 302027711U, // SDIV_ZPmZ_S - 3422573357U, // SDOT_ZZZI_D - 3456144173U, // SDOT_ZZZI_S - 3422573357U, // SDOT_ZZZ_D - 3456144173U, // SDOT_ZZZ_S - 137425709U, // SDOTlanev16i8 - 2283336493U, // SDOTlanev8i8 - 137425709U, // SDOTv16i8 - 2283336493U, // SDOTv8i8 - 302001538U, // SEL_PPPP - 302001538U, // SEL_ZPZZ_B - 302009730U, // SEL_ZPZZ_D - 2387635586U, // SEL_ZPZZ_H - 302026114U, // SEL_ZPZZ_S - 6341169U, // SETF16 - 6341184U, // SETF8 - 5959U, // SETFFR - 369190666U, // SHA1Crrr - 2248198439U, // SHA1Hrr - 369192602U, // SHA1Mrrr - 369192878U, // SHA1Prrr - 137420801U, // SHA1SU0rrr - 2284904523U, // SHA1SU1rr - 369189009U, // SHA256H2rrr - 369191311U, // SHA256Hrrr - 2284904469U, // SHA256SU0rr - 137420895U, // SHA256SU1rrr - 369191258U, // SHA512H - 369188999U, // SHA512H2 - 2216730634U, // SHA512SU0 - 2283855956U, // SHA512SU1 - 68200449U, // SHADDv16i8 - 2216208385U, // SHADDv2i32 - 69773313U, // SHADDv4i16 - 70297601U, // SHADDv4i32 - 2218305537U, // SHADDv8i16 - 2218829825U, // SHADDv8i8 - 70820086U, // SHLLv16i8 - 2216734152U, // SHLLv2i32 - 70299080U, // SHLLv4i16 - 2216730870U, // SHLLv4i32 - 70295798U, // SHLLv8i16 - 2218307016U, // SHLLv8i8 - 100715921U, // SHLd - 68201873U, // SHLv16i8_shift - 2216209809U, // SHLv2i32_shift - 2216734097U, // SHLv2i64_shift - 69774737U, // SHLv4i16_shift - 70299025U, // SHLv4i32_shift - 2218306961U, // SHLv8i16_shift - 2218831249U, // SHLv8i8_shift - 2282807645U, // SHRNv16i8_shift - 2216210193U, // SHRNv2i32_shift - 69775121U, // SHRNv4i16_shift - 2284904797U, // SHRNv4i32_shift - 137945437U, // SHRNv8i16_shift - 2218831633U, // SHRNv8i8_shift - 68200103U, // SHSUBv16i8 - 2216208039U, // SHSUBv2i32 - 69772967U, // SHSUBv4i16 - 70297255U, // SHSUBv4i32 - 2218305191U, // SHSUBv8i16 - 2218829479U, // SHSUBv8i8 - 369192057U, // SLId - 135326841U, // SLIv16i8_shift - 2283334777U, // SLIv2i32_shift - 2283859065U, // SLIv2i64_shift - 136899705U, // SLIv4i16_shift - 137423993U, // SLIv4i32_shift - 2285431929U, // SLIv8i16_shift - 2285956217U, // SLIv8i8_shift - 137420906U, // SM3PARTW1 - 137421310U, // SM3PARTW2 - 70295614U, // SM3SS1 - 137421383U, // SM3TT1A - 137421720U, // SM3TT1B - 137421392U, // SM3TT2A - 137421749U, // SM3TT2B - 2217781339U, // SM4E - 70301097U, // SM4ENCKEY - 100715874U, // SMADDLrrr - 68202617U, // SMAXPv16i8 - 2216210553U, // SMAXPv2i32 - 69775481U, // SMAXPv4i16 - 70299769U, // SMAXPv4i32 - 2218307705U, // SMAXPv8i16 - 2218831993U, // SMAXPv8i8 - 302044200U, // SMAXV_VPZ_B - 302044200U, // SMAXV_VPZ_D - 302044200U, // SMAXV_VPZ_H - 302044200U, // SMAXV_VPZ_S - 67163176U, // SMAXVv16i8v - 67163176U, // SMAXVv4i16v - 2214646824U, // SMAXVv4i32v - 67163176U, // SMAXVv8i16v - 2214646824U, // SMAXVv8i8v - 167785823U, // SMAX_ZI_B - 201348447U, // SMAX_ZI_D - 239629663U, // SMAX_ZI_H - 268473695U, // SMAX_ZI_S - 302003551U, // SMAX_ZPmZ_B - 302011743U, // SMAX_ZPmZ_D - 2186311007U, // SMAX_ZPmZ_H - 302028127U, // SMAX_ZPmZ_S - 68203871U, // SMAXv16i8 - 2216211807U, // SMAXv2i32 - 69776735U, // SMAXv4i16 - 70301023U, // SMAXv4i32 - 2218308959U, // SMAXv8i16 - 2218833247U, // SMAXv8i8 - 75562U, // SMC - 68202541U, // SMINPv16i8 - 2216210477U, // SMINPv2i32 - 69775405U, // SMINPv4i16 - 70299693U, // SMINPv4i32 - 2218307629U, // SMINPv8i16 - 2218831917U, // SMINPv8i8 - 302044148U, // SMINV_VPZ_B - 302044148U, // SMINV_VPZ_D - 302044148U, // SMINV_VPZ_H - 302044148U, // SMINV_VPZ_S - 67163124U, // SMINVv16i8v - 67163124U, // SMINVv4i16v - 2214646772U, // SMINVv4i32v - 67163124U, // SMINVv8i16v - 2214646772U, // SMINVv8i8v - 167784176U, // SMIN_ZI_B - 201346800U, // SMIN_ZI_D - 239628016U, // SMIN_ZI_H - 268472048U, // SMIN_ZI_S - 302001904U, // SMIN_ZPmZ_B - 302010096U, // SMIN_ZPmZ_D - 2186309360U, // SMIN_ZPmZ_H - 302026480U, // SMIN_ZPmZ_S - 68202224U, // SMINv16i8 - 2216210160U, // SMINv2i32 - 69775088U, // SMINv4i16 - 70299376U, // SMINv4i32 - 2218307312U, // SMINv8i16 - 2218831600U, // SMINv8i8 - 137945269U, // SMLALv16i8_v8i16 - 2283859138U, // SMLALv2i32_indexed - 2283859138U, // SMLALv2i32_v2i64 - 137424066U, // SMLALv4i16_indexed - 137424066U, // SMLALv4i16_v4i32 - 136372405U, // SMLALv4i32_indexed - 136372405U, // SMLALv4i32_v2i64 - 2284904629U, // SMLALv8i16_indexed - 2284904629U, // SMLALv8i16_v4i32 - 2285432002U, // SMLALv8i8_v8i16 - 137945393U, // SMLSLv16i8_v8i16 - 2283859517U, // SMLSLv2i32_indexed - 2283859517U, // SMLSLv2i32_v2i64 - 137424445U, // SMLSLv4i16_indexed - 137424445U, // SMLSLv4i16_v4i32 - 136372529U, // SMLSLv4i32_indexed - 136372529U, // SMLSLv4i32_v2i64 - 2284904753U, // SMLSLv8i16_indexed - 2284904753U, // SMLSLv8i16_v4i32 - 2285432381U, // SMLSLv8i8_v8i16 - 67163151U, // SMOVvi16to32 - 67163151U, // SMOVvi16to64 - 2214646799U, // SMOVvi32to64 - 2214646799U, // SMOVvi8to32 - 2214646799U, // SMOVvi8to64 - 100715822U, // SMSUBLrrr - 302000880U, // SMULH_ZPmZ_B - 302009072U, // SMULH_ZPmZ_D - 2186308336U, // SMULH_ZPmZ_H - 302025456U, // SMULH_ZPmZ_S - 100715248U, // SMULHrr - 70820119U, // SMULLv16i8_v8i16 - 2216734181U, // SMULLv2i32_indexed - 2216734181U, // SMULLv2i32_v2i64 - 70299109U, // SMULLv4i16_indexed - 70299109U, // SMULLv4i16_v4i32 - 69247255U, // SMULLv4i32_indexed - 69247255U, // SMULLv4i32_v2i64 - 2217779479U, // SMULLv8i16_indexed - 2217779479U, // SMULLv8i16_v4i32 - 2218307045U, // SMULLv8i8_v8i16 - 302000225U, // SPLICE_ZPZ_B - 302008417U, // SPLICE_ZPZ_D - 2387634273U, // SPLICE_ZPZ_H - 302024801U, // SPLICE_ZPZ_S - 68202996U, // SQABSv16i8 - 2248200692U, // SQABSv1i16 - 2248200692U, // SQABSv1i32 - 2248200692U, // SQABSv1i64 - 2248200692U, // SQABSv1i8 - 68727284U, // SQABSv2i32 - 2216735220U, // SQABSv2i64 - 69775860U, // SQABSv4i16 - 2217783796U, // SQABSv4i32 - 70824436U, // SQABSv8i16 - 2218832372U, // SQABSv8i8 - 167782431U, // SQADD_ZI_B - 201345055U, // SQADD_ZI_D - 239626271U, // SQADD_ZI_H - 268470303U, // SQADD_ZI_S - 167782431U, // SQADD_ZZZ_B - 201345055U, // SQADD_ZZZ_D - 2387109919U, // SQADD_ZZZ_H - 268470303U, // SQADD_ZZZ_S - 68200479U, // SQADDv16i8 - 100714527U, // SQADDv1i16 - 100714527U, // SQADDv1i32 - 100714527U, // SQADDv1i64 - 100714527U, // SQADDv1i8 - 2216208415U, // SQADDv2i32 - 2216732703U, // SQADDv2i64 - 69773343U, // SQADDv4i16 - 70297631U, // SQADDv4i32 - 2218305567U, // SQADDv8i16 - 2218829855U, // SQADDv8i8 - 536921165U, // SQDECB_XPiI - 1342227533U, // SQDECB_XPiWdI - 536922045U, // SQDECD_XPiI - 1342228413U, // SQDECD_XPiWdI - 536889277U, // SQDECD_ZPiI - 536922629U, // SQDECH_XPiI - 1342228997U, // SQDECH_XPiWdI - 6842885U, // SQDECH_ZPiI - 167825333U, // SQDECP_XPWd_B - 201379765U, // SQDECP_XPWd_D - 570478517U, // SQDECP_XPWd_H - 268488629U, // SQDECP_XPWd_S - 2315308981U, // SQDECP_XP_B - 2348863413U, // SQDECP_XP_D - 2717962165U, // SQDECP_XP_H - 2415972277U, // SQDECP_XP_S - 2147504053U, // SQDECP_ZP_D - 604532661U, // SQDECP_ZP_H - 2147520437U, // SQDECP_ZP_S - 536925349U, // SQDECW_XPiI - 1342231717U, // SQDECW_XPiWdI - 536908965U, // SQDECW_ZPiI - 369192121U, // SQDMLALi16 - 369192121U, // SQDMLALi32 - 369192121U, // SQDMLALv1i32_indexed - 369192121U, // SQDMLALv1i64_indexed - 2283859129U, // SQDMLALv2i32_indexed - 2283859129U, // SQDMLALv2i32_v2i64 - 137424057U, // SQDMLALv4i16_indexed - 137424057U, // SQDMLALv4i16_v4i32 - 136372395U, // SQDMLALv4i32_indexed - 136372395U, // SQDMLALv4i32_v2i64 - 2284904619U, // SQDMLALv8i16_indexed - 2284904619U, // SQDMLALv8i16_v4i32 - 369192500U, // SQDMLSLi16 - 369192500U, // SQDMLSLi32 - 369192500U, // SQDMLSLv1i32_indexed - 369192500U, // SQDMLSLv1i64_indexed - 2283859508U, // SQDMLSLv2i32_indexed - 2283859508U, // SQDMLSLv2i32_v2i64 - 137424436U, // SQDMLSLv4i16_indexed - 137424436U, // SQDMLSLv4i16_v4i32 - 136372519U, // SQDMLSLv4i32_indexed - 136372519U, // SQDMLSLv4i32_v2i64 - 2284904743U, // SQDMLSLv8i16_indexed - 2284904743U, // SQDMLSLv8i16_v4i32 - 100715229U, // SQDMULHv1i16 - 100715229U, // SQDMULHv1i16_indexed - 100715229U, // SQDMULHv1i32 - 100715229U, // SQDMULHv1i32_indexed - 2216209117U, // SQDMULHv2i32 - 2216209117U, // SQDMULHv2i32_indexed - 69774045U, // SQDMULHv4i16 - 69774045U, // SQDMULHv4i16_indexed - 70298333U, // SQDMULHv4i32 - 70298333U, // SQDMULHv4i32_indexed - 2218306269U, // SQDMULHv8i16 - 2218306269U, // SQDMULHv8i16_indexed - 100715989U, // SQDMULLi16 - 100715989U, // SQDMULLi32 - 100715989U, // SQDMULLv1i32_indexed - 100715989U, // SQDMULLv1i64_indexed - 2216734165U, // SQDMULLv2i32_indexed - 2216734165U, // SQDMULLv2i32_v2i64 - 70299093U, // SQDMULLv4i16_indexed - 70299093U, // SQDMULLv4i16_v4i32 - 69247237U, // SQDMULLv4i32_indexed - 69247237U, // SQDMULLv4i32_v2i64 - 2217779461U, // SQDMULLv8i16_indexed - 2217779461U, // SQDMULLv8i16_v4i32 - 536921181U, // SQINCB_XPiI - 1342227549U, // SQINCB_XPiWdI - 536922061U, // SQINCD_XPiI - 1342228429U, // SQINCD_XPiWdI - 536889293U, // SQINCD_ZPiI - 536922645U, // SQINCH_XPiI - 1342229013U, // SQINCH_XPiWdI - 6842901U, // SQINCH_ZPiI - 167825349U, // SQINCP_XPWd_B - 201379781U, // SQINCP_XPWd_D - 570478533U, // SQINCP_XPWd_H - 268488645U, // SQINCP_XPWd_S - 2315308997U, // SQINCP_XP_B - 2348863429U, // SQINCP_XP_D - 2717962181U, // SQINCP_XP_H - 2415972293U, // SQINCP_XP_S - 2147504069U, // SQINCP_ZP_D - 604532677U, // SQINCP_ZP_H - 2147520453U, // SQINCP_ZP_S - 536925365U, // SQINCW_XPiI - 1342231733U, // SQINCW_XPiWdI - 536908981U, // SQINCW_ZPiI - 68200729U, // SQNEGv16i8 - 2248198425U, // SQNEGv1i16 - 2248198425U, // SQNEGv1i32 - 2248198425U, // SQNEGv1i64 - 2248198425U, // SQNEGv1i8 - 68725017U, // SQNEGv2i32 - 2216732953U, // SQNEGv2i64 - 69773593U, // SQNEGv4i16 - 2217781529U, // SQNEGv4i32 - 70822169U, // SQNEGv8i16 - 2218830105U, // SQNEGv8i8 - 369191329U, // SQRDMLAHi16_indexed - 369191329U, // SQRDMLAHi32_indexed - 369191329U, // SQRDMLAHv1i16 - 369191329U, // SQRDMLAHv1i32 - 2283334049U, // SQRDMLAHv2i32 - 2283334049U, // SQRDMLAHv2i32_indexed - 136898977U, // SQRDMLAHv4i16 - 136898977U, // SQRDMLAHv4i16_indexed - 137423265U, // SQRDMLAHv4i32 - 137423265U, // SQRDMLAHv4i32_indexed - 2285431201U, // SQRDMLAHv8i16 - 2285431201U, // SQRDMLAHv8i16_indexed - 369191909U, // SQRDMLSHi16_indexed - 369191909U, // SQRDMLSHi32_indexed - 369191909U, // SQRDMLSHv1i16 - 369191909U, // SQRDMLSHv1i32 - 2283334629U, // SQRDMLSHv2i32 - 2283334629U, // SQRDMLSHv2i32_indexed - 136899557U, // SQRDMLSHv4i16 - 136899557U, // SQRDMLSHv4i16_indexed - 137423845U, // SQRDMLSHv4i32 - 137423845U, // SQRDMLSHv4i32_indexed - 2285431781U, // SQRDMLSHv8i16 - 2285431781U, // SQRDMLSHv8i16_indexed - 100715238U, // SQRDMULHv1i16 - 100715238U, // SQRDMULHv1i16_indexed - 100715238U, // SQRDMULHv1i32 - 100715238U, // SQRDMULHv1i32_indexed - 2216209126U, // SQRDMULHv2i32 - 2216209126U, // SQRDMULHv2i32_indexed - 69774054U, // SQRDMULHv4i16 - 69774054U, // SQRDMULHv4i16_indexed - 70298342U, // SQRDMULHv4i32 - 70298342U, // SQRDMULHv4i32_indexed - 2218306278U, // SQRDMULHv8i16 - 2218306278U, // SQRDMULHv8i16_indexed - 68201885U, // SQRSHLv16i8 - 100715933U, // SQRSHLv1i16 - 100715933U, // SQRSHLv1i32 - 100715933U, // SQRSHLv1i64 - 100715933U, // SQRSHLv1i8 - 2216209821U, // SQRSHLv2i32 - 2216734109U, // SQRSHLv2i64 - 69774749U, // SQRSHLv4i16 - 70299037U, // SQRSHLv4i32 - 2218306973U, // SQRSHLv8i16 - 2218831261U, // SQRSHLv8i8 - 100716319U, // SQRSHRNb - 100716319U, // SQRSHRNh - 100716319U, // SQRSHRNs - 2282807661U, // SQRSHRNv16i8_shift - 2216210207U, // SQRSHRNv2i32_shift - 69775135U, // SQRSHRNv4i16_shift - 2284904813U, // SQRSHRNv4i32_shift - 137945453U, // SQRSHRNv8i16_shift - 2218831647U, // SQRSHRNv8i8_shift - 100716380U, // SQRSHRUNb - 100716380U, // SQRSHRUNh - 100716380U, // SQRSHRUNs - 2282807721U, // SQRSHRUNv16i8_shift - 2216210268U, // SQRSHRUNv2i32_shift - 69775196U, // SQRSHRUNv4i16_shift - 2284904873U, // SQRSHRUNv4i32_shift - 137945513U, // SQRSHRUNv8i16_shift - 2218831708U, // SQRSHRUNv8i8_shift - 100717425U, // SQSHLUb - 100717425U, // SQSHLUd - 100717425U, // SQSHLUh - 100717425U, // SQSHLUs - 68203377U, // SQSHLUv16i8_shift - 2216211313U, // SQSHLUv2i32_shift - 2216735601U, // SQSHLUv2i64_shift - 69776241U, // SQSHLUv4i16_shift - 70300529U, // SQSHLUv4i32_shift - 2218308465U, // SQSHLUv8i16_shift - 2218832753U, // SQSHLUv8i8_shift - 100715919U, // SQSHLb - 100715919U, // SQSHLd - 100715919U, // SQSHLh - 100715919U, // SQSHLs - 68201871U, // SQSHLv16i8 - 68201871U, // SQSHLv16i8_shift - 100715919U, // SQSHLv1i16 - 100715919U, // SQSHLv1i32 - 100715919U, // SQSHLv1i64 - 100715919U, // SQSHLv1i8 - 2216209807U, // SQSHLv2i32 - 2216209807U, // SQSHLv2i32_shift - 2216734095U, // SQSHLv2i64 - 2216734095U, // SQSHLv2i64_shift - 69774735U, // SQSHLv4i16 - 69774735U, // SQSHLv4i16_shift - 70299023U, // SQSHLv4i32 - 70299023U, // SQSHLv4i32_shift - 2218306959U, // SQSHLv8i16 - 2218306959U, // SQSHLv8i16_shift - 2218831247U, // SQSHLv8i8 - 2218831247U, // SQSHLv8i8_shift - 100716303U, // SQSHRNb - 100716303U, // SQSHRNh - 100716303U, // SQSHRNs - 2282807643U, // SQSHRNv16i8_shift - 2216210191U, // SQSHRNv2i32_shift - 69775119U, // SQSHRNv4i16_shift - 2284904795U, // SQSHRNv4i32_shift - 137945435U, // SQSHRNv8i16_shift - 2218831631U, // SQSHRNv8i8_shift - 100716371U, // SQSHRUNb - 100716371U, // SQSHRUNh - 100716371U, // SQSHRUNs - 2282807711U, // SQSHRUNv16i8_shift - 2216210259U, // SQSHRUNv2i32_shift - 69775187U, // SQSHRUNv4i16_shift - 2284904863U, // SQSHRUNv4i32_shift - 137945503U, // SQSHRUNv8i16_shift - 2218831699U, // SQSHRUNv8i8_shift - 167782084U, // SQSUB_ZI_B - 201344708U, // SQSUB_ZI_D - 239625924U, // SQSUB_ZI_H - 268469956U, // SQSUB_ZI_S - 167782084U, // SQSUB_ZZZ_B - 201344708U, // SQSUB_ZZZ_D - 2387109572U, // SQSUB_ZZZ_H - 268469956U, // SQSUB_ZZZ_S - 68200132U, // SQSUBv16i8 - 100714180U, // SQSUBv1i16 - 100714180U, // SQSUBv1i32 - 100714180U, // SQSUBv1i64 - 100714180U, // SQSUBv1i8 - 2216208068U, // SQSUBv2i32 - 2216732356U, // SQSUBv2i64 - 69772996U, // SQSUBv4i16 - 70297284U, // SQSUBv4i32 - 2218305220U, // SQSUBv8i16 - 2218829508U, // SQSUBv8i8 - 135324047U, // SQXTNv16i8 - 2248200005U, // SQXTNv1i16 - 2248200005U, // SQXTNv1i32 - 2248200005U, // SQXTNv1i8 - 2216210245U, // SQXTNv2i32 - 2217258821U, // SQXTNv4i16 - 2284904847U, // SQXTNv4i32 - 2285429135U, // SQXTNv8i16 - 71348037U, // SQXTNv8i8 - 135324084U, // SQXTUNv16i8 - 2248200038U, // SQXTUNv1i16 - 2248200038U, // SQXTUNv1i32 - 2248200038U, // SQXTUNv1i8 - 2216210278U, // SQXTUNv2i32 - 2217258854U, // SQXTUNv4i16 - 2284904884U, // SQXTUNv4i32 - 2285429172U, // SQXTUNv8i16 - 71348070U, // SQXTUNv8i8 - 68200433U, // SRHADDv16i8 - 2216208369U, // SRHADDv2i32 - 69773297U, // SRHADDv4i16 - 70297585U, // SRHADDv4i32 - 2218305521U, // SRHADDv8i16 - 2218829809U, // SRHADDv8i8 - 369192068U, // SRId - 135326852U, // SRIv16i8_shift - 2283334788U, // SRIv2i32_shift - 2283859076U, // SRIv2i64_shift - 136899716U, // SRIv4i16_shift - 137424004U, // SRIv4i32_shift - 2285431940U, // SRIv8i16_shift - 2285956228U, // SRIv8i8_shift - 68201901U, // SRSHLv16i8 - 100715949U, // SRSHLv1i64 - 2216209837U, // SRSHLv2i32 - 2216734125U, // SRSHLv2i64 - 69774765U, // SRSHLv4i16 - 70299053U, // SRSHLv4i32 - 2218306989U, // SRSHLv8i16 - 2218831277U, // SRSHLv8i8 - 100716794U, // SRSHRd - 68202746U, // SRSHRv16i8_shift - 2216210682U, // SRSHRv2i32_shift - 2216734970U, // SRSHRv2i64_shift - 69775610U, // SRSHRv4i16_shift - 70299898U, // SRSHRv4i32_shift - 2218307834U, // SRSHRv8i16_shift - 2218832122U, // SRSHRv8i8_shift - 369189634U, // SRSRAd - 135324418U, // SRSRAv16i8_shift - 2283332354U, // SRSRAv2i32_shift - 2283856642U, // SRSRAv2i64_shift - 136897282U, // SRSRAv4i16_shift - 137421570U, // SRSRAv4i32_shift - 2285429506U, // SRSRAv8i16_shift - 2285953794U, // SRSRAv8i8_shift - 70820085U, // SSHLLv16i8_shift - 2216734151U, // SSHLLv2i32_shift - 70299079U, // SSHLLv4i16_shift - 69247221U, // SSHLLv4i32_shift - 2217779445U, // SSHLLv8i16_shift - 2218307015U, // SSHLLv8i8_shift - 68201915U, // SSHLv16i8 - 100715963U, // SSHLv1i64 - 2216209851U, // SSHLv2i32 - 2216734139U, // SSHLv2i64 - 69774779U, // SSHLv4i16 - 70299067U, // SSHLv4i32 - 2218307003U, // SSHLv8i16 - 2218831291U, // SSHLv8i8 - 100716808U, // SSHRd - 68202760U, // SSHRv16i8_shift - 2216210696U, // SSHRv2i32_shift - 2216734984U, // SSHRv2i64_shift - 69775624U, // SSHRv4i16_shift - 70299912U, // SSHRv4i32_shift - 2218307848U, // SSHRv8i16_shift - 2218832136U, // SSHRv8i8_shift - 369189648U, // SSRAd - 135324432U, // SSRAv16i8_shift - 2283332368U, // SSRAv2i32_shift - 2283856656U, // SSRAv2i64_shift - 136897296U, // SSRAv4i16_shift - 137421584U, // SSRAv4i32_shift - 2285429520U, // SSRAv8i16_shift - 2285953808U, // SSRAv8i8_shift - 374997906U, // SST1B_D - 878314386U, // SST1B_D_IMM - 374997906U, // SST1B_D_SXTW - 374997906U, // SST1B_D_UXTW - 811213714U, // SST1B_S_IMM - 375006098U, // SST1B_S_SXTW - 375006098U, // SST1B_S_UXTW - 374998886U, // SST1D - 878315366U, // SST1D_IMM - 374998886U, // SST1D_SCALED - 374998886U, // SST1D_SXTW - 374998886U, // SST1D_SXTW_SCALED - 374998886U, // SST1D_UXTW - 374998886U, // SST1D_UXTW_SCALED - 374999380U, // SST1H_D - 3025799508U, // SST1H_D_IMM - 374999380U, // SST1H_D_SCALED - 374999380U, // SST1H_D_SXTW - 374999380U, // SST1H_D_SXTW_SCALED - 374999380U, // SST1H_D_UXTW - 374999380U, // SST1H_D_UXTW_SCALED - 2958698836U, // SST1H_S_IMM - 375007572U, // SST1H_S_SXTW - 375007572U, // SST1H_S_SXTW_SCALED - 375007572U, // SST1H_S_UXTW - 375007572U, // SST1H_S_UXTW_SCALED - 375002204U, // SST1W_D - 878318684U, // SST1W_D_IMM - 375002204U, // SST1W_D_SCALED - 375002204U, // SST1W_D_SXTW - 375002204U, // SST1W_D_SXTW_SCALED - 375002204U, // SST1W_D_UXTW - 375002204U, // SST1W_D_UXTW_SCALED - 811218012U, // SST1W_IMM - 375010396U, // SST1W_SXTW - 375010396U, // SST1W_SXTW_SCALED - 375010396U, // SST1W_UXTW - 375010396U, // SST1W_UXTW_SCALED - 70820037U, // SSUBLv16i8_v8i16 - 2216734014U, // SSUBLv2i32_v2i64 - 70298942U, // SSUBLv4i16_v4i32 - 69247173U, // SSUBLv4i32_v2i64 - 2217779397U, // SSUBLv8i16_v4i32 - 2218306878U, // SSUBLv8i8_v8i16 - 2218303966U, // SSUBWv16i8_v8i16 - 2216735886U, // SSUBWv2i32_v2i64 - 70300814U, // SSUBWv4i16_v4i32 - 2216731102U, // SSUBWv4i32_v2i64 - 70296030U, // SSUBWv8i16_v4i32 - 2218308750U, // SSUBWv8i8_v8i16 - 375022482U, // ST1B - 374997906U, // ST1B_D - 374997906U, // ST1B_D_IMM - 375030674U, // ST1B_H - 375030674U, // ST1B_H_IMM - 375022482U, // ST1B_IMM - 375006098U, // ST1B_S - 375006098U, // ST1B_S_IMM - 374998886U, // ST1D - 374998886U, // ST1D_IMM - 172102U, // ST1Fourv16b - 13287494U, // ST1Fourv16b_POST - 188486U, // ST1Fourv1d - 13828166U, // ST1Fourv1d_POST - 204870U, // ST1Fourv2d - 13320262U, // ST1Fourv2d_POST - 221254U, // ST1Fourv2s - 13860934U, // ST1Fourv2s_POST - 237638U, // ST1Fourv4h - 13877318U, // ST1Fourv4h_POST - 254022U, // ST1Fourv4s - 13369414U, // ST1Fourv4s_POST - 270406U, // ST1Fourv8b - 13910086U, // ST1Fourv8b_POST - 286790U, // ST1Fourv8h - 13402182U, // ST1Fourv8h_POST - 375032148U, // ST1H - 374999380U, // ST1H_D - 374999380U, // ST1H_D_IMM - 375032148U, // ST1H_IMM - 375007572U, // ST1H_S - 375007572U, // ST1H_S_IMM - 172102U, // ST1Onev16b - 14336070U, // ST1Onev16b_POST - 188486U, // ST1Onev1d - 14876742U, // ST1Onev1d_POST - 204870U, // ST1Onev2d - 14368838U, // ST1Onev2d_POST - 221254U, // ST1Onev2s - 14909510U, // ST1Onev2s_POST - 237638U, // ST1Onev4h - 14925894U, // ST1Onev4h_POST - 254022U, // ST1Onev4s - 14417990U, // ST1Onev4s_POST - 270406U, // ST1Onev8b - 14958662U, // ST1Onev8b_POST - 286790U, // ST1Onev8h - 14450758U, // ST1Onev8h_POST - 172102U, // ST1Threev16b - 16957510U, // ST1Threev16b_POST - 188486U, // ST1Threev1d - 17498182U, // ST1Threev1d_POST - 204870U, // ST1Threev2d - 16990278U, // ST1Threev2d_POST - 221254U, // ST1Threev2s - 17530950U, // ST1Threev2s_POST - 237638U, // ST1Threev4h - 17547334U, // ST1Threev4h_POST - 254022U, // ST1Threev4s - 17039430U, // ST1Threev4s_POST - 270406U, // ST1Threev8b - 17580102U, // ST1Threev8b_POST - 286790U, // ST1Threev8h - 17072198U, // ST1Threev8h_POST - 172102U, // ST1Twov16b - 13811782U, // ST1Twov16b_POST - 188486U, // ST1Twov1d - 14352454U, // ST1Twov1d_POST - 204870U, // ST1Twov2d - 13844550U, // ST1Twov2d_POST - 221254U, // ST1Twov2s - 14385222U, // ST1Twov2s_POST - 237638U, // ST1Twov4h - 14401606U, // ST1Twov4h_POST - 254022U, // ST1Twov4s - 13893702U, // ST1Twov4s_POST - 270406U, // ST1Twov8b - 14434374U, // ST1Twov8b_POST - 286790U, // ST1Twov8h - 13926470U, // ST1Twov8h_POST - 375010396U, // ST1W - 375002204U, // ST1W_D - 375002204U, // ST1W_D_IMM - 375010396U, // ST1W_IMM - 409670U, // ST1i16 - 1404346438U, // ST1i16_POST - 417862U, // ST1i32 - 1437917254U, // ST1i32_POST - 426054U, // ST1i64 - 1471488070U, // ST1i64_POST - 434246U, // ST1i8 - 1505058886U, // ST1i8_POST - 375022511U, // ST2B - 375022511U, // ST2B_IMM - 374998898U, // ST2D - 374998898U, // ST2D_IMM - 375032177U, // ST2H - 375032177U, // ST2H_IMM - 172505U, // ST2Twov16b - 13812185U, // ST2Twov16b_POST - 205273U, // ST2Twov2d - 13844953U, // ST2Twov2d_POST - 221657U, // ST2Twov2s - 14385625U, // ST2Twov2s_POST - 238041U, // ST2Twov4h - 14402009U, // ST2Twov4h_POST - 254425U, // ST2Twov4s - 13894105U, // ST2Twov4s_POST - 270809U, // ST2Twov8b - 14434777U, // ST2Twov8b_POST - 287193U, // ST2Twov8h - 13926873U, // ST2Twov8h_POST - 375010416U, // ST2W - 375010416U, // ST2W_IMM - 410073U, // ST2i16 - 1437901273U, // ST2i16_POST - 418265U, // ST2i32 - 1471472089U, // ST2i32_POST - 426457U, // ST2i64 - 1538597337U, // ST2i64_POST - 434649U, // ST2i8 - 1404395993U, // ST2i8_POST - 375022532U, // ST3B - 375022532U, // ST3B_IMM - 374998910U, // ST3D - 374998910U, // ST3D_IMM - 375032189U, // ST3H - 375032189U, // ST3H_IMM - 172571U, // ST3Threev16b - 16957979U, // ST3Threev16b_POST - 205339U, // ST3Threev2d - 16990747U, // ST3Threev2d_POST - 221723U, // ST3Threev2s - 17531419U, // ST3Threev2s_POST - 238107U, // ST3Threev4h - 17547803U, // ST3Threev4h_POST - 254491U, // ST3Threev4s - 17039899U, // ST3Threev4s_POST - 270875U, // ST3Threev8b - 17580571U, // ST3Threev8b_POST - 287259U, // ST3Threev8h - 17072667U, // ST3Threev8h_POST - 375010428U, // ST3W - 375010428U, // ST3W_IMM - 410139U, // ST3i16 - 1572119067U, // ST3i16_POST - 418331U, // ST3i32 - 1605689883U, // ST3i32_POST - 426523U, // ST3i64 - 1639260699U, // ST3i64_POST - 434715U, // ST3i8 - 1672831515U, // ST3i8_POST - 375022544U, // ST4B - 375022544U, // ST4B_IMM - 374998922U, // ST4D - 374998922U, // ST4D_IMM - 172588U, // ST4Fourv16b - 13287980U, // ST4Fourv16b_POST - 205356U, // ST4Fourv2d - 13320748U, // ST4Fourv2d_POST - 221740U, // ST4Fourv2s - 13861420U, // ST4Fourv2s_POST - 238124U, // ST4Fourv4h - 13877804U, // ST4Fourv4h_POST - 254508U, // ST4Fourv4s - 13369900U, // ST4Fourv4s_POST - 270892U, // ST4Fourv8b - 13910572U, // ST4Fourv8b_POST - 287276U, // ST4Fourv8h - 13402668U, // ST4Fourv8h_POST - 375032201U, // ST4H - 375032201U, // ST4H_IMM - 375010440U, // ST4W - 375010440U, // ST4W_IMM - 410156U, // ST4i16 - 1471455788U, // ST4i16_POST - 418348U, // ST4i32 - 1538581036U, // ST4i32_POST - 426540U, // ST4i64 - 1706369580U, // ST4i64_POST - 434732U, // ST4i8 - 1437950508U, // ST4i8_POST - 2253964715U, // STLLRB - 2253966166U, // STLLRH - 2253967648U, // STLLRW - 2253967648U, // STLLRX - 2253964723U, // STLRB - 2253966174U, // STLRH - 2253967661U, // STLRW - 2253967661U, // STLRX - 106481125U, // STLURBi - 106482576U, // STLURHi - 106484110U, // STLURWi - 106484110U, // STLURXi - 100716685U, // STLXPW - 100716685U, // STLXPX - 2248197644U, // STLXRB - 2248199095U, // STLXRH - 2248200645U, // STLXRW - 2248200645U, // STLXRX - 2248200251U, // STNPDi - 2248200251U, // STNPQi - 2248200251U, // STNPSi - 2248200251U, // STNPWi - 2248200251U, // STNPXi - 375022474U, // STNT1B_ZRI - 375022474U, // STNT1B_ZRR - 374998878U, // STNT1D_ZRI - 374998878U, // STNT1D_ZRR - 375032140U, // STNT1H_ZRI - 375032140U, // STNT1H_ZRR - 375010388U, // STNT1W_ZRI - 375010388U, // STNT1W_ZRR - 2248200283U, // STPDi - 2516676699U, // STPDpost - 2516676699U, // STPDpre - 2248200283U, // STPQi - 2516676699U, // STPQpost - 2516676699U, // STPQpre - 2248200283U, // STPSi - 2516676699U, // STPSpost - 2516676699U, // STPSpre - 2248200283U, // STPWi - 2516676699U, // STPWpost - 2516676699U, // STPWpre - 2248200283U, // STPXi - 2516676699U, // STPXpost - 2516676699U, // STPXpre - 374957521U, // STRBBpost - 374957521U, // STRBBpre - 106481105U, // STRBBroW - 106481105U, // STRBBroX - 106481105U, // STRBBui - 374960503U, // STRBpost - 374960503U, // STRBpre - 106484087U, // STRBroW - 106484087U, // STRBroX - 106484087U, // STRBui - 374960503U, // STRDpost - 374960503U, // STRDpre - 106484087U, // STRDroW - 106484087U, // STRDroX - 106484087U, // STRDui - 374958972U, // STRHHpost - 374958972U, // STRHHpre - 106482556U, // STRHHroW - 106482556U, // STRHHroX - 106482556U, // STRHHui - 374960503U, // STRHpost - 374960503U, // STRHpre - 106484087U, // STRHroW - 106484087U, // STRHroX - 106484087U, // STRHui - 374960503U, // STRQpost - 374960503U, // STRQpre - 106484087U, // STRQroW - 106484087U, // STRQroX - 106484087U, // STRQui - 374960503U, // STRSpost - 374960503U, // STRSpre - 106484087U, // STRSroW - 106484087U, // STRSroX - 106484087U, // STRSui - 374960503U, // STRWpost - 374960503U, // STRWpre - 106484087U, // STRWroW - 106484087U, // STRWroX - 106484087U, // STRWui - 374960503U, // STRXpost - 374960503U, // STRXpre - 106484087U, // STRXroW - 106484087U, // STRXroX - 106484087U, // STRXui - 106803575U, // STR_PXI - 106803575U, // STR_ZXI - 106481111U, // STTRBi - 106482562U, // STTRHi - 106484092U, // STTRWi - 106484092U, // STTRXi - 106481142U, // STURBBi - 106484125U, // STURBi - 106484125U, // STURDi - 106482593U, // STURHHi - 106484125U, // STURHi - 106484125U, // STURQi - 106484125U, // STURSi - 106484125U, // STURWi - 106484125U, // STURXi - 100716692U, // STXPW - 100716692U, // STXPX - 2248197652U, // STXRB - 2248199103U, // STXRH - 2248200652U, // STXRW - 2248200652U, // STXRX - 2216210137U, // SUBHNv2i64_v2i32 - 2284904778U, // SUBHNv2i64_v4i32 - 69775065U, // SUBHNv4i32_v4i16 - 137945418U, // SUBHNv4i32_v8i16 - 2282807626U, // SUBHNv8i16_v16i8 - 2218831577U, // SUBHNv8i16_v8i8 - 167784668U, // SUBR_ZI_B - 201347292U, // SUBR_ZI_D - 239628508U, // SUBR_ZI_H - 268472540U, // SUBR_ZI_S - 302002396U, // SUBR_ZPmZ_B - 302010588U, // SUBR_ZPmZ_D - 2186309852U, // SUBR_ZPmZ_H - 302026972U, // SUBR_ZPmZ_S - 100717066U, // SUBSWri - 0U, // SUBSWrr - 100717066U, // SUBSWrs - 100717066U, // SUBSWrx - 100717066U, // SUBSXri - 0U, // SUBSXrr - 100717066U, // SUBSXrs - 100717066U, // SUBSXrx - 100717066U, // SUBSXrx64 - 100714146U, // SUBWri - 0U, // SUBWrr - 100714146U, // SUBWrs - 100714146U, // SUBWrx - 100714146U, // SUBXri - 0U, // SUBXrr - 100714146U, // SUBXrs - 100714146U, // SUBXrx - 100714146U, // SUBXrx64 - 167782050U, // SUB_ZI_B - 201344674U, // SUB_ZI_D - 239625890U, // SUB_ZI_H - 268469922U, // SUB_ZI_S - 301999778U, // SUB_ZPmZ_B - 302007970U, // SUB_ZPmZ_D - 2186307234U, // SUB_ZPmZ_H - 302024354U, // SUB_ZPmZ_S - 167782050U, // SUB_ZZZ_B - 201344674U, // SUB_ZZZ_D - 2387109538U, // SUB_ZZZ_H - 268469922U, // SUB_ZZZ_S - 68200098U, // SUBv16i8 - 100714146U, // SUBv1i64 - 2216208034U, // SUBv2i32 - 2216732322U, // SUBv2i64 - 69772962U, // SUBv4i16 - 70297250U, // SUBv4i32 - 2218305186U, // SUBv8i16 - 2218829474U, // SUBv8i8 - 2415938650U, // SUNPKHI_ZZ_D - 27290714U, // SUNPKHI_ZZ_H - 2717944922U, // SUNPKHI_ZZ_S - 2415939470U, // SUNPKLO_ZZ_D - 27291534U, // SUNPKLO_ZZ_H - 2717945742U, // SUNPKLO_ZZ_S - 135325734U, // SUQADDv16i8 - 2516674598U, // SUQADDv1i16 - 2516674598U, // SUQADDv1i32 - 2516674598U, // SUQADDv1i64 - 2516674598U, // SUQADDv1i8 - 135850022U, // SUQADDv2i32 - 2283857958U, // SUQADDv2i64 - 136898598U, // SUQADDv4i16 - 2284906534U, // SUQADDv4i32 - 137947174U, // SUQADDv8i16 - 2285955110U, // SUQADDv8i8 - 75579U, // SVC - 973169651U, // SWPAB - 973171135U, // SWPAH - 973169853U, // SWPALB - 973171283U, // SWPALH - 973171948U, // SWPALW - 973171948U, // SWPALX - 973169381U, // SWPAW - 973169381U, // SWPAX - 973170041U, // SWPB - 973171492U, // SWPH - 973169950U, // SWPLB - 973171380U, // SWPLH - 973172243U, // SWPLW - 973172243U, // SWPLX - 973172838U, // SWPW - 973172838U, // SWPX - 18069U, // SXTB_ZPmZ_D - 2181588629U, // SXTB_ZPmZ_H - 34453U, // SXTB_ZPmZ_S - 19494U, // SXTH_ZPmZ_D - 35878U, // SXTH_ZPmZ_S - 21815U, // SXTW_ZPmZ_D - 100716107U, // SYSLxt - 1711329984U, // SYSxt - 1744842025U, // TBL_ZZZ_B - 1778404649U, // TBL_ZZZ_D - 28863785U, // TBL_ZZZ_H - 1811975465U, // TBL_ZZZ_S - 1846586665U, // TBLv16i8Four - 1846586665U, // TBLv16i8One - 1846586665U, // TBLv16i8Three - 1846586665U, // TBLv16i8Two - 3997216041U, // TBLv8i8Four - 3997216041U, // TBLv8i8One - 3997216041U, // TBLv8i8Three - 3997216041U, // TBLv8i8Two - 100718059U, // TBNZW - 100718059U, // TBNZX - 1880159597U, // TBXv16i8Four - 1880159597U, // TBXv16i8One - 1880159597U, // TBXv16i8Three - 1880159597U, // TBXv16i8Two - 4030788973U, // TBXv8i8Four - 4030788973U, // TBXv8i8One - 4030788973U, // TBXv8i8Three - 4030788973U, // TBXv8i8Two - 100718043U, // TBZW - 100718043U, // TBZX - 0U, // TCRETURNdi - 0U, // TCRETURNri - 6346239U, // TLSDESCCALL - 0U, // TLSDESC_CALLSEQ - 167780389U, // TRN1_PPP_B - 201343013U, // TRN1_PPP_D - 2387107877U, // TRN1_PPP_H - 268468261U, // TRN1_PPP_S - 167780389U, // TRN1_ZZZ_B - 201343013U, // TRN1_ZZZ_D - 2387107877U, // TRN1_ZZZ_H - 268468261U, // TRN1_ZZZ_S - 68198437U, // TRN1v16i8 - 2216206373U, // TRN1v2i32 - 2216730661U, // TRN1v2i64 - 69771301U, // TRN1v4i16 - 70295589U, // TRN1v4i32 - 2218303525U, // TRN1v8i16 - 2218827813U, // TRN1v8i8 - 167780737U, // TRN2_PPP_B - 201343361U, // TRN2_PPP_D - 2387108225U, // TRN2_PPP_H - 268468609U, // TRN2_PPP_S - 167780737U, // TRN2_ZZZ_B - 201343361U, // TRN2_ZZZ_D - 2387108225U, // TRN2_ZZZ_H - 268468609U, // TRN2_ZZZ_S - 68198785U, // TRN2v16i8 - 2216206721U, // TRN2v2i32 - 2216731009U, // TRN2v2i64 - 69771649U, // TRN2v4i16 - 70295937U, // TRN2v4i32 - 2218303873U, // TRN2v8i16 - 2218828161U, // TRN2v8i8 - 116346U, // TSB - 137945251U, // UABALv16i8_v8i16 - 2283859113U, // UABALv2i32_v2i64 - 137424041U, // UABALv4i16_v4i32 - 136372387U, // UABALv4i32_v2i64 - 2284904611U, // UABALv8i16_v4i32 - 2285431977U, // UABALv8i8_v8i16 - 135324275U, // UABAv16i8 - 2283332211U, // UABAv2i32 - 136897139U, // UABAv4i16 - 137421427U, // UABAv4i32 - 2285429363U, // UABAv8i16 - 2285953651U, // UABAv8i8 - 70820061U, // UABDLv16i8_v8i16 - 2216734035U, // UABDLv2i32_v2i64 - 70298963U, // UABDLv4i16_v4i32 - 69247197U, // UABDLv4i32_v2i64 - 2217779421U, // UABDLv8i16_v4i32 - 2218306899U, // UABDLv8i8_v8i16 - 302000048U, // UABD_ZPmZ_B - 302008240U, // UABD_ZPmZ_D - 2186307504U, // UABD_ZPmZ_H - 302024624U, // UABD_ZPmZ_S - 68200368U, // UABDv16i8 - 2216208304U, // UABDv2i32 - 69773232U, // UABDv4i16 - 70297520U, // UABDv4i32 - 2218305456U, // UABDv8i16 - 2218829744U, // UABDv8i8 - 137949161U, // UADALPv16i8_v8i16 - 162066409U, // UADALPv2i32_v1i64 - 135852009U, // UADALPv4i16_v2i32 - 2283859945U, // UADALPv4i32_v2i64 - 137424873U, // UADALPv8i16_v4i32 - 2284384233U, // UADALPv8i8_v4i16 - 70823929U, // UADDLPv16i8_v8i16 - 94941177U, // UADDLPv2i32_v1i64 - 68726777U, // UADDLPv4i16_v2i32 - 2216734713U, // UADDLPv4i32_v2i64 - 70299641U, // UADDLPv8i16_v4i32 - 2217259001U, // UADDLPv8i8_v4i16 - 67163091U, // UADDLVv16i8v - 67163091U, // UADDLVv4i16v - 2214646739U, // UADDLVv4i32v - 67163091U, // UADDLVv8i16v - 2214646739U, // UADDLVv8i8v - 70820077U, // UADDLv16i8_v8i16 - 2216734073U, // UADDLv2i32_v2i64 - 70299001U, // UADDLv4i16_v4i32 - 69247213U, // UADDLv4i32_v2i64 - 2217779437U, // UADDLv8i16_v4i32 - 2218306937U, // UADDLv8i8_v8i16 - 302044071U, // UADDV_VPZ_B - 302044071U, // UADDV_VPZ_D - 302044071U, // UADDV_VPZ_H - 302044071U, // UADDV_VPZ_S - 2218303990U, // UADDWv16i8_v8i16 - 2216735948U, // UADDWv2i32_v2i64 - 70300876U, // UADDWv4i16_v4i32 - 2216731126U, // UADDWv4i32_v2i64 - 70296054U, // UADDWv8i16_v4i32 - 2218308812U, // UADDWv8i8_v8i16 - 100716199U, // UBFMWri - 100716199U, // UBFMXri - 100714764U, // UCVTFSWDri - 100714764U, // UCVTFSWHri - 100714764U, // UCVTFSWSri - 100714764U, // UCVTFSXDri - 100714764U, // UCVTFSXHri - 100714764U, // UCVTFSXSri - 2248198412U, // UCVTFUWDri - 2248198412U, // UCVTFUWHri - 2248198412U, // UCVTFUWSri - 2248198412U, // UCVTFUXDri - 2248198412U, // UCVTFUXHri - 2248198412U, // UCVTFUXSri - 18700U, // UCVTF_ZPmZ_DtoD - 2181589260U, // UCVTF_ZPmZ_DtoH - 35084U, // UCVTF_ZPmZ_DtoS - 2181589260U, // UCVTF_ZPmZ_HtoH - 18700U, // UCVTF_ZPmZ_StoD - 2181589260U, // UCVTF_ZPmZ_StoH - 35084U, // UCVTF_ZPmZ_StoS - 100714764U, // UCVTFd - 100714764U, // UCVTFh - 100714764U, // UCVTFs - 2248198412U, // UCVTFv1i16 - 2248198412U, // UCVTFv1i32 - 2248198412U, // UCVTFv1i64 - 68725004U, // UCVTFv2f32 - 2216732940U, // UCVTFv2f64 - 2216208652U, // UCVTFv2i32_shift - 2216732940U, // UCVTFv2i64_shift - 69773580U, // UCVTFv4f16 - 2217781516U, // UCVTFv4f32 - 69773580U, // UCVTFv4i16_shift - 70297868U, // UCVTFv4i32_shift - 70822156U, // UCVTFv8f16 - 2218305804U, // UCVTFv8i16_shift - 302010801U, // UDIVR_ZPmZ_D - 302027185U, // UDIVR_ZPmZ_S - 100717509U, // UDIVWr - 100717509U, // UDIVXr - 302011333U, // UDIV_ZPmZ_D - 302027717U, // UDIV_ZPmZ_S - 3422573363U, // UDOT_ZZZI_D - 3456144179U, // UDOT_ZZZI_S - 3422573363U, // UDOT_ZZZ_D - 3456144179U, // UDOT_ZZZ_S - 137425715U, // UDOTlanev16i8 - 2283336499U, // UDOTlanev8i8 - 137425715U, // UDOTv16i8 - 2283336499U, // UDOTv8i8 - 68200456U, // UHADDv16i8 - 2216208392U, // UHADDv2i32 - 69773320U, // UHADDv4i16 - 70297608U, // UHADDv4i32 - 2218305544U, // UHADDv8i16 - 2218829832U, // UHADDv8i8 - 68200110U, // UHSUBv16i8 - 2216208046U, // UHSUBv2i32 - 69772974U, // UHSUBv4i16 - 70297262U, // UHSUBv4i32 - 2218305198U, // UHSUBv8i16 - 2218829486U, // UHSUBv8i8 - 100715882U, // UMADDLrrr - 68202624U, // UMAXPv16i8 - 2216210560U, // UMAXPv2i32 - 69775488U, // UMAXPv4i16 - 70299776U, // UMAXPv4i32 - 2218307712U, // UMAXPv8i16 - 2218832000U, // UMAXPv8i8 - 302044207U, // UMAXV_VPZ_B - 302044207U, // UMAXV_VPZ_D - 302044207U, // UMAXV_VPZ_H - 302044207U, // UMAXV_VPZ_S - 67163183U, // UMAXVv16i8v - 67163183U, // UMAXVv4i16v - 2214646831U, // UMAXVv4i32v - 67163183U, // UMAXVv8i16v - 2214646831U, // UMAXVv8i8v - 167785831U, // UMAX_ZI_B - 201348455U, // UMAX_ZI_D - 239629671U, // UMAX_ZI_H - 268473703U, // UMAX_ZI_S - 302003559U, // UMAX_ZPmZ_B - 302011751U, // UMAX_ZPmZ_D - 2186311015U, // UMAX_ZPmZ_H - 302028135U, // UMAX_ZPmZ_S - 68203879U, // UMAXv16i8 - 2216211815U, // UMAXv2i32 - 69776743U, // UMAXv4i16 - 70301031U, // UMAXv4i32 - 2218308967U, // UMAXv8i16 - 2218833255U, // UMAXv8i8 - 68202548U, // UMINPv16i8 - 2216210484U, // UMINPv2i32 - 69775412U, // UMINPv4i16 - 70299700U, // UMINPv4i32 - 2218307636U, // UMINPv8i16 - 2218831924U, // UMINPv8i8 - 302044155U, // UMINV_VPZ_B - 302044155U, // UMINV_VPZ_D - 302044155U, // UMINV_VPZ_H - 302044155U, // UMINV_VPZ_S - 67163131U, // UMINVv16i8v - 67163131U, // UMINVv4i16v - 2214646779U, // UMINVv4i32v - 67163131U, // UMINVv8i16v - 2214646779U, // UMINVv8i8v - 167784184U, // UMIN_ZI_B - 201346808U, // UMIN_ZI_D - 239628024U, // UMIN_ZI_H - 268472056U, // UMIN_ZI_S - 302001912U, // UMIN_ZPmZ_B - 302010104U, // UMIN_ZPmZ_D - 2186309368U, // UMIN_ZPmZ_H - 302026488U, // UMIN_ZPmZ_S - 68202232U, // UMINv16i8 - 2216210168U, // UMINv2i32 - 69775096U, // UMINv4i16 - 70299384U, // UMINv4i32 - 2218307320U, // UMINv8i16 - 2218831608U, // UMINv8i8 - 137945277U, // UMLALv16i8_v8i16 - 2283859145U, // UMLALv2i32_indexed - 2283859145U, // UMLALv2i32_v2i64 - 137424073U, // UMLALv4i16_indexed - 137424073U, // UMLALv4i16_v4i32 - 136372413U, // UMLALv4i32_indexed - 136372413U, // UMLALv4i32_v2i64 - 2284904637U, // UMLALv8i16_indexed - 2284904637U, // UMLALv8i16_v4i32 - 2285432009U, // UMLALv8i8_v8i16 - 137945401U, // UMLSLv16i8_v8i16 - 2283859524U, // UMLSLv2i32_indexed - 2283859524U, // UMLSLv2i32_v2i64 - 137424452U, // UMLSLv4i16_indexed - 137424452U, // UMLSLv4i16_v4i32 - 136372537U, // UMLSLv4i32_indexed - 136372537U, // UMLSLv4i32_v2i64 - 2284904761U, // UMLSLv8i16_indexed - 2284904761U, // UMLSLv8i16_v4i32 - 2285432388U, // UMLSLv8i8_v8i16 - 67163157U, // UMOVvi16 - 2214646805U, // UMOVvi32 - 67163157U, // UMOVvi64 - 2214646805U, // UMOVvi8 - 100715830U, // UMSUBLrrr - 302000887U, // UMULH_ZPmZ_B - 302009079U, // UMULH_ZPmZ_D - 2186308343U, // UMULH_ZPmZ_H - 302025463U, // UMULH_ZPmZ_S - 100715255U, // UMULHrr - 70820127U, // UMULLv16i8_v8i16 - 2216734188U, // UMULLv2i32_indexed - 2216734188U, // UMULLv2i32_v2i64 - 70299116U, // UMULLv4i16_indexed - 70299116U, // UMULLv4i16_v4i32 - 69247263U, // UMULLv4i32_indexed - 69247263U, // UMULLv4i32_v2i64 - 2217779487U, // UMULLv8i16_indexed - 2217779487U, // UMULLv8i16_v4i32 - 2218307052U, // UMULLv8i8_v8i16 - 167782439U, // UQADD_ZI_B - 201345063U, // UQADD_ZI_D - 239626279U, // UQADD_ZI_H - 268470311U, // UQADD_ZI_S - 167782439U, // UQADD_ZZZ_B - 201345063U, // UQADD_ZZZ_D - 2387109927U, // UQADD_ZZZ_H - 268470311U, // UQADD_ZZZ_S - 68200487U, // UQADDv16i8 - 100714535U, // UQADDv1i16 - 100714535U, // UQADDv1i32 - 100714535U, // UQADDv1i64 - 100714535U, // UQADDv1i8 - 2216208423U, // UQADDv2i32 - 2216732711U, // UQADDv2i64 - 69773351U, // UQADDv4i16 - 70297639U, // UQADDv4i32 - 2218305575U, // UQADDv8i16 - 2218829863U, // UQADDv8i8 - 536921173U, // UQDECB_WPiI - 536921173U, // UQDECB_XPiI - 536922053U, // UQDECD_WPiI - 536922053U, // UQDECD_XPiI - 536889285U, // UQDECD_ZPiI - 536922637U, // UQDECH_WPiI - 536922637U, // UQDECH_XPiI - 6842893U, // UQDECH_ZPiI - 2315308989U, // UQDECP_WP_B - 2348863421U, // UQDECP_WP_D - 2717962173U, // UQDECP_WP_H - 2415972285U, // UQDECP_WP_S - 2315308989U, // UQDECP_XP_B - 2348863421U, // UQDECP_XP_D - 2717962173U, // UQDECP_XP_H - 2415972285U, // UQDECP_XP_S - 2147504061U, // UQDECP_ZP_D - 604532669U, // UQDECP_ZP_H - 2147520445U, // UQDECP_ZP_S - 536925357U, // UQDECW_WPiI - 536925357U, // UQDECW_XPiI - 536908973U, // UQDECW_ZPiI - 536921189U, // UQINCB_WPiI - 536921189U, // UQINCB_XPiI - 536922069U, // UQINCD_WPiI - 536922069U, // UQINCD_XPiI - 536889301U, // UQINCD_ZPiI - 536922653U, // UQINCH_WPiI - 536922653U, // UQINCH_XPiI - 6842909U, // UQINCH_ZPiI - 2315309005U, // UQINCP_WP_B - 2348863437U, // UQINCP_WP_D - 2717962189U, // UQINCP_WP_H - 2415972301U, // UQINCP_WP_S - 2315309005U, // UQINCP_XP_B - 2348863437U, // UQINCP_XP_D - 2717962189U, // UQINCP_XP_H - 2415972301U, // UQINCP_XP_S - 2147504077U, // UQINCP_ZP_D - 604532685U, // UQINCP_ZP_H - 2147520461U, // UQINCP_ZP_S - 536925373U, // UQINCW_WPiI - 536925373U, // UQINCW_XPiI - 536908989U, // UQINCW_ZPiI - 68201893U, // UQRSHLv16i8 - 100715941U, // UQRSHLv1i16 - 100715941U, // UQRSHLv1i32 - 100715941U, // UQRSHLv1i64 - 100715941U, // UQRSHLv1i8 - 2216209829U, // UQRSHLv2i32 - 2216734117U, // UQRSHLv2i64 - 69774757U, // UQRSHLv4i16 - 70299045U, // UQRSHLv4i32 - 2218306981U, // UQRSHLv8i16 - 2218831269U, // UQRSHLv8i8 - 100716328U, // UQRSHRNb - 100716328U, // UQRSHRNh - 100716328U, // UQRSHRNs - 2282807671U, // UQRSHRNv16i8_shift - 2216210216U, // UQRSHRNv2i32_shift - 69775144U, // UQRSHRNv4i16_shift - 2284904823U, // UQRSHRNv4i32_shift - 137945463U, // UQRSHRNv8i16_shift - 2218831656U, // UQRSHRNv8i8_shift - 100715926U, // UQSHLb - 100715926U, // UQSHLd - 100715926U, // UQSHLh - 100715926U, // UQSHLs - 68201878U, // UQSHLv16i8 - 68201878U, // UQSHLv16i8_shift - 100715926U, // UQSHLv1i16 - 100715926U, // UQSHLv1i32 - 100715926U, // UQSHLv1i64 - 100715926U, // UQSHLv1i8 - 2216209814U, // UQSHLv2i32 - 2216209814U, // UQSHLv2i32_shift - 2216734102U, // UQSHLv2i64 - 2216734102U, // UQSHLv2i64_shift - 69774742U, // UQSHLv4i16 - 69774742U, // UQSHLv4i16_shift - 70299030U, // UQSHLv4i32 - 70299030U, // UQSHLv4i32_shift - 2218306966U, // UQSHLv8i16 - 2218306966U, // UQSHLv8i16_shift - 2218831254U, // UQSHLv8i8 - 2218831254U, // UQSHLv8i8_shift - 100716311U, // UQSHRNb - 100716311U, // UQSHRNh - 100716311U, // UQSHRNs - 2282807652U, // UQSHRNv16i8_shift - 2216210199U, // UQSHRNv2i32_shift - 69775127U, // UQSHRNv4i16_shift - 2284904804U, // UQSHRNv4i32_shift - 137945444U, // UQSHRNv8i16_shift - 2218831639U, // UQSHRNv8i8_shift - 167782091U, // UQSUB_ZI_B - 201344715U, // UQSUB_ZI_D - 239625931U, // UQSUB_ZI_H - 268469963U, // UQSUB_ZI_S - 167782091U, // UQSUB_ZZZ_B - 201344715U, // UQSUB_ZZZ_D - 2387109579U, // UQSUB_ZZZ_H - 268469963U, // UQSUB_ZZZ_S - 68200139U, // UQSUBv16i8 - 100714187U, // UQSUBv1i16 - 100714187U, // UQSUBv1i32 - 100714187U, // UQSUBv1i64 - 100714187U, // UQSUBv1i8 - 2216208075U, // UQSUBv2i32 - 2216732363U, // UQSUBv2i64 - 69773003U, // UQSUBv4i16 - 70297291U, // UQSUBv4i32 - 2218305227U, // UQSUBv8i16 - 2218829515U, // UQSUBv8i8 - 135324055U, // UQXTNv16i8 - 2248200012U, // UQXTNv1i16 - 2248200012U, // UQXTNv1i32 - 2248200012U, // UQXTNv1i8 - 2216210252U, // UQXTNv2i32 - 2217258828U, // UQXTNv4i16 - 2284904855U, // UQXTNv4i32 - 2285429143U, // UQXTNv8i16 - 71348044U, // UQXTNv8i8 - 68724924U, // URECPEv2i32 - 2217781436U, // URECPEv4i32 - 68200441U, // URHADDv16i8 - 2216208377U, // URHADDv2i32 - 69773305U, // URHADDv4i16 - 70297593U, // URHADDv4i32 - 2218305529U, // URHADDv8i16 - 2218829817U, // URHADDv8i8 - 68201908U, // URSHLv16i8 - 100715956U, // URSHLv1i64 - 2216209844U, // URSHLv2i32 - 2216734132U, // URSHLv2i64 - 69774772U, // URSHLv4i16 - 70299060U, // URSHLv4i32 - 2218306996U, // URSHLv8i16 - 2218831284U, // URSHLv8i8 - 100716801U, // URSHRd - 68202753U, // URSHRv16i8_shift - 2216210689U, // URSHRv2i32_shift - 2216734977U, // URSHRv2i64_shift - 69775617U, // URSHRv4i16_shift - 70299905U, // URSHRv4i32_shift - 2218307841U, // URSHRv8i16_shift - 2218832129U, // URSHRv8i8_shift - 68724970U, // URSQRTEv2i32 - 2217781482U, // URSQRTEv4i32 - 369189641U, // URSRAd - 135324425U, // URSRAv16i8_shift - 2283332361U, // URSRAv2i32_shift - 2283856649U, // URSRAv2i64_shift - 136897289U, // URSRAv4i16_shift - 137421577U, // URSRAv4i32_shift - 2285429513U, // URSRAv8i16_shift - 2285953801U, // URSRAv8i8_shift - 70820093U, // USHLLv16i8_shift - 2216734158U, // USHLLv2i32_shift - 70299086U, // USHLLv4i16_shift - 69247229U, // USHLLv4i32_shift - 2217779453U, // USHLLv8i16_shift - 2218307022U, // USHLLv8i8_shift - 68201921U, // USHLv16i8 - 100715969U, // USHLv1i64 - 2216209857U, // USHLv2i32 - 2216734145U, // USHLv2i64 - 69774785U, // USHLv4i16 - 70299073U, // USHLv4i32 - 2218307009U, // USHLv8i16 - 2218831297U, // USHLv8i8 - 100716814U, // USHRd - 68202766U, // USHRv16i8_shift - 2216210702U, // USHRv2i32_shift - 2216734990U, // USHRv2i64_shift - 69775630U, // USHRv4i16_shift - 70299918U, // USHRv4i32_shift - 2218307854U, // USHRv8i16_shift - 2218832142U, // USHRv8i8_shift - 135325726U, // USQADDv16i8 - 2516674590U, // USQADDv1i16 - 2516674590U, // USQADDv1i32 - 2516674590U, // USQADDv1i64 - 2516674590U, // USQADDv1i8 - 135850014U, // USQADDv2i32 - 2283857950U, // USQADDv2i64 - 136898590U, // USQADDv4i16 - 2284906526U, // USQADDv4i32 - 137947166U, // USQADDv8i16 - 2285955102U, // USQADDv8i8 - 369189654U, // USRAd - 135324438U, // USRAv16i8_shift - 2283332374U, // USRAv2i32_shift - 2283856662U, // USRAv2i64_shift - 136897302U, // USRAv4i16_shift - 137421590U, // USRAv4i32_shift - 2285429526U, // USRAv8i16_shift - 2285953814U, // USRAv8i8_shift - 70820045U, // USUBLv16i8_v8i16 - 2216734021U, // USUBLv2i32_v2i64 - 70298949U, // USUBLv4i16_v4i32 - 69247181U, // USUBLv4i32_v2i64 - 2217779405U, // USUBLv8i16_v4i32 - 2218306885U, // USUBLv8i8_v8i16 - 2218303974U, // USUBWv16i8_v8i16 - 2216735893U, // USUBWv2i32_v2i64 - 70300821U, // USUBWv4i16_v4i32 - 2216731110U, // USUBWv4i32_v2i64 - 70296038U, // USUBWv8i16_v4i32 - 2218308757U, // USUBWv8i8_v8i16 - 2415938659U, // UUNPKHI_ZZ_D - 27290723U, // UUNPKHI_ZZ_H - 2717944931U, // UUNPKHI_ZZ_S - 2415939479U, // UUNPKLO_ZZ_D - 27291543U, // UUNPKLO_ZZ_H - 2717945751U, // UUNPKLO_ZZ_S - 18075U, // UXTB_ZPmZ_D - 2181588635U, // UXTB_ZPmZ_H - 34459U, // UXTB_ZPmZ_S - 19500U, // UXTH_ZPmZ_D - 35884U, // UXTH_ZPmZ_S - 21821U, // UXTW_ZPmZ_D - 167780401U, // UZP1_PPP_B - 201343025U, // UZP1_PPP_D - 2387107889U, // UZP1_PPP_H - 268468273U, // UZP1_PPP_S - 167780401U, // UZP1_ZZZ_B - 201343025U, // UZP1_ZZZ_D - 2387107889U, // UZP1_ZZZ_H - 268468273U, // UZP1_ZZZ_S - 68198449U, // UZP1v16i8 - 2216206385U, // UZP1v2i32 - 2216730673U, // UZP1v2i64 - 69771313U, // UZP1v4i16 - 70295601U, // UZP1v4i32 - 2218303537U, // UZP1v8i16 - 2218827825U, // UZP1v8i8 - 167780812U, // UZP2_PPP_B - 201343436U, // UZP2_PPP_D - 2387108300U, // UZP2_PPP_H - 268468684U, // UZP2_PPP_S - 167780812U, // UZP2_ZZZ_B - 201343436U, // UZP2_ZZZ_D - 2387108300U, // UZP2_ZZZ_H - 268468684U, // UZP2_ZZZ_S - 68198860U, // UZP2v16i8 - 2216206796U, // UZP2v2i32 - 2216731084U, // UZP2v2i64 - 69771724U, // UZP2v4i16 - 70296012U, // UZP2v4i32 - 2218303948U, // UZP2v8i16 - 2218828236U, // UZP2v8i8 - 100673670U, // WHILELE_PWW_B - 100681862U, // WHILELE_PWW_D - 242772102U, // WHILELE_PWW_H - 100698246U, // WHILELE_PWW_S - 100673670U, // WHILELE_PXX_B - 100681862U, // WHILELE_PXX_D - 242772102U, // WHILELE_PXX_H - 100698246U, // WHILELE_PXX_S - 100675452U, // WHILELO_PWW_B - 100683644U, // WHILELO_PWW_D - 242773884U, // WHILELO_PWW_H - 100700028U, // WHILELO_PWW_S - 100675452U, // WHILELO_PXX_B - 100683644U, // WHILELO_PXX_D - 242773884U, // WHILELO_PXX_H - 100700028U, // WHILELO_PXX_S - 100676169U, // WHILELS_PWW_B - 100684361U, // WHILELS_PWW_D - 242774601U, // WHILELS_PWW_H - 100700745U, // WHILELS_PWW_S - 100676169U, // WHILELS_PXX_B - 100684361U, // WHILELS_PXX_D - 242774601U, // WHILELS_PXX_H - 100700745U, // WHILELS_PXX_S - 100676358U, // WHILELT_PWW_B - 100684550U, // WHILELT_PWW_D - 242774790U, // WHILELT_PWW_H - 100700934U, // WHILELT_PWW_S - 100676358U, // WHILELT_PXX_B - 100684550U, // WHILELT_PXX_D - 242774790U, // WHILELT_PXX_H - 100700934U, // WHILELT_PXX_S - 6303987U, // WRFFR - 2216734934U, // XAR - 6342582U, // XPACD - 6343754U, // XPACI - 5905U, // XPACLRI - 135324049U, // XTNv16i8 - 2216210247U, // XTNv2i32 - 2217258823U, // XTNv4i16 - 2284904849U, // XTNv4i32 - 2285429137U, // XTNv8i16 - 71348039U, // XTNv8i8 - 167780395U, // ZIP1_PPP_B - 201343019U, // ZIP1_PPP_D - 2387107883U, // ZIP1_PPP_H - 268468267U, // ZIP1_PPP_S - 167780395U, // ZIP1_ZZZ_B - 201343019U, // ZIP1_ZZZ_D - 2387107883U, // ZIP1_ZZZ_H - 268468267U, // ZIP1_ZZZ_S - 68198443U, // ZIP1v16i8 - 2216206379U, // ZIP1v2i32 - 2216730667U, // ZIP1v2i64 - 69771307U, // ZIP1v4i16 - 70295595U, // ZIP1v4i32 - 2218303531U, // ZIP1v8i16 - 2218827819U, // ZIP1v8i8 - 167780806U, // ZIP2_PPP_B - 201343430U, // ZIP2_PPP_D - 2387108294U, // ZIP2_PPP_H - 268468678U, // ZIP2_PPP_S - 167780806U, // ZIP2_ZZZ_B - 201343430U, // ZIP2_ZZZ_D - 2387108294U, // ZIP2_ZZZ_H - 268468678U, // ZIP2_ZZZ_S - 68198854U, // ZIP2v16i8 - 2216206790U, // ZIP2v2i32 - 2216731078U, // ZIP2v2i64 - 69771718U, // ZIP2v4i16 - 70296006U, // ZIP2v4i32 - 2218303942U, // ZIP2v8i16 - 2218828230U, // ZIP2v8i8 - 302003021U, // anonymous_1349 + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 5856U, // DBG_VALUE + 5866U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 5849U, // BUNDLE + 5876U, // LIFETIME_START + 5836U, // LIFETIME_END + 0U, // STACKMAP + 5913U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 5728U, // PATCHABLE_FUNCTION_ENTER + 5645U, // PATCHABLE_RET + 5774U, // PATCHABLE_FUNCTION_EXIT + 5751U, // PATCHABLE_TAIL_CALL + 5703U, // PATCHABLE_EVENT_CALL + 5679U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 12783U, // ABS_ZPmZ_B + 20975U, // ABS_ZPmZ_D + 2181591535U, // ABS_ZPmZ_H + 37359U, // ABS_ZPmZ_S + 68202991U, // ABSv16i8 + 2248200687U, // ABSv1i64 + 68727279U, // ABSv2i32 + 2216735215U, // ABSv2i64 + 69775855U, // ABSv4i16 + 2217783791U, // ABSv4i32 + 70824431U, // ABSv8i16 + 2218832367U, // ABSv8i8 + 100717078U, // ADCSWr + 100717078U, // ADCSXr + 100714262U, // ADCWr + 100714262U, // ADCXr + 2216210145U, // ADDHNv2i64_v2i32 + 2284904787U, // ADDHNv2i64_v4i32 + 69775073U, // ADDHNv4i32_v4i16 + 137945427U, // ADDHNv4i32_v8i16 + 2282807635U, // ADDHNv8i16_v16i8 + 2218831585U, // ADDHNv8i16_v8i8 + 100716037U, // ADDPL_XXI + 68202454U, // ADDPv16i8 + 2216210390U, // ADDPv2i32 + 2216734678U, // ADDPv2i64 + 2214645718U, // ADDPv2i64p + 69775318U, // ADDPv4i16 + 70299606U, // ADDPv4i32 + 2218307542U, // ADDPv8i16 + 2218831830U, // ADDPv8i8 + 100717090U, // ADDSWri + 0U, // ADDSWrr + 100717090U, // ADDSWrs + 100717090U, // ADDSWrx + 100717090U, // ADDSXri + 0U, // ADDSXrr + 100717090U, // ADDSXrs + 100717090U, // ADDSXrx + 100717090U, // ADDSXrx64 + 100716155U, // ADDVL_XXI + 67163034U, // ADDVv16i8v + 67163034U, // ADDVv4i16v + 2214646682U, // ADDVv4i32v + 67163034U, // ADDVv8i16v + 2214646682U, // ADDVv8i8v + 100714463U, // ADDWri + 0U, // ADDWrr + 100714463U, // ADDWrs + 100714463U, // ADDWrx + 100714463U, // ADDXri + 0U, // ADDXrr + 100714463U, // ADDXrs + 100714463U, // ADDXrx + 100714463U, // ADDXrx64 + 167782367U, // ADD_ZI_B + 201344991U, // ADD_ZI_D + 239626207U, // ADD_ZI_H + 268470239U, // ADD_ZI_S + 302000095U, // ADD_ZPmZ_B + 302008287U, // ADD_ZPmZ_D + 2186307551U, // ADD_ZPmZ_H + 302024671U, // ADD_ZPmZ_S + 167782367U, // ADD_ZZZ_B + 201344991U, // ADD_ZZZ_D + 2387109855U, // ADD_ZZZ_H + 268470239U, // ADD_ZZZ_S + 0U, // ADDlowTLS + 68200415U, // ADDv16i8 + 100714463U, // ADDv1i64 + 2216208351U, // ADDv2i32 + 2216732639U, // ADDv2i64 + 69773279U, // ADDv4i16 + 70297567U, // ADDv4i32 + 2218305503U, // ADDv8i16 + 2218829791U, // ADDv8i8 + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 2248200418U, // ADR + 335597633U, // ADRP + 207114466U, // ADR_LSL_ZZZ_D_0 + 207114466U, // ADR_LSL_ZZZ_D_1 + 207114466U, // ADR_LSL_ZZZ_D_2 + 207114466U, // ADR_LSL_ZZZ_D_3 + 274239714U, // ADR_LSL_ZZZ_S_0 + 274239714U, // ADR_LSL_ZZZ_S_1 + 274239714U, // ADR_LSL_ZZZ_S_2 + 274239714U, // ADR_LSL_ZZZ_S_3 + 207114466U, // ADR_SXTW_ZZZ_D_0 + 207114466U, // ADR_SXTW_ZZZ_D_1 + 207114466U, // ADR_SXTW_ZZZ_D_2 + 207114466U, // ADR_SXTW_ZZZ_D_3 + 207114466U, // ADR_UXTW_ZZZ_D_0 + 207114466U, // ADR_UXTW_ZZZ_D_1 + 207114466U, // ADR_UXTW_ZZZ_D_2 + 207114466U, // ADR_UXTW_ZZZ_D_3 + 135325775U, // AESDrr + 135325907U, // AESErr + 68200224U, // AESIMCrr + 0U, // AESIMCrrTied + 68200232U, // AESMCrr + 0U, // AESMCrrTied + 100717097U, // ANDSWri + 0U, // ANDSWrr + 100717097U, // ANDSWrs + 100717097U, // ANDSXri + 0U, // ANDSXrr + 100717097U, // ANDSXrs + 302002729U, // ANDS_PPzPP + 302044078U, // ANDV_VPZ_B + 302044078U, // ANDV_VPZ_D + 302044078U, // ANDV_VPZ_H + 302044078U, // ANDV_VPZ_S + 100714549U, // ANDWri + 0U, // ANDWrr + 100714549U, // ANDWrs + 100714549U, // ANDXri + 0U, // ANDXrr + 100714549U, // ANDXrs + 302000181U, // AND_PPzPP + 201345077U, // AND_ZI + 302000181U, // AND_ZPmZ_B + 302008373U, // AND_ZPmZ_D + 2186307637U, // AND_ZPmZ_H + 302024757U, // AND_ZPmZ_S + 201345077U, // AND_ZZZ + 68200501U, // ANDv16i8 + 2218829877U, // ANDv8i8 + 302000201U, // ASRD_ZPmI_B + 302008393U, // ASRD_ZPmI_D + 2186307657U, // ASRD_ZPmI_H + 302024777U, // ASRD_ZPmI_S + 302002512U, // ASRR_ZPmZ_B + 302010704U, // ASRR_ZPmZ_D + 2186309968U, // ASRR_ZPmZ_H + 302027088U, // ASRR_ZPmZ_S + 100716892U, // ASRVWr + 100716892U, // ASRVXr + 302002524U, // ASR_WIDE_ZPmZ_B + 2186309980U, // ASR_WIDE_ZPmZ_H + 302027100U, // ASR_WIDE_ZPmZ_S + 167784796U, // ASR_WIDE_ZZZ_B + 2387112284U, // ASR_WIDE_ZZZ_H + 268472668U, // ASR_WIDE_ZZZ_S + 302002524U, // ASR_ZPmI_B + 302010716U, // ASR_ZPmI_D + 2186309980U, // ASR_ZPmI_H + 302027100U, // ASR_ZPmI_S + 302002524U, // ASR_ZPmZ_B + 302010716U, // ASR_ZPmZ_D + 2186309980U, // ASR_ZPmZ_H + 302027100U, // ASR_ZPmZ_S + 167784796U, // ASR_ZZI_B + 201347420U, // ASR_ZZI_D + 239628636U, // ASR_ZZI_H + 268472668U, // ASR_ZZI_S + 2248196751U, // AUTDA + 2248197244U, // AUTDB + 6341460U, // AUTDZA + 6342386U, // AUTDZB + 2248196772U, // AUTIA + 5806U, // AUTIA1716 + 5935U, // AUTIASP + 5989U, // AUTIAZ + 2248197264U, // AUTIB + 5826U, // AUTIB1716 + 5951U, // AUTIBSP + 6003U, // AUTIBZ + 6341476U, // AUTIZA + 6342402U, // AUTIZB + 66415U, // B + 68203857U, // BCAX + 369151650U, // BFMWri + 369151650U, // BFMXri + 0U, // BICSWrr + 100717084U, // BICSWrs + 0U, // BICSXrr + 100717084U, // BICSXrs + 302002716U, // BICS_PPzPP + 0U, // BICWrr + 100714267U, // BICWrs + 0U, // BICXrr + 100714267U, // BICXrs + 301999899U, // BIC_PPzPP + 301999899U, // BIC_ZPmZ_B + 302008091U, // BIC_ZPmZ_D + 2186307355U, // BIC_ZPmZ_H + 302024475U, // BIC_ZPmZ_S + 201344795U, // BIC_ZZZ + 68200219U, // BICv16i8 + 404285211U, // BICv2i32 + 405333787U, // BICv4i16 + 405858075U, // BICv4i32 + 406382363U, // BICv8i16 + 2218829595U, // BICv8i8 + 68200698U, // BIFv16i8 + 2218830074U, // BIFv8i8 + 135328513U, // BITv16i8 + 2285957889U, // BITv8i8 + 68906U, // BL + 6344980U, // BLR + 2248196710U, // BLRAA + 6346175U, // BLRAAZ + 2248197127U, // BLRAB + 6346190U, // BLRABZ + 6344926U, // BR + 2248196697U, // BRAA + 6346168U, // BRAAZ + 2248197114U, // BRAB + 6346183U, // BRABZ + 76951U, // BRK + 302002647U, // BRKAS_PPzP + 8875U, // BRKA_PPmP + 301998763U, // BRKA_PPzP + 302002683U, // BRKBS_PPzP + 9367U, // BRKB_PPmP + 301999255U, // BRKB_PPzP + 302002803U, // BRKNS_PPzP + 302001918U, // BRKN_PPzP + 302002654U, // BRKPAS_PPzPP + 301998807U, // BRKPA_PPzPP + 302002690U, // BRKPBS_PPzPP + 301999474U, // BRKPB_PPzPP + 135327279U, // BSLv16i8 + 2285956655U, // BSLv8i8 + 87596U, // Bcc + 2516673568U, // CASAB + 2516675032U, // CASAH + 2516673753U, // CASALB + 2516675183U, // CASALH + 2516675845U, // CASALW + 2516675845U, // CASALX + 2516673308U, // CASAW + 2516673308U, // CASAX + 2516674100U, // CASB + 2516675551U, // CASH + 2516673847U, // CASLB + 2516675277U, // CASLH + 2516676137U, // CASLW + 2516676137U, // CASLX + 101604U, // CASPALW + 109796U, // CASPALX + 99038U, // CASPAW + 107230U, // CASPAX + 101900U, // CASPLW + 110092U, // CASPLX + 102471U, // CASPW + 110663U, // CASPX + 2516677074U, // CASW + 2516677074U, // CASX + 436262373U, // CBNZW + 436262373U, // CBNZX + 436262358U, // CBZW + 436262358U, // CBZX + 100716292U, // CCMNWi + 100716292U, // CCMNWr + 100716292U, // CCMNXi + 100716292U, // CCMNXr + 100716546U, // CCMPWi + 100716546U, // CCMPWr + 100716546U, // CCMPXi + 100716546U, // CCMPXr + 5976U, // CFINV + 302039858U, // CLASTA_RPZ_B + 302039858U, // CLASTA_RPZ_D + 302039858U, // CLASTA_RPZ_H + 302039858U, // CLASTA_RPZ_S + 302039858U, // CLASTA_VPZ_B + 302039858U, // CLASTA_VPZ_D + 302039858U, // CLASTA_VPZ_H + 302039858U, // CLASTA_VPZ_S + 301998898U, // CLASTA_ZPZ_B + 302007090U, // CLASTA_ZPZ_D + 2387632946U, // CLASTA_ZPZ_H + 302023474U, // CLASTA_ZPZ_S + 302040717U, // CLASTB_RPZ_B + 302040717U, // CLASTB_RPZ_D + 302040717U, // CLASTB_RPZ_H + 302040717U, // CLASTB_RPZ_S + 302040717U, // CLASTB_VPZ_B + 302040717U, // CLASTB_VPZ_D + 302040717U, // CLASTB_VPZ_H + 302040717U, // CLASTB_VPZ_S + 301999757U, // CLASTB_ZPZ_B + 302007949U, // CLASTB_ZPZ_D + 2387633805U, // CLASTB_ZPZ_H + 302024333U, // CLASTB_ZPZ_S + 6346114U, // CLREX + 2248200772U, // CLSWr + 2248200772U, // CLSXr + 12868U, // CLS_ZPmZ_B + 21060U, // CLS_ZPmZ_D + 2181591620U, // CLS_ZPmZ_H + 37444U, // CLS_ZPmZ_S + 68203076U, // CLSv16i8 + 68727364U, // CLSv2i32 + 69775940U, // CLSv4i16 + 2217783876U, // CLSv4i32 + 70824516U, // CLSv8i16 + 2218832452U, // CLSv8i8 + 2248201696U, // CLZWr + 2248201696U, // CLZXr + 13792U, // CLZ_ZPmZ_B + 21984U, // CLZ_ZPmZ_D + 2181592544U, // CLZ_ZPmZ_H + 38368U, // CLZ_ZPmZ_S + 68204000U, // CLZv16i8 + 68728288U, // CLZv2i32 + 69776864U, // CLZv4i16 + 2217784800U, // CLZv4i32 + 70825440U, // CLZv8i16 + 2218833376U, // CLZv8i8 + 68202651U, // CMEQv16i8 + 68202651U, // CMEQv16i8rz + 100716699U, // CMEQv1i64 + 2248200347U, // CMEQv1i64rz + 2216210587U, // CMEQv2i32 + 68726939U, // CMEQv2i32rz + 2216734875U, // CMEQv2i64 + 2216734875U, // CMEQv2i64rz + 69775515U, // CMEQv4i16 + 69775515U, // CMEQv4i16rz + 70299803U, // CMEQv4i32 + 2217783451U, // CMEQv4i32rz + 2218307739U, // CMEQv8i16 + 70824091U, // CMEQv8i16rz + 2218832027U, // CMEQv8i8 + 2218832027U, // CMEQv8i8rz + 68200561U, // CMGEv16i8 + 68200561U, // CMGEv16i8rz + 100714609U, // CMGEv1i64 + 2248198257U, // CMGEv1i64rz + 2216208497U, // CMGEv2i32 + 68724849U, // CMGEv2i32rz + 2216732785U, // CMGEv2i64 + 2216732785U, // CMGEv2i64rz + 69773425U, // CMGEv4i16 + 69773425U, // CMGEv4i16rz + 70297713U, // CMGEv4i32 + 2217781361U, // CMGEv4i32rz + 2218305649U, // CMGEv8i16 + 70822001U, // CMGEv8i16rz + 2218829937U, // CMGEv8i8 + 2218829937U, // CMGEv8i8rz + 68203251U, // CMGTv16i8 + 68203251U, // CMGTv16i8rz + 100717299U, // CMGTv1i64 + 2248200947U, // CMGTv1i64rz + 2216211187U, // CMGTv2i32 + 68727539U, // CMGTv2i32rz + 2216735475U, // CMGTv2i64 + 2216735475U, // CMGTv2i64rz + 69776115U, // CMGTv4i16 + 69776115U, // CMGTv4i16rz + 70300403U, // CMGTv4i32 + 2217784051U, // CMGTv4i32rz + 2218308339U, // CMGTv8i16 + 70824691U, // CMGTv8i16rz + 2218832627U, // CMGTv8i8 + 2218832627U, // CMGTv8i8rz + 68201580U, // CMHIv16i8 + 100715628U, // CMHIv1i64 + 2216209516U, // CMHIv2i32 + 2216733804U, // CMHIv2i64 + 69774444U, // CMHIv4i16 + 70298732U, // CMHIv4i32 + 2218306668U, // CMHIv8i16 + 2218830956U, // CMHIv8i8 + 68203063U, // CMHSv16i8 + 100717111U, // CMHSv1i64 + 2216210999U, // CMHSv2i32 + 2216735287U, // CMHSv2i64 + 69775927U, // CMHSv4i16 + 70300215U, // CMHSv4i32 + 2218308151U, // CMHSv8i16 + 2218832439U, // CMHSv8i8 + 68200592U, // CMLEv16i8rz + 2248198288U, // CMLEv1i64rz + 68724880U, // CMLEv2i32rz + 2216732816U, // CMLEv2i64rz + 69773456U, // CMLEv4i16rz + 2217781392U, // CMLEv4i32rz + 70822032U, // CMLEv8i16rz + 2218829968U, // CMLEv8i8rz + 68203285U, // CMLTv16i8rz + 2248200981U, // CMLTv1i64rz + 68727573U, // CMLTv2i32rz + 2216735509U, // CMLTv2i64rz + 69776149U, // CMLTv4i16rz + 2217784085U, // CMLTv4i32rz + 70824725U, // CMLTv8i16rz + 2218832661U, // CMLTv8i8rz + 302002346U, // CMPEQ_PPzZI_B + 302010538U, // CMPEQ_PPzZI_D + 2622517418U, // CMPEQ_PPzZI_H + 302026922U, // CMPEQ_PPzZI_S + 302002346U, // CMPEQ_PPzZZ_B + 302010538U, // CMPEQ_PPzZZ_D + 2622517418U, // CMPEQ_PPzZZ_H + 302026922U, // CMPEQ_PPzZZ_S + 302002346U, // CMPEQ_WIDE_PPzZZ_B + 2622517418U, // CMPEQ_WIDE_PPzZZ_H + 302026922U, // CMPEQ_WIDE_PPzZZ_S + 302000247U, // CMPGE_PPzZI_B + 302008439U, // CMPGE_PPzZI_D + 2622515319U, // CMPGE_PPzZI_H + 302024823U, // CMPGE_PPzZI_S + 302000247U, // CMPGE_PPzZZ_B + 302008439U, // CMPGE_PPzZZ_D + 2622515319U, // CMPGE_PPzZZ_H + 302024823U, // CMPGE_PPzZZ_S + 302000247U, // CMPGE_WIDE_PPzZZ_B + 2622515319U, // CMPGE_WIDE_PPzZZ_H + 302024823U, // CMPGE_WIDE_PPzZZ_S + 302002937U, // CMPGT_PPzZI_B + 302011129U, // CMPGT_PPzZI_D + 2622518009U, // CMPGT_PPzZI_H + 302027513U, // CMPGT_PPzZI_S + 302002937U, // CMPGT_PPzZZ_B + 302011129U, // CMPGT_PPzZZ_D + 2622518009U, // CMPGT_PPzZZ_H + 302027513U, // CMPGT_PPzZZ_S + 302002937U, // CMPGT_WIDE_PPzZZ_B + 2622518009U, // CMPGT_WIDE_PPzZZ_H + 302027513U, // CMPGT_WIDE_PPzZZ_S + 302001266U, // CMPHI_PPzZI_B + 302009458U, // CMPHI_PPzZI_D + 2622516338U, // CMPHI_PPzZI_H + 302025842U, // CMPHI_PPzZI_S + 302001266U, // CMPHI_PPzZZ_B + 302009458U, // CMPHI_PPzZZ_D + 2622516338U, // CMPHI_PPzZZ_H + 302025842U, // CMPHI_PPzZZ_S + 302001266U, // CMPHI_WIDE_PPzZZ_B + 2622516338U, // CMPHI_WIDE_PPzZZ_H + 302025842U, // CMPHI_WIDE_PPzZZ_S + 302002749U, // CMPHS_PPzZI_B + 302010941U, // CMPHS_PPzZI_D + 2622517821U, // CMPHS_PPzZI_H + 302027325U, // CMPHS_PPzZI_S + 302002749U, // CMPHS_PPzZZ_B + 302010941U, // CMPHS_PPzZZ_D + 2622517821U, // CMPHS_PPzZZ_H + 302027325U, // CMPHS_PPzZZ_S + 302002749U, // CMPHS_WIDE_PPzZZ_B + 2622517821U, // CMPHS_WIDE_PPzZZ_H + 302027325U, // CMPHS_WIDE_PPzZZ_S + 302000278U, // CMPLE_PPzZI_B + 302008470U, // CMPLE_PPzZI_D + 2622515350U, // CMPLE_PPzZI_H + 302024854U, // CMPLE_PPzZI_S + 302000278U, // CMPLE_WIDE_PPzZZ_B + 2622515350U, // CMPLE_WIDE_PPzZZ_H + 302024854U, // CMPLE_WIDE_PPzZZ_S + 302002080U, // CMPLO_PPzZI_B + 302010272U, // CMPLO_PPzZI_D + 2622517152U, // CMPLO_PPzZI_H + 302026656U, // CMPLO_PPzZI_S + 302002080U, // CMPLO_WIDE_PPzZZ_B + 2622517152U, // CMPLO_WIDE_PPzZZ_H + 302026656U, // CMPLO_WIDE_PPzZZ_S + 302002783U, // CMPLS_PPzZI_B + 302010975U, // CMPLS_PPzZI_D + 2622517855U, // CMPLS_PPzZI_H + 302027359U, // CMPLS_PPzZI_S + 302002783U, // CMPLS_WIDE_PPzZZ_B + 2622517855U, // CMPLS_WIDE_PPzZZ_H + 302027359U, // CMPLS_WIDE_PPzZZ_S + 302002971U, // CMPLT_PPzZI_B + 302011163U, // CMPLT_PPzZI_D + 2622518043U, // CMPLT_PPzZI_H + 302027547U, // CMPLT_PPzZI_S + 302002971U, // CMPLT_WIDE_PPzZZ_B + 2622518043U, // CMPLT_WIDE_PPzZZ_H + 302027547U, // CMPLT_WIDE_PPzZZ_S + 302000301U, // CMPNE_PPzZI_B + 302008493U, // CMPNE_PPzZI_D + 2622515373U, // CMPNE_PPzZI_H + 302024877U, // CMPNE_PPzZI_S + 302000301U, // CMPNE_PPzZZ_B + 302008493U, // CMPNE_PPzZZ_D + 2622515373U, // CMPNE_PPzZZ_H + 302024877U, // CMPNE_PPzZZ_S + 302000301U, // CMPNE_WIDE_PPzZZ_B + 2622515373U, // CMPNE_WIDE_PPzZZ_H + 302024877U, // CMPNE_WIDE_PPzZZ_S + 0U, // CMP_SWAP_128 + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 68203349U, // CMTSTv16i8 + 100717397U, // CMTSTv1i64 + 2216211285U, // CMTSTv2i32 + 2216735573U, // CMTSTv2i64 + 69776213U, // CMTSTv4i16 + 70300501U, // CMTSTv4i32 + 2218308437U, // CMTSTv8i16 + 2218832725U, // CMTSTv8i8 + 13113U, // CNOT_ZPmZ_B + 21305U, // CNOT_ZPmZ_D + 2181591865U, // CNOT_ZPmZ_H + 37689U, // CNOT_ZPmZ_S + 503367303U, // CNTB_XPiI + 503367765U, // CNTD_XPiI + 503368736U, // CNTH_XPiI + 302043213U, // CNTP_XPP_B + 302043213U, // CNTP_XPP_D + 302043213U, // CNTP_XPP_H + 302043213U, // CNTP_XPP_S + 503371057U, // CNTW_XPiI + 13090U, // CNT_ZPmZ_B + 21282U, // CNT_ZPmZ_D + 2181591842U, // CNT_ZPmZ_H + 37666U, // CNT_ZPmZ_S + 68203298U, // CNTv16i8 + 2218832674U, // CNTv8i8 + 302011094U, // COMPACT_ZPZ_D + 302027478U, // COMPACT_ZPZ_S + 13747U, // CPY_ZPmI_B + 21939U, // CPY_ZPmI_D + 2181592499U, // CPY_ZPmI_H + 38323U, // CPY_ZPmI_S + 13747U, // CPY_ZPmR_B + 21939U, // CPY_ZPmR_D + 34108851U, // CPY_ZPmR_H + 38323U, // CPY_ZPmR_S + 13747U, // CPY_ZPmV_B + 21939U, // CPY_ZPmV_D + 34108851U, // CPY_ZPmV_H + 38323U, // CPY_ZPmV_S + 302003635U, // CPY_ZPzI_B + 302011827U, // CPY_ZPzI_D + 2622518707U, // CPY_ZPzI_H + 302028211U, // CPY_ZPzI_S + 67163146U, // CPYi16 + 2214646794U, // CPYi32 + 67163146U, // CPYi64 + 2214646794U, // CPYi8 + 100713377U, // CRC32Brr + 100713540U, // CRC32CBrr + 100715004U, // CRC32CHrr + 100717724U, // CRC32CWrr + 100717938U, // CRC32CXrr + 100714851U, // CRC32Hrr + 100717666U, // CRC32Wrr + 100717897U, // CRC32Xrr + 100715905U, // CSELWr + 100715905U, // CSELXr + 100714287U, // CSINCWr + 100714287U, // CSINCXr + 100717570U, // CSINVWr + 100717570U, // CSINVXr + 100714784U, // CSNEGWr + 100714784U, // CSNEGXr + 2248200353U, // CTERMEQ_WW + 2248200353U, // CTERMEQ_XX + 2248198308U, // CTERMNE_WW + 2248198308U, // CTERMNE_XX + 0U, // CompilerBarrier + 73783U, // DCPS1 + 74194U, // DCPS2 + 74260U, // DCPS3 + 536921167U, // DECB_XPiI + 536922047U, // DECD_XPiI + 536889279U, // DECD_ZPiI + 536922631U, // DECH_XPiI + 6842887U, // DECH_ZPiI + 2315308983U, // DECP_XP_B + 2348863415U, // DECP_XP_D + 2717962167U, // DECP_XP_H + 2415972279U, // DECP_XP_S + 2147504055U, // DECP_ZP_D + 604532663U, // DECP_ZP_H + 2147520439U, // DECP_ZP_S + 536925351U, // DECW_XPiI + 536908967U, // DECW_ZPiI + 116059U, // DMB + 5966U, // DRPS + 116282U, // DSB + 637554371U, // DUPM_ZI + 671101025U, // DUP_ZI_B + 704663649U, // DUP_ZI_D + 7368801U, // DUP_ZI_H + 738234465U, // DUP_ZI_S + 2248159329U, // DUP_ZR_B + 2248167521U, // DUP_ZR_D + 611872865U, // DUP_ZR_H + 2248183905U, // DUP_ZR_S + 167784545U, // DUP_ZZI_B + 201347169U, // DUP_ZZI_D + 776499297U, // DUP_ZZI_H + 127073U, // DUP_ZZI_Q + 268472417U, // DUP_ZZI_S + 2249240673U, // DUPv16i8gpr + 2215686241U, // DUPv16i8lane + 2249764961U, // DUPv2i32gpr + 2216210529U, // DUPv2i32lane + 2250289249U, // DUPv2i64gpr + 69251169U, // DUPv2i64lane + 2250813537U, // DUPv4i16gpr + 69775457U, // DUPv4i16lane + 2251337825U, // DUPv4i32gpr + 2217783393U, // DUPv4i32lane + 2251862113U, // DUPv8i16gpr + 70824033U, // DUPv8i16lane + 2252386401U, // DUPv8i8gpr + 2218831969U, // DUPv8i8lane + 0U, // EONWrr + 100716298U, // EONWrs + 0U, // EONXrr + 100716298U, // EONXrs + 68198926U, // EOR3 + 302002853U, // EORS_PPzPP + 302044187U, // EORV_VPZ_B + 302044187U, // EORV_VPZ_D + 302044187U, // EORV_VPZ_H + 302044187U, // EORV_VPZ_S + 100716853U, // EORWri + 0U, // EORWrr + 100716853U, // EORWrs + 100716853U, // EORXri + 0U, // EORXrr + 100716853U, // EORXrs + 302002485U, // EOR_PPzPP + 201347381U, // EOR_ZI + 302002485U, // EOR_ZPmZ_B + 302010677U, // EOR_ZPmZ_D + 2186309941U, // EOR_ZPmZ_H + 302027061U, // EOR_ZPmZ_S + 201347381U, // EOR_ZZZ + 68202805U, // EORv16i8 + 2218832181U, // EORv8i8 + 5971U, // ERET + 5891U, // ERETAA + 5898U, // ERETAB + 100716930U, // EXTRWrri + 100716930U, // EXTRXrri + 167785316U, // EXT_ZZI + 68203364U, // EXTv16i8 + 2218832740U, // EXTv8i8 + 0U, // F128CSEL + 100714404U, // FABD16 + 100714404U, // FABD32 + 100714404U, // FABD64 + 302008228U, // FABD_ZPmZ_D + 2186307492U, // FABD_ZPmZ_H + 302024612U, // FABD_ZPmZ_S + 2216208292U, // FABDv2f32 + 2216732580U, // FABDv2f64 + 69773220U, // FABDv4f16 + 70297508U, // FABDv4f32 + 2218305444U, // FABDv8f16 + 2248200686U, // FABSDr + 2248200686U, // FABSHr + 2248200686U, // FABSSr + 20974U, // FABS_ZPmZ_D + 2181591534U, // FABS_ZPmZ_H + 37358U, // FABS_ZPmZ_S + 68727278U, // FABSv2f32 + 2216735214U, // FABSv2f64 + 69775854U, // FABSv4f16 + 2217783790U, // FABSv4f32 + 70824430U, // FABSv8f16 + 100714601U, // FACGE16 + 100714601U, // FACGE32 + 100714601U, // FACGE64 + 302008425U, // FACGE_PPzZZ_D + 2622515305U, // FACGE_PPzZZ_H + 302024809U, // FACGE_PPzZZ_S + 2216208489U, // FACGEv2f32 + 2216732777U, // FACGEv2f64 + 69773417U, // FACGEv4f16 + 70297705U, // FACGEv4f32 + 2218305641U, // FACGEv8f16 + 100717291U, // FACGT16 + 100717291U, // FACGT32 + 100717291U, // FACGT64 + 302011115U, // FACGT_PPzZZ_D + 2622517995U, // FACGT_PPzZZ_H + 302027499U, // FACGT_PPzZZ_S + 2216211179U, // FACGTv2f32 + 2216735467U, // FACGTv2f64 + 69776107U, // FACGTv4f16 + 70300395U, // FACGTv4f32 + 2218308331U, // FACGTv8f16 + 302039688U, // FADDA_VPZ_D + 302039688U, // FADDA_VPZ_H + 302039688U, // FADDA_VPZ_S + 100714475U, // FADDDrr + 100714475U, // FADDHrr + 2216210389U, // FADDPv2f32 + 2216734677U, // FADDPv2f64 + 2214645717U, // FADDPv2i16p + 67162069U, // FADDPv2i32p + 2214645717U, // FADDPv2i64p + 69775317U, // FADDPv4f16 + 70299605U, // FADDPv4f32 + 2218307541U, // FADDPv8f16 + 100714475U, // FADDSrr + 302044057U, // FADDV_VPZ_D + 302044057U, // FADDV_VPZ_H + 302044057U, // FADDV_VPZ_S + 302008299U, // FADD_ZPmI_D + 2186307563U, // FADD_ZPmI_H + 302024683U, // FADD_ZPmI_S + 302008299U, // FADD_ZPmZ_D + 2186307563U, // FADD_ZPmZ_H + 302024683U, // FADD_ZPmZ_S + 201345003U, // FADD_ZZZ_D + 2387109867U, // FADD_ZZZ_H + 268470251U, // FADD_ZZZ_S + 2216208363U, // FADDv2f32 + 2216732651U, // FADDv2f64 + 69773291U, // FADDv4f16 + 70297579U, // FADDv4f32 + 2218305515U, // FADDv8f16 + 302008285U, // FCADD_ZPmZ_D + 2186307549U, // FCADD_ZPmZ_H + 302024669U, // FCADD_ZPmZ_S + 2216208349U, // FCADDv2f32 + 2216732637U, // FCADDv2f64 + 69773277U, // FCADDv4f16 + 70297565U, // FCADDv4f32 + 2218305501U, // FCADDv8f16 + 100716545U, // FCCMPDrr + 100714692U, // FCCMPEDrr + 100714692U, // FCCMPEHrr + 100714692U, // FCCMPESrr + 100716545U, // FCCMPHrr + 100716545U, // FCCMPSrr + 100716698U, // FCMEQ16 + 100716698U, // FCMEQ32 + 100716698U, // FCMEQ64 + 302010522U, // FCMEQ_PPzZ0_D + 2622517402U, // FCMEQ_PPzZ0_H + 302026906U, // FCMEQ_PPzZ0_S + 302010522U, // FCMEQ_PPzZZ_D + 2622517402U, // FCMEQ_PPzZZ_H + 302026906U, // FCMEQ_PPzZZ_S + 100716698U, // FCMEQv1i16rz + 100716698U, // FCMEQv1i32rz + 100716698U, // FCMEQv1i64rz + 2216210586U, // FCMEQv2f32 + 2216734874U, // FCMEQv2f64 + 2216210586U, // FCMEQv2i32rz + 69251226U, // FCMEQv2i64rz + 69775514U, // FCMEQv4f16 + 70299802U, // FCMEQv4f32 + 2217259162U, // FCMEQv4i16rz + 70299802U, // FCMEQv4i32rz + 2218307738U, // FCMEQv8f16 + 2218307738U, // FCMEQv8i16rz + 100714608U, // FCMGE16 + 100714608U, // FCMGE32 + 100714608U, // FCMGE64 + 302008432U, // FCMGE_PPzZ0_D + 2622515312U, // FCMGE_PPzZ0_H + 302024816U, // FCMGE_PPzZ0_S + 302008432U, // FCMGE_PPzZZ_D + 2622515312U, // FCMGE_PPzZZ_H + 302024816U, // FCMGE_PPzZZ_S + 100714608U, // FCMGEv1i16rz + 100714608U, // FCMGEv1i32rz + 100714608U, // FCMGEv1i64rz + 2216208496U, // FCMGEv2f32 + 2216732784U, // FCMGEv2f64 + 2216208496U, // FCMGEv2i32rz + 69249136U, // FCMGEv2i64rz + 69773424U, // FCMGEv4f16 + 70297712U, // FCMGEv4f32 + 2217257072U, // FCMGEv4i16rz + 70297712U, // FCMGEv4i32rz + 2218305648U, // FCMGEv8f16 + 2218305648U, // FCMGEv8i16rz + 100717298U, // FCMGT16 + 100717298U, // FCMGT32 + 100717298U, // FCMGT64 + 302011122U, // FCMGT_PPzZ0_D + 2622518002U, // FCMGT_PPzZ0_H + 302027506U, // FCMGT_PPzZ0_S + 302011122U, // FCMGT_PPzZZ_D + 2622518002U, // FCMGT_PPzZZ_H + 302027506U, // FCMGT_PPzZZ_S + 100717298U, // FCMGTv1i16rz + 100717298U, // FCMGTv1i32rz + 100717298U, // FCMGTv1i64rz + 2216211186U, // FCMGTv2f32 + 2216735474U, // FCMGTv2f64 + 2216211186U, // FCMGTv2i32rz + 69251826U, // FCMGTv2i64rz + 69776114U, // FCMGTv4f16 + 70300402U, // FCMGTv4f32 + 2217259762U, // FCMGTv4i16rz + 70300402U, // FCMGTv4i32rz + 2218308338U, // FCMGTv8f16 + 2218308338U, // FCMGTv8i16rz + 302006961U, // FCMLA_ZPmZZ_D + 2186306225U, // FCMLA_ZPmZZ_H + 302023345U, // FCMLA_ZPmZZ_S + 243294897U, // FCMLA_ZZZI_H + 2952823473U, // FCMLA_ZZZI_S + 2283332273U, // FCMLAv2f32 + 2283856561U, // FCMLAv2f64 + 136897201U, // FCMLAv4f16 + 136897201U, // FCMLAv4f16_indexed + 137421489U, // FCMLAv4f32 + 137421489U, // FCMLAv4f32_indexed + 2285429425U, // FCMLAv8f16 + 2285429425U, // FCMLAv8f16_indexed + 302008463U, // FCMLE_PPzZ0_D + 2622515343U, // FCMLE_PPzZ0_H + 302024847U, // FCMLE_PPzZ0_S + 100714639U, // FCMLEv1i16rz + 100714639U, // FCMLEv1i32rz + 100714639U, // FCMLEv1i64rz + 2216208527U, // FCMLEv2i32rz + 69249167U, // FCMLEv2i64rz + 2217257103U, // FCMLEv4i16rz + 70297743U, // FCMLEv4i32rz + 2218305679U, // FCMLEv8i16rz + 302011156U, // FCMLT_PPzZ0_D + 2622518036U, // FCMLT_PPzZ0_H + 302027540U, // FCMLT_PPzZ0_S + 100717332U, // FCMLTv1i16rz + 100717332U, // FCMLTv1i32rz + 100717332U, // FCMLTv1i64rz + 2216211220U, // FCMLTv2i32rz + 69251860U, // FCMLTv2i64rz + 2217259796U, // FCMLTv4i16rz + 70300436U, // FCMLTv4i32rz + 2218308372U, // FCMLTv8i16rz + 302008477U, // FCMNE_PPzZ0_D + 2622515357U, // FCMNE_PPzZ0_H + 302024861U, // FCMNE_PPzZ0_S + 302008477U, // FCMNE_PPzZZ_D + 2622515357U, // FCMNE_PPzZZ_H + 302024861U, // FCMNE_PPzZZ_S + 8966152U, // FCMPDri + 2248200200U, // FCMPDrr + 8964300U, // FCMPEDri + 2248198348U, // FCMPEDrr + 8964300U, // FCMPEHri + 2248198348U, // FCMPEHrr + 8964300U, // FCMPESri + 2248198348U, // FCMPESrr + 8966152U, // FCMPHri + 2248200200U, // FCMPHrr + 8966152U, // FCMPSri + 2248200200U, // FCMPSrr + 302010279U, // FCMUO_PPzZZ_D + 2622517159U, // FCMUO_PPzZZ_H + 302026663U, // FCMUO_PPzZZ_S + 21938U, // FCPY_ZPmI_D + 34108850U, // FCPY_ZPmI_H + 38322U, // FCPY_ZPmI_S + 100715904U, // FCSELDrrr + 100715904U, // FCSELHrrr + 100715904U, // FCSELSrrr + 2248200678U, // FCVTASUWDr + 2248200678U, // FCVTASUWHr + 2248200678U, // FCVTASUWSr + 2248200678U, // FCVTASUXDr + 2248200678U, // FCVTASUXHr + 2248200678U, // FCVTASUXSr + 2248200678U, // FCVTASv1f16 + 2248200678U, // FCVTASv1i32 + 2248200678U, // FCVTASv1i64 + 68727270U, // FCVTASv2f32 + 2216735206U, // FCVTASv2f64 + 69775846U, // FCVTASv4f16 + 2217783782U, // FCVTASv4f32 + 70824422U, // FCVTASv8f16 + 2248201065U, // FCVTAUUWDr + 2248201065U, // FCVTAUUWHr + 2248201065U, // FCVTAUUWSr + 2248201065U, // FCVTAUUXDr + 2248201065U, // FCVTAUUXHr + 2248201065U, // FCVTAUUXSr + 2248201065U, // FCVTAUv1f16 + 2248201065U, // FCVTAUv1i32 + 2248201065U, // FCVTAUv1i64 + 68727657U, // FCVTAUv2f32 + 2216735593U, // FCVTAUv2f64 + 69776233U, // FCVTAUv4f16 + 2217784169U, // FCVTAUv4f32 + 70824809U, // FCVTAUv8f16 + 2248201052U, // FCVTDHr + 2248201052U, // FCVTDSr + 2248201052U, // FCVTHDr + 2248201052U, // FCVTHSr + 69250649U, // FCVTLv2i32 + 70299225U, // FCVTLv4i16 + 2216730945U, // FCVTLv4i32 + 70295873U, // FCVTLv8i16 + 2248200806U, // FCVTMSUWDr + 2248200806U, // FCVTMSUWHr + 2248200806U, // FCVTMSUWSr + 2248200806U, // FCVTMSUXDr + 2248200806U, // FCVTMSUXHr + 2248200806U, // FCVTMSUXSr + 2248200806U, // FCVTMSv1f16 + 2248200806U, // FCVTMSv1i32 + 2248200806U, // FCVTMSv1i64 + 68727398U, // FCVTMSv2f32 + 2216735334U, // FCVTMSv2f64 + 69775974U, // FCVTMSv4f16 + 2217783910U, // FCVTMSv4f32 + 70824550U, // FCVTMSv8f16 + 2248201081U, // FCVTMUUWDr + 2248201081U, // FCVTMUUWHr + 2248201081U, // FCVTMUUWSr + 2248201081U, // FCVTMUUXDr + 2248201081U, // FCVTMUUXHr + 2248201081U, // FCVTMUUXSr + 2248201081U, // FCVTMUv1f16 + 2248201081U, // FCVTMUv1i32 + 2248201081U, // FCVTMUv1i64 + 68727673U, // FCVTMUv2f32 + 2216735609U, // FCVTMUv2f64 + 69776249U, // FCVTMUv4f16 + 2217784185U, // FCVTMUv4f32 + 70824825U, // FCVTMUv8f16 + 2248200832U, // FCVTNSUWDr + 2248200832U, // FCVTNSUWHr + 2248200832U, // FCVTNSUWSr + 2248200832U, // FCVTNSUXDr + 2248200832U, // FCVTNSUXHr + 2248200832U, // FCVTNSUXSr + 2248200832U, // FCVTNSv1f16 + 2248200832U, // FCVTNSv1i32 + 2248200832U, // FCVTNSv1i64 + 68727424U, // FCVTNSv2f32 + 2216735360U, // FCVTNSv2f64 + 69776000U, // FCVTNSv4f16 + 2217783936U, // FCVTNSv4f32 + 70824576U, // FCVTNSv8f16 + 2248201089U, // FCVTNUUWDr + 2248201089U, // FCVTNUUWHr + 2248201089U, // FCVTNUUWSr + 2248201089U, // FCVTNUUXDr + 2248201089U, // FCVTNUUXHr + 2248201089U, // FCVTNUUXSr + 2248201089U, // FCVTNUv1f16 + 2248201089U, // FCVTNUv1i32 + 2248201089U, // FCVTNUv1i64 + 68727681U, // FCVTNUv2f32 + 2216735617U, // FCVTNUv2f64 + 69776257U, // FCVTNUv4f16 + 2217784193U, // FCVTNUv4f32 + 70824833U, // FCVTNUv8f16 + 2216210238U, // FCVTNv2i32 + 2217258814U, // FCVTNv4i16 + 2284904839U, // FCVTNv4i32 + 2285429127U, // FCVTNv8i16 + 2248200848U, // FCVTPSUWDr + 2248200848U, // FCVTPSUWHr + 2248200848U, // FCVTPSUWSr + 2248200848U, // FCVTPSUXDr + 2248200848U, // FCVTPSUXHr + 2248200848U, // FCVTPSUXSr + 2248200848U, // FCVTPSv1f16 + 2248200848U, // FCVTPSv1i32 + 2248200848U, // FCVTPSv1i64 + 68727440U, // FCVTPSv2f32 + 2216735376U, // FCVTPSv2f64 + 69776016U, // FCVTPSv4f16 + 2217783952U, // FCVTPSv4f32 + 70824592U, // FCVTPSv8f16 + 2248201097U, // FCVTPUUWDr + 2248201097U, // FCVTPUUWHr + 2248201097U, // FCVTPUUWSr + 2248201097U, // FCVTPUUXDr + 2248201097U, // FCVTPUUXHr + 2248201097U, // FCVTPUUXSr + 2248201097U, // FCVTPUv1f16 + 2248201097U, // FCVTPUv1i32 + 2248201097U, // FCVTPUv1i64 + 68727689U, // FCVTPUv2f32 + 2216735625U, // FCVTPUv2f64 + 69776265U, // FCVTPUv4f16 + 2217784201U, // FCVTPUv4f32 + 70824841U, // FCVTPUv8f16 + 2248201052U, // FCVTSDr + 2248201052U, // FCVTSHr + 2248200052U, // FCVTXNv1i64 + 2216210292U, // FCVTXNv2f32 + 2284904893U, // FCVTXNv4f32 + 100717253U, // FCVTZSSWDri + 100717253U, // FCVTZSSWHri + 100717253U, // FCVTZSSWSri + 100717253U, // FCVTZSSXDri + 100717253U, // FCVTZSSXHri + 100717253U, // FCVTZSSXSri + 2248200901U, // FCVTZSUWDr + 2248200901U, // FCVTZSUWHr + 2248200901U, // FCVTZSUWSr + 2248200901U, // FCVTZSUXDr + 2248200901U, // FCVTZSUXHr + 2248200901U, // FCVTZSUXSr + 21189U, // FCVTZS_ZPmZ_DtoD + 37573U, // FCVTZS_ZPmZ_DtoS + 21189U, // FCVTZS_ZPmZ_HtoD + 2181591749U, // FCVTZS_ZPmZ_HtoH + 37573U, // FCVTZS_ZPmZ_HtoS + 21189U, // FCVTZS_ZPmZ_StoD + 37573U, // FCVTZS_ZPmZ_StoS + 100717253U, // FCVTZSd + 100717253U, // FCVTZSh + 100717253U, // FCVTZSs + 2248200901U, // FCVTZSv1f16 + 2248200901U, // FCVTZSv1i32 + 2248200901U, // FCVTZSv1i64 + 68727493U, // FCVTZSv2f32 + 2216735429U, // FCVTZSv2f64 + 2216211141U, // FCVTZSv2i32_shift + 2216735429U, // FCVTZSv2i64_shift + 69776069U, // FCVTZSv4f16 + 2217784005U, // FCVTZSv4f32 + 69776069U, // FCVTZSv4i16_shift + 70300357U, // FCVTZSv4i32_shift + 70824645U, // FCVTZSv8f16 + 2218308293U, // FCVTZSv8i16_shift + 100717457U, // FCVTZUSWDri + 100717457U, // FCVTZUSWHri + 100717457U, // FCVTZUSWSri + 100717457U, // FCVTZUSXDri + 100717457U, // FCVTZUSXHri + 100717457U, // FCVTZUSXSri + 2248201105U, // FCVTZUUWDr + 2248201105U, // FCVTZUUWHr + 2248201105U, // FCVTZUUWSr + 2248201105U, // FCVTZUUXDr + 2248201105U, // FCVTZUUXHr + 2248201105U, // FCVTZUUXSr + 21393U, // FCVTZU_ZPmZ_DtoD + 37777U, // FCVTZU_ZPmZ_DtoS + 21393U, // FCVTZU_ZPmZ_HtoD + 2181591953U, // FCVTZU_ZPmZ_HtoH + 37777U, // FCVTZU_ZPmZ_HtoS + 21393U, // FCVTZU_ZPmZ_StoD + 37777U, // FCVTZU_ZPmZ_StoS + 100717457U, // FCVTZUd + 100717457U, // FCVTZUh + 100717457U, // FCVTZUs + 2248201105U, // FCVTZUv1f16 + 2248201105U, // FCVTZUv1i32 + 2248201105U, // FCVTZUv1i64 + 68727697U, // FCVTZUv2f32 + 2216735633U, // FCVTZUv2f64 + 2216211345U, // FCVTZUv2i32_shift + 2216735633U, // FCVTZUv2i64_shift + 69776273U, // FCVTZUv4f16 + 2217784209U, // FCVTZUv4f32 + 69776273U, // FCVTZUv4i16_shift + 70300561U, // FCVTZUv4i32_shift + 70824849U, // FCVTZUv8f16 + 2218308497U, // FCVTZUv8i16_shift + 2181591900U, // FCVT_ZPmZ_DtoH + 37724U, // FCVT_ZPmZ_DtoS + 21340U, // FCVT_ZPmZ_HtoD + 37724U, // FCVT_ZPmZ_HtoS + 21340U, // FCVT_ZPmZ_StoD + 2181591900U, // FCVT_ZPmZ_StoH + 100717497U, // FDIVDrr + 100717497U, // FDIVHrr + 302010787U, // FDIVR_ZPmZ_D + 2186310051U, // FDIVR_ZPmZ_H + 302027171U, // FDIVR_ZPmZ_S + 100717497U, // FDIVSrr + 302011321U, // FDIV_ZPmZ_D + 2186310585U, // FDIV_ZPmZ_H + 302027705U, // FDIV_ZPmZ_S + 2216211385U, // FDIVv2f32 + 2216735673U, // FDIVv2f64 + 69776313U, // FDIVv4f16 + 70300601U, // FDIVv4f32 + 2218308537U, // FDIVv8f16 + 838881376U, // FDUP_ZI_D + 9465952U, // FDUP_ZI_H + 838897760U, // FDUP_ZI_S + 2348827371U, // FEXPA_ZZ_D + 608723691U, // FEXPA_ZZ_H + 2415952619U, // FEXPA_ZZ_S + 2248200909U, // FJCVTZS + 100714511U, // FMADDDrrr + 100714511U, // FMADDHrrr + 100714511U, // FMADDSrrr + 302008208U, // FMAD_ZPmZZ_D + 2186307472U, // FMAD_ZPmZZ_H + 302024592U, // FMAD_ZPmZZ_S + 100717911U, // FMAXDrr + 100717911U, // FMAXHrr + 100716219U, // FMAXNMDrr + 100716219U, // FMAXNMHrr + 2216210455U, // FMAXNMPv2f32 + 2216734743U, // FMAXNMPv2f64 + 2214645783U, // FMAXNMPv2i16p + 67162135U, // FMAXNMPv2i32p + 2214645783U, // FMAXNMPv2i64p + 69775383U, // FMAXNMPv4f16 + 70299671U, // FMAXNMPv4f32 + 2218307607U, // FMAXNMPv8f16 + 100716219U, // FMAXNMSrr + 302044132U, // FMAXNMV_VPZ_D + 302044132U, // FMAXNMV_VPZ_H + 302044132U, // FMAXNMV_VPZ_S + 67163108U, // FMAXNMVv4i16v + 2214646756U, // FMAXNMVv4i32v + 67163108U, // FMAXNMVv8i16v + 302010043U, // FMAXNM_ZPmI_D + 2186309307U, // FMAXNM_ZPmI_H + 302026427U, // FMAXNM_ZPmI_S + 302010043U, // FMAXNM_ZPmZ_D + 2186309307U, // FMAXNM_ZPmZ_H + 302026427U, // FMAXNM_ZPmZ_S + 2216210107U, // FMAXNMv2f32 + 2216734395U, // FMAXNMv2f64 + 69775035U, // FMAXNMv4f16 + 70299323U, // FMAXNMv4f32 + 2218307259U, // FMAXNMv8f16 + 2216210546U, // FMAXPv2f32 + 2216734834U, // FMAXPv2f64 + 2214645874U, // FMAXPv2i16p + 67162226U, // FMAXPv2i32p + 2214645874U, // FMAXPv2i64p + 69775474U, // FMAXPv4f16 + 70299762U, // FMAXPv4f32 + 2218307698U, // FMAXPv8f16 + 100717911U, // FMAXSrr + 302044193U, // FMAXV_VPZ_D + 302044193U, // FMAXV_VPZ_H + 302044193U, // FMAXV_VPZ_S + 67163169U, // FMAXVv4i16v + 2214646817U, // FMAXVv4i32v + 67163169U, // FMAXVv8i16v + 302011735U, // FMAX_ZPmI_D + 2186310999U, // FMAX_ZPmI_H + 302028119U, // FMAX_ZPmI_S + 302011735U, // FMAX_ZPmZ_D + 2186310999U, // FMAX_ZPmZ_H + 302028119U, // FMAX_ZPmZ_S + 2216211799U, // FMAXv2f32 + 2216736087U, // FMAXv2f64 + 69776727U, // FMAXv4f16 + 70301015U, // FMAXv4f32 + 2218308951U, // FMAXv8f16 + 100716264U, // FMINDrr + 100716264U, // FMINHrr + 100716211U, // FMINNMDrr + 100716211U, // FMINNMHrr + 2216210446U, // FMINNMPv2f32 + 2216734734U, // FMINNMPv2f64 + 2214645774U, // FMINNMPv2i16p + 67162126U, // FMINNMPv2i32p + 2214645774U, // FMINNMPv2i64p + 69775374U, // FMINNMPv4f16 + 70299662U, // FMINNMPv4f32 + 2218307598U, // FMINNMPv8f16 + 100716211U, // FMINNMSrr + 302044123U, // FMINNMV_VPZ_D + 302044123U, // FMINNMV_VPZ_H + 302044123U, // FMINNMV_VPZ_S + 67163099U, // FMINNMVv4i16v + 2214646747U, // FMINNMVv4i32v + 67163099U, // FMINNMVv8i16v + 302010035U, // FMINNM_ZPmI_D + 2186309299U, // FMINNM_ZPmI_H + 302026419U, // FMINNM_ZPmI_S + 302010035U, // FMINNM_ZPmZ_D + 2186309299U, // FMINNM_ZPmZ_H + 302026419U, // FMINNM_ZPmZ_S + 2216210099U, // FMINNMv2f32 + 2216734387U, // FMINNMv2f64 + 69775027U, // FMINNMv4f16 + 70299315U, // FMINNMv4f32 + 2218307251U, // FMINNMv8f16 + 2216210470U, // FMINPv2f32 + 2216734758U, // FMINPv2f64 + 2214645798U, // FMINPv2i16p + 67162150U, // FMINPv2i32p + 2214645798U, // FMINPv2i64p + 69775398U, // FMINPv4f16 + 70299686U, // FMINPv4f32 + 2218307622U, // FMINPv8f16 + 100716264U, // FMINSrr + 302044141U, // FMINV_VPZ_D + 302044141U, // FMINV_VPZ_H + 302044141U, // FMINV_VPZ_S + 67163117U, // FMINVv4i16v + 2214646765U, // FMINVv4i32v + 67163117U, // FMINVv8i16v + 302010088U, // FMIN_ZPmI_D + 2186309352U, // FMIN_ZPmI_H + 302026472U, // FMIN_ZPmI_S + 302010088U, // FMIN_ZPmZ_D + 2186309352U, // FMIN_ZPmZ_H + 302026472U, // FMIN_ZPmZ_S + 2216210152U, // FMINv2f32 + 2216734440U, // FMINv2f64 + 69775080U, // FMINv4f16 + 70299368U, // FMINv4f32 + 2218307304U, // FMINv8f16 + 302006968U, // FMLA_ZPmZZ_D + 2186306232U, // FMLA_ZPmZZ_H + 302023352U, // FMLA_ZPmZZ_S + 3019915960U, // FMLA_ZZZI_D + 612393656U, // FMLA_ZZZI_H + 2952823480U, // FMLA_ZZZI_S + 369189560U, // FMLAv1i16_indexed + 369189560U, // FMLAv1i32_indexed + 369189560U, // FMLAv1i64_indexed + 2283332280U, // FMLAv2f32 + 2283856568U, // FMLAv2f64 + 2283332280U, // FMLAv2i32_indexed + 2283856568U, // FMLAv2i64_indexed + 136897208U, // FMLAv4f16 + 137421496U, // FMLAv4f32 + 136897208U, // FMLAv4i16_indexed + 137421496U, // FMLAv4i32_indexed + 2285429432U, // FMLAv8f16 + 2285429432U, // FMLAv8i16_indexed + 302010962U, // FMLS_ZPmZZ_D + 2186310226U, // FMLS_ZPmZZ_H + 302027346U, // FMLS_ZPmZZ_S + 3019919954U, // FMLS_ZZZI_D + 612397650U, // FMLS_ZZZI_H + 2952827474U, // FMLS_ZZZI_S + 369193554U, // FMLSv1i16_indexed + 369193554U, // FMLSv1i32_indexed + 369193554U, // FMLSv1i64_indexed + 2283336274U, // FMLSv2f32 + 2283860562U, // FMLSv2f64 + 2283336274U, // FMLSv2i32_indexed + 2283860562U, // FMLSv2i64_indexed + 136901202U, // FMLSv4f16 + 137425490U, // FMLSv4f32 + 136901202U, // FMLSv4i16_indexed + 137425490U, // FMLSv4i32_indexed + 2285433426U, // FMLSv8f16 + 2285433426U, // FMLSv8i16_indexed + 0U, // FMOVD0 + 67163145U, // FMOVDXHighr + 2248201225U, // FMOVDXr + 838915081U, // FMOVDi + 2248201225U, // FMOVDr + 0U, // FMOVH0 + 2248201225U, // FMOVHWr + 2248201225U, // FMOVHXr + 838915081U, // FMOVHi + 2248201225U, // FMOVHr + 0U, // FMOVS0 + 2248201225U, // FMOVSWr + 838915081U, // FMOVSi + 2248201225U, // FMOVSr + 2248201225U, // FMOVWHr + 2248201225U, // FMOVWSr + 2258154505U, // FMOVXDHighr + 2248201225U, // FMOVXDr + 2248201225U, // FMOVXHr + 840479753U, // FMOVv2f32_ns + 841004041U, // FMOVv2f64_ns + 841528329U, // FMOVv4f16_ns + 842052617U, // FMOVv4f32_ns + 842576905U, // FMOVv8f16_ns + 302007876U, // FMSB_ZPmZZ_D + 2186307140U, // FMSB_ZPmZZ_H + 302024260U, // FMSB_ZPmZZ_S + 100714165U, // FMSUBDrrr + 100714165U, // FMSUBHrrr + 100714165U, // FMSUBSrrr + 100716128U, // FMULDrr + 100716128U, // FMULHrr + 100716128U, // FMULSrr + 100717970U, // FMULX16 + 100717970U, // FMULX32 + 100717970U, // FMULX64 + 302011794U, // FMULX_ZPmZ_D + 2186311058U, // FMULX_ZPmZ_H + 302028178U, // FMULX_ZPmZ_S + 100717970U, // FMULXv1i16_indexed + 100717970U, // FMULXv1i32_indexed + 100717970U, // FMULXv1i64_indexed + 2216211858U, // FMULXv2f32 + 2216736146U, // FMULXv2f64 + 2216211858U, // FMULXv2i32_indexed + 2216736146U, // FMULXv2i64_indexed + 69776786U, // FMULXv4f16 + 70301074U, // FMULXv4f32 + 69776786U, // FMULXv4i16_indexed + 70301074U, // FMULXv4i32_indexed + 2218309010U, // FMULXv8f16 + 2218309010U, // FMULXv8i16_indexed + 302009952U, // FMUL_ZPmI_D + 2186309216U, // FMUL_ZPmI_H + 302026336U, // FMUL_ZPmI_S + 302009952U, // FMUL_ZPmZ_D + 2186309216U, // FMUL_ZPmZ_H + 302026336U, // FMUL_ZPmZ_S + 201346656U, // FMUL_ZZZI_D + 2387111520U, // FMUL_ZZZI_H + 268471904U, // FMUL_ZZZI_S + 201346656U, // FMUL_ZZZ_D + 2387111520U, // FMUL_ZZZ_H + 268471904U, // FMUL_ZZZ_S + 100716128U, // FMULv1i16_indexed + 100716128U, // FMULv1i32_indexed + 100716128U, // FMULv1i64_indexed + 2216210016U, // FMULv2f32 + 2216734304U, // FMULv2f64 + 2216210016U, // FMULv2i32_indexed + 2216734304U, // FMULv2i64_indexed + 69774944U, // FMULv4f16 + 70299232U, // FMULv4f32 + 69774944U, // FMULv4i16_indexed + 70299232U, // FMULv4i32_indexed + 2218307168U, // FMULv8f16 + 2218307168U, // FMULv8i16_indexed + 2248198419U, // FNEGDr + 2248198419U, // FNEGHr + 2248198419U, // FNEGSr + 18707U, // FNEG_ZPmZ_D + 2181589267U, // FNEG_ZPmZ_H + 35091U, // FNEG_ZPmZ_S + 68725011U, // FNEGv2f32 + 2216732947U, // FNEGv2f64 + 69773587U, // FNEGv4f16 + 2217781523U, // FNEGv4f32 + 70822163U, // FNEGv8f16 + 100714518U, // FNMADDDrrr + 100714518U, // FNMADDHrrr + 100714518U, // FNMADDSrrr + 302008214U, // FNMAD_ZPmZZ_D + 2186307478U, // FNMAD_ZPmZZ_H + 302024598U, // FNMAD_ZPmZZ_S + 302006974U, // FNMLA_ZPmZZ_D + 2186306238U, // FNMLA_ZPmZZ_H + 302023358U, // FNMLA_ZPmZZ_S + 302010968U, // FNMLS_ZPmZZ_D + 2186310232U, // FNMLS_ZPmZZ_H + 302027352U, // FNMLS_ZPmZZ_S + 302007882U, // FNMSB_ZPmZZ_D + 2186307146U, // FNMSB_ZPmZZ_H + 302024266U, // FNMSB_ZPmZZ_S + 100714172U, // FNMSUBDrrr + 100714172U, // FNMSUBHrrr + 100714172U, // FNMSUBSrrr + 100716134U, // FNMULDrr + 100716134U, // FNMULHrr + 100716134U, // FNMULSrr + 2348828852U, // FRECPE_ZZ_D + 608725172U, // FRECPE_ZZ_H + 2415954100U, // FRECPE_ZZ_S + 2248198324U, // FRECPEv1f16 + 2248198324U, // FRECPEv1i32 + 2248198324U, // FRECPEv1i64 + 68724916U, // FRECPEv2f32 + 2216732852U, // FRECPEv2f64 + 69773492U, // FRECPEv4f16 + 2217781428U, // FRECPEv4f32 + 70822068U, // FRECPEv8f16 + 100717192U, // FRECPS16 + 100717192U, // FRECPS32 + 100717192U, // FRECPS64 + 201347720U, // FRECPS_ZZZ_D + 2387112584U, // FRECPS_ZZZ_H + 268472968U, // FRECPS_ZZZ_S + 2216211080U, // FRECPSv2f32 + 2216735368U, // FRECPSv2f64 + 69776008U, // FRECPSv4f16 + 70300296U, // FRECPSv4f32 + 2218308232U, // FRECPSv8f16 + 21913U, // FRECPX_ZPmZ_D + 2181592473U, // FRECPX_ZPmZ_H + 38297U, // FRECPX_ZPmZ_S + 2248201625U, // FRECPXv1f16 + 2248201625U, // FRECPXv1i32 + 2248201625U, // FRECPXv1i64 + 2248196906U, // FRINTADr + 2248196906U, // FRINTAHr + 2248196906U, // FRINTASr + 17194U, // FRINTA_ZPmZ_D + 2181587754U, // FRINTA_ZPmZ_H + 33578U, // FRINTA_ZPmZ_S + 68723498U, // FRINTAv2f32 + 2216731434U, // FRINTAv2f64 + 69772074U, // FRINTAv4f16 + 2217780010U, // FRINTAv4f32 + 70820650U, // FRINTAv8f16 + 2248199305U, // FRINTIDr + 2248199305U, // FRINTIHr + 2248199305U, // FRINTISr + 19593U, // FRINTI_ZPmZ_D + 2181590153U, // FRINTI_ZPmZ_H + 35977U, // FRINTI_ZPmZ_S + 68725897U, // FRINTIv2f32 + 2216733833U, // FRINTIv2f64 + 69774473U, // FRINTIv4f16 + 2217782409U, // FRINTIv4f32 + 70823049U, // FRINTIv8f16 + 2248199881U, // FRINTMDr + 2248199881U, // FRINTMHr + 2248199881U, // FRINTMSr + 20169U, // FRINTM_ZPmZ_D + 2181590729U, // FRINTM_ZPmZ_H + 36553U, // FRINTM_ZPmZ_S + 68726473U, // FRINTMv2f32 + 2216734409U, // FRINTMv2f64 + 69775049U, // FRINTMv4f16 + 2217782985U, // FRINTMv4f32 + 70823625U, // FRINTMv8f16 + 2248199990U, // FRINTNDr + 2248199990U, // FRINTNHr + 2248199990U, // FRINTNSr + 20278U, // FRINTN_ZPmZ_D + 2181590838U, // FRINTN_ZPmZ_H + 36662U, // FRINTN_ZPmZ_S + 68726582U, // FRINTNv2f32 + 2216734518U, // FRINTNv2f64 + 69775158U, // FRINTNv4f16 + 2217783094U, // FRINTNv4f32 + 70823734U, // FRINTNv8f16 + 2248200275U, // FRINTPDr + 2248200275U, // FRINTPHr + 2248200275U, // FRINTPSr + 20563U, // FRINTP_ZPmZ_D + 2181591123U, // FRINTP_ZPmZ_H + 36947U, // FRINTP_ZPmZ_S + 68726867U, // FRINTPv2f32 + 2216734803U, // FRINTPv2f64 + 69775443U, // FRINTPv4f16 + 2217783379U, // FRINTPv4f32 + 70824019U, // FRINTPv8f16 + 2248201633U, // FRINTXDr + 2248201633U, // FRINTXHr + 2248201633U, // FRINTXSr + 21921U, // FRINTX_ZPmZ_D + 2181592481U, // FRINTX_ZPmZ_H + 38305U, // FRINTX_ZPmZ_S + 68728225U, // FRINTXv2f32 + 2216736161U, // FRINTXv2f64 + 69776801U, // FRINTXv4f16 + 2217784737U, // FRINTXv4f32 + 70825377U, // FRINTXv8f16 + 2248201713U, // FRINTZDr + 2248201713U, // FRINTZHr + 2248201713U, // FRINTZSr + 22001U, // FRINTZ_ZPmZ_D + 2181592561U, // FRINTZ_ZPmZ_H + 38385U, // FRINTZ_ZPmZ_S + 68728305U, // FRINTZv2f32 + 2216736241U, // FRINTZv2f64 + 69776881U, // FRINTZv4f16 + 2217784817U, // FRINTZv4f32 + 70825457U, // FRINTZv8f16 + 2348828897U, // FRSQRTE_ZZ_D + 608725217U, // FRSQRTE_ZZ_H + 2415954145U, // FRSQRTE_ZZ_S + 2248198369U, // FRSQRTEv1f16 + 2248198369U, // FRSQRTEv1i32 + 2248198369U, // FRSQRTEv1i64 + 68724961U, // FRSQRTEv2f32 + 2216732897U, // FRSQRTEv2f64 + 69773537U, // FRSQRTEv4f16 + 2217781473U, // FRSQRTEv4f32 + 70822113U, // FRSQRTEv8f16 + 100717239U, // FRSQRTS16 + 100717239U, // FRSQRTS32 + 100717239U, // FRSQRTS64 + 201347767U, // FRSQRTS_ZZZ_D + 2387112631U, // FRSQRTS_ZZZ_H + 268473015U, // FRSQRTS_ZZZ_S + 2216211127U, // FRSQRTSv2f32 + 2216735415U, // FRSQRTSv2f64 + 69776055U, // FRSQRTSv4f16 + 70300343U, // FRSQRTSv4f32 + 2218308279U, // FRSQRTSv8f16 + 302008446U, // FSCALE_ZPmZ_D + 2186307710U, // FSCALE_ZPmZ_H + 302024830U, // FSCALE_ZPmZ_S + 2248201023U, // FSQRTDr + 2248201023U, // FSQRTHr + 2248201023U, // FSQRTSr + 21311U, // FSQRT_ZPmZ_D + 2181591871U, // FSQRT_ZPmZ_H + 37695U, // FSQRT_ZPmZ_S + 68727615U, // FSQRTv2f32 + 2216735551U, // FSQRTv2f64 + 69776191U, // FSQRTv4f16 + 2217784127U, // FSQRTv4f32 + 70824767U, // FSQRTv8f16 + 100714145U, // FSUBDrr + 100714145U, // FSUBHrr + 302010587U, // FSUBR_ZPmI_D + 2186309851U, // FSUBR_ZPmI_H + 302026971U, // FSUBR_ZPmI_S + 302010587U, // FSUBR_ZPmZ_D + 2186309851U, // FSUBR_ZPmZ_H + 302026971U, // FSUBR_ZPmZ_S + 100714145U, // FSUBSrr + 302007969U, // FSUB_ZPmI_D + 2186307233U, // FSUB_ZPmI_H + 302024353U, // FSUB_ZPmI_S + 302007969U, // FSUB_ZPmZ_D + 2186307233U, // FSUB_ZPmZ_H + 302024353U, // FSUB_ZPmZ_S + 201344673U, // FSUB_ZZZ_D + 2387109537U, // FSUB_ZZZ_H + 268469921U, // FSUB_ZZZ_S + 2216208033U, // FSUBv2f32 + 2216732321U, // FSUBv2f64 + 69772961U, // FSUBv4f16 + 70297249U, // FSUBv4f32 + 2218305185U, // FSUBv8f16 + 201344925U, // FTMAD_ZZI_D + 2387109789U, // FTMAD_ZZI_H + 268470173U, // FTMAD_ZZI_S + 201346675U, // FTSMUL_ZZZ_D + 2387111539U, // FTSMUL_ZZZ_H + 268471923U, // FTSMUL_ZZZ_S + 201346439U, // FTSSEL_ZZZ_D + 2387111303U, // FTSSEL_ZZZ_H + 268471687U, // FTSSEL_ZZZ_S + 883032940U, // GLD1B_D_IMM_REAL + 379716460U, // GLD1B_D_REAL + 379716460U, // GLD1B_D_SXTW_REAL + 379716460U, // GLD1B_D_UXTW_REAL + 815932268U, // GLD1B_S_IMM_REAL + 379724652U, // GLD1B_S_SXTW_REAL + 379724652U, // GLD1B_S_UXTW_REAL + 883033920U, // GLD1D_IMM_REAL + 379717440U, // GLD1D_REAL + 379717440U, // GLD1D_SCALED_REAL + 379717440U, // GLD1D_SXTW_REAL + 379717440U, // GLD1D_SXTW_SCALED_REAL + 379717440U, // GLD1D_UXTW_REAL + 379717440U, // GLD1D_UXTW_SCALED_REAL + 3030518062U, // GLD1H_D_IMM_REAL + 379717934U, // GLD1H_D_REAL + 379717934U, // GLD1H_D_SCALED_REAL + 379717934U, // GLD1H_D_SXTW_REAL + 379717934U, // GLD1H_D_SXTW_SCALED_REAL + 379717934U, // GLD1H_D_UXTW_REAL + 379717934U, // GLD1H_D_UXTW_SCALED_REAL + 2963417390U, // GLD1H_S_IMM_REAL + 379726126U, // GLD1H_S_SXTW_REAL + 379726126U, // GLD1H_S_SXTW_SCALED_REAL + 379726126U, // GLD1H_S_UXTW_REAL + 379726126U, // GLD1H_S_UXTW_SCALED_REAL + 883033627U, // GLD1SB_D_IMM_REAL + 379717147U, // GLD1SB_D_REAL + 379717147U, // GLD1SB_D_SXTW_REAL + 379717147U, // GLD1SB_D_UXTW_REAL + 815932955U, // GLD1SB_S_IMM_REAL + 379725339U, // GLD1SB_S_SXTW_REAL + 379725339U, // GLD1SB_S_UXTW_REAL + 3030518726U, // GLD1SH_D_IMM_REAL + 379718598U, // GLD1SH_D_REAL + 379718598U, // GLD1SH_D_SCALED_REAL + 379718598U, // GLD1SH_D_SXTW_REAL + 379718598U, // GLD1SH_D_SXTW_SCALED_REAL + 379718598U, // GLD1SH_D_UXTW_REAL + 379718598U, // GLD1SH_D_UXTW_SCALED_REAL + 2963418054U, // GLD1SH_S_IMM_REAL + 379726790U, // GLD1SH_S_SXTW_REAL + 379726790U, // GLD1SH_S_SXTW_SCALED_REAL + 379726790U, // GLD1SH_S_UXTW_REAL + 379726790U, // GLD1SH_S_UXTW_SCALED_REAL + 883037416U, // GLD1SW_D_IMM_REAL + 379720936U, // GLD1SW_D_REAL + 379720936U, // GLD1SW_D_SCALED_REAL + 379720936U, // GLD1SW_D_SXTW_REAL + 379720936U, // GLD1SW_D_SXTW_SCALED_REAL + 379720936U, // GLD1SW_D_UXTW_REAL + 379720936U, // GLD1SW_D_UXTW_SCALED_REAL + 883037238U, // GLD1W_D_IMM_REAL + 379720758U, // GLD1W_D_REAL + 379720758U, // GLD1W_D_SCALED_REAL + 379720758U, // GLD1W_D_SXTW_REAL + 379720758U, // GLD1W_D_SXTW_SCALED_REAL + 379720758U, // GLD1W_D_UXTW_REAL + 379720758U, // GLD1W_D_UXTW_SCALED_REAL + 815936566U, // GLD1W_IMM_REAL + 379728950U, // GLD1W_SXTW_REAL + 379728950U, // GLD1W_SXTW_SCALED_REAL + 379728950U, // GLD1W_UXTW_REAL + 379728950U, // GLD1W_UXTW_SCALED_REAL + 883032946U, // GLDFF1B_D_IMM_REAL + 379716466U, // GLDFF1B_D_REAL + 379716466U, // GLDFF1B_D_SXTW_REAL + 379716466U, // GLDFF1B_D_UXTW_REAL + 815932274U, // GLDFF1B_S_IMM_REAL + 379724658U, // GLDFF1B_S_SXTW_REAL + 379724658U, // GLDFF1B_S_UXTW_REAL + 883033926U, // GLDFF1D_IMM_REAL + 379717446U, // GLDFF1D_REAL + 379717446U, // GLDFF1D_SCALED_REAL + 379717446U, // GLDFF1D_SXTW_REAL + 379717446U, // GLDFF1D_SXTW_SCALED_REAL + 379717446U, // GLDFF1D_UXTW_REAL + 379717446U, // GLDFF1D_UXTW_SCALED_REAL + 3030518068U, // GLDFF1H_D_IMM_REAL + 379717940U, // GLDFF1H_D_REAL + 379717940U, // GLDFF1H_D_SCALED_REAL + 379717940U, // GLDFF1H_D_SXTW_REAL + 379717940U, // GLDFF1H_D_SXTW_SCALED_REAL + 379717940U, // GLDFF1H_D_UXTW_REAL + 379717940U, // GLDFF1H_D_UXTW_SCALED_REAL + 2963417396U, // GLDFF1H_S_IMM_REAL + 379726132U, // GLDFF1H_S_SXTW_REAL + 379726132U, // GLDFF1H_S_SXTW_SCALED_REAL + 379726132U, // GLDFF1H_S_UXTW_REAL + 379726132U, // GLDFF1H_S_UXTW_SCALED_REAL + 883033634U, // GLDFF1SB_D_IMM_REAL + 379717154U, // GLDFF1SB_D_REAL + 379717154U, // GLDFF1SB_D_SXTW_REAL + 379717154U, // GLDFF1SB_D_UXTW_REAL + 815932962U, // GLDFF1SB_S_IMM_REAL + 379725346U, // GLDFF1SB_S_SXTW_REAL + 379725346U, // GLDFF1SB_S_UXTW_REAL + 3030518733U, // GLDFF1SH_D_IMM_REAL + 379718605U, // GLDFF1SH_D_REAL + 379718605U, // GLDFF1SH_D_SCALED_REAL + 379718605U, // GLDFF1SH_D_SXTW_REAL + 379718605U, // GLDFF1SH_D_SXTW_SCALED_REAL + 379718605U, // GLDFF1SH_D_UXTW_REAL + 379718605U, // GLDFF1SH_D_UXTW_SCALED_REAL + 2963418061U, // GLDFF1SH_S_IMM_REAL + 379726797U, // GLDFF1SH_S_SXTW_REAL + 379726797U, // GLDFF1SH_S_SXTW_SCALED_REAL + 379726797U, // GLDFF1SH_S_UXTW_REAL + 379726797U, // GLDFF1SH_S_UXTW_SCALED_REAL + 883037423U, // GLDFF1SW_D_IMM_REAL + 379720943U, // GLDFF1SW_D_REAL + 379720943U, // GLDFF1SW_D_SCALED_REAL + 379720943U, // GLDFF1SW_D_SXTW_REAL + 379720943U, // GLDFF1SW_D_SXTW_SCALED_REAL + 379720943U, // GLDFF1SW_D_UXTW_REAL + 379720943U, // GLDFF1SW_D_UXTW_SCALED_REAL + 883037244U, // GLDFF1W_D_IMM_REAL + 379720764U, // GLDFF1W_D_REAL + 379720764U, // GLDFF1W_D_SCALED_REAL + 379720764U, // GLDFF1W_D_SXTW_REAL + 379720764U, // GLDFF1W_D_SXTW_SCALED_REAL + 379720764U, // GLDFF1W_D_UXTW_REAL + 379720764U, // GLDFF1W_D_UXTW_SCALED_REAL + 815936572U, // GLDFF1W_IMM_REAL + 379728956U, // GLDFF1W_SXTW_REAL + 379728956U, // GLDFF1W_SXTW_SCALED_REAL + 379728956U, // GLDFF1W_UXTW_REAL + 379728956U, // GLDFF1W_UXTW_SCALED_REAL + 152359U, // HINT + 78607U, // HLT + 75574U, // HVC + 536921183U, // INCB_XPiI + 536922063U, // INCD_XPiI + 536889295U, // INCD_ZPiI + 536922647U, // INCH_XPiI + 6842903U, // INCH_ZPiI + 2315308999U, // INCP_XP_B + 2348863431U, // INCP_XP_D + 2717962183U, // INCP_XP_H + 2415972295U, // INCP_XP_S + 2147504071U, // INCP_ZP_D + 604532679U, // INCP_ZP_H + 2147520455U, // INCP_ZP_S + 536925367U, // INCW_XPiI + 536908983U, // INCW_ZPiI + 100676987U, // INDEX_II_B + 100685179U, // INDEX_II_D + 242775419U, // INDEX_II_H + 100701563U, // INDEX_II_S + 100676987U, // INDEX_IR_B + 100685179U, // INDEX_IR_D + 242775419U, // INDEX_IR_H + 100701563U, // INDEX_IR_S + 100676987U, // INDEX_RI_B + 100685179U, // INDEX_RI_D + 242775419U, // INDEX_RI_H + 100701563U, // INDEX_RI_S + 100676987U, // INDEX_RR_B + 100685179U, // INDEX_RR_D + 242775419U, // INDEX_RR_H + 100701563U, // INDEX_RR_S + 2516595051U, // INSR_ZR_B + 2516603243U, // INSR_ZR_D + 615018859U, // INSR_ZR_H + 2516619627U, // INSR_ZR_S + 2516595051U, // INSR_ZV_B + 2516603243U, // INSR_ZV_D + 615018859U, // INSR_ZV_H + 2516619627U, // INSR_ZV_S + 3065049710U, // INSvi16gpr + 951120494U, // INSvi16lane + 3065573998U, // INSvi32gpr + 3099128430U, // INSvi32lane + 3063476846U, // INSvi64gpr + 949547630U, // INSvi64lane + 3066098286U, // INSvi8gpr + 3099652718U, // INSvi8lane + 116287U, // ISB + 302039859U, // LASTA_RPZ_B + 302039859U, // LASTA_RPZ_D + 302039859U, // LASTA_RPZ_H + 302039859U, // LASTA_RPZ_S + 302039859U, // LASTA_VPZ_B + 302039859U, // LASTA_VPZ_D + 302039859U, // LASTA_VPZ_H + 302039859U, // LASTA_VPZ_S + 302040718U, // LASTB_RPZ_B + 302040718U, // LASTB_RPZ_D + 302040718U, // LASTB_RPZ_H + 302040718U, // LASTB_RPZ_S + 302040718U, // LASTB_VPZ_B + 302040718U, // LASTB_VPZ_D + 302040718U, // LASTB_VPZ_H + 302040718U, // LASTB_VPZ_S + 379741036U, // LD1B + 379716460U, // LD1B_D + 379716460U, // LD1B_D_IMM_REAL + 379749228U, // LD1B_H + 379749228U, // LD1B_H_IMM_REAL + 379741036U, // LD1B_IMM_REAL + 379724652U, // LD1B_S + 379724652U, // LD1B_S_IMM_REAL + 379717440U, // LD1D + 379717440U, // LD1D_IMM_REAL + 172064U, // LD1Fourv16b + 13287456U, // LD1Fourv16b_POST + 188448U, // LD1Fourv1d + 13828128U, // LD1Fourv1d_POST + 204832U, // LD1Fourv2d + 13320224U, // LD1Fourv2d_POST + 221216U, // LD1Fourv2s + 13860896U, // LD1Fourv2s_POST + 237600U, // LD1Fourv4h + 13877280U, // LD1Fourv4h_POST + 253984U, // LD1Fourv4s + 13369376U, // LD1Fourv4s_POST + 270368U, // LD1Fourv8b + 13910048U, // LD1Fourv8b_POST + 286752U, // LD1Fourv8h + 13402144U, // LD1Fourv8h_POST + 379750702U, // LD1H + 379717934U, // LD1H_D + 379717934U, // LD1H_D_IMM_REAL + 379750702U, // LD1H_IMM_REAL + 379726126U, // LD1H_S + 379726126U, // LD1H_S_IMM_REAL + 172064U, // LD1Onev16b + 14336032U, // LD1Onev16b_POST + 188448U, // LD1Onev1d + 14876704U, // LD1Onev1d_POST + 204832U, // LD1Onev2d + 14368800U, // LD1Onev2d_POST + 221216U, // LD1Onev2s + 14909472U, // LD1Onev2s_POST + 237600U, // LD1Onev4h + 14925856U, // LD1Onev4h_POST + 253984U, // LD1Onev4s + 14417952U, // LD1Onev4s_POST + 270368U, // LD1Onev8b + 14958624U, // LD1Onev8b_POST + 286752U, // LD1Onev8h + 14450720U, // LD1Onev8h_POST + 379716999U, // LD1RB_D_IMM + 379749767U, // LD1RB_H_IMM + 379741575U, // LD1RB_IMM + 379725191U, // LD1RB_S_IMM + 379717698U, // LD1RD_IMM + 379718450U, // LD1RH_D_IMM + 379751218U, // LD1RH_IMM + 379726642U, // LD1RH_S_IMM + 379741567U, // LD1RQ_B + 379741567U, // LD1RQ_B_IMM + 379717690U, // LD1RQ_D + 379717690U, // LD1RQ_D_IMM + 379751210U, // LD1RQ_H + 379751210U, // LD1RQ_H_IMM + 379729113U, // LD1RQ_W + 379729113U, // LD1RQ_W_IMM + 379717201U, // LD1RSB_D_IMM + 379749969U, // LD1RSB_H_IMM + 379725393U, // LD1RSB_S_IMM + 379718639U, // LD1RSH_D_IMM + 379726831U, // LD1RSH_S_IMM + 379720968U, // LD1RSW_IMM + 379720929U, // LD1RW_D_IMM + 379729121U, // LD1RW_IMM + 176305U, // LD1Rv16b + 15388849U, // LD1Rv16b_POST + 192689U, // LD1Rv1d + 14880945U, // LD1Rv1d_POST + 209073U, // LD1Rv2d + 14897329U, // LD1Rv2d_POST + 225457U, // LD1Rv2s + 15962289U, // LD1Rv2s_POST + 241841U, // LD1Rv4h + 16502961U, // LD1Rv4h_POST + 258225U, // LD1Rv4s + 15995057U, // LD1Rv4s_POST + 274609U, // LD1Rv8b + 15487153U, // LD1Rv8b_POST + 290993U, // LD1Rv8h + 16552113U, // LD1Rv8h_POST + 379717147U, // LD1SB_D + 379717147U, // LD1SB_D_IMM_REAL + 379749915U, // LD1SB_H + 379749915U, // LD1SB_H_IMM_REAL + 379725339U, // LD1SB_S + 379725339U, // LD1SB_S_IMM_REAL + 379718598U, // LD1SH_D + 379718598U, // LD1SH_D_IMM_REAL + 379726790U, // LD1SH_S + 379726790U, // LD1SH_S_IMM_REAL + 379720936U, // LD1SW_D + 379720936U, // LD1SW_D_IMM_REAL + 172064U, // LD1Threev16b + 16957472U, // LD1Threev16b_POST + 188448U, // LD1Threev1d + 17498144U, // LD1Threev1d_POST + 204832U, // LD1Threev2d + 16990240U, // LD1Threev2d_POST + 221216U, // LD1Threev2s + 17530912U, // LD1Threev2s_POST + 237600U, // LD1Threev4h + 17547296U, // LD1Threev4h_POST + 253984U, // LD1Threev4s + 17039392U, // LD1Threev4s_POST + 270368U, // LD1Threev8b + 17580064U, // LD1Threev8b_POST + 286752U, // LD1Threev8h + 17072160U, // LD1Threev8h_POST + 172064U, // LD1Twov16b + 13811744U, // LD1Twov16b_POST + 188448U, // LD1Twov1d + 14352416U, // LD1Twov1d_POST + 204832U, // LD1Twov2d + 13844512U, // LD1Twov2d_POST + 221216U, // LD1Twov2s + 14385184U, // LD1Twov2s_POST + 237600U, // LD1Twov4h + 14401568U, // LD1Twov4h_POST + 253984U, // LD1Twov4s + 13893664U, // LD1Twov4s_POST + 270368U, // LD1Twov8b + 14434336U, // LD1Twov8b_POST + 286752U, // LD1Twov8h + 13926432U, // LD1Twov8h_POST + 379728950U, // LD1W + 379720758U, // LD1W_D + 379720758U, // LD1W_D_IMM_REAL + 379728950U, // LD1W_IMM_REAL + 18128928U, // LD1i16 + 18661408U, // LD1i16_POST + 18145312U, // LD1i32 + 19202080U, // LD1i32_POST + 18161696U, // LD1i64 + 19742752U, // LD1i64_POST + 18178080U, // LD1i8 + 20283424U, // LD1i8_POST + 379741097U, // LD2B + 379741097U, // LD2B_IMM + 379717484U, // LD2D + 379717484U, // LD2D_IMM + 379750763U, // LD2H + 379750763U, // LD2H_IMM + 176311U, // LD2Rv16b + 16437431U, // LD2Rv16b_POST + 192695U, // LD2Rv1d + 14356663U, // LD2Rv1d_POST + 209079U, // LD2Rv2d + 14373047U, // LD2Rv2d_POST + 225463U, // LD2Rv2s + 14913719U, // LD2Rv2s_POST + 241847U, // LD2Rv4h + 15978679U, // LD2Rv4h_POST + 258231U, // LD2Rv4s + 14946487U, // LD2Rv4s_POST + 274615U, // LD2Rv8b + 16535735U, // LD2Rv8b_POST + 290999U, // LD2Rv8h + 16027831U, // LD2Rv8h_POST + 172162U, // LD2Twov16b + 13811842U, // LD2Twov16b_POST + 204930U, // LD2Twov2d + 13844610U, // LD2Twov2d_POST + 221314U, // LD2Twov2s + 14385282U, // LD2Twov2s_POST + 237698U, // LD2Twov4h + 14401666U, // LD2Twov4h_POST + 254082U, // LD2Twov4s + 13893762U, // LD2Twov4s_POST + 270466U, // LD2Twov8b + 14434434U, // LD2Twov8b_POST + 286850U, // LD2Twov8h + 13926530U, // LD2Twov8h_POST + 379729002U, // LD2W + 379729002U, // LD2W_IMM + 18129026U, // LD2i16 + 19185794U, // LD2i16_POST + 18145410U, // LD2i32 + 19726466U, // LD2i32_POST + 18161794U, // LD2i64 + 20791426U, // LD2i64_POST + 18178178U, // LD2i8 + 18710658U, // LD2i8_POST + 379741118U, // LD3B + 379741118U, // LD3B_IMM + 379717496U, // LD3D + 379717496U, // LD3D_IMM + 379750775U, // LD3H + 379750775U, // LD3H_IMM + 176317U, // LD3Rv16b + 21156029U, // LD3Rv16b_POST + 192701U, // LD3Rv1d + 17502397U, // LD3Rv1d_POST + 209085U, // LD3Rv2d + 17518781U, // LD3Rv2d_POST + 225469U, // LD3Rv2s + 21729469U, // LD3Rv2s_POST + 241853U, // LD3Rv4h + 22270141U, // LD3Rv4h_POST + 258237U, // LD3Rv4s + 21762237U, // LD3Rv4s_POST + 274621U, // LD3Rv8b + 21254333U, // LD3Rv8b_POST + 291005U, // LD3Rv8h + 22319293U, // LD3Rv8h_POST + 172553U, // LD3Threev16b + 16957961U, // LD3Threev16b_POST + 205321U, // LD3Threev2d + 16990729U, // LD3Threev2d_POST + 221705U, // LD3Threev2s + 17531401U, // LD3Threev2s_POST + 238089U, // LD3Threev4h + 17547785U, // LD3Threev4h_POST + 254473U, // LD3Threev4s + 17039881U, // LD3Threev4s_POST + 270857U, // LD3Threev8b + 17580553U, // LD3Threev8b_POST + 287241U, // LD3Threev8h + 17072649U, // LD3Threev8h_POST + 379729014U, // LD3W + 379729014U, // LD3W_IMM + 18129417U, // LD3i16 + 22856201U, // LD3i16_POST + 18145801U, // LD3i32 + 23396873U, // LD3i32_POST + 18162185U, // LD3i64 + 23937545U, // LD3i64_POST + 18178569U, // LD3i8 + 24478217U, // LD3i8_POST + 379741130U, // LD4B + 379741130U, // LD4B_IMM + 379717508U, // LD4D + 379717508U, // LD4D_IMM + 172583U, // LD4Fourv16b + 13287975U, // LD4Fourv16b_POST + 205351U, // LD4Fourv2d + 13320743U, // LD4Fourv2d_POST + 221735U, // LD4Fourv2s + 13861415U, // LD4Fourv2s_POST + 238119U, // LD4Fourv4h + 13877799U, // LD4Fourv4h_POST + 254503U, // LD4Fourv4s + 13369895U, // LD4Fourv4s_POST + 270887U, // LD4Fourv8b + 13910567U, // LD4Fourv8b_POST + 287271U, // LD4Fourv8h + 13402663U, // LD4Fourv8h_POST + 379750787U, // LD4H + 379750787U, // LD4H_IMM + 176323U, // LD4Rv16b + 15913155U, // LD4Rv16b_POST + 192707U, // LD4Rv1d + 13832387U, // LD4Rv1d_POST + 209091U, // LD4Rv2d + 13848771U, // LD4Rv2d_POST + 225475U, // LD4Rv2s + 14389443U, // LD4Rv2s_POST + 241859U, // LD4Rv4h + 14930115U, // LD4Rv4h_POST + 258243U, // LD4Rv4s + 14422211U, // LD4Rv4s_POST + 274627U, // LD4Rv8b + 16011459U, // LD4Rv8b_POST + 291011U, // LD4Rv8h + 14979267U, // LD4Rv8h_POST + 379729026U, // LD4W + 379729026U, // LD4W_IMM + 18129447U, // LD4i16 + 19710503U, // LD4i16_POST + 18145831U, // LD4i32 + 20775463U, // LD4i32_POST + 18162215U, // LD4i64 + 24986151U, // LD4i64_POST + 18178599U, // LD4i8 + 19235367U, // LD4i8_POST + 973169622U, // LDADDAB + 973171096U, // LDADDAH + 973169821U, // LDADDALB + 973171251U, // LDADDALH + 973171888U, // LDADDALW + 973171888U, // LDADDALX + 973169280U, // LDADDAW + 973169280U, // LDADDAX + 973169780U, // LDADDB + 973171237U, // LDADDH + 973169921U, // LDADDLB + 973171351U, // LDADDLH + 973172058U, // LDADDLW + 973172058U, // LDADDLX + 973170660U, // LDADDW + 973170660U, // LDADDX + 2253964738U, // LDAPRB + 2253966189U, // LDAPRH + 2253967684U, // LDAPRW + 2253967684U, // LDAPRX + 106481133U, // LDAPURBi + 106482584U, // LDAPURHi + 106481264U, // LDAPURSBWi + 106481264U, // LDAPURSBXi + 106482702U, // LDAPURSHWi + 106482702U, // LDAPURSHXi + 106485031U, // LDAPURSWi + 106484117U, // LDAPURXi + 106484117U, // LDAPURi + 2253964686U, // LDARB + 2253966137U, // LDARH + 2253967561U, // LDARW + 2253967561U, // LDARX + 2248200299U, // LDAXPW + 2248200299U, // LDAXPX + 2253964797U, // LDAXRB + 2253966248U, // LDAXRH + 2253967800U, // LDAXRW + 2253967800U, // LDAXRX + 973169678U, // LDCLRAB + 973171142U, // LDCLRAH + 973169861U, // LDCLRALB + 973171291U, // LDCLRALH + 973171955U, // LDCLRALW + 973171955U, // LDCLRALX + 973169394U, // LDCLRAW + 973169394U, // LDCLRAX + 973170083U, // LDCLRB + 973171534U, // LDCLRH + 973169957U, // LDCLRLB + 973171387U, // LDCLRLH + 973172249U, // LDCLRLW + 973172249U, // LDCLRLX + 973173017U, // LDCLRW + 973173017U, // LDCLRX + 973169687U, // LDEORAB + 973171151U, // LDEORAH + 973169871U, // LDEORALB + 973171301U, // LDEORALH + 973171964U, // LDEORALW + 973171964U, // LDEORALX + 973169402U, // LDEORAW + 973169402U, // LDEORAX + 973170106U, // LDEORB + 973171557U, // LDEORH + 973169966U, // LDEORLB + 973171396U, // LDEORLH + 973172257U, // LDEORLW + 973172257U, // LDEORLX + 973173043U, // LDEORW + 973173043U, // LDEORX + 379716466U, // LDFF1B_D_REAL + 379749234U, // LDFF1B_H_REAL + 379741042U, // LDFF1B_REAL + 379724658U, // LDFF1B_S_REAL + 379717446U, // LDFF1D_REAL + 379717940U, // LDFF1H_D_REAL + 379750708U, // LDFF1H_REAL + 379726132U, // LDFF1H_S_REAL + 379717154U, // LDFF1SB_D_REAL + 379749922U, // LDFF1SB_H_REAL + 379725346U, // LDFF1SB_S_REAL + 379718605U, // LDFF1SH_D_REAL + 379726797U, // LDFF1SH_S_REAL + 379720943U, // LDFF1SW_D_REAL + 379720764U, // LDFF1W_D_REAL + 379728956U, // LDFF1W_REAL + 2253964693U, // LDLARB + 2253966144U, // LDLARH + 2253967567U, // LDLARW + 2253967567U, // LDLARX + 379716474U, // LDNF1B_D_IMM_REAL + 379749242U, // LDNF1B_H_IMM_REAL + 379741050U, // LDNF1B_IMM_REAL + 379724666U, // LDNF1B_S_IMM_REAL + 379717454U, // LDNF1D_IMM_REAL + 379717948U, // LDNF1H_D_IMM_REAL + 379750716U, // LDNF1H_IMM_REAL + 379726140U, // LDNF1H_S_IMM_REAL + 379717163U, // LDNF1SB_D_IMM_REAL + 379749931U, // LDNF1SB_H_IMM_REAL + 379725355U, // LDNF1SB_S_IMM_REAL + 379718614U, // LDNF1SH_D_IMM_REAL + 379726806U, // LDNF1SH_S_IMM_REAL + 379720952U, // LDNF1SW_D_IMM_REAL + 379720772U, // LDNF1W_D_IMM_REAL + 379728964U, // LDNF1W_IMM_REAL + 2248200224U, // LDNPDi + 2248200224U, // LDNPQi + 2248200224U, // LDNPSi + 2248200224U, // LDNPWi + 2248200224U, // LDNPXi + 379741058U, // LDNT1B_ZRI + 379741058U, // LDNT1B_ZRR + 379717462U, // LDNT1D_ZRI + 379717462U, // LDNT1D_ZRR + 379750724U, // LDNT1H_ZRI + 379750724U, // LDNT1H_ZRR + 379728972U, // LDNT1W_ZRI + 379728972U, // LDNT1W_ZRR + 2248200156U, // LDPDi + 2516676572U, // LDPDpost + 2516676572U, // LDPDpre + 2248200156U, // LDPQi + 2516676572U, // LDPQpost + 2516676572U, // LDPQpre + 2248201473U, // LDPSWi + 2516677889U, // LDPSWpost + 2516677889U, // LDPSWpre + 2248200156U, // LDPSi + 2516676572U, // LDPSpost + 2516676572U, // LDPSpre + 2248200156U, // LDPWi + 2516676572U, // LDPWpost + 2516676572U, // LDPWpre + 2248200156U, // LDPXi + 2516676572U, // LDPXpost + 2516676572U, // LDPXpre + 106480223U, // LDRAAindexed + 374956639U, // LDRAAwriteback + 106480640U, // LDRABindexed + 374957056U, // LDRABwriteback + 374957469U, // LDRBBpost + 374957469U, // LDRBBpre + 106481053U, // LDRBBroW + 106481053U, // LDRBBroX + 106481053U, // LDRBBui + 374960359U, // LDRBpost + 374960359U, // LDRBpre + 106483943U, // LDRBroW + 106483943U, // LDRBroX + 106483943U, // LDRBui + 436261095U, // LDRDl + 374960359U, // LDRDpost + 374960359U, // LDRDpre + 106483943U, // LDRDroW + 106483943U, // LDRDroX + 106483943U, // LDRDui + 374958920U, // LDRHHpost + 374958920U, // LDRHHpre + 106482504U, // LDRHHroW + 106482504U, // LDRHHroX + 106482504U, // LDRHHui + 374960359U, // LDRHpost + 374960359U, // LDRHpre + 106483943U, // LDRHroW + 106483943U, // LDRHroX + 106483943U, // LDRHui + 436261095U, // LDRQl + 374960359U, // LDRQpost + 374960359U, // LDRQpre + 106483943U, // LDRQroW + 106483943U, // LDRQroX + 106483943U, // LDRQui + 374957657U, // LDRSBWpost + 374957657U, // LDRSBWpre + 106481241U, // LDRSBWroW + 106481241U, // LDRSBWroX + 106481241U, // LDRSBWui + 374957657U, // LDRSBXpost + 374957657U, // LDRSBXpre + 106481241U, // LDRSBXroW + 106481241U, // LDRSBXroX + 106481241U, // LDRSBXui + 374959095U, // LDRSHWpost + 374959095U, // LDRSHWpre + 106482679U, // LDRSHWroW + 106482679U, // LDRSHWroX + 106482679U, // LDRSHWui + 374959095U, // LDRSHXpost + 374959095U, // LDRSHXpre + 106482679U, // LDRSHXroW + 106482679U, // LDRSHXroX + 106482679U, // LDRSHXui + 436262160U, // LDRSWl + 374961424U, // LDRSWpost + 374961424U, // LDRSWpre + 106485008U, // LDRSWroW + 106485008U, // LDRSWroX + 106485008U, // LDRSWui + 436261095U, // LDRSl + 374960359U, // LDRSpost + 374960359U, // LDRSpre + 106483943U, // LDRSroW + 106483943U, // LDRSroX + 106483943U, // LDRSui + 436261095U, // LDRWl + 374960359U, // LDRWpost + 374960359U, // LDRWpre + 106483943U, // LDRWroW + 106483943U, // LDRWroX + 106483943U, // LDRWui + 436261095U, // LDRXl + 374960359U, // LDRXpost + 374960359U, // LDRXpre + 106483943U, // LDRXroW + 106483943U, // LDRXroX + 106483943U, // LDRXui + 106803431U, // LDR_PXI + 106803431U, // LDR_ZXI + 973169703U, // LDSETAB + 973171167U, // LDSETAH + 973169889U, // LDSETALB + 973171319U, // LDSETALH + 973171980U, // LDSETALW + 973171980U, // LDSETALX + 973169442U, // LDSETAW + 973169442U, // LDSETAX + 973170303U, // LDSETB + 973171736U, // LDSETH + 973169982U, // LDSETLB + 973171412U, // LDSETLH + 973172305U, // LDSETLW + 973172305U, // LDSETLX + 973173476U, // LDSETW + 973173476U, // LDSETX + 973169712U, // LDSMAXAB + 973171176U, // LDSMAXAH + 973169899U, // LDSMAXALB + 973171329U, // LDSMAXALH + 973171989U, // LDSMAXALW + 973171989U, // LDSMAXALX + 973169466U, // LDSMAXAW + 973169466U, // LDSMAXAX + 973170392U, // LDSMAXB + 973171768U, // LDSMAXH + 973169991U, // LDSMAXLB + 973171454U, // LDSMAXLH + 973172360U, // LDSMAXLW + 973172360U, // LDSMAXLX + 973174109U, // LDSMAXW + 973174109U, // LDSMAXX + 973169631U, // LDSMINAB + 973171115U, // LDSMINAH + 973169831U, // LDSMINALB + 973171261U, // LDSMINALH + 973171920U, // LDSMINALW + 973171920U, // LDSMINALX + 973169349U, // LDSMINAW + 973169349U, // LDSMINAX + 973170016U, // LDSMINB + 973171474U, // LDSMINH + 973169930U, // LDSMINLB + 973171360U, // LDSMINLH + 973172211U, // LDSMINLW + 973172211U, // LDSMINLX + 973172462U, // LDSMINW + 973172462U, // LDSMINX + 106481098U, // LDTRBi + 106482549U, // LDTRHi + 106481248U, // LDTRSBWi + 106481248U, // LDTRSBXi + 106482686U, // LDTRSHWi + 106482686U, // LDTRSHXi + 106485015U, // LDTRSWi + 106484081U, // LDTRWi + 106484081U, // LDTRXi + 973169722U, // LDUMAXAB + 973171186U, // LDUMAXAH + 973169910U, // LDUMAXALB + 973171340U, // LDUMAXALH + 973171999U, // LDUMAXALW + 973171999U, // LDUMAXALX + 973169475U, // LDUMAXAW + 973169475U, // LDUMAXAX + 973170401U, // LDUMAXB + 973171777U, // LDUMAXH + 973170001U, // LDUMAXLB + 973171464U, // LDUMAXLH + 973172369U, // LDUMAXLW + 973172369U, // LDUMAXLX + 973174117U, // LDUMAXW + 973174117U, // LDUMAXX + 973169641U, // LDUMINAB + 973171125U, // LDUMINAH + 973169842U, // LDUMINALB + 973171272U, // LDUMINALH + 973171930U, // LDUMINALW + 973171930U, // LDUMINALX + 973169358U, // LDUMINAW + 973169358U, // LDUMINAX + 973170025U, // LDUMINB + 973171483U, // LDUMINH + 973169940U, // LDUMINLB + 973171370U, // LDUMINLH + 973172220U, // LDUMINLW + 973172220U, // LDUMINLX + 973172470U, // LDUMINW + 973172470U, // LDUMINX + 106481118U, // LDURBBi + 106484104U, // LDURBi + 106484104U, // LDURDi + 106482569U, // LDURHHi + 106484104U, // LDURHi + 106484104U, // LDURQi + 106481256U, // LDURSBWi + 106481256U, // LDURSBXi + 106482694U, // LDURSHWi + 106482694U, // LDURSHXi + 106485023U, // LDURSWi + 106484104U, // LDURSi + 106484104U, // LDURWi + 106484104U, // LDURXi + 2248200327U, // LDXPW + 2248200327U, // LDXPX + 2253964805U, // LDXRB + 2253966256U, // LDXRH + 2253967807U, // LDXRW + 2253967807U, // LDXRX + 0U, // LOADgot + 302002471U, // LSLR_ZPmZ_B + 302010663U, // LSLR_ZPmZ_D + 2186309927U, // LSLR_ZPmZ_H + 302027047U, // LSLR_ZPmZ_S + 100716088U, // LSLVWr + 100716088U, // LSLVXr + 302001720U, // LSL_WIDE_ZPmZ_B + 2186309176U, // LSL_WIDE_ZPmZ_H + 302026296U, // LSL_WIDE_ZPmZ_S + 167783992U, // LSL_WIDE_ZZZ_B + 2387111480U, // LSL_WIDE_ZZZ_H + 268471864U, // LSL_WIDE_ZZZ_S + 302001720U, // LSL_ZPmI_B + 302009912U, // LSL_ZPmI_D + 2186309176U, // LSL_ZPmI_H + 302026296U, // LSL_ZPmI_S + 302001720U, // LSL_ZPmZ_B + 302009912U, // LSL_ZPmZ_D + 2186309176U, // LSL_ZPmZ_H + 302026296U, // LSL_ZPmZ_S + 167783992U, // LSL_ZZI_B + 201346616U, // LSL_ZZI_D + 239627832U, // LSL_ZZI_H + 268471864U, // LSL_ZZI_S + 302002518U, // LSRR_ZPmZ_B + 302010710U, // LSRR_ZPmZ_D + 2186309974U, // LSRR_ZPmZ_H + 302027094U, // LSRR_ZPmZ_S + 100716897U, // LSRVWr + 100716897U, // LSRVXr + 302002529U, // LSR_WIDE_ZPmZ_B + 2186309985U, // LSR_WIDE_ZPmZ_H + 302027105U, // LSR_WIDE_ZPmZ_S + 167784801U, // LSR_WIDE_ZZZ_B + 2387112289U, // LSR_WIDE_ZZZ_H + 268472673U, // LSR_WIDE_ZZZ_S + 302002529U, // LSR_ZPmI_B + 302010721U, // LSR_ZPmI_D + 2186309985U, // LSR_ZPmI_H + 302027105U, // LSR_ZPmI_S + 302002529U, // LSR_ZPmZ_B + 302010721U, // LSR_ZPmZ_D + 2186309985U, // LSR_ZPmZ_H + 302027105U, // LSR_ZPmZ_S + 167784801U, // LSR_ZZI_B + 201347425U, // LSR_ZZI_D + 239628641U, // LSR_ZZI_H + 268472673U, // LSR_ZZI_S + 100714512U, // MADDWrrr + 100714512U, // MADDXrrr + 302000017U, // MAD_ZPmZZ_B + 302008209U, // MAD_ZPmZZ_D + 2186307473U, // MAD_ZPmZZ_H + 302024593U, // MAD_ZPmZZ_S + 301998771U, // MLA_ZPmZZ_B + 302006963U, // MLA_ZPmZZ_D + 2186306227U, // MLA_ZPmZZ_H + 302023347U, // MLA_ZPmZZ_S + 135324339U, // MLAv16i8 + 2283332275U, // MLAv2i32 + 2283332275U, // MLAv2i32_indexed + 136897203U, // MLAv4i16 + 136897203U, // MLAv4i16_indexed + 137421491U, // MLAv4i32 + 137421491U, // MLAv4i32_indexed + 2285429427U, // MLAv8i16 + 2285429427U, // MLAv8i16_indexed + 2285953715U, // MLAv8i8 + 302002771U, // MLS_ZPmZZ_B + 302010963U, // MLS_ZPmZZ_D + 2186310227U, // MLS_ZPmZZ_H + 302027347U, // MLS_ZPmZZ_S + 135328339U, // MLSv16i8 + 2283336275U, // MLSv2i32 + 2283336275U, // MLSv2i32_indexed + 136901203U, // MLSv4i16 + 136901203U, // MLSv4i16_indexed + 137425491U, // MLSv4i32 + 137425491U, // MLSv4i32_indexed + 2285433427U, // MLSv8i16 + 2285433427U, // MLSv8i16_indexed + 2285957715U, // MLSv8i8 + 1006685329U, // MOVID + 3188763793U, // MOVIv16b_ns + 1008774289U, // MOVIv2d_ns + 3189288081U, // MOVIv2i32 + 3189288081U, // MOVIv2s_msl + 3190336657U, // MOVIv4i16 + 3190860945U, // MOVIv4i32 + 3190860945U, // MOVIv4s_msl + 3191909521U, // MOVIv8b_ns + 3191385233U, // MOVIv8i16 + 402705564U, // MOVKWi + 402705564U, // MOVKXi + 3187724142U, // MOVNWi + 3187724142U, // MOVNXi + 13705U, // MOVPRFX_ZPmZ_B + 21897U, // MOVPRFX_ZPmZ_D + 2181592457U, // MOVPRFX_ZPmZ_H + 38281U, // MOVPRFX_ZPmZ_S + 302003593U, // MOVPRFX_ZPzZ_B + 302011785U, // MOVPRFX_ZPzZ_D + 2622518665U, // MOVPRFX_ZPzZ_H + 302028169U, // MOVPRFX_ZPzZ_S + 2449847689U, // MOVPRFX_ZZ + 3187725817U, // MOVZWi + 3187725817U, // MOVZXi + 0U, // MOVaddr + 0U, // MOVaddrBA + 0U, // MOVaddrCP + 0U, // MOVaddrEXT + 0U, // MOVaddrJT + 0U, // MOVaddrTLS + 0U, // MOVbaseTLS + 0U, // MOVi32imm + 0U, // MOVi64imm + 1073795744U, // MRS + 301999685U, // MSB_ZPmZZ_B + 302007877U, // MSB_ZPmZZ_D + 2186307141U, // MSB_ZPmZZ_H + 302024261U, // MSB_ZPmZZ_S + 381286U, // MSR + 389478U, // MSRpstateImm1 + 389478U, // MSRpstateImm4 + 100714166U, // MSUBWrrr + 100714166U, // MSUBXrrr + 167784033U, // MUL_ZI_B + 201346657U, // MUL_ZI_D + 239627873U, // MUL_ZI_H + 268471905U, // MUL_ZI_S + 302001761U, // MUL_ZPmZ_B + 302009953U, // MUL_ZPmZ_D + 2186309217U, // MUL_ZPmZ_H + 302026337U, // MUL_ZPmZ_S + 68202081U, // MULv16i8 + 2216210017U, // MULv2i32 + 2216210017U, // MULv2i32_indexed + 69774945U, // MULv4i16 + 69774945U, // MULv4i16_indexed + 70299233U, // MULv4i32 + 70299233U, // MULv4i32_indexed + 2218307169U, // MULv8i16 + 2218307169U, // MULv8i16_indexed + 2218831457U, // MULv8i8 + 3189288062U, // MVNIv2i32 + 3189288062U, // MVNIv2s_msl + 3190336638U, // MVNIv4i16 + 3190860926U, // MVNIv4i32 + 3190860926U, // MVNIv4s_msl + 3191385214U, // MVNIv8i16 + 302002728U, // NANDS_PPzPP + 302000180U, // NAND_PPzPP + 10516U, // NEG_ZPmZ_B + 18708U, // NEG_ZPmZ_D + 2181589268U, // NEG_ZPmZ_H + 35092U, // NEG_ZPmZ_S + 68200724U, // NEGv16i8 + 2248198420U, // NEGv1i64 + 68725012U, // NEGv2i32 + 2216732948U, // NEGv2i64 + 69773588U, // NEGv4i16 + 2217781524U, // NEGv4i32 + 70822164U, // NEGv8i16 + 2218830100U, // NEGv8i8 + 302002859U, // NORS_PPzPP + 302002490U, // NOR_PPzPP + 13114U, // NOT_ZPmZ_B + 21306U, // NOT_ZPmZ_D + 2181591866U, // NOT_ZPmZ_H + 37690U, // NOT_ZPmZ_S + 68203322U, // NOTv16i8 + 2218832698U, // NOTv8i8 + 302002810U, // ORNS_PPzPP + 0U, // ORNWrr + 100716337U, // ORNWrs + 0U, // ORNXrr + 100716337U, // ORNXrs + 302001969U, // ORN_PPzPP + 68202289U, // ORNv16i8 + 2218831665U, // ORNv8i8 + 302002865U, // ORRS_PPzPP + 100716875U, // ORRWri + 0U, // ORRWrr + 100716875U, // ORRWrs + 100716875U, // ORRXri + 0U, // ORRXrr + 100716875U, // ORRXrs + 302002507U, // ORR_PPzPP + 201347403U, // ORR_ZI + 302002507U, // ORR_ZPmZ_B + 302010699U, // ORR_ZPmZ_D + 2186309963U, // ORR_ZPmZ_H + 302027083U, // ORR_ZPmZ_S + 201347403U, // ORR_ZZZ + 68202827U, // ORRv16i8 + 404287819U, // ORRv2i32 + 405336395U, // ORRv4i16 + 405860683U, // ORRv4i32 + 406384971U, // ORRv8i16 + 2218832203U, // ORRv8i8 + 302044188U, // ORV_VPZ_B + 302044188U, // ORV_VPZ_D + 302044188U, // ORV_VPZ_H + 302044188U, // ORV_VPZ_S + 2248196729U, // PACDA + 2248197229U, // PACDB + 6341452U, // PACDZA + 6342378U, // PACDZB + 100713110U, // PACGA + 2248196765U, // PACIA + 5796U, // PACIA1716 + 5927U, // PACIASP + 5982U, // PACIAZ + 2248197257U, // PACIB + 5816U, // PACIB1716 + 5943U, // PACIBSP + 5996U, // PACIBZ + 6341468U, // PACIZA + 6342394U, // PACIZB + 6301913U, // PFALSE + 70820111U, // PMULLv16i8 + 1132506590U, // PMULLv1i64 + 1166057743U, // PMULLv2i64 + 2218307038U, // PMULLv8i8 + 68202093U, // PMULv16i8 + 2218831469U, // PMULv8i8 + 302003042U, // PNEXT_B + 302011234U, // PNEXT_D + 2387637090U, // PNEXT_H + 302027618U, // PNEXT_S + 3079537795U, // PRFB_D_PZI + 246285443U, // PRFB_D_SCALED + 2393769091U, // PRFB_D_SXTW_SCALED + 246285443U, // PRFB_D_UXTW_SCALED + 246285443U, // PRFB_PRI + 2393769091U, // PRFB_PRR + 3080062083U, // PRFB_S_PZI + 246285443U, // PRFB_S_SXTW_SCALED + 2393769091U, // PRFB_S_UXTW_SCALED + 1200490542U, // PRFD_D_PZI + 246286382U, // PRFD_D_SCALED + 2393770030U, // PRFD_D_SXTW_SCALED + 246286382U, // PRFD_D_UXTW_SCALED + 246286382U, // PRFD_PRI + 2393770030U, // PRFD_PRR + 1201014830U, // PRFD_S_PZI + 246286382U, // PRFD_S_SXTW_SCALED + 2393770030U, // PRFD_S_UXTW_SCALED + 1234045485U, // PRFH_D_PZI + 246286893U, // PRFH_D_SCALED + 2393770541U, // PRFH_D_SXTW_SCALED + 246286893U, // PRFH_D_UXTW_SCALED + 246286893U, // PRFH_PRI + 2393770541U, // PRFH_PRR + 1234569773U, // PRFH_S_PZI + 246286893U, // PRFH_S_SXTW_SCALED + 2393770541U, // PRFH_S_UXTW_SCALED + 436612781U, // PRFMl + 106835629U, // PRFMroW + 106835629U, // PRFMroX + 106835629U, // PRFMui + 246289619U, // PRFS_PRR + 106835665U, // PRFUMi + 1267602643U, // PRFW_D_PZI + 2393773267U, // PRFW_D_SCALED + 246289619U, // PRFW_D_SXTW_SCALED + 2393773267U, // PRFW_D_UXTW_SCALED + 246289619U, // PRFW_PRI + 1268126931U, // PRFW_S_PZI + 246289619U, // PRFW_S_SXTW_SCALED + 2393773267U, // PRFW_S_UXTW_SCALED + 2315629382U, // PTEST_PP + 2650812975U, // PTRUES_B + 2650821167U, // PTRUES_D + 26767919U, // PTRUES_H + 2650837551U, // PTRUES_S + 2650810611U, // PTRUE_B + 2650818803U, // PTRUE_D + 26765555U, // PTRUE_H + 2650835187U, // PTRUE_S + 27290705U, // PUNPKHI_PP + 27291525U, // PUNPKLO_PP + 2216210144U, // RADDHNv2i64_v2i32 + 2284904786U, // RADDHNv2i64_v4i32 + 69775072U, // RADDHNv4i32_v4i16 + 137945426U, // RADDHNv4i32_v8i16 + 2282807634U, // RADDHNv8i16_v16i8 + 2218831584U, // RADDHNv8i16_v8i8 + 2216730741U, // RAX1 + 2248200960U, // RBITWr + 2248200960U, // RBITXr + 13056U, // RBIT_ZPmZ_B + 21248U, // RBIT_ZPmZ_D + 2181591808U, // RBIT_ZPmZ_H + 37632U, // RBIT_ZPmZ_S + 68203264U, // RBITv16i8 + 2218832640U, // RBITv8i8 + 302002840U, // RDFFRS_PPz + 6303980U, // RDFFR_P + 302002412U, // RDFFR_PPz + 2248199810U, // RDVLI_XI + 6345439U, // RET + 5892U, // RETAA + 5899U, // RETAB + 0U, // RET_ReallyLR + 2248196665U, // REV16Wr + 2248196665U, // REV16Xr + 68198969U, // REV16v16i8 + 2218828345U, // REV16v8i8 + 2248196219U, // REV32Xr + 68198523U, // REV32v16i8 + 69771387U, // REV32v4i16 + 70819963U, // REV32v8i16 + 2218827899U, // REV32v8i8 + 68198944U, // REV64v16i8 + 68723232U, // REV64v2i32 + 69771808U, // REV64v4i16 + 2217779744U, // REV64v4i32 + 70820384U, // REV64v8i16 + 2218828320U, // REV64v8i8 + 18130U, // REVB_ZPmZ_D + 2181588690U, // REVB_ZPmZ_H + 34514U, // REVB_ZPmZ_S + 19506U, // REVH_ZPmZ_D + 35890U, // REVH_ZPmZ_S + 21827U, // REVW_ZPmZ_D + 2248201140U, // REVWr + 2248201140U, // REVXr + 2315269044U, // REV_PP_B + 2348831668U, // REV_PP_D + 608727988U, // REV_PP_H + 2415956916U, // REV_PP_S + 2315269044U, // REV_ZZ_B + 2348831668U, // REV_ZZ_D + 608727988U, // REV_ZZ_H + 2415956916U, // REV_ZZ_S + 100714751U, // RMIF + 100716863U, // RORVWr + 100716863U, // RORVXr + 2282807663U, // RSHRNv16i8_shift + 2216210209U, // RSHRNv2i32_shift + 69775137U, // RSHRNv4i16_shift + 2284904815U, // RSHRNv4i32_shift + 137945455U, // RSHRNv8i16_shift + 2218831649U, // RSHRNv8i8_shift + 2216210136U, // RSUBHNv2i64_v2i32 + 2284904777U, // RSUBHNv2i64_v4i32 + 69775064U, // RSUBHNv4i32_v4i16 + 137945417U, // RSUBHNv4i32_v8i16 + 2282807625U, // RSUBHNv8i16_v16i8 + 2218831576U, // RSUBHNv8i16_v8i8 + 137945243U, // SABALv16i8_v8i16 + 2283859106U, // SABALv2i32_v2i64 + 137424034U, // SABALv4i16_v4i32 + 136372379U, // SABALv4i32_v2i64 + 2284904603U, // SABALv8i16_v4i32 + 2285431970U, // SABALv8i8_v8i16 + 135324269U, // SABAv16i8 + 2283332205U, // SABAv2i32 + 136897133U, // SABAv4i16 + 137421421U, // SABAv4i32 + 2285429357U, // SABAv8i16 + 2285953645U, // SABAv8i8 + 70820053U, // SABDLv16i8_v8i16 + 2216734028U, // SABDLv2i32_v2i64 + 70298956U, // SABDLv4i16_v4i32 + 69247189U, // SABDLv4i32_v2i64 + 2217779413U, // SABDLv8i16_v4i32 + 2218306892U, // SABDLv8i8_v8i16 + 302000042U, // SABD_ZPmZ_B + 302008234U, // SABD_ZPmZ_D + 2186307498U, // SABD_ZPmZ_H + 302024618U, // SABD_ZPmZ_S + 68200362U, // SABDv16i8 + 2216208298U, // SABDv2i32 + 69773226U, // SABDv4i16 + 70297514U, // SABDv4i32 + 2218305450U, // SABDv8i16 + 2218829738U, // SABDv8i8 + 137949153U, // SADALPv16i8_v8i16 + 162066401U, // SADALPv2i32_v1i64 + 135852001U, // SADALPv4i16_v2i32 + 2283859937U, // SADALPv4i32_v2i64 + 137424865U, // SADALPv8i16_v4i32 + 2284384225U, // SADALPv8i8_v4i16 + 70823921U, // SADDLPv16i8_v8i16 + 94941169U, // SADDLPv2i32_v1i64 + 68726769U, // SADDLPv4i16_v2i32 + 2216734705U, // SADDLPv4i32_v2i64 + 70299633U, // SADDLPv8i16_v4i32 + 2217258993U, // SADDLPv8i8_v4i16 + 67163083U, // SADDLVv16i8v + 67163083U, // SADDLVv4i16v + 2214646731U, // SADDLVv4i32v + 67163083U, // SADDLVv8i16v + 2214646731U, // SADDLVv8i8v + 70820069U, // SADDLv16i8_v8i16 + 2216734066U, // SADDLv2i32_v2i64 + 70298994U, // SADDLv4i16_v4i32 + 69247205U, // SADDLv4i32_v2i64 + 2217779429U, // SADDLv8i16_v4i32 + 2218306930U, // SADDLv8i8_v8i16 + 302044064U, // SADDV_VPZ_B + 302044064U, // SADDV_VPZ_H + 302044064U, // SADDV_VPZ_S + 2218303982U, // SADDWv16i8_v8i16 + 2216735941U, // SADDWv2i32_v2i64 + 70300869U, // SADDWv4i16_v4i32 + 2216731118U, // SADDWv4i32_v2i64 + 70296046U, // SADDWv8i16_v4i32 + 2218308805U, // SADDWv8i8_v8i16 + 100717072U, // SBCSWr + 100717072U, // SBCSXr + 100714257U, // SBCWr + 100714257U, // SBCXr + 100716193U, // SBFMWri + 100716193U, // SBFMXri + 100714757U, // SCVTFSWDri + 100714757U, // SCVTFSWHri + 100714757U, // SCVTFSWSri + 100714757U, // SCVTFSXDri + 100714757U, // SCVTFSXHri + 100714757U, // SCVTFSXSri + 2248198405U, // SCVTFUWDri + 2248198405U, // SCVTFUWHri + 2248198405U, // SCVTFUWSri + 2248198405U, // SCVTFUXDri + 2248198405U, // SCVTFUXHri + 2248198405U, // SCVTFUXSri + 18693U, // SCVTF_ZPmZ_DtoD + 2181589253U, // SCVTF_ZPmZ_DtoH + 35077U, // SCVTF_ZPmZ_DtoS + 2181589253U, // SCVTF_ZPmZ_HtoH + 18693U, // SCVTF_ZPmZ_StoD + 2181589253U, // SCVTF_ZPmZ_StoH + 35077U, // SCVTF_ZPmZ_StoS + 100714757U, // SCVTFd + 100714757U, // SCVTFh + 100714757U, // SCVTFs + 2248198405U, // SCVTFv1i16 + 2248198405U, // SCVTFv1i32 + 2248198405U, // SCVTFv1i64 + 68724997U, // SCVTFv2f32 + 2216732933U, // SCVTFv2f64 + 2216208645U, // SCVTFv2i32_shift + 2216732933U, // SCVTFv2i64_shift + 69773573U, // SCVTFv4f16 + 2217781509U, // SCVTFv4f32 + 69773573U, // SCVTFv4i16_shift + 70297861U, // SCVTFv4i32_shift + 70822149U, // SCVTFv8f16 + 2218305797U, // SCVTFv8i16_shift + 302010794U, // SDIVR_ZPmZ_D + 302027178U, // SDIVR_ZPmZ_S + 100717503U, // SDIVWr + 100717503U, // SDIVXr + 302011327U, // SDIV_ZPmZ_D + 302027711U, // SDIV_ZPmZ_S + 3422573357U, // SDOT_ZZZI_D + 3456144173U, // SDOT_ZZZI_S + 3422573357U, // SDOT_ZZZ_D + 3456144173U, // SDOT_ZZZ_S + 137425709U, // SDOTlanev16i8 + 2283336493U, // SDOTlanev8i8 + 137425709U, // SDOTv16i8 + 2283336493U, // SDOTv8i8 + 302001538U, // SEL_PPPP + 302001538U, // SEL_ZPZZ_B + 302009730U, // SEL_ZPZZ_D + 2387635586U, // SEL_ZPZZ_H + 302026114U, // SEL_ZPZZ_S + 6341169U, // SETF16 + 6341184U, // SETF8 + 5959U, // SETFFR + 369190666U, // SHA1Crrr + 2248198439U, // SHA1Hrr + 369192602U, // SHA1Mrrr + 369192878U, // SHA1Prrr + 137420801U, // SHA1SU0rrr + 2284904523U, // SHA1SU1rr + 369189009U, // SHA256H2rrr + 369191311U, // SHA256Hrrr + 2284904469U, // SHA256SU0rr + 137420895U, // SHA256SU1rrr + 369191258U, // SHA512H + 369188999U, // SHA512H2 + 2216730634U, // SHA512SU0 + 2283855956U, // SHA512SU1 + 68200449U, // SHADDv16i8 + 2216208385U, // SHADDv2i32 + 69773313U, // SHADDv4i16 + 70297601U, // SHADDv4i32 + 2218305537U, // SHADDv8i16 + 2218829825U, // SHADDv8i8 + 70820086U, // SHLLv16i8 + 2216734152U, // SHLLv2i32 + 70299080U, // SHLLv4i16 + 2216730870U, // SHLLv4i32 + 70295798U, // SHLLv8i16 + 2218307016U, // SHLLv8i8 + 100715921U, // SHLd + 68201873U, // SHLv16i8_shift + 2216209809U, // SHLv2i32_shift + 2216734097U, // SHLv2i64_shift + 69774737U, // SHLv4i16_shift + 70299025U, // SHLv4i32_shift + 2218306961U, // SHLv8i16_shift + 2218831249U, // SHLv8i8_shift + 2282807645U, // SHRNv16i8_shift + 2216210193U, // SHRNv2i32_shift + 69775121U, // SHRNv4i16_shift + 2284904797U, // SHRNv4i32_shift + 137945437U, // SHRNv8i16_shift + 2218831633U, // SHRNv8i8_shift + 68200103U, // SHSUBv16i8 + 2216208039U, // SHSUBv2i32 + 69772967U, // SHSUBv4i16 + 70297255U, // SHSUBv4i32 + 2218305191U, // SHSUBv8i16 + 2218829479U, // SHSUBv8i8 + 369192057U, // SLId + 135326841U, // SLIv16i8_shift + 2283334777U, // SLIv2i32_shift + 2283859065U, // SLIv2i64_shift + 136899705U, // SLIv4i16_shift + 137423993U, // SLIv4i32_shift + 2285431929U, // SLIv8i16_shift + 2285956217U, // SLIv8i8_shift + 137420906U, // SM3PARTW1 + 137421310U, // SM3PARTW2 + 70295614U, // SM3SS1 + 137421383U, // SM3TT1A + 137421720U, // SM3TT1B + 137421392U, // SM3TT2A + 137421749U, // SM3TT2B + 2217781339U, // SM4E + 70301097U, // SM4ENCKEY + 100715874U, // SMADDLrrr + 68202617U, // SMAXPv16i8 + 2216210553U, // SMAXPv2i32 + 69775481U, // SMAXPv4i16 + 70299769U, // SMAXPv4i32 + 2218307705U, // SMAXPv8i16 + 2218831993U, // SMAXPv8i8 + 302044200U, // SMAXV_VPZ_B + 302044200U, // SMAXV_VPZ_D + 302044200U, // SMAXV_VPZ_H + 302044200U, // SMAXV_VPZ_S + 67163176U, // SMAXVv16i8v + 67163176U, // SMAXVv4i16v + 2214646824U, // SMAXVv4i32v + 67163176U, // SMAXVv8i16v + 2214646824U, // SMAXVv8i8v + 167785823U, // SMAX_ZI_B + 201348447U, // SMAX_ZI_D + 239629663U, // SMAX_ZI_H + 268473695U, // SMAX_ZI_S + 302003551U, // SMAX_ZPmZ_B + 302011743U, // SMAX_ZPmZ_D + 2186311007U, // SMAX_ZPmZ_H + 302028127U, // SMAX_ZPmZ_S + 68203871U, // SMAXv16i8 + 2216211807U, // SMAXv2i32 + 69776735U, // SMAXv4i16 + 70301023U, // SMAXv4i32 + 2218308959U, // SMAXv8i16 + 2218833247U, // SMAXv8i8 + 75562U, // SMC + 68202541U, // SMINPv16i8 + 2216210477U, // SMINPv2i32 + 69775405U, // SMINPv4i16 + 70299693U, // SMINPv4i32 + 2218307629U, // SMINPv8i16 + 2218831917U, // SMINPv8i8 + 302044148U, // SMINV_VPZ_B + 302044148U, // SMINV_VPZ_D + 302044148U, // SMINV_VPZ_H + 302044148U, // SMINV_VPZ_S + 67163124U, // SMINVv16i8v + 67163124U, // SMINVv4i16v + 2214646772U, // SMINVv4i32v + 67163124U, // SMINVv8i16v + 2214646772U, // SMINVv8i8v + 167784176U, // SMIN_ZI_B + 201346800U, // SMIN_ZI_D + 239628016U, // SMIN_ZI_H + 268472048U, // SMIN_ZI_S + 302001904U, // SMIN_ZPmZ_B + 302010096U, // SMIN_ZPmZ_D + 2186309360U, // SMIN_ZPmZ_H + 302026480U, // SMIN_ZPmZ_S + 68202224U, // SMINv16i8 + 2216210160U, // SMINv2i32 + 69775088U, // SMINv4i16 + 70299376U, // SMINv4i32 + 2218307312U, // SMINv8i16 + 2218831600U, // SMINv8i8 + 137945269U, // SMLALv16i8_v8i16 + 2283859138U, // SMLALv2i32_indexed + 2283859138U, // SMLALv2i32_v2i64 + 137424066U, // SMLALv4i16_indexed + 137424066U, // SMLALv4i16_v4i32 + 136372405U, // SMLALv4i32_indexed + 136372405U, // SMLALv4i32_v2i64 + 2284904629U, // SMLALv8i16_indexed + 2284904629U, // SMLALv8i16_v4i32 + 2285432002U, // SMLALv8i8_v8i16 + 137945393U, // SMLSLv16i8_v8i16 + 2283859517U, // SMLSLv2i32_indexed + 2283859517U, // SMLSLv2i32_v2i64 + 137424445U, // SMLSLv4i16_indexed + 137424445U, // SMLSLv4i16_v4i32 + 136372529U, // SMLSLv4i32_indexed + 136372529U, // SMLSLv4i32_v2i64 + 2284904753U, // SMLSLv8i16_indexed + 2284904753U, // SMLSLv8i16_v4i32 + 2285432381U, // SMLSLv8i8_v8i16 + 67163151U, // SMOVvi16to32 + 67163151U, // SMOVvi16to64 + 2214646799U, // SMOVvi32to64 + 2214646799U, // SMOVvi8to32 + 2214646799U, // SMOVvi8to64 + 100715822U, // SMSUBLrrr + 302000880U, // SMULH_ZPmZ_B + 302009072U, // SMULH_ZPmZ_D + 2186308336U, // SMULH_ZPmZ_H + 302025456U, // SMULH_ZPmZ_S + 100715248U, // SMULHrr + 70820119U, // SMULLv16i8_v8i16 + 2216734181U, // SMULLv2i32_indexed + 2216734181U, // SMULLv2i32_v2i64 + 70299109U, // SMULLv4i16_indexed + 70299109U, // SMULLv4i16_v4i32 + 69247255U, // SMULLv4i32_indexed + 69247255U, // SMULLv4i32_v2i64 + 2217779479U, // SMULLv8i16_indexed + 2217779479U, // SMULLv8i16_v4i32 + 2218307045U, // SMULLv8i8_v8i16 + 302000225U, // SPLICE_ZPZ_B + 302008417U, // SPLICE_ZPZ_D + 2387634273U, // SPLICE_ZPZ_H + 302024801U, // SPLICE_ZPZ_S + 68202996U, // SQABSv16i8 + 2248200692U, // SQABSv1i16 + 2248200692U, // SQABSv1i32 + 2248200692U, // SQABSv1i64 + 2248200692U, // SQABSv1i8 + 68727284U, // SQABSv2i32 + 2216735220U, // SQABSv2i64 + 69775860U, // SQABSv4i16 + 2217783796U, // SQABSv4i32 + 70824436U, // SQABSv8i16 + 2218832372U, // SQABSv8i8 + 167782431U, // SQADD_ZI_B + 201345055U, // SQADD_ZI_D + 239626271U, // SQADD_ZI_H + 268470303U, // SQADD_ZI_S + 167782431U, // SQADD_ZZZ_B + 201345055U, // SQADD_ZZZ_D + 2387109919U, // SQADD_ZZZ_H + 268470303U, // SQADD_ZZZ_S + 68200479U, // SQADDv16i8 + 100714527U, // SQADDv1i16 + 100714527U, // SQADDv1i32 + 100714527U, // SQADDv1i64 + 100714527U, // SQADDv1i8 + 2216208415U, // SQADDv2i32 + 2216732703U, // SQADDv2i64 + 69773343U, // SQADDv4i16 + 70297631U, // SQADDv4i32 + 2218305567U, // SQADDv8i16 + 2218829855U, // SQADDv8i8 + 536921165U, // SQDECB_XPiI + 1342227533U, // SQDECB_XPiWdI + 536922045U, // SQDECD_XPiI + 1342228413U, // SQDECD_XPiWdI + 536889277U, // SQDECD_ZPiI + 536922629U, // SQDECH_XPiI + 1342228997U, // SQDECH_XPiWdI + 6842885U, // SQDECH_ZPiI + 167825333U, // SQDECP_XPWd_B + 201379765U, // SQDECP_XPWd_D + 570478517U, // SQDECP_XPWd_H + 268488629U, // SQDECP_XPWd_S + 2315308981U, // SQDECP_XP_B + 2348863413U, // SQDECP_XP_D + 2717962165U, // SQDECP_XP_H + 2415972277U, // SQDECP_XP_S + 2147504053U, // SQDECP_ZP_D + 604532661U, // SQDECP_ZP_H + 2147520437U, // SQDECP_ZP_S + 536925349U, // SQDECW_XPiI + 1342231717U, // SQDECW_XPiWdI + 536908965U, // SQDECW_ZPiI + 369192121U, // SQDMLALi16 + 369192121U, // SQDMLALi32 + 369192121U, // SQDMLALv1i32_indexed + 369192121U, // SQDMLALv1i64_indexed + 2283859129U, // SQDMLALv2i32_indexed + 2283859129U, // SQDMLALv2i32_v2i64 + 137424057U, // SQDMLALv4i16_indexed + 137424057U, // SQDMLALv4i16_v4i32 + 136372395U, // SQDMLALv4i32_indexed + 136372395U, // SQDMLALv4i32_v2i64 + 2284904619U, // SQDMLALv8i16_indexed + 2284904619U, // SQDMLALv8i16_v4i32 + 369192500U, // SQDMLSLi16 + 369192500U, // SQDMLSLi32 + 369192500U, // SQDMLSLv1i32_indexed + 369192500U, // SQDMLSLv1i64_indexed + 2283859508U, // SQDMLSLv2i32_indexed + 2283859508U, // SQDMLSLv2i32_v2i64 + 137424436U, // SQDMLSLv4i16_indexed + 137424436U, // SQDMLSLv4i16_v4i32 + 136372519U, // SQDMLSLv4i32_indexed + 136372519U, // SQDMLSLv4i32_v2i64 + 2284904743U, // SQDMLSLv8i16_indexed + 2284904743U, // SQDMLSLv8i16_v4i32 + 100715229U, // SQDMULHv1i16 + 100715229U, // SQDMULHv1i16_indexed + 100715229U, // SQDMULHv1i32 + 100715229U, // SQDMULHv1i32_indexed + 2216209117U, // SQDMULHv2i32 + 2216209117U, // SQDMULHv2i32_indexed + 69774045U, // SQDMULHv4i16 + 69774045U, // SQDMULHv4i16_indexed + 70298333U, // SQDMULHv4i32 + 70298333U, // SQDMULHv4i32_indexed + 2218306269U, // SQDMULHv8i16 + 2218306269U, // SQDMULHv8i16_indexed + 100715989U, // SQDMULLi16 + 100715989U, // SQDMULLi32 + 100715989U, // SQDMULLv1i32_indexed + 100715989U, // SQDMULLv1i64_indexed + 2216734165U, // SQDMULLv2i32_indexed + 2216734165U, // SQDMULLv2i32_v2i64 + 70299093U, // SQDMULLv4i16_indexed + 70299093U, // SQDMULLv4i16_v4i32 + 69247237U, // SQDMULLv4i32_indexed + 69247237U, // SQDMULLv4i32_v2i64 + 2217779461U, // SQDMULLv8i16_indexed + 2217779461U, // SQDMULLv8i16_v4i32 + 536921181U, // SQINCB_XPiI + 1342227549U, // SQINCB_XPiWdI + 536922061U, // SQINCD_XPiI + 1342228429U, // SQINCD_XPiWdI + 536889293U, // SQINCD_ZPiI + 536922645U, // SQINCH_XPiI + 1342229013U, // SQINCH_XPiWdI + 6842901U, // SQINCH_ZPiI + 167825349U, // SQINCP_XPWd_B + 201379781U, // SQINCP_XPWd_D + 570478533U, // SQINCP_XPWd_H + 268488645U, // SQINCP_XPWd_S + 2315308997U, // SQINCP_XP_B + 2348863429U, // SQINCP_XP_D + 2717962181U, // SQINCP_XP_H + 2415972293U, // SQINCP_XP_S + 2147504069U, // SQINCP_ZP_D + 604532677U, // SQINCP_ZP_H + 2147520453U, // SQINCP_ZP_S + 536925365U, // SQINCW_XPiI + 1342231733U, // SQINCW_XPiWdI + 536908981U, // SQINCW_ZPiI + 68200729U, // SQNEGv16i8 + 2248198425U, // SQNEGv1i16 + 2248198425U, // SQNEGv1i32 + 2248198425U, // SQNEGv1i64 + 2248198425U, // SQNEGv1i8 + 68725017U, // SQNEGv2i32 + 2216732953U, // SQNEGv2i64 + 69773593U, // SQNEGv4i16 + 2217781529U, // SQNEGv4i32 + 70822169U, // SQNEGv8i16 + 2218830105U, // SQNEGv8i8 + 369191329U, // SQRDMLAHi16_indexed + 369191329U, // SQRDMLAHi32_indexed + 369191329U, // SQRDMLAHv1i16 + 369191329U, // SQRDMLAHv1i32 + 2283334049U, // SQRDMLAHv2i32 + 2283334049U, // SQRDMLAHv2i32_indexed + 136898977U, // SQRDMLAHv4i16 + 136898977U, // SQRDMLAHv4i16_indexed + 137423265U, // SQRDMLAHv4i32 + 137423265U, // SQRDMLAHv4i32_indexed + 2285431201U, // SQRDMLAHv8i16 + 2285431201U, // SQRDMLAHv8i16_indexed + 369191909U, // SQRDMLSHi16_indexed + 369191909U, // SQRDMLSHi32_indexed + 369191909U, // SQRDMLSHv1i16 + 369191909U, // SQRDMLSHv1i32 + 2283334629U, // SQRDMLSHv2i32 + 2283334629U, // SQRDMLSHv2i32_indexed + 136899557U, // SQRDMLSHv4i16 + 136899557U, // SQRDMLSHv4i16_indexed + 137423845U, // SQRDMLSHv4i32 + 137423845U, // SQRDMLSHv4i32_indexed + 2285431781U, // SQRDMLSHv8i16 + 2285431781U, // SQRDMLSHv8i16_indexed + 100715238U, // SQRDMULHv1i16 + 100715238U, // SQRDMULHv1i16_indexed + 100715238U, // SQRDMULHv1i32 + 100715238U, // SQRDMULHv1i32_indexed + 2216209126U, // SQRDMULHv2i32 + 2216209126U, // SQRDMULHv2i32_indexed + 69774054U, // SQRDMULHv4i16 + 69774054U, // SQRDMULHv4i16_indexed + 70298342U, // SQRDMULHv4i32 + 70298342U, // SQRDMULHv4i32_indexed + 2218306278U, // SQRDMULHv8i16 + 2218306278U, // SQRDMULHv8i16_indexed + 68201885U, // SQRSHLv16i8 + 100715933U, // SQRSHLv1i16 + 100715933U, // SQRSHLv1i32 + 100715933U, // SQRSHLv1i64 + 100715933U, // SQRSHLv1i8 + 2216209821U, // SQRSHLv2i32 + 2216734109U, // SQRSHLv2i64 + 69774749U, // SQRSHLv4i16 + 70299037U, // SQRSHLv4i32 + 2218306973U, // SQRSHLv8i16 + 2218831261U, // SQRSHLv8i8 + 100716319U, // SQRSHRNb + 100716319U, // SQRSHRNh + 100716319U, // SQRSHRNs + 2282807661U, // SQRSHRNv16i8_shift + 2216210207U, // SQRSHRNv2i32_shift + 69775135U, // SQRSHRNv4i16_shift + 2284904813U, // SQRSHRNv4i32_shift + 137945453U, // SQRSHRNv8i16_shift + 2218831647U, // SQRSHRNv8i8_shift + 100716380U, // SQRSHRUNb + 100716380U, // SQRSHRUNh + 100716380U, // SQRSHRUNs + 2282807721U, // SQRSHRUNv16i8_shift + 2216210268U, // SQRSHRUNv2i32_shift + 69775196U, // SQRSHRUNv4i16_shift + 2284904873U, // SQRSHRUNv4i32_shift + 137945513U, // SQRSHRUNv8i16_shift + 2218831708U, // SQRSHRUNv8i8_shift + 100717425U, // SQSHLUb + 100717425U, // SQSHLUd + 100717425U, // SQSHLUh + 100717425U, // SQSHLUs + 68203377U, // SQSHLUv16i8_shift + 2216211313U, // SQSHLUv2i32_shift + 2216735601U, // SQSHLUv2i64_shift + 69776241U, // SQSHLUv4i16_shift + 70300529U, // SQSHLUv4i32_shift + 2218308465U, // SQSHLUv8i16_shift + 2218832753U, // SQSHLUv8i8_shift + 100715919U, // SQSHLb + 100715919U, // SQSHLd + 100715919U, // SQSHLh + 100715919U, // SQSHLs + 68201871U, // SQSHLv16i8 + 68201871U, // SQSHLv16i8_shift + 100715919U, // SQSHLv1i16 + 100715919U, // SQSHLv1i32 + 100715919U, // SQSHLv1i64 + 100715919U, // SQSHLv1i8 + 2216209807U, // SQSHLv2i32 + 2216209807U, // SQSHLv2i32_shift + 2216734095U, // SQSHLv2i64 + 2216734095U, // SQSHLv2i64_shift + 69774735U, // SQSHLv4i16 + 69774735U, // SQSHLv4i16_shift + 70299023U, // SQSHLv4i32 + 70299023U, // SQSHLv4i32_shift + 2218306959U, // SQSHLv8i16 + 2218306959U, // SQSHLv8i16_shift + 2218831247U, // SQSHLv8i8 + 2218831247U, // SQSHLv8i8_shift + 100716303U, // SQSHRNb + 100716303U, // SQSHRNh + 100716303U, // SQSHRNs + 2282807643U, // SQSHRNv16i8_shift + 2216210191U, // SQSHRNv2i32_shift + 69775119U, // SQSHRNv4i16_shift + 2284904795U, // SQSHRNv4i32_shift + 137945435U, // SQSHRNv8i16_shift + 2218831631U, // SQSHRNv8i8_shift + 100716371U, // SQSHRUNb + 100716371U, // SQSHRUNh + 100716371U, // SQSHRUNs + 2282807711U, // SQSHRUNv16i8_shift + 2216210259U, // SQSHRUNv2i32_shift + 69775187U, // SQSHRUNv4i16_shift + 2284904863U, // SQSHRUNv4i32_shift + 137945503U, // SQSHRUNv8i16_shift + 2218831699U, // SQSHRUNv8i8_shift + 167782084U, // SQSUB_ZI_B + 201344708U, // SQSUB_ZI_D + 239625924U, // SQSUB_ZI_H + 268469956U, // SQSUB_ZI_S + 167782084U, // SQSUB_ZZZ_B + 201344708U, // SQSUB_ZZZ_D + 2387109572U, // SQSUB_ZZZ_H + 268469956U, // SQSUB_ZZZ_S + 68200132U, // SQSUBv16i8 + 100714180U, // SQSUBv1i16 + 100714180U, // SQSUBv1i32 + 100714180U, // SQSUBv1i64 + 100714180U, // SQSUBv1i8 + 2216208068U, // SQSUBv2i32 + 2216732356U, // SQSUBv2i64 + 69772996U, // SQSUBv4i16 + 70297284U, // SQSUBv4i32 + 2218305220U, // SQSUBv8i16 + 2218829508U, // SQSUBv8i8 + 135324047U, // SQXTNv16i8 + 2248200005U, // SQXTNv1i16 + 2248200005U, // SQXTNv1i32 + 2248200005U, // SQXTNv1i8 + 2216210245U, // SQXTNv2i32 + 2217258821U, // SQXTNv4i16 + 2284904847U, // SQXTNv4i32 + 2285429135U, // SQXTNv8i16 + 71348037U, // SQXTNv8i8 + 135324084U, // SQXTUNv16i8 + 2248200038U, // SQXTUNv1i16 + 2248200038U, // SQXTUNv1i32 + 2248200038U, // SQXTUNv1i8 + 2216210278U, // SQXTUNv2i32 + 2217258854U, // SQXTUNv4i16 + 2284904884U, // SQXTUNv4i32 + 2285429172U, // SQXTUNv8i16 + 71348070U, // SQXTUNv8i8 + 68200433U, // SRHADDv16i8 + 2216208369U, // SRHADDv2i32 + 69773297U, // SRHADDv4i16 + 70297585U, // SRHADDv4i32 + 2218305521U, // SRHADDv8i16 + 2218829809U, // SRHADDv8i8 + 369192068U, // SRId + 135326852U, // SRIv16i8_shift + 2283334788U, // SRIv2i32_shift + 2283859076U, // SRIv2i64_shift + 136899716U, // SRIv4i16_shift + 137424004U, // SRIv4i32_shift + 2285431940U, // SRIv8i16_shift + 2285956228U, // SRIv8i8_shift + 68201901U, // SRSHLv16i8 + 100715949U, // SRSHLv1i64 + 2216209837U, // SRSHLv2i32 + 2216734125U, // SRSHLv2i64 + 69774765U, // SRSHLv4i16 + 70299053U, // SRSHLv4i32 + 2218306989U, // SRSHLv8i16 + 2218831277U, // SRSHLv8i8 + 100716794U, // SRSHRd + 68202746U, // SRSHRv16i8_shift + 2216210682U, // SRSHRv2i32_shift + 2216734970U, // SRSHRv2i64_shift + 69775610U, // SRSHRv4i16_shift + 70299898U, // SRSHRv4i32_shift + 2218307834U, // SRSHRv8i16_shift + 2218832122U, // SRSHRv8i8_shift + 369189634U, // SRSRAd + 135324418U, // SRSRAv16i8_shift + 2283332354U, // SRSRAv2i32_shift + 2283856642U, // SRSRAv2i64_shift + 136897282U, // SRSRAv4i16_shift + 137421570U, // SRSRAv4i32_shift + 2285429506U, // SRSRAv8i16_shift + 2285953794U, // SRSRAv8i8_shift + 70820085U, // SSHLLv16i8_shift + 2216734151U, // SSHLLv2i32_shift + 70299079U, // SSHLLv4i16_shift + 69247221U, // SSHLLv4i32_shift + 2217779445U, // SSHLLv8i16_shift + 2218307015U, // SSHLLv8i8_shift + 68201915U, // SSHLv16i8 + 100715963U, // SSHLv1i64 + 2216209851U, // SSHLv2i32 + 2216734139U, // SSHLv2i64 + 69774779U, // SSHLv4i16 + 70299067U, // SSHLv4i32 + 2218307003U, // SSHLv8i16 + 2218831291U, // SSHLv8i8 + 100716808U, // SSHRd + 68202760U, // SSHRv16i8_shift + 2216210696U, // SSHRv2i32_shift + 2216734984U, // SSHRv2i64_shift + 69775624U, // SSHRv4i16_shift + 70299912U, // SSHRv4i32_shift + 2218307848U, // SSHRv8i16_shift + 2218832136U, // SSHRv8i8_shift + 369189648U, // SSRAd + 135324432U, // SSRAv16i8_shift + 2283332368U, // SSRAv2i32_shift + 2283856656U, // SSRAv2i64_shift + 136897296U, // SSRAv4i16_shift + 137421584U, // SSRAv4i32_shift + 2285429520U, // SSRAv8i16_shift + 2285953808U, // SSRAv8i8_shift + 374997906U, // SST1B_D + 878314386U, // SST1B_D_IMM + 374997906U, // SST1B_D_SXTW + 374997906U, // SST1B_D_UXTW + 811213714U, // SST1B_S_IMM + 375006098U, // SST1B_S_SXTW + 375006098U, // SST1B_S_UXTW + 374998886U, // SST1D + 878315366U, // SST1D_IMM + 374998886U, // SST1D_SCALED + 374998886U, // SST1D_SXTW + 374998886U, // SST1D_SXTW_SCALED + 374998886U, // SST1D_UXTW + 374998886U, // SST1D_UXTW_SCALED + 374999380U, // SST1H_D + 3025799508U, // SST1H_D_IMM + 374999380U, // SST1H_D_SCALED + 374999380U, // SST1H_D_SXTW + 374999380U, // SST1H_D_SXTW_SCALED + 374999380U, // SST1H_D_UXTW + 374999380U, // SST1H_D_UXTW_SCALED + 2958698836U, // SST1H_S_IMM + 375007572U, // SST1H_S_SXTW + 375007572U, // SST1H_S_SXTW_SCALED + 375007572U, // SST1H_S_UXTW + 375007572U, // SST1H_S_UXTW_SCALED + 375002204U, // SST1W_D + 878318684U, // SST1W_D_IMM + 375002204U, // SST1W_D_SCALED + 375002204U, // SST1W_D_SXTW + 375002204U, // SST1W_D_SXTW_SCALED + 375002204U, // SST1W_D_UXTW + 375002204U, // SST1W_D_UXTW_SCALED + 811218012U, // SST1W_IMM + 375010396U, // SST1W_SXTW + 375010396U, // SST1W_SXTW_SCALED + 375010396U, // SST1W_UXTW + 375010396U, // SST1W_UXTW_SCALED + 70820037U, // SSUBLv16i8_v8i16 + 2216734014U, // SSUBLv2i32_v2i64 + 70298942U, // SSUBLv4i16_v4i32 + 69247173U, // SSUBLv4i32_v2i64 + 2217779397U, // SSUBLv8i16_v4i32 + 2218306878U, // SSUBLv8i8_v8i16 + 2218303966U, // SSUBWv16i8_v8i16 + 2216735886U, // SSUBWv2i32_v2i64 + 70300814U, // SSUBWv4i16_v4i32 + 2216731102U, // SSUBWv4i32_v2i64 + 70296030U, // SSUBWv8i16_v4i32 + 2218308750U, // SSUBWv8i8_v8i16 + 375022482U, // ST1B + 374997906U, // ST1B_D + 374997906U, // ST1B_D_IMM + 375030674U, // ST1B_H + 375030674U, // ST1B_H_IMM + 375022482U, // ST1B_IMM + 375006098U, // ST1B_S + 375006098U, // ST1B_S_IMM + 374998886U, // ST1D + 374998886U, // ST1D_IMM + 172102U, // ST1Fourv16b + 13287494U, // ST1Fourv16b_POST + 188486U, // ST1Fourv1d + 13828166U, // ST1Fourv1d_POST + 204870U, // ST1Fourv2d + 13320262U, // ST1Fourv2d_POST + 221254U, // ST1Fourv2s + 13860934U, // ST1Fourv2s_POST + 237638U, // ST1Fourv4h + 13877318U, // ST1Fourv4h_POST + 254022U, // ST1Fourv4s + 13369414U, // ST1Fourv4s_POST + 270406U, // ST1Fourv8b + 13910086U, // ST1Fourv8b_POST + 286790U, // ST1Fourv8h + 13402182U, // ST1Fourv8h_POST + 375032148U, // ST1H + 374999380U, // ST1H_D + 374999380U, // ST1H_D_IMM + 375032148U, // ST1H_IMM + 375007572U, // ST1H_S + 375007572U, // ST1H_S_IMM + 172102U, // ST1Onev16b + 14336070U, // ST1Onev16b_POST + 188486U, // ST1Onev1d + 14876742U, // ST1Onev1d_POST + 204870U, // ST1Onev2d + 14368838U, // ST1Onev2d_POST + 221254U, // ST1Onev2s + 14909510U, // ST1Onev2s_POST + 237638U, // ST1Onev4h + 14925894U, // ST1Onev4h_POST + 254022U, // ST1Onev4s + 14417990U, // ST1Onev4s_POST + 270406U, // ST1Onev8b + 14958662U, // ST1Onev8b_POST + 286790U, // ST1Onev8h + 14450758U, // ST1Onev8h_POST + 172102U, // ST1Threev16b + 16957510U, // ST1Threev16b_POST + 188486U, // ST1Threev1d + 17498182U, // ST1Threev1d_POST + 204870U, // ST1Threev2d + 16990278U, // ST1Threev2d_POST + 221254U, // ST1Threev2s + 17530950U, // ST1Threev2s_POST + 237638U, // ST1Threev4h + 17547334U, // ST1Threev4h_POST + 254022U, // ST1Threev4s + 17039430U, // ST1Threev4s_POST + 270406U, // ST1Threev8b + 17580102U, // ST1Threev8b_POST + 286790U, // ST1Threev8h + 17072198U, // ST1Threev8h_POST + 172102U, // ST1Twov16b + 13811782U, // ST1Twov16b_POST + 188486U, // ST1Twov1d + 14352454U, // ST1Twov1d_POST + 204870U, // ST1Twov2d + 13844550U, // ST1Twov2d_POST + 221254U, // ST1Twov2s + 14385222U, // ST1Twov2s_POST + 237638U, // ST1Twov4h + 14401606U, // ST1Twov4h_POST + 254022U, // ST1Twov4s + 13893702U, // ST1Twov4s_POST + 270406U, // ST1Twov8b + 14434374U, // ST1Twov8b_POST + 286790U, // ST1Twov8h + 13926470U, // ST1Twov8h_POST + 375010396U, // ST1W + 375002204U, // ST1W_D + 375002204U, // ST1W_D_IMM + 375010396U, // ST1W_IMM + 409670U, // ST1i16 + 1404346438U, // ST1i16_POST + 417862U, // ST1i32 + 1437917254U, // ST1i32_POST + 426054U, // ST1i64 + 1471488070U, // ST1i64_POST + 434246U, // ST1i8 + 1505058886U, // ST1i8_POST + 375022511U, // ST2B + 375022511U, // ST2B_IMM + 374998898U, // ST2D + 374998898U, // ST2D_IMM + 375032177U, // ST2H + 375032177U, // ST2H_IMM + 172505U, // ST2Twov16b + 13812185U, // ST2Twov16b_POST + 205273U, // ST2Twov2d + 13844953U, // ST2Twov2d_POST + 221657U, // ST2Twov2s + 14385625U, // ST2Twov2s_POST + 238041U, // ST2Twov4h + 14402009U, // ST2Twov4h_POST + 254425U, // ST2Twov4s + 13894105U, // ST2Twov4s_POST + 270809U, // ST2Twov8b + 14434777U, // ST2Twov8b_POST + 287193U, // ST2Twov8h + 13926873U, // ST2Twov8h_POST + 375010416U, // ST2W + 375010416U, // ST2W_IMM + 410073U, // ST2i16 + 1437901273U, // ST2i16_POST + 418265U, // ST2i32 + 1471472089U, // ST2i32_POST + 426457U, // ST2i64 + 1538597337U, // ST2i64_POST + 434649U, // ST2i8 + 1404395993U, // ST2i8_POST + 375022532U, // ST3B + 375022532U, // ST3B_IMM + 374998910U, // ST3D + 374998910U, // ST3D_IMM + 375032189U, // ST3H + 375032189U, // ST3H_IMM + 172571U, // ST3Threev16b + 16957979U, // ST3Threev16b_POST + 205339U, // ST3Threev2d + 16990747U, // ST3Threev2d_POST + 221723U, // ST3Threev2s + 17531419U, // ST3Threev2s_POST + 238107U, // ST3Threev4h + 17547803U, // ST3Threev4h_POST + 254491U, // ST3Threev4s + 17039899U, // ST3Threev4s_POST + 270875U, // ST3Threev8b + 17580571U, // ST3Threev8b_POST + 287259U, // ST3Threev8h + 17072667U, // ST3Threev8h_POST + 375010428U, // ST3W + 375010428U, // ST3W_IMM + 410139U, // ST3i16 + 1572119067U, // ST3i16_POST + 418331U, // ST3i32 + 1605689883U, // ST3i32_POST + 426523U, // ST3i64 + 1639260699U, // ST3i64_POST + 434715U, // ST3i8 + 1672831515U, // ST3i8_POST + 375022544U, // ST4B + 375022544U, // ST4B_IMM + 374998922U, // ST4D + 374998922U, // ST4D_IMM + 172588U, // ST4Fourv16b + 13287980U, // ST4Fourv16b_POST + 205356U, // ST4Fourv2d + 13320748U, // ST4Fourv2d_POST + 221740U, // ST4Fourv2s + 13861420U, // ST4Fourv2s_POST + 238124U, // ST4Fourv4h + 13877804U, // ST4Fourv4h_POST + 254508U, // ST4Fourv4s + 13369900U, // ST4Fourv4s_POST + 270892U, // ST4Fourv8b + 13910572U, // ST4Fourv8b_POST + 287276U, // ST4Fourv8h + 13402668U, // ST4Fourv8h_POST + 375032201U, // ST4H + 375032201U, // ST4H_IMM + 375010440U, // ST4W + 375010440U, // ST4W_IMM + 410156U, // ST4i16 + 1471455788U, // ST4i16_POST + 418348U, // ST4i32 + 1538581036U, // ST4i32_POST + 426540U, // ST4i64 + 1706369580U, // ST4i64_POST + 434732U, // ST4i8 + 1437950508U, // ST4i8_POST + 2253964715U, // STLLRB + 2253966166U, // STLLRH + 2253967648U, // STLLRW + 2253967648U, // STLLRX + 2253964723U, // STLRB + 2253966174U, // STLRH + 2253967661U, // STLRW + 2253967661U, // STLRX + 106481125U, // STLURBi + 106482576U, // STLURHi + 106484110U, // STLURWi + 106484110U, // STLURXi + 100716685U, // STLXPW + 100716685U, // STLXPX + 2248197644U, // STLXRB + 2248199095U, // STLXRH + 2248200645U, // STLXRW + 2248200645U, // STLXRX + 2248200251U, // STNPDi + 2248200251U, // STNPQi + 2248200251U, // STNPSi + 2248200251U, // STNPWi + 2248200251U, // STNPXi + 375022474U, // STNT1B_ZRI + 375022474U, // STNT1B_ZRR + 374998878U, // STNT1D_ZRI + 374998878U, // STNT1D_ZRR + 375032140U, // STNT1H_ZRI + 375032140U, // STNT1H_ZRR + 375010388U, // STNT1W_ZRI + 375010388U, // STNT1W_ZRR + 2248200283U, // STPDi + 2516676699U, // STPDpost + 2516676699U, // STPDpre + 2248200283U, // STPQi + 2516676699U, // STPQpost + 2516676699U, // STPQpre + 2248200283U, // STPSi + 2516676699U, // STPSpost + 2516676699U, // STPSpre + 2248200283U, // STPWi + 2516676699U, // STPWpost + 2516676699U, // STPWpre + 2248200283U, // STPXi + 2516676699U, // STPXpost + 2516676699U, // STPXpre + 374957521U, // STRBBpost + 374957521U, // STRBBpre + 106481105U, // STRBBroW + 106481105U, // STRBBroX + 106481105U, // STRBBui + 374960503U, // STRBpost + 374960503U, // STRBpre + 106484087U, // STRBroW + 106484087U, // STRBroX + 106484087U, // STRBui + 374960503U, // STRDpost + 374960503U, // STRDpre + 106484087U, // STRDroW + 106484087U, // STRDroX + 106484087U, // STRDui + 374958972U, // STRHHpost + 374958972U, // STRHHpre + 106482556U, // STRHHroW + 106482556U, // STRHHroX + 106482556U, // STRHHui + 374960503U, // STRHpost + 374960503U, // STRHpre + 106484087U, // STRHroW + 106484087U, // STRHroX + 106484087U, // STRHui + 374960503U, // STRQpost + 374960503U, // STRQpre + 106484087U, // STRQroW + 106484087U, // STRQroX + 106484087U, // STRQui + 374960503U, // STRSpost + 374960503U, // STRSpre + 106484087U, // STRSroW + 106484087U, // STRSroX + 106484087U, // STRSui + 374960503U, // STRWpost + 374960503U, // STRWpre + 106484087U, // STRWroW + 106484087U, // STRWroX + 106484087U, // STRWui + 374960503U, // STRXpost + 374960503U, // STRXpre + 106484087U, // STRXroW + 106484087U, // STRXroX + 106484087U, // STRXui + 106803575U, // STR_PXI + 106803575U, // STR_ZXI + 106481111U, // STTRBi + 106482562U, // STTRHi + 106484092U, // STTRWi + 106484092U, // STTRXi + 106481142U, // STURBBi + 106484125U, // STURBi + 106484125U, // STURDi + 106482593U, // STURHHi + 106484125U, // STURHi + 106484125U, // STURQi + 106484125U, // STURSi + 106484125U, // STURWi + 106484125U, // STURXi + 100716692U, // STXPW + 100716692U, // STXPX + 2248197652U, // STXRB + 2248199103U, // STXRH + 2248200652U, // STXRW + 2248200652U, // STXRX + 2216210137U, // SUBHNv2i64_v2i32 + 2284904778U, // SUBHNv2i64_v4i32 + 69775065U, // SUBHNv4i32_v4i16 + 137945418U, // SUBHNv4i32_v8i16 + 2282807626U, // SUBHNv8i16_v16i8 + 2218831577U, // SUBHNv8i16_v8i8 + 167784668U, // SUBR_ZI_B + 201347292U, // SUBR_ZI_D + 239628508U, // SUBR_ZI_H + 268472540U, // SUBR_ZI_S + 302002396U, // SUBR_ZPmZ_B + 302010588U, // SUBR_ZPmZ_D + 2186309852U, // SUBR_ZPmZ_H + 302026972U, // SUBR_ZPmZ_S + 100717066U, // SUBSWri + 0U, // SUBSWrr + 100717066U, // SUBSWrs + 100717066U, // SUBSWrx + 100717066U, // SUBSXri + 0U, // SUBSXrr + 100717066U, // SUBSXrs + 100717066U, // SUBSXrx + 100717066U, // SUBSXrx64 + 100714146U, // SUBWri + 0U, // SUBWrr + 100714146U, // SUBWrs + 100714146U, // SUBWrx + 100714146U, // SUBXri + 0U, // SUBXrr + 100714146U, // SUBXrs + 100714146U, // SUBXrx + 100714146U, // SUBXrx64 + 167782050U, // SUB_ZI_B + 201344674U, // SUB_ZI_D + 239625890U, // SUB_ZI_H + 268469922U, // SUB_ZI_S + 301999778U, // SUB_ZPmZ_B + 302007970U, // SUB_ZPmZ_D + 2186307234U, // SUB_ZPmZ_H + 302024354U, // SUB_ZPmZ_S + 167782050U, // SUB_ZZZ_B + 201344674U, // SUB_ZZZ_D + 2387109538U, // SUB_ZZZ_H + 268469922U, // SUB_ZZZ_S + 68200098U, // SUBv16i8 + 100714146U, // SUBv1i64 + 2216208034U, // SUBv2i32 + 2216732322U, // SUBv2i64 + 69772962U, // SUBv4i16 + 70297250U, // SUBv4i32 + 2218305186U, // SUBv8i16 + 2218829474U, // SUBv8i8 + 2415938650U, // SUNPKHI_ZZ_D + 27290714U, // SUNPKHI_ZZ_H + 2717944922U, // SUNPKHI_ZZ_S + 2415939470U, // SUNPKLO_ZZ_D + 27291534U, // SUNPKLO_ZZ_H + 2717945742U, // SUNPKLO_ZZ_S + 135325734U, // SUQADDv16i8 + 2516674598U, // SUQADDv1i16 + 2516674598U, // SUQADDv1i32 + 2516674598U, // SUQADDv1i64 + 2516674598U, // SUQADDv1i8 + 135850022U, // SUQADDv2i32 + 2283857958U, // SUQADDv2i64 + 136898598U, // SUQADDv4i16 + 2284906534U, // SUQADDv4i32 + 137947174U, // SUQADDv8i16 + 2285955110U, // SUQADDv8i8 + 75579U, // SVC + 973169651U, // SWPAB + 973171135U, // SWPAH + 973169853U, // SWPALB + 973171283U, // SWPALH + 973171948U, // SWPALW + 973171948U, // SWPALX + 973169381U, // SWPAW + 973169381U, // SWPAX + 973170041U, // SWPB + 973171492U, // SWPH + 973169950U, // SWPLB + 973171380U, // SWPLH + 973172243U, // SWPLW + 973172243U, // SWPLX + 973172838U, // SWPW + 973172838U, // SWPX + 18069U, // SXTB_ZPmZ_D + 2181588629U, // SXTB_ZPmZ_H + 34453U, // SXTB_ZPmZ_S + 19494U, // SXTH_ZPmZ_D + 35878U, // SXTH_ZPmZ_S + 21815U, // SXTW_ZPmZ_D + 100716107U, // SYSLxt + 1711329984U, // SYSxt + 1744842025U, // TBL_ZZZ_B + 1778404649U, // TBL_ZZZ_D + 28863785U, // TBL_ZZZ_H + 1811975465U, // TBL_ZZZ_S + 1846586665U, // TBLv16i8Four + 1846586665U, // TBLv16i8One + 1846586665U, // TBLv16i8Three + 1846586665U, // TBLv16i8Two + 3997216041U, // TBLv8i8Four + 3997216041U, // TBLv8i8One + 3997216041U, // TBLv8i8Three + 3997216041U, // TBLv8i8Two + 100718059U, // TBNZW + 100718059U, // TBNZX + 1880159597U, // TBXv16i8Four + 1880159597U, // TBXv16i8One + 1880159597U, // TBXv16i8Three + 1880159597U, // TBXv16i8Two + 4030788973U, // TBXv8i8Four + 4030788973U, // TBXv8i8One + 4030788973U, // TBXv8i8Three + 4030788973U, // TBXv8i8Two + 100718043U, // TBZW + 100718043U, // TBZX + 0U, // TCRETURNdi + 0U, // TCRETURNri + 6346239U, // TLSDESCCALL + 0U, // TLSDESC_CALLSEQ + 167780389U, // TRN1_PPP_B + 201343013U, // TRN1_PPP_D + 2387107877U, // TRN1_PPP_H + 268468261U, // TRN1_PPP_S + 167780389U, // TRN1_ZZZ_B + 201343013U, // TRN1_ZZZ_D + 2387107877U, // TRN1_ZZZ_H + 268468261U, // TRN1_ZZZ_S + 68198437U, // TRN1v16i8 + 2216206373U, // TRN1v2i32 + 2216730661U, // TRN1v2i64 + 69771301U, // TRN1v4i16 + 70295589U, // TRN1v4i32 + 2218303525U, // TRN1v8i16 + 2218827813U, // TRN1v8i8 + 167780737U, // TRN2_PPP_B + 201343361U, // TRN2_PPP_D + 2387108225U, // TRN2_PPP_H + 268468609U, // TRN2_PPP_S + 167780737U, // TRN2_ZZZ_B + 201343361U, // TRN2_ZZZ_D + 2387108225U, // TRN2_ZZZ_H + 268468609U, // TRN2_ZZZ_S + 68198785U, // TRN2v16i8 + 2216206721U, // TRN2v2i32 + 2216731009U, // TRN2v2i64 + 69771649U, // TRN2v4i16 + 70295937U, // TRN2v4i32 + 2218303873U, // TRN2v8i16 + 2218828161U, // TRN2v8i8 + 116346U, // TSB + 137945251U, // UABALv16i8_v8i16 + 2283859113U, // UABALv2i32_v2i64 + 137424041U, // UABALv4i16_v4i32 + 136372387U, // UABALv4i32_v2i64 + 2284904611U, // UABALv8i16_v4i32 + 2285431977U, // UABALv8i8_v8i16 + 135324275U, // UABAv16i8 + 2283332211U, // UABAv2i32 + 136897139U, // UABAv4i16 + 137421427U, // UABAv4i32 + 2285429363U, // UABAv8i16 + 2285953651U, // UABAv8i8 + 70820061U, // UABDLv16i8_v8i16 + 2216734035U, // UABDLv2i32_v2i64 + 70298963U, // UABDLv4i16_v4i32 + 69247197U, // UABDLv4i32_v2i64 + 2217779421U, // UABDLv8i16_v4i32 + 2218306899U, // UABDLv8i8_v8i16 + 302000048U, // UABD_ZPmZ_B + 302008240U, // UABD_ZPmZ_D + 2186307504U, // UABD_ZPmZ_H + 302024624U, // UABD_ZPmZ_S + 68200368U, // UABDv16i8 + 2216208304U, // UABDv2i32 + 69773232U, // UABDv4i16 + 70297520U, // UABDv4i32 + 2218305456U, // UABDv8i16 + 2218829744U, // UABDv8i8 + 137949161U, // UADALPv16i8_v8i16 + 162066409U, // UADALPv2i32_v1i64 + 135852009U, // UADALPv4i16_v2i32 + 2283859945U, // UADALPv4i32_v2i64 + 137424873U, // UADALPv8i16_v4i32 + 2284384233U, // UADALPv8i8_v4i16 + 70823929U, // UADDLPv16i8_v8i16 + 94941177U, // UADDLPv2i32_v1i64 + 68726777U, // UADDLPv4i16_v2i32 + 2216734713U, // UADDLPv4i32_v2i64 + 70299641U, // UADDLPv8i16_v4i32 + 2217259001U, // UADDLPv8i8_v4i16 + 67163091U, // UADDLVv16i8v + 67163091U, // UADDLVv4i16v + 2214646739U, // UADDLVv4i32v + 67163091U, // UADDLVv8i16v + 2214646739U, // UADDLVv8i8v + 70820077U, // UADDLv16i8_v8i16 + 2216734073U, // UADDLv2i32_v2i64 + 70299001U, // UADDLv4i16_v4i32 + 69247213U, // UADDLv4i32_v2i64 + 2217779437U, // UADDLv8i16_v4i32 + 2218306937U, // UADDLv8i8_v8i16 + 302044071U, // UADDV_VPZ_B + 302044071U, // UADDV_VPZ_D + 302044071U, // UADDV_VPZ_H + 302044071U, // UADDV_VPZ_S + 2218303990U, // UADDWv16i8_v8i16 + 2216735948U, // UADDWv2i32_v2i64 + 70300876U, // UADDWv4i16_v4i32 + 2216731126U, // UADDWv4i32_v2i64 + 70296054U, // UADDWv8i16_v4i32 + 2218308812U, // UADDWv8i8_v8i16 + 100716199U, // UBFMWri + 100716199U, // UBFMXri + 100714764U, // UCVTFSWDri + 100714764U, // UCVTFSWHri + 100714764U, // UCVTFSWSri + 100714764U, // UCVTFSXDri + 100714764U, // UCVTFSXHri + 100714764U, // UCVTFSXSri + 2248198412U, // UCVTFUWDri + 2248198412U, // UCVTFUWHri + 2248198412U, // UCVTFUWSri + 2248198412U, // UCVTFUXDri + 2248198412U, // UCVTFUXHri + 2248198412U, // UCVTFUXSri + 18700U, // UCVTF_ZPmZ_DtoD + 2181589260U, // UCVTF_ZPmZ_DtoH + 35084U, // UCVTF_ZPmZ_DtoS + 2181589260U, // UCVTF_ZPmZ_HtoH + 18700U, // UCVTF_ZPmZ_StoD + 2181589260U, // UCVTF_ZPmZ_StoH + 35084U, // UCVTF_ZPmZ_StoS + 100714764U, // UCVTFd + 100714764U, // UCVTFh + 100714764U, // UCVTFs + 2248198412U, // UCVTFv1i16 + 2248198412U, // UCVTFv1i32 + 2248198412U, // UCVTFv1i64 + 68725004U, // UCVTFv2f32 + 2216732940U, // UCVTFv2f64 + 2216208652U, // UCVTFv2i32_shift + 2216732940U, // UCVTFv2i64_shift + 69773580U, // UCVTFv4f16 + 2217781516U, // UCVTFv4f32 + 69773580U, // UCVTFv4i16_shift + 70297868U, // UCVTFv4i32_shift + 70822156U, // UCVTFv8f16 + 2218305804U, // UCVTFv8i16_shift + 302010801U, // UDIVR_ZPmZ_D + 302027185U, // UDIVR_ZPmZ_S + 100717509U, // UDIVWr + 100717509U, // UDIVXr + 302011333U, // UDIV_ZPmZ_D + 302027717U, // UDIV_ZPmZ_S + 3422573363U, // UDOT_ZZZI_D + 3456144179U, // UDOT_ZZZI_S + 3422573363U, // UDOT_ZZZ_D + 3456144179U, // UDOT_ZZZ_S + 137425715U, // UDOTlanev16i8 + 2283336499U, // UDOTlanev8i8 + 137425715U, // UDOTv16i8 + 2283336499U, // UDOTv8i8 + 68200456U, // UHADDv16i8 + 2216208392U, // UHADDv2i32 + 69773320U, // UHADDv4i16 + 70297608U, // UHADDv4i32 + 2218305544U, // UHADDv8i16 + 2218829832U, // UHADDv8i8 + 68200110U, // UHSUBv16i8 + 2216208046U, // UHSUBv2i32 + 69772974U, // UHSUBv4i16 + 70297262U, // UHSUBv4i32 + 2218305198U, // UHSUBv8i16 + 2218829486U, // UHSUBv8i8 + 100715882U, // UMADDLrrr + 68202624U, // UMAXPv16i8 + 2216210560U, // UMAXPv2i32 + 69775488U, // UMAXPv4i16 + 70299776U, // UMAXPv4i32 + 2218307712U, // UMAXPv8i16 + 2218832000U, // UMAXPv8i8 + 302044207U, // UMAXV_VPZ_B + 302044207U, // UMAXV_VPZ_D + 302044207U, // UMAXV_VPZ_H + 302044207U, // UMAXV_VPZ_S + 67163183U, // UMAXVv16i8v + 67163183U, // UMAXVv4i16v + 2214646831U, // UMAXVv4i32v + 67163183U, // UMAXVv8i16v + 2214646831U, // UMAXVv8i8v + 167785831U, // UMAX_ZI_B + 201348455U, // UMAX_ZI_D + 239629671U, // UMAX_ZI_H + 268473703U, // UMAX_ZI_S + 302003559U, // UMAX_ZPmZ_B + 302011751U, // UMAX_ZPmZ_D + 2186311015U, // UMAX_ZPmZ_H + 302028135U, // UMAX_ZPmZ_S + 68203879U, // UMAXv16i8 + 2216211815U, // UMAXv2i32 + 69776743U, // UMAXv4i16 + 70301031U, // UMAXv4i32 + 2218308967U, // UMAXv8i16 + 2218833255U, // UMAXv8i8 + 68202548U, // UMINPv16i8 + 2216210484U, // UMINPv2i32 + 69775412U, // UMINPv4i16 + 70299700U, // UMINPv4i32 + 2218307636U, // UMINPv8i16 + 2218831924U, // UMINPv8i8 + 302044155U, // UMINV_VPZ_B + 302044155U, // UMINV_VPZ_D + 302044155U, // UMINV_VPZ_H + 302044155U, // UMINV_VPZ_S + 67163131U, // UMINVv16i8v + 67163131U, // UMINVv4i16v + 2214646779U, // UMINVv4i32v + 67163131U, // UMINVv8i16v + 2214646779U, // UMINVv8i8v + 167784184U, // UMIN_ZI_B + 201346808U, // UMIN_ZI_D + 239628024U, // UMIN_ZI_H + 268472056U, // UMIN_ZI_S + 302001912U, // UMIN_ZPmZ_B + 302010104U, // UMIN_ZPmZ_D + 2186309368U, // UMIN_ZPmZ_H + 302026488U, // UMIN_ZPmZ_S + 68202232U, // UMINv16i8 + 2216210168U, // UMINv2i32 + 69775096U, // UMINv4i16 + 70299384U, // UMINv4i32 + 2218307320U, // UMINv8i16 + 2218831608U, // UMINv8i8 + 137945277U, // UMLALv16i8_v8i16 + 2283859145U, // UMLALv2i32_indexed + 2283859145U, // UMLALv2i32_v2i64 + 137424073U, // UMLALv4i16_indexed + 137424073U, // UMLALv4i16_v4i32 + 136372413U, // UMLALv4i32_indexed + 136372413U, // UMLALv4i32_v2i64 + 2284904637U, // UMLALv8i16_indexed + 2284904637U, // UMLALv8i16_v4i32 + 2285432009U, // UMLALv8i8_v8i16 + 137945401U, // UMLSLv16i8_v8i16 + 2283859524U, // UMLSLv2i32_indexed + 2283859524U, // UMLSLv2i32_v2i64 + 137424452U, // UMLSLv4i16_indexed + 137424452U, // UMLSLv4i16_v4i32 + 136372537U, // UMLSLv4i32_indexed + 136372537U, // UMLSLv4i32_v2i64 + 2284904761U, // UMLSLv8i16_indexed + 2284904761U, // UMLSLv8i16_v4i32 + 2285432388U, // UMLSLv8i8_v8i16 + 67163157U, // UMOVvi16 + 2214646805U, // UMOVvi32 + 67163157U, // UMOVvi64 + 2214646805U, // UMOVvi8 + 100715830U, // UMSUBLrrr + 302000887U, // UMULH_ZPmZ_B + 302009079U, // UMULH_ZPmZ_D + 2186308343U, // UMULH_ZPmZ_H + 302025463U, // UMULH_ZPmZ_S + 100715255U, // UMULHrr + 70820127U, // UMULLv16i8_v8i16 + 2216734188U, // UMULLv2i32_indexed + 2216734188U, // UMULLv2i32_v2i64 + 70299116U, // UMULLv4i16_indexed + 70299116U, // UMULLv4i16_v4i32 + 69247263U, // UMULLv4i32_indexed + 69247263U, // UMULLv4i32_v2i64 + 2217779487U, // UMULLv8i16_indexed + 2217779487U, // UMULLv8i16_v4i32 + 2218307052U, // UMULLv8i8_v8i16 + 167782439U, // UQADD_ZI_B + 201345063U, // UQADD_ZI_D + 239626279U, // UQADD_ZI_H + 268470311U, // UQADD_ZI_S + 167782439U, // UQADD_ZZZ_B + 201345063U, // UQADD_ZZZ_D + 2387109927U, // UQADD_ZZZ_H + 268470311U, // UQADD_ZZZ_S + 68200487U, // UQADDv16i8 + 100714535U, // UQADDv1i16 + 100714535U, // UQADDv1i32 + 100714535U, // UQADDv1i64 + 100714535U, // UQADDv1i8 + 2216208423U, // UQADDv2i32 + 2216732711U, // UQADDv2i64 + 69773351U, // UQADDv4i16 + 70297639U, // UQADDv4i32 + 2218305575U, // UQADDv8i16 + 2218829863U, // UQADDv8i8 + 536921173U, // UQDECB_WPiI + 536921173U, // UQDECB_XPiI + 536922053U, // UQDECD_WPiI + 536922053U, // UQDECD_XPiI + 536889285U, // UQDECD_ZPiI + 536922637U, // UQDECH_WPiI + 536922637U, // UQDECH_XPiI + 6842893U, // UQDECH_ZPiI + 2315308989U, // UQDECP_WP_B + 2348863421U, // UQDECP_WP_D + 2717962173U, // UQDECP_WP_H + 2415972285U, // UQDECP_WP_S + 2315308989U, // UQDECP_XP_B + 2348863421U, // UQDECP_XP_D + 2717962173U, // UQDECP_XP_H + 2415972285U, // UQDECP_XP_S + 2147504061U, // UQDECP_ZP_D + 604532669U, // UQDECP_ZP_H + 2147520445U, // UQDECP_ZP_S + 536925357U, // UQDECW_WPiI + 536925357U, // UQDECW_XPiI + 536908973U, // UQDECW_ZPiI + 536921189U, // UQINCB_WPiI + 536921189U, // UQINCB_XPiI + 536922069U, // UQINCD_WPiI + 536922069U, // UQINCD_XPiI + 536889301U, // UQINCD_ZPiI + 536922653U, // UQINCH_WPiI + 536922653U, // UQINCH_XPiI + 6842909U, // UQINCH_ZPiI + 2315309005U, // UQINCP_WP_B + 2348863437U, // UQINCP_WP_D + 2717962189U, // UQINCP_WP_H + 2415972301U, // UQINCP_WP_S + 2315309005U, // UQINCP_XP_B + 2348863437U, // UQINCP_XP_D + 2717962189U, // UQINCP_XP_H + 2415972301U, // UQINCP_XP_S + 2147504077U, // UQINCP_ZP_D + 604532685U, // UQINCP_ZP_H + 2147520461U, // UQINCP_ZP_S + 536925373U, // UQINCW_WPiI + 536925373U, // UQINCW_XPiI + 536908989U, // UQINCW_ZPiI + 68201893U, // UQRSHLv16i8 + 100715941U, // UQRSHLv1i16 + 100715941U, // UQRSHLv1i32 + 100715941U, // UQRSHLv1i64 + 100715941U, // UQRSHLv1i8 + 2216209829U, // UQRSHLv2i32 + 2216734117U, // UQRSHLv2i64 + 69774757U, // UQRSHLv4i16 + 70299045U, // UQRSHLv4i32 + 2218306981U, // UQRSHLv8i16 + 2218831269U, // UQRSHLv8i8 + 100716328U, // UQRSHRNb + 100716328U, // UQRSHRNh + 100716328U, // UQRSHRNs + 2282807671U, // UQRSHRNv16i8_shift + 2216210216U, // UQRSHRNv2i32_shift + 69775144U, // UQRSHRNv4i16_shift + 2284904823U, // UQRSHRNv4i32_shift + 137945463U, // UQRSHRNv8i16_shift + 2218831656U, // UQRSHRNv8i8_shift + 100715926U, // UQSHLb + 100715926U, // UQSHLd + 100715926U, // UQSHLh + 100715926U, // UQSHLs + 68201878U, // UQSHLv16i8 + 68201878U, // UQSHLv16i8_shift + 100715926U, // UQSHLv1i16 + 100715926U, // UQSHLv1i32 + 100715926U, // UQSHLv1i64 + 100715926U, // UQSHLv1i8 + 2216209814U, // UQSHLv2i32 + 2216209814U, // UQSHLv2i32_shift + 2216734102U, // UQSHLv2i64 + 2216734102U, // UQSHLv2i64_shift + 69774742U, // UQSHLv4i16 + 69774742U, // UQSHLv4i16_shift + 70299030U, // UQSHLv4i32 + 70299030U, // UQSHLv4i32_shift + 2218306966U, // UQSHLv8i16 + 2218306966U, // UQSHLv8i16_shift + 2218831254U, // UQSHLv8i8 + 2218831254U, // UQSHLv8i8_shift + 100716311U, // UQSHRNb + 100716311U, // UQSHRNh + 100716311U, // UQSHRNs + 2282807652U, // UQSHRNv16i8_shift + 2216210199U, // UQSHRNv2i32_shift + 69775127U, // UQSHRNv4i16_shift + 2284904804U, // UQSHRNv4i32_shift + 137945444U, // UQSHRNv8i16_shift + 2218831639U, // UQSHRNv8i8_shift + 167782091U, // UQSUB_ZI_B + 201344715U, // UQSUB_ZI_D + 239625931U, // UQSUB_ZI_H + 268469963U, // UQSUB_ZI_S + 167782091U, // UQSUB_ZZZ_B + 201344715U, // UQSUB_ZZZ_D + 2387109579U, // UQSUB_ZZZ_H + 268469963U, // UQSUB_ZZZ_S + 68200139U, // UQSUBv16i8 + 100714187U, // UQSUBv1i16 + 100714187U, // UQSUBv1i32 + 100714187U, // UQSUBv1i64 + 100714187U, // UQSUBv1i8 + 2216208075U, // UQSUBv2i32 + 2216732363U, // UQSUBv2i64 + 69773003U, // UQSUBv4i16 + 70297291U, // UQSUBv4i32 + 2218305227U, // UQSUBv8i16 + 2218829515U, // UQSUBv8i8 + 135324055U, // UQXTNv16i8 + 2248200012U, // UQXTNv1i16 + 2248200012U, // UQXTNv1i32 + 2248200012U, // UQXTNv1i8 + 2216210252U, // UQXTNv2i32 + 2217258828U, // UQXTNv4i16 + 2284904855U, // UQXTNv4i32 + 2285429143U, // UQXTNv8i16 + 71348044U, // UQXTNv8i8 + 68724924U, // URECPEv2i32 + 2217781436U, // URECPEv4i32 + 68200441U, // URHADDv16i8 + 2216208377U, // URHADDv2i32 + 69773305U, // URHADDv4i16 + 70297593U, // URHADDv4i32 + 2218305529U, // URHADDv8i16 + 2218829817U, // URHADDv8i8 + 68201908U, // URSHLv16i8 + 100715956U, // URSHLv1i64 + 2216209844U, // URSHLv2i32 + 2216734132U, // URSHLv2i64 + 69774772U, // URSHLv4i16 + 70299060U, // URSHLv4i32 + 2218306996U, // URSHLv8i16 + 2218831284U, // URSHLv8i8 + 100716801U, // URSHRd + 68202753U, // URSHRv16i8_shift + 2216210689U, // URSHRv2i32_shift + 2216734977U, // URSHRv2i64_shift + 69775617U, // URSHRv4i16_shift + 70299905U, // URSHRv4i32_shift + 2218307841U, // URSHRv8i16_shift + 2218832129U, // URSHRv8i8_shift + 68724970U, // URSQRTEv2i32 + 2217781482U, // URSQRTEv4i32 + 369189641U, // URSRAd + 135324425U, // URSRAv16i8_shift + 2283332361U, // URSRAv2i32_shift + 2283856649U, // URSRAv2i64_shift + 136897289U, // URSRAv4i16_shift + 137421577U, // URSRAv4i32_shift + 2285429513U, // URSRAv8i16_shift + 2285953801U, // URSRAv8i8_shift + 70820093U, // USHLLv16i8_shift + 2216734158U, // USHLLv2i32_shift + 70299086U, // USHLLv4i16_shift + 69247229U, // USHLLv4i32_shift + 2217779453U, // USHLLv8i16_shift + 2218307022U, // USHLLv8i8_shift + 68201921U, // USHLv16i8 + 100715969U, // USHLv1i64 + 2216209857U, // USHLv2i32 + 2216734145U, // USHLv2i64 + 69774785U, // USHLv4i16 + 70299073U, // USHLv4i32 + 2218307009U, // USHLv8i16 + 2218831297U, // USHLv8i8 + 100716814U, // USHRd + 68202766U, // USHRv16i8_shift + 2216210702U, // USHRv2i32_shift + 2216734990U, // USHRv2i64_shift + 69775630U, // USHRv4i16_shift + 70299918U, // USHRv4i32_shift + 2218307854U, // USHRv8i16_shift + 2218832142U, // USHRv8i8_shift + 135325726U, // USQADDv16i8 + 2516674590U, // USQADDv1i16 + 2516674590U, // USQADDv1i32 + 2516674590U, // USQADDv1i64 + 2516674590U, // USQADDv1i8 + 135850014U, // USQADDv2i32 + 2283857950U, // USQADDv2i64 + 136898590U, // USQADDv4i16 + 2284906526U, // USQADDv4i32 + 137947166U, // USQADDv8i16 + 2285955102U, // USQADDv8i8 + 369189654U, // USRAd + 135324438U, // USRAv16i8_shift + 2283332374U, // USRAv2i32_shift + 2283856662U, // USRAv2i64_shift + 136897302U, // USRAv4i16_shift + 137421590U, // USRAv4i32_shift + 2285429526U, // USRAv8i16_shift + 2285953814U, // USRAv8i8_shift + 70820045U, // USUBLv16i8_v8i16 + 2216734021U, // USUBLv2i32_v2i64 + 70298949U, // USUBLv4i16_v4i32 + 69247181U, // USUBLv4i32_v2i64 + 2217779405U, // USUBLv8i16_v4i32 + 2218306885U, // USUBLv8i8_v8i16 + 2218303974U, // USUBWv16i8_v8i16 + 2216735893U, // USUBWv2i32_v2i64 + 70300821U, // USUBWv4i16_v4i32 + 2216731110U, // USUBWv4i32_v2i64 + 70296038U, // USUBWv8i16_v4i32 + 2218308757U, // USUBWv8i8_v8i16 + 2415938659U, // UUNPKHI_ZZ_D + 27290723U, // UUNPKHI_ZZ_H + 2717944931U, // UUNPKHI_ZZ_S + 2415939479U, // UUNPKLO_ZZ_D + 27291543U, // UUNPKLO_ZZ_H + 2717945751U, // UUNPKLO_ZZ_S + 18075U, // UXTB_ZPmZ_D + 2181588635U, // UXTB_ZPmZ_H + 34459U, // UXTB_ZPmZ_S + 19500U, // UXTH_ZPmZ_D + 35884U, // UXTH_ZPmZ_S + 21821U, // UXTW_ZPmZ_D + 167780401U, // UZP1_PPP_B + 201343025U, // UZP1_PPP_D + 2387107889U, // UZP1_PPP_H + 268468273U, // UZP1_PPP_S + 167780401U, // UZP1_ZZZ_B + 201343025U, // UZP1_ZZZ_D + 2387107889U, // UZP1_ZZZ_H + 268468273U, // UZP1_ZZZ_S + 68198449U, // UZP1v16i8 + 2216206385U, // UZP1v2i32 + 2216730673U, // UZP1v2i64 + 69771313U, // UZP1v4i16 + 70295601U, // UZP1v4i32 + 2218303537U, // UZP1v8i16 + 2218827825U, // UZP1v8i8 + 167780812U, // UZP2_PPP_B + 201343436U, // UZP2_PPP_D + 2387108300U, // UZP2_PPP_H + 268468684U, // UZP2_PPP_S + 167780812U, // UZP2_ZZZ_B + 201343436U, // UZP2_ZZZ_D + 2387108300U, // UZP2_ZZZ_H + 268468684U, // UZP2_ZZZ_S + 68198860U, // UZP2v16i8 + 2216206796U, // UZP2v2i32 + 2216731084U, // UZP2v2i64 + 69771724U, // UZP2v4i16 + 70296012U, // UZP2v4i32 + 2218303948U, // UZP2v8i16 + 2218828236U, // UZP2v8i8 + 100673670U, // WHILELE_PWW_B + 100681862U, // WHILELE_PWW_D + 242772102U, // WHILELE_PWW_H + 100698246U, // WHILELE_PWW_S + 100673670U, // WHILELE_PXX_B + 100681862U, // WHILELE_PXX_D + 242772102U, // WHILELE_PXX_H + 100698246U, // WHILELE_PXX_S + 100675452U, // WHILELO_PWW_B + 100683644U, // WHILELO_PWW_D + 242773884U, // WHILELO_PWW_H + 100700028U, // WHILELO_PWW_S + 100675452U, // WHILELO_PXX_B + 100683644U, // WHILELO_PXX_D + 242773884U, // WHILELO_PXX_H + 100700028U, // WHILELO_PXX_S + 100676169U, // WHILELS_PWW_B + 100684361U, // WHILELS_PWW_D + 242774601U, // WHILELS_PWW_H + 100700745U, // WHILELS_PWW_S + 100676169U, // WHILELS_PXX_B + 100684361U, // WHILELS_PXX_D + 242774601U, // WHILELS_PXX_H + 100700745U, // WHILELS_PXX_S + 100676358U, // WHILELT_PWW_B + 100684550U, // WHILELT_PWW_D + 242774790U, // WHILELT_PWW_H + 100700934U, // WHILELT_PWW_S + 100676358U, // WHILELT_PXX_B + 100684550U, // WHILELT_PXX_D + 242774790U, // WHILELT_PXX_H + 100700934U, // WHILELT_PXX_S + 6303987U, // WRFFR + 2216734934U, // XAR + 6342582U, // XPACD + 6343754U, // XPACI + 5905U, // XPACLRI + 135324049U, // XTNv16i8 + 2216210247U, // XTNv2i32 + 2217258823U, // XTNv4i16 + 2284904849U, // XTNv4i32 + 2285429137U, // XTNv8i16 + 71348039U, // XTNv8i8 + 167780395U, // ZIP1_PPP_B + 201343019U, // ZIP1_PPP_D + 2387107883U, // ZIP1_PPP_H + 268468267U, // ZIP1_PPP_S + 167780395U, // ZIP1_ZZZ_B + 201343019U, // ZIP1_ZZZ_D + 2387107883U, // ZIP1_ZZZ_H + 268468267U, // ZIP1_ZZZ_S + 68198443U, // ZIP1v16i8 + 2216206379U, // ZIP1v2i32 + 2216730667U, // ZIP1v2i64 + 69771307U, // ZIP1v4i16 + 70295595U, // ZIP1v4i32 + 2218303531U, // ZIP1v8i16 + 2218827819U, // ZIP1v8i8 + 167780806U, // ZIP2_PPP_B + 201343430U, // ZIP2_PPP_D + 2387108294U, // ZIP2_PPP_H + 268468678U, // ZIP2_PPP_S + 167780806U, // ZIP2_ZZZ_B + 201343430U, // ZIP2_ZZZ_D + 2387108294U, // ZIP2_ZZZ_H + 268468678U, // ZIP2_ZZZ_S + 68198854U, // ZIP2v16i8 + 2216206790U, // ZIP2v2i32 + 2216731078U, // ZIP2v2i64 + 69771718U, // ZIP2v4i16 + 70296006U, // ZIP2v4i32 + 2218303942U, // ZIP2v8i16 + 2218828230U, // ZIP2v8i8 + 302003021U, // anonymous_1349 }; static const uint32_t OpInfo1[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 0U, // DBG_VALUE - 0U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 0U, // BUNDLE - 0U, // LIFETIME_START - 0U, // LIFETIME_END - 0U, // STACKMAP - 0U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 0U, // PATCHABLE_FUNCTION_ENTER - 0U, // PATCHABLE_RET - 0U, // PATCHABLE_FUNCTION_EXIT - 0U, // PATCHABLE_TAIL_CALL - 0U, // PATCHABLE_EVENT_CALL - 0U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDE - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SSUBO - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_BSWAP - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 0U, // ABS_ZPmZ_B - 64U, // ABS_ZPmZ_D - 128U, // ABS_ZPmZ_H - 192U, // ABS_ZPmZ_S - 1U, // ABSv16i8 - 1U, // ABSv1i64 - 2U, // ABSv2i32 - 2U, // ABSv2i64 - 3U, // ABSv4i16 - 3U, // ABSv4i32 - 4U, // ABSv8i16 - 4U, // ABSv8i8 - 261U, // ADCSWr - 261U, // ADCSXr - 261U, // ADCWr - 261U, // ADCXr - 8517U, // ADDHNv2i64_v2i32 - 8581U, // ADDHNv2i64_v4i32 - 16710U, // ADDHNv4i32_v4i16 - 16774U, // ADDHNv4i32_v8i16 - 24966U, // ADDHNv8i16_v16i8 - 24902U, // ADDHNv8i16_v8i8 - 261U, // ADDPL_XXI - 33095U, // ADDPv16i8 - 41287U, // ADDPv2i32 - 8517U, // ADDPv2i64 - 2U, // ADDPv2i64p - 49480U, // ADDPv4i16 - 16710U, // ADDPv4i32 - 24902U, // ADDPv8i16 - 57672U, // ADDPv8i8 - 453U, // ADDSWri - 0U, // ADDSWrr - 517U, // ADDSWrs - 581U, // ADDSWrx - 453U, // ADDSXri - 0U, // ADDSXrr - 517U, // ADDSXrs - 581U, // ADDSXrx - 65797U, // ADDSXrx64 - 261U, // ADDVL_XXI - 1U, // ADDVv16i8v - 3U, // ADDVv4i16v - 3U, // ADDVv4i32v - 4U, // ADDVv8i16v - 4U, // ADDVv8i8v - 453U, // ADDWri - 0U, // ADDWrr - 517U, // ADDWrs - 581U, // ADDWrx - 453U, // ADDXri - 0U, // ADDXrr - 517U, // ADDXrs - 581U, // ADDXrx - 65797U, // ADDXrx64 - 645U, // ADD_ZI_B - 709U, // ADD_ZI_D - 9U, // ADD_ZI_H - 773U, // ADD_ZI_S - 74560U, // ADD_ZPmZ_B - 598912U, // ADD_ZPmZ_D - 1131465U, // ADD_ZPmZ_H - 1647616U, // ADD_ZPmZ_S - 837U, // ADD_ZZZ_B - 901U, // ADD_ZZZ_D - 137U, // ADD_ZZZ_H - 1029U, // ADD_ZZZ_S - 0U, // ADDlowTLS - 33095U, // ADDv16i8 - 261U, // ADDv1i64 - 41287U, // ADDv2i32 - 8517U, // ADDv2i64 - 49480U, // ADDv4i16 - 16710U, // ADDv4i32 - 24902U, // ADDv8i16 - 57672U, // ADDv8i8 - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 1U, // ADR - 0U, // ADRP - 1093U, // ADR_LSL_ZZZ_D_0 - 1157U, // ADR_LSL_ZZZ_D_1 - 1221U, // ADR_LSL_ZZZ_D_2 - 1285U, // ADR_LSL_ZZZ_D_3 - 1349U, // ADR_LSL_ZZZ_S_0 - 1413U, // ADR_LSL_ZZZ_S_1 - 1477U, // ADR_LSL_ZZZ_S_2 - 1541U, // ADR_LSL_ZZZ_S_3 - 1605U, // ADR_SXTW_ZZZ_D_0 - 1669U, // ADR_SXTW_ZZZ_D_1 - 1733U, // ADR_SXTW_ZZZ_D_2 - 1797U, // ADR_SXTW_ZZZ_D_3 - 1861U, // ADR_UXTW_ZZZ_D_0 - 1925U, // ADR_UXTW_ZZZ_D_1 - 1989U, // ADR_UXTW_ZZZ_D_2 - 2053U, // ADR_UXTW_ZZZ_D_3 - 1U, // AESDrr - 1U, // AESErr - 1U, // AESIMCrr - 0U, // AESIMCrrTied - 1U, // AESMCrr - 0U, // AESMCrrTied - 2117U, // ANDSWri - 0U, // ANDSWrr - 517U, // ANDSWrs - 2181U, // ANDSXri - 0U, // ANDSXrr - 517U, // ANDSXrs - 74570U, // ANDS_PPzPP - 837U, // ANDV_VPZ_B - 901U, // ANDV_VPZ_D - 2245U, // ANDV_VPZ_H - 1029U, // ANDV_VPZ_S - 2117U, // ANDWri - 0U, // ANDWrr - 517U, // ANDWrs - 2181U, // ANDXri - 0U, // ANDXrr - 517U, // ANDXrs - 74570U, // AND_PPzPP - 2181U, // AND_ZI - 74560U, // AND_ZPmZ_B - 598912U, // AND_ZPmZ_D - 1131465U, // AND_ZPmZ_H - 1647616U, // AND_ZPmZ_S - 901U, // AND_ZZZ - 33095U, // ANDv16i8 - 57672U, // ANDv8i8 - 2171712U, // ASRD_ZPmI_B - 2171776U, // ASRD_ZPmI_D - 91081U, // ASRD_ZPmI_H - 2171904U, // ASRD_ZPmI_S - 74560U, // ASRR_ZPmZ_B - 598912U, // ASRR_ZPmZ_D - 1131465U, // ASRR_ZPmZ_H - 1647616U, // ASRR_ZPmZ_S - 261U, // ASRVWr - 261U, // ASRVXr - 598848U, // ASR_WIDE_ZPmZ_B - 99273U, // ASR_WIDE_ZPmZ_H - 599040U, // ASR_WIDE_ZPmZ_S - 901U, // ASR_WIDE_ZZZ_B - 10U, // ASR_WIDE_ZZZ_H - 901U, // ASR_WIDE_ZZZ_S - 2171712U, // ASR_ZPmI_B - 2171776U, // ASR_ZPmI_D - 91081U, // ASR_ZPmI_H - 2171904U, // ASR_ZPmI_S - 74560U, // ASR_ZPmZ_B - 598912U, // ASR_ZPmZ_D - 1131465U, // ASR_ZPmZ_H - 1647616U, // ASR_ZPmZ_S - 261U, // ASR_ZZI_B - 261U, // ASR_ZZI_D - 11U, // ASR_ZZI_H - 261U, // ASR_ZZI_S - 1U, // AUTDA - 1U, // AUTDB - 0U, // AUTDZA - 0U, // AUTDZB - 1U, // AUTIA - 0U, // AUTIA1716 - 0U, // AUTIASP - 0U, // AUTIAZ - 1U, // AUTIB - 0U, // AUTIB1716 - 0U, // AUTIBSP - 0U, // AUTIBZ - 0U, // AUTIZA - 0U, // AUTIZB - 0U, // B - 36282695U, // BCAX - 3221765U, // BFMWri - 3221765U, // BFMXri - 0U, // BICSWrr - 517U, // BICSWrs - 0U, // BICSXrr - 517U, // BICSXrs - 74570U, // BICS_PPzPP - 0U, // BICWrr - 517U, // BICWrs - 0U, // BICXrr - 517U, // BICXrs - 74570U, // BIC_PPzPP - 74560U, // BIC_ZPmZ_B - 598912U, // BIC_ZPmZ_D - 1131465U, // BIC_ZPmZ_H - 1647616U, // BIC_ZPmZ_S - 901U, // BIC_ZZZ - 33095U, // BICv16i8 - 0U, // BICv2i32 - 0U, // BICv4i16 - 0U, // BICv4i32 - 0U, // BICv8i16 - 57672U, // BICv8i8 - 33095U, // BIFv16i8 - 57672U, // BIFv8i8 - 33159U, // BITv16i8 - 57736U, // BITv8i8 - 0U, // BL - 0U, // BLR - 1U, // BLRAA - 0U, // BLRAAZ - 1U, // BLRAB - 0U, // BLRABZ - 0U, // BR - 1U, // BRAA - 0U, // BRAAZ - 1U, // BRAB - 0U, // BRABZ - 0U, // BRK - 842U, // BRKAS_PPzP - 0U, // BRKA_PPmP - 842U, // BRKA_PPzP - 842U, // BRKBS_PPzP - 0U, // BRKB_PPmP - 842U, // BRKB_PPzP - 74570U, // BRKNS_PPzP - 74570U, // BRKN_PPzP - 74570U, // BRKPAS_PPzPP - 74570U, // BRKPA_PPzPP - 74570U, // BRKPBS_PPzPP - 74570U, // BRKPB_PPzPP - 33159U, // BSLv16i8 - 57736U, // BSLv8i8 - 0U, // Bcc - 117003U, // CASAB - 117003U, // CASAH - 117003U, // CASALB - 117003U, // CASALH - 117003U, // CASALW - 117003U, // CASALX - 117003U, // CASAW - 117003U, // CASAX - 117003U, // CASB - 117003U, // CASH - 117003U, // CASLB - 117003U, // CASLH - 117003U, // CASLW - 117003U, // CASLX - 0U, // CASPALW - 0U, // CASPALX - 0U, // CASPAW - 0U, // CASPAX - 0U, // CASPLW - 0U, // CASPLX - 0U, // CASPW - 0U, // CASPX - 117003U, // CASW - 117003U, // CASX - 0U, // CBNZW - 0U, // CBNZX - 0U, // CBZW - 0U, // CBZX - 3744005U, // CCMNWi - 3744005U, // CCMNWr - 3744005U, // CCMNXi - 3744005U, // CCMNXr - 3744005U, // CCMPWi - 3744005U, // CCMPWr - 3744005U, // CCMPXi - 3744005U, // CCMPXr - 0U, // CFINV - 73989U, // CLASTA_RPZ_B - 598277U, // CLASTA_RPZ_D - 4268293U, // CLASTA_RPZ_H - 1646853U, // CLASTA_RPZ_S - 73989U, // CLASTA_VPZ_B - 598277U, // CLASTA_VPZ_D - 4268293U, // CLASTA_VPZ_H - 1646853U, // CLASTA_VPZ_S - 74565U, // CLASTA_ZPZ_B - 598917U, // CLASTA_ZPZ_D - 1131465U, // CLASTA_ZPZ_H - 1647621U, // CLASTA_ZPZ_S - 73989U, // CLASTB_RPZ_B - 598277U, // CLASTB_RPZ_D - 4268293U, // CLASTB_RPZ_H - 1646853U, // CLASTB_RPZ_S - 73989U, // CLASTB_VPZ_B - 598277U, // CLASTB_VPZ_D - 4268293U, // CLASTB_VPZ_H - 1646853U, // CLASTB_VPZ_S - 74565U, // CLASTB_ZPZ_B - 598917U, // CLASTB_ZPZ_D - 1131465U, // CLASTB_ZPZ_H - 1647621U, // CLASTB_ZPZ_S - 0U, // CLREX - 1U, // CLSWr - 1U, // CLSXr - 0U, // CLS_ZPmZ_B - 64U, // CLS_ZPmZ_D - 128U, // CLS_ZPmZ_H - 192U, // CLS_ZPmZ_S - 1U, // CLSv16i8 - 2U, // CLSv2i32 - 3U, // CLSv4i16 - 3U, // CLSv4i32 - 4U, // CLSv8i16 - 4U, // CLSv8i8 - 1U, // CLZWr - 1U, // CLZXr - 0U, // CLZ_ZPmZ_B - 64U, // CLZ_ZPmZ_D - 128U, // CLZ_ZPmZ_H - 192U, // CLZ_ZPmZ_S - 1U, // CLZv16i8 - 2U, // CLZv2i32 - 3U, // CLZv4i16 - 3U, // CLZv4i32 - 4U, // CLZv8i16 - 4U, // CLZv8i8 - 33095U, // CMEQv16i8 - 12U, // CMEQv16i8rz - 261U, // CMEQv1i64 - 12U, // CMEQv1i64rz - 41287U, // CMEQv2i32 - 13U, // CMEQv2i32rz - 8517U, // CMEQv2i64 - 13U, // CMEQv2i64rz - 49480U, // CMEQv4i16 - 14U, // CMEQv4i16rz - 16710U, // CMEQv4i32 - 14U, // CMEQv4i32rz - 24902U, // CMEQv8i16 - 15U, // CMEQv8i16rz - 57672U, // CMEQv8i8 - 15U, // CMEQv8i8rz - 33095U, // CMGEv16i8 - 12U, // CMGEv16i8rz - 261U, // CMGEv1i64 - 12U, // CMGEv1i64rz - 41287U, // CMGEv2i32 - 13U, // CMGEv2i32rz - 8517U, // CMGEv2i64 - 13U, // CMGEv2i64rz - 49480U, // CMGEv4i16 - 14U, // CMGEv4i16rz - 16710U, // CMGEv4i32 - 14U, // CMGEv4i32rz - 24902U, // CMGEv8i16 - 15U, // CMGEv8i16rz - 57672U, // CMGEv8i8 - 15U, // CMGEv8i8rz - 33095U, // CMGTv16i8 - 12U, // CMGTv16i8rz - 261U, // CMGTv1i64 - 12U, // CMGTv1i64rz - 41287U, // CMGTv2i32 - 13U, // CMGTv2i32rz - 8517U, // CMGTv2i64 - 13U, // CMGTv2i64rz - 49480U, // CMGTv4i16 - 14U, // CMGTv4i16rz - 16710U, // CMGTv4i32 - 14U, // CMGTv4i32rz - 24902U, // CMGTv8i16 - 15U, // CMGTv8i16rz - 57672U, // CMGTv8i8 - 15U, // CMGTv8i8rz - 33095U, // CMHIv16i8 - 261U, // CMHIv1i64 - 41287U, // CMHIv2i32 - 8517U, // CMHIv2i64 - 49480U, // CMHIv4i16 - 16710U, // CMHIv4i32 - 24902U, // CMHIv8i16 - 57672U, // CMHIv8i8 - 33095U, // CMHSv16i8 - 261U, // CMHSv1i64 - 41287U, // CMHSv2i32 - 8517U, // CMHSv2i64 - 49480U, // CMHSv4i16 - 16710U, // CMHSv4i32 - 24902U, // CMHSv8i16 - 57672U, // CMHSv8i8 - 12U, // CMLEv16i8rz - 12U, // CMLEv1i64rz - 13U, // CMLEv2i32rz - 13U, // CMLEv2i64rz - 14U, // CMLEv4i16rz - 14U, // CMLEv4i32rz - 15U, // CMLEv8i16rz - 15U, // CMLEv8i8rz - 12U, // CMLTv16i8rz - 12U, // CMLTv1i64rz - 13U, // CMLTv2i32rz - 13U, // CMLTv2i64rz - 14U, // CMLTv4i16rz - 14U, // CMLTv4i32rz - 15U, // CMLTv8i16rz - 15U, // CMLTv8i8rz - 2171722U, // CMPEQ_PPzZI_B - 2171786U, // CMPEQ_PPzZI_D - 91081U, // CMPEQ_PPzZI_H - 2171914U, // CMPEQ_PPzZI_S - 74570U, // CMPEQ_PPzZZ_B - 598922U, // CMPEQ_PPzZZ_D - 1131465U, // CMPEQ_PPzZZ_H - 1647626U, // CMPEQ_PPzZZ_S - 598858U, // CMPEQ_WIDE_PPzZZ_B - 99273U, // CMPEQ_WIDE_PPzZZ_H - 599050U, // CMPEQ_WIDE_PPzZZ_S - 2171722U, // CMPGE_PPzZI_B - 2171786U, // CMPGE_PPzZI_D - 91081U, // CMPGE_PPzZI_H - 2171914U, // CMPGE_PPzZI_S - 74570U, // CMPGE_PPzZZ_B - 598922U, // CMPGE_PPzZZ_D - 1131465U, // CMPGE_PPzZZ_H - 1647626U, // CMPGE_PPzZZ_S - 598858U, // CMPGE_WIDE_PPzZZ_B - 99273U, // CMPGE_WIDE_PPzZZ_H - 599050U, // CMPGE_WIDE_PPzZZ_S - 2171722U, // CMPGT_PPzZI_B - 2171786U, // CMPGT_PPzZI_D - 91081U, // CMPGT_PPzZI_H - 2171914U, // CMPGT_PPzZI_S - 74570U, // CMPGT_PPzZZ_B - 598922U, // CMPGT_PPzZZ_D - 1131465U, // CMPGT_PPzZZ_H - 1647626U, // CMPGT_PPzZZ_S - 598858U, // CMPGT_WIDE_PPzZZ_B - 99273U, // CMPGT_WIDE_PPzZZ_H - 599050U, // CMPGT_WIDE_PPzZZ_S - 4793162U, // CMPHI_PPzZI_B - 4793226U, // CMPHI_PPzZI_D - 123849U, // CMPHI_PPzZI_H - 4793354U, // CMPHI_PPzZI_S - 74570U, // CMPHI_PPzZZ_B - 598922U, // CMPHI_PPzZZ_D - 1131465U, // CMPHI_PPzZZ_H - 1647626U, // CMPHI_PPzZZ_S - 598858U, // CMPHI_WIDE_PPzZZ_B - 99273U, // CMPHI_WIDE_PPzZZ_H - 599050U, // CMPHI_WIDE_PPzZZ_S - 4793162U, // CMPHS_PPzZI_B - 4793226U, // CMPHS_PPzZI_D - 123849U, // CMPHS_PPzZI_H - 4793354U, // CMPHS_PPzZI_S - 74570U, // CMPHS_PPzZZ_B - 598922U, // CMPHS_PPzZZ_D - 1131465U, // CMPHS_PPzZZ_H - 1647626U, // CMPHS_PPzZZ_S - 598858U, // CMPHS_WIDE_PPzZZ_B - 99273U, // CMPHS_WIDE_PPzZZ_H - 599050U, // CMPHS_WIDE_PPzZZ_S - 2171722U, // CMPLE_PPzZI_B - 2171786U, // CMPLE_PPzZI_D - 91081U, // CMPLE_PPzZI_H - 2171914U, // CMPLE_PPzZI_S - 598858U, // CMPLE_WIDE_PPzZZ_B - 99273U, // CMPLE_WIDE_PPzZZ_H - 599050U, // CMPLE_WIDE_PPzZZ_S - 4793162U, // CMPLO_PPzZI_B - 4793226U, // CMPLO_PPzZI_D - 123849U, // CMPLO_PPzZI_H - 4793354U, // CMPLO_PPzZI_S - 598858U, // CMPLO_WIDE_PPzZZ_B - 99273U, // CMPLO_WIDE_PPzZZ_H - 599050U, // CMPLO_WIDE_PPzZZ_S - 4793162U, // CMPLS_PPzZI_B - 4793226U, // CMPLS_PPzZI_D - 123849U, // CMPLS_PPzZI_H - 4793354U, // CMPLS_PPzZI_S - 598858U, // CMPLS_WIDE_PPzZZ_B - 99273U, // CMPLS_WIDE_PPzZZ_H - 599050U, // CMPLS_WIDE_PPzZZ_S - 2171722U, // CMPLT_PPzZI_B - 2171786U, // CMPLT_PPzZI_D - 91081U, // CMPLT_PPzZI_H - 2171914U, // CMPLT_PPzZI_S - 598858U, // CMPLT_WIDE_PPzZZ_B - 99273U, // CMPLT_WIDE_PPzZZ_H - 599050U, // CMPLT_WIDE_PPzZZ_S - 2171722U, // CMPNE_PPzZI_B - 2171786U, // CMPNE_PPzZI_D - 91081U, // CMPNE_PPzZI_H - 2171914U, // CMPNE_PPzZI_S - 74570U, // CMPNE_PPzZZ_B - 598922U, // CMPNE_PPzZZ_D - 1131465U, // CMPNE_PPzZZ_H - 1647626U, // CMPNE_PPzZZ_S - 598858U, // CMPNE_WIDE_PPzZZ_B - 99273U, // CMPNE_WIDE_PPzZZ_H - 599050U, // CMPNE_WIDE_PPzZZ_S - 0U, // CMP_SWAP_128 - 0U, // CMP_SWAP_16 - 0U, // CMP_SWAP_32 - 0U, // CMP_SWAP_64 - 0U, // CMP_SWAP_8 - 33095U, // CMTSTv16i8 - 261U, // CMTSTv1i64 - 41287U, // CMTSTv2i32 - 8517U, // CMTSTv2i64 - 49480U, // CMTSTv4i16 - 16710U, // CMTSTv4i32 - 24902U, // CMTSTv8i16 - 57672U, // CMTSTv8i8 - 0U, // CNOT_ZPmZ_B - 64U, // CNOT_ZPmZ_D - 128U, // CNOT_ZPmZ_H - 192U, // CNOT_ZPmZ_S - 16U, // CNTB_XPiI - 16U, // CNTD_XPiI - 16U, // CNTH_XPiI - 837U, // CNTP_XPP_B - 901U, // CNTP_XPP_D - 2245U, // CNTP_XPP_H - 1029U, // CNTP_XPP_S - 16U, // CNTW_XPiI - 0U, // CNT_ZPmZ_B - 64U, // CNT_ZPmZ_D - 128U, // CNT_ZPmZ_H - 192U, // CNT_ZPmZ_S - 1U, // CNTv16i8 - 4U, // CNTv8i8 - 901U, // COMPACT_ZPZ_D - 1029U, // COMPACT_ZPZ_S - 2368U, // CPY_ZPmI_B - 2432U, // CPY_ZPmI_D - 16U, // CPY_ZPmI_H - 2496U, // CPY_ZPmI_S - 2304U, // CPY_ZPmR_B - 2304U, // CPY_ZPmR_D - 145U, // CPY_ZPmR_H - 2304U, // CPY_ZPmR_S - 2304U, // CPY_ZPmV_B - 2304U, // CPY_ZPmV_D - 145U, // CPY_ZPmV_H - 2304U, // CPY_ZPmV_S - 2570U, // CPY_ZPzI_B - 2634U, // CPY_ZPzI_D - 17U, // CPY_ZPzI_H - 2698U, // CPY_ZPzI_S - 2770U, // CPYi16 - 2770U, // CPYi32 - 2771U, // CPYi64 - 2771U, // CPYi8 - 261U, // CRC32Brr - 261U, // CRC32CBrr - 261U, // CRC32CHrr - 261U, // CRC32CWrr - 261U, // CRC32CXrr - 261U, // CRC32Hrr - 261U, // CRC32Wrr - 261U, // CRC32Xrr - 3744005U, // CSELWr - 3744005U, // CSELXr - 3744005U, // CSINCWr - 3744005U, // CSINCXr - 3744005U, // CSINVWr - 3744005U, // CSINVXr - 3744005U, // CSNEGWr - 3744005U, // CSNEGXr - 1U, // CTERMEQ_WW - 1U, // CTERMEQ_XX - 1U, // CTERMNE_WW - 1U, // CTERMNE_XX - 0U, // CompilerBarrier - 0U, // DCPS1 - 0U, // DCPS2 - 0U, // DCPS3 - 0U, // DECB_XPiI - 0U, // DECD_XPiI - 0U, // DECD_ZPiI - 0U, // DECH_XPiI - 0U, // DECH_ZPiI - 1U, // DECP_XP_B - 1U, // DECP_XP_D - 1U, // DECP_XP_H - 1U, // DECP_XP_S - 1U, // DECP_ZP_D - 0U, // DECP_ZP_H - 1U, // DECP_ZP_S - 0U, // DECW_XPiI - 0U, // DECW_ZPiI - 0U, // DMB - 0U, // DRPS - 0U, // DSB - 0U, // DUPM_ZI - 0U, // DUP_ZI_B - 0U, // DUP_ZI_D - 0U, // DUP_ZI_H - 0U, // DUP_ZI_S - 1U, // DUP_ZR_B - 1U, // DUP_ZR_D - 0U, // DUP_ZR_H - 1U, // DUP_ZR_S - 20U, // DUP_ZZI_B - 20U, // DUP_ZZI_D - 0U, // DUP_ZZI_H - 0U, // DUP_ZZI_Q - 20U, // DUP_ZZI_S - 1U, // DUPv16i8gpr - 2771U, // DUPv16i8lane - 1U, // DUPv2i32gpr - 2770U, // DUPv2i32lane - 1U, // DUPv2i64gpr - 2771U, // DUPv2i64lane - 1U, // DUPv4i16gpr - 2770U, // DUPv4i16lane - 1U, // DUPv4i32gpr - 2770U, // DUPv4i32lane - 1U, // DUPv8i16gpr - 2770U, // DUPv8i16lane - 1U, // DUPv8i8gpr - 2771U, // DUPv8i8lane - 0U, // EONWrr - 517U, // EONWrs - 0U, // EONXrr - 517U, // EONXrs - 36282695U, // EOR3 - 74570U, // EORS_PPzPP - 837U, // EORV_VPZ_B - 901U, // EORV_VPZ_D - 2245U, // EORV_VPZ_H - 1029U, // EORV_VPZ_S - 2117U, // EORWri - 0U, // EORWrr - 517U, // EORWrs - 2181U, // EORXri - 0U, // EORXrr - 517U, // EORXrs - 74570U, // EOR_PPzPP - 2181U, // EOR_ZI - 74560U, // EOR_ZPmZ_B - 598912U, // EOR_ZPmZ_D - 1131465U, // EOR_ZPmZ_H - 1647616U, // EOR_ZPmZ_S - 901U, // EOR_ZZZ - 33095U, // EORv16i8 - 57672U, // EORv8i8 - 0U, // ERET - 0U, // ERETAA - 0U, // ERETAB - 2171141U, // EXTRWrri - 2171141U, // EXTRXrri - 4793157U, // EXT_ZZI - 2203975U, // EXTv16i8 - 131400U, // EXTv8i8 - 0U, // F128CSEL - 261U, // FABD16 - 261U, // FABD32 - 261U, // FABD64 - 598912U, // FABD_ZPmZ_D - 1131465U, // FABD_ZPmZ_H - 1647616U, // FABD_ZPmZ_S - 41287U, // FABDv2f32 - 8517U, // FABDv2f64 - 49480U, // FABDv4f16 - 16710U, // FABDv4f32 - 24902U, // FABDv8f16 - 1U, // FABSDr - 1U, // FABSHr - 1U, // FABSSr - 64U, // FABS_ZPmZ_D - 128U, // FABS_ZPmZ_H - 192U, // FABS_ZPmZ_S - 2U, // FABSv2f32 - 2U, // FABSv2f64 - 3U, // FABSv4f16 - 3U, // FABSv4f32 - 4U, // FABSv8f16 - 261U, // FACGE16 - 261U, // FACGE32 - 261U, // FACGE64 - 598922U, // FACGE_PPzZZ_D - 1131465U, // FACGE_PPzZZ_H - 1647626U, // FACGE_PPzZZ_S - 41287U, // FACGEv2f32 - 8517U, // FACGEv2f64 - 49480U, // FACGEv4f16 - 16710U, // FACGEv4f32 - 24902U, // FACGEv8f16 - 261U, // FACGT16 - 261U, // FACGT32 - 261U, // FACGT64 - 598922U, // FACGT_PPzZZ_D - 1131465U, // FACGT_PPzZZ_H - 1647626U, // FACGT_PPzZZ_S - 41287U, // FACGTv2f32 - 8517U, // FACGTv2f64 - 49480U, // FACGTv4f16 - 16710U, // FACGTv4f32 - 24902U, // FACGTv8f16 - 598277U, // FADDA_VPZ_D - 4268293U, // FADDA_VPZ_H - 1646853U, // FADDA_VPZ_S - 261U, // FADDDrr - 261U, // FADDHrr - 41287U, // FADDPv2f32 - 8517U, // FADDPv2f64 - 20U, // FADDPv2i16p - 2U, // FADDPv2i32p - 2U, // FADDPv2i64p - 49480U, // FADDPv4f16 - 16710U, // FADDPv4f32 - 24902U, // FADDPv8f16 - 261U, // FADDSrr - 901U, // FADDV_VPZ_D - 2245U, // FADDV_VPZ_H - 1029U, // FADDV_VPZ_S - 5317504U, // FADD_ZPmI_D - 140233U, // FADD_ZPmI_H - 5317632U, // FADD_ZPmI_S - 598912U, // FADD_ZPmZ_D - 1131465U, // FADD_ZPmZ_H - 1647616U, // FADD_ZPmZ_S - 901U, // FADD_ZZZ_D - 137U, // FADD_ZZZ_H - 1029U, // FADD_ZZZ_S - 41287U, // FADDv2f32 - 8517U, // FADDv2f64 - 49480U, // FADDv4f16 - 16710U, // FADDv4f32 - 24902U, // FADDv8f16 - 67707776U, // FCADD_ZPmZ_D - 106513353U, // FCADD_ZPmZ_H - 68756480U, // FCADD_ZPmZ_S - 6439239U, // FCADDv2f32 - 6447429U, // FCADDv2f64 - 6455624U, // FCADDv4f16 - 6463814U, // FCADDv4f32 - 6472006U, // FCADDv8f16 - 3744005U, // FCCMPDrr - 3744005U, // FCCMPEDrr - 3744005U, // FCCMPEHrr - 3744005U, // FCCMPESrr - 3744005U, // FCCMPHrr - 3744005U, // FCCMPSrr - 261U, // FCMEQ16 - 261U, // FCMEQ32 - 261U, // FCMEQ64 - 189322U, // FCMEQ_PPzZ0_D - 2825U, // FCMEQ_PPzZ0_H - 189450U, // FCMEQ_PPzZ0_S - 598922U, // FCMEQ_PPzZZ_D - 1131465U, // FCMEQ_PPzZZ_H - 1647626U, // FCMEQ_PPzZZ_S - 21U, // FCMEQv1i16rz - 21U, // FCMEQv1i32rz - 21U, // FCMEQv1i64rz - 41287U, // FCMEQv2f32 - 8517U, // FCMEQv2f64 - 21U, // FCMEQv2i32rz - 22U, // FCMEQv2i64rz - 49480U, // FCMEQv4f16 - 16710U, // FCMEQv4f32 - 22U, // FCMEQv4i16rz - 23U, // FCMEQv4i32rz - 24902U, // FCMEQv8f16 - 23U, // FCMEQv8i16rz - 261U, // FCMGE16 - 261U, // FCMGE32 - 261U, // FCMGE64 - 189322U, // FCMGE_PPzZ0_D - 2825U, // FCMGE_PPzZ0_H - 189450U, // FCMGE_PPzZ0_S - 598922U, // FCMGE_PPzZZ_D - 1131465U, // FCMGE_PPzZZ_H - 1647626U, // FCMGE_PPzZZ_S - 21U, // FCMGEv1i16rz - 21U, // FCMGEv1i32rz - 21U, // FCMGEv1i64rz - 41287U, // FCMGEv2f32 - 8517U, // FCMGEv2f64 - 21U, // FCMGEv2i32rz - 22U, // FCMGEv2i64rz - 49480U, // FCMGEv4f16 - 16710U, // FCMGEv4f32 - 22U, // FCMGEv4i16rz - 23U, // FCMGEv4i32rz - 24902U, // FCMGEv8f16 - 23U, // FCMGEv8i16rz - 261U, // FCMGT16 - 261U, // FCMGT32 - 261U, // FCMGT64 - 189322U, // FCMGT_PPzZ0_D - 2825U, // FCMGT_PPzZ0_H - 189450U, // FCMGT_PPzZ0_S - 598922U, // FCMGT_PPzZZ_D - 1131465U, // FCMGT_PPzZZ_H - 1647626U, // FCMGT_PPzZZ_S - 21U, // FCMGTv1i16rz - 21U, // FCMGTv1i32rz - 21U, // FCMGTv1i64rz - 41287U, // FCMGTv2f32 - 8517U, // FCMGTv2f64 - 21U, // FCMGTv2i32rz - 22U, // FCMGTv2i64rz - 49480U, // FCMGTv4f16 - 16710U, // FCMGTv4f32 - 22U, // FCMGTv4i16rz - 23U, // FCMGTv4i32rz - 24902U, // FCMGTv8f16 - 23U, // FCMGTv8i16rz - 342433856U, // FCMLA_ZPmZZ_D - 140182464U, // FCMLA_ZPmZZ_H - 342958272U, // FCMLA_ZPmZZ_S - 24U, // FCMLA_ZZZI_H - 7940952U, // FCMLA_ZZZI_S - 8536455U, // FCMLAv2f32 - 8544645U, // FCMLAv2f64 - 8552840U, // FCMLAv4f16 - 344662408U, // FCMLAv4f16_indexed - 8561030U, // FCMLAv4f32 - 344670598U, // FCMLAv4f32_indexed - 8569222U, // FCMLAv8f16 - 344662406U, // FCMLAv8f16_indexed - 189322U, // FCMLE_PPzZ0_D - 2825U, // FCMLE_PPzZ0_H - 189450U, // FCMLE_PPzZ0_S - 21U, // FCMLEv1i16rz - 21U, // FCMLEv1i32rz - 21U, // FCMLEv1i64rz - 21U, // FCMLEv2i32rz - 22U, // FCMLEv2i64rz - 22U, // FCMLEv4i16rz - 23U, // FCMLEv4i32rz - 23U, // FCMLEv8i16rz - 189322U, // FCMLT_PPzZ0_D - 2825U, // FCMLT_PPzZ0_H - 189450U, // FCMLT_PPzZ0_S - 21U, // FCMLTv1i16rz - 21U, // FCMLTv1i32rz - 21U, // FCMLTv1i64rz - 21U, // FCMLTv2i32rz - 22U, // FCMLTv2i64rz - 22U, // FCMLTv4i16rz - 23U, // FCMLTv4i32rz - 23U, // FCMLTv8i16rz - 189322U, // FCMNE_PPzZ0_D - 2825U, // FCMNE_PPzZ0_H - 189450U, // FCMNE_PPzZ0_S - 598922U, // FCMNE_PPzZZ_D - 1131465U, // FCMNE_PPzZZ_H - 1647626U, // FCMNE_PPzZZ_S - 0U, // FCMPDri - 1U, // FCMPDrr - 0U, // FCMPEDri - 1U, // FCMPEDrr - 0U, // FCMPEHri - 1U, // FCMPEHrr - 0U, // FCMPESri - 1U, // FCMPESrr - 0U, // FCMPHri - 1U, // FCMPHrr - 0U, // FCMPSri - 1U, // FCMPSrr - 598922U, // FCMUO_PPzZZ_D - 1131465U, // FCMUO_PPzZZ_H - 1647626U, // FCMUO_PPzZZ_S - 2944U, // FCPY_ZPmI_D - 25U, // FCPY_ZPmI_H - 2944U, // FCPY_ZPmI_S - 3744005U, // FCSELDrrr - 3744005U, // FCSELHrrr - 3744005U, // FCSELSrrr - 1U, // FCVTASUWDr - 1U, // FCVTASUWHr - 1U, // FCVTASUWSr - 1U, // FCVTASUXDr - 1U, // FCVTASUXHr - 1U, // FCVTASUXSr - 1U, // FCVTASv1f16 - 1U, // FCVTASv1i32 - 1U, // FCVTASv1i64 - 2U, // FCVTASv2f32 - 2U, // FCVTASv2f64 - 3U, // FCVTASv4f16 - 3U, // FCVTASv4f32 - 4U, // FCVTASv8f16 - 1U, // FCVTAUUWDr - 1U, // FCVTAUUWHr - 1U, // FCVTAUUWSr - 1U, // FCVTAUUXDr - 1U, // FCVTAUUXHr - 1U, // FCVTAUUXSr - 1U, // FCVTAUv1f16 - 1U, // FCVTAUv1i32 - 1U, // FCVTAUv1i64 - 2U, // FCVTAUv2f32 - 2U, // FCVTAUv2f64 - 3U, // FCVTAUv4f16 - 3U, // FCVTAUv4f32 - 4U, // FCVTAUv8f16 - 1U, // FCVTDHr - 1U, // FCVTDSr - 1U, // FCVTHDr - 1U, // FCVTHSr - 2U, // FCVTLv2i32 - 3U, // FCVTLv4i16 - 3U, // FCVTLv4i32 - 4U, // FCVTLv8i16 - 1U, // FCVTMSUWDr - 1U, // FCVTMSUWHr - 1U, // FCVTMSUWSr - 1U, // FCVTMSUXDr - 1U, // FCVTMSUXHr - 1U, // FCVTMSUXSr - 1U, // FCVTMSv1f16 - 1U, // FCVTMSv1i32 - 1U, // FCVTMSv1i64 - 2U, // FCVTMSv2f32 - 2U, // FCVTMSv2f64 - 3U, // FCVTMSv4f16 - 3U, // FCVTMSv4f32 - 4U, // FCVTMSv8f16 - 1U, // FCVTMUUWDr - 1U, // FCVTMUUWHr - 1U, // FCVTMUUWSr - 1U, // FCVTMUUXDr - 1U, // FCVTMUUXHr - 1U, // FCVTMUUXSr - 1U, // FCVTMUv1f16 - 1U, // FCVTMUv1i32 - 1U, // FCVTMUv1i64 - 2U, // FCVTMUv2f32 - 2U, // FCVTMUv2f64 - 3U, // FCVTMUv4f16 - 3U, // FCVTMUv4f32 - 4U, // FCVTMUv8f16 - 1U, // FCVTNSUWDr - 1U, // FCVTNSUWHr - 1U, // FCVTNSUWSr - 1U, // FCVTNSUXDr - 1U, // FCVTNSUXHr - 1U, // FCVTNSUXSr - 1U, // FCVTNSv1f16 - 1U, // FCVTNSv1i32 - 1U, // FCVTNSv1i64 - 2U, // FCVTNSv2f32 - 2U, // FCVTNSv2f64 - 3U, // FCVTNSv4f16 - 3U, // FCVTNSv4f32 - 4U, // FCVTNSv8f16 - 1U, // FCVTNUUWDr - 1U, // FCVTNUUWHr - 1U, // FCVTNUUWSr - 1U, // FCVTNUUXDr - 1U, // FCVTNUUXHr - 1U, // FCVTNUUXSr - 1U, // FCVTNUv1f16 - 1U, // FCVTNUv1i32 - 1U, // FCVTNUv1i64 - 2U, // FCVTNUv2f32 - 2U, // FCVTNUv2f64 - 3U, // FCVTNUv4f16 - 3U, // FCVTNUv4f32 - 4U, // FCVTNUv8f16 - 2U, // FCVTNv2i32 - 3U, // FCVTNv4i16 - 2U, // FCVTNv4i32 - 3U, // FCVTNv8i16 - 1U, // FCVTPSUWDr - 1U, // FCVTPSUWHr - 1U, // FCVTPSUWSr - 1U, // FCVTPSUXDr - 1U, // FCVTPSUXHr - 1U, // FCVTPSUXSr - 1U, // FCVTPSv1f16 - 1U, // FCVTPSv1i32 - 1U, // FCVTPSv1i64 - 2U, // FCVTPSv2f32 - 2U, // FCVTPSv2f64 - 3U, // FCVTPSv4f16 - 3U, // FCVTPSv4f32 - 4U, // FCVTPSv8f16 - 1U, // FCVTPUUWDr - 1U, // FCVTPUUWHr - 1U, // FCVTPUUWSr - 1U, // FCVTPUUXDr - 1U, // FCVTPUUXHr - 1U, // FCVTPUUXSr - 1U, // FCVTPUv1f16 - 1U, // FCVTPUv1i32 - 1U, // FCVTPUv1i64 - 2U, // FCVTPUv2f32 - 2U, // FCVTPUv2f64 - 3U, // FCVTPUv4f16 - 3U, // FCVTPUv4f32 - 4U, // FCVTPUv8f16 - 1U, // FCVTSDr - 1U, // FCVTSHr - 1U, // FCVTXNv1i64 - 2U, // FCVTXNv2f32 - 2U, // FCVTXNv4f32 - 261U, // FCVTZSSWDri - 261U, // FCVTZSSWHri - 261U, // FCVTZSSWSri - 261U, // FCVTZSSXDri - 261U, // FCVTZSSXHri - 261U, // FCVTZSSXSri - 1U, // FCVTZSUWDr - 1U, // FCVTZSUWHr - 1U, // FCVTZSUWSr - 1U, // FCVTZSUXDr - 1U, // FCVTZSUXHr - 1U, // FCVTZSUXSr - 64U, // FCVTZS_ZPmZ_DtoD - 64U, // FCVTZS_ZPmZ_DtoS - 3008U, // FCVTZS_ZPmZ_HtoD - 128U, // FCVTZS_ZPmZ_HtoH - 3008U, // FCVTZS_ZPmZ_HtoS - 192U, // FCVTZS_ZPmZ_StoD - 192U, // FCVTZS_ZPmZ_StoS - 261U, // FCVTZSd - 261U, // FCVTZSh - 261U, // FCVTZSs - 1U, // FCVTZSv1f16 - 1U, // FCVTZSv1i32 - 1U, // FCVTZSv1i64 - 2U, // FCVTZSv2f32 - 2U, // FCVTZSv2f64 - 263U, // FCVTZSv2i32_shift - 261U, // FCVTZSv2i64_shift - 3U, // FCVTZSv4f16 - 3U, // FCVTZSv4f32 - 264U, // FCVTZSv4i16_shift - 262U, // FCVTZSv4i32_shift - 4U, // FCVTZSv8f16 - 262U, // FCVTZSv8i16_shift - 261U, // FCVTZUSWDri - 261U, // FCVTZUSWHri - 261U, // FCVTZUSWSri - 261U, // FCVTZUSXDri - 261U, // FCVTZUSXHri - 261U, // FCVTZUSXSri - 1U, // FCVTZUUWDr - 1U, // FCVTZUUWHr - 1U, // FCVTZUUWSr - 1U, // FCVTZUUXDr - 1U, // FCVTZUUXHr - 1U, // FCVTZUUXSr - 64U, // FCVTZU_ZPmZ_DtoD - 64U, // FCVTZU_ZPmZ_DtoS - 3008U, // FCVTZU_ZPmZ_HtoD - 128U, // FCVTZU_ZPmZ_HtoH - 3008U, // FCVTZU_ZPmZ_HtoS - 192U, // FCVTZU_ZPmZ_StoD - 192U, // FCVTZU_ZPmZ_StoS - 261U, // FCVTZUd - 261U, // FCVTZUh - 261U, // FCVTZUs - 1U, // FCVTZUv1f16 - 1U, // FCVTZUv1i32 - 1U, // FCVTZUv1i64 - 2U, // FCVTZUv2f32 - 2U, // FCVTZUv2f64 - 263U, // FCVTZUv2i32_shift - 261U, // FCVTZUv2i64_shift - 3U, // FCVTZUv4f16 - 3U, // FCVTZUv4f32 - 264U, // FCVTZUv4i16_shift - 262U, // FCVTZUv4i32_shift - 4U, // FCVTZUv8f16 - 262U, // FCVTZUv8i16_shift - 153U, // FCVT_ZPmZ_DtoH - 64U, // FCVT_ZPmZ_DtoS - 3008U, // FCVT_ZPmZ_HtoD - 3008U, // FCVT_ZPmZ_HtoS - 192U, // FCVT_ZPmZ_StoD - 152U, // FCVT_ZPmZ_StoH - 261U, // FDIVDrr - 261U, // FDIVHrr - 598912U, // FDIVR_ZPmZ_D - 1131465U, // FDIVR_ZPmZ_H - 1647616U, // FDIVR_ZPmZ_S - 261U, // FDIVSrr - 598912U, // FDIV_ZPmZ_D - 1131465U, // FDIV_ZPmZ_H - 1647616U, // FDIV_ZPmZ_S - 41287U, // FDIVv2f32 - 8517U, // FDIVv2f64 - 49480U, // FDIVv4f16 - 16710U, // FDIVv4f32 - 24902U, // FDIVv8f16 - 0U, // FDUP_ZI_D - 0U, // FDUP_ZI_H - 0U, // FDUP_ZI_S - 1U, // FEXPA_ZZ_D - 0U, // FEXPA_ZZ_H - 1U, // FEXPA_ZZ_S - 1U, // FJCVTZS - 2171141U, // FMADDDrrr - 2171141U, // FMADDHrrr - 2171141U, // FMADDSrrr - 6889536U, // FMAD_ZPmZZ_D - 1246144U, // FMAD_ZPmZZ_H - 7413952U, // FMAD_ZPmZZ_S - 261U, // FMAXDrr - 261U, // FMAXHrr - 261U, // FMAXNMDrr - 261U, // FMAXNMHrr - 41287U, // FMAXNMPv2f32 - 8517U, // FMAXNMPv2f64 - 20U, // FMAXNMPv2i16p - 2U, // FMAXNMPv2i32p - 2U, // FMAXNMPv2i64p - 49480U, // FMAXNMPv4f16 - 16710U, // FMAXNMPv4f32 - 24902U, // FMAXNMPv8f16 - 261U, // FMAXNMSrr - 901U, // FMAXNMV_VPZ_D - 2245U, // FMAXNMV_VPZ_H - 1029U, // FMAXNMV_VPZ_S - 3U, // FMAXNMVv4i16v - 3U, // FMAXNMVv4i32v - 4U, // FMAXNMVv8i16v - 9511808U, // FMAXNM_ZPmI_D - 222153U, // FMAXNM_ZPmI_H - 9511936U, // FMAXNM_ZPmI_S - 598912U, // FMAXNM_ZPmZ_D - 1131465U, // FMAXNM_ZPmZ_H - 1647616U, // FMAXNM_ZPmZ_S - 41287U, // FMAXNMv2f32 - 8517U, // FMAXNMv2f64 - 49480U, // FMAXNMv4f16 - 16710U, // FMAXNMv4f32 - 24902U, // FMAXNMv8f16 - 41287U, // FMAXPv2f32 - 8517U, // FMAXPv2f64 - 20U, // FMAXPv2i16p - 2U, // FMAXPv2i32p - 2U, // FMAXPv2i64p - 49480U, // FMAXPv4f16 - 16710U, // FMAXPv4f32 - 24902U, // FMAXPv8f16 - 261U, // FMAXSrr - 901U, // FMAXV_VPZ_D - 2245U, // FMAXV_VPZ_H - 1029U, // FMAXV_VPZ_S - 3U, // FMAXVv4i16v - 3U, // FMAXVv4i32v - 4U, // FMAXVv8i16v - 9511808U, // FMAX_ZPmI_D - 222153U, // FMAX_ZPmI_H - 9511936U, // FMAX_ZPmI_S - 598912U, // FMAX_ZPmZ_D - 1131465U, // FMAX_ZPmZ_H - 1647616U, // FMAX_ZPmZ_S - 41287U, // FMAXv2f32 - 8517U, // FMAXv2f64 - 49480U, // FMAXv4f16 - 16710U, // FMAXv4f32 - 24902U, // FMAXv8f16 - 261U, // FMINDrr - 261U, // FMINHrr - 261U, // FMINNMDrr - 261U, // FMINNMHrr - 41287U, // FMINNMPv2f32 - 8517U, // FMINNMPv2f64 - 20U, // FMINNMPv2i16p - 2U, // FMINNMPv2i32p - 2U, // FMINNMPv2i64p - 49480U, // FMINNMPv4f16 - 16710U, // FMINNMPv4f32 - 24902U, // FMINNMPv8f16 - 261U, // FMINNMSrr - 901U, // FMINNMV_VPZ_D - 2245U, // FMINNMV_VPZ_H - 1029U, // FMINNMV_VPZ_S - 3U, // FMINNMVv4i16v - 3U, // FMINNMVv4i32v - 4U, // FMINNMVv8i16v - 9511808U, // FMINNM_ZPmI_D - 222153U, // FMINNM_ZPmI_H - 9511936U, // FMINNM_ZPmI_S - 598912U, // FMINNM_ZPmZ_D - 1131465U, // FMINNM_ZPmZ_H - 1647616U, // FMINNM_ZPmZ_S - 41287U, // FMINNMv2f32 - 8517U, // FMINNMv2f64 - 49480U, // FMINNMv4f16 - 16710U, // FMINNMv4f32 - 24902U, // FMINNMv8f16 - 41287U, // FMINPv2f32 - 8517U, // FMINPv2f64 - 20U, // FMINPv2i16p - 2U, // FMINPv2i32p - 2U, // FMINPv2i64p - 49480U, // FMINPv4f16 - 16710U, // FMINPv4f32 - 24902U, // FMINPv8f16 - 261U, // FMINSrr - 901U, // FMINV_VPZ_D - 2245U, // FMINV_VPZ_H - 1029U, // FMINV_VPZ_S - 3U, // FMINVv4i16v - 3U, // FMINVv4i32v - 4U, // FMINVv8i16v - 9511808U, // FMIN_ZPmI_D - 222153U, // FMIN_ZPmI_H - 9511936U, // FMIN_ZPmI_S - 598912U, // FMIN_ZPmZ_D - 1131465U, // FMIN_ZPmZ_H - 1647616U, // FMIN_ZPmZ_S - 41287U, // FMINv2f32 - 8517U, // FMINv2f64 - 49480U, // FMINv4f16 - 16710U, // FMINv4f32 - 24902U, // FMINv8f16 - 6889536U, // FMLA_ZPmZZ_D - 1246144U, // FMLA_ZPmZZ_H - 7413952U, // FMLA_ZPmZZ_S - 2905U, // FMLA_ZZZI_D - 0U, // FMLA_ZZZI_H - 2904U, // FMLA_ZZZI_S - 9118085U, // FMLAv1i16_indexed - 9126277U, // FMLAv1i32_indexed - 9142661U, // FMLAv1i64_indexed - 41351U, // FMLAv2f32 - 8581U, // FMLAv2f64 - 9126279U, // FMLAv2i32_indexed - 9142661U, // FMLAv2i64_indexed - 49544U, // FMLAv4f16 - 16774U, // FMLAv4f32 - 9118088U, // FMLAv4i16_indexed - 9126278U, // FMLAv4i32_indexed - 24966U, // FMLAv8f16 - 9118086U, // FMLAv8i16_indexed - 6889536U, // FMLS_ZPmZZ_D - 1246144U, // FMLS_ZPmZZ_H - 7413952U, // FMLS_ZPmZZ_S - 2905U, // FMLS_ZZZI_D - 0U, // FMLS_ZZZI_H - 2904U, // FMLS_ZZZI_S - 9118085U, // FMLSv1i16_indexed - 9126277U, // FMLSv1i32_indexed - 9142661U, // FMLSv1i64_indexed - 41351U, // FMLSv2f32 - 8581U, // FMLSv2f64 - 9126279U, // FMLSv2i32_indexed - 9142661U, // FMLSv2i64_indexed - 49544U, // FMLSv4f16 - 16774U, // FMLSv4f32 - 9118088U, // FMLSv4i16_indexed - 9126278U, // FMLSv4i32_indexed - 24966U, // FMLSv8f16 - 9118086U, // FMLSv8i16_indexed - 0U, // FMOVD0 - 2771U, // FMOVDXHighr - 1U, // FMOVDXr - 0U, // FMOVDi - 1U, // FMOVDr - 0U, // FMOVH0 - 1U, // FMOVHWr - 1U, // FMOVHXr - 0U, // FMOVHi - 1U, // FMOVHr - 0U, // FMOVS0 - 1U, // FMOVSWr - 0U, // FMOVSi - 1U, // FMOVSr - 1U, // FMOVWHr - 1U, // FMOVWSr - 1U, // FMOVXDHighr - 1U, // FMOVXDr - 1U, // FMOVXHr - 0U, // FMOVv2f32_ns - 0U, // FMOVv2f64_ns - 0U, // FMOVv4f16_ns - 0U, // FMOVv4f32_ns - 0U, // FMOVv8f16_ns - 6889536U, // FMSB_ZPmZZ_D - 1246144U, // FMSB_ZPmZZ_H - 7413952U, // FMSB_ZPmZZ_S - 2171141U, // FMSUBDrrr - 2171141U, // FMSUBHrrr - 2171141U, // FMSUBSrrr - 261U, // FMULDrr - 261U, // FMULHrr - 261U, // FMULSrr - 261U, // FMULX16 - 261U, // FMULX32 - 261U, // FMULX64 - 598912U, // FMULX_ZPmZ_D - 1131465U, // FMULX_ZPmZ_H - 1647616U, // FMULX_ZPmZ_S - 10166597U, // FMULXv1i16_indexed - 10174789U, // FMULXv1i32_indexed - 10191173U, // FMULXv1i64_indexed - 41287U, // FMULXv2f32 - 8517U, // FMULXv2f64 - 10174791U, // FMULXv2i32_indexed - 10191173U, // FMULXv2i64_indexed - 49480U, // FMULXv4f16 - 16710U, // FMULXv4f32 - 10166600U, // FMULXv4i16_indexed - 10174790U, // FMULXv4i32_indexed - 24902U, // FMULXv8f16 - 10166598U, // FMULXv8i16_indexed - 10560384U, // FMUL_ZPmI_D - 238537U, // FMUL_ZPmI_H - 10560512U, // FMUL_ZPmI_S - 598912U, // FMUL_ZPmZ_D - 1131465U, // FMUL_ZPmZ_H - 1647616U, // FMUL_ZPmZ_S - 246661U, // FMUL_ZZZI_D - 3081U, // FMUL_ZZZI_H - 246789U, // FMUL_ZZZI_S - 901U, // FMUL_ZZZ_D - 137U, // FMUL_ZZZ_H - 1029U, // FMUL_ZZZ_S - 10166597U, // FMULv1i16_indexed - 10174789U, // FMULv1i32_indexed - 10191173U, // FMULv1i64_indexed - 41287U, // FMULv2f32 - 8517U, // FMULv2f64 - 10174791U, // FMULv2i32_indexed - 10191173U, // FMULv2i64_indexed - 49480U, // FMULv4f16 - 16710U, // FMULv4f32 - 10166600U, // FMULv4i16_indexed - 10174790U, // FMULv4i32_indexed - 24902U, // FMULv8f16 - 10166598U, // FMULv8i16_indexed - 1U, // FNEGDr - 1U, // FNEGHr - 1U, // FNEGSr - 64U, // FNEG_ZPmZ_D - 128U, // FNEG_ZPmZ_H - 192U, // FNEG_ZPmZ_S - 2U, // FNEGv2f32 - 2U, // FNEGv2f64 - 3U, // FNEGv4f16 - 3U, // FNEGv4f32 - 4U, // FNEGv8f16 - 2171141U, // FNMADDDrrr - 2171141U, // FNMADDHrrr - 2171141U, // FNMADDSrrr - 6889536U, // FNMAD_ZPmZZ_D - 1246144U, // FNMAD_ZPmZZ_H - 7413952U, // FNMAD_ZPmZZ_S - 6889536U, // FNMLA_ZPmZZ_D - 1246144U, // FNMLA_ZPmZZ_H - 7413952U, // FNMLA_ZPmZZ_S - 6889536U, // FNMLS_ZPmZZ_D - 1246144U, // FNMLS_ZPmZZ_H - 7413952U, // FNMLS_ZPmZZ_S - 6889536U, // FNMSB_ZPmZZ_D - 1246144U, // FNMSB_ZPmZZ_H - 7413952U, // FNMSB_ZPmZZ_S - 2171141U, // FNMSUBDrrr - 2171141U, // FNMSUBHrrr - 2171141U, // FNMSUBSrrr - 261U, // FNMULDrr - 261U, // FNMULHrr - 261U, // FNMULSrr - 1U, // FRECPE_ZZ_D - 0U, // FRECPE_ZZ_H - 1U, // FRECPE_ZZ_S - 1U, // FRECPEv1f16 - 1U, // FRECPEv1i32 - 1U, // FRECPEv1i64 - 2U, // FRECPEv2f32 - 2U, // FRECPEv2f64 - 3U, // FRECPEv4f16 - 3U, // FRECPEv4f32 - 4U, // FRECPEv8f16 - 261U, // FRECPS16 - 261U, // FRECPS32 - 261U, // FRECPS64 - 901U, // FRECPS_ZZZ_D - 137U, // FRECPS_ZZZ_H - 1029U, // FRECPS_ZZZ_S - 41287U, // FRECPSv2f32 - 8517U, // FRECPSv2f64 - 49480U, // FRECPSv4f16 - 16710U, // FRECPSv4f32 - 24902U, // FRECPSv8f16 - 64U, // FRECPX_ZPmZ_D - 128U, // FRECPX_ZPmZ_H - 192U, // FRECPX_ZPmZ_S - 1U, // FRECPXv1f16 - 1U, // FRECPXv1i32 - 1U, // FRECPXv1i64 - 1U, // FRINTADr - 1U, // FRINTAHr - 1U, // FRINTASr - 64U, // FRINTA_ZPmZ_D - 128U, // FRINTA_ZPmZ_H - 192U, // FRINTA_ZPmZ_S - 2U, // FRINTAv2f32 - 2U, // FRINTAv2f64 - 3U, // FRINTAv4f16 - 3U, // FRINTAv4f32 - 4U, // FRINTAv8f16 - 1U, // FRINTIDr - 1U, // FRINTIHr - 1U, // FRINTISr - 64U, // FRINTI_ZPmZ_D - 128U, // FRINTI_ZPmZ_H - 192U, // FRINTI_ZPmZ_S - 2U, // FRINTIv2f32 - 2U, // FRINTIv2f64 - 3U, // FRINTIv4f16 - 3U, // FRINTIv4f32 - 4U, // FRINTIv8f16 - 1U, // FRINTMDr - 1U, // FRINTMHr - 1U, // FRINTMSr - 64U, // FRINTM_ZPmZ_D - 128U, // FRINTM_ZPmZ_H - 192U, // FRINTM_ZPmZ_S - 2U, // FRINTMv2f32 - 2U, // FRINTMv2f64 - 3U, // FRINTMv4f16 - 3U, // FRINTMv4f32 - 4U, // FRINTMv8f16 - 1U, // FRINTNDr - 1U, // FRINTNHr - 1U, // FRINTNSr - 64U, // FRINTN_ZPmZ_D - 128U, // FRINTN_ZPmZ_H - 192U, // FRINTN_ZPmZ_S - 2U, // FRINTNv2f32 - 2U, // FRINTNv2f64 - 3U, // FRINTNv4f16 - 3U, // FRINTNv4f32 - 4U, // FRINTNv8f16 - 1U, // FRINTPDr - 1U, // FRINTPHr - 1U, // FRINTPSr - 64U, // FRINTP_ZPmZ_D - 128U, // FRINTP_ZPmZ_H - 192U, // FRINTP_ZPmZ_S - 2U, // FRINTPv2f32 - 2U, // FRINTPv2f64 - 3U, // FRINTPv4f16 - 3U, // FRINTPv4f32 - 4U, // FRINTPv8f16 - 1U, // FRINTXDr - 1U, // FRINTXHr - 1U, // FRINTXSr - 64U, // FRINTX_ZPmZ_D - 128U, // FRINTX_ZPmZ_H - 192U, // FRINTX_ZPmZ_S - 2U, // FRINTXv2f32 - 2U, // FRINTXv2f64 - 3U, // FRINTXv4f16 - 3U, // FRINTXv4f32 - 4U, // FRINTXv8f16 - 1U, // FRINTZDr - 1U, // FRINTZHr - 1U, // FRINTZSr - 64U, // FRINTZ_ZPmZ_D - 128U, // FRINTZ_ZPmZ_H - 192U, // FRINTZ_ZPmZ_S - 2U, // FRINTZv2f32 - 2U, // FRINTZv2f64 - 3U, // FRINTZv4f16 - 3U, // FRINTZv4f32 - 4U, // FRINTZv8f16 - 1U, // FRSQRTE_ZZ_D - 0U, // FRSQRTE_ZZ_H - 1U, // FRSQRTE_ZZ_S - 1U, // FRSQRTEv1f16 - 1U, // FRSQRTEv1i32 - 1U, // FRSQRTEv1i64 - 2U, // FRSQRTEv2f32 - 2U, // FRSQRTEv2f64 - 3U, // FRSQRTEv4f16 - 3U, // FRSQRTEv4f32 - 4U, // FRSQRTEv8f16 - 261U, // FRSQRTS16 - 261U, // FRSQRTS32 - 261U, // FRSQRTS64 - 901U, // FRSQRTS_ZZZ_D - 137U, // FRSQRTS_ZZZ_H - 1029U, // FRSQRTS_ZZZ_S - 41287U, // FRSQRTSv2f32 - 8517U, // FRSQRTSv2f64 - 49480U, // FRSQRTSv4f16 - 16710U, // FRSQRTSv4f32 - 24902U, // FRSQRTSv8f16 - 598912U, // FSCALE_ZPmZ_D - 1131465U, // FSCALE_ZPmZ_H - 1647616U, // FSCALE_ZPmZ_S - 1U, // FSQRTDr - 1U, // FSQRTHr - 1U, // FSQRTSr - 64U, // FSQRT_ZPmZ_D - 128U, // FSQRT_ZPmZ_H - 192U, // FSQRT_ZPmZ_S - 2U, // FSQRTv2f32 - 2U, // FSQRTv2f64 - 3U, // FSQRTv4f16 - 3U, // FSQRTv4f32 - 4U, // FSQRTv8f16 - 261U, // FSUBDrr - 261U, // FSUBHrr - 5317504U, // FSUBR_ZPmI_D - 140233U, // FSUBR_ZPmI_H - 5317632U, // FSUBR_ZPmI_S - 598912U, // FSUBR_ZPmZ_D - 1131465U, // FSUBR_ZPmZ_H - 1647616U, // FSUBR_ZPmZ_S - 261U, // FSUBSrr - 5317504U, // FSUB_ZPmI_D - 140233U, // FSUB_ZPmI_H - 5317632U, // FSUB_ZPmI_S - 598912U, // FSUB_ZPmZ_D - 1131465U, // FSUB_ZPmZ_H - 1647616U, // FSUB_ZPmZ_S - 901U, // FSUB_ZZZ_D - 137U, // FSUB_ZZZ_H - 1029U, // FSUB_ZZZ_S - 41287U, // FSUBv2f32 - 8517U, // FSUBv2f64 - 49480U, // FSUBv4f16 - 16710U, // FSUBv4f32 - 24902U, // FSUBv8f16 - 2171781U, // FTMAD_ZZI_D - 91081U, // FTMAD_ZZI_H - 2171909U, // FTMAD_ZZI_S - 901U, // FTSMUL_ZZZ_D - 137U, // FTSMUL_ZZZ_H - 1029U, // FTSMUL_ZZZ_S - 901U, // FTSSEL_ZZZ_D - 137U, // FTSSEL_ZZZ_H - 1029U, // FTSSEL_ZZZ_S - 3153U, // GLD1B_D_IMM_REAL - 3205U, // GLD1B_D_REAL - 3269U, // GLD1B_D_SXTW_REAL - 3333U, // GLD1B_D_UXTW_REAL - 3153U, // GLD1B_S_IMM_REAL - 3397U, // GLD1B_S_SXTW_REAL - 3461U, // GLD1B_S_UXTW_REAL - 26U, // GLD1D_IMM_REAL - 3205U, // GLD1D_REAL - 3525U, // GLD1D_SCALED_REAL - 3269U, // GLD1D_SXTW_REAL - 3589U, // GLD1D_SXTW_SCALED_REAL - 3333U, // GLD1D_UXTW_REAL - 3653U, // GLD1D_UXTW_SCALED_REAL - 26U, // GLD1H_D_IMM_REAL - 3205U, // GLD1H_D_REAL - 3717U, // GLD1H_D_SCALED_REAL - 3269U, // GLD1H_D_SXTW_REAL - 3781U, // GLD1H_D_SXTW_SCALED_REAL - 3333U, // GLD1H_D_UXTW_REAL - 3845U, // GLD1H_D_UXTW_SCALED_REAL - 26U, // GLD1H_S_IMM_REAL - 3397U, // GLD1H_S_SXTW_REAL - 3909U, // GLD1H_S_SXTW_SCALED_REAL - 3461U, // GLD1H_S_UXTW_REAL - 3973U, // GLD1H_S_UXTW_SCALED_REAL - 3153U, // GLD1SB_D_IMM_REAL - 3205U, // GLD1SB_D_REAL - 3269U, // GLD1SB_D_SXTW_REAL - 3333U, // GLD1SB_D_UXTW_REAL - 3153U, // GLD1SB_S_IMM_REAL - 3397U, // GLD1SB_S_SXTW_REAL - 3461U, // GLD1SB_S_UXTW_REAL - 26U, // GLD1SH_D_IMM_REAL - 3205U, // GLD1SH_D_REAL - 3717U, // GLD1SH_D_SCALED_REAL - 3269U, // GLD1SH_D_SXTW_REAL - 3781U, // GLD1SH_D_SXTW_SCALED_REAL - 3333U, // GLD1SH_D_UXTW_REAL - 3845U, // GLD1SH_D_UXTW_SCALED_REAL - 26U, // GLD1SH_S_IMM_REAL - 3397U, // GLD1SH_S_SXTW_REAL - 3909U, // GLD1SH_S_SXTW_SCALED_REAL - 3461U, // GLD1SH_S_UXTW_REAL - 3973U, // GLD1SH_S_UXTW_SCALED_REAL - 27U, // GLD1SW_D_IMM_REAL - 3205U, // GLD1SW_D_REAL - 4037U, // GLD1SW_D_SCALED_REAL - 3269U, // GLD1SW_D_SXTW_REAL - 4101U, // GLD1SW_D_SXTW_SCALED_REAL - 3333U, // GLD1SW_D_UXTW_REAL - 4165U, // GLD1SW_D_UXTW_SCALED_REAL - 27U, // GLD1W_D_IMM_REAL - 3205U, // GLD1W_D_REAL - 4037U, // GLD1W_D_SCALED_REAL - 3269U, // GLD1W_D_SXTW_REAL - 4101U, // GLD1W_D_SXTW_SCALED_REAL - 3333U, // GLD1W_D_UXTW_REAL - 4165U, // GLD1W_D_UXTW_SCALED_REAL - 27U, // GLD1W_IMM_REAL - 3397U, // GLD1W_SXTW_REAL - 4229U, // GLD1W_SXTW_SCALED_REAL - 3461U, // GLD1W_UXTW_REAL - 4293U, // GLD1W_UXTW_SCALED_REAL - 3153U, // GLDFF1B_D_IMM_REAL - 3205U, // GLDFF1B_D_REAL - 3269U, // GLDFF1B_D_SXTW_REAL - 3333U, // GLDFF1B_D_UXTW_REAL - 3153U, // GLDFF1B_S_IMM_REAL - 3397U, // GLDFF1B_S_SXTW_REAL - 3461U, // GLDFF1B_S_UXTW_REAL - 26U, // GLDFF1D_IMM_REAL - 3205U, // GLDFF1D_REAL - 3525U, // GLDFF1D_SCALED_REAL - 3269U, // GLDFF1D_SXTW_REAL - 3589U, // GLDFF1D_SXTW_SCALED_REAL - 3333U, // GLDFF1D_UXTW_REAL - 3653U, // GLDFF1D_UXTW_SCALED_REAL - 26U, // GLDFF1H_D_IMM_REAL - 3205U, // GLDFF1H_D_REAL - 3717U, // GLDFF1H_D_SCALED_REAL - 3269U, // GLDFF1H_D_SXTW_REAL - 3781U, // GLDFF1H_D_SXTW_SCALED_REAL - 3333U, // GLDFF1H_D_UXTW_REAL - 3845U, // GLDFF1H_D_UXTW_SCALED_REAL - 26U, // GLDFF1H_S_IMM_REAL - 3397U, // GLDFF1H_S_SXTW_REAL - 3909U, // GLDFF1H_S_SXTW_SCALED_REAL - 3461U, // GLDFF1H_S_UXTW_REAL - 3973U, // GLDFF1H_S_UXTW_SCALED_REAL - 3153U, // GLDFF1SB_D_IMM_REAL - 3205U, // GLDFF1SB_D_REAL - 3269U, // GLDFF1SB_D_SXTW_REAL - 3333U, // GLDFF1SB_D_UXTW_REAL - 3153U, // GLDFF1SB_S_IMM_REAL - 3397U, // GLDFF1SB_S_SXTW_REAL - 3461U, // GLDFF1SB_S_UXTW_REAL - 26U, // GLDFF1SH_D_IMM_REAL - 3205U, // GLDFF1SH_D_REAL - 3717U, // GLDFF1SH_D_SCALED_REAL - 3269U, // GLDFF1SH_D_SXTW_REAL - 3781U, // GLDFF1SH_D_SXTW_SCALED_REAL - 3333U, // GLDFF1SH_D_UXTW_REAL - 3845U, // GLDFF1SH_D_UXTW_SCALED_REAL - 26U, // GLDFF1SH_S_IMM_REAL - 3397U, // GLDFF1SH_S_SXTW_REAL - 3909U, // GLDFF1SH_S_SXTW_SCALED_REAL - 3461U, // GLDFF1SH_S_UXTW_REAL - 3973U, // GLDFF1SH_S_UXTW_SCALED_REAL - 27U, // GLDFF1SW_D_IMM_REAL - 3205U, // GLDFF1SW_D_REAL - 4037U, // GLDFF1SW_D_SCALED_REAL - 3269U, // GLDFF1SW_D_SXTW_REAL - 4101U, // GLDFF1SW_D_SXTW_SCALED_REAL - 3333U, // GLDFF1SW_D_UXTW_REAL - 4165U, // GLDFF1SW_D_UXTW_SCALED_REAL - 27U, // GLDFF1W_D_IMM_REAL - 3205U, // GLDFF1W_D_REAL - 4037U, // GLDFF1W_D_SCALED_REAL - 3269U, // GLDFF1W_D_SXTW_REAL - 4101U, // GLDFF1W_D_SXTW_SCALED_REAL - 3333U, // GLDFF1W_D_UXTW_REAL - 4165U, // GLDFF1W_D_UXTW_SCALED_REAL - 27U, // GLDFF1W_IMM_REAL - 3397U, // GLDFF1W_SXTW_REAL - 4229U, // GLDFF1W_SXTW_SCALED_REAL - 3461U, // GLDFF1W_UXTW_REAL - 4293U, // GLDFF1W_UXTW_SCALED_REAL - 0U, // HINT - 0U, // HLT - 0U, // HVC - 0U, // INCB_XPiI - 0U, // INCD_XPiI - 0U, // INCD_ZPiI - 0U, // INCH_XPiI - 0U, // INCH_ZPiI - 1U, // INCP_XP_B - 1U, // INCP_XP_D - 1U, // INCP_XP_H - 1U, // INCP_XP_S - 1U, // INCP_ZP_D - 0U, // INCP_ZP_H - 1U, // INCP_ZP_S - 0U, // INCW_XPiI - 0U, // INCW_ZPiI - 261U, // INDEX_II_B - 261U, // INDEX_II_D - 11U, // INDEX_II_H - 261U, // INDEX_II_S - 261U, // INDEX_IR_B - 261U, // INDEX_IR_D - 11U, // INDEX_IR_H - 261U, // INDEX_IR_S - 261U, // INDEX_RI_B - 261U, // INDEX_RI_D - 11U, // INDEX_RI_H - 261U, // INDEX_RI_S - 261U, // INDEX_RR_B - 261U, // INDEX_RR_D - 11U, // INDEX_RR_H - 261U, // INDEX_RR_S - 1U, // INSR_ZR_B - 1U, // INSR_ZR_D - 0U, // INSR_ZR_H - 1U, // INSR_ZR_S - 1U, // INSR_ZV_B - 1U, // INSR_ZV_D - 0U, // INSR_ZV_H - 1U, // INSR_ZV_S - 1U, // INSvi16gpr - 2898U, // INSvi16lane - 1U, // INSvi32gpr - 2898U, // INSvi32lane - 1U, // INSvi64gpr - 2899U, // INSvi64lane - 1U, // INSvi8gpr - 2899U, // INSvi8lane - 0U, // ISB - 837U, // LASTA_RPZ_B - 901U, // LASTA_RPZ_D - 2245U, // LASTA_RPZ_H - 1029U, // LASTA_RPZ_S - 837U, // LASTA_VPZ_B - 901U, // LASTA_VPZ_D - 2245U, // LASTA_VPZ_H - 1029U, // LASTA_VPZ_S - 837U, // LASTB_RPZ_B - 901U, // LASTB_RPZ_D - 2245U, // LASTB_RPZ_H - 1029U, // LASTB_RPZ_S - 837U, // LASTB_VPZ_B - 901U, // LASTB_VPZ_D - 2245U, // LASTB_VPZ_H - 1029U, // LASTB_VPZ_S - 4357U, // LD1B - 4357U, // LD1B_D - 256261U, // LD1B_D_IMM_REAL - 4357U, // LD1B_H - 256261U, // LD1B_H_IMM_REAL - 256261U, // LD1B_IMM_REAL - 4357U, // LD1B_S - 256261U, // LD1B_S_IMM_REAL - 4421U, // LD1D - 256261U, // LD1D_IMM_REAL - 0U, // LD1Fourv16b - 0U, // LD1Fourv16b_POST - 0U, // LD1Fourv1d - 0U, // LD1Fourv1d_POST - 0U, // LD1Fourv2d - 0U, // LD1Fourv2d_POST - 0U, // LD1Fourv2s - 0U, // LD1Fourv2s_POST - 0U, // LD1Fourv4h - 0U, // LD1Fourv4h_POST - 0U, // LD1Fourv4s - 0U, // LD1Fourv4s_POST - 0U, // LD1Fourv8b - 0U, // LD1Fourv8b_POST - 0U, // LD1Fourv8h - 0U, // LD1Fourv8h_POST - 4485U, // LD1H - 4485U, // LD1H_D - 256261U, // LD1H_D_IMM_REAL - 256261U, // LD1H_IMM_REAL - 4485U, // LD1H_S - 256261U, // LD1H_S_IMM_REAL - 0U, // LD1Onev16b - 0U, // LD1Onev16b_POST - 0U, // LD1Onev1d - 0U, // LD1Onev1d_POST - 0U, // LD1Onev2d - 0U, // LD1Onev2d_POST - 0U, // LD1Onev2s - 0U, // LD1Onev2s_POST - 0U, // LD1Onev4h - 0U, // LD1Onev4h_POST - 0U, // LD1Onev4s - 0U, // LD1Onev4s_POST - 0U, // LD1Onev8b - 0U, // LD1Onev8b_POST - 0U, // LD1Onev8h - 0U, // LD1Onev8h_POST - 116997U, // LD1RB_D_IMM - 116997U, // LD1RB_H_IMM - 116997U, // LD1RB_IMM - 116997U, // LD1RB_S_IMM - 119237U, // LD1RD_IMM - 119301U, // LD1RH_D_IMM - 119301U, // LD1RH_IMM - 119301U, // LD1RH_S_IMM - 4357U, // LD1RQ_B - 4677U, // LD1RQ_B_IMM - 4421U, // LD1RQ_D - 4677U, // LD1RQ_D_IMM - 4485U, // LD1RQ_H - 4677U, // LD1RQ_H_IMM - 4741U, // LD1RQ_W - 4677U, // LD1RQ_W_IMM - 116997U, // LD1RSB_D_IMM - 116997U, // LD1RSB_H_IMM - 116997U, // LD1RSB_S_IMM - 119301U, // LD1RSH_D_IMM - 119301U, // LD1RSH_S_IMM - 119493U, // LD1RSW_IMM - 119493U, // LD1RW_D_IMM - 119493U, // LD1RW_IMM - 0U, // LD1Rv16b - 0U, // LD1Rv16b_POST - 0U, // LD1Rv1d - 0U, // LD1Rv1d_POST - 0U, // LD1Rv2d - 0U, // LD1Rv2d_POST - 0U, // LD1Rv2s - 0U, // LD1Rv2s_POST - 0U, // LD1Rv4h - 0U, // LD1Rv4h_POST - 0U, // LD1Rv4s - 0U, // LD1Rv4s_POST - 0U, // LD1Rv8b - 0U, // LD1Rv8b_POST - 0U, // LD1Rv8h - 0U, // LD1Rv8h_POST - 4357U, // LD1SB_D - 256261U, // LD1SB_D_IMM_REAL - 4357U, // LD1SB_H - 256261U, // LD1SB_H_IMM_REAL - 4357U, // LD1SB_S - 256261U, // LD1SB_S_IMM_REAL - 4485U, // LD1SH_D - 256261U, // LD1SH_D_IMM_REAL - 4485U, // LD1SH_S - 256261U, // LD1SH_S_IMM_REAL - 4741U, // LD1SW_D - 256261U, // LD1SW_D_IMM_REAL - 0U, // LD1Threev16b - 0U, // LD1Threev16b_POST - 0U, // LD1Threev1d - 0U, // LD1Threev1d_POST - 0U, // LD1Threev2d - 0U, // LD1Threev2d_POST - 0U, // LD1Threev2s - 0U, // LD1Threev2s_POST - 0U, // LD1Threev4h - 0U, // LD1Threev4h_POST - 0U, // LD1Threev4s - 0U, // LD1Threev4s_POST - 0U, // LD1Threev8b - 0U, // LD1Threev8b_POST - 0U, // LD1Threev8h - 0U, // LD1Threev8h_POST - 0U, // LD1Twov16b - 0U, // LD1Twov16b_POST - 0U, // LD1Twov1d - 0U, // LD1Twov1d_POST - 0U, // LD1Twov2d - 0U, // LD1Twov2d_POST - 0U, // LD1Twov2s - 0U, // LD1Twov2s_POST - 0U, // LD1Twov4h - 0U, // LD1Twov4h_POST - 0U, // LD1Twov4s - 0U, // LD1Twov4s_POST - 0U, // LD1Twov8b - 0U, // LD1Twov8b_POST - 0U, // LD1Twov8h - 0U, // LD1Twov8h_POST - 4741U, // LD1W - 4741U, // LD1W_D - 256261U, // LD1W_D_IMM_REAL - 256261U, // LD1W_IMM_REAL - 0U, // LD1i16 - 0U, // LD1i16_POST - 0U, // LD1i32 - 0U, // LD1i32_POST - 0U, // LD1i64 - 0U, // LD1i64_POST - 0U, // LD1i8 - 0U, // LD1i8_POST - 4357U, // LD2B - 258565U, // LD2B_IMM - 4421U, // LD2D - 258565U, // LD2D_IMM - 4485U, // LD2H - 258565U, // LD2H_IMM - 0U, // LD2Rv16b - 0U, // LD2Rv16b_POST - 0U, // LD2Rv1d - 0U, // LD2Rv1d_POST - 0U, // LD2Rv2d - 0U, // LD2Rv2d_POST - 0U, // LD2Rv2s - 0U, // LD2Rv2s_POST - 0U, // LD2Rv4h - 0U, // LD2Rv4h_POST - 0U, // LD2Rv4s - 0U, // LD2Rv4s_POST - 0U, // LD2Rv8b - 0U, // LD2Rv8b_POST - 0U, // LD2Rv8h - 0U, // LD2Rv8h_POST - 0U, // LD2Twov16b - 0U, // LD2Twov16b_POST - 0U, // LD2Twov2d - 0U, // LD2Twov2d_POST - 0U, // LD2Twov2s - 0U, // LD2Twov2s_POST - 0U, // LD2Twov4h - 0U, // LD2Twov4h_POST - 0U, // LD2Twov4s - 0U, // LD2Twov4s_POST - 0U, // LD2Twov8b - 0U, // LD2Twov8b_POST - 0U, // LD2Twov8h - 0U, // LD2Twov8h_POST - 4741U, // LD2W - 258565U, // LD2W_IMM - 0U, // LD2i16 - 0U, // LD2i16_POST - 0U, // LD2i32 - 0U, // LD2i32_POST - 0U, // LD2i64 - 0U, // LD2i64_POST - 0U, // LD2i8 - 0U, // LD2i8_POST - 4357U, // LD3B - 4869U, // LD3B_IMM - 4421U, // LD3D - 4869U, // LD3D_IMM - 4485U, // LD3H - 4869U, // LD3H_IMM - 0U, // LD3Rv16b - 0U, // LD3Rv16b_POST - 0U, // LD3Rv1d - 0U, // LD3Rv1d_POST - 0U, // LD3Rv2d - 0U, // LD3Rv2d_POST - 0U, // LD3Rv2s - 0U, // LD3Rv2s_POST - 0U, // LD3Rv4h - 0U, // LD3Rv4h_POST - 0U, // LD3Rv4s - 0U, // LD3Rv4s_POST - 0U, // LD3Rv8b - 0U, // LD3Rv8b_POST - 0U, // LD3Rv8h - 0U, // LD3Rv8h_POST - 0U, // LD3Threev16b - 0U, // LD3Threev16b_POST - 0U, // LD3Threev2d - 0U, // LD3Threev2d_POST - 0U, // LD3Threev2s - 0U, // LD3Threev2s_POST - 0U, // LD3Threev4h - 0U, // LD3Threev4h_POST - 0U, // LD3Threev4s - 0U, // LD3Threev4s_POST - 0U, // LD3Threev8b - 0U, // LD3Threev8b_POST - 0U, // LD3Threev8h - 0U, // LD3Threev8h_POST - 4741U, // LD3W - 4869U, // LD3W_IMM - 0U, // LD3i16 - 0U, // LD3i16_POST - 0U, // LD3i32 - 0U, // LD3i32_POST - 0U, // LD3i64 - 0U, // LD3i64_POST - 0U, // LD3i8 - 0U, // LD3i8_POST - 4357U, // LD4B - 258757U, // LD4B_IMM - 4421U, // LD4D - 258757U, // LD4D_IMM - 0U, // LD4Fourv16b - 0U, // LD4Fourv16b_POST - 0U, // LD4Fourv2d - 0U, // LD4Fourv2d_POST - 0U, // LD4Fourv2s - 0U, // LD4Fourv2s_POST - 0U, // LD4Fourv4h - 0U, // LD4Fourv4h_POST - 0U, // LD4Fourv4s - 0U, // LD4Fourv4s_POST - 0U, // LD4Fourv8b - 0U, // LD4Fourv8b_POST - 0U, // LD4Fourv8h - 0U, // LD4Fourv8h_POST - 4485U, // LD4H - 258757U, // LD4H_IMM - 0U, // LD4Rv16b - 0U, // LD4Rv16b_POST - 0U, // LD4Rv1d - 0U, // LD4Rv1d_POST - 0U, // LD4Rv2d - 0U, // LD4Rv2d_POST - 0U, // LD4Rv2s - 0U, // LD4Rv2s_POST - 0U, // LD4Rv4h - 0U, // LD4Rv4h_POST - 0U, // LD4Rv4s - 0U, // LD4Rv4s_POST - 0U, // LD4Rv8b - 0U, // LD4Rv8b_POST - 0U, // LD4Rv8h - 0U, // LD4Rv8h_POST - 4741U, // LD4W - 258757U, // LD4W_IMM - 0U, // LD4i16 - 0U, // LD4i16_POST - 0U, // LD4i32 - 0U, // LD4i32_POST - 0U, // LD4i64 - 0U, // LD4i64_POST - 0U, // LD4i8 - 0U, // LD4i8_POST - 0U, // LDADDAB - 0U, // LDADDAH - 0U, // LDADDALB - 0U, // LDADDALH - 0U, // LDADDALW - 0U, // LDADDALX - 0U, // LDADDAW - 0U, // LDADDAX - 0U, // LDADDB - 0U, // LDADDH - 0U, // LDADDLB - 0U, // LDADDLH - 0U, // LDADDLW - 0U, // LDADDLX - 0U, // LDADDW - 0U, // LDADDX - 27U, // LDAPRB - 27U, // LDAPRH - 27U, // LDAPRW - 27U, // LDAPRX - 114949U, // LDAPURBi - 114949U, // LDAPURHi - 114949U, // LDAPURSBWi - 114949U, // LDAPURSBXi - 114949U, // LDAPURSHWi - 114949U, // LDAPURSHXi - 114949U, // LDAPURSWi - 114949U, // LDAPURXi - 114949U, // LDAPURi - 27U, // LDARB - 27U, // LDARH - 27U, // LDARW - 27U, // LDARX - 114955U, // LDAXPW - 114955U, // LDAXPX - 27U, // LDAXRB - 27U, // LDAXRH - 27U, // LDAXRW - 27U, // LDAXRX - 0U, // LDCLRAB - 0U, // LDCLRAH - 0U, // LDCLRALB - 0U, // LDCLRALH - 0U, // LDCLRALW - 0U, // LDCLRALX - 0U, // LDCLRAW - 0U, // LDCLRAX - 0U, // LDCLRB - 0U, // LDCLRH - 0U, // LDCLRLB - 0U, // LDCLRLH - 0U, // LDCLRLW - 0U, // LDCLRLX - 0U, // LDCLRW - 0U, // LDCLRX - 0U, // LDEORAB - 0U, // LDEORAH - 0U, // LDEORALB - 0U, // LDEORALH - 0U, // LDEORALW - 0U, // LDEORALX - 0U, // LDEORAW - 0U, // LDEORAX - 0U, // LDEORB - 0U, // LDEORH - 0U, // LDEORLB - 0U, // LDEORLH - 0U, // LDEORLW - 0U, // LDEORLX - 0U, // LDEORW - 0U, // LDEORX - 4357U, // LDFF1B_D_REAL - 4357U, // LDFF1B_H_REAL - 4357U, // LDFF1B_REAL - 4357U, // LDFF1B_S_REAL - 4421U, // LDFF1D_REAL - 4485U, // LDFF1H_D_REAL - 4485U, // LDFF1H_REAL - 4485U, // LDFF1H_S_REAL - 4357U, // LDFF1SB_D_REAL - 4357U, // LDFF1SB_H_REAL - 4357U, // LDFF1SB_S_REAL - 4485U, // LDFF1SH_D_REAL - 4485U, // LDFF1SH_S_REAL - 4741U, // LDFF1SW_D_REAL - 4741U, // LDFF1W_D_REAL - 4741U, // LDFF1W_REAL - 27U, // LDLARB - 27U, // LDLARH - 27U, // LDLARW - 27U, // LDLARX - 256261U, // LDNF1B_D_IMM_REAL - 256261U, // LDNF1B_H_IMM_REAL - 256261U, // LDNF1B_IMM_REAL - 256261U, // LDNF1B_S_IMM_REAL - 256261U, // LDNF1D_IMM_REAL - 256261U, // LDNF1H_D_IMM_REAL - 256261U, // LDNF1H_IMM_REAL - 256261U, // LDNF1H_S_IMM_REAL - 256261U, // LDNF1SB_D_IMM_REAL - 256261U, // LDNF1SB_H_IMM_REAL - 256261U, // LDNF1SB_S_IMM_REAL - 256261U, // LDNF1SH_D_IMM_REAL - 256261U, // LDNF1SH_S_IMM_REAL - 256261U, // LDNF1SW_D_IMM_REAL - 256261U, // LDNF1W_D_IMM_REAL - 256261U, // LDNF1W_IMM_REAL - 11084043U, // LDNPDi - 11608331U, // LDNPQi - 12132619U, // LDNPSi - 12132619U, // LDNPWi - 11084043U, // LDNPXi - 256261U, // LDNT1B_ZRI - 4357U, // LDNT1B_ZRR - 256261U, // LDNT1D_ZRI - 4421U, // LDNT1D_ZRR - 256261U, // LDNT1H_ZRI - 4485U, // LDNT1H_ZRR - 256261U, // LDNT1W_ZRI - 4741U, // LDNT1W_ZRR - 11084043U, // LDPDi - 12847371U, // LDPDpost - 180431115U, // LDPDpre - 11608331U, // LDPQi - 13371659U, // LDPQpost - 180955403U, // LDPQpre - 12132619U, // LDPSWi - 13895947U, // LDPSWpost - 181479691U, // LDPSWpre - 12132619U, // LDPSi - 13895947U, // LDPSpost - 181479691U, // LDPSpre - 12132619U, // LDPWi - 13895947U, // LDPWpost - 181479691U, // LDPWpre - 11084043U, // LDPXi - 12847371U, // LDPXpost - 180431115U, // LDPXpre - 4933U, // LDRAAindexed - 274885U, // LDRAAwriteback - 4933U, // LDRABindexed - 274885U, // LDRABwriteback - 28U, // LDRBBpost - 272645U, // LDRBBpre - 14229765U, // LDRBBroW - 14754053U, // LDRBBroX - 4997U, // LDRBBui - 28U, // LDRBpost - 272645U, // LDRBpre - 14229765U, // LDRBroW - 14754053U, // LDRBroX - 4997U, // LDRBui - 0U, // LDRDl - 28U, // LDRDpost - 272645U, // LDRDpre - 15278341U, // LDRDroW - 15802629U, // LDRDroX - 5061U, // LDRDui - 28U, // LDRHHpost - 272645U, // LDRHHpre - 16326917U, // LDRHHroW - 16851205U, // LDRHHroX - 5125U, // LDRHHui - 28U, // LDRHpost - 272645U, // LDRHpre - 16326917U, // LDRHroW - 16851205U, // LDRHroX - 5125U, // LDRHui - 0U, // LDRQl - 28U, // LDRQpost - 272645U, // LDRQpre - 17375493U, // LDRQroW - 17899781U, // LDRQroX - 5189U, // LDRQui - 28U, // LDRSBWpost - 272645U, // LDRSBWpre - 14229765U, // LDRSBWroW - 14754053U, // LDRSBWroX - 4997U, // LDRSBWui - 28U, // LDRSBXpost - 272645U, // LDRSBXpre - 14229765U, // LDRSBXroW - 14754053U, // LDRSBXroX - 4997U, // LDRSBXui - 28U, // LDRSHWpost - 272645U, // LDRSHWpre - 16326917U, // LDRSHWroW - 16851205U, // LDRSHWroX - 5125U, // LDRSHWui - 28U, // LDRSHXpost - 272645U, // LDRSHXpre - 16326917U, // LDRSHXroW - 16851205U, // LDRSHXroX - 5125U, // LDRSHXui - 0U, // LDRSWl - 28U, // LDRSWpost - 272645U, // LDRSWpre - 18424069U, // LDRSWroW - 18948357U, // LDRSWroX - 5253U, // LDRSWui - 0U, // LDRSl - 28U, // LDRSpost - 272645U, // LDRSpre - 18424069U, // LDRSroW - 18948357U, // LDRSroX - 5253U, // LDRSui - 0U, // LDRWl - 28U, // LDRWpost - 272645U, // LDRWpre - 18424069U, // LDRWroW - 18948357U, // LDRWroX - 5253U, // LDRWui - 0U, // LDRXl - 28U, // LDRXpost - 272645U, // LDRXpre - 15278341U, // LDRXroW - 15802629U, // LDRXroX - 5061U, // LDRXui - 254213U, // LDR_PXI - 254213U, // LDR_ZXI - 0U, // LDSETAB - 0U, // LDSETAH - 0U, // LDSETALB - 0U, // LDSETALH - 0U, // LDSETALW - 0U, // LDSETALX - 0U, // LDSETAW - 0U, // LDSETAX - 0U, // LDSETB - 0U, // LDSETH - 0U, // LDSETLB - 0U, // LDSETLH - 0U, // LDSETLW - 0U, // LDSETLX - 0U, // LDSETW - 0U, // LDSETX - 0U, // LDSMAXAB - 0U, // LDSMAXAH - 0U, // LDSMAXALB - 0U, // LDSMAXALH - 0U, // LDSMAXALW - 0U, // LDSMAXALX - 0U, // LDSMAXAW - 0U, // LDSMAXAX - 0U, // LDSMAXB - 0U, // LDSMAXH - 0U, // LDSMAXLB - 0U, // LDSMAXLH - 0U, // LDSMAXLW - 0U, // LDSMAXLX - 0U, // LDSMAXW - 0U, // LDSMAXX - 0U, // LDSMINAB - 0U, // LDSMINAH - 0U, // LDSMINALB - 0U, // LDSMINALH - 0U, // LDSMINALW - 0U, // LDSMINALX - 0U, // LDSMINAW - 0U, // LDSMINAX - 0U, // LDSMINB - 0U, // LDSMINH - 0U, // LDSMINLB - 0U, // LDSMINLH - 0U, // LDSMINLW - 0U, // LDSMINLX - 0U, // LDSMINW - 0U, // LDSMINX - 114949U, // LDTRBi - 114949U, // LDTRHi - 114949U, // LDTRSBWi - 114949U, // LDTRSBXi - 114949U, // LDTRSHWi - 114949U, // LDTRSHXi - 114949U, // LDTRSWi - 114949U, // LDTRWi - 114949U, // LDTRXi - 0U, // LDUMAXAB - 0U, // LDUMAXAH - 0U, // LDUMAXALB - 0U, // LDUMAXALH - 0U, // LDUMAXALW - 0U, // LDUMAXALX - 0U, // LDUMAXAW - 0U, // LDUMAXAX - 0U, // LDUMAXB - 0U, // LDUMAXH - 0U, // LDUMAXLB - 0U, // LDUMAXLH - 0U, // LDUMAXLW - 0U, // LDUMAXLX - 0U, // LDUMAXW - 0U, // LDUMAXX - 0U, // LDUMINAB - 0U, // LDUMINAH - 0U, // LDUMINALB - 0U, // LDUMINALH - 0U, // LDUMINALW - 0U, // LDUMINALX - 0U, // LDUMINAW - 0U, // LDUMINAX - 0U, // LDUMINB - 0U, // LDUMINH - 0U, // LDUMINLB - 0U, // LDUMINLH - 0U, // LDUMINLW - 0U, // LDUMINLX - 0U, // LDUMINW - 0U, // LDUMINX - 114949U, // LDURBBi - 114949U, // LDURBi - 114949U, // LDURDi - 114949U, // LDURHHi - 114949U, // LDURHi - 114949U, // LDURQi - 114949U, // LDURSBWi - 114949U, // LDURSBXi - 114949U, // LDURSHWi - 114949U, // LDURSHXi - 114949U, // LDURSWi - 114949U, // LDURSi - 114949U, // LDURWi - 114949U, // LDURXi - 114955U, // LDXPW - 114955U, // LDXPX - 27U, // LDXRB - 27U, // LDXRH - 27U, // LDXRW - 27U, // LDXRX - 0U, // LOADgot - 74560U, // LSLR_ZPmZ_B - 598912U, // LSLR_ZPmZ_D - 1131465U, // LSLR_ZPmZ_H - 1647616U, // LSLR_ZPmZ_S - 261U, // LSLVWr - 261U, // LSLVXr - 598848U, // LSL_WIDE_ZPmZ_B - 99273U, // LSL_WIDE_ZPmZ_H - 599040U, // LSL_WIDE_ZPmZ_S - 901U, // LSL_WIDE_ZZZ_B - 10U, // LSL_WIDE_ZZZ_H - 901U, // LSL_WIDE_ZZZ_S - 2171712U, // LSL_ZPmI_B - 2171776U, // LSL_ZPmI_D - 91081U, // LSL_ZPmI_H - 2171904U, // LSL_ZPmI_S - 74560U, // LSL_ZPmZ_B - 598912U, // LSL_ZPmZ_D - 1131465U, // LSL_ZPmZ_H - 1647616U, // LSL_ZPmZ_S - 261U, // LSL_ZZI_B - 261U, // LSL_ZZI_D - 11U, // LSL_ZZI_H - 261U, // LSL_ZZI_S - 74560U, // LSRR_ZPmZ_B - 598912U, // LSRR_ZPmZ_D - 1131465U, // LSRR_ZPmZ_H - 1647616U, // LSRR_ZPmZ_S - 261U, // LSRVWr - 261U, // LSRVXr - 598848U, // LSR_WIDE_ZPmZ_B - 99273U, // LSR_WIDE_ZPmZ_H - 599040U, // LSR_WIDE_ZPmZ_S - 901U, // LSR_WIDE_ZZZ_B - 10U, // LSR_WIDE_ZZZ_H - 901U, // LSR_WIDE_ZZZ_S - 2171712U, // LSR_ZPmI_B - 2171776U, // LSR_ZPmI_D - 91081U, // LSR_ZPmI_H - 2171904U, // LSR_ZPmI_S - 74560U, // LSR_ZPmZ_B - 598912U, // LSR_ZPmZ_D - 1131465U, // LSR_ZPmZ_H - 1647616U, // LSR_ZPmZ_S - 261U, // LSR_ZZI_B - 261U, // LSR_ZZI_D - 11U, // LSR_ZZI_H - 261U, // LSR_ZZI_S - 2171141U, // MADDWrrr - 2171141U, // MADDXrrr - 19472384U, // MAD_ZPmZZ_B - 6889536U, // MAD_ZPmZZ_D - 1246144U, // MAD_ZPmZZ_H - 7413952U, // MAD_ZPmZZ_S - 19472384U, // MLA_ZPmZZ_B - 6889536U, // MLA_ZPmZZ_D - 1246144U, // MLA_ZPmZZ_H - 7413952U, // MLA_ZPmZZ_S - 33159U, // MLAv16i8 - 41351U, // MLAv2i32 - 9126279U, // MLAv2i32_indexed - 49544U, // MLAv4i16 - 9118088U, // MLAv4i16_indexed - 16774U, // MLAv4i32 - 9126278U, // MLAv4i32_indexed - 24966U, // MLAv8i16 - 9118086U, // MLAv8i16_indexed - 57736U, // MLAv8i8 - 19472384U, // MLS_ZPmZZ_B - 6889536U, // MLS_ZPmZZ_D - 1246144U, // MLS_ZPmZZ_H - 7413952U, // MLS_ZPmZZ_S - 33159U, // MLSv16i8 - 41351U, // MLSv2i32 - 9126279U, // MLSv2i32_indexed - 49544U, // MLSv4i16 - 9118088U, // MLSv4i16_indexed - 16774U, // MLSv4i32 - 9126278U, // MLSv4i32_indexed - 24966U, // MLSv8i16 - 9118086U, // MLSv8i16_indexed - 57736U, // MLSv8i8 - 0U, // MOVID - 1U, // MOVIv16b_ns - 0U, // MOVIv2d_ns - 28U, // MOVIv2i32 - 28U, // MOVIv2s_msl - 28U, // MOVIv4i16 - 28U, // MOVIv4i32 - 28U, // MOVIv4s_msl - 1U, // MOVIv8b_ns - 28U, // MOVIv8i16 - 0U, // MOVKWi - 0U, // MOVKXi - 28U, // MOVNWi - 28U, // MOVNXi - 0U, // MOVPRFX_ZPmZ_B - 64U, // MOVPRFX_ZPmZ_D - 128U, // MOVPRFX_ZPmZ_H - 192U, // MOVPRFX_ZPmZ_S - 842U, // MOVPRFX_ZPzZ_B - 906U, // MOVPRFX_ZPzZ_D - 137U, // MOVPRFX_ZPzZ_H - 1034U, // MOVPRFX_ZPzZ_S - 1U, // MOVPRFX_ZZ - 28U, // MOVZWi - 28U, // MOVZXi - 0U, // MOVaddr - 0U, // MOVaddrBA - 0U, // MOVaddrCP - 0U, // MOVaddrEXT - 0U, // MOVaddrJT - 0U, // MOVaddrTLS - 0U, // MOVbaseTLS - 0U, // MOVi32imm - 0U, // MOVi64imm - 0U, // MRS - 19472384U, // MSB_ZPmZZ_B - 6889536U, // MSB_ZPmZZ_D - 1246144U, // MSB_ZPmZZ_H - 7413952U, // MSB_ZPmZZ_S - 0U, // MSR - 0U, // MSRpstateImm1 - 0U, // MSRpstateImm4 - 2171141U, // MSUBWrrr - 2171141U, // MSUBXrrr - 261U, // MUL_ZI_B - 261U, // MUL_ZI_D - 11U, // MUL_ZI_H - 261U, // MUL_ZI_S - 74560U, // MUL_ZPmZ_B - 598912U, // MUL_ZPmZ_D - 1131465U, // MUL_ZPmZ_H - 1647616U, // MUL_ZPmZ_S - 33095U, // MULv16i8 - 41287U, // MULv2i32 - 10174791U, // MULv2i32_indexed - 49480U, // MULv4i16 - 10166600U, // MULv4i16_indexed - 16710U, // MULv4i32 - 10174790U, // MULv4i32_indexed - 24902U, // MULv8i16 - 10166598U, // MULv8i16_indexed - 57672U, // MULv8i8 - 28U, // MVNIv2i32 - 28U, // MVNIv2s_msl - 28U, // MVNIv4i16 - 28U, // MVNIv4i32 - 28U, // MVNIv4s_msl - 28U, // MVNIv8i16 - 74570U, // NANDS_PPzPP - 74570U, // NAND_PPzPP - 0U, // NEG_ZPmZ_B - 64U, // NEG_ZPmZ_D - 128U, // NEG_ZPmZ_H - 192U, // NEG_ZPmZ_S - 1U, // NEGv16i8 - 1U, // NEGv1i64 - 2U, // NEGv2i32 - 2U, // NEGv2i64 - 3U, // NEGv4i16 - 3U, // NEGv4i32 - 4U, // NEGv8i16 - 4U, // NEGv8i8 - 74570U, // NORS_PPzPP - 74570U, // NOR_PPzPP - 0U, // NOT_ZPmZ_B - 64U, // NOT_ZPmZ_D - 128U, // NOT_ZPmZ_H - 192U, // NOT_ZPmZ_S - 1U, // NOTv16i8 - 4U, // NOTv8i8 - 74570U, // ORNS_PPzPP - 0U, // ORNWrr - 517U, // ORNWrs - 0U, // ORNXrr - 517U, // ORNXrs - 74570U, // ORN_PPzPP - 33095U, // ORNv16i8 - 57672U, // ORNv8i8 - 74570U, // ORRS_PPzPP - 2117U, // ORRWri - 0U, // ORRWrr - 517U, // ORRWrs - 2181U, // ORRXri - 0U, // ORRXrr - 517U, // ORRXrs - 74570U, // ORR_PPzPP - 2181U, // ORR_ZI - 74560U, // ORR_ZPmZ_B - 598912U, // ORR_ZPmZ_D - 1131465U, // ORR_ZPmZ_H - 1647616U, // ORR_ZPmZ_S - 901U, // ORR_ZZZ - 33095U, // ORRv16i8 - 0U, // ORRv2i32 - 0U, // ORRv4i16 - 0U, // ORRv4i32 - 0U, // ORRv8i16 - 57672U, // ORRv8i8 - 837U, // ORV_VPZ_B - 901U, // ORV_VPZ_D - 2245U, // ORV_VPZ_H - 1029U, // ORV_VPZ_S - 1U, // PACDA - 1U, // PACDB - 0U, // PACDZA - 0U, // PACDZB - 261U, // PACGA - 1U, // PACIA - 0U, // PACIA1716 - 0U, // PACIASP - 0U, // PACIAZ - 1U, // PACIB - 0U, // PACIB1716 - 0U, // PACIBSP - 0U, // PACIBZ - 0U, // PACIZA - 0U, // PACIZB - 0U, // PFALSE - 33095U, // PMULLv16i8 - 0U, // PMULLv1i64 - 0U, // PMULLv2i64 - 57672U, // PMULLv8i8 - 33095U, // PMULv16i8 - 57672U, // PMULv8i8 - 837U, // PNEXT_B - 901U, // PNEXT_D - 137U, // PNEXT_H - 1029U, // PNEXT_S - 27U, // PRFB_D_PZI - 29U, // PRFB_D_SCALED - 29U, // PRFB_D_SXTW_SCALED - 30U, // PRFB_D_UXTW_SCALED - 5329U, // PRFB_PRI - 30U, // PRFB_PRR - 27U, // PRFB_S_PZI - 31U, // PRFB_S_SXTW_SCALED - 31U, // PRFB_S_UXTW_SCALED - 0U, // PRFD_D_PZI - 32U, // PRFD_D_SCALED - 32U, // PRFD_D_SXTW_SCALED - 33U, // PRFD_D_UXTW_SCALED - 5329U, // PRFD_PRI - 33U, // PRFD_PRR - 0U, // PRFD_S_PZI - 34U, // PRFD_S_SXTW_SCALED - 34U, // PRFD_S_UXTW_SCALED - 0U, // PRFH_D_PZI - 35U, // PRFH_D_SCALED - 35U, // PRFH_D_SXTW_SCALED - 36U, // PRFH_D_UXTW_SCALED - 5329U, // PRFH_PRI - 36U, // PRFH_PRR - 0U, // PRFH_S_PZI - 37U, // PRFH_S_SXTW_SCALED - 37U, // PRFH_S_UXTW_SCALED - 0U, // PRFMl - 15278341U, // PRFMroW - 15802629U, // PRFMroX - 5061U, // PRFMui - 38U, // PRFS_PRR - 114949U, // PRFUMi - 0U, // PRFW_D_PZI - 38U, // PRFW_D_SCALED - 39U, // PRFW_D_SXTW_SCALED - 39U, // PRFW_D_UXTW_SCALED - 5329U, // PRFW_PRI - 0U, // PRFW_S_PZI - 40U, // PRFW_S_SXTW_SCALED - 40U, // PRFW_S_UXTW_SCALED - 1U, // PTEST_PP - 1U, // PTRUES_B - 1U, // PTRUES_D - 0U, // PTRUES_H - 1U, // PTRUES_S - 1U, // PTRUE_B - 1U, // PTRUE_D - 0U, // PTRUE_H - 1U, // PTRUE_S - 0U, // PUNPKHI_PP - 0U, // PUNPKLO_PP - 8517U, // RADDHNv2i64_v2i32 - 8581U, // RADDHNv2i64_v4i32 - 16710U, // RADDHNv4i32_v4i16 - 16774U, // RADDHNv4i32_v8i16 - 24966U, // RADDHNv8i16_v16i8 - 24902U, // RADDHNv8i16_v8i8 - 8517U, // RAX1 - 1U, // RBITWr - 1U, // RBITXr - 0U, // RBIT_ZPmZ_B - 64U, // RBIT_ZPmZ_D - 128U, // RBIT_ZPmZ_H - 192U, // RBIT_ZPmZ_S - 1U, // RBITv16i8 - 4U, // RBITv8i8 - 41U, // RDFFRS_PPz - 0U, // RDFFR_P - 41U, // RDFFR_PPz - 1U, // RDVLI_XI - 0U, // RET - 0U, // RETAA - 0U, // RETAB - 0U, // RET_ReallyLR - 1U, // REV16Wr - 1U, // REV16Xr - 1U, // REV16v16i8 - 4U, // REV16v8i8 - 1U, // REV32Xr - 1U, // REV32v16i8 - 3U, // REV32v4i16 - 4U, // REV32v8i16 - 4U, // REV32v8i8 - 1U, // REV64v16i8 - 2U, // REV64v2i32 - 3U, // REV64v4i16 - 3U, // REV64v4i32 - 4U, // REV64v8i16 - 4U, // REV64v8i8 - 64U, // REVB_ZPmZ_D - 128U, // REVB_ZPmZ_H - 192U, // REVB_ZPmZ_S - 64U, // REVH_ZPmZ_D - 192U, // REVH_ZPmZ_S - 64U, // REVW_ZPmZ_D - 1U, // REVWr - 1U, // REVXr - 1U, // REV_PP_B - 1U, // REV_PP_D - 0U, // REV_PP_H - 1U, // REV_PP_S - 1U, // REV_ZZ_B - 1U, // REV_ZZ_D - 0U, // REV_ZZ_H - 1U, // REV_ZZ_S - 261U, // RMIF - 261U, // RORVWr - 261U, // RORVXr - 2310U, // RSHRNv16i8_shift - 261U, // RSHRNv2i32_shift - 262U, // RSHRNv4i16_shift - 2309U, // RSHRNv4i32_shift - 2310U, // RSHRNv8i16_shift - 262U, // RSHRNv8i8_shift - 8517U, // RSUBHNv2i64_v2i32 - 8581U, // RSUBHNv2i64_v4i32 - 16710U, // RSUBHNv4i32_v4i16 - 16774U, // RSUBHNv4i32_v8i16 - 24966U, // RSUBHNv8i16_v16i8 - 24902U, // RSUBHNv8i16_v8i8 - 33159U, // SABALv16i8_v8i16 - 41351U, // SABALv2i32_v2i64 - 49544U, // SABALv4i16_v4i32 - 16774U, // SABALv4i32_v2i64 - 24966U, // SABALv8i16_v4i32 - 57736U, // SABALv8i8_v8i16 - 33159U, // SABAv16i8 - 41351U, // SABAv2i32 - 49544U, // SABAv4i16 - 16774U, // SABAv4i32 - 24966U, // SABAv8i16 - 57736U, // SABAv8i8 - 33095U, // SABDLv16i8_v8i16 - 41287U, // SABDLv2i32_v2i64 - 49480U, // SABDLv4i16_v4i32 - 16710U, // SABDLv4i32_v2i64 - 24902U, // SABDLv8i16_v4i32 - 57672U, // SABDLv8i8_v8i16 - 74560U, // SABD_ZPmZ_B - 598912U, // SABD_ZPmZ_D - 1131465U, // SABD_ZPmZ_H - 1647616U, // SABD_ZPmZ_S - 33095U, // SABDv16i8 - 41287U, // SABDv2i32 - 49480U, // SABDv4i16 - 16710U, // SABDv4i32 - 24902U, // SABDv8i16 - 57672U, // SABDv8i8 - 1U, // SADALPv16i8_v8i16 - 2U, // SADALPv2i32_v1i64 - 3U, // SADALPv4i16_v2i32 - 3U, // SADALPv4i32_v2i64 - 4U, // SADALPv8i16_v4i32 - 4U, // SADALPv8i8_v4i16 - 1U, // SADDLPv16i8_v8i16 - 2U, // SADDLPv2i32_v1i64 - 3U, // SADDLPv4i16_v2i32 - 3U, // SADDLPv4i32_v2i64 - 4U, // SADDLPv8i16_v4i32 - 4U, // SADDLPv8i8_v4i16 - 1U, // SADDLVv16i8v - 3U, // SADDLVv4i16v - 3U, // SADDLVv4i32v - 4U, // SADDLVv8i16v - 4U, // SADDLVv8i8v - 33095U, // SADDLv16i8_v8i16 - 41287U, // SADDLv2i32_v2i64 - 49480U, // SADDLv4i16_v4i32 - 16710U, // SADDLv4i32_v2i64 - 24902U, // SADDLv8i16_v4i32 - 57672U, // SADDLv8i8_v8i16 - 837U, // SADDV_VPZ_B - 2245U, // SADDV_VPZ_H - 1029U, // SADDV_VPZ_S - 33094U, // SADDWv16i8_v8i16 - 41285U, // SADDWv2i32_v2i64 - 49478U, // SADDWv4i16_v4i32 - 16709U, // SADDWv4i32_v2i64 - 24902U, // SADDWv8i16_v4i32 - 57670U, // SADDWv8i8_v8i16 - 261U, // SBCSWr - 261U, // SBCSXr - 261U, // SBCWr - 261U, // SBCXr - 2171141U, // SBFMWri - 2171141U, // SBFMXri - 261U, // SCVTFSWDri - 261U, // SCVTFSWHri - 261U, // SCVTFSWSri - 261U, // SCVTFSXDri - 261U, // SCVTFSXHri - 261U, // SCVTFSXSri - 1U, // SCVTFUWDri - 1U, // SCVTFUWHri - 1U, // SCVTFUWSri - 1U, // SCVTFUXDri - 1U, // SCVTFUXHri - 1U, // SCVTFUXSri - 64U, // SCVTF_ZPmZ_DtoD - 153U, // SCVTF_ZPmZ_DtoH - 64U, // SCVTF_ZPmZ_DtoS - 128U, // SCVTF_ZPmZ_HtoH - 192U, // SCVTF_ZPmZ_StoD - 152U, // SCVTF_ZPmZ_StoH - 192U, // SCVTF_ZPmZ_StoS - 261U, // SCVTFd - 261U, // SCVTFh - 261U, // SCVTFs - 1U, // SCVTFv1i16 - 1U, // SCVTFv1i32 - 1U, // SCVTFv1i64 - 2U, // SCVTFv2f32 - 2U, // SCVTFv2f64 - 263U, // SCVTFv2i32_shift - 261U, // SCVTFv2i64_shift - 3U, // SCVTFv4f16 - 3U, // SCVTFv4f32 - 264U, // SCVTFv4i16_shift - 262U, // SCVTFv4i32_shift - 4U, // SCVTFv8f16 - 262U, // SCVTFv8i16_shift - 598912U, // SDIVR_ZPmZ_D - 1647616U, // SDIVR_ZPmZ_S - 261U, // SDIVWr - 261U, // SDIVXr - 598912U, // SDIV_ZPmZ_D - 1647616U, // SDIV_ZPmZ_S - 41U, // SDOT_ZZZI_D - 41U, // SDOT_ZZZI_S - 1U, // SDOT_ZZZ_D - 1U, // SDOT_ZZZ_S - 278919U, // SDOTlanev16i8 - 278920U, // SDOTlanev8i8 - 33159U, // SDOTv16i8 - 57736U, // SDOTv8i8 - 74565U, // SEL_PPPP - 74565U, // SEL_ZPZZ_B - 598917U, // SEL_ZPZZ_D - 1131465U, // SEL_ZPZZ_H - 1647621U, // SEL_ZPZZ_S - 0U, // SETF16 - 0U, // SETF8 - 0U, // SETFFR - 16773U, // SHA1Crrr - 1U, // SHA1Hrr - 16773U, // SHA1Mrrr - 16773U, // SHA1Prrr - 16774U, // SHA1SU0rrr - 3U, // SHA1SU1rr - 16773U, // SHA256H2rrr - 16773U, // SHA256Hrrr - 3U, // SHA256SU0rr - 16774U, // SHA256SU1rrr - 8581U, // SHA512H - 8581U, // SHA512H2 - 2U, // SHA512SU0 - 8581U, // SHA512SU1 - 33095U, // SHADDv16i8 - 41287U, // SHADDv2i32 - 49480U, // SHADDv4i16 - 16710U, // SHADDv4i32 - 24902U, // SHADDv8i16 - 57672U, // SHADDv8i8 - 42U, // SHLLv16i8 - 42U, // SHLLv2i32 - 43U, // SHLLv4i16 - 43U, // SHLLv4i32 - 44U, // SHLLv8i16 - 44U, // SHLLv8i8 - 261U, // SHLd - 263U, // SHLv16i8_shift - 263U, // SHLv2i32_shift - 261U, // SHLv2i64_shift - 264U, // SHLv4i16_shift - 262U, // SHLv4i32_shift - 262U, // SHLv8i16_shift - 264U, // SHLv8i8_shift - 2310U, // SHRNv16i8_shift - 261U, // SHRNv2i32_shift - 262U, // SHRNv4i16_shift - 2309U, // SHRNv4i32_shift - 2310U, // SHRNv8i16_shift - 262U, // SHRNv8i8_shift - 33095U, // SHSUBv16i8 - 41287U, // SHSUBv2i32 - 49480U, // SHSUBv4i16 - 16710U, // SHSUBv4i32 - 24902U, // SHSUBv8i16 - 57672U, // SHSUBv8i8 - 2309U, // SLId - 2311U, // SLIv16i8_shift - 2311U, // SLIv2i32_shift - 2309U, // SLIv2i64_shift - 2312U, // SLIv4i16_shift - 2310U, // SLIv4i32_shift - 2310U, // SLIv8i16_shift - 2312U, // SLIv8i8_shift - 16774U, // SM3PARTW1 - 16774U, // SM3PARTW2 - 204120390U, // SM3SS1 - 9126278U, // SM3TT1A - 9126278U, // SM3TT1B - 9126278U, // SM3TT2A - 9126278U, // SM3TT2B - 3U, // SM4E - 16710U, // SM4ENCKEY - 2171141U, // SMADDLrrr - 33095U, // SMAXPv16i8 - 41287U, // SMAXPv2i32 - 49480U, // SMAXPv4i16 - 16710U, // SMAXPv4i32 - 24902U, // SMAXPv8i16 - 57672U, // SMAXPv8i8 - 837U, // SMAXV_VPZ_B - 901U, // SMAXV_VPZ_D - 2245U, // SMAXV_VPZ_H - 1029U, // SMAXV_VPZ_S - 1U, // SMAXVv16i8v - 3U, // SMAXVv4i16v - 3U, // SMAXVv4i32v - 4U, // SMAXVv8i16v - 4U, // SMAXVv8i8v - 261U, // SMAX_ZI_B - 261U, // SMAX_ZI_D - 11U, // SMAX_ZI_H - 261U, // SMAX_ZI_S - 74560U, // SMAX_ZPmZ_B - 598912U, // SMAX_ZPmZ_D - 1131465U, // SMAX_ZPmZ_H - 1647616U, // SMAX_ZPmZ_S - 33095U, // SMAXv16i8 - 41287U, // SMAXv2i32 - 49480U, // SMAXv4i16 - 16710U, // SMAXv4i32 - 24902U, // SMAXv8i16 - 57672U, // SMAXv8i8 - 0U, // SMC - 33095U, // SMINPv16i8 - 41287U, // SMINPv2i32 - 49480U, // SMINPv4i16 - 16710U, // SMINPv4i32 - 24902U, // SMINPv8i16 - 57672U, // SMINPv8i8 - 837U, // SMINV_VPZ_B - 901U, // SMINV_VPZ_D - 2245U, // SMINV_VPZ_H - 1029U, // SMINV_VPZ_S - 1U, // SMINVv16i8v - 3U, // SMINVv4i16v - 3U, // SMINVv4i32v - 4U, // SMINVv8i16v - 4U, // SMINVv8i8v - 261U, // SMIN_ZI_B - 261U, // SMIN_ZI_D - 11U, // SMIN_ZI_H - 261U, // SMIN_ZI_S - 74560U, // SMIN_ZPmZ_B - 598912U, // SMIN_ZPmZ_D - 1131465U, // SMIN_ZPmZ_H - 1647616U, // SMIN_ZPmZ_S - 33095U, // SMINv16i8 - 41287U, // SMINv2i32 - 49480U, // SMINv4i16 - 16710U, // SMINv4i32 - 24902U, // SMINv8i16 - 57672U, // SMINv8i8 - 33159U, // SMLALv16i8_v8i16 - 9126279U, // SMLALv2i32_indexed - 41351U, // SMLALv2i32_v2i64 - 9118088U, // SMLALv4i16_indexed - 49544U, // SMLALv4i16_v4i32 - 9126278U, // SMLALv4i32_indexed - 16774U, // SMLALv4i32_v2i64 - 9118086U, // SMLALv8i16_indexed - 24966U, // SMLALv8i16_v4i32 - 57736U, // SMLALv8i8_v8i16 - 33159U, // SMLSLv16i8_v8i16 - 9126279U, // SMLSLv2i32_indexed - 41351U, // SMLSLv2i32_v2i64 - 9118088U, // SMLSLv4i16_indexed - 49544U, // SMLSLv4i16_v4i32 - 9126278U, // SMLSLv4i32_indexed - 16774U, // SMLSLv4i32_v2i64 - 9118086U, // SMLSLv8i16_indexed - 24966U, // SMLSLv8i16_v4i32 - 57736U, // SMLSLv8i8_v8i16 - 2770U, // SMOVvi16to32 - 2770U, // SMOVvi16to64 - 2770U, // SMOVvi32to64 - 2771U, // SMOVvi8to32 - 2771U, // SMOVvi8to64 - 2171141U, // SMSUBLrrr - 74560U, // SMULH_ZPmZ_B - 598912U, // SMULH_ZPmZ_D - 1131465U, // SMULH_ZPmZ_H - 1647616U, // SMULH_ZPmZ_S - 261U, // SMULHrr - 33095U, // SMULLv16i8_v8i16 - 10174791U, // SMULLv2i32_indexed - 41287U, // SMULLv2i32_v2i64 - 10166600U, // SMULLv4i16_indexed - 49480U, // SMULLv4i16_v4i32 - 10174790U, // SMULLv4i32_indexed - 16710U, // SMULLv4i32_v2i64 - 10166598U, // SMULLv8i16_indexed - 24902U, // SMULLv8i16_v4i32 - 57672U, // SMULLv8i8_v8i16 - 74565U, // SPLICE_ZPZ_B - 598917U, // SPLICE_ZPZ_D - 1131465U, // SPLICE_ZPZ_H - 1647621U, // SPLICE_ZPZ_S - 1U, // SQABSv16i8 - 1U, // SQABSv1i16 - 1U, // SQABSv1i32 - 1U, // SQABSv1i64 - 1U, // SQABSv1i8 - 2U, // SQABSv2i32 - 2U, // SQABSv2i64 - 3U, // SQABSv4i16 - 3U, // SQABSv4i32 - 4U, // SQABSv8i16 - 4U, // SQABSv8i8 - 645U, // SQADD_ZI_B - 709U, // SQADD_ZI_D - 9U, // SQADD_ZI_H - 773U, // SQADD_ZI_S - 837U, // SQADD_ZZZ_B - 901U, // SQADD_ZZZ_D - 137U, // SQADD_ZZZ_H - 1029U, // SQADD_ZZZ_S - 33095U, // SQADDv16i8 - 261U, // SQADDv1i16 - 261U, // SQADDv1i32 - 261U, // SQADDv1i64 - 261U, // SQADDv1i8 - 41287U, // SQADDv2i32 - 8517U, // SQADDv2i64 - 49480U, // SQADDv4i16 - 16710U, // SQADDv4i32 - 24902U, // SQADDv8i16 - 57672U, // SQADDv8i8 - 0U, // SQDECB_XPiI - 0U, // SQDECB_XPiWdI - 0U, // SQDECD_XPiI - 0U, // SQDECD_XPiWdI - 0U, // SQDECD_ZPiI - 0U, // SQDECH_XPiI - 0U, // SQDECH_XPiWdI - 0U, // SQDECH_ZPiI - 5381U, // SQDECP_XPWd_B - 5381U, // SQDECP_XPWd_D - 5381U, // SQDECP_XPWd_H - 5381U, // SQDECP_XPWd_S - 1U, // SQDECP_XP_B - 1U, // SQDECP_XP_D - 1U, // SQDECP_XP_H - 1U, // SQDECP_XP_S - 1U, // SQDECP_ZP_D - 0U, // SQDECP_ZP_H - 1U, // SQDECP_ZP_S - 0U, // SQDECW_XPiI - 0U, // SQDECW_XPiWdI - 0U, // SQDECW_ZPiI - 2309U, // SQDMLALi16 - 2309U, // SQDMLALi32 - 9118085U, // SQDMLALv1i32_indexed - 9126277U, // SQDMLALv1i64_indexed - 9126279U, // SQDMLALv2i32_indexed - 41351U, // SQDMLALv2i32_v2i64 - 9118088U, // SQDMLALv4i16_indexed - 49544U, // SQDMLALv4i16_v4i32 - 9126278U, // SQDMLALv4i32_indexed - 16774U, // SQDMLALv4i32_v2i64 - 9118086U, // SQDMLALv8i16_indexed - 24966U, // SQDMLALv8i16_v4i32 - 2309U, // SQDMLSLi16 - 2309U, // SQDMLSLi32 - 9118085U, // SQDMLSLv1i32_indexed - 9126277U, // SQDMLSLv1i64_indexed - 9126279U, // SQDMLSLv2i32_indexed - 41351U, // SQDMLSLv2i32_v2i64 - 9118088U, // SQDMLSLv4i16_indexed - 49544U, // SQDMLSLv4i16_v4i32 - 9126278U, // SQDMLSLv4i32_indexed - 16774U, // SQDMLSLv4i32_v2i64 - 9118086U, // SQDMLSLv8i16_indexed - 24966U, // SQDMLSLv8i16_v4i32 - 261U, // SQDMULHv1i16 - 10166597U, // SQDMULHv1i16_indexed - 261U, // SQDMULHv1i32 - 10174789U, // SQDMULHv1i32_indexed - 41287U, // SQDMULHv2i32 - 10174791U, // SQDMULHv2i32_indexed - 49480U, // SQDMULHv4i16 - 10166600U, // SQDMULHv4i16_indexed - 16710U, // SQDMULHv4i32 - 10174790U, // SQDMULHv4i32_indexed - 24902U, // SQDMULHv8i16 - 10166598U, // SQDMULHv8i16_indexed - 261U, // SQDMULLi16 - 261U, // SQDMULLi32 - 10166597U, // SQDMULLv1i32_indexed - 10174789U, // SQDMULLv1i64_indexed - 10174791U, // SQDMULLv2i32_indexed - 41287U, // SQDMULLv2i32_v2i64 - 10166600U, // SQDMULLv4i16_indexed - 49480U, // SQDMULLv4i16_v4i32 - 10174790U, // SQDMULLv4i32_indexed - 16710U, // SQDMULLv4i32_v2i64 - 10166598U, // SQDMULLv8i16_indexed - 24902U, // SQDMULLv8i16_v4i32 - 0U, // SQINCB_XPiI - 0U, // SQINCB_XPiWdI - 0U, // SQINCD_XPiI - 0U, // SQINCD_XPiWdI - 0U, // SQINCD_ZPiI - 0U, // SQINCH_XPiI - 0U, // SQINCH_XPiWdI - 0U, // SQINCH_ZPiI - 5381U, // SQINCP_XPWd_B - 5381U, // SQINCP_XPWd_D - 5381U, // SQINCP_XPWd_H - 5381U, // SQINCP_XPWd_S - 1U, // SQINCP_XP_B - 1U, // SQINCP_XP_D - 1U, // SQINCP_XP_H - 1U, // SQINCP_XP_S - 1U, // SQINCP_ZP_D - 0U, // SQINCP_ZP_H - 1U, // SQINCP_ZP_S - 0U, // SQINCW_XPiI - 0U, // SQINCW_XPiWdI - 0U, // SQINCW_ZPiI - 1U, // SQNEGv16i8 - 1U, // SQNEGv1i16 - 1U, // SQNEGv1i32 - 1U, // SQNEGv1i64 - 1U, // SQNEGv1i8 - 2U, // SQNEGv2i32 - 2U, // SQNEGv2i64 - 3U, // SQNEGv4i16 - 3U, // SQNEGv4i32 - 4U, // SQNEGv8i16 - 4U, // SQNEGv8i8 - 9118085U, // SQRDMLAHi16_indexed - 9126277U, // SQRDMLAHi32_indexed - 2309U, // SQRDMLAHv1i16 - 2309U, // SQRDMLAHv1i32 - 41351U, // SQRDMLAHv2i32 - 9126279U, // SQRDMLAHv2i32_indexed - 49544U, // SQRDMLAHv4i16 - 9118088U, // SQRDMLAHv4i16_indexed - 16774U, // SQRDMLAHv4i32 - 9126278U, // SQRDMLAHv4i32_indexed - 24966U, // SQRDMLAHv8i16 - 9118086U, // SQRDMLAHv8i16_indexed - 9118085U, // SQRDMLSHi16_indexed - 9126277U, // SQRDMLSHi32_indexed - 2309U, // SQRDMLSHv1i16 - 2309U, // SQRDMLSHv1i32 - 41351U, // SQRDMLSHv2i32 - 9126279U, // SQRDMLSHv2i32_indexed - 49544U, // SQRDMLSHv4i16 - 9118088U, // SQRDMLSHv4i16_indexed - 16774U, // SQRDMLSHv4i32 - 9126278U, // SQRDMLSHv4i32_indexed - 24966U, // SQRDMLSHv8i16 - 9118086U, // SQRDMLSHv8i16_indexed - 261U, // SQRDMULHv1i16 - 10166597U, // SQRDMULHv1i16_indexed - 261U, // SQRDMULHv1i32 - 10174789U, // SQRDMULHv1i32_indexed - 41287U, // SQRDMULHv2i32 - 10174791U, // SQRDMULHv2i32_indexed - 49480U, // SQRDMULHv4i16 - 10166600U, // SQRDMULHv4i16_indexed - 16710U, // SQRDMULHv4i32 - 10174790U, // SQRDMULHv4i32_indexed - 24902U, // SQRDMULHv8i16 - 10166598U, // SQRDMULHv8i16_indexed - 33095U, // SQRSHLv16i8 - 261U, // SQRSHLv1i16 - 261U, // SQRSHLv1i32 - 261U, // SQRSHLv1i64 - 261U, // SQRSHLv1i8 - 41287U, // SQRSHLv2i32 - 8517U, // SQRSHLv2i64 - 49480U, // SQRSHLv4i16 - 16710U, // SQRSHLv4i32 - 24902U, // SQRSHLv8i16 - 57672U, // SQRSHLv8i8 - 261U, // SQRSHRNb - 261U, // SQRSHRNh - 261U, // SQRSHRNs - 2310U, // SQRSHRNv16i8_shift - 261U, // SQRSHRNv2i32_shift - 262U, // SQRSHRNv4i16_shift - 2309U, // SQRSHRNv4i32_shift - 2310U, // SQRSHRNv8i16_shift - 262U, // SQRSHRNv8i8_shift - 261U, // SQRSHRUNb - 261U, // SQRSHRUNh - 261U, // SQRSHRUNs - 2310U, // SQRSHRUNv16i8_shift - 261U, // SQRSHRUNv2i32_shift - 262U, // SQRSHRUNv4i16_shift - 2309U, // SQRSHRUNv4i32_shift - 2310U, // SQRSHRUNv8i16_shift - 262U, // SQRSHRUNv8i8_shift - 261U, // SQSHLUb - 261U, // SQSHLUd - 261U, // SQSHLUh - 261U, // SQSHLUs - 263U, // SQSHLUv16i8_shift - 263U, // SQSHLUv2i32_shift - 261U, // SQSHLUv2i64_shift - 264U, // SQSHLUv4i16_shift - 262U, // SQSHLUv4i32_shift - 262U, // SQSHLUv8i16_shift - 264U, // SQSHLUv8i8_shift - 261U, // SQSHLb - 261U, // SQSHLd - 261U, // SQSHLh - 261U, // SQSHLs - 33095U, // SQSHLv16i8 - 263U, // SQSHLv16i8_shift - 261U, // SQSHLv1i16 - 261U, // SQSHLv1i32 - 261U, // SQSHLv1i64 - 261U, // SQSHLv1i8 - 41287U, // SQSHLv2i32 - 263U, // SQSHLv2i32_shift - 8517U, // SQSHLv2i64 - 261U, // SQSHLv2i64_shift - 49480U, // SQSHLv4i16 - 264U, // SQSHLv4i16_shift - 16710U, // SQSHLv4i32 - 262U, // SQSHLv4i32_shift - 24902U, // SQSHLv8i16 - 262U, // SQSHLv8i16_shift - 57672U, // SQSHLv8i8 - 264U, // SQSHLv8i8_shift - 261U, // SQSHRNb - 261U, // SQSHRNh - 261U, // SQSHRNs - 2310U, // SQSHRNv16i8_shift - 261U, // SQSHRNv2i32_shift - 262U, // SQSHRNv4i16_shift - 2309U, // SQSHRNv4i32_shift - 2310U, // SQSHRNv8i16_shift - 262U, // SQSHRNv8i8_shift - 261U, // SQSHRUNb - 261U, // SQSHRUNh - 261U, // SQSHRUNs - 2310U, // SQSHRUNv16i8_shift - 261U, // SQSHRUNv2i32_shift - 262U, // SQSHRUNv4i16_shift - 2309U, // SQSHRUNv4i32_shift - 2310U, // SQSHRUNv8i16_shift - 262U, // SQSHRUNv8i8_shift - 645U, // SQSUB_ZI_B - 709U, // SQSUB_ZI_D - 9U, // SQSUB_ZI_H - 773U, // SQSUB_ZI_S - 837U, // SQSUB_ZZZ_B - 901U, // SQSUB_ZZZ_D - 137U, // SQSUB_ZZZ_H - 1029U, // SQSUB_ZZZ_S - 33095U, // SQSUBv16i8 - 261U, // SQSUBv1i16 - 261U, // SQSUBv1i32 - 261U, // SQSUBv1i64 - 261U, // SQSUBv1i8 - 41287U, // SQSUBv2i32 - 8517U, // SQSUBv2i64 - 49480U, // SQSUBv4i16 - 16710U, // SQSUBv4i32 - 24902U, // SQSUBv8i16 - 57672U, // SQSUBv8i8 - 4U, // SQXTNv16i8 - 1U, // SQXTNv1i16 - 1U, // SQXTNv1i32 - 1U, // SQXTNv1i8 - 2U, // SQXTNv2i32 - 3U, // SQXTNv4i16 - 2U, // SQXTNv4i32 - 3U, // SQXTNv8i16 - 4U, // SQXTNv8i8 - 4U, // SQXTUNv16i8 - 1U, // SQXTUNv1i16 - 1U, // SQXTUNv1i32 - 1U, // SQXTUNv1i8 - 2U, // SQXTUNv2i32 - 3U, // SQXTUNv4i16 - 2U, // SQXTUNv4i32 - 3U, // SQXTUNv8i16 - 4U, // SQXTUNv8i8 - 33095U, // SRHADDv16i8 - 41287U, // SRHADDv2i32 - 49480U, // SRHADDv4i16 - 16710U, // SRHADDv4i32 - 24902U, // SRHADDv8i16 - 57672U, // SRHADDv8i8 - 2309U, // SRId - 2311U, // SRIv16i8_shift - 2311U, // SRIv2i32_shift - 2309U, // SRIv2i64_shift - 2312U, // SRIv4i16_shift - 2310U, // SRIv4i32_shift - 2310U, // SRIv8i16_shift - 2312U, // SRIv8i8_shift - 33095U, // SRSHLv16i8 - 261U, // SRSHLv1i64 - 41287U, // SRSHLv2i32 - 8517U, // SRSHLv2i64 - 49480U, // SRSHLv4i16 - 16710U, // SRSHLv4i32 - 24902U, // SRSHLv8i16 - 57672U, // SRSHLv8i8 - 261U, // SRSHRd - 263U, // SRSHRv16i8_shift - 263U, // SRSHRv2i32_shift - 261U, // SRSHRv2i64_shift - 264U, // SRSHRv4i16_shift - 262U, // SRSHRv4i32_shift - 262U, // SRSHRv8i16_shift - 264U, // SRSHRv8i8_shift - 2309U, // SRSRAd - 2311U, // SRSRAv16i8_shift - 2311U, // SRSRAv2i32_shift - 2309U, // SRSRAv2i64_shift - 2312U, // SRSRAv4i16_shift - 2310U, // SRSRAv4i32_shift - 2310U, // SRSRAv8i16_shift - 2312U, // SRSRAv8i8_shift - 263U, // SSHLLv16i8_shift - 263U, // SSHLLv2i32_shift - 264U, // SSHLLv4i16_shift - 262U, // SSHLLv4i32_shift - 262U, // SSHLLv8i16_shift - 264U, // SSHLLv8i8_shift - 33095U, // SSHLv16i8 - 261U, // SSHLv1i64 - 41287U, // SSHLv2i32 - 8517U, // SSHLv2i64 - 49480U, // SSHLv4i16 - 16710U, // SSHLv4i32 - 24902U, // SSHLv8i16 - 57672U, // SSHLv8i8 - 261U, // SSHRd - 263U, // SSHRv16i8_shift - 263U, // SSHRv2i32_shift - 261U, // SSHRv2i64_shift - 264U, // SSHRv4i16_shift - 262U, // SSHRv4i32_shift - 262U, // SSHRv8i16_shift - 264U, // SSHRv8i8_shift - 2309U, // SSRAd - 2311U, // SSRAv16i8_shift - 2311U, // SSRAv2i32_shift - 2309U, // SSRAv2i64_shift - 2312U, // SSRAv4i16_shift - 2310U, // SSRAv4i32_shift - 2310U, // SSRAv8i16_shift - 2312U, // SSRAv8i8_shift - 3205U, // SST1B_D - 3153U, // SST1B_D_IMM - 3269U, // SST1B_D_SXTW - 3333U, // SST1B_D_UXTW - 3153U, // SST1B_S_IMM - 3397U, // SST1B_S_SXTW - 3461U, // SST1B_S_UXTW - 3205U, // SST1D - 26U, // SST1D_IMM - 3525U, // SST1D_SCALED - 3269U, // SST1D_SXTW - 3589U, // SST1D_SXTW_SCALED - 3333U, // SST1D_UXTW - 3653U, // SST1D_UXTW_SCALED - 3205U, // SST1H_D - 26U, // SST1H_D_IMM - 3717U, // SST1H_D_SCALED - 3269U, // SST1H_D_SXTW - 3781U, // SST1H_D_SXTW_SCALED - 3333U, // SST1H_D_UXTW - 3845U, // SST1H_D_UXTW_SCALED - 26U, // SST1H_S_IMM - 3397U, // SST1H_S_SXTW - 3909U, // SST1H_S_SXTW_SCALED - 3461U, // SST1H_S_UXTW - 3973U, // SST1H_S_UXTW_SCALED - 3205U, // SST1W_D - 27U, // SST1W_D_IMM - 4037U, // SST1W_D_SCALED - 3269U, // SST1W_D_SXTW - 4101U, // SST1W_D_SXTW_SCALED - 3333U, // SST1W_D_UXTW - 4165U, // SST1W_D_UXTW_SCALED - 27U, // SST1W_IMM - 3397U, // SST1W_SXTW - 4229U, // SST1W_SXTW_SCALED - 3461U, // SST1W_UXTW - 4293U, // SST1W_UXTW_SCALED - 33095U, // SSUBLv16i8_v8i16 - 41287U, // SSUBLv2i32_v2i64 - 49480U, // SSUBLv4i16_v4i32 - 16710U, // SSUBLv4i32_v2i64 - 24902U, // SSUBLv8i16_v4i32 - 57672U, // SSUBLv8i8_v8i16 - 33094U, // SSUBWv16i8_v8i16 - 41285U, // SSUBWv2i32_v2i64 - 49478U, // SSUBWv4i16_v4i32 - 16709U, // SSUBWv4i32_v2i64 - 24902U, // SSUBWv8i16_v4i32 - 57670U, // SSUBWv8i8_v8i16 - 4357U, // ST1B - 4357U, // ST1B_D - 256261U, // ST1B_D_IMM - 4357U, // ST1B_H - 256261U, // ST1B_H_IMM - 256261U, // ST1B_IMM - 4357U, // ST1B_S - 256261U, // ST1B_S_IMM - 4421U, // ST1D - 256261U, // ST1D_IMM - 0U, // ST1Fourv16b - 0U, // ST1Fourv16b_POST - 0U, // ST1Fourv1d - 0U, // ST1Fourv1d_POST - 0U, // ST1Fourv2d - 0U, // ST1Fourv2d_POST - 0U, // ST1Fourv2s - 0U, // ST1Fourv2s_POST - 0U, // ST1Fourv4h - 0U, // ST1Fourv4h_POST - 0U, // ST1Fourv4s - 0U, // ST1Fourv4s_POST - 0U, // ST1Fourv8b - 0U, // ST1Fourv8b_POST - 0U, // ST1Fourv8h - 0U, // ST1Fourv8h_POST - 4485U, // ST1H - 4485U, // ST1H_D - 256261U, // ST1H_D_IMM - 256261U, // ST1H_IMM - 4485U, // ST1H_S - 256261U, // ST1H_S_IMM - 0U, // ST1Onev16b - 0U, // ST1Onev16b_POST - 0U, // ST1Onev1d - 0U, // ST1Onev1d_POST - 0U, // ST1Onev2d - 0U, // ST1Onev2d_POST - 0U, // ST1Onev2s - 0U, // ST1Onev2s_POST - 0U, // ST1Onev4h - 0U, // ST1Onev4h_POST - 0U, // ST1Onev4s - 0U, // ST1Onev4s_POST - 0U, // ST1Onev8b - 0U, // ST1Onev8b_POST - 0U, // ST1Onev8h - 0U, // ST1Onev8h_POST - 0U, // ST1Threev16b - 0U, // ST1Threev16b_POST - 0U, // ST1Threev1d - 0U, // ST1Threev1d_POST - 0U, // ST1Threev2d - 0U, // ST1Threev2d_POST - 0U, // ST1Threev2s - 0U, // ST1Threev2s_POST - 0U, // ST1Threev4h - 0U, // ST1Threev4h_POST - 0U, // ST1Threev4s - 0U, // ST1Threev4s_POST - 0U, // ST1Threev8b - 0U, // ST1Threev8b_POST - 0U, // ST1Threev8h - 0U, // ST1Threev8h_POST - 0U, // ST1Twov16b - 0U, // ST1Twov16b_POST - 0U, // ST1Twov1d - 0U, // ST1Twov1d_POST - 0U, // ST1Twov2d - 0U, // ST1Twov2d_POST - 0U, // ST1Twov2s - 0U, // ST1Twov2s_POST - 0U, // ST1Twov4h - 0U, // ST1Twov4h_POST - 0U, // ST1Twov4s - 0U, // ST1Twov4s_POST - 0U, // ST1Twov8b - 0U, // ST1Twov8b_POST - 0U, // ST1Twov8h - 0U, // ST1Twov8h_POST - 4741U, // ST1W - 4741U, // ST1W_D - 256261U, // ST1W_D_IMM - 256261U, // ST1W_IMM - 0U, // ST1i16 - 0U, // ST1i16_POST - 0U, // ST1i32 - 0U, // ST1i32_POST - 0U, // ST1i64 - 0U, // ST1i64_POST - 0U, // ST1i8 - 0U, // ST1i8_POST - 4357U, // ST2B - 258565U, // ST2B_IMM - 4421U, // ST2D - 258565U, // ST2D_IMM - 4485U, // ST2H - 258565U, // ST2H_IMM - 0U, // ST2Twov16b - 0U, // ST2Twov16b_POST - 0U, // ST2Twov2d - 0U, // ST2Twov2d_POST - 0U, // ST2Twov2s - 0U, // ST2Twov2s_POST - 0U, // ST2Twov4h - 0U, // ST2Twov4h_POST - 0U, // ST2Twov4s - 0U, // ST2Twov4s_POST - 0U, // ST2Twov8b - 0U, // ST2Twov8b_POST - 0U, // ST2Twov8h - 0U, // ST2Twov8h_POST - 4741U, // ST2W - 258565U, // ST2W_IMM - 0U, // ST2i16 - 0U, // ST2i16_POST - 0U, // ST2i32 - 0U, // ST2i32_POST - 0U, // ST2i64 - 0U, // ST2i64_POST - 0U, // ST2i8 - 0U, // ST2i8_POST - 4357U, // ST3B - 4869U, // ST3B_IMM - 4421U, // ST3D - 4869U, // ST3D_IMM - 4485U, // ST3H - 4869U, // ST3H_IMM - 0U, // ST3Threev16b - 0U, // ST3Threev16b_POST - 0U, // ST3Threev2d - 0U, // ST3Threev2d_POST - 0U, // ST3Threev2s - 0U, // ST3Threev2s_POST - 0U, // ST3Threev4h - 0U, // ST3Threev4h_POST - 0U, // ST3Threev4s - 0U, // ST3Threev4s_POST - 0U, // ST3Threev8b - 0U, // ST3Threev8b_POST - 0U, // ST3Threev8h - 0U, // ST3Threev8h_POST - 4741U, // ST3W - 4869U, // ST3W_IMM - 0U, // ST3i16 - 0U, // ST3i16_POST - 0U, // ST3i32 - 0U, // ST3i32_POST - 0U, // ST3i64 - 0U, // ST3i64_POST - 0U, // ST3i8 - 0U, // ST3i8_POST - 4357U, // ST4B - 258757U, // ST4B_IMM - 4421U, // ST4D - 258757U, // ST4D_IMM - 0U, // ST4Fourv16b - 0U, // ST4Fourv16b_POST - 0U, // ST4Fourv2d - 0U, // ST4Fourv2d_POST - 0U, // ST4Fourv2s - 0U, // ST4Fourv2s_POST - 0U, // ST4Fourv4h - 0U, // ST4Fourv4h_POST - 0U, // ST4Fourv4s - 0U, // ST4Fourv4s_POST - 0U, // ST4Fourv8b - 0U, // ST4Fourv8b_POST - 0U, // ST4Fourv8h - 0U, // ST4Fourv8h_POST - 4485U, // ST4H - 258757U, // ST4H_IMM - 4741U, // ST4W - 258757U, // ST4W_IMM - 0U, // ST4i16 - 0U, // ST4i16_POST - 0U, // ST4i32 - 0U, // ST4i32_POST - 0U, // ST4i64 - 0U, // ST4i64_POST - 0U, // ST4i8 - 0U, // ST4i8_POST - 27U, // STLLRB - 27U, // STLLRH - 27U, // STLLRW - 27U, // STLLRX - 27U, // STLRB - 27U, // STLRH - 27U, // STLRW - 27U, // STLRX - 114949U, // STLURBi - 114949U, // STLURHi - 114949U, // STLURWi - 114949U, // STLURXi - 286981U, // STLXPW - 286981U, // STLXPX - 114955U, // STLXRB - 114955U, // STLXRH - 114955U, // STLXRW - 114955U, // STLXRX - 11084043U, // STNPDi - 11608331U, // STNPQi - 12132619U, // STNPSi - 12132619U, // STNPWi - 11084043U, // STNPXi - 256261U, // STNT1B_ZRI - 4357U, // STNT1B_ZRR - 256261U, // STNT1D_ZRI - 4421U, // STNT1D_ZRR - 256261U, // STNT1H_ZRI - 4485U, // STNT1H_ZRR - 256261U, // STNT1W_ZRI - 4741U, // STNT1W_ZRR - 11084043U, // STPDi - 12847371U, // STPDpost - 180431115U, // STPDpre - 11608331U, // STPQi - 13371659U, // STPQpost - 180955403U, // STPQpre - 12132619U, // STPSi - 13895947U, // STPSpost - 181479691U, // STPSpre - 12132619U, // STPWi - 13895947U, // STPWpost - 181479691U, // STPWpre - 11084043U, // STPXi - 12847371U, // STPXpost - 180431115U, // STPXpre - 28U, // STRBBpost - 272645U, // STRBBpre - 14229765U, // STRBBroW - 14754053U, // STRBBroX - 4997U, // STRBBui - 28U, // STRBpost - 272645U, // STRBpre - 14229765U, // STRBroW - 14754053U, // STRBroX - 4997U, // STRBui - 28U, // STRDpost - 272645U, // STRDpre - 15278341U, // STRDroW - 15802629U, // STRDroX - 5061U, // STRDui - 28U, // STRHHpost - 272645U, // STRHHpre - 16326917U, // STRHHroW - 16851205U, // STRHHroX - 5125U, // STRHHui - 28U, // STRHpost - 272645U, // STRHpre - 16326917U, // STRHroW - 16851205U, // STRHroX - 5125U, // STRHui - 28U, // STRQpost - 272645U, // STRQpre - 17375493U, // STRQroW - 17899781U, // STRQroX - 5189U, // STRQui - 28U, // STRSpost - 272645U, // STRSpre - 18424069U, // STRSroW - 18948357U, // STRSroX - 5253U, // STRSui - 28U, // STRWpost - 272645U, // STRWpre - 18424069U, // STRWroW - 18948357U, // STRWroX - 5253U, // STRWui - 28U, // STRXpost - 272645U, // STRXpre - 15278341U, // STRXroW - 15802629U, // STRXroX - 5061U, // STRXui - 254213U, // STR_PXI - 254213U, // STR_ZXI - 114949U, // STTRBi - 114949U, // STTRHi - 114949U, // STTRWi - 114949U, // STTRXi - 114949U, // STURBBi - 114949U, // STURBi - 114949U, // STURDi - 114949U, // STURHHi - 114949U, // STURHi - 114949U, // STURQi - 114949U, // STURSi - 114949U, // STURWi - 114949U, // STURXi - 286981U, // STXPW - 286981U, // STXPX - 114955U, // STXRB - 114955U, // STXRH - 114955U, // STXRW - 114955U, // STXRX - 8517U, // SUBHNv2i64_v2i32 - 8581U, // SUBHNv2i64_v4i32 - 16710U, // SUBHNv4i32_v4i16 - 16774U, // SUBHNv4i32_v8i16 - 24966U, // SUBHNv8i16_v16i8 - 24902U, // SUBHNv8i16_v8i8 - 645U, // SUBR_ZI_B - 709U, // SUBR_ZI_D - 9U, // SUBR_ZI_H - 773U, // SUBR_ZI_S - 74560U, // SUBR_ZPmZ_B - 598912U, // SUBR_ZPmZ_D - 1131465U, // SUBR_ZPmZ_H - 1647616U, // SUBR_ZPmZ_S - 453U, // SUBSWri - 0U, // SUBSWrr - 517U, // SUBSWrs - 581U, // SUBSWrx - 453U, // SUBSXri - 0U, // SUBSXrr - 517U, // SUBSXrs - 581U, // SUBSXrx - 65797U, // SUBSXrx64 - 453U, // SUBWri - 0U, // SUBWrr - 517U, // SUBWrs - 581U, // SUBWrx - 453U, // SUBXri - 0U, // SUBXrr - 517U, // SUBXrs - 581U, // SUBXrx - 65797U, // SUBXrx64 - 645U, // SUB_ZI_B - 709U, // SUB_ZI_D - 9U, // SUB_ZI_H - 773U, // SUB_ZI_S - 74560U, // SUB_ZPmZ_B - 598912U, // SUB_ZPmZ_D - 1131465U, // SUB_ZPmZ_H - 1647616U, // SUB_ZPmZ_S - 837U, // SUB_ZZZ_B - 901U, // SUB_ZZZ_D - 137U, // SUB_ZZZ_H - 1029U, // SUB_ZZZ_S - 33095U, // SUBv16i8 - 261U, // SUBv1i64 - 41287U, // SUBv2i32 - 8517U, // SUBv2i64 - 49480U, // SUBv4i16 - 16710U, // SUBv4i32 - 24902U, // SUBv8i16 - 57672U, // SUBv8i8 - 1U, // SUNPKHI_ZZ_D - 0U, // SUNPKHI_ZZ_H - 1U, // SUNPKHI_ZZ_S - 1U, // SUNPKLO_ZZ_D - 0U, // SUNPKLO_ZZ_H - 1U, // SUNPKLO_ZZ_S - 1U, // SUQADDv16i8 - 1U, // SUQADDv1i16 - 1U, // SUQADDv1i32 - 1U, // SUQADDv1i64 - 1U, // SUQADDv1i8 - 2U, // SUQADDv2i32 - 2U, // SUQADDv2i64 - 3U, // SUQADDv4i16 - 3U, // SUQADDv4i32 - 4U, // SUQADDv8i16 - 4U, // SUQADDv8i8 - 0U, // SVC - 0U, // SWPAB - 0U, // SWPAH - 0U, // SWPALB - 0U, // SWPALH - 0U, // SWPALW - 0U, // SWPALX - 0U, // SWPAW - 0U, // SWPAX - 0U, // SWPB - 0U, // SWPH - 0U, // SWPLB - 0U, // SWPLH - 0U, // SWPLW - 0U, // SWPLX - 0U, // SWPW - 0U, // SWPX - 64U, // SXTB_ZPmZ_D - 128U, // SXTB_ZPmZ_H - 192U, // SXTB_ZPmZ_S - 64U, // SXTH_ZPmZ_D - 192U, // SXTH_ZPmZ_S - 64U, // SXTW_ZPmZ_D - 5445U, // SYSLxt - 0U, // SYSxt - 0U, // TBL_ZZZ_B - 0U, // TBL_ZZZ_D - 0U, // TBL_ZZZ_H - 0U, // TBL_ZZZ_S - 1U, // TBLv16i8Four - 1U, // TBLv16i8One - 1U, // TBLv16i8Three - 1U, // TBLv16i8Two - 4U, // TBLv8i8Four - 4U, // TBLv8i8One - 4U, // TBLv8i8Three - 4U, // TBLv8i8Two - 5509U, // TBNZW - 5509U, // TBNZX - 1U, // TBXv16i8Four - 1U, // TBXv16i8One - 1U, // TBXv16i8Three - 1U, // TBXv16i8Two - 4U, // TBXv8i8Four - 4U, // TBXv8i8One - 4U, // TBXv8i8Three - 4U, // TBXv8i8Two - 5509U, // TBZW - 5509U, // TBZX - 0U, // TCRETURNdi - 0U, // TCRETURNri - 0U, // TLSDESCCALL - 0U, // TLSDESC_CALLSEQ - 837U, // TRN1_PPP_B - 901U, // TRN1_PPP_D - 137U, // TRN1_PPP_H - 1029U, // TRN1_PPP_S - 837U, // TRN1_ZZZ_B - 901U, // TRN1_ZZZ_D - 137U, // TRN1_ZZZ_H - 1029U, // TRN1_ZZZ_S - 33095U, // TRN1v16i8 - 41287U, // TRN1v2i32 - 8517U, // TRN1v2i64 - 49480U, // TRN1v4i16 - 16710U, // TRN1v4i32 - 24902U, // TRN1v8i16 - 57672U, // TRN1v8i8 - 837U, // TRN2_PPP_B - 901U, // TRN2_PPP_D - 137U, // TRN2_PPP_H - 1029U, // TRN2_PPP_S - 837U, // TRN2_ZZZ_B - 901U, // TRN2_ZZZ_D - 137U, // TRN2_ZZZ_H - 1029U, // TRN2_ZZZ_S - 33095U, // TRN2v16i8 - 41287U, // TRN2v2i32 - 8517U, // TRN2v2i64 - 49480U, // TRN2v4i16 - 16710U, // TRN2v4i32 - 24902U, // TRN2v8i16 - 57672U, // TRN2v8i8 - 0U, // TSB - 33159U, // UABALv16i8_v8i16 - 41351U, // UABALv2i32_v2i64 - 49544U, // UABALv4i16_v4i32 - 16774U, // UABALv4i32_v2i64 - 24966U, // UABALv8i16_v4i32 - 57736U, // UABALv8i8_v8i16 - 33159U, // UABAv16i8 - 41351U, // UABAv2i32 - 49544U, // UABAv4i16 - 16774U, // UABAv4i32 - 24966U, // UABAv8i16 - 57736U, // UABAv8i8 - 33095U, // UABDLv16i8_v8i16 - 41287U, // UABDLv2i32_v2i64 - 49480U, // UABDLv4i16_v4i32 - 16710U, // UABDLv4i32_v2i64 - 24902U, // UABDLv8i16_v4i32 - 57672U, // UABDLv8i8_v8i16 - 74560U, // UABD_ZPmZ_B - 598912U, // UABD_ZPmZ_D - 1131465U, // UABD_ZPmZ_H - 1647616U, // UABD_ZPmZ_S - 33095U, // UABDv16i8 - 41287U, // UABDv2i32 - 49480U, // UABDv4i16 - 16710U, // UABDv4i32 - 24902U, // UABDv8i16 - 57672U, // UABDv8i8 - 1U, // UADALPv16i8_v8i16 - 2U, // UADALPv2i32_v1i64 - 3U, // UADALPv4i16_v2i32 - 3U, // UADALPv4i32_v2i64 - 4U, // UADALPv8i16_v4i32 - 4U, // UADALPv8i8_v4i16 - 1U, // UADDLPv16i8_v8i16 - 2U, // UADDLPv2i32_v1i64 - 3U, // UADDLPv4i16_v2i32 - 3U, // UADDLPv4i32_v2i64 - 4U, // UADDLPv8i16_v4i32 - 4U, // UADDLPv8i8_v4i16 - 1U, // UADDLVv16i8v - 3U, // UADDLVv4i16v - 3U, // UADDLVv4i32v - 4U, // UADDLVv8i16v - 4U, // UADDLVv8i8v - 33095U, // UADDLv16i8_v8i16 - 41287U, // UADDLv2i32_v2i64 - 49480U, // UADDLv4i16_v4i32 - 16710U, // UADDLv4i32_v2i64 - 24902U, // UADDLv8i16_v4i32 - 57672U, // UADDLv8i8_v8i16 - 837U, // UADDV_VPZ_B - 901U, // UADDV_VPZ_D - 2245U, // UADDV_VPZ_H - 1029U, // UADDV_VPZ_S - 33094U, // UADDWv16i8_v8i16 - 41285U, // UADDWv2i32_v2i64 - 49478U, // UADDWv4i16_v4i32 - 16709U, // UADDWv4i32_v2i64 - 24902U, // UADDWv8i16_v4i32 - 57670U, // UADDWv8i8_v8i16 - 2171141U, // UBFMWri - 2171141U, // UBFMXri - 261U, // UCVTFSWDri - 261U, // UCVTFSWHri - 261U, // UCVTFSWSri - 261U, // UCVTFSXDri - 261U, // UCVTFSXHri - 261U, // UCVTFSXSri - 1U, // UCVTFUWDri - 1U, // UCVTFUWHri - 1U, // UCVTFUWSri - 1U, // UCVTFUXDri - 1U, // UCVTFUXHri - 1U, // UCVTFUXSri - 64U, // UCVTF_ZPmZ_DtoD - 153U, // UCVTF_ZPmZ_DtoH - 64U, // UCVTF_ZPmZ_DtoS - 128U, // UCVTF_ZPmZ_HtoH - 192U, // UCVTF_ZPmZ_StoD - 152U, // UCVTF_ZPmZ_StoH - 192U, // UCVTF_ZPmZ_StoS - 261U, // UCVTFd - 261U, // UCVTFh - 261U, // UCVTFs - 1U, // UCVTFv1i16 - 1U, // UCVTFv1i32 - 1U, // UCVTFv1i64 - 2U, // UCVTFv2f32 - 2U, // UCVTFv2f64 - 263U, // UCVTFv2i32_shift - 261U, // UCVTFv2i64_shift - 3U, // UCVTFv4f16 - 3U, // UCVTFv4f32 - 264U, // UCVTFv4i16_shift - 262U, // UCVTFv4i32_shift - 4U, // UCVTFv8f16 - 262U, // UCVTFv8i16_shift - 598912U, // UDIVR_ZPmZ_D - 1647616U, // UDIVR_ZPmZ_S - 261U, // UDIVWr - 261U, // UDIVXr - 598912U, // UDIV_ZPmZ_D - 1647616U, // UDIV_ZPmZ_S - 41U, // UDOT_ZZZI_D - 41U, // UDOT_ZZZI_S - 1U, // UDOT_ZZZ_D - 1U, // UDOT_ZZZ_S - 278919U, // UDOTlanev16i8 - 278920U, // UDOTlanev8i8 - 33159U, // UDOTv16i8 - 57736U, // UDOTv8i8 - 33095U, // UHADDv16i8 - 41287U, // UHADDv2i32 - 49480U, // UHADDv4i16 - 16710U, // UHADDv4i32 - 24902U, // UHADDv8i16 - 57672U, // UHADDv8i8 - 33095U, // UHSUBv16i8 - 41287U, // UHSUBv2i32 - 49480U, // UHSUBv4i16 - 16710U, // UHSUBv4i32 - 24902U, // UHSUBv8i16 - 57672U, // UHSUBv8i8 - 2171141U, // UMADDLrrr - 33095U, // UMAXPv16i8 - 41287U, // UMAXPv2i32 - 49480U, // UMAXPv4i16 - 16710U, // UMAXPv4i32 - 24902U, // UMAXPv8i16 - 57672U, // UMAXPv8i8 - 837U, // UMAXV_VPZ_B - 901U, // UMAXV_VPZ_D - 2245U, // UMAXV_VPZ_H - 1029U, // UMAXV_VPZ_S - 1U, // UMAXVv16i8v - 3U, // UMAXVv4i16v - 3U, // UMAXVv4i32v - 4U, // UMAXVv8i16v - 4U, // UMAXVv8i8v - 5573U, // UMAX_ZI_B - 5573U, // UMAX_ZI_D - 45U, // UMAX_ZI_H - 5573U, // UMAX_ZI_S - 74560U, // UMAX_ZPmZ_B - 598912U, // UMAX_ZPmZ_D - 1131465U, // UMAX_ZPmZ_H - 1647616U, // UMAX_ZPmZ_S - 33095U, // UMAXv16i8 - 41287U, // UMAXv2i32 - 49480U, // UMAXv4i16 - 16710U, // UMAXv4i32 - 24902U, // UMAXv8i16 - 57672U, // UMAXv8i8 - 33095U, // UMINPv16i8 - 41287U, // UMINPv2i32 - 49480U, // UMINPv4i16 - 16710U, // UMINPv4i32 - 24902U, // UMINPv8i16 - 57672U, // UMINPv8i8 - 837U, // UMINV_VPZ_B - 901U, // UMINV_VPZ_D - 2245U, // UMINV_VPZ_H - 1029U, // UMINV_VPZ_S - 1U, // UMINVv16i8v - 3U, // UMINVv4i16v - 3U, // UMINVv4i32v - 4U, // UMINVv8i16v - 4U, // UMINVv8i8v - 5573U, // UMIN_ZI_B - 5573U, // UMIN_ZI_D - 45U, // UMIN_ZI_H - 5573U, // UMIN_ZI_S - 74560U, // UMIN_ZPmZ_B - 598912U, // UMIN_ZPmZ_D - 1131465U, // UMIN_ZPmZ_H - 1647616U, // UMIN_ZPmZ_S - 33095U, // UMINv16i8 - 41287U, // UMINv2i32 - 49480U, // UMINv4i16 - 16710U, // UMINv4i32 - 24902U, // UMINv8i16 - 57672U, // UMINv8i8 - 33159U, // UMLALv16i8_v8i16 - 9126279U, // UMLALv2i32_indexed - 41351U, // UMLALv2i32_v2i64 - 9118088U, // UMLALv4i16_indexed - 49544U, // UMLALv4i16_v4i32 - 9126278U, // UMLALv4i32_indexed - 16774U, // UMLALv4i32_v2i64 - 9118086U, // UMLALv8i16_indexed - 24966U, // UMLALv8i16_v4i32 - 57736U, // UMLALv8i8_v8i16 - 33159U, // UMLSLv16i8_v8i16 - 9126279U, // UMLSLv2i32_indexed - 41351U, // UMLSLv2i32_v2i64 - 9118088U, // UMLSLv4i16_indexed - 49544U, // UMLSLv4i16_v4i32 - 9126278U, // UMLSLv4i32_indexed - 16774U, // UMLSLv4i32_v2i64 - 9118086U, // UMLSLv8i16_indexed - 24966U, // UMLSLv8i16_v4i32 - 57736U, // UMLSLv8i8_v8i16 - 2770U, // UMOVvi16 - 2770U, // UMOVvi32 - 2771U, // UMOVvi64 - 2771U, // UMOVvi8 - 2171141U, // UMSUBLrrr - 74560U, // UMULH_ZPmZ_B - 598912U, // UMULH_ZPmZ_D - 1131465U, // UMULH_ZPmZ_H - 1647616U, // UMULH_ZPmZ_S - 261U, // UMULHrr - 33095U, // UMULLv16i8_v8i16 - 10174791U, // UMULLv2i32_indexed - 41287U, // UMULLv2i32_v2i64 - 10166600U, // UMULLv4i16_indexed - 49480U, // UMULLv4i16_v4i32 - 10174790U, // UMULLv4i32_indexed - 16710U, // UMULLv4i32_v2i64 - 10166598U, // UMULLv8i16_indexed - 24902U, // UMULLv8i16_v4i32 - 57672U, // UMULLv8i8_v8i16 - 645U, // UQADD_ZI_B - 709U, // UQADD_ZI_D - 9U, // UQADD_ZI_H - 773U, // UQADD_ZI_S - 837U, // UQADD_ZZZ_B - 901U, // UQADD_ZZZ_D - 137U, // UQADD_ZZZ_H - 1029U, // UQADD_ZZZ_S - 33095U, // UQADDv16i8 - 261U, // UQADDv1i16 - 261U, // UQADDv1i32 - 261U, // UQADDv1i64 - 261U, // UQADDv1i8 - 41287U, // UQADDv2i32 - 8517U, // UQADDv2i64 - 49480U, // UQADDv4i16 - 16710U, // UQADDv4i32 - 24902U, // UQADDv8i16 - 57672U, // UQADDv8i8 - 0U, // UQDECB_WPiI - 0U, // UQDECB_XPiI - 0U, // UQDECD_WPiI - 0U, // UQDECD_XPiI - 0U, // UQDECD_ZPiI - 0U, // UQDECH_WPiI - 0U, // UQDECH_XPiI - 0U, // UQDECH_ZPiI - 1U, // UQDECP_WP_B - 1U, // UQDECP_WP_D - 1U, // UQDECP_WP_H - 1U, // UQDECP_WP_S - 1U, // UQDECP_XP_B - 1U, // UQDECP_XP_D - 1U, // UQDECP_XP_H - 1U, // UQDECP_XP_S - 1U, // UQDECP_ZP_D - 0U, // UQDECP_ZP_H - 1U, // UQDECP_ZP_S - 0U, // UQDECW_WPiI - 0U, // UQDECW_XPiI - 0U, // UQDECW_ZPiI - 0U, // UQINCB_WPiI - 0U, // UQINCB_XPiI - 0U, // UQINCD_WPiI - 0U, // UQINCD_XPiI - 0U, // UQINCD_ZPiI - 0U, // UQINCH_WPiI - 0U, // UQINCH_XPiI - 0U, // UQINCH_ZPiI - 1U, // UQINCP_WP_B - 1U, // UQINCP_WP_D - 1U, // UQINCP_WP_H - 1U, // UQINCP_WP_S - 1U, // UQINCP_XP_B - 1U, // UQINCP_XP_D - 1U, // UQINCP_XP_H - 1U, // UQINCP_XP_S - 1U, // UQINCP_ZP_D - 0U, // UQINCP_ZP_H - 1U, // UQINCP_ZP_S - 0U, // UQINCW_WPiI - 0U, // UQINCW_XPiI - 0U, // UQINCW_ZPiI - 33095U, // UQRSHLv16i8 - 261U, // UQRSHLv1i16 - 261U, // UQRSHLv1i32 - 261U, // UQRSHLv1i64 - 261U, // UQRSHLv1i8 - 41287U, // UQRSHLv2i32 - 8517U, // UQRSHLv2i64 - 49480U, // UQRSHLv4i16 - 16710U, // UQRSHLv4i32 - 24902U, // UQRSHLv8i16 - 57672U, // UQRSHLv8i8 - 261U, // UQRSHRNb - 261U, // UQRSHRNh - 261U, // UQRSHRNs - 2310U, // UQRSHRNv16i8_shift - 261U, // UQRSHRNv2i32_shift - 262U, // UQRSHRNv4i16_shift - 2309U, // UQRSHRNv4i32_shift - 2310U, // UQRSHRNv8i16_shift - 262U, // UQRSHRNv8i8_shift - 261U, // UQSHLb - 261U, // UQSHLd - 261U, // UQSHLh - 261U, // UQSHLs - 33095U, // UQSHLv16i8 - 263U, // UQSHLv16i8_shift - 261U, // UQSHLv1i16 - 261U, // UQSHLv1i32 - 261U, // UQSHLv1i64 - 261U, // UQSHLv1i8 - 41287U, // UQSHLv2i32 - 263U, // UQSHLv2i32_shift - 8517U, // UQSHLv2i64 - 261U, // UQSHLv2i64_shift - 49480U, // UQSHLv4i16 - 264U, // UQSHLv4i16_shift - 16710U, // UQSHLv4i32 - 262U, // UQSHLv4i32_shift - 24902U, // UQSHLv8i16 - 262U, // UQSHLv8i16_shift - 57672U, // UQSHLv8i8 - 264U, // UQSHLv8i8_shift - 261U, // UQSHRNb - 261U, // UQSHRNh - 261U, // UQSHRNs - 2310U, // UQSHRNv16i8_shift - 261U, // UQSHRNv2i32_shift - 262U, // UQSHRNv4i16_shift - 2309U, // UQSHRNv4i32_shift - 2310U, // UQSHRNv8i16_shift - 262U, // UQSHRNv8i8_shift - 645U, // UQSUB_ZI_B - 709U, // UQSUB_ZI_D - 9U, // UQSUB_ZI_H - 773U, // UQSUB_ZI_S - 837U, // UQSUB_ZZZ_B - 901U, // UQSUB_ZZZ_D - 137U, // UQSUB_ZZZ_H - 1029U, // UQSUB_ZZZ_S - 33095U, // UQSUBv16i8 - 261U, // UQSUBv1i16 - 261U, // UQSUBv1i32 - 261U, // UQSUBv1i64 - 261U, // UQSUBv1i8 - 41287U, // UQSUBv2i32 - 8517U, // UQSUBv2i64 - 49480U, // UQSUBv4i16 - 16710U, // UQSUBv4i32 - 24902U, // UQSUBv8i16 - 57672U, // UQSUBv8i8 - 4U, // UQXTNv16i8 - 1U, // UQXTNv1i16 - 1U, // UQXTNv1i32 - 1U, // UQXTNv1i8 - 2U, // UQXTNv2i32 - 3U, // UQXTNv4i16 - 2U, // UQXTNv4i32 - 3U, // UQXTNv8i16 - 4U, // UQXTNv8i8 - 2U, // URECPEv2i32 - 3U, // URECPEv4i32 - 33095U, // URHADDv16i8 - 41287U, // URHADDv2i32 - 49480U, // URHADDv4i16 - 16710U, // URHADDv4i32 - 24902U, // URHADDv8i16 - 57672U, // URHADDv8i8 - 33095U, // URSHLv16i8 - 261U, // URSHLv1i64 - 41287U, // URSHLv2i32 - 8517U, // URSHLv2i64 - 49480U, // URSHLv4i16 - 16710U, // URSHLv4i32 - 24902U, // URSHLv8i16 - 57672U, // URSHLv8i8 - 261U, // URSHRd - 263U, // URSHRv16i8_shift - 263U, // URSHRv2i32_shift - 261U, // URSHRv2i64_shift - 264U, // URSHRv4i16_shift - 262U, // URSHRv4i32_shift - 262U, // URSHRv8i16_shift - 264U, // URSHRv8i8_shift - 2U, // URSQRTEv2i32 - 3U, // URSQRTEv4i32 - 2309U, // URSRAd - 2311U, // URSRAv16i8_shift - 2311U, // URSRAv2i32_shift - 2309U, // URSRAv2i64_shift - 2312U, // URSRAv4i16_shift - 2310U, // URSRAv4i32_shift - 2310U, // URSRAv8i16_shift - 2312U, // URSRAv8i8_shift - 263U, // USHLLv16i8_shift - 263U, // USHLLv2i32_shift - 264U, // USHLLv4i16_shift - 262U, // USHLLv4i32_shift - 262U, // USHLLv8i16_shift - 264U, // USHLLv8i8_shift - 33095U, // USHLv16i8 - 261U, // USHLv1i64 - 41287U, // USHLv2i32 - 8517U, // USHLv2i64 - 49480U, // USHLv4i16 - 16710U, // USHLv4i32 - 24902U, // USHLv8i16 - 57672U, // USHLv8i8 - 261U, // USHRd - 263U, // USHRv16i8_shift - 263U, // USHRv2i32_shift - 261U, // USHRv2i64_shift - 264U, // USHRv4i16_shift - 262U, // USHRv4i32_shift - 262U, // USHRv8i16_shift - 264U, // USHRv8i8_shift - 1U, // USQADDv16i8 - 1U, // USQADDv1i16 - 1U, // USQADDv1i32 - 1U, // USQADDv1i64 - 1U, // USQADDv1i8 - 2U, // USQADDv2i32 - 2U, // USQADDv2i64 - 3U, // USQADDv4i16 - 3U, // USQADDv4i32 - 4U, // USQADDv8i16 - 4U, // USQADDv8i8 - 2309U, // USRAd - 2311U, // USRAv16i8_shift - 2311U, // USRAv2i32_shift - 2309U, // USRAv2i64_shift - 2312U, // USRAv4i16_shift - 2310U, // USRAv4i32_shift - 2310U, // USRAv8i16_shift - 2312U, // USRAv8i8_shift - 33095U, // USUBLv16i8_v8i16 - 41287U, // USUBLv2i32_v2i64 - 49480U, // USUBLv4i16_v4i32 - 16710U, // USUBLv4i32_v2i64 - 24902U, // USUBLv8i16_v4i32 - 57672U, // USUBLv8i8_v8i16 - 33094U, // USUBWv16i8_v8i16 - 41285U, // USUBWv2i32_v2i64 - 49478U, // USUBWv4i16_v4i32 - 16709U, // USUBWv4i32_v2i64 - 24902U, // USUBWv8i16_v4i32 - 57670U, // USUBWv8i8_v8i16 - 1U, // UUNPKHI_ZZ_D - 0U, // UUNPKHI_ZZ_H - 1U, // UUNPKHI_ZZ_S - 1U, // UUNPKLO_ZZ_D - 0U, // UUNPKLO_ZZ_H - 1U, // UUNPKLO_ZZ_S - 64U, // UXTB_ZPmZ_D - 128U, // UXTB_ZPmZ_H - 192U, // UXTB_ZPmZ_S - 64U, // UXTH_ZPmZ_D - 192U, // UXTH_ZPmZ_S - 64U, // UXTW_ZPmZ_D - 837U, // UZP1_PPP_B - 901U, // UZP1_PPP_D - 137U, // UZP1_PPP_H - 1029U, // UZP1_PPP_S - 837U, // UZP1_ZZZ_B - 901U, // UZP1_ZZZ_D - 137U, // UZP1_ZZZ_H - 1029U, // UZP1_ZZZ_S - 33095U, // UZP1v16i8 - 41287U, // UZP1v2i32 - 8517U, // UZP1v2i64 - 49480U, // UZP1v4i16 - 16710U, // UZP1v4i32 - 24902U, // UZP1v8i16 - 57672U, // UZP1v8i8 - 837U, // UZP2_PPP_B - 901U, // UZP2_PPP_D - 137U, // UZP2_PPP_H - 1029U, // UZP2_PPP_S - 837U, // UZP2_ZZZ_B - 901U, // UZP2_ZZZ_D - 137U, // UZP2_ZZZ_H - 1029U, // UZP2_ZZZ_S - 33095U, // UZP2v16i8 - 41287U, // UZP2v2i32 - 8517U, // UZP2v2i64 - 49480U, // UZP2v4i16 - 16710U, // UZP2v4i32 - 24902U, // UZP2v8i16 - 57672U, // UZP2v8i8 - 261U, // WHILELE_PWW_B - 261U, // WHILELE_PWW_D - 11U, // WHILELE_PWW_H - 261U, // WHILELE_PWW_S - 261U, // WHILELE_PXX_B - 261U, // WHILELE_PXX_D - 11U, // WHILELE_PXX_H - 261U, // WHILELE_PXX_S - 261U, // WHILELO_PWW_B - 261U, // WHILELO_PWW_D - 11U, // WHILELO_PWW_H - 261U, // WHILELO_PWW_S - 261U, // WHILELO_PXX_B - 261U, // WHILELO_PXX_D - 11U, // WHILELO_PXX_H - 261U, // WHILELO_PXX_S - 261U, // WHILELS_PWW_B - 261U, // WHILELS_PWW_D - 11U, // WHILELS_PWW_H - 261U, // WHILELS_PWW_S - 261U, // WHILELS_PXX_B - 261U, // WHILELS_PXX_D - 11U, // WHILELS_PXX_H - 261U, // WHILELS_PXX_S - 261U, // WHILELT_PWW_B - 261U, // WHILELT_PWW_D - 11U, // WHILELT_PWW_H - 261U, // WHILELT_PWW_S - 261U, // WHILELT_PXX_B - 261U, // WHILELT_PXX_D - 11U, // WHILELT_PXX_H - 261U, // WHILELT_PXX_S - 0U, // WRFFR - 2253125U, // XAR - 0U, // XPACD - 0U, // XPACI - 0U, // XPACLRI - 4U, // XTNv16i8 - 2U, // XTNv2i32 - 3U, // XTNv4i16 - 2U, // XTNv4i32 - 3U, // XTNv8i16 - 4U, // XTNv8i8 - 837U, // ZIP1_PPP_B - 901U, // ZIP1_PPP_D - 137U, // ZIP1_PPP_H - 1029U, // ZIP1_PPP_S - 837U, // ZIP1_ZZZ_B - 901U, // ZIP1_ZZZ_D - 137U, // ZIP1_ZZZ_H - 1029U, // ZIP1_ZZZ_S - 33095U, // ZIP1v16i8 - 41287U, // ZIP1v2i32 - 8517U, // ZIP1v2i64 - 49480U, // ZIP1v4i16 - 16710U, // ZIP1v4i32 - 24902U, // ZIP1v8i16 - 57672U, // ZIP1v8i8 - 837U, // ZIP2_PPP_B - 901U, // ZIP2_PPP_D - 137U, // ZIP2_PPP_H - 1029U, // ZIP2_PPP_S - 837U, // ZIP2_ZZZ_B - 901U, // ZIP2_ZZZ_D - 137U, // ZIP2_ZZZ_H - 1029U, // ZIP2_ZZZ_S - 33095U, // ZIP2v16i8 - 41287U, // ZIP2v2i32 - 8517U, // ZIP2v2i64 - 49480U, // ZIP2v4i16 - 16710U, // ZIP2v4i32 - 24902U, // ZIP2v8i16 - 57672U, // ZIP2v8i8 - 837U, // anonymous_1349 + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // ABS_ZPmZ_B + 64U, // ABS_ZPmZ_D + 128U, // ABS_ZPmZ_H + 192U, // ABS_ZPmZ_S + 1U, // ABSv16i8 + 1U, // ABSv1i64 + 2U, // ABSv2i32 + 2U, // ABSv2i64 + 3U, // ABSv4i16 + 3U, // ABSv4i32 + 4U, // ABSv8i16 + 4U, // ABSv8i8 + 261U, // ADCSWr + 261U, // ADCSXr + 261U, // ADCWr + 261U, // ADCXr + 8517U, // ADDHNv2i64_v2i32 + 8581U, // ADDHNv2i64_v4i32 + 16710U, // ADDHNv4i32_v4i16 + 16774U, // ADDHNv4i32_v8i16 + 24966U, // ADDHNv8i16_v16i8 + 24902U, // ADDHNv8i16_v8i8 + 261U, // ADDPL_XXI + 33095U, // ADDPv16i8 + 41287U, // ADDPv2i32 + 8517U, // ADDPv2i64 + 2U, // ADDPv2i64p + 49480U, // ADDPv4i16 + 16710U, // ADDPv4i32 + 24902U, // ADDPv8i16 + 57672U, // ADDPv8i8 + 453U, // ADDSWri + 0U, // ADDSWrr + 517U, // ADDSWrs + 581U, // ADDSWrx + 453U, // ADDSXri + 0U, // ADDSXrr + 517U, // ADDSXrs + 581U, // ADDSXrx + 65797U, // ADDSXrx64 + 261U, // ADDVL_XXI + 1U, // ADDVv16i8v + 3U, // ADDVv4i16v + 3U, // ADDVv4i32v + 4U, // ADDVv8i16v + 4U, // ADDVv8i8v + 453U, // ADDWri + 0U, // ADDWrr + 517U, // ADDWrs + 581U, // ADDWrx + 453U, // ADDXri + 0U, // ADDXrr + 517U, // ADDXrs + 581U, // ADDXrx + 65797U, // ADDXrx64 + 645U, // ADD_ZI_B + 709U, // ADD_ZI_D + 9U, // ADD_ZI_H + 773U, // ADD_ZI_S + 74560U, // ADD_ZPmZ_B + 598912U, // ADD_ZPmZ_D + 1131465U, // ADD_ZPmZ_H + 1647616U, // ADD_ZPmZ_S + 837U, // ADD_ZZZ_B + 901U, // ADD_ZZZ_D + 137U, // ADD_ZZZ_H + 1029U, // ADD_ZZZ_S + 0U, // ADDlowTLS + 33095U, // ADDv16i8 + 261U, // ADDv1i64 + 41287U, // ADDv2i32 + 8517U, // ADDv2i64 + 49480U, // ADDv4i16 + 16710U, // ADDv4i32 + 24902U, // ADDv8i16 + 57672U, // ADDv8i8 + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 1U, // ADR + 0U, // ADRP + 1093U, // ADR_LSL_ZZZ_D_0 + 1157U, // ADR_LSL_ZZZ_D_1 + 1221U, // ADR_LSL_ZZZ_D_2 + 1285U, // ADR_LSL_ZZZ_D_3 + 1349U, // ADR_LSL_ZZZ_S_0 + 1413U, // ADR_LSL_ZZZ_S_1 + 1477U, // ADR_LSL_ZZZ_S_2 + 1541U, // ADR_LSL_ZZZ_S_3 + 1605U, // ADR_SXTW_ZZZ_D_0 + 1669U, // ADR_SXTW_ZZZ_D_1 + 1733U, // ADR_SXTW_ZZZ_D_2 + 1797U, // ADR_SXTW_ZZZ_D_3 + 1861U, // ADR_UXTW_ZZZ_D_0 + 1925U, // ADR_UXTW_ZZZ_D_1 + 1989U, // ADR_UXTW_ZZZ_D_2 + 2053U, // ADR_UXTW_ZZZ_D_3 + 1U, // AESDrr + 1U, // AESErr + 1U, // AESIMCrr + 0U, // AESIMCrrTied + 1U, // AESMCrr + 0U, // AESMCrrTied + 2117U, // ANDSWri + 0U, // ANDSWrr + 517U, // ANDSWrs + 2181U, // ANDSXri + 0U, // ANDSXrr + 517U, // ANDSXrs + 74570U, // ANDS_PPzPP + 837U, // ANDV_VPZ_B + 901U, // ANDV_VPZ_D + 2245U, // ANDV_VPZ_H + 1029U, // ANDV_VPZ_S + 2117U, // ANDWri + 0U, // ANDWrr + 517U, // ANDWrs + 2181U, // ANDXri + 0U, // ANDXrr + 517U, // ANDXrs + 74570U, // AND_PPzPP + 2181U, // AND_ZI + 74560U, // AND_ZPmZ_B + 598912U, // AND_ZPmZ_D + 1131465U, // AND_ZPmZ_H + 1647616U, // AND_ZPmZ_S + 901U, // AND_ZZZ + 33095U, // ANDv16i8 + 57672U, // ANDv8i8 + 2171712U, // ASRD_ZPmI_B + 2171776U, // ASRD_ZPmI_D + 91081U, // ASRD_ZPmI_H + 2171904U, // ASRD_ZPmI_S + 74560U, // ASRR_ZPmZ_B + 598912U, // ASRR_ZPmZ_D + 1131465U, // ASRR_ZPmZ_H + 1647616U, // ASRR_ZPmZ_S + 261U, // ASRVWr + 261U, // ASRVXr + 598848U, // ASR_WIDE_ZPmZ_B + 99273U, // ASR_WIDE_ZPmZ_H + 599040U, // ASR_WIDE_ZPmZ_S + 901U, // ASR_WIDE_ZZZ_B + 10U, // ASR_WIDE_ZZZ_H + 901U, // ASR_WIDE_ZZZ_S + 2171712U, // ASR_ZPmI_B + 2171776U, // ASR_ZPmI_D + 91081U, // ASR_ZPmI_H + 2171904U, // ASR_ZPmI_S + 74560U, // ASR_ZPmZ_B + 598912U, // ASR_ZPmZ_D + 1131465U, // ASR_ZPmZ_H + 1647616U, // ASR_ZPmZ_S + 261U, // ASR_ZZI_B + 261U, // ASR_ZZI_D + 11U, // ASR_ZZI_H + 261U, // ASR_ZZI_S + 1U, // AUTDA + 1U, // AUTDB + 0U, // AUTDZA + 0U, // AUTDZB + 1U, // AUTIA + 0U, // AUTIA1716 + 0U, // AUTIASP + 0U, // AUTIAZ + 1U, // AUTIB + 0U, // AUTIB1716 + 0U, // AUTIBSP + 0U, // AUTIBZ + 0U, // AUTIZA + 0U, // AUTIZB + 0U, // B + 36282695U, // BCAX + 3221765U, // BFMWri + 3221765U, // BFMXri + 0U, // BICSWrr + 517U, // BICSWrs + 0U, // BICSXrr + 517U, // BICSXrs + 74570U, // BICS_PPzPP + 0U, // BICWrr + 517U, // BICWrs + 0U, // BICXrr + 517U, // BICXrs + 74570U, // BIC_PPzPP + 74560U, // BIC_ZPmZ_B + 598912U, // BIC_ZPmZ_D + 1131465U, // BIC_ZPmZ_H + 1647616U, // BIC_ZPmZ_S + 901U, // BIC_ZZZ + 33095U, // BICv16i8 + 0U, // BICv2i32 + 0U, // BICv4i16 + 0U, // BICv4i32 + 0U, // BICv8i16 + 57672U, // BICv8i8 + 33095U, // BIFv16i8 + 57672U, // BIFv8i8 + 33159U, // BITv16i8 + 57736U, // BITv8i8 + 0U, // BL + 0U, // BLR + 1U, // BLRAA + 0U, // BLRAAZ + 1U, // BLRAB + 0U, // BLRABZ + 0U, // BR + 1U, // BRAA + 0U, // BRAAZ + 1U, // BRAB + 0U, // BRABZ + 0U, // BRK + 842U, // BRKAS_PPzP + 0U, // BRKA_PPmP + 842U, // BRKA_PPzP + 842U, // BRKBS_PPzP + 0U, // BRKB_PPmP + 842U, // BRKB_PPzP + 74570U, // BRKNS_PPzP + 74570U, // BRKN_PPzP + 74570U, // BRKPAS_PPzPP + 74570U, // BRKPA_PPzPP + 74570U, // BRKPBS_PPzPP + 74570U, // BRKPB_PPzPP + 33159U, // BSLv16i8 + 57736U, // BSLv8i8 + 0U, // Bcc + 117003U, // CASAB + 117003U, // CASAH + 117003U, // CASALB + 117003U, // CASALH + 117003U, // CASALW + 117003U, // CASALX + 117003U, // CASAW + 117003U, // CASAX + 117003U, // CASB + 117003U, // CASH + 117003U, // CASLB + 117003U, // CASLH + 117003U, // CASLW + 117003U, // CASLX + 0U, // CASPALW + 0U, // CASPALX + 0U, // CASPAW + 0U, // CASPAX + 0U, // CASPLW + 0U, // CASPLX + 0U, // CASPW + 0U, // CASPX + 117003U, // CASW + 117003U, // CASX + 0U, // CBNZW + 0U, // CBNZX + 0U, // CBZW + 0U, // CBZX + 3744005U, // CCMNWi + 3744005U, // CCMNWr + 3744005U, // CCMNXi + 3744005U, // CCMNXr + 3744005U, // CCMPWi + 3744005U, // CCMPWr + 3744005U, // CCMPXi + 3744005U, // CCMPXr + 0U, // CFINV + 73989U, // CLASTA_RPZ_B + 598277U, // CLASTA_RPZ_D + 4268293U, // CLASTA_RPZ_H + 1646853U, // CLASTA_RPZ_S + 73989U, // CLASTA_VPZ_B + 598277U, // CLASTA_VPZ_D + 4268293U, // CLASTA_VPZ_H + 1646853U, // CLASTA_VPZ_S + 74565U, // CLASTA_ZPZ_B + 598917U, // CLASTA_ZPZ_D + 1131465U, // CLASTA_ZPZ_H + 1647621U, // CLASTA_ZPZ_S + 73989U, // CLASTB_RPZ_B + 598277U, // CLASTB_RPZ_D + 4268293U, // CLASTB_RPZ_H + 1646853U, // CLASTB_RPZ_S + 73989U, // CLASTB_VPZ_B + 598277U, // CLASTB_VPZ_D + 4268293U, // CLASTB_VPZ_H + 1646853U, // CLASTB_VPZ_S + 74565U, // CLASTB_ZPZ_B + 598917U, // CLASTB_ZPZ_D + 1131465U, // CLASTB_ZPZ_H + 1647621U, // CLASTB_ZPZ_S + 0U, // CLREX + 1U, // CLSWr + 1U, // CLSXr + 0U, // CLS_ZPmZ_B + 64U, // CLS_ZPmZ_D + 128U, // CLS_ZPmZ_H + 192U, // CLS_ZPmZ_S + 1U, // CLSv16i8 + 2U, // CLSv2i32 + 3U, // CLSv4i16 + 3U, // CLSv4i32 + 4U, // CLSv8i16 + 4U, // CLSv8i8 + 1U, // CLZWr + 1U, // CLZXr + 0U, // CLZ_ZPmZ_B + 64U, // CLZ_ZPmZ_D + 128U, // CLZ_ZPmZ_H + 192U, // CLZ_ZPmZ_S + 1U, // CLZv16i8 + 2U, // CLZv2i32 + 3U, // CLZv4i16 + 3U, // CLZv4i32 + 4U, // CLZv8i16 + 4U, // CLZv8i8 + 33095U, // CMEQv16i8 + 12U, // CMEQv16i8rz + 261U, // CMEQv1i64 + 12U, // CMEQv1i64rz + 41287U, // CMEQv2i32 + 13U, // CMEQv2i32rz + 8517U, // CMEQv2i64 + 13U, // CMEQv2i64rz + 49480U, // CMEQv4i16 + 14U, // CMEQv4i16rz + 16710U, // CMEQv4i32 + 14U, // CMEQv4i32rz + 24902U, // CMEQv8i16 + 15U, // CMEQv8i16rz + 57672U, // CMEQv8i8 + 15U, // CMEQv8i8rz + 33095U, // CMGEv16i8 + 12U, // CMGEv16i8rz + 261U, // CMGEv1i64 + 12U, // CMGEv1i64rz + 41287U, // CMGEv2i32 + 13U, // CMGEv2i32rz + 8517U, // CMGEv2i64 + 13U, // CMGEv2i64rz + 49480U, // CMGEv4i16 + 14U, // CMGEv4i16rz + 16710U, // CMGEv4i32 + 14U, // CMGEv4i32rz + 24902U, // CMGEv8i16 + 15U, // CMGEv8i16rz + 57672U, // CMGEv8i8 + 15U, // CMGEv8i8rz + 33095U, // CMGTv16i8 + 12U, // CMGTv16i8rz + 261U, // CMGTv1i64 + 12U, // CMGTv1i64rz + 41287U, // CMGTv2i32 + 13U, // CMGTv2i32rz + 8517U, // CMGTv2i64 + 13U, // CMGTv2i64rz + 49480U, // CMGTv4i16 + 14U, // CMGTv4i16rz + 16710U, // CMGTv4i32 + 14U, // CMGTv4i32rz + 24902U, // CMGTv8i16 + 15U, // CMGTv8i16rz + 57672U, // CMGTv8i8 + 15U, // CMGTv8i8rz + 33095U, // CMHIv16i8 + 261U, // CMHIv1i64 + 41287U, // CMHIv2i32 + 8517U, // CMHIv2i64 + 49480U, // CMHIv4i16 + 16710U, // CMHIv4i32 + 24902U, // CMHIv8i16 + 57672U, // CMHIv8i8 + 33095U, // CMHSv16i8 + 261U, // CMHSv1i64 + 41287U, // CMHSv2i32 + 8517U, // CMHSv2i64 + 49480U, // CMHSv4i16 + 16710U, // CMHSv4i32 + 24902U, // CMHSv8i16 + 57672U, // CMHSv8i8 + 12U, // CMLEv16i8rz + 12U, // CMLEv1i64rz + 13U, // CMLEv2i32rz + 13U, // CMLEv2i64rz + 14U, // CMLEv4i16rz + 14U, // CMLEv4i32rz + 15U, // CMLEv8i16rz + 15U, // CMLEv8i8rz + 12U, // CMLTv16i8rz + 12U, // CMLTv1i64rz + 13U, // CMLTv2i32rz + 13U, // CMLTv2i64rz + 14U, // CMLTv4i16rz + 14U, // CMLTv4i32rz + 15U, // CMLTv8i16rz + 15U, // CMLTv8i8rz + 2171722U, // CMPEQ_PPzZI_B + 2171786U, // CMPEQ_PPzZI_D + 91081U, // CMPEQ_PPzZI_H + 2171914U, // CMPEQ_PPzZI_S + 74570U, // CMPEQ_PPzZZ_B + 598922U, // CMPEQ_PPzZZ_D + 1131465U, // CMPEQ_PPzZZ_H + 1647626U, // CMPEQ_PPzZZ_S + 598858U, // CMPEQ_WIDE_PPzZZ_B + 99273U, // CMPEQ_WIDE_PPzZZ_H + 599050U, // CMPEQ_WIDE_PPzZZ_S + 2171722U, // CMPGE_PPzZI_B + 2171786U, // CMPGE_PPzZI_D + 91081U, // CMPGE_PPzZI_H + 2171914U, // CMPGE_PPzZI_S + 74570U, // CMPGE_PPzZZ_B + 598922U, // CMPGE_PPzZZ_D + 1131465U, // CMPGE_PPzZZ_H + 1647626U, // CMPGE_PPzZZ_S + 598858U, // CMPGE_WIDE_PPzZZ_B + 99273U, // CMPGE_WIDE_PPzZZ_H + 599050U, // CMPGE_WIDE_PPzZZ_S + 2171722U, // CMPGT_PPzZI_B + 2171786U, // CMPGT_PPzZI_D + 91081U, // CMPGT_PPzZI_H + 2171914U, // CMPGT_PPzZI_S + 74570U, // CMPGT_PPzZZ_B + 598922U, // CMPGT_PPzZZ_D + 1131465U, // CMPGT_PPzZZ_H + 1647626U, // CMPGT_PPzZZ_S + 598858U, // CMPGT_WIDE_PPzZZ_B + 99273U, // CMPGT_WIDE_PPzZZ_H + 599050U, // CMPGT_WIDE_PPzZZ_S + 4793162U, // CMPHI_PPzZI_B + 4793226U, // CMPHI_PPzZI_D + 123849U, // CMPHI_PPzZI_H + 4793354U, // CMPHI_PPzZI_S + 74570U, // CMPHI_PPzZZ_B + 598922U, // CMPHI_PPzZZ_D + 1131465U, // CMPHI_PPzZZ_H + 1647626U, // CMPHI_PPzZZ_S + 598858U, // CMPHI_WIDE_PPzZZ_B + 99273U, // CMPHI_WIDE_PPzZZ_H + 599050U, // CMPHI_WIDE_PPzZZ_S + 4793162U, // CMPHS_PPzZI_B + 4793226U, // CMPHS_PPzZI_D + 123849U, // CMPHS_PPzZI_H + 4793354U, // CMPHS_PPzZI_S + 74570U, // CMPHS_PPzZZ_B + 598922U, // CMPHS_PPzZZ_D + 1131465U, // CMPHS_PPzZZ_H + 1647626U, // CMPHS_PPzZZ_S + 598858U, // CMPHS_WIDE_PPzZZ_B + 99273U, // CMPHS_WIDE_PPzZZ_H + 599050U, // CMPHS_WIDE_PPzZZ_S + 2171722U, // CMPLE_PPzZI_B + 2171786U, // CMPLE_PPzZI_D + 91081U, // CMPLE_PPzZI_H + 2171914U, // CMPLE_PPzZI_S + 598858U, // CMPLE_WIDE_PPzZZ_B + 99273U, // CMPLE_WIDE_PPzZZ_H + 599050U, // CMPLE_WIDE_PPzZZ_S + 4793162U, // CMPLO_PPzZI_B + 4793226U, // CMPLO_PPzZI_D + 123849U, // CMPLO_PPzZI_H + 4793354U, // CMPLO_PPzZI_S + 598858U, // CMPLO_WIDE_PPzZZ_B + 99273U, // CMPLO_WIDE_PPzZZ_H + 599050U, // CMPLO_WIDE_PPzZZ_S + 4793162U, // CMPLS_PPzZI_B + 4793226U, // CMPLS_PPzZI_D + 123849U, // CMPLS_PPzZI_H + 4793354U, // CMPLS_PPzZI_S + 598858U, // CMPLS_WIDE_PPzZZ_B + 99273U, // CMPLS_WIDE_PPzZZ_H + 599050U, // CMPLS_WIDE_PPzZZ_S + 2171722U, // CMPLT_PPzZI_B + 2171786U, // CMPLT_PPzZI_D + 91081U, // CMPLT_PPzZI_H + 2171914U, // CMPLT_PPzZI_S + 598858U, // CMPLT_WIDE_PPzZZ_B + 99273U, // CMPLT_WIDE_PPzZZ_H + 599050U, // CMPLT_WIDE_PPzZZ_S + 2171722U, // CMPNE_PPzZI_B + 2171786U, // CMPNE_PPzZI_D + 91081U, // CMPNE_PPzZI_H + 2171914U, // CMPNE_PPzZI_S + 74570U, // CMPNE_PPzZZ_B + 598922U, // CMPNE_PPzZZ_D + 1131465U, // CMPNE_PPzZZ_H + 1647626U, // CMPNE_PPzZZ_S + 598858U, // CMPNE_WIDE_PPzZZ_B + 99273U, // CMPNE_WIDE_PPzZZ_H + 599050U, // CMPNE_WIDE_PPzZZ_S + 0U, // CMP_SWAP_128 + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 33095U, // CMTSTv16i8 + 261U, // CMTSTv1i64 + 41287U, // CMTSTv2i32 + 8517U, // CMTSTv2i64 + 49480U, // CMTSTv4i16 + 16710U, // CMTSTv4i32 + 24902U, // CMTSTv8i16 + 57672U, // CMTSTv8i8 + 0U, // CNOT_ZPmZ_B + 64U, // CNOT_ZPmZ_D + 128U, // CNOT_ZPmZ_H + 192U, // CNOT_ZPmZ_S + 16U, // CNTB_XPiI + 16U, // CNTD_XPiI + 16U, // CNTH_XPiI + 837U, // CNTP_XPP_B + 901U, // CNTP_XPP_D + 2245U, // CNTP_XPP_H + 1029U, // CNTP_XPP_S + 16U, // CNTW_XPiI + 0U, // CNT_ZPmZ_B + 64U, // CNT_ZPmZ_D + 128U, // CNT_ZPmZ_H + 192U, // CNT_ZPmZ_S + 1U, // CNTv16i8 + 4U, // CNTv8i8 + 901U, // COMPACT_ZPZ_D + 1029U, // COMPACT_ZPZ_S + 2368U, // CPY_ZPmI_B + 2432U, // CPY_ZPmI_D + 16U, // CPY_ZPmI_H + 2496U, // CPY_ZPmI_S + 2304U, // CPY_ZPmR_B + 2304U, // CPY_ZPmR_D + 145U, // CPY_ZPmR_H + 2304U, // CPY_ZPmR_S + 2304U, // CPY_ZPmV_B + 2304U, // CPY_ZPmV_D + 145U, // CPY_ZPmV_H + 2304U, // CPY_ZPmV_S + 2570U, // CPY_ZPzI_B + 2634U, // CPY_ZPzI_D + 17U, // CPY_ZPzI_H + 2698U, // CPY_ZPzI_S + 2770U, // CPYi16 + 2770U, // CPYi32 + 2771U, // CPYi64 + 2771U, // CPYi8 + 261U, // CRC32Brr + 261U, // CRC32CBrr + 261U, // CRC32CHrr + 261U, // CRC32CWrr + 261U, // CRC32CXrr + 261U, // CRC32Hrr + 261U, // CRC32Wrr + 261U, // CRC32Xrr + 3744005U, // CSELWr + 3744005U, // CSELXr + 3744005U, // CSINCWr + 3744005U, // CSINCXr + 3744005U, // CSINVWr + 3744005U, // CSINVXr + 3744005U, // CSNEGWr + 3744005U, // CSNEGXr + 1U, // CTERMEQ_WW + 1U, // CTERMEQ_XX + 1U, // CTERMNE_WW + 1U, // CTERMNE_XX + 0U, // CompilerBarrier + 0U, // DCPS1 + 0U, // DCPS2 + 0U, // DCPS3 + 0U, // DECB_XPiI + 0U, // DECD_XPiI + 0U, // DECD_ZPiI + 0U, // DECH_XPiI + 0U, // DECH_ZPiI + 1U, // DECP_XP_B + 1U, // DECP_XP_D + 1U, // DECP_XP_H + 1U, // DECP_XP_S + 1U, // DECP_ZP_D + 0U, // DECP_ZP_H + 1U, // DECP_ZP_S + 0U, // DECW_XPiI + 0U, // DECW_ZPiI + 0U, // DMB + 0U, // DRPS + 0U, // DSB + 0U, // DUPM_ZI + 0U, // DUP_ZI_B + 0U, // DUP_ZI_D + 0U, // DUP_ZI_H + 0U, // DUP_ZI_S + 1U, // DUP_ZR_B + 1U, // DUP_ZR_D + 0U, // DUP_ZR_H + 1U, // DUP_ZR_S + 20U, // DUP_ZZI_B + 20U, // DUP_ZZI_D + 0U, // DUP_ZZI_H + 0U, // DUP_ZZI_Q + 20U, // DUP_ZZI_S + 1U, // DUPv16i8gpr + 2771U, // DUPv16i8lane + 1U, // DUPv2i32gpr + 2770U, // DUPv2i32lane + 1U, // DUPv2i64gpr + 2771U, // DUPv2i64lane + 1U, // DUPv4i16gpr + 2770U, // DUPv4i16lane + 1U, // DUPv4i32gpr + 2770U, // DUPv4i32lane + 1U, // DUPv8i16gpr + 2770U, // DUPv8i16lane + 1U, // DUPv8i8gpr + 2771U, // DUPv8i8lane + 0U, // EONWrr + 517U, // EONWrs + 0U, // EONXrr + 517U, // EONXrs + 36282695U, // EOR3 + 74570U, // EORS_PPzPP + 837U, // EORV_VPZ_B + 901U, // EORV_VPZ_D + 2245U, // EORV_VPZ_H + 1029U, // EORV_VPZ_S + 2117U, // EORWri + 0U, // EORWrr + 517U, // EORWrs + 2181U, // EORXri + 0U, // EORXrr + 517U, // EORXrs + 74570U, // EOR_PPzPP + 2181U, // EOR_ZI + 74560U, // EOR_ZPmZ_B + 598912U, // EOR_ZPmZ_D + 1131465U, // EOR_ZPmZ_H + 1647616U, // EOR_ZPmZ_S + 901U, // EOR_ZZZ + 33095U, // EORv16i8 + 57672U, // EORv8i8 + 0U, // ERET + 0U, // ERETAA + 0U, // ERETAB + 2171141U, // EXTRWrri + 2171141U, // EXTRXrri + 4793157U, // EXT_ZZI + 2203975U, // EXTv16i8 + 131400U, // EXTv8i8 + 0U, // F128CSEL + 261U, // FABD16 + 261U, // FABD32 + 261U, // FABD64 + 598912U, // FABD_ZPmZ_D + 1131465U, // FABD_ZPmZ_H + 1647616U, // FABD_ZPmZ_S + 41287U, // FABDv2f32 + 8517U, // FABDv2f64 + 49480U, // FABDv4f16 + 16710U, // FABDv4f32 + 24902U, // FABDv8f16 + 1U, // FABSDr + 1U, // FABSHr + 1U, // FABSSr + 64U, // FABS_ZPmZ_D + 128U, // FABS_ZPmZ_H + 192U, // FABS_ZPmZ_S + 2U, // FABSv2f32 + 2U, // FABSv2f64 + 3U, // FABSv4f16 + 3U, // FABSv4f32 + 4U, // FABSv8f16 + 261U, // FACGE16 + 261U, // FACGE32 + 261U, // FACGE64 + 598922U, // FACGE_PPzZZ_D + 1131465U, // FACGE_PPzZZ_H + 1647626U, // FACGE_PPzZZ_S + 41287U, // FACGEv2f32 + 8517U, // FACGEv2f64 + 49480U, // FACGEv4f16 + 16710U, // FACGEv4f32 + 24902U, // FACGEv8f16 + 261U, // FACGT16 + 261U, // FACGT32 + 261U, // FACGT64 + 598922U, // FACGT_PPzZZ_D + 1131465U, // FACGT_PPzZZ_H + 1647626U, // FACGT_PPzZZ_S + 41287U, // FACGTv2f32 + 8517U, // FACGTv2f64 + 49480U, // FACGTv4f16 + 16710U, // FACGTv4f32 + 24902U, // FACGTv8f16 + 598277U, // FADDA_VPZ_D + 4268293U, // FADDA_VPZ_H + 1646853U, // FADDA_VPZ_S + 261U, // FADDDrr + 261U, // FADDHrr + 41287U, // FADDPv2f32 + 8517U, // FADDPv2f64 + 20U, // FADDPv2i16p + 2U, // FADDPv2i32p + 2U, // FADDPv2i64p + 49480U, // FADDPv4f16 + 16710U, // FADDPv4f32 + 24902U, // FADDPv8f16 + 261U, // FADDSrr + 901U, // FADDV_VPZ_D + 2245U, // FADDV_VPZ_H + 1029U, // FADDV_VPZ_S + 5317504U, // FADD_ZPmI_D + 140233U, // FADD_ZPmI_H + 5317632U, // FADD_ZPmI_S + 598912U, // FADD_ZPmZ_D + 1131465U, // FADD_ZPmZ_H + 1647616U, // FADD_ZPmZ_S + 901U, // FADD_ZZZ_D + 137U, // FADD_ZZZ_H + 1029U, // FADD_ZZZ_S + 41287U, // FADDv2f32 + 8517U, // FADDv2f64 + 49480U, // FADDv4f16 + 16710U, // FADDv4f32 + 24902U, // FADDv8f16 + 67707776U, // FCADD_ZPmZ_D + 106513353U, // FCADD_ZPmZ_H + 68756480U, // FCADD_ZPmZ_S + 6439239U, // FCADDv2f32 + 6447429U, // FCADDv2f64 + 6455624U, // FCADDv4f16 + 6463814U, // FCADDv4f32 + 6472006U, // FCADDv8f16 + 3744005U, // FCCMPDrr + 3744005U, // FCCMPEDrr + 3744005U, // FCCMPEHrr + 3744005U, // FCCMPESrr + 3744005U, // FCCMPHrr + 3744005U, // FCCMPSrr + 261U, // FCMEQ16 + 261U, // FCMEQ32 + 261U, // FCMEQ64 + 189322U, // FCMEQ_PPzZ0_D + 2825U, // FCMEQ_PPzZ0_H + 189450U, // FCMEQ_PPzZ0_S + 598922U, // FCMEQ_PPzZZ_D + 1131465U, // FCMEQ_PPzZZ_H + 1647626U, // FCMEQ_PPzZZ_S + 21U, // FCMEQv1i16rz + 21U, // FCMEQv1i32rz + 21U, // FCMEQv1i64rz + 41287U, // FCMEQv2f32 + 8517U, // FCMEQv2f64 + 21U, // FCMEQv2i32rz + 22U, // FCMEQv2i64rz + 49480U, // FCMEQv4f16 + 16710U, // FCMEQv4f32 + 22U, // FCMEQv4i16rz + 23U, // FCMEQv4i32rz + 24902U, // FCMEQv8f16 + 23U, // FCMEQv8i16rz + 261U, // FCMGE16 + 261U, // FCMGE32 + 261U, // FCMGE64 + 189322U, // FCMGE_PPzZ0_D + 2825U, // FCMGE_PPzZ0_H + 189450U, // FCMGE_PPzZ0_S + 598922U, // FCMGE_PPzZZ_D + 1131465U, // FCMGE_PPzZZ_H + 1647626U, // FCMGE_PPzZZ_S + 21U, // FCMGEv1i16rz + 21U, // FCMGEv1i32rz + 21U, // FCMGEv1i64rz + 41287U, // FCMGEv2f32 + 8517U, // FCMGEv2f64 + 21U, // FCMGEv2i32rz + 22U, // FCMGEv2i64rz + 49480U, // FCMGEv4f16 + 16710U, // FCMGEv4f32 + 22U, // FCMGEv4i16rz + 23U, // FCMGEv4i32rz + 24902U, // FCMGEv8f16 + 23U, // FCMGEv8i16rz + 261U, // FCMGT16 + 261U, // FCMGT32 + 261U, // FCMGT64 + 189322U, // FCMGT_PPzZ0_D + 2825U, // FCMGT_PPzZ0_H + 189450U, // FCMGT_PPzZ0_S + 598922U, // FCMGT_PPzZZ_D + 1131465U, // FCMGT_PPzZZ_H + 1647626U, // FCMGT_PPzZZ_S + 21U, // FCMGTv1i16rz + 21U, // FCMGTv1i32rz + 21U, // FCMGTv1i64rz + 41287U, // FCMGTv2f32 + 8517U, // FCMGTv2f64 + 21U, // FCMGTv2i32rz + 22U, // FCMGTv2i64rz + 49480U, // FCMGTv4f16 + 16710U, // FCMGTv4f32 + 22U, // FCMGTv4i16rz + 23U, // FCMGTv4i32rz + 24902U, // FCMGTv8f16 + 23U, // FCMGTv8i16rz + 342433856U, // FCMLA_ZPmZZ_D + 140182464U, // FCMLA_ZPmZZ_H + 342958272U, // FCMLA_ZPmZZ_S + 24U, // FCMLA_ZZZI_H + 7940952U, // FCMLA_ZZZI_S + 8536455U, // FCMLAv2f32 + 8544645U, // FCMLAv2f64 + 8552840U, // FCMLAv4f16 + 344662408U, // FCMLAv4f16_indexed + 8561030U, // FCMLAv4f32 + 344670598U, // FCMLAv4f32_indexed + 8569222U, // FCMLAv8f16 + 344662406U, // FCMLAv8f16_indexed + 189322U, // FCMLE_PPzZ0_D + 2825U, // FCMLE_PPzZ0_H + 189450U, // FCMLE_PPzZ0_S + 21U, // FCMLEv1i16rz + 21U, // FCMLEv1i32rz + 21U, // FCMLEv1i64rz + 21U, // FCMLEv2i32rz + 22U, // FCMLEv2i64rz + 22U, // FCMLEv4i16rz + 23U, // FCMLEv4i32rz + 23U, // FCMLEv8i16rz + 189322U, // FCMLT_PPzZ0_D + 2825U, // FCMLT_PPzZ0_H + 189450U, // FCMLT_PPzZ0_S + 21U, // FCMLTv1i16rz + 21U, // FCMLTv1i32rz + 21U, // FCMLTv1i64rz + 21U, // FCMLTv2i32rz + 22U, // FCMLTv2i64rz + 22U, // FCMLTv4i16rz + 23U, // FCMLTv4i32rz + 23U, // FCMLTv8i16rz + 189322U, // FCMNE_PPzZ0_D + 2825U, // FCMNE_PPzZ0_H + 189450U, // FCMNE_PPzZ0_S + 598922U, // FCMNE_PPzZZ_D + 1131465U, // FCMNE_PPzZZ_H + 1647626U, // FCMNE_PPzZZ_S + 0U, // FCMPDri + 1U, // FCMPDrr + 0U, // FCMPEDri + 1U, // FCMPEDrr + 0U, // FCMPEHri + 1U, // FCMPEHrr + 0U, // FCMPESri + 1U, // FCMPESrr + 0U, // FCMPHri + 1U, // FCMPHrr + 0U, // FCMPSri + 1U, // FCMPSrr + 598922U, // FCMUO_PPzZZ_D + 1131465U, // FCMUO_PPzZZ_H + 1647626U, // FCMUO_PPzZZ_S + 2944U, // FCPY_ZPmI_D + 25U, // FCPY_ZPmI_H + 2944U, // FCPY_ZPmI_S + 3744005U, // FCSELDrrr + 3744005U, // FCSELHrrr + 3744005U, // FCSELSrrr + 1U, // FCVTASUWDr + 1U, // FCVTASUWHr + 1U, // FCVTASUWSr + 1U, // FCVTASUXDr + 1U, // FCVTASUXHr + 1U, // FCVTASUXSr + 1U, // FCVTASv1f16 + 1U, // FCVTASv1i32 + 1U, // FCVTASv1i64 + 2U, // FCVTASv2f32 + 2U, // FCVTASv2f64 + 3U, // FCVTASv4f16 + 3U, // FCVTASv4f32 + 4U, // FCVTASv8f16 + 1U, // FCVTAUUWDr + 1U, // FCVTAUUWHr + 1U, // FCVTAUUWSr + 1U, // FCVTAUUXDr + 1U, // FCVTAUUXHr + 1U, // FCVTAUUXSr + 1U, // FCVTAUv1f16 + 1U, // FCVTAUv1i32 + 1U, // FCVTAUv1i64 + 2U, // FCVTAUv2f32 + 2U, // FCVTAUv2f64 + 3U, // FCVTAUv4f16 + 3U, // FCVTAUv4f32 + 4U, // FCVTAUv8f16 + 1U, // FCVTDHr + 1U, // FCVTDSr + 1U, // FCVTHDr + 1U, // FCVTHSr + 2U, // FCVTLv2i32 + 3U, // FCVTLv4i16 + 3U, // FCVTLv4i32 + 4U, // FCVTLv8i16 + 1U, // FCVTMSUWDr + 1U, // FCVTMSUWHr + 1U, // FCVTMSUWSr + 1U, // FCVTMSUXDr + 1U, // FCVTMSUXHr + 1U, // FCVTMSUXSr + 1U, // FCVTMSv1f16 + 1U, // FCVTMSv1i32 + 1U, // FCVTMSv1i64 + 2U, // FCVTMSv2f32 + 2U, // FCVTMSv2f64 + 3U, // FCVTMSv4f16 + 3U, // FCVTMSv4f32 + 4U, // FCVTMSv8f16 + 1U, // FCVTMUUWDr + 1U, // FCVTMUUWHr + 1U, // FCVTMUUWSr + 1U, // FCVTMUUXDr + 1U, // FCVTMUUXHr + 1U, // FCVTMUUXSr + 1U, // FCVTMUv1f16 + 1U, // FCVTMUv1i32 + 1U, // FCVTMUv1i64 + 2U, // FCVTMUv2f32 + 2U, // FCVTMUv2f64 + 3U, // FCVTMUv4f16 + 3U, // FCVTMUv4f32 + 4U, // FCVTMUv8f16 + 1U, // FCVTNSUWDr + 1U, // FCVTNSUWHr + 1U, // FCVTNSUWSr + 1U, // FCVTNSUXDr + 1U, // FCVTNSUXHr + 1U, // FCVTNSUXSr + 1U, // FCVTNSv1f16 + 1U, // FCVTNSv1i32 + 1U, // FCVTNSv1i64 + 2U, // FCVTNSv2f32 + 2U, // FCVTNSv2f64 + 3U, // FCVTNSv4f16 + 3U, // FCVTNSv4f32 + 4U, // FCVTNSv8f16 + 1U, // FCVTNUUWDr + 1U, // FCVTNUUWHr + 1U, // FCVTNUUWSr + 1U, // FCVTNUUXDr + 1U, // FCVTNUUXHr + 1U, // FCVTNUUXSr + 1U, // FCVTNUv1f16 + 1U, // FCVTNUv1i32 + 1U, // FCVTNUv1i64 + 2U, // FCVTNUv2f32 + 2U, // FCVTNUv2f64 + 3U, // FCVTNUv4f16 + 3U, // FCVTNUv4f32 + 4U, // FCVTNUv8f16 + 2U, // FCVTNv2i32 + 3U, // FCVTNv4i16 + 2U, // FCVTNv4i32 + 3U, // FCVTNv8i16 + 1U, // FCVTPSUWDr + 1U, // FCVTPSUWHr + 1U, // FCVTPSUWSr + 1U, // FCVTPSUXDr + 1U, // FCVTPSUXHr + 1U, // FCVTPSUXSr + 1U, // FCVTPSv1f16 + 1U, // FCVTPSv1i32 + 1U, // FCVTPSv1i64 + 2U, // FCVTPSv2f32 + 2U, // FCVTPSv2f64 + 3U, // FCVTPSv4f16 + 3U, // FCVTPSv4f32 + 4U, // FCVTPSv8f16 + 1U, // FCVTPUUWDr + 1U, // FCVTPUUWHr + 1U, // FCVTPUUWSr + 1U, // FCVTPUUXDr + 1U, // FCVTPUUXHr + 1U, // FCVTPUUXSr + 1U, // FCVTPUv1f16 + 1U, // FCVTPUv1i32 + 1U, // FCVTPUv1i64 + 2U, // FCVTPUv2f32 + 2U, // FCVTPUv2f64 + 3U, // FCVTPUv4f16 + 3U, // FCVTPUv4f32 + 4U, // FCVTPUv8f16 + 1U, // FCVTSDr + 1U, // FCVTSHr + 1U, // FCVTXNv1i64 + 2U, // FCVTXNv2f32 + 2U, // FCVTXNv4f32 + 261U, // FCVTZSSWDri + 261U, // FCVTZSSWHri + 261U, // FCVTZSSWSri + 261U, // FCVTZSSXDri + 261U, // FCVTZSSXHri + 261U, // FCVTZSSXSri + 1U, // FCVTZSUWDr + 1U, // FCVTZSUWHr + 1U, // FCVTZSUWSr + 1U, // FCVTZSUXDr + 1U, // FCVTZSUXHr + 1U, // FCVTZSUXSr + 64U, // FCVTZS_ZPmZ_DtoD + 64U, // FCVTZS_ZPmZ_DtoS + 3008U, // FCVTZS_ZPmZ_HtoD + 128U, // FCVTZS_ZPmZ_HtoH + 3008U, // FCVTZS_ZPmZ_HtoS + 192U, // FCVTZS_ZPmZ_StoD + 192U, // FCVTZS_ZPmZ_StoS + 261U, // FCVTZSd + 261U, // FCVTZSh + 261U, // FCVTZSs + 1U, // FCVTZSv1f16 + 1U, // FCVTZSv1i32 + 1U, // FCVTZSv1i64 + 2U, // FCVTZSv2f32 + 2U, // FCVTZSv2f64 + 263U, // FCVTZSv2i32_shift + 261U, // FCVTZSv2i64_shift + 3U, // FCVTZSv4f16 + 3U, // FCVTZSv4f32 + 264U, // FCVTZSv4i16_shift + 262U, // FCVTZSv4i32_shift + 4U, // FCVTZSv8f16 + 262U, // FCVTZSv8i16_shift + 261U, // FCVTZUSWDri + 261U, // FCVTZUSWHri + 261U, // FCVTZUSWSri + 261U, // FCVTZUSXDri + 261U, // FCVTZUSXHri + 261U, // FCVTZUSXSri + 1U, // FCVTZUUWDr + 1U, // FCVTZUUWHr + 1U, // FCVTZUUWSr + 1U, // FCVTZUUXDr + 1U, // FCVTZUUXHr + 1U, // FCVTZUUXSr + 64U, // FCVTZU_ZPmZ_DtoD + 64U, // FCVTZU_ZPmZ_DtoS + 3008U, // FCVTZU_ZPmZ_HtoD + 128U, // FCVTZU_ZPmZ_HtoH + 3008U, // FCVTZU_ZPmZ_HtoS + 192U, // FCVTZU_ZPmZ_StoD + 192U, // FCVTZU_ZPmZ_StoS + 261U, // FCVTZUd + 261U, // FCVTZUh + 261U, // FCVTZUs + 1U, // FCVTZUv1f16 + 1U, // FCVTZUv1i32 + 1U, // FCVTZUv1i64 + 2U, // FCVTZUv2f32 + 2U, // FCVTZUv2f64 + 263U, // FCVTZUv2i32_shift + 261U, // FCVTZUv2i64_shift + 3U, // FCVTZUv4f16 + 3U, // FCVTZUv4f32 + 264U, // FCVTZUv4i16_shift + 262U, // FCVTZUv4i32_shift + 4U, // FCVTZUv8f16 + 262U, // FCVTZUv8i16_shift + 153U, // FCVT_ZPmZ_DtoH + 64U, // FCVT_ZPmZ_DtoS + 3008U, // FCVT_ZPmZ_HtoD + 3008U, // FCVT_ZPmZ_HtoS + 192U, // FCVT_ZPmZ_StoD + 152U, // FCVT_ZPmZ_StoH + 261U, // FDIVDrr + 261U, // FDIVHrr + 598912U, // FDIVR_ZPmZ_D + 1131465U, // FDIVR_ZPmZ_H + 1647616U, // FDIVR_ZPmZ_S + 261U, // FDIVSrr + 598912U, // FDIV_ZPmZ_D + 1131465U, // FDIV_ZPmZ_H + 1647616U, // FDIV_ZPmZ_S + 41287U, // FDIVv2f32 + 8517U, // FDIVv2f64 + 49480U, // FDIVv4f16 + 16710U, // FDIVv4f32 + 24902U, // FDIVv8f16 + 0U, // FDUP_ZI_D + 0U, // FDUP_ZI_H + 0U, // FDUP_ZI_S + 1U, // FEXPA_ZZ_D + 0U, // FEXPA_ZZ_H + 1U, // FEXPA_ZZ_S + 1U, // FJCVTZS + 2171141U, // FMADDDrrr + 2171141U, // FMADDHrrr + 2171141U, // FMADDSrrr + 6889536U, // FMAD_ZPmZZ_D + 1246144U, // FMAD_ZPmZZ_H + 7413952U, // FMAD_ZPmZZ_S + 261U, // FMAXDrr + 261U, // FMAXHrr + 261U, // FMAXNMDrr + 261U, // FMAXNMHrr + 41287U, // FMAXNMPv2f32 + 8517U, // FMAXNMPv2f64 + 20U, // FMAXNMPv2i16p + 2U, // FMAXNMPv2i32p + 2U, // FMAXNMPv2i64p + 49480U, // FMAXNMPv4f16 + 16710U, // FMAXNMPv4f32 + 24902U, // FMAXNMPv8f16 + 261U, // FMAXNMSrr + 901U, // FMAXNMV_VPZ_D + 2245U, // FMAXNMV_VPZ_H + 1029U, // FMAXNMV_VPZ_S + 3U, // FMAXNMVv4i16v + 3U, // FMAXNMVv4i32v + 4U, // FMAXNMVv8i16v + 9511808U, // FMAXNM_ZPmI_D + 222153U, // FMAXNM_ZPmI_H + 9511936U, // FMAXNM_ZPmI_S + 598912U, // FMAXNM_ZPmZ_D + 1131465U, // FMAXNM_ZPmZ_H + 1647616U, // FMAXNM_ZPmZ_S + 41287U, // FMAXNMv2f32 + 8517U, // FMAXNMv2f64 + 49480U, // FMAXNMv4f16 + 16710U, // FMAXNMv4f32 + 24902U, // FMAXNMv8f16 + 41287U, // FMAXPv2f32 + 8517U, // FMAXPv2f64 + 20U, // FMAXPv2i16p + 2U, // FMAXPv2i32p + 2U, // FMAXPv2i64p + 49480U, // FMAXPv4f16 + 16710U, // FMAXPv4f32 + 24902U, // FMAXPv8f16 + 261U, // FMAXSrr + 901U, // FMAXV_VPZ_D + 2245U, // FMAXV_VPZ_H + 1029U, // FMAXV_VPZ_S + 3U, // FMAXVv4i16v + 3U, // FMAXVv4i32v + 4U, // FMAXVv8i16v + 9511808U, // FMAX_ZPmI_D + 222153U, // FMAX_ZPmI_H + 9511936U, // FMAX_ZPmI_S + 598912U, // FMAX_ZPmZ_D + 1131465U, // FMAX_ZPmZ_H + 1647616U, // FMAX_ZPmZ_S + 41287U, // FMAXv2f32 + 8517U, // FMAXv2f64 + 49480U, // FMAXv4f16 + 16710U, // FMAXv4f32 + 24902U, // FMAXv8f16 + 261U, // FMINDrr + 261U, // FMINHrr + 261U, // FMINNMDrr + 261U, // FMINNMHrr + 41287U, // FMINNMPv2f32 + 8517U, // FMINNMPv2f64 + 20U, // FMINNMPv2i16p + 2U, // FMINNMPv2i32p + 2U, // FMINNMPv2i64p + 49480U, // FMINNMPv4f16 + 16710U, // FMINNMPv4f32 + 24902U, // FMINNMPv8f16 + 261U, // FMINNMSrr + 901U, // FMINNMV_VPZ_D + 2245U, // FMINNMV_VPZ_H + 1029U, // FMINNMV_VPZ_S + 3U, // FMINNMVv4i16v + 3U, // FMINNMVv4i32v + 4U, // FMINNMVv8i16v + 9511808U, // FMINNM_ZPmI_D + 222153U, // FMINNM_ZPmI_H + 9511936U, // FMINNM_ZPmI_S + 598912U, // FMINNM_ZPmZ_D + 1131465U, // FMINNM_ZPmZ_H + 1647616U, // FMINNM_ZPmZ_S + 41287U, // FMINNMv2f32 + 8517U, // FMINNMv2f64 + 49480U, // FMINNMv4f16 + 16710U, // FMINNMv4f32 + 24902U, // FMINNMv8f16 + 41287U, // FMINPv2f32 + 8517U, // FMINPv2f64 + 20U, // FMINPv2i16p + 2U, // FMINPv2i32p + 2U, // FMINPv2i64p + 49480U, // FMINPv4f16 + 16710U, // FMINPv4f32 + 24902U, // FMINPv8f16 + 261U, // FMINSrr + 901U, // FMINV_VPZ_D + 2245U, // FMINV_VPZ_H + 1029U, // FMINV_VPZ_S + 3U, // FMINVv4i16v + 3U, // FMINVv4i32v + 4U, // FMINVv8i16v + 9511808U, // FMIN_ZPmI_D + 222153U, // FMIN_ZPmI_H + 9511936U, // FMIN_ZPmI_S + 598912U, // FMIN_ZPmZ_D + 1131465U, // FMIN_ZPmZ_H + 1647616U, // FMIN_ZPmZ_S + 41287U, // FMINv2f32 + 8517U, // FMINv2f64 + 49480U, // FMINv4f16 + 16710U, // FMINv4f32 + 24902U, // FMINv8f16 + 6889536U, // FMLA_ZPmZZ_D + 1246144U, // FMLA_ZPmZZ_H + 7413952U, // FMLA_ZPmZZ_S + 2905U, // FMLA_ZZZI_D + 0U, // FMLA_ZZZI_H + 2904U, // FMLA_ZZZI_S + 9118085U, // FMLAv1i16_indexed + 9126277U, // FMLAv1i32_indexed + 9142661U, // FMLAv1i64_indexed + 41351U, // FMLAv2f32 + 8581U, // FMLAv2f64 + 9126279U, // FMLAv2i32_indexed + 9142661U, // FMLAv2i64_indexed + 49544U, // FMLAv4f16 + 16774U, // FMLAv4f32 + 9118088U, // FMLAv4i16_indexed + 9126278U, // FMLAv4i32_indexed + 24966U, // FMLAv8f16 + 9118086U, // FMLAv8i16_indexed + 6889536U, // FMLS_ZPmZZ_D + 1246144U, // FMLS_ZPmZZ_H + 7413952U, // FMLS_ZPmZZ_S + 2905U, // FMLS_ZZZI_D + 0U, // FMLS_ZZZI_H + 2904U, // FMLS_ZZZI_S + 9118085U, // FMLSv1i16_indexed + 9126277U, // FMLSv1i32_indexed + 9142661U, // FMLSv1i64_indexed + 41351U, // FMLSv2f32 + 8581U, // FMLSv2f64 + 9126279U, // FMLSv2i32_indexed + 9142661U, // FMLSv2i64_indexed + 49544U, // FMLSv4f16 + 16774U, // FMLSv4f32 + 9118088U, // FMLSv4i16_indexed + 9126278U, // FMLSv4i32_indexed + 24966U, // FMLSv8f16 + 9118086U, // FMLSv8i16_indexed + 0U, // FMOVD0 + 2771U, // FMOVDXHighr + 1U, // FMOVDXr + 0U, // FMOVDi + 1U, // FMOVDr + 0U, // FMOVH0 + 1U, // FMOVHWr + 1U, // FMOVHXr + 0U, // FMOVHi + 1U, // FMOVHr + 0U, // FMOVS0 + 1U, // FMOVSWr + 0U, // FMOVSi + 1U, // FMOVSr + 1U, // FMOVWHr + 1U, // FMOVWSr + 1U, // FMOVXDHighr + 1U, // FMOVXDr + 1U, // FMOVXHr + 0U, // FMOVv2f32_ns + 0U, // FMOVv2f64_ns + 0U, // FMOVv4f16_ns + 0U, // FMOVv4f32_ns + 0U, // FMOVv8f16_ns + 6889536U, // FMSB_ZPmZZ_D + 1246144U, // FMSB_ZPmZZ_H + 7413952U, // FMSB_ZPmZZ_S + 2171141U, // FMSUBDrrr + 2171141U, // FMSUBHrrr + 2171141U, // FMSUBSrrr + 261U, // FMULDrr + 261U, // FMULHrr + 261U, // FMULSrr + 261U, // FMULX16 + 261U, // FMULX32 + 261U, // FMULX64 + 598912U, // FMULX_ZPmZ_D + 1131465U, // FMULX_ZPmZ_H + 1647616U, // FMULX_ZPmZ_S + 10166597U, // FMULXv1i16_indexed + 10174789U, // FMULXv1i32_indexed + 10191173U, // FMULXv1i64_indexed + 41287U, // FMULXv2f32 + 8517U, // FMULXv2f64 + 10174791U, // FMULXv2i32_indexed + 10191173U, // FMULXv2i64_indexed + 49480U, // FMULXv4f16 + 16710U, // FMULXv4f32 + 10166600U, // FMULXv4i16_indexed + 10174790U, // FMULXv4i32_indexed + 24902U, // FMULXv8f16 + 10166598U, // FMULXv8i16_indexed + 10560384U, // FMUL_ZPmI_D + 238537U, // FMUL_ZPmI_H + 10560512U, // FMUL_ZPmI_S + 598912U, // FMUL_ZPmZ_D + 1131465U, // FMUL_ZPmZ_H + 1647616U, // FMUL_ZPmZ_S + 246661U, // FMUL_ZZZI_D + 3081U, // FMUL_ZZZI_H + 246789U, // FMUL_ZZZI_S + 901U, // FMUL_ZZZ_D + 137U, // FMUL_ZZZ_H + 1029U, // FMUL_ZZZ_S + 10166597U, // FMULv1i16_indexed + 10174789U, // FMULv1i32_indexed + 10191173U, // FMULv1i64_indexed + 41287U, // FMULv2f32 + 8517U, // FMULv2f64 + 10174791U, // FMULv2i32_indexed + 10191173U, // FMULv2i64_indexed + 49480U, // FMULv4f16 + 16710U, // FMULv4f32 + 10166600U, // FMULv4i16_indexed + 10174790U, // FMULv4i32_indexed + 24902U, // FMULv8f16 + 10166598U, // FMULv8i16_indexed + 1U, // FNEGDr + 1U, // FNEGHr + 1U, // FNEGSr + 64U, // FNEG_ZPmZ_D + 128U, // FNEG_ZPmZ_H + 192U, // FNEG_ZPmZ_S + 2U, // FNEGv2f32 + 2U, // FNEGv2f64 + 3U, // FNEGv4f16 + 3U, // FNEGv4f32 + 4U, // FNEGv8f16 + 2171141U, // FNMADDDrrr + 2171141U, // FNMADDHrrr + 2171141U, // FNMADDSrrr + 6889536U, // FNMAD_ZPmZZ_D + 1246144U, // FNMAD_ZPmZZ_H + 7413952U, // FNMAD_ZPmZZ_S + 6889536U, // FNMLA_ZPmZZ_D + 1246144U, // FNMLA_ZPmZZ_H + 7413952U, // FNMLA_ZPmZZ_S + 6889536U, // FNMLS_ZPmZZ_D + 1246144U, // FNMLS_ZPmZZ_H + 7413952U, // FNMLS_ZPmZZ_S + 6889536U, // FNMSB_ZPmZZ_D + 1246144U, // FNMSB_ZPmZZ_H + 7413952U, // FNMSB_ZPmZZ_S + 2171141U, // FNMSUBDrrr + 2171141U, // FNMSUBHrrr + 2171141U, // FNMSUBSrrr + 261U, // FNMULDrr + 261U, // FNMULHrr + 261U, // FNMULSrr + 1U, // FRECPE_ZZ_D + 0U, // FRECPE_ZZ_H + 1U, // FRECPE_ZZ_S + 1U, // FRECPEv1f16 + 1U, // FRECPEv1i32 + 1U, // FRECPEv1i64 + 2U, // FRECPEv2f32 + 2U, // FRECPEv2f64 + 3U, // FRECPEv4f16 + 3U, // FRECPEv4f32 + 4U, // FRECPEv8f16 + 261U, // FRECPS16 + 261U, // FRECPS32 + 261U, // FRECPS64 + 901U, // FRECPS_ZZZ_D + 137U, // FRECPS_ZZZ_H + 1029U, // FRECPS_ZZZ_S + 41287U, // FRECPSv2f32 + 8517U, // FRECPSv2f64 + 49480U, // FRECPSv4f16 + 16710U, // FRECPSv4f32 + 24902U, // FRECPSv8f16 + 64U, // FRECPX_ZPmZ_D + 128U, // FRECPX_ZPmZ_H + 192U, // FRECPX_ZPmZ_S + 1U, // FRECPXv1f16 + 1U, // FRECPXv1i32 + 1U, // FRECPXv1i64 + 1U, // FRINTADr + 1U, // FRINTAHr + 1U, // FRINTASr + 64U, // FRINTA_ZPmZ_D + 128U, // FRINTA_ZPmZ_H + 192U, // FRINTA_ZPmZ_S + 2U, // FRINTAv2f32 + 2U, // FRINTAv2f64 + 3U, // FRINTAv4f16 + 3U, // FRINTAv4f32 + 4U, // FRINTAv8f16 + 1U, // FRINTIDr + 1U, // FRINTIHr + 1U, // FRINTISr + 64U, // FRINTI_ZPmZ_D + 128U, // FRINTI_ZPmZ_H + 192U, // FRINTI_ZPmZ_S + 2U, // FRINTIv2f32 + 2U, // FRINTIv2f64 + 3U, // FRINTIv4f16 + 3U, // FRINTIv4f32 + 4U, // FRINTIv8f16 + 1U, // FRINTMDr + 1U, // FRINTMHr + 1U, // FRINTMSr + 64U, // FRINTM_ZPmZ_D + 128U, // FRINTM_ZPmZ_H + 192U, // FRINTM_ZPmZ_S + 2U, // FRINTMv2f32 + 2U, // FRINTMv2f64 + 3U, // FRINTMv4f16 + 3U, // FRINTMv4f32 + 4U, // FRINTMv8f16 + 1U, // FRINTNDr + 1U, // FRINTNHr + 1U, // FRINTNSr + 64U, // FRINTN_ZPmZ_D + 128U, // FRINTN_ZPmZ_H + 192U, // FRINTN_ZPmZ_S + 2U, // FRINTNv2f32 + 2U, // FRINTNv2f64 + 3U, // FRINTNv4f16 + 3U, // FRINTNv4f32 + 4U, // FRINTNv8f16 + 1U, // FRINTPDr + 1U, // FRINTPHr + 1U, // FRINTPSr + 64U, // FRINTP_ZPmZ_D + 128U, // FRINTP_ZPmZ_H + 192U, // FRINTP_ZPmZ_S + 2U, // FRINTPv2f32 + 2U, // FRINTPv2f64 + 3U, // FRINTPv4f16 + 3U, // FRINTPv4f32 + 4U, // FRINTPv8f16 + 1U, // FRINTXDr + 1U, // FRINTXHr + 1U, // FRINTXSr + 64U, // FRINTX_ZPmZ_D + 128U, // FRINTX_ZPmZ_H + 192U, // FRINTX_ZPmZ_S + 2U, // FRINTXv2f32 + 2U, // FRINTXv2f64 + 3U, // FRINTXv4f16 + 3U, // FRINTXv4f32 + 4U, // FRINTXv8f16 + 1U, // FRINTZDr + 1U, // FRINTZHr + 1U, // FRINTZSr + 64U, // FRINTZ_ZPmZ_D + 128U, // FRINTZ_ZPmZ_H + 192U, // FRINTZ_ZPmZ_S + 2U, // FRINTZv2f32 + 2U, // FRINTZv2f64 + 3U, // FRINTZv4f16 + 3U, // FRINTZv4f32 + 4U, // FRINTZv8f16 + 1U, // FRSQRTE_ZZ_D + 0U, // FRSQRTE_ZZ_H + 1U, // FRSQRTE_ZZ_S + 1U, // FRSQRTEv1f16 + 1U, // FRSQRTEv1i32 + 1U, // FRSQRTEv1i64 + 2U, // FRSQRTEv2f32 + 2U, // FRSQRTEv2f64 + 3U, // FRSQRTEv4f16 + 3U, // FRSQRTEv4f32 + 4U, // FRSQRTEv8f16 + 261U, // FRSQRTS16 + 261U, // FRSQRTS32 + 261U, // FRSQRTS64 + 901U, // FRSQRTS_ZZZ_D + 137U, // FRSQRTS_ZZZ_H + 1029U, // FRSQRTS_ZZZ_S + 41287U, // FRSQRTSv2f32 + 8517U, // FRSQRTSv2f64 + 49480U, // FRSQRTSv4f16 + 16710U, // FRSQRTSv4f32 + 24902U, // FRSQRTSv8f16 + 598912U, // FSCALE_ZPmZ_D + 1131465U, // FSCALE_ZPmZ_H + 1647616U, // FSCALE_ZPmZ_S + 1U, // FSQRTDr + 1U, // FSQRTHr + 1U, // FSQRTSr + 64U, // FSQRT_ZPmZ_D + 128U, // FSQRT_ZPmZ_H + 192U, // FSQRT_ZPmZ_S + 2U, // FSQRTv2f32 + 2U, // FSQRTv2f64 + 3U, // FSQRTv4f16 + 3U, // FSQRTv4f32 + 4U, // FSQRTv8f16 + 261U, // FSUBDrr + 261U, // FSUBHrr + 5317504U, // FSUBR_ZPmI_D + 140233U, // FSUBR_ZPmI_H + 5317632U, // FSUBR_ZPmI_S + 598912U, // FSUBR_ZPmZ_D + 1131465U, // FSUBR_ZPmZ_H + 1647616U, // FSUBR_ZPmZ_S + 261U, // FSUBSrr + 5317504U, // FSUB_ZPmI_D + 140233U, // FSUB_ZPmI_H + 5317632U, // FSUB_ZPmI_S + 598912U, // FSUB_ZPmZ_D + 1131465U, // FSUB_ZPmZ_H + 1647616U, // FSUB_ZPmZ_S + 901U, // FSUB_ZZZ_D + 137U, // FSUB_ZZZ_H + 1029U, // FSUB_ZZZ_S + 41287U, // FSUBv2f32 + 8517U, // FSUBv2f64 + 49480U, // FSUBv4f16 + 16710U, // FSUBv4f32 + 24902U, // FSUBv8f16 + 2171781U, // FTMAD_ZZI_D + 91081U, // FTMAD_ZZI_H + 2171909U, // FTMAD_ZZI_S + 901U, // FTSMUL_ZZZ_D + 137U, // FTSMUL_ZZZ_H + 1029U, // FTSMUL_ZZZ_S + 901U, // FTSSEL_ZZZ_D + 137U, // FTSSEL_ZZZ_H + 1029U, // FTSSEL_ZZZ_S + 3153U, // GLD1B_D_IMM_REAL + 3205U, // GLD1B_D_REAL + 3269U, // GLD1B_D_SXTW_REAL + 3333U, // GLD1B_D_UXTW_REAL + 3153U, // GLD1B_S_IMM_REAL + 3397U, // GLD1B_S_SXTW_REAL + 3461U, // GLD1B_S_UXTW_REAL + 26U, // GLD1D_IMM_REAL + 3205U, // GLD1D_REAL + 3525U, // GLD1D_SCALED_REAL + 3269U, // GLD1D_SXTW_REAL + 3589U, // GLD1D_SXTW_SCALED_REAL + 3333U, // GLD1D_UXTW_REAL + 3653U, // GLD1D_UXTW_SCALED_REAL + 26U, // GLD1H_D_IMM_REAL + 3205U, // GLD1H_D_REAL + 3717U, // GLD1H_D_SCALED_REAL + 3269U, // GLD1H_D_SXTW_REAL + 3781U, // GLD1H_D_SXTW_SCALED_REAL + 3333U, // GLD1H_D_UXTW_REAL + 3845U, // GLD1H_D_UXTW_SCALED_REAL + 26U, // GLD1H_S_IMM_REAL + 3397U, // GLD1H_S_SXTW_REAL + 3909U, // GLD1H_S_SXTW_SCALED_REAL + 3461U, // GLD1H_S_UXTW_REAL + 3973U, // GLD1H_S_UXTW_SCALED_REAL + 3153U, // GLD1SB_D_IMM_REAL + 3205U, // GLD1SB_D_REAL + 3269U, // GLD1SB_D_SXTW_REAL + 3333U, // GLD1SB_D_UXTW_REAL + 3153U, // GLD1SB_S_IMM_REAL + 3397U, // GLD1SB_S_SXTW_REAL + 3461U, // GLD1SB_S_UXTW_REAL + 26U, // GLD1SH_D_IMM_REAL + 3205U, // GLD1SH_D_REAL + 3717U, // GLD1SH_D_SCALED_REAL + 3269U, // GLD1SH_D_SXTW_REAL + 3781U, // GLD1SH_D_SXTW_SCALED_REAL + 3333U, // GLD1SH_D_UXTW_REAL + 3845U, // GLD1SH_D_UXTW_SCALED_REAL + 26U, // GLD1SH_S_IMM_REAL + 3397U, // GLD1SH_S_SXTW_REAL + 3909U, // GLD1SH_S_SXTW_SCALED_REAL + 3461U, // GLD1SH_S_UXTW_REAL + 3973U, // GLD1SH_S_UXTW_SCALED_REAL + 27U, // GLD1SW_D_IMM_REAL + 3205U, // GLD1SW_D_REAL + 4037U, // GLD1SW_D_SCALED_REAL + 3269U, // GLD1SW_D_SXTW_REAL + 4101U, // GLD1SW_D_SXTW_SCALED_REAL + 3333U, // GLD1SW_D_UXTW_REAL + 4165U, // GLD1SW_D_UXTW_SCALED_REAL + 27U, // GLD1W_D_IMM_REAL + 3205U, // GLD1W_D_REAL + 4037U, // GLD1W_D_SCALED_REAL + 3269U, // GLD1W_D_SXTW_REAL + 4101U, // GLD1W_D_SXTW_SCALED_REAL + 3333U, // GLD1W_D_UXTW_REAL + 4165U, // GLD1W_D_UXTW_SCALED_REAL + 27U, // GLD1W_IMM_REAL + 3397U, // GLD1W_SXTW_REAL + 4229U, // GLD1W_SXTW_SCALED_REAL + 3461U, // GLD1W_UXTW_REAL + 4293U, // GLD1W_UXTW_SCALED_REAL + 3153U, // GLDFF1B_D_IMM_REAL + 3205U, // GLDFF1B_D_REAL + 3269U, // GLDFF1B_D_SXTW_REAL + 3333U, // GLDFF1B_D_UXTW_REAL + 3153U, // GLDFF1B_S_IMM_REAL + 3397U, // GLDFF1B_S_SXTW_REAL + 3461U, // GLDFF1B_S_UXTW_REAL + 26U, // GLDFF1D_IMM_REAL + 3205U, // GLDFF1D_REAL + 3525U, // GLDFF1D_SCALED_REAL + 3269U, // GLDFF1D_SXTW_REAL + 3589U, // GLDFF1D_SXTW_SCALED_REAL + 3333U, // GLDFF1D_UXTW_REAL + 3653U, // GLDFF1D_UXTW_SCALED_REAL + 26U, // GLDFF1H_D_IMM_REAL + 3205U, // GLDFF1H_D_REAL + 3717U, // GLDFF1H_D_SCALED_REAL + 3269U, // GLDFF1H_D_SXTW_REAL + 3781U, // GLDFF1H_D_SXTW_SCALED_REAL + 3333U, // GLDFF1H_D_UXTW_REAL + 3845U, // GLDFF1H_D_UXTW_SCALED_REAL + 26U, // GLDFF1H_S_IMM_REAL + 3397U, // GLDFF1H_S_SXTW_REAL + 3909U, // GLDFF1H_S_SXTW_SCALED_REAL + 3461U, // GLDFF1H_S_UXTW_REAL + 3973U, // GLDFF1H_S_UXTW_SCALED_REAL + 3153U, // GLDFF1SB_D_IMM_REAL + 3205U, // GLDFF1SB_D_REAL + 3269U, // GLDFF1SB_D_SXTW_REAL + 3333U, // GLDFF1SB_D_UXTW_REAL + 3153U, // GLDFF1SB_S_IMM_REAL + 3397U, // GLDFF1SB_S_SXTW_REAL + 3461U, // GLDFF1SB_S_UXTW_REAL + 26U, // GLDFF1SH_D_IMM_REAL + 3205U, // GLDFF1SH_D_REAL + 3717U, // GLDFF1SH_D_SCALED_REAL + 3269U, // GLDFF1SH_D_SXTW_REAL + 3781U, // GLDFF1SH_D_SXTW_SCALED_REAL + 3333U, // GLDFF1SH_D_UXTW_REAL + 3845U, // GLDFF1SH_D_UXTW_SCALED_REAL + 26U, // GLDFF1SH_S_IMM_REAL + 3397U, // GLDFF1SH_S_SXTW_REAL + 3909U, // GLDFF1SH_S_SXTW_SCALED_REAL + 3461U, // GLDFF1SH_S_UXTW_REAL + 3973U, // GLDFF1SH_S_UXTW_SCALED_REAL + 27U, // GLDFF1SW_D_IMM_REAL + 3205U, // GLDFF1SW_D_REAL + 4037U, // GLDFF1SW_D_SCALED_REAL + 3269U, // GLDFF1SW_D_SXTW_REAL + 4101U, // GLDFF1SW_D_SXTW_SCALED_REAL + 3333U, // GLDFF1SW_D_UXTW_REAL + 4165U, // GLDFF1SW_D_UXTW_SCALED_REAL + 27U, // GLDFF1W_D_IMM_REAL + 3205U, // GLDFF1W_D_REAL + 4037U, // GLDFF1W_D_SCALED_REAL + 3269U, // GLDFF1W_D_SXTW_REAL + 4101U, // GLDFF1W_D_SXTW_SCALED_REAL + 3333U, // GLDFF1W_D_UXTW_REAL + 4165U, // GLDFF1W_D_UXTW_SCALED_REAL + 27U, // GLDFF1W_IMM_REAL + 3397U, // GLDFF1W_SXTW_REAL + 4229U, // GLDFF1W_SXTW_SCALED_REAL + 3461U, // GLDFF1W_UXTW_REAL + 4293U, // GLDFF1W_UXTW_SCALED_REAL + 0U, // HINT + 0U, // HLT + 0U, // HVC + 0U, // INCB_XPiI + 0U, // INCD_XPiI + 0U, // INCD_ZPiI + 0U, // INCH_XPiI + 0U, // INCH_ZPiI + 1U, // INCP_XP_B + 1U, // INCP_XP_D + 1U, // INCP_XP_H + 1U, // INCP_XP_S + 1U, // INCP_ZP_D + 0U, // INCP_ZP_H + 1U, // INCP_ZP_S + 0U, // INCW_XPiI + 0U, // INCW_ZPiI + 261U, // INDEX_II_B + 261U, // INDEX_II_D + 11U, // INDEX_II_H + 261U, // INDEX_II_S + 261U, // INDEX_IR_B + 261U, // INDEX_IR_D + 11U, // INDEX_IR_H + 261U, // INDEX_IR_S + 261U, // INDEX_RI_B + 261U, // INDEX_RI_D + 11U, // INDEX_RI_H + 261U, // INDEX_RI_S + 261U, // INDEX_RR_B + 261U, // INDEX_RR_D + 11U, // INDEX_RR_H + 261U, // INDEX_RR_S + 1U, // INSR_ZR_B + 1U, // INSR_ZR_D + 0U, // INSR_ZR_H + 1U, // INSR_ZR_S + 1U, // INSR_ZV_B + 1U, // INSR_ZV_D + 0U, // INSR_ZV_H + 1U, // INSR_ZV_S + 1U, // INSvi16gpr + 2898U, // INSvi16lane + 1U, // INSvi32gpr + 2898U, // INSvi32lane + 1U, // INSvi64gpr + 2899U, // INSvi64lane + 1U, // INSvi8gpr + 2899U, // INSvi8lane + 0U, // ISB + 837U, // LASTA_RPZ_B + 901U, // LASTA_RPZ_D + 2245U, // LASTA_RPZ_H + 1029U, // LASTA_RPZ_S + 837U, // LASTA_VPZ_B + 901U, // LASTA_VPZ_D + 2245U, // LASTA_VPZ_H + 1029U, // LASTA_VPZ_S + 837U, // LASTB_RPZ_B + 901U, // LASTB_RPZ_D + 2245U, // LASTB_RPZ_H + 1029U, // LASTB_RPZ_S + 837U, // LASTB_VPZ_B + 901U, // LASTB_VPZ_D + 2245U, // LASTB_VPZ_H + 1029U, // LASTB_VPZ_S + 4357U, // LD1B + 4357U, // LD1B_D + 256261U, // LD1B_D_IMM_REAL + 4357U, // LD1B_H + 256261U, // LD1B_H_IMM_REAL + 256261U, // LD1B_IMM_REAL + 4357U, // LD1B_S + 256261U, // LD1B_S_IMM_REAL + 4421U, // LD1D + 256261U, // LD1D_IMM_REAL + 0U, // LD1Fourv16b + 0U, // LD1Fourv16b_POST + 0U, // LD1Fourv1d + 0U, // LD1Fourv1d_POST + 0U, // LD1Fourv2d + 0U, // LD1Fourv2d_POST + 0U, // LD1Fourv2s + 0U, // LD1Fourv2s_POST + 0U, // LD1Fourv4h + 0U, // LD1Fourv4h_POST + 0U, // LD1Fourv4s + 0U, // LD1Fourv4s_POST + 0U, // LD1Fourv8b + 0U, // LD1Fourv8b_POST + 0U, // LD1Fourv8h + 0U, // LD1Fourv8h_POST + 4485U, // LD1H + 4485U, // LD1H_D + 256261U, // LD1H_D_IMM_REAL + 256261U, // LD1H_IMM_REAL + 4485U, // LD1H_S + 256261U, // LD1H_S_IMM_REAL + 0U, // LD1Onev16b + 0U, // LD1Onev16b_POST + 0U, // LD1Onev1d + 0U, // LD1Onev1d_POST + 0U, // LD1Onev2d + 0U, // LD1Onev2d_POST + 0U, // LD1Onev2s + 0U, // LD1Onev2s_POST + 0U, // LD1Onev4h + 0U, // LD1Onev4h_POST + 0U, // LD1Onev4s + 0U, // LD1Onev4s_POST + 0U, // LD1Onev8b + 0U, // LD1Onev8b_POST + 0U, // LD1Onev8h + 0U, // LD1Onev8h_POST + 116997U, // LD1RB_D_IMM + 116997U, // LD1RB_H_IMM + 116997U, // LD1RB_IMM + 116997U, // LD1RB_S_IMM + 119237U, // LD1RD_IMM + 119301U, // LD1RH_D_IMM + 119301U, // LD1RH_IMM + 119301U, // LD1RH_S_IMM + 4357U, // LD1RQ_B + 4677U, // LD1RQ_B_IMM + 4421U, // LD1RQ_D + 4677U, // LD1RQ_D_IMM + 4485U, // LD1RQ_H + 4677U, // LD1RQ_H_IMM + 4741U, // LD1RQ_W + 4677U, // LD1RQ_W_IMM + 116997U, // LD1RSB_D_IMM + 116997U, // LD1RSB_H_IMM + 116997U, // LD1RSB_S_IMM + 119301U, // LD1RSH_D_IMM + 119301U, // LD1RSH_S_IMM + 119493U, // LD1RSW_IMM + 119493U, // LD1RW_D_IMM + 119493U, // LD1RW_IMM + 0U, // LD1Rv16b + 0U, // LD1Rv16b_POST + 0U, // LD1Rv1d + 0U, // LD1Rv1d_POST + 0U, // LD1Rv2d + 0U, // LD1Rv2d_POST + 0U, // LD1Rv2s + 0U, // LD1Rv2s_POST + 0U, // LD1Rv4h + 0U, // LD1Rv4h_POST + 0U, // LD1Rv4s + 0U, // LD1Rv4s_POST + 0U, // LD1Rv8b + 0U, // LD1Rv8b_POST + 0U, // LD1Rv8h + 0U, // LD1Rv8h_POST + 4357U, // LD1SB_D + 256261U, // LD1SB_D_IMM_REAL + 4357U, // LD1SB_H + 256261U, // LD1SB_H_IMM_REAL + 4357U, // LD1SB_S + 256261U, // LD1SB_S_IMM_REAL + 4485U, // LD1SH_D + 256261U, // LD1SH_D_IMM_REAL + 4485U, // LD1SH_S + 256261U, // LD1SH_S_IMM_REAL + 4741U, // LD1SW_D + 256261U, // LD1SW_D_IMM_REAL + 0U, // LD1Threev16b + 0U, // LD1Threev16b_POST + 0U, // LD1Threev1d + 0U, // LD1Threev1d_POST + 0U, // LD1Threev2d + 0U, // LD1Threev2d_POST + 0U, // LD1Threev2s + 0U, // LD1Threev2s_POST + 0U, // LD1Threev4h + 0U, // LD1Threev4h_POST + 0U, // LD1Threev4s + 0U, // LD1Threev4s_POST + 0U, // LD1Threev8b + 0U, // LD1Threev8b_POST + 0U, // LD1Threev8h + 0U, // LD1Threev8h_POST + 0U, // LD1Twov16b + 0U, // LD1Twov16b_POST + 0U, // LD1Twov1d + 0U, // LD1Twov1d_POST + 0U, // LD1Twov2d + 0U, // LD1Twov2d_POST + 0U, // LD1Twov2s + 0U, // LD1Twov2s_POST + 0U, // LD1Twov4h + 0U, // LD1Twov4h_POST + 0U, // LD1Twov4s + 0U, // LD1Twov4s_POST + 0U, // LD1Twov8b + 0U, // LD1Twov8b_POST + 0U, // LD1Twov8h + 0U, // LD1Twov8h_POST + 4741U, // LD1W + 4741U, // LD1W_D + 256261U, // LD1W_D_IMM_REAL + 256261U, // LD1W_IMM_REAL + 0U, // LD1i16 + 0U, // LD1i16_POST + 0U, // LD1i32 + 0U, // LD1i32_POST + 0U, // LD1i64 + 0U, // LD1i64_POST + 0U, // LD1i8 + 0U, // LD1i8_POST + 4357U, // LD2B + 258565U, // LD2B_IMM + 4421U, // LD2D + 258565U, // LD2D_IMM + 4485U, // LD2H + 258565U, // LD2H_IMM + 0U, // LD2Rv16b + 0U, // LD2Rv16b_POST + 0U, // LD2Rv1d + 0U, // LD2Rv1d_POST + 0U, // LD2Rv2d + 0U, // LD2Rv2d_POST + 0U, // LD2Rv2s + 0U, // LD2Rv2s_POST + 0U, // LD2Rv4h + 0U, // LD2Rv4h_POST + 0U, // LD2Rv4s + 0U, // LD2Rv4s_POST + 0U, // LD2Rv8b + 0U, // LD2Rv8b_POST + 0U, // LD2Rv8h + 0U, // LD2Rv8h_POST + 0U, // LD2Twov16b + 0U, // LD2Twov16b_POST + 0U, // LD2Twov2d + 0U, // LD2Twov2d_POST + 0U, // LD2Twov2s + 0U, // LD2Twov2s_POST + 0U, // LD2Twov4h + 0U, // LD2Twov4h_POST + 0U, // LD2Twov4s + 0U, // LD2Twov4s_POST + 0U, // LD2Twov8b + 0U, // LD2Twov8b_POST + 0U, // LD2Twov8h + 0U, // LD2Twov8h_POST + 4741U, // LD2W + 258565U, // LD2W_IMM + 0U, // LD2i16 + 0U, // LD2i16_POST + 0U, // LD2i32 + 0U, // LD2i32_POST + 0U, // LD2i64 + 0U, // LD2i64_POST + 0U, // LD2i8 + 0U, // LD2i8_POST + 4357U, // LD3B + 4869U, // LD3B_IMM + 4421U, // LD3D + 4869U, // LD3D_IMM + 4485U, // LD3H + 4869U, // LD3H_IMM + 0U, // LD3Rv16b + 0U, // LD3Rv16b_POST + 0U, // LD3Rv1d + 0U, // LD3Rv1d_POST + 0U, // LD3Rv2d + 0U, // LD3Rv2d_POST + 0U, // LD3Rv2s + 0U, // LD3Rv2s_POST + 0U, // LD3Rv4h + 0U, // LD3Rv4h_POST + 0U, // LD3Rv4s + 0U, // LD3Rv4s_POST + 0U, // LD3Rv8b + 0U, // LD3Rv8b_POST + 0U, // LD3Rv8h + 0U, // LD3Rv8h_POST + 0U, // LD3Threev16b + 0U, // LD3Threev16b_POST + 0U, // LD3Threev2d + 0U, // LD3Threev2d_POST + 0U, // LD3Threev2s + 0U, // LD3Threev2s_POST + 0U, // LD3Threev4h + 0U, // LD3Threev4h_POST + 0U, // LD3Threev4s + 0U, // LD3Threev4s_POST + 0U, // LD3Threev8b + 0U, // LD3Threev8b_POST + 0U, // LD3Threev8h + 0U, // LD3Threev8h_POST + 4741U, // LD3W + 4869U, // LD3W_IMM + 0U, // LD3i16 + 0U, // LD3i16_POST + 0U, // LD3i32 + 0U, // LD3i32_POST + 0U, // LD3i64 + 0U, // LD3i64_POST + 0U, // LD3i8 + 0U, // LD3i8_POST + 4357U, // LD4B + 258757U, // LD4B_IMM + 4421U, // LD4D + 258757U, // LD4D_IMM + 0U, // LD4Fourv16b + 0U, // LD4Fourv16b_POST + 0U, // LD4Fourv2d + 0U, // LD4Fourv2d_POST + 0U, // LD4Fourv2s + 0U, // LD4Fourv2s_POST + 0U, // LD4Fourv4h + 0U, // LD4Fourv4h_POST + 0U, // LD4Fourv4s + 0U, // LD4Fourv4s_POST + 0U, // LD4Fourv8b + 0U, // LD4Fourv8b_POST + 0U, // LD4Fourv8h + 0U, // LD4Fourv8h_POST + 4485U, // LD4H + 258757U, // LD4H_IMM + 0U, // LD4Rv16b + 0U, // LD4Rv16b_POST + 0U, // LD4Rv1d + 0U, // LD4Rv1d_POST + 0U, // LD4Rv2d + 0U, // LD4Rv2d_POST + 0U, // LD4Rv2s + 0U, // LD4Rv2s_POST + 0U, // LD4Rv4h + 0U, // LD4Rv4h_POST + 0U, // LD4Rv4s + 0U, // LD4Rv4s_POST + 0U, // LD4Rv8b + 0U, // LD4Rv8b_POST + 0U, // LD4Rv8h + 0U, // LD4Rv8h_POST + 4741U, // LD4W + 258757U, // LD4W_IMM + 0U, // LD4i16 + 0U, // LD4i16_POST + 0U, // LD4i32 + 0U, // LD4i32_POST + 0U, // LD4i64 + 0U, // LD4i64_POST + 0U, // LD4i8 + 0U, // LD4i8_POST + 0U, // LDADDAB + 0U, // LDADDAH + 0U, // LDADDALB + 0U, // LDADDALH + 0U, // LDADDALW + 0U, // LDADDALX + 0U, // LDADDAW + 0U, // LDADDAX + 0U, // LDADDB + 0U, // LDADDH + 0U, // LDADDLB + 0U, // LDADDLH + 0U, // LDADDLW + 0U, // LDADDLX + 0U, // LDADDW + 0U, // LDADDX + 27U, // LDAPRB + 27U, // LDAPRH + 27U, // LDAPRW + 27U, // LDAPRX + 114949U, // LDAPURBi + 114949U, // LDAPURHi + 114949U, // LDAPURSBWi + 114949U, // LDAPURSBXi + 114949U, // LDAPURSHWi + 114949U, // LDAPURSHXi + 114949U, // LDAPURSWi + 114949U, // LDAPURXi + 114949U, // LDAPURi + 27U, // LDARB + 27U, // LDARH + 27U, // LDARW + 27U, // LDARX + 114955U, // LDAXPW + 114955U, // LDAXPX + 27U, // LDAXRB + 27U, // LDAXRH + 27U, // LDAXRW + 27U, // LDAXRX + 0U, // LDCLRAB + 0U, // LDCLRAH + 0U, // LDCLRALB + 0U, // LDCLRALH + 0U, // LDCLRALW + 0U, // LDCLRALX + 0U, // LDCLRAW + 0U, // LDCLRAX + 0U, // LDCLRB + 0U, // LDCLRH + 0U, // LDCLRLB + 0U, // LDCLRLH + 0U, // LDCLRLW + 0U, // LDCLRLX + 0U, // LDCLRW + 0U, // LDCLRX + 0U, // LDEORAB + 0U, // LDEORAH + 0U, // LDEORALB + 0U, // LDEORALH + 0U, // LDEORALW + 0U, // LDEORALX + 0U, // LDEORAW + 0U, // LDEORAX + 0U, // LDEORB + 0U, // LDEORH + 0U, // LDEORLB + 0U, // LDEORLH + 0U, // LDEORLW + 0U, // LDEORLX + 0U, // LDEORW + 0U, // LDEORX + 4357U, // LDFF1B_D_REAL + 4357U, // LDFF1B_H_REAL + 4357U, // LDFF1B_REAL + 4357U, // LDFF1B_S_REAL + 4421U, // LDFF1D_REAL + 4485U, // LDFF1H_D_REAL + 4485U, // LDFF1H_REAL + 4485U, // LDFF1H_S_REAL + 4357U, // LDFF1SB_D_REAL + 4357U, // LDFF1SB_H_REAL + 4357U, // LDFF1SB_S_REAL + 4485U, // LDFF1SH_D_REAL + 4485U, // LDFF1SH_S_REAL + 4741U, // LDFF1SW_D_REAL + 4741U, // LDFF1W_D_REAL + 4741U, // LDFF1W_REAL + 27U, // LDLARB + 27U, // LDLARH + 27U, // LDLARW + 27U, // LDLARX + 256261U, // LDNF1B_D_IMM_REAL + 256261U, // LDNF1B_H_IMM_REAL + 256261U, // LDNF1B_IMM_REAL + 256261U, // LDNF1B_S_IMM_REAL + 256261U, // LDNF1D_IMM_REAL + 256261U, // LDNF1H_D_IMM_REAL + 256261U, // LDNF1H_IMM_REAL + 256261U, // LDNF1H_S_IMM_REAL + 256261U, // LDNF1SB_D_IMM_REAL + 256261U, // LDNF1SB_H_IMM_REAL + 256261U, // LDNF1SB_S_IMM_REAL + 256261U, // LDNF1SH_D_IMM_REAL + 256261U, // LDNF1SH_S_IMM_REAL + 256261U, // LDNF1SW_D_IMM_REAL + 256261U, // LDNF1W_D_IMM_REAL + 256261U, // LDNF1W_IMM_REAL + 11084043U, // LDNPDi + 11608331U, // LDNPQi + 12132619U, // LDNPSi + 12132619U, // LDNPWi + 11084043U, // LDNPXi + 256261U, // LDNT1B_ZRI + 4357U, // LDNT1B_ZRR + 256261U, // LDNT1D_ZRI + 4421U, // LDNT1D_ZRR + 256261U, // LDNT1H_ZRI + 4485U, // LDNT1H_ZRR + 256261U, // LDNT1W_ZRI + 4741U, // LDNT1W_ZRR + 11084043U, // LDPDi + 12847371U, // LDPDpost + 180431115U, // LDPDpre + 11608331U, // LDPQi + 13371659U, // LDPQpost + 180955403U, // LDPQpre + 12132619U, // LDPSWi + 13895947U, // LDPSWpost + 181479691U, // LDPSWpre + 12132619U, // LDPSi + 13895947U, // LDPSpost + 181479691U, // LDPSpre + 12132619U, // LDPWi + 13895947U, // LDPWpost + 181479691U, // LDPWpre + 11084043U, // LDPXi + 12847371U, // LDPXpost + 180431115U, // LDPXpre + 4933U, // LDRAAindexed + 274885U, // LDRAAwriteback + 4933U, // LDRABindexed + 274885U, // LDRABwriteback + 28U, // LDRBBpost + 272645U, // LDRBBpre + 14229765U, // LDRBBroW + 14754053U, // LDRBBroX + 4997U, // LDRBBui + 28U, // LDRBpost + 272645U, // LDRBpre + 14229765U, // LDRBroW + 14754053U, // LDRBroX + 4997U, // LDRBui + 0U, // LDRDl + 28U, // LDRDpost + 272645U, // LDRDpre + 15278341U, // LDRDroW + 15802629U, // LDRDroX + 5061U, // LDRDui + 28U, // LDRHHpost + 272645U, // LDRHHpre + 16326917U, // LDRHHroW + 16851205U, // LDRHHroX + 5125U, // LDRHHui + 28U, // LDRHpost + 272645U, // LDRHpre + 16326917U, // LDRHroW + 16851205U, // LDRHroX + 5125U, // LDRHui + 0U, // LDRQl + 28U, // LDRQpost + 272645U, // LDRQpre + 17375493U, // LDRQroW + 17899781U, // LDRQroX + 5189U, // LDRQui + 28U, // LDRSBWpost + 272645U, // LDRSBWpre + 14229765U, // LDRSBWroW + 14754053U, // LDRSBWroX + 4997U, // LDRSBWui + 28U, // LDRSBXpost + 272645U, // LDRSBXpre + 14229765U, // LDRSBXroW + 14754053U, // LDRSBXroX + 4997U, // LDRSBXui + 28U, // LDRSHWpost + 272645U, // LDRSHWpre + 16326917U, // LDRSHWroW + 16851205U, // LDRSHWroX + 5125U, // LDRSHWui + 28U, // LDRSHXpost + 272645U, // LDRSHXpre + 16326917U, // LDRSHXroW + 16851205U, // LDRSHXroX + 5125U, // LDRSHXui + 0U, // LDRSWl + 28U, // LDRSWpost + 272645U, // LDRSWpre + 18424069U, // LDRSWroW + 18948357U, // LDRSWroX + 5253U, // LDRSWui + 0U, // LDRSl + 28U, // LDRSpost + 272645U, // LDRSpre + 18424069U, // LDRSroW + 18948357U, // LDRSroX + 5253U, // LDRSui + 0U, // LDRWl + 28U, // LDRWpost + 272645U, // LDRWpre + 18424069U, // LDRWroW + 18948357U, // LDRWroX + 5253U, // LDRWui + 0U, // LDRXl + 28U, // LDRXpost + 272645U, // LDRXpre + 15278341U, // LDRXroW + 15802629U, // LDRXroX + 5061U, // LDRXui + 254213U, // LDR_PXI + 254213U, // LDR_ZXI + 0U, // LDSETAB + 0U, // LDSETAH + 0U, // LDSETALB + 0U, // LDSETALH + 0U, // LDSETALW + 0U, // LDSETALX + 0U, // LDSETAW + 0U, // LDSETAX + 0U, // LDSETB + 0U, // LDSETH + 0U, // LDSETLB + 0U, // LDSETLH + 0U, // LDSETLW + 0U, // LDSETLX + 0U, // LDSETW + 0U, // LDSETX + 0U, // LDSMAXAB + 0U, // LDSMAXAH + 0U, // LDSMAXALB + 0U, // LDSMAXALH + 0U, // LDSMAXALW + 0U, // LDSMAXALX + 0U, // LDSMAXAW + 0U, // LDSMAXAX + 0U, // LDSMAXB + 0U, // LDSMAXH + 0U, // LDSMAXLB + 0U, // LDSMAXLH + 0U, // LDSMAXLW + 0U, // LDSMAXLX + 0U, // LDSMAXW + 0U, // LDSMAXX + 0U, // LDSMINAB + 0U, // LDSMINAH + 0U, // LDSMINALB + 0U, // LDSMINALH + 0U, // LDSMINALW + 0U, // LDSMINALX + 0U, // LDSMINAW + 0U, // LDSMINAX + 0U, // LDSMINB + 0U, // LDSMINH + 0U, // LDSMINLB + 0U, // LDSMINLH + 0U, // LDSMINLW + 0U, // LDSMINLX + 0U, // LDSMINW + 0U, // LDSMINX + 114949U, // LDTRBi + 114949U, // LDTRHi + 114949U, // LDTRSBWi + 114949U, // LDTRSBXi + 114949U, // LDTRSHWi + 114949U, // LDTRSHXi + 114949U, // LDTRSWi + 114949U, // LDTRWi + 114949U, // LDTRXi + 0U, // LDUMAXAB + 0U, // LDUMAXAH + 0U, // LDUMAXALB + 0U, // LDUMAXALH + 0U, // LDUMAXALW + 0U, // LDUMAXALX + 0U, // LDUMAXAW + 0U, // LDUMAXAX + 0U, // LDUMAXB + 0U, // LDUMAXH + 0U, // LDUMAXLB + 0U, // LDUMAXLH + 0U, // LDUMAXLW + 0U, // LDUMAXLX + 0U, // LDUMAXW + 0U, // LDUMAXX + 0U, // LDUMINAB + 0U, // LDUMINAH + 0U, // LDUMINALB + 0U, // LDUMINALH + 0U, // LDUMINALW + 0U, // LDUMINALX + 0U, // LDUMINAW + 0U, // LDUMINAX + 0U, // LDUMINB + 0U, // LDUMINH + 0U, // LDUMINLB + 0U, // LDUMINLH + 0U, // LDUMINLW + 0U, // LDUMINLX + 0U, // LDUMINW + 0U, // LDUMINX + 114949U, // LDURBBi + 114949U, // LDURBi + 114949U, // LDURDi + 114949U, // LDURHHi + 114949U, // LDURHi + 114949U, // LDURQi + 114949U, // LDURSBWi + 114949U, // LDURSBXi + 114949U, // LDURSHWi + 114949U, // LDURSHXi + 114949U, // LDURSWi + 114949U, // LDURSi + 114949U, // LDURWi + 114949U, // LDURXi + 114955U, // LDXPW + 114955U, // LDXPX + 27U, // LDXRB + 27U, // LDXRH + 27U, // LDXRW + 27U, // LDXRX + 0U, // LOADgot + 74560U, // LSLR_ZPmZ_B + 598912U, // LSLR_ZPmZ_D + 1131465U, // LSLR_ZPmZ_H + 1647616U, // LSLR_ZPmZ_S + 261U, // LSLVWr + 261U, // LSLVXr + 598848U, // LSL_WIDE_ZPmZ_B + 99273U, // LSL_WIDE_ZPmZ_H + 599040U, // LSL_WIDE_ZPmZ_S + 901U, // LSL_WIDE_ZZZ_B + 10U, // LSL_WIDE_ZZZ_H + 901U, // LSL_WIDE_ZZZ_S + 2171712U, // LSL_ZPmI_B + 2171776U, // LSL_ZPmI_D + 91081U, // LSL_ZPmI_H + 2171904U, // LSL_ZPmI_S + 74560U, // LSL_ZPmZ_B + 598912U, // LSL_ZPmZ_D + 1131465U, // LSL_ZPmZ_H + 1647616U, // LSL_ZPmZ_S + 261U, // LSL_ZZI_B + 261U, // LSL_ZZI_D + 11U, // LSL_ZZI_H + 261U, // LSL_ZZI_S + 74560U, // LSRR_ZPmZ_B + 598912U, // LSRR_ZPmZ_D + 1131465U, // LSRR_ZPmZ_H + 1647616U, // LSRR_ZPmZ_S + 261U, // LSRVWr + 261U, // LSRVXr + 598848U, // LSR_WIDE_ZPmZ_B + 99273U, // LSR_WIDE_ZPmZ_H + 599040U, // LSR_WIDE_ZPmZ_S + 901U, // LSR_WIDE_ZZZ_B + 10U, // LSR_WIDE_ZZZ_H + 901U, // LSR_WIDE_ZZZ_S + 2171712U, // LSR_ZPmI_B + 2171776U, // LSR_ZPmI_D + 91081U, // LSR_ZPmI_H + 2171904U, // LSR_ZPmI_S + 74560U, // LSR_ZPmZ_B + 598912U, // LSR_ZPmZ_D + 1131465U, // LSR_ZPmZ_H + 1647616U, // LSR_ZPmZ_S + 261U, // LSR_ZZI_B + 261U, // LSR_ZZI_D + 11U, // LSR_ZZI_H + 261U, // LSR_ZZI_S + 2171141U, // MADDWrrr + 2171141U, // MADDXrrr + 19472384U, // MAD_ZPmZZ_B + 6889536U, // MAD_ZPmZZ_D + 1246144U, // MAD_ZPmZZ_H + 7413952U, // MAD_ZPmZZ_S + 19472384U, // MLA_ZPmZZ_B + 6889536U, // MLA_ZPmZZ_D + 1246144U, // MLA_ZPmZZ_H + 7413952U, // MLA_ZPmZZ_S + 33159U, // MLAv16i8 + 41351U, // MLAv2i32 + 9126279U, // MLAv2i32_indexed + 49544U, // MLAv4i16 + 9118088U, // MLAv4i16_indexed + 16774U, // MLAv4i32 + 9126278U, // MLAv4i32_indexed + 24966U, // MLAv8i16 + 9118086U, // MLAv8i16_indexed + 57736U, // MLAv8i8 + 19472384U, // MLS_ZPmZZ_B + 6889536U, // MLS_ZPmZZ_D + 1246144U, // MLS_ZPmZZ_H + 7413952U, // MLS_ZPmZZ_S + 33159U, // MLSv16i8 + 41351U, // MLSv2i32 + 9126279U, // MLSv2i32_indexed + 49544U, // MLSv4i16 + 9118088U, // MLSv4i16_indexed + 16774U, // MLSv4i32 + 9126278U, // MLSv4i32_indexed + 24966U, // MLSv8i16 + 9118086U, // MLSv8i16_indexed + 57736U, // MLSv8i8 + 0U, // MOVID + 1U, // MOVIv16b_ns + 0U, // MOVIv2d_ns + 28U, // MOVIv2i32 + 28U, // MOVIv2s_msl + 28U, // MOVIv4i16 + 28U, // MOVIv4i32 + 28U, // MOVIv4s_msl + 1U, // MOVIv8b_ns + 28U, // MOVIv8i16 + 0U, // MOVKWi + 0U, // MOVKXi + 28U, // MOVNWi + 28U, // MOVNXi + 0U, // MOVPRFX_ZPmZ_B + 64U, // MOVPRFX_ZPmZ_D + 128U, // MOVPRFX_ZPmZ_H + 192U, // MOVPRFX_ZPmZ_S + 842U, // MOVPRFX_ZPzZ_B + 906U, // MOVPRFX_ZPzZ_D + 137U, // MOVPRFX_ZPzZ_H + 1034U, // MOVPRFX_ZPzZ_S + 1U, // MOVPRFX_ZZ + 28U, // MOVZWi + 28U, // MOVZXi + 0U, // MOVaddr + 0U, // MOVaddrBA + 0U, // MOVaddrCP + 0U, // MOVaddrEXT + 0U, // MOVaddrJT + 0U, // MOVaddrTLS + 0U, // MOVbaseTLS + 0U, // MOVi32imm + 0U, // MOVi64imm + 0U, // MRS + 19472384U, // MSB_ZPmZZ_B + 6889536U, // MSB_ZPmZZ_D + 1246144U, // MSB_ZPmZZ_H + 7413952U, // MSB_ZPmZZ_S + 0U, // MSR + 0U, // MSRpstateImm1 + 0U, // MSRpstateImm4 + 2171141U, // MSUBWrrr + 2171141U, // MSUBXrrr + 261U, // MUL_ZI_B + 261U, // MUL_ZI_D + 11U, // MUL_ZI_H + 261U, // MUL_ZI_S + 74560U, // MUL_ZPmZ_B + 598912U, // MUL_ZPmZ_D + 1131465U, // MUL_ZPmZ_H + 1647616U, // MUL_ZPmZ_S + 33095U, // MULv16i8 + 41287U, // MULv2i32 + 10174791U, // MULv2i32_indexed + 49480U, // MULv4i16 + 10166600U, // MULv4i16_indexed + 16710U, // MULv4i32 + 10174790U, // MULv4i32_indexed + 24902U, // MULv8i16 + 10166598U, // MULv8i16_indexed + 57672U, // MULv8i8 + 28U, // MVNIv2i32 + 28U, // MVNIv2s_msl + 28U, // MVNIv4i16 + 28U, // MVNIv4i32 + 28U, // MVNIv4s_msl + 28U, // MVNIv8i16 + 74570U, // NANDS_PPzPP + 74570U, // NAND_PPzPP + 0U, // NEG_ZPmZ_B + 64U, // NEG_ZPmZ_D + 128U, // NEG_ZPmZ_H + 192U, // NEG_ZPmZ_S + 1U, // NEGv16i8 + 1U, // NEGv1i64 + 2U, // NEGv2i32 + 2U, // NEGv2i64 + 3U, // NEGv4i16 + 3U, // NEGv4i32 + 4U, // NEGv8i16 + 4U, // NEGv8i8 + 74570U, // NORS_PPzPP + 74570U, // NOR_PPzPP + 0U, // NOT_ZPmZ_B + 64U, // NOT_ZPmZ_D + 128U, // NOT_ZPmZ_H + 192U, // NOT_ZPmZ_S + 1U, // NOTv16i8 + 4U, // NOTv8i8 + 74570U, // ORNS_PPzPP + 0U, // ORNWrr + 517U, // ORNWrs + 0U, // ORNXrr + 517U, // ORNXrs + 74570U, // ORN_PPzPP + 33095U, // ORNv16i8 + 57672U, // ORNv8i8 + 74570U, // ORRS_PPzPP + 2117U, // ORRWri + 0U, // ORRWrr + 517U, // ORRWrs + 2181U, // ORRXri + 0U, // ORRXrr + 517U, // ORRXrs + 74570U, // ORR_PPzPP + 2181U, // ORR_ZI + 74560U, // ORR_ZPmZ_B + 598912U, // ORR_ZPmZ_D + 1131465U, // ORR_ZPmZ_H + 1647616U, // ORR_ZPmZ_S + 901U, // ORR_ZZZ + 33095U, // ORRv16i8 + 0U, // ORRv2i32 + 0U, // ORRv4i16 + 0U, // ORRv4i32 + 0U, // ORRv8i16 + 57672U, // ORRv8i8 + 837U, // ORV_VPZ_B + 901U, // ORV_VPZ_D + 2245U, // ORV_VPZ_H + 1029U, // ORV_VPZ_S + 1U, // PACDA + 1U, // PACDB + 0U, // PACDZA + 0U, // PACDZB + 261U, // PACGA + 1U, // PACIA + 0U, // PACIA1716 + 0U, // PACIASP + 0U, // PACIAZ + 1U, // PACIB + 0U, // PACIB1716 + 0U, // PACIBSP + 0U, // PACIBZ + 0U, // PACIZA + 0U, // PACIZB + 0U, // PFALSE + 33095U, // PMULLv16i8 + 0U, // PMULLv1i64 + 0U, // PMULLv2i64 + 57672U, // PMULLv8i8 + 33095U, // PMULv16i8 + 57672U, // PMULv8i8 + 837U, // PNEXT_B + 901U, // PNEXT_D + 137U, // PNEXT_H + 1029U, // PNEXT_S + 27U, // PRFB_D_PZI + 29U, // PRFB_D_SCALED + 29U, // PRFB_D_SXTW_SCALED + 30U, // PRFB_D_UXTW_SCALED + 5329U, // PRFB_PRI + 30U, // PRFB_PRR + 27U, // PRFB_S_PZI + 31U, // PRFB_S_SXTW_SCALED + 31U, // PRFB_S_UXTW_SCALED + 0U, // PRFD_D_PZI + 32U, // PRFD_D_SCALED + 32U, // PRFD_D_SXTW_SCALED + 33U, // PRFD_D_UXTW_SCALED + 5329U, // PRFD_PRI + 33U, // PRFD_PRR + 0U, // PRFD_S_PZI + 34U, // PRFD_S_SXTW_SCALED + 34U, // PRFD_S_UXTW_SCALED + 0U, // PRFH_D_PZI + 35U, // PRFH_D_SCALED + 35U, // PRFH_D_SXTW_SCALED + 36U, // PRFH_D_UXTW_SCALED + 5329U, // PRFH_PRI + 36U, // PRFH_PRR + 0U, // PRFH_S_PZI + 37U, // PRFH_S_SXTW_SCALED + 37U, // PRFH_S_UXTW_SCALED + 0U, // PRFMl + 15278341U, // PRFMroW + 15802629U, // PRFMroX + 5061U, // PRFMui + 38U, // PRFS_PRR + 114949U, // PRFUMi + 0U, // PRFW_D_PZI + 38U, // PRFW_D_SCALED + 39U, // PRFW_D_SXTW_SCALED + 39U, // PRFW_D_UXTW_SCALED + 5329U, // PRFW_PRI + 0U, // PRFW_S_PZI + 40U, // PRFW_S_SXTW_SCALED + 40U, // PRFW_S_UXTW_SCALED + 1U, // PTEST_PP + 1U, // PTRUES_B + 1U, // PTRUES_D + 0U, // PTRUES_H + 1U, // PTRUES_S + 1U, // PTRUE_B + 1U, // PTRUE_D + 0U, // PTRUE_H + 1U, // PTRUE_S + 0U, // PUNPKHI_PP + 0U, // PUNPKLO_PP + 8517U, // RADDHNv2i64_v2i32 + 8581U, // RADDHNv2i64_v4i32 + 16710U, // RADDHNv4i32_v4i16 + 16774U, // RADDHNv4i32_v8i16 + 24966U, // RADDHNv8i16_v16i8 + 24902U, // RADDHNv8i16_v8i8 + 8517U, // RAX1 + 1U, // RBITWr + 1U, // RBITXr + 0U, // RBIT_ZPmZ_B + 64U, // RBIT_ZPmZ_D + 128U, // RBIT_ZPmZ_H + 192U, // RBIT_ZPmZ_S + 1U, // RBITv16i8 + 4U, // RBITv8i8 + 41U, // RDFFRS_PPz + 0U, // RDFFR_P + 41U, // RDFFR_PPz + 1U, // RDVLI_XI + 0U, // RET + 0U, // RETAA + 0U, // RETAB + 0U, // RET_ReallyLR + 1U, // REV16Wr + 1U, // REV16Xr + 1U, // REV16v16i8 + 4U, // REV16v8i8 + 1U, // REV32Xr + 1U, // REV32v16i8 + 3U, // REV32v4i16 + 4U, // REV32v8i16 + 4U, // REV32v8i8 + 1U, // REV64v16i8 + 2U, // REV64v2i32 + 3U, // REV64v4i16 + 3U, // REV64v4i32 + 4U, // REV64v8i16 + 4U, // REV64v8i8 + 64U, // REVB_ZPmZ_D + 128U, // REVB_ZPmZ_H + 192U, // REVB_ZPmZ_S + 64U, // REVH_ZPmZ_D + 192U, // REVH_ZPmZ_S + 64U, // REVW_ZPmZ_D + 1U, // REVWr + 1U, // REVXr + 1U, // REV_PP_B + 1U, // REV_PP_D + 0U, // REV_PP_H + 1U, // REV_PP_S + 1U, // REV_ZZ_B + 1U, // REV_ZZ_D + 0U, // REV_ZZ_H + 1U, // REV_ZZ_S + 261U, // RMIF + 261U, // RORVWr + 261U, // RORVXr + 2310U, // RSHRNv16i8_shift + 261U, // RSHRNv2i32_shift + 262U, // RSHRNv4i16_shift + 2309U, // RSHRNv4i32_shift + 2310U, // RSHRNv8i16_shift + 262U, // RSHRNv8i8_shift + 8517U, // RSUBHNv2i64_v2i32 + 8581U, // RSUBHNv2i64_v4i32 + 16710U, // RSUBHNv4i32_v4i16 + 16774U, // RSUBHNv4i32_v8i16 + 24966U, // RSUBHNv8i16_v16i8 + 24902U, // RSUBHNv8i16_v8i8 + 33159U, // SABALv16i8_v8i16 + 41351U, // SABALv2i32_v2i64 + 49544U, // SABALv4i16_v4i32 + 16774U, // SABALv4i32_v2i64 + 24966U, // SABALv8i16_v4i32 + 57736U, // SABALv8i8_v8i16 + 33159U, // SABAv16i8 + 41351U, // SABAv2i32 + 49544U, // SABAv4i16 + 16774U, // SABAv4i32 + 24966U, // SABAv8i16 + 57736U, // SABAv8i8 + 33095U, // SABDLv16i8_v8i16 + 41287U, // SABDLv2i32_v2i64 + 49480U, // SABDLv4i16_v4i32 + 16710U, // SABDLv4i32_v2i64 + 24902U, // SABDLv8i16_v4i32 + 57672U, // SABDLv8i8_v8i16 + 74560U, // SABD_ZPmZ_B + 598912U, // SABD_ZPmZ_D + 1131465U, // SABD_ZPmZ_H + 1647616U, // SABD_ZPmZ_S + 33095U, // SABDv16i8 + 41287U, // SABDv2i32 + 49480U, // SABDv4i16 + 16710U, // SABDv4i32 + 24902U, // SABDv8i16 + 57672U, // SABDv8i8 + 1U, // SADALPv16i8_v8i16 + 2U, // SADALPv2i32_v1i64 + 3U, // SADALPv4i16_v2i32 + 3U, // SADALPv4i32_v2i64 + 4U, // SADALPv8i16_v4i32 + 4U, // SADALPv8i8_v4i16 + 1U, // SADDLPv16i8_v8i16 + 2U, // SADDLPv2i32_v1i64 + 3U, // SADDLPv4i16_v2i32 + 3U, // SADDLPv4i32_v2i64 + 4U, // SADDLPv8i16_v4i32 + 4U, // SADDLPv8i8_v4i16 + 1U, // SADDLVv16i8v + 3U, // SADDLVv4i16v + 3U, // SADDLVv4i32v + 4U, // SADDLVv8i16v + 4U, // SADDLVv8i8v + 33095U, // SADDLv16i8_v8i16 + 41287U, // SADDLv2i32_v2i64 + 49480U, // SADDLv4i16_v4i32 + 16710U, // SADDLv4i32_v2i64 + 24902U, // SADDLv8i16_v4i32 + 57672U, // SADDLv8i8_v8i16 + 837U, // SADDV_VPZ_B + 2245U, // SADDV_VPZ_H + 1029U, // SADDV_VPZ_S + 33094U, // SADDWv16i8_v8i16 + 41285U, // SADDWv2i32_v2i64 + 49478U, // SADDWv4i16_v4i32 + 16709U, // SADDWv4i32_v2i64 + 24902U, // SADDWv8i16_v4i32 + 57670U, // SADDWv8i8_v8i16 + 261U, // SBCSWr + 261U, // SBCSXr + 261U, // SBCWr + 261U, // SBCXr + 2171141U, // SBFMWri + 2171141U, // SBFMXri + 261U, // SCVTFSWDri + 261U, // SCVTFSWHri + 261U, // SCVTFSWSri + 261U, // SCVTFSXDri + 261U, // SCVTFSXHri + 261U, // SCVTFSXSri + 1U, // SCVTFUWDri + 1U, // SCVTFUWHri + 1U, // SCVTFUWSri + 1U, // SCVTFUXDri + 1U, // SCVTFUXHri + 1U, // SCVTFUXSri + 64U, // SCVTF_ZPmZ_DtoD + 153U, // SCVTF_ZPmZ_DtoH + 64U, // SCVTF_ZPmZ_DtoS + 128U, // SCVTF_ZPmZ_HtoH + 192U, // SCVTF_ZPmZ_StoD + 152U, // SCVTF_ZPmZ_StoH + 192U, // SCVTF_ZPmZ_StoS + 261U, // SCVTFd + 261U, // SCVTFh + 261U, // SCVTFs + 1U, // SCVTFv1i16 + 1U, // SCVTFv1i32 + 1U, // SCVTFv1i64 + 2U, // SCVTFv2f32 + 2U, // SCVTFv2f64 + 263U, // SCVTFv2i32_shift + 261U, // SCVTFv2i64_shift + 3U, // SCVTFv4f16 + 3U, // SCVTFv4f32 + 264U, // SCVTFv4i16_shift + 262U, // SCVTFv4i32_shift + 4U, // SCVTFv8f16 + 262U, // SCVTFv8i16_shift + 598912U, // SDIVR_ZPmZ_D + 1647616U, // SDIVR_ZPmZ_S + 261U, // SDIVWr + 261U, // SDIVXr + 598912U, // SDIV_ZPmZ_D + 1647616U, // SDIV_ZPmZ_S + 41U, // SDOT_ZZZI_D + 41U, // SDOT_ZZZI_S + 1U, // SDOT_ZZZ_D + 1U, // SDOT_ZZZ_S + 278919U, // SDOTlanev16i8 + 278920U, // SDOTlanev8i8 + 33159U, // SDOTv16i8 + 57736U, // SDOTv8i8 + 74565U, // SEL_PPPP + 74565U, // SEL_ZPZZ_B + 598917U, // SEL_ZPZZ_D + 1131465U, // SEL_ZPZZ_H + 1647621U, // SEL_ZPZZ_S + 0U, // SETF16 + 0U, // SETF8 + 0U, // SETFFR + 16773U, // SHA1Crrr + 1U, // SHA1Hrr + 16773U, // SHA1Mrrr + 16773U, // SHA1Prrr + 16774U, // SHA1SU0rrr + 3U, // SHA1SU1rr + 16773U, // SHA256H2rrr + 16773U, // SHA256Hrrr + 3U, // SHA256SU0rr + 16774U, // SHA256SU1rrr + 8581U, // SHA512H + 8581U, // SHA512H2 + 2U, // SHA512SU0 + 8581U, // SHA512SU1 + 33095U, // SHADDv16i8 + 41287U, // SHADDv2i32 + 49480U, // SHADDv4i16 + 16710U, // SHADDv4i32 + 24902U, // SHADDv8i16 + 57672U, // SHADDv8i8 + 42U, // SHLLv16i8 + 42U, // SHLLv2i32 + 43U, // SHLLv4i16 + 43U, // SHLLv4i32 + 44U, // SHLLv8i16 + 44U, // SHLLv8i8 + 261U, // SHLd + 263U, // SHLv16i8_shift + 263U, // SHLv2i32_shift + 261U, // SHLv2i64_shift + 264U, // SHLv4i16_shift + 262U, // SHLv4i32_shift + 262U, // SHLv8i16_shift + 264U, // SHLv8i8_shift + 2310U, // SHRNv16i8_shift + 261U, // SHRNv2i32_shift + 262U, // SHRNv4i16_shift + 2309U, // SHRNv4i32_shift + 2310U, // SHRNv8i16_shift + 262U, // SHRNv8i8_shift + 33095U, // SHSUBv16i8 + 41287U, // SHSUBv2i32 + 49480U, // SHSUBv4i16 + 16710U, // SHSUBv4i32 + 24902U, // SHSUBv8i16 + 57672U, // SHSUBv8i8 + 2309U, // SLId + 2311U, // SLIv16i8_shift + 2311U, // SLIv2i32_shift + 2309U, // SLIv2i64_shift + 2312U, // SLIv4i16_shift + 2310U, // SLIv4i32_shift + 2310U, // SLIv8i16_shift + 2312U, // SLIv8i8_shift + 16774U, // SM3PARTW1 + 16774U, // SM3PARTW2 + 204120390U, // SM3SS1 + 9126278U, // SM3TT1A + 9126278U, // SM3TT1B + 9126278U, // SM3TT2A + 9126278U, // SM3TT2B + 3U, // SM4E + 16710U, // SM4ENCKEY + 2171141U, // SMADDLrrr + 33095U, // SMAXPv16i8 + 41287U, // SMAXPv2i32 + 49480U, // SMAXPv4i16 + 16710U, // SMAXPv4i32 + 24902U, // SMAXPv8i16 + 57672U, // SMAXPv8i8 + 837U, // SMAXV_VPZ_B + 901U, // SMAXV_VPZ_D + 2245U, // SMAXV_VPZ_H + 1029U, // SMAXV_VPZ_S + 1U, // SMAXVv16i8v + 3U, // SMAXVv4i16v + 3U, // SMAXVv4i32v + 4U, // SMAXVv8i16v + 4U, // SMAXVv8i8v + 261U, // SMAX_ZI_B + 261U, // SMAX_ZI_D + 11U, // SMAX_ZI_H + 261U, // SMAX_ZI_S + 74560U, // SMAX_ZPmZ_B + 598912U, // SMAX_ZPmZ_D + 1131465U, // SMAX_ZPmZ_H + 1647616U, // SMAX_ZPmZ_S + 33095U, // SMAXv16i8 + 41287U, // SMAXv2i32 + 49480U, // SMAXv4i16 + 16710U, // SMAXv4i32 + 24902U, // SMAXv8i16 + 57672U, // SMAXv8i8 + 0U, // SMC + 33095U, // SMINPv16i8 + 41287U, // SMINPv2i32 + 49480U, // SMINPv4i16 + 16710U, // SMINPv4i32 + 24902U, // SMINPv8i16 + 57672U, // SMINPv8i8 + 837U, // SMINV_VPZ_B + 901U, // SMINV_VPZ_D + 2245U, // SMINV_VPZ_H + 1029U, // SMINV_VPZ_S + 1U, // SMINVv16i8v + 3U, // SMINVv4i16v + 3U, // SMINVv4i32v + 4U, // SMINVv8i16v + 4U, // SMINVv8i8v + 261U, // SMIN_ZI_B + 261U, // SMIN_ZI_D + 11U, // SMIN_ZI_H + 261U, // SMIN_ZI_S + 74560U, // SMIN_ZPmZ_B + 598912U, // SMIN_ZPmZ_D + 1131465U, // SMIN_ZPmZ_H + 1647616U, // SMIN_ZPmZ_S + 33095U, // SMINv16i8 + 41287U, // SMINv2i32 + 49480U, // SMINv4i16 + 16710U, // SMINv4i32 + 24902U, // SMINv8i16 + 57672U, // SMINv8i8 + 33159U, // SMLALv16i8_v8i16 + 9126279U, // SMLALv2i32_indexed + 41351U, // SMLALv2i32_v2i64 + 9118088U, // SMLALv4i16_indexed + 49544U, // SMLALv4i16_v4i32 + 9126278U, // SMLALv4i32_indexed + 16774U, // SMLALv4i32_v2i64 + 9118086U, // SMLALv8i16_indexed + 24966U, // SMLALv8i16_v4i32 + 57736U, // SMLALv8i8_v8i16 + 33159U, // SMLSLv16i8_v8i16 + 9126279U, // SMLSLv2i32_indexed + 41351U, // SMLSLv2i32_v2i64 + 9118088U, // SMLSLv4i16_indexed + 49544U, // SMLSLv4i16_v4i32 + 9126278U, // SMLSLv4i32_indexed + 16774U, // SMLSLv4i32_v2i64 + 9118086U, // SMLSLv8i16_indexed + 24966U, // SMLSLv8i16_v4i32 + 57736U, // SMLSLv8i8_v8i16 + 2770U, // SMOVvi16to32 + 2770U, // SMOVvi16to64 + 2770U, // SMOVvi32to64 + 2771U, // SMOVvi8to32 + 2771U, // SMOVvi8to64 + 2171141U, // SMSUBLrrr + 74560U, // SMULH_ZPmZ_B + 598912U, // SMULH_ZPmZ_D + 1131465U, // SMULH_ZPmZ_H + 1647616U, // SMULH_ZPmZ_S + 261U, // SMULHrr + 33095U, // SMULLv16i8_v8i16 + 10174791U, // SMULLv2i32_indexed + 41287U, // SMULLv2i32_v2i64 + 10166600U, // SMULLv4i16_indexed + 49480U, // SMULLv4i16_v4i32 + 10174790U, // SMULLv4i32_indexed + 16710U, // SMULLv4i32_v2i64 + 10166598U, // SMULLv8i16_indexed + 24902U, // SMULLv8i16_v4i32 + 57672U, // SMULLv8i8_v8i16 + 74565U, // SPLICE_ZPZ_B + 598917U, // SPLICE_ZPZ_D + 1131465U, // SPLICE_ZPZ_H + 1647621U, // SPLICE_ZPZ_S + 1U, // SQABSv16i8 + 1U, // SQABSv1i16 + 1U, // SQABSv1i32 + 1U, // SQABSv1i64 + 1U, // SQABSv1i8 + 2U, // SQABSv2i32 + 2U, // SQABSv2i64 + 3U, // SQABSv4i16 + 3U, // SQABSv4i32 + 4U, // SQABSv8i16 + 4U, // SQABSv8i8 + 645U, // SQADD_ZI_B + 709U, // SQADD_ZI_D + 9U, // SQADD_ZI_H + 773U, // SQADD_ZI_S + 837U, // SQADD_ZZZ_B + 901U, // SQADD_ZZZ_D + 137U, // SQADD_ZZZ_H + 1029U, // SQADD_ZZZ_S + 33095U, // SQADDv16i8 + 261U, // SQADDv1i16 + 261U, // SQADDv1i32 + 261U, // SQADDv1i64 + 261U, // SQADDv1i8 + 41287U, // SQADDv2i32 + 8517U, // SQADDv2i64 + 49480U, // SQADDv4i16 + 16710U, // SQADDv4i32 + 24902U, // SQADDv8i16 + 57672U, // SQADDv8i8 + 0U, // SQDECB_XPiI + 0U, // SQDECB_XPiWdI + 0U, // SQDECD_XPiI + 0U, // SQDECD_XPiWdI + 0U, // SQDECD_ZPiI + 0U, // SQDECH_XPiI + 0U, // SQDECH_XPiWdI + 0U, // SQDECH_ZPiI + 5381U, // SQDECP_XPWd_B + 5381U, // SQDECP_XPWd_D + 5381U, // SQDECP_XPWd_H + 5381U, // SQDECP_XPWd_S + 1U, // SQDECP_XP_B + 1U, // SQDECP_XP_D + 1U, // SQDECP_XP_H + 1U, // SQDECP_XP_S + 1U, // SQDECP_ZP_D + 0U, // SQDECP_ZP_H + 1U, // SQDECP_ZP_S + 0U, // SQDECW_XPiI + 0U, // SQDECW_XPiWdI + 0U, // SQDECW_ZPiI + 2309U, // SQDMLALi16 + 2309U, // SQDMLALi32 + 9118085U, // SQDMLALv1i32_indexed + 9126277U, // SQDMLALv1i64_indexed + 9126279U, // SQDMLALv2i32_indexed + 41351U, // SQDMLALv2i32_v2i64 + 9118088U, // SQDMLALv4i16_indexed + 49544U, // SQDMLALv4i16_v4i32 + 9126278U, // SQDMLALv4i32_indexed + 16774U, // SQDMLALv4i32_v2i64 + 9118086U, // SQDMLALv8i16_indexed + 24966U, // SQDMLALv8i16_v4i32 + 2309U, // SQDMLSLi16 + 2309U, // SQDMLSLi32 + 9118085U, // SQDMLSLv1i32_indexed + 9126277U, // SQDMLSLv1i64_indexed + 9126279U, // SQDMLSLv2i32_indexed + 41351U, // SQDMLSLv2i32_v2i64 + 9118088U, // SQDMLSLv4i16_indexed + 49544U, // SQDMLSLv4i16_v4i32 + 9126278U, // SQDMLSLv4i32_indexed + 16774U, // SQDMLSLv4i32_v2i64 + 9118086U, // SQDMLSLv8i16_indexed + 24966U, // SQDMLSLv8i16_v4i32 + 261U, // SQDMULHv1i16 + 10166597U, // SQDMULHv1i16_indexed + 261U, // SQDMULHv1i32 + 10174789U, // SQDMULHv1i32_indexed + 41287U, // SQDMULHv2i32 + 10174791U, // SQDMULHv2i32_indexed + 49480U, // SQDMULHv4i16 + 10166600U, // SQDMULHv4i16_indexed + 16710U, // SQDMULHv4i32 + 10174790U, // SQDMULHv4i32_indexed + 24902U, // SQDMULHv8i16 + 10166598U, // SQDMULHv8i16_indexed + 261U, // SQDMULLi16 + 261U, // SQDMULLi32 + 10166597U, // SQDMULLv1i32_indexed + 10174789U, // SQDMULLv1i64_indexed + 10174791U, // SQDMULLv2i32_indexed + 41287U, // SQDMULLv2i32_v2i64 + 10166600U, // SQDMULLv4i16_indexed + 49480U, // SQDMULLv4i16_v4i32 + 10174790U, // SQDMULLv4i32_indexed + 16710U, // SQDMULLv4i32_v2i64 + 10166598U, // SQDMULLv8i16_indexed + 24902U, // SQDMULLv8i16_v4i32 + 0U, // SQINCB_XPiI + 0U, // SQINCB_XPiWdI + 0U, // SQINCD_XPiI + 0U, // SQINCD_XPiWdI + 0U, // SQINCD_ZPiI + 0U, // SQINCH_XPiI + 0U, // SQINCH_XPiWdI + 0U, // SQINCH_ZPiI + 5381U, // SQINCP_XPWd_B + 5381U, // SQINCP_XPWd_D + 5381U, // SQINCP_XPWd_H + 5381U, // SQINCP_XPWd_S + 1U, // SQINCP_XP_B + 1U, // SQINCP_XP_D + 1U, // SQINCP_XP_H + 1U, // SQINCP_XP_S + 1U, // SQINCP_ZP_D + 0U, // SQINCP_ZP_H + 1U, // SQINCP_ZP_S + 0U, // SQINCW_XPiI + 0U, // SQINCW_XPiWdI + 0U, // SQINCW_ZPiI + 1U, // SQNEGv16i8 + 1U, // SQNEGv1i16 + 1U, // SQNEGv1i32 + 1U, // SQNEGv1i64 + 1U, // SQNEGv1i8 + 2U, // SQNEGv2i32 + 2U, // SQNEGv2i64 + 3U, // SQNEGv4i16 + 3U, // SQNEGv4i32 + 4U, // SQNEGv8i16 + 4U, // SQNEGv8i8 + 9118085U, // SQRDMLAHi16_indexed + 9126277U, // SQRDMLAHi32_indexed + 2309U, // SQRDMLAHv1i16 + 2309U, // SQRDMLAHv1i32 + 41351U, // SQRDMLAHv2i32 + 9126279U, // SQRDMLAHv2i32_indexed + 49544U, // SQRDMLAHv4i16 + 9118088U, // SQRDMLAHv4i16_indexed + 16774U, // SQRDMLAHv4i32 + 9126278U, // SQRDMLAHv4i32_indexed + 24966U, // SQRDMLAHv8i16 + 9118086U, // SQRDMLAHv8i16_indexed + 9118085U, // SQRDMLSHi16_indexed + 9126277U, // SQRDMLSHi32_indexed + 2309U, // SQRDMLSHv1i16 + 2309U, // SQRDMLSHv1i32 + 41351U, // SQRDMLSHv2i32 + 9126279U, // SQRDMLSHv2i32_indexed + 49544U, // SQRDMLSHv4i16 + 9118088U, // SQRDMLSHv4i16_indexed + 16774U, // SQRDMLSHv4i32 + 9126278U, // SQRDMLSHv4i32_indexed + 24966U, // SQRDMLSHv8i16 + 9118086U, // SQRDMLSHv8i16_indexed + 261U, // SQRDMULHv1i16 + 10166597U, // SQRDMULHv1i16_indexed + 261U, // SQRDMULHv1i32 + 10174789U, // SQRDMULHv1i32_indexed + 41287U, // SQRDMULHv2i32 + 10174791U, // SQRDMULHv2i32_indexed + 49480U, // SQRDMULHv4i16 + 10166600U, // SQRDMULHv4i16_indexed + 16710U, // SQRDMULHv4i32 + 10174790U, // SQRDMULHv4i32_indexed + 24902U, // SQRDMULHv8i16 + 10166598U, // SQRDMULHv8i16_indexed + 33095U, // SQRSHLv16i8 + 261U, // SQRSHLv1i16 + 261U, // SQRSHLv1i32 + 261U, // SQRSHLv1i64 + 261U, // SQRSHLv1i8 + 41287U, // SQRSHLv2i32 + 8517U, // SQRSHLv2i64 + 49480U, // SQRSHLv4i16 + 16710U, // SQRSHLv4i32 + 24902U, // SQRSHLv8i16 + 57672U, // SQRSHLv8i8 + 261U, // SQRSHRNb + 261U, // SQRSHRNh + 261U, // SQRSHRNs + 2310U, // SQRSHRNv16i8_shift + 261U, // SQRSHRNv2i32_shift + 262U, // SQRSHRNv4i16_shift + 2309U, // SQRSHRNv4i32_shift + 2310U, // SQRSHRNv8i16_shift + 262U, // SQRSHRNv8i8_shift + 261U, // SQRSHRUNb + 261U, // SQRSHRUNh + 261U, // SQRSHRUNs + 2310U, // SQRSHRUNv16i8_shift + 261U, // SQRSHRUNv2i32_shift + 262U, // SQRSHRUNv4i16_shift + 2309U, // SQRSHRUNv4i32_shift + 2310U, // SQRSHRUNv8i16_shift + 262U, // SQRSHRUNv8i8_shift + 261U, // SQSHLUb + 261U, // SQSHLUd + 261U, // SQSHLUh + 261U, // SQSHLUs + 263U, // SQSHLUv16i8_shift + 263U, // SQSHLUv2i32_shift + 261U, // SQSHLUv2i64_shift + 264U, // SQSHLUv4i16_shift + 262U, // SQSHLUv4i32_shift + 262U, // SQSHLUv8i16_shift + 264U, // SQSHLUv8i8_shift + 261U, // SQSHLb + 261U, // SQSHLd + 261U, // SQSHLh + 261U, // SQSHLs + 33095U, // SQSHLv16i8 + 263U, // SQSHLv16i8_shift + 261U, // SQSHLv1i16 + 261U, // SQSHLv1i32 + 261U, // SQSHLv1i64 + 261U, // SQSHLv1i8 + 41287U, // SQSHLv2i32 + 263U, // SQSHLv2i32_shift + 8517U, // SQSHLv2i64 + 261U, // SQSHLv2i64_shift + 49480U, // SQSHLv4i16 + 264U, // SQSHLv4i16_shift + 16710U, // SQSHLv4i32 + 262U, // SQSHLv4i32_shift + 24902U, // SQSHLv8i16 + 262U, // SQSHLv8i16_shift + 57672U, // SQSHLv8i8 + 264U, // SQSHLv8i8_shift + 261U, // SQSHRNb + 261U, // SQSHRNh + 261U, // SQSHRNs + 2310U, // SQSHRNv16i8_shift + 261U, // SQSHRNv2i32_shift + 262U, // SQSHRNv4i16_shift + 2309U, // SQSHRNv4i32_shift + 2310U, // SQSHRNv8i16_shift + 262U, // SQSHRNv8i8_shift + 261U, // SQSHRUNb + 261U, // SQSHRUNh + 261U, // SQSHRUNs + 2310U, // SQSHRUNv16i8_shift + 261U, // SQSHRUNv2i32_shift + 262U, // SQSHRUNv4i16_shift + 2309U, // SQSHRUNv4i32_shift + 2310U, // SQSHRUNv8i16_shift + 262U, // SQSHRUNv8i8_shift + 645U, // SQSUB_ZI_B + 709U, // SQSUB_ZI_D + 9U, // SQSUB_ZI_H + 773U, // SQSUB_ZI_S + 837U, // SQSUB_ZZZ_B + 901U, // SQSUB_ZZZ_D + 137U, // SQSUB_ZZZ_H + 1029U, // SQSUB_ZZZ_S + 33095U, // SQSUBv16i8 + 261U, // SQSUBv1i16 + 261U, // SQSUBv1i32 + 261U, // SQSUBv1i64 + 261U, // SQSUBv1i8 + 41287U, // SQSUBv2i32 + 8517U, // SQSUBv2i64 + 49480U, // SQSUBv4i16 + 16710U, // SQSUBv4i32 + 24902U, // SQSUBv8i16 + 57672U, // SQSUBv8i8 + 4U, // SQXTNv16i8 + 1U, // SQXTNv1i16 + 1U, // SQXTNv1i32 + 1U, // SQXTNv1i8 + 2U, // SQXTNv2i32 + 3U, // SQXTNv4i16 + 2U, // SQXTNv4i32 + 3U, // SQXTNv8i16 + 4U, // SQXTNv8i8 + 4U, // SQXTUNv16i8 + 1U, // SQXTUNv1i16 + 1U, // SQXTUNv1i32 + 1U, // SQXTUNv1i8 + 2U, // SQXTUNv2i32 + 3U, // SQXTUNv4i16 + 2U, // SQXTUNv4i32 + 3U, // SQXTUNv8i16 + 4U, // SQXTUNv8i8 + 33095U, // SRHADDv16i8 + 41287U, // SRHADDv2i32 + 49480U, // SRHADDv4i16 + 16710U, // SRHADDv4i32 + 24902U, // SRHADDv8i16 + 57672U, // SRHADDv8i8 + 2309U, // SRId + 2311U, // SRIv16i8_shift + 2311U, // SRIv2i32_shift + 2309U, // SRIv2i64_shift + 2312U, // SRIv4i16_shift + 2310U, // SRIv4i32_shift + 2310U, // SRIv8i16_shift + 2312U, // SRIv8i8_shift + 33095U, // SRSHLv16i8 + 261U, // SRSHLv1i64 + 41287U, // SRSHLv2i32 + 8517U, // SRSHLv2i64 + 49480U, // SRSHLv4i16 + 16710U, // SRSHLv4i32 + 24902U, // SRSHLv8i16 + 57672U, // SRSHLv8i8 + 261U, // SRSHRd + 263U, // SRSHRv16i8_shift + 263U, // SRSHRv2i32_shift + 261U, // SRSHRv2i64_shift + 264U, // SRSHRv4i16_shift + 262U, // SRSHRv4i32_shift + 262U, // SRSHRv8i16_shift + 264U, // SRSHRv8i8_shift + 2309U, // SRSRAd + 2311U, // SRSRAv16i8_shift + 2311U, // SRSRAv2i32_shift + 2309U, // SRSRAv2i64_shift + 2312U, // SRSRAv4i16_shift + 2310U, // SRSRAv4i32_shift + 2310U, // SRSRAv8i16_shift + 2312U, // SRSRAv8i8_shift + 263U, // SSHLLv16i8_shift + 263U, // SSHLLv2i32_shift + 264U, // SSHLLv4i16_shift + 262U, // SSHLLv4i32_shift + 262U, // SSHLLv8i16_shift + 264U, // SSHLLv8i8_shift + 33095U, // SSHLv16i8 + 261U, // SSHLv1i64 + 41287U, // SSHLv2i32 + 8517U, // SSHLv2i64 + 49480U, // SSHLv4i16 + 16710U, // SSHLv4i32 + 24902U, // SSHLv8i16 + 57672U, // SSHLv8i8 + 261U, // SSHRd + 263U, // SSHRv16i8_shift + 263U, // SSHRv2i32_shift + 261U, // SSHRv2i64_shift + 264U, // SSHRv4i16_shift + 262U, // SSHRv4i32_shift + 262U, // SSHRv8i16_shift + 264U, // SSHRv8i8_shift + 2309U, // SSRAd + 2311U, // SSRAv16i8_shift + 2311U, // SSRAv2i32_shift + 2309U, // SSRAv2i64_shift + 2312U, // SSRAv4i16_shift + 2310U, // SSRAv4i32_shift + 2310U, // SSRAv8i16_shift + 2312U, // SSRAv8i8_shift + 3205U, // SST1B_D + 3153U, // SST1B_D_IMM + 3269U, // SST1B_D_SXTW + 3333U, // SST1B_D_UXTW + 3153U, // SST1B_S_IMM + 3397U, // SST1B_S_SXTW + 3461U, // SST1B_S_UXTW + 3205U, // SST1D + 26U, // SST1D_IMM + 3525U, // SST1D_SCALED + 3269U, // SST1D_SXTW + 3589U, // SST1D_SXTW_SCALED + 3333U, // SST1D_UXTW + 3653U, // SST1D_UXTW_SCALED + 3205U, // SST1H_D + 26U, // SST1H_D_IMM + 3717U, // SST1H_D_SCALED + 3269U, // SST1H_D_SXTW + 3781U, // SST1H_D_SXTW_SCALED + 3333U, // SST1H_D_UXTW + 3845U, // SST1H_D_UXTW_SCALED + 26U, // SST1H_S_IMM + 3397U, // SST1H_S_SXTW + 3909U, // SST1H_S_SXTW_SCALED + 3461U, // SST1H_S_UXTW + 3973U, // SST1H_S_UXTW_SCALED + 3205U, // SST1W_D + 27U, // SST1W_D_IMM + 4037U, // SST1W_D_SCALED + 3269U, // SST1W_D_SXTW + 4101U, // SST1W_D_SXTW_SCALED + 3333U, // SST1W_D_UXTW + 4165U, // SST1W_D_UXTW_SCALED + 27U, // SST1W_IMM + 3397U, // SST1W_SXTW + 4229U, // SST1W_SXTW_SCALED + 3461U, // SST1W_UXTW + 4293U, // SST1W_UXTW_SCALED + 33095U, // SSUBLv16i8_v8i16 + 41287U, // SSUBLv2i32_v2i64 + 49480U, // SSUBLv4i16_v4i32 + 16710U, // SSUBLv4i32_v2i64 + 24902U, // SSUBLv8i16_v4i32 + 57672U, // SSUBLv8i8_v8i16 + 33094U, // SSUBWv16i8_v8i16 + 41285U, // SSUBWv2i32_v2i64 + 49478U, // SSUBWv4i16_v4i32 + 16709U, // SSUBWv4i32_v2i64 + 24902U, // SSUBWv8i16_v4i32 + 57670U, // SSUBWv8i8_v8i16 + 4357U, // ST1B + 4357U, // ST1B_D + 256261U, // ST1B_D_IMM + 4357U, // ST1B_H + 256261U, // ST1B_H_IMM + 256261U, // ST1B_IMM + 4357U, // ST1B_S + 256261U, // ST1B_S_IMM + 4421U, // ST1D + 256261U, // ST1D_IMM + 0U, // ST1Fourv16b + 0U, // ST1Fourv16b_POST + 0U, // ST1Fourv1d + 0U, // ST1Fourv1d_POST + 0U, // ST1Fourv2d + 0U, // ST1Fourv2d_POST + 0U, // ST1Fourv2s + 0U, // ST1Fourv2s_POST + 0U, // ST1Fourv4h + 0U, // ST1Fourv4h_POST + 0U, // ST1Fourv4s + 0U, // ST1Fourv4s_POST + 0U, // ST1Fourv8b + 0U, // ST1Fourv8b_POST + 0U, // ST1Fourv8h + 0U, // ST1Fourv8h_POST + 4485U, // ST1H + 4485U, // ST1H_D + 256261U, // ST1H_D_IMM + 256261U, // ST1H_IMM + 4485U, // ST1H_S + 256261U, // ST1H_S_IMM + 0U, // ST1Onev16b + 0U, // ST1Onev16b_POST + 0U, // ST1Onev1d + 0U, // ST1Onev1d_POST + 0U, // ST1Onev2d + 0U, // ST1Onev2d_POST + 0U, // ST1Onev2s + 0U, // ST1Onev2s_POST + 0U, // ST1Onev4h + 0U, // ST1Onev4h_POST + 0U, // ST1Onev4s + 0U, // ST1Onev4s_POST + 0U, // ST1Onev8b + 0U, // ST1Onev8b_POST + 0U, // ST1Onev8h + 0U, // ST1Onev8h_POST + 0U, // ST1Threev16b + 0U, // ST1Threev16b_POST + 0U, // ST1Threev1d + 0U, // ST1Threev1d_POST + 0U, // ST1Threev2d + 0U, // ST1Threev2d_POST + 0U, // ST1Threev2s + 0U, // ST1Threev2s_POST + 0U, // ST1Threev4h + 0U, // ST1Threev4h_POST + 0U, // ST1Threev4s + 0U, // ST1Threev4s_POST + 0U, // ST1Threev8b + 0U, // ST1Threev8b_POST + 0U, // ST1Threev8h + 0U, // ST1Threev8h_POST + 0U, // ST1Twov16b + 0U, // ST1Twov16b_POST + 0U, // ST1Twov1d + 0U, // ST1Twov1d_POST + 0U, // ST1Twov2d + 0U, // ST1Twov2d_POST + 0U, // ST1Twov2s + 0U, // ST1Twov2s_POST + 0U, // ST1Twov4h + 0U, // ST1Twov4h_POST + 0U, // ST1Twov4s + 0U, // ST1Twov4s_POST + 0U, // ST1Twov8b + 0U, // ST1Twov8b_POST + 0U, // ST1Twov8h + 0U, // ST1Twov8h_POST + 4741U, // ST1W + 4741U, // ST1W_D + 256261U, // ST1W_D_IMM + 256261U, // ST1W_IMM + 0U, // ST1i16 + 0U, // ST1i16_POST + 0U, // ST1i32 + 0U, // ST1i32_POST + 0U, // ST1i64 + 0U, // ST1i64_POST + 0U, // ST1i8 + 0U, // ST1i8_POST + 4357U, // ST2B + 258565U, // ST2B_IMM + 4421U, // ST2D + 258565U, // ST2D_IMM + 4485U, // ST2H + 258565U, // ST2H_IMM + 0U, // ST2Twov16b + 0U, // ST2Twov16b_POST + 0U, // ST2Twov2d + 0U, // ST2Twov2d_POST + 0U, // ST2Twov2s + 0U, // ST2Twov2s_POST + 0U, // ST2Twov4h + 0U, // ST2Twov4h_POST + 0U, // ST2Twov4s + 0U, // ST2Twov4s_POST + 0U, // ST2Twov8b + 0U, // ST2Twov8b_POST + 0U, // ST2Twov8h + 0U, // ST2Twov8h_POST + 4741U, // ST2W + 258565U, // ST2W_IMM + 0U, // ST2i16 + 0U, // ST2i16_POST + 0U, // ST2i32 + 0U, // ST2i32_POST + 0U, // ST2i64 + 0U, // ST2i64_POST + 0U, // ST2i8 + 0U, // ST2i8_POST + 4357U, // ST3B + 4869U, // ST3B_IMM + 4421U, // ST3D + 4869U, // ST3D_IMM + 4485U, // ST3H + 4869U, // ST3H_IMM + 0U, // ST3Threev16b + 0U, // ST3Threev16b_POST + 0U, // ST3Threev2d + 0U, // ST3Threev2d_POST + 0U, // ST3Threev2s + 0U, // ST3Threev2s_POST + 0U, // ST3Threev4h + 0U, // ST3Threev4h_POST + 0U, // ST3Threev4s + 0U, // ST3Threev4s_POST + 0U, // ST3Threev8b + 0U, // ST3Threev8b_POST + 0U, // ST3Threev8h + 0U, // ST3Threev8h_POST + 4741U, // ST3W + 4869U, // ST3W_IMM + 0U, // ST3i16 + 0U, // ST3i16_POST + 0U, // ST3i32 + 0U, // ST3i32_POST + 0U, // ST3i64 + 0U, // ST3i64_POST + 0U, // ST3i8 + 0U, // ST3i8_POST + 4357U, // ST4B + 258757U, // ST4B_IMM + 4421U, // ST4D + 258757U, // ST4D_IMM + 0U, // ST4Fourv16b + 0U, // ST4Fourv16b_POST + 0U, // ST4Fourv2d + 0U, // ST4Fourv2d_POST + 0U, // ST4Fourv2s + 0U, // ST4Fourv2s_POST + 0U, // ST4Fourv4h + 0U, // ST4Fourv4h_POST + 0U, // ST4Fourv4s + 0U, // ST4Fourv4s_POST + 0U, // ST4Fourv8b + 0U, // ST4Fourv8b_POST + 0U, // ST4Fourv8h + 0U, // ST4Fourv8h_POST + 4485U, // ST4H + 258757U, // ST4H_IMM + 4741U, // ST4W + 258757U, // ST4W_IMM + 0U, // ST4i16 + 0U, // ST4i16_POST + 0U, // ST4i32 + 0U, // ST4i32_POST + 0U, // ST4i64 + 0U, // ST4i64_POST + 0U, // ST4i8 + 0U, // ST4i8_POST + 27U, // STLLRB + 27U, // STLLRH + 27U, // STLLRW + 27U, // STLLRX + 27U, // STLRB + 27U, // STLRH + 27U, // STLRW + 27U, // STLRX + 114949U, // STLURBi + 114949U, // STLURHi + 114949U, // STLURWi + 114949U, // STLURXi + 286981U, // STLXPW + 286981U, // STLXPX + 114955U, // STLXRB + 114955U, // STLXRH + 114955U, // STLXRW + 114955U, // STLXRX + 11084043U, // STNPDi + 11608331U, // STNPQi + 12132619U, // STNPSi + 12132619U, // STNPWi + 11084043U, // STNPXi + 256261U, // STNT1B_ZRI + 4357U, // STNT1B_ZRR + 256261U, // STNT1D_ZRI + 4421U, // STNT1D_ZRR + 256261U, // STNT1H_ZRI + 4485U, // STNT1H_ZRR + 256261U, // STNT1W_ZRI + 4741U, // STNT1W_ZRR + 11084043U, // STPDi + 12847371U, // STPDpost + 180431115U, // STPDpre + 11608331U, // STPQi + 13371659U, // STPQpost + 180955403U, // STPQpre + 12132619U, // STPSi + 13895947U, // STPSpost + 181479691U, // STPSpre + 12132619U, // STPWi + 13895947U, // STPWpost + 181479691U, // STPWpre + 11084043U, // STPXi + 12847371U, // STPXpost + 180431115U, // STPXpre + 28U, // STRBBpost + 272645U, // STRBBpre + 14229765U, // STRBBroW + 14754053U, // STRBBroX + 4997U, // STRBBui + 28U, // STRBpost + 272645U, // STRBpre + 14229765U, // STRBroW + 14754053U, // STRBroX + 4997U, // STRBui + 28U, // STRDpost + 272645U, // STRDpre + 15278341U, // STRDroW + 15802629U, // STRDroX + 5061U, // STRDui + 28U, // STRHHpost + 272645U, // STRHHpre + 16326917U, // STRHHroW + 16851205U, // STRHHroX + 5125U, // STRHHui + 28U, // STRHpost + 272645U, // STRHpre + 16326917U, // STRHroW + 16851205U, // STRHroX + 5125U, // STRHui + 28U, // STRQpost + 272645U, // STRQpre + 17375493U, // STRQroW + 17899781U, // STRQroX + 5189U, // STRQui + 28U, // STRSpost + 272645U, // STRSpre + 18424069U, // STRSroW + 18948357U, // STRSroX + 5253U, // STRSui + 28U, // STRWpost + 272645U, // STRWpre + 18424069U, // STRWroW + 18948357U, // STRWroX + 5253U, // STRWui + 28U, // STRXpost + 272645U, // STRXpre + 15278341U, // STRXroW + 15802629U, // STRXroX + 5061U, // STRXui + 254213U, // STR_PXI + 254213U, // STR_ZXI + 114949U, // STTRBi + 114949U, // STTRHi + 114949U, // STTRWi + 114949U, // STTRXi + 114949U, // STURBBi + 114949U, // STURBi + 114949U, // STURDi + 114949U, // STURHHi + 114949U, // STURHi + 114949U, // STURQi + 114949U, // STURSi + 114949U, // STURWi + 114949U, // STURXi + 286981U, // STXPW + 286981U, // STXPX + 114955U, // STXRB + 114955U, // STXRH + 114955U, // STXRW + 114955U, // STXRX + 8517U, // SUBHNv2i64_v2i32 + 8581U, // SUBHNv2i64_v4i32 + 16710U, // SUBHNv4i32_v4i16 + 16774U, // SUBHNv4i32_v8i16 + 24966U, // SUBHNv8i16_v16i8 + 24902U, // SUBHNv8i16_v8i8 + 645U, // SUBR_ZI_B + 709U, // SUBR_ZI_D + 9U, // SUBR_ZI_H + 773U, // SUBR_ZI_S + 74560U, // SUBR_ZPmZ_B + 598912U, // SUBR_ZPmZ_D + 1131465U, // SUBR_ZPmZ_H + 1647616U, // SUBR_ZPmZ_S + 453U, // SUBSWri + 0U, // SUBSWrr + 517U, // SUBSWrs + 581U, // SUBSWrx + 453U, // SUBSXri + 0U, // SUBSXrr + 517U, // SUBSXrs + 581U, // SUBSXrx + 65797U, // SUBSXrx64 + 453U, // SUBWri + 0U, // SUBWrr + 517U, // SUBWrs + 581U, // SUBWrx + 453U, // SUBXri + 0U, // SUBXrr + 517U, // SUBXrs + 581U, // SUBXrx + 65797U, // SUBXrx64 + 645U, // SUB_ZI_B + 709U, // SUB_ZI_D + 9U, // SUB_ZI_H + 773U, // SUB_ZI_S + 74560U, // SUB_ZPmZ_B + 598912U, // SUB_ZPmZ_D + 1131465U, // SUB_ZPmZ_H + 1647616U, // SUB_ZPmZ_S + 837U, // SUB_ZZZ_B + 901U, // SUB_ZZZ_D + 137U, // SUB_ZZZ_H + 1029U, // SUB_ZZZ_S + 33095U, // SUBv16i8 + 261U, // SUBv1i64 + 41287U, // SUBv2i32 + 8517U, // SUBv2i64 + 49480U, // SUBv4i16 + 16710U, // SUBv4i32 + 24902U, // SUBv8i16 + 57672U, // SUBv8i8 + 1U, // SUNPKHI_ZZ_D + 0U, // SUNPKHI_ZZ_H + 1U, // SUNPKHI_ZZ_S + 1U, // SUNPKLO_ZZ_D + 0U, // SUNPKLO_ZZ_H + 1U, // SUNPKLO_ZZ_S + 1U, // SUQADDv16i8 + 1U, // SUQADDv1i16 + 1U, // SUQADDv1i32 + 1U, // SUQADDv1i64 + 1U, // SUQADDv1i8 + 2U, // SUQADDv2i32 + 2U, // SUQADDv2i64 + 3U, // SUQADDv4i16 + 3U, // SUQADDv4i32 + 4U, // SUQADDv8i16 + 4U, // SUQADDv8i8 + 0U, // SVC + 0U, // SWPAB + 0U, // SWPAH + 0U, // SWPALB + 0U, // SWPALH + 0U, // SWPALW + 0U, // SWPALX + 0U, // SWPAW + 0U, // SWPAX + 0U, // SWPB + 0U, // SWPH + 0U, // SWPLB + 0U, // SWPLH + 0U, // SWPLW + 0U, // SWPLX + 0U, // SWPW + 0U, // SWPX + 64U, // SXTB_ZPmZ_D + 128U, // SXTB_ZPmZ_H + 192U, // SXTB_ZPmZ_S + 64U, // SXTH_ZPmZ_D + 192U, // SXTH_ZPmZ_S + 64U, // SXTW_ZPmZ_D + 5445U, // SYSLxt + 0U, // SYSxt + 0U, // TBL_ZZZ_B + 0U, // TBL_ZZZ_D + 0U, // TBL_ZZZ_H + 0U, // TBL_ZZZ_S + 1U, // TBLv16i8Four + 1U, // TBLv16i8One + 1U, // TBLv16i8Three + 1U, // TBLv16i8Two + 4U, // TBLv8i8Four + 4U, // TBLv8i8One + 4U, // TBLv8i8Three + 4U, // TBLv8i8Two + 5509U, // TBNZW + 5509U, // TBNZX + 1U, // TBXv16i8Four + 1U, // TBXv16i8One + 1U, // TBXv16i8Three + 1U, // TBXv16i8Two + 4U, // TBXv8i8Four + 4U, // TBXv8i8One + 4U, // TBXv8i8Three + 4U, // TBXv8i8Two + 5509U, // TBZW + 5509U, // TBZX + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TLSDESCCALL + 0U, // TLSDESC_CALLSEQ + 837U, // TRN1_PPP_B + 901U, // TRN1_PPP_D + 137U, // TRN1_PPP_H + 1029U, // TRN1_PPP_S + 837U, // TRN1_ZZZ_B + 901U, // TRN1_ZZZ_D + 137U, // TRN1_ZZZ_H + 1029U, // TRN1_ZZZ_S + 33095U, // TRN1v16i8 + 41287U, // TRN1v2i32 + 8517U, // TRN1v2i64 + 49480U, // TRN1v4i16 + 16710U, // TRN1v4i32 + 24902U, // TRN1v8i16 + 57672U, // TRN1v8i8 + 837U, // TRN2_PPP_B + 901U, // TRN2_PPP_D + 137U, // TRN2_PPP_H + 1029U, // TRN2_PPP_S + 837U, // TRN2_ZZZ_B + 901U, // TRN2_ZZZ_D + 137U, // TRN2_ZZZ_H + 1029U, // TRN2_ZZZ_S + 33095U, // TRN2v16i8 + 41287U, // TRN2v2i32 + 8517U, // TRN2v2i64 + 49480U, // TRN2v4i16 + 16710U, // TRN2v4i32 + 24902U, // TRN2v8i16 + 57672U, // TRN2v8i8 + 0U, // TSB + 33159U, // UABALv16i8_v8i16 + 41351U, // UABALv2i32_v2i64 + 49544U, // UABALv4i16_v4i32 + 16774U, // UABALv4i32_v2i64 + 24966U, // UABALv8i16_v4i32 + 57736U, // UABALv8i8_v8i16 + 33159U, // UABAv16i8 + 41351U, // UABAv2i32 + 49544U, // UABAv4i16 + 16774U, // UABAv4i32 + 24966U, // UABAv8i16 + 57736U, // UABAv8i8 + 33095U, // UABDLv16i8_v8i16 + 41287U, // UABDLv2i32_v2i64 + 49480U, // UABDLv4i16_v4i32 + 16710U, // UABDLv4i32_v2i64 + 24902U, // UABDLv8i16_v4i32 + 57672U, // UABDLv8i8_v8i16 + 74560U, // UABD_ZPmZ_B + 598912U, // UABD_ZPmZ_D + 1131465U, // UABD_ZPmZ_H + 1647616U, // UABD_ZPmZ_S + 33095U, // UABDv16i8 + 41287U, // UABDv2i32 + 49480U, // UABDv4i16 + 16710U, // UABDv4i32 + 24902U, // UABDv8i16 + 57672U, // UABDv8i8 + 1U, // UADALPv16i8_v8i16 + 2U, // UADALPv2i32_v1i64 + 3U, // UADALPv4i16_v2i32 + 3U, // UADALPv4i32_v2i64 + 4U, // UADALPv8i16_v4i32 + 4U, // UADALPv8i8_v4i16 + 1U, // UADDLPv16i8_v8i16 + 2U, // UADDLPv2i32_v1i64 + 3U, // UADDLPv4i16_v2i32 + 3U, // UADDLPv4i32_v2i64 + 4U, // UADDLPv8i16_v4i32 + 4U, // UADDLPv8i8_v4i16 + 1U, // UADDLVv16i8v + 3U, // UADDLVv4i16v + 3U, // UADDLVv4i32v + 4U, // UADDLVv8i16v + 4U, // UADDLVv8i8v + 33095U, // UADDLv16i8_v8i16 + 41287U, // UADDLv2i32_v2i64 + 49480U, // UADDLv4i16_v4i32 + 16710U, // UADDLv4i32_v2i64 + 24902U, // UADDLv8i16_v4i32 + 57672U, // UADDLv8i8_v8i16 + 837U, // UADDV_VPZ_B + 901U, // UADDV_VPZ_D + 2245U, // UADDV_VPZ_H + 1029U, // UADDV_VPZ_S + 33094U, // UADDWv16i8_v8i16 + 41285U, // UADDWv2i32_v2i64 + 49478U, // UADDWv4i16_v4i32 + 16709U, // UADDWv4i32_v2i64 + 24902U, // UADDWv8i16_v4i32 + 57670U, // UADDWv8i8_v8i16 + 2171141U, // UBFMWri + 2171141U, // UBFMXri + 261U, // UCVTFSWDri + 261U, // UCVTFSWHri + 261U, // UCVTFSWSri + 261U, // UCVTFSXDri + 261U, // UCVTFSXHri + 261U, // UCVTFSXSri + 1U, // UCVTFUWDri + 1U, // UCVTFUWHri + 1U, // UCVTFUWSri + 1U, // UCVTFUXDri + 1U, // UCVTFUXHri + 1U, // UCVTFUXSri + 64U, // UCVTF_ZPmZ_DtoD + 153U, // UCVTF_ZPmZ_DtoH + 64U, // UCVTF_ZPmZ_DtoS + 128U, // UCVTF_ZPmZ_HtoH + 192U, // UCVTF_ZPmZ_StoD + 152U, // UCVTF_ZPmZ_StoH + 192U, // UCVTF_ZPmZ_StoS + 261U, // UCVTFd + 261U, // UCVTFh + 261U, // UCVTFs + 1U, // UCVTFv1i16 + 1U, // UCVTFv1i32 + 1U, // UCVTFv1i64 + 2U, // UCVTFv2f32 + 2U, // UCVTFv2f64 + 263U, // UCVTFv2i32_shift + 261U, // UCVTFv2i64_shift + 3U, // UCVTFv4f16 + 3U, // UCVTFv4f32 + 264U, // UCVTFv4i16_shift + 262U, // UCVTFv4i32_shift + 4U, // UCVTFv8f16 + 262U, // UCVTFv8i16_shift + 598912U, // UDIVR_ZPmZ_D + 1647616U, // UDIVR_ZPmZ_S + 261U, // UDIVWr + 261U, // UDIVXr + 598912U, // UDIV_ZPmZ_D + 1647616U, // UDIV_ZPmZ_S + 41U, // UDOT_ZZZI_D + 41U, // UDOT_ZZZI_S + 1U, // UDOT_ZZZ_D + 1U, // UDOT_ZZZ_S + 278919U, // UDOTlanev16i8 + 278920U, // UDOTlanev8i8 + 33159U, // UDOTv16i8 + 57736U, // UDOTv8i8 + 33095U, // UHADDv16i8 + 41287U, // UHADDv2i32 + 49480U, // UHADDv4i16 + 16710U, // UHADDv4i32 + 24902U, // UHADDv8i16 + 57672U, // UHADDv8i8 + 33095U, // UHSUBv16i8 + 41287U, // UHSUBv2i32 + 49480U, // UHSUBv4i16 + 16710U, // UHSUBv4i32 + 24902U, // UHSUBv8i16 + 57672U, // UHSUBv8i8 + 2171141U, // UMADDLrrr + 33095U, // UMAXPv16i8 + 41287U, // UMAXPv2i32 + 49480U, // UMAXPv4i16 + 16710U, // UMAXPv4i32 + 24902U, // UMAXPv8i16 + 57672U, // UMAXPv8i8 + 837U, // UMAXV_VPZ_B + 901U, // UMAXV_VPZ_D + 2245U, // UMAXV_VPZ_H + 1029U, // UMAXV_VPZ_S + 1U, // UMAXVv16i8v + 3U, // UMAXVv4i16v + 3U, // UMAXVv4i32v + 4U, // UMAXVv8i16v + 4U, // UMAXVv8i8v + 5573U, // UMAX_ZI_B + 5573U, // UMAX_ZI_D + 45U, // UMAX_ZI_H + 5573U, // UMAX_ZI_S + 74560U, // UMAX_ZPmZ_B + 598912U, // UMAX_ZPmZ_D + 1131465U, // UMAX_ZPmZ_H + 1647616U, // UMAX_ZPmZ_S + 33095U, // UMAXv16i8 + 41287U, // UMAXv2i32 + 49480U, // UMAXv4i16 + 16710U, // UMAXv4i32 + 24902U, // UMAXv8i16 + 57672U, // UMAXv8i8 + 33095U, // UMINPv16i8 + 41287U, // UMINPv2i32 + 49480U, // UMINPv4i16 + 16710U, // UMINPv4i32 + 24902U, // UMINPv8i16 + 57672U, // UMINPv8i8 + 837U, // UMINV_VPZ_B + 901U, // UMINV_VPZ_D + 2245U, // UMINV_VPZ_H + 1029U, // UMINV_VPZ_S + 1U, // UMINVv16i8v + 3U, // UMINVv4i16v + 3U, // UMINVv4i32v + 4U, // UMINVv8i16v + 4U, // UMINVv8i8v + 5573U, // UMIN_ZI_B + 5573U, // UMIN_ZI_D + 45U, // UMIN_ZI_H + 5573U, // UMIN_ZI_S + 74560U, // UMIN_ZPmZ_B + 598912U, // UMIN_ZPmZ_D + 1131465U, // UMIN_ZPmZ_H + 1647616U, // UMIN_ZPmZ_S + 33095U, // UMINv16i8 + 41287U, // UMINv2i32 + 49480U, // UMINv4i16 + 16710U, // UMINv4i32 + 24902U, // UMINv8i16 + 57672U, // UMINv8i8 + 33159U, // UMLALv16i8_v8i16 + 9126279U, // UMLALv2i32_indexed + 41351U, // UMLALv2i32_v2i64 + 9118088U, // UMLALv4i16_indexed + 49544U, // UMLALv4i16_v4i32 + 9126278U, // UMLALv4i32_indexed + 16774U, // UMLALv4i32_v2i64 + 9118086U, // UMLALv8i16_indexed + 24966U, // UMLALv8i16_v4i32 + 57736U, // UMLALv8i8_v8i16 + 33159U, // UMLSLv16i8_v8i16 + 9126279U, // UMLSLv2i32_indexed + 41351U, // UMLSLv2i32_v2i64 + 9118088U, // UMLSLv4i16_indexed + 49544U, // UMLSLv4i16_v4i32 + 9126278U, // UMLSLv4i32_indexed + 16774U, // UMLSLv4i32_v2i64 + 9118086U, // UMLSLv8i16_indexed + 24966U, // UMLSLv8i16_v4i32 + 57736U, // UMLSLv8i8_v8i16 + 2770U, // UMOVvi16 + 2770U, // UMOVvi32 + 2771U, // UMOVvi64 + 2771U, // UMOVvi8 + 2171141U, // UMSUBLrrr + 74560U, // UMULH_ZPmZ_B + 598912U, // UMULH_ZPmZ_D + 1131465U, // UMULH_ZPmZ_H + 1647616U, // UMULH_ZPmZ_S + 261U, // UMULHrr + 33095U, // UMULLv16i8_v8i16 + 10174791U, // UMULLv2i32_indexed + 41287U, // UMULLv2i32_v2i64 + 10166600U, // UMULLv4i16_indexed + 49480U, // UMULLv4i16_v4i32 + 10174790U, // UMULLv4i32_indexed + 16710U, // UMULLv4i32_v2i64 + 10166598U, // UMULLv8i16_indexed + 24902U, // UMULLv8i16_v4i32 + 57672U, // UMULLv8i8_v8i16 + 645U, // UQADD_ZI_B + 709U, // UQADD_ZI_D + 9U, // UQADD_ZI_H + 773U, // UQADD_ZI_S + 837U, // UQADD_ZZZ_B + 901U, // UQADD_ZZZ_D + 137U, // UQADD_ZZZ_H + 1029U, // UQADD_ZZZ_S + 33095U, // UQADDv16i8 + 261U, // UQADDv1i16 + 261U, // UQADDv1i32 + 261U, // UQADDv1i64 + 261U, // UQADDv1i8 + 41287U, // UQADDv2i32 + 8517U, // UQADDv2i64 + 49480U, // UQADDv4i16 + 16710U, // UQADDv4i32 + 24902U, // UQADDv8i16 + 57672U, // UQADDv8i8 + 0U, // UQDECB_WPiI + 0U, // UQDECB_XPiI + 0U, // UQDECD_WPiI + 0U, // UQDECD_XPiI + 0U, // UQDECD_ZPiI + 0U, // UQDECH_WPiI + 0U, // UQDECH_XPiI + 0U, // UQDECH_ZPiI + 1U, // UQDECP_WP_B + 1U, // UQDECP_WP_D + 1U, // UQDECP_WP_H + 1U, // UQDECP_WP_S + 1U, // UQDECP_XP_B + 1U, // UQDECP_XP_D + 1U, // UQDECP_XP_H + 1U, // UQDECP_XP_S + 1U, // UQDECP_ZP_D + 0U, // UQDECP_ZP_H + 1U, // UQDECP_ZP_S + 0U, // UQDECW_WPiI + 0U, // UQDECW_XPiI + 0U, // UQDECW_ZPiI + 0U, // UQINCB_WPiI + 0U, // UQINCB_XPiI + 0U, // UQINCD_WPiI + 0U, // UQINCD_XPiI + 0U, // UQINCD_ZPiI + 0U, // UQINCH_WPiI + 0U, // UQINCH_XPiI + 0U, // UQINCH_ZPiI + 1U, // UQINCP_WP_B + 1U, // UQINCP_WP_D + 1U, // UQINCP_WP_H + 1U, // UQINCP_WP_S + 1U, // UQINCP_XP_B + 1U, // UQINCP_XP_D + 1U, // UQINCP_XP_H + 1U, // UQINCP_XP_S + 1U, // UQINCP_ZP_D + 0U, // UQINCP_ZP_H + 1U, // UQINCP_ZP_S + 0U, // UQINCW_WPiI + 0U, // UQINCW_XPiI + 0U, // UQINCW_ZPiI + 33095U, // UQRSHLv16i8 + 261U, // UQRSHLv1i16 + 261U, // UQRSHLv1i32 + 261U, // UQRSHLv1i64 + 261U, // UQRSHLv1i8 + 41287U, // UQRSHLv2i32 + 8517U, // UQRSHLv2i64 + 49480U, // UQRSHLv4i16 + 16710U, // UQRSHLv4i32 + 24902U, // UQRSHLv8i16 + 57672U, // UQRSHLv8i8 + 261U, // UQRSHRNb + 261U, // UQRSHRNh + 261U, // UQRSHRNs + 2310U, // UQRSHRNv16i8_shift + 261U, // UQRSHRNv2i32_shift + 262U, // UQRSHRNv4i16_shift + 2309U, // UQRSHRNv4i32_shift + 2310U, // UQRSHRNv8i16_shift + 262U, // UQRSHRNv8i8_shift + 261U, // UQSHLb + 261U, // UQSHLd + 261U, // UQSHLh + 261U, // UQSHLs + 33095U, // UQSHLv16i8 + 263U, // UQSHLv16i8_shift + 261U, // UQSHLv1i16 + 261U, // UQSHLv1i32 + 261U, // UQSHLv1i64 + 261U, // UQSHLv1i8 + 41287U, // UQSHLv2i32 + 263U, // UQSHLv2i32_shift + 8517U, // UQSHLv2i64 + 261U, // UQSHLv2i64_shift + 49480U, // UQSHLv4i16 + 264U, // UQSHLv4i16_shift + 16710U, // UQSHLv4i32 + 262U, // UQSHLv4i32_shift + 24902U, // UQSHLv8i16 + 262U, // UQSHLv8i16_shift + 57672U, // UQSHLv8i8 + 264U, // UQSHLv8i8_shift + 261U, // UQSHRNb + 261U, // UQSHRNh + 261U, // UQSHRNs + 2310U, // UQSHRNv16i8_shift + 261U, // UQSHRNv2i32_shift + 262U, // UQSHRNv4i16_shift + 2309U, // UQSHRNv4i32_shift + 2310U, // UQSHRNv8i16_shift + 262U, // UQSHRNv8i8_shift + 645U, // UQSUB_ZI_B + 709U, // UQSUB_ZI_D + 9U, // UQSUB_ZI_H + 773U, // UQSUB_ZI_S + 837U, // UQSUB_ZZZ_B + 901U, // UQSUB_ZZZ_D + 137U, // UQSUB_ZZZ_H + 1029U, // UQSUB_ZZZ_S + 33095U, // UQSUBv16i8 + 261U, // UQSUBv1i16 + 261U, // UQSUBv1i32 + 261U, // UQSUBv1i64 + 261U, // UQSUBv1i8 + 41287U, // UQSUBv2i32 + 8517U, // UQSUBv2i64 + 49480U, // UQSUBv4i16 + 16710U, // UQSUBv4i32 + 24902U, // UQSUBv8i16 + 57672U, // UQSUBv8i8 + 4U, // UQXTNv16i8 + 1U, // UQXTNv1i16 + 1U, // UQXTNv1i32 + 1U, // UQXTNv1i8 + 2U, // UQXTNv2i32 + 3U, // UQXTNv4i16 + 2U, // UQXTNv4i32 + 3U, // UQXTNv8i16 + 4U, // UQXTNv8i8 + 2U, // URECPEv2i32 + 3U, // URECPEv4i32 + 33095U, // URHADDv16i8 + 41287U, // URHADDv2i32 + 49480U, // URHADDv4i16 + 16710U, // URHADDv4i32 + 24902U, // URHADDv8i16 + 57672U, // URHADDv8i8 + 33095U, // URSHLv16i8 + 261U, // URSHLv1i64 + 41287U, // URSHLv2i32 + 8517U, // URSHLv2i64 + 49480U, // URSHLv4i16 + 16710U, // URSHLv4i32 + 24902U, // URSHLv8i16 + 57672U, // URSHLv8i8 + 261U, // URSHRd + 263U, // URSHRv16i8_shift + 263U, // URSHRv2i32_shift + 261U, // URSHRv2i64_shift + 264U, // URSHRv4i16_shift + 262U, // URSHRv4i32_shift + 262U, // URSHRv8i16_shift + 264U, // URSHRv8i8_shift + 2U, // URSQRTEv2i32 + 3U, // URSQRTEv4i32 + 2309U, // URSRAd + 2311U, // URSRAv16i8_shift + 2311U, // URSRAv2i32_shift + 2309U, // URSRAv2i64_shift + 2312U, // URSRAv4i16_shift + 2310U, // URSRAv4i32_shift + 2310U, // URSRAv8i16_shift + 2312U, // URSRAv8i8_shift + 263U, // USHLLv16i8_shift + 263U, // USHLLv2i32_shift + 264U, // USHLLv4i16_shift + 262U, // USHLLv4i32_shift + 262U, // USHLLv8i16_shift + 264U, // USHLLv8i8_shift + 33095U, // USHLv16i8 + 261U, // USHLv1i64 + 41287U, // USHLv2i32 + 8517U, // USHLv2i64 + 49480U, // USHLv4i16 + 16710U, // USHLv4i32 + 24902U, // USHLv8i16 + 57672U, // USHLv8i8 + 261U, // USHRd + 263U, // USHRv16i8_shift + 263U, // USHRv2i32_shift + 261U, // USHRv2i64_shift + 264U, // USHRv4i16_shift + 262U, // USHRv4i32_shift + 262U, // USHRv8i16_shift + 264U, // USHRv8i8_shift + 1U, // USQADDv16i8 + 1U, // USQADDv1i16 + 1U, // USQADDv1i32 + 1U, // USQADDv1i64 + 1U, // USQADDv1i8 + 2U, // USQADDv2i32 + 2U, // USQADDv2i64 + 3U, // USQADDv4i16 + 3U, // USQADDv4i32 + 4U, // USQADDv8i16 + 4U, // USQADDv8i8 + 2309U, // USRAd + 2311U, // USRAv16i8_shift + 2311U, // USRAv2i32_shift + 2309U, // USRAv2i64_shift + 2312U, // USRAv4i16_shift + 2310U, // USRAv4i32_shift + 2310U, // USRAv8i16_shift + 2312U, // USRAv8i8_shift + 33095U, // USUBLv16i8_v8i16 + 41287U, // USUBLv2i32_v2i64 + 49480U, // USUBLv4i16_v4i32 + 16710U, // USUBLv4i32_v2i64 + 24902U, // USUBLv8i16_v4i32 + 57672U, // USUBLv8i8_v8i16 + 33094U, // USUBWv16i8_v8i16 + 41285U, // USUBWv2i32_v2i64 + 49478U, // USUBWv4i16_v4i32 + 16709U, // USUBWv4i32_v2i64 + 24902U, // USUBWv8i16_v4i32 + 57670U, // USUBWv8i8_v8i16 + 1U, // UUNPKHI_ZZ_D + 0U, // UUNPKHI_ZZ_H + 1U, // UUNPKHI_ZZ_S + 1U, // UUNPKLO_ZZ_D + 0U, // UUNPKLO_ZZ_H + 1U, // UUNPKLO_ZZ_S + 64U, // UXTB_ZPmZ_D + 128U, // UXTB_ZPmZ_H + 192U, // UXTB_ZPmZ_S + 64U, // UXTH_ZPmZ_D + 192U, // UXTH_ZPmZ_S + 64U, // UXTW_ZPmZ_D + 837U, // UZP1_PPP_B + 901U, // UZP1_PPP_D + 137U, // UZP1_PPP_H + 1029U, // UZP1_PPP_S + 837U, // UZP1_ZZZ_B + 901U, // UZP1_ZZZ_D + 137U, // UZP1_ZZZ_H + 1029U, // UZP1_ZZZ_S + 33095U, // UZP1v16i8 + 41287U, // UZP1v2i32 + 8517U, // UZP1v2i64 + 49480U, // UZP1v4i16 + 16710U, // UZP1v4i32 + 24902U, // UZP1v8i16 + 57672U, // UZP1v8i8 + 837U, // UZP2_PPP_B + 901U, // UZP2_PPP_D + 137U, // UZP2_PPP_H + 1029U, // UZP2_PPP_S + 837U, // UZP2_ZZZ_B + 901U, // UZP2_ZZZ_D + 137U, // UZP2_ZZZ_H + 1029U, // UZP2_ZZZ_S + 33095U, // UZP2v16i8 + 41287U, // UZP2v2i32 + 8517U, // UZP2v2i64 + 49480U, // UZP2v4i16 + 16710U, // UZP2v4i32 + 24902U, // UZP2v8i16 + 57672U, // UZP2v8i8 + 261U, // WHILELE_PWW_B + 261U, // WHILELE_PWW_D + 11U, // WHILELE_PWW_H + 261U, // WHILELE_PWW_S + 261U, // WHILELE_PXX_B + 261U, // WHILELE_PXX_D + 11U, // WHILELE_PXX_H + 261U, // WHILELE_PXX_S + 261U, // WHILELO_PWW_B + 261U, // WHILELO_PWW_D + 11U, // WHILELO_PWW_H + 261U, // WHILELO_PWW_S + 261U, // WHILELO_PXX_B + 261U, // WHILELO_PXX_D + 11U, // WHILELO_PXX_H + 261U, // WHILELO_PXX_S + 261U, // WHILELS_PWW_B + 261U, // WHILELS_PWW_D + 11U, // WHILELS_PWW_H + 261U, // WHILELS_PWW_S + 261U, // WHILELS_PXX_B + 261U, // WHILELS_PXX_D + 11U, // WHILELS_PXX_H + 261U, // WHILELS_PXX_S + 261U, // WHILELT_PWW_B + 261U, // WHILELT_PWW_D + 11U, // WHILELT_PWW_H + 261U, // WHILELT_PWW_S + 261U, // WHILELT_PXX_B + 261U, // WHILELT_PXX_D + 11U, // WHILELT_PXX_H + 261U, // WHILELT_PXX_S + 0U, // WRFFR + 2253125U, // XAR + 0U, // XPACD + 0U, // XPACI + 0U, // XPACLRI + 4U, // XTNv16i8 + 2U, // XTNv2i32 + 3U, // XTNv4i16 + 2U, // XTNv4i32 + 3U, // XTNv8i16 + 4U, // XTNv8i8 + 837U, // ZIP1_PPP_B + 901U, // ZIP1_PPP_D + 137U, // ZIP1_PPP_H + 1029U, // ZIP1_PPP_S + 837U, // ZIP1_ZZZ_B + 901U, // ZIP1_ZZZ_D + 137U, // ZIP1_ZZZ_H + 1029U, // ZIP1_ZZZ_S + 33095U, // ZIP1v16i8 + 41287U, // ZIP1v2i32 + 8517U, // ZIP1v2i64 + 49480U, // ZIP1v4i16 + 16710U, // ZIP1v4i32 + 24902U, // ZIP1v8i16 + 57672U, // ZIP1v8i8 + 837U, // ZIP2_PPP_B + 901U, // ZIP2_PPP_D + 137U, // ZIP2_PPP_H + 1029U, // ZIP2_PPP_S + 837U, // ZIP2_ZZZ_B + 901U, // ZIP2_ZZZ_D + 137U, // ZIP2_ZZZ_H + 1029U, // ZIP2_ZZZ_S + 33095U, // ZIP2v16i8 + 41287U, // ZIP2v2i32 + 8517U, // ZIP2v2i64 + 49480U, // ZIP2v4i16 + 16710U, // ZIP2v4i32 + 24902U, // ZIP2v8i16 + 57672U, // ZIP2v8i8 + 837U, // anonymous_1349 }; unsigned int opcode = MCInst_getOpcode(MI); @@ -9860,7 +15072,7 @@ static void printInstruction(MCInst *MI, SStream *O) Bits |= (uint64_t)OpInfo0[opcode] << 0; Bits |= (uint64_t)OpInfo1[opcode] << 32; #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 8191)-1); + SStream_concat0(O, AsmStrs + (Bits & 8191) - 1); #endif // Fragment 0 encoded into 6 bits for 54 unique commands. @@ -9960,13 +15172,13 @@ static void printInstruction(MCInst *MI, SStream *O) break; case 16: // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... - printTypedVectorList(MI, 0, O, 0,'d'); + printTypedVectorList(MI, 0, O, 0, 'd'); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 0); break; case 17: // GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE... - printTypedVectorList(MI, 0, O, 0,'s'); + printTypedVectorList(MI, 0, O, 0, 's'); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 0); break; @@ -9977,13 +15189,13 @@ static void printInstruction(MCInst *MI, SStream *O) break; case 19: // LD1B, LD1B_IMM_REAL, LD1RB_IMM, LD1RQ_B, LD1RQ_B_IMM, LD2B, LD2B_IMM, ... - printTypedVectorList(MI, 0, O, 0,'b'); + printTypedVectorList(MI, 0, O, 0, 'b'); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 0); break; case 20: // LD1B_H, LD1B_H_IMM_REAL, LD1H, LD1H_IMM_REAL, LD1RB_H_IMM, LD1RH_IMM, ... - printTypedVectorList(MI, 0, O, 0,'h'); + printTypedVectorList(MI, 0, O, 0, 'h'); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 0); break; @@ -10287,7 +15499,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 1 encoded into 6 bits for 56 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 19) & 63)); switch ((Bits >> 19) & 63) { @@ -10576,14 +15787,13 @@ static void printInstruction(MCInst *MI, SStream *O) break; case 55: // TBL_ZZZ_H - printTypedVectorList(MI, 1, O, 0,'h'); + printTypedVectorList(MI, 1, O, 0, 'h'); SStream_concat0(O, ", "); printSVERegOp(MI, 2, O, 'h'); return; break; } - // Fragment 2 encoded into 6 bits for 57 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 25) & 63)); switch ((Bits >> 25) & 63) { @@ -10866,21 +16076,21 @@ static void printInstruction(MCInst *MI, SStream *O) break; case 52: // TBL_ZZZ_B - printTypedVectorList(MI, 1, O, 0,'b'); + printTypedVectorList(MI, 1, O, 0, 'b'); SStream_concat0(O, ", "); printSVERegOp(MI, 2, O, 'b'); return; break; case 53: // TBL_ZZZ_D - printTypedVectorList(MI, 1, O, 0,'d'); + printTypedVectorList(MI, 1, O, 0, 'd'); SStream_concat0(O, ", "); printSVERegOp(MI, 2, O, 'd'); return; break; case 54: // TBL_ZZZ_S - printTypedVectorList(MI, 1, O, 0,'s'); + printTypedVectorList(MI, 1, O, 0, 's'); SStream_concat0(O, ", "); printSVERegOp(MI, 2, O, 's'); return; @@ -10899,7 +16109,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 3 encoded into 7 bits for 91 unique commands. // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 31) & 127)); switch ((Bits >> 31) & 127) { @@ -11456,7 +16665,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 4 encoded into 7 bits for 88 unique commands. // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 38) & 127)); switch ((Bits >> 38) & 127) { @@ -11986,7 +17194,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 5 encoded into 6 bits for 36 unique commands. // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 45) & 63)); switch ((Bits >> 45) & 63) { @@ -12187,7 +17394,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 6 encoded into 6 bits for 38 unique commands. // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 51) & 63)); switch ((Bits >> 51) & 63) { @@ -12399,7 +17605,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 7 encoded into 3 bits for 7 unique commands. // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 57) & 7)); switch ((Bits >> 57) & 7) { @@ -12442,7 +17647,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 8 encoded into 1 bits for 2 unique commands. // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 60) & 1)); if ((Bits >> 60) & 1) { @@ -12454,24 +17658,23 @@ static void printInstruction(MCInst *MI, SStream *O) printComplexRotationOp(MI, 4, O, 180, 90); return; } - } - - #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, - unsigned PredicateIndex); -static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) -{ - #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) + unsigned PredicateIndex); +static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) { +#define GETREGCLASS_CONTAIN(_class, _reg) \ + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), \ + MCOperand_getReg(MCInst_getOperand(MI, _reg))) unsigned int I = 0, OpIdx, PrintMethodIdx; char *tmpString; const char *AsmString; switch (MCInst_getOpcode(MI)) { - default: return false; + default: + return false; case AArch64_ADDSWri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && @@ -12897,7 +18100,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 2)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; @@ -12943,7 +18147,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 2)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; @@ -13369,7 +18574,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; @@ -13393,7 +18599,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; @@ -13417,7 +18624,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; @@ -13441,7 +18649,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; @@ -13455,7 +18664,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; @@ -13469,7 +18679,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; @@ -14010,7 +19221,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) AsmString = "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; @@ -14056,7 +19268,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) AsmString = "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; @@ -14099,7 +19312,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) AsmString = "ror $\x01, $\x02, $\x04"; break; @@ -14112,7 +19326,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) AsmString = "ror $\x01, $\x02, $\x04"; break; @@ -14276,7 +19491,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14292,7 +19508,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - AsmString = "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + AsmString = + "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; @@ -14308,7 +19525,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14324,7 +19542,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - AsmString = "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + AsmString = + "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; @@ -14340,7 +19559,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14388,7 +19608,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14404,7 +19625,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - AsmString = "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + AsmString = + "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; @@ -14420,7 +19642,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14436,7 +19659,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14452,7 +19676,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - AsmString = "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + AsmString = + "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; @@ -14468,7 +19693,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14484,7 +19710,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - AsmString = "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + AsmString = + "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; @@ -14500,7 +19727,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14516,7 +19744,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - AsmString = "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + AsmString = + "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; @@ -14532,7 +19761,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14548,7 +19778,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - AsmString = "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + AsmString = + "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; @@ -14564,7 +19795,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - AsmString = "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + AsmString = + "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; @@ -14821,8 +20053,10 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { - // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - AsmString = "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19"; + // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, + // VectorIndexH:$idx2) + AsmString = + "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19"; break; } return NULL; @@ -14845,8 +20079,10 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { - // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - AsmString = "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19"; + // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, + // VectorIndexS:$idx2) + AsmString = + "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19"; break; } return NULL; @@ -14869,8 +20105,10 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { - // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - AsmString = "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19"; + // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, + // VectorIndexD:$idx2) + AsmString = + "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19"; break; } return NULL; @@ -14893,8 +20131,10 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { - // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - AsmString = "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19"; + // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, + // VectorIndexB:$idx2) + AsmString = + "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19"; break; } return NULL; @@ -19605,9 +24845,11 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x06"; @@ -19675,9 +24917,11 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x06"; @@ -19720,7 +24964,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x10"; @@ -19734,7 +24979,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (ORRv16i8 V128:$dst, V128:$src, V128:$src) AsmString = "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b"; break; @@ -19747,7 +24993,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (ORRv8i8 V64:$dst, V64:$src, V64:$src) AsmString = "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b"; break; @@ -20210,7 +25457,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; @@ -20226,7 +25474,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; @@ -20242,7 +25491,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10"; @@ -20258,7 +25508,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09"; @@ -20274,7 +25525,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B"; @@ -24002,11 +29254,10 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) return NULL; } - tmpString = cs_strdup(AsmString); - while (AsmString[I] != ' ' && AsmString[I] != '\t' && - AsmString[I] != '$' && AsmString[I] != '\0') + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') ++I; tmpString[I] = 0; @@ -24027,8 +29278,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) PrintMethodIdx = AsmString[I++] - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else { - printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); - } + printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); + } } else { if (AsmString[I] == '[') { set_mem_access(MI, true); @@ -24042,12 +29293,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) return tmpString; } - -static void printCustomAliasOperand( - MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - SStream *OS) -{ + +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { switch (PrintMethodIdx) { default: break; @@ -24145,19 +29393,19 @@ static void printCustomAliasOperand( printFPImmOperand(MI, OpIdx, OS); break; case 31: - printTypedVectorList(MI, OpIdx, OS, 0,'d'); + printTypedVectorList(MI, OpIdx, OS, 0, 'd'); break; case 32: - printTypedVectorList(MI, OpIdx, OS, 0,'s'); + printTypedVectorList(MI, OpIdx, OS, 0, 's'); break; case 33: printPSBHintOp(MI, OpIdx, OS); break; case 34: - printTypedVectorList(MI, OpIdx, OS, 0,'h'); + printTypedVectorList(MI, OpIdx, OS, 0, 'h'); break; case 35: - printTypedVectorList(MI, OpIdx, OS, 0,'b'); + printTypedVectorList(MI, OpIdx, OS, 0, 'b'); break; case 36: printTypedVectorList(MI, OpIdx, OS, 16, 'b'); @@ -24214,7 +29462,7 @@ static void printCustomAliasOperand( } static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, - unsigned PredicateIndex) { + unsigned PredicateIndex) { int64_t Val; switch (PredicateIndex) { default: @@ -24226,31 +29474,26 @@ static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, return false; Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements8(Val); - - } + } case 2: { if (!MCOperand_isImm(MCOp)) return false; Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements16(Val); - - } + } case 3: { if (!MCOperand_isImm(MCOp)) return false; Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements32(Val); - - } + } case 4: { - return MCOperand_isImm(MCOp) && - MCOperand_getImm(MCOp) != AArch64CC_AL && + return MCOperand_isImm(MCOp) && MCOperand_getImm(MCOp) != AArch64CC_AL && MCOperand_getImm(MCOp) != AArch64CC_NV; - - } + } case 5: { if (!MCOperand_isImm(MCOp)) @@ -24258,8 +29501,7 @@ static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements16(Val) && AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val); - - } + } case 6: { if (!MCOperand_isImm(MCOp)) @@ -24267,8 +29509,7 @@ static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements32(Val) && AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val); - - } + } case 7: { if (!MCOperand_isImm(MCOp)) @@ -24276,8 +29517,7 @@ static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements64(Val) && AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val); - - } + } case 8: { // Check, if operand is valid, to fix exhaustive aliasing in disassembly. @@ -24285,8 +29525,7 @@ static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, if (!MCOperand_isImm(MCOp)) return false; return AArch64PSBHint_lookupPSBByEncoding(MCOperand_getImm(MCOp)) != NULL; - - } + } } } diff --git a/arch/AArch64/AArch64GenDisassemblerTables.inc b/arch/AArch64/AArch64GenDisassemblerTables.inc index 76323be71f..3237f74be8 100644 --- a/arch/AArch64/AArch64GenDisassemblerTables.inc +++ b/arch/AArch64/AArch64GenDisassemblerTables.inc @@ -1,22561 +1,173254 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2019 */ +/* By Phosphorus15 , Year 2021 */ +/* This generator is under https://github.com/rizinorg/llvm-capstone */ /* Automatically generated file, do not edit! */ -#include "../../MCInst.h" #include "../../LEB128.h" +#include "../../MCInst.h" +#define AArch64_FeatureAES 0ULL +#define AArch64_FeatureAM 1ULL +#define AArch64_FeatureAMVS 2ULL +#define AArch64_FeatureAggressiveFMA 3ULL +#define AArch64_FeatureAltFPCmp 4ULL +#define AArch64_FeatureAlternateSExtLoadCVTF32Pattern 5ULL +#define AArch64_FeatureAppleA7SysReg 6ULL +#define AArch64_FeatureArithmeticBccFusion 7ULL +#define AArch64_FeatureArithmeticCbzFusion 8ULL +#define AArch64_FeatureBF16 9ULL +#define AArch64_FeatureBRBE 10ULL +#define AArch64_FeatureBalanceFPOps 11ULL +#define AArch64_FeatureBranchTargetId 12ULL +#define AArch64_FeatureCCIDX 13ULL +#define AArch64_FeatureCCPP 14ULL +#define AArch64_FeatureCONTEXTIDREL2 15ULL +#define AArch64_FeatureCRC 16ULL +#define AArch64_FeatureCacheDeepPersist 17ULL +#define AArch64_FeatureCallSavedX8 18ULL +#define AArch64_FeatureCallSavedX9 19ULL +#define AArch64_FeatureCallSavedX10 20ULL +#define AArch64_FeatureCallSavedX11 21ULL +#define AArch64_FeatureCallSavedX12 22ULL +#define AArch64_FeatureCallSavedX13 23ULL +#define AArch64_FeatureCallSavedX14 24ULL +#define AArch64_FeatureCallSavedX15 25ULL +#define AArch64_FeatureCallSavedX18 26ULL +#define AArch64_FeatureCmpBccFusion 27ULL +#define AArch64_FeatureComplxNum 28ULL +#define AArch64_FeatureCrypto 29ULL +#define AArch64_FeatureCustomCheapAsMoveHandling 30ULL +#define AArch64_FeatureDIT 31ULL +#define AArch64_FeatureDisableLatencySchedHeuristic 32ULL +#define AArch64_FeatureDotProd 33ULL +#define AArch64_FeatureEL2VMSA 34ULL +#define AArch64_FeatureEL3 35ULL +#define AArch64_FeatureETE 36ULL +#define AArch64_FeatureEnhancedCounterVirtualization 37ULL +#define AArch64_FeatureExperimentalZeroingPseudos 38ULL +#define AArch64_FeatureExynosCheapAsMoveHandling 39ULL +#define AArch64_FeatureFP16FML 40ULL +#define AArch64_FeatureFPARMv8 41ULL +#define AArch64_FeatureFRInt3264 42ULL +#define AArch64_FeatureFineGrainedTraps 43ULL +#define AArch64_FeatureFlagM 44ULL +#define AArch64_FeatureForce32BitJumpTables 45ULL +#define AArch64_FeatureFullFP16 46ULL +#define AArch64_FeatureFuseAES 47ULL +#define AArch64_FeatureFuseAddress 48ULL +#define AArch64_FeatureFuseArithmeticLogic 49ULL +#define AArch64_FeatureFuseCCSelect 50ULL +#define AArch64_FeatureFuseCryptoEOR 51ULL +#define AArch64_FeatureFuseLiterals 52ULL +#define AArch64_FeatureHCX 53ULL +#define AArch64_FeatureHardenSlsBlr 54ULL +#define AArch64_FeatureHardenSlsNoComdat 55ULL +#define AArch64_FeatureHardenSlsRetBr 56ULL +#define AArch64_FeatureJS 57ULL +#define AArch64_FeatureLOR 58ULL +#define AArch64_FeatureLS64 59ULL +#define AArch64_FeatureLSE 60ULL +#define AArch64_FeatureLSE2 61ULL +#define AArch64_FeatureLSLFast 62ULL +#define AArch64_FeatureMPAM 63ULL +#define AArch64_FeatureMTE 64ULL +#define AArch64_FeatureMatMulFP32 65ULL +#define AArch64_FeatureMatMulFP64 66ULL +#define AArch64_FeatureMatMulInt8 67ULL +#define AArch64_FeatureNEON 68ULL +#define AArch64_FeatureNV 69ULL +#define AArch64_FeatureNoNegativeImmediates 70ULL +#define AArch64_FeatureNoZCZeroingFP 71ULL +#define AArch64_FeatureOutlineAtomics 72ULL +#define AArch64_FeaturePAN 73ULL +#define AArch64_FeaturePAN_RWV 74ULL +#define AArch64_FeaturePAuth 75ULL +#define AArch64_FeaturePerfMon 76ULL +#define AArch64_FeaturePostRAScheduler 77ULL +#define AArch64_FeaturePredRes 78ULL +#define AArch64_FeaturePredictableSelectIsExpensive 79ULL +#define AArch64_FeaturePsUAO 80ULL +#define AArch64_FeatureRAS 81ULL +#define AArch64_FeatureRCPC 82ULL +#define AArch64_FeatureRCPC_IMMO 83ULL +#define AArch64_FeatureRDM 84ULL +#define AArch64_FeatureRME 85ULL +#define AArch64_FeatureRandGen 86ULL +#define AArch64_FeatureReserveX1 87ULL +#define AArch64_FeatureReserveX2 88ULL +#define AArch64_FeatureReserveX3 89ULL +#define AArch64_FeatureReserveX4 90ULL +#define AArch64_FeatureReserveX5 91ULL +#define AArch64_FeatureReserveX6 92ULL +#define AArch64_FeatureReserveX7 93ULL +#define AArch64_FeatureReserveX9 94ULL +#define AArch64_FeatureReserveX10 95ULL +#define AArch64_FeatureReserveX11 96ULL +#define AArch64_FeatureReserveX12 97ULL +#define AArch64_FeatureReserveX13 98ULL +#define AArch64_FeatureReserveX14 99ULL +#define AArch64_FeatureReserveX15 100ULL +#define AArch64_FeatureReserveX18 101ULL +#define AArch64_FeatureReserveX20 102ULL +#define AArch64_FeatureReserveX21 103ULL +#define AArch64_FeatureReserveX22 104ULL +#define AArch64_FeatureReserveX23 105ULL +#define AArch64_FeatureReserveX24 106ULL +#define AArch64_FeatureReserveX25 107ULL +#define AArch64_FeatureReserveX26 108ULL +#define AArch64_FeatureReserveX27 109ULL +#define AArch64_FeatureReserveX28 110ULL +#define AArch64_FeatureReserveX30 111ULL +#define AArch64_FeatureSB 112ULL +#define AArch64_FeatureSEL2 113ULL +#define AArch64_FeatureSHA2 114ULL +#define AArch64_FeatureSHA3 115ULL +#define AArch64_FeatureSM4 116ULL +#define AArch64_FeatureSME 117ULL +#define AArch64_FeatureSMEF64 118ULL +#define AArch64_FeatureSMEI64 119ULL +#define AArch64_FeatureSPE 120ULL +#define AArch64_FeatureSPE_EEF 121ULL +#define AArch64_FeatureSSBS 122ULL +#define AArch64_FeatureSVE 123ULL +#define AArch64_FeatureSVE2 124ULL +#define AArch64_FeatureSVE2AES 125ULL +#define AArch64_FeatureSVE2BitPerm 126ULL +#define AArch64_FeatureSVE2SHA3 127ULL +#define AArch64_FeatureSVE2SM4 128ULL +#define AArch64_FeatureSlowMisaligned128Store 129ULL +#define AArch64_FeatureSlowPaired128 130ULL +#define AArch64_FeatureSlowSTRQro 131ULL +#define AArch64_FeatureSpecRestrict 132ULL +#define AArch64_FeatureStreamingSVE 133ULL +#define AArch64_FeatureStrictAlign 134ULL +#define AArch64_FeatureTLB_RMI 135ULL +#define AArch64_FeatureTME 136ULL +#define AArch64_FeatureTRACEV8_4 137ULL +#define AArch64_FeatureTRBE 138ULL +#define AArch64_FeatureTaggedGlobals 139ULL +#define AArch64_FeatureUseEL1ForTP 140ULL +#define AArch64_FeatureUseEL2ForTP 141ULL +#define AArch64_FeatureUseEL3ForTP 142ULL +#define AArch64_FeatureUseRSqrt 143ULL +#define AArch64_FeatureUseScalarIncVL 144ULL +#define AArch64_FeatureVH 145ULL +#define AArch64_FeatureWFxT 146ULL +#define AArch64_FeatureXS 147ULL +#define AArch64_FeatureZCRegMove 148ULL +#define AArch64_FeatureZCZeroing 149ULL +#define AArch64_FeatureZCZeroingFPWorkaround 150ULL +#define AArch64_FeatureZCZeroingGP 151ULL +#define AArch64_HasV8_0aOps 152ULL +#define AArch64_HasV8_0rOps 153ULL +#define AArch64_HasV8_1aOps 154ULL +#define AArch64_HasV8_2aOps 155ULL +#define AArch64_HasV8_3aOps 156ULL +#define AArch64_HasV8_4aOps 157ULL +#define AArch64_HasV8_5aOps 158ULL +#define AArch64_HasV8_6aOps 159ULL +#define AArch64_HasV8_7aOps 160ULL +#define AArch64_HasV9_0aOps 161ULL +#define AArch64_HasV9_1aOps 162ULL +#define AArch64_HasV9_2aOps 163ULL +#define AArch64_TuneA35 164ULL +#define AArch64_TuneA53 165ULL +#define AArch64_TuneA55 166ULL +#define AArch64_TuneA57 167ULL +#define AArch64_TuneA64FX 168ULL +#define AArch64_TuneA65 169ULL +#define AArch64_TuneA72 170ULL +#define AArch64_TuneA73 171ULL +#define AArch64_TuneA75 172ULL +#define AArch64_TuneA76 173ULL +#define AArch64_TuneA77 174ULL +#define AArch64_TuneA78 175ULL +#define AArch64_TuneA78C 176ULL +#define AArch64_TuneA510 177ULL +#define AArch64_TuneA710 178ULL +#define AArch64_TuneAppleA7 179ULL +#define AArch64_TuneAppleA10 180ULL +#define AArch64_TuneAppleA11 181ULL +#define AArch64_TuneAppleA12 182ULL +#define AArch64_TuneAppleA13 183ULL +#define AArch64_TuneAppleA14 184ULL +#define AArch64_TuneCarmel 185ULL +#define AArch64_TuneExynosM3 186ULL +#define AArch64_TuneExynosM4 187ULL +#define AArch64_TuneFalkor 188ULL +#define AArch64_TuneKryo 189ULL +#define AArch64_TuneNeoverse512TVB 190ULL +#define AArch64_TuneNeoverseE1 191ULL +#define AArch64_TuneNeoverseN1 192ULL +#define AArch64_TuneNeoverseN2 193ULL +#define AArch64_TuneNeoverseV1 194ULL +#define AArch64_TuneR82 195ULL +#define AArch64_TuneSaphira 196ULL +#define AArch64_TuneTSV110 197ULL +#define AArch64_TuneThunderX 198ULL +#define AArch64_TuneThunderX2T99 199ULL +#define AArch64_TuneThunderX3T110 200ULL +#define AArch64_TuneThunderXT81 201ULL +#define AArch64_TuneThunderXT83 202ULL +#define AArch64_TuneThunderXT88 203ULL +#define AArch64_TuneX1 204ULL +#define AArch64_TuneX2 205ULL +#ifdef MIPS_GET_DISASSEMBLER +#undef MIPS_GET_DISASSEMBLER // Helper function for extracting fields from encoded instructions. - -//#if defined(_MSC_VER) && !defined(__clang__) -//__declspec(noinline) -//#endif - -#define FieldFromInstruction(fname, InsnType) \ -static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ -{ \ - InsnType fieldMask; \ - if (numBits == sizeof(InsnType) * 8) \ - fieldMask = (InsnType)(-1LL); \ - else \ - fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ - return (insn & fieldMask) >> startBit; \ -} +#define FieldFromInstruction(fname, InsnType) \ + static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ + } static const uint8_t DecoderTable32[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 3, // Inst{28-26} ... -/* 3 */ MCD_OPC_FilterValue, 1, 215, 111, 0, // Skip to: 28639 -/* 8 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 11 */ MCD_OPC_FilterValue, 0, 120, 43, 0, // Skip to: 11144 -/* 16 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 19 */ MCD_OPC_FilterValue, 0, 209, 17, 0, // Skip to: 4585 -/* 24 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 27 */ MCD_OPC_FilterValue, 0, 22, 8, 0, // Skip to: 2102 -/* 32 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 35 */ MCD_OPC_FilterValue, 0, 67, 2, 0, // Skip to: 619 -/* 40 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 43 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 79 -/* 48 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 51 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 65 -/* 56 */ MCD_OPC_CheckPredicate, 0, 103, 83, 1, // Skip to: 86948 -/* 61 */ MCD_OPC_Decode, 185, 1, 0, // Opcode: ADD_ZPmZ_B -/* 65 */ MCD_OPC_FilterValue, 1, 94, 83, 1, // Skip to: 86948 -/* 70 */ MCD_OPC_CheckPredicate, 0, 89, 83, 1, // Skip to: 86948 -/* 75 */ MCD_OPC_Decode, 187, 1, 0, // Opcode: ADD_ZPmZ_H -/* 79 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 115 -/* 84 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 87 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 101 -/* 92 */ MCD_OPC_CheckPredicate, 0, 67, 83, 1, // Skip to: 86948 -/* 97 */ MCD_OPC_Decode, 247, 29, 0, // Opcode: SUB_ZPmZ_B -/* 101 */ MCD_OPC_FilterValue, 1, 58, 83, 1, // Skip to: 86948 -/* 106 */ MCD_OPC_CheckPredicate, 0, 53, 83, 1, // Skip to: 86948 -/* 111 */ MCD_OPC_Decode, 249, 29, 0, // Opcode: SUB_ZPmZ_H -/* 115 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 151 -/* 120 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 123 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 137 -/* 128 */ MCD_OPC_CheckPredicate, 0, 31, 83, 1, // Skip to: 86948 -/* 133 */ MCD_OPC_Decode, 221, 29, 0, // Opcode: SUBR_ZPmZ_B -/* 137 */ MCD_OPC_FilterValue, 1, 22, 83, 1, // Skip to: 86948 -/* 142 */ MCD_OPC_CheckPredicate, 0, 17, 83, 1, // Skip to: 86948 -/* 147 */ MCD_OPC_Decode, 223, 29, 0, // Opcode: SUBR_ZPmZ_H -/* 151 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 187 -/* 156 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 159 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 173 -/* 164 */ MCD_OPC_CheckPredicate, 0, 251, 82, 1, // Skip to: 86948 -/* 169 */ MCD_OPC_Decode, 196, 23, 0, // Opcode: SMAX_ZPmZ_B -/* 173 */ MCD_OPC_FilterValue, 1, 242, 82, 1, // Skip to: 86948 -/* 178 */ MCD_OPC_CheckPredicate, 0, 237, 82, 1, // Skip to: 86948 -/* 183 */ MCD_OPC_Decode, 198, 23, 0, // Opcode: SMAX_ZPmZ_H -/* 187 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 223 -/* 192 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 195 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 209 -/* 200 */ MCD_OPC_CheckPredicate, 0, 215, 82, 1, // Skip to: 86948 -/* 205 */ MCD_OPC_Decode, 252, 31, 0, // Opcode: UMAX_ZPmZ_B -/* 209 */ MCD_OPC_FilterValue, 1, 206, 82, 1, // Skip to: 86948 -/* 214 */ MCD_OPC_CheckPredicate, 0, 201, 82, 1, // Skip to: 86948 -/* 219 */ MCD_OPC_Decode, 254, 31, 0, // Opcode: UMAX_ZPmZ_H -/* 223 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 259 -/* 228 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 231 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 245 -/* 236 */ MCD_OPC_CheckPredicate, 0, 179, 82, 1, // Skip to: 86948 -/* 241 */ MCD_OPC_Decode, 226, 23, 0, // Opcode: SMIN_ZPmZ_B -/* 245 */ MCD_OPC_FilterValue, 1, 170, 82, 1, // Skip to: 86948 -/* 250 */ MCD_OPC_CheckPredicate, 0, 165, 82, 1, // Skip to: 86948 -/* 255 */ MCD_OPC_Decode, 228, 23, 0, // Opcode: SMIN_ZPmZ_H -/* 259 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 295 -/* 264 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 281 -/* 272 */ MCD_OPC_CheckPredicate, 0, 143, 82, 1, // Skip to: 86948 -/* 277 */ MCD_OPC_Decode, 153, 32, 0, // Opcode: UMIN_ZPmZ_B -/* 281 */ MCD_OPC_FilterValue, 1, 134, 82, 1, // Skip to: 86948 -/* 286 */ MCD_OPC_CheckPredicate, 0, 129, 82, 1, // Skip to: 86948 -/* 291 */ MCD_OPC_Decode, 155, 32, 0, // Opcode: UMIN_ZPmZ_H -/* 295 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 331 -/* 300 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 303 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 317 -/* 308 */ MCD_OPC_CheckPredicate, 0, 107, 82, 1, // Skip to: 86948 -/* 313 */ MCD_OPC_Decode, 136, 22, 0, // Opcode: SABD_ZPmZ_B -/* 317 */ MCD_OPC_FilterValue, 1, 98, 82, 1, // Skip to: 86948 -/* 322 */ MCD_OPC_CheckPredicate, 0, 93, 82, 1, // Skip to: 86948 -/* 327 */ MCD_OPC_Decode, 138, 22, 0, // Opcode: SABD_ZPmZ_H -/* 331 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 367 -/* 336 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 339 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 353 -/* 344 */ MCD_OPC_CheckPredicate, 0, 71, 82, 1, // Skip to: 86948 -/* 349 */ MCD_OPC_Decode, 254, 30, 0, // Opcode: UABD_ZPmZ_B -/* 353 */ MCD_OPC_FilterValue, 1, 62, 82, 1, // Skip to: 86948 -/* 358 */ MCD_OPC_CheckPredicate, 0, 57, 82, 1, // Skip to: 86948 -/* 363 */ MCD_OPC_Decode, 128, 31, 0, // Opcode: UABD_ZPmZ_H -/* 367 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 403 -/* 372 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 375 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 389 -/* 380 */ MCD_OPC_CheckPredicate, 0, 35, 82, 1, // Skip to: 86948 -/* 385 */ MCD_OPC_Decode, 153, 20, 0, // Opcode: MUL_ZPmZ_B -/* 389 */ MCD_OPC_FilterValue, 1, 26, 82, 1, // Skip to: 86948 -/* 394 */ MCD_OPC_CheckPredicate, 0, 21, 82, 1, // Skip to: 86948 -/* 399 */ MCD_OPC_Decode, 155, 20, 0, // Opcode: MUL_ZPmZ_H -/* 403 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 439 -/* 408 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 411 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 425 -/* 416 */ MCD_OPC_CheckPredicate, 0, 255, 81, 1, // Skip to: 86948 -/* 421 */ MCD_OPC_Decode, 134, 24, 0, // Opcode: SMULH_ZPmZ_B -/* 425 */ MCD_OPC_FilterValue, 1, 246, 81, 1, // Skip to: 86948 -/* 430 */ MCD_OPC_CheckPredicate, 0, 241, 81, 1, // Skip to: 86948 -/* 435 */ MCD_OPC_Decode, 136, 24, 0, // Opcode: SMULH_ZPmZ_H -/* 439 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 475 -/* 444 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 447 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 461 -/* 452 */ MCD_OPC_CheckPredicate, 0, 219, 81, 1, // Skip to: 86948 -/* 457 */ MCD_OPC_Decode, 188, 32, 0, // Opcode: UMULH_ZPmZ_B -/* 461 */ MCD_OPC_FilterValue, 1, 210, 81, 1, // Skip to: 86948 -/* 466 */ MCD_OPC_CheckPredicate, 0, 205, 81, 1, // Skip to: 86948 -/* 471 */ MCD_OPC_Decode, 190, 32, 0, // Opcode: UMULH_ZPmZ_H -/* 475 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 511 -/* 480 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 483 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 497 -/* 488 */ MCD_OPC_CheckPredicate, 0, 183, 81, 1, // Skip to: 86948 -/* 493 */ MCD_OPC_Decode, 212, 20, 0, // Opcode: ORR_ZPmZ_B -/* 497 */ MCD_OPC_FilterValue, 1, 174, 81, 1, // Skip to: 86948 -/* 502 */ MCD_OPC_CheckPredicate, 0, 169, 81, 1, // Skip to: 86948 -/* 507 */ MCD_OPC_Decode, 214, 20, 0, // Opcode: ORR_ZPmZ_H -/* 511 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 547 -/* 516 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 519 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 533 -/* 524 */ MCD_OPC_CheckPredicate, 0, 147, 81, 1, // Skip to: 86948 -/* 529 */ MCD_OPC_Decode, 240, 5, 0, // Opcode: EOR_ZPmZ_B -/* 533 */ MCD_OPC_FilterValue, 1, 138, 81, 1, // Skip to: 86948 -/* 538 */ MCD_OPC_CheckPredicate, 0, 133, 81, 1, // Skip to: 86948 -/* 543 */ MCD_OPC_Decode, 242, 5, 0, // Opcode: EOR_ZPmZ_H -/* 547 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 583 -/* 552 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 555 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 569 -/* 560 */ MCD_OPC_CheckPredicate, 0, 111, 81, 1, // Skip to: 86948 -/* 565 */ MCD_OPC_Decode, 247, 1, 0, // Opcode: AND_ZPmZ_B -/* 569 */ MCD_OPC_FilterValue, 1, 102, 81, 1, // Skip to: 86948 -/* 574 */ MCD_OPC_CheckPredicate, 0, 97, 81, 1, // Skip to: 86948 -/* 579 */ MCD_OPC_Decode, 249, 1, 0, // Opcode: AND_ZPmZ_H -/* 583 */ MCD_OPC_FilterValue, 27, 88, 81, 1, // Skip to: 86948 -/* 588 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 591 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 605 -/* 596 */ MCD_OPC_CheckPredicate, 0, 75, 81, 1, // Skip to: 86948 -/* 601 */ MCD_OPC_Decode, 182, 2, 0, // Opcode: BIC_ZPmZ_B -/* 605 */ MCD_OPC_FilterValue, 1, 66, 81, 1, // Skip to: 86948 -/* 610 */ MCD_OPC_CheckPredicate, 0, 61, 81, 1, // Skip to: 86948 -/* 615 */ MCD_OPC_Decode, 184, 2, 0, // Opcode: BIC_ZPmZ_H -/* 619 */ MCD_OPC_FilterValue, 1, 143, 1, 0, // Skip to: 1023 -/* 624 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 627 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 663 -/* 632 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 635 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 649 -/* 640 */ MCD_OPC_CheckPredicate, 0, 31, 81, 1, // Skip to: 86948 -/* 645 */ MCD_OPC_Decode, 169, 22, 1, // Opcode: SADDV_VPZ_B -/* 649 */ MCD_OPC_FilterValue, 1, 22, 81, 1, // Skip to: 86948 -/* 654 */ MCD_OPC_CheckPredicate, 0, 17, 81, 1, // Skip to: 86948 -/* 659 */ MCD_OPC_Decode, 170, 22, 1, // Opcode: SADDV_VPZ_H -/* 663 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 699 -/* 668 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 671 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 685 -/* 676 */ MCD_OPC_CheckPredicate, 0, 251, 80, 1, // Skip to: 86948 -/* 681 */ MCD_OPC_Decode, 159, 31, 1, // Opcode: UADDV_VPZ_B -/* 685 */ MCD_OPC_FilterValue, 1, 242, 80, 1, // Skip to: 86948 -/* 690 */ MCD_OPC_CheckPredicate, 0, 237, 80, 1, // Skip to: 86948 -/* 695 */ MCD_OPC_Decode, 161, 31, 1, // Opcode: UADDV_VPZ_H -/* 699 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 735 -/* 704 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 707 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 721 -/* 712 */ MCD_OPC_CheckPredicate, 0, 215, 80, 1, // Skip to: 86948 -/* 717 */ MCD_OPC_Decode, 183, 23, 2, // Opcode: SMAXV_VPZ_B -/* 721 */ MCD_OPC_FilterValue, 1, 206, 80, 1, // Skip to: 86948 -/* 726 */ MCD_OPC_CheckPredicate, 0, 201, 80, 1, // Skip to: 86948 -/* 731 */ MCD_OPC_Decode, 185, 23, 3, // Opcode: SMAXV_VPZ_H -/* 735 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 771 -/* 740 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 743 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 757 -/* 748 */ MCD_OPC_CheckPredicate, 0, 179, 80, 1, // Skip to: 86948 -/* 753 */ MCD_OPC_Decode, 239, 31, 2, // Opcode: UMAXV_VPZ_B -/* 757 */ MCD_OPC_FilterValue, 1, 170, 80, 1, // Skip to: 86948 -/* 762 */ MCD_OPC_CheckPredicate, 0, 165, 80, 1, // Skip to: 86948 -/* 767 */ MCD_OPC_Decode, 241, 31, 3, // Opcode: UMAXV_VPZ_H -/* 771 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 807 -/* 776 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 779 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 793 -/* 784 */ MCD_OPC_CheckPredicate, 0, 143, 80, 1, // Skip to: 86948 -/* 789 */ MCD_OPC_Decode, 213, 23, 2, // Opcode: SMINV_VPZ_B -/* 793 */ MCD_OPC_FilterValue, 1, 134, 80, 1, // Skip to: 86948 -/* 798 */ MCD_OPC_CheckPredicate, 0, 129, 80, 1, // Skip to: 86948 -/* 803 */ MCD_OPC_Decode, 215, 23, 3, // Opcode: SMINV_VPZ_H -/* 807 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 843 -/* 812 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 815 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 829 -/* 820 */ MCD_OPC_CheckPredicate, 0, 107, 80, 1, // Skip to: 86948 -/* 825 */ MCD_OPC_Decode, 140, 32, 2, // Opcode: UMINV_VPZ_B -/* 829 */ MCD_OPC_FilterValue, 1, 98, 80, 1, // Skip to: 86948 -/* 834 */ MCD_OPC_CheckPredicate, 0, 93, 80, 1, // Skip to: 86948 -/* 839 */ MCD_OPC_Decode, 142, 32, 3, // Opcode: UMINV_VPZ_H -/* 843 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 879 -/* 848 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 851 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 865 -/* 856 */ MCD_OPC_CheckPredicate, 0, 71, 80, 1, // Skip to: 86948 -/* 861 */ MCD_OPC_Decode, 251, 19, 4, // Opcode: MOVPRFX_ZPzZ_B -/* 865 */ MCD_OPC_FilterValue, 1, 62, 80, 1, // Skip to: 86948 -/* 870 */ MCD_OPC_CheckPredicate, 0, 57, 80, 1, // Skip to: 86948 -/* 875 */ MCD_OPC_Decode, 253, 19, 4, // Opcode: MOVPRFX_ZPzZ_H -/* 879 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 915 -/* 884 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 887 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 901 -/* 892 */ MCD_OPC_CheckPredicate, 0, 35, 80, 1, // Skip to: 86948 -/* 897 */ MCD_OPC_Decode, 247, 19, 5, // Opcode: MOVPRFX_ZPmZ_B -/* 901 */ MCD_OPC_FilterValue, 1, 26, 80, 1, // Skip to: 86948 -/* 906 */ MCD_OPC_CheckPredicate, 0, 21, 80, 1, // Skip to: 86948 -/* 911 */ MCD_OPC_Decode, 249, 19, 5, // Opcode: MOVPRFX_ZPmZ_H -/* 915 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 951 -/* 920 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 923 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 937 -/* 928 */ MCD_OPC_CheckPredicate, 0, 255, 79, 1, // Skip to: 86948 -/* 933 */ MCD_OPC_Decode, 223, 20, 2, // Opcode: ORV_VPZ_B -/* 937 */ MCD_OPC_FilterValue, 1, 246, 79, 1, // Skip to: 86948 -/* 942 */ MCD_OPC_CheckPredicate, 0, 241, 79, 1, // Skip to: 86948 -/* 947 */ MCD_OPC_Decode, 225, 20, 3, // Opcode: ORV_VPZ_H -/* 951 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 987 -/* 956 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 959 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 973 -/* 964 */ MCD_OPC_CheckPredicate, 0, 219, 79, 1, // Skip to: 86948 -/* 969 */ MCD_OPC_Decode, 228, 5, 2, // Opcode: EORV_VPZ_B -/* 973 */ MCD_OPC_FilterValue, 1, 210, 79, 1, // Skip to: 86948 -/* 978 */ MCD_OPC_CheckPredicate, 0, 205, 79, 1, // Skip to: 86948 -/* 983 */ MCD_OPC_Decode, 230, 5, 3, // Opcode: EORV_VPZ_H -/* 987 */ MCD_OPC_FilterValue, 26, 196, 79, 1, // Skip to: 86948 -/* 992 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 995 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1009 -/* 1000 */ MCD_OPC_CheckPredicate, 0, 183, 79, 1, // Skip to: 86948 -/* 1005 */ MCD_OPC_Decode, 235, 1, 2, // Opcode: ANDV_VPZ_B -/* 1009 */ MCD_OPC_FilterValue, 1, 174, 79, 1, // Skip to: 86948 -/* 1014 */ MCD_OPC_CheckPredicate, 0, 169, 79, 1, // Skip to: 86948 -/* 1019 */ MCD_OPC_Decode, 237, 1, 3, // Opcode: ANDV_VPZ_H -/* 1023 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1059 -/* 1028 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1031 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1045 -/* 1036 */ MCD_OPC_CheckPredicate, 0, 147, 79, 1, // Skip to: 86948 -/* 1041 */ MCD_OPC_Decode, 205, 19, 6, // Opcode: MLA_ZPmZZ_B -/* 1045 */ MCD_OPC_FilterValue, 1, 138, 79, 1, // Skip to: 86948 -/* 1050 */ MCD_OPC_CheckPredicate, 0, 133, 79, 1, // Skip to: 86948 -/* 1055 */ MCD_OPC_Decode, 207, 19, 6, // Opcode: MLA_ZPmZZ_H -/* 1059 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 1095 -/* 1064 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1067 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1081 -/* 1072 */ MCD_OPC_CheckPredicate, 0, 111, 79, 1, // Skip to: 86948 -/* 1077 */ MCD_OPC_Decode, 219, 19, 6, // Opcode: MLS_ZPmZZ_B -/* 1081 */ MCD_OPC_FilterValue, 1, 102, 79, 1, // Skip to: 86948 -/* 1086 */ MCD_OPC_CheckPredicate, 0, 97, 79, 1, // Skip to: 86948 -/* 1091 */ MCD_OPC_Decode, 221, 19, 6, // Opcode: MLS_ZPmZZ_H -/* 1095 */ MCD_OPC_FilterValue, 4, 75, 2, 0, // Skip to: 1687 -/* 1100 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 1103 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 1168 -/* 1108 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1111 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1154 -/* 1116 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 1119 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1140 -/* 1124 */ MCD_OPC_CheckPredicate, 0, 59, 79, 1, // Skip to: 86948 -/* 1129 */ MCD_OPC_CheckField, 8, 1, 1, 52, 79, 1, // Skip to: 86948 -/* 1136 */ MCD_OPC_Decode, 142, 2, 7, // Opcode: ASR_ZPmI_B -/* 1140 */ MCD_OPC_FilterValue, 1, 43, 79, 1, // Skip to: 86948 -/* 1145 */ MCD_OPC_CheckPredicate, 0, 38, 79, 1, // Skip to: 86948 -/* 1150 */ MCD_OPC_Decode, 144, 2, 8, // Opcode: ASR_ZPmI_H -/* 1154 */ MCD_OPC_FilterValue, 1, 29, 79, 1, // Skip to: 86948 -/* 1159 */ MCD_OPC_CheckPredicate, 0, 24, 79, 1, // Skip to: 86948 -/* 1164 */ MCD_OPC_Decode, 145, 2, 9, // Opcode: ASR_ZPmI_S -/* 1168 */ MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 1233 -/* 1173 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1176 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1219 -/* 1181 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 1184 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1205 -/* 1189 */ MCD_OPC_CheckPredicate, 0, 250, 78, 1, // Skip to: 86948 -/* 1194 */ MCD_OPC_CheckField, 8, 1, 1, 243, 78, 1, // Skip to: 86948 -/* 1201 */ MCD_OPC_Decode, 187, 19, 7, // Opcode: LSR_ZPmI_B -/* 1205 */ MCD_OPC_FilterValue, 1, 234, 78, 1, // Skip to: 86948 -/* 1210 */ MCD_OPC_CheckPredicate, 0, 229, 78, 1, // Skip to: 86948 -/* 1215 */ MCD_OPC_Decode, 189, 19, 8, // Opcode: LSR_ZPmI_H -/* 1219 */ MCD_OPC_FilterValue, 1, 220, 78, 1, // Skip to: 86948 -/* 1224 */ MCD_OPC_CheckPredicate, 0, 215, 78, 1, // Skip to: 86948 -/* 1229 */ MCD_OPC_Decode, 190, 19, 9, // Opcode: LSR_ZPmI_S -/* 1233 */ MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 1298 -/* 1238 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1241 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1284 -/* 1246 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 1249 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1270 -/* 1254 */ MCD_OPC_CheckPredicate, 0, 185, 78, 1, // Skip to: 86948 -/* 1259 */ MCD_OPC_CheckField, 8, 1, 1, 178, 78, 1, // Skip to: 86948 -/* 1266 */ MCD_OPC_Decode, 163, 19, 10, // Opcode: LSL_ZPmI_B -/* 1270 */ MCD_OPC_FilterValue, 1, 169, 78, 1, // Skip to: 86948 -/* 1275 */ MCD_OPC_CheckPredicate, 0, 164, 78, 1, // Skip to: 86948 -/* 1280 */ MCD_OPC_Decode, 165, 19, 11, // Opcode: LSL_ZPmI_H -/* 1284 */ MCD_OPC_FilterValue, 1, 155, 78, 1, // Skip to: 86948 -/* 1289 */ MCD_OPC_CheckPredicate, 0, 150, 78, 1, // Skip to: 86948 -/* 1294 */ MCD_OPC_Decode, 166, 19, 12, // Opcode: LSL_ZPmI_S -/* 1298 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 1363 -/* 1303 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1306 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1349 -/* 1311 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 1314 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1335 -/* 1319 */ MCD_OPC_CheckPredicate, 0, 120, 78, 1, // Skip to: 86948 -/* 1324 */ MCD_OPC_CheckField, 8, 1, 1, 113, 78, 1, // Skip to: 86948 -/* 1331 */ MCD_OPC_Decode, 254, 1, 7, // Opcode: ASRD_ZPmI_B -/* 1335 */ MCD_OPC_FilterValue, 1, 104, 78, 1, // Skip to: 86948 -/* 1340 */ MCD_OPC_CheckPredicate, 0, 99, 78, 1, // Skip to: 86948 -/* 1345 */ MCD_OPC_Decode, 128, 2, 8, // Opcode: ASRD_ZPmI_H -/* 1349 */ MCD_OPC_FilterValue, 1, 90, 78, 1, // Skip to: 86948 -/* 1354 */ MCD_OPC_CheckPredicate, 0, 85, 78, 1, // Skip to: 86948 -/* 1359 */ MCD_OPC_Decode, 129, 2, 9, // Opcode: ASRD_ZPmI_S -/* 1363 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 1399 -/* 1368 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1371 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1385 -/* 1376 */ MCD_OPC_CheckPredicate, 0, 63, 78, 1, // Skip to: 86948 -/* 1381 */ MCD_OPC_Decode, 146, 2, 0, // Opcode: ASR_ZPmZ_B -/* 1385 */ MCD_OPC_FilterValue, 1, 54, 78, 1, // Skip to: 86948 -/* 1390 */ MCD_OPC_CheckPredicate, 0, 49, 78, 1, // Skip to: 86948 -/* 1395 */ MCD_OPC_Decode, 148, 2, 0, // Opcode: ASR_ZPmZ_H -/* 1399 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 1435 -/* 1404 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1407 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1421 -/* 1412 */ MCD_OPC_CheckPredicate, 0, 27, 78, 1, // Skip to: 86948 -/* 1417 */ MCD_OPC_Decode, 191, 19, 0, // Opcode: LSR_ZPmZ_B -/* 1421 */ MCD_OPC_FilterValue, 1, 18, 78, 1, // Skip to: 86948 -/* 1426 */ MCD_OPC_CheckPredicate, 0, 13, 78, 1, // Skip to: 86948 -/* 1431 */ MCD_OPC_Decode, 193, 19, 0, // Opcode: LSR_ZPmZ_H -/* 1435 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 1471 -/* 1440 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1443 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1457 -/* 1448 */ MCD_OPC_CheckPredicate, 0, 247, 77, 1, // Skip to: 86948 -/* 1453 */ MCD_OPC_Decode, 167, 19, 0, // Opcode: LSL_ZPmZ_B -/* 1457 */ MCD_OPC_FilterValue, 1, 238, 77, 1, // Skip to: 86948 -/* 1462 */ MCD_OPC_CheckPredicate, 0, 233, 77, 1, // Skip to: 86948 -/* 1467 */ MCD_OPC_Decode, 169, 19, 0, // Opcode: LSL_ZPmZ_H -/* 1471 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 1507 -/* 1476 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1479 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1493 -/* 1484 */ MCD_OPC_CheckPredicate, 0, 211, 77, 1, // Skip to: 86948 -/* 1489 */ MCD_OPC_Decode, 130, 2, 0, // Opcode: ASRR_ZPmZ_B -/* 1493 */ MCD_OPC_FilterValue, 1, 202, 77, 1, // Skip to: 86948 -/* 1498 */ MCD_OPC_CheckPredicate, 0, 197, 77, 1, // Skip to: 86948 -/* 1503 */ MCD_OPC_Decode, 132, 2, 0, // Opcode: ASRR_ZPmZ_H -/* 1507 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 1543 -/* 1512 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1515 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1529 -/* 1520 */ MCD_OPC_CheckPredicate, 0, 175, 77, 1, // Skip to: 86948 -/* 1525 */ MCD_OPC_Decode, 175, 19, 0, // Opcode: LSRR_ZPmZ_B -/* 1529 */ MCD_OPC_FilterValue, 1, 166, 77, 1, // Skip to: 86948 -/* 1534 */ MCD_OPC_CheckPredicate, 0, 161, 77, 1, // Skip to: 86948 -/* 1539 */ MCD_OPC_Decode, 177, 19, 0, // Opcode: LSRR_ZPmZ_H -/* 1543 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 1579 -/* 1548 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1551 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1565 -/* 1556 */ MCD_OPC_CheckPredicate, 0, 139, 77, 1, // Skip to: 86948 -/* 1561 */ MCD_OPC_Decode, 151, 19, 0, // Opcode: LSLR_ZPmZ_B -/* 1565 */ MCD_OPC_FilterValue, 1, 130, 77, 1, // Skip to: 86948 -/* 1570 */ MCD_OPC_CheckPredicate, 0, 125, 77, 1, // Skip to: 86948 -/* 1575 */ MCD_OPC_Decode, 153, 19, 0, // Opcode: LSLR_ZPmZ_H -/* 1579 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 1615 -/* 1584 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1587 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1601 -/* 1592 */ MCD_OPC_CheckPredicate, 0, 103, 77, 1, // Skip to: 86948 -/* 1597 */ MCD_OPC_Decode, 136, 2, 0, // Opcode: ASR_WIDE_ZPmZ_B -/* 1601 */ MCD_OPC_FilterValue, 1, 94, 77, 1, // Skip to: 86948 -/* 1606 */ MCD_OPC_CheckPredicate, 0, 89, 77, 1, // Skip to: 86948 -/* 1611 */ MCD_OPC_Decode, 137, 2, 0, // Opcode: ASR_WIDE_ZPmZ_H -/* 1615 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 1651 -/* 1620 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1623 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1637 -/* 1628 */ MCD_OPC_CheckPredicate, 0, 67, 77, 1, // Skip to: 86948 -/* 1633 */ MCD_OPC_Decode, 181, 19, 0, // Opcode: LSR_WIDE_ZPmZ_B -/* 1637 */ MCD_OPC_FilterValue, 1, 58, 77, 1, // Skip to: 86948 -/* 1642 */ MCD_OPC_CheckPredicate, 0, 53, 77, 1, // Skip to: 86948 -/* 1647 */ MCD_OPC_Decode, 182, 19, 0, // Opcode: LSR_WIDE_ZPmZ_H -/* 1651 */ MCD_OPC_FilterValue, 27, 44, 77, 1, // Skip to: 86948 -/* 1656 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1659 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1673 -/* 1664 */ MCD_OPC_CheckPredicate, 0, 31, 77, 1, // Skip to: 86948 -/* 1669 */ MCD_OPC_Decode, 157, 19, 0, // Opcode: LSL_WIDE_ZPmZ_B -/* 1673 */ MCD_OPC_FilterValue, 1, 22, 77, 1, // Skip to: 86948 -/* 1678 */ MCD_OPC_CheckPredicate, 0, 17, 77, 1, // Skip to: 86948 -/* 1683 */ MCD_OPC_Decode, 158, 19, 0, // Opcode: LSL_WIDE_ZPmZ_H -/* 1687 */ MCD_OPC_FilterValue, 5, 82, 1, 0, // Skip to: 2030 -/* 1692 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 1695 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 1716 -/* 1700 */ MCD_OPC_CheckPredicate, 0, 251, 76, 1, // Skip to: 86948 -/* 1705 */ MCD_OPC_CheckField, 22, 1, 1, 244, 76, 1, // Skip to: 86948 -/* 1712 */ MCD_OPC_Decode, 170, 30, 5, // Opcode: SXTB_ZPmZ_H -/* 1716 */ MCD_OPC_FilterValue, 17, 16, 0, 0, // Skip to: 1737 -/* 1721 */ MCD_OPC_CheckPredicate, 0, 230, 76, 1, // Skip to: 86948 -/* 1726 */ MCD_OPC_CheckField, 22, 1, 1, 223, 76, 1, // Skip to: 86948 -/* 1733 */ MCD_OPC_Decode, 183, 34, 5, // Opcode: UXTB_ZPmZ_H -/* 1737 */ MCD_OPC_FilterValue, 22, 30, 0, 0, // Skip to: 1772 -/* 1742 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1745 */ MCD_OPC_FilterValue, 0, 8, 0, 0, // Skip to: 1758 -/* 1750 */ MCD_OPC_CheckPredicate, 0, 201, 76, 1, // Skip to: 86948 -/* 1755 */ MCD_OPC_Decode, 126, 5, // Opcode: ABS_ZPmZ_B -/* 1758 */ MCD_OPC_FilterValue, 1, 193, 76, 1, // Skip to: 86948 -/* 1763 */ MCD_OPC_CheckPredicate, 0, 188, 76, 1, // Skip to: 86948 -/* 1768 */ MCD_OPC_Decode, 128, 1, 5, // Opcode: ABS_ZPmZ_H -/* 1772 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 1808 -/* 1777 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1780 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1794 -/* 1785 */ MCD_OPC_CheckPredicate, 0, 166, 76, 1, // Skip to: 86948 -/* 1790 */ MCD_OPC_Decode, 175, 20, 5, // Opcode: NEG_ZPmZ_B -/* 1794 */ MCD_OPC_FilterValue, 1, 157, 76, 1, // Skip to: 86948 -/* 1799 */ MCD_OPC_CheckPredicate, 0, 152, 76, 1, // Skip to: 86948 -/* 1804 */ MCD_OPC_Decode, 177, 20, 5, // Opcode: NEG_ZPmZ_H -/* 1808 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 1844 -/* 1813 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1816 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1830 -/* 1821 */ MCD_OPC_CheckPredicate, 0, 130, 76, 1, // Skip to: 86948 -/* 1826 */ MCD_OPC_Decode, 160, 3, 5, // Opcode: CLS_ZPmZ_B -/* 1830 */ MCD_OPC_FilterValue, 1, 121, 76, 1, // Skip to: 86948 -/* 1835 */ MCD_OPC_CheckPredicate, 0, 116, 76, 1, // Skip to: 86948 -/* 1840 */ MCD_OPC_Decode, 162, 3, 5, // Opcode: CLS_ZPmZ_H -/* 1844 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 1880 -/* 1849 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1852 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1866 -/* 1857 */ MCD_OPC_CheckPredicate, 0, 94, 76, 1, // Skip to: 86948 -/* 1862 */ MCD_OPC_Decode, 172, 3, 5, // Opcode: CLZ_ZPmZ_B -/* 1866 */ MCD_OPC_FilterValue, 1, 85, 76, 1, // Skip to: 86948 -/* 1871 */ MCD_OPC_CheckPredicate, 0, 80, 76, 1, // Skip to: 86948 -/* 1876 */ MCD_OPC_Decode, 174, 3, 5, // Opcode: CLZ_ZPmZ_H -/* 1880 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 1916 -/* 1885 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1888 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1902 -/* 1893 */ MCD_OPC_CheckPredicate, 0, 58, 76, 1, // Skip to: 86948 -/* 1898 */ MCD_OPC_Decode, 253, 4, 5, // Opcode: CNT_ZPmZ_B -/* 1902 */ MCD_OPC_FilterValue, 1, 49, 76, 1, // Skip to: 86948 -/* 1907 */ MCD_OPC_CheckPredicate, 0, 44, 76, 1, // Skip to: 86948 -/* 1912 */ MCD_OPC_Decode, 255, 4, 5, // Opcode: CNT_ZPmZ_H -/* 1916 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 1952 -/* 1921 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1924 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1938 -/* 1929 */ MCD_OPC_CheckPredicate, 0, 22, 76, 1, // Skip to: 86948 -/* 1934 */ MCD_OPC_Decode, 241, 4, 5, // Opcode: CNOT_ZPmZ_B -/* 1938 */ MCD_OPC_FilterValue, 1, 13, 76, 1, // Skip to: 86948 -/* 1943 */ MCD_OPC_CheckPredicate, 0, 8, 76, 1, // Skip to: 86948 -/* 1948 */ MCD_OPC_Decode, 243, 4, 5, // Opcode: CNOT_ZPmZ_H -/* 1952 */ MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 1973 -/* 1957 */ MCD_OPC_CheckPredicate, 0, 250, 75, 1, // Skip to: 86948 -/* 1962 */ MCD_OPC_CheckField, 22, 1, 1, 243, 75, 1, // Skip to: 86948 -/* 1969 */ MCD_OPC_Decode, 143, 6, 5, // Opcode: FABS_ZPmZ_H -/* 1973 */ MCD_OPC_FilterValue, 29, 16, 0, 0, // Skip to: 1994 -/* 1978 */ MCD_OPC_CheckPredicate, 0, 229, 75, 1, // Skip to: 86948 -/* 1983 */ MCD_OPC_CheckField, 22, 1, 1, 222, 75, 1, // Skip to: 86948 -/* 1990 */ MCD_OPC_Decode, 168, 11, 5, // Opcode: FNEG_ZPmZ_H -/* 1994 */ MCD_OPC_FilterValue, 30, 213, 75, 1, // Skip to: 86948 -/* 1999 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2002 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2016 -/* 2007 */ MCD_OPC_CheckPredicate, 0, 200, 75, 1, // Skip to: 86948 -/* 2012 */ MCD_OPC_Decode, 189, 20, 5, // Opcode: NOT_ZPmZ_B -/* 2016 */ MCD_OPC_FilterValue, 1, 191, 75, 1, // Skip to: 86948 -/* 2021 */ MCD_OPC_CheckPredicate, 0, 186, 75, 1, // Skip to: 86948 -/* 2026 */ MCD_OPC_Decode, 191, 20, 5, // Opcode: NOT_ZPmZ_H -/* 2030 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 2066 -/* 2035 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2038 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2052 -/* 2043 */ MCD_OPC_CheckPredicate, 0, 164, 75, 1, // Skip to: 86948 -/* 2048 */ MCD_OPC_Decode, 201, 19, 13, // Opcode: MAD_ZPmZZ_B -/* 2052 */ MCD_OPC_FilterValue, 1, 155, 75, 1, // Skip to: 86948 -/* 2057 */ MCD_OPC_CheckPredicate, 0, 150, 75, 1, // Skip to: 86948 -/* 2062 */ MCD_OPC_Decode, 203, 19, 13, // Opcode: MAD_ZPmZZ_H -/* 2066 */ MCD_OPC_FilterValue, 7, 141, 75, 1, // Skip to: 86948 -/* 2071 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2074 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2088 -/* 2079 */ MCD_OPC_CheckPredicate, 0, 128, 75, 1, // Skip to: 86948 -/* 2084 */ MCD_OPC_Decode, 140, 20, 13, // Opcode: MSB_ZPmZZ_B -/* 2088 */ MCD_OPC_FilterValue, 1, 119, 75, 1, // Skip to: 86948 -/* 2093 */ MCD_OPC_CheckPredicate, 0, 114, 75, 1, // Skip to: 86948 -/* 2098 */ MCD_OPC_Decode, 142, 20, 13, // Opcode: MSB_ZPmZZ_H -/* 2102 */ MCD_OPC_FilterValue, 1, 76, 8, 0, // Skip to: 4231 -/* 2107 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 2110 */ MCD_OPC_FilterValue, 0, 211, 2, 0, // Skip to: 2838 -/* 2115 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 2118 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 2154 -/* 2123 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2126 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2140 -/* 2131 */ MCD_OPC_CheckPredicate, 0, 76, 75, 1, // Skip to: 86948 -/* 2136 */ MCD_OPC_Decode, 188, 1, 0, // Opcode: ADD_ZPmZ_S -/* 2140 */ MCD_OPC_FilterValue, 1, 67, 75, 1, // Skip to: 86948 -/* 2145 */ MCD_OPC_CheckPredicate, 0, 62, 75, 1, // Skip to: 86948 -/* 2150 */ MCD_OPC_Decode, 186, 1, 0, // Opcode: ADD_ZPmZ_D -/* 2154 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 2190 -/* 2159 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2162 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2176 -/* 2167 */ MCD_OPC_CheckPredicate, 0, 40, 75, 1, // Skip to: 86948 -/* 2172 */ MCD_OPC_Decode, 250, 29, 0, // Opcode: SUB_ZPmZ_S -/* 2176 */ MCD_OPC_FilterValue, 1, 31, 75, 1, // Skip to: 86948 -/* 2181 */ MCD_OPC_CheckPredicate, 0, 26, 75, 1, // Skip to: 86948 -/* 2186 */ MCD_OPC_Decode, 248, 29, 0, // Opcode: SUB_ZPmZ_D -/* 2190 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 2226 -/* 2195 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2198 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2212 -/* 2203 */ MCD_OPC_CheckPredicate, 0, 4, 75, 1, // Skip to: 86948 -/* 2208 */ MCD_OPC_Decode, 224, 29, 0, // Opcode: SUBR_ZPmZ_S -/* 2212 */ MCD_OPC_FilterValue, 1, 251, 74, 1, // Skip to: 86948 -/* 2217 */ MCD_OPC_CheckPredicate, 0, 246, 74, 1, // Skip to: 86948 -/* 2222 */ MCD_OPC_Decode, 222, 29, 0, // Opcode: SUBR_ZPmZ_D -/* 2226 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2262 -/* 2231 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2234 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2248 -/* 2239 */ MCD_OPC_CheckPredicate, 0, 224, 74, 1, // Skip to: 86948 -/* 2244 */ MCD_OPC_Decode, 199, 23, 0, // Opcode: SMAX_ZPmZ_S -/* 2248 */ MCD_OPC_FilterValue, 1, 215, 74, 1, // Skip to: 86948 -/* 2253 */ MCD_OPC_CheckPredicate, 0, 210, 74, 1, // Skip to: 86948 -/* 2258 */ MCD_OPC_Decode, 197, 23, 0, // Opcode: SMAX_ZPmZ_D -/* 2262 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 2298 -/* 2267 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2270 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2284 -/* 2275 */ MCD_OPC_CheckPredicate, 0, 188, 74, 1, // Skip to: 86948 -/* 2280 */ MCD_OPC_Decode, 255, 31, 0, // Opcode: UMAX_ZPmZ_S -/* 2284 */ MCD_OPC_FilterValue, 1, 179, 74, 1, // Skip to: 86948 -/* 2289 */ MCD_OPC_CheckPredicate, 0, 174, 74, 1, // Skip to: 86948 -/* 2294 */ MCD_OPC_Decode, 253, 31, 0, // Opcode: UMAX_ZPmZ_D -/* 2298 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 2334 -/* 2303 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2306 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2320 -/* 2311 */ MCD_OPC_CheckPredicate, 0, 152, 74, 1, // Skip to: 86948 -/* 2316 */ MCD_OPC_Decode, 229, 23, 0, // Opcode: SMIN_ZPmZ_S -/* 2320 */ MCD_OPC_FilterValue, 1, 143, 74, 1, // Skip to: 86948 -/* 2325 */ MCD_OPC_CheckPredicate, 0, 138, 74, 1, // Skip to: 86948 -/* 2330 */ MCD_OPC_Decode, 227, 23, 0, // Opcode: SMIN_ZPmZ_D -/* 2334 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 2370 -/* 2339 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2342 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2356 -/* 2347 */ MCD_OPC_CheckPredicate, 0, 116, 74, 1, // Skip to: 86948 -/* 2352 */ MCD_OPC_Decode, 156, 32, 0, // Opcode: UMIN_ZPmZ_S -/* 2356 */ MCD_OPC_FilterValue, 1, 107, 74, 1, // Skip to: 86948 -/* 2361 */ MCD_OPC_CheckPredicate, 0, 102, 74, 1, // Skip to: 86948 -/* 2366 */ MCD_OPC_Decode, 154, 32, 0, // Opcode: UMIN_ZPmZ_D -/* 2370 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 2406 -/* 2375 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2378 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2392 -/* 2383 */ MCD_OPC_CheckPredicate, 0, 80, 74, 1, // Skip to: 86948 -/* 2388 */ MCD_OPC_Decode, 139, 22, 0, // Opcode: SABD_ZPmZ_S -/* 2392 */ MCD_OPC_FilterValue, 1, 71, 74, 1, // Skip to: 86948 -/* 2397 */ MCD_OPC_CheckPredicate, 0, 66, 74, 1, // Skip to: 86948 -/* 2402 */ MCD_OPC_Decode, 137, 22, 0, // Opcode: SABD_ZPmZ_D -/* 2406 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 2442 -/* 2411 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2414 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2428 -/* 2419 */ MCD_OPC_CheckPredicate, 0, 44, 74, 1, // Skip to: 86948 -/* 2424 */ MCD_OPC_Decode, 129, 31, 0, // Opcode: UABD_ZPmZ_S -/* 2428 */ MCD_OPC_FilterValue, 1, 35, 74, 1, // Skip to: 86948 -/* 2433 */ MCD_OPC_CheckPredicate, 0, 30, 74, 1, // Skip to: 86948 -/* 2438 */ MCD_OPC_Decode, 255, 30, 0, // Opcode: UABD_ZPmZ_D -/* 2442 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 2478 -/* 2447 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2450 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2464 -/* 2455 */ MCD_OPC_CheckPredicate, 0, 8, 74, 1, // Skip to: 86948 -/* 2460 */ MCD_OPC_Decode, 156, 20, 0, // Opcode: MUL_ZPmZ_S -/* 2464 */ MCD_OPC_FilterValue, 1, 255, 73, 1, // Skip to: 86948 -/* 2469 */ MCD_OPC_CheckPredicate, 0, 250, 73, 1, // Skip to: 86948 -/* 2474 */ MCD_OPC_Decode, 154, 20, 0, // Opcode: MUL_ZPmZ_D -/* 2478 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 2514 -/* 2483 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2486 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2500 -/* 2491 */ MCD_OPC_CheckPredicate, 0, 228, 73, 1, // Skip to: 86948 -/* 2496 */ MCD_OPC_Decode, 137, 24, 0, // Opcode: SMULH_ZPmZ_S -/* 2500 */ MCD_OPC_FilterValue, 1, 219, 73, 1, // Skip to: 86948 -/* 2505 */ MCD_OPC_CheckPredicate, 0, 214, 73, 1, // Skip to: 86948 -/* 2510 */ MCD_OPC_Decode, 135, 24, 0, // Opcode: SMULH_ZPmZ_D -/* 2514 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 2550 -/* 2519 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2522 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2536 -/* 2527 */ MCD_OPC_CheckPredicate, 0, 192, 73, 1, // Skip to: 86948 -/* 2532 */ MCD_OPC_Decode, 191, 32, 0, // Opcode: UMULH_ZPmZ_S -/* 2536 */ MCD_OPC_FilterValue, 1, 183, 73, 1, // Skip to: 86948 -/* 2541 */ MCD_OPC_CheckPredicate, 0, 178, 73, 1, // Skip to: 86948 -/* 2546 */ MCD_OPC_Decode, 189, 32, 0, // Opcode: UMULH_ZPmZ_D -/* 2550 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 2586 -/* 2555 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2558 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2572 -/* 2563 */ MCD_OPC_CheckPredicate, 0, 156, 73, 1, // Skip to: 86948 -/* 2568 */ MCD_OPC_Decode, 224, 22, 0, // Opcode: SDIV_ZPmZ_S -/* 2572 */ MCD_OPC_FilterValue, 1, 147, 73, 1, // Skip to: 86948 -/* 2577 */ MCD_OPC_CheckPredicate, 0, 142, 73, 1, // Skip to: 86948 -/* 2582 */ MCD_OPC_Decode, 223, 22, 0, // Opcode: SDIV_ZPmZ_D -/* 2586 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 2622 -/* 2591 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2594 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2608 -/* 2599 */ MCD_OPC_CheckPredicate, 0, 120, 73, 1, // Skip to: 86948 -/* 2604 */ MCD_OPC_Decode, 211, 31, 0, // Opcode: UDIV_ZPmZ_S -/* 2608 */ MCD_OPC_FilterValue, 1, 111, 73, 1, // Skip to: 86948 -/* 2613 */ MCD_OPC_CheckPredicate, 0, 106, 73, 1, // Skip to: 86948 -/* 2618 */ MCD_OPC_Decode, 210, 31, 0, // Opcode: UDIV_ZPmZ_D -/* 2622 */ MCD_OPC_FilterValue, 22, 31, 0, 0, // Skip to: 2658 -/* 2627 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2630 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2644 -/* 2635 */ MCD_OPC_CheckPredicate, 0, 84, 73, 1, // Skip to: 86948 -/* 2640 */ MCD_OPC_Decode, 220, 22, 0, // Opcode: SDIVR_ZPmZ_S -/* 2644 */ MCD_OPC_FilterValue, 1, 75, 73, 1, // Skip to: 86948 -/* 2649 */ MCD_OPC_CheckPredicate, 0, 70, 73, 1, // Skip to: 86948 -/* 2654 */ MCD_OPC_Decode, 219, 22, 0, // Opcode: SDIVR_ZPmZ_D -/* 2658 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 2694 -/* 2663 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2666 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2680 -/* 2671 */ MCD_OPC_CheckPredicate, 0, 48, 73, 1, // Skip to: 86948 -/* 2676 */ MCD_OPC_Decode, 207, 31, 0, // Opcode: UDIVR_ZPmZ_S -/* 2680 */ MCD_OPC_FilterValue, 1, 39, 73, 1, // Skip to: 86948 -/* 2685 */ MCD_OPC_CheckPredicate, 0, 34, 73, 1, // Skip to: 86948 -/* 2690 */ MCD_OPC_Decode, 206, 31, 0, // Opcode: UDIVR_ZPmZ_D -/* 2694 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 2730 -/* 2699 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2702 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2716 -/* 2707 */ MCD_OPC_CheckPredicate, 0, 12, 73, 1, // Skip to: 86948 -/* 2712 */ MCD_OPC_Decode, 215, 20, 0, // Opcode: ORR_ZPmZ_S -/* 2716 */ MCD_OPC_FilterValue, 1, 3, 73, 1, // Skip to: 86948 -/* 2721 */ MCD_OPC_CheckPredicate, 0, 254, 72, 1, // Skip to: 86948 -/* 2726 */ MCD_OPC_Decode, 213, 20, 0, // Opcode: ORR_ZPmZ_D -/* 2730 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 2766 -/* 2735 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2738 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2752 -/* 2743 */ MCD_OPC_CheckPredicate, 0, 232, 72, 1, // Skip to: 86948 -/* 2748 */ MCD_OPC_Decode, 243, 5, 0, // Opcode: EOR_ZPmZ_S -/* 2752 */ MCD_OPC_FilterValue, 1, 223, 72, 1, // Skip to: 86948 -/* 2757 */ MCD_OPC_CheckPredicate, 0, 218, 72, 1, // Skip to: 86948 -/* 2762 */ MCD_OPC_Decode, 241, 5, 0, // Opcode: EOR_ZPmZ_D -/* 2766 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 2802 -/* 2771 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2774 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2788 -/* 2779 */ MCD_OPC_CheckPredicate, 0, 196, 72, 1, // Skip to: 86948 -/* 2784 */ MCD_OPC_Decode, 250, 1, 0, // Opcode: AND_ZPmZ_S -/* 2788 */ MCD_OPC_FilterValue, 1, 187, 72, 1, // Skip to: 86948 -/* 2793 */ MCD_OPC_CheckPredicate, 0, 182, 72, 1, // Skip to: 86948 -/* 2798 */ MCD_OPC_Decode, 248, 1, 0, // Opcode: AND_ZPmZ_D -/* 2802 */ MCD_OPC_FilterValue, 27, 173, 72, 1, // Skip to: 86948 -/* 2807 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2810 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2824 -/* 2815 */ MCD_OPC_CheckPredicate, 0, 160, 72, 1, // Skip to: 86948 -/* 2820 */ MCD_OPC_Decode, 185, 2, 0, // Opcode: BIC_ZPmZ_S -/* 2824 */ MCD_OPC_FilterValue, 1, 151, 72, 1, // Skip to: 86948 -/* 2829 */ MCD_OPC_CheckPredicate, 0, 146, 72, 1, // Skip to: 86948 -/* 2834 */ MCD_OPC_Decode, 183, 2, 0, // Opcode: BIC_ZPmZ_D -/* 2838 */ MCD_OPC_FilterValue, 1, 128, 1, 0, // Skip to: 3227 -/* 2843 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 2846 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2867 -/* 2851 */ MCD_OPC_CheckPredicate, 0, 124, 72, 1, // Skip to: 86948 -/* 2856 */ MCD_OPC_CheckField, 22, 1, 0, 117, 72, 1, // Skip to: 86948 -/* 2863 */ MCD_OPC_Decode, 171, 22, 1, // Opcode: SADDV_VPZ_S -/* 2867 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 2903 -/* 2872 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2875 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2889 -/* 2880 */ MCD_OPC_CheckPredicate, 0, 95, 72, 1, // Skip to: 86948 -/* 2885 */ MCD_OPC_Decode, 162, 31, 1, // Opcode: UADDV_VPZ_S -/* 2889 */ MCD_OPC_FilterValue, 1, 86, 72, 1, // Skip to: 86948 -/* 2894 */ MCD_OPC_CheckPredicate, 0, 81, 72, 1, // Skip to: 86948 -/* 2899 */ MCD_OPC_Decode, 160, 31, 1, // Opcode: UADDV_VPZ_D -/* 2903 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2939 -/* 2908 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2911 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2925 -/* 2916 */ MCD_OPC_CheckPredicate, 0, 59, 72, 1, // Skip to: 86948 -/* 2921 */ MCD_OPC_Decode, 186, 23, 14, // Opcode: SMAXV_VPZ_S -/* 2925 */ MCD_OPC_FilterValue, 1, 50, 72, 1, // Skip to: 86948 -/* 2930 */ MCD_OPC_CheckPredicate, 0, 45, 72, 1, // Skip to: 86948 -/* 2935 */ MCD_OPC_Decode, 184, 23, 1, // Opcode: SMAXV_VPZ_D -/* 2939 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 2975 -/* 2944 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2947 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2961 -/* 2952 */ MCD_OPC_CheckPredicate, 0, 23, 72, 1, // Skip to: 86948 -/* 2957 */ MCD_OPC_Decode, 242, 31, 14, // Opcode: UMAXV_VPZ_S -/* 2961 */ MCD_OPC_FilterValue, 1, 14, 72, 1, // Skip to: 86948 -/* 2966 */ MCD_OPC_CheckPredicate, 0, 9, 72, 1, // Skip to: 86948 -/* 2971 */ MCD_OPC_Decode, 240, 31, 1, // Opcode: UMAXV_VPZ_D -/* 2975 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 3011 -/* 2980 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2983 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2997 -/* 2988 */ MCD_OPC_CheckPredicate, 0, 243, 71, 1, // Skip to: 86948 -/* 2993 */ MCD_OPC_Decode, 216, 23, 14, // Opcode: SMINV_VPZ_S -/* 2997 */ MCD_OPC_FilterValue, 1, 234, 71, 1, // Skip to: 86948 -/* 3002 */ MCD_OPC_CheckPredicate, 0, 229, 71, 1, // Skip to: 86948 -/* 3007 */ MCD_OPC_Decode, 214, 23, 1, // Opcode: SMINV_VPZ_D -/* 3011 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 3047 -/* 3016 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3019 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3033 -/* 3024 */ MCD_OPC_CheckPredicate, 0, 207, 71, 1, // Skip to: 86948 -/* 3029 */ MCD_OPC_Decode, 143, 32, 14, // Opcode: UMINV_VPZ_S -/* 3033 */ MCD_OPC_FilterValue, 1, 198, 71, 1, // Skip to: 86948 -/* 3038 */ MCD_OPC_CheckPredicate, 0, 193, 71, 1, // Skip to: 86948 -/* 3043 */ MCD_OPC_Decode, 141, 32, 1, // Opcode: UMINV_VPZ_D -/* 3047 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3083 -/* 3052 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3055 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3069 -/* 3060 */ MCD_OPC_CheckPredicate, 0, 171, 71, 1, // Skip to: 86948 -/* 3065 */ MCD_OPC_Decode, 254, 19, 4, // Opcode: MOVPRFX_ZPzZ_S -/* 3069 */ MCD_OPC_FilterValue, 1, 162, 71, 1, // Skip to: 86948 -/* 3074 */ MCD_OPC_CheckPredicate, 0, 157, 71, 1, // Skip to: 86948 -/* 3079 */ MCD_OPC_Decode, 252, 19, 4, // Opcode: MOVPRFX_ZPzZ_D -/* 3083 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 3119 -/* 3088 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3091 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3105 -/* 3096 */ MCD_OPC_CheckPredicate, 0, 135, 71, 1, // Skip to: 86948 -/* 3101 */ MCD_OPC_Decode, 250, 19, 5, // Opcode: MOVPRFX_ZPmZ_S -/* 3105 */ MCD_OPC_FilterValue, 1, 126, 71, 1, // Skip to: 86948 -/* 3110 */ MCD_OPC_CheckPredicate, 0, 121, 71, 1, // Skip to: 86948 -/* 3115 */ MCD_OPC_Decode, 248, 19, 5, // Opcode: MOVPRFX_ZPmZ_D -/* 3119 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 3155 -/* 3124 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3127 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3141 -/* 3132 */ MCD_OPC_CheckPredicate, 0, 99, 71, 1, // Skip to: 86948 -/* 3137 */ MCD_OPC_Decode, 226, 20, 14, // Opcode: ORV_VPZ_S -/* 3141 */ MCD_OPC_FilterValue, 1, 90, 71, 1, // Skip to: 86948 -/* 3146 */ MCD_OPC_CheckPredicate, 0, 85, 71, 1, // Skip to: 86948 -/* 3151 */ MCD_OPC_Decode, 224, 20, 1, // Opcode: ORV_VPZ_D -/* 3155 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 3191 -/* 3160 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3163 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3177 -/* 3168 */ MCD_OPC_CheckPredicate, 0, 63, 71, 1, // Skip to: 86948 -/* 3173 */ MCD_OPC_Decode, 231, 5, 14, // Opcode: EORV_VPZ_S -/* 3177 */ MCD_OPC_FilterValue, 1, 54, 71, 1, // Skip to: 86948 -/* 3182 */ MCD_OPC_CheckPredicate, 0, 49, 71, 1, // Skip to: 86948 -/* 3187 */ MCD_OPC_Decode, 229, 5, 1, // Opcode: EORV_VPZ_D -/* 3191 */ MCD_OPC_FilterValue, 26, 40, 71, 1, // Skip to: 86948 -/* 3196 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3199 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3213 -/* 3204 */ MCD_OPC_CheckPredicate, 0, 27, 71, 1, // Skip to: 86948 -/* 3209 */ MCD_OPC_Decode, 238, 1, 14, // Opcode: ANDV_VPZ_S -/* 3213 */ MCD_OPC_FilterValue, 1, 18, 71, 1, // Skip to: 86948 -/* 3218 */ MCD_OPC_CheckPredicate, 0, 13, 71, 1, // Skip to: 86948 -/* 3223 */ MCD_OPC_Decode, 236, 1, 1, // Opcode: ANDV_VPZ_D -/* 3227 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 3263 -/* 3232 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3235 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3249 -/* 3240 */ MCD_OPC_CheckPredicate, 0, 247, 70, 1, // Skip to: 86948 -/* 3245 */ MCD_OPC_Decode, 208, 19, 6, // Opcode: MLA_ZPmZZ_S -/* 3249 */ MCD_OPC_FilterValue, 1, 238, 70, 1, // Skip to: 86948 -/* 3254 */ MCD_OPC_CheckPredicate, 0, 233, 70, 1, // Skip to: 86948 -/* 3259 */ MCD_OPC_Decode, 206, 19, 6, // Opcode: MLA_ZPmZZ_D -/* 3263 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 3299 -/* 3268 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3271 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3285 -/* 3276 */ MCD_OPC_CheckPredicate, 0, 211, 70, 1, // Skip to: 86948 -/* 3281 */ MCD_OPC_Decode, 222, 19, 6, // Opcode: MLS_ZPmZZ_S -/* 3285 */ MCD_OPC_FilterValue, 1, 202, 70, 1, // Skip to: 86948 -/* 3290 */ MCD_OPC_CheckPredicate, 0, 197, 70, 1, // Skip to: 86948 -/* 3295 */ MCD_OPC_Decode, 220, 19, 6, // Opcode: MLS_ZPmZZ_D -/* 3299 */ MCD_OPC_FilterValue, 4, 82, 1, 0, // Skip to: 3642 -/* 3304 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 3307 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3321 -/* 3312 */ MCD_OPC_CheckPredicate, 0, 175, 70, 1, // Skip to: 86948 -/* 3317 */ MCD_OPC_Decode, 143, 2, 15, // Opcode: ASR_ZPmI_D -/* 3321 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3335 -/* 3326 */ MCD_OPC_CheckPredicate, 0, 161, 70, 1, // Skip to: 86948 -/* 3331 */ MCD_OPC_Decode, 188, 19, 15, // Opcode: LSR_ZPmI_D -/* 3335 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3349 -/* 3340 */ MCD_OPC_CheckPredicate, 0, 147, 70, 1, // Skip to: 86948 -/* 3345 */ MCD_OPC_Decode, 164, 19, 16, // Opcode: LSL_ZPmI_D -/* 3349 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3363 -/* 3354 */ MCD_OPC_CheckPredicate, 0, 133, 70, 1, // Skip to: 86948 -/* 3359 */ MCD_OPC_Decode, 255, 1, 15, // Opcode: ASRD_ZPmI_D -/* 3363 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3399 -/* 3368 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3371 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3385 -/* 3376 */ MCD_OPC_CheckPredicate, 0, 111, 70, 1, // Skip to: 86948 -/* 3381 */ MCD_OPC_Decode, 149, 2, 0, // Opcode: ASR_ZPmZ_S -/* 3385 */ MCD_OPC_FilterValue, 1, 102, 70, 1, // Skip to: 86948 -/* 3390 */ MCD_OPC_CheckPredicate, 0, 97, 70, 1, // Skip to: 86948 -/* 3395 */ MCD_OPC_Decode, 147, 2, 0, // Opcode: ASR_ZPmZ_D -/* 3399 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 3435 -/* 3404 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3407 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3421 -/* 3412 */ MCD_OPC_CheckPredicate, 0, 75, 70, 1, // Skip to: 86948 -/* 3417 */ MCD_OPC_Decode, 194, 19, 0, // Opcode: LSR_ZPmZ_S -/* 3421 */ MCD_OPC_FilterValue, 1, 66, 70, 1, // Skip to: 86948 -/* 3426 */ MCD_OPC_CheckPredicate, 0, 61, 70, 1, // Skip to: 86948 -/* 3431 */ MCD_OPC_Decode, 192, 19, 0, // Opcode: LSR_ZPmZ_D -/* 3435 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 3471 -/* 3440 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3443 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3457 -/* 3448 */ MCD_OPC_CheckPredicate, 0, 39, 70, 1, // Skip to: 86948 -/* 3453 */ MCD_OPC_Decode, 170, 19, 0, // Opcode: LSL_ZPmZ_S -/* 3457 */ MCD_OPC_FilterValue, 1, 30, 70, 1, // Skip to: 86948 -/* 3462 */ MCD_OPC_CheckPredicate, 0, 25, 70, 1, // Skip to: 86948 -/* 3467 */ MCD_OPC_Decode, 168, 19, 0, // Opcode: LSL_ZPmZ_D -/* 3471 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 3507 -/* 3476 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3479 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3493 -/* 3484 */ MCD_OPC_CheckPredicate, 0, 3, 70, 1, // Skip to: 86948 -/* 3489 */ MCD_OPC_Decode, 133, 2, 0, // Opcode: ASRR_ZPmZ_S -/* 3493 */ MCD_OPC_FilterValue, 1, 250, 69, 1, // Skip to: 86948 -/* 3498 */ MCD_OPC_CheckPredicate, 0, 245, 69, 1, // Skip to: 86948 -/* 3503 */ MCD_OPC_Decode, 131, 2, 0, // Opcode: ASRR_ZPmZ_D -/* 3507 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 3543 -/* 3512 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3515 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3529 -/* 3520 */ MCD_OPC_CheckPredicate, 0, 223, 69, 1, // Skip to: 86948 -/* 3525 */ MCD_OPC_Decode, 178, 19, 0, // Opcode: LSRR_ZPmZ_S -/* 3529 */ MCD_OPC_FilterValue, 1, 214, 69, 1, // Skip to: 86948 -/* 3534 */ MCD_OPC_CheckPredicate, 0, 209, 69, 1, // Skip to: 86948 -/* 3539 */ MCD_OPC_Decode, 176, 19, 0, // Opcode: LSRR_ZPmZ_D -/* 3543 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 3579 -/* 3548 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3551 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3565 -/* 3556 */ MCD_OPC_CheckPredicate, 0, 187, 69, 1, // Skip to: 86948 -/* 3561 */ MCD_OPC_Decode, 154, 19, 0, // Opcode: LSLR_ZPmZ_S -/* 3565 */ MCD_OPC_FilterValue, 1, 178, 69, 1, // Skip to: 86948 -/* 3570 */ MCD_OPC_CheckPredicate, 0, 173, 69, 1, // Skip to: 86948 -/* 3575 */ MCD_OPC_Decode, 152, 19, 0, // Opcode: LSLR_ZPmZ_D -/* 3579 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 3600 -/* 3584 */ MCD_OPC_CheckPredicate, 0, 159, 69, 1, // Skip to: 86948 -/* 3589 */ MCD_OPC_CheckField, 22, 1, 0, 152, 69, 1, // Skip to: 86948 -/* 3596 */ MCD_OPC_Decode, 138, 2, 0, // Opcode: ASR_WIDE_ZPmZ_S -/* 3600 */ MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 3621 -/* 3605 */ MCD_OPC_CheckPredicate, 0, 138, 69, 1, // Skip to: 86948 -/* 3610 */ MCD_OPC_CheckField, 22, 1, 0, 131, 69, 1, // Skip to: 86948 -/* 3617 */ MCD_OPC_Decode, 183, 19, 0, // Opcode: LSR_WIDE_ZPmZ_S -/* 3621 */ MCD_OPC_FilterValue, 27, 122, 69, 1, // Skip to: 86948 -/* 3626 */ MCD_OPC_CheckPredicate, 0, 117, 69, 1, // Skip to: 86948 -/* 3631 */ MCD_OPC_CheckField, 22, 1, 0, 110, 69, 1, // Skip to: 86948 -/* 3638 */ MCD_OPC_Decode, 159, 19, 0, // Opcode: LSL_WIDE_ZPmZ_S -/* 3642 */ MCD_OPC_FilterValue, 5, 0, 2, 0, // Skip to: 4159 -/* 3647 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 3650 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3686 -/* 3655 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3658 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3672 -/* 3663 */ MCD_OPC_CheckPredicate, 0, 80, 69, 1, // Skip to: 86948 -/* 3668 */ MCD_OPC_Decode, 171, 30, 5, // Opcode: SXTB_ZPmZ_S -/* 3672 */ MCD_OPC_FilterValue, 1, 71, 69, 1, // Skip to: 86948 -/* 3677 */ MCD_OPC_CheckPredicate, 0, 66, 69, 1, // Skip to: 86948 -/* 3682 */ MCD_OPC_Decode, 169, 30, 5, // Opcode: SXTB_ZPmZ_D -/* 3686 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 3722 -/* 3691 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3694 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3708 -/* 3699 */ MCD_OPC_CheckPredicate, 0, 44, 69, 1, // Skip to: 86948 -/* 3704 */ MCD_OPC_Decode, 184, 34, 5, // Opcode: UXTB_ZPmZ_S -/* 3708 */ MCD_OPC_FilterValue, 1, 35, 69, 1, // Skip to: 86948 -/* 3713 */ MCD_OPC_CheckPredicate, 0, 30, 69, 1, // Skip to: 86948 -/* 3718 */ MCD_OPC_Decode, 182, 34, 5, // Opcode: UXTB_ZPmZ_D -/* 3722 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 3758 -/* 3727 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3730 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3744 -/* 3735 */ MCD_OPC_CheckPredicate, 0, 8, 69, 1, // Skip to: 86948 -/* 3740 */ MCD_OPC_Decode, 173, 30, 5, // Opcode: SXTH_ZPmZ_S -/* 3744 */ MCD_OPC_FilterValue, 1, 255, 68, 1, // Skip to: 86948 -/* 3749 */ MCD_OPC_CheckPredicate, 0, 250, 68, 1, // Skip to: 86948 -/* 3754 */ MCD_OPC_Decode, 172, 30, 5, // Opcode: SXTH_ZPmZ_D -/* 3758 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 3794 -/* 3763 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3766 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3780 -/* 3771 */ MCD_OPC_CheckPredicate, 0, 228, 68, 1, // Skip to: 86948 -/* 3776 */ MCD_OPC_Decode, 186, 34, 5, // Opcode: UXTH_ZPmZ_S -/* 3780 */ MCD_OPC_FilterValue, 1, 219, 68, 1, // Skip to: 86948 -/* 3785 */ MCD_OPC_CheckPredicate, 0, 214, 68, 1, // Skip to: 86948 -/* 3790 */ MCD_OPC_Decode, 185, 34, 5, // Opcode: UXTH_ZPmZ_D -/* 3794 */ MCD_OPC_FilterValue, 20, 16, 0, 0, // Skip to: 3815 -/* 3799 */ MCD_OPC_CheckPredicate, 0, 200, 68, 1, // Skip to: 86948 -/* 3804 */ MCD_OPC_CheckField, 22, 1, 1, 193, 68, 1, // Skip to: 86948 -/* 3811 */ MCD_OPC_Decode, 174, 30, 5, // Opcode: SXTW_ZPmZ_D -/* 3815 */ MCD_OPC_FilterValue, 21, 16, 0, 0, // Skip to: 3836 -/* 3820 */ MCD_OPC_CheckPredicate, 0, 179, 68, 1, // Skip to: 86948 -/* 3825 */ MCD_OPC_CheckField, 22, 1, 1, 172, 68, 1, // Skip to: 86948 -/* 3832 */ MCD_OPC_Decode, 187, 34, 5, // Opcode: UXTW_ZPmZ_D -/* 3836 */ MCD_OPC_FilterValue, 22, 30, 0, 0, // Skip to: 3871 -/* 3841 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3844 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3858 -/* 3849 */ MCD_OPC_CheckPredicate, 0, 150, 68, 1, // Skip to: 86948 -/* 3854 */ MCD_OPC_Decode, 129, 1, 5, // Opcode: ABS_ZPmZ_S -/* 3858 */ MCD_OPC_FilterValue, 1, 141, 68, 1, // Skip to: 86948 -/* 3863 */ MCD_OPC_CheckPredicate, 0, 136, 68, 1, // Skip to: 86948 -/* 3868 */ MCD_OPC_Decode, 127, 5, // Opcode: ABS_ZPmZ_D -/* 3871 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 3907 -/* 3876 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3879 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3893 -/* 3884 */ MCD_OPC_CheckPredicate, 0, 115, 68, 1, // Skip to: 86948 -/* 3889 */ MCD_OPC_Decode, 178, 20, 5, // Opcode: NEG_ZPmZ_S -/* 3893 */ MCD_OPC_FilterValue, 1, 106, 68, 1, // Skip to: 86948 -/* 3898 */ MCD_OPC_CheckPredicate, 0, 101, 68, 1, // Skip to: 86948 -/* 3903 */ MCD_OPC_Decode, 176, 20, 5, // Opcode: NEG_ZPmZ_D -/* 3907 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 3943 -/* 3912 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3915 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3929 -/* 3920 */ MCD_OPC_CheckPredicate, 0, 79, 68, 1, // Skip to: 86948 -/* 3925 */ MCD_OPC_Decode, 163, 3, 5, // Opcode: CLS_ZPmZ_S -/* 3929 */ MCD_OPC_FilterValue, 1, 70, 68, 1, // Skip to: 86948 -/* 3934 */ MCD_OPC_CheckPredicate, 0, 65, 68, 1, // Skip to: 86948 -/* 3939 */ MCD_OPC_Decode, 161, 3, 5, // Opcode: CLS_ZPmZ_D -/* 3943 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 3979 -/* 3948 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3951 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3965 -/* 3956 */ MCD_OPC_CheckPredicate, 0, 43, 68, 1, // Skip to: 86948 -/* 3961 */ MCD_OPC_Decode, 175, 3, 5, // Opcode: CLZ_ZPmZ_S -/* 3965 */ MCD_OPC_FilterValue, 1, 34, 68, 1, // Skip to: 86948 -/* 3970 */ MCD_OPC_CheckPredicate, 0, 29, 68, 1, // Skip to: 86948 -/* 3975 */ MCD_OPC_Decode, 173, 3, 5, // Opcode: CLZ_ZPmZ_D -/* 3979 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 4015 -/* 3984 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3987 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4001 -/* 3992 */ MCD_OPC_CheckPredicate, 0, 7, 68, 1, // Skip to: 86948 -/* 3997 */ MCD_OPC_Decode, 128, 5, 5, // Opcode: CNT_ZPmZ_S -/* 4001 */ MCD_OPC_FilterValue, 1, 254, 67, 1, // Skip to: 86948 -/* 4006 */ MCD_OPC_CheckPredicate, 0, 249, 67, 1, // Skip to: 86948 -/* 4011 */ MCD_OPC_Decode, 254, 4, 5, // Opcode: CNT_ZPmZ_D -/* 4015 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 4051 -/* 4020 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4023 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4037 -/* 4028 */ MCD_OPC_CheckPredicate, 0, 227, 67, 1, // Skip to: 86948 -/* 4033 */ MCD_OPC_Decode, 244, 4, 5, // Opcode: CNOT_ZPmZ_S -/* 4037 */ MCD_OPC_FilterValue, 1, 218, 67, 1, // Skip to: 86948 -/* 4042 */ MCD_OPC_CheckPredicate, 0, 213, 67, 1, // Skip to: 86948 -/* 4047 */ MCD_OPC_Decode, 242, 4, 5, // Opcode: CNOT_ZPmZ_D -/* 4051 */ MCD_OPC_FilterValue, 28, 31, 0, 0, // Skip to: 4087 -/* 4056 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4059 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4073 -/* 4064 */ MCD_OPC_CheckPredicate, 0, 191, 67, 1, // Skip to: 86948 -/* 4069 */ MCD_OPC_Decode, 144, 6, 5, // Opcode: FABS_ZPmZ_S -/* 4073 */ MCD_OPC_FilterValue, 1, 182, 67, 1, // Skip to: 86948 -/* 4078 */ MCD_OPC_CheckPredicate, 0, 177, 67, 1, // Skip to: 86948 -/* 4083 */ MCD_OPC_Decode, 142, 6, 5, // Opcode: FABS_ZPmZ_D -/* 4087 */ MCD_OPC_FilterValue, 29, 31, 0, 0, // Skip to: 4123 -/* 4092 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4095 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4109 -/* 4100 */ MCD_OPC_CheckPredicate, 0, 155, 67, 1, // Skip to: 86948 -/* 4105 */ MCD_OPC_Decode, 169, 11, 5, // Opcode: FNEG_ZPmZ_S -/* 4109 */ MCD_OPC_FilterValue, 1, 146, 67, 1, // Skip to: 86948 -/* 4114 */ MCD_OPC_CheckPredicate, 0, 141, 67, 1, // Skip to: 86948 -/* 4119 */ MCD_OPC_Decode, 167, 11, 5, // Opcode: FNEG_ZPmZ_D -/* 4123 */ MCD_OPC_FilterValue, 30, 132, 67, 1, // Skip to: 86948 -/* 4128 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4131 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4145 -/* 4136 */ MCD_OPC_CheckPredicate, 0, 119, 67, 1, // Skip to: 86948 -/* 4141 */ MCD_OPC_Decode, 192, 20, 5, // Opcode: NOT_ZPmZ_S -/* 4145 */ MCD_OPC_FilterValue, 1, 110, 67, 1, // Skip to: 86948 -/* 4150 */ MCD_OPC_CheckPredicate, 0, 105, 67, 1, // Skip to: 86948 -/* 4155 */ MCD_OPC_Decode, 190, 20, 5, // Opcode: NOT_ZPmZ_D -/* 4159 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 4195 -/* 4164 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4167 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4181 -/* 4172 */ MCD_OPC_CheckPredicate, 0, 83, 67, 1, // Skip to: 86948 -/* 4177 */ MCD_OPC_Decode, 204, 19, 13, // Opcode: MAD_ZPmZZ_S -/* 4181 */ MCD_OPC_FilterValue, 1, 74, 67, 1, // Skip to: 86948 -/* 4186 */ MCD_OPC_CheckPredicate, 0, 69, 67, 1, // Skip to: 86948 -/* 4191 */ MCD_OPC_Decode, 202, 19, 13, // Opcode: MAD_ZPmZZ_D -/* 4195 */ MCD_OPC_FilterValue, 7, 60, 67, 1, // Skip to: 86948 -/* 4200 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4203 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4217 -/* 4208 */ MCD_OPC_CheckPredicate, 0, 47, 67, 1, // Skip to: 86948 -/* 4213 */ MCD_OPC_Decode, 143, 20, 13, // Opcode: MSB_ZPmZZ_S -/* 4217 */ MCD_OPC_FilterValue, 1, 38, 67, 1, // Skip to: 86948 -/* 4222 */ MCD_OPC_CheckPredicate, 0, 33, 67, 1, // Skip to: 86948 -/* 4227 */ MCD_OPC_Decode, 141, 20, 13, // Opcode: MSB_ZPmZZ_D -/* 4231 */ MCD_OPC_FilterValue, 2, 161, 0, 0, // Skip to: 4397 -/* 4236 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4239 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 4289 -/* 4244 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4247 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4268 -/* 4252 */ MCD_OPC_CheckPredicate, 0, 3, 67, 1, // Skip to: 86948 -/* 4257 */ MCD_OPC_CheckField, 18, 2, 0, 252, 66, 1, // Skip to: 86948 -/* 4264 */ MCD_OPC_Decode, 211, 20, 17, // Opcode: ORR_ZI -/* 4268 */ MCD_OPC_FilterValue, 1, 243, 66, 1, // Skip to: 86948 -/* 4273 */ MCD_OPC_CheckPredicate, 0, 238, 66, 1, // Skip to: 86948 -/* 4278 */ MCD_OPC_CheckField, 18, 2, 0, 231, 66, 1, // Skip to: 86948 -/* 4285 */ MCD_OPC_Decode, 239, 5, 17, // Opcode: EOR_ZI -/* 4289 */ MCD_OPC_FilterValue, 1, 222, 66, 1, // Skip to: 86948 -/* 4294 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 4297 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4333 -/* 4302 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4305 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4319 -/* 4310 */ MCD_OPC_CheckPredicate, 0, 201, 66, 1, // Skip to: 86948 -/* 4315 */ MCD_OPC_Decode, 145, 5, 18, // Opcode: CPY_ZPzI_B -/* 4319 */ MCD_OPC_FilterValue, 1, 192, 66, 1, // Skip to: 86948 -/* 4324 */ MCD_OPC_CheckPredicate, 0, 187, 66, 1, // Skip to: 86948 -/* 4329 */ MCD_OPC_Decode, 147, 5, 19, // Opcode: CPY_ZPzI_H -/* 4333 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 4369 -/* 4338 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4341 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4355 -/* 4346 */ MCD_OPC_CheckPredicate, 0, 165, 66, 1, // Skip to: 86948 -/* 4351 */ MCD_OPC_Decode, 133, 5, 20, // Opcode: CPY_ZPmI_B -/* 4355 */ MCD_OPC_FilterValue, 1, 156, 66, 1, // Skip to: 86948 -/* 4360 */ MCD_OPC_CheckPredicate, 0, 151, 66, 1, // Skip to: 86948 -/* 4365 */ MCD_OPC_Decode, 135, 5, 21, // Opcode: CPY_ZPmI_H -/* 4369 */ MCD_OPC_FilterValue, 3, 142, 66, 1, // Skip to: 86948 -/* 4374 */ MCD_OPC_CheckPredicate, 0, 137, 66, 1, // Skip to: 86948 -/* 4379 */ MCD_OPC_CheckField, 22, 1, 1, 130, 66, 1, // Skip to: 86948 -/* 4386 */ MCD_OPC_CheckField, 13, 1, 0, 123, 66, 1, // Skip to: 86948 -/* 4393 */ MCD_OPC_Decode, 212, 7, 22, // Opcode: FCPY_ZPmI_H -/* 4397 */ MCD_OPC_FilterValue, 3, 114, 66, 1, // Skip to: 86948 -/* 4402 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4405 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 4455 -/* 4410 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4413 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4434 -/* 4418 */ MCD_OPC_CheckPredicate, 0, 93, 66, 1, // Skip to: 86948 -/* 4423 */ MCD_OPC_CheckField, 18, 2, 0, 86, 66, 1, // Skip to: 86948 -/* 4430 */ MCD_OPC_Decode, 246, 1, 17, // Opcode: AND_ZI -/* 4434 */ MCD_OPC_FilterValue, 1, 77, 66, 1, // Skip to: 86948 -/* 4439 */ MCD_OPC_CheckPredicate, 0, 72, 66, 1, // Skip to: 86948 -/* 4444 */ MCD_OPC_CheckField, 18, 2, 0, 65, 66, 1, // Skip to: 86948 -/* 4451 */ MCD_OPC_Decode, 194, 5, 17, // Opcode: DUPM_ZI -/* 4455 */ MCD_OPC_FilterValue, 1, 56, 66, 1, // Skip to: 86948 -/* 4460 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 4463 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4499 -/* 4468 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4471 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4485 -/* 4476 */ MCD_OPC_CheckPredicate, 0, 35, 66, 1, // Skip to: 86948 -/* 4481 */ MCD_OPC_Decode, 148, 5, 23, // Opcode: CPY_ZPzI_S -/* 4485 */ MCD_OPC_FilterValue, 1, 26, 66, 1, // Skip to: 86948 -/* 4490 */ MCD_OPC_CheckPredicate, 0, 21, 66, 1, // Skip to: 86948 -/* 4495 */ MCD_OPC_Decode, 146, 5, 24, // Opcode: CPY_ZPzI_D -/* 4499 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 4535 -/* 4504 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4507 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4521 -/* 4512 */ MCD_OPC_CheckPredicate, 0, 255, 65, 1, // Skip to: 86948 -/* 4517 */ MCD_OPC_Decode, 136, 5, 25, // Opcode: CPY_ZPmI_S -/* 4521 */ MCD_OPC_FilterValue, 1, 246, 65, 1, // Skip to: 86948 -/* 4526 */ MCD_OPC_CheckPredicate, 0, 241, 65, 1, // Skip to: 86948 -/* 4531 */ MCD_OPC_Decode, 134, 5, 26, // Opcode: CPY_ZPmI_D -/* 4535 */ MCD_OPC_FilterValue, 3, 232, 65, 1, // Skip to: 86948 -/* 4540 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4543 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4564 -/* 4548 */ MCD_OPC_CheckPredicate, 0, 219, 65, 1, // Skip to: 86948 -/* 4553 */ MCD_OPC_CheckField, 13, 1, 0, 212, 65, 1, // Skip to: 86948 -/* 4560 */ MCD_OPC_Decode, 213, 7, 22, // Opcode: FCPY_ZPmI_S -/* 4564 */ MCD_OPC_FilterValue, 1, 203, 65, 1, // Skip to: 86948 -/* 4569 */ MCD_OPC_CheckPredicate, 0, 198, 65, 1, // Skip to: 86948 -/* 4574 */ MCD_OPC_CheckField, 13, 1, 0, 191, 65, 1, // Skip to: 86948 -/* 4581 */ MCD_OPC_Decode, 211, 7, 22, // Opcode: FCPY_ZPmI_D -/* 4585 */ MCD_OPC_FilterValue, 1, 182, 65, 1, // Skip to: 86948 -/* 4590 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 4593 */ MCD_OPC_FilterValue, 0, 105, 4, 0, // Skip to: 5727 -/* 4598 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 4601 */ MCD_OPC_FilterValue, 0, 129, 1, 0, // Skip to: 4991 -/* 4606 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 4609 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 4701 -/* 4614 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 4617 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4631 -/* 4622 */ MCD_OPC_CheckPredicate, 0, 145, 65, 1, // Skip to: 86948 -/* 4627 */ MCD_OPC_Decode, 189, 1, 27, // Opcode: ADD_ZZZ_B -/* 4631 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4645 -/* 4636 */ MCD_OPC_CheckPredicate, 0, 131, 65, 1, // Skip to: 86948 -/* 4641 */ MCD_OPC_Decode, 251, 29, 27, // Opcode: SUB_ZZZ_B -/* 4645 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4659 -/* 4650 */ MCD_OPC_CheckPredicate, 0, 117, 65, 1, // Skip to: 86948 -/* 4655 */ MCD_OPC_Decode, 168, 24, 27, // Opcode: SQADD_ZZZ_B -/* 4659 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4673 -/* 4664 */ MCD_OPC_CheckPredicate, 0, 103, 65, 1, // Skip to: 86948 -/* 4669 */ MCD_OPC_Decode, 207, 32, 27, // Opcode: UQADD_ZZZ_B -/* 4673 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4687 -/* 4678 */ MCD_OPC_CheckPredicate, 0, 89, 65, 1, // Skip to: 86948 -/* 4683 */ MCD_OPC_Decode, 150, 26, 27, // Opcode: SQSUB_ZZZ_B -/* 4687 */ MCD_OPC_FilterValue, 7, 80, 65, 1, // Skip to: 86948 -/* 4692 */ MCD_OPC_CheckPredicate, 0, 75, 65, 1, // Skip to: 86948 -/* 4697 */ MCD_OPC_Decode, 193, 33, 27, // Opcode: UQSUB_ZZZ_B -/* 4701 */ MCD_OPC_FilterValue, 1, 87, 0, 0, // Skip to: 4793 -/* 4706 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 4709 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4723 -/* 4714 */ MCD_OPC_CheckPredicate, 0, 53, 65, 1, // Skip to: 86948 -/* 4719 */ MCD_OPC_Decode, 191, 1, 27, // Opcode: ADD_ZZZ_H -/* 4723 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4737 -/* 4728 */ MCD_OPC_CheckPredicate, 0, 39, 65, 1, // Skip to: 86948 -/* 4733 */ MCD_OPC_Decode, 253, 29, 27, // Opcode: SUB_ZZZ_H -/* 4737 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4751 -/* 4742 */ MCD_OPC_CheckPredicate, 0, 25, 65, 1, // Skip to: 86948 -/* 4747 */ MCD_OPC_Decode, 170, 24, 27, // Opcode: SQADD_ZZZ_H -/* 4751 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4765 -/* 4756 */ MCD_OPC_CheckPredicate, 0, 11, 65, 1, // Skip to: 86948 -/* 4761 */ MCD_OPC_Decode, 209, 32, 27, // Opcode: UQADD_ZZZ_H -/* 4765 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4779 -/* 4770 */ MCD_OPC_CheckPredicate, 0, 253, 64, 1, // Skip to: 86948 -/* 4775 */ MCD_OPC_Decode, 152, 26, 27, // Opcode: SQSUB_ZZZ_H -/* 4779 */ MCD_OPC_FilterValue, 7, 244, 64, 1, // Skip to: 86948 -/* 4784 */ MCD_OPC_CheckPredicate, 0, 239, 64, 1, // Skip to: 86948 -/* 4789 */ MCD_OPC_Decode, 195, 33, 27, // Opcode: UQSUB_ZZZ_H -/* 4793 */ MCD_OPC_FilterValue, 2, 87, 0, 0, // Skip to: 4885 -/* 4798 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 4801 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4815 -/* 4806 */ MCD_OPC_CheckPredicate, 0, 217, 64, 1, // Skip to: 86948 -/* 4811 */ MCD_OPC_Decode, 192, 1, 27, // Opcode: ADD_ZZZ_S -/* 4815 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4829 -/* 4820 */ MCD_OPC_CheckPredicate, 0, 203, 64, 1, // Skip to: 86948 -/* 4825 */ MCD_OPC_Decode, 254, 29, 27, // Opcode: SUB_ZZZ_S -/* 4829 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4843 -/* 4834 */ MCD_OPC_CheckPredicate, 0, 189, 64, 1, // Skip to: 86948 -/* 4839 */ MCD_OPC_Decode, 171, 24, 27, // Opcode: SQADD_ZZZ_S -/* 4843 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4857 -/* 4848 */ MCD_OPC_CheckPredicate, 0, 175, 64, 1, // Skip to: 86948 -/* 4853 */ MCD_OPC_Decode, 210, 32, 27, // Opcode: UQADD_ZZZ_S -/* 4857 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4871 -/* 4862 */ MCD_OPC_CheckPredicate, 0, 161, 64, 1, // Skip to: 86948 -/* 4867 */ MCD_OPC_Decode, 153, 26, 27, // Opcode: SQSUB_ZZZ_S -/* 4871 */ MCD_OPC_FilterValue, 7, 152, 64, 1, // Skip to: 86948 -/* 4876 */ MCD_OPC_CheckPredicate, 0, 147, 64, 1, // Skip to: 86948 -/* 4881 */ MCD_OPC_Decode, 196, 33, 27, // Opcode: UQSUB_ZZZ_S -/* 4885 */ MCD_OPC_FilterValue, 3, 87, 0, 0, // Skip to: 4977 -/* 4890 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 4893 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4907 -/* 4898 */ MCD_OPC_CheckPredicate, 0, 125, 64, 1, // Skip to: 86948 -/* 4903 */ MCD_OPC_Decode, 190, 1, 27, // Opcode: ADD_ZZZ_D -/* 4907 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4921 -/* 4912 */ MCD_OPC_CheckPredicate, 0, 111, 64, 1, // Skip to: 86948 -/* 4917 */ MCD_OPC_Decode, 252, 29, 27, // Opcode: SUB_ZZZ_D -/* 4921 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4935 -/* 4926 */ MCD_OPC_CheckPredicate, 0, 97, 64, 1, // Skip to: 86948 -/* 4931 */ MCD_OPC_Decode, 169, 24, 27, // Opcode: SQADD_ZZZ_D -/* 4935 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4949 -/* 4940 */ MCD_OPC_CheckPredicate, 0, 83, 64, 1, // Skip to: 86948 -/* 4945 */ MCD_OPC_Decode, 208, 32, 27, // Opcode: UQADD_ZZZ_D -/* 4949 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4963 -/* 4954 */ MCD_OPC_CheckPredicate, 0, 69, 64, 1, // Skip to: 86948 -/* 4959 */ MCD_OPC_Decode, 151, 26, 27, // Opcode: SQSUB_ZZZ_D -/* 4963 */ MCD_OPC_FilterValue, 7, 60, 64, 1, // Skip to: 86948 -/* 4968 */ MCD_OPC_CheckPredicate, 0, 55, 64, 1, // Skip to: 86948 -/* 4973 */ MCD_OPC_Decode, 194, 33, 27, // Opcode: UQSUB_ZZZ_D -/* 4977 */ MCD_OPC_FilterValue, 4, 46, 64, 1, // Skip to: 86948 -/* 4982 */ MCD_OPC_CheckPredicate, 0, 41, 64, 1, // Skip to: 86948 -/* 4987 */ MCD_OPC_Decode, 252, 5, 28, // Opcode: EXT_ZZI -/* 4991 */ MCD_OPC_FilterValue, 1, 32, 64, 1, // Skip to: 86948 -/* 4996 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 4999 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 5143 -/* 5004 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 5007 */ MCD_OPC_FilterValue, 0, 110, 0, 0, // Skip to: 5122 -/* 5012 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 5015 */ MCD_OPC_FilterValue, 0, 81, 0, 0, // Skip to: 5101 -/* 5020 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 5023 */ MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 5080 -/* 5028 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 5031 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 5059 -/* 5036 */ MCD_OPC_CheckPredicate, 0, 243, 63, 1, // Skip to: 86948 -/* 5041 */ MCD_OPC_CheckField, 24, 2, 1, 236, 63, 1, // Skip to: 86948 -/* 5048 */ MCD_OPC_CheckField, 20, 1, 1, 229, 63, 1, // Skip to: 86948 -/* 5055 */ MCD_OPC_Decode, 206, 5, 29, // Opcode: DUP_ZZI_Q -/* 5059 */ MCD_OPC_FilterValue, 1, 220, 63, 1, // Skip to: 86948 -/* 5064 */ MCD_OPC_CheckPredicate, 0, 215, 63, 1, // Skip to: 86948 -/* 5069 */ MCD_OPC_CheckField, 24, 2, 1, 208, 63, 1, // Skip to: 86948 -/* 5076 */ MCD_OPC_Decode, 204, 5, 30, // Opcode: DUP_ZZI_D -/* 5080 */ MCD_OPC_FilterValue, 1, 199, 63, 1, // Skip to: 86948 -/* 5085 */ MCD_OPC_CheckPredicate, 0, 194, 63, 1, // Skip to: 86948 -/* 5090 */ MCD_OPC_CheckField, 24, 2, 1, 187, 63, 1, // Skip to: 86948 -/* 5097 */ MCD_OPC_Decode, 207, 5, 31, // Opcode: DUP_ZZI_S -/* 5101 */ MCD_OPC_FilterValue, 1, 178, 63, 1, // Skip to: 86948 -/* 5106 */ MCD_OPC_CheckPredicate, 0, 173, 63, 1, // Skip to: 86948 -/* 5111 */ MCD_OPC_CheckField, 24, 2, 1, 166, 63, 1, // Skip to: 86948 -/* 5118 */ MCD_OPC_Decode, 205, 5, 32, // Opcode: DUP_ZZI_H -/* 5122 */ MCD_OPC_FilterValue, 1, 157, 63, 1, // Skip to: 86948 -/* 5127 */ MCD_OPC_CheckPredicate, 0, 152, 63, 1, // Skip to: 86948 -/* 5132 */ MCD_OPC_CheckField, 24, 2, 1, 145, 63, 1, // Skip to: 86948 -/* 5139 */ MCD_OPC_Decode, 203, 5, 33, // Opcode: DUP_ZZI_B -/* 5143 */ MCD_OPC_FilterValue, 4, 115, 0, 0, // Skip to: 5263 -/* 5148 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5165 -/* 5156 */ MCD_OPC_CheckPredicate, 0, 123, 63, 1, // Skip to: 86948 -/* 5161 */ MCD_OPC_Decode, 251, 1, 27, // Opcode: AND_ZZZ -/* 5165 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5179 -/* 5170 */ MCD_OPC_CheckPredicate, 0, 109, 63, 1, // Skip to: 86948 -/* 5175 */ MCD_OPC_Decode, 216, 20, 27, // Opcode: ORR_ZZZ -/* 5179 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5193 -/* 5184 */ MCD_OPC_CheckPredicate, 0, 95, 63, 1, // Skip to: 86948 -/* 5189 */ MCD_OPC_Decode, 244, 5, 27, // Opcode: EOR_ZZZ -/* 5193 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 5207 -/* 5198 */ MCD_OPC_CheckPredicate, 0, 81, 63, 1, // Skip to: 86948 -/* 5203 */ MCD_OPC_Decode, 186, 2, 27, // Opcode: BIC_ZZZ -/* 5207 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5221 -/* 5212 */ MCD_OPC_CheckPredicate, 0, 67, 63, 1, // Skip to: 86948 -/* 5217 */ MCD_OPC_Decode, 177, 30, 27, // Opcode: TBL_ZZZ_B -/* 5221 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5235 -/* 5226 */ MCD_OPC_CheckPredicate, 0, 53, 63, 1, // Skip to: 86948 -/* 5231 */ MCD_OPC_Decode, 179, 30, 27, // Opcode: TBL_ZZZ_H -/* 5235 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5249 -/* 5240 */ MCD_OPC_CheckPredicate, 0, 39, 63, 1, // Skip to: 86948 -/* 5245 */ MCD_OPC_Decode, 180, 30, 27, // Opcode: TBL_ZZZ_S -/* 5249 */ MCD_OPC_FilterValue, 7, 30, 63, 1, // Skip to: 86948 -/* 5254 */ MCD_OPC_CheckPredicate, 0, 25, 63, 1, // Skip to: 86948 -/* 5259 */ MCD_OPC_Decode, 178, 30, 27, // Opcode: TBL_ZZZ_D -/* 5263 */ MCD_OPC_FilterValue, 6, 16, 63, 1, // Skip to: 86948 -/* 5268 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 5271 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 5335 -/* 5276 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5279 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5293 -/* 5284 */ MCD_OPC_CheckPredicate, 0, 251, 62, 1, // Skip to: 86948 -/* 5289 */ MCD_OPC_Decode, 199, 5, 34, // Opcode: DUP_ZR_B -/* 5293 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5307 -/* 5298 */ MCD_OPC_CheckPredicate, 0, 237, 62, 1, // Skip to: 86948 -/* 5303 */ MCD_OPC_Decode, 201, 5, 34, // Opcode: DUP_ZR_H -/* 5307 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5321 -/* 5312 */ MCD_OPC_CheckPredicate, 0, 223, 62, 1, // Skip to: 86948 -/* 5317 */ MCD_OPC_Decode, 202, 5, 34, // Opcode: DUP_ZR_S -/* 5321 */ MCD_OPC_FilterValue, 7, 214, 62, 1, // Skip to: 86948 -/* 5326 */ MCD_OPC_CheckPredicate, 0, 209, 62, 1, // Skip to: 86948 -/* 5331 */ MCD_OPC_Decode, 200, 5, 35, // Opcode: DUP_ZR_D -/* 5335 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 5399 -/* 5340 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5343 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5357 -/* 5348 */ MCD_OPC_CheckPredicate, 0, 187, 62, 1, // Skip to: 86948 -/* 5353 */ MCD_OPC_Decode, 146, 14, 36, // Opcode: INSR_ZR_B -/* 5357 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5371 -/* 5362 */ MCD_OPC_CheckPredicate, 0, 173, 62, 1, // Skip to: 86948 -/* 5367 */ MCD_OPC_Decode, 148, 14, 36, // Opcode: INSR_ZR_H -/* 5371 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5385 -/* 5376 */ MCD_OPC_CheckPredicate, 0, 159, 62, 1, // Skip to: 86948 -/* 5381 */ MCD_OPC_Decode, 149, 14, 36, // Opcode: INSR_ZR_S -/* 5385 */ MCD_OPC_FilterValue, 7, 150, 62, 1, // Skip to: 86948 -/* 5390 */ MCD_OPC_CheckPredicate, 0, 145, 62, 1, // Skip to: 86948 -/* 5395 */ MCD_OPC_Decode, 147, 14, 37, // Opcode: INSR_ZR_D -/* 5399 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 5449 -/* 5404 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5407 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5421 -/* 5412 */ MCD_OPC_CheckPredicate, 0, 123, 62, 1, // Skip to: 86948 -/* 5417 */ MCD_OPC_Decode, 139, 30, 38, // Opcode: SUNPKLO_ZZ_H -/* 5421 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5435 -/* 5426 */ MCD_OPC_CheckPredicate, 0, 109, 62, 1, // Skip to: 86948 -/* 5431 */ MCD_OPC_Decode, 140, 30, 38, // Opcode: SUNPKLO_ZZ_S -/* 5435 */ MCD_OPC_FilterValue, 7, 100, 62, 1, // Skip to: 86948 -/* 5440 */ MCD_OPC_CheckPredicate, 0, 95, 62, 1, // Skip to: 86948 -/* 5445 */ MCD_OPC_Decode, 138, 30, 38, // Opcode: SUNPKLO_ZZ_D -/* 5449 */ MCD_OPC_FilterValue, 17, 45, 0, 0, // Skip to: 5499 -/* 5454 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5457 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5471 -/* 5462 */ MCD_OPC_CheckPredicate, 0, 73, 62, 1, // Skip to: 86948 -/* 5467 */ MCD_OPC_Decode, 136, 30, 38, // Opcode: SUNPKHI_ZZ_H -/* 5471 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5485 -/* 5476 */ MCD_OPC_CheckPredicate, 0, 59, 62, 1, // Skip to: 86948 -/* 5481 */ MCD_OPC_Decode, 137, 30, 38, // Opcode: SUNPKHI_ZZ_S -/* 5485 */ MCD_OPC_FilterValue, 7, 50, 62, 1, // Skip to: 86948 -/* 5490 */ MCD_OPC_CheckPredicate, 0, 45, 62, 1, // Skip to: 86948 -/* 5495 */ MCD_OPC_Decode, 135, 30, 38, // Opcode: SUNPKHI_ZZ_D -/* 5499 */ MCD_OPC_FilterValue, 18, 45, 0, 0, // Skip to: 5549 -/* 5504 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5507 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5521 -/* 5512 */ MCD_OPC_CheckPredicate, 0, 23, 62, 1, // Skip to: 86948 -/* 5517 */ MCD_OPC_Decode, 180, 34, 38, // Opcode: UUNPKLO_ZZ_H -/* 5521 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5535 -/* 5526 */ MCD_OPC_CheckPredicate, 0, 9, 62, 1, // Skip to: 86948 -/* 5531 */ MCD_OPC_Decode, 181, 34, 38, // Opcode: UUNPKLO_ZZ_S -/* 5535 */ MCD_OPC_FilterValue, 7, 0, 62, 1, // Skip to: 86948 -/* 5540 */ MCD_OPC_CheckPredicate, 0, 251, 61, 1, // Skip to: 86948 -/* 5545 */ MCD_OPC_Decode, 179, 34, 38, // Opcode: UUNPKLO_ZZ_D -/* 5549 */ MCD_OPC_FilterValue, 19, 45, 0, 0, // Skip to: 5599 -/* 5554 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5557 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5571 -/* 5562 */ MCD_OPC_CheckPredicate, 0, 229, 61, 1, // Skip to: 86948 -/* 5567 */ MCD_OPC_Decode, 177, 34, 38, // Opcode: UUNPKHI_ZZ_H -/* 5571 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5585 -/* 5576 */ MCD_OPC_CheckPredicate, 0, 215, 61, 1, // Skip to: 86948 -/* 5581 */ MCD_OPC_Decode, 178, 34, 38, // Opcode: UUNPKHI_ZZ_S -/* 5585 */ MCD_OPC_FilterValue, 7, 206, 61, 1, // Skip to: 86948 -/* 5590 */ MCD_OPC_CheckPredicate, 0, 201, 61, 1, // Skip to: 86948 -/* 5595 */ MCD_OPC_Decode, 176, 34, 38, // Opcode: UUNPKHI_ZZ_D -/* 5599 */ MCD_OPC_FilterValue, 20, 59, 0, 0, // Skip to: 5663 -/* 5604 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5607 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5621 -/* 5612 */ MCD_OPC_CheckPredicate, 0, 179, 61, 1, // Skip to: 86948 -/* 5617 */ MCD_OPC_Decode, 150, 14, 39, // Opcode: INSR_ZV_B -/* 5621 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5635 -/* 5626 */ MCD_OPC_CheckPredicate, 0, 165, 61, 1, // Skip to: 86948 -/* 5631 */ MCD_OPC_Decode, 152, 14, 40, // Opcode: INSR_ZV_H -/* 5635 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5649 -/* 5640 */ MCD_OPC_CheckPredicate, 0, 151, 61, 1, // Skip to: 86948 -/* 5645 */ MCD_OPC_Decode, 153, 14, 41, // Opcode: INSR_ZV_S -/* 5649 */ MCD_OPC_FilterValue, 7, 142, 61, 1, // Skip to: 86948 -/* 5654 */ MCD_OPC_CheckPredicate, 0, 137, 61, 1, // Skip to: 86948 -/* 5659 */ MCD_OPC_Decode, 151, 14, 42, // Opcode: INSR_ZV_D -/* 5663 */ MCD_OPC_FilterValue, 24, 128, 61, 1, // Skip to: 86948 -/* 5668 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5671 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5685 -/* 5676 */ MCD_OPC_CheckPredicate, 0, 115, 61, 1, // Skip to: 86948 -/* 5681 */ MCD_OPC_Decode, 227, 21, 38, // Opcode: REV_ZZ_B -/* 5685 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5699 -/* 5690 */ MCD_OPC_CheckPredicate, 0, 101, 61, 1, // Skip to: 86948 -/* 5695 */ MCD_OPC_Decode, 229, 21, 38, // Opcode: REV_ZZ_H -/* 5699 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5713 -/* 5704 */ MCD_OPC_CheckPredicate, 0, 87, 61, 1, // Skip to: 86948 -/* 5709 */ MCD_OPC_Decode, 230, 21, 38, // Opcode: REV_ZZ_S -/* 5713 */ MCD_OPC_FilterValue, 7, 78, 61, 1, // Skip to: 86948 -/* 5718 */ MCD_OPC_CheckPredicate, 0, 73, 61, 1, // Skip to: 86948 -/* 5723 */ MCD_OPC_Decode, 228, 21, 38, // Opcode: REV_ZZ_D -/* 5727 */ MCD_OPC_FilterValue, 1, 229, 6, 0, // Skip to: 7497 -/* 5732 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5735 */ MCD_OPC_FilterValue, 0, 89, 0, 0, // Skip to: 5829 -/* 5740 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 5743 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5779 -/* 5748 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 5751 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5765 -/* 5756 */ MCD_OPC_CheckPredicate, 0, 35, 61, 1, // Skip to: 86948 -/* 5761 */ MCD_OPC_Decode, 130, 14, 43, // Opcode: INDEX_II_B -/* 5765 */ MCD_OPC_FilterValue, 1, 26, 61, 1, // Skip to: 86948 -/* 5770 */ MCD_OPC_CheckPredicate, 0, 21, 61, 1, // Skip to: 86948 -/* 5775 */ MCD_OPC_Decode, 138, 14, 44, // Opcode: INDEX_RI_B -/* 5779 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5815 -/* 5784 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 5787 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5801 -/* 5792 */ MCD_OPC_CheckPredicate, 0, 255, 60, 1, // Skip to: 86948 -/* 5797 */ MCD_OPC_Decode, 134, 14, 45, // Opcode: INDEX_IR_B -/* 5801 */ MCD_OPC_FilterValue, 1, 246, 60, 1, // Skip to: 86948 -/* 5806 */ MCD_OPC_CheckPredicate, 0, 241, 60, 1, // Skip to: 86948 -/* 5811 */ MCD_OPC_Decode, 142, 14, 46, // Opcode: INDEX_RR_B -/* 5815 */ MCD_OPC_FilterValue, 2, 232, 60, 1, // Skip to: 86948 -/* 5820 */ MCD_OPC_CheckPredicate, 0, 227, 60, 1, // Skip to: 86948 -/* 5825 */ MCD_OPC_Decode, 166, 1, 47, // Opcode: ADDVL_XXI -/* 5829 */ MCD_OPC_FilterValue, 1, 89, 0, 0, // Skip to: 5923 -/* 5834 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 5837 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5873 -/* 5842 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 5845 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5859 -/* 5850 */ MCD_OPC_CheckPredicate, 0, 197, 60, 1, // Skip to: 86948 -/* 5855 */ MCD_OPC_Decode, 132, 14, 43, // Opcode: INDEX_II_H -/* 5859 */ MCD_OPC_FilterValue, 1, 188, 60, 1, // Skip to: 86948 -/* 5864 */ MCD_OPC_CheckPredicate, 0, 183, 60, 1, // Skip to: 86948 -/* 5869 */ MCD_OPC_Decode, 140, 14, 44, // Opcode: INDEX_RI_H -/* 5873 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5909 -/* 5878 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 5881 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5895 -/* 5886 */ MCD_OPC_CheckPredicate, 0, 161, 60, 1, // Skip to: 86948 -/* 5891 */ MCD_OPC_Decode, 136, 14, 45, // Opcode: INDEX_IR_H -/* 5895 */ MCD_OPC_FilterValue, 1, 152, 60, 1, // Skip to: 86948 -/* 5900 */ MCD_OPC_CheckPredicate, 0, 147, 60, 1, // Skip to: 86948 -/* 5905 */ MCD_OPC_Decode, 144, 14, 46, // Opcode: INDEX_RR_H -/* 5909 */ MCD_OPC_FilterValue, 2, 138, 60, 1, // Skip to: 86948 -/* 5914 */ MCD_OPC_CheckPredicate, 0, 133, 60, 1, // Skip to: 86948 -/* 5919 */ MCD_OPC_Decode, 148, 1, 47, // Opcode: ADDPL_XXI -/* 5923 */ MCD_OPC_FilterValue, 2, 96, 0, 0, // Skip to: 6024 -/* 5928 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 5931 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5967 -/* 5936 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 5939 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5953 -/* 5944 */ MCD_OPC_CheckPredicate, 0, 103, 60, 1, // Skip to: 86948 -/* 5949 */ MCD_OPC_Decode, 133, 14, 43, // Opcode: INDEX_II_S -/* 5953 */ MCD_OPC_FilterValue, 1, 94, 60, 1, // Skip to: 86948 -/* 5958 */ MCD_OPC_CheckPredicate, 0, 89, 60, 1, // Skip to: 86948 -/* 5963 */ MCD_OPC_Decode, 141, 14, 44, // Opcode: INDEX_RI_S -/* 5967 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 6003 -/* 5972 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 5975 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5989 -/* 5980 */ MCD_OPC_CheckPredicate, 0, 67, 60, 1, // Skip to: 86948 -/* 5985 */ MCD_OPC_Decode, 137, 14, 45, // Opcode: INDEX_IR_S -/* 5989 */ MCD_OPC_FilterValue, 1, 58, 60, 1, // Skip to: 86948 -/* 5994 */ MCD_OPC_CheckPredicate, 0, 53, 60, 1, // Skip to: 86948 -/* 5999 */ MCD_OPC_Decode, 145, 14, 46, // Opcode: INDEX_RR_S -/* 6003 */ MCD_OPC_FilterValue, 2, 44, 60, 1, // Skip to: 86948 -/* 6008 */ MCD_OPC_CheckPredicate, 0, 39, 60, 1, // Skip to: 86948 -/* 6013 */ MCD_OPC_CheckField, 16, 5, 31, 32, 60, 1, // Skip to: 86948 -/* 6020 */ MCD_OPC_Decode, 195, 21, 48, // Opcode: RDVLI_XI -/* 6024 */ MCD_OPC_FilterValue, 3, 59, 0, 0, // Skip to: 6088 -/* 6029 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 6032 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6046 -/* 6037 */ MCD_OPC_CheckPredicate, 0, 10, 60, 1, // Skip to: 86948 -/* 6042 */ MCD_OPC_Decode, 131, 14, 43, // Opcode: INDEX_II_D -/* 6046 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6060 -/* 6051 */ MCD_OPC_CheckPredicate, 0, 252, 59, 1, // Skip to: 86948 -/* 6056 */ MCD_OPC_Decode, 139, 14, 49, // Opcode: INDEX_RI_D -/* 6060 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6074 -/* 6065 */ MCD_OPC_CheckPredicate, 0, 238, 59, 1, // Skip to: 86948 -/* 6070 */ MCD_OPC_Decode, 135, 14, 50, // Opcode: INDEX_IR_D -/* 6074 */ MCD_OPC_FilterValue, 3, 229, 59, 1, // Skip to: 86948 -/* 6079 */ MCD_OPC_CheckPredicate, 0, 224, 59, 1, // Skip to: 86948 -/* 6084 */ MCD_OPC_Decode, 143, 14, 51, // Opcode: INDEX_RR_D -/* 6088 */ MCD_OPC_FilterValue, 4, 134, 1, 0, // Skip to: 6483 -/* 6093 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 6096 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 6224 -/* 6101 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6104 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6132 -/* 6109 */ MCD_OPC_CheckPredicate, 0, 194, 59, 1, // Skip to: 86948 -/* 6114 */ MCD_OPC_CheckField, 9, 1, 0, 187, 59, 1, // Skip to: 86948 -/* 6121 */ MCD_OPC_CheckField, 4, 1, 0, 180, 59, 1, // Skip to: 86948 -/* 6128 */ MCD_OPC_Decode, 133, 35, 52, // Opcode: ZIP1_PPP_B -/* 6132 */ MCD_OPC_FilterValue, 1, 171, 59, 1, // Skip to: 86948 -/* 6137 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6140 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6168 -/* 6145 */ MCD_OPC_CheckPredicate, 0, 158, 59, 1, // Skip to: 86948 -/* 6150 */ MCD_OPC_CheckField, 9, 1, 0, 151, 59, 1, // Skip to: 86948 -/* 6157 */ MCD_OPC_CheckField, 4, 1, 0, 144, 59, 1, // Skip to: 86948 -/* 6164 */ MCD_OPC_Decode, 176, 21, 53, // Opcode: PUNPKLO_PP -/* 6168 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 6196 -/* 6173 */ MCD_OPC_CheckPredicate, 0, 130, 59, 1, // Skip to: 86948 -/* 6178 */ MCD_OPC_CheckField, 9, 1, 0, 123, 59, 1, // Skip to: 86948 -/* 6185 */ MCD_OPC_CheckField, 4, 1, 0, 116, 59, 1, // Skip to: 86948 -/* 6192 */ MCD_OPC_Decode, 175, 21, 53, // Opcode: PUNPKHI_PP -/* 6196 */ MCD_OPC_FilterValue, 4, 107, 59, 1, // Skip to: 86948 -/* 6201 */ MCD_OPC_CheckPredicate, 0, 102, 59, 1, // Skip to: 86948 -/* 6206 */ MCD_OPC_CheckField, 9, 1, 0, 95, 59, 1, // Skip to: 86948 -/* 6213 */ MCD_OPC_CheckField, 4, 1, 0, 88, 59, 1, // Skip to: 86948 -/* 6220 */ MCD_OPC_Decode, 223, 21, 53, // Opcode: REV_PP_B -/* 6224 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 6259 -/* 6229 */ MCD_OPC_CheckPredicate, 0, 74, 59, 1, // Skip to: 86948 -/* 6234 */ MCD_OPC_CheckField, 20, 1, 0, 67, 59, 1, // Skip to: 86948 -/* 6241 */ MCD_OPC_CheckField, 9, 1, 0, 60, 59, 1, // Skip to: 86948 -/* 6248 */ MCD_OPC_CheckField, 4, 1, 0, 53, 59, 1, // Skip to: 86948 -/* 6255 */ MCD_OPC_Decode, 148, 35, 52, // Opcode: ZIP2_PPP_B -/* 6259 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6294 -/* 6264 */ MCD_OPC_CheckPredicate, 0, 39, 59, 1, // Skip to: 86948 -/* 6269 */ MCD_OPC_CheckField, 20, 1, 0, 32, 59, 1, // Skip to: 86948 -/* 6276 */ MCD_OPC_CheckField, 9, 1, 0, 25, 59, 1, // Skip to: 86948 -/* 6283 */ MCD_OPC_CheckField, 4, 1, 0, 18, 59, 1, // Skip to: 86948 -/* 6290 */ MCD_OPC_Decode, 188, 34, 52, // Opcode: UZP1_PPP_B -/* 6294 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 6329 -/* 6299 */ MCD_OPC_CheckPredicate, 0, 4, 59, 1, // Skip to: 86948 -/* 6304 */ MCD_OPC_CheckField, 20, 1, 0, 253, 58, 1, // Skip to: 86948 -/* 6311 */ MCD_OPC_CheckField, 9, 1, 0, 246, 58, 1, // Skip to: 86948 -/* 6318 */ MCD_OPC_CheckField, 4, 1, 0, 239, 58, 1, // Skip to: 86948 -/* 6325 */ MCD_OPC_Decode, 203, 34, 52, // Opcode: UZP2_PPP_B -/* 6329 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 6364 -/* 6334 */ MCD_OPC_CheckPredicate, 0, 225, 58, 1, // Skip to: 86948 -/* 6339 */ MCD_OPC_CheckField, 20, 1, 0, 218, 58, 1, // Skip to: 86948 -/* 6346 */ MCD_OPC_CheckField, 9, 1, 0, 211, 58, 1, // Skip to: 86948 -/* 6353 */ MCD_OPC_CheckField, 4, 1, 0, 204, 58, 1, // Skip to: 86948 -/* 6360 */ MCD_OPC_Decode, 205, 30, 52, // Opcode: TRN1_PPP_B -/* 6364 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 6399 -/* 6369 */ MCD_OPC_CheckPredicate, 0, 190, 58, 1, // Skip to: 86948 -/* 6374 */ MCD_OPC_CheckField, 20, 1, 0, 183, 58, 1, // Skip to: 86948 -/* 6381 */ MCD_OPC_CheckField, 9, 1, 0, 176, 58, 1, // Skip to: 86948 -/* 6388 */ MCD_OPC_CheckField, 4, 1, 0, 169, 58, 1, // Skip to: 86948 -/* 6395 */ MCD_OPC_Decode, 220, 30, 52, // Opcode: TRN2_PPP_B -/* 6399 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 6413 -/* 6404 */ MCD_OPC_CheckPredicate, 0, 155, 58, 1, // Skip to: 86948 -/* 6409 */ MCD_OPC_Decode, 137, 35, 27, // Opcode: ZIP1_ZZZ_B -/* 6413 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 6427 -/* 6418 */ MCD_OPC_CheckPredicate, 0, 141, 58, 1, // Skip to: 86948 -/* 6423 */ MCD_OPC_Decode, 152, 35, 27, // Opcode: ZIP2_ZZZ_B -/* 6427 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 6441 -/* 6432 */ MCD_OPC_CheckPredicate, 0, 127, 58, 1, // Skip to: 86948 -/* 6437 */ MCD_OPC_Decode, 192, 34, 27, // Opcode: UZP1_ZZZ_B -/* 6441 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 6455 -/* 6446 */ MCD_OPC_CheckPredicate, 0, 113, 58, 1, // Skip to: 86948 -/* 6451 */ MCD_OPC_Decode, 207, 34, 27, // Opcode: UZP2_ZZZ_B -/* 6455 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 6469 -/* 6460 */ MCD_OPC_CheckPredicate, 0, 99, 58, 1, // Skip to: 86948 -/* 6465 */ MCD_OPC_Decode, 209, 30, 27, // Opcode: TRN1_ZZZ_B -/* 6469 */ MCD_OPC_FilterValue, 13, 90, 58, 1, // Skip to: 86948 -/* 6474 */ MCD_OPC_CheckPredicate, 0, 85, 58, 1, // Skip to: 86948 -/* 6479 */ MCD_OPC_Decode, 224, 30, 27, // Opcode: TRN2_ZZZ_B -/* 6483 */ MCD_OPC_FilterValue, 5, 77, 1, 0, // Skip to: 6821 -/* 6488 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 6491 */ MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 6562 -/* 6496 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6499 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6527 -/* 6504 */ MCD_OPC_CheckPredicate, 0, 55, 58, 1, // Skip to: 86948 -/* 6509 */ MCD_OPC_CheckField, 9, 1, 0, 48, 58, 1, // Skip to: 86948 -/* 6516 */ MCD_OPC_CheckField, 4, 1, 0, 41, 58, 1, // Skip to: 86948 -/* 6523 */ MCD_OPC_Decode, 135, 35, 52, // Opcode: ZIP1_PPP_H -/* 6527 */ MCD_OPC_FilterValue, 1, 32, 58, 1, // Skip to: 86948 -/* 6532 */ MCD_OPC_CheckPredicate, 0, 27, 58, 1, // Skip to: 86948 -/* 6537 */ MCD_OPC_CheckField, 16, 4, 4, 20, 58, 1, // Skip to: 86948 -/* 6544 */ MCD_OPC_CheckField, 9, 1, 0, 13, 58, 1, // Skip to: 86948 -/* 6551 */ MCD_OPC_CheckField, 4, 1, 0, 6, 58, 1, // Skip to: 86948 -/* 6558 */ MCD_OPC_Decode, 225, 21, 53, // Opcode: REV_PP_H -/* 6562 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 6597 -/* 6567 */ MCD_OPC_CheckPredicate, 0, 248, 57, 1, // Skip to: 86948 -/* 6572 */ MCD_OPC_CheckField, 20, 1, 0, 241, 57, 1, // Skip to: 86948 -/* 6579 */ MCD_OPC_CheckField, 9, 1, 0, 234, 57, 1, // Skip to: 86948 -/* 6586 */ MCD_OPC_CheckField, 4, 1, 0, 227, 57, 1, // Skip to: 86948 -/* 6593 */ MCD_OPC_Decode, 150, 35, 52, // Opcode: ZIP2_PPP_H -/* 6597 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6632 -/* 6602 */ MCD_OPC_CheckPredicate, 0, 213, 57, 1, // Skip to: 86948 -/* 6607 */ MCD_OPC_CheckField, 20, 1, 0, 206, 57, 1, // Skip to: 86948 -/* 6614 */ MCD_OPC_CheckField, 9, 1, 0, 199, 57, 1, // Skip to: 86948 -/* 6621 */ MCD_OPC_CheckField, 4, 1, 0, 192, 57, 1, // Skip to: 86948 -/* 6628 */ MCD_OPC_Decode, 190, 34, 52, // Opcode: UZP1_PPP_H -/* 6632 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 6667 -/* 6637 */ MCD_OPC_CheckPredicate, 0, 178, 57, 1, // Skip to: 86948 -/* 6642 */ MCD_OPC_CheckField, 20, 1, 0, 171, 57, 1, // Skip to: 86948 -/* 6649 */ MCD_OPC_CheckField, 9, 1, 0, 164, 57, 1, // Skip to: 86948 -/* 6656 */ MCD_OPC_CheckField, 4, 1, 0, 157, 57, 1, // Skip to: 86948 -/* 6663 */ MCD_OPC_Decode, 205, 34, 52, // Opcode: UZP2_PPP_H -/* 6667 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 6702 -/* 6672 */ MCD_OPC_CheckPredicate, 0, 143, 57, 1, // Skip to: 86948 -/* 6677 */ MCD_OPC_CheckField, 20, 1, 0, 136, 57, 1, // Skip to: 86948 -/* 6684 */ MCD_OPC_CheckField, 9, 1, 0, 129, 57, 1, // Skip to: 86948 -/* 6691 */ MCD_OPC_CheckField, 4, 1, 0, 122, 57, 1, // Skip to: 86948 -/* 6698 */ MCD_OPC_Decode, 207, 30, 52, // Opcode: TRN1_PPP_H -/* 6702 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 6737 -/* 6707 */ MCD_OPC_CheckPredicate, 0, 108, 57, 1, // Skip to: 86948 -/* 6712 */ MCD_OPC_CheckField, 20, 1, 0, 101, 57, 1, // Skip to: 86948 -/* 6719 */ MCD_OPC_CheckField, 9, 1, 0, 94, 57, 1, // Skip to: 86948 -/* 6726 */ MCD_OPC_CheckField, 4, 1, 0, 87, 57, 1, // Skip to: 86948 -/* 6733 */ MCD_OPC_Decode, 222, 30, 52, // Opcode: TRN2_PPP_H -/* 6737 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 6751 -/* 6742 */ MCD_OPC_CheckPredicate, 0, 73, 57, 1, // Skip to: 86948 -/* 6747 */ MCD_OPC_Decode, 139, 35, 27, // Opcode: ZIP1_ZZZ_H -/* 6751 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 6765 -/* 6756 */ MCD_OPC_CheckPredicate, 0, 59, 57, 1, // Skip to: 86948 -/* 6761 */ MCD_OPC_Decode, 154, 35, 27, // Opcode: ZIP2_ZZZ_H -/* 6765 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 6779 -/* 6770 */ MCD_OPC_CheckPredicate, 0, 45, 57, 1, // Skip to: 86948 -/* 6775 */ MCD_OPC_Decode, 194, 34, 27, // Opcode: UZP1_ZZZ_H -/* 6779 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 6793 -/* 6784 */ MCD_OPC_CheckPredicate, 0, 31, 57, 1, // Skip to: 86948 -/* 6789 */ MCD_OPC_Decode, 209, 34, 27, // Opcode: UZP2_ZZZ_H -/* 6793 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 6807 -/* 6798 */ MCD_OPC_CheckPredicate, 0, 17, 57, 1, // Skip to: 86948 -/* 6803 */ MCD_OPC_Decode, 211, 30, 27, // Opcode: TRN1_ZZZ_H -/* 6807 */ MCD_OPC_FilterValue, 13, 8, 57, 1, // Skip to: 86948 -/* 6812 */ MCD_OPC_CheckPredicate, 0, 3, 57, 1, // Skip to: 86948 -/* 6817 */ MCD_OPC_Decode, 226, 30, 27, // Opcode: TRN2_ZZZ_H -/* 6821 */ MCD_OPC_FilterValue, 6, 77, 1, 0, // Skip to: 7159 -/* 6826 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 6829 */ MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 6900 -/* 6834 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6837 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6865 -/* 6842 */ MCD_OPC_CheckPredicate, 0, 229, 56, 1, // Skip to: 86948 -/* 6847 */ MCD_OPC_CheckField, 9, 1, 0, 222, 56, 1, // Skip to: 86948 -/* 6854 */ MCD_OPC_CheckField, 4, 1, 0, 215, 56, 1, // Skip to: 86948 -/* 6861 */ MCD_OPC_Decode, 136, 35, 52, // Opcode: ZIP1_PPP_S -/* 6865 */ MCD_OPC_FilterValue, 1, 206, 56, 1, // Skip to: 86948 -/* 6870 */ MCD_OPC_CheckPredicate, 0, 201, 56, 1, // Skip to: 86948 -/* 6875 */ MCD_OPC_CheckField, 16, 4, 4, 194, 56, 1, // Skip to: 86948 -/* 6882 */ MCD_OPC_CheckField, 9, 1, 0, 187, 56, 1, // Skip to: 86948 -/* 6889 */ MCD_OPC_CheckField, 4, 1, 0, 180, 56, 1, // Skip to: 86948 -/* 6896 */ MCD_OPC_Decode, 226, 21, 53, // Opcode: REV_PP_S -/* 6900 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 6935 -/* 6905 */ MCD_OPC_CheckPredicate, 0, 166, 56, 1, // Skip to: 86948 -/* 6910 */ MCD_OPC_CheckField, 20, 1, 0, 159, 56, 1, // Skip to: 86948 -/* 6917 */ MCD_OPC_CheckField, 9, 1, 0, 152, 56, 1, // Skip to: 86948 -/* 6924 */ MCD_OPC_CheckField, 4, 1, 0, 145, 56, 1, // Skip to: 86948 -/* 6931 */ MCD_OPC_Decode, 151, 35, 52, // Opcode: ZIP2_PPP_S -/* 6935 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6970 -/* 6940 */ MCD_OPC_CheckPredicate, 0, 131, 56, 1, // Skip to: 86948 -/* 6945 */ MCD_OPC_CheckField, 20, 1, 0, 124, 56, 1, // Skip to: 86948 -/* 6952 */ MCD_OPC_CheckField, 9, 1, 0, 117, 56, 1, // Skip to: 86948 -/* 6959 */ MCD_OPC_CheckField, 4, 1, 0, 110, 56, 1, // Skip to: 86948 -/* 6966 */ MCD_OPC_Decode, 191, 34, 52, // Opcode: UZP1_PPP_S -/* 6970 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 7005 -/* 6975 */ MCD_OPC_CheckPredicate, 0, 96, 56, 1, // Skip to: 86948 -/* 6980 */ MCD_OPC_CheckField, 20, 1, 0, 89, 56, 1, // Skip to: 86948 -/* 6987 */ MCD_OPC_CheckField, 9, 1, 0, 82, 56, 1, // Skip to: 86948 -/* 6994 */ MCD_OPC_CheckField, 4, 1, 0, 75, 56, 1, // Skip to: 86948 -/* 7001 */ MCD_OPC_Decode, 206, 34, 52, // Opcode: UZP2_PPP_S -/* 7005 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 7040 -/* 7010 */ MCD_OPC_CheckPredicate, 0, 61, 56, 1, // Skip to: 86948 -/* 7015 */ MCD_OPC_CheckField, 20, 1, 0, 54, 56, 1, // Skip to: 86948 -/* 7022 */ MCD_OPC_CheckField, 9, 1, 0, 47, 56, 1, // Skip to: 86948 -/* 7029 */ MCD_OPC_CheckField, 4, 1, 0, 40, 56, 1, // Skip to: 86948 -/* 7036 */ MCD_OPC_Decode, 208, 30, 52, // Opcode: TRN1_PPP_S -/* 7040 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 7075 -/* 7045 */ MCD_OPC_CheckPredicate, 0, 26, 56, 1, // Skip to: 86948 -/* 7050 */ MCD_OPC_CheckField, 20, 1, 0, 19, 56, 1, // Skip to: 86948 -/* 7057 */ MCD_OPC_CheckField, 9, 1, 0, 12, 56, 1, // Skip to: 86948 -/* 7064 */ MCD_OPC_CheckField, 4, 1, 0, 5, 56, 1, // Skip to: 86948 -/* 7071 */ MCD_OPC_Decode, 223, 30, 52, // Opcode: TRN2_PPP_S -/* 7075 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7089 -/* 7080 */ MCD_OPC_CheckPredicate, 0, 247, 55, 1, // Skip to: 86948 -/* 7085 */ MCD_OPC_Decode, 140, 35, 27, // Opcode: ZIP1_ZZZ_S -/* 7089 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 7103 -/* 7094 */ MCD_OPC_CheckPredicate, 0, 233, 55, 1, // Skip to: 86948 -/* 7099 */ MCD_OPC_Decode, 155, 35, 27, // Opcode: ZIP2_ZZZ_S -/* 7103 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7117 -/* 7108 */ MCD_OPC_CheckPredicate, 0, 219, 55, 1, // Skip to: 86948 -/* 7113 */ MCD_OPC_Decode, 195, 34, 27, // Opcode: UZP1_ZZZ_S -/* 7117 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 7131 -/* 7122 */ MCD_OPC_CheckPredicate, 0, 205, 55, 1, // Skip to: 86948 -/* 7127 */ MCD_OPC_Decode, 210, 34, 27, // Opcode: UZP2_ZZZ_S -/* 7131 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 7145 -/* 7136 */ MCD_OPC_CheckPredicate, 0, 191, 55, 1, // Skip to: 86948 -/* 7141 */ MCD_OPC_Decode, 212, 30, 27, // Opcode: TRN1_ZZZ_S -/* 7145 */ MCD_OPC_FilterValue, 13, 182, 55, 1, // Skip to: 86948 -/* 7150 */ MCD_OPC_CheckPredicate, 0, 177, 55, 1, // Skip to: 86948 -/* 7155 */ MCD_OPC_Decode, 227, 30, 27, // Opcode: TRN2_ZZZ_S -/* 7159 */ MCD_OPC_FilterValue, 7, 168, 55, 1, // Skip to: 86948 -/* 7164 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 7167 */ MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 7238 -/* 7172 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7175 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 7203 -/* 7180 */ MCD_OPC_CheckPredicate, 0, 147, 55, 1, // Skip to: 86948 -/* 7185 */ MCD_OPC_CheckField, 9, 1, 0, 140, 55, 1, // Skip to: 86948 -/* 7192 */ MCD_OPC_CheckField, 4, 1, 0, 133, 55, 1, // Skip to: 86948 -/* 7199 */ MCD_OPC_Decode, 134, 35, 52, // Opcode: ZIP1_PPP_D -/* 7203 */ MCD_OPC_FilterValue, 1, 124, 55, 1, // Skip to: 86948 -/* 7208 */ MCD_OPC_CheckPredicate, 0, 119, 55, 1, // Skip to: 86948 -/* 7213 */ MCD_OPC_CheckField, 16, 4, 4, 112, 55, 1, // Skip to: 86948 -/* 7220 */ MCD_OPC_CheckField, 9, 1, 0, 105, 55, 1, // Skip to: 86948 -/* 7227 */ MCD_OPC_CheckField, 4, 1, 0, 98, 55, 1, // Skip to: 86948 -/* 7234 */ MCD_OPC_Decode, 224, 21, 53, // Opcode: REV_PP_D -/* 7238 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 7273 -/* 7243 */ MCD_OPC_CheckPredicate, 0, 84, 55, 1, // Skip to: 86948 -/* 7248 */ MCD_OPC_CheckField, 20, 1, 0, 77, 55, 1, // Skip to: 86948 -/* 7255 */ MCD_OPC_CheckField, 9, 1, 0, 70, 55, 1, // Skip to: 86948 -/* 7262 */ MCD_OPC_CheckField, 4, 1, 0, 63, 55, 1, // Skip to: 86948 -/* 7269 */ MCD_OPC_Decode, 149, 35, 52, // Opcode: ZIP2_PPP_D -/* 7273 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 7308 -/* 7278 */ MCD_OPC_CheckPredicate, 0, 49, 55, 1, // Skip to: 86948 -/* 7283 */ MCD_OPC_CheckField, 20, 1, 0, 42, 55, 1, // Skip to: 86948 -/* 7290 */ MCD_OPC_CheckField, 9, 1, 0, 35, 55, 1, // Skip to: 86948 -/* 7297 */ MCD_OPC_CheckField, 4, 1, 0, 28, 55, 1, // Skip to: 86948 -/* 7304 */ MCD_OPC_Decode, 189, 34, 52, // Opcode: UZP1_PPP_D -/* 7308 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 7343 -/* 7313 */ MCD_OPC_CheckPredicate, 0, 14, 55, 1, // Skip to: 86948 -/* 7318 */ MCD_OPC_CheckField, 20, 1, 0, 7, 55, 1, // Skip to: 86948 -/* 7325 */ MCD_OPC_CheckField, 9, 1, 0, 0, 55, 1, // Skip to: 86948 -/* 7332 */ MCD_OPC_CheckField, 4, 1, 0, 249, 54, 1, // Skip to: 86948 -/* 7339 */ MCD_OPC_Decode, 204, 34, 52, // Opcode: UZP2_PPP_D -/* 7343 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 7378 -/* 7348 */ MCD_OPC_CheckPredicate, 0, 235, 54, 1, // Skip to: 86948 -/* 7353 */ MCD_OPC_CheckField, 20, 1, 0, 228, 54, 1, // Skip to: 86948 -/* 7360 */ MCD_OPC_CheckField, 9, 1, 0, 221, 54, 1, // Skip to: 86948 -/* 7367 */ MCD_OPC_CheckField, 4, 1, 0, 214, 54, 1, // Skip to: 86948 -/* 7374 */ MCD_OPC_Decode, 206, 30, 52, // Opcode: TRN1_PPP_D -/* 7378 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 7413 -/* 7383 */ MCD_OPC_CheckPredicate, 0, 200, 54, 1, // Skip to: 86948 -/* 7388 */ MCD_OPC_CheckField, 20, 1, 0, 193, 54, 1, // Skip to: 86948 -/* 7395 */ MCD_OPC_CheckField, 9, 1, 0, 186, 54, 1, // Skip to: 86948 -/* 7402 */ MCD_OPC_CheckField, 4, 1, 0, 179, 54, 1, // Skip to: 86948 -/* 7409 */ MCD_OPC_Decode, 221, 30, 52, // Opcode: TRN2_PPP_D -/* 7413 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7427 -/* 7418 */ MCD_OPC_CheckPredicate, 0, 165, 54, 1, // Skip to: 86948 -/* 7423 */ MCD_OPC_Decode, 138, 35, 27, // Opcode: ZIP1_ZZZ_D -/* 7427 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 7441 -/* 7432 */ MCD_OPC_CheckPredicate, 0, 151, 54, 1, // Skip to: 86948 -/* 7437 */ MCD_OPC_Decode, 153, 35, 27, // Opcode: ZIP2_ZZZ_D -/* 7441 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7455 -/* 7446 */ MCD_OPC_CheckPredicate, 0, 137, 54, 1, // Skip to: 86948 -/* 7451 */ MCD_OPC_Decode, 193, 34, 27, // Opcode: UZP1_ZZZ_D -/* 7455 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 7469 -/* 7460 */ MCD_OPC_CheckPredicate, 0, 123, 54, 1, // Skip to: 86948 -/* 7465 */ MCD_OPC_Decode, 208, 34, 27, // Opcode: UZP2_ZZZ_D -/* 7469 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 7483 -/* 7474 */ MCD_OPC_CheckPredicate, 0, 109, 54, 1, // Skip to: 86948 -/* 7479 */ MCD_OPC_Decode, 210, 30, 27, // Opcode: TRN1_ZZZ_D -/* 7483 */ MCD_OPC_FilterValue, 13, 100, 54, 1, // Skip to: 86948 -/* 7488 */ MCD_OPC_CheckPredicate, 0, 95, 54, 1, // Skip to: 86948 -/* 7493 */ MCD_OPC_Decode, 225, 30, 27, // Opcode: TRN2_ZZZ_D -/* 7497 */ MCD_OPC_FilterValue, 2, 96, 9, 0, // Skip to: 9902 -/* 7502 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 7505 */ MCD_OPC_FilterValue, 0, 15, 2, 0, // Skip to: 8037 -/* 7510 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 7513 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7549 -/* 7518 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7521 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7535 -/* 7526 */ MCD_OPC_CheckPredicate, 0, 57, 54, 1, // Skip to: 86948 -/* 7531 */ MCD_OPC_Decode, 139, 2, 27, // Opcode: ASR_WIDE_ZZZ_B -/* 7535 */ MCD_OPC_FilterValue, 1, 48, 54, 1, // Skip to: 86948 -/* 7540 */ MCD_OPC_CheckPredicate, 0, 43, 54, 1, // Skip to: 86948 -/* 7545 */ MCD_OPC_Decode, 140, 2, 27, // Opcode: ASR_WIDE_ZZZ_H -/* 7549 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 7585 -/* 7554 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7557 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7571 -/* 7562 */ MCD_OPC_CheckPredicate, 0, 21, 54, 1, // Skip to: 86948 -/* 7567 */ MCD_OPC_Decode, 184, 19, 27, // Opcode: LSR_WIDE_ZZZ_B -/* 7571 */ MCD_OPC_FilterValue, 1, 12, 54, 1, // Skip to: 86948 -/* 7576 */ MCD_OPC_CheckPredicate, 0, 7, 54, 1, // Skip to: 86948 -/* 7581 */ MCD_OPC_Decode, 185, 19, 27, // Opcode: LSR_WIDE_ZZZ_H -/* 7585 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 7621 -/* 7590 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7593 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7607 -/* 7598 */ MCD_OPC_CheckPredicate, 0, 241, 53, 1, // Skip to: 86948 -/* 7603 */ MCD_OPC_Decode, 160, 19, 27, // Opcode: LSL_WIDE_ZZZ_B -/* 7607 */ MCD_OPC_FilterValue, 1, 232, 53, 1, // Skip to: 86948 -/* 7612 */ MCD_OPC_CheckPredicate, 0, 227, 53, 1, // Skip to: 86948 -/* 7617 */ MCD_OPC_Decode, 161, 19, 27, // Opcode: LSL_WIDE_ZZZ_H -/* 7621 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 7686 -/* 7626 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7629 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7672 -/* 7634 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7637 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7658 -/* 7642 */ MCD_OPC_CheckPredicate, 0, 197, 53, 1, // Skip to: 86948 -/* 7647 */ MCD_OPC_CheckField, 19, 1, 1, 190, 53, 1, // Skip to: 86948 -/* 7654 */ MCD_OPC_Decode, 150, 2, 54, // Opcode: ASR_ZZI_B -/* 7658 */ MCD_OPC_FilterValue, 1, 181, 53, 1, // Skip to: 86948 -/* 7663 */ MCD_OPC_CheckPredicate, 0, 176, 53, 1, // Skip to: 86948 -/* 7668 */ MCD_OPC_Decode, 152, 2, 55, // Opcode: ASR_ZZI_H -/* 7672 */ MCD_OPC_FilterValue, 1, 167, 53, 1, // Skip to: 86948 -/* 7677 */ MCD_OPC_CheckPredicate, 0, 162, 53, 1, // Skip to: 86948 -/* 7682 */ MCD_OPC_Decode, 153, 2, 56, // Opcode: ASR_ZZI_S -/* 7686 */ MCD_OPC_FilterValue, 5, 60, 0, 0, // Skip to: 7751 -/* 7691 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7694 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7737 -/* 7699 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7702 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7723 -/* 7707 */ MCD_OPC_CheckPredicate, 0, 132, 53, 1, // Skip to: 86948 -/* 7712 */ MCD_OPC_CheckField, 19, 1, 1, 125, 53, 1, // Skip to: 86948 -/* 7719 */ MCD_OPC_Decode, 195, 19, 54, // Opcode: LSR_ZZI_B -/* 7723 */ MCD_OPC_FilterValue, 1, 116, 53, 1, // Skip to: 86948 -/* 7728 */ MCD_OPC_CheckPredicate, 0, 111, 53, 1, // Skip to: 86948 -/* 7733 */ MCD_OPC_Decode, 197, 19, 55, // Opcode: LSR_ZZI_H -/* 7737 */ MCD_OPC_FilterValue, 1, 102, 53, 1, // Skip to: 86948 -/* 7742 */ MCD_OPC_CheckPredicate, 0, 97, 53, 1, // Skip to: 86948 -/* 7747 */ MCD_OPC_Decode, 198, 19, 56, // Opcode: LSR_ZZI_S -/* 7751 */ MCD_OPC_FilterValue, 7, 60, 0, 0, // Skip to: 7816 -/* 7756 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7759 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7802 -/* 7764 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7767 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7788 -/* 7772 */ MCD_OPC_CheckPredicate, 0, 67, 53, 1, // Skip to: 86948 -/* 7777 */ MCD_OPC_CheckField, 19, 1, 1, 60, 53, 1, // Skip to: 86948 -/* 7784 */ MCD_OPC_Decode, 171, 19, 57, // Opcode: LSL_ZZI_B -/* 7788 */ MCD_OPC_FilterValue, 1, 51, 53, 1, // Skip to: 86948 -/* 7793 */ MCD_OPC_CheckPredicate, 0, 46, 53, 1, // Skip to: 86948 -/* 7798 */ MCD_OPC_Decode, 173, 19, 58, // Opcode: LSL_ZZI_H -/* 7802 */ MCD_OPC_FilterValue, 1, 37, 53, 1, // Skip to: 86948 -/* 7807 */ MCD_OPC_CheckPredicate, 0, 32, 53, 1, // Skip to: 86948 -/* 7812 */ MCD_OPC_Decode, 174, 19, 59, // Opcode: LSL_ZZI_S -/* 7816 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 7852 -/* 7821 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7824 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7838 -/* 7829 */ MCD_OPC_CheckPredicate, 0, 10, 53, 1, // Skip to: 86948 -/* 7834 */ MCD_OPC_Decode, 214, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_0 -/* 7838 */ MCD_OPC_FilterValue, 1, 1, 53, 1, // Skip to: 86948 -/* 7843 */ MCD_OPC_CheckPredicate, 0, 252, 52, 1, // Skip to: 86948 -/* 7848 */ MCD_OPC_Decode, 218, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_0 -/* 7852 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 7888 -/* 7857 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7860 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7874 -/* 7865 */ MCD_OPC_CheckPredicate, 0, 230, 52, 1, // Skip to: 86948 -/* 7870 */ MCD_OPC_Decode, 215, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_1 -/* 7874 */ MCD_OPC_FilterValue, 1, 221, 52, 1, // Skip to: 86948 -/* 7879 */ MCD_OPC_CheckPredicate, 0, 216, 52, 1, // Skip to: 86948 -/* 7884 */ MCD_OPC_Decode, 219, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_1 -/* 7888 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 7924 -/* 7893 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7896 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7910 -/* 7901 */ MCD_OPC_CheckPredicate, 0, 194, 52, 1, // Skip to: 86948 -/* 7906 */ MCD_OPC_Decode, 216, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_2 -/* 7910 */ MCD_OPC_FilterValue, 1, 185, 52, 1, // Skip to: 86948 -/* 7915 */ MCD_OPC_CheckPredicate, 0, 180, 52, 1, // Skip to: 86948 -/* 7920 */ MCD_OPC_Decode, 220, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_2 -/* 7924 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 7960 -/* 7929 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 7932 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7946 -/* 7937 */ MCD_OPC_CheckPredicate, 0, 158, 52, 1, // Skip to: 86948 -/* 7942 */ MCD_OPC_Decode, 217, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_3 -/* 7946 */ MCD_OPC_FilterValue, 1, 149, 52, 1, // Skip to: 86948 -/* 7951 */ MCD_OPC_CheckPredicate, 0, 144, 52, 1, // Skip to: 86948 -/* 7956 */ MCD_OPC_Decode, 221, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_3 -/* 7960 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 7981 -/* 7965 */ MCD_OPC_CheckPredicate, 0, 130, 52, 1, // Skip to: 86948 -/* 7970 */ MCD_OPC_CheckField, 22, 1, 1, 123, 52, 1, // Skip to: 86948 -/* 7977 */ MCD_OPC_Decode, 239, 12, 27, // Opcode: FTSSEL_ZZZ_H -/* 7981 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 8009 -/* 7986 */ MCD_OPC_CheckPredicate, 0, 109, 52, 1, // Skip to: 86948 -/* 7991 */ MCD_OPC_CheckField, 22, 1, 1, 102, 52, 1, // Skip to: 86948 -/* 7998 */ MCD_OPC_CheckField, 16, 5, 0, 95, 52, 1, // Skip to: 86948 -/* 8005 */ MCD_OPC_Decode, 184, 9, 38, // Opcode: FEXPA_ZZ_H -/* 8009 */ MCD_OPC_FilterValue, 15, 86, 52, 1, // Skip to: 86948 -/* 8014 */ MCD_OPC_CheckPredicate, 0, 81, 52, 1, // Skip to: 86948 -/* 8019 */ MCD_OPC_CheckField, 22, 1, 0, 74, 52, 1, // Skip to: 86948 -/* 8026 */ MCD_OPC_CheckField, 16, 5, 0, 67, 52, 1, // Skip to: 86948 -/* 8033 */ MCD_OPC_Decode, 255, 19, 38, // Opcode: MOVPRFX_ZZ -/* 8037 */ MCD_OPC_FilterValue, 1, 82, 1, 0, // Skip to: 8380 -/* 8042 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 8045 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8066 -/* 8050 */ MCD_OPC_CheckPredicate, 0, 45, 52, 1, // Skip to: 86948 -/* 8055 */ MCD_OPC_CheckField, 22, 1, 0, 38, 52, 1, // Skip to: 86948 -/* 8062 */ MCD_OPC_Decode, 141, 2, 27, // Opcode: ASR_WIDE_ZZZ_S -/* 8066 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 8087 -/* 8071 */ MCD_OPC_CheckPredicate, 0, 24, 52, 1, // Skip to: 86948 -/* 8076 */ MCD_OPC_CheckField, 22, 1, 0, 17, 52, 1, // Skip to: 86948 -/* 8083 */ MCD_OPC_Decode, 186, 19, 27, // Opcode: LSR_WIDE_ZZZ_S -/* 8087 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 8108 -/* 8092 */ MCD_OPC_CheckPredicate, 0, 3, 52, 1, // Skip to: 86948 -/* 8097 */ MCD_OPC_CheckField, 22, 1, 0, 252, 51, 1, // Skip to: 86948 -/* 8104 */ MCD_OPC_Decode, 162, 19, 27, // Opcode: LSL_WIDE_ZZZ_S -/* 8108 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 8122 -/* 8113 */ MCD_OPC_CheckPredicate, 0, 238, 51, 1, // Skip to: 86948 -/* 8118 */ MCD_OPC_Decode, 151, 2, 60, // Opcode: ASR_ZZI_D -/* 8122 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 8136 -/* 8127 */ MCD_OPC_CheckPredicate, 0, 224, 51, 1, // Skip to: 86948 -/* 8132 */ MCD_OPC_Decode, 196, 19, 60, // Opcode: LSR_ZZI_D -/* 8136 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 8150 -/* 8141 */ MCD_OPC_CheckPredicate, 0, 210, 51, 1, // Skip to: 86948 -/* 8146 */ MCD_OPC_Decode, 172, 19, 61, // Opcode: LSL_ZZI_D -/* 8150 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 8186 -/* 8155 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8158 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8172 -/* 8163 */ MCD_OPC_CheckPredicate, 0, 188, 51, 1, // Skip to: 86948 -/* 8168 */ MCD_OPC_Decode, 210, 1, 27, // Opcode: ADR_LSL_ZZZ_S_0 -/* 8172 */ MCD_OPC_FilterValue, 1, 179, 51, 1, // Skip to: 86948 -/* 8177 */ MCD_OPC_CheckPredicate, 0, 174, 51, 1, // Skip to: 86948 -/* 8182 */ MCD_OPC_Decode, 206, 1, 27, // Opcode: ADR_LSL_ZZZ_D_0 -/* 8186 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 8222 -/* 8191 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8194 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8208 -/* 8199 */ MCD_OPC_CheckPredicate, 0, 152, 51, 1, // Skip to: 86948 -/* 8204 */ MCD_OPC_Decode, 211, 1, 27, // Opcode: ADR_LSL_ZZZ_S_1 -/* 8208 */ MCD_OPC_FilterValue, 1, 143, 51, 1, // Skip to: 86948 -/* 8213 */ MCD_OPC_CheckPredicate, 0, 138, 51, 1, // Skip to: 86948 -/* 8218 */ MCD_OPC_Decode, 207, 1, 27, // Opcode: ADR_LSL_ZZZ_D_1 -/* 8222 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 8258 -/* 8227 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8230 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8244 -/* 8235 */ MCD_OPC_CheckPredicate, 0, 116, 51, 1, // Skip to: 86948 -/* 8240 */ MCD_OPC_Decode, 212, 1, 27, // Opcode: ADR_LSL_ZZZ_S_2 -/* 8244 */ MCD_OPC_FilterValue, 1, 107, 51, 1, // Skip to: 86948 -/* 8249 */ MCD_OPC_CheckPredicate, 0, 102, 51, 1, // Skip to: 86948 -/* 8254 */ MCD_OPC_Decode, 208, 1, 27, // Opcode: ADR_LSL_ZZZ_D_2 -/* 8258 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 8294 -/* 8263 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8266 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8280 -/* 8271 */ MCD_OPC_CheckPredicate, 0, 80, 51, 1, // Skip to: 86948 -/* 8276 */ MCD_OPC_Decode, 213, 1, 27, // Opcode: ADR_LSL_ZZZ_S_3 -/* 8280 */ MCD_OPC_FilterValue, 1, 71, 51, 1, // Skip to: 86948 -/* 8285 */ MCD_OPC_CheckPredicate, 0, 66, 51, 1, // Skip to: 86948 -/* 8290 */ MCD_OPC_Decode, 209, 1, 27, // Opcode: ADR_LSL_ZZZ_D_3 -/* 8294 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 8330 -/* 8299 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8302 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8316 -/* 8307 */ MCD_OPC_CheckPredicate, 0, 44, 51, 1, // Skip to: 86948 -/* 8312 */ MCD_OPC_Decode, 240, 12, 27, // Opcode: FTSSEL_ZZZ_S -/* 8316 */ MCD_OPC_FilterValue, 1, 35, 51, 1, // Skip to: 86948 -/* 8321 */ MCD_OPC_CheckPredicate, 0, 30, 51, 1, // Skip to: 86948 -/* 8326 */ MCD_OPC_Decode, 238, 12, 27, // Opcode: FTSSEL_ZZZ_D -/* 8330 */ MCD_OPC_FilterValue, 14, 21, 51, 1, // Skip to: 86948 -/* 8335 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8338 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8359 -/* 8343 */ MCD_OPC_CheckPredicate, 0, 8, 51, 1, // Skip to: 86948 -/* 8348 */ MCD_OPC_CheckField, 16, 5, 0, 1, 51, 1, // Skip to: 86948 -/* 8355 */ MCD_OPC_Decode, 185, 9, 38, // Opcode: FEXPA_ZZ_S -/* 8359 */ MCD_OPC_FilterValue, 1, 248, 50, 1, // Skip to: 86948 -/* 8364 */ MCD_OPC_CheckPredicate, 0, 243, 50, 1, // Skip to: 86948 -/* 8369 */ MCD_OPC_CheckField, 16, 5, 0, 236, 50, 1, // Skip to: 86948 -/* 8376 */ MCD_OPC_Decode, 183, 9, 38, // Opcode: FEXPA_ZZ_D -/* 8380 */ MCD_OPC_FilterValue, 2, 179, 2, 0, // Skip to: 9076 -/* 8385 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 8388 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 8468 -/* 8393 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 8396 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8432 -/* 8401 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8404 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8418 -/* 8409 */ MCD_OPC_CheckPredicate, 0, 198, 50, 1, // Skip to: 86948 -/* 8414 */ MCD_OPC_Decode, 141, 5, 62, // Opcode: CPY_ZPmV_B -/* 8418 */ MCD_OPC_FilterValue, 1, 189, 50, 1, // Skip to: 86948 -/* 8423 */ MCD_OPC_CheckPredicate, 0, 184, 50, 1, // Skip to: 86948 -/* 8428 */ MCD_OPC_Decode, 143, 5, 63, // Opcode: CPY_ZPmV_H -/* 8432 */ MCD_OPC_FilterValue, 1, 175, 50, 1, // Skip to: 86948 -/* 8437 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8440 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8454 -/* 8445 */ MCD_OPC_CheckPredicate, 0, 162, 50, 1, // Skip to: 86948 -/* 8450 */ MCD_OPC_Decode, 163, 14, 64, // Opcode: LASTA_RPZ_B -/* 8454 */ MCD_OPC_FilterValue, 1, 153, 50, 1, // Skip to: 86948 -/* 8459 */ MCD_OPC_CheckPredicate, 0, 148, 50, 1, // Skip to: 86948 -/* 8464 */ MCD_OPC_Decode, 165, 14, 64, // Opcode: LASTA_RPZ_H -/* 8468 */ MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 8518 -/* 8473 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8476 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8497 -/* 8481 */ MCD_OPC_CheckPredicate, 0, 126, 50, 1, // Skip to: 86948 -/* 8486 */ MCD_OPC_CheckField, 13, 1, 1, 119, 50, 1, // Skip to: 86948 -/* 8493 */ MCD_OPC_Decode, 171, 14, 64, // Opcode: LASTB_RPZ_B -/* 8497 */ MCD_OPC_FilterValue, 1, 110, 50, 1, // Skip to: 86948 -/* 8502 */ MCD_OPC_CheckPredicate, 0, 105, 50, 1, // Skip to: 86948 -/* 8507 */ MCD_OPC_CheckField, 13, 1, 1, 98, 50, 1, // Skip to: 86948 -/* 8514 */ MCD_OPC_Decode, 173, 14, 64, // Opcode: LASTB_RPZ_H -/* 8518 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 8568 -/* 8523 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8526 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8547 -/* 8531 */ MCD_OPC_CheckPredicate, 0, 76, 50, 1, // Skip to: 86948 -/* 8536 */ MCD_OPC_CheckField, 13, 1, 0, 69, 50, 1, // Skip to: 86948 -/* 8543 */ MCD_OPC_Decode, 167, 14, 2, // Opcode: LASTA_VPZ_B -/* 8547 */ MCD_OPC_FilterValue, 1, 60, 50, 1, // Skip to: 86948 -/* 8552 */ MCD_OPC_CheckPredicate, 0, 55, 50, 1, // Skip to: 86948 -/* 8557 */ MCD_OPC_CheckField, 13, 1, 0, 48, 50, 1, // Skip to: 86948 -/* 8564 */ MCD_OPC_Decode, 169, 14, 3, // Opcode: LASTA_VPZ_H -/* 8568 */ MCD_OPC_FilterValue, 3, 45, 0, 0, // Skip to: 8618 -/* 8573 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8576 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8597 -/* 8581 */ MCD_OPC_CheckPredicate, 0, 26, 50, 1, // Skip to: 86948 -/* 8586 */ MCD_OPC_CheckField, 13, 1, 0, 19, 50, 1, // Skip to: 86948 -/* 8593 */ MCD_OPC_Decode, 175, 14, 2, // Opcode: LASTB_VPZ_B -/* 8597 */ MCD_OPC_FilterValue, 1, 10, 50, 1, // Skip to: 86948 -/* 8602 */ MCD_OPC_CheckPredicate, 0, 5, 50, 1, // Skip to: 86948 -/* 8607 */ MCD_OPC_CheckField, 13, 1, 0, 254, 49, 1, // Skip to: 86948 -/* 8614 */ MCD_OPC_Decode, 177, 14, 3, // Opcode: LASTB_VPZ_H -/* 8618 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 8646 -/* 8623 */ MCD_OPC_CheckPredicate, 0, 240, 49, 1, // Skip to: 86948 -/* 8628 */ MCD_OPC_CheckField, 22, 1, 1, 233, 49, 1, // Skip to: 86948 -/* 8635 */ MCD_OPC_CheckField, 13, 1, 0, 226, 49, 1, // Skip to: 86948 -/* 8642 */ MCD_OPC_Decode, 216, 21, 5, // Opcode: REVB_ZPmZ_H -/* 8646 */ MCD_OPC_FilterValue, 7, 45, 0, 0, // Skip to: 8696 -/* 8651 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8654 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8675 -/* 8659 */ MCD_OPC_CheckPredicate, 0, 204, 49, 1, // Skip to: 86948 -/* 8664 */ MCD_OPC_CheckField, 13, 1, 0, 197, 49, 1, // Skip to: 86948 -/* 8671 */ MCD_OPC_Decode, 186, 21, 5, // Opcode: RBIT_ZPmZ_B -/* 8675 */ MCD_OPC_FilterValue, 1, 188, 49, 1, // Skip to: 86948 -/* 8680 */ MCD_OPC_CheckPredicate, 0, 183, 49, 1, // Skip to: 86948 -/* 8685 */ MCD_OPC_CheckField, 13, 1, 0, 176, 49, 1, // Skip to: 86948 -/* 8692 */ MCD_OPC_Decode, 188, 21, 5, // Opcode: RBIT_ZPmZ_H -/* 8696 */ MCD_OPC_FilterValue, 8, 75, 0, 0, // Skip to: 8776 -/* 8701 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 8704 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8740 -/* 8709 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8712 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8726 -/* 8717 */ MCD_OPC_CheckPredicate, 0, 146, 49, 1, // Skip to: 86948 -/* 8722 */ MCD_OPC_Decode, 141, 3, 0, // Opcode: CLASTA_ZPZ_B -/* 8726 */ MCD_OPC_FilterValue, 1, 137, 49, 1, // Skip to: 86948 -/* 8731 */ MCD_OPC_CheckPredicate, 0, 132, 49, 1, // Skip to: 86948 -/* 8736 */ MCD_OPC_Decode, 143, 3, 0, // Opcode: CLASTA_ZPZ_H -/* 8740 */ MCD_OPC_FilterValue, 1, 123, 49, 1, // Skip to: 86948 -/* 8745 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8748 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8762 -/* 8753 */ MCD_OPC_CheckPredicate, 0, 110, 49, 1, // Skip to: 86948 -/* 8758 */ MCD_OPC_Decode, 137, 5, 65, // Opcode: CPY_ZPmR_B -/* 8762 */ MCD_OPC_FilterValue, 1, 101, 49, 1, // Skip to: 86948 -/* 8767 */ MCD_OPC_CheckPredicate, 0, 96, 49, 1, // Skip to: 86948 -/* 8772 */ MCD_OPC_Decode, 139, 5, 65, // Opcode: CPY_ZPmR_H -/* 8776 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 8826 -/* 8781 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8784 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8805 -/* 8789 */ MCD_OPC_CheckPredicate, 0, 74, 49, 1, // Skip to: 86948 -/* 8794 */ MCD_OPC_CheckField, 13, 1, 0, 67, 49, 1, // Skip to: 86948 -/* 8801 */ MCD_OPC_Decode, 153, 3, 0, // Opcode: CLASTB_ZPZ_B -/* 8805 */ MCD_OPC_FilterValue, 1, 58, 49, 1, // Skip to: 86948 -/* 8810 */ MCD_OPC_CheckPredicate, 0, 53, 49, 1, // Skip to: 86948 -/* 8815 */ MCD_OPC_CheckField, 13, 1, 0, 46, 49, 1, // Skip to: 86948 -/* 8822 */ MCD_OPC_Decode, 155, 3, 0, // Opcode: CLASTB_ZPZ_H -/* 8826 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 8876 -/* 8831 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8834 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8855 -/* 8839 */ MCD_OPC_CheckPredicate, 0, 24, 49, 1, // Skip to: 86948 -/* 8844 */ MCD_OPC_CheckField, 13, 1, 0, 17, 49, 1, // Skip to: 86948 -/* 8851 */ MCD_OPC_Decode, 137, 3, 66, // Opcode: CLASTA_VPZ_B -/* 8855 */ MCD_OPC_FilterValue, 1, 8, 49, 1, // Skip to: 86948 -/* 8860 */ MCD_OPC_CheckPredicate, 0, 3, 49, 1, // Skip to: 86948 -/* 8865 */ MCD_OPC_CheckField, 13, 1, 0, 252, 48, 1, // Skip to: 86948 -/* 8872 */ MCD_OPC_Decode, 139, 3, 67, // Opcode: CLASTA_VPZ_H -/* 8876 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 8926 -/* 8881 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8884 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8905 -/* 8889 */ MCD_OPC_CheckPredicate, 0, 230, 48, 1, // Skip to: 86948 -/* 8894 */ MCD_OPC_CheckField, 13, 1, 0, 223, 48, 1, // Skip to: 86948 -/* 8901 */ MCD_OPC_Decode, 149, 3, 66, // Opcode: CLASTB_VPZ_B -/* 8905 */ MCD_OPC_FilterValue, 1, 214, 48, 1, // Skip to: 86948 -/* 8910 */ MCD_OPC_CheckPredicate, 0, 209, 48, 1, // Skip to: 86948 -/* 8915 */ MCD_OPC_CheckField, 13, 1, 0, 202, 48, 1, // Skip to: 86948 -/* 8922 */ MCD_OPC_Decode, 151, 3, 67, // Opcode: CLASTB_VPZ_H -/* 8926 */ MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 8976 -/* 8931 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8934 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8955 -/* 8939 */ MCD_OPC_CheckPredicate, 0, 180, 48, 1, // Skip to: 86948 -/* 8944 */ MCD_OPC_CheckField, 13, 1, 0, 173, 48, 1, // Skip to: 86948 -/* 8951 */ MCD_OPC_Decode, 149, 24, 0, // Opcode: SPLICE_ZPZ_B -/* 8955 */ MCD_OPC_FilterValue, 1, 164, 48, 1, // Skip to: 86948 -/* 8960 */ MCD_OPC_CheckPredicate, 0, 159, 48, 1, // Skip to: 86948 -/* 8965 */ MCD_OPC_CheckField, 13, 1, 0, 152, 48, 1, // Skip to: 86948 -/* 8972 */ MCD_OPC_Decode, 151, 24, 0, // Opcode: SPLICE_ZPZ_H -/* 8976 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 9026 -/* 8981 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 8984 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9005 -/* 8989 */ MCD_OPC_CheckPredicate, 0, 130, 48, 1, // Skip to: 86948 -/* 8994 */ MCD_OPC_CheckField, 13, 1, 1, 123, 48, 1, // Skip to: 86948 -/* 9001 */ MCD_OPC_Decode, 133, 3, 68, // Opcode: CLASTA_RPZ_B -/* 9005 */ MCD_OPC_FilterValue, 1, 114, 48, 1, // Skip to: 86948 -/* 9010 */ MCD_OPC_CheckPredicate, 0, 109, 48, 1, // Skip to: 86948 -/* 9015 */ MCD_OPC_CheckField, 13, 1, 1, 102, 48, 1, // Skip to: 86948 -/* 9022 */ MCD_OPC_Decode, 135, 3, 68, // Opcode: CLASTA_RPZ_H -/* 9026 */ MCD_OPC_FilterValue, 17, 93, 48, 1, // Skip to: 86948 -/* 9031 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9034 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9055 -/* 9039 */ MCD_OPC_CheckPredicate, 0, 80, 48, 1, // Skip to: 86948 -/* 9044 */ MCD_OPC_CheckField, 13, 1, 1, 73, 48, 1, // Skip to: 86948 -/* 9051 */ MCD_OPC_Decode, 145, 3, 68, // Opcode: CLASTB_RPZ_B -/* 9055 */ MCD_OPC_FilterValue, 1, 64, 48, 1, // Skip to: 86948 -/* 9060 */ MCD_OPC_CheckPredicate, 0, 59, 48, 1, // Skip to: 86948 -/* 9065 */ MCD_OPC_CheckField, 13, 1, 1, 52, 48, 1, // Skip to: 86948 -/* 9072 */ MCD_OPC_Decode, 147, 3, 68, // Opcode: CLASTB_RPZ_H -/* 9076 */ MCD_OPC_FilterValue, 3, 43, 48, 1, // Skip to: 86948 -/* 9081 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 9084 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 9164 -/* 9089 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 9092 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9128 -/* 9097 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9100 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9114 -/* 9105 */ MCD_OPC_CheckPredicate, 0, 14, 48, 1, // Skip to: 86948 -/* 9110 */ MCD_OPC_Decode, 144, 5, 69, // Opcode: CPY_ZPmV_S -/* 9114 */ MCD_OPC_FilterValue, 1, 5, 48, 1, // Skip to: 86948 -/* 9119 */ MCD_OPC_CheckPredicate, 0, 0, 48, 1, // Skip to: 86948 -/* 9124 */ MCD_OPC_Decode, 142, 5, 70, // Opcode: CPY_ZPmV_D -/* 9128 */ MCD_OPC_FilterValue, 1, 247, 47, 1, // Skip to: 86948 -/* 9133 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9136 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9150 -/* 9141 */ MCD_OPC_CheckPredicate, 0, 234, 47, 1, // Skip to: 86948 -/* 9146 */ MCD_OPC_Decode, 166, 14, 64, // Opcode: LASTA_RPZ_S -/* 9150 */ MCD_OPC_FilterValue, 1, 225, 47, 1, // Skip to: 86948 -/* 9155 */ MCD_OPC_CheckPredicate, 0, 220, 47, 1, // Skip to: 86948 -/* 9160 */ MCD_OPC_Decode, 164, 14, 71, // Opcode: LASTA_RPZ_D -/* 9164 */ MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 9244 -/* 9169 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 9172 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9208 -/* 9177 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9180 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9194 -/* 9185 */ MCD_OPC_CheckPredicate, 0, 190, 47, 1, // Skip to: 86948 -/* 9190 */ MCD_OPC_Decode, 132, 5, 4, // Opcode: COMPACT_ZPZ_S -/* 9194 */ MCD_OPC_FilterValue, 1, 181, 47, 1, // Skip to: 86948 -/* 9199 */ MCD_OPC_CheckPredicate, 0, 176, 47, 1, // Skip to: 86948 -/* 9204 */ MCD_OPC_Decode, 131, 5, 4, // Opcode: COMPACT_ZPZ_D -/* 9208 */ MCD_OPC_FilterValue, 1, 167, 47, 1, // Skip to: 86948 -/* 9213 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9216 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9230 -/* 9221 */ MCD_OPC_CheckPredicate, 0, 154, 47, 1, // Skip to: 86948 -/* 9226 */ MCD_OPC_Decode, 174, 14, 64, // Opcode: LASTB_RPZ_S -/* 9230 */ MCD_OPC_FilterValue, 1, 145, 47, 1, // Skip to: 86948 -/* 9235 */ MCD_OPC_CheckPredicate, 0, 140, 47, 1, // Skip to: 86948 -/* 9240 */ MCD_OPC_Decode, 172, 14, 71, // Opcode: LASTB_RPZ_D -/* 9244 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 9294 -/* 9249 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9252 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9273 -/* 9257 */ MCD_OPC_CheckPredicate, 0, 118, 47, 1, // Skip to: 86948 -/* 9262 */ MCD_OPC_CheckField, 13, 1, 0, 111, 47, 1, // Skip to: 86948 -/* 9269 */ MCD_OPC_Decode, 170, 14, 14, // Opcode: LASTA_VPZ_S -/* 9273 */ MCD_OPC_FilterValue, 1, 102, 47, 1, // Skip to: 86948 -/* 9278 */ MCD_OPC_CheckPredicate, 0, 97, 47, 1, // Skip to: 86948 -/* 9283 */ MCD_OPC_CheckField, 13, 1, 0, 90, 47, 1, // Skip to: 86948 -/* 9290 */ MCD_OPC_Decode, 168, 14, 1, // Opcode: LASTA_VPZ_D -/* 9294 */ MCD_OPC_FilterValue, 3, 45, 0, 0, // Skip to: 9344 -/* 9299 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9302 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9323 -/* 9307 */ MCD_OPC_CheckPredicate, 0, 68, 47, 1, // Skip to: 86948 -/* 9312 */ MCD_OPC_CheckField, 13, 1, 0, 61, 47, 1, // Skip to: 86948 -/* 9319 */ MCD_OPC_Decode, 178, 14, 14, // Opcode: LASTB_VPZ_S -/* 9323 */ MCD_OPC_FilterValue, 1, 52, 47, 1, // Skip to: 86948 -/* 9328 */ MCD_OPC_CheckPredicate, 0, 47, 47, 1, // Skip to: 86948 -/* 9333 */ MCD_OPC_CheckField, 13, 1, 0, 40, 47, 1, // Skip to: 86948 -/* 9340 */ MCD_OPC_Decode, 176, 14, 1, // Opcode: LASTB_VPZ_D -/* 9344 */ MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 9394 -/* 9349 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9352 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9373 -/* 9357 */ MCD_OPC_CheckPredicate, 0, 18, 47, 1, // Skip to: 86948 -/* 9362 */ MCD_OPC_CheckField, 13, 1, 0, 11, 47, 1, // Skip to: 86948 -/* 9369 */ MCD_OPC_Decode, 217, 21, 5, // Opcode: REVB_ZPmZ_S -/* 9373 */ MCD_OPC_FilterValue, 1, 2, 47, 1, // Skip to: 86948 -/* 9378 */ MCD_OPC_CheckPredicate, 0, 253, 46, 1, // Skip to: 86948 -/* 9383 */ MCD_OPC_CheckField, 13, 1, 0, 246, 46, 1, // Skip to: 86948 -/* 9390 */ MCD_OPC_Decode, 215, 21, 5, // Opcode: REVB_ZPmZ_D -/* 9394 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 9444 -/* 9399 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9402 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9423 -/* 9407 */ MCD_OPC_CheckPredicate, 0, 224, 46, 1, // Skip to: 86948 -/* 9412 */ MCD_OPC_CheckField, 13, 1, 0, 217, 46, 1, // Skip to: 86948 -/* 9419 */ MCD_OPC_Decode, 219, 21, 5, // Opcode: REVH_ZPmZ_S -/* 9423 */ MCD_OPC_FilterValue, 1, 208, 46, 1, // Skip to: 86948 -/* 9428 */ MCD_OPC_CheckPredicate, 0, 203, 46, 1, // Skip to: 86948 -/* 9433 */ MCD_OPC_CheckField, 13, 1, 0, 196, 46, 1, // Skip to: 86948 -/* 9440 */ MCD_OPC_Decode, 218, 21, 5, // Opcode: REVH_ZPmZ_D -/* 9444 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 9472 -/* 9449 */ MCD_OPC_CheckPredicate, 0, 182, 46, 1, // Skip to: 86948 -/* 9454 */ MCD_OPC_CheckField, 22, 1, 1, 175, 46, 1, // Skip to: 86948 -/* 9461 */ MCD_OPC_CheckField, 13, 1, 0, 168, 46, 1, // Skip to: 86948 -/* 9468 */ MCD_OPC_Decode, 220, 21, 5, // Opcode: REVW_ZPmZ_D -/* 9472 */ MCD_OPC_FilterValue, 7, 45, 0, 0, // Skip to: 9522 -/* 9477 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9480 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9501 -/* 9485 */ MCD_OPC_CheckPredicate, 0, 146, 46, 1, // Skip to: 86948 -/* 9490 */ MCD_OPC_CheckField, 13, 1, 0, 139, 46, 1, // Skip to: 86948 -/* 9497 */ MCD_OPC_Decode, 189, 21, 5, // Opcode: RBIT_ZPmZ_S -/* 9501 */ MCD_OPC_FilterValue, 1, 130, 46, 1, // Skip to: 86948 -/* 9506 */ MCD_OPC_CheckPredicate, 0, 125, 46, 1, // Skip to: 86948 -/* 9511 */ MCD_OPC_CheckField, 13, 1, 0, 118, 46, 1, // Skip to: 86948 -/* 9518 */ MCD_OPC_Decode, 187, 21, 5, // Opcode: RBIT_ZPmZ_D -/* 9522 */ MCD_OPC_FilterValue, 8, 75, 0, 0, // Skip to: 9602 -/* 9527 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 9530 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9566 -/* 9535 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9538 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9552 -/* 9543 */ MCD_OPC_CheckPredicate, 0, 88, 46, 1, // Skip to: 86948 -/* 9548 */ MCD_OPC_Decode, 144, 3, 0, // Opcode: CLASTA_ZPZ_S -/* 9552 */ MCD_OPC_FilterValue, 1, 79, 46, 1, // Skip to: 86948 -/* 9557 */ MCD_OPC_CheckPredicate, 0, 74, 46, 1, // Skip to: 86948 -/* 9562 */ MCD_OPC_Decode, 142, 3, 0, // Opcode: CLASTA_ZPZ_D -/* 9566 */ MCD_OPC_FilterValue, 1, 65, 46, 1, // Skip to: 86948 -/* 9571 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9574 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9588 -/* 9579 */ MCD_OPC_CheckPredicate, 0, 52, 46, 1, // Skip to: 86948 -/* 9584 */ MCD_OPC_Decode, 140, 5, 65, // Opcode: CPY_ZPmR_S -/* 9588 */ MCD_OPC_FilterValue, 1, 43, 46, 1, // Skip to: 86948 -/* 9593 */ MCD_OPC_CheckPredicate, 0, 38, 46, 1, // Skip to: 86948 -/* 9598 */ MCD_OPC_Decode, 138, 5, 72, // Opcode: CPY_ZPmR_D -/* 9602 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 9652 -/* 9607 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9610 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9631 -/* 9615 */ MCD_OPC_CheckPredicate, 0, 16, 46, 1, // Skip to: 86948 -/* 9620 */ MCD_OPC_CheckField, 13, 1, 0, 9, 46, 1, // Skip to: 86948 -/* 9627 */ MCD_OPC_Decode, 156, 3, 0, // Opcode: CLASTB_ZPZ_S -/* 9631 */ MCD_OPC_FilterValue, 1, 0, 46, 1, // Skip to: 86948 -/* 9636 */ MCD_OPC_CheckPredicate, 0, 251, 45, 1, // Skip to: 86948 -/* 9641 */ MCD_OPC_CheckField, 13, 1, 0, 244, 45, 1, // Skip to: 86948 -/* 9648 */ MCD_OPC_Decode, 154, 3, 0, // Opcode: CLASTB_ZPZ_D -/* 9652 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 9702 -/* 9657 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9660 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9681 -/* 9665 */ MCD_OPC_CheckPredicate, 0, 222, 45, 1, // Skip to: 86948 -/* 9670 */ MCD_OPC_CheckField, 13, 1, 0, 215, 45, 1, // Skip to: 86948 -/* 9677 */ MCD_OPC_Decode, 140, 3, 73, // Opcode: CLASTA_VPZ_S -/* 9681 */ MCD_OPC_FilterValue, 1, 206, 45, 1, // Skip to: 86948 -/* 9686 */ MCD_OPC_CheckPredicate, 0, 201, 45, 1, // Skip to: 86948 -/* 9691 */ MCD_OPC_CheckField, 13, 1, 0, 194, 45, 1, // Skip to: 86948 -/* 9698 */ MCD_OPC_Decode, 138, 3, 74, // Opcode: CLASTA_VPZ_D -/* 9702 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 9752 -/* 9707 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9710 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9731 -/* 9715 */ MCD_OPC_CheckPredicate, 0, 172, 45, 1, // Skip to: 86948 -/* 9720 */ MCD_OPC_CheckField, 13, 1, 0, 165, 45, 1, // Skip to: 86948 -/* 9727 */ MCD_OPC_Decode, 152, 3, 73, // Opcode: CLASTB_VPZ_S -/* 9731 */ MCD_OPC_FilterValue, 1, 156, 45, 1, // Skip to: 86948 -/* 9736 */ MCD_OPC_CheckPredicate, 0, 151, 45, 1, // Skip to: 86948 -/* 9741 */ MCD_OPC_CheckField, 13, 1, 0, 144, 45, 1, // Skip to: 86948 -/* 9748 */ MCD_OPC_Decode, 150, 3, 74, // Opcode: CLASTB_VPZ_D -/* 9752 */ MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 9802 -/* 9757 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9760 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9781 -/* 9765 */ MCD_OPC_CheckPredicate, 0, 122, 45, 1, // Skip to: 86948 -/* 9770 */ MCD_OPC_CheckField, 13, 1, 0, 115, 45, 1, // Skip to: 86948 -/* 9777 */ MCD_OPC_Decode, 152, 24, 0, // Opcode: SPLICE_ZPZ_S -/* 9781 */ MCD_OPC_FilterValue, 1, 106, 45, 1, // Skip to: 86948 -/* 9786 */ MCD_OPC_CheckPredicate, 0, 101, 45, 1, // Skip to: 86948 -/* 9791 */ MCD_OPC_CheckField, 13, 1, 0, 94, 45, 1, // Skip to: 86948 -/* 9798 */ MCD_OPC_Decode, 150, 24, 0, // Opcode: SPLICE_ZPZ_D -/* 9802 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 9852 -/* 9807 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9810 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9831 -/* 9815 */ MCD_OPC_CheckPredicate, 0, 72, 45, 1, // Skip to: 86948 -/* 9820 */ MCD_OPC_CheckField, 13, 1, 1, 65, 45, 1, // Skip to: 86948 -/* 9827 */ MCD_OPC_Decode, 136, 3, 68, // Opcode: CLASTA_RPZ_S -/* 9831 */ MCD_OPC_FilterValue, 1, 56, 45, 1, // Skip to: 86948 -/* 9836 */ MCD_OPC_CheckPredicate, 0, 51, 45, 1, // Skip to: 86948 -/* 9841 */ MCD_OPC_CheckField, 13, 1, 1, 44, 45, 1, // Skip to: 86948 -/* 9848 */ MCD_OPC_Decode, 134, 3, 75, // Opcode: CLASTA_RPZ_D -/* 9852 */ MCD_OPC_FilterValue, 17, 35, 45, 1, // Skip to: 86948 -/* 9857 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 9860 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9881 -/* 9865 */ MCD_OPC_CheckPredicate, 0, 22, 45, 1, // Skip to: 86948 -/* 9870 */ MCD_OPC_CheckField, 13, 1, 1, 15, 45, 1, // Skip to: 86948 -/* 9877 */ MCD_OPC_Decode, 148, 3, 68, // Opcode: CLASTB_RPZ_S -/* 9881 */ MCD_OPC_FilterValue, 1, 6, 45, 1, // Skip to: 86948 -/* 9886 */ MCD_OPC_CheckPredicate, 0, 1, 45, 1, // Skip to: 86948 -/* 9891 */ MCD_OPC_CheckField, 13, 1, 1, 250, 44, 1, // Skip to: 86948 -/* 9898 */ MCD_OPC_Decode, 146, 3, 75, // Opcode: CLASTB_RPZ_D -/* 9902 */ MCD_OPC_FilterValue, 3, 241, 44, 1, // Skip to: 86948 -/* 9907 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 9910 */ MCD_OPC_FilterValue, 0, 204, 0, 0, // Skip to: 10119 -/* 9915 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 9918 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 9954 -/* 9923 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 9926 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9940 -/* 9931 */ MCD_OPC_CheckPredicate, 0, 212, 44, 1, // Skip to: 86948 -/* 9936 */ MCD_OPC_Decode, 245, 4, 76, // Opcode: CNTB_XPiI -/* 9940 */ MCD_OPC_FilterValue, 1, 203, 44, 1, // Skip to: 86948 -/* 9945 */ MCD_OPC_CheckPredicate, 0, 198, 44, 1, // Skip to: 86948 -/* 9950 */ MCD_OPC_Decode, 244, 13, 77, // Opcode: INCB_XPiI -/* 9954 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 9975 -/* 9959 */ MCD_OPC_CheckPredicate, 0, 184, 44, 1, // Skip to: 86948 -/* 9964 */ MCD_OPC_CheckField, 20, 1, 1, 177, 44, 1, // Skip to: 86948 -/* 9971 */ MCD_OPC_Decode, 177, 5, 77, // Opcode: DECB_XPiI -/* 9975 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10011 -/* 9980 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 9983 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9997 -/* 9988 */ MCD_OPC_CheckPredicate, 0, 155, 44, 1, // Skip to: 86948 -/* 9993 */ MCD_OPC_Decode, 254, 24, 77, // Opcode: SQINCB_XPiWdI -/* 9997 */ MCD_OPC_FilterValue, 1, 146, 44, 1, // Skip to: 86948 -/* 10002 */ MCD_OPC_CheckPredicate, 0, 141, 44, 1, // Skip to: 86948 -/* 10007 */ MCD_OPC_Decode, 253, 24, 77, // Opcode: SQINCB_XPiI -/* 10011 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 10047 -/* 10016 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10019 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10033 -/* 10024 */ MCD_OPC_CheckPredicate, 0, 119, 44, 1, // Skip to: 86948 -/* 10029 */ MCD_OPC_Decode, 244, 32, 78, // Opcode: UQINCB_WPiI -/* 10033 */ MCD_OPC_FilterValue, 1, 110, 44, 1, // Skip to: 86948 -/* 10038 */ MCD_OPC_CheckPredicate, 0, 105, 44, 1, // Skip to: 86948 -/* 10043 */ MCD_OPC_Decode, 245, 32, 77, // Opcode: UQINCB_XPiI -/* 10047 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 10083 -/* 10052 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10055 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10069 -/* 10060 */ MCD_OPC_CheckPredicate, 0, 83, 44, 1, // Skip to: 86948 -/* 10065 */ MCD_OPC_Decode, 184, 24, 77, // Opcode: SQDECB_XPiWdI -/* 10069 */ MCD_OPC_FilterValue, 1, 74, 44, 1, // Skip to: 86948 -/* 10074 */ MCD_OPC_CheckPredicate, 0, 69, 44, 1, // Skip to: 86948 -/* 10079 */ MCD_OPC_Decode, 183, 24, 77, // Opcode: SQDECB_XPiI -/* 10083 */ MCD_OPC_FilterValue, 15, 60, 44, 1, // Skip to: 86948 -/* 10088 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10091 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10105 -/* 10096 */ MCD_OPC_CheckPredicate, 0, 47, 44, 1, // Skip to: 86948 -/* 10101 */ MCD_OPC_Decode, 222, 32, 78, // Opcode: UQDECB_WPiI -/* 10105 */ MCD_OPC_FilterValue, 1, 38, 44, 1, // Skip to: 86948 -/* 10110 */ MCD_OPC_CheckPredicate, 0, 33, 44, 1, // Skip to: 86948 -/* 10115 */ MCD_OPC_Decode, 223, 32, 77, // Opcode: UQDECB_XPiI -/* 10119 */ MCD_OPC_FilterValue, 1, 62, 1, 0, // Skip to: 10442 -/* 10124 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 10127 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 10163 -/* 10132 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10135 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10149 -/* 10140 */ MCD_OPC_CheckPredicate, 0, 3, 44, 1, // Skip to: 86948 -/* 10145 */ MCD_OPC_Decode, 132, 25, 79, // Opcode: SQINCH_ZPiI -/* 10149 */ MCD_OPC_FilterValue, 1, 250, 43, 1, // Skip to: 86948 -/* 10154 */ MCD_OPC_CheckPredicate, 0, 245, 43, 1, // Skip to: 86948 -/* 10159 */ MCD_OPC_Decode, 248, 13, 79, // Opcode: INCH_ZPiI -/* 10163 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 10199 -/* 10168 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10171 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10185 -/* 10176 */ MCD_OPC_CheckPredicate, 0, 223, 43, 1, // Skip to: 86948 -/* 10181 */ MCD_OPC_Decode, 251, 32, 79, // Opcode: UQINCH_ZPiI -/* 10185 */ MCD_OPC_FilterValue, 1, 214, 43, 1, // Skip to: 86948 -/* 10190 */ MCD_OPC_CheckPredicate, 0, 209, 43, 1, // Skip to: 86948 -/* 10195 */ MCD_OPC_Decode, 181, 5, 79, // Opcode: DECH_ZPiI -/* 10199 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10220 -/* 10204 */ MCD_OPC_CheckPredicate, 0, 195, 43, 1, // Skip to: 86948 -/* 10209 */ MCD_OPC_CheckField, 20, 1, 0, 188, 43, 1, // Skip to: 86948 -/* 10216 */ MCD_OPC_Decode, 190, 24, 79, // Opcode: SQDECH_ZPiI -/* 10220 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10241 -/* 10225 */ MCD_OPC_CheckPredicate, 0, 174, 43, 1, // Skip to: 86948 -/* 10230 */ MCD_OPC_CheckField, 20, 1, 0, 167, 43, 1, // Skip to: 86948 -/* 10237 */ MCD_OPC_Decode, 229, 32, 79, // Opcode: UQDECH_ZPiI -/* 10241 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 10277 -/* 10246 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10249 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10263 -/* 10254 */ MCD_OPC_CheckPredicate, 0, 145, 43, 1, // Skip to: 86948 -/* 10259 */ MCD_OPC_Decode, 247, 4, 76, // Opcode: CNTH_XPiI -/* 10263 */ MCD_OPC_FilterValue, 1, 136, 43, 1, // Skip to: 86948 -/* 10268 */ MCD_OPC_CheckPredicate, 0, 131, 43, 1, // Skip to: 86948 -/* 10273 */ MCD_OPC_Decode, 247, 13, 77, // Opcode: INCH_XPiI -/* 10277 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 10298 -/* 10282 */ MCD_OPC_CheckPredicate, 0, 117, 43, 1, // Skip to: 86948 -/* 10287 */ MCD_OPC_CheckField, 20, 1, 1, 110, 43, 1, // Skip to: 86948 -/* 10294 */ MCD_OPC_Decode, 180, 5, 77, // Opcode: DECH_XPiI -/* 10298 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10334 -/* 10303 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10306 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10320 -/* 10311 */ MCD_OPC_CheckPredicate, 0, 88, 43, 1, // Skip to: 86948 -/* 10316 */ MCD_OPC_Decode, 131, 25, 77, // Opcode: SQINCH_XPiWdI -/* 10320 */ MCD_OPC_FilterValue, 1, 79, 43, 1, // Skip to: 86948 -/* 10325 */ MCD_OPC_CheckPredicate, 0, 74, 43, 1, // Skip to: 86948 -/* 10330 */ MCD_OPC_Decode, 130, 25, 77, // Opcode: SQINCH_XPiI -/* 10334 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 10370 -/* 10339 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10342 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10356 -/* 10347 */ MCD_OPC_CheckPredicate, 0, 52, 43, 1, // Skip to: 86948 -/* 10352 */ MCD_OPC_Decode, 249, 32, 78, // Opcode: UQINCH_WPiI -/* 10356 */ MCD_OPC_FilterValue, 1, 43, 43, 1, // Skip to: 86948 -/* 10361 */ MCD_OPC_CheckPredicate, 0, 38, 43, 1, // Skip to: 86948 -/* 10366 */ MCD_OPC_Decode, 250, 32, 77, // Opcode: UQINCH_XPiI -/* 10370 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 10406 -/* 10375 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10378 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10392 -/* 10383 */ MCD_OPC_CheckPredicate, 0, 16, 43, 1, // Skip to: 86948 -/* 10388 */ MCD_OPC_Decode, 189, 24, 77, // Opcode: SQDECH_XPiWdI -/* 10392 */ MCD_OPC_FilterValue, 1, 7, 43, 1, // Skip to: 86948 -/* 10397 */ MCD_OPC_CheckPredicate, 0, 2, 43, 1, // Skip to: 86948 -/* 10402 */ MCD_OPC_Decode, 188, 24, 77, // Opcode: SQDECH_XPiI -/* 10406 */ MCD_OPC_FilterValue, 15, 249, 42, 1, // Skip to: 86948 -/* 10411 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10414 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10428 -/* 10419 */ MCD_OPC_CheckPredicate, 0, 236, 42, 1, // Skip to: 86948 -/* 10424 */ MCD_OPC_Decode, 227, 32, 78, // Opcode: UQDECH_WPiI -/* 10428 */ MCD_OPC_FilterValue, 1, 227, 42, 1, // Skip to: 86948 -/* 10433 */ MCD_OPC_CheckPredicate, 0, 222, 42, 1, // Skip to: 86948 -/* 10438 */ MCD_OPC_Decode, 228, 32, 77, // Opcode: UQDECH_XPiI -/* 10442 */ MCD_OPC_FilterValue, 2, 62, 1, 0, // Skip to: 10765 -/* 10447 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 10450 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 10486 -/* 10455 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10458 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10472 -/* 10463 */ MCD_OPC_CheckPredicate, 0, 192, 42, 1, // Skip to: 86948 -/* 10468 */ MCD_OPC_Decode, 146, 25, 79, // Opcode: SQINCW_ZPiI -/* 10472 */ MCD_OPC_FilterValue, 1, 183, 42, 1, // Skip to: 86948 -/* 10477 */ MCD_OPC_CheckPredicate, 0, 178, 42, 1, // Skip to: 86948 -/* 10482 */ MCD_OPC_Decode, 129, 14, 79, // Opcode: INCW_ZPiI -/* 10486 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 10522 -/* 10491 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10494 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10508 -/* 10499 */ MCD_OPC_CheckPredicate, 0, 156, 42, 1, // Skip to: 86948 -/* 10504 */ MCD_OPC_Decode, 137, 33, 79, // Opcode: UQINCW_ZPiI -/* 10508 */ MCD_OPC_FilterValue, 1, 147, 42, 1, // Skip to: 86948 -/* 10513 */ MCD_OPC_CheckPredicate, 0, 142, 42, 1, // Skip to: 86948 -/* 10518 */ MCD_OPC_Decode, 190, 5, 79, // Opcode: DECW_ZPiI -/* 10522 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10543 -/* 10527 */ MCD_OPC_CheckPredicate, 0, 128, 42, 1, // Skip to: 86948 -/* 10532 */ MCD_OPC_CheckField, 20, 1, 0, 121, 42, 1, // Skip to: 86948 -/* 10539 */ MCD_OPC_Decode, 204, 24, 79, // Opcode: SQDECW_ZPiI -/* 10543 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10564 -/* 10548 */ MCD_OPC_CheckPredicate, 0, 107, 42, 1, // Skip to: 86948 -/* 10553 */ MCD_OPC_CheckField, 20, 1, 0, 100, 42, 1, // Skip to: 86948 -/* 10560 */ MCD_OPC_Decode, 243, 32, 79, // Opcode: UQDECW_ZPiI -/* 10564 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 10600 -/* 10569 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10572 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10586 -/* 10577 */ MCD_OPC_CheckPredicate, 0, 78, 42, 1, // Skip to: 86948 -/* 10582 */ MCD_OPC_Decode, 252, 4, 76, // Opcode: CNTW_XPiI -/* 10586 */ MCD_OPC_FilterValue, 1, 69, 42, 1, // Skip to: 86948 -/* 10591 */ MCD_OPC_CheckPredicate, 0, 64, 42, 1, // Skip to: 86948 -/* 10596 */ MCD_OPC_Decode, 128, 14, 77, // Opcode: INCW_XPiI -/* 10600 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 10621 -/* 10605 */ MCD_OPC_CheckPredicate, 0, 50, 42, 1, // Skip to: 86948 -/* 10610 */ MCD_OPC_CheckField, 20, 1, 1, 43, 42, 1, // Skip to: 86948 -/* 10617 */ MCD_OPC_Decode, 189, 5, 77, // Opcode: DECW_XPiI -/* 10621 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10657 -/* 10626 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10629 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10643 -/* 10634 */ MCD_OPC_CheckPredicate, 0, 21, 42, 1, // Skip to: 86948 -/* 10639 */ MCD_OPC_Decode, 145, 25, 77, // Opcode: SQINCW_XPiWdI -/* 10643 */ MCD_OPC_FilterValue, 1, 12, 42, 1, // Skip to: 86948 -/* 10648 */ MCD_OPC_CheckPredicate, 0, 7, 42, 1, // Skip to: 86948 -/* 10653 */ MCD_OPC_Decode, 144, 25, 77, // Opcode: SQINCW_XPiI -/* 10657 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 10693 -/* 10662 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10665 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10679 -/* 10670 */ MCD_OPC_CheckPredicate, 0, 241, 41, 1, // Skip to: 86948 -/* 10675 */ MCD_OPC_Decode, 135, 33, 78, // Opcode: UQINCW_WPiI -/* 10679 */ MCD_OPC_FilterValue, 1, 232, 41, 1, // Skip to: 86948 -/* 10684 */ MCD_OPC_CheckPredicate, 0, 227, 41, 1, // Skip to: 86948 -/* 10689 */ MCD_OPC_Decode, 136, 33, 77, // Opcode: UQINCW_XPiI -/* 10693 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 10729 -/* 10698 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10701 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10715 -/* 10706 */ MCD_OPC_CheckPredicate, 0, 205, 41, 1, // Skip to: 86948 -/* 10711 */ MCD_OPC_Decode, 203, 24, 77, // Opcode: SQDECW_XPiWdI -/* 10715 */ MCD_OPC_FilterValue, 1, 196, 41, 1, // Skip to: 86948 -/* 10720 */ MCD_OPC_CheckPredicate, 0, 191, 41, 1, // Skip to: 86948 -/* 10725 */ MCD_OPC_Decode, 202, 24, 77, // Opcode: SQDECW_XPiI -/* 10729 */ MCD_OPC_FilterValue, 15, 182, 41, 1, // Skip to: 86948 -/* 10734 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10737 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10751 -/* 10742 */ MCD_OPC_CheckPredicate, 0, 169, 41, 1, // Skip to: 86948 -/* 10747 */ MCD_OPC_Decode, 241, 32, 78, // Opcode: UQDECW_WPiI -/* 10751 */ MCD_OPC_FilterValue, 1, 160, 41, 1, // Skip to: 86948 -/* 10756 */ MCD_OPC_CheckPredicate, 0, 155, 41, 1, // Skip to: 86948 -/* 10761 */ MCD_OPC_Decode, 242, 32, 77, // Opcode: UQDECW_XPiI -/* 10765 */ MCD_OPC_FilterValue, 3, 62, 1, 0, // Skip to: 11088 -/* 10770 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 10773 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 10809 -/* 10778 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10781 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10795 -/* 10786 */ MCD_OPC_CheckPredicate, 0, 125, 41, 1, // Skip to: 86948 -/* 10791 */ MCD_OPC_Decode, 129, 25, 79, // Opcode: SQINCD_ZPiI -/* 10795 */ MCD_OPC_FilterValue, 1, 116, 41, 1, // Skip to: 86948 -/* 10800 */ MCD_OPC_CheckPredicate, 0, 111, 41, 1, // Skip to: 86948 -/* 10805 */ MCD_OPC_Decode, 246, 13, 79, // Opcode: INCD_ZPiI -/* 10809 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 10845 -/* 10814 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10817 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10831 -/* 10822 */ MCD_OPC_CheckPredicate, 0, 89, 41, 1, // Skip to: 86948 -/* 10827 */ MCD_OPC_Decode, 248, 32, 79, // Opcode: UQINCD_ZPiI -/* 10831 */ MCD_OPC_FilterValue, 1, 80, 41, 1, // Skip to: 86948 -/* 10836 */ MCD_OPC_CheckPredicate, 0, 75, 41, 1, // Skip to: 86948 -/* 10841 */ MCD_OPC_Decode, 179, 5, 79, // Opcode: DECD_ZPiI -/* 10845 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10866 -/* 10850 */ MCD_OPC_CheckPredicate, 0, 61, 41, 1, // Skip to: 86948 -/* 10855 */ MCD_OPC_CheckField, 20, 1, 0, 54, 41, 1, // Skip to: 86948 -/* 10862 */ MCD_OPC_Decode, 187, 24, 79, // Opcode: SQDECD_ZPiI -/* 10866 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10887 -/* 10871 */ MCD_OPC_CheckPredicate, 0, 40, 41, 1, // Skip to: 86948 -/* 10876 */ MCD_OPC_CheckField, 20, 1, 0, 33, 41, 1, // Skip to: 86948 -/* 10883 */ MCD_OPC_Decode, 226, 32, 79, // Opcode: UQDECD_ZPiI -/* 10887 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 10923 -/* 10892 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10895 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10909 -/* 10900 */ MCD_OPC_CheckPredicate, 0, 11, 41, 1, // Skip to: 86948 -/* 10905 */ MCD_OPC_Decode, 246, 4, 76, // Opcode: CNTD_XPiI -/* 10909 */ MCD_OPC_FilterValue, 1, 2, 41, 1, // Skip to: 86948 -/* 10914 */ MCD_OPC_CheckPredicate, 0, 253, 40, 1, // Skip to: 86948 -/* 10919 */ MCD_OPC_Decode, 245, 13, 77, // Opcode: INCD_XPiI -/* 10923 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 10944 -/* 10928 */ MCD_OPC_CheckPredicate, 0, 239, 40, 1, // Skip to: 86948 -/* 10933 */ MCD_OPC_CheckField, 20, 1, 1, 232, 40, 1, // Skip to: 86948 -/* 10940 */ MCD_OPC_Decode, 178, 5, 77, // Opcode: DECD_XPiI -/* 10944 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10980 -/* 10949 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10952 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10966 -/* 10957 */ MCD_OPC_CheckPredicate, 0, 210, 40, 1, // Skip to: 86948 -/* 10962 */ MCD_OPC_Decode, 128, 25, 77, // Opcode: SQINCD_XPiWdI -/* 10966 */ MCD_OPC_FilterValue, 1, 201, 40, 1, // Skip to: 86948 -/* 10971 */ MCD_OPC_CheckPredicate, 0, 196, 40, 1, // Skip to: 86948 -/* 10976 */ MCD_OPC_Decode, 255, 24, 77, // Opcode: SQINCD_XPiI -/* 10980 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 11016 -/* 10985 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 10988 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11002 -/* 10993 */ MCD_OPC_CheckPredicate, 0, 174, 40, 1, // Skip to: 86948 -/* 10998 */ MCD_OPC_Decode, 246, 32, 78, // Opcode: UQINCD_WPiI -/* 11002 */ MCD_OPC_FilterValue, 1, 165, 40, 1, // Skip to: 86948 -/* 11007 */ MCD_OPC_CheckPredicate, 0, 160, 40, 1, // Skip to: 86948 -/* 11012 */ MCD_OPC_Decode, 247, 32, 77, // Opcode: UQINCD_XPiI -/* 11016 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 11052 -/* 11021 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 11024 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11038 -/* 11029 */ MCD_OPC_CheckPredicate, 0, 138, 40, 1, // Skip to: 86948 -/* 11034 */ MCD_OPC_Decode, 186, 24, 77, // Opcode: SQDECD_XPiWdI -/* 11038 */ MCD_OPC_FilterValue, 1, 129, 40, 1, // Skip to: 86948 -/* 11043 */ MCD_OPC_CheckPredicate, 0, 124, 40, 1, // Skip to: 86948 -/* 11048 */ MCD_OPC_Decode, 185, 24, 77, // Opcode: SQDECD_XPiI -/* 11052 */ MCD_OPC_FilterValue, 15, 115, 40, 1, // Skip to: 86948 -/* 11057 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 11060 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11074 -/* 11065 */ MCD_OPC_CheckPredicate, 0, 102, 40, 1, // Skip to: 86948 -/* 11070 */ MCD_OPC_Decode, 224, 32, 78, // Opcode: UQDECD_WPiI -/* 11074 */ MCD_OPC_FilterValue, 1, 93, 40, 1, // Skip to: 86948 -/* 11079 */ MCD_OPC_CheckPredicate, 0, 88, 40, 1, // Skip to: 86948 -/* 11084 */ MCD_OPC_Decode, 225, 32, 77, // Opcode: UQDECD_XPiI -/* 11088 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 11102 -/* 11093 */ MCD_OPC_CheckPredicate, 0, 74, 40, 1, // Skip to: 86948 -/* 11098 */ MCD_OPC_Decode, 234, 22, 80, // Opcode: SEL_ZPZZ_B -/* 11102 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 11116 -/* 11107 */ MCD_OPC_CheckPredicate, 0, 60, 40, 1, // Skip to: 86948 -/* 11112 */ MCD_OPC_Decode, 236, 22, 80, // Opcode: SEL_ZPZZ_H -/* 11116 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 11130 -/* 11121 */ MCD_OPC_CheckPredicate, 0, 46, 40, 1, // Skip to: 86948 -/* 11126 */ MCD_OPC_Decode, 237, 22, 80, // Opcode: SEL_ZPZZ_S -/* 11130 */ MCD_OPC_FilterValue, 7, 37, 40, 1, // Skip to: 86948 -/* 11135 */ MCD_OPC_CheckPredicate, 0, 32, 40, 1, // Skip to: 86948 -/* 11140 */ MCD_OPC_Decode, 235, 22, 80, // Opcode: SEL_ZPZZ_D -/* 11144 */ MCD_OPC_FilterValue, 1, 8, 23, 0, // Skip to: 17045 -/* 11149 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 11152 */ MCD_OPC_FilterValue, 0, 35, 1, 0, // Skip to: 11448 -/* 11157 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 11160 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11196 -/* 11165 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11168 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11182 -/* 11173 */ MCD_OPC_CheckPredicate, 0, 250, 39, 1, // Skip to: 86948 -/* 11178 */ MCD_OPC_Decode, 182, 4, 81, // Opcode: CMPHS_PPzZZ_B -/* 11182 */ MCD_OPC_FilterValue, 1, 241, 39, 1, // Skip to: 86948 -/* 11187 */ MCD_OPC_CheckPredicate, 0, 236, 39, 1, // Skip to: 86948 -/* 11192 */ MCD_OPC_Decode, 171, 4, 81, // Opcode: CMPHI_PPzZZ_B -/* 11196 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 11232 -/* 11201 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11204 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11218 -/* 11209 */ MCD_OPC_CheckPredicate, 0, 214, 39, 1, // Skip to: 86948 -/* 11214 */ MCD_OPC_Decode, 142, 4, 81, // Opcode: CMPEQ_WIDE_PPzZZ_B -/* 11218 */ MCD_OPC_FilterValue, 1, 205, 39, 1, // Skip to: 86948 -/* 11223 */ MCD_OPC_CheckPredicate, 0, 200, 39, 1, // Skip to: 86948 -/* 11228 */ MCD_OPC_Decode, 225, 4, 81, // Opcode: CMPNE_WIDE_PPzZZ_B -/* 11232 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 11268 -/* 11237 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11240 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11254 -/* 11245 */ MCD_OPC_CheckPredicate, 0, 178, 39, 1, // Skip to: 86948 -/* 11250 */ MCD_OPC_Decode, 153, 4, 81, // Opcode: CMPGE_WIDE_PPzZZ_B -/* 11254 */ MCD_OPC_FilterValue, 1, 169, 39, 1, // Skip to: 86948 -/* 11259 */ MCD_OPC_CheckPredicate, 0, 164, 39, 1, // Skip to: 86948 -/* 11264 */ MCD_OPC_Decode, 164, 4, 81, // Opcode: CMPGT_WIDE_PPzZZ_B -/* 11268 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 11304 -/* 11273 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11276 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11290 -/* 11281 */ MCD_OPC_CheckPredicate, 0, 142, 39, 1, // Skip to: 86948 -/* 11286 */ MCD_OPC_Decode, 214, 4, 81, // Opcode: CMPLT_WIDE_PPzZZ_B -/* 11290 */ MCD_OPC_FilterValue, 1, 133, 39, 1, // Skip to: 86948 -/* 11295 */ MCD_OPC_CheckPredicate, 0, 128, 39, 1, // Skip to: 86948 -/* 11300 */ MCD_OPC_Decode, 193, 4, 81, // Opcode: CMPLE_WIDE_PPzZZ_B -/* 11304 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 11340 -/* 11309 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11312 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11326 -/* 11317 */ MCD_OPC_CheckPredicate, 0, 106, 39, 1, // Skip to: 86948 -/* 11322 */ MCD_OPC_Decode, 149, 4, 81, // Opcode: CMPGE_PPzZZ_B -/* 11326 */ MCD_OPC_FilterValue, 1, 97, 39, 1, // Skip to: 86948 -/* 11331 */ MCD_OPC_CheckPredicate, 0, 92, 39, 1, // Skip to: 86948 -/* 11336 */ MCD_OPC_Decode, 160, 4, 81, // Opcode: CMPGT_PPzZZ_B -/* 11340 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 11376 -/* 11345 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11348 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11362 -/* 11353 */ MCD_OPC_CheckPredicate, 0, 70, 39, 1, // Skip to: 86948 -/* 11358 */ MCD_OPC_Decode, 138, 4, 81, // Opcode: CMPEQ_PPzZZ_B -/* 11362 */ MCD_OPC_FilterValue, 1, 61, 39, 1, // Skip to: 86948 -/* 11367 */ MCD_OPC_CheckPredicate, 0, 56, 39, 1, // Skip to: 86948 -/* 11372 */ MCD_OPC_Decode, 221, 4, 81, // Opcode: CMPNE_PPzZZ_B -/* 11376 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 11412 -/* 11381 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11384 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11398 -/* 11389 */ MCD_OPC_CheckPredicate, 0, 34, 39, 1, // Skip to: 86948 -/* 11394 */ MCD_OPC_Decode, 186, 4, 81, // Opcode: CMPHS_WIDE_PPzZZ_B -/* 11398 */ MCD_OPC_FilterValue, 1, 25, 39, 1, // Skip to: 86948 -/* 11403 */ MCD_OPC_CheckPredicate, 0, 20, 39, 1, // Skip to: 86948 -/* 11408 */ MCD_OPC_Decode, 175, 4, 81, // Opcode: CMPHI_WIDE_PPzZZ_B -/* 11412 */ MCD_OPC_FilterValue, 7, 11, 39, 1, // Skip to: 86948 -/* 11417 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11420 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11434 -/* 11425 */ MCD_OPC_CheckPredicate, 0, 254, 38, 1, // Skip to: 86948 -/* 11430 */ MCD_OPC_Decode, 200, 4, 81, // Opcode: CMPLO_WIDE_PPzZZ_B -/* 11434 */ MCD_OPC_FilterValue, 1, 245, 38, 1, // Skip to: 86948 -/* 11439 */ MCD_OPC_CheckPredicate, 0, 240, 38, 1, // Skip to: 86948 -/* 11444 */ MCD_OPC_Decode, 207, 4, 81, // Opcode: CMPLS_WIDE_PPzZZ_B -/* 11448 */ MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 11528 -/* 11453 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11456 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11492 -/* 11461 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 11464 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11478 -/* 11469 */ MCD_OPC_CheckPredicate, 0, 210, 38, 1, // Skip to: 86948 -/* 11474 */ MCD_OPC_Decode, 178, 4, 82, // Opcode: CMPHS_PPzZI_B -/* 11478 */ MCD_OPC_FilterValue, 1, 201, 38, 1, // Skip to: 86948 -/* 11483 */ MCD_OPC_CheckPredicate, 0, 196, 38, 1, // Skip to: 86948 -/* 11488 */ MCD_OPC_Decode, 196, 4, 82, // Opcode: CMPLO_PPzZI_B -/* 11492 */ MCD_OPC_FilterValue, 1, 187, 38, 1, // Skip to: 86948 -/* 11497 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 11500 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11514 -/* 11505 */ MCD_OPC_CheckPredicate, 0, 174, 38, 1, // Skip to: 86948 -/* 11510 */ MCD_OPC_Decode, 167, 4, 82, // Opcode: CMPHI_PPzZI_B -/* 11514 */ MCD_OPC_FilterValue, 1, 165, 38, 1, // Skip to: 86948 -/* 11519 */ MCD_OPC_CheckPredicate, 0, 160, 38, 1, // Skip to: 86948 -/* 11524 */ MCD_OPC_Decode, 203, 4, 82, // Opcode: CMPLS_PPzZI_B -/* 11528 */ MCD_OPC_FilterValue, 2, 35, 1, 0, // Skip to: 11824 -/* 11533 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 11536 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11572 -/* 11541 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11544 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11558 -/* 11549 */ MCD_OPC_CheckPredicate, 0, 130, 38, 1, // Skip to: 86948 -/* 11554 */ MCD_OPC_Decode, 184, 4, 81, // Opcode: CMPHS_PPzZZ_H -/* 11558 */ MCD_OPC_FilterValue, 1, 121, 38, 1, // Skip to: 86948 -/* 11563 */ MCD_OPC_CheckPredicate, 0, 116, 38, 1, // Skip to: 86948 -/* 11568 */ MCD_OPC_Decode, 173, 4, 81, // Opcode: CMPHI_PPzZZ_H -/* 11572 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 11608 -/* 11577 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11580 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11594 -/* 11585 */ MCD_OPC_CheckPredicate, 0, 94, 38, 1, // Skip to: 86948 -/* 11590 */ MCD_OPC_Decode, 143, 4, 81, // Opcode: CMPEQ_WIDE_PPzZZ_H -/* 11594 */ MCD_OPC_FilterValue, 1, 85, 38, 1, // Skip to: 86948 -/* 11599 */ MCD_OPC_CheckPredicate, 0, 80, 38, 1, // Skip to: 86948 -/* 11604 */ MCD_OPC_Decode, 226, 4, 81, // Opcode: CMPNE_WIDE_PPzZZ_H -/* 11608 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 11644 -/* 11613 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11616 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11630 -/* 11621 */ MCD_OPC_CheckPredicate, 0, 58, 38, 1, // Skip to: 86948 -/* 11626 */ MCD_OPC_Decode, 154, 4, 81, // Opcode: CMPGE_WIDE_PPzZZ_H -/* 11630 */ MCD_OPC_FilterValue, 1, 49, 38, 1, // Skip to: 86948 -/* 11635 */ MCD_OPC_CheckPredicate, 0, 44, 38, 1, // Skip to: 86948 -/* 11640 */ MCD_OPC_Decode, 165, 4, 81, // Opcode: CMPGT_WIDE_PPzZZ_H -/* 11644 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 11680 -/* 11649 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11652 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11666 -/* 11657 */ MCD_OPC_CheckPredicate, 0, 22, 38, 1, // Skip to: 86948 -/* 11662 */ MCD_OPC_Decode, 215, 4, 81, // Opcode: CMPLT_WIDE_PPzZZ_H -/* 11666 */ MCD_OPC_FilterValue, 1, 13, 38, 1, // Skip to: 86948 -/* 11671 */ MCD_OPC_CheckPredicate, 0, 8, 38, 1, // Skip to: 86948 -/* 11676 */ MCD_OPC_Decode, 194, 4, 81, // Opcode: CMPLE_WIDE_PPzZZ_H -/* 11680 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 11716 -/* 11685 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11688 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11702 -/* 11693 */ MCD_OPC_CheckPredicate, 0, 242, 37, 1, // Skip to: 86948 -/* 11698 */ MCD_OPC_Decode, 151, 4, 81, // Opcode: CMPGE_PPzZZ_H -/* 11702 */ MCD_OPC_FilterValue, 1, 233, 37, 1, // Skip to: 86948 -/* 11707 */ MCD_OPC_CheckPredicate, 0, 228, 37, 1, // Skip to: 86948 -/* 11712 */ MCD_OPC_Decode, 162, 4, 81, // Opcode: CMPGT_PPzZZ_H -/* 11716 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 11752 -/* 11721 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11724 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11738 -/* 11729 */ MCD_OPC_CheckPredicate, 0, 206, 37, 1, // Skip to: 86948 -/* 11734 */ MCD_OPC_Decode, 140, 4, 81, // Opcode: CMPEQ_PPzZZ_H -/* 11738 */ MCD_OPC_FilterValue, 1, 197, 37, 1, // Skip to: 86948 -/* 11743 */ MCD_OPC_CheckPredicate, 0, 192, 37, 1, // Skip to: 86948 -/* 11748 */ MCD_OPC_Decode, 223, 4, 81, // Opcode: CMPNE_PPzZZ_H -/* 11752 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 11788 -/* 11757 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11760 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11774 -/* 11765 */ MCD_OPC_CheckPredicate, 0, 170, 37, 1, // Skip to: 86948 -/* 11770 */ MCD_OPC_Decode, 187, 4, 81, // Opcode: CMPHS_WIDE_PPzZZ_H -/* 11774 */ MCD_OPC_FilterValue, 1, 161, 37, 1, // Skip to: 86948 -/* 11779 */ MCD_OPC_CheckPredicate, 0, 156, 37, 1, // Skip to: 86948 -/* 11784 */ MCD_OPC_Decode, 176, 4, 81, // Opcode: CMPHI_WIDE_PPzZZ_H -/* 11788 */ MCD_OPC_FilterValue, 7, 147, 37, 1, // Skip to: 86948 -/* 11793 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11796 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11810 -/* 11801 */ MCD_OPC_CheckPredicate, 0, 134, 37, 1, // Skip to: 86948 -/* 11806 */ MCD_OPC_Decode, 201, 4, 81, // Opcode: CMPLO_WIDE_PPzZZ_H -/* 11810 */ MCD_OPC_FilterValue, 1, 125, 37, 1, // Skip to: 86948 -/* 11815 */ MCD_OPC_CheckPredicate, 0, 120, 37, 1, // Skip to: 86948 -/* 11820 */ MCD_OPC_Decode, 208, 4, 81, // Opcode: CMPLS_WIDE_PPzZZ_H -/* 11824 */ MCD_OPC_FilterValue, 3, 75, 0, 0, // Skip to: 11904 -/* 11829 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11832 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11868 -/* 11837 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 11840 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11854 -/* 11845 */ MCD_OPC_CheckPredicate, 0, 90, 37, 1, // Skip to: 86948 -/* 11850 */ MCD_OPC_Decode, 180, 4, 82, // Opcode: CMPHS_PPzZI_H -/* 11854 */ MCD_OPC_FilterValue, 1, 81, 37, 1, // Skip to: 86948 -/* 11859 */ MCD_OPC_CheckPredicate, 0, 76, 37, 1, // Skip to: 86948 -/* 11864 */ MCD_OPC_Decode, 198, 4, 82, // Opcode: CMPLO_PPzZI_H -/* 11868 */ MCD_OPC_FilterValue, 1, 67, 37, 1, // Skip to: 86948 -/* 11873 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 11876 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11890 -/* 11881 */ MCD_OPC_CheckPredicate, 0, 54, 37, 1, // Skip to: 86948 -/* 11886 */ MCD_OPC_Decode, 169, 4, 82, // Opcode: CMPHI_PPzZI_H -/* 11890 */ MCD_OPC_FilterValue, 1, 45, 37, 1, // Skip to: 86948 -/* 11895 */ MCD_OPC_CheckPredicate, 0, 40, 37, 1, // Skip to: 86948 -/* 11900 */ MCD_OPC_Decode, 205, 4, 82, // Opcode: CMPLS_PPzZI_H -/* 11904 */ MCD_OPC_FilterValue, 4, 35, 1, 0, // Skip to: 12200 -/* 11909 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 11912 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11948 -/* 11917 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11920 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11934 -/* 11925 */ MCD_OPC_CheckPredicate, 0, 10, 37, 1, // Skip to: 86948 -/* 11930 */ MCD_OPC_Decode, 185, 4, 81, // Opcode: CMPHS_PPzZZ_S -/* 11934 */ MCD_OPC_FilterValue, 1, 1, 37, 1, // Skip to: 86948 -/* 11939 */ MCD_OPC_CheckPredicate, 0, 252, 36, 1, // Skip to: 86948 -/* 11944 */ MCD_OPC_Decode, 174, 4, 81, // Opcode: CMPHI_PPzZZ_S -/* 11948 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 11984 -/* 11953 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11956 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11970 -/* 11961 */ MCD_OPC_CheckPredicate, 0, 230, 36, 1, // Skip to: 86948 -/* 11966 */ MCD_OPC_Decode, 144, 4, 81, // Opcode: CMPEQ_WIDE_PPzZZ_S -/* 11970 */ MCD_OPC_FilterValue, 1, 221, 36, 1, // Skip to: 86948 -/* 11975 */ MCD_OPC_CheckPredicate, 0, 216, 36, 1, // Skip to: 86948 -/* 11980 */ MCD_OPC_Decode, 227, 4, 81, // Opcode: CMPNE_WIDE_PPzZZ_S -/* 11984 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 12020 -/* 11989 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 11992 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12006 -/* 11997 */ MCD_OPC_CheckPredicate, 0, 194, 36, 1, // Skip to: 86948 -/* 12002 */ MCD_OPC_Decode, 155, 4, 81, // Opcode: CMPGE_WIDE_PPzZZ_S -/* 12006 */ MCD_OPC_FilterValue, 1, 185, 36, 1, // Skip to: 86948 -/* 12011 */ MCD_OPC_CheckPredicate, 0, 180, 36, 1, // Skip to: 86948 -/* 12016 */ MCD_OPC_Decode, 166, 4, 81, // Opcode: CMPGT_WIDE_PPzZZ_S -/* 12020 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 12056 -/* 12025 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12028 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12042 -/* 12033 */ MCD_OPC_CheckPredicate, 0, 158, 36, 1, // Skip to: 86948 -/* 12038 */ MCD_OPC_Decode, 216, 4, 81, // Opcode: CMPLT_WIDE_PPzZZ_S -/* 12042 */ MCD_OPC_FilterValue, 1, 149, 36, 1, // Skip to: 86948 -/* 12047 */ MCD_OPC_CheckPredicate, 0, 144, 36, 1, // Skip to: 86948 -/* 12052 */ MCD_OPC_Decode, 195, 4, 81, // Opcode: CMPLE_WIDE_PPzZZ_S -/* 12056 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 12092 -/* 12061 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12064 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12078 -/* 12069 */ MCD_OPC_CheckPredicate, 0, 122, 36, 1, // Skip to: 86948 -/* 12074 */ MCD_OPC_Decode, 152, 4, 81, // Opcode: CMPGE_PPzZZ_S -/* 12078 */ MCD_OPC_FilterValue, 1, 113, 36, 1, // Skip to: 86948 -/* 12083 */ MCD_OPC_CheckPredicate, 0, 108, 36, 1, // Skip to: 86948 -/* 12088 */ MCD_OPC_Decode, 163, 4, 81, // Opcode: CMPGT_PPzZZ_S -/* 12092 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 12128 -/* 12097 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12100 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12114 -/* 12105 */ MCD_OPC_CheckPredicate, 0, 86, 36, 1, // Skip to: 86948 -/* 12110 */ MCD_OPC_Decode, 141, 4, 81, // Opcode: CMPEQ_PPzZZ_S -/* 12114 */ MCD_OPC_FilterValue, 1, 77, 36, 1, // Skip to: 86948 -/* 12119 */ MCD_OPC_CheckPredicate, 0, 72, 36, 1, // Skip to: 86948 -/* 12124 */ MCD_OPC_Decode, 224, 4, 81, // Opcode: CMPNE_PPzZZ_S -/* 12128 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 12164 -/* 12133 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12136 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12150 -/* 12141 */ MCD_OPC_CheckPredicate, 0, 50, 36, 1, // Skip to: 86948 -/* 12146 */ MCD_OPC_Decode, 188, 4, 81, // Opcode: CMPHS_WIDE_PPzZZ_S -/* 12150 */ MCD_OPC_FilterValue, 1, 41, 36, 1, // Skip to: 86948 -/* 12155 */ MCD_OPC_CheckPredicate, 0, 36, 36, 1, // Skip to: 86948 -/* 12160 */ MCD_OPC_Decode, 177, 4, 81, // Opcode: CMPHI_WIDE_PPzZZ_S -/* 12164 */ MCD_OPC_FilterValue, 7, 27, 36, 1, // Skip to: 86948 -/* 12169 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12172 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12186 -/* 12177 */ MCD_OPC_CheckPredicate, 0, 14, 36, 1, // Skip to: 86948 -/* 12182 */ MCD_OPC_Decode, 202, 4, 81, // Opcode: CMPLO_WIDE_PPzZZ_S -/* 12186 */ MCD_OPC_FilterValue, 1, 5, 36, 1, // Skip to: 86948 -/* 12191 */ MCD_OPC_CheckPredicate, 0, 0, 36, 1, // Skip to: 86948 -/* 12196 */ MCD_OPC_Decode, 209, 4, 81, // Opcode: CMPLS_WIDE_PPzZZ_S -/* 12200 */ MCD_OPC_FilterValue, 5, 75, 0, 0, // Skip to: 12280 -/* 12205 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12208 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12244 -/* 12213 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 12216 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12230 -/* 12221 */ MCD_OPC_CheckPredicate, 0, 226, 35, 1, // Skip to: 86948 -/* 12226 */ MCD_OPC_Decode, 181, 4, 82, // Opcode: CMPHS_PPzZI_S -/* 12230 */ MCD_OPC_FilterValue, 1, 217, 35, 1, // Skip to: 86948 -/* 12235 */ MCD_OPC_CheckPredicate, 0, 212, 35, 1, // Skip to: 86948 -/* 12240 */ MCD_OPC_Decode, 199, 4, 82, // Opcode: CMPLO_PPzZI_S -/* 12244 */ MCD_OPC_FilterValue, 1, 203, 35, 1, // Skip to: 86948 -/* 12249 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 12252 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12266 -/* 12257 */ MCD_OPC_CheckPredicate, 0, 190, 35, 1, // Skip to: 86948 -/* 12262 */ MCD_OPC_Decode, 170, 4, 82, // Opcode: CMPHI_PPzZI_S -/* 12266 */ MCD_OPC_FilterValue, 1, 181, 35, 1, // Skip to: 86948 -/* 12271 */ MCD_OPC_CheckPredicate, 0, 176, 35, 1, // Skip to: 86948 -/* 12276 */ MCD_OPC_Decode, 206, 4, 82, // Opcode: CMPLS_PPzZI_S -/* 12280 */ MCD_OPC_FilterValue, 6, 111, 0, 0, // Skip to: 12396 -/* 12285 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 12288 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12324 -/* 12293 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12296 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12310 -/* 12301 */ MCD_OPC_CheckPredicate, 0, 146, 35, 1, // Skip to: 86948 -/* 12306 */ MCD_OPC_Decode, 183, 4, 81, // Opcode: CMPHS_PPzZZ_D -/* 12310 */ MCD_OPC_FilterValue, 1, 137, 35, 1, // Skip to: 86948 -/* 12315 */ MCD_OPC_CheckPredicate, 0, 132, 35, 1, // Skip to: 86948 -/* 12320 */ MCD_OPC_Decode, 172, 4, 81, // Opcode: CMPHI_PPzZZ_D -/* 12324 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 12360 -/* 12329 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12332 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12346 -/* 12337 */ MCD_OPC_CheckPredicate, 0, 110, 35, 1, // Skip to: 86948 -/* 12342 */ MCD_OPC_Decode, 150, 4, 81, // Opcode: CMPGE_PPzZZ_D -/* 12346 */ MCD_OPC_FilterValue, 1, 101, 35, 1, // Skip to: 86948 -/* 12351 */ MCD_OPC_CheckPredicate, 0, 96, 35, 1, // Skip to: 86948 -/* 12356 */ MCD_OPC_Decode, 161, 4, 81, // Opcode: CMPGT_PPzZZ_D -/* 12360 */ MCD_OPC_FilterValue, 5, 87, 35, 1, // Skip to: 86948 -/* 12365 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12368 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12382 -/* 12373 */ MCD_OPC_CheckPredicate, 0, 74, 35, 1, // Skip to: 86948 -/* 12378 */ MCD_OPC_Decode, 139, 4, 81, // Opcode: CMPEQ_PPzZZ_D -/* 12382 */ MCD_OPC_FilterValue, 1, 65, 35, 1, // Skip to: 86948 -/* 12387 */ MCD_OPC_CheckPredicate, 0, 60, 35, 1, // Skip to: 86948 -/* 12392 */ MCD_OPC_Decode, 222, 4, 81, // Opcode: CMPNE_PPzZZ_D -/* 12396 */ MCD_OPC_FilterValue, 7, 75, 0, 0, // Skip to: 12476 -/* 12401 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12404 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12440 -/* 12409 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 12412 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12426 -/* 12417 */ MCD_OPC_CheckPredicate, 0, 30, 35, 1, // Skip to: 86948 -/* 12422 */ MCD_OPC_Decode, 179, 4, 82, // Opcode: CMPHS_PPzZI_D -/* 12426 */ MCD_OPC_FilterValue, 1, 21, 35, 1, // Skip to: 86948 -/* 12431 */ MCD_OPC_CheckPredicate, 0, 16, 35, 1, // Skip to: 86948 -/* 12436 */ MCD_OPC_Decode, 197, 4, 82, // Opcode: CMPLO_PPzZI_D -/* 12440 */ MCD_OPC_FilterValue, 1, 7, 35, 1, // Skip to: 86948 -/* 12445 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 12448 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12462 -/* 12453 */ MCD_OPC_CheckPredicate, 0, 250, 34, 1, // Skip to: 86948 -/* 12458 */ MCD_OPC_Decode, 168, 4, 82, // Opcode: CMPHI_PPzZI_D -/* 12462 */ MCD_OPC_FilterValue, 1, 241, 34, 1, // Skip to: 86948 -/* 12467 */ MCD_OPC_CheckPredicate, 0, 236, 34, 1, // Skip to: 86948 -/* 12472 */ MCD_OPC_Decode, 204, 4, 82, // Opcode: CMPLS_PPzZI_D -/* 12476 */ MCD_OPC_FilterValue, 8, 3, 2, 0, // Skip to: 12996 -/* 12481 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 12484 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 12564 -/* 12489 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12492 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12528 -/* 12497 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 12500 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12514 -/* 12505 */ MCD_OPC_CheckPredicate, 0, 198, 34, 1, // Skip to: 86948 -/* 12510 */ MCD_OPC_Decode, 145, 4, 83, // Opcode: CMPGE_PPzZI_B -/* 12514 */ MCD_OPC_FilterValue, 1, 189, 34, 1, // Skip to: 86948 -/* 12519 */ MCD_OPC_CheckPredicate, 0, 184, 34, 1, // Skip to: 86948 -/* 12524 */ MCD_OPC_Decode, 210, 4, 83, // Opcode: CMPLT_PPzZI_B -/* 12528 */ MCD_OPC_FilterValue, 1, 175, 34, 1, // Skip to: 86948 -/* 12533 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 12536 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12550 -/* 12541 */ MCD_OPC_CheckPredicate, 0, 162, 34, 1, // Skip to: 86948 -/* 12546 */ MCD_OPC_Decode, 156, 4, 83, // Opcode: CMPGT_PPzZI_B -/* 12550 */ MCD_OPC_FilterValue, 1, 153, 34, 1, // Skip to: 86948 -/* 12555 */ MCD_OPC_CheckPredicate, 0, 148, 34, 1, // Skip to: 86948 -/* 12560 */ MCD_OPC_Decode, 189, 4, 83, // Opcode: CMPLE_PPzZI_B -/* 12564 */ MCD_OPC_FilterValue, 1, 162, 0, 0, // Skip to: 12731 -/* 12569 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12572 */ MCD_OPC_FilterValue, 0, 82, 0, 0, // Skip to: 12659 -/* 12577 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 12580 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 12638 -/* 12585 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 12588 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12602 -/* 12593 */ MCD_OPC_CheckPredicate, 0, 110, 34, 1, // Skip to: 86948 -/* 12598 */ MCD_OPC_Decode, 245, 1, 84, // Opcode: AND_PPzPP -/* 12602 */ MCD_OPC_FilterValue, 1, 101, 34, 1, // Skip to: 86948 -/* 12607 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 12610 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12624 -/* 12615 */ MCD_OPC_CheckPredicate, 0, 88, 34, 1, // Skip to: 86948 -/* 12620 */ MCD_OPC_Decode, 211, 2, 85, // Opcode: BRKA_PPzP -/* 12624 */ MCD_OPC_FilterValue, 8, 79, 34, 1, // Skip to: 86948 -/* 12629 */ MCD_OPC_CheckPredicate, 0, 74, 34, 1, // Skip to: 86948 -/* 12634 */ MCD_OPC_Decode, 216, 2, 86, // Opcode: BRKN_PPzP -/* 12638 */ MCD_OPC_FilterValue, 1, 65, 34, 1, // Skip to: 86948 -/* 12643 */ MCD_OPC_CheckPredicate, 0, 60, 34, 1, // Skip to: 86948 -/* 12648 */ MCD_OPC_CheckField, 20, 1, 0, 53, 34, 1, // Skip to: 86948 -/* 12655 */ MCD_OPC_Decode, 238, 5, 84, // Opcode: EOR_PPzPP -/* 12659 */ MCD_OPC_FilterValue, 1, 44, 34, 1, // Skip to: 86948 -/* 12664 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 12667 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 12710 -/* 12672 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 12675 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12689 -/* 12680 */ MCD_OPC_CheckPredicate, 0, 23, 34, 1, // Skip to: 86948 -/* 12685 */ MCD_OPC_Decode, 181, 2, 84, // Opcode: BIC_PPzPP -/* 12689 */ MCD_OPC_FilterValue, 1, 14, 34, 1, // Skip to: 86948 -/* 12694 */ MCD_OPC_CheckPredicate, 0, 9, 34, 1, // Skip to: 86948 -/* 12699 */ MCD_OPC_CheckField, 16, 4, 0, 2, 34, 1, // Skip to: 86948 -/* 12706 */ MCD_OPC_Decode, 210, 2, 87, // Opcode: BRKA_PPmP -/* 12710 */ MCD_OPC_FilterValue, 1, 249, 33, 1, // Skip to: 86948 -/* 12715 */ MCD_OPC_CheckPredicate, 0, 244, 33, 1, // Skip to: 86948 -/* 12720 */ MCD_OPC_CheckField, 20, 1, 0, 237, 33, 1, // Skip to: 86948 -/* 12727 */ MCD_OPC_Decode, 233, 22, 84, // Opcode: SEL_PPPP -/* 12731 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 12781 -/* 12736 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12739 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 12760 -/* 12744 */ MCD_OPC_CheckPredicate, 0, 215, 33, 1, // Skip to: 86948 -/* 12749 */ MCD_OPC_CheckField, 13, 1, 0, 208, 33, 1, // Skip to: 86948 -/* 12756 */ MCD_OPC_Decode, 134, 4, 83, // Opcode: CMPEQ_PPzZI_B -/* 12760 */ MCD_OPC_FilterValue, 1, 199, 33, 1, // Skip to: 86948 -/* 12765 */ MCD_OPC_CheckPredicate, 0, 194, 33, 1, // Skip to: 86948 -/* 12770 */ MCD_OPC_CheckField, 13, 1, 0, 187, 33, 1, // Skip to: 86948 -/* 12777 */ MCD_OPC_Decode, 217, 4, 83, // Opcode: CMPNE_PPzZI_B -/* 12781 */ MCD_OPC_FilterValue, 3, 178, 33, 1, // Skip to: 86948 -/* 12786 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 12789 */ MCD_OPC_FilterValue, 0, 174, 0, 0, // Skip to: 12968 -/* 12794 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 12797 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 12818 -/* 12802 */ MCD_OPC_CheckPredicate, 0, 157, 33, 1, // Skip to: 86948 -/* 12807 */ MCD_OPC_CheckField, 9, 1, 0, 150, 33, 1, // Skip to: 86948 -/* 12814 */ MCD_OPC_Decode, 218, 2, 84, // Opcode: BRKPA_PPzPP -/* 12818 */ MCD_OPC_FilterValue, 1, 141, 33, 1, // Skip to: 86948 -/* 12823 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 12826 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 12854 -/* 12831 */ MCD_OPC_CheckPredicate, 0, 128, 33, 1, // Skip to: 86948 -/* 12836 */ MCD_OPC_CheckField, 16, 4, 9, 121, 33, 1, // Skip to: 86948 -/* 12843 */ MCD_OPC_CheckField, 9, 1, 0, 114, 33, 1, // Skip to: 86948 -/* 12850 */ MCD_OPC_Decode, 249, 20, 88, // Opcode: PNEXT_B -/* 12854 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 12890 -/* 12859 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 12862 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 12876 -/* 12867 */ MCD_OPC_CheckPredicate, 0, 92, 33, 1, // Skip to: 86948 -/* 12872 */ MCD_OPC_Decode, 171, 21, 89, // Opcode: PTRUE_B -/* 12876 */ MCD_OPC_FilterValue, 9, 83, 33, 1, // Skip to: 86948 -/* 12881 */ MCD_OPC_CheckPredicate, 0, 78, 33, 1, // Skip to: 86948 -/* 12886 */ MCD_OPC_Decode, 167, 21, 89, // Opcode: PTRUES_B -/* 12890 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 12918 -/* 12895 */ MCD_OPC_CheckPredicate, 0, 64, 33, 1, // Skip to: 86948 -/* 12900 */ MCD_OPC_CheckField, 16, 4, 8, 57, 33, 1, // Skip to: 86948 -/* 12907 */ MCD_OPC_CheckField, 5, 5, 0, 50, 33, 1, // Skip to: 86948 -/* 12914 */ MCD_OPC_Decode, 242, 20, 90, // Opcode: PFALSE -/* 12918 */ MCD_OPC_FilterValue, 12, 41, 33, 1, // Skip to: 86948 -/* 12923 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 12926 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 12947 -/* 12931 */ MCD_OPC_CheckPredicate, 0, 28, 33, 1, // Skip to: 86948 -/* 12936 */ MCD_OPC_CheckField, 9, 1, 0, 21, 33, 1, // Skip to: 86948 -/* 12943 */ MCD_OPC_Decode, 194, 21, 53, // Opcode: RDFFR_PPz -/* 12947 */ MCD_OPC_FilterValue, 9, 12, 33, 1, // Skip to: 86948 -/* 12952 */ MCD_OPC_CheckPredicate, 0, 7, 33, 1, // Skip to: 86948 -/* 12957 */ MCD_OPC_CheckField, 5, 5, 0, 0, 33, 1, // Skip to: 86948 -/* 12964 */ MCD_OPC_Decode, 193, 21, 90, // Opcode: RDFFR_P -/* 12968 */ MCD_OPC_FilterValue, 1, 247, 32, 1, // Skip to: 86948 -/* 12973 */ MCD_OPC_CheckPredicate, 0, 242, 32, 1, // Skip to: 86948 -/* 12978 */ MCD_OPC_CheckField, 20, 1, 0, 235, 32, 1, // Skip to: 86948 -/* 12985 */ MCD_OPC_CheckField, 9, 1, 0, 228, 32, 1, // Skip to: 86948 -/* 12992 */ MCD_OPC_Decode, 220, 2, 84, // Opcode: BRKPB_PPzPP -/* 12996 */ MCD_OPC_FilterValue, 9, 126, 2, 0, // Skip to: 13639 -/* 13001 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 13004 */ MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 13156 -/* 13009 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 13012 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 13048 -/* 13017 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 13020 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13034 -/* 13025 */ MCD_OPC_CheckPredicate, 0, 190, 32, 1, // Skip to: 86948 -/* 13030 */ MCD_OPC_Decode, 242, 34, 91, // Opcode: WHILELT_PWW_B -/* 13034 */ MCD_OPC_FilterValue, 1, 181, 32, 1, // Skip to: 86948 -/* 13039 */ MCD_OPC_CheckPredicate, 0, 176, 32, 1, // Skip to: 86948 -/* 13044 */ MCD_OPC_Decode, 218, 34, 91, // Opcode: WHILELE_PWW_B -/* 13048 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 13084 -/* 13053 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 13056 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13070 -/* 13061 */ MCD_OPC_CheckPredicate, 0, 154, 32, 1, // Skip to: 86948 -/* 13066 */ MCD_OPC_Decode, 226, 34, 91, // Opcode: WHILELO_PWW_B -/* 13070 */ MCD_OPC_FilterValue, 1, 145, 32, 1, // Skip to: 86948 -/* 13075 */ MCD_OPC_CheckPredicate, 0, 140, 32, 1, // Skip to: 86948 -/* 13080 */ MCD_OPC_Decode, 234, 34, 91, // Opcode: WHILELS_PWW_B -/* 13084 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 13120 -/* 13089 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 13092 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13106 -/* 13097 */ MCD_OPC_CheckPredicate, 0, 118, 32, 1, // Skip to: 86948 -/* 13102 */ MCD_OPC_Decode, 246, 34, 92, // Opcode: WHILELT_PXX_B -/* 13106 */ MCD_OPC_FilterValue, 1, 109, 32, 1, // Skip to: 86948 -/* 13111 */ MCD_OPC_CheckPredicate, 0, 104, 32, 1, // Skip to: 86948 -/* 13116 */ MCD_OPC_Decode, 222, 34, 92, // Opcode: WHILELE_PXX_B -/* 13120 */ MCD_OPC_FilterValue, 7, 95, 32, 1, // Skip to: 86948 -/* 13125 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 13128 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13142 -/* 13133 */ MCD_OPC_CheckPredicate, 0, 82, 32, 1, // Skip to: 86948 -/* 13138 */ MCD_OPC_Decode, 230, 34, 92, // Opcode: WHILELO_PXX_B -/* 13142 */ MCD_OPC_FilterValue, 1, 73, 32, 1, // Skip to: 86948 -/* 13147 */ MCD_OPC_CheckPredicate, 0, 68, 32, 1, // Skip to: 86948 -/* 13152 */ MCD_OPC_Decode, 238, 34, 92, // Opcode: WHILELS_PXX_B -/* 13156 */ MCD_OPC_FilterValue, 2, 253, 0, 0, // Skip to: 13414 -/* 13161 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 13164 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 13185 -/* 13169 */ MCD_OPC_CheckPredicate, 0, 46, 32, 1, // Skip to: 86948 -/* 13174 */ MCD_OPC_CheckField, 9, 1, 0, 39, 32, 1, // Skip to: 86948 -/* 13181 */ MCD_OPC_Decode, 248, 4, 93, // Opcode: CNTP_XPP_B -/* 13185 */ MCD_OPC_FilterValue, 8, 52, 0, 0, // Skip to: 13242 -/* 13190 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 13193 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13207 -/* 13198 */ MCD_OPC_CheckPredicate, 0, 17, 32, 1, // Skip to: 86948 -/* 13203 */ MCD_OPC_Decode, 133, 25, 94, // Opcode: SQINCP_XPWd_B -/* 13207 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 13221 -/* 13212 */ MCD_OPC_CheckPredicate, 0, 3, 32, 1, // Skip to: 86948 -/* 13217 */ MCD_OPC_Decode, 137, 25, 94, // Opcode: SQINCP_XP_B -/* 13221 */ MCD_OPC_FilterValue, 8, 250, 31, 1, // Skip to: 86948 -/* 13226 */ MCD_OPC_CheckPredicate, 0, 245, 31, 1, // Skip to: 86948 -/* 13231 */ MCD_OPC_CheckField, 0, 5, 0, 238, 31, 1, // Skip to: 86948 -/* 13238 */ MCD_OPC_Decode, 250, 34, 95, // Opcode: WRFFR -/* 13242 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 13278 -/* 13247 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 13250 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13264 -/* 13255 */ MCD_OPC_CheckPredicate, 0, 216, 31, 1, // Skip to: 86948 -/* 13260 */ MCD_OPC_Decode, 252, 32, 96, // Opcode: UQINCP_WP_B -/* 13264 */ MCD_OPC_FilterValue, 6, 207, 31, 1, // Skip to: 86948 -/* 13269 */ MCD_OPC_CheckPredicate, 0, 202, 31, 1, // Skip to: 86948 -/* 13274 */ MCD_OPC_Decode, 128, 33, 94, // Opcode: UQINCP_XP_B -/* 13278 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 13314 -/* 13283 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 13286 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13300 -/* 13291 */ MCD_OPC_CheckPredicate, 0, 180, 31, 1, // Skip to: 86948 -/* 13296 */ MCD_OPC_Decode, 191, 24, 94, // Opcode: SQDECP_XPWd_B -/* 13300 */ MCD_OPC_FilterValue, 6, 171, 31, 1, // Skip to: 86948 -/* 13305 */ MCD_OPC_CheckPredicate, 0, 166, 31, 1, // Skip to: 86948 -/* 13310 */ MCD_OPC_Decode, 195, 24, 94, // Opcode: SQDECP_XP_B -/* 13314 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 13350 -/* 13319 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 13322 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13336 -/* 13327 */ MCD_OPC_CheckPredicate, 0, 144, 31, 1, // Skip to: 86948 -/* 13332 */ MCD_OPC_Decode, 230, 32, 96, // Opcode: UQDECP_WP_B -/* 13336 */ MCD_OPC_FilterValue, 6, 135, 31, 1, // Skip to: 86948 -/* 13341 */ MCD_OPC_CheckPredicate, 0, 130, 31, 1, // Skip to: 86948 -/* 13346 */ MCD_OPC_Decode, 234, 32, 94, // Opcode: UQDECP_XP_B -/* 13350 */ MCD_OPC_FilterValue, 12, 38, 0, 0, // Skip to: 13393 -/* 13355 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 13358 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13372 -/* 13363 */ MCD_OPC_CheckPredicate, 0, 108, 31, 1, // Skip to: 86948 -/* 13368 */ MCD_OPC_Decode, 249, 13, 94, // Opcode: INCP_XP_B -/* 13372 */ MCD_OPC_FilterValue, 8, 99, 31, 1, // Skip to: 86948 -/* 13377 */ MCD_OPC_CheckPredicate, 0, 94, 31, 1, // Skip to: 86948 -/* 13382 */ MCD_OPC_CheckField, 0, 9, 0, 87, 31, 1, // Skip to: 86948 -/* 13389 */ MCD_OPC_Decode, 240, 22, 97, // Opcode: SETFFR -/* 13393 */ MCD_OPC_FilterValue, 13, 78, 31, 1, // Skip to: 86948 -/* 13398 */ MCD_OPC_CheckPredicate, 0, 73, 31, 1, // Skip to: 86948 -/* 13403 */ MCD_OPC_CheckField, 9, 5, 4, 66, 31, 1, // Skip to: 86948 -/* 13410 */ MCD_OPC_Decode, 182, 5, 94, // Opcode: DECP_XP_B -/* 13414 */ MCD_OPC_FilterValue, 3, 57, 31, 1, // Skip to: 86948 -/* 13419 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 13422 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13436 -/* 13427 */ MCD_OPC_CheckPredicate, 0, 44, 31, 1, // Skip to: 86948 -/* 13432 */ MCD_OPC_Decode, 181, 1, 98, // Opcode: ADD_ZI_B -/* 13436 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 13450 -/* 13441 */ MCD_OPC_CheckPredicate, 0, 30, 31, 1, // Skip to: 86948 -/* 13446 */ MCD_OPC_Decode, 243, 29, 98, // Opcode: SUB_ZI_B -/* 13450 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 13464 -/* 13455 */ MCD_OPC_CheckPredicate, 0, 16, 31, 1, // Skip to: 86948 -/* 13460 */ MCD_OPC_Decode, 217, 29, 98, // Opcode: SUBR_ZI_B -/* 13464 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13478 -/* 13469 */ MCD_OPC_CheckPredicate, 0, 2, 31, 1, // Skip to: 86948 -/* 13474 */ MCD_OPC_Decode, 164, 24, 98, // Opcode: SQADD_ZI_B -/* 13478 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 13492 -/* 13483 */ MCD_OPC_CheckPredicate, 0, 244, 30, 1, // Skip to: 86948 -/* 13488 */ MCD_OPC_Decode, 203, 32, 98, // Opcode: UQADD_ZI_B -/* 13492 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 13506 -/* 13497 */ MCD_OPC_CheckPredicate, 0, 230, 30, 1, // Skip to: 86948 -/* 13502 */ MCD_OPC_Decode, 146, 26, 98, // Opcode: SQSUB_ZI_B -/* 13506 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 13520 -/* 13511 */ MCD_OPC_CheckPredicate, 0, 216, 30, 1, // Skip to: 86948 -/* 13516 */ MCD_OPC_Decode, 189, 33, 98, // Opcode: UQSUB_ZI_B -/* 13520 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 13541 -/* 13525 */ MCD_OPC_CheckPredicate, 0, 202, 30, 1, // Skip to: 86948 -/* 13530 */ MCD_OPC_CheckField, 13, 1, 0, 195, 30, 1, // Skip to: 86948 -/* 13537 */ MCD_OPC_Decode, 192, 23, 99, // Opcode: SMAX_ZI_B -/* 13541 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 13562 -/* 13546 */ MCD_OPC_CheckPredicate, 0, 181, 30, 1, // Skip to: 86948 -/* 13551 */ MCD_OPC_CheckField, 13, 1, 0, 174, 30, 1, // Skip to: 86948 -/* 13558 */ MCD_OPC_Decode, 248, 31, 100, // Opcode: UMAX_ZI_B -/* 13562 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 13583 -/* 13567 */ MCD_OPC_CheckPredicate, 0, 160, 30, 1, // Skip to: 86948 -/* 13572 */ MCD_OPC_CheckField, 13, 1, 0, 153, 30, 1, // Skip to: 86948 -/* 13579 */ MCD_OPC_Decode, 222, 23, 99, // Opcode: SMIN_ZI_B -/* 13583 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 13604 -/* 13588 */ MCD_OPC_CheckPredicate, 0, 139, 30, 1, // Skip to: 86948 -/* 13593 */ MCD_OPC_CheckField, 13, 1, 0, 132, 30, 1, // Skip to: 86948 -/* 13600 */ MCD_OPC_Decode, 149, 32, 100, // Opcode: UMIN_ZI_B -/* 13604 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 13625 -/* 13609 */ MCD_OPC_CheckPredicate, 0, 118, 30, 1, // Skip to: 86948 -/* 13614 */ MCD_OPC_CheckField, 13, 1, 0, 111, 30, 1, // Skip to: 86948 -/* 13621 */ MCD_OPC_Decode, 149, 20, 99, // Opcode: MUL_ZI_B -/* 13625 */ MCD_OPC_FilterValue, 24, 102, 30, 1, // Skip to: 86948 -/* 13630 */ MCD_OPC_CheckPredicate, 0, 97, 30, 1, // Skip to: 86948 -/* 13635 */ MCD_OPC_Decode, 195, 5, 101, // Opcode: DUP_ZI_B -/* 13639 */ MCD_OPC_FilterValue, 10, 208, 1, 0, // Skip to: 14108 -/* 13644 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 13647 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 13727 -/* 13652 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 13655 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 13691 -/* 13660 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 13663 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13677 -/* 13668 */ MCD_OPC_CheckPredicate, 0, 59, 30, 1, // Skip to: 86948 -/* 13673 */ MCD_OPC_Decode, 147, 4, 83, // Opcode: CMPGE_PPzZI_H -/* 13677 */ MCD_OPC_FilterValue, 1, 50, 30, 1, // Skip to: 86948 -/* 13682 */ MCD_OPC_CheckPredicate, 0, 45, 30, 1, // Skip to: 86948 -/* 13687 */ MCD_OPC_Decode, 212, 4, 83, // Opcode: CMPLT_PPzZI_H -/* 13691 */ MCD_OPC_FilterValue, 1, 36, 30, 1, // Skip to: 86948 -/* 13696 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 13699 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13713 -/* 13704 */ MCD_OPC_CheckPredicate, 0, 23, 30, 1, // Skip to: 86948 -/* 13709 */ MCD_OPC_Decode, 158, 4, 83, // Opcode: CMPGT_PPzZI_H -/* 13713 */ MCD_OPC_FilterValue, 1, 14, 30, 1, // Skip to: 86948 -/* 13718 */ MCD_OPC_CheckPredicate, 0, 9, 30, 1, // Skip to: 86948 -/* 13723 */ MCD_OPC_Decode, 191, 4, 83, // Opcode: CMPLE_PPzZI_H -/* 13727 */ MCD_OPC_FilterValue, 1, 118, 0, 0, // Skip to: 13850 -/* 13732 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 13735 */ MCD_OPC_FilterValue, 0, 82, 0, 0, // Skip to: 13822 -/* 13740 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 13743 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 13801 -/* 13748 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 13751 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13765 -/* 13756 */ MCD_OPC_CheckPredicate, 0, 227, 29, 1, // Skip to: 86948 -/* 13761 */ MCD_OPC_Decode, 234, 1, 84, // Opcode: ANDS_PPzPP -/* 13765 */ MCD_OPC_FilterValue, 1, 218, 29, 1, // Skip to: 86948 -/* 13770 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 13773 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13787 -/* 13778 */ MCD_OPC_CheckPredicate, 0, 205, 29, 1, // Skip to: 86948 -/* 13783 */ MCD_OPC_Decode, 209, 2, 85, // Opcode: BRKAS_PPzP -/* 13787 */ MCD_OPC_FilterValue, 8, 196, 29, 1, // Skip to: 86948 -/* 13792 */ MCD_OPC_CheckPredicate, 0, 191, 29, 1, // Skip to: 86948 -/* 13797 */ MCD_OPC_Decode, 215, 2, 86, // Opcode: BRKNS_PPzP -/* 13801 */ MCD_OPC_FilterValue, 1, 182, 29, 1, // Skip to: 86948 -/* 13806 */ MCD_OPC_CheckPredicate, 0, 177, 29, 1, // Skip to: 86948 -/* 13811 */ MCD_OPC_CheckField, 20, 1, 0, 170, 29, 1, // Skip to: 86948 -/* 13818 */ MCD_OPC_Decode, 227, 5, 84, // Opcode: EORS_PPzPP -/* 13822 */ MCD_OPC_FilterValue, 1, 161, 29, 1, // Skip to: 86948 -/* 13827 */ MCD_OPC_CheckPredicate, 0, 156, 29, 1, // Skip to: 86948 -/* 13832 */ MCD_OPC_CheckField, 20, 1, 0, 149, 29, 1, // Skip to: 86948 -/* 13839 */ MCD_OPC_CheckField, 9, 1, 0, 142, 29, 1, // Skip to: 86948 -/* 13846 */ MCD_OPC_Decode, 176, 2, 84, // Opcode: BICS_PPzPP -/* 13850 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 13900 -/* 13855 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 13858 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 13879 -/* 13863 */ MCD_OPC_CheckPredicate, 0, 120, 29, 1, // Skip to: 86948 -/* 13868 */ MCD_OPC_CheckField, 13, 1, 0, 113, 29, 1, // Skip to: 86948 -/* 13875 */ MCD_OPC_Decode, 136, 4, 83, // Opcode: CMPEQ_PPzZI_H -/* 13879 */ MCD_OPC_FilterValue, 1, 104, 29, 1, // Skip to: 86948 -/* 13884 */ MCD_OPC_CheckPredicate, 0, 99, 29, 1, // Skip to: 86948 -/* 13889 */ MCD_OPC_CheckField, 13, 1, 0, 92, 29, 1, // Skip to: 86948 -/* 13896 */ MCD_OPC_Decode, 219, 4, 83, // Opcode: CMPNE_PPzZI_H -/* 13900 */ MCD_OPC_FilterValue, 3, 83, 29, 1, // Skip to: 86948 -/* 13905 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 13908 */ MCD_OPC_FilterValue, 0, 167, 0, 0, // Skip to: 14080 -/* 13913 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 13916 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 13937 -/* 13921 */ MCD_OPC_CheckPredicate, 0, 62, 29, 1, // Skip to: 86948 -/* 13926 */ MCD_OPC_CheckField, 9, 1, 0, 55, 29, 1, // Skip to: 86948 -/* 13933 */ MCD_OPC_Decode, 217, 2, 84, // Opcode: BRKPAS_PPzPP -/* 13937 */ MCD_OPC_FilterValue, 1, 46, 29, 1, // Skip to: 86948 -/* 13942 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 13945 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 13973 -/* 13950 */ MCD_OPC_CheckPredicate, 0, 33, 29, 1, // Skip to: 86948 -/* 13955 */ MCD_OPC_CheckField, 9, 1, 0, 26, 29, 1, // Skip to: 86948 -/* 13962 */ MCD_OPC_CheckField, 0, 4, 0, 19, 29, 1, // Skip to: 86948 -/* 13969 */ MCD_OPC_Decode, 166, 21, 102, // Opcode: PTEST_PP -/* 13973 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 14037 -/* 13978 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 13981 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 14002 -/* 13986 */ MCD_OPC_CheckPredicate, 0, 253, 28, 1, // Skip to: 86948 -/* 13991 */ MCD_OPC_CheckField, 9, 1, 0, 246, 28, 1, // Skip to: 86948 -/* 13998 */ MCD_OPC_Decode, 163, 35, 88, // Opcode: anonymous_1349 -/* 14002 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 14016 -/* 14007 */ MCD_OPC_CheckPredicate, 0, 232, 28, 1, // Skip to: 86948 -/* 14012 */ MCD_OPC_Decode, 173, 21, 89, // Opcode: PTRUE_H -/* 14016 */ MCD_OPC_FilterValue, 12, 223, 28, 1, // Skip to: 86948 -/* 14021 */ MCD_OPC_CheckPredicate, 0, 218, 28, 1, // Skip to: 86948 -/* 14026 */ MCD_OPC_CheckField, 9, 1, 0, 211, 28, 1, // Skip to: 86948 -/* 14033 */ MCD_OPC_Decode, 192, 21, 53, // Opcode: RDFFRS_PPz -/* 14037 */ MCD_OPC_FilterValue, 9, 202, 28, 1, // Skip to: 86948 -/* 14042 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 14045 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 14066 -/* 14050 */ MCD_OPC_CheckPredicate, 0, 189, 28, 1, // Skip to: 86948 -/* 14055 */ MCD_OPC_CheckField, 9, 1, 0, 182, 28, 1, // Skip to: 86948 -/* 14062 */ MCD_OPC_Decode, 251, 20, 88, // Opcode: PNEXT_H -/* 14066 */ MCD_OPC_FilterValue, 8, 173, 28, 1, // Skip to: 86948 -/* 14071 */ MCD_OPC_CheckPredicate, 0, 168, 28, 1, // Skip to: 86948 -/* 14076 */ MCD_OPC_Decode, 169, 21, 89, // Opcode: PTRUES_H -/* 14080 */ MCD_OPC_FilterValue, 1, 159, 28, 1, // Skip to: 86948 -/* 14085 */ MCD_OPC_CheckPredicate, 0, 154, 28, 1, // Skip to: 86948 -/* 14090 */ MCD_OPC_CheckField, 20, 1, 0, 147, 28, 1, // Skip to: 86948 -/* 14097 */ MCD_OPC_CheckField, 9, 1, 0, 140, 28, 1, // Skip to: 86948 -/* 14104 */ MCD_OPC_Decode, 219, 2, 84, // Opcode: BRKPBS_PPzPP -/* 14108 */ MCD_OPC_FilterValue, 11, 190, 2, 0, // Skip to: 14815 -/* 14113 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 14116 */ MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 14268 -/* 14121 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 14124 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 14160 -/* 14129 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 14132 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14146 -/* 14137 */ MCD_OPC_CheckPredicate, 0, 102, 28, 1, // Skip to: 86948 -/* 14142 */ MCD_OPC_Decode, 244, 34, 91, // Opcode: WHILELT_PWW_H -/* 14146 */ MCD_OPC_FilterValue, 1, 93, 28, 1, // Skip to: 86948 -/* 14151 */ MCD_OPC_CheckPredicate, 0, 88, 28, 1, // Skip to: 86948 -/* 14156 */ MCD_OPC_Decode, 220, 34, 91, // Opcode: WHILELE_PWW_H -/* 14160 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 14196 -/* 14165 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 14168 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14182 -/* 14173 */ MCD_OPC_CheckPredicate, 0, 66, 28, 1, // Skip to: 86948 -/* 14178 */ MCD_OPC_Decode, 228, 34, 91, // Opcode: WHILELO_PWW_H -/* 14182 */ MCD_OPC_FilterValue, 1, 57, 28, 1, // Skip to: 86948 -/* 14187 */ MCD_OPC_CheckPredicate, 0, 52, 28, 1, // Skip to: 86948 -/* 14192 */ MCD_OPC_Decode, 236, 34, 91, // Opcode: WHILELS_PWW_H -/* 14196 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 14232 -/* 14201 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 14204 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14218 -/* 14209 */ MCD_OPC_CheckPredicate, 0, 30, 28, 1, // Skip to: 86948 -/* 14214 */ MCD_OPC_Decode, 248, 34, 92, // Opcode: WHILELT_PXX_H -/* 14218 */ MCD_OPC_FilterValue, 1, 21, 28, 1, // Skip to: 86948 -/* 14223 */ MCD_OPC_CheckPredicate, 0, 16, 28, 1, // Skip to: 86948 -/* 14228 */ MCD_OPC_Decode, 224, 34, 92, // Opcode: WHILELE_PXX_H -/* 14232 */ MCD_OPC_FilterValue, 7, 7, 28, 1, // Skip to: 86948 -/* 14237 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 14240 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14254 -/* 14245 */ MCD_OPC_CheckPredicate, 0, 250, 27, 1, // Skip to: 86948 -/* 14250 */ MCD_OPC_Decode, 232, 34, 92, // Opcode: WHILELO_PXX_H -/* 14254 */ MCD_OPC_FilterValue, 1, 241, 27, 1, // Skip to: 86948 -/* 14259 */ MCD_OPC_CheckPredicate, 0, 236, 27, 1, // Skip to: 86948 -/* 14264 */ MCD_OPC_Decode, 240, 34, 92, // Opcode: WHILELS_PXX_H -/* 14268 */ MCD_OPC_FilterValue, 2, 40, 1, 0, // Skip to: 14569 -/* 14273 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 14276 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 14297 -/* 14281 */ MCD_OPC_CheckPredicate, 0, 214, 27, 1, // Skip to: 86948 -/* 14286 */ MCD_OPC_CheckField, 9, 1, 0, 207, 27, 1, // Skip to: 86948 -/* 14293 */ MCD_OPC_Decode, 250, 4, 93, // Opcode: CNTP_XPP_H -/* 14297 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 14347 -/* 14302 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 14305 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14319 -/* 14310 */ MCD_OPC_CheckPredicate, 0, 185, 27, 1, // Skip to: 86948 -/* 14315 */ MCD_OPC_Decode, 142, 25, 103, // Opcode: SQINCP_ZP_H -/* 14319 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14333 -/* 14324 */ MCD_OPC_CheckPredicate, 0, 171, 27, 1, // Skip to: 86948 -/* 14329 */ MCD_OPC_Decode, 135, 25, 94, // Opcode: SQINCP_XPWd_H -/* 14333 */ MCD_OPC_FilterValue, 6, 162, 27, 1, // Skip to: 86948 -/* 14338 */ MCD_OPC_CheckPredicate, 0, 157, 27, 1, // Skip to: 86948 -/* 14343 */ MCD_OPC_Decode, 139, 25, 94, // Opcode: SQINCP_XP_H -/* 14347 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 14397 -/* 14352 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 14355 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14369 -/* 14360 */ MCD_OPC_CheckPredicate, 0, 135, 27, 1, // Skip to: 86948 -/* 14365 */ MCD_OPC_Decode, 133, 33, 103, // Opcode: UQINCP_ZP_H -/* 14369 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14383 -/* 14374 */ MCD_OPC_CheckPredicate, 0, 121, 27, 1, // Skip to: 86948 -/* 14379 */ MCD_OPC_Decode, 254, 32, 96, // Opcode: UQINCP_WP_H -/* 14383 */ MCD_OPC_FilterValue, 6, 112, 27, 1, // Skip to: 86948 -/* 14388 */ MCD_OPC_CheckPredicate, 0, 107, 27, 1, // Skip to: 86948 -/* 14393 */ MCD_OPC_Decode, 130, 33, 94, // Opcode: UQINCP_XP_H -/* 14397 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 14447 -/* 14402 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 14405 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14419 -/* 14410 */ MCD_OPC_CheckPredicate, 0, 85, 27, 1, // Skip to: 86948 -/* 14415 */ MCD_OPC_Decode, 200, 24, 103, // Opcode: SQDECP_ZP_H -/* 14419 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14433 -/* 14424 */ MCD_OPC_CheckPredicate, 0, 71, 27, 1, // Skip to: 86948 -/* 14429 */ MCD_OPC_Decode, 193, 24, 94, // Opcode: SQDECP_XPWd_H -/* 14433 */ MCD_OPC_FilterValue, 6, 62, 27, 1, // Skip to: 86948 -/* 14438 */ MCD_OPC_CheckPredicate, 0, 57, 27, 1, // Skip to: 86948 -/* 14443 */ MCD_OPC_Decode, 197, 24, 94, // Opcode: SQDECP_XP_H -/* 14447 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 14497 -/* 14452 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 14455 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14469 -/* 14460 */ MCD_OPC_CheckPredicate, 0, 35, 27, 1, // Skip to: 86948 -/* 14465 */ MCD_OPC_Decode, 239, 32, 103, // Opcode: UQDECP_ZP_H -/* 14469 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14483 -/* 14474 */ MCD_OPC_CheckPredicate, 0, 21, 27, 1, // Skip to: 86948 -/* 14479 */ MCD_OPC_Decode, 232, 32, 96, // Opcode: UQDECP_WP_H -/* 14483 */ MCD_OPC_FilterValue, 6, 12, 27, 1, // Skip to: 86948 -/* 14488 */ MCD_OPC_CheckPredicate, 0, 7, 27, 1, // Skip to: 86948 -/* 14493 */ MCD_OPC_Decode, 236, 32, 94, // Opcode: UQDECP_XP_H -/* 14497 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 14533 -/* 14502 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 14505 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14519 -/* 14510 */ MCD_OPC_CheckPredicate, 0, 241, 26, 1, // Skip to: 86948 -/* 14515 */ MCD_OPC_Decode, 254, 13, 103, // Opcode: INCP_ZP_H -/* 14519 */ MCD_OPC_FilterValue, 4, 232, 26, 1, // Skip to: 86948 -/* 14524 */ MCD_OPC_CheckPredicate, 0, 227, 26, 1, // Skip to: 86948 -/* 14529 */ MCD_OPC_Decode, 251, 13, 94, // Opcode: INCP_XP_H -/* 14533 */ MCD_OPC_FilterValue, 13, 218, 26, 1, // Skip to: 86948 -/* 14538 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 14541 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14555 -/* 14546 */ MCD_OPC_CheckPredicate, 0, 205, 26, 1, // Skip to: 86948 -/* 14551 */ MCD_OPC_Decode, 187, 5, 103, // Opcode: DECP_ZP_H -/* 14555 */ MCD_OPC_FilterValue, 4, 196, 26, 1, // Skip to: 86948 -/* 14560 */ MCD_OPC_CheckPredicate, 0, 191, 26, 1, // Skip to: 86948 -/* 14565 */ MCD_OPC_Decode, 184, 5, 94, // Opcode: DECP_XP_H -/* 14569 */ MCD_OPC_FilterValue, 3, 182, 26, 1, // Skip to: 86948 -/* 14574 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 14577 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14591 -/* 14582 */ MCD_OPC_CheckPredicate, 0, 169, 26, 1, // Skip to: 86948 -/* 14587 */ MCD_OPC_Decode, 183, 1, 104, // Opcode: ADD_ZI_H -/* 14591 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 14605 -/* 14596 */ MCD_OPC_CheckPredicate, 0, 155, 26, 1, // Skip to: 86948 -/* 14601 */ MCD_OPC_Decode, 245, 29, 104, // Opcode: SUB_ZI_H -/* 14605 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 14619 -/* 14610 */ MCD_OPC_CheckPredicate, 0, 141, 26, 1, // Skip to: 86948 -/* 14615 */ MCD_OPC_Decode, 219, 29, 104, // Opcode: SUBR_ZI_H -/* 14619 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14633 -/* 14624 */ MCD_OPC_CheckPredicate, 0, 127, 26, 1, // Skip to: 86948 -/* 14629 */ MCD_OPC_Decode, 166, 24, 104, // Opcode: SQADD_ZI_H -/* 14633 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 14647 -/* 14638 */ MCD_OPC_CheckPredicate, 0, 113, 26, 1, // Skip to: 86948 -/* 14643 */ MCD_OPC_Decode, 205, 32, 104, // Opcode: UQADD_ZI_H -/* 14647 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 14661 -/* 14652 */ MCD_OPC_CheckPredicate, 0, 99, 26, 1, // Skip to: 86948 -/* 14657 */ MCD_OPC_Decode, 148, 26, 104, // Opcode: SQSUB_ZI_H -/* 14661 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 14675 -/* 14666 */ MCD_OPC_CheckPredicate, 0, 85, 26, 1, // Skip to: 86948 -/* 14671 */ MCD_OPC_Decode, 191, 33, 104, // Opcode: UQSUB_ZI_H -/* 14675 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 14696 -/* 14680 */ MCD_OPC_CheckPredicate, 0, 71, 26, 1, // Skip to: 86948 -/* 14685 */ MCD_OPC_CheckField, 13, 1, 0, 64, 26, 1, // Skip to: 86948 -/* 14692 */ MCD_OPC_Decode, 194, 23, 99, // Opcode: SMAX_ZI_H -/* 14696 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 14717 -/* 14701 */ MCD_OPC_CheckPredicate, 0, 50, 26, 1, // Skip to: 86948 -/* 14706 */ MCD_OPC_CheckField, 13, 1, 0, 43, 26, 1, // Skip to: 86948 -/* 14713 */ MCD_OPC_Decode, 250, 31, 100, // Opcode: UMAX_ZI_H -/* 14717 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 14738 -/* 14722 */ MCD_OPC_CheckPredicate, 0, 29, 26, 1, // Skip to: 86948 -/* 14727 */ MCD_OPC_CheckField, 13, 1, 0, 22, 26, 1, // Skip to: 86948 -/* 14734 */ MCD_OPC_Decode, 224, 23, 99, // Opcode: SMIN_ZI_H -/* 14738 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 14759 -/* 14743 */ MCD_OPC_CheckPredicate, 0, 8, 26, 1, // Skip to: 86948 -/* 14748 */ MCD_OPC_CheckField, 13, 1, 0, 1, 26, 1, // Skip to: 86948 -/* 14755 */ MCD_OPC_Decode, 151, 32, 100, // Opcode: UMIN_ZI_H -/* 14759 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 14780 -/* 14764 */ MCD_OPC_CheckPredicate, 0, 243, 25, 1, // Skip to: 86948 -/* 14769 */ MCD_OPC_CheckField, 13, 1, 0, 236, 25, 1, // Skip to: 86948 -/* 14776 */ MCD_OPC_Decode, 151, 20, 99, // Opcode: MUL_ZI_H -/* 14780 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 14794 -/* 14785 */ MCD_OPC_CheckPredicate, 0, 222, 25, 1, // Skip to: 86948 -/* 14790 */ MCD_OPC_Decode, 197, 5, 105, // Opcode: DUP_ZI_H -/* 14794 */ MCD_OPC_FilterValue, 25, 213, 25, 1, // Skip to: 86948 -/* 14799 */ MCD_OPC_CheckPredicate, 0, 208, 25, 1, // Skip to: 86948 -/* 14804 */ MCD_OPC_CheckField, 13, 1, 0, 201, 25, 1, // Skip to: 86948 -/* 14811 */ MCD_OPC_Decode, 181, 9, 106, // Opcode: FDUP_ZI_H -/* 14815 */ MCD_OPC_FilterValue, 12, 122, 1, 0, // Skip to: 15198 -/* 14820 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 14823 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 14903 -/* 14828 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 14831 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 14867 -/* 14836 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 14839 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14853 -/* 14844 */ MCD_OPC_CheckPredicate, 0, 163, 25, 1, // Skip to: 86948 -/* 14849 */ MCD_OPC_Decode, 148, 4, 83, // Opcode: CMPGE_PPzZI_S -/* 14853 */ MCD_OPC_FilterValue, 1, 154, 25, 1, // Skip to: 86948 -/* 14858 */ MCD_OPC_CheckPredicate, 0, 149, 25, 1, // Skip to: 86948 -/* 14863 */ MCD_OPC_Decode, 213, 4, 83, // Opcode: CMPLT_PPzZI_S -/* 14867 */ MCD_OPC_FilterValue, 1, 140, 25, 1, // Skip to: 86948 -/* 14872 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 14875 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14889 -/* 14880 */ MCD_OPC_CheckPredicate, 0, 127, 25, 1, // Skip to: 86948 -/* 14885 */ MCD_OPC_Decode, 159, 4, 83, // Opcode: CMPGT_PPzZI_S -/* 14889 */ MCD_OPC_FilterValue, 1, 118, 25, 1, // Skip to: 86948 -/* 14894 */ MCD_OPC_CheckPredicate, 0, 113, 25, 1, // Skip to: 86948 -/* 14899 */ MCD_OPC_Decode, 192, 4, 83, // Opcode: CMPLE_PPzZI_S -/* 14903 */ MCD_OPC_FilterValue, 1, 147, 0, 0, // Skip to: 15055 -/* 14908 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 14911 */ MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 14983 -/* 14916 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 14919 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 14962 -/* 14924 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 14927 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14941 -/* 14932 */ MCD_OPC_CheckPredicate, 0, 75, 25, 1, // Skip to: 86948 -/* 14937 */ MCD_OPC_Decode, 210, 20, 84, // Opcode: ORR_PPzPP -/* 14941 */ MCD_OPC_FilterValue, 1, 66, 25, 1, // Skip to: 86948 -/* 14946 */ MCD_OPC_CheckPredicate, 0, 61, 25, 1, // Skip to: 86948 -/* 14951 */ MCD_OPC_CheckField, 16, 4, 0, 54, 25, 1, // Skip to: 86948 -/* 14958 */ MCD_OPC_Decode, 214, 2, 85, // Opcode: BRKB_PPzP -/* 14962 */ MCD_OPC_FilterValue, 1, 45, 25, 1, // Skip to: 86948 -/* 14967 */ MCD_OPC_CheckPredicate, 0, 40, 25, 1, // Skip to: 86948 -/* 14972 */ MCD_OPC_CheckField, 20, 1, 0, 33, 25, 1, // Skip to: 86948 -/* 14979 */ MCD_OPC_Decode, 188, 20, 84, // Opcode: NOR_PPzPP -/* 14983 */ MCD_OPC_FilterValue, 1, 24, 25, 1, // Skip to: 86948 -/* 14988 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 14991 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 15034 -/* 14996 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 14999 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15013 -/* 15004 */ MCD_OPC_CheckPredicate, 0, 3, 25, 1, // Skip to: 86948 -/* 15009 */ MCD_OPC_Decode, 200, 20, 84, // Opcode: ORN_PPzPP -/* 15013 */ MCD_OPC_FilterValue, 1, 250, 24, 1, // Skip to: 86948 -/* 15018 */ MCD_OPC_CheckPredicate, 0, 245, 24, 1, // Skip to: 86948 -/* 15023 */ MCD_OPC_CheckField, 16, 4, 0, 238, 24, 1, // Skip to: 86948 -/* 15030 */ MCD_OPC_Decode, 213, 2, 87, // Opcode: BRKB_PPmP -/* 15034 */ MCD_OPC_FilterValue, 1, 229, 24, 1, // Skip to: 86948 -/* 15039 */ MCD_OPC_CheckPredicate, 0, 224, 24, 1, // Skip to: 86948 -/* 15044 */ MCD_OPC_CheckField, 20, 1, 0, 217, 24, 1, // Skip to: 86948 -/* 15051 */ MCD_OPC_Decode, 174, 20, 84, // Opcode: NAND_PPzPP -/* 15055 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 15105 -/* 15060 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 15063 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 15084 -/* 15068 */ MCD_OPC_CheckPredicate, 0, 195, 24, 1, // Skip to: 86948 -/* 15073 */ MCD_OPC_CheckField, 13, 1, 0, 188, 24, 1, // Skip to: 86948 -/* 15080 */ MCD_OPC_Decode, 137, 4, 83, // Opcode: CMPEQ_PPzZI_S -/* 15084 */ MCD_OPC_FilterValue, 1, 179, 24, 1, // Skip to: 86948 -/* 15089 */ MCD_OPC_CheckPredicate, 0, 174, 24, 1, // Skip to: 86948 -/* 15094 */ MCD_OPC_CheckField, 13, 1, 0, 167, 24, 1, // Skip to: 86948 -/* 15101 */ MCD_OPC_Decode, 220, 4, 83, // Opcode: CMPNE_PPzZI_S -/* 15105 */ MCD_OPC_FilterValue, 3, 158, 24, 1, // Skip to: 86948 -/* 15110 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 15113 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 15148 -/* 15118 */ MCD_OPC_CheckPredicate, 0, 145, 24, 1, // Skip to: 86948 -/* 15123 */ MCD_OPC_CheckField, 16, 5, 25, 138, 24, 1, // Skip to: 86948 -/* 15130 */ MCD_OPC_CheckField, 9, 1, 0, 131, 24, 1, // Skip to: 86948 -/* 15137 */ MCD_OPC_CheckField, 4, 1, 0, 124, 24, 1, // Skip to: 86948 -/* 15144 */ MCD_OPC_Decode, 252, 20, 88, // Opcode: PNEXT_S -/* 15148 */ MCD_OPC_FilterValue, 8, 115, 24, 1, // Skip to: 86948 -/* 15153 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 15156 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 15177 -/* 15161 */ MCD_OPC_CheckPredicate, 0, 102, 24, 1, // Skip to: 86948 -/* 15166 */ MCD_OPC_CheckField, 4, 1, 0, 95, 24, 1, // Skip to: 86948 -/* 15173 */ MCD_OPC_Decode, 174, 21, 89, // Opcode: PTRUE_S -/* 15177 */ MCD_OPC_FilterValue, 25, 86, 24, 1, // Skip to: 86948 -/* 15182 */ MCD_OPC_CheckPredicate, 0, 81, 24, 1, // Skip to: 86948 -/* 15187 */ MCD_OPC_CheckField, 4, 1, 0, 74, 24, 1, // Skip to: 86948 -/* 15194 */ MCD_OPC_Decode, 170, 21, 89, // Opcode: PTRUES_S -/* 15198 */ MCD_OPC_FilterValue, 13, 226, 2, 0, // Skip to: 15941 -/* 15203 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 15206 */ MCD_OPC_FilterValue, 0, 183, 0, 0, // Skip to: 15394 -/* 15211 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 15214 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 15250 -/* 15219 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 15222 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15236 -/* 15227 */ MCD_OPC_CheckPredicate, 0, 36, 24, 1, // Skip to: 86948 -/* 15232 */ MCD_OPC_Decode, 245, 34, 91, // Opcode: WHILELT_PWW_S -/* 15236 */ MCD_OPC_FilterValue, 1, 27, 24, 1, // Skip to: 86948 -/* 15241 */ MCD_OPC_CheckPredicate, 0, 22, 24, 1, // Skip to: 86948 -/* 15246 */ MCD_OPC_Decode, 221, 34, 91, // Opcode: WHILELE_PWW_S -/* 15250 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 15286 -/* 15255 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 15258 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15272 -/* 15263 */ MCD_OPC_CheckPredicate, 0, 0, 24, 1, // Skip to: 86948 -/* 15268 */ MCD_OPC_Decode, 229, 34, 91, // Opcode: WHILELO_PWW_S -/* 15272 */ MCD_OPC_FilterValue, 1, 247, 23, 1, // Skip to: 86948 -/* 15277 */ MCD_OPC_CheckPredicate, 0, 242, 23, 1, // Skip to: 86948 -/* 15282 */ MCD_OPC_Decode, 237, 34, 91, // Opcode: WHILELS_PWW_S -/* 15286 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 15322 -/* 15291 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 15294 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15308 -/* 15299 */ MCD_OPC_CheckPredicate, 0, 220, 23, 1, // Skip to: 86948 -/* 15304 */ MCD_OPC_Decode, 249, 34, 92, // Opcode: WHILELT_PXX_S -/* 15308 */ MCD_OPC_FilterValue, 1, 211, 23, 1, // Skip to: 86948 -/* 15313 */ MCD_OPC_CheckPredicate, 0, 206, 23, 1, // Skip to: 86948 -/* 15318 */ MCD_OPC_Decode, 225, 34, 92, // Opcode: WHILELE_PXX_S -/* 15322 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 15358 -/* 15327 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 15330 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15344 -/* 15335 */ MCD_OPC_CheckPredicate, 0, 184, 23, 1, // Skip to: 86948 -/* 15340 */ MCD_OPC_Decode, 233, 34, 92, // Opcode: WHILELO_PXX_S -/* 15344 */ MCD_OPC_FilterValue, 1, 175, 23, 1, // Skip to: 86948 -/* 15349 */ MCD_OPC_CheckPredicate, 0, 170, 23, 1, // Skip to: 86948 -/* 15354 */ MCD_OPC_Decode, 241, 34, 92, // Opcode: WHILELS_PXX_S -/* 15358 */ MCD_OPC_FilterValue, 8, 161, 23, 1, // Skip to: 86948 -/* 15363 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 15366 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15380 -/* 15371 */ MCD_OPC_CheckPredicate, 0, 148, 23, 1, // Skip to: 86948 -/* 15376 */ MCD_OPC_Decode, 169, 5, 107, // Opcode: CTERMEQ_WW -/* 15380 */ MCD_OPC_FilterValue, 16, 139, 23, 1, // Skip to: 86948 -/* 15385 */ MCD_OPC_CheckPredicate, 0, 134, 23, 1, // Skip to: 86948 -/* 15390 */ MCD_OPC_Decode, 171, 5, 107, // Opcode: CTERMNE_WW -/* 15394 */ MCD_OPC_FilterValue, 2, 40, 1, 0, // Skip to: 15695 -/* 15399 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 15402 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 15423 -/* 15407 */ MCD_OPC_CheckPredicate, 0, 112, 23, 1, // Skip to: 86948 -/* 15412 */ MCD_OPC_CheckField, 9, 1, 0, 105, 23, 1, // Skip to: 86948 -/* 15419 */ MCD_OPC_Decode, 251, 4, 93, // Opcode: CNTP_XPP_S -/* 15423 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 15473 -/* 15428 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 15431 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15445 -/* 15436 */ MCD_OPC_CheckPredicate, 0, 83, 23, 1, // Skip to: 86948 -/* 15441 */ MCD_OPC_Decode, 143, 25, 103, // Opcode: SQINCP_ZP_S -/* 15445 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15459 -/* 15450 */ MCD_OPC_CheckPredicate, 0, 69, 23, 1, // Skip to: 86948 -/* 15455 */ MCD_OPC_Decode, 136, 25, 94, // Opcode: SQINCP_XPWd_S -/* 15459 */ MCD_OPC_FilterValue, 6, 60, 23, 1, // Skip to: 86948 -/* 15464 */ MCD_OPC_CheckPredicate, 0, 55, 23, 1, // Skip to: 86948 -/* 15469 */ MCD_OPC_Decode, 140, 25, 94, // Opcode: SQINCP_XP_S -/* 15473 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 15523 -/* 15478 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 15481 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15495 -/* 15486 */ MCD_OPC_CheckPredicate, 0, 33, 23, 1, // Skip to: 86948 -/* 15491 */ MCD_OPC_Decode, 134, 33, 103, // Opcode: UQINCP_ZP_S -/* 15495 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15509 -/* 15500 */ MCD_OPC_CheckPredicate, 0, 19, 23, 1, // Skip to: 86948 -/* 15505 */ MCD_OPC_Decode, 255, 32, 96, // Opcode: UQINCP_WP_S -/* 15509 */ MCD_OPC_FilterValue, 6, 10, 23, 1, // Skip to: 86948 -/* 15514 */ MCD_OPC_CheckPredicate, 0, 5, 23, 1, // Skip to: 86948 -/* 15519 */ MCD_OPC_Decode, 131, 33, 94, // Opcode: UQINCP_XP_S -/* 15523 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 15573 -/* 15528 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 15531 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15545 -/* 15536 */ MCD_OPC_CheckPredicate, 0, 239, 22, 1, // Skip to: 86948 -/* 15541 */ MCD_OPC_Decode, 201, 24, 103, // Opcode: SQDECP_ZP_S -/* 15545 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15559 -/* 15550 */ MCD_OPC_CheckPredicate, 0, 225, 22, 1, // Skip to: 86948 -/* 15555 */ MCD_OPC_Decode, 194, 24, 94, // Opcode: SQDECP_XPWd_S -/* 15559 */ MCD_OPC_FilterValue, 6, 216, 22, 1, // Skip to: 86948 -/* 15564 */ MCD_OPC_CheckPredicate, 0, 211, 22, 1, // Skip to: 86948 -/* 15569 */ MCD_OPC_Decode, 198, 24, 94, // Opcode: SQDECP_XP_S -/* 15573 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 15623 -/* 15578 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 15581 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15595 -/* 15586 */ MCD_OPC_CheckPredicate, 0, 189, 22, 1, // Skip to: 86948 -/* 15591 */ MCD_OPC_Decode, 240, 32, 103, // Opcode: UQDECP_ZP_S -/* 15595 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15609 -/* 15600 */ MCD_OPC_CheckPredicate, 0, 175, 22, 1, // Skip to: 86948 -/* 15605 */ MCD_OPC_Decode, 233, 32, 96, // Opcode: UQDECP_WP_S -/* 15609 */ MCD_OPC_FilterValue, 6, 166, 22, 1, // Skip to: 86948 -/* 15614 */ MCD_OPC_CheckPredicate, 0, 161, 22, 1, // Skip to: 86948 -/* 15619 */ MCD_OPC_Decode, 237, 32, 94, // Opcode: UQDECP_XP_S -/* 15623 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 15659 -/* 15628 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 15631 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15645 -/* 15636 */ MCD_OPC_CheckPredicate, 0, 139, 22, 1, // Skip to: 86948 -/* 15641 */ MCD_OPC_Decode, 255, 13, 103, // Opcode: INCP_ZP_S -/* 15645 */ MCD_OPC_FilterValue, 4, 130, 22, 1, // Skip to: 86948 -/* 15650 */ MCD_OPC_CheckPredicate, 0, 125, 22, 1, // Skip to: 86948 -/* 15655 */ MCD_OPC_Decode, 252, 13, 94, // Opcode: INCP_XP_S -/* 15659 */ MCD_OPC_FilterValue, 13, 116, 22, 1, // Skip to: 86948 -/* 15664 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 15667 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15681 -/* 15672 */ MCD_OPC_CheckPredicate, 0, 103, 22, 1, // Skip to: 86948 -/* 15677 */ MCD_OPC_Decode, 188, 5, 103, // Opcode: DECP_ZP_S -/* 15681 */ MCD_OPC_FilterValue, 4, 94, 22, 1, // Skip to: 86948 -/* 15686 */ MCD_OPC_CheckPredicate, 0, 89, 22, 1, // Skip to: 86948 -/* 15691 */ MCD_OPC_Decode, 185, 5, 94, // Opcode: DECP_XP_S -/* 15695 */ MCD_OPC_FilterValue, 3, 80, 22, 1, // Skip to: 86948 -/* 15700 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 15703 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15717 -/* 15708 */ MCD_OPC_CheckPredicate, 0, 67, 22, 1, // Skip to: 86948 -/* 15713 */ MCD_OPC_Decode, 184, 1, 108, // Opcode: ADD_ZI_S -/* 15717 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 15731 -/* 15722 */ MCD_OPC_CheckPredicate, 0, 53, 22, 1, // Skip to: 86948 -/* 15727 */ MCD_OPC_Decode, 246, 29, 108, // Opcode: SUB_ZI_S -/* 15731 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 15745 -/* 15736 */ MCD_OPC_CheckPredicate, 0, 39, 22, 1, // Skip to: 86948 -/* 15741 */ MCD_OPC_Decode, 220, 29, 108, // Opcode: SUBR_ZI_S -/* 15745 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15759 -/* 15750 */ MCD_OPC_CheckPredicate, 0, 25, 22, 1, // Skip to: 86948 -/* 15755 */ MCD_OPC_Decode, 167, 24, 108, // Opcode: SQADD_ZI_S -/* 15759 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 15773 -/* 15764 */ MCD_OPC_CheckPredicate, 0, 11, 22, 1, // Skip to: 86948 -/* 15769 */ MCD_OPC_Decode, 206, 32, 108, // Opcode: UQADD_ZI_S -/* 15773 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 15787 -/* 15778 */ MCD_OPC_CheckPredicate, 0, 253, 21, 1, // Skip to: 86948 -/* 15783 */ MCD_OPC_Decode, 149, 26, 108, // Opcode: SQSUB_ZI_S -/* 15787 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 15801 -/* 15792 */ MCD_OPC_CheckPredicate, 0, 239, 21, 1, // Skip to: 86948 -/* 15797 */ MCD_OPC_Decode, 192, 33, 108, // Opcode: UQSUB_ZI_S -/* 15801 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 15822 -/* 15806 */ MCD_OPC_CheckPredicate, 0, 225, 21, 1, // Skip to: 86948 -/* 15811 */ MCD_OPC_CheckField, 13, 1, 0, 218, 21, 1, // Skip to: 86948 -/* 15818 */ MCD_OPC_Decode, 195, 23, 99, // Opcode: SMAX_ZI_S -/* 15822 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 15843 -/* 15827 */ MCD_OPC_CheckPredicate, 0, 204, 21, 1, // Skip to: 86948 -/* 15832 */ MCD_OPC_CheckField, 13, 1, 0, 197, 21, 1, // Skip to: 86948 -/* 15839 */ MCD_OPC_Decode, 251, 31, 100, // Opcode: UMAX_ZI_S -/* 15843 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 15864 -/* 15848 */ MCD_OPC_CheckPredicate, 0, 183, 21, 1, // Skip to: 86948 -/* 15853 */ MCD_OPC_CheckField, 13, 1, 0, 176, 21, 1, // Skip to: 86948 -/* 15860 */ MCD_OPC_Decode, 225, 23, 99, // Opcode: SMIN_ZI_S -/* 15864 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 15885 -/* 15869 */ MCD_OPC_CheckPredicate, 0, 162, 21, 1, // Skip to: 86948 -/* 15874 */ MCD_OPC_CheckField, 13, 1, 0, 155, 21, 1, // Skip to: 86948 -/* 15881 */ MCD_OPC_Decode, 152, 32, 100, // Opcode: UMIN_ZI_S -/* 15885 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 15906 -/* 15890 */ MCD_OPC_CheckPredicate, 0, 141, 21, 1, // Skip to: 86948 -/* 15895 */ MCD_OPC_CheckField, 13, 1, 0, 134, 21, 1, // Skip to: 86948 -/* 15902 */ MCD_OPC_Decode, 152, 20, 99, // Opcode: MUL_ZI_S -/* 15906 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 15920 -/* 15911 */ MCD_OPC_CheckPredicate, 0, 120, 21, 1, // Skip to: 86948 -/* 15916 */ MCD_OPC_Decode, 198, 5, 109, // Opcode: DUP_ZI_S -/* 15920 */ MCD_OPC_FilterValue, 25, 111, 21, 1, // Skip to: 86948 -/* 15925 */ MCD_OPC_CheckPredicate, 0, 106, 21, 1, // Skip to: 86948 -/* 15930 */ MCD_OPC_CheckField, 13, 1, 0, 99, 21, 1, // Skip to: 86948 -/* 15937 */ MCD_OPC_Decode, 182, 9, 106, // Opcode: FDUP_ZI_S -/* 15941 */ MCD_OPC_FilterValue, 14, 100, 1, 0, // Skip to: 16302 -/* 15946 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 15949 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 16029 -/* 15954 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 15957 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 15993 -/* 15962 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 15965 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15979 -/* 15970 */ MCD_OPC_CheckPredicate, 0, 61, 21, 1, // Skip to: 86948 -/* 15975 */ MCD_OPC_Decode, 146, 4, 83, // Opcode: CMPGE_PPzZI_D -/* 15979 */ MCD_OPC_FilterValue, 1, 52, 21, 1, // Skip to: 86948 -/* 15984 */ MCD_OPC_CheckPredicate, 0, 47, 21, 1, // Skip to: 86948 -/* 15989 */ MCD_OPC_Decode, 211, 4, 83, // Opcode: CMPLT_PPzZI_D -/* 15993 */ MCD_OPC_FilterValue, 1, 38, 21, 1, // Skip to: 86948 -/* 15998 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 16001 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16015 -/* 16006 */ MCD_OPC_CheckPredicate, 0, 25, 21, 1, // Skip to: 86948 -/* 16011 */ MCD_OPC_Decode, 157, 4, 83, // Opcode: CMPGT_PPzZI_D -/* 16015 */ MCD_OPC_FilterValue, 1, 16, 21, 1, // Skip to: 86948 -/* 16020 */ MCD_OPC_CheckPredicate, 0, 11, 21, 1, // Skip to: 86948 -/* 16025 */ MCD_OPC_Decode, 190, 4, 83, // Opcode: CMPLE_PPzZI_D -/* 16029 */ MCD_OPC_FilterValue, 1, 125, 0, 0, // Skip to: 16159 -/* 16034 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 16037 */ MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 16109 -/* 16042 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 16045 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 16088 -/* 16050 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 16053 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16067 -/* 16058 */ MCD_OPC_CheckPredicate, 0, 229, 20, 1, // Skip to: 86948 -/* 16063 */ MCD_OPC_Decode, 203, 20, 84, // Opcode: ORRS_PPzPP -/* 16067 */ MCD_OPC_FilterValue, 1, 220, 20, 1, // Skip to: 86948 -/* 16072 */ MCD_OPC_CheckPredicate, 0, 215, 20, 1, // Skip to: 86948 -/* 16077 */ MCD_OPC_CheckField, 16, 4, 0, 208, 20, 1, // Skip to: 86948 -/* 16084 */ MCD_OPC_Decode, 212, 2, 85, // Opcode: BRKBS_PPzP -/* 16088 */ MCD_OPC_FilterValue, 1, 199, 20, 1, // Skip to: 86948 -/* 16093 */ MCD_OPC_CheckPredicate, 0, 194, 20, 1, // Skip to: 86948 -/* 16098 */ MCD_OPC_CheckField, 20, 1, 0, 187, 20, 1, // Skip to: 86948 -/* 16105 */ MCD_OPC_Decode, 187, 20, 84, // Opcode: NORS_PPzPP -/* 16109 */ MCD_OPC_FilterValue, 1, 178, 20, 1, // Skip to: 86948 -/* 16114 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 16117 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 16138 -/* 16122 */ MCD_OPC_CheckPredicate, 0, 165, 20, 1, // Skip to: 86948 -/* 16127 */ MCD_OPC_CheckField, 20, 1, 0, 158, 20, 1, // Skip to: 86948 -/* 16134 */ MCD_OPC_Decode, 195, 20, 84, // Opcode: ORNS_PPzPP -/* 16138 */ MCD_OPC_FilterValue, 1, 149, 20, 1, // Skip to: 86948 -/* 16143 */ MCD_OPC_CheckPredicate, 0, 144, 20, 1, // Skip to: 86948 -/* 16148 */ MCD_OPC_CheckField, 20, 1, 0, 137, 20, 1, // Skip to: 86948 -/* 16155 */ MCD_OPC_Decode, 173, 20, 84, // Opcode: NANDS_PPzPP -/* 16159 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 16209 -/* 16164 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 16167 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 16188 -/* 16172 */ MCD_OPC_CheckPredicate, 0, 115, 20, 1, // Skip to: 86948 -/* 16177 */ MCD_OPC_CheckField, 13, 1, 0, 108, 20, 1, // Skip to: 86948 -/* 16184 */ MCD_OPC_Decode, 135, 4, 83, // Opcode: CMPEQ_PPzZI_D -/* 16188 */ MCD_OPC_FilterValue, 1, 99, 20, 1, // Skip to: 86948 -/* 16193 */ MCD_OPC_CheckPredicate, 0, 94, 20, 1, // Skip to: 86948 -/* 16198 */ MCD_OPC_CheckField, 13, 1, 0, 87, 20, 1, // Skip to: 86948 -/* 16205 */ MCD_OPC_Decode, 218, 4, 83, // Opcode: CMPNE_PPzZI_D -/* 16209 */ MCD_OPC_FilterValue, 3, 78, 20, 1, // Skip to: 86948 -/* 16214 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 16217 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 16252 -/* 16222 */ MCD_OPC_CheckPredicate, 0, 65, 20, 1, // Skip to: 86948 -/* 16227 */ MCD_OPC_CheckField, 16, 5, 25, 58, 20, 1, // Skip to: 86948 -/* 16234 */ MCD_OPC_CheckField, 9, 1, 0, 51, 20, 1, // Skip to: 86948 -/* 16241 */ MCD_OPC_CheckField, 4, 1, 0, 44, 20, 1, // Skip to: 86948 -/* 16248 */ MCD_OPC_Decode, 250, 20, 88, // Opcode: PNEXT_D -/* 16252 */ MCD_OPC_FilterValue, 8, 35, 20, 1, // Skip to: 86948 -/* 16257 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 16260 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 16281 -/* 16265 */ MCD_OPC_CheckPredicate, 0, 22, 20, 1, // Skip to: 86948 -/* 16270 */ MCD_OPC_CheckField, 4, 1, 0, 15, 20, 1, // Skip to: 86948 -/* 16277 */ MCD_OPC_Decode, 172, 21, 89, // Opcode: PTRUE_D -/* 16281 */ MCD_OPC_FilterValue, 25, 6, 20, 1, // Skip to: 86948 -/* 16286 */ MCD_OPC_CheckPredicate, 0, 1, 20, 1, // Skip to: 86948 -/* 16291 */ MCD_OPC_CheckField, 4, 1, 0, 250, 19, 1, // Skip to: 86948 -/* 16298 */ MCD_OPC_Decode, 168, 21, 89, // Opcode: PTRUES_D -/* 16302 */ MCD_OPC_FilterValue, 15, 241, 19, 1, // Skip to: 86948 -/* 16307 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 16310 */ MCD_OPC_FilterValue, 0, 183, 0, 0, // Skip to: 16498 -/* 16315 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 16318 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 16354 -/* 16323 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 16326 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16340 -/* 16331 */ MCD_OPC_CheckPredicate, 0, 212, 19, 1, // Skip to: 86948 -/* 16336 */ MCD_OPC_Decode, 243, 34, 91, // Opcode: WHILELT_PWW_D -/* 16340 */ MCD_OPC_FilterValue, 1, 203, 19, 1, // Skip to: 86948 -/* 16345 */ MCD_OPC_CheckPredicate, 0, 198, 19, 1, // Skip to: 86948 -/* 16350 */ MCD_OPC_Decode, 219, 34, 91, // Opcode: WHILELE_PWW_D -/* 16354 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 16390 -/* 16359 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 16362 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16376 -/* 16367 */ MCD_OPC_CheckPredicate, 0, 176, 19, 1, // Skip to: 86948 -/* 16372 */ MCD_OPC_Decode, 227, 34, 91, // Opcode: WHILELO_PWW_D -/* 16376 */ MCD_OPC_FilterValue, 1, 167, 19, 1, // Skip to: 86948 -/* 16381 */ MCD_OPC_CheckPredicate, 0, 162, 19, 1, // Skip to: 86948 -/* 16386 */ MCD_OPC_Decode, 235, 34, 91, // Opcode: WHILELS_PWW_D -/* 16390 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 16426 -/* 16395 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 16398 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16412 -/* 16403 */ MCD_OPC_CheckPredicate, 0, 140, 19, 1, // Skip to: 86948 -/* 16408 */ MCD_OPC_Decode, 247, 34, 92, // Opcode: WHILELT_PXX_D -/* 16412 */ MCD_OPC_FilterValue, 1, 131, 19, 1, // Skip to: 86948 -/* 16417 */ MCD_OPC_CheckPredicate, 0, 126, 19, 1, // Skip to: 86948 -/* 16422 */ MCD_OPC_Decode, 223, 34, 92, // Opcode: WHILELE_PXX_D -/* 16426 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 16462 -/* 16431 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 16434 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16448 -/* 16439 */ MCD_OPC_CheckPredicate, 0, 104, 19, 1, // Skip to: 86948 -/* 16444 */ MCD_OPC_Decode, 231, 34, 92, // Opcode: WHILELO_PXX_D -/* 16448 */ MCD_OPC_FilterValue, 1, 95, 19, 1, // Skip to: 86948 -/* 16453 */ MCD_OPC_CheckPredicate, 0, 90, 19, 1, // Skip to: 86948 -/* 16458 */ MCD_OPC_Decode, 239, 34, 92, // Opcode: WHILELS_PXX_D -/* 16462 */ MCD_OPC_FilterValue, 8, 81, 19, 1, // Skip to: 86948 -/* 16467 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 16470 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16484 -/* 16475 */ MCD_OPC_CheckPredicate, 0, 68, 19, 1, // Skip to: 86948 -/* 16480 */ MCD_OPC_Decode, 170, 5, 110, // Opcode: CTERMEQ_XX -/* 16484 */ MCD_OPC_FilterValue, 16, 59, 19, 1, // Skip to: 86948 -/* 16489 */ MCD_OPC_CheckPredicate, 0, 54, 19, 1, // Skip to: 86948 -/* 16494 */ MCD_OPC_Decode, 172, 5, 110, // Opcode: CTERMNE_XX -/* 16498 */ MCD_OPC_FilterValue, 2, 40, 1, 0, // Skip to: 16799 -/* 16503 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 16506 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 16527 -/* 16511 */ MCD_OPC_CheckPredicate, 0, 32, 19, 1, // Skip to: 86948 -/* 16516 */ MCD_OPC_CheckField, 9, 1, 0, 25, 19, 1, // Skip to: 86948 -/* 16523 */ MCD_OPC_Decode, 249, 4, 93, // Opcode: CNTP_XPP_D -/* 16527 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 16577 -/* 16532 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 16535 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16549 -/* 16540 */ MCD_OPC_CheckPredicate, 0, 3, 19, 1, // Skip to: 86948 -/* 16545 */ MCD_OPC_Decode, 141, 25, 103, // Opcode: SQINCP_ZP_D -/* 16549 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16563 -/* 16554 */ MCD_OPC_CheckPredicate, 0, 245, 18, 1, // Skip to: 86948 -/* 16559 */ MCD_OPC_Decode, 134, 25, 94, // Opcode: SQINCP_XPWd_D -/* 16563 */ MCD_OPC_FilterValue, 6, 236, 18, 1, // Skip to: 86948 -/* 16568 */ MCD_OPC_CheckPredicate, 0, 231, 18, 1, // Skip to: 86948 -/* 16573 */ MCD_OPC_Decode, 138, 25, 94, // Opcode: SQINCP_XP_D -/* 16577 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 16627 -/* 16582 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 16585 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16599 -/* 16590 */ MCD_OPC_CheckPredicate, 0, 209, 18, 1, // Skip to: 86948 -/* 16595 */ MCD_OPC_Decode, 132, 33, 103, // Opcode: UQINCP_ZP_D -/* 16599 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16613 -/* 16604 */ MCD_OPC_CheckPredicate, 0, 195, 18, 1, // Skip to: 86948 -/* 16609 */ MCD_OPC_Decode, 253, 32, 96, // Opcode: UQINCP_WP_D -/* 16613 */ MCD_OPC_FilterValue, 6, 186, 18, 1, // Skip to: 86948 -/* 16618 */ MCD_OPC_CheckPredicate, 0, 181, 18, 1, // Skip to: 86948 -/* 16623 */ MCD_OPC_Decode, 129, 33, 94, // Opcode: UQINCP_XP_D -/* 16627 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 16677 -/* 16632 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 16635 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16649 -/* 16640 */ MCD_OPC_CheckPredicate, 0, 159, 18, 1, // Skip to: 86948 -/* 16645 */ MCD_OPC_Decode, 199, 24, 103, // Opcode: SQDECP_ZP_D -/* 16649 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16663 -/* 16654 */ MCD_OPC_CheckPredicate, 0, 145, 18, 1, // Skip to: 86948 -/* 16659 */ MCD_OPC_Decode, 192, 24, 94, // Opcode: SQDECP_XPWd_D -/* 16663 */ MCD_OPC_FilterValue, 6, 136, 18, 1, // Skip to: 86948 -/* 16668 */ MCD_OPC_CheckPredicate, 0, 131, 18, 1, // Skip to: 86948 -/* 16673 */ MCD_OPC_Decode, 196, 24, 94, // Opcode: SQDECP_XP_D -/* 16677 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 16727 -/* 16682 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 16685 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16699 -/* 16690 */ MCD_OPC_CheckPredicate, 0, 109, 18, 1, // Skip to: 86948 -/* 16695 */ MCD_OPC_Decode, 238, 32, 103, // Opcode: UQDECP_ZP_D -/* 16699 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16713 -/* 16704 */ MCD_OPC_CheckPredicate, 0, 95, 18, 1, // Skip to: 86948 -/* 16709 */ MCD_OPC_Decode, 231, 32, 96, // Opcode: UQDECP_WP_D -/* 16713 */ MCD_OPC_FilterValue, 6, 86, 18, 1, // Skip to: 86948 -/* 16718 */ MCD_OPC_CheckPredicate, 0, 81, 18, 1, // Skip to: 86948 -/* 16723 */ MCD_OPC_Decode, 235, 32, 94, // Opcode: UQDECP_XP_D -/* 16727 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 16763 -/* 16732 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 16735 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16749 -/* 16740 */ MCD_OPC_CheckPredicate, 0, 59, 18, 1, // Skip to: 86948 -/* 16745 */ MCD_OPC_Decode, 253, 13, 103, // Opcode: INCP_ZP_D -/* 16749 */ MCD_OPC_FilterValue, 4, 50, 18, 1, // Skip to: 86948 -/* 16754 */ MCD_OPC_CheckPredicate, 0, 45, 18, 1, // Skip to: 86948 -/* 16759 */ MCD_OPC_Decode, 250, 13, 94, // Opcode: INCP_XP_D -/* 16763 */ MCD_OPC_FilterValue, 13, 36, 18, 1, // Skip to: 86948 -/* 16768 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... -/* 16771 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16785 -/* 16776 */ MCD_OPC_CheckPredicate, 0, 23, 18, 1, // Skip to: 86948 -/* 16781 */ MCD_OPC_Decode, 186, 5, 103, // Opcode: DECP_ZP_D -/* 16785 */ MCD_OPC_FilterValue, 4, 14, 18, 1, // Skip to: 86948 -/* 16790 */ MCD_OPC_CheckPredicate, 0, 9, 18, 1, // Skip to: 86948 -/* 16795 */ MCD_OPC_Decode, 183, 5, 94, // Opcode: DECP_XP_D -/* 16799 */ MCD_OPC_FilterValue, 3, 0, 18, 1, // Skip to: 86948 -/* 16804 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 16807 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16821 -/* 16812 */ MCD_OPC_CheckPredicate, 0, 243, 17, 1, // Skip to: 86948 -/* 16817 */ MCD_OPC_Decode, 182, 1, 111, // Opcode: ADD_ZI_D -/* 16821 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 16835 -/* 16826 */ MCD_OPC_CheckPredicate, 0, 229, 17, 1, // Skip to: 86948 -/* 16831 */ MCD_OPC_Decode, 244, 29, 111, // Opcode: SUB_ZI_D -/* 16835 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 16849 -/* 16840 */ MCD_OPC_CheckPredicate, 0, 215, 17, 1, // Skip to: 86948 -/* 16845 */ MCD_OPC_Decode, 218, 29, 111, // Opcode: SUBR_ZI_D -/* 16849 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16863 -/* 16854 */ MCD_OPC_CheckPredicate, 0, 201, 17, 1, // Skip to: 86948 -/* 16859 */ MCD_OPC_Decode, 165, 24, 111, // Opcode: SQADD_ZI_D -/* 16863 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 16877 -/* 16868 */ MCD_OPC_CheckPredicate, 0, 187, 17, 1, // Skip to: 86948 -/* 16873 */ MCD_OPC_Decode, 204, 32, 111, // Opcode: UQADD_ZI_D -/* 16877 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 16891 -/* 16882 */ MCD_OPC_CheckPredicate, 0, 173, 17, 1, // Skip to: 86948 -/* 16887 */ MCD_OPC_Decode, 147, 26, 111, // Opcode: SQSUB_ZI_D -/* 16891 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 16905 -/* 16896 */ MCD_OPC_CheckPredicate, 0, 159, 17, 1, // Skip to: 86948 -/* 16901 */ MCD_OPC_Decode, 190, 33, 111, // Opcode: UQSUB_ZI_D -/* 16905 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 16926 -/* 16910 */ MCD_OPC_CheckPredicate, 0, 145, 17, 1, // Skip to: 86948 -/* 16915 */ MCD_OPC_CheckField, 13, 1, 0, 138, 17, 1, // Skip to: 86948 -/* 16922 */ MCD_OPC_Decode, 193, 23, 99, // Opcode: SMAX_ZI_D -/* 16926 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 16947 -/* 16931 */ MCD_OPC_CheckPredicate, 0, 124, 17, 1, // Skip to: 86948 -/* 16936 */ MCD_OPC_CheckField, 13, 1, 0, 117, 17, 1, // Skip to: 86948 -/* 16943 */ MCD_OPC_Decode, 249, 31, 100, // Opcode: UMAX_ZI_D -/* 16947 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 16968 -/* 16952 */ MCD_OPC_CheckPredicate, 0, 103, 17, 1, // Skip to: 86948 -/* 16957 */ MCD_OPC_CheckField, 13, 1, 0, 96, 17, 1, // Skip to: 86948 -/* 16964 */ MCD_OPC_Decode, 223, 23, 99, // Opcode: SMIN_ZI_D -/* 16968 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 16989 -/* 16973 */ MCD_OPC_CheckPredicate, 0, 82, 17, 1, // Skip to: 86948 -/* 16978 */ MCD_OPC_CheckField, 13, 1, 0, 75, 17, 1, // Skip to: 86948 -/* 16985 */ MCD_OPC_Decode, 150, 32, 100, // Opcode: UMIN_ZI_D -/* 16989 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 17010 -/* 16994 */ MCD_OPC_CheckPredicate, 0, 61, 17, 1, // Skip to: 86948 -/* 16999 */ MCD_OPC_CheckField, 13, 1, 0, 54, 17, 1, // Skip to: 86948 -/* 17006 */ MCD_OPC_Decode, 150, 20, 99, // Opcode: MUL_ZI_D -/* 17010 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 17024 -/* 17015 */ MCD_OPC_CheckPredicate, 0, 40, 17, 1, // Skip to: 86948 -/* 17020 */ MCD_OPC_Decode, 196, 5, 112, // Opcode: DUP_ZI_D -/* 17024 */ MCD_OPC_FilterValue, 25, 31, 17, 1, // Skip to: 86948 -/* 17029 */ MCD_OPC_CheckPredicate, 0, 26, 17, 1, // Skip to: 86948 -/* 17034 */ MCD_OPC_CheckField, 13, 1, 0, 19, 17, 1, // Skip to: 86948 -/* 17041 */ MCD_OPC_Decode, 180, 9, 106, // Opcode: FDUP_ZI_D -/* 17045 */ MCD_OPC_FilterValue, 2, 147, 0, 0, // Skip to: 17197 -/* 17050 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 17053 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 17089 -/* 17058 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 17061 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17075 -/* 17066 */ MCD_OPC_CheckPredicate, 0, 245, 16, 1, // Skip to: 86948 -/* 17071 */ MCD_OPC_Decode, 228, 22, 113, // Opcode: SDOT_ZZZ_S -/* 17075 */ MCD_OPC_FilterValue, 1, 236, 16, 1, // Skip to: 86948 -/* 17080 */ MCD_OPC_CheckPredicate, 0, 231, 16, 1, // Skip to: 86948 -/* 17085 */ MCD_OPC_Decode, 215, 31, 113, // Opcode: UDOT_ZZZ_S -/* 17089 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 17125 -/* 17094 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 17097 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17111 -/* 17102 */ MCD_OPC_CheckPredicate, 0, 209, 16, 1, // Skip to: 86948 -/* 17107 */ MCD_OPC_Decode, 226, 22, 114, // Opcode: SDOT_ZZZI_S -/* 17111 */ MCD_OPC_FilterValue, 1, 200, 16, 1, // Skip to: 86948 -/* 17116 */ MCD_OPC_CheckPredicate, 0, 195, 16, 1, // Skip to: 86948 -/* 17121 */ MCD_OPC_Decode, 213, 31, 114, // Opcode: UDOT_ZZZI_S -/* 17125 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 17161 -/* 17130 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 17133 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17147 -/* 17138 */ MCD_OPC_CheckPredicate, 0, 173, 16, 1, // Skip to: 86948 -/* 17143 */ MCD_OPC_Decode, 227, 22, 113, // Opcode: SDOT_ZZZ_D -/* 17147 */ MCD_OPC_FilterValue, 1, 164, 16, 1, // Skip to: 86948 -/* 17152 */ MCD_OPC_CheckPredicate, 0, 159, 16, 1, // Skip to: 86948 -/* 17157 */ MCD_OPC_Decode, 214, 31, 113, // Opcode: UDOT_ZZZ_D -/* 17161 */ MCD_OPC_FilterValue, 7, 150, 16, 1, // Skip to: 86948 -/* 17166 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 17169 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17183 -/* 17174 */ MCD_OPC_CheckPredicate, 0, 137, 16, 1, // Skip to: 86948 -/* 17179 */ MCD_OPC_Decode, 225, 22, 115, // Opcode: SDOT_ZZZI_D -/* 17183 */ MCD_OPC_FilterValue, 1, 128, 16, 1, // Skip to: 86948 -/* 17188 */ MCD_OPC_CheckPredicate, 0, 123, 16, 1, // Skip to: 86948 -/* 17193 */ MCD_OPC_Decode, 212, 31, 115, // Opcode: UDOT_ZZZI_D -/* 17197 */ MCD_OPC_FilterValue, 3, 6, 17, 0, // Skip to: 21560 -/* 17202 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 17205 */ MCD_OPC_FilterValue, 0, 110, 0, 0, // Skip to: 17320 -/* 17210 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 17213 */ MCD_OPC_FilterValue, 0, 74, 0, 0, // Skip to: 17292 -/* 17218 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 17221 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 17242 -/* 17226 */ MCD_OPC_CheckPredicate, 0, 85, 16, 1, // Skip to: 86948 -/* 17231 */ MCD_OPC_CheckField, 22, 1, 1, 78, 16, 1, // Skip to: 86948 -/* 17238 */ MCD_OPC_Decode, 156, 7, 116, // Opcode: FCMLA_ZPmZZ_H -/* 17242 */ MCD_OPC_FilterValue, 1, 69, 16, 1, // Skip to: 86948 -/* 17247 */ MCD_OPC_ExtractField, 10, 5, // Inst{14-10} ... -/* 17250 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17264 -/* 17255 */ MCD_OPC_CheckPredicate, 0, 56, 16, 1, // Skip to: 86948 -/* 17260 */ MCD_OPC_Decode, 181, 10, 117, // Opcode: FMLA_ZZZI_H -/* 17264 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17278 -/* 17269 */ MCD_OPC_CheckPredicate, 0, 42, 16, 1, // Skip to: 86948 -/* 17274 */ MCD_OPC_Decode, 200, 10, 117, // Opcode: FMLS_ZZZI_H -/* 17278 */ MCD_OPC_FilterValue, 8, 33, 16, 1, // Skip to: 86948 -/* 17283 */ MCD_OPC_CheckPredicate, 0, 28, 16, 1, // Skip to: 86948 -/* 17288 */ MCD_OPC_Decode, 146, 11, 118, // Opcode: FMUL_ZZZI_H -/* 17292 */ MCD_OPC_FilterValue, 1, 19, 16, 1, // Skip to: 86948 -/* 17297 */ MCD_OPC_CheckPredicate, 0, 14, 16, 1, // Skip to: 86948 -/* 17302 */ MCD_OPC_CheckField, 17, 6, 32, 7, 16, 1, // Skip to: 86948 -/* 17309 */ MCD_OPC_CheckField, 13, 2, 0, 0, 16, 1, // Skip to: 86948 -/* 17316 */ MCD_OPC_Decode, 204, 6, 119, // Opcode: FCADD_ZPmZ_H -/* 17320 */ MCD_OPC_FilterValue, 1, 5, 1, 0, // Skip to: 17586 -/* 17325 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 17328 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 17378 -/* 17333 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 17336 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17350 -/* 17341 */ MCD_OPC_CheckPredicate, 0, 226, 15, 1, // Skip to: 86948 -/* 17346 */ MCD_OPC_Decode, 157, 7, 116, // Opcode: FCMLA_ZPmZZ_S -/* 17350 */ MCD_OPC_FilterValue, 1, 217, 15, 1, // Skip to: 86948 -/* 17355 */ MCD_OPC_CheckPredicate, 0, 212, 15, 1, // Skip to: 86948 -/* 17360 */ MCD_OPC_CheckField, 17, 4, 0, 205, 15, 1, // Skip to: 86948 -/* 17367 */ MCD_OPC_CheckField, 13, 2, 0, 198, 15, 1, // Skip to: 86948 -/* 17374 */ MCD_OPC_Decode, 205, 6, 119, // Opcode: FCADD_ZPmZ_S -/* 17378 */ MCD_OPC_FilterValue, 1, 74, 0, 0, // Skip to: 17457 -/* 17383 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17386 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 17422 -/* 17391 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 17394 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17408 -/* 17399 */ MCD_OPC_CheckPredicate, 0, 168, 15, 1, // Skip to: 86948 -/* 17404 */ MCD_OPC_Decode, 182, 10, 114, // Opcode: FMLA_ZZZI_S -/* 17408 */ MCD_OPC_FilterValue, 1, 159, 15, 1, // Skip to: 86948 -/* 17413 */ MCD_OPC_CheckPredicate, 0, 154, 15, 1, // Skip to: 86948 -/* 17418 */ MCD_OPC_Decode, 201, 10, 114, // Opcode: FMLS_ZZZI_S -/* 17422 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17436 -/* 17427 */ MCD_OPC_CheckPredicate, 0, 140, 15, 1, // Skip to: 86948 -/* 17432 */ MCD_OPC_Decode, 158, 7, 120, // Opcode: FCMLA_ZZZI_H -/* 17436 */ MCD_OPC_FilterValue, 2, 131, 15, 1, // Skip to: 86948 -/* 17441 */ MCD_OPC_CheckPredicate, 0, 126, 15, 1, // Skip to: 86948 -/* 17446 */ MCD_OPC_CheckField, 10, 2, 0, 119, 15, 1, // Skip to: 86948 -/* 17453 */ MCD_OPC_Decode, 147, 11, 121, // Opcode: FMUL_ZZZI_S -/* 17457 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 17507 -/* 17462 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 17465 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17479 -/* 17470 */ MCD_OPC_CheckPredicate, 0, 97, 15, 1, // Skip to: 86948 -/* 17475 */ MCD_OPC_Decode, 155, 7, 116, // Opcode: FCMLA_ZPmZZ_D -/* 17479 */ MCD_OPC_FilterValue, 1, 88, 15, 1, // Skip to: 86948 -/* 17484 */ MCD_OPC_CheckPredicate, 0, 83, 15, 1, // Skip to: 86948 -/* 17489 */ MCD_OPC_CheckField, 17, 4, 0, 76, 15, 1, // Skip to: 86948 -/* 17496 */ MCD_OPC_CheckField, 13, 2, 0, 69, 15, 1, // Skip to: 86948 -/* 17503 */ MCD_OPC_Decode, 203, 6, 119, // Opcode: FCADD_ZPmZ_D -/* 17507 */ MCD_OPC_FilterValue, 3, 60, 15, 1, // Skip to: 86948 -/* 17512 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17515 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 17551 -/* 17520 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 17523 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17537 -/* 17528 */ MCD_OPC_CheckPredicate, 0, 39, 15, 1, // Skip to: 86948 -/* 17533 */ MCD_OPC_Decode, 180, 10, 115, // Opcode: FMLA_ZZZI_D -/* 17537 */ MCD_OPC_FilterValue, 1, 30, 15, 1, // Skip to: 86948 -/* 17542 */ MCD_OPC_CheckPredicate, 0, 25, 15, 1, // Skip to: 86948 -/* 17547 */ MCD_OPC_Decode, 199, 10, 115, // Opcode: FMLS_ZZZI_D -/* 17551 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17565 -/* 17556 */ MCD_OPC_CheckPredicate, 0, 11, 15, 1, // Skip to: 86948 -/* 17561 */ MCD_OPC_Decode, 159, 7, 122, // Opcode: FCMLA_ZZZI_S -/* 17565 */ MCD_OPC_FilterValue, 2, 2, 15, 1, // Skip to: 86948 -/* 17570 */ MCD_OPC_CheckPredicate, 0, 253, 14, 1, // Skip to: 86948 -/* 17575 */ MCD_OPC_CheckField, 10, 2, 0, 246, 14, 1, // Skip to: 86948 -/* 17582 */ MCD_OPC_Decode, 145, 11, 123, // Opcode: FMUL_ZZZI_D -/* 17586 */ MCD_OPC_FilterValue, 2, 73, 5, 0, // Skip to: 18944 -/* 17591 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 17594 */ MCD_OPC_FilterValue, 0, 109, 0, 0, // Skip to: 17708 -/* 17599 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 17602 */ MCD_OPC_FilterValue, 2, 87, 0, 0, // Skip to: 17694 -/* 17607 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 17610 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17624 -/* 17615 */ MCD_OPC_CheckPredicate, 0, 208, 14, 1, // Skip to: 86948 -/* 17620 */ MCD_OPC_Decode, 196, 6, 27, // Opcode: FADD_ZZZ_H -/* 17624 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17638 -/* 17629 */ MCD_OPC_CheckPredicate, 0, 194, 14, 1, // Skip to: 86948 -/* 17634 */ MCD_OPC_Decode, 225, 12, 27, // Opcode: FSUB_ZZZ_H -/* 17638 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 17652 -/* 17643 */ MCD_OPC_CheckPredicate, 0, 180, 14, 1, // Skip to: 86948 -/* 17648 */ MCD_OPC_Decode, 149, 11, 27, // Opcode: FMUL_ZZZ_H -/* 17652 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 17666 -/* 17657 */ MCD_OPC_CheckPredicate, 0, 166, 14, 1, // Skip to: 86948 -/* 17662 */ MCD_OPC_Decode, 236, 12, 27, // Opcode: FTSMUL_ZZZ_H -/* 17666 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 17680 -/* 17671 */ MCD_OPC_CheckPredicate, 0, 152, 14, 1, // Skip to: 86948 -/* 17676 */ MCD_OPC_Decode, 211, 11, 27, // Opcode: FRECPS_ZZZ_H -/* 17680 */ MCD_OPC_FilterValue, 7, 143, 14, 1, // Skip to: 86948 -/* 17685 */ MCD_OPC_CheckPredicate, 0, 138, 14, 1, // Skip to: 86948 -/* 17690 */ MCD_OPC_Decode, 188, 12, 27, // Opcode: FRSQRTS_ZZZ_H -/* 17694 */ MCD_OPC_FilterValue, 3, 129, 14, 1, // Skip to: 86948 -/* 17699 */ MCD_OPC_CheckPredicate, 0, 124, 14, 1, // Skip to: 86948 -/* 17704 */ MCD_OPC_Decode, 178, 10, 6, // Opcode: FMLA_ZPmZZ_H -/* 17708 */ MCD_OPC_FilterValue, 1, 9, 1, 0, // Skip to: 17978 -/* 17713 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 17716 */ MCD_OPC_FilterValue, 2, 243, 0, 0, // Skip to: 17964 -/* 17721 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 17724 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17738 -/* 17729 */ MCD_OPC_CheckPredicate, 0, 94, 14, 1, // Skip to: 86948 -/* 17734 */ MCD_OPC_Decode, 187, 6, 3, // Opcode: FADDV_VPZ_H -/* 17738 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 17752 -/* 17743 */ MCD_OPC_CheckPredicate, 0, 80, 14, 1, // Skip to: 86948 -/* 17748 */ MCD_OPC_Decode, 207, 9, 3, // Opcode: FMAXNMV_VPZ_H -/* 17752 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 17766 -/* 17757 */ MCD_OPC_CheckPredicate, 0, 66, 14, 1, // Skip to: 86948 -/* 17762 */ MCD_OPC_Decode, 135, 10, 3, // Opcode: FMINNMV_VPZ_H -/* 17766 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 17780 -/* 17771 */ MCD_OPC_CheckPredicate, 0, 52, 14, 1, // Skip to: 86948 -/* 17776 */ MCD_OPC_Decode, 233, 9, 3, // Opcode: FMAXV_VPZ_H -/* 17780 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 17794 -/* 17785 */ MCD_OPC_CheckPredicate, 0, 38, 14, 1, // Skip to: 86948 -/* 17790 */ MCD_OPC_Decode, 161, 10, 3, // Opcode: FMINV_VPZ_H -/* 17794 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 17815 -/* 17799 */ MCD_OPC_CheckPredicate, 0, 24, 14, 1, // Skip to: 86948 -/* 17804 */ MCD_OPC_CheckField, 10, 3, 4, 17, 14, 1, // Skip to: 86948 -/* 17811 */ MCD_OPC_Decode, 197, 11, 38, // Opcode: FRECPE_ZZ_H -/* 17815 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 17836 -/* 17820 */ MCD_OPC_CheckPredicate, 0, 3, 14, 1, // Skip to: 86948 -/* 17825 */ MCD_OPC_CheckField, 10, 3, 4, 252, 13, 1, // Skip to: 86948 -/* 17832 */ MCD_OPC_Decode, 174, 12, 38, // Opcode: FRSQRTE_ZZ_H -/* 17836 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 17872 -/* 17841 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 17844 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17858 -/* 17849 */ MCD_OPC_CheckPredicate, 0, 230, 13, 1, // Skip to: 86948 -/* 17854 */ MCD_OPC_Decode, 243, 6, 124, // Opcode: FCMGE_PPzZ0_H -/* 17858 */ MCD_OPC_FilterValue, 1, 221, 13, 1, // Skip to: 86948 -/* 17863 */ MCD_OPC_CheckPredicate, 0, 216, 13, 1, // Skip to: 86948 -/* 17868 */ MCD_OPC_Decode, 137, 7, 124, // Opcode: FCMGT_PPzZ0_H -/* 17872 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 17908 -/* 17877 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 17880 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17894 -/* 17885 */ MCD_OPC_CheckPredicate, 0, 194, 13, 1, // Skip to: 86948 -/* 17890 */ MCD_OPC_Decode, 180, 7, 124, // Opcode: FCMLT_PPzZ0_H -/* 17894 */ MCD_OPC_FilterValue, 1, 185, 13, 1, // Skip to: 86948 -/* 17899 */ MCD_OPC_CheckPredicate, 0, 180, 13, 1, // Skip to: 86948 -/* 17904 */ MCD_OPC_Decode, 169, 7, 124, // Opcode: FCMLE_PPzZ0_H -/* 17908 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 17929 -/* 17913 */ MCD_OPC_CheckPredicate, 0, 166, 13, 1, // Skip to: 86948 -/* 17918 */ MCD_OPC_CheckField, 4, 1, 0, 159, 13, 1, // Skip to: 86948 -/* 17925 */ MCD_OPC_Decode, 221, 6, 124, // Opcode: FCMEQ_PPzZ0_H -/* 17929 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 17950 -/* 17934 */ MCD_OPC_CheckPredicate, 0, 145, 13, 1, // Skip to: 86948 -/* 17939 */ MCD_OPC_CheckField, 4, 1, 0, 138, 13, 1, // Skip to: 86948 -/* 17946 */ MCD_OPC_Decode, 191, 7, 124, // Opcode: FCMNE_PPzZ0_H -/* 17950 */ MCD_OPC_FilterValue, 24, 129, 13, 1, // Skip to: 86948 -/* 17955 */ MCD_OPC_CheckPredicate, 0, 124, 13, 1, // Skip to: 86948 -/* 17960 */ MCD_OPC_Decode, 173, 6, 67, // Opcode: FADDA_VPZ_H -/* 17964 */ MCD_OPC_FilterValue, 3, 115, 13, 1, // Skip to: 86948 -/* 17969 */ MCD_OPC_CheckPredicate, 0, 110, 13, 1, // Skip to: 86948 -/* 17974 */ MCD_OPC_Decode, 197, 10, 6, // Opcode: FMLS_ZPmZZ_H -/* 17978 */ MCD_OPC_FilterValue, 2, 53, 0, 0, // Skip to: 18036 -/* 17983 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 17986 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 18022 -/* 17991 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 17994 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18008 -/* 17999 */ MCD_OPC_CheckPredicate, 0, 80, 13, 1, // Skip to: 86948 -/* 18004 */ MCD_OPC_Decode, 246, 6, 81, // Opcode: FCMGE_PPzZZ_H -/* 18008 */ MCD_OPC_FilterValue, 1, 71, 13, 1, // Skip to: 86948 -/* 18013 */ MCD_OPC_CheckPredicate, 0, 66, 13, 1, // Skip to: 86948 -/* 18018 */ MCD_OPC_Decode, 140, 7, 81, // Opcode: FCMGT_PPzZZ_H -/* 18022 */ MCD_OPC_FilterValue, 3, 57, 13, 1, // Skip to: 86948 -/* 18027 */ MCD_OPC_CheckPredicate, 0, 52, 13, 1, // Skip to: 86948 -/* 18032 */ MCD_OPC_Decode, 182, 11, 6, // Opcode: FNMLA_ZPmZZ_H -/* 18036 */ MCD_OPC_FilterValue, 3, 53, 0, 0, // Skip to: 18094 -/* 18041 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 18044 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 18080 -/* 18049 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 18052 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18066 -/* 18057 */ MCD_OPC_CheckPredicate, 0, 22, 13, 1, // Skip to: 86948 -/* 18062 */ MCD_OPC_Decode, 224, 6, 81, // Opcode: FCMEQ_PPzZZ_H -/* 18066 */ MCD_OPC_FilterValue, 1, 13, 13, 1, // Skip to: 86948 -/* 18071 */ MCD_OPC_CheckPredicate, 0, 8, 13, 1, // Skip to: 86948 -/* 18076 */ MCD_OPC_Decode, 194, 7, 81, // Opcode: FCMNE_PPzZZ_H -/* 18080 */ MCD_OPC_FilterValue, 3, 255, 12, 1, // Skip to: 86948 -/* 18085 */ MCD_OPC_CheckPredicate, 0, 250, 12, 1, // Skip to: 86948 -/* 18090 */ MCD_OPC_Decode, 185, 11, 6, // Opcode: FNMLS_ZPmZZ_H -/* 18094 */ MCD_OPC_FilterValue, 4, 164, 1, 0, // Skip to: 18519 -/* 18099 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 18102 */ MCD_OPC_FilterValue, 2, 142, 1, 0, // Skip to: 18505 -/* 18107 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... -/* 18110 */ MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 18230 -/* 18115 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... -/* 18118 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18132 -/* 18123 */ MCD_OPC_CheckPredicate, 0, 212, 12, 1, // Skip to: 86948 -/* 18128 */ MCD_OPC_Decode, 193, 6, 0, // Opcode: FADD_ZPmZ_H -/* 18132 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18146 -/* 18137 */ MCD_OPC_CheckPredicate, 0, 198, 12, 1, // Skip to: 86948 -/* 18142 */ MCD_OPC_Decode, 222, 12, 0, // Opcode: FSUB_ZPmZ_H -/* 18146 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 18160 -/* 18151 */ MCD_OPC_CheckPredicate, 0, 184, 12, 1, // Skip to: 86948 -/* 18156 */ MCD_OPC_Decode, 143, 11, 0, // Opcode: FMUL_ZPmZ_H -/* 18160 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 18174 -/* 18165 */ MCD_OPC_CheckPredicate, 0, 170, 12, 1, // Skip to: 86948 -/* 18170 */ MCD_OPC_Decode, 215, 12, 0, // Opcode: FSUBR_ZPmZ_H -/* 18174 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 18188 -/* 18179 */ MCD_OPC_CheckPredicate, 0, 156, 12, 1, // Skip to: 86948 -/* 18184 */ MCD_OPC_Decode, 216, 9, 0, // Opcode: FMAXNM_ZPmZ_H -/* 18188 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 18202 -/* 18193 */ MCD_OPC_CheckPredicate, 0, 142, 12, 1, // Skip to: 86948 -/* 18198 */ MCD_OPC_Decode, 144, 10, 0, // Opcode: FMINNM_ZPmZ_H -/* 18202 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 18216 -/* 18207 */ MCD_OPC_CheckPredicate, 0, 128, 12, 1, // Skip to: 86948 -/* 18212 */ MCD_OPC_Decode, 242, 9, 0, // Opcode: FMAX_ZPmZ_H -/* 18216 */ MCD_OPC_FilterValue, 7, 119, 12, 1, // Skip to: 86948 -/* 18221 */ MCD_OPC_CheckPredicate, 0, 114, 12, 1, // Skip to: 86948 -/* 18226 */ MCD_OPC_Decode, 170, 10, 0, // Opcode: FMIN_ZPmZ_H -/* 18230 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 18308 -/* 18235 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... -/* 18238 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18252 -/* 18243 */ MCD_OPC_CheckPredicate, 0, 92, 12, 1, // Skip to: 86948 -/* 18248 */ MCD_OPC_Decode, 132, 6, 0, // Opcode: FABD_ZPmZ_H -/* 18252 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18266 -/* 18257 */ MCD_OPC_CheckPredicate, 0, 78, 12, 1, // Skip to: 86948 -/* 18262 */ MCD_OPC_Decode, 196, 12, 0, // Opcode: FSCALE_ZPmZ_H -/* 18266 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 18280 -/* 18271 */ MCD_OPC_CheckPredicate, 0, 64, 12, 1, // Skip to: 86948 -/* 18276 */ MCD_OPC_Decode, 252, 10, 0, // Opcode: FMULX_ZPmZ_H -/* 18280 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 18294 -/* 18285 */ MCD_OPC_CheckPredicate, 0, 50, 12, 1, // Skip to: 86948 -/* 18290 */ MCD_OPC_Decode, 169, 9, 0, // Opcode: FDIVR_ZPmZ_H -/* 18294 */ MCD_OPC_FilterValue, 5, 41, 12, 1, // Skip to: 86948 -/* 18299 */ MCD_OPC_CheckPredicate, 0, 36, 12, 1, // Skip to: 86948 -/* 18304 */ MCD_OPC_Decode, 173, 9, 0, // Opcode: FDIV_ZPmZ_H -/* 18308 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 18329 -/* 18313 */ MCD_OPC_CheckPredicate, 0, 22, 12, 1, // Skip to: 86948 -/* 18318 */ MCD_OPC_CheckField, 10, 3, 0, 15, 12, 1, // Skip to: 86948 -/* 18325 */ MCD_OPC_Decode, 233, 12, 125, // Opcode: FTMAD_ZZI_H -/* 18329 */ MCD_OPC_FilterValue, 3, 6, 12, 1, // Skip to: 86948 -/* 18334 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... -/* 18337 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 18358 -/* 18342 */ MCD_OPC_CheckPredicate, 0, 249, 11, 1, // Skip to: 86948 -/* 18347 */ MCD_OPC_CheckField, 6, 4, 0, 242, 11, 1, // Skip to: 86948 -/* 18354 */ MCD_OPC_Decode, 190, 6, 126, // Opcode: FADD_ZPmI_H -/* 18358 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 18379 -/* 18363 */ MCD_OPC_CheckPredicate, 0, 228, 11, 1, // Skip to: 86948 -/* 18368 */ MCD_OPC_CheckField, 6, 4, 0, 221, 11, 1, // Skip to: 86948 -/* 18375 */ MCD_OPC_Decode, 219, 12, 126, // Opcode: FSUB_ZPmI_H -/* 18379 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 18400 -/* 18384 */ MCD_OPC_CheckPredicate, 0, 207, 11, 1, // Skip to: 86948 -/* 18389 */ MCD_OPC_CheckField, 6, 4, 0, 200, 11, 1, // Skip to: 86948 -/* 18396 */ MCD_OPC_Decode, 140, 11, 126, // Opcode: FMUL_ZPmI_H -/* 18400 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 18421 -/* 18405 */ MCD_OPC_CheckPredicate, 0, 186, 11, 1, // Skip to: 86948 -/* 18410 */ MCD_OPC_CheckField, 6, 4, 0, 179, 11, 1, // Skip to: 86948 -/* 18417 */ MCD_OPC_Decode, 212, 12, 126, // Opcode: FSUBR_ZPmI_H -/* 18421 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 18442 -/* 18426 */ MCD_OPC_CheckPredicate, 0, 165, 11, 1, // Skip to: 86948 -/* 18431 */ MCD_OPC_CheckField, 6, 4, 0, 158, 11, 1, // Skip to: 86948 -/* 18438 */ MCD_OPC_Decode, 213, 9, 126, // Opcode: FMAXNM_ZPmI_H -/* 18442 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 18463 -/* 18447 */ MCD_OPC_CheckPredicate, 0, 144, 11, 1, // Skip to: 86948 -/* 18452 */ MCD_OPC_CheckField, 6, 4, 0, 137, 11, 1, // Skip to: 86948 -/* 18459 */ MCD_OPC_Decode, 141, 10, 126, // Opcode: FMINNM_ZPmI_H -/* 18463 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 18484 -/* 18468 */ MCD_OPC_CheckPredicate, 0, 123, 11, 1, // Skip to: 86948 -/* 18473 */ MCD_OPC_CheckField, 6, 4, 0, 116, 11, 1, // Skip to: 86948 -/* 18480 */ MCD_OPC_Decode, 239, 9, 126, // Opcode: FMAX_ZPmI_H -/* 18484 */ MCD_OPC_FilterValue, 7, 107, 11, 1, // Skip to: 86948 -/* 18489 */ MCD_OPC_CheckPredicate, 0, 102, 11, 1, // Skip to: 86948 -/* 18494 */ MCD_OPC_CheckField, 6, 4, 0, 95, 11, 1, // Skip to: 86948 -/* 18501 */ MCD_OPC_Decode, 167, 10, 126, // Opcode: FMIN_ZPmI_H -/* 18505 */ MCD_OPC_FilterValue, 3, 86, 11, 1, // Skip to: 86948 -/* 18510 */ MCD_OPC_CheckPredicate, 0, 81, 11, 1, // Skip to: 86948 -/* 18515 */ MCD_OPC_Decode, 191, 9, 6, // Opcode: FMAD_ZPmZZ_H -/* 18519 */ MCD_OPC_FilterValue, 5, 63, 1, 0, // Skip to: 18843 -/* 18524 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 18527 */ MCD_OPC_FilterValue, 2, 41, 1, 0, // Skip to: 18829 -/* 18532 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 18535 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18549 -/* 18540 */ MCD_OPC_CheckPredicate, 0, 51, 11, 1, // Skip to: 86948 -/* 18545 */ MCD_OPC_Decode, 133, 12, 5, // Opcode: FRINTN_ZPmZ_H -/* 18549 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18563 -/* 18554 */ MCD_OPC_CheckPredicate, 0, 37, 11, 1, // Skip to: 86948 -/* 18559 */ MCD_OPC_Decode, 144, 12, 5, // Opcode: FRINTP_ZPmZ_H -/* 18563 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 18577 -/* 18568 */ MCD_OPC_CheckPredicate, 0, 23, 11, 1, // Skip to: 86948 -/* 18573 */ MCD_OPC_Decode, 250, 11, 5, // Opcode: FRINTM_ZPmZ_H -/* 18577 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 18591 -/* 18582 */ MCD_OPC_CheckPredicate, 0, 9, 11, 1, // Skip to: 86948 -/* 18587 */ MCD_OPC_Decode, 166, 12, 5, // Opcode: FRINTZ_ZPmZ_H -/* 18591 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 18605 -/* 18596 */ MCD_OPC_CheckPredicate, 0, 251, 10, 1, // Skip to: 86948 -/* 18601 */ MCD_OPC_Decode, 228, 11, 5, // Opcode: FRINTA_ZPmZ_H -/* 18605 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 18619 -/* 18610 */ MCD_OPC_CheckPredicate, 0, 237, 10, 1, // Skip to: 86948 -/* 18615 */ MCD_OPC_Decode, 155, 12, 5, // Opcode: FRINTX_ZPmZ_H -/* 18619 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 18633 -/* 18624 */ MCD_OPC_CheckPredicate, 0, 223, 10, 1, // Skip to: 86948 -/* 18629 */ MCD_OPC_Decode, 239, 11, 5, // Opcode: FRINTI_ZPmZ_H -/* 18633 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 18647 -/* 18638 */ MCD_OPC_CheckPredicate, 0, 209, 10, 1, // Skip to: 86948 -/* 18643 */ MCD_OPC_Decode, 219, 11, 5, // Opcode: FRECPX_ZPmZ_H -/* 18647 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 18661 -/* 18652 */ MCD_OPC_CheckPredicate, 0, 195, 10, 1, // Skip to: 86948 -/* 18657 */ MCD_OPC_Decode, 202, 12, 5, // Opcode: FSQRT_ZPmZ_H -/* 18661 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 18675 -/* 18666 */ MCD_OPC_CheckPredicate, 0, 181, 10, 1, // Skip to: 86948 -/* 18671 */ MCD_OPC_Decode, 199, 22, 5, // Opcode: SCVTF_ZPmZ_HtoH -/* 18675 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 18689 -/* 18680 */ MCD_OPC_CheckPredicate, 0, 167, 10, 1, // Skip to: 86948 -/* 18685 */ MCD_OPC_Decode, 186, 31, 5, // Opcode: UCVTF_ZPmZ_HtoH -/* 18689 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 18703 -/* 18694 */ MCD_OPC_CheckPredicate, 0, 153, 10, 1, // Skip to: 86948 -/* 18699 */ MCD_OPC_Decode, 201, 22, 5, // Opcode: SCVTF_ZPmZ_StoH -/* 18703 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 18717 -/* 18708 */ MCD_OPC_CheckPredicate, 0, 139, 10, 1, // Skip to: 86948 -/* 18713 */ MCD_OPC_Decode, 188, 31, 5, // Opcode: UCVTF_ZPmZ_StoH -/* 18717 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 18731 -/* 18722 */ MCD_OPC_CheckPredicate, 0, 125, 10, 1, // Skip to: 86948 -/* 18727 */ MCD_OPC_Decode, 197, 22, 5, // Opcode: SCVTF_ZPmZ_DtoH -/* 18731 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 18745 -/* 18736 */ MCD_OPC_CheckPredicate, 0, 111, 10, 1, // Skip to: 86948 -/* 18741 */ MCD_OPC_Decode, 184, 31, 5, // Opcode: UCVTF_ZPmZ_DtoH -/* 18745 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 18759 -/* 18750 */ MCD_OPC_CheckPredicate, 0, 97, 10, 1, // Skip to: 86948 -/* 18755 */ MCD_OPC_Decode, 233, 8, 5, // Opcode: FCVTZS_ZPmZ_HtoH -/* 18759 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 18773 -/* 18764 */ MCD_OPC_CheckPredicate, 0, 83, 10, 1, // Skip to: 86948 -/* 18769 */ MCD_OPC_Decode, 140, 9, 5, // Opcode: FCVTZU_ZPmZ_HtoH -/* 18773 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 18787 -/* 18778 */ MCD_OPC_CheckPredicate, 0, 69, 10, 1, // Skip to: 86948 -/* 18783 */ MCD_OPC_Decode, 234, 8, 5, // Opcode: FCVTZS_ZPmZ_HtoS -/* 18787 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 18801 -/* 18792 */ MCD_OPC_CheckPredicate, 0, 55, 10, 1, // Skip to: 86948 -/* 18797 */ MCD_OPC_Decode, 141, 9, 5, // Opcode: FCVTZU_ZPmZ_HtoS -/* 18801 */ MCD_OPC_FilterValue, 30, 9, 0, 0, // Skip to: 18815 -/* 18806 */ MCD_OPC_CheckPredicate, 0, 41, 10, 1, // Skip to: 86948 -/* 18811 */ MCD_OPC_Decode, 232, 8, 5, // Opcode: FCVTZS_ZPmZ_HtoD -/* 18815 */ MCD_OPC_FilterValue, 31, 32, 10, 1, // Skip to: 86948 -/* 18820 */ MCD_OPC_CheckPredicate, 0, 27, 10, 1, // Skip to: 86948 -/* 18825 */ MCD_OPC_Decode, 139, 9, 5, // Opcode: FCVTZU_ZPmZ_HtoD -/* 18829 */ MCD_OPC_FilterValue, 3, 18, 10, 1, // Skip to: 86948 -/* 18834 */ MCD_OPC_CheckPredicate, 0, 13, 10, 1, // Skip to: 86948 -/* 18839 */ MCD_OPC_Decode, 240, 10, 6, // Opcode: FMSB_ZPmZZ_H -/* 18843 */ MCD_OPC_FilterValue, 6, 53, 0, 0, // Skip to: 18901 -/* 18848 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 18851 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 18887 -/* 18856 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 18859 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18873 -/* 18864 */ MCD_OPC_CheckPredicate, 0, 239, 9, 1, // Skip to: 86948 -/* 18869 */ MCD_OPC_Decode, 209, 7, 81, // Opcode: FCMUO_PPzZZ_H -/* 18873 */ MCD_OPC_FilterValue, 1, 230, 9, 1, // Skip to: 86948 -/* 18878 */ MCD_OPC_CheckPredicate, 0, 225, 9, 1, // Skip to: 86948 -/* 18883 */ MCD_OPC_Decode, 154, 6, 81, // Opcode: FACGE_PPzZZ_H -/* 18887 */ MCD_OPC_FilterValue, 3, 216, 9, 1, // Skip to: 86948 -/* 18892 */ MCD_OPC_CheckPredicate, 0, 211, 9, 1, // Skip to: 86948 -/* 18897 */ MCD_OPC_Decode, 179, 11, 6, // Opcode: FNMAD_ZPmZZ_H -/* 18901 */ MCD_OPC_FilterValue, 7, 202, 9, 1, // Skip to: 86948 -/* 18906 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 18909 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 18930 -/* 18914 */ MCD_OPC_CheckPredicate, 0, 189, 9, 1, // Skip to: 86948 -/* 18919 */ MCD_OPC_CheckField, 4, 1, 1, 182, 9, 1, // Skip to: 86948 -/* 18926 */ MCD_OPC_Decode, 165, 6, 81, // Opcode: FACGT_PPzZZ_H -/* 18930 */ MCD_OPC_FilterValue, 3, 173, 9, 1, // Skip to: 86948 -/* 18935 */ MCD_OPC_CheckPredicate, 0, 168, 9, 1, // Skip to: 86948 -/* 18940 */ MCD_OPC_Decode, 188, 11, 6, // Opcode: FNMSB_ZPmZZ_H -/* 18944 */ MCD_OPC_FilterValue, 3, 159, 9, 1, // Skip to: 86948 -/* 18949 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 18952 */ MCD_OPC_FilterValue, 0, 215, 0, 0, // Skip to: 19172 -/* 18957 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 18960 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 19052 -/* 18965 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 18968 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18982 -/* 18973 */ MCD_OPC_CheckPredicate, 0, 130, 9, 1, // Skip to: 86948 -/* 18978 */ MCD_OPC_Decode, 197, 6, 27, // Opcode: FADD_ZZZ_S -/* 18982 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18996 -/* 18987 */ MCD_OPC_CheckPredicate, 0, 116, 9, 1, // Skip to: 86948 -/* 18992 */ MCD_OPC_Decode, 226, 12, 27, // Opcode: FSUB_ZZZ_S -/* 18996 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 19010 -/* 19001 */ MCD_OPC_CheckPredicate, 0, 102, 9, 1, // Skip to: 86948 -/* 19006 */ MCD_OPC_Decode, 150, 11, 27, // Opcode: FMUL_ZZZ_S -/* 19010 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 19024 -/* 19015 */ MCD_OPC_CheckPredicate, 0, 88, 9, 1, // Skip to: 86948 -/* 19020 */ MCD_OPC_Decode, 237, 12, 27, // Opcode: FTSMUL_ZZZ_S -/* 19024 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19038 -/* 19029 */ MCD_OPC_CheckPredicate, 0, 74, 9, 1, // Skip to: 86948 -/* 19034 */ MCD_OPC_Decode, 212, 11, 27, // Opcode: FRECPS_ZZZ_S -/* 19038 */ MCD_OPC_FilterValue, 7, 65, 9, 1, // Skip to: 86948 -/* 19043 */ MCD_OPC_CheckPredicate, 0, 60, 9, 1, // Skip to: 86948 -/* 19048 */ MCD_OPC_Decode, 189, 12, 27, // Opcode: FRSQRTS_ZZZ_S -/* 19052 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19066 -/* 19057 */ MCD_OPC_CheckPredicate, 0, 46, 9, 1, // Skip to: 86948 -/* 19062 */ MCD_OPC_Decode, 179, 10, 6, // Opcode: FMLA_ZPmZZ_S -/* 19066 */ MCD_OPC_FilterValue, 2, 87, 0, 0, // Skip to: 19158 -/* 19071 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 19074 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19088 -/* 19079 */ MCD_OPC_CheckPredicate, 0, 24, 9, 1, // Skip to: 86948 -/* 19084 */ MCD_OPC_Decode, 195, 6, 27, // Opcode: FADD_ZZZ_D -/* 19088 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19102 -/* 19093 */ MCD_OPC_CheckPredicate, 0, 10, 9, 1, // Skip to: 86948 -/* 19098 */ MCD_OPC_Decode, 224, 12, 27, // Opcode: FSUB_ZZZ_D -/* 19102 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 19116 -/* 19107 */ MCD_OPC_CheckPredicate, 0, 252, 8, 1, // Skip to: 86948 -/* 19112 */ MCD_OPC_Decode, 148, 11, 27, // Opcode: FMUL_ZZZ_D -/* 19116 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 19130 -/* 19121 */ MCD_OPC_CheckPredicate, 0, 238, 8, 1, // Skip to: 86948 -/* 19126 */ MCD_OPC_Decode, 235, 12, 27, // Opcode: FTSMUL_ZZZ_D -/* 19130 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19144 -/* 19135 */ MCD_OPC_CheckPredicate, 0, 224, 8, 1, // Skip to: 86948 -/* 19140 */ MCD_OPC_Decode, 210, 11, 27, // Opcode: FRECPS_ZZZ_D -/* 19144 */ MCD_OPC_FilterValue, 7, 215, 8, 1, // Skip to: 86948 -/* 19149 */ MCD_OPC_CheckPredicate, 0, 210, 8, 1, // Skip to: 86948 -/* 19154 */ MCD_OPC_Decode, 187, 12, 27, // Opcode: FRSQRTS_ZZZ_D -/* 19158 */ MCD_OPC_FilterValue, 3, 201, 8, 1, // Skip to: 86948 -/* 19163 */ MCD_OPC_CheckPredicate, 0, 196, 8, 1, // Skip to: 86948 -/* 19168 */ MCD_OPC_Decode, 177, 10, 6, // Opcode: FMLA_ZPmZZ_D -/* 19172 */ MCD_OPC_FilterValue, 1, 15, 2, 0, // Skip to: 19704 -/* 19177 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 19180 */ MCD_OPC_FilterValue, 0, 243, 0, 0, // Skip to: 19428 -/* 19185 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 19188 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19202 -/* 19193 */ MCD_OPC_CheckPredicate, 0, 166, 8, 1, // Skip to: 86948 -/* 19198 */ MCD_OPC_Decode, 188, 6, 14, // Opcode: FADDV_VPZ_S -/* 19202 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 19216 -/* 19207 */ MCD_OPC_CheckPredicate, 0, 152, 8, 1, // Skip to: 86948 -/* 19212 */ MCD_OPC_Decode, 208, 9, 14, // Opcode: FMAXNMV_VPZ_S -/* 19216 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 19230 -/* 19221 */ MCD_OPC_CheckPredicate, 0, 138, 8, 1, // Skip to: 86948 -/* 19226 */ MCD_OPC_Decode, 136, 10, 14, // Opcode: FMINNMV_VPZ_S -/* 19230 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19244 -/* 19235 */ MCD_OPC_CheckPredicate, 0, 124, 8, 1, // Skip to: 86948 -/* 19240 */ MCD_OPC_Decode, 234, 9, 14, // Opcode: FMAXV_VPZ_S -/* 19244 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 19258 -/* 19249 */ MCD_OPC_CheckPredicate, 0, 110, 8, 1, // Skip to: 86948 -/* 19254 */ MCD_OPC_Decode, 162, 10, 14, // Opcode: FMINV_VPZ_S -/* 19258 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 19279 -/* 19263 */ MCD_OPC_CheckPredicate, 0, 96, 8, 1, // Skip to: 86948 -/* 19268 */ MCD_OPC_CheckField, 10, 3, 4, 89, 8, 1, // Skip to: 86948 -/* 19275 */ MCD_OPC_Decode, 198, 11, 38, // Opcode: FRECPE_ZZ_S -/* 19279 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 19300 -/* 19284 */ MCD_OPC_CheckPredicate, 0, 75, 8, 1, // Skip to: 86948 -/* 19289 */ MCD_OPC_CheckField, 10, 3, 4, 68, 8, 1, // Skip to: 86948 -/* 19296 */ MCD_OPC_Decode, 175, 12, 38, // Opcode: FRSQRTE_ZZ_S -/* 19300 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 19336 -/* 19305 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 19308 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19322 -/* 19313 */ MCD_OPC_CheckPredicate, 0, 46, 8, 1, // Skip to: 86948 -/* 19318 */ MCD_OPC_Decode, 244, 6, 124, // Opcode: FCMGE_PPzZ0_S -/* 19322 */ MCD_OPC_FilterValue, 1, 37, 8, 1, // Skip to: 86948 -/* 19327 */ MCD_OPC_CheckPredicate, 0, 32, 8, 1, // Skip to: 86948 -/* 19332 */ MCD_OPC_Decode, 138, 7, 124, // Opcode: FCMGT_PPzZ0_S -/* 19336 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 19372 -/* 19341 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 19344 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19358 -/* 19349 */ MCD_OPC_CheckPredicate, 0, 10, 8, 1, // Skip to: 86948 -/* 19354 */ MCD_OPC_Decode, 181, 7, 124, // Opcode: FCMLT_PPzZ0_S -/* 19358 */ MCD_OPC_FilterValue, 1, 1, 8, 1, // Skip to: 86948 -/* 19363 */ MCD_OPC_CheckPredicate, 0, 252, 7, 1, // Skip to: 86948 -/* 19368 */ MCD_OPC_Decode, 170, 7, 124, // Opcode: FCMLE_PPzZ0_S -/* 19372 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 19393 -/* 19377 */ MCD_OPC_CheckPredicate, 0, 238, 7, 1, // Skip to: 86948 -/* 19382 */ MCD_OPC_CheckField, 4, 1, 0, 231, 7, 1, // Skip to: 86948 -/* 19389 */ MCD_OPC_Decode, 222, 6, 124, // Opcode: FCMEQ_PPzZ0_S -/* 19393 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 19414 -/* 19398 */ MCD_OPC_CheckPredicate, 0, 217, 7, 1, // Skip to: 86948 -/* 19403 */ MCD_OPC_CheckField, 4, 1, 0, 210, 7, 1, // Skip to: 86948 -/* 19410 */ MCD_OPC_Decode, 192, 7, 124, // Opcode: FCMNE_PPzZ0_S -/* 19414 */ MCD_OPC_FilterValue, 24, 201, 7, 1, // Skip to: 86948 -/* 19419 */ MCD_OPC_CheckPredicate, 0, 196, 7, 1, // Skip to: 86948 -/* 19424 */ MCD_OPC_Decode, 174, 6, 73, // Opcode: FADDA_VPZ_S -/* 19428 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19442 -/* 19433 */ MCD_OPC_CheckPredicate, 0, 182, 7, 1, // Skip to: 86948 -/* 19438 */ MCD_OPC_Decode, 198, 10, 6, // Opcode: FMLS_ZPmZZ_S -/* 19442 */ MCD_OPC_FilterValue, 2, 243, 0, 0, // Skip to: 19690 -/* 19447 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 19450 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19464 -/* 19455 */ MCD_OPC_CheckPredicate, 0, 160, 7, 1, // Skip to: 86948 -/* 19460 */ MCD_OPC_Decode, 186, 6, 1, // Opcode: FADDV_VPZ_D -/* 19464 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 19478 -/* 19469 */ MCD_OPC_CheckPredicate, 0, 146, 7, 1, // Skip to: 86948 -/* 19474 */ MCD_OPC_Decode, 206, 9, 1, // Opcode: FMAXNMV_VPZ_D -/* 19478 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 19492 -/* 19483 */ MCD_OPC_CheckPredicate, 0, 132, 7, 1, // Skip to: 86948 -/* 19488 */ MCD_OPC_Decode, 134, 10, 1, // Opcode: FMINNMV_VPZ_D -/* 19492 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19506 -/* 19497 */ MCD_OPC_CheckPredicate, 0, 118, 7, 1, // Skip to: 86948 -/* 19502 */ MCD_OPC_Decode, 232, 9, 1, // Opcode: FMAXV_VPZ_D -/* 19506 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 19520 -/* 19511 */ MCD_OPC_CheckPredicate, 0, 104, 7, 1, // Skip to: 86948 -/* 19516 */ MCD_OPC_Decode, 160, 10, 1, // Opcode: FMINV_VPZ_D -/* 19520 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 19541 -/* 19525 */ MCD_OPC_CheckPredicate, 0, 90, 7, 1, // Skip to: 86948 -/* 19530 */ MCD_OPC_CheckField, 10, 3, 4, 83, 7, 1, // Skip to: 86948 -/* 19537 */ MCD_OPC_Decode, 196, 11, 38, // Opcode: FRECPE_ZZ_D -/* 19541 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 19562 -/* 19546 */ MCD_OPC_CheckPredicate, 0, 69, 7, 1, // Skip to: 86948 -/* 19551 */ MCD_OPC_CheckField, 10, 3, 4, 62, 7, 1, // Skip to: 86948 -/* 19558 */ MCD_OPC_Decode, 173, 12, 38, // Opcode: FRSQRTE_ZZ_D -/* 19562 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 19598 -/* 19567 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 19570 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19584 -/* 19575 */ MCD_OPC_CheckPredicate, 0, 40, 7, 1, // Skip to: 86948 -/* 19580 */ MCD_OPC_Decode, 242, 6, 124, // Opcode: FCMGE_PPzZ0_D -/* 19584 */ MCD_OPC_FilterValue, 1, 31, 7, 1, // Skip to: 86948 -/* 19589 */ MCD_OPC_CheckPredicate, 0, 26, 7, 1, // Skip to: 86948 -/* 19594 */ MCD_OPC_Decode, 136, 7, 124, // Opcode: FCMGT_PPzZ0_D -/* 19598 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 19634 -/* 19603 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 19606 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19620 -/* 19611 */ MCD_OPC_CheckPredicate, 0, 4, 7, 1, // Skip to: 86948 -/* 19616 */ MCD_OPC_Decode, 179, 7, 124, // Opcode: FCMLT_PPzZ0_D -/* 19620 */ MCD_OPC_FilterValue, 1, 251, 6, 1, // Skip to: 86948 -/* 19625 */ MCD_OPC_CheckPredicate, 0, 246, 6, 1, // Skip to: 86948 -/* 19630 */ MCD_OPC_Decode, 168, 7, 124, // Opcode: FCMLE_PPzZ0_D -/* 19634 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 19655 -/* 19639 */ MCD_OPC_CheckPredicate, 0, 232, 6, 1, // Skip to: 86948 -/* 19644 */ MCD_OPC_CheckField, 4, 1, 0, 225, 6, 1, // Skip to: 86948 -/* 19651 */ MCD_OPC_Decode, 220, 6, 124, // Opcode: FCMEQ_PPzZ0_D -/* 19655 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 19676 -/* 19660 */ MCD_OPC_CheckPredicate, 0, 211, 6, 1, // Skip to: 86948 -/* 19665 */ MCD_OPC_CheckField, 4, 1, 0, 204, 6, 1, // Skip to: 86948 -/* 19672 */ MCD_OPC_Decode, 190, 7, 124, // Opcode: FCMNE_PPzZ0_D -/* 19676 */ MCD_OPC_FilterValue, 24, 195, 6, 1, // Skip to: 86948 -/* 19681 */ MCD_OPC_CheckPredicate, 0, 190, 6, 1, // Skip to: 86948 -/* 19686 */ MCD_OPC_Decode, 172, 6, 74, // Opcode: FADDA_VPZ_D -/* 19690 */ MCD_OPC_FilterValue, 3, 181, 6, 1, // Skip to: 86948 -/* 19695 */ MCD_OPC_CheckPredicate, 0, 176, 6, 1, // Skip to: 86948 -/* 19700 */ MCD_OPC_Decode, 196, 10, 6, // Opcode: FMLS_ZPmZZ_D -/* 19704 */ MCD_OPC_FilterValue, 2, 103, 0, 0, // Skip to: 19812 -/* 19709 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 19712 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 19748 -/* 19717 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 19720 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19734 -/* 19725 */ MCD_OPC_CheckPredicate, 0, 146, 6, 1, // Skip to: 86948 -/* 19730 */ MCD_OPC_Decode, 247, 6, 81, // Opcode: FCMGE_PPzZZ_S -/* 19734 */ MCD_OPC_FilterValue, 1, 137, 6, 1, // Skip to: 86948 -/* 19739 */ MCD_OPC_CheckPredicate, 0, 132, 6, 1, // Skip to: 86948 -/* 19744 */ MCD_OPC_Decode, 141, 7, 81, // Opcode: FCMGT_PPzZZ_S -/* 19748 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19762 -/* 19753 */ MCD_OPC_CheckPredicate, 0, 118, 6, 1, // Skip to: 86948 -/* 19758 */ MCD_OPC_Decode, 183, 11, 6, // Opcode: FNMLA_ZPmZZ_S -/* 19762 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 19798 -/* 19767 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 19770 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19784 -/* 19775 */ MCD_OPC_CheckPredicate, 0, 96, 6, 1, // Skip to: 86948 -/* 19780 */ MCD_OPC_Decode, 245, 6, 81, // Opcode: FCMGE_PPzZZ_D -/* 19784 */ MCD_OPC_FilterValue, 1, 87, 6, 1, // Skip to: 86948 -/* 19789 */ MCD_OPC_CheckPredicate, 0, 82, 6, 1, // Skip to: 86948 -/* 19794 */ MCD_OPC_Decode, 139, 7, 81, // Opcode: FCMGT_PPzZZ_D -/* 19798 */ MCD_OPC_FilterValue, 3, 73, 6, 1, // Skip to: 86948 -/* 19803 */ MCD_OPC_CheckPredicate, 0, 68, 6, 1, // Skip to: 86948 -/* 19808 */ MCD_OPC_Decode, 181, 11, 6, // Opcode: FNMLA_ZPmZZ_D -/* 19812 */ MCD_OPC_FilterValue, 3, 103, 0, 0, // Skip to: 19920 -/* 19817 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 19820 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 19856 -/* 19825 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 19828 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19842 -/* 19833 */ MCD_OPC_CheckPredicate, 0, 38, 6, 1, // Skip to: 86948 -/* 19838 */ MCD_OPC_Decode, 225, 6, 81, // Opcode: FCMEQ_PPzZZ_S -/* 19842 */ MCD_OPC_FilterValue, 1, 29, 6, 1, // Skip to: 86948 -/* 19847 */ MCD_OPC_CheckPredicate, 0, 24, 6, 1, // Skip to: 86948 -/* 19852 */ MCD_OPC_Decode, 195, 7, 81, // Opcode: FCMNE_PPzZZ_S -/* 19856 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19870 -/* 19861 */ MCD_OPC_CheckPredicate, 0, 10, 6, 1, // Skip to: 86948 -/* 19866 */ MCD_OPC_Decode, 186, 11, 6, // Opcode: FNMLS_ZPmZZ_S -/* 19870 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 19906 -/* 19875 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 19878 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19892 -/* 19883 */ MCD_OPC_CheckPredicate, 0, 244, 5, 1, // Skip to: 86948 -/* 19888 */ MCD_OPC_Decode, 223, 6, 81, // Opcode: FCMEQ_PPzZZ_D -/* 19892 */ MCD_OPC_FilterValue, 1, 235, 5, 1, // Skip to: 86948 -/* 19897 */ MCD_OPC_CheckPredicate, 0, 230, 5, 1, // Skip to: 86948 -/* 19902 */ MCD_OPC_Decode, 193, 7, 81, // Opcode: FCMNE_PPzZZ_D -/* 19906 */ MCD_OPC_FilterValue, 3, 221, 5, 1, // Skip to: 86948 -/* 19911 */ MCD_OPC_CheckPredicate, 0, 216, 5, 1, // Skip to: 86948 -/* 19916 */ MCD_OPC_Decode, 184, 11, 6, // Opcode: FNMLS_ZPmZZ_D -/* 19920 */ MCD_OPC_FilterValue, 4, 69, 3, 0, // Skip to: 20762 -/* 19925 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 19928 */ MCD_OPC_FilterValue, 0, 142, 1, 0, // Skip to: 20331 -/* 19933 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... -/* 19936 */ MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 20056 -/* 19941 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... -/* 19944 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19958 -/* 19949 */ MCD_OPC_CheckPredicate, 0, 178, 5, 1, // Skip to: 86948 -/* 19954 */ MCD_OPC_Decode, 194, 6, 0, // Opcode: FADD_ZPmZ_S -/* 19958 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19972 -/* 19963 */ MCD_OPC_CheckPredicate, 0, 164, 5, 1, // Skip to: 86948 -/* 19968 */ MCD_OPC_Decode, 223, 12, 0, // Opcode: FSUB_ZPmZ_S -/* 19972 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 19986 -/* 19977 */ MCD_OPC_CheckPredicate, 0, 150, 5, 1, // Skip to: 86948 -/* 19982 */ MCD_OPC_Decode, 144, 11, 0, // Opcode: FMUL_ZPmZ_S -/* 19986 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 20000 -/* 19991 */ MCD_OPC_CheckPredicate, 0, 136, 5, 1, // Skip to: 86948 -/* 19996 */ MCD_OPC_Decode, 216, 12, 0, // Opcode: FSUBR_ZPmZ_S -/* 20000 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20014 -/* 20005 */ MCD_OPC_CheckPredicate, 0, 122, 5, 1, // Skip to: 86948 -/* 20010 */ MCD_OPC_Decode, 217, 9, 0, // Opcode: FMAXNM_ZPmZ_S -/* 20014 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 20028 -/* 20019 */ MCD_OPC_CheckPredicate, 0, 108, 5, 1, // Skip to: 86948 -/* 20024 */ MCD_OPC_Decode, 145, 10, 0, // Opcode: FMINNM_ZPmZ_S -/* 20028 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 20042 -/* 20033 */ MCD_OPC_CheckPredicate, 0, 94, 5, 1, // Skip to: 86948 -/* 20038 */ MCD_OPC_Decode, 243, 9, 0, // Opcode: FMAX_ZPmZ_S -/* 20042 */ MCD_OPC_FilterValue, 7, 85, 5, 1, // Skip to: 86948 -/* 20047 */ MCD_OPC_CheckPredicate, 0, 80, 5, 1, // Skip to: 86948 -/* 20052 */ MCD_OPC_Decode, 171, 10, 0, // Opcode: FMIN_ZPmZ_S -/* 20056 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 20134 -/* 20061 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... -/* 20064 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20078 -/* 20069 */ MCD_OPC_CheckPredicate, 0, 58, 5, 1, // Skip to: 86948 -/* 20074 */ MCD_OPC_Decode, 133, 6, 0, // Opcode: FABD_ZPmZ_S -/* 20078 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20092 -/* 20083 */ MCD_OPC_CheckPredicate, 0, 44, 5, 1, // Skip to: 86948 -/* 20088 */ MCD_OPC_Decode, 197, 12, 0, // Opcode: FSCALE_ZPmZ_S -/* 20092 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20106 -/* 20097 */ MCD_OPC_CheckPredicate, 0, 30, 5, 1, // Skip to: 86948 -/* 20102 */ MCD_OPC_Decode, 253, 10, 0, // Opcode: FMULX_ZPmZ_S -/* 20106 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20120 -/* 20111 */ MCD_OPC_CheckPredicate, 0, 16, 5, 1, // Skip to: 86948 -/* 20116 */ MCD_OPC_Decode, 170, 9, 0, // Opcode: FDIVR_ZPmZ_S -/* 20120 */ MCD_OPC_FilterValue, 5, 7, 5, 1, // Skip to: 86948 -/* 20125 */ MCD_OPC_CheckPredicate, 0, 2, 5, 1, // Skip to: 86948 -/* 20130 */ MCD_OPC_Decode, 174, 9, 0, // Opcode: FDIV_ZPmZ_S -/* 20134 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20155 -/* 20139 */ MCD_OPC_CheckPredicate, 0, 244, 4, 1, // Skip to: 86948 -/* 20144 */ MCD_OPC_CheckField, 10, 3, 0, 237, 4, 1, // Skip to: 86948 -/* 20151 */ MCD_OPC_Decode, 234, 12, 125, // Opcode: FTMAD_ZZI_S -/* 20155 */ MCD_OPC_FilterValue, 3, 228, 4, 1, // Skip to: 86948 -/* 20160 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... -/* 20163 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 20184 -/* 20168 */ MCD_OPC_CheckPredicate, 0, 215, 4, 1, // Skip to: 86948 -/* 20173 */ MCD_OPC_CheckField, 6, 4, 0, 208, 4, 1, // Skip to: 86948 -/* 20180 */ MCD_OPC_Decode, 191, 6, 126, // Opcode: FADD_ZPmI_S -/* 20184 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 20205 -/* 20189 */ MCD_OPC_CheckPredicate, 0, 194, 4, 1, // Skip to: 86948 -/* 20194 */ MCD_OPC_CheckField, 6, 4, 0, 187, 4, 1, // Skip to: 86948 -/* 20201 */ MCD_OPC_Decode, 220, 12, 126, // Opcode: FSUB_ZPmI_S -/* 20205 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20226 -/* 20210 */ MCD_OPC_CheckPredicate, 0, 173, 4, 1, // Skip to: 86948 -/* 20215 */ MCD_OPC_CheckField, 6, 4, 0, 166, 4, 1, // Skip to: 86948 -/* 20222 */ MCD_OPC_Decode, 141, 11, 126, // Opcode: FMUL_ZPmI_S -/* 20226 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 20247 -/* 20231 */ MCD_OPC_CheckPredicate, 0, 152, 4, 1, // Skip to: 86948 -/* 20236 */ MCD_OPC_CheckField, 6, 4, 0, 145, 4, 1, // Skip to: 86948 -/* 20243 */ MCD_OPC_Decode, 213, 12, 126, // Opcode: FSUBR_ZPmI_S -/* 20247 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 20268 -/* 20252 */ MCD_OPC_CheckPredicate, 0, 131, 4, 1, // Skip to: 86948 -/* 20257 */ MCD_OPC_CheckField, 6, 4, 0, 124, 4, 1, // Skip to: 86948 -/* 20264 */ MCD_OPC_Decode, 214, 9, 126, // Opcode: FMAXNM_ZPmI_S -/* 20268 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 20289 -/* 20273 */ MCD_OPC_CheckPredicate, 0, 110, 4, 1, // Skip to: 86948 -/* 20278 */ MCD_OPC_CheckField, 6, 4, 0, 103, 4, 1, // Skip to: 86948 -/* 20285 */ MCD_OPC_Decode, 142, 10, 126, // Opcode: FMINNM_ZPmI_S -/* 20289 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 20310 -/* 20294 */ MCD_OPC_CheckPredicate, 0, 89, 4, 1, // Skip to: 86948 -/* 20299 */ MCD_OPC_CheckField, 6, 4, 0, 82, 4, 1, // Skip to: 86948 -/* 20306 */ MCD_OPC_Decode, 240, 9, 126, // Opcode: FMAX_ZPmI_S -/* 20310 */ MCD_OPC_FilterValue, 7, 73, 4, 1, // Skip to: 86948 -/* 20315 */ MCD_OPC_CheckPredicate, 0, 68, 4, 1, // Skip to: 86948 -/* 20320 */ MCD_OPC_CheckField, 6, 4, 0, 61, 4, 1, // Skip to: 86948 -/* 20327 */ MCD_OPC_Decode, 168, 10, 126, // Opcode: FMIN_ZPmI_S -/* 20331 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20345 -/* 20336 */ MCD_OPC_CheckPredicate, 0, 47, 4, 1, // Skip to: 86948 -/* 20341 */ MCD_OPC_Decode, 192, 9, 6, // Opcode: FMAD_ZPmZZ_S -/* 20345 */ MCD_OPC_FilterValue, 2, 142, 1, 0, // Skip to: 20748 -/* 20350 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... -/* 20353 */ MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 20473 -/* 20358 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... -/* 20361 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20375 -/* 20366 */ MCD_OPC_CheckPredicate, 0, 17, 4, 1, // Skip to: 86948 -/* 20371 */ MCD_OPC_Decode, 192, 6, 0, // Opcode: FADD_ZPmZ_D -/* 20375 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20389 -/* 20380 */ MCD_OPC_CheckPredicate, 0, 3, 4, 1, // Skip to: 86948 -/* 20385 */ MCD_OPC_Decode, 221, 12, 0, // Opcode: FSUB_ZPmZ_D -/* 20389 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20403 -/* 20394 */ MCD_OPC_CheckPredicate, 0, 245, 3, 1, // Skip to: 86948 -/* 20399 */ MCD_OPC_Decode, 142, 11, 0, // Opcode: FMUL_ZPmZ_D -/* 20403 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 20417 -/* 20408 */ MCD_OPC_CheckPredicate, 0, 231, 3, 1, // Skip to: 86948 -/* 20413 */ MCD_OPC_Decode, 214, 12, 0, // Opcode: FSUBR_ZPmZ_D -/* 20417 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20431 -/* 20422 */ MCD_OPC_CheckPredicate, 0, 217, 3, 1, // Skip to: 86948 -/* 20427 */ MCD_OPC_Decode, 215, 9, 0, // Opcode: FMAXNM_ZPmZ_D -/* 20431 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 20445 -/* 20436 */ MCD_OPC_CheckPredicate, 0, 203, 3, 1, // Skip to: 86948 -/* 20441 */ MCD_OPC_Decode, 143, 10, 0, // Opcode: FMINNM_ZPmZ_D -/* 20445 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 20459 -/* 20450 */ MCD_OPC_CheckPredicate, 0, 189, 3, 1, // Skip to: 86948 -/* 20455 */ MCD_OPC_Decode, 241, 9, 0, // Opcode: FMAX_ZPmZ_D -/* 20459 */ MCD_OPC_FilterValue, 7, 180, 3, 1, // Skip to: 86948 -/* 20464 */ MCD_OPC_CheckPredicate, 0, 175, 3, 1, // Skip to: 86948 -/* 20469 */ MCD_OPC_Decode, 169, 10, 0, // Opcode: FMIN_ZPmZ_D -/* 20473 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 20551 -/* 20478 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... -/* 20481 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20495 -/* 20486 */ MCD_OPC_CheckPredicate, 0, 153, 3, 1, // Skip to: 86948 -/* 20491 */ MCD_OPC_Decode, 131, 6, 0, // Opcode: FABD_ZPmZ_D -/* 20495 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20509 -/* 20500 */ MCD_OPC_CheckPredicate, 0, 139, 3, 1, // Skip to: 86948 -/* 20505 */ MCD_OPC_Decode, 195, 12, 0, // Opcode: FSCALE_ZPmZ_D -/* 20509 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20523 -/* 20514 */ MCD_OPC_CheckPredicate, 0, 125, 3, 1, // Skip to: 86948 -/* 20519 */ MCD_OPC_Decode, 251, 10, 0, // Opcode: FMULX_ZPmZ_D -/* 20523 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20537 -/* 20528 */ MCD_OPC_CheckPredicate, 0, 111, 3, 1, // Skip to: 86948 -/* 20533 */ MCD_OPC_Decode, 168, 9, 0, // Opcode: FDIVR_ZPmZ_D -/* 20537 */ MCD_OPC_FilterValue, 5, 102, 3, 1, // Skip to: 86948 -/* 20542 */ MCD_OPC_CheckPredicate, 0, 97, 3, 1, // Skip to: 86948 -/* 20547 */ MCD_OPC_Decode, 172, 9, 0, // Opcode: FDIV_ZPmZ_D -/* 20551 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20572 -/* 20556 */ MCD_OPC_CheckPredicate, 0, 83, 3, 1, // Skip to: 86948 -/* 20561 */ MCD_OPC_CheckField, 10, 3, 0, 76, 3, 1, // Skip to: 86948 -/* 20568 */ MCD_OPC_Decode, 232, 12, 125, // Opcode: FTMAD_ZZI_D -/* 20572 */ MCD_OPC_FilterValue, 3, 67, 3, 1, // Skip to: 86948 -/* 20577 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... -/* 20580 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 20601 -/* 20585 */ MCD_OPC_CheckPredicate, 0, 54, 3, 1, // Skip to: 86948 -/* 20590 */ MCD_OPC_CheckField, 6, 4, 0, 47, 3, 1, // Skip to: 86948 -/* 20597 */ MCD_OPC_Decode, 189, 6, 126, // Opcode: FADD_ZPmI_D -/* 20601 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 20622 -/* 20606 */ MCD_OPC_CheckPredicate, 0, 33, 3, 1, // Skip to: 86948 -/* 20611 */ MCD_OPC_CheckField, 6, 4, 0, 26, 3, 1, // Skip to: 86948 -/* 20618 */ MCD_OPC_Decode, 218, 12, 126, // Opcode: FSUB_ZPmI_D -/* 20622 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20643 -/* 20627 */ MCD_OPC_CheckPredicate, 0, 12, 3, 1, // Skip to: 86948 -/* 20632 */ MCD_OPC_CheckField, 6, 4, 0, 5, 3, 1, // Skip to: 86948 -/* 20639 */ MCD_OPC_Decode, 139, 11, 126, // Opcode: FMUL_ZPmI_D -/* 20643 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 20664 -/* 20648 */ MCD_OPC_CheckPredicate, 0, 247, 2, 1, // Skip to: 86948 -/* 20653 */ MCD_OPC_CheckField, 6, 4, 0, 240, 2, 1, // Skip to: 86948 -/* 20660 */ MCD_OPC_Decode, 211, 12, 126, // Opcode: FSUBR_ZPmI_D -/* 20664 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 20685 -/* 20669 */ MCD_OPC_CheckPredicate, 0, 226, 2, 1, // Skip to: 86948 -/* 20674 */ MCD_OPC_CheckField, 6, 4, 0, 219, 2, 1, // Skip to: 86948 -/* 20681 */ MCD_OPC_Decode, 212, 9, 126, // Opcode: FMAXNM_ZPmI_D -/* 20685 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 20706 -/* 20690 */ MCD_OPC_CheckPredicate, 0, 205, 2, 1, // Skip to: 86948 -/* 20695 */ MCD_OPC_CheckField, 6, 4, 0, 198, 2, 1, // Skip to: 86948 -/* 20702 */ MCD_OPC_Decode, 140, 10, 126, // Opcode: FMINNM_ZPmI_D -/* 20706 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 20727 -/* 20711 */ MCD_OPC_CheckPredicate, 0, 184, 2, 1, // Skip to: 86948 -/* 20716 */ MCD_OPC_CheckField, 6, 4, 0, 177, 2, 1, // Skip to: 86948 -/* 20723 */ MCD_OPC_Decode, 238, 9, 126, // Opcode: FMAX_ZPmI_D -/* 20727 */ MCD_OPC_FilterValue, 7, 168, 2, 1, // Skip to: 86948 -/* 20732 */ MCD_OPC_CheckPredicate, 0, 163, 2, 1, // Skip to: 86948 -/* 20737 */ MCD_OPC_CheckField, 6, 4, 0, 156, 2, 1, // Skip to: 86948 -/* 20744 */ MCD_OPC_Decode, 166, 10, 126, // Opcode: FMIN_ZPmI_D -/* 20748 */ MCD_OPC_FilterValue, 3, 147, 2, 1, // Skip to: 86948 -/* 20753 */ MCD_OPC_CheckPredicate, 0, 142, 2, 1, // Skip to: 86948 -/* 20758 */ MCD_OPC_Decode, 190, 9, 6, // Opcode: FMAD_ZPmZZ_D -/* 20762 */ MCD_OPC_FilterValue, 5, 95, 2, 0, // Skip to: 21374 -/* 20767 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 20770 */ MCD_OPC_FilterValue, 0, 213, 0, 0, // Skip to: 20988 -/* 20775 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 20778 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20792 -/* 20783 */ MCD_OPC_CheckPredicate, 0, 112, 2, 1, // Skip to: 86948 -/* 20788 */ MCD_OPC_Decode, 134, 12, 5, // Opcode: FRINTN_ZPmZ_S -/* 20792 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20806 -/* 20797 */ MCD_OPC_CheckPredicate, 0, 98, 2, 1, // Skip to: 86948 -/* 20802 */ MCD_OPC_Decode, 145, 12, 5, // Opcode: FRINTP_ZPmZ_S -/* 20806 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20820 -/* 20811 */ MCD_OPC_CheckPredicate, 0, 84, 2, 1, // Skip to: 86948 -/* 20816 */ MCD_OPC_Decode, 251, 11, 5, // Opcode: FRINTM_ZPmZ_S -/* 20820 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 20834 -/* 20825 */ MCD_OPC_CheckPredicate, 0, 70, 2, 1, // Skip to: 86948 -/* 20830 */ MCD_OPC_Decode, 167, 12, 5, // Opcode: FRINTZ_ZPmZ_S -/* 20834 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20848 -/* 20839 */ MCD_OPC_CheckPredicate, 0, 56, 2, 1, // Skip to: 86948 -/* 20844 */ MCD_OPC_Decode, 229, 11, 5, // Opcode: FRINTA_ZPmZ_S -/* 20848 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 20862 -/* 20853 */ MCD_OPC_CheckPredicate, 0, 42, 2, 1, // Skip to: 86948 -/* 20858 */ MCD_OPC_Decode, 156, 12, 5, // Opcode: FRINTX_ZPmZ_S -/* 20862 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 20876 -/* 20867 */ MCD_OPC_CheckPredicate, 0, 28, 2, 1, // Skip to: 86948 -/* 20872 */ MCD_OPC_Decode, 240, 11, 5, // Opcode: FRINTI_ZPmZ_S -/* 20876 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 20890 -/* 20881 */ MCD_OPC_CheckPredicate, 0, 14, 2, 1, // Skip to: 86948 -/* 20886 */ MCD_OPC_Decode, 165, 9, 5, // Opcode: FCVT_ZPmZ_StoH -/* 20890 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 20904 -/* 20895 */ MCD_OPC_CheckPredicate, 0, 0, 2, 1, // Skip to: 86948 -/* 20900 */ MCD_OPC_Decode, 163, 9, 5, // Opcode: FCVT_ZPmZ_HtoS -/* 20904 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 20918 -/* 20909 */ MCD_OPC_CheckPredicate, 0, 242, 1, 1, // Skip to: 86948 -/* 20914 */ MCD_OPC_Decode, 220, 11, 5, // Opcode: FRECPX_ZPmZ_S -/* 20918 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 20932 -/* 20923 */ MCD_OPC_CheckPredicate, 0, 228, 1, 1, // Skip to: 86948 -/* 20928 */ MCD_OPC_Decode, 203, 12, 5, // Opcode: FSQRT_ZPmZ_S -/* 20932 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 20946 -/* 20937 */ MCD_OPC_CheckPredicate, 0, 214, 1, 1, // Skip to: 86948 -/* 20942 */ MCD_OPC_Decode, 202, 22, 5, // Opcode: SCVTF_ZPmZ_StoS -/* 20946 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 20960 -/* 20951 */ MCD_OPC_CheckPredicate, 0, 200, 1, 1, // Skip to: 86948 -/* 20956 */ MCD_OPC_Decode, 189, 31, 5, // Opcode: UCVTF_ZPmZ_StoS -/* 20960 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 20974 -/* 20965 */ MCD_OPC_CheckPredicate, 0, 186, 1, 1, // Skip to: 86948 -/* 20970 */ MCD_OPC_Decode, 236, 8, 5, // Opcode: FCVTZS_ZPmZ_StoS -/* 20974 */ MCD_OPC_FilterValue, 29, 177, 1, 1, // Skip to: 86948 -/* 20979 */ MCD_OPC_CheckPredicate, 0, 172, 1, 1, // Skip to: 86948 -/* 20984 */ MCD_OPC_Decode, 143, 9, 5, // Opcode: FCVTZU_ZPmZ_StoS -/* 20988 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21002 -/* 20993 */ MCD_OPC_CheckPredicate, 0, 158, 1, 1, // Skip to: 86948 -/* 20998 */ MCD_OPC_Decode, 241, 10, 6, // Opcode: FMSB_ZPmZZ_S -/* 21002 */ MCD_OPC_FilterValue, 2, 97, 1, 0, // Skip to: 21360 -/* 21007 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 21010 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21024 -/* 21015 */ MCD_OPC_CheckPredicate, 0, 136, 1, 1, // Skip to: 86948 -/* 21020 */ MCD_OPC_Decode, 132, 12, 5, // Opcode: FRINTN_ZPmZ_D -/* 21024 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21038 -/* 21029 */ MCD_OPC_CheckPredicate, 0, 122, 1, 1, // Skip to: 86948 -/* 21034 */ MCD_OPC_Decode, 143, 12, 5, // Opcode: FRINTP_ZPmZ_D -/* 21038 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 21052 -/* 21043 */ MCD_OPC_CheckPredicate, 0, 108, 1, 1, // Skip to: 86948 -/* 21048 */ MCD_OPC_Decode, 249, 11, 5, // Opcode: FRINTM_ZPmZ_D -/* 21052 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 21066 -/* 21057 */ MCD_OPC_CheckPredicate, 0, 94, 1, 1, // Skip to: 86948 -/* 21062 */ MCD_OPC_Decode, 165, 12, 5, // Opcode: FRINTZ_ZPmZ_D -/* 21066 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 21080 -/* 21071 */ MCD_OPC_CheckPredicate, 0, 80, 1, 1, // Skip to: 86948 -/* 21076 */ MCD_OPC_Decode, 227, 11, 5, // Opcode: FRINTA_ZPmZ_D -/* 21080 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 21094 -/* 21085 */ MCD_OPC_CheckPredicate, 0, 66, 1, 1, // Skip to: 86948 -/* 21090 */ MCD_OPC_Decode, 154, 12, 5, // Opcode: FRINTX_ZPmZ_D -/* 21094 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 21108 -/* 21099 */ MCD_OPC_CheckPredicate, 0, 52, 1, 1, // Skip to: 86948 -/* 21104 */ MCD_OPC_Decode, 238, 11, 5, // Opcode: FRINTI_ZPmZ_D -/* 21108 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 21122 -/* 21113 */ MCD_OPC_CheckPredicate, 0, 38, 1, 1, // Skip to: 86948 -/* 21118 */ MCD_OPC_Decode, 160, 9, 5, // Opcode: FCVT_ZPmZ_DtoH -/* 21122 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 21136 -/* 21127 */ MCD_OPC_CheckPredicate, 0, 24, 1, 1, // Skip to: 86948 -/* 21132 */ MCD_OPC_Decode, 162, 9, 5, // Opcode: FCVT_ZPmZ_HtoD -/* 21136 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 21150 -/* 21141 */ MCD_OPC_CheckPredicate, 0, 10, 1, 1, // Skip to: 86948 -/* 21146 */ MCD_OPC_Decode, 161, 9, 5, // Opcode: FCVT_ZPmZ_DtoS -/* 21150 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 21164 -/* 21155 */ MCD_OPC_CheckPredicate, 0, 252, 0, 1, // Skip to: 86948 -/* 21160 */ MCD_OPC_Decode, 164, 9, 5, // Opcode: FCVT_ZPmZ_StoD -/* 21164 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 21178 -/* 21169 */ MCD_OPC_CheckPredicate, 0, 238, 0, 1, // Skip to: 86948 -/* 21174 */ MCD_OPC_Decode, 218, 11, 5, // Opcode: FRECPX_ZPmZ_D -/* 21178 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 21192 -/* 21183 */ MCD_OPC_CheckPredicate, 0, 224, 0, 1, // Skip to: 86948 -/* 21188 */ MCD_OPC_Decode, 201, 12, 5, // Opcode: FSQRT_ZPmZ_D -/* 21192 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 21206 -/* 21197 */ MCD_OPC_CheckPredicate, 0, 210, 0, 1, // Skip to: 86948 -/* 21202 */ MCD_OPC_Decode, 200, 22, 5, // Opcode: SCVTF_ZPmZ_StoD -/* 21206 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 21220 -/* 21211 */ MCD_OPC_CheckPredicate, 0, 196, 0, 1, // Skip to: 86948 -/* 21216 */ MCD_OPC_Decode, 187, 31, 5, // Opcode: UCVTF_ZPmZ_StoD -/* 21220 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 21234 -/* 21225 */ MCD_OPC_CheckPredicate, 0, 182, 0, 1, // Skip to: 86948 -/* 21230 */ MCD_OPC_Decode, 198, 22, 5, // Opcode: SCVTF_ZPmZ_DtoS -/* 21234 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 21248 -/* 21239 */ MCD_OPC_CheckPredicate, 0, 168, 0, 1, // Skip to: 86948 -/* 21244 */ MCD_OPC_Decode, 185, 31, 5, // Opcode: UCVTF_ZPmZ_DtoS -/* 21248 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 21262 -/* 21253 */ MCD_OPC_CheckPredicate, 0, 154, 0, 1, // Skip to: 86948 -/* 21258 */ MCD_OPC_Decode, 196, 22, 5, // Opcode: SCVTF_ZPmZ_DtoD -/* 21262 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 21276 -/* 21267 */ MCD_OPC_CheckPredicate, 0, 140, 0, 1, // Skip to: 86948 -/* 21272 */ MCD_OPC_Decode, 183, 31, 5, // Opcode: UCVTF_ZPmZ_DtoD -/* 21276 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 21290 -/* 21281 */ MCD_OPC_CheckPredicate, 0, 126, 0, 1, // Skip to: 86948 -/* 21286 */ MCD_OPC_Decode, 231, 8, 5, // Opcode: FCVTZS_ZPmZ_DtoS -/* 21290 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 21304 -/* 21295 */ MCD_OPC_CheckPredicate, 0, 112, 0, 1, // Skip to: 86948 -/* 21300 */ MCD_OPC_Decode, 138, 9, 5, // Opcode: FCVTZU_ZPmZ_DtoS -/* 21304 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 21318 -/* 21309 */ MCD_OPC_CheckPredicate, 0, 98, 0, 1, // Skip to: 86948 -/* 21314 */ MCD_OPC_Decode, 235, 8, 5, // Opcode: FCVTZS_ZPmZ_StoD -/* 21318 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 21332 -/* 21323 */ MCD_OPC_CheckPredicate, 0, 84, 0, 1, // Skip to: 86948 -/* 21328 */ MCD_OPC_Decode, 142, 9, 5, // Opcode: FCVTZU_ZPmZ_StoD -/* 21332 */ MCD_OPC_FilterValue, 30, 9, 0, 0, // Skip to: 21346 -/* 21337 */ MCD_OPC_CheckPredicate, 0, 70, 0, 1, // Skip to: 86948 -/* 21342 */ MCD_OPC_Decode, 230, 8, 5, // Opcode: FCVTZS_ZPmZ_DtoD -/* 21346 */ MCD_OPC_FilterValue, 31, 61, 0, 1, // Skip to: 86948 -/* 21351 */ MCD_OPC_CheckPredicate, 0, 56, 0, 1, // Skip to: 86948 -/* 21356 */ MCD_OPC_Decode, 137, 9, 5, // Opcode: FCVTZU_ZPmZ_DtoD -/* 21360 */ MCD_OPC_FilterValue, 3, 47, 0, 1, // Skip to: 86948 -/* 21365 */ MCD_OPC_CheckPredicate, 0, 42, 0, 1, // Skip to: 86948 -/* 21370 */ MCD_OPC_Decode, 239, 10, 6, // Opcode: FMSB_ZPmZZ_D -/* 21374 */ MCD_OPC_FilterValue, 6, 103, 0, 0, // Skip to: 21482 -/* 21379 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 21382 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 21418 -/* 21387 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 21390 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21404 -/* 21395 */ MCD_OPC_CheckPredicate, 0, 12, 0, 1, // Skip to: 86948 -/* 21400 */ MCD_OPC_Decode, 210, 7, 81, // Opcode: FCMUO_PPzZZ_S -/* 21404 */ MCD_OPC_FilterValue, 1, 3, 0, 1, // Skip to: 86948 -/* 21409 */ MCD_OPC_CheckPredicate, 0, 254, 255, 0, // Skip to: 86948 -/* 21414 */ MCD_OPC_Decode, 155, 6, 81, // Opcode: FACGE_PPzZZ_S -/* 21418 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21432 -/* 21423 */ MCD_OPC_CheckPredicate, 0, 240, 255, 0, // Skip to: 86948 -/* 21428 */ MCD_OPC_Decode, 180, 11, 6, // Opcode: FNMAD_ZPmZZ_S -/* 21432 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 21468 -/* 21437 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 21440 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21454 -/* 21445 */ MCD_OPC_CheckPredicate, 0, 218, 255, 0, // Skip to: 86948 -/* 21450 */ MCD_OPC_Decode, 208, 7, 81, // Opcode: FCMUO_PPzZZ_D -/* 21454 */ MCD_OPC_FilterValue, 1, 209, 255, 0, // Skip to: 86948 -/* 21459 */ MCD_OPC_CheckPredicate, 0, 204, 255, 0, // Skip to: 86948 -/* 21464 */ MCD_OPC_Decode, 153, 6, 81, // Opcode: FACGE_PPzZZ_D -/* 21468 */ MCD_OPC_FilterValue, 3, 195, 255, 0, // Skip to: 86948 -/* 21473 */ MCD_OPC_CheckPredicate, 0, 190, 255, 0, // Skip to: 86948 -/* 21478 */ MCD_OPC_Decode, 178, 11, 6, // Opcode: FNMAD_ZPmZZ_D -/* 21482 */ MCD_OPC_FilterValue, 7, 181, 255, 0, // Skip to: 86948 -/* 21487 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 21490 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 21511 -/* 21495 */ MCD_OPC_CheckPredicate, 0, 168, 255, 0, // Skip to: 86948 -/* 21500 */ MCD_OPC_CheckField, 4, 1, 1, 161, 255, 0, // Skip to: 86948 -/* 21507 */ MCD_OPC_Decode, 166, 6, 81, // Opcode: FACGT_PPzZZ_S -/* 21511 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21525 -/* 21516 */ MCD_OPC_CheckPredicate, 0, 147, 255, 0, // Skip to: 86948 -/* 21521 */ MCD_OPC_Decode, 189, 11, 6, // Opcode: FNMSB_ZPmZZ_S -/* 21525 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 21546 -/* 21530 */ MCD_OPC_CheckPredicate, 0, 133, 255, 0, // Skip to: 86948 -/* 21535 */ MCD_OPC_CheckField, 4, 1, 1, 126, 255, 0, // Skip to: 86948 -/* 21542 */ MCD_OPC_Decode, 164, 6, 81, // Opcode: FACGT_PPzZZ_D -/* 21546 */ MCD_OPC_FilterValue, 3, 117, 255, 0, // Skip to: 86948 -/* 21551 */ MCD_OPC_CheckPredicate, 0, 112, 255, 0, // Skip to: 86948 -/* 21556 */ MCD_OPC_Decode, 187, 11, 6, // Opcode: FNMSB_ZPmZZ_D -/* 21560 */ MCD_OPC_FilterValue, 4, 96, 6, 0, // Skip to: 23197 -/* 21565 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 21568 */ MCD_OPC_FilterValue, 0, 207, 0, 0, // Skip to: 21780 -/* 21573 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 21576 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 21620 -/* 21581 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 21584 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21598 -/* 21589 */ MCD_OPC_CheckPredicate, 0, 74, 255, 0, // Skip to: 86948 -/* 21594 */ MCD_OPC_Decode, 145, 13, 127, // Opcode: GLD1SB_S_UXTW_REAL -/* 21598 */ MCD_OPC_FilterValue, 1, 65, 255, 0, // Skip to: 86948 -/* 21603 */ MCD_OPC_CheckPredicate, 0, 60, 255, 0, // Skip to: 86948 -/* 21608 */ MCD_OPC_CheckField, 4, 1, 0, 53, 255, 0, // Skip to: 86948 -/* 21615 */ MCD_OPC_Decode, 133, 21, 128, 1, // Opcode: PRFB_S_UXTW_SCALED -/* 21620 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 21664 -/* 21625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 21628 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21642 -/* 21633 */ MCD_OPC_CheckPredicate, 0, 30, 255, 0, // Skip to: 86948 -/* 21638 */ MCD_OPC_Decode, 144, 13, 127, // Opcode: GLD1SB_S_SXTW_REAL -/* 21642 */ MCD_OPC_FilterValue, 1, 21, 255, 0, // Skip to: 86948 -/* 21647 */ MCD_OPC_CheckPredicate, 0, 16, 255, 0, // Skip to: 86948 -/* 21652 */ MCD_OPC_CheckField, 4, 1, 0, 9, 255, 0, // Skip to: 86948 -/* 21659 */ MCD_OPC_Decode, 132, 21, 128, 1, // Opcode: PRFB_S_SXTW_SCALED -/* 21664 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 21700 -/* 21669 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 21672 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21686 -/* 21677 */ MCD_OPC_CheckPredicate, 0, 242, 254, 0, // Skip to: 86948 -/* 21682 */ MCD_OPC_Decode, 156, 13, 127, // Opcode: GLD1SH_S_UXTW_REAL -/* 21686 */ MCD_OPC_FilterValue, 1, 233, 254, 0, // Skip to: 86948 -/* 21691 */ MCD_OPC_CheckPredicate, 0, 228, 254, 0, // Skip to: 86948 -/* 21696 */ MCD_OPC_Decode, 157, 13, 127, // Opcode: GLD1SH_S_UXTW_SCALED_REAL -/* 21700 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 21736 -/* 21705 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 21708 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21722 -/* 21713 */ MCD_OPC_CheckPredicate, 0, 206, 254, 0, // Skip to: 86948 -/* 21718 */ MCD_OPC_Decode, 154, 13, 127, // Opcode: GLD1SH_S_SXTW_REAL -/* 21722 */ MCD_OPC_FilterValue, 1, 197, 254, 0, // Skip to: 86948 -/* 21727 */ MCD_OPC_CheckPredicate, 0, 192, 254, 0, // Skip to: 86948 -/* 21732 */ MCD_OPC_Decode, 155, 13, 127, // Opcode: GLD1SH_S_SXTW_SCALED_REAL -/* 21736 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 21758 -/* 21741 */ MCD_OPC_CheckPredicate, 0, 178, 254, 0, // Skip to: 86948 -/* 21746 */ MCD_OPC_CheckField, 4, 1, 0, 171, 254, 0, // Skip to: 86948 -/* 21753 */ MCD_OPC_Decode, 167, 18, 129, 1, // Opcode: LDR_PXI -/* 21758 */ MCD_OPC_FilterValue, 7, 161, 254, 0, // Skip to: 86948 -/* 21763 */ MCD_OPC_CheckPredicate, 0, 156, 254, 0, // Skip to: 86948 -/* 21768 */ MCD_OPC_CheckField, 4, 1, 0, 149, 254, 0, // Skip to: 86948 -/* 21775 */ MCD_OPC_Decode, 129, 21, 130, 1, // Opcode: PRFB_PRI -/* 21780 */ MCD_OPC_FilterValue, 1, 185, 0, 0, // Skip to: 21970 -/* 21785 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 21788 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 21832 -/* 21793 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 21796 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21810 -/* 21801 */ MCD_OPC_CheckPredicate, 0, 118, 254, 0, // Skip to: 86948 -/* 21806 */ MCD_OPC_Decode, 209, 13, 127, // Opcode: GLDFF1SB_S_UXTW_REAL -/* 21810 */ MCD_OPC_FilterValue, 1, 109, 254, 0, // Skip to: 86948 -/* 21815 */ MCD_OPC_CheckPredicate, 0, 104, 254, 0, // Skip to: 86948 -/* 21820 */ MCD_OPC_CheckField, 4, 1, 0, 97, 254, 0, // Skip to: 86948 -/* 21827 */ MCD_OPC_Decode, 151, 21, 128, 1, // Opcode: PRFH_S_UXTW_SCALED -/* 21832 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 21876 -/* 21837 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 21840 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21854 -/* 21845 */ MCD_OPC_CheckPredicate, 0, 74, 254, 0, // Skip to: 86948 -/* 21850 */ MCD_OPC_Decode, 208, 13, 127, // Opcode: GLDFF1SB_S_SXTW_REAL -/* 21854 */ MCD_OPC_FilterValue, 1, 65, 254, 0, // Skip to: 86948 -/* 21859 */ MCD_OPC_CheckPredicate, 0, 60, 254, 0, // Skip to: 86948 -/* 21864 */ MCD_OPC_CheckField, 4, 1, 0, 53, 254, 0, // Skip to: 86948 -/* 21871 */ MCD_OPC_Decode, 150, 21, 128, 1, // Opcode: PRFH_S_SXTW_SCALED -/* 21876 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 21912 -/* 21881 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 21884 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21898 -/* 21889 */ MCD_OPC_CheckPredicate, 0, 30, 254, 0, // Skip to: 86948 -/* 21894 */ MCD_OPC_Decode, 220, 13, 127, // Opcode: GLDFF1SH_S_UXTW_REAL -/* 21898 */ MCD_OPC_FilterValue, 1, 21, 254, 0, // Skip to: 86948 -/* 21903 */ MCD_OPC_CheckPredicate, 0, 16, 254, 0, // Skip to: 86948 -/* 21908 */ MCD_OPC_Decode, 221, 13, 127, // Opcode: GLDFF1SH_S_UXTW_SCALED_REAL -/* 21912 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 21948 -/* 21917 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 21920 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21934 -/* 21925 */ MCD_OPC_CheckPredicate, 0, 250, 253, 0, // Skip to: 86948 -/* 21930 */ MCD_OPC_Decode, 218, 13, 127, // Opcode: GLDFF1SH_S_SXTW_REAL -/* 21934 */ MCD_OPC_FilterValue, 1, 241, 253, 0, // Skip to: 86948 -/* 21939 */ MCD_OPC_CheckPredicate, 0, 236, 253, 0, // Skip to: 86948 -/* 21944 */ MCD_OPC_Decode, 219, 13, 127, // Opcode: GLDFF1SH_S_SXTW_SCALED_REAL -/* 21948 */ MCD_OPC_FilterValue, 7, 227, 253, 0, // Skip to: 86948 -/* 21953 */ MCD_OPC_CheckPredicate, 0, 222, 253, 0, // Skip to: 86948 -/* 21958 */ MCD_OPC_CheckField, 4, 1, 0, 215, 253, 0, // Skip to: 86948 -/* 21965 */ MCD_OPC_Decode, 147, 21, 130, 1, // Opcode: PRFH_PRI -/* 21970 */ MCD_OPC_FilterValue, 2, 16, 1, 0, // Skip to: 22247 -/* 21975 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 21978 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 22022 -/* 21983 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 21986 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22000 -/* 21991 */ MCD_OPC_CheckPredicate, 0, 184, 253, 0, // Skip to: 86948 -/* 21996 */ MCD_OPC_Decode, 247, 12, 127, // Opcode: GLD1B_S_UXTW_REAL -/* 22000 */ MCD_OPC_FilterValue, 1, 175, 253, 0, // Skip to: 86948 -/* 22005 */ MCD_OPC_CheckPredicate, 0, 170, 253, 0, // Skip to: 86948 -/* 22010 */ MCD_OPC_CheckField, 4, 1, 0, 163, 253, 0, // Skip to: 86948 -/* 22017 */ MCD_OPC_Decode, 165, 21, 128, 1, // Opcode: PRFW_S_UXTW_SCALED -/* 22022 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 22066 -/* 22027 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22030 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22044 -/* 22035 */ MCD_OPC_CheckPredicate, 0, 140, 253, 0, // Skip to: 86948 -/* 22040 */ MCD_OPC_Decode, 246, 12, 127, // Opcode: GLD1B_S_SXTW_REAL -/* 22044 */ MCD_OPC_FilterValue, 1, 131, 253, 0, // Skip to: 86948 -/* 22049 */ MCD_OPC_CheckPredicate, 0, 126, 253, 0, // Skip to: 86948 -/* 22054 */ MCD_OPC_CheckField, 4, 1, 0, 119, 253, 0, // Skip to: 86948 -/* 22061 */ MCD_OPC_Decode, 164, 21, 128, 1, // Opcode: PRFW_S_SXTW_SCALED -/* 22066 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 22102 -/* 22071 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22074 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22088 -/* 22079 */ MCD_OPC_CheckPredicate, 0, 96, 253, 0, // Skip to: 86948 -/* 22084 */ MCD_OPC_Decode, 137, 13, 127, // Opcode: GLD1H_S_UXTW_REAL -/* 22088 */ MCD_OPC_FilterValue, 1, 87, 253, 0, // Skip to: 86948 -/* 22093 */ MCD_OPC_CheckPredicate, 0, 82, 253, 0, // Skip to: 86948 -/* 22098 */ MCD_OPC_Decode, 138, 13, 127, // Opcode: GLD1H_S_UXTW_SCALED_REAL -/* 22102 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 22138 -/* 22107 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22110 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22124 -/* 22115 */ MCD_OPC_CheckPredicate, 0, 60, 253, 0, // Skip to: 86948 -/* 22120 */ MCD_OPC_Decode, 135, 13, 127, // Opcode: GLD1H_S_SXTW_REAL -/* 22124 */ MCD_OPC_FilterValue, 1, 51, 253, 0, // Skip to: 86948 -/* 22129 */ MCD_OPC_CheckPredicate, 0, 46, 253, 0, // Skip to: 86948 -/* 22134 */ MCD_OPC_Decode, 136, 13, 127, // Opcode: GLD1H_S_SXTW_SCALED_REAL -/* 22138 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 22174 -/* 22143 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22146 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22160 -/* 22151 */ MCD_OPC_CheckPredicate, 0, 24, 253, 0, // Skip to: 86948 -/* 22156 */ MCD_OPC_Decode, 175, 13, 127, // Opcode: GLD1W_UXTW_REAL -/* 22160 */ MCD_OPC_FilterValue, 1, 15, 253, 0, // Skip to: 86948 -/* 22165 */ MCD_OPC_CheckPredicate, 0, 10, 253, 0, // Skip to: 86948 -/* 22170 */ MCD_OPC_Decode, 176, 13, 127, // Opcode: GLD1W_UXTW_SCALED_REAL -/* 22174 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 22210 -/* 22179 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22182 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22196 -/* 22187 */ MCD_OPC_CheckPredicate, 0, 244, 252, 0, // Skip to: 86948 -/* 22192 */ MCD_OPC_Decode, 173, 13, 127, // Opcode: GLD1W_SXTW_REAL -/* 22196 */ MCD_OPC_FilterValue, 1, 235, 252, 0, // Skip to: 86948 -/* 22201 */ MCD_OPC_CheckPredicate, 0, 230, 252, 0, // Skip to: 86948 -/* 22206 */ MCD_OPC_Decode, 174, 13, 127, // Opcode: GLD1W_SXTW_SCALED_REAL -/* 22210 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 22225 -/* 22215 */ MCD_OPC_CheckPredicate, 0, 216, 252, 0, // Skip to: 86948 -/* 22220 */ MCD_OPC_Decode, 168, 18, 131, 1, // Opcode: LDR_ZXI -/* 22225 */ MCD_OPC_FilterValue, 7, 206, 252, 0, // Skip to: 86948 -/* 22230 */ MCD_OPC_CheckPredicate, 0, 201, 252, 0, // Skip to: 86948 -/* 22235 */ MCD_OPC_CheckField, 4, 1, 0, 194, 252, 0, // Skip to: 86948 -/* 22242 */ MCD_OPC_Decode, 162, 21, 130, 1, // Opcode: PRFW_PRI -/* 22247 */ MCD_OPC_FilterValue, 3, 1, 1, 0, // Skip to: 22509 -/* 22252 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 22255 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 22299 -/* 22260 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22263 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22277 -/* 22268 */ MCD_OPC_CheckPredicate, 0, 163, 252, 0, // Skip to: 86948 -/* 22273 */ MCD_OPC_Decode, 183, 13, 127, // Opcode: GLDFF1B_S_UXTW_REAL -/* 22277 */ MCD_OPC_FilterValue, 1, 154, 252, 0, // Skip to: 86948 -/* 22282 */ MCD_OPC_CheckPredicate, 0, 149, 252, 0, // Skip to: 86948 -/* 22287 */ MCD_OPC_CheckField, 4, 1, 0, 142, 252, 0, // Skip to: 86948 -/* 22294 */ MCD_OPC_Decode, 142, 21, 128, 1, // Opcode: PRFD_S_UXTW_SCALED -/* 22299 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 22343 -/* 22304 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22307 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22321 -/* 22312 */ MCD_OPC_CheckPredicate, 0, 119, 252, 0, // Skip to: 86948 -/* 22317 */ MCD_OPC_Decode, 182, 13, 127, // Opcode: GLDFF1B_S_SXTW_REAL -/* 22321 */ MCD_OPC_FilterValue, 1, 110, 252, 0, // Skip to: 86948 -/* 22326 */ MCD_OPC_CheckPredicate, 0, 105, 252, 0, // Skip to: 86948 -/* 22331 */ MCD_OPC_CheckField, 4, 1, 0, 98, 252, 0, // Skip to: 86948 -/* 22338 */ MCD_OPC_Decode, 141, 21, 128, 1, // Opcode: PRFD_S_SXTW_SCALED -/* 22343 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 22379 -/* 22348 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22351 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22365 -/* 22356 */ MCD_OPC_CheckPredicate, 0, 75, 252, 0, // Skip to: 86948 -/* 22361 */ MCD_OPC_Decode, 201, 13, 127, // Opcode: GLDFF1H_S_UXTW_REAL -/* 22365 */ MCD_OPC_FilterValue, 1, 66, 252, 0, // Skip to: 86948 -/* 22370 */ MCD_OPC_CheckPredicate, 0, 61, 252, 0, // Skip to: 86948 -/* 22375 */ MCD_OPC_Decode, 202, 13, 127, // Opcode: GLDFF1H_S_UXTW_SCALED_REAL -/* 22379 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 22415 -/* 22384 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22387 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22401 -/* 22392 */ MCD_OPC_CheckPredicate, 0, 39, 252, 0, // Skip to: 86948 -/* 22397 */ MCD_OPC_Decode, 199, 13, 127, // Opcode: GLDFF1H_S_SXTW_REAL -/* 22401 */ MCD_OPC_FilterValue, 1, 30, 252, 0, // Skip to: 86948 -/* 22406 */ MCD_OPC_CheckPredicate, 0, 25, 252, 0, // Skip to: 86948 -/* 22411 */ MCD_OPC_Decode, 200, 13, 127, // Opcode: GLDFF1H_S_SXTW_SCALED_REAL -/* 22415 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 22451 -/* 22420 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22423 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22437 -/* 22428 */ MCD_OPC_CheckPredicate, 0, 3, 252, 0, // Skip to: 86948 -/* 22433 */ MCD_OPC_Decode, 239, 13, 127, // Opcode: GLDFF1W_UXTW_REAL -/* 22437 */ MCD_OPC_FilterValue, 1, 250, 251, 0, // Skip to: 86948 -/* 22442 */ MCD_OPC_CheckPredicate, 0, 245, 251, 0, // Skip to: 86948 -/* 22447 */ MCD_OPC_Decode, 240, 13, 127, // Opcode: GLDFF1W_UXTW_SCALED_REAL -/* 22451 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 22487 -/* 22456 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22459 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22473 -/* 22464 */ MCD_OPC_CheckPredicate, 0, 223, 251, 0, // Skip to: 86948 -/* 22469 */ MCD_OPC_Decode, 237, 13, 127, // Opcode: GLDFF1W_SXTW_REAL -/* 22473 */ MCD_OPC_FilterValue, 1, 214, 251, 0, // Skip to: 86948 -/* 22478 */ MCD_OPC_CheckPredicate, 0, 209, 251, 0, // Skip to: 86948 -/* 22483 */ MCD_OPC_Decode, 238, 13, 127, // Opcode: GLDFF1W_SXTW_SCALED_REAL -/* 22487 */ MCD_OPC_FilterValue, 7, 200, 251, 0, // Skip to: 86948 -/* 22492 */ MCD_OPC_CheckPredicate, 0, 195, 251, 0, // Skip to: 86948 -/* 22497 */ MCD_OPC_CheckField, 4, 1, 0, 188, 251, 0, // Skip to: 86948 -/* 22504 */ MCD_OPC_Decode, 138, 21, 130, 1, // Opcode: PRFD_PRI -/* 22509 */ MCD_OPC_FilterValue, 4, 107, 0, 0, // Skip to: 22621 -/* 22514 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 22517 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22539 -/* 22522 */ MCD_OPC_CheckPredicate, 0, 165, 251, 0, // Skip to: 86948 -/* 22527 */ MCD_OPC_CheckField, 21, 1, 1, 158, 251, 0, // Skip to: 86948 -/* 22534 */ MCD_OPC_Decode, 143, 13, 132, 1, // Opcode: GLD1SB_S_IMM_REAL -/* 22539 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 22554 -/* 22544 */ MCD_OPC_CheckPredicate, 0, 143, 251, 0, // Skip to: 86948 -/* 22549 */ MCD_OPC_Decode, 229, 14, 133, 1, // Opcode: LD1RB_IMM -/* 22554 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 22576 -/* 22559 */ MCD_OPC_CheckPredicate, 0, 128, 251, 0, // Skip to: 86948 -/* 22564 */ MCD_OPC_CheckField, 21, 1, 1, 121, 251, 0, // Skip to: 86948 -/* 22571 */ MCD_OPC_Decode, 153, 13, 132, 1, // Opcode: GLD1SH_S_IMM_REAL -/* 22576 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 22591 -/* 22581 */ MCD_OPC_CheckPredicate, 0, 106, 251, 0, // Skip to: 86948 -/* 22586 */ MCD_OPC_Decode, 248, 14, 133, 1, // Opcode: LD1RSW_IMM -/* 22591 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 22606 -/* 22596 */ MCD_OPC_CheckPredicate, 0, 91, 251, 0, // Skip to: 86948 -/* 22601 */ MCD_OPC_Decode, 246, 14, 133, 1, // Opcode: LD1RSH_D_IMM -/* 22606 */ MCD_OPC_FilterValue, 7, 81, 251, 0, // Skip to: 86948 -/* 22611 */ MCD_OPC_CheckPredicate, 0, 76, 251, 0, // Skip to: 86948 -/* 22616 */ MCD_OPC_Decode, 243, 14, 133, 1, // Opcode: LD1RSB_D_IMM -/* 22621 */ MCD_OPC_FilterValue, 5, 107, 0, 0, // Skip to: 22733 -/* 22626 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 22629 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22651 -/* 22634 */ MCD_OPC_CheckPredicate, 0, 53, 251, 0, // Skip to: 86948 -/* 22639 */ MCD_OPC_CheckField, 21, 1, 1, 46, 251, 0, // Skip to: 86948 -/* 22646 */ MCD_OPC_Decode, 207, 13, 132, 1, // Opcode: GLDFF1SB_S_IMM_REAL -/* 22651 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 22666 -/* 22656 */ MCD_OPC_CheckPredicate, 0, 31, 251, 0, // Skip to: 86948 -/* 22661 */ MCD_OPC_Decode, 228, 14, 133, 1, // Opcode: LD1RB_H_IMM -/* 22666 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 22688 -/* 22671 */ MCD_OPC_CheckPredicate, 0, 16, 251, 0, // Skip to: 86948 -/* 22676 */ MCD_OPC_CheckField, 21, 1, 1, 9, 251, 0, // Skip to: 86948 -/* 22683 */ MCD_OPC_Decode, 217, 13, 132, 1, // Opcode: GLDFF1SH_S_IMM_REAL -/* 22688 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 22703 -/* 22693 */ MCD_OPC_CheckPredicate, 0, 250, 250, 0, // Skip to: 86948 -/* 22698 */ MCD_OPC_Decode, 233, 14, 133, 1, // Opcode: LD1RH_IMM -/* 22703 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 22718 -/* 22708 */ MCD_OPC_CheckPredicate, 0, 235, 250, 0, // Skip to: 86948 -/* 22713 */ MCD_OPC_Decode, 247, 14, 133, 1, // Opcode: LD1RSH_S_IMM -/* 22718 */ MCD_OPC_FilterValue, 7, 225, 250, 0, // Skip to: 86948 -/* 22723 */ MCD_OPC_CheckPredicate, 0, 220, 250, 0, // Skip to: 86948 -/* 22728 */ MCD_OPC_Decode, 245, 14, 133, 1, // Opcode: LD1RSB_S_IMM -/* 22733 */ MCD_OPC_FilterValue, 6, 227, 0, 0, // Skip to: 22965 -/* 22738 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 22741 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 22786 -/* 22746 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22749 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22771 -/* 22754 */ MCD_OPC_CheckPredicate, 0, 189, 250, 0, // Skip to: 86948 -/* 22759 */ MCD_OPC_CheckField, 4, 1, 0, 182, 250, 0, // Skip to: 86948 -/* 22766 */ MCD_OPC_Decode, 130, 21, 134, 1, // Opcode: PRFB_PRR -/* 22771 */ MCD_OPC_FilterValue, 1, 172, 250, 0, // Skip to: 86948 -/* 22776 */ MCD_OPC_CheckPredicate, 0, 167, 250, 0, // Skip to: 86948 -/* 22781 */ MCD_OPC_Decode, 245, 12, 132, 1, // Opcode: GLD1B_S_IMM_REAL -/* 22786 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 22801 -/* 22791 */ MCD_OPC_CheckPredicate, 0, 152, 250, 0, // Skip to: 86948 -/* 22796 */ MCD_OPC_Decode, 230, 14, 133, 1, // Opcode: LD1RB_S_IMM -/* 22801 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 22846 -/* 22806 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22809 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22831 -/* 22814 */ MCD_OPC_CheckPredicate, 0, 129, 250, 0, // Skip to: 86948 -/* 22819 */ MCD_OPC_CheckField, 4, 1, 0, 122, 250, 0, // Skip to: 86948 -/* 22826 */ MCD_OPC_Decode, 148, 21, 134, 1, // Opcode: PRFH_PRR -/* 22831 */ MCD_OPC_FilterValue, 1, 112, 250, 0, // Skip to: 86948 -/* 22836 */ MCD_OPC_CheckPredicate, 0, 107, 250, 0, // Skip to: 86948 -/* 22841 */ MCD_OPC_Decode, 134, 13, 132, 1, // Opcode: GLD1H_S_IMM_REAL -/* 22846 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 22861 -/* 22851 */ MCD_OPC_CheckPredicate, 0, 92, 250, 0, // Skip to: 86948 -/* 22856 */ MCD_OPC_Decode, 234, 14, 133, 1, // Opcode: LD1RH_S_IMM -/* 22861 */ MCD_OPC_FilterValue, 4, 40, 0, 0, // Skip to: 22906 -/* 22866 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22869 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22891 -/* 22874 */ MCD_OPC_CheckPredicate, 0, 69, 250, 0, // Skip to: 86948 -/* 22879 */ MCD_OPC_CheckField, 4, 1, 0, 62, 250, 0, // Skip to: 86948 -/* 22886 */ MCD_OPC_Decode, 156, 21, 134, 1, // Opcode: PRFS_PRR -/* 22891 */ MCD_OPC_FilterValue, 1, 52, 250, 0, // Skip to: 86948 -/* 22896 */ MCD_OPC_CheckPredicate, 0, 47, 250, 0, // Skip to: 86948 -/* 22901 */ MCD_OPC_Decode, 172, 13, 132, 1, // Opcode: GLD1W_IMM_REAL -/* 22906 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 22921 -/* 22911 */ MCD_OPC_CheckPredicate, 0, 32, 250, 0, // Skip to: 86948 -/* 22916 */ MCD_OPC_Decode, 250, 14, 133, 1, // Opcode: LD1RW_IMM -/* 22921 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 22950 -/* 22926 */ MCD_OPC_CheckPredicate, 0, 17, 250, 0, // Skip to: 86948 -/* 22931 */ MCD_OPC_CheckField, 21, 1, 0, 10, 250, 0, // Skip to: 86948 -/* 22938 */ MCD_OPC_CheckField, 4, 1, 0, 3, 250, 0, // Skip to: 86948 -/* 22945 */ MCD_OPC_Decode, 139, 21, 134, 1, // Opcode: PRFD_PRR -/* 22950 */ MCD_OPC_FilterValue, 7, 249, 249, 0, // Skip to: 86948 -/* 22955 */ MCD_OPC_CheckPredicate, 0, 244, 249, 0, // Skip to: 86948 -/* 22960 */ MCD_OPC_Decode, 244, 14, 133, 1, // Opcode: LD1RSB_H_IMM -/* 22965 */ MCD_OPC_FilterValue, 7, 234, 249, 0, // Skip to: 86948 -/* 22970 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 22973 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 23018 -/* 22978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22981 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 23003 -/* 22986 */ MCD_OPC_CheckPredicate, 0, 213, 249, 0, // Skip to: 86948 -/* 22991 */ MCD_OPC_CheckField, 4, 1, 0, 206, 249, 0, // Skip to: 86948 -/* 22998 */ MCD_OPC_Decode, 131, 21, 135, 1, // Opcode: PRFB_S_PZI -/* 23003 */ MCD_OPC_FilterValue, 1, 196, 249, 0, // Skip to: 86948 -/* 23008 */ MCD_OPC_CheckPredicate, 0, 191, 249, 0, // Skip to: 86948 -/* 23013 */ MCD_OPC_Decode, 181, 13, 132, 1, // Opcode: GLDFF1B_S_IMM_REAL -/* 23018 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 23033 -/* 23023 */ MCD_OPC_CheckPredicate, 0, 176, 249, 0, // Skip to: 86948 -/* 23028 */ MCD_OPC_Decode, 227, 14, 133, 1, // Opcode: LD1RB_D_IMM -/* 23033 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 23078 -/* 23038 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 23041 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 23063 -/* 23046 */ MCD_OPC_CheckPredicate, 0, 153, 249, 0, // Skip to: 86948 -/* 23051 */ MCD_OPC_CheckField, 4, 1, 0, 146, 249, 0, // Skip to: 86948 -/* 23058 */ MCD_OPC_Decode, 149, 21, 135, 1, // Opcode: PRFH_S_PZI -/* 23063 */ MCD_OPC_FilterValue, 1, 136, 249, 0, // Skip to: 86948 -/* 23068 */ MCD_OPC_CheckPredicate, 0, 131, 249, 0, // Skip to: 86948 -/* 23073 */ MCD_OPC_Decode, 198, 13, 132, 1, // Opcode: GLDFF1H_S_IMM_REAL -/* 23078 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23093 -/* 23083 */ MCD_OPC_CheckPredicate, 0, 116, 249, 0, // Skip to: 86948 -/* 23088 */ MCD_OPC_Decode, 232, 14, 133, 1, // Opcode: LD1RH_D_IMM -/* 23093 */ MCD_OPC_FilterValue, 4, 40, 0, 0, // Skip to: 23138 -/* 23098 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 23101 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 23123 -/* 23106 */ MCD_OPC_CheckPredicate, 0, 93, 249, 0, // Skip to: 86948 -/* 23111 */ MCD_OPC_CheckField, 4, 1, 0, 86, 249, 0, // Skip to: 86948 -/* 23118 */ MCD_OPC_Decode, 163, 21, 135, 1, // Opcode: PRFW_S_PZI -/* 23123 */ MCD_OPC_FilterValue, 1, 76, 249, 0, // Skip to: 86948 -/* 23128 */ MCD_OPC_CheckPredicate, 0, 71, 249, 0, // Skip to: 86948 -/* 23133 */ MCD_OPC_Decode, 236, 13, 132, 1, // Opcode: GLDFF1W_IMM_REAL -/* 23138 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 23153 -/* 23143 */ MCD_OPC_CheckPredicate, 0, 56, 249, 0, // Skip to: 86948 -/* 23148 */ MCD_OPC_Decode, 249, 14, 133, 1, // Opcode: LD1RW_D_IMM -/* 23153 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 23182 -/* 23158 */ MCD_OPC_CheckPredicate, 0, 41, 249, 0, // Skip to: 86948 -/* 23163 */ MCD_OPC_CheckField, 21, 1, 0, 34, 249, 0, // Skip to: 86948 -/* 23170 */ MCD_OPC_CheckField, 4, 1, 0, 27, 249, 0, // Skip to: 86948 -/* 23177 */ MCD_OPC_Decode, 140, 21, 135, 1, // Opcode: PRFD_S_PZI -/* 23182 */ MCD_OPC_FilterValue, 7, 17, 249, 0, // Skip to: 86948 -/* 23187 */ MCD_OPC_CheckPredicate, 0, 12, 249, 0, // Skip to: 86948 -/* 23192 */ MCD_OPC_Decode, 231, 14, 133, 1, // Opcode: LD1RD_IMM -/* 23197 */ MCD_OPC_FilterValue, 5, 167, 7, 0, // Skip to: 25161 -/* 23202 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 23205 */ MCD_OPC_FilterValue, 0, 145, 0, 0, // Skip to: 23355 -/* 23210 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 23213 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23228 -/* 23218 */ MCD_OPC_CheckPredicate, 0, 237, 248, 0, // Skip to: 86948 -/* 23223 */ MCD_OPC_Decode, 235, 14, 136, 1, // Opcode: LD1RQ_B -/* 23228 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 23250 -/* 23233 */ MCD_OPC_CheckPredicate, 0, 222, 248, 0, // Skip to: 86948 -/* 23238 */ MCD_OPC_CheckField, 20, 1, 0, 215, 248, 0, // Skip to: 86948 -/* 23245 */ MCD_OPC_Decode, 236, 14, 137, 1, // Opcode: LD1RQ_B_IMM -/* 23250 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23265 -/* 23255 */ MCD_OPC_CheckPredicate, 0, 200, 248, 0, // Skip to: 86948 -/* 23260 */ MCD_OPC_Decode, 179, 14, 136, 1, // Opcode: LD1B -/* 23265 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23280 -/* 23270 */ MCD_OPC_CheckPredicate, 0, 185, 248, 0, // Skip to: 86948 -/* 23275 */ MCD_OPC_Decode, 150, 17, 138, 1, // Opcode: LDFF1B_REAL -/* 23280 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23318 -/* 23285 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 23288 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23303 -/* 23293 */ MCD_OPC_CheckPredicate, 0, 162, 248, 0, // Skip to: 86948 -/* 23298 */ MCD_OPC_Decode, 184, 14, 137, 1, // Opcode: LD1B_IMM_REAL -/* 23303 */ MCD_OPC_FilterValue, 1, 152, 248, 0, // Skip to: 86948 -/* 23308 */ MCD_OPC_CheckPredicate, 0, 147, 248, 0, // Skip to: 86948 -/* 23313 */ MCD_OPC_Decode, 170, 17, 137, 1, // Opcode: LDNF1B_IMM_REAL -/* 23318 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23333 -/* 23323 */ MCD_OPC_CheckPredicate, 0, 132, 248, 0, // Skip to: 86948 -/* 23328 */ MCD_OPC_Decode, 190, 17, 136, 1, // Opcode: LDNT1B_ZRR -/* 23333 */ MCD_OPC_FilterValue, 7, 122, 248, 0, // Skip to: 86948 -/* 23338 */ MCD_OPC_CheckPredicate, 0, 117, 248, 0, // Skip to: 86948 -/* 23343 */ MCD_OPC_CheckField, 20, 1, 0, 110, 248, 0, // Skip to: 86948 -/* 23350 */ MCD_OPC_Decode, 189, 17, 137, 1, // Opcode: LDNT1B_ZRI -/* 23355 */ MCD_OPC_FilterValue, 1, 108, 0, 0, // Skip to: 23468 -/* 23360 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 23363 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23378 -/* 23368 */ MCD_OPC_CheckPredicate, 0, 87, 248, 0, // Skip to: 86948 -/* 23373 */ MCD_OPC_Decode, 182, 14, 136, 1, // Opcode: LD1B_H -/* 23378 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23393 -/* 23383 */ MCD_OPC_CheckPredicate, 0, 72, 248, 0, // Skip to: 86948 -/* 23388 */ MCD_OPC_Decode, 149, 17, 138, 1, // Opcode: LDFF1B_H_REAL -/* 23393 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23431 -/* 23398 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 23401 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23416 -/* 23406 */ MCD_OPC_CheckPredicate, 0, 49, 248, 0, // Skip to: 86948 -/* 23411 */ MCD_OPC_Decode, 183, 14, 137, 1, // Opcode: LD1B_H_IMM_REAL -/* 23416 */ MCD_OPC_FilterValue, 1, 39, 248, 0, // Skip to: 86948 -/* 23421 */ MCD_OPC_CheckPredicate, 0, 34, 248, 0, // Skip to: 86948 -/* 23426 */ MCD_OPC_Decode, 169, 17, 137, 1, // Opcode: LDNF1B_H_IMM_REAL -/* 23431 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23446 -/* 23436 */ MCD_OPC_CheckPredicate, 0, 19, 248, 0, // Skip to: 86948 -/* 23441 */ MCD_OPC_Decode, 195, 15, 139, 1, // Opcode: LD2B -/* 23446 */ MCD_OPC_FilterValue, 7, 9, 248, 0, // Skip to: 86948 -/* 23451 */ MCD_OPC_CheckPredicate, 0, 4, 248, 0, // Skip to: 86948 -/* 23456 */ MCD_OPC_CheckField, 20, 1, 0, 253, 247, 0, // Skip to: 86948 -/* 23463 */ MCD_OPC_Decode, 196, 15, 140, 1, // Opcode: LD2B_IMM -/* 23468 */ MCD_OPC_FilterValue, 2, 108, 0, 0, // Skip to: 23581 -/* 23473 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 23476 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23491 -/* 23481 */ MCD_OPC_CheckPredicate, 0, 230, 247, 0, // Skip to: 86948 -/* 23486 */ MCD_OPC_Decode, 185, 14, 136, 1, // Opcode: LD1B_S -/* 23491 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23506 -/* 23496 */ MCD_OPC_CheckPredicate, 0, 215, 247, 0, // Skip to: 86948 -/* 23501 */ MCD_OPC_Decode, 151, 17, 138, 1, // Opcode: LDFF1B_S_REAL -/* 23506 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23544 -/* 23511 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 23514 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23529 -/* 23519 */ MCD_OPC_CheckPredicate, 0, 192, 247, 0, // Skip to: 86948 -/* 23524 */ MCD_OPC_Decode, 186, 14, 137, 1, // Opcode: LD1B_S_IMM_REAL -/* 23529 */ MCD_OPC_FilterValue, 1, 182, 247, 0, // Skip to: 86948 -/* 23534 */ MCD_OPC_CheckPredicate, 0, 177, 247, 0, // Skip to: 86948 -/* 23539 */ MCD_OPC_Decode, 171, 17, 137, 1, // Opcode: LDNF1B_S_IMM_REAL -/* 23544 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23559 -/* 23549 */ MCD_OPC_CheckPredicate, 0, 162, 247, 0, // Skip to: 86948 -/* 23554 */ MCD_OPC_Decode, 241, 15, 141, 1, // Opcode: LD3B -/* 23559 */ MCD_OPC_FilterValue, 7, 152, 247, 0, // Skip to: 86948 -/* 23564 */ MCD_OPC_CheckPredicate, 0, 147, 247, 0, // Skip to: 86948 -/* 23569 */ MCD_OPC_CheckField, 20, 1, 0, 140, 247, 0, // Skip to: 86948 -/* 23576 */ MCD_OPC_Decode, 242, 15, 142, 1, // Opcode: LD3B_IMM -/* 23581 */ MCD_OPC_FilterValue, 3, 108, 0, 0, // Skip to: 23694 -/* 23586 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 23589 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23604 -/* 23594 */ MCD_OPC_CheckPredicate, 0, 117, 247, 0, // Skip to: 86948 -/* 23599 */ MCD_OPC_Decode, 180, 14, 136, 1, // Opcode: LD1B_D -/* 23604 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23619 -/* 23609 */ MCD_OPC_CheckPredicate, 0, 102, 247, 0, // Skip to: 86948 -/* 23614 */ MCD_OPC_Decode, 148, 17, 138, 1, // Opcode: LDFF1B_D_REAL -/* 23619 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23657 -/* 23624 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 23627 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23642 -/* 23632 */ MCD_OPC_CheckPredicate, 0, 79, 247, 0, // Skip to: 86948 -/* 23637 */ MCD_OPC_Decode, 181, 14, 137, 1, // Opcode: LD1B_D_IMM_REAL -/* 23642 */ MCD_OPC_FilterValue, 1, 69, 247, 0, // Skip to: 86948 -/* 23647 */ MCD_OPC_CheckPredicate, 0, 64, 247, 0, // Skip to: 86948 -/* 23652 */ MCD_OPC_Decode, 168, 17, 137, 1, // Opcode: LDNF1B_D_IMM_REAL -/* 23657 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23672 -/* 23662 */ MCD_OPC_CheckPredicate, 0, 49, 247, 0, // Skip to: 86948 -/* 23667 */ MCD_OPC_Decode, 159, 16, 143, 1, // Opcode: LD4B -/* 23672 */ MCD_OPC_FilterValue, 7, 39, 247, 0, // Skip to: 86948 -/* 23677 */ MCD_OPC_CheckPredicate, 0, 34, 247, 0, // Skip to: 86948 -/* 23682 */ MCD_OPC_CheckField, 20, 1, 0, 27, 247, 0, // Skip to: 86948 -/* 23689 */ MCD_OPC_Decode, 160, 16, 144, 1, // Opcode: LD4B_IMM -/* 23694 */ MCD_OPC_FilterValue, 4, 145, 0, 0, // Skip to: 23844 -/* 23699 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 23702 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23717 -/* 23707 */ MCD_OPC_CheckPredicate, 0, 4, 247, 0, // Skip to: 86948 -/* 23712 */ MCD_OPC_Decode, 239, 14, 136, 1, // Opcode: LD1RQ_H -/* 23717 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 23739 -/* 23722 */ MCD_OPC_CheckPredicate, 0, 245, 246, 0, // Skip to: 86948 -/* 23727 */ MCD_OPC_CheckField, 20, 1, 0, 238, 246, 0, // Skip to: 86948 -/* 23734 */ MCD_OPC_Decode, 240, 14, 137, 1, // Opcode: LD1RQ_H_IMM -/* 23739 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23754 -/* 23744 */ MCD_OPC_CheckPredicate, 0, 223, 246, 0, // Skip to: 86948 -/* 23749 */ MCD_OPC_Decode, 149, 15, 136, 1, // Opcode: LD1SW_D -/* 23754 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23769 -/* 23759 */ MCD_OPC_CheckPredicate, 0, 208, 246, 0, // Skip to: 86948 -/* 23764 */ MCD_OPC_Decode, 161, 17, 138, 1, // Opcode: LDFF1SW_D_REAL -/* 23769 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23807 -/* 23774 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 23777 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23792 -/* 23782 */ MCD_OPC_CheckPredicate, 0, 185, 246, 0, // Skip to: 86948 -/* 23787 */ MCD_OPC_Decode, 150, 15, 137, 1, // Opcode: LD1SW_D_IMM_REAL -/* 23792 */ MCD_OPC_FilterValue, 1, 175, 246, 0, // Skip to: 86948 -/* 23797 */ MCD_OPC_CheckPredicate, 0, 170, 246, 0, // Skip to: 86948 -/* 23802 */ MCD_OPC_Decode, 181, 17, 137, 1, // Opcode: LDNF1SW_D_IMM_REAL -/* 23807 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23822 -/* 23812 */ MCD_OPC_CheckPredicate, 0, 155, 246, 0, // Skip to: 86948 -/* 23817 */ MCD_OPC_Decode, 194, 17, 136, 1, // Opcode: LDNT1H_ZRR -/* 23822 */ MCD_OPC_FilterValue, 7, 145, 246, 0, // Skip to: 86948 -/* 23827 */ MCD_OPC_CheckPredicate, 0, 140, 246, 0, // Skip to: 86948 -/* 23832 */ MCD_OPC_CheckField, 20, 1, 0, 133, 246, 0, // Skip to: 86948 -/* 23839 */ MCD_OPC_Decode, 193, 17, 137, 1, // Opcode: LDNT1H_ZRI -/* 23844 */ MCD_OPC_FilterValue, 5, 108, 0, 0, // Skip to: 23957 -/* 23849 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 23852 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23867 -/* 23857 */ MCD_OPC_CheckPredicate, 0, 110, 246, 0, // Skip to: 86948 -/* 23862 */ MCD_OPC_Decode, 205, 14, 136, 1, // Opcode: LD1H -/* 23867 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23882 -/* 23872 */ MCD_OPC_CheckPredicate, 0, 95, 246, 0, // Skip to: 86948 -/* 23877 */ MCD_OPC_Decode, 154, 17, 138, 1, // Opcode: LDFF1H_REAL -/* 23882 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23920 -/* 23887 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 23890 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23905 -/* 23895 */ MCD_OPC_CheckPredicate, 0, 72, 246, 0, // Skip to: 86948 -/* 23900 */ MCD_OPC_Decode, 208, 14, 137, 1, // Opcode: LD1H_IMM_REAL -/* 23905 */ MCD_OPC_FilterValue, 1, 62, 246, 0, // Skip to: 86948 -/* 23910 */ MCD_OPC_CheckPredicate, 0, 57, 246, 0, // Skip to: 86948 -/* 23915 */ MCD_OPC_Decode, 174, 17, 137, 1, // Opcode: LDNF1H_IMM_REAL -/* 23920 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23935 -/* 23925 */ MCD_OPC_CheckPredicate, 0, 42, 246, 0, // Skip to: 86948 -/* 23930 */ MCD_OPC_Decode, 199, 15, 139, 1, // Opcode: LD2H -/* 23935 */ MCD_OPC_FilterValue, 7, 32, 246, 0, // Skip to: 86948 -/* 23940 */ MCD_OPC_CheckPredicate, 0, 27, 246, 0, // Skip to: 86948 -/* 23945 */ MCD_OPC_CheckField, 20, 1, 0, 20, 246, 0, // Skip to: 86948 -/* 23952 */ MCD_OPC_Decode, 200, 15, 140, 1, // Opcode: LD2H_IMM -/* 23957 */ MCD_OPC_FilterValue, 6, 108, 0, 0, // Skip to: 24070 -/* 23962 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 23965 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23980 -/* 23970 */ MCD_OPC_CheckPredicate, 0, 253, 245, 0, // Skip to: 86948 -/* 23975 */ MCD_OPC_Decode, 209, 14, 136, 1, // Opcode: LD1H_S -/* 23980 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23995 -/* 23985 */ MCD_OPC_CheckPredicate, 0, 238, 245, 0, // Skip to: 86948 -/* 23990 */ MCD_OPC_Decode, 155, 17, 138, 1, // Opcode: LDFF1H_S_REAL -/* 23995 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24033 -/* 24000 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24003 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24018 -/* 24008 */ MCD_OPC_CheckPredicate, 0, 215, 245, 0, // Skip to: 86948 -/* 24013 */ MCD_OPC_Decode, 210, 14, 137, 1, // Opcode: LD1H_S_IMM_REAL -/* 24018 */ MCD_OPC_FilterValue, 1, 205, 245, 0, // Skip to: 86948 -/* 24023 */ MCD_OPC_CheckPredicate, 0, 200, 245, 0, // Skip to: 86948 -/* 24028 */ MCD_OPC_Decode, 175, 17, 137, 1, // Opcode: LDNF1H_S_IMM_REAL -/* 24033 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24048 -/* 24038 */ MCD_OPC_CheckPredicate, 0, 185, 245, 0, // Skip to: 86948 -/* 24043 */ MCD_OPC_Decode, 245, 15, 141, 1, // Opcode: LD3H -/* 24048 */ MCD_OPC_FilterValue, 7, 175, 245, 0, // Skip to: 86948 -/* 24053 */ MCD_OPC_CheckPredicate, 0, 170, 245, 0, // Skip to: 86948 -/* 24058 */ MCD_OPC_CheckField, 20, 1, 0, 163, 245, 0, // Skip to: 86948 -/* 24065 */ MCD_OPC_Decode, 246, 15, 142, 1, // Opcode: LD3H_IMM -/* 24070 */ MCD_OPC_FilterValue, 7, 108, 0, 0, // Skip to: 24183 -/* 24075 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 24078 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24093 -/* 24083 */ MCD_OPC_CheckPredicate, 0, 140, 245, 0, // Skip to: 86948 -/* 24088 */ MCD_OPC_Decode, 206, 14, 136, 1, // Opcode: LD1H_D -/* 24093 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24108 -/* 24098 */ MCD_OPC_CheckPredicate, 0, 125, 245, 0, // Skip to: 86948 -/* 24103 */ MCD_OPC_Decode, 153, 17, 138, 1, // Opcode: LDFF1H_D_REAL -/* 24108 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24146 -/* 24113 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24116 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24131 -/* 24121 */ MCD_OPC_CheckPredicate, 0, 102, 245, 0, // Skip to: 86948 -/* 24126 */ MCD_OPC_Decode, 207, 14, 137, 1, // Opcode: LD1H_D_IMM_REAL -/* 24131 */ MCD_OPC_FilterValue, 1, 92, 245, 0, // Skip to: 86948 -/* 24136 */ MCD_OPC_CheckPredicate, 0, 87, 245, 0, // Skip to: 86948 -/* 24141 */ MCD_OPC_Decode, 173, 17, 137, 1, // Opcode: LDNF1H_D_IMM_REAL -/* 24146 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24161 -/* 24151 */ MCD_OPC_CheckPredicate, 0, 72, 245, 0, // Skip to: 86948 -/* 24156 */ MCD_OPC_Decode, 177, 16, 143, 1, // Opcode: LD4H -/* 24161 */ MCD_OPC_FilterValue, 7, 62, 245, 0, // Skip to: 86948 -/* 24166 */ MCD_OPC_CheckPredicate, 0, 57, 245, 0, // Skip to: 86948 -/* 24171 */ MCD_OPC_CheckField, 20, 1, 0, 50, 245, 0, // Skip to: 86948 -/* 24178 */ MCD_OPC_Decode, 178, 16, 144, 1, // Opcode: LD4H_IMM -/* 24183 */ MCD_OPC_FilterValue, 8, 145, 0, 0, // Skip to: 24333 -/* 24188 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 24191 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24206 -/* 24196 */ MCD_OPC_CheckPredicate, 0, 27, 245, 0, // Skip to: 86948 -/* 24201 */ MCD_OPC_Decode, 241, 14, 136, 1, // Opcode: LD1RQ_W -/* 24206 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 24228 -/* 24211 */ MCD_OPC_CheckPredicate, 0, 12, 245, 0, // Skip to: 86948 -/* 24216 */ MCD_OPC_CheckField, 20, 1, 0, 5, 245, 0, // Skip to: 86948 -/* 24223 */ MCD_OPC_Decode, 242, 14, 137, 1, // Opcode: LD1RQ_W_IMM -/* 24228 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24243 -/* 24233 */ MCD_OPC_CheckPredicate, 0, 246, 244, 0, // Skip to: 86948 -/* 24238 */ MCD_OPC_Decode, 145, 15, 136, 1, // Opcode: LD1SH_D -/* 24243 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24258 -/* 24248 */ MCD_OPC_CheckPredicate, 0, 231, 244, 0, // Skip to: 86948 -/* 24253 */ MCD_OPC_Decode, 159, 17, 138, 1, // Opcode: LDFF1SH_D_REAL -/* 24258 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24296 -/* 24263 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24266 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24281 -/* 24271 */ MCD_OPC_CheckPredicate, 0, 208, 244, 0, // Skip to: 86948 -/* 24276 */ MCD_OPC_Decode, 146, 15, 137, 1, // Opcode: LD1SH_D_IMM_REAL -/* 24281 */ MCD_OPC_FilterValue, 1, 198, 244, 0, // Skip to: 86948 -/* 24286 */ MCD_OPC_CheckPredicate, 0, 193, 244, 0, // Skip to: 86948 -/* 24291 */ MCD_OPC_Decode, 179, 17, 137, 1, // Opcode: LDNF1SH_D_IMM_REAL -/* 24296 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24311 -/* 24301 */ MCD_OPC_CheckPredicate, 0, 178, 244, 0, // Skip to: 86948 -/* 24306 */ MCD_OPC_Decode, 196, 17, 136, 1, // Opcode: LDNT1W_ZRR -/* 24311 */ MCD_OPC_FilterValue, 7, 168, 244, 0, // Skip to: 86948 -/* 24316 */ MCD_OPC_CheckPredicate, 0, 163, 244, 0, // Skip to: 86948 -/* 24321 */ MCD_OPC_CheckField, 20, 1, 0, 156, 244, 0, // Skip to: 86948 -/* 24328 */ MCD_OPC_Decode, 195, 17, 137, 1, // Opcode: LDNT1W_ZRI -/* 24333 */ MCD_OPC_FilterValue, 9, 108, 0, 0, // Skip to: 24446 -/* 24338 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 24341 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24356 -/* 24346 */ MCD_OPC_CheckPredicate, 0, 133, 244, 0, // Skip to: 86948 -/* 24351 */ MCD_OPC_Decode, 147, 15, 136, 1, // Opcode: LD1SH_S -/* 24356 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24371 -/* 24361 */ MCD_OPC_CheckPredicate, 0, 118, 244, 0, // Skip to: 86948 -/* 24366 */ MCD_OPC_Decode, 160, 17, 138, 1, // Opcode: LDFF1SH_S_REAL -/* 24371 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24409 -/* 24376 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24379 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24394 -/* 24384 */ MCD_OPC_CheckPredicate, 0, 95, 244, 0, // Skip to: 86948 -/* 24389 */ MCD_OPC_Decode, 148, 15, 137, 1, // Opcode: LD1SH_S_IMM_REAL -/* 24394 */ MCD_OPC_FilterValue, 1, 85, 244, 0, // Skip to: 86948 -/* 24399 */ MCD_OPC_CheckPredicate, 0, 80, 244, 0, // Skip to: 86948 -/* 24404 */ MCD_OPC_Decode, 180, 17, 137, 1, // Opcode: LDNF1SH_S_IMM_REAL -/* 24409 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24424 -/* 24414 */ MCD_OPC_CheckPredicate, 0, 65, 244, 0, // Skip to: 86948 -/* 24419 */ MCD_OPC_Decode, 231, 15, 139, 1, // Opcode: LD2W -/* 24424 */ MCD_OPC_FilterValue, 7, 55, 244, 0, // Skip to: 86948 -/* 24429 */ MCD_OPC_CheckPredicate, 0, 50, 244, 0, // Skip to: 86948 -/* 24434 */ MCD_OPC_CheckField, 20, 1, 0, 43, 244, 0, // Skip to: 86948 -/* 24441 */ MCD_OPC_Decode, 232, 15, 140, 1, // Opcode: LD2W_IMM -/* 24446 */ MCD_OPC_FilterValue, 10, 108, 0, 0, // Skip to: 24559 -/* 24451 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 24454 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24469 -/* 24459 */ MCD_OPC_CheckPredicate, 0, 20, 244, 0, // Skip to: 86948 -/* 24464 */ MCD_OPC_Decode, 183, 15, 136, 1, // Opcode: LD1W -/* 24469 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24484 -/* 24474 */ MCD_OPC_CheckPredicate, 0, 5, 244, 0, // Skip to: 86948 -/* 24479 */ MCD_OPC_Decode, 163, 17, 138, 1, // Opcode: LDFF1W_REAL -/* 24484 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24522 -/* 24489 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24492 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24507 -/* 24497 */ MCD_OPC_CheckPredicate, 0, 238, 243, 0, // Skip to: 86948 -/* 24502 */ MCD_OPC_Decode, 186, 15, 137, 1, // Opcode: LD1W_IMM_REAL -/* 24507 */ MCD_OPC_FilterValue, 1, 228, 243, 0, // Skip to: 86948 -/* 24512 */ MCD_OPC_CheckPredicate, 0, 223, 243, 0, // Skip to: 86948 -/* 24517 */ MCD_OPC_Decode, 183, 17, 137, 1, // Opcode: LDNF1W_IMM_REAL -/* 24522 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24537 -/* 24527 */ MCD_OPC_CheckPredicate, 0, 208, 243, 0, // Skip to: 86948 -/* 24532 */ MCD_OPC_Decode, 149, 16, 141, 1, // Opcode: LD3W -/* 24537 */ MCD_OPC_FilterValue, 7, 198, 243, 0, // Skip to: 86948 -/* 24542 */ MCD_OPC_CheckPredicate, 0, 193, 243, 0, // Skip to: 86948 -/* 24547 */ MCD_OPC_CheckField, 20, 1, 0, 186, 243, 0, // Skip to: 86948 -/* 24554 */ MCD_OPC_Decode, 150, 16, 142, 1, // Opcode: LD3W_IMM -/* 24559 */ MCD_OPC_FilterValue, 11, 108, 0, 0, // Skip to: 24672 -/* 24564 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 24567 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24582 -/* 24572 */ MCD_OPC_CheckPredicate, 0, 163, 243, 0, // Skip to: 86948 -/* 24577 */ MCD_OPC_Decode, 184, 15, 136, 1, // Opcode: LD1W_D -/* 24582 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24597 -/* 24587 */ MCD_OPC_CheckPredicate, 0, 148, 243, 0, // Skip to: 86948 -/* 24592 */ MCD_OPC_Decode, 162, 17, 138, 1, // Opcode: LDFF1W_D_REAL -/* 24597 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24635 -/* 24602 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24605 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24620 -/* 24610 */ MCD_OPC_CheckPredicate, 0, 125, 243, 0, // Skip to: 86948 -/* 24615 */ MCD_OPC_Decode, 185, 15, 137, 1, // Opcode: LD1W_D_IMM_REAL -/* 24620 */ MCD_OPC_FilterValue, 1, 115, 243, 0, // Skip to: 86948 -/* 24625 */ MCD_OPC_CheckPredicate, 0, 110, 243, 0, // Skip to: 86948 -/* 24630 */ MCD_OPC_Decode, 182, 17, 137, 1, // Opcode: LDNF1W_D_IMM_REAL -/* 24635 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24650 -/* 24640 */ MCD_OPC_CheckPredicate, 0, 95, 243, 0, // Skip to: 86948 -/* 24645 */ MCD_OPC_Decode, 195, 16, 143, 1, // Opcode: LD4W -/* 24650 */ MCD_OPC_FilterValue, 7, 85, 243, 0, // Skip to: 86948 -/* 24655 */ MCD_OPC_CheckPredicate, 0, 80, 243, 0, // Skip to: 86948 -/* 24660 */ MCD_OPC_CheckField, 20, 1, 0, 73, 243, 0, // Skip to: 86948 -/* 24667 */ MCD_OPC_Decode, 196, 16, 144, 1, // Opcode: LD4W_IMM -/* 24672 */ MCD_OPC_FilterValue, 12, 145, 0, 0, // Skip to: 24822 -/* 24677 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 24680 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24695 -/* 24685 */ MCD_OPC_CheckPredicate, 0, 50, 243, 0, // Skip to: 86948 -/* 24690 */ MCD_OPC_Decode, 237, 14, 136, 1, // Opcode: LD1RQ_D -/* 24695 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 24717 -/* 24700 */ MCD_OPC_CheckPredicate, 0, 35, 243, 0, // Skip to: 86948 -/* 24705 */ MCD_OPC_CheckField, 20, 1, 0, 28, 243, 0, // Skip to: 86948 -/* 24712 */ MCD_OPC_Decode, 238, 14, 137, 1, // Opcode: LD1RQ_D_IMM -/* 24717 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24732 -/* 24722 */ MCD_OPC_CheckPredicate, 0, 13, 243, 0, // Skip to: 86948 -/* 24727 */ MCD_OPC_Decode, 139, 15, 136, 1, // Opcode: LD1SB_D -/* 24732 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24747 -/* 24737 */ MCD_OPC_CheckPredicate, 0, 254, 242, 0, // Skip to: 86948 -/* 24742 */ MCD_OPC_Decode, 156, 17, 138, 1, // Opcode: LDFF1SB_D_REAL -/* 24747 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24785 -/* 24752 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24755 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24770 -/* 24760 */ MCD_OPC_CheckPredicate, 0, 231, 242, 0, // Skip to: 86948 -/* 24765 */ MCD_OPC_Decode, 140, 15, 137, 1, // Opcode: LD1SB_D_IMM_REAL -/* 24770 */ MCD_OPC_FilterValue, 1, 221, 242, 0, // Skip to: 86948 -/* 24775 */ MCD_OPC_CheckPredicate, 0, 216, 242, 0, // Skip to: 86948 -/* 24780 */ MCD_OPC_Decode, 176, 17, 137, 1, // Opcode: LDNF1SB_D_IMM_REAL -/* 24785 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24800 -/* 24790 */ MCD_OPC_CheckPredicate, 0, 201, 242, 0, // Skip to: 86948 -/* 24795 */ MCD_OPC_Decode, 192, 17, 136, 1, // Opcode: LDNT1D_ZRR -/* 24800 */ MCD_OPC_FilterValue, 7, 191, 242, 0, // Skip to: 86948 -/* 24805 */ MCD_OPC_CheckPredicate, 0, 186, 242, 0, // Skip to: 86948 -/* 24810 */ MCD_OPC_CheckField, 20, 1, 0, 179, 242, 0, // Skip to: 86948 -/* 24817 */ MCD_OPC_Decode, 191, 17, 137, 1, // Opcode: LDNT1D_ZRI -/* 24822 */ MCD_OPC_FilterValue, 13, 108, 0, 0, // Skip to: 24935 -/* 24827 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 24830 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24845 -/* 24835 */ MCD_OPC_CheckPredicate, 0, 156, 242, 0, // Skip to: 86948 -/* 24840 */ MCD_OPC_Decode, 143, 15, 136, 1, // Opcode: LD1SB_S -/* 24845 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24860 -/* 24850 */ MCD_OPC_CheckPredicate, 0, 141, 242, 0, // Skip to: 86948 -/* 24855 */ MCD_OPC_Decode, 158, 17, 138, 1, // Opcode: LDFF1SB_S_REAL -/* 24860 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24898 -/* 24865 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24868 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24883 -/* 24873 */ MCD_OPC_CheckPredicate, 0, 118, 242, 0, // Skip to: 86948 -/* 24878 */ MCD_OPC_Decode, 144, 15, 137, 1, // Opcode: LD1SB_S_IMM_REAL -/* 24883 */ MCD_OPC_FilterValue, 1, 108, 242, 0, // Skip to: 86948 -/* 24888 */ MCD_OPC_CheckPredicate, 0, 103, 242, 0, // Skip to: 86948 -/* 24893 */ MCD_OPC_Decode, 178, 17, 137, 1, // Opcode: LDNF1SB_S_IMM_REAL -/* 24898 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24913 -/* 24903 */ MCD_OPC_CheckPredicate, 0, 88, 242, 0, // Skip to: 86948 -/* 24908 */ MCD_OPC_Decode, 197, 15, 139, 1, // Opcode: LD2D -/* 24913 */ MCD_OPC_FilterValue, 7, 78, 242, 0, // Skip to: 86948 -/* 24918 */ MCD_OPC_CheckPredicate, 0, 73, 242, 0, // Skip to: 86948 -/* 24923 */ MCD_OPC_CheckField, 20, 1, 0, 66, 242, 0, // Skip to: 86948 -/* 24930 */ MCD_OPC_Decode, 198, 15, 140, 1, // Opcode: LD2D_IMM -/* 24935 */ MCD_OPC_FilterValue, 14, 108, 0, 0, // Skip to: 25048 -/* 24940 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 24943 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24958 -/* 24948 */ MCD_OPC_CheckPredicate, 0, 43, 242, 0, // Skip to: 86948 -/* 24953 */ MCD_OPC_Decode, 141, 15, 136, 1, // Opcode: LD1SB_H -/* 24958 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24973 -/* 24963 */ MCD_OPC_CheckPredicate, 0, 28, 242, 0, // Skip to: 86948 -/* 24968 */ MCD_OPC_Decode, 157, 17, 138, 1, // Opcode: LDFF1SB_H_REAL -/* 24973 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 25011 -/* 24978 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24981 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24996 -/* 24986 */ MCD_OPC_CheckPredicate, 0, 5, 242, 0, // Skip to: 86948 -/* 24991 */ MCD_OPC_Decode, 142, 15, 137, 1, // Opcode: LD1SB_H_IMM_REAL -/* 24996 */ MCD_OPC_FilterValue, 1, 251, 241, 0, // Skip to: 86948 -/* 25001 */ MCD_OPC_CheckPredicate, 0, 246, 241, 0, // Skip to: 86948 -/* 25006 */ MCD_OPC_Decode, 177, 17, 137, 1, // Opcode: LDNF1SB_H_IMM_REAL -/* 25011 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25026 -/* 25016 */ MCD_OPC_CheckPredicate, 0, 231, 241, 0, // Skip to: 86948 -/* 25021 */ MCD_OPC_Decode, 243, 15, 141, 1, // Opcode: LD3D -/* 25026 */ MCD_OPC_FilterValue, 7, 221, 241, 0, // Skip to: 86948 -/* 25031 */ MCD_OPC_CheckPredicate, 0, 216, 241, 0, // Skip to: 86948 -/* 25036 */ MCD_OPC_CheckField, 20, 1, 0, 209, 241, 0, // Skip to: 86948 -/* 25043 */ MCD_OPC_Decode, 244, 15, 142, 1, // Opcode: LD3D_IMM -/* 25048 */ MCD_OPC_FilterValue, 15, 199, 241, 0, // Skip to: 86948 -/* 25053 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 25056 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 25071 -/* 25061 */ MCD_OPC_CheckPredicate, 0, 186, 241, 0, // Skip to: 86948 -/* 25066 */ MCD_OPC_Decode, 187, 14, 136, 1, // Opcode: LD1D -/* 25071 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 25086 -/* 25076 */ MCD_OPC_CheckPredicate, 0, 171, 241, 0, // Skip to: 86948 -/* 25081 */ MCD_OPC_Decode, 152, 17, 138, 1, // Opcode: LDFF1D_REAL -/* 25086 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 25124 -/* 25091 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 25094 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 25109 -/* 25099 */ MCD_OPC_CheckPredicate, 0, 148, 241, 0, // Skip to: 86948 -/* 25104 */ MCD_OPC_Decode, 188, 14, 137, 1, // Opcode: LD1D_IMM_REAL -/* 25109 */ MCD_OPC_FilterValue, 1, 138, 241, 0, // Skip to: 86948 -/* 25114 */ MCD_OPC_CheckPredicate, 0, 133, 241, 0, // Skip to: 86948 -/* 25119 */ MCD_OPC_Decode, 172, 17, 137, 1, // Opcode: LDNF1D_IMM_REAL -/* 25124 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25139 -/* 25129 */ MCD_OPC_CheckPredicate, 0, 118, 241, 0, // Skip to: 86948 -/* 25134 */ MCD_OPC_Decode, 161, 16, 143, 1, // Opcode: LD4D -/* 25139 */ MCD_OPC_FilterValue, 7, 108, 241, 0, // Skip to: 86948 -/* 25144 */ MCD_OPC_CheckPredicate, 0, 103, 241, 0, // Skip to: 86948 -/* 25149 */ MCD_OPC_CheckField, 20, 1, 0, 96, 241, 0, // Skip to: 86948 -/* 25156 */ MCD_OPC_Decode, 162, 16, 144, 1, // Opcode: LD4D_IMM -/* 25161 */ MCD_OPC_FilterValue, 6, 165, 6, 0, // Skip to: 26867 -/* 25166 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 25169 */ MCD_OPC_FilterValue, 0, 81, 0, 0, // Skip to: 25255 -/* 25174 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 25177 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25191 -/* 25182 */ MCD_OPC_CheckPredicate, 0, 65, 241, 0, // Skip to: 86948 -/* 25187 */ MCD_OPC_Decode, 142, 13, 127, // Opcode: GLD1SB_D_UXTW_REAL -/* 25191 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25205 -/* 25196 */ MCD_OPC_CheckPredicate, 0, 51, 241, 0, // Skip to: 86948 -/* 25201 */ MCD_OPC_Decode, 206, 13, 127, // Opcode: GLDFF1SB_D_UXTW_REAL -/* 25205 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25219 -/* 25210 */ MCD_OPC_CheckPredicate, 0, 37, 241, 0, // Skip to: 86948 -/* 25215 */ MCD_OPC_Decode, 244, 12, 127, // Opcode: GLD1B_D_UXTW_REAL -/* 25219 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25233 -/* 25224 */ MCD_OPC_CheckPredicate, 0, 23, 241, 0, // Skip to: 86948 -/* 25229 */ MCD_OPC_Decode, 180, 13, 127, // Opcode: GLDFF1B_D_UXTW_REAL -/* 25233 */ MCD_OPC_FilterValue, 7, 14, 241, 0, // Skip to: 86948 -/* 25238 */ MCD_OPC_CheckPredicate, 0, 9, 241, 0, // Skip to: 86948 -/* 25243 */ MCD_OPC_CheckField, 4, 1, 0, 2, 241, 0, // Skip to: 86948 -/* 25250 */ MCD_OPC_Decode, 253, 20, 135, 1, // Opcode: PRFB_D_PZI -/* 25255 */ MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 25411 -/* 25260 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 25263 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25285 -/* 25268 */ MCD_OPC_CheckPredicate, 0, 235, 240, 0, // Skip to: 86948 -/* 25273 */ MCD_OPC_CheckField, 4, 1, 0, 228, 240, 0, // Skip to: 86948 -/* 25280 */ MCD_OPC_Decode, 128, 21, 128, 1, // Opcode: PRFB_D_UXTW_SCALED -/* 25285 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 25307 -/* 25290 */ MCD_OPC_CheckPredicate, 0, 213, 240, 0, // Skip to: 86948 -/* 25295 */ MCD_OPC_CheckField, 4, 1, 0, 206, 240, 0, // Skip to: 86948 -/* 25302 */ MCD_OPC_Decode, 146, 21, 128, 1, // Opcode: PRFH_D_UXTW_SCALED -/* 25307 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 25329 -/* 25312 */ MCD_OPC_CheckPredicate, 0, 191, 240, 0, // Skip to: 86948 -/* 25317 */ MCD_OPC_CheckField, 4, 1, 0, 184, 240, 0, // Skip to: 86948 -/* 25324 */ MCD_OPC_Decode, 161, 21, 128, 1, // Opcode: PRFW_D_UXTW_SCALED -/* 25329 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 25351 -/* 25334 */ MCD_OPC_CheckPredicate, 0, 169, 240, 0, // Skip to: 86948 -/* 25339 */ MCD_OPC_CheckField, 4, 1, 0, 162, 240, 0, // Skip to: 86948 -/* 25346 */ MCD_OPC_Decode, 137, 21, 128, 1, // Opcode: PRFD_D_UXTW_SCALED -/* 25351 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 25366 -/* 25356 */ MCD_OPC_CheckPredicate, 0, 147, 240, 0, // Skip to: 86948 -/* 25361 */ MCD_OPC_Decode, 139, 13, 132, 1, // Opcode: GLD1SB_D_IMM_REAL -/* 25366 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 25381 -/* 25371 */ MCD_OPC_CheckPredicate, 0, 132, 240, 0, // Skip to: 86948 -/* 25376 */ MCD_OPC_Decode, 203, 13, 132, 1, // Opcode: GLDFF1SB_D_IMM_REAL -/* 25381 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25396 -/* 25386 */ MCD_OPC_CheckPredicate, 0, 117, 240, 0, // Skip to: 86948 -/* 25391 */ MCD_OPC_Decode, 241, 12, 132, 1, // Opcode: GLD1B_D_IMM_REAL -/* 25396 */ MCD_OPC_FilterValue, 7, 107, 240, 0, // Skip to: 86948 -/* 25401 */ MCD_OPC_CheckPredicate, 0, 102, 240, 0, // Skip to: 86948 -/* 25406 */ MCD_OPC_Decode, 177, 13, 132, 1, // Opcode: GLDFF1B_D_IMM_REAL -/* 25411 */ MCD_OPC_FilterValue, 2, 115, 0, 0, // Skip to: 25531 -/* 25416 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 25419 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25433 -/* 25424 */ MCD_OPC_CheckPredicate, 0, 79, 240, 0, // Skip to: 86948 -/* 25429 */ MCD_OPC_Decode, 141, 13, 127, // Opcode: GLD1SB_D_SXTW_REAL -/* 25433 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25447 -/* 25438 */ MCD_OPC_CheckPredicate, 0, 65, 240, 0, // Skip to: 86948 -/* 25443 */ MCD_OPC_Decode, 205, 13, 127, // Opcode: GLDFF1SB_D_SXTW_REAL -/* 25447 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25461 -/* 25452 */ MCD_OPC_CheckPredicate, 0, 51, 240, 0, // Skip to: 86948 -/* 25457 */ MCD_OPC_Decode, 243, 12, 127, // Opcode: GLD1B_D_SXTW_REAL -/* 25461 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25475 -/* 25466 */ MCD_OPC_CheckPredicate, 0, 37, 240, 0, // Skip to: 86948 -/* 25471 */ MCD_OPC_Decode, 179, 13, 127, // Opcode: GLDFF1B_D_SXTW_REAL -/* 25475 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 25489 -/* 25480 */ MCD_OPC_CheckPredicate, 0, 23, 240, 0, // Skip to: 86948 -/* 25485 */ MCD_OPC_Decode, 140, 13, 127, // Opcode: GLD1SB_D_REAL -/* 25489 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 25503 -/* 25494 */ MCD_OPC_CheckPredicate, 0, 9, 240, 0, // Skip to: 86948 -/* 25499 */ MCD_OPC_Decode, 204, 13, 127, // Opcode: GLDFF1SB_D_REAL -/* 25503 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 25517 -/* 25508 */ MCD_OPC_CheckPredicate, 0, 251, 239, 0, // Skip to: 86948 -/* 25513 */ MCD_OPC_Decode, 242, 12, 127, // Opcode: GLD1B_D_REAL -/* 25517 */ MCD_OPC_FilterValue, 7, 242, 239, 0, // Skip to: 86948 -/* 25522 */ MCD_OPC_CheckPredicate, 0, 237, 239, 0, // Skip to: 86948 -/* 25527 */ MCD_OPC_Decode, 178, 13, 127, // Opcode: GLDFF1B_D_REAL -/* 25531 */ MCD_OPC_FilterValue, 3, 179, 0, 0, // Skip to: 25715 -/* 25536 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 25539 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25561 -/* 25544 */ MCD_OPC_CheckPredicate, 0, 215, 239, 0, // Skip to: 86948 -/* 25549 */ MCD_OPC_CheckField, 4, 1, 0, 208, 239, 0, // Skip to: 86948 -/* 25556 */ MCD_OPC_Decode, 255, 20, 128, 1, // Opcode: PRFB_D_SXTW_SCALED -/* 25561 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 25583 -/* 25566 */ MCD_OPC_CheckPredicate, 0, 193, 239, 0, // Skip to: 86948 -/* 25571 */ MCD_OPC_CheckField, 4, 1, 0, 186, 239, 0, // Skip to: 86948 -/* 25578 */ MCD_OPC_Decode, 145, 21, 128, 1, // Opcode: PRFH_D_SXTW_SCALED -/* 25583 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 25605 -/* 25588 */ MCD_OPC_CheckPredicate, 0, 171, 239, 0, // Skip to: 86948 -/* 25593 */ MCD_OPC_CheckField, 4, 1, 0, 164, 239, 0, // Skip to: 86948 -/* 25600 */ MCD_OPC_Decode, 160, 21, 128, 1, // Opcode: PRFW_D_SXTW_SCALED -/* 25605 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 25627 -/* 25610 */ MCD_OPC_CheckPredicate, 0, 149, 239, 0, // Skip to: 86948 -/* 25615 */ MCD_OPC_CheckField, 4, 1, 0, 142, 239, 0, // Skip to: 86948 -/* 25622 */ MCD_OPC_Decode, 136, 21, 128, 1, // Opcode: PRFD_D_SXTW_SCALED -/* 25627 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 25649 -/* 25632 */ MCD_OPC_CheckPredicate, 0, 127, 239, 0, // Skip to: 86948 -/* 25637 */ MCD_OPC_CheckField, 4, 1, 0, 120, 239, 0, // Skip to: 86948 -/* 25644 */ MCD_OPC_Decode, 254, 20, 128, 1, // Opcode: PRFB_D_SCALED -/* 25649 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 25671 -/* 25654 */ MCD_OPC_CheckPredicate, 0, 105, 239, 0, // Skip to: 86948 -/* 25659 */ MCD_OPC_CheckField, 4, 1, 0, 98, 239, 0, // Skip to: 86948 -/* 25666 */ MCD_OPC_Decode, 144, 21, 128, 1, // Opcode: PRFH_D_SCALED -/* 25671 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 25693 -/* 25676 */ MCD_OPC_CheckPredicate, 0, 83, 239, 0, // Skip to: 86948 -/* 25681 */ MCD_OPC_CheckField, 4, 1, 0, 76, 239, 0, // Skip to: 86948 -/* 25688 */ MCD_OPC_Decode, 159, 21, 128, 1, // Opcode: PRFW_D_SCALED -/* 25693 */ MCD_OPC_FilterValue, 7, 66, 239, 0, // Skip to: 86948 -/* 25698 */ MCD_OPC_CheckPredicate, 0, 61, 239, 0, // Skip to: 86948 -/* 25703 */ MCD_OPC_CheckField, 4, 1, 0, 54, 239, 0, // Skip to: 86948 -/* 25710 */ MCD_OPC_Decode, 135, 21, 128, 1, // Opcode: PRFD_D_SCALED -/* 25715 */ MCD_OPC_FilterValue, 4, 81, 0, 0, // Skip to: 25801 -/* 25720 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 25723 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25737 -/* 25728 */ MCD_OPC_CheckPredicate, 0, 31, 239, 0, // Skip to: 86948 -/* 25733 */ MCD_OPC_Decode, 151, 13, 127, // Opcode: GLD1SH_D_UXTW_REAL -/* 25737 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25751 -/* 25742 */ MCD_OPC_CheckPredicate, 0, 17, 239, 0, // Skip to: 86948 -/* 25747 */ MCD_OPC_Decode, 215, 13, 127, // Opcode: GLDFF1SH_D_UXTW_REAL -/* 25751 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25765 -/* 25756 */ MCD_OPC_CheckPredicate, 0, 3, 239, 0, // Skip to: 86948 -/* 25761 */ MCD_OPC_Decode, 132, 13, 127, // Opcode: GLD1H_D_UXTW_REAL -/* 25765 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25779 -/* 25770 */ MCD_OPC_CheckPredicate, 0, 245, 238, 0, // Skip to: 86948 -/* 25775 */ MCD_OPC_Decode, 196, 13, 127, // Opcode: GLDFF1H_D_UXTW_REAL -/* 25779 */ MCD_OPC_FilterValue, 7, 236, 238, 0, // Skip to: 86948 -/* 25784 */ MCD_OPC_CheckPredicate, 0, 231, 238, 0, // Skip to: 86948 -/* 25789 */ MCD_OPC_CheckField, 4, 1, 0, 224, 238, 0, // Skip to: 86948 -/* 25796 */ MCD_OPC_Decode, 143, 21, 135, 1, // Opcode: PRFH_D_PZI -/* 25801 */ MCD_OPC_FilterValue, 5, 119, 0, 0, // Skip to: 25925 -/* 25806 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 25809 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25823 -/* 25814 */ MCD_OPC_CheckPredicate, 0, 201, 238, 0, // Skip to: 86948 -/* 25819 */ MCD_OPC_Decode, 152, 13, 127, // Opcode: GLD1SH_D_UXTW_SCALED_REAL -/* 25823 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25837 -/* 25828 */ MCD_OPC_CheckPredicate, 0, 187, 238, 0, // Skip to: 86948 -/* 25833 */ MCD_OPC_Decode, 216, 13, 127, // Opcode: GLDFF1SH_D_UXTW_SCALED_REAL -/* 25837 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25851 -/* 25842 */ MCD_OPC_CheckPredicate, 0, 173, 238, 0, // Skip to: 86948 -/* 25847 */ MCD_OPC_Decode, 133, 13, 127, // Opcode: GLD1H_D_UXTW_SCALED_REAL -/* 25851 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25865 -/* 25856 */ MCD_OPC_CheckPredicate, 0, 159, 238, 0, // Skip to: 86948 -/* 25861 */ MCD_OPC_Decode, 197, 13, 127, // Opcode: GLDFF1H_D_UXTW_SCALED_REAL -/* 25865 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 25880 -/* 25870 */ MCD_OPC_CheckPredicate, 0, 145, 238, 0, // Skip to: 86948 -/* 25875 */ MCD_OPC_Decode, 146, 13, 132, 1, // Opcode: GLD1SH_D_IMM_REAL -/* 25880 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 25895 -/* 25885 */ MCD_OPC_CheckPredicate, 0, 130, 238, 0, // Skip to: 86948 -/* 25890 */ MCD_OPC_Decode, 210, 13, 132, 1, // Opcode: GLDFF1SH_D_IMM_REAL -/* 25895 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25910 -/* 25900 */ MCD_OPC_CheckPredicate, 0, 115, 238, 0, // Skip to: 86948 -/* 25905 */ MCD_OPC_Decode, 255, 12, 132, 1, // Opcode: GLD1H_D_IMM_REAL -/* 25910 */ MCD_OPC_FilterValue, 7, 105, 238, 0, // Skip to: 86948 -/* 25915 */ MCD_OPC_CheckPredicate, 0, 100, 238, 0, // Skip to: 86948 -/* 25920 */ MCD_OPC_Decode, 191, 13, 132, 1, // Opcode: GLDFF1H_D_IMM_REAL -/* 25925 */ MCD_OPC_FilterValue, 6, 115, 0, 0, // Skip to: 26045 -/* 25930 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 25933 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25947 -/* 25938 */ MCD_OPC_CheckPredicate, 0, 77, 238, 0, // Skip to: 86948 -/* 25943 */ MCD_OPC_Decode, 149, 13, 127, // Opcode: GLD1SH_D_SXTW_REAL -/* 25947 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25961 -/* 25952 */ MCD_OPC_CheckPredicate, 0, 63, 238, 0, // Skip to: 86948 -/* 25957 */ MCD_OPC_Decode, 213, 13, 127, // Opcode: GLDFF1SH_D_SXTW_REAL -/* 25961 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25975 -/* 25966 */ MCD_OPC_CheckPredicate, 0, 49, 238, 0, // Skip to: 86948 -/* 25971 */ MCD_OPC_Decode, 130, 13, 127, // Opcode: GLD1H_D_SXTW_REAL -/* 25975 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25989 -/* 25980 */ MCD_OPC_CheckPredicate, 0, 35, 238, 0, // Skip to: 86948 -/* 25985 */ MCD_OPC_Decode, 194, 13, 127, // Opcode: GLDFF1H_D_SXTW_REAL -/* 25989 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26003 -/* 25994 */ MCD_OPC_CheckPredicate, 0, 21, 238, 0, // Skip to: 86948 -/* 25999 */ MCD_OPC_Decode, 147, 13, 127, // Opcode: GLD1SH_D_REAL -/* 26003 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26017 -/* 26008 */ MCD_OPC_CheckPredicate, 0, 7, 238, 0, // Skip to: 86948 -/* 26013 */ MCD_OPC_Decode, 211, 13, 127, // Opcode: GLDFF1SH_D_REAL -/* 26017 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26031 -/* 26022 */ MCD_OPC_CheckPredicate, 0, 249, 237, 0, // Skip to: 86948 -/* 26027 */ MCD_OPC_Decode, 128, 13, 127, // Opcode: GLD1H_D_REAL -/* 26031 */ MCD_OPC_FilterValue, 7, 240, 237, 0, // Skip to: 86948 -/* 26036 */ MCD_OPC_CheckPredicate, 0, 235, 237, 0, // Skip to: 86948 -/* 26041 */ MCD_OPC_Decode, 192, 13, 127, // Opcode: GLDFF1H_D_REAL -/* 26045 */ MCD_OPC_FilterValue, 7, 115, 0, 0, // Skip to: 26165 -/* 26050 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26053 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26067 -/* 26058 */ MCD_OPC_CheckPredicate, 0, 213, 237, 0, // Skip to: 86948 -/* 26063 */ MCD_OPC_Decode, 150, 13, 127, // Opcode: GLD1SH_D_SXTW_SCALED_REAL -/* 26067 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26081 -/* 26072 */ MCD_OPC_CheckPredicate, 0, 199, 237, 0, // Skip to: 86948 -/* 26077 */ MCD_OPC_Decode, 214, 13, 127, // Opcode: GLDFF1SH_D_SXTW_SCALED_REAL -/* 26081 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26095 -/* 26086 */ MCD_OPC_CheckPredicate, 0, 185, 237, 0, // Skip to: 86948 -/* 26091 */ MCD_OPC_Decode, 131, 13, 127, // Opcode: GLD1H_D_SXTW_SCALED_REAL -/* 26095 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26109 -/* 26100 */ MCD_OPC_CheckPredicate, 0, 171, 237, 0, // Skip to: 86948 -/* 26105 */ MCD_OPC_Decode, 195, 13, 127, // Opcode: GLDFF1H_D_SXTW_SCALED_REAL -/* 26109 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26123 -/* 26114 */ MCD_OPC_CheckPredicate, 0, 157, 237, 0, // Skip to: 86948 -/* 26119 */ MCD_OPC_Decode, 148, 13, 127, // Opcode: GLD1SH_D_SCALED_REAL -/* 26123 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26137 -/* 26128 */ MCD_OPC_CheckPredicate, 0, 143, 237, 0, // Skip to: 86948 -/* 26133 */ MCD_OPC_Decode, 212, 13, 127, // Opcode: GLDFF1SH_D_SCALED_REAL -/* 26137 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26151 -/* 26142 */ MCD_OPC_CheckPredicate, 0, 129, 237, 0, // Skip to: 86948 -/* 26147 */ MCD_OPC_Decode, 129, 13, 127, // Opcode: GLD1H_D_SCALED_REAL -/* 26151 */ MCD_OPC_FilterValue, 7, 120, 237, 0, // Skip to: 86948 -/* 26156 */ MCD_OPC_CheckPredicate, 0, 115, 237, 0, // Skip to: 86948 -/* 26161 */ MCD_OPC_Decode, 193, 13, 127, // Opcode: GLDFF1H_D_SCALED_REAL -/* 26165 */ MCD_OPC_FilterValue, 8, 81, 0, 0, // Skip to: 26251 -/* 26170 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26173 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26187 -/* 26178 */ MCD_OPC_CheckPredicate, 0, 93, 237, 0, // Skip to: 86948 -/* 26183 */ MCD_OPC_Decode, 163, 13, 127, // Opcode: GLD1SW_D_UXTW_REAL -/* 26187 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26201 -/* 26192 */ MCD_OPC_CheckPredicate, 0, 79, 237, 0, // Skip to: 86948 -/* 26197 */ MCD_OPC_Decode, 227, 13, 127, // Opcode: GLDFF1SW_D_UXTW_REAL -/* 26201 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26215 -/* 26206 */ MCD_OPC_CheckPredicate, 0, 65, 237, 0, // Skip to: 86948 -/* 26211 */ MCD_OPC_Decode, 170, 13, 127, // Opcode: GLD1W_D_UXTW_REAL -/* 26215 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26229 -/* 26220 */ MCD_OPC_CheckPredicate, 0, 51, 237, 0, // Skip to: 86948 -/* 26225 */ MCD_OPC_Decode, 234, 13, 127, // Opcode: GLDFF1W_D_UXTW_REAL -/* 26229 */ MCD_OPC_FilterValue, 7, 42, 237, 0, // Skip to: 86948 -/* 26234 */ MCD_OPC_CheckPredicate, 0, 37, 237, 0, // Skip to: 86948 -/* 26239 */ MCD_OPC_CheckField, 4, 1, 0, 30, 237, 0, // Skip to: 86948 -/* 26246 */ MCD_OPC_Decode, 158, 21, 135, 1, // Opcode: PRFW_D_PZI -/* 26251 */ MCD_OPC_FilterValue, 9, 119, 0, 0, // Skip to: 26375 -/* 26256 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26259 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26273 -/* 26264 */ MCD_OPC_CheckPredicate, 0, 7, 237, 0, // Skip to: 86948 -/* 26269 */ MCD_OPC_Decode, 164, 13, 127, // Opcode: GLD1SW_D_UXTW_SCALED_REAL -/* 26273 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26287 -/* 26278 */ MCD_OPC_CheckPredicate, 0, 249, 236, 0, // Skip to: 86948 -/* 26283 */ MCD_OPC_Decode, 228, 13, 127, // Opcode: GLDFF1SW_D_UXTW_SCALED_REAL -/* 26287 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26301 -/* 26292 */ MCD_OPC_CheckPredicate, 0, 235, 236, 0, // Skip to: 86948 -/* 26297 */ MCD_OPC_Decode, 171, 13, 127, // Opcode: GLD1W_D_UXTW_SCALED_REAL -/* 26301 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26315 -/* 26306 */ MCD_OPC_CheckPredicate, 0, 221, 236, 0, // Skip to: 86948 -/* 26311 */ MCD_OPC_Decode, 235, 13, 127, // Opcode: GLDFF1W_D_UXTW_SCALED_REAL -/* 26315 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 26330 -/* 26320 */ MCD_OPC_CheckPredicate, 0, 207, 236, 0, // Skip to: 86948 -/* 26325 */ MCD_OPC_Decode, 158, 13, 132, 1, // Opcode: GLD1SW_D_IMM_REAL -/* 26330 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 26345 -/* 26335 */ MCD_OPC_CheckPredicate, 0, 192, 236, 0, // Skip to: 86948 -/* 26340 */ MCD_OPC_Decode, 222, 13, 132, 1, // Opcode: GLDFF1SW_D_IMM_REAL -/* 26345 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 26360 -/* 26350 */ MCD_OPC_CheckPredicate, 0, 177, 236, 0, // Skip to: 86948 -/* 26355 */ MCD_OPC_Decode, 165, 13, 132, 1, // Opcode: GLD1W_D_IMM_REAL -/* 26360 */ MCD_OPC_FilterValue, 7, 167, 236, 0, // Skip to: 86948 -/* 26365 */ MCD_OPC_CheckPredicate, 0, 162, 236, 0, // Skip to: 86948 -/* 26370 */ MCD_OPC_Decode, 229, 13, 132, 1, // Opcode: GLDFF1W_D_IMM_REAL -/* 26375 */ MCD_OPC_FilterValue, 10, 115, 0, 0, // Skip to: 26495 -/* 26380 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26383 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26397 -/* 26388 */ MCD_OPC_CheckPredicate, 0, 139, 236, 0, // Skip to: 86948 -/* 26393 */ MCD_OPC_Decode, 161, 13, 127, // Opcode: GLD1SW_D_SXTW_REAL -/* 26397 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26411 -/* 26402 */ MCD_OPC_CheckPredicate, 0, 125, 236, 0, // Skip to: 86948 -/* 26407 */ MCD_OPC_Decode, 225, 13, 127, // Opcode: GLDFF1SW_D_SXTW_REAL -/* 26411 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26425 -/* 26416 */ MCD_OPC_CheckPredicate, 0, 111, 236, 0, // Skip to: 86948 -/* 26421 */ MCD_OPC_Decode, 168, 13, 127, // Opcode: GLD1W_D_SXTW_REAL -/* 26425 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26439 -/* 26430 */ MCD_OPC_CheckPredicate, 0, 97, 236, 0, // Skip to: 86948 -/* 26435 */ MCD_OPC_Decode, 232, 13, 127, // Opcode: GLDFF1W_D_SXTW_REAL -/* 26439 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26453 -/* 26444 */ MCD_OPC_CheckPredicate, 0, 83, 236, 0, // Skip to: 86948 -/* 26449 */ MCD_OPC_Decode, 159, 13, 127, // Opcode: GLD1SW_D_REAL -/* 26453 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26467 -/* 26458 */ MCD_OPC_CheckPredicate, 0, 69, 236, 0, // Skip to: 86948 -/* 26463 */ MCD_OPC_Decode, 223, 13, 127, // Opcode: GLDFF1SW_D_REAL -/* 26467 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26481 -/* 26472 */ MCD_OPC_CheckPredicate, 0, 55, 236, 0, // Skip to: 86948 -/* 26477 */ MCD_OPC_Decode, 166, 13, 127, // Opcode: GLD1W_D_REAL -/* 26481 */ MCD_OPC_FilterValue, 7, 46, 236, 0, // Skip to: 86948 -/* 26486 */ MCD_OPC_CheckPredicate, 0, 41, 236, 0, // Skip to: 86948 -/* 26491 */ MCD_OPC_Decode, 230, 13, 127, // Opcode: GLDFF1W_D_REAL -/* 26495 */ MCD_OPC_FilterValue, 11, 115, 0, 0, // Skip to: 26615 -/* 26500 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26503 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26517 -/* 26508 */ MCD_OPC_CheckPredicate, 0, 19, 236, 0, // Skip to: 86948 -/* 26513 */ MCD_OPC_Decode, 162, 13, 127, // Opcode: GLD1SW_D_SXTW_SCALED_REAL -/* 26517 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26531 -/* 26522 */ MCD_OPC_CheckPredicate, 0, 5, 236, 0, // Skip to: 86948 -/* 26527 */ MCD_OPC_Decode, 226, 13, 127, // Opcode: GLDFF1SW_D_SXTW_SCALED_REAL -/* 26531 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26545 -/* 26536 */ MCD_OPC_CheckPredicate, 0, 247, 235, 0, // Skip to: 86948 -/* 26541 */ MCD_OPC_Decode, 169, 13, 127, // Opcode: GLD1W_D_SXTW_SCALED_REAL -/* 26545 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26559 -/* 26550 */ MCD_OPC_CheckPredicate, 0, 233, 235, 0, // Skip to: 86948 -/* 26555 */ MCD_OPC_Decode, 233, 13, 127, // Opcode: GLDFF1W_D_SXTW_SCALED_REAL -/* 26559 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26573 -/* 26564 */ MCD_OPC_CheckPredicate, 0, 219, 235, 0, // Skip to: 86948 -/* 26569 */ MCD_OPC_Decode, 160, 13, 127, // Opcode: GLD1SW_D_SCALED_REAL -/* 26573 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26587 -/* 26578 */ MCD_OPC_CheckPredicate, 0, 205, 235, 0, // Skip to: 86948 -/* 26583 */ MCD_OPC_Decode, 224, 13, 127, // Opcode: GLDFF1SW_D_SCALED_REAL -/* 26587 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26601 -/* 26592 */ MCD_OPC_CheckPredicate, 0, 191, 235, 0, // Skip to: 86948 -/* 26597 */ MCD_OPC_Decode, 167, 13, 127, // Opcode: GLD1W_D_SCALED_REAL -/* 26601 */ MCD_OPC_FilterValue, 7, 182, 235, 0, // Skip to: 86948 -/* 26606 */ MCD_OPC_CheckPredicate, 0, 177, 235, 0, // Skip to: 86948 -/* 26611 */ MCD_OPC_Decode, 231, 13, 127, // Opcode: GLDFF1W_D_SCALED_REAL -/* 26615 */ MCD_OPC_FilterValue, 12, 53, 0, 0, // Skip to: 26673 -/* 26620 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26623 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26637 -/* 26628 */ MCD_OPC_CheckPredicate, 0, 155, 235, 0, // Skip to: 86948 -/* 26633 */ MCD_OPC_Decode, 253, 12, 127, // Opcode: GLD1D_UXTW_REAL -/* 26637 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26651 -/* 26642 */ MCD_OPC_CheckPredicate, 0, 141, 235, 0, // Skip to: 86948 -/* 26647 */ MCD_OPC_Decode, 189, 13, 127, // Opcode: GLDFF1D_UXTW_REAL -/* 26651 */ MCD_OPC_FilterValue, 7, 132, 235, 0, // Skip to: 86948 -/* 26656 */ MCD_OPC_CheckPredicate, 0, 127, 235, 0, // Skip to: 86948 -/* 26661 */ MCD_OPC_CheckField, 4, 1, 0, 120, 235, 0, // Skip to: 86948 -/* 26668 */ MCD_OPC_Decode, 134, 21, 135, 1, // Opcode: PRFD_D_PZI -/* 26673 */ MCD_OPC_FilterValue, 13, 61, 0, 0, // Skip to: 26739 -/* 26678 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26681 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26695 -/* 26686 */ MCD_OPC_CheckPredicate, 0, 97, 235, 0, // Skip to: 86948 -/* 26691 */ MCD_OPC_Decode, 254, 12, 127, // Opcode: GLD1D_UXTW_SCALED_REAL -/* 26695 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26709 -/* 26700 */ MCD_OPC_CheckPredicate, 0, 83, 235, 0, // Skip to: 86948 -/* 26705 */ MCD_OPC_Decode, 190, 13, 127, // Opcode: GLDFF1D_UXTW_SCALED_REAL -/* 26709 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 26724 -/* 26714 */ MCD_OPC_CheckPredicate, 0, 69, 235, 0, // Skip to: 86948 -/* 26719 */ MCD_OPC_Decode, 248, 12, 132, 1, // Opcode: GLD1D_IMM_REAL -/* 26724 */ MCD_OPC_FilterValue, 7, 59, 235, 0, // Skip to: 86948 -/* 26729 */ MCD_OPC_CheckPredicate, 0, 54, 235, 0, // Skip to: 86948 -/* 26734 */ MCD_OPC_Decode, 184, 13, 132, 1, // Opcode: GLDFF1D_IMM_REAL -/* 26739 */ MCD_OPC_FilterValue, 14, 59, 0, 0, // Skip to: 26803 -/* 26744 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26747 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26761 -/* 26752 */ MCD_OPC_CheckPredicate, 0, 31, 235, 0, // Skip to: 86948 -/* 26757 */ MCD_OPC_Decode, 251, 12, 127, // Opcode: GLD1D_SXTW_REAL -/* 26761 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26775 -/* 26766 */ MCD_OPC_CheckPredicate, 0, 17, 235, 0, // Skip to: 86948 -/* 26771 */ MCD_OPC_Decode, 187, 13, 127, // Opcode: GLDFF1D_SXTW_REAL -/* 26775 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26789 -/* 26780 */ MCD_OPC_CheckPredicate, 0, 3, 235, 0, // Skip to: 86948 -/* 26785 */ MCD_OPC_Decode, 249, 12, 127, // Opcode: GLD1D_REAL -/* 26789 */ MCD_OPC_FilterValue, 7, 250, 234, 0, // Skip to: 86948 -/* 26794 */ MCD_OPC_CheckPredicate, 0, 245, 234, 0, // Skip to: 86948 -/* 26799 */ MCD_OPC_Decode, 185, 13, 127, // Opcode: GLDFF1D_REAL -/* 26803 */ MCD_OPC_FilterValue, 15, 236, 234, 0, // Skip to: 86948 -/* 26808 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26811 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26825 -/* 26816 */ MCD_OPC_CheckPredicate, 0, 223, 234, 0, // Skip to: 86948 -/* 26821 */ MCD_OPC_Decode, 252, 12, 127, // Opcode: GLD1D_SXTW_SCALED_REAL -/* 26825 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26839 -/* 26830 */ MCD_OPC_CheckPredicate, 0, 209, 234, 0, // Skip to: 86948 -/* 26835 */ MCD_OPC_Decode, 188, 13, 127, // Opcode: GLDFF1D_SXTW_SCALED_REAL -/* 26839 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26853 -/* 26844 */ MCD_OPC_CheckPredicate, 0, 195, 234, 0, // Skip to: 86948 -/* 26849 */ MCD_OPC_Decode, 250, 12, 127, // Opcode: GLD1D_SCALED_REAL -/* 26853 */ MCD_OPC_FilterValue, 7, 186, 234, 0, // Skip to: 86948 -/* 26858 */ MCD_OPC_CheckPredicate, 0, 181, 234, 0, // Skip to: 86948 -/* 26863 */ MCD_OPC_Decode, 186, 13, 127, // Opcode: GLDFF1D_SCALED_REAL -/* 26867 */ MCD_OPC_FilterValue, 7, 172, 234, 0, // Skip to: 86948 -/* 26872 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 26875 */ MCD_OPC_FilterValue, 0, 210, 0, 0, // Skip to: 27090 -/* 26880 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 26883 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 26921 -/* 26888 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26891 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 26906 -/* 26896 */ MCD_OPC_CheckPredicate, 0, 143, 234, 0, // Skip to: 86948 -/* 26901 */ MCD_OPC_Decode, 173, 27, 136, 1, // Opcode: ST1B -/* 26906 */ MCD_OPC_FilterValue, 1, 133, 234, 0, // Skip to: 86948 -/* 26911 */ MCD_OPC_CheckPredicate, 0, 128, 234, 0, // Skip to: 86948 -/* 26916 */ MCD_OPC_Decode, 176, 27, 136, 1, // Opcode: ST1B_H -/* 26921 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 26959 -/* 26926 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26929 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 26944 -/* 26934 */ MCD_OPC_CheckPredicate, 0, 105, 234, 0, // Skip to: 86948 -/* 26939 */ MCD_OPC_Decode, 251, 28, 136, 1, // Opcode: STNT1B_ZRR -/* 26944 */ MCD_OPC_FilterValue, 1, 95, 234, 0, // Skip to: 86948 -/* 26949 */ MCD_OPC_CheckPredicate, 0, 90, 234, 0, // Skip to: 86948 -/* 26954 */ MCD_OPC_Decode, 137, 28, 139, 1, // Opcode: ST2B -/* 26959 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 26980 -/* 26964 */ MCD_OPC_CheckPredicate, 0, 75, 234, 0, // Skip to: 86948 -/* 26969 */ MCD_OPC_CheckField, 21, 1, 0, 68, 234, 0, // Skip to: 86948 -/* 26976 */ MCD_OPC_Decode, 254, 26, 127, // Opcode: SST1B_D_UXTW -/* 26980 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 27001 -/* 26985 */ MCD_OPC_CheckPredicate, 0, 54, 234, 0, // Skip to: 86948 -/* 26990 */ MCD_OPC_CheckField, 21, 1, 0, 47, 234, 0, // Skip to: 86948 -/* 26997 */ MCD_OPC_Decode, 251, 26, 127, // Opcode: SST1B_D -/* 27001 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 27022 -/* 27006 */ MCD_OPC_CheckPredicate, 0, 33, 234, 0, // Skip to: 86948 -/* 27011 */ MCD_OPC_CheckField, 21, 1, 0, 26, 234, 0, // Skip to: 86948 -/* 27018 */ MCD_OPC_Decode, 253, 26, 127, // Opcode: SST1B_D_SXTW -/* 27022 */ MCD_OPC_FilterValue, 7, 17, 234, 0, // Skip to: 86948 -/* 27027 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 27030 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27045 -/* 27035 */ MCD_OPC_CheckPredicate, 0, 4, 234, 0, // Skip to: 86948 -/* 27040 */ MCD_OPC_Decode, 178, 27, 137, 1, // Opcode: ST1B_IMM -/* 27045 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27060 -/* 27050 */ MCD_OPC_CheckPredicate, 0, 245, 233, 0, // Skip to: 86948 -/* 27055 */ MCD_OPC_Decode, 250, 28, 137, 1, // Opcode: STNT1B_ZRI -/* 27060 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27075 -/* 27065 */ MCD_OPC_CheckPredicate, 0, 230, 233, 0, // Skip to: 86948 -/* 27070 */ MCD_OPC_Decode, 177, 27, 137, 1, // Opcode: ST1B_H_IMM -/* 27075 */ MCD_OPC_FilterValue, 3, 220, 233, 0, // Skip to: 86948 -/* 27080 */ MCD_OPC_CheckPredicate, 0, 215, 233, 0, // Skip to: 86948 -/* 27085 */ MCD_OPC_Decode, 138, 28, 140, 1, // Opcode: ST2B_IMM -/* 27090 */ MCD_OPC_FilterValue, 1, 227, 0, 0, // Skip to: 27322 -/* 27095 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 27098 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 27136 -/* 27103 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27106 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27121 -/* 27111 */ MCD_OPC_CheckPredicate, 0, 184, 233, 0, // Skip to: 86948 -/* 27116 */ MCD_OPC_Decode, 179, 27, 136, 1, // Opcode: ST1B_S -/* 27121 */ MCD_OPC_FilterValue, 1, 174, 233, 0, // Skip to: 86948 -/* 27126 */ MCD_OPC_CheckPredicate, 0, 169, 233, 0, // Skip to: 86948 -/* 27131 */ MCD_OPC_Decode, 174, 27, 136, 1, // Opcode: ST1B_D -/* 27136 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27174 -/* 27141 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27144 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27159 -/* 27149 */ MCD_OPC_CheckPredicate, 0, 146, 233, 0, // Skip to: 86948 -/* 27154 */ MCD_OPC_Decode, 167, 28, 141, 1, // Opcode: ST3B -/* 27159 */ MCD_OPC_FilterValue, 1, 136, 233, 0, // Skip to: 86948 -/* 27164 */ MCD_OPC_CheckPredicate, 0, 131, 233, 0, // Skip to: 86948 -/* 27169 */ MCD_OPC_Decode, 197, 28, 143, 1, // Opcode: ST4B -/* 27174 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 27195 -/* 27179 */ MCD_OPC_CheckPredicate, 0, 116, 233, 0, // Skip to: 86948 -/* 27184 */ MCD_OPC_CheckField, 21, 1, 0, 109, 233, 0, // Skip to: 86948 -/* 27191 */ MCD_OPC_Decode, 129, 27, 127, // Opcode: SST1B_S_UXTW -/* 27195 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 27233 -/* 27200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27203 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27218 -/* 27208 */ MCD_OPC_CheckPredicate, 0, 87, 233, 0, // Skip to: 86948 -/* 27213 */ MCD_OPC_Decode, 252, 26, 132, 1, // Opcode: SST1B_D_IMM -/* 27218 */ MCD_OPC_FilterValue, 1, 77, 233, 0, // Skip to: 86948 -/* 27223 */ MCD_OPC_CheckPredicate, 0, 72, 233, 0, // Skip to: 86948 -/* 27228 */ MCD_OPC_Decode, 255, 26, 132, 1, // Opcode: SST1B_S_IMM -/* 27233 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 27254 -/* 27238 */ MCD_OPC_CheckPredicate, 0, 57, 233, 0, // Skip to: 86948 -/* 27243 */ MCD_OPC_CheckField, 21, 1, 0, 50, 233, 0, // Skip to: 86948 -/* 27250 */ MCD_OPC_Decode, 128, 27, 127, // Opcode: SST1B_S_SXTW -/* 27254 */ MCD_OPC_FilterValue, 7, 41, 233, 0, // Skip to: 86948 -/* 27259 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 27262 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27277 -/* 27267 */ MCD_OPC_CheckPredicate, 0, 28, 233, 0, // Skip to: 86948 -/* 27272 */ MCD_OPC_Decode, 180, 27, 137, 1, // Opcode: ST1B_S_IMM -/* 27277 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27292 -/* 27282 */ MCD_OPC_CheckPredicate, 0, 13, 233, 0, // Skip to: 86948 -/* 27287 */ MCD_OPC_Decode, 168, 28, 142, 1, // Opcode: ST3B_IMM -/* 27292 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27307 -/* 27297 */ MCD_OPC_CheckPredicate, 0, 254, 232, 0, // Skip to: 86948 -/* 27302 */ MCD_OPC_Decode, 175, 27, 137, 1, // Opcode: ST1B_D_IMM -/* 27307 */ MCD_OPC_FilterValue, 3, 244, 232, 0, // Skip to: 86948 -/* 27312 */ MCD_OPC_CheckPredicate, 0, 239, 232, 0, // Skip to: 86948 -/* 27317 */ MCD_OPC_Decode, 198, 28, 144, 1, // Opcode: ST4B_IMM -/* 27322 */ MCD_OPC_FilterValue, 2, 224, 0, 0, // Skip to: 27551 -/* 27327 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 27330 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 27352 -/* 27335 */ MCD_OPC_CheckPredicate, 0, 216, 232, 0, // Skip to: 86948 -/* 27340 */ MCD_OPC_CheckField, 21, 1, 1, 209, 232, 0, // Skip to: 86948 -/* 27347 */ MCD_OPC_Decode, 199, 27, 136, 1, // Opcode: ST1H -/* 27352 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27390 -/* 27357 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27360 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27375 -/* 27365 */ MCD_OPC_CheckPredicate, 0, 186, 232, 0, // Skip to: 86948 -/* 27370 */ MCD_OPC_Decode, 255, 28, 136, 1, // Opcode: STNT1H_ZRR -/* 27375 */ MCD_OPC_FilterValue, 1, 176, 232, 0, // Skip to: 86948 -/* 27380 */ MCD_OPC_CheckPredicate, 0, 171, 232, 0, // Skip to: 86948 -/* 27385 */ MCD_OPC_Decode, 141, 28, 139, 1, // Opcode: ST2H -/* 27390 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 27426 -/* 27395 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27398 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27412 -/* 27403 */ MCD_OPC_CheckPredicate, 0, 148, 232, 0, // Skip to: 86948 -/* 27408 */ MCD_OPC_Decode, 142, 27, 127, // Opcode: SST1H_D_UXTW -/* 27412 */ MCD_OPC_FilterValue, 1, 139, 232, 0, // Skip to: 86948 -/* 27417 */ MCD_OPC_CheckPredicate, 0, 134, 232, 0, // Skip to: 86948 -/* 27422 */ MCD_OPC_Decode, 143, 27, 127, // Opcode: SST1H_D_UXTW_SCALED -/* 27426 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 27462 -/* 27431 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27434 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27448 -/* 27439 */ MCD_OPC_CheckPredicate, 0, 112, 232, 0, // Skip to: 86948 -/* 27444 */ MCD_OPC_Decode, 137, 27, 127, // Opcode: SST1H_D -/* 27448 */ MCD_OPC_FilterValue, 1, 103, 232, 0, // Skip to: 86948 -/* 27453 */ MCD_OPC_CheckPredicate, 0, 98, 232, 0, // Skip to: 86948 -/* 27458 */ MCD_OPC_Decode, 139, 27, 127, // Opcode: SST1H_D_SCALED -/* 27462 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 27498 -/* 27467 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27470 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27484 -/* 27475 */ MCD_OPC_CheckPredicate, 0, 76, 232, 0, // Skip to: 86948 -/* 27480 */ MCD_OPC_Decode, 140, 27, 127, // Opcode: SST1H_D_SXTW -/* 27484 */ MCD_OPC_FilterValue, 1, 67, 232, 0, // Skip to: 86948 -/* 27489 */ MCD_OPC_CheckPredicate, 0, 62, 232, 0, // Skip to: 86948 -/* 27494 */ MCD_OPC_Decode, 141, 27, 127, // Opcode: SST1H_D_SXTW_SCALED -/* 27498 */ MCD_OPC_FilterValue, 7, 53, 232, 0, // Skip to: 86948 -/* 27503 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 27506 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27521 -/* 27511 */ MCD_OPC_CheckPredicate, 0, 40, 232, 0, // Skip to: 86948 -/* 27516 */ MCD_OPC_Decode, 254, 28, 137, 1, // Opcode: STNT1H_ZRI -/* 27521 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27536 -/* 27526 */ MCD_OPC_CheckPredicate, 0, 25, 232, 0, // Skip to: 86948 -/* 27531 */ MCD_OPC_Decode, 202, 27, 137, 1, // Opcode: ST1H_IMM -/* 27536 */ MCD_OPC_FilterValue, 3, 15, 232, 0, // Skip to: 86948 -/* 27541 */ MCD_OPC_CheckPredicate, 0, 10, 232, 0, // Skip to: 86948 -/* 27546 */ MCD_OPC_Decode, 142, 28, 140, 1, // Opcode: ST2H_IMM -/* 27551 */ MCD_OPC_FilterValue, 3, 1, 1, 0, // Skip to: 27813 -/* 27556 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 27559 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 27597 -/* 27564 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27567 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27582 -/* 27572 */ MCD_OPC_CheckPredicate, 0, 235, 231, 0, // Skip to: 86948 -/* 27577 */ MCD_OPC_Decode, 203, 27, 136, 1, // Opcode: ST1H_S -/* 27582 */ MCD_OPC_FilterValue, 1, 225, 231, 0, // Skip to: 86948 -/* 27587 */ MCD_OPC_CheckPredicate, 0, 220, 231, 0, // Skip to: 86948 -/* 27592 */ MCD_OPC_Decode, 200, 27, 136, 1, // Opcode: ST1H_D -/* 27597 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27635 -/* 27602 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27605 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27620 -/* 27610 */ MCD_OPC_CheckPredicate, 0, 197, 231, 0, // Skip to: 86948 -/* 27615 */ MCD_OPC_Decode, 171, 28, 141, 1, // Opcode: ST3H -/* 27620 */ MCD_OPC_FilterValue, 1, 187, 231, 0, // Skip to: 86948 -/* 27625 */ MCD_OPC_CheckPredicate, 0, 182, 231, 0, // Skip to: 86948 -/* 27630 */ MCD_OPC_Decode, 215, 28, 143, 1, // Opcode: ST4H -/* 27635 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 27671 -/* 27640 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27643 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27657 -/* 27648 */ MCD_OPC_CheckPredicate, 0, 159, 231, 0, // Skip to: 86948 -/* 27653 */ MCD_OPC_Decode, 147, 27, 127, // Opcode: SST1H_S_UXTW -/* 27657 */ MCD_OPC_FilterValue, 1, 150, 231, 0, // Skip to: 86948 -/* 27662 */ MCD_OPC_CheckPredicate, 0, 145, 231, 0, // Skip to: 86948 -/* 27667 */ MCD_OPC_Decode, 148, 27, 127, // Opcode: SST1H_S_UXTW_SCALED -/* 27671 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 27709 -/* 27676 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27679 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27694 -/* 27684 */ MCD_OPC_CheckPredicate, 0, 123, 231, 0, // Skip to: 86948 -/* 27689 */ MCD_OPC_Decode, 138, 27, 132, 1, // Opcode: SST1H_D_IMM -/* 27694 */ MCD_OPC_FilterValue, 1, 113, 231, 0, // Skip to: 86948 -/* 27699 */ MCD_OPC_CheckPredicate, 0, 108, 231, 0, // Skip to: 86948 -/* 27704 */ MCD_OPC_Decode, 144, 27, 132, 1, // Opcode: SST1H_S_IMM -/* 27709 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 27745 -/* 27714 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27717 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27731 -/* 27722 */ MCD_OPC_CheckPredicate, 0, 85, 231, 0, // Skip to: 86948 -/* 27727 */ MCD_OPC_Decode, 145, 27, 127, // Opcode: SST1H_S_SXTW -/* 27731 */ MCD_OPC_FilterValue, 1, 76, 231, 0, // Skip to: 86948 -/* 27736 */ MCD_OPC_CheckPredicate, 0, 71, 231, 0, // Skip to: 86948 -/* 27741 */ MCD_OPC_Decode, 146, 27, 127, // Opcode: SST1H_S_SXTW_SCALED -/* 27745 */ MCD_OPC_FilterValue, 7, 62, 231, 0, // Skip to: 86948 -/* 27750 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 27753 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27768 -/* 27758 */ MCD_OPC_CheckPredicate, 0, 49, 231, 0, // Skip to: 86948 -/* 27763 */ MCD_OPC_Decode, 204, 27, 137, 1, // Opcode: ST1H_S_IMM -/* 27768 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27783 -/* 27773 */ MCD_OPC_CheckPredicate, 0, 34, 231, 0, // Skip to: 86948 -/* 27778 */ MCD_OPC_Decode, 172, 28, 142, 1, // Opcode: ST3H_IMM -/* 27783 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27798 -/* 27788 */ MCD_OPC_CheckPredicate, 0, 19, 231, 0, // Skip to: 86948 -/* 27793 */ MCD_OPC_Decode, 201, 27, 137, 1, // Opcode: ST1H_D_IMM -/* 27798 */ MCD_OPC_FilterValue, 3, 9, 231, 0, // Skip to: 86948 -/* 27803 */ MCD_OPC_CheckPredicate, 0, 4, 231, 0, // Skip to: 86948 -/* 27808 */ MCD_OPC_Decode, 216, 28, 144, 1, // Opcode: ST4H_IMM -/* 27813 */ MCD_OPC_FilterValue, 4, 187, 0, 0, // Skip to: 28005 -/* 27818 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 27821 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27859 -/* 27826 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27829 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27844 -/* 27834 */ MCD_OPC_CheckPredicate, 0, 229, 230, 0, // Skip to: 86948 -/* 27839 */ MCD_OPC_Decode, 129, 29, 136, 1, // Opcode: STNT1W_ZRR -/* 27844 */ MCD_OPC_FilterValue, 1, 219, 230, 0, // Skip to: 86948 -/* 27849 */ MCD_OPC_CheckPredicate, 0, 214, 230, 0, // Skip to: 86948 -/* 27854 */ MCD_OPC_Decode, 157, 28, 139, 1, // Opcode: ST2W -/* 27859 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 27895 -/* 27864 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27867 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27881 -/* 27872 */ MCD_OPC_CheckPredicate, 0, 191, 230, 0, // Skip to: 86948 -/* 27877 */ MCD_OPC_Decode, 154, 27, 127, // Opcode: SST1W_D_UXTW -/* 27881 */ MCD_OPC_FilterValue, 1, 182, 230, 0, // Skip to: 86948 -/* 27886 */ MCD_OPC_CheckPredicate, 0, 177, 230, 0, // Skip to: 86948 -/* 27891 */ MCD_OPC_Decode, 155, 27, 127, // Opcode: SST1W_D_UXTW_SCALED -/* 27895 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 27931 -/* 27900 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27903 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27917 -/* 27908 */ MCD_OPC_CheckPredicate, 0, 155, 230, 0, // Skip to: 86948 -/* 27913 */ MCD_OPC_Decode, 149, 27, 127, // Opcode: SST1W_D -/* 27917 */ MCD_OPC_FilterValue, 1, 146, 230, 0, // Skip to: 86948 -/* 27922 */ MCD_OPC_CheckPredicate, 0, 141, 230, 0, // Skip to: 86948 -/* 27927 */ MCD_OPC_Decode, 151, 27, 127, // Opcode: SST1W_D_SCALED -/* 27931 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 27967 -/* 27936 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27939 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27953 -/* 27944 */ MCD_OPC_CheckPredicate, 0, 119, 230, 0, // Skip to: 86948 -/* 27949 */ MCD_OPC_Decode, 152, 27, 127, // Opcode: SST1W_D_SXTW -/* 27953 */ MCD_OPC_FilterValue, 1, 110, 230, 0, // Skip to: 86948 -/* 27958 */ MCD_OPC_CheckPredicate, 0, 105, 230, 0, // Skip to: 86948 -/* 27963 */ MCD_OPC_Decode, 153, 27, 127, // Opcode: SST1W_D_SXTW_SCALED -/* 27967 */ MCD_OPC_FilterValue, 7, 96, 230, 0, // Skip to: 86948 -/* 27972 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 27975 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27990 -/* 27980 */ MCD_OPC_CheckPredicate, 0, 83, 230, 0, // Skip to: 86948 -/* 27985 */ MCD_OPC_Decode, 128, 29, 137, 1, // Opcode: STNT1W_ZRI -/* 27990 */ MCD_OPC_FilterValue, 3, 73, 230, 0, // Skip to: 86948 -/* 27995 */ MCD_OPC_CheckPredicate, 0, 68, 230, 0, // Skip to: 86948 -/* 28000 */ MCD_OPC_Decode, 158, 28, 140, 1, // Opcode: ST2W_IMM -/* 28005 */ MCD_OPC_FilterValue, 5, 1, 1, 0, // Skip to: 28267 -/* 28010 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 28013 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 28051 -/* 28018 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28021 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28036 -/* 28026 */ MCD_OPC_CheckPredicate, 0, 37, 230, 0, // Skip to: 86948 -/* 28031 */ MCD_OPC_Decode, 253, 27, 136, 1, // Opcode: ST1W -/* 28036 */ MCD_OPC_FilterValue, 1, 27, 230, 0, // Skip to: 86948 -/* 28041 */ MCD_OPC_CheckPredicate, 0, 22, 230, 0, // Skip to: 86948 -/* 28046 */ MCD_OPC_Decode, 254, 27, 136, 1, // Opcode: ST1W_D -/* 28051 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28089 -/* 28056 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28059 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28074 -/* 28064 */ MCD_OPC_CheckPredicate, 0, 255, 229, 0, // Skip to: 86948 -/* 28069 */ MCD_OPC_Decode, 187, 28, 141, 1, // Opcode: ST3W -/* 28074 */ MCD_OPC_FilterValue, 1, 245, 229, 0, // Skip to: 86948 -/* 28079 */ MCD_OPC_CheckPredicate, 0, 240, 229, 0, // Skip to: 86948 -/* 28084 */ MCD_OPC_Decode, 217, 28, 143, 1, // Opcode: ST4W -/* 28089 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 28125 -/* 28094 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28097 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28111 -/* 28102 */ MCD_OPC_CheckPredicate, 0, 217, 229, 0, // Skip to: 86948 -/* 28107 */ MCD_OPC_Decode, 159, 27, 127, // Opcode: SST1W_UXTW -/* 28111 */ MCD_OPC_FilterValue, 1, 208, 229, 0, // Skip to: 86948 -/* 28116 */ MCD_OPC_CheckPredicate, 0, 203, 229, 0, // Skip to: 86948 -/* 28121 */ MCD_OPC_Decode, 160, 27, 127, // Opcode: SST1W_UXTW_SCALED -/* 28125 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 28163 -/* 28130 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28133 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28148 -/* 28138 */ MCD_OPC_CheckPredicate, 0, 181, 229, 0, // Skip to: 86948 -/* 28143 */ MCD_OPC_Decode, 150, 27, 132, 1, // Opcode: SST1W_D_IMM -/* 28148 */ MCD_OPC_FilterValue, 1, 171, 229, 0, // Skip to: 86948 -/* 28153 */ MCD_OPC_CheckPredicate, 0, 166, 229, 0, // Skip to: 86948 -/* 28158 */ MCD_OPC_Decode, 156, 27, 132, 1, // Opcode: SST1W_IMM -/* 28163 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 28199 -/* 28168 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28171 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28185 -/* 28176 */ MCD_OPC_CheckPredicate, 0, 143, 229, 0, // Skip to: 86948 -/* 28181 */ MCD_OPC_Decode, 157, 27, 127, // Opcode: SST1W_SXTW -/* 28185 */ MCD_OPC_FilterValue, 1, 134, 229, 0, // Skip to: 86948 -/* 28190 */ MCD_OPC_CheckPredicate, 0, 129, 229, 0, // Skip to: 86948 -/* 28195 */ MCD_OPC_Decode, 158, 27, 127, // Opcode: SST1W_SXTW_SCALED -/* 28199 */ MCD_OPC_FilterValue, 7, 120, 229, 0, // Skip to: 86948 -/* 28204 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 28207 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28222 -/* 28212 */ MCD_OPC_CheckPredicate, 0, 107, 229, 0, // Skip to: 86948 -/* 28217 */ MCD_OPC_Decode, 128, 28, 137, 1, // Opcode: ST1W_IMM -/* 28222 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 28237 -/* 28227 */ MCD_OPC_CheckPredicate, 0, 92, 229, 0, // Skip to: 86948 -/* 28232 */ MCD_OPC_Decode, 188, 28, 142, 1, // Opcode: ST3W_IMM -/* 28237 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 28252 -/* 28242 */ MCD_OPC_CheckPredicate, 0, 77, 229, 0, // Skip to: 86948 -/* 28247 */ MCD_OPC_Decode, 255, 27, 137, 1, // Opcode: ST1W_D_IMM -/* 28252 */ MCD_OPC_FilterValue, 3, 67, 229, 0, // Skip to: 86948 -/* 28257 */ MCD_OPC_CheckPredicate, 0, 62, 229, 0, // Skip to: 86948 -/* 28262 */ MCD_OPC_Decode, 218, 28, 144, 1, // Opcode: ST4W_IMM -/* 28267 */ MCD_OPC_FilterValue, 6, 224, 0, 0, // Skip to: 28496 -/* 28272 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 28275 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 28297 -/* 28280 */ MCD_OPC_CheckPredicate, 0, 39, 229, 0, // Skip to: 86948 -/* 28285 */ MCD_OPC_CheckField, 4, 1, 0, 32, 229, 0, // Skip to: 86948 -/* 28292 */ MCD_OPC_Decode, 190, 29, 129, 1, // Opcode: STR_PXI -/* 28297 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 28312 -/* 28302 */ MCD_OPC_CheckPredicate, 0, 17, 229, 0, // Skip to: 86948 -/* 28307 */ MCD_OPC_Decode, 191, 29, 131, 1, // Opcode: STR_ZXI -/* 28312 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28350 -/* 28317 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28320 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28335 -/* 28325 */ MCD_OPC_CheckPredicate, 0, 250, 228, 0, // Skip to: 86948 -/* 28330 */ MCD_OPC_Decode, 253, 28, 136, 1, // Opcode: STNT1D_ZRR -/* 28335 */ MCD_OPC_FilterValue, 1, 240, 228, 0, // Skip to: 86948 -/* 28340 */ MCD_OPC_CheckPredicate, 0, 235, 228, 0, // Skip to: 86948 -/* 28345 */ MCD_OPC_Decode, 139, 28, 139, 1, // Opcode: ST2D -/* 28350 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 28386 -/* 28355 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28358 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28372 -/* 28363 */ MCD_OPC_CheckPredicate, 0, 212, 228, 0, // Skip to: 86948 -/* 28368 */ MCD_OPC_Decode, 135, 27, 127, // Opcode: SST1D_UXTW -/* 28372 */ MCD_OPC_FilterValue, 1, 203, 228, 0, // Skip to: 86948 -/* 28377 */ MCD_OPC_CheckPredicate, 0, 198, 228, 0, // Skip to: 86948 -/* 28382 */ MCD_OPC_Decode, 136, 27, 127, // Opcode: SST1D_UXTW_SCALED -/* 28386 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 28422 -/* 28391 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28394 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28408 -/* 28399 */ MCD_OPC_CheckPredicate, 0, 176, 228, 0, // Skip to: 86948 -/* 28404 */ MCD_OPC_Decode, 130, 27, 127, // Opcode: SST1D -/* 28408 */ MCD_OPC_FilterValue, 1, 167, 228, 0, // Skip to: 86948 -/* 28413 */ MCD_OPC_CheckPredicate, 0, 162, 228, 0, // Skip to: 86948 -/* 28418 */ MCD_OPC_Decode, 132, 27, 127, // Opcode: SST1D_SCALED -/* 28422 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 28458 -/* 28427 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28430 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28444 -/* 28435 */ MCD_OPC_CheckPredicate, 0, 140, 228, 0, // Skip to: 86948 -/* 28440 */ MCD_OPC_Decode, 133, 27, 127, // Opcode: SST1D_SXTW -/* 28444 */ MCD_OPC_FilterValue, 1, 131, 228, 0, // Skip to: 86948 -/* 28449 */ MCD_OPC_CheckPredicate, 0, 126, 228, 0, // Skip to: 86948 -/* 28454 */ MCD_OPC_Decode, 134, 27, 127, // Opcode: SST1D_SXTW_SCALED -/* 28458 */ MCD_OPC_FilterValue, 7, 117, 228, 0, // Skip to: 86948 -/* 28463 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 28466 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 28481 -/* 28471 */ MCD_OPC_CheckPredicate, 0, 104, 228, 0, // Skip to: 86948 -/* 28476 */ MCD_OPC_Decode, 252, 28, 137, 1, // Opcode: STNT1D_ZRI -/* 28481 */ MCD_OPC_FilterValue, 3, 94, 228, 0, // Skip to: 86948 -/* 28486 */ MCD_OPC_CheckPredicate, 0, 89, 228, 0, // Skip to: 86948 -/* 28491 */ MCD_OPC_Decode, 140, 28, 140, 1, // Opcode: ST2D_IMM -/* 28496 */ MCD_OPC_FilterValue, 7, 79, 228, 0, // Skip to: 86948 -/* 28501 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 28504 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 28526 -/* 28509 */ MCD_OPC_CheckPredicate, 0, 66, 228, 0, // Skip to: 86948 -/* 28514 */ MCD_OPC_CheckField, 21, 1, 1, 59, 228, 0, // Skip to: 86948 -/* 28521 */ MCD_OPC_Decode, 181, 27, 136, 1, // Opcode: ST1D -/* 28526 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28564 -/* 28531 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28534 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28549 -/* 28539 */ MCD_OPC_CheckPredicate, 0, 36, 228, 0, // Skip to: 86948 -/* 28544 */ MCD_OPC_Decode, 169, 28, 141, 1, // Opcode: ST3D -/* 28549 */ MCD_OPC_FilterValue, 1, 26, 228, 0, // Skip to: 86948 -/* 28554 */ MCD_OPC_CheckPredicate, 0, 21, 228, 0, // Skip to: 86948 -/* 28559 */ MCD_OPC_Decode, 199, 28, 143, 1, // Opcode: ST4D -/* 28564 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 28586 -/* 28569 */ MCD_OPC_CheckPredicate, 0, 6, 228, 0, // Skip to: 86948 -/* 28574 */ MCD_OPC_CheckField, 21, 1, 0, 255, 227, 0, // Skip to: 86948 -/* 28581 */ MCD_OPC_Decode, 131, 27, 132, 1, // Opcode: SST1D_IMM -/* 28586 */ MCD_OPC_FilterValue, 7, 245, 227, 0, // Skip to: 86948 -/* 28591 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 28594 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 28609 -/* 28599 */ MCD_OPC_CheckPredicate, 0, 232, 227, 0, // Skip to: 86948 -/* 28604 */ MCD_OPC_Decode, 170, 28, 142, 1, // Opcode: ST3D_IMM -/* 28609 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 28624 -/* 28614 */ MCD_OPC_CheckPredicate, 0, 217, 227, 0, // Skip to: 86948 -/* 28619 */ MCD_OPC_Decode, 182, 27, 137, 1, // Opcode: ST1D_IMM -/* 28624 */ MCD_OPC_FilterValue, 3, 207, 227, 0, // Skip to: 86948 -/* 28629 */ MCD_OPC_CheckPredicate, 0, 202, 227, 0, // Skip to: 86948 -/* 28634 */ MCD_OPC_Decode, 200, 28, 144, 1, // Opcode: ST4D_IMM -/* 28639 */ MCD_OPC_FilterValue, 2, 20, 8, 0, // Skip to: 30712 -/* 28644 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28647 */ MCD_OPC_FilterValue, 0, 122, 1, 0, // Skip to: 29030 -/* 28652 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 28655 */ MCD_OPC_FilterValue, 0, 51, 1, 0, // Skip to: 28967 -/* 28660 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 28663 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 28691 -/* 28668 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 28671 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 28681 -/* 28676 */ MCD_OPC_Decode, 207, 29, 145, 1, // Opcode: STXRB -/* 28681 */ MCD_OPC_FilterValue, 1, 150, 227, 0, // Skip to: 86948 -/* 28686 */ MCD_OPC_Decode, 241, 28, 145, 1, // Opcode: STLXRB -/* 28691 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 28729 -/* 28696 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 28699 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28714 -/* 28704 */ MCD_OPC_CheckPredicate, 1, 127, 227, 0, // Skip to: 86948 -/* 28709 */ MCD_OPC_Decode, 244, 2, 146, 1, // Opcode: CASPW -/* 28714 */ MCD_OPC_FilterValue, 63, 117, 227, 0, // Skip to: 86948 -/* 28719 */ MCD_OPC_CheckPredicate, 1, 112, 227, 0, // Skip to: 86948 -/* 28724 */ MCD_OPC_Decode, 242, 2, 146, 1, // Opcode: CASPLW -/* 28729 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 28767 -/* 28734 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 28737 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28752 -/* 28742 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 28747 */ MCD_OPC_Decode, 146, 19, 145, 1, // Opcode: LDXRB -/* 28752 */ MCD_OPC_FilterValue, 1, 79, 227, 0, // Skip to: 86948 -/* 28757 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 28762 */ MCD_OPC_Decode, 240, 16, 145, 1, // Opcode: LDAXRB -/* 28767 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28805 -/* 28772 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 28775 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28790 -/* 28780 */ MCD_OPC_CheckPredicate, 1, 51, 227, 0, // Skip to: 86948 -/* 28785 */ MCD_OPC_Decode, 240, 2, 146, 1, // Opcode: CASPAW -/* 28790 */ MCD_OPC_FilterValue, 63, 41, 227, 0, // Skip to: 86948 -/* 28795 */ MCD_OPC_CheckPredicate, 1, 36, 227, 0, // Skip to: 86948 -/* 28800 */ MCD_OPC_Decode, 238, 2, 146, 1, // Opcode: CASPALW -/* 28805 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 28848 -/* 28810 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 28813 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 28833 -/* 28818 */ MCD_OPC_CheckPredicate, 2, 13, 227, 0, // Skip to: 86948 -/* 28823 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 28828 */ MCD_OPC_Decode, 227, 28, 145, 1, // Opcode: STLLRB -/* 28833 */ MCD_OPC_FilterValue, 1, 254, 226, 0, // Skip to: 86948 -/* 28838 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 28843 */ MCD_OPC_Decode, 231, 28, 145, 1, // Opcode: STLRB -/* 28848 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 28886 -/* 28853 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 28856 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28871 -/* 28861 */ MCD_OPC_CheckPredicate, 1, 226, 226, 0, // Skip to: 86948 -/* 28866 */ MCD_OPC_Decode, 232, 2, 147, 1, // Opcode: CASB -/* 28871 */ MCD_OPC_FilterValue, 63, 216, 226, 0, // Skip to: 86948 -/* 28876 */ MCD_OPC_CheckPredicate, 1, 211, 226, 0, // Skip to: 86948 -/* 28881 */ MCD_OPC_Decode, 234, 2, 147, 1, // Opcode: CASLB -/* 28886 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 28929 -/* 28891 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 28894 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 28914 -/* 28899 */ MCD_OPC_CheckPredicate, 2, 188, 226, 0, // Skip to: 86948 -/* 28904 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 28909 */ MCD_OPC_Decode, 164, 17, 145, 1, // Opcode: LDLARB -/* 28914 */ MCD_OPC_FilterValue, 1, 173, 226, 0, // Skip to: 86948 -/* 28919 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 28924 */ MCD_OPC_Decode, 234, 16, 145, 1, // Opcode: LDARB -/* 28929 */ MCD_OPC_FilterValue, 7, 158, 226, 0, // Skip to: 86948 -/* 28934 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 28937 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28952 -/* 28942 */ MCD_OPC_CheckPredicate, 1, 145, 226, 0, // Skip to: 86948 -/* 28947 */ MCD_OPC_Decode, 224, 2, 147, 1, // Opcode: CASAB -/* 28952 */ MCD_OPC_FilterValue, 63, 135, 226, 0, // Skip to: 86948 -/* 28957 */ MCD_OPC_CheckPredicate, 1, 130, 226, 0, // Skip to: 86948 -/* 28962 */ MCD_OPC_Decode, 226, 2, 147, 1, // Opcode: CASALB -/* 28967 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 28995 -/* 28972 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 28975 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 28985 -/* 28980 */ MCD_OPC_Decode, 241, 1, 148, 1, // Opcode: ANDWrs -/* 28985 */ MCD_OPC_FilterValue, 1, 102, 226, 0, // Skip to: 86948 -/* 28990 */ MCD_OPC_Decode, 178, 2, 148, 1, // Opcode: BICWrs -/* 28995 */ MCD_OPC_FilterValue, 3, 92, 226, 0, // Skip to: 86948 -/* 29000 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 29003 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29013 -/* 29008 */ MCD_OPC_Decode, 174, 1, 148, 1, // Opcode: ADDWrs -/* 29013 */ MCD_OPC_FilterValue, 1, 74, 226, 0, // Skip to: 86948 -/* 29018 */ MCD_OPC_CheckField, 22, 2, 0, 67, 226, 0, // Skip to: 86948 -/* 29025 */ MCD_OPC_Decode, 175, 1, 149, 1, // Opcode: ADDWrx -/* 29030 */ MCD_OPC_FilterValue, 1, 162, 0, 0, // Skip to: 29197 -/* 29035 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 29038 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 29086 -/* 29043 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 29046 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29056 -/* 29051 */ MCD_OPC_Decode, 248, 28, 150, 1, // Opcode: STNPWi -/* 29056 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 29066 -/* 29061 */ MCD_OPC_Decode, 187, 17, 150, 1, // Opcode: LDNPWi -/* 29066 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 29076 -/* 29071 */ MCD_OPC_Decode, 140, 29, 150, 1, // Opcode: STPWpost -/* 29076 */ MCD_OPC_FilterValue, 3, 11, 226, 0, // Skip to: 86948 -/* 29081 */ MCD_OPC_Decode, 210, 17, 150, 1, // Opcode: LDPWpost -/* 29086 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 29134 -/* 29091 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 29094 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29104 -/* 29099 */ MCD_OPC_Decode, 139, 29, 150, 1, // Opcode: STPWi -/* 29104 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 29114 -/* 29109 */ MCD_OPC_Decode, 209, 17, 150, 1, // Opcode: LDPWi -/* 29114 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 29124 -/* 29119 */ MCD_OPC_Decode, 141, 29, 150, 1, // Opcode: STPWpre -/* 29124 */ MCD_OPC_FilterValue, 3, 219, 225, 0, // Skip to: 86948 -/* 29129 */ MCD_OPC_Decode, 211, 17, 150, 1, // Opcode: LDPWpre -/* 29134 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 29162 -/* 29139 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 29142 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29152 -/* 29147 */ MCD_OPC_Decode, 206, 20, 148, 1, // Opcode: ORRWrs -/* 29152 */ MCD_OPC_FilterValue, 1, 191, 225, 0, // Skip to: 86948 -/* 29157 */ MCD_OPC_Decode, 197, 20, 148, 1, // Opcode: ORNWrs -/* 29162 */ MCD_OPC_FilterValue, 3, 181, 225, 0, // Skip to: 86948 -/* 29167 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 29170 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29180 -/* 29175 */ MCD_OPC_Decode, 159, 1, 148, 1, // Opcode: ADDSWrs -/* 29180 */ MCD_OPC_FilterValue, 1, 163, 225, 0, // Skip to: 86948 -/* 29185 */ MCD_OPC_CheckField, 22, 2, 0, 156, 225, 0, // Skip to: 86948 -/* 29192 */ MCD_OPC_Decode, 160, 1, 149, 1, // Opcode: ADDSWrx -/* 29197 */ MCD_OPC_FilterValue, 2, 122, 1, 0, // Skip to: 29580 -/* 29202 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 29205 */ MCD_OPC_FilterValue, 0, 51, 1, 0, // Skip to: 29517 -/* 29210 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 29213 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 29241 -/* 29218 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29221 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29231 -/* 29226 */ MCD_OPC_Decode, 208, 29, 145, 1, // Opcode: STXRH -/* 29231 */ MCD_OPC_FilterValue, 1, 112, 225, 0, // Skip to: 86948 -/* 29236 */ MCD_OPC_Decode, 242, 28, 145, 1, // Opcode: STLXRH -/* 29241 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 29279 -/* 29246 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 29249 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29264 -/* 29254 */ MCD_OPC_CheckPredicate, 1, 89, 225, 0, // Skip to: 86948 -/* 29259 */ MCD_OPC_Decode, 245, 2, 151, 1, // Opcode: CASPX -/* 29264 */ MCD_OPC_FilterValue, 63, 79, 225, 0, // Skip to: 86948 -/* 29269 */ MCD_OPC_CheckPredicate, 1, 74, 225, 0, // Skip to: 86948 -/* 29274 */ MCD_OPC_Decode, 243, 2, 151, 1, // Opcode: CASPLX -/* 29279 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 29317 -/* 29284 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29287 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 29302 -/* 29292 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29297 */ MCD_OPC_Decode, 147, 19, 145, 1, // Opcode: LDXRH -/* 29302 */ MCD_OPC_FilterValue, 1, 41, 225, 0, // Skip to: 86948 -/* 29307 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29312 */ MCD_OPC_Decode, 241, 16, 145, 1, // Opcode: LDAXRH -/* 29317 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 29355 -/* 29322 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 29325 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29340 -/* 29330 */ MCD_OPC_CheckPredicate, 1, 13, 225, 0, // Skip to: 86948 -/* 29335 */ MCD_OPC_Decode, 241, 2, 151, 1, // Opcode: CASPAX -/* 29340 */ MCD_OPC_FilterValue, 63, 3, 225, 0, // Skip to: 86948 -/* 29345 */ MCD_OPC_CheckPredicate, 1, 254, 224, 0, // Skip to: 86948 -/* 29350 */ MCD_OPC_Decode, 239, 2, 151, 1, // Opcode: CASPALX -/* 29355 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 29398 -/* 29360 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29363 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29383 -/* 29368 */ MCD_OPC_CheckPredicate, 2, 231, 224, 0, // Skip to: 86948 -/* 29373 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29378 */ MCD_OPC_Decode, 228, 28, 145, 1, // Opcode: STLLRH -/* 29383 */ MCD_OPC_FilterValue, 1, 216, 224, 0, // Skip to: 86948 -/* 29388 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29393 */ MCD_OPC_Decode, 232, 28, 145, 1, // Opcode: STLRH -/* 29398 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 29436 -/* 29403 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 29406 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29421 -/* 29411 */ MCD_OPC_CheckPredicate, 1, 188, 224, 0, // Skip to: 86948 -/* 29416 */ MCD_OPC_Decode, 233, 2, 147, 1, // Opcode: CASH -/* 29421 */ MCD_OPC_FilterValue, 63, 178, 224, 0, // Skip to: 86948 -/* 29426 */ MCD_OPC_CheckPredicate, 1, 173, 224, 0, // Skip to: 86948 -/* 29431 */ MCD_OPC_Decode, 235, 2, 147, 1, // Opcode: CASLH -/* 29436 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 29479 -/* 29441 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29444 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29464 -/* 29449 */ MCD_OPC_CheckPredicate, 2, 150, 224, 0, // Skip to: 86948 -/* 29454 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29459 */ MCD_OPC_Decode, 165, 17, 145, 1, // Opcode: LDLARH -/* 29464 */ MCD_OPC_FilterValue, 1, 135, 224, 0, // Skip to: 86948 -/* 29469 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29474 */ MCD_OPC_Decode, 235, 16, 145, 1, // Opcode: LDARH -/* 29479 */ MCD_OPC_FilterValue, 7, 120, 224, 0, // Skip to: 86948 -/* 29484 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 29487 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29502 -/* 29492 */ MCD_OPC_CheckPredicate, 1, 107, 224, 0, // Skip to: 86948 -/* 29497 */ MCD_OPC_Decode, 225, 2, 147, 1, // Opcode: CASAH -/* 29502 */ MCD_OPC_FilterValue, 63, 97, 224, 0, // Skip to: 86948 -/* 29507 */ MCD_OPC_CheckPredicate, 1, 92, 224, 0, // Skip to: 86948 -/* 29512 */ MCD_OPC_Decode, 227, 2, 147, 1, // Opcode: CASALH -/* 29517 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 29545 -/* 29522 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 29525 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29535 -/* 29530 */ MCD_OPC_Decode, 234, 5, 148, 1, // Opcode: EORWrs -/* 29535 */ MCD_OPC_FilterValue, 1, 64, 224, 0, // Skip to: 86948 -/* 29540 */ MCD_OPC_Decode, 223, 5, 148, 1, // Opcode: EONWrs -/* 29545 */ MCD_OPC_FilterValue, 3, 54, 224, 0, // Skip to: 86948 -/* 29550 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 29553 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29563 -/* 29558 */ MCD_OPC_Decode, 236, 29, 148, 1, // Opcode: SUBWrs -/* 29563 */ MCD_OPC_FilterValue, 1, 36, 224, 0, // Skip to: 86948 -/* 29568 */ MCD_OPC_CheckField, 22, 2, 0, 29, 224, 0, // Skip to: 86948 -/* 29575 */ MCD_OPC_Decode, 237, 29, 149, 1, // Opcode: SUBWrx -/* 29580 */ MCD_OPC_FilterValue, 3, 111, 0, 0, // Skip to: 29696 -/* 29585 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 29588 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 29605 -/* 29593 */ MCD_OPC_CheckField, 22, 2, 3, 4, 224, 0, // Skip to: 86948 -/* 29600 */ MCD_OPC_Decode, 204, 17, 150, 1, // Opcode: LDPSWpost -/* 29605 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 29633 -/* 29610 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 29613 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 29623 -/* 29618 */ MCD_OPC_Decode, 203, 17, 150, 1, // Opcode: LDPSWi -/* 29623 */ MCD_OPC_FilterValue, 3, 232, 223, 0, // Skip to: 86948 -/* 29628 */ MCD_OPC_Decode, 205, 17, 150, 1, // Opcode: LDPSWpre -/* 29633 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 29661 -/* 29638 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 29641 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29651 -/* 29646 */ MCD_OPC_Decode, 230, 1, 148, 1, // Opcode: ANDSWrs -/* 29651 */ MCD_OPC_FilterValue, 1, 204, 223, 0, // Skip to: 86948 -/* 29656 */ MCD_OPC_Decode, 173, 2, 148, 1, // Opcode: BICSWrs -/* 29661 */ MCD_OPC_FilterValue, 3, 194, 223, 0, // Skip to: 86948 -/* 29666 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 29669 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29679 -/* 29674 */ MCD_OPC_Decode, 227, 29, 148, 1, // Opcode: SUBSWrs -/* 29679 */ MCD_OPC_FilterValue, 1, 176, 223, 0, // Skip to: 86948 -/* 29684 */ MCD_OPC_CheckField, 22, 2, 0, 169, 223, 0, // Skip to: 86948 -/* 29691 */ MCD_OPC_Decode, 228, 29, 149, 1, // Opcode: SUBSWrx -/* 29696 */ MCD_OPC_FilterValue, 4, 115, 1, 0, // Skip to: 30072 -/* 29701 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 29704 */ MCD_OPC_FilterValue, 0, 31, 1, 0, // Skip to: 29996 -/* 29709 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 29712 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 29740 -/* 29717 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29720 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29730 -/* 29725 */ MCD_OPC_Decode, 209, 29, 145, 1, // Opcode: STXRW -/* 29730 */ MCD_OPC_FilterValue, 1, 125, 223, 0, // Skip to: 86948 -/* 29735 */ MCD_OPC_Decode, 243, 28, 145, 1, // Opcode: STLXRW -/* 29740 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 29768 -/* 29745 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29748 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29758 -/* 29753 */ MCD_OPC_Decode, 205, 29, 145, 1, // Opcode: STXPW -/* 29758 */ MCD_OPC_FilterValue, 1, 97, 223, 0, // Skip to: 86948 -/* 29763 */ MCD_OPC_Decode, 239, 28, 145, 1, // Opcode: STLXPW -/* 29768 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 29806 -/* 29773 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 29791 -/* 29781 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29786 */ MCD_OPC_Decode, 148, 19, 145, 1, // Opcode: LDXRW -/* 29791 */ MCD_OPC_FilterValue, 1, 64, 223, 0, // Skip to: 86948 -/* 29796 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29801 */ MCD_OPC_Decode, 242, 16, 145, 1, // Opcode: LDAXRW -/* 29806 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 29834 -/* 29811 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29814 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29824 -/* 29819 */ MCD_OPC_Decode, 144, 19, 145, 1, // Opcode: LDXPW -/* 29824 */ MCD_OPC_FilterValue, 1, 31, 223, 0, // Skip to: 86948 -/* 29829 */ MCD_OPC_Decode, 238, 16, 145, 1, // Opcode: LDAXPW -/* 29834 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 29877 -/* 29839 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29842 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29862 -/* 29847 */ MCD_OPC_CheckPredicate, 2, 8, 223, 0, // Skip to: 86948 -/* 29852 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29857 */ MCD_OPC_Decode, 229, 28, 145, 1, // Opcode: STLLRW -/* 29862 */ MCD_OPC_FilterValue, 1, 249, 222, 0, // Skip to: 86948 -/* 29867 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29872 */ MCD_OPC_Decode, 233, 28, 145, 1, // Opcode: STLRW -/* 29877 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 29915 -/* 29882 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 29885 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29900 -/* 29890 */ MCD_OPC_CheckPredicate, 1, 221, 222, 0, // Skip to: 86948 -/* 29895 */ MCD_OPC_Decode, 246, 2, 147, 1, // Opcode: CASW -/* 29900 */ MCD_OPC_FilterValue, 63, 211, 222, 0, // Skip to: 86948 -/* 29905 */ MCD_OPC_CheckPredicate, 1, 206, 222, 0, // Skip to: 86948 -/* 29910 */ MCD_OPC_Decode, 236, 2, 147, 1, // Opcode: CASLW -/* 29915 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 29958 -/* 29920 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 29923 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29943 -/* 29928 */ MCD_OPC_CheckPredicate, 2, 183, 222, 0, // Skip to: 86948 -/* 29933 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29938 */ MCD_OPC_Decode, 166, 17, 145, 1, // Opcode: LDLARW -/* 29943 */ MCD_OPC_FilterValue, 1, 168, 222, 0, // Skip to: 86948 -/* 29948 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 29953 */ MCD_OPC_Decode, 236, 16, 145, 1, // Opcode: LDARW -/* 29958 */ MCD_OPC_FilterValue, 7, 153, 222, 0, // Skip to: 86948 -/* 29963 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 29966 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29981 -/* 29971 */ MCD_OPC_CheckPredicate, 1, 140, 222, 0, // Skip to: 86948 -/* 29976 */ MCD_OPC_Decode, 230, 2, 147, 1, // Opcode: CASAW -/* 29981 */ MCD_OPC_FilterValue, 63, 130, 222, 0, // Skip to: 86948 -/* 29986 */ MCD_OPC_CheckPredicate, 1, 125, 222, 0, // Skip to: 86948 -/* 29991 */ MCD_OPC_Decode, 228, 2, 147, 1, // Opcode: CASALW -/* 29996 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 30024 -/* 30001 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30004 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30014 -/* 30009 */ MCD_OPC_Decode, 244, 1, 148, 1, // Opcode: ANDXrs -/* 30014 */ MCD_OPC_FilterValue, 1, 97, 222, 0, // Skip to: 86948 -/* 30019 */ MCD_OPC_Decode, 180, 2, 148, 1, // Opcode: BICXrs -/* 30024 */ MCD_OPC_FilterValue, 3, 87, 222, 0, // Skip to: 86948 -/* 30029 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30032 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30042 -/* 30037 */ MCD_OPC_Decode, 178, 1, 148, 1, // Opcode: ADDXrs -/* 30042 */ MCD_OPC_FilterValue, 1, 69, 222, 0, // Skip to: 86948 -/* 30047 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 30050 */ MCD_OPC_FilterValue, 0, 61, 222, 0, // Skip to: 86948 -/* 30055 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30067 -/* 30062 */ MCD_OPC_Decode, 180, 1, 149, 1, // Opcode: ADDXrx64 -/* 30067 */ MCD_OPC_Decode, 179, 1, 149, 1, // Opcode: ADDXrx -/* 30072 */ MCD_OPC_FilterValue, 5, 175, 0, 0, // Skip to: 30252 -/* 30077 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 30080 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 30128 -/* 30085 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 30088 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30098 -/* 30093 */ MCD_OPC_Decode, 249, 28, 150, 1, // Opcode: STNPXi -/* 30098 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 30108 -/* 30103 */ MCD_OPC_Decode, 188, 17, 150, 1, // Opcode: LDNPXi -/* 30108 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30118 -/* 30113 */ MCD_OPC_Decode, 143, 29, 150, 1, // Opcode: STPXpost -/* 30118 */ MCD_OPC_FilterValue, 3, 249, 221, 0, // Skip to: 86948 -/* 30123 */ MCD_OPC_Decode, 213, 17, 150, 1, // Opcode: LDPXpost -/* 30128 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 30176 -/* 30133 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 30136 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30146 -/* 30141 */ MCD_OPC_Decode, 142, 29, 150, 1, // Opcode: STPXi -/* 30146 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 30156 -/* 30151 */ MCD_OPC_Decode, 212, 17, 150, 1, // Opcode: LDPXi -/* 30156 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30166 -/* 30161 */ MCD_OPC_Decode, 144, 29, 150, 1, // Opcode: STPXpre -/* 30166 */ MCD_OPC_FilterValue, 3, 201, 221, 0, // Skip to: 86948 -/* 30171 */ MCD_OPC_Decode, 214, 17, 150, 1, // Opcode: LDPXpre -/* 30176 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 30204 -/* 30181 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30184 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30194 -/* 30189 */ MCD_OPC_Decode, 209, 20, 148, 1, // Opcode: ORRXrs -/* 30194 */ MCD_OPC_FilterValue, 1, 173, 221, 0, // Skip to: 86948 -/* 30199 */ MCD_OPC_Decode, 199, 20, 148, 1, // Opcode: ORNXrs -/* 30204 */ MCD_OPC_FilterValue, 3, 163, 221, 0, // Skip to: 86948 -/* 30209 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30212 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30222 -/* 30217 */ MCD_OPC_Decode, 163, 1, 148, 1, // Opcode: ADDSXrs -/* 30222 */ MCD_OPC_FilterValue, 1, 145, 221, 0, // Skip to: 86948 -/* 30227 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 30230 */ MCD_OPC_FilterValue, 0, 137, 221, 0, // Skip to: 86948 -/* 30235 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30247 -/* 30242 */ MCD_OPC_Decode, 165, 1, 149, 1, // Opcode: ADDSXrx64 -/* 30247 */ MCD_OPC_Decode, 164, 1, 149, 1, // Opcode: ADDSXrx -/* 30252 */ MCD_OPC_FilterValue, 6, 115, 1, 0, // Skip to: 30628 -/* 30257 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 30260 */ MCD_OPC_FilterValue, 0, 31, 1, 0, // Skip to: 30552 -/* 30265 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 30268 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 30296 -/* 30273 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 30276 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30286 -/* 30281 */ MCD_OPC_Decode, 210, 29, 145, 1, // Opcode: STXRX -/* 30286 */ MCD_OPC_FilterValue, 1, 81, 221, 0, // Skip to: 86948 -/* 30291 */ MCD_OPC_Decode, 244, 28, 145, 1, // Opcode: STLXRX -/* 30296 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 30324 -/* 30301 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 30304 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30314 -/* 30309 */ MCD_OPC_Decode, 206, 29, 145, 1, // Opcode: STXPX -/* 30314 */ MCD_OPC_FilterValue, 1, 53, 221, 0, // Skip to: 86948 -/* 30319 */ MCD_OPC_Decode, 240, 28, 145, 1, // Opcode: STLXPX -/* 30324 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 30362 -/* 30329 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 30332 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 30347 -/* 30337 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 30342 */ MCD_OPC_Decode, 149, 19, 145, 1, // Opcode: LDXRX -/* 30347 */ MCD_OPC_FilterValue, 1, 20, 221, 0, // Skip to: 86948 -/* 30352 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 30357 */ MCD_OPC_Decode, 243, 16, 145, 1, // Opcode: LDAXRX -/* 30362 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 30390 -/* 30367 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 30370 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30380 -/* 30375 */ MCD_OPC_Decode, 145, 19, 145, 1, // Opcode: LDXPX -/* 30380 */ MCD_OPC_FilterValue, 1, 243, 220, 0, // Skip to: 86948 -/* 30385 */ MCD_OPC_Decode, 239, 16, 145, 1, // Opcode: LDAXPX -/* 30390 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 30433 -/* 30395 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 30398 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 30418 -/* 30403 */ MCD_OPC_CheckPredicate, 2, 220, 220, 0, // Skip to: 86948 -/* 30408 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 30413 */ MCD_OPC_Decode, 230, 28, 145, 1, // Opcode: STLLRX -/* 30418 */ MCD_OPC_FilterValue, 1, 205, 220, 0, // Skip to: 86948 -/* 30423 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 30428 */ MCD_OPC_Decode, 234, 28, 145, 1, // Opcode: STLRX -/* 30433 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 30471 -/* 30438 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 30441 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 30456 -/* 30446 */ MCD_OPC_CheckPredicate, 1, 177, 220, 0, // Skip to: 86948 -/* 30451 */ MCD_OPC_Decode, 247, 2, 152, 1, // Opcode: CASX -/* 30456 */ MCD_OPC_FilterValue, 63, 167, 220, 0, // Skip to: 86948 -/* 30461 */ MCD_OPC_CheckPredicate, 1, 162, 220, 0, // Skip to: 86948 -/* 30466 */ MCD_OPC_Decode, 237, 2, 152, 1, // Opcode: CASLX -/* 30471 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 30514 -/* 30476 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 30479 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 30499 -/* 30484 */ MCD_OPC_CheckPredicate, 2, 139, 220, 0, // Skip to: 86948 -/* 30489 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 30494 */ MCD_OPC_Decode, 167, 17, 145, 1, // Opcode: LDLARX -/* 30499 */ MCD_OPC_FilterValue, 1, 124, 220, 0, // Skip to: 86948 -/* 30504 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, -/* 30509 */ MCD_OPC_Decode, 237, 16, 145, 1, // Opcode: LDARX -/* 30514 */ MCD_OPC_FilterValue, 7, 109, 220, 0, // Skip to: 86948 -/* 30519 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 30522 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 30537 -/* 30527 */ MCD_OPC_CheckPredicate, 1, 96, 220, 0, // Skip to: 86948 -/* 30532 */ MCD_OPC_Decode, 231, 2, 152, 1, // Opcode: CASAX -/* 30537 */ MCD_OPC_FilterValue, 63, 86, 220, 0, // Skip to: 86948 -/* 30542 */ MCD_OPC_CheckPredicate, 1, 81, 220, 0, // Skip to: 86948 -/* 30547 */ MCD_OPC_Decode, 229, 2, 152, 1, // Opcode: CASALX -/* 30552 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 30580 -/* 30557 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30560 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30570 -/* 30565 */ MCD_OPC_Decode, 237, 5, 148, 1, // Opcode: EORXrs -/* 30570 */ MCD_OPC_FilterValue, 1, 53, 220, 0, // Skip to: 86948 -/* 30575 */ MCD_OPC_Decode, 225, 5, 148, 1, // Opcode: EONXrs -/* 30580 */ MCD_OPC_FilterValue, 3, 43, 220, 0, // Skip to: 86948 -/* 30585 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30588 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30598 -/* 30593 */ MCD_OPC_Decode, 240, 29, 148, 1, // Opcode: SUBXrs -/* 30598 */ MCD_OPC_FilterValue, 1, 25, 220, 0, // Skip to: 86948 -/* 30603 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 30606 */ MCD_OPC_FilterValue, 0, 17, 220, 0, // Skip to: 86948 -/* 30611 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30623 -/* 30618 */ MCD_OPC_Decode, 242, 29, 149, 1, // Opcode: SUBXrx64 -/* 30623 */ MCD_OPC_Decode, 241, 29, 149, 1, // Opcode: SUBXrx -/* 30628 */ MCD_OPC_FilterValue, 7, 251, 219, 0, // Skip to: 86948 -/* 30633 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30636 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 30664 -/* 30641 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 30644 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30654 -/* 30649 */ MCD_OPC_Decode, 233, 1, 148, 1, // Opcode: ANDSXrs -/* 30654 */ MCD_OPC_FilterValue, 3, 225, 219, 0, // Skip to: 86948 -/* 30659 */ MCD_OPC_Decode, 231, 29, 148, 1, // Opcode: SUBSXrs -/* 30664 */ MCD_OPC_FilterValue, 1, 215, 219, 0, // Skip to: 86948 -/* 30669 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 30672 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30682 -/* 30677 */ MCD_OPC_Decode, 175, 2, 148, 1, // Opcode: BICSXrs -/* 30682 */ MCD_OPC_FilterValue, 3, 197, 219, 0, // Skip to: 86948 -/* 30687 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 30690 */ MCD_OPC_FilterValue, 0, 189, 219, 0, // Skip to: 86948 -/* 30695 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30707 -/* 30702 */ MCD_OPC_Decode, 233, 29, 149, 1, // Opcode: SUBSXrx64 -/* 30707 */ MCD_OPC_Decode, 232, 29, 149, 1, // Opcode: SUBSXrx -/* 30712 */ MCD_OPC_FilterValue, 3, 166, 145, 0, // Skip to: 68003 -/* 30717 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 30720 */ MCD_OPC_FilterValue, 0, 76, 3, 0, // Skip to: 31569 -/* 30725 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 30728 */ MCD_OPC_FilterValue, 0, 122, 1, 0, // Skip to: 31111 -/* 30733 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... -/* 30736 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 30751 -/* 30741 */ MCD_OPC_CheckPredicate, 3, 138, 219, 0, // Skip to: 86948 -/* 30746 */ MCD_OPC_Decode, 211, 28, 153, 1, // Opcode: ST4Fourv8b -/* 30751 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 30766 -/* 30756 */ MCD_OPC_CheckPredicate, 3, 123, 219, 0, // Skip to: 86948 -/* 30761 */ MCD_OPC_Decode, 207, 28, 153, 1, // Opcode: ST4Fourv4h -/* 30766 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 30781 -/* 30771 */ MCD_OPC_CheckPredicate, 3, 108, 219, 0, // Skip to: 86948 -/* 30776 */ MCD_OPC_Decode, 205, 28, 153, 1, // Opcode: ST4Fourv2s -/* 30781 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 30796 -/* 30786 */ MCD_OPC_CheckPredicate, 3, 93, 219, 0, // Skip to: 86948 -/* 30791 */ MCD_OPC_Decode, 195, 27, 153, 1, // Opcode: ST1Fourv8b -/* 30796 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 30811 -/* 30801 */ MCD_OPC_CheckPredicate, 3, 78, 219, 0, // Skip to: 86948 -/* 30806 */ MCD_OPC_Decode, 191, 27, 153, 1, // Opcode: ST1Fourv4h -/* 30811 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 30826 -/* 30816 */ MCD_OPC_CheckPredicate, 3, 63, 219, 0, // Skip to: 86948 -/* 30821 */ MCD_OPC_Decode, 189, 27, 153, 1, // Opcode: ST1Fourv2s -/* 30826 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 30841 -/* 30831 */ MCD_OPC_CheckPredicate, 3, 48, 219, 0, // Skip to: 86948 -/* 30836 */ MCD_OPC_Decode, 185, 27, 153, 1, // Opcode: ST1Fourv1d -/* 30841 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 30856 -/* 30846 */ MCD_OPC_CheckPredicate, 3, 33, 219, 0, // Skip to: 86948 -/* 30851 */ MCD_OPC_Decode, 183, 28, 154, 1, // Opcode: ST3Threev8b -/* 30856 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 30871 -/* 30861 */ MCD_OPC_CheckPredicate, 3, 18, 219, 0, // Skip to: 86948 -/* 30866 */ MCD_OPC_Decode, 179, 28, 154, 1, // Opcode: ST3Threev4h -/* 30871 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 30886 -/* 30876 */ MCD_OPC_CheckPredicate, 3, 3, 219, 0, // Skip to: 86948 -/* 30881 */ MCD_OPC_Decode, 177, 28, 154, 1, // Opcode: ST3Threev2s -/* 30886 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 30901 -/* 30891 */ MCD_OPC_CheckPredicate, 3, 244, 218, 0, // Skip to: 86948 -/* 30896 */ MCD_OPC_Decode, 233, 27, 154, 1, // Opcode: ST1Threev8b -/* 30901 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 30916 -/* 30906 */ MCD_OPC_CheckPredicate, 3, 229, 218, 0, // Skip to: 86948 -/* 30911 */ MCD_OPC_Decode, 229, 27, 154, 1, // Opcode: ST1Threev4h -/* 30916 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 30931 -/* 30921 */ MCD_OPC_CheckPredicate, 3, 214, 218, 0, // Skip to: 86948 -/* 30926 */ MCD_OPC_Decode, 227, 27, 154, 1, // Opcode: ST1Threev2s -/* 30931 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 30946 -/* 30936 */ MCD_OPC_CheckPredicate, 3, 199, 218, 0, // Skip to: 86948 -/* 30941 */ MCD_OPC_Decode, 223, 27, 154, 1, // Opcode: ST1Threev1d -/* 30946 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 30961 -/* 30951 */ MCD_OPC_CheckPredicate, 3, 184, 218, 0, // Skip to: 86948 -/* 30956 */ MCD_OPC_Decode, 217, 27, 155, 1, // Opcode: ST1Onev8b -/* 30961 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 30976 -/* 30966 */ MCD_OPC_CheckPredicate, 3, 169, 218, 0, // Skip to: 86948 -/* 30971 */ MCD_OPC_Decode, 213, 27, 155, 1, // Opcode: ST1Onev4h -/* 30976 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 30991 -/* 30981 */ MCD_OPC_CheckPredicate, 3, 154, 218, 0, // Skip to: 86948 -/* 30986 */ MCD_OPC_Decode, 211, 27, 155, 1, // Opcode: ST1Onev2s -/* 30991 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 31006 -/* 30996 */ MCD_OPC_CheckPredicate, 3, 139, 218, 0, // Skip to: 86948 -/* 31001 */ MCD_OPC_Decode, 207, 27, 155, 1, // Opcode: ST1Onev1d -/* 31006 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 31021 -/* 31011 */ MCD_OPC_CheckPredicate, 3, 124, 218, 0, // Skip to: 86948 -/* 31016 */ MCD_OPC_Decode, 153, 28, 156, 1, // Opcode: ST2Twov8b -/* 31021 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 31036 -/* 31026 */ MCD_OPC_CheckPredicate, 3, 109, 218, 0, // Skip to: 86948 -/* 31031 */ MCD_OPC_Decode, 149, 28, 156, 1, // Opcode: ST2Twov4h -/* 31036 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 31051 -/* 31041 */ MCD_OPC_CheckPredicate, 3, 94, 218, 0, // Skip to: 86948 -/* 31046 */ MCD_OPC_Decode, 147, 28, 156, 1, // Opcode: ST2Twov2s -/* 31051 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 31066 -/* 31056 */ MCD_OPC_CheckPredicate, 3, 79, 218, 0, // Skip to: 86948 -/* 31061 */ MCD_OPC_Decode, 249, 27, 156, 1, // Opcode: ST1Twov8b -/* 31066 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 31081 -/* 31071 */ MCD_OPC_CheckPredicate, 3, 64, 218, 0, // Skip to: 86948 -/* 31076 */ MCD_OPC_Decode, 245, 27, 156, 1, // Opcode: ST1Twov4h -/* 31081 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 31096 -/* 31086 */ MCD_OPC_CheckPredicate, 3, 49, 218, 0, // Skip to: 86948 -/* 31091 */ MCD_OPC_Decode, 243, 27, 156, 1, // Opcode: ST1Twov2s -/* 31096 */ MCD_OPC_FilterValue, 43, 39, 218, 0, // Skip to: 86948 -/* 31101 */ MCD_OPC_CheckPredicate, 3, 34, 218, 0, // Skip to: 86948 -/* 31106 */ MCD_OPC_Decode, 239, 27, 156, 1, // Opcode: ST1Twov1d -/* 31111 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 31121 -/* 31116 */ MCD_OPC_Decode, 247, 28, 150, 1, // Opcode: STNPSi -/* 31121 */ MCD_OPC_FilterValue, 2, 167, 1, 0, // Skip to: 31549 -/* 31126 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... -/* 31129 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 31144 -/* 31134 */ MCD_OPC_CheckPredicate, 3, 1, 218, 0, // Skip to: 86948 -/* 31139 */ MCD_OPC_Decode, 201, 28, 157, 1, // Opcode: ST4Fourv16b -/* 31144 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 31159 -/* 31149 */ MCD_OPC_CheckPredicate, 3, 242, 217, 0, // Skip to: 86948 -/* 31154 */ MCD_OPC_Decode, 213, 28, 157, 1, // Opcode: ST4Fourv8h -/* 31159 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 31174 -/* 31164 */ MCD_OPC_CheckPredicate, 3, 227, 217, 0, // Skip to: 86948 -/* 31169 */ MCD_OPC_Decode, 209, 28, 157, 1, // Opcode: ST4Fourv4s -/* 31174 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 31189 -/* 31179 */ MCD_OPC_CheckPredicate, 3, 212, 217, 0, // Skip to: 86948 -/* 31184 */ MCD_OPC_Decode, 203, 28, 157, 1, // Opcode: ST4Fourv2d -/* 31189 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 31204 -/* 31194 */ MCD_OPC_CheckPredicate, 3, 197, 217, 0, // Skip to: 86948 -/* 31199 */ MCD_OPC_Decode, 183, 27, 157, 1, // Opcode: ST1Fourv16b -/* 31204 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 31219 -/* 31209 */ MCD_OPC_CheckPredicate, 3, 182, 217, 0, // Skip to: 86948 -/* 31214 */ MCD_OPC_Decode, 197, 27, 157, 1, // Opcode: ST1Fourv8h -/* 31219 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 31234 -/* 31224 */ MCD_OPC_CheckPredicate, 3, 167, 217, 0, // Skip to: 86948 -/* 31229 */ MCD_OPC_Decode, 193, 27, 157, 1, // Opcode: ST1Fourv4s -/* 31234 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 31249 -/* 31239 */ MCD_OPC_CheckPredicate, 3, 152, 217, 0, // Skip to: 86948 -/* 31244 */ MCD_OPC_Decode, 187, 27, 157, 1, // Opcode: ST1Fourv2d -/* 31249 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 31264 -/* 31254 */ MCD_OPC_CheckPredicate, 3, 137, 217, 0, // Skip to: 86948 -/* 31259 */ MCD_OPC_Decode, 173, 28, 158, 1, // Opcode: ST3Threev16b -/* 31264 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 31279 -/* 31269 */ MCD_OPC_CheckPredicate, 3, 122, 217, 0, // Skip to: 86948 -/* 31274 */ MCD_OPC_Decode, 185, 28, 158, 1, // Opcode: ST3Threev8h -/* 31279 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 31294 -/* 31284 */ MCD_OPC_CheckPredicate, 3, 107, 217, 0, // Skip to: 86948 -/* 31289 */ MCD_OPC_Decode, 181, 28, 158, 1, // Opcode: ST3Threev4s -/* 31294 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 31309 -/* 31299 */ MCD_OPC_CheckPredicate, 3, 92, 217, 0, // Skip to: 86948 -/* 31304 */ MCD_OPC_Decode, 175, 28, 158, 1, // Opcode: ST3Threev2d -/* 31309 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 31324 -/* 31314 */ MCD_OPC_CheckPredicate, 3, 77, 217, 0, // Skip to: 86948 -/* 31319 */ MCD_OPC_Decode, 221, 27, 158, 1, // Opcode: ST1Threev16b -/* 31324 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 31339 -/* 31329 */ MCD_OPC_CheckPredicate, 3, 62, 217, 0, // Skip to: 86948 -/* 31334 */ MCD_OPC_Decode, 235, 27, 158, 1, // Opcode: ST1Threev8h -/* 31339 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 31354 -/* 31344 */ MCD_OPC_CheckPredicate, 3, 47, 217, 0, // Skip to: 86948 -/* 31349 */ MCD_OPC_Decode, 231, 27, 158, 1, // Opcode: ST1Threev4s -/* 31354 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 31369 -/* 31359 */ MCD_OPC_CheckPredicate, 3, 32, 217, 0, // Skip to: 86948 -/* 31364 */ MCD_OPC_Decode, 225, 27, 158, 1, // Opcode: ST1Threev2d -/* 31369 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 31384 -/* 31374 */ MCD_OPC_CheckPredicate, 3, 17, 217, 0, // Skip to: 86948 -/* 31379 */ MCD_OPC_Decode, 205, 27, 159, 1, // Opcode: ST1Onev16b -/* 31384 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 31399 -/* 31389 */ MCD_OPC_CheckPredicate, 3, 2, 217, 0, // Skip to: 86948 -/* 31394 */ MCD_OPC_Decode, 219, 27, 159, 1, // Opcode: ST1Onev8h -/* 31399 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 31414 -/* 31404 */ MCD_OPC_CheckPredicate, 3, 243, 216, 0, // Skip to: 86948 -/* 31409 */ MCD_OPC_Decode, 215, 27, 159, 1, // Opcode: ST1Onev4s -/* 31414 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 31429 -/* 31419 */ MCD_OPC_CheckPredicate, 3, 228, 216, 0, // Skip to: 86948 -/* 31424 */ MCD_OPC_Decode, 209, 27, 159, 1, // Opcode: ST1Onev2d -/* 31429 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 31444 -/* 31434 */ MCD_OPC_CheckPredicate, 3, 213, 216, 0, // Skip to: 86948 -/* 31439 */ MCD_OPC_Decode, 143, 28, 160, 1, // Opcode: ST2Twov16b -/* 31444 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 31459 -/* 31449 */ MCD_OPC_CheckPredicate, 3, 198, 216, 0, // Skip to: 86948 -/* 31454 */ MCD_OPC_Decode, 155, 28, 160, 1, // Opcode: ST2Twov8h -/* 31459 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 31474 -/* 31464 */ MCD_OPC_CheckPredicate, 3, 183, 216, 0, // Skip to: 86948 -/* 31469 */ MCD_OPC_Decode, 151, 28, 160, 1, // Opcode: ST2Twov4s -/* 31474 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 31489 -/* 31479 */ MCD_OPC_CheckPredicate, 3, 168, 216, 0, // Skip to: 86948 -/* 31484 */ MCD_OPC_Decode, 145, 28, 160, 1, // Opcode: ST2Twov2d -/* 31489 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 31504 -/* 31494 */ MCD_OPC_CheckPredicate, 3, 153, 216, 0, // Skip to: 86948 -/* 31499 */ MCD_OPC_Decode, 237, 27, 160, 1, // Opcode: ST1Twov16b -/* 31504 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 31519 -/* 31509 */ MCD_OPC_CheckPredicate, 3, 138, 216, 0, // Skip to: 86948 -/* 31514 */ MCD_OPC_Decode, 251, 27, 160, 1, // Opcode: ST1Twov8h -/* 31519 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 31534 -/* 31524 */ MCD_OPC_CheckPredicate, 3, 123, 216, 0, // Skip to: 86948 -/* 31529 */ MCD_OPC_Decode, 247, 27, 160, 1, // Opcode: ST1Twov4s -/* 31534 */ MCD_OPC_FilterValue, 43, 113, 216, 0, // Skip to: 86948 -/* 31539 */ MCD_OPC_CheckPredicate, 3, 108, 216, 0, // Skip to: 86948 -/* 31544 */ MCD_OPC_Decode, 241, 27, 160, 1, // Opcode: ST1Twov2d -/* 31549 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 31559 -/* 31554 */ MCD_OPC_Decode, 245, 28, 150, 1, // Opcode: STNPDi -/* 31559 */ MCD_OPC_FilterValue, 5, 88, 216, 0, // Skip to: 86948 -/* 31564 */ MCD_OPC_Decode, 246, 28, 150, 1, // Opcode: STNPQi -/* 31569 */ MCD_OPC_FilterValue, 1, 76, 3, 0, // Skip to: 32418 -/* 31574 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 31577 */ MCD_OPC_FilterValue, 0, 122, 1, 0, // Skip to: 31960 -/* 31582 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... -/* 31585 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 31600 -/* 31590 */ MCD_OPC_CheckPredicate, 3, 57, 216, 0, // Skip to: 86948 -/* 31595 */ MCD_OPC_Decode, 173, 16, 153, 1, // Opcode: LD4Fourv8b -/* 31600 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 31615 -/* 31605 */ MCD_OPC_CheckPredicate, 3, 42, 216, 0, // Skip to: 86948 -/* 31610 */ MCD_OPC_Decode, 169, 16, 153, 1, // Opcode: LD4Fourv4h -/* 31615 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 31630 -/* 31620 */ MCD_OPC_CheckPredicate, 3, 27, 216, 0, // Skip to: 86948 -/* 31625 */ MCD_OPC_Decode, 167, 16, 153, 1, // Opcode: LD4Fourv2s -/* 31630 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 31645 -/* 31635 */ MCD_OPC_CheckPredicate, 3, 12, 216, 0, // Skip to: 86948 -/* 31640 */ MCD_OPC_Decode, 201, 14, 153, 1, // Opcode: LD1Fourv8b -/* 31645 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 31660 -/* 31650 */ MCD_OPC_CheckPredicate, 3, 253, 215, 0, // Skip to: 86948 -/* 31655 */ MCD_OPC_Decode, 197, 14, 153, 1, // Opcode: LD1Fourv4h -/* 31660 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 31675 -/* 31665 */ MCD_OPC_CheckPredicate, 3, 238, 215, 0, // Skip to: 86948 -/* 31670 */ MCD_OPC_Decode, 195, 14, 153, 1, // Opcode: LD1Fourv2s -/* 31675 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 31690 -/* 31680 */ MCD_OPC_CheckPredicate, 3, 223, 215, 0, // Skip to: 86948 -/* 31685 */ MCD_OPC_Decode, 191, 14, 153, 1, // Opcode: LD1Fourv1d -/* 31690 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 31705 -/* 31695 */ MCD_OPC_CheckPredicate, 3, 208, 215, 0, // Skip to: 86948 -/* 31700 */ MCD_OPC_Decode, 145, 16, 154, 1, // Opcode: LD3Threev8b -/* 31705 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 31720 -/* 31710 */ MCD_OPC_CheckPredicate, 3, 193, 215, 0, // Skip to: 86948 -/* 31715 */ MCD_OPC_Decode, 141, 16, 154, 1, // Opcode: LD3Threev4h -/* 31720 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 31735 -/* 31725 */ MCD_OPC_CheckPredicate, 3, 178, 215, 0, // Skip to: 86948 -/* 31730 */ MCD_OPC_Decode, 139, 16, 154, 1, // Opcode: LD3Threev2s -/* 31735 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 31750 -/* 31740 */ MCD_OPC_CheckPredicate, 3, 163, 215, 0, // Skip to: 86948 -/* 31745 */ MCD_OPC_Decode, 163, 15, 154, 1, // Opcode: LD1Threev8b -/* 31750 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 31765 -/* 31755 */ MCD_OPC_CheckPredicate, 3, 148, 215, 0, // Skip to: 86948 -/* 31760 */ MCD_OPC_Decode, 159, 15, 154, 1, // Opcode: LD1Threev4h -/* 31765 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 31780 -/* 31770 */ MCD_OPC_CheckPredicate, 3, 133, 215, 0, // Skip to: 86948 -/* 31775 */ MCD_OPC_Decode, 157, 15, 154, 1, // Opcode: LD1Threev2s -/* 31780 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 31795 -/* 31785 */ MCD_OPC_CheckPredicate, 3, 118, 215, 0, // Skip to: 86948 -/* 31790 */ MCD_OPC_Decode, 153, 15, 154, 1, // Opcode: LD1Threev1d -/* 31795 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 31810 -/* 31800 */ MCD_OPC_CheckPredicate, 3, 103, 215, 0, // Skip to: 86948 -/* 31805 */ MCD_OPC_Decode, 223, 14, 155, 1, // Opcode: LD1Onev8b -/* 31810 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 31825 -/* 31815 */ MCD_OPC_CheckPredicate, 3, 88, 215, 0, // Skip to: 86948 -/* 31820 */ MCD_OPC_Decode, 219, 14, 155, 1, // Opcode: LD1Onev4h -/* 31825 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 31840 -/* 31830 */ MCD_OPC_CheckPredicate, 3, 73, 215, 0, // Skip to: 86948 -/* 31835 */ MCD_OPC_Decode, 217, 14, 155, 1, // Opcode: LD1Onev2s -/* 31840 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 31855 -/* 31845 */ MCD_OPC_CheckPredicate, 3, 58, 215, 0, // Skip to: 86948 -/* 31850 */ MCD_OPC_Decode, 213, 14, 155, 1, // Opcode: LD1Onev1d -/* 31855 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 31870 -/* 31860 */ MCD_OPC_CheckPredicate, 3, 43, 215, 0, // Skip to: 86948 -/* 31865 */ MCD_OPC_Decode, 227, 15, 156, 1, // Opcode: LD2Twov8b -/* 31870 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 31885 -/* 31875 */ MCD_OPC_CheckPredicate, 3, 28, 215, 0, // Skip to: 86948 -/* 31880 */ MCD_OPC_Decode, 223, 15, 156, 1, // Opcode: LD2Twov4h -/* 31885 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 31900 -/* 31890 */ MCD_OPC_CheckPredicate, 3, 13, 215, 0, // Skip to: 86948 -/* 31895 */ MCD_OPC_Decode, 221, 15, 156, 1, // Opcode: LD2Twov2s -/* 31900 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 31915 -/* 31905 */ MCD_OPC_CheckPredicate, 3, 254, 214, 0, // Skip to: 86948 -/* 31910 */ MCD_OPC_Decode, 179, 15, 156, 1, // Opcode: LD1Twov8b -/* 31915 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 31930 -/* 31920 */ MCD_OPC_CheckPredicate, 3, 239, 214, 0, // Skip to: 86948 -/* 31925 */ MCD_OPC_Decode, 175, 15, 156, 1, // Opcode: LD1Twov4h -/* 31930 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 31945 -/* 31935 */ MCD_OPC_CheckPredicate, 3, 224, 214, 0, // Skip to: 86948 -/* 31940 */ MCD_OPC_Decode, 173, 15, 156, 1, // Opcode: LD1Twov2s -/* 31945 */ MCD_OPC_FilterValue, 43, 214, 214, 0, // Skip to: 86948 -/* 31950 */ MCD_OPC_CheckPredicate, 3, 209, 214, 0, // Skip to: 86948 -/* 31955 */ MCD_OPC_Decode, 169, 15, 156, 1, // Opcode: LD1Twov1d -/* 31960 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 31970 -/* 31965 */ MCD_OPC_Decode, 186, 17, 150, 1, // Opcode: LDNPSi -/* 31970 */ MCD_OPC_FilterValue, 2, 167, 1, 0, // Skip to: 32398 -/* 31975 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... -/* 31978 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 31993 -/* 31983 */ MCD_OPC_CheckPredicate, 3, 176, 214, 0, // Skip to: 86948 -/* 31988 */ MCD_OPC_Decode, 163, 16, 157, 1, // Opcode: LD4Fourv16b -/* 31993 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 32008 -/* 31998 */ MCD_OPC_CheckPredicate, 3, 161, 214, 0, // Skip to: 86948 -/* 32003 */ MCD_OPC_Decode, 175, 16, 157, 1, // Opcode: LD4Fourv8h -/* 32008 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 32023 -/* 32013 */ MCD_OPC_CheckPredicate, 3, 146, 214, 0, // Skip to: 86948 -/* 32018 */ MCD_OPC_Decode, 171, 16, 157, 1, // Opcode: LD4Fourv4s -/* 32023 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 32038 -/* 32028 */ MCD_OPC_CheckPredicate, 3, 131, 214, 0, // Skip to: 86948 -/* 32033 */ MCD_OPC_Decode, 165, 16, 157, 1, // Opcode: LD4Fourv2d -/* 32038 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 32053 -/* 32043 */ MCD_OPC_CheckPredicate, 3, 116, 214, 0, // Skip to: 86948 -/* 32048 */ MCD_OPC_Decode, 189, 14, 157, 1, // Opcode: LD1Fourv16b -/* 32053 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 32068 -/* 32058 */ MCD_OPC_CheckPredicate, 3, 101, 214, 0, // Skip to: 86948 -/* 32063 */ MCD_OPC_Decode, 203, 14, 157, 1, // Opcode: LD1Fourv8h -/* 32068 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 32083 -/* 32073 */ MCD_OPC_CheckPredicate, 3, 86, 214, 0, // Skip to: 86948 -/* 32078 */ MCD_OPC_Decode, 199, 14, 157, 1, // Opcode: LD1Fourv4s -/* 32083 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 32098 -/* 32088 */ MCD_OPC_CheckPredicate, 3, 71, 214, 0, // Skip to: 86948 -/* 32093 */ MCD_OPC_Decode, 193, 14, 157, 1, // Opcode: LD1Fourv2d -/* 32098 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 32113 -/* 32103 */ MCD_OPC_CheckPredicate, 3, 56, 214, 0, // Skip to: 86948 -/* 32108 */ MCD_OPC_Decode, 135, 16, 158, 1, // Opcode: LD3Threev16b -/* 32113 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 32128 -/* 32118 */ MCD_OPC_CheckPredicate, 3, 41, 214, 0, // Skip to: 86948 -/* 32123 */ MCD_OPC_Decode, 147, 16, 158, 1, // Opcode: LD3Threev8h -/* 32128 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 32143 -/* 32133 */ MCD_OPC_CheckPredicate, 3, 26, 214, 0, // Skip to: 86948 -/* 32138 */ MCD_OPC_Decode, 143, 16, 158, 1, // Opcode: LD3Threev4s -/* 32143 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 32158 -/* 32148 */ MCD_OPC_CheckPredicate, 3, 11, 214, 0, // Skip to: 86948 -/* 32153 */ MCD_OPC_Decode, 137, 16, 158, 1, // Opcode: LD3Threev2d -/* 32158 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 32173 -/* 32163 */ MCD_OPC_CheckPredicate, 3, 252, 213, 0, // Skip to: 86948 -/* 32168 */ MCD_OPC_Decode, 151, 15, 158, 1, // Opcode: LD1Threev16b -/* 32173 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 32188 -/* 32178 */ MCD_OPC_CheckPredicate, 3, 237, 213, 0, // Skip to: 86948 -/* 32183 */ MCD_OPC_Decode, 165, 15, 158, 1, // Opcode: LD1Threev8h -/* 32188 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 32203 -/* 32193 */ MCD_OPC_CheckPredicate, 3, 222, 213, 0, // Skip to: 86948 -/* 32198 */ MCD_OPC_Decode, 161, 15, 158, 1, // Opcode: LD1Threev4s -/* 32203 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 32218 -/* 32208 */ MCD_OPC_CheckPredicate, 3, 207, 213, 0, // Skip to: 86948 -/* 32213 */ MCD_OPC_Decode, 155, 15, 158, 1, // Opcode: LD1Threev2d -/* 32218 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 32233 -/* 32223 */ MCD_OPC_CheckPredicate, 3, 192, 213, 0, // Skip to: 86948 -/* 32228 */ MCD_OPC_Decode, 211, 14, 159, 1, // Opcode: LD1Onev16b -/* 32233 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 32248 -/* 32238 */ MCD_OPC_CheckPredicate, 3, 177, 213, 0, // Skip to: 86948 -/* 32243 */ MCD_OPC_Decode, 225, 14, 159, 1, // Opcode: LD1Onev8h -/* 32248 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 32263 -/* 32253 */ MCD_OPC_CheckPredicate, 3, 162, 213, 0, // Skip to: 86948 -/* 32258 */ MCD_OPC_Decode, 221, 14, 159, 1, // Opcode: LD1Onev4s -/* 32263 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 32278 -/* 32268 */ MCD_OPC_CheckPredicate, 3, 147, 213, 0, // Skip to: 86948 -/* 32273 */ MCD_OPC_Decode, 215, 14, 159, 1, // Opcode: LD1Onev2d -/* 32278 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 32293 -/* 32283 */ MCD_OPC_CheckPredicate, 3, 132, 213, 0, // Skip to: 86948 -/* 32288 */ MCD_OPC_Decode, 217, 15, 160, 1, // Opcode: LD2Twov16b -/* 32293 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 32308 -/* 32298 */ MCD_OPC_CheckPredicate, 3, 117, 213, 0, // Skip to: 86948 -/* 32303 */ MCD_OPC_Decode, 229, 15, 160, 1, // Opcode: LD2Twov8h -/* 32308 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 32323 -/* 32313 */ MCD_OPC_CheckPredicate, 3, 102, 213, 0, // Skip to: 86948 -/* 32318 */ MCD_OPC_Decode, 225, 15, 160, 1, // Opcode: LD2Twov4s -/* 32323 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 32338 -/* 32328 */ MCD_OPC_CheckPredicate, 3, 87, 213, 0, // Skip to: 86948 -/* 32333 */ MCD_OPC_Decode, 219, 15, 160, 1, // Opcode: LD2Twov2d -/* 32338 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 32353 -/* 32343 */ MCD_OPC_CheckPredicate, 3, 72, 213, 0, // Skip to: 86948 -/* 32348 */ MCD_OPC_Decode, 167, 15, 160, 1, // Opcode: LD1Twov16b -/* 32353 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 32368 -/* 32358 */ MCD_OPC_CheckPredicate, 3, 57, 213, 0, // Skip to: 86948 -/* 32363 */ MCD_OPC_Decode, 181, 15, 160, 1, // Opcode: LD1Twov8h -/* 32368 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 32383 -/* 32373 */ MCD_OPC_CheckPredicate, 3, 42, 213, 0, // Skip to: 86948 -/* 32378 */ MCD_OPC_Decode, 177, 15, 160, 1, // Opcode: LD1Twov4s -/* 32383 */ MCD_OPC_FilterValue, 43, 32, 213, 0, // Skip to: 86948 -/* 32388 */ MCD_OPC_CheckPredicate, 3, 27, 213, 0, // Skip to: 86948 -/* 32393 */ MCD_OPC_Decode, 171, 15, 160, 1, // Opcode: LD1Twov2d -/* 32398 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 32408 -/* 32403 */ MCD_OPC_Decode, 184, 17, 150, 1, // Opcode: LDNPDi -/* 32408 */ MCD_OPC_FilterValue, 5, 7, 213, 0, // Skip to: 86948 -/* 32413 */ MCD_OPC_Decode, 185, 17, 150, 1, // Opcode: LDNPQi -/* 32418 */ MCD_OPC_FilterValue, 2, 191, 4, 0, // Skip to: 33638 -/* 32423 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 32426 */ MCD_OPC_FilterValue, 0, 41, 2, 0, // Skip to: 32984 -/* 32431 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 32434 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 32456 -/* 32439 */ MCD_OPC_CheckPredicate, 3, 232, 212, 0, // Skip to: 86948 -/* 32444 */ MCD_OPC_CheckField, 21, 1, 0, 225, 212, 0, // Skip to: 86948 -/* 32451 */ MCD_OPC_Decode, 212, 28, 161, 1, // Opcode: ST4Fourv8b_POST -/* 32456 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 32478 -/* 32461 */ MCD_OPC_CheckPredicate, 3, 210, 212, 0, // Skip to: 86948 -/* 32466 */ MCD_OPC_CheckField, 21, 1, 0, 203, 212, 0, // Skip to: 86948 -/* 32473 */ MCD_OPC_Decode, 208, 28, 161, 1, // Opcode: ST4Fourv4h_POST -/* 32478 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 32500 -/* 32483 */ MCD_OPC_CheckPredicate, 3, 188, 212, 0, // Skip to: 86948 -/* 32488 */ MCD_OPC_CheckField, 21, 1, 0, 181, 212, 0, // Skip to: 86948 -/* 32495 */ MCD_OPC_Decode, 206, 28, 161, 1, // Opcode: ST4Fourv2s_POST -/* 32500 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 32522 -/* 32505 */ MCD_OPC_CheckPredicate, 3, 166, 212, 0, // Skip to: 86948 -/* 32510 */ MCD_OPC_CheckField, 21, 1, 0, 159, 212, 0, // Skip to: 86948 -/* 32517 */ MCD_OPC_Decode, 196, 27, 161, 1, // Opcode: ST1Fourv8b_POST -/* 32522 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 32544 -/* 32527 */ MCD_OPC_CheckPredicate, 3, 144, 212, 0, // Skip to: 86948 -/* 32532 */ MCD_OPC_CheckField, 21, 1, 0, 137, 212, 0, // Skip to: 86948 -/* 32539 */ MCD_OPC_Decode, 192, 27, 161, 1, // Opcode: ST1Fourv4h_POST -/* 32544 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 32566 -/* 32549 */ MCD_OPC_CheckPredicate, 3, 122, 212, 0, // Skip to: 86948 -/* 32554 */ MCD_OPC_CheckField, 21, 1, 0, 115, 212, 0, // Skip to: 86948 -/* 32561 */ MCD_OPC_Decode, 190, 27, 161, 1, // Opcode: ST1Fourv2s_POST -/* 32566 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 32588 -/* 32571 */ MCD_OPC_CheckPredicate, 3, 100, 212, 0, // Skip to: 86948 -/* 32576 */ MCD_OPC_CheckField, 21, 1, 0, 93, 212, 0, // Skip to: 86948 -/* 32583 */ MCD_OPC_Decode, 186, 27, 161, 1, // Opcode: ST1Fourv1d_POST -/* 32588 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 32610 -/* 32593 */ MCD_OPC_CheckPredicate, 3, 78, 212, 0, // Skip to: 86948 -/* 32598 */ MCD_OPC_CheckField, 21, 1, 0, 71, 212, 0, // Skip to: 86948 -/* 32605 */ MCD_OPC_Decode, 184, 28, 162, 1, // Opcode: ST3Threev8b_POST -/* 32610 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 32632 -/* 32615 */ MCD_OPC_CheckPredicate, 3, 56, 212, 0, // Skip to: 86948 -/* 32620 */ MCD_OPC_CheckField, 21, 1, 0, 49, 212, 0, // Skip to: 86948 -/* 32627 */ MCD_OPC_Decode, 180, 28, 162, 1, // Opcode: ST3Threev4h_POST -/* 32632 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 32654 -/* 32637 */ MCD_OPC_CheckPredicate, 3, 34, 212, 0, // Skip to: 86948 -/* 32642 */ MCD_OPC_CheckField, 21, 1, 0, 27, 212, 0, // Skip to: 86948 -/* 32649 */ MCD_OPC_Decode, 178, 28, 162, 1, // Opcode: ST3Threev2s_POST -/* 32654 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 32676 -/* 32659 */ MCD_OPC_CheckPredicate, 3, 12, 212, 0, // Skip to: 86948 -/* 32664 */ MCD_OPC_CheckField, 21, 1, 0, 5, 212, 0, // Skip to: 86948 -/* 32671 */ MCD_OPC_Decode, 234, 27, 162, 1, // Opcode: ST1Threev8b_POST -/* 32676 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 32698 -/* 32681 */ MCD_OPC_CheckPredicate, 3, 246, 211, 0, // Skip to: 86948 -/* 32686 */ MCD_OPC_CheckField, 21, 1, 0, 239, 211, 0, // Skip to: 86948 -/* 32693 */ MCD_OPC_Decode, 230, 27, 162, 1, // Opcode: ST1Threev4h_POST -/* 32698 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 32720 -/* 32703 */ MCD_OPC_CheckPredicate, 3, 224, 211, 0, // Skip to: 86948 -/* 32708 */ MCD_OPC_CheckField, 21, 1, 0, 217, 211, 0, // Skip to: 86948 -/* 32715 */ MCD_OPC_Decode, 228, 27, 162, 1, // Opcode: ST1Threev2s_POST -/* 32720 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 32742 -/* 32725 */ MCD_OPC_CheckPredicate, 3, 202, 211, 0, // Skip to: 86948 -/* 32730 */ MCD_OPC_CheckField, 21, 1, 0, 195, 211, 0, // Skip to: 86948 -/* 32737 */ MCD_OPC_Decode, 224, 27, 162, 1, // Opcode: ST1Threev1d_POST -/* 32742 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 32764 -/* 32747 */ MCD_OPC_CheckPredicate, 3, 180, 211, 0, // Skip to: 86948 -/* 32752 */ MCD_OPC_CheckField, 21, 1, 0, 173, 211, 0, // Skip to: 86948 -/* 32759 */ MCD_OPC_Decode, 218, 27, 163, 1, // Opcode: ST1Onev8b_POST -/* 32764 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 32786 -/* 32769 */ MCD_OPC_CheckPredicate, 3, 158, 211, 0, // Skip to: 86948 -/* 32774 */ MCD_OPC_CheckField, 21, 1, 0, 151, 211, 0, // Skip to: 86948 -/* 32781 */ MCD_OPC_Decode, 214, 27, 163, 1, // Opcode: ST1Onev4h_POST -/* 32786 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 32808 -/* 32791 */ MCD_OPC_CheckPredicate, 3, 136, 211, 0, // Skip to: 86948 -/* 32796 */ MCD_OPC_CheckField, 21, 1, 0, 129, 211, 0, // Skip to: 86948 -/* 32803 */ MCD_OPC_Decode, 212, 27, 163, 1, // Opcode: ST1Onev2s_POST -/* 32808 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 32830 -/* 32813 */ MCD_OPC_CheckPredicate, 3, 114, 211, 0, // Skip to: 86948 -/* 32818 */ MCD_OPC_CheckField, 21, 1, 0, 107, 211, 0, // Skip to: 86948 -/* 32825 */ MCD_OPC_Decode, 208, 27, 163, 1, // Opcode: ST1Onev1d_POST -/* 32830 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 32852 -/* 32835 */ MCD_OPC_CheckPredicate, 3, 92, 211, 0, // Skip to: 86948 -/* 32840 */ MCD_OPC_CheckField, 21, 1, 0, 85, 211, 0, // Skip to: 86948 -/* 32847 */ MCD_OPC_Decode, 154, 28, 164, 1, // Opcode: ST2Twov8b_POST -/* 32852 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 32874 -/* 32857 */ MCD_OPC_CheckPredicate, 3, 70, 211, 0, // Skip to: 86948 -/* 32862 */ MCD_OPC_CheckField, 21, 1, 0, 63, 211, 0, // Skip to: 86948 -/* 32869 */ MCD_OPC_Decode, 150, 28, 164, 1, // Opcode: ST2Twov4h_POST -/* 32874 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 32896 -/* 32879 */ MCD_OPC_CheckPredicate, 3, 48, 211, 0, // Skip to: 86948 -/* 32884 */ MCD_OPC_CheckField, 21, 1, 0, 41, 211, 0, // Skip to: 86948 -/* 32891 */ MCD_OPC_Decode, 148, 28, 164, 1, // Opcode: ST2Twov2s_POST -/* 32896 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 32918 -/* 32901 */ MCD_OPC_CheckPredicate, 3, 26, 211, 0, // Skip to: 86948 -/* 32906 */ MCD_OPC_CheckField, 21, 1, 0, 19, 211, 0, // Skip to: 86948 -/* 32913 */ MCD_OPC_Decode, 250, 27, 164, 1, // Opcode: ST1Twov8b_POST -/* 32918 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 32940 -/* 32923 */ MCD_OPC_CheckPredicate, 3, 4, 211, 0, // Skip to: 86948 -/* 32928 */ MCD_OPC_CheckField, 21, 1, 0, 253, 210, 0, // Skip to: 86948 -/* 32935 */ MCD_OPC_Decode, 246, 27, 164, 1, // Opcode: ST1Twov4h_POST -/* 32940 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 32962 -/* 32945 */ MCD_OPC_CheckPredicate, 3, 238, 210, 0, // Skip to: 86948 -/* 32950 */ MCD_OPC_CheckField, 21, 1, 0, 231, 210, 0, // Skip to: 86948 -/* 32957 */ MCD_OPC_Decode, 244, 27, 164, 1, // Opcode: ST1Twov2s_POST -/* 32962 */ MCD_OPC_FilterValue, 43, 221, 210, 0, // Skip to: 86948 -/* 32967 */ MCD_OPC_CheckPredicate, 3, 216, 210, 0, // Skip to: 86948 -/* 32972 */ MCD_OPC_CheckField, 21, 1, 0, 209, 210, 0, // Skip to: 86948 -/* 32979 */ MCD_OPC_Decode, 240, 27, 164, 1, // Opcode: ST1Twov1d_POST -/* 32984 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 32994 -/* 32989 */ MCD_OPC_Decode, 137, 29, 150, 1, // Opcode: STPSpost -/* 32994 */ MCD_OPC_FilterValue, 2, 107, 2, 0, // Skip to: 33618 -/* 32999 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 33002 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 33024 -/* 33007 */ MCD_OPC_CheckPredicate, 3, 176, 210, 0, // Skip to: 86948 -/* 33012 */ MCD_OPC_CheckField, 21, 1, 0, 169, 210, 0, // Skip to: 86948 -/* 33019 */ MCD_OPC_Decode, 202, 28, 165, 1, // Opcode: ST4Fourv16b_POST -/* 33024 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 33046 -/* 33029 */ MCD_OPC_CheckPredicate, 3, 154, 210, 0, // Skip to: 86948 -/* 33034 */ MCD_OPC_CheckField, 21, 1, 0, 147, 210, 0, // Skip to: 86948 -/* 33041 */ MCD_OPC_Decode, 214, 28, 165, 1, // Opcode: ST4Fourv8h_POST -/* 33046 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 33068 -/* 33051 */ MCD_OPC_CheckPredicate, 3, 132, 210, 0, // Skip to: 86948 -/* 33056 */ MCD_OPC_CheckField, 21, 1, 0, 125, 210, 0, // Skip to: 86948 -/* 33063 */ MCD_OPC_Decode, 210, 28, 165, 1, // Opcode: ST4Fourv4s_POST -/* 33068 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 33090 -/* 33073 */ MCD_OPC_CheckPredicate, 3, 110, 210, 0, // Skip to: 86948 -/* 33078 */ MCD_OPC_CheckField, 21, 1, 0, 103, 210, 0, // Skip to: 86948 -/* 33085 */ MCD_OPC_Decode, 204, 28, 165, 1, // Opcode: ST4Fourv2d_POST -/* 33090 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 33112 -/* 33095 */ MCD_OPC_CheckPredicate, 3, 88, 210, 0, // Skip to: 86948 -/* 33100 */ MCD_OPC_CheckField, 21, 1, 0, 81, 210, 0, // Skip to: 86948 -/* 33107 */ MCD_OPC_Decode, 184, 27, 165, 1, // Opcode: ST1Fourv16b_POST -/* 33112 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 33134 -/* 33117 */ MCD_OPC_CheckPredicate, 3, 66, 210, 0, // Skip to: 86948 -/* 33122 */ MCD_OPC_CheckField, 21, 1, 0, 59, 210, 0, // Skip to: 86948 -/* 33129 */ MCD_OPC_Decode, 198, 27, 165, 1, // Opcode: ST1Fourv8h_POST -/* 33134 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 33156 -/* 33139 */ MCD_OPC_CheckPredicate, 3, 44, 210, 0, // Skip to: 86948 -/* 33144 */ MCD_OPC_CheckField, 21, 1, 0, 37, 210, 0, // Skip to: 86948 -/* 33151 */ MCD_OPC_Decode, 194, 27, 165, 1, // Opcode: ST1Fourv4s_POST -/* 33156 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 33178 -/* 33161 */ MCD_OPC_CheckPredicate, 3, 22, 210, 0, // Skip to: 86948 -/* 33166 */ MCD_OPC_CheckField, 21, 1, 0, 15, 210, 0, // Skip to: 86948 -/* 33173 */ MCD_OPC_Decode, 188, 27, 165, 1, // Opcode: ST1Fourv2d_POST -/* 33178 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 33200 -/* 33183 */ MCD_OPC_CheckPredicate, 3, 0, 210, 0, // Skip to: 86948 -/* 33188 */ MCD_OPC_CheckField, 21, 1, 0, 249, 209, 0, // Skip to: 86948 -/* 33195 */ MCD_OPC_Decode, 174, 28, 166, 1, // Opcode: ST3Threev16b_POST -/* 33200 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 33222 -/* 33205 */ MCD_OPC_CheckPredicate, 3, 234, 209, 0, // Skip to: 86948 -/* 33210 */ MCD_OPC_CheckField, 21, 1, 0, 227, 209, 0, // Skip to: 86948 -/* 33217 */ MCD_OPC_Decode, 186, 28, 166, 1, // Opcode: ST3Threev8h_POST -/* 33222 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 33244 -/* 33227 */ MCD_OPC_CheckPredicate, 3, 212, 209, 0, // Skip to: 86948 -/* 33232 */ MCD_OPC_CheckField, 21, 1, 0, 205, 209, 0, // Skip to: 86948 -/* 33239 */ MCD_OPC_Decode, 182, 28, 166, 1, // Opcode: ST3Threev4s_POST -/* 33244 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 33266 -/* 33249 */ MCD_OPC_CheckPredicate, 3, 190, 209, 0, // Skip to: 86948 -/* 33254 */ MCD_OPC_CheckField, 21, 1, 0, 183, 209, 0, // Skip to: 86948 -/* 33261 */ MCD_OPC_Decode, 176, 28, 166, 1, // Opcode: ST3Threev2d_POST -/* 33266 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 33288 -/* 33271 */ MCD_OPC_CheckPredicate, 3, 168, 209, 0, // Skip to: 86948 -/* 33276 */ MCD_OPC_CheckField, 21, 1, 0, 161, 209, 0, // Skip to: 86948 -/* 33283 */ MCD_OPC_Decode, 222, 27, 166, 1, // Opcode: ST1Threev16b_POST -/* 33288 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 33310 -/* 33293 */ MCD_OPC_CheckPredicate, 3, 146, 209, 0, // Skip to: 86948 -/* 33298 */ MCD_OPC_CheckField, 21, 1, 0, 139, 209, 0, // Skip to: 86948 -/* 33305 */ MCD_OPC_Decode, 236, 27, 166, 1, // Opcode: ST1Threev8h_POST -/* 33310 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 33332 -/* 33315 */ MCD_OPC_CheckPredicate, 3, 124, 209, 0, // Skip to: 86948 -/* 33320 */ MCD_OPC_CheckField, 21, 1, 0, 117, 209, 0, // Skip to: 86948 -/* 33327 */ MCD_OPC_Decode, 232, 27, 166, 1, // Opcode: ST1Threev4s_POST -/* 33332 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 33354 -/* 33337 */ MCD_OPC_CheckPredicate, 3, 102, 209, 0, // Skip to: 86948 -/* 33342 */ MCD_OPC_CheckField, 21, 1, 0, 95, 209, 0, // Skip to: 86948 -/* 33349 */ MCD_OPC_Decode, 226, 27, 166, 1, // Opcode: ST1Threev2d_POST -/* 33354 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 33376 -/* 33359 */ MCD_OPC_CheckPredicate, 3, 80, 209, 0, // Skip to: 86948 -/* 33364 */ MCD_OPC_CheckField, 21, 1, 0, 73, 209, 0, // Skip to: 86948 -/* 33371 */ MCD_OPC_Decode, 206, 27, 167, 1, // Opcode: ST1Onev16b_POST -/* 33376 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 33398 -/* 33381 */ MCD_OPC_CheckPredicate, 3, 58, 209, 0, // Skip to: 86948 -/* 33386 */ MCD_OPC_CheckField, 21, 1, 0, 51, 209, 0, // Skip to: 86948 -/* 33393 */ MCD_OPC_Decode, 220, 27, 167, 1, // Opcode: ST1Onev8h_POST -/* 33398 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 33420 -/* 33403 */ MCD_OPC_CheckPredicate, 3, 36, 209, 0, // Skip to: 86948 -/* 33408 */ MCD_OPC_CheckField, 21, 1, 0, 29, 209, 0, // Skip to: 86948 -/* 33415 */ MCD_OPC_Decode, 216, 27, 167, 1, // Opcode: ST1Onev4s_POST -/* 33420 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 33442 -/* 33425 */ MCD_OPC_CheckPredicate, 3, 14, 209, 0, // Skip to: 86948 -/* 33430 */ MCD_OPC_CheckField, 21, 1, 0, 7, 209, 0, // Skip to: 86948 -/* 33437 */ MCD_OPC_Decode, 210, 27, 167, 1, // Opcode: ST1Onev2d_POST -/* 33442 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 33464 -/* 33447 */ MCD_OPC_CheckPredicate, 3, 248, 208, 0, // Skip to: 86948 -/* 33452 */ MCD_OPC_CheckField, 21, 1, 0, 241, 208, 0, // Skip to: 86948 -/* 33459 */ MCD_OPC_Decode, 144, 28, 168, 1, // Opcode: ST2Twov16b_POST -/* 33464 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 33486 -/* 33469 */ MCD_OPC_CheckPredicate, 3, 226, 208, 0, // Skip to: 86948 -/* 33474 */ MCD_OPC_CheckField, 21, 1, 0, 219, 208, 0, // Skip to: 86948 -/* 33481 */ MCD_OPC_Decode, 156, 28, 168, 1, // Opcode: ST2Twov8h_POST -/* 33486 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 33508 -/* 33491 */ MCD_OPC_CheckPredicate, 3, 204, 208, 0, // Skip to: 86948 -/* 33496 */ MCD_OPC_CheckField, 21, 1, 0, 197, 208, 0, // Skip to: 86948 -/* 33503 */ MCD_OPC_Decode, 152, 28, 168, 1, // Opcode: ST2Twov4s_POST -/* 33508 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 33530 -/* 33513 */ MCD_OPC_CheckPredicate, 3, 182, 208, 0, // Skip to: 86948 -/* 33518 */ MCD_OPC_CheckField, 21, 1, 0, 175, 208, 0, // Skip to: 86948 -/* 33525 */ MCD_OPC_Decode, 146, 28, 168, 1, // Opcode: ST2Twov2d_POST -/* 33530 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 33552 -/* 33535 */ MCD_OPC_CheckPredicate, 3, 160, 208, 0, // Skip to: 86948 -/* 33540 */ MCD_OPC_CheckField, 21, 1, 0, 153, 208, 0, // Skip to: 86948 -/* 33547 */ MCD_OPC_Decode, 238, 27, 168, 1, // Opcode: ST1Twov16b_POST -/* 33552 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 33574 -/* 33557 */ MCD_OPC_CheckPredicate, 3, 138, 208, 0, // Skip to: 86948 -/* 33562 */ MCD_OPC_CheckField, 21, 1, 0, 131, 208, 0, // Skip to: 86948 -/* 33569 */ MCD_OPC_Decode, 252, 27, 168, 1, // Opcode: ST1Twov8h_POST -/* 33574 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 33596 -/* 33579 */ MCD_OPC_CheckPredicate, 3, 116, 208, 0, // Skip to: 86948 -/* 33584 */ MCD_OPC_CheckField, 21, 1, 0, 109, 208, 0, // Skip to: 86948 -/* 33591 */ MCD_OPC_Decode, 248, 27, 168, 1, // Opcode: ST1Twov4s_POST -/* 33596 */ MCD_OPC_FilterValue, 43, 99, 208, 0, // Skip to: 86948 -/* 33601 */ MCD_OPC_CheckPredicate, 3, 94, 208, 0, // Skip to: 86948 -/* 33606 */ MCD_OPC_CheckField, 21, 1, 0, 87, 208, 0, // Skip to: 86948 -/* 33613 */ MCD_OPC_Decode, 242, 27, 168, 1, // Opcode: ST1Twov2d_POST -/* 33618 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 33628 -/* 33623 */ MCD_OPC_Decode, 131, 29, 150, 1, // Opcode: STPDpost -/* 33628 */ MCD_OPC_FilterValue, 5, 67, 208, 0, // Skip to: 86948 -/* 33633 */ MCD_OPC_Decode, 134, 29, 150, 1, // Opcode: STPQpost -/* 33638 */ MCD_OPC_FilterValue, 3, 191, 4, 0, // Skip to: 34858 -/* 33643 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 33646 */ MCD_OPC_FilterValue, 0, 41, 2, 0, // Skip to: 34204 -/* 33651 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 33654 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 33676 -/* 33659 */ MCD_OPC_CheckPredicate, 3, 36, 208, 0, // Skip to: 86948 -/* 33664 */ MCD_OPC_CheckField, 21, 1, 0, 29, 208, 0, // Skip to: 86948 -/* 33671 */ MCD_OPC_Decode, 174, 16, 161, 1, // Opcode: LD4Fourv8b_POST -/* 33676 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 33698 -/* 33681 */ MCD_OPC_CheckPredicate, 3, 14, 208, 0, // Skip to: 86948 -/* 33686 */ MCD_OPC_CheckField, 21, 1, 0, 7, 208, 0, // Skip to: 86948 -/* 33693 */ MCD_OPC_Decode, 170, 16, 161, 1, // Opcode: LD4Fourv4h_POST -/* 33698 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 33720 -/* 33703 */ MCD_OPC_CheckPredicate, 3, 248, 207, 0, // Skip to: 86948 -/* 33708 */ MCD_OPC_CheckField, 21, 1, 0, 241, 207, 0, // Skip to: 86948 -/* 33715 */ MCD_OPC_Decode, 168, 16, 161, 1, // Opcode: LD4Fourv2s_POST -/* 33720 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 33742 -/* 33725 */ MCD_OPC_CheckPredicate, 3, 226, 207, 0, // Skip to: 86948 -/* 33730 */ MCD_OPC_CheckField, 21, 1, 0, 219, 207, 0, // Skip to: 86948 -/* 33737 */ MCD_OPC_Decode, 202, 14, 161, 1, // Opcode: LD1Fourv8b_POST -/* 33742 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 33764 -/* 33747 */ MCD_OPC_CheckPredicate, 3, 204, 207, 0, // Skip to: 86948 -/* 33752 */ MCD_OPC_CheckField, 21, 1, 0, 197, 207, 0, // Skip to: 86948 -/* 33759 */ MCD_OPC_Decode, 198, 14, 161, 1, // Opcode: LD1Fourv4h_POST -/* 33764 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 33786 -/* 33769 */ MCD_OPC_CheckPredicate, 3, 182, 207, 0, // Skip to: 86948 -/* 33774 */ MCD_OPC_CheckField, 21, 1, 0, 175, 207, 0, // Skip to: 86948 -/* 33781 */ MCD_OPC_Decode, 196, 14, 161, 1, // Opcode: LD1Fourv2s_POST -/* 33786 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 33808 -/* 33791 */ MCD_OPC_CheckPredicate, 3, 160, 207, 0, // Skip to: 86948 -/* 33796 */ MCD_OPC_CheckField, 21, 1, 0, 153, 207, 0, // Skip to: 86948 -/* 33803 */ MCD_OPC_Decode, 192, 14, 161, 1, // Opcode: LD1Fourv1d_POST -/* 33808 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 33830 -/* 33813 */ MCD_OPC_CheckPredicate, 3, 138, 207, 0, // Skip to: 86948 -/* 33818 */ MCD_OPC_CheckField, 21, 1, 0, 131, 207, 0, // Skip to: 86948 -/* 33825 */ MCD_OPC_Decode, 146, 16, 162, 1, // Opcode: LD3Threev8b_POST -/* 33830 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 33852 -/* 33835 */ MCD_OPC_CheckPredicate, 3, 116, 207, 0, // Skip to: 86948 -/* 33840 */ MCD_OPC_CheckField, 21, 1, 0, 109, 207, 0, // Skip to: 86948 -/* 33847 */ MCD_OPC_Decode, 142, 16, 162, 1, // Opcode: LD3Threev4h_POST -/* 33852 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 33874 -/* 33857 */ MCD_OPC_CheckPredicate, 3, 94, 207, 0, // Skip to: 86948 -/* 33862 */ MCD_OPC_CheckField, 21, 1, 0, 87, 207, 0, // Skip to: 86948 -/* 33869 */ MCD_OPC_Decode, 140, 16, 162, 1, // Opcode: LD3Threev2s_POST -/* 33874 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 33896 -/* 33879 */ MCD_OPC_CheckPredicate, 3, 72, 207, 0, // Skip to: 86948 -/* 33884 */ MCD_OPC_CheckField, 21, 1, 0, 65, 207, 0, // Skip to: 86948 -/* 33891 */ MCD_OPC_Decode, 164, 15, 162, 1, // Opcode: LD1Threev8b_POST -/* 33896 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 33918 -/* 33901 */ MCD_OPC_CheckPredicate, 3, 50, 207, 0, // Skip to: 86948 -/* 33906 */ MCD_OPC_CheckField, 21, 1, 0, 43, 207, 0, // Skip to: 86948 -/* 33913 */ MCD_OPC_Decode, 160, 15, 162, 1, // Opcode: LD1Threev4h_POST -/* 33918 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 33940 -/* 33923 */ MCD_OPC_CheckPredicate, 3, 28, 207, 0, // Skip to: 86948 -/* 33928 */ MCD_OPC_CheckField, 21, 1, 0, 21, 207, 0, // Skip to: 86948 -/* 33935 */ MCD_OPC_Decode, 158, 15, 162, 1, // Opcode: LD1Threev2s_POST -/* 33940 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 33962 -/* 33945 */ MCD_OPC_CheckPredicate, 3, 6, 207, 0, // Skip to: 86948 -/* 33950 */ MCD_OPC_CheckField, 21, 1, 0, 255, 206, 0, // Skip to: 86948 -/* 33957 */ MCD_OPC_Decode, 154, 15, 162, 1, // Opcode: LD1Threev1d_POST -/* 33962 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 33984 -/* 33967 */ MCD_OPC_CheckPredicate, 3, 240, 206, 0, // Skip to: 86948 -/* 33972 */ MCD_OPC_CheckField, 21, 1, 0, 233, 206, 0, // Skip to: 86948 -/* 33979 */ MCD_OPC_Decode, 224, 14, 163, 1, // Opcode: LD1Onev8b_POST -/* 33984 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 34006 -/* 33989 */ MCD_OPC_CheckPredicate, 3, 218, 206, 0, // Skip to: 86948 -/* 33994 */ MCD_OPC_CheckField, 21, 1, 0, 211, 206, 0, // Skip to: 86948 -/* 34001 */ MCD_OPC_Decode, 220, 14, 163, 1, // Opcode: LD1Onev4h_POST -/* 34006 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 34028 -/* 34011 */ MCD_OPC_CheckPredicate, 3, 196, 206, 0, // Skip to: 86948 -/* 34016 */ MCD_OPC_CheckField, 21, 1, 0, 189, 206, 0, // Skip to: 86948 -/* 34023 */ MCD_OPC_Decode, 218, 14, 163, 1, // Opcode: LD1Onev2s_POST -/* 34028 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 34050 -/* 34033 */ MCD_OPC_CheckPredicate, 3, 174, 206, 0, // Skip to: 86948 -/* 34038 */ MCD_OPC_CheckField, 21, 1, 0, 167, 206, 0, // Skip to: 86948 -/* 34045 */ MCD_OPC_Decode, 214, 14, 163, 1, // Opcode: LD1Onev1d_POST -/* 34050 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 34072 -/* 34055 */ MCD_OPC_CheckPredicate, 3, 152, 206, 0, // Skip to: 86948 -/* 34060 */ MCD_OPC_CheckField, 21, 1, 0, 145, 206, 0, // Skip to: 86948 -/* 34067 */ MCD_OPC_Decode, 228, 15, 164, 1, // Opcode: LD2Twov8b_POST -/* 34072 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 34094 -/* 34077 */ MCD_OPC_CheckPredicate, 3, 130, 206, 0, // Skip to: 86948 -/* 34082 */ MCD_OPC_CheckField, 21, 1, 0, 123, 206, 0, // Skip to: 86948 -/* 34089 */ MCD_OPC_Decode, 224, 15, 164, 1, // Opcode: LD2Twov4h_POST -/* 34094 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 34116 -/* 34099 */ MCD_OPC_CheckPredicate, 3, 108, 206, 0, // Skip to: 86948 -/* 34104 */ MCD_OPC_CheckField, 21, 1, 0, 101, 206, 0, // Skip to: 86948 -/* 34111 */ MCD_OPC_Decode, 222, 15, 164, 1, // Opcode: LD2Twov2s_POST -/* 34116 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 34138 -/* 34121 */ MCD_OPC_CheckPredicate, 3, 86, 206, 0, // Skip to: 86948 -/* 34126 */ MCD_OPC_CheckField, 21, 1, 0, 79, 206, 0, // Skip to: 86948 -/* 34133 */ MCD_OPC_Decode, 180, 15, 164, 1, // Opcode: LD1Twov8b_POST -/* 34138 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 34160 -/* 34143 */ MCD_OPC_CheckPredicate, 3, 64, 206, 0, // Skip to: 86948 -/* 34148 */ MCD_OPC_CheckField, 21, 1, 0, 57, 206, 0, // Skip to: 86948 -/* 34155 */ MCD_OPC_Decode, 176, 15, 164, 1, // Opcode: LD1Twov4h_POST -/* 34160 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 34182 -/* 34165 */ MCD_OPC_CheckPredicate, 3, 42, 206, 0, // Skip to: 86948 -/* 34170 */ MCD_OPC_CheckField, 21, 1, 0, 35, 206, 0, // Skip to: 86948 -/* 34177 */ MCD_OPC_Decode, 174, 15, 164, 1, // Opcode: LD1Twov2s_POST -/* 34182 */ MCD_OPC_FilterValue, 43, 25, 206, 0, // Skip to: 86948 -/* 34187 */ MCD_OPC_CheckPredicate, 3, 20, 206, 0, // Skip to: 86948 -/* 34192 */ MCD_OPC_CheckField, 21, 1, 0, 13, 206, 0, // Skip to: 86948 -/* 34199 */ MCD_OPC_Decode, 170, 15, 164, 1, // Opcode: LD1Twov1d_POST -/* 34204 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 34214 -/* 34209 */ MCD_OPC_Decode, 207, 17, 150, 1, // Opcode: LDPSpost -/* 34214 */ MCD_OPC_FilterValue, 2, 107, 2, 0, // Skip to: 34838 -/* 34219 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 34222 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 34244 -/* 34227 */ MCD_OPC_CheckPredicate, 3, 236, 205, 0, // Skip to: 86948 -/* 34232 */ MCD_OPC_CheckField, 21, 1, 0, 229, 205, 0, // Skip to: 86948 -/* 34239 */ MCD_OPC_Decode, 164, 16, 165, 1, // Opcode: LD4Fourv16b_POST -/* 34244 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 34266 -/* 34249 */ MCD_OPC_CheckPredicate, 3, 214, 205, 0, // Skip to: 86948 -/* 34254 */ MCD_OPC_CheckField, 21, 1, 0, 207, 205, 0, // Skip to: 86948 -/* 34261 */ MCD_OPC_Decode, 176, 16, 165, 1, // Opcode: LD4Fourv8h_POST -/* 34266 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 34288 -/* 34271 */ MCD_OPC_CheckPredicate, 3, 192, 205, 0, // Skip to: 86948 -/* 34276 */ MCD_OPC_CheckField, 21, 1, 0, 185, 205, 0, // Skip to: 86948 -/* 34283 */ MCD_OPC_Decode, 172, 16, 165, 1, // Opcode: LD4Fourv4s_POST -/* 34288 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 34310 -/* 34293 */ MCD_OPC_CheckPredicate, 3, 170, 205, 0, // Skip to: 86948 -/* 34298 */ MCD_OPC_CheckField, 21, 1, 0, 163, 205, 0, // Skip to: 86948 -/* 34305 */ MCD_OPC_Decode, 166, 16, 165, 1, // Opcode: LD4Fourv2d_POST -/* 34310 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 34332 -/* 34315 */ MCD_OPC_CheckPredicate, 3, 148, 205, 0, // Skip to: 86948 -/* 34320 */ MCD_OPC_CheckField, 21, 1, 0, 141, 205, 0, // Skip to: 86948 -/* 34327 */ MCD_OPC_Decode, 190, 14, 165, 1, // Opcode: LD1Fourv16b_POST -/* 34332 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 34354 -/* 34337 */ MCD_OPC_CheckPredicate, 3, 126, 205, 0, // Skip to: 86948 -/* 34342 */ MCD_OPC_CheckField, 21, 1, 0, 119, 205, 0, // Skip to: 86948 -/* 34349 */ MCD_OPC_Decode, 204, 14, 165, 1, // Opcode: LD1Fourv8h_POST -/* 34354 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 34376 -/* 34359 */ MCD_OPC_CheckPredicate, 3, 104, 205, 0, // Skip to: 86948 -/* 34364 */ MCD_OPC_CheckField, 21, 1, 0, 97, 205, 0, // Skip to: 86948 -/* 34371 */ MCD_OPC_Decode, 200, 14, 165, 1, // Opcode: LD1Fourv4s_POST -/* 34376 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 34398 -/* 34381 */ MCD_OPC_CheckPredicate, 3, 82, 205, 0, // Skip to: 86948 -/* 34386 */ MCD_OPC_CheckField, 21, 1, 0, 75, 205, 0, // Skip to: 86948 -/* 34393 */ MCD_OPC_Decode, 194, 14, 165, 1, // Opcode: LD1Fourv2d_POST -/* 34398 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 34420 -/* 34403 */ MCD_OPC_CheckPredicate, 3, 60, 205, 0, // Skip to: 86948 -/* 34408 */ MCD_OPC_CheckField, 21, 1, 0, 53, 205, 0, // Skip to: 86948 -/* 34415 */ MCD_OPC_Decode, 136, 16, 166, 1, // Opcode: LD3Threev16b_POST -/* 34420 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 34442 -/* 34425 */ MCD_OPC_CheckPredicate, 3, 38, 205, 0, // Skip to: 86948 -/* 34430 */ MCD_OPC_CheckField, 21, 1, 0, 31, 205, 0, // Skip to: 86948 -/* 34437 */ MCD_OPC_Decode, 148, 16, 166, 1, // Opcode: LD3Threev8h_POST -/* 34442 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 34464 -/* 34447 */ MCD_OPC_CheckPredicate, 3, 16, 205, 0, // Skip to: 86948 -/* 34452 */ MCD_OPC_CheckField, 21, 1, 0, 9, 205, 0, // Skip to: 86948 -/* 34459 */ MCD_OPC_Decode, 144, 16, 166, 1, // Opcode: LD3Threev4s_POST -/* 34464 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 34486 -/* 34469 */ MCD_OPC_CheckPredicate, 3, 250, 204, 0, // Skip to: 86948 -/* 34474 */ MCD_OPC_CheckField, 21, 1, 0, 243, 204, 0, // Skip to: 86948 -/* 34481 */ MCD_OPC_Decode, 138, 16, 166, 1, // Opcode: LD3Threev2d_POST -/* 34486 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 34508 -/* 34491 */ MCD_OPC_CheckPredicate, 3, 228, 204, 0, // Skip to: 86948 -/* 34496 */ MCD_OPC_CheckField, 21, 1, 0, 221, 204, 0, // Skip to: 86948 -/* 34503 */ MCD_OPC_Decode, 152, 15, 166, 1, // Opcode: LD1Threev16b_POST -/* 34508 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 34530 -/* 34513 */ MCD_OPC_CheckPredicate, 3, 206, 204, 0, // Skip to: 86948 -/* 34518 */ MCD_OPC_CheckField, 21, 1, 0, 199, 204, 0, // Skip to: 86948 -/* 34525 */ MCD_OPC_Decode, 166, 15, 166, 1, // Opcode: LD1Threev8h_POST -/* 34530 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 34552 -/* 34535 */ MCD_OPC_CheckPredicate, 3, 184, 204, 0, // Skip to: 86948 -/* 34540 */ MCD_OPC_CheckField, 21, 1, 0, 177, 204, 0, // Skip to: 86948 -/* 34547 */ MCD_OPC_Decode, 162, 15, 166, 1, // Opcode: LD1Threev4s_POST -/* 34552 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 34574 -/* 34557 */ MCD_OPC_CheckPredicate, 3, 162, 204, 0, // Skip to: 86948 -/* 34562 */ MCD_OPC_CheckField, 21, 1, 0, 155, 204, 0, // Skip to: 86948 -/* 34569 */ MCD_OPC_Decode, 156, 15, 166, 1, // Opcode: LD1Threev2d_POST -/* 34574 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 34596 -/* 34579 */ MCD_OPC_CheckPredicate, 3, 140, 204, 0, // Skip to: 86948 -/* 34584 */ MCD_OPC_CheckField, 21, 1, 0, 133, 204, 0, // Skip to: 86948 -/* 34591 */ MCD_OPC_Decode, 212, 14, 167, 1, // Opcode: LD1Onev16b_POST -/* 34596 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 34618 -/* 34601 */ MCD_OPC_CheckPredicate, 3, 118, 204, 0, // Skip to: 86948 -/* 34606 */ MCD_OPC_CheckField, 21, 1, 0, 111, 204, 0, // Skip to: 86948 -/* 34613 */ MCD_OPC_Decode, 226, 14, 167, 1, // Opcode: LD1Onev8h_POST -/* 34618 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 34640 -/* 34623 */ MCD_OPC_CheckPredicate, 3, 96, 204, 0, // Skip to: 86948 -/* 34628 */ MCD_OPC_CheckField, 21, 1, 0, 89, 204, 0, // Skip to: 86948 -/* 34635 */ MCD_OPC_Decode, 222, 14, 167, 1, // Opcode: LD1Onev4s_POST -/* 34640 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 34662 -/* 34645 */ MCD_OPC_CheckPredicate, 3, 74, 204, 0, // Skip to: 86948 -/* 34650 */ MCD_OPC_CheckField, 21, 1, 0, 67, 204, 0, // Skip to: 86948 -/* 34657 */ MCD_OPC_Decode, 216, 14, 167, 1, // Opcode: LD1Onev2d_POST -/* 34662 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 34684 -/* 34667 */ MCD_OPC_CheckPredicate, 3, 52, 204, 0, // Skip to: 86948 -/* 34672 */ MCD_OPC_CheckField, 21, 1, 0, 45, 204, 0, // Skip to: 86948 -/* 34679 */ MCD_OPC_Decode, 218, 15, 168, 1, // Opcode: LD2Twov16b_POST -/* 34684 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 34706 -/* 34689 */ MCD_OPC_CheckPredicate, 3, 30, 204, 0, // Skip to: 86948 -/* 34694 */ MCD_OPC_CheckField, 21, 1, 0, 23, 204, 0, // Skip to: 86948 -/* 34701 */ MCD_OPC_Decode, 230, 15, 168, 1, // Opcode: LD2Twov8h_POST -/* 34706 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 34728 -/* 34711 */ MCD_OPC_CheckPredicate, 3, 8, 204, 0, // Skip to: 86948 -/* 34716 */ MCD_OPC_CheckField, 21, 1, 0, 1, 204, 0, // Skip to: 86948 -/* 34723 */ MCD_OPC_Decode, 226, 15, 168, 1, // Opcode: LD2Twov4s_POST -/* 34728 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 34750 -/* 34733 */ MCD_OPC_CheckPredicate, 3, 242, 203, 0, // Skip to: 86948 -/* 34738 */ MCD_OPC_CheckField, 21, 1, 0, 235, 203, 0, // Skip to: 86948 -/* 34745 */ MCD_OPC_Decode, 220, 15, 168, 1, // Opcode: LD2Twov2d_POST -/* 34750 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 34772 -/* 34755 */ MCD_OPC_CheckPredicate, 3, 220, 203, 0, // Skip to: 86948 -/* 34760 */ MCD_OPC_CheckField, 21, 1, 0, 213, 203, 0, // Skip to: 86948 -/* 34767 */ MCD_OPC_Decode, 168, 15, 168, 1, // Opcode: LD1Twov16b_POST -/* 34772 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 34794 -/* 34777 */ MCD_OPC_CheckPredicate, 3, 198, 203, 0, // Skip to: 86948 -/* 34782 */ MCD_OPC_CheckField, 21, 1, 0, 191, 203, 0, // Skip to: 86948 -/* 34789 */ MCD_OPC_Decode, 182, 15, 168, 1, // Opcode: LD1Twov8h_POST -/* 34794 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 34816 -/* 34799 */ MCD_OPC_CheckPredicate, 3, 176, 203, 0, // Skip to: 86948 -/* 34804 */ MCD_OPC_CheckField, 21, 1, 0, 169, 203, 0, // Skip to: 86948 -/* 34811 */ MCD_OPC_Decode, 178, 15, 168, 1, // Opcode: LD1Twov4s_POST -/* 34816 */ MCD_OPC_FilterValue, 43, 159, 203, 0, // Skip to: 86948 -/* 34821 */ MCD_OPC_CheckPredicate, 3, 154, 203, 0, // Skip to: 86948 -/* 34826 */ MCD_OPC_CheckField, 21, 1, 0, 147, 203, 0, // Skip to: 86948 -/* 34833 */ MCD_OPC_Decode, 172, 15, 168, 1, // Opcode: LD1Twov2d_POST -/* 34838 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 34848 -/* 34843 */ MCD_OPC_Decode, 198, 17, 150, 1, // Opcode: LDPDpost -/* 34848 */ MCD_OPC_FilterValue, 5, 127, 203, 0, // Skip to: 86948 -/* 34853 */ MCD_OPC_Decode, 201, 17, 150, 1, // Opcode: LDPQpost -/* 34858 */ MCD_OPC_FilterValue, 4, 239, 1, 0, // Skip to: 35358 -/* 34863 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 34866 */ MCD_OPC_FilterValue, 0, 193, 1, 0, // Skip to: 35320 -/* 34871 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... -/* 34874 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 34896 -/* 34879 */ MCD_OPC_CheckPredicate, 3, 96, 203, 0, // Skip to: 86948 -/* 34884 */ MCD_OPC_CheckField, 31, 1, 0, 89, 203, 0, // Skip to: 86948 -/* 34891 */ MCD_OPC_Decode, 135, 28, 169, 1, // Opcode: ST1i8 -/* 34896 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 34918 -/* 34901 */ MCD_OPC_CheckPredicate, 3, 74, 203, 0, // Skip to: 86948 -/* 34906 */ MCD_OPC_CheckField, 31, 1, 0, 67, 203, 0, // Skip to: 86948 -/* 34913 */ MCD_OPC_Decode, 195, 28, 170, 1, // Opcode: ST3i8 -/* 34918 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 34947 -/* 34923 */ MCD_OPC_CheckPredicate, 3, 52, 203, 0, // Skip to: 86948 -/* 34928 */ MCD_OPC_CheckField, 31, 1, 0, 45, 203, 0, // Skip to: 86948 -/* 34935 */ MCD_OPC_CheckField, 10, 1, 0, 38, 203, 0, // Skip to: 86948 -/* 34942 */ MCD_OPC_Decode, 129, 28, 171, 1, // Opcode: ST1i16 -/* 34947 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 34976 -/* 34952 */ MCD_OPC_CheckPredicate, 3, 23, 203, 0, // Skip to: 86948 -/* 34957 */ MCD_OPC_CheckField, 31, 1, 0, 16, 203, 0, // Skip to: 86948 -/* 34964 */ MCD_OPC_CheckField, 10, 1, 0, 9, 203, 0, // Skip to: 86948 -/* 34971 */ MCD_OPC_Decode, 189, 28, 172, 1, // Opcode: ST3i16 -/* 34976 */ MCD_OPC_FilterValue, 4, 54, 0, 0, // Skip to: 35035 -/* 34981 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 34984 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35006 -/* 34989 */ MCD_OPC_CheckPredicate, 3, 242, 202, 0, // Skip to: 86948 -/* 34994 */ MCD_OPC_CheckField, 31, 1, 0, 235, 202, 0, // Skip to: 86948 -/* 35001 */ MCD_OPC_Decode, 131, 28, 173, 1, // Opcode: ST1i32 -/* 35006 */ MCD_OPC_FilterValue, 1, 225, 202, 0, // Skip to: 86948 -/* 35011 */ MCD_OPC_CheckPredicate, 3, 220, 202, 0, // Skip to: 86948 -/* 35016 */ MCD_OPC_CheckField, 31, 1, 0, 213, 202, 0, // Skip to: 86948 -/* 35023 */ MCD_OPC_CheckField, 12, 1, 0, 206, 202, 0, // Skip to: 86948 -/* 35030 */ MCD_OPC_Decode, 133, 28, 174, 1, // Opcode: ST1i64 -/* 35035 */ MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 35094 -/* 35040 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 35043 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35065 -/* 35048 */ MCD_OPC_CheckPredicate, 3, 183, 202, 0, // Skip to: 86948 -/* 35053 */ MCD_OPC_CheckField, 31, 1, 0, 176, 202, 0, // Skip to: 86948 -/* 35060 */ MCD_OPC_Decode, 191, 28, 175, 1, // Opcode: ST3i32 -/* 35065 */ MCD_OPC_FilterValue, 1, 166, 202, 0, // Skip to: 86948 -/* 35070 */ MCD_OPC_CheckPredicate, 3, 161, 202, 0, // Skip to: 86948 -/* 35075 */ MCD_OPC_CheckField, 31, 1, 0, 154, 202, 0, // Skip to: 86948 -/* 35082 */ MCD_OPC_CheckField, 12, 1, 0, 147, 202, 0, // Skip to: 86948 -/* 35089 */ MCD_OPC_Decode, 193, 28, 176, 1, // Opcode: ST3i64 -/* 35094 */ MCD_OPC_FilterValue, 128, 2, 17, 0, 0, // Skip to: 35117 -/* 35100 */ MCD_OPC_CheckPredicate, 3, 131, 202, 0, // Skip to: 86948 -/* 35105 */ MCD_OPC_CheckField, 31, 1, 0, 124, 202, 0, // Skip to: 86948 -/* 35112 */ MCD_OPC_Decode, 165, 28, 177, 1, // Opcode: ST2i8 -/* 35117 */ MCD_OPC_FilterValue, 129, 2, 17, 0, 0, // Skip to: 35140 -/* 35123 */ MCD_OPC_CheckPredicate, 3, 108, 202, 0, // Skip to: 86948 -/* 35128 */ MCD_OPC_CheckField, 31, 1, 0, 101, 202, 0, // Skip to: 86948 -/* 35135 */ MCD_OPC_Decode, 225, 28, 178, 1, // Opcode: ST4i8 -/* 35140 */ MCD_OPC_FilterValue, 130, 2, 24, 0, 0, // Skip to: 35170 -/* 35146 */ MCD_OPC_CheckPredicate, 3, 85, 202, 0, // Skip to: 86948 -/* 35151 */ MCD_OPC_CheckField, 31, 1, 0, 78, 202, 0, // Skip to: 86948 -/* 35158 */ MCD_OPC_CheckField, 10, 1, 0, 71, 202, 0, // Skip to: 86948 -/* 35165 */ MCD_OPC_Decode, 159, 28, 179, 1, // Opcode: ST2i16 -/* 35170 */ MCD_OPC_FilterValue, 131, 2, 24, 0, 0, // Skip to: 35200 -/* 35176 */ MCD_OPC_CheckPredicate, 3, 55, 202, 0, // Skip to: 86948 -/* 35181 */ MCD_OPC_CheckField, 31, 1, 0, 48, 202, 0, // Skip to: 86948 -/* 35188 */ MCD_OPC_CheckField, 10, 1, 0, 41, 202, 0, // Skip to: 86948 -/* 35195 */ MCD_OPC_Decode, 219, 28, 180, 1, // Opcode: ST4i16 -/* 35200 */ MCD_OPC_FilterValue, 132, 2, 54, 0, 0, // Skip to: 35260 -/* 35206 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 35209 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35231 -/* 35214 */ MCD_OPC_CheckPredicate, 3, 17, 202, 0, // Skip to: 86948 -/* 35219 */ MCD_OPC_CheckField, 31, 1, 0, 10, 202, 0, // Skip to: 86948 -/* 35226 */ MCD_OPC_Decode, 161, 28, 181, 1, // Opcode: ST2i32 -/* 35231 */ MCD_OPC_FilterValue, 1, 0, 202, 0, // Skip to: 86948 -/* 35236 */ MCD_OPC_CheckPredicate, 3, 251, 201, 0, // Skip to: 86948 -/* 35241 */ MCD_OPC_CheckField, 31, 1, 0, 244, 201, 0, // Skip to: 86948 -/* 35248 */ MCD_OPC_CheckField, 12, 1, 0, 237, 201, 0, // Skip to: 86948 -/* 35255 */ MCD_OPC_Decode, 163, 28, 182, 1, // Opcode: ST2i64 -/* 35260 */ MCD_OPC_FilterValue, 133, 2, 226, 201, 0, // Skip to: 86948 -/* 35266 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 35269 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35291 -/* 35274 */ MCD_OPC_CheckPredicate, 3, 213, 201, 0, // Skip to: 86948 -/* 35279 */ MCD_OPC_CheckField, 31, 1, 0, 206, 201, 0, // Skip to: 86948 -/* 35286 */ MCD_OPC_Decode, 221, 28, 183, 1, // Opcode: ST4i32 -/* 35291 */ MCD_OPC_FilterValue, 1, 196, 201, 0, // Skip to: 86948 -/* 35296 */ MCD_OPC_CheckPredicate, 3, 191, 201, 0, // Skip to: 86948 -/* 35301 */ MCD_OPC_CheckField, 31, 1, 0, 184, 201, 0, // Skip to: 86948 -/* 35308 */ MCD_OPC_CheckField, 12, 1, 0, 177, 201, 0, // Skip to: 86948 -/* 35315 */ MCD_OPC_Decode, 223, 28, 184, 1, // Opcode: ST4i64 -/* 35320 */ MCD_OPC_FilterValue, 1, 167, 201, 0, // Skip to: 86948 -/* 35325 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 35328 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 35338 -/* 35333 */ MCD_OPC_Decode, 136, 29, 150, 1, // Opcode: STPSi -/* 35338 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 35348 -/* 35343 */ MCD_OPC_Decode, 130, 29, 150, 1, // Opcode: STPDi -/* 35348 */ MCD_OPC_FilterValue, 2, 139, 201, 0, // Skip to: 86948 -/* 35353 */ MCD_OPC_Decode, 133, 29, 150, 1, // Opcode: STPQi -/* 35358 */ MCD_OPC_FilterValue, 5, 113, 4, 0, // Skip to: 36500 -/* 35363 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 35366 */ MCD_OPC_FilterValue, 0, 67, 4, 0, // Skip to: 36462 -/* 35371 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... -/* 35374 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35396 -/* 35379 */ MCD_OPC_CheckPredicate, 3, 108, 201, 0, // Skip to: 86948 -/* 35384 */ MCD_OPC_CheckField, 31, 1, 0, 101, 201, 0, // Skip to: 86948 -/* 35391 */ MCD_OPC_Decode, 193, 15, 185, 1, // Opcode: LD1i8 -/* 35396 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 35418 -/* 35401 */ MCD_OPC_CheckPredicate, 3, 86, 201, 0, // Skip to: 86948 -/* 35406 */ MCD_OPC_CheckField, 31, 1, 0, 79, 201, 0, // Skip to: 86948 -/* 35413 */ MCD_OPC_Decode, 157, 16, 186, 1, // Opcode: LD3i8 -/* 35418 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 35447 -/* 35423 */ MCD_OPC_CheckPredicate, 3, 64, 201, 0, // Skip to: 86948 -/* 35428 */ MCD_OPC_CheckField, 31, 1, 0, 57, 201, 0, // Skip to: 86948 -/* 35435 */ MCD_OPC_CheckField, 10, 1, 0, 50, 201, 0, // Skip to: 86948 -/* 35442 */ MCD_OPC_Decode, 187, 15, 187, 1, // Opcode: LD1i16 -/* 35447 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 35476 -/* 35452 */ MCD_OPC_CheckPredicate, 3, 35, 201, 0, // Skip to: 86948 -/* 35457 */ MCD_OPC_CheckField, 31, 1, 0, 28, 201, 0, // Skip to: 86948 -/* 35464 */ MCD_OPC_CheckField, 10, 1, 0, 21, 201, 0, // Skip to: 86948 -/* 35471 */ MCD_OPC_Decode, 151, 16, 188, 1, // Opcode: LD3i16 -/* 35476 */ MCD_OPC_FilterValue, 4, 54, 0, 0, // Skip to: 35535 -/* 35481 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 35484 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35506 -/* 35489 */ MCD_OPC_CheckPredicate, 3, 254, 200, 0, // Skip to: 86948 -/* 35494 */ MCD_OPC_CheckField, 31, 1, 0, 247, 200, 0, // Skip to: 86948 -/* 35501 */ MCD_OPC_Decode, 189, 15, 189, 1, // Opcode: LD1i32 -/* 35506 */ MCD_OPC_FilterValue, 1, 237, 200, 0, // Skip to: 86948 -/* 35511 */ MCD_OPC_CheckPredicate, 3, 232, 200, 0, // Skip to: 86948 -/* 35516 */ MCD_OPC_CheckField, 31, 1, 0, 225, 200, 0, // Skip to: 86948 -/* 35523 */ MCD_OPC_CheckField, 12, 1, 0, 218, 200, 0, // Skip to: 86948 -/* 35530 */ MCD_OPC_Decode, 191, 15, 190, 1, // Opcode: LD1i64 -/* 35535 */ MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 35594 -/* 35540 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 35543 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35565 -/* 35548 */ MCD_OPC_CheckPredicate, 3, 195, 200, 0, // Skip to: 86948 -/* 35553 */ MCD_OPC_CheckField, 31, 1, 0, 188, 200, 0, // Skip to: 86948 -/* 35560 */ MCD_OPC_Decode, 153, 16, 191, 1, // Opcode: LD3i32 -/* 35565 */ MCD_OPC_FilterValue, 1, 178, 200, 0, // Skip to: 86948 -/* 35570 */ MCD_OPC_CheckPredicate, 3, 173, 200, 0, // Skip to: 86948 -/* 35575 */ MCD_OPC_CheckField, 31, 1, 0, 166, 200, 0, // Skip to: 86948 -/* 35582 */ MCD_OPC_CheckField, 12, 1, 0, 159, 200, 0, // Skip to: 86948 -/* 35589 */ MCD_OPC_Decode, 155, 16, 192, 1, // Opcode: LD3i64 -/* 35594 */ MCD_OPC_FilterValue, 6, 155, 0, 0, // Skip to: 35754 -/* 35599 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 35602 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 35640 -/* 35607 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 35610 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35625 -/* 35615 */ MCD_OPC_CheckPredicate, 3, 128, 200, 0, // Skip to: 86948 -/* 35620 */ MCD_OPC_Decode, 135, 15, 155, 1, // Opcode: LD1Rv8b -/* 35625 */ MCD_OPC_FilterValue, 1, 118, 200, 0, // Skip to: 86948 -/* 35630 */ MCD_OPC_CheckPredicate, 3, 113, 200, 0, // Skip to: 86948 -/* 35635 */ MCD_OPC_Decode, 251, 14, 159, 1, // Opcode: LD1Rv16b -/* 35640 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 35678 -/* 35645 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 35648 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35663 -/* 35653 */ MCD_OPC_CheckPredicate, 3, 90, 200, 0, // Skip to: 86948 -/* 35658 */ MCD_OPC_Decode, 131, 15, 155, 1, // Opcode: LD1Rv4h -/* 35663 */ MCD_OPC_FilterValue, 1, 80, 200, 0, // Skip to: 86948 -/* 35668 */ MCD_OPC_CheckPredicate, 3, 75, 200, 0, // Skip to: 86948 -/* 35673 */ MCD_OPC_Decode, 137, 15, 159, 1, // Opcode: LD1Rv8h -/* 35678 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 35716 -/* 35683 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 35686 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35701 -/* 35691 */ MCD_OPC_CheckPredicate, 3, 52, 200, 0, // Skip to: 86948 -/* 35696 */ MCD_OPC_Decode, 129, 15, 155, 1, // Opcode: LD1Rv2s -/* 35701 */ MCD_OPC_FilterValue, 1, 42, 200, 0, // Skip to: 86948 -/* 35706 */ MCD_OPC_CheckPredicate, 3, 37, 200, 0, // Skip to: 86948 -/* 35711 */ MCD_OPC_Decode, 133, 15, 159, 1, // Opcode: LD1Rv4s -/* 35716 */ MCD_OPC_FilterValue, 3, 27, 200, 0, // Skip to: 86948 -/* 35721 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 35724 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35739 -/* 35729 */ MCD_OPC_CheckPredicate, 3, 14, 200, 0, // Skip to: 86948 -/* 35734 */ MCD_OPC_Decode, 253, 14, 155, 1, // Opcode: LD1Rv1d -/* 35739 */ MCD_OPC_FilterValue, 1, 4, 200, 0, // Skip to: 86948 -/* 35744 */ MCD_OPC_CheckPredicate, 3, 255, 199, 0, // Skip to: 86948 -/* 35749 */ MCD_OPC_Decode, 255, 14, 159, 1, // Opcode: LD1Rv2d -/* 35754 */ MCD_OPC_FilterValue, 7, 155, 0, 0, // Skip to: 35914 -/* 35759 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 35762 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 35800 -/* 35767 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 35770 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35785 -/* 35775 */ MCD_OPC_CheckPredicate, 3, 224, 199, 0, // Skip to: 86948 -/* 35780 */ MCD_OPC_Decode, 131, 16, 154, 1, // Opcode: LD3Rv8b -/* 35785 */ MCD_OPC_FilterValue, 1, 214, 199, 0, // Skip to: 86948 -/* 35790 */ MCD_OPC_CheckPredicate, 3, 209, 199, 0, // Skip to: 86948 -/* 35795 */ MCD_OPC_Decode, 247, 15, 158, 1, // Opcode: LD3Rv16b -/* 35800 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 35838 -/* 35805 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 35808 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35823 -/* 35813 */ MCD_OPC_CheckPredicate, 3, 186, 199, 0, // Skip to: 86948 -/* 35818 */ MCD_OPC_Decode, 255, 15, 154, 1, // Opcode: LD3Rv4h -/* 35823 */ MCD_OPC_FilterValue, 1, 176, 199, 0, // Skip to: 86948 -/* 35828 */ MCD_OPC_CheckPredicate, 3, 171, 199, 0, // Skip to: 86948 -/* 35833 */ MCD_OPC_Decode, 133, 16, 158, 1, // Opcode: LD3Rv8h -/* 35838 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 35876 -/* 35843 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 35846 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35861 -/* 35851 */ MCD_OPC_CheckPredicate, 3, 148, 199, 0, // Skip to: 86948 -/* 35856 */ MCD_OPC_Decode, 253, 15, 154, 1, // Opcode: LD3Rv2s -/* 35861 */ MCD_OPC_FilterValue, 1, 138, 199, 0, // Skip to: 86948 -/* 35866 */ MCD_OPC_CheckPredicate, 3, 133, 199, 0, // Skip to: 86948 -/* 35871 */ MCD_OPC_Decode, 129, 16, 158, 1, // Opcode: LD3Rv4s -/* 35876 */ MCD_OPC_FilterValue, 3, 123, 199, 0, // Skip to: 86948 -/* 35881 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 35884 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35899 -/* 35889 */ MCD_OPC_CheckPredicate, 3, 110, 199, 0, // Skip to: 86948 -/* 35894 */ MCD_OPC_Decode, 249, 15, 154, 1, // Opcode: LD3Rv1d -/* 35899 */ MCD_OPC_FilterValue, 1, 100, 199, 0, // Skip to: 86948 -/* 35904 */ MCD_OPC_CheckPredicate, 3, 95, 199, 0, // Skip to: 86948 -/* 35909 */ MCD_OPC_Decode, 251, 15, 158, 1, // Opcode: LD3Rv2d -/* 35914 */ MCD_OPC_FilterValue, 128, 2, 17, 0, 0, // Skip to: 35937 -/* 35920 */ MCD_OPC_CheckPredicate, 3, 79, 199, 0, // Skip to: 86948 -/* 35925 */ MCD_OPC_CheckField, 31, 1, 0, 72, 199, 0, // Skip to: 86948 -/* 35932 */ MCD_OPC_Decode, 239, 15, 193, 1, // Opcode: LD2i8 -/* 35937 */ MCD_OPC_FilterValue, 129, 2, 17, 0, 0, // Skip to: 35960 -/* 35943 */ MCD_OPC_CheckPredicate, 3, 56, 199, 0, // Skip to: 86948 -/* 35948 */ MCD_OPC_CheckField, 31, 1, 0, 49, 199, 0, // Skip to: 86948 -/* 35955 */ MCD_OPC_Decode, 203, 16, 194, 1, // Opcode: LD4i8 -/* 35960 */ MCD_OPC_FilterValue, 130, 2, 24, 0, 0, // Skip to: 35990 -/* 35966 */ MCD_OPC_CheckPredicate, 3, 33, 199, 0, // Skip to: 86948 -/* 35971 */ MCD_OPC_CheckField, 31, 1, 0, 26, 199, 0, // Skip to: 86948 -/* 35978 */ MCD_OPC_CheckField, 10, 1, 0, 19, 199, 0, // Skip to: 86948 -/* 35985 */ MCD_OPC_Decode, 233, 15, 195, 1, // Opcode: LD2i16 -/* 35990 */ MCD_OPC_FilterValue, 131, 2, 24, 0, 0, // Skip to: 36020 -/* 35996 */ MCD_OPC_CheckPredicate, 3, 3, 199, 0, // Skip to: 86948 -/* 36001 */ MCD_OPC_CheckField, 31, 1, 0, 252, 198, 0, // Skip to: 86948 -/* 36008 */ MCD_OPC_CheckField, 10, 1, 0, 245, 198, 0, // Skip to: 86948 -/* 36015 */ MCD_OPC_Decode, 197, 16, 196, 1, // Opcode: LD4i16 -/* 36020 */ MCD_OPC_FilterValue, 132, 2, 54, 0, 0, // Skip to: 36080 -/* 36026 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 36029 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36051 -/* 36034 */ MCD_OPC_CheckPredicate, 3, 221, 198, 0, // Skip to: 86948 -/* 36039 */ MCD_OPC_CheckField, 31, 1, 0, 214, 198, 0, // Skip to: 86948 -/* 36046 */ MCD_OPC_Decode, 235, 15, 197, 1, // Opcode: LD2i32 -/* 36051 */ MCD_OPC_FilterValue, 1, 204, 198, 0, // Skip to: 86948 -/* 36056 */ MCD_OPC_CheckPredicate, 3, 199, 198, 0, // Skip to: 86948 -/* 36061 */ MCD_OPC_CheckField, 31, 1, 0, 192, 198, 0, // Skip to: 86948 -/* 36068 */ MCD_OPC_CheckField, 12, 1, 0, 185, 198, 0, // Skip to: 86948 -/* 36075 */ MCD_OPC_Decode, 237, 15, 198, 1, // Opcode: LD2i64 -/* 36080 */ MCD_OPC_FilterValue, 133, 2, 54, 0, 0, // Skip to: 36140 -/* 36086 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 36089 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36111 -/* 36094 */ MCD_OPC_CheckPredicate, 3, 161, 198, 0, // Skip to: 86948 -/* 36099 */ MCD_OPC_CheckField, 31, 1, 0, 154, 198, 0, // Skip to: 86948 -/* 36106 */ MCD_OPC_Decode, 199, 16, 199, 1, // Opcode: LD4i32 -/* 36111 */ MCD_OPC_FilterValue, 1, 144, 198, 0, // Skip to: 86948 -/* 36116 */ MCD_OPC_CheckPredicate, 3, 139, 198, 0, // Skip to: 86948 -/* 36121 */ MCD_OPC_CheckField, 31, 1, 0, 132, 198, 0, // Skip to: 86948 -/* 36128 */ MCD_OPC_CheckField, 12, 1, 0, 125, 198, 0, // Skip to: 86948 -/* 36135 */ MCD_OPC_Decode, 201, 16, 200, 1, // Opcode: LD4i64 -/* 36140 */ MCD_OPC_FilterValue, 134, 2, 155, 0, 0, // Skip to: 36301 -/* 36146 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 36149 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 36187 -/* 36154 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 36157 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36172 -/* 36162 */ MCD_OPC_CheckPredicate, 3, 93, 198, 0, // Skip to: 86948 -/* 36167 */ MCD_OPC_Decode, 213, 15, 156, 1, // Opcode: LD2Rv8b -/* 36172 */ MCD_OPC_FilterValue, 1, 83, 198, 0, // Skip to: 86948 -/* 36177 */ MCD_OPC_CheckPredicate, 3, 78, 198, 0, // Skip to: 86948 -/* 36182 */ MCD_OPC_Decode, 201, 15, 160, 1, // Opcode: LD2Rv16b -/* 36187 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 36225 -/* 36192 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 36195 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36210 -/* 36200 */ MCD_OPC_CheckPredicate, 3, 55, 198, 0, // Skip to: 86948 -/* 36205 */ MCD_OPC_Decode, 209, 15, 156, 1, // Opcode: LD2Rv4h -/* 36210 */ MCD_OPC_FilterValue, 1, 45, 198, 0, // Skip to: 86948 -/* 36215 */ MCD_OPC_CheckPredicate, 3, 40, 198, 0, // Skip to: 86948 -/* 36220 */ MCD_OPC_Decode, 215, 15, 160, 1, // Opcode: LD2Rv8h -/* 36225 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 36263 -/* 36230 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 36233 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36248 -/* 36238 */ MCD_OPC_CheckPredicate, 3, 17, 198, 0, // Skip to: 86948 -/* 36243 */ MCD_OPC_Decode, 207, 15, 156, 1, // Opcode: LD2Rv2s -/* 36248 */ MCD_OPC_FilterValue, 1, 7, 198, 0, // Skip to: 86948 -/* 36253 */ MCD_OPC_CheckPredicate, 3, 2, 198, 0, // Skip to: 86948 -/* 36258 */ MCD_OPC_Decode, 211, 15, 160, 1, // Opcode: LD2Rv4s -/* 36263 */ MCD_OPC_FilterValue, 3, 248, 197, 0, // Skip to: 86948 -/* 36268 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 36271 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36286 -/* 36276 */ MCD_OPC_CheckPredicate, 3, 235, 197, 0, // Skip to: 86948 -/* 36281 */ MCD_OPC_Decode, 203, 15, 156, 1, // Opcode: LD2Rv1d -/* 36286 */ MCD_OPC_FilterValue, 1, 225, 197, 0, // Skip to: 86948 -/* 36291 */ MCD_OPC_CheckPredicate, 3, 220, 197, 0, // Skip to: 86948 -/* 36296 */ MCD_OPC_Decode, 205, 15, 160, 1, // Opcode: LD2Rv2d -/* 36301 */ MCD_OPC_FilterValue, 135, 2, 209, 197, 0, // Skip to: 86948 -/* 36307 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 36310 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 36348 -/* 36315 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 36318 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36333 -/* 36323 */ MCD_OPC_CheckPredicate, 3, 188, 197, 0, // Skip to: 86948 -/* 36328 */ MCD_OPC_Decode, 191, 16, 153, 1, // Opcode: LD4Rv8b -/* 36333 */ MCD_OPC_FilterValue, 1, 178, 197, 0, // Skip to: 86948 -/* 36338 */ MCD_OPC_CheckPredicate, 3, 173, 197, 0, // Skip to: 86948 -/* 36343 */ MCD_OPC_Decode, 179, 16, 157, 1, // Opcode: LD4Rv16b -/* 36348 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 36386 -/* 36353 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 36356 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36371 -/* 36361 */ MCD_OPC_CheckPredicate, 3, 150, 197, 0, // Skip to: 86948 -/* 36366 */ MCD_OPC_Decode, 187, 16, 153, 1, // Opcode: LD4Rv4h -/* 36371 */ MCD_OPC_FilterValue, 1, 140, 197, 0, // Skip to: 86948 -/* 36376 */ MCD_OPC_CheckPredicate, 3, 135, 197, 0, // Skip to: 86948 -/* 36381 */ MCD_OPC_Decode, 193, 16, 157, 1, // Opcode: LD4Rv8h -/* 36386 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 36424 -/* 36391 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 36394 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36409 -/* 36399 */ MCD_OPC_CheckPredicate, 3, 112, 197, 0, // Skip to: 86948 -/* 36404 */ MCD_OPC_Decode, 185, 16, 153, 1, // Opcode: LD4Rv2s -/* 36409 */ MCD_OPC_FilterValue, 1, 102, 197, 0, // Skip to: 86948 -/* 36414 */ MCD_OPC_CheckPredicate, 3, 97, 197, 0, // Skip to: 86948 -/* 36419 */ MCD_OPC_Decode, 189, 16, 157, 1, // Opcode: LD4Rv4s -/* 36424 */ MCD_OPC_FilterValue, 3, 87, 197, 0, // Skip to: 86948 -/* 36429 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 36432 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36447 -/* 36437 */ MCD_OPC_CheckPredicate, 3, 74, 197, 0, // Skip to: 86948 -/* 36442 */ MCD_OPC_Decode, 181, 16, 153, 1, // Opcode: LD4Rv1d -/* 36447 */ MCD_OPC_FilterValue, 1, 64, 197, 0, // Skip to: 86948 -/* 36452 */ MCD_OPC_CheckPredicate, 3, 59, 197, 0, // Skip to: 86948 -/* 36457 */ MCD_OPC_Decode, 183, 16, 157, 1, // Opcode: LD4Rv2d -/* 36462 */ MCD_OPC_FilterValue, 1, 49, 197, 0, // Skip to: 86948 -/* 36467 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 36470 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 36480 -/* 36475 */ MCD_OPC_Decode, 206, 17, 150, 1, // Opcode: LDPSi -/* 36480 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 36490 -/* 36485 */ MCD_OPC_Decode, 197, 17, 150, 1, // Opcode: LDPDi -/* 36490 */ MCD_OPC_FilterValue, 2, 21, 197, 0, // Skip to: 86948 -/* 36495 */ MCD_OPC_Decode, 200, 17, 150, 1, // Opcode: LDPQi -/* 36500 */ MCD_OPC_FilterValue, 6, 25, 2, 0, // Skip to: 37042 -/* 36505 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 36508 */ MCD_OPC_FilterValue, 0, 235, 1, 0, // Skip to: 37004 -/* 36513 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 36516 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 36568 -/* 36521 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36524 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36546 -/* 36529 */ MCD_OPC_CheckPredicate, 3, 238, 196, 0, // Skip to: 86948 -/* 36534 */ MCD_OPC_CheckField, 31, 1, 0, 231, 196, 0, // Skip to: 86948 -/* 36541 */ MCD_OPC_Decode, 136, 28, 201, 1, // Opcode: ST1i8_POST -/* 36546 */ MCD_OPC_FilterValue, 1, 221, 196, 0, // Skip to: 86948 -/* 36551 */ MCD_OPC_CheckPredicate, 3, 216, 196, 0, // Skip to: 86948 -/* 36556 */ MCD_OPC_CheckField, 31, 1, 0, 209, 196, 0, // Skip to: 86948 -/* 36563 */ MCD_OPC_Decode, 166, 28, 202, 1, // Opcode: ST2i8_POST -/* 36568 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 36620 -/* 36573 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36576 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36598 -/* 36581 */ MCD_OPC_CheckPredicate, 3, 186, 196, 0, // Skip to: 86948 -/* 36586 */ MCD_OPC_CheckField, 31, 1, 0, 179, 196, 0, // Skip to: 86948 -/* 36593 */ MCD_OPC_Decode, 196, 28, 203, 1, // Opcode: ST3i8_POST -/* 36598 */ MCD_OPC_FilterValue, 1, 169, 196, 0, // Skip to: 86948 -/* 36603 */ MCD_OPC_CheckPredicate, 3, 164, 196, 0, // Skip to: 86948 -/* 36608 */ MCD_OPC_CheckField, 31, 1, 0, 157, 196, 0, // Skip to: 86948 -/* 36615 */ MCD_OPC_Decode, 226, 28, 204, 1, // Opcode: ST4i8_POST -/* 36620 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 36686 -/* 36625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36628 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36657 -/* 36633 */ MCD_OPC_CheckPredicate, 3, 134, 196, 0, // Skip to: 86948 -/* 36638 */ MCD_OPC_CheckField, 31, 1, 0, 127, 196, 0, // Skip to: 86948 -/* 36645 */ MCD_OPC_CheckField, 10, 1, 0, 120, 196, 0, // Skip to: 86948 -/* 36652 */ MCD_OPC_Decode, 130, 28, 205, 1, // Opcode: ST1i16_POST -/* 36657 */ MCD_OPC_FilterValue, 1, 110, 196, 0, // Skip to: 86948 -/* 36662 */ MCD_OPC_CheckPredicate, 3, 105, 196, 0, // Skip to: 86948 -/* 36667 */ MCD_OPC_CheckField, 31, 1, 0, 98, 196, 0, // Skip to: 86948 -/* 36674 */ MCD_OPC_CheckField, 10, 1, 0, 91, 196, 0, // Skip to: 86948 -/* 36681 */ MCD_OPC_Decode, 160, 28, 206, 1, // Opcode: ST2i16_POST -/* 36686 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 36752 -/* 36691 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36694 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36723 -/* 36699 */ MCD_OPC_CheckPredicate, 3, 68, 196, 0, // Skip to: 86948 -/* 36704 */ MCD_OPC_CheckField, 31, 1, 0, 61, 196, 0, // Skip to: 86948 -/* 36711 */ MCD_OPC_CheckField, 10, 1, 0, 54, 196, 0, // Skip to: 86948 -/* 36718 */ MCD_OPC_Decode, 190, 28, 207, 1, // Opcode: ST3i16_POST -/* 36723 */ MCD_OPC_FilterValue, 1, 44, 196, 0, // Skip to: 86948 -/* 36728 */ MCD_OPC_CheckPredicate, 3, 39, 196, 0, // Skip to: 86948 -/* 36733 */ MCD_OPC_CheckField, 31, 1, 0, 32, 196, 0, // Skip to: 86948 -/* 36740 */ MCD_OPC_CheckField, 10, 1, 0, 25, 196, 0, // Skip to: 86948 -/* 36747 */ MCD_OPC_Decode, 220, 28, 208, 1, // Opcode: ST4i16_POST -/* 36752 */ MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 36878 -/* 36757 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 36760 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 36812 -/* 36765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36768 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36790 -/* 36773 */ MCD_OPC_CheckPredicate, 3, 250, 195, 0, // Skip to: 86948 -/* 36778 */ MCD_OPC_CheckField, 31, 1, 0, 243, 195, 0, // Skip to: 86948 -/* 36785 */ MCD_OPC_Decode, 132, 28, 209, 1, // Opcode: ST1i32_POST -/* 36790 */ MCD_OPC_FilterValue, 1, 233, 195, 0, // Skip to: 86948 -/* 36795 */ MCD_OPC_CheckPredicate, 3, 228, 195, 0, // Skip to: 86948 -/* 36800 */ MCD_OPC_CheckField, 31, 1, 0, 221, 195, 0, // Skip to: 86948 -/* 36807 */ MCD_OPC_Decode, 162, 28, 210, 1, // Opcode: ST2i32_POST -/* 36812 */ MCD_OPC_FilterValue, 1, 211, 195, 0, // Skip to: 86948 -/* 36817 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36820 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36849 -/* 36825 */ MCD_OPC_CheckPredicate, 3, 198, 195, 0, // Skip to: 86948 -/* 36830 */ MCD_OPC_CheckField, 31, 1, 0, 191, 195, 0, // Skip to: 86948 -/* 36837 */ MCD_OPC_CheckField, 12, 1, 0, 184, 195, 0, // Skip to: 86948 -/* 36844 */ MCD_OPC_Decode, 134, 28, 211, 1, // Opcode: ST1i64_POST -/* 36849 */ MCD_OPC_FilterValue, 1, 174, 195, 0, // Skip to: 86948 -/* 36854 */ MCD_OPC_CheckPredicate, 3, 169, 195, 0, // Skip to: 86948 -/* 36859 */ MCD_OPC_CheckField, 31, 1, 0, 162, 195, 0, // Skip to: 86948 -/* 36866 */ MCD_OPC_CheckField, 12, 1, 0, 155, 195, 0, // Skip to: 86948 -/* 36873 */ MCD_OPC_Decode, 164, 28, 212, 1, // Opcode: ST2i64_POST -/* 36878 */ MCD_OPC_FilterValue, 5, 145, 195, 0, // Skip to: 86948 -/* 36883 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 36886 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 36938 -/* 36891 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36894 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36916 -/* 36899 */ MCD_OPC_CheckPredicate, 3, 124, 195, 0, // Skip to: 86948 -/* 36904 */ MCD_OPC_CheckField, 31, 1, 0, 117, 195, 0, // Skip to: 86948 -/* 36911 */ MCD_OPC_Decode, 192, 28, 213, 1, // Opcode: ST3i32_POST -/* 36916 */ MCD_OPC_FilterValue, 1, 107, 195, 0, // Skip to: 86948 -/* 36921 */ MCD_OPC_CheckPredicate, 3, 102, 195, 0, // Skip to: 86948 -/* 36926 */ MCD_OPC_CheckField, 31, 1, 0, 95, 195, 0, // Skip to: 86948 -/* 36933 */ MCD_OPC_Decode, 222, 28, 214, 1, // Opcode: ST4i32_POST -/* 36938 */ MCD_OPC_FilterValue, 1, 85, 195, 0, // Skip to: 86948 -/* 36943 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36946 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36975 -/* 36951 */ MCD_OPC_CheckPredicate, 3, 72, 195, 0, // Skip to: 86948 -/* 36956 */ MCD_OPC_CheckField, 31, 1, 0, 65, 195, 0, // Skip to: 86948 -/* 36963 */ MCD_OPC_CheckField, 12, 1, 0, 58, 195, 0, // Skip to: 86948 -/* 36970 */ MCD_OPC_Decode, 194, 28, 215, 1, // Opcode: ST3i64_POST -/* 36975 */ MCD_OPC_FilterValue, 1, 48, 195, 0, // Skip to: 86948 -/* 36980 */ MCD_OPC_CheckPredicate, 3, 43, 195, 0, // Skip to: 86948 -/* 36985 */ MCD_OPC_CheckField, 31, 1, 0, 36, 195, 0, // Skip to: 86948 -/* 36992 */ MCD_OPC_CheckField, 12, 1, 0, 29, 195, 0, // Skip to: 86948 -/* 36999 */ MCD_OPC_Decode, 224, 28, 216, 1, // Opcode: ST4i64_POST -/* 37004 */ MCD_OPC_FilterValue, 1, 19, 195, 0, // Skip to: 86948 -/* 37009 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37012 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 37022 -/* 37017 */ MCD_OPC_Decode, 138, 29, 150, 1, // Opcode: STPSpre -/* 37022 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 37032 -/* 37027 */ MCD_OPC_Decode, 132, 29, 150, 1, // Opcode: STPDpre -/* 37032 */ MCD_OPC_FilterValue, 2, 247, 194, 0, // Skip to: 86948 -/* 37037 */ MCD_OPC_Decode, 135, 29, 150, 1, // Opcode: STPQpre -/* 37042 */ MCD_OPC_FilterValue, 7, 201, 4, 0, // Skip to: 38272 -/* 37047 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 37050 */ MCD_OPC_FilterValue, 0, 155, 4, 0, // Skip to: 38234 -/* 37055 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 37058 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 37110 -/* 37063 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37066 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37088 -/* 37071 */ MCD_OPC_CheckPredicate, 3, 208, 194, 0, // Skip to: 86948 -/* 37076 */ MCD_OPC_CheckField, 31, 1, 0, 201, 194, 0, // Skip to: 86948 -/* 37083 */ MCD_OPC_Decode, 194, 15, 217, 1, // Opcode: LD1i8_POST -/* 37088 */ MCD_OPC_FilterValue, 1, 191, 194, 0, // Skip to: 86948 -/* 37093 */ MCD_OPC_CheckPredicate, 3, 186, 194, 0, // Skip to: 86948 -/* 37098 */ MCD_OPC_CheckField, 31, 1, 0, 179, 194, 0, // Skip to: 86948 -/* 37105 */ MCD_OPC_Decode, 240, 15, 218, 1, // Opcode: LD2i8_POST -/* 37110 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 37162 -/* 37115 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37118 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37140 -/* 37123 */ MCD_OPC_CheckPredicate, 3, 156, 194, 0, // Skip to: 86948 -/* 37128 */ MCD_OPC_CheckField, 31, 1, 0, 149, 194, 0, // Skip to: 86948 -/* 37135 */ MCD_OPC_Decode, 158, 16, 219, 1, // Opcode: LD3i8_POST -/* 37140 */ MCD_OPC_FilterValue, 1, 139, 194, 0, // Skip to: 86948 -/* 37145 */ MCD_OPC_CheckPredicate, 3, 134, 194, 0, // Skip to: 86948 -/* 37150 */ MCD_OPC_CheckField, 31, 1, 0, 127, 194, 0, // Skip to: 86948 -/* 37157 */ MCD_OPC_Decode, 204, 16, 220, 1, // Opcode: LD4i8_POST -/* 37162 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 37228 -/* 37167 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37170 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37199 -/* 37175 */ MCD_OPC_CheckPredicate, 3, 104, 194, 0, // Skip to: 86948 -/* 37180 */ MCD_OPC_CheckField, 31, 1, 0, 97, 194, 0, // Skip to: 86948 -/* 37187 */ MCD_OPC_CheckField, 10, 1, 0, 90, 194, 0, // Skip to: 86948 -/* 37194 */ MCD_OPC_Decode, 188, 15, 221, 1, // Opcode: LD1i16_POST -/* 37199 */ MCD_OPC_FilterValue, 1, 80, 194, 0, // Skip to: 86948 -/* 37204 */ MCD_OPC_CheckPredicate, 3, 75, 194, 0, // Skip to: 86948 -/* 37209 */ MCD_OPC_CheckField, 31, 1, 0, 68, 194, 0, // Skip to: 86948 -/* 37216 */ MCD_OPC_CheckField, 10, 1, 0, 61, 194, 0, // Skip to: 86948 -/* 37223 */ MCD_OPC_Decode, 234, 15, 222, 1, // Opcode: LD2i16_POST -/* 37228 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 37294 -/* 37233 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37236 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37265 -/* 37241 */ MCD_OPC_CheckPredicate, 3, 38, 194, 0, // Skip to: 86948 -/* 37246 */ MCD_OPC_CheckField, 31, 1, 0, 31, 194, 0, // Skip to: 86948 -/* 37253 */ MCD_OPC_CheckField, 10, 1, 0, 24, 194, 0, // Skip to: 86948 -/* 37260 */ MCD_OPC_Decode, 152, 16, 223, 1, // Opcode: LD3i16_POST -/* 37265 */ MCD_OPC_FilterValue, 1, 14, 194, 0, // Skip to: 86948 -/* 37270 */ MCD_OPC_CheckPredicate, 3, 9, 194, 0, // Skip to: 86948 -/* 37275 */ MCD_OPC_CheckField, 31, 1, 0, 2, 194, 0, // Skip to: 86948 -/* 37282 */ MCD_OPC_CheckField, 10, 1, 0, 251, 193, 0, // Skip to: 86948 -/* 37289 */ MCD_OPC_Decode, 198, 16, 224, 1, // Opcode: LD4i16_POST -/* 37294 */ MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 37420 -/* 37299 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 37302 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 37354 -/* 37307 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37310 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37332 -/* 37315 */ MCD_OPC_CheckPredicate, 3, 220, 193, 0, // Skip to: 86948 -/* 37320 */ MCD_OPC_CheckField, 31, 1, 0, 213, 193, 0, // Skip to: 86948 -/* 37327 */ MCD_OPC_Decode, 190, 15, 225, 1, // Opcode: LD1i32_POST -/* 37332 */ MCD_OPC_FilterValue, 1, 203, 193, 0, // Skip to: 86948 -/* 37337 */ MCD_OPC_CheckPredicate, 3, 198, 193, 0, // Skip to: 86948 -/* 37342 */ MCD_OPC_CheckField, 31, 1, 0, 191, 193, 0, // Skip to: 86948 -/* 37349 */ MCD_OPC_Decode, 236, 15, 226, 1, // Opcode: LD2i32_POST -/* 37354 */ MCD_OPC_FilterValue, 1, 181, 193, 0, // Skip to: 86948 -/* 37359 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37362 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37391 -/* 37367 */ MCD_OPC_CheckPredicate, 3, 168, 193, 0, // Skip to: 86948 -/* 37372 */ MCD_OPC_CheckField, 31, 1, 0, 161, 193, 0, // Skip to: 86948 -/* 37379 */ MCD_OPC_CheckField, 12, 1, 0, 154, 193, 0, // Skip to: 86948 -/* 37386 */ MCD_OPC_Decode, 192, 15, 227, 1, // Opcode: LD1i64_POST -/* 37391 */ MCD_OPC_FilterValue, 1, 144, 193, 0, // Skip to: 86948 -/* 37396 */ MCD_OPC_CheckPredicate, 3, 139, 193, 0, // Skip to: 86948 -/* 37401 */ MCD_OPC_CheckField, 31, 1, 0, 132, 193, 0, // Skip to: 86948 -/* 37408 */ MCD_OPC_CheckField, 12, 1, 0, 125, 193, 0, // Skip to: 86948 -/* 37415 */ MCD_OPC_Decode, 238, 15, 228, 1, // Opcode: LD2i64_POST -/* 37420 */ MCD_OPC_FilterValue, 5, 121, 0, 0, // Skip to: 37546 -/* 37425 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 37428 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 37480 -/* 37433 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37436 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37458 -/* 37441 */ MCD_OPC_CheckPredicate, 3, 94, 193, 0, // Skip to: 86948 -/* 37446 */ MCD_OPC_CheckField, 31, 1, 0, 87, 193, 0, // Skip to: 86948 -/* 37453 */ MCD_OPC_Decode, 154, 16, 229, 1, // Opcode: LD3i32_POST -/* 37458 */ MCD_OPC_FilterValue, 1, 77, 193, 0, // Skip to: 86948 -/* 37463 */ MCD_OPC_CheckPredicate, 3, 72, 193, 0, // Skip to: 86948 -/* 37468 */ MCD_OPC_CheckField, 31, 1, 0, 65, 193, 0, // Skip to: 86948 -/* 37475 */ MCD_OPC_Decode, 200, 16, 230, 1, // Opcode: LD4i32_POST -/* 37480 */ MCD_OPC_FilterValue, 1, 55, 193, 0, // Skip to: 86948 -/* 37485 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37488 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37517 -/* 37493 */ MCD_OPC_CheckPredicate, 3, 42, 193, 0, // Skip to: 86948 -/* 37498 */ MCD_OPC_CheckField, 31, 1, 0, 35, 193, 0, // Skip to: 86948 -/* 37505 */ MCD_OPC_CheckField, 12, 1, 0, 28, 193, 0, // Skip to: 86948 -/* 37512 */ MCD_OPC_Decode, 156, 16, 231, 1, // Opcode: LD3i64_POST -/* 37517 */ MCD_OPC_FilterValue, 1, 18, 193, 0, // Skip to: 86948 -/* 37522 */ MCD_OPC_CheckPredicate, 3, 13, 193, 0, // Skip to: 86948 -/* 37527 */ MCD_OPC_CheckField, 31, 1, 0, 6, 193, 0, // Skip to: 86948 -/* 37534 */ MCD_OPC_CheckField, 12, 1, 0, 255, 192, 0, // Skip to: 86948 -/* 37541 */ MCD_OPC_Decode, 202, 16, 232, 1, // Opcode: LD4i64_POST -/* 37546 */ MCD_OPC_FilterValue, 6, 83, 1, 0, // Skip to: 37890 -/* 37551 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 37554 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 37638 -/* 37559 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37562 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37600 -/* 37567 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37570 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37585 -/* 37575 */ MCD_OPC_CheckPredicate, 3, 216, 192, 0, // Skip to: 86948 -/* 37580 */ MCD_OPC_Decode, 136, 15, 163, 1, // Opcode: LD1Rv8b_POST -/* 37585 */ MCD_OPC_FilterValue, 1, 206, 192, 0, // Skip to: 86948 -/* 37590 */ MCD_OPC_CheckPredicate, 3, 201, 192, 0, // Skip to: 86948 -/* 37595 */ MCD_OPC_Decode, 252, 14, 167, 1, // Opcode: LD1Rv16b_POST -/* 37600 */ MCD_OPC_FilterValue, 1, 191, 192, 0, // Skip to: 86948 -/* 37605 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37608 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37623 -/* 37613 */ MCD_OPC_CheckPredicate, 3, 178, 192, 0, // Skip to: 86948 -/* 37618 */ MCD_OPC_Decode, 214, 15, 164, 1, // Opcode: LD2Rv8b_POST -/* 37623 */ MCD_OPC_FilterValue, 1, 168, 192, 0, // Skip to: 86948 -/* 37628 */ MCD_OPC_CheckPredicate, 3, 163, 192, 0, // Skip to: 86948 -/* 37633 */ MCD_OPC_Decode, 202, 15, 168, 1, // Opcode: LD2Rv16b_POST -/* 37638 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 37722 -/* 37643 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37646 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37684 -/* 37651 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37654 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37669 -/* 37659 */ MCD_OPC_CheckPredicate, 3, 132, 192, 0, // Skip to: 86948 -/* 37664 */ MCD_OPC_Decode, 132, 15, 163, 1, // Opcode: LD1Rv4h_POST -/* 37669 */ MCD_OPC_FilterValue, 1, 122, 192, 0, // Skip to: 86948 -/* 37674 */ MCD_OPC_CheckPredicate, 3, 117, 192, 0, // Skip to: 86948 -/* 37679 */ MCD_OPC_Decode, 138, 15, 167, 1, // Opcode: LD1Rv8h_POST -/* 37684 */ MCD_OPC_FilterValue, 1, 107, 192, 0, // Skip to: 86948 -/* 37689 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37692 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37707 -/* 37697 */ MCD_OPC_CheckPredicate, 3, 94, 192, 0, // Skip to: 86948 -/* 37702 */ MCD_OPC_Decode, 210, 15, 164, 1, // Opcode: LD2Rv4h_POST -/* 37707 */ MCD_OPC_FilterValue, 1, 84, 192, 0, // Skip to: 86948 -/* 37712 */ MCD_OPC_CheckPredicate, 3, 79, 192, 0, // Skip to: 86948 -/* 37717 */ MCD_OPC_Decode, 216, 15, 168, 1, // Opcode: LD2Rv8h_POST -/* 37722 */ MCD_OPC_FilterValue, 2, 79, 0, 0, // Skip to: 37806 -/* 37727 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37730 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37768 -/* 37735 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37738 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37753 -/* 37743 */ MCD_OPC_CheckPredicate, 3, 48, 192, 0, // Skip to: 86948 -/* 37748 */ MCD_OPC_Decode, 130, 15, 163, 1, // Opcode: LD1Rv2s_POST -/* 37753 */ MCD_OPC_FilterValue, 1, 38, 192, 0, // Skip to: 86948 -/* 37758 */ MCD_OPC_CheckPredicate, 3, 33, 192, 0, // Skip to: 86948 -/* 37763 */ MCD_OPC_Decode, 134, 15, 167, 1, // Opcode: LD1Rv4s_POST -/* 37768 */ MCD_OPC_FilterValue, 1, 23, 192, 0, // Skip to: 86948 -/* 37773 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37791 -/* 37781 */ MCD_OPC_CheckPredicate, 3, 10, 192, 0, // Skip to: 86948 -/* 37786 */ MCD_OPC_Decode, 208, 15, 164, 1, // Opcode: LD2Rv2s_POST -/* 37791 */ MCD_OPC_FilterValue, 1, 0, 192, 0, // Skip to: 86948 -/* 37796 */ MCD_OPC_CheckPredicate, 3, 251, 191, 0, // Skip to: 86948 -/* 37801 */ MCD_OPC_Decode, 212, 15, 168, 1, // Opcode: LD2Rv4s_POST -/* 37806 */ MCD_OPC_FilterValue, 3, 241, 191, 0, // Skip to: 86948 -/* 37811 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37814 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37852 -/* 37819 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37822 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37837 -/* 37827 */ MCD_OPC_CheckPredicate, 3, 220, 191, 0, // Skip to: 86948 -/* 37832 */ MCD_OPC_Decode, 254, 14, 163, 1, // Opcode: LD1Rv1d_POST -/* 37837 */ MCD_OPC_FilterValue, 1, 210, 191, 0, // Skip to: 86948 -/* 37842 */ MCD_OPC_CheckPredicate, 3, 205, 191, 0, // Skip to: 86948 -/* 37847 */ MCD_OPC_Decode, 128, 15, 167, 1, // Opcode: LD1Rv2d_POST -/* 37852 */ MCD_OPC_FilterValue, 1, 195, 191, 0, // Skip to: 86948 -/* 37857 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37860 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37875 -/* 37865 */ MCD_OPC_CheckPredicate, 3, 182, 191, 0, // Skip to: 86948 -/* 37870 */ MCD_OPC_Decode, 204, 15, 164, 1, // Opcode: LD2Rv1d_POST -/* 37875 */ MCD_OPC_FilterValue, 1, 172, 191, 0, // Skip to: 86948 -/* 37880 */ MCD_OPC_CheckPredicate, 3, 167, 191, 0, // Skip to: 86948 -/* 37885 */ MCD_OPC_Decode, 206, 15, 168, 1, // Opcode: LD2Rv2d_POST -/* 37890 */ MCD_OPC_FilterValue, 7, 157, 191, 0, // Skip to: 86948 -/* 37895 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 37898 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 37982 -/* 37903 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37906 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37944 -/* 37911 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37914 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37929 -/* 37919 */ MCD_OPC_CheckPredicate, 3, 128, 191, 0, // Skip to: 86948 -/* 37924 */ MCD_OPC_Decode, 132, 16, 162, 1, // Opcode: LD3Rv8b_POST -/* 37929 */ MCD_OPC_FilterValue, 1, 118, 191, 0, // Skip to: 86948 -/* 37934 */ MCD_OPC_CheckPredicate, 3, 113, 191, 0, // Skip to: 86948 -/* 37939 */ MCD_OPC_Decode, 248, 15, 166, 1, // Opcode: LD3Rv16b_POST -/* 37944 */ MCD_OPC_FilterValue, 1, 103, 191, 0, // Skip to: 86948 -/* 37949 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37952 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37967 -/* 37957 */ MCD_OPC_CheckPredicate, 3, 90, 191, 0, // Skip to: 86948 -/* 37962 */ MCD_OPC_Decode, 192, 16, 161, 1, // Opcode: LD4Rv8b_POST -/* 37967 */ MCD_OPC_FilterValue, 1, 80, 191, 0, // Skip to: 86948 -/* 37972 */ MCD_OPC_CheckPredicate, 3, 75, 191, 0, // Skip to: 86948 -/* 37977 */ MCD_OPC_Decode, 180, 16, 165, 1, // Opcode: LD4Rv16b_POST -/* 37982 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 38066 -/* 37987 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 37990 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38028 -/* 37995 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 37998 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38013 -/* 38003 */ MCD_OPC_CheckPredicate, 3, 44, 191, 0, // Skip to: 86948 -/* 38008 */ MCD_OPC_Decode, 128, 16, 162, 1, // Opcode: LD3Rv4h_POST -/* 38013 */ MCD_OPC_FilterValue, 1, 34, 191, 0, // Skip to: 86948 -/* 38018 */ MCD_OPC_CheckPredicate, 3, 29, 191, 0, // Skip to: 86948 -/* 38023 */ MCD_OPC_Decode, 134, 16, 166, 1, // Opcode: LD3Rv8h_POST -/* 38028 */ MCD_OPC_FilterValue, 1, 19, 191, 0, // Skip to: 86948 -/* 38033 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 38036 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38051 -/* 38041 */ MCD_OPC_CheckPredicate, 3, 6, 191, 0, // Skip to: 86948 -/* 38046 */ MCD_OPC_Decode, 188, 16, 161, 1, // Opcode: LD4Rv4h_POST -/* 38051 */ MCD_OPC_FilterValue, 1, 252, 190, 0, // Skip to: 86948 -/* 38056 */ MCD_OPC_CheckPredicate, 3, 247, 190, 0, // Skip to: 86948 -/* 38061 */ MCD_OPC_Decode, 194, 16, 165, 1, // Opcode: LD4Rv8h_POST -/* 38066 */ MCD_OPC_FilterValue, 2, 79, 0, 0, // Skip to: 38150 -/* 38071 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38074 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38112 -/* 38079 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 38082 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38097 -/* 38087 */ MCD_OPC_CheckPredicate, 3, 216, 190, 0, // Skip to: 86948 -/* 38092 */ MCD_OPC_Decode, 254, 15, 162, 1, // Opcode: LD3Rv2s_POST -/* 38097 */ MCD_OPC_FilterValue, 1, 206, 190, 0, // Skip to: 86948 -/* 38102 */ MCD_OPC_CheckPredicate, 3, 201, 190, 0, // Skip to: 86948 -/* 38107 */ MCD_OPC_Decode, 130, 16, 166, 1, // Opcode: LD3Rv4s_POST -/* 38112 */ MCD_OPC_FilterValue, 1, 191, 190, 0, // Skip to: 86948 -/* 38117 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 38120 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38135 -/* 38125 */ MCD_OPC_CheckPredicate, 3, 178, 190, 0, // Skip to: 86948 -/* 38130 */ MCD_OPC_Decode, 186, 16, 161, 1, // Opcode: LD4Rv2s_POST -/* 38135 */ MCD_OPC_FilterValue, 1, 168, 190, 0, // Skip to: 86948 -/* 38140 */ MCD_OPC_CheckPredicate, 3, 163, 190, 0, // Skip to: 86948 -/* 38145 */ MCD_OPC_Decode, 190, 16, 165, 1, // Opcode: LD4Rv4s_POST -/* 38150 */ MCD_OPC_FilterValue, 3, 153, 190, 0, // Skip to: 86948 -/* 38155 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38158 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38196 -/* 38163 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 38166 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38181 -/* 38171 */ MCD_OPC_CheckPredicate, 3, 132, 190, 0, // Skip to: 86948 -/* 38176 */ MCD_OPC_Decode, 250, 15, 162, 1, // Opcode: LD3Rv1d_POST -/* 38181 */ MCD_OPC_FilterValue, 1, 122, 190, 0, // Skip to: 86948 -/* 38186 */ MCD_OPC_CheckPredicate, 3, 117, 190, 0, // Skip to: 86948 -/* 38191 */ MCD_OPC_Decode, 252, 15, 166, 1, // Opcode: LD3Rv2d_POST -/* 38196 */ MCD_OPC_FilterValue, 1, 107, 190, 0, // Skip to: 86948 -/* 38201 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 38204 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38219 -/* 38209 */ MCD_OPC_CheckPredicate, 3, 94, 190, 0, // Skip to: 86948 -/* 38214 */ MCD_OPC_Decode, 182, 16, 161, 1, // Opcode: LD4Rv1d_POST -/* 38219 */ MCD_OPC_FilterValue, 1, 84, 190, 0, // Skip to: 86948 -/* 38224 */ MCD_OPC_CheckPredicate, 3, 79, 190, 0, // Skip to: 86948 -/* 38229 */ MCD_OPC_Decode, 184, 16, 165, 1, // Opcode: LD4Rv2d_POST -/* 38234 */ MCD_OPC_FilterValue, 1, 69, 190, 0, // Skip to: 86948 -/* 38239 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 38242 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 38252 -/* 38247 */ MCD_OPC_Decode, 208, 17, 150, 1, // Opcode: LDPSpre -/* 38252 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 38262 -/* 38257 */ MCD_OPC_Decode, 199, 17, 150, 1, // Opcode: LDPDpre -/* 38262 */ MCD_OPC_FilterValue, 2, 41, 190, 0, // Skip to: 86948 -/* 38267 */ MCD_OPC_Decode, 202, 17, 150, 1, // Opcode: LDPQpre -/* 38272 */ MCD_OPC_FilterValue, 8, 6, 27, 0, // Skip to: 45195 -/* 38277 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 38280 */ MCD_OPC_FilterValue, 0, 189, 7, 0, // Skip to: 40266 -/* 38285 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 38288 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38326 -/* 38293 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38311 -/* 38301 */ MCD_OPC_CheckPredicate, 3, 2, 190, 0, // Skip to: 86948 -/* 38306 */ MCD_OPC_Decode, 186, 30, 233, 1, // Opcode: TBLv8i8One -/* 38311 */ MCD_OPC_FilterValue, 1, 248, 189, 0, // Skip to: 86948 -/* 38316 */ MCD_OPC_CheckPredicate, 3, 243, 189, 0, // Skip to: 86948 -/* 38321 */ MCD_OPC_Decode, 168, 22, 234, 1, // Opcode: SADDLv8i8_v8i16 -/* 38326 */ MCD_OPC_FilterValue, 1, 86, 0, 0, // Skip to: 38417 -/* 38331 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38334 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 38402 -/* 38339 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 38342 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 38387 -/* 38347 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 38350 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 38372 -/* 38355 */ MCD_OPC_CheckPredicate, 3, 204, 189, 0, // Skip to: 86948 -/* 38360 */ MCD_OPC_CheckField, 18, 1, 1, 197, 189, 0, // Skip to: 86948 -/* 38367 */ MCD_OPC_Decode, 211, 5, 235, 1, // Opcode: DUPv2i32lane -/* 38372 */ MCD_OPC_FilterValue, 1, 187, 189, 0, // Skip to: 86948 -/* 38377 */ MCD_OPC_CheckPredicate, 3, 182, 189, 0, // Skip to: 86948 -/* 38382 */ MCD_OPC_Decode, 215, 5, 236, 1, // Opcode: DUPv4i16lane -/* 38387 */ MCD_OPC_FilterValue, 1, 172, 189, 0, // Skip to: 86948 -/* 38392 */ MCD_OPC_CheckPredicate, 3, 167, 189, 0, // Skip to: 86948 -/* 38397 */ MCD_OPC_Decode, 221, 5, 237, 1, // Opcode: DUPv8i8lane -/* 38402 */ MCD_OPC_FilterValue, 1, 157, 189, 0, // Skip to: 86948 -/* 38407 */ MCD_OPC_CheckPredicate, 3, 152, 189, 0, // Skip to: 86948 -/* 38412 */ MCD_OPC_Decode, 132, 23, 238, 1, // Opcode: SHADDv8i8 -/* 38417 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 38439 -/* 38422 */ MCD_OPC_CheckPredicate, 3, 137, 189, 0, // Skip to: 86948 -/* 38427 */ MCD_OPC_CheckField, 16, 6, 32, 130, 189, 0, // Skip to: 86948 -/* 38434 */ MCD_OPC_Decode, 214, 21, 239, 1, // Opcode: REV64v8i8 -/* 38439 */ MCD_OPC_FilterValue, 3, 86, 0, 0, // Skip to: 38530 -/* 38444 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38447 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 38515 -/* 38452 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 38455 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 38500 -/* 38460 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 38463 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 38485 -/* 38468 */ MCD_OPC_CheckPredicate, 3, 91, 189, 0, // Skip to: 86948 -/* 38473 */ MCD_OPC_CheckField, 18, 1, 1, 84, 189, 0, // Skip to: 86948 -/* 38480 */ MCD_OPC_Decode, 210, 5, 240, 1, // Opcode: DUPv2i32gpr -/* 38485 */ MCD_OPC_FilterValue, 1, 74, 189, 0, // Skip to: 86948 -/* 38490 */ MCD_OPC_CheckPredicate, 3, 69, 189, 0, // Skip to: 86948 -/* 38495 */ MCD_OPC_Decode, 214, 5, 240, 1, // Opcode: DUPv4i16gpr -/* 38500 */ MCD_OPC_FilterValue, 1, 59, 189, 0, // Skip to: 86948 -/* 38505 */ MCD_OPC_CheckPredicate, 3, 54, 189, 0, // Skip to: 86948 -/* 38510 */ MCD_OPC_Decode, 220, 5, 240, 1, // Opcode: DUPv8i8gpr -/* 38515 */ MCD_OPC_FilterValue, 1, 44, 189, 0, // Skip to: 86948 -/* 38520 */ MCD_OPC_CheckPredicate, 3, 39, 189, 0, // Skip to: 86948 -/* 38525 */ MCD_OPC_Decode, 182, 24, 238, 1, // Opcode: SQADDv8i8 -/* 38530 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 38568 -/* 38535 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38538 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38553 -/* 38543 */ MCD_OPC_CheckPredicate, 3, 16, 189, 0, // Skip to: 86948 -/* 38548 */ MCD_OPC_Decode, 196, 30, 241, 1, // Opcode: TBXv8i8One -/* 38553 */ MCD_OPC_FilterValue, 1, 6, 189, 0, // Skip to: 86948 -/* 38558 */ MCD_OPC_CheckPredicate, 3, 1, 189, 0, // Skip to: 86948 -/* 38563 */ MCD_OPC_Decode, 177, 22, 242, 1, // Opcode: SADDWv8i8_v8i16 -/* 38568 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 38590 -/* 38573 */ MCD_OPC_CheckPredicate, 3, 242, 188, 0, // Skip to: 86948 -/* 38578 */ MCD_OPC_CheckField, 21, 1, 1, 235, 188, 0, // Skip to: 86948 -/* 38585 */ MCD_OPC_Decode, 188, 26, 238, 1, // Opcode: SRHADDv8i8 -/* 38590 */ MCD_OPC_FilterValue, 6, 40, 0, 0, // Skip to: 38635 -/* 38595 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38598 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38613 -/* 38603 */ MCD_OPC_CheckPredicate, 3, 212, 188, 0, // Skip to: 86948 -/* 38608 */ MCD_OPC_Decode, 202, 34, 238, 1, // Opcode: UZP1v8i8 -/* 38613 */ MCD_OPC_FilterValue, 1, 202, 188, 0, // Skip to: 86948 -/* 38618 */ MCD_OPC_CheckPredicate, 3, 197, 188, 0, // Skip to: 86948 -/* 38623 */ MCD_OPC_CheckField, 16, 5, 0, 190, 188, 0, // Skip to: 86948 -/* 38630 */ MCD_OPC_Decode, 203, 21, 239, 1, // Opcode: REV16v8i8 -/* 38635 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 38657 -/* 38640 */ MCD_OPC_CheckPredicate, 3, 175, 188, 0, // Skip to: 86948 -/* 38645 */ MCD_OPC_CheckField, 21, 1, 1, 168, 188, 0, // Skip to: 86948 -/* 38652 */ MCD_OPC_Decode, 253, 1, 238, 1, // Opcode: ANDv8i8 -/* 38657 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 38695 -/* 38662 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38665 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38680 -/* 38670 */ MCD_OPC_CheckPredicate, 3, 145, 188, 0, // Skip to: 86948 -/* 38675 */ MCD_OPC_Decode, 188, 30, 243, 1, // Opcode: TBLv8i8Two -/* 38680 */ MCD_OPC_FilterValue, 1, 135, 188, 0, // Skip to: 86948 -/* 38685 */ MCD_OPC_CheckPredicate, 3, 130, 188, 0, // Skip to: 86948 -/* 38690 */ MCD_OPC_Decode, 166, 27, 234, 1, // Opcode: SSUBLv8i8_v8i16 -/* 38695 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 38717 -/* 38700 */ MCD_OPC_CheckPredicate, 3, 115, 188, 0, // Skip to: 86948 -/* 38705 */ MCD_OPC_CheckField, 21, 1, 1, 108, 188, 0, // Skip to: 86948 -/* 38712 */ MCD_OPC_Decode, 158, 23, 238, 1, // Opcode: SHSUBv8i8 -/* 38717 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 38778 -/* 38722 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38725 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38740 -/* 38730 */ MCD_OPC_CheckPredicate, 3, 85, 188, 0, // Skip to: 86948 -/* 38735 */ MCD_OPC_Decode, 219, 30, 238, 1, // Opcode: TRN1v8i8 -/* 38740 */ MCD_OPC_FilterValue, 1, 75, 188, 0, // Skip to: 86948 -/* 38745 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 38748 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38763 -/* 38753 */ MCD_OPC_CheckPredicate, 3, 62, 188, 0, // Skip to: 86948 -/* 38758 */ MCD_OPC_Decode, 157, 22, 239, 1, // Opcode: SADDLPv8i8_v4i16 -/* 38763 */ MCD_OPC_FilterValue, 1, 52, 188, 0, // Skip to: 86948 -/* 38768 */ MCD_OPC_CheckPredicate, 3, 47, 188, 0, // Skip to: 86948 -/* 38773 */ MCD_OPC_Decode, 132, 35, 244, 1, // Opcode: XTNv8i8 -/* 38778 */ MCD_OPC_FilterValue, 11, 63, 0, 0, // Skip to: 38846 -/* 38783 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38786 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 38831 -/* 38791 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 38794 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 38816 -/* 38799 */ MCD_OPC_CheckPredicate, 3, 16, 188, 0, // Skip to: 86948 -/* 38804 */ MCD_OPC_CheckField, 17, 1, 1, 9, 188, 0, // Skip to: 86948 -/* 38811 */ MCD_OPC_Decode, 128, 24, 245, 1, // Opcode: SMOVvi16to32 -/* 38816 */ MCD_OPC_FilterValue, 1, 255, 187, 0, // Skip to: 86948 -/* 38821 */ MCD_OPC_CheckPredicate, 3, 250, 187, 0, // Skip to: 86948 -/* 38826 */ MCD_OPC_Decode, 131, 24, 246, 1, // Opcode: SMOVvi8to32 -/* 38831 */ MCD_OPC_FilterValue, 1, 240, 187, 0, // Skip to: 86948 -/* 38836 */ MCD_OPC_CheckPredicate, 3, 235, 187, 0, // Skip to: 86948 -/* 38841 */ MCD_OPC_Decode, 164, 26, 238, 1, // Opcode: SQSUBv8i8 -/* 38846 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 38884 -/* 38851 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38854 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38869 -/* 38859 */ MCD_OPC_CheckPredicate, 3, 212, 187, 0, // Skip to: 86948 -/* 38864 */ MCD_OPC_Decode, 198, 30, 247, 1, // Opcode: TBXv8i8Two -/* 38869 */ MCD_OPC_FilterValue, 1, 202, 187, 0, // Skip to: 86948 -/* 38874 */ MCD_OPC_CheckPredicate, 3, 197, 187, 0, // Skip to: 86948 -/* 38879 */ MCD_OPC_Decode, 172, 27, 242, 1, // Opcode: SSUBWv8i8_v8i16 -/* 38884 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 38906 -/* 38889 */ MCD_OPC_CheckPredicate, 3, 182, 187, 0, // Skip to: 86948 -/* 38894 */ MCD_OPC_CheckField, 21, 1, 1, 175, 187, 0, // Skip to: 86948 -/* 38901 */ MCD_OPC_Decode, 228, 3, 238, 1, // Opcode: CMGTv8i8 -/* 38906 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 38967 -/* 38911 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38914 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38929 -/* 38919 */ MCD_OPC_CheckPredicate, 3, 152, 187, 0, // Skip to: 86948 -/* 38924 */ MCD_OPC_Decode, 147, 35, 238, 1, // Opcode: ZIP1v8i8 -/* 38929 */ MCD_OPC_FilterValue, 1, 142, 187, 0, // Skip to: 86948 -/* 38934 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 38937 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38952 -/* 38942 */ MCD_OPC_CheckPredicate, 3, 129, 187, 0, // Skip to: 86948 -/* 38947 */ MCD_OPC_Decode, 151, 30, 248, 1, // Opcode: SUQADDv8i8 -/* 38952 */ MCD_OPC_FilterValue, 16, 119, 187, 0, // Skip to: 86948 -/* 38957 */ MCD_OPC_CheckPredicate, 3, 114, 187, 0, // Skip to: 86948 -/* 38962 */ MCD_OPC_Decode, 162, 22, 249, 1, // Opcode: SADDLVv8i8v -/* 38967 */ MCD_OPC_FilterValue, 15, 86, 0, 0, // Skip to: 39058 -/* 38972 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38975 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 39043 -/* 38980 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 38983 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 39028 -/* 38988 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 38991 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 39013 -/* 38996 */ MCD_OPC_CheckPredicate, 3, 75, 187, 0, // Skip to: 86948 -/* 39001 */ MCD_OPC_CheckField, 18, 1, 1, 68, 187, 0, // Skip to: 86948 -/* 39008 */ MCD_OPC_Decode, 184, 32, 250, 1, // Opcode: UMOVvi32 -/* 39013 */ MCD_OPC_FilterValue, 1, 58, 187, 0, // Skip to: 86948 -/* 39018 */ MCD_OPC_CheckPredicate, 3, 53, 187, 0, // Skip to: 86948 -/* 39023 */ MCD_OPC_Decode, 183, 32, 245, 1, // Opcode: UMOVvi16 -/* 39028 */ MCD_OPC_FilterValue, 1, 43, 187, 0, // Skip to: 86948 -/* 39033 */ MCD_OPC_CheckPredicate, 3, 38, 187, 0, // Skip to: 86948 -/* 39038 */ MCD_OPC_Decode, 186, 32, 246, 1, // Opcode: UMOVvi8 -/* 39043 */ MCD_OPC_FilterValue, 1, 28, 187, 0, // Skip to: 86948 -/* 39048 */ MCD_OPC_CheckPredicate, 3, 23, 187, 0, // Skip to: 86948 -/* 39053 */ MCD_OPC_Decode, 212, 3, 238, 1, // Opcode: CMGEv8i8 -/* 39058 */ MCD_OPC_FilterValue, 16, 33, 0, 0, // Skip to: 39096 -/* 39063 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39066 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39081 -/* 39071 */ MCD_OPC_CheckPredicate, 3, 0, 187, 0, // Skip to: 86948 -/* 39076 */ MCD_OPC_Decode, 187, 30, 251, 1, // Opcode: TBLv8i8Three -/* 39081 */ MCD_OPC_FilterValue, 1, 246, 186, 0, // Skip to: 86948 -/* 39086 */ MCD_OPC_CheckPredicate, 3, 241, 186, 0, // Skip to: 86948 -/* 39091 */ MCD_OPC_Decode, 147, 1, 252, 1, // Opcode: ADDHNv8i16_v8i8 -/* 39096 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 39118 -/* 39101 */ MCD_OPC_CheckPredicate, 3, 226, 186, 0, // Skip to: 86948 -/* 39106 */ MCD_OPC_CheckField, 21, 1, 1, 219, 186, 0, // Skip to: 86948 -/* 39113 */ MCD_OPC_Decode, 234, 26, 238, 1, // Opcode: SSHLv8i8 -/* 39118 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 39156 -/* 39123 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 39126 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39141 -/* 39131 */ MCD_OPC_CheckPredicate, 3, 196, 186, 0, // Skip to: 86948 -/* 39136 */ MCD_OPC_Decode, 169, 3, 239, 1, // Opcode: CLSv8i8 -/* 39141 */ MCD_OPC_FilterValue, 33, 186, 186, 0, // Skip to: 86948 -/* 39146 */ MCD_OPC_CheckPredicate, 3, 181, 186, 0, // Skip to: 86948 -/* 39151 */ MCD_OPC_Decode, 173, 26, 244, 1, // Opcode: SQXTNv8i8 -/* 39156 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 39178 -/* 39161 */ MCD_OPC_CheckPredicate, 3, 166, 186, 0, // Skip to: 86948 -/* 39166 */ MCD_OPC_CheckField, 21, 1, 1, 159, 186, 0, // Skip to: 86948 -/* 39173 */ MCD_OPC_Decode, 254, 25, 238, 1, // Opcode: SQSHLv8i8 -/* 39178 */ MCD_OPC_FilterValue, 20, 33, 0, 0, // Skip to: 39216 -/* 39183 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39186 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39201 -/* 39191 */ MCD_OPC_CheckPredicate, 3, 136, 186, 0, // Skip to: 86948 -/* 39196 */ MCD_OPC_Decode, 197, 30, 253, 1, // Opcode: TBXv8i8Three -/* 39201 */ MCD_OPC_FilterValue, 1, 126, 186, 0, // Skip to: 86948 -/* 39206 */ MCD_OPC_CheckPredicate, 3, 121, 186, 0, // Skip to: 86948 -/* 39211 */ MCD_OPC_Decode, 251, 21, 254, 1, // Opcode: SABALv8i8_v8i16 -/* 39216 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 39238 -/* 39221 */ MCD_OPC_CheckPredicate, 3, 106, 186, 0, // Skip to: 86948 -/* 39226 */ MCD_OPC_CheckField, 21, 1, 1, 99, 186, 0, // Skip to: 86948 -/* 39233 */ MCD_OPC_Decode, 204, 26, 238, 1, // Opcode: SRSHLv8i8 -/* 39238 */ MCD_OPC_FilterValue, 22, 40, 0, 0, // Skip to: 39283 -/* 39243 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39246 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39261 -/* 39251 */ MCD_OPC_CheckPredicate, 3, 76, 186, 0, // Skip to: 86948 -/* 39256 */ MCD_OPC_Decode, 217, 34, 238, 1, // Opcode: UZP2v8i8 -/* 39261 */ MCD_OPC_FilterValue, 1, 66, 186, 0, // Skip to: 86948 -/* 39266 */ MCD_OPC_CheckPredicate, 3, 61, 186, 0, // Skip to: 86948 -/* 39271 */ MCD_OPC_CheckField, 16, 5, 0, 54, 186, 0, // Skip to: 86948 -/* 39278 */ MCD_OPC_Decode, 130, 5, 239, 1, // Opcode: CNTv8i8 -/* 39283 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 39305 -/* 39288 */ MCD_OPC_CheckPredicate, 3, 39, 186, 0, // Skip to: 86948 -/* 39293 */ MCD_OPC_CheckField, 21, 1, 1, 32, 186, 0, // Skip to: 86948 -/* 39300 */ MCD_OPC_Decode, 204, 25, 238, 1, // Opcode: SQRSHLv8i8 -/* 39305 */ MCD_OPC_FilterValue, 24, 33, 0, 0, // Skip to: 39343 -/* 39310 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39313 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39328 -/* 39318 */ MCD_OPC_CheckPredicate, 3, 9, 186, 0, // Skip to: 86948 -/* 39323 */ MCD_OPC_Decode, 185, 30, 255, 1, // Opcode: TBLv8i8Four -/* 39328 */ MCD_OPC_FilterValue, 1, 255, 185, 0, // Skip to: 86948 -/* 39333 */ MCD_OPC_CheckPredicate, 3, 250, 185, 0, // Skip to: 86948 -/* 39338 */ MCD_OPC_Decode, 216, 29, 252, 1, // Opcode: SUBHNv8i16_v8i8 -/* 39343 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 39365 -/* 39348 */ MCD_OPC_CheckPredicate, 3, 235, 185, 0, // Skip to: 86948 -/* 39353 */ MCD_OPC_CheckField, 21, 1, 1, 228, 185, 0, // Skip to: 86948 -/* 39360 */ MCD_OPC_Decode, 205, 23, 238, 1, // Opcode: SMAXv8i8 -/* 39365 */ MCD_OPC_FilterValue, 26, 56, 0, 0, // Skip to: 39426 -/* 39370 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39373 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39388 -/* 39378 */ MCD_OPC_CheckPredicate, 3, 205, 185, 0, // Skip to: 86948 -/* 39383 */ MCD_OPC_Decode, 234, 30, 238, 1, // Opcode: TRN2v8i8 -/* 39388 */ MCD_OPC_FilterValue, 1, 195, 185, 0, // Skip to: 86948 -/* 39393 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 39396 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39411 -/* 39401 */ MCD_OPC_CheckPredicate, 3, 182, 185, 0, // Skip to: 86948 -/* 39406 */ MCD_OPC_Decode, 151, 22, 248, 1, // Opcode: SADALPv8i8_v4i16 -/* 39411 */ MCD_OPC_FilterValue, 1, 172, 185, 0, // Skip to: 86948 -/* 39416 */ MCD_OPC_CheckPredicate, 3, 167, 185, 0, // Skip to: 86948 -/* 39421 */ MCD_OPC_Decode, 182, 8, 244, 1, // Opcode: FCVTNv4i16 -/* 39426 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 39448 -/* 39431 */ MCD_OPC_CheckPredicate, 3, 152, 185, 0, // Skip to: 86948 -/* 39436 */ MCD_OPC_CheckField, 21, 1, 1, 145, 185, 0, // Skip to: 86948 -/* 39443 */ MCD_OPC_Decode, 235, 23, 238, 1, // Opcode: SMINv8i8 -/* 39448 */ MCD_OPC_FilterValue, 28, 33, 0, 0, // Skip to: 39486 -/* 39453 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39456 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39471 -/* 39461 */ MCD_OPC_CheckPredicate, 3, 122, 185, 0, // Skip to: 86948 -/* 39466 */ MCD_OPC_Decode, 195, 30, 128, 2, // Opcode: TBXv8i8Four -/* 39471 */ MCD_OPC_FilterValue, 1, 112, 185, 0, // Skip to: 86948 -/* 39476 */ MCD_OPC_CheckPredicate, 3, 107, 185, 0, // Skip to: 86948 -/* 39481 */ MCD_OPC_Decode, 135, 22, 234, 1, // Opcode: SABDLv8i8_v8i16 -/* 39486 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 39508 -/* 39491 */ MCD_OPC_CheckPredicate, 3, 92, 185, 0, // Skip to: 86948 -/* 39496 */ MCD_OPC_CheckField, 21, 1, 1, 85, 185, 0, // Skip to: 86948 -/* 39503 */ MCD_OPC_Decode, 145, 22, 238, 1, // Opcode: SABDv8i8 -/* 39508 */ MCD_OPC_FilterValue, 30, 56, 0, 0, // Skip to: 39569 -/* 39513 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39516 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39531 -/* 39521 */ MCD_OPC_CheckPredicate, 3, 62, 185, 0, // Skip to: 86948 -/* 39526 */ MCD_OPC_Decode, 162, 35, 238, 1, // Opcode: ZIP2v8i8 -/* 39531 */ MCD_OPC_FilterValue, 1, 52, 185, 0, // Skip to: 86948 -/* 39536 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 39539 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39554 -/* 39544 */ MCD_OPC_CheckPredicate, 3, 39, 185, 0, // Skip to: 86948 -/* 39549 */ MCD_OPC_Decode, 163, 24, 239, 1, // Opcode: SQABSv8i8 -/* 39554 */ MCD_OPC_FilterValue, 1, 29, 185, 0, // Skip to: 86948 -/* 39559 */ MCD_OPC_CheckPredicate, 3, 24, 185, 0, // Skip to: 86948 -/* 39564 */ MCD_OPC_Decode, 250, 7, 129, 2, // Opcode: FCVTLv4i16 -/* 39569 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 39591 -/* 39574 */ MCD_OPC_CheckPredicate, 3, 9, 185, 0, // Skip to: 86948 -/* 39579 */ MCD_OPC_CheckField, 21, 1, 1, 2, 185, 0, // Skip to: 86948 -/* 39586 */ MCD_OPC_Decode, 129, 22, 130, 2, // Opcode: SABAv8i8 -/* 39591 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 39613 -/* 39596 */ MCD_OPC_CheckPredicate, 3, 243, 184, 0, // Skip to: 86948 -/* 39601 */ MCD_OPC_CheckField, 21, 1, 1, 236, 184, 0, // Skip to: 86948 -/* 39608 */ MCD_OPC_Decode, 245, 23, 254, 1, // Opcode: SMLALv8i8_v8i16 -/* 39613 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 39635 -/* 39618 */ MCD_OPC_CheckPredicate, 3, 221, 184, 0, // Skip to: 86948 -/* 39623 */ MCD_OPC_CheckField, 21, 1, 1, 214, 184, 0, // Skip to: 86948 -/* 39630 */ MCD_OPC_Decode, 201, 1, 238, 1, // Opcode: ADDv8i8 -/* 39635 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 39673 -/* 39640 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 39643 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39658 -/* 39648 */ MCD_OPC_CheckPredicate, 3, 191, 184, 0, // Skip to: 86948 -/* 39653 */ MCD_OPC_Decode, 229, 3, 239, 1, // Opcode: CMGTv8i8rz -/* 39658 */ MCD_OPC_FilterValue, 33, 181, 184, 0, // Skip to: 86948 -/* 39663 */ MCD_OPC_CheckPredicate, 3, 176, 184, 0, // Skip to: 86948 -/* 39668 */ MCD_OPC_Decode, 135, 12, 239, 1, // Opcode: FRINTNv2f32 -/* 39673 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 39695 -/* 39678 */ MCD_OPC_CheckPredicate, 3, 161, 184, 0, // Skip to: 86948 -/* 39683 */ MCD_OPC_CheckField, 21, 1, 1, 154, 184, 0, // Skip to: 86948 -/* 39690 */ MCD_OPC_Decode, 240, 4, 238, 1, // Opcode: CMTSTv8i8 -/* 39695 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 39717 -/* 39700 */ MCD_OPC_CheckPredicate, 3, 139, 184, 0, // Skip to: 86948 -/* 39705 */ MCD_OPC_CheckField, 21, 1, 1, 132, 184, 0, // Skip to: 86948 -/* 39712 */ MCD_OPC_Decode, 218, 19, 130, 2, // Opcode: MLAv8i8 -/* 39717 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 39755 -/* 39722 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 39725 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39740 -/* 39730 */ MCD_OPC_CheckPredicate, 3, 109, 184, 0, // Skip to: 86948 -/* 39735 */ MCD_OPC_Decode, 197, 3, 239, 1, // Opcode: CMEQv8i8rz -/* 39740 */ MCD_OPC_FilterValue, 33, 99, 184, 0, // Skip to: 86948 -/* 39745 */ MCD_OPC_CheckPredicate, 3, 94, 184, 0, // Skip to: 86948 -/* 39750 */ MCD_OPC_Decode, 252, 11, 239, 1, // Opcode: FRINTMv2f32 -/* 39755 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 39777 -/* 39760 */ MCD_OPC_CheckPredicate, 3, 79, 184, 0, // Skip to: 86948 -/* 39765 */ MCD_OPC_CheckField, 21, 1, 1, 72, 184, 0, // Skip to: 86948 -/* 39772 */ MCD_OPC_Decode, 166, 20, 238, 1, // Opcode: MULv8i8 -/* 39777 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 39799 -/* 39782 */ MCD_OPC_CheckPredicate, 3, 57, 184, 0, // Skip to: 86948 -/* 39787 */ MCD_OPC_CheckField, 21, 1, 1, 50, 184, 0, // Skip to: 86948 -/* 39794 */ MCD_OPC_Decode, 255, 23, 254, 1, // Opcode: SMLSLv8i8_v8i16 -/* 39799 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 39821 -/* 39804 */ MCD_OPC_CheckPredicate, 3, 35, 184, 0, // Skip to: 86948 -/* 39809 */ MCD_OPC_CheckField, 21, 1, 1, 28, 184, 0, // Skip to: 86948 -/* 39816 */ MCD_OPC_Decode, 182, 23, 238, 1, // Opcode: SMAXPv8i8 -/* 39821 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 39889 -/* 39826 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 39829 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39844 -/* 39834 */ MCD_OPC_CheckPredicate, 3, 5, 184, 0, // Skip to: 86948 -/* 39839 */ MCD_OPC_Decode, 133, 4, 239, 1, // Opcode: CMLTv8i8rz -/* 39844 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 39859 -/* 39849 */ MCD_OPC_CheckPredicate, 3, 246, 183, 0, // Skip to: 86948 -/* 39854 */ MCD_OPC_Decode, 162, 8, 239, 1, // Opcode: FCVTNSv2f32 -/* 39859 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 39874 -/* 39864 */ MCD_OPC_CheckPredicate, 3, 231, 183, 0, // Skip to: 86948 -/* 39869 */ MCD_OPC_Decode, 191, 23, 131, 2, // Opcode: SMAXVv8i8v -/* 39874 */ MCD_OPC_FilterValue, 49, 221, 183, 0, // Skip to: 86948 -/* 39879 */ MCD_OPC_CheckPredicate, 3, 216, 183, 0, // Skip to: 86948 -/* 39884 */ MCD_OPC_Decode, 221, 23, 131, 2, // Opcode: SMINVv8i8v -/* 39889 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 39911 -/* 39894 */ MCD_OPC_CheckPredicate, 3, 201, 183, 0, // Skip to: 86948 -/* 39899 */ MCD_OPC_CheckField, 21, 1, 1, 194, 183, 0, // Skip to: 86948 -/* 39906 */ MCD_OPC_Decode, 212, 23, 238, 1, // Opcode: SMINPv8i8 -/* 39911 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 39964 -/* 39916 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 39919 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39934 -/* 39924 */ MCD_OPC_CheckPredicate, 3, 171, 183, 0, // Skip to: 86948 -/* 39929 */ MCD_OPC_Decode, 137, 1, 239, 1, // Opcode: ABSv8i8 -/* 39934 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 39949 -/* 39939 */ MCD_OPC_CheckPredicate, 3, 156, 183, 0, // Skip to: 86948 -/* 39944 */ MCD_OPC_Decode, 134, 8, 239, 1, // Opcode: FCVTMSv2f32 -/* 39949 */ MCD_OPC_FilterValue, 49, 146, 183, 0, // Skip to: 86948 -/* 39954 */ MCD_OPC_CheckPredicate, 3, 141, 183, 0, // Skip to: 86948 -/* 39959 */ MCD_OPC_Decode, 171, 1, 131, 2, // Opcode: ADDVv8i8v -/* 39964 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 39986 -/* 39969 */ MCD_OPC_CheckPredicate, 3, 126, 183, 0, // Skip to: 86948 -/* 39974 */ MCD_OPC_CheckField, 21, 1, 1, 119, 183, 0, // Skip to: 86948 -/* 39981 */ MCD_OPC_Decode, 156, 1, 238, 1, // Opcode: ADDPv8i8 -/* 39986 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 40008 -/* 39991 */ MCD_OPC_CheckPredicate, 3, 104, 183, 0, // Skip to: 86948 -/* 39996 */ MCD_OPC_CheckField, 21, 1, 1, 97, 183, 0, // Skip to: 86948 -/* 40003 */ MCD_OPC_Decode, 148, 24, 234, 1, // Opcode: SMULLv8i8_v8i16 -/* 40008 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 40030 -/* 40013 */ MCD_OPC_CheckPredicate, 3, 82, 183, 0, // Skip to: 86948 -/* 40018 */ MCD_OPC_CheckField, 21, 1, 1, 75, 183, 0, // Skip to: 86948 -/* 40025 */ MCD_OPC_Decode, 218, 9, 238, 1, // Opcode: FMAXNMv2f32 -/* 40030 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 40068 -/* 40035 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 40038 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 40053 -/* 40043 */ MCD_OPC_CheckPredicate, 3, 52, 183, 0, // Skip to: 86948 -/* 40048 */ MCD_OPC_Decode, 226, 7, 239, 1, // Opcode: FCVTASv2f32 -/* 40053 */ MCD_OPC_FilterValue, 48, 42, 183, 0, // Skip to: 86948 -/* 40058 */ MCD_OPC_CheckPredicate, 4, 37, 183, 0, // Skip to: 86948 -/* 40063 */ MCD_OPC_Decode, 209, 9, 249, 1, // Opcode: FMAXNMVv4i16v -/* 40068 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 40090 -/* 40073 */ MCD_OPC_CheckPredicate, 3, 22, 183, 0, // Skip to: 86948 -/* 40078 */ MCD_OPC_CheckField, 21, 1, 1, 15, 183, 0, // Skip to: 86948 -/* 40085 */ MCD_OPC_Decode, 186, 10, 130, 2, // Opcode: FMLAv2f32 -/* 40090 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 40112 -/* 40095 */ MCD_OPC_CheckPredicate, 3, 0, 183, 0, // Skip to: 86948 -/* 40100 */ MCD_OPC_CheckField, 21, 1, 1, 249, 182, 0, // Skip to: 86948 -/* 40107 */ MCD_OPC_Decode, 198, 6, 238, 1, // Opcode: FADDv2f32 -/* 40112 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 40134 -/* 40117 */ MCD_OPC_CheckPredicate, 3, 234, 182, 0, // Skip to: 86948 -/* 40122 */ MCD_OPC_CheckField, 16, 6, 33, 227, 182, 0, // Skip to: 86948 -/* 40129 */ MCD_OPC_Decode, 209, 22, 239, 1, // Opcode: SCVTFv2f32 -/* 40134 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 40156 -/* 40139 */ MCD_OPC_CheckPredicate, 3, 212, 182, 0, // Skip to: 86948 -/* 40144 */ MCD_OPC_CheckField, 21, 1, 1, 205, 182, 0, // Skip to: 86948 -/* 40151 */ MCD_OPC_Decode, 129, 11, 238, 1, // Opcode: FMULXv2f32 -/* 40156 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 40178 -/* 40161 */ MCD_OPC_CheckPredicate, 3, 190, 182, 0, // Skip to: 86948 -/* 40166 */ MCD_OPC_CheckField, 21, 1, 1, 183, 182, 0, // Skip to: 86948 -/* 40173 */ MCD_OPC_Decode, 246, 20, 234, 1, // Opcode: PMULLv8i8 -/* 40178 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 40200 -/* 40183 */ MCD_OPC_CheckPredicate, 3, 168, 182, 0, // Skip to: 86948 -/* 40188 */ MCD_OPC_CheckField, 21, 1, 1, 161, 182, 0, // Skip to: 86948 -/* 40195 */ MCD_OPC_Decode, 229, 6, 238, 1, // Opcode: FCMEQv2f32 -/* 40200 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 40222 -/* 40205 */ MCD_OPC_CheckPredicate, 3, 146, 182, 0, // Skip to: 86948 -/* 40210 */ MCD_OPC_CheckField, 21, 1, 1, 139, 182, 0, // Skip to: 86948 -/* 40217 */ MCD_OPC_Decode, 244, 9, 238, 1, // Opcode: FMAXv2f32 -/* 40222 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 40244 -/* 40227 */ MCD_OPC_CheckPredicate, 4, 124, 182, 0, // Skip to: 86948 -/* 40232 */ MCD_OPC_CheckField, 16, 6, 48, 117, 182, 0, // Skip to: 86948 -/* 40239 */ MCD_OPC_Decode, 235, 9, 249, 1, // Opcode: FMAXVv4i16v -/* 40244 */ MCD_OPC_FilterValue, 63, 107, 182, 0, // Skip to: 86948 -/* 40249 */ MCD_OPC_CheckPredicate, 3, 102, 182, 0, // Skip to: 86948 -/* 40254 */ MCD_OPC_CheckField, 21, 1, 1, 95, 182, 0, // Skip to: 86948 -/* 40261 */ MCD_OPC_Decode, 213, 11, 238, 1, // Opcode: FRECPSv2f32 -/* 40266 */ MCD_OPC_FilterValue, 1, 74, 5, 0, // Skip to: 41625 -/* 40271 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 40274 */ MCD_OPC_FilterValue, 0, 135, 1, 0, // Skip to: 40670 -/* 40279 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 40282 */ MCD_OPC_FilterValue, 0, 199, 0, 0, // Skip to: 40486 -/* 40287 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 40290 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40305 -/* 40295 */ MCD_OPC_CheckPredicate, 3, 56, 182, 0, // Skip to: 86948 -/* 40300 */ MCD_OPC_Decode, 254, 5, 132, 2, // Opcode: EXTv8i8 -/* 40305 */ MCD_OPC_FilterValue, 1, 46, 182, 0, // Skip to: 86948 -/* 40310 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 40313 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40328 -/* 40318 */ MCD_OPC_CheckPredicate, 3, 33, 182, 0, // Skip to: 86948 -/* 40323 */ MCD_OPC_Decode, 158, 31, 234, 1, // Opcode: UADDLv8i8_v8i16 -/* 40328 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 40350 -/* 40333 */ MCD_OPC_CheckPredicate, 3, 18, 182, 0, // Skip to: 86948 -/* 40338 */ MCD_OPC_CheckField, 16, 5, 0, 11, 182, 0, // Skip to: 86948 -/* 40345 */ MCD_OPC_Decode, 208, 21, 239, 1, // Opcode: REV32v8i8 -/* 40350 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 40365 -/* 40355 */ MCD_OPC_CheckPredicate, 3, 252, 181, 0, // Skip to: 86948 -/* 40360 */ MCD_OPC_Decode, 168, 31, 242, 1, // Opcode: UADDWv8i8_v8i16 -/* 40365 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 40380 -/* 40370 */ MCD_OPC_CheckPredicate, 3, 237, 181, 0, // Skip to: 86948 -/* 40375 */ MCD_OPC_Decode, 169, 34, 234, 1, // Opcode: USUBLv8i8_v8i16 -/* 40380 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 40418 -/* 40385 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 40388 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40403 -/* 40393 */ MCD_OPC_CheckPredicate, 3, 214, 181, 0, // Skip to: 86948 -/* 40398 */ MCD_OPC_Decode, 147, 31, 239, 1, // Opcode: UADDLPv8i8_v4i16 -/* 40403 */ MCD_OPC_FilterValue, 1, 204, 181, 0, // Skip to: 86948 -/* 40408 */ MCD_OPC_CheckPredicate, 3, 199, 181, 0, // Skip to: 86948 -/* 40413 */ MCD_OPC_Decode, 182, 26, 244, 1, // Opcode: SQXTUNv8i8 -/* 40418 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 40433 -/* 40423 */ MCD_OPC_CheckPredicate, 3, 184, 181, 0, // Skip to: 86948 -/* 40428 */ MCD_OPC_Decode, 175, 34, 242, 1, // Opcode: USUBWv8i8_v8i16 -/* 40433 */ MCD_OPC_FilterValue, 7, 174, 181, 0, // Skip to: 86948 -/* 40438 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 40441 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40456 -/* 40446 */ MCD_OPC_CheckPredicate, 3, 161, 181, 0, // Skip to: 86948 -/* 40451 */ MCD_OPC_Decode, 155, 34, 248, 1, // Opcode: USQADDv8i8 -/* 40456 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 40471 -/* 40461 */ MCD_OPC_CheckPredicate, 3, 146, 181, 0, // Skip to: 86948 -/* 40466 */ MCD_OPC_Decode, 138, 23, 129, 2, // Opcode: SHLLv8i8 -/* 40471 */ MCD_OPC_FilterValue, 16, 136, 181, 0, // Skip to: 86948 -/* 40476 */ MCD_OPC_CheckPredicate, 3, 131, 181, 0, // Skip to: 86948 -/* 40481 */ MCD_OPC_Decode, 152, 31, 249, 1, // Opcode: UADDLVv8i8v -/* 40486 */ MCD_OPC_FilterValue, 1, 121, 181, 0, // Skip to: 86948 -/* 40491 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 40494 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 40516 -/* 40499 */ MCD_OPC_CheckPredicate, 3, 108, 181, 0, // Skip to: 86948 -/* 40504 */ MCD_OPC_CheckField, 21, 1, 1, 101, 181, 0, // Skip to: 86948 -/* 40511 */ MCD_OPC_Decode, 225, 31, 238, 1, // Opcode: UHADDv8i8 -/* 40516 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 40538 -/* 40521 */ MCD_OPC_CheckPredicate, 3, 86, 181, 0, // Skip to: 86948 -/* 40526 */ MCD_OPC_CheckField, 21, 1, 1, 79, 181, 0, // Skip to: 86948 -/* 40533 */ MCD_OPC_Decode, 221, 32, 238, 1, // Opcode: UQADDv8i8 -/* 40538 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 40560 -/* 40543 */ MCD_OPC_CheckPredicate, 3, 64, 181, 0, // Skip to: 86948 -/* 40548 */ MCD_OPC_CheckField, 21, 1, 1, 57, 181, 0, // Skip to: 86948 -/* 40555 */ MCD_OPC_Decode, 224, 33, 238, 1, // Opcode: URHADDv8i8 -/* 40560 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 40582 -/* 40565 */ MCD_OPC_CheckPredicate, 3, 42, 181, 0, // Skip to: 86948 -/* 40570 */ MCD_OPC_CheckField, 21, 1, 1, 35, 181, 0, // Skip to: 86948 -/* 40577 */ MCD_OPC_Decode, 246, 5, 238, 1, // Opcode: EORv8i8 -/* 40582 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 40604 -/* 40587 */ MCD_OPC_CheckPredicate, 3, 20, 181, 0, // Skip to: 86948 -/* 40592 */ MCD_OPC_CheckField, 21, 1, 1, 13, 181, 0, // Skip to: 86948 -/* 40599 */ MCD_OPC_Decode, 231, 31, 238, 1, // Opcode: UHSUBv8i8 -/* 40604 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 40626 -/* 40609 */ MCD_OPC_CheckPredicate, 3, 254, 180, 0, // Skip to: 86948 -/* 40614 */ MCD_OPC_CheckField, 21, 1, 1, 247, 180, 0, // Skip to: 86948 -/* 40621 */ MCD_OPC_Decode, 207, 33, 238, 1, // Opcode: UQSUBv8i8 -/* 40626 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 40648 -/* 40631 */ MCD_OPC_CheckPredicate, 3, 232, 180, 0, // Skip to: 86948 -/* 40636 */ MCD_OPC_CheckField, 21, 1, 1, 225, 180, 0, // Skip to: 86948 -/* 40643 */ MCD_OPC_Decode, 237, 3, 238, 1, // Opcode: CMHIv8i8 -/* 40648 */ MCD_OPC_FilterValue, 7, 215, 180, 0, // Skip to: 86948 -/* 40653 */ MCD_OPC_CheckPredicate, 3, 210, 180, 0, // Skip to: 86948 -/* 40658 */ MCD_OPC_CheckField, 21, 1, 1, 203, 180, 0, // Skip to: 86948 -/* 40665 */ MCD_OPC_Decode, 245, 3, 238, 1, // Opcode: CMHSv8i8 -/* 40670 */ MCD_OPC_FilterValue, 1, 115, 1, 0, // Skip to: 41046 -/* 40675 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 40678 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 40700 -/* 40683 */ MCD_OPC_CheckPredicate, 3, 180, 180, 0, // Skip to: 86948 -/* 40688 */ MCD_OPC_CheckField, 21, 1, 1, 173, 180, 0, // Skip to: 86948 -/* 40695 */ MCD_OPC_Decode, 182, 21, 252, 1, // Opcode: RADDHNv8i16_v8i8 -/* 40700 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 40722 -/* 40705 */ MCD_OPC_CheckPredicate, 3, 158, 180, 0, // Skip to: 86948 -/* 40710 */ MCD_OPC_CheckField, 21, 1, 1, 151, 180, 0, // Skip to: 86948 -/* 40717 */ MCD_OPC_Decode, 136, 34, 238, 1, // Opcode: USHLv8i8 -/* 40722 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 40760 -/* 40727 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 40730 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 40745 -/* 40735 */ MCD_OPC_CheckPredicate, 3, 128, 180, 0, // Skip to: 86948 -/* 40740 */ MCD_OPC_Decode, 181, 3, 239, 1, // Opcode: CLZv8i8 -/* 40745 */ MCD_OPC_FilterValue, 33, 118, 180, 0, // Skip to: 86948 -/* 40750 */ MCD_OPC_CheckPredicate, 3, 113, 180, 0, // Skip to: 86948 -/* 40755 */ MCD_OPC_Decode, 216, 33, 244, 1, // Opcode: UQXTNv8i8 -/* 40760 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 40782 -/* 40765 */ MCD_OPC_CheckPredicate, 3, 98, 180, 0, // Skip to: 86948 -/* 40770 */ MCD_OPC_CheckField, 21, 1, 1, 91, 180, 0, // Skip to: 86948 -/* 40777 */ MCD_OPC_Decode, 178, 33, 238, 1, // Opcode: UQSHLv8i8 -/* 40782 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 40804 -/* 40787 */ MCD_OPC_CheckPredicate, 3, 76, 180, 0, // Skip to: 86948 -/* 40792 */ MCD_OPC_CheckField, 21, 1, 1, 69, 180, 0, // Skip to: 86948 -/* 40799 */ MCD_OPC_Decode, 241, 30, 254, 1, // Opcode: UABALv8i8_v8i16 -/* 40804 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 40826 -/* 40809 */ MCD_OPC_CheckPredicate, 3, 54, 180, 0, // Skip to: 86948 -/* 40814 */ MCD_OPC_CheckField, 21, 1, 1, 47, 180, 0, // Skip to: 86948 -/* 40821 */ MCD_OPC_Decode, 232, 33, 238, 1, // Opcode: URSHLv8i8 -/* 40826 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 40848 -/* 40831 */ MCD_OPC_CheckPredicate, 3, 32, 180, 0, // Skip to: 86948 -/* 40836 */ MCD_OPC_CheckField, 16, 6, 32, 25, 180, 0, // Skip to: 86948 -/* 40843 */ MCD_OPC_Decode, 194, 20, 239, 1, // Opcode: NOTv8i8 -/* 40848 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 40870 -/* 40853 */ MCD_OPC_CheckPredicate, 3, 10, 180, 0, // Skip to: 86948 -/* 40858 */ MCD_OPC_CheckField, 21, 1, 1, 3, 180, 0, // Skip to: 86948 -/* 40865 */ MCD_OPC_Decode, 148, 33, 238, 1, // Opcode: UQRSHLv8i8 -/* 40870 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 40892 -/* 40875 */ MCD_OPC_CheckPredicate, 3, 244, 179, 0, // Skip to: 86948 -/* 40880 */ MCD_OPC_CheckField, 21, 1, 1, 237, 179, 0, // Skip to: 86948 -/* 40887 */ MCD_OPC_Decode, 245, 21, 252, 1, // Opcode: RSUBHNv8i16_v8i8 -/* 40892 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 40914 -/* 40897 */ MCD_OPC_CheckPredicate, 3, 222, 179, 0, // Skip to: 86948 -/* 40902 */ MCD_OPC_CheckField, 21, 1, 1, 215, 179, 0, // Skip to: 86948 -/* 40909 */ MCD_OPC_Decode, 133, 32, 238, 1, // Opcode: UMAXv8i8 -/* 40914 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 40936 -/* 40919 */ MCD_OPC_CheckPredicate, 3, 200, 179, 0, // Skip to: 86948 -/* 40924 */ MCD_OPC_CheckField, 16, 6, 32, 193, 179, 0, // Skip to: 86948 -/* 40931 */ MCD_OPC_Decode, 141, 31, 248, 1, // Opcode: UADALPv8i8_v4i16 -/* 40936 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 40958 -/* 40941 */ MCD_OPC_CheckPredicate, 3, 178, 179, 0, // Skip to: 86948 -/* 40946 */ MCD_OPC_CheckField, 21, 1, 1, 171, 179, 0, // Skip to: 86948 -/* 40953 */ MCD_OPC_Decode, 162, 32, 238, 1, // Opcode: UMINv8i8 -/* 40958 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 40980 -/* 40963 */ MCD_OPC_CheckPredicate, 3, 156, 179, 0, // Skip to: 86948 -/* 40968 */ MCD_OPC_CheckField, 21, 1, 1, 149, 179, 0, // Skip to: 86948 -/* 40975 */ MCD_OPC_Decode, 253, 30, 234, 1, // Opcode: UABDLv8i8_v8i16 -/* 40980 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 41002 -/* 40985 */ MCD_OPC_CheckPredicate, 3, 134, 179, 0, // Skip to: 86948 -/* 40990 */ MCD_OPC_CheckField, 21, 1, 1, 127, 179, 0, // Skip to: 86948 -/* 40997 */ MCD_OPC_Decode, 135, 31, 238, 1, // Opcode: UABDv8i8 -/* 41002 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 41024 -/* 41007 */ MCD_OPC_CheckPredicate, 3, 112, 179, 0, // Skip to: 86948 -/* 41012 */ MCD_OPC_CheckField, 16, 6, 32, 105, 179, 0, // Skip to: 86948 -/* 41019 */ MCD_OPC_Decode, 157, 25, 239, 1, // Opcode: SQNEGv8i8 -/* 41024 */ MCD_OPC_FilterValue, 15, 95, 179, 0, // Skip to: 86948 -/* 41029 */ MCD_OPC_CheckPredicate, 3, 90, 179, 0, // Skip to: 86948 -/* 41034 */ MCD_OPC_CheckField, 21, 1, 1, 83, 179, 0, // Skip to: 86948 -/* 41041 */ MCD_OPC_Decode, 247, 30, 130, 2, // Opcode: UABAv8i8 -/* 41046 */ MCD_OPC_FilterValue, 2, 90, 1, 0, // Skip to: 41397 -/* 41051 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 41054 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41076 -/* 41059 */ MCD_OPC_CheckPredicate, 3, 60, 179, 0, // Skip to: 86948 -/* 41064 */ MCD_OPC_CheckField, 21, 1, 1, 53, 179, 0, // Skip to: 86948 -/* 41071 */ MCD_OPC_Decode, 172, 32, 254, 1, // Opcode: UMLALv8i8_v8i16 -/* 41076 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 41098 -/* 41081 */ MCD_OPC_CheckPredicate, 3, 38, 179, 0, // Skip to: 86948 -/* 41086 */ MCD_OPC_CheckField, 21, 1, 1, 31, 179, 0, // Skip to: 86948 -/* 41093 */ MCD_OPC_Decode, 134, 30, 238, 1, // Opcode: SUBv8i8 -/* 41098 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 41136 -/* 41103 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 41106 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 41121 -/* 41111 */ MCD_OPC_CheckPredicate, 3, 8, 179, 0, // Skip to: 86948 -/* 41116 */ MCD_OPC_Decode, 213, 3, 239, 1, // Opcode: CMGEv8i8rz -/* 41121 */ MCD_OPC_FilterValue, 33, 254, 178, 0, // Skip to: 86948 -/* 41126 */ MCD_OPC_CheckPredicate, 3, 249, 178, 0, // Skip to: 86948 -/* 41131 */ MCD_OPC_Decode, 230, 11, 239, 1, // Opcode: FRINTAv2f32 -/* 41136 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 41158 -/* 41141 */ MCD_OPC_CheckPredicate, 3, 234, 178, 0, // Skip to: 86948 -/* 41146 */ MCD_OPC_CheckField, 21, 1, 1, 227, 178, 0, // Skip to: 86948 -/* 41153 */ MCD_OPC_Decode, 196, 3, 238, 1, // Opcode: CMEQv8i8 -/* 41158 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 41180 -/* 41163 */ MCD_OPC_CheckPredicate, 3, 212, 178, 0, // Skip to: 86948 -/* 41168 */ MCD_OPC_CheckField, 21, 1, 1, 205, 178, 0, // Skip to: 86948 -/* 41175 */ MCD_OPC_Decode, 232, 19, 130, 2, // Opcode: MLSv8i8 -/* 41180 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 41218 -/* 41185 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 41188 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 41203 -/* 41193 */ MCD_OPC_CheckPredicate, 3, 182, 178, 0, // Skip to: 86948 -/* 41198 */ MCD_OPC_Decode, 253, 3, 239, 1, // Opcode: CMLEv8i8rz -/* 41203 */ MCD_OPC_FilterValue, 33, 172, 178, 0, // Skip to: 86948 -/* 41208 */ MCD_OPC_CheckPredicate, 3, 167, 178, 0, // Skip to: 86948 -/* 41213 */ MCD_OPC_Decode, 157, 12, 239, 1, // Opcode: FRINTXv2f32 -/* 41218 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 41240 -/* 41223 */ MCD_OPC_CheckPredicate, 3, 152, 178, 0, // Skip to: 86948 -/* 41228 */ MCD_OPC_CheckField, 21, 1, 1, 145, 178, 0, // Skip to: 86948 -/* 41235 */ MCD_OPC_Decode, 248, 20, 238, 1, // Opcode: PMULv8i8 -/* 41240 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 41262 -/* 41245 */ MCD_OPC_CheckPredicate, 3, 130, 178, 0, // Skip to: 86948 -/* 41250 */ MCD_OPC_CheckField, 21, 1, 1, 123, 178, 0, // Skip to: 86948 -/* 41257 */ MCD_OPC_Decode, 182, 32, 254, 1, // Opcode: UMLSLv8i8_v8i16 -/* 41262 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 41284 -/* 41267 */ MCD_OPC_CheckPredicate, 3, 108, 178, 0, // Skip to: 86948 -/* 41272 */ MCD_OPC_CheckField, 21, 1, 1, 101, 178, 0, // Skip to: 86948 -/* 41279 */ MCD_OPC_Decode, 238, 31, 238, 1, // Opcode: UMAXPv8i8 -/* 41284 */ MCD_OPC_FilterValue, 10, 48, 0, 0, // Skip to: 41337 -/* 41289 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 41292 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 41307 -/* 41297 */ MCD_OPC_CheckPredicate, 3, 78, 178, 0, // Skip to: 86948 -/* 41302 */ MCD_OPC_Decode, 176, 8, 239, 1, // Opcode: FCVTNUv2f32 -/* 41307 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 41322 -/* 41312 */ MCD_OPC_CheckPredicate, 3, 63, 178, 0, // Skip to: 86948 -/* 41317 */ MCD_OPC_Decode, 247, 31, 131, 2, // Opcode: UMAXVv8i8v -/* 41322 */ MCD_OPC_FilterValue, 49, 53, 178, 0, // Skip to: 86948 -/* 41327 */ MCD_OPC_CheckPredicate, 3, 48, 178, 0, // Skip to: 86948 -/* 41332 */ MCD_OPC_Decode, 148, 32, 131, 2, // Opcode: UMINVv8i8v -/* 41337 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 41359 -/* 41342 */ MCD_OPC_CheckPredicate, 3, 33, 178, 0, // Skip to: 86948 -/* 41347 */ MCD_OPC_CheckField, 21, 1, 1, 26, 178, 0, // Skip to: 86948 -/* 41354 */ MCD_OPC_Decode, 139, 32, 238, 1, // Opcode: UMINPv8i8 -/* 41359 */ MCD_OPC_FilterValue, 14, 16, 178, 0, // Skip to: 86948 -/* 41364 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 41367 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 41382 -/* 41372 */ MCD_OPC_CheckPredicate, 3, 3, 178, 0, // Skip to: 86948 -/* 41377 */ MCD_OPC_Decode, 186, 20, 239, 1, // Opcode: NEGv8i8 -/* 41382 */ MCD_OPC_FilterValue, 33, 249, 177, 0, // Skip to: 86948 -/* 41387 */ MCD_OPC_CheckPredicate, 3, 244, 177, 0, // Skip to: 86948 -/* 41392 */ MCD_OPC_Decode, 148, 8, 239, 1, // Opcode: FCVTMUv2f32 -/* 41397 */ MCD_OPC_FilterValue, 3, 234, 177, 0, // Skip to: 86948 -/* 41402 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 41405 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41427 -/* 41410 */ MCD_OPC_CheckPredicate, 3, 221, 177, 0, // Skip to: 86948 -/* 41415 */ MCD_OPC_CheckField, 21, 1, 1, 214, 177, 0, // Skip to: 86948 -/* 41422 */ MCD_OPC_Decode, 202, 32, 234, 1, // Opcode: UMULLv8i8_v8i16 -/* 41427 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 41449 -/* 41432 */ MCD_OPC_CheckPredicate, 3, 199, 177, 0, // Skip to: 86948 -/* 41437 */ MCD_OPC_CheckField, 21, 1, 1, 192, 177, 0, // Skip to: 86948 -/* 41444 */ MCD_OPC_Decode, 197, 9, 238, 1, // Opcode: FMAXNMPv2f32 -/* 41449 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 41471 -/* 41454 */ MCD_OPC_CheckPredicate, 3, 177, 177, 0, // Skip to: 86948 -/* 41459 */ MCD_OPC_CheckField, 16, 6, 33, 170, 177, 0, // Skip to: 86948 -/* 41466 */ MCD_OPC_Decode, 240, 7, 239, 1, // Opcode: FCVTAUv2f32 -/* 41471 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 41493 -/* 41476 */ MCD_OPC_CheckPredicate, 3, 155, 177, 0, // Skip to: 86948 -/* 41481 */ MCD_OPC_CheckField, 21, 1, 1, 148, 177, 0, // Skip to: 86948 -/* 41488 */ MCD_OPC_Decode, 177, 6, 238, 1, // Opcode: FADDPv2f32 -/* 41493 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 41515 -/* 41498 */ MCD_OPC_CheckPredicate, 3, 133, 177, 0, // Skip to: 86948 -/* 41503 */ MCD_OPC_CheckField, 16, 6, 33, 126, 177, 0, // Skip to: 86948 -/* 41510 */ MCD_OPC_Decode, 196, 31, 239, 1, // Opcode: UCVTFv2f32 -/* 41515 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 41537 -/* 41520 */ MCD_OPC_CheckPredicate, 3, 111, 177, 0, // Skip to: 86948 -/* 41525 */ MCD_OPC_CheckField, 21, 1, 1, 104, 177, 0, // Skip to: 86948 -/* 41532 */ MCD_OPC_Decode, 154, 11, 238, 1, // Opcode: FMULv2f32 -/* 41537 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 41559 -/* 41542 */ MCD_OPC_CheckPredicate, 3, 89, 177, 0, // Skip to: 86948 -/* 41547 */ MCD_OPC_CheckField, 21, 1, 1, 82, 177, 0, // Skip to: 86948 -/* 41554 */ MCD_OPC_Decode, 251, 6, 238, 1, // Opcode: FCMGEv2f32 -/* 41559 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 41581 -/* 41564 */ MCD_OPC_CheckPredicate, 3, 67, 177, 0, // Skip to: 86948 -/* 41569 */ MCD_OPC_CheckField, 21, 1, 1, 60, 177, 0, // Skip to: 86948 -/* 41576 */ MCD_OPC_Decode, 156, 6, 238, 1, // Opcode: FACGEv2f32 -/* 41581 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 41603 -/* 41586 */ MCD_OPC_CheckPredicate, 3, 45, 177, 0, // Skip to: 86948 -/* 41591 */ MCD_OPC_CheckField, 21, 1, 1, 38, 177, 0, // Skip to: 86948 -/* 41598 */ MCD_OPC_Decode, 223, 9, 238, 1, // Opcode: FMAXPv2f32 -/* 41603 */ MCD_OPC_FilterValue, 15, 28, 177, 0, // Skip to: 86948 -/* 41608 */ MCD_OPC_CheckPredicate, 3, 23, 177, 0, // Skip to: 86948 -/* 41613 */ MCD_OPC_CheckField, 21, 1, 1, 16, 177, 0, // Skip to: 86948 -/* 41620 */ MCD_OPC_Decode, 175, 9, 238, 1, // Opcode: FDIVv2f32 -/* 41625 */ MCD_OPC_FilterValue, 2, 109, 8, 0, // Skip to: 43787 -/* 41630 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 41633 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 41671 -/* 41638 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 41641 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 41656 -/* 41646 */ MCD_OPC_CheckPredicate, 3, 241, 176, 0, // Skip to: 86948 -/* 41651 */ MCD_OPC_Decode, 182, 30, 133, 2, // Opcode: TBLv16i8One -/* 41656 */ MCD_OPC_FilterValue, 1, 231, 176, 0, // Skip to: 86948 -/* 41661 */ MCD_OPC_CheckPredicate, 3, 226, 176, 0, // Skip to: 86948 -/* 41666 */ MCD_OPC_Decode, 163, 22, 133, 2, // Opcode: SADDLv16i8_v8i16 -/* 41671 */ MCD_OPC_FilterValue, 1, 109, 0, 0, // Skip to: 41785 -/* 41676 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 41679 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 41770 -/* 41684 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 41687 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 41755 -/* 41692 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 41695 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 41740 -/* 41700 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 41703 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41725 -/* 41708 */ MCD_OPC_CheckPredicate, 3, 179, 176, 0, // Skip to: 86948 -/* 41713 */ MCD_OPC_CheckField, 19, 1, 1, 172, 176, 0, // Skip to: 86948 -/* 41720 */ MCD_OPC_Decode, 213, 5, 134, 2, // Opcode: DUPv2i64lane -/* 41725 */ MCD_OPC_FilterValue, 1, 162, 176, 0, // Skip to: 86948 -/* 41730 */ MCD_OPC_CheckPredicate, 3, 157, 176, 0, // Skip to: 86948 -/* 41735 */ MCD_OPC_Decode, 217, 5, 135, 2, // Opcode: DUPv4i32lane -/* 41740 */ MCD_OPC_FilterValue, 1, 147, 176, 0, // Skip to: 86948 -/* 41745 */ MCD_OPC_CheckPredicate, 3, 142, 176, 0, // Skip to: 86948 -/* 41750 */ MCD_OPC_Decode, 219, 5, 136, 2, // Opcode: DUPv8i16lane -/* 41755 */ MCD_OPC_FilterValue, 1, 132, 176, 0, // Skip to: 86948 -/* 41760 */ MCD_OPC_CheckPredicate, 3, 127, 176, 0, // Skip to: 86948 -/* 41765 */ MCD_OPC_Decode, 209, 5, 137, 2, // Opcode: DUPv16i8lane -/* 41770 */ MCD_OPC_FilterValue, 1, 117, 176, 0, // Skip to: 86948 -/* 41775 */ MCD_OPC_CheckPredicate, 3, 112, 176, 0, // Skip to: 86948 -/* 41780 */ MCD_OPC_Decode, 255, 22, 133, 2, // Opcode: SHADDv16i8 -/* 41785 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 41807 -/* 41790 */ MCD_OPC_CheckPredicate, 3, 97, 176, 0, // Skip to: 86948 -/* 41795 */ MCD_OPC_CheckField, 16, 6, 32, 90, 176, 0, // Skip to: 86948 -/* 41802 */ MCD_OPC_Decode, 209, 21, 138, 2, // Opcode: REV64v16i8 -/* 41807 */ MCD_OPC_FilterValue, 3, 109, 0, 0, // Skip to: 41921 -/* 41812 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 41815 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 41906 -/* 41820 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 41823 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 41891 -/* 41828 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 41831 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 41876 -/* 41836 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 41839 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41861 -/* 41844 */ MCD_OPC_CheckPredicate, 3, 43, 176, 0, // Skip to: 86948 -/* 41849 */ MCD_OPC_CheckField, 19, 1, 1, 36, 176, 0, // Skip to: 86948 -/* 41856 */ MCD_OPC_Decode, 212, 5, 139, 2, // Opcode: DUPv2i64gpr -/* 41861 */ MCD_OPC_FilterValue, 1, 26, 176, 0, // Skip to: 86948 -/* 41866 */ MCD_OPC_CheckPredicate, 3, 21, 176, 0, // Skip to: 86948 -/* 41871 */ MCD_OPC_Decode, 216, 5, 140, 2, // Opcode: DUPv4i32gpr -/* 41876 */ MCD_OPC_FilterValue, 1, 11, 176, 0, // Skip to: 86948 -/* 41881 */ MCD_OPC_CheckPredicate, 3, 6, 176, 0, // Skip to: 86948 -/* 41886 */ MCD_OPC_Decode, 218, 5, 140, 2, // Opcode: DUPv8i16gpr -/* 41891 */ MCD_OPC_FilterValue, 1, 252, 175, 0, // Skip to: 86948 -/* 41896 */ MCD_OPC_CheckPredicate, 3, 247, 175, 0, // Skip to: 86948 -/* 41901 */ MCD_OPC_Decode, 208, 5, 140, 2, // Opcode: DUPv16i8gpr -/* 41906 */ MCD_OPC_FilterValue, 1, 237, 175, 0, // Skip to: 86948 -/* 41911 */ MCD_OPC_CheckPredicate, 3, 232, 175, 0, // Skip to: 86948 -/* 41916 */ MCD_OPC_Decode, 172, 24, 133, 2, // Opcode: SQADDv16i8 -/* 41921 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 41959 -/* 41926 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 41929 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 41944 -/* 41934 */ MCD_OPC_CheckPredicate, 3, 209, 175, 0, // Skip to: 86948 -/* 41939 */ MCD_OPC_Decode, 192, 30, 141, 2, // Opcode: TBXv16i8One -/* 41944 */ MCD_OPC_FilterValue, 1, 199, 175, 0, // Skip to: 86948 -/* 41949 */ MCD_OPC_CheckPredicate, 3, 194, 175, 0, // Skip to: 86948 -/* 41954 */ MCD_OPC_Decode, 172, 22, 133, 2, // Opcode: SADDWv16i8_v8i16 -/* 41959 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 41981 -/* 41964 */ MCD_OPC_CheckPredicate, 3, 179, 175, 0, // Skip to: 86948 -/* 41969 */ MCD_OPC_CheckField, 21, 1, 1, 172, 175, 0, // Skip to: 86948 -/* 41976 */ MCD_OPC_Decode, 183, 26, 133, 2, // Opcode: SRHADDv16i8 -/* 41981 */ MCD_OPC_FilterValue, 6, 40, 0, 0, // Skip to: 42026 -/* 41986 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 41989 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42004 -/* 41994 */ MCD_OPC_CheckPredicate, 3, 149, 175, 0, // Skip to: 86948 -/* 41999 */ MCD_OPC_Decode, 196, 34, 133, 2, // Opcode: UZP1v16i8 -/* 42004 */ MCD_OPC_FilterValue, 1, 139, 175, 0, // Skip to: 86948 -/* 42009 */ MCD_OPC_CheckPredicate, 3, 134, 175, 0, // Skip to: 86948 -/* 42014 */ MCD_OPC_CheckField, 16, 5, 0, 127, 175, 0, // Skip to: 86948 -/* 42021 */ MCD_OPC_Decode, 202, 21, 138, 2, // Opcode: REV16v16i8 -/* 42026 */ MCD_OPC_FilterValue, 7, 109, 0, 0, // Skip to: 42140 -/* 42031 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42034 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 42125 -/* 42039 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 42042 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 42110 -/* 42047 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 42050 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 42095 -/* 42055 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 42058 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 42080 -/* 42063 */ MCD_OPC_CheckPredicate, 3, 80, 175, 0, // Skip to: 86948 -/* 42068 */ MCD_OPC_CheckField, 19, 1, 1, 73, 175, 0, // Skip to: 86948 -/* 42075 */ MCD_OPC_Decode, 158, 14, 142, 2, // Opcode: INSvi64gpr -/* 42080 */ MCD_OPC_FilterValue, 1, 63, 175, 0, // Skip to: 86948 -/* 42085 */ MCD_OPC_CheckPredicate, 3, 58, 175, 0, // Skip to: 86948 -/* 42090 */ MCD_OPC_Decode, 156, 14, 143, 2, // Opcode: INSvi32gpr -/* 42095 */ MCD_OPC_FilterValue, 1, 48, 175, 0, // Skip to: 86948 -/* 42100 */ MCD_OPC_CheckPredicate, 3, 43, 175, 0, // Skip to: 86948 -/* 42105 */ MCD_OPC_Decode, 154, 14, 144, 2, // Opcode: INSvi16gpr -/* 42110 */ MCD_OPC_FilterValue, 1, 33, 175, 0, // Skip to: 86948 -/* 42115 */ MCD_OPC_CheckPredicate, 3, 28, 175, 0, // Skip to: 86948 -/* 42120 */ MCD_OPC_Decode, 160, 14, 145, 2, // Opcode: INSvi8gpr -/* 42125 */ MCD_OPC_FilterValue, 1, 18, 175, 0, // Skip to: 86948 -/* 42130 */ MCD_OPC_CheckPredicate, 3, 13, 175, 0, // Skip to: 86948 -/* 42135 */ MCD_OPC_Decode, 252, 1, 133, 2, // Opcode: ANDv16i8 -/* 42140 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 42178 -/* 42145 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42148 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42163 -/* 42153 */ MCD_OPC_CheckPredicate, 3, 246, 174, 0, // Skip to: 86948 -/* 42158 */ MCD_OPC_Decode, 184, 30, 146, 2, // Opcode: TBLv16i8Two -/* 42163 */ MCD_OPC_FilterValue, 1, 236, 174, 0, // Skip to: 86948 -/* 42168 */ MCD_OPC_CheckPredicate, 3, 231, 174, 0, // Skip to: 86948 -/* 42173 */ MCD_OPC_Decode, 161, 27, 133, 2, // Opcode: SSUBLv16i8_v8i16 -/* 42178 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 42200 -/* 42183 */ MCD_OPC_CheckPredicate, 3, 216, 174, 0, // Skip to: 86948 -/* 42188 */ MCD_OPC_CheckField, 21, 1, 1, 209, 174, 0, // Skip to: 86948 -/* 42195 */ MCD_OPC_Decode, 153, 23, 133, 2, // Opcode: SHSUBv16i8 -/* 42200 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 42261 -/* 42205 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42208 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42223 -/* 42213 */ MCD_OPC_CheckPredicate, 3, 186, 174, 0, // Skip to: 86948 -/* 42218 */ MCD_OPC_Decode, 213, 30, 133, 2, // Opcode: TRN1v16i8 -/* 42223 */ MCD_OPC_FilterValue, 1, 176, 174, 0, // Skip to: 86948 -/* 42228 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 42231 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42246 -/* 42236 */ MCD_OPC_CheckPredicate, 3, 163, 174, 0, // Skip to: 86948 -/* 42241 */ MCD_OPC_Decode, 152, 22, 138, 2, // Opcode: SADDLPv16i8_v8i16 -/* 42246 */ MCD_OPC_FilterValue, 1, 153, 174, 0, // Skip to: 86948 -/* 42251 */ MCD_OPC_CheckPredicate, 3, 148, 174, 0, // Skip to: 86948 -/* 42256 */ MCD_OPC_Decode, 255, 34, 147, 2, // Opcode: XTNv16i8 -/* 42261 */ MCD_OPC_FilterValue, 11, 86, 0, 0, // Skip to: 42352 -/* 42266 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42269 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 42337 -/* 42274 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 42277 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 42322 -/* 42282 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 42285 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 42307 -/* 42290 */ MCD_OPC_CheckPredicate, 3, 109, 174, 0, // Skip to: 86948 -/* 42295 */ MCD_OPC_CheckField, 18, 1, 1, 102, 174, 0, // Skip to: 86948 -/* 42302 */ MCD_OPC_Decode, 130, 24, 148, 2, // Opcode: SMOVvi32to64 -/* 42307 */ MCD_OPC_FilterValue, 1, 92, 174, 0, // Skip to: 86948 -/* 42312 */ MCD_OPC_CheckPredicate, 3, 87, 174, 0, // Skip to: 86948 -/* 42317 */ MCD_OPC_Decode, 129, 24, 149, 2, // Opcode: SMOVvi16to64 -/* 42322 */ MCD_OPC_FilterValue, 1, 77, 174, 0, // Skip to: 86948 -/* 42327 */ MCD_OPC_CheckPredicate, 3, 72, 174, 0, // Skip to: 86948 -/* 42332 */ MCD_OPC_Decode, 132, 24, 150, 2, // Opcode: SMOVvi8to64 -/* 42337 */ MCD_OPC_FilterValue, 1, 62, 174, 0, // Skip to: 86948 -/* 42342 */ MCD_OPC_CheckPredicate, 3, 57, 174, 0, // Skip to: 86948 -/* 42347 */ MCD_OPC_Decode, 154, 26, 133, 2, // Opcode: SQSUBv16i8 -/* 42352 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 42390 -/* 42357 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42360 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42375 -/* 42365 */ MCD_OPC_CheckPredicate, 3, 34, 174, 0, // Skip to: 86948 -/* 42370 */ MCD_OPC_Decode, 194, 30, 151, 2, // Opcode: TBXv16i8Two -/* 42375 */ MCD_OPC_FilterValue, 1, 24, 174, 0, // Skip to: 86948 -/* 42380 */ MCD_OPC_CheckPredicate, 3, 19, 174, 0, // Skip to: 86948 -/* 42385 */ MCD_OPC_Decode, 167, 27, 133, 2, // Opcode: SSUBWv16i8_v8i16 -/* 42390 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 42412 -/* 42395 */ MCD_OPC_CheckPredicate, 3, 4, 174, 0, // Skip to: 86948 -/* 42400 */ MCD_OPC_CheckField, 21, 1, 1, 253, 173, 0, // Skip to: 86948 -/* 42407 */ MCD_OPC_Decode, 214, 3, 133, 2, // Opcode: CMGTv16i8 -/* 42412 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 42473 -/* 42417 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42420 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42435 -/* 42425 */ MCD_OPC_CheckPredicate, 3, 230, 173, 0, // Skip to: 86948 -/* 42430 */ MCD_OPC_Decode, 141, 35, 133, 2, // Opcode: ZIP1v16i8 -/* 42435 */ MCD_OPC_FilterValue, 1, 220, 173, 0, // Skip to: 86948 -/* 42440 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 42443 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42458 -/* 42448 */ MCD_OPC_CheckPredicate, 3, 207, 173, 0, // Skip to: 86948 -/* 42453 */ MCD_OPC_Decode, 141, 30, 147, 2, // Opcode: SUQADDv16i8 -/* 42458 */ MCD_OPC_FilterValue, 16, 197, 173, 0, // Skip to: 86948 -/* 42463 */ MCD_OPC_CheckPredicate, 3, 192, 173, 0, // Skip to: 86948 -/* 42468 */ MCD_OPC_Decode, 158, 22, 152, 2, // Opcode: SADDLVv16i8v -/* 42473 */ MCD_OPC_FilterValue, 15, 40, 0, 0, // Skip to: 42518 -/* 42478 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42481 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 42503 -/* 42486 */ MCD_OPC_CheckPredicate, 3, 169, 173, 0, // Skip to: 86948 -/* 42491 */ MCD_OPC_CheckField, 16, 4, 8, 162, 173, 0, // Skip to: 86948 -/* 42498 */ MCD_OPC_Decode, 185, 32, 153, 2, // Opcode: UMOVvi64 -/* 42503 */ MCD_OPC_FilterValue, 1, 152, 173, 0, // Skip to: 86948 -/* 42508 */ MCD_OPC_CheckPredicate, 3, 147, 173, 0, // Skip to: 86948 -/* 42513 */ MCD_OPC_Decode, 198, 3, 133, 2, // Opcode: CMGEv16i8 -/* 42518 */ MCD_OPC_FilterValue, 16, 33, 0, 0, // Skip to: 42556 -/* 42523 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42526 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42541 -/* 42531 */ MCD_OPC_CheckPredicate, 3, 124, 173, 0, // Skip to: 86948 -/* 42536 */ MCD_OPC_Decode, 183, 30, 154, 2, // Opcode: TBLv16i8Three -/* 42541 */ MCD_OPC_FilterValue, 1, 114, 173, 0, // Skip to: 86948 -/* 42546 */ MCD_OPC_CheckPredicate, 3, 109, 173, 0, // Skip to: 86948 -/* 42551 */ MCD_OPC_Decode, 146, 1, 141, 2, // Opcode: ADDHNv8i16_v16i8 -/* 42556 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 42578 -/* 42561 */ MCD_OPC_CheckPredicate, 3, 94, 173, 0, // Skip to: 86948 -/* 42566 */ MCD_OPC_CheckField, 21, 1, 1, 87, 173, 0, // Skip to: 86948 -/* 42573 */ MCD_OPC_Decode, 227, 26, 133, 2, // Opcode: SSHLv16i8 -/* 42578 */ MCD_OPC_FilterValue, 18, 48, 0, 0, // Skip to: 42631 -/* 42583 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 42586 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 42601 -/* 42591 */ MCD_OPC_CheckPredicate, 3, 64, 173, 0, // Skip to: 86948 -/* 42596 */ MCD_OPC_Decode, 164, 3, 138, 2, // Opcode: CLSv16i8 -/* 42601 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 42616 -/* 42606 */ MCD_OPC_CheckPredicate, 3, 49, 173, 0, // Skip to: 86948 -/* 42611 */ MCD_OPC_Decode, 165, 26, 147, 2, // Opcode: SQXTNv16i8 -/* 42616 */ MCD_OPC_FilterValue, 40, 39, 173, 0, // Skip to: 86948 -/* 42621 */ MCD_OPC_CheckPredicate, 5, 34, 173, 0, // Skip to: 86948 -/* 42626 */ MCD_OPC_Decode, 223, 1, 147, 2, // Opcode: AESErr -/* 42631 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 42653 -/* 42636 */ MCD_OPC_CheckPredicate, 3, 19, 173, 0, // Skip to: 86948 -/* 42641 */ MCD_OPC_CheckField, 21, 1, 1, 12, 173, 0, // Skip to: 86948 -/* 42648 */ MCD_OPC_Decode, 238, 25, 133, 2, // Opcode: SQSHLv16i8 -/* 42653 */ MCD_OPC_FilterValue, 20, 33, 0, 0, // Skip to: 42691 -/* 42658 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42676 -/* 42666 */ MCD_OPC_CheckPredicate, 3, 245, 172, 0, // Skip to: 86948 -/* 42671 */ MCD_OPC_Decode, 193, 30, 155, 2, // Opcode: TBXv16i8Three -/* 42676 */ MCD_OPC_FilterValue, 1, 235, 172, 0, // Skip to: 86948 -/* 42681 */ MCD_OPC_CheckPredicate, 3, 230, 172, 0, // Skip to: 86948 -/* 42686 */ MCD_OPC_Decode, 246, 21, 141, 2, // Opcode: SABALv16i8_v8i16 -/* 42691 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 42713 -/* 42696 */ MCD_OPC_CheckPredicate, 3, 215, 172, 0, // Skip to: 86948 -/* 42701 */ MCD_OPC_CheckField, 21, 1, 1, 208, 172, 0, // Skip to: 86948 -/* 42708 */ MCD_OPC_Decode, 197, 26, 133, 2, // Opcode: SRSHLv16i8 -/* 42713 */ MCD_OPC_FilterValue, 22, 56, 0, 0, // Skip to: 42774 -/* 42718 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42721 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42736 -/* 42726 */ MCD_OPC_CheckPredicate, 3, 185, 172, 0, // Skip to: 86948 -/* 42731 */ MCD_OPC_Decode, 211, 34, 133, 2, // Opcode: UZP2v16i8 -/* 42736 */ MCD_OPC_FilterValue, 1, 175, 172, 0, // Skip to: 86948 -/* 42741 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 42744 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42759 -/* 42749 */ MCD_OPC_CheckPredicate, 3, 162, 172, 0, // Skip to: 86948 -/* 42754 */ MCD_OPC_Decode, 129, 5, 138, 2, // Opcode: CNTv16i8 -/* 42759 */ MCD_OPC_FilterValue, 8, 152, 172, 0, // Skip to: 86948 -/* 42764 */ MCD_OPC_CheckPredicate, 5, 147, 172, 0, // Skip to: 86948 -/* 42769 */ MCD_OPC_Decode, 222, 1, 147, 2, // Opcode: AESDrr -/* 42774 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 42796 -/* 42779 */ MCD_OPC_CheckPredicate, 3, 132, 172, 0, // Skip to: 86948 -/* 42784 */ MCD_OPC_CheckField, 21, 1, 1, 125, 172, 0, // Skip to: 86948 -/* 42791 */ MCD_OPC_Decode, 194, 25, 133, 2, // Opcode: SQRSHLv16i8 -/* 42796 */ MCD_OPC_FilterValue, 24, 33, 0, 0, // Skip to: 42834 -/* 42801 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42804 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42819 -/* 42809 */ MCD_OPC_CheckPredicate, 3, 102, 172, 0, // Skip to: 86948 -/* 42814 */ MCD_OPC_Decode, 181, 30, 156, 2, // Opcode: TBLv16i8Four -/* 42819 */ MCD_OPC_FilterValue, 1, 92, 172, 0, // Skip to: 86948 -/* 42824 */ MCD_OPC_CheckPredicate, 3, 87, 172, 0, // Skip to: 86948 -/* 42829 */ MCD_OPC_Decode, 215, 29, 141, 2, // Opcode: SUBHNv8i16_v16i8 -/* 42834 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 42856 -/* 42839 */ MCD_OPC_CheckPredicate, 3, 72, 172, 0, // Skip to: 86948 -/* 42844 */ MCD_OPC_CheckField, 21, 1, 1, 65, 172, 0, // Skip to: 86948 -/* 42851 */ MCD_OPC_Decode, 200, 23, 133, 2, // Opcode: SMAXv16i8 -/* 42856 */ MCD_OPC_FilterValue, 26, 71, 0, 0, // Skip to: 42932 -/* 42861 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42864 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42879 -/* 42869 */ MCD_OPC_CheckPredicate, 3, 42, 172, 0, // Skip to: 86948 -/* 42874 */ MCD_OPC_Decode, 228, 30, 133, 2, // Opcode: TRN2v16i8 -/* 42879 */ MCD_OPC_FilterValue, 1, 32, 172, 0, // Skip to: 86948 -/* 42884 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 42887 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42902 -/* 42892 */ MCD_OPC_CheckPredicate, 3, 19, 172, 0, // Skip to: 86948 -/* 42897 */ MCD_OPC_Decode, 146, 22, 147, 2, // Opcode: SADALPv16i8_v8i16 -/* 42902 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 42917 -/* 42907 */ MCD_OPC_CheckPredicate, 3, 4, 172, 0, // Skip to: 86948 -/* 42912 */ MCD_OPC_Decode, 184, 8, 147, 2, // Opcode: FCVTNv8i16 -/* 42917 */ MCD_OPC_FilterValue, 8, 250, 171, 0, // Skip to: 86948 -/* 42922 */ MCD_OPC_CheckPredicate, 5, 245, 171, 0, // Skip to: 86948 -/* 42927 */ MCD_OPC_Decode, 226, 1, 138, 2, // Opcode: AESMCrr -/* 42932 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 42954 -/* 42937 */ MCD_OPC_CheckPredicate, 3, 230, 171, 0, // Skip to: 86948 -/* 42942 */ MCD_OPC_CheckField, 21, 1, 1, 223, 171, 0, // Skip to: 86948 -/* 42949 */ MCD_OPC_Decode, 230, 23, 133, 2, // Opcode: SMINv16i8 -/* 42954 */ MCD_OPC_FilterValue, 28, 33, 0, 0, // Skip to: 42992 -/* 42959 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 42962 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42977 -/* 42967 */ MCD_OPC_CheckPredicate, 3, 200, 171, 0, // Skip to: 86948 -/* 42972 */ MCD_OPC_Decode, 191, 30, 157, 2, // Opcode: TBXv16i8Four -/* 42977 */ MCD_OPC_FilterValue, 1, 190, 171, 0, // Skip to: 86948 -/* 42982 */ MCD_OPC_CheckPredicate, 3, 185, 171, 0, // Skip to: 86948 -/* 42987 */ MCD_OPC_Decode, 130, 22, 133, 2, // Opcode: SABDLv16i8_v8i16 -/* 42992 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 43014 -/* 42997 */ MCD_OPC_CheckPredicate, 3, 170, 171, 0, // Skip to: 86948 -/* 43002 */ MCD_OPC_CheckField, 21, 1, 1, 163, 171, 0, // Skip to: 86948 -/* 43009 */ MCD_OPC_Decode, 140, 22, 133, 2, // Opcode: SABDv16i8 -/* 43014 */ MCD_OPC_FilterValue, 30, 71, 0, 0, // Skip to: 43090 -/* 43019 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 43022 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43037 -/* 43027 */ MCD_OPC_CheckPredicate, 3, 140, 171, 0, // Skip to: 86948 -/* 43032 */ MCD_OPC_Decode, 156, 35, 133, 2, // Opcode: ZIP2v16i8 -/* 43037 */ MCD_OPC_FilterValue, 1, 130, 171, 0, // Skip to: 86948 -/* 43042 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 43045 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43060 -/* 43050 */ MCD_OPC_CheckPredicate, 3, 117, 171, 0, // Skip to: 86948 -/* 43055 */ MCD_OPC_Decode, 153, 24, 138, 2, // Opcode: SQABSv16i8 -/* 43060 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 43075 -/* 43065 */ MCD_OPC_CheckPredicate, 3, 102, 171, 0, // Skip to: 86948 -/* 43070 */ MCD_OPC_Decode, 252, 7, 138, 2, // Opcode: FCVTLv8i16 -/* 43075 */ MCD_OPC_FilterValue, 8, 92, 171, 0, // Skip to: 86948 -/* 43080 */ MCD_OPC_CheckPredicate, 5, 87, 171, 0, // Skip to: 86948 -/* 43085 */ MCD_OPC_Decode, 224, 1, 138, 2, // Opcode: AESIMCrr -/* 43090 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 43112 -/* 43095 */ MCD_OPC_CheckPredicate, 3, 72, 171, 0, // Skip to: 86948 -/* 43100 */ MCD_OPC_CheckField, 21, 1, 1, 65, 171, 0, // Skip to: 86948 -/* 43107 */ MCD_OPC_Decode, 252, 21, 141, 2, // Opcode: SABAv16i8 -/* 43112 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 43134 -/* 43117 */ MCD_OPC_CheckPredicate, 3, 50, 171, 0, // Skip to: 86948 -/* 43122 */ MCD_OPC_CheckField, 21, 1, 1, 43, 171, 0, // Skip to: 86948 -/* 43129 */ MCD_OPC_Decode, 236, 23, 141, 2, // Opcode: SMLALv16i8_v8i16 -/* 43134 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 43156 -/* 43139 */ MCD_OPC_CheckPredicate, 3, 28, 171, 0, // Skip to: 86948 -/* 43144 */ MCD_OPC_CheckField, 21, 1, 1, 21, 171, 0, // Skip to: 86948 -/* 43151 */ MCD_OPC_Decode, 194, 1, 133, 2, // Opcode: ADDv16i8 -/* 43156 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 43194 -/* 43161 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 43164 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43179 -/* 43169 */ MCD_OPC_CheckPredicate, 3, 254, 170, 0, // Skip to: 86948 -/* 43174 */ MCD_OPC_Decode, 215, 3, 138, 2, // Opcode: CMGTv16i8rz -/* 43179 */ MCD_OPC_FilterValue, 33, 244, 170, 0, // Skip to: 86948 -/* 43184 */ MCD_OPC_CheckPredicate, 3, 239, 170, 0, // Skip to: 86948 -/* 43189 */ MCD_OPC_Decode, 138, 12, 138, 2, // Opcode: FRINTNv4f32 -/* 43194 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 43216 -/* 43199 */ MCD_OPC_CheckPredicate, 3, 224, 170, 0, // Skip to: 86948 -/* 43204 */ MCD_OPC_CheckField, 21, 1, 1, 217, 170, 0, // Skip to: 86948 -/* 43211 */ MCD_OPC_Decode, 233, 4, 133, 2, // Opcode: CMTSTv16i8 -/* 43216 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 43238 -/* 43221 */ MCD_OPC_CheckPredicate, 3, 202, 170, 0, // Skip to: 86948 -/* 43226 */ MCD_OPC_CheckField, 21, 1, 1, 195, 170, 0, // Skip to: 86948 -/* 43233 */ MCD_OPC_Decode, 209, 19, 141, 2, // Opcode: MLAv16i8 -/* 43238 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 43276 -/* 43243 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 43246 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43261 -/* 43251 */ MCD_OPC_CheckPredicate, 3, 172, 170, 0, // Skip to: 86948 -/* 43256 */ MCD_OPC_Decode, 183, 3, 138, 2, // Opcode: CMEQv16i8rz -/* 43261 */ MCD_OPC_FilterValue, 33, 162, 170, 0, // Skip to: 86948 -/* 43266 */ MCD_OPC_CheckPredicate, 3, 157, 170, 0, // Skip to: 86948 -/* 43271 */ MCD_OPC_Decode, 255, 11, 138, 2, // Opcode: FRINTMv4f32 -/* 43276 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 43298 -/* 43281 */ MCD_OPC_CheckPredicate, 3, 142, 170, 0, // Skip to: 86948 -/* 43286 */ MCD_OPC_CheckField, 21, 1, 1, 135, 170, 0, // Skip to: 86948 -/* 43293 */ MCD_OPC_Decode, 157, 20, 133, 2, // Opcode: MULv16i8 -/* 43298 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 43320 -/* 43303 */ MCD_OPC_CheckPredicate, 3, 120, 170, 0, // Skip to: 86948 -/* 43308 */ MCD_OPC_CheckField, 21, 1, 1, 113, 170, 0, // Skip to: 86948 -/* 43315 */ MCD_OPC_Decode, 246, 23, 141, 2, // Opcode: SMLSLv16i8_v8i16 -/* 43320 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 43342 -/* 43325 */ MCD_OPC_CheckPredicate, 3, 98, 170, 0, // Skip to: 86948 -/* 43330 */ MCD_OPC_CheckField, 21, 1, 1, 91, 170, 0, // Skip to: 86948 -/* 43337 */ MCD_OPC_Decode, 177, 23, 133, 2, // Opcode: SMAXPv16i8 -/* 43342 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 43410 -/* 43347 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 43350 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43365 -/* 43355 */ MCD_OPC_CheckPredicate, 3, 68, 170, 0, // Skip to: 86948 -/* 43360 */ MCD_OPC_Decode, 254, 3, 138, 2, // Opcode: CMLTv16i8rz -/* 43365 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 43380 -/* 43370 */ MCD_OPC_CheckPredicate, 3, 53, 170, 0, // Skip to: 86948 -/* 43375 */ MCD_OPC_Decode, 165, 8, 138, 2, // Opcode: FCVTNSv4f32 -/* 43380 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 43395 -/* 43385 */ MCD_OPC_CheckPredicate, 3, 38, 170, 0, // Skip to: 86948 -/* 43390 */ MCD_OPC_Decode, 187, 23, 158, 2, // Opcode: SMAXVv16i8v -/* 43395 */ MCD_OPC_FilterValue, 49, 28, 170, 0, // Skip to: 86948 -/* 43400 */ MCD_OPC_CheckPredicate, 3, 23, 170, 0, // Skip to: 86948 -/* 43405 */ MCD_OPC_Decode, 217, 23, 158, 2, // Opcode: SMINVv16i8v -/* 43410 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 43432 -/* 43415 */ MCD_OPC_CheckPredicate, 3, 8, 170, 0, // Skip to: 86948 -/* 43420 */ MCD_OPC_CheckField, 21, 1, 1, 1, 170, 0, // Skip to: 86948 -/* 43427 */ MCD_OPC_Decode, 207, 23, 133, 2, // Opcode: SMINPv16i8 -/* 43432 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 43485 -/* 43437 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 43440 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43455 -/* 43445 */ MCD_OPC_CheckPredicate, 3, 234, 169, 0, // Skip to: 86948 -/* 43450 */ MCD_OPC_Decode, 130, 1, 138, 2, // Opcode: ABSv16i8 -/* 43455 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 43470 -/* 43460 */ MCD_OPC_CheckPredicate, 3, 219, 169, 0, // Skip to: 86948 -/* 43465 */ MCD_OPC_Decode, 137, 8, 138, 2, // Opcode: FCVTMSv4f32 -/* 43470 */ MCD_OPC_FilterValue, 49, 209, 169, 0, // Skip to: 86948 -/* 43475 */ MCD_OPC_CheckPredicate, 3, 204, 169, 0, // Skip to: 86948 -/* 43480 */ MCD_OPC_Decode, 167, 1, 158, 2, // Opcode: ADDVv16i8v -/* 43485 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 43507 -/* 43490 */ MCD_OPC_CheckPredicate, 3, 189, 169, 0, // Skip to: 86948 -/* 43495 */ MCD_OPC_CheckField, 21, 1, 1, 182, 169, 0, // Skip to: 86948 -/* 43502 */ MCD_OPC_Decode, 149, 1, 133, 2, // Opcode: ADDPv16i8 -/* 43507 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 43529 -/* 43512 */ MCD_OPC_CheckPredicate, 3, 167, 169, 0, // Skip to: 86948 -/* 43517 */ MCD_OPC_CheckField, 21, 1, 1, 160, 169, 0, // Skip to: 86948 -/* 43524 */ MCD_OPC_Decode, 139, 24, 133, 2, // Opcode: SMULLv16i8_v8i16 -/* 43529 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 43551 -/* 43534 */ MCD_OPC_CheckPredicate, 3, 145, 169, 0, // Skip to: 86948 -/* 43539 */ MCD_OPC_CheckField, 21, 1, 1, 138, 169, 0, // Skip to: 86948 -/* 43546 */ MCD_OPC_Decode, 221, 9, 133, 2, // Opcode: FMAXNMv4f32 -/* 43551 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 43589 -/* 43556 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 43559 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 43574 -/* 43564 */ MCD_OPC_CheckPredicate, 3, 115, 169, 0, // Skip to: 86948 -/* 43569 */ MCD_OPC_Decode, 229, 7, 138, 2, // Opcode: FCVTASv4f32 -/* 43574 */ MCD_OPC_FilterValue, 48, 105, 169, 0, // Skip to: 86948 -/* 43579 */ MCD_OPC_CheckPredicate, 4, 100, 169, 0, // Skip to: 86948 -/* 43584 */ MCD_OPC_Decode, 211, 9, 152, 2, // Opcode: FMAXNMVv8i16v -/* 43589 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 43611 -/* 43594 */ MCD_OPC_CheckPredicate, 3, 85, 169, 0, // Skip to: 86948 -/* 43599 */ MCD_OPC_CheckField, 21, 1, 1, 78, 169, 0, // Skip to: 86948 -/* 43606 */ MCD_OPC_Decode, 191, 10, 141, 2, // Opcode: FMLAv4f32 -/* 43611 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 43633 -/* 43616 */ MCD_OPC_CheckPredicate, 3, 63, 169, 0, // Skip to: 86948 -/* 43621 */ MCD_OPC_CheckField, 21, 1, 1, 56, 169, 0, // Skip to: 86948 -/* 43628 */ MCD_OPC_Decode, 201, 6, 133, 2, // Opcode: FADDv4f32 -/* 43633 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 43655 -/* 43638 */ MCD_OPC_CheckPredicate, 3, 41, 169, 0, // Skip to: 86948 -/* 43643 */ MCD_OPC_CheckField, 16, 6, 33, 34, 169, 0, // Skip to: 86948 -/* 43650 */ MCD_OPC_Decode, 214, 22, 138, 2, // Opcode: SCVTFv4f32 -/* 43655 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 43677 -/* 43660 */ MCD_OPC_CheckPredicate, 3, 19, 169, 0, // Skip to: 86948 -/* 43665 */ MCD_OPC_CheckField, 21, 1, 1, 12, 169, 0, // Skip to: 86948 -/* 43672 */ MCD_OPC_Decode, 134, 11, 133, 2, // Opcode: FMULXv4f32 -/* 43677 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 43699 -/* 43682 */ MCD_OPC_CheckPredicate, 3, 253, 168, 0, // Skip to: 86948 -/* 43687 */ MCD_OPC_CheckField, 21, 1, 1, 246, 168, 0, // Skip to: 86948 -/* 43694 */ MCD_OPC_Decode, 243, 20, 133, 2, // Opcode: PMULLv16i8 -/* 43699 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 43721 -/* 43704 */ MCD_OPC_CheckPredicate, 3, 231, 168, 0, // Skip to: 86948 -/* 43709 */ MCD_OPC_CheckField, 21, 1, 1, 224, 168, 0, // Skip to: 86948 -/* 43716 */ MCD_OPC_Decode, 234, 6, 133, 2, // Opcode: FCMEQv4f32 -/* 43721 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 43743 -/* 43726 */ MCD_OPC_CheckPredicate, 3, 209, 168, 0, // Skip to: 86948 -/* 43731 */ MCD_OPC_CheckField, 21, 1, 1, 202, 168, 0, // Skip to: 86948 -/* 43738 */ MCD_OPC_Decode, 247, 9, 133, 2, // Opcode: FMAXv4f32 -/* 43743 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 43765 -/* 43748 */ MCD_OPC_CheckPredicate, 4, 187, 168, 0, // Skip to: 86948 -/* 43753 */ MCD_OPC_CheckField, 16, 6, 48, 180, 168, 0, // Skip to: 86948 -/* 43760 */ MCD_OPC_Decode, 237, 9, 152, 2, // Opcode: FMAXVv8i16v -/* 43765 */ MCD_OPC_FilterValue, 63, 170, 168, 0, // Skip to: 86948 -/* 43770 */ MCD_OPC_CheckPredicate, 3, 165, 168, 0, // Skip to: 86948 -/* 43775 */ MCD_OPC_CheckField, 21, 1, 1, 158, 168, 0, // Skip to: 86948 -/* 43782 */ MCD_OPC_Decode, 216, 11, 133, 2, // Opcode: FRECPSv4f32 -/* 43787 */ MCD_OPC_FilterValue, 3, 71, 5, 0, // Skip to: 45143 -/* 43792 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 43795 */ MCD_OPC_FilterValue, 0, 182, 2, 0, // Skip to: 44494 -/* 43800 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 43803 */ MCD_OPC_FilterValue, 0, 107, 1, 0, // Skip to: 44171 -/* 43808 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 43811 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43826 -/* 43816 */ MCD_OPC_CheckPredicate, 3, 119, 168, 0, // Skip to: 86948 -/* 43821 */ MCD_OPC_Decode, 253, 5, 159, 2, // Opcode: EXTv16i8 -/* 43826 */ MCD_OPC_FilterValue, 1, 109, 168, 0, // Skip to: 86948 -/* 43831 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... -/* 43834 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43849 -/* 43839 */ MCD_OPC_CheckPredicate, 3, 96, 168, 0, // Skip to: 86948 -/* 43844 */ MCD_OPC_Decode, 153, 31, 133, 2, // Opcode: UADDLv16i8_v8i16 -/* 43849 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 43871 -/* 43854 */ MCD_OPC_CheckPredicate, 3, 81, 168, 0, // Skip to: 86948 -/* 43859 */ MCD_OPC_CheckField, 16, 5, 0, 74, 168, 0, // Skip to: 86948 -/* 43866 */ MCD_OPC_Decode, 205, 21, 138, 2, // Opcode: REV32v16i8 -/* 43871 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 43886 -/* 43876 */ MCD_OPC_CheckPredicate, 3, 59, 168, 0, // Skip to: 86948 -/* 43881 */ MCD_OPC_Decode, 163, 31, 133, 2, // Opcode: UADDWv16i8_v8i16 -/* 43886 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 43901 -/* 43891 */ MCD_OPC_CheckPredicate, 3, 44, 168, 0, // Skip to: 86948 -/* 43896 */ MCD_OPC_Decode, 164, 34, 133, 2, // Opcode: USUBLv16i8_v8i16 -/* 43901 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 43939 -/* 43906 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 43909 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43924 -/* 43914 */ MCD_OPC_CheckPredicate, 3, 21, 168, 0, // Skip to: 86948 -/* 43919 */ MCD_OPC_Decode, 142, 31, 138, 2, // Opcode: UADDLPv16i8_v8i16 -/* 43924 */ MCD_OPC_FilterValue, 1, 11, 168, 0, // Skip to: 86948 -/* 43929 */ MCD_OPC_CheckPredicate, 3, 6, 168, 0, // Skip to: 86948 -/* 43934 */ MCD_OPC_Decode, 174, 26, 147, 2, // Opcode: SQXTUNv16i8 -/* 43939 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 43954 -/* 43944 */ MCD_OPC_CheckPredicate, 3, 247, 167, 0, // Skip to: 86948 -/* 43949 */ MCD_OPC_Decode, 170, 34, 133, 2, // Opcode: USUBWv16i8_v8i16 -/* 43954 */ MCD_OPC_FilterValue, 7, 48, 0, 0, // Skip to: 44007 -/* 43959 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 43962 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43977 -/* 43967 */ MCD_OPC_CheckPredicate, 3, 224, 167, 0, // Skip to: 86948 -/* 43972 */ MCD_OPC_Decode, 145, 34, 147, 2, // Opcode: USQADDv16i8 -/* 43977 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 43992 -/* 43982 */ MCD_OPC_CheckPredicate, 3, 209, 167, 0, // Skip to: 86948 -/* 43987 */ MCD_OPC_Decode, 133, 23, 138, 2, // Opcode: SHLLv16i8 -/* 43992 */ MCD_OPC_FilterValue, 16, 199, 167, 0, // Skip to: 86948 -/* 43997 */ MCD_OPC_CheckPredicate, 3, 194, 167, 0, // Skip to: 86948 -/* 44002 */ MCD_OPC_Decode, 148, 31, 152, 2, // Opcode: UADDLVv16i8v -/* 44007 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 44022 -/* 44012 */ MCD_OPC_CheckPredicate, 3, 179, 167, 0, // Skip to: 86948 -/* 44017 */ MCD_OPC_Decode, 181, 21, 141, 2, // Opcode: RADDHNv8i16_v16i8 -/* 44022 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 44060 -/* 44027 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 44030 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 44045 -/* 44035 */ MCD_OPC_CheckPredicate, 3, 156, 167, 0, // Skip to: 86948 -/* 44040 */ MCD_OPC_Decode, 176, 3, 138, 2, // Opcode: CLZv16i8 -/* 44045 */ MCD_OPC_FilterValue, 1, 146, 167, 0, // Skip to: 86948 -/* 44050 */ MCD_OPC_CheckPredicate, 3, 141, 167, 0, // Skip to: 86948 -/* 44055 */ MCD_OPC_Decode, 208, 33, 147, 2, // Opcode: UQXTNv16i8 -/* 44060 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 44075 -/* 44065 */ MCD_OPC_CheckPredicate, 3, 126, 167, 0, // Skip to: 86948 -/* 44070 */ MCD_OPC_Decode, 236, 30, 141, 2, // Opcode: UABALv16i8_v8i16 -/* 44075 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 44097 -/* 44080 */ MCD_OPC_CheckPredicate, 3, 111, 167, 0, // Skip to: 86948 -/* 44085 */ MCD_OPC_CheckField, 16, 5, 0, 104, 167, 0, // Skip to: 86948 -/* 44092 */ MCD_OPC_Decode, 193, 20, 138, 2, // Opcode: NOTv16i8 -/* 44097 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 44112 -/* 44102 */ MCD_OPC_CheckPredicate, 3, 89, 167, 0, // Skip to: 86948 -/* 44107 */ MCD_OPC_Decode, 244, 21, 141, 2, // Opcode: RSUBHNv8i16_v16i8 -/* 44112 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 44134 -/* 44117 */ MCD_OPC_CheckPredicate, 3, 74, 167, 0, // Skip to: 86948 -/* 44122 */ MCD_OPC_CheckField, 16, 5, 0, 67, 167, 0, // Skip to: 86948 -/* 44129 */ MCD_OPC_Decode, 136, 31, 147, 2, // Opcode: UADALPv16i8_v8i16 -/* 44134 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 44149 -/* 44139 */ MCD_OPC_CheckPredicate, 3, 52, 167, 0, // Skip to: 86948 -/* 44144 */ MCD_OPC_Decode, 248, 30, 133, 2, // Opcode: UABDLv16i8_v8i16 -/* 44149 */ MCD_OPC_FilterValue, 15, 42, 167, 0, // Skip to: 86948 -/* 44154 */ MCD_OPC_CheckPredicate, 3, 37, 167, 0, // Skip to: 86948 -/* 44159 */ MCD_OPC_CheckField, 16, 5, 0, 30, 167, 0, // Skip to: 86948 -/* 44166 */ MCD_OPC_Decode, 147, 25, 138, 2, // Opcode: SQNEGv16i8 -/* 44171 */ MCD_OPC_FilterValue, 1, 20, 167, 0, // Skip to: 86948 -/* 44176 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... -/* 44179 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 44201 -/* 44184 */ MCD_OPC_CheckPredicate, 3, 7, 167, 0, // Skip to: 86948 -/* 44189 */ MCD_OPC_CheckField, 21, 1, 1, 0, 167, 0, // Skip to: 86948 -/* 44196 */ MCD_OPC_Decode, 163, 32, 141, 2, // Opcode: UMLALv16i8_v8i16 -/* 44201 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 44239 -/* 44206 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 44209 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 44224 -/* 44214 */ MCD_OPC_CheckPredicate, 3, 233, 166, 0, // Skip to: 86948 -/* 44219 */ MCD_OPC_Decode, 199, 3, 138, 2, // Opcode: CMGEv16i8rz -/* 44224 */ MCD_OPC_FilterValue, 33, 223, 166, 0, // Skip to: 86948 -/* 44229 */ MCD_OPC_CheckPredicate, 3, 218, 166, 0, // Skip to: 86948 -/* 44234 */ MCD_OPC_Decode, 233, 11, 138, 2, // Opcode: FRINTAv4f32 -/* 44239 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 44277 -/* 44244 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 44247 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 44262 -/* 44252 */ MCD_OPC_CheckPredicate, 3, 195, 166, 0, // Skip to: 86948 -/* 44257 */ MCD_OPC_Decode, 246, 3, 138, 2, // Opcode: CMLEv16i8rz -/* 44262 */ MCD_OPC_FilterValue, 33, 185, 166, 0, // Skip to: 86948 -/* 44267 */ MCD_OPC_CheckPredicate, 3, 180, 166, 0, // Skip to: 86948 -/* 44272 */ MCD_OPC_Decode, 160, 12, 138, 2, // Opcode: FRINTXv4f32 -/* 44277 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 44299 -/* 44282 */ MCD_OPC_CheckPredicate, 3, 165, 166, 0, // Skip to: 86948 -/* 44287 */ MCD_OPC_CheckField, 21, 1, 1, 158, 166, 0, // Skip to: 86948 -/* 44294 */ MCD_OPC_Decode, 173, 32, 141, 2, // Opcode: UMLSLv16i8_v8i16 -/* 44299 */ MCD_OPC_FilterValue, 5, 48, 0, 0, // Skip to: 44352 -/* 44304 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 44307 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 44322 -/* 44312 */ MCD_OPC_CheckPredicate, 3, 135, 166, 0, // Skip to: 86948 -/* 44317 */ MCD_OPC_Decode, 179, 8, 138, 2, // Opcode: FCVTNUv4f32 -/* 44322 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 44337 -/* 44327 */ MCD_OPC_CheckPredicate, 3, 120, 166, 0, // Skip to: 86948 -/* 44332 */ MCD_OPC_Decode, 243, 31, 158, 2, // Opcode: UMAXVv16i8v -/* 44337 */ MCD_OPC_FilterValue, 49, 110, 166, 0, // Skip to: 86948 -/* 44342 */ MCD_OPC_CheckPredicate, 3, 105, 166, 0, // Skip to: 86948 -/* 44347 */ MCD_OPC_Decode, 144, 32, 158, 2, // Opcode: UMINVv16i8v -/* 44352 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 44390 -/* 44357 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 44360 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 44375 -/* 44365 */ MCD_OPC_CheckPredicate, 3, 82, 166, 0, // Skip to: 86948 -/* 44370 */ MCD_OPC_Decode, 179, 20, 138, 2, // Opcode: NEGv16i8 -/* 44375 */ MCD_OPC_FilterValue, 33, 72, 166, 0, // Skip to: 86948 -/* 44380 */ MCD_OPC_CheckPredicate, 3, 67, 166, 0, // Skip to: 86948 -/* 44385 */ MCD_OPC_Decode, 151, 8, 138, 2, // Opcode: FCVTMUv4f32 -/* 44390 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 44412 -/* 44395 */ MCD_OPC_CheckPredicate, 3, 52, 166, 0, // Skip to: 86948 -/* 44400 */ MCD_OPC_CheckField, 21, 1, 1, 45, 166, 0, // Skip to: 86948 -/* 44407 */ MCD_OPC_Decode, 193, 32, 133, 2, // Opcode: UMULLv16i8_v8i16 -/* 44412 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 44450 -/* 44417 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 44420 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 44435 -/* 44425 */ MCD_OPC_CheckPredicate, 3, 22, 166, 0, // Skip to: 86948 -/* 44430 */ MCD_OPC_Decode, 243, 7, 138, 2, // Opcode: FCVTAUv4f32 -/* 44435 */ MCD_OPC_FilterValue, 48, 12, 166, 0, // Skip to: 86948 -/* 44440 */ MCD_OPC_CheckPredicate, 3, 7, 166, 0, // Skip to: 86948 -/* 44445 */ MCD_OPC_Decode, 210, 9, 160, 2, // Opcode: FMAXNMVv4i32v -/* 44450 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 44472 -/* 44455 */ MCD_OPC_CheckPredicate, 3, 248, 165, 0, // Skip to: 86948 -/* 44460 */ MCD_OPC_CheckField, 16, 6, 33, 241, 165, 0, // Skip to: 86948 -/* 44467 */ MCD_OPC_Decode, 201, 31, 138, 2, // Opcode: UCVTFv4f32 -/* 44472 */ MCD_OPC_FilterValue, 15, 231, 165, 0, // Skip to: 86948 -/* 44477 */ MCD_OPC_CheckPredicate, 3, 226, 165, 0, // Skip to: 86948 -/* 44482 */ MCD_OPC_CheckField, 16, 6, 48, 219, 165, 0, // Skip to: 86948 -/* 44489 */ MCD_OPC_Decode, 236, 9, 160, 2, // Opcode: FMAXVv4i32v -/* 44494 */ MCD_OPC_FilterValue, 1, 209, 165, 0, // Skip to: 86948 -/* 44499 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 44502 */ MCD_OPC_FilterValue, 0, 86, 1, 0, // Skip to: 44849 -/* 44507 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 44510 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 44601 -/* 44515 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 44518 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 44586 -/* 44523 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 44526 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 44571 -/* 44531 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 44534 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 44556 -/* 44539 */ MCD_OPC_CheckPredicate, 3, 164, 165, 0, // Skip to: 86948 -/* 44544 */ MCD_OPC_CheckField, 19, 1, 1, 157, 165, 0, // Skip to: 86948 -/* 44551 */ MCD_OPC_Decode, 159, 14, 161, 2, // Opcode: INSvi64lane -/* 44556 */ MCD_OPC_FilterValue, 1, 147, 165, 0, // Skip to: 86948 -/* 44561 */ MCD_OPC_CheckPredicate, 3, 142, 165, 0, // Skip to: 86948 -/* 44566 */ MCD_OPC_Decode, 157, 14, 162, 2, // Opcode: INSvi32lane -/* 44571 */ MCD_OPC_FilterValue, 1, 132, 165, 0, // Skip to: 86948 -/* 44576 */ MCD_OPC_CheckPredicate, 3, 127, 165, 0, // Skip to: 86948 -/* 44581 */ MCD_OPC_Decode, 155, 14, 163, 2, // Opcode: INSvi16lane -/* 44586 */ MCD_OPC_FilterValue, 1, 117, 165, 0, // Skip to: 86948 -/* 44591 */ MCD_OPC_CheckPredicate, 3, 112, 165, 0, // Skip to: 86948 -/* 44596 */ MCD_OPC_Decode, 161, 14, 164, 2, // Opcode: INSvi8lane -/* 44601 */ MCD_OPC_FilterValue, 1, 102, 165, 0, // Skip to: 86948 -/* 44606 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... -/* 44609 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 44624 -/* 44614 */ MCD_OPC_CheckPredicate, 3, 89, 165, 0, // Skip to: 86948 -/* 44619 */ MCD_OPC_Decode, 220, 31, 133, 2, // Opcode: UHADDv16i8 -/* 44624 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 44639 -/* 44629 */ MCD_OPC_CheckPredicate, 3, 74, 165, 0, // Skip to: 86948 -/* 44634 */ MCD_OPC_Decode, 211, 32, 133, 2, // Opcode: UQADDv16i8 -/* 44639 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 44654 -/* 44644 */ MCD_OPC_CheckPredicate, 3, 59, 165, 0, // Skip to: 86948 -/* 44649 */ MCD_OPC_Decode, 219, 33, 133, 2, // Opcode: URHADDv16i8 -/* 44654 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 44669 -/* 44659 */ MCD_OPC_CheckPredicate, 3, 44, 165, 0, // Skip to: 86948 -/* 44664 */ MCD_OPC_Decode, 245, 5, 133, 2, // Opcode: EORv16i8 -/* 44669 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 44684 -/* 44674 */ MCD_OPC_CheckPredicate, 3, 29, 165, 0, // Skip to: 86948 -/* 44679 */ MCD_OPC_Decode, 226, 31, 133, 2, // Opcode: UHSUBv16i8 -/* 44684 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 44699 -/* 44689 */ MCD_OPC_CheckPredicate, 3, 14, 165, 0, // Skip to: 86948 -/* 44694 */ MCD_OPC_Decode, 197, 33, 133, 2, // Opcode: UQSUBv16i8 -/* 44699 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 44714 -/* 44704 */ MCD_OPC_CheckPredicate, 3, 255, 164, 0, // Skip to: 86948 -/* 44709 */ MCD_OPC_Decode, 230, 3, 133, 2, // Opcode: CMHIv16i8 -/* 44714 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 44729 -/* 44719 */ MCD_OPC_CheckPredicate, 3, 240, 164, 0, // Skip to: 86948 -/* 44724 */ MCD_OPC_Decode, 238, 3, 133, 2, // Opcode: CMHSv16i8 -/* 44729 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 44744 -/* 44734 */ MCD_OPC_CheckPredicate, 3, 225, 164, 0, // Skip to: 86948 -/* 44739 */ MCD_OPC_Decode, 129, 34, 133, 2, // Opcode: USHLv16i8 -/* 44744 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 44759 -/* 44749 */ MCD_OPC_CheckPredicate, 3, 210, 164, 0, // Skip to: 86948 -/* 44754 */ MCD_OPC_Decode, 162, 33, 133, 2, // Opcode: UQSHLv16i8 -/* 44759 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 44774 -/* 44764 */ MCD_OPC_CheckPredicate, 3, 195, 164, 0, // Skip to: 86948 -/* 44769 */ MCD_OPC_Decode, 225, 33, 133, 2, // Opcode: URSHLv16i8 -/* 44774 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 44789 -/* 44779 */ MCD_OPC_CheckPredicate, 3, 180, 164, 0, // Skip to: 86948 -/* 44784 */ MCD_OPC_Decode, 138, 33, 133, 2, // Opcode: UQRSHLv16i8 -/* 44789 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 44804 -/* 44794 */ MCD_OPC_CheckPredicate, 3, 165, 164, 0, // Skip to: 86948 -/* 44799 */ MCD_OPC_Decode, 128, 32, 133, 2, // Opcode: UMAXv16i8 -/* 44804 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 44819 -/* 44809 */ MCD_OPC_CheckPredicate, 3, 150, 164, 0, // Skip to: 86948 -/* 44814 */ MCD_OPC_Decode, 157, 32, 133, 2, // Opcode: UMINv16i8 -/* 44819 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 44834 -/* 44824 */ MCD_OPC_CheckPredicate, 3, 135, 164, 0, // Skip to: 86948 -/* 44829 */ MCD_OPC_Decode, 130, 31, 133, 2, // Opcode: UABDv16i8 -/* 44834 */ MCD_OPC_FilterValue, 15, 125, 164, 0, // Skip to: 86948 -/* 44839 */ MCD_OPC_CheckPredicate, 3, 120, 164, 0, // Skip to: 86948 -/* 44844 */ MCD_OPC_Decode, 242, 30, 141, 2, // Opcode: UABAv16i8 -/* 44849 */ MCD_OPC_FilterValue, 1, 110, 164, 0, // Skip to: 86948 -/* 44854 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... -/* 44857 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 44879 -/* 44862 */ MCD_OPC_CheckPredicate, 3, 97, 164, 0, // Skip to: 86948 -/* 44867 */ MCD_OPC_CheckField, 21, 1, 1, 90, 164, 0, // Skip to: 86948 -/* 44874 */ MCD_OPC_Decode, 255, 29, 133, 2, // Opcode: SUBv16i8 -/* 44879 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 44901 -/* 44884 */ MCD_OPC_CheckPredicate, 3, 75, 164, 0, // Skip to: 86948 -/* 44889 */ MCD_OPC_CheckField, 21, 1, 1, 68, 164, 0, // Skip to: 86948 -/* 44896 */ MCD_OPC_Decode, 182, 3, 133, 2, // Opcode: CMEQv16i8 -/* 44901 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 44923 -/* 44906 */ MCD_OPC_CheckPredicate, 3, 53, 164, 0, // Skip to: 86948 -/* 44911 */ MCD_OPC_CheckField, 21, 1, 1, 46, 164, 0, // Skip to: 86948 -/* 44918 */ MCD_OPC_Decode, 223, 19, 141, 2, // Opcode: MLSv16i8 -/* 44923 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 44945 -/* 44928 */ MCD_OPC_CheckPredicate, 3, 31, 164, 0, // Skip to: 86948 -/* 44933 */ MCD_OPC_CheckField, 21, 1, 1, 24, 164, 0, // Skip to: 86948 -/* 44940 */ MCD_OPC_Decode, 247, 20, 133, 2, // Opcode: PMULv16i8 -/* 44945 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 44967 -/* 44950 */ MCD_OPC_CheckPredicate, 3, 9, 164, 0, // Skip to: 86948 -/* 44955 */ MCD_OPC_CheckField, 21, 1, 1, 2, 164, 0, // Skip to: 86948 -/* 44962 */ MCD_OPC_Decode, 233, 31, 133, 2, // Opcode: UMAXPv16i8 -/* 44967 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 44989 -/* 44972 */ MCD_OPC_CheckPredicate, 3, 243, 163, 0, // Skip to: 86948 -/* 44977 */ MCD_OPC_CheckField, 21, 1, 1, 236, 163, 0, // Skip to: 86948 -/* 44984 */ MCD_OPC_Decode, 134, 32, 133, 2, // Opcode: UMINPv16i8 -/* 44989 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 45011 -/* 44994 */ MCD_OPC_CheckPredicate, 3, 221, 163, 0, // Skip to: 86948 -/* 44999 */ MCD_OPC_CheckField, 21, 1, 1, 214, 163, 0, // Skip to: 86948 -/* 45006 */ MCD_OPC_Decode, 203, 9, 133, 2, // Opcode: FMAXNMPv4f32 -/* 45011 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 45033 -/* 45016 */ MCD_OPC_CheckPredicate, 3, 199, 163, 0, // Skip to: 86948 -/* 45021 */ MCD_OPC_CheckField, 21, 1, 1, 192, 163, 0, // Skip to: 86948 -/* 45028 */ MCD_OPC_Decode, 183, 6, 133, 2, // Opcode: FADDPv4f32 -/* 45033 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 45055 -/* 45038 */ MCD_OPC_CheckPredicate, 3, 177, 163, 0, // Skip to: 86948 -/* 45043 */ MCD_OPC_CheckField, 21, 1, 1, 170, 163, 0, // Skip to: 86948 -/* 45050 */ MCD_OPC_Decode, 159, 11, 133, 2, // Opcode: FMULv4f32 -/* 45055 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 45077 -/* 45060 */ MCD_OPC_CheckPredicate, 3, 155, 163, 0, // Skip to: 86948 -/* 45065 */ MCD_OPC_CheckField, 21, 1, 1, 148, 163, 0, // Skip to: 86948 -/* 45072 */ MCD_OPC_Decode, 128, 7, 133, 2, // Opcode: FCMGEv4f32 -/* 45077 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 45099 -/* 45082 */ MCD_OPC_CheckPredicate, 3, 133, 163, 0, // Skip to: 86948 -/* 45087 */ MCD_OPC_CheckField, 21, 1, 1, 126, 163, 0, // Skip to: 86948 -/* 45094 */ MCD_OPC_Decode, 159, 6, 133, 2, // Opcode: FACGEv4f32 -/* 45099 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 45121 -/* 45104 */ MCD_OPC_CheckPredicate, 3, 111, 163, 0, // Skip to: 86948 -/* 45109 */ MCD_OPC_CheckField, 21, 1, 1, 104, 163, 0, // Skip to: 86948 -/* 45116 */ MCD_OPC_Decode, 229, 9, 133, 2, // Opcode: FMAXPv4f32 -/* 45121 */ MCD_OPC_FilterValue, 15, 94, 163, 0, // Skip to: 86948 -/* 45126 */ MCD_OPC_CheckPredicate, 3, 89, 163, 0, // Skip to: 86948 -/* 45131 */ MCD_OPC_CheckField, 21, 1, 1, 82, 163, 0, // Skip to: 86948 -/* 45138 */ MCD_OPC_Decode, 178, 9, 133, 2, // Opcode: FDIVv4f32 -/* 45143 */ MCD_OPC_FilterValue, 6, 72, 163, 0, // Skip to: 86948 -/* 45148 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45151 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 45173 -/* 45156 */ MCD_OPC_CheckPredicate, 6, 59, 163, 0, // Skip to: 86948 -/* 45161 */ MCD_OPC_CheckField, 15, 1, 0, 52, 163, 0, // Skip to: 86948 -/* 45168 */ MCD_OPC_Decode, 226, 5, 165, 2, // Opcode: EOR3 -/* 45173 */ MCD_OPC_FilterValue, 1, 42, 163, 0, // Skip to: 86948 -/* 45178 */ MCD_OPC_CheckPredicate, 6, 37, 163, 0, // Skip to: 86948 -/* 45183 */ MCD_OPC_CheckField, 15, 1, 0, 30, 163, 0, // Skip to: 86948 -/* 45190 */ MCD_OPC_Decode, 169, 2, 165, 2, // Opcode: BCAX -/* 45195 */ MCD_OPC_FilterValue, 9, 131, 26, 0, // Skip to: 51987 -/* 45200 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 45203 */ MCD_OPC_FilterValue, 0, 4, 6, 0, // Skip to: 46748 -/* 45208 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 45211 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 45233 -/* 45216 */ MCD_OPC_CheckPredicate, 3, 255, 162, 0, // Skip to: 86948 -/* 45221 */ MCD_OPC_CheckField, 21, 1, 1, 248, 162, 0, // Skip to: 86948 -/* 45228 */ MCD_OPC_Decode, 165, 22, 234, 1, // Opcode: SADDLv4i16_v4i32 -/* 45233 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 45271 -/* 45238 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45241 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45256 -/* 45246 */ MCD_OPC_CheckPredicate, 4, 225, 162, 0, // Skip to: 86948 -/* 45251 */ MCD_OPC_Decode, 220, 9, 238, 1, // Opcode: FMAXNMv4f16 -/* 45256 */ MCD_OPC_FilterValue, 1, 215, 162, 0, // Skip to: 86948 -/* 45261 */ MCD_OPC_CheckPredicate, 3, 210, 162, 0, // Skip to: 86948 -/* 45266 */ MCD_OPC_Decode, 129, 23, 238, 1, // Opcode: SHADDv4i16 -/* 45271 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 45293 -/* 45276 */ MCD_OPC_CheckPredicate, 3, 195, 162, 0, // Skip to: 86948 -/* 45281 */ MCD_OPC_CheckField, 16, 6, 32, 188, 162, 0, // Skip to: 86948 -/* 45288 */ MCD_OPC_Decode, 211, 21, 239, 1, // Opcode: REV64v4i16 -/* 45293 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 45331 -/* 45298 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45301 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45316 -/* 45306 */ MCD_OPC_CheckPredicate, 4, 165, 162, 0, // Skip to: 86948 -/* 45311 */ MCD_OPC_Decode, 190, 10, 130, 2, // Opcode: FMLAv4f16 -/* 45316 */ MCD_OPC_FilterValue, 1, 155, 162, 0, // Skip to: 86948 -/* 45321 */ MCD_OPC_CheckPredicate, 3, 150, 162, 0, // Skip to: 86948 -/* 45326 */ MCD_OPC_Decode, 179, 24, 238, 1, // Opcode: SQADDv4i16 -/* 45331 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 45353 -/* 45336 */ MCD_OPC_CheckPredicate, 3, 135, 162, 0, // Skip to: 86948 -/* 45341 */ MCD_OPC_CheckField, 21, 1, 1, 128, 162, 0, // Skip to: 86948 -/* 45348 */ MCD_OPC_Decode, 174, 22, 242, 1, // Opcode: SADDWv4i16_v4i32 -/* 45353 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 45391 -/* 45358 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45361 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45376 -/* 45366 */ MCD_OPC_CheckPredicate, 4, 105, 162, 0, // Skip to: 86948 -/* 45371 */ MCD_OPC_Decode, 200, 6, 238, 1, // Opcode: FADDv4f16 -/* 45376 */ MCD_OPC_FilterValue, 1, 95, 162, 0, // Skip to: 86948 -/* 45381 */ MCD_OPC_CheckPredicate, 3, 90, 162, 0, // Skip to: 86948 -/* 45386 */ MCD_OPC_Decode, 185, 26, 238, 1, // Opcode: SRHADDv4i16 -/* 45391 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 45413 -/* 45396 */ MCD_OPC_CheckPredicate, 3, 75, 162, 0, // Skip to: 86948 -/* 45401 */ MCD_OPC_CheckField, 21, 1, 0, 68, 162, 0, // Skip to: 86948 -/* 45408 */ MCD_OPC_Decode, 199, 34, 238, 1, // Opcode: UZP1v4i16 -/* 45413 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 45451 -/* 45418 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45421 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45436 -/* 45426 */ MCD_OPC_CheckPredicate, 4, 45, 162, 0, // Skip to: 86948 -/* 45431 */ MCD_OPC_Decode, 133, 11, 238, 1, // Opcode: FMULXv4f16 -/* 45436 */ MCD_OPC_FilterValue, 1, 35, 162, 0, // Skip to: 86948 -/* 45441 */ MCD_OPC_CheckPredicate, 3, 30, 162, 0, // Skip to: 86948 -/* 45446 */ MCD_OPC_Decode, 192, 2, 238, 1, // Opcode: BICv8i8 -/* 45451 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 45473 -/* 45456 */ MCD_OPC_CheckPredicate, 3, 15, 162, 0, // Skip to: 86948 -/* 45461 */ MCD_OPC_CheckField, 21, 1, 1, 8, 162, 0, // Skip to: 86948 -/* 45468 */ MCD_OPC_Decode, 163, 27, 234, 1, // Opcode: SSUBLv4i16_v4i32 -/* 45473 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 45511 -/* 45478 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45481 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45496 -/* 45486 */ MCD_OPC_CheckPredicate, 4, 241, 161, 0, // Skip to: 86948 -/* 45491 */ MCD_OPC_Decode, 233, 6, 238, 1, // Opcode: FCMEQv4f16 -/* 45496 */ MCD_OPC_FilterValue, 1, 231, 161, 0, // Skip to: 86948 -/* 45501 */ MCD_OPC_CheckPredicate, 3, 226, 161, 0, // Skip to: 86948 -/* 45506 */ MCD_OPC_Decode, 155, 23, 238, 1, // Opcode: SHSUBv4i16 -/* 45511 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 45572 -/* 45516 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45519 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45534 -/* 45524 */ MCD_OPC_CheckPredicate, 3, 203, 161, 0, // Skip to: 86948 -/* 45529 */ MCD_OPC_Decode, 216, 30, 238, 1, // Opcode: TRN1v4i16 -/* 45534 */ MCD_OPC_FilterValue, 1, 193, 161, 0, // Skip to: 86948 -/* 45539 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 45542 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45557 -/* 45547 */ MCD_OPC_CheckPredicate, 3, 180, 161, 0, // Skip to: 86948 -/* 45552 */ MCD_OPC_Decode, 154, 22, 239, 1, // Opcode: SADDLPv4i16_v2i32 -/* 45557 */ MCD_OPC_FilterValue, 1, 170, 161, 0, // Skip to: 86948 -/* 45562 */ MCD_OPC_CheckPredicate, 3, 165, 161, 0, // Skip to: 86948 -/* 45567 */ MCD_OPC_Decode, 129, 35, 244, 1, // Opcode: XTNv4i16 -/* 45572 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 45594 -/* 45577 */ MCD_OPC_CheckPredicate, 3, 150, 161, 0, // Skip to: 86948 -/* 45582 */ MCD_OPC_CheckField, 21, 1, 1, 143, 161, 0, // Skip to: 86948 -/* 45589 */ MCD_OPC_Decode, 161, 26, 238, 1, // Opcode: SQSUBv4i16 -/* 45594 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 45616 -/* 45599 */ MCD_OPC_CheckPredicate, 3, 128, 161, 0, // Skip to: 86948 -/* 45604 */ MCD_OPC_CheckField, 21, 1, 1, 121, 161, 0, // Skip to: 86948 -/* 45611 */ MCD_OPC_Decode, 169, 27, 242, 1, // Opcode: SSUBWv4i16_v4i32 -/* 45616 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 45654 -/* 45621 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45624 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45639 -/* 45629 */ MCD_OPC_CheckPredicate, 4, 98, 161, 0, // Skip to: 86948 -/* 45634 */ MCD_OPC_Decode, 246, 9, 238, 1, // Opcode: FMAXv4f16 -/* 45639 */ MCD_OPC_FilterValue, 1, 88, 161, 0, // Skip to: 86948 -/* 45644 */ MCD_OPC_CheckPredicate, 3, 83, 161, 0, // Skip to: 86948 -/* 45649 */ MCD_OPC_Decode, 222, 3, 238, 1, // Opcode: CMGTv4i16 -/* 45654 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 45715 -/* 45659 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45662 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45677 -/* 45667 */ MCD_OPC_CheckPredicate, 3, 60, 161, 0, // Skip to: 86948 -/* 45672 */ MCD_OPC_Decode, 144, 35, 238, 1, // Opcode: ZIP1v4i16 -/* 45677 */ MCD_OPC_FilterValue, 1, 50, 161, 0, // Skip to: 86948 -/* 45682 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 45685 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45700 -/* 45690 */ MCD_OPC_CheckPredicate, 3, 37, 161, 0, // Skip to: 86948 -/* 45695 */ MCD_OPC_Decode, 148, 30, 248, 1, // Opcode: SUQADDv4i16 -/* 45700 */ MCD_OPC_FilterValue, 16, 27, 161, 0, // Skip to: 86948 -/* 45705 */ MCD_OPC_CheckPredicate, 3, 22, 161, 0, // Skip to: 86948 -/* 45710 */ MCD_OPC_Decode, 159, 22, 166, 2, // Opcode: SADDLVv4i16v -/* 45715 */ MCD_OPC_FilterValue, 15, 33, 0, 0, // Skip to: 45753 -/* 45720 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45723 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45738 -/* 45728 */ MCD_OPC_CheckPredicate, 4, 255, 160, 0, // Skip to: 86948 -/* 45733 */ MCD_OPC_Decode, 215, 11, 238, 1, // Opcode: FRECPSv4f16 -/* 45738 */ MCD_OPC_FilterValue, 1, 245, 160, 0, // Skip to: 86948 -/* 45743 */ MCD_OPC_CheckPredicate, 3, 240, 160, 0, // Skip to: 86948 -/* 45748 */ MCD_OPC_Decode, 206, 3, 238, 1, // Opcode: CMGEv4i16 -/* 45753 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 45775 -/* 45758 */ MCD_OPC_CheckPredicate, 3, 225, 160, 0, // Skip to: 86948 -/* 45763 */ MCD_OPC_CheckField, 21, 1, 1, 218, 160, 0, // Skip to: 86948 -/* 45770 */ MCD_OPC_Decode, 144, 1, 252, 1, // Opcode: ADDHNv4i32_v4i16 -/* 45775 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 45797 -/* 45780 */ MCD_OPC_CheckPredicate, 3, 203, 160, 0, // Skip to: 86948 -/* 45785 */ MCD_OPC_CheckField, 21, 1, 1, 196, 160, 0, // Skip to: 86948 -/* 45792 */ MCD_OPC_Decode, 231, 26, 238, 1, // Opcode: SSHLv4i16 -/* 45797 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 45835 -/* 45802 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 45805 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 45820 -/* 45810 */ MCD_OPC_CheckPredicate, 3, 173, 160, 0, // Skip to: 86948 -/* 45815 */ MCD_OPC_Decode, 166, 3, 239, 1, // Opcode: CLSv4i16 -/* 45820 */ MCD_OPC_FilterValue, 33, 163, 160, 0, // Skip to: 86948 -/* 45825 */ MCD_OPC_CheckPredicate, 3, 158, 160, 0, // Skip to: 86948 -/* 45830 */ MCD_OPC_Decode, 170, 26, 244, 1, // Opcode: SQXTNv4i16 -/* 45835 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 45857 -/* 45840 */ MCD_OPC_CheckPredicate, 3, 143, 160, 0, // Skip to: 86948 -/* 45845 */ MCD_OPC_CheckField, 21, 1, 1, 136, 160, 0, // Skip to: 86948 -/* 45852 */ MCD_OPC_Decode, 248, 25, 238, 1, // Opcode: SQSHLv4i16 -/* 45857 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 45879 -/* 45862 */ MCD_OPC_CheckPredicate, 3, 121, 160, 0, // Skip to: 86948 -/* 45867 */ MCD_OPC_CheckField, 21, 1, 1, 114, 160, 0, // Skip to: 86948 -/* 45874 */ MCD_OPC_Decode, 248, 21, 254, 1, // Opcode: SABALv4i16_v4i32 -/* 45879 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 45901 -/* 45884 */ MCD_OPC_CheckPredicate, 3, 99, 160, 0, // Skip to: 86948 -/* 45889 */ MCD_OPC_CheckField, 21, 1, 1, 92, 160, 0, // Skip to: 86948 -/* 45896 */ MCD_OPC_Decode, 201, 26, 238, 1, // Opcode: SRSHLv4i16 -/* 45901 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 45923 -/* 45906 */ MCD_OPC_CheckPredicate, 3, 77, 160, 0, // Skip to: 86948 -/* 45911 */ MCD_OPC_CheckField, 21, 1, 0, 70, 160, 0, // Skip to: 86948 -/* 45918 */ MCD_OPC_Decode, 214, 34, 238, 1, // Opcode: UZP2v4i16 -/* 45923 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 45945 -/* 45928 */ MCD_OPC_CheckPredicate, 3, 55, 160, 0, // Skip to: 86948 -/* 45933 */ MCD_OPC_CheckField, 21, 1, 1, 48, 160, 0, // Skip to: 86948 -/* 45940 */ MCD_OPC_Decode, 201, 25, 238, 1, // Opcode: SQRSHLv4i16 -/* 45945 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 45967 -/* 45950 */ MCD_OPC_CheckPredicate, 3, 33, 160, 0, // Skip to: 86948 -/* 45955 */ MCD_OPC_CheckField, 21, 1, 1, 26, 160, 0, // Skip to: 86948 -/* 45962 */ MCD_OPC_Decode, 213, 29, 252, 1, // Opcode: SUBHNv4i32_v4i16 -/* 45967 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 45989 -/* 45972 */ MCD_OPC_CheckPredicate, 3, 11, 160, 0, // Skip to: 86948 -/* 45977 */ MCD_OPC_CheckField, 21, 1, 1, 4, 160, 0, // Skip to: 86948 -/* 45984 */ MCD_OPC_Decode, 202, 23, 238, 1, // Opcode: SMAXv4i16 -/* 45989 */ MCD_OPC_FilterValue, 26, 56, 0, 0, // Skip to: 46050 -/* 45994 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 45997 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46012 -/* 46002 */ MCD_OPC_CheckPredicate, 3, 237, 159, 0, // Skip to: 86948 -/* 46007 */ MCD_OPC_Decode, 231, 30, 238, 1, // Opcode: TRN2v4i16 -/* 46012 */ MCD_OPC_FilterValue, 1, 227, 159, 0, // Skip to: 86948 -/* 46017 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 46020 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46035 -/* 46025 */ MCD_OPC_CheckPredicate, 3, 214, 159, 0, // Skip to: 86948 -/* 46030 */ MCD_OPC_Decode, 148, 22, 248, 1, // Opcode: SADALPv4i16_v2i32 -/* 46035 */ MCD_OPC_FilterValue, 1, 204, 159, 0, // Skip to: 86948 -/* 46040 */ MCD_OPC_CheckPredicate, 3, 199, 159, 0, // Skip to: 86948 -/* 46045 */ MCD_OPC_Decode, 181, 8, 244, 1, // Opcode: FCVTNv2i32 -/* 46050 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 46072 -/* 46055 */ MCD_OPC_CheckPredicate, 3, 184, 159, 0, // Skip to: 86948 -/* 46060 */ MCD_OPC_CheckField, 21, 1, 1, 177, 159, 0, // Skip to: 86948 -/* 46067 */ MCD_OPC_Decode, 232, 23, 238, 1, // Opcode: SMINv4i16 -/* 46072 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 46094 -/* 46077 */ MCD_OPC_CheckPredicate, 3, 162, 159, 0, // Skip to: 86948 -/* 46082 */ MCD_OPC_CheckField, 21, 1, 1, 155, 159, 0, // Skip to: 86948 -/* 46089 */ MCD_OPC_Decode, 132, 22, 234, 1, // Opcode: SABDLv4i16_v4i32 -/* 46094 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 46116 -/* 46099 */ MCD_OPC_CheckPredicate, 3, 140, 159, 0, // Skip to: 86948 -/* 46104 */ MCD_OPC_CheckField, 21, 1, 1, 133, 159, 0, // Skip to: 86948 -/* 46111 */ MCD_OPC_Decode, 142, 22, 238, 1, // Opcode: SABDv4i16 -/* 46116 */ MCD_OPC_FilterValue, 30, 56, 0, 0, // Skip to: 46177 -/* 46121 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 46124 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46139 -/* 46129 */ MCD_OPC_CheckPredicate, 3, 110, 159, 0, // Skip to: 86948 -/* 46134 */ MCD_OPC_Decode, 159, 35, 238, 1, // Opcode: ZIP2v4i16 -/* 46139 */ MCD_OPC_FilterValue, 1, 100, 159, 0, // Skip to: 86948 -/* 46144 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 46147 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46162 -/* 46152 */ MCD_OPC_CheckPredicate, 3, 87, 159, 0, // Skip to: 86948 -/* 46157 */ MCD_OPC_Decode, 160, 24, 239, 1, // Opcode: SQABSv4i16 -/* 46162 */ MCD_OPC_FilterValue, 1, 77, 159, 0, // Skip to: 86948 -/* 46167 */ MCD_OPC_CheckPredicate, 3, 72, 159, 0, // Skip to: 86948 -/* 46172 */ MCD_OPC_Decode, 249, 7, 129, 2, // Opcode: FCVTLv2i32 -/* 46177 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 46199 -/* 46182 */ MCD_OPC_CheckPredicate, 3, 57, 159, 0, // Skip to: 86948 -/* 46187 */ MCD_OPC_CheckField, 21, 1, 1, 50, 159, 0, // Skip to: 86948 -/* 46194 */ MCD_OPC_Decode, 254, 21, 130, 2, // Opcode: SABAv4i16 -/* 46199 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 46221 -/* 46204 */ MCD_OPC_CheckPredicate, 3, 35, 159, 0, // Skip to: 86948 -/* 46209 */ MCD_OPC_CheckField, 21, 1, 1, 28, 159, 0, // Skip to: 86948 -/* 46216 */ MCD_OPC_Decode, 240, 23, 254, 1, // Opcode: SMLALv4i16_v4i32 -/* 46221 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 46243 -/* 46226 */ MCD_OPC_CheckPredicate, 3, 13, 159, 0, // Skip to: 86948 -/* 46231 */ MCD_OPC_CheckField, 21, 1, 1, 6, 159, 0, // Skip to: 86948 -/* 46238 */ MCD_OPC_Decode, 198, 1, 238, 1, // Opcode: ADDv4i16 -/* 46243 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 46281 -/* 46248 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 46251 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46266 -/* 46256 */ MCD_OPC_CheckPredicate, 3, 239, 158, 0, // Skip to: 86948 -/* 46261 */ MCD_OPC_Decode, 223, 3, 239, 1, // Opcode: CMGTv4i16rz -/* 46266 */ MCD_OPC_FilterValue, 57, 229, 158, 0, // Skip to: 86948 -/* 46271 */ MCD_OPC_CheckPredicate, 4, 224, 158, 0, // Skip to: 86948 -/* 46276 */ MCD_OPC_Decode, 137, 12, 239, 1, // Opcode: FRINTNv4f16 -/* 46281 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 46303 -/* 46286 */ MCD_OPC_CheckPredicate, 3, 209, 158, 0, // Skip to: 86948 -/* 46291 */ MCD_OPC_CheckField, 21, 1, 1, 202, 158, 0, // Skip to: 86948 -/* 46298 */ MCD_OPC_Decode, 237, 4, 238, 1, // Opcode: CMTSTv4i16 -/* 46303 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 46325 -/* 46308 */ MCD_OPC_CheckPredicate, 3, 187, 158, 0, // Skip to: 86948 -/* 46313 */ MCD_OPC_CheckField, 21, 1, 1, 180, 158, 0, // Skip to: 86948 -/* 46320 */ MCD_OPC_Decode, 212, 24, 254, 1, // Opcode: SQDMLALv4i16_v4i32 -/* 46325 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 46347 -/* 46330 */ MCD_OPC_CheckPredicate, 3, 165, 158, 0, // Skip to: 86948 -/* 46335 */ MCD_OPC_CheckField, 21, 1, 1, 158, 158, 0, // Skip to: 86948 -/* 46342 */ MCD_OPC_Decode, 212, 19, 130, 2, // Opcode: MLAv4i16 -/* 46347 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 46385 -/* 46352 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 46355 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46370 -/* 46360 */ MCD_OPC_CheckPredicate, 3, 135, 158, 0, // Skip to: 86948 -/* 46365 */ MCD_OPC_Decode, 191, 3, 239, 1, // Opcode: CMEQv4i16rz -/* 46370 */ MCD_OPC_FilterValue, 57, 125, 158, 0, // Skip to: 86948 -/* 46375 */ MCD_OPC_CheckPredicate, 4, 120, 158, 0, // Skip to: 86948 -/* 46380 */ MCD_OPC_Decode, 254, 11, 239, 1, // Opcode: FRINTMv4f16 -/* 46385 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 46407 -/* 46390 */ MCD_OPC_CheckPredicate, 3, 105, 158, 0, // Skip to: 86948 -/* 46395 */ MCD_OPC_CheckField, 21, 1, 1, 98, 158, 0, // Skip to: 86948 -/* 46402 */ MCD_OPC_Decode, 160, 20, 238, 1, // Opcode: MULv4i16 -/* 46407 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 46429 -/* 46412 */ MCD_OPC_CheckPredicate, 3, 83, 158, 0, // Skip to: 86948 -/* 46417 */ MCD_OPC_CheckField, 21, 1, 1, 76, 158, 0, // Skip to: 86948 -/* 46424 */ MCD_OPC_Decode, 250, 23, 254, 1, // Opcode: SMLSLv4i16_v4i32 -/* 46429 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 46451 -/* 46434 */ MCD_OPC_CheckPredicate, 3, 61, 158, 0, // Skip to: 86948 -/* 46439 */ MCD_OPC_CheckField, 21, 1, 1, 54, 158, 0, // Skip to: 86948 -/* 46446 */ MCD_OPC_Decode, 179, 23, 238, 1, // Opcode: SMAXPv4i16 -/* 46451 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 46519 -/* 46456 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 46459 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46474 -/* 46464 */ MCD_OPC_CheckPredicate, 3, 31, 158, 0, // Skip to: 86948 -/* 46469 */ MCD_OPC_Decode, 130, 4, 239, 1, // Opcode: CMLTv4i16rz -/* 46474 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 46489 -/* 46479 */ MCD_OPC_CheckPredicate, 3, 16, 158, 0, // Skip to: 86948 -/* 46484 */ MCD_OPC_Decode, 188, 23, 249, 1, // Opcode: SMAXVv4i16v -/* 46489 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 46504 -/* 46494 */ MCD_OPC_CheckPredicate, 3, 1, 158, 0, // Skip to: 86948 -/* 46499 */ MCD_OPC_Decode, 218, 23, 249, 1, // Opcode: SMINVv4i16v -/* 46504 */ MCD_OPC_FilterValue, 57, 247, 157, 0, // Skip to: 86948 -/* 46509 */ MCD_OPC_CheckPredicate, 4, 242, 157, 0, // Skip to: 86948 -/* 46514 */ MCD_OPC_Decode, 164, 8, 239, 1, // Opcode: FCVTNSv4f16 -/* 46519 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 46541 -/* 46524 */ MCD_OPC_CheckPredicate, 3, 227, 157, 0, // Skip to: 86948 -/* 46529 */ MCD_OPC_CheckField, 21, 1, 1, 220, 157, 0, // Skip to: 86948 -/* 46536 */ MCD_OPC_Decode, 209, 23, 238, 1, // Opcode: SMINPv4i16 -/* 46541 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 46563 -/* 46546 */ MCD_OPC_CheckPredicate, 3, 205, 157, 0, // Skip to: 86948 -/* 46551 */ MCD_OPC_CheckField, 21, 1, 1, 198, 157, 0, // Skip to: 86948 -/* 46558 */ MCD_OPC_Decode, 224, 24, 254, 1, // Opcode: SQDMLSLv4i16_v4i32 -/* 46563 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 46585 -/* 46568 */ MCD_OPC_CheckPredicate, 3, 183, 157, 0, // Skip to: 86948 -/* 46573 */ MCD_OPC_CheckField, 21, 1, 1, 176, 157, 0, // Skip to: 86948 -/* 46580 */ MCD_OPC_Decode, 235, 24, 238, 1, // Opcode: SQDMULHv4i16 -/* 46585 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 46638 -/* 46590 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 46593 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46608 -/* 46598 */ MCD_OPC_CheckPredicate, 3, 153, 157, 0, // Skip to: 86948 -/* 46603 */ MCD_OPC_Decode, 134, 1, 239, 1, // Opcode: ABSv4i16 -/* 46608 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 46623 -/* 46613 */ MCD_OPC_CheckPredicate, 3, 138, 157, 0, // Skip to: 86948 -/* 46618 */ MCD_OPC_Decode, 168, 1, 249, 1, // Opcode: ADDVv4i16v -/* 46623 */ MCD_OPC_FilterValue, 57, 128, 157, 0, // Skip to: 86948 -/* 46628 */ MCD_OPC_CheckPredicate, 4, 123, 157, 0, // Skip to: 86948 -/* 46633 */ MCD_OPC_Decode, 136, 8, 239, 1, // Opcode: FCVTMSv4f16 -/* 46638 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 46660 -/* 46643 */ MCD_OPC_CheckPredicate, 3, 108, 157, 0, // Skip to: 86948 -/* 46648 */ MCD_OPC_CheckField, 21, 1, 1, 101, 157, 0, // Skip to: 86948 -/* 46655 */ MCD_OPC_Decode, 153, 1, 238, 1, // Opcode: ADDPv4i16 -/* 46660 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 46682 -/* 46665 */ MCD_OPC_CheckPredicate, 3, 86, 157, 0, // Skip to: 86948 -/* 46670 */ MCD_OPC_CheckField, 21, 1, 1, 79, 157, 0, // Skip to: 86948 -/* 46677 */ MCD_OPC_Decode, 143, 24, 234, 1, // Opcode: SMULLv4i16_v4i32 -/* 46682 */ MCD_OPC_FilterValue, 50, 17, 0, 0, // Skip to: 46704 -/* 46687 */ MCD_OPC_CheckPredicate, 4, 64, 157, 0, // Skip to: 86948 -/* 46692 */ MCD_OPC_CheckField, 16, 6, 57, 57, 157, 0, // Skip to: 86948 -/* 46699 */ MCD_OPC_Decode, 228, 7, 239, 1, // Opcode: FCVTASv4f16 -/* 46704 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 46726 -/* 46709 */ MCD_OPC_CheckPredicate, 3, 42, 157, 0, // Skip to: 86948 -/* 46714 */ MCD_OPC_CheckField, 21, 1, 1, 35, 157, 0, // Skip to: 86948 -/* 46721 */ MCD_OPC_Decode, 248, 24, 234, 1, // Opcode: SQDMULLv4i16_v4i32 -/* 46726 */ MCD_OPC_FilterValue, 54, 25, 157, 0, // Skip to: 86948 -/* 46731 */ MCD_OPC_CheckPredicate, 4, 20, 157, 0, // Skip to: 86948 -/* 46736 */ MCD_OPC_CheckField, 16, 6, 57, 13, 157, 0, // Skip to: 86948 -/* 46743 */ MCD_OPC_Decode, 213, 22, 239, 1, // Opcode: SCVTFv4f16 -/* 46748 */ MCD_OPC_FilterValue, 1, 152, 5, 0, // Skip to: 48185 -/* 46753 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 46756 */ MCD_OPC_FilterValue, 0, 205, 0, 0, // Skip to: 46966 -/* 46761 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 46764 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 46786 -/* 46769 */ MCD_OPC_CheckPredicate, 3, 238, 156, 0, // Skip to: 86948 -/* 46774 */ MCD_OPC_CheckField, 21, 1, 1, 231, 156, 0, // Skip to: 86948 -/* 46781 */ MCD_OPC_Decode, 155, 31, 234, 1, // Opcode: UADDLv4i16_v4i32 -/* 46786 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 46824 -/* 46791 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 46794 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46809 -/* 46799 */ MCD_OPC_CheckPredicate, 4, 208, 156, 0, // Skip to: 86948 -/* 46804 */ MCD_OPC_Decode, 202, 9, 238, 1, // Opcode: FMAXNMPv4f16 -/* 46809 */ MCD_OPC_FilterValue, 1, 198, 156, 0, // Skip to: 86948 -/* 46814 */ MCD_OPC_CheckPredicate, 3, 193, 156, 0, // Skip to: 86948 -/* 46819 */ MCD_OPC_Decode, 222, 31, 238, 1, // Opcode: UHADDv4i16 -/* 46824 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 46846 -/* 46829 */ MCD_OPC_CheckPredicate, 3, 178, 156, 0, // Skip to: 86948 -/* 46834 */ MCD_OPC_CheckField, 16, 6, 32, 171, 156, 0, // Skip to: 86948 -/* 46841 */ MCD_OPC_Decode, 206, 21, 239, 1, // Opcode: REV32v4i16 -/* 46846 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 46868 -/* 46851 */ MCD_OPC_CheckPredicate, 3, 156, 156, 0, // Skip to: 86948 -/* 46856 */ MCD_OPC_CheckField, 21, 1, 1, 149, 156, 0, // Skip to: 86948 -/* 46863 */ MCD_OPC_Decode, 218, 32, 238, 1, // Opcode: UQADDv4i16 -/* 46868 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 46890 -/* 46873 */ MCD_OPC_CheckPredicate, 3, 134, 156, 0, // Skip to: 86948 -/* 46878 */ MCD_OPC_CheckField, 21, 1, 1, 127, 156, 0, // Skip to: 86948 -/* 46885 */ MCD_OPC_Decode, 165, 31, 242, 1, // Opcode: UADDWv4i16_v4i32 -/* 46890 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 46928 -/* 46895 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 46898 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46913 -/* 46903 */ MCD_OPC_CheckPredicate, 4, 104, 156, 0, // Skip to: 86948 -/* 46908 */ MCD_OPC_Decode, 182, 6, 238, 1, // Opcode: FADDPv4f16 -/* 46913 */ MCD_OPC_FilterValue, 1, 94, 156, 0, // Skip to: 86948 -/* 46918 */ MCD_OPC_CheckPredicate, 3, 89, 156, 0, // Skip to: 86948 -/* 46923 */ MCD_OPC_Decode, 221, 33, 238, 1, // Opcode: URHADDv4i16 -/* 46928 */ MCD_OPC_FilterValue, 7, 79, 156, 0, // Skip to: 86948 -/* 46933 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 46936 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46951 -/* 46941 */ MCD_OPC_CheckPredicate, 4, 66, 156, 0, // Skip to: 86948 -/* 46946 */ MCD_OPC_Decode, 158, 11, 238, 1, // Opcode: FMULv4f16 -/* 46951 */ MCD_OPC_FilterValue, 1, 56, 156, 0, // Skip to: 86948 -/* 46956 */ MCD_OPC_CheckPredicate, 3, 51, 156, 0, // Skip to: 86948 -/* 46961 */ MCD_OPC_Decode, 222, 2, 130, 2, // Opcode: BSLv8i8 -/* 46966 */ MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 47261 -/* 46971 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 46974 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 46996 -/* 46979 */ MCD_OPC_CheckPredicate, 3, 28, 156, 0, // Skip to: 86948 -/* 46984 */ MCD_OPC_CheckField, 21, 1, 1, 21, 156, 0, // Skip to: 86948 -/* 46991 */ MCD_OPC_Decode, 166, 34, 234, 1, // Opcode: USUBLv4i16_v4i32 -/* 46996 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 47034 -/* 47001 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 47004 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47019 -/* 47009 */ MCD_OPC_CheckPredicate, 4, 254, 155, 0, // Skip to: 86948 -/* 47014 */ MCD_OPC_Decode, 255, 6, 238, 1, // Opcode: FCMGEv4f16 -/* 47019 */ MCD_OPC_FilterValue, 1, 244, 155, 0, // Skip to: 86948 -/* 47024 */ MCD_OPC_CheckPredicate, 3, 239, 155, 0, // Skip to: 86948 -/* 47029 */ MCD_OPC_Decode, 228, 31, 238, 1, // Opcode: UHSUBv4i16 -/* 47034 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47072 -/* 47039 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 47042 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47057 -/* 47047 */ MCD_OPC_CheckPredicate, 3, 216, 155, 0, // Skip to: 86948 -/* 47052 */ MCD_OPC_Decode, 144, 31, 239, 1, // Opcode: UADDLPv4i16_v2i32 -/* 47057 */ MCD_OPC_FilterValue, 33, 206, 155, 0, // Skip to: 86948 -/* 47062 */ MCD_OPC_CheckPredicate, 3, 201, 155, 0, // Skip to: 86948 -/* 47067 */ MCD_OPC_Decode, 179, 26, 244, 1, // Opcode: SQXTUNv4i16 -/* 47072 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 47110 -/* 47077 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 47080 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47095 -/* 47085 */ MCD_OPC_CheckPredicate, 4, 178, 155, 0, // Skip to: 86948 -/* 47090 */ MCD_OPC_Decode, 158, 6, 238, 1, // Opcode: FACGEv4f16 -/* 47095 */ MCD_OPC_FilterValue, 1, 168, 155, 0, // Skip to: 86948 -/* 47100 */ MCD_OPC_CheckPredicate, 3, 163, 155, 0, // Skip to: 86948 -/* 47105 */ MCD_OPC_Decode, 204, 33, 238, 1, // Opcode: UQSUBv4i16 -/* 47110 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 47132 -/* 47115 */ MCD_OPC_CheckPredicate, 3, 148, 155, 0, // Skip to: 86948 -/* 47120 */ MCD_OPC_CheckField, 21, 1, 1, 141, 155, 0, // Skip to: 86948 -/* 47127 */ MCD_OPC_Decode, 172, 34, 242, 1, // Opcode: USUBWv4i16_v4i32 -/* 47132 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 47170 -/* 47137 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 47140 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47155 -/* 47145 */ MCD_OPC_CheckPredicate, 4, 118, 155, 0, // Skip to: 86948 -/* 47150 */ MCD_OPC_Decode, 228, 9, 238, 1, // Opcode: FMAXPv4f16 -/* 47155 */ MCD_OPC_FilterValue, 1, 108, 155, 0, // Skip to: 86948 -/* 47160 */ MCD_OPC_CheckPredicate, 3, 103, 155, 0, // Skip to: 86948 -/* 47165 */ MCD_OPC_Decode, 234, 3, 238, 1, // Opcode: CMHIv4i16 -/* 47170 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 47223 -/* 47175 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 47178 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47193 -/* 47183 */ MCD_OPC_CheckPredicate, 3, 80, 155, 0, // Skip to: 86948 -/* 47188 */ MCD_OPC_Decode, 152, 34, 248, 1, // Opcode: USQADDv4i16 -/* 47193 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 47208 -/* 47198 */ MCD_OPC_CheckPredicate, 3, 65, 155, 0, // Skip to: 86948 -/* 47203 */ MCD_OPC_Decode, 135, 23, 129, 2, // Opcode: SHLLv4i16 -/* 47208 */ MCD_OPC_FilterValue, 48, 55, 155, 0, // Skip to: 86948 -/* 47213 */ MCD_OPC_CheckPredicate, 3, 50, 155, 0, // Skip to: 86948 -/* 47218 */ MCD_OPC_Decode, 149, 31, 166, 2, // Opcode: UADDLVv4i16v -/* 47223 */ MCD_OPC_FilterValue, 7, 40, 155, 0, // Skip to: 86948 -/* 47228 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 47231 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47246 -/* 47236 */ MCD_OPC_CheckPredicate, 4, 27, 155, 0, // Skip to: 86948 -/* 47241 */ MCD_OPC_Decode, 177, 9, 238, 1, // Opcode: FDIVv4f16 -/* 47246 */ MCD_OPC_FilterValue, 1, 17, 155, 0, // Skip to: 86948 -/* 47251 */ MCD_OPC_CheckPredicate, 3, 12, 155, 0, // Skip to: 86948 -/* 47256 */ MCD_OPC_Decode, 242, 3, 238, 1, // Opcode: CMHSv4i16 -/* 47261 */ MCD_OPC_FilterValue, 2, 195, 0, 0, // Skip to: 47461 -/* 47266 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 47269 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47291 -/* 47274 */ MCD_OPC_CheckPredicate, 3, 245, 154, 0, // Skip to: 86948 -/* 47279 */ MCD_OPC_CheckField, 21, 1, 1, 238, 154, 0, // Skip to: 86948 -/* 47286 */ MCD_OPC_Decode, 179, 21, 252, 1, // Opcode: RADDHNv4i32_v4i16 -/* 47291 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47313 -/* 47296 */ MCD_OPC_CheckPredicate, 3, 223, 154, 0, // Skip to: 86948 -/* 47301 */ MCD_OPC_CheckField, 21, 1, 1, 216, 154, 0, // Skip to: 86948 -/* 47308 */ MCD_OPC_Decode, 133, 34, 238, 1, // Opcode: USHLv4i16 -/* 47313 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47351 -/* 47318 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 47321 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47336 -/* 47326 */ MCD_OPC_CheckPredicate, 3, 193, 154, 0, // Skip to: 86948 -/* 47331 */ MCD_OPC_Decode, 178, 3, 239, 1, // Opcode: CLZv4i16 -/* 47336 */ MCD_OPC_FilterValue, 33, 183, 154, 0, // Skip to: 86948 -/* 47341 */ MCD_OPC_CheckPredicate, 3, 178, 154, 0, // Skip to: 86948 -/* 47346 */ MCD_OPC_Decode, 213, 33, 244, 1, // Opcode: UQXTNv4i16 -/* 47351 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 47373 -/* 47356 */ MCD_OPC_CheckPredicate, 3, 163, 154, 0, // Skip to: 86948 -/* 47361 */ MCD_OPC_CheckField, 21, 1, 1, 156, 154, 0, // Skip to: 86948 -/* 47368 */ MCD_OPC_Decode, 172, 33, 238, 1, // Opcode: UQSHLv4i16 -/* 47373 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 47395 -/* 47378 */ MCD_OPC_CheckPredicate, 3, 141, 154, 0, // Skip to: 86948 -/* 47383 */ MCD_OPC_CheckField, 21, 1, 1, 134, 154, 0, // Skip to: 86948 -/* 47390 */ MCD_OPC_Decode, 238, 30, 254, 1, // Opcode: UABALv4i16_v4i32 -/* 47395 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 47417 -/* 47400 */ MCD_OPC_CheckPredicate, 3, 119, 154, 0, // Skip to: 86948 -/* 47405 */ MCD_OPC_CheckField, 21, 1, 1, 112, 154, 0, // Skip to: 86948 -/* 47412 */ MCD_OPC_Decode, 229, 33, 238, 1, // Opcode: URSHLv4i16 -/* 47417 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 47439 -/* 47422 */ MCD_OPC_CheckPredicate, 3, 97, 154, 0, // Skip to: 86948 -/* 47427 */ MCD_OPC_CheckField, 16, 6, 32, 90, 154, 0, // Skip to: 86948 -/* 47434 */ MCD_OPC_Decode, 191, 21, 239, 1, // Opcode: RBITv8i8 -/* 47439 */ MCD_OPC_FilterValue, 7, 80, 154, 0, // Skip to: 86948 -/* 47444 */ MCD_OPC_CheckPredicate, 3, 75, 154, 0, // Skip to: 86948 -/* 47449 */ MCD_OPC_CheckField, 21, 1, 1, 68, 154, 0, // Skip to: 86948 -/* 47456 */ MCD_OPC_Decode, 145, 33, 238, 1, // Opcode: UQRSHLv4i16 -/* 47461 */ MCD_OPC_FilterValue, 3, 195, 0, 0, // Skip to: 47661 -/* 47466 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 47469 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47491 -/* 47474 */ MCD_OPC_CheckPredicate, 3, 45, 154, 0, // Skip to: 86948 -/* 47479 */ MCD_OPC_CheckField, 21, 1, 1, 38, 154, 0, // Skip to: 86948 -/* 47486 */ MCD_OPC_Decode, 242, 21, 252, 1, // Opcode: RSUBHNv4i32_v4i16 -/* 47491 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47513 -/* 47496 */ MCD_OPC_CheckPredicate, 3, 23, 154, 0, // Skip to: 86948 -/* 47501 */ MCD_OPC_CheckField, 21, 1, 1, 16, 154, 0, // Skip to: 86948 -/* 47508 */ MCD_OPC_Decode, 130, 32, 238, 1, // Opcode: UMAXv4i16 -/* 47513 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47551 -/* 47518 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 47521 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47536 -/* 47526 */ MCD_OPC_CheckPredicate, 3, 249, 153, 0, // Skip to: 86948 -/* 47531 */ MCD_OPC_Decode, 138, 31, 248, 1, // Opcode: UADALPv4i16_v2i32 -/* 47536 */ MCD_OPC_FilterValue, 33, 239, 153, 0, // Skip to: 86948 -/* 47541 */ MCD_OPC_CheckPredicate, 3, 234, 153, 0, // Skip to: 86948 -/* 47546 */ MCD_OPC_Decode, 216, 8, 244, 1, // Opcode: FCVTXNv2f32 -/* 47551 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 47573 -/* 47556 */ MCD_OPC_CheckPredicate, 3, 219, 153, 0, // Skip to: 86948 -/* 47561 */ MCD_OPC_CheckField, 21, 1, 1, 212, 153, 0, // Skip to: 86948 -/* 47568 */ MCD_OPC_Decode, 159, 32, 238, 1, // Opcode: UMINv4i16 -/* 47573 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 47595 -/* 47578 */ MCD_OPC_CheckPredicate, 3, 197, 153, 0, // Skip to: 86948 -/* 47583 */ MCD_OPC_CheckField, 21, 1, 1, 190, 153, 0, // Skip to: 86948 -/* 47590 */ MCD_OPC_Decode, 250, 30, 234, 1, // Opcode: UABDLv4i16_v4i32 -/* 47595 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 47617 -/* 47600 */ MCD_OPC_CheckPredicate, 3, 175, 153, 0, // Skip to: 86948 -/* 47605 */ MCD_OPC_CheckField, 21, 1, 1, 168, 153, 0, // Skip to: 86948 -/* 47612 */ MCD_OPC_Decode, 132, 31, 238, 1, // Opcode: UABDv4i16 -/* 47617 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 47639 -/* 47622 */ MCD_OPC_CheckPredicate, 3, 153, 153, 0, // Skip to: 86948 -/* 47627 */ MCD_OPC_CheckField, 16, 6, 32, 146, 153, 0, // Skip to: 86948 -/* 47634 */ MCD_OPC_Decode, 154, 25, 239, 1, // Opcode: SQNEGv4i16 -/* 47639 */ MCD_OPC_FilterValue, 7, 136, 153, 0, // Skip to: 86948 -/* 47644 */ MCD_OPC_CheckPredicate, 3, 131, 153, 0, // Skip to: 86948 -/* 47649 */ MCD_OPC_CheckField, 21, 1, 1, 124, 153, 0, // Skip to: 86948 -/* 47656 */ MCD_OPC_Decode, 244, 30, 130, 2, // Opcode: UABAv4i16 -/* 47661 */ MCD_OPC_FilterValue, 4, 199, 0, 0, // Skip to: 47865 -/* 47666 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 47669 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47691 -/* 47674 */ MCD_OPC_CheckPredicate, 3, 101, 153, 0, // Skip to: 86948 -/* 47679 */ MCD_OPC_CheckField, 21, 1, 1, 94, 153, 0, // Skip to: 86948 -/* 47686 */ MCD_OPC_Decode, 167, 32, 254, 1, // Opcode: UMLALv4i16_v4i32 -/* 47691 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 47729 -/* 47696 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 47699 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47714 -/* 47704 */ MCD_OPC_CheckPredicate, 7, 71, 153, 0, // Skip to: 86948 -/* 47709 */ MCD_OPC_Decode, 164, 25, 130, 2, // Opcode: SQRDMLAHv4i16 -/* 47714 */ MCD_OPC_FilterValue, 1, 61, 153, 0, // Skip to: 86948 -/* 47719 */ MCD_OPC_CheckPredicate, 3, 56, 153, 0, // Skip to: 86948 -/* 47724 */ MCD_OPC_Decode, 131, 30, 238, 1, // Opcode: SUBv4i16 -/* 47729 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47767 -/* 47734 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 47737 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47752 -/* 47742 */ MCD_OPC_CheckPredicate, 3, 33, 153, 0, // Skip to: 86948 -/* 47747 */ MCD_OPC_Decode, 207, 3, 239, 1, // Opcode: CMGEv4i16rz -/* 47752 */ MCD_OPC_FilterValue, 57, 23, 153, 0, // Skip to: 86948 -/* 47757 */ MCD_OPC_CheckPredicate, 4, 18, 153, 0, // Skip to: 86948 -/* 47762 */ MCD_OPC_Decode, 232, 11, 239, 1, // Opcode: FRINTAv4f16 -/* 47767 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 47805 -/* 47772 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 47775 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47790 -/* 47780 */ MCD_OPC_CheckPredicate, 7, 251, 152, 0, // Skip to: 86948 -/* 47785 */ MCD_OPC_Decode, 176, 25, 130, 2, // Opcode: SQRDMLSHv4i16 -/* 47790 */ MCD_OPC_FilterValue, 1, 241, 152, 0, // Skip to: 86948 -/* 47795 */ MCD_OPC_CheckPredicate, 3, 236, 152, 0, // Skip to: 86948 -/* 47800 */ MCD_OPC_Decode, 190, 3, 238, 1, // Opcode: CMEQv4i16 -/* 47805 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 47827 -/* 47810 */ MCD_OPC_CheckPredicate, 3, 221, 152, 0, // Skip to: 86948 -/* 47815 */ MCD_OPC_CheckField, 21, 1, 1, 214, 152, 0, // Skip to: 86948 -/* 47822 */ MCD_OPC_Decode, 226, 19, 130, 2, // Opcode: MLSv4i16 -/* 47827 */ MCD_OPC_FilterValue, 6, 204, 152, 0, // Skip to: 86948 -/* 47832 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 47835 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47850 -/* 47840 */ MCD_OPC_CheckPredicate, 3, 191, 152, 0, // Skip to: 86948 -/* 47845 */ MCD_OPC_Decode, 250, 3, 239, 1, // Opcode: CMLEv4i16rz -/* 47850 */ MCD_OPC_FilterValue, 57, 181, 152, 0, // Skip to: 86948 -/* 47855 */ MCD_OPC_CheckPredicate, 4, 176, 152, 0, // Skip to: 86948 -/* 47860 */ MCD_OPC_Decode, 159, 12, 239, 1, // Opcode: FRINTXv4f16 -/* 47865 */ MCD_OPC_FilterValue, 5, 182, 0, 0, // Skip to: 48052 -/* 47870 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 47873 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47895 -/* 47878 */ MCD_OPC_CheckPredicate, 3, 153, 152, 0, // Skip to: 86948 -/* 47883 */ MCD_OPC_CheckField, 21, 1, 1, 146, 152, 0, // Skip to: 86948 -/* 47890 */ MCD_OPC_Decode, 177, 32, 254, 1, // Opcode: UMLSLv4i16_v4i32 -/* 47895 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47917 -/* 47900 */ MCD_OPC_CheckPredicate, 3, 131, 152, 0, // Skip to: 86948 -/* 47905 */ MCD_OPC_CheckField, 21, 1, 1, 124, 152, 0, // Skip to: 86948 -/* 47912 */ MCD_OPC_Decode, 235, 31, 238, 1, // Opcode: UMAXPv4i16 -/* 47917 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 47970 -/* 47922 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 47925 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 47940 -/* 47930 */ MCD_OPC_CheckPredicate, 3, 101, 152, 0, // Skip to: 86948 -/* 47935 */ MCD_OPC_Decode, 244, 31, 249, 1, // Opcode: UMAXVv4i16v -/* 47940 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 47955 -/* 47945 */ MCD_OPC_CheckPredicate, 3, 86, 152, 0, // Skip to: 86948 -/* 47950 */ MCD_OPC_Decode, 145, 32, 249, 1, // Opcode: UMINVv4i16v -/* 47955 */ MCD_OPC_FilterValue, 57, 76, 152, 0, // Skip to: 86948 -/* 47960 */ MCD_OPC_CheckPredicate, 4, 71, 152, 0, // Skip to: 86948 -/* 47965 */ MCD_OPC_Decode, 178, 8, 239, 1, // Opcode: FCVTNUv4f16 -/* 47970 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 47992 -/* 47975 */ MCD_OPC_CheckPredicate, 3, 56, 152, 0, // Skip to: 86948 -/* 47980 */ MCD_OPC_CheckField, 21, 1, 1, 49, 152, 0, // Skip to: 86948 -/* 47987 */ MCD_OPC_Decode, 136, 32, 238, 1, // Opcode: UMINPv4i16 -/* 47992 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 48014 -/* 47997 */ MCD_OPC_CheckPredicate, 3, 34, 152, 0, // Skip to: 86948 -/* 48002 */ MCD_OPC_CheckField, 21, 1, 1, 27, 152, 0, // Skip to: 86948 -/* 48009 */ MCD_OPC_Decode, 188, 25, 238, 1, // Opcode: SQRDMULHv4i16 -/* 48014 */ MCD_OPC_FilterValue, 6, 17, 152, 0, // Skip to: 86948 -/* 48019 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 48022 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 48037 -/* 48027 */ MCD_OPC_CheckPredicate, 3, 4, 152, 0, // Skip to: 86948 -/* 48032 */ MCD_OPC_Decode, 183, 20, 239, 1, // Opcode: NEGv4i16 -/* 48037 */ MCD_OPC_FilterValue, 57, 250, 151, 0, // Skip to: 86948 -/* 48042 */ MCD_OPC_CheckPredicate, 4, 245, 151, 0, // Skip to: 86948 -/* 48047 */ MCD_OPC_Decode, 150, 8, 239, 1, // Opcode: FCVTMUv4f16 -/* 48052 */ MCD_OPC_FilterValue, 6, 99, 0, 0, // Skip to: 48156 -/* 48057 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 48060 */ MCD_OPC_FilterValue, 0, 69, 0, 0, // Skip to: 48134 -/* 48065 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 48068 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 48090 -/* 48073 */ MCD_OPC_CheckPredicate, 3, 214, 151, 0, // Skip to: 86948 -/* 48078 */ MCD_OPC_CheckField, 21, 1, 1, 207, 151, 0, // Skip to: 86948 -/* 48085 */ MCD_OPC_Decode, 197, 32, 234, 1, // Opcode: UMULLv4i16_v4i32 -/* 48090 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 48112 -/* 48095 */ MCD_OPC_CheckPredicate, 4, 192, 151, 0, // Skip to: 86948 -/* 48100 */ MCD_OPC_CheckField, 16, 6, 57, 185, 151, 0, // Skip to: 86948 -/* 48107 */ MCD_OPC_Decode, 242, 7, 239, 1, // Opcode: FCVTAUv4f16 -/* 48112 */ MCD_OPC_FilterValue, 3, 175, 151, 0, // Skip to: 86948 -/* 48117 */ MCD_OPC_CheckPredicate, 4, 170, 151, 0, // Skip to: 86948 -/* 48122 */ MCD_OPC_CheckField, 16, 6, 57, 163, 151, 0, // Skip to: 86948 -/* 48129 */ MCD_OPC_Decode, 200, 31, 239, 1, // Opcode: UCVTFv4f16 -/* 48134 */ MCD_OPC_FilterValue, 1, 153, 151, 0, // Skip to: 86948 -/* 48139 */ MCD_OPC_CheckPredicate, 8, 148, 151, 0, // Skip to: 86948 -/* 48144 */ MCD_OPC_CheckField, 21, 1, 0, 141, 151, 0, // Skip to: 86948 -/* 48151 */ MCD_OPC_Decode, 162, 7, 167, 2, // Opcode: FCMLAv4f16 -/* 48156 */ MCD_OPC_FilterValue, 7, 131, 151, 0, // Skip to: 86948 -/* 48161 */ MCD_OPC_CheckPredicate, 8, 126, 151, 0, // Skip to: 86948 -/* 48166 */ MCD_OPC_CheckField, 21, 1, 0, 119, 151, 0, // Skip to: 86948 -/* 48173 */ MCD_OPC_CheckField, 10, 2, 1, 112, 151, 0, // Skip to: 86948 -/* 48180 */ MCD_OPC_Decode, 208, 6, 168, 2, // Opcode: FCADDv4f16 -/* 48185 */ MCD_OPC_FilterValue, 2, 250, 6, 0, // Skip to: 49976 -/* 48190 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 48193 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 48215 -/* 48198 */ MCD_OPC_CheckPredicate, 3, 89, 151, 0, // Skip to: 86948 -/* 48203 */ MCD_OPC_CheckField, 21, 1, 1, 82, 151, 0, // Skip to: 86948 -/* 48210 */ MCD_OPC_Decode, 167, 22, 133, 2, // Opcode: SADDLv8i16_v4i32 -/* 48215 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 48253 -/* 48220 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48223 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48238 -/* 48228 */ MCD_OPC_CheckPredicate, 4, 59, 151, 0, // Skip to: 86948 -/* 48233 */ MCD_OPC_Decode, 222, 9, 133, 2, // Opcode: FMAXNMv8f16 -/* 48238 */ MCD_OPC_FilterValue, 1, 49, 151, 0, // Skip to: 86948 -/* 48243 */ MCD_OPC_CheckPredicate, 3, 44, 151, 0, // Skip to: 86948 -/* 48248 */ MCD_OPC_Decode, 131, 23, 133, 2, // Opcode: SHADDv8i16 -/* 48253 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 48275 -/* 48258 */ MCD_OPC_CheckPredicate, 3, 29, 151, 0, // Skip to: 86948 -/* 48263 */ MCD_OPC_CheckField, 16, 6, 32, 22, 151, 0, // Skip to: 86948 -/* 48270 */ MCD_OPC_Decode, 213, 21, 138, 2, // Opcode: REV64v8i16 -/* 48275 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 48313 -/* 48280 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48283 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48298 -/* 48288 */ MCD_OPC_CheckPredicate, 4, 255, 150, 0, // Skip to: 86948 -/* 48293 */ MCD_OPC_Decode, 194, 10, 141, 2, // Opcode: FMLAv8f16 -/* 48298 */ MCD_OPC_FilterValue, 1, 245, 150, 0, // Skip to: 86948 -/* 48303 */ MCD_OPC_CheckPredicate, 3, 240, 150, 0, // Skip to: 86948 -/* 48308 */ MCD_OPC_Decode, 181, 24, 133, 2, // Opcode: SQADDv8i16 -/* 48313 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 48335 -/* 48318 */ MCD_OPC_CheckPredicate, 3, 225, 150, 0, // Skip to: 86948 -/* 48323 */ MCD_OPC_CheckField, 21, 1, 1, 218, 150, 0, // Skip to: 86948 -/* 48330 */ MCD_OPC_Decode, 176, 22, 133, 2, // Opcode: SADDWv8i16_v4i32 -/* 48335 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 48373 -/* 48340 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48343 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48358 -/* 48348 */ MCD_OPC_CheckPredicate, 4, 195, 150, 0, // Skip to: 86948 -/* 48353 */ MCD_OPC_Decode, 202, 6, 133, 2, // Opcode: FADDv8f16 -/* 48358 */ MCD_OPC_FilterValue, 1, 185, 150, 0, // Skip to: 86948 -/* 48363 */ MCD_OPC_CheckPredicate, 3, 180, 150, 0, // Skip to: 86948 -/* 48368 */ MCD_OPC_Decode, 187, 26, 133, 2, // Opcode: SRHADDv8i16 -/* 48373 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 48395 -/* 48378 */ MCD_OPC_CheckPredicate, 3, 165, 150, 0, // Skip to: 86948 -/* 48383 */ MCD_OPC_CheckField, 21, 1, 0, 158, 150, 0, // Skip to: 86948 -/* 48390 */ MCD_OPC_Decode, 201, 34, 133, 2, // Opcode: UZP1v8i16 -/* 48395 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 48433 -/* 48400 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48403 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48418 -/* 48408 */ MCD_OPC_CheckPredicate, 4, 135, 150, 0, // Skip to: 86948 -/* 48413 */ MCD_OPC_Decode, 137, 11, 133, 2, // Opcode: FMULXv8f16 -/* 48418 */ MCD_OPC_FilterValue, 1, 125, 150, 0, // Skip to: 86948 -/* 48423 */ MCD_OPC_CheckPredicate, 3, 120, 150, 0, // Skip to: 86948 -/* 48428 */ MCD_OPC_Decode, 187, 2, 133, 2, // Opcode: BICv16i8 -/* 48433 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 48455 -/* 48438 */ MCD_OPC_CheckPredicate, 3, 105, 150, 0, // Skip to: 86948 -/* 48443 */ MCD_OPC_CheckField, 21, 1, 1, 98, 150, 0, // Skip to: 86948 -/* 48450 */ MCD_OPC_Decode, 165, 27, 133, 2, // Opcode: SSUBLv8i16_v4i32 -/* 48455 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 48493 -/* 48460 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48463 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48478 -/* 48468 */ MCD_OPC_CheckPredicate, 4, 75, 150, 0, // Skip to: 86948 -/* 48473 */ MCD_OPC_Decode, 237, 6, 133, 2, // Opcode: FCMEQv8f16 -/* 48478 */ MCD_OPC_FilterValue, 1, 65, 150, 0, // Skip to: 86948 -/* 48483 */ MCD_OPC_CheckPredicate, 3, 60, 150, 0, // Skip to: 86948 -/* 48488 */ MCD_OPC_Decode, 157, 23, 133, 2, // Opcode: SHSUBv8i16 -/* 48493 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 48554 -/* 48498 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48501 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48516 -/* 48506 */ MCD_OPC_CheckPredicate, 3, 37, 150, 0, // Skip to: 86948 -/* 48511 */ MCD_OPC_Decode, 218, 30, 133, 2, // Opcode: TRN1v8i16 -/* 48516 */ MCD_OPC_FilterValue, 1, 27, 150, 0, // Skip to: 86948 -/* 48521 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 48524 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48539 -/* 48529 */ MCD_OPC_CheckPredicate, 3, 14, 150, 0, // Skip to: 86948 -/* 48534 */ MCD_OPC_Decode, 156, 22, 138, 2, // Opcode: SADDLPv8i16_v4i32 -/* 48539 */ MCD_OPC_FilterValue, 1, 4, 150, 0, // Skip to: 86948 -/* 48544 */ MCD_OPC_CheckPredicate, 3, 255, 149, 0, // Skip to: 86948 -/* 48549 */ MCD_OPC_Decode, 131, 35, 147, 2, // Opcode: XTNv8i16 -/* 48554 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 48576 -/* 48559 */ MCD_OPC_CheckPredicate, 3, 240, 149, 0, // Skip to: 86948 -/* 48564 */ MCD_OPC_CheckField, 21, 1, 1, 233, 149, 0, // Skip to: 86948 -/* 48571 */ MCD_OPC_Decode, 163, 26, 133, 2, // Opcode: SQSUBv8i16 -/* 48576 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 48598 -/* 48581 */ MCD_OPC_CheckPredicate, 3, 218, 149, 0, // Skip to: 86948 -/* 48586 */ MCD_OPC_CheckField, 21, 1, 1, 211, 149, 0, // Skip to: 86948 -/* 48593 */ MCD_OPC_Decode, 171, 27, 133, 2, // Opcode: SSUBWv8i16_v4i32 -/* 48598 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 48636 -/* 48603 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48606 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48621 -/* 48611 */ MCD_OPC_CheckPredicate, 4, 188, 149, 0, // Skip to: 86948 -/* 48616 */ MCD_OPC_Decode, 248, 9, 133, 2, // Opcode: FMAXv8f16 -/* 48621 */ MCD_OPC_FilterValue, 1, 178, 149, 0, // Skip to: 86948 -/* 48626 */ MCD_OPC_CheckPredicate, 3, 173, 149, 0, // Skip to: 86948 -/* 48631 */ MCD_OPC_Decode, 226, 3, 133, 2, // Opcode: CMGTv8i16 -/* 48636 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 48697 -/* 48641 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48659 -/* 48649 */ MCD_OPC_CheckPredicate, 3, 150, 149, 0, // Skip to: 86948 -/* 48654 */ MCD_OPC_Decode, 146, 35, 133, 2, // Opcode: ZIP1v8i16 -/* 48659 */ MCD_OPC_FilterValue, 1, 140, 149, 0, // Skip to: 86948 -/* 48664 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 48667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48682 -/* 48672 */ MCD_OPC_CheckPredicate, 3, 127, 149, 0, // Skip to: 86948 -/* 48677 */ MCD_OPC_Decode, 150, 30, 147, 2, // Opcode: SUQADDv8i16 -/* 48682 */ MCD_OPC_FilterValue, 16, 117, 149, 0, // Skip to: 86948 -/* 48687 */ MCD_OPC_CheckPredicate, 3, 112, 149, 0, // Skip to: 86948 -/* 48692 */ MCD_OPC_Decode, 161, 22, 160, 2, // Opcode: SADDLVv8i16v -/* 48697 */ MCD_OPC_FilterValue, 15, 33, 0, 0, // Skip to: 48735 -/* 48702 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48705 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48720 -/* 48710 */ MCD_OPC_CheckPredicate, 4, 89, 149, 0, // Skip to: 86948 -/* 48715 */ MCD_OPC_Decode, 217, 11, 133, 2, // Opcode: FRECPSv8f16 -/* 48720 */ MCD_OPC_FilterValue, 1, 79, 149, 0, // Skip to: 86948 -/* 48725 */ MCD_OPC_CheckPredicate, 3, 74, 149, 0, // Skip to: 86948 -/* 48730 */ MCD_OPC_Decode, 210, 3, 133, 2, // Opcode: CMGEv8i16 -/* 48735 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 48757 -/* 48740 */ MCD_OPC_CheckPredicate, 3, 59, 149, 0, // Skip to: 86948 -/* 48745 */ MCD_OPC_CheckField, 21, 1, 1, 52, 149, 0, // Skip to: 86948 -/* 48752 */ MCD_OPC_Decode, 145, 1, 141, 2, // Opcode: ADDHNv4i32_v8i16 -/* 48757 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 48779 -/* 48762 */ MCD_OPC_CheckPredicate, 3, 37, 149, 0, // Skip to: 86948 -/* 48767 */ MCD_OPC_CheckField, 21, 1, 1, 30, 149, 0, // Skip to: 86948 -/* 48774 */ MCD_OPC_Decode, 233, 26, 133, 2, // Opcode: SSHLv8i16 -/* 48779 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 48817 -/* 48784 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 48787 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 48802 -/* 48792 */ MCD_OPC_CheckPredicate, 3, 7, 149, 0, // Skip to: 86948 -/* 48797 */ MCD_OPC_Decode, 168, 3, 138, 2, // Opcode: CLSv8i16 -/* 48802 */ MCD_OPC_FilterValue, 33, 253, 148, 0, // Skip to: 86948 -/* 48807 */ MCD_OPC_CheckPredicate, 3, 248, 148, 0, // Skip to: 86948 -/* 48812 */ MCD_OPC_Decode, 172, 26, 147, 2, // Opcode: SQXTNv8i16 -/* 48817 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 48839 -/* 48822 */ MCD_OPC_CheckPredicate, 3, 233, 148, 0, // Skip to: 86948 -/* 48827 */ MCD_OPC_CheckField, 21, 1, 1, 226, 148, 0, // Skip to: 86948 -/* 48834 */ MCD_OPC_Decode, 252, 25, 133, 2, // Opcode: SQSHLv8i16 -/* 48839 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 48861 -/* 48844 */ MCD_OPC_CheckPredicate, 3, 211, 148, 0, // Skip to: 86948 -/* 48849 */ MCD_OPC_CheckField, 21, 1, 1, 204, 148, 0, // Skip to: 86948 -/* 48856 */ MCD_OPC_Decode, 250, 21, 141, 2, // Opcode: SABALv8i16_v4i32 -/* 48861 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 48883 -/* 48866 */ MCD_OPC_CheckPredicate, 3, 189, 148, 0, // Skip to: 86948 -/* 48871 */ MCD_OPC_CheckField, 21, 1, 1, 182, 148, 0, // Skip to: 86948 -/* 48878 */ MCD_OPC_Decode, 203, 26, 133, 2, // Opcode: SRSHLv8i16 -/* 48883 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 48905 -/* 48888 */ MCD_OPC_CheckPredicate, 3, 167, 148, 0, // Skip to: 86948 -/* 48893 */ MCD_OPC_CheckField, 21, 1, 0, 160, 148, 0, // Skip to: 86948 -/* 48900 */ MCD_OPC_Decode, 216, 34, 133, 2, // Opcode: UZP2v8i16 -/* 48905 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 48927 -/* 48910 */ MCD_OPC_CheckPredicate, 3, 145, 148, 0, // Skip to: 86948 -/* 48915 */ MCD_OPC_CheckField, 21, 1, 1, 138, 148, 0, // Skip to: 86948 -/* 48922 */ MCD_OPC_Decode, 203, 25, 133, 2, // Opcode: SQRSHLv8i16 -/* 48927 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 48949 -/* 48932 */ MCD_OPC_CheckPredicate, 3, 123, 148, 0, // Skip to: 86948 -/* 48937 */ MCD_OPC_CheckField, 21, 1, 1, 116, 148, 0, // Skip to: 86948 -/* 48944 */ MCD_OPC_Decode, 214, 29, 141, 2, // Opcode: SUBHNv4i32_v8i16 -/* 48949 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 48971 -/* 48954 */ MCD_OPC_CheckPredicate, 3, 101, 148, 0, // Skip to: 86948 -/* 48959 */ MCD_OPC_CheckField, 21, 1, 1, 94, 148, 0, // Skip to: 86948 -/* 48966 */ MCD_OPC_Decode, 204, 23, 133, 2, // Opcode: SMAXv8i16 -/* 48971 */ MCD_OPC_FilterValue, 26, 56, 0, 0, // Skip to: 49032 -/* 48976 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 48979 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48994 -/* 48984 */ MCD_OPC_CheckPredicate, 3, 71, 148, 0, // Skip to: 86948 -/* 48989 */ MCD_OPC_Decode, 233, 30, 133, 2, // Opcode: TRN2v8i16 -/* 48994 */ MCD_OPC_FilterValue, 1, 61, 148, 0, // Skip to: 86948 -/* 48999 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 49002 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 49017 -/* 49007 */ MCD_OPC_CheckPredicate, 3, 48, 148, 0, // Skip to: 86948 -/* 49012 */ MCD_OPC_Decode, 150, 22, 147, 2, // Opcode: SADALPv8i16_v4i32 -/* 49017 */ MCD_OPC_FilterValue, 1, 38, 148, 0, // Skip to: 86948 -/* 49022 */ MCD_OPC_CheckPredicate, 3, 33, 148, 0, // Skip to: 86948 -/* 49027 */ MCD_OPC_Decode, 183, 8, 147, 2, // Opcode: FCVTNv4i32 -/* 49032 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 49054 -/* 49037 */ MCD_OPC_CheckPredicate, 3, 18, 148, 0, // Skip to: 86948 -/* 49042 */ MCD_OPC_CheckField, 21, 1, 1, 11, 148, 0, // Skip to: 86948 -/* 49049 */ MCD_OPC_Decode, 234, 23, 133, 2, // Opcode: SMINv8i16 -/* 49054 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 49076 -/* 49059 */ MCD_OPC_CheckPredicate, 3, 252, 147, 0, // Skip to: 86948 -/* 49064 */ MCD_OPC_CheckField, 21, 1, 1, 245, 147, 0, // Skip to: 86948 -/* 49071 */ MCD_OPC_Decode, 134, 22, 133, 2, // Opcode: SABDLv8i16_v4i32 -/* 49076 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 49098 -/* 49081 */ MCD_OPC_CheckPredicate, 3, 230, 147, 0, // Skip to: 86948 -/* 49086 */ MCD_OPC_CheckField, 21, 1, 1, 223, 147, 0, // Skip to: 86948 -/* 49093 */ MCD_OPC_Decode, 144, 22, 133, 2, // Opcode: SABDv8i16 -/* 49098 */ MCD_OPC_FilterValue, 30, 56, 0, 0, // Skip to: 49159 -/* 49103 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 49106 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 49121 -/* 49111 */ MCD_OPC_CheckPredicate, 3, 200, 147, 0, // Skip to: 86948 -/* 49116 */ MCD_OPC_Decode, 161, 35, 133, 2, // Opcode: ZIP2v8i16 -/* 49121 */ MCD_OPC_FilterValue, 1, 190, 147, 0, // Skip to: 86948 -/* 49126 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 49129 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 49144 -/* 49134 */ MCD_OPC_CheckPredicate, 3, 177, 147, 0, // Skip to: 86948 -/* 49139 */ MCD_OPC_Decode, 162, 24, 138, 2, // Opcode: SQABSv8i16 -/* 49144 */ MCD_OPC_FilterValue, 1, 167, 147, 0, // Skip to: 86948 -/* 49149 */ MCD_OPC_CheckPredicate, 3, 162, 147, 0, // Skip to: 86948 -/* 49154 */ MCD_OPC_Decode, 251, 7, 138, 2, // Opcode: FCVTLv4i32 -/* 49159 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 49181 -/* 49164 */ MCD_OPC_CheckPredicate, 3, 147, 147, 0, // Skip to: 86948 -/* 49169 */ MCD_OPC_CheckField, 21, 1, 1, 140, 147, 0, // Skip to: 86948 -/* 49176 */ MCD_OPC_Decode, 128, 22, 141, 2, // Opcode: SABAv8i16 -/* 49181 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 49203 -/* 49186 */ MCD_OPC_CheckPredicate, 3, 125, 147, 0, // Skip to: 86948 -/* 49191 */ MCD_OPC_CheckField, 21, 1, 1, 118, 147, 0, // Skip to: 86948 -/* 49198 */ MCD_OPC_Decode, 244, 23, 141, 2, // Opcode: SMLALv8i16_v4i32 -/* 49203 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 49225 -/* 49208 */ MCD_OPC_CheckPredicate, 3, 103, 147, 0, // Skip to: 86948 -/* 49213 */ MCD_OPC_CheckField, 21, 1, 1, 96, 147, 0, // Skip to: 86948 -/* 49220 */ MCD_OPC_Decode, 200, 1, 133, 2, // Opcode: ADDv8i16 -/* 49225 */ MCD_OPC_FilterValue, 34, 48, 0, 0, // Skip to: 49278 -/* 49230 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 49233 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49248 -/* 49238 */ MCD_OPC_CheckPredicate, 3, 73, 147, 0, // Skip to: 86948 -/* 49243 */ MCD_OPC_Decode, 227, 3, 138, 2, // Opcode: CMGTv8i16rz -/* 49248 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49263 -/* 49253 */ MCD_OPC_CheckPredicate, 3, 58, 147, 0, // Skip to: 86948 -/* 49258 */ MCD_OPC_Decode, 136, 12, 138, 2, // Opcode: FRINTNv2f64 -/* 49263 */ MCD_OPC_FilterValue, 57, 48, 147, 0, // Skip to: 86948 -/* 49268 */ MCD_OPC_CheckPredicate, 4, 43, 147, 0, // Skip to: 86948 -/* 49273 */ MCD_OPC_Decode, 139, 12, 138, 2, // Opcode: FRINTNv8f16 -/* 49278 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 49300 -/* 49283 */ MCD_OPC_CheckPredicate, 3, 28, 147, 0, // Skip to: 86948 -/* 49288 */ MCD_OPC_CheckField, 21, 1, 1, 21, 147, 0, // Skip to: 86948 -/* 49295 */ MCD_OPC_Decode, 239, 4, 133, 2, // Opcode: CMTSTv8i16 -/* 49300 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 49322 -/* 49305 */ MCD_OPC_CheckPredicate, 3, 6, 147, 0, // Skip to: 86948 -/* 49310 */ MCD_OPC_CheckField, 21, 1, 1, 255, 146, 0, // Skip to: 86948 -/* 49317 */ MCD_OPC_Decode, 216, 24, 141, 2, // Opcode: SQDMLALv8i16_v4i32 -/* 49322 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 49344 -/* 49327 */ MCD_OPC_CheckPredicate, 3, 240, 146, 0, // Skip to: 86948 -/* 49332 */ MCD_OPC_CheckField, 21, 1, 1, 233, 146, 0, // Skip to: 86948 -/* 49339 */ MCD_OPC_Decode, 216, 19, 141, 2, // Opcode: MLAv8i16 -/* 49344 */ MCD_OPC_FilterValue, 38, 48, 0, 0, // Skip to: 49397 -/* 49349 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 49352 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49367 -/* 49357 */ MCD_OPC_CheckPredicate, 3, 210, 146, 0, // Skip to: 86948 -/* 49362 */ MCD_OPC_Decode, 195, 3, 138, 2, // Opcode: CMEQv8i16rz -/* 49367 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49382 -/* 49372 */ MCD_OPC_CheckPredicate, 3, 195, 146, 0, // Skip to: 86948 -/* 49377 */ MCD_OPC_Decode, 253, 11, 138, 2, // Opcode: FRINTMv2f64 -/* 49382 */ MCD_OPC_FilterValue, 57, 185, 146, 0, // Skip to: 86948 -/* 49387 */ MCD_OPC_CheckPredicate, 4, 180, 146, 0, // Skip to: 86948 -/* 49392 */ MCD_OPC_Decode, 128, 12, 138, 2, // Opcode: FRINTMv8f16 -/* 49397 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 49419 -/* 49402 */ MCD_OPC_CheckPredicate, 3, 165, 146, 0, // Skip to: 86948 -/* 49407 */ MCD_OPC_CheckField, 21, 1, 1, 158, 146, 0, // Skip to: 86948 -/* 49414 */ MCD_OPC_Decode, 164, 20, 133, 2, // Opcode: MULv8i16 -/* 49419 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 49441 -/* 49424 */ MCD_OPC_CheckPredicate, 3, 143, 146, 0, // Skip to: 86948 -/* 49429 */ MCD_OPC_CheckField, 21, 1, 1, 136, 146, 0, // Skip to: 86948 -/* 49436 */ MCD_OPC_Decode, 254, 23, 141, 2, // Opcode: SMLSLv8i16_v4i32 -/* 49441 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 49463 -/* 49446 */ MCD_OPC_CheckPredicate, 3, 121, 146, 0, // Skip to: 86948 -/* 49451 */ MCD_OPC_CheckField, 21, 1, 1, 114, 146, 0, // Skip to: 86948 -/* 49458 */ MCD_OPC_Decode, 181, 23, 133, 2, // Opcode: SMAXPv8i16 -/* 49463 */ MCD_OPC_FilterValue, 42, 78, 0, 0, // Skip to: 49546 -/* 49468 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 49471 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49486 -/* 49476 */ MCD_OPC_CheckPredicate, 3, 91, 146, 0, // Skip to: 86948 -/* 49481 */ MCD_OPC_Decode, 132, 4, 138, 2, // Opcode: CMLTv8i16rz -/* 49486 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49501 -/* 49491 */ MCD_OPC_CheckPredicate, 3, 76, 146, 0, // Skip to: 86948 -/* 49496 */ MCD_OPC_Decode, 163, 8, 138, 2, // Opcode: FCVTNSv2f64 -/* 49501 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 49516 -/* 49506 */ MCD_OPC_CheckPredicate, 3, 61, 146, 0, // Skip to: 86948 -/* 49511 */ MCD_OPC_Decode, 190, 23, 152, 2, // Opcode: SMAXVv8i16v -/* 49516 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 49531 -/* 49521 */ MCD_OPC_CheckPredicate, 3, 46, 146, 0, // Skip to: 86948 -/* 49526 */ MCD_OPC_Decode, 220, 23, 152, 2, // Opcode: SMINVv8i16v -/* 49531 */ MCD_OPC_FilterValue, 57, 36, 146, 0, // Skip to: 86948 -/* 49536 */ MCD_OPC_CheckPredicate, 4, 31, 146, 0, // Skip to: 86948 -/* 49541 */ MCD_OPC_Decode, 166, 8, 138, 2, // Opcode: FCVTNSv8f16 -/* 49546 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 49568 -/* 49551 */ MCD_OPC_CheckPredicate, 3, 16, 146, 0, // Skip to: 86948 -/* 49556 */ MCD_OPC_CheckField, 21, 1, 1, 9, 146, 0, // Skip to: 86948 -/* 49563 */ MCD_OPC_Decode, 211, 23, 133, 2, // Opcode: SMINPv8i16 -/* 49568 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 49590 -/* 49573 */ MCD_OPC_CheckPredicate, 3, 250, 145, 0, // Skip to: 86948 -/* 49578 */ MCD_OPC_CheckField, 21, 1, 1, 243, 145, 0, // Skip to: 86948 -/* 49585 */ MCD_OPC_Decode, 228, 24, 141, 2, // Opcode: SQDMLSLv8i16_v4i32 -/* 49590 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 49612 -/* 49595 */ MCD_OPC_CheckPredicate, 3, 228, 145, 0, // Skip to: 86948 -/* 49600 */ MCD_OPC_CheckField, 21, 1, 1, 221, 145, 0, // Skip to: 86948 -/* 49607 */ MCD_OPC_Decode, 239, 24, 133, 2, // Opcode: SQDMULHv8i16 -/* 49612 */ MCD_OPC_FilterValue, 46, 63, 0, 0, // Skip to: 49680 -/* 49617 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 49620 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49635 -/* 49625 */ MCD_OPC_CheckPredicate, 3, 198, 145, 0, // Skip to: 86948 -/* 49630 */ MCD_OPC_Decode, 136, 1, 138, 2, // Opcode: ABSv8i16 -/* 49635 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49650 -/* 49640 */ MCD_OPC_CheckPredicate, 3, 183, 145, 0, // Skip to: 86948 -/* 49645 */ MCD_OPC_Decode, 135, 8, 138, 2, // Opcode: FCVTMSv2f64 -/* 49650 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 49665 -/* 49655 */ MCD_OPC_CheckPredicate, 3, 168, 145, 0, // Skip to: 86948 -/* 49660 */ MCD_OPC_Decode, 170, 1, 152, 2, // Opcode: ADDVv8i16v -/* 49665 */ MCD_OPC_FilterValue, 57, 158, 145, 0, // Skip to: 86948 -/* 49670 */ MCD_OPC_CheckPredicate, 4, 153, 145, 0, // Skip to: 86948 -/* 49675 */ MCD_OPC_Decode, 138, 8, 138, 2, // Opcode: FCVTMSv8f16 -/* 49680 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 49702 -/* 49685 */ MCD_OPC_CheckPredicate, 3, 138, 145, 0, // Skip to: 86948 -/* 49690 */ MCD_OPC_CheckField, 21, 1, 1, 131, 145, 0, // Skip to: 86948 -/* 49697 */ MCD_OPC_Decode, 155, 1, 133, 2, // Opcode: ADDPv8i16 -/* 49702 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 49724 -/* 49707 */ MCD_OPC_CheckPredicate, 3, 116, 145, 0, // Skip to: 86948 -/* 49712 */ MCD_OPC_CheckField, 21, 1, 1, 109, 145, 0, // Skip to: 86948 -/* 49719 */ MCD_OPC_Decode, 147, 24, 133, 2, // Opcode: SMULLv8i16_v4i32 -/* 49724 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 49746 -/* 49729 */ MCD_OPC_CheckPredicate, 3, 94, 145, 0, // Skip to: 86948 -/* 49734 */ MCD_OPC_CheckField, 21, 1, 1, 87, 145, 0, // Skip to: 86948 -/* 49741 */ MCD_OPC_Decode, 219, 9, 133, 2, // Opcode: FMAXNMv2f64 -/* 49746 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 49784 -/* 49751 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 49754 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49769 -/* 49759 */ MCD_OPC_CheckPredicate, 3, 64, 145, 0, // Skip to: 86948 -/* 49764 */ MCD_OPC_Decode, 227, 7, 138, 2, // Opcode: FCVTASv2f64 -/* 49769 */ MCD_OPC_FilterValue, 57, 54, 145, 0, // Skip to: 86948 -/* 49774 */ MCD_OPC_CheckPredicate, 4, 49, 145, 0, // Skip to: 86948 -/* 49779 */ MCD_OPC_Decode, 230, 7, 138, 2, // Opcode: FCVTASv8f16 -/* 49784 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 49806 -/* 49789 */ MCD_OPC_CheckPredicate, 3, 34, 145, 0, // Skip to: 86948 -/* 49794 */ MCD_OPC_CheckField, 21, 1, 1, 27, 145, 0, // Skip to: 86948 -/* 49801 */ MCD_OPC_Decode, 187, 10, 141, 2, // Opcode: FMLAv2f64 -/* 49806 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 49828 -/* 49811 */ MCD_OPC_CheckPredicate, 3, 12, 145, 0, // Skip to: 86948 -/* 49816 */ MCD_OPC_CheckField, 21, 1, 1, 5, 145, 0, // Skip to: 86948 -/* 49823 */ MCD_OPC_Decode, 252, 24, 133, 2, // Opcode: SQDMULLv8i16_v4i32 -/* 49828 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 49850 -/* 49833 */ MCD_OPC_CheckPredicate, 3, 246, 144, 0, // Skip to: 86948 -/* 49838 */ MCD_OPC_CheckField, 21, 1, 1, 239, 144, 0, // Skip to: 86948 -/* 49845 */ MCD_OPC_Decode, 199, 6, 133, 2, // Opcode: FADDv2f64 -/* 49850 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 49888 -/* 49855 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 49858 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49873 -/* 49863 */ MCD_OPC_CheckPredicate, 3, 216, 144, 0, // Skip to: 86948 -/* 49868 */ MCD_OPC_Decode, 210, 22, 138, 2, // Opcode: SCVTFv2f64 -/* 49873 */ MCD_OPC_FilterValue, 57, 206, 144, 0, // Skip to: 86948 -/* 49878 */ MCD_OPC_CheckPredicate, 4, 201, 144, 0, // Skip to: 86948 -/* 49883 */ MCD_OPC_Decode, 217, 22, 138, 2, // Opcode: SCVTFv8f16 -/* 49888 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 49910 -/* 49893 */ MCD_OPC_CheckPredicate, 3, 186, 144, 0, // Skip to: 86948 -/* 49898 */ MCD_OPC_CheckField, 21, 1, 1, 179, 144, 0, // Skip to: 86948 -/* 49905 */ MCD_OPC_Decode, 130, 11, 133, 2, // Opcode: FMULXv2f64 -/* 49910 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 49932 -/* 49915 */ MCD_OPC_CheckPredicate, 3, 164, 144, 0, // Skip to: 86948 -/* 49920 */ MCD_OPC_CheckField, 21, 1, 1, 157, 144, 0, // Skip to: 86948 -/* 49927 */ MCD_OPC_Decode, 230, 6, 133, 2, // Opcode: FCMEQv2f64 -/* 49932 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 49954 -/* 49937 */ MCD_OPC_CheckPredicate, 3, 142, 144, 0, // Skip to: 86948 -/* 49942 */ MCD_OPC_CheckField, 21, 1, 1, 135, 144, 0, // Skip to: 86948 -/* 49949 */ MCD_OPC_Decode, 245, 9, 133, 2, // Opcode: FMAXv2f64 -/* 49954 */ MCD_OPC_FilterValue, 63, 125, 144, 0, // Skip to: 86948 -/* 49959 */ MCD_OPC_CheckPredicate, 3, 120, 144, 0, // Skip to: 86948 -/* 49964 */ MCD_OPC_CheckField, 21, 1, 1, 113, 144, 0, // Skip to: 86948 -/* 49971 */ MCD_OPC_Decode, 214, 11, 133, 2, // Opcode: FRECPSv2f64 -/* 49976 */ MCD_OPC_FilterValue, 3, 134, 6, 0, // Skip to: 51651 -/* 49981 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 49984 */ MCD_OPC_FilterValue, 0, 205, 0, 0, // Skip to: 50194 -/* 49989 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 49992 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50014 -/* 49997 */ MCD_OPC_CheckPredicate, 3, 82, 144, 0, // Skip to: 86948 -/* 50002 */ MCD_OPC_CheckField, 21, 1, 1, 75, 144, 0, // Skip to: 86948 -/* 50009 */ MCD_OPC_Decode, 157, 31, 133, 2, // Opcode: UADDLv8i16_v4i32 -/* 50014 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 50052 -/* 50019 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 50022 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50037 -/* 50027 */ MCD_OPC_CheckPredicate, 4, 52, 144, 0, // Skip to: 86948 -/* 50032 */ MCD_OPC_Decode, 204, 9, 133, 2, // Opcode: FMAXNMPv8f16 -/* 50037 */ MCD_OPC_FilterValue, 1, 42, 144, 0, // Skip to: 86948 -/* 50042 */ MCD_OPC_CheckPredicate, 3, 37, 144, 0, // Skip to: 86948 -/* 50047 */ MCD_OPC_Decode, 224, 31, 133, 2, // Opcode: UHADDv8i16 -/* 50052 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 50074 -/* 50057 */ MCD_OPC_CheckPredicate, 3, 22, 144, 0, // Skip to: 86948 -/* 50062 */ MCD_OPC_CheckField, 16, 6, 32, 15, 144, 0, // Skip to: 86948 -/* 50069 */ MCD_OPC_Decode, 207, 21, 138, 2, // Opcode: REV32v8i16 -/* 50074 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 50096 -/* 50079 */ MCD_OPC_CheckPredicate, 3, 0, 144, 0, // Skip to: 86948 -/* 50084 */ MCD_OPC_CheckField, 21, 1, 1, 249, 143, 0, // Skip to: 86948 -/* 50091 */ MCD_OPC_Decode, 220, 32, 133, 2, // Opcode: UQADDv8i16 -/* 50096 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50118 -/* 50101 */ MCD_OPC_CheckPredicate, 3, 234, 143, 0, // Skip to: 86948 -/* 50106 */ MCD_OPC_CheckField, 21, 1, 1, 227, 143, 0, // Skip to: 86948 -/* 50113 */ MCD_OPC_Decode, 167, 31, 133, 2, // Opcode: UADDWv8i16_v4i32 -/* 50118 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 50156 -/* 50123 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 50126 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50141 -/* 50131 */ MCD_OPC_CheckPredicate, 4, 204, 143, 0, // Skip to: 86948 -/* 50136 */ MCD_OPC_Decode, 184, 6, 133, 2, // Opcode: FADDPv8f16 -/* 50141 */ MCD_OPC_FilterValue, 1, 194, 143, 0, // Skip to: 86948 -/* 50146 */ MCD_OPC_CheckPredicate, 3, 189, 143, 0, // Skip to: 86948 -/* 50151 */ MCD_OPC_Decode, 223, 33, 133, 2, // Opcode: URHADDv8i16 -/* 50156 */ MCD_OPC_FilterValue, 7, 179, 143, 0, // Skip to: 86948 -/* 50161 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 50164 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50179 -/* 50169 */ MCD_OPC_CheckPredicate, 4, 166, 143, 0, // Skip to: 86948 -/* 50174 */ MCD_OPC_Decode, 162, 11, 133, 2, // Opcode: FMULv8f16 -/* 50179 */ MCD_OPC_FilterValue, 1, 156, 143, 0, // Skip to: 86948 -/* 50184 */ MCD_OPC_CheckPredicate, 3, 151, 143, 0, // Skip to: 86948 -/* 50189 */ MCD_OPC_Decode, 221, 2, 141, 2, // Opcode: BSLv16i8 -/* 50194 */ MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 50489 -/* 50199 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 50202 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50224 -/* 50207 */ MCD_OPC_CheckPredicate, 3, 128, 143, 0, // Skip to: 86948 -/* 50212 */ MCD_OPC_CheckField, 21, 1, 1, 121, 143, 0, // Skip to: 86948 -/* 50219 */ MCD_OPC_Decode, 168, 34, 133, 2, // Opcode: USUBLv8i16_v4i32 -/* 50224 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 50262 -/* 50229 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 50232 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50247 -/* 50237 */ MCD_OPC_CheckPredicate, 4, 98, 143, 0, // Skip to: 86948 -/* 50242 */ MCD_OPC_Decode, 131, 7, 133, 2, // Opcode: FCMGEv8f16 -/* 50247 */ MCD_OPC_FilterValue, 1, 88, 143, 0, // Skip to: 86948 -/* 50252 */ MCD_OPC_CheckPredicate, 3, 83, 143, 0, // Skip to: 86948 -/* 50257 */ MCD_OPC_Decode, 230, 31, 133, 2, // Opcode: UHSUBv8i16 -/* 50262 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 50300 -/* 50267 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 50270 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50285 -/* 50275 */ MCD_OPC_CheckPredicate, 3, 60, 143, 0, // Skip to: 86948 -/* 50280 */ MCD_OPC_Decode, 146, 31, 138, 2, // Opcode: UADDLPv8i16_v4i32 -/* 50285 */ MCD_OPC_FilterValue, 33, 50, 143, 0, // Skip to: 86948 -/* 50290 */ MCD_OPC_CheckPredicate, 3, 45, 143, 0, // Skip to: 86948 -/* 50295 */ MCD_OPC_Decode, 181, 26, 147, 2, // Opcode: SQXTUNv8i16 -/* 50300 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 50338 -/* 50305 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 50308 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50323 -/* 50313 */ MCD_OPC_CheckPredicate, 4, 22, 143, 0, // Skip to: 86948 -/* 50318 */ MCD_OPC_Decode, 160, 6, 133, 2, // Opcode: FACGEv8f16 -/* 50323 */ MCD_OPC_FilterValue, 1, 12, 143, 0, // Skip to: 86948 -/* 50328 */ MCD_OPC_CheckPredicate, 3, 7, 143, 0, // Skip to: 86948 -/* 50333 */ MCD_OPC_Decode, 206, 33, 133, 2, // Opcode: UQSUBv8i16 -/* 50338 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50360 -/* 50343 */ MCD_OPC_CheckPredicate, 3, 248, 142, 0, // Skip to: 86948 -/* 50348 */ MCD_OPC_CheckField, 21, 1, 1, 241, 142, 0, // Skip to: 86948 -/* 50355 */ MCD_OPC_Decode, 174, 34, 133, 2, // Opcode: USUBWv8i16_v4i32 -/* 50360 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 50398 -/* 50365 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 50368 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50383 -/* 50373 */ MCD_OPC_CheckPredicate, 4, 218, 142, 0, // Skip to: 86948 -/* 50378 */ MCD_OPC_Decode, 230, 9, 133, 2, // Opcode: FMAXPv8f16 -/* 50383 */ MCD_OPC_FilterValue, 1, 208, 142, 0, // Skip to: 86948 -/* 50388 */ MCD_OPC_CheckPredicate, 3, 203, 142, 0, // Skip to: 86948 -/* 50393 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: CMHIv8i16 -/* 50398 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 50451 -/* 50403 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 50406 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50421 -/* 50411 */ MCD_OPC_CheckPredicate, 3, 180, 142, 0, // Skip to: 86948 -/* 50416 */ MCD_OPC_Decode, 154, 34, 147, 2, // Opcode: USQADDv8i16 -/* 50421 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 50436 -/* 50426 */ MCD_OPC_CheckPredicate, 3, 165, 142, 0, // Skip to: 86948 -/* 50431 */ MCD_OPC_Decode, 137, 23, 138, 2, // Opcode: SHLLv8i16 -/* 50436 */ MCD_OPC_FilterValue, 48, 155, 142, 0, // Skip to: 86948 -/* 50441 */ MCD_OPC_CheckPredicate, 3, 150, 142, 0, // Skip to: 86948 -/* 50446 */ MCD_OPC_Decode, 151, 31, 160, 2, // Opcode: UADDLVv8i16v -/* 50451 */ MCD_OPC_FilterValue, 7, 140, 142, 0, // Skip to: 86948 -/* 50456 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 50459 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50474 -/* 50464 */ MCD_OPC_CheckPredicate, 4, 127, 142, 0, // Skip to: 86948 -/* 50469 */ MCD_OPC_Decode, 179, 9, 133, 2, // Opcode: FDIVv8f16 -/* 50474 */ MCD_OPC_FilterValue, 1, 117, 142, 0, // Skip to: 86948 -/* 50479 */ MCD_OPC_CheckPredicate, 3, 112, 142, 0, // Skip to: 86948 -/* 50484 */ MCD_OPC_Decode, 244, 3, 133, 2, // Opcode: CMHSv8i16 -/* 50489 */ MCD_OPC_FilterValue, 2, 195, 0, 0, // Skip to: 50689 -/* 50494 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 50497 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50519 -/* 50502 */ MCD_OPC_CheckPredicate, 3, 89, 142, 0, // Skip to: 86948 -/* 50507 */ MCD_OPC_CheckField, 21, 1, 1, 82, 142, 0, // Skip to: 86948 -/* 50514 */ MCD_OPC_Decode, 180, 21, 141, 2, // Opcode: RADDHNv4i32_v8i16 -/* 50519 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 50541 -/* 50524 */ MCD_OPC_CheckPredicate, 3, 67, 142, 0, // Skip to: 86948 -/* 50529 */ MCD_OPC_CheckField, 21, 1, 1, 60, 142, 0, // Skip to: 86948 -/* 50536 */ MCD_OPC_Decode, 135, 34, 133, 2, // Opcode: USHLv8i16 -/* 50541 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 50579 -/* 50546 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 50549 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50564 -/* 50554 */ MCD_OPC_CheckPredicate, 3, 37, 142, 0, // Skip to: 86948 -/* 50559 */ MCD_OPC_Decode, 180, 3, 138, 2, // Opcode: CLZv8i16 -/* 50564 */ MCD_OPC_FilterValue, 33, 27, 142, 0, // Skip to: 86948 -/* 50569 */ MCD_OPC_CheckPredicate, 3, 22, 142, 0, // Skip to: 86948 -/* 50574 */ MCD_OPC_Decode, 215, 33, 147, 2, // Opcode: UQXTNv8i16 -/* 50579 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 50601 -/* 50584 */ MCD_OPC_CheckPredicate, 3, 7, 142, 0, // Skip to: 86948 -/* 50589 */ MCD_OPC_CheckField, 21, 1, 1, 0, 142, 0, // Skip to: 86948 -/* 50596 */ MCD_OPC_Decode, 176, 33, 133, 2, // Opcode: UQSHLv8i16 -/* 50601 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50623 -/* 50606 */ MCD_OPC_CheckPredicate, 3, 241, 141, 0, // Skip to: 86948 -/* 50611 */ MCD_OPC_CheckField, 21, 1, 1, 234, 141, 0, // Skip to: 86948 -/* 50618 */ MCD_OPC_Decode, 240, 30, 141, 2, // Opcode: UABALv8i16_v4i32 -/* 50623 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 50645 -/* 50628 */ MCD_OPC_CheckPredicate, 3, 219, 141, 0, // Skip to: 86948 -/* 50633 */ MCD_OPC_CheckField, 21, 1, 1, 212, 141, 0, // Skip to: 86948 -/* 50640 */ MCD_OPC_Decode, 231, 33, 133, 2, // Opcode: URSHLv8i16 -/* 50645 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 50667 -/* 50650 */ MCD_OPC_CheckPredicate, 3, 197, 141, 0, // Skip to: 86948 -/* 50655 */ MCD_OPC_CheckField, 16, 6, 32, 190, 141, 0, // Skip to: 86948 -/* 50662 */ MCD_OPC_Decode, 190, 21, 138, 2, // Opcode: RBITv16i8 -/* 50667 */ MCD_OPC_FilterValue, 7, 180, 141, 0, // Skip to: 86948 -/* 50672 */ MCD_OPC_CheckPredicate, 3, 175, 141, 0, // Skip to: 86948 -/* 50677 */ MCD_OPC_CheckField, 21, 1, 1, 168, 141, 0, // Skip to: 86948 -/* 50684 */ MCD_OPC_Decode, 147, 33, 133, 2, // Opcode: UQRSHLv8i16 -/* 50689 */ MCD_OPC_FilterValue, 3, 195, 0, 0, // Skip to: 50889 -/* 50694 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 50697 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50719 -/* 50702 */ MCD_OPC_CheckPredicate, 3, 145, 141, 0, // Skip to: 86948 -/* 50707 */ MCD_OPC_CheckField, 21, 1, 1, 138, 141, 0, // Skip to: 86948 -/* 50714 */ MCD_OPC_Decode, 243, 21, 141, 2, // Opcode: RSUBHNv4i32_v8i16 -/* 50719 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 50741 -/* 50724 */ MCD_OPC_CheckPredicate, 3, 123, 141, 0, // Skip to: 86948 -/* 50729 */ MCD_OPC_CheckField, 21, 1, 1, 116, 141, 0, // Skip to: 86948 -/* 50736 */ MCD_OPC_Decode, 132, 32, 133, 2, // Opcode: UMAXv8i16 -/* 50741 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 50779 -/* 50746 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 50749 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50764 -/* 50754 */ MCD_OPC_CheckPredicate, 3, 93, 141, 0, // Skip to: 86948 -/* 50759 */ MCD_OPC_Decode, 140, 31, 147, 2, // Opcode: UADALPv8i16_v4i32 -/* 50764 */ MCD_OPC_FilterValue, 33, 83, 141, 0, // Skip to: 86948 -/* 50769 */ MCD_OPC_CheckPredicate, 3, 78, 141, 0, // Skip to: 86948 -/* 50774 */ MCD_OPC_Decode, 217, 8, 147, 2, // Opcode: FCVTXNv4f32 -/* 50779 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 50801 -/* 50784 */ MCD_OPC_CheckPredicate, 3, 63, 141, 0, // Skip to: 86948 -/* 50789 */ MCD_OPC_CheckField, 21, 1, 1, 56, 141, 0, // Skip to: 86948 -/* 50796 */ MCD_OPC_Decode, 161, 32, 133, 2, // Opcode: UMINv8i16 -/* 50801 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50823 -/* 50806 */ MCD_OPC_CheckPredicate, 3, 41, 141, 0, // Skip to: 86948 -/* 50811 */ MCD_OPC_CheckField, 21, 1, 1, 34, 141, 0, // Skip to: 86948 -/* 50818 */ MCD_OPC_Decode, 252, 30, 133, 2, // Opcode: UABDLv8i16_v4i32 -/* 50823 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 50845 -/* 50828 */ MCD_OPC_CheckPredicate, 3, 19, 141, 0, // Skip to: 86948 -/* 50833 */ MCD_OPC_CheckField, 21, 1, 1, 12, 141, 0, // Skip to: 86948 -/* 50840 */ MCD_OPC_Decode, 134, 31, 133, 2, // Opcode: UABDv8i16 -/* 50845 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 50867 -/* 50850 */ MCD_OPC_CheckPredicate, 3, 253, 140, 0, // Skip to: 86948 -/* 50855 */ MCD_OPC_CheckField, 16, 6, 32, 246, 140, 0, // Skip to: 86948 -/* 50862 */ MCD_OPC_Decode, 156, 25, 138, 2, // Opcode: SQNEGv8i16 -/* 50867 */ MCD_OPC_FilterValue, 7, 236, 140, 0, // Skip to: 86948 -/* 50872 */ MCD_OPC_CheckPredicate, 3, 231, 140, 0, // Skip to: 86948 -/* 50877 */ MCD_OPC_CheckField, 21, 1, 1, 224, 140, 0, // Skip to: 86948 -/* 50884 */ MCD_OPC_Decode, 246, 30, 141, 2, // Opcode: UABAv8i16 -/* 50889 */ MCD_OPC_FilterValue, 4, 229, 0, 0, // Skip to: 51123 -/* 50894 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 50897 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50919 -/* 50902 */ MCD_OPC_CheckPredicate, 3, 201, 140, 0, // Skip to: 86948 -/* 50907 */ MCD_OPC_CheckField, 21, 1, 1, 194, 140, 0, // Skip to: 86948 -/* 50914 */ MCD_OPC_Decode, 171, 32, 141, 2, // Opcode: UMLALv8i16_v4i32 -/* 50919 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 50957 -/* 50924 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 50927 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50942 -/* 50932 */ MCD_OPC_CheckPredicate, 7, 171, 140, 0, // Skip to: 86948 -/* 50937 */ MCD_OPC_Decode, 168, 25, 141, 2, // Opcode: SQRDMLAHv8i16 -/* 50942 */ MCD_OPC_FilterValue, 1, 161, 140, 0, // Skip to: 86948 -/* 50947 */ MCD_OPC_CheckPredicate, 3, 156, 140, 0, // Skip to: 86948 -/* 50952 */ MCD_OPC_Decode, 133, 30, 133, 2, // Opcode: SUBv8i16 -/* 50957 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 51010 -/* 50962 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 50965 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50980 -/* 50970 */ MCD_OPC_CheckPredicate, 3, 133, 140, 0, // Skip to: 86948 -/* 50975 */ MCD_OPC_Decode, 211, 3, 138, 2, // Opcode: CMGEv8i16rz -/* 50980 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 50995 -/* 50985 */ MCD_OPC_CheckPredicate, 3, 118, 140, 0, // Skip to: 86948 -/* 50990 */ MCD_OPC_Decode, 231, 11, 138, 2, // Opcode: FRINTAv2f64 -/* 50995 */ MCD_OPC_FilterValue, 57, 108, 140, 0, // Skip to: 86948 -/* 51000 */ MCD_OPC_CheckPredicate, 4, 103, 140, 0, // Skip to: 86948 -/* 51005 */ MCD_OPC_Decode, 234, 11, 138, 2, // Opcode: FRINTAv8f16 -/* 51010 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 51048 -/* 51015 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 51018 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51033 -/* 51023 */ MCD_OPC_CheckPredicate, 7, 80, 140, 0, // Skip to: 86948 -/* 51028 */ MCD_OPC_Decode, 180, 25, 141, 2, // Opcode: SQRDMLSHv8i16 -/* 51033 */ MCD_OPC_FilterValue, 1, 70, 140, 0, // Skip to: 86948 -/* 51038 */ MCD_OPC_CheckPredicate, 3, 65, 140, 0, // Skip to: 86948 -/* 51043 */ MCD_OPC_Decode, 194, 3, 133, 2, // Opcode: CMEQv8i16 -/* 51048 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 51070 -/* 51053 */ MCD_OPC_CheckPredicate, 3, 50, 140, 0, // Skip to: 86948 -/* 51058 */ MCD_OPC_CheckField, 21, 1, 1, 43, 140, 0, // Skip to: 86948 -/* 51065 */ MCD_OPC_Decode, 230, 19, 141, 2, // Opcode: MLSv8i16 -/* 51070 */ MCD_OPC_FilterValue, 6, 33, 140, 0, // Skip to: 86948 -/* 51075 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 51078 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 51093 -/* 51083 */ MCD_OPC_CheckPredicate, 3, 20, 140, 0, // Skip to: 86948 -/* 51088 */ MCD_OPC_Decode, 252, 3, 138, 2, // Opcode: CMLEv8i16rz -/* 51093 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51108 -/* 51098 */ MCD_OPC_CheckPredicate, 3, 5, 140, 0, // Skip to: 86948 -/* 51103 */ MCD_OPC_Decode, 158, 12, 138, 2, // Opcode: FRINTXv2f64 -/* 51108 */ MCD_OPC_FilterValue, 57, 251, 139, 0, // Skip to: 86948 -/* 51113 */ MCD_OPC_CheckPredicate, 4, 246, 139, 0, // Skip to: 86948 -/* 51118 */ MCD_OPC_Decode, 161, 12, 138, 2, // Opcode: FRINTXv8f16 -/* 51123 */ MCD_OPC_FilterValue, 5, 212, 0, 0, // Skip to: 51340 -/* 51128 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 51131 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51153 -/* 51136 */ MCD_OPC_CheckPredicate, 3, 223, 139, 0, // Skip to: 86948 -/* 51141 */ MCD_OPC_CheckField, 21, 1, 1, 216, 139, 0, // Skip to: 86948 -/* 51148 */ MCD_OPC_Decode, 181, 32, 141, 2, // Opcode: UMLSLv8i16_v4i32 -/* 51153 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 51175 -/* 51158 */ MCD_OPC_CheckPredicate, 3, 201, 139, 0, // Skip to: 86948 -/* 51163 */ MCD_OPC_CheckField, 21, 1, 1, 194, 139, 0, // Skip to: 86948 -/* 51170 */ MCD_OPC_Decode, 237, 31, 133, 2, // Opcode: UMAXPv8i16 -/* 51175 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 51243 -/* 51180 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 51183 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51198 -/* 51188 */ MCD_OPC_CheckPredicate, 3, 171, 139, 0, // Skip to: 86948 -/* 51193 */ MCD_OPC_Decode, 177, 8, 138, 2, // Opcode: FCVTNUv2f64 -/* 51198 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 51213 -/* 51203 */ MCD_OPC_CheckPredicate, 3, 156, 139, 0, // Skip to: 86948 -/* 51208 */ MCD_OPC_Decode, 246, 31, 152, 2, // Opcode: UMAXVv8i16v -/* 51213 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 51228 -/* 51218 */ MCD_OPC_CheckPredicate, 3, 141, 139, 0, // Skip to: 86948 -/* 51223 */ MCD_OPC_Decode, 147, 32, 152, 2, // Opcode: UMINVv8i16v -/* 51228 */ MCD_OPC_FilterValue, 57, 131, 139, 0, // Skip to: 86948 -/* 51233 */ MCD_OPC_CheckPredicate, 4, 126, 139, 0, // Skip to: 86948 -/* 51238 */ MCD_OPC_Decode, 180, 8, 138, 2, // Opcode: FCVTNUv8f16 -/* 51243 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 51265 -/* 51248 */ MCD_OPC_CheckPredicate, 3, 111, 139, 0, // Skip to: 86948 -/* 51253 */ MCD_OPC_CheckField, 21, 1, 1, 104, 139, 0, // Skip to: 86948 -/* 51260 */ MCD_OPC_Decode, 138, 32, 133, 2, // Opcode: UMINPv8i16 -/* 51265 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 51287 -/* 51270 */ MCD_OPC_CheckPredicate, 3, 89, 139, 0, // Skip to: 86948 -/* 51275 */ MCD_OPC_CheckField, 21, 1, 1, 82, 139, 0, // Skip to: 86948 -/* 51282 */ MCD_OPC_Decode, 192, 25, 133, 2, // Opcode: SQRDMULHv8i16 -/* 51287 */ MCD_OPC_FilterValue, 6, 72, 139, 0, // Skip to: 86948 -/* 51292 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 51295 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 51310 -/* 51300 */ MCD_OPC_CheckPredicate, 3, 59, 139, 0, // Skip to: 86948 -/* 51305 */ MCD_OPC_Decode, 185, 20, 138, 2, // Opcode: NEGv8i16 -/* 51310 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51325 -/* 51315 */ MCD_OPC_CheckPredicate, 3, 44, 139, 0, // Skip to: 86948 -/* 51320 */ MCD_OPC_Decode, 149, 8, 138, 2, // Opcode: FCVTMUv2f64 -/* 51325 */ MCD_OPC_FilterValue, 57, 34, 139, 0, // Skip to: 86948 -/* 51330 */ MCD_OPC_CheckPredicate, 4, 29, 139, 0, // Skip to: 86948 -/* 51335 */ MCD_OPC_Decode, 152, 8, 138, 2, // Opcode: FCVTMUv8f16 -/* 51340 */ MCD_OPC_FilterValue, 6, 185, 0, 0, // Skip to: 51530 -/* 51345 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 51348 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 51454 -/* 51353 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 51356 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51378 -/* 51361 */ MCD_OPC_CheckPredicate, 3, 254, 138, 0, // Skip to: 86948 -/* 51366 */ MCD_OPC_CheckField, 21, 1, 1, 247, 138, 0, // Skip to: 86948 -/* 51373 */ MCD_OPC_Decode, 201, 32, 133, 2, // Opcode: UMULLv8i16_v4i32 -/* 51378 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 51416 -/* 51383 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 51386 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51401 -/* 51391 */ MCD_OPC_CheckPredicate, 3, 224, 138, 0, // Skip to: 86948 -/* 51396 */ MCD_OPC_Decode, 241, 7, 138, 2, // Opcode: FCVTAUv2f64 -/* 51401 */ MCD_OPC_FilterValue, 57, 214, 138, 0, // Skip to: 86948 -/* 51406 */ MCD_OPC_CheckPredicate, 4, 209, 138, 0, // Skip to: 86948 -/* 51411 */ MCD_OPC_Decode, 244, 7, 138, 2, // Opcode: FCVTAUv8f16 -/* 51416 */ MCD_OPC_FilterValue, 3, 199, 138, 0, // Skip to: 86948 -/* 51421 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 51424 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51439 -/* 51429 */ MCD_OPC_CheckPredicate, 3, 186, 138, 0, // Skip to: 86948 -/* 51434 */ MCD_OPC_Decode, 197, 31, 138, 2, // Opcode: UCVTFv2f64 -/* 51439 */ MCD_OPC_FilterValue, 57, 176, 138, 0, // Skip to: 86948 -/* 51444 */ MCD_OPC_CheckPredicate, 4, 171, 138, 0, // Skip to: 86948 -/* 51449 */ MCD_OPC_Decode, 204, 31, 138, 2, // Opcode: UCVTFv8f16 -/* 51454 */ MCD_OPC_FilterValue, 1, 161, 138, 0, // Skip to: 86948 -/* 51459 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 51462 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51477 -/* 51467 */ MCD_OPC_CheckPredicate, 8, 148, 138, 0, // Skip to: 86948 -/* 51472 */ MCD_OPC_Decode, 166, 7, 169, 2, // Opcode: FCMLAv8f16 -/* 51477 */ MCD_OPC_FilterValue, 1, 138, 138, 0, // Skip to: 86948 -/* 51482 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 51485 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51500 -/* 51490 */ MCD_OPC_CheckPredicate, 3, 125, 138, 0, // Skip to: 86948 -/* 51495 */ MCD_OPC_Decode, 198, 9, 133, 2, // Opcode: FMAXNMPv2f64 -/* 51500 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 51515 -/* 51505 */ MCD_OPC_CheckPredicate, 3, 110, 138, 0, // Skip to: 86948 -/* 51510 */ MCD_OPC_Decode, 178, 6, 133, 2, // Opcode: FADDPv2f64 -/* 51515 */ MCD_OPC_FilterValue, 3, 100, 138, 0, // Skip to: 86948 -/* 51520 */ MCD_OPC_CheckPredicate, 3, 95, 138, 0, // Skip to: 86948 -/* 51525 */ MCD_OPC_Decode, 155, 11, 133, 2, // Opcode: FMULv2f64 -/* 51530 */ MCD_OPC_FilterValue, 7, 85, 138, 0, // Skip to: 86948 -/* 51535 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 51538 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 51599 -/* 51543 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 51546 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51561 -/* 51551 */ MCD_OPC_CheckPredicate, 8, 64, 138, 0, // Skip to: 86948 -/* 51556 */ MCD_OPC_Decode, 210, 6, 170, 2, // Opcode: FCADDv8f16 -/* 51561 */ MCD_OPC_FilterValue, 1, 54, 138, 0, // Skip to: 86948 -/* 51566 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 51569 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51584 -/* 51574 */ MCD_OPC_CheckPredicate, 3, 41, 138, 0, // Skip to: 86948 -/* 51579 */ MCD_OPC_Decode, 252, 6, 133, 2, // Opcode: FCMGEv2f64 -/* 51584 */ MCD_OPC_FilterValue, 1, 31, 138, 0, // Skip to: 86948 -/* 51589 */ MCD_OPC_CheckPredicate, 3, 26, 138, 0, // Skip to: 86948 -/* 51594 */ MCD_OPC_Decode, 224, 9, 133, 2, // Opcode: FMAXPv2f64 -/* 51599 */ MCD_OPC_FilterValue, 3, 16, 138, 0, // Skip to: 86948 -/* 51604 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 51607 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51629 -/* 51612 */ MCD_OPC_CheckPredicate, 3, 3, 138, 0, // Skip to: 86948 -/* 51617 */ MCD_OPC_CheckField, 21, 1, 1, 252, 137, 0, // Skip to: 86948 -/* 51624 */ MCD_OPC_Decode, 157, 6, 133, 2, // Opcode: FACGEv2f64 -/* 51629 */ MCD_OPC_FilterValue, 1, 242, 137, 0, // Skip to: 86948 -/* 51634 */ MCD_OPC_CheckPredicate, 3, 237, 137, 0, // Skip to: 86948 -/* 51639 */ MCD_OPC_CheckField, 21, 1, 1, 230, 137, 0, // Skip to: 86948 -/* 51646 */ MCD_OPC_Decode, 176, 9, 133, 2, // Opcode: FDIVv2f64 -/* 51651 */ MCD_OPC_FilterValue, 6, 220, 137, 0, // Skip to: 86948 -/* 51656 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 51659 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51681 -/* 51664 */ MCD_OPC_CheckPredicate, 9, 207, 137, 0, // Skip to: 86948 -/* 51669 */ MCD_OPC_CheckField, 21, 1, 0, 200, 137, 0, // Skip to: 86948 -/* 51676 */ MCD_OPC_Decode, 169, 23, 165, 2, // Opcode: SM3SS1 -/* 51681 */ MCD_OPC_FilterValue, 1, 190, 137, 0, // Skip to: 86948 -/* 51686 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 51689 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 51771 -/* 51694 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 51697 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 51742 -/* 51702 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 51705 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51720 -/* 51710 */ MCD_OPC_CheckPredicate, 9, 161, 137, 0, // Skip to: 86948 -/* 51715 */ MCD_OPC_Decode, 170, 23, 171, 2, // Opcode: SM3TT1A -/* 51720 */ MCD_OPC_FilterValue, 1, 151, 137, 0, // Skip to: 86948 -/* 51725 */ MCD_OPC_CheckPredicate, 6, 146, 137, 0, // Skip to: 86948 -/* 51730 */ MCD_OPC_CheckField, 12, 2, 0, 139, 137, 0, // Skip to: 86948 -/* 51737 */ MCD_OPC_Decode, 251, 22, 141, 2, // Opcode: SHA512H -/* 51742 */ MCD_OPC_FilterValue, 1, 129, 137, 0, // Skip to: 86948 -/* 51747 */ MCD_OPC_CheckPredicate, 9, 124, 137, 0, // Skip to: 86948 -/* 51752 */ MCD_OPC_CheckField, 21, 1, 1, 117, 137, 0, // Skip to: 86948 -/* 51759 */ MCD_OPC_CheckField, 12, 2, 0, 110, 137, 0, // Skip to: 86948 -/* 51766 */ MCD_OPC_Decode, 167, 23, 141, 2, // Opcode: SM3PARTW1 -/* 51771 */ MCD_OPC_FilterValue, 1, 77, 0, 0, // Skip to: 51853 -/* 51776 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 51779 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 51824 -/* 51784 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 51787 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51802 -/* 51792 */ MCD_OPC_CheckPredicate, 9, 79, 137, 0, // Skip to: 86948 -/* 51797 */ MCD_OPC_Decode, 171, 23, 171, 2, // Opcode: SM3TT1B -/* 51802 */ MCD_OPC_FilterValue, 1, 69, 137, 0, // Skip to: 86948 -/* 51807 */ MCD_OPC_CheckPredicate, 6, 64, 137, 0, // Skip to: 86948 -/* 51812 */ MCD_OPC_CheckField, 12, 2, 0, 57, 137, 0, // Skip to: 86948 -/* 51819 */ MCD_OPC_Decode, 252, 22, 141, 2, // Opcode: SHA512H2 -/* 51824 */ MCD_OPC_FilterValue, 1, 47, 137, 0, // Skip to: 86948 -/* 51829 */ MCD_OPC_CheckPredicate, 9, 42, 137, 0, // Skip to: 86948 -/* 51834 */ MCD_OPC_CheckField, 21, 1, 1, 35, 137, 0, // Skip to: 86948 -/* 51841 */ MCD_OPC_CheckField, 12, 2, 0, 28, 137, 0, // Skip to: 86948 -/* 51848 */ MCD_OPC_Decode, 168, 23, 141, 2, // Opcode: SM3PARTW2 -/* 51853 */ MCD_OPC_FilterValue, 2, 77, 0, 0, // Skip to: 51935 -/* 51858 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 51861 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 51906 -/* 51866 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 51869 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51884 -/* 51874 */ MCD_OPC_CheckPredicate, 9, 253, 136, 0, // Skip to: 86948 -/* 51879 */ MCD_OPC_Decode, 172, 23, 171, 2, // Opcode: SM3TT2A -/* 51884 */ MCD_OPC_FilterValue, 1, 243, 136, 0, // Skip to: 86948 -/* 51889 */ MCD_OPC_CheckPredicate, 6, 238, 136, 0, // Skip to: 86948 -/* 51894 */ MCD_OPC_CheckField, 12, 2, 0, 231, 136, 0, // Skip to: 86948 -/* 51901 */ MCD_OPC_Decode, 254, 22, 141, 2, // Opcode: SHA512SU1 -/* 51906 */ MCD_OPC_FilterValue, 1, 221, 136, 0, // Skip to: 86948 -/* 51911 */ MCD_OPC_CheckPredicate, 9, 216, 136, 0, // Skip to: 86948 -/* 51916 */ MCD_OPC_CheckField, 21, 1, 1, 209, 136, 0, // Skip to: 86948 -/* 51923 */ MCD_OPC_CheckField, 12, 2, 0, 202, 136, 0, // Skip to: 86948 -/* 51930 */ MCD_OPC_Decode, 175, 23, 133, 2, // Opcode: SM4ENCKEY -/* 51935 */ MCD_OPC_FilterValue, 3, 192, 136, 0, // Skip to: 86948 -/* 51940 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 51943 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51965 -/* 51948 */ MCD_OPC_CheckPredicate, 9, 179, 136, 0, // Skip to: 86948 -/* 51953 */ MCD_OPC_CheckField, 14, 1, 0, 172, 136, 0, // Skip to: 86948 -/* 51960 */ MCD_OPC_Decode, 173, 23, 171, 2, // Opcode: SM3TT2B -/* 51965 */ MCD_OPC_FilterValue, 1, 162, 136, 0, // Skip to: 86948 -/* 51970 */ MCD_OPC_CheckPredicate, 6, 157, 136, 0, // Skip to: 86948 -/* 51975 */ MCD_OPC_CheckField, 12, 3, 0, 150, 136, 0, // Skip to: 86948 -/* 51982 */ MCD_OPC_Decode, 183, 21, 133, 2, // Opcode: RAX1 -/* 51987 */ MCD_OPC_FilterValue, 10, 249, 23, 0, // Skip to: 58129 -/* 51992 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 51995 */ MCD_OPC_FilterValue, 0, 32, 6, 0, // Skip to: 53568 -/* 52000 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 52003 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 52025 -/* 52008 */ MCD_OPC_CheckPredicate, 3, 119, 136, 0, // Skip to: 86948 -/* 52013 */ MCD_OPC_CheckField, 21, 1, 1, 112, 136, 0, // Skip to: 86948 -/* 52020 */ MCD_OPC_Decode, 164, 22, 234, 1, // Opcode: SADDLv2i32_v2i64 -/* 52025 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 52047 -/* 52030 */ MCD_OPC_CheckPredicate, 3, 97, 136, 0, // Skip to: 86948 -/* 52035 */ MCD_OPC_CheckField, 21, 1, 1, 90, 136, 0, // Skip to: 86948 -/* 52042 */ MCD_OPC_Decode, 128, 23, 238, 1, // Opcode: SHADDv2i32 -/* 52047 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 52069 -/* 52052 */ MCD_OPC_CheckPredicate, 3, 75, 136, 0, // Skip to: 86948 -/* 52057 */ MCD_OPC_CheckField, 16, 6, 32, 68, 136, 0, // Skip to: 86948 -/* 52064 */ MCD_OPC_Decode, 210, 21, 239, 1, // Opcode: REV64v2i32 -/* 52069 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 52091 -/* 52074 */ MCD_OPC_CheckPredicate, 3, 53, 136, 0, // Skip to: 86948 -/* 52079 */ MCD_OPC_CheckField, 21, 1, 1, 46, 136, 0, // Skip to: 86948 -/* 52086 */ MCD_OPC_Decode, 177, 24, 238, 1, // Opcode: SQADDv2i32 -/* 52091 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 52113 -/* 52096 */ MCD_OPC_CheckPredicate, 3, 31, 136, 0, // Skip to: 86948 -/* 52101 */ MCD_OPC_CheckField, 21, 1, 1, 24, 136, 0, // Skip to: 86948 -/* 52108 */ MCD_OPC_Decode, 173, 22, 242, 1, // Opcode: SADDWv2i32_v2i64 -/* 52113 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 52135 -/* 52118 */ MCD_OPC_CheckPredicate, 3, 9, 136, 0, // Skip to: 86948 -/* 52123 */ MCD_OPC_CheckField, 21, 1, 1, 2, 136, 0, // Skip to: 86948 -/* 52130 */ MCD_OPC_Decode, 184, 26, 238, 1, // Opcode: SRHADDv2i32 -/* 52135 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 52157 -/* 52140 */ MCD_OPC_CheckPredicate, 3, 243, 135, 0, // Skip to: 86948 -/* 52145 */ MCD_OPC_CheckField, 21, 1, 0, 236, 135, 0, // Skip to: 86948 -/* 52152 */ MCD_OPC_Decode, 197, 34, 238, 1, // Opcode: UZP1v2i32 -/* 52157 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 52179 -/* 52162 */ MCD_OPC_CheckPredicate, 3, 221, 135, 0, // Skip to: 86948 -/* 52167 */ MCD_OPC_CheckField, 21, 1, 1, 214, 135, 0, // Skip to: 86948 -/* 52174 */ MCD_OPC_Decode, 222, 20, 238, 1, // Opcode: ORRv8i8 -/* 52179 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 52201 -/* 52184 */ MCD_OPC_CheckPredicate, 3, 199, 135, 0, // Skip to: 86948 -/* 52189 */ MCD_OPC_CheckField, 21, 1, 1, 192, 135, 0, // Skip to: 86948 -/* 52196 */ MCD_OPC_Decode, 162, 27, 234, 1, // Opcode: SSUBLv2i32_v2i64 -/* 52201 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 52223 -/* 52206 */ MCD_OPC_CheckPredicate, 3, 177, 135, 0, // Skip to: 86948 -/* 52211 */ MCD_OPC_CheckField, 21, 1, 1, 170, 135, 0, // Skip to: 86948 -/* 52218 */ MCD_OPC_Decode, 154, 23, 238, 1, // Opcode: SHSUBv2i32 -/* 52223 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 52284 -/* 52228 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 52231 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52246 -/* 52236 */ MCD_OPC_CheckPredicate, 3, 147, 135, 0, // Skip to: 86948 -/* 52241 */ MCD_OPC_Decode, 214, 30, 238, 1, // Opcode: TRN1v2i32 -/* 52246 */ MCD_OPC_FilterValue, 1, 137, 135, 0, // Skip to: 86948 -/* 52251 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 52254 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52269 -/* 52259 */ MCD_OPC_CheckPredicate, 3, 124, 135, 0, // Skip to: 86948 -/* 52264 */ MCD_OPC_Decode, 153, 22, 239, 1, // Opcode: SADDLPv2i32_v1i64 -/* 52269 */ MCD_OPC_FilterValue, 1, 114, 135, 0, // Skip to: 86948 -/* 52274 */ MCD_OPC_CheckPredicate, 3, 109, 135, 0, // Skip to: 86948 -/* 52279 */ MCD_OPC_Decode, 128, 35, 244, 1, // Opcode: XTNv2i32 -/* 52284 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 52306 -/* 52289 */ MCD_OPC_CheckPredicate, 3, 94, 135, 0, // Skip to: 86948 -/* 52294 */ MCD_OPC_CheckField, 21, 1, 1, 87, 135, 0, // Skip to: 86948 -/* 52301 */ MCD_OPC_Decode, 159, 26, 238, 1, // Opcode: SQSUBv2i32 -/* 52306 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 52328 -/* 52311 */ MCD_OPC_CheckPredicate, 3, 72, 135, 0, // Skip to: 86948 -/* 52316 */ MCD_OPC_CheckField, 21, 1, 1, 65, 135, 0, // Skip to: 86948 -/* 52323 */ MCD_OPC_Decode, 168, 27, 242, 1, // Opcode: SSUBWv2i32_v2i64 -/* 52328 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 52350 -/* 52333 */ MCD_OPC_CheckPredicate, 3, 50, 135, 0, // Skip to: 86948 -/* 52338 */ MCD_OPC_CheckField, 21, 1, 1, 43, 135, 0, // Skip to: 86948 -/* 52345 */ MCD_OPC_Decode, 218, 3, 238, 1, // Opcode: CMGTv2i32 -/* 52350 */ MCD_OPC_FilterValue, 14, 40, 0, 0, // Skip to: 52395 -/* 52355 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 52358 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52373 -/* 52363 */ MCD_OPC_CheckPredicate, 3, 20, 135, 0, // Skip to: 86948 -/* 52368 */ MCD_OPC_Decode, 142, 35, 238, 1, // Opcode: ZIP1v2i32 -/* 52373 */ MCD_OPC_FilterValue, 1, 10, 135, 0, // Skip to: 86948 -/* 52378 */ MCD_OPC_CheckPredicate, 3, 5, 135, 0, // Skip to: 86948 -/* 52383 */ MCD_OPC_CheckField, 16, 5, 0, 254, 134, 0, // Skip to: 86948 -/* 52390 */ MCD_OPC_Decode, 146, 30, 248, 1, // Opcode: SUQADDv2i32 -/* 52395 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 52417 -/* 52400 */ MCD_OPC_CheckPredicate, 3, 239, 134, 0, // Skip to: 86948 -/* 52405 */ MCD_OPC_CheckField, 21, 1, 1, 232, 134, 0, // Skip to: 86948 -/* 52412 */ MCD_OPC_Decode, 202, 3, 238, 1, // Opcode: CMGEv2i32 -/* 52417 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 52439 -/* 52422 */ MCD_OPC_CheckPredicate, 3, 217, 134, 0, // Skip to: 86948 -/* 52427 */ MCD_OPC_CheckField, 21, 1, 1, 210, 134, 0, // Skip to: 86948 -/* 52434 */ MCD_OPC_Decode, 142, 1, 252, 1, // Opcode: ADDHNv2i64_v2i32 -/* 52439 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 52461 -/* 52444 */ MCD_OPC_CheckPredicate, 3, 195, 134, 0, // Skip to: 86948 -/* 52449 */ MCD_OPC_CheckField, 21, 1, 1, 188, 134, 0, // Skip to: 86948 -/* 52456 */ MCD_OPC_Decode, 229, 26, 238, 1, // Opcode: SSHLv2i32 -/* 52461 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 52499 -/* 52466 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 52469 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 52484 -/* 52474 */ MCD_OPC_CheckPredicate, 3, 165, 134, 0, // Skip to: 86948 -/* 52479 */ MCD_OPC_Decode, 165, 3, 239, 1, // Opcode: CLSv2i32 -/* 52484 */ MCD_OPC_FilterValue, 33, 155, 134, 0, // Skip to: 86948 -/* 52489 */ MCD_OPC_CheckPredicate, 3, 150, 134, 0, // Skip to: 86948 -/* 52494 */ MCD_OPC_Decode, 169, 26, 244, 1, // Opcode: SQXTNv2i32 -/* 52499 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 52521 -/* 52504 */ MCD_OPC_CheckPredicate, 3, 135, 134, 0, // Skip to: 86948 -/* 52509 */ MCD_OPC_CheckField, 21, 1, 1, 128, 134, 0, // Skip to: 86948 -/* 52516 */ MCD_OPC_Decode, 244, 25, 238, 1, // Opcode: SQSHLv2i32 -/* 52521 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 52543 -/* 52526 */ MCD_OPC_CheckPredicate, 3, 113, 134, 0, // Skip to: 86948 -/* 52531 */ MCD_OPC_CheckField, 21, 1, 1, 106, 134, 0, // Skip to: 86948 -/* 52538 */ MCD_OPC_Decode, 247, 21, 254, 1, // Opcode: SABALv2i32_v2i64 -/* 52543 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 52565 -/* 52548 */ MCD_OPC_CheckPredicate, 3, 91, 134, 0, // Skip to: 86948 -/* 52553 */ MCD_OPC_CheckField, 21, 1, 1, 84, 134, 0, // Skip to: 86948 -/* 52560 */ MCD_OPC_Decode, 199, 26, 238, 1, // Opcode: SRSHLv2i32 -/* 52565 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 52587 -/* 52570 */ MCD_OPC_CheckPredicate, 3, 69, 134, 0, // Skip to: 86948 -/* 52575 */ MCD_OPC_CheckField, 21, 1, 0, 62, 134, 0, // Skip to: 86948 -/* 52582 */ MCD_OPC_Decode, 212, 34, 238, 1, // Opcode: UZP2v2i32 -/* 52587 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 52609 -/* 52592 */ MCD_OPC_CheckPredicate, 3, 47, 134, 0, // Skip to: 86948 -/* 52597 */ MCD_OPC_CheckField, 21, 1, 1, 40, 134, 0, // Skip to: 86948 -/* 52604 */ MCD_OPC_Decode, 199, 25, 238, 1, // Opcode: SQRSHLv2i32 -/* 52609 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 52631 -/* 52614 */ MCD_OPC_CheckPredicate, 3, 25, 134, 0, // Skip to: 86948 -/* 52619 */ MCD_OPC_CheckField, 21, 1, 1, 18, 134, 0, // Skip to: 86948 -/* 52626 */ MCD_OPC_Decode, 211, 29, 252, 1, // Opcode: SUBHNv2i64_v2i32 -/* 52631 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 52653 -/* 52636 */ MCD_OPC_CheckPredicate, 3, 3, 134, 0, // Skip to: 86948 -/* 52641 */ MCD_OPC_CheckField, 21, 1, 1, 252, 133, 0, // Skip to: 86948 -/* 52648 */ MCD_OPC_Decode, 201, 23, 238, 1, // Opcode: SMAXv2i32 -/* 52653 */ MCD_OPC_FilterValue, 26, 40, 0, 0, // Skip to: 52698 -/* 52658 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 52661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52676 -/* 52666 */ MCD_OPC_CheckPredicate, 3, 229, 133, 0, // Skip to: 86948 -/* 52671 */ MCD_OPC_Decode, 229, 30, 238, 1, // Opcode: TRN2v2i32 -/* 52676 */ MCD_OPC_FilterValue, 1, 219, 133, 0, // Skip to: 86948 -/* 52681 */ MCD_OPC_CheckPredicate, 3, 214, 133, 0, // Skip to: 86948 -/* 52686 */ MCD_OPC_CheckField, 16, 5, 0, 207, 133, 0, // Skip to: 86948 -/* 52693 */ MCD_OPC_Decode, 147, 22, 248, 1, // Opcode: SADALPv2i32_v1i64 -/* 52698 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 52720 -/* 52703 */ MCD_OPC_CheckPredicate, 3, 192, 133, 0, // Skip to: 86948 -/* 52708 */ MCD_OPC_CheckField, 21, 1, 1, 185, 133, 0, // Skip to: 86948 -/* 52715 */ MCD_OPC_Decode, 231, 23, 238, 1, // Opcode: SMINv2i32 -/* 52720 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 52742 -/* 52725 */ MCD_OPC_CheckPredicate, 3, 170, 133, 0, // Skip to: 86948 -/* 52730 */ MCD_OPC_CheckField, 21, 1, 1, 163, 133, 0, // Skip to: 86948 -/* 52737 */ MCD_OPC_Decode, 131, 22, 234, 1, // Opcode: SABDLv2i32_v2i64 -/* 52742 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 52764 -/* 52747 */ MCD_OPC_CheckPredicate, 3, 148, 133, 0, // Skip to: 86948 -/* 52752 */ MCD_OPC_CheckField, 21, 1, 1, 141, 133, 0, // Skip to: 86948 -/* 52759 */ MCD_OPC_Decode, 141, 22, 238, 1, // Opcode: SABDv2i32 -/* 52764 */ MCD_OPC_FilterValue, 30, 40, 0, 0, // Skip to: 52809 -/* 52769 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 52772 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52787 -/* 52777 */ MCD_OPC_CheckPredicate, 3, 118, 133, 0, // Skip to: 86948 -/* 52782 */ MCD_OPC_Decode, 157, 35, 238, 1, // Opcode: ZIP2v2i32 -/* 52787 */ MCD_OPC_FilterValue, 1, 108, 133, 0, // Skip to: 86948 -/* 52792 */ MCD_OPC_CheckPredicate, 3, 103, 133, 0, // Skip to: 86948 -/* 52797 */ MCD_OPC_CheckField, 16, 5, 0, 96, 133, 0, // Skip to: 86948 -/* 52804 */ MCD_OPC_Decode, 158, 24, 239, 1, // Opcode: SQABSv2i32 -/* 52809 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 52831 -/* 52814 */ MCD_OPC_CheckPredicate, 3, 81, 133, 0, // Skip to: 86948 -/* 52819 */ MCD_OPC_CheckField, 21, 1, 1, 74, 133, 0, // Skip to: 86948 -/* 52826 */ MCD_OPC_Decode, 253, 21, 130, 2, // Opcode: SABAv2i32 -/* 52831 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 52853 -/* 52836 */ MCD_OPC_CheckPredicate, 3, 59, 133, 0, // Skip to: 86948 -/* 52841 */ MCD_OPC_CheckField, 21, 1, 1, 52, 133, 0, // Skip to: 86948 -/* 52848 */ MCD_OPC_Decode, 238, 23, 254, 1, // Opcode: SMLALv2i32_v2i64 -/* 52853 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 52875 -/* 52858 */ MCD_OPC_CheckPredicate, 3, 37, 133, 0, // Skip to: 86948 -/* 52863 */ MCD_OPC_CheckField, 21, 1, 1, 30, 133, 0, // Skip to: 86948 -/* 52870 */ MCD_OPC_Decode, 196, 1, 238, 1, // Opcode: ADDv2i32 -/* 52875 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 52913 -/* 52880 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 52883 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 52898 -/* 52888 */ MCD_OPC_CheckPredicate, 3, 7, 133, 0, // Skip to: 86948 -/* 52893 */ MCD_OPC_Decode, 219, 3, 239, 1, // Opcode: CMGTv2i32rz -/* 52898 */ MCD_OPC_FilterValue, 33, 253, 132, 0, // Skip to: 86948 -/* 52903 */ MCD_OPC_CheckPredicate, 3, 248, 132, 0, // Skip to: 86948 -/* 52908 */ MCD_OPC_Decode, 146, 12, 239, 1, // Opcode: FRINTPv2f32 -/* 52913 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 52935 -/* 52918 */ MCD_OPC_CheckPredicate, 3, 233, 132, 0, // Skip to: 86948 -/* 52923 */ MCD_OPC_CheckField, 21, 1, 1, 226, 132, 0, // Skip to: 86948 -/* 52930 */ MCD_OPC_Decode, 235, 4, 238, 1, // Opcode: CMTSTv2i32 -/* 52935 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 52957 -/* 52940 */ MCD_OPC_CheckPredicate, 3, 211, 132, 0, // Skip to: 86948 -/* 52945 */ MCD_OPC_CheckField, 21, 1, 1, 204, 132, 0, // Skip to: 86948 -/* 52952 */ MCD_OPC_Decode, 210, 24, 254, 1, // Opcode: SQDMLALv2i32_v2i64 -/* 52957 */ MCD_OPC_FilterValue, 37, 33, 0, 0, // Skip to: 52995 -/* 52962 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 52965 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52980 -/* 52970 */ MCD_OPC_CheckPredicate, 10, 181, 132, 0, // Skip to: 86948 -/* 52975 */ MCD_OPC_Decode, 232, 22, 130, 2, // Opcode: SDOTv8i8 -/* 52980 */ MCD_OPC_FilterValue, 1, 171, 132, 0, // Skip to: 86948 -/* 52985 */ MCD_OPC_CheckPredicate, 3, 166, 132, 0, // Skip to: 86948 -/* 52990 */ MCD_OPC_Decode, 210, 19, 130, 2, // Opcode: MLAv2i32 -/* 52995 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 53033 -/* 53000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 53003 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53018 -/* 53008 */ MCD_OPC_CheckPredicate, 3, 143, 132, 0, // Skip to: 86948 -/* 53013 */ MCD_OPC_Decode, 187, 3, 239, 1, // Opcode: CMEQv2i32rz -/* 53018 */ MCD_OPC_FilterValue, 33, 133, 132, 0, // Skip to: 86948 -/* 53023 */ MCD_OPC_CheckPredicate, 3, 128, 132, 0, // Skip to: 86948 -/* 53028 */ MCD_OPC_Decode, 168, 12, 239, 1, // Opcode: FRINTZv2f32 -/* 53033 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 53055 -/* 53038 */ MCD_OPC_CheckPredicate, 3, 113, 132, 0, // Skip to: 86948 -/* 53043 */ MCD_OPC_CheckField, 21, 1, 1, 106, 132, 0, // Skip to: 86948 -/* 53050 */ MCD_OPC_Decode, 158, 20, 238, 1, // Opcode: MULv2i32 -/* 53055 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 53077 -/* 53060 */ MCD_OPC_CheckPredicate, 3, 91, 132, 0, // Skip to: 86948 -/* 53065 */ MCD_OPC_CheckField, 21, 1, 1, 84, 132, 0, // Skip to: 86948 -/* 53072 */ MCD_OPC_Decode, 248, 23, 254, 1, // Opcode: SMLSLv2i32_v2i64 -/* 53077 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 53099 -/* 53082 */ MCD_OPC_CheckPredicate, 3, 69, 132, 0, // Skip to: 86948 -/* 53087 */ MCD_OPC_CheckField, 21, 1, 1, 62, 132, 0, // Skip to: 86948 -/* 53094 */ MCD_OPC_Decode, 178, 23, 238, 1, // Opcode: SMAXPv2i32 -/* 53099 */ MCD_OPC_FilterValue, 42, 33, 0, 0, // Skip to: 53137 -/* 53104 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 53107 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53122 -/* 53112 */ MCD_OPC_CheckPredicate, 3, 39, 132, 0, // Skip to: 86948 -/* 53117 */ MCD_OPC_Decode, 128, 4, 239, 1, // Opcode: CMLTv2i32rz -/* 53122 */ MCD_OPC_FilterValue, 33, 29, 132, 0, // Skip to: 86948 -/* 53127 */ MCD_OPC_CheckPredicate, 3, 24, 132, 0, // Skip to: 86948 -/* 53132 */ MCD_OPC_Decode, 194, 8, 239, 1, // Opcode: FCVTPSv2f32 -/* 53137 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 53159 -/* 53142 */ MCD_OPC_CheckPredicate, 3, 9, 132, 0, // Skip to: 86948 -/* 53147 */ MCD_OPC_CheckField, 21, 1, 1, 2, 132, 0, // Skip to: 86948 -/* 53154 */ MCD_OPC_Decode, 208, 23, 238, 1, // Opcode: SMINPv2i32 -/* 53159 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 53181 -/* 53164 */ MCD_OPC_CheckPredicate, 3, 243, 131, 0, // Skip to: 86948 -/* 53169 */ MCD_OPC_CheckField, 21, 1, 1, 236, 131, 0, // Skip to: 86948 -/* 53176 */ MCD_OPC_Decode, 222, 24, 254, 1, // Opcode: SQDMLSLv2i32_v2i64 -/* 53181 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 53203 -/* 53186 */ MCD_OPC_CheckPredicate, 3, 221, 131, 0, // Skip to: 86948 -/* 53191 */ MCD_OPC_CheckField, 21, 1, 1, 214, 131, 0, // Skip to: 86948 -/* 53198 */ MCD_OPC_Decode, 233, 24, 238, 1, // Opcode: SQDMULHv2i32 -/* 53203 */ MCD_OPC_FilterValue, 46, 33, 0, 0, // Skip to: 53241 -/* 53208 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 53211 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53226 -/* 53216 */ MCD_OPC_CheckPredicate, 3, 191, 131, 0, // Skip to: 86948 -/* 53221 */ MCD_OPC_Decode, 132, 1, 239, 1, // Opcode: ABSv2i32 -/* 53226 */ MCD_OPC_FilterValue, 33, 181, 131, 0, // Skip to: 86948 -/* 53231 */ MCD_OPC_CheckPredicate, 3, 176, 131, 0, // Skip to: 86948 -/* 53236 */ MCD_OPC_Decode, 243, 8, 239, 1, // Opcode: FCVTZSv2f32 -/* 53241 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 53263 -/* 53246 */ MCD_OPC_CheckPredicate, 3, 161, 131, 0, // Skip to: 86948 -/* 53251 */ MCD_OPC_CheckField, 21, 1, 1, 154, 131, 0, // Skip to: 86948 -/* 53258 */ MCD_OPC_Decode, 150, 1, 238, 1, // Opcode: ADDPv2i32 -/* 53263 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 53285 -/* 53268 */ MCD_OPC_CheckPredicate, 3, 139, 131, 0, // Skip to: 86948 -/* 53273 */ MCD_OPC_CheckField, 21, 1, 1, 132, 131, 0, // Skip to: 86948 -/* 53280 */ MCD_OPC_Decode, 141, 24, 234, 1, // Opcode: SMULLv2i32_v2i64 -/* 53285 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 53307 -/* 53290 */ MCD_OPC_CheckPredicate, 3, 117, 131, 0, // Skip to: 86948 -/* 53295 */ MCD_OPC_CheckField, 21, 1, 1, 110, 131, 0, // Skip to: 86948 -/* 53302 */ MCD_OPC_Decode, 146, 10, 238, 1, // Opcode: FMINNMv2f32 -/* 53307 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 53360 -/* 53312 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 53315 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53330 -/* 53320 */ MCD_OPC_CheckPredicate, 3, 87, 131, 0, // Skip to: 86948 -/* 53325 */ MCD_OPC_Decode, 147, 7, 239, 1, // Opcode: FCMGTv2i32rz -/* 53330 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 53345 -/* 53335 */ MCD_OPC_CheckPredicate, 3, 72, 131, 0, // Skip to: 86948 -/* 53340 */ MCD_OPC_Decode, 217, 33, 239, 1, // Opcode: URECPEv2i32 -/* 53345 */ MCD_OPC_FilterValue, 48, 62, 131, 0, // Skip to: 86948 -/* 53350 */ MCD_OPC_CheckPredicate, 4, 57, 131, 0, // Skip to: 86948 -/* 53355 */ MCD_OPC_Decode, 137, 10, 249, 1, // Opcode: FMINNMVv4i16v -/* 53360 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 53382 -/* 53365 */ MCD_OPC_CheckPredicate, 3, 42, 131, 0, // Skip to: 86948 -/* 53370 */ MCD_OPC_CheckField, 21, 1, 1, 35, 131, 0, // Skip to: 86948 -/* 53377 */ MCD_OPC_Decode, 205, 10, 130, 2, // Opcode: FMLSv2f32 -/* 53382 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 53404 -/* 53387 */ MCD_OPC_CheckPredicate, 3, 20, 131, 0, // Skip to: 86948 -/* 53392 */ MCD_OPC_CheckField, 21, 1, 1, 13, 131, 0, // Skip to: 86948 -/* 53399 */ MCD_OPC_Decode, 246, 24, 234, 1, // Opcode: SQDMULLv2i32_v2i64 -/* 53404 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 53426 -/* 53409 */ MCD_OPC_CheckPredicate, 3, 254, 130, 0, // Skip to: 86948 -/* 53414 */ MCD_OPC_CheckField, 21, 1, 1, 247, 130, 0, // Skip to: 86948 -/* 53421 */ MCD_OPC_Decode, 227, 12, 238, 1, // Opcode: FSUBv2f32 -/* 53426 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 53464 -/* 53431 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 53434 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53449 -/* 53439 */ MCD_OPC_CheckPredicate, 3, 224, 130, 0, // Skip to: 86948 -/* 53444 */ MCD_OPC_Decode, 231, 6, 239, 1, // Opcode: FCMEQv2i32rz -/* 53449 */ MCD_OPC_FilterValue, 33, 214, 130, 0, // Skip to: 86948 -/* 53454 */ MCD_OPC_CheckPredicate, 3, 209, 130, 0, // Skip to: 86948 -/* 53459 */ MCD_OPC_Decode, 202, 11, 239, 1, // Opcode: FRECPEv2f32 -/* 53464 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 53486 -/* 53469 */ MCD_OPC_CheckPredicate, 3, 194, 130, 0, // Skip to: 86948 -/* 53474 */ MCD_OPC_CheckField, 16, 6, 32, 187, 130, 0, // Skip to: 86948 -/* 53481 */ MCD_OPC_Decode, 185, 7, 239, 1, // Opcode: FCMLTv2i32rz -/* 53486 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 53508 -/* 53491 */ MCD_OPC_CheckPredicate, 3, 172, 130, 0, // Skip to: 86948 -/* 53496 */ MCD_OPC_CheckField, 21, 1, 1, 165, 130, 0, // Skip to: 86948 -/* 53503 */ MCD_OPC_Decode, 172, 10, 238, 1, // Opcode: FMINv2f32 -/* 53508 */ MCD_OPC_FilterValue, 62, 33, 0, 0, // Skip to: 53546 -/* 53513 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 53516 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53531 -/* 53521 */ MCD_OPC_CheckPredicate, 3, 142, 130, 0, // Skip to: 86948 -/* 53526 */ MCD_OPC_Decode, 145, 6, 239, 1, // Opcode: FABSv2f32 -/* 53531 */ MCD_OPC_FilterValue, 48, 132, 130, 0, // Skip to: 86948 -/* 53536 */ MCD_OPC_CheckPredicate, 4, 127, 130, 0, // Skip to: 86948 -/* 53541 */ MCD_OPC_Decode, 163, 10, 249, 1, // Opcode: FMINVv4i16v -/* 53546 */ MCD_OPC_FilterValue, 63, 117, 130, 0, // Skip to: 86948 -/* 53551 */ MCD_OPC_CheckPredicate, 3, 112, 130, 0, // Skip to: 86948 -/* 53556 */ MCD_OPC_CheckField, 21, 1, 1, 105, 130, 0, // Skip to: 86948 -/* 53563 */ MCD_OPC_Decode, 190, 12, 238, 1, // Opcode: FRSQRTSv2f32 -/* 53568 */ MCD_OPC_FilterValue, 1, 126, 5, 0, // Skip to: 54979 -/* 53573 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 53576 */ MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 53716 -/* 53581 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 53584 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 53606 -/* 53589 */ MCD_OPC_CheckPredicate, 3, 74, 130, 0, // Skip to: 86948 -/* 53594 */ MCD_OPC_CheckField, 21, 1, 1, 67, 130, 0, // Skip to: 86948 -/* 53601 */ MCD_OPC_Decode, 154, 31, 234, 1, // Opcode: UADDLv2i32_v2i64 -/* 53606 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 53628 -/* 53611 */ MCD_OPC_CheckPredicate, 3, 52, 130, 0, // Skip to: 86948 -/* 53616 */ MCD_OPC_CheckField, 21, 1, 1, 45, 130, 0, // Skip to: 86948 -/* 53623 */ MCD_OPC_Decode, 221, 31, 238, 1, // Opcode: UHADDv2i32 -/* 53628 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 53650 -/* 53633 */ MCD_OPC_CheckPredicate, 3, 30, 130, 0, // Skip to: 86948 -/* 53638 */ MCD_OPC_CheckField, 21, 1, 1, 23, 130, 0, // Skip to: 86948 -/* 53645 */ MCD_OPC_Decode, 216, 32, 238, 1, // Opcode: UQADDv2i32 -/* 53650 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 53672 -/* 53655 */ MCD_OPC_CheckPredicate, 3, 8, 130, 0, // Skip to: 86948 -/* 53660 */ MCD_OPC_CheckField, 21, 1, 1, 1, 130, 0, // Skip to: 86948 -/* 53667 */ MCD_OPC_Decode, 164, 31, 242, 1, // Opcode: UADDWv2i32_v2i64 -/* 53672 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 53694 -/* 53677 */ MCD_OPC_CheckPredicate, 3, 242, 129, 0, // Skip to: 86948 -/* 53682 */ MCD_OPC_CheckField, 21, 1, 1, 235, 129, 0, // Skip to: 86948 -/* 53689 */ MCD_OPC_Decode, 220, 33, 238, 1, // Opcode: URHADDv2i32 -/* 53694 */ MCD_OPC_FilterValue, 7, 225, 129, 0, // Skip to: 86948 -/* 53699 */ MCD_OPC_CheckPredicate, 3, 220, 129, 0, // Skip to: 86948 -/* 53704 */ MCD_OPC_CheckField, 21, 1, 1, 213, 129, 0, // Skip to: 86948 -/* 53711 */ MCD_OPC_Decode, 196, 2, 130, 2, // Opcode: BITv8i8 -/* 53716 */ MCD_OPC_FilterValue, 1, 211, 0, 0, // Skip to: 53932 -/* 53721 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 53724 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 53746 -/* 53729 */ MCD_OPC_CheckPredicate, 3, 190, 129, 0, // Skip to: 86948 -/* 53734 */ MCD_OPC_CheckField, 21, 1, 1, 183, 129, 0, // Skip to: 86948 -/* 53741 */ MCD_OPC_Decode, 165, 34, 234, 1, // Opcode: USUBLv2i32_v2i64 -/* 53746 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 53768 -/* 53751 */ MCD_OPC_CheckPredicate, 3, 168, 129, 0, // Skip to: 86948 -/* 53756 */ MCD_OPC_CheckField, 21, 1, 1, 161, 129, 0, // Skip to: 86948 -/* 53763 */ MCD_OPC_Decode, 227, 31, 238, 1, // Opcode: UHSUBv2i32 -/* 53768 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 53806 -/* 53773 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 53776 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53791 -/* 53781 */ MCD_OPC_CheckPredicate, 3, 138, 129, 0, // Skip to: 86948 -/* 53786 */ MCD_OPC_Decode, 143, 31, 239, 1, // Opcode: UADDLPv2i32_v1i64 -/* 53791 */ MCD_OPC_FilterValue, 33, 128, 129, 0, // Skip to: 86948 -/* 53796 */ MCD_OPC_CheckPredicate, 3, 123, 129, 0, // Skip to: 86948 -/* 53801 */ MCD_OPC_Decode, 178, 26, 244, 1, // Opcode: SQXTUNv2i32 -/* 53806 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 53828 -/* 53811 */ MCD_OPC_CheckPredicate, 3, 108, 129, 0, // Skip to: 86948 -/* 53816 */ MCD_OPC_CheckField, 21, 1, 1, 101, 129, 0, // Skip to: 86948 -/* 53823 */ MCD_OPC_Decode, 202, 33, 238, 1, // Opcode: UQSUBv2i32 -/* 53828 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 53850 -/* 53833 */ MCD_OPC_CheckPredicate, 3, 86, 129, 0, // Skip to: 86948 -/* 53838 */ MCD_OPC_CheckField, 21, 1, 1, 79, 129, 0, // Skip to: 86948 -/* 53845 */ MCD_OPC_Decode, 171, 34, 242, 1, // Opcode: USUBWv2i32_v2i64 -/* 53850 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 53872 -/* 53855 */ MCD_OPC_CheckPredicate, 3, 64, 129, 0, // Skip to: 86948 -/* 53860 */ MCD_OPC_CheckField, 21, 1, 1, 57, 129, 0, // Skip to: 86948 -/* 53867 */ MCD_OPC_Decode, 232, 3, 238, 1, // Opcode: CMHIv2i32 -/* 53872 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 53910 -/* 53877 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 53880 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53895 -/* 53885 */ MCD_OPC_CheckPredicate, 3, 34, 129, 0, // Skip to: 86948 -/* 53890 */ MCD_OPC_Decode, 150, 34, 248, 1, // Opcode: USQADDv2i32 -/* 53895 */ MCD_OPC_FilterValue, 33, 24, 129, 0, // Skip to: 86948 -/* 53900 */ MCD_OPC_CheckPredicate, 3, 19, 129, 0, // Skip to: 86948 -/* 53905 */ MCD_OPC_Decode, 134, 23, 129, 2, // Opcode: SHLLv2i32 -/* 53910 */ MCD_OPC_FilterValue, 7, 9, 129, 0, // Skip to: 86948 -/* 53915 */ MCD_OPC_CheckPredicate, 3, 4, 129, 0, // Skip to: 86948 -/* 53920 */ MCD_OPC_CheckField, 21, 1, 1, 253, 128, 0, // Skip to: 86948 -/* 53927 */ MCD_OPC_Decode, 240, 3, 238, 1, // Opcode: CMHSv2i32 -/* 53932 */ MCD_OPC_FilterValue, 2, 173, 0, 0, // Skip to: 54110 -/* 53937 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 53940 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 53962 -/* 53945 */ MCD_OPC_CheckPredicate, 3, 230, 128, 0, // Skip to: 86948 -/* 53950 */ MCD_OPC_CheckField, 21, 1, 1, 223, 128, 0, // Skip to: 86948 -/* 53957 */ MCD_OPC_Decode, 177, 21, 252, 1, // Opcode: RADDHNv2i64_v2i32 -/* 53962 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 53984 -/* 53967 */ MCD_OPC_CheckPredicate, 3, 208, 128, 0, // Skip to: 86948 -/* 53972 */ MCD_OPC_CheckField, 21, 1, 1, 201, 128, 0, // Skip to: 86948 -/* 53979 */ MCD_OPC_Decode, 131, 34, 238, 1, // Opcode: USHLv2i32 -/* 53984 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 54022 -/* 53989 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 53992 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54007 -/* 53997 */ MCD_OPC_CheckPredicate, 3, 178, 128, 0, // Skip to: 86948 -/* 54002 */ MCD_OPC_Decode, 177, 3, 239, 1, // Opcode: CLZv2i32 -/* 54007 */ MCD_OPC_FilterValue, 33, 168, 128, 0, // Skip to: 86948 -/* 54012 */ MCD_OPC_CheckPredicate, 3, 163, 128, 0, // Skip to: 86948 -/* 54017 */ MCD_OPC_Decode, 212, 33, 244, 1, // Opcode: UQXTNv2i32 -/* 54022 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 54044 -/* 54027 */ MCD_OPC_CheckPredicate, 3, 148, 128, 0, // Skip to: 86948 -/* 54032 */ MCD_OPC_CheckField, 21, 1, 1, 141, 128, 0, // Skip to: 86948 -/* 54039 */ MCD_OPC_Decode, 168, 33, 238, 1, // Opcode: UQSHLv2i32 -/* 54044 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 54066 -/* 54049 */ MCD_OPC_CheckPredicate, 3, 126, 128, 0, // Skip to: 86948 -/* 54054 */ MCD_OPC_CheckField, 21, 1, 1, 119, 128, 0, // Skip to: 86948 -/* 54061 */ MCD_OPC_Decode, 237, 30, 254, 1, // Opcode: UABALv2i32_v2i64 -/* 54066 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 54088 -/* 54071 */ MCD_OPC_CheckPredicate, 3, 104, 128, 0, // Skip to: 86948 -/* 54076 */ MCD_OPC_CheckField, 21, 1, 1, 97, 128, 0, // Skip to: 86948 -/* 54083 */ MCD_OPC_Decode, 227, 33, 238, 1, // Opcode: URSHLv2i32 -/* 54088 */ MCD_OPC_FilterValue, 7, 87, 128, 0, // Skip to: 86948 -/* 54093 */ MCD_OPC_CheckPredicate, 3, 82, 128, 0, // Skip to: 86948 -/* 54098 */ MCD_OPC_CheckField, 21, 1, 1, 75, 128, 0, // Skip to: 86948 -/* 54105 */ MCD_OPC_Decode, 143, 33, 238, 1, // Opcode: UQRSHLv2i32 -/* 54110 */ MCD_OPC_FilterValue, 3, 179, 0, 0, // Skip to: 54294 -/* 54115 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 54118 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54140 -/* 54123 */ MCD_OPC_CheckPredicate, 3, 52, 128, 0, // Skip to: 86948 -/* 54128 */ MCD_OPC_CheckField, 21, 1, 1, 45, 128, 0, // Skip to: 86948 -/* 54135 */ MCD_OPC_Decode, 240, 21, 252, 1, // Opcode: RSUBHNv2i64_v2i32 -/* 54140 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 54162 -/* 54145 */ MCD_OPC_CheckPredicate, 3, 30, 128, 0, // Skip to: 86948 -/* 54150 */ MCD_OPC_CheckField, 21, 1, 1, 23, 128, 0, // Skip to: 86948 -/* 54157 */ MCD_OPC_Decode, 129, 32, 238, 1, // Opcode: UMAXv2i32 -/* 54162 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 54184 -/* 54167 */ MCD_OPC_CheckPredicate, 3, 8, 128, 0, // Skip to: 86948 -/* 54172 */ MCD_OPC_CheckField, 16, 6, 32, 1, 128, 0, // Skip to: 86948 -/* 54179 */ MCD_OPC_Decode, 137, 31, 248, 1, // Opcode: UADALPv2i32_v1i64 -/* 54184 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 54206 -/* 54189 */ MCD_OPC_CheckPredicate, 3, 242, 127, 0, // Skip to: 86948 -/* 54194 */ MCD_OPC_CheckField, 21, 1, 1, 235, 127, 0, // Skip to: 86948 -/* 54201 */ MCD_OPC_Decode, 158, 32, 238, 1, // Opcode: UMINv2i32 -/* 54206 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 54228 -/* 54211 */ MCD_OPC_CheckPredicate, 3, 220, 127, 0, // Skip to: 86948 -/* 54216 */ MCD_OPC_CheckField, 21, 1, 1, 213, 127, 0, // Skip to: 86948 -/* 54223 */ MCD_OPC_Decode, 249, 30, 234, 1, // Opcode: UABDLv2i32_v2i64 -/* 54228 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 54250 -/* 54233 */ MCD_OPC_CheckPredicate, 3, 198, 127, 0, // Skip to: 86948 -/* 54238 */ MCD_OPC_CheckField, 21, 1, 1, 191, 127, 0, // Skip to: 86948 -/* 54245 */ MCD_OPC_Decode, 131, 31, 238, 1, // Opcode: UABDv2i32 -/* 54250 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 54272 -/* 54255 */ MCD_OPC_CheckPredicate, 3, 176, 127, 0, // Skip to: 86948 -/* 54260 */ MCD_OPC_CheckField, 16, 6, 32, 169, 127, 0, // Skip to: 86948 -/* 54267 */ MCD_OPC_Decode, 152, 25, 239, 1, // Opcode: SQNEGv2i32 -/* 54272 */ MCD_OPC_FilterValue, 7, 159, 127, 0, // Skip to: 86948 -/* 54277 */ MCD_OPC_CheckPredicate, 3, 154, 127, 0, // Skip to: 86948 -/* 54282 */ MCD_OPC_CheckField, 21, 1, 1, 147, 127, 0, // Skip to: 86948 -/* 54289 */ MCD_OPC_Decode, 243, 30, 130, 2, // Opcode: UABAv2i32 -/* 54294 */ MCD_OPC_FilterValue, 4, 199, 0, 0, // Skip to: 54498 -/* 54299 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 54302 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54324 -/* 54307 */ MCD_OPC_CheckPredicate, 3, 124, 127, 0, // Skip to: 86948 -/* 54312 */ MCD_OPC_CheckField, 21, 1, 1, 117, 127, 0, // Skip to: 86948 -/* 54319 */ MCD_OPC_Decode, 165, 32, 254, 1, // Opcode: UMLALv2i32_v2i64 -/* 54324 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 54362 -/* 54329 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 54332 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54347 -/* 54337 */ MCD_OPC_CheckPredicate, 7, 94, 127, 0, // Skip to: 86948 -/* 54342 */ MCD_OPC_Decode, 162, 25, 130, 2, // Opcode: SQRDMLAHv2i32 -/* 54347 */ MCD_OPC_FilterValue, 1, 84, 127, 0, // Skip to: 86948 -/* 54352 */ MCD_OPC_CheckPredicate, 3, 79, 127, 0, // Skip to: 86948 -/* 54357 */ MCD_OPC_Decode, 129, 30, 238, 1, // Opcode: SUBv2i32 -/* 54362 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 54384 -/* 54367 */ MCD_OPC_CheckPredicate, 3, 64, 127, 0, // Skip to: 86948 -/* 54372 */ MCD_OPC_CheckField, 16, 6, 32, 57, 127, 0, // Skip to: 86948 -/* 54379 */ MCD_OPC_Decode, 203, 3, 239, 1, // Opcode: CMGEv2i32rz -/* 54384 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 54422 -/* 54389 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 54392 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54407 -/* 54397 */ MCD_OPC_CheckPredicate, 7, 34, 127, 0, // Skip to: 86948 -/* 54402 */ MCD_OPC_Decode, 174, 25, 130, 2, // Opcode: SQRDMLSHv2i32 -/* 54407 */ MCD_OPC_FilterValue, 1, 24, 127, 0, // Skip to: 86948 -/* 54412 */ MCD_OPC_CheckPredicate, 3, 19, 127, 0, // Skip to: 86948 -/* 54417 */ MCD_OPC_Decode, 186, 3, 238, 1, // Opcode: CMEQv2i32 -/* 54422 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 54460 -/* 54427 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 54430 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54445 -/* 54435 */ MCD_OPC_CheckPredicate, 10, 252, 126, 0, // Skip to: 86948 -/* 54440 */ MCD_OPC_Decode, 219, 31, 130, 2, // Opcode: UDOTv8i8 -/* 54445 */ MCD_OPC_FilterValue, 1, 242, 126, 0, // Skip to: 86948 -/* 54450 */ MCD_OPC_CheckPredicate, 3, 237, 126, 0, // Skip to: 86948 -/* 54455 */ MCD_OPC_Decode, 224, 19, 130, 2, // Opcode: MLSv2i32 -/* 54460 */ MCD_OPC_FilterValue, 6, 227, 126, 0, // Skip to: 86948 -/* 54465 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 54468 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54483 -/* 54473 */ MCD_OPC_CheckPredicate, 3, 214, 126, 0, // Skip to: 86948 -/* 54478 */ MCD_OPC_Decode, 248, 3, 239, 1, // Opcode: CMLEv2i32rz -/* 54483 */ MCD_OPC_FilterValue, 33, 204, 126, 0, // Skip to: 86948 -/* 54488 */ MCD_OPC_CheckPredicate, 3, 199, 126, 0, // Skip to: 86948 -/* 54493 */ MCD_OPC_Decode, 241, 11, 239, 1, // Opcode: FRINTIv2f32 -/* 54498 */ MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 54654 -/* 54503 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 54506 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54528 -/* 54511 */ MCD_OPC_CheckPredicate, 3, 176, 126, 0, // Skip to: 86948 -/* 54516 */ MCD_OPC_CheckField, 21, 1, 1, 169, 126, 0, // Skip to: 86948 -/* 54523 */ MCD_OPC_Decode, 175, 32, 254, 1, // Opcode: UMLSLv2i32_v2i64 -/* 54528 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 54550 -/* 54533 */ MCD_OPC_CheckPredicate, 3, 154, 126, 0, // Skip to: 86948 -/* 54538 */ MCD_OPC_CheckField, 21, 1, 1, 147, 126, 0, // Skip to: 86948 -/* 54545 */ MCD_OPC_Decode, 234, 31, 238, 1, // Opcode: UMAXPv2i32 -/* 54550 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 54572 -/* 54555 */ MCD_OPC_CheckPredicate, 3, 132, 126, 0, // Skip to: 86948 -/* 54560 */ MCD_OPC_CheckField, 16, 6, 33, 125, 126, 0, // Skip to: 86948 -/* 54567 */ MCD_OPC_Decode, 208, 8, 239, 1, // Opcode: FCVTPUv2f32 -/* 54572 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 54594 -/* 54577 */ MCD_OPC_CheckPredicate, 3, 110, 126, 0, // Skip to: 86948 -/* 54582 */ MCD_OPC_CheckField, 21, 1, 1, 103, 126, 0, // Skip to: 86948 -/* 54589 */ MCD_OPC_Decode, 135, 32, 238, 1, // Opcode: UMINPv2i32 -/* 54594 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 54616 -/* 54599 */ MCD_OPC_CheckPredicate, 3, 88, 126, 0, // Skip to: 86948 -/* 54604 */ MCD_OPC_CheckField, 21, 1, 1, 81, 126, 0, // Skip to: 86948 -/* 54611 */ MCD_OPC_Decode, 186, 25, 238, 1, // Opcode: SQRDMULHv2i32 -/* 54616 */ MCD_OPC_FilterValue, 6, 71, 126, 0, // Skip to: 86948 -/* 54621 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 54624 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54639 -/* 54629 */ MCD_OPC_CheckPredicate, 3, 58, 126, 0, // Skip to: 86948 -/* 54634 */ MCD_OPC_Decode, 181, 20, 239, 1, // Opcode: NEGv2i32 -/* 54639 */ MCD_OPC_FilterValue, 33, 48, 126, 0, // Skip to: 86948 -/* 54644 */ MCD_OPC_CheckPredicate, 3, 43, 126, 0, // Skip to: 86948 -/* 54649 */ MCD_OPC_Decode, 150, 9, 239, 1, // Opcode: FCVTZUv2f32 -/* 54654 */ MCD_OPC_FilterValue, 6, 170, 0, 0, // Skip to: 54829 -/* 54659 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 54662 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 54768 -/* 54667 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 54670 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54692 -/* 54675 */ MCD_OPC_CheckPredicate, 3, 12, 126, 0, // Skip to: 86948 -/* 54680 */ MCD_OPC_CheckField, 21, 1, 1, 5, 126, 0, // Skip to: 86948 -/* 54687 */ MCD_OPC_Decode, 195, 32, 234, 1, // Opcode: UMULLv2i32_v2i64 -/* 54692 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 54730 -/* 54697 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 54700 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54715 -/* 54705 */ MCD_OPC_CheckPredicate, 3, 238, 125, 0, // Skip to: 86948 -/* 54710 */ MCD_OPC_Decode, 253, 6, 239, 1, // Opcode: FCMGEv2i32rz -/* 54715 */ MCD_OPC_FilterValue, 33, 228, 125, 0, // Skip to: 86948 -/* 54720 */ MCD_OPC_CheckPredicate, 3, 223, 125, 0, // Skip to: 86948 -/* 54725 */ MCD_OPC_Decode, 241, 33, 239, 1, // Opcode: URSQRTEv2i32 -/* 54730 */ MCD_OPC_FilterValue, 3, 213, 125, 0, // Skip to: 86948 -/* 54735 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 54738 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54753 -/* 54743 */ MCD_OPC_CheckPredicate, 3, 200, 125, 0, // Skip to: 86948 -/* 54748 */ MCD_OPC_Decode, 174, 7, 239, 1, // Opcode: FCMLEv2i32rz -/* 54753 */ MCD_OPC_FilterValue, 33, 190, 125, 0, // Skip to: 86948 -/* 54758 */ MCD_OPC_CheckPredicate, 3, 185, 125, 0, // Skip to: 86948 -/* 54763 */ MCD_OPC_Decode, 179, 12, 239, 1, // Opcode: FRSQRTEv2f32 -/* 54768 */ MCD_OPC_FilterValue, 1, 175, 125, 0, // Skip to: 86948 -/* 54773 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 54776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54791 -/* 54781 */ MCD_OPC_CheckPredicate, 11, 162, 125, 0, // Skip to: 86948 -/* 54786 */ MCD_OPC_Decode, 160, 7, 167, 2, // Opcode: FCMLAv2f32 -/* 54791 */ MCD_OPC_FilterValue, 1, 152, 125, 0, // Skip to: 86948 -/* 54796 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 54799 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54814 -/* 54804 */ MCD_OPC_CheckPredicate, 3, 139, 125, 0, // Skip to: 86948 -/* 54809 */ MCD_OPC_Decode, 253, 9, 238, 1, // Opcode: FMINNMPv2f32 -/* 54814 */ MCD_OPC_FilterValue, 2, 129, 125, 0, // Skip to: 86948 -/* 54819 */ MCD_OPC_CheckPredicate, 3, 124, 125, 0, // Skip to: 86948 -/* 54824 */ MCD_OPC_Decode, 134, 6, 238, 1, // Opcode: FABDv2f32 -/* 54829 */ MCD_OPC_FilterValue, 7, 114, 125, 0, // Skip to: 86948 -/* 54834 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 54837 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 54898 -/* 54842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 54845 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54860 -/* 54850 */ MCD_OPC_CheckPredicate, 11, 93, 125, 0, // Skip to: 86948 -/* 54855 */ MCD_OPC_Decode, 206, 6, 168, 2, // Opcode: FCADDv2f32 -/* 54860 */ MCD_OPC_FilterValue, 1, 83, 125, 0, // Skip to: 86948 -/* 54865 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 54868 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54883 -/* 54873 */ MCD_OPC_CheckPredicate, 3, 70, 125, 0, // Skip to: 86948 -/* 54878 */ MCD_OPC_Decode, 145, 7, 238, 1, // Opcode: FCMGTv2f32 -/* 54883 */ MCD_OPC_FilterValue, 1, 60, 125, 0, // Skip to: 86948 -/* 54888 */ MCD_OPC_CheckPredicate, 3, 55, 125, 0, // Skip to: 86948 -/* 54893 */ MCD_OPC_Decode, 151, 10, 238, 1, // Opcode: FMINPv2f32 -/* 54898 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 54950 -/* 54903 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 54906 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 54928 -/* 54911 */ MCD_OPC_CheckPredicate, 3, 32, 125, 0, // Skip to: 86948 -/* 54916 */ MCD_OPC_CheckField, 12, 1, 1, 25, 125, 0, // Skip to: 86948 -/* 54923 */ MCD_OPC_Decode, 170, 11, 239, 1, // Opcode: FNEGv2f32 -/* 54928 */ MCD_OPC_FilterValue, 33, 15, 125, 0, // Skip to: 86948 -/* 54933 */ MCD_OPC_CheckPredicate, 3, 10, 125, 0, // Skip to: 86948 -/* 54938 */ MCD_OPC_CheckField, 12, 1, 1, 3, 125, 0, // Skip to: 86948 -/* 54945 */ MCD_OPC_Decode, 204, 12, 239, 1, // Opcode: FSQRTv2f32 -/* 54950 */ MCD_OPC_FilterValue, 3, 249, 124, 0, // Skip to: 86948 -/* 54955 */ MCD_OPC_CheckPredicate, 3, 244, 124, 0, // Skip to: 86948 -/* 54960 */ MCD_OPC_CheckField, 21, 1, 1, 237, 124, 0, // Skip to: 86948 -/* 54967 */ MCD_OPC_CheckField, 12, 1, 0, 230, 124, 0, // Skip to: 86948 -/* 54974 */ MCD_OPC_Decode, 167, 6, 238, 1, // Opcode: FACGTv2f32 -/* 54979 */ MCD_OPC_FilterValue, 2, 93, 6, 0, // Skip to: 56613 -/* 54984 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 54987 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 55009 -/* 54992 */ MCD_OPC_CheckPredicate, 3, 207, 124, 0, // Skip to: 86948 -/* 54997 */ MCD_OPC_CheckField, 21, 1, 1, 200, 124, 0, // Skip to: 86948 -/* 55004 */ MCD_OPC_Decode, 166, 22, 133, 2, // Opcode: SADDLv4i32_v2i64 -/* 55009 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 55031 -/* 55014 */ MCD_OPC_CheckPredicate, 3, 185, 124, 0, // Skip to: 86948 -/* 55019 */ MCD_OPC_CheckField, 21, 1, 1, 178, 124, 0, // Skip to: 86948 -/* 55026 */ MCD_OPC_Decode, 130, 23, 133, 2, // Opcode: SHADDv4i32 -/* 55031 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 55053 -/* 55036 */ MCD_OPC_CheckPredicate, 3, 163, 124, 0, // Skip to: 86948 -/* 55041 */ MCD_OPC_CheckField, 16, 6, 32, 156, 124, 0, // Skip to: 86948 -/* 55048 */ MCD_OPC_Decode, 212, 21, 138, 2, // Opcode: REV64v4i32 -/* 55053 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 55075 -/* 55058 */ MCD_OPC_CheckPredicate, 3, 141, 124, 0, // Skip to: 86948 -/* 55063 */ MCD_OPC_CheckField, 21, 1, 1, 134, 124, 0, // Skip to: 86948 -/* 55070 */ MCD_OPC_Decode, 180, 24, 133, 2, // Opcode: SQADDv4i32 -/* 55075 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 55097 -/* 55080 */ MCD_OPC_CheckPredicate, 3, 119, 124, 0, // Skip to: 86948 -/* 55085 */ MCD_OPC_CheckField, 21, 1, 1, 112, 124, 0, // Skip to: 86948 -/* 55092 */ MCD_OPC_Decode, 175, 22, 133, 2, // Opcode: SADDWv4i32_v2i64 -/* 55097 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 55119 -/* 55102 */ MCD_OPC_CheckPredicate, 3, 97, 124, 0, // Skip to: 86948 -/* 55107 */ MCD_OPC_CheckField, 21, 1, 1, 90, 124, 0, // Skip to: 86948 -/* 55114 */ MCD_OPC_Decode, 186, 26, 133, 2, // Opcode: SRHADDv4i32 -/* 55119 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 55141 -/* 55124 */ MCD_OPC_CheckPredicate, 3, 75, 124, 0, // Skip to: 86948 -/* 55129 */ MCD_OPC_CheckField, 21, 1, 0, 68, 124, 0, // Skip to: 86948 -/* 55136 */ MCD_OPC_Decode, 200, 34, 133, 2, // Opcode: UZP1v4i32 -/* 55141 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 55163 -/* 55146 */ MCD_OPC_CheckPredicate, 3, 53, 124, 0, // Skip to: 86948 -/* 55151 */ MCD_OPC_CheckField, 21, 1, 1, 46, 124, 0, // Skip to: 86948 -/* 55158 */ MCD_OPC_Decode, 217, 20, 133, 2, // Opcode: ORRv16i8 -/* 55163 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 55185 -/* 55168 */ MCD_OPC_CheckPredicate, 3, 31, 124, 0, // Skip to: 86948 -/* 55173 */ MCD_OPC_CheckField, 21, 1, 1, 24, 124, 0, // Skip to: 86948 -/* 55180 */ MCD_OPC_Decode, 164, 27, 133, 2, // Opcode: SSUBLv4i32_v2i64 -/* 55185 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 55207 -/* 55190 */ MCD_OPC_CheckPredicate, 3, 9, 124, 0, // Skip to: 86948 -/* 55195 */ MCD_OPC_CheckField, 21, 1, 1, 2, 124, 0, // Skip to: 86948 -/* 55202 */ MCD_OPC_Decode, 156, 23, 133, 2, // Opcode: SHSUBv4i32 -/* 55207 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 55268 -/* 55212 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 55215 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55230 -/* 55220 */ MCD_OPC_CheckPredicate, 3, 235, 123, 0, // Skip to: 86948 -/* 55225 */ MCD_OPC_Decode, 217, 30, 133, 2, // Opcode: TRN1v4i32 -/* 55230 */ MCD_OPC_FilterValue, 1, 225, 123, 0, // Skip to: 86948 -/* 55235 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 55238 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55253 -/* 55243 */ MCD_OPC_CheckPredicate, 3, 212, 123, 0, // Skip to: 86948 -/* 55248 */ MCD_OPC_Decode, 155, 22, 138, 2, // Opcode: SADDLPv4i32_v2i64 -/* 55253 */ MCD_OPC_FilterValue, 1, 202, 123, 0, // Skip to: 86948 -/* 55258 */ MCD_OPC_CheckPredicate, 3, 197, 123, 0, // Skip to: 86948 -/* 55263 */ MCD_OPC_Decode, 130, 35, 147, 2, // Opcode: XTNv4i32 -/* 55268 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 55290 -/* 55273 */ MCD_OPC_CheckPredicate, 3, 182, 123, 0, // Skip to: 86948 -/* 55278 */ MCD_OPC_CheckField, 21, 1, 1, 175, 123, 0, // Skip to: 86948 -/* 55285 */ MCD_OPC_Decode, 162, 26, 133, 2, // Opcode: SQSUBv4i32 -/* 55290 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 55312 -/* 55295 */ MCD_OPC_CheckPredicate, 3, 160, 123, 0, // Skip to: 86948 -/* 55300 */ MCD_OPC_CheckField, 21, 1, 1, 153, 123, 0, // Skip to: 86948 -/* 55307 */ MCD_OPC_Decode, 170, 27, 133, 2, // Opcode: SSUBWv4i32_v2i64 -/* 55312 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 55334 -/* 55317 */ MCD_OPC_CheckPredicate, 3, 138, 123, 0, // Skip to: 86948 -/* 55322 */ MCD_OPC_CheckField, 21, 1, 1, 131, 123, 0, // Skip to: 86948 -/* 55329 */ MCD_OPC_Decode, 224, 3, 133, 2, // Opcode: CMGTv4i32 -/* 55334 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 55395 -/* 55339 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 55342 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55357 -/* 55347 */ MCD_OPC_CheckPredicate, 3, 108, 123, 0, // Skip to: 86948 -/* 55352 */ MCD_OPC_Decode, 145, 35, 133, 2, // Opcode: ZIP1v4i32 -/* 55357 */ MCD_OPC_FilterValue, 1, 98, 123, 0, // Skip to: 86948 -/* 55362 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 55365 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55380 -/* 55370 */ MCD_OPC_CheckPredicate, 3, 85, 123, 0, // Skip to: 86948 -/* 55375 */ MCD_OPC_Decode, 149, 30, 147, 2, // Opcode: SUQADDv4i32 -/* 55380 */ MCD_OPC_FilterValue, 16, 75, 123, 0, // Skip to: 86948 -/* 55385 */ MCD_OPC_CheckPredicate, 3, 70, 123, 0, // Skip to: 86948 -/* 55390 */ MCD_OPC_Decode, 160, 22, 244, 1, // Opcode: SADDLVv4i32v -/* 55395 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 55417 -/* 55400 */ MCD_OPC_CheckPredicate, 3, 55, 123, 0, // Skip to: 86948 -/* 55405 */ MCD_OPC_CheckField, 21, 1, 1, 48, 123, 0, // Skip to: 86948 -/* 55412 */ MCD_OPC_Decode, 208, 3, 133, 2, // Opcode: CMGEv4i32 -/* 55417 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 55439 -/* 55422 */ MCD_OPC_CheckPredicate, 3, 33, 123, 0, // Skip to: 86948 -/* 55427 */ MCD_OPC_CheckField, 21, 1, 1, 26, 123, 0, // Skip to: 86948 -/* 55434 */ MCD_OPC_Decode, 143, 1, 141, 2, // Opcode: ADDHNv2i64_v4i32 -/* 55439 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 55461 -/* 55444 */ MCD_OPC_CheckPredicate, 3, 11, 123, 0, // Skip to: 86948 -/* 55449 */ MCD_OPC_CheckField, 21, 1, 1, 4, 123, 0, // Skip to: 86948 -/* 55456 */ MCD_OPC_Decode, 232, 26, 133, 2, // Opcode: SSHLv4i32 -/* 55461 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 55499 -/* 55466 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 55469 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 55484 -/* 55474 */ MCD_OPC_CheckPredicate, 3, 237, 122, 0, // Skip to: 86948 -/* 55479 */ MCD_OPC_Decode, 167, 3, 138, 2, // Opcode: CLSv4i32 -/* 55484 */ MCD_OPC_FilterValue, 33, 227, 122, 0, // Skip to: 86948 -/* 55489 */ MCD_OPC_CheckPredicate, 3, 222, 122, 0, // Skip to: 86948 -/* 55494 */ MCD_OPC_Decode, 171, 26, 147, 2, // Opcode: SQXTNv4i32 -/* 55499 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 55521 -/* 55504 */ MCD_OPC_CheckPredicate, 3, 207, 122, 0, // Skip to: 86948 -/* 55509 */ MCD_OPC_CheckField, 21, 1, 1, 200, 122, 0, // Skip to: 86948 -/* 55516 */ MCD_OPC_Decode, 250, 25, 133, 2, // Opcode: SQSHLv4i32 -/* 55521 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 55543 -/* 55526 */ MCD_OPC_CheckPredicate, 3, 185, 122, 0, // Skip to: 86948 -/* 55531 */ MCD_OPC_CheckField, 21, 1, 1, 178, 122, 0, // Skip to: 86948 -/* 55538 */ MCD_OPC_Decode, 249, 21, 141, 2, // Opcode: SABALv4i32_v2i64 -/* 55543 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 55565 -/* 55548 */ MCD_OPC_CheckPredicate, 3, 163, 122, 0, // Skip to: 86948 -/* 55553 */ MCD_OPC_CheckField, 21, 1, 1, 156, 122, 0, // Skip to: 86948 -/* 55560 */ MCD_OPC_Decode, 202, 26, 133, 2, // Opcode: SRSHLv4i32 -/* 55565 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 55587 -/* 55570 */ MCD_OPC_CheckPredicate, 3, 141, 122, 0, // Skip to: 86948 -/* 55575 */ MCD_OPC_CheckField, 21, 1, 0, 134, 122, 0, // Skip to: 86948 -/* 55582 */ MCD_OPC_Decode, 215, 34, 133, 2, // Opcode: UZP2v4i32 -/* 55587 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 55609 -/* 55592 */ MCD_OPC_CheckPredicate, 3, 119, 122, 0, // Skip to: 86948 -/* 55597 */ MCD_OPC_CheckField, 21, 1, 1, 112, 122, 0, // Skip to: 86948 -/* 55604 */ MCD_OPC_Decode, 202, 25, 133, 2, // Opcode: SQRSHLv4i32 -/* 55609 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 55631 -/* 55614 */ MCD_OPC_CheckPredicate, 3, 97, 122, 0, // Skip to: 86948 -/* 55619 */ MCD_OPC_CheckField, 21, 1, 1, 90, 122, 0, // Skip to: 86948 -/* 55626 */ MCD_OPC_Decode, 212, 29, 141, 2, // Opcode: SUBHNv2i64_v4i32 -/* 55631 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 55653 -/* 55636 */ MCD_OPC_CheckPredicate, 3, 75, 122, 0, // Skip to: 86948 -/* 55641 */ MCD_OPC_CheckField, 21, 1, 1, 68, 122, 0, // Skip to: 86948 -/* 55648 */ MCD_OPC_Decode, 203, 23, 133, 2, // Opcode: SMAXv4i32 -/* 55653 */ MCD_OPC_FilterValue, 26, 40, 0, 0, // Skip to: 55698 -/* 55658 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 55661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55676 -/* 55666 */ MCD_OPC_CheckPredicate, 3, 45, 122, 0, // Skip to: 86948 -/* 55671 */ MCD_OPC_Decode, 232, 30, 133, 2, // Opcode: TRN2v4i32 -/* 55676 */ MCD_OPC_FilterValue, 1, 35, 122, 0, // Skip to: 86948 -/* 55681 */ MCD_OPC_CheckPredicate, 3, 30, 122, 0, // Skip to: 86948 -/* 55686 */ MCD_OPC_CheckField, 16, 5, 0, 23, 122, 0, // Skip to: 86948 -/* 55693 */ MCD_OPC_Decode, 149, 22, 147, 2, // Opcode: SADALPv4i32_v2i64 -/* 55698 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 55720 -/* 55703 */ MCD_OPC_CheckPredicate, 3, 8, 122, 0, // Skip to: 86948 -/* 55708 */ MCD_OPC_CheckField, 21, 1, 1, 1, 122, 0, // Skip to: 86948 -/* 55715 */ MCD_OPC_Decode, 233, 23, 133, 2, // Opcode: SMINv4i32 -/* 55720 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 55742 -/* 55725 */ MCD_OPC_CheckPredicate, 3, 242, 121, 0, // Skip to: 86948 -/* 55730 */ MCD_OPC_CheckField, 21, 1, 1, 235, 121, 0, // Skip to: 86948 -/* 55737 */ MCD_OPC_Decode, 133, 22, 133, 2, // Opcode: SABDLv4i32_v2i64 -/* 55742 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 55764 -/* 55747 */ MCD_OPC_CheckPredicate, 3, 220, 121, 0, // Skip to: 86948 -/* 55752 */ MCD_OPC_CheckField, 21, 1, 1, 213, 121, 0, // Skip to: 86948 -/* 55759 */ MCD_OPC_Decode, 143, 22, 133, 2, // Opcode: SABDv4i32 -/* 55764 */ MCD_OPC_FilterValue, 30, 40, 0, 0, // Skip to: 55809 -/* 55769 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 55772 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55787 -/* 55777 */ MCD_OPC_CheckPredicate, 3, 190, 121, 0, // Skip to: 86948 -/* 55782 */ MCD_OPC_Decode, 160, 35, 133, 2, // Opcode: ZIP2v4i32 -/* 55787 */ MCD_OPC_FilterValue, 1, 180, 121, 0, // Skip to: 86948 -/* 55792 */ MCD_OPC_CheckPredicate, 3, 175, 121, 0, // Skip to: 86948 -/* 55797 */ MCD_OPC_CheckField, 16, 5, 0, 168, 121, 0, // Skip to: 86948 -/* 55804 */ MCD_OPC_Decode, 161, 24, 138, 2, // Opcode: SQABSv4i32 -/* 55809 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 55831 -/* 55814 */ MCD_OPC_CheckPredicate, 3, 153, 121, 0, // Skip to: 86948 -/* 55819 */ MCD_OPC_CheckField, 21, 1, 1, 146, 121, 0, // Skip to: 86948 -/* 55826 */ MCD_OPC_Decode, 255, 21, 141, 2, // Opcode: SABAv4i32 -/* 55831 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 55853 -/* 55836 */ MCD_OPC_CheckPredicate, 3, 131, 121, 0, // Skip to: 86948 -/* 55841 */ MCD_OPC_CheckField, 21, 1, 1, 124, 121, 0, // Skip to: 86948 -/* 55848 */ MCD_OPC_Decode, 242, 23, 141, 2, // Opcode: SMLALv4i32_v2i64 -/* 55853 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 55875 -/* 55858 */ MCD_OPC_CheckPredicate, 3, 109, 121, 0, // Skip to: 86948 -/* 55863 */ MCD_OPC_CheckField, 21, 1, 1, 102, 121, 0, // Skip to: 86948 -/* 55870 */ MCD_OPC_Decode, 199, 1, 133, 2, // Opcode: ADDv4i32 -/* 55875 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 55913 -/* 55880 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 55883 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 55898 -/* 55888 */ MCD_OPC_CheckPredicate, 3, 79, 121, 0, // Skip to: 86948 -/* 55893 */ MCD_OPC_Decode, 225, 3, 138, 2, // Opcode: CMGTv4i32rz -/* 55898 */ MCD_OPC_FilterValue, 33, 69, 121, 0, // Skip to: 86948 -/* 55903 */ MCD_OPC_CheckPredicate, 3, 64, 121, 0, // Skip to: 86948 -/* 55908 */ MCD_OPC_Decode, 149, 12, 138, 2, // Opcode: FRINTPv4f32 -/* 55913 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 55935 -/* 55918 */ MCD_OPC_CheckPredicate, 3, 49, 121, 0, // Skip to: 86948 -/* 55923 */ MCD_OPC_CheckField, 21, 1, 1, 42, 121, 0, // Skip to: 86948 -/* 55930 */ MCD_OPC_Decode, 238, 4, 133, 2, // Opcode: CMTSTv4i32 -/* 55935 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 55957 -/* 55940 */ MCD_OPC_CheckPredicate, 3, 27, 121, 0, // Skip to: 86948 -/* 55945 */ MCD_OPC_CheckField, 21, 1, 1, 20, 121, 0, // Skip to: 86948 -/* 55952 */ MCD_OPC_Decode, 214, 24, 141, 2, // Opcode: SQDMLALv4i32_v2i64 -/* 55957 */ MCD_OPC_FilterValue, 37, 33, 0, 0, // Skip to: 55995 -/* 55962 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 55965 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55980 -/* 55970 */ MCD_OPC_CheckPredicate, 10, 253, 120, 0, // Skip to: 86948 -/* 55975 */ MCD_OPC_Decode, 231, 22, 141, 2, // Opcode: SDOTv16i8 -/* 55980 */ MCD_OPC_FilterValue, 1, 243, 120, 0, // Skip to: 86948 -/* 55985 */ MCD_OPC_CheckPredicate, 3, 238, 120, 0, // Skip to: 86948 -/* 55990 */ MCD_OPC_Decode, 214, 19, 141, 2, // Opcode: MLAv4i32 -/* 55995 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 56033 -/* 56000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 56003 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56018 -/* 56008 */ MCD_OPC_CheckPredicate, 3, 215, 120, 0, // Skip to: 86948 -/* 56013 */ MCD_OPC_Decode, 193, 3, 138, 2, // Opcode: CMEQv4i32rz -/* 56018 */ MCD_OPC_FilterValue, 33, 205, 120, 0, // Skip to: 86948 -/* 56023 */ MCD_OPC_CheckPredicate, 3, 200, 120, 0, // Skip to: 86948 -/* 56028 */ MCD_OPC_Decode, 171, 12, 138, 2, // Opcode: FRINTZv4f32 -/* 56033 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 56055 -/* 56038 */ MCD_OPC_CheckPredicate, 3, 185, 120, 0, // Skip to: 86948 -/* 56043 */ MCD_OPC_CheckField, 21, 1, 1, 178, 120, 0, // Skip to: 86948 -/* 56050 */ MCD_OPC_Decode, 162, 20, 133, 2, // Opcode: MULv4i32 -/* 56055 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 56077 -/* 56060 */ MCD_OPC_CheckPredicate, 3, 163, 120, 0, // Skip to: 86948 -/* 56065 */ MCD_OPC_CheckField, 21, 1, 1, 156, 120, 0, // Skip to: 86948 -/* 56072 */ MCD_OPC_Decode, 252, 23, 141, 2, // Opcode: SMLSLv4i32_v2i64 -/* 56077 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 56099 -/* 56082 */ MCD_OPC_CheckPredicate, 3, 141, 120, 0, // Skip to: 86948 -/* 56087 */ MCD_OPC_CheckField, 21, 1, 1, 134, 120, 0, // Skip to: 86948 -/* 56094 */ MCD_OPC_Decode, 180, 23, 133, 2, // Opcode: SMAXPv4i32 -/* 56099 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 56167 -/* 56104 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 56107 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56122 -/* 56112 */ MCD_OPC_CheckPredicate, 3, 111, 120, 0, // Skip to: 86948 -/* 56117 */ MCD_OPC_Decode, 131, 4, 138, 2, // Opcode: CMLTv4i32rz -/* 56122 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56137 -/* 56127 */ MCD_OPC_CheckPredicate, 3, 96, 120, 0, // Skip to: 86948 -/* 56132 */ MCD_OPC_Decode, 197, 8, 138, 2, // Opcode: FCVTPSv4f32 -/* 56137 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 56152 -/* 56142 */ MCD_OPC_CheckPredicate, 3, 81, 120, 0, // Skip to: 86948 -/* 56147 */ MCD_OPC_Decode, 189, 23, 160, 2, // Opcode: SMAXVv4i32v -/* 56152 */ MCD_OPC_FilterValue, 49, 71, 120, 0, // Skip to: 86948 -/* 56157 */ MCD_OPC_CheckPredicate, 3, 66, 120, 0, // Skip to: 86948 -/* 56162 */ MCD_OPC_Decode, 219, 23, 160, 2, // Opcode: SMINVv4i32v -/* 56167 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 56189 -/* 56172 */ MCD_OPC_CheckPredicate, 3, 51, 120, 0, // Skip to: 86948 -/* 56177 */ MCD_OPC_CheckField, 21, 1, 1, 44, 120, 0, // Skip to: 86948 -/* 56184 */ MCD_OPC_Decode, 210, 23, 133, 2, // Opcode: SMINPv4i32 -/* 56189 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 56211 -/* 56194 */ MCD_OPC_CheckPredicate, 3, 29, 120, 0, // Skip to: 86948 -/* 56199 */ MCD_OPC_CheckField, 21, 1, 1, 22, 120, 0, // Skip to: 86948 -/* 56206 */ MCD_OPC_Decode, 226, 24, 141, 2, // Opcode: SQDMLSLv4i32_v2i64 -/* 56211 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 56233 -/* 56216 */ MCD_OPC_CheckPredicate, 3, 7, 120, 0, // Skip to: 86948 -/* 56221 */ MCD_OPC_CheckField, 21, 1, 1, 0, 120, 0, // Skip to: 86948 -/* 56228 */ MCD_OPC_Decode, 237, 24, 133, 2, // Opcode: SQDMULHv4i32 -/* 56233 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 56286 -/* 56238 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 56241 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56256 -/* 56246 */ MCD_OPC_CheckPredicate, 3, 233, 119, 0, // Skip to: 86948 -/* 56251 */ MCD_OPC_Decode, 135, 1, 138, 2, // Opcode: ABSv4i32 -/* 56256 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56271 -/* 56261 */ MCD_OPC_CheckPredicate, 3, 218, 119, 0, // Skip to: 86948 -/* 56266 */ MCD_OPC_Decode, 248, 8, 138, 2, // Opcode: FCVTZSv4f32 -/* 56271 */ MCD_OPC_FilterValue, 49, 208, 119, 0, // Skip to: 86948 -/* 56276 */ MCD_OPC_CheckPredicate, 3, 203, 119, 0, // Skip to: 86948 -/* 56281 */ MCD_OPC_Decode, 169, 1, 160, 2, // Opcode: ADDVv4i32v -/* 56286 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 56308 -/* 56291 */ MCD_OPC_CheckPredicate, 3, 188, 119, 0, // Skip to: 86948 -/* 56296 */ MCD_OPC_CheckField, 21, 1, 1, 181, 119, 0, // Skip to: 86948 -/* 56303 */ MCD_OPC_Decode, 154, 1, 133, 2, // Opcode: ADDPv4i32 -/* 56308 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 56330 -/* 56313 */ MCD_OPC_CheckPredicate, 3, 166, 119, 0, // Skip to: 86948 -/* 56318 */ MCD_OPC_CheckField, 21, 1, 1, 159, 119, 0, // Skip to: 86948 -/* 56325 */ MCD_OPC_Decode, 145, 24, 133, 2, // Opcode: SMULLv4i32_v2i64 -/* 56330 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 56352 -/* 56335 */ MCD_OPC_CheckPredicate, 3, 144, 119, 0, // Skip to: 86948 -/* 56340 */ MCD_OPC_CheckField, 21, 1, 1, 137, 119, 0, // Skip to: 86948 -/* 56347 */ MCD_OPC_Decode, 149, 10, 133, 2, // Opcode: FMINNMv4f32 -/* 56352 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 56405 -/* 56357 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 56360 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56375 -/* 56365 */ MCD_OPC_CheckPredicate, 3, 114, 119, 0, // Skip to: 86948 -/* 56370 */ MCD_OPC_Decode, 152, 7, 138, 2, // Opcode: FCMGTv4i32rz -/* 56375 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56390 -/* 56380 */ MCD_OPC_CheckPredicate, 3, 99, 119, 0, // Skip to: 86948 -/* 56385 */ MCD_OPC_Decode, 218, 33, 138, 2, // Opcode: URECPEv4i32 -/* 56390 */ MCD_OPC_FilterValue, 48, 89, 119, 0, // Skip to: 86948 -/* 56395 */ MCD_OPC_CheckPredicate, 4, 84, 119, 0, // Skip to: 86948 -/* 56400 */ MCD_OPC_Decode, 139, 10, 152, 2, // Opcode: FMINNMVv8i16v -/* 56405 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 56427 -/* 56410 */ MCD_OPC_CheckPredicate, 3, 69, 119, 0, // Skip to: 86948 -/* 56415 */ MCD_OPC_CheckField, 21, 1, 1, 62, 119, 0, // Skip to: 86948 -/* 56422 */ MCD_OPC_Decode, 210, 10, 141, 2, // Opcode: FMLSv4f32 -/* 56427 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 56449 -/* 56432 */ MCD_OPC_CheckPredicate, 3, 47, 119, 0, // Skip to: 86948 -/* 56437 */ MCD_OPC_CheckField, 21, 1, 1, 40, 119, 0, // Skip to: 86948 -/* 56444 */ MCD_OPC_Decode, 250, 24, 133, 2, // Opcode: SQDMULLv4i32_v2i64 -/* 56449 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 56471 -/* 56454 */ MCD_OPC_CheckPredicate, 3, 25, 119, 0, // Skip to: 86948 -/* 56459 */ MCD_OPC_CheckField, 21, 1, 1, 18, 119, 0, // Skip to: 86948 -/* 56466 */ MCD_OPC_Decode, 230, 12, 133, 2, // Opcode: FSUBv4f32 -/* 56471 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 56509 -/* 56476 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 56479 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56494 -/* 56484 */ MCD_OPC_CheckPredicate, 3, 251, 118, 0, // Skip to: 86948 -/* 56489 */ MCD_OPC_Decode, 236, 6, 138, 2, // Opcode: FCMEQv4i32rz -/* 56494 */ MCD_OPC_FilterValue, 33, 241, 118, 0, // Skip to: 86948 -/* 56499 */ MCD_OPC_CheckPredicate, 3, 236, 118, 0, // Skip to: 86948 -/* 56504 */ MCD_OPC_Decode, 205, 11, 138, 2, // Opcode: FRECPEv4f32 -/* 56509 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 56531 -/* 56514 */ MCD_OPC_CheckPredicate, 3, 221, 118, 0, // Skip to: 86948 -/* 56519 */ MCD_OPC_CheckField, 16, 6, 32, 214, 118, 0, // Skip to: 86948 -/* 56526 */ MCD_OPC_Decode, 188, 7, 138, 2, // Opcode: FCMLTv4i32rz -/* 56531 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 56553 -/* 56536 */ MCD_OPC_CheckPredicate, 3, 199, 118, 0, // Skip to: 86948 -/* 56541 */ MCD_OPC_CheckField, 21, 1, 1, 192, 118, 0, // Skip to: 86948 -/* 56548 */ MCD_OPC_Decode, 175, 10, 133, 2, // Opcode: FMINv4f32 -/* 56553 */ MCD_OPC_FilterValue, 62, 33, 0, 0, // Skip to: 56591 -/* 56558 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 56561 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56576 -/* 56566 */ MCD_OPC_CheckPredicate, 3, 169, 118, 0, // Skip to: 86948 -/* 56571 */ MCD_OPC_Decode, 148, 6, 138, 2, // Opcode: FABSv4f32 -/* 56576 */ MCD_OPC_FilterValue, 48, 159, 118, 0, // Skip to: 86948 -/* 56581 */ MCD_OPC_CheckPredicate, 4, 154, 118, 0, // Skip to: 86948 -/* 56586 */ MCD_OPC_Decode, 165, 10, 152, 2, // Opcode: FMINVv8i16v -/* 56591 */ MCD_OPC_FilterValue, 63, 144, 118, 0, // Skip to: 86948 -/* 56596 */ MCD_OPC_CheckPredicate, 3, 139, 118, 0, // Skip to: 86948 -/* 56601 */ MCD_OPC_CheckField, 21, 1, 1, 132, 118, 0, // Skip to: 86948 -/* 56608 */ MCD_OPC_Decode, 193, 12, 133, 2, // Opcode: FRSQRTSv4f32 -/* 56613 */ MCD_OPC_FilterValue, 3, 209, 5, 0, // Skip to: 58107 -/* 56618 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 56621 */ MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 56761 -/* 56626 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 56629 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 56651 -/* 56634 */ MCD_OPC_CheckPredicate, 3, 101, 118, 0, // Skip to: 86948 -/* 56639 */ MCD_OPC_CheckField, 21, 1, 1, 94, 118, 0, // Skip to: 86948 -/* 56646 */ MCD_OPC_Decode, 156, 31, 133, 2, // Opcode: UADDLv4i32_v2i64 -/* 56651 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 56673 -/* 56656 */ MCD_OPC_CheckPredicate, 3, 79, 118, 0, // Skip to: 86948 -/* 56661 */ MCD_OPC_CheckField, 21, 1, 1, 72, 118, 0, // Skip to: 86948 -/* 56668 */ MCD_OPC_Decode, 223, 31, 133, 2, // Opcode: UHADDv4i32 -/* 56673 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 56695 -/* 56678 */ MCD_OPC_CheckPredicate, 3, 57, 118, 0, // Skip to: 86948 -/* 56683 */ MCD_OPC_CheckField, 21, 1, 1, 50, 118, 0, // Skip to: 86948 -/* 56690 */ MCD_OPC_Decode, 219, 32, 133, 2, // Opcode: UQADDv4i32 -/* 56695 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 56717 -/* 56700 */ MCD_OPC_CheckPredicate, 3, 35, 118, 0, // Skip to: 86948 -/* 56705 */ MCD_OPC_CheckField, 21, 1, 1, 28, 118, 0, // Skip to: 86948 -/* 56712 */ MCD_OPC_Decode, 166, 31, 133, 2, // Opcode: UADDWv4i32_v2i64 -/* 56717 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 56739 -/* 56722 */ MCD_OPC_CheckPredicate, 3, 13, 118, 0, // Skip to: 86948 -/* 56727 */ MCD_OPC_CheckField, 21, 1, 1, 6, 118, 0, // Skip to: 86948 -/* 56734 */ MCD_OPC_Decode, 222, 33, 133, 2, // Opcode: URHADDv4i32 -/* 56739 */ MCD_OPC_FilterValue, 7, 252, 117, 0, // Skip to: 86948 -/* 56744 */ MCD_OPC_CheckPredicate, 3, 247, 117, 0, // Skip to: 86948 -/* 56749 */ MCD_OPC_CheckField, 21, 1, 1, 240, 117, 0, // Skip to: 86948 -/* 56756 */ MCD_OPC_Decode, 195, 2, 141, 2, // Opcode: BITv16i8 -/* 56761 */ MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 56992 -/* 56766 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 56769 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 56791 -/* 56774 */ MCD_OPC_CheckPredicate, 3, 217, 117, 0, // Skip to: 86948 -/* 56779 */ MCD_OPC_CheckField, 21, 1, 1, 210, 117, 0, // Skip to: 86948 -/* 56786 */ MCD_OPC_Decode, 167, 34, 133, 2, // Opcode: USUBLv4i32_v2i64 -/* 56791 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 56813 -/* 56796 */ MCD_OPC_CheckPredicate, 3, 195, 117, 0, // Skip to: 86948 -/* 56801 */ MCD_OPC_CheckField, 21, 1, 1, 188, 117, 0, // Skip to: 86948 -/* 56808 */ MCD_OPC_Decode, 229, 31, 133, 2, // Opcode: UHSUBv4i32 -/* 56813 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 56851 -/* 56818 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 56821 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56836 -/* 56826 */ MCD_OPC_CheckPredicate, 3, 165, 117, 0, // Skip to: 86948 -/* 56831 */ MCD_OPC_Decode, 145, 31, 138, 2, // Opcode: UADDLPv4i32_v2i64 -/* 56836 */ MCD_OPC_FilterValue, 33, 155, 117, 0, // Skip to: 86948 -/* 56841 */ MCD_OPC_CheckPredicate, 3, 150, 117, 0, // Skip to: 86948 -/* 56846 */ MCD_OPC_Decode, 180, 26, 147, 2, // Opcode: SQXTUNv4i32 -/* 56851 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 56873 -/* 56856 */ MCD_OPC_CheckPredicate, 3, 135, 117, 0, // Skip to: 86948 -/* 56861 */ MCD_OPC_CheckField, 21, 1, 1, 128, 117, 0, // Skip to: 86948 -/* 56868 */ MCD_OPC_Decode, 205, 33, 133, 2, // Opcode: UQSUBv4i32 -/* 56873 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 56895 -/* 56878 */ MCD_OPC_CheckPredicate, 3, 113, 117, 0, // Skip to: 86948 -/* 56883 */ MCD_OPC_CheckField, 21, 1, 1, 106, 117, 0, // Skip to: 86948 -/* 56890 */ MCD_OPC_Decode, 173, 34, 133, 2, // Opcode: USUBWv4i32_v2i64 -/* 56895 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 56917 -/* 56900 */ MCD_OPC_CheckPredicate, 3, 91, 117, 0, // Skip to: 86948 -/* 56905 */ MCD_OPC_CheckField, 21, 1, 1, 84, 117, 0, // Skip to: 86948 -/* 56912 */ MCD_OPC_Decode, 235, 3, 133, 2, // Opcode: CMHIv4i32 -/* 56917 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 56970 -/* 56922 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 56925 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56940 -/* 56930 */ MCD_OPC_CheckPredicate, 3, 61, 117, 0, // Skip to: 86948 -/* 56935 */ MCD_OPC_Decode, 153, 34, 147, 2, // Opcode: USQADDv4i32 -/* 56940 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56955 -/* 56945 */ MCD_OPC_CheckPredicate, 3, 46, 117, 0, // Skip to: 86948 -/* 56950 */ MCD_OPC_Decode, 136, 23, 138, 2, // Opcode: SHLLv4i32 -/* 56955 */ MCD_OPC_FilterValue, 48, 36, 117, 0, // Skip to: 86948 -/* 56960 */ MCD_OPC_CheckPredicate, 3, 31, 117, 0, // Skip to: 86948 -/* 56965 */ MCD_OPC_Decode, 150, 31, 244, 1, // Opcode: UADDLVv4i32v -/* 56970 */ MCD_OPC_FilterValue, 7, 21, 117, 0, // Skip to: 86948 -/* 56975 */ MCD_OPC_CheckPredicate, 3, 16, 117, 0, // Skip to: 86948 -/* 56980 */ MCD_OPC_CheckField, 21, 1, 1, 9, 117, 0, // Skip to: 86948 -/* 56987 */ MCD_OPC_Decode, 243, 3, 133, 2, // Opcode: CMHSv4i32 -/* 56992 */ MCD_OPC_FilterValue, 2, 173, 0, 0, // Skip to: 57170 -/* 56997 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 57000 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57022 -/* 57005 */ MCD_OPC_CheckPredicate, 3, 242, 116, 0, // Skip to: 86948 -/* 57010 */ MCD_OPC_CheckField, 21, 1, 1, 235, 116, 0, // Skip to: 86948 -/* 57017 */ MCD_OPC_Decode, 178, 21, 141, 2, // Opcode: RADDHNv2i64_v4i32 -/* 57022 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 57044 -/* 57027 */ MCD_OPC_CheckPredicate, 3, 220, 116, 0, // Skip to: 86948 -/* 57032 */ MCD_OPC_CheckField, 21, 1, 1, 213, 116, 0, // Skip to: 86948 -/* 57039 */ MCD_OPC_Decode, 134, 34, 133, 2, // Opcode: USHLv4i32 -/* 57044 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 57082 -/* 57049 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 57052 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57067 -/* 57057 */ MCD_OPC_CheckPredicate, 3, 190, 116, 0, // Skip to: 86948 -/* 57062 */ MCD_OPC_Decode, 179, 3, 138, 2, // Opcode: CLZv4i32 -/* 57067 */ MCD_OPC_FilterValue, 33, 180, 116, 0, // Skip to: 86948 -/* 57072 */ MCD_OPC_CheckPredicate, 3, 175, 116, 0, // Skip to: 86948 -/* 57077 */ MCD_OPC_Decode, 214, 33, 147, 2, // Opcode: UQXTNv4i32 -/* 57082 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 57104 -/* 57087 */ MCD_OPC_CheckPredicate, 3, 160, 116, 0, // Skip to: 86948 -/* 57092 */ MCD_OPC_CheckField, 21, 1, 1, 153, 116, 0, // Skip to: 86948 -/* 57099 */ MCD_OPC_Decode, 174, 33, 133, 2, // Opcode: UQSHLv4i32 -/* 57104 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 57126 -/* 57109 */ MCD_OPC_CheckPredicate, 3, 138, 116, 0, // Skip to: 86948 -/* 57114 */ MCD_OPC_CheckField, 21, 1, 1, 131, 116, 0, // Skip to: 86948 -/* 57121 */ MCD_OPC_Decode, 239, 30, 141, 2, // Opcode: UABALv4i32_v2i64 -/* 57126 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 57148 -/* 57131 */ MCD_OPC_CheckPredicate, 3, 116, 116, 0, // Skip to: 86948 -/* 57136 */ MCD_OPC_CheckField, 21, 1, 1, 109, 116, 0, // Skip to: 86948 -/* 57143 */ MCD_OPC_Decode, 230, 33, 133, 2, // Opcode: URSHLv4i32 -/* 57148 */ MCD_OPC_FilterValue, 7, 99, 116, 0, // Skip to: 86948 -/* 57153 */ MCD_OPC_CheckPredicate, 3, 94, 116, 0, // Skip to: 86948 -/* 57158 */ MCD_OPC_CheckField, 21, 1, 1, 87, 116, 0, // Skip to: 86948 -/* 57165 */ MCD_OPC_Decode, 146, 33, 133, 2, // Opcode: UQRSHLv4i32 -/* 57170 */ MCD_OPC_FilterValue, 3, 179, 0, 0, // Skip to: 57354 -/* 57175 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 57178 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57200 -/* 57183 */ MCD_OPC_CheckPredicate, 3, 64, 116, 0, // Skip to: 86948 -/* 57188 */ MCD_OPC_CheckField, 21, 1, 1, 57, 116, 0, // Skip to: 86948 -/* 57195 */ MCD_OPC_Decode, 241, 21, 141, 2, // Opcode: RSUBHNv2i64_v4i32 -/* 57200 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 57222 -/* 57205 */ MCD_OPC_CheckPredicate, 3, 42, 116, 0, // Skip to: 86948 -/* 57210 */ MCD_OPC_CheckField, 21, 1, 1, 35, 116, 0, // Skip to: 86948 -/* 57217 */ MCD_OPC_Decode, 131, 32, 133, 2, // Opcode: UMAXv4i32 -/* 57222 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 57244 -/* 57227 */ MCD_OPC_CheckPredicate, 3, 20, 116, 0, // Skip to: 86948 -/* 57232 */ MCD_OPC_CheckField, 16, 6, 32, 13, 116, 0, // Skip to: 86948 -/* 57239 */ MCD_OPC_Decode, 139, 31, 147, 2, // Opcode: UADALPv4i32_v2i64 -/* 57244 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 57266 -/* 57249 */ MCD_OPC_CheckPredicate, 3, 254, 115, 0, // Skip to: 86948 -/* 57254 */ MCD_OPC_CheckField, 21, 1, 1, 247, 115, 0, // Skip to: 86948 -/* 57261 */ MCD_OPC_Decode, 160, 32, 133, 2, // Opcode: UMINv4i32 -/* 57266 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 57288 -/* 57271 */ MCD_OPC_CheckPredicate, 3, 232, 115, 0, // Skip to: 86948 -/* 57276 */ MCD_OPC_CheckField, 21, 1, 1, 225, 115, 0, // Skip to: 86948 -/* 57283 */ MCD_OPC_Decode, 251, 30, 133, 2, // Opcode: UABDLv4i32_v2i64 -/* 57288 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 57310 -/* 57293 */ MCD_OPC_CheckPredicate, 3, 210, 115, 0, // Skip to: 86948 -/* 57298 */ MCD_OPC_CheckField, 21, 1, 1, 203, 115, 0, // Skip to: 86948 -/* 57305 */ MCD_OPC_Decode, 133, 31, 133, 2, // Opcode: UABDv4i32 -/* 57310 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 57332 -/* 57315 */ MCD_OPC_CheckPredicate, 3, 188, 115, 0, // Skip to: 86948 -/* 57320 */ MCD_OPC_CheckField, 16, 6, 32, 181, 115, 0, // Skip to: 86948 -/* 57327 */ MCD_OPC_Decode, 155, 25, 138, 2, // Opcode: SQNEGv4i32 -/* 57332 */ MCD_OPC_FilterValue, 7, 171, 115, 0, // Skip to: 86948 -/* 57337 */ MCD_OPC_CheckPredicate, 3, 166, 115, 0, // Skip to: 86948 -/* 57342 */ MCD_OPC_CheckField, 21, 1, 1, 159, 115, 0, // Skip to: 86948 -/* 57349 */ MCD_OPC_Decode, 245, 30, 141, 2, // Opcode: UABAv4i32 -/* 57354 */ MCD_OPC_FilterValue, 4, 199, 0, 0, // Skip to: 57558 -/* 57359 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 57362 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57384 -/* 57367 */ MCD_OPC_CheckPredicate, 3, 136, 115, 0, // Skip to: 86948 -/* 57372 */ MCD_OPC_CheckField, 21, 1, 1, 129, 115, 0, // Skip to: 86948 -/* 57379 */ MCD_OPC_Decode, 169, 32, 141, 2, // Opcode: UMLALv4i32_v2i64 -/* 57384 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 57422 -/* 57389 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 57392 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57407 -/* 57397 */ MCD_OPC_CheckPredicate, 7, 106, 115, 0, // Skip to: 86948 -/* 57402 */ MCD_OPC_Decode, 166, 25, 141, 2, // Opcode: SQRDMLAHv4i32 -/* 57407 */ MCD_OPC_FilterValue, 1, 96, 115, 0, // Skip to: 86948 -/* 57412 */ MCD_OPC_CheckPredicate, 3, 91, 115, 0, // Skip to: 86948 -/* 57417 */ MCD_OPC_Decode, 132, 30, 133, 2, // Opcode: SUBv4i32 -/* 57422 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 57444 -/* 57427 */ MCD_OPC_CheckPredicate, 3, 76, 115, 0, // Skip to: 86948 -/* 57432 */ MCD_OPC_CheckField, 16, 6, 32, 69, 115, 0, // Skip to: 86948 -/* 57439 */ MCD_OPC_Decode, 209, 3, 138, 2, // Opcode: CMGEv4i32rz -/* 57444 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 57482 -/* 57449 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 57452 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57467 -/* 57457 */ MCD_OPC_CheckPredicate, 7, 46, 115, 0, // Skip to: 86948 -/* 57462 */ MCD_OPC_Decode, 178, 25, 141, 2, // Opcode: SQRDMLSHv4i32 -/* 57467 */ MCD_OPC_FilterValue, 1, 36, 115, 0, // Skip to: 86948 -/* 57472 */ MCD_OPC_CheckPredicate, 3, 31, 115, 0, // Skip to: 86948 -/* 57477 */ MCD_OPC_Decode, 192, 3, 133, 2, // Opcode: CMEQv4i32 -/* 57482 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 57520 -/* 57487 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 57490 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57505 -/* 57495 */ MCD_OPC_CheckPredicate, 10, 8, 115, 0, // Skip to: 86948 -/* 57500 */ MCD_OPC_Decode, 218, 31, 141, 2, // Opcode: UDOTv16i8 -/* 57505 */ MCD_OPC_FilterValue, 1, 254, 114, 0, // Skip to: 86948 -/* 57510 */ MCD_OPC_CheckPredicate, 3, 249, 114, 0, // Skip to: 86948 -/* 57515 */ MCD_OPC_Decode, 228, 19, 141, 2, // Opcode: MLSv4i32 -/* 57520 */ MCD_OPC_FilterValue, 6, 239, 114, 0, // Skip to: 86948 -/* 57525 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 57528 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57543 -/* 57533 */ MCD_OPC_CheckPredicate, 3, 226, 114, 0, // Skip to: 86948 -/* 57538 */ MCD_OPC_Decode, 251, 3, 138, 2, // Opcode: CMLEv4i32rz -/* 57543 */ MCD_OPC_FilterValue, 33, 216, 114, 0, // Skip to: 86948 -/* 57548 */ MCD_OPC_CheckPredicate, 3, 211, 114, 0, // Skip to: 86948 -/* 57553 */ MCD_OPC_Decode, 244, 11, 138, 2, // Opcode: FRINTIv4f32 -/* 57558 */ MCD_OPC_FilterValue, 5, 182, 0, 0, // Skip to: 57745 -/* 57563 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 57566 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57588 -/* 57571 */ MCD_OPC_CheckPredicate, 3, 188, 114, 0, // Skip to: 86948 -/* 57576 */ MCD_OPC_CheckField, 21, 1, 1, 181, 114, 0, // Skip to: 86948 -/* 57583 */ MCD_OPC_Decode, 179, 32, 141, 2, // Opcode: UMLSLv4i32_v2i64 -/* 57588 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 57610 -/* 57593 */ MCD_OPC_CheckPredicate, 3, 166, 114, 0, // Skip to: 86948 -/* 57598 */ MCD_OPC_CheckField, 21, 1, 1, 159, 114, 0, // Skip to: 86948 -/* 57605 */ MCD_OPC_Decode, 236, 31, 133, 2, // Opcode: UMAXPv4i32 -/* 57610 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 57663 -/* 57615 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 57618 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 57633 -/* 57623 */ MCD_OPC_CheckPredicate, 3, 136, 114, 0, // Skip to: 86948 -/* 57628 */ MCD_OPC_Decode, 211, 8, 138, 2, // Opcode: FCVTPUv4f32 -/* 57633 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 57648 -/* 57638 */ MCD_OPC_CheckPredicate, 3, 121, 114, 0, // Skip to: 86948 -/* 57643 */ MCD_OPC_Decode, 245, 31, 160, 2, // Opcode: UMAXVv4i32v -/* 57648 */ MCD_OPC_FilterValue, 49, 111, 114, 0, // Skip to: 86948 -/* 57653 */ MCD_OPC_CheckPredicate, 3, 106, 114, 0, // Skip to: 86948 -/* 57658 */ MCD_OPC_Decode, 146, 32, 160, 2, // Opcode: UMINVv4i32v -/* 57663 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 57685 -/* 57668 */ MCD_OPC_CheckPredicate, 3, 91, 114, 0, // Skip to: 86948 -/* 57673 */ MCD_OPC_CheckField, 21, 1, 1, 84, 114, 0, // Skip to: 86948 -/* 57680 */ MCD_OPC_Decode, 137, 32, 133, 2, // Opcode: UMINPv4i32 -/* 57685 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 57707 -/* 57690 */ MCD_OPC_CheckPredicate, 3, 69, 114, 0, // Skip to: 86948 -/* 57695 */ MCD_OPC_CheckField, 21, 1, 1, 62, 114, 0, // Skip to: 86948 -/* 57702 */ MCD_OPC_Decode, 190, 25, 133, 2, // Opcode: SQRDMULHv4i32 -/* 57707 */ MCD_OPC_FilterValue, 6, 52, 114, 0, // Skip to: 86948 -/* 57712 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 57715 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57730 -/* 57720 */ MCD_OPC_CheckPredicate, 3, 39, 114, 0, // Skip to: 86948 -/* 57725 */ MCD_OPC_Decode, 184, 20, 138, 2, // Opcode: NEGv4i32 -/* 57730 */ MCD_OPC_FilterValue, 33, 29, 114, 0, // Skip to: 86948 -/* 57735 */ MCD_OPC_CheckPredicate, 3, 24, 114, 0, // Skip to: 86948 -/* 57740 */ MCD_OPC_Decode, 155, 9, 138, 2, // Opcode: FCVTZUv4f32 -/* 57745 */ MCD_OPC_FilterValue, 6, 185, 0, 0, // Skip to: 57935 -/* 57750 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 57753 */ MCD_OPC_FilterValue, 0, 116, 0, 0, // Skip to: 57874 -/* 57758 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 57761 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57783 -/* 57766 */ MCD_OPC_CheckPredicate, 3, 249, 113, 0, // Skip to: 86948 -/* 57771 */ MCD_OPC_CheckField, 21, 1, 1, 242, 113, 0, // Skip to: 86948 -/* 57778 */ MCD_OPC_Decode, 199, 32, 133, 2, // Opcode: UMULLv4i32_v2i64 -/* 57783 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 57836 -/* 57788 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 57791 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57806 -/* 57796 */ MCD_OPC_CheckPredicate, 3, 219, 113, 0, // Skip to: 86948 -/* 57801 */ MCD_OPC_Decode, 130, 7, 138, 2, // Opcode: FCMGEv4i32rz -/* 57806 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 57821 -/* 57811 */ MCD_OPC_CheckPredicate, 3, 204, 113, 0, // Skip to: 86948 -/* 57816 */ MCD_OPC_Decode, 242, 33, 138, 2, // Opcode: URSQRTEv4i32 -/* 57821 */ MCD_OPC_FilterValue, 48, 194, 113, 0, // Skip to: 86948 -/* 57826 */ MCD_OPC_CheckPredicate, 3, 189, 113, 0, // Skip to: 86948 -/* 57831 */ MCD_OPC_Decode, 138, 10, 160, 2, // Opcode: FMINNMVv4i32v -/* 57836 */ MCD_OPC_FilterValue, 3, 179, 113, 0, // Skip to: 86948 -/* 57841 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 57844 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57859 -/* 57849 */ MCD_OPC_CheckPredicate, 3, 166, 113, 0, // Skip to: 86948 -/* 57854 */ MCD_OPC_Decode, 177, 7, 138, 2, // Opcode: FCMLEv4i32rz -/* 57859 */ MCD_OPC_FilterValue, 33, 156, 113, 0, // Skip to: 86948 -/* 57864 */ MCD_OPC_CheckPredicate, 3, 151, 113, 0, // Skip to: 86948 -/* 57869 */ MCD_OPC_Decode, 182, 12, 138, 2, // Opcode: FRSQRTEv4f32 -/* 57874 */ MCD_OPC_FilterValue, 1, 141, 113, 0, // Skip to: 86948 -/* 57879 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 57882 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57897 -/* 57887 */ MCD_OPC_CheckPredicate, 11, 128, 113, 0, // Skip to: 86948 -/* 57892 */ MCD_OPC_Decode, 164, 7, 169, 2, // Opcode: FCMLAv4f32 -/* 57897 */ MCD_OPC_FilterValue, 1, 118, 113, 0, // Skip to: 86948 -/* 57902 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 57905 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57920 -/* 57910 */ MCD_OPC_CheckPredicate, 3, 105, 113, 0, // Skip to: 86948 -/* 57915 */ MCD_OPC_Decode, 131, 10, 133, 2, // Opcode: FMINNMPv4f32 -/* 57920 */ MCD_OPC_FilterValue, 2, 95, 113, 0, // Skip to: 86948 -/* 57925 */ MCD_OPC_CheckPredicate, 3, 90, 113, 0, // Skip to: 86948 -/* 57930 */ MCD_OPC_Decode, 137, 6, 133, 2, // Opcode: FABDv4f32 -/* 57935 */ MCD_OPC_FilterValue, 7, 80, 113, 0, // Skip to: 86948 -/* 57940 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 57943 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 58004 -/* 57948 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 57951 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57966 -/* 57956 */ MCD_OPC_CheckPredicate, 11, 59, 113, 0, // Skip to: 86948 -/* 57961 */ MCD_OPC_Decode, 209, 6, 170, 2, // Opcode: FCADDv4f32 -/* 57966 */ MCD_OPC_FilterValue, 1, 49, 113, 0, // Skip to: 86948 -/* 57971 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 57974 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57989 -/* 57979 */ MCD_OPC_CheckPredicate, 3, 36, 113, 0, // Skip to: 86948 -/* 57984 */ MCD_OPC_Decode, 150, 7, 133, 2, // Opcode: FCMGTv4f32 -/* 57989 */ MCD_OPC_FilterValue, 1, 26, 113, 0, // Skip to: 86948 -/* 57994 */ MCD_OPC_CheckPredicate, 3, 21, 113, 0, // Skip to: 86948 -/* 57999 */ MCD_OPC_Decode, 157, 10, 133, 2, // Opcode: FMINPv4f32 -/* 58004 */ MCD_OPC_FilterValue, 2, 69, 0, 0, // Skip to: 58078 -/* 58009 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 58012 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 58034 -/* 58017 */ MCD_OPC_CheckPredicate, 3, 254, 112, 0, // Skip to: 86948 -/* 58022 */ MCD_OPC_CheckField, 12, 1, 1, 247, 112, 0, // Skip to: 86948 -/* 58029 */ MCD_OPC_Decode, 173, 11, 138, 2, // Opcode: FNEGv4f32 -/* 58034 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 58056 -/* 58039 */ MCD_OPC_CheckPredicate, 3, 232, 112, 0, // Skip to: 86948 -/* 58044 */ MCD_OPC_CheckField, 12, 1, 1, 225, 112, 0, // Skip to: 86948 -/* 58051 */ MCD_OPC_Decode, 207, 12, 138, 2, // Opcode: FSQRTv4f32 -/* 58056 */ MCD_OPC_FilterValue, 48, 215, 112, 0, // Skip to: 86948 -/* 58061 */ MCD_OPC_CheckPredicate, 3, 210, 112, 0, // Skip to: 86948 -/* 58066 */ MCD_OPC_CheckField, 12, 1, 1, 203, 112, 0, // Skip to: 86948 -/* 58073 */ MCD_OPC_Decode, 164, 10, 160, 2, // Opcode: FMINVv4i32v -/* 58078 */ MCD_OPC_FilterValue, 3, 193, 112, 0, // Skip to: 86948 -/* 58083 */ MCD_OPC_CheckPredicate, 3, 188, 112, 0, // Skip to: 86948 -/* 58088 */ MCD_OPC_CheckField, 21, 1, 1, 181, 112, 0, // Skip to: 86948 -/* 58095 */ MCD_OPC_CheckField, 12, 1, 0, 174, 112, 0, // Skip to: 86948 -/* 58102 */ MCD_OPC_Decode, 170, 6, 133, 2, // Opcode: FACGTv4f32 -/* 58107 */ MCD_OPC_FilterValue, 6, 164, 112, 0, // Skip to: 86948 -/* 58112 */ MCD_OPC_CheckPredicate, 6, 159, 112, 0, // Skip to: 86948 -/* 58117 */ MCD_OPC_CheckField, 21, 1, 0, 152, 112, 0, // Skip to: 86948 -/* 58124 */ MCD_OPC_Decode, 251, 34, 172, 2, // Opcode: XAR -/* 58129 */ MCD_OPC_FilterValue, 11, 14, 12, 0, // Skip to: 61220 -/* 58134 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 58137 */ MCD_OPC_FilterValue, 0, 154, 1, 0, // Skip to: 58552 -/* 58142 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 58145 */ MCD_OPC_FilterValue, 1, 91, 0, 0, // Skip to: 58241 -/* 58150 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 58153 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58175 -/* 58158 */ MCD_OPC_CheckPredicate, 4, 113, 112, 0, // Skip to: 86948 -/* 58163 */ MCD_OPC_CheckField, 21, 1, 0, 106, 112, 0, // Skip to: 86948 -/* 58170 */ MCD_OPC_Decode, 148, 10, 238, 1, // Opcode: FMINNMv4f16 -/* 58175 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58197 -/* 58180 */ MCD_OPC_CheckPredicate, 4, 91, 112, 0, // Skip to: 86948 -/* 58185 */ MCD_OPC_CheckField, 21, 1, 0, 84, 112, 0, // Skip to: 86948 -/* 58192 */ MCD_OPC_Decode, 130, 10, 238, 1, // Opcode: FMINNMPv4f16 -/* 58197 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58219 -/* 58202 */ MCD_OPC_CheckPredicate, 4, 69, 112, 0, // Skip to: 86948 -/* 58207 */ MCD_OPC_CheckField, 21, 1, 0, 62, 112, 0, // Skip to: 86948 -/* 58214 */ MCD_OPC_Decode, 150, 10, 133, 2, // Opcode: FMINNMv8f16 -/* 58219 */ MCD_OPC_FilterValue, 3, 52, 112, 0, // Skip to: 86948 -/* 58224 */ MCD_OPC_CheckPredicate, 4, 47, 112, 0, // Skip to: 86948 -/* 58229 */ MCD_OPC_CheckField, 21, 1, 0, 40, 112, 0, // Skip to: 86948 -/* 58236 */ MCD_OPC_Decode, 132, 10, 133, 2, // Opcode: FMINNMPv8f16 -/* 58241 */ MCD_OPC_FilterValue, 3, 85, 0, 0, // Skip to: 58331 -/* 58246 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 58249 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58271 -/* 58254 */ MCD_OPC_CheckPredicate, 4, 17, 112, 0, // Skip to: 86948 -/* 58259 */ MCD_OPC_CheckField, 21, 1, 0, 10, 112, 0, // Skip to: 86948 -/* 58266 */ MCD_OPC_Decode, 209, 10, 130, 2, // Opcode: FMLSv4f16 -/* 58271 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 58309 -/* 58276 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 58279 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58294 -/* 58284 */ MCD_OPC_CheckPredicate, 4, 243, 111, 0, // Skip to: 86948 -/* 58289 */ MCD_OPC_Decode, 213, 10, 141, 2, // Opcode: FMLSv8f16 -/* 58294 */ MCD_OPC_FilterValue, 1, 233, 111, 0, // Skip to: 86948 -/* 58299 */ MCD_OPC_CheckPredicate, 3, 228, 111, 0, // Skip to: 86948 -/* 58304 */ MCD_OPC_Decode, 178, 24, 133, 2, // Opcode: SQADDv2i64 -/* 58309 */ MCD_OPC_FilterValue, 3, 218, 111, 0, // Skip to: 86948 -/* 58314 */ MCD_OPC_CheckPredicate, 3, 213, 111, 0, // Skip to: 86948 -/* 58319 */ MCD_OPC_CheckField, 21, 1, 1, 206, 111, 0, // Skip to: 86948 -/* 58326 */ MCD_OPC_Decode, 217, 32, 133, 2, // Opcode: UQADDv2i64 -/* 58331 */ MCD_OPC_FilterValue, 5, 91, 0, 0, // Skip to: 58427 -/* 58336 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 58339 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58361 -/* 58344 */ MCD_OPC_CheckPredicate, 4, 183, 111, 0, // Skip to: 86948 -/* 58349 */ MCD_OPC_CheckField, 21, 1, 0, 176, 111, 0, // Skip to: 86948 -/* 58356 */ MCD_OPC_Decode, 229, 12, 238, 1, // Opcode: FSUBv4f16 -/* 58361 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58383 -/* 58366 */ MCD_OPC_CheckPredicate, 4, 161, 111, 0, // Skip to: 86948 -/* 58371 */ MCD_OPC_CheckField, 21, 1, 0, 154, 111, 0, // Skip to: 86948 -/* 58378 */ MCD_OPC_Decode, 136, 6, 238, 1, // Opcode: FABDv4f16 -/* 58383 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58405 -/* 58388 */ MCD_OPC_CheckPredicate, 4, 139, 111, 0, // Skip to: 86948 -/* 58393 */ MCD_OPC_CheckField, 21, 1, 0, 132, 111, 0, // Skip to: 86948 -/* 58400 */ MCD_OPC_Decode, 231, 12, 133, 2, // Opcode: FSUBv8f16 -/* 58405 */ MCD_OPC_FilterValue, 3, 122, 111, 0, // Skip to: 86948 -/* 58410 */ MCD_OPC_CheckPredicate, 4, 117, 111, 0, // Skip to: 86948 -/* 58415 */ MCD_OPC_CheckField, 21, 1, 0, 110, 111, 0, // Skip to: 86948 -/* 58422 */ MCD_OPC_Decode, 138, 6, 133, 2, // Opcode: FABDv8f16 -/* 58427 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 58456 -/* 58432 */ MCD_OPC_CheckPredicate, 3, 95, 111, 0, // Skip to: 86948 -/* 58437 */ MCD_OPC_CheckField, 29, 3, 2, 88, 111, 0, // Skip to: 86948 -/* 58444 */ MCD_OPC_CheckField, 21, 1, 0, 81, 111, 0, // Skip to: 86948 -/* 58451 */ MCD_OPC_Decode, 198, 34, 133, 2, // Opcode: UZP1v2i64 -/* 58456 */ MCD_OPC_FilterValue, 7, 71, 111, 0, // Skip to: 86948 -/* 58461 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 58464 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58486 -/* 58469 */ MCD_OPC_CheckPredicate, 3, 58, 111, 0, // Skip to: 86948 -/* 58474 */ MCD_OPC_CheckField, 21, 1, 1, 51, 111, 0, // Skip to: 86948 -/* 58481 */ MCD_OPC_Decode, 202, 20, 238, 1, // Opcode: ORNv8i8 -/* 58486 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58508 -/* 58491 */ MCD_OPC_CheckPredicate, 3, 36, 111, 0, // Skip to: 86948 -/* 58496 */ MCD_OPC_CheckField, 21, 1, 1, 29, 111, 0, // Skip to: 86948 -/* 58503 */ MCD_OPC_Decode, 194, 2, 238, 1, // Opcode: BIFv8i8 -/* 58508 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58530 -/* 58513 */ MCD_OPC_CheckPredicate, 3, 14, 111, 0, // Skip to: 86948 -/* 58518 */ MCD_OPC_CheckField, 21, 1, 1, 7, 111, 0, // Skip to: 86948 -/* 58525 */ MCD_OPC_Decode, 201, 20, 133, 2, // Opcode: ORNv16i8 -/* 58530 */ MCD_OPC_FilterValue, 3, 253, 110, 0, // Skip to: 86948 -/* 58535 */ MCD_OPC_CheckPredicate, 3, 248, 110, 0, // Skip to: 86948 -/* 58540 */ MCD_OPC_CheckField, 21, 1, 1, 241, 110, 0, // Skip to: 86948 -/* 58547 */ MCD_OPC_Decode, 193, 2, 133, 2, // Opcode: BIFv16i8 -/* 58552 */ MCD_OPC_FilterValue, 1, 218, 1, 0, // Skip to: 59031 -/* 58557 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 58560 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 58612 -/* 58565 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 58568 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58590 -/* 58573 */ MCD_OPC_CheckPredicate, 4, 210, 110, 0, // Skip to: 86948 -/* 58578 */ MCD_OPC_CheckField, 21, 1, 0, 203, 110, 0, // Skip to: 86948 -/* 58585 */ MCD_OPC_Decode, 149, 7, 238, 1, // Opcode: FCMGTv4f16 -/* 58590 */ MCD_OPC_FilterValue, 3, 193, 110, 0, // Skip to: 86948 -/* 58595 */ MCD_OPC_CheckPredicate, 4, 188, 110, 0, // Skip to: 86948 -/* 58600 */ MCD_OPC_CheckField, 21, 1, 0, 181, 110, 0, // Skip to: 86948 -/* 58607 */ MCD_OPC_Decode, 153, 7, 133, 2, // Opcode: FCMGTv8f16 -/* 58612 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 58641 -/* 58617 */ MCD_OPC_CheckPredicate, 3, 166, 110, 0, // Skip to: 86948 -/* 58622 */ MCD_OPC_CheckField, 29, 3, 2, 159, 110, 0, // Skip to: 86948 -/* 58629 */ MCD_OPC_CheckField, 21, 1, 0, 152, 110, 0, // Skip to: 86948 -/* 58636 */ MCD_OPC_Decode, 215, 30, 133, 2, // Opcode: TRN1v2i64 -/* 58641 */ MCD_OPC_FilterValue, 3, 85, 0, 0, // Skip to: 58731 -/* 58646 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 58649 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58671 -/* 58654 */ MCD_OPC_CheckPredicate, 4, 129, 110, 0, // Skip to: 86948 -/* 58659 */ MCD_OPC_CheckField, 21, 1, 0, 122, 110, 0, // Skip to: 86948 -/* 58666 */ MCD_OPC_Decode, 169, 6, 238, 1, // Opcode: FACGTv4f16 -/* 58671 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58693 -/* 58676 */ MCD_OPC_CheckPredicate, 3, 107, 110, 0, // Skip to: 86948 -/* 58681 */ MCD_OPC_CheckField, 21, 1, 1, 100, 110, 0, // Skip to: 86948 -/* 58688 */ MCD_OPC_Decode, 160, 26, 133, 2, // Opcode: SQSUBv2i64 -/* 58693 */ MCD_OPC_FilterValue, 3, 90, 110, 0, // Skip to: 86948 -/* 58698 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 58701 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58716 -/* 58706 */ MCD_OPC_CheckPredicate, 4, 77, 110, 0, // Skip to: 86948 -/* 58711 */ MCD_OPC_Decode, 171, 6, 133, 2, // Opcode: FACGTv8f16 -/* 58716 */ MCD_OPC_FilterValue, 1, 67, 110, 0, // Skip to: 86948 -/* 58721 */ MCD_OPC_CheckPredicate, 3, 62, 110, 0, // Skip to: 86948 -/* 58726 */ MCD_OPC_Decode, 203, 33, 133, 2, // Opcode: UQSUBv2i64 -/* 58731 */ MCD_OPC_FilterValue, 5, 123, 0, 0, // Skip to: 58859 -/* 58736 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 58739 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58761 -/* 58744 */ MCD_OPC_CheckPredicate, 4, 39, 110, 0, // Skip to: 86948 -/* 58749 */ MCD_OPC_CheckField, 21, 1, 0, 32, 110, 0, // Skip to: 86948 -/* 58756 */ MCD_OPC_Decode, 174, 10, 238, 1, // Opcode: FMINv4f16 -/* 58761 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58783 -/* 58766 */ MCD_OPC_CheckPredicate, 4, 17, 110, 0, // Skip to: 86948 -/* 58771 */ MCD_OPC_CheckField, 21, 1, 0, 10, 110, 0, // Skip to: 86948 -/* 58778 */ MCD_OPC_Decode, 156, 10, 238, 1, // Opcode: FMINPv4f16 -/* 58783 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 58821 -/* 58788 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 58791 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58806 -/* 58796 */ MCD_OPC_CheckPredicate, 4, 243, 109, 0, // Skip to: 86948 -/* 58801 */ MCD_OPC_Decode, 176, 10, 133, 2, // Opcode: FMINv8f16 -/* 58806 */ MCD_OPC_FilterValue, 1, 233, 109, 0, // Skip to: 86948 -/* 58811 */ MCD_OPC_CheckPredicate, 3, 228, 109, 0, // Skip to: 86948 -/* 58816 */ MCD_OPC_Decode, 220, 3, 133, 2, // Opcode: CMGTv2i64 -/* 58821 */ MCD_OPC_FilterValue, 3, 218, 109, 0, // Skip to: 86948 -/* 58826 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 58829 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58844 -/* 58834 */ MCD_OPC_CheckPredicate, 4, 205, 109, 0, // Skip to: 86948 -/* 58839 */ MCD_OPC_Decode, 158, 10, 133, 2, // Opcode: FMINPv8f16 -/* 58844 */ MCD_OPC_FilterValue, 1, 195, 109, 0, // Skip to: 86948 -/* 58849 */ MCD_OPC_CheckPredicate, 3, 190, 109, 0, // Skip to: 86948 -/* 58854 */ MCD_OPC_Decode, 233, 3, 133, 2, // Opcode: CMHIv2i64 -/* 58859 */ MCD_OPC_FilterValue, 6, 77, 0, 0, // Skip to: 58941 -/* 58864 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 58867 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58889 -/* 58872 */ MCD_OPC_CheckPredicate, 3, 167, 109, 0, // Skip to: 86948 -/* 58877 */ MCD_OPC_CheckField, 29, 3, 2, 160, 109, 0, // Skip to: 86948 -/* 58884 */ MCD_OPC_Decode, 143, 35, 133, 2, // Opcode: ZIP1v2i64 -/* 58889 */ MCD_OPC_FilterValue, 1, 150, 109, 0, // Skip to: 86948 -/* 58894 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 58897 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58919 -/* 58902 */ MCD_OPC_CheckPredicate, 3, 137, 109, 0, // Skip to: 86948 -/* 58907 */ MCD_OPC_CheckField, 16, 5, 0, 130, 109, 0, // Skip to: 86948 -/* 58914 */ MCD_OPC_Decode, 147, 30, 147, 2, // Opcode: SUQADDv2i64 -/* 58919 */ MCD_OPC_FilterValue, 3, 120, 109, 0, // Skip to: 86948 -/* 58924 */ MCD_OPC_CheckPredicate, 3, 115, 109, 0, // Skip to: 86948 -/* 58929 */ MCD_OPC_CheckField, 16, 5, 0, 108, 109, 0, // Skip to: 86948 -/* 58936 */ MCD_OPC_Decode, 151, 34, 147, 2, // Opcode: USQADDv2i64 -/* 58941 */ MCD_OPC_FilterValue, 7, 98, 109, 0, // Skip to: 86948 -/* 58946 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 58949 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58971 -/* 58954 */ MCD_OPC_CheckPredicate, 4, 85, 109, 0, // Skip to: 86948 -/* 58959 */ MCD_OPC_CheckField, 21, 1, 0, 78, 109, 0, // Skip to: 86948 -/* 58966 */ MCD_OPC_Decode, 192, 12, 238, 1, // Opcode: FRSQRTSv4f16 -/* 58971 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 59009 -/* 58976 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 58979 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58994 -/* 58984 */ MCD_OPC_CheckPredicate, 4, 55, 109, 0, // Skip to: 86948 -/* 58989 */ MCD_OPC_Decode, 194, 12, 133, 2, // Opcode: FRSQRTSv8f16 -/* 58994 */ MCD_OPC_FilterValue, 1, 45, 109, 0, // Skip to: 86948 -/* 58999 */ MCD_OPC_CheckPredicate, 3, 40, 109, 0, // Skip to: 86948 -/* 59004 */ MCD_OPC_Decode, 204, 3, 133, 2, // Opcode: CMGEv2i64 -/* 59009 */ MCD_OPC_FilterValue, 3, 30, 109, 0, // Skip to: 86948 -/* 59014 */ MCD_OPC_CheckPredicate, 3, 25, 109, 0, // Skip to: 86948 -/* 59019 */ MCD_OPC_CheckField, 21, 1, 1, 18, 109, 0, // Skip to: 86948 -/* 59026 */ MCD_OPC_Decode, 241, 3, 133, 2, // Opcode: CMHSv2i64 -/* 59031 */ MCD_OPC_FilterValue, 2, 240, 0, 0, // Skip to: 59276 -/* 59036 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 59039 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 59091 -/* 59044 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59047 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59069 -/* 59052 */ MCD_OPC_CheckPredicate, 3, 243, 108, 0, // Skip to: 86948 -/* 59057 */ MCD_OPC_CheckField, 21, 1, 1, 236, 108, 0, // Skip to: 86948 -/* 59064 */ MCD_OPC_Decode, 230, 26, 133, 2, // Opcode: SSHLv2i64 -/* 59069 */ MCD_OPC_FilterValue, 3, 226, 108, 0, // Skip to: 86948 -/* 59074 */ MCD_OPC_CheckPredicate, 3, 221, 108, 0, // Skip to: 86948 -/* 59079 */ MCD_OPC_CheckField, 21, 1, 1, 214, 108, 0, // Skip to: 86948 -/* 59086 */ MCD_OPC_Decode, 132, 34, 133, 2, // Opcode: USHLv2i64 -/* 59091 */ MCD_OPC_FilterValue, 3, 47, 0, 0, // Skip to: 59143 -/* 59096 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59099 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59121 -/* 59104 */ MCD_OPC_CheckPredicate, 3, 191, 108, 0, // Skip to: 86948 -/* 59109 */ MCD_OPC_CheckField, 21, 1, 1, 184, 108, 0, // Skip to: 86948 -/* 59116 */ MCD_OPC_Decode, 246, 25, 133, 2, // Opcode: SQSHLv2i64 -/* 59121 */ MCD_OPC_FilterValue, 3, 174, 108, 0, // Skip to: 86948 -/* 59126 */ MCD_OPC_CheckPredicate, 3, 169, 108, 0, // Skip to: 86948 -/* 59131 */ MCD_OPC_CheckField, 21, 1, 1, 162, 108, 0, // Skip to: 86948 -/* 59138 */ MCD_OPC_Decode, 170, 33, 133, 2, // Opcode: UQSHLv2i64 -/* 59143 */ MCD_OPC_FilterValue, 5, 47, 0, 0, // Skip to: 59195 -/* 59148 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59151 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59173 -/* 59156 */ MCD_OPC_CheckPredicate, 3, 139, 108, 0, // Skip to: 86948 -/* 59161 */ MCD_OPC_CheckField, 21, 1, 1, 132, 108, 0, // Skip to: 86948 -/* 59168 */ MCD_OPC_Decode, 200, 26, 133, 2, // Opcode: SRSHLv2i64 -/* 59173 */ MCD_OPC_FilterValue, 3, 122, 108, 0, // Skip to: 86948 -/* 59178 */ MCD_OPC_CheckPredicate, 3, 117, 108, 0, // Skip to: 86948 -/* 59183 */ MCD_OPC_CheckField, 21, 1, 1, 110, 108, 0, // Skip to: 86948 -/* 59190 */ MCD_OPC_Decode, 228, 33, 133, 2, // Opcode: URSHLv2i64 -/* 59195 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 59224 -/* 59200 */ MCD_OPC_CheckPredicate, 3, 95, 108, 0, // Skip to: 86948 -/* 59205 */ MCD_OPC_CheckField, 29, 3, 2, 88, 108, 0, // Skip to: 86948 -/* 59212 */ MCD_OPC_CheckField, 21, 1, 0, 81, 108, 0, // Skip to: 86948 -/* 59219 */ MCD_OPC_Decode, 213, 34, 133, 2, // Opcode: UZP2v2i64 -/* 59224 */ MCD_OPC_FilterValue, 7, 71, 108, 0, // Skip to: 86948 -/* 59229 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59232 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59254 -/* 59237 */ MCD_OPC_CheckPredicate, 3, 58, 108, 0, // Skip to: 86948 -/* 59242 */ MCD_OPC_CheckField, 21, 1, 1, 51, 108, 0, // Skip to: 86948 -/* 59249 */ MCD_OPC_Decode, 200, 25, 133, 2, // Opcode: SQRSHLv2i64 -/* 59254 */ MCD_OPC_FilterValue, 3, 41, 108, 0, // Skip to: 86948 -/* 59259 */ MCD_OPC_CheckPredicate, 3, 36, 108, 0, // Skip to: 86948 -/* 59264 */ MCD_OPC_CheckField, 21, 1, 1, 29, 108, 0, // Skip to: 86948 -/* 59271 */ MCD_OPC_Decode, 144, 33, 133, 2, // Opcode: UQRSHLv2i64 -/* 59276 */ MCD_OPC_FilterValue, 3, 114, 0, 0, // Skip to: 59395 -/* 59281 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 59284 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 59313 -/* 59289 */ MCD_OPC_CheckPredicate, 3, 6, 108, 0, // Skip to: 86948 -/* 59294 */ MCD_OPC_CheckField, 29, 3, 2, 255, 107, 0, // Skip to: 86948 -/* 59301 */ MCD_OPC_CheckField, 21, 1, 0, 248, 107, 0, // Skip to: 86948 -/* 59308 */ MCD_OPC_Decode, 230, 30, 133, 2, // Opcode: TRN2v2i64 -/* 59313 */ MCD_OPC_FilterValue, 6, 238, 107, 0, // Skip to: 86948 -/* 59318 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 59321 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 59343 -/* 59326 */ MCD_OPC_CheckPredicate, 3, 225, 107, 0, // Skip to: 86948 -/* 59331 */ MCD_OPC_CheckField, 29, 3, 2, 218, 107, 0, // Skip to: 86948 -/* 59338 */ MCD_OPC_Decode, 158, 35, 133, 2, // Opcode: ZIP2v2i64 -/* 59343 */ MCD_OPC_FilterValue, 1, 208, 107, 0, // Skip to: 86948 -/* 59348 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59351 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59373 -/* 59356 */ MCD_OPC_CheckPredicate, 3, 195, 107, 0, // Skip to: 86948 -/* 59361 */ MCD_OPC_CheckField, 16, 5, 0, 188, 107, 0, // Skip to: 86948 -/* 59368 */ MCD_OPC_Decode, 159, 24, 138, 2, // Opcode: SQABSv2i64 -/* 59373 */ MCD_OPC_FilterValue, 3, 178, 107, 0, // Skip to: 86948 -/* 59378 */ MCD_OPC_CheckPredicate, 3, 173, 107, 0, // Skip to: 86948 -/* 59383 */ MCD_OPC_CheckField, 16, 5, 0, 166, 107, 0, // Skip to: 86948 -/* 59390 */ MCD_OPC_Decode, 153, 25, 138, 2, // Opcode: SQNEGv2i64 -/* 59395 */ MCD_OPC_FilterValue, 4, 166, 1, 0, // Skip to: 59822 -/* 59400 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 59403 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 59432 -/* 59408 */ MCD_OPC_CheckPredicate, 6, 143, 107, 0, // Skip to: 86948 -/* 59413 */ MCD_OPC_CheckField, 29, 3, 6, 136, 107, 0, // Skip to: 86948 -/* 59420 */ MCD_OPC_CheckField, 16, 6, 0, 129, 107, 0, // Skip to: 86948 -/* 59427 */ MCD_OPC_Decode, 253, 22, 173, 2, // Opcode: SHA512SU0 -/* 59432 */ MCD_OPC_FilterValue, 1, 69, 0, 0, // Skip to: 59506 -/* 59437 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59440 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59462 -/* 59445 */ MCD_OPC_CheckPredicate, 3, 106, 107, 0, // Skip to: 86948 -/* 59450 */ MCD_OPC_CheckField, 21, 1, 1, 99, 107, 0, // Skip to: 86948 -/* 59457 */ MCD_OPC_Decode, 197, 1, 133, 2, // Opcode: ADDv2i64 -/* 59462 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 59484 -/* 59467 */ MCD_OPC_CheckPredicate, 3, 84, 107, 0, // Skip to: 86948 -/* 59472 */ MCD_OPC_CheckField, 21, 1, 1, 77, 107, 0, // Skip to: 86948 -/* 59479 */ MCD_OPC_Decode, 130, 30, 133, 2, // Opcode: SUBv2i64 -/* 59484 */ MCD_OPC_FilterValue, 6, 67, 107, 0, // Skip to: 86948 -/* 59489 */ MCD_OPC_CheckPredicate, 9, 62, 107, 0, // Skip to: 86948 -/* 59494 */ MCD_OPC_CheckField, 16, 6, 0, 55, 107, 0, // Skip to: 86948 -/* 59501 */ MCD_OPC_Decode, 174, 23, 173, 2, // Opcode: SM4E -/* 59506 */ MCD_OPC_FilterValue, 2, 101, 0, 0, // Skip to: 59612 -/* 59511 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 59514 */ MCD_OPC_FilterValue, 32, 33, 0, 0, // Skip to: 59552 -/* 59519 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59522 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 59537 -/* 59527 */ MCD_OPC_CheckPredicate, 3, 24, 107, 0, // Skip to: 86948 -/* 59532 */ MCD_OPC_Decode, 221, 3, 138, 2, // Opcode: CMGTv2i64rz -/* 59537 */ MCD_OPC_FilterValue, 3, 14, 107, 0, // Skip to: 86948 -/* 59542 */ MCD_OPC_CheckPredicate, 3, 9, 107, 0, // Skip to: 86948 -/* 59547 */ MCD_OPC_Decode, 205, 3, 138, 2, // Opcode: CMGEv2i64rz -/* 59552 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 59574 -/* 59557 */ MCD_OPC_CheckPredicate, 3, 250, 106, 0, // Skip to: 86948 -/* 59562 */ MCD_OPC_CheckField, 29, 3, 2, 243, 106, 0, // Skip to: 86948 -/* 59569 */ MCD_OPC_Decode, 147, 12, 138, 2, // Opcode: FRINTPv2f64 -/* 59574 */ MCD_OPC_FilterValue, 57, 233, 106, 0, // Skip to: 86948 -/* 59579 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59582 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 59597 -/* 59587 */ MCD_OPC_CheckPredicate, 4, 220, 106, 0, // Skip to: 86948 -/* 59592 */ MCD_OPC_Decode, 148, 12, 239, 1, // Opcode: FRINTPv4f16 -/* 59597 */ MCD_OPC_FilterValue, 2, 210, 106, 0, // Skip to: 86948 -/* 59602 */ MCD_OPC_CheckPredicate, 4, 205, 106, 0, // Skip to: 86948 -/* 59607 */ MCD_OPC_Decode, 150, 12, 138, 2, // Opcode: FRINTPv8f16 -/* 59612 */ MCD_OPC_FilterValue, 3, 47, 0, 0, // Skip to: 59664 -/* 59617 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59620 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59642 -/* 59625 */ MCD_OPC_CheckPredicate, 3, 182, 106, 0, // Skip to: 86948 -/* 59630 */ MCD_OPC_CheckField, 21, 1, 1, 175, 106, 0, // Skip to: 86948 -/* 59637 */ MCD_OPC_Decode, 236, 4, 133, 2, // Opcode: CMTSTv2i64 -/* 59642 */ MCD_OPC_FilterValue, 3, 165, 106, 0, // Skip to: 86948 -/* 59647 */ MCD_OPC_CheckPredicate, 3, 160, 106, 0, // Skip to: 86948 -/* 59652 */ MCD_OPC_CheckField, 21, 1, 1, 153, 106, 0, // Skip to: 86948 -/* 59659 */ MCD_OPC_Decode, 188, 3, 133, 2, // Opcode: CMEQv2i64 -/* 59664 */ MCD_OPC_FilterValue, 6, 143, 106, 0, // Skip to: 86948 -/* 59669 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59672 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 59694 -/* 59677 */ MCD_OPC_CheckPredicate, 4, 130, 106, 0, // Skip to: 86948 -/* 59682 */ MCD_OPC_CheckField, 16, 6, 57, 123, 106, 0, // Skip to: 86948 -/* 59689 */ MCD_OPC_Decode, 170, 12, 239, 1, // Opcode: FRINTZv4f16 -/* 59694 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 59716 -/* 59699 */ MCD_OPC_CheckPredicate, 4, 108, 106, 0, // Skip to: 86948 -/* 59704 */ MCD_OPC_CheckField, 16, 6, 57, 101, 106, 0, // Skip to: 86948 -/* 59711 */ MCD_OPC_Decode, 243, 11, 239, 1, // Opcode: FRINTIv4f16 -/* 59716 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 59769 -/* 59721 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 59724 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 59739 -/* 59729 */ MCD_OPC_CheckPredicate, 3, 78, 106, 0, // Skip to: 86948 -/* 59734 */ MCD_OPC_Decode, 189, 3, 138, 2, // Opcode: CMEQv2i64rz -/* 59739 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 59754 -/* 59744 */ MCD_OPC_CheckPredicate, 3, 63, 106, 0, // Skip to: 86948 -/* 59749 */ MCD_OPC_Decode, 169, 12, 138, 2, // Opcode: FRINTZv2f64 -/* 59754 */ MCD_OPC_FilterValue, 57, 53, 106, 0, // Skip to: 86948 -/* 59759 */ MCD_OPC_CheckPredicate, 4, 48, 106, 0, // Skip to: 86948 -/* 59764 */ MCD_OPC_Decode, 172, 12, 138, 2, // Opcode: FRINTZv8f16 -/* 59769 */ MCD_OPC_FilterValue, 3, 38, 106, 0, // Skip to: 86948 -/* 59774 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 59777 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 59792 -/* 59782 */ MCD_OPC_CheckPredicate, 3, 25, 106, 0, // Skip to: 86948 -/* 59787 */ MCD_OPC_Decode, 249, 3, 138, 2, // Opcode: CMLEv2i64rz -/* 59792 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 59807 -/* 59797 */ MCD_OPC_CheckPredicate, 3, 10, 106, 0, // Skip to: 86948 -/* 59802 */ MCD_OPC_Decode, 242, 11, 138, 2, // Opcode: FRINTIv2f64 -/* 59807 */ MCD_OPC_FilterValue, 57, 0, 106, 0, // Skip to: 86948 -/* 59812 */ MCD_OPC_CheckPredicate, 4, 251, 105, 0, // Skip to: 86948 -/* 59817 */ MCD_OPC_Decode, 245, 11, 138, 2, // Opcode: FRINTIv8f16 -/* 59822 */ MCD_OPC_FilterValue, 5, 93, 1, 0, // Skip to: 60176 -/* 59827 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 59830 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 59882 -/* 59835 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 59838 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59860 -/* 59843 */ MCD_OPC_CheckPredicate, 4, 220, 105, 0, // Skip to: 86948 -/* 59848 */ MCD_OPC_CheckField, 16, 6, 57, 213, 105, 0, // Skip to: 86948 -/* 59855 */ MCD_OPC_Decode, 196, 8, 239, 1, // Opcode: FCVTPSv4f16 -/* 59860 */ MCD_OPC_FilterValue, 6, 203, 105, 0, // Skip to: 86948 -/* 59865 */ MCD_OPC_CheckPredicate, 4, 198, 105, 0, // Skip to: 86948 -/* 59870 */ MCD_OPC_CheckField, 16, 6, 57, 191, 105, 0, // Skip to: 86948 -/* 59877 */ MCD_OPC_Decode, 247, 8, 239, 1, // Opcode: FCVTZSv4f16 -/* 59882 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 59934 -/* 59887 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 59890 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59912 -/* 59895 */ MCD_OPC_CheckPredicate, 4, 168, 105, 0, // Skip to: 86948 -/* 59900 */ MCD_OPC_CheckField, 16, 6, 57, 161, 105, 0, // Skip to: 86948 -/* 59907 */ MCD_OPC_Decode, 210, 8, 239, 1, // Opcode: FCVTPUv4f16 -/* 59912 */ MCD_OPC_FilterValue, 6, 151, 105, 0, // Skip to: 86948 -/* 59917 */ MCD_OPC_CheckPredicate, 4, 146, 105, 0, // Skip to: 86948 -/* 59922 */ MCD_OPC_CheckField, 16, 6, 57, 139, 105, 0, // Skip to: 86948 -/* 59929 */ MCD_OPC_Decode, 154, 9, 239, 1, // Opcode: FCVTZUv4f16 -/* 59934 */ MCD_OPC_FilterValue, 2, 131, 0, 0, // Skip to: 60070 -/* 59939 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 59942 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 59995 -/* 59947 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 59950 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 59965 -/* 59955 */ MCD_OPC_CheckPredicate, 3, 108, 105, 0, // Skip to: 86948 -/* 59960 */ MCD_OPC_Decode, 129, 4, 138, 2, // Opcode: CMLTv2i64rz -/* 59965 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 59980 -/* 59970 */ MCD_OPC_CheckPredicate, 3, 93, 105, 0, // Skip to: 86948 -/* 59975 */ MCD_OPC_Decode, 195, 8, 138, 2, // Opcode: FCVTPSv2f64 -/* 59980 */ MCD_OPC_FilterValue, 57, 83, 105, 0, // Skip to: 86948 -/* 59985 */ MCD_OPC_CheckPredicate, 4, 78, 105, 0, // Skip to: 86948 -/* 59990 */ MCD_OPC_Decode, 198, 8, 138, 2, // Opcode: FCVTPSv8f16 -/* 59995 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 60048 -/* 60000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 60003 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 60018 -/* 60008 */ MCD_OPC_CheckPredicate, 3, 55, 105, 0, // Skip to: 86948 -/* 60013 */ MCD_OPC_Decode, 133, 1, 138, 2, // Opcode: ABSv2i64 -/* 60018 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 60033 -/* 60023 */ MCD_OPC_CheckPredicate, 3, 40, 105, 0, // Skip to: 86948 -/* 60028 */ MCD_OPC_Decode, 244, 8, 138, 2, // Opcode: FCVTZSv2f64 -/* 60033 */ MCD_OPC_FilterValue, 57, 30, 105, 0, // Skip to: 86948 -/* 60038 */ MCD_OPC_CheckPredicate, 4, 25, 105, 0, // Skip to: 86948 -/* 60043 */ MCD_OPC_Decode, 251, 8, 138, 2, // Opcode: FCVTZSv8f16 -/* 60048 */ MCD_OPC_FilterValue, 7, 15, 105, 0, // Skip to: 86948 -/* 60053 */ MCD_OPC_CheckPredicate, 3, 10, 105, 0, // Skip to: 86948 -/* 60058 */ MCD_OPC_CheckField, 21, 1, 1, 3, 105, 0, // Skip to: 86948 -/* 60065 */ MCD_OPC_Decode, 151, 1, 133, 2, // Opcode: ADDPv2i64 -/* 60070 */ MCD_OPC_FilterValue, 3, 249, 104, 0, // Skip to: 86948 -/* 60075 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 60078 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 60100 -/* 60083 */ MCD_OPC_CheckPredicate, 3, 236, 104, 0, // Skip to: 86948 -/* 60088 */ MCD_OPC_CheckField, 10, 3, 6, 229, 104, 0, // Skip to: 86948 -/* 60095 */ MCD_OPC_Decode, 182, 20, 138, 2, // Opcode: NEGv2i64 -/* 60100 */ MCD_OPC_FilterValue, 33, 33, 0, 0, // Skip to: 60138 -/* 60105 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 60108 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60123 -/* 60113 */ MCD_OPC_CheckPredicate, 3, 206, 104, 0, // Skip to: 86948 -/* 60118 */ MCD_OPC_Decode, 209, 8, 138, 2, // Opcode: FCVTPUv2f64 -/* 60123 */ MCD_OPC_FilterValue, 6, 196, 104, 0, // Skip to: 86948 -/* 60128 */ MCD_OPC_CheckPredicate, 3, 191, 104, 0, // Skip to: 86948 -/* 60133 */ MCD_OPC_Decode, 151, 9, 138, 2, // Opcode: FCVTZUv2f64 -/* 60138 */ MCD_OPC_FilterValue, 57, 181, 104, 0, // Skip to: 86948 -/* 60143 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 60146 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60161 -/* 60151 */ MCD_OPC_CheckPredicate, 4, 168, 104, 0, // Skip to: 86948 -/* 60156 */ MCD_OPC_Decode, 212, 8, 138, 2, // Opcode: FCVTPUv8f16 -/* 60161 */ MCD_OPC_FilterValue, 6, 158, 104, 0, // Skip to: 86948 -/* 60166 */ MCD_OPC_CheckPredicate, 4, 153, 104, 0, // Skip to: 86948 -/* 60171 */ MCD_OPC_Decode, 158, 9, 138, 2, // Opcode: FCVTZUv8f16 -/* 60176 */ MCD_OPC_FilterValue, 6, 4, 2, 0, // Skip to: 60697 -/* 60181 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 60184 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 60252 -/* 60189 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 60192 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 60214 -/* 60197 */ MCD_OPC_CheckPredicate, 4, 122, 104, 0, // Skip to: 86948 -/* 60202 */ MCD_OPC_CheckField, 16, 6, 56, 115, 104, 0, // Skip to: 86948 -/* 60209 */ MCD_OPC_Decode, 151, 7, 239, 1, // Opcode: FCMGTv4i16rz -/* 60214 */ MCD_OPC_FilterValue, 6, 105, 104, 0, // Skip to: 86948 -/* 60219 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 60222 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 60237 -/* 60227 */ MCD_OPC_CheckPredicate, 4, 92, 104, 0, // Skip to: 86948 -/* 60232 */ MCD_OPC_Decode, 235, 6, 239, 1, // Opcode: FCMEQv4i16rz -/* 60237 */ MCD_OPC_FilterValue, 57, 82, 104, 0, // Skip to: 86948 -/* 60242 */ MCD_OPC_CheckPredicate, 4, 77, 104, 0, // Skip to: 86948 -/* 60247 */ MCD_OPC_Decode, 204, 11, 239, 1, // Opcode: FRECPEv4f16 -/* 60252 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 60320 -/* 60257 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 60260 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 60282 -/* 60265 */ MCD_OPC_CheckPredicate, 4, 54, 104, 0, // Skip to: 86948 -/* 60270 */ MCD_OPC_CheckField, 16, 6, 56, 47, 104, 0, // Skip to: 86948 -/* 60277 */ MCD_OPC_Decode, 129, 7, 239, 1, // Opcode: FCMGEv4i16rz -/* 60282 */ MCD_OPC_FilterValue, 6, 37, 104, 0, // Skip to: 86948 -/* 60287 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 60290 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 60305 -/* 60295 */ MCD_OPC_CheckPredicate, 4, 24, 104, 0, // Skip to: 86948 -/* 60300 */ MCD_OPC_Decode, 176, 7, 239, 1, // Opcode: FCMLEv4i16rz -/* 60305 */ MCD_OPC_FilterValue, 57, 14, 104, 0, // Skip to: 86948 -/* 60310 */ MCD_OPC_CheckPredicate, 4, 9, 104, 0, // Skip to: 86948 -/* 60315 */ MCD_OPC_Decode, 181, 12, 239, 1, // Opcode: FRSQRTEv4f16 -/* 60320 */ MCD_OPC_FilterValue, 2, 175, 0, 0, // Skip to: 60500 -/* 60325 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 60328 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 60350 -/* 60333 */ MCD_OPC_CheckPredicate, 3, 242, 103, 0, // Skip to: 86948 -/* 60338 */ MCD_OPC_CheckField, 21, 1, 1, 235, 103, 0, // Skip to: 86948 -/* 60345 */ MCD_OPC_Decode, 147, 10, 133, 2, // Opcode: FMINNMv2f64 -/* 60350 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 60388 -/* 60355 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 60358 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 60373 -/* 60363 */ MCD_OPC_CheckPredicate, 3, 212, 103, 0, // Skip to: 86948 -/* 60368 */ MCD_OPC_Decode, 148, 7, 138, 2, // Opcode: FCMGTv2i64rz -/* 60373 */ MCD_OPC_FilterValue, 56, 202, 103, 0, // Skip to: 86948 -/* 60378 */ MCD_OPC_CheckPredicate, 4, 197, 103, 0, // Skip to: 86948 -/* 60383 */ MCD_OPC_Decode, 154, 7, 138, 2, // Opcode: FCMGTv8i16rz -/* 60388 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 60410 -/* 60393 */ MCD_OPC_CheckPredicate, 3, 182, 103, 0, // Skip to: 86948 -/* 60398 */ MCD_OPC_CheckField, 21, 1, 1, 175, 103, 0, // Skip to: 86948 -/* 60405 */ MCD_OPC_Decode, 206, 10, 141, 2, // Opcode: FMLSv2f64 -/* 60410 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 60432 -/* 60415 */ MCD_OPC_CheckPredicate, 3, 160, 103, 0, // Skip to: 86948 -/* 60420 */ MCD_OPC_CheckField, 21, 1, 1, 153, 103, 0, // Skip to: 86948 -/* 60427 */ MCD_OPC_Decode, 228, 12, 133, 2, // Opcode: FSUBv2f64 -/* 60432 */ MCD_OPC_FilterValue, 6, 143, 103, 0, // Skip to: 86948 -/* 60437 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 60440 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 60455 -/* 60445 */ MCD_OPC_CheckPredicate, 3, 130, 103, 0, // Skip to: 86948 -/* 60450 */ MCD_OPC_Decode, 232, 6, 138, 2, // Opcode: FCMEQv2i64rz -/* 60455 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 60470 -/* 60460 */ MCD_OPC_CheckPredicate, 3, 115, 103, 0, // Skip to: 86948 -/* 60465 */ MCD_OPC_Decode, 203, 11, 138, 2, // Opcode: FRECPEv2f64 -/* 60470 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 60485 -/* 60475 */ MCD_OPC_CheckPredicate, 4, 100, 103, 0, // Skip to: 86948 -/* 60480 */ MCD_OPC_Decode, 238, 6, 138, 2, // Opcode: FCMEQv8i16rz -/* 60485 */ MCD_OPC_FilterValue, 57, 90, 103, 0, // Skip to: 86948 -/* 60490 */ MCD_OPC_CheckPredicate, 4, 85, 103, 0, // Skip to: 86948 -/* 60495 */ MCD_OPC_Decode, 206, 11, 138, 2, // Opcode: FRECPEv8f16 -/* 60500 */ MCD_OPC_FilterValue, 3, 75, 103, 0, // Skip to: 86948 -/* 60505 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 60508 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 60636 -/* 60513 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 60516 */ MCD_OPC_FilterValue, 32, 33, 0, 0, // Skip to: 60554 -/* 60521 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 60524 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 60539 -/* 60529 */ MCD_OPC_CheckPredicate, 3, 46, 103, 0, // Skip to: 86948 -/* 60534 */ MCD_OPC_Decode, 254, 6, 138, 2, // Opcode: FCMGEv2i64rz -/* 60539 */ MCD_OPC_FilterValue, 3, 36, 103, 0, // Skip to: 86948 -/* 60544 */ MCD_OPC_CheckPredicate, 3, 31, 103, 0, // Skip to: 86948 -/* 60549 */ MCD_OPC_Decode, 175, 7, 138, 2, // Opcode: FCMLEv2i64rz -/* 60554 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 60576 -/* 60559 */ MCD_OPC_CheckPredicate, 3, 16, 103, 0, // Skip to: 86948 -/* 60564 */ MCD_OPC_CheckField, 11, 2, 3, 9, 103, 0, // Skip to: 86948 -/* 60571 */ MCD_OPC_Decode, 180, 12, 138, 2, // Opcode: FRSQRTEv2f64 -/* 60576 */ MCD_OPC_FilterValue, 56, 33, 0, 0, // Skip to: 60614 -/* 60581 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 60584 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 60599 -/* 60589 */ MCD_OPC_CheckPredicate, 4, 242, 102, 0, // Skip to: 86948 -/* 60594 */ MCD_OPC_Decode, 132, 7, 138, 2, // Opcode: FCMGEv8i16rz -/* 60599 */ MCD_OPC_FilterValue, 3, 232, 102, 0, // Skip to: 86948 -/* 60604 */ MCD_OPC_CheckPredicate, 4, 227, 102, 0, // Skip to: 86948 -/* 60609 */ MCD_OPC_Decode, 178, 7, 138, 2, // Opcode: FCMLEv8i16rz -/* 60614 */ MCD_OPC_FilterValue, 57, 217, 102, 0, // Skip to: 86948 -/* 60619 */ MCD_OPC_CheckPredicate, 4, 212, 102, 0, // Skip to: 86948 -/* 60624 */ MCD_OPC_CheckField, 11, 2, 3, 205, 102, 0, // Skip to: 86948 -/* 60631 */ MCD_OPC_Decode, 183, 12, 138, 2, // Opcode: FRSQRTEv8f16 -/* 60636 */ MCD_OPC_FilterValue, 1, 195, 102, 0, // Skip to: 86948 -/* 60641 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 60644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 60659 -/* 60649 */ MCD_OPC_CheckPredicate, 11, 182, 102, 0, // Skip to: 86948 -/* 60654 */ MCD_OPC_Decode, 161, 7, 169, 2, // Opcode: FCMLAv2f64 -/* 60659 */ MCD_OPC_FilterValue, 1, 172, 102, 0, // Skip to: 86948 -/* 60664 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 60667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 60682 -/* 60672 */ MCD_OPC_CheckPredicate, 3, 159, 102, 0, // Skip to: 86948 -/* 60677 */ MCD_OPC_Decode, 254, 9, 133, 2, // Opcode: FMINNMPv2f64 -/* 60682 */ MCD_OPC_FilterValue, 2, 149, 102, 0, // Skip to: 86948 -/* 60687 */ MCD_OPC_CheckPredicate, 3, 144, 102, 0, // Skip to: 86948 -/* 60692 */ MCD_OPC_Decode, 135, 6, 133, 2, // Opcode: FABDv2f64 -/* 60697 */ MCD_OPC_FilterValue, 7, 134, 102, 0, // Skip to: 86948 -/* 60702 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 60705 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 60771 -/* 60710 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 60713 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 60742 -/* 60718 */ MCD_OPC_CheckPredicate, 5, 113, 102, 0, // Skip to: 86948 -/* 60723 */ MCD_OPC_CheckField, 21, 1, 1, 106, 102, 0, // Skip to: 86948 -/* 60730 */ MCD_OPC_CheckField, 12, 1, 0, 99, 102, 0, // Skip to: 86948 -/* 60737 */ MCD_OPC_Decode, 244, 20, 234, 1, // Opcode: PMULLv1i64 -/* 60742 */ MCD_OPC_FilterValue, 2, 89, 102, 0, // Skip to: 86948 -/* 60747 */ MCD_OPC_CheckPredicate, 5, 84, 102, 0, // Skip to: 86948 -/* 60752 */ MCD_OPC_CheckField, 21, 1, 1, 77, 102, 0, // Skip to: 86948 -/* 60759 */ MCD_OPC_CheckField, 12, 1, 0, 70, 102, 0, // Skip to: 86948 -/* 60766 */ MCD_OPC_Decode, 245, 20, 133, 2, // Opcode: PMULLv2i64 -/* 60771 */ MCD_OPC_FilterValue, 1, 93, 0, 0, // Skip to: 60869 -/* 60776 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 60779 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 60801 -/* 60784 */ MCD_OPC_CheckPredicate, 11, 47, 102, 0, // Skip to: 86948 -/* 60789 */ MCD_OPC_CheckField, 29, 3, 3, 40, 102, 0, // Skip to: 86948 -/* 60796 */ MCD_OPC_Decode, 207, 6, 170, 2, // Opcode: FCADDv2f64 -/* 60801 */ MCD_OPC_FilterValue, 1, 30, 102, 0, // Skip to: 86948 -/* 60806 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 60809 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 60831 -/* 60814 */ MCD_OPC_CheckPredicate, 3, 17, 102, 0, // Skip to: 86948 -/* 60819 */ MCD_OPC_CheckField, 29, 3, 3, 10, 102, 0, // Skip to: 86948 -/* 60826 */ MCD_OPC_Decode, 146, 7, 133, 2, // Opcode: FCMGTv2f64 -/* 60831 */ MCD_OPC_FilterValue, 1, 0, 102, 0, // Skip to: 86948 -/* 60836 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 60839 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60854 -/* 60844 */ MCD_OPC_CheckPredicate, 3, 243, 101, 0, // Skip to: 86948 -/* 60849 */ MCD_OPC_Decode, 173, 10, 133, 2, // Opcode: FMINv2f64 -/* 60854 */ MCD_OPC_FilterValue, 3, 233, 101, 0, // Skip to: 86948 -/* 60859 */ MCD_OPC_CheckPredicate, 3, 228, 101, 0, // Skip to: 86948 -/* 60864 */ MCD_OPC_Decode, 152, 10, 133, 2, // Opcode: FMINPv2f64 -/* 60869 */ MCD_OPC_FilterValue, 2, 24, 1, 0, // Skip to: 61154 -/* 60874 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 60877 */ MCD_OPC_FilterValue, 32, 63, 0, 0, // Skip to: 60945 -/* 60882 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 60885 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 60907 -/* 60890 */ MCD_OPC_CheckPredicate, 3, 197, 101, 0, // Skip to: 86948 -/* 60895 */ MCD_OPC_CheckField, 29, 3, 2, 190, 101, 0, // Skip to: 86948 -/* 60902 */ MCD_OPC_Decode, 186, 7, 138, 2, // Opcode: FCMLTv2i64rz -/* 60907 */ MCD_OPC_FilterValue, 1, 180, 101, 0, // Skip to: 86948 -/* 60912 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 60915 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60930 -/* 60920 */ MCD_OPC_CheckPredicate, 3, 167, 101, 0, // Skip to: 86948 -/* 60925 */ MCD_OPC_Decode, 146, 6, 138, 2, // Opcode: FABSv2f64 -/* 60930 */ MCD_OPC_FilterValue, 3, 157, 101, 0, // Skip to: 86948 -/* 60935 */ MCD_OPC_CheckPredicate, 3, 152, 101, 0, // Skip to: 86948 -/* 60940 */ MCD_OPC_Decode, 171, 11, 138, 2, // Opcode: FNEGv2f64 -/* 60945 */ MCD_OPC_FilterValue, 33, 24, 0, 0, // Skip to: 60974 -/* 60950 */ MCD_OPC_CheckPredicate, 3, 137, 101, 0, // Skip to: 86948 -/* 60955 */ MCD_OPC_CheckField, 29, 3, 3, 130, 101, 0, // Skip to: 86948 -/* 60962 */ MCD_OPC_CheckField, 12, 1, 1, 123, 101, 0, // Skip to: 86948 -/* 60969 */ MCD_OPC_Decode, 205, 12, 138, 2, // Opcode: FSQRTv2f64 -/* 60974 */ MCD_OPC_FilterValue, 56, 123, 0, 0, // Skip to: 61102 -/* 60979 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 60982 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 61020 -/* 60987 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 60990 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61005 -/* 60995 */ MCD_OPC_CheckPredicate, 4, 92, 101, 0, // Skip to: 86948 -/* 61000 */ MCD_OPC_Decode, 187, 7, 239, 1, // Opcode: FCMLTv4i16rz -/* 61005 */ MCD_OPC_FilterValue, 1, 82, 101, 0, // Skip to: 86948 -/* 61010 */ MCD_OPC_CheckPredicate, 4, 77, 101, 0, // Skip to: 86948 -/* 61015 */ MCD_OPC_Decode, 147, 6, 239, 1, // Opcode: FABSv4f16 -/* 61020 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 61042 -/* 61025 */ MCD_OPC_CheckPredicate, 4, 62, 101, 0, // Skip to: 86948 -/* 61030 */ MCD_OPC_CheckField, 12, 1, 1, 55, 101, 0, // Skip to: 86948 -/* 61037 */ MCD_OPC_Decode, 172, 11, 239, 1, // Opcode: FNEGv4f16 -/* 61042 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 61080 -/* 61047 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 61050 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61065 -/* 61055 */ MCD_OPC_CheckPredicate, 4, 32, 101, 0, // Skip to: 86948 -/* 61060 */ MCD_OPC_Decode, 189, 7, 138, 2, // Opcode: FCMLTv8i16rz -/* 61065 */ MCD_OPC_FilterValue, 1, 22, 101, 0, // Skip to: 86948 -/* 61070 */ MCD_OPC_CheckPredicate, 4, 17, 101, 0, // Skip to: 86948 -/* 61075 */ MCD_OPC_Decode, 149, 6, 138, 2, // Opcode: FABSv8f16 -/* 61080 */ MCD_OPC_FilterValue, 3, 7, 101, 0, // Skip to: 86948 -/* 61085 */ MCD_OPC_CheckPredicate, 4, 2, 101, 0, // Skip to: 86948 -/* 61090 */ MCD_OPC_CheckField, 12, 1, 1, 251, 100, 0, // Skip to: 86948 -/* 61097 */ MCD_OPC_Decode, 174, 11, 138, 2, // Opcode: FNEGv8f16 -/* 61102 */ MCD_OPC_FilterValue, 57, 241, 100, 0, // Skip to: 86948 -/* 61107 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 61110 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 61132 -/* 61115 */ MCD_OPC_CheckPredicate, 4, 228, 100, 0, // Skip to: 86948 -/* 61120 */ MCD_OPC_CheckField, 12, 1, 1, 221, 100, 0, // Skip to: 86948 -/* 61127 */ MCD_OPC_Decode, 206, 12, 239, 1, // Opcode: FSQRTv4f16 -/* 61132 */ MCD_OPC_FilterValue, 3, 211, 100, 0, // Skip to: 86948 -/* 61137 */ MCD_OPC_CheckPredicate, 4, 206, 100, 0, // Skip to: 86948 -/* 61142 */ MCD_OPC_CheckField, 12, 1, 1, 199, 100, 0, // Skip to: 86948 -/* 61149 */ MCD_OPC_Decode, 208, 12, 138, 2, // Opcode: FSQRTv8f16 -/* 61154 */ MCD_OPC_FilterValue, 3, 189, 100, 0, // Skip to: 86948 -/* 61159 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 61162 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 61191 -/* 61167 */ MCD_OPC_CheckPredicate, 3, 176, 100, 0, // Skip to: 86948 -/* 61172 */ MCD_OPC_CheckField, 29, 3, 3, 169, 100, 0, // Skip to: 86948 -/* 61179 */ MCD_OPC_CheckField, 21, 1, 1, 162, 100, 0, // Skip to: 86948 -/* 61186 */ MCD_OPC_Decode, 168, 6, 133, 2, // Opcode: FACGTv2f64 -/* 61191 */ MCD_OPC_FilterValue, 1, 152, 100, 0, // Skip to: 86948 -/* 61196 */ MCD_OPC_CheckPredicate, 3, 147, 100, 0, // Skip to: 86948 -/* 61201 */ MCD_OPC_CheckField, 29, 3, 2, 140, 100, 0, // Skip to: 86948 -/* 61208 */ MCD_OPC_CheckField, 21, 1, 1, 133, 100, 0, // Skip to: 86948 -/* 61215 */ MCD_OPC_Decode, 191, 12, 133, 2, // Opcode: FRSQRTSv2f64 -/* 61220 */ MCD_OPC_FilterValue, 12, 94, 17, 0, // Skip to: 65671 -/* 61225 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 61228 */ MCD_OPC_FilterValue, 0, 66, 4, 0, // Skip to: 62323 -/* 61233 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 61236 */ MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 61289 -/* 61241 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 61244 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61259 -/* 61249 */ MCD_OPC_CheckPredicate, 4, 94, 100, 0, // Skip to: 86948 -/* 61254 */ MCD_OPC_Decode, 192, 10, 174, 2, // Opcode: FMLAv4i16_indexed -/* 61259 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 61274 -/* 61264 */ MCD_OPC_CheckPredicate, 4, 79, 100, 0, // Skip to: 86948 -/* 61269 */ MCD_OPC_Decode, 211, 10, 174, 2, // Opcode: FMLSv4i16_indexed -/* 61274 */ MCD_OPC_FilterValue, 9, 69, 100, 0, // Skip to: 86948 -/* 61279 */ MCD_OPC_CheckPredicate, 4, 64, 100, 0, // Skip to: 86948 -/* 61284 */ MCD_OPC_Decode, 160, 11, 175, 2, // Opcode: FMULv4i16_indexed -/* 61289 */ MCD_OPC_FilterValue, 1, 54, 100, 0, // Skip to: 86948 -/* 61294 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 61297 */ MCD_OPC_FilterValue, 0, 41, 3, 0, // Skip to: 62111 -/* 61302 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 61305 */ MCD_OPC_FilterValue, 0, 143, 1, 0, // Skip to: 61709 -/* 61310 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 61313 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 61466 -/* 61318 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 61321 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 61428 -/* 61326 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 61329 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 61390 -/* 61334 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 61337 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61352 -/* 61342 */ MCD_OPC_CheckPredicate, 3, 1, 100, 0, // Skip to: 86948 -/* 61347 */ MCD_OPC_Decode, 236, 19, 176, 2, // Opcode: MOVIv2i32 -/* 61352 */ MCD_OPC_FilterValue, 1, 247, 99, 0, // Skip to: 86948 -/* 61357 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 61360 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61375 -/* 61365 */ MCD_OPC_CheckPredicate, 3, 234, 99, 0, // Skip to: 86948 -/* 61370 */ MCD_OPC_Decode, 242, 26, 177, 2, // Opcode: SSHRv8i8_shift -/* 61375 */ MCD_OPC_FilterValue, 1, 224, 99, 0, // Skip to: 86948 -/* 61380 */ MCD_OPC_CheckPredicate, 3, 219, 99, 0, // Skip to: 86948 -/* 61385 */ MCD_OPC_Decode, 212, 26, 177, 2, // Opcode: SRSHRv8i8_shift -/* 61390 */ MCD_OPC_FilterValue, 1, 209, 99, 0, // Skip to: 86948 -/* 61395 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 61398 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61413 -/* 61403 */ MCD_OPC_CheckPredicate, 3, 196, 99, 0, // Skip to: 86948 -/* 61408 */ MCD_OPC_Decode, 239, 26, 178, 2, // Opcode: SSHRv4i16_shift -/* 61413 */ MCD_OPC_FilterValue, 1, 186, 99, 0, // Skip to: 86948 -/* 61418 */ MCD_OPC_CheckPredicate, 3, 181, 99, 0, // Skip to: 86948 -/* 61423 */ MCD_OPC_Decode, 209, 26, 178, 2, // Opcode: SRSHRv4i16_shift -/* 61428 */ MCD_OPC_FilterValue, 1, 171, 99, 0, // Skip to: 86948 -/* 61433 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 61436 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61451 -/* 61441 */ MCD_OPC_CheckPredicate, 3, 158, 99, 0, // Skip to: 86948 -/* 61446 */ MCD_OPC_Decode, 237, 26, 179, 2, // Opcode: SSHRv2i32_shift -/* 61451 */ MCD_OPC_FilterValue, 1, 148, 99, 0, // Skip to: 86948 -/* 61456 */ MCD_OPC_CheckPredicate, 3, 143, 99, 0, // Skip to: 86948 -/* 61461 */ MCD_OPC_Decode, 207, 26, 179, 2, // Opcode: SRSHRv2i32_shift -/* 61466 */ MCD_OPC_FilterValue, 1, 133, 99, 0, // Skip to: 86948 -/* 61471 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 61474 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 61641 -/* 61479 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 61482 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 61573 -/* 61487 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 61490 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61505 -/* 61495 */ MCD_OPC_CheckPredicate, 3, 104, 99, 0, // Skip to: 86948 -/* 61500 */ MCD_OPC_Decode, 218, 20, 180, 2, // Opcode: ORRv2i32 -/* 61505 */ MCD_OPC_FilterValue, 1, 94, 99, 0, // Skip to: 86948 -/* 61510 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 61513 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61528 -/* 61518 */ MCD_OPC_CheckPredicate, 3, 81, 99, 0, // Skip to: 86948 -/* 61523 */ MCD_OPC_Decode, 250, 26, 181, 2, // Opcode: SSRAv8i8_shift -/* 61528 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61543 -/* 61533 */ MCD_OPC_CheckPredicate, 3, 66, 99, 0, // Skip to: 86948 -/* 61538 */ MCD_OPC_Decode, 220, 26, 181, 2, // Opcode: SRSRAv8i8_shift -/* 61543 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 61558 -/* 61548 */ MCD_OPC_CheckPredicate, 3, 51, 99, 0, // Skip to: 86948 -/* 61553 */ MCD_OPC_Decode, 146, 23, 182, 2, // Opcode: SHLv8i8_shift -/* 61558 */ MCD_OPC_FilterValue, 3, 41, 99, 0, // Skip to: 86948 -/* 61563 */ MCD_OPC_CheckPredicate, 3, 36, 99, 0, // Skip to: 86948 -/* 61568 */ MCD_OPC_Decode, 255, 25, 182, 2, // Opcode: SQSHLv8i8_shift -/* 61573 */ MCD_OPC_FilterValue, 1, 26, 99, 0, // Skip to: 86948 -/* 61578 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 61581 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61596 -/* 61586 */ MCD_OPC_CheckPredicate, 3, 13, 99, 0, // Skip to: 86948 -/* 61591 */ MCD_OPC_Decode, 247, 26, 183, 2, // Opcode: SSRAv4i16_shift -/* 61596 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61611 -/* 61601 */ MCD_OPC_CheckPredicate, 3, 254, 98, 0, // Skip to: 86948 -/* 61606 */ MCD_OPC_Decode, 217, 26, 183, 2, // Opcode: SRSRAv4i16_shift -/* 61611 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 61626 -/* 61616 */ MCD_OPC_CheckPredicate, 3, 239, 98, 0, // Skip to: 86948 -/* 61621 */ MCD_OPC_Decode, 143, 23, 184, 2, // Opcode: SHLv4i16_shift -/* 61626 */ MCD_OPC_FilterValue, 3, 229, 98, 0, // Skip to: 86948 -/* 61631 */ MCD_OPC_CheckPredicate, 3, 224, 98, 0, // Skip to: 86948 -/* 61636 */ MCD_OPC_Decode, 249, 25, 184, 2, // Opcode: SQSHLv4i16_shift -/* 61641 */ MCD_OPC_FilterValue, 1, 214, 98, 0, // Skip to: 86948 -/* 61646 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 61649 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61664 -/* 61654 */ MCD_OPC_CheckPredicate, 3, 201, 98, 0, // Skip to: 86948 -/* 61659 */ MCD_OPC_Decode, 245, 26, 185, 2, // Opcode: SSRAv2i32_shift -/* 61664 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61679 -/* 61669 */ MCD_OPC_CheckPredicate, 3, 186, 98, 0, // Skip to: 86948 -/* 61674 */ MCD_OPC_Decode, 215, 26, 185, 2, // Opcode: SRSRAv2i32_shift -/* 61679 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 61694 -/* 61684 */ MCD_OPC_CheckPredicate, 3, 171, 98, 0, // Skip to: 86948 -/* 61689 */ MCD_OPC_Decode, 141, 23, 186, 2, // Opcode: SHLv2i32_shift -/* 61694 */ MCD_OPC_FilterValue, 3, 161, 98, 0, // Skip to: 86948 -/* 61699 */ MCD_OPC_CheckPredicate, 3, 156, 98, 0, // Skip to: 86948 -/* 61704 */ MCD_OPC_Decode, 245, 25, 186, 2, // Opcode: SQSHLv2i32_shift -/* 61709 */ MCD_OPC_FilterValue, 1, 146, 98, 0, // Skip to: 86948 -/* 61714 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 61717 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 61983 -/* 61722 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 61725 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 61878 -/* 61730 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 61733 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 61840 -/* 61738 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 61741 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 61802 -/* 61746 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 61749 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61764 -/* 61754 */ MCD_OPC_CheckPredicate, 3, 101, 98, 0, // Skip to: 86948 -/* 61759 */ MCD_OPC_Decode, 238, 19, 176, 2, // Opcode: MOVIv4i16 -/* 61764 */ MCD_OPC_FilterValue, 1, 91, 98, 0, // Skip to: 86948 -/* 61769 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 61772 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61787 -/* 61777 */ MCD_OPC_CheckPredicate, 3, 78, 98, 0, // Skip to: 86948 -/* 61782 */ MCD_OPC_Decode, 152, 23, 187, 2, // Opcode: SHRNv8i8_shift -/* 61787 */ MCD_OPC_FilterValue, 1, 68, 98, 0, // Skip to: 86948 -/* 61792 */ MCD_OPC_CheckPredicate, 3, 63, 98, 0, // Skip to: 86948 -/* 61797 */ MCD_OPC_Decode, 226, 26, 188, 2, // Opcode: SSHLLv8i8_shift -/* 61802 */ MCD_OPC_FilterValue, 1, 53, 98, 0, // Skip to: 86948 -/* 61807 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 61810 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61825 -/* 61815 */ MCD_OPC_CheckPredicate, 3, 40, 98, 0, // Skip to: 86948 -/* 61820 */ MCD_OPC_Decode, 149, 23, 189, 2, // Opcode: SHRNv4i16_shift -/* 61825 */ MCD_OPC_FilterValue, 1, 30, 98, 0, // Skip to: 86948 -/* 61830 */ MCD_OPC_CheckPredicate, 3, 25, 98, 0, // Skip to: 86948 -/* 61835 */ MCD_OPC_Decode, 223, 26, 190, 2, // Opcode: SSHLLv4i16_shift -/* 61840 */ MCD_OPC_FilterValue, 1, 15, 98, 0, // Skip to: 86948 -/* 61845 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 61848 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61863 -/* 61853 */ MCD_OPC_CheckPredicate, 3, 2, 98, 0, // Skip to: 86948 -/* 61858 */ MCD_OPC_Decode, 148, 23, 191, 2, // Opcode: SHRNv2i32_shift -/* 61863 */ MCD_OPC_FilterValue, 1, 248, 97, 0, // Skip to: 86948 -/* 61868 */ MCD_OPC_CheckPredicate, 3, 243, 97, 0, // Skip to: 86948 -/* 61873 */ MCD_OPC_Decode, 222, 26, 192, 2, // Opcode: SSHLLv2i32_shift -/* 61878 */ MCD_OPC_FilterValue, 1, 233, 97, 0, // Skip to: 86948 -/* 61883 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 61886 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 61961 -/* 61891 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 61894 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 61939 -/* 61899 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 61902 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61917 -/* 61907 */ MCD_OPC_CheckPredicate, 3, 204, 97, 0, // Skip to: 86948 -/* 61912 */ MCD_OPC_Decode, 219, 20, 180, 2, // Opcode: ORRv4i16 -/* 61917 */ MCD_OPC_FilterValue, 1, 194, 97, 0, // Skip to: 86948 -/* 61922 */ MCD_OPC_CheckPredicate, 3, 189, 97, 0, // Skip to: 86948 -/* 61927 */ MCD_OPC_CheckField, 13, 1, 0, 182, 97, 0, // Skip to: 86948 -/* 61934 */ MCD_OPC_Decode, 136, 26, 187, 2, // Opcode: SQSHRNv8i8_shift -/* 61939 */ MCD_OPC_FilterValue, 1, 172, 97, 0, // Skip to: 86948 -/* 61944 */ MCD_OPC_CheckPredicate, 3, 167, 97, 0, // Skip to: 86948 -/* 61949 */ MCD_OPC_CheckField, 13, 1, 0, 160, 97, 0, // Skip to: 86948 -/* 61956 */ MCD_OPC_Decode, 133, 26, 189, 2, // Opcode: SQSHRNv4i16_shift -/* 61961 */ MCD_OPC_FilterValue, 1, 150, 97, 0, // Skip to: 86948 -/* 61966 */ MCD_OPC_CheckPredicate, 3, 145, 97, 0, // Skip to: 86948 -/* 61971 */ MCD_OPC_CheckField, 13, 1, 0, 138, 97, 0, // Skip to: 86948 -/* 61978 */ MCD_OPC_Decode, 132, 26, 191, 2, // Opcode: SQSHRNv2i32_shift -/* 61983 */ MCD_OPC_FilterValue, 1, 128, 97, 0, // Skip to: 86948 -/* 61988 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 61991 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62013 -/* 61996 */ MCD_OPC_CheckPredicate, 3, 115, 97, 0, // Skip to: 86948 -/* 62001 */ MCD_OPC_CheckField, 19, 3, 0, 108, 97, 0, // Skip to: 86948 -/* 62008 */ MCD_OPC_Decode, 237, 19, 176, 2, // Opcode: MOVIv2s_msl -/* 62013 */ MCD_OPC_FilterValue, 1, 98, 97, 0, // Skip to: 86948 -/* 62018 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 62021 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 62089 -/* 62026 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 62029 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62074 -/* 62034 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 62037 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62059 -/* 62042 */ MCD_OPC_CheckPredicate, 3, 69, 97, 0, // Skip to: 86948 -/* 62047 */ MCD_OPC_CheckField, 19, 1, 0, 62, 97, 0, // Skip to: 86948 -/* 62054 */ MCD_OPC_Decode, 241, 19, 176, 2, // Opcode: MOVIv8b_ns -/* 62059 */ MCD_OPC_FilterValue, 1, 52, 97, 0, // Skip to: 86948 -/* 62064 */ MCD_OPC_CheckPredicate, 4, 47, 97, 0, // Skip to: 86948 -/* 62069 */ MCD_OPC_Decode, 215, 22, 178, 2, // Opcode: SCVTFv4i16_shift -/* 62074 */ MCD_OPC_FilterValue, 1, 37, 97, 0, // Skip to: 86948 -/* 62079 */ MCD_OPC_CheckPredicate, 3, 32, 97, 0, // Skip to: 86948 -/* 62084 */ MCD_OPC_Decode, 211, 22, 179, 2, // Opcode: SCVTFv2i32_shift -/* 62089 */ MCD_OPC_FilterValue, 1, 22, 97, 0, // Skip to: 86948 -/* 62094 */ MCD_OPC_CheckPredicate, 3, 17, 97, 0, // Skip to: 86948 -/* 62099 */ MCD_OPC_CheckField, 19, 3, 0, 10, 97, 0, // Skip to: 86948 -/* 62106 */ MCD_OPC_Decode, 234, 10, 176, 2, // Opcode: FMOVv2f32_ns -/* 62111 */ MCD_OPC_FilterValue, 1, 0, 97, 0, // Skip to: 86948 -/* 62116 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 62119 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 62187 -/* 62124 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 62127 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62172 -/* 62132 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 62135 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62157 -/* 62140 */ MCD_OPC_CheckPredicate, 3, 227, 96, 0, // Skip to: 86948 -/* 62145 */ MCD_OPC_CheckField, 19, 1, 1, 220, 96, 0, // Skip to: 86948 -/* 62152 */ MCD_OPC_Decode, 239, 21, 187, 2, // Opcode: RSHRNv8i8_shift -/* 62157 */ MCD_OPC_FilterValue, 1, 210, 96, 0, // Skip to: 86948 -/* 62162 */ MCD_OPC_CheckPredicate, 3, 205, 96, 0, // Skip to: 86948 -/* 62167 */ MCD_OPC_Decode, 236, 21, 189, 2, // Opcode: RSHRNv4i16_shift -/* 62172 */ MCD_OPC_FilterValue, 1, 195, 96, 0, // Skip to: 86948 -/* 62177 */ MCD_OPC_CheckPredicate, 3, 190, 96, 0, // Skip to: 86948 -/* 62182 */ MCD_OPC_Decode, 235, 21, 191, 2, // Opcode: RSHRNv2i32_shift -/* 62187 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 62255 -/* 62192 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 62195 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62240 -/* 62200 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 62203 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62225 -/* 62208 */ MCD_OPC_CheckPredicate, 3, 159, 96, 0, // Skip to: 86948 -/* 62213 */ MCD_OPC_CheckField, 19, 1, 1, 152, 96, 0, // Skip to: 86948 -/* 62220 */ MCD_OPC_Decode, 213, 25, 187, 2, // Opcode: SQRSHRNv8i8_shift -/* 62225 */ MCD_OPC_FilterValue, 1, 142, 96, 0, // Skip to: 86948 -/* 62230 */ MCD_OPC_CheckPredicate, 3, 137, 96, 0, // Skip to: 86948 -/* 62235 */ MCD_OPC_Decode, 210, 25, 189, 2, // Opcode: SQRSHRNv4i16_shift -/* 62240 */ MCD_OPC_FilterValue, 1, 127, 96, 0, // Skip to: 86948 -/* 62245 */ MCD_OPC_CheckPredicate, 3, 122, 96, 0, // Skip to: 86948 -/* 62250 */ MCD_OPC_Decode, 209, 25, 191, 2, // Opcode: SQRSHRNv2i32_shift -/* 62255 */ MCD_OPC_FilterValue, 15, 112, 96, 0, // Skip to: 86948 -/* 62260 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 62263 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62308 -/* 62268 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 62271 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62293 -/* 62276 */ MCD_OPC_CheckPredicate, 4, 91, 96, 0, // Skip to: 86948 -/* 62281 */ MCD_OPC_CheckField, 19, 1, 0, 84, 96, 0, // Skip to: 86948 -/* 62288 */ MCD_OPC_Decode, 236, 10, 176, 2, // Opcode: FMOVv4f16_ns -/* 62293 */ MCD_OPC_FilterValue, 1, 74, 96, 0, // Skip to: 86948 -/* 62298 */ MCD_OPC_CheckPredicate, 4, 69, 96, 0, // Skip to: 86948 -/* 62303 */ MCD_OPC_Decode, 249, 8, 178, 2, // Opcode: FCVTZSv4i16_shift -/* 62308 */ MCD_OPC_FilterValue, 1, 59, 96, 0, // Skip to: 86948 -/* 62313 */ MCD_OPC_CheckPredicate, 3, 54, 96, 0, // Skip to: 86948 -/* 62318 */ MCD_OPC_Decode, 245, 8, 179, 2, // Opcode: FCVTZSv2i32_shift -/* 62323 */ MCD_OPC_FilterValue, 1, 93, 4, 0, // Skip to: 63445 -/* 62328 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 62331 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62353 -/* 62336 */ MCD_OPC_CheckPredicate, 4, 31, 96, 0, // Skip to: 86948 -/* 62341 */ MCD_OPC_CheckField, 12, 4, 9, 24, 96, 0, // Skip to: 86948 -/* 62348 */ MCD_OPC_Decode, 135, 11, 175, 2, // Opcode: FMULXv4i16_indexed -/* 62353 */ MCD_OPC_FilterValue, 1, 14, 96, 0, // Skip to: 86948 -/* 62358 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 62361 */ MCD_OPC_FilterValue, 0, 122, 3, 0, // Skip to: 63256 -/* 62366 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 62369 */ MCD_OPC_FilterValue, 0, 233, 1, 0, // Skip to: 62863 -/* 62374 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 62377 */ MCD_OPC_FilterValue, 0, 238, 0, 0, // Skip to: 62620 -/* 62382 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 62385 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 62552 -/* 62390 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 62393 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 62484 -/* 62398 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 62401 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62416 -/* 62406 */ MCD_OPC_CheckPredicate, 3, 217, 95, 0, // Skip to: 86948 -/* 62411 */ MCD_OPC_Decode, 167, 20, 176, 2, // Opcode: MVNIv2i32 -/* 62416 */ MCD_OPC_FilterValue, 1, 207, 95, 0, // Skip to: 86948 -/* 62421 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 62424 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62439 -/* 62429 */ MCD_OPC_CheckPredicate, 3, 194, 95, 0, // Skip to: 86948 -/* 62434 */ MCD_OPC_Decode, 144, 34, 177, 2, // Opcode: USHRv8i8_shift -/* 62439 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62454 -/* 62444 */ MCD_OPC_CheckPredicate, 3, 179, 95, 0, // Skip to: 86948 -/* 62449 */ MCD_OPC_Decode, 240, 33, 177, 2, // Opcode: URSHRv8i8_shift -/* 62454 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62469 -/* 62459 */ MCD_OPC_CheckPredicate, 3, 164, 95, 0, // Skip to: 86948 -/* 62464 */ MCD_OPC_Decode, 196, 26, 181, 2, // Opcode: SRIv8i8_shift -/* 62469 */ MCD_OPC_FilterValue, 3, 154, 95, 0, // Skip to: 86948 -/* 62474 */ MCD_OPC_CheckPredicate, 3, 149, 95, 0, // Skip to: 86948 -/* 62479 */ MCD_OPC_Decode, 233, 25, 182, 2, // Opcode: SQSHLUv8i8_shift -/* 62484 */ MCD_OPC_FilterValue, 1, 139, 95, 0, // Skip to: 86948 -/* 62489 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 62492 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62507 -/* 62497 */ MCD_OPC_CheckPredicate, 3, 126, 95, 0, // Skip to: 86948 -/* 62502 */ MCD_OPC_Decode, 141, 34, 178, 2, // Opcode: USHRv4i16_shift -/* 62507 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62522 -/* 62512 */ MCD_OPC_CheckPredicate, 3, 111, 95, 0, // Skip to: 86948 -/* 62517 */ MCD_OPC_Decode, 237, 33, 178, 2, // Opcode: URSHRv4i16_shift -/* 62522 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62537 -/* 62527 */ MCD_OPC_CheckPredicate, 3, 96, 95, 0, // Skip to: 86948 -/* 62532 */ MCD_OPC_Decode, 193, 26, 183, 2, // Opcode: SRIv4i16_shift -/* 62537 */ MCD_OPC_FilterValue, 3, 86, 95, 0, // Skip to: 86948 -/* 62542 */ MCD_OPC_CheckPredicate, 3, 81, 95, 0, // Skip to: 86948 -/* 62547 */ MCD_OPC_Decode, 230, 25, 184, 2, // Opcode: SQSHLUv4i16_shift -/* 62552 */ MCD_OPC_FilterValue, 1, 71, 95, 0, // Skip to: 86948 -/* 62557 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 62560 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62575 -/* 62565 */ MCD_OPC_CheckPredicate, 3, 58, 95, 0, // Skip to: 86948 -/* 62570 */ MCD_OPC_Decode, 139, 34, 179, 2, // Opcode: USHRv2i32_shift -/* 62575 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62590 -/* 62580 */ MCD_OPC_CheckPredicate, 3, 43, 95, 0, // Skip to: 86948 -/* 62585 */ MCD_OPC_Decode, 235, 33, 179, 2, // Opcode: URSHRv2i32_shift -/* 62590 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62605 -/* 62595 */ MCD_OPC_CheckPredicate, 3, 28, 95, 0, // Skip to: 86948 -/* 62600 */ MCD_OPC_Decode, 191, 26, 185, 2, // Opcode: SRIv2i32_shift -/* 62605 */ MCD_OPC_FilterValue, 3, 18, 95, 0, // Skip to: 86948 -/* 62610 */ MCD_OPC_CheckPredicate, 3, 13, 95, 0, // Skip to: 86948 -/* 62615 */ MCD_OPC_Decode, 228, 25, 186, 2, // Opcode: SQSHLUv2i32_shift -/* 62620 */ MCD_OPC_FilterValue, 1, 3, 95, 0, // Skip to: 86948 -/* 62625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 62628 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 62795 -/* 62633 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 62636 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 62727 -/* 62641 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 62644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62659 -/* 62649 */ MCD_OPC_CheckPredicate, 3, 230, 94, 0, // Skip to: 86948 -/* 62654 */ MCD_OPC_Decode, 188, 2, 180, 2, // Opcode: BICv2i32 -/* 62659 */ MCD_OPC_FilterValue, 1, 220, 94, 0, // Skip to: 86948 -/* 62664 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 62667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62682 -/* 62672 */ MCD_OPC_CheckPredicate, 3, 207, 94, 0, // Skip to: 86948 -/* 62677 */ MCD_OPC_Decode, 163, 34, 181, 2, // Opcode: USRAv8i8_shift -/* 62682 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62697 -/* 62687 */ MCD_OPC_CheckPredicate, 3, 192, 94, 0, // Skip to: 86948 -/* 62692 */ MCD_OPC_Decode, 250, 33, 181, 2, // Opcode: URSRAv8i8_shift -/* 62697 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62712 -/* 62702 */ MCD_OPC_CheckPredicate, 3, 177, 94, 0, // Skip to: 86948 -/* 62707 */ MCD_OPC_Decode, 166, 23, 193, 2, // Opcode: SLIv8i8_shift -/* 62712 */ MCD_OPC_FilterValue, 3, 167, 94, 0, // Skip to: 86948 -/* 62717 */ MCD_OPC_CheckPredicate, 3, 162, 94, 0, // Skip to: 86948 -/* 62722 */ MCD_OPC_Decode, 179, 33, 182, 2, // Opcode: UQSHLv8i8_shift -/* 62727 */ MCD_OPC_FilterValue, 1, 152, 94, 0, // Skip to: 86948 -/* 62732 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 62735 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62750 -/* 62740 */ MCD_OPC_CheckPredicate, 3, 139, 94, 0, // Skip to: 86948 -/* 62745 */ MCD_OPC_Decode, 160, 34, 183, 2, // Opcode: USRAv4i16_shift -/* 62750 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62765 -/* 62755 */ MCD_OPC_CheckPredicate, 3, 124, 94, 0, // Skip to: 86948 -/* 62760 */ MCD_OPC_Decode, 247, 33, 183, 2, // Opcode: URSRAv4i16_shift -/* 62765 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62780 -/* 62770 */ MCD_OPC_CheckPredicate, 3, 109, 94, 0, // Skip to: 86948 -/* 62775 */ MCD_OPC_Decode, 163, 23, 194, 2, // Opcode: SLIv4i16_shift -/* 62780 */ MCD_OPC_FilterValue, 3, 99, 94, 0, // Skip to: 86948 -/* 62785 */ MCD_OPC_CheckPredicate, 3, 94, 94, 0, // Skip to: 86948 -/* 62790 */ MCD_OPC_Decode, 173, 33, 184, 2, // Opcode: UQSHLv4i16_shift -/* 62795 */ MCD_OPC_FilterValue, 1, 84, 94, 0, // Skip to: 86948 -/* 62800 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 62803 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62818 -/* 62808 */ MCD_OPC_CheckPredicate, 3, 71, 94, 0, // Skip to: 86948 -/* 62813 */ MCD_OPC_Decode, 158, 34, 185, 2, // Opcode: USRAv2i32_shift -/* 62818 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62833 -/* 62823 */ MCD_OPC_CheckPredicate, 3, 56, 94, 0, // Skip to: 86948 -/* 62828 */ MCD_OPC_Decode, 245, 33, 185, 2, // Opcode: URSRAv2i32_shift -/* 62833 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62848 -/* 62838 */ MCD_OPC_CheckPredicate, 3, 41, 94, 0, // Skip to: 86948 -/* 62843 */ MCD_OPC_Decode, 161, 23, 195, 2, // Opcode: SLIv2i32_shift -/* 62848 */ MCD_OPC_FilterValue, 3, 31, 94, 0, // Skip to: 86948 -/* 62853 */ MCD_OPC_CheckPredicate, 3, 26, 94, 0, // Skip to: 86948 -/* 62858 */ MCD_OPC_Decode, 169, 33, 186, 2, // Opcode: UQSHLv2i32_shift -/* 62863 */ MCD_OPC_FilterValue, 1, 16, 94, 0, // Skip to: 86948 -/* 62868 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 62871 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 63137 -/* 62876 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 62879 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 63032 -/* 62884 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 62887 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 62994 -/* 62892 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 62895 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 62956 -/* 62900 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 62903 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62918 -/* 62908 */ MCD_OPC_CheckPredicate, 3, 227, 93, 0, // Skip to: 86948 -/* 62913 */ MCD_OPC_Decode, 169, 20, 176, 2, // Opcode: MVNIv4i16 -/* 62918 */ MCD_OPC_FilterValue, 1, 217, 93, 0, // Skip to: 86948 -/* 62923 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 62926 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62941 -/* 62931 */ MCD_OPC_CheckPredicate, 3, 204, 93, 0, // Skip to: 86948 -/* 62936 */ MCD_OPC_Decode, 145, 26, 187, 2, // Opcode: SQSHRUNv8i8_shift -/* 62941 */ MCD_OPC_FilterValue, 1, 194, 93, 0, // Skip to: 86948 -/* 62946 */ MCD_OPC_CheckPredicate, 3, 189, 93, 0, // Skip to: 86948 -/* 62951 */ MCD_OPC_Decode, 128, 34, 188, 2, // Opcode: USHLLv8i8_shift -/* 62956 */ MCD_OPC_FilterValue, 1, 179, 93, 0, // Skip to: 86948 -/* 62961 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 62964 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62979 -/* 62969 */ MCD_OPC_CheckPredicate, 3, 166, 93, 0, // Skip to: 86948 -/* 62974 */ MCD_OPC_Decode, 142, 26, 189, 2, // Opcode: SQSHRUNv4i16_shift -/* 62979 */ MCD_OPC_FilterValue, 1, 156, 93, 0, // Skip to: 86948 -/* 62984 */ MCD_OPC_CheckPredicate, 3, 151, 93, 0, // Skip to: 86948 -/* 62989 */ MCD_OPC_Decode, 253, 33, 190, 2, // Opcode: USHLLv4i16_shift -/* 62994 */ MCD_OPC_FilterValue, 1, 141, 93, 0, // Skip to: 86948 -/* 62999 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 63002 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63017 -/* 63007 */ MCD_OPC_CheckPredicate, 3, 128, 93, 0, // Skip to: 86948 -/* 63012 */ MCD_OPC_Decode, 141, 26, 191, 2, // Opcode: SQSHRUNv2i32_shift -/* 63017 */ MCD_OPC_FilterValue, 1, 118, 93, 0, // Skip to: 86948 -/* 63022 */ MCD_OPC_CheckPredicate, 3, 113, 93, 0, // Skip to: 86948 -/* 63027 */ MCD_OPC_Decode, 252, 33, 192, 2, // Opcode: USHLLv2i32_shift -/* 63032 */ MCD_OPC_FilterValue, 1, 103, 93, 0, // Skip to: 86948 -/* 63037 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 63040 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 63115 -/* 63045 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 63048 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 63093 -/* 63053 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 63056 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63071 -/* 63061 */ MCD_OPC_CheckPredicate, 3, 74, 93, 0, // Skip to: 86948 -/* 63066 */ MCD_OPC_Decode, 189, 2, 180, 2, // Opcode: BICv4i16 -/* 63071 */ MCD_OPC_FilterValue, 1, 64, 93, 0, // Skip to: 86948 -/* 63076 */ MCD_OPC_CheckPredicate, 3, 59, 93, 0, // Skip to: 86948 -/* 63081 */ MCD_OPC_CheckField, 13, 1, 0, 52, 93, 0, // Skip to: 86948 -/* 63088 */ MCD_OPC_Decode, 188, 33, 187, 2, // Opcode: UQSHRNv8i8_shift -/* 63093 */ MCD_OPC_FilterValue, 1, 42, 93, 0, // Skip to: 86948 -/* 63098 */ MCD_OPC_CheckPredicate, 3, 37, 93, 0, // Skip to: 86948 -/* 63103 */ MCD_OPC_CheckField, 13, 1, 0, 30, 93, 0, // Skip to: 86948 -/* 63110 */ MCD_OPC_Decode, 185, 33, 189, 2, // Opcode: UQSHRNv4i16_shift -/* 63115 */ MCD_OPC_FilterValue, 1, 20, 93, 0, // Skip to: 86948 -/* 63120 */ MCD_OPC_CheckPredicate, 3, 15, 93, 0, // Skip to: 86948 -/* 63125 */ MCD_OPC_CheckField, 13, 1, 0, 8, 93, 0, // Skip to: 86948 -/* 63132 */ MCD_OPC_Decode, 184, 33, 191, 2, // Opcode: UQSHRNv2i32_shift -/* 63137 */ MCD_OPC_FilterValue, 1, 254, 92, 0, // Skip to: 86948 -/* 63142 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 63145 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63167 -/* 63150 */ MCD_OPC_CheckPredicate, 3, 241, 92, 0, // Skip to: 86948 -/* 63155 */ MCD_OPC_CheckField, 19, 3, 0, 234, 92, 0, // Skip to: 86948 -/* 63162 */ MCD_OPC_Decode, 168, 20, 176, 2, // Opcode: MVNIv2s_msl -/* 63167 */ MCD_OPC_FilterValue, 1, 224, 92, 0, // Skip to: 86948 -/* 63172 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 63175 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 63234 -/* 63180 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 63183 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 63212 -/* 63188 */ MCD_OPC_CheckPredicate, 3, 203, 92, 0, // Skip to: 86948 -/* 63193 */ MCD_OPC_CheckField, 19, 1, 0, 196, 92, 0, // Skip to: 86948 -/* 63200 */ MCD_OPC_CheckField, 12, 1, 0, 189, 92, 0, // Skip to: 86948 -/* 63207 */ MCD_OPC_Decode, 233, 19, 176, 2, // Opcode: MOVID -/* 63212 */ MCD_OPC_FilterValue, 1, 179, 92, 0, // Skip to: 86948 -/* 63217 */ MCD_OPC_CheckPredicate, 4, 174, 92, 0, // Skip to: 86948 -/* 63222 */ MCD_OPC_CheckField, 12, 1, 0, 167, 92, 0, // Skip to: 86948 -/* 63229 */ MCD_OPC_Decode, 202, 31, 178, 2, // Opcode: UCVTFv4i16_shift -/* 63234 */ MCD_OPC_FilterValue, 1, 157, 92, 0, // Skip to: 86948 -/* 63239 */ MCD_OPC_CheckPredicate, 3, 152, 92, 0, // Skip to: 86948 -/* 63244 */ MCD_OPC_CheckField, 12, 1, 0, 145, 92, 0, // Skip to: 86948 -/* 63251 */ MCD_OPC_Decode, 198, 31, 179, 2, // Opcode: UCVTFv2i32_shift -/* 63256 */ MCD_OPC_FilterValue, 1, 135, 92, 0, // Skip to: 86948 -/* 63261 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 63264 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 63332 -/* 63269 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 63272 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 63317 -/* 63277 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 63280 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63302 -/* 63285 */ MCD_OPC_CheckPredicate, 3, 106, 92, 0, // Skip to: 86948 -/* 63290 */ MCD_OPC_CheckField, 19, 1, 1, 99, 92, 0, // Skip to: 86948 -/* 63297 */ MCD_OPC_Decode, 222, 25, 187, 2, // Opcode: SQRSHRUNv8i8_shift -/* 63302 */ MCD_OPC_FilterValue, 1, 89, 92, 0, // Skip to: 86948 -/* 63307 */ MCD_OPC_CheckPredicate, 3, 84, 92, 0, // Skip to: 86948 -/* 63312 */ MCD_OPC_Decode, 219, 25, 189, 2, // Opcode: SQRSHRUNv4i16_shift -/* 63317 */ MCD_OPC_FilterValue, 1, 74, 92, 0, // Skip to: 86948 -/* 63322 */ MCD_OPC_CheckPredicate, 3, 69, 92, 0, // Skip to: 86948 -/* 63327 */ MCD_OPC_Decode, 218, 25, 191, 2, // Opcode: SQRSHRUNv2i32_shift -/* 63332 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 63400 -/* 63337 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 63340 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 63385 -/* 63345 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 63348 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63370 -/* 63353 */ MCD_OPC_CheckPredicate, 3, 38, 92, 0, // Skip to: 86948 -/* 63358 */ MCD_OPC_CheckField, 19, 1, 1, 31, 92, 0, // Skip to: 86948 -/* 63365 */ MCD_OPC_Decode, 157, 33, 187, 2, // Opcode: UQRSHRNv8i8_shift -/* 63370 */ MCD_OPC_FilterValue, 1, 21, 92, 0, // Skip to: 86948 -/* 63375 */ MCD_OPC_CheckPredicate, 3, 16, 92, 0, // Skip to: 86948 -/* 63380 */ MCD_OPC_Decode, 154, 33, 189, 2, // Opcode: UQRSHRNv4i16_shift -/* 63385 */ MCD_OPC_FilterValue, 1, 6, 92, 0, // Skip to: 86948 -/* 63390 */ MCD_OPC_CheckPredicate, 3, 1, 92, 0, // Skip to: 86948 -/* 63395 */ MCD_OPC_Decode, 153, 33, 191, 2, // Opcode: UQRSHRNv2i32_shift -/* 63400 */ MCD_OPC_FilterValue, 15, 247, 91, 0, // Skip to: 86948 -/* 63405 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 63408 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63430 -/* 63413 */ MCD_OPC_CheckPredicate, 4, 234, 91, 0, // Skip to: 86948 -/* 63418 */ MCD_OPC_CheckField, 20, 1, 1, 227, 91, 0, // Skip to: 86948 -/* 63425 */ MCD_OPC_Decode, 156, 9, 178, 2, // Opcode: FCVTZUv4i16_shift -/* 63430 */ MCD_OPC_FilterValue, 1, 217, 91, 0, // Skip to: 86948 -/* 63435 */ MCD_OPC_CheckPredicate, 3, 212, 91, 0, // Skip to: 86948 -/* 63440 */ MCD_OPC_Decode, 152, 9, 179, 2, // Opcode: FCVTZUv2i32_shift -/* 63445 */ MCD_OPC_FilterValue, 2, 66, 4, 0, // Skip to: 64540 -/* 63450 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 63453 */ MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 63506 -/* 63458 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 63461 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63476 -/* 63466 */ MCD_OPC_CheckPredicate, 4, 181, 91, 0, // Skip to: 86948 -/* 63471 */ MCD_OPC_Decode, 195, 10, 196, 2, // Opcode: FMLAv8i16_indexed -/* 63476 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 63491 -/* 63481 */ MCD_OPC_CheckPredicate, 4, 166, 91, 0, // Skip to: 86948 -/* 63486 */ MCD_OPC_Decode, 214, 10, 196, 2, // Opcode: FMLSv8i16_indexed -/* 63491 */ MCD_OPC_FilterValue, 9, 156, 91, 0, // Skip to: 86948 -/* 63496 */ MCD_OPC_CheckPredicate, 4, 151, 91, 0, // Skip to: 86948 -/* 63501 */ MCD_OPC_Decode, 163, 11, 197, 2, // Opcode: FMULv8i16_indexed -/* 63506 */ MCD_OPC_FilterValue, 1, 141, 91, 0, // Skip to: 86948 -/* 63511 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 63514 */ MCD_OPC_FilterValue, 0, 41, 3, 0, // Skip to: 64328 -/* 63519 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 63522 */ MCD_OPC_FilterValue, 0, 143, 1, 0, // Skip to: 63926 -/* 63527 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 63530 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 63683 -/* 63535 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 63538 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 63645 -/* 63543 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 63546 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 63607 -/* 63551 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 63554 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63569 -/* 63559 */ MCD_OPC_CheckPredicate, 3, 88, 91, 0, // Skip to: 86948 -/* 63564 */ MCD_OPC_Decode, 239, 19, 176, 2, // Opcode: MOVIv4i32 -/* 63569 */ MCD_OPC_FilterValue, 1, 78, 91, 0, // Skip to: 86948 -/* 63574 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 63577 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63592 -/* 63582 */ MCD_OPC_CheckPredicate, 3, 65, 91, 0, // Skip to: 86948 -/* 63587 */ MCD_OPC_Decode, 236, 26, 198, 2, // Opcode: SSHRv16i8_shift -/* 63592 */ MCD_OPC_FilterValue, 1, 55, 91, 0, // Skip to: 86948 -/* 63597 */ MCD_OPC_CheckPredicate, 3, 50, 91, 0, // Skip to: 86948 -/* 63602 */ MCD_OPC_Decode, 206, 26, 198, 2, // Opcode: SRSHRv16i8_shift -/* 63607 */ MCD_OPC_FilterValue, 1, 40, 91, 0, // Skip to: 86948 -/* 63612 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 63615 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63630 -/* 63620 */ MCD_OPC_CheckPredicate, 3, 27, 91, 0, // Skip to: 86948 -/* 63625 */ MCD_OPC_Decode, 241, 26, 199, 2, // Opcode: SSHRv8i16_shift -/* 63630 */ MCD_OPC_FilterValue, 1, 17, 91, 0, // Skip to: 86948 -/* 63635 */ MCD_OPC_CheckPredicate, 3, 12, 91, 0, // Skip to: 86948 -/* 63640 */ MCD_OPC_Decode, 211, 26, 199, 2, // Opcode: SRSHRv8i16_shift -/* 63645 */ MCD_OPC_FilterValue, 1, 2, 91, 0, // Skip to: 86948 -/* 63650 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 63653 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63668 -/* 63658 */ MCD_OPC_CheckPredicate, 3, 245, 90, 0, // Skip to: 86948 -/* 63663 */ MCD_OPC_Decode, 240, 26, 200, 2, // Opcode: SSHRv4i32_shift -/* 63668 */ MCD_OPC_FilterValue, 1, 235, 90, 0, // Skip to: 86948 -/* 63673 */ MCD_OPC_CheckPredicate, 3, 230, 90, 0, // Skip to: 86948 -/* 63678 */ MCD_OPC_Decode, 210, 26, 200, 2, // Opcode: SRSHRv4i32_shift -/* 63683 */ MCD_OPC_FilterValue, 1, 220, 90, 0, // Skip to: 86948 -/* 63688 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 63691 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 63858 -/* 63696 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 63699 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 63790 -/* 63704 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 63707 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63722 -/* 63712 */ MCD_OPC_CheckPredicate, 3, 191, 90, 0, // Skip to: 86948 -/* 63717 */ MCD_OPC_Decode, 220, 20, 180, 2, // Opcode: ORRv4i32 -/* 63722 */ MCD_OPC_FilterValue, 1, 181, 90, 0, // Skip to: 86948 -/* 63727 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 63730 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63745 -/* 63735 */ MCD_OPC_CheckPredicate, 3, 168, 90, 0, // Skip to: 86948 -/* 63740 */ MCD_OPC_Decode, 244, 26, 201, 2, // Opcode: SSRAv16i8_shift -/* 63745 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63760 -/* 63750 */ MCD_OPC_CheckPredicate, 3, 153, 90, 0, // Skip to: 86948 -/* 63755 */ MCD_OPC_Decode, 214, 26, 201, 2, // Opcode: SRSRAv16i8_shift -/* 63760 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 63775 -/* 63765 */ MCD_OPC_CheckPredicate, 3, 138, 90, 0, // Skip to: 86948 -/* 63770 */ MCD_OPC_Decode, 140, 23, 202, 2, // Opcode: SHLv16i8_shift -/* 63775 */ MCD_OPC_FilterValue, 3, 128, 90, 0, // Skip to: 86948 -/* 63780 */ MCD_OPC_CheckPredicate, 3, 123, 90, 0, // Skip to: 86948 -/* 63785 */ MCD_OPC_Decode, 239, 25, 202, 2, // Opcode: SQSHLv16i8_shift -/* 63790 */ MCD_OPC_FilterValue, 1, 113, 90, 0, // Skip to: 86948 -/* 63795 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 63798 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63813 -/* 63803 */ MCD_OPC_CheckPredicate, 3, 100, 90, 0, // Skip to: 86948 -/* 63808 */ MCD_OPC_Decode, 249, 26, 203, 2, // Opcode: SSRAv8i16_shift -/* 63813 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63828 -/* 63818 */ MCD_OPC_CheckPredicate, 3, 85, 90, 0, // Skip to: 86948 -/* 63823 */ MCD_OPC_Decode, 219, 26, 203, 2, // Opcode: SRSRAv8i16_shift -/* 63828 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 63843 -/* 63833 */ MCD_OPC_CheckPredicate, 3, 70, 90, 0, // Skip to: 86948 -/* 63838 */ MCD_OPC_Decode, 145, 23, 204, 2, // Opcode: SHLv8i16_shift -/* 63843 */ MCD_OPC_FilterValue, 3, 60, 90, 0, // Skip to: 86948 -/* 63848 */ MCD_OPC_CheckPredicate, 3, 55, 90, 0, // Skip to: 86948 -/* 63853 */ MCD_OPC_Decode, 253, 25, 204, 2, // Opcode: SQSHLv8i16_shift -/* 63858 */ MCD_OPC_FilterValue, 1, 45, 90, 0, // Skip to: 86948 -/* 63863 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 63866 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63881 -/* 63871 */ MCD_OPC_CheckPredicate, 3, 32, 90, 0, // Skip to: 86948 -/* 63876 */ MCD_OPC_Decode, 248, 26, 205, 2, // Opcode: SSRAv4i32_shift -/* 63881 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63896 -/* 63886 */ MCD_OPC_CheckPredicate, 3, 17, 90, 0, // Skip to: 86948 -/* 63891 */ MCD_OPC_Decode, 218, 26, 205, 2, // Opcode: SRSRAv4i32_shift -/* 63896 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 63911 -/* 63901 */ MCD_OPC_CheckPredicate, 3, 2, 90, 0, // Skip to: 86948 -/* 63906 */ MCD_OPC_Decode, 144, 23, 206, 2, // Opcode: SHLv4i32_shift -/* 63911 */ MCD_OPC_FilterValue, 3, 248, 89, 0, // Skip to: 86948 -/* 63916 */ MCD_OPC_CheckPredicate, 3, 243, 89, 0, // Skip to: 86948 -/* 63921 */ MCD_OPC_Decode, 251, 25, 206, 2, // Opcode: SQSHLv4i32_shift -/* 63926 */ MCD_OPC_FilterValue, 1, 233, 89, 0, // Skip to: 86948 -/* 63931 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 63934 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 64200 -/* 63939 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 63942 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 64095 -/* 63947 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 63950 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 64057 -/* 63955 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 63958 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 64019 -/* 63963 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 63966 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63981 -/* 63971 */ MCD_OPC_CheckPredicate, 3, 188, 89, 0, // Skip to: 86948 -/* 63976 */ MCD_OPC_Decode, 242, 19, 176, 2, // Opcode: MOVIv8i16 -/* 63981 */ MCD_OPC_FilterValue, 1, 178, 89, 0, // Skip to: 86948 -/* 63986 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 63989 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64004 -/* 63994 */ MCD_OPC_CheckPredicate, 3, 165, 89, 0, // Skip to: 86948 -/* 63999 */ MCD_OPC_Decode, 147, 23, 207, 2, // Opcode: SHRNv16i8_shift -/* 64004 */ MCD_OPC_FilterValue, 1, 155, 89, 0, // Skip to: 86948 -/* 64009 */ MCD_OPC_CheckPredicate, 3, 150, 89, 0, // Skip to: 86948 -/* 64014 */ MCD_OPC_Decode, 221, 26, 202, 2, // Opcode: SSHLLv16i8_shift -/* 64019 */ MCD_OPC_FilterValue, 1, 140, 89, 0, // Skip to: 86948 -/* 64024 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 64027 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64042 -/* 64032 */ MCD_OPC_CheckPredicate, 3, 127, 89, 0, // Skip to: 86948 -/* 64037 */ MCD_OPC_Decode, 151, 23, 208, 2, // Opcode: SHRNv8i16_shift -/* 64042 */ MCD_OPC_FilterValue, 1, 117, 89, 0, // Skip to: 86948 -/* 64047 */ MCD_OPC_CheckPredicate, 3, 112, 89, 0, // Skip to: 86948 -/* 64052 */ MCD_OPC_Decode, 225, 26, 204, 2, // Opcode: SSHLLv8i16_shift -/* 64057 */ MCD_OPC_FilterValue, 1, 102, 89, 0, // Skip to: 86948 -/* 64062 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 64065 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64080 -/* 64070 */ MCD_OPC_CheckPredicate, 3, 89, 89, 0, // Skip to: 86948 -/* 64075 */ MCD_OPC_Decode, 150, 23, 209, 2, // Opcode: SHRNv4i32_shift -/* 64080 */ MCD_OPC_FilterValue, 1, 79, 89, 0, // Skip to: 86948 -/* 64085 */ MCD_OPC_CheckPredicate, 3, 74, 89, 0, // Skip to: 86948 -/* 64090 */ MCD_OPC_Decode, 224, 26, 206, 2, // Opcode: SSHLLv4i32_shift -/* 64095 */ MCD_OPC_FilterValue, 1, 64, 89, 0, // Skip to: 86948 -/* 64100 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 64103 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 64178 -/* 64108 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 64111 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64156 -/* 64116 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 64119 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64134 -/* 64124 */ MCD_OPC_CheckPredicate, 3, 35, 89, 0, // Skip to: 86948 -/* 64129 */ MCD_OPC_Decode, 221, 20, 180, 2, // Opcode: ORRv8i16 -/* 64134 */ MCD_OPC_FilterValue, 1, 25, 89, 0, // Skip to: 86948 -/* 64139 */ MCD_OPC_CheckPredicate, 3, 20, 89, 0, // Skip to: 86948 -/* 64144 */ MCD_OPC_CheckField, 13, 1, 0, 13, 89, 0, // Skip to: 86948 -/* 64151 */ MCD_OPC_Decode, 131, 26, 207, 2, // Opcode: SQSHRNv16i8_shift -/* 64156 */ MCD_OPC_FilterValue, 1, 3, 89, 0, // Skip to: 86948 -/* 64161 */ MCD_OPC_CheckPredicate, 3, 254, 88, 0, // Skip to: 86948 -/* 64166 */ MCD_OPC_CheckField, 13, 1, 0, 247, 88, 0, // Skip to: 86948 -/* 64173 */ MCD_OPC_Decode, 135, 26, 208, 2, // Opcode: SQSHRNv8i16_shift -/* 64178 */ MCD_OPC_FilterValue, 1, 237, 88, 0, // Skip to: 86948 -/* 64183 */ MCD_OPC_CheckPredicate, 3, 232, 88, 0, // Skip to: 86948 -/* 64188 */ MCD_OPC_CheckField, 13, 1, 0, 225, 88, 0, // Skip to: 86948 -/* 64195 */ MCD_OPC_Decode, 134, 26, 209, 2, // Opcode: SQSHRNv4i32_shift -/* 64200 */ MCD_OPC_FilterValue, 1, 215, 88, 0, // Skip to: 86948 -/* 64205 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 64208 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64230 -/* 64213 */ MCD_OPC_CheckPredicate, 3, 202, 88, 0, // Skip to: 86948 -/* 64218 */ MCD_OPC_CheckField, 19, 3, 0, 195, 88, 0, // Skip to: 86948 -/* 64225 */ MCD_OPC_Decode, 240, 19, 176, 2, // Opcode: MOVIv4s_msl -/* 64230 */ MCD_OPC_FilterValue, 1, 185, 88, 0, // Skip to: 86948 -/* 64235 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 64238 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 64306 -/* 64243 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 64246 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64291 -/* 64251 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 64254 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64276 -/* 64259 */ MCD_OPC_CheckPredicate, 3, 156, 88, 0, // Skip to: 86948 -/* 64264 */ MCD_OPC_CheckField, 19, 1, 0, 149, 88, 0, // Skip to: 86948 -/* 64271 */ MCD_OPC_Decode, 234, 19, 176, 2, // Opcode: MOVIv16b_ns -/* 64276 */ MCD_OPC_FilterValue, 1, 139, 88, 0, // Skip to: 86948 -/* 64281 */ MCD_OPC_CheckPredicate, 4, 134, 88, 0, // Skip to: 86948 -/* 64286 */ MCD_OPC_Decode, 218, 22, 199, 2, // Opcode: SCVTFv8i16_shift -/* 64291 */ MCD_OPC_FilterValue, 1, 124, 88, 0, // Skip to: 86948 -/* 64296 */ MCD_OPC_CheckPredicate, 3, 119, 88, 0, // Skip to: 86948 -/* 64301 */ MCD_OPC_Decode, 216, 22, 200, 2, // Opcode: SCVTFv4i32_shift -/* 64306 */ MCD_OPC_FilterValue, 1, 109, 88, 0, // Skip to: 86948 -/* 64311 */ MCD_OPC_CheckPredicate, 3, 104, 88, 0, // Skip to: 86948 -/* 64316 */ MCD_OPC_CheckField, 19, 3, 0, 97, 88, 0, // Skip to: 86948 -/* 64323 */ MCD_OPC_Decode, 237, 10, 176, 2, // Opcode: FMOVv4f32_ns -/* 64328 */ MCD_OPC_FilterValue, 1, 87, 88, 0, // Skip to: 86948 -/* 64333 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 64336 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 64404 -/* 64341 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 64344 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64389 -/* 64349 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 64352 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64374 -/* 64357 */ MCD_OPC_CheckPredicate, 3, 58, 88, 0, // Skip to: 86948 -/* 64362 */ MCD_OPC_CheckField, 19, 1, 1, 51, 88, 0, // Skip to: 86948 -/* 64369 */ MCD_OPC_Decode, 234, 21, 207, 2, // Opcode: RSHRNv16i8_shift -/* 64374 */ MCD_OPC_FilterValue, 1, 41, 88, 0, // Skip to: 86948 -/* 64379 */ MCD_OPC_CheckPredicate, 3, 36, 88, 0, // Skip to: 86948 -/* 64384 */ MCD_OPC_Decode, 238, 21, 208, 2, // Opcode: RSHRNv8i16_shift -/* 64389 */ MCD_OPC_FilterValue, 1, 26, 88, 0, // Skip to: 86948 -/* 64394 */ MCD_OPC_CheckPredicate, 3, 21, 88, 0, // Skip to: 86948 -/* 64399 */ MCD_OPC_Decode, 237, 21, 209, 2, // Opcode: RSHRNv4i32_shift -/* 64404 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 64472 -/* 64409 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 64412 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64457 -/* 64417 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 64420 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64442 -/* 64425 */ MCD_OPC_CheckPredicate, 3, 246, 87, 0, // Skip to: 86948 -/* 64430 */ MCD_OPC_CheckField, 19, 1, 1, 239, 87, 0, // Skip to: 86948 -/* 64437 */ MCD_OPC_Decode, 208, 25, 207, 2, // Opcode: SQRSHRNv16i8_shift -/* 64442 */ MCD_OPC_FilterValue, 1, 229, 87, 0, // Skip to: 86948 -/* 64447 */ MCD_OPC_CheckPredicate, 3, 224, 87, 0, // Skip to: 86948 -/* 64452 */ MCD_OPC_Decode, 212, 25, 208, 2, // Opcode: SQRSHRNv8i16_shift -/* 64457 */ MCD_OPC_FilterValue, 1, 214, 87, 0, // Skip to: 86948 -/* 64462 */ MCD_OPC_CheckPredicate, 3, 209, 87, 0, // Skip to: 86948 -/* 64467 */ MCD_OPC_Decode, 211, 25, 209, 2, // Opcode: SQRSHRNv4i32_shift -/* 64472 */ MCD_OPC_FilterValue, 15, 199, 87, 0, // Skip to: 86948 -/* 64477 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 64480 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64525 -/* 64485 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 64488 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64510 -/* 64493 */ MCD_OPC_CheckPredicate, 4, 178, 87, 0, // Skip to: 86948 -/* 64498 */ MCD_OPC_CheckField, 19, 1, 0, 171, 87, 0, // Skip to: 86948 -/* 64505 */ MCD_OPC_Decode, 238, 10, 176, 2, // Opcode: FMOVv8f16_ns -/* 64510 */ MCD_OPC_FilterValue, 1, 161, 87, 0, // Skip to: 86948 -/* 64515 */ MCD_OPC_CheckPredicate, 4, 156, 87, 0, // Skip to: 86948 -/* 64520 */ MCD_OPC_Decode, 252, 8, 199, 2, // Opcode: FCVTZSv8i16_shift -/* 64525 */ MCD_OPC_FilterValue, 1, 146, 87, 0, // Skip to: 86948 -/* 64530 */ MCD_OPC_CheckPredicate, 3, 141, 87, 0, // Skip to: 86948 -/* 64535 */ MCD_OPC_Decode, 250, 8, 200, 2, // Opcode: FCVTZSv4i32_shift -/* 64540 */ MCD_OPC_FilterValue, 3, 131, 87, 0, // Skip to: 86948 -/* 64545 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 64548 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64570 -/* 64553 */ MCD_OPC_CheckPredicate, 4, 118, 87, 0, // Skip to: 86948 -/* 64558 */ MCD_OPC_CheckField, 12, 4, 9, 111, 87, 0, // Skip to: 86948 -/* 64565 */ MCD_OPC_Decode, 138, 11, 197, 2, // Opcode: FMULXv8i16_indexed -/* 64570 */ MCD_OPC_FilterValue, 1, 101, 87, 0, // Skip to: 86948 -/* 64575 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 64578 */ MCD_OPC_FilterValue, 0, 131, 3, 0, // Skip to: 65482 -/* 64583 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 64586 */ MCD_OPC_FilterValue, 0, 233, 1, 0, // Skip to: 65080 -/* 64591 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 64594 */ MCD_OPC_FilterValue, 0, 238, 0, 0, // Skip to: 64837 -/* 64599 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 64602 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 64769 -/* 64607 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 64610 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 64701 -/* 64615 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 64618 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64633 -/* 64623 */ MCD_OPC_CheckPredicate, 3, 48, 87, 0, // Skip to: 86948 -/* 64628 */ MCD_OPC_Decode, 170, 20, 176, 2, // Opcode: MVNIv4i32 -/* 64633 */ MCD_OPC_FilterValue, 1, 38, 87, 0, // Skip to: 86948 -/* 64638 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 64641 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64656 -/* 64646 */ MCD_OPC_CheckPredicate, 3, 25, 87, 0, // Skip to: 86948 -/* 64651 */ MCD_OPC_Decode, 138, 34, 198, 2, // Opcode: USHRv16i8_shift -/* 64656 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64671 -/* 64661 */ MCD_OPC_CheckPredicate, 3, 10, 87, 0, // Skip to: 86948 -/* 64666 */ MCD_OPC_Decode, 234, 33, 198, 2, // Opcode: URSHRv16i8_shift -/* 64671 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64686 -/* 64676 */ MCD_OPC_CheckPredicate, 3, 251, 86, 0, // Skip to: 86948 -/* 64681 */ MCD_OPC_Decode, 190, 26, 201, 2, // Opcode: SRIv16i8_shift -/* 64686 */ MCD_OPC_FilterValue, 3, 241, 86, 0, // Skip to: 86948 -/* 64691 */ MCD_OPC_CheckPredicate, 3, 236, 86, 0, // Skip to: 86948 -/* 64696 */ MCD_OPC_Decode, 227, 25, 202, 2, // Opcode: SQSHLUv16i8_shift -/* 64701 */ MCD_OPC_FilterValue, 1, 226, 86, 0, // Skip to: 86948 -/* 64706 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 64709 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64724 -/* 64714 */ MCD_OPC_CheckPredicate, 3, 213, 86, 0, // Skip to: 86948 -/* 64719 */ MCD_OPC_Decode, 143, 34, 199, 2, // Opcode: USHRv8i16_shift -/* 64724 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64739 -/* 64729 */ MCD_OPC_CheckPredicate, 3, 198, 86, 0, // Skip to: 86948 -/* 64734 */ MCD_OPC_Decode, 239, 33, 199, 2, // Opcode: URSHRv8i16_shift -/* 64739 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64754 -/* 64744 */ MCD_OPC_CheckPredicate, 3, 183, 86, 0, // Skip to: 86948 -/* 64749 */ MCD_OPC_Decode, 195, 26, 203, 2, // Opcode: SRIv8i16_shift -/* 64754 */ MCD_OPC_FilterValue, 3, 173, 86, 0, // Skip to: 86948 -/* 64759 */ MCD_OPC_CheckPredicate, 3, 168, 86, 0, // Skip to: 86948 -/* 64764 */ MCD_OPC_Decode, 232, 25, 204, 2, // Opcode: SQSHLUv8i16_shift -/* 64769 */ MCD_OPC_FilterValue, 1, 158, 86, 0, // Skip to: 86948 -/* 64774 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 64777 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64792 -/* 64782 */ MCD_OPC_CheckPredicate, 3, 145, 86, 0, // Skip to: 86948 -/* 64787 */ MCD_OPC_Decode, 142, 34, 200, 2, // Opcode: USHRv4i32_shift -/* 64792 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64807 -/* 64797 */ MCD_OPC_CheckPredicate, 3, 130, 86, 0, // Skip to: 86948 -/* 64802 */ MCD_OPC_Decode, 238, 33, 200, 2, // Opcode: URSHRv4i32_shift -/* 64807 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64822 -/* 64812 */ MCD_OPC_CheckPredicate, 3, 115, 86, 0, // Skip to: 86948 -/* 64817 */ MCD_OPC_Decode, 194, 26, 205, 2, // Opcode: SRIv4i32_shift -/* 64822 */ MCD_OPC_FilterValue, 3, 105, 86, 0, // Skip to: 86948 -/* 64827 */ MCD_OPC_CheckPredicate, 3, 100, 86, 0, // Skip to: 86948 -/* 64832 */ MCD_OPC_Decode, 231, 25, 206, 2, // Opcode: SQSHLUv4i32_shift -/* 64837 */ MCD_OPC_FilterValue, 1, 90, 86, 0, // Skip to: 86948 -/* 64842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 64845 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 65012 -/* 64850 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 64853 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 64944 -/* 64858 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 64861 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64876 -/* 64866 */ MCD_OPC_CheckPredicate, 3, 61, 86, 0, // Skip to: 86948 -/* 64871 */ MCD_OPC_Decode, 190, 2, 180, 2, // Opcode: BICv4i32 -/* 64876 */ MCD_OPC_FilterValue, 1, 51, 86, 0, // Skip to: 86948 -/* 64881 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 64884 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64899 -/* 64889 */ MCD_OPC_CheckPredicate, 3, 38, 86, 0, // Skip to: 86948 -/* 64894 */ MCD_OPC_Decode, 157, 34, 201, 2, // Opcode: USRAv16i8_shift -/* 64899 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64914 -/* 64904 */ MCD_OPC_CheckPredicate, 3, 23, 86, 0, // Skip to: 86948 -/* 64909 */ MCD_OPC_Decode, 244, 33, 201, 2, // Opcode: URSRAv16i8_shift -/* 64914 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64929 -/* 64919 */ MCD_OPC_CheckPredicate, 3, 8, 86, 0, // Skip to: 86948 -/* 64924 */ MCD_OPC_Decode, 160, 23, 210, 2, // Opcode: SLIv16i8_shift -/* 64929 */ MCD_OPC_FilterValue, 3, 254, 85, 0, // Skip to: 86948 -/* 64934 */ MCD_OPC_CheckPredicate, 3, 249, 85, 0, // Skip to: 86948 -/* 64939 */ MCD_OPC_Decode, 163, 33, 202, 2, // Opcode: UQSHLv16i8_shift -/* 64944 */ MCD_OPC_FilterValue, 1, 239, 85, 0, // Skip to: 86948 -/* 64949 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 64952 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64967 -/* 64957 */ MCD_OPC_CheckPredicate, 3, 226, 85, 0, // Skip to: 86948 -/* 64962 */ MCD_OPC_Decode, 162, 34, 203, 2, // Opcode: USRAv8i16_shift -/* 64967 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64982 -/* 64972 */ MCD_OPC_CheckPredicate, 3, 211, 85, 0, // Skip to: 86948 -/* 64977 */ MCD_OPC_Decode, 249, 33, 203, 2, // Opcode: URSRAv8i16_shift -/* 64982 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64997 -/* 64987 */ MCD_OPC_CheckPredicate, 3, 196, 85, 0, // Skip to: 86948 -/* 64992 */ MCD_OPC_Decode, 165, 23, 211, 2, // Opcode: SLIv8i16_shift -/* 64997 */ MCD_OPC_FilterValue, 3, 186, 85, 0, // Skip to: 86948 -/* 65002 */ MCD_OPC_CheckPredicate, 3, 181, 85, 0, // Skip to: 86948 -/* 65007 */ MCD_OPC_Decode, 177, 33, 204, 2, // Opcode: UQSHLv8i16_shift -/* 65012 */ MCD_OPC_FilterValue, 1, 171, 85, 0, // Skip to: 86948 -/* 65017 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 65020 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65035 -/* 65025 */ MCD_OPC_CheckPredicate, 3, 158, 85, 0, // Skip to: 86948 -/* 65030 */ MCD_OPC_Decode, 161, 34, 205, 2, // Opcode: USRAv4i32_shift -/* 65035 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 65050 -/* 65040 */ MCD_OPC_CheckPredicate, 3, 143, 85, 0, // Skip to: 86948 -/* 65045 */ MCD_OPC_Decode, 248, 33, 205, 2, // Opcode: URSRAv4i32_shift -/* 65050 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 65065 -/* 65055 */ MCD_OPC_CheckPredicate, 3, 128, 85, 0, // Skip to: 86948 -/* 65060 */ MCD_OPC_Decode, 164, 23, 212, 2, // Opcode: SLIv4i32_shift -/* 65065 */ MCD_OPC_FilterValue, 3, 118, 85, 0, // Skip to: 86948 -/* 65070 */ MCD_OPC_CheckPredicate, 3, 113, 85, 0, // Skip to: 86948 -/* 65075 */ MCD_OPC_Decode, 175, 33, 206, 2, // Opcode: UQSHLv4i32_shift -/* 65080 */ MCD_OPC_FilterValue, 1, 103, 85, 0, // Skip to: 86948 -/* 65085 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 65088 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 65354 -/* 65093 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 65096 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 65249 -/* 65101 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 65104 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 65211 -/* 65109 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 65112 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 65173 -/* 65117 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 65120 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65135 -/* 65125 */ MCD_OPC_CheckPredicate, 3, 58, 85, 0, // Skip to: 86948 -/* 65130 */ MCD_OPC_Decode, 172, 20, 176, 2, // Opcode: MVNIv8i16 -/* 65135 */ MCD_OPC_FilterValue, 1, 48, 85, 0, // Skip to: 86948 -/* 65140 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 65143 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65158 -/* 65148 */ MCD_OPC_CheckPredicate, 3, 35, 85, 0, // Skip to: 86948 -/* 65153 */ MCD_OPC_Decode, 140, 26, 207, 2, // Opcode: SQSHRUNv16i8_shift -/* 65158 */ MCD_OPC_FilterValue, 1, 25, 85, 0, // Skip to: 86948 -/* 65163 */ MCD_OPC_CheckPredicate, 3, 20, 85, 0, // Skip to: 86948 -/* 65168 */ MCD_OPC_Decode, 251, 33, 202, 2, // Opcode: USHLLv16i8_shift -/* 65173 */ MCD_OPC_FilterValue, 1, 10, 85, 0, // Skip to: 86948 -/* 65178 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 65181 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65196 -/* 65186 */ MCD_OPC_CheckPredicate, 3, 253, 84, 0, // Skip to: 86948 -/* 65191 */ MCD_OPC_Decode, 144, 26, 208, 2, // Opcode: SQSHRUNv8i16_shift -/* 65196 */ MCD_OPC_FilterValue, 1, 243, 84, 0, // Skip to: 86948 -/* 65201 */ MCD_OPC_CheckPredicate, 3, 238, 84, 0, // Skip to: 86948 -/* 65206 */ MCD_OPC_Decode, 255, 33, 204, 2, // Opcode: USHLLv8i16_shift -/* 65211 */ MCD_OPC_FilterValue, 1, 228, 84, 0, // Skip to: 86948 -/* 65216 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 65219 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65234 -/* 65224 */ MCD_OPC_CheckPredicate, 3, 215, 84, 0, // Skip to: 86948 -/* 65229 */ MCD_OPC_Decode, 143, 26, 209, 2, // Opcode: SQSHRUNv4i32_shift -/* 65234 */ MCD_OPC_FilterValue, 1, 205, 84, 0, // Skip to: 86948 -/* 65239 */ MCD_OPC_CheckPredicate, 3, 200, 84, 0, // Skip to: 86948 -/* 65244 */ MCD_OPC_Decode, 254, 33, 206, 2, // Opcode: USHLLv4i32_shift -/* 65249 */ MCD_OPC_FilterValue, 1, 190, 84, 0, // Skip to: 86948 -/* 65254 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 65257 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 65332 -/* 65262 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 65265 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65310 -/* 65270 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 65273 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65288 -/* 65278 */ MCD_OPC_CheckPredicate, 3, 161, 84, 0, // Skip to: 86948 -/* 65283 */ MCD_OPC_Decode, 191, 2, 180, 2, // Opcode: BICv8i16 -/* 65288 */ MCD_OPC_FilterValue, 1, 151, 84, 0, // Skip to: 86948 -/* 65293 */ MCD_OPC_CheckPredicate, 3, 146, 84, 0, // Skip to: 86948 -/* 65298 */ MCD_OPC_CheckField, 13, 1, 0, 139, 84, 0, // Skip to: 86948 -/* 65305 */ MCD_OPC_Decode, 183, 33, 207, 2, // Opcode: UQSHRNv16i8_shift -/* 65310 */ MCD_OPC_FilterValue, 1, 129, 84, 0, // Skip to: 86948 -/* 65315 */ MCD_OPC_CheckPredicate, 3, 124, 84, 0, // Skip to: 86948 -/* 65320 */ MCD_OPC_CheckField, 13, 1, 0, 117, 84, 0, // Skip to: 86948 -/* 65327 */ MCD_OPC_Decode, 187, 33, 208, 2, // Opcode: UQSHRNv8i16_shift -/* 65332 */ MCD_OPC_FilterValue, 1, 107, 84, 0, // Skip to: 86948 -/* 65337 */ MCD_OPC_CheckPredicate, 3, 102, 84, 0, // Skip to: 86948 -/* 65342 */ MCD_OPC_CheckField, 13, 1, 0, 95, 84, 0, // Skip to: 86948 -/* 65349 */ MCD_OPC_Decode, 186, 33, 209, 2, // Opcode: UQSHRNv4i32_shift -/* 65354 */ MCD_OPC_FilterValue, 1, 85, 84, 0, // Skip to: 86948 -/* 65359 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 65362 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65384 -/* 65367 */ MCD_OPC_CheckPredicate, 3, 72, 84, 0, // Skip to: 86948 -/* 65372 */ MCD_OPC_CheckField, 19, 3, 0, 65, 84, 0, // Skip to: 86948 -/* 65379 */ MCD_OPC_Decode, 171, 20, 176, 2, // Opcode: MVNIv4s_msl -/* 65384 */ MCD_OPC_FilterValue, 1, 55, 84, 0, // Skip to: 86948 -/* 65389 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 65392 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 65460 -/* 65397 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 65400 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65445 -/* 65405 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 65408 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65430 -/* 65413 */ MCD_OPC_CheckPredicate, 3, 26, 84, 0, // Skip to: 86948 -/* 65418 */ MCD_OPC_CheckField, 19, 1, 0, 19, 84, 0, // Skip to: 86948 -/* 65425 */ MCD_OPC_Decode, 235, 19, 176, 2, // Opcode: MOVIv2d_ns -/* 65430 */ MCD_OPC_FilterValue, 1, 9, 84, 0, // Skip to: 86948 -/* 65435 */ MCD_OPC_CheckPredicate, 4, 4, 84, 0, // Skip to: 86948 -/* 65440 */ MCD_OPC_Decode, 205, 31, 199, 2, // Opcode: UCVTFv8i16_shift -/* 65445 */ MCD_OPC_FilterValue, 1, 250, 83, 0, // Skip to: 86948 -/* 65450 */ MCD_OPC_CheckPredicate, 3, 245, 83, 0, // Skip to: 86948 -/* 65455 */ MCD_OPC_Decode, 203, 31, 200, 2, // Opcode: UCVTFv4i32_shift -/* 65460 */ MCD_OPC_FilterValue, 1, 235, 83, 0, // Skip to: 86948 -/* 65465 */ MCD_OPC_CheckPredicate, 3, 230, 83, 0, // Skip to: 86948 -/* 65470 */ MCD_OPC_CheckField, 19, 3, 0, 223, 83, 0, // Skip to: 86948 -/* 65477 */ MCD_OPC_Decode, 235, 10, 176, 2, // Opcode: FMOVv2f64_ns -/* 65482 */ MCD_OPC_FilterValue, 1, 213, 83, 0, // Skip to: 86948 -/* 65487 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 65490 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 65558 -/* 65495 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 65498 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65543 -/* 65503 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 65506 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65528 -/* 65511 */ MCD_OPC_CheckPredicate, 3, 184, 83, 0, // Skip to: 86948 -/* 65516 */ MCD_OPC_CheckField, 19, 1, 1, 177, 83, 0, // Skip to: 86948 -/* 65523 */ MCD_OPC_Decode, 217, 25, 207, 2, // Opcode: SQRSHRUNv16i8_shift -/* 65528 */ MCD_OPC_FilterValue, 1, 167, 83, 0, // Skip to: 86948 -/* 65533 */ MCD_OPC_CheckPredicate, 3, 162, 83, 0, // Skip to: 86948 -/* 65538 */ MCD_OPC_Decode, 221, 25, 208, 2, // Opcode: SQRSHRUNv8i16_shift -/* 65543 */ MCD_OPC_FilterValue, 1, 152, 83, 0, // Skip to: 86948 -/* 65548 */ MCD_OPC_CheckPredicate, 3, 147, 83, 0, // Skip to: 86948 -/* 65553 */ MCD_OPC_Decode, 220, 25, 209, 2, // Opcode: SQRSHRUNv4i32_shift -/* 65558 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 65626 -/* 65563 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 65566 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65611 -/* 65571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 65574 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65596 -/* 65579 */ MCD_OPC_CheckPredicate, 3, 116, 83, 0, // Skip to: 86948 -/* 65584 */ MCD_OPC_CheckField, 19, 1, 1, 109, 83, 0, // Skip to: 86948 -/* 65591 */ MCD_OPC_Decode, 152, 33, 207, 2, // Opcode: UQRSHRNv16i8_shift -/* 65596 */ MCD_OPC_FilterValue, 1, 99, 83, 0, // Skip to: 86948 -/* 65601 */ MCD_OPC_CheckPredicate, 3, 94, 83, 0, // Skip to: 86948 -/* 65606 */ MCD_OPC_Decode, 156, 33, 208, 2, // Opcode: UQRSHRNv8i16_shift -/* 65611 */ MCD_OPC_FilterValue, 1, 84, 83, 0, // Skip to: 86948 -/* 65616 */ MCD_OPC_CheckPredicate, 3, 79, 83, 0, // Skip to: 86948 -/* 65621 */ MCD_OPC_Decode, 155, 33, 209, 2, // Opcode: UQRSHRNv4i32_shift -/* 65626 */ MCD_OPC_FilterValue, 15, 69, 83, 0, // Skip to: 86948 -/* 65631 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 65634 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65656 -/* 65639 */ MCD_OPC_CheckPredicate, 4, 56, 83, 0, // Skip to: 86948 -/* 65644 */ MCD_OPC_CheckField, 20, 1, 1, 49, 83, 0, // Skip to: 86948 -/* 65651 */ MCD_OPC_Decode, 159, 9, 199, 2, // Opcode: FCVTZUv8i16_shift -/* 65656 */ MCD_OPC_FilterValue, 1, 39, 83, 0, // Skip to: 86948 -/* 65661 */ MCD_OPC_CheckPredicate, 3, 34, 83, 0, // Skip to: 86948 -/* 65666 */ MCD_OPC_Decode, 157, 9, 200, 2, // Opcode: FCVTZUv4i32_shift -/* 65671 */ MCD_OPC_FilterValue, 13, 96, 4, 0, // Skip to: 66796 -/* 65676 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 65679 */ MCD_OPC_FilterValue, 0, 201, 0, 0, // Skip to: 65885 -/* 65684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 65687 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 65709 -/* 65692 */ MCD_OPC_CheckPredicate, 3, 3, 83, 0, // Skip to: 86948 -/* 65697 */ MCD_OPC_CheckField, 10, 1, 0, 252, 82, 0, // Skip to: 86948 -/* 65704 */ MCD_OPC_Decode, 239, 23, 213, 2, // Opcode: SMLALv4i16_indexed -/* 65709 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 65731 -/* 65714 */ MCD_OPC_CheckPredicate, 3, 237, 82, 0, // Skip to: 86948 -/* 65719 */ MCD_OPC_CheckField, 10, 1, 0, 230, 82, 0, // Skip to: 86948 -/* 65726 */ MCD_OPC_Decode, 211, 24, 213, 2, // Opcode: SQDMLALv4i16_indexed -/* 65731 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 65753 -/* 65736 */ MCD_OPC_CheckPredicate, 3, 215, 82, 0, // Skip to: 86948 -/* 65741 */ MCD_OPC_CheckField, 10, 1, 0, 208, 82, 0, // Skip to: 86948 -/* 65748 */ MCD_OPC_Decode, 249, 23, 213, 2, // Opcode: SMLSLv4i16_indexed -/* 65753 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 65775 -/* 65758 */ MCD_OPC_CheckPredicate, 3, 193, 82, 0, // Skip to: 86948 -/* 65763 */ MCD_OPC_CheckField, 10, 1, 0, 186, 82, 0, // Skip to: 86948 -/* 65770 */ MCD_OPC_Decode, 223, 24, 213, 2, // Opcode: SQDMLSLv4i16_indexed -/* 65775 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 65797 -/* 65780 */ MCD_OPC_CheckPredicate, 3, 171, 82, 0, // Skip to: 86948 -/* 65785 */ MCD_OPC_CheckField, 10, 1, 0, 164, 82, 0, // Skip to: 86948 -/* 65792 */ MCD_OPC_Decode, 161, 20, 175, 2, // Opcode: MULv4i16_indexed -/* 65797 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 65819 -/* 65802 */ MCD_OPC_CheckPredicate, 3, 149, 82, 0, // Skip to: 86948 -/* 65807 */ MCD_OPC_CheckField, 10, 1, 0, 142, 82, 0, // Skip to: 86948 -/* 65814 */ MCD_OPC_Decode, 142, 24, 214, 2, // Opcode: SMULLv4i16_indexed -/* 65819 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 65841 -/* 65824 */ MCD_OPC_CheckPredicate, 3, 127, 82, 0, // Skip to: 86948 -/* 65829 */ MCD_OPC_CheckField, 10, 1, 0, 120, 82, 0, // Skip to: 86948 -/* 65836 */ MCD_OPC_Decode, 247, 24, 214, 2, // Opcode: SQDMULLv4i16_indexed -/* 65841 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 65863 -/* 65846 */ MCD_OPC_CheckPredicate, 3, 105, 82, 0, // Skip to: 86948 -/* 65851 */ MCD_OPC_CheckField, 10, 1, 0, 98, 82, 0, // Skip to: 86948 -/* 65858 */ MCD_OPC_Decode, 236, 24, 175, 2, // Opcode: SQDMULHv4i16_indexed -/* 65863 */ MCD_OPC_FilterValue, 13, 88, 82, 0, // Skip to: 86948 -/* 65868 */ MCD_OPC_CheckPredicate, 3, 83, 82, 0, // Skip to: 86948 -/* 65873 */ MCD_OPC_CheckField, 10, 1, 0, 76, 82, 0, // Skip to: 86948 -/* 65880 */ MCD_OPC_Decode, 189, 25, 175, 2, // Opcode: SQRDMULHv4i16_indexed -/* 65885 */ MCD_OPC_FilterValue, 1, 203, 0, 0, // Skip to: 66093 -/* 65890 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 65893 */ MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 66011 -/* 65898 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 65901 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65923 -/* 65906 */ MCD_OPC_CheckPredicate, 3, 45, 82, 0, // Skip to: 86948 -/* 65911 */ MCD_OPC_CheckField, 10, 1, 0, 38, 82, 0, // Skip to: 86948 -/* 65918 */ MCD_OPC_Decode, 213, 19, 174, 2, // Opcode: MLAv4i16_indexed -/* 65923 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 65945 -/* 65928 */ MCD_OPC_CheckPredicate, 3, 23, 82, 0, // Skip to: 86948 -/* 65933 */ MCD_OPC_CheckField, 10, 1, 0, 16, 82, 0, // Skip to: 86948 -/* 65940 */ MCD_OPC_Decode, 166, 32, 213, 2, // Opcode: UMLALv4i16_indexed -/* 65945 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 65967 -/* 65950 */ MCD_OPC_CheckPredicate, 3, 1, 82, 0, // Skip to: 86948 -/* 65955 */ MCD_OPC_CheckField, 10, 1, 0, 250, 81, 0, // Skip to: 86948 -/* 65962 */ MCD_OPC_Decode, 227, 19, 174, 2, // Opcode: MLSv4i16_indexed -/* 65967 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 65989 -/* 65972 */ MCD_OPC_CheckPredicate, 3, 235, 81, 0, // Skip to: 86948 -/* 65977 */ MCD_OPC_CheckField, 10, 1, 0, 228, 81, 0, // Skip to: 86948 -/* 65984 */ MCD_OPC_Decode, 176, 32, 213, 2, // Opcode: UMLSLv4i16_indexed -/* 65989 */ MCD_OPC_FilterValue, 5, 218, 81, 0, // Skip to: 86948 -/* 65994 */ MCD_OPC_CheckPredicate, 3, 213, 81, 0, // Skip to: 86948 -/* 65999 */ MCD_OPC_CheckField, 10, 1, 0, 206, 81, 0, // Skip to: 86948 -/* 66006 */ MCD_OPC_Decode, 196, 32, 214, 2, // Opcode: UMULLv4i16_indexed -/* 66011 */ MCD_OPC_FilterValue, 1, 196, 81, 0, // Skip to: 86948 -/* 66016 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 66019 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 66041 -/* 66024 */ MCD_OPC_CheckPredicate, 8, 183, 81, 0, // Skip to: 86948 -/* 66029 */ MCD_OPC_CheckField, 10, 2, 0, 176, 81, 0, // Skip to: 86948 -/* 66036 */ MCD_OPC_Decode, 163, 7, 215, 2, // Opcode: FCMLAv4f16_indexed -/* 66041 */ MCD_OPC_FilterValue, 1, 166, 81, 0, // Skip to: 86948 -/* 66046 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 66049 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 66071 -/* 66054 */ MCD_OPC_CheckPredicate, 7, 153, 81, 0, // Skip to: 86948 -/* 66059 */ MCD_OPC_CheckField, 10, 1, 0, 146, 81, 0, // Skip to: 86948 -/* 66066 */ MCD_OPC_Decode, 165, 25, 174, 2, // Opcode: SQRDMLAHv4i16_indexed -/* 66071 */ MCD_OPC_FilterValue, 3, 136, 81, 0, // Skip to: 86948 -/* 66076 */ MCD_OPC_CheckPredicate, 7, 131, 81, 0, // Skip to: 86948 -/* 66081 */ MCD_OPC_CheckField, 10, 1, 0, 124, 81, 0, // Skip to: 86948 -/* 66088 */ MCD_OPC_Decode, 177, 25, 174, 2, // Opcode: SQRDMLSHv4i16_indexed -/* 66093 */ MCD_OPC_FilterValue, 2, 124, 1, 0, // Skip to: 66478 -/* 66098 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 66101 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 66123 -/* 66106 */ MCD_OPC_CheckPredicate, 3, 101, 81, 0, // Skip to: 86948 -/* 66111 */ MCD_OPC_CheckField, 10, 2, 1, 94, 81, 0, // Skip to: 86948 -/* 66118 */ MCD_OPC_Decode, 238, 26, 216, 2, // Opcode: SSHRv2i64_shift -/* 66123 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 66145 -/* 66128 */ MCD_OPC_CheckPredicate, 3, 79, 81, 0, // Skip to: 86948 -/* 66133 */ MCD_OPC_CheckField, 10, 2, 1, 72, 81, 0, // Skip to: 86948 -/* 66140 */ MCD_OPC_Decode, 246, 26, 217, 2, // Opcode: SSRAv2i64_shift -/* 66145 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 66190 -/* 66150 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 66153 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66168 -/* 66158 */ MCD_OPC_CheckPredicate, 3, 49, 81, 0, // Skip to: 86948 -/* 66163 */ MCD_OPC_Decode, 243, 23, 196, 2, // Opcode: SMLALv8i16_indexed -/* 66168 */ MCD_OPC_FilterValue, 1, 39, 81, 0, // Skip to: 86948 -/* 66173 */ MCD_OPC_CheckPredicate, 3, 34, 81, 0, // Skip to: 86948 -/* 66178 */ MCD_OPC_CheckField, 11, 1, 0, 27, 81, 0, // Skip to: 86948 -/* 66185 */ MCD_OPC_Decode, 208, 26, 216, 2, // Opcode: SRSHRv2i64_shift -/* 66190 */ MCD_OPC_FilterValue, 3, 40, 0, 0, // Skip to: 66235 -/* 66195 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 66198 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66213 -/* 66203 */ MCD_OPC_CheckPredicate, 3, 4, 81, 0, // Skip to: 86948 -/* 66208 */ MCD_OPC_Decode, 215, 24, 196, 2, // Opcode: SQDMLALv8i16_indexed -/* 66213 */ MCD_OPC_FilterValue, 1, 250, 80, 0, // Skip to: 86948 -/* 66218 */ MCD_OPC_CheckPredicate, 3, 245, 80, 0, // Skip to: 86948 -/* 66223 */ MCD_OPC_CheckField, 11, 1, 0, 238, 80, 0, // Skip to: 86948 -/* 66230 */ MCD_OPC_Decode, 216, 26, 217, 2, // Opcode: SRSRAv2i64_shift -/* 66235 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 66257 -/* 66240 */ MCD_OPC_CheckPredicate, 3, 223, 80, 0, // Skip to: 86948 -/* 66245 */ MCD_OPC_CheckField, 10, 2, 1, 216, 80, 0, // Skip to: 86948 -/* 66252 */ MCD_OPC_Decode, 142, 23, 218, 2, // Opcode: SHLv2i64_shift -/* 66257 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 66279 -/* 66262 */ MCD_OPC_CheckPredicate, 3, 201, 80, 0, // Skip to: 86948 -/* 66267 */ MCD_OPC_CheckField, 10, 1, 0, 194, 80, 0, // Skip to: 86948 -/* 66274 */ MCD_OPC_Decode, 253, 23, 196, 2, // Opcode: SMLSLv8i16_indexed -/* 66279 */ MCD_OPC_FilterValue, 7, 40, 0, 0, // Skip to: 66324 -/* 66284 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 66287 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66302 -/* 66292 */ MCD_OPC_CheckPredicate, 3, 171, 80, 0, // Skip to: 86948 -/* 66297 */ MCD_OPC_Decode, 227, 24, 196, 2, // Opcode: SQDMLSLv8i16_indexed -/* 66302 */ MCD_OPC_FilterValue, 1, 161, 80, 0, // Skip to: 86948 -/* 66307 */ MCD_OPC_CheckPredicate, 3, 156, 80, 0, // Skip to: 86948 -/* 66312 */ MCD_OPC_CheckField, 11, 1, 0, 149, 80, 0, // Skip to: 86948 -/* 66319 */ MCD_OPC_Decode, 247, 25, 218, 2, // Opcode: SQSHLv2i64_shift -/* 66324 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 66346 -/* 66329 */ MCD_OPC_CheckPredicate, 3, 134, 80, 0, // Skip to: 86948 -/* 66334 */ MCD_OPC_CheckField, 10, 1, 0, 127, 80, 0, // Skip to: 86948 -/* 66341 */ MCD_OPC_Decode, 165, 20, 197, 2, // Opcode: MULv8i16_indexed -/* 66346 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 66368 -/* 66351 */ MCD_OPC_CheckPredicate, 3, 112, 80, 0, // Skip to: 86948 -/* 66356 */ MCD_OPC_CheckField, 10, 1, 0, 105, 80, 0, // Skip to: 86948 -/* 66363 */ MCD_OPC_Decode, 146, 24, 197, 2, // Opcode: SMULLv8i16_indexed -/* 66368 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 66390 -/* 66373 */ MCD_OPC_CheckPredicate, 3, 90, 80, 0, // Skip to: 86948 -/* 66378 */ MCD_OPC_CheckField, 10, 1, 0, 83, 80, 0, // Skip to: 86948 -/* 66385 */ MCD_OPC_Decode, 251, 24, 197, 2, // Opcode: SQDMULLv8i16_indexed -/* 66390 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 66412 -/* 66395 */ MCD_OPC_CheckPredicate, 3, 68, 80, 0, // Skip to: 86948 -/* 66400 */ MCD_OPC_CheckField, 10, 1, 0, 61, 80, 0, // Skip to: 86948 -/* 66407 */ MCD_OPC_Decode, 240, 24, 197, 2, // Opcode: SQDMULHv8i16_indexed -/* 66412 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 66434 -/* 66417 */ MCD_OPC_CheckPredicate, 3, 46, 80, 0, // Skip to: 86948 -/* 66422 */ MCD_OPC_CheckField, 10, 1, 0, 39, 80, 0, // Skip to: 86948 -/* 66429 */ MCD_OPC_Decode, 193, 25, 197, 2, // Opcode: SQRDMULHv8i16_indexed -/* 66434 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 66456 -/* 66439 */ MCD_OPC_CheckPredicate, 3, 24, 80, 0, // Skip to: 86948 -/* 66444 */ MCD_OPC_CheckField, 10, 2, 1, 17, 80, 0, // Skip to: 86948 -/* 66451 */ MCD_OPC_Decode, 212, 22, 216, 2, // Opcode: SCVTFv2i64_shift -/* 66456 */ MCD_OPC_FilterValue, 15, 7, 80, 0, // Skip to: 86948 -/* 66461 */ MCD_OPC_CheckPredicate, 3, 2, 80, 0, // Skip to: 86948 -/* 66466 */ MCD_OPC_CheckField, 10, 2, 3, 251, 79, 0, // Skip to: 86948 -/* 66473 */ MCD_OPC_Decode, 246, 8, 216, 2, // Opcode: FCVTZSv2i64_shift -/* 66478 */ MCD_OPC_FilterValue, 3, 241, 79, 0, // Skip to: 86948 -/* 66483 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 66486 */ MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 66638 -/* 66491 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 66494 */ MCD_OPC_FilterValue, 0, 78, 0, 0, // Skip to: 66577 -/* 66499 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 66502 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66517 -/* 66507 */ MCD_OPC_CheckPredicate, 3, 212, 79, 0, // Skip to: 86948 -/* 66512 */ MCD_OPC_Decode, 217, 19, 196, 2, // Opcode: MLAv8i16_indexed -/* 66517 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 66532 -/* 66522 */ MCD_OPC_CheckPredicate, 3, 197, 79, 0, // Skip to: 86948 -/* 66527 */ MCD_OPC_Decode, 170, 32, 196, 2, // Opcode: UMLALv8i16_indexed -/* 66532 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 66547 -/* 66537 */ MCD_OPC_CheckPredicate, 3, 182, 79, 0, // Skip to: 86948 -/* 66542 */ MCD_OPC_Decode, 231, 19, 196, 2, // Opcode: MLSv8i16_indexed -/* 66547 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 66562 -/* 66552 */ MCD_OPC_CheckPredicate, 3, 167, 79, 0, // Skip to: 86948 -/* 66557 */ MCD_OPC_Decode, 180, 32, 196, 2, // Opcode: UMLSLv8i16_indexed -/* 66562 */ MCD_OPC_FilterValue, 5, 157, 79, 0, // Skip to: 86948 -/* 66567 */ MCD_OPC_CheckPredicate, 3, 152, 79, 0, // Skip to: 86948 -/* 66572 */ MCD_OPC_Decode, 200, 32, 197, 2, // Opcode: UMULLv8i16_indexed -/* 66577 */ MCD_OPC_FilterValue, 1, 142, 79, 0, // Skip to: 86948 -/* 66582 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 66585 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66600 -/* 66590 */ MCD_OPC_CheckPredicate, 8, 129, 79, 0, // Skip to: 86948 -/* 66595 */ MCD_OPC_Decode, 167, 7, 219, 2, // Opcode: FCMLAv8f16_indexed -/* 66600 */ MCD_OPC_FilterValue, 1, 119, 79, 0, // Skip to: 86948 -/* 66605 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 66608 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 66623 -/* 66613 */ MCD_OPC_CheckPredicate, 7, 106, 79, 0, // Skip to: 86948 -/* 66618 */ MCD_OPC_Decode, 169, 25, 196, 2, // Opcode: SQRDMLAHv8i16_indexed -/* 66623 */ MCD_OPC_FilterValue, 3, 96, 79, 0, // Skip to: 86948 -/* 66628 */ MCD_OPC_CheckPredicate, 7, 91, 79, 0, // Skip to: 86948 -/* 66633 */ MCD_OPC_Decode, 181, 25, 196, 2, // Opcode: SQRDMLSHv8i16_indexed -/* 66638 */ MCD_OPC_FilterValue, 1, 81, 79, 0, // Skip to: 86948 -/* 66643 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... -/* 66646 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66661 -/* 66651 */ MCD_OPC_CheckPredicate, 3, 68, 79, 0, // Skip to: 86948 -/* 66656 */ MCD_OPC_Decode, 140, 34, 216, 2, // Opcode: USHRv2i64_shift -/* 66661 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 66676 -/* 66666 */ MCD_OPC_CheckPredicate, 3, 53, 79, 0, // Skip to: 86948 -/* 66671 */ MCD_OPC_Decode, 159, 34, 217, 2, // Opcode: USRAv2i64_shift -/* 66676 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 66691 -/* 66681 */ MCD_OPC_CheckPredicate, 3, 38, 79, 0, // Skip to: 86948 -/* 66686 */ MCD_OPC_Decode, 236, 33, 216, 2, // Opcode: URSHRv2i64_shift -/* 66691 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 66706 -/* 66696 */ MCD_OPC_CheckPredicate, 3, 23, 79, 0, // Skip to: 86948 -/* 66701 */ MCD_OPC_Decode, 246, 33, 217, 2, // Opcode: URSRAv2i64_shift -/* 66706 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 66721 -/* 66711 */ MCD_OPC_CheckPredicate, 3, 8, 79, 0, // Skip to: 86948 -/* 66716 */ MCD_OPC_Decode, 192, 26, 217, 2, // Opcode: SRIv2i64_shift -/* 66721 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 66736 -/* 66726 */ MCD_OPC_CheckPredicate, 3, 249, 78, 0, // Skip to: 86948 -/* 66731 */ MCD_OPC_Decode, 162, 23, 220, 2, // Opcode: SLIv2i64_shift -/* 66736 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 66751 -/* 66741 */ MCD_OPC_CheckPredicate, 3, 234, 78, 0, // Skip to: 86948 -/* 66746 */ MCD_OPC_Decode, 229, 25, 218, 2, // Opcode: SQSHLUv2i64_shift -/* 66751 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 66766 -/* 66756 */ MCD_OPC_CheckPredicate, 3, 219, 78, 0, // Skip to: 86948 -/* 66761 */ MCD_OPC_Decode, 171, 33, 218, 2, // Opcode: UQSHLv2i64_shift -/* 66766 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 66781 -/* 66771 */ MCD_OPC_CheckPredicate, 3, 204, 78, 0, // Skip to: 86948 -/* 66776 */ MCD_OPC_Decode, 199, 31, 216, 2, // Opcode: UCVTFv2i64_shift -/* 66781 */ MCD_OPC_FilterValue, 31, 194, 78, 0, // Skip to: 86948 -/* 66786 */ MCD_OPC_CheckPredicate, 3, 189, 78, 0, // Skip to: 86948 -/* 66791 */ MCD_OPC_Decode, 153, 9, 216, 2, // Opcode: FCVTZUv2i64_shift -/* 66796 */ MCD_OPC_FilterValue, 14, 32, 4, 0, // Skip to: 67857 -/* 66801 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 66804 */ MCD_OPC_FilterValue, 0, 33, 1, 0, // Skip to: 67098 -/* 66809 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 66812 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 66834 -/* 66817 */ MCD_OPC_CheckPredicate, 3, 158, 78, 0, // Skip to: 86948 -/* 66822 */ MCD_OPC_CheckField, 10, 1, 0, 151, 78, 0, // Skip to: 86948 -/* 66829 */ MCD_OPC_Decode, 188, 10, 221, 2, // Opcode: FMLAv2i32_indexed -/* 66834 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 66856 -/* 66839 */ MCD_OPC_CheckPredicate, 3, 136, 78, 0, // Skip to: 86948 -/* 66844 */ MCD_OPC_CheckField, 10, 1, 0, 129, 78, 0, // Skip to: 86948 -/* 66851 */ MCD_OPC_Decode, 237, 23, 222, 2, // Opcode: SMLALv2i32_indexed -/* 66856 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 66878 -/* 66861 */ MCD_OPC_CheckPredicate, 3, 114, 78, 0, // Skip to: 86948 -/* 66866 */ MCD_OPC_CheckField, 10, 1, 0, 107, 78, 0, // Skip to: 86948 -/* 66873 */ MCD_OPC_Decode, 209, 24, 222, 2, // Opcode: SQDMLALv2i32_indexed -/* 66878 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 66900 -/* 66883 */ MCD_OPC_CheckPredicate, 3, 92, 78, 0, // Skip to: 86948 -/* 66888 */ MCD_OPC_CheckField, 10, 1, 0, 85, 78, 0, // Skip to: 86948 -/* 66895 */ MCD_OPC_Decode, 207, 10, 221, 2, // Opcode: FMLSv2i32_indexed -/* 66900 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 66922 -/* 66905 */ MCD_OPC_CheckPredicate, 3, 70, 78, 0, // Skip to: 86948 -/* 66910 */ MCD_OPC_CheckField, 10, 1, 0, 63, 78, 0, // Skip to: 86948 -/* 66917 */ MCD_OPC_Decode, 247, 23, 222, 2, // Opcode: SMLSLv2i32_indexed -/* 66922 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 66944 -/* 66927 */ MCD_OPC_CheckPredicate, 3, 48, 78, 0, // Skip to: 86948 -/* 66932 */ MCD_OPC_CheckField, 10, 1, 0, 41, 78, 0, // Skip to: 86948 -/* 66939 */ MCD_OPC_Decode, 221, 24, 222, 2, // Opcode: SQDMLSLv2i32_indexed -/* 66944 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 66966 -/* 66949 */ MCD_OPC_CheckPredicate, 3, 26, 78, 0, // Skip to: 86948 -/* 66954 */ MCD_OPC_CheckField, 10, 1, 0, 19, 78, 0, // Skip to: 86948 -/* 66961 */ MCD_OPC_Decode, 159, 20, 223, 2, // Opcode: MULv2i32_indexed -/* 66966 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 66988 -/* 66971 */ MCD_OPC_CheckPredicate, 3, 4, 78, 0, // Skip to: 86948 -/* 66976 */ MCD_OPC_CheckField, 10, 1, 0, 253, 77, 0, // Skip to: 86948 -/* 66983 */ MCD_OPC_Decode, 156, 11, 223, 2, // Opcode: FMULv2i32_indexed -/* 66988 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 67010 -/* 66993 */ MCD_OPC_CheckPredicate, 3, 238, 77, 0, // Skip to: 86948 -/* 66998 */ MCD_OPC_CheckField, 10, 1, 0, 231, 77, 0, // Skip to: 86948 -/* 67005 */ MCD_OPC_Decode, 140, 24, 224, 2, // Opcode: SMULLv2i32_indexed -/* 67010 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 67032 -/* 67015 */ MCD_OPC_CheckPredicate, 3, 216, 77, 0, // Skip to: 86948 -/* 67020 */ MCD_OPC_CheckField, 10, 1, 0, 209, 77, 0, // Skip to: 86948 -/* 67027 */ MCD_OPC_Decode, 245, 24, 224, 2, // Opcode: SQDMULLv2i32_indexed -/* 67032 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 67054 -/* 67037 */ MCD_OPC_CheckPredicate, 3, 194, 77, 0, // Skip to: 86948 -/* 67042 */ MCD_OPC_CheckField, 10, 1, 0, 187, 77, 0, // Skip to: 86948 -/* 67049 */ MCD_OPC_Decode, 234, 24, 223, 2, // Opcode: SQDMULHv2i32_indexed -/* 67054 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 67076 -/* 67059 */ MCD_OPC_CheckPredicate, 3, 172, 77, 0, // Skip to: 86948 -/* 67064 */ MCD_OPC_CheckField, 10, 1, 0, 165, 77, 0, // Skip to: 86948 -/* 67071 */ MCD_OPC_Decode, 187, 25, 223, 2, // Opcode: SQRDMULHv2i32_indexed -/* 67076 */ MCD_OPC_FilterValue, 14, 155, 77, 0, // Skip to: 86948 -/* 67081 */ MCD_OPC_CheckPredicate, 10, 150, 77, 0, // Skip to: 86948 -/* 67086 */ MCD_OPC_CheckField, 10, 1, 0, 143, 77, 0, // Skip to: 86948 -/* 67093 */ MCD_OPC_Decode, 230, 22, 221, 2, // Opcode: SDOTlanev8i8 -/* 67098 */ MCD_OPC_FilterValue, 1, 201, 0, 0, // Skip to: 67304 -/* 67103 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 67106 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 67128 -/* 67111 */ MCD_OPC_CheckPredicate, 3, 120, 77, 0, // Skip to: 86948 -/* 67116 */ MCD_OPC_CheckField, 10, 1, 0, 113, 77, 0, // Skip to: 86948 -/* 67123 */ MCD_OPC_Decode, 211, 19, 221, 2, // Opcode: MLAv2i32_indexed -/* 67128 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67150 -/* 67133 */ MCD_OPC_CheckPredicate, 3, 98, 77, 0, // Skip to: 86948 -/* 67138 */ MCD_OPC_CheckField, 10, 1, 0, 91, 77, 0, // Skip to: 86948 -/* 67145 */ MCD_OPC_Decode, 164, 32, 222, 2, // Opcode: UMLALv2i32_indexed -/* 67150 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 67172 -/* 67155 */ MCD_OPC_CheckPredicate, 3, 76, 77, 0, // Skip to: 86948 -/* 67160 */ MCD_OPC_CheckField, 10, 1, 0, 69, 77, 0, // Skip to: 86948 -/* 67167 */ MCD_OPC_Decode, 225, 19, 221, 2, // Opcode: MLSv2i32_indexed -/* 67172 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 67194 -/* 67177 */ MCD_OPC_CheckPredicate, 3, 54, 77, 0, // Skip to: 86948 -/* 67182 */ MCD_OPC_CheckField, 10, 1, 0, 47, 77, 0, // Skip to: 86948 -/* 67189 */ MCD_OPC_Decode, 174, 32, 222, 2, // Opcode: UMLSLv2i32_indexed -/* 67194 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 67216 -/* 67199 */ MCD_OPC_CheckPredicate, 3, 32, 77, 0, // Skip to: 86948 -/* 67204 */ MCD_OPC_CheckField, 10, 1, 0, 25, 77, 0, // Skip to: 86948 -/* 67211 */ MCD_OPC_Decode, 131, 11, 223, 2, // Opcode: FMULXv2i32_indexed -/* 67216 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 67238 -/* 67221 */ MCD_OPC_CheckPredicate, 3, 10, 77, 0, // Skip to: 86948 -/* 67226 */ MCD_OPC_CheckField, 10, 1, 0, 3, 77, 0, // Skip to: 86948 -/* 67233 */ MCD_OPC_Decode, 194, 32, 224, 2, // Opcode: UMULLv2i32_indexed -/* 67238 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 67260 -/* 67243 */ MCD_OPC_CheckPredicate, 7, 244, 76, 0, // Skip to: 86948 -/* 67248 */ MCD_OPC_CheckField, 10, 1, 0, 237, 76, 0, // Skip to: 86948 -/* 67255 */ MCD_OPC_Decode, 163, 25, 221, 2, // Opcode: SQRDMLAHv2i32_indexed -/* 67260 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 67282 -/* 67265 */ MCD_OPC_CheckPredicate, 10, 222, 76, 0, // Skip to: 86948 -/* 67270 */ MCD_OPC_CheckField, 10, 1, 0, 215, 76, 0, // Skip to: 86948 -/* 67277 */ MCD_OPC_Decode, 217, 31, 221, 2, // Opcode: UDOTlanev8i8 -/* 67282 */ MCD_OPC_FilterValue, 15, 205, 76, 0, // Skip to: 86948 -/* 67287 */ MCD_OPC_CheckPredicate, 7, 200, 76, 0, // Skip to: 86948 -/* 67292 */ MCD_OPC_CheckField, 10, 1, 0, 193, 76, 0, // Skip to: 86948 -/* 67299 */ MCD_OPC_Decode, 175, 25, 221, 2, // Opcode: SQRDMLSHv2i32_indexed -/* 67304 */ MCD_OPC_FilterValue, 2, 33, 1, 0, // Skip to: 67598 -/* 67309 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 67312 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 67334 -/* 67317 */ MCD_OPC_CheckPredicate, 3, 170, 76, 0, // Skip to: 86948 -/* 67322 */ MCD_OPC_CheckField, 10, 1, 0, 163, 76, 0, // Skip to: 86948 -/* 67329 */ MCD_OPC_Decode, 193, 10, 225, 2, // Opcode: FMLAv4i32_indexed -/* 67334 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67356 -/* 67339 */ MCD_OPC_CheckPredicate, 3, 148, 76, 0, // Skip to: 86948 -/* 67344 */ MCD_OPC_CheckField, 10, 1, 0, 141, 76, 0, // Skip to: 86948 -/* 67351 */ MCD_OPC_Decode, 241, 23, 225, 2, // Opcode: SMLALv4i32_indexed -/* 67356 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 67378 -/* 67361 */ MCD_OPC_CheckPredicate, 3, 126, 76, 0, // Skip to: 86948 -/* 67366 */ MCD_OPC_CheckField, 10, 1, 0, 119, 76, 0, // Skip to: 86948 -/* 67373 */ MCD_OPC_Decode, 213, 24, 225, 2, // Opcode: SQDMLALv4i32_indexed -/* 67378 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 67400 -/* 67383 */ MCD_OPC_CheckPredicate, 3, 104, 76, 0, // Skip to: 86948 -/* 67388 */ MCD_OPC_CheckField, 10, 1, 0, 97, 76, 0, // Skip to: 86948 -/* 67395 */ MCD_OPC_Decode, 212, 10, 225, 2, // Opcode: FMLSv4i32_indexed -/* 67400 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 67422 -/* 67405 */ MCD_OPC_CheckPredicate, 3, 82, 76, 0, // Skip to: 86948 -/* 67410 */ MCD_OPC_CheckField, 10, 1, 0, 75, 76, 0, // Skip to: 86948 -/* 67417 */ MCD_OPC_Decode, 251, 23, 225, 2, // Opcode: SMLSLv4i32_indexed -/* 67422 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 67444 -/* 67427 */ MCD_OPC_CheckPredicate, 3, 60, 76, 0, // Skip to: 86948 -/* 67432 */ MCD_OPC_CheckField, 10, 1, 0, 53, 76, 0, // Skip to: 86948 -/* 67439 */ MCD_OPC_Decode, 225, 24, 225, 2, // Opcode: SQDMLSLv4i32_indexed -/* 67444 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 67466 -/* 67449 */ MCD_OPC_CheckPredicate, 3, 38, 76, 0, // Skip to: 86948 -/* 67454 */ MCD_OPC_CheckField, 10, 1, 0, 31, 76, 0, // Skip to: 86948 -/* 67461 */ MCD_OPC_Decode, 163, 20, 226, 2, // Opcode: MULv4i32_indexed -/* 67466 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 67488 -/* 67471 */ MCD_OPC_CheckPredicate, 3, 16, 76, 0, // Skip to: 86948 -/* 67476 */ MCD_OPC_CheckField, 10, 1, 0, 9, 76, 0, // Skip to: 86948 -/* 67483 */ MCD_OPC_Decode, 161, 11, 226, 2, // Opcode: FMULv4i32_indexed -/* 67488 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 67510 -/* 67493 */ MCD_OPC_CheckPredicate, 3, 250, 75, 0, // Skip to: 86948 -/* 67498 */ MCD_OPC_CheckField, 10, 1, 0, 243, 75, 0, // Skip to: 86948 -/* 67505 */ MCD_OPC_Decode, 144, 24, 226, 2, // Opcode: SMULLv4i32_indexed -/* 67510 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 67532 -/* 67515 */ MCD_OPC_CheckPredicate, 3, 228, 75, 0, // Skip to: 86948 -/* 67520 */ MCD_OPC_CheckField, 10, 1, 0, 221, 75, 0, // Skip to: 86948 -/* 67527 */ MCD_OPC_Decode, 249, 24, 226, 2, // Opcode: SQDMULLv4i32_indexed -/* 67532 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 67554 -/* 67537 */ MCD_OPC_CheckPredicate, 3, 206, 75, 0, // Skip to: 86948 -/* 67542 */ MCD_OPC_CheckField, 10, 1, 0, 199, 75, 0, // Skip to: 86948 -/* 67549 */ MCD_OPC_Decode, 238, 24, 226, 2, // Opcode: SQDMULHv4i32_indexed -/* 67554 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 67576 -/* 67559 */ MCD_OPC_CheckPredicate, 3, 184, 75, 0, // Skip to: 86948 -/* 67564 */ MCD_OPC_CheckField, 10, 1, 0, 177, 75, 0, // Skip to: 86948 -/* 67571 */ MCD_OPC_Decode, 191, 25, 226, 2, // Opcode: SQRDMULHv4i32_indexed -/* 67576 */ MCD_OPC_FilterValue, 14, 167, 75, 0, // Skip to: 86948 -/* 67581 */ MCD_OPC_CheckPredicate, 10, 162, 75, 0, // Skip to: 86948 -/* 67586 */ MCD_OPC_CheckField, 10, 1, 0, 155, 75, 0, // Skip to: 86948 -/* 67593 */ MCD_OPC_Decode, 229, 22, 225, 2, // Opcode: SDOTlanev16i8 -/* 67598 */ MCD_OPC_FilterValue, 3, 145, 75, 0, // Skip to: 86948 -/* 67603 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 67606 */ MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 67746 -/* 67611 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 67614 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 67636 -/* 67619 */ MCD_OPC_CheckPredicate, 3, 124, 75, 0, // Skip to: 86948 -/* 67624 */ MCD_OPC_CheckField, 10, 1, 0, 117, 75, 0, // Skip to: 86948 -/* 67631 */ MCD_OPC_Decode, 215, 19, 225, 2, // Opcode: MLAv4i32_indexed -/* 67636 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 67658 -/* 67641 */ MCD_OPC_CheckPredicate, 3, 102, 75, 0, // Skip to: 86948 -/* 67646 */ MCD_OPC_CheckField, 10, 1, 0, 95, 75, 0, // Skip to: 86948 -/* 67653 */ MCD_OPC_Decode, 168, 32, 225, 2, // Opcode: UMLALv4i32_indexed -/* 67658 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67680 -/* 67663 */ MCD_OPC_CheckPredicate, 3, 80, 75, 0, // Skip to: 86948 -/* 67668 */ MCD_OPC_CheckField, 10, 1, 0, 73, 75, 0, // Skip to: 86948 -/* 67675 */ MCD_OPC_Decode, 229, 19, 225, 2, // Opcode: MLSv4i32_indexed -/* 67680 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 67702 -/* 67685 */ MCD_OPC_CheckPredicate, 3, 58, 75, 0, // Skip to: 86948 -/* 67690 */ MCD_OPC_CheckField, 10, 1, 0, 51, 75, 0, // Skip to: 86948 -/* 67697 */ MCD_OPC_Decode, 178, 32, 225, 2, // Opcode: UMLSLv4i32_indexed -/* 67702 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 67724 -/* 67707 */ MCD_OPC_CheckPredicate, 3, 36, 75, 0, // Skip to: 86948 -/* 67712 */ MCD_OPC_CheckField, 10, 1, 0, 29, 75, 0, // Skip to: 86948 -/* 67719 */ MCD_OPC_Decode, 198, 32, 226, 2, // Opcode: UMULLv4i32_indexed -/* 67724 */ MCD_OPC_FilterValue, 7, 19, 75, 0, // Skip to: 86948 -/* 67729 */ MCD_OPC_CheckPredicate, 10, 14, 75, 0, // Skip to: 86948 -/* 67734 */ MCD_OPC_CheckField, 10, 1, 0, 7, 75, 0, // Skip to: 86948 -/* 67741 */ MCD_OPC_Decode, 216, 31, 225, 2, // Opcode: UDOTlanev16i8 -/* 67746 */ MCD_OPC_FilterValue, 1, 253, 74, 0, // Skip to: 86948 -/* 67751 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 67754 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 67783 -/* 67759 */ MCD_OPC_CheckPredicate, 11, 240, 74, 0, // Skip to: 86948 -/* 67764 */ MCD_OPC_CheckField, 21, 1, 0, 233, 74, 0, // Skip to: 86948 -/* 67771 */ MCD_OPC_CheckField, 10, 1, 0, 226, 74, 0, // Skip to: 86948 -/* 67778 */ MCD_OPC_Decode, 165, 7, 227, 2, // Opcode: FCMLAv4f32_indexed -/* 67783 */ MCD_OPC_FilterValue, 1, 216, 74, 0, // Skip to: 86948 -/* 67788 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 67791 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 67813 -/* 67796 */ MCD_OPC_CheckPredicate, 3, 203, 74, 0, // Skip to: 86948 -/* 67801 */ MCD_OPC_CheckField, 10, 1, 0, 196, 74, 0, // Skip to: 86948 -/* 67808 */ MCD_OPC_Decode, 136, 11, 226, 2, // Opcode: FMULXv4i32_indexed -/* 67813 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67835 -/* 67818 */ MCD_OPC_CheckPredicate, 7, 181, 74, 0, // Skip to: 86948 -/* 67823 */ MCD_OPC_CheckField, 10, 1, 0, 174, 74, 0, // Skip to: 86948 -/* 67830 */ MCD_OPC_Decode, 167, 25, 225, 2, // Opcode: SQRDMLAHv4i32_indexed -/* 67835 */ MCD_OPC_FilterValue, 3, 164, 74, 0, // Skip to: 86948 -/* 67840 */ MCD_OPC_CheckPredicate, 7, 159, 74, 0, // Skip to: 86948 -/* 67845 */ MCD_OPC_CheckField, 10, 1, 0, 152, 74, 0, // Skip to: 86948 -/* 67852 */ MCD_OPC_Decode, 179, 25, 225, 2, // Opcode: SQRDMLSHv4i32_indexed -/* 67857 */ MCD_OPC_FilterValue, 15, 142, 74, 0, // Skip to: 86948 -/* 67862 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 67865 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 67901 -/* 67870 */ MCD_OPC_CheckPredicate, 3, 129, 74, 0, // Skip to: 86948 -/* 67875 */ MCD_OPC_CheckField, 29, 3, 2, 122, 74, 0, // Skip to: 86948 -/* 67882 */ MCD_OPC_CheckField, 21, 1, 0, 115, 74, 0, // Skip to: 86948 -/* 67889 */ MCD_OPC_CheckField, 10, 1, 0, 108, 74, 0, // Skip to: 86948 -/* 67896 */ MCD_OPC_Decode, 189, 10, 228, 2, // Opcode: FMLAv2i64_indexed -/* 67901 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 67937 -/* 67906 */ MCD_OPC_CheckPredicate, 3, 93, 74, 0, // Skip to: 86948 -/* 67911 */ MCD_OPC_CheckField, 29, 3, 2, 86, 74, 0, // Skip to: 86948 -/* 67918 */ MCD_OPC_CheckField, 21, 1, 0, 79, 74, 0, // Skip to: 86948 -/* 67925 */ MCD_OPC_CheckField, 10, 1, 0, 72, 74, 0, // Skip to: 86948 -/* 67932 */ MCD_OPC_Decode, 208, 10, 228, 2, // Opcode: FMLSv2i64_indexed -/* 67937 */ MCD_OPC_FilterValue, 9, 62, 74, 0, // Skip to: 86948 -/* 67942 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 67945 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 67974 -/* 67950 */ MCD_OPC_CheckPredicate, 3, 49, 74, 0, // Skip to: 86948 -/* 67955 */ MCD_OPC_CheckField, 21, 1, 0, 42, 74, 0, // Skip to: 86948 -/* 67962 */ MCD_OPC_CheckField, 10, 1, 0, 35, 74, 0, // Skip to: 86948 -/* 67969 */ MCD_OPC_Decode, 157, 11, 229, 2, // Opcode: FMULv2i64_indexed -/* 67974 */ MCD_OPC_FilterValue, 3, 25, 74, 0, // Skip to: 86948 -/* 67979 */ MCD_OPC_CheckPredicate, 3, 20, 74, 0, // Skip to: 86948 -/* 67984 */ MCD_OPC_CheckField, 21, 1, 0, 13, 74, 0, // Skip to: 86948 -/* 67991 */ MCD_OPC_CheckField, 10, 1, 0, 6, 74, 0, // Skip to: 86948 -/* 67998 */ MCD_OPC_Decode, 132, 11, 229, 2, // Opcode: FMULXv2i64_indexed -/* 68003 */ MCD_OPC_FilterValue, 4, 5, 2, 0, // Skip to: 68525 -/* 68008 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 68011 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 68039 -/* 68016 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ... -/* 68019 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68029 -/* 68024 */ MCD_OPC_Decode, 204, 1, 230, 2, // Opcode: ADR -/* 68029 */ MCD_OPC_FilterValue, 1, 226, 73, 0, // Skip to: 86948 -/* 68034 */ MCD_OPC_Decode, 205, 1, 230, 2, // Opcode: ADRP -/* 68039 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 68127 -/* 68044 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 68047 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68057 -/* 68052 */ MCD_OPC_Decode, 172, 1, 231, 2, // Opcode: ADDWri -/* 68057 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68067 -/* 68062 */ MCD_OPC_Decode, 157, 1, 231, 2, // Opcode: ADDSWri -/* 68067 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68077 -/* 68072 */ MCD_OPC_Decode, 234, 29, 231, 2, // Opcode: SUBWri -/* 68077 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 68087 -/* 68082 */ MCD_OPC_Decode, 225, 29, 231, 2, // Opcode: SUBSWri -/* 68087 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 68097 -/* 68092 */ MCD_OPC_Decode, 176, 1, 231, 2, // Opcode: ADDXri -/* 68097 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 68107 -/* 68102 */ MCD_OPC_Decode, 161, 1, 231, 2, // Opcode: ADDSXri -/* 68107 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 68117 -/* 68112 */ MCD_OPC_Decode, 238, 29, 231, 2, // Opcode: SUBXri -/* 68117 */ MCD_OPC_FilterValue, 7, 138, 73, 0, // Skip to: 86948 -/* 68122 */ MCD_OPC_Decode, 229, 29, 231, 2, // Opcode: SUBSXri -/* 68127 */ MCD_OPC_FilterValue, 2, 226, 0, 0, // Skip to: 68358 -/* 68132 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 68135 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 68170 -/* 68140 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 68143 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68160 -/* 68148 */ MCD_OPC_CheckField, 22, 1, 0, 105, 73, 0, // Skip to: 86948 -/* 68155 */ MCD_OPC_Decode, 239, 1, 232, 2, // Opcode: ANDWri -/* 68160 */ MCD_OPC_FilterValue, 1, 95, 73, 0, // Skip to: 86948 -/* 68165 */ MCD_OPC_Decode, 245, 19, 233, 2, // Opcode: MOVNWi -/* 68170 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 68187 -/* 68175 */ MCD_OPC_CheckField, 22, 2, 0, 78, 73, 0, // Skip to: 86948 -/* 68182 */ MCD_OPC_Decode, 204, 20, 232, 2, // Opcode: ORRWri -/* 68187 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 68222 -/* 68192 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 68195 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68212 -/* 68200 */ MCD_OPC_CheckField, 22, 1, 0, 53, 73, 0, // Skip to: 86948 -/* 68207 */ MCD_OPC_Decode, 232, 5, 232, 2, // Opcode: EORWri -/* 68212 */ MCD_OPC_FilterValue, 1, 43, 73, 0, // Skip to: 86948 -/* 68217 */ MCD_OPC_Decode, 128, 20, 233, 2, // Opcode: MOVZWi -/* 68222 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 68257 -/* 68227 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 68230 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68247 -/* 68235 */ MCD_OPC_CheckField, 22, 1, 0, 18, 73, 0, // Skip to: 86948 -/* 68242 */ MCD_OPC_Decode, 228, 1, 232, 2, // Opcode: ANDSWri -/* 68247 */ MCD_OPC_FilterValue, 1, 8, 73, 0, // Skip to: 86948 -/* 68252 */ MCD_OPC_Decode, 243, 19, 233, 2, // Opcode: MOVKWi -/* 68257 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 68285 -/* 68262 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 68265 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68275 -/* 68270 */ MCD_OPC_Decode, 242, 1, 232, 2, // Opcode: ANDXri -/* 68275 */ MCD_OPC_FilterValue, 1, 236, 72, 0, // Skip to: 86948 -/* 68280 */ MCD_OPC_Decode, 246, 19, 233, 2, // Opcode: MOVNXi -/* 68285 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 68302 -/* 68290 */ MCD_OPC_CheckField, 23, 1, 0, 219, 72, 0, // Skip to: 86948 -/* 68297 */ MCD_OPC_Decode, 207, 20, 232, 2, // Opcode: ORRXri -/* 68302 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 68330 -/* 68307 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 68310 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68320 -/* 68315 */ MCD_OPC_Decode, 235, 5, 232, 2, // Opcode: EORXri -/* 68320 */ MCD_OPC_FilterValue, 1, 191, 72, 0, // Skip to: 86948 -/* 68325 */ MCD_OPC_Decode, 129, 20, 233, 2, // Opcode: MOVZXi -/* 68330 */ MCD_OPC_FilterValue, 7, 181, 72, 0, // Skip to: 86948 -/* 68335 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 68338 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68348 -/* 68343 */ MCD_OPC_Decode, 231, 1, 232, 2, // Opcode: ANDSXri -/* 68348 */ MCD_OPC_FilterValue, 1, 163, 72, 0, // Skip to: 86948 -/* 68353 */ MCD_OPC_Decode, 244, 19, 233, 2, // Opcode: MOVKXi -/* 68358 */ MCD_OPC_FilterValue, 3, 153, 72, 0, // Skip to: 86948 -/* 68363 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 68366 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 68408 -/* 68371 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 68374 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68391 -/* 68379 */ MCD_OPC_CheckField, 15, 1, 0, 130, 72, 0, // Skip to: 86948 -/* 68386 */ MCD_OPC_Decode, 182, 22, 234, 2, // Opcode: SBFMWri -/* 68391 */ MCD_OPC_FilterValue, 4, 120, 72, 0, // Skip to: 86948 -/* 68396 */ MCD_OPC_CheckField, 15, 1, 0, 113, 72, 0, // Skip to: 86948 -/* 68403 */ MCD_OPC_Decode, 250, 5, 235, 2, // Opcode: EXTRWrri -/* 68408 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 68432 -/* 68413 */ MCD_OPC_CheckField, 21, 3, 0, 96, 72, 0, // Skip to: 86948 -/* 68420 */ MCD_OPC_CheckField, 15, 1, 0, 89, 72, 0, // Skip to: 86948 -/* 68427 */ MCD_OPC_Decode, 170, 2, 236, 2, // Opcode: BFMWri -/* 68432 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 68456 -/* 68437 */ MCD_OPC_CheckField, 21, 3, 0, 72, 72, 0, // Skip to: 86948 -/* 68444 */ MCD_OPC_CheckField, 15, 1, 0, 65, 72, 0, // Skip to: 86948 -/* 68451 */ MCD_OPC_Decode, 169, 31, 234, 2, // Opcode: UBFMWri -/* 68456 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 68491 -/* 68461 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 68464 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68474 -/* 68469 */ MCD_OPC_Decode, 183, 22, 237, 2, // Opcode: SBFMXri -/* 68474 */ MCD_OPC_FilterValue, 3, 37, 72, 0, // Skip to: 86948 -/* 68479 */ MCD_OPC_CheckField, 21, 1, 0, 30, 72, 0, // Skip to: 86948 -/* 68486 */ MCD_OPC_Decode, 251, 5, 238, 2, // Opcode: EXTRXrri -/* 68491 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 68508 -/* 68496 */ MCD_OPC_CheckField, 22, 2, 1, 13, 72, 0, // Skip to: 86948 -/* 68503 */ MCD_OPC_Decode, 171, 2, 239, 2, // Opcode: BFMXri -/* 68508 */ MCD_OPC_FilterValue, 6, 3, 72, 0, // Skip to: 86948 -/* 68513 */ MCD_OPC_CheckField, 22, 2, 1, 252, 71, 0, // Skip to: 86948 -/* 68520 */ MCD_OPC_Decode, 170, 31, 237, 2, // Opcode: UBFMXri -/* 68525 */ MCD_OPC_FilterValue, 5, 218, 3, 0, // Skip to: 69516 -/* 68530 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 68533 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68543 -/* 68538 */ MCD_OPC_Decode, 168, 2, 240, 2, // Opcode: B -/* 68543 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 68591 -/* 68548 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 68551 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68561 -/* 68556 */ MCD_OPC_Decode, 250, 2, 241, 2, // Opcode: CBZW -/* 68561 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68571 -/* 68566 */ MCD_OPC_Decode, 248, 2, 241, 2, // Opcode: CBNZW -/* 68571 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68581 -/* 68576 */ MCD_OPC_Decode, 199, 30, 242, 2, // Opcode: TBZW -/* 68581 */ MCD_OPC_FilterValue, 3, 186, 71, 0, // Skip to: 86948 -/* 68586 */ MCD_OPC_Decode, 189, 30, 242, 2, // Opcode: TBNZW -/* 68591 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 68615 -/* 68596 */ MCD_OPC_CheckField, 24, 2, 0, 169, 71, 0, // Skip to: 86948 -/* 68603 */ MCD_OPC_CheckField, 4, 1, 0, 162, 71, 0, // Skip to: 86948 -/* 68610 */ MCD_OPC_Decode, 223, 2, 243, 2, // Opcode: Bcc -/* 68615 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 68625 -/* 68620 */ MCD_OPC_Decode, 197, 2, 240, 2, // Opcode: BL -/* 68625 */ MCD_OPC_FilterValue, 5, 43, 0, 0, // Skip to: 68673 -/* 68630 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 68633 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68643 -/* 68638 */ MCD_OPC_Decode, 251, 2, 244, 2, // Opcode: CBZX -/* 68643 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68653 -/* 68648 */ MCD_OPC_Decode, 249, 2, 244, 2, // Opcode: CBNZX -/* 68653 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68663 -/* 68658 */ MCD_OPC_Decode, 200, 30, 242, 2, // Opcode: TBZX -/* 68663 */ MCD_OPC_FilterValue, 3, 104, 71, 0, // Skip to: 86948 -/* 68668 */ MCD_OPC_Decode, 190, 30, 242, 2, // Opcode: TBNZX -/* 68673 */ MCD_OPC_FilterValue, 6, 94, 71, 0, // Skip to: 86948 -/* 68678 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 68681 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 68719 -/* 68686 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 68689 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68699 -/* 68694 */ MCD_OPC_Decode, 152, 30, 245, 2, // Opcode: SVC -/* 68699 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68709 -/* 68704 */ MCD_OPC_Decode, 243, 13, 245, 2, // Opcode: HVC -/* 68709 */ MCD_OPC_FilterValue, 3, 58, 71, 0, // Skip to: 86948 -/* 68714 */ MCD_OPC_Decode, 206, 23, 245, 2, // Opcode: SMC -/* 68719 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 68736 -/* 68724 */ MCD_OPC_CheckField, 0, 5, 0, 41, 71, 0, // Skip to: 86948 -/* 68731 */ MCD_OPC_Decode, 208, 2, 245, 2, // Opcode: BRK -/* 68736 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 68753 -/* 68741 */ MCD_OPC_CheckField, 0, 5, 0, 24, 71, 0, // Skip to: 86948 -/* 68748 */ MCD_OPC_Decode, 242, 13, 245, 2, // Opcode: HLT -/* 68753 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 68791 -/* 68758 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 68761 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68771 -/* 68766 */ MCD_OPC_Decode, 174, 5, 245, 2, // Opcode: DCPS1 -/* 68771 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68781 -/* 68776 */ MCD_OPC_Decode, 175, 5, 245, 2, // Opcode: DCPS2 -/* 68781 */ MCD_OPC_FilterValue, 3, 242, 70, 0, // Skip to: 86948 -/* 68786 */ MCD_OPC_Decode, 176, 5, 245, 2, // Opcode: DCPS3 -/* 68791 */ MCD_OPC_FilterValue, 8, 77, 1, 0, // Skip to: 69129 -/* 68796 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... -/* 68799 */ MCD_OPC_FilterValue, 159, 128, 1, 9, 0, 0, // Skip to: 68815 -/* 68806 */ MCD_OPC_CheckPredicate, 12, 163, 0, 0, // Skip to: 68974 -/* 68811 */ MCD_OPC_Decode, 132, 3, 97, // Opcode: CFINV -/* 68815 */ MCD_OPC_FilterValue, 255, 193, 12, 4, 0, 0, // Skip to: 68826 -/* 68822 */ MCD_OPC_Decode, 254, 34, 97, // Opcode: XPACLRI -/* 68826 */ MCD_OPC_FilterValue, 159, 194, 12, 4, 0, 0, // Skip to: 68837 -/* 68833 */ MCD_OPC_Decode, 233, 20, 97, // Opcode: PACIA1716 -/* 68837 */ MCD_OPC_FilterValue, 223, 194, 12, 4, 0, 0, // Skip to: 68848 -/* 68844 */ MCD_OPC_Decode, 237, 20, 97, // Opcode: PACIB1716 -/* 68848 */ MCD_OPC_FilterValue, 159, 195, 12, 4, 0, 0, // Skip to: 68859 -/* 68855 */ MCD_OPC_Decode, 159, 2, 97, // Opcode: AUTIA1716 -/* 68859 */ MCD_OPC_FilterValue, 223, 195, 12, 4, 0, 0, // Skip to: 68870 -/* 68866 */ MCD_OPC_Decode, 163, 2, 97, // Opcode: AUTIB1716 -/* 68870 */ MCD_OPC_FilterValue, 223, 196, 12, 9, 0, 0, // Skip to: 68886 -/* 68877 */ MCD_OPC_CheckPredicate, 12, 92, 0, 0, // Skip to: 68974 -/* 68882 */ MCD_OPC_Decode, 235, 30, 97, // Opcode: TSB -/* 68886 */ MCD_OPC_FilterValue, 159, 198, 12, 4, 0, 0, // Skip to: 68897 -/* 68893 */ MCD_OPC_Decode, 235, 20, 97, // Opcode: PACIAZ -/* 68897 */ MCD_OPC_FilterValue, 191, 198, 12, 4, 0, 0, // Skip to: 68908 -/* 68904 */ MCD_OPC_Decode, 234, 20, 97, // Opcode: PACIASP -/* 68908 */ MCD_OPC_FilterValue, 223, 198, 12, 4, 0, 0, // Skip to: 68919 -/* 68915 */ MCD_OPC_Decode, 239, 20, 97, // Opcode: PACIBZ -/* 68919 */ MCD_OPC_FilterValue, 255, 198, 12, 4, 0, 0, // Skip to: 68930 -/* 68926 */ MCD_OPC_Decode, 238, 20, 97, // Opcode: PACIBSP -/* 68930 */ MCD_OPC_FilterValue, 159, 199, 12, 4, 0, 0, // Skip to: 68941 -/* 68937 */ MCD_OPC_Decode, 161, 2, 97, // Opcode: AUTIAZ -/* 68941 */ MCD_OPC_FilterValue, 191, 199, 12, 4, 0, 0, // Skip to: 68952 -/* 68948 */ MCD_OPC_Decode, 160, 2, 97, // Opcode: AUTIASP -/* 68952 */ MCD_OPC_FilterValue, 223, 199, 12, 4, 0, 0, // Skip to: 68963 -/* 68959 */ MCD_OPC_Decode, 165, 2, 97, // Opcode: AUTIBZ -/* 68963 */ MCD_OPC_FilterValue, 255, 199, 12, 4, 0, 0, // Skip to: 68974 -/* 68970 */ MCD_OPC_Decode, 164, 2, 97, // Opcode: AUTIBSP -/* 68974 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 68977 */ MCD_OPC_FilterValue, 95, 12, 0, 0, // Skip to: 68994 -/* 68982 */ MCD_OPC_CheckField, 12, 9, 51, 59, 0, 0, // Skip to: 69048 -/* 68989 */ MCD_OPC_Decode, 157, 3, 246, 2, // Opcode: CLREX -/* 68994 */ MCD_OPC_FilterValue, 159, 1, 12, 0, 0, // Skip to: 69012 -/* 69000 */ MCD_OPC_CheckField, 12, 9, 51, 41, 0, 0, // Skip to: 69048 -/* 69007 */ MCD_OPC_Decode, 193, 5, 246, 2, // Opcode: DSB -/* 69012 */ MCD_OPC_FilterValue, 191, 1, 12, 0, 0, // Skip to: 69030 -/* 69018 */ MCD_OPC_CheckField, 12, 9, 51, 23, 0, 0, // Skip to: 69048 -/* 69025 */ MCD_OPC_Decode, 191, 5, 246, 2, // Opcode: DMB -/* 69030 */ MCD_OPC_FilterValue, 223, 1, 12, 0, 0, // Skip to: 69048 -/* 69036 */ MCD_OPC_CheckField, 12, 9, 51, 5, 0, 0, // Skip to: 69048 -/* 69043 */ MCD_OPC_Decode, 162, 14, 246, 2, // Opcode: ISB -/* 69048 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 69051 */ MCD_OPC_FilterValue, 31, 56, 0, 0, // Skip to: 69112 -/* 69056 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 69059 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 69076 -/* 69064 */ MCD_OPC_CheckField, 16, 5, 3, 41, 0, 0, // Skip to: 69112 -/* 69071 */ MCD_OPC_Decode, 241, 13, 247, 2, // Opcode: HINT -/* 69076 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 69112 -/* 69081 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... -/* 69084 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 69112 -/* 69089 */ MCD_OPC_CheckField, 9, 3, 0, 8, 0, 0, // Skip to: 69104 -/* 69096 */ MCD_OPC_TryDecode, 145, 20, 248, 2, 0, 0, 0, // Opcode: MSRpstateImm1, skip to: 69104 -/* 69104 */ MCD_OPC_TryDecode, 146, 20, 248, 2, 0, 0, 0, // Opcode: MSRpstateImm4, skip to: 69112 -/* 69112 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, 0, // Skip to: 69124 -/* 69119 */ MCD_OPC_Decode, 176, 30, 249, 2, // Opcode: SYSxt -/* 69124 */ MCD_OPC_Decode, 144, 20, 250, 2, // Opcode: MSR -/* 69129 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 69151 -/* 69134 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, 0, // Skip to: 69146 -/* 69141 */ MCD_OPC_Decode, 175, 30, 251, 2, // Opcode: SYSLxt -/* 69146 */ MCD_OPC_Decode, 139, 20, 252, 2, // Opcode: MRS -/* 69151 */ MCD_OPC_FilterValue, 16, 67, 0, 0, // Skip to: 69223 -/* 69156 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... -/* 69159 */ MCD_OPC_FilterValue, 192, 15, 12, 0, 0, // Skip to: 69177 -/* 69165 */ MCD_OPC_CheckField, 0, 5, 0, 112, 69, 0, // Skip to: 86948 -/* 69172 */ MCD_OPC_Decode, 203, 2, 253, 2, // Opcode: BR -/* 69177 */ MCD_OPC_FilterValue, 194, 15, 17, 0, 0, // Skip to: 69200 -/* 69183 */ MCD_OPC_CheckPredicate, 13, 96, 69, 0, // Skip to: 86948 -/* 69188 */ MCD_OPC_CheckField, 0, 5, 31, 89, 69, 0, // Skip to: 86948 -/* 69195 */ MCD_OPC_Decode, 205, 2, 253, 2, // Opcode: BRAAZ -/* 69200 */ MCD_OPC_FilterValue, 195, 15, 78, 69, 0, // Skip to: 86948 -/* 69206 */ MCD_OPC_CheckPredicate, 13, 73, 69, 0, // Skip to: 86948 -/* 69211 */ MCD_OPC_CheckField, 0, 5, 31, 66, 69, 0, // Skip to: 86948 -/* 69218 */ MCD_OPC_Decode, 207, 2, 253, 2, // Opcode: BRABZ -/* 69223 */ MCD_OPC_FilterValue, 17, 67, 0, 0, // Skip to: 69295 -/* 69228 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... -/* 69231 */ MCD_OPC_FilterValue, 192, 15, 12, 0, 0, // Skip to: 69249 -/* 69237 */ MCD_OPC_CheckField, 0, 5, 0, 40, 69, 0, // Skip to: 86948 -/* 69244 */ MCD_OPC_Decode, 198, 2, 253, 2, // Opcode: BLR -/* 69249 */ MCD_OPC_FilterValue, 194, 15, 17, 0, 0, // Skip to: 69272 -/* 69255 */ MCD_OPC_CheckPredicate, 13, 24, 69, 0, // Skip to: 86948 -/* 69260 */ MCD_OPC_CheckField, 0, 5, 31, 17, 69, 0, // Skip to: 86948 -/* 69267 */ MCD_OPC_Decode, 200, 2, 253, 2, // Opcode: BLRAAZ -/* 69272 */ MCD_OPC_FilterValue, 195, 15, 6, 69, 0, // Skip to: 86948 -/* 69278 */ MCD_OPC_CheckPredicate, 13, 1, 69, 0, // Skip to: 86948 -/* 69283 */ MCD_OPC_CheckField, 0, 5, 31, 250, 68, 0, // Skip to: 86948 -/* 69290 */ MCD_OPC_Decode, 202, 2, 253, 2, // Opcode: BLRABZ -/* 69295 */ MCD_OPC_FilterValue, 18, 67, 0, 0, // Skip to: 69367 -/* 69300 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... -/* 69303 */ MCD_OPC_FilterValue, 192, 15, 12, 0, 0, // Skip to: 69321 -/* 69309 */ MCD_OPC_CheckField, 0, 5, 0, 224, 68, 0, // Skip to: 86948 -/* 69316 */ MCD_OPC_Decode, 196, 21, 253, 2, // Opcode: RET -/* 69321 */ MCD_OPC_FilterValue, 194, 15, 17, 0, 0, // Skip to: 69344 -/* 69327 */ MCD_OPC_CheckPredicate, 13, 208, 68, 0, // Skip to: 86948 -/* 69332 */ MCD_OPC_CheckField, 0, 10, 255, 7, 200, 68, 0, // Skip to: 86948 -/* 69340 */ MCD_OPC_Decode, 197, 21, 97, // Opcode: RETAA -/* 69344 */ MCD_OPC_FilterValue, 195, 15, 190, 68, 0, // Skip to: 86948 -/* 69350 */ MCD_OPC_CheckPredicate, 13, 185, 68, 0, // Skip to: 86948 -/* 69355 */ MCD_OPC_CheckField, 0, 10, 255, 7, 177, 68, 0, // Skip to: 86948 -/* 69363 */ MCD_OPC_Decode, 198, 21, 97, // Opcode: RETAB -/* 69367 */ MCD_OPC_FilterValue, 20, 46, 0, 0, // Skip to: 69418 -/* 69372 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... -/* 69375 */ MCD_OPC_FilterValue, 224, 135, 124, 4, 0, 0, // Skip to: 69386 -/* 69382 */ MCD_OPC_Decode, 247, 5, 97, // Opcode: ERET -/* 69386 */ MCD_OPC_FilterValue, 255, 151, 124, 9, 0, 0, // Skip to: 69402 -/* 69393 */ MCD_OPC_CheckPredicate, 13, 142, 68, 0, // Skip to: 86948 -/* 69398 */ MCD_OPC_Decode, 248, 5, 97, // Opcode: ERETAA -/* 69402 */ MCD_OPC_FilterValue, 255, 159, 124, 131, 68, 0, // Skip to: 86948 -/* 69409 */ MCD_OPC_CheckPredicate, 13, 126, 68, 0, // Skip to: 86948 -/* 69414 */ MCD_OPC_Decode, 249, 5, 97, // Opcode: ERETAB -/* 69418 */ MCD_OPC_FilterValue, 21, 13, 0, 0, // Skip to: 69436 -/* 69423 */ MCD_OPC_CheckField, 0, 21, 224, 135, 124, 108, 68, 0, // Skip to: 86948 -/* 69432 */ MCD_OPC_Decode, 192, 5, 97, // Opcode: DRPS -/* 69436 */ MCD_OPC_FilterValue, 24, 35, 0, 0, // Skip to: 69476 -/* 69441 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... -/* 69444 */ MCD_OPC_FilterValue, 194, 15, 10, 0, 0, // Skip to: 69460 -/* 69450 */ MCD_OPC_CheckPredicate, 13, 85, 68, 0, // Skip to: 86948 -/* 69455 */ MCD_OPC_Decode, 204, 2, 254, 2, // Opcode: BRAA -/* 69460 */ MCD_OPC_FilterValue, 195, 15, 74, 68, 0, // Skip to: 86948 -/* 69466 */ MCD_OPC_CheckPredicate, 13, 69, 68, 0, // Skip to: 86948 -/* 69471 */ MCD_OPC_Decode, 206, 2, 254, 2, // Opcode: BRAB -/* 69476 */ MCD_OPC_FilterValue, 25, 59, 68, 0, // Skip to: 86948 -/* 69481 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... -/* 69484 */ MCD_OPC_FilterValue, 194, 15, 10, 0, 0, // Skip to: 69500 -/* 69490 */ MCD_OPC_CheckPredicate, 13, 45, 68, 0, // Skip to: 86948 -/* 69495 */ MCD_OPC_Decode, 199, 2, 254, 2, // Opcode: BLRAA -/* 69500 */ MCD_OPC_FilterValue, 195, 15, 34, 68, 0, // Skip to: 86948 -/* 69506 */ MCD_OPC_CheckPredicate, 13, 29, 68, 0, // Skip to: 86948 -/* 69511 */ MCD_OPC_Decode, 201, 2, 254, 2, // Opcode: BLRAB -/* 69516 */ MCD_OPC_FilterValue, 6, 115, 24, 0, // Skip to: 75780 -/* 69521 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 69524 */ MCD_OPC_FilterValue, 0, 180, 1, 0, // Skip to: 69965 -/* 69529 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 69532 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 69542 -/* 69537 */ MCD_OPC_Decode, 155, 18, 241, 2, // Opcode: LDRWl -/* 69542 */ MCD_OPC_FilterValue, 1, 91, 0, 0, // Skip to: 69638 -/* 69547 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 69550 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 69572 -/* 69555 */ MCD_OPC_CheckPredicate, 12, 236, 67, 0, // Skip to: 86948 -/* 69560 */ MCD_OPC_CheckField, 10, 2, 0, 229, 67, 0, // Skip to: 86948 -/* 69567 */ MCD_OPC_Decode, 235, 28, 255, 2, // Opcode: STLURBi -/* 69572 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 69594 -/* 69577 */ MCD_OPC_CheckPredicate, 12, 214, 67, 0, // Skip to: 86948 -/* 69582 */ MCD_OPC_CheckField, 10, 2, 0, 207, 67, 0, // Skip to: 86948 -/* 69589 */ MCD_OPC_Decode, 225, 16, 255, 2, // Opcode: LDAPURBi -/* 69594 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 69616 -/* 69599 */ MCD_OPC_CheckPredicate, 12, 192, 67, 0, // Skip to: 86948 -/* 69604 */ MCD_OPC_CheckField, 10, 2, 0, 185, 67, 0, // Skip to: 86948 -/* 69611 */ MCD_OPC_Decode, 228, 16, 255, 2, // Opcode: LDAPURSBXi -/* 69616 */ MCD_OPC_FilterValue, 6, 175, 67, 0, // Skip to: 86948 -/* 69621 */ MCD_OPC_CheckPredicate, 12, 170, 67, 0, // Skip to: 86948 -/* 69626 */ MCD_OPC_CheckField, 10, 2, 0, 163, 67, 0, // Skip to: 86948 -/* 69633 */ MCD_OPC_Decode, 227, 16, 255, 2, // Opcode: LDAPURSBWi -/* 69638 */ MCD_OPC_FilterValue, 2, 24, 1, 0, // Skip to: 69923 -/* 69643 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 69646 */ MCD_OPC_FilterValue, 0, 78, 0, 0, // Skip to: 69729 -/* 69651 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 69654 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69671 -/* 69659 */ MCD_OPC_CheckField, 12, 4, 0, 130, 67, 0, // Skip to: 86948 -/* 69666 */ MCD_OPC_Decode, 140, 1, 128, 3, // Opcode: ADCWr -/* 69671 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 69681 -/* 69676 */ MCD_OPC_Decode, 161, 5, 129, 3, // Opcode: CSELWr -/* 69681 */ MCD_OPC_FilterValue, 6, 110, 67, 0, // Skip to: 86948 -/* 69686 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 69689 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 69699 -/* 69694 */ MCD_OPC_Decode, 155, 19, 128, 3, // Opcode: LSLVWr -/* 69699 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 69714 -/* 69704 */ MCD_OPC_CheckPredicate, 14, 87, 67, 0, // Skip to: 86948 -/* 69709 */ MCD_OPC_Decode, 153, 5, 128, 3, // Opcode: CRC32Brr -/* 69714 */ MCD_OPC_FilterValue, 5, 77, 67, 0, // Skip to: 86948 -/* 69719 */ MCD_OPC_CheckPredicate, 14, 72, 67, 0, // Skip to: 86948 -/* 69724 */ MCD_OPC_Decode, 154, 5, 128, 3, // Opcode: CRC32CBrr -/* 69729 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 69795 -/* 69734 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 69737 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 69747 -/* 69742 */ MCD_OPC_Decode, 163, 5, 129, 3, // Opcode: CSINCWr -/* 69747 */ MCD_OPC_FilterValue, 6, 44, 67, 0, // Skip to: 86948 -/* 69752 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 69755 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 69765 -/* 69760 */ MCD_OPC_Decode, 179, 19, 128, 3, // Opcode: LSRVWr -/* 69765 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 69780 -/* 69770 */ MCD_OPC_CheckPredicate, 14, 21, 67, 0, // Skip to: 86948 -/* 69775 */ MCD_OPC_Decode, 158, 5, 128, 3, // Opcode: CRC32Hrr -/* 69780 */ MCD_OPC_FilterValue, 5, 11, 67, 0, // Skip to: 86948 -/* 69785 */ MCD_OPC_CheckPredicate, 14, 6, 67, 0, // Skip to: 86948 -/* 69790 */ MCD_OPC_Decode, 155, 5, 128, 3, // Opcode: CRC32CHrr -/* 69795 */ MCD_OPC_FilterValue, 2, 81, 0, 0, // Skip to: 69881 -/* 69800 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 69803 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69820 -/* 69808 */ MCD_OPC_CheckField, 21, 3, 6, 237, 66, 0, // Skip to: 86948 -/* 69815 */ MCD_OPC_Decode, 208, 31, 128, 3, // Opcode: UDIVWr -/* 69820 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 69837 -/* 69825 */ MCD_OPC_CheckField, 21, 3, 6, 220, 66, 0, // Skip to: 86948 -/* 69832 */ MCD_OPC_Decode, 134, 2, 128, 3, // Opcode: ASRVWr -/* 69837 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 69859 -/* 69842 */ MCD_OPC_CheckPredicate, 14, 205, 66, 0, // Skip to: 86948 -/* 69847 */ MCD_OPC_CheckField, 21, 3, 6, 198, 66, 0, // Skip to: 86948 -/* 69854 */ MCD_OPC_Decode, 159, 5, 128, 3, // Opcode: CRC32Wrr -/* 69859 */ MCD_OPC_FilterValue, 5, 188, 66, 0, // Skip to: 86948 -/* 69864 */ MCD_OPC_CheckPredicate, 14, 183, 66, 0, // Skip to: 86948 -/* 69869 */ MCD_OPC_CheckField, 21, 3, 6, 176, 66, 0, // Skip to: 86948 -/* 69876 */ MCD_OPC_Decode, 156, 5, 128, 3, // Opcode: CRC32CWrr -/* 69881 */ MCD_OPC_FilterValue, 3, 166, 66, 0, // Skip to: 86948 -/* 69886 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 69889 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69906 -/* 69894 */ MCD_OPC_CheckField, 21, 3, 6, 151, 66, 0, // Skip to: 86948 -/* 69901 */ MCD_OPC_Decode, 221, 22, 128, 3, // Opcode: SDIVWr -/* 69906 */ MCD_OPC_FilterValue, 2, 141, 66, 0, // Skip to: 86948 -/* 69911 */ MCD_OPC_CheckField, 21, 3, 6, 134, 66, 0, // Skip to: 86948 -/* 69918 */ MCD_OPC_Decode, 232, 21, 128, 3, // Opcode: RORVWr -/* 69923 */ MCD_OPC_FilterValue, 3, 124, 66, 0, // Skip to: 86948 -/* 69928 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 69931 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69948 -/* 69936 */ MCD_OPC_CheckField, 21, 3, 0, 109, 66, 0, // Skip to: 86948 -/* 69943 */ MCD_OPC_Decode, 199, 19, 130, 3, // Opcode: MADDWrrr -/* 69948 */ MCD_OPC_FilterValue, 1, 99, 66, 0, // Skip to: 86948 -/* 69953 */ MCD_OPC_CheckField, 21, 3, 0, 92, 66, 0, // Skip to: 86948 -/* 69960 */ MCD_OPC_Decode, 147, 20, 130, 3, // Opcode: MSUBWrrr -/* 69965 */ MCD_OPC_FilterValue, 1, 176, 4, 0, // Skip to: 71170 -/* 69970 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 69973 */ MCD_OPC_FilterValue, 0, 244, 0, 0, // Skip to: 70222 -/* 69978 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 69981 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 70142 -/* 69986 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 69989 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 69999 -/* 69994 */ MCD_OPC_Decode, 196, 29, 255, 2, // Opcode: STURBBi -/* 69999 */ MCD_OPC_FilterValue, 1, 48, 66, 0, // Skip to: 86948 -/* 70004 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 70007 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70022 -/* 70012 */ MCD_OPC_CheckPredicate, 1, 35, 66, 0, // Skip to: 86948 -/* 70017 */ MCD_OPC_Decode, 213, 16, 131, 3, // Opcode: LDADDB -/* 70022 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70037 -/* 70027 */ MCD_OPC_CheckPredicate, 1, 20, 66, 0, // Skip to: 86948 -/* 70032 */ MCD_OPC_Decode, 252, 16, 131, 3, // Opcode: LDCLRB -/* 70037 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70052 -/* 70042 */ MCD_OPC_CheckPredicate, 1, 5, 66, 0, // Skip to: 86948 -/* 70047 */ MCD_OPC_Decode, 140, 17, 131, 3, // Opcode: LDEORB -/* 70052 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70067 -/* 70057 */ MCD_OPC_CheckPredicate, 1, 246, 65, 0, // Skip to: 86948 -/* 70062 */ MCD_OPC_Decode, 177, 18, 131, 3, // Opcode: LDSETB -/* 70067 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70082 -/* 70072 */ MCD_OPC_CheckPredicate, 1, 231, 65, 0, // Skip to: 86948 -/* 70077 */ MCD_OPC_Decode, 193, 18, 131, 3, // Opcode: LDSMAXB -/* 70082 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70097 -/* 70087 */ MCD_OPC_CheckPredicate, 1, 216, 65, 0, // Skip to: 86948 -/* 70092 */ MCD_OPC_Decode, 209, 18, 131, 3, // Opcode: LDSMINB -/* 70097 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70112 -/* 70102 */ MCD_OPC_CheckPredicate, 1, 201, 65, 0, // Skip to: 86948 -/* 70107 */ MCD_OPC_Decode, 234, 18, 131, 3, // Opcode: LDUMAXB -/* 70112 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70127 -/* 70117 */ MCD_OPC_CheckPredicate, 1, 186, 65, 0, // Skip to: 86948 -/* 70122 */ MCD_OPC_Decode, 250, 18, 131, 3, // Opcode: LDUMINB -/* 70127 */ MCD_OPC_FilterValue, 8, 176, 65, 0, // Skip to: 86948 -/* 70132 */ MCD_OPC_CheckPredicate, 1, 171, 65, 0, // Skip to: 86948 -/* 70137 */ MCD_OPC_Decode, 161, 30, 131, 3, // Opcode: SWPB -/* 70142 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70159 -/* 70147 */ MCD_OPC_CheckField, 21, 1, 0, 154, 65, 0, // Skip to: 86948 -/* 70154 */ MCD_OPC_Decode, 145, 29, 255, 2, // Opcode: STRBBpost -/* 70159 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70205 -/* 70164 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 70167 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70177 -/* 70172 */ MCD_OPC_Decode, 192, 29, 255, 2, // Opcode: STTRBi -/* 70177 */ MCD_OPC_FilterValue, 1, 126, 65, 0, // Skip to: 86948 -/* 70182 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 70185 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70195 -/* 70190 */ MCD_OPC_Decode, 147, 29, 132, 3, // Opcode: STRBBroW -/* 70195 */ MCD_OPC_FilterValue, 3, 108, 65, 0, // Skip to: 86948 -/* 70200 */ MCD_OPC_Decode, 148, 29, 133, 3, // Opcode: STRBBroX -/* 70205 */ MCD_OPC_FilterValue, 3, 98, 65, 0, // Skip to: 86948 -/* 70210 */ MCD_OPC_CheckField, 21, 1, 0, 91, 65, 0, // Skip to: 86948 -/* 70217 */ MCD_OPC_Decode, 146, 29, 255, 2, // Opcode: STRBBpre -/* 70222 */ MCD_OPC_FilterValue, 1, 244, 0, 0, // Skip to: 70471 -/* 70227 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 70230 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 70391 -/* 70235 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 70238 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70248 -/* 70243 */ MCD_OPC_Decode, 130, 19, 255, 2, // Opcode: LDURBBi -/* 70248 */ MCD_OPC_FilterValue, 1, 55, 65, 0, // Skip to: 86948 -/* 70253 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 70256 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70271 -/* 70261 */ MCD_OPC_CheckPredicate, 1, 42, 65, 0, // Skip to: 86948 -/* 70266 */ MCD_OPC_Decode, 215, 16, 131, 3, // Opcode: LDADDLB -/* 70271 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70286 -/* 70276 */ MCD_OPC_CheckPredicate, 1, 27, 65, 0, // Skip to: 86948 -/* 70281 */ MCD_OPC_Decode, 254, 16, 131, 3, // Opcode: LDCLRLB -/* 70286 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70301 -/* 70291 */ MCD_OPC_CheckPredicate, 1, 12, 65, 0, // Skip to: 86948 -/* 70296 */ MCD_OPC_Decode, 142, 17, 131, 3, // Opcode: LDEORLB -/* 70301 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70316 -/* 70306 */ MCD_OPC_CheckPredicate, 1, 253, 64, 0, // Skip to: 86948 -/* 70311 */ MCD_OPC_Decode, 179, 18, 131, 3, // Opcode: LDSETLB -/* 70316 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70331 -/* 70321 */ MCD_OPC_CheckPredicate, 1, 238, 64, 0, // Skip to: 86948 -/* 70326 */ MCD_OPC_Decode, 195, 18, 131, 3, // Opcode: LDSMAXLB -/* 70331 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70346 -/* 70336 */ MCD_OPC_CheckPredicate, 1, 223, 64, 0, // Skip to: 86948 -/* 70341 */ MCD_OPC_Decode, 211, 18, 131, 3, // Opcode: LDSMINLB -/* 70346 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70361 -/* 70351 */ MCD_OPC_CheckPredicate, 1, 208, 64, 0, // Skip to: 86948 -/* 70356 */ MCD_OPC_Decode, 236, 18, 131, 3, // Opcode: LDUMAXLB -/* 70361 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70376 -/* 70366 */ MCD_OPC_CheckPredicate, 1, 193, 64, 0, // Skip to: 86948 -/* 70371 */ MCD_OPC_Decode, 252, 18, 131, 3, // Opcode: LDUMINLB -/* 70376 */ MCD_OPC_FilterValue, 8, 183, 64, 0, // Skip to: 86948 -/* 70381 */ MCD_OPC_CheckPredicate, 1, 178, 64, 0, // Skip to: 86948 -/* 70386 */ MCD_OPC_Decode, 163, 30, 131, 3, // Opcode: SWPLB -/* 70391 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70408 -/* 70396 */ MCD_OPC_CheckField, 21, 1, 0, 161, 64, 0, // Skip to: 86948 -/* 70403 */ MCD_OPC_Decode, 219, 17, 255, 2, // Opcode: LDRBBpost -/* 70408 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70454 -/* 70413 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 70416 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70426 -/* 70421 */ MCD_OPC_Decode, 217, 18, 255, 2, // Opcode: LDTRBi -/* 70426 */ MCD_OPC_FilterValue, 1, 133, 64, 0, // Skip to: 86948 -/* 70431 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 70434 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70444 -/* 70439 */ MCD_OPC_Decode, 221, 17, 132, 3, // Opcode: LDRBBroW -/* 70444 */ MCD_OPC_FilterValue, 3, 115, 64, 0, // Skip to: 86948 -/* 70449 */ MCD_OPC_Decode, 222, 17, 133, 3, // Opcode: LDRBBroX -/* 70454 */ MCD_OPC_FilterValue, 3, 105, 64, 0, // Skip to: 86948 -/* 70459 */ MCD_OPC_CheckField, 21, 1, 0, 98, 64, 0, // Skip to: 86948 -/* 70466 */ MCD_OPC_Decode, 220, 17, 255, 2, // Opcode: LDRBBpre -/* 70471 */ MCD_OPC_FilterValue, 2, 10, 1, 0, // Skip to: 70742 -/* 70476 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 70479 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 70662 -/* 70484 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 70487 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70497 -/* 70492 */ MCD_OPC_Decode, 137, 19, 255, 2, // Opcode: LDURSBXi -/* 70497 */ MCD_OPC_FilterValue, 1, 62, 64, 0, // Skip to: 86948 -/* 70502 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 70505 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70520 -/* 70510 */ MCD_OPC_CheckPredicate, 1, 49, 64, 0, // Skip to: 86948 -/* 70515 */ MCD_OPC_Decode, 205, 16, 131, 3, // Opcode: LDADDAB -/* 70520 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70535 -/* 70525 */ MCD_OPC_CheckPredicate, 1, 34, 64, 0, // Skip to: 86948 -/* 70530 */ MCD_OPC_Decode, 244, 16, 131, 3, // Opcode: LDCLRAB -/* 70535 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70550 -/* 70540 */ MCD_OPC_CheckPredicate, 1, 19, 64, 0, // Skip to: 86948 -/* 70545 */ MCD_OPC_Decode, 132, 17, 131, 3, // Opcode: LDEORAB -/* 70550 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70565 -/* 70555 */ MCD_OPC_CheckPredicate, 1, 4, 64, 0, // Skip to: 86948 -/* 70560 */ MCD_OPC_Decode, 169, 18, 131, 3, // Opcode: LDSETAB -/* 70565 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70580 -/* 70570 */ MCD_OPC_CheckPredicate, 1, 245, 63, 0, // Skip to: 86948 -/* 70575 */ MCD_OPC_Decode, 185, 18, 131, 3, // Opcode: LDSMAXAB -/* 70580 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70595 -/* 70585 */ MCD_OPC_CheckPredicate, 1, 230, 63, 0, // Skip to: 86948 -/* 70590 */ MCD_OPC_Decode, 201, 18, 131, 3, // Opcode: LDSMINAB -/* 70595 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70610 -/* 70600 */ MCD_OPC_CheckPredicate, 1, 215, 63, 0, // Skip to: 86948 -/* 70605 */ MCD_OPC_Decode, 226, 18, 131, 3, // Opcode: LDUMAXAB -/* 70610 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70625 -/* 70615 */ MCD_OPC_CheckPredicate, 1, 200, 63, 0, // Skip to: 86948 -/* 70620 */ MCD_OPC_Decode, 242, 18, 131, 3, // Opcode: LDUMINAB -/* 70625 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 70640 -/* 70630 */ MCD_OPC_CheckPredicate, 1, 185, 63, 0, // Skip to: 86948 -/* 70635 */ MCD_OPC_Decode, 153, 30, 131, 3, // Opcode: SWPAB -/* 70640 */ MCD_OPC_FilterValue, 12, 175, 63, 0, // Skip to: 86948 -/* 70645 */ MCD_OPC_CheckPredicate, 15, 170, 63, 0, // Skip to: 86948 -/* 70650 */ MCD_OPC_CheckField, 16, 5, 31, 163, 63, 0, // Skip to: 86948 -/* 70657 */ MCD_OPC_Decode, 221, 16, 134, 3, // Opcode: LDAPRB -/* 70662 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70679 -/* 70667 */ MCD_OPC_CheckField, 21, 1, 0, 146, 63, 0, // Skip to: 86948 -/* 70674 */ MCD_OPC_Decode, 128, 18, 255, 2, // Opcode: LDRSBXpost -/* 70679 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70725 -/* 70684 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 70687 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70697 -/* 70692 */ MCD_OPC_Decode, 220, 18, 255, 2, // Opcode: LDTRSBXi -/* 70697 */ MCD_OPC_FilterValue, 1, 118, 63, 0, // Skip to: 86948 -/* 70702 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 70705 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70715 -/* 70710 */ MCD_OPC_Decode, 130, 18, 135, 3, // Opcode: LDRSBXroW -/* 70715 */ MCD_OPC_FilterValue, 3, 100, 63, 0, // Skip to: 86948 -/* 70720 */ MCD_OPC_Decode, 131, 18, 136, 3, // Opcode: LDRSBXroX -/* 70725 */ MCD_OPC_FilterValue, 3, 90, 63, 0, // Skip to: 86948 -/* 70730 */ MCD_OPC_CheckField, 21, 1, 0, 83, 63, 0, // Skip to: 86948 -/* 70737 */ MCD_OPC_Decode, 129, 18, 255, 2, // Opcode: LDRSBXpre -/* 70742 */ MCD_OPC_FilterValue, 3, 244, 0, 0, // Skip to: 70991 -/* 70747 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 70750 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 70911 -/* 70755 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 70758 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70768 -/* 70763 */ MCD_OPC_Decode, 136, 19, 255, 2, // Opcode: LDURSBWi -/* 70768 */ MCD_OPC_FilterValue, 1, 47, 63, 0, // Skip to: 86948 -/* 70773 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 70776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70791 -/* 70781 */ MCD_OPC_CheckPredicate, 1, 34, 63, 0, // Skip to: 86948 -/* 70786 */ MCD_OPC_Decode, 207, 16, 131, 3, // Opcode: LDADDALB -/* 70791 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70806 -/* 70796 */ MCD_OPC_CheckPredicate, 1, 19, 63, 0, // Skip to: 86948 -/* 70801 */ MCD_OPC_Decode, 246, 16, 131, 3, // Opcode: LDCLRALB -/* 70806 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70821 -/* 70811 */ MCD_OPC_CheckPredicate, 1, 4, 63, 0, // Skip to: 86948 -/* 70816 */ MCD_OPC_Decode, 134, 17, 131, 3, // Opcode: LDEORALB -/* 70821 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70836 -/* 70826 */ MCD_OPC_CheckPredicate, 1, 245, 62, 0, // Skip to: 86948 -/* 70831 */ MCD_OPC_Decode, 171, 18, 131, 3, // Opcode: LDSETALB -/* 70836 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70851 -/* 70841 */ MCD_OPC_CheckPredicate, 1, 230, 62, 0, // Skip to: 86948 -/* 70846 */ MCD_OPC_Decode, 187, 18, 131, 3, // Opcode: LDSMAXALB -/* 70851 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70866 -/* 70856 */ MCD_OPC_CheckPredicate, 1, 215, 62, 0, // Skip to: 86948 -/* 70861 */ MCD_OPC_Decode, 203, 18, 131, 3, // Opcode: LDSMINALB -/* 70866 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70881 -/* 70871 */ MCD_OPC_CheckPredicate, 1, 200, 62, 0, // Skip to: 86948 -/* 70876 */ MCD_OPC_Decode, 228, 18, 131, 3, // Opcode: LDUMAXALB -/* 70881 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70896 -/* 70886 */ MCD_OPC_CheckPredicate, 1, 185, 62, 0, // Skip to: 86948 -/* 70891 */ MCD_OPC_Decode, 244, 18, 131, 3, // Opcode: LDUMINALB -/* 70896 */ MCD_OPC_FilterValue, 8, 175, 62, 0, // Skip to: 86948 -/* 70901 */ MCD_OPC_CheckPredicate, 1, 170, 62, 0, // Skip to: 86948 -/* 70906 */ MCD_OPC_Decode, 155, 30, 131, 3, // Opcode: SWPALB -/* 70911 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70928 -/* 70916 */ MCD_OPC_CheckField, 21, 1, 0, 153, 62, 0, // Skip to: 86948 -/* 70923 */ MCD_OPC_Decode, 251, 17, 255, 2, // Opcode: LDRSBWpost -/* 70928 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70974 -/* 70933 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 70936 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70946 -/* 70941 */ MCD_OPC_Decode, 219, 18, 255, 2, // Opcode: LDTRSBWi -/* 70946 */ MCD_OPC_FilterValue, 1, 125, 62, 0, // Skip to: 86948 -/* 70951 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 70954 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70964 -/* 70959 */ MCD_OPC_Decode, 253, 17, 132, 3, // Opcode: LDRSBWroW -/* 70964 */ MCD_OPC_FilterValue, 3, 107, 62, 0, // Skip to: 86948 -/* 70969 */ MCD_OPC_Decode, 254, 17, 133, 3, // Opcode: LDRSBWroX -/* 70974 */ MCD_OPC_FilterValue, 3, 97, 62, 0, // Skip to: 86948 -/* 70979 */ MCD_OPC_CheckField, 21, 1, 0, 90, 62, 0, // Skip to: 86948 -/* 70986 */ MCD_OPC_Decode, 252, 17, 255, 2, // Opcode: LDRSBWpre -/* 70991 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 71001 -/* 70996 */ MCD_OPC_Decode, 149, 29, 137, 3, // Opcode: STRBBui -/* 71001 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 71011 -/* 71006 */ MCD_OPC_Decode, 223, 17, 137, 3, // Opcode: LDRBBui -/* 71011 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 71021 -/* 71016 */ MCD_OPC_Decode, 132, 18, 137, 3, // Opcode: LDRSBXui -/* 71021 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 71031 -/* 71026 */ MCD_OPC_Decode, 255, 17, 137, 3, // Opcode: LDRSBWui -/* 71031 */ MCD_OPC_FilterValue, 8, 78, 0, 0, // Skip to: 71114 -/* 71036 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 71039 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 71056 -/* 71044 */ MCD_OPC_CheckField, 21, 1, 0, 25, 62, 0, // Skip to: 86948 -/* 71051 */ MCD_OPC_Decode, 138, 1, 128, 3, // Opcode: ADCSWr -/* 71056 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 71085 -/* 71061 */ MCD_OPC_CheckPredicate, 12, 10, 62, 0, // Skip to: 86948 -/* 71066 */ MCD_OPC_CheckField, 16, 6, 0, 3, 62, 0, // Skip to: 86948 -/* 71073 */ MCD_OPC_CheckField, 0, 5, 13, 252, 61, 0, // Skip to: 86948 -/* 71080 */ MCD_OPC_Decode, 239, 22, 138, 3, // Opcode: SETF8 -/* 71085 */ MCD_OPC_FilterValue, 18, 242, 61, 0, // Skip to: 86948 -/* 71090 */ MCD_OPC_CheckPredicate, 12, 237, 61, 0, // Skip to: 86948 -/* 71095 */ MCD_OPC_CheckField, 16, 6, 0, 230, 61, 0, // Skip to: 86948 -/* 71102 */ MCD_OPC_CheckField, 0, 5, 13, 223, 61, 0, // Skip to: 86948 -/* 71109 */ MCD_OPC_Decode, 238, 22, 138, 3, // Opcode: SETF16 -/* 71114 */ MCD_OPC_FilterValue, 9, 213, 61, 0, // Skip to: 86948 -/* 71119 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 71122 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 71146 -/* 71127 */ MCD_OPC_CheckField, 21, 1, 0, 198, 61, 0, // Skip to: 86948 -/* 71134 */ MCD_OPC_CheckField, 4, 1, 0, 191, 61, 0, // Skip to: 86948 -/* 71141 */ MCD_OPC_Decode, 253, 2, 139, 3, // Opcode: CCMNWr -/* 71146 */ MCD_OPC_FilterValue, 2, 181, 61, 0, // Skip to: 86948 -/* 71151 */ MCD_OPC_CheckField, 21, 1, 0, 174, 61, 0, // Skip to: 86948 -/* 71158 */ MCD_OPC_CheckField, 4, 1, 0, 167, 61, 0, // Skip to: 86948 -/* 71165 */ MCD_OPC_Decode, 252, 2, 140, 3, // Opcode: CCMNWi -/* 71170 */ MCD_OPC_FilterValue, 2, 244, 0, 0, // Skip to: 71419 -/* 71175 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 71178 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71188 -/* 71183 */ MCD_OPC_Decode, 161, 18, 244, 2, // Opcode: LDRXl -/* 71188 */ MCD_OPC_FilterValue, 1, 91, 0, 0, // Skip to: 71284 -/* 71193 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 71196 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 71218 -/* 71201 */ MCD_OPC_CheckPredicate, 12, 126, 61, 0, // Skip to: 86948 -/* 71206 */ MCD_OPC_CheckField, 10, 2, 0, 119, 61, 0, // Skip to: 86948 -/* 71213 */ MCD_OPC_Decode, 236, 28, 255, 2, // Opcode: STLURHi -/* 71218 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 71240 -/* 71223 */ MCD_OPC_CheckPredicate, 12, 104, 61, 0, // Skip to: 86948 -/* 71228 */ MCD_OPC_CheckField, 10, 2, 0, 97, 61, 0, // Skip to: 86948 -/* 71235 */ MCD_OPC_Decode, 226, 16, 255, 2, // Opcode: LDAPURHi -/* 71240 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 71262 -/* 71245 */ MCD_OPC_CheckPredicate, 12, 82, 61, 0, // Skip to: 86948 -/* 71250 */ MCD_OPC_CheckField, 10, 2, 0, 75, 61, 0, // Skip to: 86948 -/* 71257 */ MCD_OPC_Decode, 230, 16, 255, 2, // Opcode: LDAPURSHXi -/* 71262 */ MCD_OPC_FilterValue, 6, 65, 61, 0, // Skip to: 86948 -/* 71267 */ MCD_OPC_CheckPredicate, 12, 60, 61, 0, // Skip to: 86948 -/* 71272 */ MCD_OPC_CheckField, 10, 2, 0, 53, 61, 0, // Skip to: 86948 -/* 71279 */ MCD_OPC_Decode, 229, 16, 255, 2, // Opcode: LDAPURSHWi -/* 71284 */ MCD_OPC_FilterValue, 2, 43, 61, 0, // Skip to: 86948 -/* 71289 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 71292 */ MCD_OPC_FilterValue, 0, 58, 0, 0, // Skip to: 71355 -/* 71297 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 71300 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 71317 -/* 71305 */ MCD_OPC_CheckField, 12, 4, 0, 20, 61, 0, // Skip to: 86948 -/* 71312 */ MCD_OPC_Decode, 180, 22, 128, 3, // Opcode: SBCWr -/* 71317 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 71327 -/* 71322 */ MCD_OPC_Decode, 165, 5, 129, 3, // Opcode: CSINVWr -/* 71327 */ MCD_OPC_FilterValue, 6, 0, 61, 0, // Skip to: 86948 -/* 71332 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... -/* 71335 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71345 -/* 71340 */ MCD_OPC_Decode, 184, 21, 141, 3, // Opcode: RBITWr -/* 71345 */ MCD_OPC_FilterValue, 1, 238, 60, 0, // Skip to: 86948 -/* 71350 */ MCD_OPC_Decode, 170, 3, 141, 3, // Opcode: CLZWr -/* 71355 */ MCD_OPC_FilterValue, 1, 41, 0, 0, // Skip to: 71401 -/* 71360 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 71363 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 71373 -/* 71368 */ MCD_OPC_Decode, 167, 5, 129, 3, // Opcode: CSNEGWr -/* 71373 */ MCD_OPC_FilterValue, 6, 210, 60, 0, // Skip to: 86948 -/* 71378 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... -/* 71381 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71391 -/* 71386 */ MCD_OPC_Decode, 200, 21, 141, 3, // Opcode: REV16Wr -/* 71391 */ MCD_OPC_FilterValue, 1, 192, 60, 0, // Skip to: 86948 -/* 71396 */ MCD_OPC_Decode, 158, 3, 141, 3, // Opcode: CLSWr -/* 71401 */ MCD_OPC_FilterValue, 2, 182, 60, 0, // Skip to: 86948 -/* 71406 */ MCD_OPC_CheckField, 12, 12, 128, 24, 174, 60, 0, // Skip to: 86948 -/* 71414 */ MCD_OPC_Decode, 221, 21, 141, 3, // Opcode: REVWr -/* 71419 */ MCD_OPC_FilterValue, 3, 117, 4, 0, // Skip to: 72565 -/* 71424 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 71427 */ MCD_OPC_FilterValue, 0, 244, 0, 0, // Skip to: 71676 -/* 71432 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 71435 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 71596 -/* 71440 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 71443 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71453 -/* 71448 */ MCD_OPC_Decode, 199, 29, 255, 2, // Opcode: STURHHi -/* 71453 */ MCD_OPC_FilterValue, 1, 130, 60, 0, // Skip to: 86948 -/* 71458 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 71461 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71476 -/* 71466 */ MCD_OPC_CheckPredicate, 1, 117, 60, 0, // Skip to: 86948 -/* 71471 */ MCD_OPC_Decode, 214, 16, 131, 3, // Opcode: LDADDH -/* 71476 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 71491 -/* 71481 */ MCD_OPC_CheckPredicate, 1, 102, 60, 0, // Skip to: 86948 -/* 71486 */ MCD_OPC_Decode, 253, 16, 131, 3, // Opcode: LDCLRH -/* 71491 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 71506 -/* 71496 */ MCD_OPC_CheckPredicate, 1, 87, 60, 0, // Skip to: 86948 -/* 71501 */ MCD_OPC_Decode, 141, 17, 131, 3, // Opcode: LDEORH -/* 71506 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 71521 -/* 71511 */ MCD_OPC_CheckPredicate, 1, 72, 60, 0, // Skip to: 86948 -/* 71516 */ MCD_OPC_Decode, 178, 18, 131, 3, // Opcode: LDSETH -/* 71521 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 71536 -/* 71526 */ MCD_OPC_CheckPredicate, 1, 57, 60, 0, // Skip to: 86948 -/* 71531 */ MCD_OPC_Decode, 194, 18, 131, 3, // Opcode: LDSMAXH -/* 71536 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 71551 -/* 71541 */ MCD_OPC_CheckPredicate, 1, 42, 60, 0, // Skip to: 86948 -/* 71546 */ MCD_OPC_Decode, 210, 18, 131, 3, // Opcode: LDSMINH -/* 71551 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 71566 -/* 71556 */ MCD_OPC_CheckPredicate, 1, 27, 60, 0, // Skip to: 86948 -/* 71561 */ MCD_OPC_Decode, 235, 18, 131, 3, // Opcode: LDUMAXH -/* 71566 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 71581 -/* 71571 */ MCD_OPC_CheckPredicate, 1, 12, 60, 0, // Skip to: 86948 -/* 71576 */ MCD_OPC_Decode, 251, 18, 131, 3, // Opcode: LDUMINH -/* 71581 */ MCD_OPC_FilterValue, 8, 2, 60, 0, // Skip to: 86948 -/* 71586 */ MCD_OPC_CheckPredicate, 1, 253, 59, 0, // Skip to: 86948 -/* 71591 */ MCD_OPC_Decode, 162, 30, 131, 3, // Opcode: SWPH -/* 71596 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 71613 -/* 71601 */ MCD_OPC_CheckField, 21, 1, 0, 236, 59, 0, // Skip to: 86948 -/* 71608 */ MCD_OPC_Decode, 160, 29, 255, 2, // Opcode: STRHHpost -/* 71613 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 71659 -/* 71618 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 71621 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71631 -/* 71626 */ MCD_OPC_Decode, 193, 29, 255, 2, // Opcode: STTRHi -/* 71631 */ MCD_OPC_FilterValue, 1, 208, 59, 0, // Skip to: 86948 -/* 71636 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 71639 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 71649 -/* 71644 */ MCD_OPC_Decode, 162, 29, 132, 3, // Opcode: STRHHroW -/* 71649 */ MCD_OPC_FilterValue, 3, 190, 59, 0, // Skip to: 86948 -/* 71654 */ MCD_OPC_Decode, 163, 29, 133, 3, // Opcode: STRHHroX -/* 71659 */ MCD_OPC_FilterValue, 3, 180, 59, 0, // Skip to: 86948 -/* 71664 */ MCD_OPC_CheckField, 21, 1, 0, 173, 59, 0, // Skip to: 86948 -/* 71671 */ MCD_OPC_Decode, 161, 29, 255, 2, // Opcode: STRHHpre -/* 71676 */ MCD_OPC_FilterValue, 1, 244, 0, 0, // Skip to: 71925 -/* 71681 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 71684 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 71845 -/* 71689 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 71692 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71702 -/* 71697 */ MCD_OPC_Decode, 133, 19, 255, 2, // Opcode: LDURHHi -/* 71702 */ MCD_OPC_FilterValue, 1, 137, 59, 0, // Skip to: 86948 -/* 71707 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 71710 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71725 -/* 71715 */ MCD_OPC_CheckPredicate, 1, 124, 59, 0, // Skip to: 86948 -/* 71720 */ MCD_OPC_Decode, 216, 16, 131, 3, // Opcode: LDADDLH -/* 71725 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 71740 -/* 71730 */ MCD_OPC_CheckPredicate, 1, 109, 59, 0, // Skip to: 86948 -/* 71735 */ MCD_OPC_Decode, 255, 16, 131, 3, // Opcode: LDCLRLH -/* 71740 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 71755 -/* 71745 */ MCD_OPC_CheckPredicate, 1, 94, 59, 0, // Skip to: 86948 -/* 71750 */ MCD_OPC_Decode, 143, 17, 131, 3, // Opcode: LDEORLH -/* 71755 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 71770 -/* 71760 */ MCD_OPC_CheckPredicate, 1, 79, 59, 0, // Skip to: 86948 -/* 71765 */ MCD_OPC_Decode, 180, 18, 131, 3, // Opcode: LDSETLH -/* 71770 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 71785 -/* 71775 */ MCD_OPC_CheckPredicate, 1, 64, 59, 0, // Skip to: 86948 -/* 71780 */ MCD_OPC_Decode, 196, 18, 131, 3, // Opcode: LDSMAXLH -/* 71785 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 71800 -/* 71790 */ MCD_OPC_CheckPredicate, 1, 49, 59, 0, // Skip to: 86948 -/* 71795 */ MCD_OPC_Decode, 212, 18, 131, 3, // Opcode: LDSMINLH -/* 71800 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 71815 -/* 71805 */ MCD_OPC_CheckPredicate, 1, 34, 59, 0, // Skip to: 86948 -/* 71810 */ MCD_OPC_Decode, 237, 18, 131, 3, // Opcode: LDUMAXLH -/* 71815 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 71830 -/* 71820 */ MCD_OPC_CheckPredicate, 1, 19, 59, 0, // Skip to: 86948 -/* 71825 */ MCD_OPC_Decode, 253, 18, 131, 3, // Opcode: LDUMINLH -/* 71830 */ MCD_OPC_FilterValue, 8, 9, 59, 0, // Skip to: 86948 -/* 71835 */ MCD_OPC_CheckPredicate, 1, 4, 59, 0, // Skip to: 86948 -/* 71840 */ MCD_OPC_Decode, 164, 30, 131, 3, // Opcode: SWPLH -/* 71845 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 71862 -/* 71850 */ MCD_OPC_CheckField, 21, 1, 0, 243, 58, 0, // Skip to: 86948 -/* 71857 */ MCD_OPC_Decode, 235, 17, 255, 2, // Opcode: LDRHHpost -/* 71862 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 71908 -/* 71867 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 71870 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71880 -/* 71875 */ MCD_OPC_Decode, 218, 18, 255, 2, // Opcode: LDTRHi -/* 71880 */ MCD_OPC_FilterValue, 1, 215, 58, 0, // Skip to: 86948 -/* 71885 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 71888 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 71898 -/* 71893 */ MCD_OPC_Decode, 237, 17, 132, 3, // Opcode: LDRHHroW -/* 71898 */ MCD_OPC_FilterValue, 3, 197, 58, 0, // Skip to: 86948 -/* 71903 */ MCD_OPC_Decode, 238, 17, 133, 3, // Opcode: LDRHHroX -/* 71908 */ MCD_OPC_FilterValue, 3, 187, 58, 0, // Skip to: 86948 -/* 71913 */ MCD_OPC_CheckField, 21, 1, 0, 180, 58, 0, // Skip to: 86948 -/* 71920 */ MCD_OPC_Decode, 236, 17, 255, 2, // Opcode: LDRHHpre -/* 71925 */ MCD_OPC_FilterValue, 2, 10, 1, 0, // Skip to: 72196 -/* 71930 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 71933 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 72116 -/* 71938 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 71941 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71951 -/* 71946 */ MCD_OPC_Decode, 139, 19, 255, 2, // Opcode: LDURSHXi -/* 71951 */ MCD_OPC_FilterValue, 1, 144, 58, 0, // Skip to: 86948 -/* 71956 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 71959 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71974 -/* 71964 */ MCD_OPC_CheckPredicate, 1, 131, 58, 0, // Skip to: 86948 -/* 71969 */ MCD_OPC_Decode, 206, 16, 131, 3, // Opcode: LDADDAH -/* 71974 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 71989 -/* 71979 */ MCD_OPC_CheckPredicate, 1, 116, 58, 0, // Skip to: 86948 -/* 71984 */ MCD_OPC_Decode, 245, 16, 131, 3, // Opcode: LDCLRAH -/* 71989 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 72004 -/* 71994 */ MCD_OPC_CheckPredicate, 1, 101, 58, 0, // Skip to: 86948 -/* 71999 */ MCD_OPC_Decode, 133, 17, 131, 3, // Opcode: LDEORAH -/* 72004 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 72019 -/* 72009 */ MCD_OPC_CheckPredicate, 1, 86, 58, 0, // Skip to: 86948 -/* 72014 */ MCD_OPC_Decode, 170, 18, 131, 3, // Opcode: LDSETAH -/* 72019 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 72034 -/* 72024 */ MCD_OPC_CheckPredicate, 1, 71, 58, 0, // Skip to: 86948 -/* 72029 */ MCD_OPC_Decode, 186, 18, 131, 3, // Opcode: LDSMAXAH -/* 72034 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 72049 -/* 72039 */ MCD_OPC_CheckPredicate, 1, 56, 58, 0, // Skip to: 86948 -/* 72044 */ MCD_OPC_Decode, 202, 18, 131, 3, // Opcode: LDSMINAH -/* 72049 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 72064 -/* 72054 */ MCD_OPC_CheckPredicate, 1, 41, 58, 0, // Skip to: 86948 -/* 72059 */ MCD_OPC_Decode, 227, 18, 131, 3, // Opcode: LDUMAXAH -/* 72064 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 72079 -/* 72069 */ MCD_OPC_CheckPredicate, 1, 26, 58, 0, // Skip to: 86948 -/* 72074 */ MCD_OPC_Decode, 243, 18, 131, 3, // Opcode: LDUMINAH -/* 72079 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 72094 -/* 72084 */ MCD_OPC_CheckPredicate, 1, 11, 58, 0, // Skip to: 86948 -/* 72089 */ MCD_OPC_Decode, 154, 30, 131, 3, // Opcode: SWPAH -/* 72094 */ MCD_OPC_FilterValue, 12, 1, 58, 0, // Skip to: 86948 -/* 72099 */ MCD_OPC_CheckPredicate, 15, 252, 57, 0, // Skip to: 86948 -/* 72104 */ MCD_OPC_CheckField, 16, 5, 31, 245, 57, 0, // Skip to: 86948 -/* 72111 */ MCD_OPC_Decode, 222, 16, 134, 3, // Opcode: LDAPRH -/* 72116 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 72133 -/* 72121 */ MCD_OPC_CheckField, 21, 1, 0, 228, 57, 0, // Skip to: 86948 -/* 72128 */ MCD_OPC_Decode, 138, 18, 255, 2, // Opcode: LDRSHXpost -/* 72133 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 72179 -/* 72138 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 72141 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72151 -/* 72146 */ MCD_OPC_Decode, 222, 18, 255, 2, // Opcode: LDTRSHXi -/* 72151 */ MCD_OPC_FilterValue, 1, 200, 57, 0, // Skip to: 86948 -/* 72156 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 72159 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 72169 -/* 72164 */ MCD_OPC_Decode, 140, 18, 135, 3, // Opcode: LDRSHXroW -/* 72169 */ MCD_OPC_FilterValue, 3, 182, 57, 0, // Skip to: 86948 -/* 72174 */ MCD_OPC_Decode, 141, 18, 136, 3, // Opcode: LDRSHXroX -/* 72179 */ MCD_OPC_FilterValue, 3, 172, 57, 0, // Skip to: 86948 -/* 72184 */ MCD_OPC_CheckField, 21, 1, 0, 165, 57, 0, // Skip to: 86948 -/* 72191 */ MCD_OPC_Decode, 139, 18, 255, 2, // Opcode: LDRSHXpre -/* 72196 */ MCD_OPC_FilterValue, 3, 244, 0, 0, // Skip to: 72445 -/* 72201 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 72204 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 72365 -/* 72209 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 72212 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72222 -/* 72217 */ MCD_OPC_Decode, 138, 19, 255, 2, // Opcode: LDURSHWi -/* 72222 */ MCD_OPC_FilterValue, 1, 129, 57, 0, // Skip to: 86948 -/* 72227 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 72230 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 72245 -/* 72235 */ MCD_OPC_CheckPredicate, 1, 116, 57, 0, // Skip to: 86948 -/* 72240 */ MCD_OPC_Decode, 208, 16, 131, 3, // Opcode: LDADDALH -/* 72245 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 72260 -/* 72250 */ MCD_OPC_CheckPredicate, 1, 101, 57, 0, // Skip to: 86948 -/* 72255 */ MCD_OPC_Decode, 247, 16, 131, 3, // Opcode: LDCLRALH -/* 72260 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 72275 -/* 72265 */ MCD_OPC_CheckPredicate, 1, 86, 57, 0, // Skip to: 86948 -/* 72270 */ MCD_OPC_Decode, 135, 17, 131, 3, // Opcode: LDEORALH -/* 72275 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 72290 -/* 72280 */ MCD_OPC_CheckPredicate, 1, 71, 57, 0, // Skip to: 86948 -/* 72285 */ MCD_OPC_Decode, 172, 18, 131, 3, // Opcode: LDSETALH -/* 72290 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 72305 -/* 72295 */ MCD_OPC_CheckPredicate, 1, 56, 57, 0, // Skip to: 86948 -/* 72300 */ MCD_OPC_Decode, 188, 18, 131, 3, // Opcode: LDSMAXALH -/* 72305 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 72320 -/* 72310 */ MCD_OPC_CheckPredicate, 1, 41, 57, 0, // Skip to: 86948 -/* 72315 */ MCD_OPC_Decode, 204, 18, 131, 3, // Opcode: LDSMINALH -/* 72320 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 72335 -/* 72325 */ MCD_OPC_CheckPredicate, 1, 26, 57, 0, // Skip to: 86948 -/* 72330 */ MCD_OPC_Decode, 229, 18, 131, 3, // Opcode: LDUMAXALH -/* 72335 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 72350 -/* 72340 */ MCD_OPC_CheckPredicate, 1, 11, 57, 0, // Skip to: 86948 -/* 72345 */ MCD_OPC_Decode, 245, 18, 131, 3, // Opcode: LDUMINALH -/* 72350 */ MCD_OPC_FilterValue, 8, 1, 57, 0, // Skip to: 86948 -/* 72355 */ MCD_OPC_CheckPredicate, 1, 252, 56, 0, // Skip to: 86948 -/* 72360 */ MCD_OPC_Decode, 156, 30, 131, 3, // Opcode: SWPALH -/* 72365 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 72382 -/* 72370 */ MCD_OPC_CheckField, 21, 1, 0, 235, 56, 0, // Skip to: 86948 -/* 72377 */ MCD_OPC_Decode, 133, 18, 255, 2, // Opcode: LDRSHWpost -/* 72382 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 72428 -/* 72387 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 72390 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72400 -/* 72395 */ MCD_OPC_Decode, 221, 18, 255, 2, // Opcode: LDTRSHWi -/* 72400 */ MCD_OPC_FilterValue, 1, 207, 56, 0, // Skip to: 86948 -/* 72405 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 72408 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 72418 -/* 72413 */ MCD_OPC_Decode, 135, 18, 132, 3, // Opcode: LDRSHWroW -/* 72418 */ MCD_OPC_FilterValue, 3, 189, 56, 0, // Skip to: 86948 -/* 72423 */ MCD_OPC_Decode, 136, 18, 133, 3, // Opcode: LDRSHWroX -/* 72428 */ MCD_OPC_FilterValue, 3, 179, 56, 0, // Skip to: 86948 -/* 72433 */ MCD_OPC_CheckField, 21, 1, 0, 172, 56, 0, // Skip to: 86948 -/* 72440 */ MCD_OPC_Decode, 134, 18, 255, 2, // Opcode: LDRSHWpre -/* 72445 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 72455 -/* 72450 */ MCD_OPC_Decode, 164, 29, 137, 3, // Opcode: STRHHui -/* 72455 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 72465 -/* 72460 */ MCD_OPC_Decode, 239, 17, 137, 3, // Opcode: LDRHHui -/* 72465 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 72475 -/* 72470 */ MCD_OPC_Decode, 142, 18, 137, 3, // Opcode: LDRSHXui -/* 72475 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 72485 -/* 72480 */ MCD_OPC_Decode, 137, 18, 137, 3, // Opcode: LDRSHWui -/* 72485 */ MCD_OPC_FilterValue, 8, 19, 0, 0, // Skip to: 72509 -/* 72490 */ MCD_OPC_CheckField, 21, 1, 0, 115, 56, 0, // Skip to: 86948 -/* 72497 */ MCD_OPC_CheckField, 10, 6, 0, 108, 56, 0, // Skip to: 86948 -/* 72504 */ MCD_OPC_Decode, 178, 22, 128, 3, // Opcode: SBCSWr -/* 72509 */ MCD_OPC_FilterValue, 9, 98, 56, 0, // Skip to: 86948 -/* 72514 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 72517 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 72541 -/* 72522 */ MCD_OPC_CheckField, 21, 1, 0, 83, 56, 0, // Skip to: 86948 -/* 72529 */ MCD_OPC_CheckField, 4, 1, 0, 76, 56, 0, // Skip to: 86948 -/* 72536 */ MCD_OPC_Decode, 129, 3, 139, 3, // Opcode: CCMPWr -/* 72541 */ MCD_OPC_FilterValue, 2, 66, 56, 0, // Skip to: 86948 -/* 72546 */ MCD_OPC_CheckField, 21, 1, 0, 59, 56, 0, // Skip to: 86948 -/* 72553 */ MCD_OPC_CheckField, 4, 1, 0, 52, 56, 0, // Skip to: 86948 -/* 72560 */ MCD_OPC_Decode, 128, 3, 140, 3, // Opcode: CCMPWi -/* 72565 */ MCD_OPC_FilterValue, 4, 196, 1, 0, // Skip to: 73022 -/* 72570 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 72573 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72583 -/* 72578 */ MCD_OPC_Decode, 143, 18, 244, 2, // Opcode: LDRSWl -/* 72583 */ MCD_OPC_FilterValue, 1, 69, 0, 0, // Skip to: 72657 -/* 72588 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 72591 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 72613 -/* 72596 */ MCD_OPC_CheckPredicate, 12, 11, 56, 0, // Skip to: 86948 -/* 72601 */ MCD_OPC_CheckField, 10, 2, 0, 4, 56, 0, // Skip to: 86948 -/* 72608 */ MCD_OPC_Decode, 237, 28, 255, 2, // Opcode: STLURWi -/* 72613 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 72635 -/* 72618 */ MCD_OPC_CheckPredicate, 12, 245, 55, 0, // Skip to: 86948 -/* 72623 */ MCD_OPC_CheckField, 10, 2, 0, 238, 55, 0, // Skip to: 86948 -/* 72630 */ MCD_OPC_Decode, 233, 16, 255, 2, // Opcode: LDAPURi -/* 72635 */ MCD_OPC_FilterValue, 4, 228, 55, 0, // Skip to: 86948 -/* 72640 */ MCD_OPC_CheckPredicate, 12, 223, 55, 0, // Skip to: 86948 -/* 72645 */ MCD_OPC_CheckField, 10, 2, 0, 216, 55, 0, // Skip to: 86948 -/* 72652 */ MCD_OPC_Decode, 231, 16, 255, 2, // Opcode: LDAPURSWi -/* 72657 */ MCD_OPC_FilterValue, 2, 234, 0, 0, // Skip to: 72896 -/* 72662 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 72665 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 72733 -/* 72670 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 72673 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 72690 -/* 72678 */ MCD_OPC_CheckField, 12, 4, 0, 183, 55, 0, // Skip to: 86948 -/* 72685 */ MCD_OPC_Decode, 141, 1, 142, 3, // Opcode: ADCXr -/* 72690 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 72700 -/* 72695 */ MCD_OPC_Decode, 162, 5, 143, 3, // Opcode: CSELXr -/* 72700 */ MCD_OPC_FilterValue, 6, 163, 55, 0, // Skip to: 86948 -/* 72705 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 72708 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 72718 -/* 72713 */ MCD_OPC_Decode, 156, 19, 142, 3, // Opcode: LSLVXr -/* 72718 */ MCD_OPC_FilterValue, 3, 145, 55, 0, // Skip to: 86948 -/* 72723 */ MCD_OPC_CheckPredicate, 13, 140, 55, 0, // Skip to: 86948 -/* 72728 */ MCD_OPC_Decode, 231, 20, 144, 3, // Opcode: PACGA -/* 72733 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 72768 -/* 72738 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 72741 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 72751 -/* 72746 */ MCD_OPC_Decode, 164, 5, 143, 3, // Opcode: CSINCXr -/* 72751 */ MCD_OPC_FilterValue, 6, 112, 55, 0, // Skip to: 86948 -/* 72756 */ MCD_OPC_CheckField, 12, 4, 2, 105, 55, 0, // Skip to: 86948 -/* 72763 */ MCD_OPC_Decode, 180, 19, 142, 3, // Opcode: LSRVXr -/* 72768 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 72810 -/* 72773 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 72776 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 72793 -/* 72781 */ MCD_OPC_CheckField, 21, 3, 6, 80, 55, 0, // Skip to: 86948 -/* 72788 */ MCD_OPC_Decode, 209, 31, 142, 3, // Opcode: UDIVXr -/* 72793 */ MCD_OPC_FilterValue, 2, 70, 55, 0, // Skip to: 86948 -/* 72798 */ MCD_OPC_CheckField, 21, 3, 6, 63, 55, 0, // Skip to: 86948 -/* 72805 */ MCD_OPC_Decode, 135, 2, 142, 3, // Opcode: ASRVXr -/* 72810 */ MCD_OPC_FilterValue, 3, 53, 55, 0, // Skip to: 86948 -/* 72815 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 72818 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 72835 -/* 72823 */ MCD_OPC_CheckField, 21, 3, 6, 38, 55, 0, // Skip to: 86948 -/* 72830 */ MCD_OPC_Decode, 222, 22, 142, 3, // Opcode: SDIVXr -/* 72835 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 72852 -/* 72840 */ MCD_OPC_CheckField, 21, 3, 6, 21, 55, 0, // Skip to: 86948 -/* 72847 */ MCD_OPC_Decode, 233, 21, 142, 3, // Opcode: RORVXr -/* 72852 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 72874 -/* 72857 */ MCD_OPC_CheckPredicate, 14, 6, 55, 0, // Skip to: 86948 -/* 72862 */ MCD_OPC_CheckField, 21, 3, 6, 255, 54, 0, // Skip to: 86948 -/* 72869 */ MCD_OPC_Decode, 160, 5, 145, 3, // Opcode: CRC32Xrr -/* 72874 */ MCD_OPC_FilterValue, 5, 245, 54, 0, // Skip to: 86948 -/* 72879 */ MCD_OPC_CheckPredicate, 14, 240, 54, 0, // Skip to: 86948 -/* 72884 */ MCD_OPC_CheckField, 21, 3, 6, 233, 54, 0, // Skip to: 86948 -/* 72891 */ MCD_OPC_Decode, 157, 5, 145, 3, // Opcode: CRC32CXrr -/* 72896 */ MCD_OPC_FilterValue, 3, 223, 54, 0, // Skip to: 86948 -/* 72901 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 72904 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 72932 -/* 72909 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 72912 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72922 -/* 72917 */ MCD_OPC_Decode, 200, 19, 146, 3, // Opcode: MADDXrrr -/* 72922 */ MCD_OPC_FilterValue, 1, 197, 54, 0, // Skip to: 86948 -/* 72927 */ MCD_OPC_Decode, 148, 20, 146, 3, // Opcode: MSUBXrrr -/* 72932 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 72960 -/* 72937 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 72940 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72950 -/* 72945 */ MCD_OPC_Decode, 176, 23, 147, 3, // Opcode: SMADDLrrr -/* 72950 */ MCD_OPC_FilterValue, 1, 169, 54, 0, // Skip to: 86948 -/* 72955 */ MCD_OPC_Decode, 133, 24, 147, 3, // Opcode: SMSUBLrrr -/* 72960 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 72977 -/* 72965 */ MCD_OPC_CheckField, 15, 1, 0, 152, 54, 0, // Skip to: 86948 -/* 72972 */ MCD_OPC_Decode, 138, 24, 142, 3, // Opcode: SMULHrr -/* 72977 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 73005 -/* 72982 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 72985 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72995 -/* 72990 */ MCD_OPC_Decode, 232, 31, 147, 3, // Opcode: UMADDLrrr -/* 72995 */ MCD_OPC_FilterValue, 1, 124, 54, 0, // Skip to: 86948 -/* 73000 */ MCD_OPC_Decode, 187, 32, 147, 3, // Opcode: UMSUBLrrr -/* 73005 */ MCD_OPC_FilterValue, 6, 114, 54, 0, // Skip to: 86948 -/* 73010 */ MCD_OPC_CheckField, 15, 1, 0, 107, 54, 0, // Skip to: 86948 -/* 73017 */ MCD_OPC_Decode, 192, 32, 142, 3, // Opcode: UMULHrr -/* 73022 */ MCD_OPC_FilterValue, 5, 101, 4, 0, // Skip to: 74152 -/* 73027 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 73030 */ MCD_OPC_FilterValue, 0, 244, 0, 0, // Skip to: 73279 -/* 73035 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 73038 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 73199 -/* 73043 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 73046 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73056 -/* 73051 */ MCD_OPC_Decode, 203, 29, 255, 2, // Opcode: STURWi -/* 73056 */ MCD_OPC_FilterValue, 1, 63, 54, 0, // Skip to: 86948 -/* 73061 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 73064 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73079 -/* 73069 */ MCD_OPC_CheckPredicate, 1, 50, 54, 0, // Skip to: 86948 -/* 73074 */ MCD_OPC_Decode, 219, 16, 131, 3, // Opcode: LDADDW -/* 73079 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 73094 -/* 73084 */ MCD_OPC_CheckPredicate, 1, 35, 54, 0, // Skip to: 86948 -/* 73089 */ MCD_OPC_Decode, 130, 17, 131, 3, // Opcode: LDCLRW -/* 73094 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 73109 -/* 73099 */ MCD_OPC_CheckPredicate, 1, 20, 54, 0, // Skip to: 86948 -/* 73104 */ MCD_OPC_Decode, 146, 17, 131, 3, // Opcode: LDEORW -/* 73109 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73124 -/* 73114 */ MCD_OPC_CheckPredicate, 1, 5, 54, 0, // Skip to: 86948 -/* 73119 */ MCD_OPC_Decode, 183, 18, 131, 3, // Opcode: LDSETW -/* 73124 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 73139 -/* 73129 */ MCD_OPC_CheckPredicate, 1, 246, 53, 0, // Skip to: 86948 -/* 73134 */ MCD_OPC_Decode, 199, 18, 131, 3, // Opcode: LDSMAXW -/* 73139 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 73154 -/* 73144 */ MCD_OPC_CheckPredicate, 1, 231, 53, 0, // Skip to: 86948 -/* 73149 */ MCD_OPC_Decode, 215, 18, 131, 3, // Opcode: LDSMINW -/* 73154 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 73169 -/* 73159 */ MCD_OPC_CheckPredicate, 1, 216, 53, 0, // Skip to: 86948 -/* 73164 */ MCD_OPC_Decode, 240, 18, 131, 3, // Opcode: LDUMAXW -/* 73169 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 73184 -/* 73174 */ MCD_OPC_CheckPredicate, 1, 201, 53, 0, // Skip to: 86948 -/* 73179 */ MCD_OPC_Decode, 128, 19, 131, 3, // Opcode: LDUMINW -/* 73184 */ MCD_OPC_FilterValue, 8, 191, 53, 0, // Skip to: 86948 -/* 73189 */ MCD_OPC_CheckPredicate, 1, 186, 53, 0, // Skip to: 86948 -/* 73194 */ MCD_OPC_Decode, 167, 30, 131, 3, // Opcode: SWPW -/* 73199 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 73216 -/* 73204 */ MCD_OPC_CheckField, 21, 1, 0, 169, 53, 0, // Skip to: 86948 -/* 73211 */ MCD_OPC_Decode, 180, 29, 255, 2, // Opcode: STRWpost -/* 73216 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 73262 -/* 73221 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 73224 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73234 -/* 73229 */ MCD_OPC_Decode, 194, 29, 255, 2, // Opcode: STTRWi -/* 73234 */ MCD_OPC_FilterValue, 1, 141, 53, 0, // Skip to: 86948 -/* 73239 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 73242 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 73252 -/* 73247 */ MCD_OPC_Decode, 182, 29, 132, 3, // Opcode: STRWroW -/* 73252 */ MCD_OPC_FilterValue, 3, 123, 53, 0, // Skip to: 86948 -/* 73257 */ MCD_OPC_Decode, 183, 29, 133, 3, // Opcode: STRWroX -/* 73262 */ MCD_OPC_FilterValue, 3, 113, 53, 0, // Skip to: 86948 -/* 73267 */ MCD_OPC_CheckField, 21, 1, 0, 106, 53, 0, // Skip to: 86948 -/* 73274 */ MCD_OPC_Decode, 181, 29, 255, 2, // Opcode: STRWpre -/* 73279 */ MCD_OPC_FilterValue, 1, 244, 0, 0, // Skip to: 73528 -/* 73284 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 73287 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 73448 -/* 73292 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 73295 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73305 -/* 73300 */ MCD_OPC_Decode, 142, 19, 255, 2, // Opcode: LDURWi -/* 73305 */ MCD_OPC_FilterValue, 1, 70, 53, 0, // Skip to: 86948 -/* 73310 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 73313 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73328 -/* 73318 */ MCD_OPC_CheckPredicate, 1, 57, 53, 0, // Skip to: 86948 -/* 73323 */ MCD_OPC_Decode, 217, 16, 131, 3, // Opcode: LDADDLW -/* 73328 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 73343 -/* 73333 */ MCD_OPC_CheckPredicate, 1, 42, 53, 0, // Skip to: 86948 -/* 73338 */ MCD_OPC_Decode, 128, 17, 131, 3, // Opcode: LDCLRLW -/* 73343 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 73358 -/* 73348 */ MCD_OPC_CheckPredicate, 1, 27, 53, 0, // Skip to: 86948 -/* 73353 */ MCD_OPC_Decode, 144, 17, 131, 3, // Opcode: LDEORLW -/* 73358 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73373 -/* 73363 */ MCD_OPC_CheckPredicate, 1, 12, 53, 0, // Skip to: 86948 -/* 73368 */ MCD_OPC_Decode, 181, 18, 131, 3, // Opcode: LDSETLW -/* 73373 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 73388 -/* 73378 */ MCD_OPC_CheckPredicate, 1, 253, 52, 0, // Skip to: 86948 -/* 73383 */ MCD_OPC_Decode, 197, 18, 131, 3, // Opcode: LDSMAXLW -/* 73388 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 73403 -/* 73393 */ MCD_OPC_CheckPredicate, 1, 238, 52, 0, // Skip to: 86948 -/* 73398 */ MCD_OPC_Decode, 213, 18, 131, 3, // Opcode: LDSMINLW -/* 73403 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 73418 -/* 73408 */ MCD_OPC_CheckPredicate, 1, 223, 52, 0, // Skip to: 86948 -/* 73413 */ MCD_OPC_Decode, 238, 18, 131, 3, // Opcode: LDUMAXLW -/* 73418 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 73433 -/* 73423 */ MCD_OPC_CheckPredicate, 1, 208, 52, 0, // Skip to: 86948 -/* 73428 */ MCD_OPC_Decode, 254, 18, 131, 3, // Opcode: LDUMINLW -/* 73433 */ MCD_OPC_FilterValue, 8, 198, 52, 0, // Skip to: 86948 -/* 73438 */ MCD_OPC_CheckPredicate, 1, 193, 52, 0, // Skip to: 86948 -/* 73443 */ MCD_OPC_Decode, 165, 30, 131, 3, // Opcode: SWPLW -/* 73448 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 73465 -/* 73453 */ MCD_OPC_CheckField, 21, 1, 0, 176, 52, 0, // Skip to: 86948 -/* 73460 */ MCD_OPC_Decode, 156, 18, 255, 2, // Opcode: LDRWpost -/* 73465 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 73511 -/* 73470 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 73473 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73483 -/* 73478 */ MCD_OPC_Decode, 224, 18, 255, 2, // Opcode: LDTRWi -/* 73483 */ MCD_OPC_FilterValue, 1, 148, 52, 0, // Skip to: 86948 -/* 73488 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 73491 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 73501 -/* 73496 */ MCD_OPC_Decode, 158, 18, 132, 3, // Opcode: LDRWroW -/* 73501 */ MCD_OPC_FilterValue, 3, 130, 52, 0, // Skip to: 86948 -/* 73506 */ MCD_OPC_Decode, 159, 18, 133, 3, // Opcode: LDRWroX -/* 73511 */ MCD_OPC_FilterValue, 3, 120, 52, 0, // Skip to: 86948 -/* 73516 */ MCD_OPC_CheckField, 21, 1, 0, 113, 52, 0, // Skip to: 86948 -/* 73523 */ MCD_OPC_Decode, 157, 18, 255, 2, // Opcode: LDRWpre -/* 73528 */ MCD_OPC_FilterValue, 2, 10, 1, 0, // Skip to: 73799 -/* 73533 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 73536 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 73719 -/* 73541 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 73544 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73554 -/* 73549 */ MCD_OPC_Decode, 140, 19, 255, 2, // Opcode: LDURSWi -/* 73554 */ MCD_OPC_FilterValue, 1, 77, 52, 0, // Skip to: 86948 -/* 73559 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 73562 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73577 -/* 73567 */ MCD_OPC_CheckPredicate, 1, 64, 52, 0, // Skip to: 86948 -/* 73572 */ MCD_OPC_Decode, 211, 16, 131, 3, // Opcode: LDADDAW -/* 73577 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 73592 -/* 73582 */ MCD_OPC_CheckPredicate, 1, 49, 52, 0, // Skip to: 86948 -/* 73587 */ MCD_OPC_Decode, 250, 16, 131, 3, // Opcode: LDCLRAW -/* 73592 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 73607 -/* 73597 */ MCD_OPC_CheckPredicate, 1, 34, 52, 0, // Skip to: 86948 -/* 73602 */ MCD_OPC_Decode, 138, 17, 131, 3, // Opcode: LDEORAW -/* 73607 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73622 -/* 73612 */ MCD_OPC_CheckPredicate, 1, 19, 52, 0, // Skip to: 86948 -/* 73617 */ MCD_OPC_Decode, 175, 18, 131, 3, // Opcode: LDSETAW -/* 73622 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 73637 -/* 73627 */ MCD_OPC_CheckPredicate, 1, 4, 52, 0, // Skip to: 86948 -/* 73632 */ MCD_OPC_Decode, 191, 18, 131, 3, // Opcode: LDSMAXAW -/* 73637 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 73652 -/* 73642 */ MCD_OPC_CheckPredicate, 1, 245, 51, 0, // Skip to: 86948 -/* 73647 */ MCD_OPC_Decode, 207, 18, 131, 3, // Opcode: LDSMINAW -/* 73652 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 73667 -/* 73657 */ MCD_OPC_CheckPredicate, 1, 230, 51, 0, // Skip to: 86948 -/* 73662 */ MCD_OPC_Decode, 232, 18, 131, 3, // Opcode: LDUMAXAW -/* 73667 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 73682 -/* 73672 */ MCD_OPC_CheckPredicate, 1, 215, 51, 0, // Skip to: 86948 -/* 73677 */ MCD_OPC_Decode, 248, 18, 131, 3, // Opcode: LDUMINAW -/* 73682 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 73697 -/* 73687 */ MCD_OPC_CheckPredicate, 1, 200, 51, 0, // Skip to: 86948 -/* 73692 */ MCD_OPC_Decode, 159, 30, 131, 3, // Opcode: SWPAW -/* 73697 */ MCD_OPC_FilterValue, 12, 190, 51, 0, // Skip to: 86948 -/* 73702 */ MCD_OPC_CheckPredicate, 15, 185, 51, 0, // Skip to: 86948 -/* 73707 */ MCD_OPC_CheckField, 16, 5, 31, 178, 51, 0, // Skip to: 86948 -/* 73714 */ MCD_OPC_Decode, 223, 16, 134, 3, // Opcode: LDAPRW -/* 73719 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 73736 -/* 73724 */ MCD_OPC_CheckField, 21, 1, 0, 161, 51, 0, // Skip to: 86948 -/* 73731 */ MCD_OPC_Decode, 144, 18, 255, 2, // Opcode: LDRSWpost -/* 73736 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 73782 -/* 73741 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 73744 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73754 -/* 73749 */ MCD_OPC_Decode, 223, 18, 255, 2, // Opcode: LDTRSWi -/* 73754 */ MCD_OPC_FilterValue, 1, 133, 51, 0, // Skip to: 86948 -/* 73759 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 73762 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 73772 -/* 73767 */ MCD_OPC_Decode, 146, 18, 135, 3, // Opcode: LDRSWroW -/* 73772 */ MCD_OPC_FilterValue, 3, 115, 51, 0, // Skip to: 86948 -/* 73777 */ MCD_OPC_Decode, 147, 18, 136, 3, // Opcode: LDRSWroX -/* 73782 */ MCD_OPC_FilterValue, 3, 105, 51, 0, // Skip to: 86948 -/* 73787 */ MCD_OPC_CheckField, 21, 1, 0, 98, 51, 0, // Skip to: 86948 -/* 73794 */ MCD_OPC_Decode, 145, 18, 255, 2, // Opcode: LDRSWpre -/* 73799 */ MCD_OPC_FilterValue, 3, 201, 0, 0, // Skip to: 74005 -/* 73804 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 73807 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 73829 -/* 73812 */ MCD_OPC_CheckPredicate, 1, 75, 51, 0, // Skip to: 86948 -/* 73817 */ MCD_OPC_CheckField, 21, 1, 1, 68, 51, 0, // Skip to: 86948 -/* 73824 */ MCD_OPC_Decode, 209, 16, 131, 3, // Opcode: LDADDALW -/* 73829 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 73851 -/* 73834 */ MCD_OPC_CheckPredicate, 1, 53, 51, 0, // Skip to: 86948 -/* 73839 */ MCD_OPC_CheckField, 21, 1, 1, 46, 51, 0, // Skip to: 86948 -/* 73846 */ MCD_OPC_Decode, 248, 16, 131, 3, // Opcode: LDCLRALW -/* 73851 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 73873 -/* 73856 */ MCD_OPC_CheckPredicate, 1, 31, 51, 0, // Skip to: 86948 -/* 73861 */ MCD_OPC_CheckField, 21, 1, 1, 24, 51, 0, // Skip to: 86948 -/* 73868 */ MCD_OPC_Decode, 136, 17, 131, 3, // Opcode: LDEORALW -/* 73873 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 73895 -/* 73878 */ MCD_OPC_CheckPredicate, 1, 9, 51, 0, // Skip to: 86948 -/* 73883 */ MCD_OPC_CheckField, 21, 1, 1, 2, 51, 0, // Skip to: 86948 -/* 73890 */ MCD_OPC_Decode, 173, 18, 131, 3, // Opcode: LDSETALW -/* 73895 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 73917 -/* 73900 */ MCD_OPC_CheckPredicate, 1, 243, 50, 0, // Skip to: 86948 -/* 73905 */ MCD_OPC_CheckField, 21, 1, 1, 236, 50, 0, // Skip to: 86948 -/* 73912 */ MCD_OPC_Decode, 189, 18, 131, 3, // Opcode: LDSMAXALW -/* 73917 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 73939 -/* 73922 */ MCD_OPC_CheckPredicate, 1, 221, 50, 0, // Skip to: 86948 -/* 73927 */ MCD_OPC_CheckField, 21, 1, 1, 214, 50, 0, // Skip to: 86948 -/* 73934 */ MCD_OPC_Decode, 205, 18, 131, 3, // Opcode: LDSMINALW -/* 73939 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 73961 -/* 73944 */ MCD_OPC_CheckPredicate, 1, 199, 50, 0, // Skip to: 86948 -/* 73949 */ MCD_OPC_CheckField, 21, 1, 1, 192, 50, 0, // Skip to: 86948 -/* 73956 */ MCD_OPC_Decode, 230, 18, 131, 3, // Opcode: LDUMAXALW -/* 73961 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 73983 -/* 73966 */ MCD_OPC_CheckPredicate, 1, 177, 50, 0, // Skip to: 86948 -/* 73971 */ MCD_OPC_CheckField, 21, 1, 1, 170, 50, 0, // Skip to: 86948 -/* 73978 */ MCD_OPC_Decode, 246, 18, 131, 3, // Opcode: LDUMINALW -/* 73983 */ MCD_OPC_FilterValue, 32, 160, 50, 0, // Skip to: 86948 -/* 73988 */ MCD_OPC_CheckPredicate, 1, 155, 50, 0, // Skip to: 86948 -/* 73993 */ MCD_OPC_CheckField, 21, 1, 1, 148, 50, 0, // Skip to: 86948 -/* 74000 */ MCD_OPC_Decode, 157, 30, 131, 3, // Opcode: SWPALW -/* 74005 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 74015 -/* 74010 */ MCD_OPC_Decode, 184, 29, 137, 3, // Opcode: STRWui -/* 74015 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 74025 -/* 74020 */ MCD_OPC_Decode, 160, 18, 137, 3, // Opcode: LDRWui -/* 74025 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 74035 -/* 74030 */ MCD_OPC_Decode, 148, 18, 137, 3, // Opcode: LDRSWui -/* 74035 */ MCD_OPC_FilterValue, 8, 56, 0, 0, // Skip to: 74096 -/* 74040 */ MCD_OPC_ExtractField, 10, 5, // Inst{14-10} ... -/* 74043 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 74067 -/* 74048 */ MCD_OPC_CheckField, 21, 1, 0, 93, 50, 0, // Skip to: 86948 -/* 74055 */ MCD_OPC_CheckField, 15, 1, 0, 86, 50, 0, // Skip to: 86948 -/* 74062 */ MCD_OPC_Decode, 139, 1, 142, 3, // Opcode: ADCSXr -/* 74067 */ MCD_OPC_FilterValue, 1, 76, 50, 0, // Skip to: 86948 -/* 74072 */ MCD_OPC_CheckPredicate, 12, 71, 50, 0, // Skip to: 86948 -/* 74077 */ MCD_OPC_CheckField, 21, 1, 0, 64, 50, 0, // Skip to: 86948 -/* 74084 */ MCD_OPC_CheckField, 4, 1, 0, 57, 50, 0, // Skip to: 86948 -/* 74091 */ MCD_OPC_Decode, 231, 21, 148, 3, // Opcode: RMIF -/* 74096 */ MCD_OPC_FilterValue, 9, 47, 50, 0, // Skip to: 86948 -/* 74101 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 74104 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 74128 -/* 74109 */ MCD_OPC_CheckField, 21, 1, 0, 32, 50, 0, // Skip to: 86948 -/* 74116 */ MCD_OPC_CheckField, 4, 1, 0, 25, 50, 0, // Skip to: 86948 -/* 74123 */ MCD_OPC_Decode, 255, 2, 149, 3, // Opcode: CCMNXr -/* 74128 */ MCD_OPC_FilterValue, 2, 15, 50, 0, // Skip to: 86948 -/* 74133 */ MCD_OPC_CheckField, 21, 1, 0, 8, 50, 0, // Skip to: 86948 -/* 74140 */ MCD_OPC_CheckField, 4, 1, 0, 1, 50, 0, // Skip to: 86948 -/* 74147 */ MCD_OPC_Decode, 254, 2, 150, 3, // Opcode: CCMNXi -/* 74152 */ MCD_OPC_FilterValue, 6, 56, 2, 0, // Skip to: 74725 -/* 74157 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 74160 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74170 -/* 74165 */ MCD_OPC_Decode, 152, 21, 151, 3, // Opcode: PRFMl -/* 74170 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 74222 -/* 74175 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 74178 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 74200 -/* 74183 */ MCD_OPC_CheckPredicate, 12, 216, 49, 0, // Skip to: 86948 -/* 74188 */ MCD_OPC_CheckField, 10, 2, 0, 209, 49, 0, // Skip to: 86948 -/* 74195 */ MCD_OPC_Decode, 238, 28, 255, 2, // Opcode: STLURXi -/* 74200 */ MCD_OPC_FilterValue, 2, 199, 49, 0, // Skip to: 86948 -/* 74205 */ MCD_OPC_CheckPredicate, 12, 194, 49, 0, // Skip to: 86948 -/* 74210 */ MCD_OPC_CheckField, 10, 2, 0, 187, 49, 0, // Skip to: 86948 -/* 74217 */ MCD_OPC_Decode, 232, 16, 255, 2, // Opcode: LDAPURXi -/* 74222 */ MCD_OPC_FilterValue, 2, 177, 49, 0, // Skip to: 86948 -/* 74227 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 74230 */ MCD_OPC_FilterValue, 0, 154, 0, 0, // Skip to: 74389 -/* 74235 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 74238 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 74255 -/* 74243 */ MCD_OPC_CheckField, 12, 4, 0, 154, 49, 0, // Skip to: 86948 -/* 74250 */ MCD_OPC_Decode, 181, 22, 142, 3, // Opcode: SBCXr -/* 74255 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 74265 -/* 74260 */ MCD_OPC_Decode, 166, 5, 143, 3, // Opcode: CSINVXr -/* 74265 */ MCD_OPC_FilterValue, 6, 134, 49, 0, // Skip to: 86948 -/* 74270 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... -/* 74273 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74283 -/* 74278 */ MCD_OPC_Decode, 185, 21, 152, 3, // Opcode: RBITXr -/* 74283 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 74293 -/* 74288 */ MCD_OPC_Decode, 171, 3, 152, 3, // Opcode: CLZXr -/* 74293 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 74308 -/* 74298 */ MCD_OPC_CheckPredicate, 13, 101, 49, 0, // Skip to: 86948 -/* 74303 */ MCD_OPC_Decode, 232, 20, 153, 3, // Opcode: PACIA -/* 74308 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 74323 -/* 74313 */ MCD_OPC_CheckPredicate, 13, 86, 49, 0, // Skip to: 86948 -/* 74318 */ MCD_OPC_Decode, 158, 2, 153, 3, // Opcode: AUTIA -/* 74323 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 74345 -/* 74328 */ MCD_OPC_CheckPredicate, 13, 71, 49, 0, // Skip to: 86948 -/* 74333 */ MCD_OPC_CheckField, 5, 5, 31, 64, 49, 0, // Skip to: 86948 -/* 74340 */ MCD_OPC_Decode, 240, 20, 154, 3, // Opcode: PACIZA -/* 74345 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 74367 -/* 74350 */ MCD_OPC_CheckPredicate, 13, 49, 49, 0, // Skip to: 86948 -/* 74355 */ MCD_OPC_CheckField, 5, 5, 31, 42, 49, 0, // Skip to: 86948 -/* 74362 */ MCD_OPC_Decode, 166, 2, 154, 3, // Opcode: AUTIZA -/* 74367 */ MCD_OPC_FilterValue, 20, 32, 49, 0, // Skip to: 86948 -/* 74372 */ MCD_OPC_CheckPredicate, 13, 27, 49, 0, // Skip to: 86948 -/* 74377 */ MCD_OPC_CheckField, 5, 5, 31, 20, 49, 0, // Skip to: 86948 -/* 74384 */ MCD_OPC_Decode, 253, 34, 154, 3, // Opcode: XPACI -/* 74389 */ MCD_OPC_FilterValue, 1, 137, 0, 0, // Skip to: 74531 -/* 74394 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 74397 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 74407 -/* 74402 */ MCD_OPC_Decode, 168, 5, 143, 3, // Opcode: CSNEGXr -/* 74407 */ MCD_OPC_FilterValue, 6, 248, 48, 0, // Skip to: 86948 -/* 74412 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... -/* 74415 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74425 -/* 74420 */ MCD_OPC_Decode, 201, 21, 152, 3, // Opcode: REV16Xr -/* 74425 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 74435 -/* 74430 */ MCD_OPC_Decode, 159, 3, 152, 3, // Opcode: CLSXr -/* 74435 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 74450 -/* 74440 */ MCD_OPC_CheckPredicate, 13, 215, 48, 0, // Skip to: 86948 -/* 74445 */ MCD_OPC_Decode, 236, 20, 153, 3, // Opcode: PACIB -/* 74450 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 74465 -/* 74455 */ MCD_OPC_CheckPredicate, 13, 200, 48, 0, // Skip to: 86948 -/* 74460 */ MCD_OPC_Decode, 162, 2, 153, 3, // Opcode: AUTIB -/* 74465 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 74487 -/* 74470 */ MCD_OPC_CheckPredicate, 13, 185, 48, 0, // Skip to: 86948 -/* 74475 */ MCD_OPC_CheckField, 5, 5, 31, 178, 48, 0, // Skip to: 86948 -/* 74482 */ MCD_OPC_Decode, 241, 20, 154, 3, // Opcode: PACIZB -/* 74487 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 74509 -/* 74492 */ MCD_OPC_CheckPredicate, 13, 163, 48, 0, // Skip to: 86948 -/* 74497 */ MCD_OPC_CheckField, 5, 5, 31, 156, 48, 0, // Skip to: 86948 -/* 74504 */ MCD_OPC_Decode, 167, 2, 154, 3, // Opcode: AUTIZB -/* 74509 */ MCD_OPC_FilterValue, 20, 146, 48, 0, // Skip to: 86948 -/* 74514 */ MCD_OPC_CheckPredicate, 13, 141, 48, 0, // Skip to: 86948 -/* 74519 */ MCD_OPC_CheckField, 5, 5, 31, 134, 48, 0, // Skip to: 86948 -/* 74526 */ MCD_OPC_Decode, 252, 34, 154, 3, // Opcode: XPACD -/* 74531 */ MCD_OPC_FilterValue, 2, 92, 0, 0, // Skip to: 74628 -/* 74536 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 74539 */ MCD_OPC_FilterValue, 128, 24, 5, 0, 0, // Skip to: 74550 -/* 74545 */ MCD_OPC_Decode, 204, 21, 152, 3, // Opcode: REV32Xr -/* 74550 */ MCD_OPC_FilterValue, 144, 24, 10, 0, 0, // Skip to: 74566 -/* 74556 */ MCD_OPC_CheckPredicate, 13, 99, 48, 0, // Skip to: 86948 -/* 74561 */ MCD_OPC_Decode, 227, 20, 153, 3, // Opcode: PACDA -/* 74566 */ MCD_OPC_FilterValue, 145, 24, 10, 0, 0, // Skip to: 74582 -/* 74572 */ MCD_OPC_CheckPredicate, 13, 83, 48, 0, // Skip to: 86948 -/* 74577 */ MCD_OPC_Decode, 154, 2, 153, 3, // Opcode: AUTDA -/* 74582 */ MCD_OPC_FilterValue, 146, 24, 17, 0, 0, // Skip to: 74605 -/* 74588 */ MCD_OPC_CheckPredicate, 13, 67, 48, 0, // Skip to: 86948 -/* 74593 */ MCD_OPC_CheckField, 5, 5, 31, 60, 48, 0, // Skip to: 86948 -/* 74600 */ MCD_OPC_Decode, 229, 20, 154, 3, // Opcode: PACDZA -/* 74605 */ MCD_OPC_FilterValue, 147, 24, 49, 48, 0, // Skip to: 86948 -/* 74611 */ MCD_OPC_CheckPredicate, 13, 44, 48, 0, // Skip to: 86948 -/* 74616 */ MCD_OPC_CheckField, 5, 5, 31, 37, 48, 0, // Skip to: 86948 -/* 74623 */ MCD_OPC_Decode, 156, 2, 154, 3, // Opcode: AUTDZA -/* 74628 */ MCD_OPC_FilterValue, 3, 27, 48, 0, // Skip to: 86948 -/* 74633 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 74636 */ MCD_OPC_FilterValue, 128, 24, 5, 0, 0, // Skip to: 74647 -/* 74642 */ MCD_OPC_Decode, 222, 21, 152, 3, // Opcode: REVXr -/* 74647 */ MCD_OPC_FilterValue, 144, 24, 10, 0, 0, // Skip to: 74663 -/* 74653 */ MCD_OPC_CheckPredicate, 13, 2, 48, 0, // Skip to: 86948 -/* 74658 */ MCD_OPC_Decode, 228, 20, 153, 3, // Opcode: PACDB -/* 74663 */ MCD_OPC_FilterValue, 145, 24, 10, 0, 0, // Skip to: 74679 -/* 74669 */ MCD_OPC_CheckPredicate, 13, 242, 47, 0, // Skip to: 86948 -/* 74674 */ MCD_OPC_Decode, 155, 2, 153, 3, // Opcode: AUTDB -/* 74679 */ MCD_OPC_FilterValue, 146, 24, 17, 0, 0, // Skip to: 74702 -/* 74685 */ MCD_OPC_CheckPredicate, 13, 226, 47, 0, // Skip to: 86948 -/* 74690 */ MCD_OPC_CheckField, 5, 5, 31, 219, 47, 0, // Skip to: 86948 -/* 74697 */ MCD_OPC_Decode, 230, 20, 154, 3, // Opcode: PACDZB -/* 74702 */ MCD_OPC_FilterValue, 147, 24, 208, 47, 0, // Skip to: 86948 -/* 74708 */ MCD_OPC_CheckPredicate, 13, 203, 47, 0, // Skip to: 86948 -/* 74713 */ MCD_OPC_CheckField, 5, 5, 31, 196, 47, 0, // Skip to: 86948 -/* 74720 */ MCD_OPC_Decode, 157, 2, 154, 3, // Opcode: AUTDZB -/* 74725 */ MCD_OPC_FilterValue, 7, 186, 47, 0, // Skip to: 86948 -/* 74730 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 74733 */ MCD_OPC_FilterValue, 0, 247, 1, 0, // Skip to: 75241 -/* 74738 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 74741 */ MCD_OPC_FilterValue, 0, 53, 1, 0, // Skip to: 75055 -/* 74746 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 74749 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74759 -/* 74754 */ MCD_OPC_Decode, 204, 29, 255, 2, // Opcode: STURXi -/* 74759 */ MCD_OPC_FilterValue, 1, 138, 0, 0, // Skip to: 74902 -/* 74764 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 74767 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 74782 -/* 74772 */ MCD_OPC_CheckPredicate, 1, 139, 47, 0, // Skip to: 86948 -/* 74777 */ MCD_OPC_Decode, 220, 16, 155, 3, // Opcode: LDADDX -/* 74782 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 74797 -/* 74787 */ MCD_OPC_CheckPredicate, 1, 124, 47, 0, // Skip to: 86948 -/* 74792 */ MCD_OPC_Decode, 131, 17, 155, 3, // Opcode: LDCLRX -/* 74797 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 74812 -/* 74802 */ MCD_OPC_CheckPredicate, 1, 109, 47, 0, // Skip to: 86948 -/* 74807 */ MCD_OPC_Decode, 147, 17, 155, 3, // Opcode: LDEORX -/* 74812 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 74827 -/* 74817 */ MCD_OPC_CheckPredicate, 1, 94, 47, 0, // Skip to: 86948 -/* 74822 */ MCD_OPC_Decode, 184, 18, 155, 3, // Opcode: LDSETX -/* 74827 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 74842 -/* 74832 */ MCD_OPC_CheckPredicate, 1, 79, 47, 0, // Skip to: 86948 -/* 74837 */ MCD_OPC_Decode, 200, 18, 155, 3, // Opcode: LDSMAXX -/* 74842 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 74857 -/* 74847 */ MCD_OPC_CheckPredicate, 1, 64, 47, 0, // Skip to: 86948 -/* 74852 */ MCD_OPC_Decode, 216, 18, 155, 3, // Opcode: LDSMINX -/* 74857 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 74872 -/* 74862 */ MCD_OPC_CheckPredicate, 1, 49, 47, 0, // Skip to: 86948 -/* 74867 */ MCD_OPC_Decode, 241, 18, 155, 3, // Opcode: LDUMAXX -/* 74872 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 74887 -/* 74877 */ MCD_OPC_CheckPredicate, 1, 34, 47, 0, // Skip to: 86948 -/* 74882 */ MCD_OPC_Decode, 129, 19, 155, 3, // Opcode: LDUMINX -/* 74887 */ MCD_OPC_FilterValue, 8, 24, 47, 0, // Skip to: 86948 -/* 74892 */ MCD_OPC_CheckPredicate, 1, 19, 47, 0, // Skip to: 86948 -/* 74897 */ MCD_OPC_Decode, 168, 30, 155, 3, // Opcode: SWPX -/* 74902 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 74912 -/* 74907 */ MCD_OPC_Decode, 143, 19, 255, 2, // Opcode: LDURXi -/* 74912 */ MCD_OPC_FilterValue, 3, 255, 46, 0, // Skip to: 86948 -/* 74917 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 74920 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 74935 -/* 74925 */ MCD_OPC_CheckPredicate, 1, 242, 46, 0, // Skip to: 86948 -/* 74930 */ MCD_OPC_Decode, 218, 16, 155, 3, // Opcode: LDADDLX -/* 74935 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 74950 -/* 74940 */ MCD_OPC_CheckPredicate, 1, 227, 46, 0, // Skip to: 86948 -/* 74945 */ MCD_OPC_Decode, 129, 17, 155, 3, // Opcode: LDCLRLX -/* 74950 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 74965 -/* 74955 */ MCD_OPC_CheckPredicate, 1, 212, 46, 0, // Skip to: 86948 -/* 74960 */ MCD_OPC_Decode, 145, 17, 155, 3, // Opcode: LDEORLX -/* 74965 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 74980 -/* 74970 */ MCD_OPC_CheckPredicate, 1, 197, 46, 0, // Skip to: 86948 -/* 74975 */ MCD_OPC_Decode, 182, 18, 155, 3, // Opcode: LDSETLX -/* 74980 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 74995 -/* 74985 */ MCD_OPC_CheckPredicate, 1, 182, 46, 0, // Skip to: 86948 -/* 74990 */ MCD_OPC_Decode, 198, 18, 155, 3, // Opcode: LDSMAXLX -/* 74995 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75010 -/* 75000 */ MCD_OPC_CheckPredicate, 1, 167, 46, 0, // Skip to: 86948 -/* 75005 */ MCD_OPC_Decode, 214, 18, 155, 3, // Opcode: LDSMINLX -/* 75010 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 75025 -/* 75015 */ MCD_OPC_CheckPredicate, 1, 152, 46, 0, // Skip to: 86948 -/* 75020 */ MCD_OPC_Decode, 239, 18, 155, 3, // Opcode: LDUMAXLX -/* 75025 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75040 -/* 75030 */ MCD_OPC_CheckPredicate, 1, 137, 46, 0, // Skip to: 86948 -/* 75035 */ MCD_OPC_Decode, 255, 18, 155, 3, // Opcode: LDUMINLX -/* 75040 */ MCD_OPC_FilterValue, 8, 127, 46, 0, // Skip to: 86948 -/* 75045 */ MCD_OPC_CheckPredicate, 1, 122, 46, 0, // Skip to: 86948 -/* 75050 */ MCD_OPC_Decode, 166, 30, 155, 3, // Opcode: SWPLX -/* 75055 */ MCD_OPC_FilterValue, 1, 46, 0, 0, // Skip to: 75106 -/* 75060 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 75063 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 75091 -/* 75068 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 75071 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75081 -/* 75076 */ MCD_OPC_Decode, 185, 29, 255, 2, // Opcode: STRXpost -/* 75081 */ MCD_OPC_FilterValue, 1, 86, 46, 0, // Skip to: 86948 -/* 75086 */ MCD_OPC_Decode, 162, 18, 255, 2, // Opcode: LDRXpost -/* 75091 */ MCD_OPC_FilterValue, 1, 76, 46, 0, // Skip to: 86948 -/* 75096 */ MCD_OPC_CheckPredicate, 13, 71, 46, 0, // Skip to: 86948 -/* 75101 */ MCD_OPC_Decode, 215, 17, 156, 3, // Opcode: LDRAAindexed -/* 75106 */ MCD_OPC_FilterValue, 2, 79, 0, 0, // Skip to: 75190 -/* 75111 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 75114 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75124 -/* 75119 */ MCD_OPC_Decode, 195, 29, 255, 2, // Opcode: STTRXi -/* 75124 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 75152 -/* 75129 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 75132 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 75142 -/* 75137 */ MCD_OPC_Decode, 187, 29, 135, 3, // Opcode: STRXroW -/* 75142 */ MCD_OPC_FilterValue, 3, 25, 46, 0, // Skip to: 86948 -/* 75147 */ MCD_OPC_Decode, 188, 29, 136, 3, // Opcode: STRXroX -/* 75152 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 75162 -/* 75157 */ MCD_OPC_Decode, 225, 18, 255, 2, // Opcode: LDTRXi -/* 75162 */ MCD_OPC_FilterValue, 3, 5, 46, 0, // Skip to: 86948 -/* 75167 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 75170 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 75180 -/* 75175 */ MCD_OPC_Decode, 164, 18, 135, 3, // Opcode: LDRXroW -/* 75180 */ MCD_OPC_FilterValue, 3, 243, 45, 0, // Skip to: 86948 -/* 75185 */ MCD_OPC_Decode, 165, 18, 136, 3, // Opcode: LDRXroX -/* 75190 */ MCD_OPC_FilterValue, 3, 233, 45, 0, // Skip to: 86948 -/* 75195 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 75198 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 75226 -/* 75203 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 75206 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75216 -/* 75211 */ MCD_OPC_Decode, 186, 29, 255, 2, // Opcode: STRXpre -/* 75216 */ MCD_OPC_FilterValue, 1, 207, 45, 0, // Skip to: 86948 -/* 75221 */ MCD_OPC_Decode, 163, 18, 255, 2, // Opcode: LDRXpre -/* 75226 */ MCD_OPC_FilterValue, 1, 197, 45, 0, // Skip to: 86948 -/* 75231 */ MCD_OPC_CheckPredicate, 13, 192, 45, 0, // Skip to: 86948 -/* 75236 */ MCD_OPC_Decode, 216, 17, 157, 3, // Opcode: LDRAAwriteback -/* 75241 */ MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 75661 -/* 75246 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 75249 */ MCD_OPC_FilterValue, 0, 65, 1, 0, // Skip to: 75575 -/* 75254 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 75257 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75267 -/* 75262 */ MCD_OPC_Decode, 157, 21, 255, 2, // Opcode: PRFUMi -/* 75267 */ MCD_OPC_FilterValue, 1, 160, 0, 0, // Skip to: 75432 -/* 75272 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 75275 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 75290 -/* 75280 */ MCD_OPC_CheckPredicate, 1, 143, 45, 0, // Skip to: 86948 -/* 75285 */ MCD_OPC_Decode, 212, 16, 155, 3, // Opcode: LDADDAX -/* 75290 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 75305 -/* 75295 */ MCD_OPC_CheckPredicate, 1, 128, 45, 0, // Skip to: 86948 -/* 75300 */ MCD_OPC_Decode, 251, 16, 155, 3, // Opcode: LDCLRAX -/* 75305 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 75320 -/* 75310 */ MCD_OPC_CheckPredicate, 1, 113, 45, 0, // Skip to: 86948 -/* 75315 */ MCD_OPC_Decode, 139, 17, 155, 3, // Opcode: LDEORAX -/* 75320 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 75335 -/* 75325 */ MCD_OPC_CheckPredicate, 1, 98, 45, 0, // Skip to: 86948 -/* 75330 */ MCD_OPC_Decode, 176, 18, 155, 3, // Opcode: LDSETAX -/* 75335 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 75350 -/* 75340 */ MCD_OPC_CheckPredicate, 1, 83, 45, 0, // Skip to: 86948 -/* 75345 */ MCD_OPC_Decode, 192, 18, 155, 3, // Opcode: LDSMAXAX -/* 75350 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75365 -/* 75355 */ MCD_OPC_CheckPredicate, 1, 68, 45, 0, // Skip to: 86948 -/* 75360 */ MCD_OPC_Decode, 208, 18, 155, 3, // Opcode: LDSMINAX -/* 75365 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 75380 -/* 75370 */ MCD_OPC_CheckPredicate, 1, 53, 45, 0, // Skip to: 86948 -/* 75375 */ MCD_OPC_Decode, 233, 18, 155, 3, // Opcode: LDUMAXAX -/* 75380 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75395 -/* 75385 */ MCD_OPC_CheckPredicate, 1, 38, 45, 0, // Skip to: 86948 -/* 75390 */ MCD_OPC_Decode, 249, 18, 155, 3, // Opcode: LDUMINAX -/* 75395 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 75410 -/* 75400 */ MCD_OPC_CheckPredicate, 1, 23, 45, 0, // Skip to: 86948 -/* 75405 */ MCD_OPC_Decode, 160, 30, 155, 3, // Opcode: SWPAX -/* 75410 */ MCD_OPC_FilterValue, 12, 13, 45, 0, // Skip to: 86948 -/* 75415 */ MCD_OPC_CheckPredicate, 15, 8, 45, 0, // Skip to: 86948 -/* 75420 */ MCD_OPC_CheckField, 16, 5, 31, 1, 45, 0, // Skip to: 86948 -/* 75427 */ MCD_OPC_Decode, 224, 16, 153, 3, // Opcode: LDAPRX -/* 75432 */ MCD_OPC_FilterValue, 3, 247, 44, 0, // Skip to: 86948 -/* 75437 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 75440 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 75455 -/* 75445 */ MCD_OPC_CheckPredicate, 1, 234, 44, 0, // Skip to: 86948 -/* 75450 */ MCD_OPC_Decode, 210, 16, 155, 3, // Opcode: LDADDALX -/* 75455 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 75470 -/* 75460 */ MCD_OPC_CheckPredicate, 1, 219, 44, 0, // Skip to: 86948 -/* 75465 */ MCD_OPC_Decode, 249, 16, 155, 3, // Opcode: LDCLRALX -/* 75470 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 75485 -/* 75475 */ MCD_OPC_CheckPredicate, 1, 204, 44, 0, // Skip to: 86948 -/* 75480 */ MCD_OPC_Decode, 137, 17, 155, 3, // Opcode: LDEORALX -/* 75485 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 75500 -/* 75490 */ MCD_OPC_CheckPredicate, 1, 189, 44, 0, // Skip to: 86948 -/* 75495 */ MCD_OPC_Decode, 174, 18, 155, 3, // Opcode: LDSETALX -/* 75500 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 75515 -/* 75505 */ MCD_OPC_CheckPredicate, 1, 174, 44, 0, // Skip to: 86948 -/* 75510 */ MCD_OPC_Decode, 190, 18, 155, 3, // Opcode: LDSMAXALX -/* 75515 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75530 -/* 75520 */ MCD_OPC_CheckPredicate, 1, 159, 44, 0, // Skip to: 86948 -/* 75525 */ MCD_OPC_Decode, 206, 18, 155, 3, // Opcode: LDSMINALX -/* 75530 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 75545 -/* 75535 */ MCD_OPC_CheckPredicate, 1, 144, 44, 0, // Skip to: 86948 -/* 75540 */ MCD_OPC_Decode, 231, 18, 155, 3, // Opcode: LDUMAXALX -/* 75545 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75560 -/* 75550 */ MCD_OPC_CheckPredicate, 1, 129, 44, 0, // Skip to: 86948 -/* 75555 */ MCD_OPC_Decode, 247, 18, 155, 3, // Opcode: LDUMINALX -/* 75560 */ MCD_OPC_FilterValue, 8, 119, 44, 0, // Skip to: 86948 -/* 75565 */ MCD_OPC_CheckPredicate, 1, 114, 44, 0, // Skip to: 86948 -/* 75570 */ MCD_OPC_Decode, 158, 30, 155, 3, // Opcode: SWPALX -/* 75575 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 75597 -/* 75580 */ MCD_OPC_CheckPredicate, 13, 99, 44, 0, // Skip to: 86948 -/* 75585 */ MCD_OPC_CheckField, 21, 1, 1, 92, 44, 0, // Skip to: 86948 -/* 75592 */ MCD_OPC_Decode, 217, 17, 156, 3, // Opcode: LDRABindexed -/* 75597 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 75639 -/* 75602 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 75605 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 75622 -/* 75610 */ MCD_OPC_CheckField, 21, 2, 1, 67, 44, 0, // Skip to: 86948 -/* 75617 */ MCD_OPC_Decode, 153, 21, 158, 3, // Opcode: PRFMroW -/* 75622 */ MCD_OPC_FilterValue, 3, 57, 44, 0, // Skip to: 86948 -/* 75627 */ MCD_OPC_CheckField, 21, 2, 1, 50, 44, 0, // Skip to: 86948 -/* 75634 */ MCD_OPC_Decode, 154, 21, 159, 3, // Opcode: PRFMroX -/* 75639 */ MCD_OPC_FilterValue, 3, 40, 44, 0, // Skip to: 86948 -/* 75644 */ MCD_OPC_CheckPredicate, 13, 35, 44, 0, // Skip to: 86948 -/* 75649 */ MCD_OPC_CheckField, 21, 1, 1, 28, 44, 0, // Skip to: 86948 -/* 75656 */ MCD_OPC_Decode, 218, 17, 157, 3, // Opcode: LDRABwriteback -/* 75661 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 75689 -/* 75666 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 75669 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75679 -/* 75674 */ MCD_OPC_Decode, 189, 29, 137, 3, // Opcode: STRXui -/* 75679 */ MCD_OPC_FilterValue, 1, 0, 44, 0, // Skip to: 86948 -/* 75684 */ MCD_OPC_Decode, 166, 18, 137, 3, // Opcode: LDRXui -/* 75689 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 75706 -/* 75694 */ MCD_OPC_CheckField, 22, 1, 0, 239, 43, 0, // Skip to: 86948 -/* 75701 */ MCD_OPC_Decode, 155, 21, 137, 3, // Opcode: PRFMui -/* 75706 */ MCD_OPC_FilterValue, 4, 229, 43, 0, // Skip to: 86948 -/* 75711 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 75714 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 75756 -/* 75719 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 75722 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 75739 -/* 75727 */ MCD_OPC_CheckField, 12, 4, 0, 206, 43, 0, // Skip to: 86948 -/* 75734 */ MCD_OPC_Decode, 179, 22, 142, 3, // Opcode: SBCSXr -/* 75739 */ MCD_OPC_FilterValue, 2, 196, 43, 0, // Skip to: 86948 -/* 75744 */ MCD_OPC_CheckField, 4, 1, 0, 189, 43, 0, // Skip to: 86948 -/* 75751 */ MCD_OPC_Decode, 131, 3, 149, 3, // Opcode: CCMPXr -/* 75756 */ MCD_OPC_FilterValue, 2, 179, 43, 0, // Skip to: 86948 -/* 75761 */ MCD_OPC_CheckField, 21, 2, 2, 172, 43, 0, // Skip to: 86948 -/* 75768 */ MCD_OPC_CheckField, 4, 1, 0, 165, 43, 0, // Skip to: 86948 -/* 75775 */ MCD_OPC_Decode, 130, 3, 150, 3, // Opcode: CCMPXi -/* 75780 */ MCD_OPC_FilterValue, 7, 155, 43, 0, // Skip to: 86948 -/* 75785 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 75788 */ MCD_OPC_FilterValue, 0, 103, 10, 0, // Skip to: 78456 -/* 75793 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 75796 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75806 -/* 75801 */ MCD_OPC_Decode, 149, 18, 160, 3, // Opcode: LDRSl -/* 75806 */ MCD_OPC_FilterValue, 2, 105, 9, 0, // Skip to: 78220 -/* 75811 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 75814 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 75882 -/* 75819 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... -/* 75822 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75837 -/* 75827 */ MCD_OPC_CheckPredicate, 16, 108, 43, 0, // Skip to: 86948 -/* 75832 */ MCD_OPC_Decode, 186, 22, 161, 3, // Opcode: SCVTFSWSri -/* 75837 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75852 -/* 75842 */ MCD_OPC_CheckPredicate, 16, 93, 43, 0, // Skip to: 86948 -/* 75847 */ MCD_OPC_Decode, 173, 31, 161, 3, // Opcode: UCVTFSWSri -/* 75852 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 75867 -/* 75857 */ MCD_OPC_CheckPredicate, 16, 78, 43, 0, // Skip to: 86948 -/* 75862 */ MCD_OPC_Decode, 220, 8, 162, 3, // Opcode: FCVTZSSWSri -/* 75867 */ MCD_OPC_FilterValue, 51, 68, 43, 0, // Skip to: 86948 -/* 75872 */ MCD_OPC_CheckPredicate, 16, 63, 43, 0, // Skip to: 86948 -/* 75877 */ MCD_OPC_Decode, 255, 8, 162, 3, // Opcode: FCVTZUSWSri -/* 75882 */ MCD_OPC_FilterValue, 1, 222, 2, 0, // Skip to: 76621 -/* 75887 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 75890 */ MCD_OPC_FilterValue, 0, 18, 2, 0, // Skip to: 76425 -/* 75895 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 75898 */ MCD_OPC_FilterValue, 0, 244, 1, 0, // Skip to: 76403 -/* 75903 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 75906 */ MCD_OPC_FilterValue, 0, 213, 0, 0, // Skip to: 76124 -/* 75911 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 75914 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 75929 -/* 75919 */ MCD_OPC_CheckPredicate, 16, 16, 43, 0, // Skip to: 86948 -/* 75924 */ MCD_OPC_Decode, 155, 8, 163, 3, // Opcode: FCVTNSUWSr -/* 75929 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 75944 -/* 75934 */ MCD_OPC_CheckPredicate, 16, 1, 43, 0, // Skip to: 86948 -/* 75939 */ MCD_OPC_Decode, 169, 8, 163, 3, // Opcode: FCVTNUUWSr -/* 75944 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 75959 -/* 75949 */ MCD_OPC_CheckPredicate, 16, 242, 42, 0, // Skip to: 86948 -/* 75954 */ MCD_OPC_Decode, 192, 22, 164, 3, // Opcode: SCVTFUWSri -/* 75959 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 75974 -/* 75964 */ MCD_OPC_CheckPredicate, 16, 227, 42, 0, // Skip to: 86948 -/* 75969 */ MCD_OPC_Decode, 179, 31, 164, 3, // Opcode: UCVTFUWSri -/* 75974 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 75989 -/* 75979 */ MCD_OPC_CheckPredicate, 16, 212, 42, 0, // Skip to: 86948 -/* 75984 */ MCD_OPC_Decode, 219, 7, 163, 3, // Opcode: FCVTASUWSr -/* 75989 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76004 -/* 75994 */ MCD_OPC_CheckPredicate, 16, 197, 42, 0, // Skip to: 86948 -/* 75999 */ MCD_OPC_Decode, 233, 7, 163, 3, // Opcode: FCVTAUUWSr -/* 76004 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76019 -/* 76009 */ MCD_OPC_CheckPredicate, 16, 182, 42, 0, // Skip to: 86948 -/* 76014 */ MCD_OPC_Decode, 226, 10, 163, 3, // Opcode: FMOVSWr -/* 76019 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 76034 -/* 76024 */ MCD_OPC_CheckPredicate, 16, 167, 42, 0, // Skip to: 86948 -/* 76029 */ MCD_OPC_Decode, 230, 10, 164, 3, // Opcode: FMOVWSr -/* 76034 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76049 -/* 76039 */ MCD_OPC_CheckPredicate, 16, 152, 42, 0, // Skip to: 86948 -/* 76044 */ MCD_OPC_Decode, 187, 8, 163, 3, // Opcode: FCVTPSUWSr -/* 76049 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 76064 -/* 76054 */ MCD_OPC_CheckPredicate, 16, 137, 42, 0, // Skip to: 86948 -/* 76059 */ MCD_OPC_Decode, 201, 8, 163, 3, // Opcode: FCVTPUUWSr -/* 76064 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76079 -/* 76069 */ MCD_OPC_CheckPredicate, 16, 122, 42, 0, // Skip to: 86948 -/* 76074 */ MCD_OPC_Decode, 255, 7, 163, 3, // Opcode: FCVTMSUWSr -/* 76079 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 76094 -/* 76084 */ MCD_OPC_CheckPredicate, 16, 107, 42, 0, // Skip to: 86948 -/* 76089 */ MCD_OPC_Decode, 141, 8, 163, 3, // Opcode: FCVTMUUWSr -/* 76094 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 76109 -/* 76099 */ MCD_OPC_CheckPredicate, 16, 92, 42, 0, // Skip to: 86948 -/* 76104 */ MCD_OPC_Decode, 226, 8, 163, 3, // Opcode: FCVTZSUWSr -/* 76109 */ MCD_OPC_FilterValue, 25, 82, 42, 0, // Skip to: 86948 -/* 76114 */ MCD_OPC_CheckPredicate, 16, 77, 42, 0, // Skip to: 86948 -/* 76119 */ MCD_OPC_Decode, 133, 9, 163, 3, // Opcode: FCVTZUUWSr -/* 76124 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 76192 -/* 76129 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 76132 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76147 -/* 76137 */ MCD_OPC_CheckPredicate, 16, 54, 42, 0, // Skip to: 86948 -/* 76142 */ MCD_OPC_Decode, 207, 7, 165, 3, // Opcode: FCMPSrr -/* 76147 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76162 -/* 76152 */ MCD_OPC_CheckPredicate, 16, 39, 42, 0, // Skip to: 86948 -/* 76157 */ MCD_OPC_Decode, 206, 7, 166, 3, // Opcode: FCMPSri -/* 76162 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76177 -/* 76167 */ MCD_OPC_CheckPredicate, 16, 24, 42, 0, // Skip to: 86948 -/* 76172 */ MCD_OPC_Decode, 203, 7, 165, 3, // Opcode: FCMPESrr -/* 76177 */ MCD_OPC_FilterValue, 24, 14, 42, 0, // Skip to: 86948 -/* 76182 */ MCD_OPC_CheckPredicate, 16, 9, 42, 0, // Skip to: 86948 -/* 76187 */ MCD_OPC_Decode, 202, 7, 166, 3, // Opcode: FCMPESri -/* 76192 */ MCD_OPC_FilterValue, 2, 93, 0, 0, // Skip to: 76290 -/* 76197 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 76200 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76215 -/* 76205 */ MCD_OPC_CheckPredicate, 16, 242, 41, 0, // Skip to: 86948 -/* 76210 */ MCD_OPC_Decode, 228, 10, 167, 3, // Opcode: FMOVSr -/* 76215 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76230 -/* 76220 */ MCD_OPC_CheckPredicate, 16, 227, 41, 0, // Skip to: 86948 -/* 76225 */ MCD_OPC_Decode, 166, 11, 167, 3, // Opcode: FNEGSr -/* 76230 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76245 -/* 76235 */ MCD_OPC_CheckPredicate, 16, 212, 41, 0, // Skip to: 86948 -/* 76240 */ MCD_OPC_Decode, 131, 12, 167, 3, // Opcode: FRINTNSr -/* 76245 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76260 -/* 76250 */ MCD_OPC_CheckPredicate, 16, 197, 41, 0, // Skip to: 86948 -/* 76255 */ MCD_OPC_Decode, 248, 11, 167, 3, // Opcode: FRINTMSr -/* 76260 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76275 -/* 76265 */ MCD_OPC_CheckPredicate, 16, 182, 41, 0, // Skip to: 86948 -/* 76270 */ MCD_OPC_Decode, 226, 11, 167, 3, // Opcode: FRINTASr -/* 76275 */ MCD_OPC_FilterValue, 7, 172, 41, 0, // Skip to: 86948 -/* 76280 */ MCD_OPC_CheckPredicate, 16, 167, 41, 0, // Skip to: 86948 -/* 76285 */ MCD_OPC_Decode, 153, 12, 167, 3, // Opcode: FRINTXSr -/* 76290 */ MCD_OPC_FilterValue, 6, 157, 41, 0, // Skip to: 86948 -/* 76295 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 76298 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76313 -/* 76303 */ MCD_OPC_CheckPredicate, 16, 144, 41, 0, // Skip to: 86948 -/* 76308 */ MCD_OPC_Decode, 141, 6, 167, 3, // Opcode: FABSSr -/* 76313 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76328 -/* 76318 */ MCD_OPC_CheckPredicate, 16, 129, 41, 0, // Skip to: 86948 -/* 76323 */ MCD_OPC_Decode, 200, 12, 167, 3, // Opcode: FSQRTSr -/* 76328 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 76343 -/* 76333 */ MCD_OPC_CheckPredicate, 16, 114, 41, 0, // Skip to: 86948 -/* 76338 */ MCD_OPC_Decode, 246, 7, 168, 3, // Opcode: FCVTDSr -/* 76343 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 76358 -/* 76348 */ MCD_OPC_CheckPredicate, 16, 99, 41, 0, // Skip to: 86948 -/* 76353 */ MCD_OPC_Decode, 248, 7, 169, 3, // Opcode: FCVTHSr -/* 76358 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76373 -/* 76363 */ MCD_OPC_CheckPredicate, 16, 84, 41, 0, // Skip to: 86948 -/* 76368 */ MCD_OPC_Decode, 142, 12, 167, 3, // Opcode: FRINTPSr -/* 76373 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76388 -/* 76378 */ MCD_OPC_CheckPredicate, 16, 69, 41, 0, // Skip to: 86948 -/* 76383 */ MCD_OPC_Decode, 164, 12, 167, 3, // Opcode: FRINTZSr -/* 76388 */ MCD_OPC_FilterValue, 7, 59, 41, 0, // Skip to: 86948 -/* 76393 */ MCD_OPC_CheckPredicate, 16, 54, 41, 0, // Skip to: 86948 -/* 76398 */ MCD_OPC_Decode, 237, 11, 167, 3, // Opcode: FRINTISr -/* 76403 */ MCD_OPC_FilterValue, 1, 44, 41, 0, // Skip to: 86948 -/* 76408 */ MCD_OPC_CheckPredicate, 16, 39, 41, 0, // Skip to: 86948 -/* 76413 */ MCD_OPC_CheckField, 5, 5, 0, 32, 41, 0, // Skip to: 86948 -/* 76420 */ MCD_OPC_Decode, 227, 10, 170, 3, // Opcode: FMOVSi -/* 76425 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 76463 -/* 76430 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 76433 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76448 -/* 76438 */ MCD_OPC_CheckPredicate, 16, 9, 41, 0, // Skip to: 86948 -/* 76443 */ MCD_OPC_Decode, 216, 6, 171, 3, // Opcode: FCCMPSrr -/* 76448 */ MCD_OPC_FilterValue, 1, 255, 40, 0, // Skip to: 86948 -/* 76453 */ MCD_OPC_CheckPredicate, 16, 250, 40, 0, // Skip to: 86948 -/* 76458 */ MCD_OPC_Decode, 214, 6, 171, 3, // Opcode: FCCMPESrr -/* 76463 */ MCD_OPC_FilterValue, 2, 138, 0, 0, // Skip to: 76606 -/* 76468 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 76471 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76486 -/* 76476 */ MCD_OPC_CheckPredicate, 16, 227, 40, 0, // Skip to: 86948 -/* 76481 */ MCD_OPC_Decode, 247, 10, 172, 3, // Opcode: FMULSrr -/* 76486 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76501 -/* 76491 */ MCD_OPC_CheckPredicate, 16, 212, 40, 0, // Skip to: 86948 -/* 76496 */ MCD_OPC_Decode, 171, 9, 172, 3, // Opcode: FDIVSrr -/* 76501 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 76516 -/* 76506 */ MCD_OPC_CheckPredicate, 16, 197, 40, 0, // Skip to: 86948 -/* 76511 */ MCD_OPC_Decode, 185, 6, 172, 3, // Opcode: FADDSrr -/* 76516 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 76531 -/* 76521 */ MCD_OPC_CheckPredicate, 16, 182, 40, 0, // Skip to: 86948 -/* 76526 */ MCD_OPC_Decode, 217, 12, 172, 3, // Opcode: FSUBSrr -/* 76531 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76546 -/* 76536 */ MCD_OPC_CheckPredicate, 16, 167, 40, 0, // Skip to: 86948 -/* 76541 */ MCD_OPC_Decode, 231, 9, 172, 3, // Opcode: FMAXSrr -/* 76546 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76561 -/* 76551 */ MCD_OPC_CheckPredicate, 16, 152, 40, 0, // Skip to: 86948 -/* 76556 */ MCD_OPC_Decode, 159, 10, 172, 3, // Opcode: FMINSrr -/* 76561 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76576 -/* 76566 */ MCD_OPC_CheckPredicate, 16, 137, 40, 0, // Skip to: 86948 -/* 76571 */ MCD_OPC_Decode, 205, 9, 172, 3, // Opcode: FMAXNMSrr -/* 76576 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 76591 -/* 76581 */ MCD_OPC_CheckPredicate, 16, 122, 40, 0, // Skip to: 86948 -/* 76586 */ MCD_OPC_Decode, 133, 10, 172, 3, // Opcode: FMINNMSrr -/* 76591 */ MCD_OPC_FilterValue, 8, 112, 40, 0, // Skip to: 86948 -/* 76596 */ MCD_OPC_CheckPredicate, 16, 107, 40, 0, // Skip to: 86948 -/* 76601 */ MCD_OPC_Decode, 195, 11, 172, 3, // Opcode: FNMULSrr -/* 76606 */ MCD_OPC_FilterValue, 3, 97, 40, 0, // Skip to: 86948 -/* 76611 */ MCD_OPC_CheckPredicate, 16, 92, 40, 0, // Skip to: 86948 -/* 76616 */ MCD_OPC_Decode, 216, 7, 173, 3, // Opcode: FCSELSrrr -/* 76621 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 76689 -/* 76626 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... -/* 76629 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76644 -/* 76634 */ MCD_OPC_CheckPredicate, 16, 69, 40, 0, // Skip to: 86948 -/* 76639 */ MCD_OPC_Decode, 184, 22, 174, 3, // Opcode: SCVTFSWDri -/* 76644 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 76659 -/* 76649 */ MCD_OPC_CheckPredicate, 16, 54, 40, 0, // Skip to: 86948 -/* 76654 */ MCD_OPC_Decode, 171, 31, 174, 3, // Opcode: UCVTFSWDri -/* 76659 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 76674 -/* 76664 */ MCD_OPC_CheckPredicate, 16, 39, 40, 0, // Skip to: 86948 -/* 76669 */ MCD_OPC_Decode, 218, 8, 175, 3, // Opcode: FCVTZSSWDri -/* 76674 */ MCD_OPC_FilterValue, 51, 29, 40, 0, // Skip to: 86948 -/* 76679 */ MCD_OPC_CheckPredicate, 16, 24, 40, 0, // Skip to: 86948 -/* 76684 */ MCD_OPC_Decode, 253, 8, 175, 3, // Opcode: FCVTZUSWDri -/* 76689 */ MCD_OPC_FilterValue, 3, 207, 2, 0, // Skip to: 77413 -/* 76694 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 76697 */ MCD_OPC_FilterValue, 0, 3, 2, 0, // Skip to: 77217 -/* 76702 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 76705 */ MCD_OPC_FilterValue, 0, 229, 1, 0, // Skip to: 77195 -/* 76710 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 76713 */ MCD_OPC_FilterValue, 0, 198, 0, 0, // Skip to: 76916 -/* 76718 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 76721 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76736 -/* 76726 */ MCD_OPC_CheckPredicate, 16, 233, 39, 0, // Skip to: 86948 -/* 76731 */ MCD_OPC_Decode, 153, 8, 176, 3, // Opcode: FCVTNSUWDr -/* 76736 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76751 -/* 76741 */ MCD_OPC_CheckPredicate, 16, 218, 39, 0, // Skip to: 86948 -/* 76746 */ MCD_OPC_Decode, 167, 8, 176, 3, // Opcode: FCVTNUUWDr -/* 76751 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 76766 -/* 76756 */ MCD_OPC_CheckPredicate, 16, 203, 39, 0, // Skip to: 86948 -/* 76761 */ MCD_OPC_Decode, 190, 22, 240, 1, // Opcode: SCVTFUWDri -/* 76766 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 76781 -/* 76771 */ MCD_OPC_CheckPredicate, 16, 188, 39, 0, // Skip to: 86948 -/* 76776 */ MCD_OPC_Decode, 177, 31, 240, 1, // Opcode: UCVTFUWDri -/* 76781 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76796 -/* 76786 */ MCD_OPC_CheckPredicate, 16, 173, 39, 0, // Skip to: 86948 -/* 76791 */ MCD_OPC_Decode, 217, 7, 176, 3, // Opcode: FCVTASUWDr -/* 76796 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76811 -/* 76801 */ MCD_OPC_CheckPredicate, 16, 158, 39, 0, // Skip to: 86948 -/* 76806 */ MCD_OPC_Decode, 231, 7, 176, 3, // Opcode: FCVTAUUWDr -/* 76811 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76826 -/* 76816 */ MCD_OPC_CheckPredicate, 16, 143, 39, 0, // Skip to: 86948 -/* 76821 */ MCD_OPC_Decode, 185, 8, 176, 3, // Opcode: FCVTPSUWDr -/* 76826 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 76841 -/* 76831 */ MCD_OPC_CheckPredicate, 16, 128, 39, 0, // Skip to: 86948 -/* 76836 */ MCD_OPC_Decode, 199, 8, 176, 3, // Opcode: FCVTPUUWDr -/* 76841 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76856 -/* 76846 */ MCD_OPC_CheckPredicate, 16, 113, 39, 0, // Skip to: 86948 -/* 76851 */ MCD_OPC_Decode, 253, 7, 176, 3, // Opcode: FCVTMSUWDr -/* 76856 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 76871 -/* 76861 */ MCD_OPC_CheckPredicate, 16, 98, 39, 0, // Skip to: 86948 -/* 76866 */ MCD_OPC_Decode, 139, 8, 176, 3, // Opcode: FCVTMUUWDr -/* 76871 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 76886 -/* 76876 */ MCD_OPC_CheckPredicate, 16, 83, 39, 0, // Skip to: 86948 -/* 76881 */ MCD_OPC_Decode, 224, 8, 176, 3, // Opcode: FCVTZSUWDr -/* 76886 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 76901 -/* 76891 */ MCD_OPC_CheckPredicate, 16, 68, 39, 0, // Skip to: 86948 -/* 76896 */ MCD_OPC_Decode, 131, 9, 176, 3, // Opcode: FCVTZUUWDr -/* 76901 */ MCD_OPC_FilterValue, 30, 58, 39, 0, // Skip to: 86948 -/* 76906 */ MCD_OPC_CheckPredicate, 17, 53, 39, 0, // Skip to: 86948 -/* 76911 */ MCD_OPC_Decode, 186, 9, 176, 3, // Opcode: FJCVTZS -/* 76916 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 76984 -/* 76921 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 76924 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76939 -/* 76929 */ MCD_OPC_CheckPredicate, 16, 30, 39, 0, // Skip to: 86948 -/* 76934 */ MCD_OPC_Decode, 197, 7, 177, 3, // Opcode: FCMPDrr -/* 76939 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76954 -/* 76944 */ MCD_OPC_CheckPredicate, 16, 15, 39, 0, // Skip to: 86948 -/* 76949 */ MCD_OPC_Decode, 196, 7, 178, 3, // Opcode: FCMPDri -/* 76954 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76969 -/* 76959 */ MCD_OPC_CheckPredicate, 16, 0, 39, 0, // Skip to: 86948 -/* 76964 */ MCD_OPC_Decode, 199, 7, 177, 3, // Opcode: FCMPEDrr -/* 76969 */ MCD_OPC_FilterValue, 24, 246, 38, 0, // Skip to: 86948 -/* 76974 */ MCD_OPC_CheckPredicate, 16, 241, 38, 0, // Skip to: 86948 -/* 76979 */ MCD_OPC_Decode, 198, 7, 178, 3, // Opcode: FCMPEDri -/* 76984 */ MCD_OPC_FilterValue, 2, 108, 0, 0, // Skip to: 77097 -/* 76989 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 76992 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77007 -/* 76997 */ MCD_OPC_CheckPredicate, 16, 218, 38, 0, // Skip to: 86948 -/* 77002 */ MCD_OPC_Decode, 219, 10, 239, 1, // Opcode: FMOVDr -/* 77007 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77022 -/* 77012 */ MCD_OPC_CheckPredicate, 16, 203, 38, 0, // Skip to: 86948 -/* 77017 */ MCD_OPC_Decode, 164, 11, 239, 1, // Opcode: FNEGDr -/* 77022 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77037 -/* 77027 */ MCD_OPC_CheckPredicate, 16, 188, 38, 0, // Skip to: 86948 -/* 77032 */ MCD_OPC_Decode, 213, 8, 166, 2, // Opcode: FCVTSDr -/* 77037 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77052 -/* 77042 */ MCD_OPC_CheckPredicate, 16, 173, 38, 0, // Skip to: 86948 -/* 77047 */ MCD_OPC_Decode, 129, 12, 239, 1, // Opcode: FRINTNDr -/* 77052 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77067 -/* 77057 */ MCD_OPC_CheckPredicate, 16, 158, 38, 0, // Skip to: 86948 -/* 77062 */ MCD_OPC_Decode, 246, 11, 239, 1, // Opcode: FRINTMDr -/* 77067 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77082 -/* 77072 */ MCD_OPC_CheckPredicate, 16, 143, 38, 0, // Skip to: 86948 -/* 77077 */ MCD_OPC_Decode, 224, 11, 239, 1, // Opcode: FRINTADr -/* 77082 */ MCD_OPC_FilterValue, 7, 133, 38, 0, // Skip to: 86948 -/* 77087 */ MCD_OPC_CheckPredicate, 16, 128, 38, 0, // Skip to: 86948 -/* 77092 */ MCD_OPC_Decode, 151, 12, 239, 1, // Opcode: FRINTXDr -/* 77097 */ MCD_OPC_FilterValue, 6, 118, 38, 0, // Skip to: 86948 -/* 77102 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 77105 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77120 -/* 77110 */ MCD_OPC_CheckPredicate, 16, 105, 38, 0, // Skip to: 86948 -/* 77115 */ MCD_OPC_Decode, 139, 6, 239, 1, // Opcode: FABSDr -/* 77120 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77135 -/* 77125 */ MCD_OPC_CheckPredicate, 16, 90, 38, 0, // Skip to: 86948 -/* 77130 */ MCD_OPC_Decode, 198, 12, 239, 1, // Opcode: FSQRTDr -/* 77135 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 77150 -/* 77140 */ MCD_OPC_CheckPredicate, 16, 75, 38, 0, // Skip to: 86948 -/* 77145 */ MCD_OPC_Decode, 247, 7, 249, 1, // Opcode: FCVTHDr -/* 77150 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77165 -/* 77155 */ MCD_OPC_CheckPredicate, 16, 60, 38, 0, // Skip to: 86948 -/* 77160 */ MCD_OPC_Decode, 140, 12, 239, 1, // Opcode: FRINTPDr -/* 77165 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77180 -/* 77170 */ MCD_OPC_CheckPredicate, 16, 45, 38, 0, // Skip to: 86948 -/* 77175 */ MCD_OPC_Decode, 162, 12, 239, 1, // Opcode: FRINTZDr -/* 77180 */ MCD_OPC_FilterValue, 7, 35, 38, 0, // Skip to: 86948 -/* 77185 */ MCD_OPC_CheckPredicate, 16, 30, 38, 0, // Skip to: 86948 -/* 77190 */ MCD_OPC_Decode, 235, 11, 239, 1, // Opcode: FRINTIDr -/* 77195 */ MCD_OPC_FilterValue, 1, 20, 38, 0, // Skip to: 86948 -/* 77200 */ MCD_OPC_CheckPredicate, 16, 15, 38, 0, // Skip to: 86948 -/* 77205 */ MCD_OPC_CheckField, 5, 5, 0, 8, 38, 0, // Skip to: 86948 -/* 77212 */ MCD_OPC_Decode, 218, 10, 179, 3, // Opcode: FMOVDi -/* 77217 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 77255 -/* 77222 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 77225 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77240 -/* 77230 */ MCD_OPC_CheckPredicate, 16, 241, 37, 0, // Skip to: 86948 -/* 77235 */ MCD_OPC_Decode, 211, 6, 180, 3, // Opcode: FCCMPDrr -/* 77240 */ MCD_OPC_FilterValue, 1, 231, 37, 0, // Skip to: 86948 -/* 77245 */ MCD_OPC_CheckPredicate, 16, 226, 37, 0, // Skip to: 86948 -/* 77250 */ MCD_OPC_Decode, 212, 6, 180, 3, // Opcode: FCCMPEDrr -/* 77255 */ MCD_OPC_FilterValue, 2, 138, 0, 0, // Skip to: 77398 -/* 77260 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 77263 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77278 -/* 77268 */ MCD_OPC_CheckPredicate, 16, 203, 37, 0, // Skip to: 86948 -/* 77273 */ MCD_OPC_Decode, 245, 10, 238, 1, // Opcode: FMULDrr -/* 77278 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77293 -/* 77283 */ MCD_OPC_CheckPredicate, 16, 188, 37, 0, // Skip to: 86948 -/* 77288 */ MCD_OPC_Decode, 166, 9, 238, 1, // Opcode: FDIVDrr -/* 77293 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77308 -/* 77298 */ MCD_OPC_CheckPredicate, 16, 173, 37, 0, // Skip to: 86948 -/* 77303 */ MCD_OPC_Decode, 175, 6, 238, 1, // Opcode: FADDDrr -/* 77308 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 77323 -/* 77313 */ MCD_OPC_CheckPredicate, 16, 158, 37, 0, // Skip to: 86948 -/* 77318 */ MCD_OPC_Decode, 209, 12, 238, 1, // Opcode: FSUBDrr -/* 77323 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77338 -/* 77328 */ MCD_OPC_CheckPredicate, 16, 143, 37, 0, // Skip to: 86948 -/* 77333 */ MCD_OPC_Decode, 193, 9, 238, 1, // Opcode: FMAXDrr -/* 77338 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77353 -/* 77343 */ MCD_OPC_CheckPredicate, 16, 128, 37, 0, // Skip to: 86948 -/* 77348 */ MCD_OPC_Decode, 249, 9, 238, 1, // Opcode: FMINDrr -/* 77353 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77368 -/* 77358 */ MCD_OPC_CheckPredicate, 16, 113, 37, 0, // Skip to: 86948 -/* 77363 */ MCD_OPC_Decode, 195, 9, 238, 1, // Opcode: FMAXNMDrr -/* 77368 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 77383 -/* 77373 */ MCD_OPC_CheckPredicate, 16, 98, 37, 0, // Skip to: 86948 -/* 77378 */ MCD_OPC_Decode, 251, 9, 238, 1, // Opcode: FMINNMDrr -/* 77383 */ MCD_OPC_FilterValue, 8, 88, 37, 0, // Skip to: 86948 -/* 77388 */ MCD_OPC_CheckPredicate, 16, 83, 37, 0, // Skip to: 86948 -/* 77393 */ MCD_OPC_Decode, 193, 11, 238, 1, // Opcode: FNMULDrr -/* 77398 */ MCD_OPC_FilterValue, 3, 73, 37, 0, // Skip to: 86948 -/* 77403 */ MCD_OPC_CheckPredicate, 16, 68, 37, 0, // Skip to: 86948 -/* 77408 */ MCD_OPC_Decode, 214, 7, 181, 3, // Opcode: FCSELDrrr -/* 77413 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 77481 -/* 77418 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... -/* 77421 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77436 -/* 77426 */ MCD_OPC_CheckPredicate, 18, 45, 37, 0, // Skip to: 86948 -/* 77431 */ MCD_OPC_Decode, 185, 22, 182, 3, // Opcode: SCVTFSWHri -/* 77436 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 77451 -/* 77441 */ MCD_OPC_CheckPredicate, 18, 30, 37, 0, // Skip to: 86948 -/* 77446 */ MCD_OPC_Decode, 172, 31, 182, 3, // Opcode: UCVTFSWHri -/* 77451 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 77466 -/* 77456 */ MCD_OPC_CheckPredicate, 18, 15, 37, 0, // Skip to: 86948 -/* 77461 */ MCD_OPC_Decode, 219, 8, 183, 3, // Opcode: FCVTZSSWHri -/* 77466 */ MCD_OPC_FilterValue, 51, 5, 37, 0, // Skip to: 86948 -/* 77471 */ MCD_OPC_CheckPredicate, 18, 0, 37, 0, // Skip to: 86948 -/* 77476 */ MCD_OPC_Decode, 254, 8, 183, 3, // Opcode: FCVTZUSWHri -/* 77481 */ MCD_OPC_FilterValue, 7, 246, 36, 0, // Skip to: 86948 -/* 77486 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 77489 */ MCD_OPC_FilterValue, 0, 18, 2, 0, // Skip to: 78024 -/* 77494 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 77497 */ MCD_OPC_FilterValue, 0, 244, 1, 0, // Skip to: 78002 -/* 77502 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 77505 */ MCD_OPC_FilterValue, 0, 213, 0, 0, // Skip to: 77723 -/* 77510 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 77513 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77528 -/* 77518 */ MCD_OPC_CheckPredicate, 18, 209, 36, 0, // Skip to: 86948 -/* 77523 */ MCD_OPC_Decode, 154, 8, 184, 3, // Opcode: FCVTNSUWHr -/* 77528 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77543 -/* 77533 */ MCD_OPC_CheckPredicate, 18, 194, 36, 0, // Skip to: 86948 -/* 77538 */ MCD_OPC_Decode, 168, 8, 184, 3, // Opcode: FCVTNUUWHr -/* 77543 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77558 -/* 77548 */ MCD_OPC_CheckPredicate, 18, 179, 36, 0, // Skip to: 86948 -/* 77553 */ MCD_OPC_Decode, 191, 22, 185, 3, // Opcode: SCVTFUWHri -/* 77558 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 77573 -/* 77563 */ MCD_OPC_CheckPredicate, 18, 164, 36, 0, // Skip to: 86948 -/* 77568 */ MCD_OPC_Decode, 178, 31, 185, 3, // Opcode: UCVTFUWHri -/* 77573 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77588 -/* 77578 */ MCD_OPC_CheckPredicate, 18, 149, 36, 0, // Skip to: 86948 -/* 77583 */ MCD_OPC_Decode, 218, 7, 184, 3, // Opcode: FCVTASUWHr -/* 77588 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77603 -/* 77593 */ MCD_OPC_CheckPredicate, 18, 134, 36, 0, // Skip to: 86948 -/* 77598 */ MCD_OPC_Decode, 232, 7, 184, 3, // Opcode: FCVTAUUWHr -/* 77603 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77618 -/* 77608 */ MCD_OPC_CheckPredicate, 18, 119, 36, 0, // Skip to: 86948 -/* 77613 */ MCD_OPC_Decode, 221, 10, 184, 3, // Opcode: FMOVHWr -/* 77618 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 77633 -/* 77623 */ MCD_OPC_CheckPredicate, 18, 104, 36, 0, // Skip to: 86948 -/* 77628 */ MCD_OPC_Decode, 229, 10, 185, 3, // Opcode: FMOVWHr -/* 77633 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 77648 -/* 77638 */ MCD_OPC_CheckPredicate, 18, 89, 36, 0, // Skip to: 86948 -/* 77643 */ MCD_OPC_Decode, 186, 8, 184, 3, // Opcode: FCVTPSUWHr -/* 77648 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 77663 -/* 77653 */ MCD_OPC_CheckPredicate, 18, 74, 36, 0, // Skip to: 86948 -/* 77658 */ MCD_OPC_Decode, 200, 8, 184, 3, // Opcode: FCVTPUUWHr -/* 77663 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 77678 -/* 77668 */ MCD_OPC_CheckPredicate, 18, 59, 36, 0, // Skip to: 86948 -/* 77673 */ MCD_OPC_Decode, 254, 7, 184, 3, // Opcode: FCVTMSUWHr -/* 77678 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 77693 -/* 77683 */ MCD_OPC_CheckPredicate, 18, 44, 36, 0, // Skip to: 86948 -/* 77688 */ MCD_OPC_Decode, 140, 8, 184, 3, // Opcode: FCVTMUUWHr -/* 77693 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 77708 -/* 77698 */ MCD_OPC_CheckPredicate, 18, 29, 36, 0, // Skip to: 86948 -/* 77703 */ MCD_OPC_Decode, 225, 8, 184, 3, // Opcode: FCVTZSUWHr -/* 77708 */ MCD_OPC_FilterValue, 25, 19, 36, 0, // Skip to: 86948 -/* 77713 */ MCD_OPC_CheckPredicate, 18, 14, 36, 0, // Skip to: 86948 -/* 77718 */ MCD_OPC_Decode, 132, 9, 184, 3, // Opcode: FCVTZUUWHr -/* 77723 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 77791 -/* 77728 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 77731 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77746 -/* 77736 */ MCD_OPC_CheckPredicate, 18, 247, 35, 0, // Skip to: 86948 -/* 77741 */ MCD_OPC_Decode, 205, 7, 186, 3, // Opcode: FCMPHrr -/* 77746 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 77761 -/* 77751 */ MCD_OPC_CheckPredicate, 18, 232, 35, 0, // Skip to: 86948 -/* 77756 */ MCD_OPC_Decode, 204, 7, 187, 3, // Opcode: FCMPHri -/* 77761 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 77776 -/* 77766 */ MCD_OPC_CheckPredicate, 18, 217, 35, 0, // Skip to: 86948 -/* 77771 */ MCD_OPC_Decode, 201, 7, 186, 3, // Opcode: FCMPEHrr -/* 77776 */ MCD_OPC_FilterValue, 24, 207, 35, 0, // Skip to: 86948 -/* 77781 */ MCD_OPC_CheckPredicate, 18, 202, 35, 0, // Skip to: 86948 -/* 77786 */ MCD_OPC_Decode, 200, 7, 187, 3, // Opcode: FCMPEHri -/* 77791 */ MCD_OPC_FilterValue, 2, 108, 0, 0, // Skip to: 77904 -/* 77796 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 77799 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77814 -/* 77804 */ MCD_OPC_CheckPredicate, 18, 179, 35, 0, // Skip to: 86948 -/* 77809 */ MCD_OPC_Decode, 224, 10, 188, 3, // Opcode: FMOVHr -/* 77814 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77829 -/* 77819 */ MCD_OPC_CheckPredicate, 18, 164, 35, 0, // Skip to: 86948 -/* 77824 */ MCD_OPC_Decode, 165, 11, 188, 3, // Opcode: FNEGHr -/* 77829 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77844 -/* 77834 */ MCD_OPC_CheckPredicate, 16, 149, 35, 0, // Skip to: 86948 -/* 77839 */ MCD_OPC_Decode, 214, 8, 189, 3, // Opcode: FCVTSHr -/* 77844 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77859 -/* 77849 */ MCD_OPC_CheckPredicate, 18, 134, 35, 0, // Skip to: 86948 -/* 77854 */ MCD_OPC_Decode, 130, 12, 188, 3, // Opcode: FRINTNHr -/* 77859 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77874 -/* 77864 */ MCD_OPC_CheckPredicate, 18, 119, 35, 0, // Skip to: 86948 -/* 77869 */ MCD_OPC_Decode, 247, 11, 188, 3, // Opcode: FRINTMHr -/* 77874 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77889 -/* 77879 */ MCD_OPC_CheckPredicate, 18, 104, 35, 0, // Skip to: 86948 -/* 77884 */ MCD_OPC_Decode, 225, 11, 188, 3, // Opcode: FRINTAHr -/* 77889 */ MCD_OPC_FilterValue, 7, 94, 35, 0, // Skip to: 86948 -/* 77894 */ MCD_OPC_CheckPredicate, 18, 89, 35, 0, // Skip to: 86948 -/* 77899 */ MCD_OPC_Decode, 152, 12, 188, 3, // Opcode: FRINTXHr -/* 77904 */ MCD_OPC_FilterValue, 6, 79, 35, 0, // Skip to: 86948 -/* 77909 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 77912 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77927 -/* 77917 */ MCD_OPC_CheckPredicate, 18, 66, 35, 0, // Skip to: 86948 -/* 77922 */ MCD_OPC_Decode, 140, 6, 188, 3, // Opcode: FABSHr -/* 77927 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77942 -/* 77932 */ MCD_OPC_CheckPredicate, 18, 51, 35, 0, // Skip to: 86948 -/* 77937 */ MCD_OPC_Decode, 199, 12, 188, 3, // Opcode: FSQRTHr -/* 77942 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77957 -/* 77947 */ MCD_OPC_CheckPredicate, 16, 36, 35, 0, // Skip to: 86948 -/* 77952 */ MCD_OPC_Decode, 245, 7, 190, 3, // Opcode: FCVTDHr -/* 77957 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77972 -/* 77962 */ MCD_OPC_CheckPredicate, 18, 21, 35, 0, // Skip to: 86948 -/* 77967 */ MCD_OPC_Decode, 141, 12, 188, 3, // Opcode: FRINTPHr -/* 77972 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77987 -/* 77977 */ MCD_OPC_CheckPredicate, 18, 6, 35, 0, // Skip to: 86948 -/* 77982 */ MCD_OPC_Decode, 163, 12, 188, 3, // Opcode: FRINTZHr -/* 77987 */ MCD_OPC_FilterValue, 7, 252, 34, 0, // Skip to: 86948 -/* 77992 */ MCD_OPC_CheckPredicate, 18, 247, 34, 0, // Skip to: 86948 -/* 77997 */ MCD_OPC_Decode, 236, 11, 188, 3, // Opcode: FRINTIHr -/* 78002 */ MCD_OPC_FilterValue, 1, 237, 34, 0, // Skip to: 86948 -/* 78007 */ MCD_OPC_CheckPredicate, 18, 232, 34, 0, // Skip to: 86948 -/* 78012 */ MCD_OPC_CheckField, 5, 5, 0, 225, 34, 0, // Skip to: 86948 -/* 78019 */ MCD_OPC_Decode, 223, 10, 191, 3, // Opcode: FMOVHi -/* 78024 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 78062 -/* 78029 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 78032 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78047 -/* 78037 */ MCD_OPC_CheckPredicate, 18, 202, 34, 0, // Skip to: 86948 -/* 78042 */ MCD_OPC_Decode, 215, 6, 192, 3, // Opcode: FCCMPHrr -/* 78047 */ MCD_OPC_FilterValue, 1, 192, 34, 0, // Skip to: 86948 -/* 78052 */ MCD_OPC_CheckPredicate, 18, 187, 34, 0, // Skip to: 86948 -/* 78057 */ MCD_OPC_Decode, 213, 6, 192, 3, // Opcode: FCCMPEHrr -/* 78062 */ MCD_OPC_FilterValue, 2, 138, 0, 0, // Skip to: 78205 -/* 78067 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 78070 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78085 -/* 78075 */ MCD_OPC_CheckPredicate, 18, 164, 34, 0, // Skip to: 86948 -/* 78080 */ MCD_OPC_Decode, 246, 10, 193, 3, // Opcode: FMULHrr -/* 78085 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 78100 -/* 78090 */ MCD_OPC_CheckPredicate, 18, 149, 34, 0, // Skip to: 86948 -/* 78095 */ MCD_OPC_Decode, 167, 9, 193, 3, // Opcode: FDIVHrr -/* 78100 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 78115 -/* 78105 */ MCD_OPC_CheckPredicate, 18, 134, 34, 0, // Skip to: 86948 -/* 78110 */ MCD_OPC_Decode, 176, 6, 193, 3, // Opcode: FADDHrr -/* 78115 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 78130 -/* 78120 */ MCD_OPC_CheckPredicate, 18, 119, 34, 0, // Skip to: 86948 -/* 78125 */ MCD_OPC_Decode, 210, 12, 193, 3, // Opcode: FSUBHrr -/* 78130 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 78145 -/* 78135 */ MCD_OPC_CheckPredicate, 18, 104, 34, 0, // Skip to: 86948 -/* 78140 */ MCD_OPC_Decode, 194, 9, 193, 3, // Opcode: FMAXHrr -/* 78145 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 78160 -/* 78150 */ MCD_OPC_CheckPredicate, 18, 89, 34, 0, // Skip to: 86948 -/* 78155 */ MCD_OPC_Decode, 250, 9, 193, 3, // Opcode: FMINHrr -/* 78160 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 78175 -/* 78165 */ MCD_OPC_CheckPredicate, 18, 74, 34, 0, // Skip to: 86948 -/* 78170 */ MCD_OPC_Decode, 196, 9, 193, 3, // Opcode: FMAXNMHrr -/* 78175 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 78190 -/* 78180 */ MCD_OPC_CheckPredicate, 18, 59, 34, 0, // Skip to: 86948 -/* 78185 */ MCD_OPC_Decode, 252, 9, 193, 3, // Opcode: FMINNMHrr -/* 78190 */ MCD_OPC_FilterValue, 8, 49, 34, 0, // Skip to: 86948 -/* 78195 */ MCD_OPC_CheckPredicate, 18, 44, 34, 0, // Skip to: 86948 -/* 78200 */ MCD_OPC_Decode, 194, 11, 193, 3, // Opcode: FNMULHrr -/* 78205 */ MCD_OPC_FilterValue, 3, 34, 34, 0, // Skip to: 86948 -/* 78210 */ MCD_OPC_CheckPredicate, 18, 29, 34, 0, // Skip to: 86948 -/* 78215 */ MCD_OPC_Decode, 215, 7, 194, 3, // Opcode: FCSELHrrr -/* 78220 */ MCD_OPC_FilterValue, 3, 19, 34, 0, // Skip to: 86948 -/* 78225 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 78228 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 78266 -/* 78233 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 78236 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78251 -/* 78241 */ MCD_OPC_CheckPredicate, 16, 254, 33, 0, // Skip to: 86948 -/* 78246 */ MCD_OPC_Decode, 189, 9, 195, 3, // Opcode: FMADDSrrr -/* 78251 */ MCD_OPC_FilterValue, 1, 244, 33, 0, // Skip to: 86948 -/* 78256 */ MCD_OPC_CheckPredicate, 16, 239, 33, 0, // Skip to: 86948 -/* 78261 */ MCD_OPC_Decode, 244, 10, 195, 3, // Opcode: FMSUBSrrr -/* 78266 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 78304 -/* 78271 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 78274 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78289 -/* 78279 */ MCD_OPC_CheckPredicate, 16, 216, 33, 0, // Skip to: 86948 -/* 78284 */ MCD_OPC_Decode, 177, 11, 195, 3, // Opcode: FNMADDSrrr -/* 78289 */ MCD_OPC_FilterValue, 1, 206, 33, 0, // Skip to: 86948 -/* 78294 */ MCD_OPC_CheckPredicate, 16, 201, 33, 0, // Skip to: 86948 -/* 78299 */ MCD_OPC_Decode, 192, 11, 195, 3, // Opcode: FNMSUBSrrr -/* 78304 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 78342 -/* 78309 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 78312 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78327 -/* 78317 */ MCD_OPC_CheckPredicate, 16, 178, 33, 0, // Skip to: 86948 -/* 78322 */ MCD_OPC_Decode, 187, 9, 196, 3, // Opcode: FMADDDrrr -/* 78327 */ MCD_OPC_FilterValue, 1, 168, 33, 0, // Skip to: 86948 -/* 78332 */ MCD_OPC_CheckPredicate, 16, 163, 33, 0, // Skip to: 86948 -/* 78337 */ MCD_OPC_Decode, 242, 10, 196, 3, // Opcode: FMSUBDrrr -/* 78342 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 78380 -/* 78347 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 78350 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78365 -/* 78355 */ MCD_OPC_CheckPredicate, 16, 140, 33, 0, // Skip to: 86948 -/* 78360 */ MCD_OPC_Decode, 175, 11, 196, 3, // Opcode: FNMADDDrrr -/* 78365 */ MCD_OPC_FilterValue, 1, 130, 33, 0, // Skip to: 86948 -/* 78370 */ MCD_OPC_CheckPredicate, 16, 125, 33, 0, // Skip to: 86948 -/* 78375 */ MCD_OPC_Decode, 190, 11, 196, 3, // Opcode: FNMSUBDrrr -/* 78380 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 78418 -/* 78385 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 78388 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78403 -/* 78393 */ MCD_OPC_CheckPredicate, 18, 102, 33, 0, // Skip to: 86948 -/* 78398 */ MCD_OPC_Decode, 188, 9, 197, 3, // Opcode: FMADDHrrr -/* 78403 */ MCD_OPC_FilterValue, 1, 92, 33, 0, // Skip to: 86948 -/* 78408 */ MCD_OPC_CheckPredicate, 18, 87, 33, 0, // Skip to: 86948 -/* 78413 */ MCD_OPC_Decode, 243, 10, 197, 3, // Opcode: FMSUBHrrr -/* 78418 */ MCD_OPC_FilterValue, 7, 77, 33, 0, // Skip to: 86948 -/* 78423 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 78426 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78441 -/* 78431 */ MCD_OPC_CheckPredicate, 18, 64, 33, 0, // Skip to: 86948 -/* 78436 */ MCD_OPC_Decode, 176, 11, 197, 3, // Opcode: FNMADDHrrr -/* 78441 */ MCD_OPC_FilterValue, 1, 54, 33, 0, // Skip to: 86948 -/* 78446 */ MCD_OPC_CheckPredicate, 18, 49, 33, 0, // Skip to: 86948 -/* 78451 */ MCD_OPC_Decode, 191, 11, 197, 3, // Opcode: FNMSUBHrrr -/* 78456 */ MCD_OPC_FilterValue, 1, 191, 1, 0, // Skip to: 78908 -/* 78461 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 78464 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 78565 -/* 78469 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 78472 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78489 -/* 78477 */ MCD_OPC_CheckField, 21, 1, 0, 16, 33, 0, // Skip to: 86948 -/* 78484 */ MCD_OPC_Decode, 197, 29, 255, 2, // Opcode: STURBi -/* 78489 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78506 -/* 78494 */ MCD_OPC_CheckField, 21, 1, 0, 255, 32, 0, // Skip to: 86948 -/* 78501 */ MCD_OPC_Decode, 150, 29, 255, 2, // Opcode: STRBpost -/* 78506 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78548 -/* 78511 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 78514 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78531 -/* 78519 */ MCD_OPC_CheckField, 21, 1, 1, 230, 32, 0, // Skip to: 86948 -/* 78526 */ MCD_OPC_Decode, 152, 29, 198, 3, // Opcode: STRBroW -/* 78531 */ MCD_OPC_FilterValue, 3, 220, 32, 0, // Skip to: 86948 -/* 78536 */ MCD_OPC_CheckField, 21, 1, 1, 213, 32, 0, // Skip to: 86948 -/* 78543 */ MCD_OPC_Decode, 153, 29, 199, 3, // Opcode: STRBroX -/* 78548 */ MCD_OPC_FilterValue, 3, 203, 32, 0, // Skip to: 86948 -/* 78553 */ MCD_OPC_CheckField, 21, 1, 0, 196, 32, 0, // Skip to: 86948 -/* 78560 */ MCD_OPC_Decode, 151, 29, 255, 2, // Opcode: STRBpre -/* 78565 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 78666 -/* 78570 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 78573 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78590 -/* 78578 */ MCD_OPC_CheckField, 21, 1, 0, 171, 32, 0, // Skip to: 86948 -/* 78585 */ MCD_OPC_Decode, 131, 19, 255, 2, // Opcode: LDURBi -/* 78590 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78607 -/* 78595 */ MCD_OPC_CheckField, 21, 1, 0, 154, 32, 0, // Skip to: 86948 -/* 78602 */ MCD_OPC_Decode, 224, 17, 255, 2, // Opcode: LDRBpost -/* 78607 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78649 -/* 78612 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 78615 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78632 -/* 78620 */ MCD_OPC_CheckField, 21, 1, 1, 129, 32, 0, // Skip to: 86948 -/* 78627 */ MCD_OPC_Decode, 226, 17, 198, 3, // Opcode: LDRBroW -/* 78632 */ MCD_OPC_FilterValue, 3, 119, 32, 0, // Skip to: 86948 -/* 78637 */ MCD_OPC_CheckField, 21, 1, 1, 112, 32, 0, // Skip to: 86948 -/* 78644 */ MCD_OPC_Decode, 227, 17, 199, 3, // Opcode: LDRBroX -/* 78649 */ MCD_OPC_FilterValue, 3, 102, 32, 0, // Skip to: 86948 -/* 78654 */ MCD_OPC_CheckField, 21, 1, 0, 95, 32, 0, // Skip to: 86948 -/* 78661 */ MCD_OPC_Decode, 225, 17, 255, 2, // Opcode: LDRBpre -/* 78666 */ MCD_OPC_FilterValue, 2, 96, 0, 0, // Skip to: 78767 -/* 78671 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 78674 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78691 -/* 78679 */ MCD_OPC_CheckField, 21, 1, 0, 70, 32, 0, // Skip to: 86948 -/* 78686 */ MCD_OPC_Decode, 201, 29, 255, 2, // Opcode: STURQi -/* 78691 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78708 -/* 78696 */ MCD_OPC_CheckField, 21, 1, 0, 53, 32, 0, // Skip to: 86948 -/* 78703 */ MCD_OPC_Decode, 170, 29, 255, 2, // Opcode: STRQpost -/* 78708 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78750 -/* 78713 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 78716 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78733 -/* 78721 */ MCD_OPC_CheckField, 21, 1, 1, 28, 32, 0, // Skip to: 86948 -/* 78728 */ MCD_OPC_Decode, 172, 29, 200, 3, // Opcode: STRQroW -/* 78733 */ MCD_OPC_FilterValue, 3, 18, 32, 0, // Skip to: 86948 -/* 78738 */ MCD_OPC_CheckField, 21, 1, 1, 11, 32, 0, // Skip to: 86948 -/* 78745 */ MCD_OPC_Decode, 173, 29, 201, 3, // Opcode: STRQroX -/* 78750 */ MCD_OPC_FilterValue, 3, 1, 32, 0, // Skip to: 86948 -/* 78755 */ MCD_OPC_CheckField, 21, 1, 0, 250, 31, 0, // Skip to: 86948 -/* 78762 */ MCD_OPC_Decode, 171, 29, 255, 2, // Opcode: STRQpre -/* 78767 */ MCD_OPC_FilterValue, 3, 96, 0, 0, // Skip to: 78868 -/* 78772 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 78775 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78792 -/* 78780 */ MCD_OPC_CheckField, 21, 1, 0, 225, 31, 0, // Skip to: 86948 -/* 78787 */ MCD_OPC_Decode, 135, 19, 255, 2, // Opcode: LDURQi -/* 78792 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78809 -/* 78797 */ MCD_OPC_CheckField, 21, 1, 0, 208, 31, 0, // Skip to: 86948 -/* 78804 */ MCD_OPC_Decode, 246, 17, 255, 2, // Opcode: LDRQpost -/* 78809 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78851 -/* 78814 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 78817 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78834 -/* 78822 */ MCD_OPC_CheckField, 21, 1, 1, 183, 31, 0, // Skip to: 86948 -/* 78829 */ MCD_OPC_Decode, 248, 17, 200, 3, // Opcode: LDRQroW -/* 78834 */ MCD_OPC_FilterValue, 3, 173, 31, 0, // Skip to: 86948 -/* 78839 */ MCD_OPC_CheckField, 21, 1, 1, 166, 31, 0, // Skip to: 86948 -/* 78846 */ MCD_OPC_Decode, 249, 17, 201, 3, // Opcode: LDRQroX -/* 78851 */ MCD_OPC_FilterValue, 3, 156, 31, 0, // Skip to: 86948 -/* 78856 */ MCD_OPC_CheckField, 21, 1, 0, 149, 31, 0, // Skip to: 86948 -/* 78863 */ MCD_OPC_Decode, 247, 17, 255, 2, // Opcode: LDRQpre -/* 78868 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 78878 -/* 78873 */ MCD_OPC_Decode, 154, 29, 137, 3, // Opcode: STRBui -/* 78878 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 78888 -/* 78883 */ MCD_OPC_Decode, 228, 17, 137, 3, // Opcode: LDRBui -/* 78888 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 78898 -/* 78893 */ MCD_OPC_Decode, 174, 29, 137, 3, // Opcode: STRQui -/* 78898 */ MCD_OPC_FilterValue, 7, 109, 31, 0, // Skip to: 86948 -/* 78903 */ MCD_OPC_Decode, 250, 17, 137, 3, // Opcode: LDRQui -/* 78908 */ MCD_OPC_FilterValue, 2, 63, 12, 0, // Skip to: 82048 -/* 78913 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 78916 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 78926 -/* 78921 */ MCD_OPC_Decode, 229, 17, 202, 3, // Opcode: LDRDl -/* 78926 */ MCD_OPC_FilterValue, 2, 254, 7, 0, // Skip to: 80977 -/* 78931 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 78934 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 78956 -/* 78939 */ MCD_OPC_CheckPredicate, 19, 68, 31, 0, // Skip to: 86948 -/* 78944 */ MCD_OPC_CheckField, 21, 3, 0, 61, 31, 0, // Skip to: 86948 -/* 78951 */ MCD_OPC_Decode, 241, 22, 203, 3, // Opcode: SHA1Crrr -/* 78956 */ MCD_OPC_FilterValue, 1, 114, 0, 0, // Skip to: 79075 -/* 78961 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 78964 */ MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 79053 -/* 78969 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 78972 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 79031 -/* 78977 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 78980 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 79009 -/* 78985 */ MCD_OPC_CheckPredicate, 3, 22, 31, 0, // Skip to: 86948 -/* 78990 */ MCD_OPC_CheckField, 21, 3, 0, 15, 31, 0, // Skip to: 86948 -/* 78997 */ MCD_OPC_CheckField, 19, 1, 1, 8, 31, 0, // Skip to: 86948 -/* 79004 */ MCD_OPC_Decode, 151, 5, 204, 3, // Opcode: CPYi64 -/* 79009 */ MCD_OPC_FilterValue, 1, 254, 30, 0, // Skip to: 86948 -/* 79014 */ MCD_OPC_CheckPredicate, 3, 249, 30, 0, // Skip to: 86948 -/* 79019 */ MCD_OPC_CheckField, 21, 3, 0, 242, 30, 0, // Skip to: 86948 -/* 79026 */ MCD_OPC_Decode, 150, 5, 205, 3, // Opcode: CPYi32 -/* 79031 */ MCD_OPC_FilterValue, 1, 232, 30, 0, // Skip to: 86948 -/* 79036 */ MCD_OPC_CheckPredicate, 3, 227, 30, 0, // Skip to: 86948 -/* 79041 */ MCD_OPC_CheckField, 21, 3, 0, 220, 30, 0, // Skip to: 86948 -/* 79048 */ MCD_OPC_Decode, 149, 5, 206, 3, // Opcode: CPYi16 -/* 79053 */ MCD_OPC_FilterValue, 1, 210, 30, 0, // Skip to: 86948 -/* 79058 */ MCD_OPC_CheckPredicate, 3, 205, 30, 0, // Skip to: 86948 -/* 79063 */ MCD_OPC_CheckField, 21, 3, 0, 198, 30, 0, // Skip to: 86948 -/* 79070 */ MCD_OPC_Decode, 152, 5, 207, 3, // Opcode: CPYi8 -/* 79075 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 79097 -/* 79080 */ MCD_OPC_CheckPredicate, 19, 183, 30, 0, // Skip to: 86948 -/* 79085 */ MCD_OPC_CheckField, 16, 8, 40, 176, 30, 0, // Skip to: 86948 -/* 79092 */ MCD_OPC_Decode, 242, 22, 167, 3, // Opcode: SHA1Hrr -/* 79097 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 79165 -/* 79102 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 79105 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79120 -/* 79110 */ MCD_OPC_CheckPredicate, 3, 153, 30, 0, // Skip to: 86948 -/* 79115 */ MCD_OPC_Decode, 176, 24, 208, 3, // Opcode: SQADDv1i8 -/* 79120 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79135 -/* 79125 */ MCD_OPC_CheckPredicate, 3, 138, 30, 0, // Skip to: 86948 -/* 79130 */ MCD_OPC_Decode, 173, 24, 193, 3, // Opcode: SQADDv1i16 -/* 79135 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79150 -/* 79140 */ MCD_OPC_CheckPredicate, 3, 123, 30, 0, // Skip to: 86948 -/* 79145 */ MCD_OPC_Decode, 174, 24, 172, 3, // Opcode: SQADDv1i32 -/* 79150 */ MCD_OPC_FilterValue, 7, 113, 30, 0, // Skip to: 86948 -/* 79155 */ MCD_OPC_CheckPredicate, 3, 108, 30, 0, // Skip to: 86948 -/* 79160 */ MCD_OPC_Decode, 175, 24, 238, 1, // Opcode: SQADDv1i64 -/* 79165 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 79187 -/* 79170 */ MCD_OPC_CheckPredicate, 19, 93, 30, 0, // Skip to: 86948 -/* 79175 */ MCD_OPC_CheckField, 21, 3, 0, 86, 30, 0, // Skip to: 86948 -/* 79182 */ MCD_OPC_Decode, 244, 22, 203, 3, // Opcode: SHA1Prrr -/* 79187 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 79209 -/* 79192 */ MCD_OPC_CheckPredicate, 19, 71, 30, 0, // Skip to: 86948 -/* 79197 */ MCD_OPC_CheckField, 16, 8, 40, 64, 30, 0, // Skip to: 86948 -/* 79204 */ MCD_OPC_Decode, 246, 22, 147, 2, // Opcode: SHA1SU1rr -/* 79209 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 79231 -/* 79214 */ MCD_OPC_CheckPredicate, 4, 49, 30, 0, // Skip to: 86948 -/* 79219 */ MCD_OPC_CheckField, 21, 3, 2, 42, 30, 0, // Skip to: 86948 -/* 79226 */ MCD_OPC_Decode, 248, 10, 193, 3, // Opcode: FMULX16 -/* 79231 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 79253 -/* 79236 */ MCD_OPC_CheckPredicate, 19, 27, 30, 0, // Skip to: 86948 -/* 79241 */ MCD_OPC_CheckField, 21, 3, 0, 20, 30, 0, // Skip to: 86948 -/* 79248 */ MCD_OPC_Decode, 243, 22, 203, 3, // Opcode: SHA1Mrrr -/* 79253 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 79275 -/* 79258 */ MCD_OPC_CheckPredicate, 4, 5, 30, 0, // Skip to: 86948 -/* 79263 */ MCD_OPC_CheckField, 21, 3, 2, 254, 29, 0, // Skip to: 86948 -/* 79270 */ MCD_OPC_Decode, 217, 6, 193, 3, // Opcode: FCMEQ16 -/* 79275 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 79297 -/* 79280 */ MCD_OPC_CheckPredicate, 19, 239, 29, 0, // Skip to: 86948 -/* 79285 */ MCD_OPC_CheckField, 16, 8, 40, 232, 29, 0, // Skip to: 86948 -/* 79292 */ MCD_OPC_Decode, 249, 22, 147, 2, // Opcode: SHA256SU0rr -/* 79297 */ MCD_OPC_FilterValue, 11, 63, 0, 0, // Skip to: 79365 -/* 79302 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 79305 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79320 -/* 79310 */ MCD_OPC_CheckPredicate, 3, 209, 29, 0, // Skip to: 86948 -/* 79315 */ MCD_OPC_Decode, 158, 26, 208, 3, // Opcode: SQSUBv1i8 -/* 79320 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79335 -/* 79325 */ MCD_OPC_CheckPredicate, 3, 194, 29, 0, // Skip to: 86948 -/* 79330 */ MCD_OPC_Decode, 155, 26, 193, 3, // Opcode: SQSUBv1i16 -/* 79335 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79350 -/* 79340 */ MCD_OPC_CheckPredicate, 3, 179, 29, 0, // Skip to: 86948 -/* 79345 */ MCD_OPC_Decode, 156, 26, 172, 3, // Opcode: SQSUBv1i32 -/* 79350 */ MCD_OPC_FilterValue, 7, 169, 29, 0, // Skip to: 86948 -/* 79355 */ MCD_OPC_CheckPredicate, 3, 164, 29, 0, // Skip to: 86948 -/* 79360 */ MCD_OPC_Decode, 157, 26, 238, 1, // Opcode: SQSUBv1i64 -/* 79365 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 79387 -/* 79370 */ MCD_OPC_CheckPredicate, 19, 149, 29, 0, // Skip to: 86948 -/* 79375 */ MCD_OPC_CheckField, 21, 3, 0, 142, 29, 0, // Skip to: 86948 -/* 79382 */ MCD_OPC_Decode, 245, 22, 141, 2, // Opcode: SHA1SU0rrr -/* 79387 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 79409 -/* 79392 */ MCD_OPC_CheckPredicate, 3, 127, 29, 0, // Skip to: 86948 -/* 79397 */ MCD_OPC_CheckField, 21, 3, 7, 120, 29, 0, // Skip to: 86948 -/* 79404 */ MCD_OPC_Decode, 216, 3, 238, 1, // Opcode: CMGTv1i64 -/* 79409 */ MCD_OPC_FilterValue, 14, 65, 0, 0, // Skip to: 79479 -/* 79414 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 79417 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 79432 -/* 79422 */ MCD_OPC_CheckPredicate, 3, 97, 29, 0, // Skip to: 86948 -/* 79427 */ MCD_OPC_Decode, 145, 30, 209, 3, // Opcode: SUQADDv1i8 -/* 79432 */ MCD_OPC_FilterValue, 96, 10, 0, 0, // Skip to: 79447 -/* 79437 */ MCD_OPC_CheckPredicate, 3, 82, 29, 0, // Skip to: 86948 -/* 79442 */ MCD_OPC_Decode, 142, 30, 210, 3, // Opcode: SUQADDv1i16 -/* 79447 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 79463 -/* 79453 */ MCD_OPC_CheckPredicate, 3, 66, 29, 0, // Skip to: 86948 -/* 79458 */ MCD_OPC_Decode, 143, 30, 211, 3, // Opcode: SUQADDv1i32 -/* 79463 */ MCD_OPC_FilterValue, 224, 1, 55, 29, 0, // Skip to: 86948 -/* 79469 */ MCD_OPC_CheckPredicate, 3, 50, 29, 0, // Skip to: 86948 -/* 79474 */ MCD_OPC_Decode, 144, 30, 248, 1, // Opcode: SUQADDv1i64 -/* 79479 */ MCD_OPC_FilterValue, 15, 48, 0, 0, // Skip to: 79532 -/* 79484 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 79487 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 79502 -/* 79492 */ MCD_OPC_CheckPredicate, 4, 27, 29, 0, // Skip to: 86948 -/* 79497 */ MCD_OPC_Decode, 207, 11, 193, 3, // Opcode: FRECPS16 -/* 79502 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 79517 -/* 79507 */ MCD_OPC_CheckPredicate, 4, 12, 29, 0, // Skip to: 86948 -/* 79512 */ MCD_OPC_Decode, 184, 12, 193, 3, // Opcode: FRSQRTS16 -/* 79517 */ MCD_OPC_FilterValue, 7, 2, 29, 0, // Skip to: 86948 -/* 79522 */ MCD_OPC_CheckPredicate, 3, 253, 28, 0, // Skip to: 86948 -/* 79527 */ MCD_OPC_Decode, 200, 3, 238, 1, // Opcode: CMGEv1i64 -/* 79532 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 79554 -/* 79537 */ MCD_OPC_CheckPredicate, 19, 238, 28, 0, // Skip to: 86948 -/* 79542 */ MCD_OPC_CheckField, 21, 3, 0, 231, 28, 0, // Skip to: 86948 -/* 79549 */ MCD_OPC_Decode, 248, 22, 141, 2, // Opcode: SHA256Hrrr -/* 79554 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 79576 -/* 79559 */ MCD_OPC_CheckPredicate, 3, 216, 28, 0, // Skip to: 86948 -/* 79564 */ MCD_OPC_CheckField, 21, 3, 7, 209, 28, 0, // Skip to: 86948 -/* 79571 */ MCD_OPC_Decode, 228, 26, 238, 1, // Opcode: SSHLv1i64 -/* 79576 */ MCD_OPC_FilterValue, 18, 49, 0, 0, // Skip to: 79630 -/* 79581 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 79584 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 79599 -/* 79589 */ MCD_OPC_CheckPredicate, 3, 186, 28, 0, // Skip to: 86948 -/* 79594 */ MCD_OPC_Decode, 168, 26, 212, 3, // Opcode: SQXTNv1i8 -/* 79599 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 79614 -/* 79604 */ MCD_OPC_CheckPredicate, 3, 171, 28, 0, // Skip to: 86948 -/* 79609 */ MCD_OPC_Decode, 166, 26, 169, 3, // Opcode: SQXTNv1i16 -/* 79614 */ MCD_OPC_FilterValue, 161, 1, 160, 28, 0, // Skip to: 86948 -/* 79620 */ MCD_OPC_CheckPredicate, 3, 155, 28, 0, // Skip to: 86948 -/* 79625 */ MCD_OPC_Decode, 167, 26, 166, 2, // Opcode: SQXTNv1i32 -/* 79630 */ MCD_OPC_FilterValue, 19, 63, 0, 0, // Skip to: 79698 -/* 79635 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 79638 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79653 -/* 79643 */ MCD_OPC_CheckPredicate, 3, 132, 28, 0, // Skip to: 86948 -/* 79648 */ MCD_OPC_Decode, 243, 25, 208, 3, // Opcode: SQSHLv1i8 -/* 79653 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79668 -/* 79658 */ MCD_OPC_CheckPredicate, 3, 117, 28, 0, // Skip to: 86948 -/* 79663 */ MCD_OPC_Decode, 240, 25, 193, 3, // Opcode: SQSHLv1i16 -/* 79668 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79683 -/* 79673 */ MCD_OPC_CheckPredicate, 3, 102, 28, 0, // Skip to: 86948 -/* 79678 */ MCD_OPC_Decode, 241, 25, 172, 3, // Opcode: SQSHLv1i32 -/* 79683 */ MCD_OPC_FilterValue, 7, 92, 28, 0, // Skip to: 86948 -/* 79688 */ MCD_OPC_CheckPredicate, 3, 87, 28, 0, // Skip to: 86948 -/* 79693 */ MCD_OPC_Decode, 242, 25, 238, 1, // Opcode: SQSHLv1i64 -/* 79698 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 79720 -/* 79703 */ MCD_OPC_CheckPredicate, 19, 72, 28, 0, // Skip to: 86948 -/* 79708 */ MCD_OPC_CheckField, 21, 3, 0, 65, 28, 0, // Skip to: 86948 -/* 79715 */ MCD_OPC_Decode, 247, 22, 141, 2, // Opcode: SHA256H2rrr -/* 79720 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 79742 -/* 79725 */ MCD_OPC_CheckPredicate, 3, 50, 28, 0, // Skip to: 86948 -/* 79730 */ MCD_OPC_CheckField, 21, 3, 7, 43, 28, 0, // Skip to: 86948 -/* 79737 */ MCD_OPC_Decode, 198, 26, 238, 1, // Opcode: SRSHLv1i64 -/* 79742 */ MCD_OPC_FilterValue, 23, 63, 0, 0, // Skip to: 79810 -/* 79747 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 79750 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79765 -/* 79755 */ MCD_OPC_CheckPredicate, 3, 20, 28, 0, // Skip to: 86948 -/* 79760 */ MCD_OPC_Decode, 198, 25, 208, 3, // Opcode: SQRSHLv1i8 -/* 79765 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79780 -/* 79770 */ MCD_OPC_CheckPredicate, 3, 5, 28, 0, // Skip to: 86948 -/* 79775 */ MCD_OPC_Decode, 195, 25, 193, 3, // Opcode: SQRSHLv1i16 -/* 79780 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79795 -/* 79785 */ MCD_OPC_CheckPredicate, 3, 246, 27, 0, // Skip to: 86948 -/* 79790 */ MCD_OPC_Decode, 196, 25, 172, 3, // Opcode: SQRSHLv1i32 -/* 79795 */ MCD_OPC_FilterValue, 7, 236, 27, 0, // Skip to: 86948 -/* 79800 */ MCD_OPC_CheckPredicate, 3, 231, 27, 0, // Skip to: 86948 -/* 79805 */ MCD_OPC_Decode, 197, 25, 238, 1, // Opcode: SQRSHLv1i64 -/* 79810 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 79832 -/* 79815 */ MCD_OPC_CheckPredicate, 19, 216, 27, 0, // Skip to: 86948 -/* 79820 */ MCD_OPC_CheckField, 21, 3, 0, 209, 27, 0, // Skip to: 86948 -/* 79827 */ MCD_OPC_Decode, 250, 22, 141, 2, // Opcode: SHA256SU1rrr -/* 79832 */ MCD_OPC_FilterValue, 30, 65, 0, 0, // Skip to: 79902 -/* 79837 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 79840 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 79855 -/* 79845 */ MCD_OPC_CheckPredicate, 3, 186, 27, 0, // Skip to: 86948 -/* 79850 */ MCD_OPC_Decode, 157, 24, 213, 3, // Opcode: SQABSv1i8 -/* 79855 */ MCD_OPC_FilterValue, 96, 10, 0, 0, // Skip to: 79870 -/* 79860 */ MCD_OPC_CheckPredicate, 3, 171, 27, 0, // Skip to: 86948 -/* 79865 */ MCD_OPC_Decode, 154, 24, 188, 3, // Opcode: SQABSv1i16 -/* 79870 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 79886 -/* 79876 */ MCD_OPC_CheckPredicate, 3, 155, 27, 0, // Skip to: 86948 -/* 79881 */ MCD_OPC_Decode, 155, 24, 167, 3, // Opcode: SQABSv1i32 -/* 79886 */ MCD_OPC_FilterValue, 224, 1, 144, 27, 0, // Skip to: 86948 -/* 79892 */ MCD_OPC_CheckPredicate, 3, 139, 27, 0, // Skip to: 86948 -/* 79897 */ MCD_OPC_Decode, 156, 24, 239, 1, // Opcode: SQABSv1i64 -/* 79902 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 79924 -/* 79907 */ MCD_OPC_CheckPredicate, 3, 124, 27, 0, // Skip to: 86948 -/* 79912 */ MCD_OPC_CheckField, 21, 3, 7, 117, 27, 0, // Skip to: 86948 -/* 79919 */ MCD_OPC_Decode, 195, 1, 238, 1, // Opcode: ADDv1i64 -/* 79924 */ MCD_OPC_FilterValue, 34, 18, 0, 0, // Skip to: 79947 -/* 79929 */ MCD_OPC_CheckPredicate, 3, 102, 27, 0, // Skip to: 86948 -/* 79934 */ MCD_OPC_CheckField, 16, 8, 224, 1, 94, 27, 0, // Skip to: 86948 -/* 79942 */ MCD_OPC_Decode, 217, 3, 239, 1, // Opcode: CMGTv1i64rz -/* 79947 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 79969 -/* 79952 */ MCD_OPC_CheckPredicate, 3, 79, 27, 0, // Skip to: 86948 -/* 79957 */ MCD_OPC_CheckField, 21, 3, 7, 72, 27, 0, // Skip to: 86948 -/* 79964 */ MCD_OPC_Decode, 234, 4, 238, 1, // Opcode: CMTSTv1i64 -/* 79969 */ MCD_OPC_FilterValue, 36, 33, 0, 0, // Skip to: 80007 -/* 79974 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 79977 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79992 -/* 79982 */ MCD_OPC_CheckPredicate, 3, 49, 27, 0, // Skip to: 86948 -/* 79987 */ MCD_OPC_Decode, 205, 24, 214, 3, // Opcode: SQDMLALi16 -/* 79992 */ MCD_OPC_FilterValue, 5, 39, 27, 0, // Skip to: 86948 -/* 79997 */ MCD_OPC_CheckPredicate, 3, 34, 27, 0, // Skip to: 86948 -/* 80002 */ MCD_OPC_Decode, 206, 24, 215, 3, // Opcode: SQDMLALi32 -/* 80007 */ MCD_OPC_FilterValue, 38, 18, 0, 0, // Skip to: 80030 -/* 80012 */ MCD_OPC_CheckPredicate, 3, 19, 27, 0, // Skip to: 86948 -/* 80017 */ MCD_OPC_CheckField, 16, 8, 224, 1, 11, 27, 0, // Skip to: 86948 -/* 80025 */ MCD_OPC_Decode, 185, 3, 239, 1, // Opcode: CMEQv1i64rz -/* 80030 */ MCD_OPC_FilterValue, 42, 112, 0, 0, // Skip to: 80147 -/* 80035 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 80038 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80053 -/* 80043 */ MCD_OPC_CheckPredicate, 3, 244, 26, 0, // Skip to: 86948 -/* 80048 */ MCD_OPC_Decode, 160, 8, 167, 3, // Opcode: FCVTNSv1i32 -/* 80053 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80068 -/* 80058 */ MCD_OPC_CheckPredicate, 3, 229, 26, 0, // Skip to: 86948 -/* 80063 */ MCD_OPC_Decode, 161, 8, 239, 1, // Opcode: FCVTNSv1i64 -/* 80068 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80083 -/* 80073 */ MCD_OPC_CheckPredicate, 4, 214, 26, 0, // Skip to: 86948 -/* 80078 */ MCD_OPC_Decode, 159, 8, 188, 3, // Opcode: FCVTNSv1f16 -/* 80083 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80099 -/* 80089 */ MCD_OPC_CheckPredicate, 3, 198, 26, 0, // Skip to: 86948 -/* 80094 */ MCD_OPC_Decode, 192, 8, 167, 3, // Opcode: FCVTPSv1i32 -/* 80099 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80115 -/* 80105 */ MCD_OPC_CheckPredicate, 3, 182, 26, 0, // Skip to: 86948 -/* 80110 */ MCD_OPC_Decode, 255, 3, 239, 1, // Opcode: CMLTv1i64rz -/* 80115 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80131 -/* 80121 */ MCD_OPC_CheckPredicate, 3, 166, 26, 0, // Skip to: 86948 -/* 80126 */ MCD_OPC_Decode, 193, 8, 239, 1, // Opcode: FCVTPSv1i64 -/* 80131 */ MCD_OPC_FilterValue, 249, 1, 155, 26, 0, // Skip to: 86948 -/* 80137 */ MCD_OPC_CheckPredicate, 4, 150, 26, 0, // Skip to: 86948 -/* 80142 */ MCD_OPC_Decode, 191, 8, 188, 3, // Opcode: FCVTPSv1f16 -/* 80147 */ MCD_OPC_FilterValue, 44, 33, 0, 0, // Skip to: 80185 -/* 80152 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 80155 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80170 -/* 80160 */ MCD_OPC_CheckPredicate, 3, 127, 26, 0, // Skip to: 86948 -/* 80165 */ MCD_OPC_Decode, 217, 24, 214, 3, // Opcode: SQDMLSLi16 -/* 80170 */ MCD_OPC_FilterValue, 5, 117, 26, 0, // Skip to: 86948 -/* 80175 */ MCD_OPC_CheckPredicate, 3, 112, 26, 0, // Skip to: 86948 -/* 80180 */ MCD_OPC_Decode, 218, 24, 215, 3, // Opcode: SQDMLSLi32 -/* 80185 */ MCD_OPC_FilterValue, 45, 33, 0, 0, // Skip to: 80223 -/* 80190 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 80193 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80208 -/* 80198 */ MCD_OPC_CheckPredicate, 3, 89, 26, 0, // Skip to: 86948 -/* 80203 */ MCD_OPC_Decode, 229, 24, 193, 3, // Opcode: SQDMULHv1i16 -/* 80208 */ MCD_OPC_FilterValue, 5, 79, 26, 0, // Skip to: 86948 -/* 80213 */ MCD_OPC_CheckPredicate, 3, 74, 26, 0, // Skip to: 86948 -/* 80218 */ MCD_OPC_Decode, 231, 24, 172, 3, // Opcode: SQDMULHv1i32 -/* 80223 */ MCD_OPC_FilterValue, 46, 128, 0, 0, // Skip to: 80356 -/* 80228 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 80231 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80246 -/* 80236 */ MCD_OPC_CheckPredicate, 3, 51, 26, 0, // Skip to: 86948 -/* 80241 */ MCD_OPC_Decode, 132, 8, 167, 3, // Opcode: FCVTMSv1i32 -/* 80246 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80261 -/* 80251 */ MCD_OPC_CheckPredicate, 3, 36, 26, 0, // Skip to: 86948 -/* 80256 */ MCD_OPC_Decode, 133, 8, 239, 1, // Opcode: FCVTMSv1i64 -/* 80261 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80276 -/* 80266 */ MCD_OPC_CheckPredicate, 4, 21, 26, 0, // Skip to: 86948 -/* 80271 */ MCD_OPC_Decode, 131, 8, 188, 3, // Opcode: FCVTMSv1f16 -/* 80276 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80292 -/* 80282 */ MCD_OPC_CheckPredicate, 3, 5, 26, 0, // Skip to: 86948 -/* 80287 */ MCD_OPC_Decode, 241, 8, 167, 3, // Opcode: FCVTZSv1i32 -/* 80292 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80308 -/* 80298 */ MCD_OPC_CheckPredicate, 3, 245, 25, 0, // Skip to: 86948 -/* 80303 */ MCD_OPC_Decode, 131, 1, 239, 1, // Opcode: ABSv1i64 -/* 80308 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80324 -/* 80314 */ MCD_OPC_CheckPredicate, 3, 229, 25, 0, // Skip to: 86948 -/* 80319 */ MCD_OPC_Decode, 242, 8, 239, 1, // Opcode: FCVTZSv1i64 -/* 80324 */ MCD_OPC_FilterValue, 241, 1, 10, 0, 0, // Skip to: 80340 -/* 80330 */ MCD_OPC_CheckPredicate, 3, 213, 25, 0, // Skip to: 86948 -/* 80335 */ MCD_OPC_Decode, 152, 1, 244, 1, // Opcode: ADDPv2i64p -/* 80340 */ MCD_OPC_FilterValue, 249, 1, 202, 25, 0, // Skip to: 86948 -/* 80346 */ MCD_OPC_CheckPredicate, 4, 197, 25, 0, // Skip to: 86948 -/* 80351 */ MCD_OPC_Decode, 240, 8, 188, 3, // Opcode: FCVTZSv1f16 -/* 80356 */ MCD_OPC_FilterValue, 50, 127, 0, 0, // Skip to: 80488 -/* 80361 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 80364 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80379 -/* 80369 */ MCD_OPC_CheckPredicate, 3, 174, 25, 0, // Skip to: 86948 -/* 80374 */ MCD_OPC_Decode, 224, 7, 167, 3, // Opcode: FCVTASv1i32 -/* 80379 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 80394 -/* 80384 */ MCD_OPC_CheckPredicate, 4, 159, 25, 0, // Skip to: 86948 -/* 80389 */ MCD_OPC_Decode, 199, 9, 249, 1, // Opcode: FMAXNMPv2i16p -/* 80394 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80409 -/* 80399 */ MCD_OPC_CheckPredicate, 3, 144, 25, 0, // Skip to: 86948 -/* 80404 */ MCD_OPC_Decode, 225, 7, 239, 1, // Opcode: FCVTASv1i64 -/* 80409 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80424 -/* 80414 */ MCD_OPC_CheckPredicate, 4, 129, 25, 0, // Skip to: 86948 -/* 80419 */ MCD_OPC_Decode, 223, 7, 188, 3, // Opcode: FCVTASv1f16 -/* 80424 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 80440 -/* 80430 */ MCD_OPC_CheckPredicate, 3, 113, 25, 0, // Skip to: 86948 -/* 80435 */ MCD_OPC_Decode, 143, 7, 167, 3, // Opcode: FCMGTv1i32rz -/* 80440 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 80456 -/* 80446 */ MCD_OPC_CheckPredicate, 4, 97, 25, 0, // Skip to: 86948 -/* 80451 */ MCD_OPC_Decode, 255, 9, 249, 1, // Opcode: FMINNMPv2i16p -/* 80456 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80472 -/* 80462 */ MCD_OPC_CheckPredicate, 3, 81, 25, 0, // Skip to: 86948 -/* 80467 */ MCD_OPC_Decode, 144, 7, 239, 1, // Opcode: FCMGTv1i64rz -/* 80472 */ MCD_OPC_FilterValue, 248, 1, 70, 25, 0, // Skip to: 86948 -/* 80478 */ MCD_OPC_CheckPredicate, 4, 65, 25, 0, // Skip to: 86948 -/* 80483 */ MCD_OPC_Decode, 142, 7, 188, 3, // Opcode: FCMGTv1i16rz -/* 80488 */ MCD_OPC_FilterValue, 52, 33, 0, 0, // Skip to: 80526 -/* 80493 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 80496 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80511 -/* 80501 */ MCD_OPC_CheckPredicate, 3, 42, 25, 0, // Skip to: 86948 -/* 80506 */ MCD_OPC_Decode, 241, 24, 216, 3, // Opcode: SQDMULLi16 -/* 80511 */ MCD_OPC_FilterValue, 5, 32, 25, 0, // Skip to: 86948 -/* 80516 */ MCD_OPC_CheckPredicate, 3, 27, 25, 0, // Skip to: 86948 -/* 80521 */ MCD_OPC_Decode, 242, 24, 217, 3, // Opcode: SQDMULLi32 -/* 80526 */ MCD_OPC_FilterValue, 54, 159, 0, 0, // Skip to: 80690 -/* 80531 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 80534 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80549 -/* 80539 */ MCD_OPC_CheckPredicate, 3, 4, 25, 0, // Skip to: 86948 -/* 80544 */ MCD_OPC_Decode, 207, 22, 167, 3, // Opcode: SCVTFv1i32 -/* 80549 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 80564 -/* 80554 */ MCD_OPC_CheckPredicate, 4, 245, 24, 0, // Skip to: 86948 -/* 80559 */ MCD_OPC_Decode, 179, 6, 249, 1, // Opcode: FADDPv2i16p -/* 80564 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80579 -/* 80569 */ MCD_OPC_CheckPredicate, 3, 230, 24, 0, // Skip to: 86948 -/* 80574 */ MCD_OPC_Decode, 208, 22, 239, 1, // Opcode: SCVTFv1i64 -/* 80579 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80594 -/* 80584 */ MCD_OPC_CheckPredicate, 4, 215, 24, 0, // Skip to: 86948 -/* 80589 */ MCD_OPC_Decode, 206, 22, 188, 3, // Opcode: SCVTFv1i16 -/* 80594 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 80610 -/* 80600 */ MCD_OPC_CheckPredicate, 3, 199, 24, 0, // Skip to: 86948 -/* 80605 */ MCD_OPC_Decode, 227, 6, 167, 3, // Opcode: FCMEQv1i32rz -/* 80610 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80626 -/* 80616 */ MCD_OPC_CheckPredicate, 3, 183, 24, 0, // Skip to: 86948 -/* 80621 */ MCD_OPC_Decode, 200, 11, 167, 3, // Opcode: FRECPEv1i32 -/* 80626 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80642 -/* 80632 */ MCD_OPC_CheckPredicate, 3, 167, 24, 0, // Skip to: 86948 -/* 80637 */ MCD_OPC_Decode, 228, 6, 239, 1, // Opcode: FCMEQv1i64rz -/* 80642 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80658 -/* 80648 */ MCD_OPC_CheckPredicate, 3, 151, 24, 0, // Skip to: 86948 -/* 80653 */ MCD_OPC_Decode, 201, 11, 239, 1, // Opcode: FRECPEv1i64 -/* 80658 */ MCD_OPC_FilterValue, 248, 1, 10, 0, 0, // Skip to: 80674 -/* 80664 */ MCD_OPC_CheckPredicate, 4, 135, 24, 0, // Skip to: 86948 -/* 80669 */ MCD_OPC_Decode, 226, 6, 188, 3, // Opcode: FCMEQv1i16rz -/* 80674 */ MCD_OPC_FilterValue, 249, 1, 124, 24, 0, // Skip to: 86948 -/* 80680 */ MCD_OPC_CheckPredicate, 4, 119, 24, 0, // Skip to: 86948 -/* 80685 */ MCD_OPC_Decode, 199, 11, 188, 3, // Opcode: FRECPEv1f16 -/* 80690 */ MCD_OPC_FilterValue, 55, 33, 0, 0, // Skip to: 80728 -/* 80695 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 80698 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 80713 -/* 80703 */ MCD_OPC_CheckPredicate, 3, 96, 24, 0, // Skip to: 86948 -/* 80708 */ MCD_OPC_Decode, 249, 10, 172, 3, // Opcode: FMULX32 -/* 80713 */ MCD_OPC_FilterValue, 3, 86, 24, 0, // Skip to: 86948 -/* 80718 */ MCD_OPC_CheckPredicate, 3, 81, 24, 0, // Skip to: 86948 -/* 80723 */ MCD_OPC_Decode, 250, 10, 238, 1, // Opcode: FMULX64 -/* 80728 */ MCD_OPC_FilterValue, 57, 33, 0, 0, // Skip to: 80766 -/* 80733 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 80736 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 80751 -/* 80741 */ MCD_OPC_CheckPredicate, 3, 58, 24, 0, // Skip to: 86948 -/* 80746 */ MCD_OPC_Decode, 218, 6, 172, 3, // Opcode: FCMEQ32 -/* 80751 */ MCD_OPC_FilterValue, 3, 48, 24, 0, // Skip to: 86948 -/* 80756 */ MCD_OPC_CheckPredicate, 3, 43, 24, 0, // Skip to: 86948 -/* 80761 */ MCD_OPC_Decode, 219, 6, 238, 1, // Opcode: FCMEQ64 -/* 80766 */ MCD_OPC_FilterValue, 58, 51, 0, 0, // Skip to: 80822 -/* 80771 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 80774 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 80790 -/* 80780 */ MCD_OPC_CheckPredicate, 3, 19, 24, 0, // Skip to: 86948 -/* 80785 */ MCD_OPC_Decode, 183, 7, 167, 3, // Opcode: FCMLTv1i32rz -/* 80790 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80806 -/* 80796 */ MCD_OPC_CheckPredicate, 3, 3, 24, 0, // Skip to: 86948 -/* 80801 */ MCD_OPC_Decode, 184, 7, 239, 1, // Opcode: FCMLTv1i64rz -/* 80806 */ MCD_OPC_FilterValue, 248, 1, 248, 23, 0, // Skip to: 86948 -/* 80812 */ MCD_OPC_CheckPredicate, 4, 243, 23, 0, // Skip to: 86948 -/* 80817 */ MCD_OPC_Decode, 182, 7, 188, 3, // Opcode: FCMLTv1i16rz -/* 80822 */ MCD_OPC_FilterValue, 62, 82, 0, 0, // Skip to: 80909 -/* 80827 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 80830 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 80845 -/* 80835 */ MCD_OPC_CheckPredicate, 4, 220, 23, 0, // Skip to: 86948 -/* 80840 */ MCD_OPC_Decode, 225, 9, 249, 1, // Opcode: FMAXPv2i16p -/* 80845 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80861 -/* 80851 */ MCD_OPC_CheckPredicate, 3, 204, 23, 0, // Skip to: 86948 -/* 80856 */ MCD_OPC_Decode, 222, 11, 167, 3, // Opcode: FRECPXv1i32 -/* 80861 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 80877 -/* 80867 */ MCD_OPC_CheckPredicate, 4, 188, 23, 0, // Skip to: 86948 -/* 80872 */ MCD_OPC_Decode, 153, 10, 249, 1, // Opcode: FMINPv2i16p -/* 80877 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80893 -/* 80883 */ MCD_OPC_CheckPredicate, 3, 172, 23, 0, // Skip to: 86948 -/* 80888 */ MCD_OPC_Decode, 223, 11, 239, 1, // Opcode: FRECPXv1i64 -/* 80893 */ MCD_OPC_FilterValue, 249, 1, 161, 23, 0, // Skip to: 86948 -/* 80899 */ MCD_OPC_CheckPredicate, 4, 156, 23, 0, // Skip to: 86948 -/* 80904 */ MCD_OPC_Decode, 221, 11, 188, 3, // Opcode: FRECPXv1f16 -/* 80909 */ MCD_OPC_FilterValue, 63, 146, 23, 0, // Skip to: 86948 -/* 80914 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 80917 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 80932 -/* 80922 */ MCD_OPC_CheckPredicate, 3, 133, 23, 0, // Skip to: 86948 -/* 80927 */ MCD_OPC_Decode, 208, 11, 172, 3, // Opcode: FRECPS32 -/* 80932 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80947 -/* 80937 */ MCD_OPC_CheckPredicate, 3, 118, 23, 0, // Skip to: 86948 -/* 80942 */ MCD_OPC_Decode, 209, 11, 238, 1, // Opcode: FRECPS64 -/* 80947 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 80962 -/* 80952 */ MCD_OPC_CheckPredicate, 3, 103, 23, 0, // Skip to: 86948 -/* 80957 */ MCD_OPC_Decode, 185, 12, 172, 3, // Opcode: FRSQRTS32 -/* 80962 */ MCD_OPC_FilterValue, 7, 93, 23, 0, // Skip to: 86948 -/* 80967 */ MCD_OPC_CheckPredicate, 3, 88, 23, 0, // Skip to: 86948 -/* 80972 */ MCD_OPC_Decode, 186, 12, 238, 1, // Opcode: FRSQRTS64 -/* 80977 */ MCD_OPC_FilterValue, 3, 78, 23, 0, // Skip to: 86948 -/* 80982 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 80985 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 81014 -/* 80990 */ MCD_OPC_CheckPredicate, 3, 65, 23, 0, // Skip to: 86948 -/* 80995 */ MCD_OPC_CheckField, 22, 2, 1, 58, 23, 0, // Skip to: 86948 -/* 81002 */ MCD_OPC_CheckField, 10, 2, 1, 51, 23, 0, // Skip to: 86948 -/* 81009 */ MCD_OPC_Decode, 235, 26, 218, 3, // Opcode: SSHRd -/* 81014 */ MCD_OPC_FilterValue, 1, 98, 0, 0, // Skip to: 81117 -/* 81019 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81022 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81044 -/* 81027 */ MCD_OPC_CheckPredicate, 4, 28, 23, 0, // Skip to: 86948 -/* 81032 */ MCD_OPC_CheckField, 10, 1, 0, 21, 23, 0, // Skip to: 86948 -/* 81039 */ MCD_OPC_Decode, 183, 10, 219, 3, // Opcode: FMLAv1i16_indexed -/* 81044 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81066 -/* 81049 */ MCD_OPC_CheckPredicate, 3, 6, 23, 0, // Skip to: 86948 -/* 81054 */ MCD_OPC_CheckField, 10, 2, 1, 255, 22, 0, // Skip to: 86948 -/* 81061 */ MCD_OPC_Decode, 243, 26, 220, 3, // Opcode: SSRAd -/* 81066 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 81088 -/* 81071 */ MCD_OPC_CheckPredicate, 3, 240, 22, 0, // Skip to: 86948 -/* 81076 */ MCD_OPC_CheckField, 10, 1, 0, 233, 22, 0, // Skip to: 86948 -/* 81083 */ MCD_OPC_Decode, 184, 10, 221, 3, // Opcode: FMLAv1i32_indexed -/* 81088 */ MCD_OPC_FilterValue, 3, 223, 22, 0, // Skip to: 86948 -/* 81093 */ MCD_OPC_CheckPredicate, 3, 218, 22, 0, // Skip to: 86948 -/* 81098 */ MCD_OPC_CheckField, 21, 1, 0, 211, 22, 0, // Skip to: 86948 -/* 81105 */ MCD_OPC_CheckField, 10, 1, 0, 204, 22, 0, // Skip to: 86948 -/* 81112 */ MCD_OPC_Decode, 185, 10, 222, 3, // Opcode: FMLAv1i64_indexed -/* 81117 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 81146 -/* 81122 */ MCD_OPC_CheckPredicate, 3, 189, 22, 0, // Skip to: 86948 -/* 81127 */ MCD_OPC_CheckField, 22, 2, 1, 182, 22, 0, // Skip to: 86948 -/* 81134 */ MCD_OPC_CheckField, 10, 2, 1, 175, 22, 0, // Skip to: 86948 -/* 81141 */ MCD_OPC_Decode, 205, 26, 218, 3, // Opcode: SRSHRd -/* 81146 */ MCD_OPC_FilterValue, 3, 70, 0, 0, // Skip to: 81221 -/* 81151 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 81154 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 81192 -/* 81159 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81162 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 81177 -/* 81167 */ MCD_OPC_CheckPredicate, 3, 144, 22, 0, // Skip to: 86948 -/* 81172 */ MCD_OPC_Decode, 207, 24, 223, 3, // Opcode: SQDMLALv1i32_indexed -/* 81177 */ MCD_OPC_FilterValue, 2, 134, 22, 0, // Skip to: 86948 -/* 81182 */ MCD_OPC_CheckPredicate, 3, 129, 22, 0, // Skip to: 86948 -/* 81187 */ MCD_OPC_Decode, 208, 24, 224, 3, // Opcode: SQDMLALv1i64_indexed -/* 81192 */ MCD_OPC_FilterValue, 1, 119, 22, 0, // Skip to: 86948 -/* 81197 */ MCD_OPC_CheckPredicate, 3, 114, 22, 0, // Skip to: 86948 -/* 81202 */ MCD_OPC_CheckField, 22, 2, 1, 107, 22, 0, // Skip to: 86948 -/* 81209 */ MCD_OPC_CheckField, 11, 1, 0, 100, 22, 0, // Skip to: 86948 -/* 81216 */ MCD_OPC_Decode, 213, 26, 220, 3, // Opcode: SRSRAd -/* 81221 */ MCD_OPC_FilterValue, 5, 98, 0, 0, // Skip to: 81324 -/* 81226 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81229 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81251 -/* 81234 */ MCD_OPC_CheckPredicate, 4, 77, 22, 0, // Skip to: 86948 -/* 81239 */ MCD_OPC_CheckField, 10, 1, 0, 70, 22, 0, // Skip to: 86948 -/* 81246 */ MCD_OPC_Decode, 202, 10, 219, 3, // Opcode: FMLSv1i16_indexed -/* 81251 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81273 -/* 81256 */ MCD_OPC_CheckPredicate, 3, 55, 22, 0, // Skip to: 86948 -/* 81261 */ MCD_OPC_CheckField, 10, 2, 1, 48, 22, 0, // Skip to: 86948 -/* 81268 */ MCD_OPC_Decode, 139, 23, 225, 3, // Opcode: SHLd -/* 81273 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 81295 -/* 81278 */ MCD_OPC_CheckPredicate, 3, 33, 22, 0, // Skip to: 86948 -/* 81283 */ MCD_OPC_CheckField, 10, 1, 0, 26, 22, 0, // Skip to: 86948 -/* 81290 */ MCD_OPC_Decode, 203, 10, 221, 3, // Opcode: FMLSv1i32_indexed -/* 81295 */ MCD_OPC_FilterValue, 3, 16, 22, 0, // Skip to: 86948 -/* 81300 */ MCD_OPC_CheckPredicate, 3, 11, 22, 0, // Skip to: 86948 -/* 81305 */ MCD_OPC_CheckField, 21, 1, 0, 4, 22, 0, // Skip to: 86948 -/* 81312 */ MCD_OPC_CheckField, 10, 1, 0, 253, 21, 0, // Skip to: 86948 -/* 81319 */ MCD_OPC_Decode, 204, 10, 222, 3, // Opcode: FMLSv1i64_indexed -/* 81324 */ MCD_OPC_FilterValue, 7, 159, 0, 0, // Skip to: 81488 -/* 81329 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81332 */ MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 81421 -/* 81337 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 81340 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 81399 -/* 81345 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 81348 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 81377 -/* 81353 */ MCD_OPC_CheckPredicate, 3, 214, 21, 0, // Skip to: 86948 -/* 81358 */ MCD_OPC_CheckField, 19, 1, 1, 207, 21, 0, // Skip to: 86948 -/* 81365 */ MCD_OPC_CheckField, 10, 2, 1, 200, 21, 0, // Skip to: 86948 -/* 81372 */ MCD_OPC_Decode, 234, 25, 226, 3, // Opcode: SQSHLb -/* 81377 */ MCD_OPC_FilterValue, 1, 190, 21, 0, // Skip to: 86948 -/* 81382 */ MCD_OPC_CheckPredicate, 3, 185, 21, 0, // Skip to: 86948 -/* 81387 */ MCD_OPC_CheckField, 10, 2, 1, 178, 21, 0, // Skip to: 86948 -/* 81394 */ MCD_OPC_Decode, 236, 25, 227, 3, // Opcode: SQSHLh -/* 81399 */ MCD_OPC_FilterValue, 1, 168, 21, 0, // Skip to: 86948 -/* 81404 */ MCD_OPC_CheckPredicate, 3, 163, 21, 0, // Skip to: 86948 -/* 81409 */ MCD_OPC_CheckField, 10, 2, 1, 156, 21, 0, // Skip to: 86948 -/* 81416 */ MCD_OPC_Decode, 237, 25, 228, 3, // Opcode: SQSHLs -/* 81421 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 81466 -/* 81426 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 81429 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 81444 -/* 81434 */ MCD_OPC_CheckPredicate, 3, 133, 21, 0, // Skip to: 86948 -/* 81439 */ MCD_OPC_Decode, 219, 24, 223, 3, // Opcode: SQDMLSLv1i32_indexed -/* 81444 */ MCD_OPC_FilterValue, 1, 123, 21, 0, // Skip to: 86948 -/* 81449 */ MCD_OPC_CheckPredicate, 3, 118, 21, 0, // Skip to: 86948 -/* 81454 */ MCD_OPC_CheckField, 11, 1, 0, 111, 21, 0, // Skip to: 86948 -/* 81461 */ MCD_OPC_Decode, 235, 25, 225, 3, // Opcode: SQSHLd -/* 81466 */ MCD_OPC_FilterValue, 2, 101, 21, 0, // Skip to: 86948 -/* 81471 */ MCD_OPC_CheckPredicate, 3, 96, 21, 0, // Skip to: 86948 -/* 81476 */ MCD_OPC_CheckField, 10, 1, 0, 89, 21, 0, // Skip to: 86948 -/* 81483 */ MCD_OPC_Decode, 220, 24, 224, 3, // Opcode: SQDMLSLv1i64_indexed -/* 81488 */ MCD_OPC_FilterValue, 9, 221, 0, 0, // Skip to: 81714 -/* 81493 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81496 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 81663 -/* 81501 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 81504 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 81519 -/* 81509 */ MCD_OPC_CheckPredicate, 4, 58, 21, 0, // Skip to: 86948 -/* 81514 */ MCD_OPC_Decode, 151, 11, 229, 3, // Opcode: FMULv1i16_indexed -/* 81519 */ MCD_OPC_FilterValue, 1, 48, 21, 0, // Skip to: 86948 -/* 81524 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 81527 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 81595 -/* 81532 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 81535 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 81580 -/* 81540 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 81543 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81565 -/* 81548 */ MCD_OPC_CheckPredicate, 3, 19, 21, 0, // Skip to: 86948 -/* 81553 */ MCD_OPC_CheckField, 19, 1, 1, 12, 21, 0, // Skip to: 86948 -/* 81560 */ MCD_OPC_Decode, 128, 26, 230, 3, // Opcode: SQSHRNb -/* 81565 */ MCD_OPC_FilterValue, 1, 2, 21, 0, // Skip to: 86948 -/* 81570 */ MCD_OPC_CheckPredicate, 3, 253, 20, 0, // Skip to: 86948 -/* 81575 */ MCD_OPC_Decode, 129, 26, 231, 3, // Opcode: SQSHRNh -/* 81580 */ MCD_OPC_FilterValue, 1, 243, 20, 0, // Skip to: 86948 -/* 81585 */ MCD_OPC_CheckPredicate, 3, 238, 20, 0, // Skip to: 86948 -/* 81590 */ MCD_OPC_Decode, 130, 26, 232, 3, // Opcode: SQSHRNs -/* 81595 */ MCD_OPC_FilterValue, 1, 228, 20, 0, // Skip to: 86948 -/* 81600 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 81603 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 81648 -/* 81608 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 81611 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81633 -/* 81616 */ MCD_OPC_CheckPredicate, 3, 207, 20, 0, // Skip to: 86948 -/* 81621 */ MCD_OPC_CheckField, 19, 1, 1, 200, 20, 0, // Skip to: 86948 -/* 81628 */ MCD_OPC_Decode, 205, 25, 230, 3, // Opcode: SQRSHRNb -/* 81633 */ MCD_OPC_FilterValue, 1, 190, 20, 0, // Skip to: 86948 -/* 81638 */ MCD_OPC_CheckPredicate, 3, 185, 20, 0, // Skip to: 86948 -/* 81643 */ MCD_OPC_Decode, 206, 25, 231, 3, // Opcode: SQRSHRNh -/* 81648 */ MCD_OPC_FilterValue, 1, 175, 20, 0, // Skip to: 86948 -/* 81653 */ MCD_OPC_CheckPredicate, 3, 170, 20, 0, // Skip to: 86948 -/* 81658 */ MCD_OPC_Decode, 207, 25, 232, 3, // Opcode: SQRSHRNs -/* 81663 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 81685 -/* 81668 */ MCD_OPC_CheckPredicate, 3, 155, 20, 0, // Skip to: 86948 -/* 81673 */ MCD_OPC_CheckField, 10, 1, 0, 148, 20, 0, // Skip to: 86948 -/* 81680 */ MCD_OPC_Decode, 152, 11, 233, 3, // Opcode: FMULv1i32_indexed -/* 81685 */ MCD_OPC_FilterValue, 3, 138, 20, 0, // Skip to: 86948 -/* 81690 */ MCD_OPC_CheckPredicate, 3, 133, 20, 0, // Skip to: 86948 -/* 81695 */ MCD_OPC_CheckField, 21, 1, 0, 126, 20, 0, // Skip to: 86948 -/* 81702 */ MCD_OPC_CheckField, 10, 1, 0, 119, 20, 0, // Skip to: 86948 -/* 81709 */ MCD_OPC_Decode, 153, 11, 234, 3, // Opcode: FMULv1i64_indexed -/* 81714 */ MCD_OPC_FilterValue, 11, 47, 0, 0, // Skip to: 81766 -/* 81719 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81722 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81744 -/* 81727 */ MCD_OPC_CheckPredicate, 3, 96, 20, 0, // Skip to: 86948 -/* 81732 */ MCD_OPC_CheckField, 10, 1, 0, 89, 20, 0, // Skip to: 86948 -/* 81739 */ MCD_OPC_Decode, 243, 24, 235, 3, // Opcode: SQDMULLv1i32_indexed -/* 81744 */ MCD_OPC_FilterValue, 2, 79, 20, 0, // Skip to: 86948 -/* 81749 */ MCD_OPC_CheckPredicate, 3, 74, 20, 0, // Skip to: 86948 -/* 81754 */ MCD_OPC_CheckField, 10, 1, 0, 67, 20, 0, // Skip to: 86948 -/* 81761 */ MCD_OPC_Decode, 244, 24, 236, 3, // Opcode: SQDMULLv1i64_indexed -/* 81766 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 81818 -/* 81771 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81774 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81796 -/* 81779 */ MCD_OPC_CheckPredicate, 3, 44, 20, 0, // Skip to: 86948 -/* 81784 */ MCD_OPC_CheckField, 10, 1, 0, 37, 20, 0, // Skip to: 86948 -/* 81791 */ MCD_OPC_Decode, 230, 24, 229, 3, // Opcode: SQDMULHv1i16_indexed -/* 81796 */ MCD_OPC_FilterValue, 2, 27, 20, 0, // Skip to: 86948 -/* 81801 */ MCD_OPC_CheckPredicate, 3, 22, 20, 0, // Skip to: 86948 -/* 81806 */ MCD_OPC_CheckField, 10, 1, 0, 15, 20, 0, // Skip to: 86948 -/* 81813 */ MCD_OPC_Decode, 232, 24, 233, 3, // Opcode: SQDMULHv1i32_indexed -/* 81818 */ MCD_OPC_FilterValue, 13, 47, 0, 0, // Skip to: 81870 -/* 81823 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81826 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81848 -/* 81831 */ MCD_OPC_CheckPredicate, 3, 248, 19, 0, // Skip to: 86948 -/* 81836 */ MCD_OPC_CheckField, 10, 1, 0, 241, 19, 0, // Skip to: 86948 -/* 81843 */ MCD_OPC_Decode, 183, 25, 229, 3, // Opcode: SQRDMULHv1i16_indexed -/* 81848 */ MCD_OPC_FilterValue, 2, 231, 19, 0, // Skip to: 86948 -/* 81853 */ MCD_OPC_CheckPredicate, 3, 226, 19, 0, // Skip to: 86948 -/* 81858 */ MCD_OPC_CheckField, 10, 1, 0, 219, 19, 0, // Skip to: 86948 -/* 81865 */ MCD_OPC_Decode, 185, 25, 233, 3, // Opcode: SQRDMULHv1i32_indexed -/* 81870 */ MCD_OPC_FilterValue, 14, 84, 0, 0, // Skip to: 81959 -/* 81875 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81878 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 81937 -/* 81883 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 81886 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 81915 -/* 81891 */ MCD_OPC_CheckPredicate, 4, 188, 19, 0, // Skip to: 86948 -/* 81896 */ MCD_OPC_CheckField, 20, 1, 1, 181, 19, 0, // Skip to: 86948 -/* 81903 */ MCD_OPC_CheckField, 10, 2, 1, 174, 19, 0, // Skip to: 86948 -/* 81910 */ MCD_OPC_Decode, 204, 22, 237, 3, // Opcode: SCVTFh -/* 81915 */ MCD_OPC_FilterValue, 1, 164, 19, 0, // Skip to: 86948 -/* 81920 */ MCD_OPC_CheckPredicate, 3, 159, 19, 0, // Skip to: 86948 -/* 81925 */ MCD_OPC_CheckField, 10, 2, 1, 152, 19, 0, // Skip to: 86948 -/* 81932 */ MCD_OPC_Decode, 205, 22, 238, 3, // Opcode: SCVTFs -/* 81937 */ MCD_OPC_FilterValue, 1, 142, 19, 0, // Skip to: 86948 -/* 81942 */ MCD_OPC_CheckPredicate, 3, 137, 19, 0, // Skip to: 86948 -/* 81947 */ MCD_OPC_CheckField, 10, 2, 1, 130, 19, 0, // Skip to: 86948 -/* 81954 */ MCD_OPC_Decode, 203, 22, 218, 3, // Opcode: SCVTFd -/* 81959 */ MCD_OPC_FilterValue, 15, 120, 19, 0, // Skip to: 86948 -/* 81964 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 81967 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 82026 -/* 81972 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 81975 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 82004 -/* 81980 */ MCD_OPC_CheckPredicate, 4, 99, 19, 0, // Skip to: 86948 -/* 81985 */ MCD_OPC_CheckField, 20, 1, 1, 92, 19, 0, // Skip to: 86948 -/* 81992 */ MCD_OPC_CheckField, 10, 2, 3, 85, 19, 0, // Skip to: 86948 -/* 81999 */ MCD_OPC_Decode, 238, 8, 237, 3, // Opcode: FCVTZSh -/* 82004 */ MCD_OPC_FilterValue, 1, 75, 19, 0, // Skip to: 86948 -/* 82009 */ MCD_OPC_CheckPredicate, 3, 70, 19, 0, // Skip to: 86948 -/* 82014 */ MCD_OPC_CheckField, 10, 2, 3, 63, 19, 0, // Skip to: 86948 -/* 82021 */ MCD_OPC_Decode, 239, 8, 238, 3, // Opcode: FCVTZSs -/* 82026 */ MCD_OPC_FilterValue, 1, 53, 19, 0, // Skip to: 86948 -/* 82031 */ MCD_OPC_CheckPredicate, 3, 48, 19, 0, // Skip to: 86948 -/* 82036 */ MCD_OPC_CheckField, 10, 2, 3, 41, 19, 0, // Skip to: 86948 -/* 82043 */ MCD_OPC_Decode, 237, 8, 218, 3, // Opcode: FCVTZSd -/* 82048 */ MCD_OPC_FilterValue, 3, 213, 12, 0, // Skip to: 85338 -/* 82053 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 82056 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 82157 -/* 82061 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 82064 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 82081 -/* 82069 */ MCD_OPC_CheckField, 21, 1, 0, 8, 19, 0, // Skip to: 86948 -/* 82076 */ MCD_OPC_Decode, 200, 29, 255, 2, // Opcode: STURHi -/* 82081 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 82098 -/* 82086 */ MCD_OPC_CheckField, 21, 1, 0, 247, 18, 0, // Skip to: 86948 -/* 82093 */ MCD_OPC_Decode, 165, 29, 255, 2, // Opcode: STRHpost -/* 82098 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 82140 -/* 82103 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 82106 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 82123 -/* 82111 */ MCD_OPC_CheckField, 21, 1, 1, 222, 18, 0, // Skip to: 86948 -/* 82118 */ MCD_OPC_Decode, 167, 29, 239, 3, // Opcode: STRHroW -/* 82123 */ MCD_OPC_FilterValue, 3, 212, 18, 0, // Skip to: 86948 -/* 82128 */ MCD_OPC_CheckField, 21, 1, 1, 205, 18, 0, // Skip to: 86948 -/* 82135 */ MCD_OPC_Decode, 168, 29, 240, 3, // Opcode: STRHroX -/* 82140 */ MCD_OPC_FilterValue, 3, 195, 18, 0, // Skip to: 86948 -/* 82145 */ MCD_OPC_CheckField, 21, 1, 0, 188, 18, 0, // Skip to: 86948 -/* 82152 */ MCD_OPC_Decode, 166, 29, 255, 2, // Opcode: STRHpre -/* 82157 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 82258 -/* 82162 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 82165 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 82182 -/* 82170 */ MCD_OPC_CheckField, 21, 1, 0, 163, 18, 0, // Skip to: 86948 -/* 82177 */ MCD_OPC_Decode, 134, 19, 255, 2, // Opcode: LDURHi -/* 82182 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 82199 -/* 82187 */ MCD_OPC_CheckField, 21, 1, 0, 146, 18, 0, // Skip to: 86948 -/* 82194 */ MCD_OPC_Decode, 240, 17, 255, 2, // Opcode: LDRHpost -/* 82199 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 82241 -/* 82204 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 82207 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 82224 -/* 82212 */ MCD_OPC_CheckField, 21, 1, 1, 121, 18, 0, // Skip to: 86948 -/* 82219 */ MCD_OPC_Decode, 242, 17, 239, 3, // Opcode: LDRHroW -/* 82224 */ MCD_OPC_FilterValue, 3, 111, 18, 0, // Skip to: 86948 -/* 82229 */ MCD_OPC_CheckField, 21, 1, 1, 104, 18, 0, // Skip to: 86948 -/* 82236 */ MCD_OPC_Decode, 243, 17, 240, 3, // Opcode: LDRHroX -/* 82241 */ MCD_OPC_FilterValue, 3, 94, 18, 0, // Skip to: 86948 -/* 82246 */ MCD_OPC_CheckField, 21, 1, 0, 87, 18, 0, // Skip to: 86948 -/* 82253 */ MCD_OPC_Decode, 241, 17, 255, 2, // Opcode: LDRHpre -/* 82258 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 82268 -/* 82263 */ MCD_OPC_Decode, 169, 29, 137, 3, // Opcode: STRHui -/* 82268 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 82278 -/* 82273 */ MCD_OPC_Decode, 244, 17, 137, 3, // Opcode: LDRHui -/* 82278 */ MCD_OPC_FilterValue, 8, 109, 1, 0, // Skip to: 82648 -/* 82283 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 82286 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 82308 -/* 82291 */ MCD_OPC_CheckPredicate, 3, 44, 18, 0, // Skip to: 86948 -/* 82296 */ MCD_OPC_CheckField, 21, 1, 1, 37, 18, 0, // Skip to: 86948 -/* 82303 */ MCD_OPC_Decode, 215, 32, 208, 3, // Opcode: UQADDv1i8 -/* 82308 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 82330 -/* 82313 */ MCD_OPC_CheckPredicate, 3, 22, 18, 0, // Skip to: 86948 -/* 82318 */ MCD_OPC_CheckField, 16, 6, 33, 15, 18, 0, // Skip to: 86948 -/* 82325 */ MCD_OPC_Decode, 177, 26, 212, 3, // Opcode: SQXTUNv1i8 -/* 82330 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 82352 -/* 82335 */ MCD_OPC_CheckPredicate, 3, 0, 18, 0, // Skip to: 86948 -/* 82340 */ MCD_OPC_CheckField, 21, 1, 1, 249, 17, 0, // Skip to: 86948 -/* 82347 */ MCD_OPC_Decode, 201, 33, 208, 3, // Opcode: UQSUBv1i8 -/* 82352 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 82374 -/* 82357 */ MCD_OPC_CheckPredicate, 3, 234, 17, 0, // Skip to: 86948 -/* 82362 */ MCD_OPC_CheckField, 16, 6, 32, 227, 17, 0, // Skip to: 86948 -/* 82369 */ MCD_OPC_Decode, 149, 34, 209, 3, // Opcode: USQADDv1i8 -/* 82374 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 82396 -/* 82379 */ MCD_OPC_CheckPredicate, 3, 212, 17, 0, // Skip to: 86948 -/* 82384 */ MCD_OPC_CheckField, 16, 6, 33, 205, 17, 0, // Skip to: 86948 -/* 82391 */ MCD_OPC_Decode, 211, 33, 212, 3, // Opcode: UQXTNv1i8 -/* 82396 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 82418 -/* 82401 */ MCD_OPC_CheckPredicate, 3, 190, 17, 0, // Skip to: 86948 -/* 82406 */ MCD_OPC_CheckField, 21, 1, 1, 183, 17, 0, // Skip to: 86948 -/* 82413 */ MCD_OPC_Decode, 167, 33, 208, 3, // Opcode: UQSHLv1i8 -/* 82418 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 82440 -/* 82423 */ MCD_OPC_CheckPredicate, 3, 168, 17, 0, // Skip to: 86948 -/* 82428 */ MCD_OPC_CheckField, 21, 1, 1, 161, 17, 0, // Skip to: 86948 -/* 82435 */ MCD_OPC_Decode, 142, 33, 208, 3, // Opcode: UQRSHLv1i8 -/* 82440 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 82462 -/* 82445 */ MCD_OPC_CheckPredicate, 3, 146, 17, 0, // Skip to: 86948 -/* 82450 */ MCD_OPC_CheckField, 16, 6, 32, 139, 17, 0, // Skip to: 86948 -/* 82457 */ MCD_OPC_Decode, 151, 25, 213, 3, // Opcode: SQNEGv1i8 -/* 82462 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 82484 -/* 82467 */ MCD_OPC_CheckPredicate, 3, 124, 17, 0, // Skip to: 86948 -/* 82472 */ MCD_OPC_CheckField, 16, 6, 33, 117, 17, 0, // Skip to: 86948 -/* 82479 */ MCD_OPC_Decode, 174, 8, 167, 3, // Opcode: FCVTNUv1i32 -/* 82484 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 82506 -/* 82489 */ MCD_OPC_CheckPredicate, 3, 102, 17, 0, // Skip to: 86948 -/* 82494 */ MCD_OPC_CheckField, 16, 6, 33, 95, 17, 0, // Skip to: 86948 -/* 82501 */ MCD_OPC_Decode, 146, 8, 167, 3, // Opcode: FCVTMUv1i32 -/* 82506 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 82544 -/* 82511 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 82514 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 82529 -/* 82519 */ MCD_OPC_CheckPredicate, 3, 72, 17, 0, // Skip to: 86948 -/* 82524 */ MCD_OPC_Decode, 238, 7, 167, 3, // Opcode: FCVTAUv1i32 -/* 82529 */ MCD_OPC_FilterValue, 48, 62, 17, 0, // Skip to: 86948 -/* 82534 */ MCD_OPC_CheckPredicate, 3, 57, 17, 0, // Skip to: 86948 -/* 82539 */ MCD_OPC_Decode, 200, 9, 166, 2, // Opcode: FMAXNMPv2i32p -/* 82544 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 82582 -/* 82549 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 82552 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 82567 -/* 82557 */ MCD_OPC_CheckPredicate, 3, 34, 17, 0, // Skip to: 86948 -/* 82562 */ MCD_OPC_Decode, 194, 31, 167, 3, // Opcode: UCVTFv1i32 -/* 82567 */ MCD_OPC_FilterValue, 48, 24, 17, 0, // Skip to: 86948 -/* 82572 */ MCD_OPC_CheckPredicate, 3, 19, 17, 0, // Skip to: 86948 -/* 82577 */ MCD_OPC_Decode, 180, 6, 166, 2, // Opcode: FADDPv2i32p -/* 82582 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 82604 -/* 82587 */ MCD_OPC_CheckPredicate, 3, 4, 17, 0, // Skip to: 86948 -/* 82592 */ MCD_OPC_CheckField, 21, 1, 1, 253, 16, 0, // Skip to: 86948 -/* 82599 */ MCD_OPC_Decode, 240, 6, 172, 3, // Opcode: FCMGE32 -/* 82604 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 82626 -/* 82609 */ MCD_OPC_CheckPredicate, 3, 238, 16, 0, // Skip to: 86948 -/* 82614 */ MCD_OPC_CheckField, 21, 1, 1, 231, 16, 0, // Skip to: 86948 -/* 82621 */ MCD_OPC_Decode, 151, 6, 172, 3, // Opcode: FACGE32 -/* 82626 */ MCD_OPC_FilterValue, 62, 221, 16, 0, // Skip to: 86948 -/* 82631 */ MCD_OPC_CheckPredicate, 3, 216, 16, 0, // Skip to: 86948 -/* 82636 */ MCD_OPC_CheckField, 16, 6, 48, 209, 16, 0, // Skip to: 86948 -/* 82643 */ MCD_OPC_Decode, 226, 9, 166, 2, // Opcode: FMAXPv2i32p -/* 82648 */ MCD_OPC_FilterValue, 9, 41, 2, 0, // Skip to: 83206 -/* 82653 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 82656 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 82678 -/* 82661 */ MCD_OPC_CheckPredicate, 3, 186, 16, 0, // Skip to: 86948 -/* 82666 */ MCD_OPC_CheckField, 21, 1, 1, 179, 16, 0, // Skip to: 86948 -/* 82673 */ MCD_OPC_Decode, 212, 32, 193, 3, // Opcode: UQADDv1i16 -/* 82678 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 82700 -/* 82683 */ MCD_OPC_CheckPredicate, 4, 164, 16, 0, // Skip to: 86948 -/* 82688 */ MCD_OPC_CheckField, 21, 1, 0, 157, 16, 0, // Skip to: 86948 -/* 82695 */ MCD_OPC_Decode, 239, 6, 193, 3, // Opcode: FCMGE16 -/* 82700 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 82722 -/* 82705 */ MCD_OPC_CheckPredicate, 3, 142, 16, 0, // Skip to: 86948 -/* 82710 */ MCD_OPC_CheckField, 16, 6, 33, 135, 16, 0, // Skip to: 86948 -/* 82717 */ MCD_OPC_Decode, 175, 26, 169, 3, // Opcode: SQXTUNv1i16 -/* 82722 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 82760 -/* 82727 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 82730 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 82745 -/* 82735 */ MCD_OPC_CheckPredicate, 4, 112, 16, 0, // Skip to: 86948 -/* 82740 */ MCD_OPC_Decode, 150, 6, 193, 3, // Opcode: FACGE16 -/* 82745 */ MCD_OPC_FilterValue, 1, 102, 16, 0, // Skip to: 86948 -/* 82750 */ MCD_OPC_CheckPredicate, 3, 97, 16, 0, // Skip to: 86948 -/* 82755 */ MCD_OPC_Decode, 198, 33, 193, 3, // Opcode: UQSUBv1i16 -/* 82760 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 82782 -/* 82765 */ MCD_OPC_CheckPredicate, 3, 82, 16, 0, // Skip to: 86948 -/* 82770 */ MCD_OPC_CheckField, 16, 6, 32, 75, 16, 0, // Skip to: 86948 -/* 82777 */ MCD_OPC_Decode, 146, 34, 210, 3, // Opcode: USQADDv1i16 -/* 82782 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 82804 -/* 82787 */ MCD_OPC_CheckPredicate, 3, 60, 16, 0, // Skip to: 86948 -/* 82792 */ MCD_OPC_CheckField, 16, 6, 33, 53, 16, 0, // Skip to: 86948 -/* 82799 */ MCD_OPC_Decode, 209, 33, 169, 3, // Opcode: UQXTNv1i16 -/* 82804 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 82826 -/* 82809 */ MCD_OPC_CheckPredicate, 3, 38, 16, 0, // Skip to: 86948 -/* 82814 */ MCD_OPC_CheckField, 21, 1, 1, 31, 16, 0, // Skip to: 86948 -/* 82821 */ MCD_OPC_Decode, 164, 33, 193, 3, // Opcode: UQSHLv1i16 -/* 82826 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 82848 -/* 82831 */ MCD_OPC_CheckPredicate, 3, 16, 16, 0, // Skip to: 86948 -/* 82836 */ MCD_OPC_CheckField, 21, 1, 1, 9, 16, 0, // Skip to: 86948 -/* 82843 */ MCD_OPC_Decode, 139, 33, 193, 3, // Opcode: UQRSHLv1i16 -/* 82848 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 82870 -/* 82853 */ MCD_OPC_CheckPredicate, 3, 250, 15, 0, // Skip to: 86948 -/* 82858 */ MCD_OPC_CheckField, 16, 6, 33, 243, 15, 0, // Skip to: 86948 -/* 82865 */ MCD_OPC_Decode, 215, 8, 166, 2, // Opcode: FCVTXNv1i64 -/* 82870 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 82892 -/* 82875 */ MCD_OPC_CheckPredicate, 3, 228, 15, 0, // Skip to: 86948 -/* 82880 */ MCD_OPC_CheckField, 16, 6, 32, 221, 15, 0, // Skip to: 86948 -/* 82887 */ MCD_OPC_Decode, 148, 25, 188, 3, // Opcode: SQNEGv1i16 -/* 82892 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 82914 -/* 82897 */ MCD_OPC_CheckPredicate, 20, 206, 15, 0, // Skip to: 86948 -/* 82902 */ MCD_OPC_CheckField, 21, 1, 0, 199, 15, 0, // Skip to: 86948 -/* 82909 */ MCD_OPC_Decode, 160, 25, 241, 3, // Opcode: SQRDMLAHv1i16 -/* 82914 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 82936 -/* 82919 */ MCD_OPC_CheckPredicate, 20, 184, 15, 0, // Skip to: 86948 -/* 82924 */ MCD_OPC_CheckField, 21, 1, 0, 177, 15, 0, // Skip to: 86948 -/* 82931 */ MCD_OPC_Decode, 172, 25, 241, 3, // Opcode: SQRDMLSHv1i16 -/* 82936 */ MCD_OPC_FilterValue, 42, 33, 0, 0, // Skip to: 82974 -/* 82941 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 82944 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 82959 -/* 82949 */ MCD_OPC_CheckPredicate, 3, 154, 15, 0, // Skip to: 86948 -/* 82954 */ MCD_OPC_Decode, 175, 8, 239, 1, // Opcode: FCVTNUv1i64 -/* 82959 */ MCD_OPC_FilterValue, 57, 144, 15, 0, // Skip to: 86948 -/* 82964 */ MCD_OPC_CheckPredicate, 4, 139, 15, 0, // Skip to: 86948 -/* 82969 */ MCD_OPC_Decode, 173, 8, 188, 3, // Opcode: FCVTNUv1f16 -/* 82974 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 82996 -/* 82979 */ MCD_OPC_CheckPredicate, 3, 124, 15, 0, // Skip to: 86948 -/* 82984 */ MCD_OPC_CheckField, 21, 1, 1, 117, 15, 0, // Skip to: 86948 -/* 82991 */ MCD_OPC_Decode, 182, 25, 193, 3, // Opcode: SQRDMULHv1i16 -/* 82996 */ MCD_OPC_FilterValue, 46, 33, 0, 0, // Skip to: 83034 -/* 83001 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 83004 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 83019 -/* 83009 */ MCD_OPC_CheckPredicate, 3, 94, 15, 0, // Skip to: 86948 -/* 83014 */ MCD_OPC_Decode, 147, 8, 239, 1, // Opcode: FCVTMUv1i64 -/* 83019 */ MCD_OPC_FilterValue, 57, 84, 15, 0, // Skip to: 86948 -/* 83024 */ MCD_OPC_CheckPredicate, 4, 79, 15, 0, // Skip to: 86948 -/* 83029 */ MCD_OPC_Decode, 145, 8, 188, 3, // Opcode: FCVTMUv1f16 -/* 83034 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 83087 -/* 83039 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 83042 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 83057 -/* 83047 */ MCD_OPC_CheckPredicate, 3, 56, 15, 0, // Skip to: 86948 -/* 83052 */ MCD_OPC_Decode, 239, 7, 239, 1, // Opcode: FCVTAUv1i64 -/* 83057 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 83072 -/* 83062 */ MCD_OPC_CheckPredicate, 3, 41, 15, 0, // Skip to: 86948 -/* 83067 */ MCD_OPC_Decode, 201, 9, 244, 1, // Opcode: FMAXNMPv2i64p -/* 83072 */ MCD_OPC_FilterValue, 57, 31, 15, 0, // Skip to: 86948 -/* 83077 */ MCD_OPC_CheckPredicate, 4, 26, 15, 0, // Skip to: 86948 -/* 83082 */ MCD_OPC_Decode, 237, 7, 188, 3, // Opcode: FCVTAUv1f16 -/* 83087 */ MCD_OPC_FilterValue, 54, 48, 0, 0, // Skip to: 83140 -/* 83092 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 83095 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 83110 -/* 83100 */ MCD_OPC_CheckPredicate, 3, 3, 15, 0, // Skip to: 86948 -/* 83105 */ MCD_OPC_Decode, 195, 31, 239, 1, // Opcode: UCVTFv1i64 -/* 83110 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 83125 -/* 83115 */ MCD_OPC_CheckPredicate, 3, 244, 14, 0, // Skip to: 86948 -/* 83120 */ MCD_OPC_Decode, 181, 6, 244, 1, // Opcode: FADDPv2i64p -/* 83125 */ MCD_OPC_FilterValue, 57, 234, 14, 0, // Skip to: 86948 -/* 83130 */ MCD_OPC_CheckPredicate, 4, 229, 14, 0, // Skip to: 86948 -/* 83135 */ MCD_OPC_Decode, 193, 31, 188, 3, // Opcode: UCVTFv1i16 -/* 83140 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 83162 -/* 83145 */ MCD_OPC_CheckPredicate, 3, 214, 14, 0, // Skip to: 86948 -/* 83150 */ MCD_OPC_CheckField, 21, 1, 1, 207, 14, 0, // Skip to: 86948 -/* 83157 */ MCD_OPC_Decode, 241, 6, 238, 1, // Opcode: FCMGE64 -/* 83162 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 83184 -/* 83167 */ MCD_OPC_CheckPredicate, 3, 192, 14, 0, // Skip to: 86948 -/* 83172 */ MCD_OPC_CheckField, 21, 1, 1, 185, 14, 0, // Skip to: 86948 -/* 83179 */ MCD_OPC_Decode, 152, 6, 238, 1, // Opcode: FACGE64 -/* 83184 */ MCD_OPC_FilterValue, 62, 175, 14, 0, // Skip to: 86948 -/* 83189 */ MCD_OPC_CheckPredicate, 3, 170, 14, 0, // Skip to: 86948 -/* 83194 */ MCD_OPC_CheckField, 16, 6, 48, 163, 14, 0, // Skip to: 86948 -/* 83201 */ MCD_OPC_Decode, 227, 9, 244, 1, // Opcode: FMAXPv2i64p -/* 83206 */ MCD_OPC_FilterValue, 10, 197, 1, 0, // Skip to: 83664 -/* 83211 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 83214 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 83236 -/* 83219 */ MCD_OPC_CheckPredicate, 3, 140, 14, 0, // Skip to: 86948 -/* 83224 */ MCD_OPC_CheckField, 21, 1, 1, 133, 14, 0, // Skip to: 86948 -/* 83231 */ MCD_OPC_Decode, 213, 32, 172, 3, // Opcode: UQADDv1i32 -/* 83236 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 83258 -/* 83241 */ MCD_OPC_CheckPredicate, 3, 118, 14, 0, // Skip to: 86948 -/* 83246 */ MCD_OPC_CheckField, 16, 6, 33, 111, 14, 0, // Skip to: 86948 -/* 83253 */ MCD_OPC_Decode, 176, 26, 166, 2, // Opcode: SQXTUNv1i32 -/* 83258 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 83280 -/* 83263 */ MCD_OPC_CheckPredicate, 3, 96, 14, 0, // Skip to: 86948 -/* 83268 */ MCD_OPC_CheckField, 21, 1, 1, 89, 14, 0, // Skip to: 86948 -/* 83275 */ MCD_OPC_Decode, 199, 33, 172, 3, // Opcode: UQSUBv1i32 -/* 83280 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 83302 -/* 83285 */ MCD_OPC_CheckPredicate, 3, 74, 14, 0, // Skip to: 86948 -/* 83290 */ MCD_OPC_CheckField, 16, 6, 32, 67, 14, 0, // Skip to: 86948 -/* 83297 */ MCD_OPC_Decode, 147, 34, 211, 3, // Opcode: USQADDv1i32 -/* 83302 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 83324 -/* 83307 */ MCD_OPC_CheckPredicate, 3, 52, 14, 0, // Skip to: 86948 -/* 83312 */ MCD_OPC_CheckField, 16, 6, 33, 45, 14, 0, // Skip to: 86948 -/* 83319 */ MCD_OPC_Decode, 210, 33, 166, 2, // Opcode: UQXTNv1i32 -/* 83324 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 83346 -/* 83329 */ MCD_OPC_CheckPredicate, 3, 30, 14, 0, // Skip to: 86948 -/* 83334 */ MCD_OPC_CheckField, 21, 1, 1, 23, 14, 0, // Skip to: 86948 -/* 83341 */ MCD_OPC_Decode, 165, 33, 172, 3, // Opcode: UQSHLv1i32 -/* 83346 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 83368 -/* 83351 */ MCD_OPC_CheckPredicate, 3, 8, 14, 0, // Skip to: 86948 -/* 83356 */ MCD_OPC_CheckField, 21, 1, 1, 1, 14, 0, // Skip to: 86948 -/* 83363 */ MCD_OPC_Decode, 140, 33, 172, 3, // Opcode: UQRSHLv1i32 -/* 83368 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 83390 -/* 83373 */ MCD_OPC_CheckPredicate, 3, 242, 13, 0, // Skip to: 86948 -/* 83378 */ MCD_OPC_CheckField, 16, 6, 32, 235, 13, 0, // Skip to: 86948 -/* 83385 */ MCD_OPC_Decode, 149, 25, 167, 3, // Opcode: SQNEGv1i32 -/* 83390 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 83412 -/* 83395 */ MCD_OPC_CheckPredicate, 20, 220, 13, 0, // Skip to: 86948 -/* 83400 */ MCD_OPC_CheckField, 21, 1, 0, 213, 13, 0, // Skip to: 86948 -/* 83407 */ MCD_OPC_Decode, 161, 25, 242, 3, // Opcode: SQRDMLAHv1i32 -/* 83412 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 83434 -/* 83417 */ MCD_OPC_CheckPredicate, 20, 198, 13, 0, // Skip to: 86948 -/* 83422 */ MCD_OPC_CheckField, 21, 1, 0, 191, 13, 0, // Skip to: 86948 -/* 83429 */ MCD_OPC_Decode, 173, 25, 242, 3, // Opcode: SQRDMLSHv1i32 -/* 83434 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 83456 -/* 83439 */ MCD_OPC_CheckPredicate, 3, 176, 13, 0, // Skip to: 86948 -/* 83444 */ MCD_OPC_CheckField, 16, 6, 33, 169, 13, 0, // Skip to: 86948 -/* 83451 */ MCD_OPC_Decode, 206, 8, 167, 3, // Opcode: FCVTPUv1i32 -/* 83456 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 83478 -/* 83461 */ MCD_OPC_CheckPredicate, 3, 154, 13, 0, // Skip to: 86948 -/* 83466 */ MCD_OPC_CheckField, 21, 1, 1, 147, 13, 0, // Skip to: 86948 -/* 83473 */ MCD_OPC_Decode, 184, 25, 172, 3, // Opcode: SQRDMULHv1i32 -/* 83478 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 83500 -/* 83483 */ MCD_OPC_CheckPredicate, 3, 132, 13, 0, // Skip to: 86948 -/* 83488 */ MCD_OPC_CheckField, 16, 6, 33, 125, 13, 0, // Skip to: 86948 -/* 83495 */ MCD_OPC_Decode, 148, 9, 167, 3, // Opcode: FCVTZUv1i32 -/* 83500 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 83538 -/* 83505 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 83508 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 83523 -/* 83513 */ MCD_OPC_CheckPredicate, 3, 102, 13, 0, // Skip to: 86948 -/* 83518 */ MCD_OPC_Decode, 249, 6, 167, 3, // Opcode: FCMGEv1i32rz -/* 83523 */ MCD_OPC_FilterValue, 48, 92, 13, 0, // Skip to: 86948 -/* 83528 */ MCD_OPC_CheckPredicate, 3, 87, 13, 0, // Skip to: 86948 -/* 83533 */ MCD_OPC_Decode, 128, 10, 166, 2, // Opcode: FMINNMPv2i32p -/* 83538 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 83560 -/* 83543 */ MCD_OPC_CheckPredicate, 3, 72, 13, 0, // Skip to: 86948 -/* 83548 */ MCD_OPC_CheckField, 21, 1, 1, 65, 13, 0, // Skip to: 86948 -/* 83555 */ MCD_OPC_Decode, 129, 6, 172, 3, // Opcode: FABD32 -/* 83560 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 83598 -/* 83565 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 83568 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 83583 -/* 83573 */ MCD_OPC_CheckPredicate, 3, 42, 13, 0, // Skip to: 86948 -/* 83578 */ MCD_OPC_Decode, 172, 7, 167, 3, // Opcode: FCMLEv1i32rz -/* 83583 */ MCD_OPC_FilterValue, 33, 32, 13, 0, // Skip to: 86948 -/* 83588 */ MCD_OPC_CheckPredicate, 3, 27, 13, 0, // Skip to: 86948 -/* 83593 */ MCD_OPC_Decode, 177, 12, 167, 3, // Opcode: FRSQRTEv1i32 -/* 83598 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 83620 -/* 83603 */ MCD_OPC_CheckPredicate, 3, 12, 13, 0, // Skip to: 86948 -/* 83608 */ MCD_OPC_CheckField, 21, 1, 1, 5, 13, 0, // Skip to: 86948 -/* 83615 */ MCD_OPC_Decode, 134, 7, 172, 3, // Opcode: FCMGT32 -/* 83620 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 83642 -/* 83625 */ MCD_OPC_CheckPredicate, 3, 246, 12, 0, // Skip to: 86948 -/* 83630 */ MCD_OPC_CheckField, 21, 1, 1, 239, 12, 0, // Skip to: 86948 -/* 83637 */ MCD_OPC_Decode, 162, 6, 172, 3, // Opcode: FACGT32 -/* 83642 */ MCD_OPC_FilterValue, 62, 229, 12, 0, // Skip to: 86948 -/* 83647 */ MCD_OPC_CheckPredicate, 3, 224, 12, 0, // Skip to: 86948 -/* 83652 */ MCD_OPC_CheckField, 16, 6, 48, 217, 12, 0, // Skip to: 86948 -/* 83659 */ MCD_OPC_Decode, 154, 10, 166, 2, // Opcode: FMINPv2i32p -/* 83664 */ MCD_OPC_FilterValue, 11, 159, 2, 0, // Skip to: 84340 -/* 83669 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 83672 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 83694 -/* 83677 */ MCD_OPC_CheckPredicate, 3, 194, 12, 0, // Skip to: 86948 -/* 83682 */ MCD_OPC_CheckField, 21, 1, 1, 187, 12, 0, // Skip to: 86948 -/* 83689 */ MCD_OPC_Decode, 214, 32, 238, 1, // Opcode: UQADDv1i64 -/* 83694 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 83716 -/* 83699 */ MCD_OPC_CheckPredicate, 4, 172, 12, 0, // Skip to: 86948 -/* 83704 */ MCD_OPC_CheckField, 21, 1, 0, 165, 12, 0, // Skip to: 86948 -/* 83711 */ MCD_OPC_Decode, 128, 6, 193, 3, // Opcode: FABD16 -/* 83716 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 83738 -/* 83721 */ MCD_OPC_CheckPredicate, 4, 150, 12, 0, // Skip to: 86948 -/* 83726 */ MCD_OPC_CheckField, 21, 1, 0, 143, 12, 0, // Skip to: 86948 -/* 83733 */ MCD_OPC_Decode, 133, 7, 193, 3, // Opcode: FCMGT16 -/* 83738 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 83776 -/* 83743 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 83746 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 83761 -/* 83751 */ MCD_OPC_CheckPredicate, 4, 120, 12, 0, // Skip to: 86948 -/* 83756 */ MCD_OPC_Decode, 161, 6, 193, 3, // Opcode: FACGT16 -/* 83761 */ MCD_OPC_FilterValue, 1, 110, 12, 0, // Skip to: 86948 -/* 83766 */ MCD_OPC_CheckPredicate, 3, 105, 12, 0, // Skip to: 86948 -/* 83771 */ MCD_OPC_Decode, 200, 33, 238, 1, // Opcode: UQSUBv1i64 -/* 83776 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 83798 -/* 83781 */ MCD_OPC_CheckPredicate, 3, 90, 12, 0, // Skip to: 86948 -/* 83786 */ MCD_OPC_CheckField, 21, 1, 1, 83, 12, 0, // Skip to: 86948 -/* 83793 */ MCD_OPC_Decode, 231, 3, 238, 1, // Opcode: CMHIv1i64 -/* 83798 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 83820 -/* 83803 */ MCD_OPC_CheckPredicate, 3, 68, 12, 0, // Skip to: 86948 -/* 83808 */ MCD_OPC_CheckField, 16, 6, 32, 61, 12, 0, // Skip to: 86948 -/* 83815 */ MCD_OPC_Decode, 148, 34, 248, 1, // Opcode: USQADDv1i64 -/* 83820 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 83842 -/* 83825 */ MCD_OPC_CheckPredicate, 3, 46, 12, 0, // Skip to: 86948 -/* 83830 */ MCD_OPC_CheckField, 21, 1, 1, 39, 12, 0, // Skip to: 86948 -/* 83837 */ MCD_OPC_Decode, 239, 3, 238, 1, // Opcode: CMHSv1i64 -/* 83842 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 83864 -/* 83847 */ MCD_OPC_CheckPredicate, 3, 24, 12, 0, // Skip to: 86948 -/* 83852 */ MCD_OPC_CheckField, 21, 1, 1, 17, 12, 0, // Skip to: 86948 -/* 83859 */ MCD_OPC_Decode, 130, 34, 238, 1, // Opcode: USHLv1i64 -/* 83864 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 83886 -/* 83869 */ MCD_OPC_CheckPredicate, 3, 2, 12, 0, // Skip to: 86948 -/* 83874 */ MCD_OPC_CheckField, 21, 1, 1, 251, 11, 0, // Skip to: 86948 -/* 83881 */ MCD_OPC_Decode, 166, 33, 238, 1, // Opcode: UQSHLv1i64 -/* 83886 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 83908 -/* 83891 */ MCD_OPC_CheckPredicate, 3, 236, 11, 0, // Skip to: 86948 -/* 83896 */ MCD_OPC_CheckField, 21, 1, 1, 229, 11, 0, // Skip to: 86948 -/* 83903 */ MCD_OPC_Decode, 226, 33, 238, 1, // Opcode: URSHLv1i64 -/* 83908 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 83930 -/* 83913 */ MCD_OPC_CheckPredicate, 3, 214, 11, 0, // Skip to: 86948 -/* 83918 */ MCD_OPC_CheckField, 21, 1, 1, 207, 11, 0, // Skip to: 86948 -/* 83925 */ MCD_OPC_Decode, 141, 33, 238, 1, // Opcode: UQRSHLv1i64 -/* 83930 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 83952 -/* 83935 */ MCD_OPC_CheckPredicate, 3, 192, 11, 0, // Skip to: 86948 -/* 83940 */ MCD_OPC_CheckField, 16, 6, 32, 185, 11, 0, // Skip to: 86948 -/* 83947 */ MCD_OPC_Decode, 150, 25, 239, 1, // Opcode: SQNEGv1i64 -/* 83952 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 83974 -/* 83957 */ MCD_OPC_CheckPredicate, 3, 170, 11, 0, // Skip to: 86948 -/* 83962 */ MCD_OPC_CheckField, 21, 1, 1, 163, 11, 0, // Skip to: 86948 -/* 83969 */ MCD_OPC_Decode, 128, 30, 238, 1, // Opcode: SUBv1i64 -/* 83974 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 83996 -/* 83979 */ MCD_OPC_CheckPredicate, 3, 148, 11, 0, // Skip to: 86948 -/* 83984 */ MCD_OPC_CheckField, 16, 6, 32, 141, 11, 0, // Skip to: 86948 -/* 83991 */ MCD_OPC_Decode, 201, 3, 239, 1, // Opcode: CMGEv1i64rz -/* 83996 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 84018 -/* 84001 */ MCD_OPC_CheckPredicate, 3, 126, 11, 0, // Skip to: 86948 -/* 84006 */ MCD_OPC_CheckField, 21, 1, 1, 119, 11, 0, // Skip to: 86948 -/* 84013 */ MCD_OPC_Decode, 184, 3, 238, 1, // Opcode: CMEQv1i64 -/* 84018 */ MCD_OPC_FilterValue, 38, 17, 0, 0, // Skip to: 84040 -/* 84023 */ MCD_OPC_CheckPredicate, 3, 104, 11, 0, // Skip to: 86948 -/* 84028 */ MCD_OPC_CheckField, 16, 6, 32, 97, 11, 0, // Skip to: 86948 -/* 84035 */ MCD_OPC_Decode, 247, 3, 239, 1, // Opcode: CMLEv1i64rz -/* 84040 */ MCD_OPC_FilterValue, 42, 33, 0, 0, // Skip to: 84078 -/* 84045 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 84048 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 84063 -/* 84053 */ MCD_OPC_CheckPredicate, 3, 74, 11, 0, // Skip to: 86948 -/* 84058 */ MCD_OPC_Decode, 207, 8, 239, 1, // Opcode: FCVTPUv1i64 -/* 84063 */ MCD_OPC_FilterValue, 57, 64, 11, 0, // Skip to: 86948 -/* 84068 */ MCD_OPC_CheckPredicate, 4, 59, 11, 0, // Skip to: 86948 -/* 84073 */ MCD_OPC_Decode, 205, 8, 188, 3, // Opcode: FCVTPUv1f16 -/* 84078 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 84131 -/* 84083 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 84086 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 84101 -/* 84091 */ MCD_OPC_CheckPredicate, 3, 36, 11, 0, // Skip to: 86948 -/* 84096 */ MCD_OPC_Decode, 180, 20, 239, 1, // Opcode: NEGv1i64 -/* 84101 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 84116 -/* 84106 */ MCD_OPC_CheckPredicate, 3, 21, 11, 0, // Skip to: 86948 -/* 84111 */ MCD_OPC_Decode, 149, 9, 239, 1, // Opcode: FCVTZUv1i64 -/* 84116 */ MCD_OPC_FilterValue, 57, 11, 11, 0, // Skip to: 86948 -/* 84121 */ MCD_OPC_CheckPredicate, 4, 6, 11, 0, // Skip to: 86948 -/* 84126 */ MCD_OPC_Decode, 147, 9, 188, 3, // Opcode: FCVTZUv1f16 -/* 84131 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 84184 -/* 84136 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 84139 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 84154 -/* 84144 */ MCD_OPC_CheckPredicate, 3, 239, 10, 0, // Skip to: 86948 -/* 84149 */ MCD_OPC_Decode, 250, 6, 239, 1, // Opcode: FCMGEv1i64rz -/* 84154 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 84169 -/* 84159 */ MCD_OPC_CheckPredicate, 3, 224, 10, 0, // Skip to: 86948 -/* 84164 */ MCD_OPC_Decode, 129, 10, 244, 1, // Opcode: FMINNMPv2i64p -/* 84169 */ MCD_OPC_FilterValue, 56, 214, 10, 0, // Skip to: 86948 -/* 84174 */ MCD_OPC_CheckPredicate, 4, 209, 10, 0, // Skip to: 86948 -/* 84179 */ MCD_OPC_Decode, 248, 6, 188, 3, // Opcode: FCMGEv1i16rz -/* 84184 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 84206 -/* 84189 */ MCD_OPC_CheckPredicate, 3, 194, 10, 0, // Skip to: 86948 -/* 84194 */ MCD_OPC_CheckField, 21, 1, 1, 187, 10, 0, // Skip to: 86948 -/* 84201 */ MCD_OPC_Decode, 130, 6, 238, 1, // Opcode: FABD64 -/* 84206 */ MCD_OPC_FilterValue, 54, 63, 0, 0, // Skip to: 84274 -/* 84211 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 84214 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 84229 -/* 84219 */ MCD_OPC_CheckPredicate, 3, 164, 10, 0, // Skip to: 86948 -/* 84224 */ MCD_OPC_Decode, 173, 7, 239, 1, // Opcode: FCMLEv1i64rz -/* 84229 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 84244 -/* 84234 */ MCD_OPC_CheckPredicate, 3, 149, 10, 0, // Skip to: 86948 -/* 84239 */ MCD_OPC_Decode, 178, 12, 239, 1, // Opcode: FRSQRTEv1i64 -/* 84244 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 84259 -/* 84249 */ MCD_OPC_CheckPredicate, 4, 134, 10, 0, // Skip to: 86948 -/* 84254 */ MCD_OPC_Decode, 171, 7, 188, 3, // Opcode: FCMLEv1i16rz -/* 84259 */ MCD_OPC_FilterValue, 57, 124, 10, 0, // Skip to: 86948 -/* 84264 */ MCD_OPC_CheckPredicate, 4, 119, 10, 0, // Skip to: 86948 -/* 84269 */ MCD_OPC_Decode, 176, 12, 188, 3, // Opcode: FRSQRTEv1f16 -/* 84274 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 84296 -/* 84279 */ MCD_OPC_CheckPredicate, 3, 104, 10, 0, // Skip to: 86948 -/* 84284 */ MCD_OPC_CheckField, 21, 1, 1, 97, 10, 0, // Skip to: 86948 -/* 84291 */ MCD_OPC_Decode, 135, 7, 238, 1, // Opcode: FCMGT64 -/* 84296 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 84318 -/* 84301 */ MCD_OPC_CheckPredicate, 3, 82, 10, 0, // Skip to: 86948 -/* 84306 */ MCD_OPC_CheckField, 21, 1, 1, 75, 10, 0, // Skip to: 86948 -/* 84313 */ MCD_OPC_Decode, 163, 6, 238, 1, // Opcode: FACGT64 -/* 84318 */ MCD_OPC_FilterValue, 62, 65, 10, 0, // Skip to: 86948 -/* 84323 */ MCD_OPC_CheckPredicate, 3, 60, 10, 0, // Skip to: 86948 -/* 84328 */ MCD_OPC_CheckField, 16, 6, 48, 53, 10, 0, // Skip to: 86948 -/* 84335 */ MCD_OPC_Decode, 155, 10, 244, 1, // Opcode: FMINPv2i64p -/* 84340 */ MCD_OPC_FilterValue, 12, 98, 2, 0, // Skip to: 84955 -/* 84345 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 84348 */ MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 84437 -/* 84353 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 84356 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 84415 -/* 84361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 84364 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84393 -/* 84369 */ MCD_OPC_CheckPredicate, 3, 14, 10, 0, // Skip to: 86948 -/* 84374 */ MCD_OPC_CheckField, 19, 1, 1, 7, 10, 0, // Skip to: 86948 -/* 84381 */ MCD_OPC_CheckField, 10, 2, 1, 0, 10, 0, // Skip to: 86948 -/* 84388 */ MCD_OPC_Decode, 223, 25, 226, 3, // Opcode: SQSHLUb -/* 84393 */ MCD_OPC_FilterValue, 1, 246, 9, 0, // Skip to: 86948 -/* 84398 */ MCD_OPC_CheckPredicate, 3, 241, 9, 0, // Skip to: 86948 -/* 84403 */ MCD_OPC_CheckField, 10, 2, 1, 234, 9, 0, // Skip to: 86948 -/* 84410 */ MCD_OPC_Decode, 225, 25, 227, 3, // Opcode: SQSHLUh -/* 84415 */ MCD_OPC_FilterValue, 1, 224, 9, 0, // Skip to: 86948 -/* 84420 */ MCD_OPC_CheckPredicate, 3, 219, 9, 0, // Skip to: 86948 -/* 84425 */ MCD_OPC_CheckField, 10, 2, 1, 212, 9, 0, // Skip to: 86948 -/* 84432 */ MCD_OPC_Decode, 226, 25, 228, 3, // Opcode: SQSHLUs -/* 84437 */ MCD_OPC_FilterValue, 7, 84, 0, 0, // Skip to: 84526 -/* 84442 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 84445 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 84504 -/* 84450 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 84453 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84482 -/* 84458 */ MCD_OPC_CheckPredicate, 3, 181, 9, 0, // Skip to: 86948 -/* 84463 */ MCD_OPC_CheckField, 19, 1, 1, 174, 9, 0, // Skip to: 86948 -/* 84470 */ MCD_OPC_CheckField, 10, 2, 1, 167, 9, 0, // Skip to: 86948 -/* 84477 */ MCD_OPC_Decode, 158, 33, 226, 3, // Opcode: UQSHLb -/* 84482 */ MCD_OPC_FilterValue, 1, 157, 9, 0, // Skip to: 86948 -/* 84487 */ MCD_OPC_CheckPredicate, 3, 152, 9, 0, // Skip to: 86948 -/* 84492 */ MCD_OPC_CheckField, 10, 2, 1, 145, 9, 0, // Skip to: 86948 -/* 84499 */ MCD_OPC_Decode, 160, 33, 227, 3, // Opcode: UQSHLh -/* 84504 */ MCD_OPC_FilterValue, 1, 135, 9, 0, // Skip to: 86948 -/* 84509 */ MCD_OPC_CheckPredicate, 3, 130, 9, 0, // Skip to: 86948 -/* 84514 */ MCD_OPC_CheckField, 10, 2, 1, 123, 9, 0, // Skip to: 86948 -/* 84521 */ MCD_OPC_Decode, 161, 33, 228, 3, // Opcode: UQSHLs -/* 84526 */ MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 84670 -/* 84531 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 84534 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 84602 -/* 84539 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 84542 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84587 -/* 84547 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 84550 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84572 -/* 84555 */ MCD_OPC_CheckPredicate, 3, 84, 9, 0, // Skip to: 86948 -/* 84560 */ MCD_OPC_CheckField, 19, 1, 1, 77, 9, 0, // Skip to: 86948 -/* 84567 */ MCD_OPC_Decode, 137, 26, 230, 3, // Opcode: SQSHRUNb -/* 84572 */ MCD_OPC_FilterValue, 1, 67, 9, 0, // Skip to: 86948 -/* 84577 */ MCD_OPC_CheckPredicate, 3, 62, 9, 0, // Skip to: 86948 -/* 84582 */ MCD_OPC_Decode, 138, 26, 231, 3, // Opcode: SQSHRUNh -/* 84587 */ MCD_OPC_FilterValue, 1, 52, 9, 0, // Skip to: 86948 -/* 84592 */ MCD_OPC_CheckPredicate, 3, 47, 9, 0, // Skip to: 86948 -/* 84597 */ MCD_OPC_Decode, 139, 26, 232, 3, // Opcode: SQSHRUNs -/* 84602 */ MCD_OPC_FilterValue, 3, 37, 9, 0, // Skip to: 86948 -/* 84607 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 84610 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84655 -/* 84615 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 84618 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84640 -/* 84623 */ MCD_OPC_CheckPredicate, 3, 16, 9, 0, // Skip to: 86948 -/* 84628 */ MCD_OPC_CheckField, 19, 1, 1, 9, 9, 0, // Skip to: 86948 -/* 84635 */ MCD_OPC_Decode, 214, 25, 230, 3, // Opcode: SQRSHRUNb -/* 84640 */ MCD_OPC_FilterValue, 1, 255, 8, 0, // Skip to: 86948 -/* 84645 */ MCD_OPC_CheckPredicate, 3, 250, 8, 0, // Skip to: 86948 -/* 84650 */ MCD_OPC_Decode, 215, 25, 231, 3, // Opcode: SQRSHRUNh -/* 84655 */ MCD_OPC_FilterValue, 1, 240, 8, 0, // Skip to: 86948 -/* 84660 */ MCD_OPC_CheckPredicate, 3, 235, 8, 0, // Skip to: 86948 -/* 84665 */ MCD_OPC_Decode, 216, 25, 232, 3, // Opcode: SQRSHRUNs -/* 84670 */ MCD_OPC_FilterValue, 9, 162, 0, 0, // Skip to: 84837 -/* 84675 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 84678 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 84693 -/* 84683 */ MCD_OPC_CheckPredicate, 4, 212, 8, 0, // Skip to: 86948 -/* 84688 */ MCD_OPC_Decode, 254, 10, 229, 3, // Opcode: FMULXv1i16_indexed -/* 84693 */ MCD_OPC_FilterValue, 1, 202, 8, 0, // Skip to: 86948 -/* 84698 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 84701 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 84769 -/* 84706 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 84709 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84754 -/* 84714 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 84717 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84739 -/* 84722 */ MCD_OPC_CheckPredicate, 3, 173, 8, 0, // Skip to: 86948 -/* 84727 */ MCD_OPC_CheckField, 19, 1, 1, 166, 8, 0, // Skip to: 86948 -/* 84734 */ MCD_OPC_Decode, 180, 33, 230, 3, // Opcode: UQSHRNb -/* 84739 */ MCD_OPC_FilterValue, 1, 156, 8, 0, // Skip to: 86948 -/* 84744 */ MCD_OPC_CheckPredicate, 3, 151, 8, 0, // Skip to: 86948 -/* 84749 */ MCD_OPC_Decode, 181, 33, 231, 3, // Opcode: UQSHRNh -/* 84754 */ MCD_OPC_FilterValue, 1, 141, 8, 0, // Skip to: 86948 -/* 84759 */ MCD_OPC_CheckPredicate, 3, 136, 8, 0, // Skip to: 86948 -/* 84764 */ MCD_OPC_Decode, 182, 33, 232, 3, // Opcode: UQSHRNs -/* 84769 */ MCD_OPC_FilterValue, 1, 126, 8, 0, // Skip to: 86948 -/* 84774 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 84777 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84822 -/* 84782 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 84785 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84807 -/* 84790 */ MCD_OPC_CheckPredicate, 3, 105, 8, 0, // Skip to: 86948 -/* 84795 */ MCD_OPC_CheckField, 19, 1, 1, 98, 8, 0, // Skip to: 86948 -/* 84802 */ MCD_OPC_Decode, 149, 33, 230, 3, // Opcode: UQRSHRNb -/* 84807 */ MCD_OPC_FilterValue, 1, 88, 8, 0, // Skip to: 86948 -/* 84812 */ MCD_OPC_CheckPredicate, 3, 83, 8, 0, // Skip to: 86948 -/* 84817 */ MCD_OPC_Decode, 150, 33, 231, 3, // Opcode: UQRSHRNh -/* 84822 */ MCD_OPC_FilterValue, 1, 73, 8, 0, // Skip to: 86948 -/* 84827 */ MCD_OPC_CheckPredicate, 3, 68, 8, 0, // Skip to: 86948 -/* 84832 */ MCD_OPC_Decode, 151, 33, 232, 3, // Opcode: UQRSHRNs -/* 84837 */ MCD_OPC_FilterValue, 14, 54, 0, 0, // Skip to: 84896 -/* 84842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 84845 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84874 -/* 84850 */ MCD_OPC_CheckPredicate, 4, 45, 8, 0, // Skip to: 86948 -/* 84855 */ MCD_OPC_CheckField, 20, 1, 1, 38, 8, 0, // Skip to: 86948 -/* 84862 */ MCD_OPC_CheckField, 10, 2, 1, 31, 8, 0, // Skip to: 86948 -/* 84869 */ MCD_OPC_Decode, 191, 31, 237, 3, // Opcode: UCVTFh -/* 84874 */ MCD_OPC_FilterValue, 1, 21, 8, 0, // Skip to: 86948 -/* 84879 */ MCD_OPC_CheckPredicate, 3, 16, 8, 0, // Skip to: 86948 -/* 84884 */ MCD_OPC_CheckField, 10, 2, 1, 9, 8, 0, // Skip to: 86948 -/* 84891 */ MCD_OPC_Decode, 192, 31, 238, 3, // Opcode: UCVTFs -/* 84896 */ MCD_OPC_FilterValue, 15, 255, 7, 0, // Skip to: 86948 -/* 84901 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 84904 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84933 -/* 84909 */ MCD_OPC_CheckPredicate, 4, 242, 7, 0, // Skip to: 86948 -/* 84914 */ MCD_OPC_CheckField, 20, 1, 1, 235, 7, 0, // Skip to: 86948 -/* 84921 */ MCD_OPC_CheckField, 10, 2, 3, 228, 7, 0, // Skip to: 86948 -/* 84928 */ MCD_OPC_Decode, 145, 9, 237, 3, // Opcode: FCVTZUh -/* 84933 */ MCD_OPC_FilterValue, 1, 218, 7, 0, // Skip to: 86948 -/* 84938 */ MCD_OPC_CheckPredicate, 3, 213, 7, 0, // Skip to: 86948 -/* 84943 */ MCD_OPC_CheckField, 10, 2, 3, 206, 7, 0, // Skip to: 86948 -/* 84950 */ MCD_OPC_Decode, 146, 9, 238, 3, // Opcode: FCVTZUs -/* 84955 */ MCD_OPC_FilterValue, 13, 12, 1, 0, // Skip to: 85228 -/* 84960 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 84963 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84985 -/* 84968 */ MCD_OPC_CheckPredicate, 3, 183, 7, 0, // Skip to: 86948 -/* 84973 */ MCD_OPC_CheckField, 10, 2, 1, 176, 7, 0, // Skip to: 86948 -/* 84980 */ MCD_OPC_Decode, 137, 34, 218, 3, // Opcode: USHRd -/* 84985 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 85007 -/* 84990 */ MCD_OPC_CheckPredicate, 3, 161, 7, 0, // Skip to: 86948 -/* 84995 */ MCD_OPC_CheckField, 10, 2, 1, 154, 7, 0, // Skip to: 86948 -/* 85002 */ MCD_OPC_Decode, 156, 34, 220, 3, // Opcode: USRAd -/* 85007 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 85029 -/* 85012 */ MCD_OPC_CheckPredicate, 3, 139, 7, 0, // Skip to: 86948 -/* 85017 */ MCD_OPC_CheckField, 10, 2, 1, 132, 7, 0, // Skip to: 86948 -/* 85024 */ MCD_OPC_Decode, 233, 33, 218, 3, // Opcode: URSHRd -/* 85029 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 85051 -/* 85034 */ MCD_OPC_CheckPredicate, 3, 117, 7, 0, // Skip to: 86948 -/* 85039 */ MCD_OPC_CheckField, 10, 2, 1, 110, 7, 0, // Skip to: 86948 -/* 85046 */ MCD_OPC_Decode, 243, 33, 220, 3, // Opcode: URSRAd -/* 85051 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 85073 -/* 85056 */ MCD_OPC_CheckPredicate, 3, 95, 7, 0, // Skip to: 86948 -/* 85061 */ MCD_OPC_CheckField, 10, 2, 1, 88, 7, 0, // Skip to: 86948 -/* 85068 */ MCD_OPC_Decode, 189, 26, 220, 3, // Opcode: SRId -/* 85073 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 85095 -/* 85078 */ MCD_OPC_CheckPredicate, 3, 73, 7, 0, // Skip to: 86948 -/* 85083 */ MCD_OPC_CheckField, 10, 2, 1, 66, 7, 0, // Skip to: 86948 -/* 85090 */ MCD_OPC_Decode, 159, 23, 243, 3, // Opcode: SLId -/* 85095 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 85117 -/* 85100 */ MCD_OPC_CheckPredicate, 3, 51, 7, 0, // Skip to: 86948 -/* 85105 */ MCD_OPC_CheckField, 10, 2, 1, 44, 7, 0, // Skip to: 86948 -/* 85112 */ MCD_OPC_Decode, 224, 25, 225, 3, // Opcode: SQSHLUd -/* 85117 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 85139 -/* 85122 */ MCD_OPC_CheckPredicate, 3, 29, 7, 0, // Skip to: 86948 -/* 85127 */ MCD_OPC_CheckField, 10, 2, 1, 22, 7, 0, // Skip to: 86948 -/* 85134 */ MCD_OPC_Decode, 159, 33, 225, 3, // Opcode: UQSHLd -/* 85139 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 85161 -/* 85144 */ MCD_OPC_CheckPredicate, 7, 7, 7, 0, // Skip to: 86948 -/* 85149 */ MCD_OPC_CheckField, 10, 1, 0, 0, 7, 0, // Skip to: 86948 -/* 85156 */ MCD_OPC_Decode, 158, 25, 219, 3, // Opcode: SQRDMLAHi16_indexed -/* 85161 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 85183 -/* 85166 */ MCD_OPC_CheckPredicate, 3, 241, 6, 0, // Skip to: 86948 -/* 85171 */ MCD_OPC_CheckField, 10, 2, 1, 234, 6, 0, // Skip to: 86948 -/* 85178 */ MCD_OPC_Decode, 190, 31, 218, 3, // Opcode: UCVTFd -/* 85183 */ MCD_OPC_FilterValue, 15, 224, 6, 0, // Skip to: 86948 -/* 85188 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 85191 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 85206 -/* 85196 */ MCD_OPC_CheckPredicate, 7, 211, 6, 0, // Skip to: 86948 -/* 85201 */ MCD_OPC_Decode, 170, 25, 219, 3, // Opcode: SQRDMLSHi16_indexed -/* 85206 */ MCD_OPC_FilterValue, 1, 201, 6, 0, // Skip to: 86948 -/* 85211 */ MCD_OPC_CheckPredicate, 3, 196, 6, 0, // Skip to: 86948 -/* 85216 */ MCD_OPC_CheckField, 11, 1, 1, 189, 6, 0, // Skip to: 86948 -/* 85223 */ MCD_OPC_Decode, 144, 9, 218, 3, // Opcode: FCVTZUd -/* 85228 */ MCD_OPC_FilterValue, 14, 69, 0, 0, // Skip to: 85302 -/* 85233 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 85236 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 85258 -/* 85241 */ MCD_OPC_CheckPredicate, 3, 166, 6, 0, // Skip to: 86948 -/* 85246 */ MCD_OPC_CheckField, 10, 1, 0, 159, 6, 0, // Skip to: 86948 -/* 85253 */ MCD_OPC_Decode, 255, 10, 233, 3, // Opcode: FMULXv1i32_indexed -/* 85258 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 85280 -/* 85263 */ MCD_OPC_CheckPredicate, 7, 144, 6, 0, // Skip to: 86948 -/* 85268 */ MCD_OPC_CheckField, 10, 1, 0, 137, 6, 0, // Skip to: 86948 -/* 85275 */ MCD_OPC_Decode, 159, 25, 221, 3, // Opcode: SQRDMLAHi32_indexed -/* 85280 */ MCD_OPC_FilterValue, 15, 127, 6, 0, // Skip to: 86948 -/* 85285 */ MCD_OPC_CheckPredicate, 7, 122, 6, 0, // Skip to: 86948 -/* 85290 */ MCD_OPC_CheckField, 10, 1, 0, 115, 6, 0, // Skip to: 86948 -/* 85297 */ MCD_OPC_Decode, 171, 25, 221, 3, // Opcode: SQRDMLSHi32_indexed -/* 85302 */ MCD_OPC_FilterValue, 15, 105, 6, 0, // Skip to: 86948 -/* 85307 */ MCD_OPC_CheckPredicate, 3, 100, 6, 0, // Skip to: 86948 -/* 85312 */ MCD_OPC_CheckField, 21, 1, 0, 93, 6, 0, // Skip to: 86948 -/* 85319 */ MCD_OPC_CheckField, 12, 4, 9, 86, 6, 0, // Skip to: 86948 -/* 85326 */ MCD_OPC_CheckField, 10, 1, 0, 79, 6, 0, // Skip to: 86948 -/* 85333 */ MCD_OPC_Decode, 128, 11, 234, 3, // Opcode: FMULXv1i64_indexed -/* 85338 */ MCD_OPC_FilterValue, 4, 121, 4, 0, // Skip to: 86488 -/* 85343 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 85346 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 85356 -/* 85351 */ MCD_OPC_Decode, 245, 17, 244, 3, // Opcode: LDRQl -/* 85356 */ MCD_OPC_FilterValue, 2, 51, 6, 0, // Skip to: 86948 -/* 85361 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 85364 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 85379 -/* 85369 */ MCD_OPC_CheckPredicate, 16, 38, 6, 0, // Skip to: 86948 -/* 85374 */ MCD_OPC_Decode, 189, 22, 245, 3, // Opcode: SCVTFSXSri -/* 85379 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 85394 -/* 85384 */ MCD_OPC_CheckPredicate, 16, 23, 6, 0, // Skip to: 86948 -/* 85389 */ MCD_OPC_Decode, 176, 31, 245, 3, // Opcode: UCVTFSXSri -/* 85394 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 85409 -/* 85399 */ MCD_OPC_CheckPredicate, 16, 8, 6, 0, // Skip to: 86948 -/* 85404 */ MCD_OPC_Decode, 223, 8, 246, 3, // Opcode: FCVTZSSXSri -/* 85409 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 85424 -/* 85414 */ MCD_OPC_CheckPredicate, 16, 249, 5, 0, // Skip to: 86948 -/* 85419 */ MCD_OPC_Decode, 130, 9, 246, 3, // Opcode: FCVTZUSXSri -/* 85424 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 85446 -/* 85429 */ MCD_OPC_CheckPredicate, 16, 234, 5, 0, // Skip to: 86948 -/* 85434 */ MCD_OPC_CheckField, 10, 6, 0, 227, 5, 0, // Skip to: 86948 -/* 85441 */ MCD_OPC_Decode, 158, 8, 247, 3, // Opcode: FCVTNSUXSr -/* 85446 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 85468 -/* 85451 */ MCD_OPC_CheckPredicate, 16, 212, 5, 0, // Skip to: 86948 -/* 85456 */ MCD_OPC_CheckField, 10, 6, 0, 205, 5, 0, // Skip to: 86948 -/* 85463 */ MCD_OPC_Decode, 172, 8, 247, 3, // Opcode: FCVTNUUXSr -/* 85468 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 85490 -/* 85473 */ MCD_OPC_CheckPredicate, 16, 190, 5, 0, // Skip to: 86948 -/* 85478 */ MCD_OPC_CheckField, 10, 6, 0, 183, 5, 0, // Skip to: 86948 -/* 85485 */ MCD_OPC_Decode, 195, 22, 248, 3, // Opcode: SCVTFUXSri -/* 85490 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 85512 -/* 85495 */ MCD_OPC_CheckPredicate, 16, 168, 5, 0, // Skip to: 86948 -/* 85500 */ MCD_OPC_CheckField, 10, 6, 0, 161, 5, 0, // Skip to: 86948 -/* 85507 */ MCD_OPC_Decode, 182, 31, 248, 3, // Opcode: UCVTFUXSri -/* 85512 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 85534 -/* 85517 */ MCD_OPC_CheckPredicate, 16, 146, 5, 0, // Skip to: 86948 -/* 85522 */ MCD_OPC_CheckField, 10, 6, 0, 139, 5, 0, // Skip to: 86948 -/* 85529 */ MCD_OPC_Decode, 222, 7, 247, 3, // Opcode: FCVTASUXSr -/* 85534 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 85556 -/* 85539 */ MCD_OPC_CheckPredicate, 16, 124, 5, 0, // Skip to: 86948 -/* 85544 */ MCD_OPC_CheckField, 10, 6, 0, 117, 5, 0, // Skip to: 86948 -/* 85551 */ MCD_OPC_Decode, 236, 7, 247, 3, // Opcode: FCVTAUUXSr -/* 85556 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 85578 -/* 85561 */ MCD_OPC_CheckPredicate, 16, 102, 5, 0, // Skip to: 86948 -/* 85566 */ MCD_OPC_CheckField, 10, 6, 0, 95, 5, 0, // Skip to: 86948 -/* 85573 */ MCD_OPC_Decode, 190, 8, 247, 3, // Opcode: FCVTPSUXSr -/* 85578 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 85600 -/* 85583 */ MCD_OPC_CheckPredicate, 16, 80, 5, 0, // Skip to: 86948 -/* 85588 */ MCD_OPC_CheckField, 10, 6, 0, 73, 5, 0, // Skip to: 86948 -/* 85595 */ MCD_OPC_Decode, 204, 8, 247, 3, // Opcode: FCVTPUUXSr -/* 85600 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 85622 -/* 85605 */ MCD_OPC_CheckPredicate, 16, 58, 5, 0, // Skip to: 86948 -/* 85610 */ MCD_OPC_CheckField, 10, 6, 0, 51, 5, 0, // Skip to: 86948 -/* 85617 */ MCD_OPC_Decode, 130, 8, 247, 3, // Opcode: FCVTMSUXSr -/* 85622 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 85644 -/* 85627 */ MCD_OPC_CheckPredicate, 16, 36, 5, 0, // Skip to: 86948 -/* 85632 */ MCD_OPC_CheckField, 10, 6, 0, 29, 5, 0, // Skip to: 86948 -/* 85639 */ MCD_OPC_Decode, 144, 8, 247, 3, // Opcode: FCVTMUUXSr -/* 85644 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 85666 -/* 85649 */ MCD_OPC_CheckPredicate, 16, 14, 5, 0, // Skip to: 86948 -/* 85654 */ MCD_OPC_CheckField, 10, 6, 0, 7, 5, 0, // Skip to: 86948 -/* 85661 */ MCD_OPC_Decode, 229, 8, 247, 3, // Opcode: FCVTZSUXSr -/* 85666 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 85688 -/* 85671 */ MCD_OPC_CheckPredicate, 16, 248, 4, 0, // Skip to: 86948 -/* 85676 */ MCD_OPC_CheckField, 10, 6, 0, 241, 4, 0, // Skip to: 86948 -/* 85683 */ MCD_OPC_Decode, 136, 9, 247, 3, // Opcode: FCVTZUUXSr -/* 85688 */ MCD_OPC_FilterValue, 66, 10, 0, 0, // Skip to: 85703 -/* 85693 */ MCD_OPC_CheckPredicate, 16, 226, 4, 0, // Skip to: 86948 -/* 85698 */ MCD_OPC_Decode, 187, 22, 249, 3, // Opcode: SCVTFSXDri -/* 85703 */ MCD_OPC_FilterValue, 67, 10, 0, 0, // Skip to: 85718 -/* 85708 */ MCD_OPC_CheckPredicate, 16, 211, 4, 0, // Skip to: 86948 -/* 85713 */ MCD_OPC_Decode, 174, 31, 249, 3, // Opcode: UCVTFSXDri -/* 85718 */ MCD_OPC_FilterValue, 88, 10, 0, 0, // Skip to: 85733 -/* 85723 */ MCD_OPC_CheckPredicate, 16, 196, 4, 0, // Skip to: 86948 -/* 85728 */ MCD_OPC_Decode, 221, 8, 250, 3, // Opcode: FCVTZSSXDri -/* 85733 */ MCD_OPC_FilterValue, 89, 10, 0, 0, // Skip to: 85748 -/* 85738 */ MCD_OPC_CheckPredicate, 16, 181, 4, 0, // Skip to: 86948 -/* 85743 */ MCD_OPC_Decode, 128, 9, 250, 3, // Opcode: FCVTZUSXDri -/* 85748 */ MCD_OPC_FilterValue, 96, 17, 0, 0, // Skip to: 85770 -/* 85753 */ MCD_OPC_CheckPredicate, 16, 166, 4, 0, // Skip to: 86948 -/* 85758 */ MCD_OPC_CheckField, 10, 6, 0, 159, 4, 0, // Skip to: 86948 -/* 85765 */ MCD_OPC_Decode, 156, 8, 251, 3, // Opcode: FCVTNSUXDr -/* 85770 */ MCD_OPC_FilterValue, 97, 17, 0, 0, // Skip to: 85792 -/* 85775 */ MCD_OPC_CheckPredicate, 16, 144, 4, 0, // Skip to: 86948 -/* 85780 */ MCD_OPC_CheckField, 10, 6, 0, 137, 4, 0, // Skip to: 86948 -/* 85787 */ MCD_OPC_Decode, 170, 8, 251, 3, // Opcode: FCVTNUUXDr -/* 85792 */ MCD_OPC_FilterValue, 98, 17, 0, 0, // Skip to: 85814 -/* 85797 */ MCD_OPC_CheckPredicate, 16, 122, 4, 0, // Skip to: 86948 -/* 85802 */ MCD_OPC_CheckField, 10, 6, 0, 115, 4, 0, // Skip to: 86948 -/* 85809 */ MCD_OPC_Decode, 193, 22, 252, 3, // Opcode: SCVTFUXDri -/* 85814 */ MCD_OPC_FilterValue, 99, 17, 0, 0, // Skip to: 85836 -/* 85819 */ MCD_OPC_CheckPredicate, 16, 100, 4, 0, // Skip to: 86948 -/* 85824 */ MCD_OPC_CheckField, 10, 6, 0, 93, 4, 0, // Skip to: 86948 -/* 85831 */ MCD_OPC_Decode, 180, 31, 252, 3, // Opcode: UCVTFUXDri -/* 85836 */ MCD_OPC_FilterValue, 100, 17, 0, 0, // Skip to: 85858 -/* 85841 */ MCD_OPC_CheckPredicate, 16, 78, 4, 0, // Skip to: 86948 -/* 85846 */ MCD_OPC_CheckField, 10, 6, 0, 71, 4, 0, // Skip to: 86948 -/* 85853 */ MCD_OPC_Decode, 220, 7, 251, 3, // Opcode: FCVTASUXDr -/* 85858 */ MCD_OPC_FilterValue, 101, 17, 0, 0, // Skip to: 85880 -/* 85863 */ MCD_OPC_CheckPredicate, 16, 56, 4, 0, // Skip to: 86948 -/* 85868 */ MCD_OPC_CheckField, 10, 6, 0, 49, 4, 0, // Skip to: 86948 -/* 85875 */ MCD_OPC_Decode, 234, 7, 251, 3, // Opcode: FCVTAUUXDr -/* 85880 */ MCD_OPC_FilterValue, 102, 17, 0, 0, // Skip to: 85902 -/* 85885 */ MCD_OPC_CheckPredicate, 16, 34, 4, 0, // Skip to: 86948 -/* 85890 */ MCD_OPC_CheckField, 10, 6, 0, 27, 4, 0, // Skip to: 86948 -/* 85897 */ MCD_OPC_Decode, 217, 10, 251, 3, // Opcode: FMOVDXr -/* 85902 */ MCD_OPC_FilterValue, 103, 17, 0, 0, // Skip to: 85924 -/* 85907 */ MCD_OPC_CheckPredicate, 16, 12, 4, 0, // Skip to: 86948 -/* 85912 */ MCD_OPC_CheckField, 10, 6, 0, 5, 4, 0, // Skip to: 86948 -/* 85919 */ MCD_OPC_Decode, 232, 10, 252, 3, // Opcode: FMOVXDr -/* 85924 */ MCD_OPC_FilterValue, 104, 17, 0, 0, // Skip to: 85946 -/* 85929 */ MCD_OPC_CheckPredicate, 16, 246, 3, 0, // Skip to: 86948 -/* 85934 */ MCD_OPC_CheckField, 10, 6, 0, 239, 3, 0, // Skip to: 86948 -/* 85941 */ MCD_OPC_Decode, 188, 8, 251, 3, // Opcode: FCVTPSUXDr -/* 85946 */ MCD_OPC_FilterValue, 105, 17, 0, 0, // Skip to: 85968 -/* 85951 */ MCD_OPC_CheckPredicate, 16, 224, 3, 0, // Skip to: 86948 -/* 85956 */ MCD_OPC_CheckField, 10, 6, 0, 217, 3, 0, // Skip to: 86948 -/* 85963 */ MCD_OPC_Decode, 202, 8, 251, 3, // Opcode: FCVTPUUXDr -/* 85968 */ MCD_OPC_FilterValue, 112, 17, 0, 0, // Skip to: 85990 -/* 85973 */ MCD_OPC_CheckPredicate, 16, 202, 3, 0, // Skip to: 86948 -/* 85978 */ MCD_OPC_CheckField, 10, 6, 0, 195, 3, 0, // Skip to: 86948 -/* 85985 */ MCD_OPC_Decode, 128, 8, 251, 3, // Opcode: FCVTMSUXDr -/* 85990 */ MCD_OPC_FilterValue, 113, 17, 0, 0, // Skip to: 86012 -/* 85995 */ MCD_OPC_CheckPredicate, 16, 180, 3, 0, // Skip to: 86948 -/* 86000 */ MCD_OPC_CheckField, 10, 6, 0, 173, 3, 0, // Skip to: 86948 -/* 86007 */ MCD_OPC_Decode, 142, 8, 251, 3, // Opcode: FCVTMUUXDr -/* 86012 */ MCD_OPC_FilterValue, 120, 17, 0, 0, // Skip to: 86034 -/* 86017 */ MCD_OPC_CheckPredicate, 16, 158, 3, 0, // Skip to: 86948 -/* 86022 */ MCD_OPC_CheckField, 10, 6, 0, 151, 3, 0, // Skip to: 86948 -/* 86029 */ MCD_OPC_Decode, 227, 8, 251, 3, // Opcode: FCVTZSUXDr -/* 86034 */ MCD_OPC_FilterValue, 121, 17, 0, 0, // Skip to: 86056 -/* 86039 */ MCD_OPC_CheckPredicate, 16, 136, 3, 0, // Skip to: 86948 -/* 86044 */ MCD_OPC_CheckField, 10, 6, 0, 129, 3, 0, // Skip to: 86948 -/* 86051 */ MCD_OPC_Decode, 134, 9, 251, 3, // Opcode: FCVTZUUXDr -/* 86056 */ MCD_OPC_FilterValue, 174, 1, 17, 0, 0, // Skip to: 86079 -/* 86062 */ MCD_OPC_CheckPredicate, 16, 113, 3, 0, // Skip to: 86948 -/* 86067 */ MCD_OPC_CheckField, 10, 6, 0, 106, 3, 0, // Skip to: 86948 -/* 86074 */ MCD_OPC_Decode, 216, 10, 253, 3, // Opcode: FMOVDXHighr -/* 86079 */ MCD_OPC_FilterValue, 175, 1, 17, 0, 0, // Skip to: 86102 -/* 86085 */ MCD_OPC_CheckPredicate, 16, 90, 3, 0, // Skip to: 86948 -/* 86090 */ MCD_OPC_CheckField, 10, 6, 0, 83, 3, 0, // Skip to: 86948 -/* 86097 */ MCD_OPC_Decode, 231, 10, 253, 3, // Opcode: FMOVXDHighr -/* 86102 */ MCD_OPC_FilterValue, 194, 1, 10, 0, 0, // Skip to: 86118 -/* 86108 */ MCD_OPC_CheckPredicate, 18, 67, 3, 0, // Skip to: 86948 -/* 86113 */ MCD_OPC_Decode, 188, 22, 254, 3, // Opcode: SCVTFSXHri -/* 86118 */ MCD_OPC_FilterValue, 195, 1, 10, 0, 0, // Skip to: 86134 -/* 86124 */ MCD_OPC_CheckPredicate, 18, 51, 3, 0, // Skip to: 86948 -/* 86129 */ MCD_OPC_Decode, 175, 31, 254, 3, // Opcode: UCVTFSXHri -/* 86134 */ MCD_OPC_FilterValue, 216, 1, 10, 0, 0, // Skip to: 86150 -/* 86140 */ MCD_OPC_CheckPredicate, 18, 35, 3, 0, // Skip to: 86948 -/* 86145 */ MCD_OPC_Decode, 222, 8, 255, 3, // Opcode: FCVTZSSXHri -/* 86150 */ MCD_OPC_FilterValue, 217, 1, 10, 0, 0, // Skip to: 86166 -/* 86156 */ MCD_OPC_CheckPredicate, 18, 19, 3, 0, // Skip to: 86948 -/* 86161 */ MCD_OPC_Decode, 129, 9, 255, 3, // Opcode: FCVTZUSXHri -/* 86166 */ MCD_OPC_FilterValue, 224, 1, 17, 0, 0, // Skip to: 86189 -/* 86172 */ MCD_OPC_CheckPredicate, 18, 3, 3, 0, // Skip to: 86948 -/* 86177 */ MCD_OPC_CheckField, 10, 6, 0, 252, 2, 0, // Skip to: 86948 -/* 86184 */ MCD_OPC_Decode, 157, 8, 128, 4, // Opcode: FCVTNSUXHr -/* 86189 */ MCD_OPC_FilterValue, 225, 1, 17, 0, 0, // Skip to: 86212 -/* 86195 */ MCD_OPC_CheckPredicate, 18, 236, 2, 0, // Skip to: 86948 -/* 86200 */ MCD_OPC_CheckField, 10, 6, 0, 229, 2, 0, // Skip to: 86948 -/* 86207 */ MCD_OPC_Decode, 171, 8, 128, 4, // Opcode: FCVTNUUXHr -/* 86212 */ MCD_OPC_FilterValue, 226, 1, 17, 0, 0, // Skip to: 86235 -/* 86218 */ MCD_OPC_CheckPredicate, 18, 213, 2, 0, // Skip to: 86948 -/* 86223 */ MCD_OPC_CheckField, 10, 6, 0, 206, 2, 0, // Skip to: 86948 -/* 86230 */ MCD_OPC_Decode, 194, 22, 129, 4, // Opcode: SCVTFUXHri -/* 86235 */ MCD_OPC_FilterValue, 227, 1, 17, 0, 0, // Skip to: 86258 -/* 86241 */ MCD_OPC_CheckPredicate, 18, 190, 2, 0, // Skip to: 86948 -/* 86246 */ MCD_OPC_CheckField, 10, 6, 0, 183, 2, 0, // Skip to: 86948 -/* 86253 */ MCD_OPC_Decode, 181, 31, 129, 4, // Opcode: UCVTFUXHri -/* 86258 */ MCD_OPC_FilterValue, 228, 1, 17, 0, 0, // Skip to: 86281 -/* 86264 */ MCD_OPC_CheckPredicate, 18, 167, 2, 0, // Skip to: 86948 -/* 86269 */ MCD_OPC_CheckField, 10, 6, 0, 160, 2, 0, // Skip to: 86948 -/* 86276 */ MCD_OPC_Decode, 221, 7, 128, 4, // Opcode: FCVTASUXHr -/* 86281 */ MCD_OPC_FilterValue, 229, 1, 17, 0, 0, // Skip to: 86304 -/* 86287 */ MCD_OPC_CheckPredicate, 18, 144, 2, 0, // Skip to: 86948 -/* 86292 */ MCD_OPC_CheckField, 10, 6, 0, 137, 2, 0, // Skip to: 86948 -/* 86299 */ MCD_OPC_Decode, 235, 7, 128, 4, // Opcode: FCVTAUUXHr -/* 86304 */ MCD_OPC_FilterValue, 230, 1, 17, 0, 0, // Skip to: 86327 -/* 86310 */ MCD_OPC_CheckPredicate, 18, 121, 2, 0, // Skip to: 86948 -/* 86315 */ MCD_OPC_CheckField, 10, 6, 0, 114, 2, 0, // Skip to: 86948 -/* 86322 */ MCD_OPC_Decode, 222, 10, 128, 4, // Opcode: FMOVHXr -/* 86327 */ MCD_OPC_FilterValue, 231, 1, 17, 0, 0, // Skip to: 86350 -/* 86333 */ MCD_OPC_CheckPredicate, 18, 98, 2, 0, // Skip to: 86948 -/* 86338 */ MCD_OPC_CheckField, 10, 6, 0, 91, 2, 0, // Skip to: 86948 -/* 86345 */ MCD_OPC_Decode, 233, 10, 129, 4, // Opcode: FMOVXHr -/* 86350 */ MCD_OPC_FilterValue, 232, 1, 17, 0, 0, // Skip to: 86373 -/* 86356 */ MCD_OPC_CheckPredicate, 18, 75, 2, 0, // Skip to: 86948 -/* 86361 */ MCD_OPC_CheckField, 10, 6, 0, 68, 2, 0, // Skip to: 86948 -/* 86368 */ MCD_OPC_Decode, 189, 8, 128, 4, // Opcode: FCVTPSUXHr -/* 86373 */ MCD_OPC_FilterValue, 233, 1, 17, 0, 0, // Skip to: 86396 -/* 86379 */ MCD_OPC_CheckPredicate, 18, 52, 2, 0, // Skip to: 86948 -/* 86384 */ MCD_OPC_CheckField, 10, 6, 0, 45, 2, 0, // Skip to: 86948 -/* 86391 */ MCD_OPC_Decode, 203, 8, 128, 4, // Opcode: FCVTPUUXHr -/* 86396 */ MCD_OPC_FilterValue, 240, 1, 17, 0, 0, // Skip to: 86419 -/* 86402 */ MCD_OPC_CheckPredicate, 18, 29, 2, 0, // Skip to: 86948 -/* 86407 */ MCD_OPC_CheckField, 10, 6, 0, 22, 2, 0, // Skip to: 86948 -/* 86414 */ MCD_OPC_Decode, 129, 8, 128, 4, // Opcode: FCVTMSUXHr -/* 86419 */ MCD_OPC_FilterValue, 241, 1, 17, 0, 0, // Skip to: 86442 -/* 86425 */ MCD_OPC_CheckPredicate, 18, 6, 2, 0, // Skip to: 86948 -/* 86430 */ MCD_OPC_CheckField, 10, 6, 0, 255, 1, 0, // Skip to: 86948 -/* 86437 */ MCD_OPC_Decode, 143, 8, 128, 4, // Opcode: FCVTMUUXHr -/* 86442 */ MCD_OPC_FilterValue, 248, 1, 17, 0, 0, // Skip to: 86465 -/* 86448 */ MCD_OPC_CheckPredicate, 18, 239, 1, 0, // Skip to: 86948 -/* 86453 */ MCD_OPC_CheckField, 10, 6, 0, 232, 1, 0, // Skip to: 86948 -/* 86460 */ MCD_OPC_Decode, 228, 8, 128, 4, // Opcode: FCVTZSUXHr -/* 86465 */ MCD_OPC_FilterValue, 249, 1, 221, 1, 0, // Skip to: 86948 -/* 86471 */ MCD_OPC_CheckPredicate, 18, 216, 1, 0, // Skip to: 86948 -/* 86476 */ MCD_OPC_CheckField, 10, 6, 0, 209, 1, 0, // Skip to: 86948 -/* 86483 */ MCD_OPC_Decode, 135, 9, 128, 4, // Opcode: FCVTZUUXHr -/* 86488 */ MCD_OPC_FilterValue, 5, 225, 0, 0, // Skip to: 86718 -/* 86493 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 86496 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 86597 -/* 86501 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 86504 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86521 -/* 86509 */ MCD_OPC_CheckField, 21, 1, 0, 176, 1, 0, // Skip to: 86948 -/* 86516 */ MCD_OPC_Decode, 202, 29, 255, 2, // Opcode: STURSi -/* 86521 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86538 -/* 86526 */ MCD_OPC_CheckField, 21, 1, 0, 159, 1, 0, // Skip to: 86948 -/* 86533 */ MCD_OPC_Decode, 175, 29, 255, 2, // Opcode: STRSpost -/* 86538 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86580 -/* 86543 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 86546 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86563 -/* 86551 */ MCD_OPC_CheckField, 21, 1, 1, 134, 1, 0, // Skip to: 86948 -/* 86558 */ MCD_OPC_Decode, 177, 29, 130, 4, // Opcode: STRSroW -/* 86563 */ MCD_OPC_FilterValue, 3, 124, 1, 0, // Skip to: 86948 -/* 86568 */ MCD_OPC_CheckField, 21, 1, 1, 117, 1, 0, // Skip to: 86948 -/* 86575 */ MCD_OPC_Decode, 178, 29, 131, 4, // Opcode: STRSroX -/* 86580 */ MCD_OPC_FilterValue, 3, 107, 1, 0, // Skip to: 86948 -/* 86585 */ MCD_OPC_CheckField, 21, 1, 0, 100, 1, 0, // Skip to: 86948 -/* 86592 */ MCD_OPC_Decode, 176, 29, 255, 2, // Opcode: STRSpre -/* 86597 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 86698 -/* 86602 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 86605 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86622 -/* 86610 */ MCD_OPC_CheckField, 21, 1, 0, 75, 1, 0, // Skip to: 86948 -/* 86617 */ MCD_OPC_Decode, 141, 19, 255, 2, // Opcode: LDURSi -/* 86622 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86639 -/* 86627 */ MCD_OPC_CheckField, 21, 1, 0, 58, 1, 0, // Skip to: 86948 -/* 86634 */ MCD_OPC_Decode, 150, 18, 255, 2, // Opcode: LDRSpost -/* 86639 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86681 -/* 86644 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 86647 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86664 -/* 86652 */ MCD_OPC_CheckField, 21, 1, 1, 33, 1, 0, // Skip to: 86948 -/* 86659 */ MCD_OPC_Decode, 152, 18, 130, 4, // Opcode: LDRSroW -/* 86664 */ MCD_OPC_FilterValue, 3, 23, 1, 0, // Skip to: 86948 -/* 86669 */ MCD_OPC_CheckField, 21, 1, 1, 16, 1, 0, // Skip to: 86948 -/* 86676 */ MCD_OPC_Decode, 153, 18, 131, 4, // Opcode: LDRSroX -/* 86681 */ MCD_OPC_FilterValue, 3, 6, 1, 0, // Skip to: 86948 -/* 86686 */ MCD_OPC_CheckField, 21, 1, 0, 255, 0, 0, // Skip to: 86948 -/* 86693 */ MCD_OPC_Decode, 151, 18, 255, 2, // Opcode: LDRSpre -/* 86698 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 86708 -/* 86703 */ MCD_OPC_Decode, 179, 29, 137, 3, // Opcode: STRSui -/* 86708 */ MCD_OPC_FilterValue, 5, 235, 0, 0, // Skip to: 86948 -/* 86713 */ MCD_OPC_Decode, 154, 18, 137, 3, // Opcode: LDRSui -/* 86718 */ MCD_OPC_FilterValue, 7, 225, 0, 0, // Skip to: 86948 -/* 86723 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 86726 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 86827 -/* 86731 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 86734 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86751 -/* 86739 */ MCD_OPC_CheckField, 21, 1, 0, 202, 0, 0, // Skip to: 86948 -/* 86746 */ MCD_OPC_Decode, 198, 29, 255, 2, // Opcode: STURDi -/* 86751 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86768 -/* 86756 */ MCD_OPC_CheckField, 21, 1, 0, 185, 0, 0, // Skip to: 86948 -/* 86763 */ MCD_OPC_Decode, 155, 29, 255, 2, // Opcode: STRDpost -/* 86768 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86810 -/* 86773 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 86776 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86793 -/* 86781 */ MCD_OPC_CheckField, 21, 1, 1, 160, 0, 0, // Skip to: 86948 -/* 86788 */ MCD_OPC_Decode, 157, 29, 132, 4, // Opcode: STRDroW -/* 86793 */ MCD_OPC_FilterValue, 3, 150, 0, 0, // Skip to: 86948 -/* 86798 */ MCD_OPC_CheckField, 21, 1, 1, 143, 0, 0, // Skip to: 86948 -/* 86805 */ MCD_OPC_Decode, 158, 29, 133, 4, // Opcode: STRDroX -/* 86810 */ MCD_OPC_FilterValue, 3, 133, 0, 0, // Skip to: 86948 -/* 86815 */ MCD_OPC_CheckField, 21, 1, 0, 126, 0, 0, // Skip to: 86948 -/* 86822 */ MCD_OPC_Decode, 156, 29, 255, 2, // Opcode: STRDpre -/* 86827 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 86928 -/* 86832 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 86835 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86852 -/* 86840 */ MCD_OPC_CheckField, 21, 1, 0, 101, 0, 0, // Skip to: 86948 -/* 86847 */ MCD_OPC_Decode, 132, 19, 255, 2, // Opcode: LDURDi -/* 86852 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86869 -/* 86857 */ MCD_OPC_CheckField, 21, 1, 0, 84, 0, 0, // Skip to: 86948 -/* 86864 */ MCD_OPC_Decode, 230, 17, 255, 2, // Opcode: LDRDpost -/* 86869 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86911 -/* 86874 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 86877 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86894 -/* 86882 */ MCD_OPC_CheckField, 21, 1, 1, 59, 0, 0, // Skip to: 86948 -/* 86889 */ MCD_OPC_Decode, 232, 17, 132, 4, // Opcode: LDRDroW -/* 86894 */ MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 86948 -/* 86899 */ MCD_OPC_CheckField, 21, 1, 1, 42, 0, 0, // Skip to: 86948 -/* 86906 */ MCD_OPC_Decode, 233, 17, 133, 4, // Opcode: LDRDroX -/* 86911 */ MCD_OPC_FilterValue, 3, 32, 0, 0, // Skip to: 86948 -/* 86916 */ MCD_OPC_CheckField, 21, 1, 0, 25, 0, 0, // Skip to: 86948 -/* 86923 */ MCD_OPC_Decode, 231, 17, 255, 2, // Opcode: LDRDpre -/* 86928 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 86938 -/* 86933 */ MCD_OPC_Decode, 159, 29, 137, 3, // Opcode: STRDui -/* 86938 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 86948 -/* 86943 */ MCD_OPC_Decode, 234, 17, 137, 3, // Opcode: LDRDui -/* 86948 */ MCD_OPC_Fail, - 0 -}; - -static bool checkDecoderPredicate(unsigned Idx, MCInst *MI) -{ + /* 0 */ MCD_OPC_ExtractField, + 26, + 3, // Inst{28-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 0, + 7, + 0, // Skip to: 1800 + /* 8 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 182, + 0, + 0, // Skip to: 198 + /* 16 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 35 + /* 24 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 48, + 152, + 1, // Skip to: 104527 + /* 31 */ MCD_OPC_Decode, + 223, + 42, + 0, // Opcode: UDF + /* 35 */ MCD_OPC_FilterValue, + 6, + 108, + 0, + 0, // Skip to: 148 + /* 40 */ MCD_OPC_ExtractField, + 15, + 6, // Inst{20-15} ... + /* 43 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 64 + /* 48 */ MCD_OPC_CheckPredicate, + 0, + 26, + 152, + 1, // Skip to: 104527 + /* 53 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 19, + 152, + 1, // Skip to: 104527 + /* 60 */ MCD_OPC_Decode, + 165, + 21, + 1, // Opcode: INSERT_MXIPZ_H_B + /* 64 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 85 + /* 69 */ MCD_OPC_CheckPredicate, + 0, + 5, + 152, + 1, // Skip to: 104527 + /* 74 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 254, + 151, + 1, // Skip to: 104527 + /* 81 */ MCD_OPC_Decode, + 170, + 21, + 1, // Opcode: INSERT_MXIPZ_V_B + /* 85 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 106 + /* 90 */ MCD_OPC_CheckPredicate, + 0, + 240, + 151, + 1, // Skip to: 104527 + /* 95 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 233, + 151, + 1, // Skip to: 104527 + /* 102 */ MCD_OPC_Decode, + 184, + 12, + 2, // Opcode: EXTRACT_ZPMXI_H_B + /* 106 */ MCD_OPC_FilterValue, + 5, + 16, + 0, + 0, // Skip to: 127 + /* 111 */ MCD_OPC_CheckPredicate, + 0, + 219, + 151, + 1, // Skip to: 104527 + /* 116 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 212, + 151, + 1, // Skip to: 104527 + /* 123 */ MCD_OPC_Decode, + 189, + 12, + 2, // Opcode: EXTRACT_ZPMXI_V_B + /* 127 */ MCD_OPC_FilterValue, + 16, + 203, + 151, + 1, // Skip to: 104527 + /* 132 */ MCD_OPC_CheckPredicate, + 0, + 198, + 151, + 1, // Skip to: 104527 + /* 137 */ MCD_OPC_CheckField, + 8, + 7, + 0, + 191, + 151, + 1, // Skip to: 104527 + /* 144 */ MCD_OPC_Decode, + 246, + 47, + 3, // Opcode: ZERO_M + /* 148 */ MCD_OPC_FilterValue, + 7, + 182, + 151, + 1, // Skip to: 104527 + /* 153 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 156 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 177 + /* 161 */ MCD_OPC_CheckPredicate, + 0, + 169, + 151, + 1, // Skip to: 104527 + /* 166 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 162, + 151, + 1, // Skip to: 104527 + /* 173 */ MCD_OPC_Decode, + 225, + 22, + 4, // Opcode: LD1_MXIPXX_H_B + /* 177 */ MCD_OPC_FilterValue, + 1, + 153, + 151, + 1, // Skip to: 104527 + /* 182 */ MCD_OPC_CheckPredicate, + 0, + 148, + 151, + 1, // Skip to: 104527 + /* 187 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 141, + 151, + 1, // Skip to: 104527 + /* 194 */ MCD_OPC_Decode, + 230, + 22, + 4, // Opcode: LD1_MXIPXX_V_B + /* 198 */ MCD_OPC_FilterValue, + 1, + 59, + 0, + 0, // Skip to: 262 + /* 203 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 206 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 234 + /* 211 */ MCD_OPC_CheckPredicate, + 0, + 119, + 151, + 1, // Skip to: 104527 + /* 216 */ MCD_OPC_CheckField, + 29, + 3, + 7, + 112, + 151, + 1, // Skip to: 104527 + /* 223 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 105, + 151, + 1, // Skip to: 104527 + /* 230 */ MCD_OPC_Decode, + 175, + 38, + 4, // Opcode: ST1_MXIPXX_H_B + /* 234 */ MCD_OPC_FilterValue, + 1, + 96, + 151, + 1, // Skip to: 104527 + /* 239 */ MCD_OPC_CheckPredicate, + 0, + 91, + 151, + 1, // Skip to: 104527 + /* 244 */ MCD_OPC_CheckField, + 29, + 3, + 7, + 84, + 151, + 1, // Skip to: 104527 + /* 251 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 77, + 151, + 1, // Skip to: 104527 + /* 258 */ MCD_OPC_Decode, + 180, + 38, + 4, // Opcode: ST1_MXIPXX_V_B + /* 262 */ MCD_OPC_FilterValue, + 2, + 161, + 0, + 0, // Skip to: 428 + /* 267 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 270 */ MCD_OPC_FilterValue, + 0, + 74, + 0, + 0, // Skip to: 349 + /* 275 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 278 */ MCD_OPC_FilterValue, + 6, + 45, + 0, + 0, // Skip to: 328 + /* 283 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 286 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 307 + /* 291 */ MCD_OPC_CheckPredicate, + 0, + 39, + 151, + 1, // Skip to: 104527 + /* 296 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 32, + 151, + 1, // Skip to: 104527 + /* 303 */ MCD_OPC_Decode, + 167, + 21, + 5, // Opcode: INSERT_MXIPZ_H_H + /* 307 */ MCD_OPC_FilterValue, + 2, + 23, + 151, + 1, // Skip to: 104527 + /* 312 */ MCD_OPC_CheckPredicate, + 0, + 18, + 151, + 1, // Skip to: 104527 + /* 317 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 11, + 151, + 1, // Skip to: 104527 + /* 324 */ MCD_OPC_Decode, + 186, + 12, + 6, // Opcode: EXTRACT_ZPMXI_H_H + /* 328 */ MCD_OPC_FilterValue, + 7, + 2, + 151, + 1, // Skip to: 104527 + /* 333 */ MCD_OPC_CheckPredicate, + 0, + 253, + 150, + 1, // Skip to: 104527 + /* 338 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 246, + 150, + 1, // Skip to: 104527 + /* 345 */ MCD_OPC_Decode, + 227, + 22, + 7, // Opcode: LD1_MXIPXX_H_H + /* 349 */ MCD_OPC_FilterValue, + 1, + 237, + 150, + 1, // Skip to: 104527 + /* 354 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 357 */ MCD_OPC_FilterValue, + 6, + 45, + 0, + 0, // Skip to: 407 + /* 362 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 365 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 386 + /* 370 */ MCD_OPC_CheckPredicate, + 0, + 216, + 150, + 1, // Skip to: 104527 + /* 375 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 209, + 150, + 1, // Skip to: 104527 + /* 382 */ MCD_OPC_Decode, + 172, + 21, + 5, // Opcode: INSERT_MXIPZ_V_H + /* 386 */ MCD_OPC_FilterValue, + 2, + 200, + 150, + 1, // Skip to: 104527 + /* 391 */ MCD_OPC_CheckPredicate, + 0, + 195, + 150, + 1, // Skip to: 104527 + /* 396 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 188, + 150, + 1, // Skip to: 104527 + /* 403 */ MCD_OPC_Decode, + 191, + 12, + 6, // Opcode: EXTRACT_ZPMXI_V_H + /* 407 */ MCD_OPC_FilterValue, + 7, + 179, + 150, + 1, // Skip to: 104527 + /* 412 */ MCD_OPC_CheckPredicate, + 0, + 174, + 150, + 1, // Skip to: 104527 + /* 417 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 167, + 150, + 1, // Skip to: 104527 + /* 424 */ MCD_OPC_Decode, + 232, + 22, + 7, // Opcode: LD1_MXIPXX_V_H + /* 428 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 492 + /* 433 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 436 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 464 + /* 441 */ MCD_OPC_CheckPredicate, + 0, + 145, + 150, + 1, // Skip to: 104527 + /* 446 */ MCD_OPC_CheckField, + 29, + 3, + 7, + 138, + 150, + 1, // Skip to: 104527 + /* 453 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 131, + 150, + 1, // Skip to: 104527 + /* 460 */ MCD_OPC_Decode, + 177, + 38, + 7, // Opcode: ST1_MXIPXX_H_H + /* 464 */ MCD_OPC_FilterValue, + 1, + 122, + 150, + 1, // Skip to: 104527 + /* 469 */ MCD_OPC_CheckPredicate, + 0, + 117, + 150, + 1, // Skip to: 104527 + /* 474 */ MCD_OPC_CheckField, + 29, + 3, + 7, + 110, + 150, + 1, // Skip to: 104527 + /* 481 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 103, + 150, + 1, // Skip to: 104527 + /* 488 */ MCD_OPC_Decode, + 182, + 38, + 7, // Opcode: ST1_MXIPXX_V_H + /* 492 */ MCD_OPC_FilterValue, + 4, + 19, + 1, + 0, // Skip to: 772 + /* 497 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 500 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 536 + /* 505 */ MCD_OPC_ExtractField, + 2, + 3, // Inst{4-2} ... + /* 508 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 522 + /* 513 */ MCD_OPC_CheckPredicate, + 0, + 73, + 150, + 1, // Skip to: 104527 + /* 518 */ MCD_OPC_Decode, + 210, + 17, + 8, // Opcode: FMOPA_MPPZZ_S + /* 522 */ MCD_OPC_FilterValue, + 4, + 64, + 150, + 1, // Skip to: 104527 + /* 527 */ MCD_OPC_CheckPredicate, + 0, + 59, + 150, + 1, // Skip to: 104527 + /* 532 */ MCD_OPC_Decode, + 212, + 17, + 8, // Opcode: FMOPS_MPPZZ_S + /* 536 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 572 + /* 541 */ MCD_OPC_ExtractField, + 2, + 3, // Inst{4-2} ... + /* 544 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 558 + /* 549 */ MCD_OPC_CheckPredicate, + 0, + 37, + 150, + 1, // Skip to: 104527 + /* 554 */ MCD_OPC_Decode, + 198, + 32, + 8, // Opcode: SMOPA_MPPZZ_S + /* 558 */ MCD_OPC_FilterValue, + 4, + 28, + 150, + 1, // Skip to: 104527 + /* 563 */ MCD_OPC_CheckPredicate, + 0, + 23, + 150, + 1, // Skip to: 104527 + /* 568 */ MCD_OPC_Decode, + 200, + 32, + 8, // Opcode: SMOPS_MPPZZ_S + /* 572 */ MCD_OPC_FilterValue, + 6, + 145, + 0, + 0, // Skip to: 722 + /* 577 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 580 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 630 + /* 585 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 588 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 609 + /* 593 */ MCD_OPC_CheckPredicate, + 0, + 249, + 149, + 1, // Skip to: 104527 + /* 598 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 242, + 149, + 1, // Skip to: 104527 + /* 605 */ MCD_OPC_Decode, + 169, + 21, + 9, // Opcode: INSERT_MXIPZ_H_S + /* 609 */ MCD_OPC_FilterValue, + 1, + 233, + 149, + 1, // Skip to: 104527 + /* 614 */ MCD_OPC_CheckPredicate, + 0, + 228, + 149, + 1, // Skip to: 104527 + /* 619 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 221, + 149, + 1, // Skip to: 104527 + /* 626 */ MCD_OPC_Decode, + 174, + 21, + 9, // Opcode: INSERT_MXIPZ_V_S + /* 630 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 680 + /* 635 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 638 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 659 + /* 643 */ MCD_OPC_CheckPredicate, + 0, + 199, + 149, + 1, // Skip to: 104527 + /* 648 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 192, + 149, + 1, // Skip to: 104527 + /* 655 */ MCD_OPC_Decode, + 188, + 12, + 10, // Opcode: EXTRACT_ZPMXI_H_S + /* 659 */ MCD_OPC_FilterValue, + 1, + 183, + 149, + 1, // Skip to: 104527 + /* 664 */ MCD_OPC_CheckPredicate, + 0, + 178, + 149, + 1, // Skip to: 104527 + /* 669 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 171, + 149, + 1, // Skip to: 104527 + /* 676 */ MCD_OPC_Decode, + 193, + 12, + 10, // Opcode: EXTRACT_ZPMXI_V_S + /* 680 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 701 + /* 685 */ MCD_OPC_CheckPredicate, + 0, + 157, + 149, + 1, // Skip to: 104527 + /* 690 */ MCD_OPC_CheckField, + 2, + 3, + 0, + 150, + 149, + 1, // Skip to: 104527 + /* 697 */ MCD_OPC_Decode, + 150, + 7, + 11, // Opcode: ADDHA_MPPZ_S + /* 701 */ MCD_OPC_FilterValue, + 17, + 141, + 149, + 1, // Skip to: 104527 + /* 706 */ MCD_OPC_CheckPredicate, + 0, + 136, + 149, + 1, // Skip to: 104527 + /* 711 */ MCD_OPC_CheckField, + 2, + 3, + 0, + 129, + 149, + 1, // Skip to: 104527 + /* 718 */ MCD_OPC_Decode, + 184, + 7, + 11, // Opcode: ADDVA_MPPZ_S + /* 722 */ MCD_OPC_FilterValue, + 7, + 120, + 149, + 1, // Skip to: 104527 + /* 727 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 730 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 751 + /* 735 */ MCD_OPC_CheckPredicate, + 0, + 107, + 149, + 1, // Skip to: 104527 + /* 740 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 100, + 149, + 1, // Skip to: 104527 + /* 747 */ MCD_OPC_Decode, + 229, + 22, + 12, // Opcode: LD1_MXIPXX_H_S + /* 751 */ MCD_OPC_FilterValue, + 1, + 91, + 149, + 1, // Skip to: 104527 + /* 756 */ MCD_OPC_CheckPredicate, + 0, + 86, + 149, + 1, // Skip to: 104527 + /* 761 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 79, + 149, + 1, // Skip to: 104527 + /* 768 */ MCD_OPC_Decode, + 234, + 22, + 12, // Opcode: LD1_MXIPXX_V_S + /* 772 */ MCD_OPC_FilterValue, + 5, + 96, + 0, + 0, // Skip to: 873 + /* 777 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 780 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 845 + /* 785 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 788 */ MCD_OPC_FilterValue, + 5, + 16, + 0, + 0, // Skip to: 809 + /* 793 */ MCD_OPC_CheckPredicate, + 0, + 49, + 149, + 1, // Skip to: 104527 + /* 798 */ MCD_OPC_CheckField, + 2, + 2, + 0, + 42, + 149, + 1, // Skip to: 104527 + /* 805 */ MCD_OPC_Decode, + 228, + 40, + 8, // Opcode: SUMOPA_MPPZZ_S + /* 809 */ MCD_OPC_FilterValue, + 7, + 33, + 149, + 1, // Skip to: 104527 + /* 814 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 817 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 831 + /* 822 */ MCD_OPC_CheckPredicate, + 0, + 20, + 149, + 1, // Skip to: 104527 + /* 827 */ MCD_OPC_Decode, + 179, + 38, + 12, // Opcode: ST1_MXIPXX_H_S + /* 831 */ MCD_OPC_FilterValue, + 1, + 11, + 149, + 1, // Skip to: 104527 + /* 836 */ MCD_OPC_CheckPredicate, + 0, + 6, + 149, + 1, // Skip to: 104527 + /* 841 */ MCD_OPC_Decode, + 184, + 38, + 12, // Opcode: ST1_MXIPXX_V_S + /* 845 */ MCD_OPC_FilterValue, + 1, + 253, + 148, + 1, // Skip to: 104527 + /* 850 */ MCD_OPC_CheckPredicate, + 0, + 248, + 148, + 1, // Skip to: 104527 + /* 855 */ MCD_OPC_CheckField, + 29, + 3, + 5, + 241, + 148, + 1, // Skip to: 104527 + /* 862 */ MCD_OPC_CheckField, + 2, + 2, + 0, + 234, + 148, + 1, // Skip to: 104527 + /* 869 */ MCD_OPC_Decode, + 230, + 40, + 8, // Opcode: SUMOPS_MPPZZ_S + /* 873 */ MCD_OPC_FilterValue, + 6, + 119, + 1, + 0, // Skip to: 1253 + /* 878 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 881 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 917 + /* 886 */ MCD_OPC_ExtractField, + 3, + 2, // Inst{4-3} ... + /* 889 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 903 + /* 894 */ MCD_OPC_CheckPredicate, + 1, + 204, + 148, + 1, // Skip to: 104527 + /* 899 */ MCD_OPC_Decode, + 209, + 17, + 13, // Opcode: FMOPA_MPPZZ_D + /* 903 */ MCD_OPC_FilterValue, + 2, + 195, + 148, + 1, // Skip to: 104527 + /* 908 */ MCD_OPC_CheckPredicate, + 1, + 190, + 148, + 1, // Skip to: 104527 + /* 913 */ MCD_OPC_Decode, + 211, + 17, + 13, // Opcode: FMOPS_MPPZZ_D + /* 917 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 953 + /* 922 */ MCD_OPC_ExtractField, + 3, + 2, // Inst{4-3} ... + /* 925 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 939 + /* 930 */ MCD_OPC_CheckPredicate, + 2, + 168, + 148, + 1, // Skip to: 104527 + /* 935 */ MCD_OPC_Decode, + 197, + 32, + 13, // Opcode: SMOPA_MPPZZ_D + /* 939 */ MCD_OPC_FilterValue, + 2, + 159, + 148, + 1, // Skip to: 104527 + /* 944 */ MCD_OPC_CheckPredicate, + 2, + 154, + 148, + 1, // Skip to: 104527 + /* 949 */ MCD_OPC_Decode, + 199, + 32, + 13, // Opcode: SMOPS_MPPZZ_D + /* 953 */ MCD_OPC_FilterValue, + 6, + 245, + 0, + 0, // Skip to: 1203 + /* 958 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 961 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 1011 + /* 966 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 969 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 990 + /* 974 */ MCD_OPC_CheckPredicate, + 0, + 124, + 148, + 1, // Skip to: 104527 + /* 979 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 117, + 148, + 1, // Skip to: 104527 + /* 986 */ MCD_OPC_Decode, + 166, + 21, + 14, // Opcode: INSERT_MXIPZ_H_D + /* 990 */ MCD_OPC_FilterValue, + 1, + 108, + 148, + 1, // Skip to: 104527 + /* 995 */ MCD_OPC_CheckPredicate, + 0, + 103, + 148, + 1, // Skip to: 104527 + /* 1000 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 96, + 148, + 1, // Skip to: 104527 + /* 1007 */ MCD_OPC_Decode, + 171, + 21, + 14, // Opcode: INSERT_MXIPZ_V_D + /* 1011 */ MCD_OPC_FilterValue, + 1, + 45, + 0, + 0, // Skip to: 1061 + /* 1016 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 1019 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1040 + /* 1024 */ MCD_OPC_CheckPredicate, + 0, + 74, + 148, + 1, // Skip to: 104527 + /* 1029 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 67, + 148, + 1, // Skip to: 104527 + /* 1036 */ MCD_OPC_Decode, + 168, + 21, + 15, // Opcode: INSERT_MXIPZ_H_Q + /* 1040 */ MCD_OPC_FilterValue, + 1, + 58, + 148, + 1, // Skip to: 104527 + /* 1045 */ MCD_OPC_CheckPredicate, + 0, + 53, + 148, + 1, // Skip to: 104527 + /* 1050 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 46, + 148, + 1, // Skip to: 104527 + /* 1057 */ MCD_OPC_Decode, + 173, + 21, + 15, // Opcode: INSERT_MXIPZ_V_Q + /* 1061 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 1111 + /* 1066 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 1069 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1090 + /* 1074 */ MCD_OPC_CheckPredicate, + 0, + 24, + 148, + 1, // Skip to: 104527 + /* 1079 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 17, + 148, + 1, // Skip to: 104527 + /* 1086 */ MCD_OPC_Decode, + 185, + 12, + 16, // Opcode: EXTRACT_ZPMXI_H_D + /* 1090 */ MCD_OPC_FilterValue, + 1, + 8, + 148, + 1, // Skip to: 104527 + /* 1095 */ MCD_OPC_CheckPredicate, + 0, + 3, + 148, + 1, // Skip to: 104527 + /* 1100 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 252, + 147, + 1, // Skip to: 104527 + /* 1107 */ MCD_OPC_Decode, + 190, + 12, + 16, // Opcode: EXTRACT_ZPMXI_V_D + /* 1111 */ MCD_OPC_FilterValue, + 3, + 45, + 0, + 0, // Skip to: 1161 + /* 1116 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 1119 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1140 + /* 1124 */ MCD_OPC_CheckPredicate, + 0, + 230, + 147, + 1, // Skip to: 104527 + /* 1129 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 223, + 147, + 1, // Skip to: 104527 + /* 1136 */ MCD_OPC_Decode, + 187, + 12, + 17, // Opcode: EXTRACT_ZPMXI_H_Q + /* 1140 */ MCD_OPC_FilterValue, + 1, + 214, + 147, + 1, // Skip to: 104527 + /* 1145 */ MCD_OPC_CheckPredicate, + 0, + 209, + 147, + 1, // Skip to: 104527 + /* 1150 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 202, + 147, + 1, // Skip to: 104527 + /* 1157 */ MCD_OPC_Decode, + 192, + 12, + 17, // Opcode: EXTRACT_ZPMXI_V_Q + /* 1161 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 1182 + /* 1166 */ MCD_OPC_CheckPredicate, + 2, + 188, + 147, + 1, // Skip to: 104527 + /* 1171 */ MCD_OPC_CheckField, + 3, + 2, + 0, + 181, + 147, + 1, // Skip to: 104527 + /* 1178 */ MCD_OPC_Decode, + 149, + 7, + 18, // Opcode: ADDHA_MPPZ_D + /* 1182 */ MCD_OPC_FilterValue, + 17, + 172, + 147, + 1, // Skip to: 104527 + /* 1187 */ MCD_OPC_CheckPredicate, + 2, + 167, + 147, + 1, // Skip to: 104527 + /* 1192 */ MCD_OPC_CheckField, + 3, + 2, + 0, + 160, + 147, + 1, // Skip to: 104527 + /* 1199 */ MCD_OPC_Decode, + 183, + 7, + 18, // Opcode: ADDVA_MPPZ_D + /* 1203 */ MCD_OPC_FilterValue, + 7, + 151, + 147, + 1, // Skip to: 104527 + /* 1208 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 1211 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1232 + /* 1216 */ MCD_OPC_CheckPredicate, + 0, + 138, + 147, + 1, // Skip to: 104527 + /* 1221 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 131, + 147, + 1, // Skip to: 104527 + /* 1228 */ MCD_OPC_Decode, + 226, + 22, + 19, // Opcode: LD1_MXIPXX_H_D + /* 1232 */ MCD_OPC_FilterValue, + 1, + 122, + 147, + 1, // Skip to: 104527 + /* 1237 */ MCD_OPC_CheckPredicate, + 0, + 117, + 147, + 1, // Skip to: 104527 + /* 1242 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 110, + 147, + 1, // Skip to: 104527 + /* 1249 */ MCD_OPC_Decode, + 231, + 22, + 19, // Opcode: LD1_MXIPXX_V_D + /* 1253 */ MCD_OPC_FilterValue, + 7, + 96, + 0, + 0, // Skip to: 1354 + /* 1258 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1261 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 1326 + /* 1266 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 1269 */ MCD_OPC_FilterValue, + 5, + 16, + 0, + 0, // Skip to: 1290 + /* 1274 */ MCD_OPC_CheckPredicate, + 2, + 80, + 147, + 1, // Skip to: 104527 + /* 1279 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 73, + 147, + 1, // Skip to: 104527 + /* 1286 */ MCD_OPC_Decode, + 227, + 40, + 13, // Opcode: SUMOPA_MPPZZ_D + /* 1290 */ MCD_OPC_FilterValue, + 7, + 64, + 147, + 1, // Skip to: 104527 + /* 1295 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 1298 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1312 + /* 1303 */ MCD_OPC_CheckPredicate, + 0, + 51, + 147, + 1, // Skip to: 104527 + /* 1308 */ MCD_OPC_Decode, + 176, + 38, + 19, // Opcode: ST1_MXIPXX_H_D + /* 1312 */ MCD_OPC_FilterValue, + 1, + 42, + 147, + 1, // Skip to: 104527 + /* 1317 */ MCD_OPC_CheckPredicate, + 0, + 37, + 147, + 1, // Skip to: 104527 + /* 1322 */ MCD_OPC_Decode, + 181, + 38, + 19, // Opcode: ST1_MXIPXX_V_D + /* 1326 */ MCD_OPC_FilterValue, + 1, + 28, + 147, + 1, // Skip to: 104527 + /* 1331 */ MCD_OPC_CheckPredicate, + 2, + 23, + 147, + 1, // Skip to: 104527 + /* 1336 */ MCD_OPC_CheckField, + 29, + 3, + 5, + 16, + 147, + 1, // Skip to: 104527 + /* 1343 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 9, + 147, + 1, // Skip to: 104527 + /* 1350 */ MCD_OPC_Decode, + 229, + 40, + 13, // Opcode: SUMOPS_MPPZZ_D + /* 1354 */ MCD_OPC_FilterValue, + 8, + 37, + 0, + 0, // Skip to: 1396 + /* 1359 */ MCD_OPC_CheckPredicate, + 0, + 251, + 146, + 1, // Skip to: 104527 + /* 1364 */ MCD_OPC_CheckField, + 29, + 3, + 7, + 244, + 146, + 1, // Skip to: 104527 + /* 1371 */ MCD_OPC_CheckField, + 15, + 6, + 0, + 237, + 146, + 1, // Skip to: 104527 + /* 1378 */ MCD_OPC_CheckField, + 10, + 3, + 0, + 230, + 146, + 1, // Skip to: 104527 + /* 1385 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 223, + 146, + 1, // Skip to: 104527 + /* 1392 */ MCD_OPC_Decode, + 231, + 25, + 20, // Opcode: LDR_ZA + /* 1396 */ MCD_OPC_FilterValue, + 9, + 37, + 0, + 0, // Skip to: 1438 + /* 1401 */ MCD_OPC_CheckPredicate, + 0, + 209, + 146, + 1, // Skip to: 104527 + /* 1406 */ MCD_OPC_CheckField, + 29, + 3, + 7, + 202, + 146, + 1, // Skip to: 104527 + /* 1413 */ MCD_OPC_CheckField, + 15, + 6, + 0, + 195, + 146, + 1, // Skip to: 104527 + /* 1420 */ MCD_OPC_CheckField, + 10, + 3, + 0, + 188, + 146, + 1, // Skip to: 104527 + /* 1427 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 146, + 1, // Skip to: 104527 + /* 1434 */ MCD_OPC_Decode, + 139, + 40, + 20, // Opcode: STR_ZA + /* 1438 */ MCD_OPC_FilterValue, + 12, + 75, + 0, + 0, // Skip to: 1518 + /* 1443 */ MCD_OPC_ExtractField, + 2, + 3, // Inst{4-2} ... + /* 1446 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 1482 + /* 1451 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 1454 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1468 + /* 1459 */ MCD_OPC_CheckPredicate, + 0, + 151, + 146, + 1, // Skip to: 104527 + /* 1464 */ MCD_OPC_Decode, + 153, + 48, + 8, // Opcode: anonymous_5364 + /* 1468 */ MCD_OPC_FilterValue, + 5, + 142, + 146, + 1, // Skip to: 104527 + /* 1473 */ MCD_OPC_CheckPredicate, + 0, + 137, + 146, + 1, // Skip to: 104527 + /* 1478 */ MCD_OPC_Decode, + 186, + 46, + 8, // Opcode: USMOPA_MPPZZ_S + /* 1482 */ MCD_OPC_FilterValue, + 4, + 128, + 146, + 1, // Skip to: 104527 + /* 1487 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 1490 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1504 + /* 1495 */ MCD_OPC_CheckPredicate, + 0, + 115, + 146, + 1, // Skip to: 104527 + /* 1500 */ MCD_OPC_Decode, + 151, + 48, + 8, // Opcode: anonymous_13653 + /* 1504 */ MCD_OPC_FilterValue, + 5, + 106, + 146, + 1, // Skip to: 104527 + /* 1509 */ MCD_OPC_CheckPredicate, + 0, + 101, + 146, + 1, // Skip to: 104527 + /* 1514 */ MCD_OPC_Decode, + 188, + 46, + 8, // Opcode: USMOPS_MPPZZ_S + /* 1518 */ MCD_OPC_FilterValue, + 13, + 75, + 0, + 0, // Skip to: 1598 + /* 1523 */ MCD_OPC_ExtractField, + 2, + 3, // Inst{4-2} ... + /* 1526 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 1562 + /* 1531 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 1534 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1548 + /* 1539 */ MCD_OPC_CheckPredicate, + 0, + 71, + 146, + 1, // Skip to: 104527 + /* 1544 */ MCD_OPC_Decode, + 154, + 48, + 8, // Opcode: anonymous_5365 + /* 1548 */ MCD_OPC_FilterValue, + 5, + 62, + 146, + 1, // Skip to: 104527 + /* 1553 */ MCD_OPC_CheckPredicate, + 0, + 57, + 146, + 1, // Skip to: 104527 + /* 1558 */ MCD_OPC_Decode, + 244, + 43, + 8, // Opcode: UMOPA_MPPZZ_S + /* 1562 */ MCD_OPC_FilterValue, + 4, + 48, + 146, + 1, // Skip to: 104527 + /* 1567 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 1570 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1584 + /* 1575 */ MCD_OPC_CheckPredicate, + 0, + 35, + 146, + 1, // Skip to: 104527 + /* 1580 */ MCD_OPC_Decode, + 152, + 48, + 8, // Opcode: anonymous_13654 + /* 1584 */ MCD_OPC_FilterValue, + 5, + 26, + 146, + 1, // Skip to: 104527 + /* 1589 */ MCD_OPC_CheckPredicate, + 0, + 21, + 146, + 1, // Skip to: 104527 + /* 1594 */ MCD_OPC_Decode, + 246, + 43, + 8, // Opcode: UMOPS_MPPZZ_S + /* 1598 */ MCD_OPC_FilterValue, + 14, + 96, + 0, + 0, // Skip to: 1699 + /* 1603 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1606 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 1671 + /* 1611 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 1614 */ MCD_OPC_FilterValue, + 5, + 16, + 0, + 0, // Skip to: 1635 + /* 1619 */ MCD_OPC_CheckPredicate, + 2, + 247, + 145, + 1, // Skip to: 104527 + /* 1624 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 240, + 145, + 1, // Skip to: 104527 + /* 1631 */ MCD_OPC_Decode, + 185, + 46, + 13, // Opcode: USMOPA_MPPZZ_D + /* 1635 */ MCD_OPC_FilterValue, + 7, + 231, + 145, + 1, // Skip to: 104527 + /* 1640 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 1643 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1657 + /* 1648 */ MCD_OPC_CheckPredicate, + 0, + 218, + 145, + 1, // Skip to: 104527 + /* 1653 */ MCD_OPC_Decode, + 228, + 22, + 21, // Opcode: LD1_MXIPXX_H_Q + /* 1657 */ MCD_OPC_FilterValue, + 1, + 209, + 145, + 1, // Skip to: 104527 + /* 1662 */ MCD_OPC_CheckPredicate, + 0, + 204, + 145, + 1, // Skip to: 104527 + /* 1667 */ MCD_OPC_Decode, + 233, + 22, + 21, // Opcode: LD1_MXIPXX_V_Q + /* 1671 */ MCD_OPC_FilterValue, + 1, + 195, + 145, + 1, // Skip to: 104527 + /* 1676 */ MCD_OPC_CheckPredicate, + 2, + 190, + 145, + 1, // Skip to: 104527 + /* 1681 */ MCD_OPC_CheckField, + 29, + 3, + 5, + 183, + 145, + 1, // Skip to: 104527 + /* 1688 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 176, + 145, + 1, // Skip to: 104527 + /* 1695 */ MCD_OPC_Decode, + 187, + 46, + 13, // Opcode: USMOPS_MPPZZ_D + /* 1699 */ MCD_OPC_FilterValue, + 15, + 167, + 145, + 1, // Skip to: 104527 + /* 1704 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1707 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 1772 + /* 1712 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 1715 */ MCD_OPC_FilterValue, + 5, + 16, + 0, + 0, // Skip to: 1736 + /* 1720 */ MCD_OPC_CheckPredicate, + 2, + 146, + 145, + 1, // Skip to: 104527 + /* 1725 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 139, + 145, + 1, // Skip to: 104527 + /* 1732 */ MCD_OPC_Decode, + 243, + 43, + 13, // Opcode: UMOPA_MPPZZ_D + /* 1736 */ MCD_OPC_FilterValue, + 7, + 130, + 145, + 1, // Skip to: 104527 + /* 1741 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 1744 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1758 + /* 1749 */ MCD_OPC_CheckPredicate, + 0, + 117, + 145, + 1, // Skip to: 104527 + /* 1754 */ MCD_OPC_Decode, + 178, + 38, + 21, // Opcode: ST1_MXIPXX_H_Q + /* 1758 */ MCD_OPC_FilterValue, + 1, + 108, + 145, + 1, // Skip to: 104527 + /* 1763 */ MCD_OPC_CheckPredicate, + 0, + 103, + 145, + 1, // Skip to: 104527 + /* 1768 */ MCD_OPC_Decode, + 183, + 38, + 21, // Opcode: ST1_MXIPXX_V_Q + /* 1772 */ MCD_OPC_FilterValue, + 1, + 94, + 145, + 1, // Skip to: 104527 + /* 1777 */ MCD_OPC_CheckPredicate, + 2, + 89, + 145, + 1, // Skip to: 104527 + /* 1782 */ MCD_OPC_CheckField, + 29, + 3, + 5, + 82, + 145, + 1, // Skip to: 104527 + /* 1789 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 75, + 145, + 1, // Skip to: 104527 + /* 1796 */ MCD_OPC_Decode, + 245, + 43, + 13, // Opcode: UMOPS_MPPZZ_D + /* 1800 */ MCD_OPC_FilterValue, + 1, + 42, + 165, + 0, // Skip to: 44087 + /* 1805 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 1808 */ MCD_OPC_FilterValue, + 0, + 110, + 48, + 0, // Skip to: 14211 + /* 1813 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 1816 */ MCD_OPC_FilterValue, + 0, + 94, + 19, + 0, // Skip to: 6779 + /* 1821 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 1824 */ MCD_OPC_FilterValue, + 0, + 92, + 9, + 0, // Skip to: 4225 + /* 1829 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 1832 */ MCD_OPC_FilterValue, + 0, + 67, + 2, + 0, // Skip to: 2416 + /* 1837 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 1840 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 1876 + /* 1845 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 1848 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1862 + /* 1853 */ MCD_OPC_CheckPredicate, + 3, + 13, + 145, + 1, // Skip to: 104527 + /* 1858 */ MCD_OPC_Decode, + 202, + 7, + 22, // Opcode: ADD_ZPmZ_B + /* 1862 */ MCD_OPC_FilterValue, + 1, + 4, + 145, + 1, // Skip to: 104527 + /* 1867 */ MCD_OPC_CheckPredicate, + 3, + 255, + 144, + 1, // Skip to: 104527 + /* 1872 */ MCD_OPC_Decode, + 204, + 7, + 22, // Opcode: ADD_ZPmZ_H + /* 1876 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 1912 + /* 1881 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 1884 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1898 + /* 1889 */ MCD_OPC_CheckPredicate, + 3, + 233, + 144, + 1, // Skip to: 104527 + /* 1894 */ MCD_OPC_Decode, + 208, + 40, + 22, // Opcode: SUB_ZPmZ_B + /* 1898 */ MCD_OPC_FilterValue, + 1, + 224, + 144, + 1, // Skip to: 104527 + /* 1903 */ MCD_OPC_CheckPredicate, + 3, + 219, + 144, + 1, // Skip to: 104527 + /* 1908 */ MCD_OPC_Decode, + 210, + 40, + 22, // Opcode: SUB_ZPmZ_H + /* 1912 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 1948 + /* 1917 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 1920 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1934 + /* 1925 */ MCD_OPC_CheckPredicate, + 3, + 197, + 144, + 1, // Skip to: 104527 + /* 1930 */ MCD_OPC_Decode, + 186, + 40, + 22, // Opcode: SUBR_ZPmZ_B + /* 1934 */ MCD_OPC_FilterValue, + 1, + 188, + 144, + 1, // Skip to: 104527 + /* 1939 */ MCD_OPC_CheckPredicate, + 3, + 183, + 144, + 1, // Skip to: 104527 + /* 1944 */ MCD_OPC_Decode, + 188, + 40, + 22, // Opcode: SUBR_ZPmZ_H + /* 1948 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 1984 + /* 1953 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 1956 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1970 + /* 1961 */ MCD_OPC_CheckPredicate, + 3, + 161, + 144, + 1, // Skip to: 104527 + /* 1966 */ MCD_OPC_Decode, + 239, + 31, + 22, // Opcode: SMAX_ZPmZ_B + /* 1970 */ MCD_OPC_FilterValue, + 1, + 152, + 144, + 1, // Skip to: 104527 + /* 1975 */ MCD_OPC_CheckPredicate, + 3, + 147, + 144, + 1, // Skip to: 104527 + /* 1980 */ MCD_OPC_Decode, + 241, + 31, + 22, // Opcode: SMAX_ZPmZ_H + /* 1984 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 2020 + /* 1989 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 1992 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2006 + /* 1997 */ MCD_OPC_CheckPredicate, + 3, + 125, + 144, + 1, // Skip to: 104527 + /* 2002 */ MCD_OPC_Decode, + 158, + 43, + 22, // Opcode: UMAX_ZPmZ_B + /* 2006 */ MCD_OPC_FilterValue, + 1, + 116, + 144, + 1, // Skip to: 104527 + /* 2011 */ MCD_OPC_CheckPredicate, + 3, + 111, + 144, + 1, // Skip to: 104527 + /* 2016 */ MCD_OPC_Decode, + 160, + 43, + 22, // Opcode: UMAX_ZPmZ_H + /* 2020 */ MCD_OPC_FilterValue, + 10, + 31, + 0, + 0, // Skip to: 2056 + /* 2025 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2028 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2042 + /* 2033 */ MCD_OPC_CheckPredicate, + 3, + 89, + 144, + 1, // Skip to: 104527 + /* 2038 */ MCD_OPC_Decode, + 145, + 32, + 22, // Opcode: SMIN_ZPmZ_B + /* 2042 */ MCD_OPC_FilterValue, + 1, + 80, + 144, + 1, // Skip to: 104527 + /* 2047 */ MCD_OPC_CheckPredicate, + 3, + 75, + 144, + 1, // Skip to: 104527 + /* 2052 */ MCD_OPC_Decode, + 147, + 32, + 22, // Opcode: SMIN_ZPmZ_H + /* 2056 */ MCD_OPC_FilterValue, + 11, + 31, + 0, + 0, // Skip to: 2092 + /* 2061 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2064 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2078 + /* 2069 */ MCD_OPC_CheckPredicate, + 3, + 53, + 144, + 1, // Skip to: 104527 + /* 2074 */ MCD_OPC_Decode, + 191, + 43, + 22, // Opcode: UMIN_ZPmZ_B + /* 2078 */ MCD_OPC_FilterValue, + 1, + 44, + 144, + 1, // Skip to: 104527 + /* 2083 */ MCD_OPC_CheckPredicate, + 3, + 39, + 144, + 1, // Skip to: 104527 + /* 2088 */ MCD_OPC_Decode, + 193, + 43, + 22, // Opcode: UMIN_ZPmZ_H + /* 2092 */ MCD_OPC_FilterValue, + 12, + 31, + 0, + 0, // Skip to: 2128 + /* 2097 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2100 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2114 + /* 2105 */ MCD_OPC_CheckPredicate, + 3, + 17, + 144, + 1, // Skip to: 104527 + /* 2110 */ MCD_OPC_Decode, + 252, + 29, + 22, // Opcode: SABD_ZPmZ_B + /* 2114 */ MCD_OPC_FilterValue, + 1, + 8, + 144, + 1, // Skip to: 104527 + /* 2119 */ MCD_OPC_CheckPredicate, + 3, + 3, + 144, + 1, // Skip to: 104527 + /* 2124 */ MCD_OPC_Decode, + 254, + 29, + 22, // Opcode: SABD_ZPmZ_H + /* 2128 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 2164 + /* 2133 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2136 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2150 + /* 2141 */ MCD_OPC_CheckPredicate, + 3, + 237, + 143, + 1, // Skip to: 104527 + /* 2146 */ MCD_OPC_Decode, + 252, + 41, + 22, // Opcode: UABD_ZPmZ_B + /* 2150 */ MCD_OPC_FilterValue, + 1, + 228, + 143, + 1, // Skip to: 104527 + /* 2155 */ MCD_OPC_CheckPredicate, + 3, + 223, + 143, + 1, // Skip to: 104527 + /* 2160 */ MCD_OPC_Decode, + 254, + 41, + 22, // Opcode: UABD_ZPmZ_H + /* 2164 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 2200 + /* 2169 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2172 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2186 + /* 2177 */ MCD_OPC_CheckPredicate, + 3, + 201, + 143, + 1, // Skip to: 104527 + /* 2182 */ MCD_OPC_Decode, + 216, + 27, + 22, // Opcode: MUL_ZPmZ_B + /* 2186 */ MCD_OPC_FilterValue, + 1, + 192, + 143, + 1, // Skip to: 104527 + /* 2191 */ MCD_OPC_CheckPredicate, + 3, + 187, + 143, + 1, // Skip to: 104527 + /* 2196 */ MCD_OPC_Decode, + 218, + 27, + 22, // Opcode: MUL_ZPmZ_H + /* 2200 */ MCD_OPC_FilterValue, + 18, + 31, + 0, + 0, // Skip to: 2236 + /* 2205 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2208 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2222 + /* 2213 */ MCD_OPC_CheckPredicate, + 3, + 165, + 143, + 1, // Skip to: 104527 + /* 2218 */ MCD_OPC_Decode, + 212, + 32, + 22, // Opcode: SMULH_ZPmZ_B + /* 2222 */ MCD_OPC_FilterValue, + 1, + 156, + 143, + 1, // Skip to: 104527 + /* 2227 */ MCD_OPC_CheckPredicate, + 3, + 151, + 143, + 1, // Skip to: 104527 + /* 2232 */ MCD_OPC_Decode, + 214, + 32, + 22, // Opcode: SMULH_ZPmZ_H + /* 2236 */ MCD_OPC_FilterValue, + 19, + 31, + 0, + 0, // Skip to: 2272 + /* 2241 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2244 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2258 + /* 2249 */ MCD_OPC_CheckPredicate, + 3, + 129, + 143, + 1, // Skip to: 104527 + /* 2254 */ MCD_OPC_Decode, + 128, + 44, + 22, // Opcode: UMULH_ZPmZ_B + /* 2258 */ MCD_OPC_FilterValue, + 1, + 120, + 143, + 1, // Skip to: 104527 + /* 2263 */ MCD_OPC_CheckPredicate, + 3, + 115, + 143, + 1, // Skip to: 104527 + /* 2268 */ MCD_OPC_Decode, + 130, + 44, + 22, // Opcode: UMULH_ZPmZ_H + /* 2272 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 2308 + /* 2277 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2280 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2294 + /* 2285 */ MCD_OPC_CheckPredicate, + 3, + 93, + 143, + 1, // Skip to: 104527 + /* 2290 */ MCD_OPC_Decode, + 153, + 28, + 22, // Opcode: ORR_ZPmZ_B + /* 2294 */ MCD_OPC_FilterValue, + 1, + 84, + 143, + 1, // Skip to: 104527 + /* 2299 */ MCD_OPC_CheckPredicate, + 3, + 79, + 143, + 1, // Skip to: 104527 + /* 2304 */ MCD_OPC_Decode, + 155, + 28, + 22, // Opcode: ORR_ZPmZ_H + /* 2308 */ MCD_OPC_FilterValue, + 25, + 31, + 0, + 0, // Skip to: 2344 + /* 2313 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2316 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2330 + /* 2321 */ MCD_OPC_CheckPredicate, + 3, + 57, + 143, + 1, // Skip to: 104527 + /* 2326 */ MCD_OPC_Decode, + 174, + 12, + 22, // Opcode: EOR_ZPmZ_B + /* 2330 */ MCD_OPC_FilterValue, + 1, + 48, + 143, + 1, // Skip to: 104527 + /* 2335 */ MCD_OPC_CheckPredicate, + 3, + 43, + 143, + 1, // Skip to: 104527 + /* 2340 */ MCD_OPC_Decode, + 176, + 12, + 22, // Opcode: EOR_ZPmZ_H + /* 2344 */ MCD_OPC_FilterValue, + 26, + 31, + 0, + 0, // Skip to: 2380 + /* 2349 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2352 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2366 + /* 2357 */ MCD_OPC_CheckPredicate, + 3, + 21, + 143, + 1, // Skip to: 104527 + /* 2362 */ MCD_OPC_Decode, + 131, + 8, + 22, // Opcode: AND_ZPmZ_B + /* 2366 */ MCD_OPC_FilterValue, + 1, + 12, + 143, + 1, // Skip to: 104527 + /* 2371 */ MCD_OPC_CheckPredicate, + 3, + 7, + 143, + 1, // Skip to: 104527 + /* 2376 */ MCD_OPC_Decode, + 133, + 8, + 22, // Opcode: AND_ZPmZ_H + /* 2380 */ MCD_OPC_FilterValue, + 27, + 254, + 142, + 1, // Skip to: 104527 + /* 2385 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2388 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2402 + /* 2393 */ MCD_OPC_CheckPredicate, + 3, + 241, + 142, + 1, // Skip to: 104527 + /* 2398 */ MCD_OPC_Decode, + 225, + 8, + 22, // Opcode: BIC_ZPmZ_B + /* 2402 */ MCD_OPC_FilterValue, + 1, + 232, + 142, + 1, // Skip to: 104527 + /* 2407 */ MCD_OPC_CheckPredicate, + 3, + 227, + 142, + 1, // Skip to: 104527 + /* 2412 */ MCD_OPC_Decode, + 227, + 8, + 22, // Opcode: BIC_ZPmZ_H + /* 2416 */ MCD_OPC_FilterValue, + 1, + 143, + 1, + 0, // Skip to: 2820 + /* 2421 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 2424 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 2460 + /* 2429 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2432 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2446 + /* 2437 */ MCD_OPC_CheckPredicate, + 3, + 197, + 142, + 1, // Skip to: 104527 + /* 2442 */ MCD_OPC_Decode, + 169, + 30, + 23, // Opcode: SADDV_VPZ_B + /* 2446 */ MCD_OPC_FilterValue, + 1, + 188, + 142, + 1, // Skip to: 104527 + /* 2451 */ MCD_OPC_CheckPredicate, + 3, + 183, + 142, + 1, // Skip to: 104527 + /* 2456 */ MCD_OPC_Decode, + 170, + 30, + 23, // Opcode: SADDV_VPZ_H + /* 2460 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 2496 + /* 2465 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2468 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2482 + /* 2473 */ MCD_OPC_CheckPredicate, + 3, + 161, + 142, + 1, // Skip to: 104527 + /* 2478 */ MCD_OPC_Decode, + 166, + 42, + 23, // Opcode: UADDV_VPZ_B + /* 2482 */ MCD_OPC_FilterValue, + 1, + 152, + 142, + 1, // Skip to: 104527 + /* 2487 */ MCD_OPC_CheckPredicate, + 3, + 147, + 142, + 1, // Skip to: 104527 + /* 2492 */ MCD_OPC_Decode, + 168, + 42, + 23, // Opcode: UADDV_VPZ_H + /* 2496 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 2532 + /* 2501 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2504 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2518 + /* 2509 */ MCD_OPC_CheckPredicate, + 3, + 125, + 142, + 1, // Skip to: 104527 + /* 2514 */ MCD_OPC_Decode, + 226, + 31, + 23, // Opcode: SMAXV_VPZ_B + /* 2518 */ MCD_OPC_FilterValue, + 1, + 116, + 142, + 1, // Skip to: 104527 + /* 2523 */ MCD_OPC_CheckPredicate, + 3, + 111, + 142, + 1, // Skip to: 104527 + /* 2528 */ MCD_OPC_Decode, + 228, + 31, + 23, // Opcode: SMAXV_VPZ_H + /* 2532 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 2568 + /* 2537 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2540 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2554 + /* 2545 */ MCD_OPC_CheckPredicate, + 3, + 89, + 142, + 1, // Skip to: 104527 + /* 2550 */ MCD_OPC_Decode, + 145, + 43, + 23, // Opcode: UMAXV_VPZ_B + /* 2554 */ MCD_OPC_FilterValue, + 1, + 80, + 142, + 1, // Skip to: 104527 + /* 2559 */ MCD_OPC_CheckPredicate, + 3, + 75, + 142, + 1, // Skip to: 104527 + /* 2564 */ MCD_OPC_Decode, + 147, + 43, + 23, // Opcode: UMAXV_VPZ_H + /* 2568 */ MCD_OPC_FilterValue, + 10, + 31, + 0, + 0, // Skip to: 2604 + /* 2573 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2576 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2590 + /* 2581 */ MCD_OPC_CheckPredicate, + 3, + 53, + 142, + 1, // Skip to: 104527 + /* 2586 */ MCD_OPC_Decode, + 132, + 32, + 23, // Opcode: SMINV_VPZ_B + /* 2590 */ MCD_OPC_FilterValue, + 1, + 44, + 142, + 1, // Skip to: 104527 + /* 2595 */ MCD_OPC_CheckPredicate, + 3, + 39, + 142, + 1, // Skip to: 104527 + /* 2600 */ MCD_OPC_Decode, + 134, + 32, + 23, // Opcode: SMINV_VPZ_H + /* 2604 */ MCD_OPC_FilterValue, + 11, + 31, + 0, + 0, // Skip to: 2640 + /* 2609 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2612 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2626 + /* 2617 */ MCD_OPC_CheckPredicate, + 3, + 17, + 142, + 1, // Skip to: 104527 + /* 2622 */ MCD_OPC_Decode, + 178, + 43, + 23, // Opcode: UMINV_VPZ_B + /* 2626 */ MCD_OPC_FilterValue, + 1, + 8, + 142, + 1, // Skip to: 104527 + /* 2631 */ MCD_OPC_CheckPredicate, + 3, + 3, + 142, + 1, // Skip to: 104527 + /* 2636 */ MCD_OPC_Decode, + 180, + 43, + 23, // Opcode: UMINV_VPZ_H + /* 2640 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 2676 + /* 2645 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2648 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2662 + /* 2653 */ MCD_OPC_CheckPredicate, + 3, + 237, + 141, + 1, // Skip to: 104527 + /* 2658 */ MCD_OPC_Decode, + 194, + 27, + 23, // Opcode: MOVPRFX_ZPzZ_B + /* 2662 */ MCD_OPC_FilterValue, + 1, + 228, + 141, + 1, // Skip to: 104527 + /* 2667 */ MCD_OPC_CheckPredicate, + 3, + 223, + 141, + 1, // Skip to: 104527 + /* 2672 */ MCD_OPC_Decode, + 196, + 27, + 23, // Opcode: MOVPRFX_ZPzZ_H + /* 2676 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 2712 + /* 2681 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2684 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2698 + /* 2689 */ MCD_OPC_CheckPredicate, + 3, + 201, + 141, + 1, // Skip to: 104527 + /* 2694 */ MCD_OPC_Decode, + 190, + 27, + 24, // Opcode: MOVPRFX_ZPmZ_B + /* 2698 */ MCD_OPC_FilterValue, + 1, + 192, + 141, + 1, // Skip to: 104527 + /* 2703 */ MCD_OPC_CheckPredicate, + 3, + 187, + 141, + 1, // Skip to: 104527 + /* 2708 */ MCD_OPC_Decode, + 192, + 27, + 24, // Opcode: MOVPRFX_ZPmZ_H + /* 2712 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 2748 + /* 2717 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2720 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2734 + /* 2725 */ MCD_OPC_CheckPredicate, + 3, + 165, + 141, + 1, // Skip to: 104527 + /* 2730 */ MCD_OPC_Decode, + 164, + 28, + 23, // Opcode: ORV_VPZ_B + /* 2734 */ MCD_OPC_FilterValue, + 1, + 156, + 141, + 1, // Skip to: 104527 + /* 2739 */ MCD_OPC_CheckPredicate, + 3, + 151, + 141, + 1, // Skip to: 104527 + /* 2744 */ MCD_OPC_Decode, + 166, + 28, + 23, // Opcode: ORV_VPZ_H + /* 2748 */ MCD_OPC_FilterValue, + 25, + 31, + 0, + 0, // Skip to: 2784 + /* 2753 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2756 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2770 + /* 2761 */ MCD_OPC_CheckPredicate, + 3, + 129, + 141, + 1, // Skip to: 104527 + /* 2766 */ MCD_OPC_Decode, + 164, + 12, + 23, // Opcode: EORV_VPZ_B + /* 2770 */ MCD_OPC_FilterValue, + 1, + 120, + 141, + 1, // Skip to: 104527 + /* 2775 */ MCD_OPC_CheckPredicate, + 3, + 115, + 141, + 1, // Skip to: 104527 + /* 2780 */ MCD_OPC_Decode, + 166, + 12, + 23, // Opcode: EORV_VPZ_H + /* 2784 */ MCD_OPC_FilterValue, + 26, + 106, + 141, + 1, // Skip to: 104527 + /* 2789 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2792 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2806 + /* 2797 */ MCD_OPC_CheckPredicate, + 3, + 93, + 141, + 1, // Skip to: 104527 + /* 2802 */ MCD_OPC_Decode, + 249, + 7, + 23, // Opcode: ANDV_VPZ_B + /* 2806 */ MCD_OPC_FilterValue, + 1, + 84, + 141, + 1, // Skip to: 104527 + /* 2811 */ MCD_OPC_CheckPredicate, + 3, + 79, + 141, + 1, // Skip to: 104527 + /* 2816 */ MCD_OPC_Decode, + 251, + 7, + 23, // Opcode: ANDV_VPZ_H + /* 2820 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 2856 + /* 2825 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2828 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2842 + /* 2833 */ MCD_OPC_CheckPredicate, + 3, + 57, + 141, + 1, // Skip to: 104527 + /* 2838 */ MCD_OPC_Decode, + 142, + 27, + 25, // Opcode: MLA_ZPmZZ_B + /* 2842 */ MCD_OPC_FilterValue, + 1, + 48, + 141, + 1, // Skip to: 104527 + /* 2847 */ MCD_OPC_CheckPredicate, + 3, + 43, + 141, + 1, // Skip to: 104527 + /* 2852 */ MCD_OPC_Decode, + 144, + 27, + 25, // Opcode: MLA_ZPmZZ_H + /* 2856 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 2892 + /* 2861 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2864 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2878 + /* 2869 */ MCD_OPC_CheckPredicate, + 3, + 21, + 141, + 1, // Skip to: 104527 + /* 2874 */ MCD_OPC_Decode, + 159, + 27, + 25, // Opcode: MLS_ZPmZZ_B + /* 2878 */ MCD_OPC_FilterValue, + 1, + 12, + 141, + 1, // Skip to: 104527 + /* 2883 */ MCD_OPC_CheckPredicate, + 3, + 7, + 141, + 1, // Skip to: 104527 + /* 2888 */ MCD_OPC_Decode, + 161, + 27, + 25, // Opcode: MLS_ZPmZZ_H + /* 2892 */ MCD_OPC_FilterValue, + 4, + 144, + 3, + 0, // Skip to: 3809 + /* 2897 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 2900 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 2965 + /* 2905 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2908 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 2951 + /* 2913 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 2916 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 2937 + /* 2921 */ MCD_OPC_CheckPredicate, + 3, + 225, + 140, + 1, // Skip to: 104527 + /* 2926 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 218, + 140, + 1, // Skip to: 104527 + /* 2933 */ MCD_OPC_Decode, + 154, + 8, + 26, // Opcode: ASR_ZPmI_B + /* 2937 */ MCD_OPC_FilterValue, + 1, + 209, + 140, + 1, // Skip to: 104527 + /* 2942 */ MCD_OPC_CheckPredicate, + 3, + 204, + 140, + 1, // Skip to: 104527 + /* 2947 */ MCD_OPC_Decode, + 156, + 8, + 27, // Opcode: ASR_ZPmI_H + /* 2951 */ MCD_OPC_FilterValue, + 1, + 195, + 140, + 1, // Skip to: 104527 + /* 2956 */ MCD_OPC_CheckPredicate, + 3, + 190, + 140, + 1, // Skip to: 104527 + /* 2961 */ MCD_OPC_Decode, + 157, + 8, + 28, // Opcode: ASR_ZPmI_S + /* 2965 */ MCD_OPC_FilterValue, + 1, + 60, + 0, + 0, // Skip to: 3030 + /* 2970 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2973 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3016 + /* 2978 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 2981 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3002 + /* 2986 */ MCD_OPC_CheckPredicate, + 3, + 160, + 140, + 1, // Skip to: 104527 + /* 2991 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 153, + 140, + 1, // Skip to: 104527 + /* 2998 */ MCD_OPC_Decode, + 250, + 26, + 26, // Opcode: LSR_ZPmI_B + /* 3002 */ MCD_OPC_FilterValue, + 1, + 144, + 140, + 1, // Skip to: 104527 + /* 3007 */ MCD_OPC_CheckPredicate, + 3, + 139, + 140, + 1, // Skip to: 104527 + /* 3012 */ MCD_OPC_Decode, + 252, + 26, + 27, // Opcode: LSR_ZPmI_H + /* 3016 */ MCD_OPC_FilterValue, + 1, + 130, + 140, + 1, // Skip to: 104527 + /* 3021 */ MCD_OPC_CheckPredicate, + 3, + 125, + 140, + 1, // Skip to: 104527 + /* 3026 */ MCD_OPC_Decode, + 253, + 26, + 28, // Opcode: LSR_ZPmI_S + /* 3030 */ MCD_OPC_FilterValue, + 3, + 60, + 0, + 0, // Skip to: 3095 + /* 3035 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3038 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3081 + /* 3043 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 3046 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3067 + /* 3051 */ MCD_OPC_CheckPredicate, + 3, + 95, + 140, + 1, // Skip to: 104527 + /* 3056 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 88, + 140, + 1, // Skip to: 104527 + /* 3063 */ MCD_OPC_Decode, + 226, + 26, + 29, // Opcode: LSL_ZPmI_B + /* 3067 */ MCD_OPC_FilterValue, + 1, + 79, + 140, + 1, // Skip to: 104527 + /* 3072 */ MCD_OPC_CheckPredicate, + 3, + 74, + 140, + 1, // Skip to: 104527 + /* 3077 */ MCD_OPC_Decode, + 228, + 26, + 30, // Opcode: LSL_ZPmI_H + /* 3081 */ MCD_OPC_FilterValue, + 1, + 65, + 140, + 1, // Skip to: 104527 + /* 3086 */ MCD_OPC_CheckPredicate, + 3, + 60, + 140, + 1, // Skip to: 104527 + /* 3091 */ MCD_OPC_Decode, + 229, + 26, + 31, // Opcode: LSL_ZPmI_S + /* 3095 */ MCD_OPC_FilterValue, + 4, + 60, + 0, + 0, // Skip to: 3160 + /* 3100 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3103 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3146 + /* 3108 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 3111 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3132 + /* 3116 */ MCD_OPC_CheckPredicate, + 3, + 30, + 140, + 1, // Skip to: 104527 + /* 3121 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 23, + 140, + 1, // Skip to: 104527 + /* 3128 */ MCD_OPC_Decode, + 138, + 8, + 26, // Opcode: ASRD_ZPmI_B + /* 3132 */ MCD_OPC_FilterValue, + 1, + 14, + 140, + 1, // Skip to: 104527 + /* 3137 */ MCD_OPC_CheckPredicate, + 3, + 9, + 140, + 1, // Skip to: 104527 + /* 3142 */ MCD_OPC_Decode, + 140, + 8, + 27, // Opcode: ASRD_ZPmI_H + /* 3146 */ MCD_OPC_FilterValue, + 1, + 0, + 140, + 1, // Skip to: 104527 + /* 3151 */ MCD_OPC_CheckPredicate, + 3, + 251, + 139, + 1, // Skip to: 104527 + /* 3156 */ MCD_OPC_Decode, + 141, + 8, + 28, // Opcode: ASRD_ZPmI_S + /* 3160 */ MCD_OPC_FilterValue, + 6, + 60, + 0, + 0, // Skip to: 3225 + /* 3165 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3168 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3211 + /* 3173 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 3176 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3197 + /* 3181 */ MCD_OPC_CheckPredicate, + 4, + 221, + 139, + 1, // Skip to: 104527 + /* 3186 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 214, + 139, + 1, // Skip to: 104527 + /* 3193 */ MCD_OPC_Decode, + 188, + 35, + 29, // Opcode: SQSHL_ZPmI_B + /* 3197 */ MCD_OPC_FilterValue, + 1, + 205, + 139, + 1, // Skip to: 104527 + /* 3202 */ MCD_OPC_CheckPredicate, + 4, + 200, + 139, + 1, // Skip to: 104527 + /* 3207 */ MCD_OPC_Decode, + 190, + 35, + 30, // Opcode: SQSHL_ZPmI_H + /* 3211 */ MCD_OPC_FilterValue, + 1, + 191, + 139, + 1, // Skip to: 104527 + /* 3216 */ MCD_OPC_CheckPredicate, + 4, + 186, + 139, + 1, // Skip to: 104527 + /* 3221 */ MCD_OPC_Decode, + 191, + 35, + 31, // Opcode: SQSHL_ZPmI_S + /* 3225 */ MCD_OPC_FilterValue, + 7, + 60, + 0, + 0, // Skip to: 3290 + /* 3230 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3233 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3276 + /* 3238 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 3241 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3262 + /* 3246 */ MCD_OPC_CheckPredicate, + 4, + 156, + 139, + 1, // Skip to: 104527 + /* 3251 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 149, + 139, + 1, // Skip to: 104527 + /* 3258 */ MCD_OPC_Decode, + 134, + 45, + 29, // Opcode: UQSHL_ZPmI_B + /* 3262 */ MCD_OPC_FilterValue, + 1, + 140, + 139, + 1, // Skip to: 104527 + /* 3267 */ MCD_OPC_CheckPredicate, + 4, + 135, + 139, + 1, // Skip to: 104527 + /* 3272 */ MCD_OPC_Decode, + 136, + 45, + 30, // Opcode: UQSHL_ZPmI_H + /* 3276 */ MCD_OPC_FilterValue, + 1, + 126, + 139, + 1, // Skip to: 104527 + /* 3281 */ MCD_OPC_CheckPredicate, + 4, + 121, + 139, + 1, // Skip to: 104527 + /* 3286 */ MCD_OPC_Decode, + 137, + 45, + 31, // Opcode: UQSHL_ZPmI_S + /* 3290 */ MCD_OPC_FilterValue, + 12, + 60, + 0, + 0, // Skip to: 3355 + /* 3295 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3298 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3341 + /* 3303 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 3306 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3327 + /* 3311 */ MCD_OPC_CheckPredicate, + 4, + 91, + 139, + 1, // Skip to: 104527 + /* 3316 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 84, + 139, + 1, // Skip to: 104527 + /* 3323 */ MCD_OPC_Decode, + 215, + 36, + 26, // Opcode: SRSHR_ZPmI_B + /* 3327 */ MCD_OPC_FilterValue, + 1, + 75, + 139, + 1, // Skip to: 104527 + /* 3332 */ MCD_OPC_CheckPredicate, + 4, + 70, + 139, + 1, // Skip to: 104527 + /* 3337 */ MCD_OPC_Decode, + 217, + 36, + 27, // Opcode: SRSHR_ZPmI_H + /* 3341 */ MCD_OPC_FilterValue, + 1, + 61, + 139, + 1, // Skip to: 104527 + /* 3346 */ MCD_OPC_CheckPredicate, + 4, + 56, + 139, + 1, // Skip to: 104527 + /* 3351 */ MCD_OPC_Decode, + 218, + 36, + 28, // Opcode: SRSHR_ZPmI_S + /* 3355 */ MCD_OPC_FilterValue, + 13, + 60, + 0, + 0, // Skip to: 3420 + /* 3360 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3363 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3406 + /* 3368 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 3371 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3392 + /* 3376 */ MCD_OPC_CheckPredicate, + 4, + 26, + 139, + 1, // Skip to: 104527 + /* 3381 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 19, + 139, + 1, // Skip to: 104527 + /* 3388 */ MCD_OPC_Decode, + 250, + 45, + 26, // Opcode: URSHR_ZPmI_B + /* 3392 */ MCD_OPC_FilterValue, + 1, + 10, + 139, + 1, // Skip to: 104527 + /* 3397 */ MCD_OPC_CheckPredicate, + 4, + 5, + 139, + 1, // Skip to: 104527 + /* 3402 */ MCD_OPC_Decode, + 252, + 45, + 27, // Opcode: URSHR_ZPmI_H + /* 3406 */ MCD_OPC_FilterValue, + 1, + 252, + 138, + 1, // Skip to: 104527 + /* 3411 */ MCD_OPC_CheckPredicate, + 4, + 247, + 138, + 1, // Skip to: 104527 + /* 3416 */ MCD_OPC_Decode, + 253, + 45, + 28, // Opcode: URSHR_ZPmI_S + /* 3420 */ MCD_OPC_FilterValue, + 15, + 60, + 0, + 0, // Skip to: 3485 + /* 3425 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3428 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3471 + /* 3433 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 3436 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3457 + /* 3441 */ MCD_OPC_CheckPredicate, + 4, + 217, + 138, + 1, // Skip to: 104527 + /* 3446 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 210, + 138, + 1, // Skip to: 104527 + /* 3453 */ MCD_OPC_Decode, + 173, + 35, + 29, // Opcode: SQSHLU_ZPmI_B + /* 3457 */ MCD_OPC_FilterValue, + 1, + 201, + 138, + 1, // Skip to: 104527 + /* 3462 */ MCD_OPC_CheckPredicate, + 4, + 196, + 138, + 1, // Skip to: 104527 + /* 3467 */ MCD_OPC_Decode, + 175, + 35, + 30, // Opcode: SQSHLU_ZPmI_H + /* 3471 */ MCD_OPC_FilterValue, + 1, + 187, + 138, + 1, // Skip to: 104527 + /* 3476 */ MCD_OPC_CheckPredicate, + 4, + 182, + 138, + 1, // Skip to: 104527 + /* 3481 */ MCD_OPC_Decode, + 176, + 35, + 31, // Opcode: SQSHLU_ZPmI_S + /* 3485 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 3521 + /* 3490 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3493 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3507 + /* 3498 */ MCD_OPC_CheckPredicate, + 3, + 160, + 138, + 1, // Skip to: 104527 + /* 3503 */ MCD_OPC_Decode, + 158, + 8, + 22, // Opcode: ASR_ZPmZ_B + /* 3507 */ MCD_OPC_FilterValue, + 1, + 151, + 138, + 1, // Skip to: 104527 + /* 3512 */ MCD_OPC_CheckPredicate, + 3, + 146, + 138, + 1, // Skip to: 104527 + /* 3517 */ MCD_OPC_Decode, + 160, + 8, + 22, // Opcode: ASR_ZPmZ_H + /* 3521 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 3557 + /* 3526 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3529 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3543 + /* 3534 */ MCD_OPC_CheckPredicate, + 3, + 124, + 138, + 1, // Skip to: 104527 + /* 3539 */ MCD_OPC_Decode, + 254, + 26, + 22, // Opcode: LSR_ZPmZ_B + /* 3543 */ MCD_OPC_FilterValue, + 1, + 115, + 138, + 1, // Skip to: 104527 + /* 3548 */ MCD_OPC_CheckPredicate, + 3, + 110, + 138, + 1, // Skip to: 104527 + /* 3553 */ MCD_OPC_Decode, + 128, + 27, + 22, // Opcode: LSR_ZPmZ_H + /* 3557 */ MCD_OPC_FilterValue, + 19, + 31, + 0, + 0, // Skip to: 3593 + /* 3562 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3565 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3579 + /* 3570 */ MCD_OPC_CheckPredicate, + 3, + 88, + 138, + 1, // Skip to: 104527 + /* 3575 */ MCD_OPC_Decode, + 230, + 26, + 22, // Opcode: LSL_ZPmZ_B + /* 3579 */ MCD_OPC_FilterValue, + 1, + 79, + 138, + 1, // Skip to: 104527 + /* 3584 */ MCD_OPC_CheckPredicate, + 3, + 74, + 138, + 1, // Skip to: 104527 + /* 3589 */ MCD_OPC_Decode, + 232, + 26, + 22, // Opcode: LSL_ZPmZ_H + /* 3593 */ MCD_OPC_FilterValue, + 20, + 31, + 0, + 0, // Skip to: 3629 + /* 3598 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3601 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3615 + /* 3606 */ MCD_OPC_CheckPredicate, + 3, + 52, + 138, + 1, // Skip to: 104527 + /* 3611 */ MCD_OPC_Decode, + 142, + 8, + 22, // Opcode: ASRR_ZPmZ_B + /* 3615 */ MCD_OPC_FilterValue, + 1, + 43, + 138, + 1, // Skip to: 104527 + /* 3620 */ MCD_OPC_CheckPredicate, + 3, + 38, + 138, + 1, // Skip to: 104527 + /* 3625 */ MCD_OPC_Decode, + 144, + 8, + 22, // Opcode: ASRR_ZPmZ_H + /* 3629 */ MCD_OPC_FilterValue, + 21, + 31, + 0, + 0, // Skip to: 3665 + /* 3634 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3637 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3651 + /* 3642 */ MCD_OPC_CheckPredicate, + 3, + 16, + 138, + 1, // Skip to: 104527 + /* 3647 */ MCD_OPC_Decode, + 238, + 26, + 22, // Opcode: LSRR_ZPmZ_B + /* 3651 */ MCD_OPC_FilterValue, + 1, + 7, + 138, + 1, // Skip to: 104527 + /* 3656 */ MCD_OPC_CheckPredicate, + 3, + 2, + 138, + 1, // Skip to: 104527 + /* 3661 */ MCD_OPC_Decode, + 240, + 26, + 22, // Opcode: LSRR_ZPmZ_H + /* 3665 */ MCD_OPC_FilterValue, + 23, + 31, + 0, + 0, // Skip to: 3701 + /* 3670 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3673 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3687 + /* 3678 */ MCD_OPC_CheckPredicate, + 3, + 236, + 137, + 1, // Skip to: 104527 + /* 3683 */ MCD_OPC_Decode, + 214, + 26, + 22, // Opcode: LSLR_ZPmZ_B + /* 3687 */ MCD_OPC_FilterValue, + 1, + 227, + 137, + 1, // Skip to: 104527 + /* 3692 */ MCD_OPC_CheckPredicate, + 3, + 222, + 137, + 1, // Skip to: 104527 + /* 3697 */ MCD_OPC_Decode, + 216, + 26, + 22, // Opcode: LSLR_ZPmZ_H + /* 3701 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 3737 + /* 3706 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3709 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3723 + /* 3714 */ MCD_OPC_CheckPredicate, + 3, + 200, + 137, + 1, // Skip to: 104527 + /* 3719 */ MCD_OPC_Decode, + 148, + 8, + 22, // Opcode: ASR_WIDE_ZPmZ_B + /* 3723 */ MCD_OPC_FilterValue, + 1, + 191, + 137, + 1, // Skip to: 104527 + /* 3728 */ MCD_OPC_CheckPredicate, + 3, + 186, + 137, + 1, // Skip to: 104527 + /* 3733 */ MCD_OPC_Decode, + 149, + 8, + 22, // Opcode: ASR_WIDE_ZPmZ_H + /* 3737 */ MCD_OPC_FilterValue, + 25, + 31, + 0, + 0, // Skip to: 3773 + /* 3742 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3745 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3759 + /* 3750 */ MCD_OPC_CheckPredicate, + 3, + 164, + 137, + 1, // Skip to: 104527 + /* 3755 */ MCD_OPC_Decode, + 244, + 26, + 22, // Opcode: LSR_WIDE_ZPmZ_B + /* 3759 */ MCD_OPC_FilterValue, + 1, + 155, + 137, + 1, // Skip to: 104527 + /* 3764 */ MCD_OPC_CheckPredicate, + 3, + 150, + 137, + 1, // Skip to: 104527 + /* 3769 */ MCD_OPC_Decode, + 245, + 26, + 22, // Opcode: LSR_WIDE_ZPmZ_H + /* 3773 */ MCD_OPC_FilterValue, + 27, + 141, + 137, + 1, // Skip to: 104527 + /* 3778 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3781 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3795 + /* 3786 */ MCD_OPC_CheckPredicate, + 3, + 128, + 137, + 1, // Skip to: 104527 + /* 3791 */ MCD_OPC_Decode, + 220, + 26, + 22, // Opcode: LSL_WIDE_ZPmZ_B + /* 3795 */ MCD_OPC_FilterValue, + 1, + 119, + 137, + 1, // Skip to: 104527 + /* 3800 */ MCD_OPC_CheckPredicate, + 3, + 114, + 137, + 1, // Skip to: 104527 + /* 3805 */ MCD_OPC_Decode, + 221, + 26, + 22, // Opcode: LSL_WIDE_ZPmZ_H + /* 3809 */ MCD_OPC_FilterValue, + 5, + 83, + 1, + 0, // Skip to: 4153 + /* 3814 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 3817 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 3838 + /* 3822 */ MCD_OPC_CheckPredicate, + 3, + 92, + 137, + 1, // Skip to: 104527 + /* 3827 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 85, + 137, + 1, // Skip to: 104527 + /* 3834 */ MCD_OPC_Decode, + 142, + 41, + 24, // Opcode: SXTB_ZPmZ_H + /* 3838 */ MCD_OPC_FilterValue, + 17, + 16, + 0, + 0, // Skip to: 3859 + /* 3843 */ MCD_OPC_CheckPredicate, + 3, + 71, + 137, + 1, // Skip to: 104527 + /* 3848 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 64, + 137, + 1, // Skip to: 104527 + /* 3855 */ MCD_OPC_Decode, + 247, + 46, + 24, // Opcode: UXTB_ZPmZ_H + /* 3859 */ MCD_OPC_FilterValue, + 22, + 31, + 0, + 0, // Skip to: 3895 + /* 3864 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3867 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3881 + /* 3872 */ MCD_OPC_CheckPredicate, + 3, + 42, + 137, + 1, // Skip to: 104527 + /* 3877 */ MCD_OPC_Decode, + 128, + 7, + 24, // Opcode: ABS_ZPmZ_B + /* 3881 */ MCD_OPC_FilterValue, + 1, + 33, + 137, + 1, // Skip to: 104527 + /* 3886 */ MCD_OPC_CheckPredicate, + 3, + 28, + 137, + 1, // Skip to: 104527 + /* 3891 */ MCD_OPC_Decode, + 130, + 7, + 24, // Opcode: ABS_ZPmZ_H + /* 3895 */ MCD_OPC_FilterValue, + 23, + 31, + 0, + 0, // Skip to: 3931 + /* 3900 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3903 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3917 + /* 3908 */ MCD_OPC_CheckPredicate, + 3, + 6, + 137, + 1, // Skip to: 104527 + /* 3913 */ MCD_OPC_Decode, + 246, + 27, + 24, // Opcode: NEG_ZPmZ_B + /* 3917 */ MCD_OPC_FilterValue, + 1, + 253, + 136, + 1, // Skip to: 104527 + /* 3922 */ MCD_OPC_CheckPredicate, + 3, + 248, + 136, + 1, // Skip to: 104527 + /* 3927 */ MCD_OPC_Decode, + 248, + 27, + 24, // Opcode: NEG_ZPmZ_H + /* 3931 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 3967 + /* 3936 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3939 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3953 + /* 3944 */ MCD_OPC_CheckPredicate, + 3, + 226, + 136, + 1, // Skip to: 104527 + /* 3949 */ MCD_OPC_Decode, + 216, + 9, + 24, // Opcode: CLS_ZPmZ_B + /* 3953 */ MCD_OPC_FilterValue, + 1, + 217, + 136, + 1, // Skip to: 104527 + /* 3958 */ MCD_OPC_CheckPredicate, + 3, + 212, + 136, + 1, // Skip to: 104527 + /* 3963 */ MCD_OPC_Decode, + 218, + 9, + 24, // Opcode: CLS_ZPmZ_H + /* 3967 */ MCD_OPC_FilterValue, + 25, + 31, + 0, + 0, // Skip to: 4003 + /* 3972 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3975 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3989 + /* 3980 */ MCD_OPC_CheckPredicate, + 3, + 190, + 136, + 1, // Skip to: 104527 + /* 3985 */ MCD_OPC_Decode, + 228, + 9, + 24, // Opcode: CLZ_ZPmZ_B + /* 3989 */ MCD_OPC_FilterValue, + 1, + 181, + 136, + 1, // Skip to: 104527 + /* 3994 */ MCD_OPC_CheckPredicate, + 3, + 176, + 136, + 1, // Skip to: 104527 + /* 3999 */ MCD_OPC_Decode, + 230, + 9, + 24, // Opcode: CLZ_ZPmZ_H + /* 4003 */ MCD_OPC_FilterValue, + 26, + 31, + 0, + 0, // Skip to: 4039 + /* 4008 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4011 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4025 + /* 4016 */ MCD_OPC_CheckPredicate, + 3, + 154, + 136, + 1, // Skip to: 104527 + /* 4021 */ MCD_OPC_Decode, + 182, + 11, + 24, // Opcode: CNT_ZPmZ_B + /* 4025 */ MCD_OPC_FilterValue, + 1, + 145, + 136, + 1, // Skip to: 104527 + /* 4030 */ MCD_OPC_CheckPredicate, + 3, + 140, + 136, + 1, // Skip to: 104527 + /* 4035 */ MCD_OPC_Decode, + 184, + 11, + 24, // Opcode: CNT_ZPmZ_H + /* 4039 */ MCD_OPC_FilterValue, + 27, + 31, + 0, + 0, // Skip to: 4075 + /* 4044 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4047 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4061 + /* 4052 */ MCD_OPC_CheckPredicate, + 3, + 118, + 136, + 1, // Skip to: 104527 + /* 4057 */ MCD_OPC_Decode, + 170, + 11, + 24, // Opcode: CNOT_ZPmZ_B + /* 4061 */ MCD_OPC_FilterValue, + 1, + 109, + 136, + 1, // Skip to: 104527 + /* 4066 */ MCD_OPC_CheckPredicate, + 3, + 104, + 136, + 1, // Skip to: 104527 + /* 4071 */ MCD_OPC_Decode, + 172, + 11, + 24, // Opcode: CNOT_ZPmZ_H + /* 4075 */ MCD_OPC_FilterValue, + 28, + 16, + 0, + 0, // Skip to: 4096 + /* 4080 */ MCD_OPC_CheckPredicate, + 3, + 90, + 136, + 1, // Skip to: 104527 + /* 4085 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 83, + 136, + 1, // Skip to: 104527 + /* 4092 */ MCD_OPC_Decode, + 215, + 12, + 24, // Opcode: FABS_ZPmZ_H + /* 4096 */ MCD_OPC_FilterValue, + 29, + 16, + 0, + 0, // Skip to: 4117 + /* 4101 */ MCD_OPC_CheckPredicate, + 3, + 69, + 136, + 1, // Skip to: 104527 + /* 4106 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 62, + 136, + 1, // Skip to: 104527 + /* 4113 */ MCD_OPC_Decode, + 163, + 18, + 24, // Opcode: FNEG_ZPmZ_H + /* 4117 */ MCD_OPC_FilterValue, + 30, + 53, + 136, + 1, // Skip to: 104527 + /* 4122 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4125 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4139 + /* 4130 */ MCD_OPC_CheckPredicate, + 3, + 40, + 136, + 1, // Skip to: 104527 + /* 4135 */ MCD_OPC_Decode, + 134, + 28, + 24, // Opcode: NOT_ZPmZ_B + /* 4139 */ MCD_OPC_FilterValue, + 1, + 31, + 136, + 1, // Skip to: 104527 + /* 4144 */ MCD_OPC_CheckPredicate, + 3, + 26, + 136, + 1, // Skip to: 104527 + /* 4149 */ MCD_OPC_Decode, + 136, + 28, + 24, // Opcode: NOT_ZPmZ_H + /* 4153 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 4189 + /* 4158 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4161 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4175 + /* 4166 */ MCD_OPC_CheckPredicate, + 3, + 4, + 136, + 1, // Skip to: 104527 + /* 4171 */ MCD_OPC_Decode, + 136, + 27, + 32, // Opcode: MAD_ZPmZZ_B + /* 4175 */ MCD_OPC_FilterValue, + 1, + 251, + 135, + 1, // Skip to: 104527 + /* 4180 */ MCD_OPC_CheckPredicate, + 3, + 246, + 135, + 1, // Skip to: 104527 + /* 4185 */ MCD_OPC_Decode, + 138, + 27, + 32, // Opcode: MAD_ZPmZZ_H + /* 4189 */ MCD_OPC_FilterValue, + 7, + 237, + 135, + 1, // Skip to: 104527 + /* 4194 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4197 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4211 + /* 4202 */ MCD_OPC_CheckPredicate, + 3, + 224, + 135, + 1, // Skip to: 104527 + /* 4207 */ MCD_OPC_Decode, + 202, + 27, + 32, // Opcode: MSB_ZPmZZ_B + /* 4211 */ MCD_OPC_FilterValue, + 1, + 215, + 135, + 1, // Skip to: 104527 + /* 4216 */ MCD_OPC_CheckPredicate, + 3, + 210, + 135, + 1, // Skip to: 104527 + /* 4221 */ MCD_OPC_Decode, + 204, + 27, + 32, // Opcode: MSB_ZPmZZ_H + /* 4225 */ MCD_OPC_FilterValue, + 1, + 147, + 8, + 0, // Skip to: 6425 + /* 4230 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4233 */ MCD_OPC_FilterValue, + 0, + 211, + 2, + 0, // Skip to: 4961 + /* 4238 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 4241 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 4277 + /* 4246 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4249 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4263 + /* 4254 */ MCD_OPC_CheckPredicate, + 3, + 172, + 135, + 1, // Skip to: 104527 + /* 4259 */ MCD_OPC_Decode, + 205, + 7, + 22, // Opcode: ADD_ZPmZ_S + /* 4263 */ MCD_OPC_FilterValue, + 1, + 163, + 135, + 1, // Skip to: 104527 + /* 4268 */ MCD_OPC_CheckPredicate, + 3, + 158, + 135, + 1, // Skip to: 104527 + /* 4273 */ MCD_OPC_Decode, + 203, + 7, + 22, // Opcode: ADD_ZPmZ_D + /* 4277 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 4313 + /* 4282 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4285 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4299 + /* 4290 */ MCD_OPC_CheckPredicate, + 3, + 136, + 135, + 1, // Skip to: 104527 + /* 4295 */ MCD_OPC_Decode, + 211, + 40, + 22, // Opcode: SUB_ZPmZ_S + /* 4299 */ MCD_OPC_FilterValue, + 1, + 127, + 135, + 1, // Skip to: 104527 + /* 4304 */ MCD_OPC_CheckPredicate, + 3, + 122, + 135, + 1, // Skip to: 104527 + /* 4309 */ MCD_OPC_Decode, + 209, + 40, + 22, // Opcode: SUB_ZPmZ_D + /* 4313 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 4349 + /* 4318 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4321 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4335 + /* 4326 */ MCD_OPC_CheckPredicate, + 3, + 100, + 135, + 1, // Skip to: 104527 + /* 4331 */ MCD_OPC_Decode, + 189, + 40, + 22, // Opcode: SUBR_ZPmZ_S + /* 4335 */ MCD_OPC_FilterValue, + 1, + 91, + 135, + 1, // Skip to: 104527 + /* 4340 */ MCD_OPC_CheckPredicate, + 3, + 86, + 135, + 1, // Skip to: 104527 + /* 4345 */ MCD_OPC_Decode, + 187, + 40, + 22, // Opcode: SUBR_ZPmZ_D + /* 4349 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 4385 + /* 4354 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4357 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4371 + /* 4362 */ MCD_OPC_CheckPredicate, + 3, + 64, + 135, + 1, // Skip to: 104527 + /* 4367 */ MCD_OPC_Decode, + 242, + 31, + 22, // Opcode: SMAX_ZPmZ_S + /* 4371 */ MCD_OPC_FilterValue, + 1, + 55, + 135, + 1, // Skip to: 104527 + /* 4376 */ MCD_OPC_CheckPredicate, + 3, + 50, + 135, + 1, // Skip to: 104527 + /* 4381 */ MCD_OPC_Decode, + 240, + 31, + 22, // Opcode: SMAX_ZPmZ_D + /* 4385 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 4421 + /* 4390 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4393 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4407 + /* 4398 */ MCD_OPC_CheckPredicate, + 3, + 28, + 135, + 1, // Skip to: 104527 + /* 4403 */ MCD_OPC_Decode, + 161, + 43, + 22, // Opcode: UMAX_ZPmZ_S + /* 4407 */ MCD_OPC_FilterValue, + 1, + 19, + 135, + 1, // Skip to: 104527 + /* 4412 */ MCD_OPC_CheckPredicate, + 3, + 14, + 135, + 1, // Skip to: 104527 + /* 4417 */ MCD_OPC_Decode, + 159, + 43, + 22, // Opcode: UMAX_ZPmZ_D + /* 4421 */ MCD_OPC_FilterValue, + 10, + 31, + 0, + 0, // Skip to: 4457 + /* 4426 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4429 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4443 + /* 4434 */ MCD_OPC_CheckPredicate, + 3, + 248, + 134, + 1, // Skip to: 104527 + /* 4439 */ MCD_OPC_Decode, + 148, + 32, + 22, // Opcode: SMIN_ZPmZ_S + /* 4443 */ MCD_OPC_FilterValue, + 1, + 239, + 134, + 1, // Skip to: 104527 + /* 4448 */ MCD_OPC_CheckPredicate, + 3, + 234, + 134, + 1, // Skip to: 104527 + /* 4453 */ MCD_OPC_Decode, + 146, + 32, + 22, // Opcode: SMIN_ZPmZ_D + /* 4457 */ MCD_OPC_FilterValue, + 11, + 31, + 0, + 0, // Skip to: 4493 + /* 4462 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4465 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4479 + /* 4470 */ MCD_OPC_CheckPredicate, + 3, + 212, + 134, + 1, // Skip to: 104527 + /* 4475 */ MCD_OPC_Decode, + 194, + 43, + 22, // Opcode: UMIN_ZPmZ_S + /* 4479 */ MCD_OPC_FilterValue, + 1, + 203, + 134, + 1, // Skip to: 104527 + /* 4484 */ MCD_OPC_CheckPredicate, + 3, + 198, + 134, + 1, // Skip to: 104527 + /* 4489 */ MCD_OPC_Decode, + 192, + 43, + 22, // Opcode: UMIN_ZPmZ_D + /* 4493 */ MCD_OPC_FilterValue, + 12, + 31, + 0, + 0, // Skip to: 4529 + /* 4498 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4501 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4515 + /* 4506 */ MCD_OPC_CheckPredicate, + 3, + 176, + 134, + 1, // Skip to: 104527 + /* 4511 */ MCD_OPC_Decode, + 255, + 29, + 22, // Opcode: SABD_ZPmZ_S + /* 4515 */ MCD_OPC_FilterValue, + 1, + 167, + 134, + 1, // Skip to: 104527 + /* 4520 */ MCD_OPC_CheckPredicate, + 3, + 162, + 134, + 1, // Skip to: 104527 + /* 4525 */ MCD_OPC_Decode, + 253, + 29, + 22, // Opcode: SABD_ZPmZ_D + /* 4529 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 4565 + /* 4534 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4537 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4551 + /* 4542 */ MCD_OPC_CheckPredicate, + 3, + 140, + 134, + 1, // Skip to: 104527 + /* 4547 */ MCD_OPC_Decode, + 255, + 41, + 22, // Opcode: UABD_ZPmZ_S + /* 4551 */ MCD_OPC_FilterValue, + 1, + 131, + 134, + 1, // Skip to: 104527 + /* 4556 */ MCD_OPC_CheckPredicate, + 3, + 126, + 134, + 1, // Skip to: 104527 + /* 4561 */ MCD_OPC_Decode, + 253, + 41, + 22, // Opcode: UABD_ZPmZ_D + /* 4565 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 4601 + /* 4570 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4573 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4587 + /* 4578 */ MCD_OPC_CheckPredicate, + 3, + 104, + 134, + 1, // Skip to: 104527 + /* 4583 */ MCD_OPC_Decode, + 219, + 27, + 22, // Opcode: MUL_ZPmZ_S + /* 4587 */ MCD_OPC_FilterValue, + 1, + 95, + 134, + 1, // Skip to: 104527 + /* 4592 */ MCD_OPC_CheckPredicate, + 3, + 90, + 134, + 1, // Skip to: 104527 + /* 4597 */ MCD_OPC_Decode, + 217, + 27, + 22, // Opcode: MUL_ZPmZ_D + /* 4601 */ MCD_OPC_FilterValue, + 18, + 31, + 0, + 0, // Skip to: 4637 + /* 4606 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4609 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4623 + /* 4614 */ MCD_OPC_CheckPredicate, + 3, + 68, + 134, + 1, // Skip to: 104527 + /* 4619 */ MCD_OPC_Decode, + 215, + 32, + 22, // Opcode: SMULH_ZPmZ_S + /* 4623 */ MCD_OPC_FilterValue, + 1, + 59, + 134, + 1, // Skip to: 104527 + /* 4628 */ MCD_OPC_CheckPredicate, + 3, + 54, + 134, + 1, // Skip to: 104527 + /* 4633 */ MCD_OPC_Decode, + 213, + 32, + 22, // Opcode: SMULH_ZPmZ_D + /* 4637 */ MCD_OPC_FilterValue, + 19, + 31, + 0, + 0, // Skip to: 4673 + /* 4642 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4645 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4659 + /* 4650 */ MCD_OPC_CheckPredicate, + 3, + 32, + 134, + 1, // Skip to: 104527 + /* 4655 */ MCD_OPC_Decode, + 131, + 44, + 22, // Opcode: UMULH_ZPmZ_S + /* 4659 */ MCD_OPC_FilterValue, + 1, + 23, + 134, + 1, // Skip to: 104527 + /* 4664 */ MCD_OPC_CheckPredicate, + 3, + 18, + 134, + 1, // Skip to: 104527 + /* 4669 */ MCD_OPC_Decode, + 129, + 44, + 22, // Opcode: UMULH_ZPmZ_D + /* 4673 */ MCD_OPC_FilterValue, + 20, + 31, + 0, + 0, // Skip to: 4709 + /* 4678 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4681 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4695 + /* 4686 */ MCD_OPC_CheckPredicate, + 3, + 252, + 133, + 1, // Skip to: 104527 + /* 4691 */ MCD_OPC_Decode, + 239, + 30, + 22, // Opcode: SDIV_ZPmZ_S + /* 4695 */ MCD_OPC_FilterValue, + 1, + 243, + 133, + 1, // Skip to: 104527 + /* 4700 */ MCD_OPC_CheckPredicate, + 3, + 238, + 133, + 1, // Skip to: 104527 + /* 4705 */ MCD_OPC_Decode, + 238, + 30, + 22, // Opcode: SDIV_ZPmZ_D + /* 4709 */ MCD_OPC_FilterValue, + 21, + 31, + 0, + 0, // Skip to: 4745 + /* 4714 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4717 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4731 + /* 4722 */ MCD_OPC_CheckPredicate, + 3, + 216, + 133, + 1, // Skip to: 104527 + /* 4727 */ MCD_OPC_Decode, + 229, + 42, + 22, // Opcode: UDIV_ZPmZ_S + /* 4731 */ MCD_OPC_FilterValue, + 1, + 207, + 133, + 1, // Skip to: 104527 + /* 4736 */ MCD_OPC_CheckPredicate, + 3, + 202, + 133, + 1, // Skip to: 104527 + /* 4741 */ MCD_OPC_Decode, + 228, + 42, + 22, // Opcode: UDIV_ZPmZ_D + /* 4745 */ MCD_OPC_FilterValue, + 22, + 31, + 0, + 0, // Skip to: 4781 + /* 4750 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4753 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4767 + /* 4758 */ MCD_OPC_CheckPredicate, + 3, + 180, + 133, + 1, // Skip to: 104527 + /* 4763 */ MCD_OPC_Decode, + 235, + 30, + 22, // Opcode: SDIVR_ZPmZ_S + /* 4767 */ MCD_OPC_FilterValue, + 1, + 171, + 133, + 1, // Skip to: 104527 + /* 4772 */ MCD_OPC_CheckPredicate, + 3, + 166, + 133, + 1, // Skip to: 104527 + /* 4777 */ MCD_OPC_Decode, + 234, + 30, + 22, // Opcode: SDIVR_ZPmZ_D + /* 4781 */ MCD_OPC_FilterValue, + 23, + 31, + 0, + 0, // Skip to: 4817 + /* 4786 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4789 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4803 + /* 4794 */ MCD_OPC_CheckPredicate, + 3, + 144, + 133, + 1, // Skip to: 104527 + /* 4799 */ MCD_OPC_Decode, + 225, + 42, + 22, // Opcode: UDIVR_ZPmZ_S + /* 4803 */ MCD_OPC_FilterValue, + 1, + 135, + 133, + 1, // Skip to: 104527 + /* 4808 */ MCD_OPC_CheckPredicate, + 3, + 130, + 133, + 1, // Skip to: 104527 + /* 4813 */ MCD_OPC_Decode, + 224, + 42, + 22, // Opcode: UDIVR_ZPmZ_D + /* 4817 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 4853 + /* 4822 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4825 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4839 + /* 4830 */ MCD_OPC_CheckPredicate, + 3, + 108, + 133, + 1, // Skip to: 104527 + /* 4835 */ MCD_OPC_Decode, + 156, + 28, + 22, // Opcode: ORR_ZPmZ_S + /* 4839 */ MCD_OPC_FilterValue, + 1, + 99, + 133, + 1, // Skip to: 104527 + /* 4844 */ MCD_OPC_CheckPredicate, + 3, + 94, + 133, + 1, // Skip to: 104527 + /* 4849 */ MCD_OPC_Decode, + 154, + 28, + 22, // Opcode: ORR_ZPmZ_D + /* 4853 */ MCD_OPC_FilterValue, + 25, + 31, + 0, + 0, // Skip to: 4889 + /* 4858 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4861 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4875 + /* 4866 */ MCD_OPC_CheckPredicate, + 3, + 72, + 133, + 1, // Skip to: 104527 + /* 4871 */ MCD_OPC_Decode, + 177, + 12, + 22, // Opcode: EOR_ZPmZ_S + /* 4875 */ MCD_OPC_FilterValue, + 1, + 63, + 133, + 1, // Skip to: 104527 + /* 4880 */ MCD_OPC_CheckPredicate, + 3, + 58, + 133, + 1, // Skip to: 104527 + /* 4885 */ MCD_OPC_Decode, + 175, + 12, + 22, // Opcode: EOR_ZPmZ_D + /* 4889 */ MCD_OPC_FilterValue, + 26, + 31, + 0, + 0, // Skip to: 4925 + /* 4894 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4897 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4911 + /* 4902 */ MCD_OPC_CheckPredicate, + 3, + 36, + 133, + 1, // Skip to: 104527 + /* 4907 */ MCD_OPC_Decode, + 134, + 8, + 22, // Opcode: AND_ZPmZ_S + /* 4911 */ MCD_OPC_FilterValue, + 1, + 27, + 133, + 1, // Skip to: 104527 + /* 4916 */ MCD_OPC_CheckPredicate, + 3, + 22, + 133, + 1, // Skip to: 104527 + /* 4921 */ MCD_OPC_Decode, + 132, + 8, + 22, // Opcode: AND_ZPmZ_D + /* 4925 */ MCD_OPC_FilterValue, + 27, + 13, + 133, + 1, // Skip to: 104527 + /* 4930 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4933 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4947 + /* 4938 */ MCD_OPC_CheckPredicate, + 3, + 0, + 133, + 1, // Skip to: 104527 + /* 4943 */ MCD_OPC_Decode, + 228, + 8, + 22, // Opcode: BIC_ZPmZ_S + /* 4947 */ MCD_OPC_FilterValue, + 1, + 247, + 132, + 1, // Skip to: 104527 + /* 4952 */ MCD_OPC_CheckPredicate, + 3, + 242, + 132, + 1, // Skip to: 104527 + /* 4957 */ MCD_OPC_Decode, + 226, + 8, + 22, // Opcode: BIC_ZPmZ_D + /* 4961 */ MCD_OPC_FilterValue, + 1, + 128, + 1, + 0, // Skip to: 5350 + /* 4966 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 4969 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4990 + /* 4974 */ MCD_OPC_CheckPredicate, + 3, + 220, + 132, + 1, // Skip to: 104527 + /* 4979 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 213, + 132, + 1, // Skip to: 104527 + /* 4986 */ MCD_OPC_Decode, + 171, + 30, + 23, // Opcode: SADDV_VPZ_S + /* 4990 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 5026 + /* 4995 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4998 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5012 + /* 5003 */ MCD_OPC_CheckPredicate, + 3, + 191, + 132, + 1, // Skip to: 104527 + /* 5008 */ MCD_OPC_Decode, + 169, + 42, + 23, // Opcode: UADDV_VPZ_S + /* 5012 */ MCD_OPC_FilterValue, + 1, + 182, + 132, + 1, // Skip to: 104527 + /* 5017 */ MCD_OPC_CheckPredicate, + 3, + 177, + 132, + 1, // Skip to: 104527 + /* 5022 */ MCD_OPC_Decode, + 167, + 42, + 23, // Opcode: UADDV_VPZ_D + /* 5026 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 5062 + /* 5031 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5034 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5048 + /* 5039 */ MCD_OPC_CheckPredicate, + 3, + 155, + 132, + 1, // Skip to: 104527 + /* 5044 */ MCD_OPC_Decode, + 229, + 31, + 23, // Opcode: SMAXV_VPZ_S + /* 5048 */ MCD_OPC_FilterValue, + 1, + 146, + 132, + 1, // Skip to: 104527 + /* 5053 */ MCD_OPC_CheckPredicate, + 3, + 141, + 132, + 1, // Skip to: 104527 + /* 5058 */ MCD_OPC_Decode, + 227, + 31, + 23, // Opcode: SMAXV_VPZ_D + /* 5062 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 5098 + /* 5067 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5070 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5084 + /* 5075 */ MCD_OPC_CheckPredicate, + 3, + 119, + 132, + 1, // Skip to: 104527 + /* 5080 */ MCD_OPC_Decode, + 148, + 43, + 23, // Opcode: UMAXV_VPZ_S + /* 5084 */ MCD_OPC_FilterValue, + 1, + 110, + 132, + 1, // Skip to: 104527 + /* 5089 */ MCD_OPC_CheckPredicate, + 3, + 105, + 132, + 1, // Skip to: 104527 + /* 5094 */ MCD_OPC_Decode, + 146, + 43, + 23, // Opcode: UMAXV_VPZ_D + /* 5098 */ MCD_OPC_FilterValue, + 10, + 31, + 0, + 0, // Skip to: 5134 + /* 5103 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5106 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5120 + /* 5111 */ MCD_OPC_CheckPredicate, + 3, + 83, + 132, + 1, // Skip to: 104527 + /* 5116 */ MCD_OPC_Decode, + 135, + 32, + 23, // Opcode: SMINV_VPZ_S + /* 5120 */ MCD_OPC_FilterValue, + 1, + 74, + 132, + 1, // Skip to: 104527 + /* 5125 */ MCD_OPC_CheckPredicate, + 3, + 69, + 132, + 1, // Skip to: 104527 + /* 5130 */ MCD_OPC_Decode, + 133, + 32, + 23, // Opcode: SMINV_VPZ_D + /* 5134 */ MCD_OPC_FilterValue, + 11, + 31, + 0, + 0, // Skip to: 5170 + /* 5139 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5142 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5156 + /* 5147 */ MCD_OPC_CheckPredicate, + 3, + 47, + 132, + 1, // Skip to: 104527 + /* 5152 */ MCD_OPC_Decode, + 181, + 43, + 23, // Opcode: UMINV_VPZ_S + /* 5156 */ MCD_OPC_FilterValue, + 1, + 38, + 132, + 1, // Skip to: 104527 + /* 5161 */ MCD_OPC_CheckPredicate, + 3, + 33, + 132, + 1, // Skip to: 104527 + /* 5166 */ MCD_OPC_Decode, + 179, + 43, + 23, // Opcode: UMINV_VPZ_D + /* 5170 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 5206 + /* 5175 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5178 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5192 + /* 5183 */ MCD_OPC_CheckPredicate, + 3, + 11, + 132, + 1, // Skip to: 104527 + /* 5188 */ MCD_OPC_Decode, + 197, + 27, + 23, // Opcode: MOVPRFX_ZPzZ_S + /* 5192 */ MCD_OPC_FilterValue, + 1, + 2, + 132, + 1, // Skip to: 104527 + /* 5197 */ MCD_OPC_CheckPredicate, + 3, + 253, + 131, + 1, // Skip to: 104527 + /* 5202 */ MCD_OPC_Decode, + 195, + 27, + 23, // Opcode: MOVPRFX_ZPzZ_D + /* 5206 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 5242 + /* 5211 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5214 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5228 + /* 5219 */ MCD_OPC_CheckPredicate, + 3, + 231, + 131, + 1, // Skip to: 104527 + /* 5224 */ MCD_OPC_Decode, + 193, + 27, + 24, // Opcode: MOVPRFX_ZPmZ_S + /* 5228 */ MCD_OPC_FilterValue, + 1, + 222, + 131, + 1, // Skip to: 104527 + /* 5233 */ MCD_OPC_CheckPredicate, + 3, + 217, + 131, + 1, // Skip to: 104527 + /* 5238 */ MCD_OPC_Decode, + 191, + 27, + 24, // Opcode: MOVPRFX_ZPmZ_D + /* 5242 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 5278 + /* 5247 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5250 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5264 + /* 5255 */ MCD_OPC_CheckPredicate, + 3, + 195, + 131, + 1, // Skip to: 104527 + /* 5260 */ MCD_OPC_Decode, + 167, + 28, + 23, // Opcode: ORV_VPZ_S + /* 5264 */ MCD_OPC_FilterValue, + 1, + 186, + 131, + 1, // Skip to: 104527 + /* 5269 */ MCD_OPC_CheckPredicate, + 3, + 181, + 131, + 1, // Skip to: 104527 + /* 5274 */ MCD_OPC_Decode, + 165, + 28, + 23, // Opcode: ORV_VPZ_D + /* 5278 */ MCD_OPC_FilterValue, + 25, + 31, + 0, + 0, // Skip to: 5314 + /* 5283 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5286 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5300 + /* 5291 */ MCD_OPC_CheckPredicate, + 3, + 159, + 131, + 1, // Skip to: 104527 + /* 5296 */ MCD_OPC_Decode, + 167, + 12, + 23, // Opcode: EORV_VPZ_S + /* 5300 */ MCD_OPC_FilterValue, + 1, + 150, + 131, + 1, // Skip to: 104527 + /* 5305 */ MCD_OPC_CheckPredicate, + 3, + 145, + 131, + 1, // Skip to: 104527 + /* 5310 */ MCD_OPC_Decode, + 165, + 12, + 23, // Opcode: EORV_VPZ_D + /* 5314 */ MCD_OPC_FilterValue, + 26, + 136, + 131, + 1, // Skip to: 104527 + /* 5319 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5322 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5336 + /* 5327 */ MCD_OPC_CheckPredicate, + 3, + 123, + 131, + 1, // Skip to: 104527 + /* 5332 */ MCD_OPC_Decode, + 252, + 7, + 23, // Opcode: ANDV_VPZ_S + /* 5336 */ MCD_OPC_FilterValue, + 1, + 114, + 131, + 1, // Skip to: 104527 + /* 5341 */ MCD_OPC_CheckPredicate, + 3, + 109, + 131, + 1, // Skip to: 104527 + /* 5346 */ MCD_OPC_Decode, + 250, + 7, + 23, // Opcode: ANDV_VPZ_D + /* 5350 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 5386 + /* 5355 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5358 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5372 + /* 5363 */ MCD_OPC_CheckPredicate, + 3, + 87, + 131, + 1, // Skip to: 104527 + /* 5368 */ MCD_OPC_Decode, + 145, + 27, + 25, // Opcode: MLA_ZPmZZ_S + /* 5372 */ MCD_OPC_FilterValue, + 1, + 78, + 131, + 1, // Skip to: 104527 + /* 5377 */ MCD_OPC_CheckPredicate, + 3, + 73, + 131, + 1, // Skip to: 104527 + /* 5382 */ MCD_OPC_Decode, + 143, + 27, + 25, // Opcode: MLA_ZPmZZ_D + /* 5386 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 5422 + /* 5391 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5394 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5408 + /* 5399 */ MCD_OPC_CheckPredicate, + 3, + 51, + 131, + 1, // Skip to: 104527 + /* 5404 */ MCD_OPC_Decode, + 162, + 27, + 25, // Opcode: MLS_ZPmZZ_S + /* 5408 */ MCD_OPC_FilterValue, + 1, + 42, + 131, + 1, // Skip to: 104527 + /* 5413 */ MCD_OPC_CheckPredicate, + 3, + 37, + 131, + 1, // Skip to: 104527 + /* 5418 */ MCD_OPC_Decode, + 160, + 27, + 25, // Opcode: MLS_ZPmZZ_D + /* 5422 */ MCD_OPC_FilterValue, + 4, + 152, + 1, + 0, // Skip to: 5835 + /* 5427 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 5430 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5444 + /* 5435 */ MCD_OPC_CheckPredicate, + 3, + 15, + 131, + 1, // Skip to: 104527 + /* 5440 */ MCD_OPC_Decode, + 155, + 8, + 33, // Opcode: ASR_ZPmI_D + /* 5444 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5458 + /* 5449 */ MCD_OPC_CheckPredicate, + 3, + 1, + 131, + 1, // Skip to: 104527 + /* 5454 */ MCD_OPC_Decode, + 251, + 26, + 33, // Opcode: LSR_ZPmI_D + /* 5458 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 5472 + /* 5463 */ MCD_OPC_CheckPredicate, + 3, + 243, + 130, + 1, // Skip to: 104527 + /* 5468 */ MCD_OPC_Decode, + 227, + 26, + 34, // Opcode: LSL_ZPmI_D + /* 5472 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 5486 + /* 5477 */ MCD_OPC_CheckPredicate, + 3, + 229, + 130, + 1, // Skip to: 104527 + /* 5482 */ MCD_OPC_Decode, + 139, + 8, + 33, // Opcode: ASRD_ZPmI_D + /* 5486 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 5500 + /* 5491 */ MCD_OPC_CheckPredicate, + 4, + 215, + 130, + 1, // Skip to: 104527 + /* 5496 */ MCD_OPC_Decode, + 189, + 35, + 34, // Opcode: SQSHL_ZPmI_D + /* 5500 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 5514 + /* 5505 */ MCD_OPC_CheckPredicate, + 4, + 201, + 130, + 1, // Skip to: 104527 + /* 5510 */ MCD_OPC_Decode, + 135, + 45, + 34, // Opcode: UQSHL_ZPmI_D + /* 5514 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 5528 + /* 5519 */ MCD_OPC_CheckPredicate, + 4, + 187, + 130, + 1, // Skip to: 104527 + /* 5524 */ MCD_OPC_Decode, + 216, + 36, + 33, // Opcode: SRSHR_ZPmI_D + /* 5528 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 5542 + /* 5533 */ MCD_OPC_CheckPredicate, + 4, + 173, + 130, + 1, // Skip to: 104527 + /* 5538 */ MCD_OPC_Decode, + 251, + 45, + 33, // Opcode: URSHR_ZPmI_D + /* 5542 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 5556 + /* 5547 */ MCD_OPC_CheckPredicate, + 4, + 159, + 130, + 1, // Skip to: 104527 + /* 5552 */ MCD_OPC_Decode, + 174, + 35, + 34, // Opcode: SQSHLU_ZPmI_D + /* 5556 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 5592 + /* 5561 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5564 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5578 + /* 5569 */ MCD_OPC_CheckPredicate, + 3, + 137, + 130, + 1, // Skip to: 104527 + /* 5574 */ MCD_OPC_Decode, + 161, + 8, + 22, // Opcode: ASR_ZPmZ_S + /* 5578 */ MCD_OPC_FilterValue, + 1, + 128, + 130, + 1, // Skip to: 104527 + /* 5583 */ MCD_OPC_CheckPredicate, + 3, + 123, + 130, + 1, // Skip to: 104527 + /* 5588 */ MCD_OPC_Decode, + 159, + 8, + 22, // Opcode: ASR_ZPmZ_D + /* 5592 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 5628 + /* 5597 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5600 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5614 + /* 5605 */ MCD_OPC_CheckPredicate, + 3, + 101, + 130, + 1, // Skip to: 104527 + /* 5610 */ MCD_OPC_Decode, + 129, + 27, + 22, // Opcode: LSR_ZPmZ_S + /* 5614 */ MCD_OPC_FilterValue, + 1, + 92, + 130, + 1, // Skip to: 104527 + /* 5619 */ MCD_OPC_CheckPredicate, + 3, + 87, + 130, + 1, // Skip to: 104527 + /* 5624 */ MCD_OPC_Decode, + 255, + 26, + 22, // Opcode: LSR_ZPmZ_D + /* 5628 */ MCD_OPC_FilterValue, + 19, + 31, + 0, + 0, // Skip to: 5664 + /* 5633 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5636 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5650 + /* 5641 */ MCD_OPC_CheckPredicate, + 3, + 65, + 130, + 1, // Skip to: 104527 + /* 5646 */ MCD_OPC_Decode, + 233, + 26, + 22, // Opcode: LSL_ZPmZ_S + /* 5650 */ MCD_OPC_FilterValue, + 1, + 56, + 130, + 1, // Skip to: 104527 + /* 5655 */ MCD_OPC_CheckPredicate, + 3, + 51, + 130, + 1, // Skip to: 104527 + /* 5660 */ MCD_OPC_Decode, + 231, + 26, + 22, // Opcode: LSL_ZPmZ_D + /* 5664 */ MCD_OPC_FilterValue, + 20, + 31, + 0, + 0, // Skip to: 5700 + /* 5669 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5672 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5686 + /* 5677 */ MCD_OPC_CheckPredicate, + 3, + 29, + 130, + 1, // Skip to: 104527 + /* 5682 */ MCD_OPC_Decode, + 145, + 8, + 22, // Opcode: ASRR_ZPmZ_S + /* 5686 */ MCD_OPC_FilterValue, + 1, + 20, + 130, + 1, // Skip to: 104527 + /* 5691 */ MCD_OPC_CheckPredicate, + 3, + 15, + 130, + 1, // Skip to: 104527 + /* 5696 */ MCD_OPC_Decode, + 143, + 8, + 22, // Opcode: ASRR_ZPmZ_D + /* 5700 */ MCD_OPC_FilterValue, + 21, + 31, + 0, + 0, // Skip to: 5736 + /* 5705 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5708 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5722 + /* 5713 */ MCD_OPC_CheckPredicate, + 3, + 249, + 129, + 1, // Skip to: 104527 + /* 5718 */ MCD_OPC_Decode, + 241, + 26, + 22, // Opcode: LSRR_ZPmZ_S + /* 5722 */ MCD_OPC_FilterValue, + 1, + 240, + 129, + 1, // Skip to: 104527 + /* 5727 */ MCD_OPC_CheckPredicate, + 3, + 235, + 129, + 1, // Skip to: 104527 + /* 5732 */ MCD_OPC_Decode, + 239, + 26, + 22, // Opcode: LSRR_ZPmZ_D + /* 5736 */ MCD_OPC_FilterValue, + 23, + 31, + 0, + 0, // Skip to: 5772 + /* 5741 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5744 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5758 + /* 5749 */ MCD_OPC_CheckPredicate, + 3, + 213, + 129, + 1, // Skip to: 104527 + /* 5754 */ MCD_OPC_Decode, + 217, + 26, + 22, // Opcode: LSLR_ZPmZ_S + /* 5758 */ MCD_OPC_FilterValue, + 1, + 204, + 129, + 1, // Skip to: 104527 + /* 5763 */ MCD_OPC_CheckPredicate, + 3, + 199, + 129, + 1, // Skip to: 104527 + /* 5768 */ MCD_OPC_Decode, + 215, + 26, + 22, // Opcode: LSLR_ZPmZ_D + /* 5772 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 5793 + /* 5777 */ MCD_OPC_CheckPredicate, + 3, + 185, + 129, + 1, // Skip to: 104527 + /* 5782 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 178, + 129, + 1, // Skip to: 104527 + /* 5789 */ MCD_OPC_Decode, + 150, + 8, + 22, // Opcode: ASR_WIDE_ZPmZ_S + /* 5793 */ MCD_OPC_FilterValue, + 25, + 16, + 0, + 0, // Skip to: 5814 + /* 5798 */ MCD_OPC_CheckPredicate, + 3, + 164, + 129, + 1, // Skip to: 104527 + /* 5803 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 157, + 129, + 1, // Skip to: 104527 + /* 5810 */ MCD_OPC_Decode, + 246, + 26, + 22, // Opcode: LSR_WIDE_ZPmZ_S + /* 5814 */ MCD_OPC_FilterValue, + 27, + 148, + 129, + 1, // Skip to: 104527 + /* 5819 */ MCD_OPC_CheckPredicate, + 3, + 143, + 129, + 1, // Skip to: 104527 + /* 5824 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 136, + 129, + 1, // Skip to: 104527 + /* 5831 */ MCD_OPC_Decode, + 222, + 26, + 22, // Opcode: LSL_WIDE_ZPmZ_S + /* 5835 */ MCD_OPC_FilterValue, + 5, + 1, + 2, + 0, // Skip to: 6353 + /* 5840 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 5843 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 5879 + /* 5848 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5851 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5865 + /* 5856 */ MCD_OPC_CheckPredicate, + 3, + 106, + 129, + 1, // Skip to: 104527 + /* 5861 */ MCD_OPC_Decode, + 143, + 41, + 24, // Opcode: SXTB_ZPmZ_S + /* 5865 */ MCD_OPC_FilterValue, + 1, + 97, + 129, + 1, // Skip to: 104527 + /* 5870 */ MCD_OPC_CheckPredicate, + 3, + 92, + 129, + 1, // Skip to: 104527 + /* 5875 */ MCD_OPC_Decode, + 141, + 41, + 24, // Opcode: SXTB_ZPmZ_D + /* 5879 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 5915 + /* 5884 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5887 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5901 + /* 5892 */ MCD_OPC_CheckPredicate, + 3, + 70, + 129, + 1, // Skip to: 104527 + /* 5897 */ MCD_OPC_Decode, + 248, + 46, + 24, // Opcode: UXTB_ZPmZ_S + /* 5901 */ MCD_OPC_FilterValue, + 1, + 61, + 129, + 1, // Skip to: 104527 + /* 5906 */ MCD_OPC_CheckPredicate, + 3, + 56, + 129, + 1, // Skip to: 104527 + /* 5911 */ MCD_OPC_Decode, + 246, + 46, + 24, // Opcode: UXTB_ZPmZ_D + /* 5915 */ MCD_OPC_FilterValue, + 18, + 31, + 0, + 0, // Skip to: 5951 + /* 5920 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5923 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5937 + /* 5928 */ MCD_OPC_CheckPredicate, + 3, + 34, + 129, + 1, // Skip to: 104527 + /* 5933 */ MCD_OPC_Decode, + 145, + 41, + 24, // Opcode: SXTH_ZPmZ_S + /* 5937 */ MCD_OPC_FilterValue, + 1, + 25, + 129, + 1, // Skip to: 104527 + /* 5942 */ MCD_OPC_CheckPredicate, + 3, + 20, + 129, + 1, // Skip to: 104527 + /* 5947 */ MCD_OPC_Decode, + 144, + 41, + 24, // Opcode: SXTH_ZPmZ_D + /* 5951 */ MCD_OPC_FilterValue, + 19, + 31, + 0, + 0, // Skip to: 5987 + /* 5956 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5959 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5973 + /* 5964 */ MCD_OPC_CheckPredicate, + 3, + 254, + 128, + 1, // Skip to: 104527 + /* 5969 */ MCD_OPC_Decode, + 250, + 46, + 24, // Opcode: UXTH_ZPmZ_S + /* 5973 */ MCD_OPC_FilterValue, + 1, + 245, + 128, + 1, // Skip to: 104527 + /* 5978 */ MCD_OPC_CheckPredicate, + 3, + 240, + 128, + 1, // Skip to: 104527 + /* 5983 */ MCD_OPC_Decode, + 249, + 46, + 24, // Opcode: UXTH_ZPmZ_D + /* 5987 */ MCD_OPC_FilterValue, + 20, + 16, + 0, + 0, // Skip to: 6008 + /* 5992 */ MCD_OPC_CheckPredicate, + 3, + 226, + 128, + 1, // Skip to: 104527 + /* 5997 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 219, + 128, + 1, // Skip to: 104527 + /* 6004 */ MCD_OPC_Decode, + 146, + 41, + 24, // Opcode: SXTW_ZPmZ_D + /* 6008 */ MCD_OPC_FilterValue, + 21, + 16, + 0, + 0, // Skip to: 6029 + /* 6013 */ MCD_OPC_CheckPredicate, + 3, + 205, + 128, + 1, // Skip to: 104527 + /* 6018 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 198, + 128, + 1, // Skip to: 104527 + /* 6025 */ MCD_OPC_Decode, + 251, + 46, + 24, // Opcode: UXTW_ZPmZ_D + /* 6029 */ MCD_OPC_FilterValue, + 22, + 31, + 0, + 0, // Skip to: 6065 + /* 6034 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6037 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6051 + /* 6042 */ MCD_OPC_CheckPredicate, + 3, + 176, + 128, + 1, // Skip to: 104527 + /* 6047 */ MCD_OPC_Decode, + 131, + 7, + 24, // Opcode: ABS_ZPmZ_S + /* 6051 */ MCD_OPC_FilterValue, + 1, + 167, + 128, + 1, // Skip to: 104527 + /* 6056 */ MCD_OPC_CheckPredicate, + 3, + 162, + 128, + 1, // Skip to: 104527 + /* 6061 */ MCD_OPC_Decode, + 129, + 7, + 24, // Opcode: ABS_ZPmZ_D + /* 6065 */ MCD_OPC_FilterValue, + 23, + 31, + 0, + 0, // Skip to: 6101 + /* 6070 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6073 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6087 + /* 6078 */ MCD_OPC_CheckPredicate, + 3, + 140, + 128, + 1, // Skip to: 104527 + /* 6083 */ MCD_OPC_Decode, + 249, + 27, + 24, // Opcode: NEG_ZPmZ_S + /* 6087 */ MCD_OPC_FilterValue, + 1, + 131, + 128, + 1, // Skip to: 104527 + /* 6092 */ MCD_OPC_CheckPredicate, + 3, + 126, + 128, + 1, // Skip to: 104527 + /* 6097 */ MCD_OPC_Decode, + 247, + 27, + 24, // Opcode: NEG_ZPmZ_D + /* 6101 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 6137 + /* 6106 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6109 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6123 + /* 6114 */ MCD_OPC_CheckPredicate, + 3, + 104, + 128, + 1, // Skip to: 104527 + /* 6119 */ MCD_OPC_Decode, + 219, + 9, + 24, // Opcode: CLS_ZPmZ_S + /* 6123 */ MCD_OPC_FilterValue, + 1, + 95, + 128, + 1, // Skip to: 104527 + /* 6128 */ MCD_OPC_CheckPredicate, + 3, + 90, + 128, + 1, // Skip to: 104527 + /* 6133 */ MCD_OPC_Decode, + 217, + 9, + 24, // Opcode: CLS_ZPmZ_D + /* 6137 */ MCD_OPC_FilterValue, + 25, + 31, + 0, + 0, // Skip to: 6173 + /* 6142 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6145 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6159 + /* 6150 */ MCD_OPC_CheckPredicate, + 3, + 68, + 128, + 1, // Skip to: 104527 + /* 6155 */ MCD_OPC_Decode, + 231, + 9, + 24, // Opcode: CLZ_ZPmZ_S + /* 6159 */ MCD_OPC_FilterValue, + 1, + 59, + 128, + 1, // Skip to: 104527 + /* 6164 */ MCD_OPC_CheckPredicate, + 3, + 54, + 128, + 1, // Skip to: 104527 + /* 6169 */ MCD_OPC_Decode, + 229, + 9, + 24, // Opcode: CLZ_ZPmZ_D + /* 6173 */ MCD_OPC_FilterValue, + 26, + 31, + 0, + 0, // Skip to: 6209 + /* 6178 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6181 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6195 + /* 6186 */ MCD_OPC_CheckPredicate, + 3, + 32, + 128, + 1, // Skip to: 104527 + /* 6191 */ MCD_OPC_Decode, + 185, + 11, + 24, // Opcode: CNT_ZPmZ_S + /* 6195 */ MCD_OPC_FilterValue, + 1, + 23, + 128, + 1, // Skip to: 104527 + /* 6200 */ MCD_OPC_CheckPredicate, + 3, + 18, + 128, + 1, // Skip to: 104527 + /* 6205 */ MCD_OPC_Decode, + 183, + 11, + 24, // Opcode: CNT_ZPmZ_D + /* 6209 */ MCD_OPC_FilterValue, + 27, + 31, + 0, + 0, // Skip to: 6245 + /* 6214 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6217 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6231 + /* 6222 */ MCD_OPC_CheckPredicate, + 3, + 252, + 127, + 1, // Skip to: 104527 + /* 6227 */ MCD_OPC_Decode, + 173, + 11, + 24, // Opcode: CNOT_ZPmZ_S + /* 6231 */ MCD_OPC_FilterValue, + 1, + 243, + 127, + 1, // Skip to: 104527 + /* 6236 */ MCD_OPC_CheckPredicate, + 3, + 238, + 127, + 1, // Skip to: 104527 + /* 6241 */ MCD_OPC_Decode, + 171, + 11, + 24, // Opcode: CNOT_ZPmZ_D + /* 6245 */ MCD_OPC_FilterValue, + 28, + 31, + 0, + 0, // Skip to: 6281 + /* 6250 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6253 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6267 + /* 6258 */ MCD_OPC_CheckPredicate, + 3, + 216, + 127, + 1, // Skip to: 104527 + /* 6263 */ MCD_OPC_Decode, + 216, + 12, + 24, // Opcode: FABS_ZPmZ_S + /* 6267 */ MCD_OPC_FilterValue, + 1, + 207, + 127, + 1, // Skip to: 104527 + /* 6272 */ MCD_OPC_CheckPredicate, + 3, + 202, + 127, + 1, // Skip to: 104527 + /* 6277 */ MCD_OPC_Decode, + 214, + 12, + 24, // Opcode: FABS_ZPmZ_D + /* 6281 */ MCD_OPC_FilterValue, + 29, + 31, + 0, + 0, // Skip to: 6317 + /* 6286 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6289 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6303 + /* 6294 */ MCD_OPC_CheckPredicate, + 3, + 180, + 127, + 1, // Skip to: 104527 + /* 6299 */ MCD_OPC_Decode, + 164, + 18, + 24, // Opcode: FNEG_ZPmZ_S + /* 6303 */ MCD_OPC_FilterValue, + 1, + 171, + 127, + 1, // Skip to: 104527 + /* 6308 */ MCD_OPC_CheckPredicate, + 3, + 166, + 127, + 1, // Skip to: 104527 + /* 6313 */ MCD_OPC_Decode, + 162, + 18, + 24, // Opcode: FNEG_ZPmZ_D + /* 6317 */ MCD_OPC_FilterValue, + 30, + 157, + 127, + 1, // Skip to: 104527 + /* 6322 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6325 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6339 + /* 6330 */ MCD_OPC_CheckPredicate, + 3, + 144, + 127, + 1, // Skip to: 104527 + /* 6335 */ MCD_OPC_Decode, + 137, + 28, + 24, // Opcode: NOT_ZPmZ_S + /* 6339 */ MCD_OPC_FilterValue, + 1, + 135, + 127, + 1, // Skip to: 104527 + /* 6344 */ MCD_OPC_CheckPredicate, + 3, + 130, + 127, + 1, // Skip to: 104527 + /* 6349 */ MCD_OPC_Decode, + 135, + 28, + 24, // Opcode: NOT_ZPmZ_D + /* 6353 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 6389 + /* 6358 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6361 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6375 + /* 6366 */ MCD_OPC_CheckPredicate, + 3, + 108, + 127, + 1, // Skip to: 104527 + /* 6371 */ MCD_OPC_Decode, + 139, + 27, + 32, // Opcode: MAD_ZPmZZ_S + /* 6375 */ MCD_OPC_FilterValue, + 1, + 99, + 127, + 1, // Skip to: 104527 + /* 6380 */ MCD_OPC_CheckPredicate, + 3, + 94, + 127, + 1, // Skip to: 104527 + /* 6385 */ MCD_OPC_Decode, + 137, + 27, + 32, // Opcode: MAD_ZPmZZ_D + /* 6389 */ MCD_OPC_FilterValue, + 7, + 85, + 127, + 1, // Skip to: 104527 + /* 6394 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6397 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6411 + /* 6402 */ MCD_OPC_CheckPredicate, + 3, + 72, + 127, + 1, // Skip to: 104527 + /* 6407 */ MCD_OPC_Decode, + 205, + 27, + 32, // Opcode: MSB_ZPmZZ_S + /* 6411 */ MCD_OPC_FilterValue, + 1, + 63, + 127, + 1, // Skip to: 104527 + /* 6416 */ MCD_OPC_CheckPredicate, + 3, + 58, + 127, + 1, // Skip to: 104527 + /* 6421 */ MCD_OPC_Decode, + 203, + 27, + 32, // Opcode: MSB_ZPmZZ_D + /* 6425 */ MCD_OPC_FilterValue, + 2, + 161, + 0, + 0, // Skip to: 6591 + /* 6430 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6433 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 6483 + /* 6438 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6441 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 6462 + /* 6446 */ MCD_OPC_CheckPredicate, + 3, + 28, + 127, + 1, // Skip to: 104527 + /* 6451 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 21, + 127, + 1, // Skip to: 104527 + /* 6458 */ MCD_OPC_Decode, + 152, + 28, + 35, // Opcode: ORR_ZI + /* 6462 */ MCD_OPC_FilterValue, + 1, + 12, + 127, + 1, // Skip to: 104527 + /* 6467 */ MCD_OPC_CheckPredicate, + 3, + 7, + 127, + 1, // Skip to: 104527 + /* 6472 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 0, + 127, + 1, // Skip to: 104527 + /* 6479 */ MCD_OPC_Decode, + 173, + 12, + 35, // Opcode: EOR_ZI + /* 6483 */ MCD_OPC_FilterValue, + 1, + 247, + 126, + 1, // Skip to: 104527 + /* 6488 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 6491 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 6527 + /* 6496 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6499 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6513 + /* 6504 */ MCD_OPC_CheckPredicate, + 3, + 226, + 126, + 1, // Skip to: 104527 + /* 6509 */ MCD_OPC_Decode, + 202, + 11, + 36, // Opcode: CPY_ZPzI_B + /* 6513 */ MCD_OPC_FilterValue, + 1, + 217, + 126, + 1, // Skip to: 104527 + /* 6518 */ MCD_OPC_CheckPredicate, + 3, + 212, + 126, + 1, // Skip to: 104527 + /* 6523 */ MCD_OPC_Decode, + 204, + 11, + 37, // Opcode: CPY_ZPzI_H + /* 6527 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 6563 + /* 6532 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6535 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6549 + /* 6540 */ MCD_OPC_CheckPredicate, + 3, + 190, + 126, + 1, // Skip to: 104527 + /* 6545 */ MCD_OPC_Decode, + 190, + 11, + 38, // Opcode: CPY_ZPmI_B + /* 6549 */ MCD_OPC_FilterValue, + 1, + 181, + 126, + 1, // Skip to: 104527 + /* 6554 */ MCD_OPC_CheckPredicate, + 3, + 176, + 126, + 1, // Skip to: 104527 + /* 6559 */ MCD_OPC_Decode, + 192, + 11, + 39, // Opcode: CPY_ZPmI_H + /* 6563 */ MCD_OPC_FilterValue, + 3, + 167, + 126, + 1, // Skip to: 104527 + /* 6568 */ MCD_OPC_CheckPredicate, + 3, + 162, + 126, + 1, // Skip to: 104527 + /* 6573 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 155, + 126, + 1, // Skip to: 104527 + /* 6580 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 148, + 126, + 1, // Skip to: 104527 + /* 6587 */ MCD_OPC_Decode, + 159, + 14, + 40, // Opcode: FCPY_ZPmI_H + /* 6591 */ MCD_OPC_FilterValue, + 3, + 139, + 126, + 1, // Skip to: 104527 + /* 6596 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6599 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 6649 + /* 6604 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6607 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 6628 + /* 6612 */ MCD_OPC_CheckPredicate, + 3, + 118, + 126, + 1, // Skip to: 104527 + /* 6617 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 111, + 126, + 1, // Skip to: 104527 + /* 6624 */ MCD_OPC_Decode, + 130, + 8, + 35, // Opcode: AND_ZI + /* 6628 */ MCD_OPC_FilterValue, + 1, + 102, + 126, + 1, // Skip to: 104527 + /* 6633 */ MCD_OPC_CheckPredicate, + 3, + 97, + 126, + 1, // Skip to: 104527 + /* 6638 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 90, + 126, + 1, // Skip to: 104527 + /* 6645 */ MCD_OPC_Decode, + 251, + 11, + 35, // Opcode: DUPM_ZI + /* 6649 */ MCD_OPC_FilterValue, + 1, + 81, + 126, + 1, // Skip to: 104527 + /* 6654 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 6657 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 6693 + /* 6662 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6665 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6679 + /* 6670 */ MCD_OPC_CheckPredicate, + 3, + 60, + 126, + 1, // Skip to: 104527 + /* 6675 */ MCD_OPC_Decode, + 205, + 11, + 41, // Opcode: CPY_ZPzI_S + /* 6679 */ MCD_OPC_FilterValue, + 1, + 51, + 126, + 1, // Skip to: 104527 + /* 6684 */ MCD_OPC_CheckPredicate, + 3, + 46, + 126, + 1, // Skip to: 104527 + /* 6689 */ MCD_OPC_Decode, + 203, + 11, + 42, // Opcode: CPY_ZPzI_D + /* 6693 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 6729 + /* 6698 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6701 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6715 + /* 6706 */ MCD_OPC_CheckPredicate, + 3, + 24, + 126, + 1, // Skip to: 104527 + /* 6711 */ MCD_OPC_Decode, + 193, + 11, + 43, // Opcode: CPY_ZPmI_S + /* 6715 */ MCD_OPC_FilterValue, + 1, + 15, + 126, + 1, // Skip to: 104527 + /* 6720 */ MCD_OPC_CheckPredicate, + 3, + 10, + 126, + 1, // Skip to: 104527 + /* 6725 */ MCD_OPC_Decode, + 191, + 11, + 44, // Opcode: CPY_ZPmI_D + /* 6729 */ MCD_OPC_FilterValue, + 3, + 1, + 126, + 1, // Skip to: 104527 + /* 6734 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 6737 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 6758 + /* 6742 */ MCD_OPC_CheckPredicate, + 3, + 244, + 125, + 1, // Skip to: 104527 + /* 6747 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 237, + 125, + 1, // Skip to: 104527 + /* 6754 */ MCD_OPC_Decode, + 160, + 14, + 40, // Opcode: FCPY_ZPmI_S + /* 6758 */ MCD_OPC_FilterValue, + 1, + 228, + 125, + 1, // Skip to: 104527 + /* 6763 */ MCD_OPC_CheckPredicate, + 3, + 223, + 125, + 1, // Skip to: 104527 + /* 6768 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 216, + 125, + 1, // Skip to: 104527 + /* 6775 */ MCD_OPC_Decode, + 158, + 14, + 40, // Opcode: FCPY_ZPmI_D + /* 6779 */ MCD_OPC_FilterValue, + 1, + 207, + 125, + 1, // Skip to: 104527 + /* 6784 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 6787 */ MCD_OPC_FilterValue, + 0, + 230, + 5, + 0, // Skip to: 8302 + /* 6792 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6795 */ MCD_OPC_FilterValue, + 0, + 235, + 1, + 0, // Skip to: 7291 + /* 6800 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 6803 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 6895 + /* 6808 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 6811 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6825 + /* 6816 */ MCD_OPC_CheckPredicate, + 3, + 170, + 125, + 1, // Skip to: 104527 + /* 6821 */ MCD_OPC_Decode, + 206, + 7, + 45, // Opcode: ADD_ZZZ_B + /* 6825 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6839 + /* 6830 */ MCD_OPC_CheckPredicate, + 3, + 156, + 125, + 1, // Skip to: 104527 + /* 6835 */ MCD_OPC_Decode, + 212, + 40, + 45, // Opcode: SUB_ZZZ_B + /* 6839 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 6853 + /* 6844 */ MCD_OPC_CheckPredicate, + 3, + 142, + 125, + 1, // Skip to: 104527 + /* 6849 */ MCD_OPC_Decode, + 144, + 33, + 45, // Opcode: SQADD_ZZZ_B + /* 6853 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 6867 + /* 6858 */ MCD_OPC_CheckPredicate, + 3, + 128, + 125, + 1, // Skip to: 104527 + /* 6863 */ MCD_OPC_Decode, + 165, + 44, + 45, // Opcode: UQADD_ZZZ_B + /* 6867 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 6881 + /* 6872 */ MCD_OPC_CheckPredicate, + 3, + 114, + 125, + 1, // Skip to: 104527 + /* 6877 */ MCD_OPC_Decode, + 132, + 36, + 45, // Opcode: SQSUB_ZZZ_B + /* 6881 */ MCD_OPC_FilterValue, + 7, + 105, + 125, + 1, // Skip to: 104527 + /* 6886 */ MCD_OPC_CheckPredicate, + 3, + 100, + 125, + 1, // Skip to: 104527 + /* 6891 */ MCD_OPC_Decode, + 191, + 45, + 45, // Opcode: UQSUB_ZZZ_B + /* 6895 */ MCD_OPC_FilterValue, + 1, + 87, + 0, + 0, // Skip to: 6987 + /* 6900 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 6903 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6917 + /* 6908 */ MCD_OPC_CheckPredicate, + 3, + 78, + 125, + 1, // Skip to: 104527 + /* 6913 */ MCD_OPC_Decode, + 208, + 7, + 45, // Opcode: ADD_ZZZ_H + /* 6917 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6931 + /* 6922 */ MCD_OPC_CheckPredicate, + 3, + 64, + 125, + 1, // Skip to: 104527 + /* 6927 */ MCD_OPC_Decode, + 214, + 40, + 45, // Opcode: SUB_ZZZ_H + /* 6931 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 6945 + /* 6936 */ MCD_OPC_CheckPredicate, + 3, + 50, + 125, + 1, // Skip to: 104527 + /* 6941 */ MCD_OPC_Decode, + 146, + 33, + 45, // Opcode: SQADD_ZZZ_H + /* 6945 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 6959 + /* 6950 */ MCD_OPC_CheckPredicate, + 3, + 36, + 125, + 1, // Skip to: 104527 + /* 6955 */ MCD_OPC_Decode, + 167, + 44, + 45, // Opcode: UQADD_ZZZ_H + /* 6959 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 6973 + /* 6964 */ MCD_OPC_CheckPredicate, + 3, + 22, + 125, + 1, // Skip to: 104527 + /* 6969 */ MCD_OPC_Decode, + 134, + 36, + 45, // Opcode: SQSUB_ZZZ_H + /* 6973 */ MCD_OPC_FilterValue, + 7, + 13, + 125, + 1, // Skip to: 104527 + /* 6978 */ MCD_OPC_CheckPredicate, + 3, + 8, + 125, + 1, // Skip to: 104527 + /* 6983 */ MCD_OPC_Decode, + 193, + 45, + 45, // Opcode: UQSUB_ZZZ_H + /* 6987 */ MCD_OPC_FilterValue, + 2, + 87, + 0, + 0, // Skip to: 7079 + /* 6992 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 6995 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7009 + /* 7000 */ MCD_OPC_CheckPredicate, + 3, + 242, + 124, + 1, // Skip to: 104527 + /* 7005 */ MCD_OPC_Decode, + 209, + 7, + 45, // Opcode: ADD_ZZZ_S + /* 7009 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7023 + /* 7014 */ MCD_OPC_CheckPredicate, + 3, + 228, + 124, + 1, // Skip to: 104527 + /* 7019 */ MCD_OPC_Decode, + 215, + 40, + 45, // Opcode: SUB_ZZZ_S + /* 7023 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 7037 + /* 7028 */ MCD_OPC_CheckPredicate, + 3, + 214, + 124, + 1, // Skip to: 104527 + /* 7033 */ MCD_OPC_Decode, + 147, + 33, + 45, // Opcode: SQADD_ZZZ_S + /* 7037 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 7051 + /* 7042 */ MCD_OPC_CheckPredicate, + 3, + 200, + 124, + 1, // Skip to: 104527 + /* 7047 */ MCD_OPC_Decode, + 168, + 44, + 45, // Opcode: UQADD_ZZZ_S + /* 7051 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 7065 + /* 7056 */ MCD_OPC_CheckPredicate, + 3, + 186, + 124, + 1, // Skip to: 104527 + /* 7061 */ MCD_OPC_Decode, + 135, + 36, + 45, // Opcode: SQSUB_ZZZ_S + /* 7065 */ MCD_OPC_FilterValue, + 7, + 177, + 124, + 1, // Skip to: 104527 + /* 7070 */ MCD_OPC_CheckPredicate, + 3, + 172, + 124, + 1, // Skip to: 104527 + /* 7075 */ MCD_OPC_Decode, + 194, + 45, + 45, // Opcode: UQSUB_ZZZ_S + /* 7079 */ MCD_OPC_FilterValue, + 3, + 87, + 0, + 0, // Skip to: 7171 + /* 7084 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 7087 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7101 + /* 7092 */ MCD_OPC_CheckPredicate, + 3, + 150, + 124, + 1, // Skip to: 104527 + /* 7097 */ MCD_OPC_Decode, + 207, + 7, + 45, // Opcode: ADD_ZZZ_D + /* 7101 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7115 + /* 7106 */ MCD_OPC_CheckPredicate, + 3, + 136, + 124, + 1, // Skip to: 104527 + /* 7111 */ MCD_OPC_Decode, + 213, + 40, + 45, // Opcode: SUB_ZZZ_D + /* 7115 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 7129 + /* 7120 */ MCD_OPC_CheckPredicate, + 3, + 122, + 124, + 1, // Skip to: 104527 + /* 7125 */ MCD_OPC_Decode, + 145, + 33, + 45, // Opcode: SQADD_ZZZ_D + /* 7129 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 7143 + /* 7134 */ MCD_OPC_CheckPredicate, + 3, + 108, + 124, + 1, // Skip to: 104527 + /* 7139 */ MCD_OPC_Decode, + 166, + 44, + 45, // Opcode: UQADD_ZZZ_D + /* 7143 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 7157 + /* 7148 */ MCD_OPC_CheckPredicate, + 3, + 94, + 124, + 1, // Skip to: 104527 + /* 7153 */ MCD_OPC_Decode, + 133, + 36, + 45, // Opcode: SQSUB_ZZZ_D + /* 7157 */ MCD_OPC_FilterValue, + 7, + 85, + 124, + 1, // Skip to: 104527 + /* 7162 */ MCD_OPC_CheckPredicate, + 3, + 80, + 124, + 1, // Skip to: 104527 + /* 7167 */ MCD_OPC_Decode, + 192, + 45, + 45, // Opcode: UQSUB_ZZZ_D + /* 7171 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 7185 + /* 7176 */ MCD_OPC_CheckPredicate, + 3, + 66, + 124, + 1, // Skip to: 104527 + /* 7181 */ MCD_OPC_Decode, + 196, + 12, + 46, // Opcode: EXT_ZZI + /* 7185 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 7199 + /* 7190 */ MCD_OPC_CheckPredicate, + 4, + 52, + 124, + 1, // Skip to: 104527 + /* 7195 */ MCD_OPC_Decode, + 197, + 12, + 47, // Opcode: EXT_ZZI_B + /* 7199 */ MCD_OPC_FilterValue, + 6, + 43, + 124, + 1, // Skip to: 104527 + /* 7204 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 7207 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7221 + /* 7212 */ MCD_OPC_CheckPredicate, + 5, + 30, + 124, + 1, // Skip to: 104527 + /* 7217 */ MCD_OPC_Decode, + 254, + 47, + 45, // Opcode: ZIP1_ZZZ_Q + /* 7221 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7235 + /* 7226 */ MCD_OPC_CheckPredicate, + 5, + 16, + 124, + 1, // Skip to: 104527 + /* 7231 */ MCD_OPC_Decode, + 142, + 48, + 45, // Opcode: ZIP2_ZZZ_Q + /* 7235 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7249 + /* 7240 */ MCD_OPC_CheckPredicate, + 5, + 2, + 124, + 1, // Skip to: 104527 + /* 7245 */ MCD_OPC_Decode, + 131, + 47, + 45, // Opcode: UZP1_ZZZ_Q + /* 7249 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 7263 + /* 7254 */ MCD_OPC_CheckPredicate, + 5, + 244, + 123, + 1, // Skip to: 104527 + /* 7259 */ MCD_OPC_Decode, + 147, + 47, + 45, // Opcode: UZP2_ZZZ_Q + /* 7263 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 7277 + /* 7268 */ MCD_OPC_CheckPredicate, + 5, + 230, + 123, + 1, // Skip to: 104527 + /* 7273 */ MCD_OPC_Decode, + 190, + 41, + 45, // Opcode: TRN1_ZZZ_Q + /* 7277 */ MCD_OPC_FilterValue, + 7, + 221, + 123, + 1, // Skip to: 104527 + /* 7282 */ MCD_OPC_CheckPredicate, + 5, + 216, + 123, + 1, // Skip to: 104527 + /* 7287 */ MCD_OPC_Decode, + 206, + 41, + 45, // Opcode: TRN2_ZZZ_Q + /* 7291 */ MCD_OPC_FilterValue, + 1, + 207, + 123, + 1, // Skip to: 104527 + /* 7296 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 7299 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 7443 + /* 7304 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7307 */ MCD_OPC_FilterValue, + 0, + 110, + 0, + 0, // Skip to: 7422 + /* 7312 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 7315 */ MCD_OPC_FilterValue, + 0, + 81, + 0, + 0, // Skip to: 7401 + /* 7320 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 7323 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 7380 + /* 7328 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 7331 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 7359 + /* 7336 */ MCD_OPC_CheckPredicate, + 3, + 162, + 123, + 1, // Skip to: 104527 + /* 7341 */ MCD_OPC_CheckField, + 24, + 2, + 1, + 155, + 123, + 1, // Skip to: 104527 + /* 7348 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 148, + 123, + 1, // Skip to: 104527 + /* 7355 */ MCD_OPC_Decode, + 135, + 12, + 48, // Opcode: DUP_ZZI_Q + /* 7359 */ MCD_OPC_FilterValue, + 1, + 139, + 123, + 1, // Skip to: 104527 + /* 7364 */ MCD_OPC_CheckPredicate, + 3, + 134, + 123, + 1, // Skip to: 104527 + /* 7369 */ MCD_OPC_CheckField, + 24, + 2, + 1, + 127, + 123, + 1, // Skip to: 104527 + /* 7376 */ MCD_OPC_Decode, + 133, + 12, + 49, // Opcode: DUP_ZZI_D + /* 7380 */ MCD_OPC_FilterValue, + 1, + 118, + 123, + 1, // Skip to: 104527 + /* 7385 */ MCD_OPC_CheckPredicate, + 3, + 113, + 123, + 1, // Skip to: 104527 + /* 7390 */ MCD_OPC_CheckField, + 24, + 2, + 1, + 106, + 123, + 1, // Skip to: 104527 + /* 7397 */ MCD_OPC_Decode, + 136, + 12, + 50, // Opcode: DUP_ZZI_S + /* 7401 */ MCD_OPC_FilterValue, + 1, + 97, + 123, + 1, // Skip to: 104527 + /* 7406 */ MCD_OPC_CheckPredicate, + 3, + 92, + 123, + 1, // Skip to: 104527 + /* 7411 */ MCD_OPC_CheckField, + 24, + 2, + 1, + 85, + 123, + 1, // Skip to: 104527 + /* 7418 */ MCD_OPC_Decode, + 134, + 12, + 51, // Opcode: DUP_ZZI_H + /* 7422 */ MCD_OPC_FilterValue, + 1, + 76, + 123, + 1, // Skip to: 104527 + /* 7427 */ MCD_OPC_CheckPredicate, + 3, + 71, + 123, + 1, // Skip to: 104527 + /* 7432 */ MCD_OPC_CheckField, + 24, + 2, + 1, + 64, + 123, + 1, // Skip to: 104527 + /* 7439 */ MCD_OPC_Decode, + 132, + 12, + 52, // Opcode: DUP_ZZI_B + /* 7443 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 7507 + /* 7448 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 7451 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 7465 + /* 7456 */ MCD_OPC_CheckPredicate, + 4, + 42, + 123, + 1, // Skip to: 104527 + /* 7461 */ MCD_OPC_Decode, + 149, + 41, + 53, // Opcode: TBL_ZZZZ_B + /* 7465 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 7479 + /* 7470 */ MCD_OPC_CheckPredicate, + 4, + 28, + 123, + 1, // Skip to: 104527 + /* 7475 */ MCD_OPC_Decode, + 151, + 41, + 53, // Opcode: TBL_ZZZZ_H + /* 7479 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 7493 + /* 7484 */ MCD_OPC_CheckPredicate, + 4, + 14, + 123, + 1, // Skip to: 104527 + /* 7489 */ MCD_OPC_Decode, + 152, + 41, + 53, // Opcode: TBL_ZZZZ_S + /* 7493 */ MCD_OPC_FilterValue, + 7, + 5, + 123, + 1, // Skip to: 104527 + /* 7498 */ MCD_OPC_CheckPredicate, + 4, + 0, + 123, + 1, // Skip to: 104527 + /* 7503 */ MCD_OPC_Decode, + 150, + 41, + 53, // Opcode: TBL_ZZZZ_D + /* 7507 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 7571 + /* 7512 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 7515 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 7529 + /* 7520 */ MCD_OPC_CheckPredicate, + 4, + 234, + 122, + 1, // Skip to: 104527 + /* 7525 */ MCD_OPC_Decode, + 167, + 41, + 54, // Opcode: TBX_ZZZ_B + /* 7529 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 7543 + /* 7534 */ MCD_OPC_CheckPredicate, + 4, + 220, + 122, + 1, // Skip to: 104527 + /* 7539 */ MCD_OPC_Decode, + 169, + 41, + 54, // Opcode: TBX_ZZZ_H + /* 7543 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 7557 + /* 7548 */ MCD_OPC_CheckPredicate, + 4, + 206, + 122, + 1, // Skip to: 104527 + /* 7553 */ MCD_OPC_Decode, + 170, + 41, + 54, // Opcode: TBX_ZZZ_S + /* 7557 */ MCD_OPC_FilterValue, + 7, + 197, + 122, + 1, // Skip to: 104527 + /* 7562 */ MCD_OPC_CheckPredicate, + 4, + 192, + 122, + 1, // Skip to: 104527 + /* 7567 */ MCD_OPC_Decode, + 168, + 41, + 54, // Opcode: TBX_ZZZ_D + /* 7571 */ MCD_OPC_FilterValue, + 4, + 115, + 0, + 0, // Skip to: 7691 + /* 7576 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 7579 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7593 + /* 7584 */ MCD_OPC_CheckPredicate, + 3, + 170, + 122, + 1, // Skip to: 104527 + /* 7589 */ MCD_OPC_Decode, + 135, + 8, + 45, // Opcode: AND_ZZZ + /* 7593 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7607 + /* 7598 */ MCD_OPC_CheckPredicate, + 3, + 156, + 122, + 1, // Skip to: 104527 + /* 7603 */ MCD_OPC_Decode, + 157, + 28, + 45, // Opcode: ORR_ZZZ + /* 7607 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7621 + /* 7612 */ MCD_OPC_CheckPredicate, + 3, + 142, + 122, + 1, // Skip to: 104527 + /* 7617 */ MCD_OPC_Decode, + 178, + 12, + 45, // Opcode: EOR_ZZZ + /* 7621 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 7635 + /* 7626 */ MCD_OPC_CheckPredicate, + 3, + 128, + 122, + 1, // Skip to: 104527 + /* 7631 */ MCD_OPC_Decode, + 229, + 8, + 45, // Opcode: BIC_ZZZ + /* 7635 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 7649 + /* 7640 */ MCD_OPC_CheckPredicate, + 3, + 114, + 122, + 1, // Skip to: 104527 + /* 7645 */ MCD_OPC_Decode, + 153, + 41, + 45, // Opcode: TBL_ZZZ_B + /* 7649 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 7663 + /* 7654 */ MCD_OPC_CheckPredicate, + 3, + 100, + 122, + 1, // Skip to: 104527 + /* 7659 */ MCD_OPC_Decode, + 155, + 41, + 45, // Opcode: TBL_ZZZ_H + /* 7663 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 7677 + /* 7668 */ MCD_OPC_CheckPredicate, + 3, + 86, + 122, + 1, // Skip to: 104527 + /* 7673 */ MCD_OPC_Decode, + 156, + 41, + 45, // Opcode: TBL_ZZZ_S + /* 7677 */ MCD_OPC_FilterValue, + 7, + 77, + 122, + 1, // Skip to: 104527 + /* 7682 */ MCD_OPC_CheckPredicate, + 3, + 72, + 122, + 1, // Skip to: 104527 + /* 7687 */ MCD_OPC_Decode, + 154, + 41, + 45, // Opcode: TBL_ZZZ_D + /* 7691 */ MCD_OPC_FilterValue, + 5, + 82, + 0, + 0, // Skip to: 7778 + /* 7696 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 7699 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 7764 + /* 7704 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 7707 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 7750 + /* 7712 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7715 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 7736 + /* 7720 */ MCD_OPC_CheckPredicate, + 4, + 34, + 122, + 1, // Skip to: 104527 + /* 7725 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 27, + 122, + 1, // Skip to: 104527 + /* 7732 */ MCD_OPC_Decode, + 233, + 47, + 55, // Opcode: XAR_ZZZI_B + /* 7736 */ MCD_OPC_FilterValue, + 1, + 18, + 122, + 1, // Skip to: 104527 + /* 7741 */ MCD_OPC_CheckPredicate, + 4, + 13, + 122, + 1, // Skip to: 104527 + /* 7746 */ MCD_OPC_Decode, + 235, + 47, + 56, // Opcode: XAR_ZZZI_H + /* 7750 */ MCD_OPC_FilterValue, + 1, + 4, + 122, + 1, // Skip to: 104527 + /* 7755 */ MCD_OPC_CheckPredicate, + 4, + 255, + 121, + 1, // Skip to: 104527 + /* 7760 */ MCD_OPC_Decode, + 236, + 47, + 57, // Opcode: XAR_ZZZI_S + /* 7764 */ MCD_OPC_FilterValue, + 1, + 246, + 121, + 1, // Skip to: 104527 + /* 7769 */ MCD_OPC_CheckPredicate, + 4, + 241, + 121, + 1, // Skip to: 104527 + /* 7774 */ MCD_OPC_Decode, + 234, + 47, + 58, // Opcode: XAR_ZZZI_D + /* 7778 */ MCD_OPC_FilterValue, + 6, + 199, + 1, + 0, // Skip to: 8238 + /* 7783 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 7786 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7800 + /* 7791 */ MCD_OPC_CheckPredicate, + 4, + 219, + 121, + 1, // Skip to: 104527 + /* 7796 */ MCD_OPC_Decode, + 154, + 12, + 59, // Opcode: EOR3_ZZZZ + /* 7800 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7814 + /* 7805 */ MCD_OPC_CheckPredicate, + 4, + 205, + 121, + 1, // Skip to: 104527 + /* 7810 */ MCD_OPC_Decode, + 183, + 8, + 59, // Opcode: BCAX_ZZZZ + /* 7814 */ MCD_OPC_FilterValue, + 4, + 59, + 0, + 0, // Skip to: 7878 + /* 7819 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 7822 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7836 + /* 7827 */ MCD_OPC_CheckPredicate, + 3, + 183, + 121, + 1, // Skip to: 104527 + /* 7832 */ MCD_OPC_Decode, + 128, + 12, + 60, // Opcode: DUP_ZR_B + /* 7836 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 7850 + /* 7841 */ MCD_OPC_CheckPredicate, + 3, + 169, + 121, + 1, // Skip to: 104527 + /* 7846 */ MCD_OPC_Decode, + 175, + 21, + 61, // Opcode: INSR_ZR_B + /* 7850 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 7864 + /* 7855 */ MCD_OPC_CheckPredicate, + 3, + 155, + 121, + 1, // Skip to: 104527 + /* 7860 */ MCD_OPC_Decode, + 179, + 21, + 62, // Opcode: INSR_ZV_B + /* 7864 */ MCD_OPC_FilterValue, + 24, + 146, + 121, + 1, // Skip to: 104527 + /* 7869 */ MCD_OPC_CheckPredicate, + 3, + 141, + 121, + 1, // Skip to: 104527 + /* 7874 */ MCD_OPC_Decode, + 187, + 29, + 63, // Opcode: REV_ZZ_B + /* 7878 */ MCD_OPC_FilterValue, + 5, + 115, + 0, + 0, // Skip to: 7998 + /* 7883 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 7886 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7900 + /* 7891 */ MCD_OPC_CheckPredicate, + 3, + 119, + 121, + 1, // Skip to: 104527 + /* 7896 */ MCD_OPC_Decode, + 130, + 12, + 60, // Opcode: DUP_ZR_H + /* 7900 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 7914 + /* 7905 */ MCD_OPC_CheckPredicate, + 3, + 105, + 121, + 1, // Skip to: 104527 + /* 7910 */ MCD_OPC_Decode, + 177, + 21, + 61, // Opcode: INSR_ZR_H + /* 7914 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 7928 + /* 7919 */ MCD_OPC_CheckPredicate, + 3, + 91, + 121, + 1, // Skip to: 104527 + /* 7924 */ MCD_OPC_Decode, + 235, + 40, + 63, // Opcode: SUNPKLO_ZZ_H + /* 7928 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 7942 + /* 7933 */ MCD_OPC_CheckPredicate, + 3, + 77, + 121, + 1, // Skip to: 104527 + /* 7938 */ MCD_OPC_Decode, + 232, + 40, + 63, // Opcode: SUNPKHI_ZZ_H + /* 7942 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 7956 + /* 7947 */ MCD_OPC_CheckPredicate, + 3, + 63, + 121, + 1, // Skip to: 104527 + /* 7952 */ MCD_OPC_Decode, + 244, + 46, + 63, // Opcode: UUNPKLO_ZZ_H + /* 7956 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 7970 + /* 7961 */ MCD_OPC_CheckPredicate, + 3, + 49, + 121, + 1, // Skip to: 104527 + /* 7966 */ MCD_OPC_Decode, + 241, + 46, + 63, // Opcode: UUNPKHI_ZZ_H + /* 7970 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 7984 + /* 7975 */ MCD_OPC_CheckPredicate, + 3, + 35, + 121, + 1, // Skip to: 104527 + /* 7980 */ MCD_OPC_Decode, + 181, + 21, + 62, // Opcode: INSR_ZV_H + /* 7984 */ MCD_OPC_FilterValue, + 24, + 26, + 121, + 1, // Skip to: 104527 + /* 7989 */ MCD_OPC_CheckPredicate, + 3, + 21, + 121, + 1, // Skip to: 104527 + /* 7994 */ MCD_OPC_Decode, + 189, + 29, + 63, // Opcode: REV_ZZ_H + /* 7998 */ MCD_OPC_FilterValue, + 6, + 115, + 0, + 0, // Skip to: 8118 + /* 8003 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 8006 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8020 + /* 8011 */ MCD_OPC_CheckPredicate, + 3, + 255, + 120, + 1, // Skip to: 104527 + /* 8016 */ MCD_OPC_Decode, + 131, + 12, + 60, // Opcode: DUP_ZR_S + /* 8020 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 8034 + /* 8025 */ MCD_OPC_CheckPredicate, + 3, + 241, + 120, + 1, // Skip to: 104527 + /* 8030 */ MCD_OPC_Decode, + 178, + 21, + 61, // Opcode: INSR_ZR_S + /* 8034 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 8048 + /* 8039 */ MCD_OPC_CheckPredicate, + 3, + 227, + 120, + 1, // Skip to: 104527 + /* 8044 */ MCD_OPC_Decode, + 236, + 40, + 63, // Opcode: SUNPKLO_ZZ_S + /* 8048 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 8062 + /* 8053 */ MCD_OPC_CheckPredicate, + 3, + 213, + 120, + 1, // Skip to: 104527 + /* 8058 */ MCD_OPC_Decode, + 233, + 40, + 63, // Opcode: SUNPKHI_ZZ_S + /* 8062 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 8076 + /* 8067 */ MCD_OPC_CheckPredicate, + 3, + 199, + 120, + 1, // Skip to: 104527 + /* 8072 */ MCD_OPC_Decode, + 245, + 46, + 63, // Opcode: UUNPKLO_ZZ_S + /* 8076 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 8090 + /* 8081 */ MCD_OPC_CheckPredicate, + 3, + 185, + 120, + 1, // Skip to: 104527 + /* 8086 */ MCD_OPC_Decode, + 242, + 46, + 63, // Opcode: UUNPKHI_ZZ_S + /* 8090 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 8104 + /* 8095 */ MCD_OPC_CheckPredicate, + 3, + 171, + 120, + 1, // Skip to: 104527 + /* 8100 */ MCD_OPC_Decode, + 182, + 21, + 62, // Opcode: INSR_ZV_S + /* 8104 */ MCD_OPC_FilterValue, + 24, + 162, + 120, + 1, // Skip to: 104527 + /* 8109 */ MCD_OPC_CheckPredicate, + 3, + 157, + 120, + 1, // Skip to: 104527 + /* 8114 */ MCD_OPC_Decode, + 190, + 29, + 63, // Opcode: REV_ZZ_S + /* 8118 */ MCD_OPC_FilterValue, + 7, + 148, + 120, + 1, // Skip to: 104527 + /* 8123 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 8126 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8140 + /* 8131 */ MCD_OPC_CheckPredicate, + 3, + 135, + 120, + 1, // Skip to: 104527 + /* 8136 */ MCD_OPC_Decode, + 129, + 12, + 64, // Opcode: DUP_ZR_D + /* 8140 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 8154 + /* 8145 */ MCD_OPC_CheckPredicate, + 3, + 121, + 120, + 1, // Skip to: 104527 + /* 8150 */ MCD_OPC_Decode, + 176, + 21, + 65, // Opcode: INSR_ZR_D + /* 8154 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 8168 + /* 8159 */ MCD_OPC_CheckPredicate, + 3, + 107, + 120, + 1, // Skip to: 104527 + /* 8164 */ MCD_OPC_Decode, + 234, + 40, + 63, // Opcode: SUNPKLO_ZZ_D + /* 8168 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 8182 + /* 8173 */ MCD_OPC_CheckPredicate, + 3, + 93, + 120, + 1, // Skip to: 104527 + /* 8178 */ MCD_OPC_Decode, + 231, + 40, + 63, // Opcode: SUNPKHI_ZZ_D + /* 8182 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 8196 + /* 8187 */ MCD_OPC_CheckPredicate, + 3, + 79, + 120, + 1, // Skip to: 104527 + /* 8192 */ MCD_OPC_Decode, + 243, + 46, + 63, // Opcode: UUNPKLO_ZZ_D + /* 8196 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 8210 + /* 8201 */ MCD_OPC_CheckPredicate, + 3, + 65, + 120, + 1, // Skip to: 104527 + /* 8206 */ MCD_OPC_Decode, + 240, + 46, + 63, // Opcode: UUNPKHI_ZZ_D + /* 8210 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 8224 + /* 8215 */ MCD_OPC_CheckPredicate, + 3, + 51, + 120, + 1, // Skip to: 104527 + /* 8220 */ MCD_OPC_Decode, + 180, + 21, + 62, // Opcode: INSR_ZV_D + /* 8224 */ MCD_OPC_FilterValue, + 24, + 42, + 120, + 1, // Skip to: 104527 + /* 8229 */ MCD_OPC_CheckPredicate, + 3, + 37, + 120, + 1, // Skip to: 104527 + /* 8234 */ MCD_OPC_Decode, + 188, + 29, + 63, // Opcode: REV_ZZ_D + /* 8238 */ MCD_OPC_FilterValue, + 7, + 28, + 120, + 1, // Skip to: 104527 + /* 8243 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 8246 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8260 + /* 8251 */ MCD_OPC_CheckPredicate, + 4, + 15, + 120, + 1, // Skip to: 104527 + /* 8256 */ MCD_OPC_Decode, + 140, + 9, + 59, // Opcode: BSL_ZZZZ + /* 8260 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8274 + /* 8265 */ MCD_OPC_CheckPredicate, + 4, + 1, + 120, + 1, // Skip to: 104527 + /* 8270 */ MCD_OPC_Decode, + 138, + 9, + 59, // Opcode: BSL1N_ZZZZ + /* 8274 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8288 + /* 8279 */ MCD_OPC_CheckPredicate, + 4, + 243, + 119, + 1, // Skip to: 104527 + /* 8284 */ MCD_OPC_Decode, + 139, + 9, + 59, // Opcode: BSL2N_ZZZZ + /* 8288 */ MCD_OPC_FilterValue, + 3, + 234, + 119, + 1, // Skip to: 104527 + /* 8293 */ MCD_OPC_CheckPredicate, + 4, + 229, + 119, + 1, // Skip to: 104527 + /* 8298 */ MCD_OPC_Decode, + 245, + 27, + 59, // Opcode: NBSL_ZZZZ + /* 8302 */ MCD_OPC_FilterValue, + 1, + 81, + 8, + 0, // Skip to: 10436 + /* 8307 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 8310 */ MCD_OPC_FilterValue, + 0, + 197, + 0, + 0, // Skip to: 8512 + /* 8315 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 8318 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 8354 + /* 8323 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8326 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8340 + /* 8331 */ MCD_OPC_CheckPredicate, + 3, + 191, + 119, + 1, // Skip to: 104527 + /* 8336 */ MCD_OPC_Decode, + 149, + 21, + 66, // Opcode: INDEX_II_B + /* 8340 */ MCD_OPC_FilterValue, + 1, + 182, + 119, + 1, // Skip to: 104527 + /* 8345 */ MCD_OPC_CheckPredicate, + 3, + 177, + 119, + 1, // Skip to: 104527 + /* 8350 */ MCD_OPC_Decode, + 157, + 21, + 67, // Opcode: INDEX_RI_B + /* 8354 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 8390 + /* 8359 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8362 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8376 + /* 8367 */ MCD_OPC_CheckPredicate, + 3, + 155, + 119, + 1, // Skip to: 104527 + /* 8372 */ MCD_OPC_Decode, + 153, + 21, + 68, // Opcode: INDEX_IR_B + /* 8376 */ MCD_OPC_FilterValue, + 1, + 146, + 119, + 1, // Skip to: 104527 + /* 8381 */ MCD_OPC_CheckPredicate, + 3, + 141, + 119, + 1, // Skip to: 104527 + /* 8386 */ MCD_OPC_Decode, + 161, + 21, + 69, // Opcode: INDEX_RR_B + /* 8390 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8404 + /* 8395 */ MCD_OPC_CheckPredicate, + 3, + 127, + 119, + 1, // Skip to: 104527 + /* 8400 */ MCD_OPC_Decode, + 185, + 7, + 70, // Opcode: ADDVL_XXI + /* 8404 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 8440 + /* 8409 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8412 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8426 + /* 8417 */ MCD_OPC_CheckPredicate, + 4, + 105, + 119, + 1, // Skip to: 104527 + /* 8422 */ MCD_OPC_Decode, + 223, + 27, + 45, // Opcode: MUL_ZZZ_B + /* 8426 */ MCD_OPC_FilterValue, + 1, + 96, + 119, + 1, // Skip to: 104527 + /* 8431 */ MCD_OPC_CheckPredicate, + 4, + 91, + 119, + 1, // Skip to: 104527 + /* 8436 */ MCD_OPC_Decode, + 195, + 28, + 45, // Opcode: PMUL_ZZZ_B + /* 8440 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 8476 + /* 8445 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8448 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8462 + /* 8453 */ MCD_OPC_CheckPredicate, + 4, + 69, + 119, + 1, // Skip to: 104527 + /* 8458 */ MCD_OPC_Decode, + 216, + 32, + 45, // Opcode: SMULH_ZZZ_B + /* 8462 */ MCD_OPC_FilterValue, + 1, + 60, + 119, + 1, // Skip to: 104527 + /* 8467 */ MCD_OPC_CheckPredicate, + 4, + 55, + 119, + 1, // Skip to: 104527 + /* 8472 */ MCD_OPC_Decode, + 132, + 44, + 45, // Opcode: UMULH_ZZZ_B + /* 8476 */ MCD_OPC_FilterValue, + 6, + 46, + 119, + 1, // Skip to: 104527 + /* 8481 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8484 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8498 + /* 8489 */ MCD_OPC_CheckPredicate, + 4, + 33, + 119, + 1, // Skip to: 104527 + /* 8494 */ MCD_OPC_Decode, + 238, + 33, + 45, // Opcode: SQDMULH_ZZZ_B + /* 8498 */ MCD_OPC_FilterValue, + 1, + 24, + 119, + 1, // Skip to: 104527 + /* 8503 */ MCD_OPC_CheckPredicate, + 4, + 19, + 119, + 1, // Skip to: 104527 + /* 8508 */ MCD_OPC_Decode, + 232, + 34, + 45, // Opcode: SQRDMULH_ZZZ_B + /* 8512 */ MCD_OPC_FilterValue, + 1, + 182, + 0, + 0, // Skip to: 8699 + /* 8517 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 8520 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 8556 + /* 8525 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8528 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8542 + /* 8533 */ MCD_OPC_CheckPredicate, + 3, + 245, + 118, + 1, // Skip to: 104527 + /* 8538 */ MCD_OPC_Decode, + 151, + 21, + 66, // Opcode: INDEX_II_H + /* 8542 */ MCD_OPC_FilterValue, + 1, + 236, + 118, + 1, // Skip to: 104527 + /* 8547 */ MCD_OPC_CheckPredicate, + 3, + 231, + 118, + 1, // Skip to: 104527 + /* 8552 */ MCD_OPC_Decode, + 159, + 21, + 67, // Opcode: INDEX_RI_H + /* 8556 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 8592 + /* 8561 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8564 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8578 + /* 8569 */ MCD_OPC_CheckPredicate, + 3, + 209, + 118, + 1, // Skip to: 104527 + /* 8574 */ MCD_OPC_Decode, + 155, + 21, + 68, // Opcode: INDEX_IR_H + /* 8578 */ MCD_OPC_FilterValue, + 1, + 200, + 118, + 1, // Skip to: 104527 + /* 8583 */ MCD_OPC_CheckPredicate, + 3, + 195, + 118, + 1, // Skip to: 104527 + /* 8588 */ MCD_OPC_Decode, + 163, + 21, + 69, // Opcode: INDEX_RR_H + /* 8592 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8606 + /* 8597 */ MCD_OPC_CheckPredicate, + 3, + 181, + 118, + 1, // Skip to: 104527 + /* 8602 */ MCD_OPC_Decode, + 163, + 7, + 70, // Opcode: ADDPL_XXI + /* 8606 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 8627 + /* 8611 */ MCD_OPC_CheckPredicate, + 4, + 167, + 118, + 1, // Skip to: 104527 + /* 8616 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 160, + 118, + 1, // Skip to: 104527 + /* 8623 */ MCD_OPC_Decode, + 225, + 27, + 45, // Opcode: MUL_ZZZ_H + /* 8627 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 8663 + /* 8632 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8635 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8649 + /* 8640 */ MCD_OPC_CheckPredicate, + 4, + 138, + 118, + 1, // Skip to: 104527 + /* 8645 */ MCD_OPC_Decode, + 218, + 32, + 45, // Opcode: SMULH_ZZZ_H + /* 8649 */ MCD_OPC_FilterValue, + 1, + 129, + 118, + 1, // Skip to: 104527 + /* 8654 */ MCD_OPC_CheckPredicate, + 4, + 124, + 118, + 1, // Skip to: 104527 + /* 8659 */ MCD_OPC_Decode, + 134, + 44, + 45, // Opcode: UMULH_ZZZ_H + /* 8663 */ MCD_OPC_FilterValue, + 6, + 115, + 118, + 1, // Skip to: 104527 + /* 8668 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8671 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8685 + /* 8676 */ MCD_OPC_CheckPredicate, + 4, + 102, + 118, + 1, // Skip to: 104527 + /* 8681 */ MCD_OPC_Decode, + 240, + 33, + 45, // Opcode: SQDMULH_ZZZ_H + /* 8685 */ MCD_OPC_FilterValue, + 1, + 93, + 118, + 1, // Skip to: 104527 + /* 8690 */ MCD_OPC_CheckPredicate, + 4, + 88, + 118, + 1, // Skip to: 104527 + /* 8695 */ MCD_OPC_Decode, + 234, + 34, + 45, // Opcode: SQRDMULH_ZZZ_H + /* 8699 */ MCD_OPC_FilterValue, + 2, + 189, + 0, + 0, // Skip to: 8893 + /* 8704 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 8707 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 8743 + /* 8712 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8715 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8729 + /* 8720 */ MCD_OPC_CheckPredicate, + 3, + 58, + 118, + 1, // Skip to: 104527 + /* 8725 */ MCD_OPC_Decode, + 152, + 21, + 66, // Opcode: INDEX_II_S + /* 8729 */ MCD_OPC_FilterValue, + 1, + 49, + 118, + 1, // Skip to: 104527 + /* 8734 */ MCD_OPC_CheckPredicate, + 3, + 44, + 118, + 1, // Skip to: 104527 + /* 8739 */ MCD_OPC_Decode, + 160, + 21, + 67, // Opcode: INDEX_RI_S + /* 8743 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 8779 + /* 8748 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8751 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8765 + /* 8756 */ MCD_OPC_CheckPredicate, + 3, + 22, + 118, + 1, // Skip to: 104527 + /* 8761 */ MCD_OPC_Decode, + 156, + 21, + 68, // Opcode: INDEX_IR_S + /* 8765 */ MCD_OPC_FilterValue, + 1, + 13, + 118, + 1, // Skip to: 104527 + /* 8770 */ MCD_OPC_CheckPredicate, + 3, + 8, + 118, + 1, // Skip to: 104527 + /* 8775 */ MCD_OPC_Decode, + 164, + 21, + 69, // Opcode: INDEX_RR_S + /* 8779 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 8800 + /* 8784 */ MCD_OPC_CheckPredicate, + 3, + 250, + 117, + 1, // Skip to: 104527 + /* 8789 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 243, + 117, + 1, // Skip to: 104527 + /* 8796 */ MCD_OPC_Decode, + 155, + 29, + 71, // Opcode: RDVLI_XI + /* 8800 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 8821 + /* 8805 */ MCD_OPC_CheckPredicate, + 4, + 229, + 117, + 1, // Skip to: 104527 + /* 8810 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 222, + 117, + 1, // Skip to: 104527 + /* 8817 */ MCD_OPC_Decode, + 226, + 27, + 45, // Opcode: MUL_ZZZ_S + /* 8821 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 8857 + /* 8826 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8829 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8843 + /* 8834 */ MCD_OPC_CheckPredicate, + 4, + 200, + 117, + 1, // Skip to: 104527 + /* 8839 */ MCD_OPC_Decode, + 219, + 32, + 45, // Opcode: SMULH_ZZZ_S + /* 8843 */ MCD_OPC_FilterValue, + 1, + 191, + 117, + 1, // Skip to: 104527 + /* 8848 */ MCD_OPC_CheckPredicate, + 4, + 186, + 117, + 1, // Skip to: 104527 + /* 8853 */ MCD_OPC_Decode, + 135, + 44, + 45, // Opcode: UMULH_ZZZ_S + /* 8857 */ MCD_OPC_FilterValue, + 6, + 177, + 117, + 1, // Skip to: 104527 + /* 8862 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 8865 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8879 + /* 8870 */ MCD_OPC_CheckPredicate, + 4, + 164, + 117, + 1, // Skip to: 104527 + /* 8875 */ MCD_OPC_Decode, + 241, + 33, + 45, // Opcode: SQDMULH_ZZZ_S + /* 8879 */ MCD_OPC_FilterValue, + 1, + 155, + 117, + 1, // Skip to: 104527 + /* 8884 */ MCD_OPC_CheckPredicate, + 4, + 150, + 117, + 1, // Skip to: 104527 + /* 8889 */ MCD_OPC_Decode, + 235, + 34, + 45, // Opcode: SQRDMULH_ZZZ_S + /* 8893 */ MCD_OPC_FilterValue, + 3, + 129, + 0, + 0, // Skip to: 9027 + /* 8898 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 8901 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8915 + /* 8906 */ MCD_OPC_CheckPredicate, + 3, + 128, + 117, + 1, // Skip to: 104527 + /* 8911 */ MCD_OPC_Decode, + 150, + 21, + 66, // Opcode: INDEX_II_D + /* 8915 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8929 + /* 8920 */ MCD_OPC_CheckPredicate, + 3, + 114, + 117, + 1, // Skip to: 104527 + /* 8925 */ MCD_OPC_Decode, + 158, + 21, + 72, // Opcode: INDEX_RI_D + /* 8929 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8943 + /* 8934 */ MCD_OPC_CheckPredicate, + 3, + 100, + 117, + 1, // Skip to: 104527 + /* 8939 */ MCD_OPC_Decode, + 154, + 21, + 73, // Opcode: INDEX_IR_D + /* 8943 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 8957 + /* 8948 */ MCD_OPC_CheckPredicate, + 3, + 86, + 117, + 1, // Skip to: 104527 + /* 8953 */ MCD_OPC_Decode, + 162, + 21, + 74, // Opcode: INDEX_RR_D + /* 8957 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 8971 + /* 8962 */ MCD_OPC_CheckPredicate, + 4, + 72, + 117, + 1, // Skip to: 104527 + /* 8967 */ MCD_OPC_Decode, + 224, + 27, + 45, // Opcode: MUL_ZZZ_D + /* 8971 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 8985 + /* 8976 */ MCD_OPC_CheckPredicate, + 4, + 58, + 117, + 1, // Skip to: 104527 + /* 8981 */ MCD_OPC_Decode, + 217, + 32, + 45, // Opcode: SMULH_ZZZ_D + /* 8985 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 8999 + /* 8990 */ MCD_OPC_CheckPredicate, + 4, + 44, + 117, + 1, // Skip to: 104527 + /* 8995 */ MCD_OPC_Decode, + 133, + 44, + 45, // Opcode: UMULH_ZZZ_D + /* 8999 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 9013 + /* 9004 */ MCD_OPC_CheckPredicate, + 4, + 30, + 117, + 1, // Skip to: 104527 + /* 9009 */ MCD_OPC_Decode, + 239, + 33, + 45, // Opcode: SQDMULH_ZZZ_D + /* 9013 */ MCD_OPC_FilterValue, + 13, + 21, + 117, + 1, // Skip to: 104527 + /* 9018 */ MCD_OPC_CheckPredicate, + 4, + 16, + 117, + 1, // Skip to: 104527 + /* 9023 */ MCD_OPC_Decode, + 233, + 34, + 45, // Opcode: SQRDMULH_ZZZ_D + /* 9027 */ MCD_OPC_FilterValue, + 4, + 134, + 1, + 0, // Skip to: 9422 + /* 9032 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 9035 */ MCD_OPC_FilterValue, + 0, + 123, + 0, + 0, // Skip to: 9163 + /* 9040 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 9043 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 9071 + /* 9048 */ MCD_OPC_CheckPredicate, + 3, + 242, + 116, + 1, // Skip to: 104527 + /* 9053 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 235, + 116, + 1, // Skip to: 104527 + /* 9060 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 228, + 116, + 1, // Skip to: 104527 + /* 9067 */ MCD_OPC_Decode, + 247, + 47, + 75, // Opcode: ZIP1_PPP_B + /* 9071 */ MCD_OPC_FilterValue, + 1, + 219, + 116, + 1, // Skip to: 104527 + /* 9076 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9079 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 9107 + /* 9084 */ MCD_OPC_CheckPredicate, + 3, + 206, + 116, + 1, // Skip to: 104527 + /* 9089 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 199, + 116, + 1, // Skip to: 104527 + /* 9096 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 192, + 116, + 1, // Skip to: 104527 + /* 9103 */ MCD_OPC_Decode, + 129, + 29, + 76, // Opcode: PUNPKLO_PP + /* 9107 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 9135 + /* 9112 */ MCD_OPC_CheckPredicate, + 3, + 178, + 116, + 1, // Skip to: 104527 + /* 9117 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 171, + 116, + 1, // Skip to: 104527 + /* 9124 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 164, + 116, + 1, // Skip to: 104527 + /* 9131 */ MCD_OPC_Decode, + 128, + 29, + 76, // Opcode: PUNPKHI_PP + /* 9135 */ MCD_OPC_FilterValue, + 4, + 155, + 116, + 1, // Skip to: 104527 + /* 9140 */ MCD_OPC_CheckPredicate, + 3, + 150, + 116, + 1, // Skip to: 104527 + /* 9145 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 143, + 116, + 1, // Skip to: 104527 + /* 9152 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 136, + 116, + 1, // Skip to: 104527 + /* 9159 */ MCD_OPC_Decode, + 183, + 29, + 76, // Opcode: REV_PP_B + /* 9163 */ MCD_OPC_FilterValue, + 1, + 30, + 0, + 0, // Skip to: 9198 + /* 9168 */ MCD_OPC_CheckPredicate, + 3, + 122, + 116, + 1, // Skip to: 104527 + /* 9173 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 115, + 116, + 1, // Skip to: 104527 + /* 9180 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 108, + 116, + 1, // Skip to: 104527 + /* 9187 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 101, + 116, + 1, // Skip to: 104527 + /* 9194 */ MCD_OPC_Decode, + 135, + 48, + 75, // Opcode: ZIP2_PPP_B + /* 9198 */ MCD_OPC_FilterValue, + 2, + 30, + 0, + 0, // Skip to: 9233 + /* 9203 */ MCD_OPC_CheckPredicate, + 3, + 87, + 116, + 1, // Skip to: 104527 + /* 9208 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 80, + 116, + 1, // Skip to: 104527 + /* 9215 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 73, + 116, + 1, // Skip to: 104527 + /* 9222 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 66, + 116, + 1, // Skip to: 104527 + /* 9229 */ MCD_OPC_Decode, + 252, + 46, + 75, // Opcode: UZP1_PPP_B + /* 9233 */ MCD_OPC_FilterValue, + 3, + 30, + 0, + 0, // Skip to: 9268 + /* 9238 */ MCD_OPC_CheckPredicate, + 3, + 52, + 116, + 1, // Skip to: 104527 + /* 9243 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 45, + 116, + 1, // Skip to: 104527 + /* 9250 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 38, + 116, + 1, // Skip to: 104527 + /* 9257 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 31, + 116, + 1, // Skip to: 104527 + /* 9264 */ MCD_OPC_Decode, + 140, + 47, + 75, // Opcode: UZP2_PPP_B + /* 9268 */ MCD_OPC_FilterValue, + 4, + 30, + 0, + 0, // Skip to: 9303 + /* 9273 */ MCD_OPC_CheckPredicate, + 3, + 17, + 116, + 1, // Skip to: 104527 + /* 9278 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 10, + 116, + 1, // Skip to: 104527 + /* 9285 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 3, + 116, + 1, // Skip to: 104527 + /* 9292 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 252, + 115, + 1, // Skip to: 104527 + /* 9299 */ MCD_OPC_Decode, + 183, + 41, + 75, // Opcode: TRN1_PPP_B + /* 9303 */ MCD_OPC_FilterValue, + 5, + 30, + 0, + 0, // Skip to: 9338 + /* 9308 */ MCD_OPC_CheckPredicate, + 3, + 238, + 115, + 1, // Skip to: 104527 + /* 9313 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 231, + 115, + 1, // Skip to: 104527 + /* 9320 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 224, + 115, + 1, // Skip to: 104527 + /* 9327 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 217, + 115, + 1, // Skip to: 104527 + /* 9334 */ MCD_OPC_Decode, + 199, + 41, + 75, // Opcode: TRN2_PPP_B + /* 9338 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 9352 + /* 9343 */ MCD_OPC_CheckPredicate, + 3, + 203, + 115, + 1, // Skip to: 104527 + /* 9348 */ MCD_OPC_Decode, + 251, + 47, + 45, // Opcode: ZIP1_ZZZ_B + /* 9352 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 9366 + /* 9357 */ MCD_OPC_CheckPredicate, + 3, + 189, + 115, + 1, // Skip to: 104527 + /* 9362 */ MCD_OPC_Decode, + 139, + 48, + 45, // Opcode: ZIP2_ZZZ_B + /* 9366 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 9380 + /* 9371 */ MCD_OPC_CheckPredicate, + 3, + 175, + 115, + 1, // Skip to: 104527 + /* 9376 */ MCD_OPC_Decode, + 128, + 47, + 45, // Opcode: UZP1_ZZZ_B + /* 9380 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 9394 + /* 9385 */ MCD_OPC_CheckPredicate, + 3, + 161, + 115, + 1, // Skip to: 104527 + /* 9390 */ MCD_OPC_Decode, + 144, + 47, + 45, // Opcode: UZP2_ZZZ_B + /* 9394 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 9408 + /* 9399 */ MCD_OPC_CheckPredicate, + 3, + 147, + 115, + 1, // Skip to: 104527 + /* 9404 */ MCD_OPC_Decode, + 187, + 41, + 45, // Opcode: TRN1_ZZZ_B + /* 9408 */ MCD_OPC_FilterValue, + 13, + 138, + 115, + 1, // Skip to: 104527 + /* 9413 */ MCD_OPC_CheckPredicate, + 3, + 133, + 115, + 1, // Skip to: 104527 + /* 9418 */ MCD_OPC_Decode, + 203, + 41, + 45, // Opcode: TRN2_ZZZ_B + /* 9422 */ MCD_OPC_FilterValue, + 5, + 77, + 1, + 0, // Skip to: 9760 + /* 9427 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 9430 */ MCD_OPC_FilterValue, + 0, + 66, + 0, + 0, // Skip to: 9501 + /* 9435 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 9438 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 9466 + /* 9443 */ MCD_OPC_CheckPredicate, + 3, + 103, + 115, + 1, // Skip to: 104527 + /* 9448 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 96, + 115, + 1, // Skip to: 104527 + /* 9455 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 89, + 115, + 1, // Skip to: 104527 + /* 9462 */ MCD_OPC_Decode, + 249, + 47, + 75, // Opcode: ZIP1_PPP_H + /* 9466 */ MCD_OPC_FilterValue, + 1, + 80, + 115, + 1, // Skip to: 104527 + /* 9471 */ MCD_OPC_CheckPredicate, + 3, + 75, + 115, + 1, // Skip to: 104527 + /* 9476 */ MCD_OPC_CheckField, + 16, + 4, + 4, + 68, + 115, + 1, // Skip to: 104527 + /* 9483 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 61, + 115, + 1, // Skip to: 104527 + /* 9490 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 54, + 115, + 1, // Skip to: 104527 + /* 9497 */ MCD_OPC_Decode, + 185, + 29, + 76, // Opcode: REV_PP_H + /* 9501 */ MCD_OPC_FilterValue, + 1, + 30, + 0, + 0, // Skip to: 9536 + /* 9506 */ MCD_OPC_CheckPredicate, + 3, + 40, + 115, + 1, // Skip to: 104527 + /* 9511 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 33, + 115, + 1, // Skip to: 104527 + /* 9518 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 26, + 115, + 1, // Skip to: 104527 + /* 9525 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 19, + 115, + 1, // Skip to: 104527 + /* 9532 */ MCD_OPC_Decode, + 137, + 48, + 75, // Opcode: ZIP2_PPP_H + /* 9536 */ MCD_OPC_FilterValue, + 2, + 30, + 0, + 0, // Skip to: 9571 + /* 9541 */ MCD_OPC_CheckPredicate, + 3, + 5, + 115, + 1, // Skip to: 104527 + /* 9546 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 254, + 114, + 1, // Skip to: 104527 + /* 9553 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 247, + 114, + 1, // Skip to: 104527 + /* 9560 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 240, + 114, + 1, // Skip to: 104527 + /* 9567 */ MCD_OPC_Decode, + 254, + 46, + 75, // Opcode: UZP1_PPP_H + /* 9571 */ MCD_OPC_FilterValue, + 3, + 30, + 0, + 0, // Skip to: 9606 + /* 9576 */ MCD_OPC_CheckPredicate, + 3, + 226, + 114, + 1, // Skip to: 104527 + /* 9581 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 219, + 114, + 1, // Skip to: 104527 + /* 9588 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 212, + 114, + 1, // Skip to: 104527 + /* 9595 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 205, + 114, + 1, // Skip to: 104527 + /* 9602 */ MCD_OPC_Decode, + 142, + 47, + 75, // Opcode: UZP2_PPP_H + /* 9606 */ MCD_OPC_FilterValue, + 4, + 30, + 0, + 0, // Skip to: 9641 + /* 9611 */ MCD_OPC_CheckPredicate, + 3, + 191, + 114, + 1, // Skip to: 104527 + /* 9616 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 184, + 114, + 1, // Skip to: 104527 + /* 9623 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 177, + 114, + 1, // Skip to: 104527 + /* 9630 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 170, + 114, + 1, // Skip to: 104527 + /* 9637 */ MCD_OPC_Decode, + 185, + 41, + 75, // Opcode: TRN1_PPP_H + /* 9641 */ MCD_OPC_FilterValue, + 5, + 30, + 0, + 0, // Skip to: 9676 + /* 9646 */ MCD_OPC_CheckPredicate, + 3, + 156, + 114, + 1, // Skip to: 104527 + /* 9651 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 149, + 114, + 1, // Skip to: 104527 + /* 9658 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 142, + 114, + 1, // Skip to: 104527 + /* 9665 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 135, + 114, + 1, // Skip to: 104527 + /* 9672 */ MCD_OPC_Decode, + 201, + 41, + 75, // Opcode: TRN2_PPP_H + /* 9676 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 9690 + /* 9681 */ MCD_OPC_CheckPredicate, + 3, + 121, + 114, + 1, // Skip to: 104527 + /* 9686 */ MCD_OPC_Decode, + 253, + 47, + 45, // Opcode: ZIP1_ZZZ_H + /* 9690 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 9704 + /* 9695 */ MCD_OPC_CheckPredicate, + 3, + 107, + 114, + 1, // Skip to: 104527 + /* 9700 */ MCD_OPC_Decode, + 141, + 48, + 45, // Opcode: ZIP2_ZZZ_H + /* 9704 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 9718 + /* 9709 */ MCD_OPC_CheckPredicate, + 3, + 93, + 114, + 1, // Skip to: 104527 + /* 9714 */ MCD_OPC_Decode, + 130, + 47, + 45, // Opcode: UZP1_ZZZ_H + /* 9718 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 9732 + /* 9723 */ MCD_OPC_CheckPredicate, + 3, + 79, + 114, + 1, // Skip to: 104527 + /* 9728 */ MCD_OPC_Decode, + 146, + 47, + 45, // Opcode: UZP2_ZZZ_H + /* 9732 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 9746 + /* 9737 */ MCD_OPC_CheckPredicate, + 3, + 65, + 114, + 1, // Skip to: 104527 + /* 9742 */ MCD_OPC_Decode, + 189, + 41, + 45, // Opcode: TRN1_ZZZ_H + /* 9746 */ MCD_OPC_FilterValue, + 13, + 56, + 114, + 1, // Skip to: 104527 + /* 9751 */ MCD_OPC_CheckPredicate, + 3, + 51, + 114, + 1, // Skip to: 104527 + /* 9756 */ MCD_OPC_Decode, + 205, + 41, + 45, // Opcode: TRN2_ZZZ_H + /* 9760 */ MCD_OPC_FilterValue, + 6, + 77, + 1, + 0, // Skip to: 10098 + /* 9765 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 9768 */ MCD_OPC_FilterValue, + 0, + 66, + 0, + 0, // Skip to: 9839 + /* 9773 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 9776 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 9804 + /* 9781 */ MCD_OPC_CheckPredicate, + 3, + 21, + 114, + 1, // Skip to: 104527 + /* 9786 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 14, + 114, + 1, // Skip to: 104527 + /* 9793 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 7, + 114, + 1, // Skip to: 104527 + /* 9800 */ MCD_OPC_Decode, + 250, + 47, + 75, // Opcode: ZIP1_PPP_S + /* 9804 */ MCD_OPC_FilterValue, + 1, + 254, + 113, + 1, // Skip to: 104527 + /* 9809 */ MCD_OPC_CheckPredicate, + 3, + 249, + 113, + 1, // Skip to: 104527 + /* 9814 */ MCD_OPC_CheckField, + 16, + 4, + 4, + 242, + 113, + 1, // Skip to: 104527 + /* 9821 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 235, + 113, + 1, // Skip to: 104527 + /* 9828 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 228, + 113, + 1, // Skip to: 104527 + /* 9835 */ MCD_OPC_Decode, + 186, + 29, + 76, // Opcode: REV_PP_S + /* 9839 */ MCD_OPC_FilterValue, + 1, + 30, + 0, + 0, // Skip to: 9874 + /* 9844 */ MCD_OPC_CheckPredicate, + 3, + 214, + 113, + 1, // Skip to: 104527 + /* 9849 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 207, + 113, + 1, // Skip to: 104527 + /* 9856 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 200, + 113, + 1, // Skip to: 104527 + /* 9863 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 193, + 113, + 1, // Skip to: 104527 + /* 9870 */ MCD_OPC_Decode, + 138, + 48, + 75, // Opcode: ZIP2_PPP_S + /* 9874 */ MCD_OPC_FilterValue, + 2, + 30, + 0, + 0, // Skip to: 9909 + /* 9879 */ MCD_OPC_CheckPredicate, + 3, + 179, + 113, + 1, // Skip to: 104527 + /* 9884 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 172, + 113, + 1, // Skip to: 104527 + /* 9891 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 165, + 113, + 1, // Skip to: 104527 + /* 9898 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 158, + 113, + 1, // Skip to: 104527 + /* 9905 */ MCD_OPC_Decode, + 255, + 46, + 75, // Opcode: UZP1_PPP_S + /* 9909 */ MCD_OPC_FilterValue, + 3, + 30, + 0, + 0, // Skip to: 9944 + /* 9914 */ MCD_OPC_CheckPredicate, + 3, + 144, + 113, + 1, // Skip to: 104527 + /* 9919 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 137, + 113, + 1, // Skip to: 104527 + /* 9926 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 130, + 113, + 1, // Skip to: 104527 + /* 9933 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 123, + 113, + 1, // Skip to: 104527 + /* 9940 */ MCD_OPC_Decode, + 143, + 47, + 75, // Opcode: UZP2_PPP_S + /* 9944 */ MCD_OPC_FilterValue, + 4, + 30, + 0, + 0, // Skip to: 9979 + /* 9949 */ MCD_OPC_CheckPredicate, + 3, + 109, + 113, + 1, // Skip to: 104527 + /* 9954 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 102, + 113, + 1, // Skip to: 104527 + /* 9961 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 95, + 113, + 1, // Skip to: 104527 + /* 9968 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 88, + 113, + 1, // Skip to: 104527 + /* 9975 */ MCD_OPC_Decode, + 186, + 41, + 75, // Opcode: TRN1_PPP_S + /* 9979 */ MCD_OPC_FilterValue, + 5, + 30, + 0, + 0, // Skip to: 10014 + /* 9984 */ MCD_OPC_CheckPredicate, + 3, + 74, + 113, + 1, // Skip to: 104527 + /* 9989 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 67, + 113, + 1, // Skip to: 104527 + /* 9996 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 60, + 113, + 1, // Skip to: 104527 + /* 10003 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 53, + 113, + 1, // Skip to: 104527 + /* 10010 */ MCD_OPC_Decode, + 202, + 41, + 75, // Opcode: TRN2_PPP_S + /* 10014 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 10028 + /* 10019 */ MCD_OPC_CheckPredicate, + 3, + 39, + 113, + 1, // Skip to: 104527 + /* 10024 */ MCD_OPC_Decode, + 255, + 47, + 45, // Opcode: ZIP1_ZZZ_S + /* 10028 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 10042 + /* 10033 */ MCD_OPC_CheckPredicate, + 3, + 25, + 113, + 1, // Skip to: 104527 + /* 10038 */ MCD_OPC_Decode, + 143, + 48, + 45, // Opcode: ZIP2_ZZZ_S + /* 10042 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 10056 + /* 10047 */ MCD_OPC_CheckPredicate, + 3, + 11, + 113, + 1, // Skip to: 104527 + /* 10052 */ MCD_OPC_Decode, + 132, + 47, + 45, // Opcode: UZP1_ZZZ_S + /* 10056 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 10070 + /* 10061 */ MCD_OPC_CheckPredicate, + 3, + 253, + 112, + 1, // Skip to: 104527 + /* 10066 */ MCD_OPC_Decode, + 148, + 47, + 45, // Opcode: UZP2_ZZZ_S + /* 10070 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 10084 + /* 10075 */ MCD_OPC_CheckPredicate, + 3, + 239, + 112, + 1, // Skip to: 104527 + /* 10080 */ MCD_OPC_Decode, + 191, + 41, + 45, // Opcode: TRN1_ZZZ_S + /* 10084 */ MCD_OPC_FilterValue, + 13, + 230, + 112, + 1, // Skip to: 104527 + /* 10089 */ MCD_OPC_CheckPredicate, + 3, + 225, + 112, + 1, // Skip to: 104527 + /* 10094 */ MCD_OPC_Decode, + 207, + 41, + 45, // Opcode: TRN2_ZZZ_S + /* 10098 */ MCD_OPC_FilterValue, + 7, + 216, + 112, + 1, // Skip to: 104527 + /* 10103 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 10106 */ MCD_OPC_FilterValue, + 0, + 66, + 0, + 0, // Skip to: 10177 + /* 10111 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 10114 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 10142 + /* 10119 */ MCD_OPC_CheckPredicate, + 3, + 195, + 112, + 1, // Skip to: 104527 + /* 10124 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 188, + 112, + 1, // Skip to: 104527 + /* 10131 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 112, + 1, // Skip to: 104527 + /* 10138 */ MCD_OPC_Decode, + 248, + 47, + 75, // Opcode: ZIP1_PPP_D + /* 10142 */ MCD_OPC_FilterValue, + 1, + 172, + 112, + 1, // Skip to: 104527 + /* 10147 */ MCD_OPC_CheckPredicate, + 3, + 167, + 112, + 1, // Skip to: 104527 + /* 10152 */ MCD_OPC_CheckField, + 16, + 4, + 4, + 160, + 112, + 1, // Skip to: 104527 + /* 10159 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 153, + 112, + 1, // Skip to: 104527 + /* 10166 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 146, + 112, + 1, // Skip to: 104527 + /* 10173 */ MCD_OPC_Decode, + 184, + 29, + 76, // Opcode: REV_PP_D + /* 10177 */ MCD_OPC_FilterValue, + 1, + 30, + 0, + 0, // Skip to: 10212 + /* 10182 */ MCD_OPC_CheckPredicate, + 3, + 132, + 112, + 1, // Skip to: 104527 + /* 10187 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 125, + 112, + 1, // Skip to: 104527 + /* 10194 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 118, + 112, + 1, // Skip to: 104527 + /* 10201 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 111, + 112, + 1, // Skip to: 104527 + /* 10208 */ MCD_OPC_Decode, + 136, + 48, + 75, // Opcode: ZIP2_PPP_D + /* 10212 */ MCD_OPC_FilterValue, + 2, + 30, + 0, + 0, // Skip to: 10247 + /* 10217 */ MCD_OPC_CheckPredicate, + 3, + 97, + 112, + 1, // Skip to: 104527 + /* 10222 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 90, + 112, + 1, // Skip to: 104527 + /* 10229 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 83, + 112, + 1, // Skip to: 104527 + /* 10236 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 76, + 112, + 1, // Skip to: 104527 + /* 10243 */ MCD_OPC_Decode, + 253, + 46, + 75, // Opcode: UZP1_PPP_D + /* 10247 */ MCD_OPC_FilterValue, + 3, + 30, + 0, + 0, // Skip to: 10282 + /* 10252 */ MCD_OPC_CheckPredicate, + 3, + 62, + 112, + 1, // Skip to: 104527 + /* 10257 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 55, + 112, + 1, // Skip to: 104527 + /* 10264 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 48, + 112, + 1, // Skip to: 104527 + /* 10271 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 41, + 112, + 1, // Skip to: 104527 + /* 10278 */ MCD_OPC_Decode, + 141, + 47, + 75, // Opcode: UZP2_PPP_D + /* 10282 */ MCD_OPC_FilterValue, + 4, + 30, + 0, + 0, // Skip to: 10317 + /* 10287 */ MCD_OPC_CheckPredicate, + 3, + 27, + 112, + 1, // Skip to: 104527 + /* 10292 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 20, + 112, + 1, // Skip to: 104527 + /* 10299 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 13, + 112, + 1, // Skip to: 104527 + /* 10306 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 6, + 112, + 1, // Skip to: 104527 + /* 10313 */ MCD_OPC_Decode, + 184, + 41, + 75, // Opcode: TRN1_PPP_D + /* 10317 */ MCD_OPC_FilterValue, + 5, + 30, + 0, + 0, // Skip to: 10352 + /* 10322 */ MCD_OPC_CheckPredicate, + 3, + 248, + 111, + 1, // Skip to: 104527 + /* 10327 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 241, + 111, + 1, // Skip to: 104527 + /* 10334 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 234, + 111, + 1, // Skip to: 104527 + /* 10341 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 227, + 111, + 1, // Skip to: 104527 + /* 10348 */ MCD_OPC_Decode, + 200, + 41, + 75, // Opcode: TRN2_PPP_D + /* 10352 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 10366 + /* 10357 */ MCD_OPC_CheckPredicate, + 3, + 213, + 111, + 1, // Skip to: 104527 + /* 10362 */ MCD_OPC_Decode, + 252, + 47, + 45, // Opcode: ZIP1_ZZZ_D + /* 10366 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 10380 + /* 10371 */ MCD_OPC_CheckPredicate, + 3, + 199, + 111, + 1, // Skip to: 104527 + /* 10376 */ MCD_OPC_Decode, + 140, + 48, + 45, // Opcode: ZIP2_ZZZ_D + /* 10380 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 10394 + /* 10385 */ MCD_OPC_CheckPredicate, + 3, + 185, + 111, + 1, // Skip to: 104527 + /* 10390 */ MCD_OPC_Decode, + 129, + 47, + 45, // Opcode: UZP1_ZZZ_D + /* 10394 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 10408 + /* 10399 */ MCD_OPC_CheckPredicate, + 3, + 171, + 111, + 1, // Skip to: 104527 + /* 10404 */ MCD_OPC_Decode, + 145, + 47, + 45, // Opcode: UZP2_ZZZ_D + /* 10408 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 10422 + /* 10413 */ MCD_OPC_CheckPredicate, + 3, + 157, + 111, + 1, // Skip to: 104527 + /* 10418 */ MCD_OPC_Decode, + 188, + 41, + 45, // Opcode: TRN1_ZZZ_D + /* 10422 */ MCD_OPC_FilterValue, + 13, + 148, + 111, + 1, // Skip to: 104527 + /* 10427 */ MCD_OPC_CheckPredicate, + 3, + 143, + 111, + 1, // Skip to: 104527 + /* 10432 */ MCD_OPC_Decode, + 204, + 41, + 45, // Opcode: TRN2_ZZZ_D + /* 10436 */ MCD_OPC_FilterValue, + 2, + 224, + 9, + 0, // Skip to: 12969 + /* 10441 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 10444 */ MCD_OPC_FilterValue, + 0, + 15, + 2, + 0, // Skip to: 10976 + /* 10449 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 10452 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 10488 + /* 10457 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10460 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10474 + /* 10465 */ MCD_OPC_CheckPredicate, + 3, + 105, + 111, + 1, // Skip to: 104527 + /* 10470 */ MCD_OPC_Decode, + 151, + 8, + 45, // Opcode: ASR_WIDE_ZZZ_B + /* 10474 */ MCD_OPC_FilterValue, + 1, + 96, + 111, + 1, // Skip to: 104527 + /* 10479 */ MCD_OPC_CheckPredicate, + 3, + 91, + 111, + 1, // Skip to: 104527 + /* 10484 */ MCD_OPC_Decode, + 152, + 8, + 45, // Opcode: ASR_WIDE_ZZZ_H + /* 10488 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 10524 + /* 10493 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10496 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10510 + /* 10501 */ MCD_OPC_CheckPredicate, + 3, + 69, + 111, + 1, // Skip to: 104527 + /* 10506 */ MCD_OPC_Decode, + 247, + 26, + 45, // Opcode: LSR_WIDE_ZZZ_B + /* 10510 */ MCD_OPC_FilterValue, + 1, + 60, + 111, + 1, // Skip to: 104527 + /* 10515 */ MCD_OPC_CheckPredicate, + 3, + 55, + 111, + 1, // Skip to: 104527 + /* 10520 */ MCD_OPC_Decode, + 248, + 26, + 45, // Opcode: LSR_WIDE_ZZZ_H + /* 10524 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 10560 + /* 10529 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10532 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10546 + /* 10537 */ MCD_OPC_CheckPredicate, + 3, + 33, + 111, + 1, // Skip to: 104527 + /* 10542 */ MCD_OPC_Decode, + 223, + 26, + 45, // Opcode: LSL_WIDE_ZZZ_B + /* 10546 */ MCD_OPC_FilterValue, + 1, + 24, + 111, + 1, // Skip to: 104527 + /* 10551 */ MCD_OPC_CheckPredicate, + 3, + 19, + 111, + 1, // Skip to: 104527 + /* 10556 */ MCD_OPC_Decode, + 224, + 26, + 45, // Opcode: LSL_WIDE_ZZZ_H + /* 10560 */ MCD_OPC_FilterValue, + 4, + 60, + 0, + 0, // Skip to: 10625 + /* 10565 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10568 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 10611 + /* 10573 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 10576 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 10597 + /* 10581 */ MCD_OPC_CheckPredicate, + 3, + 245, + 110, + 1, // Skip to: 104527 + /* 10586 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 238, + 110, + 1, // Skip to: 104527 + /* 10593 */ MCD_OPC_Decode, + 162, + 8, + 77, // Opcode: ASR_ZZI_B + /* 10597 */ MCD_OPC_FilterValue, + 1, + 229, + 110, + 1, // Skip to: 104527 + /* 10602 */ MCD_OPC_CheckPredicate, + 3, + 224, + 110, + 1, // Skip to: 104527 + /* 10607 */ MCD_OPC_Decode, + 164, + 8, + 78, // Opcode: ASR_ZZI_H + /* 10611 */ MCD_OPC_FilterValue, + 1, + 215, + 110, + 1, // Skip to: 104527 + /* 10616 */ MCD_OPC_CheckPredicate, + 3, + 210, + 110, + 1, // Skip to: 104527 + /* 10621 */ MCD_OPC_Decode, + 165, + 8, + 79, // Opcode: ASR_ZZI_S + /* 10625 */ MCD_OPC_FilterValue, + 5, + 60, + 0, + 0, // Skip to: 10690 + /* 10630 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10633 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 10676 + /* 10638 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 10641 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 10662 + /* 10646 */ MCD_OPC_CheckPredicate, + 3, + 180, + 110, + 1, // Skip to: 104527 + /* 10651 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 173, + 110, + 1, // Skip to: 104527 + /* 10658 */ MCD_OPC_Decode, + 130, + 27, + 77, // Opcode: LSR_ZZI_B + /* 10662 */ MCD_OPC_FilterValue, + 1, + 164, + 110, + 1, // Skip to: 104527 + /* 10667 */ MCD_OPC_CheckPredicate, + 3, + 159, + 110, + 1, // Skip to: 104527 + /* 10672 */ MCD_OPC_Decode, + 132, + 27, + 78, // Opcode: LSR_ZZI_H + /* 10676 */ MCD_OPC_FilterValue, + 1, + 150, + 110, + 1, // Skip to: 104527 + /* 10681 */ MCD_OPC_CheckPredicate, + 3, + 145, + 110, + 1, // Skip to: 104527 + /* 10686 */ MCD_OPC_Decode, + 133, + 27, + 79, // Opcode: LSR_ZZI_S + /* 10690 */ MCD_OPC_FilterValue, + 7, + 60, + 0, + 0, // Skip to: 10755 + /* 10695 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10698 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 10741 + /* 10703 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 10706 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 10727 + /* 10711 */ MCD_OPC_CheckPredicate, + 3, + 115, + 110, + 1, // Skip to: 104527 + /* 10716 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 108, + 110, + 1, // Skip to: 104527 + /* 10723 */ MCD_OPC_Decode, + 234, + 26, + 80, // Opcode: LSL_ZZI_B + /* 10727 */ MCD_OPC_FilterValue, + 1, + 99, + 110, + 1, // Skip to: 104527 + /* 10732 */ MCD_OPC_CheckPredicate, + 3, + 94, + 110, + 1, // Skip to: 104527 + /* 10737 */ MCD_OPC_Decode, + 236, + 26, + 81, // Opcode: LSL_ZZI_H + /* 10741 */ MCD_OPC_FilterValue, + 1, + 85, + 110, + 1, // Skip to: 104527 + /* 10746 */ MCD_OPC_CheckPredicate, + 3, + 80, + 110, + 1, // Skip to: 104527 + /* 10751 */ MCD_OPC_Decode, + 237, + 26, + 82, // Opcode: LSL_ZZI_S + /* 10755 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 10791 + /* 10760 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10763 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10777 + /* 10768 */ MCD_OPC_CheckPredicate, + 6, + 58, + 110, + 1, // Skip to: 104527 + /* 10773 */ MCD_OPC_Decode, + 228, + 7, + 45, // Opcode: ADR_SXTW_ZZZ_D_0 + /* 10777 */ MCD_OPC_FilterValue, + 1, + 49, + 110, + 1, // Skip to: 104527 + /* 10782 */ MCD_OPC_CheckPredicate, + 6, + 44, + 110, + 1, // Skip to: 104527 + /* 10787 */ MCD_OPC_Decode, + 232, + 7, + 45, // Opcode: ADR_UXTW_ZZZ_D_0 + /* 10791 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 10827 + /* 10796 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10799 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10813 + /* 10804 */ MCD_OPC_CheckPredicate, + 6, + 22, + 110, + 1, // Skip to: 104527 + /* 10809 */ MCD_OPC_Decode, + 229, + 7, + 45, // Opcode: ADR_SXTW_ZZZ_D_1 + /* 10813 */ MCD_OPC_FilterValue, + 1, + 13, + 110, + 1, // Skip to: 104527 + /* 10818 */ MCD_OPC_CheckPredicate, + 6, + 8, + 110, + 1, // Skip to: 104527 + /* 10823 */ MCD_OPC_Decode, + 233, + 7, + 45, // Opcode: ADR_UXTW_ZZZ_D_1 + /* 10827 */ MCD_OPC_FilterValue, + 10, + 31, + 0, + 0, // Skip to: 10863 + /* 10832 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10835 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10849 + /* 10840 */ MCD_OPC_CheckPredicate, + 6, + 242, + 109, + 1, // Skip to: 104527 + /* 10845 */ MCD_OPC_Decode, + 230, + 7, + 45, // Opcode: ADR_SXTW_ZZZ_D_2 + /* 10849 */ MCD_OPC_FilterValue, + 1, + 233, + 109, + 1, // Skip to: 104527 + /* 10854 */ MCD_OPC_CheckPredicate, + 6, + 228, + 109, + 1, // Skip to: 104527 + /* 10859 */ MCD_OPC_Decode, + 234, + 7, + 45, // Opcode: ADR_UXTW_ZZZ_D_2 + /* 10863 */ MCD_OPC_FilterValue, + 11, + 31, + 0, + 0, // Skip to: 10899 + /* 10868 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 10871 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10885 + /* 10876 */ MCD_OPC_CheckPredicate, + 6, + 206, + 109, + 1, // Skip to: 104527 + /* 10881 */ MCD_OPC_Decode, + 231, + 7, + 45, // Opcode: ADR_SXTW_ZZZ_D_3 + /* 10885 */ MCD_OPC_FilterValue, + 1, + 197, + 109, + 1, // Skip to: 104527 + /* 10890 */ MCD_OPC_CheckPredicate, + 6, + 192, + 109, + 1, // Skip to: 104527 + /* 10895 */ MCD_OPC_Decode, + 235, + 7, + 45, // Opcode: ADR_UXTW_ZZZ_D_3 + /* 10899 */ MCD_OPC_FilterValue, + 12, + 16, + 0, + 0, // Skip to: 10920 + /* 10904 */ MCD_OPC_CheckPredicate, + 6, + 178, + 109, + 1, // Skip to: 104527 + /* 10909 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 171, + 109, + 1, // Skip to: 104527 + /* 10916 */ MCD_OPC_Decode, + 254, + 19, + 45, // Opcode: FTSSEL_ZZZ_H + /* 10920 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 10948 + /* 10925 */ MCD_OPC_CheckPredicate, + 6, + 157, + 109, + 1, // Skip to: 104527 + /* 10930 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 150, + 109, + 1, // Skip to: 104527 + /* 10937 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 143, + 109, + 1, // Skip to: 104527 + /* 10944 */ MCD_OPC_Decode, + 137, + 16, + 63, // Opcode: FEXPA_ZZ_H + /* 10948 */ MCD_OPC_FilterValue, + 15, + 134, + 109, + 1, // Skip to: 104527 + /* 10953 */ MCD_OPC_CheckPredicate, + 3, + 129, + 109, + 1, // Skip to: 104527 + /* 10958 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 122, + 109, + 1, // Skip to: 104527 + /* 10965 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 115, + 109, + 1, // Skip to: 104527 + /* 10972 */ MCD_OPC_Decode, + 198, + 27, + 63, // Opcode: MOVPRFX_ZZ + /* 10976 */ MCD_OPC_FilterValue, + 1, + 82, + 1, + 0, // Skip to: 11319 + /* 10981 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 10984 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11005 + /* 10989 */ MCD_OPC_CheckPredicate, + 3, + 93, + 109, + 1, // Skip to: 104527 + /* 10994 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 86, + 109, + 1, // Skip to: 104527 + /* 11001 */ MCD_OPC_Decode, + 153, + 8, + 45, // Opcode: ASR_WIDE_ZZZ_S + /* 11005 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 11026 + /* 11010 */ MCD_OPC_CheckPredicate, + 3, + 72, + 109, + 1, // Skip to: 104527 + /* 11015 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 65, + 109, + 1, // Skip to: 104527 + /* 11022 */ MCD_OPC_Decode, + 249, + 26, + 45, // Opcode: LSR_WIDE_ZZZ_S + /* 11026 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 11047 + /* 11031 */ MCD_OPC_CheckPredicate, + 3, + 51, + 109, + 1, // Skip to: 104527 + /* 11036 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 44, + 109, + 1, // Skip to: 104527 + /* 11043 */ MCD_OPC_Decode, + 225, + 26, + 45, // Opcode: LSL_WIDE_ZZZ_S + /* 11047 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 11061 + /* 11052 */ MCD_OPC_CheckPredicate, + 3, + 30, + 109, + 1, // Skip to: 104527 + /* 11057 */ MCD_OPC_Decode, + 163, + 8, + 83, // Opcode: ASR_ZZI_D + /* 11061 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 11075 + /* 11066 */ MCD_OPC_CheckPredicate, + 3, + 16, + 109, + 1, // Skip to: 104527 + /* 11071 */ MCD_OPC_Decode, + 131, + 27, + 83, // Opcode: LSR_ZZI_D + /* 11075 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 11089 + /* 11080 */ MCD_OPC_CheckPredicate, + 3, + 2, + 109, + 1, // Skip to: 104527 + /* 11085 */ MCD_OPC_Decode, + 235, + 26, + 84, // Opcode: LSL_ZZI_D + /* 11089 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 11125 + /* 11094 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11097 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11111 + /* 11102 */ MCD_OPC_CheckPredicate, + 6, + 236, + 108, + 1, // Skip to: 104527 + /* 11107 */ MCD_OPC_Decode, + 224, + 7, + 45, // Opcode: ADR_LSL_ZZZ_S_0 + /* 11111 */ MCD_OPC_FilterValue, + 1, + 227, + 108, + 1, // Skip to: 104527 + /* 11116 */ MCD_OPC_CheckPredicate, + 6, + 222, + 108, + 1, // Skip to: 104527 + /* 11121 */ MCD_OPC_Decode, + 220, + 7, + 45, // Opcode: ADR_LSL_ZZZ_D_0 + /* 11125 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 11161 + /* 11130 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11133 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11147 + /* 11138 */ MCD_OPC_CheckPredicate, + 6, + 200, + 108, + 1, // Skip to: 104527 + /* 11143 */ MCD_OPC_Decode, + 225, + 7, + 45, // Opcode: ADR_LSL_ZZZ_S_1 + /* 11147 */ MCD_OPC_FilterValue, + 1, + 191, + 108, + 1, // Skip to: 104527 + /* 11152 */ MCD_OPC_CheckPredicate, + 6, + 186, + 108, + 1, // Skip to: 104527 + /* 11157 */ MCD_OPC_Decode, + 221, + 7, + 45, // Opcode: ADR_LSL_ZZZ_D_1 + /* 11161 */ MCD_OPC_FilterValue, + 10, + 31, + 0, + 0, // Skip to: 11197 + /* 11166 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11169 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11183 + /* 11174 */ MCD_OPC_CheckPredicate, + 6, + 164, + 108, + 1, // Skip to: 104527 + /* 11179 */ MCD_OPC_Decode, + 226, + 7, + 45, // Opcode: ADR_LSL_ZZZ_S_2 + /* 11183 */ MCD_OPC_FilterValue, + 1, + 155, + 108, + 1, // Skip to: 104527 + /* 11188 */ MCD_OPC_CheckPredicate, + 6, + 150, + 108, + 1, // Skip to: 104527 + /* 11193 */ MCD_OPC_Decode, + 222, + 7, + 45, // Opcode: ADR_LSL_ZZZ_D_2 + /* 11197 */ MCD_OPC_FilterValue, + 11, + 31, + 0, + 0, // Skip to: 11233 + /* 11202 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11205 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11219 + /* 11210 */ MCD_OPC_CheckPredicate, + 6, + 128, + 108, + 1, // Skip to: 104527 + /* 11215 */ MCD_OPC_Decode, + 227, + 7, + 45, // Opcode: ADR_LSL_ZZZ_S_3 + /* 11219 */ MCD_OPC_FilterValue, + 1, + 119, + 108, + 1, // Skip to: 104527 + /* 11224 */ MCD_OPC_CheckPredicate, + 6, + 114, + 108, + 1, // Skip to: 104527 + /* 11229 */ MCD_OPC_Decode, + 223, + 7, + 45, // Opcode: ADR_LSL_ZZZ_D_3 + /* 11233 */ MCD_OPC_FilterValue, + 12, + 31, + 0, + 0, // Skip to: 11269 + /* 11238 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11241 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11255 + /* 11246 */ MCD_OPC_CheckPredicate, + 6, + 92, + 108, + 1, // Skip to: 104527 + /* 11251 */ MCD_OPC_Decode, + 255, + 19, + 45, // Opcode: FTSSEL_ZZZ_S + /* 11255 */ MCD_OPC_FilterValue, + 1, + 83, + 108, + 1, // Skip to: 104527 + /* 11260 */ MCD_OPC_CheckPredicate, + 6, + 78, + 108, + 1, // Skip to: 104527 + /* 11265 */ MCD_OPC_Decode, + 253, + 19, + 45, // Opcode: FTSSEL_ZZZ_D + /* 11269 */ MCD_OPC_FilterValue, + 14, + 69, + 108, + 1, // Skip to: 104527 + /* 11274 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11277 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11298 + /* 11282 */ MCD_OPC_CheckPredicate, + 6, + 56, + 108, + 1, // Skip to: 104527 + /* 11287 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 49, + 108, + 1, // Skip to: 104527 + /* 11294 */ MCD_OPC_Decode, + 138, + 16, + 63, // Opcode: FEXPA_ZZ_S + /* 11298 */ MCD_OPC_FilterValue, + 1, + 40, + 108, + 1, // Skip to: 104527 + /* 11303 */ MCD_OPC_CheckPredicate, + 6, + 35, + 108, + 1, // Skip to: 104527 + /* 11308 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 28, + 108, + 1, // Skip to: 104527 + /* 11315 */ MCD_OPC_Decode, + 136, + 16, + 63, // Opcode: FEXPA_ZZ_D + /* 11319 */ MCD_OPC_FilterValue, + 2, + 1, + 3, + 0, // Skip to: 12093 + /* 11324 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 11327 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 11407 + /* 11332 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 11335 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 11371 + /* 11340 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11343 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11357 + /* 11348 */ MCD_OPC_CheckPredicate, + 3, + 246, + 107, + 1, // Skip to: 104527 + /* 11353 */ MCD_OPC_Decode, + 198, + 11, + 85, // Opcode: CPY_ZPmV_B + /* 11357 */ MCD_OPC_FilterValue, + 1, + 237, + 107, + 1, // Skip to: 104527 + /* 11362 */ MCD_OPC_CheckPredicate, + 3, + 232, + 107, + 1, // Skip to: 104527 + /* 11367 */ MCD_OPC_Decode, + 200, + 11, + 86, // Opcode: CPY_ZPmV_H + /* 11371 */ MCD_OPC_FilterValue, + 1, + 223, + 107, + 1, // Skip to: 104527 + /* 11376 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11379 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11393 + /* 11384 */ MCD_OPC_CheckPredicate, + 3, + 210, + 107, + 1, // Skip to: 104527 + /* 11389 */ MCD_OPC_Decode, + 193, + 21, + 87, // Opcode: LASTA_RPZ_B + /* 11393 */ MCD_OPC_FilterValue, + 1, + 201, + 107, + 1, // Skip to: 104527 + /* 11398 */ MCD_OPC_CheckPredicate, + 3, + 196, + 107, + 1, // Skip to: 104527 + /* 11403 */ MCD_OPC_Decode, + 195, + 21, + 87, // Opcode: LASTA_RPZ_H + /* 11407 */ MCD_OPC_FilterValue, + 1, + 45, + 0, + 0, // Skip to: 11457 + /* 11412 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11415 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11436 + /* 11420 */ MCD_OPC_CheckPredicate, + 3, + 174, + 107, + 1, // Skip to: 104527 + /* 11425 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 167, + 107, + 1, // Skip to: 104527 + /* 11432 */ MCD_OPC_Decode, + 201, + 21, + 87, // Opcode: LASTB_RPZ_B + /* 11436 */ MCD_OPC_FilterValue, + 1, + 158, + 107, + 1, // Skip to: 104527 + /* 11441 */ MCD_OPC_CheckPredicate, + 3, + 153, + 107, + 1, // Skip to: 104527 + /* 11446 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 146, + 107, + 1, // Skip to: 104527 + /* 11453 */ MCD_OPC_Decode, + 203, + 21, + 87, // Opcode: LASTB_RPZ_H + /* 11457 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 11507 + /* 11462 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11465 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11486 + /* 11470 */ MCD_OPC_CheckPredicate, + 3, + 124, + 107, + 1, // Skip to: 104527 + /* 11475 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 117, + 107, + 1, // Skip to: 104527 + /* 11482 */ MCD_OPC_Decode, + 197, + 21, + 88, // Opcode: LASTA_VPZ_B + /* 11486 */ MCD_OPC_FilterValue, + 1, + 108, + 107, + 1, // Skip to: 104527 + /* 11491 */ MCD_OPC_CheckPredicate, + 3, + 103, + 107, + 1, // Skip to: 104527 + /* 11496 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 96, + 107, + 1, // Skip to: 104527 + /* 11503 */ MCD_OPC_Decode, + 199, + 21, + 89, // Opcode: LASTA_VPZ_H + /* 11507 */ MCD_OPC_FilterValue, + 3, + 45, + 0, + 0, // Skip to: 11557 + /* 11512 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11515 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11536 + /* 11520 */ MCD_OPC_CheckPredicate, + 3, + 74, + 107, + 1, // Skip to: 104527 + /* 11525 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 67, + 107, + 1, // Skip to: 104527 + /* 11532 */ MCD_OPC_Decode, + 205, + 21, + 88, // Opcode: LASTB_VPZ_B + /* 11536 */ MCD_OPC_FilterValue, + 1, + 58, + 107, + 1, // Skip to: 104527 + /* 11541 */ MCD_OPC_CheckPredicate, + 3, + 53, + 107, + 1, // Skip to: 104527 + /* 11546 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 46, + 107, + 1, // Skip to: 104527 + /* 11553 */ MCD_OPC_Decode, + 207, + 21, + 89, // Opcode: LASTB_VPZ_H + /* 11557 */ MCD_OPC_FilterValue, + 4, + 23, + 0, + 0, // Skip to: 11585 + /* 11562 */ MCD_OPC_CheckPredicate, + 3, + 32, + 107, + 1, // Skip to: 104527 + /* 11567 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 25, + 107, + 1, // Skip to: 104527 + /* 11574 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 18, + 107, + 1, // Skip to: 104527 + /* 11581 */ MCD_OPC_Decode, + 175, + 29, + 24, // Opcode: REVB_ZPmZ_H + /* 11585 */ MCD_OPC_FilterValue, + 7, + 45, + 0, + 0, // Skip to: 11635 + /* 11590 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11593 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11614 + /* 11598 */ MCD_OPC_CheckPredicate, + 3, + 252, + 106, + 1, // Skip to: 104527 + /* 11603 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 245, + 106, + 1, // Skip to: 104527 + /* 11610 */ MCD_OPC_Decode, + 146, + 29, + 24, // Opcode: RBIT_ZPmZ_B + /* 11614 */ MCD_OPC_FilterValue, + 1, + 236, + 106, + 1, // Skip to: 104527 + /* 11619 */ MCD_OPC_CheckPredicate, + 3, + 231, + 106, + 1, // Skip to: 104527 + /* 11624 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 224, + 106, + 1, // Skip to: 104527 + /* 11631 */ MCD_OPC_Decode, + 148, + 29, + 24, // Opcode: RBIT_ZPmZ_H + /* 11635 */ MCD_OPC_FilterValue, + 8, + 75, + 0, + 0, // Skip to: 11715 + /* 11640 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 11643 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 11679 + /* 11648 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11651 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11665 + /* 11656 */ MCD_OPC_CheckPredicate, + 3, + 194, + 106, + 1, // Skip to: 104527 + /* 11661 */ MCD_OPC_Decode, + 197, + 9, + 22, // Opcode: CLASTA_ZPZ_B + /* 11665 */ MCD_OPC_FilterValue, + 1, + 185, + 106, + 1, // Skip to: 104527 + /* 11670 */ MCD_OPC_CheckPredicate, + 3, + 180, + 106, + 1, // Skip to: 104527 + /* 11675 */ MCD_OPC_Decode, + 199, + 9, + 22, // Opcode: CLASTA_ZPZ_H + /* 11679 */ MCD_OPC_FilterValue, + 1, + 171, + 106, + 1, // Skip to: 104527 + /* 11684 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11687 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11701 + /* 11692 */ MCD_OPC_CheckPredicate, + 3, + 158, + 106, + 1, // Skip to: 104527 + /* 11697 */ MCD_OPC_Decode, + 194, + 11, + 90, // Opcode: CPY_ZPmR_B + /* 11701 */ MCD_OPC_FilterValue, + 1, + 149, + 106, + 1, // Skip to: 104527 + /* 11706 */ MCD_OPC_CheckPredicate, + 3, + 144, + 106, + 1, // Skip to: 104527 + /* 11711 */ MCD_OPC_Decode, + 196, + 11, + 90, // Opcode: CPY_ZPmR_H + /* 11715 */ MCD_OPC_FilterValue, + 9, + 45, + 0, + 0, // Skip to: 11765 + /* 11720 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11723 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11744 + /* 11728 */ MCD_OPC_CheckPredicate, + 3, + 122, + 106, + 1, // Skip to: 104527 + /* 11733 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 115, + 106, + 1, // Skip to: 104527 + /* 11740 */ MCD_OPC_Decode, + 209, + 9, + 22, // Opcode: CLASTB_ZPZ_B + /* 11744 */ MCD_OPC_FilterValue, + 1, + 106, + 106, + 1, // Skip to: 104527 + /* 11749 */ MCD_OPC_CheckPredicate, + 3, + 101, + 106, + 1, // Skip to: 104527 + /* 11754 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 94, + 106, + 1, // Skip to: 104527 + /* 11761 */ MCD_OPC_Decode, + 211, + 9, + 22, // Opcode: CLASTB_ZPZ_H + /* 11765 */ MCD_OPC_FilterValue, + 10, + 45, + 0, + 0, // Skip to: 11815 + /* 11770 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11773 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11794 + /* 11778 */ MCD_OPC_CheckPredicate, + 3, + 72, + 106, + 1, // Skip to: 104527 + /* 11783 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 65, + 106, + 1, // Skip to: 104527 + /* 11790 */ MCD_OPC_Decode, + 193, + 9, + 91, // Opcode: CLASTA_VPZ_B + /* 11794 */ MCD_OPC_FilterValue, + 1, + 56, + 106, + 1, // Skip to: 104527 + /* 11799 */ MCD_OPC_CheckPredicate, + 3, + 51, + 106, + 1, // Skip to: 104527 + /* 11804 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 44, + 106, + 1, // Skip to: 104527 + /* 11811 */ MCD_OPC_Decode, + 195, + 9, + 92, // Opcode: CLASTA_VPZ_H + /* 11815 */ MCD_OPC_FilterValue, + 11, + 45, + 0, + 0, // Skip to: 11865 + /* 11820 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11823 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11844 + /* 11828 */ MCD_OPC_CheckPredicate, + 3, + 22, + 106, + 1, // Skip to: 104527 + /* 11833 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 15, + 106, + 1, // Skip to: 104527 + /* 11840 */ MCD_OPC_Decode, + 205, + 9, + 91, // Opcode: CLASTB_VPZ_B + /* 11844 */ MCD_OPC_FilterValue, + 1, + 6, + 106, + 1, // Skip to: 104527 + /* 11849 */ MCD_OPC_CheckPredicate, + 3, + 1, + 106, + 1, // Skip to: 104527 + /* 11854 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 250, + 105, + 1, // Skip to: 104527 + /* 11861 */ MCD_OPC_Decode, + 207, + 9, + 92, // Opcode: CLASTB_VPZ_H + /* 11865 */ MCD_OPC_FilterValue, + 12, + 45, + 0, + 0, // Skip to: 11915 + /* 11870 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11873 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11894 + /* 11878 */ MCD_OPC_CheckPredicate, + 3, + 228, + 105, + 1, // Skip to: 104527 + /* 11883 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 221, + 105, + 1, // Skip to: 104527 + /* 11890 */ MCD_OPC_Decode, + 245, + 32, + 22, // Opcode: SPLICE_ZPZ_B + /* 11894 */ MCD_OPC_FilterValue, + 1, + 212, + 105, + 1, // Skip to: 104527 + /* 11899 */ MCD_OPC_CheckPredicate, + 3, + 207, + 105, + 1, // Skip to: 104527 + /* 11904 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 200, + 105, + 1, // Skip to: 104527 + /* 11911 */ MCD_OPC_Decode, + 247, + 32, + 22, // Opcode: SPLICE_ZPZ_H + /* 11915 */ MCD_OPC_FilterValue, + 13, + 45, + 0, + 0, // Skip to: 11965 + /* 11920 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 11923 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11944 + /* 11928 */ MCD_OPC_CheckPredicate, + 4, + 178, + 105, + 1, // Skip to: 104527 + /* 11933 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 171, + 105, + 1, // Skip to: 104527 + /* 11940 */ MCD_OPC_Decode, + 241, + 32, + 93, // Opcode: SPLICE_ZPZZ_B + /* 11944 */ MCD_OPC_FilterValue, + 1, + 162, + 105, + 1, // Skip to: 104527 + /* 11949 */ MCD_OPC_CheckPredicate, + 4, + 157, + 105, + 1, // Skip to: 104527 + /* 11954 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 150, + 105, + 1, // Skip to: 104527 + /* 11961 */ MCD_OPC_Decode, + 243, + 32, + 93, // Opcode: SPLICE_ZPZZ_H + /* 11965 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 11993 + /* 11970 */ MCD_OPC_CheckPredicate, + 0, + 136, + 105, + 1, // Skip to: 104527 + /* 11975 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 129, + 105, + 1, // Skip to: 104527 + /* 11982 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 122, + 105, + 1, // Skip to: 104527 + /* 11989 */ MCD_OPC_Decode, + 177, + 29, + 24, // Opcode: REVD_ZPmZ + /* 11993 */ MCD_OPC_FilterValue, + 16, + 45, + 0, + 0, // Skip to: 12043 + /* 11998 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12001 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12022 + /* 12006 */ MCD_OPC_CheckPredicate, + 3, + 100, + 105, + 1, // Skip to: 104527 + /* 12011 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 93, + 105, + 1, // Skip to: 104527 + /* 12018 */ MCD_OPC_Decode, + 189, + 9, + 94, // Opcode: CLASTA_RPZ_B + /* 12022 */ MCD_OPC_FilterValue, + 1, + 84, + 105, + 1, // Skip to: 104527 + /* 12027 */ MCD_OPC_CheckPredicate, + 3, + 79, + 105, + 1, // Skip to: 104527 + /* 12032 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 72, + 105, + 1, // Skip to: 104527 + /* 12039 */ MCD_OPC_Decode, + 191, + 9, + 94, // Opcode: CLASTA_RPZ_H + /* 12043 */ MCD_OPC_FilterValue, + 17, + 63, + 105, + 1, // Skip to: 104527 + /* 12048 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12051 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12072 + /* 12056 */ MCD_OPC_CheckPredicate, + 3, + 50, + 105, + 1, // Skip to: 104527 + /* 12061 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 43, + 105, + 1, // Skip to: 104527 + /* 12068 */ MCD_OPC_Decode, + 201, + 9, + 94, // Opcode: CLASTB_RPZ_B + /* 12072 */ MCD_OPC_FilterValue, + 1, + 34, + 105, + 1, // Skip to: 104527 + /* 12077 */ MCD_OPC_CheckPredicate, + 3, + 29, + 105, + 1, // Skip to: 104527 + /* 12082 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 22, + 105, + 1, // Skip to: 104527 + /* 12089 */ MCD_OPC_Decode, + 203, + 9, + 94, // Opcode: CLASTB_RPZ_H + /* 12093 */ MCD_OPC_FilterValue, + 3, + 13, + 105, + 1, // Skip to: 104527 + /* 12098 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 12101 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 12181 + /* 12106 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 12109 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 12145 + /* 12114 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12117 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 12131 + /* 12122 */ MCD_OPC_CheckPredicate, + 3, + 240, + 104, + 1, // Skip to: 104527 + /* 12127 */ MCD_OPC_Decode, + 201, + 11, + 95, // Opcode: CPY_ZPmV_S + /* 12131 */ MCD_OPC_FilterValue, + 1, + 231, + 104, + 1, // Skip to: 104527 + /* 12136 */ MCD_OPC_CheckPredicate, + 3, + 226, + 104, + 1, // Skip to: 104527 + /* 12141 */ MCD_OPC_Decode, + 199, + 11, + 96, // Opcode: CPY_ZPmV_D + /* 12145 */ MCD_OPC_FilterValue, + 1, + 217, + 104, + 1, // Skip to: 104527 + /* 12150 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12153 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 12167 + /* 12158 */ MCD_OPC_CheckPredicate, + 3, + 204, + 104, + 1, // Skip to: 104527 + /* 12163 */ MCD_OPC_Decode, + 196, + 21, + 87, // Opcode: LASTA_RPZ_S + /* 12167 */ MCD_OPC_FilterValue, + 1, + 195, + 104, + 1, // Skip to: 104527 + /* 12172 */ MCD_OPC_CheckPredicate, + 3, + 190, + 104, + 1, // Skip to: 104527 + /* 12177 */ MCD_OPC_Decode, + 194, + 21, + 97, // Opcode: LASTA_RPZ_D + /* 12181 */ MCD_OPC_FilterValue, + 1, + 75, + 0, + 0, // Skip to: 12261 + /* 12186 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 12189 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 12225 + /* 12194 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12197 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 12211 + /* 12202 */ MCD_OPC_CheckPredicate, + 6, + 160, + 104, + 1, // Skip to: 104527 + /* 12207 */ MCD_OPC_Decode, + 189, + 11, + 23, // Opcode: COMPACT_ZPZ_S + /* 12211 */ MCD_OPC_FilterValue, + 1, + 151, + 104, + 1, // Skip to: 104527 + /* 12216 */ MCD_OPC_CheckPredicate, + 6, + 146, + 104, + 1, // Skip to: 104527 + /* 12221 */ MCD_OPC_Decode, + 188, + 11, + 23, // Opcode: COMPACT_ZPZ_D + /* 12225 */ MCD_OPC_FilterValue, + 1, + 137, + 104, + 1, // Skip to: 104527 + /* 12230 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12233 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 12247 + /* 12238 */ MCD_OPC_CheckPredicate, + 3, + 124, + 104, + 1, // Skip to: 104527 + /* 12243 */ MCD_OPC_Decode, + 204, + 21, + 87, // Opcode: LASTB_RPZ_S + /* 12247 */ MCD_OPC_FilterValue, + 1, + 115, + 104, + 1, // Skip to: 104527 + /* 12252 */ MCD_OPC_CheckPredicate, + 3, + 110, + 104, + 1, // Skip to: 104527 + /* 12257 */ MCD_OPC_Decode, + 202, + 21, + 97, // Opcode: LASTB_RPZ_D + /* 12261 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 12311 + /* 12266 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12269 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12290 + /* 12274 */ MCD_OPC_CheckPredicate, + 3, + 88, + 104, + 1, // Skip to: 104527 + /* 12279 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 81, + 104, + 1, // Skip to: 104527 + /* 12286 */ MCD_OPC_Decode, + 200, + 21, + 98, // Opcode: LASTA_VPZ_S + /* 12290 */ MCD_OPC_FilterValue, + 1, + 72, + 104, + 1, // Skip to: 104527 + /* 12295 */ MCD_OPC_CheckPredicate, + 3, + 67, + 104, + 1, // Skip to: 104527 + /* 12300 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 60, + 104, + 1, // Skip to: 104527 + /* 12307 */ MCD_OPC_Decode, + 198, + 21, + 99, // Opcode: LASTA_VPZ_D + /* 12311 */ MCD_OPC_FilterValue, + 3, + 45, + 0, + 0, // Skip to: 12361 + /* 12316 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12319 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12340 + /* 12324 */ MCD_OPC_CheckPredicate, + 3, + 38, + 104, + 1, // Skip to: 104527 + /* 12329 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 31, + 104, + 1, // Skip to: 104527 + /* 12336 */ MCD_OPC_Decode, + 208, + 21, + 98, // Opcode: LASTB_VPZ_S + /* 12340 */ MCD_OPC_FilterValue, + 1, + 22, + 104, + 1, // Skip to: 104527 + /* 12345 */ MCD_OPC_CheckPredicate, + 3, + 17, + 104, + 1, // Skip to: 104527 + /* 12350 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 10, + 104, + 1, // Skip to: 104527 + /* 12357 */ MCD_OPC_Decode, + 206, + 21, + 99, // Opcode: LASTB_VPZ_D + /* 12361 */ MCD_OPC_FilterValue, + 4, + 45, + 0, + 0, // Skip to: 12411 + /* 12366 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12369 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12390 + /* 12374 */ MCD_OPC_CheckPredicate, + 3, + 244, + 103, + 1, // Skip to: 104527 + /* 12379 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 237, + 103, + 1, // Skip to: 104527 + /* 12386 */ MCD_OPC_Decode, + 176, + 29, + 24, // Opcode: REVB_ZPmZ_S + /* 12390 */ MCD_OPC_FilterValue, + 1, + 228, + 103, + 1, // Skip to: 104527 + /* 12395 */ MCD_OPC_CheckPredicate, + 3, + 223, + 103, + 1, // Skip to: 104527 + /* 12400 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 216, + 103, + 1, // Skip to: 104527 + /* 12407 */ MCD_OPC_Decode, + 174, + 29, + 24, // Opcode: REVB_ZPmZ_D + /* 12411 */ MCD_OPC_FilterValue, + 5, + 45, + 0, + 0, // Skip to: 12461 + /* 12416 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12419 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12440 + /* 12424 */ MCD_OPC_CheckPredicate, + 3, + 194, + 103, + 1, // Skip to: 104527 + /* 12429 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 187, + 103, + 1, // Skip to: 104527 + /* 12436 */ MCD_OPC_Decode, + 179, + 29, + 24, // Opcode: REVH_ZPmZ_S + /* 12440 */ MCD_OPC_FilterValue, + 1, + 178, + 103, + 1, // Skip to: 104527 + /* 12445 */ MCD_OPC_CheckPredicate, + 3, + 173, + 103, + 1, // Skip to: 104527 + /* 12450 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 166, + 103, + 1, // Skip to: 104527 + /* 12457 */ MCD_OPC_Decode, + 178, + 29, + 24, // Opcode: REVH_ZPmZ_D + /* 12461 */ MCD_OPC_FilterValue, + 6, + 23, + 0, + 0, // Skip to: 12489 + /* 12466 */ MCD_OPC_CheckPredicate, + 3, + 152, + 103, + 1, // Skip to: 104527 + /* 12471 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 145, + 103, + 1, // Skip to: 104527 + /* 12478 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 138, + 103, + 1, // Skip to: 104527 + /* 12485 */ MCD_OPC_Decode, + 180, + 29, + 24, // Opcode: REVW_ZPmZ_D + /* 12489 */ MCD_OPC_FilterValue, + 7, + 45, + 0, + 0, // Skip to: 12539 + /* 12494 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12497 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12518 + /* 12502 */ MCD_OPC_CheckPredicate, + 3, + 116, + 103, + 1, // Skip to: 104527 + /* 12507 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 109, + 103, + 1, // Skip to: 104527 + /* 12514 */ MCD_OPC_Decode, + 149, + 29, + 24, // Opcode: RBIT_ZPmZ_S + /* 12518 */ MCD_OPC_FilterValue, + 1, + 100, + 103, + 1, // Skip to: 104527 + /* 12523 */ MCD_OPC_CheckPredicate, + 3, + 95, + 103, + 1, // Skip to: 104527 + /* 12528 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 88, + 103, + 1, // Skip to: 104527 + /* 12535 */ MCD_OPC_Decode, + 147, + 29, + 24, // Opcode: RBIT_ZPmZ_D + /* 12539 */ MCD_OPC_FilterValue, + 8, + 75, + 0, + 0, // Skip to: 12619 + /* 12544 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 12547 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 12583 + /* 12552 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12555 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 12569 + /* 12560 */ MCD_OPC_CheckPredicate, + 3, + 58, + 103, + 1, // Skip to: 104527 + /* 12565 */ MCD_OPC_Decode, + 200, + 9, + 22, // Opcode: CLASTA_ZPZ_S + /* 12569 */ MCD_OPC_FilterValue, + 1, + 49, + 103, + 1, // Skip to: 104527 + /* 12574 */ MCD_OPC_CheckPredicate, + 3, + 44, + 103, + 1, // Skip to: 104527 + /* 12579 */ MCD_OPC_Decode, + 198, + 9, + 22, // Opcode: CLASTA_ZPZ_D + /* 12583 */ MCD_OPC_FilterValue, + 1, + 35, + 103, + 1, // Skip to: 104527 + /* 12588 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12591 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 12605 + /* 12596 */ MCD_OPC_CheckPredicate, + 3, + 22, + 103, + 1, // Skip to: 104527 + /* 12601 */ MCD_OPC_Decode, + 197, + 11, + 90, // Opcode: CPY_ZPmR_S + /* 12605 */ MCD_OPC_FilterValue, + 1, + 13, + 103, + 1, // Skip to: 104527 + /* 12610 */ MCD_OPC_CheckPredicate, + 3, + 8, + 103, + 1, // Skip to: 104527 + /* 12615 */ MCD_OPC_Decode, + 195, + 11, + 100, // Opcode: CPY_ZPmR_D + /* 12619 */ MCD_OPC_FilterValue, + 9, + 45, + 0, + 0, // Skip to: 12669 + /* 12624 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12627 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12648 + /* 12632 */ MCD_OPC_CheckPredicate, + 3, + 242, + 102, + 1, // Skip to: 104527 + /* 12637 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 235, + 102, + 1, // Skip to: 104527 + /* 12644 */ MCD_OPC_Decode, + 212, + 9, + 22, // Opcode: CLASTB_ZPZ_S + /* 12648 */ MCD_OPC_FilterValue, + 1, + 226, + 102, + 1, // Skip to: 104527 + /* 12653 */ MCD_OPC_CheckPredicate, + 3, + 221, + 102, + 1, // Skip to: 104527 + /* 12658 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 214, + 102, + 1, // Skip to: 104527 + /* 12665 */ MCD_OPC_Decode, + 210, + 9, + 22, // Opcode: CLASTB_ZPZ_D + /* 12669 */ MCD_OPC_FilterValue, + 10, + 45, + 0, + 0, // Skip to: 12719 + /* 12674 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12677 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12698 + /* 12682 */ MCD_OPC_CheckPredicate, + 3, + 192, + 102, + 1, // Skip to: 104527 + /* 12687 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 185, + 102, + 1, // Skip to: 104527 + /* 12694 */ MCD_OPC_Decode, + 196, + 9, + 101, // Opcode: CLASTA_VPZ_S + /* 12698 */ MCD_OPC_FilterValue, + 1, + 176, + 102, + 1, // Skip to: 104527 + /* 12703 */ MCD_OPC_CheckPredicate, + 3, + 171, + 102, + 1, // Skip to: 104527 + /* 12708 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 164, + 102, + 1, // Skip to: 104527 + /* 12715 */ MCD_OPC_Decode, + 194, + 9, + 102, // Opcode: CLASTA_VPZ_D + /* 12719 */ MCD_OPC_FilterValue, + 11, + 45, + 0, + 0, // Skip to: 12769 + /* 12724 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12727 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12748 + /* 12732 */ MCD_OPC_CheckPredicate, + 3, + 142, + 102, + 1, // Skip to: 104527 + /* 12737 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 135, + 102, + 1, // Skip to: 104527 + /* 12744 */ MCD_OPC_Decode, + 208, + 9, + 101, // Opcode: CLASTB_VPZ_S + /* 12748 */ MCD_OPC_FilterValue, + 1, + 126, + 102, + 1, // Skip to: 104527 + /* 12753 */ MCD_OPC_CheckPredicate, + 3, + 121, + 102, + 1, // Skip to: 104527 + /* 12758 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 114, + 102, + 1, // Skip to: 104527 + /* 12765 */ MCD_OPC_Decode, + 206, + 9, + 102, // Opcode: CLASTB_VPZ_D + /* 12769 */ MCD_OPC_FilterValue, + 12, + 45, + 0, + 0, // Skip to: 12819 + /* 12774 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12777 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12798 + /* 12782 */ MCD_OPC_CheckPredicate, + 3, + 92, + 102, + 1, // Skip to: 104527 + /* 12787 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 85, + 102, + 1, // Skip to: 104527 + /* 12794 */ MCD_OPC_Decode, + 248, + 32, + 22, // Opcode: SPLICE_ZPZ_S + /* 12798 */ MCD_OPC_FilterValue, + 1, + 76, + 102, + 1, // Skip to: 104527 + /* 12803 */ MCD_OPC_CheckPredicate, + 3, + 71, + 102, + 1, // Skip to: 104527 + /* 12808 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 64, + 102, + 1, // Skip to: 104527 + /* 12815 */ MCD_OPC_Decode, + 246, + 32, + 22, // Opcode: SPLICE_ZPZ_D + /* 12819 */ MCD_OPC_FilterValue, + 13, + 45, + 0, + 0, // Skip to: 12869 + /* 12824 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12827 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12848 + /* 12832 */ MCD_OPC_CheckPredicate, + 4, + 42, + 102, + 1, // Skip to: 104527 + /* 12837 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 35, + 102, + 1, // Skip to: 104527 + /* 12844 */ MCD_OPC_Decode, + 244, + 32, + 93, // Opcode: SPLICE_ZPZZ_S + /* 12848 */ MCD_OPC_FilterValue, + 1, + 26, + 102, + 1, // Skip to: 104527 + /* 12853 */ MCD_OPC_CheckPredicate, + 4, + 21, + 102, + 1, // Skip to: 104527 + /* 12858 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 14, + 102, + 1, // Skip to: 104527 + /* 12865 */ MCD_OPC_Decode, + 242, + 32, + 93, // Opcode: SPLICE_ZPZZ_D + /* 12869 */ MCD_OPC_FilterValue, + 16, + 45, + 0, + 0, // Skip to: 12919 + /* 12874 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12877 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12898 + /* 12882 */ MCD_OPC_CheckPredicate, + 3, + 248, + 101, + 1, // Skip to: 104527 + /* 12887 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 241, + 101, + 1, // Skip to: 104527 + /* 12894 */ MCD_OPC_Decode, + 192, + 9, + 94, // Opcode: CLASTA_RPZ_S + /* 12898 */ MCD_OPC_FilterValue, + 1, + 232, + 101, + 1, // Skip to: 104527 + /* 12903 */ MCD_OPC_CheckPredicate, + 3, + 227, + 101, + 1, // Skip to: 104527 + /* 12908 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 220, + 101, + 1, // Skip to: 104527 + /* 12915 */ MCD_OPC_Decode, + 190, + 9, + 103, // Opcode: CLASTA_RPZ_D + /* 12919 */ MCD_OPC_FilterValue, + 17, + 211, + 101, + 1, // Skip to: 104527 + /* 12924 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 12927 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 12948 + /* 12932 */ MCD_OPC_CheckPredicate, + 3, + 198, + 101, + 1, // Skip to: 104527 + /* 12937 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 191, + 101, + 1, // Skip to: 104527 + /* 12944 */ MCD_OPC_Decode, + 204, + 9, + 94, // Opcode: CLASTB_RPZ_S + /* 12948 */ MCD_OPC_FilterValue, + 1, + 182, + 101, + 1, // Skip to: 104527 + /* 12953 */ MCD_OPC_CheckPredicate, + 3, + 177, + 101, + 1, // Skip to: 104527 + /* 12958 */ MCD_OPC_CheckField, + 13, + 1, + 1, + 170, + 101, + 1, // Skip to: 104527 + /* 12965 */ MCD_OPC_Decode, + 202, + 9, + 103, // Opcode: CLASTB_RPZ_D + /* 12969 */ MCD_OPC_FilterValue, + 3, + 161, + 101, + 1, // Skip to: 104527 + /* 12974 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 12977 */ MCD_OPC_FilterValue, + 0, + 204, + 0, + 0, // Skip to: 13186 + /* 12982 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 12985 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 13021 + /* 12990 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 12993 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13007 + /* 12998 */ MCD_OPC_CheckPredicate, + 3, + 132, + 101, + 1, // Skip to: 104527 + /* 13003 */ MCD_OPC_Decode, + 174, + 11, + 104, // Opcode: CNTB_XPiI + /* 13007 */ MCD_OPC_FilterValue, + 1, + 123, + 101, + 1, // Skip to: 104527 + /* 13012 */ MCD_OPC_CheckPredicate, + 3, + 118, + 101, + 1, // Skip to: 104527 + /* 13017 */ MCD_OPC_Decode, + 135, + 21, + 105, // Opcode: INCB_XPiI + /* 13021 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 13042 + /* 13026 */ MCD_OPC_CheckPredicate, + 3, + 104, + 101, + 1, // Skip to: 104527 + /* 13031 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 97, + 101, + 1, // Skip to: 104527 + /* 13038 */ MCD_OPC_Decode, + 233, + 11, + 105, // Opcode: DECB_XPiI + /* 13042 */ MCD_OPC_FilterValue, + 12, + 31, + 0, + 0, // Skip to: 13078 + /* 13047 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13050 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13064 + /* 13055 */ MCD_OPC_CheckPredicate, + 3, + 75, + 101, + 1, // Skip to: 104527 + /* 13060 */ MCD_OPC_Decode, + 149, + 34, + 105, // Opcode: SQINCB_XPiWdI + /* 13064 */ MCD_OPC_FilterValue, + 1, + 66, + 101, + 1, // Skip to: 104527 + /* 13069 */ MCD_OPC_CheckPredicate, + 3, + 61, + 101, + 1, // Skip to: 104527 + /* 13074 */ MCD_OPC_Decode, + 148, + 34, + 105, // Opcode: SQINCB_XPiI + /* 13078 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 13114 + /* 13083 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13086 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13100 + /* 13091 */ MCD_OPC_CheckPredicate, + 3, + 39, + 101, + 1, // Skip to: 104527 + /* 13096 */ MCD_OPC_Decode, + 202, + 44, + 106, // Opcode: UQINCB_WPiI + /* 13100 */ MCD_OPC_FilterValue, + 1, + 30, + 101, + 1, // Skip to: 104527 + /* 13105 */ MCD_OPC_CheckPredicate, + 3, + 25, + 101, + 1, // Skip to: 104527 + /* 13110 */ MCD_OPC_Decode, + 203, + 44, + 105, // Opcode: UQINCB_XPiI + /* 13114 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 13150 + /* 13119 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13122 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13136 + /* 13127 */ MCD_OPC_CheckPredicate, + 3, + 3, + 101, + 1, // Skip to: 104527 + /* 13132 */ MCD_OPC_Decode, + 164, + 33, + 105, // Opcode: SQDECB_XPiWdI + /* 13136 */ MCD_OPC_FilterValue, + 1, + 250, + 100, + 1, // Skip to: 104527 + /* 13141 */ MCD_OPC_CheckPredicate, + 3, + 245, + 100, + 1, // Skip to: 104527 + /* 13146 */ MCD_OPC_Decode, + 163, + 33, + 105, // Opcode: SQDECB_XPiI + /* 13150 */ MCD_OPC_FilterValue, + 15, + 236, + 100, + 1, // Skip to: 104527 + /* 13155 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13158 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13172 + /* 13163 */ MCD_OPC_CheckPredicate, + 3, + 223, + 100, + 1, // Skip to: 104527 + /* 13168 */ MCD_OPC_Decode, + 180, + 44, + 106, // Opcode: UQDECB_WPiI + /* 13172 */ MCD_OPC_FilterValue, + 1, + 214, + 100, + 1, // Skip to: 104527 + /* 13177 */ MCD_OPC_CheckPredicate, + 3, + 209, + 100, + 1, // Skip to: 104527 + /* 13182 */ MCD_OPC_Decode, + 181, + 44, + 105, // Opcode: UQDECB_XPiI + /* 13186 */ MCD_OPC_FilterValue, + 1, + 62, + 1, + 0, // Skip to: 13509 + /* 13191 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 13194 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 13230 + /* 13199 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13202 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13216 + /* 13207 */ MCD_OPC_CheckPredicate, + 3, + 179, + 100, + 1, // Skip to: 104527 + /* 13212 */ MCD_OPC_Decode, + 155, + 34, + 107, // Opcode: SQINCH_ZPiI + /* 13216 */ MCD_OPC_FilterValue, + 1, + 170, + 100, + 1, // Skip to: 104527 + /* 13221 */ MCD_OPC_CheckPredicate, + 3, + 165, + 100, + 1, // Skip to: 104527 + /* 13226 */ MCD_OPC_Decode, + 139, + 21, + 107, // Opcode: INCH_ZPiI + /* 13230 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 13266 + /* 13235 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13238 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13252 + /* 13243 */ MCD_OPC_CheckPredicate, + 3, + 143, + 100, + 1, // Skip to: 104527 + /* 13248 */ MCD_OPC_Decode, + 209, + 44, + 107, // Opcode: UQINCH_ZPiI + /* 13252 */ MCD_OPC_FilterValue, + 1, + 134, + 100, + 1, // Skip to: 104527 + /* 13257 */ MCD_OPC_CheckPredicate, + 3, + 129, + 100, + 1, // Skip to: 104527 + /* 13262 */ MCD_OPC_Decode, + 237, + 11, + 107, // Opcode: DECH_ZPiI + /* 13266 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 13287 + /* 13271 */ MCD_OPC_CheckPredicate, + 3, + 115, + 100, + 1, // Skip to: 104527 + /* 13276 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 108, + 100, + 1, // Skip to: 104527 + /* 13283 */ MCD_OPC_Decode, + 170, + 33, + 107, // Opcode: SQDECH_ZPiI + /* 13287 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 13308 + /* 13292 */ MCD_OPC_CheckPredicate, + 3, + 94, + 100, + 1, // Skip to: 104527 + /* 13297 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 87, + 100, + 1, // Skip to: 104527 + /* 13304 */ MCD_OPC_Decode, + 187, + 44, + 107, // Opcode: UQDECH_ZPiI + /* 13308 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 13344 + /* 13313 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13316 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13330 + /* 13321 */ MCD_OPC_CheckPredicate, + 3, + 65, + 100, + 1, // Skip to: 104527 + /* 13326 */ MCD_OPC_Decode, + 176, + 11, + 104, // Opcode: CNTH_XPiI + /* 13330 */ MCD_OPC_FilterValue, + 1, + 56, + 100, + 1, // Skip to: 104527 + /* 13335 */ MCD_OPC_CheckPredicate, + 3, + 51, + 100, + 1, // Skip to: 104527 + /* 13340 */ MCD_OPC_Decode, + 138, + 21, + 105, // Opcode: INCH_XPiI + /* 13344 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 13365 + /* 13349 */ MCD_OPC_CheckPredicate, + 3, + 37, + 100, + 1, // Skip to: 104527 + /* 13354 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 30, + 100, + 1, // Skip to: 104527 + /* 13361 */ MCD_OPC_Decode, + 236, + 11, + 105, // Opcode: DECH_XPiI + /* 13365 */ MCD_OPC_FilterValue, + 12, + 31, + 0, + 0, // Skip to: 13401 + /* 13370 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13373 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13387 + /* 13378 */ MCD_OPC_CheckPredicate, + 3, + 8, + 100, + 1, // Skip to: 104527 + /* 13383 */ MCD_OPC_Decode, + 154, + 34, + 105, // Opcode: SQINCH_XPiWdI + /* 13387 */ MCD_OPC_FilterValue, + 1, + 255, + 99, + 1, // Skip to: 104527 + /* 13392 */ MCD_OPC_CheckPredicate, + 3, + 250, + 99, + 1, // Skip to: 104527 + /* 13397 */ MCD_OPC_Decode, + 153, + 34, + 105, // Opcode: SQINCH_XPiI + /* 13401 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 13437 + /* 13406 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13409 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13423 + /* 13414 */ MCD_OPC_CheckPredicate, + 3, + 228, + 99, + 1, // Skip to: 104527 + /* 13419 */ MCD_OPC_Decode, + 207, + 44, + 106, // Opcode: UQINCH_WPiI + /* 13423 */ MCD_OPC_FilterValue, + 1, + 219, + 99, + 1, // Skip to: 104527 + /* 13428 */ MCD_OPC_CheckPredicate, + 3, + 214, + 99, + 1, // Skip to: 104527 + /* 13433 */ MCD_OPC_Decode, + 208, + 44, + 105, // Opcode: UQINCH_XPiI + /* 13437 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 13473 + /* 13442 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13445 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13459 + /* 13450 */ MCD_OPC_CheckPredicate, + 3, + 192, + 99, + 1, // Skip to: 104527 + /* 13455 */ MCD_OPC_Decode, + 169, + 33, + 105, // Opcode: SQDECH_XPiWdI + /* 13459 */ MCD_OPC_FilterValue, + 1, + 183, + 99, + 1, // Skip to: 104527 + /* 13464 */ MCD_OPC_CheckPredicate, + 3, + 178, + 99, + 1, // Skip to: 104527 + /* 13469 */ MCD_OPC_Decode, + 168, + 33, + 105, // Opcode: SQDECH_XPiI + /* 13473 */ MCD_OPC_FilterValue, + 15, + 169, + 99, + 1, // Skip to: 104527 + /* 13478 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13481 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13495 + /* 13486 */ MCD_OPC_CheckPredicate, + 3, + 156, + 99, + 1, // Skip to: 104527 + /* 13491 */ MCD_OPC_Decode, + 185, + 44, + 106, // Opcode: UQDECH_WPiI + /* 13495 */ MCD_OPC_FilterValue, + 1, + 147, + 99, + 1, // Skip to: 104527 + /* 13500 */ MCD_OPC_CheckPredicate, + 3, + 142, + 99, + 1, // Skip to: 104527 + /* 13505 */ MCD_OPC_Decode, + 186, + 44, + 105, // Opcode: UQDECH_XPiI + /* 13509 */ MCD_OPC_FilterValue, + 2, + 62, + 1, + 0, // Skip to: 13832 + /* 13514 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 13517 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 13553 + /* 13522 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13525 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13539 + /* 13530 */ MCD_OPC_CheckPredicate, + 3, + 112, + 99, + 1, // Skip to: 104527 + /* 13535 */ MCD_OPC_Decode, + 169, + 34, + 107, // Opcode: SQINCW_ZPiI + /* 13539 */ MCD_OPC_FilterValue, + 1, + 103, + 99, + 1, // Skip to: 104527 + /* 13544 */ MCD_OPC_CheckPredicate, + 3, + 98, + 99, + 1, // Skip to: 104527 + /* 13549 */ MCD_OPC_Decode, + 148, + 21, + 107, // Opcode: INCW_ZPiI + /* 13553 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 13589 + /* 13558 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13561 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13575 + /* 13566 */ MCD_OPC_CheckPredicate, + 3, + 76, + 99, + 1, // Skip to: 104527 + /* 13571 */ MCD_OPC_Decode, + 223, + 44, + 107, // Opcode: UQINCW_ZPiI + /* 13575 */ MCD_OPC_FilterValue, + 1, + 67, + 99, + 1, // Skip to: 104527 + /* 13580 */ MCD_OPC_CheckPredicate, + 3, + 62, + 99, + 1, // Skip to: 104527 + /* 13585 */ MCD_OPC_Decode, + 246, + 11, + 107, // Opcode: DECW_ZPiI + /* 13589 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 13610 + /* 13594 */ MCD_OPC_CheckPredicate, + 3, + 48, + 99, + 1, // Skip to: 104527 + /* 13599 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 41, + 99, + 1, // Skip to: 104527 + /* 13606 */ MCD_OPC_Decode, + 184, + 33, + 107, // Opcode: SQDECW_ZPiI + /* 13610 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 13631 + /* 13615 */ MCD_OPC_CheckPredicate, + 3, + 27, + 99, + 1, // Skip to: 104527 + /* 13620 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 20, + 99, + 1, // Skip to: 104527 + /* 13627 */ MCD_OPC_Decode, + 201, + 44, + 107, // Opcode: UQDECW_ZPiI + /* 13631 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 13667 + /* 13636 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13639 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13653 + /* 13644 */ MCD_OPC_CheckPredicate, + 3, + 254, + 98, + 1, // Skip to: 104527 + /* 13649 */ MCD_OPC_Decode, + 181, + 11, + 104, // Opcode: CNTW_XPiI + /* 13653 */ MCD_OPC_FilterValue, + 1, + 245, + 98, + 1, // Skip to: 104527 + /* 13658 */ MCD_OPC_CheckPredicate, + 3, + 240, + 98, + 1, // Skip to: 104527 + /* 13663 */ MCD_OPC_Decode, + 147, + 21, + 105, // Opcode: INCW_XPiI + /* 13667 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 13688 + /* 13672 */ MCD_OPC_CheckPredicate, + 3, + 226, + 98, + 1, // Skip to: 104527 + /* 13677 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 219, + 98, + 1, // Skip to: 104527 + /* 13684 */ MCD_OPC_Decode, + 245, + 11, + 105, // Opcode: DECW_XPiI + /* 13688 */ MCD_OPC_FilterValue, + 12, + 31, + 0, + 0, // Skip to: 13724 + /* 13693 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13696 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13710 + /* 13701 */ MCD_OPC_CheckPredicate, + 3, + 197, + 98, + 1, // Skip to: 104527 + /* 13706 */ MCD_OPC_Decode, + 168, + 34, + 105, // Opcode: SQINCW_XPiWdI + /* 13710 */ MCD_OPC_FilterValue, + 1, + 188, + 98, + 1, // Skip to: 104527 + /* 13715 */ MCD_OPC_CheckPredicate, + 3, + 183, + 98, + 1, // Skip to: 104527 + /* 13720 */ MCD_OPC_Decode, + 167, + 34, + 105, // Opcode: SQINCW_XPiI + /* 13724 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 13760 + /* 13729 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13732 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13746 + /* 13737 */ MCD_OPC_CheckPredicate, + 3, + 161, + 98, + 1, // Skip to: 104527 + /* 13742 */ MCD_OPC_Decode, + 221, + 44, + 106, // Opcode: UQINCW_WPiI + /* 13746 */ MCD_OPC_FilterValue, + 1, + 152, + 98, + 1, // Skip to: 104527 + /* 13751 */ MCD_OPC_CheckPredicate, + 3, + 147, + 98, + 1, // Skip to: 104527 + /* 13756 */ MCD_OPC_Decode, + 222, + 44, + 105, // Opcode: UQINCW_XPiI + /* 13760 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 13796 + /* 13765 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13768 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13782 + /* 13773 */ MCD_OPC_CheckPredicate, + 3, + 125, + 98, + 1, // Skip to: 104527 + /* 13778 */ MCD_OPC_Decode, + 183, + 33, + 105, // Opcode: SQDECW_XPiWdI + /* 13782 */ MCD_OPC_FilterValue, + 1, + 116, + 98, + 1, // Skip to: 104527 + /* 13787 */ MCD_OPC_CheckPredicate, + 3, + 111, + 98, + 1, // Skip to: 104527 + /* 13792 */ MCD_OPC_Decode, + 182, + 33, + 105, // Opcode: SQDECW_XPiI + /* 13796 */ MCD_OPC_FilterValue, + 15, + 102, + 98, + 1, // Skip to: 104527 + /* 13801 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13804 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13818 + /* 13809 */ MCD_OPC_CheckPredicate, + 3, + 89, + 98, + 1, // Skip to: 104527 + /* 13814 */ MCD_OPC_Decode, + 199, + 44, + 106, // Opcode: UQDECW_WPiI + /* 13818 */ MCD_OPC_FilterValue, + 1, + 80, + 98, + 1, // Skip to: 104527 + /* 13823 */ MCD_OPC_CheckPredicate, + 3, + 75, + 98, + 1, // Skip to: 104527 + /* 13828 */ MCD_OPC_Decode, + 200, + 44, + 105, // Opcode: UQDECW_XPiI + /* 13832 */ MCD_OPC_FilterValue, + 3, + 62, + 1, + 0, // Skip to: 14155 + /* 13837 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 13840 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 13876 + /* 13845 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13848 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13862 + /* 13853 */ MCD_OPC_CheckPredicate, + 3, + 45, + 98, + 1, // Skip to: 104527 + /* 13858 */ MCD_OPC_Decode, + 152, + 34, + 107, // Opcode: SQINCD_ZPiI + /* 13862 */ MCD_OPC_FilterValue, + 1, + 36, + 98, + 1, // Skip to: 104527 + /* 13867 */ MCD_OPC_CheckPredicate, + 3, + 31, + 98, + 1, // Skip to: 104527 + /* 13872 */ MCD_OPC_Decode, + 137, + 21, + 107, // Opcode: INCD_ZPiI + /* 13876 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 13912 + /* 13881 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13884 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13898 + /* 13889 */ MCD_OPC_CheckPredicate, + 3, + 9, + 98, + 1, // Skip to: 104527 + /* 13894 */ MCD_OPC_Decode, + 206, + 44, + 107, // Opcode: UQINCD_ZPiI + /* 13898 */ MCD_OPC_FilterValue, + 1, + 0, + 98, + 1, // Skip to: 104527 + /* 13903 */ MCD_OPC_CheckPredicate, + 3, + 251, + 97, + 1, // Skip to: 104527 + /* 13908 */ MCD_OPC_Decode, + 235, + 11, + 107, // Opcode: DECD_ZPiI + /* 13912 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 13933 + /* 13917 */ MCD_OPC_CheckPredicate, + 3, + 237, + 97, + 1, // Skip to: 104527 + /* 13922 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 230, + 97, + 1, // Skip to: 104527 + /* 13929 */ MCD_OPC_Decode, + 167, + 33, + 107, // Opcode: SQDECD_ZPiI + /* 13933 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 13954 + /* 13938 */ MCD_OPC_CheckPredicate, + 3, + 216, + 97, + 1, // Skip to: 104527 + /* 13943 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 209, + 97, + 1, // Skip to: 104527 + /* 13950 */ MCD_OPC_Decode, + 184, + 44, + 107, // Opcode: UQDECD_ZPiI + /* 13954 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 13990 + /* 13959 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13962 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13976 + /* 13967 */ MCD_OPC_CheckPredicate, + 3, + 187, + 97, + 1, // Skip to: 104527 + /* 13972 */ MCD_OPC_Decode, + 175, + 11, + 104, // Opcode: CNTD_XPiI + /* 13976 */ MCD_OPC_FilterValue, + 1, + 178, + 97, + 1, // Skip to: 104527 + /* 13981 */ MCD_OPC_CheckPredicate, + 3, + 173, + 97, + 1, // Skip to: 104527 + /* 13986 */ MCD_OPC_Decode, + 136, + 21, + 105, // Opcode: INCD_XPiI + /* 13990 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 14011 + /* 13995 */ MCD_OPC_CheckPredicate, + 3, + 159, + 97, + 1, // Skip to: 104527 + /* 14000 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 152, + 97, + 1, // Skip to: 104527 + /* 14007 */ MCD_OPC_Decode, + 234, + 11, + 105, // Opcode: DECD_XPiI + /* 14011 */ MCD_OPC_FilterValue, + 12, + 31, + 0, + 0, // Skip to: 14047 + /* 14016 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 14019 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14033 + /* 14024 */ MCD_OPC_CheckPredicate, + 3, + 130, + 97, + 1, // Skip to: 104527 + /* 14029 */ MCD_OPC_Decode, + 151, + 34, + 105, // Opcode: SQINCD_XPiWdI + /* 14033 */ MCD_OPC_FilterValue, + 1, + 121, + 97, + 1, // Skip to: 104527 + /* 14038 */ MCD_OPC_CheckPredicate, + 3, + 116, + 97, + 1, // Skip to: 104527 + /* 14043 */ MCD_OPC_Decode, + 150, + 34, + 105, // Opcode: SQINCD_XPiI + /* 14047 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 14083 + /* 14052 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 14055 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14069 + /* 14060 */ MCD_OPC_CheckPredicate, + 3, + 94, + 97, + 1, // Skip to: 104527 + /* 14065 */ MCD_OPC_Decode, + 204, + 44, + 106, // Opcode: UQINCD_WPiI + /* 14069 */ MCD_OPC_FilterValue, + 1, + 85, + 97, + 1, // Skip to: 104527 + /* 14074 */ MCD_OPC_CheckPredicate, + 3, + 80, + 97, + 1, // Skip to: 104527 + /* 14079 */ MCD_OPC_Decode, + 205, + 44, + 105, // Opcode: UQINCD_XPiI + /* 14083 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 14119 + /* 14088 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 14091 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14105 + /* 14096 */ MCD_OPC_CheckPredicate, + 3, + 58, + 97, + 1, // Skip to: 104527 + /* 14101 */ MCD_OPC_Decode, + 166, + 33, + 105, // Opcode: SQDECD_XPiWdI + /* 14105 */ MCD_OPC_FilterValue, + 1, + 49, + 97, + 1, // Skip to: 104527 + /* 14110 */ MCD_OPC_CheckPredicate, + 3, + 44, + 97, + 1, // Skip to: 104527 + /* 14115 */ MCD_OPC_Decode, + 165, + 33, + 105, // Opcode: SQDECD_XPiI + /* 14119 */ MCD_OPC_FilterValue, + 15, + 35, + 97, + 1, // Skip to: 104527 + /* 14124 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 14127 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14141 + /* 14132 */ MCD_OPC_CheckPredicate, + 3, + 22, + 97, + 1, // Skip to: 104527 + /* 14137 */ MCD_OPC_Decode, + 182, + 44, + 106, // Opcode: UQDECD_WPiI + /* 14141 */ MCD_OPC_FilterValue, + 1, + 13, + 97, + 1, // Skip to: 104527 + /* 14146 */ MCD_OPC_CheckPredicate, + 3, + 8, + 97, + 1, // Skip to: 104527 + /* 14151 */ MCD_OPC_Decode, + 183, + 44, + 105, // Opcode: UQDECD_XPiI + /* 14155 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 14169 + /* 14160 */ MCD_OPC_CheckPredicate, + 3, + 250, + 96, + 1, // Skip to: 104527 + /* 14165 */ MCD_OPC_Decode, + 249, + 30, + 108, // Opcode: SEL_ZPZZ_B + /* 14169 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 14183 + /* 14174 */ MCD_OPC_CheckPredicate, + 3, + 236, + 96, + 1, // Skip to: 104527 + /* 14179 */ MCD_OPC_Decode, + 251, + 30, + 108, // Opcode: SEL_ZPZZ_H + /* 14183 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 14197 + /* 14188 */ MCD_OPC_CheckPredicate, + 3, + 222, + 96, + 1, // Skip to: 104527 + /* 14193 */ MCD_OPC_Decode, + 252, + 30, + 108, // Opcode: SEL_ZPZZ_S + /* 14197 */ MCD_OPC_FilterValue, + 7, + 213, + 96, + 1, // Skip to: 104527 + /* 14202 */ MCD_OPC_CheckPredicate, + 3, + 208, + 96, + 1, // Skip to: 104527 + /* 14207 */ MCD_OPC_Decode, + 250, + 30, + 108, // Opcode: SEL_ZPZZ_D + /* 14211 */ MCD_OPC_FilterValue, + 1, + 141, + 27, + 0, // Skip to: 21269 + /* 14216 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 14219 */ MCD_OPC_FilterValue, + 0, + 180, + 10, + 0, // Skip to: 16964 + /* 14224 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 14227 */ MCD_OPC_FilterValue, + 0, + 35, + 1, + 0, // Skip to: 14523 + /* 14232 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 14235 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 14271 + /* 14240 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14243 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14257 + /* 14248 */ MCD_OPC_CheckPredicate, + 3, + 162, + 96, + 1, // Skip to: 104527 + /* 14253 */ MCD_OPC_Decode, + 244, + 10, + 109, // Opcode: CMPHS_PPzZZ_B + /* 14257 */ MCD_OPC_FilterValue, + 1, + 153, + 96, + 1, // Skip to: 104527 + /* 14262 */ MCD_OPC_CheckPredicate, + 3, + 148, + 96, + 1, // Skip to: 104527 + /* 14267 */ MCD_OPC_Decode, + 233, + 10, + 109, // Opcode: CMPHI_PPzZZ_B + /* 14271 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 14307 + /* 14276 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14279 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14293 + /* 14284 */ MCD_OPC_CheckPredicate, + 3, + 126, + 96, + 1, // Skip to: 104527 + /* 14289 */ MCD_OPC_Decode, + 204, + 10, + 109, // Opcode: CMPEQ_WIDE_PPzZZ_B + /* 14293 */ MCD_OPC_FilterValue, + 1, + 117, + 96, + 1, // Skip to: 104527 + /* 14298 */ MCD_OPC_CheckPredicate, + 3, + 112, + 96, + 1, // Skip to: 104527 + /* 14303 */ MCD_OPC_Decode, + 159, + 11, + 109, // Opcode: CMPNE_WIDE_PPzZZ_B + /* 14307 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 14343 + /* 14312 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14315 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14329 + /* 14320 */ MCD_OPC_CheckPredicate, + 3, + 90, + 96, + 1, // Skip to: 104527 + /* 14325 */ MCD_OPC_Decode, + 215, + 10, + 109, // Opcode: CMPGE_WIDE_PPzZZ_B + /* 14329 */ MCD_OPC_FilterValue, + 1, + 81, + 96, + 1, // Skip to: 104527 + /* 14334 */ MCD_OPC_CheckPredicate, + 3, + 76, + 96, + 1, // Skip to: 104527 + /* 14339 */ MCD_OPC_Decode, + 226, + 10, + 109, // Opcode: CMPGT_WIDE_PPzZZ_B + /* 14343 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 14379 + /* 14348 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14351 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14365 + /* 14356 */ MCD_OPC_CheckPredicate, + 3, + 54, + 96, + 1, // Skip to: 104527 + /* 14361 */ MCD_OPC_Decode, + 148, + 11, + 109, // Opcode: CMPLT_WIDE_PPzZZ_B + /* 14365 */ MCD_OPC_FilterValue, + 1, + 45, + 96, + 1, // Skip to: 104527 + /* 14370 */ MCD_OPC_CheckPredicate, + 3, + 40, + 96, + 1, // Skip to: 104527 + /* 14375 */ MCD_OPC_Decode, + 255, + 10, + 109, // Opcode: CMPLE_WIDE_PPzZZ_B + /* 14379 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 14415 + /* 14384 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14387 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14401 + /* 14392 */ MCD_OPC_CheckPredicate, + 3, + 18, + 96, + 1, // Skip to: 104527 + /* 14397 */ MCD_OPC_Decode, + 211, + 10, + 109, // Opcode: CMPGE_PPzZZ_B + /* 14401 */ MCD_OPC_FilterValue, + 1, + 9, + 96, + 1, // Skip to: 104527 + /* 14406 */ MCD_OPC_CheckPredicate, + 3, + 4, + 96, + 1, // Skip to: 104527 + /* 14411 */ MCD_OPC_Decode, + 222, + 10, + 109, // Opcode: CMPGT_PPzZZ_B + /* 14415 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 14451 + /* 14420 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14423 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14437 + /* 14428 */ MCD_OPC_CheckPredicate, + 3, + 238, + 95, + 1, // Skip to: 104527 + /* 14433 */ MCD_OPC_Decode, + 200, + 10, + 109, // Opcode: CMPEQ_PPzZZ_B + /* 14437 */ MCD_OPC_FilterValue, + 1, + 229, + 95, + 1, // Skip to: 104527 + /* 14442 */ MCD_OPC_CheckPredicate, + 3, + 224, + 95, + 1, // Skip to: 104527 + /* 14447 */ MCD_OPC_Decode, + 155, + 11, + 109, // Opcode: CMPNE_PPzZZ_B + /* 14451 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 14487 + /* 14456 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14459 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14473 + /* 14464 */ MCD_OPC_CheckPredicate, + 3, + 202, + 95, + 1, // Skip to: 104527 + /* 14469 */ MCD_OPC_Decode, + 248, + 10, + 109, // Opcode: CMPHS_WIDE_PPzZZ_B + /* 14473 */ MCD_OPC_FilterValue, + 1, + 193, + 95, + 1, // Skip to: 104527 + /* 14478 */ MCD_OPC_CheckPredicate, + 3, + 188, + 95, + 1, // Skip to: 104527 + /* 14483 */ MCD_OPC_Decode, + 237, + 10, + 109, // Opcode: CMPHI_WIDE_PPzZZ_B + /* 14487 */ MCD_OPC_FilterValue, + 7, + 179, + 95, + 1, // Skip to: 104527 + /* 14492 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14495 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14509 + /* 14500 */ MCD_OPC_CheckPredicate, + 3, + 166, + 95, + 1, // Skip to: 104527 + /* 14505 */ MCD_OPC_Decode, + 134, + 11, + 109, // Opcode: CMPLO_WIDE_PPzZZ_B + /* 14509 */ MCD_OPC_FilterValue, + 1, + 157, + 95, + 1, // Skip to: 104527 + /* 14514 */ MCD_OPC_CheckPredicate, + 3, + 152, + 95, + 1, // Skip to: 104527 + /* 14519 */ MCD_OPC_Decode, + 141, + 11, + 109, // Opcode: CMPLS_WIDE_PPzZZ_B + /* 14523 */ MCD_OPC_FilterValue, + 1, + 35, + 1, + 0, // Skip to: 14819 + /* 14528 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 14531 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 14567 + /* 14536 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14539 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14553 + /* 14544 */ MCD_OPC_CheckPredicate, + 3, + 122, + 95, + 1, // Skip to: 104527 + /* 14549 */ MCD_OPC_Decode, + 246, + 10, + 109, // Opcode: CMPHS_PPzZZ_H + /* 14553 */ MCD_OPC_FilterValue, + 1, + 113, + 95, + 1, // Skip to: 104527 + /* 14558 */ MCD_OPC_CheckPredicate, + 3, + 108, + 95, + 1, // Skip to: 104527 + /* 14563 */ MCD_OPC_Decode, + 235, + 10, + 109, // Opcode: CMPHI_PPzZZ_H + /* 14567 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 14603 + /* 14572 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14575 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14589 + /* 14580 */ MCD_OPC_CheckPredicate, + 3, + 86, + 95, + 1, // Skip to: 104527 + /* 14585 */ MCD_OPC_Decode, + 205, + 10, + 109, // Opcode: CMPEQ_WIDE_PPzZZ_H + /* 14589 */ MCD_OPC_FilterValue, + 1, + 77, + 95, + 1, // Skip to: 104527 + /* 14594 */ MCD_OPC_CheckPredicate, + 3, + 72, + 95, + 1, // Skip to: 104527 + /* 14599 */ MCD_OPC_Decode, + 160, + 11, + 109, // Opcode: CMPNE_WIDE_PPzZZ_H + /* 14603 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 14639 + /* 14608 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14611 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14625 + /* 14616 */ MCD_OPC_CheckPredicate, + 3, + 50, + 95, + 1, // Skip to: 104527 + /* 14621 */ MCD_OPC_Decode, + 216, + 10, + 109, // Opcode: CMPGE_WIDE_PPzZZ_H + /* 14625 */ MCD_OPC_FilterValue, + 1, + 41, + 95, + 1, // Skip to: 104527 + /* 14630 */ MCD_OPC_CheckPredicate, + 3, + 36, + 95, + 1, // Skip to: 104527 + /* 14635 */ MCD_OPC_Decode, + 227, + 10, + 109, // Opcode: CMPGT_WIDE_PPzZZ_H + /* 14639 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 14675 + /* 14644 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14647 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14661 + /* 14652 */ MCD_OPC_CheckPredicate, + 3, + 14, + 95, + 1, // Skip to: 104527 + /* 14657 */ MCD_OPC_Decode, + 149, + 11, + 109, // Opcode: CMPLT_WIDE_PPzZZ_H + /* 14661 */ MCD_OPC_FilterValue, + 1, + 5, + 95, + 1, // Skip to: 104527 + /* 14666 */ MCD_OPC_CheckPredicate, + 3, + 0, + 95, + 1, // Skip to: 104527 + /* 14671 */ MCD_OPC_Decode, + 128, + 11, + 109, // Opcode: CMPLE_WIDE_PPzZZ_H + /* 14675 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 14711 + /* 14680 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14683 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14697 + /* 14688 */ MCD_OPC_CheckPredicate, + 3, + 234, + 94, + 1, // Skip to: 104527 + /* 14693 */ MCD_OPC_Decode, + 213, + 10, + 109, // Opcode: CMPGE_PPzZZ_H + /* 14697 */ MCD_OPC_FilterValue, + 1, + 225, + 94, + 1, // Skip to: 104527 + /* 14702 */ MCD_OPC_CheckPredicate, + 3, + 220, + 94, + 1, // Skip to: 104527 + /* 14707 */ MCD_OPC_Decode, + 224, + 10, + 109, // Opcode: CMPGT_PPzZZ_H + /* 14711 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 14747 + /* 14716 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14719 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14733 + /* 14724 */ MCD_OPC_CheckPredicate, + 3, + 198, + 94, + 1, // Skip to: 104527 + /* 14729 */ MCD_OPC_Decode, + 202, + 10, + 109, // Opcode: CMPEQ_PPzZZ_H + /* 14733 */ MCD_OPC_FilterValue, + 1, + 189, + 94, + 1, // Skip to: 104527 + /* 14738 */ MCD_OPC_CheckPredicate, + 3, + 184, + 94, + 1, // Skip to: 104527 + /* 14743 */ MCD_OPC_Decode, + 157, + 11, + 109, // Opcode: CMPNE_PPzZZ_H + /* 14747 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 14783 + /* 14752 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14755 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14769 + /* 14760 */ MCD_OPC_CheckPredicate, + 3, + 162, + 94, + 1, // Skip to: 104527 + /* 14765 */ MCD_OPC_Decode, + 249, + 10, + 109, // Opcode: CMPHS_WIDE_PPzZZ_H + /* 14769 */ MCD_OPC_FilterValue, + 1, + 153, + 94, + 1, // Skip to: 104527 + /* 14774 */ MCD_OPC_CheckPredicate, + 3, + 148, + 94, + 1, // Skip to: 104527 + /* 14779 */ MCD_OPC_Decode, + 238, + 10, + 109, // Opcode: CMPHI_WIDE_PPzZZ_H + /* 14783 */ MCD_OPC_FilterValue, + 7, + 139, + 94, + 1, // Skip to: 104527 + /* 14788 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14791 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14805 + /* 14796 */ MCD_OPC_CheckPredicate, + 3, + 126, + 94, + 1, // Skip to: 104527 + /* 14801 */ MCD_OPC_Decode, + 135, + 11, + 109, // Opcode: CMPLO_WIDE_PPzZZ_H + /* 14805 */ MCD_OPC_FilterValue, + 1, + 117, + 94, + 1, // Skip to: 104527 + /* 14810 */ MCD_OPC_CheckPredicate, + 3, + 112, + 94, + 1, // Skip to: 104527 + /* 14815 */ MCD_OPC_Decode, + 142, + 11, + 109, // Opcode: CMPLS_WIDE_PPzZZ_H + /* 14819 */ MCD_OPC_FilterValue, + 2, + 35, + 1, + 0, // Skip to: 15115 + /* 14824 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 14827 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 14863 + /* 14832 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14835 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14849 + /* 14840 */ MCD_OPC_CheckPredicate, + 3, + 82, + 94, + 1, // Skip to: 104527 + /* 14845 */ MCD_OPC_Decode, + 247, + 10, + 109, // Opcode: CMPHS_PPzZZ_S + /* 14849 */ MCD_OPC_FilterValue, + 1, + 73, + 94, + 1, // Skip to: 104527 + /* 14854 */ MCD_OPC_CheckPredicate, + 3, + 68, + 94, + 1, // Skip to: 104527 + /* 14859 */ MCD_OPC_Decode, + 236, + 10, + 109, // Opcode: CMPHI_PPzZZ_S + /* 14863 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 14899 + /* 14868 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14871 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14885 + /* 14876 */ MCD_OPC_CheckPredicate, + 3, + 46, + 94, + 1, // Skip to: 104527 + /* 14881 */ MCD_OPC_Decode, + 206, + 10, + 109, // Opcode: CMPEQ_WIDE_PPzZZ_S + /* 14885 */ MCD_OPC_FilterValue, + 1, + 37, + 94, + 1, // Skip to: 104527 + /* 14890 */ MCD_OPC_CheckPredicate, + 3, + 32, + 94, + 1, // Skip to: 104527 + /* 14895 */ MCD_OPC_Decode, + 161, + 11, + 109, // Opcode: CMPNE_WIDE_PPzZZ_S + /* 14899 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 14935 + /* 14904 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14907 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14921 + /* 14912 */ MCD_OPC_CheckPredicate, + 3, + 10, + 94, + 1, // Skip to: 104527 + /* 14917 */ MCD_OPC_Decode, + 217, + 10, + 109, // Opcode: CMPGE_WIDE_PPzZZ_S + /* 14921 */ MCD_OPC_FilterValue, + 1, + 1, + 94, + 1, // Skip to: 104527 + /* 14926 */ MCD_OPC_CheckPredicate, + 3, + 252, + 93, + 1, // Skip to: 104527 + /* 14931 */ MCD_OPC_Decode, + 228, + 10, + 109, // Opcode: CMPGT_WIDE_PPzZZ_S + /* 14935 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 14971 + /* 14940 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14943 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14957 + /* 14948 */ MCD_OPC_CheckPredicate, + 3, + 230, + 93, + 1, // Skip to: 104527 + /* 14953 */ MCD_OPC_Decode, + 150, + 11, + 109, // Opcode: CMPLT_WIDE_PPzZZ_S + /* 14957 */ MCD_OPC_FilterValue, + 1, + 221, + 93, + 1, // Skip to: 104527 + /* 14962 */ MCD_OPC_CheckPredicate, + 3, + 216, + 93, + 1, // Skip to: 104527 + /* 14967 */ MCD_OPC_Decode, + 129, + 11, + 109, // Opcode: CMPLE_WIDE_PPzZZ_S + /* 14971 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 15007 + /* 14976 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 14979 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14993 + /* 14984 */ MCD_OPC_CheckPredicate, + 3, + 194, + 93, + 1, // Skip to: 104527 + /* 14989 */ MCD_OPC_Decode, + 214, + 10, + 109, // Opcode: CMPGE_PPzZZ_S + /* 14993 */ MCD_OPC_FilterValue, + 1, + 185, + 93, + 1, // Skip to: 104527 + /* 14998 */ MCD_OPC_CheckPredicate, + 3, + 180, + 93, + 1, // Skip to: 104527 + /* 15003 */ MCD_OPC_Decode, + 225, + 10, + 109, // Opcode: CMPGT_PPzZZ_S + /* 15007 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 15043 + /* 15012 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15015 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15029 + /* 15020 */ MCD_OPC_CheckPredicate, + 3, + 158, + 93, + 1, // Skip to: 104527 + /* 15025 */ MCD_OPC_Decode, + 203, + 10, + 109, // Opcode: CMPEQ_PPzZZ_S + /* 15029 */ MCD_OPC_FilterValue, + 1, + 149, + 93, + 1, // Skip to: 104527 + /* 15034 */ MCD_OPC_CheckPredicate, + 3, + 144, + 93, + 1, // Skip to: 104527 + /* 15039 */ MCD_OPC_Decode, + 158, + 11, + 109, // Opcode: CMPNE_PPzZZ_S + /* 15043 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 15079 + /* 15048 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15051 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15065 + /* 15056 */ MCD_OPC_CheckPredicate, + 3, + 122, + 93, + 1, // Skip to: 104527 + /* 15061 */ MCD_OPC_Decode, + 250, + 10, + 109, // Opcode: CMPHS_WIDE_PPzZZ_S + /* 15065 */ MCD_OPC_FilterValue, + 1, + 113, + 93, + 1, // Skip to: 104527 + /* 15070 */ MCD_OPC_CheckPredicate, + 3, + 108, + 93, + 1, // Skip to: 104527 + /* 15075 */ MCD_OPC_Decode, + 239, + 10, + 109, // Opcode: CMPHI_WIDE_PPzZZ_S + /* 15079 */ MCD_OPC_FilterValue, + 7, + 99, + 93, + 1, // Skip to: 104527 + /* 15084 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15087 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15101 + /* 15092 */ MCD_OPC_CheckPredicate, + 3, + 86, + 93, + 1, // Skip to: 104527 + /* 15097 */ MCD_OPC_Decode, + 136, + 11, + 109, // Opcode: CMPLO_WIDE_PPzZZ_S + /* 15101 */ MCD_OPC_FilterValue, + 1, + 77, + 93, + 1, // Skip to: 104527 + /* 15106 */ MCD_OPC_CheckPredicate, + 3, + 72, + 93, + 1, // Skip to: 104527 + /* 15111 */ MCD_OPC_Decode, + 143, + 11, + 109, // Opcode: CMPLS_WIDE_PPzZZ_S + /* 15115 */ MCD_OPC_FilterValue, + 3, + 111, + 0, + 0, // Skip to: 15231 + /* 15120 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 15123 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 15159 + /* 15128 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15131 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15145 + /* 15136 */ MCD_OPC_CheckPredicate, + 3, + 42, + 93, + 1, // Skip to: 104527 + /* 15141 */ MCD_OPC_Decode, + 245, + 10, + 109, // Opcode: CMPHS_PPzZZ_D + /* 15145 */ MCD_OPC_FilterValue, + 1, + 33, + 93, + 1, // Skip to: 104527 + /* 15150 */ MCD_OPC_CheckPredicate, + 3, + 28, + 93, + 1, // Skip to: 104527 + /* 15155 */ MCD_OPC_Decode, + 234, + 10, + 109, // Opcode: CMPHI_PPzZZ_D + /* 15159 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 15195 + /* 15164 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15167 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15181 + /* 15172 */ MCD_OPC_CheckPredicate, + 3, + 6, + 93, + 1, // Skip to: 104527 + /* 15177 */ MCD_OPC_Decode, + 212, + 10, + 109, // Opcode: CMPGE_PPzZZ_D + /* 15181 */ MCD_OPC_FilterValue, + 1, + 253, + 92, + 1, // Skip to: 104527 + /* 15186 */ MCD_OPC_CheckPredicate, + 3, + 248, + 92, + 1, // Skip to: 104527 + /* 15191 */ MCD_OPC_Decode, + 223, + 10, + 109, // Opcode: CMPGT_PPzZZ_D + /* 15195 */ MCD_OPC_FilterValue, + 5, + 239, + 92, + 1, // Skip to: 104527 + /* 15200 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15203 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15217 + /* 15208 */ MCD_OPC_CheckPredicate, + 3, + 226, + 92, + 1, // Skip to: 104527 + /* 15213 */ MCD_OPC_Decode, + 201, + 10, + 109, // Opcode: CMPEQ_PPzZZ_D + /* 15217 */ MCD_OPC_FilterValue, + 1, + 217, + 92, + 1, // Skip to: 104527 + /* 15222 */ MCD_OPC_CheckPredicate, + 3, + 212, + 92, + 1, // Skip to: 104527 + /* 15227 */ MCD_OPC_Decode, + 156, + 11, + 109, // Opcode: CMPNE_PPzZZ_D + /* 15231 */ MCD_OPC_FilterValue, + 4, + 3, + 2, + 0, // Skip to: 15751 + /* 15236 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 15239 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 15319 + /* 15244 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15247 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 15283 + /* 15252 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 15255 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15269 + /* 15260 */ MCD_OPC_CheckPredicate, + 3, + 174, + 92, + 1, // Skip to: 104527 + /* 15265 */ MCD_OPC_Decode, + 207, + 10, + 110, // Opcode: CMPGE_PPzZI_B + /* 15269 */ MCD_OPC_FilterValue, + 1, + 165, + 92, + 1, // Skip to: 104527 + /* 15274 */ MCD_OPC_CheckPredicate, + 3, + 160, + 92, + 1, // Skip to: 104527 + /* 15279 */ MCD_OPC_Decode, + 144, + 11, + 110, // Opcode: CMPLT_PPzZI_B + /* 15283 */ MCD_OPC_FilterValue, + 1, + 151, + 92, + 1, // Skip to: 104527 + /* 15288 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 15291 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15305 + /* 15296 */ MCD_OPC_CheckPredicate, + 3, + 138, + 92, + 1, // Skip to: 104527 + /* 15301 */ MCD_OPC_Decode, + 218, + 10, + 110, // Opcode: CMPGT_PPzZI_B + /* 15305 */ MCD_OPC_FilterValue, + 1, + 129, + 92, + 1, // Skip to: 104527 + /* 15310 */ MCD_OPC_CheckPredicate, + 3, + 124, + 92, + 1, // Skip to: 104527 + /* 15315 */ MCD_OPC_Decode, + 251, + 10, + 110, // Opcode: CMPLE_PPzZI_B + /* 15319 */ MCD_OPC_FilterValue, + 1, + 162, + 0, + 0, // Skip to: 15486 + /* 15324 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15327 */ MCD_OPC_FilterValue, + 0, + 82, + 0, + 0, // Skip to: 15414 + /* 15332 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 15335 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 15393 + /* 15340 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 15343 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15357 + /* 15348 */ MCD_OPC_CheckPredicate, + 3, + 86, + 92, + 1, // Skip to: 104527 + /* 15353 */ MCD_OPC_Decode, + 129, + 8, + 111, // Opcode: AND_PPzPP + /* 15357 */ MCD_OPC_FilterValue, + 1, + 77, + 92, + 1, // Skip to: 104527 + /* 15362 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 15365 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15379 + /* 15370 */ MCD_OPC_CheckPredicate, + 3, + 64, + 92, + 1, // Skip to: 104527 + /* 15375 */ MCD_OPC_Decode, + 128, + 9, + 112, // Opcode: BRKA_PPzP + /* 15379 */ MCD_OPC_FilterValue, + 8, + 55, + 92, + 1, // Skip to: 104527 + /* 15384 */ MCD_OPC_CheckPredicate, + 3, + 50, + 92, + 1, // Skip to: 104527 + /* 15389 */ MCD_OPC_Decode, + 133, + 9, + 113, // Opcode: BRKN_PPzP + /* 15393 */ MCD_OPC_FilterValue, + 1, + 41, + 92, + 1, // Skip to: 104527 + /* 15398 */ MCD_OPC_CheckPredicate, + 3, + 36, + 92, + 1, // Skip to: 104527 + /* 15403 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 29, + 92, + 1, // Skip to: 104527 + /* 15410 */ MCD_OPC_Decode, + 172, + 12, + 111, // Opcode: EOR_PPzPP + /* 15414 */ MCD_OPC_FilterValue, + 1, + 20, + 92, + 1, // Skip to: 104527 + /* 15419 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 15422 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 15465 + /* 15427 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 15430 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15444 + /* 15435 */ MCD_OPC_CheckPredicate, + 3, + 255, + 91, + 1, // Skip to: 104527 + /* 15440 */ MCD_OPC_Decode, + 224, + 8, + 111, // Opcode: BIC_PPzPP + /* 15444 */ MCD_OPC_FilterValue, + 1, + 246, + 91, + 1, // Skip to: 104527 + /* 15449 */ MCD_OPC_CheckPredicate, + 3, + 241, + 91, + 1, // Skip to: 104527 + /* 15454 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 234, + 91, + 1, // Skip to: 104527 + /* 15461 */ MCD_OPC_Decode, + 255, + 8, + 114, // Opcode: BRKA_PPmP + /* 15465 */ MCD_OPC_FilterValue, + 1, + 225, + 91, + 1, // Skip to: 104527 + /* 15470 */ MCD_OPC_CheckPredicate, + 3, + 220, + 91, + 1, // Skip to: 104527 + /* 15475 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 213, + 91, + 1, // Skip to: 104527 + /* 15482 */ MCD_OPC_Decode, + 248, + 30, + 111, // Opcode: SEL_PPPP + /* 15486 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 15536 + /* 15491 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15494 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 15515 + /* 15499 */ MCD_OPC_CheckPredicate, + 3, + 191, + 91, + 1, // Skip to: 104527 + /* 15504 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 184, + 91, + 1, // Skip to: 104527 + /* 15511 */ MCD_OPC_Decode, + 196, + 10, + 110, // Opcode: CMPEQ_PPzZI_B + /* 15515 */ MCD_OPC_FilterValue, + 1, + 175, + 91, + 1, // Skip to: 104527 + /* 15520 */ MCD_OPC_CheckPredicate, + 3, + 170, + 91, + 1, // Skip to: 104527 + /* 15525 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 163, + 91, + 1, // Skip to: 104527 + /* 15532 */ MCD_OPC_Decode, + 151, + 11, + 110, // Opcode: CMPNE_PPzZI_B + /* 15536 */ MCD_OPC_FilterValue, + 3, + 154, + 91, + 1, // Skip to: 104527 + /* 15541 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15544 */ MCD_OPC_FilterValue, + 0, + 174, + 0, + 0, // Skip to: 15723 + /* 15549 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 15552 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 15573 + /* 15557 */ MCD_OPC_CheckPredicate, + 3, + 133, + 91, + 1, // Skip to: 104527 + /* 15562 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 126, + 91, + 1, // Skip to: 104527 + /* 15569 */ MCD_OPC_Decode, + 135, + 9, + 111, // Opcode: BRKPA_PPzPP + /* 15573 */ MCD_OPC_FilterValue, + 1, + 117, + 91, + 1, // Skip to: 104527 + /* 15578 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 15581 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 15609 + /* 15586 */ MCD_OPC_CheckPredicate, + 3, + 104, + 91, + 1, // Skip to: 104527 + /* 15591 */ MCD_OPC_CheckField, + 16, + 4, + 9, + 97, + 91, + 1, // Skip to: 104527 + /* 15598 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 90, + 91, + 1, // Skip to: 104527 + /* 15605 */ MCD_OPC_Decode, + 198, + 28, + 115, // Opcode: PNEXT_B + /* 15609 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 15645 + /* 15614 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 15617 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 15631 + /* 15622 */ MCD_OPC_CheckPredicate, + 3, + 68, + 91, + 1, // Skip to: 104527 + /* 15627 */ MCD_OPC_Decode, + 252, + 28, + 116, // Opcode: PTRUE_B + /* 15631 */ MCD_OPC_FilterValue, + 9, + 59, + 91, + 1, // Skip to: 104527 + /* 15636 */ MCD_OPC_CheckPredicate, + 3, + 54, + 91, + 1, // Skip to: 104527 + /* 15641 */ MCD_OPC_Decode, + 248, + 28, + 116, // Opcode: PTRUES_B + /* 15645 */ MCD_OPC_FilterValue, + 9, + 23, + 0, + 0, // Skip to: 15673 + /* 15650 */ MCD_OPC_CheckPredicate, + 3, + 40, + 91, + 1, // Skip to: 104527 + /* 15655 */ MCD_OPC_CheckField, + 16, + 4, + 8, + 33, + 91, + 1, // Skip to: 104527 + /* 15662 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 26, + 91, + 1, // Skip to: 104527 + /* 15669 */ MCD_OPC_Decode, + 183, + 28, + 117, // Opcode: PFALSE + /* 15673 */ MCD_OPC_FilterValue, + 12, + 17, + 91, + 1, // Skip to: 104527 + /* 15678 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 15681 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 15702 + /* 15686 */ MCD_OPC_CheckPredicate, + 6, + 4, + 91, + 1, // Skip to: 104527 + /* 15691 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 253, + 90, + 1, // Skip to: 104527 + /* 15698 */ MCD_OPC_Decode, + 153, + 29, + 76, // Opcode: RDFFR_PPz_REAL + /* 15702 */ MCD_OPC_FilterValue, + 9, + 244, + 90, + 1, // Skip to: 104527 + /* 15707 */ MCD_OPC_CheckPredicate, + 6, + 239, + 90, + 1, // Skip to: 104527 + /* 15712 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 232, + 90, + 1, // Skip to: 104527 + /* 15719 */ MCD_OPC_Decode, + 154, + 29, + 117, // Opcode: RDFFR_P_REAL + /* 15723 */ MCD_OPC_FilterValue, + 1, + 223, + 90, + 1, // Skip to: 104527 + /* 15728 */ MCD_OPC_CheckPredicate, + 3, + 218, + 90, + 1, // Skip to: 104527 + /* 15733 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 211, + 90, + 1, // Skip to: 104527 + /* 15740 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 204, + 90, + 1, // Skip to: 104527 + /* 15747 */ MCD_OPC_Decode, + 137, + 9, + 111, // Opcode: BRKPB_PPzPP + /* 15751 */ MCD_OPC_FilterValue, + 5, + 208, + 1, + 0, // Skip to: 16220 + /* 15756 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 15759 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 15839 + /* 15764 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15767 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 15803 + /* 15772 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 15775 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15789 + /* 15780 */ MCD_OPC_CheckPredicate, + 3, + 166, + 90, + 1, // Skip to: 104527 + /* 15785 */ MCD_OPC_Decode, + 209, + 10, + 110, // Opcode: CMPGE_PPzZI_H + /* 15789 */ MCD_OPC_FilterValue, + 1, + 157, + 90, + 1, // Skip to: 104527 + /* 15794 */ MCD_OPC_CheckPredicate, + 3, + 152, + 90, + 1, // Skip to: 104527 + /* 15799 */ MCD_OPC_Decode, + 146, + 11, + 110, // Opcode: CMPLT_PPzZI_H + /* 15803 */ MCD_OPC_FilterValue, + 1, + 143, + 90, + 1, // Skip to: 104527 + /* 15808 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 15811 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15825 + /* 15816 */ MCD_OPC_CheckPredicate, + 3, + 130, + 90, + 1, // Skip to: 104527 + /* 15821 */ MCD_OPC_Decode, + 220, + 10, + 110, // Opcode: CMPGT_PPzZI_H + /* 15825 */ MCD_OPC_FilterValue, + 1, + 121, + 90, + 1, // Skip to: 104527 + /* 15830 */ MCD_OPC_CheckPredicate, + 3, + 116, + 90, + 1, // Skip to: 104527 + /* 15835 */ MCD_OPC_Decode, + 253, + 10, + 110, // Opcode: CMPLE_PPzZI_H + /* 15839 */ MCD_OPC_FilterValue, + 1, + 118, + 0, + 0, // Skip to: 15962 + /* 15844 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15847 */ MCD_OPC_FilterValue, + 0, + 82, + 0, + 0, // Skip to: 15934 + /* 15852 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 15855 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 15913 + /* 15860 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 15863 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15877 + /* 15868 */ MCD_OPC_CheckPredicate, + 3, + 78, + 90, + 1, // Skip to: 104527 + /* 15873 */ MCD_OPC_Decode, + 248, + 7, + 111, // Opcode: ANDS_PPzPP + /* 15877 */ MCD_OPC_FilterValue, + 1, + 69, + 90, + 1, // Skip to: 104527 + /* 15882 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 15885 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15899 + /* 15890 */ MCD_OPC_CheckPredicate, + 3, + 56, + 90, + 1, // Skip to: 104527 + /* 15895 */ MCD_OPC_Decode, + 254, + 8, + 112, // Opcode: BRKAS_PPzP + /* 15899 */ MCD_OPC_FilterValue, + 8, + 47, + 90, + 1, // Skip to: 104527 + /* 15904 */ MCD_OPC_CheckPredicate, + 3, + 42, + 90, + 1, // Skip to: 104527 + /* 15909 */ MCD_OPC_Decode, + 132, + 9, + 113, // Opcode: BRKNS_PPzP + /* 15913 */ MCD_OPC_FilterValue, + 1, + 33, + 90, + 1, // Skip to: 104527 + /* 15918 */ MCD_OPC_CheckPredicate, + 3, + 28, + 90, + 1, // Skip to: 104527 + /* 15923 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 21, + 90, + 1, // Skip to: 104527 + /* 15930 */ MCD_OPC_Decode, + 159, + 12, + 111, // Opcode: EORS_PPzPP + /* 15934 */ MCD_OPC_FilterValue, + 1, + 12, + 90, + 1, // Skip to: 104527 + /* 15939 */ MCD_OPC_CheckPredicate, + 3, + 7, + 90, + 1, // Skip to: 104527 + /* 15944 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 0, + 90, + 1, // Skip to: 104527 + /* 15951 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 249, + 89, + 1, // Skip to: 104527 + /* 15958 */ MCD_OPC_Decode, + 221, + 8, + 111, // Opcode: BICS_PPzPP + /* 15962 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 16012 + /* 15967 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 15970 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 15991 + /* 15975 */ MCD_OPC_CheckPredicate, + 3, + 227, + 89, + 1, // Skip to: 104527 + /* 15980 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 220, + 89, + 1, // Skip to: 104527 + /* 15987 */ MCD_OPC_Decode, + 198, + 10, + 110, // Opcode: CMPEQ_PPzZI_H + /* 15991 */ MCD_OPC_FilterValue, + 1, + 211, + 89, + 1, // Skip to: 104527 + /* 15996 */ MCD_OPC_CheckPredicate, + 3, + 206, + 89, + 1, // Skip to: 104527 + /* 16001 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 199, + 89, + 1, // Skip to: 104527 + /* 16008 */ MCD_OPC_Decode, + 153, + 11, + 110, // Opcode: CMPNE_PPzZI_H + /* 16012 */ MCD_OPC_FilterValue, + 3, + 190, + 89, + 1, // Skip to: 104527 + /* 16017 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16020 */ MCD_OPC_FilterValue, + 0, + 167, + 0, + 0, // Skip to: 16192 + /* 16025 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 16028 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 16049 + /* 16033 */ MCD_OPC_CheckPredicate, + 3, + 169, + 89, + 1, // Skip to: 104527 + /* 16038 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 162, + 89, + 1, // Skip to: 104527 + /* 16045 */ MCD_OPC_Decode, + 134, + 9, + 111, // Opcode: BRKPAS_PPzPP + /* 16049 */ MCD_OPC_FilterValue, + 1, + 153, + 89, + 1, // Skip to: 104527 + /* 16054 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 16057 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 16085 + /* 16062 */ MCD_OPC_CheckPredicate, + 3, + 140, + 89, + 1, // Skip to: 104527 + /* 16067 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 133, + 89, + 1, // Skip to: 104527 + /* 16074 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 126, + 89, + 1, // Skip to: 104527 + /* 16081 */ MCD_OPC_Decode, + 247, + 28, + 118, // Opcode: PTEST_PP + /* 16085 */ MCD_OPC_FilterValue, + 8, + 59, + 0, + 0, // Skip to: 16149 + /* 16090 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 16093 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 16114 + /* 16098 */ MCD_OPC_CheckPredicate, + 3, + 104, + 89, + 1, // Skip to: 104527 + /* 16103 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 97, + 89, + 1, // Skip to: 104527 + /* 16110 */ MCD_OPC_Decode, + 184, + 28, + 115, // Opcode: PFIRST_B + /* 16114 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 16128 + /* 16119 */ MCD_OPC_CheckPredicate, + 3, + 83, + 89, + 1, // Skip to: 104527 + /* 16124 */ MCD_OPC_Decode, + 254, + 28, + 116, // Opcode: PTRUE_H + /* 16128 */ MCD_OPC_FilterValue, + 12, + 74, + 89, + 1, // Skip to: 104527 + /* 16133 */ MCD_OPC_CheckPredicate, + 6, + 69, + 89, + 1, // Skip to: 104527 + /* 16138 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 62, + 89, + 1, // Skip to: 104527 + /* 16145 */ MCD_OPC_Decode, + 152, + 29, + 76, // Opcode: RDFFRS_PPz + /* 16149 */ MCD_OPC_FilterValue, + 9, + 53, + 89, + 1, // Skip to: 104527 + /* 16154 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 16157 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 16178 + /* 16162 */ MCD_OPC_CheckPredicate, + 3, + 40, + 89, + 1, // Skip to: 104527 + /* 16167 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 33, + 89, + 1, // Skip to: 104527 + /* 16174 */ MCD_OPC_Decode, + 200, + 28, + 115, // Opcode: PNEXT_H + /* 16178 */ MCD_OPC_FilterValue, + 8, + 24, + 89, + 1, // Skip to: 104527 + /* 16183 */ MCD_OPC_CheckPredicate, + 3, + 19, + 89, + 1, // Skip to: 104527 + /* 16188 */ MCD_OPC_Decode, + 250, + 28, + 116, // Opcode: PTRUES_H + /* 16192 */ MCD_OPC_FilterValue, + 1, + 10, + 89, + 1, // Skip to: 104527 + /* 16197 */ MCD_OPC_CheckPredicate, + 3, + 5, + 89, + 1, // Skip to: 104527 + /* 16202 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 254, + 88, + 1, // Skip to: 104527 + /* 16209 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 247, + 88, + 1, // Skip to: 104527 + /* 16216 */ MCD_OPC_Decode, + 136, + 9, + 111, // Opcode: BRKPBS_PPzPP + /* 16220 */ MCD_OPC_FilterValue, + 6, + 122, + 1, + 0, // Skip to: 16603 + /* 16225 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 16228 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 16308 + /* 16233 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16236 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 16272 + /* 16241 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 16244 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 16258 + /* 16249 */ MCD_OPC_CheckPredicate, + 3, + 209, + 88, + 1, // Skip to: 104527 + /* 16254 */ MCD_OPC_Decode, + 210, + 10, + 110, // Opcode: CMPGE_PPzZI_S + /* 16258 */ MCD_OPC_FilterValue, + 1, + 200, + 88, + 1, // Skip to: 104527 + /* 16263 */ MCD_OPC_CheckPredicate, + 3, + 195, + 88, + 1, // Skip to: 104527 + /* 16268 */ MCD_OPC_Decode, + 147, + 11, + 110, // Opcode: CMPLT_PPzZI_S + /* 16272 */ MCD_OPC_FilterValue, + 1, + 186, + 88, + 1, // Skip to: 104527 + /* 16277 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 16280 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 16294 + /* 16285 */ MCD_OPC_CheckPredicate, + 3, + 173, + 88, + 1, // Skip to: 104527 + /* 16290 */ MCD_OPC_Decode, + 221, + 10, + 110, // Opcode: CMPGT_PPzZI_S + /* 16294 */ MCD_OPC_FilterValue, + 1, + 164, + 88, + 1, // Skip to: 104527 + /* 16299 */ MCD_OPC_CheckPredicate, + 3, + 159, + 88, + 1, // Skip to: 104527 + /* 16304 */ MCD_OPC_Decode, + 254, + 10, + 110, // Opcode: CMPLE_PPzZI_S + /* 16308 */ MCD_OPC_FilterValue, + 1, + 147, + 0, + 0, // Skip to: 16460 + /* 16313 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16316 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 16388 + /* 16321 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 16324 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 16367 + /* 16329 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 16332 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 16346 + /* 16337 */ MCD_OPC_CheckPredicate, + 3, + 121, + 88, + 1, // Skip to: 104527 + /* 16342 */ MCD_OPC_Decode, + 151, + 28, + 111, // Opcode: ORR_PPzPP + /* 16346 */ MCD_OPC_FilterValue, + 1, + 112, + 88, + 1, // Skip to: 104527 + /* 16351 */ MCD_OPC_CheckPredicate, + 3, + 107, + 88, + 1, // Skip to: 104527 + /* 16356 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 100, + 88, + 1, // Skip to: 104527 + /* 16363 */ MCD_OPC_Decode, + 131, + 9, + 112, // Opcode: BRKB_PPzP + /* 16367 */ MCD_OPC_FilterValue, + 1, + 91, + 88, + 1, // Skip to: 104527 + /* 16372 */ MCD_OPC_CheckPredicate, + 3, + 86, + 88, + 1, // Skip to: 104527 + /* 16377 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 79, + 88, + 1, // Skip to: 104527 + /* 16384 */ MCD_OPC_Decode, + 133, + 28, + 111, // Opcode: NOR_PPzPP + /* 16388 */ MCD_OPC_FilterValue, + 1, + 70, + 88, + 1, // Skip to: 104527 + /* 16393 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 16396 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 16439 + /* 16401 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 16404 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 16418 + /* 16409 */ MCD_OPC_CheckPredicate, + 3, + 49, + 88, + 1, // Skip to: 104527 + /* 16414 */ MCD_OPC_Decode, + 143, + 28, + 111, // Opcode: ORN_PPzPP + /* 16418 */ MCD_OPC_FilterValue, + 1, + 40, + 88, + 1, // Skip to: 104527 + /* 16423 */ MCD_OPC_CheckPredicate, + 3, + 35, + 88, + 1, // Skip to: 104527 + /* 16428 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 28, + 88, + 1, // Skip to: 104527 + /* 16435 */ MCD_OPC_Decode, + 130, + 9, + 114, // Opcode: BRKB_PPmP + /* 16439 */ MCD_OPC_FilterValue, + 1, + 19, + 88, + 1, // Skip to: 104527 + /* 16444 */ MCD_OPC_CheckPredicate, + 3, + 14, + 88, + 1, // Skip to: 104527 + /* 16449 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 7, + 88, + 1, // Skip to: 104527 + /* 16456 */ MCD_OPC_Decode, + 244, + 27, + 111, // Opcode: NAND_PPzPP + /* 16460 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 16510 + /* 16465 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16468 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 16489 + /* 16473 */ MCD_OPC_CheckPredicate, + 3, + 241, + 87, + 1, // Skip to: 104527 + /* 16478 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 234, + 87, + 1, // Skip to: 104527 + /* 16485 */ MCD_OPC_Decode, + 199, + 10, + 110, // Opcode: CMPEQ_PPzZI_S + /* 16489 */ MCD_OPC_FilterValue, + 1, + 225, + 87, + 1, // Skip to: 104527 + /* 16494 */ MCD_OPC_CheckPredicate, + 3, + 220, + 87, + 1, // Skip to: 104527 + /* 16499 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 213, + 87, + 1, // Skip to: 104527 + /* 16506 */ MCD_OPC_Decode, + 154, + 11, + 110, // Opcode: CMPNE_PPzZI_S + /* 16510 */ MCD_OPC_FilterValue, + 3, + 204, + 87, + 1, // Skip to: 104527 + /* 16515 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 16518 */ MCD_OPC_FilterValue, + 1, + 30, + 0, + 0, // Skip to: 16553 + /* 16523 */ MCD_OPC_CheckPredicate, + 3, + 191, + 87, + 1, // Skip to: 104527 + /* 16528 */ MCD_OPC_CheckField, + 16, + 5, + 25, + 184, + 87, + 1, // Skip to: 104527 + /* 16535 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 177, + 87, + 1, // Skip to: 104527 + /* 16542 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 170, + 87, + 1, // Skip to: 104527 + /* 16549 */ MCD_OPC_Decode, + 201, + 28, + 115, // Opcode: PNEXT_S + /* 16553 */ MCD_OPC_FilterValue, + 8, + 161, + 87, + 1, // Skip to: 104527 + /* 16558 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 16561 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 16582 + /* 16566 */ MCD_OPC_CheckPredicate, + 3, + 148, + 87, + 1, // Skip to: 104527 + /* 16571 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 141, + 87, + 1, // Skip to: 104527 + /* 16578 */ MCD_OPC_Decode, + 255, + 28, + 116, // Opcode: PTRUE_S + /* 16582 */ MCD_OPC_FilterValue, + 25, + 132, + 87, + 1, // Skip to: 104527 + /* 16587 */ MCD_OPC_CheckPredicate, + 3, + 127, + 87, + 1, // Skip to: 104527 + /* 16592 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 120, + 87, + 1, // Skip to: 104527 + /* 16599 */ MCD_OPC_Decode, + 251, + 28, + 116, // Opcode: PTRUES_S + /* 16603 */ MCD_OPC_FilterValue, + 7, + 111, + 87, + 1, // Skip to: 104527 + /* 16608 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 16611 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 16691 + /* 16616 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16619 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 16655 + /* 16624 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 16627 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 16641 + /* 16632 */ MCD_OPC_CheckPredicate, + 3, + 82, + 87, + 1, // Skip to: 104527 + /* 16637 */ MCD_OPC_Decode, + 208, + 10, + 110, // Opcode: CMPGE_PPzZI_D + /* 16641 */ MCD_OPC_FilterValue, + 1, + 73, + 87, + 1, // Skip to: 104527 + /* 16646 */ MCD_OPC_CheckPredicate, + 3, + 68, + 87, + 1, // Skip to: 104527 + /* 16651 */ MCD_OPC_Decode, + 145, + 11, + 110, // Opcode: CMPLT_PPzZI_D + /* 16655 */ MCD_OPC_FilterValue, + 1, + 59, + 87, + 1, // Skip to: 104527 + /* 16660 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 16663 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 16677 + /* 16668 */ MCD_OPC_CheckPredicate, + 3, + 46, + 87, + 1, // Skip to: 104527 + /* 16673 */ MCD_OPC_Decode, + 219, + 10, + 110, // Opcode: CMPGT_PPzZI_D + /* 16677 */ MCD_OPC_FilterValue, + 1, + 37, + 87, + 1, // Skip to: 104527 + /* 16682 */ MCD_OPC_CheckPredicate, + 3, + 32, + 87, + 1, // Skip to: 104527 + /* 16687 */ MCD_OPC_Decode, + 252, + 10, + 110, // Opcode: CMPLE_PPzZI_D + /* 16691 */ MCD_OPC_FilterValue, + 1, + 125, + 0, + 0, // Skip to: 16821 + /* 16696 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16699 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 16771 + /* 16704 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 16707 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 16750 + /* 16712 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 16715 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 16729 + /* 16720 */ MCD_OPC_CheckPredicate, + 3, + 250, + 86, + 1, // Skip to: 104527 + /* 16725 */ MCD_OPC_Decode, + 146, + 28, + 111, // Opcode: ORRS_PPzPP + /* 16729 */ MCD_OPC_FilterValue, + 1, + 241, + 86, + 1, // Skip to: 104527 + /* 16734 */ MCD_OPC_CheckPredicate, + 3, + 236, + 86, + 1, // Skip to: 104527 + /* 16739 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 229, + 86, + 1, // Skip to: 104527 + /* 16746 */ MCD_OPC_Decode, + 129, + 9, + 112, // Opcode: BRKBS_PPzP + /* 16750 */ MCD_OPC_FilterValue, + 1, + 220, + 86, + 1, // Skip to: 104527 + /* 16755 */ MCD_OPC_CheckPredicate, + 3, + 215, + 86, + 1, // Skip to: 104527 + /* 16760 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 208, + 86, + 1, // Skip to: 104527 + /* 16767 */ MCD_OPC_Decode, + 132, + 28, + 111, // Opcode: NORS_PPzPP + /* 16771 */ MCD_OPC_FilterValue, + 1, + 199, + 86, + 1, // Skip to: 104527 + /* 16776 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 16779 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 16800 + /* 16784 */ MCD_OPC_CheckPredicate, + 3, + 186, + 86, + 1, // Skip to: 104527 + /* 16789 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 179, + 86, + 1, // Skip to: 104527 + /* 16796 */ MCD_OPC_Decode, + 140, + 28, + 111, // Opcode: ORNS_PPzPP + /* 16800 */ MCD_OPC_FilterValue, + 1, + 170, + 86, + 1, // Skip to: 104527 + /* 16805 */ MCD_OPC_CheckPredicate, + 3, + 165, + 86, + 1, // Skip to: 104527 + /* 16810 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 158, + 86, + 1, // Skip to: 104527 + /* 16817 */ MCD_OPC_Decode, + 243, + 27, + 111, // Opcode: NANDS_PPzPP + /* 16821 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 16871 + /* 16826 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16829 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 16850 + /* 16834 */ MCD_OPC_CheckPredicate, + 3, + 136, + 86, + 1, // Skip to: 104527 + /* 16839 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 129, + 86, + 1, // Skip to: 104527 + /* 16846 */ MCD_OPC_Decode, + 197, + 10, + 110, // Opcode: CMPEQ_PPzZI_D + /* 16850 */ MCD_OPC_FilterValue, + 1, + 120, + 86, + 1, // Skip to: 104527 + /* 16855 */ MCD_OPC_CheckPredicate, + 3, + 115, + 86, + 1, // Skip to: 104527 + /* 16860 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 108, + 86, + 1, // Skip to: 104527 + /* 16867 */ MCD_OPC_Decode, + 152, + 11, + 110, // Opcode: CMPNE_PPzZI_D + /* 16871 */ MCD_OPC_FilterValue, + 3, + 99, + 86, + 1, // Skip to: 104527 + /* 16876 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 16879 */ MCD_OPC_FilterValue, + 1, + 30, + 0, + 0, // Skip to: 16914 + /* 16884 */ MCD_OPC_CheckPredicate, + 3, + 86, + 86, + 1, // Skip to: 104527 + /* 16889 */ MCD_OPC_CheckField, + 16, + 5, + 25, + 79, + 86, + 1, // Skip to: 104527 + /* 16896 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 72, + 86, + 1, // Skip to: 104527 + /* 16903 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 65, + 86, + 1, // Skip to: 104527 + /* 16910 */ MCD_OPC_Decode, + 199, + 28, + 115, // Opcode: PNEXT_D + /* 16914 */ MCD_OPC_FilterValue, + 8, + 56, + 86, + 1, // Skip to: 104527 + /* 16919 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 16922 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 16943 + /* 16927 */ MCD_OPC_CheckPredicate, + 3, + 43, + 86, + 1, // Skip to: 104527 + /* 16932 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 36, + 86, + 1, // Skip to: 104527 + /* 16939 */ MCD_OPC_Decode, + 253, + 28, + 116, // Opcode: PTRUE_D + /* 16943 */ MCD_OPC_FilterValue, + 25, + 27, + 86, + 1, // Skip to: 104527 + /* 16948 */ MCD_OPC_CheckPredicate, + 3, + 22, + 86, + 1, // Skip to: 104527 + /* 16953 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 15, + 86, + 1, // Skip to: 104527 + /* 16960 */ MCD_OPC_Decode, + 249, + 28, + 116, // Opcode: PTRUES_D + /* 16964 */ MCD_OPC_FilterValue, + 1, + 6, + 86, + 1, // Skip to: 104527 + /* 16969 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 16972 */ MCD_OPC_FilterValue, + 0, + 67, + 1, + 0, // Skip to: 17300 + /* 16977 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 16980 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17060 + /* 16985 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16988 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 17024 + /* 16993 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 16996 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17010 + /* 17001 */ MCD_OPC_CheckPredicate, + 3, + 225, + 85, + 1, // Skip to: 104527 + /* 17006 */ MCD_OPC_Decode, + 240, + 10, + 119, // Opcode: CMPHS_PPzZI_B + /* 17010 */ MCD_OPC_FilterValue, + 1, + 216, + 85, + 1, // Skip to: 104527 + /* 17015 */ MCD_OPC_CheckPredicate, + 3, + 211, + 85, + 1, // Skip to: 104527 + /* 17020 */ MCD_OPC_Decode, + 130, + 11, + 119, // Opcode: CMPLO_PPzZI_B + /* 17024 */ MCD_OPC_FilterValue, + 1, + 202, + 85, + 1, // Skip to: 104527 + /* 17029 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 17032 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17046 + /* 17037 */ MCD_OPC_CheckPredicate, + 3, + 189, + 85, + 1, // Skip to: 104527 + /* 17042 */ MCD_OPC_Decode, + 229, + 10, + 119, // Opcode: CMPHI_PPzZI_B + /* 17046 */ MCD_OPC_FilterValue, + 1, + 180, + 85, + 1, // Skip to: 104527 + /* 17051 */ MCD_OPC_CheckPredicate, + 3, + 175, + 85, + 1, // Skip to: 104527 + /* 17056 */ MCD_OPC_Decode, + 137, + 11, + 119, // Opcode: CMPLS_PPzZI_B + /* 17060 */ MCD_OPC_FilterValue, + 1, + 75, + 0, + 0, // Skip to: 17140 + /* 17065 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17068 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 17104 + /* 17073 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 17076 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17090 + /* 17081 */ MCD_OPC_CheckPredicate, + 3, + 145, + 85, + 1, // Skip to: 104527 + /* 17086 */ MCD_OPC_Decode, + 242, + 10, + 119, // Opcode: CMPHS_PPzZI_H + /* 17090 */ MCD_OPC_FilterValue, + 1, + 136, + 85, + 1, // Skip to: 104527 + /* 17095 */ MCD_OPC_CheckPredicate, + 3, + 131, + 85, + 1, // Skip to: 104527 + /* 17100 */ MCD_OPC_Decode, + 132, + 11, + 119, // Opcode: CMPLO_PPzZI_H + /* 17104 */ MCD_OPC_FilterValue, + 1, + 122, + 85, + 1, // Skip to: 104527 + /* 17109 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 17112 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17126 + /* 17117 */ MCD_OPC_CheckPredicate, + 3, + 109, + 85, + 1, // Skip to: 104527 + /* 17122 */ MCD_OPC_Decode, + 231, + 10, + 119, // Opcode: CMPHI_PPzZI_H + /* 17126 */ MCD_OPC_FilterValue, + 1, + 100, + 85, + 1, // Skip to: 104527 + /* 17131 */ MCD_OPC_CheckPredicate, + 3, + 95, + 85, + 1, // Skip to: 104527 + /* 17136 */ MCD_OPC_Decode, + 139, + 11, + 119, // Opcode: CMPLS_PPzZI_H + /* 17140 */ MCD_OPC_FilterValue, + 2, + 75, + 0, + 0, // Skip to: 17220 + /* 17145 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17148 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 17184 + /* 17153 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 17156 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17170 + /* 17161 */ MCD_OPC_CheckPredicate, + 3, + 65, + 85, + 1, // Skip to: 104527 + /* 17166 */ MCD_OPC_Decode, + 243, + 10, + 119, // Opcode: CMPHS_PPzZI_S + /* 17170 */ MCD_OPC_FilterValue, + 1, + 56, + 85, + 1, // Skip to: 104527 + /* 17175 */ MCD_OPC_CheckPredicate, + 3, + 51, + 85, + 1, // Skip to: 104527 + /* 17180 */ MCD_OPC_Decode, + 133, + 11, + 119, // Opcode: CMPLO_PPzZI_S + /* 17184 */ MCD_OPC_FilterValue, + 1, + 42, + 85, + 1, // Skip to: 104527 + /* 17189 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 17192 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17206 + /* 17197 */ MCD_OPC_CheckPredicate, + 3, + 29, + 85, + 1, // Skip to: 104527 + /* 17202 */ MCD_OPC_Decode, + 232, + 10, + 119, // Opcode: CMPHI_PPzZI_S + /* 17206 */ MCD_OPC_FilterValue, + 1, + 20, + 85, + 1, // Skip to: 104527 + /* 17211 */ MCD_OPC_CheckPredicate, + 3, + 15, + 85, + 1, // Skip to: 104527 + /* 17216 */ MCD_OPC_Decode, + 140, + 11, + 119, // Opcode: CMPLS_PPzZI_S + /* 17220 */ MCD_OPC_FilterValue, + 3, + 6, + 85, + 1, // Skip to: 104527 + /* 17225 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17228 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 17264 + /* 17233 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 17236 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17250 + /* 17241 */ MCD_OPC_CheckPredicate, + 3, + 241, + 84, + 1, // Skip to: 104527 + /* 17246 */ MCD_OPC_Decode, + 241, + 10, + 119, // Opcode: CMPHS_PPzZI_D + /* 17250 */ MCD_OPC_FilterValue, + 1, + 232, + 84, + 1, // Skip to: 104527 + /* 17255 */ MCD_OPC_CheckPredicate, + 3, + 227, + 84, + 1, // Skip to: 104527 + /* 17260 */ MCD_OPC_Decode, + 131, + 11, + 119, // Opcode: CMPLO_PPzZI_D + /* 17264 */ MCD_OPC_FilterValue, + 1, + 218, + 84, + 1, // Skip to: 104527 + /* 17269 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 17272 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17286 + /* 17277 */ MCD_OPC_CheckPredicate, + 3, + 205, + 84, + 1, // Skip to: 104527 + /* 17282 */ MCD_OPC_Decode, + 230, + 10, + 119, // Opcode: CMPHI_PPzZI_D + /* 17286 */ MCD_OPC_FilterValue, + 1, + 196, + 84, + 1, // Skip to: 104527 + /* 17291 */ MCD_OPC_CheckPredicate, + 3, + 191, + 84, + 1, // Skip to: 104527 + /* 17296 */ MCD_OPC_Decode, + 138, + 11, + 119, // Opcode: CMPLS_PPzZI_D + /* 17300 */ MCD_OPC_FilterValue, + 1, + 182, + 84, + 1, // Skip to: 104527 + /* 17305 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 17308 */ MCD_OPC_FilterValue, + 0, + 171, + 5, + 0, // Skip to: 18764 + /* 17313 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 17316 */ MCD_OPC_FilterValue, + 0, + 147, + 0, + 0, // Skip to: 17468 + /* 17321 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 17324 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 17360 + /* 17329 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17332 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17346 + /* 17337 */ MCD_OPC_CheckPredicate, + 4, + 145, + 84, + 1, // Skip to: 104527 + /* 17342 */ MCD_OPC_Decode, + 158, + 47, + 120, // Opcode: WHILEGE_PWW_B + /* 17346 */ MCD_OPC_FilterValue, + 1, + 136, + 84, + 1, // Skip to: 104527 + /* 17351 */ MCD_OPC_CheckPredicate, + 4, + 131, + 84, + 1, // Skip to: 104527 + /* 17356 */ MCD_OPC_Decode, + 166, + 47, + 120, // Opcode: WHILEGT_PWW_B + /* 17360 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 17396 + /* 17365 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17368 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17382 + /* 17373 */ MCD_OPC_CheckPredicate, + 4, + 109, + 84, + 1, // Skip to: 104527 + /* 17378 */ MCD_OPC_Decode, + 160, + 47, + 120, // Opcode: WHILEGE_PWW_H + /* 17382 */ MCD_OPC_FilterValue, + 1, + 100, + 84, + 1, // Skip to: 104527 + /* 17387 */ MCD_OPC_CheckPredicate, + 4, + 95, + 84, + 1, // Skip to: 104527 + /* 17392 */ MCD_OPC_Decode, + 168, + 47, + 120, // Opcode: WHILEGT_PWW_H + /* 17396 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 17432 + /* 17401 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17404 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17418 + /* 17409 */ MCD_OPC_CheckPredicate, + 4, + 73, + 84, + 1, // Skip to: 104527 + /* 17414 */ MCD_OPC_Decode, + 161, + 47, + 120, // Opcode: WHILEGE_PWW_S + /* 17418 */ MCD_OPC_FilterValue, + 1, + 64, + 84, + 1, // Skip to: 104527 + /* 17423 */ MCD_OPC_CheckPredicate, + 4, + 59, + 84, + 1, // Skip to: 104527 + /* 17428 */ MCD_OPC_Decode, + 169, + 47, + 120, // Opcode: WHILEGT_PWW_S + /* 17432 */ MCD_OPC_FilterValue, + 3, + 50, + 84, + 1, // Skip to: 104527 + /* 17437 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17440 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17454 + /* 17445 */ MCD_OPC_CheckPredicate, + 4, + 37, + 84, + 1, // Skip to: 104527 + /* 17450 */ MCD_OPC_Decode, + 159, + 47, + 120, // Opcode: WHILEGE_PWW_D + /* 17454 */ MCD_OPC_FilterValue, + 1, + 28, + 84, + 1, // Skip to: 104527 + /* 17459 */ MCD_OPC_CheckPredicate, + 4, + 23, + 84, + 1, // Skip to: 104527 + /* 17464 */ MCD_OPC_Decode, + 167, + 47, + 120, // Opcode: WHILEGT_PWW_D + /* 17468 */ MCD_OPC_FilterValue, + 1, + 147, + 0, + 0, // Skip to: 17620 + /* 17473 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 17476 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 17512 + /* 17481 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17484 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17498 + /* 17489 */ MCD_OPC_CheckPredicate, + 3, + 249, + 83, + 1, // Skip to: 104527 + /* 17494 */ MCD_OPC_Decode, + 214, + 47, + 120, // Opcode: WHILELT_PWW_B + /* 17498 */ MCD_OPC_FilterValue, + 1, + 240, + 83, + 1, // Skip to: 104527 + /* 17503 */ MCD_OPC_CheckPredicate, + 3, + 235, + 83, + 1, // Skip to: 104527 + /* 17508 */ MCD_OPC_Decode, + 190, + 47, + 120, // Opcode: WHILELE_PWW_B + /* 17512 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 17548 + /* 17517 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17520 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17534 + /* 17525 */ MCD_OPC_CheckPredicate, + 3, + 213, + 83, + 1, // Skip to: 104527 + /* 17530 */ MCD_OPC_Decode, + 216, + 47, + 120, // Opcode: WHILELT_PWW_H + /* 17534 */ MCD_OPC_FilterValue, + 1, + 204, + 83, + 1, // Skip to: 104527 + /* 17539 */ MCD_OPC_CheckPredicate, + 3, + 199, + 83, + 1, // Skip to: 104527 + /* 17544 */ MCD_OPC_Decode, + 192, + 47, + 120, // Opcode: WHILELE_PWW_H + /* 17548 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 17584 + /* 17553 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17556 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17570 + /* 17561 */ MCD_OPC_CheckPredicate, + 3, + 177, + 83, + 1, // Skip to: 104527 + /* 17566 */ MCD_OPC_Decode, + 217, + 47, + 120, // Opcode: WHILELT_PWW_S + /* 17570 */ MCD_OPC_FilterValue, + 1, + 168, + 83, + 1, // Skip to: 104527 + /* 17575 */ MCD_OPC_CheckPredicate, + 3, + 163, + 83, + 1, // Skip to: 104527 + /* 17580 */ MCD_OPC_Decode, + 193, + 47, + 120, // Opcode: WHILELE_PWW_S + /* 17584 */ MCD_OPC_FilterValue, + 3, + 154, + 83, + 1, // Skip to: 104527 + /* 17589 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17592 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17606 + /* 17597 */ MCD_OPC_CheckPredicate, + 3, + 141, + 83, + 1, // Skip to: 104527 + /* 17602 */ MCD_OPC_Decode, + 215, + 47, + 120, // Opcode: WHILELT_PWW_D + /* 17606 */ MCD_OPC_FilterValue, + 1, + 132, + 83, + 1, // Skip to: 104527 + /* 17611 */ MCD_OPC_CheckPredicate, + 3, + 127, + 83, + 1, // Skip to: 104527 + /* 17616 */ MCD_OPC_Decode, + 191, + 47, + 120, // Opcode: WHILELE_PWW_D + /* 17620 */ MCD_OPC_FilterValue, + 2, + 147, + 0, + 0, // Skip to: 17772 + /* 17625 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 17628 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 17664 + /* 17633 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17636 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17650 + /* 17641 */ MCD_OPC_CheckPredicate, + 4, + 97, + 83, + 1, // Skip to: 104527 + /* 17646 */ MCD_OPC_Decode, + 182, + 47, + 120, // Opcode: WHILEHS_PWW_B + /* 17650 */ MCD_OPC_FilterValue, + 1, + 88, + 83, + 1, // Skip to: 104527 + /* 17655 */ MCD_OPC_CheckPredicate, + 4, + 83, + 83, + 1, // Skip to: 104527 + /* 17660 */ MCD_OPC_Decode, + 174, + 47, + 120, // Opcode: WHILEHI_PWW_B + /* 17664 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 17700 + /* 17669 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17672 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17686 + /* 17677 */ MCD_OPC_CheckPredicate, + 4, + 61, + 83, + 1, // Skip to: 104527 + /* 17682 */ MCD_OPC_Decode, + 184, + 47, + 120, // Opcode: WHILEHS_PWW_H + /* 17686 */ MCD_OPC_FilterValue, + 1, + 52, + 83, + 1, // Skip to: 104527 + /* 17691 */ MCD_OPC_CheckPredicate, + 4, + 47, + 83, + 1, // Skip to: 104527 + /* 17696 */ MCD_OPC_Decode, + 176, + 47, + 120, // Opcode: WHILEHI_PWW_H + /* 17700 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 17736 + /* 17705 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17708 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17722 + /* 17713 */ MCD_OPC_CheckPredicate, + 4, + 25, + 83, + 1, // Skip to: 104527 + /* 17718 */ MCD_OPC_Decode, + 185, + 47, + 120, // Opcode: WHILEHS_PWW_S + /* 17722 */ MCD_OPC_FilterValue, + 1, + 16, + 83, + 1, // Skip to: 104527 + /* 17727 */ MCD_OPC_CheckPredicate, + 4, + 11, + 83, + 1, // Skip to: 104527 + /* 17732 */ MCD_OPC_Decode, + 177, + 47, + 120, // Opcode: WHILEHI_PWW_S + /* 17736 */ MCD_OPC_FilterValue, + 3, + 2, + 83, + 1, // Skip to: 104527 + /* 17741 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17744 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17758 + /* 17749 */ MCD_OPC_CheckPredicate, + 4, + 245, + 82, + 1, // Skip to: 104527 + /* 17754 */ MCD_OPC_Decode, + 183, + 47, + 120, // Opcode: WHILEHS_PWW_D + /* 17758 */ MCD_OPC_FilterValue, + 1, + 236, + 82, + 1, // Skip to: 104527 + /* 17763 */ MCD_OPC_CheckPredicate, + 4, + 231, + 82, + 1, // Skip to: 104527 + /* 17768 */ MCD_OPC_Decode, + 175, + 47, + 120, // Opcode: WHILEHI_PWW_D + /* 17772 */ MCD_OPC_FilterValue, + 3, + 147, + 0, + 0, // Skip to: 17924 + /* 17777 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 17780 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 17816 + /* 17785 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17788 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17802 + /* 17793 */ MCD_OPC_CheckPredicate, + 3, + 201, + 82, + 1, // Skip to: 104527 + /* 17798 */ MCD_OPC_Decode, + 198, + 47, + 120, // Opcode: WHILELO_PWW_B + /* 17802 */ MCD_OPC_FilterValue, + 1, + 192, + 82, + 1, // Skip to: 104527 + /* 17807 */ MCD_OPC_CheckPredicate, + 3, + 187, + 82, + 1, // Skip to: 104527 + /* 17812 */ MCD_OPC_Decode, + 206, + 47, + 120, // Opcode: WHILELS_PWW_B + /* 17816 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 17852 + /* 17821 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17824 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17838 + /* 17829 */ MCD_OPC_CheckPredicate, + 3, + 165, + 82, + 1, // Skip to: 104527 + /* 17834 */ MCD_OPC_Decode, + 200, + 47, + 120, // Opcode: WHILELO_PWW_H + /* 17838 */ MCD_OPC_FilterValue, + 1, + 156, + 82, + 1, // Skip to: 104527 + /* 17843 */ MCD_OPC_CheckPredicate, + 3, + 151, + 82, + 1, // Skip to: 104527 + /* 17848 */ MCD_OPC_Decode, + 208, + 47, + 120, // Opcode: WHILELS_PWW_H + /* 17852 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 17888 + /* 17857 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17860 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17874 + /* 17865 */ MCD_OPC_CheckPredicate, + 3, + 129, + 82, + 1, // Skip to: 104527 + /* 17870 */ MCD_OPC_Decode, + 201, + 47, + 120, // Opcode: WHILELO_PWW_S + /* 17874 */ MCD_OPC_FilterValue, + 1, + 120, + 82, + 1, // Skip to: 104527 + /* 17879 */ MCD_OPC_CheckPredicate, + 3, + 115, + 82, + 1, // Skip to: 104527 + /* 17884 */ MCD_OPC_Decode, + 209, + 47, + 120, // Opcode: WHILELS_PWW_S + /* 17888 */ MCD_OPC_FilterValue, + 3, + 106, + 82, + 1, // Skip to: 104527 + /* 17893 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17896 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17910 + /* 17901 */ MCD_OPC_CheckPredicate, + 3, + 93, + 82, + 1, // Skip to: 104527 + /* 17906 */ MCD_OPC_Decode, + 199, + 47, + 120, // Opcode: WHILELO_PWW_D + /* 17910 */ MCD_OPC_FilterValue, + 1, + 84, + 82, + 1, // Skip to: 104527 + /* 17915 */ MCD_OPC_CheckPredicate, + 3, + 79, + 82, + 1, // Skip to: 104527 + /* 17920 */ MCD_OPC_Decode, + 207, + 47, + 120, // Opcode: WHILELS_PWW_D + /* 17924 */ MCD_OPC_FilterValue, + 4, + 147, + 0, + 0, // Skip to: 18076 + /* 17929 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 17932 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 17968 + /* 17937 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17940 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17954 + /* 17945 */ MCD_OPC_CheckPredicate, + 4, + 49, + 82, + 1, // Skip to: 104527 + /* 17950 */ MCD_OPC_Decode, + 162, + 47, + 121, // Opcode: WHILEGE_PXX_B + /* 17954 */ MCD_OPC_FilterValue, + 1, + 40, + 82, + 1, // Skip to: 104527 + /* 17959 */ MCD_OPC_CheckPredicate, + 4, + 35, + 82, + 1, // Skip to: 104527 + /* 17964 */ MCD_OPC_Decode, + 170, + 47, + 121, // Opcode: WHILEGT_PXX_B + /* 17968 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 18004 + /* 17973 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17976 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 17990 + /* 17981 */ MCD_OPC_CheckPredicate, + 4, + 13, + 82, + 1, // Skip to: 104527 + /* 17986 */ MCD_OPC_Decode, + 164, + 47, + 121, // Opcode: WHILEGE_PXX_H + /* 17990 */ MCD_OPC_FilterValue, + 1, + 4, + 82, + 1, // Skip to: 104527 + /* 17995 */ MCD_OPC_CheckPredicate, + 4, + 255, + 81, + 1, // Skip to: 104527 + /* 18000 */ MCD_OPC_Decode, + 172, + 47, + 121, // Opcode: WHILEGT_PXX_H + /* 18004 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 18040 + /* 18009 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18012 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18026 + /* 18017 */ MCD_OPC_CheckPredicate, + 4, + 233, + 81, + 1, // Skip to: 104527 + /* 18022 */ MCD_OPC_Decode, + 165, + 47, + 121, // Opcode: WHILEGE_PXX_S + /* 18026 */ MCD_OPC_FilterValue, + 1, + 224, + 81, + 1, // Skip to: 104527 + /* 18031 */ MCD_OPC_CheckPredicate, + 4, + 219, + 81, + 1, // Skip to: 104527 + /* 18036 */ MCD_OPC_Decode, + 173, + 47, + 121, // Opcode: WHILEGT_PXX_S + /* 18040 */ MCD_OPC_FilterValue, + 3, + 210, + 81, + 1, // Skip to: 104527 + /* 18045 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18048 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18062 + /* 18053 */ MCD_OPC_CheckPredicate, + 4, + 197, + 81, + 1, // Skip to: 104527 + /* 18058 */ MCD_OPC_Decode, + 163, + 47, + 121, // Opcode: WHILEGE_PXX_D + /* 18062 */ MCD_OPC_FilterValue, + 1, + 188, + 81, + 1, // Skip to: 104527 + /* 18067 */ MCD_OPC_CheckPredicate, + 4, + 183, + 81, + 1, // Skip to: 104527 + /* 18072 */ MCD_OPC_Decode, + 171, + 47, + 121, // Opcode: WHILEGT_PXX_D + /* 18076 */ MCD_OPC_FilterValue, + 5, + 147, + 0, + 0, // Skip to: 18228 + /* 18081 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 18084 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 18120 + /* 18089 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18092 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18106 + /* 18097 */ MCD_OPC_CheckPredicate, + 3, + 153, + 81, + 1, // Skip to: 104527 + /* 18102 */ MCD_OPC_Decode, + 218, + 47, + 121, // Opcode: WHILELT_PXX_B + /* 18106 */ MCD_OPC_FilterValue, + 1, + 144, + 81, + 1, // Skip to: 104527 + /* 18111 */ MCD_OPC_CheckPredicate, + 3, + 139, + 81, + 1, // Skip to: 104527 + /* 18116 */ MCD_OPC_Decode, + 194, + 47, + 121, // Opcode: WHILELE_PXX_B + /* 18120 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 18156 + /* 18125 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18128 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18142 + /* 18133 */ MCD_OPC_CheckPredicate, + 3, + 117, + 81, + 1, // Skip to: 104527 + /* 18138 */ MCD_OPC_Decode, + 220, + 47, + 121, // Opcode: WHILELT_PXX_H + /* 18142 */ MCD_OPC_FilterValue, + 1, + 108, + 81, + 1, // Skip to: 104527 + /* 18147 */ MCD_OPC_CheckPredicate, + 3, + 103, + 81, + 1, // Skip to: 104527 + /* 18152 */ MCD_OPC_Decode, + 196, + 47, + 121, // Opcode: WHILELE_PXX_H + /* 18156 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 18192 + /* 18161 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18164 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18178 + /* 18169 */ MCD_OPC_CheckPredicate, + 3, + 81, + 81, + 1, // Skip to: 104527 + /* 18174 */ MCD_OPC_Decode, + 221, + 47, + 121, // Opcode: WHILELT_PXX_S + /* 18178 */ MCD_OPC_FilterValue, + 1, + 72, + 81, + 1, // Skip to: 104527 + /* 18183 */ MCD_OPC_CheckPredicate, + 3, + 67, + 81, + 1, // Skip to: 104527 + /* 18188 */ MCD_OPC_Decode, + 197, + 47, + 121, // Opcode: WHILELE_PXX_S + /* 18192 */ MCD_OPC_FilterValue, + 3, + 58, + 81, + 1, // Skip to: 104527 + /* 18197 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18200 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18214 + /* 18205 */ MCD_OPC_CheckPredicate, + 3, + 45, + 81, + 1, // Skip to: 104527 + /* 18210 */ MCD_OPC_Decode, + 219, + 47, + 121, // Opcode: WHILELT_PXX_D + /* 18214 */ MCD_OPC_FilterValue, + 1, + 36, + 81, + 1, // Skip to: 104527 + /* 18219 */ MCD_OPC_CheckPredicate, + 3, + 31, + 81, + 1, // Skip to: 104527 + /* 18224 */ MCD_OPC_Decode, + 195, + 47, + 121, // Opcode: WHILELE_PXX_D + /* 18228 */ MCD_OPC_FilterValue, + 6, + 147, + 0, + 0, // Skip to: 18380 + /* 18233 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 18236 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 18272 + /* 18241 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18244 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18258 + /* 18249 */ MCD_OPC_CheckPredicate, + 4, + 1, + 81, + 1, // Skip to: 104527 + /* 18254 */ MCD_OPC_Decode, + 186, + 47, + 121, // Opcode: WHILEHS_PXX_B + /* 18258 */ MCD_OPC_FilterValue, + 1, + 248, + 80, + 1, // Skip to: 104527 + /* 18263 */ MCD_OPC_CheckPredicate, + 4, + 243, + 80, + 1, // Skip to: 104527 + /* 18268 */ MCD_OPC_Decode, + 178, + 47, + 121, // Opcode: WHILEHI_PXX_B + /* 18272 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 18308 + /* 18277 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18280 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18294 + /* 18285 */ MCD_OPC_CheckPredicate, + 4, + 221, + 80, + 1, // Skip to: 104527 + /* 18290 */ MCD_OPC_Decode, + 188, + 47, + 121, // Opcode: WHILEHS_PXX_H + /* 18294 */ MCD_OPC_FilterValue, + 1, + 212, + 80, + 1, // Skip to: 104527 + /* 18299 */ MCD_OPC_CheckPredicate, + 4, + 207, + 80, + 1, // Skip to: 104527 + /* 18304 */ MCD_OPC_Decode, + 180, + 47, + 121, // Opcode: WHILEHI_PXX_H + /* 18308 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 18344 + /* 18313 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18316 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18330 + /* 18321 */ MCD_OPC_CheckPredicate, + 4, + 185, + 80, + 1, // Skip to: 104527 + /* 18326 */ MCD_OPC_Decode, + 189, + 47, + 121, // Opcode: WHILEHS_PXX_S + /* 18330 */ MCD_OPC_FilterValue, + 1, + 176, + 80, + 1, // Skip to: 104527 + /* 18335 */ MCD_OPC_CheckPredicate, + 4, + 171, + 80, + 1, // Skip to: 104527 + /* 18340 */ MCD_OPC_Decode, + 181, + 47, + 121, // Opcode: WHILEHI_PXX_S + /* 18344 */ MCD_OPC_FilterValue, + 3, + 162, + 80, + 1, // Skip to: 104527 + /* 18349 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18352 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18366 + /* 18357 */ MCD_OPC_CheckPredicate, + 4, + 149, + 80, + 1, // Skip to: 104527 + /* 18362 */ MCD_OPC_Decode, + 187, + 47, + 121, // Opcode: WHILEHS_PXX_D + /* 18366 */ MCD_OPC_FilterValue, + 1, + 140, + 80, + 1, // Skip to: 104527 + /* 18371 */ MCD_OPC_CheckPredicate, + 4, + 135, + 80, + 1, // Skip to: 104527 + /* 18376 */ MCD_OPC_Decode, + 179, + 47, + 121, // Opcode: WHILEHI_PXX_D + /* 18380 */ MCD_OPC_FilterValue, + 7, + 147, + 0, + 0, // Skip to: 18532 + /* 18385 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 18388 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 18424 + /* 18393 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18396 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18410 + /* 18401 */ MCD_OPC_CheckPredicate, + 3, + 105, + 80, + 1, // Skip to: 104527 + /* 18406 */ MCD_OPC_Decode, + 202, + 47, + 121, // Opcode: WHILELO_PXX_B + /* 18410 */ MCD_OPC_FilterValue, + 1, + 96, + 80, + 1, // Skip to: 104527 + /* 18415 */ MCD_OPC_CheckPredicate, + 3, + 91, + 80, + 1, // Skip to: 104527 + /* 18420 */ MCD_OPC_Decode, + 210, + 47, + 121, // Opcode: WHILELS_PXX_B + /* 18424 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 18460 + /* 18429 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18432 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18446 + /* 18437 */ MCD_OPC_CheckPredicate, + 3, + 69, + 80, + 1, // Skip to: 104527 + /* 18442 */ MCD_OPC_Decode, + 204, + 47, + 121, // Opcode: WHILELO_PXX_H + /* 18446 */ MCD_OPC_FilterValue, + 1, + 60, + 80, + 1, // Skip to: 104527 + /* 18451 */ MCD_OPC_CheckPredicate, + 3, + 55, + 80, + 1, // Skip to: 104527 + /* 18456 */ MCD_OPC_Decode, + 212, + 47, + 121, // Opcode: WHILELS_PXX_H + /* 18460 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 18496 + /* 18465 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18468 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18482 + /* 18473 */ MCD_OPC_CheckPredicate, + 3, + 33, + 80, + 1, // Skip to: 104527 + /* 18478 */ MCD_OPC_Decode, + 205, + 47, + 121, // Opcode: WHILELO_PXX_S + /* 18482 */ MCD_OPC_FilterValue, + 1, + 24, + 80, + 1, // Skip to: 104527 + /* 18487 */ MCD_OPC_CheckPredicate, + 3, + 19, + 80, + 1, // Skip to: 104527 + /* 18492 */ MCD_OPC_Decode, + 213, + 47, + 121, // Opcode: WHILELS_PXX_S + /* 18496 */ MCD_OPC_FilterValue, + 3, + 10, + 80, + 1, // Skip to: 104527 + /* 18501 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18504 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18518 + /* 18509 */ MCD_OPC_CheckPredicate, + 3, + 253, + 79, + 1, // Skip to: 104527 + /* 18514 */ MCD_OPC_Decode, + 203, + 47, + 121, // Opcode: WHILELO_PXX_D + /* 18518 */ MCD_OPC_FilterValue, + 1, + 244, + 79, + 1, // Skip to: 104527 + /* 18523 */ MCD_OPC_CheckPredicate, + 3, + 239, + 79, + 1, // Skip to: 104527 + /* 18528 */ MCD_OPC_Decode, + 211, + 47, + 121, // Opcode: WHILELS_PXX_D + /* 18532 */ MCD_OPC_FilterValue, + 8, + 75, + 0, + 0, // Skip to: 18612 + /* 18537 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 18540 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 18576 + /* 18545 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 18548 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 18562 + /* 18553 */ MCD_OPC_CheckPredicate, + 3, + 209, + 79, + 1, // Skip to: 104527 + /* 18558 */ MCD_OPC_Decode, + 226, + 11, + 122, // Opcode: CTERMEQ_WW + /* 18562 */ MCD_OPC_FilterValue, + 3, + 200, + 79, + 1, // Skip to: 104527 + /* 18567 */ MCD_OPC_CheckPredicate, + 3, + 195, + 79, + 1, // Skip to: 104527 + /* 18572 */ MCD_OPC_Decode, + 227, + 11, + 123, // Opcode: CTERMEQ_XX + /* 18576 */ MCD_OPC_FilterValue, + 16, + 186, + 79, + 1, // Skip to: 104527 + /* 18581 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 18584 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 18598 + /* 18589 */ MCD_OPC_CheckPredicate, + 3, + 173, + 79, + 1, // Skip to: 104527 + /* 18594 */ MCD_OPC_Decode, + 228, + 11, + 122, // Opcode: CTERMNE_WW + /* 18598 */ MCD_OPC_FilterValue, + 3, + 164, + 79, + 1, // Skip to: 104527 + /* 18603 */ MCD_OPC_CheckPredicate, + 3, + 159, + 79, + 1, // Skip to: 104527 + /* 18608 */ MCD_OPC_Decode, + 229, + 11, + 123, // Opcode: CTERMNE_XX + /* 18612 */ MCD_OPC_FilterValue, + 12, + 150, + 79, + 1, // Skip to: 104527 + /* 18617 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 18620 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 18656 + /* 18625 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18628 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18642 + /* 18633 */ MCD_OPC_CheckPredicate, + 4, + 129, + 79, + 1, // Skip to: 104527 + /* 18638 */ MCD_OPC_Decode, + 226, + 47, + 121, // Opcode: WHILEWR_PXX_B + /* 18642 */ MCD_OPC_FilterValue, + 1, + 120, + 79, + 1, // Skip to: 104527 + /* 18647 */ MCD_OPC_CheckPredicate, + 4, + 115, + 79, + 1, // Skip to: 104527 + /* 18652 */ MCD_OPC_Decode, + 222, + 47, + 121, // Opcode: WHILERW_PXX_B + /* 18656 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 18692 + /* 18661 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18664 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18678 + /* 18669 */ MCD_OPC_CheckPredicate, + 4, + 93, + 79, + 1, // Skip to: 104527 + /* 18674 */ MCD_OPC_Decode, + 228, + 47, + 121, // Opcode: WHILEWR_PXX_H + /* 18678 */ MCD_OPC_FilterValue, + 1, + 84, + 79, + 1, // Skip to: 104527 + /* 18683 */ MCD_OPC_CheckPredicate, + 4, + 79, + 79, + 1, // Skip to: 104527 + /* 18688 */ MCD_OPC_Decode, + 224, + 47, + 121, // Opcode: WHILERW_PXX_H + /* 18692 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 18728 + /* 18697 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18700 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18714 + /* 18705 */ MCD_OPC_CheckPredicate, + 4, + 57, + 79, + 1, // Skip to: 104527 + /* 18710 */ MCD_OPC_Decode, + 229, + 47, + 121, // Opcode: WHILEWR_PXX_S + /* 18714 */ MCD_OPC_FilterValue, + 1, + 48, + 79, + 1, // Skip to: 104527 + /* 18719 */ MCD_OPC_CheckPredicate, + 4, + 43, + 79, + 1, // Skip to: 104527 + /* 18724 */ MCD_OPC_Decode, + 225, + 47, + 121, // Opcode: WHILERW_PXX_S + /* 18728 */ MCD_OPC_FilterValue, + 3, + 34, + 79, + 1, // Skip to: 104527 + /* 18733 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18736 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 18750 + /* 18741 */ MCD_OPC_CheckPredicate, + 4, + 21, + 79, + 1, // Skip to: 104527 + /* 18746 */ MCD_OPC_Decode, + 227, + 47, + 121, // Opcode: WHILEWR_PXX_D + /* 18750 */ MCD_OPC_FilterValue, + 1, + 12, + 79, + 1, // Skip to: 104527 + /* 18755 */ MCD_OPC_CheckPredicate, + 4, + 7, + 79, + 1, // Skip to: 104527 + /* 18760 */ MCD_OPC_Decode, + 223, + 47, + 121, // Opcode: WHILERW_PXX_D + /* 18764 */ MCD_OPC_FilterValue, + 1, + 138, + 0, + 0, // Skip to: 18907 + /* 18769 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 18772 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 18879 + /* 18777 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 18780 */ MCD_OPC_FilterValue, + 0, + 66, + 0, + 0, // Skip to: 18851 + /* 18785 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 18788 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 18823 + /* 18793 */ MCD_OPC_CheckPredicate, + 0, + 225, + 78, + 1, // Skip to: 104527 + /* 18798 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 218, + 78, + 1, // Skip to: 104527 + /* 18805 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 211, + 78, + 1, // Skip to: 104527 + /* 18812 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 204, + 78, + 1, // Skip to: 104527 + /* 18819 */ MCD_OPC_Decode, + 244, + 28, + 124, // Opcode: PSEL_PPPRI_D + /* 18823 */ MCD_OPC_FilterValue, + 1, + 195, + 78, + 1, // Skip to: 104527 + /* 18828 */ MCD_OPC_CheckPredicate, + 0, + 190, + 78, + 1, // Skip to: 104527 + /* 18833 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 183, + 78, + 1, // Skip to: 104527 + /* 18840 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 176, + 78, + 1, // Skip to: 104527 + /* 18847 */ MCD_OPC_Decode, + 246, + 28, + 125, // Opcode: PSEL_PPPRI_S + /* 18851 */ MCD_OPC_FilterValue, + 1, + 167, + 78, + 1, // Skip to: 104527 + /* 18856 */ MCD_OPC_CheckPredicate, + 0, + 162, + 78, + 1, // Skip to: 104527 + /* 18861 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 155, + 78, + 1, // Skip to: 104527 + /* 18868 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 148, + 78, + 1, // Skip to: 104527 + /* 18875 */ MCD_OPC_Decode, + 245, + 28, + 126, // Opcode: PSEL_PPPRI_H + /* 18879 */ MCD_OPC_FilterValue, + 1, + 139, + 78, + 1, // Skip to: 104527 + /* 18884 */ MCD_OPC_CheckPredicate, + 0, + 134, + 78, + 1, // Skip to: 104527 + /* 18889 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 127, + 78, + 1, // Skip to: 104527 + /* 18896 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 120, + 78, + 1, // Skip to: 104527 + /* 18903 */ MCD_OPC_Decode, + 243, + 28, + 127, // Opcode: PSEL_PPPRI_B + /* 18907 */ MCD_OPC_FilterValue, + 2, + 227, + 4, + 0, // Skip to: 20163 + /* 18912 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 18915 */ MCD_OPC_FilterValue, + 0, + 91, + 0, + 0, // Skip to: 19011 + /* 18920 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 18923 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18945 + /* 18928 */ MCD_OPC_CheckPredicate, + 3, + 90, + 78, + 1, // Skip to: 104527 + /* 18933 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 83, + 78, + 1, // Skip to: 104527 + /* 18940 */ MCD_OPC_Decode, + 177, + 11, + 128, + 1, // Opcode: CNTP_XPP_B + /* 18945 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 18967 + /* 18950 */ MCD_OPC_CheckPredicate, + 3, + 68, + 78, + 1, // Skip to: 104527 + /* 18955 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 61, + 78, + 1, // Skip to: 104527 + /* 18962 */ MCD_OPC_Decode, + 179, + 11, + 128, + 1, // Opcode: CNTP_XPP_H + /* 18967 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 18989 + /* 18972 */ MCD_OPC_CheckPredicate, + 3, + 46, + 78, + 1, // Skip to: 104527 + /* 18977 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 39, + 78, + 1, // Skip to: 104527 + /* 18984 */ MCD_OPC_Decode, + 180, + 11, + 128, + 1, // Opcode: CNTP_XPP_S + /* 18989 */ MCD_OPC_FilterValue, + 3, + 29, + 78, + 1, // Skip to: 104527 + /* 18994 */ MCD_OPC_CheckPredicate, + 3, + 24, + 78, + 1, // Skip to: 104527 + /* 18999 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 17, + 78, + 1, // Skip to: 104527 + /* 19006 */ MCD_OPC_Decode, + 178, + 11, + 128, + 1, // Opcode: CNTP_XPP_D + /* 19011 */ MCD_OPC_FilterValue, + 8, + 221, + 0, + 0, // Skip to: 19237 + /* 19016 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19019 */ MCD_OPC_FilterValue, + 0, + 48, + 0, + 0, // Skip to: 19072 + /* 19024 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 19027 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 19042 + /* 19032 */ MCD_OPC_CheckPredicate, + 3, + 242, + 77, + 1, // Skip to: 104527 + /* 19037 */ MCD_OPC_Decode, + 165, + 34, + 129, + 1, // Opcode: SQINCP_ZP_H + /* 19042 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 19057 + /* 19047 */ MCD_OPC_CheckPredicate, + 3, + 227, + 77, + 1, // Skip to: 104527 + /* 19052 */ MCD_OPC_Decode, + 166, + 34, + 129, + 1, // Opcode: SQINCP_ZP_S + /* 19057 */ MCD_OPC_FilterValue, + 3, + 217, + 77, + 1, // Skip to: 104527 + /* 19062 */ MCD_OPC_CheckPredicate, + 3, + 212, + 77, + 1, // Skip to: 104527 + /* 19067 */ MCD_OPC_Decode, + 164, + 34, + 129, + 1, // Opcode: SQINCP_ZP_D + /* 19072 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 19140 + /* 19077 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 19080 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19095 + /* 19085 */ MCD_OPC_CheckPredicate, + 3, + 189, + 77, + 1, // Skip to: 104527 + /* 19090 */ MCD_OPC_Decode, + 156, + 34, + 130, + 1, // Opcode: SQINCP_XPWd_B + /* 19095 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 19110 + /* 19100 */ MCD_OPC_CheckPredicate, + 3, + 174, + 77, + 1, // Skip to: 104527 + /* 19105 */ MCD_OPC_Decode, + 158, + 34, + 130, + 1, // Opcode: SQINCP_XPWd_H + /* 19110 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 19125 + /* 19115 */ MCD_OPC_CheckPredicate, + 3, + 159, + 77, + 1, // Skip to: 104527 + /* 19120 */ MCD_OPC_Decode, + 159, + 34, + 130, + 1, // Opcode: SQINCP_XPWd_S + /* 19125 */ MCD_OPC_FilterValue, + 3, + 149, + 77, + 1, // Skip to: 104527 + /* 19130 */ MCD_OPC_CheckPredicate, + 3, + 144, + 77, + 1, // Skip to: 104527 + /* 19135 */ MCD_OPC_Decode, + 157, + 34, + 130, + 1, // Opcode: SQINCP_XPWd_D + /* 19140 */ MCD_OPC_FilterValue, + 6, + 63, + 0, + 0, // Skip to: 19208 + /* 19145 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 19148 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19163 + /* 19153 */ MCD_OPC_CheckPredicate, + 3, + 121, + 77, + 1, // Skip to: 104527 + /* 19158 */ MCD_OPC_Decode, + 160, + 34, + 130, + 1, // Opcode: SQINCP_XP_B + /* 19163 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 19178 + /* 19168 */ MCD_OPC_CheckPredicate, + 3, + 106, + 77, + 1, // Skip to: 104527 + /* 19173 */ MCD_OPC_Decode, + 162, + 34, + 130, + 1, // Opcode: SQINCP_XP_H + /* 19178 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 19193 + /* 19183 */ MCD_OPC_CheckPredicate, + 3, + 91, + 77, + 1, // Skip to: 104527 + /* 19188 */ MCD_OPC_Decode, + 163, + 34, + 130, + 1, // Opcode: SQINCP_XP_S + /* 19193 */ MCD_OPC_FilterValue, + 3, + 81, + 77, + 1, // Skip to: 104527 + /* 19198 */ MCD_OPC_CheckPredicate, + 3, + 76, + 77, + 1, // Skip to: 104527 + /* 19203 */ MCD_OPC_Decode, + 161, + 34, + 130, + 1, // Opcode: SQINCP_XP_D + /* 19208 */ MCD_OPC_FilterValue, + 8, + 66, + 77, + 1, // Skip to: 104527 + /* 19213 */ MCD_OPC_CheckPredicate, + 6, + 61, + 77, + 1, // Skip to: 104527 + /* 19218 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 54, + 77, + 1, // Skip to: 104527 + /* 19225 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 47, + 77, + 1, // Skip to: 104527 + /* 19232 */ MCD_OPC_Decode, + 230, + 47, + 131, + 1, // Opcode: WRFFR + /* 19237 */ MCD_OPC_FilterValue, + 9, + 200, + 0, + 0, // Skip to: 19442 + /* 19242 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 19245 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 19283 + /* 19250 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19253 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19268 + /* 19258 */ MCD_OPC_CheckPredicate, + 3, + 16, + 77, + 1, // Skip to: 104527 + /* 19263 */ MCD_OPC_Decode, + 210, + 44, + 132, + 1, // Opcode: UQINCP_WP_B + /* 19268 */ MCD_OPC_FilterValue, + 6, + 6, + 77, + 1, // Skip to: 104527 + /* 19273 */ MCD_OPC_CheckPredicate, + 3, + 1, + 77, + 1, // Skip to: 104527 + /* 19278 */ MCD_OPC_Decode, + 214, + 44, + 130, + 1, // Opcode: UQINCP_XP_B + /* 19283 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 19336 + /* 19288 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19291 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19306 + /* 19296 */ MCD_OPC_CheckPredicate, + 3, + 234, + 76, + 1, // Skip to: 104527 + /* 19301 */ MCD_OPC_Decode, + 219, + 44, + 129, + 1, // Opcode: UQINCP_ZP_H + /* 19306 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19321 + /* 19311 */ MCD_OPC_CheckPredicate, + 3, + 219, + 76, + 1, // Skip to: 104527 + /* 19316 */ MCD_OPC_Decode, + 212, + 44, + 132, + 1, // Opcode: UQINCP_WP_H + /* 19321 */ MCD_OPC_FilterValue, + 6, + 209, + 76, + 1, // Skip to: 104527 + /* 19326 */ MCD_OPC_CheckPredicate, + 3, + 204, + 76, + 1, // Skip to: 104527 + /* 19331 */ MCD_OPC_Decode, + 216, + 44, + 130, + 1, // Opcode: UQINCP_XP_H + /* 19336 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 19389 + /* 19341 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19344 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19359 + /* 19349 */ MCD_OPC_CheckPredicate, + 3, + 181, + 76, + 1, // Skip to: 104527 + /* 19354 */ MCD_OPC_Decode, + 220, + 44, + 129, + 1, // Opcode: UQINCP_ZP_S + /* 19359 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19374 + /* 19364 */ MCD_OPC_CheckPredicate, + 3, + 166, + 76, + 1, // Skip to: 104527 + /* 19369 */ MCD_OPC_Decode, + 213, + 44, + 132, + 1, // Opcode: UQINCP_WP_S + /* 19374 */ MCD_OPC_FilterValue, + 6, + 156, + 76, + 1, // Skip to: 104527 + /* 19379 */ MCD_OPC_CheckPredicate, + 3, + 151, + 76, + 1, // Skip to: 104527 + /* 19384 */ MCD_OPC_Decode, + 217, + 44, + 130, + 1, // Opcode: UQINCP_XP_S + /* 19389 */ MCD_OPC_FilterValue, + 3, + 141, + 76, + 1, // Skip to: 104527 + /* 19394 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19397 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19412 + /* 19402 */ MCD_OPC_CheckPredicate, + 3, + 128, + 76, + 1, // Skip to: 104527 + /* 19407 */ MCD_OPC_Decode, + 218, + 44, + 129, + 1, // Opcode: UQINCP_ZP_D + /* 19412 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19427 + /* 19417 */ MCD_OPC_CheckPredicate, + 3, + 113, + 76, + 1, // Skip to: 104527 + /* 19422 */ MCD_OPC_Decode, + 211, + 44, + 132, + 1, // Opcode: UQINCP_WP_D + /* 19427 */ MCD_OPC_FilterValue, + 6, + 103, + 76, + 1, // Skip to: 104527 + /* 19432 */ MCD_OPC_CheckPredicate, + 3, + 98, + 76, + 1, // Skip to: 104527 + /* 19437 */ MCD_OPC_Decode, + 215, + 44, + 130, + 1, // Opcode: UQINCP_XP_D + /* 19442 */ MCD_OPC_FilterValue, + 10, + 200, + 0, + 0, // Skip to: 19647 + /* 19447 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 19450 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 19488 + /* 19455 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19458 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19473 + /* 19463 */ MCD_OPC_CheckPredicate, + 3, + 67, + 76, + 1, // Skip to: 104527 + /* 19468 */ MCD_OPC_Decode, + 171, + 33, + 130, + 1, // Opcode: SQDECP_XPWd_B + /* 19473 */ MCD_OPC_FilterValue, + 6, + 57, + 76, + 1, // Skip to: 104527 + /* 19478 */ MCD_OPC_CheckPredicate, + 3, + 52, + 76, + 1, // Skip to: 104527 + /* 19483 */ MCD_OPC_Decode, + 175, + 33, + 130, + 1, // Opcode: SQDECP_XP_B + /* 19488 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 19541 + /* 19493 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19496 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19511 + /* 19501 */ MCD_OPC_CheckPredicate, + 3, + 29, + 76, + 1, // Skip to: 104527 + /* 19506 */ MCD_OPC_Decode, + 180, + 33, + 129, + 1, // Opcode: SQDECP_ZP_H + /* 19511 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19526 + /* 19516 */ MCD_OPC_CheckPredicate, + 3, + 14, + 76, + 1, // Skip to: 104527 + /* 19521 */ MCD_OPC_Decode, + 173, + 33, + 130, + 1, // Opcode: SQDECP_XPWd_H + /* 19526 */ MCD_OPC_FilterValue, + 6, + 4, + 76, + 1, // Skip to: 104527 + /* 19531 */ MCD_OPC_CheckPredicate, + 3, + 255, + 75, + 1, // Skip to: 104527 + /* 19536 */ MCD_OPC_Decode, + 177, + 33, + 130, + 1, // Opcode: SQDECP_XP_H + /* 19541 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 19594 + /* 19546 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19549 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19564 + /* 19554 */ MCD_OPC_CheckPredicate, + 3, + 232, + 75, + 1, // Skip to: 104527 + /* 19559 */ MCD_OPC_Decode, + 181, + 33, + 129, + 1, // Opcode: SQDECP_ZP_S + /* 19564 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19579 + /* 19569 */ MCD_OPC_CheckPredicate, + 3, + 217, + 75, + 1, // Skip to: 104527 + /* 19574 */ MCD_OPC_Decode, + 174, + 33, + 130, + 1, // Opcode: SQDECP_XPWd_S + /* 19579 */ MCD_OPC_FilterValue, + 6, + 207, + 75, + 1, // Skip to: 104527 + /* 19584 */ MCD_OPC_CheckPredicate, + 3, + 202, + 75, + 1, // Skip to: 104527 + /* 19589 */ MCD_OPC_Decode, + 178, + 33, + 130, + 1, // Opcode: SQDECP_XP_S + /* 19594 */ MCD_OPC_FilterValue, + 3, + 192, + 75, + 1, // Skip to: 104527 + /* 19599 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19602 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19617 + /* 19607 */ MCD_OPC_CheckPredicate, + 3, + 179, + 75, + 1, // Skip to: 104527 + /* 19612 */ MCD_OPC_Decode, + 179, + 33, + 129, + 1, // Opcode: SQDECP_ZP_D + /* 19617 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19632 + /* 19622 */ MCD_OPC_CheckPredicate, + 3, + 164, + 75, + 1, // Skip to: 104527 + /* 19627 */ MCD_OPC_Decode, + 172, + 33, + 130, + 1, // Opcode: SQDECP_XPWd_D + /* 19632 */ MCD_OPC_FilterValue, + 6, + 154, + 75, + 1, // Skip to: 104527 + /* 19637 */ MCD_OPC_CheckPredicate, + 3, + 149, + 75, + 1, // Skip to: 104527 + /* 19642 */ MCD_OPC_Decode, + 176, + 33, + 130, + 1, // Opcode: SQDECP_XP_D + /* 19647 */ MCD_OPC_FilterValue, + 11, + 200, + 0, + 0, // Skip to: 19852 + /* 19652 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 19655 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 19693 + /* 19660 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19663 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19678 + /* 19668 */ MCD_OPC_CheckPredicate, + 3, + 118, + 75, + 1, // Skip to: 104527 + /* 19673 */ MCD_OPC_Decode, + 188, + 44, + 132, + 1, // Opcode: UQDECP_WP_B + /* 19678 */ MCD_OPC_FilterValue, + 6, + 108, + 75, + 1, // Skip to: 104527 + /* 19683 */ MCD_OPC_CheckPredicate, + 3, + 103, + 75, + 1, // Skip to: 104527 + /* 19688 */ MCD_OPC_Decode, + 192, + 44, + 130, + 1, // Opcode: UQDECP_XP_B + /* 19693 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 19746 + /* 19698 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19701 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19716 + /* 19706 */ MCD_OPC_CheckPredicate, + 3, + 80, + 75, + 1, // Skip to: 104527 + /* 19711 */ MCD_OPC_Decode, + 197, + 44, + 129, + 1, // Opcode: UQDECP_ZP_H + /* 19716 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19731 + /* 19721 */ MCD_OPC_CheckPredicate, + 3, + 65, + 75, + 1, // Skip to: 104527 + /* 19726 */ MCD_OPC_Decode, + 190, + 44, + 132, + 1, // Opcode: UQDECP_WP_H + /* 19731 */ MCD_OPC_FilterValue, + 6, + 55, + 75, + 1, // Skip to: 104527 + /* 19736 */ MCD_OPC_CheckPredicate, + 3, + 50, + 75, + 1, // Skip to: 104527 + /* 19741 */ MCD_OPC_Decode, + 194, + 44, + 130, + 1, // Opcode: UQDECP_XP_H + /* 19746 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 19799 + /* 19751 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19754 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19769 + /* 19759 */ MCD_OPC_CheckPredicate, + 3, + 27, + 75, + 1, // Skip to: 104527 + /* 19764 */ MCD_OPC_Decode, + 198, + 44, + 129, + 1, // Opcode: UQDECP_ZP_S + /* 19769 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19784 + /* 19774 */ MCD_OPC_CheckPredicate, + 3, + 12, + 75, + 1, // Skip to: 104527 + /* 19779 */ MCD_OPC_Decode, + 191, + 44, + 132, + 1, // Opcode: UQDECP_WP_S + /* 19784 */ MCD_OPC_FilterValue, + 6, + 2, + 75, + 1, // Skip to: 104527 + /* 19789 */ MCD_OPC_CheckPredicate, + 3, + 253, + 74, + 1, // Skip to: 104527 + /* 19794 */ MCD_OPC_Decode, + 195, + 44, + 130, + 1, // Opcode: UQDECP_XP_S + /* 19799 */ MCD_OPC_FilterValue, + 3, + 243, + 74, + 1, // Skip to: 104527 + /* 19804 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19807 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19822 + /* 19812 */ MCD_OPC_CheckPredicate, + 3, + 230, + 74, + 1, // Skip to: 104527 + /* 19817 */ MCD_OPC_Decode, + 196, + 44, + 129, + 1, // Opcode: UQDECP_ZP_D + /* 19822 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19837 + /* 19827 */ MCD_OPC_CheckPredicate, + 3, + 215, + 74, + 1, // Skip to: 104527 + /* 19832 */ MCD_OPC_Decode, + 189, + 44, + 132, + 1, // Opcode: UQDECP_WP_D + /* 19837 */ MCD_OPC_FilterValue, + 6, + 205, + 74, + 1, // Skip to: 104527 + /* 19842 */ MCD_OPC_CheckPredicate, + 3, + 200, + 74, + 1, // Skip to: 104527 + /* 19847 */ MCD_OPC_Decode, + 193, + 44, + 130, + 1, // Opcode: UQDECP_XP_D + /* 19852 */ MCD_OPC_FilterValue, + 12, + 162, + 0, + 0, // Skip to: 20019 + /* 19857 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 19860 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 19905 + /* 19865 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19868 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19883 + /* 19873 */ MCD_OPC_CheckPredicate, + 3, + 169, + 74, + 1, // Skip to: 104527 + /* 19878 */ MCD_OPC_Decode, + 140, + 21, + 130, + 1, // Opcode: INCP_XP_B + /* 19883 */ MCD_OPC_FilterValue, + 8, + 159, + 74, + 1, // Skip to: 104527 + /* 19888 */ MCD_OPC_CheckPredicate, + 6, + 154, + 74, + 1, // Skip to: 104527 + /* 19893 */ MCD_OPC_CheckField, + 0, + 9, + 0, + 147, + 74, + 1, // Skip to: 104527 + /* 19900 */ MCD_OPC_Decode, + 255, + 30, + 133, + 1, // Opcode: SETFFR + /* 19905 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 19943 + /* 19910 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19913 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19928 + /* 19918 */ MCD_OPC_CheckPredicate, + 3, + 124, + 74, + 1, // Skip to: 104527 + /* 19923 */ MCD_OPC_Decode, + 145, + 21, + 129, + 1, // Opcode: INCP_ZP_H + /* 19928 */ MCD_OPC_FilterValue, + 4, + 114, + 74, + 1, // Skip to: 104527 + /* 19933 */ MCD_OPC_CheckPredicate, + 3, + 109, + 74, + 1, // Skip to: 104527 + /* 19938 */ MCD_OPC_Decode, + 142, + 21, + 130, + 1, // Opcode: INCP_XP_H + /* 19943 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 19981 + /* 19948 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19951 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 19966 + /* 19956 */ MCD_OPC_CheckPredicate, + 3, + 86, + 74, + 1, // Skip to: 104527 + /* 19961 */ MCD_OPC_Decode, + 146, + 21, + 129, + 1, // Opcode: INCP_ZP_S + /* 19966 */ MCD_OPC_FilterValue, + 4, + 76, + 74, + 1, // Skip to: 104527 + /* 19971 */ MCD_OPC_CheckPredicate, + 3, + 71, + 74, + 1, // Skip to: 104527 + /* 19976 */ MCD_OPC_Decode, + 143, + 21, + 130, + 1, // Opcode: INCP_XP_S + /* 19981 */ MCD_OPC_FilterValue, + 3, + 61, + 74, + 1, // Skip to: 104527 + /* 19986 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 19989 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20004 + /* 19994 */ MCD_OPC_CheckPredicate, + 3, + 48, + 74, + 1, // Skip to: 104527 + /* 19999 */ MCD_OPC_Decode, + 144, + 21, + 129, + 1, // Opcode: INCP_ZP_D + /* 20004 */ MCD_OPC_FilterValue, + 4, + 38, + 74, + 1, // Skip to: 104527 + /* 20009 */ MCD_OPC_CheckPredicate, + 3, + 33, + 74, + 1, // Skip to: 104527 + /* 20014 */ MCD_OPC_Decode, + 141, + 21, + 130, + 1, // Opcode: INCP_XP_D + /* 20019 */ MCD_OPC_FilterValue, + 13, + 23, + 74, + 1, // Skip to: 104527 + /* 20024 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20027 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 20049 + /* 20032 */ MCD_OPC_CheckPredicate, + 3, + 10, + 74, + 1, // Skip to: 104527 + /* 20037 */ MCD_OPC_CheckField, + 9, + 5, + 4, + 3, + 74, + 1, // Skip to: 104527 + /* 20044 */ MCD_OPC_Decode, + 238, + 11, + 130, + 1, // Opcode: DECP_XP_B + /* 20049 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 20087 + /* 20054 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 20057 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20072 + /* 20062 */ MCD_OPC_CheckPredicate, + 3, + 236, + 73, + 1, // Skip to: 104527 + /* 20067 */ MCD_OPC_Decode, + 243, + 11, + 129, + 1, // Opcode: DECP_ZP_H + /* 20072 */ MCD_OPC_FilterValue, + 4, + 226, + 73, + 1, // Skip to: 104527 + /* 20077 */ MCD_OPC_CheckPredicate, + 3, + 221, + 73, + 1, // Skip to: 104527 + /* 20082 */ MCD_OPC_Decode, + 240, + 11, + 130, + 1, // Opcode: DECP_XP_H + /* 20087 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 20125 + /* 20092 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 20095 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20110 + /* 20100 */ MCD_OPC_CheckPredicate, + 3, + 198, + 73, + 1, // Skip to: 104527 + /* 20105 */ MCD_OPC_Decode, + 244, + 11, + 129, + 1, // Opcode: DECP_ZP_S + /* 20110 */ MCD_OPC_FilterValue, + 4, + 188, + 73, + 1, // Skip to: 104527 + /* 20115 */ MCD_OPC_CheckPredicate, + 3, + 183, + 73, + 1, // Skip to: 104527 + /* 20120 */ MCD_OPC_Decode, + 241, + 11, + 130, + 1, // Opcode: DECP_XP_S + /* 20125 */ MCD_OPC_FilterValue, + 3, + 173, + 73, + 1, // Skip to: 104527 + /* 20130 */ MCD_OPC_ExtractField, + 9, + 5, // Inst{13-9} ... + /* 20133 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20148 + /* 20138 */ MCD_OPC_CheckPredicate, + 3, + 160, + 73, + 1, // Skip to: 104527 + /* 20143 */ MCD_OPC_Decode, + 242, + 11, + 129, + 1, // Opcode: DECP_ZP_D + /* 20148 */ MCD_OPC_FilterValue, + 4, + 150, + 73, + 1, // Skip to: 104527 + /* 20153 */ MCD_OPC_CheckPredicate, + 3, + 145, + 73, + 1, // Skip to: 104527 + /* 20158 */ MCD_OPC_Decode, + 239, + 11, + 130, + 1, // Opcode: DECP_XP_D + /* 20163 */ MCD_OPC_FilterValue, + 3, + 135, + 73, + 1, // Skip to: 104527 + /* 20168 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 20171 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 20239 + /* 20176 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20179 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20194 + /* 20184 */ MCD_OPC_CheckPredicate, + 3, + 114, + 73, + 1, // Skip to: 104527 + /* 20189 */ MCD_OPC_Decode, + 198, + 7, + 134, + 1, // Opcode: ADD_ZI_B + /* 20194 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 20209 + /* 20199 */ MCD_OPC_CheckPredicate, + 3, + 99, + 73, + 1, // Skip to: 104527 + /* 20204 */ MCD_OPC_Decode, + 200, + 7, + 135, + 1, // Opcode: ADD_ZI_H + /* 20209 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 20224 + /* 20214 */ MCD_OPC_CheckPredicate, + 3, + 84, + 73, + 1, // Skip to: 104527 + /* 20219 */ MCD_OPC_Decode, + 201, + 7, + 136, + 1, // Opcode: ADD_ZI_S + /* 20224 */ MCD_OPC_FilterValue, + 3, + 74, + 73, + 1, // Skip to: 104527 + /* 20229 */ MCD_OPC_CheckPredicate, + 3, + 69, + 73, + 1, // Skip to: 104527 + /* 20234 */ MCD_OPC_Decode, + 199, + 7, + 137, + 1, // Opcode: ADD_ZI_D + /* 20239 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 20307 + /* 20244 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20247 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20262 + /* 20252 */ MCD_OPC_CheckPredicate, + 3, + 46, + 73, + 1, // Skip to: 104527 + /* 20257 */ MCD_OPC_Decode, + 204, + 40, + 134, + 1, // Opcode: SUB_ZI_B + /* 20262 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 20277 + /* 20267 */ MCD_OPC_CheckPredicate, + 3, + 31, + 73, + 1, // Skip to: 104527 + /* 20272 */ MCD_OPC_Decode, + 206, + 40, + 135, + 1, // Opcode: SUB_ZI_H + /* 20277 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 20292 + /* 20282 */ MCD_OPC_CheckPredicate, + 3, + 16, + 73, + 1, // Skip to: 104527 + /* 20287 */ MCD_OPC_Decode, + 207, + 40, + 136, + 1, // Opcode: SUB_ZI_S + /* 20292 */ MCD_OPC_FilterValue, + 3, + 6, + 73, + 1, // Skip to: 104527 + /* 20297 */ MCD_OPC_CheckPredicate, + 3, + 1, + 73, + 1, // Skip to: 104527 + /* 20302 */ MCD_OPC_Decode, + 205, + 40, + 137, + 1, // Opcode: SUB_ZI_D + /* 20307 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 20375 + /* 20312 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20315 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20330 + /* 20320 */ MCD_OPC_CheckPredicate, + 3, + 234, + 72, + 1, // Skip to: 104527 + /* 20325 */ MCD_OPC_Decode, + 182, + 40, + 134, + 1, // Opcode: SUBR_ZI_B + /* 20330 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 20345 + /* 20335 */ MCD_OPC_CheckPredicate, + 3, + 219, + 72, + 1, // Skip to: 104527 + /* 20340 */ MCD_OPC_Decode, + 184, + 40, + 135, + 1, // Opcode: SUBR_ZI_H + /* 20345 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 20360 + /* 20350 */ MCD_OPC_CheckPredicate, + 3, + 204, + 72, + 1, // Skip to: 104527 + /* 20355 */ MCD_OPC_Decode, + 185, + 40, + 136, + 1, // Opcode: SUBR_ZI_S + /* 20360 */ MCD_OPC_FilterValue, + 3, + 194, + 72, + 1, // Skip to: 104527 + /* 20365 */ MCD_OPC_CheckPredicate, + 3, + 189, + 72, + 1, // Skip to: 104527 + /* 20370 */ MCD_OPC_Decode, + 183, + 40, + 137, + 1, // Opcode: SUBR_ZI_D + /* 20375 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 20443 + /* 20380 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20383 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20398 + /* 20388 */ MCD_OPC_CheckPredicate, + 3, + 166, + 72, + 1, // Skip to: 104527 + /* 20393 */ MCD_OPC_Decode, + 136, + 33, + 134, + 1, // Opcode: SQADD_ZI_B + /* 20398 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 20413 + /* 20403 */ MCD_OPC_CheckPredicate, + 3, + 151, + 72, + 1, // Skip to: 104527 + /* 20408 */ MCD_OPC_Decode, + 138, + 33, + 135, + 1, // Opcode: SQADD_ZI_H + /* 20413 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 20428 + /* 20418 */ MCD_OPC_CheckPredicate, + 3, + 136, + 72, + 1, // Skip to: 104527 + /* 20423 */ MCD_OPC_Decode, + 139, + 33, + 136, + 1, // Opcode: SQADD_ZI_S + /* 20428 */ MCD_OPC_FilterValue, + 3, + 126, + 72, + 1, // Skip to: 104527 + /* 20433 */ MCD_OPC_CheckPredicate, + 3, + 121, + 72, + 1, // Skip to: 104527 + /* 20438 */ MCD_OPC_Decode, + 137, + 33, + 137, + 1, // Opcode: SQADD_ZI_D + /* 20443 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 20511 + /* 20448 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20451 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20466 + /* 20456 */ MCD_OPC_CheckPredicate, + 3, + 98, + 72, + 1, // Skip to: 104527 + /* 20461 */ MCD_OPC_Decode, + 157, + 44, + 134, + 1, // Opcode: UQADD_ZI_B + /* 20466 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 20481 + /* 20471 */ MCD_OPC_CheckPredicate, + 3, + 83, + 72, + 1, // Skip to: 104527 + /* 20476 */ MCD_OPC_Decode, + 159, + 44, + 135, + 1, // Opcode: UQADD_ZI_H + /* 20481 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 20496 + /* 20486 */ MCD_OPC_CheckPredicate, + 3, + 68, + 72, + 1, // Skip to: 104527 + /* 20491 */ MCD_OPC_Decode, + 160, + 44, + 136, + 1, // Opcode: UQADD_ZI_S + /* 20496 */ MCD_OPC_FilterValue, + 3, + 58, + 72, + 1, // Skip to: 104527 + /* 20501 */ MCD_OPC_CheckPredicate, + 3, + 53, + 72, + 1, // Skip to: 104527 + /* 20506 */ MCD_OPC_Decode, + 158, + 44, + 137, + 1, // Opcode: UQADD_ZI_D + /* 20511 */ MCD_OPC_FilterValue, + 6, + 63, + 0, + 0, // Skip to: 20579 + /* 20516 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20519 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20534 + /* 20524 */ MCD_OPC_CheckPredicate, + 3, + 30, + 72, + 1, // Skip to: 104527 + /* 20529 */ MCD_OPC_Decode, + 252, + 35, + 134, + 1, // Opcode: SQSUB_ZI_B + /* 20534 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 20549 + /* 20539 */ MCD_OPC_CheckPredicate, + 3, + 15, + 72, + 1, // Skip to: 104527 + /* 20544 */ MCD_OPC_Decode, + 254, + 35, + 135, + 1, // Opcode: SQSUB_ZI_H + /* 20549 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 20564 + /* 20554 */ MCD_OPC_CheckPredicate, + 3, + 0, + 72, + 1, // Skip to: 104527 + /* 20559 */ MCD_OPC_Decode, + 255, + 35, + 136, + 1, // Opcode: SQSUB_ZI_S + /* 20564 */ MCD_OPC_FilterValue, + 3, + 246, + 71, + 1, // Skip to: 104527 + /* 20569 */ MCD_OPC_CheckPredicate, + 3, + 241, + 71, + 1, // Skip to: 104527 + /* 20574 */ MCD_OPC_Decode, + 253, + 35, + 137, + 1, // Opcode: SQSUB_ZI_D + /* 20579 */ MCD_OPC_FilterValue, + 7, + 63, + 0, + 0, // Skip to: 20647 + /* 20584 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20587 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 20602 + /* 20592 */ MCD_OPC_CheckPredicate, + 3, + 218, + 71, + 1, // Skip to: 104527 + /* 20597 */ MCD_OPC_Decode, + 183, + 45, + 134, + 1, // Opcode: UQSUB_ZI_B + /* 20602 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 20617 + /* 20607 */ MCD_OPC_CheckPredicate, + 3, + 203, + 71, + 1, // Skip to: 104527 + /* 20612 */ MCD_OPC_Decode, + 185, + 45, + 135, + 1, // Opcode: UQSUB_ZI_H + /* 20617 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 20632 + /* 20622 */ MCD_OPC_CheckPredicate, + 3, + 188, + 71, + 1, // Skip to: 104527 + /* 20627 */ MCD_OPC_Decode, + 186, + 45, + 136, + 1, // Opcode: UQSUB_ZI_S + /* 20632 */ MCD_OPC_FilterValue, + 3, + 178, + 71, + 1, // Skip to: 104527 + /* 20637 */ MCD_OPC_CheckPredicate, + 3, + 173, + 71, + 1, // Skip to: 104527 + /* 20642 */ MCD_OPC_Decode, + 184, + 45, + 137, + 1, // Opcode: UQSUB_ZI_D + /* 20647 */ MCD_OPC_FilterValue, + 8, + 91, + 0, + 0, // Skip to: 20743 + /* 20652 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20655 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 20677 + /* 20660 */ MCD_OPC_CheckPredicate, + 3, + 150, + 71, + 1, // Skip to: 104527 + /* 20665 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 143, + 71, + 1, // Skip to: 104527 + /* 20672 */ MCD_OPC_Decode, + 235, + 31, + 138, + 1, // Opcode: SMAX_ZI_B + /* 20677 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 20699 + /* 20682 */ MCD_OPC_CheckPredicate, + 3, + 128, + 71, + 1, // Skip to: 104527 + /* 20687 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 121, + 71, + 1, // Skip to: 104527 + /* 20694 */ MCD_OPC_Decode, + 237, + 31, + 138, + 1, // Opcode: SMAX_ZI_H + /* 20699 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 20721 + /* 20704 */ MCD_OPC_CheckPredicate, + 3, + 106, + 71, + 1, // Skip to: 104527 + /* 20709 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 99, + 71, + 1, // Skip to: 104527 + /* 20716 */ MCD_OPC_Decode, + 238, + 31, + 138, + 1, // Opcode: SMAX_ZI_S + /* 20721 */ MCD_OPC_FilterValue, + 3, + 89, + 71, + 1, // Skip to: 104527 + /* 20726 */ MCD_OPC_CheckPredicate, + 3, + 84, + 71, + 1, // Skip to: 104527 + /* 20731 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 77, + 71, + 1, // Skip to: 104527 + /* 20738 */ MCD_OPC_Decode, + 236, + 31, + 138, + 1, // Opcode: SMAX_ZI_D + /* 20743 */ MCD_OPC_FilterValue, + 9, + 91, + 0, + 0, // Skip to: 20839 + /* 20748 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20751 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 20773 + /* 20756 */ MCD_OPC_CheckPredicate, + 3, + 54, + 71, + 1, // Skip to: 104527 + /* 20761 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 47, + 71, + 1, // Skip to: 104527 + /* 20768 */ MCD_OPC_Decode, + 154, + 43, + 139, + 1, // Opcode: UMAX_ZI_B + /* 20773 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 20795 + /* 20778 */ MCD_OPC_CheckPredicate, + 3, + 32, + 71, + 1, // Skip to: 104527 + /* 20783 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 25, + 71, + 1, // Skip to: 104527 + /* 20790 */ MCD_OPC_Decode, + 156, + 43, + 139, + 1, // Opcode: UMAX_ZI_H + /* 20795 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 20817 + /* 20800 */ MCD_OPC_CheckPredicate, + 3, + 10, + 71, + 1, // Skip to: 104527 + /* 20805 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 3, + 71, + 1, // Skip to: 104527 + /* 20812 */ MCD_OPC_Decode, + 157, + 43, + 139, + 1, // Opcode: UMAX_ZI_S + /* 20817 */ MCD_OPC_FilterValue, + 3, + 249, + 70, + 1, // Skip to: 104527 + /* 20822 */ MCD_OPC_CheckPredicate, + 3, + 244, + 70, + 1, // Skip to: 104527 + /* 20827 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 237, + 70, + 1, // Skip to: 104527 + /* 20834 */ MCD_OPC_Decode, + 155, + 43, + 139, + 1, // Opcode: UMAX_ZI_D + /* 20839 */ MCD_OPC_FilterValue, + 10, + 91, + 0, + 0, // Skip to: 20935 + /* 20844 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20847 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 20869 + /* 20852 */ MCD_OPC_CheckPredicate, + 3, + 214, + 70, + 1, // Skip to: 104527 + /* 20857 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 207, + 70, + 1, // Skip to: 104527 + /* 20864 */ MCD_OPC_Decode, + 141, + 32, + 138, + 1, // Opcode: SMIN_ZI_B + /* 20869 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 20891 + /* 20874 */ MCD_OPC_CheckPredicate, + 3, + 192, + 70, + 1, // Skip to: 104527 + /* 20879 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 185, + 70, + 1, // Skip to: 104527 + /* 20886 */ MCD_OPC_Decode, + 143, + 32, + 138, + 1, // Opcode: SMIN_ZI_H + /* 20891 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 20913 + /* 20896 */ MCD_OPC_CheckPredicate, + 3, + 170, + 70, + 1, // Skip to: 104527 + /* 20901 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 163, + 70, + 1, // Skip to: 104527 + /* 20908 */ MCD_OPC_Decode, + 144, + 32, + 138, + 1, // Opcode: SMIN_ZI_S + /* 20913 */ MCD_OPC_FilterValue, + 3, + 153, + 70, + 1, // Skip to: 104527 + /* 20918 */ MCD_OPC_CheckPredicate, + 3, + 148, + 70, + 1, // Skip to: 104527 + /* 20923 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 141, + 70, + 1, // Skip to: 104527 + /* 20930 */ MCD_OPC_Decode, + 142, + 32, + 138, + 1, // Opcode: SMIN_ZI_D + /* 20935 */ MCD_OPC_FilterValue, + 11, + 91, + 0, + 0, // Skip to: 21031 + /* 20940 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 20943 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 20965 + /* 20948 */ MCD_OPC_CheckPredicate, + 3, + 118, + 70, + 1, // Skip to: 104527 + /* 20953 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 111, + 70, + 1, // Skip to: 104527 + /* 20960 */ MCD_OPC_Decode, + 187, + 43, + 139, + 1, // Opcode: UMIN_ZI_B + /* 20965 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 20987 + /* 20970 */ MCD_OPC_CheckPredicate, + 3, + 96, + 70, + 1, // Skip to: 104527 + /* 20975 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 89, + 70, + 1, // Skip to: 104527 + /* 20982 */ MCD_OPC_Decode, + 189, + 43, + 139, + 1, // Opcode: UMIN_ZI_H + /* 20987 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 21009 + /* 20992 */ MCD_OPC_CheckPredicate, + 3, + 74, + 70, + 1, // Skip to: 104527 + /* 20997 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 67, + 70, + 1, // Skip to: 104527 + /* 21004 */ MCD_OPC_Decode, + 190, + 43, + 139, + 1, // Opcode: UMIN_ZI_S + /* 21009 */ MCD_OPC_FilterValue, + 3, + 57, + 70, + 1, // Skip to: 104527 + /* 21014 */ MCD_OPC_CheckPredicate, + 3, + 52, + 70, + 1, // Skip to: 104527 + /* 21019 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 45, + 70, + 1, // Skip to: 104527 + /* 21026 */ MCD_OPC_Decode, + 188, + 43, + 139, + 1, // Opcode: UMIN_ZI_D + /* 21031 */ MCD_OPC_FilterValue, + 16, + 91, + 0, + 0, // Skip to: 21127 + /* 21036 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 21039 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 21061 + /* 21044 */ MCD_OPC_CheckPredicate, + 3, + 22, + 70, + 1, // Skip to: 104527 + /* 21049 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 15, + 70, + 1, // Skip to: 104527 + /* 21056 */ MCD_OPC_Decode, + 212, + 27, + 138, + 1, // Opcode: MUL_ZI_B + /* 21061 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 21083 + /* 21066 */ MCD_OPC_CheckPredicate, + 3, + 0, + 70, + 1, // Skip to: 104527 + /* 21071 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 249, + 69, + 1, // Skip to: 104527 + /* 21078 */ MCD_OPC_Decode, + 214, + 27, + 138, + 1, // Opcode: MUL_ZI_H + /* 21083 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 21105 + /* 21088 */ MCD_OPC_CheckPredicate, + 3, + 234, + 69, + 1, // Skip to: 104527 + /* 21093 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 227, + 69, + 1, // Skip to: 104527 + /* 21100 */ MCD_OPC_Decode, + 215, + 27, + 138, + 1, // Opcode: MUL_ZI_S + /* 21105 */ MCD_OPC_FilterValue, + 3, + 217, + 69, + 1, // Skip to: 104527 + /* 21110 */ MCD_OPC_CheckPredicate, + 3, + 212, + 69, + 1, // Skip to: 104527 + /* 21115 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 205, + 69, + 1, // Skip to: 104527 + /* 21122 */ MCD_OPC_Decode, + 213, + 27, + 138, + 1, // Opcode: MUL_ZI_D + /* 21127 */ MCD_OPC_FilterValue, + 24, + 63, + 0, + 0, // Skip to: 21195 + /* 21132 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 21135 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 21150 + /* 21140 */ MCD_OPC_CheckPredicate, + 3, + 182, + 69, + 1, // Skip to: 104527 + /* 21145 */ MCD_OPC_Decode, + 252, + 11, + 140, + 1, // Opcode: DUP_ZI_B + /* 21150 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 21165 + /* 21155 */ MCD_OPC_CheckPredicate, + 3, + 167, + 69, + 1, // Skip to: 104527 + /* 21160 */ MCD_OPC_Decode, + 254, + 11, + 141, + 1, // Opcode: DUP_ZI_H + /* 21165 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 21180 + /* 21170 */ MCD_OPC_CheckPredicate, + 3, + 152, + 69, + 1, // Skip to: 104527 + /* 21175 */ MCD_OPC_Decode, + 255, + 11, + 142, + 1, // Opcode: DUP_ZI_S + /* 21180 */ MCD_OPC_FilterValue, + 3, + 142, + 69, + 1, // Skip to: 104527 + /* 21185 */ MCD_OPC_CheckPredicate, + 3, + 137, + 69, + 1, // Skip to: 104527 + /* 21190 */ MCD_OPC_Decode, + 253, + 11, + 143, + 1, // Opcode: DUP_ZI_D + /* 21195 */ MCD_OPC_FilterValue, + 25, + 127, + 69, + 1, // Skip to: 104527 + /* 21200 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 21203 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 21225 + /* 21208 */ MCD_OPC_CheckPredicate, + 3, + 114, + 69, + 1, // Skip to: 104527 + /* 21213 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 107, + 69, + 1, // Skip to: 104527 + /* 21220 */ MCD_OPC_Decode, + 134, + 16, + 144, + 1, // Opcode: FDUP_ZI_H + /* 21225 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 21247 + /* 21230 */ MCD_OPC_CheckPredicate, + 3, + 92, + 69, + 1, // Skip to: 104527 + /* 21235 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 85, + 69, + 1, // Skip to: 104527 + /* 21242 */ MCD_OPC_Decode, + 135, + 16, + 144, + 1, // Opcode: FDUP_ZI_S + /* 21247 */ MCD_OPC_FilterValue, + 3, + 75, + 69, + 1, // Skip to: 104527 + /* 21252 */ MCD_OPC_CheckPredicate, + 3, + 70, + 69, + 1, // Skip to: 104527 + /* 21257 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 63, + 69, + 1, // Skip to: 104527 + /* 21264 */ MCD_OPC_Decode, + 133, + 16, + 144, + 1, // Opcode: FDUP_ZI_D + /* 21269 */ MCD_OPC_FilterValue, + 2, + 122, + 39, + 0, // Skip to: 31380 + /* 21274 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 21277 */ MCD_OPC_FilterValue, + 0, + 207, + 5, + 0, // Skip to: 22769 + /* 21282 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 21285 */ MCD_OPC_FilterValue, + 0, + 135, + 0, + 0, // Skip to: 21425 + /* 21290 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 21293 */ MCD_OPC_FilterValue, + 2, + 39, + 0, + 0, // Skip to: 21337 + /* 21298 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 21301 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 21322 + /* 21306 */ MCD_OPC_CheckPredicate, + 4, + 16, + 69, + 1, // Skip to: 104527 + /* 21311 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 9, + 69, + 1, // Skip to: 104527 + /* 21318 */ MCD_OPC_Decode, + 186, + 33, + 54, // Opcode: SQDMLALBT_ZZZ_H + /* 21322 */ MCD_OPC_FilterValue, + 1, + 0, + 69, + 1, // Skip to: 104527 + /* 21327 */ MCD_OPC_CheckPredicate, + 4, + 251, + 68, + 1, // Skip to: 104527 + /* 21332 */ MCD_OPC_Decode, + 147, + 27, + 145, + 1, // Opcode: MLA_ZZZI_H + /* 21337 */ MCD_OPC_FilterValue, + 3, + 39, + 0, + 0, // Skip to: 21381 + /* 21342 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 21345 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 21366 + /* 21350 */ MCD_OPC_CheckPredicate, + 4, + 228, + 68, + 1, // Skip to: 104527 + /* 21355 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 221, + 68, + 1, // Skip to: 104527 + /* 21362 */ MCD_OPC_Decode, + 211, + 33, + 54, // Opcode: SQDMLSLBT_ZZZ_H + /* 21366 */ MCD_OPC_FilterValue, + 1, + 212, + 68, + 1, // Skip to: 104527 + /* 21371 */ MCD_OPC_CheckPredicate, + 4, + 207, + 68, + 1, // Skip to: 104527 + /* 21376 */ MCD_OPC_Decode, + 164, + 27, + 145, + 1, // Opcode: MLS_ZZZI_H + /* 21381 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 21403 + /* 21386 */ MCD_OPC_CheckPredicate, + 4, + 192, + 68, + 1, // Skip to: 104527 + /* 21391 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 185, + 68, + 1, // Skip to: 104527 + /* 21398 */ MCD_OPC_Decode, + 192, + 34, + 145, + 1, // Opcode: SQRDMLAH_ZZZI_H + /* 21403 */ MCD_OPC_FilterValue, + 5, + 175, + 68, + 1, // Skip to: 104527 + /* 21408 */ MCD_OPC_CheckPredicate, + 4, + 170, + 68, + 1, // Skip to: 104527 + /* 21413 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 163, + 68, + 1, // Skip to: 104527 + /* 21420 */ MCD_OPC_Decode, + 211, + 34, + 145, + 1, // Opcode: SQRDMLSH_ZZZI_H + /* 21425 */ MCD_OPC_FilterValue, + 1, + 147, + 1, + 0, // Skip to: 21833 + /* 21430 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 21433 */ MCD_OPC_FilterValue, + 0, + 82, + 0, + 0, // Skip to: 21520 + /* 21438 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 21441 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 21505 + /* 21446 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 21449 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 21463 + /* 21454 */ MCD_OPC_CheckPredicate, + 3, + 124, + 68, + 1, // Skip to: 104527 + /* 21459 */ MCD_OPC_Decode, + 243, + 30, + 54, // Opcode: SDOT_ZZZ_S + /* 21463 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 21477 + /* 21468 */ MCD_OPC_CheckPredicate, + 3, + 110, + 68, + 1, // Skip to: 104527 + /* 21473 */ MCD_OPC_Decode, + 233, + 42, + 54, // Opcode: UDOT_ZZZ_S + /* 21477 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 21491 + /* 21482 */ MCD_OPC_CheckPredicate, + 4, + 96, + 68, + 1, // Skip to: 104527 + /* 21487 */ MCD_OPC_Decode, + 187, + 33, + 54, // Opcode: SQDMLALBT_ZZZ_S + /* 21491 */ MCD_OPC_FilterValue, + 3, + 87, + 68, + 1, // Skip to: 104527 + /* 21496 */ MCD_OPC_CheckPredicate, + 4, + 82, + 68, + 1, // Skip to: 104527 + /* 21501 */ MCD_OPC_Decode, + 212, + 33, + 54, // Opcode: SQDMLSLBT_ZZZ_S + /* 21505 */ MCD_OPC_FilterValue, + 1, + 73, + 68, + 1, // Skip to: 104527 + /* 21510 */ MCD_OPC_CheckPredicate, + 4, + 68, + 68, + 1, // Skip to: 104527 + /* 21515 */ MCD_OPC_Decode, + 187, + 9, + 146, + 1, // Opcode: CDOT_ZZZ_S + /* 21520 */ MCD_OPC_FilterValue, + 1, + 123, + 0, + 0, // Skip to: 21648 + /* 21525 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 21528 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 21543 + /* 21533 */ MCD_OPC_CheckPredicate, + 3, + 45, + 68, + 1, // Skip to: 104527 + /* 21538 */ MCD_OPC_Decode, + 241, + 30, + 147, + 1, // Opcode: SDOT_ZZZI_S + /* 21543 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 21558 + /* 21548 */ MCD_OPC_CheckPredicate, + 3, + 30, + 68, + 1, // Skip to: 104527 + /* 21553 */ MCD_OPC_Decode, + 231, + 42, + 147, + 1, // Opcode: UDOT_ZZZI_S + /* 21558 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 21573 + /* 21563 */ MCD_OPC_CheckPredicate, + 4, + 15, + 68, + 1, // Skip to: 104527 + /* 21568 */ MCD_OPC_Decode, + 148, + 27, + 147, + 1, // Opcode: MLA_ZZZI_S + /* 21573 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 21588 + /* 21578 */ MCD_OPC_CheckPredicate, + 4, + 0, + 68, + 1, // Skip to: 104527 + /* 21583 */ MCD_OPC_Decode, + 165, + 27, + 147, + 1, // Opcode: MLS_ZZZI_S + /* 21588 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 21603 + /* 21593 */ MCD_OPC_CheckPredicate, + 4, + 241, + 67, + 1, // Skip to: 104527 + /* 21598 */ MCD_OPC_Decode, + 193, + 34, + 147, + 1, // Opcode: SQRDMLAH_ZZZI_S + /* 21603 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 21618 + /* 21608 */ MCD_OPC_CheckPredicate, + 4, + 226, + 67, + 1, // Skip to: 104527 + /* 21613 */ MCD_OPC_Decode, + 212, + 34, + 147, + 1, // Opcode: SQRDMLSH_ZZZI_S + /* 21618 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 21633 + /* 21623 */ MCD_OPC_CheckPredicate, + 7, + 211, + 67, + 1, // Skip to: 104527 + /* 21628 */ MCD_OPC_Decode, + 150, + 46, + 147, + 1, // Opcode: USDOT_ZZZI + /* 21633 */ MCD_OPC_FilterValue, + 7, + 201, + 67, + 1, // Skip to: 104527 + /* 21638 */ MCD_OPC_CheckPredicate, + 7, + 196, + 67, + 1, // Skip to: 104527 + /* 21643 */ MCD_OPC_Decode, + 224, + 40, + 147, + 1, // Opcode: SUDOT_ZZZI + /* 21648 */ MCD_OPC_FilterValue, + 2, + 82, + 0, + 0, // Skip to: 21735 + /* 21653 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 21656 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 21720 + /* 21661 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 21664 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 21678 + /* 21669 */ MCD_OPC_CheckPredicate, + 3, + 165, + 67, + 1, // Skip to: 104527 + /* 21674 */ MCD_OPC_Decode, + 242, + 30, + 54, // Opcode: SDOT_ZZZ_D + /* 21678 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 21692 + /* 21683 */ MCD_OPC_CheckPredicate, + 3, + 151, + 67, + 1, // Skip to: 104527 + /* 21688 */ MCD_OPC_Decode, + 232, + 42, + 54, // Opcode: UDOT_ZZZ_D + /* 21692 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 21706 + /* 21697 */ MCD_OPC_CheckPredicate, + 4, + 137, + 67, + 1, // Skip to: 104527 + /* 21702 */ MCD_OPC_Decode, + 185, + 33, + 54, // Opcode: SQDMLALBT_ZZZ_D + /* 21706 */ MCD_OPC_FilterValue, + 3, + 128, + 67, + 1, // Skip to: 104527 + /* 21711 */ MCD_OPC_CheckPredicate, + 4, + 123, + 67, + 1, // Skip to: 104527 + /* 21716 */ MCD_OPC_Decode, + 210, + 33, + 54, // Opcode: SQDMLSLBT_ZZZ_D + /* 21720 */ MCD_OPC_FilterValue, + 1, + 114, + 67, + 1, // Skip to: 104527 + /* 21725 */ MCD_OPC_CheckPredicate, + 4, + 109, + 67, + 1, // Skip to: 104527 + /* 21730 */ MCD_OPC_Decode, + 186, + 9, + 146, + 1, // Opcode: CDOT_ZZZ_D + /* 21735 */ MCD_OPC_FilterValue, + 3, + 99, + 67, + 1, // Skip to: 104527 + /* 21740 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 21743 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 21758 + /* 21748 */ MCD_OPC_CheckPredicate, + 3, + 86, + 67, + 1, // Skip to: 104527 + /* 21753 */ MCD_OPC_Decode, + 240, + 30, + 148, + 1, // Opcode: SDOT_ZZZI_D + /* 21758 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 21773 + /* 21763 */ MCD_OPC_CheckPredicate, + 3, + 71, + 67, + 1, // Skip to: 104527 + /* 21768 */ MCD_OPC_Decode, + 230, + 42, + 148, + 1, // Opcode: UDOT_ZZZI_D + /* 21773 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 21788 + /* 21778 */ MCD_OPC_CheckPredicate, + 4, + 56, + 67, + 1, // Skip to: 104527 + /* 21783 */ MCD_OPC_Decode, + 146, + 27, + 148, + 1, // Opcode: MLA_ZZZI_D + /* 21788 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 21803 + /* 21793 */ MCD_OPC_CheckPredicate, + 4, + 41, + 67, + 1, // Skip to: 104527 + /* 21798 */ MCD_OPC_Decode, + 163, + 27, + 148, + 1, // Opcode: MLS_ZZZI_D + /* 21803 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 21818 + /* 21808 */ MCD_OPC_CheckPredicate, + 4, + 26, + 67, + 1, // Skip to: 104527 + /* 21813 */ MCD_OPC_Decode, + 191, + 34, + 148, + 1, // Opcode: SQRDMLAH_ZZZI_D + /* 21818 */ MCD_OPC_FilterValue, + 5, + 16, + 67, + 1, // Skip to: 104527 + /* 21823 */ MCD_OPC_CheckPredicate, + 4, + 11, + 67, + 1, // Skip to: 104527 + /* 21828 */ MCD_OPC_Decode, + 210, + 34, + 148, + 1, // Opcode: SQRDMLSH_ZZZI_D + /* 21833 */ MCD_OPC_FilterValue, + 2, + 123, + 2, + 0, // Skip to: 22473 + /* 21838 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 21841 */ MCD_OPC_FilterValue, + 0, + 74, + 0, + 0, // Skip to: 21920 + /* 21846 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 21849 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 21892 + /* 21854 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 21857 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 21878 + /* 21862 */ MCD_OPC_CheckPredicate, + 4, + 228, + 66, + 1, // Skip to: 104527 + /* 21867 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 221, + 66, + 1, // Skip to: 104527 + /* 21874 */ MCD_OPC_Decode, + 233, + 35, + 77, // Opcode: SQSHRUNB_ZZI_B + /* 21878 */ MCD_OPC_FilterValue, + 1, + 212, + 66, + 1, // Skip to: 104527 + /* 21883 */ MCD_OPC_CheckPredicate, + 4, + 207, + 66, + 1, // Skip to: 104527 + /* 21888 */ MCD_OPC_Decode, + 234, + 35, + 78, // Opcode: SQSHRUNB_ZZI_H + /* 21892 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 21906 + /* 21897 */ MCD_OPC_CheckPredicate, + 4, + 193, + 66, + 1, // Skip to: 104527 + /* 21902 */ MCD_OPC_Decode, + 147, + 30, + 45, // Opcode: SADDLB_ZZZ_H + /* 21906 */ MCD_OPC_FilterValue, + 3, + 184, + 66, + 1, // Skip to: 104527 + /* 21911 */ MCD_OPC_CheckPredicate, + 4, + 179, + 66, + 1, // Skip to: 104527 + /* 21916 */ MCD_OPC_Decode, + 235, + 35, + 79, // Opcode: SQSHRUNB_ZZI_S + /* 21920 */ MCD_OPC_FilterValue, + 1, + 74, + 0, + 0, // Skip to: 21999 + /* 21925 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 21928 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 21971 + /* 21933 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 21936 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 21957 + /* 21941 */ MCD_OPC_CheckPredicate, + 4, + 149, + 66, + 1, // Skip to: 104527 + /* 21946 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 142, + 66, + 1, // Skip to: 104527 + /* 21953 */ MCD_OPC_Decode, + 236, + 35, + 55, // Opcode: SQSHRUNT_ZZI_B + /* 21957 */ MCD_OPC_FilterValue, + 1, + 133, + 66, + 1, // Skip to: 104527 + /* 21962 */ MCD_OPC_CheckPredicate, + 4, + 128, + 66, + 1, // Skip to: 104527 + /* 21967 */ MCD_OPC_Decode, + 237, + 35, + 56, // Opcode: SQSHRUNT_ZZI_H + /* 21971 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 21985 + /* 21976 */ MCD_OPC_CheckPredicate, + 4, + 114, + 66, + 1, // Skip to: 104527 + /* 21981 */ MCD_OPC_Decode, + 156, + 30, + 45, // Opcode: SADDLT_ZZZ_H + /* 21985 */ MCD_OPC_FilterValue, + 3, + 105, + 66, + 1, // Skip to: 104527 + /* 21990 */ MCD_OPC_CheckPredicate, + 4, + 100, + 66, + 1, // Skip to: 104527 + /* 21995 */ MCD_OPC_Decode, + 238, + 35, + 57, // Opcode: SQSHRUNT_ZZI_S + /* 21999 */ MCD_OPC_FilterValue, + 2, + 74, + 0, + 0, // Skip to: 22078 + /* 22004 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22007 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 22050 + /* 22012 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 22015 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 22036 + /* 22020 */ MCD_OPC_CheckPredicate, + 4, + 70, + 66, + 1, // Skip to: 104527 + /* 22025 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 63, + 66, + 1, // Skip to: 104527 + /* 22032 */ MCD_OPC_Decode, + 154, + 35, + 77, // Opcode: SQRSHRUNB_ZZI_B + /* 22036 */ MCD_OPC_FilterValue, + 1, + 54, + 66, + 1, // Skip to: 104527 + /* 22041 */ MCD_OPC_CheckPredicate, + 4, + 49, + 66, + 1, // Skip to: 104527 + /* 22046 */ MCD_OPC_Decode, + 155, + 35, + 78, // Opcode: SQRSHRUNB_ZZI_H + /* 22050 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 22064 + /* 22055 */ MCD_OPC_CheckPredicate, + 4, + 35, + 66, + 1, // Skip to: 104527 + /* 22060 */ MCD_OPC_Decode, + 144, + 42, + 45, // Opcode: UADDLB_ZZZ_H + /* 22064 */ MCD_OPC_FilterValue, + 3, + 26, + 66, + 1, // Skip to: 104527 + /* 22069 */ MCD_OPC_CheckPredicate, + 4, + 21, + 66, + 1, // Skip to: 104527 + /* 22074 */ MCD_OPC_Decode, + 156, + 35, + 79, // Opcode: SQRSHRUNB_ZZI_S + /* 22078 */ MCD_OPC_FilterValue, + 3, + 74, + 0, + 0, // Skip to: 22157 + /* 22083 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22086 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 22129 + /* 22091 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 22094 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 22115 + /* 22099 */ MCD_OPC_CheckPredicate, + 4, + 247, + 65, + 1, // Skip to: 104527 + /* 22104 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 240, + 65, + 1, // Skip to: 104527 + /* 22111 */ MCD_OPC_Decode, + 157, + 35, + 55, // Opcode: SQRSHRUNT_ZZI_B + /* 22115 */ MCD_OPC_FilterValue, + 1, + 231, + 65, + 1, // Skip to: 104527 + /* 22120 */ MCD_OPC_CheckPredicate, + 4, + 226, + 65, + 1, // Skip to: 104527 + /* 22125 */ MCD_OPC_Decode, + 158, + 35, + 56, // Opcode: SQRSHRUNT_ZZI_H + /* 22129 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 22143 + /* 22134 */ MCD_OPC_CheckPredicate, + 4, + 212, + 65, + 1, // Skip to: 104527 + /* 22139 */ MCD_OPC_Decode, + 153, + 42, + 45, // Opcode: UADDLT_ZZZ_H + /* 22143 */ MCD_OPC_FilterValue, + 3, + 203, + 65, + 1, // Skip to: 104527 + /* 22148 */ MCD_OPC_CheckPredicate, + 4, + 198, + 65, + 1, // Skip to: 104527 + /* 22153 */ MCD_OPC_Decode, + 159, + 35, + 57, // Opcode: SQRSHRUNT_ZZI_S + /* 22157 */ MCD_OPC_FilterValue, + 4, + 74, + 0, + 0, // Skip to: 22236 + /* 22162 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22165 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 22208 + /* 22170 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 22173 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 22194 + /* 22178 */ MCD_OPC_CheckPredicate, + 4, + 168, + 65, + 1, // Skip to: 104527 + /* 22183 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 161, + 65, + 1, // Skip to: 104527 + /* 22190 */ MCD_OPC_Decode, + 166, + 31, + 77, // Opcode: SHRNB_ZZI_B + /* 22194 */ MCD_OPC_FilterValue, + 1, + 152, + 65, + 1, // Skip to: 104527 + /* 22199 */ MCD_OPC_CheckPredicate, + 4, + 147, + 65, + 1, // Skip to: 104527 + /* 22204 */ MCD_OPC_Decode, + 167, + 31, + 78, // Opcode: SHRNB_ZZI_H + /* 22208 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 22222 + /* 22213 */ MCD_OPC_CheckPredicate, + 4, + 133, + 65, + 1, // Skip to: 104527 + /* 22218 */ MCD_OPC_Decode, + 193, + 37, + 45, // Opcode: SSUBLB_ZZZ_H + /* 22222 */ MCD_OPC_FilterValue, + 3, + 124, + 65, + 1, // Skip to: 104527 + /* 22227 */ MCD_OPC_CheckPredicate, + 4, + 119, + 65, + 1, // Skip to: 104527 + /* 22232 */ MCD_OPC_Decode, + 168, + 31, + 79, // Opcode: SHRNB_ZZI_S + /* 22236 */ MCD_OPC_FilterValue, + 5, + 74, + 0, + 0, // Skip to: 22315 + /* 22241 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22244 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 22287 + /* 22249 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 22252 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 22273 + /* 22257 */ MCD_OPC_CheckPredicate, + 4, + 89, + 65, + 1, // Skip to: 104527 + /* 22262 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 82, + 65, + 1, // Skip to: 104527 + /* 22269 */ MCD_OPC_Decode, + 169, + 31, + 55, // Opcode: SHRNT_ZZI_B + /* 22273 */ MCD_OPC_FilterValue, + 1, + 73, + 65, + 1, // Skip to: 104527 + /* 22278 */ MCD_OPC_CheckPredicate, + 4, + 68, + 65, + 1, // Skip to: 104527 + /* 22283 */ MCD_OPC_Decode, + 170, + 31, + 56, // Opcode: SHRNT_ZZI_H + /* 22287 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 22301 + /* 22292 */ MCD_OPC_CheckPredicate, + 4, + 54, + 65, + 1, // Skip to: 104527 + /* 22297 */ MCD_OPC_Decode, + 199, + 37, + 45, // Opcode: SSUBLT_ZZZ_H + /* 22301 */ MCD_OPC_FilterValue, + 3, + 45, + 65, + 1, // Skip to: 104527 + /* 22306 */ MCD_OPC_CheckPredicate, + 4, + 40, + 65, + 1, // Skip to: 104527 + /* 22311 */ MCD_OPC_Decode, + 171, + 31, + 57, // Opcode: SHRNT_ZZI_S + /* 22315 */ MCD_OPC_FilterValue, + 6, + 74, + 0, + 0, // Skip to: 22394 + /* 22320 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22323 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 22366 + /* 22328 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 22331 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 22352 + /* 22336 */ MCD_OPC_CheckPredicate, + 4, + 10, + 65, + 1, // Skip to: 104527 + /* 22341 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 3, + 65, + 1, // Skip to: 104527 + /* 22348 */ MCD_OPC_Decode, + 194, + 29, + 77, // Opcode: RSHRNB_ZZI_B + /* 22352 */ MCD_OPC_FilterValue, + 1, + 250, + 64, + 1, // Skip to: 104527 + /* 22357 */ MCD_OPC_CheckPredicate, + 4, + 245, + 64, + 1, // Skip to: 104527 + /* 22362 */ MCD_OPC_Decode, + 195, + 29, + 78, // Opcode: RSHRNB_ZZI_H + /* 22366 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 22380 + /* 22371 */ MCD_OPC_CheckPredicate, + 4, + 231, + 64, + 1, // Skip to: 104527 + /* 22376 */ MCD_OPC_Decode, + 217, + 46, + 45, // Opcode: USUBLB_ZZZ_H + /* 22380 */ MCD_OPC_FilterValue, + 3, + 222, + 64, + 1, // Skip to: 104527 + /* 22385 */ MCD_OPC_CheckPredicate, + 4, + 217, + 64, + 1, // Skip to: 104527 + /* 22390 */ MCD_OPC_Decode, + 196, + 29, + 79, // Opcode: RSHRNB_ZZI_S + /* 22394 */ MCD_OPC_FilterValue, + 7, + 208, + 64, + 1, // Skip to: 104527 + /* 22399 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22402 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 22445 + /* 22407 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 22410 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 22431 + /* 22415 */ MCD_OPC_CheckPredicate, + 4, + 187, + 64, + 1, // Skip to: 104527 + /* 22420 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 180, + 64, + 1, // Skip to: 104527 + /* 22427 */ MCD_OPC_Decode, + 197, + 29, + 55, // Opcode: RSHRNT_ZZI_B + /* 22431 */ MCD_OPC_FilterValue, + 1, + 171, + 64, + 1, // Skip to: 104527 + /* 22436 */ MCD_OPC_CheckPredicate, + 4, + 166, + 64, + 1, // Skip to: 104527 + /* 22441 */ MCD_OPC_Decode, + 198, + 29, + 56, // Opcode: RSHRNT_ZZI_H + /* 22445 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 22459 + /* 22450 */ MCD_OPC_CheckPredicate, + 4, + 152, + 64, + 1, // Skip to: 104527 + /* 22455 */ MCD_OPC_Decode, + 220, + 46, + 45, // Opcode: USUBLT_ZZZ_H + /* 22459 */ MCD_OPC_FilterValue, + 3, + 143, + 64, + 1, // Skip to: 104527 + /* 22464 */ MCD_OPC_CheckPredicate, + 4, + 138, + 64, + 1, // Skip to: 104527 + /* 22469 */ MCD_OPC_Decode, + 199, + 29, + 57, // Opcode: RSHRNT_ZZI_S + /* 22473 */ MCD_OPC_FilterValue, + 3, + 129, + 64, + 1, // Skip to: 104527 + /* 22478 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 22481 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 22517 + /* 22486 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22489 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 22503 + /* 22494 */ MCD_OPC_CheckPredicate, + 4, + 108, + 64, + 1, // Skip to: 104527 + /* 22499 */ MCD_OPC_Decode, + 148, + 30, + 45, // Opcode: SADDLB_ZZZ_S + /* 22503 */ MCD_OPC_FilterValue, + 2, + 99, + 64, + 1, // Skip to: 104527 + /* 22508 */ MCD_OPC_CheckPredicate, + 4, + 94, + 64, + 1, // Skip to: 104527 + /* 22513 */ MCD_OPC_Decode, + 146, + 30, + 45, // Opcode: SADDLB_ZZZ_D + /* 22517 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 22553 + /* 22522 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22525 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 22539 + /* 22530 */ MCD_OPC_CheckPredicate, + 4, + 72, + 64, + 1, // Skip to: 104527 + /* 22535 */ MCD_OPC_Decode, + 157, + 30, + 45, // Opcode: SADDLT_ZZZ_S + /* 22539 */ MCD_OPC_FilterValue, + 2, + 63, + 64, + 1, // Skip to: 104527 + /* 22544 */ MCD_OPC_CheckPredicate, + 4, + 58, + 64, + 1, // Skip to: 104527 + /* 22549 */ MCD_OPC_Decode, + 155, + 30, + 45, // Opcode: SADDLT_ZZZ_D + /* 22553 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 22589 + /* 22558 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22561 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 22575 + /* 22566 */ MCD_OPC_CheckPredicate, + 4, + 36, + 64, + 1, // Skip to: 104527 + /* 22571 */ MCD_OPC_Decode, + 145, + 42, + 45, // Opcode: UADDLB_ZZZ_S + /* 22575 */ MCD_OPC_FilterValue, + 2, + 27, + 64, + 1, // Skip to: 104527 + /* 22580 */ MCD_OPC_CheckPredicate, + 4, + 22, + 64, + 1, // Skip to: 104527 + /* 22585 */ MCD_OPC_Decode, + 143, + 42, + 45, // Opcode: UADDLB_ZZZ_D + /* 22589 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 22625 + /* 22594 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22597 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 22611 + /* 22602 */ MCD_OPC_CheckPredicate, + 4, + 0, + 64, + 1, // Skip to: 104527 + /* 22607 */ MCD_OPC_Decode, + 154, + 42, + 45, // Opcode: UADDLT_ZZZ_S + /* 22611 */ MCD_OPC_FilterValue, + 2, + 247, + 63, + 1, // Skip to: 104527 + /* 22616 */ MCD_OPC_CheckPredicate, + 4, + 242, + 63, + 1, // Skip to: 104527 + /* 22621 */ MCD_OPC_Decode, + 152, + 42, + 45, // Opcode: UADDLT_ZZZ_D + /* 22625 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 22661 + /* 22630 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22633 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 22647 + /* 22638 */ MCD_OPC_CheckPredicate, + 4, + 220, + 63, + 1, // Skip to: 104527 + /* 22643 */ MCD_OPC_Decode, + 194, + 37, + 45, // Opcode: SSUBLB_ZZZ_S + /* 22647 */ MCD_OPC_FilterValue, + 2, + 211, + 63, + 1, // Skip to: 104527 + /* 22652 */ MCD_OPC_CheckPredicate, + 4, + 206, + 63, + 1, // Skip to: 104527 + /* 22657 */ MCD_OPC_Decode, + 192, + 37, + 45, // Opcode: SSUBLB_ZZZ_D + /* 22661 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 22697 + /* 22666 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22669 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 22683 + /* 22674 */ MCD_OPC_CheckPredicate, + 4, + 184, + 63, + 1, // Skip to: 104527 + /* 22679 */ MCD_OPC_Decode, + 200, + 37, + 45, // Opcode: SSUBLT_ZZZ_S + /* 22683 */ MCD_OPC_FilterValue, + 2, + 175, + 63, + 1, // Skip to: 104527 + /* 22688 */ MCD_OPC_CheckPredicate, + 4, + 170, + 63, + 1, // Skip to: 104527 + /* 22693 */ MCD_OPC_Decode, + 198, + 37, + 45, // Opcode: SSUBLT_ZZZ_D + /* 22697 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 22733 + /* 22702 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22705 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 22719 + /* 22710 */ MCD_OPC_CheckPredicate, + 4, + 148, + 63, + 1, // Skip to: 104527 + /* 22715 */ MCD_OPC_Decode, + 218, + 46, + 45, // Opcode: USUBLB_ZZZ_S + /* 22719 */ MCD_OPC_FilterValue, + 2, + 139, + 63, + 1, // Skip to: 104527 + /* 22724 */ MCD_OPC_CheckPredicate, + 4, + 134, + 63, + 1, // Skip to: 104527 + /* 22729 */ MCD_OPC_Decode, + 216, + 46, + 45, // Opcode: USUBLB_ZZZ_D + /* 22733 */ MCD_OPC_FilterValue, + 7, + 125, + 63, + 1, // Skip to: 104527 + /* 22738 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 22741 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 22755 + /* 22746 */ MCD_OPC_CheckPredicate, + 4, + 112, + 63, + 1, // Skip to: 104527 + /* 22751 */ MCD_OPC_Decode, + 221, + 46, + 45, // Opcode: USUBLT_ZZZ_S + /* 22755 */ MCD_OPC_FilterValue, + 2, + 103, + 63, + 1, // Skip to: 104527 + /* 22760 */ MCD_OPC_CheckPredicate, + 4, + 98, + 63, + 1, // Skip to: 104527 + /* 22765 */ MCD_OPC_Decode, + 219, + 46, + 45, // Opcode: USUBLT_ZZZ_D + /* 22769 */ MCD_OPC_FilterValue, + 1, + 219, + 3, + 0, // Skip to: 23761 + /* 22774 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 22777 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 22815 + /* 22782 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 22785 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 22800 + /* 22790 */ MCD_OPC_CheckPredicate, + 4, + 68, + 63, + 1, // Skip to: 104527 + /* 22795 */ MCD_OPC_Decode, + 176, + 10, + 146, + 1, // Opcode: CMLA_ZZZ_B + /* 22800 */ MCD_OPC_FilterValue, + 1, + 58, + 63, + 1, // Skip to: 104527 + /* 22805 */ MCD_OPC_CheckPredicate, + 4, + 53, + 63, + 1, // Skip to: 104527 + /* 22810 */ MCD_OPC_Decode, + 187, + 34, + 146, + 1, // Opcode: SQRDCMLAH_ZZZ_B + /* 22815 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 22853 + /* 22820 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 22823 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 22838 + /* 22828 */ MCD_OPC_CheckPredicate, + 4, + 30, + 63, + 1, // Skip to: 104527 + /* 22833 */ MCD_OPC_Decode, + 178, + 10, + 146, + 1, // Opcode: CMLA_ZZZ_H + /* 22838 */ MCD_OPC_FilterValue, + 1, + 20, + 63, + 1, // Skip to: 104527 + /* 22843 */ MCD_OPC_CheckPredicate, + 4, + 15, + 63, + 1, // Skip to: 104527 + /* 22848 */ MCD_OPC_Decode, + 189, + 34, + 146, + 1, // Opcode: SQRDCMLAH_ZZZ_H + /* 22853 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 22891 + /* 22858 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 22861 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 22876 + /* 22866 */ MCD_OPC_CheckPredicate, + 4, + 248, + 62, + 1, // Skip to: 104527 + /* 22871 */ MCD_OPC_Decode, + 179, + 10, + 146, + 1, // Opcode: CMLA_ZZZ_S + /* 22876 */ MCD_OPC_FilterValue, + 1, + 238, + 62, + 1, // Skip to: 104527 + /* 22881 */ MCD_OPC_CheckPredicate, + 4, + 233, + 62, + 1, // Skip to: 104527 + /* 22886 */ MCD_OPC_Decode, + 190, + 34, + 146, + 1, // Opcode: SQRDCMLAH_ZZZ_S + /* 22891 */ MCD_OPC_FilterValue, + 5, + 79, + 0, + 0, // Skip to: 22975 + /* 22896 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 22899 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 22937 + /* 22904 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 22907 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 22922 + /* 22912 */ MCD_OPC_CheckPredicate, + 4, + 202, + 62, + 1, // Skip to: 104527 + /* 22917 */ MCD_OPC_Decode, + 189, + 33, + 149, + 1, // Opcode: SQDMLALB_ZZZI_S + /* 22922 */ MCD_OPC_FilterValue, + 1, + 192, + 62, + 1, // Skip to: 104527 + /* 22927 */ MCD_OPC_CheckPredicate, + 4, + 187, + 62, + 1, // Skip to: 104527 + /* 22932 */ MCD_OPC_Decode, + 214, + 33, + 149, + 1, // Opcode: SQDMLSLB_ZZZI_S + /* 22937 */ MCD_OPC_FilterValue, + 1, + 177, + 62, + 1, // Skip to: 104527 + /* 22942 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 22945 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 22960 + /* 22950 */ MCD_OPC_CheckPredicate, + 4, + 164, + 62, + 1, // Skip to: 104527 + /* 22955 */ MCD_OPC_Decode, + 194, + 33, + 149, + 1, // Opcode: SQDMLALT_ZZZI_S + /* 22960 */ MCD_OPC_FilterValue, + 1, + 154, + 62, + 1, // Skip to: 104527 + /* 22965 */ MCD_OPC_CheckPredicate, + 4, + 149, + 62, + 1, // Skip to: 104527 + /* 22970 */ MCD_OPC_Decode, + 219, + 33, + 149, + 1, // Opcode: SQDMLSLT_ZZZI_S + /* 22975 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 23013 + /* 22980 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 22983 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 22998 + /* 22988 */ MCD_OPC_CheckPredicate, + 4, + 126, + 62, + 1, // Skip to: 104527 + /* 22993 */ MCD_OPC_Decode, + 177, + 10, + 146, + 1, // Opcode: CMLA_ZZZ_D + /* 22998 */ MCD_OPC_FilterValue, + 1, + 116, + 62, + 1, // Skip to: 104527 + /* 23003 */ MCD_OPC_CheckPredicate, + 4, + 111, + 62, + 1, // Skip to: 104527 + /* 23008 */ MCD_OPC_Decode, + 188, + 34, + 146, + 1, // Opcode: SQRDCMLAH_ZZZ_D + /* 23013 */ MCD_OPC_FilterValue, + 7, + 79, + 0, + 0, // Skip to: 23097 + /* 23018 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 23021 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 23059 + /* 23026 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 23029 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 23044 + /* 23034 */ MCD_OPC_CheckPredicate, + 4, + 80, + 62, + 1, // Skip to: 104527 + /* 23039 */ MCD_OPC_Decode, + 188, + 33, + 150, + 1, // Opcode: SQDMLALB_ZZZI_D + /* 23044 */ MCD_OPC_FilterValue, + 1, + 70, + 62, + 1, // Skip to: 104527 + /* 23049 */ MCD_OPC_CheckPredicate, + 4, + 65, + 62, + 1, // Skip to: 104527 + /* 23054 */ MCD_OPC_Decode, + 213, + 33, + 150, + 1, // Opcode: SQDMLSLB_ZZZI_D + /* 23059 */ MCD_OPC_FilterValue, + 1, + 55, + 62, + 1, // Skip to: 104527 + /* 23064 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 23067 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 23082 + /* 23072 */ MCD_OPC_CheckPredicate, + 4, + 42, + 62, + 1, // Skip to: 104527 + /* 23077 */ MCD_OPC_Decode, + 193, + 33, + 150, + 1, // Opcode: SQDMLALT_ZZZI_D + /* 23082 */ MCD_OPC_FilterValue, + 1, + 32, + 62, + 1, // Skip to: 104527 + /* 23087 */ MCD_OPC_CheckPredicate, + 4, + 27, + 62, + 1, // Skip to: 104527 + /* 23092 */ MCD_OPC_Decode, + 218, + 33, + 150, + 1, // Opcode: SQDMLSLT_ZZZI_D + /* 23097 */ MCD_OPC_FilterValue, + 9, + 91, + 1, + 0, // Skip to: 23449 + /* 23102 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 23105 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 23148 + /* 23110 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 23113 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 23134 + /* 23118 */ MCD_OPC_CheckPredicate, + 4, + 252, + 61, + 1, // Skip to: 104527 + /* 23123 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 245, + 61, + 1, // Skip to: 104527 + /* 23130 */ MCD_OPC_Decode, + 218, + 35, + 77, // Opcode: SQSHRNB_ZZI_B + /* 23134 */ MCD_OPC_FilterValue, + 1, + 236, + 61, + 1, // Skip to: 104527 + /* 23139 */ MCD_OPC_CheckPredicate, + 4, + 231, + 61, + 1, // Skip to: 104527 + /* 23144 */ MCD_OPC_Decode, + 219, + 35, + 78, // Opcode: SQSHRNB_ZZI_H + /* 23148 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 23191 + /* 23153 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 23156 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 23177 + /* 23161 */ MCD_OPC_CheckPredicate, + 4, + 209, + 61, + 1, // Skip to: 104527 + /* 23166 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 202, + 61, + 1, // Skip to: 104527 + /* 23173 */ MCD_OPC_Decode, + 221, + 35, + 55, // Opcode: SQSHRNT_ZZI_B + /* 23177 */ MCD_OPC_FilterValue, + 1, + 193, + 61, + 1, // Skip to: 104527 + /* 23182 */ MCD_OPC_CheckPredicate, + 4, + 188, + 61, + 1, // Skip to: 104527 + /* 23187 */ MCD_OPC_Decode, + 222, + 35, + 56, // Opcode: SQSHRNT_ZZI_H + /* 23191 */ MCD_OPC_FilterValue, + 2, + 38, + 0, + 0, // Skip to: 23234 + /* 23196 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 23199 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 23220 + /* 23204 */ MCD_OPC_CheckPredicate, + 4, + 166, + 61, + 1, // Skip to: 104527 + /* 23209 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 159, + 61, + 1, // Skip to: 104527 + /* 23216 */ MCD_OPC_Decode, + 139, + 35, + 77, // Opcode: SQRSHRNB_ZZI_B + /* 23220 */ MCD_OPC_FilterValue, + 1, + 150, + 61, + 1, // Skip to: 104527 + /* 23225 */ MCD_OPC_CheckPredicate, + 4, + 145, + 61, + 1, // Skip to: 104527 + /* 23230 */ MCD_OPC_Decode, + 140, + 35, + 78, // Opcode: SQRSHRNB_ZZI_H + /* 23234 */ MCD_OPC_FilterValue, + 3, + 38, + 0, + 0, // Skip to: 23277 + /* 23239 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 23242 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 23263 + /* 23247 */ MCD_OPC_CheckPredicate, + 4, + 123, + 61, + 1, // Skip to: 104527 + /* 23252 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 116, + 61, + 1, // Skip to: 104527 + /* 23259 */ MCD_OPC_Decode, + 142, + 35, + 55, // Opcode: SQRSHRNT_ZZI_B + /* 23263 */ MCD_OPC_FilterValue, + 1, + 107, + 61, + 1, // Skip to: 104527 + /* 23268 */ MCD_OPC_CheckPredicate, + 4, + 102, + 61, + 1, // Skip to: 104527 + /* 23273 */ MCD_OPC_Decode, + 143, + 35, + 56, // Opcode: SQRSHRNT_ZZI_H + /* 23277 */ MCD_OPC_FilterValue, + 4, + 38, + 0, + 0, // Skip to: 23320 + /* 23282 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 23285 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 23306 + /* 23290 */ MCD_OPC_CheckPredicate, + 4, + 80, + 61, + 1, // Skip to: 104527 + /* 23295 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 73, + 61, + 1, // Skip to: 104527 + /* 23302 */ MCD_OPC_Decode, + 164, + 45, + 77, // Opcode: UQSHRNB_ZZI_B + /* 23306 */ MCD_OPC_FilterValue, + 1, + 64, + 61, + 1, // Skip to: 104527 + /* 23311 */ MCD_OPC_CheckPredicate, + 4, + 59, + 61, + 1, // Skip to: 104527 + /* 23316 */ MCD_OPC_Decode, + 165, + 45, + 78, // Opcode: UQSHRNB_ZZI_H + /* 23320 */ MCD_OPC_FilterValue, + 5, + 38, + 0, + 0, // Skip to: 23363 + /* 23325 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 23328 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 23349 + /* 23333 */ MCD_OPC_CheckPredicate, + 4, + 37, + 61, + 1, // Skip to: 104527 + /* 23338 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 30, + 61, + 1, // Skip to: 104527 + /* 23345 */ MCD_OPC_Decode, + 167, + 45, + 55, // Opcode: UQSHRNT_ZZI_B + /* 23349 */ MCD_OPC_FilterValue, + 1, + 21, + 61, + 1, // Skip to: 104527 + /* 23354 */ MCD_OPC_CheckPredicate, + 4, + 16, + 61, + 1, // Skip to: 104527 + /* 23359 */ MCD_OPC_Decode, + 168, + 45, + 56, // Opcode: UQSHRNT_ZZI_H + /* 23363 */ MCD_OPC_FilterValue, + 6, + 38, + 0, + 0, // Skip to: 23406 + /* 23368 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 23371 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 23392 + /* 23376 */ MCD_OPC_CheckPredicate, + 4, + 250, + 60, + 1, // Skip to: 104527 + /* 23381 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 243, + 60, + 1, // Skip to: 104527 + /* 23388 */ MCD_OPC_Decode, + 243, + 44, + 77, // Opcode: UQRSHRNB_ZZI_B + /* 23392 */ MCD_OPC_FilterValue, + 1, + 234, + 60, + 1, // Skip to: 104527 + /* 23397 */ MCD_OPC_CheckPredicate, + 4, + 229, + 60, + 1, // Skip to: 104527 + /* 23402 */ MCD_OPC_Decode, + 244, + 44, + 78, // Opcode: UQRSHRNB_ZZI_H + /* 23406 */ MCD_OPC_FilterValue, + 7, + 220, + 60, + 1, // Skip to: 104527 + /* 23411 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 23414 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 23435 + /* 23419 */ MCD_OPC_CheckPredicate, + 4, + 207, + 60, + 1, // Skip to: 104527 + /* 23424 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 200, + 60, + 1, // Skip to: 104527 + /* 23431 */ MCD_OPC_Decode, + 246, + 44, + 55, // Opcode: UQRSHRNT_ZZI_B + /* 23435 */ MCD_OPC_FilterValue, + 1, + 191, + 60, + 1, // Skip to: 104527 + /* 23440 */ MCD_OPC_CheckPredicate, + 4, + 186, + 60, + 1, // Skip to: 104527 + /* 23445 */ MCD_OPC_Decode, + 247, + 44, + 56, // Opcode: UQRSHRNT_ZZI_H + /* 23449 */ MCD_OPC_FilterValue, + 10, + 59, + 0, + 0, // Skip to: 23513 + /* 23454 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 23457 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 23471 + /* 23462 */ MCD_OPC_CheckPredicate, + 4, + 164, + 60, + 1, // Skip to: 104527 + /* 23467 */ MCD_OPC_Decode, + 241, + 29, + 45, // Opcode: SABDLB_ZZZ_H + /* 23471 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 23485 + /* 23476 */ MCD_OPC_CheckPredicate, + 4, + 150, + 60, + 1, // Skip to: 104527 + /* 23481 */ MCD_OPC_Decode, + 244, + 29, + 45, // Opcode: SABDLT_ZZZ_H + /* 23485 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 23499 + /* 23490 */ MCD_OPC_CheckPredicate, + 4, + 136, + 60, + 1, // Skip to: 104527 + /* 23495 */ MCD_OPC_Decode, + 241, + 41, + 45, // Opcode: UABDLB_ZZZ_H + /* 23499 */ MCD_OPC_FilterValue, + 7, + 127, + 60, + 1, // Skip to: 104527 + /* 23504 */ MCD_OPC_CheckPredicate, + 4, + 122, + 60, + 1, // Skip to: 104527 + /* 23509 */ MCD_OPC_Decode, + 244, + 41, + 45, // Opcode: UABDLT_ZZZ_H + /* 23513 */ MCD_OPC_FilterValue, + 11, + 115, + 0, + 0, // Skip to: 23633 + /* 23518 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 23521 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 23535 + /* 23526 */ MCD_OPC_CheckPredicate, + 4, + 100, + 60, + 1, // Skip to: 104527 + /* 23531 */ MCD_OPC_Decode, + 220, + 35, + 79, // Opcode: SQSHRNB_ZZI_S + /* 23535 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 23549 + /* 23540 */ MCD_OPC_CheckPredicate, + 4, + 86, + 60, + 1, // Skip to: 104527 + /* 23545 */ MCD_OPC_Decode, + 223, + 35, + 57, // Opcode: SQSHRNT_ZZI_S + /* 23549 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 23563 + /* 23554 */ MCD_OPC_CheckPredicate, + 4, + 72, + 60, + 1, // Skip to: 104527 + /* 23559 */ MCD_OPC_Decode, + 141, + 35, + 79, // Opcode: SQRSHRNB_ZZI_S + /* 23563 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 23577 + /* 23568 */ MCD_OPC_CheckPredicate, + 4, + 58, + 60, + 1, // Skip to: 104527 + /* 23573 */ MCD_OPC_Decode, + 144, + 35, + 57, // Opcode: SQRSHRNT_ZZI_S + /* 23577 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 23591 + /* 23582 */ MCD_OPC_CheckPredicate, + 4, + 44, + 60, + 1, // Skip to: 104527 + /* 23587 */ MCD_OPC_Decode, + 166, + 45, + 79, // Opcode: UQSHRNB_ZZI_S + /* 23591 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 23605 + /* 23596 */ MCD_OPC_CheckPredicate, + 4, + 30, + 60, + 1, // Skip to: 104527 + /* 23601 */ MCD_OPC_Decode, + 169, + 45, + 57, // Opcode: UQSHRNT_ZZI_S + /* 23605 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 23619 + /* 23610 */ MCD_OPC_CheckPredicate, + 4, + 16, + 60, + 1, // Skip to: 104527 + /* 23615 */ MCD_OPC_Decode, + 245, + 44, + 79, // Opcode: UQRSHRNB_ZZI_S + /* 23619 */ MCD_OPC_FilterValue, + 7, + 7, + 60, + 1, // Skip to: 104527 + /* 23624 */ MCD_OPC_CheckPredicate, + 4, + 2, + 60, + 1, // Skip to: 104527 + /* 23629 */ MCD_OPC_Decode, + 248, + 44, + 57, // Opcode: UQRSHRNT_ZZI_S + /* 23633 */ MCD_OPC_FilterValue, + 12, + 59, + 0, + 0, // Skip to: 23697 + /* 23638 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 23641 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 23655 + /* 23646 */ MCD_OPC_CheckPredicate, + 4, + 236, + 59, + 1, // Skip to: 104527 + /* 23651 */ MCD_OPC_Decode, + 242, + 29, + 45, // Opcode: SABDLB_ZZZ_S + /* 23655 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 23669 + /* 23660 */ MCD_OPC_CheckPredicate, + 4, + 222, + 59, + 1, // Skip to: 104527 + /* 23665 */ MCD_OPC_Decode, + 245, + 29, + 45, // Opcode: SABDLT_ZZZ_S + /* 23669 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 23683 + /* 23674 */ MCD_OPC_CheckPredicate, + 4, + 208, + 59, + 1, // Skip to: 104527 + /* 23679 */ MCD_OPC_Decode, + 242, + 41, + 45, // Opcode: UABDLB_ZZZ_S + /* 23683 */ MCD_OPC_FilterValue, + 7, + 199, + 59, + 1, // Skip to: 104527 + /* 23688 */ MCD_OPC_CheckPredicate, + 4, + 194, + 59, + 1, // Skip to: 104527 + /* 23693 */ MCD_OPC_Decode, + 245, + 41, + 45, // Opcode: UABDLT_ZZZ_S + /* 23697 */ MCD_OPC_FilterValue, + 14, + 185, + 59, + 1, // Skip to: 104527 + /* 23702 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 23705 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 23719 + /* 23710 */ MCD_OPC_CheckPredicate, + 4, + 172, + 59, + 1, // Skip to: 104527 + /* 23715 */ MCD_OPC_Decode, + 240, + 29, + 45, // Opcode: SABDLB_ZZZ_D + /* 23719 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 23733 + /* 23724 */ MCD_OPC_CheckPredicate, + 4, + 158, + 59, + 1, // Skip to: 104527 + /* 23729 */ MCD_OPC_Decode, + 243, + 29, + 45, // Opcode: SABDLT_ZZZ_D + /* 23733 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 23747 + /* 23738 */ MCD_OPC_CheckPredicate, + 4, + 144, + 59, + 1, // Skip to: 104527 + /* 23743 */ MCD_OPC_Decode, + 240, + 41, + 45, // Opcode: UABDLB_ZZZ_D + /* 23747 */ MCD_OPC_FilterValue, + 7, + 135, + 59, + 1, // Skip to: 104527 + /* 23752 */ MCD_OPC_CheckPredicate, + 4, + 130, + 59, + 1, // Skip to: 104527 + /* 23757 */ MCD_OPC_Decode, + 243, + 41, + 45, // Opcode: UABDLT_ZZZ_D + /* 23761 */ MCD_OPC_FilterValue, + 2, + 101, + 4, + 0, // Skip to: 24891 + /* 23766 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 23769 */ MCD_OPC_FilterValue, + 2, + 115, + 0, + 0, // Skip to: 23889 + /* 23774 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 23777 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 23791 + /* 23782 */ MCD_OPC_CheckPredicate, + 4, + 100, + 59, + 1, // Skip to: 104527 + /* 23787 */ MCD_OPC_Decode, + 158, + 32, + 54, // Opcode: SMLALB_ZZZ_H + /* 23791 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 23805 + /* 23796 */ MCD_OPC_CheckPredicate, + 4, + 86, + 59, + 1, // Skip to: 104527 + /* 23801 */ MCD_OPC_Decode, + 163, + 32, + 54, // Opcode: SMLALT_ZZZ_H + /* 23805 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 23819 + /* 23810 */ MCD_OPC_CheckPredicate, + 4, + 72, + 59, + 1, // Skip to: 104527 + /* 23815 */ MCD_OPC_Decode, + 204, + 43, + 54, // Opcode: UMLALB_ZZZ_H + /* 23819 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 23833 + /* 23824 */ MCD_OPC_CheckPredicate, + 4, + 58, + 59, + 1, // Skip to: 104527 + /* 23829 */ MCD_OPC_Decode, + 209, + 43, + 54, // Opcode: UMLALT_ZZZ_H + /* 23833 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 23847 + /* 23838 */ MCD_OPC_CheckPredicate, + 4, + 44, + 59, + 1, // Skip to: 104527 + /* 23843 */ MCD_OPC_Decode, + 178, + 32, + 54, // Opcode: SMLSLB_ZZZ_H + /* 23847 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 23861 + /* 23852 */ MCD_OPC_CheckPredicate, + 4, + 30, + 59, + 1, // Skip to: 104527 + /* 23857 */ MCD_OPC_Decode, + 183, + 32, + 54, // Opcode: SMLSLT_ZZZ_H + /* 23861 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 23875 + /* 23866 */ MCD_OPC_CheckPredicate, + 4, + 16, + 59, + 1, // Skip to: 104527 + /* 23871 */ MCD_OPC_Decode, + 224, + 43, + 54, // Opcode: UMLSLB_ZZZ_H + /* 23875 */ MCD_OPC_FilterValue, + 7, + 7, + 59, + 1, // Skip to: 104527 + /* 23880 */ MCD_OPC_CheckPredicate, + 4, + 2, + 59, + 1, // Skip to: 104527 + /* 23885 */ MCD_OPC_Decode, + 229, + 43, + 54, // Opcode: UMLSLT_ZZZ_H + /* 23889 */ MCD_OPC_FilterValue, + 4, + 115, + 0, + 0, // Skip to: 24009 + /* 23894 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 23897 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 23911 + /* 23902 */ MCD_OPC_CheckPredicate, + 4, + 236, + 58, + 1, // Skip to: 104527 + /* 23907 */ MCD_OPC_Decode, + 159, + 32, + 54, // Opcode: SMLALB_ZZZ_S + /* 23911 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 23925 + /* 23916 */ MCD_OPC_CheckPredicate, + 4, + 222, + 58, + 1, // Skip to: 104527 + /* 23921 */ MCD_OPC_Decode, + 164, + 32, + 54, // Opcode: SMLALT_ZZZ_S + /* 23925 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 23939 + /* 23930 */ MCD_OPC_CheckPredicate, + 4, + 208, + 58, + 1, // Skip to: 104527 + /* 23935 */ MCD_OPC_Decode, + 205, + 43, + 54, // Opcode: UMLALB_ZZZ_S + /* 23939 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 23953 + /* 23944 */ MCD_OPC_CheckPredicate, + 4, + 194, + 58, + 1, // Skip to: 104527 + /* 23949 */ MCD_OPC_Decode, + 210, + 43, + 54, // Opcode: UMLALT_ZZZ_S + /* 23953 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 23967 + /* 23958 */ MCD_OPC_CheckPredicate, + 4, + 180, + 58, + 1, // Skip to: 104527 + /* 23963 */ MCD_OPC_Decode, + 179, + 32, + 54, // Opcode: SMLSLB_ZZZ_S + /* 23967 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 23981 + /* 23972 */ MCD_OPC_CheckPredicate, + 4, + 166, + 58, + 1, // Skip to: 104527 + /* 23977 */ MCD_OPC_Decode, + 184, + 32, + 54, // Opcode: SMLSLT_ZZZ_S + /* 23981 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 23995 + /* 23986 */ MCD_OPC_CheckPredicate, + 4, + 152, + 58, + 1, // Skip to: 104527 + /* 23991 */ MCD_OPC_Decode, + 225, + 43, + 54, // Opcode: UMLSLB_ZZZ_S + /* 23995 */ MCD_OPC_FilterValue, + 7, + 143, + 58, + 1, // Skip to: 104527 + /* 24000 */ MCD_OPC_CheckPredicate, + 4, + 138, + 58, + 1, // Skip to: 104527 + /* 24005 */ MCD_OPC_Decode, + 230, + 43, + 54, // Opcode: UMLSLT_ZZZ_S + /* 24009 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 24031 + /* 24014 */ MCD_OPC_CheckPredicate, + 4, + 124, + 58, + 1, // Skip to: 104527 + /* 24019 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 117, + 58, + 1, // Skip to: 104527 + /* 24026 */ MCD_OPC_Decode, + 185, + 9, + 151, + 1, // Opcode: CDOT_ZZZI_S + /* 24031 */ MCD_OPC_FilterValue, + 6, + 115, + 0, + 0, // Skip to: 24151 + /* 24036 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 24039 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 24053 + /* 24044 */ MCD_OPC_CheckPredicate, + 4, + 94, + 58, + 1, // Skip to: 104527 + /* 24049 */ MCD_OPC_Decode, + 157, + 32, + 54, // Opcode: SMLALB_ZZZ_D + /* 24053 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 24067 + /* 24058 */ MCD_OPC_CheckPredicate, + 4, + 80, + 58, + 1, // Skip to: 104527 + /* 24063 */ MCD_OPC_Decode, + 162, + 32, + 54, // Opcode: SMLALT_ZZZ_D + /* 24067 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 24081 + /* 24072 */ MCD_OPC_CheckPredicate, + 4, + 66, + 58, + 1, // Skip to: 104527 + /* 24077 */ MCD_OPC_Decode, + 203, + 43, + 54, // Opcode: UMLALB_ZZZ_D + /* 24081 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 24095 + /* 24086 */ MCD_OPC_CheckPredicate, + 4, + 52, + 58, + 1, // Skip to: 104527 + /* 24091 */ MCD_OPC_Decode, + 208, + 43, + 54, // Opcode: UMLALT_ZZZ_D + /* 24095 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 24109 + /* 24100 */ MCD_OPC_CheckPredicate, + 4, + 38, + 58, + 1, // Skip to: 104527 + /* 24105 */ MCD_OPC_Decode, + 177, + 32, + 54, // Opcode: SMLSLB_ZZZ_D + /* 24109 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 24123 + /* 24114 */ MCD_OPC_CheckPredicate, + 4, + 24, + 58, + 1, // Skip to: 104527 + /* 24119 */ MCD_OPC_Decode, + 182, + 32, + 54, // Opcode: SMLSLT_ZZZ_D + /* 24123 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 24137 + /* 24128 */ MCD_OPC_CheckPredicate, + 4, + 10, + 58, + 1, // Skip to: 104527 + /* 24133 */ MCD_OPC_Decode, + 223, + 43, + 54, // Opcode: UMLSLB_ZZZ_D + /* 24137 */ MCD_OPC_FilterValue, + 7, + 1, + 58, + 1, // Skip to: 104527 + /* 24142 */ MCD_OPC_CheckPredicate, + 4, + 252, + 57, + 1, // Skip to: 104527 + /* 24147 */ MCD_OPC_Decode, + 228, + 43, + 54, // Opcode: UMLSLT_ZZZ_D + /* 24151 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 24173 + /* 24156 */ MCD_OPC_CheckPredicate, + 4, + 238, + 57, + 1, // Skip to: 104527 + /* 24161 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 231, + 57, + 1, // Skip to: 104527 + /* 24168 */ MCD_OPC_Decode, + 184, + 9, + 152, + 1, // Opcode: CDOT_ZZZI_D + /* 24173 */ MCD_OPC_FilterValue, + 9, + 219, + 0, + 0, // Skip to: 24397 + /* 24178 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 24181 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 24217 + /* 24186 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 24189 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 24203 + /* 24194 */ MCD_OPC_CheckPredicate, + 4, + 200, + 57, + 1, // Skip to: 104527 + /* 24199 */ MCD_OPC_Decode, + 147, + 36, + 63, // Opcode: SQXTNB_ZZ_B + /* 24203 */ MCD_OPC_FilterValue, + 16, + 191, + 57, + 1, // Skip to: 104527 + /* 24208 */ MCD_OPC_CheckPredicate, + 4, + 186, + 57, + 1, // Skip to: 104527 + /* 24213 */ MCD_OPC_Decode, + 148, + 36, + 63, // Opcode: SQXTNB_ZZ_H + /* 24217 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 24253 + /* 24222 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 24225 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 24239 + /* 24230 */ MCD_OPC_CheckPredicate, + 4, + 164, + 57, + 1, // Skip to: 104527 + /* 24235 */ MCD_OPC_Decode, + 150, + 36, + 62, // Opcode: SQXTNT_ZZ_B + /* 24239 */ MCD_OPC_FilterValue, + 16, + 155, + 57, + 1, // Skip to: 104527 + /* 24244 */ MCD_OPC_CheckPredicate, + 4, + 150, + 57, + 1, // Skip to: 104527 + /* 24249 */ MCD_OPC_Decode, + 151, + 36, + 62, // Opcode: SQXTNT_ZZ_H + /* 24253 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 24289 + /* 24258 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 24261 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 24275 + /* 24266 */ MCD_OPC_CheckPredicate, + 4, + 128, + 57, + 1, // Skip to: 104527 + /* 24271 */ MCD_OPC_Decode, + 206, + 45, + 63, // Opcode: UQXTNB_ZZ_B + /* 24275 */ MCD_OPC_FilterValue, + 16, + 119, + 57, + 1, // Skip to: 104527 + /* 24280 */ MCD_OPC_CheckPredicate, + 4, + 114, + 57, + 1, // Skip to: 104527 + /* 24285 */ MCD_OPC_Decode, + 207, + 45, + 63, // Opcode: UQXTNB_ZZ_H + /* 24289 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 24325 + /* 24294 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 24297 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 24311 + /* 24302 */ MCD_OPC_CheckPredicate, + 4, + 92, + 57, + 1, // Skip to: 104527 + /* 24307 */ MCD_OPC_Decode, + 209, + 45, + 62, // Opcode: UQXTNT_ZZ_B + /* 24311 */ MCD_OPC_FilterValue, + 16, + 83, + 57, + 1, // Skip to: 104527 + /* 24316 */ MCD_OPC_CheckPredicate, + 4, + 78, + 57, + 1, // Skip to: 104527 + /* 24321 */ MCD_OPC_Decode, + 210, + 45, + 62, // Opcode: UQXTNT_ZZ_H + /* 24325 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 24361 + /* 24330 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 24333 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 24347 + /* 24338 */ MCD_OPC_CheckPredicate, + 4, + 56, + 57, + 1, // Skip to: 104527 + /* 24343 */ MCD_OPC_Decode, + 162, + 36, + 63, // Opcode: SQXTUNB_ZZ_B + /* 24347 */ MCD_OPC_FilterValue, + 16, + 47, + 57, + 1, // Skip to: 104527 + /* 24352 */ MCD_OPC_CheckPredicate, + 4, + 42, + 57, + 1, // Skip to: 104527 + /* 24357 */ MCD_OPC_Decode, + 163, + 36, + 63, // Opcode: SQXTUNB_ZZ_H + /* 24361 */ MCD_OPC_FilterValue, + 5, + 33, + 57, + 1, // Skip to: 104527 + /* 24366 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 24369 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 24383 + /* 24374 */ MCD_OPC_CheckPredicate, + 4, + 20, + 57, + 1, // Skip to: 104527 + /* 24379 */ MCD_OPC_Decode, + 165, + 36, + 62, // Opcode: SQXTUNT_ZZ_B + /* 24383 */ MCD_OPC_FilterValue, + 16, + 11, + 57, + 1, // Skip to: 104527 + /* 24388 */ MCD_OPC_CheckPredicate, + 4, + 6, + 57, + 1, // Skip to: 104527 + /* 24393 */ MCD_OPC_Decode, + 166, + 36, + 62, // Opcode: SQXTUNT_ZZ_H + /* 24397 */ MCD_OPC_FilterValue, + 10, + 115, + 0, + 0, // Skip to: 24517 + /* 24402 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 24405 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 24419 + /* 24410 */ MCD_OPC_CheckPredicate, + 4, + 240, + 56, + 1, // Skip to: 104527 + /* 24415 */ MCD_OPC_Decode, + 173, + 30, + 45, // Opcode: SADDWB_ZZZ_H + /* 24419 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 24433 + /* 24424 */ MCD_OPC_CheckPredicate, + 4, + 226, + 56, + 1, // Skip to: 104527 + /* 24429 */ MCD_OPC_Decode, + 176, + 30, + 45, // Opcode: SADDWT_ZZZ_H + /* 24433 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 24447 + /* 24438 */ MCD_OPC_CheckPredicate, + 4, + 212, + 56, + 1, // Skip to: 104527 + /* 24443 */ MCD_OPC_Decode, + 171, + 42, + 45, // Opcode: UADDWB_ZZZ_H + /* 24447 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 24461 + /* 24452 */ MCD_OPC_CheckPredicate, + 4, + 198, + 56, + 1, // Skip to: 104527 + /* 24457 */ MCD_OPC_Decode, + 174, + 42, + 45, // Opcode: UADDWT_ZZZ_H + /* 24461 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 24475 + /* 24466 */ MCD_OPC_CheckPredicate, + 4, + 184, + 56, + 1, // Skip to: 104527 + /* 24471 */ MCD_OPC_Decode, + 208, + 37, + 45, // Opcode: SSUBWB_ZZZ_H + /* 24475 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 24489 + /* 24480 */ MCD_OPC_CheckPredicate, + 4, + 170, + 56, + 1, // Skip to: 104527 + /* 24485 */ MCD_OPC_Decode, + 211, + 37, + 45, // Opcode: SSUBWT_ZZZ_H + /* 24489 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 24503 + /* 24494 */ MCD_OPC_CheckPredicate, + 4, + 156, + 56, + 1, // Skip to: 104527 + /* 24499 */ MCD_OPC_Decode, + 229, + 46, + 45, // Opcode: USUBWB_ZZZ_H + /* 24503 */ MCD_OPC_FilterValue, + 7, + 147, + 56, + 1, // Skip to: 104527 + /* 24508 */ MCD_OPC_CheckPredicate, + 4, + 142, + 56, + 1, // Skip to: 104527 + /* 24513 */ MCD_OPC_Decode, + 232, + 46, + 45, // Opcode: USUBWT_ZZZ_H + /* 24517 */ MCD_OPC_FilterValue, + 11, + 129, + 0, + 0, // Skip to: 24651 + /* 24522 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 24525 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 24546 + /* 24530 */ MCD_OPC_CheckPredicate, + 4, + 120, + 56, + 1, // Skip to: 104527 + /* 24535 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 113, + 56, + 1, // Skip to: 104527 + /* 24542 */ MCD_OPC_Decode, + 149, + 36, + 63, // Opcode: SQXTNB_ZZ_S + /* 24546 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 24567 + /* 24551 */ MCD_OPC_CheckPredicate, + 4, + 99, + 56, + 1, // Skip to: 104527 + /* 24556 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 92, + 56, + 1, // Skip to: 104527 + /* 24563 */ MCD_OPC_Decode, + 152, + 36, + 62, // Opcode: SQXTNT_ZZ_S + /* 24567 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 24588 + /* 24572 */ MCD_OPC_CheckPredicate, + 4, + 78, + 56, + 1, // Skip to: 104527 + /* 24577 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 71, + 56, + 1, // Skip to: 104527 + /* 24584 */ MCD_OPC_Decode, + 208, + 45, + 63, // Opcode: UQXTNB_ZZ_S + /* 24588 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 24609 + /* 24593 */ MCD_OPC_CheckPredicate, + 4, + 57, + 56, + 1, // Skip to: 104527 + /* 24598 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 50, + 56, + 1, // Skip to: 104527 + /* 24605 */ MCD_OPC_Decode, + 211, + 45, + 62, // Opcode: UQXTNT_ZZ_S + /* 24609 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 24630 + /* 24614 */ MCD_OPC_CheckPredicate, + 4, + 36, + 56, + 1, // Skip to: 104527 + /* 24619 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 29, + 56, + 1, // Skip to: 104527 + /* 24626 */ MCD_OPC_Decode, + 164, + 36, + 63, // Opcode: SQXTUNB_ZZ_S + /* 24630 */ MCD_OPC_FilterValue, + 5, + 20, + 56, + 1, // Skip to: 104527 + /* 24635 */ MCD_OPC_CheckPredicate, + 4, + 15, + 56, + 1, // Skip to: 104527 + /* 24640 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 8, + 56, + 1, // Skip to: 104527 + /* 24647 */ MCD_OPC_Decode, + 167, + 36, + 62, // Opcode: SQXTUNT_ZZ_S + /* 24651 */ MCD_OPC_FilterValue, + 12, + 115, + 0, + 0, // Skip to: 24771 + /* 24656 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 24659 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 24673 + /* 24664 */ MCD_OPC_CheckPredicate, + 4, + 242, + 55, + 1, // Skip to: 104527 + /* 24669 */ MCD_OPC_Decode, + 174, + 30, + 45, // Opcode: SADDWB_ZZZ_S + /* 24673 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 24687 + /* 24678 */ MCD_OPC_CheckPredicate, + 4, + 228, + 55, + 1, // Skip to: 104527 + /* 24683 */ MCD_OPC_Decode, + 177, + 30, + 45, // Opcode: SADDWT_ZZZ_S + /* 24687 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 24701 + /* 24692 */ MCD_OPC_CheckPredicate, + 4, + 214, + 55, + 1, // Skip to: 104527 + /* 24697 */ MCD_OPC_Decode, + 172, + 42, + 45, // Opcode: UADDWB_ZZZ_S + /* 24701 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 24715 + /* 24706 */ MCD_OPC_CheckPredicate, + 4, + 200, + 55, + 1, // Skip to: 104527 + /* 24711 */ MCD_OPC_Decode, + 175, + 42, + 45, // Opcode: UADDWT_ZZZ_S + /* 24715 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 24729 + /* 24720 */ MCD_OPC_CheckPredicate, + 4, + 186, + 55, + 1, // Skip to: 104527 + /* 24725 */ MCD_OPC_Decode, + 209, + 37, + 45, // Opcode: SSUBWB_ZZZ_S + /* 24729 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 24743 + /* 24734 */ MCD_OPC_CheckPredicate, + 4, + 172, + 55, + 1, // Skip to: 104527 + /* 24739 */ MCD_OPC_Decode, + 212, + 37, + 45, // Opcode: SSUBWT_ZZZ_S + /* 24743 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 24757 + /* 24748 */ MCD_OPC_CheckPredicate, + 4, + 158, + 55, + 1, // Skip to: 104527 + /* 24753 */ MCD_OPC_Decode, + 230, + 46, + 45, // Opcode: USUBWB_ZZZ_S + /* 24757 */ MCD_OPC_FilterValue, + 7, + 149, + 55, + 1, // Skip to: 104527 + /* 24762 */ MCD_OPC_CheckPredicate, + 4, + 144, + 55, + 1, // Skip to: 104527 + /* 24767 */ MCD_OPC_Decode, + 233, + 46, + 45, // Opcode: USUBWT_ZZZ_S + /* 24771 */ MCD_OPC_FilterValue, + 14, + 135, + 55, + 1, // Skip to: 104527 + /* 24776 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 24779 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 24793 + /* 24784 */ MCD_OPC_CheckPredicate, + 4, + 122, + 55, + 1, // Skip to: 104527 + /* 24789 */ MCD_OPC_Decode, + 172, + 30, + 45, // Opcode: SADDWB_ZZZ_D + /* 24793 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 24807 + /* 24798 */ MCD_OPC_CheckPredicate, + 4, + 108, + 55, + 1, // Skip to: 104527 + /* 24803 */ MCD_OPC_Decode, + 175, + 30, + 45, // Opcode: SADDWT_ZZZ_D + /* 24807 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 24821 + /* 24812 */ MCD_OPC_CheckPredicate, + 4, + 94, + 55, + 1, // Skip to: 104527 + /* 24817 */ MCD_OPC_Decode, + 170, + 42, + 45, // Opcode: UADDWB_ZZZ_D + /* 24821 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 24835 + /* 24826 */ MCD_OPC_CheckPredicate, + 4, + 80, + 55, + 1, // Skip to: 104527 + /* 24831 */ MCD_OPC_Decode, + 173, + 42, + 45, // Opcode: UADDWT_ZZZ_D + /* 24835 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 24849 + /* 24840 */ MCD_OPC_CheckPredicate, + 4, + 66, + 55, + 1, // Skip to: 104527 + /* 24845 */ MCD_OPC_Decode, + 207, + 37, + 45, // Opcode: SSUBWB_ZZZ_D + /* 24849 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 24863 + /* 24854 */ MCD_OPC_CheckPredicate, + 4, + 52, + 55, + 1, // Skip to: 104527 + /* 24859 */ MCD_OPC_Decode, + 210, + 37, + 45, // Opcode: SSUBWT_ZZZ_D + /* 24863 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 24877 + /* 24868 */ MCD_OPC_CheckPredicate, + 4, + 38, + 55, + 1, // Skip to: 104527 + /* 24873 */ MCD_OPC_Decode, + 228, + 46, + 45, // Opcode: USUBWB_ZZZ_D + /* 24877 */ MCD_OPC_FilterValue, + 7, + 29, + 55, + 1, // Skip to: 104527 + /* 24882 */ MCD_OPC_CheckPredicate, + 4, + 24, + 55, + 1, // Skip to: 104527 + /* 24887 */ MCD_OPC_Decode, + 231, + 46, + 45, // Opcode: USUBWT_ZZZ_D + /* 24891 */ MCD_OPC_FilterValue, + 3, + 109, + 4, + 0, // Skip to: 26029 + /* 24896 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 24899 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 24935 + /* 24904 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 24907 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 24921 + /* 24912 */ MCD_OPC_CheckPredicate, + 4, + 250, + 54, + 1, // Skip to: 104527 + /* 24917 */ MCD_OPC_Decode, + 194, + 34, + 54, // Opcode: SQRDMLAH_ZZZ_B + /* 24921 */ MCD_OPC_FilterValue, + 5, + 241, + 54, + 1, // Skip to: 104527 + /* 24926 */ MCD_OPC_CheckPredicate, + 4, + 236, + 54, + 1, // Skip to: 104527 + /* 24931 */ MCD_OPC_Decode, + 213, + 34, + 54, // Opcode: SQRDMLSH_ZZZ_B + /* 24935 */ MCD_OPC_FilterValue, + 2, + 87, + 0, + 0, // Skip to: 25027 + /* 24940 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 24943 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 24957 + /* 24948 */ MCD_OPC_CheckPredicate, + 4, + 214, + 54, + 1, // Skip to: 104527 + /* 24953 */ MCD_OPC_Decode, + 191, + 33, + 54, // Opcode: SQDMLALB_ZZZ_H + /* 24957 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 24971 + /* 24962 */ MCD_OPC_CheckPredicate, + 4, + 200, + 54, + 1, // Skip to: 104527 + /* 24967 */ MCD_OPC_Decode, + 196, + 33, + 54, // Opcode: SQDMLALT_ZZZ_H + /* 24971 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 24985 + /* 24976 */ MCD_OPC_CheckPredicate, + 4, + 186, + 54, + 1, // Skip to: 104527 + /* 24981 */ MCD_OPC_Decode, + 216, + 33, + 54, // Opcode: SQDMLSLB_ZZZ_H + /* 24985 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 24999 + /* 24990 */ MCD_OPC_CheckPredicate, + 4, + 172, + 54, + 1, // Skip to: 104527 + /* 24995 */ MCD_OPC_Decode, + 221, + 33, + 54, // Opcode: SQDMLSLT_ZZZ_H + /* 24999 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 25013 + /* 25004 */ MCD_OPC_CheckPredicate, + 4, + 158, + 54, + 1, // Skip to: 104527 + /* 25009 */ MCD_OPC_Decode, + 196, + 34, + 54, // Opcode: SQRDMLAH_ZZZ_H + /* 25013 */ MCD_OPC_FilterValue, + 5, + 149, + 54, + 1, // Skip to: 104527 + /* 25018 */ MCD_OPC_CheckPredicate, + 4, + 144, + 54, + 1, // Skip to: 104527 + /* 25023 */ MCD_OPC_Decode, + 215, + 34, + 54, // Opcode: SQRDMLSH_ZZZ_H + /* 25027 */ MCD_OPC_FilterValue, + 4, + 101, + 0, + 0, // Skip to: 25133 + /* 25032 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 25035 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25049 + /* 25040 */ MCD_OPC_CheckPredicate, + 4, + 122, + 54, + 1, // Skip to: 104527 + /* 25045 */ MCD_OPC_Decode, + 192, + 33, + 54, // Opcode: SQDMLALB_ZZZ_S + /* 25049 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25063 + /* 25054 */ MCD_OPC_CheckPredicate, + 4, + 108, + 54, + 1, // Skip to: 104527 + /* 25059 */ MCD_OPC_Decode, + 197, + 33, + 54, // Opcode: SQDMLALT_ZZZ_S + /* 25063 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 25077 + /* 25068 */ MCD_OPC_CheckPredicate, + 4, + 94, + 54, + 1, // Skip to: 104527 + /* 25073 */ MCD_OPC_Decode, + 217, + 33, + 54, // Opcode: SQDMLSLB_ZZZ_S + /* 25077 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 25091 + /* 25082 */ MCD_OPC_CheckPredicate, + 4, + 80, + 54, + 1, // Skip to: 104527 + /* 25087 */ MCD_OPC_Decode, + 222, + 33, + 54, // Opcode: SQDMLSLT_ZZZ_S + /* 25091 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 25105 + /* 25096 */ MCD_OPC_CheckPredicate, + 4, + 66, + 54, + 1, // Skip to: 104527 + /* 25101 */ MCD_OPC_Decode, + 197, + 34, + 54, // Opcode: SQRDMLAH_ZZZ_S + /* 25105 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 25119 + /* 25110 */ MCD_OPC_CheckPredicate, + 4, + 52, + 54, + 1, // Skip to: 104527 + /* 25115 */ MCD_OPC_Decode, + 216, + 34, + 54, // Opcode: SQRDMLSH_ZZZ_S + /* 25119 */ MCD_OPC_FilterValue, + 6, + 43, + 54, + 1, // Skip to: 104527 + /* 25124 */ MCD_OPC_CheckPredicate, + 7, + 38, + 54, + 1, // Skip to: 104527 + /* 25129 */ MCD_OPC_Decode, + 149, + 46, + 54, // Opcode: USDOT_ZZZ + /* 25133 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 25171 + /* 25138 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 25141 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 25156 + /* 25146 */ MCD_OPC_CheckPredicate, + 4, + 16, + 54, + 1, // Skip to: 104527 + /* 25151 */ MCD_OPC_Decode, + 174, + 10, + 151, + 1, // Opcode: CMLA_ZZZI_H + /* 25156 */ MCD_OPC_FilterValue, + 1, + 6, + 54, + 1, // Skip to: 104527 + /* 25161 */ MCD_OPC_CheckPredicate, + 4, + 1, + 54, + 1, // Skip to: 104527 + /* 25166 */ MCD_OPC_Decode, + 185, + 34, + 151, + 1, // Opcode: SQRDCMLAH_ZZZI_H + /* 25171 */ MCD_OPC_FilterValue, + 6, + 87, + 0, + 0, // Skip to: 25263 + /* 25176 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 25179 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25193 + /* 25184 */ MCD_OPC_CheckPredicate, + 4, + 234, + 53, + 1, // Skip to: 104527 + /* 25189 */ MCD_OPC_Decode, + 190, + 33, + 54, // Opcode: SQDMLALB_ZZZ_D + /* 25193 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25207 + /* 25198 */ MCD_OPC_CheckPredicate, + 4, + 220, + 53, + 1, // Skip to: 104527 + /* 25203 */ MCD_OPC_Decode, + 195, + 33, + 54, // Opcode: SQDMLALT_ZZZ_D + /* 25207 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 25221 + /* 25212 */ MCD_OPC_CheckPredicate, + 4, + 206, + 53, + 1, // Skip to: 104527 + /* 25217 */ MCD_OPC_Decode, + 215, + 33, + 54, // Opcode: SQDMLSLB_ZZZ_D + /* 25221 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 25235 + /* 25226 */ MCD_OPC_CheckPredicate, + 4, + 192, + 53, + 1, // Skip to: 104527 + /* 25231 */ MCD_OPC_Decode, + 220, + 33, + 54, // Opcode: SQDMLSLT_ZZZ_D + /* 25235 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 25249 + /* 25240 */ MCD_OPC_CheckPredicate, + 4, + 178, + 53, + 1, // Skip to: 104527 + /* 25245 */ MCD_OPC_Decode, + 195, + 34, + 54, // Opcode: SQRDMLAH_ZZZ_D + /* 25249 */ MCD_OPC_FilterValue, + 5, + 169, + 53, + 1, // Skip to: 104527 + /* 25254 */ MCD_OPC_CheckPredicate, + 4, + 164, + 53, + 1, // Skip to: 104527 + /* 25259 */ MCD_OPC_Decode, + 214, + 34, + 54, // Opcode: SQRDMLSH_ZZZ_D + /* 25263 */ MCD_OPC_FilterValue, + 7, + 33, + 0, + 0, // Skip to: 25301 + /* 25268 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 25271 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 25286 + /* 25276 */ MCD_OPC_CheckPredicate, + 4, + 142, + 53, + 1, // Skip to: 104527 + /* 25281 */ MCD_OPC_Decode, + 175, + 10, + 152, + 1, // Opcode: CMLA_ZZZI_S + /* 25286 */ MCD_OPC_FilterValue, + 1, + 132, + 53, + 1, // Skip to: 104527 + /* 25291 */ MCD_OPC_CheckPredicate, + 4, + 127, + 53, + 1, // Skip to: 104527 + /* 25296 */ MCD_OPC_Decode, + 186, + 34, + 152, + 1, // Opcode: SQRDCMLAH_ZZZI_S + /* 25301 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 25337 + /* 25306 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 25309 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 25323 + /* 25314 */ MCD_OPC_CheckPredicate, + 8, + 104, + 53, + 1, // Skip to: 104527 + /* 25319 */ MCD_OPC_Decode, + 187, + 28, + 45, // Opcode: PMULLB_ZZZ_Q + /* 25323 */ MCD_OPC_FilterValue, + 3, + 95, + 53, + 1, // Skip to: 104527 + /* 25328 */ MCD_OPC_CheckPredicate, + 8, + 90, + 53, + 1, // Skip to: 104527 + /* 25333 */ MCD_OPC_Decode, + 190, + 28, + 45, // Opcode: PMULLT_ZZZ_Q + /* 25337 */ MCD_OPC_FilterValue, + 10, + 115, + 0, + 0, // Skip to: 25457 + /* 25342 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 25345 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25359 + /* 25350 */ MCD_OPC_CheckPredicate, + 4, + 68, + 53, + 1, // Skip to: 104527 + /* 25355 */ MCD_OPC_Decode, + 129, + 34, + 45, // Opcode: SQDMULLB_ZZZ_H + /* 25359 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25373 + /* 25364 */ MCD_OPC_CheckPredicate, + 4, + 54, + 53, + 1, // Skip to: 104527 + /* 25369 */ MCD_OPC_Decode, + 134, + 34, + 45, // Opcode: SQDMULLT_ZZZ_H + /* 25373 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 25387 + /* 25378 */ MCD_OPC_CheckPredicate, + 4, + 40, + 53, + 1, // Skip to: 104527 + /* 25383 */ MCD_OPC_Decode, + 186, + 28, + 45, // Opcode: PMULLB_ZZZ_H + /* 25387 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 25401 + /* 25392 */ MCD_OPC_CheckPredicate, + 4, + 26, + 53, + 1, // Skip to: 104527 + /* 25397 */ MCD_OPC_Decode, + 189, + 28, + 45, // Opcode: PMULLT_ZZZ_H + /* 25401 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 25415 + /* 25406 */ MCD_OPC_CheckPredicate, + 4, + 12, + 53, + 1, // Skip to: 104527 + /* 25411 */ MCD_OPC_Decode, + 224, + 32, + 45, // Opcode: SMULLB_ZZZ_H + /* 25415 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 25429 + /* 25420 */ MCD_OPC_CheckPredicate, + 4, + 254, + 52, + 1, // Skip to: 104527 + /* 25425 */ MCD_OPC_Decode, + 229, + 32, + 45, // Opcode: SMULLT_ZZZ_H + /* 25429 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 25443 + /* 25434 */ MCD_OPC_CheckPredicate, + 4, + 240, + 52, + 1, // Skip to: 104527 + /* 25439 */ MCD_OPC_Decode, + 140, + 44, + 45, // Opcode: UMULLB_ZZZ_H + /* 25443 */ MCD_OPC_FilterValue, + 7, + 231, + 52, + 1, // Skip to: 104527 + /* 25448 */ MCD_OPC_CheckPredicate, + 4, + 226, + 52, + 1, // Skip to: 104527 + /* 25453 */ MCD_OPC_Decode, + 145, + 44, + 45, // Opcode: UMULLT_ZZZ_H + /* 25457 */ MCD_OPC_FilterValue, + 11, + 115, + 0, + 0, // Skip to: 25577 + /* 25462 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 25465 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25479 + /* 25470 */ MCD_OPC_CheckPredicate, + 4, + 204, + 52, + 1, // Skip to: 104527 + /* 25475 */ MCD_OPC_Decode, + 151, + 7, + 45, // Opcode: ADDHNB_ZZZ_B + /* 25479 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25493 + /* 25484 */ MCD_OPC_CheckPredicate, + 4, + 190, + 52, + 1, // Skip to: 104527 + /* 25489 */ MCD_OPC_Decode, + 154, + 7, + 54, // Opcode: ADDHNT_ZZZ_B + /* 25493 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 25507 + /* 25498 */ MCD_OPC_CheckPredicate, + 4, + 176, + 52, + 1, // Skip to: 104527 + /* 25503 */ MCD_OPC_Decode, + 130, + 29, + 45, // Opcode: RADDHNB_ZZZ_B + /* 25507 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 25521 + /* 25512 */ MCD_OPC_CheckPredicate, + 4, + 162, + 52, + 1, // Skip to: 104527 + /* 25517 */ MCD_OPC_Decode, + 133, + 29, + 54, // Opcode: RADDHNT_ZZZ_B + /* 25521 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 25535 + /* 25526 */ MCD_OPC_CheckPredicate, + 4, + 148, + 52, + 1, // Skip to: 104527 + /* 25531 */ MCD_OPC_Decode, + 168, + 40, + 45, // Opcode: SUBHNB_ZZZ_B + /* 25535 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 25549 + /* 25540 */ MCD_OPC_CheckPredicate, + 4, + 134, + 52, + 1, // Skip to: 104527 + /* 25545 */ MCD_OPC_Decode, + 171, + 40, + 54, // Opcode: SUBHNT_ZZZ_B + /* 25549 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 25563 + /* 25554 */ MCD_OPC_CheckPredicate, + 4, + 120, + 52, + 1, // Skip to: 104527 + /* 25559 */ MCD_OPC_Decode, + 206, + 29, + 45, // Opcode: RSUBHNB_ZZZ_B + /* 25563 */ MCD_OPC_FilterValue, + 7, + 111, + 52, + 1, // Skip to: 104527 + /* 25568 */ MCD_OPC_CheckPredicate, + 4, + 106, + 52, + 1, // Skip to: 104527 + /* 25573 */ MCD_OPC_Decode, + 209, + 29, + 54, // Opcode: RSUBHNT_ZZZ_B + /* 25577 */ MCD_OPC_FilterValue, + 12, + 87, + 0, + 0, // Skip to: 25669 + /* 25582 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 25585 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25599 + /* 25590 */ MCD_OPC_CheckPredicate, + 4, + 84, + 52, + 1, // Skip to: 104527 + /* 25595 */ MCD_OPC_Decode, + 130, + 34, + 45, // Opcode: SQDMULLB_ZZZ_S + /* 25599 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25613 + /* 25604 */ MCD_OPC_CheckPredicate, + 4, + 70, + 52, + 1, // Skip to: 104527 + /* 25609 */ MCD_OPC_Decode, + 135, + 34, + 45, // Opcode: SQDMULLT_ZZZ_S + /* 25613 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 25627 + /* 25618 */ MCD_OPC_CheckPredicate, + 4, + 56, + 52, + 1, // Skip to: 104527 + /* 25623 */ MCD_OPC_Decode, + 225, + 32, + 45, // Opcode: SMULLB_ZZZ_S + /* 25627 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 25641 + /* 25632 */ MCD_OPC_CheckPredicate, + 4, + 42, + 52, + 1, // Skip to: 104527 + /* 25637 */ MCD_OPC_Decode, + 230, + 32, + 45, // Opcode: SMULLT_ZZZ_S + /* 25641 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 25655 + /* 25646 */ MCD_OPC_CheckPredicate, + 4, + 28, + 52, + 1, // Skip to: 104527 + /* 25651 */ MCD_OPC_Decode, + 141, + 44, + 45, // Opcode: UMULLB_ZZZ_S + /* 25655 */ MCD_OPC_FilterValue, + 7, + 19, + 52, + 1, // Skip to: 104527 + /* 25660 */ MCD_OPC_CheckPredicate, + 4, + 14, + 52, + 1, // Skip to: 104527 + /* 25665 */ MCD_OPC_Decode, + 146, + 44, + 45, // Opcode: UMULLT_ZZZ_S + /* 25669 */ MCD_OPC_FilterValue, + 13, + 115, + 0, + 0, // Skip to: 25789 + /* 25674 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 25677 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25691 + /* 25682 */ MCD_OPC_CheckPredicate, + 4, + 248, + 51, + 1, // Skip to: 104527 + /* 25687 */ MCD_OPC_Decode, + 152, + 7, + 45, // Opcode: ADDHNB_ZZZ_H + /* 25691 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25705 + /* 25696 */ MCD_OPC_CheckPredicate, + 4, + 234, + 51, + 1, // Skip to: 104527 + /* 25701 */ MCD_OPC_Decode, + 155, + 7, + 54, // Opcode: ADDHNT_ZZZ_H + /* 25705 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 25719 + /* 25710 */ MCD_OPC_CheckPredicate, + 4, + 220, + 51, + 1, // Skip to: 104527 + /* 25715 */ MCD_OPC_Decode, + 131, + 29, + 45, // Opcode: RADDHNB_ZZZ_H + /* 25719 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 25733 + /* 25724 */ MCD_OPC_CheckPredicate, + 4, + 206, + 51, + 1, // Skip to: 104527 + /* 25729 */ MCD_OPC_Decode, + 134, + 29, + 54, // Opcode: RADDHNT_ZZZ_H + /* 25733 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 25747 + /* 25738 */ MCD_OPC_CheckPredicate, + 4, + 192, + 51, + 1, // Skip to: 104527 + /* 25743 */ MCD_OPC_Decode, + 169, + 40, + 45, // Opcode: SUBHNB_ZZZ_H + /* 25747 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 25761 + /* 25752 */ MCD_OPC_CheckPredicate, + 4, + 178, + 51, + 1, // Skip to: 104527 + /* 25757 */ MCD_OPC_Decode, + 172, + 40, + 54, // Opcode: SUBHNT_ZZZ_H + /* 25761 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 25775 + /* 25766 */ MCD_OPC_CheckPredicate, + 4, + 164, + 51, + 1, // Skip to: 104527 + /* 25771 */ MCD_OPC_Decode, + 207, + 29, + 45, // Opcode: RSUBHNB_ZZZ_H + /* 25775 */ MCD_OPC_FilterValue, + 7, + 155, + 51, + 1, // Skip to: 104527 + /* 25780 */ MCD_OPC_CheckPredicate, + 4, + 150, + 51, + 1, // Skip to: 104527 + /* 25785 */ MCD_OPC_Decode, + 210, + 29, + 54, // Opcode: RSUBHNT_ZZZ_H + /* 25789 */ MCD_OPC_FilterValue, + 14, + 115, + 0, + 0, // Skip to: 25909 + /* 25794 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 25797 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25811 + /* 25802 */ MCD_OPC_CheckPredicate, + 4, + 128, + 51, + 1, // Skip to: 104527 + /* 25807 */ MCD_OPC_Decode, + 128, + 34, + 45, // Opcode: SQDMULLB_ZZZ_D + /* 25811 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25825 + /* 25816 */ MCD_OPC_CheckPredicate, + 4, + 114, + 51, + 1, // Skip to: 104527 + /* 25821 */ MCD_OPC_Decode, + 133, + 34, + 45, // Opcode: SQDMULLT_ZZZ_D + /* 25825 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 25839 + /* 25830 */ MCD_OPC_CheckPredicate, + 4, + 100, + 51, + 1, // Skip to: 104527 + /* 25835 */ MCD_OPC_Decode, + 185, + 28, + 45, // Opcode: PMULLB_ZZZ_D + /* 25839 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 25853 + /* 25844 */ MCD_OPC_CheckPredicate, + 4, + 86, + 51, + 1, // Skip to: 104527 + /* 25849 */ MCD_OPC_Decode, + 188, + 28, + 45, // Opcode: PMULLT_ZZZ_D + /* 25853 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 25867 + /* 25858 */ MCD_OPC_CheckPredicate, + 4, + 72, + 51, + 1, // Skip to: 104527 + /* 25863 */ MCD_OPC_Decode, + 223, + 32, + 45, // Opcode: SMULLB_ZZZ_D + /* 25867 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 25881 + /* 25872 */ MCD_OPC_CheckPredicate, + 4, + 58, + 51, + 1, // Skip to: 104527 + /* 25877 */ MCD_OPC_Decode, + 228, + 32, + 45, // Opcode: SMULLT_ZZZ_D + /* 25881 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 25895 + /* 25886 */ MCD_OPC_CheckPredicate, + 4, + 44, + 51, + 1, // Skip to: 104527 + /* 25891 */ MCD_OPC_Decode, + 139, + 44, + 45, // Opcode: UMULLB_ZZZ_D + /* 25895 */ MCD_OPC_FilterValue, + 7, + 35, + 51, + 1, // Skip to: 104527 + /* 25900 */ MCD_OPC_CheckPredicate, + 4, + 30, + 51, + 1, // Skip to: 104527 + /* 25905 */ MCD_OPC_Decode, + 144, + 44, + 45, // Opcode: UMULLT_ZZZ_D + /* 25909 */ MCD_OPC_FilterValue, + 15, + 21, + 51, + 1, // Skip to: 104527 + /* 25914 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 25917 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25931 + /* 25922 */ MCD_OPC_CheckPredicate, + 4, + 8, + 51, + 1, // Skip to: 104527 + /* 25927 */ MCD_OPC_Decode, + 153, + 7, + 45, // Opcode: ADDHNB_ZZZ_S + /* 25931 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25945 + /* 25936 */ MCD_OPC_CheckPredicate, + 4, + 250, + 50, + 1, // Skip to: 104527 + /* 25941 */ MCD_OPC_Decode, + 156, + 7, + 54, // Opcode: ADDHNT_ZZZ_S + /* 25945 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 25959 + /* 25950 */ MCD_OPC_CheckPredicate, + 4, + 236, + 50, + 1, // Skip to: 104527 + /* 25955 */ MCD_OPC_Decode, + 132, + 29, + 45, // Opcode: RADDHNB_ZZZ_S + /* 25959 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 25973 + /* 25964 */ MCD_OPC_CheckPredicate, + 4, + 222, + 50, + 1, // Skip to: 104527 + /* 25969 */ MCD_OPC_Decode, + 135, + 29, + 54, // Opcode: RADDHNT_ZZZ_S + /* 25973 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 25987 + /* 25978 */ MCD_OPC_CheckPredicate, + 4, + 208, + 50, + 1, // Skip to: 104527 + /* 25983 */ MCD_OPC_Decode, + 170, + 40, + 45, // Opcode: SUBHNB_ZZZ_S + /* 25987 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 26001 + /* 25992 */ MCD_OPC_CheckPredicate, + 4, + 194, + 50, + 1, // Skip to: 104527 + /* 25997 */ MCD_OPC_Decode, + 173, + 40, + 54, // Opcode: SUBHNT_ZZZ_S + /* 26001 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 26015 + /* 26006 */ MCD_OPC_CheckPredicate, + 4, + 180, + 50, + 1, // Skip to: 104527 + /* 26011 */ MCD_OPC_Decode, + 208, + 29, + 45, // Opcode: RSUBHNB_ZZZ_S + /* 26015 */ MCD_OPC_FilterValue, + 7, + 171, + 50, + 1, // Skip to: 104527 + /* 26020 */ MCD_OPC_CheckPredicate, + 4, + 166, + 50, + 1, // Skip to: 104527 + /* 26025 */ MCD_OPC_Decode, + 211, + 29, + 54, // Opcode: RSUBHNT_ZZZ_S + /* 26029 */ MCD_OPC_FilterValue, + 4, + 107, + 8, + 0, // Skip to: 28189 + /* 26034 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 26037 */ MCD_OPC_FilterValue, + 0, + 139, + 1, + 0, // Skip to: 26437 + /* 26042 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 26045 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 26059 + /* 26050 */ MCD_OPC_CheckPredicate, + 4, + 136, + 50, + 1, // Skip to: 104527 + /* 26055 */ MCD_OPC_Decode, + 203, + 36, + 22, // Opcode: SRSHL_ZPmZ_B + /* 26059 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 26073 + /* 26064 */ MCD_OPC_CheckPredicate, + 4, + 122, + 50, + 1, // Skip to: 104527 + /* 26069 */ MCD_OPC_Decode, + 238, + 45, + 22, // Opcode: URSHL_ZPmZ_B + /* 26073 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 26087 + /* 26078 */ MCD_OPC_CheckPredicate, + 4, + 108, + 50, + 1, // Skip to: 104527 + /* 26083 */ MCD_OPC_Decode, + 199, + 36, + 22, // Opcode: SRSHLR_ZPmZ_B + /* 26087 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 26101 + /* 26092 */ MCD_OPC_CheckPredicate, + 4, + 94, + 50, + 1, // Skip to: 104527 + /* 26097 */ MCD_OPC_Decode, + 234, + 45, + 22, // Opcode: URSHLR_ZPmZ_B + /* 26101 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 26115 + /* 26106 */ MCD_OPC_CheckPredicate, + 4, + 80, + 50, + 1, // Skip to: 104527 + /* 26111 */ MCD_OPC_Decode, + 192, + 35, + 22, // Opcode: SQSHL_ZPmZ_B + /* 26115 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 26129 + /* 26120 */ MCD_OPC_CheckPredicate, + 4, + 66, + 50, + 1, // Skip to: 104527 + /* 26125 */ MCD_OPC_Decode, + 138, + 45, + 22, // Opcode: UQSHL_ZPmZ_B + /* 26129 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 26143 + /* 26134 */ MCD_OPC_CheckPredicate, + 4, + 52, + 50, + 1, // Skip to: 104527 + /* 26139 */ MCD_OPC_Decode, + 252, + 34, + 22, // Opcode: SQRSHL_ZPmZ_B + /* 26143 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 26157 + /* 26148 */ MCD_OPC_CheckPredicate, + 4, + 38, + 50, + 1, // Skip to: 104527 + /* 26153 */ MCD_OPC_Decode, + 228, + 44, + 22, // Opcode: UQRSHL_ZPmZ_B + /* 26157 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 26171 + /* 26162 */ MCD_OPC_CheckPredicate, + 4, + 24, + 50, + 1, // Skip to: 104527 + /* 26167 */ MCD_OPC_Decode, + 169, + 35, + 22, // Opcode: SQSHLR_ZPmZ_B + /* 26171 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 26185 + /* 26176 */ MCD_OPC_CheckPredicate, + 4, + 10, + 50, + 1, // Skip to: 104527 + /* 26181 */ MCD_OPC_Decode, + 130, + 45, + 22, // Opcode: UQSHLR_ZPmZ_B + /* 26185 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 26199 + /* 26190 */ MCD_OPC_CheckPredicate, + 4, + 252, + 49, + 1, // Skip to: 104527 + /* 26195 */ MCD_OPC_Decode, + 248, + 34, + 22, // Opcode: SQRSHLR_ZPmZ_B + /* 26199 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 26213 + /* 26204 */ MCD_OPC_CheckPredicate, + 4, + 238, + 49, + 1, // Skip to: 104527 + /* 26209 */ MCD_OPC_Decode, + 224, + 44, + 22, // Opcode: UQRSHLR_ZPmZ_B + /* 26213 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 26227 + /* 26218 */ MCD_OPC_CheckPredicate, + 4, + 224, + 49, + 1, // Skip to: 104527 + /* 26223 */ MCD_OPC_Decode, + 142, + 31, + 22, // Opcode: SHADD_ZPmZ_B + /* 26227 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 26241 + /* 26232 */ MCD_OPC_CheckPredicate, + 4, + 210, + 49, + 1, // Skip to: 104527 + /* 26237 */ MCD_OPC_Decode, + 238, + 42, + 22, // Opcode: UHADD_ZPmZ_B + /* 26241 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 26255 + /* 26246 */ MCD_OPC_CheckPredicate, + 4, + 196, + 49, + 1, // Skip to: 104527 + /* 26251 */ MCD_OPC_Decode, + 182, + 31, + 22, // Opcode: SHSUB_ZPmZ_B + /* 26255 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 26269 + /* 26260 */ MCD_OPC_CheckPredicate, + 4, + 182, + 49, + 1, // Skip to: 104527 + /* 26265 */ MCD_OPC_Decode, + 252, + 42, + 22, // Opcode: UHSUB_ZPmZ_B + /* 26269 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 26283 + /* 26274 */ MCD_OPC_CheckPredicate, + 4, + 168, + 49, + 1, // Skip to: 104527 + /* 26279 */ MCD_OPC_Decode, + 177, + 36, + 22, // Opcode: SRHADD_ZPmZ_B + /* 26283 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 26297 + /* 26288 */ MCD_OPC_CheckPredicate, + 4, + 154, + 49, + 1, // Skip to: 104527 + /* 26293 */ MCD_OPC_Decode, + 224, + 45, + 22, // Opcode: URHADD_ZPmZ_B + /* 26297 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 26311 + /* 26302 */ MCD_OPC_CheckPredicate, + 4, + 140, + 49, + 1, // Skip to: 104527 + /* 26307 */ MCD_OPC_Decode, + 178, + 31, + 22, // Opcode: SHSUBR_ZPmZ_B + /* 26311 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 26325 + /* 26316 */ MCD_OPC_CheckPredicate, + 4, + 126, + 49, + 1, // Skip to: 104527 + /* 26321 */ MCD_OPC_Decode, + 248, + 42, + 22, // Opcode: UHSUBR_ZPmZ_B + /* 26325 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 26339 + /* 26330 */ MCD_OPC_CheckPredicate, + 4, + 112, + 49, + 1, // Skip to: 104527 + /* 26335 */ MCD_OPC_Decode, + 140, + 33, + 22, // Opcode: SQADD_ZPmZ_B + /* 26339 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 26353 + /* 26344 */ MCD_OPC_CheckPredicate, + 4, + 98, + 49, + 1, // Skip to: 104527 + /* 26349 */ MCD_OPC_Decode, + 161, + 44, + 22, // Opcode: UQADD_ZPmZ_B + /* 26353 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 26367 + /* 26358 */ MCD_OPC_CheckPredicate, + 4, + 84, + 49, + 1, // Skip to: 104527 + /* 26363 */ MCD_OPC_Decode, + 128, + 36, + 22, // Opcode: SQSUB_ZPmZ_B + /* 26367 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 26381 + /* 26372 */ MCD_OPC_CheckPredicate, + 4, + 70, + 49, + 1, // Skip to: 104527 + /* 26377 */ MCD_OPC_Decode, + 187, + 45, + 22, // Opcode: UQSUB_ZPmZ_B + /* 26381 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 26395 + /* 26386 */ MCD_OPC_CheckPredicate, + 4, + 56, + 49, + 1, // Skip to: 104527 + /* 26391 */ MCD_OPC_Decode, + 237, + 40, + 22, // Opcode: SUQADD_ZPmZ_B + /* 26395 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 26409 + /* 26400 */ MCD_OPC_CheckPredicate, + 4, + 42, + 49, + 1, // Skip to: 104527 + /* 26405 */ MCD_OPC_Decode, + 189, + 46, + 22, // Opcode: USQADD_ZPmZ_B + /* 26409 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 26423 + /* 26414 */ MCD_OPC_CheckPredicate, + 4, + 28, + 49, + 1, // Skip to: 104527 + /* 26419 */ MCD_OPC_Decode, + 248, + 35, + 22, // Opcode: SQSUBR_ZPmZ_B + /* 26423 */ MCD_OPC_FilterValue, + 31, + 19, + 49, + 1, // Skip to: 104527 + /* 26428 */ MCD_OPC_CheckPredicate, + 4, + 14, + 49, + 1, // Skip to: 104527 + /* 26433 */ MCD_OPC_Decode, + 179, + 45, + 22, // Opcode: UQSUBR_ZPmZ_B + /* 26437 */ MCD_OPC_FilterValue, + 2, + 139, + 1, + 0, // Skip to: 26837 + /* 26442 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 26445 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 26459 + /* 26450 */ MCD_OPC_CheckPredicate, + 4, + 248, + 48, + 1, // Skip to: 104527 + /* 26455 */ MCD_OPC_Decode, + 205, + 36, + 22, // Opcode: SRSHL_ZPmZ_H + /* 26459 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 26473 + /* 26464 */ MCD_OPC_CheckPredicate, + 4, + 234, + 48, + 1, // Skip to: 104527 + /* 26469 */ MCD_OPC_Decode, + 240, + 45, + 22, // Opcode: URSHL_ZPmZ_H + /* 26473 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 26487 + /* 26478 */ MCD_OPC_CheckPredicate, + 4, + 220, + 48, + 1, // Skip to: 104527 + /* 26483 */ MCD_OPC_Decode, + 201, + 36, + 22, // Opcode: SRSHLR_ZPmZ_H + /* 26487 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 26501 + /* 26492 */ MCD_OPC_CheckPredicate, + 4, + 206, + 48, + 1, // Skip to: 104527 + /* 26497 */ MCD_OPC_Decode, + 236, + 45, + 22, // Opcode: URSHLR_ZPmZ_H + /* 26501 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 26515 + /* 26506 */ MCD_OPC_CheckPredicate, + 4, + 192, + 48, + 1, // Skip to: 104527 + /* 26511 */ MCD_OPC_Decode, + 194, + 35, + 22, // Opcode: SQSHL_ZPmZ_H + /* 26515 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 26529 + /* 26520 */ MCD_OPC_CheckPredicate, + 4, + 178, + 48, + 1, // Skip to: 104527 + /* 26525 */ MCD_OPC_Decode, + 140, + 45, + 22, // Opcode: UQSHL_ZPmZ_H + /* 26529 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 26543 + /* 26534 */ MCD_OPC_CheckPredicate, + 4, + 164, + 48, + 1, // Skip to: 104527 + /* 26539 */ MCD_OPC_Decode, + 254, + 34, + 22, // Opcode: SQRSHL_ZPmZ_H + /* 26543 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 26557 + /* 26548 */ MCD_OPC_CheckPredicate, + 4, + 150, + 48, + 1, // Skip to: 104527 + /* 26553 */ MCD_OPC_Decode, + 230, + 44, + 22, // Opcode: UQRSHL_ZPmZ_H + /* 26557 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 26571 + /* 26562 */ MCD_OPC_CheckPredicate, + 4, + 136, + 48, + 1, // Skip to: 104527 + /* 26567 */ MCD_OPC_Decode, + 171, + 35, + 22, // Opcode: SQSHLR_ZPmZ_H + /* 26571 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 26585 + /* 26576 */ MCD_OPC_CheckPredicate, + 4, + 122, + 48, + 1, // Skip to: 104527 + /* 26581 */ MCD_OPC_Decode, + 132, + 45, + 22, // Opcode: UQSHLR_ZPmZ_H + /* 26585 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 26599 + /* 26590 */ MCD_OPC_CheckPredicate, + 4, + 108, + 48, + 1, // Skip to: 104527 + /* 26595 */ MCD_OPC_Decode, + 250, + 34, + 22, // Opcode: SQRSHLR_ZPmZ_H + /* 26599 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 26613 + /* 26604 */ MCD_OPC_CheckPredicate, + 4, + 94, + 48, + 1, // Skip to: 104527 + /* 26609 */ MCD_OPC_Decode, + 226, + 44, + 22, // Opcode: UQRSHLR_ZPmZ_H + /* 26613 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 26627 + /* 26618 */ MCD_OPC_CheckPredicate, + 4, + 80, + 48, + 1, // Skip to: 104527 + /* 26623 */ MCD_OPC_Decode, + 144, + 31, + 22, // Opcode: SHADD_ZPmZ_H + /* 26627 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 26641 + /* 26632 */ MCD_OPC_CheckPredicate, + 4, + 66, + 48, + 1, // Skip to: 104527 + /* 26637 */ MCD_OPC_Decode, + 240, + 42, + 22, // Opcode: UHADD_ZPmZ_H + /* 26641 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 26655 + /* 26646 */ MCD_OPC_CheckPredicate, + 4, + 52, + 48, + 1, // Skip to: 104527 + /* 26651 */ MCD_OPC_Decode, + 184, + 31, + 22, // Opcode: SHSUB_ZPmZ_H + /* 26655 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 26669 + /* 26660 */ MCD_OPC_CheckPredicate, + 4, + 38, + 48, + 1, // Skip to: 104527 + /* 26665 */ MCD_OPC_Decode, + 254, + 42, + 22, // Opcode: UHSUB_ZPmZ_H + /* 26669 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 26683 + /* 26674 */ MCD_OPC_CheckPredicate, + 4, + 24, + 48, + 1, // Skip to: 104527 + /* 26679 */ MCD_OPC_Decode, + 179, + 36, + 22, // Opcode: SRHADD_ZPmZ_H + /* 26683 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 26697 + /* 26688 */ MCD_OPC_CheckPredicate, + 4, + 10, + 48, + 1, // Skip to: 104527 + /* 26693 */ MCD_OPC_Decode, + 226, + 45, + 22, // Opcode: URHADD_ZPmZ_H + /* 26697 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 26711 + /* 26702 */ MCD_OPC_CheckPredicate, + 4, + 252, + 47, + 1, // Skip to: 104527 + /* 26707 */ MCD_OPC_Decode, + 180, + 31, + 22, // Opcode: SHSUBR_ZPmZ_H + /* 26711 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 26725 + /* 26716 */ MCD_OPC_CheckPredicate, + 4, + 238, + 47, + 1, // Skip to: 104527 + /* 26721 */ MCD_OPC_Decode, + 250, + 42, + 22, // Opcode: UHSUBR_ZPmZ_H + /* 26725 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 26739 + /* 26730 */ MCD_OPC_CheckPredicate, + 4, + 224, + 47, + 1, // Skip to: 104527 + /* 26735 */ MCD_OPC_Decode, + 142, + 33, + 22, // Opcode: SQADD_ZPmZ_H + /* 26739 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 26753 + /* 26744 */ MCD_OPC_CheckPredicate, + 4, + 210, + 47, + 1, // Skip to: 104527 + /* 26749 */ MCD_OPC_Decode, + 163, + 44, + 22, // Opcode: UQADD_ZPmZ_H + /* 26753 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 26767 + /* 26758 */ MCD_OPC_CheckPredicate, + 4, + 196, + 47, + 1, // Skip to: 104527 + /* 26763 */ MCD_OPC_Decode, + 130, + 36, + 22, // Opcode: SQSUB_ZPmZ_H + /* 26767 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 26781 + /* 26772 */ MCD_OPC_CheckPredicate, + 4, + 182, + 47, + 1, // Skip to: 104527 + /* 26777 */ MCD_OPC_Decode, + 189, + 45, + 22, // Opcode: UQSUB_ZPmZ_H + /* 26781 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 26795 + /* 26786 */ MCD_OPC_CheckPredicate, + 4, + 168, + 47, + 1, // Skip to: 104527 + /* 26791 */ MCD_OPC_Decode, + 239, + 40, + 22, // Opcode: SUQADD_ZPmZ_H + /* 26795 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 26809 + /* 26800 */ MCD_OPC_CheckPredicate, + 4, + 154, + 47, + 1, // Skip to: 104527 + /* 26805 */ MCD_OPC_Decode, + 191, + 46, + 22, // Opcode: USQADD_ZPmZ_H + /* 26809 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 26823 + /* 26814 */ MCD_OPC_CheckPredicate, + 4, + 140, + 47, + 1, // Skip to: 104527 + /* 26819 */ MCD_OPC_Decode, + 250, + 35, + 22, // Opcode: SQSUBR_ZPmZ_H + /* 26823 */ MCD_OPC_FilterValue, + 31, + 131, + 47, + 1, // Skip to: 104527 + /* 26828 */ MCD_OPC_CheckPredicate, + 4, + 126, + 47, + 1, // Skip to: 104527 + /* 26833 */ MCD_OPC_Decode, + 181, + 45, + 22, // Opcode: UQSUBR_ZPmZ_H + /* 26837 */ MCD_OPC_FilterValue, + 4, + 139, + 1, + 0, // Skip to: 27237 + /* 26842 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 26845 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 26859 + /* 26850 */ MCD_OPC_CheckPredicate, + 4, + 104, + 47, + 1, // Skip to: 104527 + /* 26855 */ MCD_OPC_Decode, + 206, + 36, + 22, // Opcode: SRSHL_ZPmZ_S + /* 26859 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 26873 + /* 26864 */ MCD_OPC_CheckPredicate, + 4, + 90, + 47, + 1, // Skip to: 104527 + /* 26869 */ MCD_OPC_Decode, + 241, + 45, + 22, // Opcode: URSHL_ZPmZ_S + /* 26873 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 26887 + /* 26878 */ MCD_OPC_CheckPredicate, + 4, + 76, + 47, + 1, // Skip to: 104527 + /* 26883 */ MCD_OPC_Decode, + 202, + 36, + 22, // Opcode: SRSHLR_ZPmZ_S + /* 26887 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 26901 + /* 26892 */ MCD_OPC_CheckPredicate, + 4, + 62, + 47, + 1, // Skip to: 104527 + /* 26897 */ MCD_OPC_Decode, + 237, + 45, + 22, // Opcode: URSHLR_ZPmZ_S + /* 26901 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 26915 + /* 26906 */ MCD_OPC_CheckPredicate, + 4, + 48, + 47, + 1, // Skip to: 104527 + /* 26911 */ MCD_OPC_Decode, + 195, + 35, + 22, // Opcode: SQSHL_ZPmZ_S + /* 26915 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 26929 + /* 26920 */ MCD_OPC_CheckPredicate, + 4, + 34, + 47, + 1, // Skip to: 104527 + /* 26925 */ MCD_OPC_Decode, + 141, + 45, + 22, // Opcode: UQSHL_ZPmZ_S + /* 26929 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 26943 + /* 26934 */ MCD_OPC_CheckPredicate, + 4, + 20, + 47, + 1, // Skip to: 104527 + /* 26939 */ MCD_OPC_Decode, + 255, + 34, + 22, // Opcode: SQRSHL_ZPmZ_S + /* 26943 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 26957 + /* 26948 */ MCD_OPC_CheckPredicate, + 4, + 6, + 47, + 1, // Skip to: 104527 + /* 26953 */ MCD_OPC_Decode, + 231, + 44, + 22, // Opcode: UQRSHL_ZPmZ_S + /* 26957 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 26971 + /* 26962 */ MCD_OPC_CheckPredicate, + 4, + 248, + 46, + 1, // Skip to: 104527 + /* 26967 */ MCD_OPC_Decode, + 172, + 35, + 22, // Opcode: SQSHLR_ZPmZ_S + /* 26971 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 26985 + /* 26976 */ MCD_OPC_CheckPredicate, + 4, + 234, + 46, + 1, // Skip to: 104527 + /* 26981 */ MCD_OPC_Decode, + 133, + 45, + 22, // Opcode: UQSHLR_ZPmZ_S + /* 26985 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 26999 + /* 26990 */ MCD_OPC_CheckPredicate, + 4, + 220, + 46, + 1, // Skip to: 104527 + /* 26995 */ MCD_OPC_Decode, + 251, + 34, + 22, // Opcode: SQRSHLR_ZPmZ_S + /* 26999 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 27013 + /* 27004 */ MCD_OPC_CheckPredicate, + 4, + 206, + 46, + 1, // Skip to: 104527 + /* 27009 */ MCD_OPC_Decode, + 227, + 44, + 22, // Opcode: UQRSHLR_ZPmZ_S + /* 27013 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 27027 + /* 27018 */ MCD_OPC_CheckPredicate, + 4, + 192, + 46, + 1, // Skip to: 104527 + /* 27023 */ MCD_OPC_Decode, + 145, + 31, + 22, // Opcode: SHADD_ZPmZ_S + /* 27027 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 27041 + /* 27032 */ MCD_OPC_CheckPredicate, + 4, + 178, + 46, + 1, // Skip to: 104527 + /* 27037 */ MCD_OPC_Decode, + 241, + 42, + 22, // Opcode: UHADD_ZPmZ_S + /* 27041 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 27055 + /* 27046 */ MCD_OPC_CheckPredicate, + 4, + 164, + 46, + 1, // Skip to: 104527 + /* 27051 */ MCD_OPC_Decode, + 185, + 31, + 22, // Opcode: SHSUB_ZPmZ_S + /* 27055 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 27069 + /* 27060 */ MCD_OPC_CheckPredicate, + 4, + 150, + 46, + 1, // Skip to: 104527 + /* 27065 */ MCD_OPC_Decode, + 255, + 42, + 22, // Opcode: UHSUB_ZPmZ_S + /* 27069 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 27083 + /* 27074 */ MCD_OPC_CheckPredicate, + 4, + 136, + 46, + 1, // Skip to: 104527 + /* 27079 */ MCD_OPC_Decode, + 180, + 36, + 22, // Opcode: SRHADD_ZPmZ_S + /* 27083 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 27097 + /* 27088 */ MCD_OPC_CheckPredicate, + 4, + 122, + 46, + 1, // Skip to: 104527 + /* 27093 */ MCD_OPC_Decode, + 227, + 45, + 22, // Opcode: URHADD_ZPmZ_S + /* 27097 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 27111 + /* 27102 */ MCD_OPC_CheckPredicate, + 4, + 108, + 46, + 1, // Skip to: 104527 + /* 27107 */ MCD_OPC_Decode, + 181, + 31, + 22, // Opcode: SHSUBR_ZPmZ_S + /* 27111 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 27125 + /* 27116 */ MCD_OPC_CheckPredicate, + 4, + 94, + 46, + 1, // Skip to: 104527 + /* 27121 */ MCD_OPC_Decode, + 251, + 42, + 22, // Opcode: UHSUBR_ZPmZ_S + /* 27125 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 27139 + /* 27130 */ MCD_OPC_CheckPredicate, + 4, + 80, + 46, + 1, // Skip to: 104527 + /* 27135 */ MCD_OPC_Decode, + 143, + 33, + 22, // Opcode: SQADD_ZPmZ_S + /* 27139 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 27153 + /* 27144 */ MCD_OPC_CheckPredicate, + 4, + 66, + 46, + 1, // Skip to: 104527 + /* 27149 */ MCD_OPC_Decode, + 164, + 44, + 22, // Opcode: UQADD_ZPmZ_S + /* 27153 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 27167 + /* 27158 */ MCD_OPC_CheckPredicate, + 4, + 52, + 46, + 1, // Skip to: 104527 + /* 27163 */ MCD_OPC_Decode, + 131, + 36, + 22, // Opcode: SQSUB_ZPmZ_S + /* 27167 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 27181 + /* 27172 */ MCD_OPC_CheckPredicate, + 4, + 38, + 46, + 1, // Skip to: 104527 + /* 27177 */ MCD_OPC_Decode, + 190, + 45, + 22, // Opcode: UQSUB_ZPmZ_S + /* 27181 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 27195 + /* 27186 */ MCD_OPC_CheckPredicate, + 4, + 24, + 46, + 1, // Skip to: 104527 + /* 27191 */ MCD_OPC_Decode, + 240, + 40, + 22, // Opcode: SUQADD_ZPmZ_S + /* 27195 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 27209 + /* 27200 */ MCD_OPC_CheckPredicate, + 4, + 10, + 46, + 1, // Skip to: 104527 + /* 27205 */ MCD_OPC_Decode, + 192, + 46, + 22, // Opcode: USQADD_ZPmZ_S + /* 27209 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 27223 + /* 27214 */ MCD_OPC_CheckPredicate, + 4, + 252, + 45, + 1, // Skip to: 104527 + /* 27219 */ MCD_OPC_Decode, + 251, + 35, + 22, // Opcode: SQSUBR_ZPmZ_S + /* 27223 */ MCD_OPC_FilterValue, + 31, + 243, + 45, + 1, // Skip to: 104527 + /* 27228 */ MCD_OPC_CheckPredicate, + 4, + 238, + 45, + 1, // Skip to: 104527 + /* 27233 */ MCD_OPC_Decode, + 182, + 45, + 22, // Opcode: UQSUBR_ZPmZ_S + /* 27237 */ MCD_OPC_FilterValue, + 5, + 79, + 0, + 0, // Skip to: 27321 + /* 27242 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 27245 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 27283 + /* 27250 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 27253 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 27268 + /* 27258 */ MCD_OPC_CheckPredicate, + 4, + 208, + 45, + 1, // Skip to: 104527 + /* 27263 */ MCD_OPC_Decode, + 156, + 32, + 149, + 1, // Opcode: SMLALB_ZZZI_S + /* 27268 */ MCD_OPC_FilterValue, + 1, + 198, + 45, + 1, // Skip to: 104527 + /* 27273 */ MCD_OPC_CheckPredicate, + 4, + 193, + 45, + 1, // Skip to: 104527 + /* 27278 */ MCD_OPC_Decode, + 202, + 43, + 149, + 1, // Opcode: UMLALB_ZZZI_S + /* 27283 */ MCD_OPC_FilterValue, + 1, + 183, + 45, + 1, // Skip to: 104527 + /* 27288 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 27291 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 27306 + /* 27296 */ MCD_OPC_CheckPredicate, + 4, + 170, + 45, + 1, // Skip to: 104527 + /* 27301 */ MCD_OPC_Decode, + 161, + 32, + 149, + 1, // Opcode: SMLALT_ZZZI_S + /* 27306 */ MCD_OPC_FilterValue, + 1, + 160, + 45, + 1, // Skip to: 104527 + /* 27311 */ MCD_OPC_CheckPredicate, + 4, + 155, + 45, + 1, // Skip to: 104527 + /* 27316 */ MCD_OPC_Decode, + 207, + 43, + 149, + 1, // Opcode: UMLALT_ZZZI_S + /* 27321 */ MCD_OPC_FilterValue, + 6, + 139, + 1, + 0, // Skip to: 27721 + /* 27326 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 27329 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 27343 + /* 27334 */ MCD_OPC_CheckPredicate, + 4, + 132, + 45, + 1, // Skip to: 104527 + /* 27339 */ MCD_OPC_Decode, + 204, + 36, + 22, // Opcode: SRSHL_ZPmZ_D + /* 27343 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 27357 + /* 27348 */ MCD_OPC_CheckPredicate, + 4, + 118, + 45, + 1, // Skip to: 104527 + /* 27353 */ MCD_OPC_Decode, + 239, + 45, + 22, // Opcode: URSHL_ZPmZ_D + /* 27357 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 27371 + /* 27362 */ MCD_OPC_CheckPredicate, + 4, + 104, + 45, + 1, // Skip to: 104527 + /* 27367 */ MCD_OPC_Decode, + 200, + 36, + 22, // Opcode: SRSHLR_ZPmZ_D + /* 27371 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 27385 + /* 27376 */ MCD_OPC_CheckPredicate, + 4, + 90, + 45, + 1, // Skip to: 104527 + /* 27381 */ MCD_OPC_Decode, + 235, + 45, + 22, // Opcode: URSHLR_ZPmZ_D + /* 27385 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 27399 + /* 27390 */ MCD_OPC_CheckPredicate, + 4, + 76, + 45, + 1, // Skip to: 104527 + /* 27395 */ MCD_OPC_Decode, + 193, + 35, + 22, // Opcode: SQSHL_ZPmZ_D + /* 27399 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 27413 + /* 27404 */ MCD_OPC_CheckPredicate, + 4, + 62, + 45, + 1, // Skip to: 104527 + /* 27409 */ MCD_OPC_Decode, + 139, + 45, + 22, // Opcode: UQSHL_ZPmZ_D + /* 27413 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 27427 + /* 27418 */ MCD_OPC_CheckPredicate, + 4, + 48, + 45, + 1, // Skip to: 104527 + /* 27423 */ MCD_OPC_Decode, + 253, + 34, + 22, // Opcode: SQRSHL_ZPmZ_D + /* 27427 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 27441 + /* 27432 */ MCD_OPC_CheckPredicate, + 4, + 34, + 45, + 1, // Skip to: 104527 + /* 27437 */ MCD_OPC_Decode, + 229, + 44, + 22, // Opcode: UQRSHL_ZPmZ_D + /* 27441 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 27455 + /* 27446 */ MCD_OPC_CheckPredicate, + 4, + 20, + 45, + 1, // Skip to: 104527 + /* 27451 */ MCD_OPC_Decode, + 170, + 35, + 22, // Opcode: SQSHLR_ZPmZ_D + /* 27455 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 27469 + /* 27460 */ MCD_OPC_CheckPredicate, + 4, + 6, + 45, + 1, // Skip to: 104527 + /* 27465 */ MCD_OPC_Decode, + 131, + 45, + 22, // Opcode: UQSHLR_ZPmZ_D + /* 27469 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 27483 + /* 27474 */ MCD_OPC_CheckPredicate, + 4, + 248, + 44, + 1, // Skip to: 104527 + /* 27479 */ MCD_OPC_Decode, + 249, + 34, + 22, // Opcode: SQRSHLR_ZPmZ_D + /* 27483 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 27497 + /* 27488 */ MCD_OPC_CheckPredicate, + 4, + 234, + 44, + 1, // Skip to: 104527 + /* 27493 */ MCD_OPC_Decode, + 225, + 44, + 22, // Opcode: UQRSHLR_ZPmZ_D + /* 27497 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 27511 + /* 27502 */ MCD_OPC_CheckPredicate, + 4, + 220, + 44, + 1, // Skip to: 104527 + /* 27507 */ MCD_OPC_Decode, + 143, + 31, + 22, // Opcode: SHADD_ZPmZ_D + /* 27511 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 27525 + /* 27516 */ MCD_OPC_CheckPredicate, + 4, + 206, + 44, + 1, // Skip to: 104527 + /* 27521 */ MCD_OPC_Decode, + 239, + 42, + 22, // Opcode: UHADD_ZPmZ_D + /* 27525 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 27539 + /* 27530 */ MCD_OPC_CheckPredicate, + 4, + 192, + 44, + 1, // Skip to: 104527 + /* 27535 */ MCD_OPC_Decode, + 183, + 31, + 22, // Opcode: SHSUB_ZPmZ_D + /* 27539 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 27553 + /* 27544 */ MCD_OPC_CheckPredicate, + 4, + 178, + 44, + 1, // Skip to: 104527 + /* 27549 */ MCD_OPC_Decode, + 253, + 42, + 22, // Opcode: UHSUB_ZPmZ_D + /* 27553 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 27567 + /* 27558 */ MCD_OPC_CheckPredicate, + 4, + 164, + 44, + 1, // Skip to: 104527 + /* 27563 */ MCD_OPC_Decode, + 178, + 36, + 22, // Opcode: SRHADD_ZPmZ_D + /* 27567 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 27581 + /* 27572 */ MCD_OPC_CheckPredicate, + 4, + 150, + 44, + 1, // Skip to: 104527 + /* 27577 */ MCD_OPC_Decode, + 225, + 45, + 22, // Opcode: URHADD_ZPmZ_D + /* 27581 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 27595 + /* 27586 */ MCD_OPC_CheckPredicate, + 4, + 136, + 44, + 1, // Skip to: 104527 + /* 27591 */ MCD_OPC_Decode, + 179, + 31, + 22, // Opcode: SHSUBR_ZPmZ_D + /* 27595 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 27609 + /* 27600 */ MCD_OPC_CheckPredicate, + 4, + 122, + 44, + 1, // Skip to: 104527 + /* 27605 */ MCD_OPC_Decode, + 249, + 42, + 22, // Opcode: UHSUBR_ZPmZ_D + /* 27609 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 27623 + /* 27614 */ MCD_OPC_CheckPredicate, + 4, + 108, + 44, + 1, // Skip to: 104527 + /* 27619 */ MCD_OPC_Decode, + 141, + 33, + 22, // Opcode: SQADD_ZPmZ_D + /* 27623 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 27637 + /* 27628 */ MCD_OPC_CheckPredicate, + 4, + 94, + 44, + 1, // Skip to: 104527 + /* 27633 */ MCD_OPC_Decode, + 162, + 44, + 22, // Opcode: UQADD_ZPmZ_D + /* 27637 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 27651 + /* 27642 */ MCD_OPC_CheckPredicate, + 4, + 80, + 44, + 1, // Skip to: 104527 + /* 27647 */ MCD_OPC_Decode, + 129, + 36, + 22, // Opcode: SQSUB_ZPmZ_D + /* 27651 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 27665 + /* 27656 */ MCD_OPC_CheckPredicate, + 4, + 66, + 44, + 1, // Skip to: 104527 + /* 27661 */ MCD_OPC_Decode, + 188, + 45, + 22, // Opcode: UQSUB_ZPmZ_D + /* 27665 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 27679 + /* 27670 */ MCD_OPC_CheckPredicate, + 4, + 52, + 44, + 1, // Skip to: 104527 + /* 27675 */ MCD_OPC_Decode, + 238, + 40, + 22, // Opcode: SUQADD_ZPmZ_D + /* 27679 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 27693 + /* 27684 */ MCD_OPC_CheckPredicate, + 4, + 38, + 44, + 1, // Skip to: 104527 + /* 27689 */ MCD_OPC_Decode, + 190, + 46, + 22, // Opcode: USQADD_ZPmZ_D + /* 27693 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 27707 + /* 27698 */ MCD_OPC_CheckPredicate, + 4, + 24, + 44, + 1, // Skip to: 104527 + /* 27703 */ MCD_OPC_Decode, + 249, + 35, + 22, // Opcode: SQSUBR_ZPmZ_D + /* 27707 */ MCD_OPC_FilterValue, + 31, + 15, + 44, + 1, // Skip to: 104527 + /* 27712 */ MCD_OPC_CheckPredicate, + 4, + 10, + 44, + 1, // Skip to: 104527 + /* 27717 */ MCD_OPC_Decode, + 180, + 45, + 22, // Opcode: UQSUBR_ZPmZ_D + /* 27721 */ MCD_OPC_FilterValue, + 7, + 79, + 0, + 0, // Skip to: 27805 + /* 27726 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 27729 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 27767 + /* 27734 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 27737 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 27752 + /* 27742 */ MCD_OPC_CheckPredicate, + 4, + 236, + 43, + 1, // Skip to: 104527 + /* 27747 */ MCD_OPC_Decode, + 155, + 32, + 150, + 1, // Opcode: SMLALB_ZZZI_D + /* 27752 */ MCD_OPC_FilterValue, + 1, + 226, + 43, + 1, // Skip to: 104527 + /* 27757 */ MCD_OPC_CheckPredicate, + 4, + 221, + 43, + 1, // Skip to: 104527 + /* 27762 */ MCD_OPC_Decode, + 201, + 43, + 150, + 1, // Opcode: UMLALB_ZZZI_D + /* 27767 */ MCD_OPC_FilterValue, + 1, + 211, + 43, + 1, // Skip to: 104527 + /* 27772 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 27775 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 27790 + /* 27780 */ MCD_OPC_CheckPredicate, + 4, + 198, + 43, + 1, // Skip to: 104527 + /* 27785 */ MCD_OPC_Decode, + 160, + 32, + 150, + 1, // Opcode: SMLALT_ZZZI_D + /* 27790 */ MCD_OPC_FilterValue, + 1, + 188, + 43, + 1, // Skip to: 104527 + /* 27795 */ MCD_OPC_CheckPredicate, + 4, + 183, + 43, + 1, // Skip to: 104527 + /* 27800 */ MCD_OPC_Decode, + 206, + 43, + 150, + 1, // Opcode: UMLALT_ZZZI_D + /* 27805 */ MCD_OPC_FilterValue, + 8, + 45, + 0, + 0, // Skip to: 27855 + /* 27810 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 27813 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 27827 + /* 27818 */ MCD_OPC_CheckPredicate, + 4, + 160, + 43, + 1, // Skip to: 104527 + /* 27823 */ MCD_OPC_Decode, + 155, + 12, + 54, // Opcode: EORBT_ZZZ_B + /* 27827 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 27841 + /* 27832 */ MCD_OPC_CheckPredicate, + 4, + 146, + 43, + 1, // Skip to: 104527 + /* 27837 */ MCD_OPC_Decode, + 160, + 12, + 54, // Opcode: EORTB_ZZZ_B + /* 27841 */ MCD_OPC_FilterValue, + 6, + 137, + 43, + 1, // Skip to: 104527 + /* 27846 */ MCD_OPC_CheckPredicate, + 9, + 132, + 43, + 1, // Skip to: 104527 + /* 27851 */ MCD_OPC_Decode, + 196, + 32, + 54, // Opcode: SMMLA_ZZZ + /* 27855 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 27891 + /* 27860 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 27863 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 27877 + /* 27868 */ MCD_OPC_CheckPredicate, + 10, + 110, + 43, + 1, // Skip to: 104527 + /* 27873 */ MCD_OPC_Decode, + 140, + 27, + 109, // Opcode: MATCH_PPzZZ_B + /* 27877 */ MCD_OPC_FilterValue, + 1, + 101, + 43, + 1, // Skip to: 104527 + /* 27882 */ MCD_OPC_CheckPredicate, + 10, + 96, + 43, + 1, // Skip to: 104527 + /* 27887 */ MCD_OPC_Decode, + 130, + 28, + 109, // Opcode: NMATCH_PPzZZ_B + /* 27891 */ MCD_OPC_FilterValue, + 10, + 73, + 0, + 0, // Skip to: 27969 + /* 27896 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 27899 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 27913 + /* 27904 */ MCD_OPC_CheckPredicate, + 4, + 74, + 43, + 1, // Skip to: 104527 + /* 27909 */ MCD_OPC_Decode, + 144, + 30, + 45, // Opcode: SADDLBT_ZZZ_H + /* 27913 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 27927 + /* 27918 */ MCD_OPC_CheckPredicate, + 4, + 60, + 43, + 1, // Skip to: 104527 + /* 27923 */ MCD_OPC_Decode, + 190, + 37, + 45, // Opcode: SSUBLBT_ZZZ_H + /* 27927 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 27941 + /* 27932 */ MCD_OPC_CheckPredicate, + 4, + 46, + 43, + 1, // Skip to: 104527 + /* 27937 */ MCD_OPC_Decode, + 196, + 37, + 45, // Opcode: SSUBLTB_ZZZ_H + /* 27941 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 27955 + /* 27946 */ MCD_OPC_CheckPredicate, + 4, + 32, + 43, + 1, // Skip to: 104527 + /* 27951 */ MCD_OPC_Decode, + 157, + 12, + 54, // Opcode: EORBT_ZZZ_H + /* 27955 */ MCD_OPC_FilterValue, + 5, + 23, + 43, + 1, // Skip to: 104527 + /* 27960 */ MCD_OPC_CheckPredicate, + 4, + 18, + 43, + 1, // Skip to: 104527 + /* 27965 */ MCD_OPC_Decode, + 162, + 12, + 54, // Opcode: EORTB_ZZZ_H + /* 27969 */ MCD_OPC_FilterValue, + 11, + 31, + 0, + 0, // Skip to: 28005 + /* 27974 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 27977 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 27991 + /* 27982 */ MCD_OPC_CheckPredicate, + 10, + 252, + 42, + 1, // Skip to: 104527 + /* 27987 */ MCD_OPC_Decode, + 141, + 27, + 109, // Opcode: MATCH_PPzZZ_H + /* 27991 */ MCD_OPC_FilterValue, + 1, + 243, + 42, + 1, // Skip to: 104527 + /* 27996 */ MCD_OPC_CheckPredicate, + 10, + 238, + 42, + 1, // Skip to: 104527 + /* 28001 */ MCD_OPC_Decode, + 131, + 28, + 109, // Opcode: NMATCH_PPzZZ_H + /* 28005 */ MCD_OPC_FilterValue, + 12, + 87, + 0, + 0, // Skip to: 28097 + /* 28010 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 28013 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 28027 + /* 28018 */ MCD_OPC_CheckPredicate, + 4, + 216, + 42, + 1, // Skip to: 104527 + /* 28023 */ MCD_OPC_Decode, + 145, + 30, + 45, // Opcode: SADDLBT_ZZZ_S + /* 28027 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 28041 + /* 28032 */ MCD_OPC_CheckPredicate, + 4, + 202, + 42, + 1, // Skip to: 104527 + /* 28037 */ MCD_OPC_Decode, + 191, + 37, + 45, // Opcode: SSUBLBT_ZZZ_S + /* 28041 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 28055 + /* 28046 */ MCD_OPC_CheckPredicate, + 4, + 188, + 42, + 1, // Skip to: 104527 + /* 28051 */ MCD_OPC_Decode, + 197, + 37, + 45, // Opcode: SSUBLTB_ZZZ_S + /* 28055 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 28069 + /* 28060 */ MCD_OPC_CheckPredicate, + 4, + 174, + 42, + 1, // Skip to: 104527 + /* 28065 */ MCD_OPC_Decode, + 158, + 12, + 54, // Opcode: EORBT_ZZZ_S + /* 28069 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 28083 + /* 28074 */ MCD_OPC_CheckPredicate, + 4, + 160, + 42, + 1, // Skip to: 104527 + /* 28079 */ MCD_OPC_Decode, + 163, + 12, + 54, // Opcode: EORTB_ZZZ_S + /* 28083 */ MCD_OPC_FilterValue, + 6, + 151, + 42, + 1, // Skip to: 104527 + /* 28088 */ MCD_OPC_CheckPredicate, + 9, + 146, + 42, + 1, // Skip to: 104527 + /* 28093 */ MCD_OPC_Decode, + 184, + 46, + 54, // Opcode: USMMLA_ZZZ + /* 28097 */ MCD_OPC_FilterValue, + 14, + 137, + 42, + 1, // Skip to: 104527 + /* 28102 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 28105 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 28119 + /* 28110 */ MCD_OPC_CheckPredicate, + 4, + 124, + 42, + 1, // Skip to: 104527 + /* 28115 */ MCD_OPC_Decode, + 143, + 30, + 45, // Opcode: SADDLBT_ZZZ_D + /* 28119 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 28133 + /* 28124 */ MCD_OPC_CheckPredicate, + 4, + 110, + 42, + 1, // Skip to: 104527 + /* 28129 */ MCD_OPC_Decode, + 189, + 37, + 45, // Opcode: SSUBLBT_ZZZ_D + /* 28133 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 28147 + /* 28138 */ MCD_OPC_CheckPredicate, + 4, + 96, + 42, + 1, // Skip to: 104527 + /* 28143 */ MCD_OPC_Decode, + 195, + 37, + 45, // Opcode: SSUBLTB_ZZZ_D + /* 28147 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 28161 + /* 28152 */ MCD_OPC_CheckPredicate, + 4, + 82, + 42, + 1, // Skip to: 104527 + /* 28157 */ MCD_OPC_Decode, + 156, + 12, + 54, // Opcode: EORBT_ZZZ_D + /* 28161 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 28175 + /* 28166 */ MCD_OPC_CheckPredicate, + 4, + 68, + 42, + 1, // Skip to: 104527 + /* 28171 */ MCD_OPC_Decode, + 161, + 12, + 54, // Opcode: EORTB_ZZZ_D + /* 28175 */ MCD_OPC_FilterValue, + 6, + 59, + 42, + 1, // Skip to: 104527 + /* 28180 */ MCD_OPC_CheckPredicate, + 9, + 54, + 42, + 1, // Skip to: 104527 + /* 28185 */ MCD_OPC_Decode, + 242, + 43, + 54, // Opcode: UMMLA_ZZZ + /* 28189 */ MCD_OPC_FilterValue, + 5, + 132, + 4, + 0, // Skip to: 29350 + /* 28194 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 28197 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 28303 + /* 28202 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 28205 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 28219 + /* 28210 */ MCD_OPC_CheckPredicate, + 4, + 24, + 42, + 1, // Skip to: 104527 + /* 28215 */ MCD_OPC_Decode, + 249, + 32, + 24, // Opcode: SQABS_ZPmZ_B + /* 28219 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 28233 + /* 28224 */ MCD_OPC_CheckPredicate, + 4, + 10, + 42, + 1, // Skip to: 104527 + /* 28229 */ MCD_OPC_Decode, + 170, + 34, + 24, // Opcode: SQNEG_ZPmZ_B + /* 28233 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 28247 + /* 28238 */ MCD_OPC_CheckPredicate, + 4, + 252, + 41, + 1, // Skip to: 104527 + /* 28243 */ MCD_OPC_Decode, + 164, + 7, + 22, // Opcode: ADDP_ZPmZ_B + /* 28247 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 28261 + /* 28252 */ MCD_OPC_CheckPredicate, + 4, + 238, + 41, + 1, // Skip to: 104527 + /* 28257 */ MCD_OPC_Decode, + 216, + 31, + 22, // Opcode: SMAXP_ZPmZ_B + /* 28261 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 28275 + /* 28266 */ MCD_OPC_CheckPredicate, + 4, + 224, + 41, + 1, // Skip to: 104527 + /* 28271 */ MCD_OPC_Decode, + 135, + 43, + 22, // Opcode: UMAXP_ZPmZ_B + /* 28275 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 28289 + /* 28280 */ MCD_OPC_CheckPredicate, + 4, + 210, + 41, + 1, // Skip to: 104527 + /* 28285 */ MCD_OPC_Decode, + 250, + 31, + 22, // Opcode: SMINP_ZPmZ_B + /* 28289 */ MCD_OPC_FilterValue, + 23, + 201, + 41, + 1, // Skip to: 104527 + /* 28294 */ MCD_OPC_CheckPredicate, + 4, + 196, + 41, + 1, // Skip to: 104527 + /* 28299 */ MCD_OPC_Decode, + 168, + 43, + 22, // Opcode: UMINP_ZPmZ_B + /* 28303 */ MCD_OPC_FilterValue, + 2, + 129, + 0, + 0, // Skip to: 28437 + /* 28308 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 28311 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 28325 + /* 28316 */ MCD_OPC_CheckPredicate, + 4, + 174, + 41, + 1, // Skip to: 104527 + /* 28321 */ MCD_OPC_Decode, + 135, + 30, + 22, // Opcode: SADALP_ZPmZ_H + /* 28325 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 28339 + /* 28330 */ MCD_OPC_CheckPredicate, + 4, + 160, + 41, + 1, // Skip to: 104527 + /* 28335 */ MCD_OPC_Decode, + 135, + 42, + 22, // Opcode: UADALP_ZPmZ_H + /* 28339 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 28353 + /* 28344 */ MCD_OPC_CheckPredicate, + 4, + 146, + 41, + 1, // Skip to: 104527 + /* 28349 */ MCD_OPC_Decode, + 251, + 32, + 24, // Opcode: SQABS_ZPmZ_H + /* 28353 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 28367 + /* 28358 */ MCD_OPC_CheckPredicate, + 4, + 132, + 41, + 1, // Skip to: 104527 + /* 28363 */ MCD_OPC_Decode, + 172, + 34, + 24, // Opcode: SQNEG_ZPmZ_H + /* 28367 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 28381 + /* 28372 */ MCD_OPC_CheckPredicate, + 4, + 118, + 41, + 1, // Skip to: 104527 + /* 28377 */ MCD_OPC_Decode, + 166, + 7, + 22, // Opcode: ADDP_ZPmZ_H + /* 28381 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 28395 + /* 28386 */ MCD_OPC_CheckPredicate, + 4, + 104, + 41, + 1, // Skip to: 104527 + /* 28391 */ MCD_OPC_Decode, + 218, + 31, + 22, // Opcode: SMAXP_ZPmZ_H + /* 28395 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 28409 + /* 28400 */ MCD_OPC_CheckPredicate, + 4, + 90, + 41, + 1, // Skip to: 104527 + /* 28405 */ MCD_OPC_Decode, + 137, + 43, + 22, // Opcode: UMAXP_ZPmZ_H + /* 28409 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 28423 + /* 28414 */ MCD_OPC_CheckPredicate, + 4, + 76, + 41, + 1, // Skip to: 104527 + /* 28419 */ MCD_OPC_Decode, + 252, + 31, + 22, // Opcode: SMINP_ZPmZ_H + /* 28423 */ MCD_OPC_FilterValue, + 23, + 67, + 41, + 1, // Skip to: 104527 + /* 28428 */ MCD_OPC_CheckPredicate, + 4, + 62, + 41, + 1, // Skip to: 104527 + /* 28433 */ MCD_OPC_Decode, + 170, + 43, + 22, // Opcode: UMINP_ZPmZ_H + /* 28437 */ MCD_OPC_FilterValue, + 4, + 157, + 0, + 0, // Skip to: 28599 + /* 28442 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 28445 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 28459 + /* 28450 */ MCD_OPC_CheckPredicate, + 4, + 40, + 41, + 1, // Skip to: 104527 + /* 28455 */ MCD_OPC_Decode, + 221, + 45, + 24, // Opcode: URECPE_ZPmZ_S + /* 28459 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 28473 + /* 28464 */ MCD_OPC_CheckPredicate, + 4, + 26, + 41, + 1, // Skip to: 104527 + /* 28469 */ MCD_OPC_Decode, + 134, + 46, + 24, // Opcode: URSQRTE_ZPmZ_S + /* 28473 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 28487 + /* 28478 */ MCD_OPC_CheckPredicate, + 4, + 12, + 41, + 1, // Skip to: 104527 + /* 28483 */ MCD_OPC_Decode, + 136, + 30, + 22, // Opcode: SADALP_ZPmZ_S + /* 28487 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 28501 + /* 28492 */ MCD_OPC_CheckPredicate, + 4, + 254, + 40, + 1, // Skip to: 104527 + /* 28497 */ MCD_OPC_Decode, + 136, + 42, + 22, // Opcode: UADALP_ZPmZ_S + /* 28501 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 28515 + /* 28506 */ MCD_OPC_CheckPredicate, + 4, + 240, + 40, + 1, // Skip to: 104527 + /* 28511 */ MCD_OPC_Decode, + 252, + 32, + 24, // Opcode: SQABS_ZPmZ_S + /* 28515 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 28529 + /* 28520 */ MCD_OPC_CheckPredicate, + 4, + 226, + 40, + 1, // Skip to: 104527 + /* 28525 */ MCD_OPC_Decode, + 173, + 34, + 24, // Opcode: SQNEG_ZPmZ_S + /* 28529 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 28543 + /* 28534 */ MCD_OPC_CheckPredicate, + 4, + 212, + 40, + 1, // Skip to: 104527 + /* 28539 */ MCD_OPC_Decode, + 167, + 7, + 22, // Opcode: ADDP_ZPmZ_S + /* 28543 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 28557 + /* 28548 */ MCD_OPC_CheckPredicate, + 4, + 198, + 40, + 1, // Skip to: 104527 + /* 28553 */ MCD_OPC_Decode, + 219, + 31, + 22, // Opcode: SMAXP_ZPmZ_S + /* 28557 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 28571 + /* 28562 */ MCD_OPC_CheckPredicate, + 4, + 184, + 40, + 1, // Skip to: 104527 + /* 28567 */ MCD_OPC_Decode, + 138, + 43, + 22, // Opcode: UMAXP_ZPmZ_S + /* 28571 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 28585 + /* 28576 */ MCD_OPC_CheckPredicate, + 4, + 170, + 40, + 1, // Skip to: 104527 + /* 28581 */ MCD_OPC_Decode, + 253, + 31, + 22, // Opcode: SMINP_ZPmZ_S + /* 28585 */ MCD_OPC_FilterValue, + 23, + 161, + 40, + 1, // Skip to: 104527 + /* 28590 */ MCD_OPC_CheckPredicate, + 4, + 156, + 40, + 1, // Skip to: 104527 + /* 28595 */ MCD_OPC_Decode, + 171, + 43, + 22, // Opcode: UMINP_ZPmZ_S + /* 28599 */ MCD_OPC_FilterValue, + 5, + 79, + 0, + 0, // Skip to: 28683 + /* 28604 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 28607 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 28645 + /* 28612 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 28615 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 28630 + /* 28620 */ MCD_OPC_CheckPredicate, + 4, + 126, + 40, + 1, // Skip to: 104527 + /* 28625 */ MCD_OPC_Decode, + 176, + 32, + 149, + 1, // Opcode: SMLSLB_ZZZI_S + /* 28630 */ MCD_OPC_FilterValue, + 1, + 116, + 40, + 1, // Skip to: 104527 + /* 28635 */ MCD_OPC_CheckPredicate, + 4, + 111, + 40, + 1, // Skip to: 104527 + /* 28640 */ MCD_OPC_Decode, + 222, + 43, + 149, + 1, // Opcode: UMLSLB_ZZZI_S + /* 28645 */ MCD_OPC_FilterValue, + 1, + 101, + 40, + 1, // Skip to: 104527 + /* 28650 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 28653 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 28668 + /* 28658 */ MCD_OPC_CheckPredicate, + 4, + 88, + 40, + 1, // Skip to: 104527 + /* 28663 */ MCD_OPC_Decode, + 181, + 32, + 149, + 1, // Opcode: SMLSLT_ZZZI_S + /* 28668 */ MCD_OPC_FilterValue, + 1, + 78, + 40, + 1, // Skip to: 104527 + /* 28673 */ MCD_OPC_CheckPredicate, + 4, + 73, + 40, + 1, // Skip to: 104527 + /* 28678 */ MCD_OPC_Decode, + 227, + 43, + 149, + 1, // Opcode: UMLSLT_ZZZI_S + /* 28683 */ MCD_OPC_FilterValue, + 6, + 129, + 0, + 0, // Skip to: 28817 + /* 28688 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 28691 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 28705 + /* 28696 */ MCD_OPC_CheckPredicate, + 4, + 50, + 40, + 1, // Skip to: 104527 + /* 28701 */ MCD_OPC_Decode, + 134, + 30, + 22, // Opcode: SADALP_ZPmZ_D + /* 28705 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 28719 + /* 28710 */ MCD_OPC_CheckPredicate, + 4, + 36, + 40, + 1, // Skip to: 104527 + /* 28715 */ MCD_OPC_Decode, + 134, + 42, + 22, // Opcode: UADALP_ZPmZ_D + /* 28719 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 28733 + /* 28724 */ MCD_OPC_CheckPredicate, + 4, + 22, + 40, + 1, // Skip to: 104527 + /* 28729 */ MCD_OPC_Decode, + 250, + 32, + 24, // Opcode: SQABS_ZPmZ_D + /* 28733 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 28747 + /* 28738 */ MCD_OPC_CheckPredicate, + 4, + 8, + 40, + 1, // Skip to: 104527 + /* 28743 */ MCD_OPC_Decode, + 171, + 34, + 24, // Opcode: SQNEG_ZPmZ_D + /* 28747 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 28761 + /* 28752 */ MCD_OPC_CheckPredicate, + 4, + 250, + 39, + 1, // Skip to: 104527 + /* 28757 */ MCD_OPC_Decode, + 165, + 7, + 22, // Opcode: ADDP_ZPmZ_D + /* 28761 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 28775 + /* 28766 */ MCD_OPC_CheckPredicate, + 4, + 236, + 39, + 1, // Skip to: 104527 + /* 28771 */ MCD_OPC_Decode, + 217, + 31, + 22, // Opcode: SMAXP_ZPmZ_D + /* 28775 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 28789 + /* 28780 */ MCD_OPC_CheckPredicate, + 4, + 222, + 39, + 1, // Skip to: 104527 + /* 28785 */ MCD_OPC_Decode, + 136, + 43, + 22, // Opcode: UMAXP_ZPmZ_D + /* 28789 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 28803 + /* 28794 */ MCD_OPC_CheckPredicate, + 4, + 208, + 39, + 1, // Skip to: 104527 + /* 28799 */ MCD_OPC_Decode, + 251, + 31, + 22, // Opcode: SMINP_ZPmZ_D + /* 28803 */ MCD_OPC_FilterValue, + 23, + 199, + 39, + 1, // Skip to: 104527 + /* 28808 */ MCD_OPC_CheckPredicate, + 4, + 194, + 39, + 1, // Skip to: 104527 + /* 28813 */ MCD_OPC_Decode, + 169, + 43, + 22, // Opcode: UMINP_ZPmZ_D + /* 28817 */ MCD_OPC_FilterValue, + 7, + 79, + 0, + 0, // Skip to: 28901 + /* 28822 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 28825 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 28863 + /* 28830 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 28833 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 28848 + /* 28838 */ MCD_OPC_CheckPredicate, + 4, + 164, + 39, + 1, // Skip to: 104527 + /* 28843 */ MCD_OPC_Decode, + 175, + 32, + 150, + 1, // Opcode: SMLSLB_ZZZI_D + /* 28848 */ MCD_OPC_FilterValue, + 1, + 154, + 39, + 1, // Skip to: 104527 + /* 28853 */ MCD_OPC_CheckPredicate, + 4, + 149, + 39, + 1, // Skip to: 104527 + /* 28858 */ MCD_OPC_Decode, + 221, + 43, + 150, + 1, // Opcode: UMLSLB_ZZZI_D + /* 28863 */ MCD_OPC_FilterValue, + 1, + 139, + 39, + 1, // Skip to: 104527 + /* 28868 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 28871 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 28886 + /* 28876 */ MCD_OPC_CheckPredicate, + 4, + 126, + 39, + 1, // Skip to: 104527 + /* 28881 */ MCD_OPC_Decode, + 180, + 32, + 150, + 1, // Opcode: SMLSLT_ZZZI_D + /* 28886 */ MCD_OPC_FilterValue, + 1, + 116, + 39, + 1, // Skip to: 104527 + /* 28891 */ MCD_OPC_CheckPredicate, + 4, + 111, + 39, + 1, // Skip to: 104527 + /* 28896 */ MCD_OPC_Decode, + 226, + 43, + 150, + 1, // Opcode: UMLSLT_ZZZI_D + /* 28901 */ MCD_OPC_FilterValue, + 8, + 217, + 0, + 0, // Skip to: 29123 + /* 28906 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 28909 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 28952 + /* 28914 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 28917 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 28938 + /* 28922 */ MCD_OPC_CheckPredicate, + 4, + 80, + 39, + 1, // Skip to: 104527 + /* 28927 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 73, + 39, + 1, // Skip to: 104527 + /* 28934 */ MCD_OPC_Decode, + 240, + 36, + 80, // Opcode: SSHLLB_ZZI_H + /* 28938 */ MCD_OPC_FilterValue, + 1, + 64, + 39, + 1, // Skip to: 104527 + /* 28943 */ MCD_OPC_CheckPredicate, + 4, + 59, + 39, + 1, // Skip to: 104527 + /* 28948 */ MCD_OPC_Decode, + 241, + 36, + 81, // Opcode: SSHLLB_ZZI_S + /* 28952 */ MCD_OPC_FilterValue, + 1, + 38, + 0, + 0, // Skip to: 28995 + /* 28957 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 28960 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 28981 + /* 28965 */ MCD_OPC_CheckPredicate, + 4, + 37, + 39, + 1, // Skip to: 104527 + /* 28970 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 30, + 39, + 1, // Skip to: 104527 + /* 28977 */ MCD_OPC_Decode, + 243, + 36, + 80, // Opcode: SSHLLT_ZZI_H + /* 28981 */ MCD_OPC_FilterValue, + 1, + 21, + 39, + 1, // Skip to: 104527 + /* 28986 */ MCD_OPC_CheckPredicate, + 4, + 16, + 39, + 1, // Skip to: 104527 + /* 28991 */ MCD_OPC_Decode, + 244, + 36, + 81, // Opcode: SSHLLT_ZZI_S + /* 28995 */ MCD_OPC_FilterValue, + 2, + 38, + 0, + 0, // Skip to: 29038 + /* 29000 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 29003 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 29024 + /* 29008 */ MCD_OPC_CheckPredicate, + 4, + 250, + 38, + 1, // Skip to: 104527 + /* 29013 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 243, + 38, + 1, // Skip to: 104527 + /* 29020 */ MCD_OPC_Decode, + 156, + 46, + 80, // Opcode: USHLLB_ZZI_H + /* 29024 */ MCD_OPC_FilterValue, + 1, + 234, + 38, + 1, // Skip to: 104527 + /* 29029 */ MCD_OPC_CheckPredicate, + 4, + 229, + 38, + 1, // Skip to: 104527 + /* 29034 */ MCD_OPC_Decode, + 157, + 46, + 81, // Opcode: USHLLB_ZZI_S + /* 29038 */ MCD_OPC_FilterValue, + 3, + 38, + 0, + 0, // Skip to: 29081 + /* 29043 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 29046 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 29067 + /* 29051 */ MCD_OPC_CheckPredicate, + 4, + 207, + 38, + 1, // Skip to: 104527 + /* 29056 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 200, + 38, + 1, // Skip to: 104527 + /* 29063 */ MCD_OPC_Decode, + 159, + 46, + 80, // Opcode: USHLLT_ZZI_H + /* 29067 */ MCD_OPC_FilterValue, + 1, + 191, + 38, + 1, // Skip to: 104527 + /* 29072 */ MCD_OPC_CheckPredicate, + 4, + 186, + 38, + 1, // Skip to: 104527 + /* 29077 */ MCD_OPC_Decode, + 160, + 46, + 81, // Opcode: USHLLT_ZZI_S + /* 29081 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 29095 + /* 29086 */ MCD_OPC_CheckPredicate, + 11, + 172, + 38, + 1, // Skip to: 104527 + /* 29091 */ MCD_OPC_Decode, + 188, + 8, + 45, // Opcode: BEXT_ZZZ_B + /* 29095 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 29109 + /* 29100 */ MCD_OPC_CheckPredicate, + 11, + 158, + 38, + 1, // Skip to: 104527 + /* 29105 */ MCD_OPC_Decode, + 184, + 8, + 45, // Opcode: BDEP_ZZZ_B + /* 29109 */ MCD_OPC_FilterValue, + 6, + 149, + 38, + 1, // Skip to: 104527 + /* 29114 */ MCD_OPC_CheckPredicate, + 11, + 144, + 38, + 1, // Skip to: 104527 + /* 29119 */ MCD_OPC_Decode, + 215, + 8, + 45, // Opcode: BGRP_ZZZ_B + /* 29123 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 29144 + /* 29128 */ MCD_OPC_CheckPredicate, + 10, + 130, + 38, + 1, // Skip to: 104527 + /* 29133 */ MCD_OPC_CheckField, + 10, + 3, + 0, + 123, + 38, + 1, // Skip to: 104527 + /* 29140 */ MCD_OPC_Decode, + 132, + 21, + 45, // Opcode: HISTSEG_ZZZ + /* 29144 */ MCD_OPC_FilterValue, + 10, + 101, + 0, + 0, // Skip to: 29250 + /* 29149 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 29152 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 29166 + /* 29157 */ MCD_OPC_CheckPredicate, + 4, + 101, + 38, + 1, // Skip to: 104527 + /* 29162 */ MCD_OPC_Decode, + 239, + 36, + 82, // Opcode: SSHLLB_ZZI_D + /* 29166 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 29180 + /* 29171 */ MCD_OPC_CheckPredicate, + 4, + 87, + 38, + 1, // Skip to: 104527 + /* 29176 */ MCD_OPC_Decode, + 242, + 36, + 82, // Opcode: SSHLLT_ZZI_D + /* 29180 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 29194 + /* 29185 */ MCD_OPC_CheckPredicate, + 4, + 73, + 38, + 1, // Skip to: 104527 + /* 29190 */ MCD_OPC_Decode, + 155, + 46, + 82, // Opcode: USHLLB_ZZI_D + /* 29194 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 29208 + /* 29199 */ MCD_OPC_CheckPredicate, + 4, + 59, + 38, + 1, // Skip to: 104527 + /* 29204 */ MCD_OPC_Decode, + 158, + 46, + 82, // Opcode: USHLLT_ZZI_D + /* 29208 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 29222 + /* 29213 */ MCD_OPC_CheckPredicate, + 11, + 45, + 38, + 1, // Skip to: 104527 + /* 29218 */ MCD_OPC_Decode, + 190, + 8, + 45, // Opcode: BEXT_ZZZ_H + /* 29222 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 29236 + /* 29227 */ MCD_OPC_CheckPredicate, + 11, + 31, + 38, + 1, // Skip to: 104527 + /* 29232 */ MCD_OPC_Decode, + 186, + 8, + 45, // Opcode: BDEP_ZZZ_H + /* 29236 */ MCD_OPC_FilterValue, + 6, + 22, + 38, + 1, // Skip to: 104527 + /* 29241 */ MCD_OPC_CheckPredicate, + 11, + 17, + 38, + 1, // Skip to: 104527 + /* 29246 */ MCD_OPC_Decode, + 217, + 8, + 45, // Opcode: BGRP_ZZZ_H + /* 29250 */ MCD_OPC_FilterValue, + 12, + 45, + 0, + 0, // Skip to: 29300 + /* 29255 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 29258 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 29272 + /* 29263 */ MCD_OPC_CheckPredicate, + 11, + 251, + 37, + 1, // Skip to: 104527 + /* 29268 */ MCD_OPC_Decode, + 191, + 8, + 45, // Opcode: BEXT_ZZZ_S + /* 29272 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 29286 + /* 29277 */ MCD_OPC_CheckPredicate, + 11, + 237, + 37, + 1, // Skip to: 104527 + /* 29282 */ MCD_OPC_Decode, + 187, + 8, + 45, // Opcode: BDEP_ZZZ_S + /* 29286 */ MCD_OPC_FilterValue, + 6, + 228, + 37, + 1, // Skip to: 104527 + /* 29291 */ MCD_OPC_CheckPredicate, + 11, + 223, + 37, + 1, // Skip to: 104527 + /* 29296 */ MCD_OPC_Decode, + 218, + 8, + 45, // Opcode: BGRP_ZZZ_S + /* 29300 */ MCD_OPC_FilterValue, + 14, + 214, + 37, + 1, // Skip to: 104527 + /* 29305 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 29308 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 29322 + /* 29313 */ MCD_OPC_CheckPredicate, + 11, + 201, + 37, + 1, // Skip to: 104527 + /* 29318 */ MCD_OPC_Decode, + 189, + 8, + 45, // Opcode: BEXT_ZZZ_D + /* 29322 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 29336 + /* 29327 */ MCD_OPC_CheckPredicate, + 11, + 187, + 37, + 1, // Skip to: 104527 + /* 29332 */ MCD_OPC_Decode, + 185, + 8, + 45, // Opcode: BDEP_ZZZ_D + /* 29336 */ MCD_OPC_FilterValue, + 6, + 178, + 37, + 1, // Skip to: 104527 + /* 29341 */ MCD_OPC_CheckPredicate, + 11, + 173, + 37, + 1, // Skip to: 104527 + /* 29346 */ MCD_OPC_Decode, + 216, + 8, + 45, // Opcode: BGRP_ZZZ_D + /* 29350 */ MCD_OPC_FilterValue, + 6, + 129, + 3, + 0, // Skip to: 30252 + /* 29355 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 29358 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 29396 + /* 29363 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 29366 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29381 + /* 29371 */ MCD_OPC_CheckPredicate, + 0, + 143, + 37, + 1, // Skip to: 104527 + /* 29376 */ MCD_OPC_Decode, + 195, + 30, + 153, + 1, // Opcode: SCLAMP_ZZZ_B + /* 29381 */ MCD_OPC_FilterValue, + 1, + 133, + 37, + 1, // Skip to: 104527 + /* 29386 */ MCD_OPC_CheckPredicate, + 0, + 128, + 37, + 1, // Skip to: 104527 + /* 29391 */ MCD_OPC_Decode, + 184, + 42, + 153, + 1, // Opcode: UCLAMP_ZZZ_B + /* 29396 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 29434 + /* 29401 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 29404 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29419 + /* 29409 */ MCD_OPC_CheckPredicate, + 0, + 105, + 37, + 1, // Skip to: 104527 + /* 29414 */ MCD_OPC_Decode, + 197, + 30, + 153, + 1, // Opcode: SCLAMP_ZZZ_H + /* 29419 */ MCD_OPC_FilterValue, + 1, + 95, + 37, + 1, // Skip to: 104527 + /* 29424 */ MCD_OPC_CheckPredicate, + 0, + 90, + 37, + 1, // Skip to: 104527 + /* 29429 */ MCD_OPC_Decode, + 186, + 42, + 153, + 1, // Opcode: UCLAMP_ZZZ_H + /* 29434 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 29472 + /* 29439 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 29442 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29457 + /* 29447 */ MCD_OPC_CheckPredicate, + 0, + 67, + 37, + 1, // Skip to: 104527 + /* 29452 */ MCD_OPC_Decode, + 198, + 30, + 153, + 1, // Opcode: SCLAMP_ZZZ_S + /* 29457 */ MCD_OPC_FilterValue, + 1, + 57, + 37, + 1, // Skip to: 104527 + /* 29462 */ MCD_OPC_CheckPredicate, + 0, + 52, + 37, + 1, // Skip to: 104527 + /* 29467 */ MCD_OPC_Decode, + 187, + 42, + 153, + 1, // Opcode: UCLAMP_ZZZ_S + /* 29472 */ MCD_OPC_FilterValue, + 5, + 79, + 0, + 0, // Skip to: 29556 + /* 29477 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 29480 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 29518 + /* 29485 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 29488 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29503 + /* 29493 */ MCD_OPC_CheckPredicate, + 4, + 21, + 37, + 1, // Skip to: 104527 + /* 29498 */ MCD_OPC_Decode, + 222, + 32, + 154, + 1, // Opcode: SMULLB_ZZZI_S + /* 29503 */ MCD_OPC_FilterValue, + 1, + 11, + 37, + 1, // Skip to: 104527 + /* 29508 */ MCD_OPC_CheckPredicate, + 4, + 6, + 37, + 1, // Skip to: 104527 + /* 29513 */ MCD_OPC_Decode, + 138, + 44, + 154, + 1, // Opcode: UMULLB_ZZZI_S + /* 29518 */ MCD_OPC_FilterValue, + 1, + 252, + 36, + 1, // Skip to: 104527 + /* 29523 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 29526 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29541 + /* 29531 */ MCD_OPC_CheckPredicate, + 4, + 239, + 36, + 1, // Skip to: 104527 + /* 29536 */ MCD_OPC_Decode, + 227, + 32, + 154, + 1, // Opcode: SMULLT_ZZZI_S + /* 29541 */ MCD_OPC_FilterValue, + 1, + 229, + 36, + 1, // Skip to: 104527 + /* 29546 */ MCD_OPC_CheckPredicate, + 4, + 224, + 36, + 1, // Skip to: 104527 + /* 29551 */ MCD_OPC_Decode, + 143, + 44, + 154, + 1, // Opcode: UMULLT_ZZZI_S + /* 29556 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 29594 + /* 29561 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 29564 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29579 + /* 29569 */ MCD_OPC_CheckPredicate, + 0, + 201, + 36, + 1, // Skip to: 104527 + /* 29574 */ MCD_OPC_Decode, + 196, + 30, + 153, + 1, // Opcode: SCLAMP_ZZZ_D + /* 29579 */ MCD_OPC_FilterValue, + 1, + 191, + 36, + 1, // Skip to: 104527 + /* 29584 */ MCD_OPC_CheckPredicate, + 0, + 186, + 36, + 1, // Skip to: 104527 + /* 29589 */ MCD_OPC_Decode, + 185, + 42, + 153, + 1, // Opcode: UCLAMP_ZZZ_D + /* 29594 */ MCD_OPC_FilterValue, + 7, + 79, + 0, + 0, // Skip to: 29678 + /* 29599 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 29602 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 29640 + /* 29607 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 29610 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29625 + /* 29615 */ MCD_OPC_CheckPredicate, + 4, + 155, + 36, + 1, // Skip to: 104527 + /* 29620 */ MCD_OPC_Decode, + 221, + 32, + 155, + 1, // Opcode: SMULLB_ZZZI_D + /* 29625 */ MCD_OPC_FilterValue, + 1, + 145, + 36, + 1, // Skip to: 104527 + /* 29630 */ MCD_OPC_CheckPredicate, + 4, + 140, + 36, + 1, // Skip to: 104527 + /* 29635 */ MCD_OPC_Decode, + 137, + 44, + 155, + 1, // Opcode: UMULLB_ZZZI_D + /* 29640 */ MCD_OPC_FilterValue, + 1, + 130, + 36, + 1, // Skip to: 104527 + /* 29645 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 29648 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29663 + /* 29653 */ MCD_OPC_CheckPredicate, + 4, + 117, + 36, + 1, // Skip to: 104527 + /* 29658 */ MCD_OPC_Decode, + 226, + 32, + 155, + 1, // Opcode: SMULLT_ZZZI_D + /* 29663 */ MCD_OPC_FilterValue, + 1, + 107, + 36, + 1, // Skip to: 104527 + /* 29668 */ MCD_OPC_CheckPredicate, + 4, + 102, + 36, + 1, // Skip to: 104527 + /* 29673 */ MCD_OPC_Decode, + 142, + 44, + 155, + 1, // Opcode: UMULLT_ZZZI_D + /* 29678 */ MCD_OPC_FilterValue, + 8, + 77, + 0, + 0, // Skip to: 29760 + /* 29683 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 29686 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 29722 + /* 29691 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 29694 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 29708 + /* 29699 */ MCD_OPC_CheckPredicate, + 4, + 71, + 36, + 1, // Skip to: 104527 + /* 29704 */ MCD_OPC_Decode, + 141, + 7, + 54, // Opcode: ADCLB_ZZZ_S + /* 29708 */ MCD_OPC_FilterValue, + 1, + 62, + 36, + 1, // Skip to: 104527 + /* 29713 */ MCD_OPC_CheckPredicate, + 4, + 57, + 36, + 1, // Skip to: 104527 + /* 29718 */ MCD_OPC_Decode, + 143, + 7, + 54, // Opcode: ADCLT_ZZZ_S + /* 29722 */ MCD_OPC_FilterValue, + 3, + 48, + 36, + 1, // Skip to: 104527 + /* 29727 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 29730 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29745 + /* 29735 */ MCD_OPC_CheckPredicate, + 4, + 35, + 36, + 1, // Skip to: 104527 + /* 29740 */ MCD_OPC_Decode, + 144, + 9, + 156, + 1, // Opcode: CADD_ZZI_B + /* 29745 */ MCD_OPC_FilterValue, + 1, + 25, + 36, + 1, // Skip to: 104527 + /* 29750 */ MCD_OPC_CheckPredicate, + 4, + 20, + 36, + 1, // Skip to: 104527 + /* 29755 */ MCD_OPC_Decode, + 159, + 33, + 156, + 1, // Opcode: SQCADD_ZZI_B + /* 29760 */ MCD_OPC_FilterValue, + 10, + 149, + 0, + 0, // Skip to: 29914 + /* 29765 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 29768 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 29804 + /* 29773 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 29776 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 29790 + /* 29781 */ MCD_OPC_CheckPredicate, + 4, + 245, + 35, + 1, // Skip to: 104527 + /* 29786 */ MCD_OPC_Decode, + 219, + 29, + 54, // Opcode: SABALB_ZZZ_H + /* 29790 */ MCD_OPC_FilterValue, + 1, + 236, + 35, + 1, // Skip to: 104527 + /* 29795 */ MCD_OPC_CheckPredicate, + 4, + 231, + 35, + 1, // Skip to: 104527 + /* 29800 */ MCD_OPC_Decode, + 222, + 29, + 54, // Opcode: SABALT_ZZZ_H + /* 29804 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 29840 + /* 29809 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 29812 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 29826 + /* 29817 */ MCD_OPC_CheckPredicate, + 4, + 209, + 35, + 1, // Skip to: 104527 + /* 29822 */ MCD_OPC_Decode, + 219, + 41, + 54, // Opcode: UABALB_ZZZ_H + /* 29826 */ MCD_OPC_FilterValue, + 1, + 200, + 35, + 1, // Skip to: 104527 + /* 29831 */ MCD_OPC_CheckPredicate, + 4, + 195, + 35, + 1, // Skip to: 104527 + /* 29836 */ MCD_OPC_Decode, + 222, + 41, + 54, // Opcode: UABALT_ZZZ_H + /* 29840 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 29876 + /* 29845 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 29848 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 29862 + /* 29853 */ MCD_OPC_CheckPredicate, + 4, + 173, + 35, + 1, // Skip to: 104527 + /* 29858 */ MCD_OPC_Decode, + 140, + 7, + 54, // Opcode: ADCLB_ZZZ_D + /* 29862 */ MCD_OPC_FilterValue, + 1, + 164, + 35, + 1, // Skip to: 104527 + /* 29867 */ MCD_OPC_CheckPredicate, + 4, + 159, + 35, + 1, // Skip to: 104527 + /* 29872 */ MCD_OPC_Decode, + 142, + 7, + 54, // Opcode: ADCLT_ZZZ_D + /* 29876 */ MCD_OPC_FilterValue, + 3, + 150, + 35, + 1, // Skip to: 104527 + /* 29881 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 29884 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 29899 + /* 29889 */ MCD_OPC_CheckPredicate, + 4, + 137, + 35, + 1, // Skip to: 104527 + /* 29894 */ MCD_OPC_Decode, + 146, + 9, + 156, + 1, // Opcode: CADD_ZZI_H + /* 29899 */ MCD_OPC_FilterValue, + 1, + 127, + 35, + 1, // Skip to: 104527 + /* 29904 */ MCD_OPC_CheckPredicate, + 4, + 122, + 35, + 1, // Skip to: 104527 + /* 29909 */ MCD_OPC_Decode, + 161, + 33, + 156, + 1, // Opcode: SQCADD_ZZI_H + /* 29914 */ MCD_OPC_FilterValue, + 12, + 149, + 0, + 0, // Skip to: 30068 + /* 29919 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 29922 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 29958 + /* 29927 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 29930 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 29944 + /* 29935 */ MCD_OPC_CheckPredicate, + 4, + 91, + 35, + 1, // Skip to: 104527 + /* 29940 */ MCD_OPC_Decode, + 220, + 29, + 54, // Opcode: SABALB_ZZZ_S + /* 29944 */ MCD_OPC_FilterValue, + 1, + 82, + 35, + 1, // Skip to: 104527 + /* 29949 */ MCD_OPC_CheckPredicate, + 4, + 77, + 35, + 1, // Skip to: 104527 + /* 29954 */ MCD_OPC_Decode, + 223, + 29, + 54, // Opcode: SABALT_ZZZ_S + /* 29958 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 29994 + /* 29963 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 29966 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 29980 + /* 29971 */ MCD_OPC_CheckPredicate, + 4, + 55, + 35, + 1, // Skip to: 104527 + /* 29976 */ MCD_OPC_Decode, + 220, + 41, + 54, // Opcode: UABALB_ZZZ_S + /* 29980 */ MCD_OPC_FilterValue, + 1, + 46, + 35, + 1, // Skip to: 104527 + /* 29985 */ MCD_OPC_CheckPredicate, + 4, + 41, + 35, + 1, // Skip to: 104527 + /* 29990 */ MCD_OPC_Decode, + 223, + 41, + 54, // Opcode: UABALT_ZZZ_S + /* 29994 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 30030 + /* 29999 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 30002 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 30016 + /* 30007 */ MCD_OPC_CheckPredicate, + 4, + 19, + 35, + 1, // Skip to: 104527 + /* 30012 */ MCD_OPC_Decode, + 186, + 30, + 54, // Opcode: SBCLB_ZZZ_S + /* 30016 */ MCD_OPC_FilterValue, + 1, + 10, + 35, + 1, // Skip to: 104527 + /* 30021 */ MCD_OPC_CheckPredicate, + 4, + 5, + 35, + 1, // Skip to: 104527 + /* 30026 */ MCD_OPC_Decode, + 188, + 30, + 54, // Opcode: SBCLT_ZZZ_S + /* 30030 */ MCD_OPC_FilterValue, + 3, + 252, + 34, + 1, // Skip to: 104527 + /* 30035 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 30038 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 30053 + /* 30043 */ MCD_OPC_CheckPredicate, + 4, + 239, + 34, + 1, // Skip to: 104527 + /* 30048 */ MCD_OPC_Decode, + 147, + 9, + 156, + 1, // Opcode: CADD_ZZI_S + /* 30053 */ MCD_OPC_FilterValue, + 1, + 229, + 34, + 1, // Skip to: 104527 + /* 30058 */ MCD_OPC_CheckPredicate, + 4, + 224, + 34, + 1, // Skip to: 104527 + /* 30063 */ MCD_OPC_Decode, + 162, + 33, + 156, + 1, // Opcode: SQCADD_ZZI_S + /* 30068 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 30083 + /* 30073 */ MCD_OPC_CheckPredicate, + 10, + 209, + 34, + 1, // Skip to: 104527 + /* 30078 */ MCD_OPC_Decode, + 131, + 21, + 157, + 1, // Opcode: HISTCNT_ZPzZZ_S + /* 30083 */ MCD_OPC_FilterValue, + 14, + 149, + 0, + 0, // Skip to: 30237 + /* 30088 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 30091 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 30127 + /* 30096 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 30099 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 30113 + /* 30104 */ MCD_OPC_CheckPredicate, + 4, + 178, + 34, + 1, // Skip to: 104527 + /* 30109 */ MCD_OPC_Decode, + 218, + 29, + 54, // Opcode: SABALB_ZZZ_D + /* 30113 */ MCD_OPC_FilterValue, + 1, + 169, + 34, + 1, // Skip to: 104527 + /* 30118 */ MCD_OPC_CheckPredicate, + 4, + 164, + 34, + 1, // Skip to: 104527 + /* 30123 */ MCD_OPC_Decode, + 221, + 29, + 54, // Opcode: SABALT_ZZZ_D + /* 30127 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 30163 + /* 30132 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 30135 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 30149 + /* 30140 */ MCD_OPC_CheckPredicate, + 4, + 142, + 34, + 1, // Skip to: 104527 + /* 30145 */ MCD_OPC_Decode, + 218, + 41, + 54, // Opcode: UABALB_ZZZ_D + /* 30149 */ MCD_OPC_FilterValue, + 1, + 133, + 34, + 1, // Skip to: 104527 + /* 30154 */ MCD_OPC_CheckPredicate, + 4, + 128, + 34, + 1, // Skip to: 104527 + /* 30159 */ MCD_OPC_Decode, + 221, + 41, + 54, // Opcode: UABALT_ZZZ_D + /* 30163 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 30199 + /* 30168 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 30171 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 30185 + /* 30176 */ MCD_OPC_CheckPredicate, + 4, + 106, + 34, + 1, // Skip to: 104527 + /* 30181 */ MCD_OPC_Decode, + 185, + 30, + 54, // Opcode: SBCLB_ZZZ_D + /* 30185 */ MCD_OPC_FilterValue, + 1, + 97, + 34, + 1, // Skip to: 104527 + /* 30190 */ MCD_OPC_CheckPredicate, + 4, + 92, + 34, + 1, // Skip to: 104527 + /* 30195 */ MCD_OPC_Decode, + 187, + 30, + 54, // Opcode: SBCLT_ZZZ_D + /* 30199 */ MCD_OPC_FilterValue, + 3, + 83, + 34, + 1, // Skip to: 104527 + /* 30204 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 30207 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 30222 + /* 30212 */ MCD_OPC_CheckPredicate, + 4, + 70, + 34, + 1, // Skip to: 104527 + /* 30217 */ MCD_OPC_Decode, + 145, + 9, + 156, + 1, // Opcode: CADD_ZZI_D + /* 30222 */ MCD_OPC_FilterValue, + 1, + 60, + 34, + 1, // Skip to: 104527 + /* 30227 */ MCD_OPC_CheckPredicate, + 4, + 55, + 34, + 1, // Skip to: 104527 + /* 30232 */ MCD_OPC_Decode, + 160, + 33, + 156, + 1, // Opcode: SQCADD_ZZI_D + /* 30237 */ MCD_OPC_FilterValue, + 15, + 45, + 34, + 1, // Skip to: 104527 + /* 30242 */ MCD_OPC_CheckPredicate, + 10, + 40, + 34, + 1, // Skip to: 104527 + /* 30247 */ MCD_OPC_Decode, + 130, + 21, + 157, + 1, // Opcode: HISTCNT_ZPzZZ_D + /* 30252 */ MCD_OPC_FilterValue, + 7, + 30, + 34, + 1, // Skip to: 104527 + /* 30257 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 30260 */ MCD_OPC_FilterValue, + 0, + 69, + 0, + 0, // Skip to: 30334 + /* 30265 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 30268 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 30290 + /* 30273 */ MCD_OPC_CheckPredicate, + 4, + 9, + 34, + 1, // Skip to: 104527 + /* 30278 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 2, + 34, + 1, // Skip to: 104527 + /* 30285 */ MCD_OPC_Decode, + 236, + 33, + 158, + 1, // Opcode: SQDMULH_ZZZI_H + /* 30290 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 30312 + /* 30295 */ MCD_OPC_CheckPredicate, + 4, + 243, + 33, + 1, // Skip to: 104527 + /* 30300 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 236, + 33, + 1, // Skip to: 104527 + /* 30307 */ MCD_OPC_Decode, + 230, + 34, + 158, + 1, // Opcode: SQRDMULH_ZZZI_H + /* 30312 */ MCD_OPC_FilterValue, + 6, + 226, + 33, + 1, // Skip to: 104527 + /* 30317 */ MCD_OPC_CheckPredicate, + 4, + 221, + 33, + 1, // Skip to: 104527 + /* 30322 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 214, + 33, + 1, // Skip to: 104527 + /* 30329 */ MCD_OPC_Decode, + 221, + 27, + 158, + 1, // Opcode: MUL_ZZZI_H + /* 30334 */ MCD_OPC_FilterValue, + 1, + 231, + 0, + 0, // Skip to: 30570 + /* 30339 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 30342 */ MCD_OPC_FilterValue, + 0, + 125, + 0, + 0, // Skip to: 30472 + /* 30347 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 30350 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 30388 + /* 30355 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30358 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 30373 + /* 30363 */ MCD_OPC_CheckPredicate, + 4, + 175, + 33, + 1, // Skip to: 104527 + /* 30368 */ MCD_OPC_Decode, + 255, + 33, + 154, + 1, // Opcode: SQDMULLB_ZZZI_S + /* 30373 */ MCD_OPC_FilterValue, + 3, + 165, + 33, + 1, // Skip to: 104527 + /* 30378 */ MCD_OPC_CheckPredicate, + 4, + 160, + 33, + 1, // Skip to: 104527 + /* 30383 */ MCD_OPC_Decode, + 254, + 33, + 155, + 1, // Opcode: SQDMULLB_ZZZI_D + /* 30388 */ MCD_OPC_FilterValue, + 1, + 150, + 33, + 1, // Skip to: 104527 + /* 30393 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 30396 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 30434 + /* 30401 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30404 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 30419 + /* 30409 */ MCD_OPC_CheckPredicate, + 4, + 129, + 33, + 1, // Skip to: 104527 + /* 30414 */ MCD_OPC_Decode, + 237, + 33, + 159, + 1, // Opcode: SQDMULH_ZZZI_S + /* 30419 */ MCD_OPC_FilterValue, + 3, + 119, + 33, + 1, // Skip to: 104527 + /* 30424 */ MCD_OPC_CheckPredicate, + 4, + 114, + 33, + 1, // Skip to: 104527 + /* 30429 */ MCD_OPC_Decode, + 235, + 33, + 160, + 1, // Opcode: SQDMULH_ZZZI_D + /* 30434 */ MCD_OPC_FilterValue, + 1, + 104, + 33, + 1, // Skip to: 104527 + /* 30439 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30442 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 30457 + /* 30447 */ MCD_OPC_CheckPredicate, + 4, + 91, + 33, + 1, // Skip to: 104527 + /* 30452 */ MCD_OPC_Decode, + 222, + 27, + 159, + 1, // Opcode: MUL_ZZZI_S + /* 30457 */ MCD_OPC_FilterValue, + 3, + 81, + 33, + 1, // Skip to: 104527 + /* 30462 */ MCD_OPC_CheckPredicate, + 4, + 76, + 33, + 1, // Skip to: 104527 + /* 30467 */ MCD_OPC_Decode, + 220, + 27, + 160, + 1, // Opcode: MUL_ZZZI_D + /* 30472 */ MCD_OPC_FilterValue, + 1, + 66, + 33, + 1, // Skip to: 104527 + /* 30477 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 30480 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 30518 + /* 30485 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30488 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 30503 + /* 30493 */ MCD_OPC_CheckPredicate, + 4, + 45, + 33, + 1, // Skip to: 104527 + /* 30498 */ MCD_OPC_Decode, + 132, + 34, + 154, + 1, // Opcode: SQDMULLT_ZZZI_S + /* 30503 */ MCD_OPC_FilterValue, + 3, + 35, + 33, + 1, // Skip to: 104527 + /* 30508 */ MCD_OPC_CheckPredicate, + 4, + 30, + 33, + 1, // Skip to: 104527 + /* 30513 */ MCD_OPC_Decode, + 131, + 34, + 155, + 1, // Opcode: SQDMULLT_ZZZI_D + /* 30518 */ MCD_OPC_FilterValue, + 1, + 20, + 33, + 1, // Skip to: 104527 + /* 30523 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30526 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 30548 + /* 30531 */ MCD_OPC_CheckPredicate, + 4, + 7, + 33, + 1, // Skip to: 104527 + /* 30536 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 0, + 33, + 1, // Skip to: 104527 + /* 30543 */ MCD_OPC_Decode, + 231, + 34, + 159, + 1, // Opcode: SQRDMULH_ZZZI_S + /* 30548 */ MCD_OPC_FilterValue, + 3, + 246, + 32, + 1, // Skip to: 104527 + /* 30553 */ MCD_OPC_CheckPredicate, + 4, + 241, + 32, + 1, // Skip to: 104527 + /* 30558 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 234, + 32, + 1, // Skip to: 104527 + /* 30565 */ MCD_OPC_Decode, + 229, + 34, + 160, + 1, // Opcode: SQRDMULH_ZZZI_D + /* 30570 */ MCD_OPC_FilterValue, + 2, + 86, + 2, + 0, // Skip to: 31173 + /* 30575 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 30578 */ MCD_OPC_FilterValue, + 0, + 118, + 0, + 0, // Skip to: 30701 + /* 30583 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30586 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 30629 + /* 30591 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 30594 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 30615 + /* 30599 */ MCD_OPC_CheckPredicate, + 4, + 195, + 32, + 1, // Skip to: 104527 + /* 30604 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 188, + 32, + 1, // Skip to: 104527 + /* 30611 */ MCD_OPC_Decode, + 139, + 37, + 55, // Opcode: SSRA_ZZI_B + /* 30615 */ MCD_OPC_FilterValue, + 1, + 179, + 32, + 1, // Skip to: 104527 + /* 30620 */ MCD_OPC_CheckPredicate, + 4, + 174, + 32, + 1, // Skip to: 104527 + /* 30625 */ MCD_OPC_Decode, + 141, + 37, + 56, // Opcode: SSRA_ZZI_H + /* 30629 */ MCD_OPC_FilterValue, + 1, + 53, + 0, + 0, // Skip to: 30687 + /* 30634 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 30637 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 30659 + /* 30642 */ MCD_OPC_CheckPredicate, + 8, + 152, + 32, + 1, // Skip to: 104527 + /* 30647 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 145, + 32, + 1, // Skip to: 104527 + /* 30654 */ MCD_OPC_Decode, + 242, + 7, + 161, + 1, // Opcode: AESMC_ZZ_B + /* 30659 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 30673 + /* 30664 */ MCD_OPC_CheckPredicate, + 8, + 130, + 32, + 1, // Skip to: 104527 + /* 30669 */ MCD_OPC_Decode, + 238, + 7, + 62, // Opcode: AESE_ZZZ_B + /* 30673 */ MCD_OPC_FilterValue, + 3, + 121, + 32, + 1, // Skip to: 104527 + /* 30678 */ MCD_OPC_CheckPredicate, + 12, + 116, + 32, + 1, // Skip to: 104527 + /* 30683 */ MCD_OPC_Decode, + 214, + 31, + 62, // Opcode: SM4E_ZZZ_S + /* 30687 */ MCD_OPC_FilterValue, + 2, + 107, + 32, + 1, // Skip to: 104527 + /* 30692 */ MCD_OPC_CheckPredicate, + 4, + 102, + 32, + 1, // Skip to: 104527 + /* 30697 */ MCD_OPC_Decode, + 142, + 37, + 57, // Opcode: SSRA_ZZI_S + /* 30701 */ MCD_OPC_FilterValue, + 1, + 104, + 0, + 0, // Skip to: 30810 + /* 30706 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30709 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 30752 + /* 30714 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 30717 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 30738 + /* 30722 */ MCD_OPC_CheckPredicate, + 4, + 72, + 32, + 1, // Skip to: 104527 + /* 30727 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 65, + 32, + 1, // Skip to: 104527 + /* 30734 */ MCD_OPC_Decode, + 204, + 46, + 55, // Opcode: USRA_ZZI_B + /* 30738 */ MCD_OPC_FilterValue, + 1, + 56, + 32, + 1, // Skip to: 104527 + /* 30743 */ MCD_OPC_CheckPredicate, + 4, + 51, + 32, + 1, // Skip to: 104527 + /* 30748 */ MCD_OPC_Decode, + 206, + 46, + 56, // Opcode: USRA_ZZI_H + /* 30752 */ MCD_OPC_FilterValue, + 1, + 39, + 0, + 0, // Skip to: 30796 + /* 30757 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 30760 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 30782 + /* 30765 */ MCD_OPC_CheckPredicate, + 8, + 29, + 32, + 1, // Skip to: 104527 + /* 30770 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 22, + 32, + 1, // Skip to: 104527 + /* 30777 */ MCD_OPC_Decode, + 240, + 7, + 161, + 1, // Opcode: AESIMC_ZZ_B + /* 30782 */ MCD_OPC_FilterValue, + 2, + 12, + 32, + 1, // Skip to: 104527 + /* 30787 */ MCD_OPC_CheckPredicate, + 8, + 7, + 32, + 1, // Skip to: 104527 + /* 30792 */ MCD_OPC_Decode, + 236, + 7, + 62, // Opcode: AESD_ZZZ_B + /* 30796 */ MCD_OPC_FilterValue, + 2, + 254, + 31, + 1, // Skip to: 104527 + /* 30801 */ MCD_OPC_CheckPredicate, + 4, + 249, + 31, + 1, // Skip to: 104527 + /* 30806 */ MCD_OPC_Decode, + 207, + 46, + 57, // Opcode: USRA_ZZI_S + /* 30810 */ MCD_OPC_FilterValue, + 2, + 60, + 0, + 0, // Skip to: 30875 + /* 30815 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30818 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 30861 + /* 30823 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 30826 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 30847 + /* 30831 */ MCD_OPC_CheckPredicate, + 4, + 219, + 31, + 1, // Skip to: 104527 + /* 30836 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 212, + 31, + 1, // Skip to: 104527 + /* 30843 */ MCD_OPC_Decode, + 227, + 36, + 55, // Opcode: SRSRA_ZZI_B + /* 30847 */ MCD_OPC_FilterValue, + 1, + 203, + 31, + 1, // Skip to: 104527 + /* 30852 */ MCD_OPC_CheckPredicate, + 4, + 198, + 31, + 1, // Skip to: 104527 + /* 30857 */ MCD_OPC_Decode, + 229, + 36, + 56, // Opcode: SRSRA_ZZI_H + /* 30861 */ MCD_OPC_FilterValue, + 2, + 189, + 31, + 1, // Skip to: 104527 + /* 30866 */ MCD_OPC_CheckPredicate, + 4, + 184, + 31, + 1, // Skip to: 104527 + /* 30871 */ MCD_OPC_Decode, + 230, + 36, + 57, // Opcode: SRSRA_ZZI_S + /* 30875 */ MCD_OPC_FilterValue, + 3, + 60, + 0, + 0, // Skip to: 30940 + /* 30880 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30883 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 30926 + /* 30888 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 30891 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 30912 + /* 30896 */ MCD_OPC_CheckPredicate, + 4, + 154, + 31, + 1, // Skip to: 104527 + /* 30901 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 147, + 31, + 1, // Skip to: 104527 + /* 30908 */ MCD_OPC_Decode, + 137, + 46, + 55, // Opcode: URSRA_ZZI_B + /* 30912 */ MCD_OPC_FilterValue, + 1, + 138, + 31, + 1, // Skip to: 104527 + /* 30917 */ MCD_OPC_CheckPredicate, + 4, + 133, + 31, + 1, // Skip to: 104527 + /* 30922 */ MCD_OPC_Decode, + 139, + 46, + 56, // Opcode: URSRA_ZZI_H + /* 30926 */ MCD_OPC_FilterValue, + 2, + 124, + 31, + 1, // Skip to: 104527 + /* 30931 */ MCD_OPC_CheckPredicate, + 4, + 119, + 31, + 1, // Skip to: 104527 + /* 30936 */ MCD_OPC_Decode, + 140, + 46, + 57, // Opcode: URSRA_ZZI_S + /* 30940 */ MCD_OPC_FilterValue, + 4, + 74, + 0, + 0, // Skip to: 31019 + /* 30945 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 30948 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 30991 + /* 30953 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 30956 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 30977 + /* 30961 */ MCD_OPC_CheckPredicate, + 4, + 89, + 31, + 1, // Skip to: 104527 + /* 30966 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 82, + 31, + 1, // Skip to: 104527 + /* 30973 */ MCD_OPC_Decode, + 187, + 36, + 55, // Opcode: SRI_ZZI_B + /* 30977 */ MCD_OPC_FilterValue, + 1, + 73, + 31, + 1, // Skip to: 104527 + /* 30982 */ MCD_OPC_CheckPredicate, + 4, + 68, + 31, + 1, // Skip to: 104527 + /* 30987 */ MCD_OPC_Decode, + 189, + 36, + 56, // Opcode: SRI_ZZI_H + /* 30991 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 31005 + /* 30996 */ MCD_OPC_CheckPredicate, + 12, + 54, + 31, + 1, // Skip to: 104527 + /* 31001 */ MCD_OPC_Decode, + 212, + 31, + 45, // Opcode: SM4EKEY_ZZZ_S + /* 31005 */ MCD_OPC_FilterValue, + 2, + 45, + 31, + 1, // Skip to: 104527 + /* 31010 */ MCD_OPC_CheckPredicate, + 4, + 40, + 31, + 1, // Skip to: 104527 + /* 31015 */ MCD_OPC_Decode, + 190, + 36, + 57, // Opcode: SRI_ZZI_S + /* 31019 */ MCD_OPC_FilterValue, + 5, + 77, + 0, + 0, // Skip to: 31101 + /* 31024 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 31027 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 31072 + /* 31032 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 31035 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 31057 + /* 31040 */ MCD_OPC_CheckPredicate, + 4, + 10, + 31, + 1, // Skip to: 104527 + /* 31045 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 3, + 31, + 1, // Skip to: 104527 + /* 31052 */ MCD_OPC_Decode, + 192, + 31, + 162, + 1, // Opcode: SLI_ZZI_B + /* 31057 */ MCD_OPC_FilterValue, + 1, + 249, + 30, + 1, // Skip to: 104527 + /* 31062 */ MCD_OPC_CheckPredicate, + 4, + 244, + 30, + 1, // Skip to: 104527 + /* 31067 */ MCD_OPC_Decode, + 194, + 31, + 163, + 1, // Opcode: SLI_ZZI_H + /* 31072 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 31086 + /* 31077 */ MCD_OPC_CheckPredicate, + 13, + 229, + 30, + 1, // Skip to: 104527 + /* 31082 */ MCD_OPC_Decode, + 143, + 29, + 45, // Opcode: RAX1_ZZZ_D + /* 31086 */ MCD_OPC_FilterValue, + 2, + 220, + 30, + 1, // Skip to: 104527 + /* 31091 */ MCD_OPC_CheckPredicate, + 4, + 215, + 30, + 1, // Skip to: 104527 + /* 31096 */ MCD_OPC_Decode, + 195, + 31, + 164, + 1, // Opcode: SLI_ZZI_S + /* 31101 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 31137 + /* 31106 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 31109 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 31123 + /* 31114 */ MCD_OPC_CheckPredicate, + 4, + 192, + 30, + 1, // Skip to: 104527 + /* 31119 */ MCD_OPC_Decode, + 230, + 29, + 54, // Opcode: SABA_ZZZ_B + /* 31123 */ MCD_OPC_FilterValue, + 2, + 183, + 30, + 1, // Skip to: 104527 + /* 31128 */ MCD_OPC_CheckPredicate, + 4, + 178, + 30, + 1, // Skip to: 104527 + /* 31133 */ MCD_OPC_Decode, + 232, + 29, + 54, // Opcode: SABA_ZZZ_H + /* 31137 */ MCD_OPC_FilterValue, + 7, + 169, + 30, + 1, // Skip to: 104527 + /* 31142 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 31145 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 31159 + /* 31150 */ MCD_OPC_CheckPredicate, + 4, + 156, + 30, + 1, // Skip to: 104527 + /* 31155 */ MCD_OPC_Decode, + 230, + 41, + 54, // Opcode: UABA_ZZZ_B + /* 31159 */ MCD_OPC_FilterValue, + 2, + 147, + 30, + 1, // Skip to: 104527 + /* 31164 */ MCD_OPC_CheckPredicate, + 4, + 142, + 30, + 1, // Skip to: 104527 + /* 31169 */ MCD_OPC_Decode, + 232, + 41, + 54, // Opcode: UABA_ZZZ_H + /* 31173 */ MCD_OPC_FilterValue, + 3, + 133, + 30, + 1, // Skip to: 104527 + /* 31178 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 31181 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 31202 + /* 31186 */ MCD_OPC_CheckPredicate, + 4, + 120, + 30, + 1, // Skip to: 104527 + /* 31191 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 113, + 30, + 1, // Skip to: 104527 + /* 31198 */ MCD_OPC_Decode, + 140, + 37, + 58, // Opcode: SSRA_ZZI_D + /* 31202 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 31223 + /* 31207 */ MCD_OPC_CheckPredicate, + 4, + 99, + 30, + 1, // Skip to: 104527 + /* 31212 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 92, + 30, + 1, // Skip to: 104527 + /* 31219 */ MCD_OPC_Decode, + 205, + 46, + 58, // Opcode: USRA_ZZI_D + /* 31223 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 31244 + /* 31228 */ MCD_OPC_CheckPredicate, + 4, + 78, + 30, + 1, // Skip to: 104527 + /* 31233 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 71, + 30, + 1, // Skip to: 104527 + /* 31240 */ MCD_OPC_Decode, + 228, + 36, + 58, // Opcode: SRSRA_ZZI_D + /* 31244 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 31265 + /* 31249 */ MCD_OPC_CheckPredicate, + 4, + 57, + 30, + 1, // Skip to: 104527 + /* 31254 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 50, + 30, + 1, // Skip to: 104527 + /* 31261 */ MCD_OPC_Decode, + 138, + 46, + 58, // Opcode: URSRA_ZZI_D + /* 31265 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 31286 + /* 31270 */ MCD_OPC_CheckPredicate, + 4, + 36, + 30, + 1, // Skip to: 104527 + /* 31275 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 29, + 30, + 1, // Skip to: 104527 + /* 31282 */ MCD_OPC_Decode, + 188, + 36, + 58, // Opcode: SRI_ZZI_D + /* 31286 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 31308 + /* 31291 */ MCD_OPC_CheckPredicate, + 4, + 15, + 30, + 1, // Skip to: 104527 + /* 31296 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 8, + 30, + 1, // Skip to: 104527 + /* 31303 */ MCD_OPC_Decode, + 193, + 31, + 165, + 1, // Opcode: SLI_ZZI_D + /* 31308 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 31344 + /* 31313 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 31316 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 31330 + /* 31321 */ MCD_OPC_CheckPredicate, + 4, + 241, + 29, + 1, // Skip to: 104527 + /* 31326 */ MCD_OPC_Decode, + 233, + 29, + 54, // Opcode: SABA_ZZZ_S + /* 31330 */ MCD_OPC_FilterValue, + 2, + 232, + 29, + 1, // Skip to: 104527 + /* 31335 */ MCD_OPC_CheckPredicate, + 4, + 227, + 29, + 1, // Skip to: 104527 + /* 31340 */ MCD_OPC_Decode, + 231, + 29, + 54, // Opcode: SABA_ZZZ_D + /* 31344 */ MCD_OPC_FilterValue, + 7, + 218, + 29, + 1, // Skip to: 104527 + /* 31349 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 31352 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 31366 + /* 31357 */ MCD_OPC_CheckPredicate, + 4, + 205, + 29, + 1, // Skip to: 104527 + /* 31362 */ MCD_OPC_Decode, + 233, + 41, + 54, // Opcode: UABA_ZZZ_S + /* 31366 */ MCD_OPC_FilterValue, + 2, + 196, + 29, + 1, // Skip to: 104527 + /* 31371 */ MCD_OPC_CheckPredicate, + 4, + 191, + 29, + 1, // Skip to: 104527 + /* 31376 */ MCD_OPC_Decode, + 231, + 41, + 54, // Opcode: UABA_ZZZ_D + /* 31380 */ MCD_OPC_FilterValue, + 3, + 223, + 20, + 0, // Skip to: 36728 + /* 31385 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 31388 */ MCD_OPC_FilterValue, + 0, + 54, + 1, + 0, // Skip to: 31703 + /* 31393 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 31396 */ MCD_OPC_FilterValue, + 0, + 100, + 0, + 0, // Skip to: 31501 + /* 31401 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 31404 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 31426 + /* 31409 */ MCD_OPC_CheckPredicate, + 3, + 153, + 29, + 1, // Skip to: 104527 + /* 31414 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 146, + 29, + 1, // Skip to: 104527 + /* 31421 */ MCD_OPC_Decode, + 231, + 13, + 166, + 1, // Opcode: FCMLA_ZPmZZ_H + /* 31426 */ MCD_OPC_FilterValue, + 1, + 136, + 29, + 1, // Skip to: 104527 + /* 31431 */ MCD_OPC_ExtractField, + 10, + 5, // Inst{14-10} ... + /* 31434 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 31449 + /* 31439 */ MCD_OPC_CheckPredicate, + 3, + 123, + 29, + 1, // Skip to: 104527 + /* 31444 */ MCD_OPC_Decode, + 161, + 17, + 145, + 1, // Opcode: FMLA_ZZZI_H + /* 31449 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 31464 + /* 31454 */ MCD_OPC_CheckPredicate, + 3, + 108, + 29, + 1, // Skip to: 104527 + /* 31459 */ MCD_OPC_Decode, + 192, + 17, + 145, + 1, // Opcode: FMLS_ZZZI_H + /* 31464 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 31479 + /* 31469 */ MCD_OPC_CheckPredicate, + 3, + 93, + 29, + 1, // Skip to: 104527 + /* 31474 */ MCD_OPC_Decode, + 141, + 18, + 158, + 1, // Opcode: FMUL_ZZZI_H + /* 31479 */ MCD_OPC_FilterValue, + 16, + 83, + 29, + 1, // Skip to: 104527 + /* 31484 */ MCD_OPC_CheckPredicate, + 14, + 78, + 29, + 1, // Skip to: 104527 + /* 31489 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 71, + 29, + 1, // Skip to: 104527 + /* 31496 */ MCD_OPC_Decode, + 199, + 8, + 147, + 1, // Opcode: BFDOT_ZZI + /* 31501 */ MCD_OPC_FilterValue, + 1, + 61, + 29, + 1, // Skip to: 104527 + /* 31506 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 31509 */ MCD_OPC_FilterValue, + 0, + 140, + 0, + 0, // Skip to: 31654 + /* 31514 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 31517 */ MCD_OPC_FilterValue, + 2, + 111, + 0, + 0, // Skip to: 31633 + /* 31522 */ MCD_OPC_ExtractField, + 17, + 4, // Inst{20-17} ... + /* 31525 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 31540 + /* 31530 */ MCD_OPC_CheckPredicate, + 3, + 32, + 29, + 1, // Skip to: 104527 + /* 31535 */ MCD_OPC_Decode, + 151, + 13, + 167, + 1, // Opcode: FCADD_ZPmZ_H + /* 31540 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 31561 + /* 31545 */ MCD_OPC_CheckPredicate, + 4, + 17, + 29, + 1, // Skip to: 104527 + /* 31550 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 10, + 29, + 1, // Skip to: 104527 + /* 31557 */ MCD_OPC_Decode, + 250, + 12, + 22, // Opcode: FADDP_ZPmZZ_H + /* 31561 */ MCD_OPC_FilterValue, + 10, + 31, + 0, + 0, // Skip to: 31597 + /* 31566 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 31569 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 31583 + /* 31574 */ MCD_OPC_CheckPredicate, + 4, + 244, + 28, + 1, // Skip to: 104527 + /* 31579 */ MCD_OPC_Decode, + 154, + 16, + 22, // Opcode: FMAXNMP_ZPmZZ_H + /* 31583 */ MCD_OPC_FilterValue, + 1, + 235, + 28, + 1, // Skip to: 104527 + /* 31588 */ MCD_OPC_CheckPredicate, + 4, + 230, + 28, + 1, // Skip to: 104527 + /* 31593 */ MCD_OPC_Decode, + 216, + 16, + 22, // Opcode: FMINNMP_ZPmZZ_H + /* 31597 */ MCD_OPC_FilterValue, + 11, + 221, + 28, + 1, // Skip to: 104527 + /* 31602 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 31605 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 31619 + /* 31610 */ MCD_OPC_CheckPredicate, + 4, + 208, + 28, + 1, // Skip to: 104527 + /* 31615 */ MCD_OPC_Decode, + 183, + 16, + 22, // Opcode: FMAXP_ZPmZZ_H + /* 31619 */ MCD_OPC_FilterValue, + 1, + 199, + 28, + 1, // Skip to: 104527 + /* 31624 */ MCD_OPC_CheckPredicate, + 4, + 194, + 28, + 1, // Skip to: 104527 + /* 31629 */ MCD_OPC_Decode, + 245, + 16, + 22, // Opcode: FMINP_ZPmZZ_H + /* 31633 */ MCD_OPC_FilterValue, + 3, + 185, + 28, + 1, // Skip to: 104527 + /* 31638 */ MCD_OPC_CheckPredicate, + 14, + 180, + 28, + 1, // Skip to: 104527 + /* 31643 */ MCD_OPC_CheckField, + 10, + 3, + 0, + 173, + 28, + 1, // Skip to: 104527 + /* 31650 */ MCD_OPC_Decode, + 200, + 8, + 54, // Opcode: BFDOT_ZZZ + /* 31654 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 31675 + /* 31659 */ MCD_OPC_CheckPredicate, + 4, + 159, + 28, + 1, // Skip to: 104527 + /* 31664 */ MCD_OPC_CheckField, + 16, + 7, + 10, + 152, + 28, + 1, // Skip to: 104527 + /* 31671 */ MCD_OPC_Decode, + 166, + 15, + 24, // Opcode: FCVTXNT_ZPmZ_DtoS + /* 31675 */ MCD_OPC_FilterValue, + 3, + 143, + 28, + 1, // Skip to: 104527 + /* 31680 */ MCD_OPC_CheckPredicate, + 15, + 138, + 28, + 1, // Skip to: 104527 + /* 31685 */ MCD_OPC_CheckField, + 21, + 2, + 3, + 131, + 28, + 1, // Skip to: 104527 + /* 31692 */ MCD_OPC_CheckField, + 10, + 3, + 1, + 124, + 28, + 1, // Skip to: 104527 + /* 31699 */ MCD_OPC_Decode, + 212, + 8, + 54, // Opcode: BFMMLA_ZZZ + /* 31703 */ MCD_OPC_FilterValue, + 1, + 155, + 3, + 0, // Skip to: 32631 + /* 31708 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 31711 */ MCD_OPC_FilterValue, + 0, + 254, + 0, + 0, // Skip to: 31970 + /* 31716 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 31719 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 31734 + /* 31724 */ MCD_OPC_CheckPredicate, + 3, + 94, + 28, + 1, // Skip to: 104527 + /* 31729 */ MCD_OPC_Decode, + 232, + 13, + 166, + 1, // Opcode: FCMLA_ZPmZZ_S + /* 31734 */ MCD_OPC_FilterValue, + 1, + 84, + 28, + 1, // Skip to: 104527 + /* 31739 */ MCD_OPC_ExtractField, + 17, + 4, // Inst{20-17} ... + /* 31742 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 31764 + /* 31747 */ MCD_OPC_CheckPredicate, + 3, + 71, + 28, + 1, // Skip to: 104527 + /* 31752 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 64, + 28, + 1, // Skip to: 104527 + /* 31759 */ MCD_OPC_Decode, + 152, + 13, + 167, + 1, // Opcode: FCADD_ZPmZ_S + /* 31764 */ MCD_OPC_FilterValue, + 4, + 45, + 0, + 0, // Skip to: 31814 + /* 31769 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 31772 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 31793 + /* 31777 */ MCD_OPC_CheckPredicate, + 4, + 41, + 28, + 1, // Skip to: 104527 + /* 31782 */ MCD_OPC_CheckField, + 13, + 2, + 1, + 34, + 28, + 1, // Skip to: 104527 + /* 31789 */ MCD_OPC_Decode, + 245, + 14, + 24, // Opcode: FCVTNT_ZPmZ_StoH + /* 31793 */ MCD_OPC_FilterValue, + 1, + 25, + 28, + 1, // Skip to: 104527 + /* 31798 */ MCD_OPC_CheckPredicate, + 4, + 20, + 28, + 1, // Skip to: 104527 + /* 31803 */ MCD_OPC_CheckField, + 13, + 2, + 1, + 13, + 28, + 1, // Skip to: 104527 + /* 31810 */ MCD_OPC_Decode, + 196, + 14, + 24, // Opcode: FCVTLT_ZPmZ_HtoS + /* 31814 */ MCD_OPC_FilterValue, + 5, + 23, + 0, + 0, // Skip to: 31842 + /* 31819 */ MCD_OPC_CheckPredicate, + 14, + 255, + 27, + 1, // Skip to: 104527 + /* 31824 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 248, + 27, + 1, // Skip to: 104527 + /* 31831 */ MCD_OPC_CheckField, + 13, + 2, + 1, + 241, + 27, + 1, // Skip to: 104527 + /* 31838 */ MCD_OPC_Decode, + 197, + 8, + 24, // Opcode: BFCVTNT_ZPmZ + /* 31842 */ MCD_OPC_FilterValue, + 8, + 23, + 0, + 0, // Skip to: 31870 + /* 31847 */ MCD_OPC_CheckPredicate, + 4, + 227, + 27, + 1, // Skip to: 104527 + /* 31852 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 220, + 27, + 1, // Skip to: 104527 + /* 31859 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 213, + 27, + 1, // Skip to: 104527 + /* 31866 */ MCD_OPC_Decode, + 251, + 12, + 22, // Opcode: FADDP_ZPmZZ_S + /* 31870 */ MCD_OPC_FilterValue, + 10, + 45, + 0, + 0, // Skip to: 31920 + /* 31875 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 31878 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 31899 + /* 31883 */ MCD_OPC_CheckPredicate, + 4, + 191, + 27, + 1, // Skip to: 104527 + /* 31888 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 184, + 27, + 1, // Skip to: 104527 + /* 31895 */ MCD_OPC_Decode, + 155, + 16, + 22, // Opcode: FMAXNMP_ZPmZZ_S + /* 31899 */ MCD_OPC_FilterValue, + 1, + 175, + 27, + 1, // Skip to: 104527 + /* 31904 */ MCD_OPC_CheckPredicate, + 4, + 170, + 27, + 1, // Skip to: 104527 + /* 31909 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 163, + 27, + 1, // Skip to: 104527 + /* 31916 */ MCD_OPC_Decode, + 217, + 16, + 22, // Opcode: FMINNMP_ZPmZZ_S + /* 31920 */ MCD_OPC_FilterValue, + 11, + 154, + 27, + 1, // Skip to: 104527 + /* 31925 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 31928 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 31949 + /* 31933 */ MCD_OPC_CheckPredicate, + 4, + 141, + 27, + 1, // Skip to: 104527 + /* 31938 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 134, + 27, + 1, // Skip to: 104527 + /* 31945 */ MCD_OPC_Decode, + 184, + 16, + 22, // Opcode: FMAXP_ZPmZZ_S + /* 31949 */ MCD_OPC_FilterValue, + 1, + 125, + 27, + 1, // Skip to: 104527 + /* 31954 */ MCD_OPC_CheckPredicate, + 4, + 120, + 27, + 1, // Skip to: 104527 + /* 31959 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 113, + 27, + 1, // Skip to: 104527 + /* 31966 */ MCD_OPC_Decode, + 246, + 16, + 22, // Opcode: FMINP_ZPmZZ_S + /* 31970 */ MCD_OPC_FilterValue, + 1, + 247, + 0, + 0, // Skip to: 32222 + /* 31975 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 31978 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 32016 + /* 31983 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 31986 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 32001 + /* 31991 */ MCD_OPC_CheckPredicate, + 3, + 83, + 27, + 1, // Skip to: 104527 + /* 31996 */ MCD_OPC_Decode, + 162, + 17, + 147, + 1, // Opcode: FMLA_ZZZI_S + /* 32001 */ MCD_OPC_FilterValue, + 1, + 73, + 27, + 1, // Skip to: 104527 + /* 32006 */ MCD_OPC_CheckPredicate, + 3, + 68, + 27, + 1, // Skip to: 104527 + /* 32011 */ MCD_OPC_Decode, + 193, + 17, + 147, + 1, // Opcode: FMLS_ZZZI_S + /* 32016 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 32031 + /* 32021 */ MCD_OPC_CheckPredicate, + 3, + 53, + 27, + 1, // Skip to: 104527 + /* 32026 */ MCD_OPC_Decode, + 233, + 13, + 151, + 1, // Opcode: FCMLA_ZZZI_H + /* 32031 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 32053 + /* 32036 */ MCD_OPC_CheckPredicate, + 3, + 38, + 27, + 1, // Skip to: 104527 + /* 32041 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 31, + 27, + 1, // Skip to: 104527 + /* 32048 */ MCD_OPC_Decode, + 142, + 18, + 159, + 1, // Opcode: FMUL_ZZZI_S + /* 32053 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 32091 + /* 32058 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 32061 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 32076 + /* 32066 */ MCD_OPC_CheckPredicate, + 4, + 8, + 27, + 1, // Skip to: 104527 + /* 32071 */ MCD_OPC_Decode, + 149, + 17, + 149, + 1, // Opcode: FMLALB_ZZZI_SHH + /* 32076 */ MCD_OPC_FilterValue, + 1, + 254, + 26, + 1, // Skip to: 104527 + /* 32081 */ MCD_OPC_CheckPredicate, + 4, + 249, + 26, + 1, // Skip to: 104527 + /* 32086 */ MCD_OPC_Decode, + 151, + 17, + 149, + 1, // Opcode: FMLALT_ZZZI_SHH + /* 32091 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 32129 + /* 32096 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 32099 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 32114 + /* 32104 */ MCD_OPC_CheckPredicate, + 4, + 226, + 26, + 1, // Skip to: 104527 + /* 32109 */ MCD_OPC_Decode, + 180, + 17, + 149, + 1, // Opcode: FMLSLB_ZZZI_SHH + /* 32114 */ MCD_OPC_FilterValue, + 1, + 216, + 26, + 1, // Skip to: 104527 + /* 32119 */ MCD_OPC_CheckPredicate, + 4, + 211, + 26, + 1, // Skip to: 104527 + /* 32124 */ MCD_OPC_Decode, + 182, + 17, + 149, + 1, // Opcode: FMLSLT_ZZZI_SHH + /* 32129 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 32165 + /* 32134 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 32137 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 32151 + /* 32142 */ MCD_OPC_CheckPredicate, + 4, + 188, + 26, + 1, // Skip to: 104527 + /* 32147 */ MCD_OPC_Decode, + 150, + 17, + 54, // Opcode: FMLALB_ZZZ_SHH + /* 32151 */ MCD_OPC_FilterValue, + 1, + 179, + 26, + 1, // Skip to: 104527 + /* 32156 */ MCD_OPC_CheckPredicate, + 4, + 174, + 26, + 1, // Skip to: 104527 + /* 32161 */ MCD_OPC_Decode, + 152, + 17, + 54, // Opcode: FMLALT_ZZZ_SHH + /* 32165 */ MCD_OPC_FilterValue, + 10, + 31, + 0, + 0, // Skip to: 32201 + /* 32170 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 32173 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 32187 + /* 32178 */ MCD_OPC_CheckPredicate, + 4, + 152, + 26, + 1, // Skip to: 104527 + /* 32183 */ MCD_OPC_Decode, + 181, + 17, + 54, // Opcode: FMLSLB_ZZZ_SHH + /* 32187 */ MCD_OPC_FilterValue, + 1, + 143, + 26, + 1, // Skip to: 104527 + /* 32192 */ MCD_OPC_CheckPredicate, + 4, + 138, + 26, + 1, // Skip to: 104527 + /* 32197 */ MCD_OPC_Decode, + 183, + 17, + 54, // Opcode: FMLSLT_ZZZ_SHH + /* 32201 */ MCD_OPC_FilterValue, + 14, + 129, + 26, + 1, // Skip to: 104527 + /* 32206 */ MCD_OPC_CheckPredicate, + 16, + 124, + 26, + 1, // Skip to: 104527 + /* 32211 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 117, + 26, + 1, // Skip to: 104527 + /* 32218 */ MCD_OPC_Decode, + 208, + 17, + 54, // Opcode: FMMLA_ZZZ_S + /* 32222 */ MCD_OPC_FilterValue, + 2, + 226, + 0, + 0, // Skip to: 32453 + /* 32227 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 32230 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 32245 + /* 32235 */ MCD_OPC_CheckPredicate, + 3, + 95, + 26, + 1, // Skip to: 104527 + /* 32240 */ MCD_OPC_Decode, + 230, + 13, + 166, + 1, // Opcode: FCMLA_ZPmZZ_D + /* 32245 */ MCD_OPC_FilterValue, + 1, + 85, + 26, + 1, // Skip to: 104527 + /* 32250 */ MCD_OPC_ExtractField, + 17, + 4, // Inst{20-17} ... + /* 32253 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 32275 + /* 32258 */ MCD_OPC_CheckPredicate, + 3, + 72, + 26, + 1, // Skip to: 104527 + /* 32263 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 65, + 26, + 1, // Skip to: 104527 + /* 32270 */ MCD_OPC_Decode, + 150, + 13, + 167, + 1, // Opcode: FCADD_ZPmZ_D + /* 32275 */ MCD_OPC_FilterValue, + 5, + 45, + 0, + 0, // Skip to: 32325 + /* 32280 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 32283 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 32304 + /* 32288 */ MCD_OPC_CheckPredicate, + 4, + 42, + 26, + 1, // Skip to: 104527 + /* 32293 */ MCD_OPC_CheckField, + 13, + 2, + 1, + 35, + 26, + 1, // Skip to: 104527 + /* 32300 */ MCD_OPC_Decode, + 244, + 14, + 24, // Opcode: FCVTNT_ZPmZ_DtoS + /* 32304 */ MCD_OPC_FilterValue, + 1, + 26, + 26, + 1, // Skip to: 104527 + /* 32309 */ MCD_OPC_CheckPredicate, + 4, + 21, + 26, + 1, // Skip to: 104527 + /* 32314 */ MCD_OPC_CheckField, + 13, + 2, + 1, + 14, + 26, + 1, // Skip to: 104527 + /* 32321 */ MCD_OPC_Decode, + 197, + 14, + 24, // Opcode: FCVTLT_ZPmZ_StoD + /* 32325 */ MCD_OPC_FilterValue, + 8, + 23, + 0, + 0, // Skip to: 32353 + /* 32330 */ MCD_OPC_CheckPredicate, + 4, + 0, + 26, + 1, // Skip to: 104527 + /* 32335 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 249, + 25, + 1, // Skip to: 104527 + /* 32342 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 242, + 25, + 1, // Skip to: 104527 + /* 32349 */ MCD_OPC_Decode, + 249, + 12, + 22, // Opcode: FADDP_ZPmZZ_D + /* 32353 */ MCD_OPC_FilterValue, + 10, + 45, + 0, + 0, // Skip to: 32403 + /* 32358 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 32361 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 32382 + /* 32366 */ MCD_OPC_CheckPredicate, + 4, + 220, + 25, + 1, // Skip to: 104527 + /* 32371 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 213, + 25, + 1, // Skip to: 104527 + /* 32378 */ MCD_OPC_Decode, + 153, + 16, + 22, // Opcode: FMAXNMP_ZPmZZ_D + /* 32382 */ MCD_OPC_FilterValue, + 1, + 204, + 25, + 1, // Skip to: 104527 + /* 32387 */ MCD_OPC_CheckPredicate, + 4, + 199, + 25, + 1, // Skip to: 104527 + /* 32392 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 192, + 25, + 1, // Skip to: 104527 + /* 32399 */ MCD_OPC_Decode, + 215, + 16, + 22, // Opcode: FMINNMP_ZPmZZ_D + /* 32403 */ MCD_OPC_FilterValue, + 11, + 183, + 25, + 1, // Skip to: 104527 + /* 32408 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 32411 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 32432 + /* 32416 */ MCD_OPC_CheckPredicate, + 4, + 170, + 25, + 1, // Skip to: 104527 + /* 32421 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 163, + 25, + 1, // Skip to: 104527 + /* 32428 */ MCD_OPC_Decode, + 182, + 16, + 22, // Opcode: FMAXP_ZPmZZ_D + /* 32432 */ MCD_OPC_FilterValue, + 1, + 154, + 25, + 1, // Skip to: 104527 + /* 32437 */ MCD_OPC_CheckPredicate, + 4, + 149, + 25, + 1, // Skip to: 104527 + /* 32442 */ MCD_OPC_CheckField, + 13, + 2, + 0, + 142, + 25, + 1, // Skip to: 104527 + /* 32449 */ MCD_OPC_Decode, + 244, + 16, + 22, // Opcode: FMINP_ZPmZZ_D + /* 32453 */ MCD_OPC_FilterValue, + 3, + 133, + 25, + 1, // Skip to: 104527 + /* 32458 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 32461 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 32499 + /* 32466 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 32469 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 32484 + /* 32474 */ MCD_OPC_CheckPredicate, + 3, + 112, + 25, + 1, // Skip to: 104527 + /* 32479 */ MCD_OPC_Decode, + 160, + 17, + 148, + 1, // Opcode: FMLA_ZZZI_D + /* 32484 */ MCD_OPC_FilterValue, + 1, + 102, + 25, + 1, // Skip to: 104527 + /* 32489 */ MCD_OPC_CheckPredicate, + 3, + 97, + 25, + 1, // Skip to: 104527 + /* 32494 */ MCD_OPC_Decode, + 191, + 17, + 148, + 1, // Opcode: FMLS_ZZZI_D + /* 32499 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 32514 + /* 32504 */ MCD_OPC_CheckPredicate, + 3, + 82, + 25, + 1, // Skip to: 104527 + /* 32509 */ MCD_OPC_Decode, + 234, + 13, + 152, + 1, // Opcode: FCMLA_ZZZI_S + /* 32514 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 32536 + /* 32519 */ MCD_OPC_CheckPredicate, + 3, + 67, + 25, + 1, // Skip to: 104527 + /* 32524 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 60, + 25, + 1, // Skip to: 104527 + /* 32531 */ MCD_OPC_Decode, + 140, + 18, + 160, + 1, // Opcode: FMUL_ZZZI_D + /* 32536 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 32574 + /* 32541 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 32544 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 32559 + /* 32549 */ MCD_OPC_CheckPredicate, + 14, + 37, + 25, + 1, // Skip to: 104527 + /* 32554 */ MCD_OPC_Decode, + 208, + 8, + 149, + 1, // Opcode: BFMMLA_B_ZZI + /* 32559 */ MCD_OPC_FilterValue, + 1, + 27, + 25, + 1, // Skip to: 104527 + /* 32564 */ MCD_OPC_CheckPredicate, + 14, + 22, + 25, + 1, // Skip to: 104527 + /* 32569 */ MCD_OPC_Decode, + 210, + 8, + 149, + 1, // Opcode: BFMMLA_T_ZZI + /* 32574 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 32610 + /* 32579 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 32582 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 32596 + /* 32587 */ MCD_OPC_CheckPredicate, + 14, + 255, + 24, + 1, // Skip to: 104527 + /* 32592 */ MCD_OPC_Decode, + 209, + 8, + 54, // Opcode: BFMMLA_B_ZZZ + /* 32596 */ MCD_OPC_FilterValue, + 1, + 246, + 24, + 1, // Skip to: 104527 + /* 32601 */ MCD_OPC_CheckPredicate, + 14, + 241, + 24, + 1, // Skip to: 104527 + /* 32606 */ MCD_OPC_Decode, + 211, + 8, + 54, // Opcode: BFMMLA_T_ZZZ + /* 32610 */ MCD_OPC_FilterValue, + 14, + 232, + 24, + 1, // Skip to: 104527 + /* 32615 */ MCD_OPC_CheckPredicate, + 17, + 227, + 24, + 1, // Skip to: 104527 + /* 32620 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 220, + 24, + 1, // Skip to: 104527 + /* 32627 */ MCD_OPC_Decode, + 207, + 17, + 54, // Opcode: FMMLA_ZZZ_D + /* 32631 */ MCD_OPC_FilterValue, + 2, + 152, + 5, + 0, // Skip to: 34068 + /* 32636 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 32639 */ MCD_OPC_FilterValue, + 0, + 109, + 0, + 0, // Skip to: 32753 + /* 32644 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 32647 */ MCD_OPC_FilterValue, + 2, + 87, + 0, + 0, // Skip to: 32739 + /* 32652 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 32655 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 32669 + /* 32660 */ MCD_OPC_CheckPredicate, + 3, + 182, + 24, + 1, // Skip to: 104527 + /* 32665 */ MCD_OPC_Decode, + 143, + 13, + 45, // Opcode: FADD_ZZZ_H + /* 32669 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 32683 + /* 32674 */ MCD_OPC_CheckPredicate, + 3, + 168, + 24, + 1, // Skip to: 104527 + /* 32679 */ MCD_OPC_Decode, + 240, + 19, + 45, // Opcode: FSUB_ZZZ_H + /* 32683 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 32697 + /* 32688 */ MCD_OPC_CheckPredicate, + 3, + 154, + 24, + 1, // Skip to: 104527 + /* 32693 */ MCD_OPC_Decode, + 144, + 18, + 45, // Opcode: FMUL_ZZZ_H + /* 32697 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 32711 + /* 32702 */ MCD_OPC_CheckPredicate, + 6, + 140, + 24, + 1, // Skip to: 104527 + /* 32707 */ MCD_OPC_Decode, + 251, + 19, + 45, // Opcode: FTSMUL_ZZZ_H + /* 32711 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 32725 + /* 32716 */ MCD_OPC_CheckPredicate, + 3, + 126, + 24, + 1, // Skip to: 104527 + /* 32721 */ MCD_OPC_Decode, + 206, + 18, + 45, // Opcode: FRECPS_ZZZ_H + /* 32725 */ MCD_OPC_FilterValue, + 7, + 117, + 24, + 1, // Skip to: 104527 + /* 32730 */ MCD_OPC_CheckPredicate, + 3, + 112, + 24, + 1, // Skip to: 104527 + /* 32735 */ MCD_OPC_Decode, + 203, + 19, + 45, // Opcode: FRSQRTS_ZZZ_H + /* 32739 */ MCD_OPC_FilterValue, + 3, + 103, + 24, + 1, // Skip to: 104527 + /* 32744 */ MCD_OPC_CheckPredicate, + 3, + 98, + 24, + 1, // Skip to: 104527 + /* 32749 */ MCD_OPC_Decode, + 158, + 17, + 25, // Opcode: FMLA_ZPmZZ_H + /* 32753 */ MCD_OPC_FilterValue, + 1, + 15, + 1, + 0, // Skip to: 33029 + /* 32758 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 32761 */ MCD_OPC_FilterValue, + 2, + 249, + 0, + 0, // Skip to: 33015 + /* 32766 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 32769 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 32783 + /* 32774 */ MCD_OPC_CheckPredicate, + 3, + 68, + 24, + 1, // Skip to: 104527 + /* 32779 */ MCD_OPC_Decode, + 134, + 13, + 23, // Opcode: FADDV_VPZ_H + /* 32783 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 32797 + /* 32788 */ MCD_OPC_CheckPredicate, + 3, + 54, + 24, + 1, // Skip to: 104527 + /* 32793 */ MCD_OPC_Decode, + 166, + 16, + 23, // Opcode: FMAXNMV_VPZ_H + /* 32797 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 32811 + /* 32802 */ MCD_OPC_CheckPredicate, + 3, + 40, + 24, + 1, // Skip to: 104527 + /* 32807 */ MCD_OPC_Decode, + 228, + 16, + 23, // Opcode: FMINNMV_VPZ_H + /* 32811 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 32825 + /* 32816 */ MCD_OPC_CheckPredicate, + 3, + 26, + 24, + 1, // Skip to: 104527 + /* 32821 */ MCD_OPC_Decode, + 195, + 16, + 23, // Opcode: FMAXV_VPZ_H + /* 32825 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 32839 + /* 32830 */ MCD_OPC_CheckPredicate, + 3, + 12, + 24, + 1, // Skip to: 104527 + /* 32835 */ MCD_OPC_Decode, + 129, + 17, + 23, // Opcode: FMINV_VPZ_H + /* 32839 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 32860 + /* 32844 */ MCD_OPC_CheckPredicate, + 3, + 254, + 23, + 1, // Skip to: 104527 + /* 32849 */ MCD_OPC_CheckField, + 10, + 3, + 4, + 247, + 23, + 1, // Skip to: 104527 + /* 32856 */ MCD_OPC_Decode, + 192, + 18, + 63, // Opcode: FRECPE_ZZ_H + /* 32860 */ MCD_OPC_FilterValue, + 15, + 16, + 0, + 0, // Skip to: 32881 + /* 32865 */ MCD_OPC_CheckPredicate, + 3, + 233, + 23, + 1, // Skip to: 104527 + /* 32870 */ MCD_OPC_CheckField, + 10, + 3, + 4, + 226, + 23, + 1, // Skip to: 104527 + /* 32877 */ MCD_OPC_Decode, + 189, + 19, + 63, // Opcode: FRSQRTE_ZZ_H + /* 32881 */ MCD_OPC_FilterValue, + 16, + 33, + 0, + 0, // Skip to: 32919 + /* 32886 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 32889 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 32904 + /* 32894 */ MCD_OPC_CheckPredicate, + 3, + 204, + 23, + 1, // Skip to: 104527 + /* 32899 */ MCD_OPC_Decode, + 190, + 13, + 168, + 1, // Opcode: FCMGE_PPzZ0_H + /* 32904 */ MCD_OPC_FilterValue, + 1, + 194, + 23, + 1, // Skip to: 104527 + /* 32909 */ MCD_OPC_CheckPredicate, + 3, + 189, + 23, + 1, // Skip to: 104527 + /* 32914 */ MCD_OPC_Decode, + 212, + 13, + 168, + 1, // Opcode: FCMGT_PPzZ0_H + /* 32919 */ MCD_OPC_FilterValue, + 17, + 33, + 0, + 0, // Skip to: 32957 + /* 32924 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 32927 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 32942 + /* 32932 */ MCD_OPC_CheckPredicate, + 3, + 166, + 23, + 1, // Skip to: 104527 + /* 32937 */ MCD_OPC_Decode, + 255, + 13, + 168, + 1, // Opcode: FCMLT_PPzZ0_H + /* 32942 */ MCD_OPC_FilterValue, + 1, + 156, + 23, + 1, // Skip to: 104527 + /* 32947 */ MCD_OPC_CheckPredicate, + 3, + 151, + 23, + 1, // Skip to: 104527 + /* 32952 */ MCD_OPC_Decode, + 244, + 13, + 168, + 1, // Opcode: FCMLE_PPzZ0_H + /* 32957 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 32979 + /* 32962 */ MCD_OPC_CheckPredicate, + 3, + 136, + 23, + 1, // Skip to: 104527 + /* 32967 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 129, + 23, + 1, // Skip to: 104527 + /* 32974 */ MCD_OPC_Decode, + 168, + 13, + 168, + 1, // Opcode: FCMEQ_PPzZ0_H + /* 32979 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 33001 + /* 32984 */ MCD_OPC_CheckPredicate, + 3, + 114, + 23, + 1, // Skip to: 104527 + /* 32989 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 107, + 23, + 1, // Skip to: 104527 + /* 32996 */ MCD_OPC_Decode, + 138, + 14, + 168, + 1, // Opcode: FCMNE_PPzZ0_H + /* 33001 */ MCD_OPC_FilterValue, + 24, + 97, + 23, + 1, // Skip to: 104527 + /* 33006 */ MCD_OPC_CheckPredicate, + 6, + 92, + 23, + 1, // Skip to: 104527 + /* 33011 */ MCD_OPC_Decode, + 245, + 12, + 22, // Opcode: FADDA_VPZ_H + /* 33015 */ MCD_OPC_FilterValue, + 3, + 83, + 23, + 1, // Skip to: 104527 + /* 33020 */ MCD_OPC_CheckPredicate, + 3, + 78, + 23, + 1, // Skip to: 104527 + /* 33025 */ MCD_OPC_Decode, + 189, + 17, + 25, // Opcode: FMLS_ZPmZZ_H + /* 33029 */ MCD_OPC_FilterValue, + 2, + 53, + 0, + 0, // Skip to: 33087 + /* 33034 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 33037 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 33073 + /* 33042 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 33045 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 33059 + /* 33050 */ MCD_OPC_CheckPredicate, + 3, + 48, + 23, + 1, // Skip to: 104527 + /* 33055 */ MCD_OPC_Decode, + 193, + 13, + 109, // Opcode: FCMGE_PPzZZ_H + /* 33059 */ MCD_OPC_FilterValue, + 1, + 39, + 23, + 1, // Skip to: 104527 + /* 33064 */ MCD_OPC_CheckPredicate, + 3, + 34, + 23, + 1, // Skip to: 104527 + /* 33069 */ MCD_OPC_Decode, + 215, + 13, + 109, // Opcode: FCMGT_PPzZZ_H + /* 33073 */ MCD_OPC_FilterValue, + 3, + 25, + 23, + 1, // Skip to: 104527 + /* 33078 */ MCD_OPC_CheckPredicate, + 3, + 20, + 23, + 1, // Skip to: 104527 + /* 33083 */ MCD_OPC_Decode, + 177, + 18, + 25, // Opcode: FNMLA_ZPmZZ_H + /* 33087 */ MCD_OPC_FilterValue, + 3, + 53, + 0, + 0, // Skip to: 33145 + /* 33092 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 33095 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 33131 + /* 33100 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 33103 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 33117 + /* 33108 */ MCD_OPC_CheckPredicate, + 3, + 246, + 22, + 1, // Skip to: 104527 + /* 33113 */ MCD_OPC_Decode, + 171, + 13, + 109, // Opcode: FCMEQ_PPzZZ_H + /* 33117 */ MCD_OPC_FilterValue, + 1, + 237, + 22, + 1, // Skip to: 104527 + /* 33122 */ MCD_OPC_CheckPredicate, + 3, + 232, + 22, + 1, // Skip to: 104527 + /* 33127 */ MCD_OPC_Decode, + 141, + 14, + 109, // Opcode: FCMNE_PPzZZ_H + /* 33131 */ MCD_OPC_FilterValue, + 3, + 223, + 22, + 1, // Skip to: 104527 + /* 33136 */ MCD_OPC_CheckPredicate, + 3, + 218, + 22, + 1, // Skip to: 104527 + /* 33141 */ MCD_OPC_Decode, + 180, + 18, + 25, // Opcode: FNMLS_ZPmZZ_H + /* 33145 */ MCD_OPC_FilterValue, + 4, + 173, + 1, + 0, // Skip to: 33579 + /* 33150 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 33153 */ MCD_OPC_FilterValue, + 2, + 151, + 1, + 0, // Skip to: 33565 + /* 33158 */ MCD_OPC_ExtractField, + 19, + 2, // Inst{20-19} ... + /* 33161 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 33281 + /* 33166 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 33169 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 33183 + /* 33174 */ MCD_OPC_CheckPredicate, + 3, + 180, + 22, + 1, // Skip to: 104527 + /* 33179 */ MCD_OPC_Decode, + 140, + 13, + 22, // Opcode: FADD_ZPmZ_H + /* 33183 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 33197 + /* 33188 */ MCD_OPC_CheckPredicate, + 3, + 166, + 22, + 1, // Skip to: 104527 + /* 33193 */ MCD_OPC_Decode, + 237, + 19, + 22, // Opcode: FSUB_ZPmZ_H + /* 33197 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 33211 + /* 33202 */ MCD_OPC_CheckPredicate, + 3, + 152, + 22, + 1, // Skip to: 104527 + /* 33207 */ MCD_OPC_Decode, + 138, + 18, + 22, // Opcode: FMUL_ZPmZ_H + /* 33211 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 33225 + /* 33216 */ MCD_OPC_CheckPredicate, + 3, + 138, + 22, + 1, // Skip to: 104527 + /* 33221 */ MCD_OPC_Decode, + 230, + 19, + 22, // Opcode: FSUBR_ZPmZ_H + /* 33225 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 33239 + /* 33230 */ MCD_OPC_CheckPredicate, + 3, + 124, + 22, + 1, // Skip to: 104527 + /* 33235 */ MCD_OPC_Decode, + 175, + 16, + 22, // Opcode: FMAXNM_ZPmZ_H + /* 33239 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 33253 + /* 33244 */ MCD_OPC_CheckPredicate, + 3, + 110, + 22, + 1, // Skip to: 104527 + /* 33249 */ MCD_OPC_Decode, + 237, + 16, + 22, // Opcode: FMINNM_ZPmZ_H + /* 33253 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 33267 + /* 33258 */ MCD_OPC_CheckPredicate, + 3, + 96, + 22, + 1, // Skip to: 104527 + /* 33263 */ MCD_OPC_Decode, + 204, + 16, + 22, // Opcode: FMAX_ZPmZ_H + /* 33267 */ MCD_OPC_FilterValue, + 7, + 87, + 22, + 1, // Skip to: 104527 + /* 33272 */ MCD_OPC_CheckPredicate, + 3, + 82, + 22, + 1, // Skip to: 104527 + /* 33277 */ MCD_OPC_Decode, + 138, + 17, + 22, // Opcode: FMIN_ZPmZ_H + /* 33281 */ MCD_OPC_FilterValue, + 1, + 73, + 0, + 0, // Skip to: 33359 + /* 33286 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 33289 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 33303 + /* 33294 */ MCD_OPC_CheckPredicate, + 3, + 60, + 22, + 1, // Skip to: 104527 + /* 33299 */ MCD_OPC_Decode, + 204, + 12, + 22, // Opcode: FABD_ZPmZ_H + /* 33303 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 33317 + /* 33308 */ MCD_OPC_CheckPredicate, + 3, + 46, + 22, + 1, // Skip to: 104527 + /* 33313 */ MCD_OPC_Decode, + 211, + 19, + 22, // Opcode: FSCALE_ZPmZ_H + /* 33317 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 33331 + /* 33322 */ MCD_OPC_CheckPredicate, + 3, + 32, + 22, + 1, // Skip to: 104527 + /* 33327 */ MCD_OPC_Decode, + 247, + 17, + 22, // Opcode: FMULX_ZPmZ_H + /* 33331 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 33345 + /* 33336 */ MCD_OPC_CheckPredicate, + 3, + 18, + 22, + 1, // Skip to: 104527 + /* 33341 */ MCD_OPC_Decode, + 250, + 15, + 22, // Opcode: FDIVR_ZPmZ_H + /* 33345 */ MCD_OPC_FilterValue, + 5, + 9, + 22, + 1, // Skip to: 104527 + /* 33350 */ MCD_OPC_CheckPredicate, + 3, + 4, + 22, + 1, // Skip to: 104527 + /* 33355 */ MCD_OPC_Decode, + 254, + 15, + 22, // Opcode: FDIV_ZPmZ_H + /* 33359 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 33381 + /* 33364 */ MCD_OPC_CheckPredicate, + 6, + 246, + 21, + 1, // Skip to: 104527 + /* 33369 */ MCD_OPC_CheckField, + 10, + 3, + 0, + 239, + 21, + 1, // Skip to: 104527 + /* 33376 */ MCD_OPC_Decode, + 248, + 19, + 169, + 1, // Opcode: FTMAD_ZZI_H + /* 33381 */ MCD_OPC_FilterValue, + 3, + 229, + 21, + 1, // Skip to: 104527 + /* 33386 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 33389 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 33411 + /* 33394 */ MCD_OPC_CheckPredicate, + 3, + 216, + 21, + 1, // Skip to: 104527 + /* 33399 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 209, + 21, + 1, // Skip to: 104527 + /* 33406 */ MCD_OPC_Decode, + 137, + 13, + 170, + 1, // Opcode: FADD_ZPmI_H + /* 33411 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 33433 + /* 33416 */ MCD_OPC_CheckPredicate, + 3, + 194, + 21, + 1, // Skip to: 104527 + /* 33421 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 187, + 21, + 1, // Skip to: 104527 + /* 33428 */ MCD_OPC_Decode, + 234, + 19, + 170, + 1, // Opcode: FSUB_ZPmI_H + /* 33433 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 33455 + /* 33438 */ MCD_OPC_CheckPredicate, + 3, + 172, + 21, + 1, // Skip to: 104527 + /* 33443 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 165, + 21, + 1, // Skip to: 104527 + /* 33450 */ MCD_OPC_Decode, + 135, + 18, + 170, + 1, // Opcode: FMUL_ZPmI_H + /* 33455 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 33477 + /* 33460 */ MCD_OPC_CheckPredicate, + 3, + 150, + 21, + 1, // Skip to: 104527 + /* 33465 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 143, + 21, + 1, // Skip to: 104527 + /* 33472 */ MCD_OPC_Decode, + 227, + 19, + 170, + 1, // Opcode: FSUBR_ZPmI_H + /* 33477 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 33499 + /* 33482 */ MCD_OPC_CheckPredicate, + 3, + 128, + 21, + 1, // Skip to: 104527 + /* 33487 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 121, + 21, + 1, // Skip to: 104527 + /* 33494 */ MCD_OPC_Decode, + 172, + 16, + 170, + 1, // Opcode: FMAXNM_ZPmI_H + /* 33499 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 33521 + /* 33504 */ MCD_OPC_CheckPredicate, + 3, + 106, + 21, + 1, // Skip to: 104527 + /* 33509 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 99, + 21, + 1, // Skip to: 104527 + /* 33516 */ MCD_OPC_Decode, + 234, + 16, + 170, + 1, // Opcode: FMINNM_ZPmI_H + /* 33521 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 33543 + /* 33526 */ MCD_OPC_CheckPredicate, + 3, + 84, + 21, + 1, // Skip to: 104527 + /* 33531 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 77, + 21, + 1, // Skip to: 104527 + /* 33538 */ MCD_OPC_Decode, + 201, + 16, + 170, + 1, // Opcode: FMAX_ZPmI_H + /* 33543 */ MCD_OPC_FilterValue, + 7, + 67, + 21, + 1, // Skip to: 104527 + /* 33548 */ MCD_OPC_CheckPredicate, + 3, + 62, + 21, + 1, // Skip to: 104527 + /* 33553 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 55, + 21, + 1, // Skip to: 104527 + /* 33560 */ MCD_OPC_Decode, + 135, + 17, + 170, + 1, // Opcode: FMIN_ZPmI_H + /* 33565 */ MCD_OPC_FilterValue, + 3, + 45, + 21, + 1, // Skip to: 104527 + /* 33570 */ MCD_OPC_CheckPredicate, + 3, + 40, + 21, + 1, // Skip to: 104527 + /* 33575 */ MCD_OPC_Decode, + 147, + 16, + 25, // Opcode: FMAD_ZPmZZ_H + /* 33579 */ MCD_OPC_FilterValue, + 5, + 127, + 1, + 0, // Skip to: 33967 + /* 33584 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 33587 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 33651 + /* 33592 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 33595 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 33609 + /* 33600 */ MCD_OPC_CheckPredicate, + 4, + 10, + 21, + 1, // Skip to: 104527 + /* 33605 */ MCD_OPC_Decode, + 170, + 15, + 24, // Opcode: FCVTX_ZPmZ_DtoS + /* 33609 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 33623 + /* 33614 */ MCD_OPC_CheckPredicate, + 4, + 252, + 20, + 1, // Skip to: 104527 + /* 33619 */ MCD_OPC_Decode, + 141, + 16, + 24, // Opcode: FLOGB_ZPmZ_H + /* 33623 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 33637 + /* 33628 */ MCD_OPC_CheckPredicate, + 4, + 238, + 20, + 1, // Skip to: 104527 + /* 33633 */ MCD_OPC_Decode, + 142, + 16, + 24, // Opcode: FLOGB_ZPmZ_S + /* 33637 */ MCD_OPC_FilterValue, + 30, + 229, + 20, + 1, // Skip to: 104527 + /* 33642 */ MCD_OPC_CheckPredicate, + 4, + 224, + 20, + 1, // Skip to: 104527 + /* 33647 */ MCD_OPC_Decode, + 140, + 16, + 24, // Opcode: FLOGB_ZPmZ_D + /* 33651 */ MCD_OPC_FilterValue, + 2, + 41, + 1, + 0, // Skip to: 33953 + /* 33656 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 33659 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 33673 + /* 33664 */ MCD_OPC_CheckPredicate, + 3, + 202, + 20, + 1, // Skip to: 104527 + /* 33669 */ MCD_OPC_Decode, + 148, + 19, + 24, // Opcode: FRINTN_ZPmZ_H + /* 33673 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 33687 + /* 33678 */ MCD_OPC_CheckPredicate, + 3, + 188, + 20, + 1, // Skip to: 104527 + /* 33683 */ MCD_OPC_Decode, + 159, + 19, + 24, // Opcode: FRINTP_ZPmZ_H + /* 33687 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 33701 + /* 33692 */ MCD_OPC_CheckPredicate, + 3, + 174, + 20, + 1, // Skip to: 104527 + /* 33697 */ MCD_OPC_Decode, + 137, + 19, + 24, // Opcode: FRINTM_ZPmZ_H + /* 33701 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 33715 + /* 33706 */ MCD_OPC_CheckPredicate, + 3, + 160, + 20, + 1, // Skip to: 104527 + /* 33711 */ MCD_OPC_Decode, + 181, + 19, + 24, // Opcode: FRINTZ_ZPmZ_H + /* 33715 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 33729 + /* 33720 */ MCD_OPC_CheckPredicate, + 3, + 146, + 20, + 1, // Skip to: 104527 + /* 33725 */ MCD_OPC_Decode, + 243, + 18, + 24, // Opcode: FRINTA_ZPmZ_H + /* 33729 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 33743 + /* 33734 */ MCD_OPC_CheckPredicate, + 3, + 132, + 20, + 1, // Skip to: 104527 + /* 33739 */ MCD_OPC_Decode, + 170, + 19, + 24, // Opcode: FRINTX_ZPmZ_H + /* 33743 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 33757 + /* 33748 */ MCD_OPC_CheckPredicate, + 3, + 118, + 20, + 1, // Skip to: 104527 + /* 33753 */ MCD_OPC_Decode, + 254, + 18, + 24, // Opcode: FRINTI_ZPmZ_H + /* 33757 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 33771 + /* 33762 */ MCD_OPC_CheckPredicate, + 3, + 104, + 20, + 1, // Skip to: 104527 + /* 33767 */ MCD_OPC_Decode, + 214, + 18, + 24, // Opcode: FRECPX_ZPmZ_H + /* 33771 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 33785 + /* 33776 */ MCD_OPC_CheckPredicate, + 3, + 90, + 20, + 1, // Skip to: 104527 + /* 33781 */ MCD_OPC_Decode, + 217, + 19, + 24, // Opcode: FSQRT_ZPmZ_H + /* 33785 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 33799 + /* 33790 */ MCD_OPC_CheckPredicate, + 3, + 76, + 20, + 1, // Skip to: 104527 + /* 33795 */ MCD_OPC_Decode, + 214, + 30, + 24, // Opcode: SCVTF_ZPmZ_HtoH + /* 33799 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 33813 + /* 33804 */ MCD_OPC_CheckPredicate, + 3, + 62, + 20, + 1, // Skip to: 104527 + /* 33809 */ MCD_OPC_Decode, + 203, + 42, + 24, // Opcode: UCVTF_ZPmZ_HtoH + /* 33813 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 33827 + /* 33818 */ MCD_OPC_CheckPredicate, + 3, + 48, + 20, + 1, // Skip to: 104527 + /* 33823 */ MCD_OPC_Decode, + 216, + 30, + 24, // Opcode: SCVTF_ZPmZ_StoH + /* 33827 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 33841 + /* 33832 */ MCD_OPC_CheckPredicate, + 3, + 34, + 20, + 1, // Skip to: 104527 + /* 33837 */ MCD_OPC_Decode, + 205, + 42, + 24, // Opcode: UCVTF_ZPmZ_StoH + /* 33841 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 33855 + /* 33846 */ MCD_OPC_CheckPredicate, + 3, + 20, + 20, + 1, // Skip to: 104527 + /* 33851 */ MCD_OPC_Decode, + 212, + 30, + 24, // Opcode: SCVTF_ZPmZ_DtoH + /* 33855 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 33869 + /* 33860 */ MCD_OPC_CheckPredicate, + 3, + 6, + 20, + 1, // Skip to: 104527 + /* 33865 */ MCD_OPC_Decode, + 201, + 42, + 24, // Opcode: UCVTF_ZPmZ_DtoH + /* 33869 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 33883 + /* 33874 */ MCD_OPC_CheckPredicate, + 3, + 248, + 19, + 1, // Skip to: 104527 + /* 33879 */ MCD_OPC_Decode, + 186, + 15, + 24, // Opcode: FCVTZS_ZPmZ_HtoH + /* 33883 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 33897 + /* 33888 */ MCD_OPC_CheckPredicate, + 3, + 234, + 19, + 1, // Skip to: 104527 + /* 33893 */ MCD_OPC_Decode, + 221, + 15, + 24, // Opcode: FCVTZU_ZPmZ_HtoH + /* 33897 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 33911 + /* 33902 */ MCD_OPC_CheckPredicate, + 3, + 220, + 19, + 1, // Skip to: 104527 + /* 33907 */ MCD_OPC_Decode, + 187, + 15, + 24, // Opcode: FCVTZS_ZPmZ_HtoS + /* 33911 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 33925 + /* 33916 */ MCD_OPC_CheckPredicate, + 3, + 206, + 19, + 1, // Skip to: 104527 + /* 33921 */ MCD_OPC_Decode, + 222, + 15, + 24, // Opcode: FCVTZU_ZPmZ_HtoS + /* 33925 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 33939 + /* 33930 */ MCD_OPC_CheckPredicate, + 3, + 192, + 19, + 1, // Skip to: 104527 + /* 33935 */ MCD_OPC_Decode, + 185, + 15, + 24, // Opcode: FCVTZS_ZPmZ_HtoD + /* 33939 */ MCD_OPC_FilterValue, + 31, + 183, + 19, + 1, // Skip to: 104527 + /* 33944 */ MCD_OPC_CheckPredicate, + 3, + 178, + 19, + 1, // Skip to: 104527 + /* 33949 */ MCD_OPC_Decode, + 220, + 15, + 24, // Opcode: FCVTZU_ZPmZ_HtoD + /* 33953 */ MCD_OPC_FilterValue, + 3, + 169, + 19, + 1, // Skip to: 104527 + /* 33958 */ MCD_OPC_CheckPredicate, + 3, + 164, + 19, + 1, // Skip to: 104527 + /* 33963 */ MCD_OPC_Decode, + 235, + 17, + 25, // Opcode: FMSB_ZPmZZ_H + /* 33967 */ MCD_OPC_FilterValue, + 6, + 53, + 0, + 0, // Skip to: 34025 + /* 33972 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 33975 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 34011 + /* 33980 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 33983 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 33997 + /* 33988 */ MCD_OPC_CheckPredicate, + 3, + 134, + 19, + 1, // Skip to: 104527 + /* 33993 */ MCD_OPC_Decode, + 156, + 14, + 109, // Opcode: FCMUO_PPzZZ_H + /* 33997 */ MCD_OPC_FilterValue, + 1, + 125, + 19, + 1, // Skip to: 104527 + /* 34002 */ MCD_OPC_CheckPredicate, + 3, + 120, + 19, + 1, // Skip to: 104527 + /* 34007 */ MCD_OPC_Decode, + 226, + 12, + 109, // Opcode: FACGE_PPzZZ_H + /* 34011 */ MCD_OPC_FilterValue, + 3, + 111, + 19, + 1, // Skip to: 104527 + /* 34016 */ MCD_OPC_CheckPredicate, + 3, + 106, + 19, + 1, // Skip to: 104527 + /* 34021 */ MCD_OPC_Decode, + 174, + 18, + 25, // Opcode: FNMAD_ZPmZZ_H + /* 34025 */ MCD_OPC_FilterValue, + 7, + 97, + 19, + 1, // Skip to: 104527 + /* 34030 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 34033 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 34054 + /* 34038 */ MCD_OPC_CheckPredicate, + 3, + 84, + 19, + 1, // Skip to: 104527 + /* 34043 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 77, + 19, + 1, // Skip to: 104527 + /* 34050 */ MCD_OPC_Decode, + 237, + 12, + 109, // Opcode: FACGT_PPzZZ_H + /* 34054 */ MCD_OPC_FilterValue, + 3, + 68, + 19, + 1, // Skip to: 104527 + /* 34059 */ MCD_OPC_CheckPredicate, + 3, + 63, + 19, + 1, // Skip to: 104527 + /* 34064 */ MCD_OPC_Decode, + 183, + 18, + 25, // Opcode: FNMSB_ZPmZZ_H + /* 34068 */ MCD_OPC_FilterValue, + 3, + 54, + 19, + 1, // Skip to: 104527 + /* 34073 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 34076 */ MCD_OPC_FilterValue, + 0, + 215, + 0, + 0, // Skip to: 34296 + /* 34081 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 34084 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 34176 + /* 34089 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 34092 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 34106 + /* 34097 */ MCD_OPC_CheckPredicate, + 3, + 25, + 19, + 1, // Skip to: 104527 + /* 34102 */ MCD_OPC_Decode, + 144, + 13, + 45, // Opcode: FADD_ZZZ_S + /* 34106 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 34120 + /* 34111 */ MCD_OPC_CheckPredicate, + 3, + 11, + 19, + 1, // Skip to: 104527 + /* 34116 */ MCD_OPC_Decode, + 241, + 19, + 45, // Opcode: FSUB_ZZZ_S + /* 34120 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 34134 + /* 34125 */ MCD_OPC_CheckPredicate, + 3, + 253, + 18, + 1, // Skip to: 104527 + /* 34130 */ MCD_OPC_Decode, + 145, + 18, + 45, // Opcode: FMUL_ZZZ_S + /* 34134 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 34148 + /* 34139 */ MCD_OPC_CheckPredicate, + 6, + 239, + 18, + 1, // Skip to: 104527 + /* 34144 */ MCD_OPC_Decode, + 252, + 19, + 45, // Opcode: FTSMUL_ZZZ_S + /* 34148 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 34162 + /* 34153 */ MCD_OPC_CheckPredicate, + 3, + 225, + 18, + 1, // Skip to: 104527 + /* 34158 */ MCD_OPC_Decode, + 207, + 18, + 45, // Opcode: FRECPS_ZZZ_S + /* 34162 */ MCD_OPC_FilterValue, + 7, + 216, + 18, + 1, // Skip to: 104527 + /* 34167 */ MCD_OPC_CheckPredicate, + 3, + 211, + 18, + 1, // Skip to: 104527 + /* 34172 */ MCD_OPC_Decode, + 204, + 19, + 45, // Opcode: FRSQRTS_ZZZ_S + /* 34176 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 34190 + /* 34181 */ MCD_OPC_CheckPredicate, + 3, + 197, + 18, + 1, // Skip to: 104527 + /* 34186 */ MCD_OPC_Decode, + 159, + 17, + 25, // Opcode: FMLA_ZPmZZ_S + /* 34190 */ MCD_OPC_FilterValue, + 2, + 87, + 0, + 0, // Skip to: 34282 + /* 34195 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 34198 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 34212 + /* 34203 */ MCD_OPC_CheckPredicate, + 3, + 175, + 18, + 1, // Skip to: 104527 + /* 34208 */ MCD_OPC_Decode, + 142, + 13, + 45, // Opcode: FADD_ZZZ_D + /* 34212 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 34226 + /* 34217 */ MCD_OPC_CheckPredicate, + 3, + 161, + 18, + 1, // Skip to: 104527 + /* 34222 */ MCD_OPC_Decode, + 239, + 19, + 45, // Opcode: FSUB_ZZZ_D + /* 34226 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 34240 + /* 34231 */ MCD_OPC_CheckPredicate, + 3, + 147, + 18, + 1, // Skip to: 104527 + /* 34236 */ MCD_OPC_Decode, + 143, + 18, + 45, // Opcode: FMUL_ZZZ_D + /* 34240 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 34254 + /* 34245 */ MCD_OPC_CheckPredicate, + 6, + 133, + 18, + 1, // Skip to: 104527 + /* 34250 */ MCD_OPC_Decode, + 250, + 19, + 45, // Opcode: FTSMUL_ZZZ_D + /* 34254 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 34268 + /* 34259 */ MCD_OPC_CheckPredicate, + 3, + 119, + 18, + 1, // Skip to: 104527 + /* 34264 */ MCD_OPC_Decode, + 205, + 18, + 45, // Opcode: FRECPS_ZZZ_D + /* 34268 */ MCD_OPC_FilterValue, + 7, + 110, + 18, + 1, // Skip to: 104527 + /* 34273 */ MCD_OPC_CheckPredicate, + 3, + 105, + 18, + 1, // Skip to: 104527 + /* 34278 */ MCD_OPC_Decode, + 202, + 19, + 45, // Opcode: FRSQRTS_ZZZ_D + /* 34282 */ MCD_OPC_FilterValue, + 3, + 96, + 18, + 1, // Skip to: 104527 + /* 34287 */ MCD_OPC_CheckPredicate, + 3, + 91, + 18, + 1, // Skip to: 104527 + /* 34292 */ MCD_OPC_Decode, + 157, + 17, + 25, // Opcode: FMLA_ZPmZZ_D + /* 34296 */ MCD_OPC_FilterValue, + 1, + 27, + 2, + 0, // Skip to: 34840 + /* 34301 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 34304 */ MCD_OPC_FilterValue, + 0, + 249, + 0, + 0, // Skip to: 34558 + /* 34309 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 34312 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 34326 + /* 34317 */ MCD_OPC_CheckPredicate, + 3, + 61, + 18, + 1, // Skip to: 104527 + /* 34322 */ MCD_OPC_Decode, + 135, + 13, + 23, // Opcode: FADDV_VPZ_S + /* 34326 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 34340 + /* 34331 */ MCD_OPC_CheckPredicate, + 3, + 47, + 18, + 1, // Skip to: 104527 + /* 34336 */ MCD_OPC_Decode, + 167, + 16, + 23, // Opcode: FMAXNMV_VPZ_S + /* 34340 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 34354 + /* 34345 */ MCD_OPC_CheckPredicate, + 3, + 33, + 18, + 1, // Skip to: 104527 + /* 34350 */ MCD_OPC_Decode, + 229, + 16, + 23, // Opcode: FMINNMV_VPZ_S + /* 34354 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 34368 + /* 34359 */ MCD_OPC_CheckPredicate, + 3, + 19, + 18, + 1, // Skip to: 104527 + /* 34364 */ MCD_OPC_Decode, + 196, + 16, + 23, // Opcode: FMAXV_VPZ_S + /* 34368 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 34382 + /* 34373 */ MCD_OPC_CheckPredicate, + 3, + 5, + 18, + 1, // Skip to: 104527 + /* 34378 */ MCD_OPC_Decode, + 130, + 17, + 23, // Opcode: FMINV_VPZ_S + /* 34382 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 34403 + /* 34387 */ MCD_OPC_CheckPredicate, + 3, + 247, + 17, + 1, // Skip to: 104527 + /* 34392 */ MCD_OPC_CheckField, + 10, + 3, + 4, + 240, + 17, + 1, // Skip to: 104527 + /* 34399 */ MCD_OPC_Decode, + 193, + 18, + 63, // Opcode: FRECPE_ZZ_S + /* 34403 */ MCD_OPC_FilterValue, + 15, + 16, + 0, + 0, // Skip to: 34424 + /* 34408 */ MCD_OPC_CheckPredicate, + 3, + 226, + 17, + 1, // Skip to: 104527 + /* 34413 */ MCD_OPC_CheckField, + 10, + 3, + 4, + 219, + 17, + 1, // Skip to: 104527 + /* 34420 */ MCD_OPC_Decode, + 190, + 19, + 63, // Opcode: FRSQRTE_ZZ_S + /* 34424 */ MCD_OPC_FilterValue, + 16, + 33, + 0, + 0, // Skip to: 34462 + /* 34429 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 34432 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 34447 + /* 34437 */ MCD_OPC_CheckPredicate, + 3, + 197, + 17, + 1, // Skip to: 104527 + /* 34442 */ MCD_OPC_Decode, + 191, + 13, + 168, + 1, // Opcode: FCMGE_PPzZ0_S + /* 34447 */ MCD_OPC_FilterValue, + 1, + 187, + 17, + 1, // Skip to: 104527 + /* 34452 */ MCD_OPC_CheckPredicate, + 3, + 182, + 17, + 1, // Skip to: 104527 + /* 34457 */ MCD_OPC_Decode, + 213, + 13, + 168, + 1, // Opcode: FCMGT_PPzZ0_S + /* 34462 */ MCD_OPC_FilterValue, + 17, + 33, + 0, + 0, // Skip to: 34500 + /* 34467 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 34470 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 34485 + /* 34475 */ MCD_OPC_CheckPredicate, + 3, + 159, + 17, + 1, // Skip to: 104527 + /* 34480 */ MCD_OPC_Decode, + 128, + 14, + 168, + 1, // Opcode: FCMLT_PPzZ0_S + /* 34485 */ MCD_OPC_FilterValue, + 1, + 149, + 17, + 1, // Skip to: 104527 + /* 34490 */ MCD_OPC_CheckPredicate, + 3, + 144, + 17, + 1, // Skip to: 104527 + /* 34495 */ MCD_OPC_Decode, + 245, + 13, + 168, + 1, // Opcode: FCMLE_PPzZ0_S + /* 34500 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 34522 + /* 34505 */ MCD_OPC_CheckPredicate, + 3, + 129, + 17, + 1, // Skip to: 104527 + /* 34510 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 122, + 17, + 1, // Skip to: 104527 + /* 34517 */ MCD_OPC_Decode, + 169, + 13, + 168, + 1, // Opcode: FCMEQ_PPzZ0_S + /* 34522 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 34544 + /* 34527 */ MCD_OPC_CheckPredicate, + 3, + 107, + 17, + 1, // Skip to: 104527 + /* 34532 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 100, + 17, + 1, // Skip to: 104527 + /* 34539 */ MCD_OPC_Decode, + 139, + 14, + 168, + 1, // Opcode: FCMNE_PPzZ0_S + /* 34544 */ MCD_OPC_FilterValue, + 24, + 90, + 17, + 1, // Skip to: 104527 + /* 34549 */ MCD_OPC_CheckPredicate, + 6, + 85, + 17, + 1, // Skip to: 104527 + /* 34554 */ MCD_OPC_Decode, + 246, + 12, + 22, // Opcode: FADDA_VPZ_S + /* 34558 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 34572 + /* 34563 */ MCD_OPC_CheckPredicate, + 3, + 71, + 17, + 1, // Skip to: 104527 + /* 34568 */ MCD_OPC_Decode, + 190, + 17, + 25, // Opcode: FMLS_ZPmZZ_S + /* 34572 */ MCD_OPC_FilterValue, + 2, + 249, + 0, + 0, // Skip to: 34826 + /* 34577 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 34580 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 34594 + /* 34585 */ MCD_OPC_CheckPredicate, + 3, + 49, + 17, + 1, // Skip to: 104527 + /* 34590 */ MCD_OPC_Decode, + 133, + 13, + 23, // Opcode: FADDV_VPZ_D + /* 34594 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 34608 + /* 34599 */ MCD_OPC_CheckPredicate, + 3, + 35, + 17, + 1, // Skip to: 104527 + /* 34604 */ MCD_OPC_Decode, + 165, + 16, + 23, // Opcode: FMAXNMV_VPZ_D + /* 34608 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 34622 + /* 34613 */ MCD_OPC_CheckPredicate, + 3, + 21, + 17, + 1, // Skip to: 104527 + /* 34618 */ MCD_OPC_Decode, + 227, + 16, + 23, // Opcode: FMINNMV_VPZ_D + /* 34622 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 34636 + /* 34627 */ MCD_OPC_CheckPredicate, + 3, + 7, + 17, + 1, // Skip to: 104527 + /* 34632 */ MCD_OPC_Decode, + 194, + 16, + 23, // Opcode: FMAXV_VPZ_D + /* 34636 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 34650 + /* 34641 */ MCD_OPC_CheckPredicate, + 3, + 249, + 16, + 1, // Skip to: 104527 + /* 34646 */ MCD_OPC_Decode, + 128, + 17, + 23, // Opcode: FMINV_VPZ_D + /* 34650 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 34671 + /* 34655 */ MCD_OPC_CheckPredicate, + 3, + 235, + 16, + 1, // Skip to: 104527 + /* 34660 */ MCD_OPC_CheckField, + 10, + 3, + 4, + 228, + 16, + 1, // Skip to: 104527 + /* 34667 */ MCD_OPC_Decode, + 191, + 18, + 63, // Opcode: FRECPE_ZZ_D + /* 34671 */ MCD_OPC_FilterValue, + 15, + 16, + 0, + 0, // Skip to: 34692 + /* 34676 */ MCD_OPC_CheckPredicate, + 3, + 214, + 16, + 1, // Skip to: 104527 + /* 34681 */ MCD_OPC_CheckField, + 10, + 3, + 4, + 207, + 16, + 1, // Skip to: 104527 + /* 34688 */ MCD_OPC_Decode, + 188, + 19, + 63, // Opcode: FRSQRTE_ZZ_D + /* 34692 */ MCD_OPC_FilterValue, + 16, + 33, + 0, + 0, // Skip to: 34730 + /* 34697 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 34700 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 34715 + /* 34705 */ MCD_OPC_CheckPredicate, + 3, + 185, + 16, + 1, // Skip to: 104527 + /* 34710 */ MCD_OPC_Decode, + 189, + 13, + 168, + 1, // Opcode: FCMGE_PPzZ0_D + /* 34715 */ MCD_OPC_FilterValue, + 1, + 175, + 16, + 1, // Skip to: 104527 + /* 34720 */ MCD_OPC_CheckPredicate, + 3, + 170, + 16, + 1, // Skip to: 104527 + /* 34725 */ MCD_OPC_Decode, + 211, + 13, + 168, + 1, // Opcode: FCMGT_PPzZ0_D + /* 34730 */ MCD_OPC_FilterValue, + 17, + 33, + 0, + 0, // Skip to: 34768 + /* 34735 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 34738 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 34753 + /* 34743 */ MCD_OPC_CheckPredicate, + 3, + 147, + 16, + 1, // Skip to: 104527 + /* 34748 */ MCD_OPC_Decode, + 254, + 13, + 168, + 1, // Opcode: FCMLT_PPzZ0_D + /* 34753 */ MCD_OPC_FilterValue, + 1, + 137, + 16, + 1, // Skip to: 104527 + /* 34758 */ MCD_OPC_CheckPredicate, + 3, + 132, + 16, + 1, // Skip to: 104527 + /* 34763 */ MCD_OPC_Decode, + 243, + 13, + 168, + 1, // Opcode: FCMLE_PPzZ0_D + /* 34768 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 34790 + /* 34773 */ MCD_OPC_CheckPredicate, + 3, + 117, + 16, + 1, // Skip to: 104527 + /* 34778 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 110, + 16, + 1, // Skip to: 104527 + /* 34785 */ MCD_OPC_Decode, + 167, + 13, + 168, + 1, // Opcode: FCMEQ_PPzZ0_D + /* 34790 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 34812 + /* 34795 */ MCD_OPC_CheckPredicate, + 3, + 95, + 16, + 1, // Skip to: 104527 + /* 34800 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 88, + 16, + 1, // Skip to: 104527 + /* 34807 */ MCD_OPC_Decode, + 137, + 14, + 168, + 1, // Opcode: FCMNE_PPzZ0_D + /* 34812 */ MCD_OPC_FilterValue, + 24, + 78, + 16, + 1, // Skip to: 104527 + /* 34817 */ MCD_OPC_CheckPredicate, + 6, + 73, + 16, + 1, // Skip to: 104527 + /* 34822 */ MCD_OPC_Decode, + 244, + 12, + 22, // Opcode: FADDA_VPZ_D + /* 34826 */ MCD_OPC_FilterValue, + 3, + 64, + 16, + 1, // Skip to: 104527 + /* 34831 */ MCD_OPC_CheckPredicate, + 3, + 59, + 16, + 1, // Skip to: 104527 + /* 34836 */ MCD_OPC_Decode, + 188, + 17, + 25, // Opcode: FMLS_ZPmZZ_D + /* 34840 */ MCD_OPC_FilterValue, + 2, + 103, + 0, + 0, // Skip to: 34948 + /* 34845 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 34848 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 34884 + /* 34853 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 34856 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 34870 + /* 34861 */ MCD_OPC_CheckPredicate, + 3, + 29, + 16, + 1, // Skip to: 104527 + /* 34866 */ MCD_OPC_Decode, + 194, + 13, + 109, // Opcode: FCMGE_PPzZZ_S + /* 34870 */ MCD_OPC_FilterValue, + 1, + 20, + 16, + 1, // Skip to: 104527 + /* 34875 */ MCD_OPC_CheckPredicate, + 3, + 15, + 16, + 1, // Skip to: 104527 + /* 34880 */ MCD_OPC_Decode, + 216, + 13, + 109, // Opcode: FCMGT_PPzZZ_S + /* 34884 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 34898 + /* 34889 */ MCD_OPC_CheckPredicate, + 3, + 1, + 16, + 1, // Skip to: 104527 + /* 34894 */ MCD_OPC_Decode, + 178, + 18, + 25, // Opcode: FNMLA_ZPmZZ_S + /* 34898 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 34934 + /* 34903 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 34906 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 34920 + /* 34911 */ MCD_OPC_CheckPredicate, + 3, + 235, + 15, + 1, // Skip to: 104527 + /* 34916 */ MCD_OPC_Decode, + 192, + 13, + 109, // Opcode: FCMGE_PPzZZ_D + /* 34920 */ MCD_OPC_FilterValue, + 1, + 226, + 15, + 1, // Skip to: 104527 + /* 34925 */ MCD_OPC_CheckPredicate, + 3, + 221, + 15, + 1, // Skip to: 104527 + /* 34930 */ MCD_OPC_Decode, + 214, + 13, + 109, // Opcode: FCMGT_PPzZZ_D + /* 34934 */ MCD_OPC_FilterValue, + 3, + 212, + 15, + 1, // Skip to: 104527 + /* 34939 */ MCD_OPC_CheckPredicate, + 3, + 207, + 15, + 1, // Skip to: 104527 + /* 34944 */ MCD_OPC_Decode, + 176, + 18, + 25, // Opcode: FNMLA_ZPmZZ_D + /* 34948 */ MCD_OPC_FilterValue, + 3, + 103, + 0, + 0, // Skip to: 35056 + /* 34953 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 34956 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 34992 + /* 34961 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 34964 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 34978 + /* 34969 */ MCD_OPC_CheckPredicate, + 3, + 177, + 15, + 1, // Skip to: 104527 + /* 34974 */ MCD_OPC_Decode, + 172, + 13, + 109, // Opcode: FCMEQ_PPzZZ_S + /* 34978 */ MCD_OPC_FilterValue, + 1, + 168, + 15, + 1, // Skip to: 104527 + /* 34983 */ MCD_OPC_CheckPredicate, + 3, + 163, + 15, + 1, // Skip to: 104527 + /* 34988 */ MCD_OPC_Decode, + 142, + 14, + 109, // Opcode: FCMNE_PPzZZ_S + /* 34992 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 35006 + /* 34997 */ MCD_OPC_CheckPredicate, + 3, + 149, + 15, + 1, // Skip to: 104527 + /* 35002 */ MCD_OPC_Decode, + 181, + 18, + 25, // Opcode: FNMLS_ZPmZZ_S + /* 35006 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 35042 + /* 35011 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 35014 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 35028 + /* 35019 */ MCD_OPC_CheckPredicate, + 3, + 127, + 15, + 1, // Skip to: 104527 + /* 35024 */ MCD_OPC_Decode, + 170, + 13, + 109, // Opcode: FCMEQ_PPzZZ_D + /* 35028 */ MCD_OPC_FilterValue, + 1, + 118, + 15, + 1, // Skip to: 104527 + /* 35033 */ MCD_OPC_CheckPredicate, + 3, + 113, + 15, + 1, // Skip to: 104527 + /* 35038 */ MCD_OPC_Decode, + 140, + 14, + 109, // Opcode: FCMNE_PPzZZ_D + /* 35042 */ MCD_OPC_FilterValue, + 3, + 104, + 15, + 1, // Skip to: 104527 + /* 35047 */ MCD_OPC_CheckPredicate, + 3, + 99, + 15, + 1, // Skip to: 104527 + /* 35052 */ MCD_OPC_Decode, + 179, + 18, + 25, // Opcode: FNMLS_ZPmZZ_D + /* 35056 */ MCD_OPC_FilterValue, + 4, + 87, + 3, + 0, // Skip to: 35916 + /* 35061 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 35064 */ MCD_OPC_FilterValue, + 0, + 151, + 1, + 0, // Skip to: 35476 + /* 35069 */ MCD_OPC_ExtractField, + 19, + 2, // Inst{20-19} ... + /* 35072 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 35192 + /* 35077 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 35080 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 35094 + /* 35085 */ MCD_OPC_CheckPredicate, + 3, + 61, + 15, + 1, // Skip to: 104527 + /* 35090 */ MCD_OPC_Decode, + 141, + 13, + 22, // Opcode: FADD_ZPmZ_S + /* 35094 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 35108 + /* 35099 */ MCD_OPC_CheckPredicate, + 3, + 47, + 15, + 1, // Skip to: 104527 + /* 35104 */ MCD_OPC_Decode, + 238, + 19, + 22, // Opcode: FSUB_ZPmZ_S + /* 35108 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 35122 + /* 35113 */ MCD_OPC_CheckPredicate, + 3, + 33, + 15, + 1, // Skip to: 104527 + /* 35118 */ MCD_OPC_Decode, + 139, + 18, + 22, // Opcode: FMUL_ZPmZ_S + /* 35122 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 35136 + /* 35127 */ MCD_OPC_CheckPredicate, + 3, + 19, + 15, + 1, // Skip to: 104527 + /* 35132 */ MCD_OPC_Decode, + 231, + 19, + 22, // Opcode: FSUBR_ZPmZ_S + /* 35136 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 35150 + /* 35141 */ MCD_OPC_CheckPredicate, + 3, + 5, + 15, + 1, // Skip to: 104527 + /* 35146 */ MCD_OPC_Decode, + 176, + 16, + 22, // Opcode: FMAXNM_ZPmZ_S + /* 35150 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 35164 + /* 35155 */ MCD_OPC_CheckPredicate, + 3, + 247, + 14, + 1, // Skip to: 104527 + /* 35160 */ MCD_OPC_Decode, + 238, + 16, + 22, // Opcode: FMINNM_ZPmZ_S + /* 35164 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 35178 + /* 35169 */ MCD_OPC_CheckPredicate, + 3, + 233, + 14, + 1, // Skip to: 104527 + /* 35174 */ MCD_OPC_Decode, + 205, + 16, + 22, // Opcode: FMAX_ZPmZ_S + /* 35178 */ MCD_OPC_FilterValue, + 7, + 224, + 14, + 1, // Skip to: 104527 + /* 35183 */ MCD_OPC_CheckPredicate, + 3, + 219, + 14, + 1, // Skip to: 104527 + /* 35188 */ MCD_OPC_Decode, + 139, + 17, + 22, // Opcode: FMIN_ZPmZ_S + /* 35192 */ MCD_OPC_FilterValue, + 1, + 73, + 0, + 0, // Skip to: 35270 + /* 35197 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 35200 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 35214 + /* 35205 */ MCD_OPC_CheckPredicate, + 3, + 197, + 14, + 1, // Skip to: 104527 + /* 35210 */ MCD_OPC_Decode, + 205, + 12, + 22, // Opcode: FABD_ZPmZ_S + /* 35214 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 35228 + /* 35219 */ MCD_OPC_CheckPredicate, + 3, + 183, + 14, + 1, // Skip to: 104527 + /* 35224 */ MCD_OPC_Decode, + 212, + 19, + 22, // Opcode: FSCALE_ZPmZ_S + /* 35228 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 35242 + /* 35233 */ MCD_OPC_CheckPredicate, + 3, + 169, + 14, + 1, // Skip to: 104527 + /* 35238 */ MCD_OPC_Decode, + 248, + 17, + 22, // Opcode: FMULX_ZPmZ_S + /* 35242 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 35256 + /* 35247 */ MCD_OPC_CheckPredicate, + 3, + 155, + 14, + 1, // Skip to: 104527 + /* 35252 */ MCD_OPC_Decode, + 251, + 15, + 22, // Opcode: FDIVR_ZPmZ_S + /* 35256 */ MCD_OPC_FilterValue, + 5, + 146, + 14, + 1, // Skip to: 104527 + /* 35261 */ MCD_OPC_CheckPredicate, + 3, + 141, + 14, + 1, // Skip to: 104527 + /* 35266 */ MCD_OPC_Decode, + 255, + 15, + 22, // Opcode: FDIV_ZPmZ_S + /* 35270 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 35292 + /* 35275 */ MCD_OPC_CheckPredicate, + 6, + 127, + 14, + 1, // Skip to: 104527 + /* 35280 */ MCD_OPC_CheckField, + 10, + 3, + 0, + 120, + 14, + 1, // Skip to: 104527 + /* 35287 */ MCD_OPC_Decode, + 249, + 19, + 169, + 1, // Opcode: FTMAD_ZZI_S + /* 35292 */ MCD_OPC_FilterValue, + 3, + 110, + 14, + 1, // Skip to: 104527 + /* 35297 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 35300 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 35322 + /* 35305 */ MCD_OPC_CheckPredicate, + 3, + 97, + 14, + 1, // Skip to: 104527 + /* 35310 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 90, + 14, + 1, // Skip to: 104527 + /* 35317 */ MCD_OPC_Decode, + 138, + 13, + 170, + 1, // Opcode: FADD_ZPmI_S + /* 35322 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 35344 + /* 35327 */ MCD_OPC_CheckPredicate, + 3, + 75, + 14, + 1, // Skip to: 104527 + /* 35332 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 68, + 14, + 1, // Skip to: 104527 + /* 35339 */ MCD_OPC_Decode, + 235, + 19, + 170, + 1, // Opcode: FSUB_ZPmI_S + /* 35344 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 35366 + /* 35349 */ MCD_OPC_CheckPredicate, + 3, + 53, + 14, + 1, // Skip to: 104527 + /* 35354 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 46, + 14, + 1, // Skip to: 104527 + /* 35361 */ MCD_OPC_Decode, + 136, + 18, + 170, + 1, // Opcode: FMUL_ZPmI_S + /* 35366 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 35388 + /* 35371 */ MCD_OPC_CheckPredicate, + 3, + 31, + 14, + 1, // Skip to: 104527 + /* 35376 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 24, + 14, + 1, // Skip to: 104527 + /* 35383 */ MCD_OPC_Decode, + 228, + 19, + 170, + 1, // Opcode: FSUBR_ZPmI_S + /* 35388 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 35410 + /* 35393 */ MCD_OPC_CheckPredicate, + 3, + 9, + 14, + 1, // Skip to: 104527 + /* 35398 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 2, + 14, + 1, // Skip to: 104527 + /* 35405 */ MCD_OPC_Decode, + 173, + 16, + 170, + 1, // Opcode: FMAXNM_ZPmI_S + /* 35410 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 35432 + /* 35415 */ MCD_OPC_CheckPredicate, + 3, + 243, + 13, + 1, // Skip to: 104527 + /* 35420 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 236, + 13, + 1, // Skip to: 104527 + /* 35427 */ MCD_OPC_Decode, + 235, + 16, + 170, + 1, // Opcode: FMINNM_ZPmI_S + /* 35432 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 35454 + /* 35437 */ MCD_OPC_CheckPredicate, + 3, + 221, + 13, + 1, // Skip to: 104527 + /* 35442 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 214, + 13, + 1, // Skip to: 104527 + /* 35449 */ MCD_OPC_Decode, + 202, + 16, + 170, + 1, // Opcode: FMAX_ZPmI_S + /* 35454 */ MCD_OPC_FilterValue, + 7, + 204, + 13, + 1, // Skip to: 104527 + /* 35459 */ MCD_OPC_CheckPredicate, + 3, + 199, + 13, + 1, // Skip to: 104527 + /* 35464 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 192, + 13, + 1, // Skip to: 104527 + /* 35471 */ MCD_OPC_Decode, + 136, + 17, + 170, + 1, // Opcode: FMIN_ZPmI_S + /* 35476 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 35490 + /* 35481 */ MCD_OPC_CheckPredicate, + 3, + 177, + 13, + 1, // Skip to: 104527 + /* 35486 */ MCD_OPC_Decode, + 148, + 16, + 25, // Opcode: FMAD_ZPmZZ_S + /* 35490 */ MCD_OPC_FilterValue, + 2, + 151, + 1, + 0, // Skip to: 35902 + /* 35495 */ MCD_OPC_ExtractField, + 19, + 2, // Inst{20-19} ... + /* 35498 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 35618 + /* 35503 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 35506 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 35520 + /* 35511 */ MCD_OPC_CheckPredicate, + 3, + 147, + 13, + 1, // Skip to: 104527 + /* 35516 */ MCD_OPC_Decode, + 139, + 13, + 22, // Opcode: FADD_ZPmZ_D + /* 35520 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 35534 + /* 35525 */ MCD_OPC_CheckPredicate, + 3, + 133, + 13, + 1, // Skip to: 104527 + /* 35530 */ MCD_OPC_Decode, + 236, + 19, + 22, // Opcode: FSUB_ZPmZ_D + /* 35534 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 35548 + /* 35539 */ MCD_OPC_CheckPredicate, + 3, + 119, + 13, + 1, // Skip to: 104527 + /* 35544 */ MCD_OPC_Decode, + 137, + 18, + 22, // Opcode: FMUL_ZPmZ_D + /* 35548 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 35562 + /* 35553 */ MCD_OPC_CheckPredicate, + 3, + 105, + 13, + 1, // Skip to: 104527 + /* 35558 */ MCD_OPC_Decode, + 229, + 19, + 22, // Opcode: FSUBR_ZPmZ_D + /* 35562 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 35576 + /* 35567 */ MCD_OPC_CheckPredicate, + 3, + 91, + 13, + 1, // Skip to: 104527 + /* 35572 */ MCD_OPC_Decode, + 174, + 16, + 22, // Opcode: FMAXNM_ZPmZ_D + /* 35576 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 35590 + /* 35581 */ MCD_OPC_CheckPredicate, + 3, + 77, + 13, + 1, // Skip to: 104527 + /* 35586 */ MCD_OPC_Decode, + 236, + 16, + 22, // Opcode: FMINNM_ZPmZ_D + /* 35590 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 35604 + /* 35595 */ MCD_OPC_CheckPredicate, + 3, + 63, + 13, + 1, // Skip to: 104527 + /* 35600 */ MCD_OPC_Decode, + 203, + 16, + 22, // Opcode: FMAX_ZPmZ_D + /* 35604 */ MCD_OPC_FilterValue, + 7, + 54, + 13, + 1, // Skip to: 104527 + /* 35609 */ MCD_OPC_CheckPredicate, + 3, + 49, + 13, + 1, // Skip to: 104527 + /* 35614 */ MCD_OPC_Decode, + 137, + 17, + 22, // Opcode: FMIN_ZPmZ_D + /* 35618 */ MCD_OPC_FilterValue, + 1, + 73, + 0, + 0, // Skip to: 35696 + /* 35623 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 35626 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 35640 + /* 35631 */ MCD_OPC_CheckPredicate, + 3, + 27, + 13, + 1, // Skip to: 104527 + /* 35636 */ MCD_OPC_Decode, + 203, + 12, + 22, // Opcode: FABD_ZPmZ_D + /* 35640 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 35654 + /* 35645 */ MCD_OPC_CheckPredicate, + 3, + 13, + 13, + 1, // Skip to: 104527 + /* 35650 */ MCD_OPC_Decode, + 210, + 19, + 22, // Opcode: FSCALE_ZPmZ_D + /* 35654 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 35668 + /* 35659 */ MCD_OPC_CheckPredicate, + 3, + 255, + 12, + 1, // Skip to: 104527 + /* 35664 */ MCD_OPC_Decode, + 246, + 17, + 22, // Opcode: FMULX_ZPmZ_D + /* 35668 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 35682 + /* 35673 */ MCD_OPC_CheckPredicate, + 3, + 241, + 12, + 1, // Skip to: 104527 + /* 35678 */ MCD_OPC_Decode, + 249, + 15, + 22, // Opcode: FDIVR_ZPmZ_D + /* 35682 */ MCD_OPC_FilterValue, + 5, + 232, + 12, + 1, // Skip to: 104527 + /* 35687 */ MCD_OPC_CheckPredicate, + 3, + 227, + 12, + 1, // Skip to: 104527 + /* 35692 */ MCD_OPC_Decode, + 253, + 15, + 22, // Opcode: FDIV_ZPmZ_D + /* 35696 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 35718 + /* 35701 */ MCD_OPC_CheckPredicate, + 6, + 213, + 12, + 1, // Skip to: 104527 + /* 35706 */ MCD_OPC_CheckField, + 10, + 3, + 0, + 206, + 12, + 1, // Skip to: 104527 + /* 35713 */ MCD_OPC_Decode, + 247, + 19, + 169, + 1, // Opcode: FTMAD_ZZI_D + /* 35718 */ MCD_OPC_FilterValue, + 3, + 196, + 12, + 1, // Skip to: 104527 + /* 35723 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 35726 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 35748 + /* 35731 */ MCD_OPC_CheckPredicate, + 3, + 183, + 12, + 1, // Skip to: 104527 + /* 35736 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 176, + 12, + 1, // Skip to: 104527 + /* 35743 */ MCD_OPC_Decode, + 136, + 13, + 170, + 1, // Opcode: FADD_ZPmI_D + /* 35748 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 35770 + /* 35753 */ MCD_OPC_CheckPredicate, + 3, + 161, + 12, + 1, // Skip to: 104527 + /* 35758 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 154, + 12, + 1, // Skip to: 104527 + /* 35765 */ MCD_OPC_Decode, + 233, + 19, + 170, + 1, // Opcode: FSUB_ZPmI_D + /* 35770 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 35792 + /* 35775 */ MCD_OPC_CheckPredicate, + 3, + 139, + 12, + 1, // Skip to: 104527 + /* 35780 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 132, + 12, + 1, // Skip to: 104527 + /* 35787 */ MCD_OPC_Decode, + 134, + 18, + 170, + 1, // Opcode: FMUL_ZPmI_D + /* 35792 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 35814 + /* 35797 */ MCD_OPC_CheckPredicate, + 3, + 117, + 12, + 1, // Skip to: 104527 + /* 35802 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 110, + 12, + 1, // Skip to: 104527 + /* 35809 */ MCD_OPC_Decode, + 226, + 19, + 170, + 1, // Opcode: FSUBR_ZPmI_D + /* 35814 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 35836 + /* 35819 */ MCD_OPC_CheckPredicate, + 3, + 95, + 12, + 1, // Skip to: 104527 + /* 35824 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 88, + 12, + 1, // Skip to: 104527 + /* 35831 */ MCD_OPC_Decode, + 171, + 16, + 170, + 1, // Opcode: FMAXNM_ZPmI_D + /* 35836 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 35858 + /* 35841 */ MCD_OPC_CheckPredicate, + 3, + 73, + 12, + 1, // Skip to: 104527 + /* 35846 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 66, + 12, + 1, // Skip to: 104527 + /* 35853 */ MCD_OPC_Decode, + 233, + 16, + 170, + 1, // Opcode: FMINNM_ZPmI_D + /* 35858 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 35880 + /* 35863 */ MCD_OPC_CheckPredicate, + 3, + 51, + 12, + 1, // Skip to: 104527 + /* 35868 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 44, + 12, + 1, // Skip to: 104527 + /* 35875 */ MCD_OPC_Decode, + 200, + 16, + 170, + 1, // Opcode: FMAX_ZPmI_D + /* 35880 */ MCD_OPC_FilterValue, + 7, + 34, + 12, + 1, // Skip to: 104527 + /* 35885 */ MCD_OPC_CheckPredicate, + 3, + 29, + 12, + 1, // Skip to: 104527 + /* 35890 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 22, + 12, + 1, // Skip to: 104527 + /* 35897 */ MCD_OPC_Decode, + 134, + 17, + 170, + 1, // Opcode: FMIN_ZPmI_D + /* 35902 */ MCD_OPC_FilterValue, + 3, + 12, + 12, + 1, // Skip to: 104527 + /* 35907 */ MCD_OPC_CheckPredicate, + 3, + 7, + 12, + 1, // Skip to: 104527 + /* 35912 */ MCD_OPC_Decode, + 146, + 16, + 25, // Opcode: FMAD_ZPmZZ_D + /* 35916 */ MCD_OPC_FilterValue, + 5, + 109, + 2, + 0, // Skip to: 36542 + /* 35921 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 35924 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 36156 + /* 35929 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 35932 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 35946 + /* 35937 */ MCD_OPC_CheckPredicate, + 3, + 233, + 11, + 1, // Skip to: 104527 + /* 35942 */ MCD_OPC_Decode, + 149, + 19, + 24, // Opcode: FRINTN_ZPmZ_S + /* 35946 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 35960 + /* 35951 */ MCD_OPC_CheckPredicate, + 3, + 219, + 11, + 1, // Skip to: 104527 + /* 35956 */ MCD_OPC_Decode, + 160, + 19, + 24, // Opcode: FRINTP_ZPmZ_S + /* 35960 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 35974 + /* 35965 */ MCD_OPC_CheckPredicate, + 3, + 205, + 11, + 1, // Skip to: 104527 + /* 35970 */ MCD_OPC_Decode, + 138, + 19, + 24, // Opcode: FRINTM_ZPmZ_S + /* 35974 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 35988 + /* 35979 */ MCD_OPC_CheckPredicate, + 3, + 191, + 11, + 1, // Skip to: 104527 + /* 35984 */ MCD_OPC_Decode, + 182, + 19, + 24, // Opcode: FRINTZ_ZPmZ_S + /* 35988 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 36002 + /* 35993 */ MCD_OPC_CheckPredicate, + 3, + 177, + 11, + 1, // Skip to: 104527 + /* 35998 */ MCD_OPC_Decode, + 244, + 18, + 24, // Opcode: FRINTA_ZPmZ_S + /* 36002 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 36016 + /* 36007 */ MCD_OPC_CheckPredicate, + 3, + 163, + 11, + 1, // Skip to: 104527 + /* 36012 */ MCD_OPC_Decode, + 171, + 19, + 24, // Opcode: FRINTX_ZPmZ_S + /* 36016 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 36030 + /* 36021 */ MCD_OPC_CheckPredicate, + 3, + 149, + 11, + 1, // Skip to: 104527 + /* 36026 */ MCD_OPC_Decode, + 255, + 18, + 24, // Opcode: FRINTI_ZPmZ_S + /* 36030 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 36044 + /* 36035 */ MCD_OPC_CheckPredicate, + 3, + 135, + 11, + 1, // Skip to: 104527 + /* 36040 */ MCD_OPC_Decode, + 246, + 15, + 24, // Opcode: FCVT_ZPmZ_StoH + /* 36044 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 36058 + /* 36049 */ MCD_OPC_CheckPredicate, + 3, + 121, + 11, + 1, // Skip to: 104527 + /* 36054 */ MCD_OPC_Decode, + 244, + 15, + 24, // Opcode: FCVT_ZPmZ_HtoS + /* 36058 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 36072 + /* 36063 */ MCD_OPC_CheckPredicate, + 14, + 107, + 11, + 1, // Skip to: 104527 + /* 36068 */ MCD_OPC_Decode, + 198, + 8, + 24, // Opcode: BFCVT_ZPmZ + /* 36072 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 36086 + /* 36077 */ MCD_OPC_CheckPredicate, + 3, + 93, + 11, + 1, // Skip to: 104527 + /* 36082 */ MCD_OPC_Decode, + 215, + 18, + 24, // Opcode: FRECPX_ZPmZ_S + /* 36086 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 36100 + /* 36091 */ MCD_OPC_CheckPredicate, + 3, + 79, + 11, + 1, // Skip to: 104527 + /* 36096 */ MCD_OPC_Decode, + 218, + 19, + 24, // Opcode: FSQRT_ZPmZ_S + /* 36100 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 36114 + /* 36105 */ MCD_OPC_CheckPredicate, + 3, + 65, + 11, + 1, // Skip to: 104527 + /* 36110 */ MCD_OPC_Decode, + 217, + 30, + 24, // Opcode: SCVTF_ZPmZ_StoS + /* 36114 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 36128 + /* 36119 */ MCD_OPC_CheckPredicate, + 3, + 51, + 11, + 1, // Skip to: 104527 + /* 36124 */ MCD_OPC_Decode, + 206, + 42, + 24, // Opcode: UCVTF_ZPmZ_StoS + /* 36128 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 36142 + /* 36133 */ MCD_OPC_CheckPredicate, + 3, + 37, + 11, + 1, // Skip to: 104527 + /* 36138 */ MCD_OPC_Decode, + 189, + 15, + 24, // Opcode: FCVTZS_ZPmZ_StoS + /* 36142 */ MCD_OPC_FilterValue, + 29, + 28, + 11, + 1, // Skip to: 104527 + /* 36147 */ MCD_OPC_CheckPredicate, + 3, + 23, + 11, + 1, // Skip to: 104527 + /* 36152 */ MCD_OPC_Decode, + 224, + 15, + 24, // Opcode: FCVTZU_ZPmZ_StoS + /* 36156 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 36170 + /* 36161 */ MCD_OPC_CheckPredicate, + 3, + 9, + 11, + 1, // Skip to: 104527 + /* 36166 */ MCD_OPC_Decode, + 236, + 17, + 25, // Opcode: FMSB_ZPmZZ_S + /* 36170 */ MCD_OPC_FilterValue, + 2, + 97, + 1, + 0, // Skip to: 36528 + /* 36175 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 36178 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 36192 + /* 36183 */ MCD_OPC_CheckPredicate, + 3, + 243, + 10, + 1, // Skip to: 104527 + /* 36188 */ MCD_OPC_Decode, + 147, + 19, + 24, // Opcode: FRINTN_ZPmZ_D + /* 36192 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 36206 + /* 36197 */ MCD_OPC_CheckPredicate, + 3, + 229, + 10, + 1, // Skip to: 104527 + /* 36202 */ MCD_OPC_Decode, + 158, + 19, + 24, // Opcode: FRINTP_ZPmZ_D + /* 36206 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 36220 + /* 36211 */ MCD_OPC_CheckPredicate, + 3, + 215, + 10, + 1, // Skip to: 104527 + /* 36216 */ MCD_OPC_Decode, + 136, + 19, + 24, // Opcode: FRINTM_ZPmZ_D + /* 36220 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 36234 + /* 36225 */ MCD_OPC_CheckPredicate, + 3, + 201, + 10, + 1, // Skip to: 104527 + /* 36230 */ MCD_OPC_Decode, + 180, + 19, + 24, // Opcode: FRINTZ_ZPmZ_D + /* 36234 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 36248 + /* 36239 */ MCD_OPC_CheckPredicate, + 3, + 187, + 10, + 1, // Skip to: 104527 + /* 36244 */ MCD_OPC_Decode, + 242, + 18, + 24, // Opcode: FRINTA_ZPmZ_D + /* 36248 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 36262 + /* 36253 */ MCD_OPC_CheckPredicate, + 3, + 173, + 10, + 1, // Skip to: 104527 + /* 36258 */ MCD_OPC_Decode, + 169, + 19, + 24, // Opcode: FRINTX_ZPmZ_D + /* 36262 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 36276 + /* 36267 */ MCD_OPC_CheckPredicate, + 3, + 159, + 10, + 1, // Skip to: 104527 + /* 36272 */ MCD_OPC_Decode, + 253, + 18, + 24, // Opcode: FRINTI_ZPmZ_D + /* 36276 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 36290 + /* 36281 */ MCD_OPC_CheckPredicate, + 3, + 145, + 10, + 1, // Skip to: 104527 + /* 36286 */ MCD_OPC_Decode, + 241, + 15, + 24, // Opcode: FCVT_ZPmZ_DtoH + /* 36290 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 36304 + /* 36295 */ MCD_OPC_CheckPredicate, + 3, + 131, + 10, + 1, // Skip to: 104527 + /* 36300 */ MCD_OPC_Decode, + 243, + 15, + 24, // Opcode: FCVT_ZPmZ_HtoD + /* 36304 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 36318 + /* 36309 */ MCD_OPC_CheckPredicate, + 3, + 117, + 10, + 1, // Skip to: 104527 + /* 36314 */ MCD_OPC_Decode, + 242, + 15, + 24, // Opcode: FCVT_ZPmZ_DtoS + /* 36318 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 36332 + /* 36323 */ MCD_OPC_CheckPredicate, + 3, + 103, + 10, + 1, // Skip to: 104527 + /* 36328 */ MCD_OPC_Decode, + 245, + 15, + 24, // Opcode: FCVT_ZPmZ_StoD + /* 36332 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 36346 + /* 36337 */ MCD_OPC_CheckPredicate, + 3, + 89, + 10, + 1, // Skip to: 104527 + /* 36342 */ MCD_OPC_Decode, + 213, + 18, + 24, // Opcode: FRECPX_ZPmZ_D + /* 36346 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 36360 + /* 36351 */ MCD_OPC_CheckPredicate, + 3, + 75, + 10, + 1, // Skip to: 104527 + /* 36356 */ MCD_OPC_Decode, + 216, + 19, + 24, // Opcode: FSQRT_ZPmZ_D + /* 36360 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 36374 + /* 36365 */ MCD_OPC_CheckPredicate, + 3, + 61, + 10, + 1, // Skip to: 104527 + /* 36370 */ MCD_OPC_Decode, + 215, + 30, + 24, // Opcode: SCVTF_ZPmZ_StoD + /* 36374 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 36388 + /* 36379 */ MCD_OPC_CheckPredicate, + 3, + 47, + 10, + 1, // Skip to: 104527 + /* 36384 */ MCD_OPC_Decode, + 204, + 42, + 24, // Opcode: UCVTF_ZPmZ_StoD + /* 36388 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 36402 + /* 36393 */ MCD_OPC_CheckPredicate, + 3, + 33, + 10, + 1, // Skip to: 104527 + /* 36398 */ MCD_OPC_Decode, + 213, + 30, + 24, // Opcode: SCVTF_ZPmZ_DtoS + /* 36402 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 36416 + /* 36407 */ MCD_OPC_CheckPredicate, + 3, + 19, + 10, + 1, // Skip to: 104527 + /* 36412 */ MCD_OPC_Decode, + 202, + 42, + 24, // Opcode: UCVTF_ZPmZ_DtoS + /* 36416 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 36430 + /* 36421 */ MCD_OPC_CheckPredicate, + 3, + 5, + 10, + 1, // Skip to: 104527 + /* 36426 */ MCD_OPC_Decode, + 211, + 30, + 24, // Opcode: SCVTF_ZPmZ_DtoD + /* 36430 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 36444 + /* 36435 */ MCD_OPC_CheckPredicate, + 3, + 247, + 9, + 1, // Skip to: 104527 + /* 36440 */ MCD_OPC_Decode, + 200, + 42, + 24, // Opcode: UCVTF_ZPmZ_DtoD + /* 36444 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 36458 + /* 36449 */ MCD_OPC_CheckPredicate, + 3, + 233, + 9, + 1, // Skip to: 104527 + /* 36454 */ MCD_OPC_Decode, + 184, + 15, + 24, // Opcode: FCVTZS_ZPmZ_DtoS + /* 36458 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 36472 + /* 36463 */ MCD_OPC_CheckPredicate, + 3, + 219, + 9, + 1, // Skip to: 104527 + /* 36468 */ MCD_OPC_Decode, + 219, + 15, + 24, // Opcode: FCVTZU_ZPmZ_DtoS + /* 36472 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 36486 + /* 36477 */ MCD_OPC_CheckPredicate, + 3, + 205, + 9, + 1, // Skip to: 104527 + /* 36482 */ MCD_OPC_Decode, + 188, + 15, + 24, // Opcode: FCVTZS_ZPmZ_StoD + /* 36486 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 36500 + /* 36491 */ MCD_OPC_CheckPredicate, + 3, + 191, + 9, + 1, // Skip to: 104527 + /* 36496 */ MCD_OPC_Decode, + 223, + 15, + 24, // Opcode: FCVTZU_ZPmZ_StoD + /* 36500 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 36514 + /* 36505 */ MCD_OPC_CheckPredicate, + 3, + 177, + 9, + 1, // Skip to: 104527 + /* 36510 */ MCD_OPC_Decode, + 183, + 15, + 24, // Opcode: FCVTZS_ZPmZ_DtoD + /* 36514 */ MCD_OPC_FilterValue, + 31, + 168, + 9, + 1, // Skip to: 104527 + /* 36519 */ MCD_OPC_CheckPredicate, + 3, + 163, + 9, + 1, // Skip to: 104527 + /* 36524 */ MCD_OPC_Decode, + 218, + 15, + 24, // Opcode: FCVTZU_ZPmZ_DtoD + /* 36528 */ MCD_OPC_FilterValue, + 3, + 154, + 9, + 1, // Skip to: 104527 + /* 36533 */ MCD_OPC_CheckPredicate, + 3, + 149, + 9, + 1, // Skip to: 104527 + /* 36538 */ MCD_OPC_Decode, + 234, + 17, + 25, // Opcode: FMSB_ZPmZZ_D + /* 36542 */ MCD_OPC_FilterValue, + 6, + 103, + 0, + 0, // Skip to: 36650 + /* 36547 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 36550 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 36586 + /* 36555 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 36558 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 36572 + /* 36563 */ MCD_OPC_CheckPredicate, + 3, + 119, + 9, + 1, // Skip to: 104527 + /* 36568 */ MCD_OPC_Decode, + 157, + 14, + 109, // Opcode: FCMUO_PPzZZ_S + /* 36572 */ MCD_OPC_FilterValue, + 1, + 110, + 9, + 1, // Skip to: 104527 + /* 36577 */ MCD_OPC_CheckPredicate, + 3, + 105, + 9, + 1, // Skip to: 104527 + /* 36582 */ MCD_OPC_Decode, + 227, + 12, + 109, // Opcode: FACGE_PPzZZ_S + /* 36586 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 36600 + /* 36591 */ MCD_OPC_CheckPredicate, + 3, + 91, + 9, + 1, // Skip to: 104527 + /* 36596 */ MCD_OPC_Decode, + 175, + 18, + 25, // Opcode: FNMAD_ZPmZZ_S + /* 36600 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 36636 + /* 36605 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 36608 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 36622 + /* 36613 */ MCD_OPC_CheckPredicate, + 3, + 69, + 9, + 1, // Skip to: 104527 + /* 36618 */ MCD_OPC_Decode, + 155, + 14, + 109, // Opcode: FCMUO_PPzZZ_D + /* 36622 */ MCD_OPC_FilterValue, + 1, + 60, + 9, + 1, // Skip to: 104527 + /* 36627 */ MCD_OPC_CheckPredicate, + 3, + 55, + 9, + 1, // Skip to: 104527 + /* 36632 */ MCD_OPC_Decode, + 225, + 12, + 109, // Opcode: FACGE_PPzZZ_D + /* 36636 */ MCD_OPC_FilterValue, + 3, + 46, + 9, + 1, // Skip to: 104527 + /* 36641 */ MCD_OPC_CheckPredicate, + 3, + 41, + 9, + 1, // Skip to: 104527 + /* 36646 */ MCD_OPC_Decode, + 173, + 18, + 25, // Opcode: FNMAD_ZPmZZ_D + /* 36650 */ MCD_OPC_FilterValue, + 7, + 32, + 9, + 1, // Skip to: 104527 + /* 36655 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 36658 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 36679 + /* 36663 */ MCD_OPC_CheckPredicate, + 3, + 19, + 9, + 1, // Skip to: 104527 + /* 36668 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 12, + 9, + 1, // Skip to: 104527 + /* 36675 */ MCD_OPC_Decode, + 238, + 12, + 109, // Opcode: FACGT_PPzZZ_S + /* 36679 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 36693 + /* 36684 */ MCD_OPC_CheckPredicate, + 3, + 254, + 8, + 1, // Skip to: 104527 + /* 36689 */ MCD_OPC_Decode, + 184, + 18, + 25, // Opcode: FNMSB_ZPmZZ_S + /* 36693 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 36714 + /* 36698 */ MCD_OPC_CheckPredicate, + 3, + 240, + 8, + 1, // Skip to: 104527 + /* 36703 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 233, + 8, + 1, // Skip to: 104527 + /* 36710 */ MCD_OPC_Decode, + 236, + 12, + 109, // Opcode: FACGT_PPzZZ_D + /* 36714 */ MCD_OPC_FilterValue, + 3, + 224, + 8, + 1, // Skip to: 104527 + /* 36719 */ MCD_OPC_CheckPredicate, + 3, + 219, + 8, + 1, // Skip to: 104527 + /* 36724 */ MCD_OPC_Decode, + 182, + 18, + 25, // Opcode: FNMSB_ZPmZZ_D + /* 36728 */ MCD_OPC_FilterValue, + 4, + 214, + 6, + 0, // Skip to: 38483 + /* 36733 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 36736 */ MCD_OPC_FilterValue, + 0, + 213, + 0, + 0, // Skip to: 36954 + /* 36741 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 36744 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 36789 + /* 36749 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 36752 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 36767 + /* 36757 */ MCD_OPC_CheckPredicate, + 6, + 181, + 8, + 1, // Skip to: 104527 + /* 36762 */ MCD_OPC_Decode, + 160, + 20, + 171, + 1, // Opcode: GLD1SB_S_UXTW_REAL + /* 36767 */ MCD_OPC_FilterValue, + 1, + 171, + 8, + 1, // Skip to: 104527 + /* 36772 */ MCD_OPC_CheckPredicate, + 6, + 166, + 8, + 1, // Skip to: 104527 + /* 36777 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 159, + 8, + 1, // Skip to: 104527 + /* 36784 */ MCD_OPC_Decode, + 210, + 28, + 172, + 1, // Opcode: PRFB_S_UXTW_SCALED + /* 36789 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 36834 + /* 36794 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 36797 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 36812 + /* 36802 */ MCD_OPC_CheckPredicate, + 6, + 136, + 8, + 1, // Skip to: 104527 + /* 36807 */ MCD_OPC_Decode, + 159, + 20, + 171, + 1, // Opcode: GLD1SB_S_SXTW_REAL + /* 36812 */ MCD_OPC_FilterValue, + 1, + 126, + 8, + 1, // Skip to: 104527 + /* 36817 */ MCD_OPC_CheckPredicate, + 6, + 121, + 8, + 1, // Skip to: 104527 + /* 36822 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 114, + 8, + 1, // Skip to: 104527 + /* 36829 */ MCD_OPC_Decode, + 209, + 28, + 172, + 1, // Opcode: PRFB_S_SXTW_SCALED + /* 36834 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 36872 + /* 36839 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 36842 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 36857 + /* 36847 */ MCD_OPC_CheckPredicate, + 6, + 91, + 8, + 1, // Skip to: 104527 + /* 36852 */ MCD_OPC_Decode, + 171, + 20, + 171, + 1, // Opcode: GLD1SH_S_UXTW_REAL + /* 36857 */ MCD_OPC_FilterValue, + 1, + 81, + 8, + 1, // Skip to: 104527 + /* 36862 */ MCD_OPC_CheckPredicate, + 6, + 76, + 8, + 1, // Skip to: 104527 + /* 36867 */ MCD_OPC_Decode, + 172, + 20, + 171, + 1, // Opcode: GLD1SH_S_UXTW_SCALED_REAL + /* 36872 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 36910 + /* 36877 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 36880 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 36895 + /* 36885 */ MCD_OPC_CheckPredicate, + 6, + 53, + 8, + 1, // Skip to: 104527 + /* 36890 */ MCD_OPC_Decode, + 169, + 20, + 171, + 1, // Opcode: GLD1SH_S_SXTW_REAL + /* 36895 */ MCD_OPC_FilterValue, + 1, + 43, + 8, + 1, // Skip to: 104527 + /* 36900 */ MCD_OPC_CheckPredicate, + 6, + 38, + 8, + 1, // Skip to: 104527 + /* 36905 */ MCD_OPC_Decode, + 170, + 20, + 171, + 1, // Opcode: GLD1SH_S_SXTW_SCALED_REAL + /* 36910 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 36932 + /* 36915 */ MCD_OPC_CheckPredicate, + 3, + 23, + 8, + 1, // Skip to: 104527 + /* 36920 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 16, + 8, + 1, // Skip to: 104527 + /* 36927 */ MCD_OPC_Decode, + 230, + 25, + 173, + 1, // Opcode: LDR_PXI + /* 36932 */ MCD_OPC_FilterValue, + 7, + 6, + 8, + 1, // Skip to: 104527 + /* 36937 */ MCD_OPC_CheckPredicate, + 3, + 1, + 8, + 1, // Skip to: 104527 + /* 36942 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 250, + 7, + 1, // Skip to: 104527 + /* 36949 */ MCD_OPC_Decode, + 206, + 28, + 174, + 1, // Opcode: PRFB_PRI + /* 36954 */ MCD_OPC_FilterValue, + 1, + 191, + 0, + 0, // Skip to: 37150 + /* 36959 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 36962 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 37007 + /* 36967 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 36970 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 36985 + /* 36975 */ MCD_OPC_CheckPredicate, + 6, + 219, + 7, + 1, // Skip to: 104527 + /* 36980 */ MCD_OPC_Decode, + 224, + 20, + 171, + 1, // Opcode: GLDFF1SB_S_UXTW_REAL + /* 36985 */ MCD_OPC_FilterValue, + 1, + 209, + 7, + 1, // Skip to: 104527 + /* 36990 */ MCD_OPC_CheckPredicate, + 6, + 204, + 7, + 1, // Skip to: 104527 + /* 36995 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 197, + 7, + 1, // Skip to: 104527 + /* 37002 */ MCD_OPC_Decode, + 228, + 28, + 172, + 1, // Opcode: PRFH_S_UXTW_SCALED + /* 37007 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 37052 + /* 37012 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37015 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37030 + /* 37020 */ MCD_OPC_CheckPredicate, + 6, + 174, + 7, + 1, // Skip to: 104527 + /* 37025 */ MCD_OPC_Decode, + 223, + 20, + 171, + 1, // Opcode: GLDFF1SB_S_SXTW_REAL + /* 37030 */ MCD_OPC_FilterValue, + 1, + 164, + 7, + 1, // Skip to: 104527 + /* 37035 */ MCD_OPC_CheckPredicate, + 6, + 159, + 7, + 1, // Skip to: 104527 + /* 37040 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 152, + 7, + 1, // Skip to: 104527 + /* 37047 */ MCD_OPC_Decode, + 227, + 28, + 172, + 1, // Opcode: PRFH_S_SXTW_SCALED + /* 37052 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 37090 + /* 37057 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37060 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37075 + /* 37065 */ MCD_OPC_CheckPredicate, + 6, + 129, + 7, + 1, // Skip to: 104527 + /* 37070 */ MCD_OPC_Decode, + 235, + 20, + 171, + 1, // Opcode: GLDFF1SH_S_UXTW_REAL + /* 37075 */ MCD_OPC_FilterValue, + 1, + 119, + 7, + 1, // Skip to: 104527 + /* 37080 */ MCD_OPC_CheckPredicate, + 6, + 114, + 7, + 1, // Skip to: 104527 + /* 37085 */ MCD_OPC_Decode, + 236, + 20, + 171, + 1, // Opcode: GLDFF1SH_S_UXTW_SCALED_REAL + /* 37090 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 37128 + /* 37095 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37098 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37113 + /* 37103 */ MCD_OPC_CheckPredicate, + 6, + 91, + 7, + 1, // Skip to: 104527 + /* 37108 */ MCD_OPC_Decode, + 233, + 20, + 171, + 1, // Opcode: GLDFF1SH_S_SXTW_REAL + /* 37113 */ MCD_OPC_FilterValue, + 1, + 81, + 7, + 1, // Skip to: 104527 + /* 37118 */ MCD_OPC_CheckPredicate, + 6, + 76, + 7, + 1, // Skip to: 104527 + /* 37123 */ MCD_OPC_Decode, + 234, + 20, + 171, + 1, // Opcode: GLDFF1SH_S_SXTW_SCALED_REAL + /* 37128 */ MCD_OPC_FilterValue, + 7, + 66, + 7, + 1, // Skip to: 104527 + /* 37133 */ MCD_OPC_CheckPredicate, + 3, + 61, + 7, + 1, // Skip to: 104527 + /* 37138 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 54, + 7, + 1, // Skip to: 104527 + /* 37145 */ MCD_OPC_Decode, + 224, + 28, + 174, + 1, // Opcode: PRFH_PRI + /* 37150 */ MCD_OPC_FilterValue, + 2, + 26, + 1, + 0, // Skip to: 37437 + /* 37155 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 37158 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 37203 + /* 37163 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37166 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37181 + /* 37171 */ MCD_OPC_CheckPredicate, + 6, + 23, + 7, + 1, // Skip to: 104527 + /* 37176 */ MCD_OPC_Decode, + 134, + 20, + 171, + 1, // Opcode: GLD1B_S_UXTW_REAL + /* 37181 */ MCD_OPC_FilterValue, + 1, + 13, + 7, + 1, // Skip to: 104527 + /* 37186 */ MCD_OPC_CheckPredicate, + 6, + 8, + 7, + 1, // Skip to: 104527 + /* 37191 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 1, + 7, + 1, // Skip to: 104527 + /* 37198 */ MCD_OPC_Decode, + 242, + 28, + 172, + 1, // Opcode: PRFW_S_UXTW_SCALED + /* 37203 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 37248 + /* 37208 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37211 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37226 + /* 37216 */ MCD_OPC_CheckPredicate, + 6, + 234, + 6, + 1, // Skip to: 104527 + /* 37221 */ MCD_OPC_Decode, + 133, + 20, + 171, + 1, // Opcode: GLD1B_S_SXTW_REAL + /* 37226 */ MCD_OPC_FilterValue, + 1, + 224, + 6, + 1, // Skip to: 104527 + /* 37231 */ MCD_OPC_CheckPredicate, + 6, + 219, + 6, + 1, // Skip to: 104527 + /* 37236 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 212, + 6, + 1, // Skip to: 104527 + /* 37243 */ MCD_OPC_Decode, + 241, + 28, + 172, + 1, // Opcode: PRFW_S_SXTW_SCALED + /* 37248 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 37286 + /* 37253 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37256 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37271 + /* 37261 */ MCD_OPC_CheckPredicate, + 6, + 189, + 6, + 1, // Skip to: 104527 + /* 37266 */ MCD_OPC_Decode, + 152, + 20, + 171, + 1, // Opcode: GLD1H_S_UXTW_REAL + /* 37271 */ MCD_OPC_FilterValue, + 1, + 179, + 6, + 1, // Skip to: 104527 + /* 37276 */ MCD_OPC_CheckPredicate, + 6, + 174, + 6, + 1, // Skip to: 104527 + /* 37281 */ MCD_OPC_Decode, + 153, + 20, + 171, + 1, // Opcode: GLD1H_S_UXTW_SCALED_REAL + /* 37286 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 37324 + /* 37291 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37294 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37309 + /* 37299 */ MCD_OPC_CheckPredicate, + 6, + 151, + 6, + 1, // Skip to: 104527 + /* 37304 */ MCD_OPC_Decode, + 150, + 20, + 171, + 1, // Opcode: GLD1H_S_SXTW_REAL + /* 37309 */ MCD_OPC_FilterValue, + 1, + 141, + 6, + 1, // Skip to: 104527 + /* 37314 */ MCD_OPC_CheckPredicate, + 6, + 136, + 6, + 1, // Skip to: 104527 + /* 37319 */ MCD_OPC_Decode, + 151, + 20, + 171, + 1, // Opcode: GLD1H_S_SXTW_SCALED_REAL + /* 37324 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 37362 + /* 37329 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37332 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37347 + /* 37337 */ MCD_OPC_CheckPredicate, + 6, + 113, + 6, + 1, // Skip to: 104527 + /* 37342 */ MCD_OPC_Decode, + 190, + 20, + 171, + 1, // Opcode: GLD1W_UXTW_REAL + /* 37347 */ MCD_OPC_FilterValue, + 1, + 103, + 6, + 1, // Skip to: 104527 + /* 37352 */ MCD_OPC_CheckPredicate, + 6, + 98, + 6, + 1, // Skip to: 104527 + /* 37357 */ MCD_OPC_Decode, + 191, + 20, + 171, + 1, // Opcode: GLD1W_UXTW_SCALED_REAL + /* 37362 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 37400 + /* 37367 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37370 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37385 + /* 37375 */ MCD_OPC_CheckPredicate, + 6, + 75, + 6, + 1, // Skip to: 104527 + /* 37380 */ MCD_OPC_Decode, + 188, + 20, + 171, + 1, // Opcode: GLD1W_SXTW_REAL + /* 37385 */ MCD_OPC_FilterValue, + 1, + 65, + 6, + 1, // Skip to: 104527 + /* 37390 */ MCD_OPC_CheckPredicate, + 6, + 60, + 6, + 1, // Skip to: 104527 + /* 37395 */ MCD_OPC_Decode, + 189, + 20, + 171, + 1, // Opcode: GLD1W_SXTW_SCALED_REAL + /* 37400 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 37415 + /* 37405 */ MCD_OPC_CheckPredicate, + 3, + 45, + 6, + 1, // Skip to: 104527 + /* 37410 */ MCD_OPC_Decode, + 232, + 25, + 175, + 1, // Opcode: LDR_ZXI + /* 37415 */ MCD_OPC_FilterValue, + 7, + 35, + 6, + 1, // Skip to: 104527 + /* 37420 */ MCD_OPC_CheckPredicate, + 3, + 30, + 6, + 1, // Skip to: 104527 + /* 37425 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 23, + 6, + 1, // Skip to: 104527 + /* 37432 */ MCD_OPC_Decode, + 239, + 28, + 174, + 1, // Opcode: PRFW_PRI + /* 37437 */ MCD_OPC_FilterValue, + 3, + 11, + 1, + 0, // Skip to: 37709 + /* 37442 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 37445 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 37490 + /* 37450 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37453 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37468 + /* 37458 */ MCD_OPC_CheckPredicate, + 6, + 248, + 5, + 1, // Skip to: 104527 + /* 37463 */ MCD_OPC_Decode, + 198, + 20, + 171, + 1, // Opcode: GLDFF1B_S_UXTW_REAL + /* 37468 */ MCD_OPC_FilterValue, + 1, + 238, + 5, + 1, // Skip to: 104527 + /* 37473 */ MCD_OPC_CheckPredicate, + 6, + 233, + 5, + 1, // Skip to: 104527 + /* 37478 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 226, + 5, + 1, // Skip to: 104527 + /* 37485 */ MCD_OPC_Decode, + 219, + 28, + 172, + 1, // Opcode: PRFD_S_UXTW_SCALED + /* 37490 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 37535 + /* 37495 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37498 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37513 + /* 37503 */ MCD_OPC_CheckPredicate, + 6, + 203, + 5, + 1, // Skip to: 104527 + /* 37508 */ MCD_OPC_Decode, + 197, + 20, + 171, + 1, // Opcode: GLDFF1B_S_SXTW_REAL + /* 37513 */ MCD_OPC_FilterValue, + 1, + 193, + 5, + 1, // Skip to: 104527 + /* 37518 */ MCD_OPC_CheckPredicate, + 6, + 188, + 5, + 1, // Skip to: 104527 + /* 37523 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 5, + 1, // Skip to: 104527 + /* 37530 */ MCD_OPC_Decode, + 218, + 28, + 172, + 1, // Opcode: PRFD_S_SXTW_SCALED + /* 37535 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 37573 + /* 37540 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37543 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37558 + /* 37548 */ MCD_OPC_CheckPredicate, + 6, + 158, + 5, + 1, // Skip to: 104527 + /* 37553 */ MCD_OPC_Decode, + 216, + 20, + 171, + 1, // Opcode: GLDFF1H_S_UXTW_REAL + /* 37558 */ MCD_OPC_FilterValue, + 1, + 148, + 5, + 1, // Skip to: 104527 + /* 37563 */ MCD_OPC_CheckPredicate, + 6, + 143, + 5, + 1, // Skip to: 104527 + /* 37568 */ MCD_OPC_Decode, + 217, + 20, + 171, + 1, // Opcode: GLDFF1H_S_UXTW_SCALED_REAL + /* 37573 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 37611 + /* 37578 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37581 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37596 + /* 37586 */ MCD_OPC_CheckPredicate, + 6, + 120, + 5, + 1, // Skip to: 104527 + /* 37591 */ MCD_OPC_Decode, + 214, + 20, + 171, + 1, // Opcode: GLDFF1H_S_SXTW_REAL + /* 37596 */ MCD_OPC_FilterValue, + 1, + 110, + 5, + 1, // Skip to: 104527 + /* 37601 */ MCD_OPC_CheckPredicate, + 6, + 105, + 5, + 1, // Skip to: 104527 + /* 37606 */ MCD_OPC_Decode, + 215, + 20, + 171, + 1, // Opcode: GLDFF1H_S_SXTW_SCALED_REAL + /* 37611 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 37649 + /* 37616 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37619 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37634 + /* 37624 */ MCD_OPC_CheckPredicate, + 6, + 82, + 5, + 1, // Skip to: 104527 + /* 37629 */ MCD_OPC_Decode, + 254, + 20, + 171, + 1, // Opcode: GLDFF1W_UXTW_REAL + /* 37634 */ MCD_OPC_FilterValue, + 1, + 72, + 5, + 1, // Skip to: 104527 + /* 37639 */ MCD_OPC_CheckPredicate, + 6, + 67, + 5, + 1, // Skip to: 104527 + /* 37644 */ MCD_OPC_Decode, + 255, + 20, + 171, + 1, // Opcode: GLDFF1W_UXTW_SCALED_REAL + /* 37649 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 37687 + /* 37654 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37657 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37672 + /* 37662 */ MCD_OPC_CheckPredicate, + 6, + 44, + 5, + 1, // Skip to: 104527 + /* 37667 */ MCD_OPC_Decode, + 252, + 20, + 171, + 1, // Opcode: GLDFF1W_SXTW_REAL + /* 37672 */ MCD_OPC_FilterValue, + 1, + 34, + 5, + 1, // Skip to: 104527 + /* 37677 */ MCD_OPC_CheckPredicate, + 6, + 29, + 5, + 1, // Skip to: 104527 + /* 37682 */ MCD_OPC_Decode, + 253, + 20, + 171, + 1, // Opcode: GLDFF1W_SXTW_SCALED_REAL + /* 37687 */ MCD_OPC_FilterValue, + 7, + 19, + 5, + 1, // Skip to: 104527 + /* 37692 */ MCD_OPC_CheckPredicate, + 3, + 14, + 5, + 1, // Skip to: 104527 + /* 37697 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 7, + 5, + 1, // Skip to: 104527 + /* 37704 */ MCD_OPC_Decode, + 215, + 28, + 174, + 1, // Opcode: PRFD_PRI + /* 37709 */ MCD_OPC_FilterValue, + 4, + 139, + 0, + 0, // Skip to: 37853 + /* 37714 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 37717 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 37755 + /* 37722 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37725 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37740 + /* 37730 */ MCD_OPC_CheckPredicate, + 10, + 232, + 4, + 1, // Skip to: 104527 + /* 37735 */ MCD_OPC_Decode, + 252, + 24, + 176, + 1, // Opcode: LDNT1SB_ZZR_S_REAL + /* 37740 */ MCD_OPC_FilterValue, + 1, + 222, + 4, + 1, // Skip to: 104527 + /* 37745 */ MCD_OPC_CheckPredicate, + 6, + 217, + 4, + 1, // Skip to: 104527 + /* 37750 */ MCD_OPC_Decode, + 158, + 20, + 177, + 1, // Opcode: GLD1SB_S_IMM_REAL + /* 37755 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 37770 + /* 37760 */ MCD_OPC_CheckPredicate, + 3, + 202, + 4, + 1, // Skip to: 104527 + /* 37765 */ MCD_OPC_Decode, + 131, + 22, + 178, + 1, // Opcode: LD1RB_IMM + /* 37770 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 37808 + /* 37775 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37778 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37793 + /* 37783 */ MCD_OPC_CheckPredicate, + 10, + 179, + 4, + 1, // Skip to: 104527 + /* 37788 */ MCD_OPC_Decode, + 254, + 24, + 176, + 1, // Opcode: LDNT1SH_ZZR_S_REAL + /* 37793 */ MCD_OPC_FilterValue, + 1, + 169, + 4, + 1, // Skip to: 104527 + /* 37798 */ MCD_OPC_CheckPredicate, + 6, + 164, + 4, + 1, // Skip to: 104527 + /* 37803 */ MCD_OPC_Decode, + 168, + 20, + 177, + 1, // Opcode: GLD1SH_S_IMM_REAL + /* 37808 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 37823 + /* 37813 */ MCD_OPC_CheckPredicate, + 3, + 149, + 4, + 1, // Skip to: 104527 + /* 37818 */ MCD_OPC_Decode, + 158, + 22, + 178, + 1, // Opcode: LD1RSW_IMM + /* 37823 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 37838 + /* 37828 */ MCD_OPC_CheckPredicate, + 3, + 134, + 4, + 1, // Skip to: 104527 + /* 37833 */ MCD_OPC_Decode, + 156, + 22, + 178, + 1, // Opcode: LD1RSH_D_IMM + /* 37838 */ MCD_OPC_FilterValue, + 7, + 124, + 4, + 1, // Skip to: 104527 + /* 37843 */ MCD_OPC_CheckPredicate, + 3, + 119, + 4, + 1, // Skip to: 104527 + /* 37848 */ MCD_OPC_Decode, + 153, + 22, + 178, + 1, // Opcode: LD1RSB_D_IMM + /* 37853 */ MCD_OPC_FilterValue, + 5, + 161, + 0, + 0, // Skip to: 38019 + /* 37858 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 37861 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 37899 + /* 37866 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37869 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37884 + /* 37874 */ MCD_OPC_CheckPredicate, + 10, + 88, + 4, + 1, // Skip to: 104527 + /* 37879 */ MCD_OPC_Decode, + 243, + 24, + 176, + 1, // Opcode: LDNT1B_ZZR_S_REAL + /* 37884 */ MCD_OPC_FilterValue, + 1, + 78, + 4, + 1, // Skip to: 104527 + /* 37889 */ MCD_OPC_CheckPredicate, + 6, + 73, + 4, + 1, // Skip to: 104527 + /* 37894 */ MCD_OPC_Decode, + 222, + 20, + 177, + 1, // Opcode: GLDFF1SB_S_IMM_REAL + /* 37899 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 37914 + /* 37904 */ MCD_OPC_CheckPredicate, + 3, + 58, + 4, + 1, // Skip to: 104527 + /* 37909 */ MCD_OPC_Decode, + 130, + 22, + 178, + 1, // Opcode: LD1RB_H_IMM + /* 37914 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 37952 + /* 37919 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 37922 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 37937 + /* 37927 */ MCD_OPC_CheckPredicate, + 10, + 35, + 4, + 1, // Skip to: 104527 + /* 37932 */ MCD_OPC_Decode, + 250, + 24, + 176, + 1, // Opcode: LDNT1H_ZZR_S_REAL + /* 37937 */ MCD_OPC_FilterValue, + 1, + 25, + 4, + 1, // Skip to: 104527 + /* 37942 */ MCD_OPC_CheckPredicate, + 6, + 20, + 4, + 1, // Skip to: 104527 + /* 37947 */ MCD_OPC_Decode, + 232, + 20, + 177, + 1, // Opcode: GLDFF1SH_S_IMM_REAL + /* 37952 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 37967 + /* 37957 */ MCD_OPC_CheckPredicate, + 3, + 5, + 4, + 1, // Skip to: 104527 + /* 37962 */ MCD_OPC_Decode, + 135, + 22, + 178, + 1, // Opcode: LD1RH_IMM + /* 37967 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 37989 + /* 37972 */ MCD_OPC_CheckPredicate, + 10, + 246, + 3, + 1, // Skip to: 104527 + /* 37977 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 239, + 3, + 1, // Skip to: 104527 + /* 37984 */ MCD_OPC_Decode, + 131, + 25, + 176, + 1, // Opcode: LDNT1W_ZZR_S_REAL + /* 37989 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 38004 + /* 37994 */ MCD_OPC_CheckPredicate, + 3, + 224, + 3, + 1, // Skip to: 104527 + /* 37999 */ MCD_OPC_Decode, + 157, + 22, + 178, + 1, // Opcode: LD1RSH_S_IMM + /* 38004 */ MCD_OPC_FilterValue, + 7, + 214, + 3, + 1, // Skip to: 104527 + /* 38009 */ MCD_OPC_CheckPredicate, + 3, + 209, + 3, + 1, // Skip to: 104527 + /* 38014 */ MCD_OPC_Decode, + 155, + 22, + 178, + 1, // Opcode: LD1RSB_S_IMM + /* 38019 */ MCD_OPC_FilterValue, + 6, + 227, + 0, + 0, // Skip to: 38251 + /* 38024 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 38027 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 38072 + /* 38032 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 38035 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 38057 + /* 38040 */ MCD_OPC_CheckPredicate, + 3, + 178, + 3, + 1, // Skip to: 104527 + /* 38045 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 171, + 3, + 1, // Skip to: 104527 + /* 38052 */ MCD_OPC_Decode, + 207, + 28, + 179, + 1, // Opcode: PRFB_PRR + /* 38057 */ MCD_OPC_FilterValue, + 1, + 161, + 3, + 1, // Skip to: 104527 + /* 38062 */ MCD_OPC_CheckPredicate, + 6, + 156, + 3, + 1, // Skip to: 104527 + /* 38067 */ MCD_OPC_Decode, + 132, + 20, + 177, + 1, // Opcode: GLD1B_S_IMM_REAL + /* 38072 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 38087 + /* 38077 */ MCD_OPC_CheckPredicate, + 3, + 141, + 3, + 1, // Skip to: 104527 + /* 38082 */ MCD_OPC_Decode, + 132, + 22, + 178, + 1, // Opcode: LD1RB_S_IMM + /* 38087 */ MCD_OPC_FilterValue, + 2, + 40, + 0, + 0, // Skip to: 38132 + /* 38092 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 38095 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 38117 + /* 38100 */ MCD_OPC_CheckPredicate, + 3, + 118, + 3, + 1, // Skip to: 104527 + /* 38105 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 111, + 3, + 1, // Skip to: 104527 + /* 38112 */ MCD_OPC_Decode, + 225, + 28, + 179, + 1, // Opcode: PRFH_PRR + /* 38117 */ MCD_OPC_FilterValue, + 1, + 101, + 3, + 1, // Skip to: 104527 + /* 38122 */ MCD_OPC_CheckPredicate, + 6, + 96, + 3, + 1, // Skip to: 104527 + /* 38127 */ MCD_OPC_Decode, + 149, + 20, + 177, + 1, // Opcode: GLD1H_S_IMM_REAL + /* 38132 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 38147 + /* 38137 */ MCD_OPC_CheckPredicate, + 3, + 81, + 3, + 1, // Skip to: 104527 + /* 38142 */ MCD_OPC_Decode, + 136, + 22, + 178, + 1, // Opcode: LD1RH_S_IMM + /* 38147 */ MCD_OPC_FilterValue, + 4, + 40, + 0, + 0, // Skip to: 38192 + /* 38152 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 38155 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 38177 + /* 38160 */ MCD_OPC_CheckPredicate, + 3, + 58, + 3, + 1, // Skip to: 104527 + /* 38165 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 51, + 3, + 1, // Skip to: 104527 + /* 38172 */ MCD_OPC_Decode, + 233, + 28, + 179, + 1, // Opcode: PRFS_PRR + /* 38177 */ MCD_OPC_FilterValue, + 1, + 41, + 3, + 1, // Skip to: 104527 + /* 38182 */ MCD_OPC_CheckPredicate, + 6, + 36, + 3, + 1, // Skip to: 104527 + /* 38187 */ MCD_OPC_Decode, + 187, + 20, + 177, + 1, // Opcode: GLD1W_IMM_REAL + /* 38192 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 38207 + /* 38197 */ MCD_OPC_CheckPredicate, + 3, + 21, + 3, + 1, // Skip to: 104527 + /* 38202 */ MCD_OPC_Decode, + 160, + 22, + 178, + 1, // Opcode: LD1RW_IMM + /* 38207 */ MCD_OPC_FilterValue, + 6, + 24, + 0, + 0, // Skip to: 38236 + /* 38212 */ MCD_OPC_CheckPredicate, + 3, + 6, + 3, + 1, // Skip to: 104527 + /* 38217 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 255, + 2, + 1, // Skip to: 104527 + /* 38224 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 248, + 2, + 1, // Skip to: 104527 + /* 38231 */ MCD_OPC_Decode, + 216, + 28, + 179, + 1, // Opcode: PRFD_PRR + /* 38236 */ MCD_OPC_FilterValue, + 7, + 238, + 2, + 1, // Skip to: 104527 + /* 38241 */ MCD_OPC_CheckPredicate, + 3, + 233, + 2, + 1, // Skip to: 104527 + /* 38246 */ MCD_OPC_Decode, + 154, + 22, + 178, + 1, // Opcode: LD1RSB_H_IMM + /* 38251 */ MCD_OPC_FilterValue, + 7, + 223, + 2, + 1, // Skip to: 104527 + /* 38256 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 38259 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 38304 + /* 38264 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 38267 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 38289 + /* 38272 */ MCD_OPC_CheckPredicate, + 6, + 202, + 2, + 1, // Skip to: 104527 + /* 38277 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 195, + 2, + 1, // Skip to: 104527 + /* 38284 */ MCD_OPC_Decode, + 208, + 28, + 180, + 1, // Opcode: PRFB_S_PZI + /* 38289 */ MCD_OPC_FilterValue, + 1, + 185, + 2, + 1, // Skip to: 104527 + /* 38294 */ MCD_OPC_CheckPredicate, + 6, + 180, + 2, + 1, // Skip to: 104527 + /* 38299 */ MCD_OPC_Decode, + 196, + 20, + 177, + 1, // Opcode: GLDFF1B_S_IMM_REAL + /* 38304 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 38319 + /* 38309 */ MCD_OPC_CheckPredicate, + 3, + 165, + 2, + 1, // Skip to: 104527 + /* 38314 */ MCD_OPC_Decode, + 129, + 22, + 178, + 1, // Opcode: LD1RB_D_IMM + /* 38319 */ MCD_OPC_FilterValue, + 2, + 40, + 0, + 0, // Skip to: 38364 + /* 38324 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 38327 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 38349 + /* 38332 */ MCD_OPC_CheckPredicate, + 6, + 142, + 2, + 1, // Skip to: 104527 + /* 38337 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 135, + 2, + 1, // Skip to: 104527 + /* 38344 */ MCD_OPC_Decode, + 226, + 28, + 180, + 1, // Opcode: PRFH_S_PZI + /* 38349 */ MCD_OPC_FilterValue, + 1, + 125, + 2, + 1, // Skip to: 104527 + /* 38354 */ MCD_OPC_CheckPredicate, + 6, + 120, + 2, + 1, // Skip to: 104527 + /* 38359 */ MCD_OPC_Decode, + 213, + 20, + 177, + 1, // Opcode: GLDFF1H_S_IMM_REAL + /* 38364 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 38379 + /* 38369 */ MCD_OPC_CheckPredicate, + 3, + 105, + 2, + 1, // Skip to: 104527 + /* 38374 */ MCD_OPC_Decode, + 134, + 22, + 178, + 1, // Opcode: LD1RH_D_IMM + /* 38379 */ MCD_OPC_FilterValue, + 4, + 40, + 0, + 0, // Skip to: 38424 + /* 38384 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 38387 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 38409 + /* 38392 */ MCD_OPC_CheckPredicate, + 6, + 82, + 2, + 1, // Skip to: 104527 + /* 38397 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 75, + 2, + 1, // Skip to: 104527 + /* 38404 */ MCD_OPC_Decode, + 240, + 28, + 180, + 1, // Opcode: PRFW_S_PZI + /* 38409 */ MCD_OPC_FilterValue, + 1, + 65, + 2, + 1, // Skip to: 104527 + /* 38414 */ MCD_OPC_CheckPredicate, + 6, + 60, + 2, + 1, // Skip to: 104527 + /* 38419 */ MCD_OPC_Decode, + 251, + 20, + 177, + 1, // Opcode: GLDFF1W_IMM_REAL + /* 38424 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 38439 + /* 38429 */ MCD_OPC_CheckPredicate, + 3, + 45, + 2, + 1, // Skip to: 104527 + /* 38434 */ MCD_OPC_Decode, + 159, + 22, + 178, + 1, // Opcode: LD1RW_D_IMM + /* 38439 */ MCD_OPC_FilterValue, + 6, + 24, + 0, + 0, // Skip to: 38468 + /* 38444 */ MCD_OPC_CheckPredicate, + 6, + 30, + 2, + 1, // Skip to: 104527 + /* 38449 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 23, + 2, + 1, // Skip to: 104527 + /* 38456 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 16, + 2, + 1, // Skip to: 104527 + /* 38463 */ MCD_OPC_Decode, + 217, + 28, + 180, + 1, // Opcode: PRFD_S_PZI + /* 38468 */ MCD_OPC_FilterValue, + 7, + 6, + 2, + 1, // Skip to: 104527 + /* 38473 */ MCD_OPC_CheckPredicate, + 3, + 1, + 2, + 1, // Skip to: 104527 + /* 38478 */ MCD_OPC_Decode, + 133, + 22, + 178, + 1, // Opcode: LD1RD_IMM + /* 38483 */ MCD_OPC_FilterValue, + 5, + 59, + 8, + 0, // Skip to: 40595 + /* 38488 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 38491 */ MCD_OPC_FilterValue, + 0, + 145, + 0, + 0, // Skip to: 38641 + /* 38496 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 38499 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 38514 + /* 38504 */ MCD_OPC_CheckPredicate, + 3, + 226, + 1, + 1, // Skip to: 104527 + /* 38509 */ MCD_OPC_Decode, + 145, + 22, + 181, + 1, // Opcode: LD1RQ_B + /* 38514 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 38536 + /* 38519 */ MCD_OPC_CheckPredicate, + 3, + 211, + 1, + 1, // Skip to: 104527 + /* 38524 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 204, + 1, + 1, // Skip to: 104527 + /* 38531 */ MCD_OPC_Decode, + 146, + 22, + 182, + 1, // Opcode: LD1RQ_B_IMM + /* 38536 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 38551 + /* 38541 */ MCD_OPC_CheckPredicate, + 3, + 189, + 1, + 1, // Skip to: 104527 + /* 38546 */ MCD_OPC_Decode, + 209, + 21, + 181, + 1, // Opcode: LD1B + /* 38551 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 38566 + /* 38556 */ MCD_OPC_CheckPredicate, + 6, + 174, + 1, + 1, // Skip to: 104527 + /* 38561 */ MCD_OPC_Decode, + 199, + 24, + 183, + 1, // Opcode: LDFF1B_REAL + /* 38566 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 38604 + /* 38571 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 38574 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 38589 + /* 38579 */ MCD_OPC_CheckPredicate, + 3, + 151, + 1, + 1, // Skip to: 104527 + /* 38584 */ MCD_OPC_Decode, + 214, + 21, + 182, + 1, // Opcode: LD1B_IMM_REAL + /* 38589 */ MCD_OPC_FilterValue, + 1, + 141, + 1, + 1, // Skip to: 104527 + /* 38594 */ MCD_OPC_CheckPredicate, + 6, + 136, + 1, + 1, // Skip to: 104527 + /* 38599 */ MCD_OPC_Decode, + 221, + 24, + 182, + 1, // Opcode: LDNF1B_IMM_REAL + /* 38604 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 38619 + /* 38609 */ MCD_OPC_CheckPredicate, + 3, + 121, + 1, + 1, // Skip to: 104527 + /* 38614 */ MCD_OPC_Decode, + 241, + 24, + 181, + 1, // Opcode: LDNT1B_ZRR + /* 38619 */ MCD_OPC_FilterValue, + 7, + 111, + 1, + 1, // Skip to: 104527 + /* 38624 */ MCD_OPC_CheckPredicate, + 3, + 106, + 1, + 1, // Skip to: 104527 + /* 38629 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 99, + 1, + 1, // Skip to: 104527 + /* 38636 */ MCD_OPC_Decode, + 240, + 24, + 182, + 1, // Opcode: LDNT1B_ZRI + /* 38641 */ MCD_OPC_FilterValue, + 1, + 145, + 0, + 0, // Skip to: 38791 + /* 38646 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 38649 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 38664 + /* 38654 */ MCD_OPC_CheckPredicate, + 17, + 76, + 1, + 1, // Skip to: 104527 + /* 38659 */ MCD_OPC_Decode, + 137, + 22, + 181, + 1, // Opcode: LD1RO_B + /* 38664 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 38686 + /* 38669 */ MCD_OPC_CheckPredicate, + 17, + 61, + 1, + 1, // Skip to: 104527 + /* 38674 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 54, + 1, + 1, // Skip to: 104527 + /* 38681 */ MCD_OPC_Decode, + 138, + 22, + 182, + 1, // Opcode: LD1RO_B_IMM + /* 38686 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 38701 + /* 38691 */ MCD_OPC_CheckPredicate, + 3, + 39, + 1, + 1, // Skip to: 104527 + /* 38696 */ MCD_OPC_Decode, + 212, + 21, + 181, + 1, // Opcode: LD1B_H + /* 38701 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 38716 + /* 38706 */ MCD_OPC_CheckPredicate, + 6, + 24, + 1, + 1, // Skip to: 104527 + /* 38711 */ MCD_OPC_Decode, + 198, + 24, + 183, + 1, // Opcode: LDFF1B_H_REAL + /* 38716 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 38754 + /* 38721 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 38724 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 38739 + /* 38729 */ MCD_OPC_CheckPredicate, + 3, + 1, + 1, + 1, // Skip to: 104527 + /* 38734 */ MCD_OPC_Decode, + 213, + 21, + 182, + 1, // Opcode: LD1B_H_IMM_REAL + /* 38739 */ MCD_OPC_FilterValue, + 1, + 247, + 0, + 1, // Skip to: 104527 + /* 38744 */ MCD_OPC_CheckPredicate, + 6, + 242, + 0, + 1, // Skip to: 104527 + /* 38749 */ MCD_OPC_Decode, + 220, + 24, + 182, + 1, // Opcode: LDNF1B_H_IMM_REAL + /* 38754 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 38769 + /* 38759 */ MCD_OPC_CheckPredicate, + 3, + 227, + 0, + 1, // Skip to: 104527 + /* 38764 */ MCD_OPC_Decode, + 243, + 22, + 184, + 1, // Opcode: LD2B + /* 38769 */ MCD_OPC_FilterValue, + 7, + 217, + 0, + 1, // Skip to: 104527 + /* 38774 */ MCD_OPC_CheckPredicate, + 3, + 212, + 0, + 1, // Skip to: 104527 + /* 38779 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 205, + 0, + 1, // Skip to: 104527 + /* 38786 */ MCD_OPC_Decode, + 244, + 22, + 185, + 1, // Opcode: LD2B_IMM + /* 38791 */ MCD_OPC_FilterValue, + 2, + 108, + 0, + 0, // Skip to: 38904 + /* 38796 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 38799 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 38814 + /* 38804 */ MCD_OPC_CheckPredicate, + 3, + 182, + 0, + 1, // Skip to: 104527 + /* 38809 */ MCD_OPC_Decode, + 215, + 21, + 181, + 1, // Opcode: LD1B_S + /* 38814 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 38829 + /* 38819 */ MCD_OPC_CheckPredicate, + 6, + 167, + 0, + 1, // Skip to: 104527 + /* 38824 */ MCD_OPC_Decode, + 200, + 24, + 183, + 1, // Opcode: LDFF1B_S_REAL + /* 38829 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 38867 + /* 38834 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 38837 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 38852 + /* 38842 */ MCD_OPC_CheckPredicate, + 3, + 144, + 0, + 1, // Skip to: 104527 + /* 38847 */ MCD_OPC_Decode, + 216, + 21, + 182, + 1, // Opcode: LD1B_S_IMM_REAL + /* 38852 */ MCD_OPC_FilterValue, + 1, + 134, + 0, + 1, // Skip to: 104527 + /* 38857 */ MCD_OPC_CheckPredicate, + 6, + 129, + 0, + 1, // Skip to: 104527 + /* 38862 */ MCD_OPC_Decode, + 222, + 24, + 182, + 1, // Opcode: LDNF1B_S_IMM_REAL + /* 38867 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 38882 + /* 38872 */ MCD_OPC_CheckPredicate, + 3, + 114, + 0, + 1, // Skip to: 104527 + /* 38877 */ MCD_OPC_Decode, + 161, + 23, + 186, + 1, // Opcode: LD3B + /* 38882 */ MCD_OPC_FilterValue, + 7, + 104, + 0, + 1, // Skip to: 104527 + /* 38887 */ MCD_OPC_CheckPredicate, + 3, + 99, + 0, + 1, // Skip to: 104527 + /* 38892 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 92, + 0, + 1, // Skip to: 104527 + /* 38899 */ MCD_OPC_Decode, + 162, + 23, + 187, + 1, // Opcode: LD3B_IMM + /* 38904 */ MCD_OPC_FilterValue, + 3, + 108, + 0, + 0, // Skip to: 39017 + /* 38909 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 38912 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 38927 + /* 38917 */ MCD_OPC_CheckPredicate, + 3, + 69, + 0, + 1, // Skip to: 104527 + /* 38922 */ MCD_OPC_Decode, + 210, + 21, + 181, + 1, // Opcode: LD1B_D + /* 38927 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 38942 + /* 38932 */ MCD_OPC_CheckPredicate, + 6, + 54, + 0, + 1, // Skip to: 104527 + /* 38937 */ MCD_OPC_Decode, + 197, + 24, + 183, + 1, // Opcode: LDFF1B_D_REAL + /* 38942 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 38980 + /* 38947 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 38950 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 38965 + /* 38955 */ MCD_OPC_CheckPredicate, + 3, + 31, + 0, + 1, // Skip to: 104527 + /* 38960 */ MCD_OPC_Decode, + 211, + 21, + 182, + 1, // Opcode: LD1B_D_IMM_REAL + /* 38965 */ MCD_OPC_FilterValue, + 1, + 21, + 0, + 1, // Skip to: 104527 + /* 38970 */ MCD_OPC_CheckPredicate, + 6, + 16, + 0, + 1, // Skip to: 104527 + /* 38975 */ MCD_OPC_Decode, + 219, + 24, + 182, + 1, // Opcode: LDNF1B_D_IMM_REAL + /* 38980 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 38995 + /* 38985 */ MCD_OPC_CheckPredicate, + 3, + 1, + 0, + 1, // Skip to: 104527 + /* 38990 */ MCD_OPC_Decode, + 207, + 23, + 188, + 1, // Opcode: LD4B + /* 38995 */ MCD_OPC_FilterValue, + 7, + 247, + 255, + 0, // Skip to: 104527 + /* 39000 */ MCD_OPC_CheckPredicate, + 3, + 242, + 255, + 0, // Skip to: 104527 + /* 39005 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 235, + 255, + 0, // Skip to: 104527 + /* 39012 */ MCD_OPC_Decode, + 208, + 23, + 189, + 1, // Opcode: LD4B_IMM + /* 39017 */ MCD_OPC_FilterValue, + 4, + 145, + 0, + 0, // Skip to: 39167 + /* 39022 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 39025 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39040 + /* 39030 */ MCD_OPC_CheckPredicate, + 3, + 212, + 255, + 0, // Skip to: 104527 + /* 39035 */ MCD_OPC_Decode, + 149, + 22, + 181, + 1, // Opcode: LD1RQ_H + /* 39040 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 39062 + /* 39045 */ MCD_OPC_CheckPredicate, + 3, + 197, + 255, + 0, // Skip to: 104527 + /* 39050 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 190, + 255, + 0, // Skip to: 104527 + /* 39057 */ MCD_OPC_Decode, + 150, + 22, + 182, + 1, // Opcode: LD1RQ_H_IMM + /* 39062 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 39077 + /* 39067 */ MCD_OPC_CheckPredicate, + 3, + 175, + 255, + 0, // Skip to: 104527 + /* 39072 */ MCD_OPC_Decode, + 187, + 22, + 181, + 1, // Opcode: LD1SW_D + /* 39077 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 39092 + /* 39082 */ MCD_OPC_CheckPredicate, + 6, + 160, + 255, + 0, // Skip to: 104527 + /* 39087 */ MCD_OPC_Decode, + 210, + 24, + 183, + 1, // Opcode: LDFF1SW_D_REAL + /* 39092 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 39130 + /* 39097 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 39100 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39115 + /* 39105 */ MCD_OPC_CheckPredicate, + 3, + 137, + 255, + 0, // Skip to: 104527 + /* 39110 */ MCD_OPC_Decode, + 188, + 22, + 182, + 1, // Opcode: LD1SW_D_IMM_REAL + /* 39115 */ MCD_OPC_FilterValue, + 1, + 127, + 255, + 0, // Skip to: 104527 + /* 39120 */ MCD_OPC_CheckPredicate, + 6, + 122, + 255, + 0, // Skip to: 104527 + /* 39125 */ MCD_OPC_Decode, + 232, + 24, + 182, + 1, // Opcode: LDNF1SW_D_IMM_REAL + /* 39130 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 39145 + /* 39135 */ MCD_OPC_CheckPredicate, + 3, + 107, + 255, + 0, // Skip to: 104527 + /* 39140 */ MCD_OPC_Decode, + 248, + 24, + 181, + 1, // Opcode: LDNT1H_ZRR + /* 39145 */ MCD_OPC_FilterValue, + 7, + 97, + 255, + 0, // Skip to: 104527 + /* 39150 */ MCD_OPC_CheckPredicate, + 3, + 92, + 255, + 0, // Skip to: 104527 + /* 39155 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 85, + 255, + 0, // Skip to: 104527 + /* 39162 */ MCD_OPC_Decode, + 247, + 24, + 182, + 1, // Opcode: LDNT1H_ZRI + /* 39167 */ MCD_OPC_FilterValue, + 5, + 145, + 0, + 0, // Skip to: 39317 + /* 39172 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 39175 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39190 + /* 39180 */ MCD_OPC_CheckPredicate, + 17, + 62, + 255, + 0, // Skip to: 104527 + /* 39185 */ MCD_OPC_Decode, + 141, + 22, + 181, + 1, // Opcode: LD1RO_H + /* 39190 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 39212 + /* 39195 */ MCD_OPC_CheckPredicate, + 17, + 47, + 255, + 0, // Skip to: 104527 + /* 39200 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 40, + 255, + 0, // Skip to: 104527 + /* 39207 */ MCD_OPC_Decode, + 142, + 22, + 182, + 1, // Opcode: LD1RO_H_IMM + /* 39212 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 39227 + /* 39217 */ MCD_OPC_CheckPredicate, + 3, + 25, + 255, + 0, // Skip to: 104527 + /* 39222 */ MCD_OPC_Decode, + 235, + 21, + 181, + 1, // Opcode: LD1H + /* 39227 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 39242 + /* 39232 */ MCD_OPC_CheckPredicate, + 6, + 10, + 255, + 0, // Skip to: 104527 + /* 39237 */ MCD_OPC_Decode, + 203, + 24, + 183, + 1, // Opcode: LDFF1H_REAL + /* 39242 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 39280 + /* 39247 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 39250 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39265 + /* 39255 */ MCD_OPC_CheckPredicate, + 3, + 243, + 254, + 0, // Skip to: 104527 + /* 39260 */ MCD_OPC_Decode, + 238, + 21, + 182, + 1, // Opcode: LD1H_IMM_REAL + /* 39265 */ MCD_OPC_FilterValue, + 1, + 233, + 254, + 0, // Skip to: 104527 + /* 39270 */ MCD_OPC_CheckPredicate, + 6, + 228, + 254, + 0, // Skip to: 104527 + /* 39275 */ MCD_OPC_Decode, + 225, + 24, + 182, + 1, // Opcode: LDNF1H_IMM_REAL + /* 39280 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 39295 + /* 39285 */ MCD_OPC_CheckPredicate, + 3, + 213, + 254, + 0, // Skip to: 104527 + /* 39290 */ MCD_OPC_Decode, + 247, + 22, + 184, + 1, // Opcode: LD2H + /* 39295 */ MCD_OPC_FilterValue, + 7, + 203, + 254, + 0, // Skip to: 104527 + /* 39300 */ MCD_OPC_CheckPredicate, + 3, + 198, + 254, + 0, // Skip to: 104527 + /* 39305 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 191, + 254, + 0, // Skip to: 104527 + /* 39312 */ MCD_OPC_Decode, + 248, + 22, + 185, + 1, // Opcode: LD2H_IMM + /* 39317 */ MCD_OPC_FilterValue, + 6, + 108, + 0, + 0, // Skip to: 39430 + /* 39322 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 39325 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 39340 + /* 39330 */ MCD_OPC_CheckPredicate, + 3, + 168, + 254, + 0, // Skip to: 104527 + /* 39335 */ MCD_OPC_Decode, + 239, + 21, + 181, + 1, // Opcode: LD1H_S + /* 39340 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 39355 + /* 39345 */ MCD_OPC_CheckPredicate, + 6, + 153, + 254, + 0, // Skip to: 104527 + /* 39350 */ MCD_OPC_Decode, + 204, + 24, + 183, + 1, // Opcode: LDFF1H_S_REAL + /* 39355 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 39393 + /* 39360 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 39363 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39378 + /* 39368 */ MCD_OPC_CheckPredicate, + 3, + 130, + 254, + 0, // Skip to: 104527 + /* 39373 */ MCD_OPC_Decode, + 240, + 21, + 182, + 1, // Opcode: LD1H_S_IMM_REAL + /* 39378 */ MCD_OPC_FilterValue, + 1, + 120, + 254, + 0, // Skip to: 104527 + /* 39383 */ MCD_OPC_CheckPredicate, + 6, + 115, + 254, + 0, // Skip to: 104527 + /* 39388 */ MCD_OPC_Decode, + 226, + 24, + 182, + 1, // Opcode: LDNF1H_S_IMM_REAL + /* 39393 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 39408 + /* 39398 */ MCD_OPC_CheckPredicate, + 3, + 100, + 254, + 0, // Skip to: 104527 + /* 39403 */ MCD_OPC_Decode, + 165, + 23, + 186, + 1, // Opcode: LD3H + /* 39408 */ MCD_OPC_FilterValue, + 7, + 90, + 254, + 0, // Skip to: 104527 + /* 39413 */ MCD_OPC_CheckPredicate, + 3, + 85, + 254, + 0, // Skip to: 104527 + /* 39418 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 78, + 254, + 0, // Skip to: 104527 + /* 39425 */ MCD_OPC_Decode, + 166, + 23, + 187, + 1, // Opcode: LD3H_IMM + /* 39430 */ MCD_OPC_FilterValue, + 7, + 108, + 0, + 0, // Skip to: 39543 + /* 39435 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 39438 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 39453 + /* 39443 */ MCD_OPC_CheckPredicate, + 3, + 55, + 254, + 0, // Skip to: 104527 + /* 39448 */ MCD_OPC_Decode, + 236, + 21, + 181, + 1, // Opcode: LD1H_D + /* 39453 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 39468 + /* 39458 */ MCD_OPC_CheckPredicate, + 6, + 40, + 254, + 0, // Skip to: 104527 + /* 39463 */ MCD_OPC_Decode, + 202, + 24, + 183, + 1, // Opcode: LDFF1H_D_REAL + /* 39468 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 39506 + /* 39473 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 39476 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39491 + /* 39481 */ MCD_OPC_CheckPredicate, + 3, + 17, + 254, + 0, // Skip to: 104527 + /* 39486 */ MCD_OPC_Decode, + 237, + 21, + 182, + 1, // Opcode: LD1H_D_IMM_REAL + /* 39491 */ MCD_OPC_FilterValue, + 1, + 7, + 254, + 0, // Skip to: 104527 + /* 39496 */ MCD_OPC_CheckPredicate, + 6, + 2, + 254, + 0, // Skip to: 104527 + /* 39501 */ MCD_OPC_Decode, + 224, + 24, + 182, + 1, // Opcode: LDNF1H_D_IMM_REAL + /* 39506 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 39521 + /* 39511 */ MCD_OPC_CheckPredicate, + 3, + 243, + 253, + 0, // Skip to: 104527 + /* 39516 */ MCD_OPC_Decode, + 225, + 23, + 188, + 1, // Opcode: LD4H + /* 39521 */ MCD_OPC_FilterValue, + 7, + 233, + 253, + 0, // Skip to: 104527 + /* 39526 */ MCD_OPC_CheckPredicate, + 3, + 228, + 253, + 0, // Skip to: 104527 + /* 39531 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 221, + 253, + 0, // Skip to: 104527 + /* 39538 */ MCD_OPC_Decode, + 226, + 23, + 189, + 1, // Opcode: LD4H_IMM + /* 39543 */ MCD_OPC_FilterValue, + 8, + 145, + 0, + 0, // Skip to: 39693 + /* 39548 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 39551 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39566 + /* 39556 */ MCD_OPC_CheckPredicate, + 3, + 198, + 253, + 0, // Skip to: 104527 + /* 39561 */ MCD_OPC_Decode, + 151, + 22, + 181, + 1, // Opcode: LD1RQ_W + /* 39566 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 39588 + /* 39571 */ MCD_OPC_CheckPredicate, + 3, + 183, + 253, + 0, // Skip to: 104527 + /* 39576 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 176, + 253, + 0, // Skip to: 104527 + /* 39583 */ MCD_OPC_Decode, + 152, + 22, + 182, + 1, // Opcode: LD1RQ_W_IMM + /* 39588 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 39603 + /* 39593 */ MCD_OPC_CheckPredicate, + 3, + 161, + 253, + 0, // Skip to: 104527 + /* 39598 */ MCD_OPC_Decode, + 183, + 22, + 181, + 1, // Opcode: LD1SH_D + /* 39603 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 39618 + /* 39608 */ MCD_OPC_CheckPredicate, + 6, + 146, + 253, + 0, // Skip to: 104527 + /* 39613 */ MCD_OPC_Decode, + 208, + 24, + 183, + 1, // Opcode: LDFF1SH_D_REAL + /* 39618 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 39656 + /* 39623 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 39626 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39641 + /* 39631 */ MCD_OPC_CheckPredicate, + 3, + 123, + 253, + 0, // Skip to: 104527 + /* 39636 */ MCD_OPC_Decode, + 184, + 22, + 182, + 1, // Opcode: LD1SH_D_IMM_REAL + /* 39641 */ MCD_OPC_FilterValue, + 1, + 113, + 253, + 0, // Skip to: 104527 + /* 39646 */ MCD_OPC_CheckPredicate, + 6, + 108, + 253, + 0, // Skip to: 104527 + /* 39651 */ MCD_OPC_Decode, + 230, + 24, + 182, + 1, // Opcode: LDNF1SH_D_IMM_REAL + /* 39656 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 39671 + /* 39661 */ MCD_OPC_CheckPredicate, + 3, + 93, + 253, + 0, // Skip to: 104527 + /* 39666 */ MCD_OPC_Decode, + 129, + 25, + 181, + 1, // Opcode: LDNT1W_ZRR + /* 39671 */ MCD_OPC_FilterValue, + 7, + 83, + 253, + 0, // Skip to: 104527 + /* 39676 */ MCD_OPC_CheckPredicate, + 3, + 78, + 253, + 0, // Skip to: 104527 + /* 39681 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 71, + 253, + 0, // Skip to: 104527 + /* 39688 */ MCD_OPC_Decode, + 128, + 25, + 182, + 1, // Opcode: LDNT1W_ZRI + /* 39693 */ MCD_OPC_FilterValue, + 9, + 145, + 0, + 0, // Skip to: 39843 + /* 39698 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 39701 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39716 + /* 39706 */ MCD_OPC_CheckPredicate, + 17, + 48, + 253, + 0, // Skip to: 104527 + /* 39711 */ MCD_OPC_Decode, + 143, + 22, + 181, + 1, // Opcode: LD1RO_W + /* 39716 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 39738 + /* 39721 */ MCD_OPC_CheckPredicate, + 17, + 33, + 253, + 0, // Skip to: 104527 + /* 39726 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 26, + 253, + 0, // Skip to: 104527 + /* 39733 */ MCD_OPC_Decode, + 144, + 22, + 182, + 1, // Opcode: LD1RO_W_IMM + /* 39738 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 39753 + /* 39743 */ MCD_OPC_CheckPredicate, + 3, + 11, + 253, + 0, // Skip to: 104527 + /* 39748 */ MCD_OPC_Decode, + 185, + 22, + 181, + 1, // Opcode: LD1SH_S + /* 39753 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 39768 + /* 39758 */ MCD_OPC_CheckPredicate, + 6, + 252, + 252, + 0, // Skip to: 104527 + /* 39763 */ MCD_OPC_Decode, + 209, + 24, + 183, + 1, // Opcode: LDFF1SH_S_REAL + /* 39768 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 39806 + /* 39773 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 39776 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39791 + /* 39781 */ MCD_OPC_CheckPredicate, + 3, + 229, + 252, + 0, // Skip to: 104527 + /* 39786 */ MCD_OPC_Decode, + 186, + 22, + 182, + 1, // Opcode: LD1SH_S_IMM_REAL + /* 39791 */ MCD_OPC_FilterValue, + 1, + 219, + 252, + 0, // Skip to: 104527 + /* 39796 */ MCD_OPC_CheckPredicate, + 6, + 214, + 252, + 0, // Skip to: 104527 + /* 39801 */ MCD_OPC_Decode, + 231, + 24, + 182, + 1, // Opcode: LDNF1SH_S_IMM_REAL + /* 39806 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 39821 + /* 39811 */ MCD_OPC_CheckPredicate, + 3, + 199, + 252, + 0, // Skip to: 104527 + /* 39816 */ MCD_OPC_Decode, + 151, + 23, + 184, + 1, // Opcode: LD2W + /* 39821 */ MCD_OPC_FilterValue, + 7, + 189, + 252, + 0, // Skip to: 104527 + /* 39826 */ MCD_OPC_CheckPredicate, + 3, + 184, + 252, + 0, // Skip to: 104527 + /* 39831 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 177, + 252, + 0, // Skip to: 104527 + /* 39838 */ MCD_OPC_Decode, + 152, + 23, + 185, + 1, // Opcode: LD2W_IMM + /* 39843 */ MCD_OPC_FilterValue, + 10, + 108, + 0, + 0, // Skip to: 39956 + /* 39848 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 39851 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 39866 + /* 39856 */ MCD_OPC_CheckPredicate, + 3, + 154, + 252, + 0, // Skip to: 104527 + /* 39861 */ MCD_OPC_Decode, + 221, + 22, + 181, + 1, // Opcode: LD1W + /* 39866 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 39881 + /* 39871 */ MCD_OPC_CheckPredicate, + 6, + 139, + 252, + 0, // Skip to: 104527 + /* 39876 */ MCD_OPC_Decode, + 212, + 24, + 183, + 1, // Opcode: LDFF1W_REAL + /* 39881 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 39919 + /* 39886 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 39889 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 39904 + /* 39894 */ MCD_OPC_CheckPredicate, + 3, + 116, + 252, + 0, // Skip to: 104527 + /* 39899 */ MCD_OPC_Decode, + 224, + 22, + 182, + 1, // Opcode: LD1W_IMM_REAL + /* 39904 */ MCD_OPC_FilterValue, + 1, + 106, + 252, + 0, // Skip to: 104527 + /* 39909 */ MCD_OPC_CheckPredicate, + 6, + 101, + 252, + 0, // Skip to: 104527 + /* 39914 */ MCD_OPC_Decode, + 234, + 24, + 182, + 1, // Opcode: LDNF1W_IMM_REAL + /* 39919 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 39934 + /* 39924 */ MCD_OPC_CheckPredicate, + 3, + 86, + 252, + 0, // Skip to: 104527 + /* 39929 */ MCD_OPC_Decode, + 197, + 23, + 186, + 1, // Opcode: LD3W + /* 39934 */ MCD_OPC_FilterValue, + 7, + 76, + 252, + 0, // Skip to: 104527 + /* 39939 */ MCD_OPC_CheckPredicate, + 3, + 71, + 252, + 0, // Skip to: 104527 + /* 39944 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 64, + 252, + 0, // Skip to: 104527 + /* 39951 */ MCD_OPC_Decode, + 198, + 23, + 187, + 1, // Opcode: LD3W_IMM + /* 39956 */ MCD_OPC_FilterValue, + 11, + 108, + 0, + 0, // Skip to: 40069 + /* 39961 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 39964 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 39979 + /* 39969 */ MCD_OPC_CheckPredicate, + 3, + 41, + 252, + 0, // Skip to: 104527 + /* 39974 */ MCD_OPC_Decode, + 222, + 22, + 181, + 1, // Opcode: LD1W_D + /* 39979 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 39994 + /* 39984 */ MCD_OPC_CheckPredicate, + 6, + 26, + 252, + 0, // Skip to: 104527 + /* 39989 */ MCD_OPC_Decode, + 211, + 24, + 183, + 1, // Opcode: LDFF1W_D_REAL + /* 39994 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 40032 + /* 39999 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 40002 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 40017 + /* 40007 */ MCD_OPC_CheckPredicate, + 3, + 3, + 252, + 0, // Skip to: 104527 + /* 40012 */ MCD_OPC_Decode, + 223, + 22, + 182, + 1, // Opcode: LD1W_D_IMM_REAL + /* 40017 */ MCD_OPC_FilterValue, + 1, + 249, + 251, + 0, // Skip to: 104527 + /* 40022 */ MCD_OPC_CheckPredicate, + 6, + 244, + 251, + 0, // Skip to: 104527 + /* 40027 */ MCD_OPC_Decode, + 233, + 24, + 182, + 1, // Opcode: LDNF1W_D_IMM_REAL + /* 40032 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 40047 + /* 40037 */ MCD_OPC_CheckPredicate, + 3, + 229, + 251, + 0, // Skip to: 104527 + /* 40042 */ MCD_OPC_Decode, + 243, + 23, + 188, + 1, // Opcode: LD4W + /* 40047 */ MCD_OPC_FilterValue, + 7, + 219, + 251, + 0, // Skip to: 104527 + /* 40052 */ MCD_OPC_CheckPredicate, + 3, + 214, + 251, + 0, // Skip to: 104527 + /* 40057 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 207, + 251, + 0, // Skip to: 104527 + /* 40064 */ MCD_OPC_Decode, + 244, + 23, + 189, + 1, // Opcode: LD4W_IMM + /* 40069 */ MCD_OPC_FilterValue, + 12, + 145, + 0, + 0, // Skip to: 40219 + /* 40074 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 40077 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 40092 + /* 40082 */ MCD_OPC_CheckPredicate, + 3, + 184, + 251, + 0, // Skip to: 104527 + /* 40087 */ MCD_OPC_Decode, + 147, + 22, + 181, + 1, // Opcode: LD1RQ_D + /* 40092 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 40114 + /* 40097 */ MCD_OPC_CheckPredicate, + 3, + 169, + 251, + 0, // Skip to: 104527 + /* 40102 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 162, + 251, + 0, // Skip to: 104527 + /* 40109 */ MCD_OPC_Decode, + 148, + 22, + 182, + 1, // Opcode: LD1RQ_D_IMM + /* 40114 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 40129 + /* 40119 */ MCD_OPC_CheckPredicate, + 3, + 147, + 251, + 0, // Skip to: 104527 + /* 40124 */ MCD_OPC_Decode, + 177, + 22, + 181, + 1, // Opcode: LD1SB_D + /* 40129 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 40144 + /* 40134 */ MCD_OPC_CheckPredicate, + 6, + 132, + 251, + 0, // Skip to: 104527 + /* 40139 */ MCD_OPC_Decode, + 205, + 24, + 183, + 1, // Opcode: LDFF1SB_D_REAL + /* 40144 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 40182 + /* 40149 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 40152 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 40167 + /* 40157 */ MCD_OPC_CheckPredicate, + 3, + 109, + 251, + 0, // Skip to: 104527 + /* 40162 */ MCD_OPC_Decode, + 178, + 22, + 182, + 1, // Opcode: LD1SB_D_IMM_REAL + /* 40167 */ MCD_OPC_FilterValue, + 1, + 99, + 251, + 0, // Skip to: 104527 + /* 40172 */ MCD_OPC_CheckPredicate, + 6, + 94, + 251, + 0, // Skip to: 104527 + /* 40177 */ MCD_OPC_Decode, + 227, + 24, + 182, + 1, // Opcode: LDNF1SB_D_IMM_REAL + /* 40182 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 40197 + /* 40187 */ MCD_OPC_CheckPredicate, + 3, + 79, + 251, + 0, // Skip to: 104527 + /* 40192 */ MCD_OPC_Decode, + 245, + 24, + 181, + 1, // Opcode: LDNT1D_ZRR + /* 40197 */ MCD_OPC_FilterValue, + 7, + 69, + 251, + 0, // Skip to: 104527 + /* 40202 */ MCD_OPC_CheckPredicate, + 3, + 64, + 251, + 0, // Skip to: 104527 + /* 40207 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 57, + 251, + 0, // Skip to: 104527 + /* 40214 */ MCD_OPC_Decode, + 244, + 24, + 182, + 1, // Opcode: LDNT1D_ZRI + /* 40219 */ MCD_OPC_FilterValue, + 13, + 145, + 0, + 0, // Skip to: 40369 + /* 40224 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 40227 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 40242 + /* 40232 */ MCD_OPC_CheckPredicate, + 17, + 34, + 251, + 0, // Skip to: 104527 + /* 40237 */ MCD_OPC_Decode, + 139, + 22, + 181, + 1, // Opcode: LD1RO_D + /* 40242 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 40264 + /* 40247 */ MCD_OPC_CheckPredicate, + 17, + 19, + 251, + 0, // Skip to: 104527 + /* 40252 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 12, + 251, + 0, // Skip to: 104527 + /* 40259 */ MCD_OPC_Decode, + 140, + 22, + 182, + 1, // Opcode: LD1RO_D_IMM + /* 40264 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 40279 + /* 40269 */ MCD_OPC_CheckPredicate, + 3, + 253, + 250, + 0, // Skip to: 104527 + /* 40274 */ MCD_OPC_Decode, + 181, + 22, + 181, + 1, // Opcode: LD1SB_S + /* 40279 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 40294 + /* 40284 */ MCD_OPC_CheckPredicate, + 6, + 238, + 250, + 0, // Skip to: 104527 + /* 40289 */ MCD_OPC_Decode, + 207, + 24, + 183, + 1, // Opcode: LDFF1SB_S_REAL + /* 40294 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 40332 + /* 40299 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 40302 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 40317 + /* 40307 */ MCD_OPC_CheckPredicate, + 3, + 215, + 250, + 0, // Skip to: 104527 + /* 40312 */ MCD_OPC_Decode, + 182, + 22, + 182, + 1, // Opcode: LD1SB_S_IMM_REAL + /* 40317 */ MCD_OPC_FilterValue, + 1, + 205, + 250, + 0, // Skip to: 104527 + /* 40322 */ MCD_OPC_CheckPredicate, + 6, + 200, + 250, + 0, // Skip to: 104527 + /* 40327 */ MCD_OPC_Decode, + 229, + 24, + 182, + 1, // Opcode: LDNF1SB_S_IMM_REAL + /* 40332 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 40347 + /* 40337 */ MCD_OPC_CheckPredicate, + 3, + 185, + 250, + 0, // Skip to: 104527 + /* 40342 */ MCD_OPC_Decode, + 245, + 22, + 184, + 1, // Opcode: LD2D + /* 40347 */ MCD_OPC_FilterValue, + 7, + 175, + 250, + 0, // Skip to: 104527 + /* 40352 */ MCD_OPC_CheckPredicate, + 3, + 170, + 250, + 0, // Skip to: 104527 + /* 40357 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 163, + 250, + 0, // Skip to: 104527 + /* 40364 */ MCD_OPC_Decode, + 246, + 22, + 185, + 1, // Opcode: LD2D_IMM + /* 40369 */ MCD_OPC_FilterValue, + 14, + 108, + 0, + 0, // Skip to: 40482 + /* 40374 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 40377 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 40392 + /* 40382 */ MCD_OPC_CheckPredicate, + 3, + 140, + 250, + 0, // Skip to: 104527 + /* 40387 */ MCD_OPC_Decode, + 179, + 22, + 181, + 1, // Opcode: LD1SB_H + /* 40392 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 40407 + /* 40397 */ MCD_OPC_CheckPredicate, + 6, + 125, + 250, + 0, // Skip to: 104527 + /* 40402 */ MCD_OPC_Decode, + 206, + 24, + 183, + 1, // Opcode: LDFF1SB_H_REAL + /* 40407 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 40445 + /* 40412 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 40415 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 40430 + /* 40420 */ MCD_OPC_CheckPredicate, + 3, + 102, + 250, + 0, // Skip to: 104527 + /* 40425 */ MCD_OPC_Decode, + 180, + 22, + 182, + 1, // Opcode: LD1SB_H_IMM_REAL + /* 40430 */ MCD_OPC_FilterValue, + 1, + 92, + 250, + 0, // Skip to: 104527 + /* 40435 */ MCD_OPC_CheckPredicate, + 6, + 87, + 250, + 0, // Skip to: 104527 + /* 40440 */ MCD_OPC_Decode, + 228, + 24, + 182, + 1, // Opcode: LDNF1SB_H_IMM_REAL + /* 40445 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 40460 + /* 40450 */ MCD_OPC_CheckPredicate, + 3, + 72, + 250, + 0, // Skip to: 104527 + /* 40455 */ MCD_OPC_Decode, + 163, + 23, + 186, + 1, // Opcode: LD3D + /* 40460 */ MCD_OPC_FilterValue, + 7, + 62, + 250, + 0, // Skip to: 104527 + /* 40465 */ MCD_OPC_CheckPredicate, + 3, + 57, + 250, + 0, // Skip to: 104527 + /* 40470 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 50, + 250, + 0, // Skip to: 104527 + /* 40477 */ MCD_OPC_Decode, + 164, + 23, + 187, + 1, // Opcode: LD3D_IMM + /* 40482 */ MCD_OPC_FilterValue, + 15, + 40, + 250, + 0, // Skip to: 104527 + /* 40487 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 40490 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 40505 + /* 40495 */ MCD_OPC_CheckPredicate, + 3, + 27, + 250, + 0, // Skip to: 104527 + /* 40500 */ MCD_OPC_Decode, + 217, + 21, + 181, + 1, // Opcode: LD1D + /* 40505 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 40520 + /* 40510 */ MCD_OPC_CheckPredicate, + 6, + 12, + 250, + 0, // Skip to: 104527 + /* 40515 */ MCD_OPC_Decode, + 201, + 24, + 183, + 1, // Opcode: LDFF1D_REAL + /* 40520 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 40558 + /* 40525 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 40528 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 40543 + /* 40533 */ MCD_OPC_CheckPredicate, + 3, + 245, + 249, + 0, // Skip to: 104527 + /* 40538 */ MCD_OPC_Decode, + 218, + 21, + 182, + 1, // Opcode: LD1D_IMM_REAL + /* 40543 */ MCD_OPC_FilterValue, + 1, + 235, + 249, + 0, // Skip to: 104527 + /* 40548 */ MCD_OPC_CheckPredicate, + 6, + 230, + 249, + 0, // Skip to: 104527 + /* 40553 */ MCD_OPC_Decode, + 223, + 24, + 182, + 1, // Opcode: LDNF1D_IMM_REAL + /* 40558 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 40573 + /* 40563 */ MCD_OPC_CheckPredicate, + 3, + 215, + 249, + 0, // Skip to: 104527 + /* 40568 */ MCD_OPC_Decode, + 209, + 23, + 188, + 1, // Opcode: LD4D + /* 40573 */ MCD_OPC_FilterValue, + 7, + 205, + 249, + 0, // Skip to: 104527 + /* 40578 */ MCD_OPC_CheckPredicate, + 3, + 200, + 249, + 0, // Skip to: 104527 + /* 40583 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 193, + 249, + 0, // Skip to: 104527 + /* 40590 */ MCD_OPC_Decode, + 210, + 23, + 189, + 1, // Opcode: LD4D_IMM + /* 40595 */ MCD_OPC_FilterValue, + 6, + 86, + 7, + 0, // Skip to: 42478 + /* 40600 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 40603 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 40723 + /* 40608 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 40611 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 40626 + /* 40616 */ MCD_OPC_CheckPredicate, + 6, + 162, + 249, + 0, // Skip to: 104527 + /* 40621 */ MCD_OPC_Decode, + 157, + 20, + 171, + 1, // Opcode: GLD1SB_D_UXTW_REAL + /* 40626 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 40641 + /* 40631 */ MCD_OPC_CheckPredicate, + 6, + 147, + 249, + 0, // Skip to: 104527 + /* 40636 */ MCD_OPC_Decode, + 221, + 20, + 171, + 1, // Opcode: GLDFF1SB_D_UXTW_REAL + /* 40641 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 40656 + /* 40646 */ MCD_OPC_CheckPredicate, + 6, + 132, + 249, + 0, // Skip to: 104527 + /* 40651 */ MCD_OPC_Decode, + 131, + 20, + 171, + 1, // Opcode: GLD1B_D_UXTW_REAL + /* 40656 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 40671 + /* 40661 */ MCD_OPC_CheckPredicate, + 6, + 117, + 249, + 0, // Skip to: 104527 + /* 40666 */ MCD_OPC_Decode, + 195, + 20, + 171, + 1, // Opcode: GLDFF1B_D_UXTW_REAL + /* 40671 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 40686 + /* 40676 */ MCD_OPC_CheckPredicate, + 10, + 102, + 249, + 0, // Skip to: 104527 + /* 40681 */ MCD_OPC_Decode, + 251, + 24, + 176, + 1, // Opcode: LDNT1SB_ZZR_D_REAL + /* 40686 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 40701 + /* 40691 */ MCD_OPC_CheckPredicate, + 10, + 87, + 249, + 0, // Skip to: 104527 + /* 40696 */ MCD_OPC_Decode, + 242, + 24, + 176, + 1, // Opcode: LDNT1B_ZZR_D_REAL + /* 40701 */ MCD_OPC_FilterValue, + 7, + 77, + 249, + 0, // Skip to: 104527 + /* 40706 */ MCD_OPC_CheckPredicate, + 6, + 72, + 249, + 0, // Skip to: 104527 + /* 40711 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 65, + 249, + 0, // Skip to: 104527 + /* 40718 */ MCD_OPC_Decode, + 202, + 28, + 180, + 1, // Opcode: PRFB_D_PZI + /* 40723 */ MCD_OPC_FilterValue, + 1, + 151, + 0, + 0, // Skip to: 40879 + /* 40728 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 40731 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 40753 + /* 40736 */ MCD_OPC_CheckPredicate, + 6, + 42, + 249, + 0, // Skip to: 104527 + /* 40741 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 35, + 249, + 0, // Skip to: 104527 + /* 40748 */ MCD_OPC_Decode, + 205, + 28, + 172, + 1, // Opcode: PRFB_D_UXTW_SCALED + /* 40753 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 40775 + /* 40758 */ MCD_OPC_CheckPredicate, + 6, + 20, + 249, + 0, // Skip to: 104527 + /* 40763 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 13, + 249, + 0, // Skip to: 104527 + /* 40770 */ MCD_OPC_Decode, + 223, + 28, + 172, + 1, // Opcode: PRFH_D_UXTW_SCALED + /* 40775 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 40797 + /* 40780 */ MCD_OPC_CheckPredicate, + 6, + 254, + 248, + 0, // Skip to: 104527 + /* 40785 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 247, + 248, + 0, // Skip to: 104527 + /* 40792 */ MCD_OPC_Decode, + 238, + 28, + 172, + 1, // Opcode: PRFW_D_UXTW_SCALED + /* 40797 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 40819 + /* 40802 */ MCD_OPC_CheckPredicate, + 6, + 232, + 248, + 0, // Skip to: 104527 + /* 40807 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 225, + 248, + 0, // Skip to: 104527 + /* 40814 */ MCD_OPC_Decode, + 214, + 28, + 172, + 1, // Opcode: PRFD_D_UXTW_SCALED + /* 40819 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 40834 + /* 40824 */ MCD_OPC_CheckPredicate, + 6, + 210, + 248, + 0, // Skip to: 104527 + /* 40829 */ MCD_OPC_Decode, + 154, + 20, + 177, + 1, // Opcode: GLD1SB_D_IMM_REAL + /* 40834 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 40849 + /* 40839 */ MCD_OPC_CheckPredicate, + 6, + 195, + 248, + 0, // Skip to: 104527 + /* 40844 */ MCD_OPC_Decode, + 218, + 20, + 177, + 1, // Opcode: GLDFF1SB_D_IMM_REAL + /* 40849 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 40864 + /* 40854 */ MCD_OPC_CheckPredicate, + 6, + 180, + 248, + 0, // Skip to: 104527 + /* 40859 */ MCD_OPC_Decode, + 128, + 20, + 177, + 1, // Opcode: GLD1B_D_IMM_REAL + /* 40864 */ MCD_OPC_FilterValue, + 7, + 170, + 248, + 0, // Skip to: 104527 + /* 40869 */ MCD_OPC_CheckPredicate, + 6, + 165, + 248, + 0, // Skip to: 104527 + /* 40874 */ MCD_OPC_Decode, + 192, + 20, + 177, + 1, // Opcode: GLDFF1B_D_IMM_REAL + /* 40879 */ MCD_OPC_FilterValue, + 2, + 123, + 0, + 0, // Skip to: 41007 + /* 40884 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 40887 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 40902 + /* 40892 */ MCD_OPC_CheckPredicate, + 6, + 142, + 248, + 0, // Skip to: 104527 + /* 40897 */ MCD_OPC_Decode, + 156, + 20, + 171, + 1, // Opcode: GLD1SB_D_SXTW_REAL + /* 40902 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 40917 + /* 40907 */ MCD_OPC_CheckPredicate, + 6, + 127, + 248, + 0, // Skip to: 104527 + /* 40912 */ MCD_OPC_Decode, + 220, + 20, + 171, + 1, // Opcode: GLDFF1SB_D_SXTW_REAL + /* 40917 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 40932 + /* 40922 */ MCD_OPC_CheckPredicate, + 6, + 112, + 248, + 0, // Skip to: 104527 + /* 40927 */ MCD_OPC_Decode, + 130, + 20, + 171, + 1, // Opcode: GLD1B_D_SXTW_REAL + /* 40932 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 40947 + /* 40937 */ MCD_OPC_CheckPredicate, + 6, + 97, + 248, + 0, // Skip to: 104527 + /* 40942 */ MCD_OPC_Decode, + 194, + 20, + 171, + 1, // Opcode: GLDFF1B_D_SXTW_REAL + /* 40947 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 40962 + /* 40952 */ MCD_OPC_CheckPredicate, + 6, + 82, + 248, + 0, // Skip to: 104527 + /* 40957 */ MCD_OPC_Decode, + 155, + 20, + 171, + 1, // Opcode: GLD1SB_D_REAL + /* 40962 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 40977 + /* 40967 */ MCD_OPC_CheckPredicate, + 6, + 67, + 248, + 0, // Skip to: 104527 + /* 40972 */ MCD_OPC_Decode, + 219, + 20, + 171, + 1, // Opcode: GLDFF1SB_D_REAL + /* 40977 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 40992 + /* 40982 */ MCD_OPC_CheckPredicate, + 6, + 52, + 248, + 0, // Skip to: 104527 + /* 40987 */ MCD_OPC_Decode, + 129, + 20, + 171, + 1, // Opcode: GLD1B_D_REAL + /* 40992 */ MCD_OPC_FilterValue, + 7, + 42, + 248, + 0, // Skip to: 104527 + /* 40997 */ MCD_OPC_CheckPredicate, + 6, + 37, + 248, + 0, // Skip to: 104527 + /* 41002 */ MCD_OPC_Decode, + 193, + 20, + 171, + 1, // Opcode: GLDFF1B_D_REAL + /* 41007 */ MCD_OPC_FilterValue, + 3, + 179, + 0, + 0, // Skip to: 41191 + /* 41012 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 41015 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 41037 + /* 41020 */ MCD_OPC_CheckPredicate, + 6, + 14, + 248, + 0, // Skip to: 104527 + /* 41025 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 7, + 248, + 0, // Skip to: 104527 + /* 41032 */ MCD_OPC_Decode, + 204, + 28, + 172, + 1, // Opcode: PRFB_D_SXTW_SCALED + /* 41037 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 41059 + /* 41042 */ MCD_OPC_CheckPredicate, + 6, + 248, + 247, + 0, // Skip to: 104527 + /* 41047 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 241, + 247, + 0, // Skip to: 104527 + /* 41054 */ MCD_OPC_Decode, + 222, + 28, + 172, + 1, // Opcode: PRFH_D_SXTW_SCALED + /* 41059 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 41081 + /* 41064 */ MCD_OPC_CheckPredicate, + 6, + 226, + 247, + 0, // Skip to: 104527 + /* 41069 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 219, + 247, + 0, // Skip to: 104527 + /* 41076 */ MCD_OPC_Decode, + 237, + 28, + 172, + 1, // Opcode: PRFW_D_SXTW_SCALED + /* 41081 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 41103 + /* 41086 */ MCD_OPC_CheckPredicate, + 6, + 204, + 247, + 0, // Skip to: 104527 + /* 41091 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 197, + 247, + 0, // Skip to: 104527 + /* 41098 */ MCD_OPC_Decode, + 213, + 28, + 172, + 1, // Opcode: PRFD_D_SXTW_SCALED + /* 41103 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 41125 + /* 41108 */ MCD_OPC_CheckPredicate, + 6, + 182, + 247, + 0, // Skip to: 104527 + /* 41113 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 175, + 247, + 0, // Skip to: 104527 + /* 41120 */ MCD_OPC_Decode, + 203, + 28, + 172, + 1, // Opcode: PRFB_D_SCALED + /* 41125 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 41147 + /* 41130 */ MCD_OPC_CheckPredicate, + 6, + 160, + 247, + 0, // Skip to: 104527 + /* 41135 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 153, + 247, + 0, // Skip to: 104527 + /* 41142 */ MCD_OPC_Decode, + 221, + 28, + 172, + 1, // Opcode: PRFH_D_SCALED + /* 41147 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 41169 + /* 41152 */ MCD_OPC_CheckPredicate, + 6, + 138, + 247, + 0, // Skip to: 104527 + /* 41157 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 131, + 247, + 0, // Skip to: 104527 + /* 41164 */ MCD_OPC_Decode, + 236, + 28, + 172, + 1, // Opcode: PRFW_D_SCALED + /* 41169 */ MCD_OPC_FilterValue, + 7, + 121, + 247, + 0, // Skip to: 104527 + /* 41174 */ MCD_OPC_CheckPredicate, + 6, + 116, + 247, + 0, // Skip to: 104527 + /* 41179 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 109, + 247, + 0, // Skip to: 104527 + /* 41186 */ MCD_OPC_Decode, + 212, + 28, + 172, + 1, // Opcode: PRFD_D_SCALED + /* 41191 */ MCD_OPC_FilterValue, + 4, + 115, + 0, + 0, // Skip to: 41311 + /* 41196 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 41199 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 41214 + /* 41204 */ MCD_OPC_CheckPredicate, + 6, + 86, + 247, + 0, // Skip to: 104527 + /* 41209 */ MCD_OPC_Decode, + 166, + 20, + 171, + 1, // Opcode: GLD1SH_D_UXTW_REAL + /* 41214 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 41229 + /* 41219 */ MCD_OPC_CheckPredicate, + 6, + 71, + 247, + 0, // Skip to: 104527 + /* 41224 */ MCD_OPC_Decode, + 230, + 20, + 171, + 1, // Opcode: GLDFF1SH_D_UXTW_REAL + /* 41229 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 41244 + /* 41234 */ MCD_OPC_CheckPredicate, + 6, + 56, + 247, + 0, // Skip to: 104527 + /* 41239 */ MCD_OPC_Decode, + 147, + 20, + 171, + 1, // Opcode: GLD1H_D_UXTW_REAL + /* 41244 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 41259 + /* 41249 */ MCD_OPC_CheckPredicate, + 6, + 41, + 247, + 0, // Skip to: 104527 + /* 41254 */ MCD_OPC_Decode, + 211, + 20, + 171, + 1, // Opcode: GLDFF1H_D_UXTW_REAL + /* 41259 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 41274 + /* 41264 */ MCD_OPC_CheckPredicate, + 10, + 26, + 247, + 0, // Skip to: 104527 + /* 41269 */ MCD_OPC_Decode, + 253, + 24, + 176, + 1, // Opcode: LDNT1SH_ZZR_D_REAL + /* 41274 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 41289 + /* 41279 */ MCD_OPC_CheckPredicate, + 10, + 11, + 247, + 0, // Skip to: 104527 + /* 41284 */ MCD_OPC_Decode, + 249, + 24, + 176, + 1, // Opcode: LDNT1H_ZZR_D_REAL + /* 41289 */ MCD_OPC_FilterValue, + 7, + 1, + 247, + 0, // Skip to: 104527 + /* 41294 */ MCD_OPC_CheckPredicate, + 6, + 252, + 246, + 0, // Skip to: 104527 + /* 41299 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 245, + 246, + 0, // Skip to: 104527 + /* 41306 */ MCD_OPC_Decode, + 220, + 28, + 180, + 1, // Opcode: PRFH_D_PZI + /* 41311 */ MCD_OPC_FilterValue, + 5, + 123, + 0, + 0, // Skip to: 41439 + /* 41316 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 41319 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 41334 + /* 41324 */ MCD_OPC_CheckPredicate, + 6, + 222, + 246, + 0, // Skip to: 104527 + /* 41329 */ MCD_OPC_Decode, + 167, + 20, + 171, + 1, // Opcode: GLD1SH_D_UXTW_SCALED_REAL + /* 41334 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 41349 + /* 41339 */ MCD_OPC_CheckPredicate, + 6, + 207, + 246, + 0, // Skip to: 104527 + /* 41344 */ MCD_OPC_Decode, + 231, + 20, + 171, + 1, // Opcode: GLDFF1SH_D_UXTW_SCALED_REAL + /* 41349 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 41364 + /* 41354 */ MCD_OPC_CheckPredicate, + 6, + 192, + 246, + 0, // Skip to: 104527 + /* 41359 */ MCD_OPC_Decode, + 148, + 20, + 171, + 1, // Opcode: GLD1H_D_UXTW_SCALED_REAL + /* 41364 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 41379 + /* 41369 */ MCD_OPC_CheckPredicate, + 6, + 177, + 246, + 0, // Skip to: 104527 + /* 41374 */ MCD_OPC_Decode, + 212, + 20, + 171, + 1, // Opcode: GLDFF1H_D_UXTW_SCALED_REAL + /* 41379 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 41394 + /* 41384 */ MCD_OPC_CheckPredicate, + 6, + 162, + 246, + 0, // Skip to: 104527 + /* 41389 */ MCD_OPC_Decode, + 161, + 20, + 177, + 1, // Opcode: GLD1SH_D_IMM_REAL + /* 41394 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 41409 + /* 41399 */ MCD_OPC_CheckPredicate, + 6, + 147, + 246, + 0, // Skip to: 104527 + /* 41404 */ MCD_OPC_Decode, + 225, + 20, + 177, + 1, // Opcode: GLDFF1SH_D_IMM_REAL + /* 41409 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 41424 + /* 41414 */ MCD_OPC_CheckPredicate, + 6, + 132, + 246, + 0, // Skip to: 104527 + /* 41419 */ MCD_OPC_Decode, + 142, + 20, + 177, + 1, // Opcode: GLD1H_D_IMM_REAL + /* 41424 */ MCD_OPC_FilterValue, + 7, + 122, + 246, + 0, // Skip to: 104527 + /* 41429 */ MCD_OPC_CheckPredicate, + 6, + 117, + 246, + 0, // Skip to: 104527 + /* 41434 */ MCD_OPC_Decode, + 206, + 20, + 177, + 1, // Opcode: GLDFF1H_D_IMM_REAL + /* 41439 */ MCD_OPC_FilterValue, + 6, + 123, + 0, + 0, // Skip to: 41567 + /* 41444 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 41447 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 41462 + /* 41452 */ MCD_OPC_CheckPredicate, + 6, + 94, + 246, + 0, // Skip to: 104527 + /* 41457 */ MCD_OPC_Decode, + 164, + 20, + 171, + 1, // Opcode: GLD1SH_D_SXTW_REAL + /* 41462 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 41477 + /* 41467 */ MCD_OPC_CheckPredicate, + 6, + 79, + 246, + 0, // Skip to: 104527 + /* 41472 */ MCD_OPC_Decode, + 228, + 20, + 171, + 1, // Opcode: GLDFF1SH_D_SXTW_REAL + /* 41477 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 41492 + /* 41482 */ MCD_OPC_CheckPredicate, + 6, + 64, + 246, + 0, // Skip to: 104527 + /* 41487 */ MCD_OPC_Decode, + 145, + 20, + 171, + 1, // Opcode: GLD1H_D_SXTW_REAL + /* 41492 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 41507 + /* 41497 */ MCD_OPC_CheckPredicate, + 6, + 49, + 246, + 0, // Skip to: 104527 + /* 41502 */ MCD_OPC_Decode, + 209, + 20, + 171, + 1, // Opcode: GLDFF1H_D_SXTW_REAL + /* 41507 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 41522 + /* 41512 */ MCD_OPC_CheckPredicate, + 6, + 34, + 246, + 0, // Skip to: 104527 + /* 41517 */ MCD_OPC_Decode, + 162, + 20, + 171, + 1, // Opcode: GLD1SH_D_REAL + /* 41522 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 41537 + /* 41527 */ MCD_OPC_CheckPredicate, + 6, + 19, + 246, + 0, // Skip to: 104527 + /* 41532 */ MCD_OPC_Decode, + 226, + 20, + 171, + 1, // Opcode: GLDFF1SH_D_REAL + /* 41537 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 41552 + /* 41542 */ MCD_OPC_CheckPredicate, + 6, + 4, + 246, + 0, // Skip to: 104527 + /* 41547 */ MCD_OPC_Decode, + 143, + 20, + 171, + 1, // Opcode: GLD1H_D_REAL + /* 41552 */ MCD_OPC_FilterValue, + 7, + 250, + 245, + 0, // Skip to: 104527 + /* 41557 */ MCD_OPC_CheckPredicate, + 6, + 245, + 245, + 0, // Skip to: 104527 + /* 41562 */ MCD_OPC_Decode, + 207, + 20, + 171, + 1, // Opcode: GLDFF1H_D_REAL + /* 41567 */ MCD_OPC_FilterValue, + 7, + 123, + 0, + 0, // Skip to: 41695 + /* 41572 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 41575 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 41590 + /* 41580 */ MCD_OPC_CheckPredicate, + 6, + 222, + 245, + 0, // Skip to: 104527 + /* 41585 */ MCD_OPC_Decode, + 165, + 20, + 171, + 1, // Opcode: GLD1SH_D_SXTW_SCALED_REAL + /* 41590 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 41605 + /* 41595 */ MCD_OPC_CheckPredicate, + 6, + 207, + 245, + 0, // Skip to: 104527 + /* 41600 */ MCD_OPC_Decode, + 229, + 20, + 171, + 1, // Opcode: GLDFF1SH_D_SXTW_SCALED_REAL + /* 41605 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 41620 + /* 41610 */ MCD_OPC_CheckPredicate, + 6, + 192, + 245, + 0, // Skip to: 104527 + /* 41615 */ MCD_OPC_Decode, + 146, + 20, + 171, + 1, // Opcode: GLD1H_D_SXTW_SCALED_REAL + /* 41620 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 41635 + /* 41625 */ MCD_OPC_CheckPredicate, + 6, + 177, + 245, + 0, // Skip to: 104527 + /* 41630 */ MCD_OPC_Decode, + 210, + 20, + 171, + 1, // Opcode: GLDFF1H_D_SXTW_SCALED_REAL + /* 41635 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 41650 + /* 41640 */ MCD_OPC_CheckPredicate, + 6, + 162, + 245, + 0, // Skip to: 104527 + /* 41645 */ MCD_OPC_Decode, + 163, + 20, + 171, + 1, // Opcode: GLD1SH_D_SCALED_REAL + /* 41650 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 41665 + /* 41655 */ MCD_OPC_CheckPredicate, + 6, + 147, + 245, + 0, // Skip to: 104527 + /* 41660 */ MCD_OPC_Decode, + 227, + 20, + 171, + 1, // Opcode: GLDFF1SH_D_SCALED_REAL + /* 41665 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 41680 + /* 41670 */ MCD_OPC_CheckPredicate, + 6, + 132, + 245, + 0, // Skip to: 104527 + /* 41675 */ MCD_OPC_Decode, + 144, + 20, + 171, + 1, // Opcode: GLD1H_D_SCALED_REAL + /* 41680 */ MCD_OPC_FilterValue, + 7, + 122, + 245, + 0, // Skip to: 104527 + /* 41685 */ MCD_OPC_CheckPredicate, + 6, + 117, + 245, + 0, // Skip to: 104527 + /* 41690 */ MCD_OPC_Decode, + 208, + 20, + 171, + 1, // Opcode: GLDFF1H_D_SCALED_REAL + /* 41695 */ MCD_OPC_FilterValue, + 8, + 115, + 0, + 0, // Skip to: 41815 + /* 41700 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 41703 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 41718 + /* 41708 */ MCD_OPC_CheckPredicate, + 6, + 94, + 245, + 0, // Skip to: 104527 + /* 41713 */ MCD_OPC_Decode, + 178, + 20, + 171, + 1, // Opcode: GLD1SW_D_UXTW_REAL + /* 41718 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 41733 + /* 41723 */ MCD_OPC_CheckPredicate, + 6, + 79, + 245, + 0, // Skip to: 104527 + /* 41728 */ MCD_OPC_Decode, + 242, + 20, + 171, + 1, // Opcode: GLDFF1SW_D_UXTW_REAL + /* 41733 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 41748 + /* 41738 */ MCD_OPC_CheckPredicate, + 6, + 64, + 245, + 0, // Skip to: 104527 + /* 41743 */ MCD_OPC_Decode, + 185, + 20, + 171, + 1, // Opcode: GLD1W_D_UXTW_REAL + /* 41748 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 41763 + /* 41753 */ MCD_OPC_CheckPredicate, + 6, + 49, + 245, + 0, // Skip to: 104527 + /* 41758 */ MCD_OPC_Decode, + 249, + 20, + 171, + 1, // Opcode: GLDFF1W_D_UXTW_REAL + /* 41763 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 41778 + /* 41768 */ MCD_OPC_CheckPredicate, + 10, + 34, + 245, + 0, // Skip to: 104527 + /* 41773 */ MCD_OPC_Decode, + 255, + 24, + 176, + 1, // Opcode: LDNT1SW_ZZR_D_REAL + /* 41778 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 41793 + /* 41783 */ MCD_OPC_CheckPredicate, + 10, + 19, + 245, + 0, // Skip to: 104527 + /* 41788 */ MCD_OPC_Decode, + 130, + 25, + 176, + 1, // Opcode: LDNT1W_ZZR_D_REAL + /* 41793 */ MCD_OPC_FilterValue, + 7, + 9, + 245, + 0, // Skip to: 104527 + /* 41798 */ MCD_OPC_CheckPredicate, + 6, + 4, + 245, + 0, // Skip to: 104527 + /* 41803 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 253, + 244, + 0, // Skip to: 104527 + /* 41810 */ MCD_OPC_Decode, + 235, + 28, + 180, + 1, // Opcode: PRFW_D_PZI + /* 41815 */ MCD_OPC_FilterValue, + 9, + 123, + 0, + 0, // Skip to: 41943 + /* 41820 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 41823 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 41838 + /* 41828 */ MCD_OPC_CheckPredicate, + 6, + 230, + 244, + 0, // Skip to: 104527 + /* 41833 */ MCD_OPC_Decode, + 179, + 20, + 171, + 1, // Opcode: GLD1SW_D_UXTW_SCALED_REAL + /* 41838 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 41853 + /* 41843 */ MCD_OPC_CheckPredicate, + 6, + 215, + 244, + 0, // Skip to: 104527 + /* 41848 */ MCD_OPC_Decode, + 243, + 20, + 171, + 1, // Opcode: GLDFF1SW_D_UXTW_SCALED_REAL + /* 41853 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 41868 + /* 41858 */ MCD_OPC_CheckPredicate, + 6, + 200, + 244, + 0, // Skip to: 104527 + /* 41863 */ MCD_OPC_Decode, + 186, + 20, + 171, + 1, // Opcode: GLD1W_D_UXTW_SCALED_REAL + /* 41868 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 41883 + /* 41873 */ MCD_OPC_CheckPredicate, + 6, + 185, + 244, + 0, // Skip to: 104527 + /* 41878 */ MCD_OPC_Decode, + 250, + 20, + 171, + 1, // Opcode: GLDFF1W_D_UXTW_SCALED_REAL + /* 41883 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 41898 + /* 41888 */ MCD_OPC_CheckPredicate, + 6, + 170, + 244, + 0, // Skip to: 104527 + /* 41893 */ MCD_OPC_Decode, + 173, + 20, + 177, + 1, // Opcode: GLD1SW_D_IMM_REAL + /* 41898 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 41913 + /* 41903 */ MCD_OPC_CheckPredicate, + 6, + 155, + 244, + 0, // Skip to: 104527 + /* 41908 */ MCD_OPC_Decode, + 237, + 20, + 177, + 1, // Opcode: GLDFF1SW_D_IMM_REAL + /* 41913 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 41928 + /* 41918 */ MCD_OPC_CheckPredicate, + 6, + 140, + 244, + 0, // Skip to: 104527 + /* 41923 */ MCD_OPC_Decode, + 180, + 20, + 177, + 1, // Opcode: GLD1W_D_IMM_REAL + /* 41928 */ MCD_OPC_FilterValue, + 7, + 130, + 244, + 0, // Skip to: 104527 + /* 41933 */ MCD_OPC_CheckPredicate, + 6, + 125, + 244, + 0, // Skip to: 104527 + /* 41938 */ MCD_OPC_Decode, + 244, + 20, + 177, + 1, // Opcode: GLDFF1W_D_IMM_REAL + /* 41943 */ MCD_OPC_FilterValue, + 10, + 123, + 0, + 0, // Skip to: 42071 + /* 41948 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 41951 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 41966 + /* 41956 */ MCD_OPC_CheckPredicate, + 6, + 102, + 244, + 0, // Skip to: 104527 + /* 41961 */ MCD_OPC_Decode, + 176, + 20, + 171, + 1, // Opcode: GLD1SW_D_SXTW_REAL + /* 41966 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 41981 + /* 41971 */ MCD_OPC_CheckPredicate, + 6, + 87, + 244, + 0, // Skip to: 104527 + /* 41976 */ MCD_OPC_Decode, + 240, + 20, + 171, + 1, // Opcode: GLDFF1SW_D_SXTW_REAL + /* 41981 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 41996 + /* 41986 */ MCD_OPC_CheckPredicate, + 6, + 72, + 244, + 0, // Skip to: 104527 + /* 41991 */ MCD_OPC_Decode, + 183, + 20, + 171, + 1, // Opcode: GLD1W_D_SXTW_REAL + /* 41996 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 42011 + /* 42001 */ MCD_OPC_CheckPredicate, + 6, + 57, + 244, + 0, // Skip to: 104527 + /* 42006 */ MCD_OPC_Decode, + 247, + 20, + 171, + 1, // Opcode: GLDFF1W_D_SXTW_REAL + /* 42011 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 42026 + /* 42016 */ MCD_OPC_CheckPredicate, + 6, + 42, + 244, + 0, // Skip to: 104527 + /* 42021 */ MCD_OPC_Decode, + 174, + 20, + 171, + 1, // Opcode: GLD1SW_D_REAL + /* 42026 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 42041 + /* 42031 */ MCD_OPC_CheckPredicate, + 6, + 27, + 244, + 0, // Skip to: 104527 + /* 42036 */ MCD_OPC_Decode, + 238, + 20, + 171, + 1, // Opcode: GLDFF1SW_D_REAL + /* 42041 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 42056 + /* 42046 */ MCD_OPC_CheckPredicate, + 6, + 12, + 244, + 0, // Skip to: 104527 + /* 42051 */ MCD_OPC_Decode, + 181, + 20, + 171, + 1, // Opcode: GLD1W_D_REAL + /* 42056 */ MCD_OPC_FilterValue, + 7, + 2, + 244, + 0, // Skip to: 104527 + /* 42061 */ MCD_OPC_CheckPredicate, + 6, + 253, + 243, + 0, // Skip to: 104527 + /* 42066 */ MCD_OPC_Decode, + 245, + 20, + 171, + 1, // Opcode: GLDFF1W_D_REAL + /* 42071 */ MCD_OPC_FilterValue, + 11, + 123, + 0, + 0, // Skip to: 42199 + /* 42076 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 42079 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 42094 + /* 42084 */ MCD_OPC_CheckPredicate, + 6, + 230, + 243, + 0, // Skip to: 104527 + /* 42089 */ MCD_OPC_Decode, + 177, + 20, + 171, + 1, // Opcode: GLD1SW_D_SXTW_SCALED_REAL + /* 42094 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 42109 + /* 42099 */ MCD_OPC_CheckPredicate, + 6, + 215, + 243, + 0, // Skip to: 104527 + /* 42104 */ MCD_OPC_Decode, + 241, + 20, + 171, + 1, // Opcode: GLDFF1SW_D_SXTW_SCALED_REAL + /* 42109 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 42124 + /* 42114 */ MCD_OPC_CheckPredicate, + 6, + 200, + 243, + 0, // Skip to: 104527 + /* 42119 */ MCD_OPC_Decode, + 184, + 20, + 171, + 1, // Opcode: GLD1W_D_SXTW_SCALED_REAL + /* 42124 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 42139 + /* 42129 */ MCD_OPC_CheckPredicate, + 6, + 185, + 243, + 0, // Skip to: 104527 + /* 42134 */ MCD_OPC_Decode, + 248, + 20, + 171, + 1, // Opcode: GLDFF1W_D_SXTW_SCALED_REAL + /* 42139 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 42154 + /* 42144 */ MCD_OPC_CheckPredicate, + 6, + 170, + 243, + 0, // Skip to: 104527 + /* 42149 */ MCD_OPC_Decode, + 175, + 20, + 171, + 1, // Opcode: GLD1SW_D_SCALED_REAL + /* 42154 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 42169 + /* 42159 */ MCD_OPC_CheckPredicate, + 6, + 155, + 243, + 0, // Skip to: 104527 + /* 42164 */ MCD_OPC_Decode, + 239, + 20, + 171, + 1, // Opcode: GLDFF1SW_D_SCALED_REAL + /* 42169 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 42184 + /* 42174 */ MCD_OPC_CheckPredicate, + 6, + 140, + 243, + 0, // Skip to: 104527 + /* 42179 */ MCD_OPC_Decode, + 182, + 20, + 171, + 1, // Opcode: GLD1W_D_SCALED_REAL + /* 42184 */ MCD_OPC_FilterValue, + 7, + 130, + 243, + 0, // Skip to: 104527 + /* 42189 */ MCD_OPC_CheckPredicate, + 6, + 125, + 243, + 0, // Skip to: 104527 + /* 42194 */ MCD_OPC_Decode, + 246, + 20, + 171, + 1, // Opcode: GLDFF1W_D_SCALED_REAL + /* 42199 */ MCD_OPC_FilterValue, + 12, + 70, + 0, + 0, // Skip to: 42274 + /* 42204 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 42207 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 42222 + /* 42212 */ MCD_OPC_CheckPredicate, + 6, + 102, + 243, + 0, // Skip to: 104527 + /* 42217 */ MCD_OPC_Decode, + 140, + 20, + 171, + 1, // Opcode: GLD1D_UXTW_REAL + /* 42222 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 42237 + /* 42227 */ MCD_OPC_CheckPredicate, + 6, + 87, + 243, + 0, // Skip to: 104527 + /* 42232 */ MCD_OPC_Decode, + 204, + 20, + 171, + 1, // Opcode: GLDFF1D_UXTW_REAL + /* 42237 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 42252 + /* 42242 */ MCD_OPC_CheckPredicate, + 10, + 72, + 243, + 0, // Skip to: 104527 + /* 42247 */ MCD_OPC_Decode, + 246, + 24, + 176, + 1, // Opcode: LDNT1D_ZZR_D_REAL + /* 42252 */ MCD_OPC_FilterValue, + 7, + 62, + 243, + 0, // Skip to: 104527 + /* 42257 */ MCD_OPC_CheckPredicate, + 6, + 57, + 243, + 0, // Skip to: 104527 + /* 42262 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 50, + 243, + 0, // Skip to: 104527 + /* 42269 */ MCD_OPC_Decode, + 211, + 28, + 180, + 1, // Opcode: PRFD_D_PZI + /* 42274 */ MCD_OPC_FilterValue, + 13, + 63, + 0, + 0, // Skip to: 42342 + /* 42279 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 42282 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 42297 + /* 42287 */ MCD_OPC_CheckPredicate, + 6, + 27, + 243, + 0, // Skip to: 104527 + /* 42292 */ MCD_OPC_Decode, + 141, + 20, + 171, + 1, // Opcode: GLD1D_UXTW_SCALED_REAL + /* 42297 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 42312 + /* 42302 */ MCD_OPC_CheckPredicate, + 6, + 12, + 243, + 0, // Skip to: 104527 + /* 42307 */ MCD_OPC_Decode, + 205, + 20, + 171, + 1, // Opcode: GLDFF1D_UXTW_SCALED_REAL + /* 42312 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 42327 + /* 42317 */ MCD_OPC_CheckPredicate, + 6, + 253, + 242, + 0, // Skip to: 104527 + /* 42322 */ MCD_OPC_Decode, + 135, + 20, + 177, + 1, // Opcode: GLD1D_IMM_REAL + /* 42327 */ MCD_OPC_FilterValue, + 7, + 243, + 242, + 0, // Skip to: 104527 + /* 42332 */ MCD_OPC_CheckPredicate, + 6, + 238, + 242, + 0, // Skip to: 104527 + /* 42337 */ MCD_OPC_Decode, + 199, + 20, + 177, + 1, // Opcode: GLDFF1D_IMM_REAL + /* 42342 */ MCD_OPC_FilterValue, + 14, + 63, + 0, + 0, // Skip to: 42410 + /* 42347 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 42350 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 42365 + /* 42355 */ MCD_OPC_CheckPredicate, + 6, + 215, + 242, + 0, // Skip to: 104527 + /* 42360 */ MCD_OPC_Decode, + 138, + 20, + 171, + 1, // Opcode: GLD1D_SXTW_REAL + /* 42365 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 42380 + /* 42370 */ MCD_OPC_CheckPredicate, + 6, + 200, + 242, + 0, // Skip to: 104527 + /* 42375 */ MCD_OPC_Decode, + 202, + 20, + 171, + 1, // Opcode: GLDFF1D_SXTW_REAL + /* 42380 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 42395 + /* 42385 */ MCD_OPC_CheckPredicate, + 6, + 185, + 242, + 0, // Skip to: 104527 + /* 42390 */ MCD_OPC_Decode, + 136, + 20, + 171, + 1, // Opcode: GLD1D_REAL + /* 42395 */ MCD_OPC_FilterValue, + 7, + 175, + 242, + 0, // Skip to: 104527 + /* 42400 */ MCD_OPC_CheckPredicate, + 6, + 170, + 242, + 0, // Skip to: 104527 + /* 42405 */ MCD_OPC_Decode, + 200, + 20, + 171, + 1, // Opcode: GLDFF1D_REAL + /* 42410 */ MCD_OPC_FilterValue, + 15, + 160, + 242, + 0, // Skip to: 104527 + /* 42415 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 42418 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 42433 + /* 42423 */ MCD_OPC_CheckPredicate, + 6, + 147, + 242, + 0, // Skip to: 104527 + /* 42428 */ MCD_OPC_Decode, + 139, + 20, + 171, + 1, // Opcode: GLD1D_SXTW_SCALED_REAL + /* 42433 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 42448 + /* 42438 */ MCD_OPC_CheckPredicate, + 6, + 132, + 242, + 0, // Skip to: 104527 + /* 42443 */ MCD_OPC_Decode, + 203, + 20, + 171, + 1, // Opcode: GLDFF1D_SXTW_SCALED_REAL + /* 42448 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 42463 + /* 42453 */ MCD_OPC_CheckPredicate, + 6, + 117, + 242, + 0, // Skip to: 104527 + /* 42458 */ MCD_OPC_Decode, + 137, + 20, + 171, + 1, // Opcode: GLD1D_SCALED_REAL + /* 42463 */ MCD_OPC_FilterValue, + 7, + 107, + 242, + 0, // Skip to: 104527 + /* 42468 */ MCD_OPC_CheckPredicate, + 6, + 102, + 242, + 0, // Skip to: 104527 + /* 42473 */ MCD_OPC_Decode, + 201, + 20, + 171, + 1, // Opcode: GLDFF1D_SCALED_REAL + /* 42478 */ MCD_OPC_FilterValue, + 7, + 92, + 242, + 0, // Skip to: 104527 + /* 42483 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 42486 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 42515 + /* 42491 */ MCD_OPC_CheckPredicate, + 3, + 79, + 242, + 0, // Skip to: 104527 + /* 42496 */ MCD_OPC_CheckField, + 22, + 4, + 6, + 72, + 242, + 0, // Skip to: 104527 + /* 42503 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 65, + 242, + 0, // Skip to: 104527 + /* 42510 */ MCD_OPC_Decode, + 138, + 40, + 173, + 1, // Opcode: STR_PXI + /* 42515 */ MCD_OPC_FilterValue, + 1, + 108, + 0, + 0, // Skip to: 42628 + /* 42520 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 42523 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 42538 + /* 42528 */ MCD_OPC_CheckPredicate, + 10, + 42, + 242, + 0, // Skip to: 104527 + /* 42533 */ MCD_OPC_Decode, + 193, + 39, + 176, + 1, // Opcode: STNT1B_ZZR_D_REAL + /* 42538 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 42553 + /* 42543 */ MCD_OPC_CheckPredicate, + 10, + 27, + 242, + 0, // Skip to: 104527 + /* 42548 */ MCD_OPC_Decode, + 194, + 39, + 176, + 1, // Opcode: STNT1B_ZZR_S_REAL + /* 42553 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 42568 + /* 42558 */ MCD_OPC_CheckPredicate, + 10, + 12, + 242, + 0, // Skip to: 104527 + /* 42563 */ MCD_OPC_Decode, + 200, + 39, + 176, + 1, // Opcode: STNT1H_ZZR_D_REAL + /* 42568 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 42583 + /* 42573 */ MCD_OPC_CheckPredicate, + 10, + 253, + 241, + 0, // Skip to: 104527 + /* 42578 */ MCD_OPC_Decode, + 201, + 39, + 176, + 1, // Opcode: STNT1H_ZZR_S_REAL + /* 42583 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 42598 + /* 42588 */ MCD_OPC_CheckPredicate, + 10, + 238, + 241, + 0, // Skip to: 104527 + /* 42593 */ MCD_OPC_Decode, + 204, + 39, + 176, + 1, // Opcode: STNT1W_ZZR_D_REAL + /* 42598 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 42613 + /* 42603 */ MCD_OPC_CheckPredicate, + 10, + 223, + 241, + 0, // Skip to: 104527 + /* 42608 */ MCD_OPC_Decode, + 205, + 39, + 176, + 1, // Opcode: STNT1W_ZZR_S_REAL + /* 42613 */ MCD_OPC_FilterValue, + 12, + 213, + 241, + 0, // Skip to: 104527 + /* 42618 */ MCD_OPC_CheckPredicate, + 10, + 208, + 241, + 0, // Skip to: 104527 + /* 42623 */ MCD_OPC_Decode, + 197, + 39, + 176, + 1, // Opcode: STNT1D_ZZR_D_REAL + /* 42628 */ MCD_OPC_FilterValue, + 2, + 214, + 0, + 0, // Skip to: 42847 + /* 42633 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 42636 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 42674 + /* 42641 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 42644 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 42659 + /* 42649 */ MCD_OPC_CheckPredicate, + 3, + 177, + 241, + 0, // Skip to: 104527 + /* 42654 */ MCD_OPC_Decode, + 219, + 37, + 181, + 1, // Opcode: ST1B + /* 42659 */ MCD_OPC_FilterValue, + 1, + 167, + 241, + 0, // Skip to: 104527 + /* 42664 */ MCD_OPC_CheckPredicate, + 3, + 162, + 241, + 0, // Skip to: 104527 + /* 42669 */ MCD_OPC_Decode, + 222, + 37, + 181, + 1, // Opcode: ST1B_H + /* 42674 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 42712 + /* 42679 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 42682 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 42697 + /* 42687 */ MCD_OPC_CheckPredicate, + 3, + 139, + 241, + 0, // Skip to: 104527 + /* 42692 */ MCD_OPC_Decode, + 225, + 37, + 181, + 1, // Opcode: ST1B_S + /* 42697 */ MCD_OPC_FilterValue, + 1, + 129, + 241, + 0, // Skip to: 104527 + /* 42702 */ MCD_OPC_CheckPredicate, + 3, + 124, + 241, + 0, // Skip to: 104527 + /* 42707 */ MCD_OPC_Decode, + 220, + 37, + 181, + 1, // Opcode: ST1B_D + /* 42712 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 42734 + /* 42717 */ MCD_OPC_CheckPredicate, + 3, + 109, + 241, + 0, // Skip to: 104527 + /* 42722 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 102, + 241, + 0, // Skip to: 104527 + /* 42729 */ MCD_OPC_Decode, + 245, + 37, + 181, + 1, // Opcode: ST1H + /* 42734 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 42772 + /* 42739 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 42742 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 42757 + /* 42747 */ MCD_OPC_CheckPredicate, + 3, + 79, + 241, + 0, // Skip to: 104527 + /* 42752 */ MCD_OPC_Decode, + 249, + 37, + 181, + 1, // Opcode: ST1H_S + /* 42757 */ MCD_OPC_FilterValue, + 1, + 69, + 241, + 0, // Skip to: 104527 + /* 42762 */ MCD_OPC_CheckPredicate, + 3, + 64, + 241, + 0, // Skip to: 104527 + /* 42767 */ MCD_OPC_Decode, + 246, + 37, + 181, + 1, // Opcode: ST1H_D + /* 42772 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 42810 + /* 42777 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 42780 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 42795 + /* 42785 */ MCD_OPC_CheckPredicate, + 3, + 41, + 241, + 0, // Skip to: 104527 + /* 42790 */ MCD_OPC_Decode, + 171, + 38, + 181, + 1, // Opcode: ST1W + /* 42795 */ MCD_OPC_FilterValue, + 1, + 31, + 241, + 0, // Skip to: 104527 + /* 42800 */ MCD_OPC_CheckPredicate, + 3, + 26, + 241, + 0, // Skip to: 104527 + /* 42805 */ MCD_OPC_Decode, + 172, + 38, + 181, + 1, // Opcode: ST1W_D + /* 42810 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 42825 + /* 42815 */ MCD_OPC_CheckPredicate, + 3, + 11, + 241, + 0, // Skip to: 104527 + /* 42820 */ MCD_OPC_Decode, + 140, + 40, + 175, + 1, // Opcode: STR_ZXI + /* 42825 */ MCD_OPC_FilterValue, + 7, + 1, + 241, + 0, // Skip to: 104527 + /* 42830 */ MCD_OPC_CheckPredicate, + 3, + 252, + 240, + 0, // Skip to: 104527 + /* 42835 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 245, + 240, + 0, // Skip to: 104527 + /* 42842 */ MCD_OPC_Decode, + 227, + 37, + 181, + 1, // Opcode: ST1D + /* 42847 */ MCD_OPC_FilterValue, + 3, + 243, + 0, + 0, // Skip to: 43095 + /* 42852 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 42855 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 42870 + /* 42860 */ MCD_OPC_CheckPredicate, + 3, + 222, + 240, + 0, // Skip to: 104527 + /* 42865 */ MCD_OPC_Decode, + 192, + 39, + 181, + 1, // Opcode: STNT1B_ZRR + /* 42870 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 42885 + /* 42875 */ MCD_OPC_CheckPredicate, + 3, + 207, + 240, + 0, // Skip to: 104527 + /* 42880 */ MCD_OPC_Decode, + 193, + 38, + 184, + 1, // Opcode: ST2B + /* 42885 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 42900 + /* 42890 */ MCD_OPC_CheckPredicate, + 3, + 192, + 240, + 0, // Skip to: 104527 + /* 42895 */ MCD_OPC_Decode, + 226, + 38, + 186, + 1, // Opcode: ST3B + /* 42900 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 42915 + /* 42905 */ MCD_OPC_CheckPredicate, + 3, + 177, + 240, + 0, // Skip to: 104527 + /* 42910 */ MCD_OPC_Decode, + 128, + 39, + 188, + 1, // Opcode: ST4B + /* 42915 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 42930 + /* 42920 */ MCD_OPC_CheckPredicate, + 3, + 162, + 240, + 0, // Skip to: 104527 + /* 42925 */ MCD_OPC_Decode, + 199, + 39, + 181, + 1, // Opcode: STNT1H_ZRR + /* 42930 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 42945 + /* 42935 */ MCD_OPC_CheckPredicate, + 3, + 147, + 240, + 0, // Skip to: 104527 + /* 42940 */ MCD_OPC_Decode, + 200, + 38, + 184, + 1, // Opcode: ST2H + /* 42945 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 42960 + /* 42950 */ MCD_OPC_CheckPredicate, + 3, + 132, + 240, + 0, // Skip to: 104527 + /* 42955 */ MCD_OPC_Decode, + 230, + 38, + 186, + 1, // Opcode: ST3H + /* 42960 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 42975 + /* 42965 */ MCD_OPC_CheckPredicate, + 3, + 117, + 240, + 0, // Skip to: 104527 + /* 42970 */ MCD_OPC_Decode, + 146, + 39, + 188, + 1, // Opcode: ST4H + /* 42975 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 42990 + /* 42980 */ MCD_OPC_CheckPredicate, + 3, + 102, + 240, + 0, // Skip to: 104527 + /* 42985 */ MCD_OPC_Decode, + 203, + 39, + 181, + 1, // Opcode: STNT1W_ZRR + /* 42990 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 43005 + /* 42995 */ MCD_OPC_CheckPredicate, + 3, + 87, + 240, + 0, // Skip to: 104527 + /* 43000 */ MCD_OPC_Decode, + 216, + 38, + 184, + 1, // Opcode: ST2W + /* 43005 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 43020 + /* 43010 */ MCD_OPC_CheckPredicate, + 3, + 72, + 240, + 0, // Skip to: 104527 + /* 43015 */ MCD_OPC_Decode, + 246, + 38, + 186, + 1, // Opcode: ST3W + /* 43020 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 43035 + /* 43025 */ MCD_OPC_CheckPredicate, + 3, + 57, + 240, + 0, // Skip to: 104527 + /* 43030 */ MCD_OPC_Decode, + 148, + 39, + 188, + 1, // Opcode: ST4W + /* 43035 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 43050 + /* 43040 */ MCD_OPC_CheckPredicate, + 3, + 42, + 240, + 0, // Skip to: 104527 + /* 43045 */ MCD_OPC_Decode, + 196, + 39, + 181, + 1, // Opcode: STNT1D_ZRR + /* 43050 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 43065 + /* 43055 */ MCD_OPC_CheckPredicate, + 3, + 27, + 240, + 0, // Skip to: 104527 + /* 43060 */ MCD_OPC_Decode, + 195, + 38, + 184, + 1, // Opcode: ST2D + /* 43065 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 43080 + /* 43070 */ MCD_OPC_CheckPredicate, + 3, + 12, + 240, + 0, // Skip to: 104527 + /* 43075 */ MCD_OPC_Decode, + 228, + 38, + 186, + 1, // Opcode: ST3D + /* 43080 */ MCD_OPC_FilterValue, + 15, + 2, + 240, + 0, // Skip to: 104527 + /* 43085 */ MCD_OPC_CheckPredicate, + 3, + 253, + 239, + 0, // Skip to: 104527 + /* 43090 */ MCD_OPC_Decode, + 130, + 39, + 188, + 1, // Opcode: ST4D + /* 43095 */ MCD_OPC_FilterValue, + 4, + 183, + 0, + 0, // Skip to: 43283 + /* 43100 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 43103 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 43118 + /* 43108 */ MCD_OPC_CheckPredicate, + 6, + 230, + 239, + 0, // Skip to: 104527 + /* 43113 */ MCD_OPC_Decode, + 154, + 37, + 171, + 1, // Opcode: SST1B_D_UXTW + /* 43118 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 43133 + /* 43123 */ MCD_OPC_CheckPredicate, + 6, + 215, + 239, + 0, // Skip to: 104527 + /* 43128 */ MCD_OPC_Decode, + 157, + 37, + 171, + 1, // Opcode: SST1B_S_UXTW + /* 43133 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 43148 + /* 43138 */ MCD_OPC_CheckPredicate, + 6, + 200, + 239, + 0, // Skip to: 104527 + /* 43143 */ MCD_OPC_Decode, + 170, + 37, + 171, + 1, // Opcode: SST1H_D_UXTW + /* 43148 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 43163 + /* 43153 */ MCD_OPC_CheckPredicate, + 6, + 185, + 239, + 0, // Skip to: 104527 + /* 43158 */ MCD_OPC_Decode, + 171, + 37, + 171, + 1, // Opcode: SST1H_D_UXTW_SCALED + /* 43163 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 43178 + /* 43168 */ MCD_OPC_CheckPredicate, + 6, + 170, + 239, + 0, // Skip to: 104527 + /* 43173 */ MCD_OPC_Decode, + 175, + 37, + 171, + 1, // Opcode: SST1H_S_UXTW + /* 43178 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 43193 + /* 43183 */ MCD_OPC_CheckPredicate, + 6, + 155, + 239, + 0, // Skip to: 104527 + /* 43188 */ MCD_OPC_Decode, + 176, + 37, + 171, + 1, // Opcode: SST1H_S_UXTW_SCALED + /* 43193 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 43208 + /* 43198 */ MCD_OPC_CheckPredicate, + 6, + 140, + 239, + 0, // Skip to: 104527 + /* 43203 */ MCD_OPC_Decode, + 182, + 37, + 171, + 1, // Opcode: SST1W_D_UXTW + /* 43208 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 43223 + /* 43213 */ MCD_OPC_CheckPredicate, + 6, + 125, + 239, + 0, // Skip to: 104527 + /* 43218 */ MCD_OPC_Decode, + 183, + 37, + 171, + 1, // Opcode: SST1W_D_UXTW_SCALED + /* 43223 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 43238 + /* 43228 */ MCD_OPC_CheckPredicate, + 6, + 110, + 239, + 0, // Skip to: 104527 + /* 43233 */ MCD_OPC_Decode, + 187, + 37, + 171, + 1, // Opcode: SST1W_UXTW + /* 43238 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 43253 + /* 43243 */ MCD_OPC_CheckPredicate, + 6, + 95, + 239, + 0, // Skip to: 104527 + /* 43248 */ MCD_OPC_Decode, + 188, + 37, + 171, + 1, // Opcode: SST1W_UXTW_SCALED + /* 43253 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 43268 + /* 43258 */ MCD_OPC_CheckPredicate, + 6, + 80, + 239, + 0, // Skip to: 104527 + /* 43263 */ MCD_OPC_Decode, + 163, + 37, + 171, + 1, // Opcode: SST1D_UXTW + /* 43268 */ MCD_OPC_FilterValue, + 13, + 70, + 239, + 0, // Skip to: 104527 + /* 43273 */ MCD_OPC_CheckPredicate, + 6, + 65, + 239, + 0, // Skip to: 104527 + /* 43278 */ MCD_OPC_Decode, + 164, + 37, + 171, + 1, // Opcode: SST1D_UXTW_SCALED + /* 43283 */ MCD_OPC_FilterValue, + 5, + 213, + 0, + 0, // Skip to: 43501 + /* 43288 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 43291 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 43306 + /* 43296 */ MCD_OPC_CheckPredicate, + 6, + 42, + 239, + 0, // Skip to: 104527 + /* 43301 */ MCD_OPC_Decode, + 152, + 37, + 171, + 1, // Opcode: SST1B_D_REAL + /* 43306 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 43321 + /* 43311 */ MCD_OPC_CheckPredicate, + 6, + 27, + 239, + 0, // Skip to: 104527 + /* 43316 */ MCD_OPC_Decode, + 151, + 37, + 177, + 1, // Opcode: SST1B_D_IMM + /* 43321 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 43336 + /* 43326 */ MCD_OPC_CheckPredicate, + 6, + 12, + 239, + 0, // Skip to: 104527 + /* 43331 */ MCD_OPC_Decode, + 155, + 37, + 177, + 1, // Opcode: SST1B_S_IMM + /* 43336 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 43351 + /* 43341 */ MCD_OPC_CheckPredicate, + 6, + 253, + 238, + 0, // Skip to: 104527 + /* 43346 */ MCD_OPC_Decode, + 166, + 37, + 171, + 1, // Opcode: SST1H_D_REAL + /* 43351 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 43366 + /* 43356 */ MCD_OPC_CheckPredicate, + 6, + 238, + 238, + 0, // Skip to: 104527 + /* 43361 */ MCD_OPC_Decode, + 167, + 37, + 171, + 1, // Opcode: SST1H_D_SCALED_SCALED_REAL + /* 43366 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 43381 + /* 43371 */ MCD_OPC_CheckPredicate, + 6, + 223, + 238, + 0, // Skip to: 104527 + /* 43376 */ MCD_OPC_Decode, + 165, + 37, + 177, + 1, // Opcode: SST1H_D_IMM + /* 43381 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 43396 + /* 43386 */ MCD_OPC_CheckPredicate, + 6, + 208, + 238, + 0, // Skip to: 104527 + /* 43391 */ MCD_OPC_Decode, + 172, + 37, + 177, + 1, // Opcode: SST1H_S_IMM + /* 43396 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 43411 + /* 43401 */ MCD_OPC_CheckPredicate, + 6, + 193, + 238, + 0, // Skip to: 104527 + /* 43406 */ MCD_OPC_Decode, + 178, + 37, + 171, + 1, // Opcode: SST1W_D_REAL + /* 43411 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 43426 + /* 43416 */ MCD_OPC_CheckPredicate, + 6, + 178, + 238, + 0, // Skip to: 104527 + /* 43421 */ MCD_OPC_Decode, + 179, + 37, + 171, + 1, // Opcode: SST1W_D_SCALED_SCALED_REAL + /* 43426 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 43441 + /* 43431 */ MCD_OPC_CheckPredicate, + 6, + 163, + 238, + 0, // Skip to: 104527 + /* 43436 */ MCD_OPC_Decode, + 177, + 37, + 177, + 1, // Opcode: SST1W_D_IMM + /* 43441 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 43456 + /* 43446 */ MCD_OPC_CheckPredicate, + 6, + 148, + 238, + 0, // Skip to: 104527 + /* 43451 */ MCD_OPC_Decode, + 184, + 37, + 177, + 1, // Opcode: SST1W_IMM + /* 43456 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 43471 + /* 43461 */ MCD_OPC_CheckPredicate, + 6, + 133, + 238, + 0, // Skip to: 104527 + /* 43466 */ MCD_OPC_Decode, + 159, + 37, + 171, + 1, // Opcode: SST1D_REAL + /* 43471 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 43486 + /* 43476 */ MCD_OPC_CheckPredicate, + 6, + 118, + 238, + 0, // Skip to: 104527 + /* 43481 */ MCD_OPC_Decode, + 160, + 37, + 171, + 1, // Opcode: SST1D_SCALED_SCALED_REAL + /* 43486 */ MCD_OPC_FilterValue, + 14, + 108, + 238, + 0, // Skip to: 104527 + /* 43491 */ MCD_OPC_CheckPredicate, + 6, + 103, + 238, + 0, // Skip to: 104527 + /* 43496 */ MCD_OPC_Decode, + 158, + 37, + 177, + 1, // Opcode: SST1D_IMM + /* 43501 */ MCD_OPC_FilterValue, + 6, + 183, + 0, + 0, // Skip to: 43689 + /* 43506 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 43509 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 43524 + /* 43514 */ MCD_OPC_CheckPredicate, + 6, + 80, + 238, + 0, // Skip to: 104527 + /* 43519 */ MCD_OPC_Decode, + 153, + 37, + 171, + 1, // Opcode: SST1B_D_SXTW + /* 43524 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 43539 + /* 43529 */ MCD_OPC_CheckPredicate, + 6, + 65, + 238, + 0, // Skip to: 104527 + /* 43534 */ MCD_OPC_Decode, + 156, + 37, + 171, + 1, // Opcode: SST1B_S_SXTW + /* 43539 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 43554 + /* 43544 */ MCD_OPC_CheckPredicate, + 6, + 50, + 238, + 0, // Skip to: 104527 + /* 43549 */ MCD_OPC_Decode, + 168, + 37, + 171, + 1, // Opcode: SST1H_D_SXTW + /* 43554 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 43569 + /* 43559 */ MCD_OPC_CheckPredicate, + 6, + 35, + 238, + 0, // Skip to: 104527 + /* 43564 */ MCD_OPC_Decode, + 169, + 37, + 171, + 1, // Opcode: SST1H_D_SXTW_SCALED + /* 43569 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 43584 + /* 43574 */ MCD_OPC_CheckPredicate, + 6, + 20, + 238, + 0, // Skip to: 104527 + /* 43579 */ MCD_OPC_Decode, + 173, + 37, + 171, + 1, // Opcode: SST1H_S_SXTW + /* 43584 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 43599 + /* 43589 */ MCD_OPC_CheckPredicate, + 6, + 5, + 238, + 0, // Skip to: 104527 + /* 43594 */ MCD_OPC_Decode, + 174, + 37, + 171, + 1, // Opcode: SST1H_S_SXTW_SCALED + /* 43599 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 43614 + /* 43604 */ MCD_OPC_CheckPredicate, + 6, + 246, + 237, + 0, // Skip to: 104527 + /* 43609 */ MCD_OPC_Decode, + 180, + 37, + 171, + 1, // Opcode: SST1W_D_SXTW + /* 43614 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 43629 + /* 43619 */ MCD_OPC_CheckPredicate, + 6, + 231, + 237, + 0, // Skip to: 104527 + /* 43624 */ MCD_OPC_Decode, + 181, + 37, + 171, + 1, // Opcode: SST1W_D_SXTW_SCALED + /* 43629 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 43644 + /* 43634 */ MCD_OPC_CheckPredicate, + 6, + 216, + 237, + 0, // Skip to: 104527 + /* 43639 */ MCD_OPC_Decode, + 185, + 37, + 171, + 1, // Opcode: SST1W_SXTW + /* 43644 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 43659 + /* 43649 */ MCD_OPC_CheckPredicate, + 6, + 201, + 237, + 0, // Skip to: 104527 + /* 43654 */ MCD_OPC_Decode, + 186, + 37, + 171, + 1, // Opcode: SST1W_SXTW_SCALED + /* 43659 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 43674 + /* 43664 */ MCD_OPC_CheckPredicate, + 6, + 186, + 237, + 0, // Skip to: 104527 + /* 43669 */ MCD_OPC_Decode, + 161, + 37, + 171, + 1, // Opcode: SST1D_SXTW + /* 43674 */ MCD_OPC_FilterValue, + 13, + 176, + 237, + 0, // Skip to: 104527 + /* 43679 */ MCD_OPC_CheckPredicate, + 6, + 171, + 237, + 0, // Skip to: 104527 + /* 43684 */ MCD_OPC_Decode, + 162, + 37, + 171, + 1, // Opcode: SST1D_SXTW_SCALED + /* 43689 */ MCD_OPC_FilterValue, + 7, + 161, + 237, + 0, // Skip to: 104527 + /* 43694 */ MCD_OPC_ExtractField, + 20, + 6, // Inst{25-20} ... + /* 43697 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 43712 + /* 43702 */ MCD_OPC_CheckPredicate, + 3, + 148, + 237, + 0, // Skip to: 104527 + /* 43707 */ MCD_OPC_Decode, + 224, + 37, + 182, + 1, // Opcode: ST1B_IMM + /* 43712 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 43727 + /* 43717 */ MCD_OPC_CheckPredicate, + 3, + 133, + 237, + 0, // Skip to: 104527 + /* 43722 */ MCD_OPC_Decode, + 191, + 39, + 182, + 1, // Opcode: STNT1B_ZRI + /* 43727 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 43742 + /* 43732 */ MCD_OPC_CheckPredicate, + 3, + 118, + 237, + 0, // Skip to: 104527 + /* 43737 */ MCD_OPC_Decode, + 223, + 37, + 182, + 1, // Opcode: ST1B_H_IMM + /* 43742 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 43757 + /* 43747 */ MCD_OPC_CheckPredicate, + 3, + 103, + 237, + 0, // Skip to: 104527 + /* 43752 */ MCD_OPC_Decode, + 194, + 38, + 185, + 1, // Opcode: ST2B_IMM + /* 43757 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 43772 + /* 43762 */ MCD_OPC_CheckPredicate, + 3, + 88, + 237, + 0, // Skip to: 104527 + /* 43767 */ MCD_OPC_Decode, + 226, + 37, + 182, + 1, // Opcode: ST1B_S_IMM + /* 43772 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 43787 + /* 43777 */ MCD_OPC_CheckPredicate, + 3, + 73, + 237, + 0, // Skip to: 104527 + /* 43782 */ MCD_OPC_Decode, + 227, + 38, + 187, + 1, // Opcode: ST3B_IMM + /* 43787 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 43802 + /* 43792 */ MCD_OPC_CheckPredicate, + 3, + 58, + 237, + 0, // Skip to: 104527 + /* 43797 */ MCD_OPC_Decode, + 221, + 37, + 182, + 1, // Opcode: ST1B_D_IMM + /* 43802 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 43817 + /* 43807 */ MCD_OPC_CheckPredicate, + 3, + 43, + 237, + 0, // Skip to: 104527 + /* 43812 */ MCD_OPC_Decode, + 129, + 39, + 189, + 1, // Opcode: ST4B_IMM + /* 43817 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 43832 + /* 43822 */ MCD_OPC_CheckPredicate, + 3, + 28, + 237, + 0, // Skip to: 104527 + /* 43827 */ MCD_OPC_Decode, + 198, + 39, + 182, + 1, // Opcode: STNT1H_ZRI + /* 43832 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 43847 + /* 43837 */ MCD_OPC_CheckPredicate, + 3, + 13, + 237, + 0, // Skip to: 104527 + /* 43842 */ MCD_OPC_Decode, + 248, + 37, + 182, + 1, // Opcode: ST1H_IMM + /* 43847 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 43862 + /* 43852 */ MCD_OPC_CheckPredicate, + 3, + 254, + 236, + 0, // Skip to: 104527 + /* 43857 */ MCD_OPC_Decode, + 201, + 38, + 185, + 1, // Opcode: ST2H_IMM + /* 43862 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 43877 + /* 43867 */ MCD_OPC_CheckPredicate, + 3, + 239, + 236, + 0, // Skip to: 104527 + /* 43872 */ MCD_OPC_Decode, + 250, + 37, + 182, + 1, // Opcode: ST1H_S_IMM + /* 43877 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 43892 + /* 43882 */ MCD_OPC_CheckPredicate, + 3, + 224, + 236, + 0, // Skip to: 104527 + /* 43887 */ MCD_OPC_Decode, + 231, + 38, + 187, + 1, // Opcode: ST3H_IMM + /* 43892 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 43907 + /* 43897 */ MCD_OPC_CheckPredicate, + 3, + 209, + 236, + 0, // Skip to: 104527 + /* 43902 */ MCD_OPC_Decode, + 247, + 37, + 182, + 1, // Opcode: ST1H_D_IMM + /* 43907 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 43922 + /* 43912 */ MCD_OPC_CheckPredicate, + 3, + 194, + 236, + 0, // Skip to: 104527 + /* 43917 */ MCD_OPC_Decode, + 147, + 39, + 189, + 1, // Opcode: ST4H_IMM + /* 43922 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 43937 + /* 43927 */ MCD_OPC_CheckPredicate, + 3, + 179, + 236, + 0, // Skip to: 104527 + /* 43932 */ MCD_OPC_Decode, + 202, + 39, + 182, + 1, // Opcode: STNT1W_ZRI + /* 43937 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 43952 + /* 43942 */ MCD_OPC_CheckPredicate, + 3, + 164, + 236, + 0, // Skip to: 104527 + /* 43947 */ MCD_OPC_Decode, + 217, + 38, + 185, + 1, // Opcode: ST2W_IMM + /* 43952 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 43967 + /* 43957 */ MCD_OPC_CheckPredicate, + 3, + 149, + 236, + 0, // Skip to: 104527 + /* 43962 */ MCD_OPC_Decode, + 174, + 38, + 182, + 1, // Opcode: ST1W_IMM + /* 43967 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 43982 + /* 43972 */ MCD_OPC_CheckPredicate, + 3, + 134, + 236, + 0, // Skip to: 104527 + /* 43977 */ MCD_OPC_Decode, + 247, + 38, + 187, + 1, // Opcode: ST3W_IMM + /* 43982 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 43997 + /* 43987 */ MCD_OPC_CheckPredicate, + 3, + 119, + 236, + 0, // Skip to: 104527 + /* 43992 */ MCD_OPC_Decode, + 173, + 38, + 182, + 1, // Opcode: ST1W_D_IMM + /* 43997 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 44012 + /* 44002 */ MCD_OPC_CheckPredicate, + 3, + 104, + 236, + 0, // Skip to: 104527 + /* 44007 */ MCD_OPC_Decode, + 149, + 39, + 189, + 1, // Opcode: ST4W_IMM + /* 44012 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 44027 + /* 44017 */ MCD_OPC_CheckPredicate, + 3, + 89, + 236, + 0, // Skip to: 104527 + /* 44022 */ MCD_OPC_Decode, + 195, + 39, + 182, + 1, // Opcode: STNT1D_ZRI + /* 44027 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 44042 + /* 44032 */ MCD_OPC_CheckPredicate, + 3, + 74, + 236, + 0, // Skip to: 104527 + /* 44037 */ MCD_OPC_Decode, + 196, + 38, + 185, + 1, // Opcode: ST2D_IMM + /* 44042 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 44057 + /* 44047 */ MCD_OPC_CheckPredicate, + 3, + 59, + 236, + 0, // Skip to: 104527 + /* 44052 */ MCD_OPC_Decode, + 229, + 38, + 187, + 1, // Opcode: ST3D_IMM + /* 44057 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 44072 + /* 44062 */ MCD_OPC_CheckPredicate, + 3, + 44, + 236, + 0, // Skip to: 104527 + /* 44067 */ MCD_OPC_Decode, + 228, + 37, + 182, + 1, // Opcode: ST1D_IMM + /* 44072 */ MCD_OPC_FilterValue, + 31, + 34, + 236, + 0, // Skip to: 104527 + /* 44077 */ MCD_OPC_CheckPredicate, + 3, + 29, + 236, + 0, // Skip to: 104527 + /* 44082 */ MCD_OPC_Decode, + 131, + 39, + 189, + 1, // Opcode: ST4D_IMM + /* 44087 */ MCD_OPC_FilterValue, + 2, + 66, + 8, + 0, // Skip to: 46206 + /* 44092 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 44095 */ MCD_OPC_FilterValue, + 0, + 122, + 1, + 0, // Skip to: 44478 + /* 44100 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 44103 */ MCD_OPC_FilterValue, + 0, + 51, + 1, + 0, // Skip to: 44415 + /* 44108 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 44111 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 44139 + /* 44116 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 44119 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 44129 + /* 44124 */ MCD_OPC_Decode, + 156, + 40, + 190, + 1, // Opcode: STXRB + /* 44129 */ MCD_OPC_FilterValue, + 1, + 233, + 235, + 0, // Skip to: 104527 + /* 44134 */ MCD_OPC_Decode, + 182, + 39, + 190, + 1, // Opcode: STLXRB + /* 44139 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 44177 + /* 44144 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 44147 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 44162 + /* 44152 */ MCD_OPC_CheckPredicate, + 18, + 210, + 235, + 0, // Skip to: 104527 + /* 44157 */ MCD_OPC_Decode, + 168, + 9, + 191, + 1, // Opcode: CASPW + /* 44162 */ MCD_OPC_FilterValue, + 63, + 200, + 235, + 0, // Skip to: 104527 + /* 44167 */ MCD_OPC_CheckPredicate, + 18, + 195, + 235, + 0, // Skip to: 104527 + /* 44172 */ MCD_OPC_Decode, + 166, + 9, + 191, + 1, // Opcode: CASPLW + /* 44177 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 44215 + /* 44182 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 44185 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 44200 + /* 44190 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44195 */ MCD_OPC_Decode, + 210, + 26, + 190, + 1, // Opcode: LDXRB + /* 44200 */ MCD_OPC_FilterValue, + 1, + 162, + 235, + 0, // Skip to: 104527 + /* 44205 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44210 */ MCD_OPC_Decode, + 161, + 24, + 190, + 1, // Opcode: LDAXRB + /* 44215 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 44253 + /* 44220 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 44223 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 44238 + /* 44228 */ MCD_OPC_CheckPredicate, + 18, + 134, + 235, + 0, // Skip to: 104527 + /* 44233 */ MCD_OPC_Decode, + 164, + 9, + 191, + 1, // Opcode: CASPAW + /* 44238 */ MCD_OPC_FilterValue, + 63, + 124, + 235, + 0, // Skip to: 104527 + /* 44243 */ MCD_OPC_CheckPredicate, + 18, + 119, + 235, + 0, // Skip to: 104527 + /* 44248 */ MCD_OPC_Decode, + 162, + 9, + 191, + 1, // Opcode: CASPALW + /* 44253 */ MCD_OPC_FilterValue, + 4, + 38, + 0, + 0, // Skip to: 44296 + /* 44258 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 44261 */ MCD_OPC_FilterValue, + 0, + 15, + 0, + 0, // Skip to: 44281 + /* 44266 */ MCD_OPC_CheckPredicate, + 19, + 96, + 235, + 0, // Skip to: 104527 + /* 44271 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44276 */ MCD_OPC_Decode, + 168, + 39, + 190, + 1, // Opcode: STLLRB + /* 44281 */ MCD_OPC_FilterValue, + 1, + 81, + 235, + 0, // Skip to: 104527 + /* 44286 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44291 */ MCD_OPC_Decode, + 172, + 39, + 190, + 1, // Opcode: STLRB + /* 44296 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 44334 + /* 44301 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 44304 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 44319 + /* 44309 */ MCD_OPC_CheckPredicate, + 18, + 53, + 235, + 0, // Skip to: 104527 + /* 44314 */ MCD_OPC_Decode, + 156, + 9, + 192, + 1, // Opcode: CASB + /* 44319 */ MCD_OPC_FilterValue, + 63, + 43, + 235, + 0, // Skip to: 104527 + /* 44324 */ MCD_OPC_CheckPredicate, + 18, + 38, + 235, + 0, // Skip to: 104527 + /* 44329 */ MCD_OPC_Decode, + 158, + 9, + 192, + 1, // Opcode: CASLB + /* 44334 */ MCD_OPC_FilterValue, + 6, + 38, + 0, + 0, // Skip to: 44377 + /* 44339 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 44342 */ MCD_OPC_FilterValue, + 0, + 15, + 0, + 0, // Skip to: 44362 + /* 44347 */ MCD_OPC_CheckPredicate, + 19, + 15, + 235, + 0, // Skip to: 104527 + /* 44352 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44357 */ MCD_OPC_Decode, + 215, + 24, + 190, + 1, // Opcode: LDLARB + /* 44362 */ MCD_OPC_FilterValue, + 1, + 0, + 235, + 0, // Skip to: 104527 + /* 44367 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44372 */ MCD_OPC_Decode, + 155, + 24, + 190, + 1, // Opcode: LDARB + /* 44377 */ MCD_OPC_FilterValue, + 7, + 241, + 234, + 0, // Skip to: 104527 + /* 44382 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 44385 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 44400 + /* 44390 */ MCD_OPC_CheckPredicate, + 18, + 228, + 234, + 0, // Skip to: 104527 + /* 44395 */ MCD_OPC_Decode, + 148, + 9, + 192, + 1, // Opcode: CASAB + /* 44400 */ MCD_OPC_FilterValue, + 63, + 218, + 234, + 0, // Skip to: 104527 + /* 44405 */ MCD_OPC_CheckPredicate, + 18, + 213, + 234, + 0, // Skip to: 104527 + /* 44410 */ MCD_OPC_Decode, + 150, + 9, + 192, + 1, // Opcode: CASALB + /* 44415 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 44443 + /* 44420 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 44423 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 44433 + /* 44428 */ MCD_OPC_Decode, + 254, + 7, + 193, + 1, // Opcode: ANDWrs + /* 44433 */ MCD_OPC_FilterValue, + 1, + 185, + 234, + 0, // Skip to: 104527 + /* 44438 */ MCD_OPC_Decode, + 222, + 8, + 193, + 1, // Opcode: BICWrs + /* 44443 */ MCD_OPC_FilterValue, + 3, + 175, + 234, + 0, // Skip to: 104527 + /* 44448 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 44451 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 44461 + /* 44456 */ MCD_OPC_Decode, + 192, + 7, + 193, + 1, // Opcode: ADDWrs + /* 44461 */ MCD_OPC_FilterValue, + 1, + 157, + 234, + 0, // Skip to: 104527 + /* 44466 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 150, + 234, + 0, // Skip to: 104527 + /* 44473 */ MCD_OPC_Decode, + 193, + 7, + 194, + 1, // Opcode: ADDWrx + /* 44478 */ MCD_OPC_FilterValue, + 1, + 162, + 0, + 0, // Skip to: 44645 + /* 44483 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 44486 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 44534 + /* 44491 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 44494 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 44504 + /* 44499 */ MCD_OPC_Decode, + 189, + 39, + 195, + 1, // Opcode: STNPWi + /* 44504 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 44514 + /* 44509 */ MCD_OPC_Decode, + 238, + 24, + 195, + 1, // Opcode: LDNPWi + /* 44514 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 44524 + /* 44519 */ MCD_OPC_Decode, + 216, + 39, + 195, + 1, // Opcode: STPWpost + /* 44524 */ MCD_OPC_FilterValue, + 3, + 94, + 234, + 0, // Skip to: 104527 + /* 44529 */ MCD_OPC_Decode, + 145, + 25, + 195, + 1, // Opcode: LDPWpost + /* 44534 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 44582 + /* 44539 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 44542 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 44552 + /* 44547 */ MCD_OPC_Decode, + 215, + 39, + 195, + 1, // Opcode: STPWi + /* 44552 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 44562 + /* 44557 */ MCD_OPC_Decode, + 144, + 25, + 195, + 1, // Opcode: LDPWi + /* 44562 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 44572 + /* 44567 */ MCD_OPC_Decode, + 217, + 39, + 195, + 1, // Opcode: STPWpre + /* 44572 */ MCD_OPC_FilterValue, + 3, + 46, + 234, + 0, // Skip to: 104527 + /* 44577 */ MCD_OPC_Decode, + 146, + 25, + 195, + 1, // Opcode: LDPWpre + /* 44582 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 44610 + /* 44587 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 44590 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 44600 + /* 44595 */ MCD_OPC_Decode, + 148, + 28, + 193, + 1, // Opcode: ORRWrs + /* 44600 */ MCD_OPC_FilterValue, + 1, + 18, + 234, + 0, // Skip to: 104527 + /* 44605 */ MCD_OPC_Decode, + 141, + 28, + 193, + 1, // Opcode: ORNWrs + /* 44610 */ MCD_OPC_FilterValue, + 3, + 8, + 234, + 0, // Skip to: 104527 + /* 44615 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 44618 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 44628 + /* 44623 */ MCD_OPC_Decode, + 177, + 7, + 193, + 1, // Opcode: ADDSWrs + /* 44628 */ MCD_OPC_FilterValue, + 1, + 246, + 233, + 0, // Skip to: 104527 + /* 44633 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 239, + 233, + 0, // Skip to: 104527 + /* 44640 */ MCD_OPC_Decode, + 178, + 7, + 194, + 1, // Opcode: ADDSWrx + /* 44645 */ MCD_OPC_FilterValue, + 2, + 122, + 1, + 0, // Skip to: 45028 + /* 44650 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 44653 */ MCD_OPC_FilterValue, + 0, + 51, + 1, + 0, // Skip to: 44965 + /* 44658 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 44661 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 44689 + /* 44666 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 44669 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 44679 + /* 44674 */ MCD_OPC_Decode, + 157, + 40, + 190, + 1, // Opcode: STXRH + /* 44679 */ MCD_OPC_FilterValue, + 1, + 195, + 233, + 0, // Skip to: 104527 + /* 44684 */ MCD_OPC_Decode, + 183, + 39, + 190, + 1, // Opcode: STLXRH + /* 44689 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 44727 + /* 44694 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 44697 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 44712 + /* 44702 */ MCD_OPC_CheckPredicate, + 18, + 172, + 233, + 0, // Skip to: 104527 + /* 44707 */ MCD_OPC_Decode, + 169, + 9, + 196, + 1, // Opcode: CASPX + /* 44712 */ MCD_OPC_FilterValue, + 63, + 162, + 233, + 0, // Skip to: 104527 + /* 44717 */ MCD_OPC_CheckPredicate, + 18, + 157, + 233, + 0, // Skip to: 104527 + /* 44722 */ MCD_OPC_Decode, + 167, + 9, + 196, + 1, // Opcode: CASPLX + /* 44727 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 44765 + /* 44732 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 44735 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 44750 + /* 44740 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44745 */ MCD_OPC_Decode, + 211, + 26, + 190, + 1, // Opcode: LDXRH + /* 44750 */ MCD_OPC_FilterValue, + 1, + 124, + 233, + 0, // Skip to: 104527 + /* 44755 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44760 */ MCD_OPC_Decode, + 162, + 24, + 190, + 1, // Opcode: LDAXRH + /* 44765 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 44803 + /* 44770 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 44773 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 44788 + /* 44778 */ MCD_OPC_CheckPredicate, + 18, + 96, + 233, + 0, // Skip to: 104527 + /* 44783 */ MCD_OPC_Decode, + 165, + 9, + 196, + 1, // Opcode: CASPAX + /* 44788 */ MCD_OPC_FilterValue, + 63, + 86, + 233, + 0, // Skip to: 104527 + /* 44793 */ MCD_OPC_CheckPredicate, + 18, + 81, + 233, + 0, // Skip to: 104527 + /* 44798 */ MCD_OPC_Decode, + 163, + 9, + 196, + 1, // Opcode: CASPALX + /* 44803 */ MCD_OPC_FilterValue, + 4, + 38, + 0, + 0, // Skip to: 44846 + /* 44808 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 44811 */ MCD_OPC_FilterValue, + 0, + 15, + 0, + 0, // Skip to: 44831 + /* 44816 */ MCD_OPC_CheckPredicate, + 19, + 58, + 233, + 0, // Skip to: 104527 + /* 44821 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44826 */ MCD_OPC_Decode, + 169, + 39, + 190, + 1, // Opcode: STLLRH + /* 44831 */ MCD_OPC_FilterValue, + 1, + 43, + 233, + 0, // Skip to: 104527 + /* 44836 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44841 */ MCD_OPC_Decode, + 173, + 39, + 190, + 1, // Opcode: STLRH + /* 44846 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 44884 + /* 44851 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 44854 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 44869 + /* 44859 */ MCD_OPC_CheckPredicate, + 18, + 15, + 233, + 0, // Skip to: 104527 + /* 44864 */ MCD_OPC_Decode, + 157, + 9, + 192, + 1, // Opcode: CASH + /* 44869 */ MCD_OPC_FilterValue, + 63, + 5, + 233, + 0, // Skip to: 104527 + /* 44874 */ MCD_OPC_CheckPredicate, + 18, + 0, + 233, + 0, // Skip to: 104527 + /* 44879 */ MCD_OPC_Decode, + 159, + 9, + 192, + 1, // Opcode: CASLH + /* 44884 */ MCD_OPC_FilterValue, + 6, + 38, + 0, + 0, // Skip to: 44927 + /* 44889 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 44892 */ MCD_OPC_FilterValue, + 0, + 15, + 0, + 0, // Skip to: 44912 + /* 44897 */ MCD_OPC_CheckPredicate, + 19, + 233, + 232, + 0, // Skip to: 104527 + /* 44902 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44907 */ MCD_OPC_Decode, + 216, + 24, + 190, + 1, // Opcode: LDLARH + /* 44912 */ MCD_OPC_FilterValue, + 1, + 218, + 232, + 0, // Skip to: 104527 + /* 44917 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 44922 */ MCD_OPC_Decode, + 156, + 24, + 190, + 1, // Opcode: LDARH + /* 44927 */ MCD_OPC_FilterValue, + 7, + 203, + 232, + 0, // Skip to: 104527 + /* 44932 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 44935 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 44950 + /* 44940 */ MCD_OPC_CheckPredicate, + 18, + 190, + 232, + 0, // Skip to: 104527 + /* 44945 */ MCD_OPC_Decode, + 149, + 9, + 192, + 1, // Opcode: CASAH + /* 44950 */ MCD_OPC_FilterValue, + 63, + 180, + 232, + 0, // Skip to: 104527 + /* 44955 */ MCD_OPC_CheckPredicate, + 18, + 175, + 232, + 0, // Skip to: 104527 + /* 44960 */ MCD_OPC_Decode, + 151, + 9, + 192, + 1, // Opcode: CASALH + /* 44965 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 44993 + /* 44970 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 44973 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 44983 + /* 44978 */ MCD_OPC_Decode, + 169, + 12, + 193, + 1, // Opcode: EORWrs + /* 44983 */ MCD_OPC_FilterValue, + 1, + 147, + 232, + 0, // Skip to: 104527 + /* 44988 */ MCD_OPC_Decode, + 151, + 12, + 193, + 1, // Opcode: EONWrs + /* 44993 */ MCD_OPC_FilterValue, + 3, + 137, + 232, + 0, // Skip to: 104527 + /* 44998 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 45001 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45011 + /* 45006 */ MCD_OPC_Decode, + 198, + 40, + 193, + 1, // Opcode: SUBWrs + /* 45011 */ MCD_OPC_FilterValue, + 1, + 119, + 232, + 0, // Skip to: 104527 + /* 45016 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 112, + 232, + 0, // Skip to: 104527 + /* 45023 */ MCD_OPC_Decode, + 199, + 40, + 194, + 1, // Opcode: SUBWrx + /* 45028 */ MCD_OPC_FilterValue, + 3, + 157, + 0, + 0, // Skip to: 45190 + /* 45033 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 45036 */ MCD_OPC_FilterValue, + 0, + 28, + 0, + 0, // Skip to: 45069 + /* 45041 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 45044 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 45059 + /* 45049 */ MCD_OPC_CheckPredicate, + 20, + 81, + 232, + 0, // Skip to: 104527 + /* 45054 */ MCD_OPC_Decode, + 165, + 39, + 195, + 1, // Opcode: STGPpost + /* 45059 */ MCD_OPC_FilterValue, + 3, + 71, + 232, + 0, // Skip to: 104527 + /* 45064 */ MCD_OPC_Decode, + 139, + 25, + 195, + 1, // Opcode: LDPSWpost + /* 45069 */ MCD_OPC_FilterValue, + 1, + 53, + 0, + 0, // Skip to: 45127 + /* 45074 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 45077 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 45092 + /* 45082 */ MCD_OPC_CheckPredicate, + 20, + 48, + 232, + 0, // Skip to: 104527 + /* 45087 */ MCD_OPC_Decode, + 163, + 39, + 195, + 1, // Opcode: STGPi + /* 45092 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 45102 + /* 45097 */ MCD_OPC_Decode, + 138, + 25, + 195, + 1, // Opcode: LDPSWi + /* 45102 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 45117 + /* 45107 */ MCD_OPC_CheckPredicate, + 20, + 23, + 232, + 0, // Skip to: 104527 + /* 45112 */ MCD_OPC_Decode, + 166, + 39, + 195, + 1, // Opcode: STGPpre + /* 45117 */ MCD_OPC_FilterValue, + 3, + 13, + 232, + 0, // Skip to: 104527 + /* 45122 */ MCD_OPC_Decode, + 140, + 25, + 195, + 1, // Opcode: LDPSWpre + /* 45127 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 45155 + /* 45132 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 45135 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45145 + /* 45140 */ MCD_OPC_Decode, + 245, + 7, + 193, + 1, // Opcode: ANDSWrs + /* 45145 */ MCD_OPC_FilterValue, + 1, + 241, + 231, + 0, // Skip to: 104527 + /* 45150 */ MCD_OPC_Decode, + 219, + 8, + 193, + 1, // Opcode: BICSWrs + /* 45155 */ MCD_OPC_FilterValue, + 3, + 231, + 231, + 0, // Skip to: 104527 + /* 45160 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 45163 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45173 + /* 45168 */ MCD_OPC_Decode, + 191, + 40, + 193, + 1, // Opcode: SUBSWrs + /* 45173 */ MCD_OPC_FilterValue, + 1, + 213, + 231, + 0, // Skip to: 104527 + /* 45178 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 206, + 231, + 0, // Skip to: 104527 + /* 45185 */ MCD_OPC_Decode, + 192, + 40, + 194, + 1, // Opcode: SUBSWrx + /* 45190 */ MCD_OPC_FilterValue, + 4, + 115, + 1, + 0, // Skip to: 45566 + /* 45195 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 45198 */ MCD_OPC_FilterValue, + 0, + 31, + 1, + 0, // Skip to: 45490 + /* 45203 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 45206 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 45234 + /* 45211 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45214 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45224 + /* 45219 */ MCD_OPC_Decode, + 158, + 40, + 190, + 1, // Opcode: STXRW + /* 45224 */ MCD_OPC_FilterValue, + 1, + 162, + 231, + 0, // Skip to: 104527 + /* 45229 */ MCD_OPC_Decode, + 184, + 39, + 190, + 1, // Opcode: STLXRW + /* 45234 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 45262 + /* 45239 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45242 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45252 + /* 45247 */ MCD_OPC_Decode, + 154, + 40, + 190, + 1, // Opcode: STXPW + /* 45252 */ MCD_OPC_FilterValue, + 1, + 134, + 231, + 0, // Skip to: 104527 + /* 45257 */ MCD_OPC_Decode, + 180, + 39, + 190, + 1, // Opcode: STLXPW + /* 45262 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 45300 + /* 45267 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45270 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 45285 + /* 45275 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45280 */ MCD_OPC_Decode, + 212, + 26, + 190, + 1, // Opcode: LDXRW + /* 45285 */ MCD_OPC_FilterValue, + 1, + 101, + 231, + 0, // Skip to: 104527 + /* 45290 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45295 */ MCD_OPC_Decode, + 163, + 24, + 190, + 1, // Opcode: LDAXRW + /* 45300 */ MCD_OPC_FilterValue, + 3, + 23, + 0, + 0, // Skip to: 45328 + /* 45305 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45308 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45318 + /* 45313 */ MCD_OPC_Decode, + 208, + 26, + 190, + 1, // Opcode: LDXPW + /* 45318 */ MCD_OPC_FilterValue, + 1, + 68, + 231, + 0, // Skip to: 104527 + /* 45323 */ MCD_OPC_Decode, + 159, + 24, + 190, + 1, // Opcode: LDAXPW + /* 45328 */ MCD_OPC_FilterValue, + 4, + 38, + 0, + 0, // Skip to: 45371 + /* 45333 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45336 */ MCD_OPC_FilterValue, + 0, + 15, + 0, + 0, // Skip to: 45356 + /* 45341 */ MCD_OPC_CheckPredicate, + 19, + 45, + 231, + 0, // Skip to: 104527 + /* 45346 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45351 */ MCD_OPC_Decode, + 170, + 39, + 190, + 1, // Opcode: STLLRW + /* 45356 */ MCD_OPC_FilterValue, + 1, + 30, + 231, + 0, // Skip to: 104527 + /* 45361 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45366 */ MCD_OPC_Decode, + 174, + 39, + 190, + 1, // Opcode: STLRW + /* 45371 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 45409 + /* 45376 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 45379 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 45394 + /* 45384 */ MCD_OPC_CheckPredicate, + 18, + 2, + 231, + 0, // Skip to: 104527 + /* 45389 */ MCD_OPC_Decode, + 170, + 9, + 192, + 1, // Opcode: CASW + /* 45394 */ MCD_OPC_FilterValue, + 63, + 248, + 230, + 0, // Skip to: 104527 + /* 45399 */ MCD_OPC_CheckPredicate, + 18, + 243, + 230, + 0, // Skip to: 104527 + /* 45404 */ MCD_OPC_Decode, + 160, + 9, + 192, + 1, // Opcode: CASLW + /* 45409 */ MCD_OPC_FilterValue, + 6, + 38, + 0, + 0, // Skip to: 45452 + /* 45414 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45417 */ MCD_OPC_FilterValue, + 0, + 15, + 0, + 0, // Skip to: 45437 + /* 45422 */ MCD_OPC_CheckPredicate, + 19, + 220, + 230, + 0, // Skip to: 104527 + /* 45427 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45432 */ MCD_OPC_Decode, + 217, + 24, + 190, + 1, // Opcode: LDLARW + /* 45437 */ MCD_OPC_FilterValue, + 1, + 205, + 230, + 0, // Skip to: 104527 + /* 45442 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45447 */ MCD_OPC_Decode, + 157, + 24, + 190, + 1, // Opcode: LDARW + /* 45452 */ MCD_OPC_FilterValue, + 7, + 190, + 230, + 0, // Skip to: 104527 + /* 45457 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 45460 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 45475 + /* 45465 */ MCD_OPC_CheckPredicate, + 18, + 177, + 230, + 0, // Skip to: 104527 + /* 45470 */ MCD_OPC_Decode, + 154, + 9, + 192, + 1, // Opcode: CASAW + /* 45475 */ MCD_OPC_FilterValue, + 63, + 167, + 230, + 0, // Skip to: 104527 + /* 45480 */ MCD_OPC_CheckPredicate, + 18, + 162, + 230, + 0, // Skip to: 104527 + /* 45485 */ MCD_OPC_Decode, + 152, + 9, + 192, + 1, // Opcode: CASALW + /* 45490 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 45518 + /* 45495 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 45498 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45508 + /* 45503 */ MCD_OPC_Decode, + 128, + 8, + 193, + 1, // Opcode: ANDXrs + /* 45508 */ MCD_OPC_FilterValue, + 1, + 134, + 230, + 0, // Skip to: 104527 + /* 45513 */ MCD_OPC_Decode, + 223, + 8, + 193, + 1, // Opcode: BICXrs + /* 45518 */ MCD_OPC_FilterValue, + 3, + 124, + 230, + 0, // Skip to: 104527 + /* 45523 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 45526 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45536 + /* 45531 */ MCD_OPC_Decode, + 195, + 7, + 193, + 1, // Opcode: ADDXrs + /* 45536 */ MCD_OPC_FilterValue, + 1, + 106, + 230, + 0, // Skip to: 104527 + /* 45541 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 45544 */ MCD_OPC_FilterValue, + 0, + 98, + 230, + 0, // Skip to: 104527 + /* 45549 */ MCD_OPC_CheckField, + 13, + 2, + 3, + 5, + 0, + 0, // Skip to: 45561 + /* 45556 */ MCD_OPC_Decode, + 197, + 7, + 194, + 1, // Opcode: ADDXrx64 + /* 45561 */ MCD_OPC_Decode, + 196, + 7, + 194, + 1, // Opcode: ADDXrx + /* 45566 */ MCD_OPC_FilterValue, + 5, + 175, + 0, + 0, // Skip to: 45746 + /* 45571 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 45574 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 45622 + /* 45579 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 45582 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45592 + /* 45587 */ MCD_OPC_Decode, + 190, + 39, + 195, + 1, // Opcode: STNPXi + /* 45592 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 45602 + /* 45597 */ MCD_OPC_Decode, + 239, + 24, + 195, + 1, // Opcode: LDNPXi + /* 45602 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 45612 + /* 45607 */ MCD_OPC_Decode, + 219, + 39, + 195, + 1, // Opcode: STPXpost + /* 45612 */ MCD_OPC_FilterValue, + 3, + 30, + 230, + 0, // Skip to: 104527 + /* 45617 */ MCD_OPC_Decode, + 148, + 25, + 195, + 1, // Opcode: LDPXpost + /* 45622 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 45670 + /* 45627 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 45630 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45640 + /* 45635 */ MCD_OPC_Decode, + 218, + 39, + 195, + 1, // Opcode: STPXi + /* 45640 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 45650 + /* 45645 */ MCD_OPC_Decode, + 147, + 25, + 195, + 1, // Opcode: LDPXi + /* 45650 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 45660 + /* 45655 */ MCD_OPC_Decode, + 220, + 39, + 195, + 1, // Opcode: STPXpre + /* 45660 */ MCD_OPC_FilterValue, + 3, + 238, + 229, + 0, // Skip to: 104527 + /* 45665 */ MCD_OPC_Decode, + 149, + 25, + 195, + 1, // Opcode: LDPXpre + /* 45670 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 45698 + /* 45675 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 45678 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45688 + /* 45683 */ MCD_OPC_Decode, + 150, + 28, + 193, + 1, // Opcode: ORRXrs + /* 45688 */ MCD_OPC_FilterValue, + 1, + 210, + 229, + 0, // Skip to: 104527 + /* 45693 */ MCD_OPC_Decode, + 142, + 28, + 193, + 1, // Opcode: ORNXrs + /* 45698 */ MCD_OPC_FilterValue, + 3, + 200, + 229, + 0, // Skip to: 104527 + /* 45703 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 45706 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45716 + /* 45711 */ MCD_OPC_Decode, + 180, + 7, + 193, + 1, // Opcode: ADDSXrs + /* 45716 */ MCD_OPC_FilterValue, + 1, + 182, + 229, + 0, // Skip to: 104527 + /* 45721 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 45724 */ MCD_OPC_FilterValue, + 0, + 174, + 229, + 0, // Skip to: 104527 + /* 45729 */ MCD_OPC_CheckField, + 13, + 2, + 3, + 5, + 0, + 0, // Skip to: 45741 + /* 45736 */ MCD_OPC_Decode, + 182, + 7, + 194, + 1, // Opcode: ADDSXrx64 + /* 45741 */ MCD_OPC_Decode, + 181, + 7, + 194, + 1, // Opcode: ADDSXrx + /* 45746 */ MCD_OPC_FilterValue, + 6, + 115, + 1, + 0, // Skip to: 46122 + /* 45751 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 45754 */ MCD_OPC_FilterValue, + 0, + 31, + 1, + 0, // Skip to: 46046 + /* 45759 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 45762 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 45790 + /* 45767 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45770 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45780 + /* 45775 */ MCD_OPC_Decode, + 159, + 40, + 190, + 1, // Opcode: STXRX + /* 45780 */ MCD_OPC_FilterValue, + 1, + 118, + 229, + 0, // Skip to: 104527 + /* 45785 */ MCD_OPC_Decode, + 185, + 39, + 190, + 1, // Opcode: STLXRX + /* 45790 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 45818 + /* 45795 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45798 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45808 + /* 45803 */ MCD_OPC_Decode, + 155, + 40, + 190, + 1, // Opcode: STXPX + /* 45808 */ MCD_OPC_FilterValue, + 1, + 90, + 229, + 0, // Skip to: 104527 + /* 45813 */ MCD_OPC_Decode, + 181, + 39, + 190, + 1, // Opcode: STLXPX + /* 45818 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 45856 + /* 45823 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45826 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 45841 + /* 45831 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45836 */ MCD_OPC_Decode, + 213, + 26, + 190, + 1, // Opcode: LDXRX + /* 45841 */ MCD_OPC_FilterValue, + 1, + 57, + 229, + 0, // Skip to: 104527 + /* 45846 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45851 */ MCD_OPC_Decode, + 164, + 24, + 190, + 1, // Opcode: LDAXRX + /* 45856 */ MCD_OPC_FilterValue, + 3, + 23, + 0, + 0, // Skip to: 45884 + /* 45861 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45864 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 45874 + /* 45869 */ MCD_OPC_Decode, + 209, + 26, + 190, + 1, // Opcode: LDXPX + /* 45874 */ MCD_OPC_FilterValue, + 1, + 24, + 229, + 0, // Skip to: 104527 + /* 45879 */ MCD_OPC_Decode, + 160, + 24, + 190, + 1, // Opcode: LDAXPX + /* 45884 */ MCD_OPC_FilterValue, + 4, + 38, + 0, + 0, // Skip to: 45927 + /* 45889 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45892 */ MCD_OPC_FilterValue, + 0, + 15, + 0, + 0, // Skip to: 45912 + /* 45897 */ MCD_OPC_CheckPredicate, + 19, + 1, + 229, + 0, // Skip to: 104527 + /* 45902 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45907 */ MCD_OPC_Decode, + 171, + 39, + 190, + 1, // Opcode: STLLRX + /* 45912 */ MCD_OPC_FilterValue, + 1, + 242, + 228, + 0, // Skip to: 104527 + /* 45917 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45922 */ MCD_OPC_Decode, + 175, + 39, + 190, + 1, // Opcode: STLRX + /* 45927 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 45965 + /* 45932 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 45935 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 45950 + /* 45940 */ MCD_OPC_CheckPredicate, + 18, + 214, + 228, + 0, // Skip to: 104527 + /* 45945 */ MCD_OPC_Decode, + 171, + 9, + 197, + 1, // Opcode: CASX + /* 45950 */ MCD_OPC_FilterValue, + 63, + 204, + 228, + 0, // Skip to: 104527 + /* 45955 */ MCD_OPC_CheckPredicate, + 18, + 199, + 228, + 0, // Skip to: 104527 + /* 45960 */ MCD_OPC_Decode, + 161, + 9, + 197, + 1, // Opcode: CASLX + /* 45965 */ MCD_OPC_FilterValue, + 6, + 38, + 0, + 0, // Skip to: 46008 + /* 45970 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 45973 */ MCD_OPC_FilterValue, + 0, + 15, + 0, + 0, // Skip to: 45993 + /* 45978 */ MCD_OPC_CheckPredicate, + 19, + 176, + 228, + 0, // Skip to: 104527 + /* 45983 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 45988 */ MCD_OPC_Decode, + 218, + 24, + 190, + 1, // Opcode: LDLARX + /* 45993 */ MCD_OPC_FilterValue, + 1, + 161, + 228, + 0, // Skip to: 104527 + /* 45998 */ MCD_OPC_SoftFail, + 0, + 128, + 248, + 125 /* 0x1f7c00 */, + /* 46003 */ MCD_OPC_Decode, + 158, + 24, + 190, + 1, // Opcode: LDARX + /* 46008 */ MCD_OPC_FilterValue, + 7, + 146, + 228, + 0, // Skip to: 104527 + /* 46013 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 46016 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 46031 + /* 46021 */ MCD_OPC_CheckPredicate, + 18, + 133, + 228, + 0, // Skip to: 104527 + /* 46026 */ MCD_OPC_Decode, + 155, + 9, + 197, + 1, // Opcode: CASAX + /* 46031 */ MCD_OPC_FilterValue, + 63, + 123, + 228, + 0, // Skip to: 104527 + /* 46036 */ MCD_OPC_CheckPredicate, + 18, + 118, + 228, + 0, // Skip to: 104527 + /* 46041 */ MCD_OPC_Decode, + 153, + 9, + 197, + 1, // Opcode: CASALX + /* 46046 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 46074 + /* 46051 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 46054 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 46064 + /* 46059 */ MCD_OPC_Decode, + 171, + 12, + 193, + 1, // Opcode: EORXrs + /* 46064 */ MCD_OPC_FilterValue, + 1, + 90, + 228, + 0, // Skip to: 104527 + /* 46069 */ MCD_OPC_Decode, + 152, + 12, + 193, + 1, // Opcode: EONXrs + /* 46074 */ MCD_OPC_FilterValue, + 3, + 80, + 228, + 0, // Skip to: 104527 + /* 46079 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 46082 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 46092 + /* 46087 */ MCD_OPC_Decode, + 201, + 40, + 193, + 1, // Opcode: SUBXrs + /* 46092 */ MCD_OPC_FilterValue, + 1, + 62, + 228, + 0, // Skip to: 104527 + /* 46097 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 46100 */ MCD_OPC_FilterValue, + 0, + 54, + 228, + 0, // Skip to: 104527 + /* 46105 */ MCD_OPC_CheckField, + 13, + 2, + 3, + 5, + 0, + 0, // Skip to: 46117 + /* 46112 */ MCD_OPC_Decode, + 203, + 40, + 194, + 1, // Opcode: SUBXrx64 + /* 46117 */ MCD_OPC_Decode, + 202, + 40, + 194, + 1, // Opcode: SUBXrx + /* 46122 */ MCD_OPC_FilterValue, + 7, + 32, + 228, + 0, // Skip to: 104527 + /* 46127 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 46130 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 46158 + /* 46135 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 46138 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 46148 + /* 46143 */ MCD_OPC_Decode, + 247, + 7, + 193, + 1, // Opcode: ANDSXrs + /* 46148 */ MCD_OPC_FilterValue, + 3, + 6, + 228, + 0, // Skip to: 104527 + /* 46153 */ MCD_OPC_Decode, + 194, + 40, + 193, + 1, // Opcode: SUBSXrs + /* 46158 */ MCD_OPC_FilterValue, + 1, + 252, + 227, + 0, // Skip to: 104527 + /* 46163 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 46166 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 46176 + /* 46171 */ MCD_OPC_Decode, + 220, + 8, + 193, + 1, // Opcode: BICSXrs + /* 46176 */ MCD_OPC_FilterValue, + 3, + 234, + 227, + 0, // Skip to: 104527 + /* 46181 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 46184 */ MCD_OPC_FilterValue, + 0, + 226, + 227, + 0, // Skip to: 104527 + /* 46189 */ MCD_OPC_CheckField, + 13, + 2, + 3, + 5, + 0, + 0, // Skip to: 46201 + /* 46196 */ MCD_OPC_Decode, + 196, + 40, + 194, + 1, // Opcode: SUBSXrx64 + /* 46201 */ MCD_OPC_Decode, + 195, + 40, + 194, + 1, // Opcode: SUBSXrx + /* 46206 */ MCD_OPC_FilterValue, + 3, + 32, + 150, + 0, // Skip to: 84643 + /* 46211 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 46214 */ MCD_OPC_FilterValue, + 0, + 76, + 3, + 0, // Skip to: 47063 + /* 46219 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 46222 */ MCD_OPC_FilterValue, + 0, + 122, + 1, + 0, // Skip to: 46605 + /* 46227 */ MCD_OPC_ExtractField, + 10, + 12, // Inst{21-10} ... + /* 46230 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 46245 + /* 46235 */ MCD_OPC_CheckPredicate, + 21, + 175, + 227, + 0, // Skip to: 104527 + /* 46240 */ MCD_OPC_Decode, + 142, + 39, + 198, + 1, // Opcode: ST4Fourv8b + /* 46245 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 46260 + /* 46250 */ MCD_OPC_CheckPredicate, + 21, + 160, + 227, + 0, // Skip to: 104527 + /* 46255 */ MCD_OPC_Decode, + 138, + 39, + 198, + 1, // Opcode: ST4Fourv4h + /* 46260 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 46275 + /* 46265 */ MCD_OPC_CheckPredicate, + 21, + 145, + 227, + 0, // Skip to: 104527 + /* 46270 */ MCD_OPC_Decode, + 136, + 39, + 198, + 1, // Opcode: ST4Fourv2s + /* 46275 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 46290 + /* 46280 */ MCD_OPC_CheckPredicate, + 21, + 130, + 227, + 0, // Skip to: 104527 + /* 46285 */ MCD_OPC_Decode, + 241, + 37, + 198, + 1, // Opcode: ST1Fourv8b + /* 46290 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 46305 + /* 46295 */ MCD_OPC_CheckPredicate, + 21, + 115, + 227, + 0, // Skip to: 104527 + /* 46300 */ MCD_OPC_Decode, + 237, + 37, + 198, + 1, // Opcode: ST1Fourv4h + /* 46305 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 46320 + /* 46310 */ MCD_OPC_CheckPredicate, + 21, + 100, + 227, + 0, // Skip to: 104527 + /* 46315 */ MCD_OPC_Decode, + 235, + 37, + 198, + 1, // Opcode: ST1Fourv2s + /* 46320 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 46335 + /* 46325 */ MCD_OPC_CheckPredicate, + 21, + 85, + 227, + 0, // Skip to: 104527 + /* 46330 */ MCD_OPC_Decode, + 231, + 37, + 198, + 1, // Opcode: ST1Fourv1d + /* 46335 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 46350 + /* 46340 */ MCD_OPC_CheckPredicate, + 21, + 70, + 227, + 0, // Skip to: 104527 + /* 46345 */ MCD_OPC_Decode, + 242, + 38, + 199, + 1, // Opcode: ST3Threev8b + /* 46350 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 46365 + /* 46355 */ MCD_OPC_CheckPredicate, + 21, + 55, + 227, + 0, // Skip to: 104527 + /* 46360 */ MCD_OPC_Decode, + 238, + 38, + 199, + 1, // Opcode: ST3Threev4h + /* 46365 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 46380 + /* 46370 */ MCD_OPC_CheckPredicate, + 21, + 40, + 227, + 0, // Skip to: 104527 + /* 46375 */ MCD_OPC_Decode, + 236, + 38, + 199, + 1, // Opcode: ST3Threev2s + /* 46380 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 46395 + /* 46385 */ MCD_OPC_CheckPredicate, + 21, + 25, + 227, + 0, // Skip to: 104527 + /* 46390 */ MCD_OPC_Decode, + 151, + 38, + 199, + 1, // Opcode: ST1Threev8b + /* 46395 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 46410 + /* 46400 */ MCD_OPC_CheckPredicate, + 21, + 10, + 227, + 0, // Skip to: 104527 + /* 46405 */ MCD_OPC_Decode, + 147, + 38, + 199, + 1, // Opcode: ST1Threev4h + /* 46410 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 46425 + /* 46415 */ MCD_OPC_CheckPredicate, + 21, + 251, + 226, + 0, // Skip to: 104527 + /* 46420 */ MCD_OPC_Decode, + 145, + 38, + 199, + 1, // Opcode: ST1Threev2s + /* 46425 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 46440 + /* 46430 */ MCD_OPC_CheckPredicate, + 21, + 236, + 226, + 0, // Skip to: 104527 + /* 46435 */ MCD_OPC_Decode, + 141, + 38, + 199, + 1, // Opcode: ST1Threev1d + /* 46440 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 46455 + /* 46445 */ MCD_OPC_CheckPredicate, + 21, + 221, + 226, + 0, // Skip to: 104527 + /* 46450 */ MCD_OPC_Decode, + 135, + 38, + 200, + 1, // Opcode: ST1Onev8b + /* 46455 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 46470 + /* 46460 */ MCD_OPC_CheckPredicate, + 21, + 206, + 226, + 0, // Skip to: 104527 + /* 46465 */ MCD_OPC_Decode, + 131, + 38, + 200, + 1, // Opcode: ST1Onev4h + /* 46470 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 46485 + /* 46475 */ MCD_OPC_CheckPredicate, + 21, + 191, + 226, + 0, // Skip to: 104527 + /* 46480 */ MCD_OPC_Decode, + 129, + 38, + 200, + 1, // Opcode: ST1Onev2s + /* 46485 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 46500 + /* 46490 */ MCD_OPC_CheckPredicate, + 21, + 176, + 226, + 0, // Skip to: 104527 + /* 46495 */ MCD_OPC_Decode, + 253, + 37, + 200, + 1, // Opcode: ST1Onev1d + /* 46500 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 46515 + /* 46505 */ MCD_OPC_CheckPredicate, + 21, + 161, + 226, + 0, // Skip to: 104527 + /* 46510 */ MCD_OPC_Decode, + 212, + 38, + 201, + 1, // Opcode: ST2Twov8b + /* 46515 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 46530 + /* 46520 */ MCD_OPC_CheckPredicate, + 21, + 146, + 226, + 0, // Skip to: 104527 + /* 46525 */ MCD_OPC_Decode, + 208, + 38, + 201, + 1, // Opcode: ST2Twov4h + /* 46530 */ MCD_OPC_FilterValue, + 34, + 10, + 0, + 0, // Skip to: 46545 + /* 46535 */ MCD_OPC_CheckPredicate, + 21, + 131, + 226, + 0, // Skip to: 104527 + /* 46540 */ MCD_OPC_Decode, + 206, + 38, + 201, + 1, // Opcode: ST2Twov2s + /* 46545 */ MCD_OPC_FilterValue, + 40, + 10, + 0, + 0, // Skip to: 46560 + /* 46550 */ MCD_OPC_CheckPredicate, + 21, + 116, + 226, + 0, // Skip to: 104527 + /* 46555 */ MCD_OPC_Decode, + 167, + 38, + 201, + 1, // Opcode: ST1Twov8b + /* 46560 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 46575 + /* 46565 */ MCD_OPC_CheckPredicate, + 21, + 101, + 226, + 0, // Skip to: 104527 + /* 46570 */ MCD_OPC_Decode, + 163, + 38, + 201, + 1, // Opcode: ST1Twov4h + /* 46575 */ MCD_OPC_FilterValue, + 42, + 10, + 0, + 0, // Skip to: 46590 + /* 46580 */ MCD_OPC_CheckPredicate, + 21, + 86, + 226, + 0, // Skip to: 104527 + /* 46585 */ MCD_OPC_Decode, + 161, + 38, + 201, + 1, // Opcode: ST1Twov2s + /* 46590 */ MCD_OPC_FilterValue, + 43, + 76, + 226, + 0, // Skip to: 104527 + /* 46595 */ MCD_OPC_CheckPredicate, + 21, + 71, + 226, + 0, // Skip to: 104527 + /* 46600 */ MCD_OPC_Decode, + 157, + 38, + 201, + 1, // Opcode: ST1Twov1d + /* 46605 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 46615 + /* 46610 */ MCD_OPC_Decode, + 188, + 39, + 195, + 1, // Opcode: STNPSi + /* 46615 */ MCD_OPC_FilterValue, + 2, + 167, + 1, + 0, // Skip to: 47043 + /* 46620 */ MCD_OPC_ExtractField, + 10, + 12, // Inst{21-10} ... + /* 46623 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 46638 + /* 46628 */ MCD_OPC_CheckPredicate, + 21, + 38, + 226, + 0, // Skip to: 104527 + /* 46633 */ MCD_OPC_Decode, + 132, + 39, + 202, + 1, // Opcode: ST4Fourv16b + /* 46638 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 46653 + /* 46643 */ MCD_OPC_CheckPredicate, + 21, + 23, + 226, + 0, // Skip to: 104527 + /* 46648 */ MCD_OPC_Decode, + 144, + 39, + 202, + 1, // Opcode: ST4Fourv8h + /* 46653 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 46668 + /* 46658 */ MCD_OPC_CheckPredicate, + 21, + 8, + 226, + 0, // Skip to: 104527 + /* 46663 */ MCD_OPC_Decode, + 140, + 39, + 202, + 1, // Opcode: ST4Fourv4s + /* 46668 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 46683 + /* 46673 */ MCD_OPC_CheckPredicate, + 21, + 249, + 225, + 0, // Skip to: 104527 + /* 46678 */ MCD_OPC_Decode, + 134, + 39, + 202, + 1, // Opcode: ST4Fourv2d + /* 46683 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 46698 + /* 46688 */ MCD_OPC_CheckPredicate, + 21, + 234, + 225, + 0, // Skip to: 104527 + /* 46693 */ MCD_OPC_Decode, + 229, + 37, + 202, + 1, // Opcode: ST1Fourv16b + /* 46698 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 46713 + /* 46703 */ MCD_OPC_CheckPredicate, + 21, + 219, + 225, + 0, // Skip to: 104527 + /* 46708 */ MCD_OPC_Decode, + 243, + 37, + 202, + 1, // Opcode: ST1Fourv8h + /* 46713 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 46728 + /* 46718 */ MCD_OPC_CheckPredicate, + 21, + 204, + 225, + 0, // Skip to: 104527 + /* 46723 */ MCD_OPC_Decode, + 239, + 37, + 202, + 1, // Opcode: ST1Fourv4s + /* 46728 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 46743 + /* 46733 */ MCD_OPC_CheckPredicate, + 21, + 189, + 225, + 0, // Skip to: 104527 + /* 46738 */ MCD_OPC_Decode, + 233, + 37, + 202, + 1, // Opcode: ST1Fourv2d + /* 46743 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 46758 + /* 46748 */ MCD_OPC_CheckPredicate, + 21, + 174, + 225, + 0, // Skip to: 104527 + /* 46753 */ MCD_OPC_Decode, + 232, + 38, + 203, + 1, // Opcode: ST3Threev16b + /* 46758 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 46773 + /* 46763 */ MCD_OPC_CheckPredicate, + 21, + 159, + 225, + 0, // Skip to: 104527 + /* 46768 */ MCD_OPC_Decode, + 244, + 38, + 203, + 1, // Opcode: ST3Threev8h + /* 46773 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 46788 + /* 46778 */ MCD_OPC_CheckPredicate, + 21, + 144, + 225, + 0, // Skip to: 104527 + /* 46783 */ MCD_OPC_Decode, + 240, + 38, + 203, + 1, // Opcode: ST3Threev4s + /* 46788 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 46803 + /* 46793 */ MCD_OPC_CheckPredicate, + 21, + 129, + 225, + 0, // Skip to: 104527 + /* 46798 */ MCD_OPC_Decode, + 234, + 38, + 203, + 1, // Opcode: ST3Threev2d + /* 46803 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 46818 + /* 46808 */ MCD_OPC_CheckPredicate, + 21, + 114, + 225, + 0, // Skip to: 104527 + /* 46813 */ MCD_OPC_Decode, + 139, + 38, + 203, + 1, // Opcode: ST1Threev16b + /* 46818 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 46833 + /* 46823 */ MCD_OPC_CheckPredicate, + 21, + 99, + 225, + 0, // Skip to: 104527 + /* 46828 */ MCD_OPC_Decode, + 153, + 38, + 203, + 1, // Opcode: ST1Threev8h + /* 46833 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 46848 + /* 46838 */ MCD_OPC_CheckPredicate, + 21, + 84, + 225, + 0, // Skip to: 104527 + /* 46843 */ MCD_OPC_Decode, + 149, + 38, + 203, + 1, // Opcode: ST1Threev4s + /* 46848 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 46863 + /* 46853 */ MCD_OPC_CheckPredicate, + 21, + 69, + 225, + 0, // Skip to: 104527 + /* 46858 */ MCD_OPC_Decode, + 143, + 38, + 203, + 1, // Opcode: ST1Threev2d + /* 46863 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 46878 + /* 46868 */ MCD_OPC_CheckPredicate, + 21, + 54, + 225, + 0, // Skip to: 104527 + /* 46873 */ MCD_OPC_Decode, + 251, + 37, + 204, + 1, // Opcode: ST1Onev16b + /* 46878 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 46893 + /* 46883 */ MCD_OPC_CheckPredicate, + 21, + 39, + 225, + 0, // Skip to: 104527 + /* 46888 */ MCD_OPC_Decode, + 137, + 38, + 204, + 1, // Opcode: ST1Onev8h + /* 46893 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 46908 + /* 46898 */ MCD_OPC_CheckPredicate, + 21, + 24, + 225, + 0, // Skip to: 104527 + /* 46903 */ MCD_OPC_Decode, + 133, + 38, + 204, + 1, // Opcode: ST1Onev4s + /* 46908 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 46923 + /* 46913 */ MCD_OPC_CheckPredicate, + 21, + 9, + 225, + 0, // Skip to: 104527 + /* 46918 */ MCD_OPC_Decode, + 255, + 37, + 204, + 1, // Opcode: ST1Onev2d + /* 46923 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 46938 + /* 46928 */ MCD_OPC_CheckPredicate, + 21, + 250, + 224, + 0, // Skip to: 104527 + /* 46933 */ MCD_OPC_Decode, + 202, + 38, + 205, + 1, // Opcode: ST2Twov16b + /* 46938 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 46953 + /* 46943 */ MCD_OPC_CheckPredicate, + 21, + 235, + 224, + 0, // Skip to: 104527 + /* 46948 */ MCD_OPC_Decode, + 214, + 38, + 205, + 1, // Opcode: ST2Twov8h + /* 46953 */ MCD_OPC_FilterValue, + 34, + 10, + 0, + 0, // Skip to: 46968 + /* 46958 */ MCD_OPC_CheckPredicate, + 21, + 220, + 224, + 0, // Skip to: 104527 + /* 46963 */ MCD_OPC_Decode, + 210, + 38, + 205, + 1, // Opcode: ST2Twov4s + /* 46968 */ MCD_OPC_FilterValue, + 35, + 10, + 0, + 0, // Skip to: 46983 + /* 46973 */ MCD_OPC_CheckPredicate, + 21, + 205, + 224, + 0, // Skip to: 104527 + /* 46978 */ MCD_OPC_Decode, + 204, + 38, + 205, + 1, // Opcode: ST2Twov2d + /* 46983 */ MCD_OPC_FilterValue, + 40, + 10, + 0, + 0, // Skip to: 46998 + /* 46988 */ MCD_OPC_CheckPredicate, + 21, + 190, + 224, + 0, // Skip to: 104527 + /* 46993 */ MCD_OPC_Decode, + 155, + 38, + 205, + 1, // Opcode: ST1Twov16b + /* 46998 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 47013 + /* 47003 */ MCD_OPC_CheckPredicate, + 21, + 175, + 224, + 0, // Skip to: 104527 + /* 47008 */ MCD_OPC_Decode, + 169, + 38, + 205, + 1, // Opcode: ST1Twov8h + /* 47013 */ MCD_OPC_FilterValue, + 42, + 10, + 0, + 0, // Skip to: 47028 + /* 47018 */ MCD_OPC_CheckPredicate, + 21, + 160, + 224, + 0, // Skip to: 104527 + /* 47023 */ MCD_OPC_Decode, + 165, + 38, + 205, + 1, // Opcode: ST1Twov4s + /* 47028 */ MCD_OPC_FilterValue, + 43, + 150, + 224, + 0, // Skip to: 104527 + /* 47033 */ MCD_OPC_CheckPredicate, + 21, + 145, + 224, + 0, // Skip to: 104527 + /* 47038 */ MCD_OPC_Decode, + 159, + 38, + 205, + 1, // Opcode: ST1Twov2d + /* 47043 */ MCD_OPC_FilterValue, + 3, + 5, + 0, + 0, // Skip to: 47053 + /* 47048 */ MCD_OPC_Decode, + 186, + 39, + 195, + 1, // Opcode: STNPDi + /* 47053 */ MCD_OPC_FilterValue, + 5, + 125, + 224, + 0, // Skip to: 104527 + /* 47058 */ MCD_OPC_Decode, + 187, + 39, + 195, + 1, // Opcode: STNPQi + /* 47063 */ MCD_OPC_FilterValue, + 1, + 76, + 3, + 0, // Skip to: 47912 + /* 47068 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 47071 */ MCD_OPC_FilterValue, + 0, + 122, + 1, + 0, // Skip to: 47454 + /* 47076 */ MCD_OPC_ExtractField, + 10, + 12, // Inst{21-10} ... + /* 47079 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 47094 + /* 47084 */ MCD_OPC_CheckPredicate, + 21, + 94, + 224, + 0, // Skip to: 104527 + /* 47089 */ MCD_OPC_Decode, + 221, + 23, + 198, + 1, // Opcode: LD4Fourv8b + /* 47094 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 47109 + /* 47099 */ MCD_OPC_CheckPredicate, + 21, + 79, + 224, + 0, // Skip to: 104527 + /* 47104 */ MCD_OPC_Decode, + 217, + 23, + 198, + 1, // Opcode: LD4Fourv4h + /* 47109 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 47124 + /* 47114 */ MCD_OPC_CheckPredicate, + 21, + 64, + 224, + 0, // Skip to: 104527 + /* 47119 */ MCD_OPC_Decode, + 215, + 23, + 198, + 1, // Opcode: LD4Fourv2s + /* 47124 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 47139 + /* 47129 */ MCD_OPC_CheckPredicate, + 21, + 49, + 224, + 0, // Skip to: 104527 + /* 47134 */ MCD_OPC_Decode, + 231, + 21, + 198, + 1, // Opcode: LD1Fourv8b + /* 47139 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 47154 + /* 47144 */ MCD_OPC_CheckPredicate, + 21, + 34, + 224, + 0, // Skip to: 104527 + /* 47149 */ MCD_OPC_Decode, + 227, + 21, + 198, + 1, // Opcode: LD1Fourv4h + /* 47154 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 47169 + /* 47159 */ MCD_OPC_CheckPredicate, + 21, + 19, + 224, + 0, // Skip to: 104527 + /* 47164 */ MCD_OPC_Decode, + 225, + 21, + 198, + 1, // Opcode: LD1Fourv2s + /* 47169 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 47184 + /* 47174 */ MCD_OPC_CheckPredicate, + 21, + 4, + 224, + 0, // Skip to: 104527 + /* 47179 */ MCD_OPC_Decode, + 221, + 21, + 198, + 1, // Opcode: LD1Fourv1d + /* 47184 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 47199 + /* 47189 */ MCD_OPC_CheckPredicate, + 21, + 245, + 223, + 0, // Skip to: 104527 + /* 47194 */ MCD_OPC_Decode, + 193, + 23, + 199, + 1, // Opcode: LD3Threev8b + /* 47199 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 47214 + /* 47204 */ MCD_OPC_CheckPredicate, + 21, + 230, + 223, + 0, // Skip to: 104527 + /* 47209 */ MCD_OPC_Decode, + 189, + 23, + 199, + 1, // Opcode: LD3Threev4h + /* 47214 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 47229 + /* 47219 */ MCD_OPC_CheckPredicate, + 21, + 215, + 223, + 0, // Skip to: 104527 + /* 47224 */ MCD_OPC_Decode, + 187, + 23, + 199, + 1, // Opcode: LD3Threev2s + /* 47229 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 47244 + /* 47234 */ MCD_OPC_CheckPredicate, + 21, + 200, + 223, + 0, // Skip to: 104527 + /* 47239 */ MCD_OPC_Decode, + 201, + 22, + 199, + 1, // Opcode: LD1Threev8b + /* 47244 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 47259 + /* 47249 */ MCD_OPC_CheckPredicate, + 21, + 185, + 223, + 0, // Skip to: 104527 + /* 47254 */ MCD_OPC_Decode, + 197, + 22, + 199, + 1, // Opcode: LD1Threev4h + /* 47259 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 47274 + /* 47264 */ MCD_OPC_CheckPredicate, + 21, + 170, + 223, + 0, // Skip to: 104527 + /* 47269 */ MCD_OPC_Decode, + 195, + 22, + 199, + 1, // Opcode: LD1Threev2s + /* 47274 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 47289 + /* 47279 */ MCD_OPC_CheckPredicate, + 21, + 155, + 223, + 0, // Skip to: 104527 + /* 47284 */ MCD_OPC_Decode, + 191, + 22, + 199, + 1, // Opcode: LD1Threev1d + /* 47289 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 47304 + /* 47294 */ MCD_OPC_CheckPredicate, + 21, + 140, + 223, + 0, // Skip to: 104527 + /* 47299 */ MCD_OPC_Decode, + 253, + 21, + 200, + 1, // Opcode: LD1Onev8b + /* 47304 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 47319 + /* 47309 */ MCD_OPC_CheckPredicate, + 21, + 125, + 223, + 0, // Skip to: 104527 + /* 47314 */ MCD_OPC_Decode, + 249, + 21, + 200, + 1, // Opcode: LD1Onev4h + /* 47319 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 47334 + /* 47324 */ MCD_OPC_CheckPredicate, + 21, + 110, + 223, + 0, // Skip to: 104527 + /* 47329 */ MCD_OPC_Decode, + 247, + 21, + 200, + 1, // Opcode: LD1Onev2s + /* 47334 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 47349 + /* 47339 */ MCD_OPC_CheckPredicate, + 21, + 95, + 223, + 0, // Skip to: 104527 + /* 47344 */ MCD_OPC_Decode, + 243, + 21, + 200, + 1, // Opcode: LD1Onev1d + /* 47349 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 47364 + /* 47354 */ MCD_OPC_CheckPredicate, + 21, + 80, + 223, + 0, // Skip to: 104527 + /* 47359 */ MCD_OPC_Decode, + 147, + 23, + 201, + 1, // Opcode: LD2Twov8b + /* 47364 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 47379 + /* 47369 */ MCD_OPC_CheckPredicate, + 21, + 65, + 223, + 0, // Skip to: 104527 + /* 47374 */ MCD_OPC_Decode, + 143, + 23, + 201, + 1, // Opcode: LD2Twov4h + /* 47379 */ MCD_OPC_FilterValue, + 34, + 10, + 0, + 0, // Skip to: 47394 + /* 47384 */ MCD_OPC_CheckPredicate, + 21, + 50, + 223, + 0, // Skip to: 104527 + /* 47389 */ MCD_OPC_Decode, + 141, + 23, + 201, + 1, // Opcode: LD2Twov2s + /* 47394 */ MCD_OPC_FilterValue, + 40, + 10, + 0, + 0, // Skip to: 47409 + /* 47399 */ MCD_OPC_CheckPredicate, + 21, + 35, + 223, + 0, // Skip to: 104527 + /* 47404 */ MCD_OPC_Decode, + 217, + 22, + 201, + 1, // Opcode: LD1Twov8b + /* 47409 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 47424 + /* 47414 */ MCD_OPC_CheckPredicate, + 21, + 20, + 223, + 0, // Skip to: 104527 + /* 47419 */ MCD_OPC_Decode, + 213, + 22, + 201, + 1, // Opcode: LD1Twov4h + /* 47424 */ MCD_OPC_FilterValue, + 42, + 10, + 0, + 0, // Skip to: 47439 + /* 47429 */ MCD_OPC_CheckPredicate, + 21, + 5, + 223, + 0, // Skip to: 104527 + /* 47434 */ MCD_OPC_Decode, + 211, + 22, + 201, + 1, // Opcode: LD1Twov2s + /* 47439 */ MCD_OPC_FilterValue, + 43, + 251, + 222, + 0, // Skip to: 104527 + /* 47444 */ MCD_OPC_CheckPredicate, + 21, + 246, + 222, + 0, // Skip to: 104527 + /* 47449 */ MCD_OPC_Decode, + 207, + 22, + 201, + 1, // Opcode: LD1Twov1d + /* 47454 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 47464 + /* 47459 */ MCD_OPC_Decode, + 237, + 24, + 195, + 1, // Opcode: LDNPSi + /* 47464 */ MCD_OPC_FilterValue, + 2, + 167, + 1, + 0, // Skip to: 47892 + /* 47469 */ MCD_OPC_ExtractField, + 10, + 12, // Inst{21-10} ... + /* 47472 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 47487 + /* 47477 */ MCD_OPC_CheckPredicate, + 21, + 213, + 222, + 0, // Skip to: 104527 + /* 47482 */ MCD_OPC_Decode, + 211, + 23, + 202, + 1, // Opcode: LD4Fourv16b + /* 47487 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 47502 + /* 47492 */ MCD_OPC_CheckPredicate, + 21, + 198, + 222, + 0, // Skip to: 104527 + /* 47497 */ MCD_OPC_Decode, + 223, + 23, + 202, + 1, // Opcode: LD4Fourv8h + /* 47502 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 47517 + /* 47507 */ MCD_OPC_CheckPredicate, + 21, + 183, + 222, + 0, // Skip to: 104527 + /* 47512 */ MCD_OPC_Decode, + 219, + 23, + 202, + 1, // Opcode: LD4Fourv4s + /* 47517 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 47532 + /* 47522 */ MCD_OPC_CheckPredicate, + 21, + 168, + 222, + 0, // Skip to: 104527 + /* 47527 */ MCD_OPC_Decode, + 213, + 23, + 202, + 1, // Opcode: LD4Fourv2d + /* 47532 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 47547 + /* 47537 */ MCD_OPC_CheckPredicate, + 21, + 153, + 222, + 0, // Skip to: 104527 + /* 47542 */ MCD_OPC_Decode, + 219, + 21, + 202, + 1, // Opcode: LD1Fourv16b + /* 47547 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 47562 + /* 47552 */ MCD_OPC_CheckPredicate, + 21, + 138, + 222, + 0, // Skip to: 104527 + /* 47557 */ MCD_OPC_Decode, + 233, + 21, + 202, + 1, // Opcode: LD1Fourv8h + /* 47562 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 47577 + /* 47567 */ MCD_OPC_CheckPredicate, + 21, + 123, + 222, + 0, // Skip to: 104527 + /* 47572 */ MCD_OPC_Decode, + 229, + 21, + 202, + 1, // Opcode: LD1Fourv4s + /* 47577 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 47592 + /* 47582 */ MCD_OPC_CheckPredicate, + 21, + 108, + 222, + 0, // Skip to: 104527 + /* 47587 */ MCD_OPC_Decode, + 223, + 21, + 202, + 1, // Opcode: LD1Fourv2d + /* 47592 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 47607 + /* 47597 */ MCD_OPC_CheckPredicate, + 21, + 93, + 222, + 0, // Skip to: 104527 + /* 47602 */ MCD_OPC_Decode, + 183, + 23, + 203, + 1, // Opcode: LD3Threev16b + /* 47607 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 47622 + /* 47612 */ MCD_OPC_CheckPredicate, + 21, + 78, + 222, + 0, // Skip to: 104527 + /* 47617 */ MCD_OPC_Decode, + 195, + 23, + 203, + 1, // Opcode: LD3Threev8h + /* 47622 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 47637 + /* 47627 */ MCD_OPC_CheckPredicate, + 21, + 63, + 222, + 0, // Skip to: 104527 + /* 47632 */ MCD_OPC_Decode, + 191, + 23, + 203, + 1, // Opcode: LD3Threev4s + /* 47637 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 47652 + /* 47642 */ MCD_OPC_CheckPredicate, + 21, + 48, + 222, + 0, // Skip to: 104527 + /* 47647 */ MCD_OPC_Decode, + 185, + 23, + 203, + 1, // Opcode: LD3Threev2d + /* 47652 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 47667 + /* 47657 */ MCD_OPC_CheckPredicate, + 21, + 33, + 222, + 0, // Skip to: 104527 + /* 47662 */ MCD_OPC_Decode, + 189, + 22, + 203, + 1, // Opcode: LD1Threev16b + /* 47667 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 47682 + /* 47672 */ MCD_OPC_CheckPredicate, + 21, + 18, + 222, + 0, // Skip to: 104527 + /* 47677 */ MCD_OPC_Decode, + 203, + 22, + 203, + 1, // Opcode: LD1Threev8h + /* 47682 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 47697 + /* 47687 */ MCD_OPC_CheckPredicate, + 21, + 3, + 222, + 0, // Skip to: 104527 + /* 47692 */ MCD_OPC_Decode, + 199, + 22, + 203, + 1, // Opcode: LD1Threev4s + /* 47697 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 47712 + /* 47702 */ MCD_OPC_CheckPredicate, + 21, + 244, + 221, + 0, // Skip to: 104527 + /* 47707 */ MCD_OPC_Decode, + 193, + 22, + 203, + 1, // Opcode: LD1Threev2d + /* 47712 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 47727 + /* 47717 */ MCD_OPC_CheckPredicate, + 21, + 229, + 221, + 0, // Skip to: 104527 + /* 47722 */ MCD_OPC_Decode, + 241, + 21, + 204, + 1, // Opcode: LD1Onev16b + /* 47727 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 47742 + /* 47732 */ MCD_OPC_CheckPredicate, + 21, + 214, + 221, + 0, // Skip to: 104527 + /* 47737 */ MCD_OPC_Decode, + 255, + 21, + 204, + 1, // Opcode: LD1Onev8h + /* 47742 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 47757 + /* 47747 */ MCD_OPC_CheckPredicate, + 21, + 199, + 221, + 0, // Skip to: 104527 + /* 47752 */ MCD_OPC_Decode, + 251, + 21, + 204, + 1, // Opcode: LD1Onev4s + /* 47757 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 47772 + /* 47762 */ MCD_OPC_CheckPredicate, + 21, + 184, + 221, + 0, // Skip to: 104527 + /* 47767 */ MCD_OPC_Decode, + 245, + 21, + 204, + 1, // Opcode: LD1Onev2d + /* 47772 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 47787 + /* 47777 */ MCD_OPC_CheckPredicate, + 21, + 169, + 221, + 0, // Skip to: 104527 + /* 47782 */ MCD_OPC_Decode, + 137, + 23, + 205, + 1, // Opcode: LD2Twov16b + /* 47787 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 47802 + /* 47792 */ MCD_OPC_CheckPredicate, + 21, + 154, + 221, + 0, // Skip to: 104527 + /* 47797 */ MCD_OPC_Decode, + 149, + 23, + 205, + 1, // Opcode: LD2Twov8h + /* 47802 */ MCD_OPC_FilterValue, + 34, + 10, + 0, + 0, // Skip to: 47817 + /* 47807 */ MCD_OPC_CheckPredicate, + 21, + 139, + 221, + 0, // Skip to: 104527 + /* 47812 */ MCD_OPC_Decode, + 145, + 23, + 205, + 1, // Opcode: LD2Twov4s + /* 47817 */ MCD_OPC_FilterValue, + 35, + 10, + 0, + 0, // Skip to: 47832 + /* 47822 */ MCD_OPC_CheckPredicate, + 21, + 124, + 221, + 0, // Skip to: 104527 + /* 47827 */ MCD_OPC_Decode, + 139, + 23, + 205, + 1, // Opcode: LD2Twov2d + /* 47832 */ MCD_OPC_FilterValue, + 40, + 10, + 0, + 0, // Skip to: 47847 + /* 47837 */ MCD_OPC_CheckPredicate, + 21, + 109, + 221, + 0, // Skip to: 104527 + /* 47842 */ MCD_OPC_Decode, + 205, + 22, + 205, + 1, // Opcode: LD1Twov16b + /* 47847 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 47862 + /* 47852 */ MCD_OPC_CheckPredicate, + 21, + 94, + 221, + 0, // Skip to: 104527 + /* 47857 */ MCD_OPC_Decode, + 219, + 22, + 205, + 1, // Opcode: LD1Twov8h + /* 47862 */ MCD_OPC_FilterValue, + 42, + 10, + 0, + 0, // Skip to: 47877 + /* 47867 */ MCD_OPC_CheckPredicate, + 21, + 79, + 221, + 0, // Skip to: 104527 + /* 47872 */ MCD_OPC_Decode, + 215, + 22, + 205, + 1, // Opcode: LD1Twov4s + /* 47877 */ MCD_OPC_FilterValue, + 43, + 69, + 221, + 0, // Skip to: 104527 + /* 47882 */ MCD_OPC_CheckPredicate, + 21, + 64, + 221, + 0, // Skip to: 104527 + /* 47887 */ MCD_OPC_Decode, + 209, + 22, + 205, + 1, // Opcode: LD1Twov2d + /* 47892 */ MCD_OPC_FilterValue, + 3, + 5, + 0, + 0, // Skip to: 47902 + /* 47897 */ MCD_OPC_Decode, + 235, + 24, + 195, + 1, // Opcode: LDNPDi + /* 47902 */ MCD_OPC_FilterValue, + 5, + 44, + 221, + 0, // Skip to: 104527 + /* 47907 */ MCD_OPC_Decode, + 236, + 24, + 195, + 1, // Opcode: LDNPQi + /* 47912 */ MCD_OPC_FilterValue, + 2, + 191, + 4, + 0, // Skip to: 49132 + /* 47917 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 47920 */ MCD_OPC_FilterValue, + 0, + 41, + 2, + 0, // Skip to: 48478 + /* 47925 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 47928 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 47950 + /* 47933 */ MCD_OPC_CheckPredicate, + 21, + 13, + 221, + 0, // Skip to: 104527 + /* 47938 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 6, + 221, + 0, // Skip to: 104527 + /* 47945 */ MCD_OPC_Decode, + 143, + 39, + 206, + 1, // Opcode: ST4Fourv8b_POST + /* 47950 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 47972 + /* 47955 */ MCD_OPC_CheckPredicate, + 21, + 247, + 220, + 0, // Skip to: 104527 + /* 47960 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 240, + 220, + 0, // Skip to: 104527 + /* 47967 */ MCD_OPC_Decode, + 139, + 39, + 206, + 1, // Opcode: ST4Fourv4h_POST + /* 47972 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 47994 + /* 47977 */ MCD_OPC_CheckPredicate, + 21, + 225, + 220, + 0, // Skip to: 104527 + /* 47982 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 218, + 220, + 0, // Skip to: 104527 + /* 47989 */ MCD_OPC_Decode, + 137, + 39, + 206, + 1, // Opcode: ST4Fourv2s_POST + /* 47994 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 48016 + /* 47999 */ MCD_OPC_CheckPredicate, + 21, + 203, + 220, + 0, // Skip to: 104527 + /* 48004 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 196, + 220, + 0, // Skip to: 104527 + /* 48011 */ MCD_OPC_Decode, + 242, + 37, + 206, + 1, // Opcode: ST1Fourv8b_POST + /* 48016 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 48038 + /* 48021 */ MCD_OPC_CheckPredicate, + 21, + 181, + 220, + 0, // Skip to: 104527 + /* 48026 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 174, + 220, + 0, // Skip to: 104527 + /* 48033 */ MCD_OPC_Decode, + 238, + 37, + 206, + 1, // Opcode: ST1Fourv4h_POST + /* 48038 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 48060 + /* 48043 */ MCD_OPC_CheckPredicate, + 21, + 159, + 220, + 0, // Skip to: 104527 + /* 48048 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 152, + 220, + 0, // Skip to: 104527 + /* 48055 */ MCD_OPC_Decode, + 236, + 37, + 206, + 1, // Opcode: ST1Fourv2s_POST + /* 48060 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 48082 + /* 48065 */ MCD_OPC_CheckPredicate, + 21, + 137, + 220, + 0, // Skip to: 104527 + /* 48070 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 130, + 220, + 0, // Skip to: 104527 + /* 48077 */ MCD_OPC_Decode, + 232, + 37, + 206, + 1, // Opcode: ST1Fourv1d_POST + /* 48082 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 48104 + /* 48087 */ MCD_OPC_CheckPredicate, + 21, + 115, + 220, + 0, // Skip to: 104527 + /* 48092 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 108, + 220, + 0, // Skip to: 104527 + /* 48099 */ MCD_OPC_Decode, + 243, + 38, + 207, + 1, // Opcode: ST3Threev8b_POST + /* 48104 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 48126 + /* 48109 */ MCD_OPC_CheckPredicate, + 21, + 93, + 220, + 0, // Skip to: 104527 + /* 48114 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 86, + 220, + 0, // Skip to: 104527 + /* 48121 */ MCD_OPC_Decode, + 239, + 38, + 207, + 1, // Opcode: ST3Threev4h_POST + /* 48126 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 48148 + /* 48131 */ MCD_OPC_CheckPredicate, + 21, + 71, + 220, + 0, // Skip to: 104527 + /* 48136 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 64, + 220, + 0, // Skip to: 104527 + /* 48143 */ MCD_OPC_Decode, + 237, + 38, + 207, + 1, // Opcode: ST3Threev2s_POST + /* 48148 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 48170 + /* 48153 */ MCD_OPC_CheckPredicate, + 21, + 49, + 220, + 0, // Skip to: 104527 + /* 48158 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 42, + 220, + 0, // Skip to: 104527 + /* 48165 */ MCD_OPC_Decode, + 152, + 38, + 207, + 1, // Opcode: ST1Threev8b_POST + /* 48170 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 48192 + /* 48175 */ MCD_OPC_CheckPredicate, + 21, + 27, + 220, + 0, // Skip to: 104527 + /* 48180 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 20, + 220, + 0, // Skip to: 104527 + /* 48187 */ MCD_OPC_Decode, + 148, + 38, + 207, + 1, // Opcode: ST1Threev4h_POST + /* 48192 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 48214 + /* 48197 */ MCD_OPC_CheckPredicate, + 21, + 5, + 220, + 0, // Skip to: 104527 + /* 48202 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 254, + 219, + 0, // Skip to: 104527 + /* 48209 */ MCD_OPC_Decode, + 146, + 38, + 207, + 1, // Opcode: ST1Threev2s_POST + /* 48214 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 48236 + /* 48219 */ MCD_OPC_CheckPredicate, + 21, + 239, + 219, + 0, // Skip to: 104527 + /* 48224 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 232, + 219, + 0, // Skip to: 104527 + /* 48231 */ MCD_OPC_Decode, + 142, + 38, + 207, + 1, // Opcode: ST1Threev1d_POST + /* 48236 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 48258 + /* 48241 */ MCD_OPC_CheckPredicate, + 21, + 217, + 219, + 0, // Skip to: 104527 + /* 48246 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 210, + 219, + 0, // Skip to: 104527 + /* 48253 */ MCD_OPC_Decode, + 136, + 38, + 208, + 1, // Opcode: ST1Onev8b_POST + /* 48258 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 48280 + /* 48263 */ MCD_OPC_CheckPredicate, + 21, + 195, + 219, + 0, // Skip to: 104527 + /* 48268 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 188, + 219, + 0, // Skip to: 104527 + /* 48275 */ MCD_OPC_Decode, + 132, + 38, + 208, + 1, // Opcode: ST1Onev4h_POST + /* 48280 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 48302 + /* 48285 */ MCD_OPC_CheckPredicate, + 21, + 173, + 219, + 0, // Skip to: 104527 + /* 48290 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 166, + 219, + 0, // Skip to: 104527 + /* 48297 */ MCD_OPC_Decode, + 130, + 38, + 208, + 1, // Opcode: ST1Onev2s_POST + /* 48302 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 48324 + /* 48307 */ MCD_OPC_CheckPredicate, + 21, + 151, + 219, + 0, // Skip to: 104527 + /* 48312 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 144, + 219, + 0, // Skip to: 104527 + /* 48319 */ MCD_OPC_Decode, + 254, + 37, + 208, + 1, // Opcode: ST1Onev1d_POST + /* 48324 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 48346 + /* 48329 */ MCD_OPC_CheckPredicate, + 21, + 129, + 219, + 0, // Skip to: 104527 + /* 48334 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 122, + 219, + 0, // Skip to: 104527 + /* 48341 */ MCD_OPC_Decode, + 213, + 38, + 209, + 1, // Opcode: ST2Twov8b_POST + /* 48346 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 48368 + /* 48351 */ MCD_OPC_CheckPredicate, + 21, + 107, + 219, + 0, // Skip to: 104527 + /* 48356 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 100, + 219, + 0, // Skip to: 104527 + /* 48363 */ MCD_OPC_Decode, + 209, + 38, + 209, + 1, // Opcode: ST2Twov4h_POST + /* 48368 */ MCD_OPC_FilterValue, + 34, + 17, + 0, + 0, // Skip to: 48390 + /* 48373 */ MCD_OPC_CheckPredicate, + 21, + 85, + 219, + 0, // Skip to: 104527 + /* 48378 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 78, + 219, + 0, // Skip to: 104527 + /* 48385 */ MCD_OPC_Decode, + 207, + 38, + 209, + 1, // Opcode: ST2Twov2s_POST + /* 48390 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 48412 + /* 48395 */ MCD_OPC_CheckPredicate, + 21, + 63, + 219, + 0, // Skip to: 104527 + /* 48400 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 56, + 219, + 0, // Skip to: 104527 + /* 48407 */ MCD_OPC_Decode, + 168, + 38, + 209, + 1, // Opcode: ST1Twov8b_POST + /* 48412 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 48434 + /* 48417 */ MCD_OPC_CheckPredicate, + 21, + 41, + 219, + 0, // Skip to: 104527 + /* 48422 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 34, + 219, + 0, // Skip to: 104527 + /* 48429 */ MCD_OPC_Decode, + 164, + 38, + 209, + 1, // Opcode: ST1Twov4h_POST + /* 48434 */ MCD_OPC_FilterValue, + 42, + 17, + 0, + 0, // Skip to: 48456 + /* 48439 */ MCD_OPC_CheckPredicate, + 21, + 19, + 219, + 0, // Skip to: 104527 + /* 48444 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 12, + 219, + 0, // Skip to: 104527 + /* 48451 */ MCD_OPC_Decode, + 162, + 38, + 209, + 1, // Opcode: ST1Twov2s_POST + /* 48456 */ MCD_OPC_FilterValue, + 43, + 2, + 219, + 0, // Skip to: 104527 + /* 48461 */ MCD_OPC_CheckPredicate, + 21, + 253, + 218, + 0, // Skip to: 104527 + /* 48466 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 246, + 218, + 0, // Skip to: 104527 + /* 48473 */ MCD_OPC_Decode, + 158, + 38, + 209, + 1, // Opcode: ST1Twov1d_POST + /* 48478 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 48488 + /* 48483 */ MCD_OPC_Decode, + 213, + 39, + 195, + 1, // Opcode: STPSpost + /* 48488 */ MCD_OPC_FilterValue, + 2, + 107, + 2, + 0, // Skip to: 49112 + /* 48493 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 48496 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 48518 + /* 48501 */ MCD_OPC_CheckPredicate, + 21, + 213, + 218, + 0, // Skip to: 104527 + /* 48506 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 206, + 218, + 0, // Skip to: 104527 + /* 48513 */ MCD_OPC_Decode, + 133, + 39, + 210, + 1, // Opcode: ST4Fourv16b_POST + /* 48518 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 48540 + /* 48523 */ MCD_OPC_CheckPredicate, + 21, + 191, + 218, + 0, // Skip to: 104527 + /* 48528 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 184, + 218, + 0, // Skip to: 104527 + /* 48535 */ MCD_OPC_Decode, + 145, + 39, + 210, + 1, // Opcode: ST4Fourv8h_POST + /* 48540 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 48562 + /* 48545 */ MCD_OPC_CheckPredicate, + 21, + 169, + 218, + 0, // Skip to: 104527 + /* 48550 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 162, + 218, + 0, // Skip to: 104527 + /* 48557 */ MCD_OPC_Decode, + 141, + 39, + 210, + 1, // Opcode: ST4Fourv4s_POST + /* 48562 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 48584 + /* 48567 */ MCD_OPC_CheckPredicate, + 21, + 147, + 218, + 0, // Skip to: 104527 + /* 48572 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 140, + 218, + 0, // Skip to: 104527 + /* 48579 */ MCD_OPC_Decode, + 135, + 39, + 210, + 1, // Opcode: ST4Fourv2d_POST + /* 48584 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 48606 + /* 48589 */ MCD_OPC_CheckPredicate, + 21, + 125, + 218, + 0, // Skip to: 104527 + /* 48594 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 118, + 218, + 0, // Skip to: 104527 + /* 48601 */ MCD_OPC_Decode, + 230, + 37, + 210, + 1, // Opcode: ST1Fourv16b_POST + /* 48606 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 48628 + /* 48611 */ MCD_OPC_CheckPredicate, + 21, + 103, + 218, + 0, // Skip to: 104527 + /* 48616 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 96, + 218, + 0, // Skip to: 104527 + /* 48623 */ MCD_OPC_Decode, + 244, + 37, + 210, + 1, // Opcode: ST1Fourv8h_POST + /* 48628 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 48650 + /* 48633 */ MCD_OPC_CheckPredicate, + 21, + 81, + 218, + 0, // Skip to: 104527 + /* 48638 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 74, + 218, + 0, // Skip to: 104527 + /* 48645 */ MCD_OPC_Decode, + 240, + 37, + 210, + 1, // Opcode: ST1Fourv4s_POST + /* 48650 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 48672 + /* 48655 */ MCD_OPC_CheckPredicate, + 21, + 59, + 218, + 0, // Skip to: 104527 + /* 48660 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 52, + 218, + 0, // Skip to: 104527 + /* 48667 */ MCD_OPC_Decode, + 234, + 37, + 210, + 1, // Opcode: ST1Fourv2d_POST + /* 48672 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 48694 + /* 48677 */ MCD_OPC_CheckPredicate, + 21, + 37, + 218, + 0, // Skip to: 104527 + /* 48682 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 30, + 218, + 0, // Skip to: 104527 + /* 48689 */ MCD_OPC_Decode, + 233, + 38, + 211, + 1, // Opcode: ST3Threev16b_POST + /* 48694 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 48716 + /* 48699 */ MCD_OPC_CheckPredicate, + 21, + 15, + 218, + 0, // Skip to: 104527 + /* 48704 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 8, + 218, + 0, // Skip to: 104527 + /* 48711 */ MCD_OPC_Decode, + 245, + 38, + 211, + 1, // Opcode: ST3Threev8h_POST + /* 48716 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 48738 + /* 48721 */ MCD_OPC_CheckPredicate, + 21, + 249, + 217, + 0, // Skip to: 104527 + /* 48726 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 242, + 217, + 0, // Skip to: 104527 + /* 48733 */ MCD_OPC_Decode, + 241, + 38, + 211, + 1, // Opcode: ST3Threev4s_POST + /* 48738 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 48760 + /* 48743 */ MCD_OPC_CheckPredicate, + 21, + 227, + 217, + 0, // Skip to: 104527 + /* 48748 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 220, + 217, + 0, // Skip to: 104527 + /* 48755 */ MCD_OPC_Decode, + 235, + 38, + 211, + 1, // Opcode: ST3Threev2d_POST + /* 48760 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 48782 + /* 48765 */ MCD_OPC_CheckPredicate, + 21, + 205, + 217, + 0, // Skip to: 104527 + /* 48770 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 198, + 217, + 0, // Skip to: 104527 + /* 48777 */ MCD_OPC_Decode, + 140, + 38, + 211, + 1, // Opcode: ST1Threev16b_POST + /* 48782 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 48804 + /* 48787 */ MCD_OPC_CheckPredicate, + 21, + 183, + 217, + 0, // Skip to: 104527 + /* 48792 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 176, + 217, + 0, // Skip to: 104527 + /* 48799 */ MCD_OPC_Decode, + 154, + 38, + 211, + 1, // Opcode: ST1Threev8h_POST + /* 48804 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 48826 + /* 48809 */ MCD_OPC_CheckPredicate, + 21, + 161, + 217, + 0, // Skip to: 104527 + /* 48814 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 154, + 217, + 0, // Skip to: 104527 + /* 48821 */ MCD_OPC_Decode, + 150, + 38, + 211, + 1, // Opcode: ST1Threev4s_POST + /* 48826 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 48848 + /* 48831 */ MCD_OPC_CheckPredicate, + 21, + 139, + 217, + 0, // Skip to: 104527 + /* 48836 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 132, + 217, + 0, // Skip to: 104527 + /* 48843 */ MCD_OPC_Decode, + 144, + 38, + 211, + 1, // Opcode: ST1Threev2d_POST + /* 48848 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 48870 + /* 48853 */ MCD_OPC_CheckPredicate, + 21, + 117, + 217, + 0, // Skip to: 104527 + /* 48858 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 110, + 217, + 0, // Skip to: 104527 + /* 48865 */ MCD_OPC_Decode, + 252, + 37, + 212, + 1, // Opcode: ST1Onev16b_POST + /* 48870 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 48892 + /* 48875 */ MCD_OPC_CheckPredicate, + 21, + 95, + 217, + 0, // Skip to: 104527 + /* 48880 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 88, + 217, + 0, // Skip to: 104527 + /* 48887 */ MCD_OPC_Decode, + 138, + 38, + 212, + 1, // Opcode: ST1Onev8h_POST + /* 48892 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 48914 + /* 48897 */ MCD_OPC_CheckPredicate, + 21, + 73, + 217, + 0, // Skip to: 104527 + /* 48902 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 66, + 217, + 0, // Skip to: 104527 + /* 48909 */ MCD_OPC_Decode, + 134, + 38, + 212, + 1, // Opcode: ST1Onev4s_POST + /* 48914 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 48936 + /* 48919 */ MCD_OPC_CheckPredicate, + 21, + 51, + 217, + 0, // Skip to: 104527 + /* 48924 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 44, + 217, + 0, // Skip to: 104527 + /* 48931 */ MCD_OPC_Decode, + 128, + 38, + 212, + 1, // Opcode: ST1Onev2d_POST + /* 48936 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 48958 + /* 48941 */ MCD_OPC_CheckPredicate, + 21, + 29, + 217, + 0, // Skip to: 104527 + /* 48946 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 22, + 217, + 0, // Skip to: 104527 + /* 48953 */ MCD_OPC_Decode, + 203, + 38, + 213, + 1, // Opcode: ST2Twov16b_POST + /* 48958 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 48980 + /* 48963 */ MCD_OPC_CheckPredicate, + 21, + 7, + 217, + 0, // Skip to: 104527 + /* 48968 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 0, + 217, + 0, // Skip to: 104527 + /* 48975 */ MCD_OPC_Decode, + 215, + 38, + 213, + 1, // Opcode: ST2Twov8h_POST + /* 48980 */ MCD_OPC_FilterValue, + 34, + 17, + 0, + 0, // Skip to: 49002 + /* 48985 */ MCD_OPC_CheckPredicate, + 21, + 241, + 216, + 0, // Skip to: 104527 + /* 48990 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 234, + 216, + 0, // Skip to: 104527 + /* 48997 */ MCD_OPC_Decode, + 211, + 38, + 213, + 1, // Opcode: ST2Twov4s_POST + /* 49002 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 49024 + /* 49007 */ MCD_OPC_CheckPredicate, + 21, + 219, + 216, + 0, // Skip to: 104527 + /* 49012 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 212, + 216, + 0, // Skip to: 104527 + /* 49019 */ MCD_OPC_Decode, + 205, + 38, + 213, + 1, // Opcode: ST2Twov2d_POST + /* 49024 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 49046 + /* 49029 */ MCD_OPC_CheckPredicate, + 21, + 197, + 216, + 0, // Skip to: 104527 + /* 49034 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 190, + 216, + 0, // Skip to: 104527 + /* 49041 */ MCD_OPC_Decode, + 156, + 38, + 213, + 1, // Opcode: ST1Twov16b_POST + /* 49046 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 49068 + /* 49051 */ MCD_OPC_CheckPredicate, + 21, + 175, + 216, + 0, // Skip to: 104527 + /* 49056 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 168, + 216, + 0, // Skip to: 104527 + /* 49063 */ MCD_OPC_Decode, + 170, + 38, + 213, + 1, // Opcode: ST1Twov8h_POST + /* 49068 */ MCD_OPC_FilterValue, + 42, + 17, + 0, + 0, // Skip to: 49090 + /* 49073 */ MCD_OPC_CheckPredicate, + 21, + 153, + 216, + 0, // Skip to: 104527 + /* 49078 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 146, + 216, + 0, // Skip to: 104527 + /* 49085 */ MCD_OPC_Decode, + 166, + 38, + 213, + 1, // Opcode: ST1Twov4s_POST + /* 49090 */ MCD_OPC_FilterValue, + 43, + 136, + 216, + 0, // Skip to: 104527 + /* 49095 */ MCD_OPC_CheckPredicate, + 21, + 131, + 216, + 0, // Skip to: 104527 + /* 49100 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 124, + 216, + 0, // Skip to: 104527 + /* 49107 */ MCD_OPC_Decode, + 160, + 38, + 213, + 1, // Opcode: ST1Twov2d_POST + /* 49112 */ MCD_OPC_FilterValue, + 3, + 5, + 0, + 0, // Skip to: 49122 + /* 49117 */ MCD_OPC_Decode, + 207, + 39, + 195, + 1, // Opcode: STPDpost + /* 49122 */ MCD_OPC_FilterValue, + 5, + 104, + 216, + 0, // Skip to: 104527 + /* 49127 */ MCD_OPC_Decode, + 210, + 39, + 195, + 1, // Opcode: STPQpost + /* 49132 */ MCD_OPC_FilterValue, + 3, + 191, + 4, + 0, // Skip to: 50352 + /* 49137 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 49140 */ MCD_OPC_FilterValue, + 0, + 41, + 2, + 0, // Skip to: 49698 + /* 49145 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 49148 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 49170 + /* 49153 */ MCD_OPC_CheckPredicate, + 21, + 73, + 216, + 0, // Skip to: 104527 + /* 49158 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 66, + 216, + 0, // Skip to: 104527 + /* 49165 */ MCD_OPC_Decode, + 222, + 23, + 206, + 1, // Opcode: LD4Fourv8b_POST + /* 49170 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 49192 + /* 49175 */ MCD_OPC_CheckPredicate, + 21, + 51, + 216, + 0, // Skip to: 104527 + /* 49180 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 44, + 216, + 0, // Skip to: 104527 + /* 49187 */ MCD_OPC_Decode, + 218, + 23, + 206, + 1, // Opcode: LD4Fourv4h_POST + /* 49192 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 49214 + /* 49197 */ MCD_OPC_CheckPredicate, + 21, + 29, + 216, + 0, // Skip to: 104527 + /* 49202 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 22, + 216, + 0, // Skip to: 104527 + /* 49209 */ MCD_OPC_Decode, + 216, + 23, + 206, + 1, // Opcode: LD4Fourv2s_POST + /* 49214 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 49236 + /* 49219 */ MCD_OPC_CheckPredicate, + 21, + 7, + 216, + 0, // Skip to: 104527 + /* 49224 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 0, + 216, + 0, // Skip to: 104527 + /* 49231 */ MCD_OPC_Decode, + 232, + 21, + 206, + 1, // Opcode: LD1Fourv8b_POST + /* 49236 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 49258 + /* 49241 */ MCD_OPC_CheckPredicate, + 21, + 241, + 215, + 0, // Skip to: 104527 + /* 49246 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 234, + 215, + 0, // Skip to: 104527 + /* 49253 */ MCD_OPC_Decode, + 228, + 21, + 206, + 1, // Opcode: LD1Fourv4h_POST + /* 49258 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 49280 + /* 49263 */ MCD_OPC_CheckPredicate, + 21, + 219, + 215, + 0, // Skip to: 104527 + /* 49268 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 212, + 215, + 0, // Skip to: 104527 + /* 49275 */ MCD_OPC_Decode, + 226, + 21, + 206, + 1, // Opcode: LD1Fourv2s_POST + /* 49280 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 49302 + /* 49285 */ MCD_OPC_CheckPredicate, + 21, + 197, + 215, + 0, // Skip to: 104527 + /* 49290 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 190, + 215, + 0, // Skip to: 104527 + /* 49297 */ MCD_OPC_Decode, + 222, + 21, + 206, + 1, // Opcode: LD1Fourv1d_POST + /* 49302 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 49324 + /* 49307 */ MCD_OPC_CheckPredicate, + 21, + 175, + 215, + 0, // Skip to: 104527 + /* 49312 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 168, + 215, + 0, // Skip to: 104527 + /* 49319 */ MCD_OPC_Decode, + 194, + 23, + 207, + 1, // Opcode: LD3Threev8b_POST + /* 49324 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 49346 + /* 49329 */ MCD_OPC_CheckPredicate, + 21, + 153, + 215, + 0, // Skip to: 104527 + /* 49334 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 146, + 215, + 0, // Skip to: 104527 + /* 49341 */ MCD_OPC_Decode, + 190, + 23, + 207, + 1, // Opcode: LD3Threev4h_POST + /* 49346 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 49368 + /* 49351 */ MCD_OPC_CheckPredicate, + 21, + 131, + 215, + 0, // Skip to: 104527 + /* 49356 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 124, + 215, + 0, // Skip to: 104527 + /* 49363 */ MCD_OPC_Decode, + 188, + 23, + 207, + 1, // Opcode: LD3Threev2s_POST + /* 49368 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 49390 + /* 49373 */ MCD_OPC_CheckPredicate, + 21, + 109, + 215, + 0, // Skip to: 104527 + /* 49378 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 102, + 215, + 0, // Skip to: 104527 + /* 49385 */ MCD_OPC_Decode, + 202, + 22, + 207, + 1, // Opcode: LD1Threev8b_POST + /* 49390 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 49412 + /* 49395 */ MCD_OPC_CheckPredicate, + 21, + 87, + 215, + 0, // Skip to: 104527 + /* 49400 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 80, + 215, + 0, // Skip to: 104527 + /* 49407 */ MCD_OPC_Decode, + 198, + 22, + 207, + 1, // Opcode: LD1Threev4h_POST + /* 49412 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 49434 + /* 49417 */ MCD_OPC_CheckPredicate, + 21, + 65, + 215, + 0, // Skip to: 104527 + /* 49422 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 58, + 215, + 0, // Skip to: 104527 + /* 49429 */ MCD_OPC_Decode, + 196, + 22, + 207, + 1, // Opcode: LD1Threev2s_POST + /* 49434 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 49456 + /* 49439 */ MCD_OPC_CheckPredicate, + 21, + 43, + 215, + 0, // Skip to: 104527 + /* 49444 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 36, + 215, + 0, // Skip to: 104527 + /* 49451 */ MCD_OPC_Decode, + 192, + 22, + 207, + 1, // Opcode: LD1Threev1d_POST + /* 49456 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 49478 + /* 49461 */ MCD_OPC_CheckPredicate, + 21, + 21, + 215, + 0, // Skip to: 104527 + /* 49466 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 14, + 215, + 0, // Skip to: 104527 + /* 49473 */ MCD_OPC_Decode, + 254, + 21, + 208, + 1, // Opcode: LD1Onev8b_POST + /* 49478 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 49500 + /* 49483 */ MCD_OPC_CheckPredicate, + 21, + 255, + 214, + 0, // Skip to: 104527 + /* 49488 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 248, + 214, + 0, // Skip to: 104527 + /* 49495 */ MCD_OPC_Decode, + 250, + 21, + 208, + 1, // Opcode: LD1Onev4h_POST + /* 49500 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 49522 + /* 49505 */ MCD_OPC_CheckPredicate, + 21, + 233, + 214, + 0, // Skip to: 104527 + /* 49510 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 226, + 214, + 0, // Skip to: 104527 + /* 49517 */ MCD_OPC_Decode, + 248, + 21, + 208, + 1, // Opcode: LD1Onev2s_POST + /* 49522 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 49544 + /* 49527 */ MCD_OPC_CheckPredicate, + 21, + 211, + 214, + 0, // Skip to: 104527 + /* 49532 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 204, + 214, + 0, // Skip to: 104527 + /* 49539 */ MCD_OPC_Decode, + 244, + 21, + 208, + 1, // Opcode: LD1Onev1d_POST + /* 49544 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 49566 + /* 49549 */ MCD_OPC_CheckPredicate, + 21, + 189, + 214, + 0, // Skip to: 104527 + /* 49554 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 182, + 214, + 0, // Skip to: 104527 + /* 49561 */ MCD_OPC_Decode, + 148, + 23, + 209, + 1, // Opcode: LD2Twov8b_POST + /* 49566 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 49588 + /* 49571 */ MCD_OPC_CheckPredicate, + 21, + 167, + 214, + 0, // Skip to: 104527 + /* 49576 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 160, + 214, + 0, // Skip to: 104527 + /* 49583 */ MCD_OPC_Decode, + 144, + 23, + 209, + 1, // Opcode: LD2Twov4h_POST + /* 49588 */ MCD_OPC_FilterValue, + 34, + 17, + 0, + 0, // Skip to: 49610 + /* 49593 */ MCD_OPC_CheckPredicate, + 21, + 145, + 214, + 0, // Skip to: 104527 + /* 49598 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 138, + 214, + 0, // Skip to: 104527 + /* 49605 */ MCD_OPC_Decode, + 142, + 23, + 209, + 1, // Opcode: LD2Twov2s_POST + /* 49610 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 49632 + /* 49615 */ MCD_OPC_CheckPredicate, + 21, + 123, + 214, + 0, // Skip to: 104527 + /* 49620 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 116, + 214, + 0, // Skip to: 104527 + /* 49627 */ MCD_OPC_Decode, + 218, + 22, + 209, + 1, // Opcode: LD1Twov8b_POST + /* 49632 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 49654 + /* 49637 */ MCD_OPC_CheckPredicate, + 21, + 101, + 214, + 0, // Skip to: 104527 + /* 49642 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 94, + 214, + 0, // Skip to: 104527 + /* 49649 */ MCD_OPC_Decode, + 214, + 22, + 209, + 1, // Opcode: LD1Twov4h_POST + /* 49654 */ MCD_OPC_FilterValue, + 42, + 17, + 0, + 0, // Skip to: 49676 + /* 49659 */ MCD_OPC_CheckPredicate, + 21, + 79, + 214, + 0, // Skip to: 104527 + /* 49664 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 72, + 214, + 0, // Skip to: 104527 + /* 49671 */ MCD_OPC_Decode, + 212, + 22, + 209, + 1, // Opcode: LD1Twov2s_POST + /* 49676 */ MCD_OPC_FilterValue, + 43, + 62, + 214, + 0, // Skip to: 104527 + /* 49681 */ MCD_OPC_CheckPredicate, + 21, + 57, + 214, + 0, // Skip to: 104527 + /* 49686 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 50, + 214, + 0, // Skip to: 104527 + /* 49693 */ MCD_OPC_Decode, + 208, + 22, + 209, + 1, // Opcode: LD1Twov1d_POST + /* 49698 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 49708 + /* 49703 */ MCD_OPC_Decode, + 142, + 25, + 195, + 1, // Opcode: LDPSpost + /* 49708 */ MCD_OPC_FilterValue, + 2, + 107, + 2, + 0, // Skip to: 50332 + /* 49713 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 49716 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 49738 + /* 49721 */ MCD_OPC_CheckPredicate, + 21, + 17, + 214, + 0, // Skip to: 104527 + /* 49726 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 10, + 214, + 0, // Skip to: 104527 + /* 49733 */ MCD_OPC_Decode, + 212, + 23, + 210, + 1, // Opcode: LD4Fourv16b_POST + /* 49738 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 49760 + /* 49743 */ MCD_OPC_CheckPredicate, + 21, + 251, + 213, + 0, // Skip to: 104527 + /* 49748 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 244, + 213, + 0, // Skip to: 104527 + /* 49755 */ MCD_OPC_Decode, + 224, + 23, + 210, + 1, // Opcode: LD4Fourv8h_POST + /* 49760 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 49782 + /* 49765 */ MCD_OPC_CheckPredicate, + 21, + 229, + 213, + 0, // Skip to: 104527 + /* 49770 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 222, + 213, + 0, // Skip to: 104527 + /* 49777 */ MCD_OPC_Decode, + 220, + 23, + 210, + 1, // Opcode: LD4Fourv4s_POST + /* 49782 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 49804 + /* 49787 */ MCD_OPC_CheckPredicate, + 21, + 207, + 213, + 0, // Skip to: 104527 + /* 49792 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 200, + 213, + 0, // Skip to: 104527 + /* 49799 */ MCD_OPC_Decode, + 214, + 23, + 210, + 1, // Opcode: LD4Fourv2d_POST + /* 49804 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 49826 + /* 49809 */ MCD_OPC_CheckPredicate, + 21, + 185, + 213, + 0, // Skip to: 104527 + /* 49814 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 178, + 213, + 0, // Skip to: 104527 + /* 49821 */ MCD_OPC_Decode, + 220, + 21, + 210, + 1, // Opcode: LD1Fourv16b_POST + /* 49826 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 49848 + /* 49831 */ MCD_OPC_CheckPredicate, + 21, + 163, + 213, + 0, // Skip to: 104527 + /* 49836 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 156, + 213, + 0, // Skip to: 104527 + /* 49843 */ MCD_OPC_Decode, + 234, + 21, + 210, + 1, // Opcode: LD1Fourv8h_POST + /* 49848 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 49870 + /* 49853 */ MCD_OPC_CheckPredicate, + 21, + 141, + 213, + 0, // Skip to: 104527 + /* 49858 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 134, + 213, + 0, // Skip to: 104527 + /* 49865 */ MCD_OPC_Decode, + 230, + 21, + 210, + 1, // Opcode: LD1Fourv4s_POST + /* 49870 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 49892 + /* 49875 */ MCD_OPC_CheckPredicate, + 21, + 119, + 213, + 0, // Skip to: 104527 + /* 49880 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 112, + 213, + 0, // Skip to: 104527 + /* 49887 */ MCD_OPC_Decode, + 224, + 21, + 210, + 1, // Opcode: LD1Fourv2d_POST + /* 49892 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 49914 + /* 49897 */ MCD_OPC_CheckPredicate, + 21, + 97, + 213, + 0, // Skip to: 104527 + /* 49902 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 90, + 213, + 0, // Skip to: 104527 + /* 49909 */ MCD_OPC_Decode, + 184, + 23, + 211, + 1, // Opcode: LD3Threev16b_POST + /* 49914 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 49936 + /* 49919 */ MCD_OPC_CheckPredicate, + 21, + 75, + 213, + 0, // Skip to: 104527 + /* 49924 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 68, + 213, + 0, // Skip to: 104527 + /* 49931 */ MCD_OPC_Decode, + 196, + 23, + 211, + 1, // Opcode: LD3Threev8h_POST + /* 49936 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 49958 + /* 49941 */ MCD_OPC_CheckPredicate, + 21, + 53, + 213, + 0, // Skip to: 104527 + /* 49946 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 46, + 213, + 0, // Skip to: 104527 + /* 49953 */ MCD_OPC_Decode, + 192, + 23, + 211, + 1, // Opcode: LD3Threev4s_POST + /* 49958 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 49980 + /* 49963 */ MCD_OPC_CheckPredicate, + 21, + 31, + 213, + 0, // Skip to: 104527 + /* 49968 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 24, + 213, + 0, // Skip to: 104527 + /* 49975 */ MCD_OPC_Decode, + 186, + 23, + 211, + 1, // Opcode: LD3Threev2d_POST + /* 49980 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 50002 + /* 49985 */ MCD_OPC_CheckPredicate, + 21, + 9, + 213, + 0, // Skip to: 104527 + /* 49990 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 2, + 213, + 0, // Skip to: 104527 + /* 49997 */ MCD_OPC_Decode, + 190, + 22, + 211, + 1, // Opcode: LD1Threev16b_POST + /* 50002 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 50024 + /* 50007 */ MCD_OPC_CheckPredicate, + 21, + 243, + 212, + 0, // Skip to: 104527 + /* 50012 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 236, + 212, + 0, // Skip to: 104527 + /* 50019 */ MCD_OPC_Decode, + 204, + 22, + 211, + 1, // Opcode: LD1Threev8h_POST + /* 50024 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 50046 + /* 50029 */ MCD_OPC_CheckPredicate, + 21, + 221, + 212, + 0, // Skip to: 104527 + /* 50034 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 214, + 212, + 0, // Skip to: 104527 + /* 50041 */ MCD_OPC_Decode, + 200, + 22, + 211, + 1, // Opcode: LD1Threev4s_POST + /* 50046 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 50068 + /* 50051 */ MCD_OPC_CheckPredicate, + 21, + 199, + 212, + 0, // Skip to: 104527 + /* 50056 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 192, + 212, + 0, // Skip to: 104527 + /* 50063 */ MCD_OPC_Decode, + 194, + 22, + 211, + 1, // Opcode: LD1Threev2d_POST + /* 50068 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 50090 + /* 50073 */ MCD_OPC_CheckPredicate, + 21, + 177, + 212, + 0, // Skip to: 104527 + /* 50078 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 170, + 212, + 0, // Skip to: 104527 + /* 50085 */ MCD_OPC_Decode, + 242, + 21, + 212, + 1, // Opcode: LD1Onev16b_POST + /* 50090 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 50112 + /* 50095 */ MCD_OPC_CheckPredicate, + 21, + 155, + 212, + 0, // Skip to: 104527 + /* 50100 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 148, + 212, + 0, // Skip to: 104527 + /* 50107 */ MCD_OPC_Decode, + 128, + 22, + 212, + 1, // Opcode: LD1Onev8h_POST + /* 50112 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 50134 + /* 50117 */ MCD_OPC_CheckPredicate, + 21, + 133, + 212, + 0, // Skip to: 104527 + /* 50122 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 126, + 212, + 0, // Skip to: 104527 + /* 50129 */ MCD_OPC_Decode, + 252, + 21, + 212, + 1, // Opcode: LD1Onev4s_POST + /* 50134 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 50156 + /* 50139 */ MCD_OPC_CheckPredicate, + 21, + 111, + 212, + 0, // Skip to: 104527 + /* 50144 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 104, + 212, + 0, // Skip to: 104527 + /* 50151 */ MCD_OPC_Decode, + 246, + 21, + 212, + 1, // Opcode: LD1Onev2d_POST + /* 50156 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 50178 + /* 50161 */ MCD_OPC_CheckPredicate, + 21, + 89, + 212, + 0, // Skip to: 104527 + /* 50166 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 82, + 212, + 0, // Skip to: 104527 + /* 50173 */ MCD_OPC_Decode, + 138, + 23, + 213, + 1, // Opcode: LD2Twov16b_POST + /* 50178 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 50200 + /* 50183 */ MCD_OPC_CheckPredicate, + 21, + 67, + 212, + 0, // Skip to: 104527 + /* 50188 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 60, + 212, + 0, // Skip to: 104527 + /* 50195 */ MCD_OPC_Decode, + 150, + 23, + 213, + 1, // Opcode: LD2Twov8h_POST + /* 50200 */ MCD_OPC_FilterValue, + 34, + 17, + 0, + 0, // Skip to: 50222 + /* 50205 */ MCD_OPC_CheckPredicate, + 21, + 45, + 212, + 0, // Skip to: 104527 + /* 50210 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 38, + 212, + 0, // Skip to: 104527 + /* 50217 */ MCD_OPC_Decode, + 146, + 23, + 213, + 1, // Opcode: LD2Twov4s_POST + /* 50222 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 50244 + /* 50227 */ MCD_OPC_CheckPredicate, + 21, + 23, + 212, + 0, // Skip to: 104527 + /* 50232 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 16, + 212, + 0, // Skip to: 104527 + /* 50239 */ MCD_OPC_Decode, + 140, + 23, + 213, + 1, // Opcode: LD2Twov2d_POST + /* 50244 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 50266 + /* 50249 */ MCD_OPC_CheckPredicate, + 21, + 1, + 212, + 0, // Skip to: 104527 + /* 50254 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 250, + 211, + 0, // Skip to: 104527 + /* 50261 */ MCD_OPC_Decode, + 206, + 22, + 213, + 1, // Opcode: LD1Twov16b_POST + /* 50266 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 50288 + /* 50271 */ MCD_OPC_CheckPredicate, + 21, + 235, + 211, + 0, // Skip to: 104527 + /* 50276 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 228, + 211, + 0, // Skip to: 104527 + /* 50283 */ MCD_OPC_Decode, + 220, + 22, + 213, + 1, // Opcode: LD1Twov8h_POST + /* 50288 */ MCD_OPC_FilterValue, + 42, + 17, + 0, + 0, // Skip to: 50310 + /* 50293 */ MCD_OPC_CheckPredicate, + 21, + 213, + 211, + 0, // Skip to: 104527 + /* 50298 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 206, + 211, + 0, // Skip to: 104527 + /* 50305 */ MCD_OPC_Decode, + 216, + 22, + 213, + 1, // Opcode: LD1Twov4s_POST + /* 50310 */ MCD_OPC_FilterValue, + 43, + 196, + 211, + 0, // Skip to: 104527 + /* 50315 */ MCD_OPC_CheckPredicate, + 21, + 191, + 211, + 0, // Skip to: 104527 + /* 50320 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 184, + 211, + 0, // Skip to: 104527 + /* 50327 */ MCD_OPC_Decode, + 210, + 22, + 213, + 1, // Opcode: LD1Twov2d_POST + /* 50332 */ MCD_OPC_FilterValue, + 3, + 5, + 0, + 0, // Skip to: 50342 + /* 50337 */ MCD_OPC_Decode, + 133, + 25, + 195, + 1, // Opcode: LDPDpost + /* 50342 */ MCD_OPC_FilterValue, + 5, + 164, + 211, + 0, // Skip to: 104527 + /* 50347 */ MCD_OPC_Decode, + 136, + 25, + 195, + 1, // Opcode: LDPQpost + /* 50352 */ MCD_OPC_FilterValue, + 4, + 239, + 1, + 0, // Skip to: 50852 + /* 50357 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 50360 */ MCD_OPC_FilterValue, + 0, + 193, + 1, + 0, // Skip to: 50814 + /* 50365 */ MCD_OPC_ExtractField, + 13, + 9, // Inst{21-13} ... + /* 50368 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 50390 + /* 50373 */ MCD_OPC_CheckPredicate, + 21, + 133, + 211, + 0, // Skip to: 104527 + /* 50378 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 126, + 211, + 0, // Skip to: 104527 + /* 50385 */ MCD_OPC_Decode, + 191, + 38, + 214, + 1, // Opcode: ST1i8 + /* 50390 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 50412 + /* 50395 */ MCD_OPC_CheckPredicate, + 21, + 111, + 211, + 0, // Skip to: 104527 + /* 50400 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 104, + 211, + 0, // Skip to: 104527 + /* 50407 */ MCD_OPC_Decode, + 254, + 38, + 215, + 1, // Opcode: ST3i8 + /* 50412 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 50441 + /* 50417 */ MCD_OPC_CheckPredicate, + 21, + 89, + 211, + 0, // Skip to: 104527 + /* 50422 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 82, + 211, + 0, // Skip to: 104527 + /* 50429 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 75, + 211, + 0, // Skip to: 104527 + /* 50436 */ MCD_OPC_Decode, + 185, + 38, + 216, + 1, // Opcode: ST1i16 + /* 50441 */ MCD_OPC_FilterValue, + 3, + 24, + 0, + 0, // Skip to: 50470 + /* 50446 */ MCD_OPC_CheckPredicate, + 21, + 60, + 211, + 0, // Skip to: 104527 + /* 50451 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 53, + 211, + 0, // Skip to: 104527 + /* 50458 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 46, + 211, + 0, // Skip to: 104527 + /* 50465 */ MCD_OPC_Decode, + 248, + 38, + 217, + 1, // Opcode: ST3i16 + /* 50470 */ MCD_OPC_FilterValue, + 4, + 54, + 0, + 0, // Skip to: 50529 + /* 50475 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 50478 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 50500 + /* 50483 */ MCD_OPC_CheckPredicate, + 21, + 23, + 211, + 0, // Skip to: 104527 + /* 50488 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 16, + 211, + 0, // Skip to: 104527 + /* 50495 */ MCD_OPC_Decode, + 187, + 38, + 218, + 1, // Opcode: ST1i32 + /* 50500 */ MCD_OPC_FilterValue, + 1, + 6, + 211, + 0, // Skip to: 104527 + /* 50505 */ MCD_OPC_CheckPredicate, + 21, + 1, + 211, + 0, // Skip to: 104527 + /* 50510 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 250, + 210, + 0, // Skip to: 104527 + /* 50517 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 243, + 210, + 0, // Skip to: 104527 + /* 50524 */ MCD_OPC_Decode, + 189, + 38, + 219, + 1, // Opcode: ST1i64 + /* 50529 */ MCD_OPC_FilterValue, + 5, + 54, + 0, + 0, // Skip to: 50588 + /* 50534 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 50537 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 50559 + /* 50542 */ MCD_OPC_CheckPredicate, + 21, + 220, + 210, + 0, // Skip to: 104527 + /* 50547 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 213, + 210, + 0, // Skip to: 104527 + /* 50554 */ MCD_OPC_Decode, + 250, + 38, + 220, + 1, // Opcode: ST3i32 + /* 50559 */ MCD_OPC_FilterValue, + 1, + 203, + 210, + 0, // Skip to: 104527 + /* 50564 */ MCD_OPC_CheckPredicate, + 21, + 198, + 210, + 0, // Skip to: 104527 + /* 50569 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 191, + 210, + 0, // Skip to: 104527 + /* 50576 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 184, + 210, + 0, // Skip to: 104527 + /* 50583 */ MCD_OPC_Decode, + 252, + 38, + 221, + 1, // Opcode: ST3i64 + /* 50588 */ MCD_OPC_FilterValue, + 128, + 2, + 17, + 0, + 0, // Skip to: 50611 + /* 50594 */ MCD_OPC_CheckPredicate, + 21, + 168, + 210, + 0, // Skip to: 104527 + /* 50599 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 161, + 210, + 0, // Skip to: 104527 + /* 50606 */ MCD_OPC_Decode, + 224, + 38, + 222, + 1, // Opcode: ST2i8 + /* 50611 */ MCD_OPC_FilterValue, + 129, + 2, + 17, + 0, + 0, // Skip to: 50634 + /* 50617 */ MCD_OPC_CheckPredicate, + 21, + 145, + 210, + 0, // Skip to: 104527 + /* 50622 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 138, + 210, + 0, // Skip to: 104527 + /* 50629 */ MCD_OPC_Decode, + 156, + 39, + 223, + 1, // Opcode: ST4i8 + /* 50634 */ MCD_OPC_FilterValue, + 130, + 2, + 24, + 0, + 0, // Skip to: 50664 + /* 50640 */ MCD_OPC_CheckPredicate, + 21, + 122, + 210, + 0, // Skip to: 104527 + /* 50645 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 115, + 210, + 0, // Skip to: 104527 + /* 50652 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 108, + 210, + 0, // Skip to: 104527 + /* 50659 */ MCD_OPC_Decode, + 218, + 38, + 224, + 1, // Opcode: ST2i16 + /* 50664 */ MCD_OPC_FilterValue, + 131, + 2, + 24, + 0, + 0, // Skip to: 50694 + /* 50670 */ MCD_OPC_CheckPredicate, + 21, + 92, + 210, + 0, // Skip to: 104527 + /* 50675 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 85, + 210, + 0, // Skip to: 104527 + /* 50682 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 78, + 210, + 0, // Skip to: 104527 + /* 50689 */ MCD_OPC_Decode, + 150, + 39, + 225, + 1, // Opcode: ST4i16 + /* 50694 */ MCD_OPC_FilterValue, + 132, + 2, + 54, + 0, + 0, // Skip to: 50754 + /* 50700 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 50703 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 50725 + /* 50708 */ MCD_OPC_CheckPredicate, + 21, + 54, + 210, + 0, // Skip to: 104527 + /* 50713 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 47, + 210, + 0, // Skip to: 104527 + /* 50720 */ MCD_OPC_Decode, + 220, + 38, + 226, + 1, // Opcode: ST2i32 + /* 50725 */ MCD_OPC_FilterValue, + 1, + 37, + 210, + 0, // Skip to: 104527 + /* 50730 */ MCD_OPC_CheckPredicate, + 21, + 32, + 210, + 0, // Skip to: 104527 + /* 50735 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 25, + 210, + 0, // Skip to: 104527 + /* 50742 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 18, + 210, + 0, // Skip to: 104527 + /* 50749 */ MCD_OPC_Decode, + 222, + 38, + 227, + 1, // Opcode: ST2i64 + /* 50754 */ MCD_OPC_FilterValue, + 133, + 2, + 7, + 210, + 0, // Skip to: 104527 + /* 50760 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 50763 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 50785 + /* 50768 */ MCD_OPC_CheckPredicate, + 21, + 250, + 209, + 0, // Skip to: 104527 + /* 50773 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 243, + 209, + 0, // Skip to: 104527 + /* 50780 */ MCD_OPC_Decode, + 152, + 39, + 228, + 1, // Opcode: ST4i32 + /* 50785 */ MCD_OPC_FilterValue, + 1, + 233, + 209, + 0, // Skip to: 104527 + /* 50790 */ MCD_OPC_CheckPredicate, + 21, + 228, + 209, + 0, // Skip to: 104527 + /* 50795 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 221, + 209, + 0, // Skip to: 104527 + /* 50802 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 214, + 209, + 0, // Skip to: 104527 + /* 50809 */ MCD_OPC_Decode, + 154, + 39, + 229, + 1, // Opcode: ST4i64 + /* 50814 */ MCD_OPC_FilterValue, + 1, + 204, + 209, + 0, // Skip to: 104527 + /* 50819 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 50822 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 50832 + /* 50827 */ MCD_OPC_Decode, + 212, + 39, + 195, + 1, // Opcode: STPSi + /* 50832 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 50842 + /* 50837 */ MCD_OPC_Decode, + 206, + 39, + 195, + 1, // Opcode: STPDi + /* 50842 */ MCD_OPC_FilterValue, + 2, + 176, + 209, + 0, // Skip to: 104527 + /* 50847 */ MCD_OPC_Decode, + 209, + 39, + 195, + 1, // Opcode: STPQi + /* 50852 */ MCD_OPC_FilterValue, + 5, + 113, + 4, + 0, // Skip to: 51994 + /* 50857 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 50860 */ MCD_OPC_FilterValue, + 0, + 67, + 4, + 0, // Skip to: 51956 + /* 50865 */ MCD_OPC_ExtractField, + 13, + 9, // Inst{21-13} ... + /* 50868 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 50890 + /* 50873 */ MCD_OPC_CheckPredicate, + 21, + 145, + 209, + 0, // Skip to: 104527 + /* 50878 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 138, + 209, + 0, // Skip to: 104527 + /* 50885 */ MCD_OPC_Decode, + 241, + 22, + 230, + 1, // Opcode: LD1i8 + /* 50890 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 50912 + /* 50895 */ MCD_OPC_CheckPredicate, + 21, + 123, + 209, + 0, // Skip to: 104527 + /* 50900 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 116, + 209, + 0, // Skip to: 104527 + /* 50907 */ MCD_OPC_Decode, + 205, + 23, + 231, + 1, // Opcode: LD3i8 + /* 50912 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 50941 + /* 50917 */ MCD_OPC_CheckPredicate, + 21, + 101, + 209, + 0, // Skip to: 104527 + /* 50922 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 94, + 209, + 0, // Skip to: 104527 + /* 50929 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 87, + 209, + 0, // Skip to: 104527 + /* 50936 */ MCD_OPC_Decode, + 235, + 22, + 232, + 1, // Opcode: LD1i16 + /* 50941 */ MCD_OPC_FilterValue, + 3, + 24, + 0, + 0, // Skip to: 50970 + /* 50946 */ MCD_OPC_CheckPredicate, + 21, + 72, + 209, + 0, // Skip to: 104527 + /* 50951 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 65, + 209, + 0, // Skip to: 104527 + /* 50958 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 58, + 209, + 0, // Skip to: 104527 + /* 50965 */ MCD_OPC_Decode, + 199, + 23, + 233, + 1, // Opcode: LD3i16 + /* 50970 */ MCD_OPC_FilterValue, + 4, + 54, + 0, + 0, // Skip to: 51029 + /* 50975 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 50978 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 51000 + /* 50983 */ MCD_OPC_CheckPredicate, + 21, + 35, + 209, + 0, // Skip to: 104527 + /* 50988 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 28, + 209, + 0, // Skip to: 104527 + /* 50995 */ MCD_OPC_Decode, + 237, + 22, + 234, + 1, // Opcode: LD1i32 + /* 51000 */ MCD_OPC_FilterValue, + 1, + 18, + 209, + 0, // Skip to: 104527 + /* 51005 */ MCD_OPC_CheckPredicate, + 21, + 13, + 209, + 0, // Skip to: 104527 + /* 51010 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 6, + 209, + 0, // Skip to: 104527 + /* 51017 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 255, + 208, + 0, // Skip to: 104527 + /* 51024 */ MCD_OPC_Decode, + 239, + 22, + 235, + 1, // Opcode: LD1i64 + /* 51029 */ MCD_OPC_FilterValue, + 5, + 54, + 0, + 0, // Skip to: 51088 + /* 51034 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 51037 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 51059 + /* 51042 */ MCD_OPC_CheckPredicate, + 21, + 232, + 208, + 0, // Skip to: 104527 + /* 51047 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 225, + 208, + 0, // Skip to: 104527 + /* 51054 */ MCD_OPC_Decode, + 201, + 23, + 236, + 1, // Opcode: LD3i32 + /* 51059 */ MCD_OPC_FilterValue, + 1, + 215, + 208, + 0, // Skip to: 104527 + /* 51064 */ MCD_OPC_CheckPredicate, + 21, + 210, + 208, + 0, // Skip to: 104527 + /* 51069 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 203, + 208, + 0, // Skip to: 104527 + /* 51076 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 196, + 208, + 0, // Skip to: 104527 + /* 51083 */ MCD_OPC_Decode, + 203, + 23, + 237, + 1, // Opcode: LD3i64 + /* 51088 */ MCD_OPC_FilterValue, + 6, + 155, + 0, + 0, // Skip to: 51248 + /* 51093 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 51096 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 51134 + /* 51101 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51104 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51119 + /* 51109 */ MCD_OPC_CheckPredicate, + 21, + 165, + 208, + 0, // Skip to: 104527 + /* 51114 */ MCD_OPC_Decode, + 173, + 22, + 200, + 1, // Opcode: LD1Rv8b + /* 51119 */ MCD_OPC_FilterValue, + 1, + 155, + 208, + 0, // Skip to: 104527 + /* 51124 */ MCD_OPC_CheckPredicate, + 21, + 150, + 208, + 0, // Skip to: 104527 + /* 51129 */ MCD_OPC_Decode, + 161, + 22, + 204, + 1, // Opcode: LD1Rv16b + /* 51134 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 51172 + /* 51139 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51142 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51157 + /* 51147 */ MCD_OPC_CheckPredicate, + 21, + 127, + 208, + 0, // Skip to: 104527 + /* 51152 */ MCD_OPC_Decode, + 169, + 22, + 200, + 1, // Opcode: LD1Rv4h + /* 51157 */ MCD_OPC_FilterValue, + 1, + 117, + 208, + 0, // Skip to: 104527 + /* 51162 */ MCD_OPC_CheckPredicate, + 21, + 112, + 208, + 0, // Skip to: 104527 + /* 51167 */ MCD_OPC_Decode, + 175, + 22, + 204, + 1, // Opcode: LD1Rv8h + /* 51172 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 51210 + /* 51177 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51180 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51195 + /* 51185 */ MCD_OPC_CheckPredicate, + 21, + 89, + 208, + 0, // Skip to: 104527 + /* 51190 */ MCD_OPC_Decode, + 167, + 22, + 200, + 1, // Opcode: LD1Rv2s + /* 51195 */ MCD_OPC_FilterValue, + 1, + 79, + 208, + 0, // Skip to: 104527 + /* 51200 */ MCD_OPC_CheckPredicate, + 21, + 74, + 208, + 0, // Skip to: 104527 + /* 51205 */ MCD_OPC_Decode, + 171, + 22, + 204, + 1, // Opcode: LD1Rv4s + /* 51210 */ MCD_OPC_FilterValue, + 3, + 64, + 208, + 0, // Skip to: 104527 + /* 51215 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51218 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51233 + /* 51223 */ MCD_OPC_CheckPredicate, + 21, + 51, + 208, + 0, // Skip to: 104527 + /* 51228 */ MCD_OPC_Decode, + 163, + 22, + 200, + 1, // Opcode: LD1Rv1d + /* 51233 */ MCD_OPC_FilterValue, + 1, + 41, + 208, + 0, // Skip to: 104527 + /* 51238 */ MCD_OPC_CheckPredicate, + 21, + 36, + 208, + 0, // Skip to: 104527 + /* 51243 */ MCD_OPC_Decode, + 165, + 22, + 204, + 1, // Opcode: LD1Rv2d + /* 51248 */ MCD_OPC_FilterValue, + 7, + 155, + 0, + 0, // Skip to: 51408 + /* 51253 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 51256 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 51294 + /* 51261 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51264 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51279 + /* 51269 */ MCD_OPC_CheckPredicate, + 21, + 5, + 208, + 0, // Skip to: 104527 + /* 51274 */ MCD_OPC_Decode, + 179, + 23, + 199, + 1, // Opcode: LD3Rv8b + /* 51279 */ MCD_OPC_FilterValue, + 1, + 251, + 207, + 0, // Skip to: 104527 + /* 51284 */ MCD_OPC_CheckPredicate, + 21, + 246, + 207, + 0, // Skip to: 104527 + /* 51289 */ MCD_OPC_Decode, + 167, + 23, + 203, + 1, // Opcode: LD3Rv16b + /* 51294 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 51332 + /* 51299 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51302 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51317 + /* 51307 */ MCD_OPC_CheckPredicate, + 21, + 223, + 207, + 0, // Skip to: 104527 + /* 51312 */ MCD_OPC_Decode, + 175, + 23, + 199, + 1, // Opcode: LD3Rv4h + /* 51317 */ MCD_OPC_FilterValue, + 1, + 213, + 207, + 0, // Skip to: 104527 + /* 51322 */ MCD_OPC_CheckPredicate, + 21, + 208, + 207, + 0, // Skip to: 104527 + /* 51327 */ MCD_OPC_Decode, + 181, + 23, + 203, + 1, // Opcode: LD3Rv8h + /* 51332 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 51370 + /* 51337 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51340 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51355 + /* 51345 */ MCD_OPC_CheckPredicate, + 21, + 185, + 207, + 0, // Skip to: 104527 + /* 51350 */ MCD_OPC_Decode, + 173, + 23, + 199, + 1, // Opcode: LD3Rv2s + /* 51355 */ MCD_OPC_FilterValue, + 1, + 175, + 207, + 0, // Skip to: 104527 + /* 51360 */ MCD_OPC_CheckPredicate, + 21, + 170, + 207, + 0, // Skip to: 104527 + /* 51365 */ MCD_OPC_Decode, + 177, + 23, + 203, + 1, // Opcode: LD3Rv4s + /* 51370 */ MCD_OPC_FilterValue, + 3, + 160, + 207, + 0, // Skip to: 104527 + /* 51375 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51378 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51393 + /* 51383 */ MCD_OPC_CheckPredicate, + 21, + 147, + 207, + 0, // Skip to: 104527 + /* 51388 */ MCD_OPC_Decode, + 169, + 23, + 199, + 1, // Opcode: LD3Rv1d + /* 51393 */ MCD_OPC_FilterValue, + 1, + 137, + 207, + 0, // Skip to: 104527 + /* 51398 */ MCD_OPC_CheckPredicate, + 21, + 132, + 207, + 0, // Skip to: 104527 + /* 51403 */ MCD_OPC_Decode, + 171, + 23, + 203, + 1, // Opcode: LD3Rv2d + /* 51408 */ MCD_OPC_FilterValue, + 128, + 2, + 17, + 0, + 0, // Skip to: 51431 + /* 51414 */ MCD_OPC_CheckPredicate, + 21, + 116, + 207, + 0, // Skip to: 104527 + /* 51419 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 109, + 207, + 0, // Skip to: 104527 + /* 51426 */ MCD_OPC_Decode, + 159, + 23, + 238, + 1, // Opcode: LD2i8 + /* 51431 */ MCD_OPC_FilterValue, + 129, + 2, + 17, + 0, + 0, // Skip to: 51454 + /* 51437 */ MCD_OPC_CheckPredicate, + 21, + 93, + 207, + 0, // Skip to: 104527 + /* 51442 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 86, + 207, + 0, // Skip to: 104527 + /* 51449 */ MCD_OPC_Decode, + 251, + 23, + 239, + 1, // Opcode: LD4i8 + /* 51454 */ MCD_OPC_FilterValue, + 130, + 2, + 24, + 0, + 0, // Skip to: 51484 + /* 51460 */ MCD_OPC_CheckPredicate, + 21, + 70, + 207, + 0, // Skip to: 104527 + /* 51465 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 63, + 207, + 0, // Skip to: 104527 + /* 51472 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 56, + 207, + 0, // Skip to: 104527 + /* 51479 */ MCD_OPC_Decode, + 153, + 23, + 240, + 1, // Opcode: LD2i16 + /* 51484 */ MCD_OPC_FilterValue, + 131, + 2, + 24, + 0, + 0, // Skip to: 51514 + /* 51490 */ MCD_OPC_CheckPredicate, + 21, + 40, + 207, + 0, // Skip to: 104527 + /* 51495 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 33, + 207, + 0, // Skip to: 104527 + /* 51502 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 26, + 207, + 0, // Skip to: 104527 + /* 51509 */ MCD_OPC_Decode, + 245, + 23, + 241, + 1, // Opcode: LD4i16 + /* 51514 */ MCD_OPC_FilterValue, + 132, + 2, + 54, + 0, + 0, // Skip to: 51574 + /* 51520 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 51523 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 51545 + /* 51528 */ MCD_OPC_CheckPredicate, + 21, + 2, + 207, + 0, // Skip to: 104527 + /* 51533 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 251, + 206, + 0, // Skip to: 104527 + /* 51540 */ MCD_OPC_Decode, + 155, + 23, + 242, + 1, // Opcode: LD2i32 + /* 51545 */ MCD_OPC_FilterValue, + 1, + 241, + 206, + 0, // Skip to: 104527 + /* 51550 */ MCD_OPC_CheckPredicate, + 21, + 236, + 206, + 0, // Skip to: 104527 + /* 51555 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 229, + 206, + 0, // Skip to: 104527 + /* 51562 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 222, + 206, + 0, // Skip to: 104527 + /* 51569 */ MCD_OPC_Decode, + 157, + 23, + 243, + 1, // Opcode: LD2i64 + /* 51574 */ MCD_OPC_FilterValue, + 133, + 2, + 54, + 0, + 0, // Skip to: 51634 + /* 51580 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 51583 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 51605 + /* 51588 */ MCD_OPC_CheckPredicate, + 21, + 198, + 206, + 0, // Skip to: 104527 + /* 51593 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 191, + 206, + 0, // Skip to: 104527 + /* 51600 */ MCD_OPC_Decode, + 247, + 23, + 244, + 1, // Opcode: LD4i32 + /* 51605 */ MCD_OPC_FilterValue, + 1, + 181, + 206, + 0, // Skip to: 104527 + /* 51610 */ MCD_OPC_CheckPredicate, + 21, + 176, + 206, + 0, // Skip to: 104527 + /* 51615 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 169, + 206, + 0, // Skip to: 104527 + /* 51622 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 162, + 206, + 0, // Skip to: 104527 + /* 51629 */ MCD_OPC_Decode, + 249, + 23, + 245, + 1, // Opcode: LD4i64 + /* 51634 */ MCD_OPC_FilterValue, + 134, + 2, + 155, + 0, + 0, // Skip to: 51795 + /* 51640 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 51643 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 51681 + /* 51648 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51651 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51666 + /* 51656 */ MCD_OPC_CheckPredicate, + 21, + 130, + 206, + 0, // Skip to: 104527 + /* 51661 */ MCD_OPC_Decode, + 133, + 23, + 201, + 1, // Opcode: LD2Rv8b + /* 51666 */ MCD_OPC_FilterValue, + 1, + 120, + 206, + 0, // Skip to: 104527 + /* 51671 */ MCD_OPC_CheckPredicate, + 21, + 115, + 206, + 0, // Skip to: 104527 + /* 51676 */ MCD_OPC_Decode, + 249, + 22, + 205, + 1, // Opcode: LD2Rv16b + /* 51681 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 51719 + /* 51686 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51689 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51704 + /* 51694 */ MCD_OPC_CheckPredicate, + 21, + 92, + 206, + 0, // Skip to: 104527 + /* 51699 */ MCD_OPC_Decode, + 129, + 23, + 201, + 1, // Opcode: LD2Rv4h + /* 51704 */ MCD_OPC_FilterValue, + 1, + 82, + 206, + 0, // Skip to: 104527 + /* 51709 */ MCD_OPC_CheckPredicate, + 21, + 77, + 206, + 0, // Skip to: 104527 + /* 51714 */ MCD_OPC_Decode, + 135, + 23, + 205, + 1, // Opcode: LD2Rv8h + /* 51719 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 51757 + /* 51724 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51727 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51742 + /* 51732 */ MCD_OPC_CheckPredicate, + 21, + 54, + 206, + 0, // Skip to: 104527 + /* 51737 */ MCD_OPC_Decode, + 255, + 22, + 201, + 1, // Opcode: LD2Rv2s + /* 51742 */ MCD_OPC_FilterValue, + 1, + 44, + 206, + 0, // Skip to: 104527 + /* 51747 */ MCD_OPC_CheckPredicate, + 21, + 39, + 206, + 0, // Skip to: 104527 + /* 51752 */ MCD_OPC_Decode, + 131, + 23, + 205, + 1, // Opcode: LD2Rv4s + /* 51757 */ MCD_OPC_FilterValue, + 3, + 29, + 206, + 0, // Skip to: 104527 + /* 51762 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51765 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51780 + /* 51770 */ MCD_OPC_CheckPredicate, + 21, + 16, + 206, + 0, // Skip to: 104527 + /* 51775 */ MCD_OPC_Decode, + 251, + 22, + 201, + 1, // Opcode: LD2Rv1d + /* 51780 */ MCD_OPC_FilterValue, + 1, + 6, + 206, + 0, // Skip to: 104527 + /* 51785 */ MCD_OPC_CheckPredicate, + 21, + 1, + 206, + 0, // Skip to: 104527 + /* 51790 */ MCD_OPC_Decode, + 253, + 22, + 205, + 1, // Opcode: LD2Rv2d + /* 51795 */ MCD_OPC_FilterValue, + 135, + 2, + 246, + 205, + 0, // Skip to: 104527 + /* 51801 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 51804 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 51842 + /* 51809 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51812 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51827 + /* 51817 */ MCD_OPC_CheckPredicate, + 21, + 225, + 205, + 0, // Skip to: 104527 + /* 51822 */ MCD_OPC_Decode, + 239, + 23, + 198, + 1, // Opcode: LD4Rv8b + /* 51827 */ MCD_OPC_FilterValue, + 1, + 215, + 205, + 0, // Skip to: 104527 + /* 51832 */ MCD_OPC_CheckPredicate, + 21, + 210, + 205, + 0, // Skip to: 104527 + /* 51837 */ MCD_OPC_Decode, + 227, + 23, + 202, + 1, // Opcode: LD4Rv16b + /* 51842 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 51880 + /* 51847 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51850 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51865 + /* 51855 */ MCD_OPC_CheckPredicate, + 21, + 187, + 205, + 0, // Skip to: 104527 + /* 51860 */ MCD_OPC_Decode, + 235, + 23, + 198, + 1, // Opcode: LD4Rv4h + /* 51865 */ MCD_OPC_FilterValue, + 1, + 177, + 205, + 0, // Skip to: 104527 + /* 51870 */ MCD_OPC_CheckPredicate, + 21, + 172, + 205, + 0, // Skip to: 104527 + /* 51875 */ MCD_OPC_Decode, + 241, + 23, + 202, + 1, // Opcode: LD4Rv8h + /* 51880 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 51918 + /* 51885 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51888 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51903 + /* 51893 */ MCD_OPC_CheckPredicate, + 21, + 149, + 205, + 0, // Skip to: 104527 + /* 51898 */ MCD_OPC_Decode, + 233, + 23, + 198, + 1, // Opcode: LD4Rv2s + /* 51903 */ MCD_OPC_FilterValue, + 1, + 139, + 205, + 0, // Skip to: 104527 + /* 51908 */ MCD_OPC_CheckPredicate, + 21, + 134, + 205, + 0, // Skip to: 104527 + /* 51913 */ MCD_OPC_Decode, + 237, + 23, + 202, + 1, // Opcode: LD4Rv4s + /* 51918 */ MCD_OPC_FilterValue, + 3, + 124, + 205, + 0, // Skip to: 104527 + /* 51923 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51926 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51941 + /* 51931 */ MCD_OPC_CheckPredicate, + 21, + 111, + 205, + 0, // Skip to: 104527 + /* 51936 */ MCD_OPC_Decode, + 229, + 23, + 198, + 1, // Opcode: LD4Rv1d + /* 51941 */ MCD_OPC_FilterValue, + 1, + 101, + 205, + 0, // Skip to: 104527 + /* 51946 */ MCD_OPC_CheckPredicate, + 21, + 96, + 205, + 0, // Skip to: 104527 + /* 51951 */ MCD_OPC_Decode, + 231, + 23, + 202, + 1, // Opcode: LD4Rv2d + /* 51956 */ MCD_OPC_FilterValue, + 1, + 86, + 205, + 0, // Skip to: 104527 + /* 51961 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 51964 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 51974 + /* 51969 */ MCD_OPC_Decode, + 141, + 25, + 195, + 1, // Opcode: LDPSi + /* 51974 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 51984 + /* 51979 */ MCD_OPC_Decode, + 132, + 25, + 195, + 1, // Opcode: LDPDi + /* 51984 */ MCD_OPC_FilterValue, + 2, + 58, + 205, + 0, // Skip to: 104527 + /* 51989 */ MCD_OPC_Decode, + 135, + 25, + 195, + 1, // Opcode: LDPQi + /* 51994 */ MCD_OPC_FilterValue, + 6, + 25, + 2, + 0, // Skip to: 52536 + /* 51999 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 52002 */ MCD_OPC_FilterValue, + 0, + 235, + 1, + 0, // Skip to: 52498 + /* 52007 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 52010 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 52062 + /* 52015 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52018 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 52040 + /* 52023 */ MCD_OPC_CheckPredicate, + 21, + 19, + 205, + 0, // Skip to: 104527 + /* 52028 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 12, + 205, + 0, // Skip to: 104527 + /* 52035 */ MCD_OPC_Decode, + 192, + 38, + 246, + 1, // Opcode: ST1i8_POST + /* 52040 */ MCD_OPC_FilterValue, + 1, + 2, + 205, + 0, // Skip to: 104527 + /* 52045 */ MCD_OPC_CheckPredicate, + 21, + 253, + 204, + 0, // Skip to: 104527 + /* 52050 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 246, + 204, + 0, // Skip to: 104527 + /* 52057 */ MCD_OPC_Decode, + 225, + 38, + 247, + 1, // Opcode: ST2i8_POST + /* 52062 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 52114 + /* 52067 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52070 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 52092 + /* 52075 */ MCD_OPC_CheckPredicate, + 21, + 223, + 204, + 0, // Skip to: 104527 + /* 52080 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 216, + 204, + 0, // Skip to: 104527 + /* 52087 */ MCD_OPC_Decode, + 255, + 38, + 248, + 1, // Opcode: ST3i8_POST + /* 52092 */ MCD_OPC_FilterValue, + 1, + 206, + 204, + 0, // Skip to: 104527 + /* 52097 */ MCD_OPC_CheckPredicate, + 21, + 201, + 204, + 0, // Skip to: 104527 + /* 52102 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 194, + 204, + 0, // Skip to: 104527 + /* 52109 */ MCD_OPC_Decode, + 157, + 39, + 249, + 1, // Opcode: ST4i8_POST + /* 52114 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 52180 + /* 52119 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52122 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 52151 + /* 52127 */ MCD_OPC_CheckPredicate, + 21, + 171, + 204, + 0, // Skip to: 104527 + /* 52132 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 164, + 204, + 0, // Skip to: 104527 + /* 52139 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 157, + 204, + 0, // Skip to: 104527 + /* 52146 */ MCD_OPC_Decode, + 186, + 38, + 250, + 1, // Opcode: ST1i16_POST + /* 52151 */ MCD_OPC_FilterValue, + 1, + 147, + 204, + 0, // Skip to: 104527 + /* 52156 */ MCD_OPC_CheckPredicate, + 21, + 142, + 204, + 0, // Skip to: 104527 + /* 52161 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 135, + 204, + 0, // Skip to: 104527 + /* 52168 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 128, + 204, + 0, // Skip to: 104527 + /* 52175 */ MCD_OPC_Decode, + 219, + 38, + 251, + 1, // Opcode: ST2i16_POST + /* 52180 */ MCD_OPC_FilterValue, + 3, + 61, + 0, + 0, // Skip to: 52246 + /* 52185 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52188 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 52217 + /* 52193 */ MCD_OPC_CheckPredicate, + 21, + 105, + 204, + 0, // Skip to: 104527 + /* 52198 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 98, + 204, + 0, // Skip to: 104527 + /* 52205 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 91, + 204, + 0, // Skip to: 104527 + /* 52212 */ MCD_OPC_Decode, + 249, + 38, + 252, + 1, // Opcode: ST3i16_POST + /* 52217 */ MCD_OPC_FilterValue, + 1, + 81, + 204, + 0, // Skip to: 104527 + /* 52222 */ MCD_OPC_CheckPredicate, + 21, + 76, + 204, + 0, // Skip to: 104527 + /* 52227 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 69, + 204, + 0, // Skip to: 104527 + /* 52234 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 62, + 204, + 0, // Skip to: 104527 + /* 52241 */ MCD_OPC_Decode, + 151, + 39, + 253, + 1, // Opcode: ST4i16_POST + /* 52246 */ MCD_OPC_FilterValue, + 4, + 121, + 0, + 0, // Skip to: 52372 + /* 52251 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 52254 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 52306 + /* 52259 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52262 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 52284 + /* 52267 */ MCD_OPC_CheckPredicate, + 21, + 31, + 204, + 0, // Skip to: 104527 + /* 52272 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 24, + 204, + 0, // Skip to: 104527 + /* 52279 */ MCD_OPC_Decode, + 188, + 38, + 254, + 1, // Opcode: ST1i32_POST + /* 52284 */ MCD_OPC_FilterValue, + 1, + 14, + 204, + 0, // Skip to: 104527 + /* 52289 */ MCD_OPC_CheckPredicate, + 21, + 9, + 204, + 0, // Skip to: 104527 + /* 52294 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 2, + 204, + 0, // Skip to: 104527 + /* 52301 */ MCD_OPC_Decode, + 221, + 38, + 255, + 1, // Opcode: ST2i32_POST + /* 52306 */ MCD_OPC_FilterValue, + 1, + 248, + 203, + 0, // Skip to: 104527 + /* 52311 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52314 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 52343 + /* 52319 */ MCD_OPC_CheckPredicate, + 21, + 235, + 203, + 0, // Skip to: 104527 + /* 52324 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 228, + 203, + 0, // Skip to: 104527 + /* 52331 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 221, + 203, + 0, // Skip to: 104527 + /* 52338 */ MCD_OPC_Decode, + 190, + 38, + 128, + 2, // Opcode: ST1i64_POST + /* 52343 */ MCD_OPC_FilterValue, + 1, + 211, + 203, + 0, // Skip to: 104527 + /* 52348 */ MCD_OPC_CheckPredicate, + 21, + 206, + 203, + 0, // Skip to: 104527 + /* 52353 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 199, + 203, + 0, // Skip to: 104527 + /* 52360 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 192, + 203, + 0, // Skip to: 104527 + /* 52367 */ MCD_OPC_Decode, + 223, + 38, + 129, + 2, // Opcode: ST2i64_POST + /* 52372 */ MCD_OPC_FilterValue, + 5, + 182, + 203, + 0, // Skip to: 104527 + /* 52377 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 52380 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 52432 + /* 52385 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52388 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 52410 + /* 52393 */ MCD_OPC_CheckPredicate, + 21, + 161, + 203, + 0, // Skip to: 104527 + /* 52398 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 154, + 203, + 0, // Skip to: 104527 + /* 52405 */ MCD_OPC_Decode, + 251, + 38, + 130, + 2, // Opcode: ST3i32_POST + /* 52410 */ MCD_OPC_FilterValue, + 1, + 144, + 203, + 0, // Skip to: 104527 + /* 52415 */ MCD_OPC_CheckPredicate, + 21, + 139, + 203, + 0, // Skip to: 104527 + /* 52420 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 132, + 203, + 0, // Skip to: 104527 + /* 52427 */ MCD_OPC_Decode, + 153, + 39, + 131, + 2, // Opcode: ST4i32_POST + /* 52432 */ MCD_OPC_FilterValue, + 1, + 122, + 203, + 0, // Skip to: 104527 + /* 52437 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52440 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 52469 + /* 52445 */ MCD_OPC_CheckPredicate, + 21, + 109, + 203, + 0, // Skip to: 104527 + /* 52450 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 102, + 203, + 0, // Skip to: 104527 + /* 52457 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 95, + 203, + 0, // Skip to: 104527 + /* 52464 */ MCD_OPC_Decode, + 253, + 38, + 132, + 2, // Opcode: ST3i64_POST + /* 52469 */ MCD_OPC_FilterValue, + 1, + 85, + 203, + 0, // Skip to: 104527 + /* 52474 */ MCD_OPC_CheckPredicate, + 21, + 80, + 203, + 0, // Skip to: 104527 + /* 52479 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 73, + 203, + 0, // Skip to: 104527 + /* 52486 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 66, + 203, + 0, // Skip to: 104527 + /* 52493 */ MCD_OPC_Decode, + 155, + 39, + 133, + 2, // Opcode: ST4i64_POST + /* 52498 */ MCD_OPC_FilterValue, + 1, + 56, + 203, + 0, // Skip to: 104527 + /* 52503 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 52506 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 52516 + /* 52511 */ MCD_OPC_Decode, + 214, + 39, + 195, + 1, // Opcode: STPSpre + /* 52516 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 52526 + /* 52521 */ MCD_OPC_Decode, + 208, + 39, + 195, + 1, // Opcode: STPDpre + /* 52526 */ MCD_OPC_FilterValue, + 2, + 28, + 203, + 0, // Skip to: 104527 + /* 52531 */ MCD_OPC_Decode, + 211, + 39, + 195, + 1, // Opcode: STPQpre + /* 52536 */ MCD_OPC_FilterValue, + 7, + 201, + 4, + 0, // Skip to: 53766 + /* 52541 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 52544 */ MCD_OPC_FilterValue, + 0, + 155, + 4, + 0, // Skip to: 53728 + /* 52549 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 52552 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 52604 + /* 52557 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52560 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 52582 + /* 52565 */ MCD_OPC_CheckPredicate, + 21, + 245, + 202, + 0, // Skip to: 104527 + /* 52570 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 238, + 202, + 0, // Skip to: 104527 + /* 52577 */ MCD_OPC_Decode, + 242, + 22, + 134, + 2, // Opcode: LD1i8_POST + /* 52582 */ MCD_OPC_FilterValue, + 1, + 228, + 202, + 0, // Skip to: 104527 + /* 52587 */ MCD_OPC_CheckPredicate, + 21, + 223, + 202, + 0, // Skip to: 104527 + /* 52592 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 216, + 202, + 0, // Skip to: 104527 + /* 52599 */ MCD_OPC_Decode, + 160, + 23, + 135, + 2, // Opcode: LD2i8_POST + /* 52604 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 52656 + /* 52609 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52612 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 52634 + /* 52617 */ MCD_OPC_CheckPredicate, + 21, + 193, + 202, + 0, // Skip to: 104527 + /* 52622 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 186, + 202, + 0, // Skip to: 104527 + /* 52629 */ MCD_OPC_Decode, + 206, + 23, + 136, + 2, // Opcode: LD3i8_POST + /* 52634 */ MCD_OPC_FilterValue, + 1, + 176, + 202, + 0, // Skip to: 104527 + /* 52639 */ MCD_OPC_CheckPredicate, + 21, + 171, + 202, + 0, // Skip to: 104527 + /* 52644 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 164, + 202, + 0, // Skip to: 104527 + /* 52651 */ MCD_OPC_Decode, + 252, + 23, + 137, + 2, // Opcode: LD4i8_POST + /* 52656 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 52722 + /* 52661 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52664 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 52693 + /* 52669 */ MCD_OPC_CheckPredicate, + 21, + 141, + 202, + 0, // Skip to: 104527 + /* 52674 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 134, + 202, + 0, // Skip to: 104527 + /* 52681 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 127, + 202, + 0, // Skip to: 104527 + /* 52688 */ MCD_OPC_Decode, + 236, + 22, + 138, + 2, // Opcode: LD1i16_POST + /* 52693 */ MCD_OPC_FilterValue, + 1, + 117, + 202, + 0, // Skip to: 104527 + /* 52698 */ MCD_OPC_CheckPredicate, + 21, + 112, + 202, + 0, // Skip to: 104527 + /* 52703 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 105, + 202, + 0, // Skip to: 104527 + /* 52710 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 98, + 202, + 0, // Skip to: 104527 + /* 52717 */ MCD_OPC_Decode, + 154, + 23, + 139, + 2, // Opcode: LD2i16_POST + /* 52722 */ MCD_OPC_FilterValue, + 3, + 61, + 0, + 0, // Skip to: 52788 + /* 52727 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52730 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 52759 + /* 52735 */ MCD_OPC_CheckPredicate, + 21, + 75, + 202, + 0, // Skip to: 104527 + /* 52740 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 68, + 202, + 0, // Skip to: 104527 + /* 52747 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 61, + 202, + 0, // Skip to: 104527 + /* 52754 */ MCD_OPC_Decode, + 200, + 23, + 140, + 2, // Opcode: LD3i16_POST + /* 52759 */ MCD_OPC_FilterValue, + 1, + 51, + 202, + 0, // Skip to: 104527 + /* 52764 */ MCD_OPC_CheckPredicate, + 21, + 46, + 202, + 0, // Skip to: 104527 + /* 52769 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 39, + 202, + 0, // Skip to: 104527 + /* 52776 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 32, + 202, + 0, // Skip to: 104527 + /* 52783 */ MCD_OPC_Decode, + 246, + 23, + 141, + 2, // Opcode: LD4i16_POST + /* 52788 */ MCD_OPC_FilterValue, + 4, + 121, + 0, + 0, // Skip to: 52914 + /* 52793 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 52796 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 52848 + /* 52801 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52804 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 52826 + /* 52809 */ MCD_OPC_CheckPredicate, + 21, + 1, + 202, + 0, // Skip to: 104527 + /* 52814 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 250, + 201, + 0, // Skip to: 104527 + /* 52821 */ MCD_OPC_Decode, + 238, + 22, + 142, + 2, // Opcode: LD1i32_POST + /* 52826 */ MCD_OPC_FilterValue, + 1, + 240, + 201, + 0, // Skip to: 104527 + /* 52831 */ MCD_OPC_CheckPredicate, + 21, + 235, + 201, + 0, // Skip to: 104527 + /* 52836 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 228, + 201, + 0, // Skip to: 104527 + /* 52843 */ MCD_OPC_Decode, + 156, + 23, + 143, + 2, // Opcode: LD2i32_POST + /* 52848 */ MCD_OPC_FilterValue, + 1, + 218, + 201, + 0, // Skip to: 104527 + /* 52853 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52856 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 52885 + /* 52861 */ MCD_OPC_CheckPredicate, + 21, + 205, + 201, + 0, // Skip to: 104527 + /* 52866 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 198, + 201, + 0, // Skip to: 104527 + /* 52873 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 191, + 201, + 0, // Skip to: 104527 + /* 52880 */ MCD_OPC_Decode, + 240, + 22, + 144, + 2, // Opcode: LD1i64_POST + /* 52885 */ MCD_OPC_FilterValue, + 1, + 181, + 201, + 0, // Skip to: 104527 + /* 52890 */ MCD_OPC_CheckPredicate, + 21, + 176, + 201, + 0, // Skip to: 104527 + /* 52895 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 169, + 201, + 0, // Skip to: 104527 + /* 52902 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 162, + 201, + 0, // Skip to: 104527 + /* 52909 */ MCD_OPC_Decode, + 158, + 23, + 145, + 2, // Opcode: LD2i64_POST + /* 52914 */ MCD_OPC_FilterValue, + 5, + 121, + 0, + 0, // Skip to: 53040 + /* 52919 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 52922 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 52974 + /* 52927 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52930 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 52952 + /* 52935 */ MCD_OPC_CheckPredicate, + 21, + 131, + 201, + 0, // Skip to: 104527 + /* 52940 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 124, + 201, + 0, // Skip to: 104527 + /* 52947 */ MCD_OPC_Decode, + 202, + 23, + 146, + 2, // Opcode: LD3i32_POST + /* 52952 */ MCD_OPC_FilterValue, + 1, + 114, + 201, + 0, // Skip to: 104527 + /* 52957 */ MCD_OPC_CheckPredicate, + 21, + 109, + 201, + 0, // Skip to: 104527 + /* 52962 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 102, + 201, + 0, // Skip to: 104527 + /* 52969 */ MCD_OPC_Decode, + 248, + 23, + 147, + 2, // Opcode: LD4i32_POST + /* 52974 */ MCD_OPC_FilterValue, + 1, + 92, + 201, + 0, // Skip to: 104527 + /* 52979 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 52982 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 53011 + /* 52987 */ MCD_OPC_CheckPredicate, + 21, + 79, + 201, + 0, // Skip to: 104527 + /* 52992 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 72, + 201, + 0, // Skip to: 104527 + /* 52999 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 65, + 201, + 0, // Skip to: 104527 + /* 53006 */ MCD_OPC_Decode, + 204, + 23, + 148, + 2, // Opcode: LD3i64_POST + /* 53011 */ MCD_OPC_FilterValue, + 1, + 55, + 201, + 0, // Skip to: 104527 + /* 53016 */ MCD_OPC_CheckPredicate, + 21, + 50, + 201, + 0, // Skip to: 104527 + /* 53021 */ MCD_OPC_CheckField, + 31, + 1, + 0, + 43, + 201, + 0, // Skip to: 104527 + /* 53028 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 36, + 201, + 0, // Skip to: 104527 + /* 53035 */ MCD_OPC_Decode, + 250, + 23, + 149, + 2, // Opcode: LD4i64_POST + /* 53040 */ MCD_OPC_FilterValue, + 6, + 83, + 1, + 0, // Skip to: 53384 + /* 53045 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 53048 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 53132 + /* 53053 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53056 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 53094 + /* 53061 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53064 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53079 + /* 53069 */ MCD_OPC_CheckPredicate, + 21, + 253, + 200, + 0, // Skip to: 104527 + /* 53074 */ MCD_OPC_Decode, + 174, + 22, + 208, + 1, // Opcode: LD1Rv8b_POST + /* 53079 */ MCD_OPC_FilterValue, + 1, + 243, + 200, + 0, // Skip to: 104527 + /* 53084 */ MCD_OPC_CheckPredicate, + 21, + 238, + 200, + 0, // Skip to: 104527 + /* 53089 */ MCD_OPC_Decode, + 162, + 22, + 212, + 1, // Opcode: LD1Rv16b_POST + /* 53094 */ MCD_OPC_FilterValue, + 1, + 228, + 200, + 0, // Skip to: 104527 + /* 53099 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53102 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53117 + /* 53107 */ MCD_OPC_CheckPredicate, + 21, + 215, + 200, + 0, // Skip to: 104527 + /* 53112 */ MCD_OPC_Decode, + 134, + 23, + 209, + 1, // Opcode: LD2Rv8b_POST + /* 53117 */ MCD_OPC_FilterValue, + 1, + 205, + 200, + 0, // Skip to: 104527 + /* 53122 */ MCD_OPC_CheckPredicate, + 21, + 200, + 200, + 0, // Skip to: 104527 + /* 53127 */ MCD_OPC_Decode, + 250, + 22, + 213, + 1, // Opcode: LD2Rv16b_POST + /* 53132 */ MCD_OPC_FilterValue, + 1, + 79, + 0, + 0, // Skip to: 53216 + /* 53137 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53140 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 53178 + /* 53145 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53148 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53163 + /* 53153 */ MCD_OPC_CheckPredicate, + 21, + 169, + 200, + 0, // Skip to: 104527 + /* 53158 */ MCD_OPC_Decode, + 170, + 22, + 208, + 1, // Opcode: LD1Rv4h_POST + /* 53163 */ MCD_OPC_FilterValue, + 1, + 159, + 200, + 0, // Skip to: 104527 + /* 53168 */ MCD_OPC_CheckPredicate, + 21, + 154, + 200, + 0, // Skip to: 104527 + /* 53173 */ MCD_OPC_Decode, + 176, + 22, + 212, + 1, // Opcode: LD1Rv8h_POST + /* 53178 */ MCD_OPC_FilterValue, + 1, + 144, + 200, + 0, // Skip to: 104527 + /* 53183 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53186 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53201 + /* 53191 */ MCD_OPC_CheckPredicate, + 21, + 131, + 200, + 0, // Skip to: 104527 + /* 53196 */ MCD_OPC_Decode, + 130, + 23, + 209, + 1, // Opcode: LD2Rv4h_POST + /* 53201 */ MCD_OPC_FilterValue, + 1, + 121, + 200, + 0, // Skip to: 104527 + /* 53206 */ MCD_OPC_CheckPredicate, + 21, + 116, + 200, + 0, // Skip to: 104527 + /* 53211 */ MCD_OPC_Decode, + 136, + 23, + 213, + 1, // Opcode: LD2Rv8h_POST + /* 53216 */ MCD_OPC_FilterValue, + 2, + 79, + 0, + 0, // Skip to: 53300 + /* 53221 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53224 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 53262 + /* 53229 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53232 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53247 + /* 53237 */ MCD_OPC_CheckPredicate, + 21, + 85, + 200, + 0, // Skip to: 104527 + /* 53242 */ MCD_OPC_Decode, + 168, + 22, + 208, + 1, // Opcode: LD1Rv2s_POST + /* 53247 */ MCD_OPC_FilterValue, + 1, + 75, + 200, + 0, // Skip to: 104527 + /* 53252 */ MCD_OPC_CheckPredicate, + 21, + 70, + 200, + 0, // Skip to: 104527 + /* 53257 */ MCD_OPC_Decode, + 172, + 22, + 212, + 1, // Opcode: LD1Rv4s_POST + /* 53262 */ MCD_OPC_FilterValue, + 1, + 60, + 200, + 0, // Skip to: 104527 + /* 53267 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53270 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53285 + /* 53275 */ MCD_OPC_CheckPredicate, + 21, + 47, + 200, + 0, // Skip to: 104527 + /* 53280 */ MCD_OPC_Decode, + 128, + 23, + 209, + 1, // Opcode: LD2Rv2s_POST + /* 53285 */ MCD_OPC_FilterValue, + 1, + 37, + 200, + 0, // Skip to: 104527 + /* 53290 */ MCD_OPC_CheckPredicate, + 21, + 32, + 200, + 0, // Skip to: 104527 + /* 53295 */ MCD_OPC_Decode, + 132, + 23, + 213, + 1, // Opcode: LD2Rv4s_POST + /* 53300 */ MCD_OPC_FilterValue, + 3, + 22, + 200, + 0, // Skip to: 104527 + /* 53305 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53308 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 53346 + /* 53313 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53316 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53331 + /* 53321 */ MCD_OPC_CheckPredicate, + 21, + 1, + 200, + 0, // Skip to: 104527 + /* 53326 */ MCD_OPC_Decode, + 164, + 22, + 208, + 1, // Opcode: LD1Rv1d_POST + /* 53331 */ MCD_OPC_FilterValue, + 1, + 247, + 199, + 0, // Skip to: 104527 + /* 53336 */ MCD_OPC_CheckPredicate, + 21, + 242, + 199, + 0, // Skip to: 104527 + /* 53341 */ MCD_OPC_Decode, + 166, + 22, + 212, + 1, // Opcode: LD1Rv2d_POST + /* 53346 */ MCD_OPC_FilterValue, + 1, + 232, + 199, + 0, // Skip to: 104527 + /* 53351 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53354 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53369 + /* 53359 */ MCD_OPC_CheckPredicate, + 21, + 219, + 199, + 0, // Skip to: 104527 + /* 53364 */ MCD_OPC_Decode, + 252, + 22, + 209, + 1, // Opcode: LD2Rv1d_POST + /* 53369 */ MCD_OPC_FilterValue, + 1, + 209, + 199, + 0, // Skip to: 104527 + /* 53374 */ MCD_OPC_CheckPredicate, + 21, + 204, + 199, + 0, // Skip to: 104527 + /* 53379 */ MCD_OPC_Decode, + 254, + 22, + 213, + 1, // Opcode: LD2Rv2d_POST + /* 53384 */ MCD_OPC_FilterValue, + 7, + 194, + 199, + 0, // Skip to: 104527 + /* 53389 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 53392 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 53476 + /* 53397 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53400 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 53438 + /* 53405 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53408 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53423 + /* 53413 */ MCD_OPC_CheckPredicate, + 21, + 165, + 199, + 0, // Skip to: 104527 + /* 53418 */ MCD_OPC_Decode, + 180, + 23, + 207, + 1, // Opcode: LD3Rv8b_POST + /* 53423 */ MCD_OPC_FilterValue, + 1, + 155, + 199, + 0, // Skip to: 104527 + /* 53428 */ MCD_OPC_CheckPredicate, + 21, + 150, + 199, + 0, // Skip to: 104527 + /* 53433 */ MCD_OPC_Decode, + 168, + 23, + 211, + 1, // Opcode: LD3Rv16b_POST + /* 53438 */ MCD_OPC_FilterValue, + 1, + 140, + 199, + 0, // Skip to: 104527 + /* 53443 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53446 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53461 + /* 53451 */ MCD_OPC_CheckPredicate, + 21, + 127, + 199, + 0, // Skip to: 104527 + /* 53456 */ MCD_OPC_Decode, + 240, + 23, + 206, + 1, // Opcode: LD4Rv8b_POST + /* 53461 */ MCD_OPC_FilterValue, + 1, + 117, + 199, + 0, // Skip to: 104527 + /* 53466 */ MCD_OPC_CheckPredicate, + 21, + 112, + 199, + 0, // Skip to: 104527 + /* 53471 */ MCD_OPC_Decode, + 228, + 23, + 210, + 1, // Opcode: LD4Rv16b_POST + /* 53476 */ MCD_OPC_FilterValue, + 1, + 79, + 0, + 0, // Skip to: 53560 + /* 53481 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53484 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 53522 + /* 53489 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53492 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53507 + /* 53497 */ MCD_OPC_CheckPredicate, + 21, + 81, + 199, + 0, // Skip to: 104527 + /* 53502 */ MCD_OPC_Decode, + 176, + 23, + 207, + 1, // Opcode: LD3Rv4h_POST + /* 53507 */ MCD_OPC_FilterValue, + 1, + 71, + 199, + 0, // Skip to: 104527 + /* 53512 */ MCD_OPC_CheckPredicate, + 21, + 66, + 199, + 0, // Skip to: 104527 + /* 53517 */ MCD_OPC_Decode, + 182, + 23, + 211, + 1, // Opcode: LD3Rv8h_POST + /* 53522 */ MCD_OPC_FilterValue, + 1, + 56, + 199, + 0, // Skip to: 104527 + /* 53527 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53530 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53545 + /* 53535 */ MCD_OPC_CheckPredicate, + 21, + 43, + 199, + 0, // Skip to: 104527 + /* 53540 */ MCD_OPC_Decode, + 236, + 23, + 206, + 1, // Opcode: LD4Rv4h_POST + /* 53545 */ MCD_OPC_FilterValue, + 1, + 33, + 199, + 0, // Skip to: 104527 + /* 53550 */ MCD_OPC_CheckPredicate, + 21, + 28, + 199, + 0, // Skip to: 104527 + /* 53555 */ MCD_OPC_Decode, + 242, + 23, + 210, + 1, // Opcode: LD4Rv8h_POST + /* 53560 */ MCD_OPC_FilterValue, + 2, + 79, + 0, + 0, // Skip to: 53644 + /* 53565 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53568 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 53606 + /* 53573 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53576 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53591 + /* 53581 */ MCD_OPC_CheckPredicate, + 21, + 253, + 198, + 0, // Skip to: 104527 + /* 53586 */ MCD_OPC_Decode, + 174, + 23, + 207, + 1, // Opcode: LD3Rv2s_POST + /* 53591 */ MCD_OPC_FilterValue, + 1, + 243, + 198, + 0, // Skip to: 104527 + /* 53596 */ MCD_OPC_CheckPredicate, + 21, + 238, + 198, + 0, // Skip to: 104527 + /* 53601 */ MCD_OPC_Decode, + 178, + 23, + 211, + 1, // Opcode: LD3Rv4s_POST + /* 53606 */ MCD_OPC_FilterValue, + 1, + 228, + 198, + 0, // Skip to: 104527 + /* 53611 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53614 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53629 + /* 53619 */ MCD_OPC_CheckPredicate, + 21, + 215, + 198, + 0, // Skip to: 104527 + /* 53624 */ MCD_OPC_Decode, + 234, + 23, + 206, + 1, // Opcode: LD4Rv2s_POST + /* 53629 */ MCD_OPC_FilterValue, + 1, + 205, + 198, + 0, // Skip to: 104527 + /* 53634 */ MCD_OPC_CheckPredicate, + 21, + 200, + 198, + 0, // Skip to: 104527 + /* 53639 */ MCD_OPC_Decode, + 238, + 23, + 210, + 1, // Opcode: LD4Rv4s_POST + /* 53644 */ MCD_OPC_FilterValue, + 3, + 190, + 198, + 0, // Skip to: 104527 + /* 53649 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53652 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 53690 + /* 53657 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53660 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53675 + /* 53665 */ MCD_OPC_CheckPredicate, + 21, + 169, + 198, + 0, // Skip to: 104527 + /* 53670 */ MCD_OPC_Decode, + 170, + 23, + 207, + 1, // Opcode: LD3Rv1d_POST + /* 53675 */ MCD_OPC_FilterValue, + 1, + 159, + 198, + 0, // Skip to: 104527 + /* 53680 */ MCD_OPC_CheckPredicate, + 21, + 154, + 198, + 0, // Skip to: 104527 + /* 53685 */ MCD_OPC_Decode, + 172, + 23, + 211, + 1, // Opcode: LD3Rv2d_POST + /* 53690 */ MCD_OPC_FilterValue, + 1, + 144, + 198, + 0, // Skip to: 104527 + /* 53695 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53698 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53713 + /* 53703 */ MCD_OPC_CheckPredicate, + 21, + 131, + 198, + 0, // Skip to: 104527 + /* 53708 */ MCD_OPC_Decode, + 230, + 23, + 206, + 1, // Opcode: LD4Rv1d_POST + /* 53713 */ MCD_OPC_FilterValue, + 1, + 121, + 198, + 0, // Skip to: 104527 + /* 53718 */ MCD_OPC_CheckPredicate, + 21, + 116, + 198, + 0, // Skip to: 104527 + /* 53723 */ MCD_OPC_Decode, + 232, + 23, + 210, + 1, // Opcode: LD4Rv2d_POST + /* 53728 */ MCD_OPC_FilterValue, + 1, + 106, + 198, + 0, // Skip to: 104527 + /* 53733 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 53736 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 53746 + /* 53741 */ MCD_OPC_Decode, + 143, + 25, + 195, + 1, // Opcode: LDPSpre + /* 53746 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 53756 + /* 53751 */ MCD_OPC_Decode, + 134, + 25, + 195, + 1, // Opcode: LDPDpre + /* 53756 */ MCD_OPC_FilterValue, + 2, + 78, + 198, + 0, // Skip to: 104527 + /* 53761 */ MCD_OPC_Decode, + 137, + 25, + 195, + 1, // Opcode: LDPQpre + /* 53766 */ MCD_OPC_FilterValue, + 8, + 153, + 28, + 0, // Skip to: 61092 + /* 53771 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 53774 */ MCD_OPC_FilterValue, + 0, + 80, + 8, + 0, // Skip to: 55907 + /* 53779 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 53782 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 53820 + /* 53787 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53790 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 53805 + /* 53795 */ MCD_OPC_CheckPredicate, + 21, + 39, + 198, + 0, // Skip to: 104527 + /* 53800 */ MCD_OPC_Decode, + 162, + 41, + 150, + 2, // Opcode: TBLv8i8One + /* 53805 */ MCD_OPC_FilterValue, + 1, + 29, + 198, + 0, // Skip to: 104527 + /* 53810 */ MCD_OPC_CheckPredicate, + 21, + 24, + 198, + 0, // Skip to: 104527 + /* 53815 */ MCD_OPC_Decode, + 168, + 30, + 151, + 2, // Opcode: SADDLv8i8_v8i16 + /* 53820 */ MCD_OPC_FilterValue, + 1, + 86, + 0, + 0, // Skip to: 53911 + /* 53825 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53828 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 53896 + /* 53833 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 53836 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 53881 + /* 53841 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 53844 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 53866 + /* 53849 */ MCD_OPC_CheckPredicate, + 21, + 241, + 197, + 0, // Skip to: 104527 + /* 53854 */ MCD_OPC_CheckField, + 18, + 1, + 1, + 234, + 197, + 0, // Skip to: 104527 + /* 53861 */ MCD_OPC_Decode, + 140, + 12, + 152, + 2, // Opcode: DUPv2i32lane + /* 53866 */ MCD_OPC_FilterValue, + 1, + 224, + 197, + 0, // Skip to: 104527 + /* 53871 */ MCD_OPC_CheckPredicate, + 21, + 219, + 197, + 0, // Skip to: 104527 + /* 53876 */ MCD_OPC_Decode, + 144, + 12, + 153, + 2, // Opcode: DUPv4i16lane + /* 53881 */ MCD_OPC_FilterValue, + 1, + 209, + 197, + 0, // Skip to: 104527 + /* 53886 */ MCD_OPC_CheckPredicate, + 21, + 204, + 197, + 0, // Skip to: 104527 + /* 53891 */ MCD_OPC_Decode, + 150, + 12, + 154, + 2, // Opcode: DUPv8i8lane + /* 53896 */ MCD_OPC_FilterValue, + 1, + 194, + 197, + 0, // Skip to: 104527 + /* 53901 */ MCD_OPC_CheckPredicate, + 21, + 189, + 197, + 0, // Skip to: 104527 + /* 53906 */ MCD_OPC_Decode, + 151, + 31, + 155, + 2, // Opcode: SHADDv8i8 + /* 53911 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 53933 + /* 53916 */ MCD_OPC_CheckPredicate, + 21, + 174, + 197, + 0, // Skip to: 104527 + /* 53921 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 167, + 197, + 0, // Skip to: 104527 + /* 53928 */ MCD_OPC_Decode, + 173, + 29, + 156, + 2, // Opcode: REV64v8i8 + /* 53933 */ MCD_OPC_FilterValue, + 3, + 86, + 0, + 0, // Skip to: 54024 + /* 53938 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 53941 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 54009 + /* 53946 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 53949 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 53994 + /* 53954 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 53957 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 53979 + /* 53962 */ MCD_OPC_CheckPredicate, + 21, + 128, + 197, + 0, // Skip to: 104527 + /* 53967 */ MCD_OPC_CheckField, + 18, + 1, + 1, + 121, + 197, + 0, // Skip to: 104527 + /* 53974 */ MCD_OPC_Decode, + 139, + 12, + 157, + 2, // Opcode: DUPv2i32gpr + /* 53979 */ MCD_OPC_FilterValue, + 1, + 111, + 197, + 0, // Skip to: 104527 + /* 53984 */ MCD_OPC_CheckPredicate, + 21, + 106, + 197, + 0, // Skip to: 104527 + /* 53989 */ MCD_OPC_Decode, + 143, + 12, + 157, + 2, // Opcode: DUPv4i16gpr + /* 53994 */ MCD_OPC_FilterValue, + 1, + 96, + 197, + 0, // Skip to: 104527 + /* 53999 */ MCD_OPC_CheckPredicate, + 21, + 91, + 197, + 0, // Skip to: 104527 + /* 54004 */ MCD_OPC_Decode, + 149, + 12, + 157, + 2, // Opcode: DUPv8i8gpr + /* 54009 */ MCD_OPC_FilterValue, + 1, + 81, + 197, + 0, // Skip to: 104527 + /* 54014 */ MCD_OPC_CheckPredicate, + 21, + 76, + 197, + 0, // Skip to: 104527 + /* 54019 */ MCD_OPC_Decode, + 158, + 33, + 155, + 2, // Opcode: SQADDv8i8 + /* 54024 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 54062 + /* 54029 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54032 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54047 + /* 54037 */ MCD_OPC_CheckPredicate, + 21, + 53, + 197, + 0, // Skip to: 104527 + /* 54042 */ MCD_OPC_Decode, + 176, + 41, + 158, + 2, // Opcode: TBXv8i8One + /* 54047 */ MCD_OPC_FilterValue, + 1, + 43, + 197, + 0, // Skip to: 104527 + /* 54052 */ MCD_OPC_CheckPredicate, + 21, + 38, + 197, + 0, // Skip to: 104527 + /* 54057 */ MCD_OPC_Decode, + 183, + 30, + 159, + 2, // Opcode: SADDWv8i8_v8i16 + /* 54062 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 54084 + /* 54067 */ MCD_OPC_CheckPredicate, + 21, + 23, + 197, + 0, // Skip to: 104527 + /* 54072 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 16, + 197, + 0, // Skip to: 104527 + /* 54079 */ MCD_OPC_Decode, + 186, + 36, + 155, + 2, // Opcode: SRHADDv8i8 + /* 54084 */ MCD_OPC_FilterValue, + 6, + 40, + 0, + 0, // Skip to: 54129 + /* 54089 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54092 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54107 + /* 54097 */ MCD_OPC_CheckPredicate, + 21, + 249, + 196, + 0, // Skip to: 104527 + /* 54102 */ MCD_OPC_Decode, + 139, + 47, + 155, + 2, // Opcode: UZP1v8i8 + /* 54107 */ MCD_OPC_FilterValue, + 1, + 239, + 196, + 0, // Skip to: 104527 + /* 54112 */ MCD_OPC_CheckPredicate, + 21, + 234, + 196, + 0, // Skip to: 104527 + /* 54117 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 227, + 196, + 0, // Skip to: 104527 + /* 54124 */ MCD_OPC_Decode, + 162, + 29, + 156, + 2, // Opcode: REV16v8i8 + /* 54129 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 54151 + /* 54134 */ MCD_OPC_CheckPredicate, + 21, + 212, + 196, + 0, // Skip to: 104527 + /* 54139 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 205, + 196, + 0, // Skip to: 104527 + /* 54146 */ MCD_OPC_Decode, + 137, + 8, + 155, + 2, // Opcode: ANDv8i8 + /* 54151 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 54189 + /* 54156 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54159 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54174 + /* 54164 */ MCD_OPC_CheckPredicate, + 21, + 182, + 196, + 0, // Skip to: 104527 + /* 54169 */ MCD_OPC_Decode, + 164, + 41, + 160, + 2, // Opcode: TBLv8i8Two + /* 54174 */ MCD_OPC_FilterValue, + 1, + 172, + 196, + 0, // Skip to: 104527 + /* 54179 */ MCD_OPC_CheckPredicate, + 21, + 167, + 196, + 0, // Skip to: 104527 + /* 54184 */ MCD_OPC_Decode, + 206, + 37, + 151, + 2, // Opcode: SSUBLv8i8_v8i16 + /* 54189 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 54211 + /* 54194 */ MCD_OPC_CheckPredicate, + 21, + 152, + 196, + 0, // Skip to: 104527 + /* 54199 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 145, + 196, + 0, // Skip to: 104527 + /* 54206 */ MCD_OPC_Decode, + 191, + 31, + 155, + 2, // Opcode: SHSUBv8i8 + /* 54211 */ MCD_OPC_FilterValue, + 10, + 56, + 0, + 0, // Skip to: 54272 + /* 54216 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54219 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54234 + /* 54224 */ MCD_OPC_CheckPredicate, + 21, + 122, + 196, + 0, // Skip to: 104527 + /* 54229 */ MCD_OPC_Decode, + 198, + 41, + 155, + 2, // Opcode: TRN1v8i8 + /* 54234 */ MCD_OPC_FilterValue, + 1, + 112, + 196, + 0, // Skip to: 104527 + /* 54239 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 54242 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54257 + /* 54247 */ MCD_OPC_CheckPredicate, + 21, + 99, + 196, + 0, // Skip to: 104527 + /* 54252 */ MCD_OPC_Decode, + 154, + 30, + 156, + 2, // Opcode: SADDLPv8i8_v4i16 + /* 54257 */ MCD_OPC_FilterValue, + 1, + 89, + 196, + 0, // Skip to: 104527 + /* 54262 */ MCD_OPC_CheckPredicate, + 21, + 84, + 196, + 0, // Skip to: 104527 + /* 54267 */ MCD_OPC_Decode, + 245, + 47, + 161, + 2, // Opcode: XTNv8i8 + /* 54272 */ MCD_OPC_FilterValue, + 11, + 98, + 0, + 0, // Skip to: 54375 + /* 54277 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54280 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 54360 + /* 54285 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 54288 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 54328 + /* 54293 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 54296 */ MCD_OPC_FilterValue, + 1, + 50, + 196, + 0, // Skip to: 104527 + /* 54301 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 54318 + /* 54306 */ MCD_OPC_CheckField, + 18, + 3, + 0, + 5, + 0, + 0, // Skip to: 54318 + /* 54313 */ MCD_OPC_Decode, + 202, + 32, + 162, + 2, // Opcode: SMOVvi16to32_idx0 + /* 54318 */ MCD_OPC_CheckPredicate, + 21, + 28, + 196, + 0, // Skip to: 104527 + /* 54323 */ MCD_OPC_Decode, + 201, + 32, + 163, + 2, // Opcode: SMOVvi16to32 + /* 54328 */ MCD_OPC_FilterValue, + 1, + 18, + 196, + 0, // Skip to: 104527 + /* 54333 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 54350 + /* 54338 */ MCD_OPC_CheckField, + 17, + 4, + 0, + 5, + 0, + 0, // Skip to: 54350 + /* 54345 */ MCD_OPC_Decode, + 208, + 32, + 162, + 2, // Opcode: SMOVvi8to32_idx0 + /* 54350 */ MCD_OPC_CheckPredicate, + 21, + 252, + 195, + 0, // Skip to: 104527 + /* 54355 */ MCD_OPC_Decode, + 207, + 32, + 164, + 2, // Opcode: SMOVvi8to32 + /* 54360 */ MCD_OPC_FilterValue, + 1, + 242, + 195, + 0, // Skip to: 104527 + /* 54365 */ MCD_OPC_CheckPredicate, + 21, + 237, + 195, + 0, // Skip to: 104527 + /* 54370 */ MCD_OPC_Decode, + 146, + 36, + 155, + 2, // Opcode: SQSUBv8i8 + /* 54375 */ MCD_OPC_FilterValue, + 12, + 33, + 0, + 0, // Skip to: 54413 + /* 54380 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54383 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54398 + /* 54388 */ MCD_OPC_CheckPredicate, + 21, + 214, + 195, + 0, // Skip to: 104527 + /* 54393 */ MCD_OPC_Decode, + 178, + 41, + 165, + 2, // Opcode: TBXv8i8Two + /* 54398 */ MCD_OPC_FilterValue, + 1, + 204, + 195, + 0, // Skip to: 104527 + /* 54403 */ MCD_OPC_CheckPredicate, + 21, + 199, + 195, + 0, // Skip to: 104527 + /* 54408 */ MCD_OPC_Decode, + 218, + 37, + 159, + 2, // Opcode: SSUBWv8i8_v8i16 + /* 54413 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 54435 + /* 54418 */ MCD_OPC_CheckPredicate, + 21, + 184, + 195, + 0, // Skip to: 104527 + /* 54423 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 177, + 195, + 0, // Skip to: 104527 + /* 54430 */ MCD_OPC_Decode, + 156, + 10, + 155, + 2, // Opcode: CMGTv8i8 + /* 54435 */ MCD_OPC_FilterValue, + 14, + 56, + 0, + 0, // Skip to: 54496 + /* 54440 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54443 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54458 + /* 54448 */ MCD_OPC_CheckPredicate, + 21, + 154, + 195, + 0, // Skip to: 104527 + /* 54453 */ MCD_OPC_Decode, + 134, + 48, + 155, + 2, // Opcode: ZIP1v8i8 + /* 54458 */ MCD_OPC_FilterValue, + 1, + 144, + 195, + 0, // Skip to: 104527 + /* 54463 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 54466 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54481 + /* 54471 */ MCD_OPC_CheckPredicate, + 21, + 131, + 195, + 0, // Skip to: 104527 + /* 54476 */ MCD_OPC_Decode, + 251, + 40, + 166, + 2, // Opcode: SUQADDv8i8 + /* 54481 */ MCD_OPC_FilterValue, + 16, + 121, + 195, + 0, // Skip to: 104527 + /* 54486 */ MCD_OPC_CheckPredicate, + 21, + 116, + 195, + 0, // Skip to: 104527 + /* 54491 */ MCD_OPC_Decode, + 162, + 30, + 167, + 2, // Opcode: SADDLVv8i8v + /* 54496 */ MCD_OPC_FilterValue, + 15, + 138, + 0, + 0, // Skip to: 54639 + /* 54501 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54504 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 54624 + /* 54509 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 54512 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 54592 + /* 54517 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 54520 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 54560 + /* 54525 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 54528 */ MCD_OPC_FilterValue, + 1, + 74, + 195, + 0, // Skip to: 104527 + /* 54533 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 54550 + /* 54538 */ MCD_OPC_CheckField, + 19, + 2, + 0, + 5, + 0, + 0, // Skip to: 54550 + /* 54545 */ MCD_OPC_Decode, + 250, + 43, + 162, + 2, // Opcode: UMOVvi32_idx0 + /* 54550 */ MCD_OPC_CheckPredicate, + 21, + 52, + 195, + 0, // Skip to: 104527 + /* 54555 */ MCD_OPC_Decode, + 249, + 43, + 168, + 2, // Opcode: UMOVvi32 + /* 54560 */ MCD_OPC_FilterValue, + 1, + 42, + 195, + 0, // Skip to: 104527 + /* 54565 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 54582 + /* 54570 */ MCD_OPC_CheckField, + 18, + 3, + 0, + 5, + 0, + 0, // Skip to: 54582 + /* 54577 */ MCD_OPC_Decode, + 248, + 43, + 162, + 2, // Opcode: UMOVvi16_idx0 + /* 54582 */ MCD_OPC_CheckPredicate, + 21, + 20, + 195, + 0, // Skip to: 104527 + /* 54587 */ MCD_OPC_Decode, + 247, + 43, + 163, + 2, // Opcode: UMOVvi16 + /* 54592 */ MCD_OPC_FilterValue, + 1, + 10, + 195, + 0, // Skip to: 104527 + /* 54597 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 54614 + /* 54602 */ MCD_OPC_CheckField, + 17, + 4, + 0, + 5, + 0, + 0, // Skip to: 54614 + /* 54609 */ MCD_OPC_Decode, + 254, + 43, + 162, + 2, // Opcode: UMOVvi8_idx0 + /* 54614 */ MCD_OPC_CheckPredicate, + 21, + 244, + 194, + 0, // Skip to: 104527 + /* 54619 */ MCD_OPC_Decode, + 253, + 43, + 164, + 2, // Opcode: UMOVvi8 + /* 54624 */ MCD_OPC_FilterValue, + 1, + 234, + 194, + 0, // Skip to: 104527 + /* 54629 */ MCD_OPC_CheckPredicate, + 21, + 229, + 194, + 0, // Skip to: 104527 + /* 54634 */ MCD_OPC_Decode, + 140, + 10, + 155, + 2, // Opcode: CMGEv8i8 + /* 54639 */ MCD_OPC_FilterValue, + 16, + 33, + 0, + 0, // Skip to: 54677 + /* 54644 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54647 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54662 + /* 54652 */ MCD_OPC_CheckPredicate, + 21, + 206, + 194, + 0, // Skip to: 104527 + /* 54657 */ MCD_OPC_Decode, + 163, + 41, + 169, + 2, // Opcode: TBLv8i8Three + /* 54662 */ MCD_OPC_FilterValue, + 1, + 196, + 194, + 0, // Skip to: 104527 + /* 54667 */ MCD_OPC_CheckPredicate, + 21, + 191, + 194, + 0, // Skip to: 104527 + /* 54672 */ MCD_OPC_Decode, + 162, + 7, + 170, + 2, // Opcode: ADDHNv8i16_v8i8 + /* 54677 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 54699 + /* 54682 */ MCD_OPC_CheckPredicate, + 21, + 176, + 194, + 0, // Skip to: 104527 + /* 54687 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 169, + 194, + 0, // Skip to: 104527 + /* 54694 */ MCD_OPC_Decode, + 130, + 37, + 155, + 2, // Opcode: SSHLv8i8 + /* 54699 */ MCD_OPC_FilterValue, + 18, + 33, + 0, + 0, // Skip to: 54737 + /* 54704 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 54707 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 54722 + /* 54712 */ MCD_OPC_CheckPredicate, + 21, + 146, + 194, + 0, // Skip to: 104527 + /* 54717 */ MCD_OPC_Decode, + 225, + 9, + 156, + 2, // Opcode: CLSv8i8 + /* 54722 */ MCD_OPC_FilterValue, + 33, + 136, + 194, + 0, // Skip to: 104527 + /* 54727 */ MCD_OPC_CheckPredicate, + 21, + 131, + 194, + 0, // Skip to: 104527 + /* 54732 */ MCD_OPC_Decode, + 161, + 36, + 161, + 2, // Opcode: SQXTNv8i8 + /* 54737 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 54759 + /* 54742 */ MCD_OPC_CheckPredicate, + 21, + 116, + 194, + 0, // Skip to: 104527 + /* 54747 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 109, + 194, + 0, // Skip to: 104527 + /* 54754 */ MCD_OPC_Decode, + 216, + 35, + 155, + 2, // Opcode: SQSHLv8i8 + /* 54759 */ MCD_OPC_FilterValue, + 20, + 33, + 0, + 0, // Skip to: 54797 + /* 54764 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54767 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54782 + /* 54772 */ MCD_OPC_CheckPredicate, + 21, + 86, + 194, + 0, // Skip to: 104527 + /* 54777 */ MCD_OPC_Decode, + 177, + 41, + 171, + 2, // Opcode: TBXv8i8Three + /* 54782 */ MCD_OPC_FilterValue, + 1, + 76, + 194, + 0, // Skip to: 104527 + /* 54787 */ MCD_OPC_CheckPredicate, + 21, + 71, + 194, + 0, // Skip to: 104527 + /* 54792 */ MCD_OPC_Decode, + 229, + 29, + 172, + 2, // Opcode: SABALv8i8_v8i16 + /* 54797 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 54819 + /* 54802 */ MCD_OPC_CheckPredicate, + 21, + 56, + 194, + 0, // Skip to: 104527 + /* 54807 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 49, + 194, + 0, // Skip to: 104527 + /* 54814 */ MCD_OPC_Decode, + 214, + 36, + 155, + 2, // Opcode: SRSHLv8i8 + /* 54819 */ MCD_OPC_FilterValue, + 22, + 40, + 0, + 0, // Skip to: 54864 + /* 54824 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54827 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54842 + /* 54832 */ MCD_OPC_CheckPredicate, + 21, + 26, + 194, + 0, // Skip to: 104527 + /* 54837 */ MCD_OPC_Decode, + 155, + 47, + 155, + 2, // Opcode: UZP2v8i8 + /* 54842 */ MCD_OPC_FilterValue, + 1, + 16, + 194, + 0, // Skip to: 104527 + /* 54847 */ MCD_OPC_CheckPredicate, + 21, + 11, + 194, + 0, // Skip to: 104527 + /* 54852 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 4, + 194, + 0, // Skip to: 104527 + /* 54859 */ MCD_OPC_Decode, + 187, + 11, + 156, + 2, // Opcode: CNTv8i8 + /* 54864 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 54886 + /* 54869 */ MCD_OPC_CheckPredicate, + 21, + 245, + 193, + 0, // Skip to: 104527 + /* 54874 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 238, + 193, + 0, // Skip to: 104527 + /* 54881 */ MCD_OPC_Decode, + 138, + 35, + 155, + 2, // Opcode: SQRSHLv8i8 + /* 54886 */ MCD_OPC_FilterValue, + 24, + 33, + 0, + 0, // Skip to: 54924 + /* 54891 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54894 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54909 + /* 54899 */ MCD_OPC_CheckPredicate, + 21, + 215, + 193, + 0, // Skip to: 104527 + /* 54904 */ MCD_OPC_Decode, + 161, + 41, + 173, + 2, // Opcode: TBLv8i8Four + /* 54909 */ MCD_OPC_FilterValue, + 1, + 205, + 193, + 0, // Skip to: 104527 + /* 54914 */ MCD_OPC_CheckPredicate, + 21, + 200, + 193, + 0, // Skip to: 104527 + /* 54919 */ MCD_OPC_Decode, + 179, + 40, + 170, + 2, // Opcode: SUBHNv8i16_v8i8 + /* 54924 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 54946 + /* 54929 */ MCD_OPC_CheckPredicate, + 21, + 185, + 193, + 0, // Skip to: 104527 + /* 54934 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 178, + 193, + 0, // Skip to: 104527 + /* 54941 */ MCD_OPC_Decode, + 248, + 31, + 155, + 2, // Opcode: SMAXv8i8 + /* 54946 */ MCD_OPC_FilterValue, + 26, + 56, + 0, + 0, // Skip to: 55007 + /* 54951 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 54954 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54969 + /* 54959 */ MCD_OPC_CheckPredicate, + 21, + 155, + 193, + 0, // Skip to: 104527 + /* 54964 */ MCD_OPC_Decode, + 214, + 41, + 155, + 2, // Opcode: TRN2v8i8 + /* 54969 */ MCD_OPC_FilterValue, + 1, + 145, + 193, + 0, // Skip to: 104527 + /* 54974 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 54977 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 54992 + /* 54982 */ MCD_OPC_CheckPredicate, + 21, + 132, + 193, + 0, // Skip to: 104527 + /* 54987 */ MCD_OPC_Decode, + 142, + 30, + 166, + 2, // Opcode: SADALPv8i8_v4i16 + /* 54992 */ MCD_OPC_FilterValue, + 1, + 122, + 193, + 0, // Skip to: 104527 + /* 54997 */ MCD_OPC_CheckPredicate, + 21, + 117, + 193, + 0, // Skip to: 104527 + /* 55002 */ MCD_OPC_Decode, + 133, + 15, + 161, + 2, // Opcode: FCVTNv4i16 + /* 55007 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 55029 + /* 55012 */ MCD_OPC_CheckPredicate, + 21, + 102, + 193, + 0, // Skip to: 104527 + /* 55017 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 95, + 193, + 0, // Skip to: 104527 + /* 55024 */ MCD_OPC_Decode, + 154, + 32, + 155, + 2, // Opcode: SMINv8i8 + /* 55029 */ MCD_OPC_FilterValue, + 28, + 33, + 0, + 0, // Skip to: 55067 + /* 55034 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 55037 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 55052 + /* 55042 */ MCD_OPC_CheckPredicate, + 21, + 72, + 193, + 0, // Skip to: 104527 + /* 55047 */ MCD_OPC_Decode, + 175, + 41, + 174, + 2, // Opcode: TBXv8i8Four + /* 55052 */ MCD_OPC_FilterValue, + 1, + 62, + 193, + 0, // Skip to: 104527 + /* 55057 */ MCD_OPC_CheckPredicate, + 21, + 57, + 193, + 0, // Skip to: 104527 + /* 55062 */ MCD_OPC_Decode, + 251, + 29, + 151, + 2, // Opcode: SABDLv8i8_v8i16 + /* 55067 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 55089 + /* 55072 */ MCD_OPC_CheckPredicate, + 21, + 42, + 193, + 0, // Skip to: 104527 + /* 55077 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 35, + 193, + 0, // Skip to: 104527 + /* 55084 */ MCD_OPC_Decode, + 133, + 30, + 155, + 2, // Opcode: SABDv8i8 + /* 55089 */ MCD_OPC_FilterValue, + 30, + 56, + 0, + 0, // Skip to: 55150 + /* 55094 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 55097 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 55112 + /* 55102 */ MCD_OPC_CheckPredicate, + 21, + 12, + 193, + 0, // Skip to: 104527 + /* 55107 */ MCD_OPC_Decode, + 150, + 48, + 155, + 2, // Opcode: ZIP2v8i8 + /* 55112 */ MCD_OPC_FilterValue, + 1, + 2, + 193, + 0, // Skip to: 104527 + /* 55117 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 55120 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 55135 + /* 55125 */ MCD_OPC_CheckPredicate, + 21, + 245, + 192, + 0, // Skip to: 104527 + /* 55130 */ MCD_OPC_Decode, + 135, + 33, + 156, + 2, // Opcode: SQABSv8i8 + /* 55135 */ MCD_OPC_FilterValue, + 1, + 235, + 192, + 0, // Skip to: 104527 + /* 55140 */ MCD_OPC_CheckPredicate, + 21, + 230, + 192, + 0, // Skip to: 104527 + /* 55145 */ MCD_OPC_Decode, + 199, + 14, + 175, + 2, // Opcode: FCVTLv4i16 + /* 55150 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 55172 + /* 55155 */ MCD_OPC_CheckPredicate, + 21, + 215, + 192, + 0, // Skip to: 104527 + /* 55160 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 208, + 192, + 0, // Skip to: 104527 + /* 55167 */ MCD_OPC_Decode, + 239, + 29, + 176, + 2, // Opcode: SABAv8i8 + /* 55172 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 55194 + /* 55177 */ MCD_OPC_CheckPredicate, + 21, + 193, + 192, + 0, // Skip to: 104527 + /* 55182 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 186, + 192, + 0, // Skip to: 104527 + /* 55189 */ MCD_OPC_Decode, + 174, + 32, + 172, + 2, // Opcode: SMLALv8i8_v8i16 + /* 55194 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 55216 + /* 55199 */ MCD_OPC_CheckPredicate, + 21, + 171, + 192, + 0, // Skip to: 104527 + /* 55204 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 164, + 192, + 0, // Skip to: 104527 + /* 55211 */ MCD_OPC_Decode, + 217, + 7, + 155, + 2, // Opcode: ADDv8i8 + /* 55216 */ MCD_OPC_FilterValue, + 34, + 33, + 0, + 0, // Skip to: 55254 + /* 55221 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 55224 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 55239 + /* 55229 */ MCD_OPC_CheckPredicate, + 21, + 141, + 192, + 0, // Skip to: 104527 + /* 55234 */ MCD_OPC_Decode, + 157, + 10, + 156, + 2, // Opcode: CMGTv8i8rz + /* 55239 */ MCD_OPC_FilterValue, + 33, + 131, + 192, + 0, // Skip to: 104527 + /* 55244 */ MCD_OPC_CheckPredicate, + 21, + 126, + 192, + 0, // Skip to: 104527 + /* 55249 */ MCD_OPC_Decode, + 150, + 19, + 156, + 2, // Opcode: FRINTNv2f32 + /* 55254 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 55276 + /* 55259 */ MCD_OPC_CheckPredicate, + 21, + 111, + 192, + 0, // Skip to: 104527 + /* 55264 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 104, + 192, + 0, // Skip to: 104527 + /* 55271 */ MCD_OPC_Decode, + 169, + 11, + 155, + 2, // Opcode: CMTSTv8i8 + /* 55276 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 55298 + /* 55281 */ MCD_OPC_CheckPredicate, + 21, + 89, + 192, + 0, // Skip to: 104527 + /* 55286 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 82, + 192, + 0, // Skip to: 104527 + /* 55293 */ MCD_OPC_Decode, + 158, + 27, + 176, + 2, // Opcode: MLAv8i8 + /* 55298 */ MCD_OPC_FilterValue, + 38, + 33, + 0, + 0, // Skip to: 55336 + /* 55303 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 55306 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 55321 + /* 55311 */ MCD_OPC_CheckPredicate, + 21, + 59, + 192, + 0, // Skip to: 104527 + /* 55316 */ MCD_OPC_Decode, + 253, + 9, + 156, + 2, // Opcode: CMEQv8i8rz + /* 55321 */ MCD_OPC_FilterValue, + 33, + 49, + 192, + 0, // Skip to: 104527 + /* 55326 */ MCD_OPC_CheckPredicate, + 21, + 44, + 192, + 0, // Skip to: 104527 + /* 55331 */ MCD_OPC_Decode, + 139, + 19, + 156, + 2, // Opcode: FRINTMv2f32 + /* 55336 */ MCD_OPC_FilterValue, + 39, + 17, + 0, + 0, // Skip to: 55358 + /* 55341 */ MCD_OPC_CheckPredicate, + 21, + 29, + 192, + 0, // Skip to: 104527 + /* 55346 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 22, + 192, + 0, // Skip to: 104527 + /* 55353 */ MCD_OPC_Decode, + 236, + 27, + 155, + 2, // Opcode: MULv8i8 + /* 55358 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 55380 + /* 55363 */ MCD_OPC_CheckPredicate, + 21, + 7, + 192, + 0, // Skip to: 104527 + /* 55368 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 0, + 192, + 0, // Skip to: 104527 + /* 55375 */ MCD_OPC_Decode, + 194, + 32, + 172, + 2, // Opcode: SMLSLv8i8_v8i16 + /* 55380 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 55402 + /* 55385 */ MCD_OPC_CheckPredicate, + 21, + 241, + 191, + 0, // Skip to: 104527 + /* 55390 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 234, + 191, + 0, // Skip to: 104527 + /* 55397 */ MCD_OPC_Decode, + 225, + 31, + 155, + 2, // Opcode: SMAXPv8i8 + /* 55402 */ MCD_OPC_FilterValue, + 42, + 63, + 0, + 0, // Skip to: 55470 + /* 55407 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 55410 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 55425 + /* 55415 */ MCD_OPC_CheckPredicate, + 21, + 211, + 191, + 0, // Skip to: 104527 + /* 55420 */ MCD_OPC_Decode, + 195, + 10, + 156, + 2, // Opcode: CMLTv8i8rz + /* 55425 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 55440 + /* 55430 */ MCD_OPC_CheckPredicate, + 21, + 196, + 191, + 0, // Skip to: 104527 + /* 55435 */ MCD_OPC_Decode, + 239, + 14, + 156, + 2, // Opcode: FCVTNSv2f32 + /* 55440 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 55455 + /* 55445 */ MCD_OPC_CheckPredicate, + 21, + 181, + 191, + 0, // Skip to: 104527 + /* 55450 */ MCD_OPC_Decode, + 234, + 31, + 177, + 2, // Opcode: SMAXVv8i8v + /* 55455 */ MCD_OPC_FilterValue, + 49, + 171, + 191, + 0, // Skip to: 104527 + /* 55460 */ MCD_OPC_CheckPredicate, + 21, + 166, + 191, + 0, // Skip to: 104527 + /* 55465 */ MCD_OPC_Decode, + 140, + 32, + 177, + 2, // Opcode: SMINVv8i8v + /* 55470 */ MCD_OPC_FilterValue, + 43, + 17, + 0, + 0, // Skip to: 55492 + /* 55475 */ MCD_OPC_CheckPredicate, + 21, + 151, + 191, + 0, // Skip to: 104527 + /* 55480 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 144, + 191, + 0, // Skip to: 104527 + /* 55487 */ MCD_OPC_Decode, + 131, + 32, + 155, + 2, // Opcode: SMINPv8i8 + /* 55492 */ MCD_OPC_FilterValue, + 46, + 48, + 0, + 0, // Skip to: 55545 + /* 55497 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 55500 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 55515 + /* 55505 */ MCD_OPC_CheckPredicate, + 21, + 121, + 191, + 0, // Skip to: 104527 + /* 55510 */ MCD_OPC_Decode, + 139, + 7, + 156, + 2, // Opcode: ABSv8i8 + /* 55515 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 55530 + /* 55520 */ MCD_OPC_CheckPredicate, + 21, + 106, + 191, + 0, // Skip to: 104527 + /* 55525 */ MCD_OPC_Decode, + 211, + 14, + 156, + 2, // Opcode: FCVTMSv2f32 + /* 55530 */ MCD_OPC_FilterValue, + 49, + 96, + 191, + 0, // Skip to: 104527 + /* 55535 */ MCD_OPC_CheckPredicate, + 21, + 91, + 191, + 0, // Skip to: 104527 + /* 55540 */ MCD_OPC_Decode, + 190, + 7, + 177, + 2, // Opcode: ADDVv8i8v + /* 55545 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 55567 + /* 55550 */ MCD_OPC_CheckPredicate, + 21, + 76, + 191, + 0, // Skip to: 104527 + /* 55555 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 69, + 191, + 0, // Skip to: 104527 + /* 55562 */ MCD_OPC_Decode, + 175, + 7, + 155, + 2, // Opcode: ADDPv8i8 + /* 55567 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 55589 + /* 55572 */ MCD_OPC_CheckPredicate, + 21, + 54, + 191, + 0, // Skip to: 104527 + /* 55577 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 47, + 191, + 0, // Skip to: 104527 + /* 55584 */ MCD_OPC_Decode, + 240, + 32, + 151, + 2, // Opcode: SMULLv8i8_v8i16 + /* 55589 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 55611 + /* 55594 */ MCD_OPC_CheckPredicate, + 21, + 32, + 191, + 0, // Skip to: 104527 + /* 55599 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 25, + 191, + 0, // Skip to: 104527 + /* 55606 */ MCD_OPC_Decode, + 177, + 16, + 155, + 2, // Opcode: FMAXNMv2f32 + /* 55611 */ MCD_OPC_FilterValue, + 50, + 33, + 0, + 0, // Skip to: 55649 + /* 55616 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 55619 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 55634 + /* 55624 */ MCD_OPC_CheckPredicate, + 21, + 2, + 191, + 0, // Skip to: 104527 + /* 55629 */ MCD_OPC_Decode, + 173, + 14, + 156, + 2, // Opcode: FCVTASv2f32 + /* 55634 */ MCD_OPC_FilterValue, + 48, + 248, + 190, + 0, // Skip to: 104527 + /* 55639 */ MCD_OPC_CheckPredicate, + 23, + 243, + 190, + 0, // Skip to: 104527 + /* 55644 */ MCD_OPC_Decode, + 168, + 16, + 167, + 2, // Opcode: FMAXNMVv4i16v + /* 55649 */ MCD_OPC_FilterValue, + 51, + 17, + 0, + 0, // Skip to: 55671 + /* 55654 */ MCD_OPC_CheckPredicate, + 21, + 228, + 190, + 0, // Skip to: 104527 + /* 55659 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 221, + 190, + 0, // Skip to: 104527 + /* 55666 */ MCD_OPC_Decode, + 166, + 17, + 176, + 2, // Opcode: FMLAv2f32 + /* 55671 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 55693 + /* 55676 */ MCD_OPC_CheckPredicate, + 21, + 206, + 190, + 0, // Skip to: 104527 + /* 55681 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 199, + 190, + 0, // Skip to: 104527 + /* 55688 */ MCD_OPC_Decode, + 145, + 13, + 155, + 2, // Opcode: FADDv2f32 + /* 55693 */ MCD_OPC_FilterValue, + 54, + 17, + 0, + 0, // Skip to: 55715 + /* 55698 */ MCD_OPC_CheckPredicate, + 21, + 184, + 190, + 0, // Skip to: 104527 + /* 55703 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 177, + 190, + 0, // Skip to: 104527 + /* 55710 */ MCD_OPC_Decode, + 224, + 30, + 156, + 2, // Opcode: SCVTFv2f32 + /* 55715 */ MCD_OPC_FilterValue, + 55, + 17, + 0, + 0, // Skip to: 55737 + /* 55720 */ MCD_OPC_CheckPredicate, + 21, + 162, + 190, + 0, // Skip to: 104527 + /* 55725 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 155, + 190, + 0, // Skip to: 104527 + /* 55732 */ MCD_OPC_Decode, + 252, + 17, + 155, + 2, // Opcode: FMULXv2f32 + /* 55737 */ MCD_OPC_FilterValue, + 56, + 17, + 0, + 0, // Skip to: 55759 + /* 55742 */ MCD_OPC_CheckPredicate, + 21, + 140, + 190, + 0, // Skip to: 104527 + /* 55747 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 133, + 190, + 0, // Skip to: 104527 + /* 55754 */ MCD_OPC_Decode, + 194, + 28, + 151, + 2, // Opcode: PMULLv8i8 + /* 55759 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 55781 + /* 55764 */ MCD_OPC_CheckPredicate, + 21, + 118, + 190, + 0, // Skip to: 104527 + /* 55769 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 111, + 190, + 0, // Skip to: 104527 + /* 55776 */ MCD_OPC_Decode, + 176, + 13, + 155, + 2, // Opcode: FCMEQv2f32 + /* 55781 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 55803 + /* 55786 */ MCD_OPC_CheckPredicate, + 24, + 96, + 190, + 0, // Skip to: 104527 + /* 55791 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 89, + 190, + 0, // Skip to: 104527 + /* 55798 */ MCD_OPC_Decode, + 226, + 18, + 156, + 2, // Opcode: FRINT32Zv2f32 + /* 55803 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 55825 + /* 55808 */ MCD_OPC_CheckPredicate, + 25, + 74, + 190, + 0, // Skip to: 104527 + /* 55813 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 67, + 190, + 0, // Skip to: 104527 + /* 55820 */ MCD_OPC_Decode, + 155, + 17, + 176, + 2, // Opcode: FMLALv4f16 + /* 55825 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 55847 + /* 55830 */ MCD_OPC_CheckPredicate, + 21, + 52, + 190, + 0, // Skip to: 104527 + /* 55835 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 45, + 190, + 0, // Skip to: 104527 + /* 55842 */ MCD_OPC_Decode, + 206, + 16, + 155, + 2, // Opcode: FMAXv2f32 + /* 55847 */ MCD_OPC_FilterValue, + 62, + 33, + 0, + 0, // Skip to: 55885 + /* 55852 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 55855 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 55870 + /* 55860 */ MCD_OPC_CheckPredicate, + 24, + 22, + 190, + 0, // Skip to: 104527 + /* 55865 */ MCD_OPC_Decode, + 236, + 18, + 156, + 2, // Opcode: FRINT64Zv2f32 + /* 55870 */ MCD_OPC_FilterValue, + 48, + 12, + 190, + 0, // Skip to: 104527 + /* 55875 */ MCD_OPC_CheckPredicate, + 23, + 7, + 190, + 0, // Skip to: 104527 + /* 55880 */ MCD_OPC_Decode, + 197, + 16, + 167, + 2, // Opcode: FMAXVv4i16v + /* 55885 */ MCD_OPC_FilterValue, + 63, + 253, + 189, + 0, // Skip to: 104527 + /* 55890 */ MCD_OPC_CheckPredicate, + 21, + 248, + 189, + 0, // Skip to: 104527 + /* 55895 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 241, + 189, + 0, // Skip to: 104527 + /* 55902 */ MCD_OPC_Decode, + 208, + 18, + 155, + 2, // Opcode: FRECPSv2f32 + /* 55907 */ MCD_OPC_FilterValue, + 1, + 140, + 5, + 0, // Skip to: 57332 + /* 55912 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 55915 */ MCD_OPC_FilterValue, + 0, + 135, + 1, + 0, // Skip to: 56311 + /* 55920 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 55923 */ MCD_OPC_FilterValue, + 0, + 199, + 0, + 0, // Skip to: 56127 + /* 55928 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 55931 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 55946 + /* 55936 */ MCD_OPC_CheckPredicate, + 21, + 202, + 189, + 0, // Skip to: 104527 + /* 55941 */ MCD_OPC_Decode, + 199, + 12, + 178, + 2, // Opcode: EXTv8i8 + /* 55946 */ MCD_OPC_FilterValue, + 1, + 192, + 189, + 0, // Skip to: 104527 + /* 55951 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 55954 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 55969 + /* 55959 */ MCD_OPC_CheckPredicate, + 21, + 179, + 189, + 0, // Skip to: 104527 + /* 55964 */ MCD_OPC_Decode, + 165, + 42, + 151, + 2, // Opcode: UADDLv8i8_v8i16 + /* 55969 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 55991 + /* 55974 */ MCD_OPC_CheckPredicate, + 21, + 164, + 189, + 0, // Skip to: 104527 + /* 55979 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 157, + 189, + 0, // Skip to: 104527 + /* 55986 */ MCD_OPC_Decode, + 167, + 29, + 156, + 2, // Opcode: REV32v8i8 + /* 55991 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 56006 + /* 55996 */ MCD_OPC_CheckPredicate, + 21, + 142, + 189, + 0, // Skip to: 104527 + /* 56001 */ MCD_OPC_Decode, + 181, + 42, + 159, + 2, // Opcode: UADDWv8i8_v8i16 + /* 56006 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 56021 + /* 56011 */ MCD_OPC_CheckPredicate, + 21, + 127, + 189, + 0, // Skip to: 104527 + /* 56016 */ MCD_OPC_Decode, + 227, + 46, + 151, + 2, // Opcode: USUBLv8i8_v8i16 + /* 56021 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 56059 + /* 56026 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 56029 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 56044 + /* 56034 */ MCD_OPC_CheckPredicate, + 21, + 104, + 189, + 0, // Skip to: 104527 + /* 56039 */ MCD_OPC_Decode, + 151, + 42, + 156, + 2, // Opcode: UADDLPv8i8_v4i16 + /* 56044 */ MCD_OPC_FilterValue, + 1, + 94, + 189, + 0, // Skip to: 104527 + /* 56049 */ MCD_OPC_CheckPredicate, + 21, + 89, + 189, + 0, // Skip to: 104527 + /* 56054 */ MCD_OPC_Decode, + 176, + 36, + 161, + 2, // Opcode: SQXTUNv8i8 + /* 56059 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 56074 + /* 56064 */ MCD_OPC_CheckPredicate, + 21, + 74, + 189, + 0, // Skip to: 104527 + /* 56069 */ MCD_OPC_Decode, + 239, + 46, + 159, + 2, // Opcode: USUBWv8i8_v8i16 + /* 56074 */ MCD_OPC_FilterValue, + 7, + 64, + 189, + 0, // Skip to: 104527 + /* 56079 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 56082 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 56097 + /* 56087 */ MCD_OPC_CheckPredicate, + 21, + 51, + 189, + 0, // Skip to: 104527 + /* 56092 */ MCD_OPC_Decode, + 203, + 46, + 166, + 2, // Opcode: USQADDv8i8 + /* 56097 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 56112 + /* 56102 */ MCD_OPC_CheckPredicate, + 21, + 36, + 189, + 0, // Skip to: 104527 + /* 56107 */ MCD_OPC_Decode, + 157, + 31, + 175, + 2, // Opcode: SHLLv8i8 + /* 56112 */ MCD_OPC_FilterValue, + 16, + 26, + 189, + 0, // Skip to: 104527 + /* 56117 */ MCD_OPC_CheckPredicate, + 21, + 21, + 189, + 0, // Skip to: 104527 + /* 56122 */ MCD_OPC_Decode, + 159, + 42, + 167, + 2, // Opcode: UADDLVv8i8v + /* 56127 */ MCD_OPC_FilterValue, + 1, + 11, + 189, + 0, // Skip to: 104527 + /* 56132 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 56135 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 56157 + /* 56140 */ MCD_OPC_CheckPredicate, + 21, + 254, + 188, + 0, // Skip to: 104527 + /* 56145 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 247, + 188, + 0, // Skip to: 104527 + /* 56152 */ MCD_OPC_Decode, + 247, + 42, + 155, + 2, // Opcode: UHADDv8i8 + /* 56157 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 56179 + /* 56162 */ MCD_OPC_CheckPredicate, + 21, + 232, + 188, + 0, // Skip to: 104527 + /* 56167 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 225, + 188, + 0, // Skip to: 104527 + /* 56174 */ MCD_OPC_Decode, + 179, + 44, + 155, + 2, // Opcode: UQADDv8i8 + /* 56179 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 56201 + /* 56184 */ MCD_OPC_CheckPredicate, + 21, + 210, + 188, + 0, // Skip to: 104527 + /* 56189 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 203, + 188, + 0, // Skip to: 104527 + /* 56196 */ MCD_OPC_Decode, + 233, + 45, + 155, + 2, // Opcode: URHADDv8i8 + /* 56201 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 56223 + /* 56206 */ MCD_OPC_CheckPredicate, + 21, + 188, + 188, + 0, // Skip to: 104527 + /* 56211 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 181, + 188, + 0, // Skip to: 104527 + /* 56218 */ MCD_OPC_Decode, + 180, + 12, + 155, + 2, // Opcode: EORv8i8 + /* 56223 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 56245 + /* 56228 */ MCD_OPC_CheckPredicate, + 21, + 166, + 188, + 0, // Skip to: 104527 + /* 56233 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 159, + 188, + 0, // Skip to: 104527 + /* 56240 */ MCD_OPC_Decode, + 133, + 43, + 155, + 2, // Opcode: UHSUBv8i8 + /* 56245 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 56267 + /* 56250 */ MCD_OPC_CheckPredicate, + 21, + 144, + 188, + 0, // Skip to: 104527 + /* 56255 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 137, + 188, + 0, // Skip to: 104527 + /* 56262 */ MCD_OPC_Decode, + 205, + 45, + 155, + 2, // Opcode: UQSUBv8i8 + /* 56267 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 56289 + /* 56272 */ MCD_OPC_CheckPredicate, + 21, + 122, + 188, + 0, // Skip to: 104527 + /* 56277 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 115, + 188, + 0, // Skip to: 104527 + /* 56284 */ MCD_OPC_Decode, + 165, + 10, + 155, + 2, // Opcode: CMHIv8i8 + /* 56289 */ MCD_OPC_FilterValue, + 7, + 105, + 188, + 0, // Skip to: 104527 + /* 56294 */ MCD_OPC_CheckPredicate, + 21, + 100, + 188, + 0, // Skip to: 104527 + /* 56299 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 93, + 188, + 0, // Skip to: 104527 + /* 56306 */ MCD_OPC_Decode, + 173, + 10, + 155, + 2, // Opcode: CMHSv8i8 + /* 56311 */ MCD_OPC_FilterValue, + 1, + 115, + 1, + 0, // Skip to: 56687 + /* 56316 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 56319 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 56341 + /* 56324 */ MCD_OPC_CheckPredicate, + 21, + 70, + 188, + 0, // Skip to: 104527 + /* 56329 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 63, + 188, + 0, // Skip to: 104527 + /* 56336 */ MCD_OPC_Decode, + 141, + 29, + 170, + 2, // Opcode: RADDHNv8i16_v8i8 + /* 56341 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 56363 + /* 56346 */ MCD_OPC_CheckPredicate, + 21, + 48, + 188, + 0, // Skip to: 104527 + /* 56351 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 41, + 188, + 0, // Skip to: 104527 + /* 56358 */ MCD_OPC_Decode, + 174, + 46, + 155, + 2, // Opcode: USHLv8i8 + /* 56363 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 56401 + /* 56368 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 56371 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 56386 + /* 56376 */ MCD_OPC_CheckPredicate, + 21, + 18, + 188, + 0, // Skip to: 104527 + /* 56381 */ MCD_OPC_Decode, + 237, + 9, + 156, + 2, // Opcode: CLZv8i8 + /* 56386 */ MCD_OPC_FilterValue, + 33, + 8, + 188, + 0, // Skip to: 104527 + /* 56391 */ MCD_OPC_CheckPredicate, + 21, + 3, + 188, + 0, // Skip to: 104527 + /* 56396 */ MCD_OPC_Decode, + 220, + 45, + 161, + 2, // Opcode: UQXTNv8i8 + /* 56401 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 56423 + /* 56406 */ MCD_OPC_CheckPredicate, + 21, + 244, + 187, + 0, // Skip to: 104527 + /* 56411 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 237, + 187, + 0, // Skip to: 104527 + /* 56418 */ MCD_OPC_Decode, + 162, + 45, + 155, + 2, // Opcode: UQSHLv8i8 + /* 56423 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 56445 + /* 56428 */ MCD_OPC_CheckPredicate, + 21, + 222, + 187, + 0, // Skip to: 104527 + /* 56433 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 215, + 187, + 0, // Skip to: 104527 + /* 56440 */ MCD_OPC_Decode, + 229, + 41, + 172, + 2, // Opcode: UABALv8i8_v8i16 + /* 56445 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 56467 + /* 56450 */ MCD_OPC_CheckPredicate, + 21, + 200, + 187, + 0, // Skip to: 104527 + /* 56455 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 193, + 187, + 0, // Skip to: 104527 + /* 56462 */ MCD_OPC_Decode, + 249, + 45, + 155, + 2, // Opcode: URSHLv8i8 + /* 56467 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 56489 + /* 56472 */ MCD_OPC_CheckPredicate, + 21, + 178, + 187, + 0, // Skip to: 104527 + /* 56477 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 171, + 187, + 0, // Skip to: 104527 + /* 56484 */ MCD_OPC_Decode, + 139, + 28, + 156, + 2, // Opcode: NOTv8i8 + /* 56489 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 56511 + /* 56494 */ MCD_OPC_CheckPredicate, + 21, + 156, + 187, + 0, // Skip to: 104527 + /* 56499 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 149, + 187, + 0, // Skip to: 104527 + /* 56506 */ MCD_OPC_Decode, + 242, + 44, + 155, + 2, // Opcode: UQRSHLv8i8 + /* 56511 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 56533 + /* 56516 */ MCD_OPC_CheckPredicate, + 21, + 134, + 187, + 0, // Skip to: 104527 + /* 56521 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 127, + 187, + 0, // Skip to: 104527 + /* 56528 */ MCD_OPC_Decode, + 217, + 29, + 170, + 2, // Opcode: RSUBHNv8i16_v8i8 + /* 56533 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 56555 + /* 56538 */ MCD_OPC_CheckPredicate, + 21, + 112, + 187, + 0, // Skip to: 104527 + /* 56543 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 105, + 187, + 0, // Skip to: 104527 + /* 56550 */ MCD_OPC_Decode, + 167, + 43, + 155, + 2, // Opcode: UMAXv8i8 + /* 56555 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 56577 + /* 56560 */ MCD_OPC_CheckPredicate, + 21, + 90, + 187, + 0, // Skip to: 104527 + /* 56565 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 83, + 187, + 0, // Skip to: 104527 + /* 56572 */ MCD_OPC_Decode, + 142, + 42, + 166, + 2, // Opcode: UADALPv8i8_v4i16 + /* 56577 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 56599 + /* 56582 */ MCD_OPC_CheckPredicate, + 21, + 68, + 187, + 0, // Skip to: 104527 + /* 56587 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 61, + 187, + 0, // Skip to: 104527 + /* 56594 */ MCD_OPC_Decode, + 200, + 43, + 155, + 2, // Opcode: UMINv8i8 + /* 56599 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 56621 + /* 56604 */ MCD_OPC_CheckPredicate, + 21, + 46, + 187, + 0, // Skip to: 104527 + /* 56609 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 39, + 187, + 0, // Skip to: 104527 + /* 56616 */ MCD_OPC_Decode, + 251, + 41, + 151, + 2, // Opcode: UABDLv8i8_v8i16 + /* 56621 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 56643 + /* 56626 */ MCD_OPC_CheckPredicate, + 21, + 24, + 187, + 0, // Skip to: 104527 + /* 56631 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 17, + 187, + 0, // Skip to: 104527 + /* 56638 */ MCD_OPC_Decode, + 133, + 42, + 155, + 2, // Opcode: UABDv8i8 + /* 56643 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 56665 + /* 56648 */ MCD_OPC_CheckPredicate, + 21, + 2, + 187, + 0, // Skip to: 104527 + /* 56653 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 251, + 186, + 0, // Skip to: 104527 + /* 56660 */ MCD_OPC_Decode, + 184, + 34, + 156, + 2, // Opcode: SQNEGv8i8 + /* 56665 */ MCD_OPC_FilterValue, + 15, + 241, + 186, + 0, // Skip to: 104527 + /* 56670 */ MCD_OPC_CheckPredicate, + 21, + 236, + 186, + 0, // Skip to: 104527 + /* 56675 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 229, + 186, + 0, // Skip to: 104527 + /* 56682 */ MCD_OPC_Decode, + 239, + 41, + 176, + 2, // Opcode: UABAv8i8 + /* 56687 */ MCD_OPC_FilterValue, + 2, + 90, + 1, + 0, // Skip to: 57038 + /* 56692 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 56695 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 56717 + /* 56700 */ MCD_OPC_CheckPredicate, + 21, + 206, + 186, + 0, // Skip to: 104527 + /* 56705 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 199, + 186, + 0, // Skip to: 104527 + /* 56712 */ MCD_OPC_Decode, + 220, + 43, + 172, + 2, // Opcode: UMLALv8i8_v8i16 + /* 56717 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 56739 + /* 56722 */ MCD_OPC_CheckPredicate, + 21, + 184, + 186, + 0, // Skip to: 104527 + /* 56727 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 177, + 186, + 0, // Skip to: 104527 + /* 56734 */ MCD_OPC_Decode, + 223, + 40, + 155, + 2, // Opcode: SUBv8i8 + /* 56739 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 56777 + /* 56744 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 56747 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 56762 + /* 56752 */ MCD_OPC_CheckPredicate, + 21, + 154, + 186, + 0, // Skip to: 104527 + /* 56757 */ MCD_OPC_Decode, + 141, + 10, + 156, + 2, // Opcode: CMGEv8i8rz + /* 56762 */ MCD_OPC_FilterValue, + 33, + 144, + 186, + 0, // Skip to: 104527 + /* 56767 */ MCD_OPC_CheckPredicate, + 21, + 139, + 186, + 0, // Skip to: 104527 + /* 56772 */ MCD_OPC_Decode, + 245, + 18, + 156, + 2, // Opcode: FRINTAv2f32 + /* 56777 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 56799 + /* 56782 */ MCD_OPC_CheckPredicate, + 21, + 124, + 186, + 0, // Skip to: 104527 + /* 56787 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 117, + 186, + 0, // Skip to: 104527 + /* 56794 */ MCD_OPC_Decode, + 252, + 9, + 155, + 2, // Opcode: CMEQv8i8 + /* 56799 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 56821 + /* 56804 */ MCD_OPC_CheckPredicate, + 21, + 102, + 186, + 0, // Skip to: 104527 + /* 56809 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 95, + 186, + 0, // Skip to: 104527 + /* 56816 */ MCD_OPC_Decode, + 175, + 27, + 176, + 2, // Opcode: MLSv8i8 + /* 56821 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 56859 + /* 56826 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 56829 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 56844 + /* 56834 */ MCD_OPC_CheckPredicate, + 21, + 72, + 186, + 0, // Skip to: 104527 + /* 56839 */ MCD_OPC_Decode, + 187, + 10, + 156, + 2, // Opcode: CMLEv8i8rz + /* 56844 */ MCD_OPC_FilterValue, + 33, + 62, + 186, + 0, // Skip to: 104527 + /* 56849 */ MCD_OPC_CheckPredicate, + 21, + 57, + 186, + 0, // Skip to: 104527 + /* 56854 */ MCD_OPC_Decode, + 172, + 19, + 156, + 2, // Opcode: FRINTXv2f32 + /* 56859 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 56881 + /* 56864 */ MCD_OPC_CheckPredicate, + 21, + 42, + 186, + 0, // Skip to: 104527 + /* 56869 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 35, + 186, + 0, // Skip to: 104527 + /* 56876 */ MCD_OPC_Decode, + 197, + 28, + 155, + 2, // Opcode: PMULv8i8 + /* 56881 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 56903 + /* 56886 */ MCD_OPC_CheckPredicate, + 21, + 20, + 186, + 0, // Skip to: 104527 + /* 56891 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 13, + 186, + 0, // Skip to: 104527 + /* 56898 */ MCD_OPC_Decode, + 240, + 43, + 172, + 2, // Opcode: UMLSLv8i8_v8i16 + /* 56903 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 56925 + /* 56908 */ MCD_OPC_CheckPredicate, + 21, + 254, + 185, + 0, // Skip to: 104527 + /* 56913 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 247, + 185, + 0, // Skip to: 104527 + /* 56920 */ MCD_OPC_Decode, + 144, + 43, + 155, + 2, // Opcode: UMAXPv8i8 + /* 56925 */ MCD_OPC_FilterValue, + 10, + 48, + 0, + 0, // Skip to: 56978 + /* 56930 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 56933 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 56948 + /* 56938 */ MCD_OPC_CheckPredicate, + 21, + 224, + 185, + 0, // Skip to: 104527 + /* 56943 */ MCD_OPC_Decode, + 255, + 14, + 156, + 2, // Opcode: FCVTNUv2f32 + /* 56948 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 56963 + /* 56953 */ MCD_OPC_CheckPredicate, + 21, + 209, + 185, + 0, // Skip to: 104527 + /* 56958 */ MCD_OPC_Decode, + 153, + 43, + 177, + 2, // Opcode: UMAXVv8i8v + /* 56963 */ MCD_OPC_FilterValue, + 49, + 199, + 185, + 0, // Skip to: 104527 + /* 56968 */ MCD_OPC_CheckPredicate, + 21, + 194, + 185, + 0, // Skip to: 104527 + /* 56973 */ MCD_OPC_Decode, + 186, + 43, + 177, + 2, // Opcode: UMINVv8i8v + /* 56978 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 57000 + /* 56983 */ MCD_OPC_CheckPredicate, + 21, + 179, + 185, + 0, // Skip to: 104527 + /* 56988 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 172, + 185, + 0, // Skip to: 104527 + /* 56995 */ MCD_OPC_Decode, + 177, + 43, + 155, + 2, // Opcode: UMINPv8i8 + /* 57000 */ MCD_OPC_FilterValue, + 14, + 162, + 185, + 0, // Skip to: 104527 + /* 57005 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 57008 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 57023 + /* 57013 */ MCD_OPC_CheckPredicate, + 21, + 149, + 185, + 0, // Skip to: 104527 + /* 57018 */ MCD_OPC_Decode, + 129, + 28, + 156, + 2, // Opcode: NEGv8i8 + /* 57023 */ MCD_OPC_FilterValue, + 33, + 139, + 185, + 0, // Skip to: 104527 + /* 57028 */ MCD_OPC_CheckPredicate, + 21, + 134, + 185, + 0, // Skip to: 104527 + /* 57033 */ MCD_OPC_Decode, + 225, + 14, + 156, + 2, // Opcode: FCVTMUv2f32 + /* 57038 */ MCD_OPC_FilterValue, + 3, + 124, + 185, + 0, // Skip to: 104527 + /* 57043 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 57046 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 57068 + /* 57051 */ MCD_OPC_CheckPredicate, + 21, + 111, + 185, + 0, // Skip to: 104527 + /* 57056 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 104, + 185, + 0, // Skip to: 104527 + /* 57063 */ MCD_OPC_Decode, + 156, + 44, + 151, + 2, // Opcode: UMULLv8i8_v8i16 + /* 57068 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 57090 + /* 57073 */ MCD_OPC_CheckPredicate, + 21, + 89, + 185, + 0, // Skip to: 104527 + /* 57078 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 82, + 185, + 0, // Skip to: 104527 + /* 57085 */ MCD_OPC_Decode, + 156, + 16, + 155, + 2, // Opcode: FMAXNMPv2f32 + /* 57090 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 57112 + /* 57095 */ MCD_OPC_CheckPredicate, + 21, + 67, + 185, + 0, // Skip to: 104527 + /* 57100 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 60, + 185, + 0, // Skip to: 104527 + /* 57107 */ MCD_OPC_Decode, + 187, + 14, + 156, + 2, // Opcode: FCVTAUv2f32 + /* 57112 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 57134 + /* 57117 */ MCD_OPC_CheckPredicate, + 25, + 45, + 185, + 0, // Skip to: 104527 + /* 57122 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 38, + 185, + 0, // Skip to: 104527 + /* 57129 */ MCD_OPC_Decode, + 147, + 17, + 176, + 2, // Opcode: FMLAL2v4f16 + /* 57134 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 57156 + /* 57139 */ MCD_OPC_CheckPredicate, + 21, + 23, + 185, + 0, // Skip to: 104527 + /* 57144 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 16, + 185, + 0, // Skip to: 104527 + /* 57151 */ MCD_OPC_Decode, + 252, + 12, + 155, + 2, // Opcode: FADDPv2f32 + /* 57156 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 57178 + /* 57161 */ MCD_OPC_CheckPredicate, + 21, + 1, + 185, + 0, // Skip to: 104527 + /* 57166 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 250, + 184, + 0, // Skip to: 104527 + /* 57173 */ MCD_OPC_Decode, + 213, + 42, + 156, + 2, // Opcode: UCVTFv2f32 + /* 57178 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 57200 + /* 57183 */ MCD_OPC_CheckPredicate, + 21, + 235, + 184, + 0, // Skip to: 104527 + /* 57188 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 228, + 184, + 0, // Skip to: 104527 + /* 57195 */ MCD_OPC_Decode, + 149, + 18, + 155, + 2, // Opcode: FMULv2f32 + /* 57200 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 57222 + /* 57205 */ MCD_OPC_CheckPredicate, + 21, + 213, + 184, + 0, // Skip to: 104527 + /* 57210 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 206, + 184, + 0, // Skip to: 104527 + /* 57217 */ MCD_OPC_Decode, + 198, + 13, + 155, + 2, // Opcode: FCMGEv2f32 + /* 57222 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 57244 + /* 57227 */ MCD_OPC_CheckPredicate, + 24, + 191, + 184, + 0, // Skip to: 104527 + /* 57232 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 184, + 184, + 0, // Skip to: 104527 + /* 57239 */ MCD_OPC_Decode, + 221, + 18, + 156, + 2, // Opcode: FRINT32Xv2f32 + /* 57244 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 57266 + /* 57249 */ MCD_OPC_CheckPredicate, + 21, + 169, + 184, + 0, // Skip to: 104527 + /* 57254 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 162, + 184, + 0, // Skip to: 104527 + /* 57261 */ MCD_OPC_Decode, + 228, + 12, + 155, + 2, // Opcode: FACGEv2f32 + /* 57266 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 57288 + /* 57271 */ MCD_OPC_CheckPredicate, + 21, + 147, + 184, + 0, // Skip to: 104527 + /* 57276 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 140, + 184, + 0, // Skip to: 104527 + /* 57283 */ MCD_OPC_Decode, + 185, + 16, + 155, + 2, // Opcode: FMAXPv2f32 + /* 57288 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 57310 + /* 57293 */ MCD_OPC_CheckPredicate, + 24, + 125, + 184, + 0, // Skip to: 104527 + /* 57298 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 118, + 184, + 0, // Skip to: 104527 + /* 57305 */ MCD_OPC_Decode, + 231, + 18, + 156, + 2, // Opcode: FRINT64Xv2f32 + /* 57310 */ MCD_OPC_FilterValue, + 15, + 108, + 184, + 0, // Skip to: 104527 + /* 57315 */ MCD_OPC_CheckPredicate, + 21, + 103, + 184, + 0, // Skip to: 104527 + /* 57320 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 96, + 184, + 0, // Skip to: 104527 + /* 57327 */ MCD_OPC_Decode, + 128, + 16, + 155, + 2, // Opcode: FDIVv2f32 + /* 57332 */ MCD_OPC_FilterValue, + 2, + 239, + 8, + 0, // Skip to: 59624 + /* 57337 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 57340 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 57378 + /* 57345 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 57348 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 57363 + /* 57353 */ MCD_OPC_CheckPredicate, + 21, + 65, + 184, + 0, // Skip to: 104527 + /* 57358 */ MCD_OPC_Decode, + 158, + 41, + 179, + 2, // Opcode: TBLv16i8One + /* 57363 */ MCD_OPC_FilterValue, + 1, + 55, + 184, + 0, // Skip to: 104527 + /* 57368 */ MCD_OPC_CheckPredicate, + 21, + 50, + 184, + 0, // Skip to: 104527 + /* 57373 */ MCD_OPC_Decode, + 163, + 30, + 179, + 2, // Opcode: SADDLv16i8_v8i16 + /* 57378 */ MCD_OPC_FilterValue, + 1, + 109, + 0, + 0, // Skip to: 57492 + /* 57383 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 57386 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 57477 + /* 57391 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 57394 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 57462 + /* 57399 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 57402 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 57447 + /* 57407 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 57410 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 57432 + /* 57415 */ MCD_OPC_CheckPredicate, + 21, + 3, + 184, + 0, // Skip to: 104527 + /* 57420 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 252, + 183, + 0, // Skip to: 104527 + /* 57427 */ MCD_OPC_Decode, + 142, + 12, + 180, + 2, // Opcode: DUPv2i64lane + /* 57432 */ MCD_OPC_FilterValue, + 1, + 242, + 183, + 0, // Skip to: 104527 + /* 57437 */ MCD_OPC_CheckPredicate, + 21, + 237, + 183, + 0, // Skip to: 104527 + /* 57442 */ MCD_OPC_Decode, + 146, + 12, + 181, + 2, // Opcode: DUPv4i32lane + /* 57447 */ MCD_OPC_FilterValue, + 1, + 227, + 183, + 0, // Skip to: 104527 + /* 57452 */ MCD_OPC_CheckPredicate, + 21, + 222, + 183, + 0, // Skip to: 104527 + /* 57457 */ MCD_OPC_Decode, + 148, + 12, + 182, + 2, // Opcode: DUPv8i16lane + /* 57462 */ MCD_OPC_FilterValue, + 1, + 212, + 183, + 0, // Skip to: 104527 + /* 57467 */ MCD_OPC_CheckPredicate, + 21, + 207, + 183, + 0, // Skip to: 104527 + /* 57472 */ MCD_OPC_Decode, + 138, + 12, + 183, + 2, // Opcode: DUPv16i8lane + /* 57477 */ MCD_OPC_FilterValue, + 1, + 197, + 183, + 0, // Skip to: 104527 + /* 57482 */ MCD_OPC_CheckPredicate, + 21, + 192, + 183, + 0, // Skip to: 104527 + /* 57487 */ MCD_OPC_Decode, + 146, + 31, + 179, + 2, // Opcode: SHADDv16i8 + /* 57492 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 57514 + /* 57497 */ MCD_OPC_CheckPredicate, + 21, + 177, + 183, + 0, // Skip to: 104527 + /* 57502 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 170, + 183, + 0, // Skip to: 104527 + /* 57509 */ MCD_OPC_Decode, + 168, + 29, + 184, + 2, // Opcode: REV64v16i8 + /* 57514 */ MCD_OPC_FilterValue, + 3, + 109, + 0, + 0, // Skip to: 57628 + /* 57519 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 57522 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 57613 + /* 57527 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 57530 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 57598 + /* 57535 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 57538 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 57583 + /* 57543 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 57546 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 57568 + /* 57551 */ MCD_OPC_CheckPredicate, + 21, + 123, + 183, + 0, // Skip to: 104527 + /* 57556 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 116, + 183, + 0, // Skip to: 104527 + /* 57563 */ MCD_OPC_Decode, + 141, + 12, + 185, + 2, // Opcode: DUPv2i64gpr + /* 57568 */ MCD_OPC_FilterValue, + 1, + 106, + 183, + 0, // Skip to: 104527 + /* 57573 */ MCD_OPC_CheckPredicate, + 21, + 101, + 183, + 0, // Skip to: 104527 + /* 57578 */ MCD_OPC_Decode, + 145, + 12, + 186, + 2, // Opcode: DUPv4i32gpr + /* 57583 */ MCD_OPC_FilterValue, + 1, + 91, + 183, + 0, // Skip to: 104527 + /* 57588 */ MCD_OPC_CheckPredicate, + 21, + 86, + 183, + 0, // Skip to: 104527 + /* 57593 */ MCD_OPC_Decode, + 147, + 12, + 186, + 2, // Opcode: DUPv8i16gpr + /* 57598 */ MCD_OPC_FilterValue, + 1, + 76, + 183, + 0, // Skip to: 104527 + /* 57603 */ MCD_OPC_CheckPredicate, + 21, + 71, + 183, + 0, // Skip to: 104527 + /* 57608 */ MCD_OPC_Decode, + 137, + 12, + 186, + 2, // Opcode: DUPv16i8gpr + /* 57613 */ MCD_OPC_FilterValue, + 1, + 61, + 183, + 0, // Skip to: 104527 + /* 57618 */ MCD_OPC_CheckPredicate, + 21, + 56, + 183, + 0, // Skip to: 104527 + /* 57623 */ MCD_OPC_Decode, + 148, + 33, + 179, + 2, // Opcode: SQADDv16i8 + /* 57628 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 57666 + /* 57633 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 57636 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 57651 + /* 57641 */ MCD_OPC_CheckPredicate, + 21, + 33, + 183, + 0, // Skip to: 104527 + /* 57646 */ MCD_OPC_Decode, + 172, + 41, + 187, + 2, // Opcode: TBXv16i8One + /* 57651 */ MCD_OPC_FilterValue, + 1, + 23, + 183, + 0, // Skip to: 104527 + /* 57656 */ MCD_OPC_CheckPredicate, + 21, + 18, + 183, + 0, // Skip to: 104527 + /* 57661 */ MCD_OPC_Decode, + 178, + 30, + 179, + 2, // Opcode: SADDWv16i8_v8i16 + /* 57666 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 57688 + /* 57671 */ MCD_OPC_CheckPredicate, + 21, + 3, + 183, + 0, // Skip to: 104527 + /* 57676 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 252, + 182, + 0, // Skip to: 104527 + /* 57683 */ MCD_OPC_Decode, + 181, + 36, + 179, + 2, // Opcode: SRHADDv16i8 + /* 57688 */ MCD_OPC_FilterValue, + 6, + 40, + 0, + 0, // Skip to: 57733 + /* 57693 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 57696 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 57711 + /* 57701 */ MCD_OPC_CheckPredicate, + 21, + 229, + 182, + 0, // Skip to: 104527 + /* 57706 */ MCD_OPC_Decode, + 133, + 47, + 179, + 2, // Opcode: UZP1v16i8 + /* 57711 */ MCD_OPC_FilterValue, + 1, + 219, + 182, + 0, // Skip to: 104527 + /* 57716 */ MCD_OPC_CheckPredicate, + 21, + 214, + 182, + 0, // Skip to: 104527 + /* 57721 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 207, + 182, + 0, // Skip to: 104527 + /* 57728 */ MCD_OPC_Decode, + 161, + 29, + 184, + 2, // Opcode: REV16v16i8 + /* 57733 */ MCD_OPC_FilterValue, + 7, + 109, + 0, + 0, // Skip to: 57847 + /* 57738 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 57741 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 57832 + /* 57746 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 57749 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 57817 + /* 57754 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 57757 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 57802 + /* 57762 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 57765 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 57787 + /* 57770 */ MCD_OPC_CheckPredicate, + 21, + 160, + 182, + 0, // Skip to: 104527 + /* 57775 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 153, + 182, + 0, // Skip to: 104527 + /* 57782 */ MCD_OPC_Decode, + 187, + 21, + 188, + 2, // Opcode: INSvi64gpr + /* 57787 */ MCD_OPC_FilterValue, + 1, + 143, + 182, + 0, // Skip to: 104527 + /* 57792 */ MCD_OPC_CheckPredicate, + 21, + 138, + 182, + 0, // Skip to: 104527 + /* 57797 */ MCD_OPC_Decode, + 185, + 21, + 189, + 2, // Opcode: INSvi32gpr + /* 57802 */ MCD_OPC_FilterValue, + 1, + 128, + 182, + 0, // Skip to: 104527 + /* 57807 */ MCD_OPC_CheckPredicate, + 21, + 123, + 182, + 0, // Skip to: 104527 + /* 57812 */ MCD_OPC_Decode, + 183, + 21, + 190, + 2, // Opcode: INSvi16gpr + /* 57817 */ MCD_OPC_FilterValue, + 1, + 113, + 182, + 0, // Skip to: 104527 + /* 57822 */ MCD_OPC_CheckPredicate, + 21, + 108, + 182, + 0, // Skip to: 104527 + /* 57827 */ MCD_OPC_Decode, + 189, + 21, + 191, + 2, // Opcode: INSvi8gpr + /* 57832 */ MCD_OPC_FilterValue, + 1, + 98, + 182, + 0, // Skip to: 104527 + /* 57837 */ MCD_OPC_CheckPredicate, + 21, + 93, + 182, + 0, // Skip to: 104527 + /* 57842 */ MCD_OPC_Decode, + 136, + 8, + 179, + 2, // Opcode: ANDv16i8 + /* 57847 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 57885 + /* 57852 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 57855 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 57870 + /* 57860 */ MCD_OPC_CheckPredicate, + 21, + 70, + 182, + 0, // Skip to: 104527 + /* 57865 */ MCD_OPC_Decode, + 160, + 41, + 192, + 2, // Opcode: TBLv16i8Two + /* 57870 */ MCD_OPC_FilterValue, + 1, + 60, + 182, + 0, // Skip to: 104527 + /* 57875 */ MCD_OPC_CheckPredicate, + 21, + 55, + 182, + 0, // Skip to: 104527 + /* 57880 */ MCD_OPC_Decode, + 201, + 37, + 179, + 2, // Opcode: SSUBLv16i8_v8i16 + /* 57885 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 57907 + /* 57890 */ MCD_OPC_CheckPredicate, + 21, + 40, + 182, + 0, // Skip to: 104527 + /* 57895 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 33, + 182, + 0, // Skip to: 104527 + /* 57902 */ MCD_OPC_Decode, + 186, + 31, + 179, + 2, // Opcode: SHSUBv16i8 + /* 57907 */ MCD_OPC_FilterValue, + 10, + 56, + 0, + 0, // Skip to: 57968 + /* 57912 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 57915 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 57930 + /* 57920 */ MCD_OPC_CheckPredicate, + 21, + 10, + 182, + 0, // Skip to: 104527 + /* 57925 */ MCD_OPC_Decode, + 192, + 41, + 179, + 2, // Opcode: TRN1v16i8 + /* 57930 */ MCD_OPC_FilterValue, + 1, + 0, + 182, + 0, // Skip to: 104527 + /* 57935 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 57938 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 57953 + /* 57943 */ MCD_OPC_CheckPredicate, + 21, + 243, + 181, + 0, // Skip to: 104527 + /* 57948 */ MCD_OPC_Decode, + 149, + 30, + 184, + 2, // Opcode: SADDLPv16i8_v8i16 + /* 57953 */ MCD_OPC_FilterValue, + 1, + 233, + 181, + 0, // Skip to: 104527 + /* 57958 */ MCD_OPC_CheckPredicate, + 21, + 228, + 181, + 0, // Skip to: 104527 + /* 57963 */ MCD_OPC_Decode, + 240, + 47, + 193, + 2, // Opcode: XTNv16i8 + /* 57968 */ MCD_OPC_FilterValue, + 11, + 138, + 0, + 0, // Skip to: 58111 + /* 57973 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 57976 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 58096 + /* 57981 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 57984 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 58064 + /* 57989 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 57992 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 58032 + /* 57997 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 58000 */ MCD_OPC_FilterValue, + 1, + 186, + 181, + 0, // Skip to: 104527 + /* 58005 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 58022 + /* 58010 */ MCD_OPC_CheckField, + 19, + 2, + 0, + 5, + 0, + 0, // Skip to: 58022 + /* 58017 */ MCD_OPC_Decode, + 206, + 32, + 194, + 2, // Opcode: SMOVvi32to64_idx0 + /* 58022 */ MCD_OPC_CheckPredicate, + 21, + 164, + 181, + 0, // Skip to: 104527 + /* 58027 */ MCD_OPC_Decode, + 205, + 32, + 195, + 2, // Opcode: SMOVvi32to64 + /* 58032 */ MCD_OPC_FilterValue, + 1, + 154, + 181, + 0, // Skip to: 104527 + /* 58037 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 58054 + /* 58042 */ MCD_OPC_CheckField, + 18, + 3, + 0, + 5, + 0, + 0, // Skip to: 58054 + /* 58049 */ MCD_OPC_Decode, + 204, + 32, + 194, + 2, // Opcode: SMOVvi16to64_idx0 + /* 58054 */ MCD_OPC_CheckPredicate, + 21, + 132, + 181, + 0, // Skip to: 104527 + /* 58059 */ MCD_OPC_Decode, + 203, + 32, + 196, + 2, // Opcode: SMOVvi16to64 + /* 58064 */ MCD_OPC_FilterValue, + 1, + 122, + 181, + 0, // Skip to: 104527 + /* 58069 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 58086 + /* 58074 */ MCD_OPC_CheckField, + 17, + 4, + 0, + 5, + 0, + 0, // Skip to: 58086 + /* 58081 */ MCD_OPC_Decode, + 210, + 32, + 194, + 2, // Opcode: SMOVvi8to64_idx0 + /* 58086 */ MCD_OPC_CheckPredicate, + 21, + 100, + 181, + 0, // Skip to: 104527 + /* 58091 */ MCD_OPC_Decode, + 209, + 32, + 197, + 2, // Opcode: SMOVvi8to64 + /* 58096 */ MCD_OPC_FilterValue, + 1, + 90, + 181, + 0, // Skip to: 104527 + /* 58101 */ MCD_OPC_CheckPredicate, + 21, + 85, + 181, + 0, // Skip to: 104527 + /* 58106 */ MCD_OPC_Decode, + 136, + 36, + 179, + 2, // Opcode: SQSUBv16i8 + /* 58111 */ MCD_OPC_FilterValue, + 12, + 33, + 0, + 0, // Skip to: 58149 + /* 58116 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58119 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58134 + /* 58124 */ MCD_OPC_CheckPredicate, + 21, + 62, + 181, + 0, // Skip to: 104527 + /* 58129 */ MCD_OPC_Decode, + 174, + 41, + 198, + 2, // Opcode: TBXv16i8Two + /* 58134 */ MCD_OPC_FilterValue, + 1, + 52, + 181, + 0, // Skip to: 104527 + /* 58139 */ MCD_OPC_CheckPredicate, + 21, + 47, + 181, + 0, // Skip to: 104527 + /* 58144 */ MCD_OPC_Decode, + 213, + 37, + 179, + 2, // Opcode: SSUBWv16i8_v8i16 + /* 58149 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 58171 + /* 58154 */ MCD_OPC_CheckPredicate, + 21, + 32, + 181, + 0, // Skip to: 104527 + /* 58159 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 25, + 181, + 0, // Skip to: 104527 + /* 58166 */ MCD_OPC_Decode, + 142, + 10, + 179, + 2, // Opcode: CMGTv16i8 + /* 58171 */ MCD_OPC_FilterValue, + 14, + 56, + 0, + 0, // Skip to: 58232 + /* 58176 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58179 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58194 + /* 58184 */ MCD_OPC_CheckPredicate, + 21, + 2, + 181, + 0, // Skip to: 104527 + /* 58189 */ MCD_OPC_Decode, + 128, + 48, + 179, + 2, // Opcode: ZIP1v16i8 + /* 58194 */ MCD_OPC_FilterValue, + 1, + 248, + 180, + 0, // Skip to: 104527 + /* 58199 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 58202 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58217 + /* 58207 */ MCD_OPC_CheckPredicate, + 21, + 235, + 180, + 0, // Skip to: 104527 + /* 58212 */ MCD_OPC_Decode, + 241, + 40, + 193, + 2, // Opcode: SUQADDv16i8 + /* 58217 */ MCD_OPC_FilterValue, + 16, + 225, + 180, + 0, // Skip to: 104527 + /* 58222 */ MCD_OPC_CheckPredicate, + 21, + 220, + 180, + 0, // Skip to: 104527 + /* 58227 */ MCD_OPC_Decode, + 158, + 30, + 199, + 2, // Opcode: SADDLVv16i8v + /* 58232 */ MCD_OPC_FilterValue, + 15, + 58, + 0, + 0, // Skip to: 58295 + /* 58237 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58240 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 58280 + /* 58245 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 58248 */ MCD_OPC_FilterValue, + 8, + 194, + 180, + 0, // Skip to: 104527 + /* 58253 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 58270 + /* 58258 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 5, + 0, + 0, // Skip to: 58270 + /* 58265 */ MCD_OPC_Decode, + 252, + 43, + 194, + 2, // Opcode: UMOVvi64_idx0 + /* 58270 */ MCD_OPC_CheckPredicate, + 21, + 172, + 180, + 0, // Skip to: 104527 + /* 58275 */ MCD_OPC_Decode, + 251, + 43, + 200, + 2, // Opcode: UMOVvi64 + /* 58280 */ MCD_OPC_FilterValue, + 1, + 162, + 180, + 0, // Skip to: 104527 + /* 58285 */ MCD_OPC_CheckPredicate, + 21, + 157, + 180, + 0, // Skip to: 104527 + /* 58290 */ MCD_OPC_Decode, + 254, + 9, + 179, + 2, // Opcode: CMGEv16i8 + /* 58295 */ MCD_OPC_FilterValue, + 16, + 33, + 0, + 0, // Skip to: 58333 + /* 58300 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58303 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58318 + /* 58308 */ MCD_OPC_CheckPredicate, + 21, + 134, + 180, + 0, // Skip to: 104527 + /* 58313 */ MCD_OPC_Decode, + 159, + 41, + 201, + 2, // Opcode: TBLv16i8Three + /* 58318 */ MCD_OPC_FilterValue, + 1, + 124, + 180, + 0, // Skip to: 104527 + /* 58323 */ MCD_OPC_CheckPredicate, + 21, + 119, + 180, + 0, // Skip to: 104527 + /* 58328 */ MCD_OPC_Decode, + 161, + 7, + 187, + 2, // Opcode: ADDHNv8i16_v16i8 + /* 58333 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 58355 + /* 58338 */ MCD_OPC_CheckPredicate, + 21, + 104, + 180, + 0, // Skip to: 104527 + /* 58343 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 97, + 180, + 0, // Skip to: 104527 + /* 58350 */ MCD_OPC_Decode, + 251, + 36, + 179, + 2, // Opcode: SSHLv16i8 + /* 58355 */ MCD_OPC_FilterValue, + 18, + 48, + 0, + 0, // Skip to: 58408 + /* 58360 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 58363 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 58378 + /* 58368 */ MCD_OPC_CheckPredicate, + 21, + 74, + 180, + 0, // Skip to: 104527 + /* 58373 */ MCD_OPC_Decode, + 220, + 9, + 184, + 2, // Opcode: CLSv16i8 + /* 58378 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 58393 + /* 58383 */ MCD_OPC_CheckPredicate, + 21, + 59, + 180, + 0, // Skip to: 104527 + /* 58388 */ MCD_OPC_Decode, + 153, + 36, + 193, + 2, // Opcode: SQXTNv16i8 + /* 58393 */ MCD_OPC_FilterValue, + 40, + 49, + 180, + 0, // Skip to: 104527 + /* 58398 */ MCD_OPC_CheckPredicate, + 26, + 44, + 180, + 0, // Skip to: 104527 + /* 58403 */ MCD_OPC_Decode, + 239, + 7, + 193, + 2, // Opcode: AESErr + /* 58408 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 58430 + /* 58413 */ MCD_OPC_CheckPredicate, + 21, + 29, + 180, + 0, // Skip to: 104527 + /* 58418 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 22, + 180, + 0, // Skip to: 104527 + /* 58425 */ MCD_OPC_Decode, + 200, + 35, + 179, + 2, // Opcode: SQSHLv16i8 + /* 58430 */ MCD_OPC_FilterValue, + 20, + 33, + 0, + 0, // Skip to: 58468 + /* 58435 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58438 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58453 + /* 58443 */ MCD_OPC_CheckPredicate, + 21, + 255, + 179, + 0, // Skip to: 104527 + /* 58448 */ MCD_OPC_Decode, + 173, + 41, + 202, + 2, // Opcode: TBXv16i8Three + /* 58453 */ MCD_OPC_FilterValue, + 1, + 245, + 179, + 0, // Skip to: 104527 + /* 58458 */ MCD_OPC_CheckPredicate, + 21, + 240, + 179, + 0, // Skip to: 104527 + /* 58463 */ MCD_OPC_Decode, + 224, + 29, + 187, + 2, // Opcode: SABALv16i8_v8i16 + /* 58468 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 58490 + /* 58473 */ MCD_OPC_CheckPredicate, + 21, + 225, + 179, + 0, // Skip to: 104527 + /* 58478 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 218, + 179, + 0, // Skip to: 104527 + /* 58485 */ MCD_OPC_Decode, + 207, + 36, + 179, + 2, // Opcode: SRSHLv16i8 + /* 58490 */ MCD_OPC_FilterValue, + 22, + 56, + 0, + 0, // Skip to: 58551 + /* 58495 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58498 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58513 + /* 58503 */ MCD_OPC_CheckPredicate, + 21, + 195, + 179, + 0, // Skip to: 104527 + /* 58508 */ MCD_OPC_Decode, + 149, + 47, + 179, + 2, // Opcode: UZP2v16i8 + /* 58513 */ MCD_OPC_FilterValue, + 1, + 185, + 179, + 0, // Skip to: 104527 + /* 58518 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 58521 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58536 + /* 58526 */ MCD_OPC_CheckPredicate, + 21, + 172, + 179, + 0, // Skip to: 104527 + /* 58531 */ MCD_OPC_Decode, + 186, + 11, + 184, + 2, // Opcode: CNTv16i8 + /* 58536 */ MCD_OPC_FilterValue, + 8, + 162, + 179, + 0, // Skip to: 104527 + /* 58541 */ MCD_OPC_CheckPredicate, + 26, + 157, + 179, + 0, // Skip to: 104527 + /* 58546 */ MCD_OPC_Decode, + 237, + 7, + 193, + 2, // Opcode: AESDrr + /* 58551 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 58573 + /* 58556 */ MCD_OPC_CheckPredicate, + 21, + 142, + 179, + 0, // Skip to: 104527 + /* 58561 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 135, + 179, + 0, // Skip to: 104527 + /* 58568 */ MCD_OPC_Decode, + 128, + 35, + 179, + 2, // Opcode: SQRSHLv16i8 + /* 58573 */ MCD_OPC_FilterValue, + 24, + 33, + 0, + 0, // Skip to: 58611 + /* 58578 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58581 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58596 + /* 58586 */ MCD_OPC_CheckPredicate, + 21, + 112, + 179, + 0, // Skip to: 104527 + /* 58591 */ MCD_OPC_Decode, + 157, + 41, + 203, + 2, // Opcode: TBLv16i8Four + /* 58596 */ MCD_OPC_FilterValue, + 1, + 102, + 179, + 0, // Skip to: 104527 + /* 58601 */ MCD_OPC_CheckPredicate, + 21, + 97, + 179, + 0, // Skip to: 104527 + /* 58606 */ MCD_OPC_Decode, + 178, + 40, + 187, + 2, // Opcode: SUBHNv8i16_v16i8 + /* 58611 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 58633 + /* 58616 */ MCD_OPC_CheckPredicate, + 21, + 82, + 179, + 0, // Skip to: 104527 + /* 58621 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 75, + 179, + 0, // Skip to: 104527 + /* 58628 */ MCD_OPC_Decode, + 243, + 31, + 179, + 2, // Opcode: SMAXv16i8 + /* 58633 */ MCD_OPC_FilterValue, + 26, + 71, + 0, + 0, // Skip to: 58709 + /* 58638 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58641 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58656 + /* 58646 */ MCD_OPC_CheckPredicate, + 21, + 52, + 179, + 0, // Skip to: 104527 + /* 58651 */ MCD_OPC_Decode, + 208, + 41, + 179, + 2, // Opcode: TRN2v16i8 + /* 58656 */ MCD_OPC_FilterValue, + 1, + 42, + 179, + 0, // Skip to: 104527 + /* 58661 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 58664 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58679 + /* 58669 */ MCD_OPC_CheckPredicate, + 21, + 29, + 179, + 0, // Skip to: 104527 + /* 58674 */ MCD_OPC_Decode, + 137, + 30, + 193, + 2, // Opcode: SADALPv16i8_v8i16 + /* 58679 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 58694 + /* 58684 */ MCD_OPC_CheckPredicate, + 21, + 14, + 179, + 0, // Skip to: 104527 + /* 58689 */ MCD_OPC_Decode, + 135, + 15, + 193, + 2, // Opcode: FCVTNv8i16 + /* 58694 */ MCD_OPC_FilterValue, + 8, + 4, + 179, + 0, // Skip to: 104527 + /* 58699 */ MCD_OPC_CheckPredicate, + 26, + 255, + 178, + 0, // Skip to: 104527 + /* 58704 */ MCD_OPC_Decode, + 243, + 7, + 184, + 2, // Opcode: AESMCrr + /* 58709 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 58731 + /* 58714 */ MCD_OPC_CheckPredicate, + 21, + 240, + 178, + 0, // Skip to: 104527 + /* 58719 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 233, + 178, + 0, // Skip to: 104527 + /* 58726 */ MCD_OPC_Decode, + 149, + 32, + 179, + 2, // Opcode: SMINv16i8 + /* 58731 */ MCD_OPC_FilterValue, + 28, + 33, + 0, + 0, // Skip to: 58769 + /* 58736 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58739 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58754 + /* 58744 */ MCD_OPC_CheckPredicate, + 21, + 210, + 178, + 0, // Skip to: 104527 + /* 58749 */ MCD_OPC_Decode, + 171, + 41, + 204, + 2, // Opcode: TBXv16i8Four + /* 58754 */ MCD_OPC_FilterValue, + 1, + 200, + 178, + 0, // Skip to: 104527 + /* 58759 */ MCD_OPC_CheckPredicate, + 21, + 195, + 178, + 0, // Skip to: 104527 + /* 58764 */ MCD_OPC_Decode, + 246, + 29, + 179, + 2, // Opcode: SABDLv16i8_v8i16 + /* 58769 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 58791 + /* 58774 */ MCD_OPC_CheckPredicate, + 21, + 180, + 178, + 0, // Skip to: 104527 + /* 58779 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 173, + 178, + 0, // Skip to: 104527 + /* 58786 */ MCD_OPC_Decode, + 128, + 30, + 179, + 2, // Opcode: SABDv16i8 + /* 58791 */ MCD_OPC_FilterValue, + 30, + 71, + 0, + 0, // Skip to: 58867 + /* 58796 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 58799 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58814 + /* 58804 */ MCD_OPC_CheckPredicate, + 21, + 150, + 178, + 0, // Skip to: 104527 + /* 58809 */ MCD_OPC_Decode, + 144, + 48, + 179, + 2, // Opcode: ZIP2v16i8 + /* 58814 */ MCD_OPC_FilterValue, + 1, + 140, + 178, + 0, // Skip to: 104527 + /* 58819 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 58822 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 58837 + /* 58827 */ MCD_OPC_CheckPredicate, + 21, + 127, + 178, + 0, // Skip to: 104527 + /* 58832 */ MCD_OPC_Decode, + 253, + 32, + 184, + 2, // Opcode: SQABSv16i8 + /* 58837 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 58852 + /* 58842 */ MCD_OPC_CheckPredicate, + 21, + 112, + 178, + 0, // Skip to: 104527 + /* 58847 */ MCD_OPC_Decode, + 201, + 14, + 184, + 2, // Opcode: FCVTLv8i16 + /* 58852 */ MCD_OPC_FilterValue, + 8, + 102, + 178, + 0, // Skip to: 104527 + /* 58857 */ MCD_OPC_CheckPredicate, + 26, + 97, + 178, + 0, // Skip to: 104527 + /* 58862 */ MCD_OPC_Decode, + 241, + 7, + 184, + 2, // Opcode: AESIMCrr + /* 58867 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 58889 + /* 58872 */ MCD_OPC_CheckPredicate, + 21, + 82, + 178, + 0, // Skip to: 104527 + /* 58877 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 75, + 178, + 0, // Skip to: 104527 + /* 58884 */ MCD_OPC_Decode, + 234, + 29, + 187, + 2, // Opcode: SABAv16i8 + /* 58889 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 58911 + /* 58894 */ MCD_OPC_CheckPredicate, + 21, + 60, + 178, + 0, // Skip to: 104527 + /* 58899 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 53, + 178, + 0, // Skip to: 104527 + /* 58906 */ MCD_OPC_Decode, + 165, + 32, + 187, + 2, // Opcode: SMLALv16i8_v8i16 + /* 58911 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 58933 + /* 58916 */ MCD_OPC_CheckPredicate, + 21, + 38, + 178, + 0, // Skip to: 104527 + /* 58921 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 31, + 178, + 0, // Skip to: 104527 + /* 58928 */ MCD_OPC_Decode, + 210, + 7, + 179, + 2, // Opcode: ADDv16i8 + /* 58933 */ MCD_OPC_FilterValue, + 34, + 33, + 0, + 0, // Skip to: 58971 + /* 58938 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 58941 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 58956 + /* 58946 */ MCD_OPC_CheckPredicate, + 21, + 8, + 178, + 0, // Skip to: 104527 + /* 58951 */ MCD_OPC_Decode, + 143, + 10, + 184, + 2, // Opcode: CMGTv16i8rz + /* 58956 */ MCD_OPC_FilterValue, + 33, + 254, + 177, + 0, // Skip to: 104527 + /* 58961 */ MCD_OPC_CheckPredicate, + 21, + 249, + 177, + 0, // Skip to: 104527 + /* 58966 */ MCD_OPC_Decode, + 153, + 19, + 184, + 2, // Opcode: FRINTNv4f32 + /* 58971 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 58993 + /* 58976 */ MCD_OPC_CheckPredicate, + 21, + 234, + 177, + 0, // Skip to: 104527 + /* 58981 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 227, + 177, + 0, // Skip to: 104527 + /* 58988 */ MCD_OPC_Decode, + 162, + 11, + 179, + 2, // Opcode: CMTSTv16i8 + /* 58993 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 59015 + /* 58998 */ MCD_OPC_CheckPredicate, + 21, + 212, + 177, + 0, // Skip to: 104527 + /* 59003 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 205, + 177, + 0, // Skip to: 104527 + /* 59010 */ MCD_OPC_Decode, + 149, + 27, + 187, + 2, // Opcode: MLAv16i8 + /* 59015 */ MCD_OPC_FilterValue, + 38, + 33, + 0, + 0, // Skip to: 59053 + /* 59020 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 59023 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 59038 + /* 59028 */ MCD_OPC_CheckPredicate, + 21, + 182, + 177, + 0, // Skip to: 104527 + /* 59033 */ MCD_OPC_Decode, + 239, + 9, + 184, + 2, // Opcode: CMEQv16i8rz + /* 59038 */ MCD_OPC_FilterValue, + 33, + 172, + 177, + 0, // Skip to: 104527 + /* 59043 */ MCD_OPC_CheckPredicate, + 21, + 167, + 177, + 0, // Skip to: 104527 + /* 59048 */ MCD_OPC_Decode, + 142, + 19, + 184, + 2, // Opcode: FRINTMv4f32 + /* 59053 */ MCD_OPC_FilterValue, + 39, + 17, + 0, + 0, // Skip to: 59075 + /* 59058 */ MCD_OPC_CheckPredicate, + 21, + 152, + 177, + 0, // Skip to: 104527 + /* 59063 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 145, + 177, + 0, // Skip to: 104527 + /* 59070 */ MCD_OPC_Decode, + 227, + 27, + 179, + 2, // Opcode: MULv16i8 + /* 59075 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 59097 + /* 59080 */ MCD_OPC_CheckPredicate, + 21, + 130, + 177, + 0, // Skip to: 104527 + /* 59085 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 123, + 177, + 0, // Skip to: 104527 + /* 59092 */ MCD_OPC_Decode, + 185, + 32, + 187, + 2, // Opcode: SMLSLv16i8_v8i16 + /* 59097 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 59119 + /* 59102 */ MCD_OPC_CheckPredicate, + 21, + 108, + 177, + 0, // Skip to: 104527 + /* 59107 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 101, + 177, + 0, // Skip to: 104527 + /* 59114 */ MCD_OPC_Decode, + 220, + 31, + 179, + 2, // Opcode: SMAXPv16i8 + /* 59119 */ MCD_OPC_FilterValue, + 42, + 63, + 0, + 0, // Skip to: 59187 + /* 59124 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 59127 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 59142 + /* 59132 */ MCD_OPC_CheckPredicate, + 21, + 78, + 177, + 0, // Skip to: 104527 + /* 59137 */ MCD_OPC_Decode, + 188, + 10, + 184, + 2, // Opcode: CMLTv16i8rz + /* 59142 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 59157 + /* 59147 */ MCD_OPC_CheckPredicate, + 21, + 63, + 177, + 0, // Skip to: 104527 + /* 59152 */ MCD_OPC_Decode, + 242, + 14, + 184, + 2, // Opcode: FCVTNSv4f32 + /* 59157 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 59172 + /* 59162 */ MCD_OPC_CheckPredicate, + 21, + 48, + 177, + 0, // Skip to: 104527 + /* 59167 */ MCD_OPC_Decode, + 230, + 31, + 205, + 2, // Opcode: SMAXVv16i8v + /* 59172 */ MCD_OPC_FilterValue, + 49, + 38, + 177, + 0, // Skip to: 104527 + /* 59177 */ MCD_OPC_CheckPredicate, + 21, + 33, + 177, + 0, // Skip to: 104527 + /* 59182 */ MCD_OPC_Decode, + 136, + 32, + 205, + 2, // Opcode: SMINVv16i8v + /* 59187 */ MCD_OPC_FilterValue, + 43, + 17, + 0, + 0, // Skip to: 59209 + /* 59192 */ MCD_OPC_CheckPredicate, + 21, + 18, + 177, + 0, // Skip to: 104527 + /* 59197 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 11, + 177, + 0, // Skip to: 104527 + /* 59204 */ MCD_OPC_Decode, + 254, + 31, + 179, + 2, // Opcode: SMINPv16i8 + /* 59209 */ MCD_OPC_FilterValue, + 46, + 48, + 0, + 0, // Skip to: 59262 + /* 59214 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 59217 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 59232 + /* 59222 */ MCD_OPC_CheckPredicate, + 21, + 244, + 176, + 0, // Skip to: 104527 + /* 59227 */ MCD_OPC_Decode, + 132, + 7, + 184, + 2, // Opcode: ABSv16i8 + /* 59232 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 59247 + /* 59237 */ MCD_OPC_CheckPredicate, + 21, + 229, + 176, + 0, // Skip to: 104527 + /* 59242 */ MCD_OPC_Decode, + 214, + 14, + 184, + 2, // Opcode: FCVTMSv4f32 + /* 59247 */ MCD_OPC_FilterValue, + 49, + 219, + 176, + 0, // Skip to: 104527 + /* 59252 */ MCD_OPC_CheckPredicate, + 21, + 214, + 176, + 0, // Skip to: 104527 + /* 59257 */ MCD_OPC_Decode, + 186, + 7, + 205, + 2, // Opcode: ADDVv16i8v + /* 59262 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 59284 + /* 59267 */ MCD_OPC_CheckPredicate, + 21, + 199, + 176, + 0, // Skip to: 104527 + /* 59272 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 192, + 176, + 0, // Skip to: 104527 + /* 59279 */ MCD_OPC_Decode, + 168, + 7, + 179, + 2, // Opcode: ADDPv16i8 + /* 59284 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 59306 + /* 59289 */ MCD_OPC_CheckPredicate, + 21, + 177, + 176, + 0, // Skip to: 104527 + /* 59294 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 170, + 176, + 0, // Skip to: 104527 + /* 59301 */ MCD_OPC_Decode, + 231, + 32, + 179, + 2, // Opcode: SMULLv16i8_v8i16 + /* 59306 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 59328 + /* 59311 */ MCD_OPC_CheckPredicate, + 21, + 155, + 176, + 0, // Skip to: 104527 + /* 59316 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 148, + 176, + 0, // Skip to: 104527 + /* 59323 */ MCD_OPC_Decode, + 180, + 16, + 179, + 2, // Opcode: FMAXNMv4f32 + /* 59328 */ MCD_OPC_FilterValue, + 50, + 33, + 0, + 0, // Skip to: 59366 + /* 59333 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 59336 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 59351 + /* 59341 */ MCD_OPC_CheckPredicate, + 21, + 125, + 176, + 0, // Skip to: 104527 + /* 59346 */ MCD_OPC_Decode, + 176, + 14, + 184, + 2, // Opcode: FCVTASv4f32 + /* 59351 */ MCD_OPC_FilterValue, + 48, + 115, + 176, + 0, // Skip to: 104527 + /* 59356 */ MCD_OPC_CheckPredicate, + 23, + 110, + 176, + 0, // Skip to: 104527 + /* 59361 */ MCD_OPC_Decode, + 170, + 16, + 199, + 2, // Opcode: FMAXNMVv8i16v + /* 59366 */ MCD_OPC_FilterValue, + 51, + 17, + 0, + 0, // Skip to: 59388 + /* 59371 */ MCD_OPC_CheckPredicate, + 21, + 95, + 176, + 0, // Skip to: 104527 + /* 59376 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 88, + 176, + 0, // Skip to: 104527 + /* 59383 */ MCD_OPC_Decode, + 171, + 17, + 187, + 2, // Opcode: FMLAv4f32 + /* 59388 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 59410 + /* 59393 */ MCD_OPC_CheckPredicate, + 21, + 73, + 176, + 0, // Skip to: 104527 + /* 59398 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 66, + 176, + 0, // Skip to: 104527 + /* 59405 */ MCD_OPC_Decode, + 148, + 13, + 179, + 2, // Opcode: FADDv4f32 + /* 59410 */ MCD_OPC_FilterValue, + 54, + 17, + 0, + 0, // Skip to: 59432 + /* 59415 */ MCD_OPC_CheckPredicate, + 21, + 51, + 176, + 0, // Skip to: 104527 + /* 59420 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 44, + 176, + 0, // Skip to: 104527 + /* 59427 */ MCD_OPC_Decode, + 229, + 30, + 184, + 2, // Opcode: SCVTFv4f32 + /* 59432 */ MCD_OPC_FilterValue, + 55, + 17, + 0, + 0, // Skip to: 59454 + /* 59437 */ MCD_OPC_CheckPredicate, + 21, + 29, + 176, + 0, // Skip to: 104527 + /* 59442 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 22, + 176, + 0, // Skip to: 104527 + /* 59449 */ MCD_OPC_Decode, + 129, + 18, + 179, + 2, // Opcode: FMULXv4f32 + /* 59454 */ MCD_OPC_FilterValue, + 56, + 17, + 0, + 0, // Skip to: 59476 + /* 59459 */ MCD_OPC_CheckPredicate, + 21, + 7, + 176, + 0, // Skip to: 104527 + /* 59464 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 0, + 176, + 0, // Skip to: 104527 + /* 59471 */ MCD_OPC_Decode, + 191, + 28, + 179, + 2, // Opcode: PMULLv16i8 + /* 59476 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 59498 + /* 59481 */ MCD_OPC_CheckPredicate, + 21, + 241, + 175, + 0, // Skip to: 104527 + /* 59486 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 234, + 175, + 0, // Skip to: 104527 + /* 59493 */ MCD_OPC_Decode, + 181, + 13, + 179, + 2, // Opcode: FCMEQv4f32 + /* 59498 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 59520 + /* 59503 */ MCD_OPC_CheckPredicate, + 24, + 219, + 175, + 0, // Skip to: 104527 + /* 59508 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 212, + 175, + 0, // Skip to: 104527 + /* 59515 */ MCD_OPC_Decode, + 228, + 18, + 184, + 2, // Opcode: FRINT32Zv4f32 + /* 59520 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 59542 + /* 59525 */ MCD_OPC_CheckPredicate, + 25, + 197, + 175, + 0, // Skip to: 104527 + /* 59530 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 190, + 175, + 0, // Skip to: 104527 + /* 59537 */ MCD_OPC_Decode, + 156, + 17, + 187, + 2, // Opcode: FMLALv8f16 + /* 59542 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 59564 + /* 59547 */ MCD_OPC_CheckPredicate, + 21, + 175, + 175, + 0, // Skip to: 104527 + /* 59552 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 168, + 175, + 0, // Skip to: 104527 + /* 59559 */ MCD_OPC_Decode, + 209, + 16, + 179, + 2, // Opcode: FMAXv4f32 + /* 59564 */ MCD_OPC_FilterValue, + 62, + 33, + 0, + 0, // Skip to: 59602 + /* 59569 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 59572 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 59587 + /* 59577 */ MCD_OPC_CheckPredicate, + 24, + 145, + 175, + 0, // Skip to: 104527 + /* 59582 */ MCD_OPC_Decode, + 238, + 18, + 184, + 2, // Opcode: FRINT64Zv4f32 + /* 59587 */ MCD_OPC_FilterValue, + 48, + 135, + 175, + 0, // Skip to: 104527 + /* 59592 */ MCD_OPC_CheckPredicate, + 23, + 130, + 175, + 0, // Skip to: 104527 + /* 59597 */ MCD_OPC_Decode, + 199, + 16, + 199, + 2, // Opcode: FMAXVv8i16v + /* 59602 */ MCD_OPC_FilterValue, + 63, + 120, + 175, + 0, // Skip to: 104527 + /* 59607 */ MCD_OPC_CheckPredicate, + 21, + 115, + 175, + 0, // Skip to: 104527 + /* 59612 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 108, + 175, + 0, // Skip to: 104527 + /* 59619 */ MCD_OPC_Decode, + 211, + 18, + 179, + 2, // Opcode: FRECPSv4f32 + /* 59624 */ MCD_OPC_FilterValue, + 3, + 131, + 5, + 0, // Skip to: 61040 + /* 59629 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 59632 */ MCD_OPC_FilterValue, + 0, + 220, + 2, + 0, // Skip to: 60369 + /* 59637 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 59640 */ MCD_OPC_FilterValue, + 0, + 107, + 1, + 0, // Skip to: 60008 + /* 59645 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 59648 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 59663 + /* 59653 */ MCD_OPC_CheckPredicate, + 21, + 69, + 175, + 0, // Skip to: 104527 + /* 59658 */ MCD_OPC_Decode, + 198, + 12, + 206, + 2, // Opcode: EXTv16i8 + /* 59663 */ MCD_OPC_FilterValue, + 1, + 59, + 175, + 0, // Skip to: 104527 + /* 59668 */ MCD_OPC_ExtractField, + 11, + 4, // Inst{14-11} ... + /* 59671 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 59686 + /* 59676 */ MCD_OPC_CheckPredicate, + 21, + 46, + 175, + 0, // Skip to: 104527 + /* 59681 */ MCD_OPC_Decode, + 160, + 42, + 179, + 2, // Opcode: UADDLv16i8_v8i16 + /* 59686 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 59708 + /* 59691 */ MCD_OPC_CheckPredicate, + 21, + 31, + 175, + 0, // Skip to: 104527 + /* 59696 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 24, + 175, + 0, // Skip to: 104527 + /* 59703 */ MCD_OPC_Decode, + 164, + 29, + 184, + 2, // Opcode: REV32v16i8 + /* 59708 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 59723 + /* 59713 */ MCD_OPC_CheckPredicate, + 21, + 9, + 175, + 0, // Skip to: 104527 + /* 59718 */ MCD_OPC_Decode, + 176, + 42, + 179, + 2, // Opcode: UADDWv16i8_v8i16 + /* 59723 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 59738 + /* 59728 */ MCD_OPC_CheckPredicate, + 21, + 250, + 174, + 0, // Skip to: 104527 + /* 59733 */ MCD_OPC_Decode, + 222, + 46, + 179, + 2, // Opcode: USUBLv16i8_v8i16 + /* 59738 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 59776 + /* 59743 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 59746 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 59761 + /* 59751 */ MCD_OPC_CheckPredicate, + 21, + 227, + 174, + 0, // Skip to: 104527 + /* 59756 */ MCD_OPC_Decode, + 146, + 42, + 184, + 2, // Opcode: UADDLPv16i8_v8i16 + /* 59761 */ MCD_OPC_FilterValue, + 1, + 217, + 174, + 0, // Skip to: 104527 + /* 59766 */ MCD_OPC_CheckPredicate, + 21, + 212, + 174, + 0, // Skip to: 104527 + /* 59771 */ MCD_OPC_Decode, + 168, + 36, + 193, + 2, // Opcode: SQXTUNv16i8 + /* 59776 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 59791 + /* 59781 */ MCD_OPC_CheckPredicate, + 21, + 197, + 174, + 0, // Skip to: 104527 + /* 59786 */ MCD_OPC_Decode, + 234, + 46, + 179, + 2, // Opcode: USUBWv16i8_v8i16 + /* 59791 */ MCD_OPC_FilterValue, + 7, + 48, + 0, + 0, // Skip to: 59844 + /* 59796 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 59799 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 59814 + /* 59804 */ MCD_OPC_CheckPredicate, + 21, + 174, + 174, + 0, // Skip to: 104527 + /* 59809 */ MCD_OPC_Decode, + 193, + 46, + 193, + 2, // Opcode: USQADDv16i8 + /* 59814 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 59829 + /* 59819 */ MCD_OPC_CheckPredicate, + 21, + 159, + 174, + 0, // Skip to: 104527 + /* 59824 */ MCD_OPC_Decode, + 152, + 31, + 184, + 2, // Opcode: SHLLv16i8 + /* 59829 */ MCD_OPC_FilterValue, + 16, + 149, + 174, + 0, // Skip to: 104527 + /* 59834 */ MCD_OPC_CheckPredicate, + 21, + 144, + 174, + 0, // Skip to: 104527 + /* 59839 */ MCD_OPC_Decode, + 155, + 42, + 199, + 2, // Opcode: UADDLVv16i8v + /* 59844 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 59859 + /* 59849 */ MCD_OPC_CheckPredicate, + 21, + 129, + 174, + 0, // Skip to: 104527 + /* 59854 */ MCD_OPC_Decode, + 140, + 29, + 187, + 2, // Opcode: RADDHNv8i16_v16i8 + /* 59859 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 59897 + /* 59864 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 59867 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 59882 + /* 59872 */ MCD_OPC_CheckPredicate, + 21, + 106, + 174, + 0, // Skip to: 104527 + /* 59877 */ MCD_OPC_Decode, + 232, + 9, + 184, + 2, // Opcode: CLZv16i8 + /* 59882 */ MCD_OPC_FilterValue, + 1, + 96, + 174, + 0, // Skip to: 104527 + /* 59887 */ MCD_OPC_CheckPredicate, + 21, + 91, + 174, + 0, // Skip to: 104527 + /* 59892 */ MCD_OPC_Decode, + 212, + 45, + 193, + 2, // Opcode: UQXTNv16i8 + /* 59897 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 59912 + /* 59902 */ MCD_OPC_CheckPredicate, + 21, + 76, + 174, + 0, // Skip to: 104527 + /* 59907 */ MCD_OPC_Decode, + 224, + 41, + 187, + 2, // Opcode: UABALv16i8_v8i16 + /* 59912 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 59934 + /* 59917 */ MCD_OPC_CheckPredicate, + 21, + 61, + 174, + 0, // Skip to: 104527 + /* 59922 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 54, + 174, + 0, // Skip to: 104527 + /* 59929 */ MCD_OPC_Decode, + 138, + 28, + 184, + 2, // Opcode: NOTv16i8 + /* 59934 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 59949 + /* 59939 */ MCD_OPC_CheckPredicate, + 21, + 39, + 174, + 0, // Skip to: 104527 + /* 59944 */ MCD_OPC_Decode, + 216, + 29, + 187, + 2, // Opcode: RSUBHNv8i16_v16i8 + /* 59949 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 59971 + /* 59954 */ MCD_OPC_CheckPredicate, + 21, + 24, + 174, + 0, // Skip to: 104527 + /* 59959 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 17, + 174, + 0, // Skip to: 104527 + /* 59966 */ MCD_OPC_Decode, + 137, + 42, + 193, + 2, // Opcode: UADALPv16i8_v8i16 + /* 59971 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 59986 + /* 59976 */ MCD_OPC_CheckPredicate, + 21, + 2, + 174, + 0, // Skip to: 104527 + /* 59981 */ MCD_OPC_Decode, + 246, + 41, + 179, + 2, // Opcode: UABDLv16i8_v8i16 + /* 59986 */ MCD_OPC_FilterValue, + 15, + 248, + 173, + 0, // Skip to: 104527 + /* 59991 */ MCD_OPC_CheckPredicate, + 21, + 243, + 173, + 0, // Skip to: 104527 + /* 59996 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 236, + 173, + 0, // Skip to: 104527 + /* 60003 */ MCD_OPC_Decode, + 174, + 34, + 184, + 2, // Opcode: SQNEGv16i8 + /* 60008 */ MCD_OPC_FilterValue, + 1, + 226, + 173, + 0, // Skip to: 104527 + /* 60013 */ MCD_OPC_ExtractField, + 11, + 4, // Inst{14-11} ... + /* 60016 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 60038 + /* 60021 */ MCD_OPC_CheckPredicate, + 21, + 213, + 173, + 0, // Skip to: 104527 + /* 60026 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 206, + 173, + 0, // Skip to: 104527 + /* 60033 */ MCD_OPC_Decode, + 211, + 43, + 187, + 2, // Opcode: UMLALv16i8_v8i16 + /* 60038 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 60076 + /* 60043 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 60046 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 60061 + /* 60051 */ MCD_OPC_CheckPredicate, + 21, + 183, + 173, + 0, // Skip to: 104527 + /* 60056 */ MCD_OPC_Decode, + 255, + 9, + 184, + 2, // Opcode: CMGEv16i8rz + /* 60061 */ MCD_OPC_FilterValue, + 33, + 173, + 173, + 0, // Skip to: 104527 + /* 60066 */ MCD_OPC_CheckPredicate, + 21, + 168, + 173, + 0, // Skip to: 104527 + /* 60071 */ MCD_OPC_Decode, + 248, + 18, + 184, + 2, // Opcode: FRINTAv4f32 + /* 60076 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 60114 + /* 60081 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 60084 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 60099 + /* 60089 */ MCD_OPC_CheckPredicate, + 21, + 145, + 173, + 0, // Skip to: 104527 + /* 60094 */ MCD_OPC_Decode, + 180, + 10, + 184, + 2, // Opcode: CMLEv16i8rz + /* 60099 */ MCD_OPC_FilterValue, + 33, + 135, + 173, + 0, // Skip to: 104527 + /* 60104 */ MCD_OPC_CheckPredicate, + 21, + 130, + 173, + 0, // Skip to: 104527 + /* 60109 */ MCD_OPC_Decode, + 175, + 19, + 184, + 2, // Opcode: FRINTXv4f32 + /* 60114 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 60136 + /* 60119 */ MCD_OPC_CheckPredicate, + 21, + 115, + 173, + 0, // Skip to: 104527 + /* 60124 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 108, + 173, + 0, // Skip to: 104527 + /* 60131 */ MCD_OPC_Decode, + 231, + 43, + 187, + 2, // Opcode: UMLSLv16i8_v8i16 + /* 60136 */ MCD_OPC_FilterValue, + 5, + 48, + 0, + 0, // Skip to: 60189 + /* 60141 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 60144 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 60159 + /* 60149 */ MCD_OPC_CheckPredicate, + 21, + 85, + 173, + 0, // Skip to: 104527 + /* 60154 */ MCD_OPC_Decode, + 130, + 15, + 184, + 2, // Opcode: FCVTNUv4f32 + /* 60159 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 60174 + /* 60164 */ MCD_OPC_CheckPredicate, + 21, + 70, + 173, + 0, // Skip to: 104527 + /* 60169 */ MCD_OPC_Decode, + 149, + 43, + 205, + 2, // Opcode: UMAXVv16i8v + /* 60174 */ MCD_OPC_FilterValue, + 49, + 60, + 173, + 0, // Skip to: 104527 + /* 60179 */ MCD_OPC_CheckPredicate, + 21, + 55, + 173, + 0, // Skip to: 104527 + /* 60184 */ MCD_OPC_Decode, + 182, + 43, + 205, + 2, // Opcode: UMINVv16i8v + /* 60189 */ MCD_OPC_FilterValue, + 7, + 33, + 0, + 0, // Skip to: 60227 + /* 60194 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 60197 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 60212 + /* 60202 */ MCD_OPC_CheckPredicate, + 21, + 32, + 173, + 0, // Skip to: 104527 + /* 60207 */ MCD_OPC_Decode, + 250, + 27, + 184, + 2, // Opcode: NEGv16i8 + /* 60212 */ MCD_OPC_FilterValue, + 33, + 22, + 173, + 0, // Skip to: 104527 + /* 60217 */ MCD_OPC_CheckPredicate, + 21, + 17, + 173, + 0, // Skip to: 104527 + /* 60222 */ MCD_OPC_Decode, + 228, + 14, + 184, + 2, // Opcode: FCVTMUv4f32 + /* 60227 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 60249 + /* 60232 */ MCD_OPC_CheckPredicate, + 21, + 2, + 173, + 0, // Skip to: 104527 + /* 60237 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 251, + 172, + 0, // Skip to: 104527 + /* 60244 */ MCD_OPC_Decode, + 147, + 44, + 179, + 2, // Opcode: UMULLv16i8_v8i16 + /* 60249 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 60287 + /* 60254 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 60257 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 60272 + /* 60262 */ MCD_OPC_CheckPredicate, + 21, + 228, + 172, + 0, // Skip to: 104527 + /* 60267 */ MCD_OPC_Decode, + 190, + 14, + 184, + 2, // Opcode: FCVTAUv4f32 + /* 60272 */ MCD_OPC_FilterValue, + 48, + 218, + 172, + 0, // Skip to: 104527 + /* 60277 */ MCD_OPC_CheckPredicate, + 21, + 213, + 172, + 0, // Skip to: 104527 + /* 60282 */ MCD_OPC_Decode, + 169, + 16, + 207, + 2, // Opcode: FMAXNMVv4i32v + /* 60287 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 60309 + /* 60292 */ MCD_OPC_CheckPredicate, + 21, + 198, + 172, + 0, // Skip to: 104527 + /* 60297 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 191, + 172, + 0, // Skip to: 104527 + /* 60304 */ MCD_OPC_Decode, + 218, + 42, + 184, + 2, // Opcode: UCVTFv4f32 + /* 60309 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 60331 + /* 60314 */ MCD_OPC_CheckPredicate, + 24, + 176, + 172, + 0, // Skip to: 104527 + /* 60319 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 169, + 172, + 0, // Skip to: 104527 + /* 60326 */ MCD_OPC_Decode, + 223, + 18, + 184, + 2, // Opcode: FRINT32Xv4f32 + /* 60331 */ MCD_OPC_FilterValue, + 15, + 159, + 172, + 0, // Skip to: 104527 + /* 60336 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 60339 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 60354 + /* 60344 */ MCD_OPC_CheckPredicate, + 24, + 146, + 172, + 0, // Skip to: 104527 + /* 60349 */ MCD_OPC_Decode, + 233, + 18, + 184, + 2, // Opcode: FRINT64Xv4f32 + /* 60354 */ MCD_OPC_FilterValue, + 48, + 136, + 172, + 0, // Skip to: 104527 + /* 60359 */ MCD_OPC_CheckPredicate, + 21, + 131, + 172, + 0, // Skip to: 104527 + /* 60364 */ MCD_OPC_Decode, + 198, + 16, + 207, + 2, // Opcode: FMAXVv4i32v + /* 60369 */ MCD_OPC_FilterValue, + 1, + 121, + 172, + 0, // Skip to: 104527 + /* 60374 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 60377 */ MCD_OPC_FilterValue, + 0, + 86, + 1, + 0, // Skip to: 60724 + /* 60382 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 60385 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 60476 + /* 60390 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 60393 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 60461 + /* 60398 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 60401 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 60446 + /* 60406 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 60409 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 60431 + /* 60414 */ MCD_OPC_CheckPredicate, + 21, + 76, + 172, + 0, // Skip to: 104527 + /* 60419 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 69, + 172, + 0, // Skip to: 104527 + /* 60426 */ MCD_OPC_Decode, + 188, + 21, + 208, + 2, // Opcode: INSvi64lane + /* 60431 */ MCD_OPC_FilterValue, + 1, + 59, + 172, + 0, // Skip to: 104527 + /* 60436 */ MCD_OPC_CheckPredicate, + 21, + 54, + 172, + 0, // Skip to: 104527 + /* 60441 */ MCD_OPC_Decode, + 186, + 21, + 209, + 2, // Opcode: INSvi32lane + /* 60446 */ MCD_OPC_FilterValue, + 1, + 44, + 172, + 0, // Skip to: 104527 + /* 60451 */ MCD_OPC_CheckPredicate, + 21, + 39, + 172, + 0, // Skip to: 104527 + /* 60456 */ MCD_OPC_Decode, + 184, + 21, + 210, + 2, // Opcode: INSvi16lane + /* 60461 */ MCD_OPC_FilterValue, + 1, + 29, + 172, + 0, // Skip to: 104527 + /* 60466 */ MCD_OPC_CheckPredicate, + 21, + 24, + 172, + 0, // Skip to: 104527 + /* 60471 */ MCD_OPC_Decode, + 190, + 21, + 211, + 2, // Opcode: INSvi8lane + /* 60476 */ MCD_OPC_FilterValue, + 1, + 14, + 172, + 0, // Skip to: 104527 + /* 60481 */ MCD_OPC_ExtractField, + 11, + 4, // Inst{14-11} ... + /* 60484 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 60499 + /* 60489 */ MCD_OPC_CheckPredicate, + 21, + 1, + 172, + 0, // Skip to: 104527 + /* 60494 */ MCD_OPC_Decode, + 242, + 42, + 179, + 2, // Opcode: UHADDv16i8 + /* 60499 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 60514 + /* 60504 */ MCD_OPC_CheckPredicate, + 21, + 242, + 171, + 0, // Skip to: 104527 + /* 60509 */ MCD_OPC_Decode, + 169, + 44, + 179, + 2, // Opcode: UQADDv16i8 + /* 60514 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 60529 + /* 60519 */ MCD_OPC_CheckPredicate, + 21, + 227, + 171, + 0, // Skip to: 104527 + /* 60524 */ MCD_OPC_Decode, + 228, + 45, + 179, + 2, // Opcode: URHADDv16i8 + /* 60529 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 60544 + /* 60534 */ MCD_OPC_CheckPredicate, + 21, + 212, + 171, + 0, // Skip to: 104527 + /* 60539 */ MCD_OPC_Decode, + 179, + 12, + 179, + 2, // Opcode: EORv16i8 + /* 60544 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 60559 + /* 60549 */ MCD_OPC_CheckPredicate, + 21, + 197, + 171, + 0, // Skip to: 104527 + /* 60554 */ MCD_OPC_Decode, + 128, + 43, + 179, + 2, // Opcode: UHSUBv16i8 + /* 60559 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 60574 + /* 60564 */ MCD_OPC_CheckPredicate, + 21, + 182, + 171, + 0, // Skip to: 104527 + /* 60569 */ MCD_OPC_Decode, + 195, + 45, + 179, + 2, // Opcode: UQSUBv16i8 + /* 60574 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 60589 + /* 60579 */ MCD_OPC_CheckPredicate, + 21, + 167, + 171, + 0, // Skip to: 104527 + /* 60584 */ MCD_OPC_Decode, + 158, + 10, + 179, + 2, // Opcode: CMHIv16i8 + /* 60589 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 60604 + /* 60594 */ MCD_OPC_CheckPredicate, + 21, + 152, + 171, + 0, // Skip to: 104527 + /* 60599 */ MCD_OPC_Decode, + 166, + 10, + 179, + 2, // Opcode: CMHSv16i8 + /* 60604 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 60619 + /* 60609 */ MCD_OPC_CheckPredicate, + 21, + 137, + 171, + 0, // Skip to: 104527 + /* 60614 */ MCD_OPC_Decode, + 167, + 46, + 179, + 2, // Opcode: USHLv16i8 + /* 60619 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 60634 + /* 60624 */ MCD_OPC_CheckPredicate, + 21, + 122, + 171, + 0, // Skip to: 104527 + /* 60629 */ MCD_OPC_Decode, + 146, + 45, + 179, + 2, // Opcode: UQSHLv16i8 + /* 60634 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 60649 + /* 60639 */ MCD_OPC_CheckPredicate, + 21, + 107, + 171, + 0, // Skip to: 104527 + /* 60644 */ MCD_OPC_Decode, + 242, + 45, + 179, + 2, // Opcode: URSHLv16i8 + /* 60649 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 60664 + /* 60654 */ MCD_OPC_CheckPredicate, + 21, + 92, + 171, + 0, // Skip to: 104527 + /* 60659 */ MCD_OPC_Decode, + 232, + 44, + 179, + 2, // Opcode: UQRSHLv16i8 + /* 60664 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 60679 + /* 60669 */ MCD_OPC_CheckPredicate, + 21, + 77, + 171, + 0, // Skip to: 104527 + /* 60674 */ MCD_OPC_Decode, + 162, + 43, + 179, + 2, // Opcode: UMAXv16i8 + /* 60679 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 60694 + /* 60684 */ MCD_OPC_CheckPredicate, + 21, + 62, + 171, + 0, // Skip to: 104527 + /* 60689 */ MCD_OPC_Decode, + 195, + 43, + 179, + 2, // Opcode: UMINv16i8 + /* 60694 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 60709 + /* 60699 */ MCD_OPC_CheckPredicate, + 21, + 47, + 171, + 0, // Skip to: 104527 + /* 60704 */ MCD_OPC_Decode, + 128, + 42, + 179, + 2, // Opcode: UABDv16i8 + /* 60709 */ MCD_OPC_FilterValue, + 15, + 37, + 171, + 0, // Skip to: 104527 + /* 60714 */ MCD_OPC_CheckPredicate, + 21, + 32, + 171, + 0, // Skip to: 104527 + /* 60719 */ MCD_OPC_Decode, + 234, + 41, + 187, + 2, // Opcode: UABAv16i8 + /* 60724 */ MCD_OPC_FilterValue, + 1, + 22, + 171, + 0, // Skip to: 104527 + /* 60729 */ MCD_OPC_ExtractField, + 11, + 4, // Inst{14-11} ... + /* 60732 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 60754 + /* 60737 */ MCD_OPC_CheckPredicate, + 21, + 9, + 171, + 0, // Skip to: 104527 + /* 60742 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 2, + 171, + 0, // Skip to: 104527 + /* 60749 */ MCD_OPC_Decode, + 216, + 40, + 179, + 2, // Opcode: SUBv16i8 + /* 60754 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 60776 + /* 60759 */ MCD_OPC_CheckPredicate, + 21, + 243, + 170, + 0, // Skip to: 104527 + /* 60764 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 236, + 170, + 0, // Skip to: 104527 + /* 60771 */ MCD_OPC_Decode, + 238, + 9, + 179, + 2, // Opcode: CMEQv16i8 + /* 60776 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 60798 + /* 60781 */ MCD_OPC_CheckPredicate, + 21, + 221, + 170, + 0, // Skip to: 104527 + /* 60786 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 214, + 170, + 0, // Skip to: 104527 + /* 60793 */ MCD_OPC_Decode, + 166, + 27, + 187, + 2, // Opcode: MLSv16i8 + /* 60798 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 60820 + /* 60803 */ MCD_OPC_CheckPredicate, + 21, + 199, + 170, + 0, // Skip to: 104527 + /* 60808 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 192, + 170, + 0, // Skip to: 104527 + /* 60815 */ MCD_OPC_Decode, + 196, + 28, + 179, + 2, // Opcode: PMULv16i8 + /* 60820 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 60842 + /* 60825 */ MCD_OPC_CheckPredicate, + 21, + 177, + 170, + 0, // Skip to: 104527 + /* 60830 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 170, + 170, + 0, // Skip to: 104527 + /* 60837 */ MCD_OPC_Decode, + 139, + 43, + 179, + 2, // Opcode: UMAXPv16i8 + /* 60842 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 60864 + /* 60847 */ MCD_OPC_CheckPredicate, + 21, + 155, + 170, + 0, // Skip to: 104527 + /* 60852 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 148, + 170, + 0, // Skip to: 104527 + /* 60859 */ MCD_OPC_Decode, + 172, + 43, + 179, + 2, // Opcode: UMINPv16i8 + /* 60864 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 60886 + /* 60869 */ MCD_OPC_CheckPredicate, + 21, + 133, + 170, + 0, // Skip to: 104527 + /* 60874 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 126, + 170, + 0, // Skip to: 104527 + /* 60881 */ MCD_OPC_Decode, + 162, + 16, + 179, + 2, // Opcode: FMAXNMPv4f32 + /* 60886 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 60908 + /* 60891 */ MCD_OPC_CheckPredicate, + 25, + 111, + 170, + 0, // Skip to: 104527 + /* 60896 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 104, + 170, + 0, // Skip to: 104527 + /* 60903 */ MCD_OPC_Decode, + 148, + 17, + 187, + 2, // Opcode: FMLAL2v8f16 + /* 60908 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 60930 + /* 60913 */ MCD_OPC_CheckPredicate, + 21, + 89, + 170, + 0, // Skip to: 104527 + /* 60918 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 82, + 170, + 0, // Skip to: 104527 + /* 60925 */ MCD_OPC_Decode, + 130, + 13, + 179, + 2, // Opcode: FADDPv4f32 + /* 60930 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 60952 + /* 60935 */ MCD_OPC_CheckPredicate, + 21, + 67, + 170, + 0, // Skip to: 104527 + /* 60940 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 60, + 170, + 0, // Skip to: 104527 + /* 60947 */ MCD_OPC_Decode, + 154, + 18, + 179, + 2, // Opcode: FMULv4f32 + /* 60952 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 60974 + /* 60957 */ MCD_OPC_CheckPredicate, + 21, + 45, + 170, + 0, // Skip to: 104527 + /* 60962 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 38, + 170, + 0, // Skip to: 104527 + /* 60969 */ MCD_OPC_Decode, + 203, + 13, + 179, + 2, // Opcode: FCMGEv4f32 + /* 60974 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 60996 + /* 60979 */ MCD_OPC_CheckPredicate, + 21, + 23, + 170, + 0, // Skip to: 104527 + /* 60984 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 16, + 170, + 0, // Skip to: 104527 + /* 60991 */ MCD_OPC_Decode, + 231, + 12, + 179, + 2, // Opcode: FACGEv4f32 + /* 60996 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 61018 + /* 61001 */ MCD_OPC_CheckPredicate, + 21, + 1, + 170, + 0, // Skip to: 104527 + /* 61006 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 250, + 169, + 0, // Skip to: 104527 + /* 61013 */ MCD_OPC_Decode, + 191, + 16, + 179, + 2, // Opcode: FMAXPv4f32 + /* 61018 */ MCD_OPC_FilterValue, + 15, + 240, + 169, + 0, // Skip to: 104527 + /* 61023 */ MCD_OPC_CheckPredicate, + 21, + 235, + 169, + 0, // Skip to: 104527 + /* 61028 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 228, + 169, + 0, // Skip to: 104527 + /* 61035 */ MCD_OPC_Decode, + 131, + 16, + 179, + 2, // Opcode: FDIVv4f32 + /* 61040 */ MCD_OPC_FilterValue, + 6, + 218, + 169, + 0, // Skip to: 104527 + /* 61045 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61048 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 61070 + /* 61053 */ MCD_OPC_CheckPredicate, + 27, + 205, + 169, + 0, // Skip to: 104527 + /* 61058 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 198, + 169, + 0, // Skip to: 104527 + /* 61065 */ MCD_OPC_Decode, + 153, + 12, + 212, + 2, // Opcode: EOR3 + /* 61070 */ MCD_OPC_FilterValue, + 1, + 188, + 169, + 0, // Skip to: 104527 + /* 61075 */ MCD_OPC_CheckPredicate, + 27, + 183, + 169, + 0, // Skip to: 104527 + /* 61080 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 176, + 169, + 0, // Skip to: 104527 + /* 61087 */ MCD_OPC_Decode, + 182, + 8, + 212, + 2, // Opcode: BCAX + /* 61092 */ MCD_OPC_FilterValue, + 9, + 33, + 27, + 0, // Skip to: 68042 + /* 61097 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 61100 */ MCD_OPC_FilterValue, + 0, + 4, + 6, + 0, // Skip to: 62645 + /* 61105 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 61108 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 61130 + /* 61113 */ MCD_OPC_CheckPredicate, + 21, + 145, + 169, + 0, // Skip to: 104527 + /* 61118 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 138, + 169, + 0, // Skip to: 104527 + /* 61125 */ MCD_OPC_Decode, + 165, + 30, + 151, + 2, // Opcode: SADDLv4i16_v4i32 + /* 61130 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 61168 + /* 61135 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61138 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61153 + /* 61143 */ MCD_OPC_CheckPredicate, + 23, + 115, + 169, + 0, // Skip to: 104527 + /* 61148 */ MCD_OPC_Decode, + 179, + 16, + 155, + 2, // Opcode: FMAXNMv4f16 + /* 61153 */ MCD_OPC_FilterValue, + 1, + 105, + 169, + 0, // Skip to: 104527 + /* 61158 */ MCD_OPC_CheckPredicate, + 21, + 100, + 169, + 0, // Skip to: 104527 + /* 61163 */ MCD_OPC_Decode, + 148, + 31, + 155, + 2, // Opcode: SHADDv4i16 + /* 61168 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 61190 + /* 61173 */ MCD_OPC_CheckPredicate, + 21, + 85, + 169, + 0, // Skip to: 104527 + /* 61178 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 78, + 169, + 0, // Skip to: 104527 + /* 61185 */ MCD_OPC_Decode, + 170, + 29, + 156, + 2, // Opcode: REV64v4i16 + /* 61190 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 61228 + /* 61195 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61198 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61213 + /* 61203 */ MCD_OPC_CheckPredicate, + 23, + 55, + 169, + 0, // Skip to: 104527 + /* 61208 */ MCD_OPC_Decode, + 170, + 17, + 176, + 2, // Opcode: FMLAv4f16 + /* 61213 */ MCD_OPC_FilterValue, + 1, + 45, + 169, + 0, // Skip to: 104527 + /* 61218 */ MCD_OPC_CheckPredicate, + 21, + 40, + 169, + 0, // Skip to: 104527 + /* 61223 */ MCD_OPC_Decode, + 155, + 33, + 155, + 2, // Opcode: SQADDv4i16 + /* 61228 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 61250 + /* 61233 */ MCD_OPC_CheckPredicate, + 21, + 25, + 169, + 0, // Skip to: 104527 + /* 61238 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 18, + 169, + 0, // Skip to: 104527 + /* 61245 */ MCD_OPC_Decode, + 180, + 30, + 159, + 2, // Opcode: SADDWv4i16_v4i32 + /* 61250 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 61288 + /* 61255 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61258 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61273 + /* 61263 */ MCD_OPC_CheckPredicate, + 23, + 251, + 168, + 0, // Skip to: 104527 + /* 61268 */ MCD_OPC_Decode, + 147, + 13, + 155, + 2, // Opcode: FADDv4f16 + /* 61273 */ MCD_OPC_FilterValue, + 1, + 241, + 168, + 0, // Skip to: 104527 + /* 61278 */ MCD_OPC_CheckPredicate, + 21, + 236, + 168, + 0, // Skip to: 104527 + /* 61283 */ MCD_OPC_Decode, + 183, + 36, + 155, + 2, // Opcode: SRHADDv4i16 + /* 61288 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 61310 + /* 61293 */ MCD_OPC_CheckPredicate, + 21, + 221, + 168, + 0, // Skip to: 104527 + /* 61298 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 214, + 168, + 0, // Skip to: 104527 + /* 61305 */ MCD_OPC_Decode, + 136, + 47, + 155, + 2, // Opcode: UZP1v4i16 + /* 61310 */ MCD_OPC_FilterValue, + 7, + 33, + 0, + 0, // Skip to: 61348 + /* 61315 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61318 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61333 + /* 61323 */ MCD_OPC_CheckPredicate, + 23, + 191, + 168, + 0, // Skip to: 104527 + /* 61328 */ MCD_OPC_Decode, + 128, + 18, + 155, + 2, // Opcode: FMULXv4f16 + /* 61333 */ MCD_OPC_FilterValue, + 1, + 181, + 168, + 0, // Skip to: 104527 + /* 61338 */ MCD_OPC_CheckPredicate, + 21, + 176, + 168, + 0, // Skip to: 104527 + /* 61343 */ MCD_OPC_Decode, + 235, + 8, + 155, + 2, // Opcode: BICv8i8 + /* 61348 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 61370 + /* 61353 */ MCD_OPC_CheckPredicate, + 21, + 161, + 168, + 0, // Skip to: 104527 + /* 61358 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 154, + 168, + 0, // Skip to: 104527 + /* 61365 */ MCD_OPC_Decode, + 203, + 37, + 151, + 2, // Opcode: SSUBLv4i16_v4i32 + /* 61370 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 61408 + /* 61375 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61378 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61393 + /* 61383 */ MCD_OPC_CheckPredicate, + 23, + 131, + 168, + 0, // Skip to: 104527 + /* 61388 */ MCD_OPC_Decode, + 180, + 13, + 155, + 2, // Opcode: FCMEQv4f16 + /* 61393 */ MCD_OPC_FilterValue, + 1, + 121, + 168, + 0, // Skip to: 104527 + /* 61398 */ MCD_OPC_CheckPredicate, + 21, + 116, + 168, + 0, // Skip to: 104527 + /* 61403 */ MCD_OPC_Decode, + 188, + 31, + 155, + 2, // Opcode: SHSUBv4i16 + /* 61408 */ MCD_OPC_FilterValue, + 10, + 56, + 0, + 0, // Skip to: 61469 + /* 61413 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61416 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61431 + /* 61421 */ MCD_OPC_CheckPredicate, + 21, + 93, + 168, + 0, // Skip to: 104527 + /* 61426 */ MCD_OPC_Decode, + 195, + 41, + 155, + 2, // Opcode: TRN1v4i16 + /* 61431 */ MCD_OPC_FilterValue, + 1, + 83, + 168, + 0, // Skip to: 104527 + /* 61436 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 61439 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61454 + /* 61444 */ MCD_OPC_CheckPredicate, + 21, + 70, + 168, + 0, // Skip to: 104527 + /* 61449 */ MCD_OPC_Decode, + 151, + 30, + 156, + 2, // Opcode: SADDLPv4i16_v2i32 + /* 61454 */ MCD_OPC_FilterValue, + 1, + 60, + 168, + 0, // Skip to: 104527 + /* 61459 */ MCD_OPC_CheckPredicate, + 21, + 55, + 168, + 0, // Skip to: 104527 + /* 61464 */ MCD_OPC_Decode, + 242, + 47, + 161, + 2, // Opcode: XTNv4i16 + /* 61469 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 61491 + /* 61474 */ MCD_OPC_CheckPredicate, + 21, + 40, + 168, + 0, // Skip to: 104527 + /* 61479 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 33, + 168, + 0, // Skip to: 104527 + /* 61486 */ MCD_OPC_Decode, + 143, + 36, + 155, + 2, // Opcode: SQSUBv4i16 + /* 61491 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 61513 + /* 61496 */ MCD_OPC_CheckPredicate, + 21, + 18, + 168, + 0, // Skip to: 104527 + /* 61501 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 11, + 168, + 0, // Skip to: 104527 + /* 61508 */ MCD_OPC_Decode, + 215, + 37, + 159, + 2, // Opcode: SSUBWv4i16_v4i32 + /* 61513 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 61551 + /* 61518 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61521 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61536 + /* 61526 */ MCD_OPC_CheckPredicate, + 23, + 244, + 167, + 0, // Skip to: 104527 + /* 61531 */ MCD_OPC_Decode, + 208, + 16, + 155, + 2, // Opcode: FMAXv4f16 + /* 61536 */ MCD_OPC_FilterValue, + 1, + 234, + 167, + 0, // Skip to: 104527 + /* 61541 */ MCD_OPC_CheckPredicate, + 21, + 229, + 167, + 0, // Skip to: 104527 + /* 61546 */ MCD_OPC_Decode, + 150, + 10, + 155, + 2, // Opcode: CMGTv4i16 + /* 61551 */ MCD_OPC_FilterValue, + 14, + 56, + 0, + 0, // Skip to: 61612 + /* 61556 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61559 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61574 + /* 61564 */ MCD_OPC_CheckPredicate, + 21, + 206, + 167, + 0, // Skip to: 104527 + /* 61569 */ MCD_OPC_Decode, + 131, + 48, + 155, + 2, // Opcode: ZIP1v4i16 + /* 61574 */ MCD_OPC_FilterValue, + 1, + 196, + 167, + 0, // Skip to: 104527 + /* 61579 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 61582 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61597 + /* 61587 */ MCD_OPC_CheckPredicate, + 21, + 183, + 167, + 0, // Skip to: 104527 + /* 61592 */ MCD_OPC_Decode, + 248, + 40, + 166, + 2, // Opcode: SUQADDv4i16 + /* 61597 */ MCD_OPC_FilterValue, + 16, + 173, + 167, + 0, // Skip to: 104527 + /* 61602 */ MCD_OPC_CheckPredicate, + 21, + 168, + 167, + 0, // Skip to: 104527 + /* 61607 */ MCD_OPC_Decode, + 159, + 30, + 213, + 2, // Opcode: SADDLVv4i16v + /* 61612 */ MCD_OPC_FilterValue, + 15, + 33, + 0, + 0, // Skip to: 61650 + /* 61617 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61620 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61635 + /* 61625 */ MCD_OPC_CheckPredicate, + 23, + 145, + 167, + 0, // Skip to: 104527 + /* 61630 */ MCD_OPC_Decode, + 210, + 18, + 155, + 2, // Opcode: FRECPSv4f16 + /* 61635 */ MCD_OPC_FilterValue, + 1, + 135, + 167, + 0, // Skip to: 104527 + /* 61640 */ MCD_OPC_CheckPredicate, + 21, + 130, + 167, + 0, // Skip to: 104527 + /* 61645 */ MCD_OPC_Decode, + 134, + 10, + 155, + 2, // Opcode: CMGEv4i16 + /* 61650 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 61672 + /* 61655 */ MCD_OPC_CheckPredicate, + 21, + 115, + 167, + 0, // Skip to: 104527 + /* 61660 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 108, + 167, + 0, // Skip to: 104527 + /* 61667 */ MCD_OPC_Decode, + 159, + 7, + 170, + 2, // Opcode: ADDHNv4i32_v4i16 + /* 61672 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 61694 + /* 61677 */ MCD_OPC_CheckPredicate, + 21, + 93, + 167, + 0, // Skip to: 104527 + /* 61682 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 86, + 167, + 0, // Skip to: 104527 + /* 61689 */ MCD_OPC_Decode, + 255, + 36, + 155, + 2, // Opcode: SSHLv4i16 + /* 61694 */ MCD_OPC_FilterValue, + 18, + 33, + 0, + 0, // Skip to: 61732 + /* 61699 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 61702 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 61717 + /* 61707 */ MCD_OPC_CheckPredicate, + 21, + 63, + 167, + 0, // Skip to: 104527 + /* 61712 */ MCD_OPC_Decode, + 222, + 9, + 156, + 2, // Opcode: CLSv4i16 + /* 61717 */ MCD_OPC_FilterValue, + 33, + 53, + 167, + 0, // Skip to: 104527 + /* 61722 */ MCD_OPC_CheckPredicate, + 21, + 48, + 167, + 0, // Skip to: 104527 + /* 61727 */ MCD_OPC_Decode, + 158, + 36, + 161, + 2, // Opcode: SQXTNv4i16 + /* 61732 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 61754 + /* 61737 */ MCD_OPC_CheckPredicate, + 21, + 33, + 167, + 0, // Skip to: 104527 + /* 61742 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 26, + 167, + 0, // Skip to: 104527 + /* 61749 */ MCD_OPC_Decode, + 210, + 35, + 155, + 2, // Opcode: SQSHLv4i16 + /* 61754 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 61776 + /* 61759 */ MCD_OPC_CheckPredicate, + 21, + 11, + 167, + 0, // Skip to: 104527 + /* 61764 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 4, + 167, + 0, // Skip to: 104527 + /* 61771 */ MCD_OPC_Decode, + 226, + 29, + 172, + 2, // Opcode: SABALv4i16_v4i32 + /* 61776 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 61798 + /* 61781 */ MCD_OPC_CheckPredicate, + 21, + 245, + 166, + 0, // Skip to: 104527 + /* 61786 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 238, + 166, + 0, // Skip to: 104527 + /* 61793 */ MCD_OPC_Decode, + 211, + 36, + 155, + 2, // Opcode: SRSHLv4i16 + /* 61798 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 61820 + /* 61803 */ MCD_OPC_CheckPredicate, + 21, + 223, + 166, + 0, // Skip to: 104527 + /* 61808 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 216, + 166, + 0, // Skip to: 104527 + /* 61815 */ MCD_OPC_Decode, + 152, + 47, + 155, + 2, // Opcode: UZP2v4i16 + /* 61820 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 61842 + /* 61825 */ MCD_OPC_CheckPredicate, + 21, + 201, + 166, + 0, // Skip to: 104527 + /* 61830 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 194, + 166, + 0, // Skip to: 104527 + /* 61837 */ MCD_OPC_Decode, + 135, + 35, + 155, + 2, // Opcode: SQRSHLv4i16 + /* 61842 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 61864 + /* 61847 */ MCD_OPC_CheckPredicate, + 21, + 179, + 166, + 0, // Skip to: 104527 + /* 61852 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 172, + 166, + 0, // Skip to: 104527 + /* 61859 */ MCD_OPC_Decode, + 176, + 40, + 170, + 2, // Opcode: SUBHNv4i32_v4i16 + /* 61864 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 61886 + /* 61869 */ MCD_OPC_CheckPredicate, + 21, + 157, + 166, + 0, // Skip to: 104527 + /* 61874 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 150, + 166, + 0, // Skip to: 104527 + /* 61881 */ MCD_OPC_Decode, + 245, + 31, + 155, + 2, // Opcode: SMAXv4i16 + /* 61886 */ MCD_OPC_FilterValue, + 26, + 56, + 0, + 0, // Skip to: 61947 + /* 61891 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 61894 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61909 + /* 61899 */ MCD_OPC_CheckPredicate, + 21, + 127, + 166, + 0, // Skip to: 104527 + /* 61904 */ MCD_OPC_Decode, + 211, + 41, + 155, + 2, // Opcode: TRN2v4i16 + /* 61909 */ MCD_OPC_FilterValue, + 1, + 117, + 166, + 0, // Skip to: 104527 + /* 61914 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 61917 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 61932 + /* 61922 */ MCD_OPC_CheckPredicate, + 21, + 104, + 166, + 0, // Skip to: 104527 + /* 61927 */ MCD_OPC_Decode, + 139, + 30, + 166, + 2, // Opcode: SADALPv4i16_v2i32 + /* 61932 */ MCD_OPC_FilterValue, + 1, + 94, + 166, + 0, // Skip to: 104527 + /* 61937 */ MCD_OPC_CheckPredicate, + 21, + 89, + 166, + 0, // Skip to: 104527 + /* 61942 */ MCD_OPC_Decode, + 132, + 15, + 161, + 2, // Opcode: FCVTNv2i32 + /* 61947 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 61969 + /* 61952 */ MCD_OPC_CheckPredicate, + 21, + 74, + 166, + 0, // Skip to: 104527 + /* 61957 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 67, + 166, + 0, // Skip to: 104527 + /* 61964 */ MCD_OPC_Decode, + 151, + 32, + 155, + 2, // Opcode: SMINv4i16 + /* 61969 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 61991 + /* 61974 */ MCD_OPC_CheckPredicate, + 21, + 52, + 166, + 0, // Skip to: 104527 + /* 61979 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 45, + 166, + 0, // Skip to: 104527 + /* 61986 */ MCD_OPC_Decode, + 248, + 29, + 151, + 2, // Opcode: SABDLv4i16_v4i32 + /* 61991 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 62013 + /* 61996 */ MCD_OPC_CheckPredicate, + 21, + 30, + 166, + 0, // Skip to: 104527 + /* 62001 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 23, + 166, + 0, // Skip to: 104527 + /* 62008 */ MCD_OPC_Decode, + 130, + 30, + 155, + 2, // Opcode: SABDv4i16 + /* 62013 */ MCD_OPC_FilterValue, + 30, + 56, + 0, + 0, // Skip to: 62074 + /* 62018 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 62021 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 62036 + /* 62026 */ MCD_OPC_CheckPredicate, + 21, + 0, + 166, + 0, // Skip to: 104527 + /* 62031 */ MCD_OPC_Decode, + 147, + 48, + 155, + 2, // Opcode: ZIP2v4i16 + /* 62036 */ MCD_OPC_FilterValue, + 1, + 246, + 165, + 0, // Skip to: 104527 + /* 62041 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 62044 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 62059 + /* 62049 */ MCD_OPC_CheckPredicate, + 21, + 233, + 165, + 0, // Skip to: 104527 + /* 62054 */ MCD_OPC_Decode, + 132, + 33, + 156, + 2, // Opcode: SQABSv4i16 + /* 62059 */ MCD_OPC_FilterValue, + 1, + 223, + 165, + 0, // Skip to: 104527 + /* 62064 */ MCD_OPC_CheckPredicate, + 21, + 218, + 165, + 0, // Skip to: 104527 + /* 62069 */ MCD_OPC_Decode, + 198, + 14, + 175, + 2, // Opcode: FCVTLv2i32 + /* 62074 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 62096 + /* 62079 */ MCD_OPC_CheckPredicate, + 21, + 203, + 165, + 0, // Skip to: 104527 + /* 62084 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 196, + 165, + 0, // Skip to: 104527 + /* 62091 */ MCD_OPC_Decode, + 236, + 29, + 176, + 2, // Opcode: SABAv4i16 + /* 62096 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 62118 + /* 62101 */ MCD_OPC_CheckPredicate, + 21, + 181, + 165, + 0, // Skip to: 104527 + /* 62106 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 174, + 165, + 0, // Skip to: 104527 + /* 62113 */ MCD_OPC_Decode, + 169, + 32, + 172, + 2, // Opcode: SMLALv4i16_v4i32 + /* 62118 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 62140 + /* 62123 */ MCD_OPC_CheckPredicate, + 21, + 159, + 165, + 0, // Skip to: 104527 + /* 62128 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 152, + 165, + 0, // Skip to: 104527 + /* 62135 */ MCD_OPC_Decode, + 214, + 7, + 155, + 2, // Opcode: ADDv4i16 + /* 62140 */ MCD_OPC_FilterValue, + 34, + 33, + 0, + 0, // Skip to: 62178 + /* 62145 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 62148 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 62163 + /* 62153 */ MCD_OPC_CheckPredicate, + 21, + 129, + 165, + 0, // Skip to: 104527 + /* 62158 */ MCD_OPC_Decode, + 151, + 10, + 156, + 2, // Opcode: CMGTv4i16rz + /* 62163 */ MCD_OPC_FilterValue, + 57, + 119, + 165, + 0, // Skip to: 104527 + /* 62168 */ MCD_OPC_CheckPredicate, + 23, + 114, + 165, + 0, // Skip to: 104527 + /* 62173 */ MCD_OPC_Decode, + 152, + 19, + 156, + 2, // Opcode: FRINTNv4f16 + /* 62178 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 62200 + /* 62183 */ MCD_OPC_CheckPredicate, + 21, + 99, + 165, + 0, // Skip to: 104527 + /* 62188 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 92, + 165, + 0, // Skip to: 104527 + /* 62195 */ MCD_OPC_Decode, + 166, + 11, + 155, + 2, // Opcode: CMTSTv4i16 + /* 62200 */ MCD_OPC_FilterValue, + 36, + 17, + 0, + 0, // Skip to: 62222 + /* 62205 */ MCD_OPC_CheckPredicate, + 21, + 77, + 165, + 0, // Skip to: 104527 + /* 62210 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 70, + 165, + 0, // Skip to: 104527 + /* 62217 */ MCD_OPC_Decode, + 205, + 33, + 172, + 2, // Opcode: SQDMLALv4i16_v4i32 + /* 62222 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 62244 + /* 62227 */ MCD_OPC_CheckPredicate, + 21, + 55, + 165, + 0, // Skip to: 104527 + /* 62232 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 48, + 165, + 0, // Skip to: 104527 + /* 62239 */ MCD_OPC_Decode, + 152, + 27, + 176, + 2, // Opcode: MLAv4i16 + /* 62244 */ MCD_OPC_FilterValue, + 38, + 33, + 0, + 0, // Skip to: 62282 + /* 62249 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 62252 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 62267 + /* 62257 */ MCD_OPC_CheckPredicate, + 21, + 25, + 165, + 0, // Skip to: 104527 + /* 62262 */ MCD_OPC_Decode, + 247, + 9, + 156, + 2, // Opcode: CMEQv4i16rz + /* 62267 */ MCD_OPC_FilterValue, + 57, + 15, + 165, + 0, // Skip to: 104527 + /* 62272 */ MCD_OPC_CheckPredicate, + 23, + 10, + 165, + 0, // Skip to: 104527 + /* 62277 */ MCD_OPC_Decode, + 141, + 19, + 156, + 2, // Opcode: FRINTMv4f16 + /* 62282 */ MCD_OPC_FilterValue, + 39, + 17, + 0, + 0, // Skip to: 62304 + /* 62287 */ MCD_OPC_CheckPredicate, + 21, + 251, + 164, + 0, // Skip to: 104527 + /* 62292 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 244, + 164, + 0, // Skip to: 104527 + /* 62299 */ MCD_OPC_Decode, + 230, + 27, + 155, + 2, // Opcode: MULv4i16 + /* 62304 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 62326 + /* 62309 */ MCD_OPC_CheckPredicate, + 21, + 229, + 164, + 0, // Skip to: 104527 + /* 62314 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 222, + 164, + 0, // Skip to: 104527 + /* 62321 */ MCD_OPC_Decode, + 189, + 32, + 172, + 2, // Opcode: SMLSLv4i16_v4i32 + /* 62326 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 62348 + /* 62331 */ MCD_OPC_CheckPredicate, + 21, + 207, + 164, + 0, // Skip to: 104527 + /* 62336 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 200, + 164, + 0, // Skip to: 104527 + /* 62343 */ MCD_OPC_Decode, + 222, + 31, + 155, + 2, // Opcode: SMAXPv4i16 + /* 62348 */ MCD_OPC_FilterValue, + 42, + 63, + 0, + 0, // Skip to: 62416 + /* 62353 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 62356 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 62371 + /* 62361 */ MCD_OPC_CheckPredicate, + 21, + 177, + 164, + 0, // Skip to: 104527 + /* 62366 */ MCD_OPC_Decode, + 192, + 10, + 156, + 2, // Opcode: CMLTv4i16rz + /* 62371 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 62386 + /* 62376 */ MCD_OPC_CheckPredicate, + 21, + 162, + 164, + 0, // Skip to: 104527 + /* 62381 */ MCD_OPC_Decode, + 231, + 31, + 167, + 2, // Opcode: SMAXVv4i16v + /* 62386 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 62401 + /* 62391 */ MCD_OPC_CheckPredicate, + 21, + 147, + 164, + 0, // Skip to: 104527 + /* 62396 */ MCD_OPC_Decode, + 137, + 32, + 167, + 2, // Opcode: SMINVv4i16v + /* 62401 */ MCD_OPC_FilterValue, + 57, + 137, + 164, + 0, // Skip to: 104527 + /* 62406 */ MCD_OPC_CheckPredicate, + 23, + 132, + 164, + 0, // Skip to: 104527 + /* 62411 */ MCD_OPC_Decode, + 241, + 14, + 156, + 2, // Opcode: FCVTNSv4f16 + /* 62416 */ MCD_OPC_FilterValue, + 43, + 17, + 0, + 0, // Skip to: 62438 + /* 62421 */ MCD_OPC_CheckPredicate, + 21, + 117, + 164, + 0, // Skip to: 104527 + /* 62426 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 110, + 164, + 0, // Skip to: 104527 + /* 62433 */ MCD_OPC_Decode, + 128, + 32, + 155, + 2, // Opcode: SMINPv4i16 + /* 62438 */ MCD_OPC_FilterValue, + 44, + 17, + 0, + 0, // Skip to: 62460 + /* 62443 */ MCD_OPC_CheckPredicate, + 21, + 95, + 164, + 0, // Skip to: 104527 + /* 62448 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 88, + 164, + 0, // Skip to: 104527 + /* 62455 */ MCD_OPC_Decode, + 230, + 33, + 172, + 2, // Opcode: SQDMLSLv4i16_v4i32 + /* 62460 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 62482 + /* 62465 */ MCD_OPC_CheckPredicate, + 21, + 73, + 164, + 0, // Skip to: 104527 + /* 62470 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 66, + 164, + 0, // Skip to: 104527 + /* 62477 */ MCD_OPC_Decode, + 248, + 33, + 155, + 2, // Opcode: SQDMULHv4i16 + /* 62482 */ MCD_OPC_FilterValue, + 46, + 48, + 0, + 0, // Skip to: 62535 + /* 62487 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 62490 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 62505 + /* 62495 */ MCD_OPC_CheckPredicate, + 21, + 43, + 164, + 0, // Skip to: 104527 + /* 62500 */ MCD_OPC_Decode, + 136, + 7, + 156, + 2, // Opcode: ABSv4i16 + /* 62505 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 62520 + /* 62510 */ MCD_OPC_CheckPredicate, + 21, + 28, + 164, + 0, // Skip to: 104527 + /* 62515 */ MCD_OPC_Decode, + 187, + 7, + 167, + 2, // Opcode: ADDVv4i16v + /* 62520 */ MCD_OPC_FilterValue, + 57, + 18, + 164, + 0, // Skip to: 104527 + /* 62525 */ MCD_OPC_CheckPredicate, + 23, + 13, + 164, + 0, // Skip to: 104527 + /* 62530 */ MCD_OPC_Decode, + 213, + 14, + 156, + 2, // Opcode: FCVTMSv4f16 + /* 62535 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 62557 + /* 62540 */ MCD_OPC_CheckPredicate, + 21, + 254, + 163, + 0, // Skip to: 104527 + /* 62545 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 247, + 163, + 0, // Skip to: 104527 + /* 62552 */ MCD_OPC_Decode, + 172, + 7, + 155, + 2, // Opcode: ADDPv4i16 + /* 62557 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 62579 + /* 62562 */ MCD_OPC_CheckPredicate, + 21, + 232, + 163, + 0, // Skip to: 104527 + /* 62567 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 225, + 163, + 0, // Skip to: 104527 + /* 62574 */ MCD_OPC_Decode, + 235, + 32, + 151, + 2, // Opcode: SMULLv4i16_v4i32 + /* 62579 */ MCD_OPC_FilterValue, + 50, + 17, + 0, + 0, // Skip to: 62601 + /* 62584 */ MCD_OPC_CheckPredicate, + 23, + 210, + 163, + 0, // Skip to: 104527 + /* 62589 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 203, + 163, + 0, // Skip to: 104527 + /* 62596 */ MCD_OPC_Decode, + 175, + 14, + 156, + 2, // Opcode: FCVTASv4f16 + /* 62601 */ MCD_OPC_FilterValue, + 52, + 17, + 0, + 0, // Skip to: 62623 + /* 62606 */ MCD_OPC_CheckPredicate, + 21, + 188, + 163, + 0, // Skip to: 104527 + /* 62611 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 181, + 163, + 0, // Skip to: 104527 + /* 62618 */ MCD_OPC_Decode, + 143, + 34, + 151, + 2, // Opcode: SQDMULLv4i16_v4i32 + /* 62623 */ MCD_OPC_FilterValue, + 54, + 171, + 163, + 0, // Skip to: 104527 + /* 62628 */ MCD_OPC_CheckPredicate, + 23, + 166, + 163, + 0, // Skip to: 104527 + /* 62633 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 159, + 163, + 0, // Skip to: 104527 + /* 62640 */ MCD_OPC_Decode, + 228, + 30, + 156, + 2, // Opcode: SCVTFv4f16 + /* 62645 */ MCD_OPC_FilterValue, + 1, + 182, + 5, + 0, // Skip to: 64112 + /* 62650 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 62653 */ MCD_OPC_FilterValue, + 0, + 205, + 0, + 0, // Skip to: 62863 + /* 62658 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 62661 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 62683 + /* 62666 */ MCD_OPC_CheckPredicate, + 21, + 128, + 163, + 0, // Skip to: 104527 + /* 62671 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 121, + 163, + 0, // Skip to: 104527 + /* 62678 */ MCD_OPC_Decode, + 162, + 42, + 151, + 2, // Opcode: UADDLv4i16_v4i32 + /* 62683 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 62721 + /* 62688 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 62691 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 62706 + /* 62696 */ MCD_OPC_CheckPredicate, + 23, + 98, + 163, + 0, // Skip to: 104527 + /* 62701 */ MCD_OPC_Decode, + 161, + 16, + 155, + 2, // Opcode: FMAXNMPv4f16 + /* 62706 */ MCD_OPC_FilterValue, + 1, + 88, + 163, + 0, // Skip to: 104527 + /* 62711 */ MCD_OPC_CheckPredicate, + 21, + 83, + 163, + 0, // Skip to: 104527 + /* 62716 */ MCD_OPC_Decode, + 244, + 42, + 155, + 2, // Opcode: UHADDv4i16 + /* 62721 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 62743 + /* 62726 */ MCD_OPC_CheckPredicate, + 21, + 68, + 163, + 0, // Skip to: 104527 + /* 62731 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 61, + 163, + 0, // Skip to: 104527 + /* 62738 */ MCD_OPC_Decode, + 165, + 29, + 156, + 2, // Opcode: REV32v4i16 + /* 62743 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 62765 + /* 62748 */ MCD_OPC_CheckPredicate, + 21, + 46, + 163, + 0, // Skip to: 104527 + /* 62753 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 39, + 163, + 0, // Skip to: 104527 + /* 62760 */ MCD_OPC_Decode, + 176, + 44, + 155, + 2, // Opcode: UQADDv4i16 + /* 62765 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 62787 + /* 62770 */ MCD_OPC_CheckPredicate, + 21, + 24, + 163, + 0, // Skip to: 104527 + /* 62775 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 17, + 163, + 0, // Skip to: 104527 + /* 62782 */ MCD_OPC_Decode, + 178, + 42, + 159, + 2, // Opcode: UADDWv4i16_v4i32 + /* 62787 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 62825 + /* 62792 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 62795 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 62810 + /* 62800 */ MCD_OPC_CheckPredicate, + 23, + 250, + 162, + 0, // Skip to: 104527 + /* 62805 */ MCD_OPC_Decode, + 129, + 13, + 155, + 2, // Opcode: FADDPv4f16 + /* 62810 */ MCD_OPC_FilterValue, + 1, + 240, + 162, + 0, // Skip to: 104527 + /* 62815 */ MCD_OPC_CheckPredicate, + 21, + 235, + 162, + 0, // Skip to: 104527 + /* 62820 */ MCD_OPC_Decode, + 230, + 45, + 155, + 2, // Opcode: URHADDv4i16 + /* 62825 */ MCD_OPC_FilterValue, + 7, + 225, + 162, + 0, // Skip to: 104527 + /* 62830 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 62833 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 62848 + /* 62838 */ MCD_OPC_CheckPredicate, + 23, + 212, + 162, + 0, // Skip to: 104527 + /* 62843 */ MCD_OPC_Decode, + 153, + 18, + 155, + 2, // Opcode: FMULv4f16 + /* 62848 */ MCD_OPC_FilterValue, + 1, + 202, + 162, + 0, // Skip to: 104527 + /* 62853 */ MCD_OPC_CheckPredicate, + 21, + 197, + 162, + 0, // Skip to: 104527 + /* 62858 */ MCD_OPC_Decode, + 142, + 9, + 176, + 2, // Opcode: BSLv8i8 + /* 62863 */ MCD_OPC_FilterValue, + 1, + 34, + 1, + 0, // Skip to: 63158 + /* 62868 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 62871 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 62893 + /* 62876 */ MCD_OPC_CheckPredicate, + 21, + 174, + 162, + 0, // Skip to: 104527 + /* 62881 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 167, + 162, + 0, // Skip to: 104527 + /* 62888 */ MCD_OPC_Decode, + 224, + 46, + 151, + 2, // Opcode: USUBLv4i16_v4i32 + /* 62893 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 62931 + /* 62898 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 62901 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 62916 + /* 62906 */ MCD_OPC_CheckPredicate, + 23, + 144, + 162, + 0, // Skip to: 104527 + /* 62911 */ MCD_OPC_Decode, + 202, + 13, + 155, + 2, // Opcode: FCMGEv4f16 + /* 62916 */ MCD_OPC_FilterValue, + 1, + 134, + 162, + 0, // Skip to: 104527 + /* 62921 */ MCD_OPC_CheckPredicate, + 21, + 129, + 162, + 0, // Skip to: 104527 + /* 62926 */ MCD_OPC_Decode, + 130, + 43, + 155, + 2, // Opcode: UHSUBv4i16 + /* 62931 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 62969 + /* 62936 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 62939 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 62954 + /* 62944 */ MCD_OPC_CheckPredicate, + 21, + 106, + 162, + 0, // Skip to: 104527 + /* 62949 */ MCD_OPC_Decode, + 148, + 42, + 156, + 2, // Opcode: UADDLPv4i16_v2i32 + /* 62954 */ MCD_OPC_FilterValue, + 33, + 96, + 162, + 0, // Skip to: 104527 + /* 62959 */ MCD_OPC_CheckPredicate, + 21, + 91, + 162, + 0, // Skip to: 104527 + /* 62964 */ MCD_OPC_Decode, + 173, + 36, + 161, + 2, // Opcode: SQXTUNv4i16 + /* 62969 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 63007 + /* 62974 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 62977 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 62992 + /* 62982 */ MCD_OPC_CheckPredicate, + 23, + 68, + 162, + 0, // Skip to: 104527 + /* 62987 */ MCD_OPC_Decode, + 230, + 12, + 155, + 2, // Opcode: FACGEv4f16 + /* 62992 */ MCD_OPC_FilterValue, + 1, + 58, + 162, + 0, // Skip to: 104527 + /* 62997 */ MCD_OPC_CheckPredicate, + 21, + 53, + 162, + 0, // Skip to: 104527 + /* 63002 */ MCD_OPC_Decode, + 202, + 45, + 155, + 2, // Opcode: UQSUBv4i16 + /* 63007 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 63029 + /* 63012 */ MCD_OPC_CheckPredicate, + 21, + 38, + 162, + 0, // Skip to: 104527 + /* 63017 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 31, + 162, + 0, // Skip to: 104527 + /* 63024 */ MCD_OPC_Decode, + 236, + 46, + 159, + 2, // Opcode: USUBWv4i16_v4i32 + /* 63029 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 63067 + /* 63034 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 63037 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 63052 + /* 63042 */ MCD_OPC_CheckPredicate, + 23, + 8, + 162, + 0, // Skip to: 104527 + /* 63047 */ MCD_OPC_Decode, + 190, + 16, + 155, + 2, // Opcode: FMAXPv4f16 + /* 63052 */ MCD_OPC_FilterValue, + 1, + 254, + 161, + 0, // Skip to: 104527 + /* 63057 */ MCD_OPC_CheckPredicate, + 21, + 249, + 161, + 0, // Skip to: 104527 + /* 63062 */ MCD_OPC_Decode, + 162, + 10, + 155, + 2, // Opcode: CMHIv4i16 + /* 63067 */ MCD_OPC_FilterValue, + 6, + 48, + 0, + 0, // Skip to: 63120 + /* 63072 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 63075 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 63090 + /* 63080 */ MCD_OPC_CheckPredicate, + 21, + 226, + 161, + 0, // Skip to: 104527 + /* 63085 */ MCD_OPC_Decode, + 200, + 46, + 166, + 2, // Opcode: USQADDv4i16 + /* 63090 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 63105 + /* 63095 */ MCD_OPC_CheckPredicate, + 21, + 211, + 161, + 0, // Skip to: 104527 + /* 63100 */ MCD_OPC_Decode, + 154, + 31, + 175, + 2, // Opcode: SHLLv4i16 + /* 63105 */ MCD_OPC_FilterValue, + 48, + 201, + 161, + 0, // Skip to: 104527 + /* 63110 */ MCD_OPC_CheckPredicate, + 21, + 196, + 161, + 0, // Skip to: 104527 + /* 63115 */ MCD_OPC_Decode, + 156, + 42, + 213, + 2, // Opcode: UADDLVv4i16v + /* 63120 */ MCD_OPC_FilterValue, + 7, + 186, + 161, + 0, // Skip to: 104527 + /* 63125 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 63128 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 63143 + /* 63133 */ MCD_OPC_CheckPredicate, + 23, + 173, + 161, + 0, // Skip to: 104527 + /* 63138 */ MCD_OPC_Decode, + 130, + 16, + 155, + 2, // Opcode: FDIVv4f16 + /* 63143 */ MCD_OPC_FilterValue, + 1, + 163, + 161, + 0, // Skip to: 104527 + /* 63148 */ MCD_OPC_CheckPredicate, + 21, + 158, + 161, + 0, // Skip to: 104527 + /* 63153 */ MCD_OPC_Decode, + 170, + 10, + 155, + 2, // Opcode: CMHSv4i16 + /* 63158 */ MCD_OPC_FilterValue, + 2, + 195, + 0, + 0, // Skip to: 63358 + /* 63163 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 63166 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 63188 + /* 63171 */ MCD_OPC_CheckPredicate, + 21, + 135, + 161, + 0, // Skip to: 104527 + /* 63176 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 128, + 161, + 0, // Skip to: 104527 + /* 63183 */ MCD_OPC_Decode, + 138, + 29, + 170, + 2, // Opcode: RADDHNv4i32_v4i16 + /* 63188 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 63210 + /* 63193 */ MCD_OPC_CheckPredicate, + 21, + 113, + 161, + 0, // Skip to: 104527 + /* 63198 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 106, + 161, + 0, // Skip to: 104527 + /* 63205 */ MCD_OPC_Decode, + 171, + 46, + 155, + 2, // Opcode: USHLv4i16 + /* 63210 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 63248 + /* 63215 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 63218 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 63233 + /* 63223 */ MCD_OPC_CheckPredicate, + 21, + 83, + 161, + 0, // Skip to: 104527 + /* 63228 */ MCD_OPC_Decode, + 234, + 9, + 156, + 2, // Opcode: CLZv4i16 + /* 63233 */ MCD_OPC_FilterValue, + 33, + 73, + 161, + 0, // Skip to: 104527 + /* 63238 */ MCD_OPC_CheckPredicate, + 21, + 68, + 161, + 0, // Skip to: 104527 + /* 63243 */ MCD_OPC_Decode, + 217, + 45, + 161, + 2, // Opcode: UQXTNv4i16 + /* 63248 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 63270 + /* 63253 */ MCD_OPC_CheckPredicate, + 21, + 53, + 161, + 0, // Skip to: 104527 + /* 63258 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 46, + 161, + 0, // Skip to: 104527 + /* 63265 */ MCD_OPC_Decode, + 156, + 45, + 155, + 2, // Opcode: UQSHLv4i16 + /* 63270 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 63292 + /* 63275 */ MCD_OPC_CheckPredicate, + 21, + 31, + 161, + 0, // Skip to: 104527 + /* 63280 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 24, + 161, + 0, // Skip to: 104527 + /* 63287 */ MCD_OPC_Decode, + 226, + 41, + 172, + 2, // Opcode: UABALv4i16_v4i32 + /* 63292 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 63314 + /* 63297 */ MCD_OPC_CheckPredicate, + 21, + 9, + 161, + 0, // Skip to: 104527 + /* 63302 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 2, + 161, + 0, // Skip to: 104527 + /* 63309 */ MCD_OPC_Decode, + 246, + 45, + 155, + 2, // Opcode: URSHLv4i16 + /* 63314 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 63336 + /* 63319 */ MCD_OPC_CheckPredicate, + 21, + 243, + 160, + 0, // Skip to: 104527 + /* 63324 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 236, + 160, + 0, // Skip to: 104527 + /* 63331 */ MCD_OPC_Decode, + 151, + 29, + 156, + 2, // Opcode: RBITv8i8 + /* 63336 */ MCD_OPC_FilterValue, + 7, + 226, + 160, + 0, // Skip to: 104527 + /* 63341 */ MCD_OPC_CheckPredicate, + 21, + 221, + 160, + 0, // Skip to: 104527 + /* 63346 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 214, + 160, + 0, // Skip to: 104527 + /* 63353 */ MCD_OPC_Decode, + 239, + 44, + 155, + 2, // Opcode: UQRSHLv4i16 + /* 63358 */ MCD_OPC_FilterValue, + 3, + 195, + 0, + 0, // Skip to: 63558 + /* 63363 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 63366 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 63388 + /* 63371 */ MCD_OPC_CheckPredicate, + 21, + 191, + 160, + 0, // Skip to: 104527 + /* 63376 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 184, + 160, + 0, // Skip to: 104527 + /* 63383 */ MCD_OPC_Decode, + 214, + 29, + 170, + 2, // Opcode: RSUBHNv4i32_v4i16 + /* 63388 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 63410 + /* 63393 */ MCD_OPC_CheckPredicate, + 21, + 169, + 160, + 0, // Skip to: 104527 + /* 63398 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 162, + 160, + 0, // Skip to: 104527 + /* 63405 */ MCD_OPC_Decode, + 164, + 43, + 155, + 2, // Opcode: UMAXv4i16 + /* 63410 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 63448 + /* 63415 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 63418 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 63433 + /* 63423 */ MCD_OPC_CheckPredicate, + 21, + 139, + 160, + 0, // Skip to: 104527 + /* 63428 */ MCD_OPC_Decode, + 139, + 42, + 166, + 2, // Opcode: UADALPv4i16_v2i32 + /* 63433 */ MCD_OPC_FilterValue, + 33, + 129, + 160, + 0, // Skip to: 104527 + /* 63438 */ MCD_OPC_CheckPredicate, + 21, + 124, + 160, + 0, // Skip to: 104527 + /* 63443 */ MCD_OPC_Decode, + 168, + 15, + 161, + 2, // Opcode: FCVTXNv2f32 + /* 63448 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 63470 + /* 63453 */ MCD_OPC_CheckPredicate, + 21, + 109, + 160, + 0, // Skip to: 104527 + /* 63458 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 102, + 160, + 0, // Skip to: 104527 + /* 63465 */ MCD_OPC_Decode, + 197, + 43, + 155, + 2, // Opcode: UMINv4i16 + /* 63470 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 63492 + /* 63475 */ MCD_OPC_CheckPredicate, + 21, + 87, + 160, + 0, // Skip to: 104527 + /* 63480 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 80, + 160, + 0, // Skip to: 104527 + /* 63487 */ MCD_OPC_Decode, + 248, + 41, + 151, + 2, // Opcode: UABDLv4i16_v4i32 + /* 63492 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 63514 + /* 63497 */ MCD_OPC_CheckPredicate, + 21, + 65, + 160, + 0, // Skip to: 104527 + /* 63502 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 58, + 160, + 0, // Skip to: 104527 + /* 63509 */ MCD_OPC_Decode, + 130, + 42, + 155, + 2, // Opcode: UABDv4i16 + /* 63514 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 63536 + /* 63519 */ MCD_OPC_CheckPredicate, + 21, + 43, + 160, + 0, // Skip to: 104527 + /* 63524 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 36, + 160, + 0, // Skip to: 104527 + /* 63531 */ MCD_OPC_Decode, + 181, + 34, + 156, + 2, // Opcode: SQNEGv4i16 + /* 63536 */ MCD_OPC_FilterValue, + 7, + 26, + 160, + 0, // Skip to: 104527 + /* 63541 */ MCD_OPC_CheckPredicate, + 21, + 21, + 160, + 0, // Skip to: 104527 + /* 63546 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 14, + 160, + 0, // Skip to: 104527 + /* 63553 */ MCD_OPC_Decode, + 236, + 41, + 176, + 2, // Opcode: UABAv4i16 + /* 63558 */ MCD_OPC_FilterValue, + 4, + 199, + 0, + 0, // Skip to: 63762 + /* 63563 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 63566 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 63588 + /* 63571 */ MCD_OPC_CheckPredicate, + 21, + 247, + 159, + 0, // Skip to: 104527 + /* 63576 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 240, + 159, + 0, // Skip to: 104527 + /* 63583 */ MCD_OPC_Decode, + 215, + 43, + 172, + 2, // Opcode: UMLALv4i16_v4i32 + /* 63588 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 63626 + /* 63593 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 63596 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 63611 + /* 63601 */ MCD_OPC_CheckPredicate, + 28, + 217, + 159, + 0, // Skip to: 104527 + /* 63606 */ MCD_OPC_Decode, + 204, + 34, + 176, + 2, // Opcode: SQRDMLAHv4i16 + /* 63611 */ MCD_OPC_FilterValue, + 1, + 207, + 159, + 0, // Skip to: 104527 + /* 63616 */ MCD_OPC_CheckPredicate, + 21, + 202, + 159, + 0, // Skip to: 104527 + /* 63621 */ MCD_OPC_Decode, + 220, + 40, + 155, + 2, // Opcode: SUBv4i16 + /* 63626 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 63664 + /* 63631 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 63634 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 63649 + /* 63639 */ MCD_OPC_CheckPredicate, + 21, + 179, + 159, + 0, // Skip to: 104527 + /* 63644 */ MCD_OPC_Decode, + 135, + 10, + 156, + 2, // Opcode: CMGEv4i16rz + /* 63649 */ MCD_OPC_FilterValue, + 57, + 169, + 159, + 0, // Skip to: 104527 + /* 63654 */ MCD_OPC_CheckPredicate, + 23, + 164, + 159, + 0, // Skip to: 104527 + /* 63659 */ MCD_OPC_Decode, + 247, + 18, + 156, + 2, // Opcode: FRINTAv4f16 + /* 63664 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 63702 + /* 63669 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 63672 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 63687 + /* 63677 */ MCD_OPC_CheckPredicate, + 28, + 141, + 159, + 0, // Skip to: 104527 + /* 63682 */ MCD_OPC_Decode, + 223, + 34, + 176, + 2, // Opcode: SQRDMLSHv4i16 + /* 63687 */ MCD_OPC_FilterValue, + 1, + 131, + 159, + 0, // Skip to: 104527 + /* 63692 */ MCD_OPC_CheckPredicate, + 21, + 126, + 159, + 0, // Skip to: 104527 + /* 63697 */ MCD_OPC_Decode, + 246, + 9, + 155, + 2, // Opcode: CMEQv4i16 + /* 63702 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 63724 + /* 63707 */ MCD_OPC_CheckPredicate, + 21, + 111, + 159, + 0, // Skip to: 104527 + /* 63712 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 104, + 159, + 0, // Skip to: 104527 + /* 63719 */ MCD_OPC_Decode, + 169, + 27, + 176, + 2, // Opcode: MLSv4i16 + /* 63724 */ MCD_OPC_FilterValue, + 6, + 94, + 159, + 0, // Skip to: 104527 + /* 63729 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 63732 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 63747 + /* 63737 */ MCD_OPC_CheckPredicate, + 21, + 81, + 159, + 0, // Skip to: 104527 + /* 63742 */ MCD_OPC_Decode, + 184, + 10, + 156, + 2, // Opcode: CMLEv4i16rz + /* 63747 */ MCD_OPC_FilterValue, + 57, + 71, + 159, + 0, // Skip to: 104527 + /* 63752 */ MCD_OPC_CheckPredicate, + 23, + 66, + 159, + 0, // Skip to: 104527 + /* 63757 */ MCD_OPC_Decode, + 174, + 19, + 156, + 2, // Opcode: FRINTXv4f16 + /* 63762 */ MCD_OPC_FilterValue, + 5, + 182, + 0, + 0, // Skip to: 63949 + /* 63767 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 63770 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 63792 + /* 63775 */ MCD_OPC_CheckPredicate, + 21, + 43, + 159, + 0, // Skip to: 104527 + /* 63780 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 36, + 159, + 0, // Skip to: 104527 + /* 63787 */ MCD_OPC_Decode, + 235, + 43, + 172, + 2, // Opcode: UMLSLv4i16_v4i32 + /* 63792 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 63814 + /* 63797 */ MCD_OPC_CheckPredicate, + 21, + 21, + 159, + 0, // Skip to: 104527 + /* 63802 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 14, + 159, + 0, // Skip to: 104527 + /* 63809 */ MCD_OPC_Decode, + 141, + 43, + 155, + 2, // Opcode: UMAXPv4i16 + /* 63814 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 63867 + /* 63819 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 63822 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 63837 + /* 63827 */ MCD_OPC_CheckPredicate, + 21, + 247, + 158, + 0, // Skip to: 104527 + /* 63832 */ MCD_OPC_Decode, + 150, + 43, + 167, + 2, // Opcode: UMAXVv4i16v + /* 63837 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 63852 + /* 63842 */ MCD_OPC_CheckPredicate, + 21, + 232, + 158, + 0, // Skip to: 104527 + /* 63847 */ MCD_OPC_Decode, + 183, + 43, + 167, + 2, // Opcode: UMINVv4i16v + /* 63852 */ MCD_OPC_FilterValue, + 57, + 222, + 158, + 0, // Skip to: 104527 + /* 63857 */ MCD_OPC_CheckPredicate, + 23, + 217, + 158, + 0, // Skip to: 104527 + /* 63862 */ MCD_OPC_Decode, + 129, + 15, + 156, + 2, // Opcode: FCVTNUv4f16 + /* 63867 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 63889 + /* 63872 */ MCD_OPC_CheckPredicate, + 21, + 202, + 158, + 0, // Skip to: 104527 + /* 63877 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 195, + 158, + 0, // Skip to: 104527 + /* 63884 */ MCD_OPC_Decode, + 174, + 43, + 155, + 2, // Opcode: UMINPv4i16 + /* 63889 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 63911 + /* 63894 */ MCD_OPC_CheckPredicate, + 21, + 180, + 158, + 0, // Skip to: 104527 + /* 63899 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 173, + 158, + 0, // Skip to: 104527 + /* 63906 */ MCD_OPC_Decode, + 242, + 34, + 155, + 2, // Opcode: SQRDMULHv4i16 + /* 63911 */ MCD_OPC_FilterValue, + 6, + 163, + 158, + 0, // Skip to: 104527 + /* 63916 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 63919 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 63934 + /* 63924 */ MCD_OPC_CheckPredicate, + 21, + 150, + 158, + 0, // Skip to: 104527 + /* 63929 */ MCD_OPC_Decode, + 254, + 27, + 156, + 2, // Opcode: NEGv4i16 + /* 63934 */ MCD_OPC_FilterValue, + 57, + 140, + 158, + 0, // Skip to: 104527 + /* 63939 */ MCD_OPC_CheckPredicate, + 23, + 135, + 158, + 0, // Skip to: 104527 + /* 63944 */ MCD_OPC_Decode, + 227, + 14, + 156, + 2, // Opcode: FCVTMUv4f16 + /* 63949 */ MCD_OPC_FilterValue, + 6, + 99, + 0, + 0, // Skip to: 64053 + /* 63954 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 63957 */ MCD_OPC_FilterValue, + 0, + 69, + 0, + 0, // Skip to: 64031 + /* 63962 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 63965 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 63987 + /* 63970 */ MCD_OPC_CheckPredicate, + 21, + 104, + 158, + 0, // Skip to: 104527 + /* 63975 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 97, + 158, + 0, // Skip to: 104527 + /* 63982 */ MCD_OPC_Decode, + 151, + 44, + 151, + 2, // Opcode: UMULLv4i16_v4i32 + /* 63987 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 64009 + /* 63992 */ MCD_OPC_CheckPredicate, + 23, + 82, + 158, + 0, // Skip to: 104527 + /* 63997 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 75, + 158, + 0, // Skip to: 104527 + /* 64004 */ MCD_OPC_Decode, + 189, + 14, + 156, + 2, // Opcode: FCVTAUv4f16 + /* 64009 */ MCD_OPC_FilterValue, + 3, + 65, + 158, + 0, // Skip to: 104527 + /* 64014 */ MCD_OPC_CheckPredicate, + 23, + 60, + 158, + 0, // Skip to: 104527 + /* 64019 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 53, + 158, + 0, // Skip to: 104527 + /* 64026 */ MCD_OPC_Decode, + 217, + 42, + 156, + 2, // Opcode: UCVTFv4f16 + /* 64031 */ MCD_OPC_FilterValue, + 1, + 43, + 158, + 0, // Skip to: 104527 + /* 64036 */ MCD_OPC_CheckPredicate, + 29, + 38, + 158, + 0, // Skip to: 104527 + /* 64041 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 31, + 158, + 0, // Skip to: 104527 + /* 64048 */ MCD_OPC_Decode, + 237, + 13, + 214, + 2, // Opcode: FCMLAv4f16 + /* 64053 */ MCD_OPC_FilterValue, + 7, + 21, + 158, + 0, // Skip to: 104527 + /* 64058 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 64061 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 64083 + /* 64066 */ MCD_OPC_CheckPredicate, + 29, + 8, + 158, + 0, // Skip to: 104527 + /* 64071 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 1, + 158, + 0, // Skip to: 104527 + /* 64078 */ MCD_OPC_Decode, + 155, + 13, + 215, + 2, // Opcode: FCADDv4f16 + /* 64083 */ MCD_OPC_FilterValue, + 3, + 247, + 157, + 0, // Skip to: 104527 + /* 64088 */ MCD_OPC_CheckPredicate, + 30, + 242, + 157, + 0, // Skip to: 104527 + /* 64093 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 235, + 157, + 0, // Skip to: 104527 + /* 64100 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 228, + 157, + 0, // Skip to: 104527 + /* 64107 */ MCD_OPC_Decode, + 201, + 8, + 176, + 2, // Opcode: BFDOTv4bf16 + /* 64112 */ MCD_OPC_FilterValue, + 2, + 38, + 7, + 0, // Skip to: 65947 + /* 64117 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 64120 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 64142 + /* 64125 */ MCD_OPC_CheckPredicate, + 21, + 205, + 157, + 0, // Skip to: 104527 + /* 64130 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 198, + 157, + 0, // Skip to: 104527 + /* 64137 */ MCD_OPC_Decode, + 167, + 30, + 179, + 2, // Opcode: SADDLv8i16_v4i32 + /* 64142 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 64180 + /* 64147 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64150 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64165 + /* 64155 */ MCD_OPC_CheckPredicate, + 23, + 175, + 157, + 0, // Skip to: 104527 + /* 64160 */ MCD_OPC_Decode, + 181, + 16, + 179, + 2, // Opcode: FMAXNMv8f16 + /* 64165 */ MCD_OPC_FilterValue, + 1, + 165, + 157, + 0, // Skip to: 104527 + /* 64170 */ MCD_OPC_CheckPredicate, + 21, + 160, + 157, + 0, // Skip to: 104527 + /* 64175 */ MCD_OPC_Decode, + 150, + 31, + 179, + 2, // Opcode: SHADDv8i16 + /* 64180 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 64202 + /* 64185 */ MCD_OPC_CheckPredicate, + 21, + 145, + 157, + 0, // Skip to: 104527 + /* 64190 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 138, + 157, + 0, // Skip to: 104527 + /* 64197 */ MCD_OPC_Decode, + 172, + 29, + 184, + 2, // Opcode: REV64v8i16 + /* 64202 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 64240 + /* 64207 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64210 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64225 + /* 64215 */ MCD_OPC_CheckPredicate, + 23, + 115, + 157, + 0, // Skip to: 104527 + /* 64220 */ MCD_OPC_Decode, + 174, + 17, + 187, + 2, // Opcode: FMLAv8f16 + /* 64225 */ MCD_OPC_FilterValue, + 1, + 105, + 157, + 0, // Skip to: 104527 + /* 64230 */ MCD_OPC_CheckPredicate, + 21, + 100, + 157, + 0, // Skip to: 104527 + /* 64235 */ MCD_OPC_Decode, + 157, + 33, + 179, + 2, // Opcode: SQADDv8i16 + /* 64240 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 64262 + /* 64245 */ MCD_OPC_CheckPredicate, + 21, + 85, + 157, + 0, // Skip to: 104527 + /* 64250 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 78, + 157, + 0, // Skip to: 104527 + /* 64257 */ MCD_OPC_Decode, + 182, + 30, + 179, + 2, // Opcode: SADDWv8i16_v4i32 + /* 64262 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 64300 + /* 64267 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64270 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64285 + /* 64275 */ MCD_OPC_CheckPredicate, + 23, + 55, + 157, + 0, // Skip to: 104527 + /* 64280 */ MCD_OPC_Decode, + 149, + 13, + 179, + 2, // Opcode: FADDv8f16 + /* 64285 */ MCD_OPC_FilterValue, + 1, + 45, + 157, + 0, // Skip to: 104527 + /* 64290 */ MCD_OPC_CheckPredicate, + 21, + 40, + 157, + 0, // Skip to: 104527 + /* 64295 */ MCD_OPC_Decode, + 185, + 36, + 179, + 2, // Opcode: SRHADDv8i16 + /* 64300 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 64322 + /* 64305 */ MCD_OPC_CheckPredicate, + 21, + 25, + 157, + 0, // Skip to: 104527 + /* 64310 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 18, + 157, + 0, // Skip to: 104527 + /* 64317 */ MCD_OPC_Decode, + 138, + 47, + 179, + 2, // Opcode: UZP1v8i16 + /* 64322 */ MCD_OPC_FilterValue, + 7, + 33, + 0, + 0, // Skip to: 64360 + /* 64327 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64330 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64345 + /* 64335 */ MCD_OPC_CheckPredicate, + 23, + 251, + 156, + 0, // Skip to: 104527 + /* 64340 */ MCD_OPC_Decode, + 132, + 18, + 179, + 2, // Opcode: FMULXv8f16 + /* 64345 */ MCD_OPC_FilterValue, + 1, + 241, + 156, + 0, // Skip to: 104527 + /* 64350 */ MCD_OPC_CheckPredicate, + 21, + 236, + 156, + 0, // Skip to: 104527 + /* 64355 */ MCD_OPC_Decode, + 230, + 8, + 179, + 2, // Opcode: BICv16i8 + /* 64360 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 64382 + /* 64365 */ MCD_OPC_CheckPredicate, + 21, + 221, + 156, + 0, // Skip to: 104527 + /* 64370 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 214, + 156, + 0, // Skip to: 104527 + /* 64377 */ MCD_OPC_Decode, + 205, + 37, + 179, + 2, // Opcode: SSUBLv8i16_v4i32 + /* 64382 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 64420 + /* 64387 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64390 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64405 + /* 64395 */ MCD_OPC_CheckPredicate, + 23, + 191, + 156, + 0, // Skip to: 104527 + /* 64400 */ MCD_OPC_Decode, + 184, + 13, + 179, + 2, // Opcode: FCMEQv8f16 + /* 64405 */ MCD_OPC_FilterValue, + 1, + 181, + 156, + 0, // Skip to: 104527 + /* 64410 */ MCD_OPC_CheckPredicate, + 21, + 176, + 156, + 0, // Skip to: 104527 + /* 64415 */ MCD_OPC_Decode, + 190, + 31, + 179, + 2, // Opcode: SHSUBv8i16 + /* 64420 */ MCD_OPC_FilterValue, + 10, + 56, + 0, + 0, // Skip to: 64481 + /* 64425 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64428 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64443 + /* 64433 */ MCD_OPC_CheckPredicate, + 21, + 153, + 156, + 0, // Skip to: 104527 + /* 64438 */ MCD_OPC_Decode, + 197, + 41, + 179, + 2, // Opcode: TRN1v8i16 + /* 64443 */ MCD_OPC_FilterValue, + 1, + 143, + 156, + 0, // Skip to: 104527 + /* 64448 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 64451 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64466 + /* 64456 */ MCD_OPC_CheckPredicate, + 21, + 130, + 156, + 0, // Skip to: 104527 + /* 64461 */ MCD_OPC_Decode, + 153, + 30, + 184, + 2, // Opcode: SADDLPv8i16_v4i32 + /* 64466 */ MCD_OPC_FilterValue, + 1, + 120, + 156, + 0, // Skip to: 104527 + /* 64471 */ MCD_OPC_CheckPredicate, + 21, + 115, + 156, + 0, // Skip to: 104527 + /* 64476 */ MCD_OPC_Decode, + 244, + 47, + 193, + 2, // Opcode: XTNv8i16 + /* 64481 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 64503 + /* 64486 */ MCD_OPC_CheckPredicate, + 21, + 100, + 156, + 0, // Skip to: 104527 + /* 64491 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 93, + 156, + 0, // Skip to: 104527 + /* 64498 */ MCD_OPC_Decode, + 145, + 36, + 179, + 2, // Opcode: SQSUBv8i16 + /* 64503 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 64525 + /* 64508 */ MCD_OPC_CheckPredicate, + 21, + 78, + 156, + 0, // Skip to: 104527 + /* 64513 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 71, + 156, + 0, // Skip to: 104527 + /* 64520 */ MCD_OPC_Decode, + 217, + 37, + 179, + 2, // Opcode: SSUBWv8i16_v4i32 + /* 64525 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 64563 + /* 64530 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64533 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64548 + /* 64538 */ MCD_OPC_CheckPredicate, + 23, + 48, + 156, + 0, // Skip to: 104527 + /* 64543 */ MCD_OPC_Decode, + 210, + 16, + 179, + 2, // Opcode: FMAXv8f16 + /* 64548 */ MCD_OPC_FilterValue, + 1, + 38, + 156, + 0, // Skip to: 104527 + /* 64553 */ MCD_OPC_CheckPredicate, + 21, + 33, + 156, + 0, // Skip to: 104527 + /* 64558 */ MCD_OPC_Decode, + 154, + 10, + 179, + 2, // Opcode: CMGTv8i16 + /* 64563 */ MCD_OPC_FilterValue, + 14, + 56, + 0, + 0, // Skip to: 64624 + /* 64568 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64571 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64586 + /* 64576 */ MCD_OPC_CheckPredicate, + 21, + 10, + 156, + 0, // Skip to: 104527 + /* 64581 */ MCD_OPC_Decode, + 133, + 48, + 179, + 2, // Opcode: ZIP1v8i16 + /* 64586 */ MCD_OPC_FilterValue, + 1, + 0, + 156, + 0, // Skip to: 104527 + /* 64591 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 64594 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64609 + /* 64599 */ MCD_OPC_CheckPredicate, + 21, + 243, + 155, + 0, // Skip to: 104527 + /* 64604 */ MCD_OPC_Decode, + 250, + 40, + 193, + 2, // Opcode: SUQADDv8i16 + /* 64609 */ MCD_OPC_FilterValue, + 16, + 233, + 155, + 0, // Skip to: 104527 + /* 64614 */ MCD_OPC_CheckPredicate, + 21, + 228, + 155, + 0, // Skip to: 104527 + /* 64619 */ MCD_OPC_Decode, + 161, + 30, + 207, + 2, // Opcode: SADDLVv8i16v + /* 64624 */ MCD_OPC_FilterValue, + 15, + 33, + 0, + 0, // Skip to: 64662 + /* 64629 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64632 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64647 + /* 64637 */ MCD_OPC_CheckPredicate, + 23, + 205, + 155, + 0, // Skip to: 104527 + /* 64642 */ MCD_OPC_Decode, + 212, + 18, + 179, + 2, // Opcode: FRECPSv8f16 + /* 64647 */ MCD_OPC_FilterValue, + 1, + 195, + 155, + 0, // Skip to: 104527 + /* 64652 */ MCD_OPC_CheckPredicate, + 21, + 190, + 155, + 0, // Skip to: 104527 + /* 64657 */ MCD_OPC_Decode, + 138, + 10, + 179, + 2, // Opcode: CMGEv8i16 + /* 64662 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 64684 + /* 64667 */ MCD_OPC_CheckPredicate, + 21, + 175, + 155, + 0, // Skip to: 104527 + /* 64672 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 168, + 155, + 0, // Skip to: 104527 + /* 64679 */ MCD_OPC_Decode, + 160, + 7, + 187, + 2, // Opcode: ADDHNv4i32_v8i16 + /* 64684 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 64706 + /* 64689 */ MCD_OPC_CheckPredicate, + 21, + 153, + 155, + 0, // Skip to: 104527 + /* 64694 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 146, + 155, + 0, // Skip to: 104527 + /* 64701 */ MCD_OPC_Decode, + 129, + 37, + 179, + 2, // Opcode: SSHLv8i16 + /* 64706 */ MCD_OPC_FilterValue, + 18, + 33, + 0, + 0, // Skip to: 64744 + /* 64711 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 64714 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 64729 + /* 64719 */ MCD_OPC_CheckPredicate, + 21, + 123, + 155, + 0, // Skip to: 104527 + /* 64724 */ MCD_OPC_Decode, + 224, + 9, + 184, + 2, // Opcode: CLSv8i16 + /* 64729 */ MCD_OPC_FilterValue, + 33, + 113, + 155, + 0, // Skip to: 104527 + /* 64734 */ MCD_OPC_CheckPredicate, + 21, + 108, + 155, + 0, // Skip to: 104527 + /* 64739 */ MCD_OPC_Decode, + 160, + 36, + 193, + 2, // Opcode: SQXTNv8i16 + /* 64744 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 64766 + /* 64749 */ MCD_OPC_CheckPredicate, + 21, + 93, + 155, + 0, // Skip to: 104527 + /* 64754 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 86, + 155, + 0, // Skip to: 104527 + /* 64761 */ MCD_OPC_Decode, + 214, + 35, + 179, + 2, // Opcode: SQSHLv8i16 + /* 64766 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 64788 + /* 64771 */ MCD_OPC_CheckPredicate, + 21, + 71, + 155, + 0, // Skip to: 104527 + /* 64776 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 64, + 155, + 0, // Skip to: 104527 + /* 64783 */ MCD_OPC_Decode, + 228, + 29, + 187, + 2, // Opcode: SABALv8i16_v4i32 + /* 64788 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 64810 + /* 64793 */ MCD_OPC_CheckPredicate, + 21, + 49, + 155, + 0, // Skip to: 104527 + /* 64798 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 42, + 155, + 0, // Skip to: 104527 + /* 64805 */ MCD_OPC_Decode, + 213, + 36, + 179, + 2, // Opcode: SRSHLv8i16 + /* 64810 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 64832 + /* 64815 */ MCD_OPC_CheckPredicate, + 21, + 27, + 155, + 0, // Skip to: 104527 + /* 64820 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 20, + 155, + 0, // Skip to: 104527 + /* 64827 */ MCD_OPC_Decode, + 154, + 47, + 179, + 2, // Opcode: UZP2v8i16 + /* 64832 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 64854 + /* 64837 */ MCD_OPC_CheckPredicate, + 21, + 5, + 155, + 0, // Skip to: 104527 + /* 64842 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 254, + 154, + 0, // Skip to: 104527 + /* 64849 */ MCD_OPC_Decode, + 137, + 35, + 179, + 2, // Opcode: SQRSHLv8i16 + /* 64854 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 64876 + /* 64859 */ MCD_OPC_CheckPredicate, + 21, + 239, + 154, + 0, // Skip to: 104527 + /* 64864 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 232, + 154, + 0, // Skip to: 104527 + /* 64871 */ MCD_OPC_Decode, + 177, + 40, + 187, + 2, // Opcode: SUBHNv4i32_v8i16 + /* 64876 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 64898 + /* 64881 */ MCD_OPC_CheckPredicate, + 21, + 217, + 154, + 0, // Skip to: 104527 + /* 64886 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 210, + 154, + 0, // Skip to: 104527 + /* 64893 */ MCD_OPC_Decode, + 247, + 31, + 179, + 2, // Opcode: SMAXv8i16 + /* 64898 */ MCD_OPC_FilterValue, + 26, + 56, + 0, + 0, // Skip to: 64959 + /* 64903 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 64906 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64921 + /* 64911 */ MCD_OPC_CheckPredicate, + 21, + 187, + 154, + 0, // Skip to: 104527 + /* 64916 */ MCD_OPC_Decode, + 213, + 41, + 179, + 2, // Opcode: TRN2v8i16 + /* 64921 */ MCD_OPC_FilterValue, + 1, + 177, + 154, + 0, // Skip to: 104527 + /* 64926 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 64929 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 64944 + /* 64934 */ MCD_OPC_CheckPredicate, + 21, + 164, + 154, + 0, // Skip to: 104527 + /* 64939 */ MCD_OPC_Decode, + 141, + 30, + 193, + 2, // Opcode: SADALPv8i16_v4i32 + /* 64944 */ MCD_OPC_FilterValue, + 1, + 154, + 154, + 0, // Skip to: 104527 + /* 64949 */ MCD_OPC_CheckPredicate, + 21, + 149, + 154, + 0, // Skip to: 104527 + /* 64954 */ MCD_OPC_Decode, + 134, + 15, + 193, + 2, // Opcode: FCVTNv4i32 + /* 64959 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 64981 + /* 64964 */ MCD_OPC_CheckPredicate, + 21, + 134, + 154, + 0, // Skip to: 104527 + /* 64969 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 127, + 154, + 0, // Skip to: 104527 + /* 64976 */ MCD_OPC_Decode, + 153, + 32, + 179, + 2, // Opcode: SMINv8i16 + /* 64981 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 65003 + /* 64986 */ MCD_OPC_CheckPredicate, + 21, + 112, + 154, + 0, // Skip to: 104527 + /* 64991 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 105, + 154, + 0, // Skip to: 104527 + /* 64998 */ MCD_OPC_Decode, + 250, + 29, + 179, + 2, // Opcode: SABDLv8i16_v4i32 + /* 65003 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 65025 + /* 65008 */ MCD_OPC_CheckPredicate, + 21, + 90, + 154, + 0, // Skip to: 104527 + /* 65013 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 83, + 154, + 0, // Skip to: 104527 + /* 65020 */ MCD_OPC_Decode, + 132, + 30, + 179, + 2, // Opcode: SABDv8i16 + /* 65025 */ MCD_OPC_FilterValue, + 30, + 56, + 0, + 0, // Skip to: 65086 + /* 65030 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 65033 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 65048 + /* 65038 */ MCD_OPC_CheckPredicate, + 21, + 60, + 154, + 0, // Skip to: 104527 + /* 65043 */ MCD_OPC_Decode, + 149, + 48, + 179, + 2, // Opcode: ZIP2v8i16 + /* 65048 */ MCD_OPC_FilterValue, + 1, + 50, + 154, + 0, // Skip to: 104527 + /* 65053 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 65056 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 65071 + /* 65061 */ MCD_OPC_CheckPredicate, + 21, + 37, + 154, + 0, // Skip to: 104527 + /* 65066 */ MCD_OPC_Decode, + 134, + 33, + 184, + 2, // Opcode: SQABSv8i16 + /* 65071 */ MCD_OPC_FilterValue, + 1, + 27, + 154, + 0, // Skip to: 104527 + /* 65076 */ MCD_OPC_CheckPredicate, + 21, + 22, + 154, + 0, // Skip to: 104527 + /* 65081 */ MCD_OPC_Decode, + 200, + 14, + 184, + 2, // Opcode: FCVTLv4i32 + /* 65086 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 65108 + /* 65091 */ MCD_OPC_CheckPredicate, + 21, + 7, + 154, + 0, // Skip to: 104527 + /* 65096 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 0, + 154, + 0, // Skip to: 104527 + /* 65103 */ MCD_OPC_Decode, + 238, + 29, + 187, + 2, // Opcode: SABAv8i16 + /* 65108 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 65130 + /* 65113 */ MCD_OPC_CheckPredicate, + 21, + 241, + 153, + 0, // Skip to: 104527 + /* 65118 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 234, + 153, + 0, // Skip to: 104527 + /* 65125 */ MCD_OPC_Decode, + 173, + 32, + 187, + 2, // Opcode: SMLALv8i16_v4i32 + /* 65130 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 65152 + /* 65135 */ MCD_OPC_CheckPredicate, + 21, + 219, + 153, + 0, // Skip to: 104527 + /* 65140 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 212, + 153, + 0, // Skip to: 104527 + /* 65147 */ MCD_OPC_Decode, + 216, + 7, + 179, + 2, // Opcode: ADDv8i16 + /* 65152 */ MCD_OPC_FilterValue, + 34, + 48, + 0, + 0, // Skip to: 65205 + /* 65157 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 65160 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 65175 + /* 65165 */ MCD_OPC_CheckPredicate, + 21, + 189, + 153, + 0, // Skip to: 104527 + /* 65170 */ MCD_OPC_Decode, + 155, + 10, + 184, + 2, // Opcode: CMGTv8i16rz + /* 65175 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 65190 + /* 65180 */ MCD_OPC_CheckPredicate, + 21, + 174, + 153, + 0, // Skip to: 104527 + /* 65185 */ MCD_OPC_Decode, + 151, + 19, + 184, + 2, // Opcode: FRINTNv2f64 + /* 65190 */ MCD_OPC_FilterValue, + 57, + 164, + 153, + 0, // Skip to: 104527 + /* 65195 */ MCD_OPC_CheckPredicate, + 23, + 159, + 153, + 0, // Skip to: 104527 + /* 65200 */ MCD_OPC_Decode, + 154, + 19, + 184, + 2, // Opcode: FRINTNv8f16 + /* 65205 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 65227 + /* 65210 */ MCD_OPC_CheckPredicate, + 21, + 144, + 153, + 0, // Skip to: 104527 + /* 65215 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 137, + 153, + 0, // Skip to: 104527 + /* 65222 */ MCD_OPC_Decode, + 168, + 11, + 179, + 2, // Opcode: CMTSTv8i16 + /* 65227 */ MCD_OPC_FilterValue, + 36, + 17, + 0, + 0, // Skip to: 65249 + /* 65232 */ MCD_OPC_CheckPredicate, + 21, + 122, + 153, + 0, // Skip to: 104527 + /* 65237 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 115, + 153, + 0, // Skip to: 104527 + /* 65244 */ MCD_OPC_Decode, + 209, + 33, + 187, + 2, // Opcode: SQDMLALv8i16_v4i32 + /* 65249 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 65271 + /* 65254 */ MCD_OPC_CheckPredicate, + 21, + 100, + 153, + 0, // Skip to: 104527 + /* 65259 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 93, + 153, + 0, // Skip to: 104527 + /* 65266 */ MCD_OPC_Decode, + 156, + 27, + 187, + 2, // Opcode: MLAv8i16 + /* 65271 */ MCD_OPC_FilterValue, + 38, + 48, + 0, + 0, // Skip to: 65324 + /* 65276 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 65279 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 65294 + /* 65284 */ MCD_OPC_CheckPredicate, + 21, + 70, + 153, + 0, // Skip to: 104527 + /* 65289 */ MCD_OPC_Decode, + 251, + 9, + 184, + 2, // Opcode: CMEQv8i16rz + /* 65294 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 65309 + /* 65299 */ MCD_OPC_CheckPredicate, + 21, + 55, + 153, + 0, // Skip to: 104527 + /* 65304 */ MCD_OPC_Decode, + 140, + 19, + 184, + 2, // Opcode: FRINTMv2f64 + /* 65309 */ MCD_OPC_FilterValue, + 57, + 45, + 153, + 0, // Skip to: 104527 + /* 65314 */ MCD_OPC_CheckPredicate, + 23, + 40, + 153, + 0, // Skip to: 104527 + /* 65319 */ MCD_OPC_Decode, + 143, + 19, + 184, + 2, // Opcode: FRINTMv8f16 + /* 65324 */ MCD_OPC_FilterValue, + 39, + 17, + 0, + 0, // Skip to: 65346 + /* 65329 */ MCD_OPC_CheckPredicate, + 21, + 25, + 153, + 0, // Skip to: 104527 + /* 65334 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 18, + 153, + 0, // Skip to: 104527 + /* 65341 */ MCD_OPC_Decode, + 234, + 27, + 179, + 2, // Opcode: MULv8i16 + /* 65346 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 65368 + /* 65351 */ MCD_OPC_CheckPredicate, + 21, + 3, + 153, + 0, // Skip to: 104527 + /* 65356 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 252, + 152, + 0, // Skip to: 104527 + /* 65363 */ MCD_OPC_Decode, + 193, + 32, + 187, + 2, // Opcode: SMLSLv8i16_v4i32 + /* 65368 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 65390 + /* 65373 */ MCD_OPC_CheckPredicate, + 21, + 237, + 152, + 0, // Skip to: 104527 + /* 65378 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 230, + 152, + 0, // Skip to: 104527 + /* 65385 */ MCD_OPC_Decode, + 224, + 31, + 179, + 2, // Opcode: SMAXPv8i16 + /* 65390 */ MCD_OPC_FilterValue, + 42, + 78, + 0, + 0, // Skip to: 65473 + /* 65395 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 65398 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 65413 + /* 65403 */ MCD_OPC_CheckPredicate, + 21, + 207, + 152, + 0, // Skip to: 104527 + /* 65408 */ MCD_OPC_Decode, + 194, + 10, + 184, + 2, // Opcode: CMLTv8i16rz + /* 65413 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 65428 + /* 65418 */ MCD_OPC_CheckPredicate, + 21, + 192, + 152, + 0, // Skip to: 104527 + /* 65423 */ MCD_OPC_Decode, + 240, + 14, + 184, + 2, // Opcode: FCVTNSv2f64 + /* 65428 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 65443 + /* 65433 */ MCD_OPC_CheckPredicate, + 21, + 177, + 152, + 0, // Skip to: 104527 + /* 65438 */ MCD_OPC_Decode, + 233, + 31, + 199, + 2, // Opcode: SMAXVv8i16v + /* 65443 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 65458 + /* 65448 */ MCD_OPC_CheckPredicate, + 21, + 162, + 152, + 0, // Skip to: 104527 + /* 65453 */ MCD_OPC_Decode, + 139, + 32, + 199, + 2, // Opcode: SMINVv8i16v + /* 65458 */ MCD_OPC_FilterValue, + 57, + 152, + 152, + 0, // Skip to: 104527 + /* 65463 */ MCD_OPC_CheckPredicate, + 23, + 147, + 152, + 0, // Skip to: 104527 + /* 65468 */ MCD_OPC_Decode, + 243, + 14, + 184, + 2, // Opcode: FCVTNSv8f16 + /* 65473 */ MCD_OPC_FilterValue, + 43, + 17, + 0, + 0, // Skip to: 65495 + /* 65478 */ MCD_OPC_CheckPredicate, + 21, + 132, + 152, + 0, // Skip to: 104527 + /* 65483 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 125, + 152, + 0, // Skip to: 104527 + /* 65490 */ MCD_OPC_Decode, + 130, + 32, + 179, + 2, // Opcode: SMINPv8i16 + /* 65495 */ MCD_OPC_FilterValue, + 44, + 17, + 0, + 0, // Skip to: 65517 + /* 65500 */ MCD_OPC_CheckPredicate, + 21, + 110, + 152, + 0, // Skip to: 104527 + /* 65505 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 103, + 152, + 0, // Skip to: 104527 + /* 65512 */ MCD_OPC_Decode, + 234, + 33, + 187, + 2, // Opcode: SQDMLSLv8i16_v4i32 + /* 65517 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 65539 + /* 65522 */ MCD_OPC_CheckPredicate, + 21, + 88, + 152, + 0, // Skip to: 104527 + /* 65527 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 81, + 152, + 0, // Skip to: 104527 + /* 65534 */ MCD_OPC_Decode, + 252, + 33, + 179, + 2, // Opcode: SQDMULHv8i16 + /* 65539 */ MCD_OPC_FilterValue, + 46, + 63, + 0, + 0, // Skip to: 65607 + /* 65544 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 65547 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 65562 + /* 65552 */ MCD_OPC_CheckPredicate, + 21, + 58, + 152, + 0, // Skip to: 104527 + /* 65557 */ MCD_OPC_Decode, + 138, + 7, + 184, + 2, // Opcode: ABSv8i16 + /* 65562 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 65577 + /* 65567 */ MCD_OPC_CheckPredicate, + 21, + 43, + 152, + 0, // Skip to: 104527 + /* 65572 */ MCD_OPC_Decode, + 212, + 14, + 184, + 2, // Opcode: FCVTMSv2f64 + /* 65577 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 65592 + /* 65582 */ MCD_OPC_CheckPredicate, + 21, + 28, + 152, + 0, // Skip to: 104527 + /* 65587 */ MCD_OPC_Decode, + 189, + 7, + 199, + 2, // Opcode: ADDVv8i16v + /* 65592 */ MCD_OPC_FilterValue, + 57, + 18, + 152, + 0, // Skip to: 104527 + /* 65597 */ MCD_OPC_CheckPredicate, + 23, + 13, + 152, + 0, // Skip to: 104527 + /* 65602 */ MCD_OPC_Decode, + 215, + 14, + 184, + 2, // Opcode: FCVTMSv8f16 + /* 65607 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 65629 + /* 65612 */ MCD_OPC_CheckPredicate, + 21, + 254, + 151, + 0, // Skip to: 104527 + /* 65617 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 247, + 151, + 0, // Skip to: 104527 + /* 65624 */ MCD_OPC_Decode, + 174, + 7, + 179, + 2, // Opcode: ADDPv8i16 + /* 65629 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 65651 + /* 65634 */ MCD_OPC_CheckPredicate, + 21, + 232, + 151, + 0, // Skip to: 104527 + /* 65639 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 225, + 151, + 0, // Skip to: 104527 + /* 65646 */ MCD_OPC_Decode, + 239, + 32, + 179, + 2, // Opcode: SMULLv8i16_v4i32 + /* 65651 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 65673 + /* 65656 */ MCD_OPC_CheckPredicate, + 21, + 210, + 151, + 0, // Skip to: 104527 + /* 65661 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 203, + 151, + 0, // Skip to: 104527 + /* 65668 */ MCD_OPC_Decode, + 178, + 16, + 179, + 2, // Opcode: FMAXNMv2f64 + /* 65673 */ MCD_OPC_FilterValue, + 50, + 33, + 0, + 0, // Skip to: 65711 + /* 65678 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 65681 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 65696 + /* 65686 */ MCD_OPC_CheckPredicate, + 21, + 180, + 151, + 0, // Skip to: 104527 + /* 65691 */ MCD_OPC_Decode, + 174, + 14, + 184, + 2, // Opcode: FCVTASv2f64 + /* 65696 */ MCD_OPC_FilterValue, + 57, + 170, + 151, + 0, // Skip to: 104527 + /* 65701 */ MCD_OPC_CheckPredicate, + 23, + 165, + 151, + 0, // Skip to: 104527 + /* 65706 */ MCD_OPC_Decode, + 177, + 14, + 184, + 2, // Opcode: FCVTASv8f16 + /* 65711 */ MCD_OPC_FilterValue, + 51, + 17, + 0, + 0, // Skip to: 65733 + /* 65716 */ MCD_OPC_CheckPredicate, + 21, + 150, + 151, + 0, // Skip to: 104527 + /* 65721 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 143, + 151, + 0, // Skip to: 104527 + /* 65728 */ MCD_OPC_Decode, + 167, + 17, + 187, + 2, // Opcode: FMLAv2f64 + /* 65733 */ MCD_OPC_FilterValue, + 52, + 17, + 0, + 0, // Skip to: 65755 + /* 65738 */ MCD_OPC_CheckPredicate, + 21, + 128, + 151, + 0, // Skip to: 104527 + /* 65743 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 121, + 151, + 0, // Skip to: 104527 + /* 65750 */ MCD_OPC_Decode, + 147, + 34, + 179, + 2, // Opcode: SQDMULLv8i16_v4i32 + /* 65755 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 65777 + /* 65760 */ MCD_OPC_CheckPredicate, + 21, + 106, + 151, + 0, // Skip to: 104527 + /* 65765 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 99, + 151, + 0, // Skip to: 104527 + /* 65772 */ MCD_OPC_Decode, + 146, + 13, + 179, + 2, // Opcode: FADDv2f64 + /* 65777 */ MCD_OPC_FilterValue, + 54, + 33, + 0, + 0, // Skip to: 65815 + /* 65782 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 65785 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 65800 + /* 65790 */ MCD_OPC_CheckPredicate, + 21, + 76, + 151, + 0, // Skip to: 104527 + /* 65795 */ MCD_OPC_Decode, + 225, + 30, + 184, + 2, // Opcode: SCVTFv2f64 + /* 65800 */ MCD_OPC_FilterValue, + 57, + 66, + 151, + 0, // Skip to: 104527 + /* 65805 */ MCD_OPC_CheckPredicate, + 23, + 61, + 151, + 0, // Skip to: 104527 + /* 65810 */ MCD_OPC_Decode, + 232, + 30, + 184, + 2, // Opcode: SCVTFv8f16 + /* 65815 */ MCD_OPC_FilterValue, + 55, + 17, + 0, + 0, // Skip to: 65837 + /* 65820 */ MCD_OPC_CheckPredicate, + 21, + 46, + 151, + 0, // Skip to: 104527 + /* 65825 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 39, + 151, + 0, // Skip to: 104527 + /* 65832 */ MCD_OPC_Decode, + 253, + 17, + 179, + 2, // Opcode: FMULXv2f64 + /* 65837 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 65859 + /* 65842 */ MCD_OPC_CheckPredicate, + 21, + 24, + 151, + 0, // Skip to: 104527 + /* 65847 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 17, + 151, + 0, // Skip to: 104527 + /* 65854 */ MCD_OPC_Decode, + 177, + 13, + 179, + 2, // Opcode: FCMEQv2f64 + /* 65859 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 65881 + /* 65864 */ MCD_OPC_CheckPredicate, + 24, + 2, + 151, + 0, // Skip to: 104527 + /* 65869 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 251, + 150, + 0, // Skip to: 104527 + /* 65876 */ MCD_OPC_Decode, + 227, + 18, + 184, + 2, // Opcode: FRINT32Zv2f64 + /* 65881 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 65903 + /* 65886 */ MCD_OPC_CheckPredicate, + 21, + 236, + 150, + 0, // Skip to: 104527 + /* 65891 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 229, + 150, + 0, // Skip to: 104527 + /* 65898 */ MCD_OPC_Decode, + 207, + 16, + 179, + 2, // Opcode: FMAXv2f64 + /* 65903 */ MCD_OPC_FilterValue, + 62, + 17, + 0, + 0, // Skip to: 65925 + /* 65908 */ MCD_OPC_CheckPredicate, + 24, + 214, + 150, + 0, // Skip to: 104527 + /* 65913 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 207, + 150, + 0, // Skip to: 104527 + /* 65920 */ MCD_OPC_Decode, + 237, + 18, + 184, + 2, // Opcode: FRINT64Zv2f64 + /* 65925 */ MCD_OPC_FilterValue, + 63, + 197, + 150, + 0, // Skip to: 104527 + /* 65930 */ MCD_OPC_CheckPredicate, + 21, + 192, + 150, + 0, // Skip to: 104527 + /* 65935 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 185, + 150, + 0, // Skip to: 104527 + /* 65942 */ MCD_OPC_Decode, + 209, + 18, + 179, + 2, // Opcode: FRECPSv2f64 + /* 65947 */ MCD_OPC_FilterValue, + 3, + 218, + 6, + 0, // Skip to: 67706 + /* 65952 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 65955 */ MCD_OPC_FilterValue, + 0, + 205, + 0, + 0, // Skip to: 66165 + /* 65960 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 65963 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 65985 + /* 65968 */ MCD_OPC_CheckPredicate, + 21, + 154, + 150, + 0, // Skip to: 104527 + /* 65973 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 147, + 150, + 0, // Skip to: 104527 + /* 65980 */ MCD_OPC_Decode, + 164, + 42, + 179, + 2, // Opcode: UADDLv8i16_v4i32 + /* 65985 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 66023 + /* 65990 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 65993 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 66008 + /* 65998 */ MCD_OPC_CheckPredicate, + 23, + 124, + 150, + 0, // Skip to: 104527 + /* 66003 */ MCD_OPC_Decode, + 163, + 16, + 179, + 2, // Opcode: FMAXNMPv8f16 + /* 66008 */ MCD_OPC_FilterValue, + 1, + 114, + 150, + 0, // Skip to: 104527 + /* 66013 */ MCD_OPC_CheckPredicate, + 21, + 109, + 150, + 0, // Skip to: 104527 + /* 66018 */ MCD_OPC_Decode, + 246, + 42, + 179, + 2, // Opcode: UHADDv8i16 + /* 66023 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 66045 + /* 66028 */ MCD_OPC_CheckPredicate, + 21, + 94, + 150, + 0, // Skip to: 104527 + /* 66033 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 87, + 150, + 0, // Skip to: 104527 + /* 66040 */ MCD_OPC_Decode, + 166, + 29, + 184, + 2, // Opcode: REV32v8i16 + /* 66045 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 66067 + /* 66050 */ MCD_OPC_CheckPredicate, + 21, + 72, + 150, + 0, // Skip to: 104527 + /* 66055 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 65, + 150, + 0, // Skip to: 104527 + /* 66062 */ MCD_OPC_Decode, + 178, + 44, + 179, + 2, // Opcode: UQADDv8i16 + /* 66067 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 66089 + /* 66072 */ MCD_OPC_CheckPredicate, + 21, + 50, + 150, + 0, // Skip to: 104527 + /* 66077 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 43, + 150, + 0, // Skip to: 104527 + /* 66084 */ MCD_OPC_Decode, + 180, + 42, + 179, + 2, // Opcode: UADDWv8i16_v4i32 + /* 66089 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 66127 + /* 66094 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 66097 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 66112 + /* 66102 */ MCD_OPC_CheckPredicate, + 23, + 20, + 150, + 0, // Skip to: 104527 + /* 66107 */ MCD_OPC_Decode, + 131, + 13, + 179, + 2, // Opcode: FADDPv8f16 + /* 66112 */ MCD_OPC_FilterValue, + 1, + 10, + 150, + 0, // Skip to: 104527 + /* 66117 */ MCD_OPC_CheckPredicate, + 21, + 5, + 150, + 0, // Skip to: 104527 + /* 66122 */ MCD_OPC_Decode, + 232, + 45, + 179, + 2, // Opcode: URHADDv8i16 + /* 66127 */ MCD_OPC_FilterValue, + 7, + 251, + 149, + 0, // Skip to: 104527 + /* 66132 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 66135 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 66150 + /* 66140 */ MCD_OPC_CheckPredicate, + 23, + 238, + 149, + 0, // Skip to: 104527 + /* 66145 */ MCD_OPC_Decode, + 157, + 18, + 179, + 2, // Opcode: FMULv8f16 + /* 66150 */ MCD_OPC_FilterValue, + 1, + 228, + 149, + 0, // Skip to: 104527 + /* 66155 */ MCD_OPC_CheckPredicate, + 21, + 223, + 149, + 0, // Skip to: 104527 + /* 66160 */ MCD_OPC_Decode, + 141, + 9, + 187, + 2, // Opcode: BSLv16i8 + /* 66165 */ MCD_OPC_FilterValue, + 1, + 34, + 1, + 0, // Skip to: 66460 + /* 66170 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 66173 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 66195 + /* 66178 */ MCD_OPC_CheckPredicate, + 21, + 200, + 149, + 0, // Skip to: 104527 + /* 66183 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 193, + 149, + 0, // Skip to: 104527 + /* 66190 */ MCD_OPC_Decode, + 226, + 46, + 179, + 2, // Opcode: USUBLv8i16_v4i32 + /* 66195 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 66233 + /* 66200 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 66203 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 66218 + /* 66208 */ MCD_OPC_CheckPredicate, + 23, + 170, + 149, + 0, // Skip to: 104527 + /* 66213 */ MCD_OPC_Decode, + 206, + 13, + 179, + 2, // Opcode: FCMGEv8f16 + /* 66218 */ MCD_OPC_FilterValue, + 1, + 160, + 149, + 0, // Skip to: 104527 + /* 66223 */ MCD_OPC_CheckPredicate, + 21, + 155, + 149, + 0, // Skip to: 104527 + /* 66228 */ MCD_OPC_Decode, + 132, + 43, + 179, + 2, // Opcode: UHSUBv8i16 + /* 66233 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 66271 + /* 66238 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 66241 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 66256 + /* 66246 */ MCD_OPC_CheckPredicate, + 21, + 132, + 149, + 0, // Skip to: 104527 + /* 66251 */ MCD_OPC_Decode, + 150, + 42, + 184, + 2, // Opcode: UADDLPv8i16_v4i32 + /* 66256 */ MCD_OPC_FilterValue, + 33, + 122, + 149, + 0, // Skip to: 104527 + /* 66261 */ MCD_OPC_CheckPredicate, + 21, + 117, + 149, + 0, // Skip to: 104527 + /* 66266 */ MCD_OPC_Decode, + 175, + 36, + 193, + 2, // Opcode: SQXTUNv8i16 + /* 66271 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 66309 + /* 66276 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 66279 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 66294 + /* 66284 */ MCD_OPC_CheckPredicate, + 23, + 94, + 149, + 0, // Skip to: 104527 + /* 66289 */ MCD_OPC_Decode, + 232, + 12, + 179, + 2, // Opcode: FACGEv8f16 + /* 66294 */ MCD_OPC_FilterValue, + 1, + 84, + 149, + 0, // Skip to: 104527 + /* 66299 */ MCD_OPC_CheckPredicate, + 21, + 79, + 149, + 0, // Skip to: 104527 + /* 66304 */ MCD_OPC_Decode, + 204, + 45, + 179, + 2, // Opcode: UQSUBv8i16 + /* 66309 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 66331 + /* 66314 */ MCD_OPC_CheckPredicate, + 21, + 64, + 149, + 0, // Skip to: 104527 + /* 66319 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 57, + 149, + 0, // Skip to: 104527 + /* 66326 */ MCD_OPC_Decode, + 238, + 46, + 179, + 2, // Opcode: USUBWv8i16_v4i32 + /* 66331 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 66369 + /* 66336 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 66339 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 66354 + /* 66344 */ MCD_OPC_CheckPredicate, + 23, + 34, + 149, + 0, // Skip to: 104527 + /* 66349 */ MCD_OPC_Decode, + 192, + 16, + 179, + 2, // Opcode: FMAXPv8f16 + /* 66354 */ MCD_OPC_FilterValue, + 1, + 24, + 149, + 0, // Skip to: 104527 + /* 66359 */ MCD_OPC_CheckPredicate, + 21, + 19, + 149, + 0, // Skip to: 104527 + /* 66364 */ MCD_OPC_Decode, + 164, + 10, + 179, + 2, // Opcode: CMHIv8i16 + /* 66369 */ MCD_OPC_FilterValue, + 6, + 48, + 0, + 0, // Skip to: 66422 + /* 66374 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 66377 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 66392 + /* 66382 */ MCD_OPC_CheckPredicate, + 21, + 252, + 148, + 0, // Skip to: 104527 + /* 66387 */ MCD_OPC_Decode, + 202, + 46, + 193, + 2, // Opcode: USQADDv8i16 + /* 66392 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 66407 + /* 66397 */ MCD_OPC_CheckPredicate, + 21, + 237, + 148, + 0, // Skip to: 104527 + /* 66402 */ MCD_OPC_Decode, + 156, + 31, + 184, + 2, // Opcode: SHLLv8i16 + /* 66407 */ MCD_OPC_FilterValue, + 48, + 227, + 148, + 0, // Skip to: 104527 + /* 66412 */ MCD_OPC_CheckPredicate, + 21, + 222, + 148, + 0, // Skip to: 104527 + /* 66417 */ MCD_OPC_Decode, + 158, + 42, + 207, + 2, // Opcode: UADDLVv8i16v + /* 66422 */ MCD_OPC_FilterValue, + 7, + 212, + 148, + 0, // Skip to: 104527 + /* 66427 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 66430 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 66445 + /* 66435 */ MCD_OPC_CheckPredicate, + 23, + 199, + 148, + 0, // Skip to: 104527 + /* 66440 */ MCD_OPC_Decode, + 132, + 16, + 179, + 2, // Opcode: FDIVv8f16 + /* 66445 */ MCD_OPC_FilterValue, + 1, + 189, + 148, + 0, // Skip to: 104527 + /* 66450 */ MCD_OPC_CheckPredicate, + 21, + 184, + 148, + 0, // Skip to: 104527 + /* 66455 */ MCD_OPC_Decode, + 172, + 10, + 179, + 2, // Opcode: CMHSv8i16 + /* 66460 */ MCD_OPC_FilterValue, + 2, + 195, + 0, + 0, // Skip to: 66660 + /* 66465 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 66468 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 66490 + /* 66473 */ MCD_OPC_CheckPredicate, + 21, + 161, + 148, + 0, // Skip to: 104527 + /* 66478 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 154, + 148, + 0, // Skip to: 104527 + /* 66485 */ MCD_OPC_Decode, + 139, + 29, + 187, + 2, // Opcode: RADDHNv4i32_v8i16 + /* 66490 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 66512 + /* 66495 */ MCD_OPC_CheckPredicate, + 21, + 139, + 148, + 0, // Skip to: 104527 + /* 66500 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 132, + 148, + 0, // Skip to: 104527 + /* 66507 */ MCD_OPC_Decode, + 173, + 46, + 179, + 2, // Opcode: USHLv8i16 + /* 66512 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 66550 + /* 66517 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 66520 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 66535 + /* 66525 */ MCD_OPC_CheckPredicate, + 21, + 109, + 148, + 0, // Skip to: 104527 + /* 66530 */ MCD_OPC_Decode, + 236, + 9, + 184, + 2, // Opcode: CLZv8i16 + /* 66535 */ MCD_OPC_FilterValue, + 33, + 99, + 148, + 0, // Skip to: 104527 + /* 66540 */ MCD_OPC_CheckPredicate, + 21, + 94, + 148, + 0, // Skip to: 104527 + /* 66545 */ MCD_OPC_Decode, + 219, + 45, + 193, + 2, // Opcode: UQXTNv8i16 + /* 66550 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 66572 + /* 66555 */ MCD_OPC_CheckPredicate, + 21, + 79, + 148, + 0, // Skip to: 104527 + /* 66560 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 72, + 148, + 0, // Skip to: 104527 + /* 66567 */ MCD_OPC_Decode, + 160, + 45, + 179, + 2, // Opcode: UQSHLv8i16 + /* 66572 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 66594 + /* 66577 */ MCD_OPC_CheckPredicate, + 21, + 57, + 148, + 0, // Skip to: 104527 + /* 66582 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 50, + 148, + 0, // Skip to: 104527 + /* 66589 */ MCD_OPC_Decode, + 228, + 41, + 187, + 2, // Opcode: UABALv8i16_v4i32 + /* 66594 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 66616 + /* 66599 */ MCD_OPC_CheckPredicate, + 21, + 35, + 148, + 0, // Skip to: 104527 + /* 66604 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 28, + 148, + 0, // Skip to: 104527 + /* 66611 */ MCD_OPC_Decode, + 248, + 45, + 179, + 2, // Opcode: URSHLv8i16 + /* 66616 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 66638 + /* 66621 */ MCD_OPC_CheckPredicate, + 21, + 13, + 148, + 0, // Skip to: 104527 + /* 66626 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 6, + 148, + 0, // Skip to: 104527 + /* 66633 */ MCD_OPC_Decode, + 150, + 29, + 184, + 2, // Opcode: RBITv16i8 + /* 66638 */ MCD_OPC_FilterValue, + 7, + 252, + 147, + 0, // Skip to: 104527 + /* 66643 */ MCD_OPC_CheckPredicate, + 21, + 247, + 147, + 0, // Skip to: 104527 + /* 66648 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 240, + 147, + 0, // Skip to: 104527 + /* 66655 */ MCD_OPC_Decode, + 241, + 44, + 179, + 2, // Opcode: UQRSHLv8i16 + /* 66660 */ MCD_OPC_FilterValue, + 3, + 195, + 0, + 0, // Skip to: 66860 + /* 66665 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 66668 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 66690 + /* 66673 */ MCD_OPC_CheckPredicate, + 21, + 217, + 147, + 0, // Skip to: 104527 + /* 66678 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 210, + 147, + 0, // Skip to: 104527 + /* 66685 */ MCD_OPC_Decode, + 215, + 29, + 187, + 2, // Opcode: RSUBHNv4i32_v8i16 + /* 66690 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 66712 + /* 66695 */ MCD_OPC_CheckPredicate, + 21, + 195, + 147, + 0, // Skip to: 104527 + /* 66700 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 188, + 147, + 0, // Skip to: 104527 + /* 66707 */ MCD_OPC_Decode, + 166, + 43, + 179, + 2, // Opcode: UMAXv8i16 + /* 66712 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 66750 + /* 66717 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 66720 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 66735 + /* 66725 */ MCD_OPC_CheckPredicate, + 21, + 165, + 147, + 0, // Skip to: 104527 + /* 66730 */ MCD_OPC_Decode, + 141, + 42, + 193, + 2, // Opcode: UADALPv8i16_v4i32 + /* 66735 */ MCD_OPC_FilterValue, + 33, + 155, + 147, + 0, // Skip to: 104527 + /* 66740 */ MCD_OPC_CheckPredicate, + 21, + 150, + 147, + 0, // Skip to: 104527 + /* 66745 */ MCD_OPC_Decode, + 169, + 15, + 193, + 2, // Opcode: FCVTXNv4f32 + /* 66750 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 66772 + /* 66755 */ MCD_OPC_CheckPredicate, + 21, + 135, + 147, + 0, // Skip to: 104527 + /* 66760 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 128, + 147, + 0, // Skip to: 104527 + /* 66767 */ MCD_OPC_Decode, + 199, + 43, + 179, + 2, // Opcode: UMINv8i16 + /* 66772 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 66794 + /* 66777 */ MCD_OPC_CheckPredicate, + 21, + 113, + 147, + 0, // Skip to: 104527 + /* 66782 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 106, + 147, + 0, // Skip to: 104527 + /* 66789 */ MCD_OPC_Decode, + 250, + 41, + 179, + 2, // Opcode: UABDLv8i16_v4i32 + /* 66794 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 66816 + /* 66799 */ MCD_OPC_CheckPredicate, + 21, + 91, + 147, + 0, // Skip to: 104527 + /* 66804 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 84, + 147, + 0, // Skip to: 104527 + /* 66811 */ MCD_OPC_Decode, + 132, + 42, + 179, + 2, // Opcode: UABDv8i16 + /* 66816 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 66838 + /* 66821 */ MCD_OPC_CheckPredicate, + 21, + 69, + 147, + 0, // Skip to: 104527 + /* 66826 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 62, + 147, + 0, // Skip to: 104527 + /* 66833 */ MCD_OPC_Decode, + 183, + 34, + 184, + 2, // Opcode: SQNEGv8i16 + /* 66838 */ MCD_OPC_FilterValue, + 7, + 52, + 147, + 0, // Skip to: 104527 + /* 66843 */ MCD_OPC_CheckPredicate, + 21, + 47, + 147, + 0, // Skip to: 104527 + /* 66848 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 40, + 147, + 0, // Skip to: 104527 + /* 66855 */ MCD_OPC_Decode, + 238, + 41, + 187, + 2, // Opcode: UABAv8i16 + /* 66860 */ MCD_OPC_FilterValue, + 4, + 229, + 0, + 0, // Skip to: 67094 + /* 66865 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 66868 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 66890 + /* 66873 */ MCD_OPC_CheckPredicate, + 21, + 17, + 147, + 0, // Skip to: 104527 + /* 66878 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 10, + 147, + 0, // Skip to: 104527 + /* 66885 */ MCD_OPC_Decode, + 219, + 43, + 187, + 2, // Opcode: UMLALv8i16_v4i32 + /* 66890 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 66928 + /* 66895 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 66898 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 66913 + /* 66903 */ MCD_OPC_CheckPredicate, + 28, + 243, + 146, + 0, // Skip to: 104527 + /* 66908 */ MCD_OPC_Decode, + 208, + 34, + 187, + 2, // Opcode: SQRDMLAHv8i16 + /* 66913 */ MCD_OPC_FilterValue, + 1, + 233, + 146, + 0, // Skip to: 104527 + /* 66918 */ MCD_OPC_CheckPredicate, + 21, + 228, + 146, + 0, // Skip to: 104527 + /* 66923 */ MCD_OPC_Decode, + 222, + 40, + 179, + 2, // Opcode: SUBv8i16 + /* 66928 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 66981 + /* 66933 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 66936 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 66951 + /* 66941 */ MCD_OPC_CheckPredicate, + 21, + 205, + 146, + 0, // Skip to: 104527 + /* 66946 */ MCD_OPC_Decode, + 139, + 10, + 184, + 2, // Opcode: CMGEv8i16rz + /* 66951 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 66966 + /* 66956 */ MCD_OPC_CheckPredicate, + 21, + 190, + 146, + 0, // Skip to: 104527 + /* 66961 */ MCD_OPC_Decode, + 246, + 18, + 184, + 2, // Opcode: FRINTAv2f64 + /* 66966 */ MCD_OPC_FilterValue, + 57, + 180, + 146, + 0, // Skip to: 104527 + /* 66971 */ MCD_OPC_CheckPredicate, + 23, + 175, + 146, + 0, // Skip to: 104527 + /* 66976 */ MCD_OPC_Decode, + 249, + 18, + 184, + 2, // Opcode: FRINTAv8f16 + /* 66981 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 67019 + /* 66986 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 66989 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67004 + /* 66994 */ MCD_OPC_CheckPredicate, + 28, + 152, + 146, + 0, // Skip to: 104527 + /* 66999 */ MCD_OPC_Decode, + 227, + 34, + 187, + 2, // Opcode: SQRDMLSHv8i16 + /* 67004 */ MCD_OPC_FilterValue, + 1, + 142, + 146, + 0, // Skip to: 104527 + /* 67009 */ MCD_OPC_CheckPredicate, + 21, + 137, + 146, + 0, // Skip to: 104527 + /* 67014 */ MCD_OPC_Decode, + 250, + 9, + 179, + 2, // Opcode: CMEQv8i16 + /* 67019 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 67041 + /* 67024 */ MCD_OPC_CheckPredicate, + 21, + 122, + 146, + 0, // Skip to: 104527 + /* 67029 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 115, + 146, + 0, // Skip to: 104527 + /* 67036 */ MCD_OPC_Decode, + 173, + 27, + 187, + 2, // Opcode: MLSv8i16 + /* 67041 */ MCD_OPC_FilterValue, + 6, + 105, + 146, + 0, // Skip to: 104527 + /* 67046 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 67049 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 67064 + /* 67054 */ MCD_OPC_CheckPredicate, + 21, + 92, + 146, + 0, // Skip to: 104527 + /* 67059 */ MCD_OPC_Decode, + 186, + 10, + 184, + 2, // Opcode: CMLEv8i16rz + /* 67064 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 67079 + /* 67069 */ MCD_OPC_CheckPredicate, + 21, + 77, + 146, + 0, // Skip to: 104527 + /* 67074 */ MCD_OPC_Decode, + 173, + 19, + 184, + 2, // Opcode: FRINTXv2f64 + /* 67079 */ MCD_OPC_FilterValue, + 57, + 67, + 146, + 0, // Skip to: 104527 + /* 67084 */ MCD_OPC_CheckPredicate, + 23, + 62, + 146, + 0, // Skip to: 104527 + /* 67089 */ MCD_OPC_Decode, + 176, + 19, + 184, + 2, // Opcode: FRINTXv8f16 + /* 67094 */ MCD_OPC_FilterValue, + 5, + 212, + 0, + 0, // Skip to: 67311 + /* 67099 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 67102 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 67124 + /* 67107 */ MCD_OPC_CheckPredicate, + 21, + 39, + 146, + 0, // Skip to: 104527 + /* 67112 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 32, + 146, + 0, // Skip to: 104527 + /* 67119 */ MCD_OPC_Decode, + 239, + 43, + 187, + 2, // Opcode: UMLSLv8i16_v4i32 + /* 67124 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 67146 + /* 67129 */ MCD_OPC_CheckPredicate, + 21, + 17, + 146, + 0, // Skip to: 104527 + /* 67134 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 10, + 146, + 0, // Skip to: 104527 + /* 67141 */ MCD_OPC_Decode, + 143, + 43, + 179, + 2, // Opcode: UMAXPv8i16 + /* 67146 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 67214 + /* 67151 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 67154 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 67169 + /* 67159 */ MCD_OPC_CheckPredicate, + 21, + 243, + 145, + 0, // Skip to: 104527 + /* 67164 */ MCD_OPC_Decode, + 128, + 15, + 184, + 2, // Opcode: FCVTNUv2f64 + /* 67169 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 67184 + /* 67174 */ MCD_OPC_CheckPredicate, + 21, + 228, + 145, + 0, // Skip to: 104527 + /* 67179 */ MCD_OPC_Decode, + 152, + 43, + 199, + 2, // Opcode: UMAXVv8i16v + /* 67184 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 67199 + /* 67189 */ MCD_OPC_CheckPredicate, + 21, + 213, + 145, + 0, // Skip to: 104527 + /* 67194 */ MCD_OPC_Decode, + 185, + 43, + 199, + 2, // Opcode: UMINVv8i16v + /* 67199 */ MCD_OPC_FilterValue, + 57, + 203, + 145, + 0, // Skip to: 104527 + /* 67204 */ MCD_OPC_CheckPredicate, + 23, + 198, + 145, + 0, // Skip to: 104527 + /* 67209 */ MCD_OPC_Decode, + 131, + 15, + 184, + 2, // Opcode: FCVTNUv8f16 + /* 67214 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 67236 + /* 67219 */ MCD_OPC_CheckPredicate, + 21, + 183, + 145, + 0, // Skip to: 104527 + /* 67224 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 176, + 145, + 0, // Skip to: 104527 + /* 67231 */ MCD_OPC_Decode, + 176, + 43, + 179, + 2, // Opcode: UMINPv8i16 + /* 67236 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 67258 + /* 67241 */ MCD_OPC_CheckPredicate, + 21, + 161, + 145, + 0, // Skip to: 104527 + /* 67246 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 154, + 145, + 0, // Skip to: 104527 + /* 67253 */ MCD_OPC_Decode, + 246, + 34, + 179, + 2, // Opcode: SQRDMULHv8i16 + /* 67258 */ MCD_OPC_FilterValue, + 6, + 144, + 145, + 0, // Skip to: 104527 + /* 67263 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 67266 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 67281 + /* 67271 */ MCD_OPC_CheckPredicate, + 21, + 131, + 145, + 0, // Skip to: 104527 + /* 67276 */ MCD_OPC_Decode, + 128, + 28, + 184, + 2, // Opcode: NEGv8i16 + /* 67281 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 67296 + /* 67286 */ MCD_OPC_CheckPredicate, + 21, + 116, + 145, + 0, // Skip to: 104527 + /* 67291 */ MCD_OPC_Decode, + 226, + 14, + 184, + 2, // Opcode: FCVTMUv2f64 + /* 67296 */ MCD_OPC_FilterValue, + 57, + 106, + 145, + 0, // Skip to: 104527 + /* 67301 */ MCD_OPC_CheckPredicate, + 23, + 101, + 145, + 0, // Skip to: 104527 + /* 67306 */ MCD_OPC_Decode, + 229, + 14, + 184, + 2, // Opcode: FCVTMUv8f16 + /* 67311 */ MCD_OPC_FilterValue, + 6, + 185, + 0, + 0, // Skip to: 67501 + /* 67316 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 67319 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 67425 + /* 67324 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 67327 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 67349 + /* 67332 */ MCD_OPC_CheckPredicate, + 21, + 70, + 145, + 0, // Skip to: 104527 + /* 67337 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 63, + 145, + 0, // Skip to: 104527 + /* 67344 */ MCD_OPC_Decode, + 155, + 44, + 179, + 2, // Opcode: UMULLv8i16_v4i32 + /* 67349 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 67387 + /* 67354 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 67357 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 67372 + /* 67362 */ MCD_OPC_CheckPredicate, + 21, + 40, + 145, + 0, // Skip to: 104527 + /* 67367 */ MCD_OPC_Decode, + 188, + 14, + 184, + 2, // Opcode: FCVTAUv2f64 + /* 67372 */ MCD_OPC_FilterValue, + 57, + 30, + 145, + 0, // Skip to: 104527 + /* 67377 */ MCD_OPC_CheckPredicate, + 23, + 25, + 145, + 0, // Skip to: 104527 + /* 67382 */ MCD_OPC_Decode, + 191, + 14, + 184, + 2, // Opcode: FCVTAUv8f16 + /* 67387 */ MCD_OPC_FilterValue, + 3, + 15, + 145, + 0, // Skip to: 104527 + /* 67392 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 67395 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 67410 + /* 67400 */ MCD_OPC_CheckPredicate, + 21, + 2, + 145, + 0, // Skip to: 104527 + /* 67405 */ MCD_OPC_Decode, + 214, + 42, + 184, + 2, // Opcode: UCVTFv2f64 + /* 67410 */ MCD_OPC_FilterValue, + 57, + 248, + 144, + 0, // Skip to: 104527 + /* 67415 */ MCD_OPC_CheckPredicate, + 23, + 243, + 144, + 0, // Skip to: 104527 + /* 67420 */ MCD_OPC_Decode, + 221, + 42, + 184, + 2, // Opcode: UCVTFv8f16 + /* 67425 */ MCD_OPC_FilterValue, + 1, + 233, + 144, + 0, // Skip to: 104527 + /* 67430 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 67433 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67448 + /* 67438 */ MCD_OPC_CheckPredicate, + 29, + 220, + 144, + 0, // Skip to: 104527 + /* 67443 */ MCD_OPC_Decode, + 241, + 13, + 216, + 2, // Opcode: FCMLAv8f16 + /* 67448 */ MCD_OPC_FilterValue, + 1, + 210, + 144, + 0, // Skip to: 104527 + /* 67453 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 67456 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67471 + /* 67461 */ MCD_OPC_CheckPredicate, + 21, + 197, + 144, + 0, // Skip to: 104527 + /* 67466 */ MCD_OPC_Decode, + 157, + 16, + 179, + 2, // Opcode: FMAXNMPv2f64 + /* 67471 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 67486 + /* 67476 */ MCD_OPC_CheckPredicate, + 21, + 182, + 144, + 0, // Skip to: 104527 + /* 67481 */ MCD_OPC_Decode, + 253, + 12, + 179, + 2, // Opcode: FADDPv2f64 + /* 67486 */ MCD_OPC_FilterValue, + 3, + 172, + 144, + 0, // Skip to: 104527 + /* 67491 */ MCD_OPC_CheckPredicate, + 21, + 167, + 144, + 0, // Skip to: 104527 + /* 67496 */ MCD_OPC_Decode, + 150, + 18, + 179, + 2, // Opcode: FMULv2f64 + /* 67501 */ MCD_OPC_FilterValue, + 7, + 157, + 144, + 0, // Skip to: 104527 + /* 67506 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 67509 */ MCD_OPC_FilterValue, + 1, + 56, + 0, + 0, // Skip to: 67570 + /* 67514 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 67517 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67532 + /* 67522 */ MCD_OPC_CheckPredicate, + 29, + 136, + 144, + 0, // Skip to: 104527 + /* 67527 */ MCD_OPC_Decode, + 157, + 13, + 217, + 2, // Opcode: FCADDv8f16 + /* 67532 */ MCD_OPC_FilterValue, + 1, + 126, + 144, + 0, // Skip to: 104527 + /* 67537 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 67540 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67555 + /* 67545 */ MCD_OPC_CheckPredicate, + 21, + 113, + 144, + 0, // Skip to: 104527 + /* 67550 */ MCD_OPC_Decode, + 199, + 13, + 179, + 2, // Opcode: FCMGEv2f64 + /* 67555 */ MCD_OPC_FilterValue, + 1, + 103, + 144, + 0, // Skip to: 104527 + /* 67560 */ MCD_OPC_CheckPredicate, + 21, + 98, + 144, + 0, // Skip to: 104527 + /* 67565 */ MCD_OPC_Decode, + 186, + 16, + 179, + 2, // Opcode: FMAXPv2f64 + /* 67570 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 67622 + /* 67575 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 67578 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 67600 + /* 67583 */ MCD_OPC_CheckPredicate, + 24, + 75, + 144, + 0, // Skip to: 104527 + /* 67588 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 68, + 144, + 0, // Skip to: 104527 + /* 67595 */ MCD_OPC_Decode, + 222, + 18, + 184, + 2, // Opcode: FRINT32Xv2f64 + /* 67600 */ MCD_OPC_FilterValue, + 1, + 58, + 144, + 0, // Skip to: 104527 + /* 67605 */ MCD_OPC_CheckPredicate, + 24, + 53, + 144, + 0, // Skip to: 104527 + /* 67610 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 46, + 144, + 0, // Skip to: 104527 + /* 67617 */ MCD_OPC_Decode, + 232, + 18, + 184, + 2, // Opcode: FRINT64Xv2f64 + /* 67622 */ MCD_OPC_FilterValue, + 3, + 36, + 144, + 0, // Skip to: 104527 + /* 67627 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 67630 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 67668 + /* 67635 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 67638 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67653 + /* 67643 */ MCD_OPC_CheckPredicate, + 30, + 15, + 144, + 0, // Skip to: 104527 + /* 67648 */ MCD_OPC_Decode, + 207, + 8, + 187, + 2, // Opcode: BFMMLA + /* 67653 */ MCD_OPC_FilterValue, + 1, + 5, + 144, + 0, // Skip to: 104527 + /* 67658 */ MCD_OPC_CheckPredicate, + 21, + 0, + 144, + 0, // Skip to: 104527 + /* 67663 */ MCD_OPC_Decode, + 229, + 12, + 179, + 2, // Opcode: FACGEv2f64 + /* 67668 */ MCD_OPC_FilterValue, + 1, + 246, + 143, + 0, // Skip to: 104527 + /* 67673 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 67676 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67691 + /* 67681 */ MCD_OPC_CheckPredicate, + 30, + 233, + 143, + 0, // Skip to: 104527 + /* 67686 */ MCD_OPC_Decode, + 202, + 8, + 187, + 2, // Opcode: BFDOTv8bf16 + /* 67691 */ MCD_OPC_FilterValue, + 1, + 223, + 143, + 0, // Skip to: 104527 + /* 67696 */ MCD_OPC_CheckPredicate, + 21, + 218, + 143, + 0, // Skip to: 104527 + /* 67701 */ MCD_OPC_Decode, + 129, + 16, + 179, + 2, // Opcode: FDIVv2f64 + /* 67706 */ MCD_OPC_FilterValue, + 6, + 208, + 143, + 0, // Skip to: 104527 + /* 67711 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 67714 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 67736 + /* 67719 */ MCD_OPC_CheckPredicate, + 31, + 195, + 143, + 0, // Skip to: 104527 + /* 67724 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 188, + 143, + 0, // Skip to: 104527 + /* 67731 */ MCD_OPC_Decode, + 206, + 31, + 212, + 2, // Opcode: SM3SS1 + /* 67736 */ MCD_OPC_FilterValue, + 1, + 178, + 143, + 0, // Skip to: 104527 + /* 67741 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 67744 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 67826 + /* 67749 */ MCD_OPC_ExtractField, + 14, + 1, // Inst{14} ... + /* 67752 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 67797 + /* 67757 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 67760 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67775 + /* 67765 */ MCD_OPC_CheckPredicate, + 31, + 149, + 143, + 0, // Skip to: 104527 + /* 67770 */ MCD_OPC_Decode, + 207, + 31, + 218, + 2, // Opcode: SM3TT1A + /* 67775 */ MCD_OPC_FilterValue, + 1, + 139, + 143, + 0, // Skip to: 104527 + /* 67780 */ MCD_OPC_CheckPredicate, + 27, + 134, + 143, + 0, // Skip to: 104527 + /* 67785 */ MCD_OPC_CheckField, + 12, + 2, + 0, + 127, + 143, + 0, // Skip to: 104527 + /* 67792 */ MCD_OPC_Decode, + 138, + 31, + 187, + 2, // Opcode: SHA512H + /* 67797 */ MCD_OPC_FilterValue, + 1, + 117, + 143, + 0, // Skip to: 104527 + /* 67802 */ MCD_OPC_CheckPredicate, + 31, + 112, + 143, + 0, // Skip to: 104527 + /* 67807 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 105, + 143, + 0, // Skip to: 104527 + /* 67814 */ MCD_OPC_CheckField, + 12, + 2, + 0, + 98, + 143, + 0, // Skip to: 104527 + /* 67821 */ MCD_OPC_Decode, + 204, + 31, + 187, + 2, // Opcode: SM3PARTW1 + /* 67826 */ MCD_OPC_FilterValue, + 1, + 77, + 0, + 0, // Skip to: 67908 + /* 67831 */ MCD_OPC_ExtractField, + 14, + 1, // Inst{14} ... + /* 67834 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 67879 + /* 67839 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 67842 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67857 + /* 67847 */ MCD_OPC_CheckPredicate, + 31, + 67, + 143, + 0, // Skip to: 104527 + /* 67852 */ MCD_OPC_Decode, + 208, + 31, + 218, + 2, // Opcode: SM3TT1B + /* 67857 */ MCD_OPC_FilterValue, + 1, + 57, + 143, + 0, // Skip to: 104527 + /* 67862 */ MCD_OPC_CheckPredicate, + 27, + 52, + 143, + 0, // Skip to: 104527 + /* 67867 */ MCD_OPC_CheckField, + 12, + 2, + 0, + 45, + 143, + 0, // Skip to: 104527 + /* 67874 */ MCD_OPC_Decode, + 139, + 31, + 187, + 2, // Opcode: SHA512H2 + /* 67879 */ MCD_OPC_FilterValue, + 1, + 35, + 143, + 0, // Skip to: 104527 + /* 67884 */ MCD_OPC_CheckPredicate, + 31, + 30, + 143, + 0, // Skip to: 104527 + /* 67889 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 23, + 143, + 0, // Skip to: 104527 + /* 67896 */ MCD_OPC_CheckField, + 12, + 2, + 0, + 16, + 143, + 0, // Skip to: 104527 + /* 67903 */ MCD_OPC_Decode, + 205, + 31, + 187, + 2, // Opcode: SM3PARTW2 + /* 67908 */ MCD_OPC_FilterValue, + 2, + 77, + 0, + 0, // Skip to: 67990 + /* 67913 */ MCD_OPC_ExtractField, + 14, + 1, // Inst{14} ... + /* 67916 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 67961 + /* 67921 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 67924 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 67939 + /* 67929 */ MCD_OPC_CheckPredicate, + 31, + 241, + 142, + 0, // Skip to: 104527 + /* 67934 */ MCD_OPC_Decode, + 209, + 31, + 218, + 2, // Opcode: SM3TT2A + /* 67939 */ MCD_OPC_FilterValue, + 1, + 231, + 142, + 0, // Skip to: 104527 + /* 67944 */ MCD_OPC_CheckPredicate, + 27, + 226, + 142, + 0, // Skip to: 104527 + /* 67949 */ MCD_OPC_CheckField, + 12, + 2, + 0, + 219, + 142, + 0, // Skip to: 104527 + /* 67956 */ MCD_OPC_Decode, + 141, + 31, + 187, + 2, // Opcode: SHA512SU1 + /* 67961 */ MCD_OPC_FilterValue, + 1, + 209, + 142, + 0, // Skip to: 104527 + /* 67966 */ MCD_OPC_CheckPredicate, + 31, + 204, + 142, + 0, // Skip to: 104527 + /* 67971 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 197, + 142, + 0, // Skip to: 104527 + /* 67978 */ MCD_OPC_CheckField, + 12, + 2, + 0, + 190, + 142, + 0, // Skip to: 104527 + /* 67985 */ MCD_OPC_Decode, + 213, + 31, + 179, + 2, // Opcode: SM4ENCKEY + /* 67990 */ MCD_OPC_FilterValue, + 3, + 180, + 142, + 0, // Skip to: 104527 + /* 67995 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 67998 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 68020 + /* 68003 */ MCD_OPC_CheckPredicate, + 31, + 167, + 142, + 0, // Skip to: 104527 + /* 68008 */ MCD_OPC_CheckField, + 14, + 1, + 0, + 160, + 142, + 0, // Skip to: 104527 + /* 68015 */ MCD_OPC_Decode, + 210, + 31, + 218, + 2, // Opcode: SM3TT2B + /* 68020 */ MCD_OPC_FilterValue, + 1, + 150, + 142, + 0, // Skip to: 104527 + /* 68025 */ MCD_OPC_CheckPredicate, + 27, + 145, + 142, + 0, // Skip to: 104527 + /* 68030 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 138, + 142, + 0, // Skip to: 104527 + /* 68037 */ MCD_OPC_Decode, + 142, + 29, + 179, + 2, // Opcode: RAX1 + /* 68042 */ MCD_OPC_FilterValue, + 10, + 179, + 24, + 0, // Skip to: 74370 + /* 68047 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 68050 */ MCD_OPC_FilterValue, + 0, + 86, + 6, + 0, // Skip to: 69677 + /* 68055 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 68058 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 68080 + /* 68063 */ MCD_OPC_CheckPredicate, + 21, + 107, + 142, + 0, // Skip to: 104527 + /* 68068 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 100, + 142, + 0, // Skip to: 104527 + /* 68075 */ MCD_OPC_Decode, + 164, + 30, + 151, + 2, // Opcode: SADDLv2i32_v2i64 + /* 68080 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 68102 + /* 68085 */ MCD_OPC_CheckPredicate, + 21, + 85, + 142, + 0, // Skip to: 104527 + /* 68090 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 78, + 142, + 0, // Skip to: 104527 + /* 68097 */ MCD_OPC_Decode, + 147, + 31, + 155, + 2, // Opcode: SHADDv2i32 + /* 68102 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 68124 + /* 68107 */ MCD_OPC_CheckPredicate, + 21, + 63, + 142, + 0, // Skip to: 104527 + /* 68112 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 56, + 142, + 0, // Skip to: 104527 + /* 68119 */ MCD_OPC_Decode, + 169, + 29, + 156, + 2, // Opcode: REV64v2i32 + /* 68124 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 68146 + /* 68129 */ MCD_OPC_CheckPredicate, + 21, + 41, + 142, + 0, // Skip to: 104527 + /* 68134 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 34, + 142, + 0, // Skip to: 104527 + /* 68141 */ MCD_OPC_Decode, + 153, + 33, + 155, + 2, // Opcode: SQADDv2i32 + /* 68146 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 68168 + /* 68151 */ MCD_OPC_CheckPredicate, + 21, + 19, + 142, + 0, // Skip to: 104527 + /* 68156 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 12, + 142, + 0, // Skip to: 104527 + /* 68163 */ MCD_OPC_Decode, + 179, + 30, + 159, + 2, // Opcode: SADDWv2i32_v2i64 + /* 68168 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 68190 + /* 68173 */ MCD_OPC_CheckPredicate, + 21, + 253, + 141, + 0, // Skip to: 104527 + /* 68178 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 246, + 141, + 0, // Skip to: 104527 + /* 68185 */ MCD_OPC_Decode, + 182, + 36, + 155, + 2, // Opcode: SRHADDv2i32 + /* 68190 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 68212 + /* 68195 */ MCD_OPC_CheckPredicate, + 21, + 231, + 141, + 0, // Skip to: 104527 + /* 68200 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 224, + 141, + 0, // Skip to: 104527 + /* 68207 */ MCD_OPC_Decode, + 134, + 47, + 155, + 2, // Opcode: UZP1v2i32 + /* 68212 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 68234 + /* 68217 */ MCD_OPC_CheckPredicate, + 21, + 209, + 141, + 0, // Skip to: 104527 + /* 68222 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 202, + 141, + 0, // Skip to: 104527 + /* 68229 */ MCD_OPC_Decode, + 163, + 28, + 155, + 2, // Opcode: ORRv8i8 + /* 68234 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 68256 + /* 68239 */ MCD_OPC_CheckPredicate, + 21, + 187, + 141, + 0, // Skip to: 104527 + /* 68244 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 180, + 141, + 0, // Skip to: 104527 + /* 68251 */ MCD_OPC_Decode, + 202, + 37, + 151, + 2, // Opcode: SSUBLv2i32_v2i64 + /* 68256 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 68278 + /* 68261 */ MCD_OPC_CheckPredicate, + 21, + 165, + 141, + 0, // Skip to: 104527 + /* 68266 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 158, + 141, + 0, // Skip to: 104527 + /* 68273 */ MCD_OPC_Decode, + 187, + 31, + 155, + 2, // Opcode: SHSUBv2i32 + /* 68278 */ MCD_OPC_FilterValue, + 10, + 56, + 0, + 0, // Skip to: 68339 + /* 68283 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 68286 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 68301 + /* 68291 */ MCD_OPC_CheckPredicate, + 21, + 135, + 141, + 0, // Skip to: 104527 + /* 68296 */ MCD_OPC_Decode, + 193, + 41, + 155, + 2, // Opcode: TRN1v2i32 + /* 68301 */ MCD_OPC_FilterValue, + 1, + 125, + 141, + 0, // Skip to: 104527 + /* 68306 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 68309 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 68324 + /* 68314 */ MCD_OPC_CheckPredicate, + 21, + 112, + 141, + 0, // Skip to: 104527 + /* 68319 */ MCD_OPC_Decode, + 150, + 30, + 156, + 2, // Opcode: SADDLPv2i32_v1i64 + /* 68324 */ MCD_OPC_FilterValue, + 1, + 102, + 141, + 0, // Skip to: 104527 + /* 68329 */ MCD_OPC_CheckPredicate, + 21, + 97, + 141, + 0, // Skip to: 104527 + /* 68334 */ MCD_OPC_Decode, + 241, + 47, + 161, + 2, // Opcode: XTNv2i32 + /* 68339 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 68361 + /* 68344 */ MCD_OPC_CheckPredicate, + 21, + 82, + 141, + 0, // Skip to: 104527 + /* 68349 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 75, + 141, + 0, // Skip to: 104527 + /* 68356 */ MCD_OPC_Decode, + 141, + 36, + 155, + 2, // Opcode: SQSUBv2i32 + /* 68361 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 68383 + /* 68366 */ MCD_OPC_CheckPredicate, + 21, + 60, + 141, + 0, // Skip to: 104527 + /* 68371 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 53, + 141, + 0, // Skip to: 104527 + /* 68378 */ MCD_OPC_Decode, + 214, + 37, + 159, + 2, // Opcode: SSUBWv2i32_v2i64 + /* 68383 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 68405 + /* 68388 */ MCD_OPC_CheckPredicate, + 21, + 38, + 141, + 0, // Skip to: 104527 + /* 68393 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 31, + 141, + 0, // Skip to: 104527 + /* 68400 */ MCD_OPC_Decode, + 146, + 10, + 155, + 2, // Opcode: CMGTv2i32 + /* 68405 */ MCD_OPC_FilterValue, + 14, + 40, + 0, + 0, // Skip to: 68450 + /* 68410 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 68413 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 68428 + /* 68418 */ MCD_OPC_CheckPredicate, + 21, + 8, + 141, + 0, // Skip to: 104527 + /* 68423 */ MCD_OPC_Decode, + 129, + 48, + 155, + 2, // Opcode: ZIP1v2i32 + /* 68428 */ MCD_OPC_FilterValue, + 1, + 254, + 140, + 0, // Skip to: 104527 + /* 68433 */ MCD_OPC_CheckPredicate, + 21, + 249, + 140, + 0, // Skip to: 104527 + /* 68438 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 242, + 140, + 0, // Skip to: 104527 + /* 68445 */ MCD_OPC_Decode, + 246, + 40, + 166, + 2, // Opcode: SUQADDv2i32 + /* 68450 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 68472 + /* 68455 */ MCD_OPC_CheckPredicate, + 21, + 227, + 140, + 0, // Skip to: 104527 + /* 68460 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 220, + 140, + 0, // Skip to: 104527 + /* 68467 */ MCD_OPC_Decode, + 130, + 10, + 155, + 2, // Opcode: CMGEv2i32 + /* 68472 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 68494 + /* 68477 */ MCD_OPC_CheckPredicate, + 21, + 205, + 140, + 0, // Skip to: 104527 + /* 68482 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 198, + 140, + 0, // Skip to: 104527 + /* 68489 */ MCD_OPC_Decode, + 157, + 7, + 170, + 2, // Opcode: ADDHNv2i64_v2i32 + /* 68494 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 68516 + /* 68499 */ MCD_OPC_CheckPredicate, + 21, + 183, + 140, + 0, // Skip to: 104527 + /* 68504 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 176, + 140, + 0, // Skip to: 104527 + /* 68511 */ MCD_OPC_Decode, + 253, + 36, + 155, + 2, // Opcode: SSHLv2i32 + /* 68516 */ MCD_OPC_FilterValue, + 18, + 33, + 0, + 0, // Skip to: 68554 + /* 68521 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 68524 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 68539 + /* 68529 */ MCD_OPC_CheckPredicate, + 21, + 153, + 140, + 0, // Skip to: 104527 + /* 68534 */ MCD_OPC_Decode, + 221, + 9, + 156, + 2, // Opcode: CLSv2i32 + /* 68539 */ MCD_OPC_FilterValue, + 33, + 143, + 140, + 0, // Skip to: 104527 + /* 68544 */ MCD_OPC_CheckPredicate, + 21, + 138, + 140, + 0, // Skip to: 104527 + /* 68549 */ MCD_OPC_Decode, + 157, + 36, + 161, + 2, // Opcode: SQXTNv2i32 + /* 68554 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 68576 + /* 68559 */ MCD_OPC_CheckPredicate, + 21, + 123, + 140, + 0, // Skip to: 104527 + /* 68564 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 116, + 140, + 0, // Skip to: 104527 + /* 68571 */ MCD_OPC_Decode, + 206, + 35, + 155, + 2, // Opcode: SQSHLv2i32 + /* 68576 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 68598 + /* 68581 */ MCD_OPC_CheckPredicate, + 21, + 101, + 140, + 0, // Skip to: 104527 + /* 68586 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 94, + 140, + 0, // Skip to: 104527 + /* 68593 */ MCD_OPC_Decode, + 225, + 29, + 172, + 2, // Opcode: SABALv2i32_v2i64 + /* 68598 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 68620 + /* 68603 */ MCD_OPC_CheckPredicate, + 21, + 79, + 140, + 0, // Skip to: 104527 + /* 68608 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 72, + 140, + 0, // Skip to: 104527 + /* 68615 */ MCD_OPC_Decode, + 209, + 36, + 155, + 2, // Opcode: SRSHLv2i32 + /* 68620 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 68642 + /* 68625 */ MCD_OPC_CheckPredicate, + 21, + 57, + 140, + 0, // Skip to: 104527 + /* 68630 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 50, + 140, + 0, // Skip to: 104527 + /* 68637 */ MCD_OPC_Decode, + 150, + 47, + 155, + 2, // Opcode: UZP2v2i32 + /* 68642 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 68664 + /* 68647 */ MCD_OPC_CheckPredicate, + 21, + 35, + 140, + 0, // Skip to: 104527 + /* 68652 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 28, + 140, + 0, // Skip to: 104527 + /* 68659 */ MCD_OPC_Decode, + 133, + 35, + 155, + 2, // Opcode: SQRSHLv2i32 + /* 68664 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 68686 + /* 68669 */ MCD_OPC_CheckPredicate, + 21, + 13, + 140, + 0, // Skip to: 104527 + /* 68674 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 6, + 140, + 0, // Skip to: 104527 + /* 68681 */ MCD_OPC_Decode, + 174, + 40, + 170, + 2, // Opcode: SUBHNv2i64_v2i32 + /* 68686 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 68708 + /* 68691 */ MCD_OPC_CheckPredicate, + 21, + 247, + 139, + 0, // Skip to: 104527 + /* 68696 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 240, + 139, + 0, // Skip to: 104527 + /* 68703 */ MCD_OPC_Decode, + 244, + 31, + 155, + 2, // Opcode: SMAXv2i32 + /* 68708 */ MCD_OPC_FilterValue, + 26, + 56, + 0, + 0, // Skip to: 68769 + /* 68713 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 68716 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 68731 + /* 68721 */ MCD_OPC_CheckPredicate, + 21, + 217, + 139, + 0, // Skip to: 104527 + /* 68726 */ MCD_OPC_Decode, + 209, + 41, + 155, + 2, // Opcode: TRN2v2i32 + /* 68731 */ MCD_OPC_FilterValue, + 1, + 207, + 139, + 0, // Skip to: 104527 + /* 68736 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 68739 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 68754 + /* 68744 */ MCD_OPC_CheckPredicate, + 21, + 194, + 139, + 0, // Skip to: 104527 + /* 68749 */ MCD_OPC_Decode, + 138, + 30, + 166, + 2, // Opcode: SADALPv2i32_v1i64 + /* 68754 */ MCD_OPC_FilterValue, + 1, + 184, + 139, + 0, // Skip to: 104527 + /* 68759 */ MCD_OPC_CheckPredicate, + 30, + 179, + 139, + 0, // Skip to: 104527 + /* 68764 */ MCD_OPC_Decode, + 195, + 8, + 184, + 2, // Opcode: BFCVTN + /* 68769 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 68791 + /* 68774 */ MCD_OPC_CheckPredicate, + 21, + 164, + 139, + 0, // Skip to: 104527 + /* 68779 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 157, + 139, + 0, // Skip to: 104527 + /* 68786 */ MCD_OPC_Decode, + 150, + 32, + 155, + 2, // Opcode: SMINv2i32 + /* 68791 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 68813 + /* 68796 */ MCD_OPC_CheckPredicate, + 21, + 142, + 139, + 0, // Skip to: 104527 + /* 68801 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 135, + 139, + 0, // Skip to: 104527 + /* 68808 */ MCD_OPC_Decode, + 247, + 29, + 151, + 2, // Opcode: SABDLv2i32_v2i64 + /* 68813 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 68835 + /* 68818 */ MCD_OPC_CheckPredicate, + 21, + 120, + 139, + 0, // Skip to: 104527 + /* 68823 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 113, + 139, + 0, // Skip to: 104527 + /* 68830 */ MCD_OPC_Decode, + 129, + 30, + 155, + 2, // Opcode: SABDv2i32 + /* 68835 */ MCD_OPC_FilterValue, + 30, + 40, + 0, + 0, // Skip to: 68880 + /* 68840 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 68843 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 68858 + /* 68848 */ MCD_OPC_CheckPredicate, + 21, + 90, + 139, + 0, // Skip to: 104527 + /* 68853 */ MCD_OPC_Decode, + 145, + 48, + 155, + 2, // Opcode: ZIP2v2i32 + /* 68858 */ MCD_OPC_FilterValue, + 1, + 80, + 139, + 0, // Skip to: 104527 + /* 68863 */ MCD_OPC_CheckPredicate, + 21, + 75, + 139, + 0, // Skip to: 104527 + /* 68868 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 68, + 139, + 0, // Skip to: 104527 + /* 68875 */ MCD_OPC_Decode, + 130, + 33, + 156, + 2, // Opcode: SQABSv2i32 + /* 68880 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 68902 + /* 68885 */ MCD_OPC_CheckPredicate, + 21, + 53, + 139, + 0, // Skip to: 104527 + /* 68890 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 46, + 139, + 0, // Skip to: 104527 + /* 68897 */ MCD_OPC_Decode, + 235, + 29, + 176, + 2, // Opcode: SABAv2i32 + /* 68902 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 68924 + /* 68907 */ MCD_OPC_CheckPredicate, + 21, + 31, + 139, + 0, // Skip to: 104527 + /* 68912 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 24, + 139, + 0, // Skip to: 104527 + /* 68919 */ MCD_OPC_Decode, + 167, + 32, + 172, + 2, // Opcode: SMLALv2i32_v2i64 + /* 68924 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 68946 + /* 68929 */ MCD_OPC_CheckPredicate, + 21, + 9, + 139, + 0, // Skip to: 104527 + /* 68934 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 2, + 139, + 0, // Skip to: 104527 + /* 68941 */ MCD_OPC_Decode, + 212, + 7, + 155, + 2, // Opcode: ADDv2i32 + /* 68946 */ MCD_OPC_FilterValue, + 34, + 33, + 0, + 0, // Skip to: 68984 + /* 68951 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 68954 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 68969 + /* 68959 */ MCD_OPC_CheckPredicate, + 21, + 235, + 138, + 0, // Skip to: 104527 + /* 68964 */ MCD_OPC_Decode, + 147, + 10, + 156, + 2, // Opcode: CMGTv2i32rz + /* 68969 */ MCD_OPC_FilterValue, + 33, + 225, + 138, + 0, // Skip to: 104527 + /* 68974 */ MCD_OPC_CheckPredicate, + 21, + 220, + 138, + 0, // Skip to: 104527 + /* 68979 */ MCD_OPC_Decode, + 161, + 19, + 156, + 2, // Opcode: FRINTPv2f32 + /* 68984 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 69006 + /* 68989 */ MCD_OPC_CheckPredicate, + 21, + 205, + 138, + 0, // Skip to: 104527 + /* 68994 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 198, + 138, + 0, // Skip to: 104527 + /* 69001 */ MCD_OPC_Decode, + 164, + 11, + 155, + 2, // Opcode: CMTSTv2i32 + /* 69006 */ MCD_OPC_FilterValue, + 36, + 17, + 0, + 0, // Skip to: 69028 + /* 69011 */ MCD_OPC_CheckPredicate, + 21, + 183, + 138, + 0, // Skip to: 104527 + /* 69016 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 176, + 138, + 0, // Skip to: 104527 + /* 69023 */ MCD_OPC_Decode, + 203, + 33, + 172, + 2, // Opcode: SQDMLALv2i32_v2i64 + /* 69028 */ MCD_OPC_FilterValue, + 37, + 33, + 0, + 0, // Skip to: 69066 + /* 69033 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 69036 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 69051 + /* 69041 */ MCD_OPC_CheckPredicate, + 32, + 153, + 138, + 0, // Skip to: 104527 + /* 69046 */ MCD_OPC_Decode, + 247, + 30, + 176, + 2, // Opcode: SDOTv8i8 + /* 69051 */ MCD_OPC_FilterValue, + 1, + 143, + 138, + 0, // Skip to: 104527 + /* 69056 */ MCD_OPC_CheckPredicate, + 21, + 138, + 138, + 0, // Skip to: 104527 + /* 69061 */ MCD_OPC_Decode, + 150, + 27, + 176, + 2, // Opcode: MLAv2i32 + /* 69066 */ MCD_OPC_FilterValue, + 38, + 33, + 0, + 0, // Skip to: 69104 + /* 69071 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 69074 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 69089 + /* 69079 */ MCD_OPC_CheckPredicate, + 21, + 115, + 138, + 0, // Skip to: 104527 + /* 69084 */ MCD_OPC_Decode, + 243, + 9, + 156, + 2, // Opcode: CMEQv2i32rz + /* 69089 */ MCD_OPC_FilterValue, + 33, + 105, + 138, + 0, // Skip to: 104527 + /* 69094 */ MCD_OPC_CheckPredicate, + 21, + 100, + 138, + 0, // Skip to: 104527 + /* 69099 */ MCD_OPC_Decode, + 183, + 19, + 156, + 2, // Opcode: FRINTZv2f32 + /* 69104 */ MCD_OPC_FilterValue, + 39, + 33, + 0, + 0, // Skip to: 69142 + /* 69109 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 69112 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 69127 + /* 69117 */ MCD_OPC_CheckPredicate, + 33, + 77, + 138, + 0, // Skip to: 104527 + /* 69122 */ MCD_OPC_Decode, + 154, + 46, + 176, + 2, // Opcode: USDOTv8i8 + /* 69127 */ MCD_OPC_FilterValue, + 1, + 67, + 138, + 0, // Skip to: 104527 + /* 69132 */ MCD_OPC_CheckPredicate, + 21, + 62, + 138, + 0, // Skip to: 104527 + /* 69137 */ MCD_OPC_Decode, + 228, + 27, + 155, + 2, // Opcode: MULv2i32 + /* 69142 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 69164 + /* 69147 */ MCD_OPC_CheckPredicate, + 21, + 47, + 138, + 0, // Skip to: 104527 + /* 69152 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 40, + 138, + 0, // Skip to: 104527 + /* 69159 */ MCD_OPC_Decode, + 187, + 32, + 172, + 2, // Opcode: SMLSLv2i32_v2i64 + /* 69164 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 69186 + /* 69169 */ MCD_OPC_CheckPredicate, + 21, + 25, + 138, + 0, // Skip to: 104527 + /* 69174 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 18, + 138, + 0, // Skip to: 104527 + /* 69181 */ MCD_OPC_Decode, + 221, + 31, + 155, + 2, // Opcode: SMAXPv2i32 + /* 69186 */ MCD_OPC_FilterValue, + 42, + 33, + 0, + 0, // Skip to: 69224 + /* 69191 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 69194 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 69209 + /* 69199 */ MCD_OPC_CheckPredicate, + 21, + 251, + 137, + 0, // Skip to: 104527 + /* 69204 */ MCD_OPC_Decode, + 190, + 10, + 156, + 2, // Opcode: CMLTv2i32rz + /* 69209 */ MCD_OPC_FilterValue, + 33, + 241, + 137, + 0, // Skip to: 104527 + /* 69214 */ MCD_OPC_CheckPredicate, + 21, + 236, + 137, + 0, // Skip to: 104527 + /* 69219 */ MCD_OPC_Decode, + 145, + 15, + 156, + 2, // Opcode: FCVTPSv2f32 + /* 69224 */ MCD_OPC_FilterValue, + 43, + 17, + 0, + 0, // Skip to: 69246 + /* 69229 */ MCD_OPC_CheckPredicate, + 21, + 221, + 137, + 0, // Skip to: 104527 + /* 69234 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 214, + 137, + 0, // Skip to: 104527 + /* 69241 */ MCD_OPC_Decode, + 255, + 31, + 155, + 2, // Opcode: SMINPv2i32 + /* 69246 */ MCD_OPC_FilterValue, + 44, + 17, + 0, + 0, // Skip to: 69268 + /* 69251 */ MCD_OPC_CheckPredicate, + 21, + 199, + 137, + 0, // Skip to: 104527 + /* 69256 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 192, + 137, + 0, // Skip to: 104527 + /* 69263 */ MCD_OPC_Decode, + 228, + 33, + 172, + 2, // Opcode: SQDMLSLv2i32_v2i64 + /* 69268 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 69290 + /* 69273 */ MCD_OPC_CheckPredicate, + 21, + 177, + 137, + 0, // Skip to: 104527 + /* 69278 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 170, + 137, + 0, // Skip to: 104527 + /* 69285 */ MCD_OPC_Decode, + 246, + 33, + 155, + 2, // Opcode: SQDMULHv2i32 + /* 69290 */ MCD_OPC_FilterValue, + 46, + 33, + 0, + 0, // Skip to: 69328 + /* 69295 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 69298 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 69313 + /* 69303 */ MCD_OPC_CheckPredicate, + 21, + 147, + 137, + 0, // Skip to: 104527 + /* 69308 */ MCD_OPC_Decode, + 134, + 7, + 156, + 2, // Opcode: ABSv2i32 + /* 69313 */ MCD_OPC_FilterValue, + 33, + 137, + 137, + 0, // Skip to: 104527 + /* 69318 */ MCD_OPC_CheckPredicate, + 21, + 132, + 137, + 0, // Skip to: 104527 + /* 69323 */ MCD_OPC_Decode, + 196, + 15, + 156, + 2, // Opcode: FCVTZSv2f32 + /* 69328 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 69350 + /* 69333 */ MCD_OPC_CheckPredicate, + 21, + 117, + 137, + 0, // Skip to: 104527 + /* 69338 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 110, + 137, + 0, // Skip to: 104527 + /* 69345 */ MCD_OPC_Decode, + 169, + 7, + 155, + 2, // Opcode: ADDPv2i32 + /* 69350 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 69372 + /* 69355 */ MCD_OPC_CheckPredicate, + 21, + 95, + 137, + 0, // Skip to: 104527 + /* 69360 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 88, + 137, + 0, // Skip to: 104527 + /* 69367 */ MCD_OPC_Decode, + 233, + 32, + 151, + 2, // Opcode: SMULLv2i32_v2i64 + /* 69372 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 69394 + /* 69377 */ MCD_OPC_CheckPredicate, + 21, + 73, + 137, + 0, // Skip to: 104527 + /* 69382 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 66, + 137, + 0, // Skip to: 104527 + /* 69389 */ MCD_OPC_Decode, + 239, + 16, + 155, + 2, // Opcode: FMINNMv2f32 + /* 69394 */ MCD_OPC_FilterValue, + 50, + 48, + 0, + 0, // Skip to: 69447 + /* 69399 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 69402 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 69417 + /* 69407 */ MCD_OPC_CheckPredicate, + 21, + 43, + 137, + 0, // Skip to: 104527 + /* 69412 */ MCD_OPC_Decode, + 222, + 13, + 156, + 2, // Opcode: FCMGTv2i32rz + /* 69417 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 69432 + /* 69422 */ MCD_OPC_CheckPredicate, + 21, + 28, + 137, + 0, // Skip to: 104527 + /* 69427 */ MCD_OPC_Decode, + 222, + 45, + 156, + 2, // Opcode: URECPEv2i32 + /* 69432 */ MCD_OPC_FilterValue, + 48, + 18, + 137, + 0, // Skip to: 104527 + /* 69437 */ MCD_OPC_CheckPredicate, + 23, + 13, + 137, + 0, // Skip to: 104527 + /* 69442 */ MCD_OPC_Decode, + 230, + 16, + 167, + 2, // Opcode: FMINNMVv4i16v + /* 69447 */ MCD_OPC_FilterValue, + 51, + 17, + 0, + 0, // Skip to: 69469 + /* 69452 */ MCD_OPC_CheckPredicate, + 21, + 254, + 136, + 0, // Skip to: 104527 + /* 69457 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 247, + 136, + 0, // Skip to: 104527 + /* 69464 */ MCD_OPC_Decode, + 197, + 17, + 176, + 2, // Opcode: FMLSv2f32 + /* 69469 */ MCD_OPC_FilterValue, + 52, + 17, + 0, + 0, // Skip to: 69491 + /* 69474 */ MCD_OPC_CheckPredicate, + 21, + 232, + 136, + 0, // Skip to: 104527 + /* 69479 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 225, + 136, + 0, // Skip to: 104527 + /* 69486 */ MCD_OPC_Decode, + 141, + 34, + 151, + 2, // Opcode: SQDMULLv2i32_v2i64 + /* 69491 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 69513 + /* 69496 */ MCD_OPC_CheckPredicate, + 21, + 210, + 136, + 0, // Skip to: 104527 + /* 69501 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 203, + 136, + 0, // Skip to: 104527 + /* 69508 */ MCD_OPC_Decode, + 242, + 19, + 155, + 2, // Opcode: FSUBv2f32 + /* 69513 */ MCD_OPC_FilterValue, + 54, + 33, + 0, + 0, // Skip to: 69551 + /* 69518 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 69521 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 69536 + /* 69526 */ MCD_OPC_CheckPredicate, + 21, + 180, + 136, + 0, // Skip to: 104527 + /* 69531 */ MCD_OPC_Decode, + 178, + 13, + 156, + 2, // Opcode: FCMEQv2i32rz + /* 69536 */ MCD_OPC_FilterValue, + 33, + 170, + 136, + 0, // Skip to: 104527 + /* 69541 */ MCD_OPC_CheckPredicate, + 21, + 165, + 136, + 0, // Skip to: 104527 + /* 69546 */ MCD_OPC_Decode, + 197, + 18, + 156, + 2, // Opcode: FRECPEv2f32 + /* 69551 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 69573 + /* 69556 */ MCD_OPC_CheckPredicate, + 21, + 150, + 136, + 0, // Skip to: 104527 + /* 69561 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 143, + 136, + 0, // Skip to: 104527 + /* 69568 */ MCD_OPC_Decode, + 132, + 14, + 156, + 2, // Opcode: FCMLTv2i32rz + /* 69573 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 69595 + /* 69578 */ MCD_OPC_CheckPredicate, + 25, + 128, + 136, + 0, // Skip to: 104527 + /* 69583 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 121, + 136, + 0, // Skip to: 104527 + /* 69590 */ MCD_OPC_Decode, + 186, + 17, + 176, + 2, // Opcode: FMLSLv4f16 + /* 69595 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 69617 + /* 69600 */ MCD_OPC_CheckPredicate, + 21, + 106, + 136, + 0, // Skip to: 104527 + /* 69605 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 99, + 136, + 0, // Skip to: 104527 + /* 69612 */ MCD_OPC_Decode, + 140, + 17, + 155, + 2, // Opcode: FMINv2f32 + /* 69617 */ MCD_OPC_FilterValue, + 62, + 33, + 0, + 0, // Skip to: 69655 + /* 69622 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 69625 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 69640 + /* 69630 */ MCD_OPC_CheckPredicate, + 21, + 76, + 136, + 0, // Skip to: 104527 + /* 69635 */ MCD_OPC_Decode, + 217, + 12, + 156, + 2, // Opcode: FABSv2f32 + /* 69640 */ MCD_OPC_FilterValue, + 48, + 66, + 136, + 0, // Skip to: 104527 + /* 69645 */ MCD_OPC_CheckPredicate, + 23, + 61, + 136, + 0, // Skip to: 104527 + /* 69650 */ MCD_OPC_Decode, + 131, + 17, + 167, + 2, // Opcode: FMINVv4i16v + /* 69655 */ MCD_OPC_FilterValue, + 63, + 51, + 136, + 0, // Skip to: 104527 + /* 69660 */ MCD_OPC_CheckPredicate, + 21, + 46, + 136, + 0, // Skip to: 104527 + /* 69665 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 39, + 136, + 0, // Skip to: 104527 + /* 69672 */ MCD_OPC_Decode, + 205, + 19, + 155, + 2, // Opcode: FRSQRTSv2f32 + /* 69677 */ MCD_OPC_FilterValue, + 1, + 141, + 5, + 0, // Skip to: 71103 + /* 69682 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 69685 */ MCD_OPC_FilterValue, + 0, + 135, + 0, + 0, // Skip to: 69825 + /* 69690 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 69693 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 69715 + /* 69698 */ MCD_OPC_CheckPredicate, + 21, + 8, + 136, + 0, // Skip to: 104527 + /* 69703 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 1, + 136, + 0, // Skip to: 104527 + /* 69710 */ MCD_OPC_Decode, + 161, + 42, + 151, + 2, // Opcode: UADDLv2i32_v2i64 + /* 69715 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 69737 + /* 69720 */ MCD_OPC_CheckPredicate, + 21, + 242, + 135, + 0, // Skip to: 104527 + /* 69725 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 235, + 135, + 0, // Skip to: 104527 + /* 69732 */ MCD_OPC_Decode, + 243, + 42, + 155, + 2, // Opcode: UHADDv2i32 + /* 69737 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 69759 + /* 69742 */ MCD_OPC_CheckPredicate, + 21, + 220, + 135, + 0, // Skip to: 104527 + /* 69747 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 213, + 135, + 0, // Skip to: 104527 + /* 69754 */ MCD_OPC_Decode, + 174, + 44, + 155, + 2, // Opcode: UQADDv2i32 + /* 69759 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 69781 + /* 69764 */ MCD_OPC_CheckPredicate, + 21, + 198, + 135, + 0, // Skip to: 104527 + /* 69769 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 191, + 135, + 0, // Skip to: 104527 + /* 69776 */ MCD_OPC_Decode, + 177, + 42, + 159, + 2, // Opcode: UADDWv2i32_v2i64 + /* 69781 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 69803 + /* 69786 */ MCD_OPC_CheckPredicate, + 21, + 176, + 135, + 0, // Skip to: 104527 + /* 69791 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 169, + 135, + 0, // Skip to: 104527 + /* 69798 */ MCD_OPC_Decode, + 229, + 45, + 155, + 2, // Opcode: URHADDv2i32 + /* 69803 */ MCD_OPC_FilterValue, + 7, + 159, + 135, + 0, // Skip to: 104527 + /* 69808 */ MCD_OPC_CheckPredicate, + 21, + 154, + 135, + 0, // Skip to: 104527 + /* 69813 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 147, + 135, + 0, // Skip to: 104527 + /* 69820 */ MCD_OPC_Decode, + 239, + 8, + 176, + 2, // Opcode: BITv8i8 + /* 69825 */ MCD_OPC_FilterValue, + 1, + 211, + 0, + 0, // Skip to: 70041 + /* 69830 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 69833 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 69855 + /* 69838 */ MCD_OPC_CheckPredicate, + 21, + 124, + 135, + 0, // Skip to: 104527 + /* 69843 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 117, + 135, + 0, // Skip to: 104527 + /* 69850 */ MCD_OPC_Decode, + 223, + 46, + 151, + 2, // Opcode: USUBLv2i32_v2i64 + /* 69855 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 69877 + /* 69860 */ MCD_OPC_CheckPredicate, + 21, + 102, + 135, + 0, // Skip to: 104527 + /* 69865 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 95, + 135, + 0, // Skip to: 104527 + /* 69872 */ MCD_OPC_Decode, + 129, + 43, + 155, + 2, // Opcode: UHSUBv2i32 + /* 69877 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 69915 + /* 69882 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 69885 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 69900 + /* 69890 */ MCD_OPC_CheckPredicate, + 21, + 72, + 135, + 0, // Skip to: 104527 + /* 69895 */ MCD_OPC_Decode, + 147, + 42, + 156, + 2, // Opcode: UADDLPv2i32_v1i64 + /* 69900 */ MCD_OPC_FilterValue, + 33, + 62, + 135, + 0, // Skip to: 104527 + /* 69905 */ MCD_OPC_CheckPredicate, + 21, + 57, + 135, + 0, // Skip to: 104527 + /* 69910 */ MCD_OPC_Decode, + 172, + 36, + 161, + 2, // Opcode: SQXTUNv2i32 + /* 69915 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 69937 + /* 69920 */ MCD_OPC_CheckPredicate, + 21, + 42, + 135, + 0, // Skip to: 104527 + /* 69925 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 35, + 135, + 0, // Skip to: 104527 + /* 69932 */ MCD_OPC_Decode, + 200, + 45, + 155, + 2, // Opcode: UQSUBv2i32 + /* 69937 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 69959 + /* 69942 */ MCD_OPC_CheckPredicate, + 21, + 20, + 135, + 0, // Skip to: 104527 + /* 69947 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 13, + 135, + 0, // Skip to: 104527 + /* 69954 */ MCD_OPC_Decode, + 235, + 46, + 159, + 2, // Opcode: USUBWv2i32_v2i64 + /* 69959 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 69981 + /* 69964 */ MCD_OPC_CheckPredicate, + 21, + 254, + 134, + 0, // Skip to: 104527 + /* 69969 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 247, + 134, + 0, // Skip to: 104527 + /* 69976 */ MCD_OPC_Decode, + 160, + 10, + 155, + 2, // Opcode: CMHIv2i32 + /* 69981 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 70019 + /* 69986 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 69989 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 70004 + /* 69994 */ MCD_OPC_CheckPredicate, + 21, + 224, + 134, + 0, // Skip to: 104527 + /* 69999 */ MCD_OPC_Decode, + 198, + 46, + 166, + 2, // Opcode: USQADDv2i32 + /* 70004 */ MCD_OPC_FilterValue, + 33, + 214, + 134, + 0, // Skip to: 104527 + /* 70009 */ MCD_OPC_CheckPredicate, + 21, + 209, + 134, + 0, // Skip to: 104527 + /* 70014 */ MCD_OPC_Decode, + 153, + 31, + 175, + 2, // Opcode: SHLLv2i32 + /* 70019 */ MCD_OPC_FilterValue, + 7, + 199, + 134, + 0, // Skip to: 104527 + /* 70024 */ MCD_OPC_CheckPredicate, + 21, + 194, + 134, + 0, // Skip to: 104527 + /* 70029 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 187, + 134, + 0, // Skip to: 104527 + /* 70036 */ MCD_OPC_Decode, + 168, + 10, + 155, + 2, // Opcode: CMHSv2i32 + /* 70041 */ MCD_OPC_FilterValue, + 2, + 173, + 0, + 0, // Skip to: 70219 + /* 70046 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 70049 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 70071 + /* 70054 */ MCD_OPC_CheckPredicate, + 21, + 164, + 134, + 0, // Skip to: 104527 + /* 70059 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 157, + 134, + 0, // Skip to: 104527 + /* 70066 */ MCD_OPC_Decode, + 136, + 29, + 170, + 2, // Opcode: RADDHNv2i64_v2i32 + /* 70071 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 70093 + /* 70076 */ MCD_OPC_CheckPredicate, + 21, + 142, + 134, + 0, // Skip to: 104527 + /* 70081 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 135, + 134, + 0, // Skip to: 104527 + /* 70088 */ MCD_OPC_Decode, + 169, + 46, + 155, + 2, // Opcode: USHLv2i32 + /* 70093 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 70131 + /* 70098 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 70101 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 70116 + /* 70106 */ MCD_OPC_CheckPredicate, + 21, + 112, + 134, + 0, // Skip to: 104527 + /* 70111 */ MCD_OPC_Decode, + 233, + 9, + 156, + 2, // Opcode: CLZv2i32 + /* 70116 */ MCD_OPC_FilterValue, + 33, + 102, + 134, + 0, // Skip to: 104527 + /* 70121 */ MCD_OPC_CheckPredicate, + 21, + 97, + 134, + 0, // Skip to: 104527 + /* 70126 */ MCD_OPC_Decode, + 216, + 45, + 161, + 2, // Opcode: UQXTNv2i32 + /* 70131 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 70153 + /* 70136 */ MCD_OPC_CheckPredicate, + 21, + 82, + 134, + 0, // Skip to: 104527 + /* 70141 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 75, + 134, + 0, // Skip to: 104527 + /* 70148 */ MCD_OPC_Decode, + 152, + 45, + 155, + 2, // Opcode: UQSHLv2i32 + /* 70153 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 70175 + /* 70158 */ MCD_OPC_CheckPredicate, + 21, + 60, + 134, + 0, // Skip to: 104527 + /* 70163 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 53, + 134, + 0, // Skip to: 104527 + /* 70170 */ MCD_OPC_Decode, + 225, + 41, + 172, + 2, // Opcode: UABALv2i32_v2i64 + /* 70175 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 70197 + /* 70180 */ MCD_OPC_CheckPredicate, + 21, + 38, + 134, + 0, // Skip to: 104527 + /* 70185 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 31, + 134, + 0, // Skip to: 104527 + /* 70192 */ MCD_OPC_Decode, + 244, + 45, + 155, + 2, // Opcode: URSHLv2i32 + /* 70197 */ MCD_OPC_FilterValue, + 7, + 21, + 134, + 0, // Skip to: 104527 + /* 70202 */ MCD_OPC_CheckPredicate, + 21, + 16, + 134, + 0, // Skip to: 104527 + /* 70207 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 9, + 134, + 0, // Skip to: 104527 + /* 70214 */ MCD_OPC_Decode, + 237, + 44, + 155, + 2, // Opcode: UQRSHLv2i32 + /* 70219 */ MCD_OPC_FilterValue, + 3, + 179, + 0, + 0, // Skip to: 70403 + /* 70224 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 70227 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 70249 + /* 70232 */ MCD_OPC_CheckPredicate, + 21, + 242, + 133, + 0, // Skip to: 104527 + /* 70237 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 235, + 133, + 0, // Skip to: 104527 + /* 70244 */ MCD_OPC_Decode, + 212, + 29, + 170, + 2, // Opcode: RSUBHNv2i64_v2i32 + /* 70249 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 70271 + /* 70254 */ MCD_OPC_CheckPredicate, + 21, + 220, + 133, + 0, // Skip to: 104527 + /* 70259 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 213, + 133, + 0, // Skip to: 104527 + /* 70266 */ MCD_OPC_Decode, + 163, + 43, + 155, + 2, // Opcode: UMAXv2i32 + /* 70271 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 70293 + /* 70276 */ MCD_OPC_CheckPredicate, + 21, + 198, + 133, + 0, // Skip to: 104527 + /* 70281 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 191, + 133, + 0, // Skip to: 104527 + /* 70288 */ MCD_OPC_Decode, + 138, + 42, + 166, + 2, // Opcode: UADALPv2i32_v1i64 + /* 70293 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 70315 + /* 70298 */ MCD_OPC_CheckPredicate, + 21, + 176, + 133, + 0, // Skip to: 104527 + /* 70303 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 169, + 133, + 0, // Skip to: 104527 + /* 70310 */ MCD_OPC_Decode, + 196, + 43, + 155, + 2, // Opcode: UMINv2i32 + /* 70315 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 70337 + /* 70320 */ MCD_OPC_CheckPredicate, + 21, + 154, + 133, + 0, // Skip to: 104527 + /* 70325 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 147, + 133, + 0, // Skip to: 104527 + /* 70332 */ MCD_OPC_Decode, + 247, + 41, + 151, + 2, // Opcode: UABDLv2i32_v2i64 + /* 70337 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 70359 + /* 70342 */ MCD_OPC_CheckPredicate, + 21, + 132, + 133, + 0, // Skip to: 104527 + /* 70347 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 125, + 133, + 0, // Skip to: 104527 + /* 70354 */ MCD_OPC_Decode, + 129, + 42, + 155, + 2, // Opcode: UABDv2i32 + /* 70359 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 70381 + /* 70364 */ MCD_OPC_CheckPredicate, + 21, + 110, + 133, + 0, // Skip to: 104527 + /* 70369 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 103, + 133, + 0, // Skip to: 104527 + /* 70376 */ MCD_OPC_Decode, + 179, + 34, + 156, + 2, // Opcode: SQNEGv2i32 + /* 70381 */ MCD_OPC_FilterValue, + 7, + 93, + 133, + 0, // Skip to: 104527 + /* 70386 */ MCD_OPC_CheckPredicate, + 21, + 88, + 133, + 0, // Skip to: 104527 + /* 70391 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 81, + 133, + 0, // Skip to: 104527 + /* 70398 */ MCD_OPC_Decode, + 235, + 41, + 176, + 2, // Opcode: UABAv2i32 + /* 70403 */ MCD_OPC_FilterValue, + 4, + 199, + 0, + 0, // Skip to: 70607 + /* 70408 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 70411 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 70433 + /* 70416 */ MCD_OPC_CheckPredicate, + 21, + 58, + 133, + 0, // Skip to: 104527 + /* 70421 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 51, + 133, + 0, // Skip to: 104527 + /* 70428 */ MCD_OPC_Decode, + 213, + 43, + 172, + 2, // Opcode: UMLALv2i32_v2i64 + /* 70433 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 70471 + /* 70438 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 70441 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 70456 + /* 70446 */ MCD_OPC_CheckPredicate, + 28, + 28, + 133, + 0, // Skip to: 104527 + /* 70451 */ MCD_OPC_Decode, + 202, + 34, + 176, + 2, // Opcode: SQRDMLAHv2i32 + /* 70456 */ MCD_OPC_FilterValue, + 1, + 18, + 133, + 0, // Skip to: 104527 + /* 70461 */ MCD_OPC_CheckPredicate, + 21, + 13, + 133, + 0, // Skip to: 104527 + /* 70466 */ MCD_OPC_Decode, + 218, + 40, + 155, + 2, // Opcode: SUBv2i32 + /* 70471 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 70493 + /* 70476 */ MCD_OPC_CheckPredicate, + 21, + 254, + 132, + 0, // Skip to: 104527 + /* 70481 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 247, + 132, + 0, // Skip to: 104527 + /* 70488 */ MCD_OPC_Decode, + 131, + 10, + 156, + 2, // Opcode: CMGEv2i32rz + /* 70493 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 70531 + /* 70498 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 70501 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 70516 + /* 70506 */ MCD_OPC_CheckPredicate, + 28, + 224, + 132, + 0, // Skip to: 104527 + /* 70511 */ MCD_OPC_Decode, + 221, + 34, + 176, + 2, // Opcode: SQRDMLSHv2i32 + /* 70516 */ MCD_OPC_FilterValue, + 1, + 214, + 132, + 0, // Skip to: 104527 + /* 70521 */ MCD_OPC_CheckPredicate, + 21, + 209, + 132, + 0, // Skip to: 104527 + /* 70526 */ MCD_OPC_Decode, + 242, + 9, + 155, + 2, // Opcode: CMEQv2i32 + /* 70531 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 70569 + /* 70536 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 70539 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 70554 + /* 70544 */ MCD_OPC_CheckPredicate, + 32, + 186, + 132, + 0, // Skip to: 104527 + /* 70549 */ MCD_OPC_Decode, + 237, + 42, + 176, + 2, // Opcode: UDOTv8i8 + /* 70554 */ MCD_OPC_FilterValue, + 1, + 176, + 132, + 0, // Skip to: 104527 + /* 70559 */ MCD_OPC_CheckPredicate, + 21, + 171, + 132, + 0, // Skip to: 104527 + /* 70564 */ MCD_OPC_Decode, + 167, + 27, + 176, + 2, // Opcode: MLSv2i32 + /* 70569 */ MCD_OPC_FilterValue, + 6, + 161, + 132, + 0, // Skip to: 104527 + /* 70574 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 70577 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 70592 + /* 70582 */ MCD_OPC_CheckPredicate, + 21, + 148, + 132, + 0, // Skip to: 104527 + /* 70587 */ MCD_OPC_Decode, + 182, + 10, + 156, + 2, // Opcode: CMLEv2i32rz + /* 70592 */ MCD_OPC_FilterValue, + 33, + 138, + 132, + 0, // Skip to: 104527 + /* 70597 */ MCD_OPC_CheckPredicate, + 21, + 133, + 132, + 0, // Skip to: 104527 + /* 70602 */ MCD_OPC_Decode, + 128, + 19, + 156, + 2, // Opcode: FRINTIv2f32 + /* 70607 */ MCD_OPC_FilterValue, + 5, + 151, + 0, + 0, // Skip to: 70763 + /* 70612 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 70615 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 70637 + /* 70620 */ MCD_OPC_CheckPredicate, + 21, + 110, + 132, + 0, // Skip to: 104527 + /* 70625 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 103, + 132, + 0, // Skip to: 104527 + /* 70632 */ MCD_OPC_Decode, + 233, + 43, + 172, + 2, // Opcode: UMLSLv2i32_v2i64 + /* 70637 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 70659 + /* 70642 */ MCD_OPC_CheckPredicate, + 21, + 88, + 132, + 0, // Skip to: 104527 + /* 70647 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 81, + 132, + 0, // Skip to: 104527 + /* 70654 */ MCD_OPC_Decode, + 140, + 43, + 155, + 2, // Opcode: UMAXPv2i32 + /* 70659 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 70681 + /* 70664 */ MCD_OPC_CheckPredicate, + 21, + 66, + 132, + 0, // Skip to: 104527 + /* 70669 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 59, + 132, + 0, // Skip to: 104527 + /* 70676 */ MCD_OPC_Decode, + 159, + 15, + 156, + 2, // Opcode: FCVTPUv2f32 + /* 70681 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 70703 + /* 70686 */ MCD_OPC_CheckPredicate, + 21, + 44, + 132, + 0, // Skip to: 104527 + /* 70691 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 37, + 132, + 0, // Skip to: 104527 + /* 70698 */ MCD_OPC_Decode, + 173, + 43, + 155, + 2, // Opcode: UMINPv2i32 + /* 70703 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 70725 + /* 70708 */ MCD_OPC_CheckPredicate, + 21, + 22, + 132, + 0, // Skip to: 104527 + /* 70713 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 15, + 132, + 0, // Skip to: 104527 + /* 70720 */ MCD_OPC_Decode, + 240, + 34, + 155, + 2, // Opcode: SQRDMULHv2i32 + /* 70725 */ MCD_OPC_FilterValue, + 6, + 5, + 132, + 0, // Skip to: 104527 + /* 70730 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 70733 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 70748 + /* 70738 */ MCD_OPC_CheckPredicate, + 21, + 248, + 131, + 0, // Skip to: 104527 + /* 70743 */ MCD_OPC_Decode, + 252, + 27, + 156, + 2, // Opcode: NEGv2i32 + /* 70748 */ MCD_OPC_FilterValue, + 33, + 238, + 131, + 0, // Skip to: 104527 + /* 70753 */ MCD_OPC_CheckPredicate, + 21, + 233, + 131, + 0, // Skip to: 104527 + /* 70758 */ MCD_OPC_Decode, + 231, + 15, + 156, + 2, // Opcode: FCVTZUv2f32 + /* 70763 */ MCD_OPC_FilterValue, + 6, + 185, + 0, + 0, // Skip to: 70953 + /* 70768 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 70771 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 70877 + /* 70776 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 70779 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 70801 + /* 70784 */ MCD_OPC_CheckPredicate, + 21, + 202, + 131, + 0, // Skip to: 104527 + /* 70789 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 195, + 131, + 0, // Skip to: 104527 + /* 70796 */ MCD_OPC_Decode, + 149, + 44, + 151, + 2, // Opcode: UMULLv2i32_v2i64 + /* 70801 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 70839 + /* 70806 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 70809 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 70824 + /* 70814 */ MCD_OPC_CheckPredicate, + 21, + 172, + 131, + 0, // Skip to: 104527 + /* 70819 */ MCD_OPC_Decode, + 200, + 13, + 156, + 2, // Opcode: FCMGEv2i32rz + /* 70824 */ MCD_OPC_FilterValue, + 33, + 162, + 131, + 0, // Skip to: 104527 + /* 70829 */ MCD_OPC_CheckPredicate, + 21, + 157, + 131, + 0, // Skip to: 104527 + /* 70834 */ MCD_OPC_Decode, + 135, + 46, + 156, + 2, // Opcode: URSQRTEv2i32 + /* 70839 */ MCD_OPC_FilterValue, + 3, + 147, + 131, + 0, // Skip to: 104527 + /* 70844 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 70847 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 70862 + /* 70852 */ MCD_OPC_CheckPredicate, + 21, + 134, + 131, + 0, // Skip to: 104527 + /* 70857 */ MCD_OPC_Decode, + 249, + 13, + 156, + 2, // Opcode: FCMLEv2i32rz + /* 70862 */ MCD_OPC_FilterValue, + 33, + 124, + 131, + 0, // Skip to: 104527 + /* 70867 */ MCD_OPC_CheckPredicate, + 21, + 119, + 131, + 0, // Skip to: 104527 + /* 70872 */ MCD_OPC_Decode, + 194, + 19, + 156, + 2, // Opcode: FRSQRTEv2f32 + /* 70877 */ MCD_OPC_FilterValue, + 1, + 109, + 131, + 0, // Skip to: 104527 + /* 70882 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 70885 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 70900 + /* 70890 */ MCD_OPC_CheckPredicate, + 34, + 96, + 131, + 0, // Skip to: 104527 + /* 70895 */ MCD_OPC_Decode, + 235, + 13, + 214, + 2, // Opcode: FCMLAv2f32 + /* 70900 */ MCD_OPC_FilterValue, + 1, + 86, + 131, + 0, // Skip to: 104527 + /* 70905 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 70908 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 70923 + /* 70913 */ MCD_OPC_CheckPredicate, + 21, + 73, + 131, + 0, // Skip to: 104527 + /* 70918 */ MCD_OPC_Decode, + 218, + 16, + 155, + 2, // Opcode: FMINNMPv2f32 + /* 70923 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 70938 + /* 70928 */ MCD_OPC_CheckPredicate, + 25, + 58, + 131, + 0, // Skip to: 104527 + /* 70933 */ MCD_OPC_Decode, + 178, + 17, + 176, + 2, // Opcode: FMLSL2v4f16 + /* 70938 */ MCD_OPC_FilterValue, + 2, + 48, + 131, + 0, // Skip to: 104527 + /* 70943 */ MCD_OPC_CheckPredicate, + 21, + 43, + 131, + 0, // Skip to: 104527 + /* 70948 */ MCD_OPC_Decode, + 206, + 12, + 155, + 2, // Opcode: FABDv2f32 + /* 70953 */ MCD_OPC_FilterValue, + 7, + 33, + 131, + 0, // Skip to: 104527 + /* 70958 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 70961 */ MCD_OPC_FilterValue, + 1, + 56, + 0, + 0, // Skip to: 71022 + /* 70966 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 70969 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 70984 + /* 70974 */ MCD_OPC_CheckPredicate, + 34, + 12, + 131, + 0, // Skip to: 104527 + /* 70979 */ MCD_OPC_Decode, + 153, + 13, + 215, + 2, // Opcode: FCADDv2f32 + /* 70984 */ MCD_OPC_FilterValue, + 1, + 2, + 131, + 0, // Skip to: 104527 + /* 70989 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 70992 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71007 + /* 70997 */ MCD_OPC_CheckPredicate, + 21, + 245, + 130, + 0, // Skip to: 104527 + /* 71002 */ MCD_OPC_Decode, + 220, + 13, + 155, + 2, // Opcode: FCMGTv2f32 + /* 71007 */ MCD_OPC_FilterValue, + 1, + 235, + 130, + 0, // Skip to: 104527 + /* 71012 */ MCD_OPC_CheckPredicate, + 21, + 230, + 130, + 0, // Skip to: 104527 + /* 71017 */ MCD_OPC_Decode, + 247, + 16, + 155, + 2, // Opcode: FMINPv2f32 + /* 71022 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 71074 + /* 71027 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 71030 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 71052 + /* 71035 */ MCD_OPC_CheckPredicate, + 21, + 207, + 130, + 0, // Skip to: 104527 + /* 71040 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 200, + 130, + 0, // Skip to: 104527 + /* 71047 */ MCD_OPC_Decode, + 165, + 18, + 156, + 2, // Opcode: FNEGv2f32 + /* 71052 */ MCD_OPC_FilterValue, + 33, + 190, + 130, + 0, // Skip to: 104527 + /* 71057 */ MCD_OPC_CheckPredicate, + 21, + 185, + 130, + 0, // Skip to: 104527 + /* 71062 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 178, + 130, + 0, // Skip to: 104527 + /* 71069 */ MCD_OPC_Decode, + 219, + 19, + 156, + 2, // Opcode: FSQRTv2f32 + /* 71074 */ MCD_OPC_FilterValue, + 3, + 168, + 130, + 0, // Skip to: 104527 + /* 71079 */ MCD_OPC_CheckPredicate, + 21, + 163, + 130, + 0, // Skip to: 104527 + /* 71084 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 156, + 130, + 0, // Skip to: 104527 + /* 71091 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 149, + 130, + 0, // Skip to: 104527 + /* 71098 */ MCD_OPC_Decode, + 239, + 12, + 155, + 2, // Opcode: FACGTv2f32 + /* 71103 */ MCD_OPC_FilterValue, + 2, + 179, + 6, + 0, // Skip to: 72823 + /* 71108 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 71111 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 71133 + /* 71116 */ MCD_OPC_CheckPredicate, + 21, + 126, + 130, + 0, // Skip to: 104527 + /* 71121 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 119, + 130, + 0, // Skip to: 104527 + /* 71128 */ MCD_OPC_Decode, + 166, + 30, + 179, + 2, // Opcode: SADDLv4i32_v2i64 + /* 71133 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 71155 + /* 71138 */ MCD_OPC_CheckPredicate, + 21, + 104, + 130, + 0, // Skip to: 104527 + /* 71143 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 97, + 130, + 0, // Skip to: 104527 + /* 71150 */ MCD_OPC_Decode, + 149, + 31, + 179, + 2, // Opcode: SHADDv4i32 + /* 71155 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 71177 + /* 71160 */ MCD_OPC_CheckPredicate, + 21, + 82, + 130, + 0, // Skip to: 104527 + /* 71165 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 75, + 130, + 0, // Skip to: 104527 + /* 71172 */ MCD_OPC_Decode, + 171, + 29, + 184, + 2, // Opcode: REV64v4i32 + /* 71177 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 71199 + /* 71182 */ MCD_OPC_CheckPredicate, + 21, + 60, + 130, + 0, // Skip to: 104527 + /* 71187 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 53, + 130, + 0, // Skip to: 104527 + /* 71194 */ MCD_OPC_Decode, + 156, + 33, + 179, + 2, // Opcode: SQADDv4i32 + /* 71199 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 71221 + /* 71204 */ MCD_OPC_CheckPredicate, + 21, + 38, + 130, + 0, // Skip to: 104527 + /* 71209 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 31, + 130, + 0, // Skip to: 104527 + /* 71216 */ MCD_OPC_Decode, + 181, + 30, + 179, + 2, // Opcode: SADDWv4i32_v2i64 + /* 71221 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 71243 + /* 71226 */ MCD_OPC_CheckPredicate, + 21, + 16, + 130, + 0, // Skip to: 104527 + /* 71231 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 9, + 130, + 0, // Skip to: 104527 + /* 71238 */ MCD_OPC_Decode, + 184, + 36, + 179, + 2, // Opcode: SRHADDv4i32 + /* 71243 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 71265 + /* 71248 */ MCD_OPC_CheckPredicate, + 21, + 250, + 129, + 0, // Skip to: 104527 + /* 71253 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 243, + 129, + 0, // Skip to: 104527 + /* 71260 */ MCD_OPC_Decode, + 137, + 47, + 179, + 2, // Opcode: UZP1v4i32 + /* 71265 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 71287 + /* 71270 */ MCD_OPC_CheckPredicate, + 21, + 228, + 129, + 0, // Skip to: 104527 + /* 71275 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 221, + 129, + 0, // Skip to: 104527 + /* 71282 */ MCD_OPC_Decode, + 158, + 28, + 179, + 2, // Opcode: ORRv16i8 + /* 71287 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 71309 + /* 71292 */ MCD_OPC_CheckPredicate, + 21, + 206, + 129, + 0, // Skip to: 104527 + /* 71297 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 199, + 129, + 0, // Skip to: 104527 + /* 71304 */ MCD_OPC_Decode, + 204, + 37, + 179, + 2, // Opcode: SSUBLv4i32_v2i64 + /* 71309 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 71331 + /* 71314 */ MCD_OPC_CheckPredicate, + 21, + 184, + 129, + 0, // Skip to: 104527 + /* 71319 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 177, + 129, + 0, // Skip to: 104527 + /* 71326 */ MCD_OPC_Decode, + 189, + 31, + 179, + 2, // Opcode: SHSUBv4i32 + /* 71331 */ MCD_OPC_FilterValue, + 10, + 56, + 0, + 0, // Skip to: 71392 + /* 71336 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 71339 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71354 + /* 71344 */ MCD_OPC_CheckPredicate, + 21, + 154, + 129, + 0, // Skip to: 104527 + /* 71349 */ MCD_OPC_Decode, + 196, + 41, + 179, + 2, // Opcode: TRN1v4i32 + /* 71354 */ MCD_OPC_FilterValue, + 1, + 144, + 129, + 0, // Skip to: 104527 + /* 71359 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 71362 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71377 + /* 71367 */ MCD_OPC_CheckPredicate, + 21, + 131, + 129, + 0, // Skip to: 104527 + /* 71372 */ MCD_OPC_Decode, + 152, + 30, + 184, + 2, // Opcode: SADDLPv4i32_v2i64 + /* 71377 */ MCD_OPC_FilterValue, + 1, + 121, + 129, + 0, // Skip to: 104527 + /* 71382 */ MCD_OPC_CheckPredicate, + 21, + 116, + 129, + 0, // Skip to: 104527 + /* 71387 */ MCD_OPC_Decode, + 243, + 47, + 193, + 2, // Opcode: XTNv4i32 + /* 71392 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 71414 + /* 71397 */ MCD_OPC_CheckPredicate, + 21, + 101, + 129, + 0, // Skip to: 104527 + /* 71402 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 94, + 129, + 0, // Skip to: 104527 + /* 71409 */ MCD_OPC_Decode, + 144, + 36, + 179, + 2, // Opcode: SQSUBv4i32 + /* 71414 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 71436 + /* 71419 */ MCD_OPC_CheckPredicate, + 21, + 79, + 129, + 0, // Skip to: 104527 + /* 71424 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 72, + 129, + 0, // Skip to: 104527 + /* 71431 */ MCD_OPC_Decode, + 216, + 37, + 179, + 2, // Opcode: SSUBWv4i32_v2i64 + /* 71436 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 71458 + /* 71441 */ MCD_OPC_CheckPredicate, + 21, + 57, + 129, + 0, // Skip to: 104527 + /* 71446 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 50, + 129, + 0, // Skip to: 104527 + /* 71453 */ MCD_OPC_Decode, + 152, + 10, + 179, + 2, // Opcode: CMGTv4i32 + /* 71458 */ MCD_OPC_FilterValue, + 14, + 56, + 0, + 0, // Skip to: 71519 + /* 71463 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 71466 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71481 + /* 71471 */ MCD_OPC_CheckPredicate, + 21, + 27, + 129, + 0, // Skip to: 104527 + /* 71476 */ MCD_OPC_Decode, + 132, + 48, + 179, + 2, // Opcode: ZIP1v4i32 + /* 71481 */ MCD_OPC_FilterValue, + 1, + 17, + 129, + 0, // Skip to: 104527 + /* 71486 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 71489 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71504 + /* 71494 */ MCD_OPC_CheckPredicate, + 21, + 4, + 129, + 0, // Skip to: 104527 + /* 71499 */ MCD_OPC_Decode, + 249, + 40, + 193, + 2, // Opcode: SUQADDv4i32 + /* 71504 */ MCD_OPC_FilterValue, + 16, + 250, + 128, + 0, // Skip to: 104527 + /* 71509 */ MCD_OPC_CheckPredicate, + 21, + 245, + 128, + 0, // Skip to: 104527 + /* 71514 */ MCD_OPC_Decode, + 160, + 30, + 161, + 2, // Opcode: SADDLVv4i32v + /* 71519 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 71541 + /* 71524 */ MCD_OPC_CheckPredicate, + 21, + 230, + 128, + 0, // Skip to: 104527 + /* 71529 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 223, + 128, + 0, // Skip to: 104527 + /* 71536 */ MCD_OPC_Decode, + 136, + 10, + 179, + 2, // Opcode: CMGEv4i32 + /* 71541 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 71563 + /* 71546 */ MCD_OPC_CheckPredicate, + 21, + 208, + 128, + 0, // Skip to: 104527 + /* 71551 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 201, + 128, + 0, // Skip to: 104527 + /* 71558 */ MCD_OPC_Decode, + 158, + 7, + 187, + 2, // Opcode: ADDHNv2i64_v4i32 + /* 71563 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 71585 + /* 71568 */ MCD_OPC_CheckPredicate, + 21, + 186, + 128, + 0, // Skip to: 104527 + /* 71573 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 179, + 128, + 0, // Skip to: 104527 + /* 71580 */ MCD_OPC_Decode, + 128, + 37, + 179, + 2, // Opcode: SSHLv4i32 + /* 71585 */ MCD_OPC_FilterValue, + 18, + 33, + 0, + 0, // Skip to: 71623 + /* 71590 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 71593 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 71608 + /* 71598 */ MCD_OPC_CheckPredicate, + 21, + 156, + 128, + 0, // Skip to: 104527 + /* 71603 */ MCD_OPC_Decode, + 223, + 9, + 184, + 2, // Opcode: CLSv4i32 + /* 71608 */ MCD_OPC_FilterValue, + 33, + 146, + 128, + 0, // Skip to: 104527 + /* 71613 */ MCD_OPC_CheckPredicate, + 21, + 141, + 128, + 0, // Skip to: 104527 + /* 71618 */ MCD_OPC_Decode, + 159, + 36, + 193, + 2, // Opcode: SQXTNv4i32 + /* 71623 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 71645 + /* 71628 */ MCD_OPC_CheckPredicate, + 21, + 126, + 128, + 0, // Skip to: 104527 + /* 71633 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 119, + 128, + 0, // Skip to: 104527 + /* 71640 */ MCD_OPC_Decode, + 212, + 35, + 179, + 2, // Opcode: SQSHLv4i32 + /* 71645 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 71667 + /* 71650 */ MCD_OPC_CheckPredicate, + 21, + 104, + 128, + 0, // Skip to: 104527 + /* 71655 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 97, + 128, + 0, // Skip to: 104527 + /* 71662 */ MCD_OPC_Decode, + 227, + 29, + 187, + 2, // Opcode: SABALv4i32_v2i64 + /* 71667 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 71689 + /* 71672 */ MCD_OPC_CheckPredicate, + 21, + 82, + 128, + 0, // Skip to: 104527 + /* 71677 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 75, + 128, + 0, // Skip to: 104527 + /* 71684 */ MCD_OPC_Decode, + 212, + 36, + 179, + 2, // Opcode: SRSHLv4i32 + /* 71689 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 71711 + /* 71694 */ MCD_OPC_CheckPredicate, + 21, + 60, + 128, + 0, // Skip to: 104527 + /* 71699 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 53, + 128, + 0, // Skip to: 104527 + /* 71706 */ MCD_OPC_Decode, + 153, + 47, + 179, + 2, // Opcode: UZP2v4i32 + /* 71711 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 71733 + /* 71716 */ MCD_OPC_CheckPredicate, + 21, + 38, + 128, + 0, // Skip to: 104527 + /* 71721 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 31, + 128, + 0, // Skip to: 104527 + /* 71728 */ MCD_OPC_Decode, + 136, + 35, + 179, + 2, // Opcode: SQRSHLv4i32 + /* 71733 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 71755 + /* 71738 */ MCD_OPC_CheckPredicate, + 21, + 16, + 128, + 0, // Skip to: 104527 + /* 71743 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 9, + 128, + 0, // Skip to: 104527 + /* 71750 */ MCD_OPC_Decode, + 175, + 40, + 187, + 2, // Opcode: SUBHNv2i64_v4i32 + /* 71755 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 71777 + /* 71760 */ MCD_OPC_CheckPredicate, + 21, + 250, + 127, + 0, // Skip to: 104527 + /* 71765 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 243, + 127, + 0, // Skip to: 104527 + /* 71772 */ MCD_OPC_Decode, + 246, + 31, + 179, + 2, // Opcode: SMAXv4i32 + /* 71777 */ MCD_OPC_FilterValue, + 26, + 56, + 0, + 0, // Skip to: 71838 + /* 71782 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 71785 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71800 + /* 71790 */ MCD_OPC_CheckPredicate, + 21, + 220, + 127, + 0, // Skip to: 104527 + /* 71795 */ MCD_OPC_Decode, + 212, + 41, + 179, + 2, // Opcode: TRN2v4i32 + /* 71800 */ MCD_OPC_FilterValue, + 1, + 210, + 127, + 0, // Skip to: 104527 + /* 71805 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 71808 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71823 + /* 71813 */ MCD_OPC_CheckPredicate, + 21, + 197, + 127, + 0, // Skip to: 104527 + /* 71818 */ MCD_OPC_Decode, + 140, + 30, + 193, + 2, // Opcode: SADALPv4i32_v2i64 + /* 71823 */ MCD_OPC_FilterValue, + 1, + 187, + 127, + 0, // Skip to: 104527 + /* 71828 */ MCD_OPC_CheckPredicate, + 30, + 182, + 127, + 0, // Skip to: 104527 + /* 71833 */ MCD_OPC_Decode, + 196, + 8, + 193, + 2, // Opcode: BFCVTN2 + /* 71838 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 71860 + /* 71843 */ MCD_OPC_CheckPredicate, + 21, + 167, + 127, + 0, // Skip to: 104527 + /* 71848 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 160, + 127, + 0, // Skip to: 104527 + /* 71855 */ MCD_OPC_Decode, + 152, + 32, + 179, + 2, // Opcode: SMINv4i32 + /* 71860 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 71882 + /* 71865 */ MCD_OPC_CheckPredicate, + 21, + 145, + 127, + 0, // Skip to: 104527 + /* 71870 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 138, + 127, + 0, // Skip to: 104527 + /* 71877 */ MCD_OPC_Decode, + 249, + 29, + 179, + 2, // Opcode: SABDLv4i32_v2i64 + /* 71882 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 71904 + /* 71887 */ MCD_OPC_CheckPredicate, + 21, + 123, + 127, + 0, // Skip to: 104527 + /* 71892 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 116, + 127, + 0, // Skip to: 104527 + /* 71899 */ MCD_OPC_Decode, + 131, + 30, + 179, + 2, // Opcode: SABDv4i32 + /* 71904 */ MCD_OPC_FilterValue, + 30, + 40, + 0, + 0, // Skip to: 71949 + /* 71909 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 71912 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71927 + /* 71917 */ MCD_OPC_CheckPredicate, + 21, + 93, + 127, + 0, // Skip to: 104527 + /* 71922 */ MCD_OPC_Decode, + 148, + 48, + 179, + 2, // Opcode: ZIP2v4i32 + /* 71927 */ MCD_OPC_FilterValue, + 1, + 83, + 127, + 0, // Skip to: 104527 + /* 71932 */ MCD_OPC_CheckPredicate, + 21, + 78, + 127, + 0, // Skip to: 104527 + /* 71937 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 71, + 127, + 0, // Skip to: 104527 + /* 71944 */ MCD_OPC_Decode, + 133, + 33, + 184, + 2, // Opcode: SQABSv4i32 + /* 71949 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 71971 + /* 71954 */ MCD_OPC_CheckPredicate, + 21, + 56, + 127, + 0, // Skip to: 104527 + /* 71959 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 49, + 127, + 0, // Skip to: 104527 + /* 71966 */ MCD_OPC_Decode, + 237, + 29, + 187, + 2, // Opcode: SABAv4i32 + /* 71971 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 71993 + /* 71976 */ MCD_OPC_CheckPredicate, + 21, + 34, + 127, + 0, // Skip to: 104527 + /* 71981 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 27, + 127, + 0, // Skip to: 104527 + /* 71988 */ MCD_OPC_Decode, + 171, + 32, + 187, + 2, // Opcode: SMLALv4i32_v2i64 + /* 71993 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 72015 + /* 71998 */ MCD_OPC_CheckPredicate, + 21, + 12, + 127, + 0, // Skip to: 104527 + /* 72003 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 5, + 127, + 0, // Skip to: 104527 + /* 72010 */ MCD_OPC_Decode, + 215, + 7, + 179, + 2, // Opcode: ADDv4i32 + /* 72015 */ MCD_OPC_FilterValue, + 34, + 33, + 0, + 0, // Skip to: 72053 + /* 72020 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 72023 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 72038 + /* 72028 */ MCD_OPC_CheckPredicate, + 21, + 238, + 126, + 0, // Skip to: 104527 + /* 72033 */ MCD_OPC_Decode, + 153, + 10, + 184, + 2, // Opcode: CMGTv4i32rz + /* 72038 */ MCD_OPC_FilterValue, + 33, + 228, + 126, + 0, // Skip to: 104527 + /* 72043 */ MCD_OPC_CheckPredicate, + 21, + 223, + 126, + 0, // Skip to: 104527 + /* 72048 */ MCD_OPC_Decode, + 164, + 19, + 184, + 2, // Opcode: FRINTPv4f32 + /* 72053 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 72075 + /* 72058 */ MCD_OPC_CheckPredicate, + 21, + 208, + 126, + 0, // Skip to: 104527 + /* 72063 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 201, + 126, + 0, // Skip to: 104527 + /* 72070 */ MCD_OPC_Decode, + 167, + 11, + 179, + 2, // Opcode: CMTSTv4i32 + /* 72075 */ MCD_OPC_FilterValue, + 36, + 17, + 0, + 0, // Skip to: 72097 + /* 72080 */ MCD_OPC_CheckPredicate, + 21, + 186, + 126, + 0, // Skip to: 104527 + /* 72085 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 179, + 126, + 0, // Skip to: 104527 + /* 72092 */ MCD_OPC_Decode, + 207, + 33, + 187, + 2, // Opcode: SQDMLALv4i32_v2i64 + /* 72097 */ MCD_OPC_FilterValue, + 37, + 33, + 0, + 0, // Skip to: 72135 + /* 72102 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 72105 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 72120 + /* 72110 */ MCD_OPC_CheckPredicate, + 32, + 156, + 126, + 0, // Skip to: 104527 + /* 72115 */ MCD_OPC_Decode, + 246, + 30, + 187, + 2, // Opcode: SDOTv16i8 + /* 72120 */ MCD_OPC_FilterValue, + 1, + 146, + 126, + 0, // Skip to: 104527 + /* 72125 */ MCD_OPC_CheckPredicate, + 21, + 141, + 126, + 0, // Skip to: 104527 + /* 72130 */ MCD_OPC_Decode, + 154, + 27, + 187, + 2, // Opcode: MLAv4i32 + /* 72135 */ MCD_OPC_FilterValue, + 38, + 33, + 0, + 0, // Skip to: 72173 + /* 72140 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 72143 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 72158 + /* 72148 */ MCD_OPC_CheckPredicate, + 21, + 118, + 126, + 0, // Skip to: 104527 + /* 72153 */ MCD_OPC_Decode, + 249, + 9, + 184, + 2, // Opcode: CMEQv4i32rz + /* 72158 */ MCD_OPC_FilterValue, + 33, + 108, + 126, + 0, // Skip to: 104527 + /* 72163 */ MCD_OPC_CheckPredicate, + 21, + 103, + 126, + 0, // Skip to: 104527 + /* 72168 */ MCD_OPC_Decode, + 186, + 19, + 184, + 2, // Opcode: FRINTZv4f32 + /* 72173 */ MCD_OPC_FilterValue, + 39, + 33, + 0, + 0, // Skip to: 72211 + /* 72178 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 72181 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 72196 + /* 72186 */ MCD_OPC_CheckPredicate, + 33, + 80, + 126, + 0, // Skip to: 104527 + /* 72191 */ MCD_OPC_Decode, + 153, + 46, + 187, + 2, // Opcode: USDOTv16i8 + /* 72196 */ MCD_OPC_FilterValue, + 1, + 70, + 126, + 0, // Skip to: 104527 + /* 72201 */ MCD_OPC_CheckPredicate, + 21, + 65, + 126, + 0, // Skip to: 104527 + /* 72206 */ MCD_OPC_Decode, + 232, + 27, + 179, + 2, // Opcode: MULv4i32 + /* 72211 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 72233 + /* 72216 */ MCD_OPC_CheckPredicate, + 21, + 50, + 126, + 0, // Skip to: 104527 + /* 72221 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 43, + 126, + 0, // Skip to: 104527 + /* 72228 */ MCD_OPC_Decode, + 191, + 32, + 187, + 2, // Opcode: SMLSLv4i32_v2i64 + /* 72233 */ MCD_OPC_FilterValue, + 41, + 33, + 0, + 0, // Skip to: 72271 + /* 72238 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 72241 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 72256 + /* 72246 */ MCD_OPC_CheckPredicate, + 33, + 20, + 126, + 0, // Skip to: 104527 + /* 72251 */ MCD_OPC_Decode, + 195, + 32, + 187, + 2, // Opcode: SMMLA + /* 72256 */ MCD_OPC_FilterValue, + 1, + 10, + 126, + 0, // Skip to: 104527 + /* 72261 */ MCD_OPC_CheckPredicate, + 21, + 5, + 126, + 0, // Skip to: 104527 + /* 72266 */ MCD_OPC_Decode, + 223, + 31, + 179, + 2, // Opcode: SMAXPv4i32 + /* 72271 */ MCD_OPC_FilterValue, + 42, + 63, + 0, + 0, // Skip to: 72339 + /* 72276 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 72279 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 72294 + /* 72284 */ MCD_OPC_CheckPredicate, + 21, + 238, + 125, + 0, // Skip to: 104527 + /* 72289 */ MCD_OPC_Decode, + 193, + 10, + 184, + 2, // Opcode: CMLTv4i32rz + /* 72294 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 72309 + /* 72299 */ MCD_OPC_CheckPredicate, + 21, + 223, + 125, + 0, // Skip to: 104527 + /* 72304 */ MCD_OPC_Decode, + 148, + 15, + 184, + 2, // Opcode: FCVTPSv4f32 + /* 72309 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 72324 + /* 72314 */ MCD_OPC_CheckPredicate, + 21, + 208, + 125, + 0, // Skip to: 104527 + /* 72319 */ MCD_OPC_Decode, + 232, + 31, + 207, + 2, // Opcode: SMAXVv4i32v + /* 72324 */ MCD_OPC_FilterValue, + 49, + 198, + 125, + 0, // Skip to: 104527 + /* 72329 */ MCD_OPC_CheckPredicate, + 21, + 193, + 125, + 0, // Skip to: 104527 + /* 72334 */ MCD_OPC_Decode, + 138, + 32, + 207, + 2, // Opcode: SMINVv4i32v + /* 72339 */ MCD_OPC_FilterValue, + 43, + 33, + 0, + 0, // Skip to: 72377 + /* 72344 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 72347 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 72362 + /* 72352 */ MCD_OPC_CheckPredicate, + 33, + 170, + 125, + 0, // Skip to: 104527 + /* 72357 */ MCD_OPC_Decode, + 183, + 46, + 187, + 2, // Opcode: USMMLA + /* 72362 */ MCD_OPC_FilterValue, + 1, + 160, + 125, + 0, // Skip to: 104527 + /* 72367 */ MCD_OPC_CheckPredicate, + 21, + 155, + 125, + 0, // Skip to: 104527 + /* 72372 */ MCD_OPC_Decode, + 129, + 32, + 179, + 2, // Opcode: SMINPv4i32 + /* 72377 */ MCD_OPC_FilterValue, + 44, + 17, + 0, + 0, // Skip to: 72399 + /* 72382 */ MCD_OPC_CheckPredicate, + 21, + 140, + 125, + 0, // Skip to: 104527 + /* 72387 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 133, + 125, + 0, // Skip to: 104527 + /* 72394 */ MCD_OPC_Decode, + 232, + 33, + 187, + 2, // Opcode: SQDMLSLv4i32_v2i64 + /* 72399 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 72421 + /* 72404 */ MCD_OPC_CheckPredicate, + 21, + 118, + 125, + 0, // Skip to: 104527 + /* 72409 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 111, + 125, + 0, // Skip to: 104527 + /* 72416 */ MCD_OPC_Decode, + 250, + 33, + 179, + 2, // Opcode: SQDMULHv4i32 + /* 72421 */ MCD_OPC_FilterValue, + 46, + 48, + 0, + 0, // Skip to: 72474 + /* 72426 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 72429 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 72444 + /* 72434 */ MCD_OPC_CheckPredicate, + 21, + 88, + 125, + 0, // Skip to: 104527 + /* 72439 */ MCD_OPC_Decode, + 137, + 7, + 184, + 2, // Opcode: ABSv4i32 + /* 72444 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 72459 + /* 72449 */ MCD_OPC_CheckPredicate, + 21, + 73, + 125, + 0, // Skip to: 104527 + /* 72454 */ MCD_OPC_Decode, + 201, + 15, + 184, + 2, // Opcode: FCVTZSv4f32 + /* 72459 */ MCD_OPC_FilterValue, + 49, + 63, + 125, + 0, // Skip to: 104527 + /* 72464 */ MCD_OPC_CheckPredicate, + 21, + 58, + 125, + 0, // Skip to: 104527 + /* 72469 */ MCD_OPC_Decode, + 188, + 7, + 207, + 2, // Opcode: ADDVv4i32v + /* 72474 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 72496 + /* 72479 */ MCD_OPC_CheckPredicate, + 21, + 43, + 125, + 0, // Skip to: 104527 + /* 72484 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 36, + 125, + 0, // Skip to: 104527 + /* 72491 */ MCD_OPC_Decode, + 173, + 7, + 179, + 2, // Opcode: ADDPv4i32 + /* 72496 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 72518 + /* 72501 */ MCD_OPC_CheckPredicate, + 21, + 21, + 125, + 0, // Skip to: 104527 + /* 72506 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 14, + 125, + 0, // Skip to: 104527 + /* 72513 */ MCD_OPC_Decode, + 237, + 32, + 179, + 2, // Opcode: SMULLv4i32_v2i64 + /* 72518 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 72540 + /* 72523 */ MCD_OPC_CheckPredicate, + 21, + 255, + 124, + 0, // Skip to: 104527 + /* 72528 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 248, + 124, + 0, // Skip to: 104527 + /* 72535 */ MCD_OPC_Decode, + 242, + 16, + 179, + 2, // Opcode: FMINNMv4f32 + /* 72540 */ MCD_OPC_FilterValue, + 50, + 48, + 0, + 0, // Skip to: 72593 + /* 72545 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 72548 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 72563 + /* 72553 */ MCD_OPC_CheckPredicate, + 21, + 225, + 124, + 0, // Skip to: 104527 + /* 72558 */ MCD_OPC_Decode, + 227, + 13, + 184, + 2, // Opcode: FCMGTv4i32rz + /* 72563 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 72578 + /* 72568 */ MCD_OPC_CheckPredicate, + 21, + 210, + 124, + 0, // Skip to: 104527 + /* 72573 */ MCD_OPC_Decode, + 223, + 45, + 184, + 2, // Opcode: URECPEv4i32 + /* 72578 */ MCD_OPC_FilterValue, + 48, + 200, + 124, + 0, // Skip to: 104527 + /* 72583 */ MCD_OPC_CheckPredicate, + 23, + 195, + 124, + 0, // Skip to: 104527 + /* 72588 */ MCD_OPC_Decode, + 232, + 16, + 199, + 2, // Opcode: FMINNMVv8i16v + /* 72593 */ MCD_OPC_FilterValue, + 51, + 17, + 0, + 0, // Skip to: 72615 + /* 72598 */ MCD_OPC_CheckPredicate, + 21, + 180, + 124, + 0, // Skip to: 104527 + /* 72603 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 173, + 124, + 0, // Skip to: 104527 + /* 72610 */ MCD_OPC_Decode, + 202, + 17, + 187, + 2, // Opcode: FMLSv4f32 + /* 72615 */ MCD_OPC_FilterValue, + 52, + 17, + 0, + 0, // Skip to: 72637 + /* 72620 */ MCD_OPC_CheckPredicate, + 21, + 158, + 124, + 0, // Skip to: 104527 + /* 72625 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 151, + 124, + 0, // Skip to: 104527 + /* 72632 */ MCD_OPC_Decode, + 145, + 34, + 179, + 2, // Opcode: SQDMULLv4i32_v2i64 + /* 72637 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 72659 + /* 72642 */ MCD_OPC_CheckPredicate, + 21, + 136, + 124, + 0, // Skip to: 104527 + /* 72647 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 129, + 124, + 0, // Skip to: 104527 + /* 72654 */ MCD_OPC_Decode, + 245, + 19, + 179, + 2, // Opcode: FSUBv4f32 + /* 72659 */ MCD_OPC_FilterValue, + 54, + 33, + 0, + 0, // Skip to: 72697 + /* 72664 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 72667 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 72682 + /* 72672 */ MCD_OPC_CheckPredicate, + 21, + 106, + 124, + 0, // Skip to: 104527 + /* 72677 */ MCD_OPC_Decode, + 183, + 13, + 184, + 2, // Opcode: FCMEQv4i32rz + /* 72682 */ MCD_OPC_FilterValue, + 33, + 96, + 124, + 0, // Skip to: 104527 + /* 72687 */ MCD_OPC_CheckPredicate, + 21, + 91, + 124, + 0, // Skip to: 104527 + /* 72692 */ MCD_OPC_Decode, + 200, + 18, + 184, + 2, // Opcode: FRECPEv4f32 + /* 72697 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 72719 + /* 72702 */ MCD_OPC_CheckPredicate, + 21, + 76, + 124, + 0, // Skip to: 104527 + /* 72707 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 69, + 124, + 0, // Skip to: 104527 + /* 72714 */ MCD_OPC_Decode, + 135, + 14, + 184, + 2, // Opcode: FCMLTv4i32rz + /* 72719 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 72741 + /* 72724 */ MCD_OPC_CheckPredicate, + 25, + 54, + 124, + 0, // Skip to: 104527 + /* 72729 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 47, + 124, + 0, // Skip to: 104527 + /* 72736 */ MCD_OPC_Decode, + 187, + 17, + 187, + 2, // Opcode: FMLSLv8f16 + /* 72741 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 72763 + /* 72746 */ MCD_OPC_CheckPredicate, + 21, + 32, + 124, + 0, // Skip to: 104527 + /* 72751 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 25, + 124, + 0, // Skip to: 104527 + /* 72758 */ MCD_OPC_Decode, + 143, + 17, + 179, + 2, // Opcode: FMINv4f32 + /* 72763 */ MCD_OPC_FilterValue, + 62, + 33, + 0, + 0, // Skip to: 72801 + /* 72768 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 72771 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 72786 + /* 72776 */ MCD_OPC_CheckPredicate, + 21, + 2, + 124, + 0, // Skip to: 104527 + /* 72781 */ MCD_OPC_Decode, + 220, + 12, + 184, + 2, // Opcode: FABSv4f32 + /* 72786 */ MCD_OPC_FilterValue, + 48, + 248, + 123, + 0, // Skip to: 104527 + /* 72791 */ MCD_OPC_CheckPredicate, + 23, + 243, + 123, + 0, // Skip to: 104527 + /* 72796 */ MCD_OPC_Decode, + 133, + 17, + 199, + 2, // Opcode: FMINVv8i16v + /* 72801 */ MCD_OPC_FilterValue, + 63, + 233, + 123, + 0, // Skip to: 104527 + /* 72806 */ MCD_OPC_CheckPredicate, + 21, + 228, + 123, + 0, // Skip to: 104527 + /* 72811 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 221, + 123, + 0, // Skip to: 104527 + /* 72818 */ MCD_OPC_Decode, + 208, + 19, + 179, + 2, // Opcode: FRSQRTSv4f32 + /* 72823 */ MCD_OPC_FilterValue, + 3, + 240, + 5, + 0, // Skip to: 74348 + /* 72828 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 72831 */ MCD_OPC_FilterValue, + 0, + 135, + 0, + 0, // Skip to: 72971 + /* 72836 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 72839 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 72861 + /* 72844 */ MCD_OPC_CheckPredicate, + 21, + 190, + 123, + 0, // Skip to: 104527 + /* 72849 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 183, + 123, + 0, // Skip to: 104527 + /* 72856 */ MCD_OPC_Decode, + 163, + 42, + 179, + 2, // Opcode: UADDLv4i32_v2i64 + /* 72861 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 72883 + /* 72866 */ MCD_OPC_CheckPredicate, + 21, + 168, + 123, + 0, // Skip to: 104527 + /* 72871 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 161, + 123, + 0, // Skip to: 104527 + /* 72878 */ MCD_OPC_Decode, + 245, + 42, + 179, + 2, // Opcode: UHADDv4i32 + /* 72883 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 72905 + /* 72888 */ MCD_OPC_CheckPredicate, + 21, + 146, + 123, + 0, // Skip to: 104527 + /* 72893 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 139, + 123, + 0, // Skip to: 104527 + /* 72900 */ MCD_OPC_Decode, + 177, + 44, + 179, + 2, // Opcode: UQADDv4i32 + /* 72905 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 72927 + /* 72910 */ MCD_OPC_CheckPredicate, + 21, + 124, + 123, + 0, // Skip to: 104527 + /* 72915 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 117, + 123, + 0, // Skip to: 104527 + /* 72922 */ MCD_OPC_Decode, + 179, + 42, + 179, + 2, // Opcode: UADDWv4i32_v2i64 + /* 72927 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 72949 + /* 72932 */ MCD_OPC_CheckPredicate, + 21, + 102, + 123, + 0, // Skip to: 104527 + /* 72937 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 95, + 123, + 0, // Skip to: 104527 + /* 72944 */ MCD_OPC_Decode, + 231, + 45, + 179, + 2, // Opcode: URHADDv4i32 + /* 72949 */ MCD_OPC_FilterValue, + 7, + 85, + 123, + 0, // Skip to: 104527 + /* 72954 */ MCD_OPC_CheckPredicate, + 21, + 80, + 123, + 0, // Skip to: 104527 + /* 72959 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 73, + 123, + 0, // Skip to: 104527 + /* 72966 */ MCD_OPC_Decode, + 238, + 8, + 187, + 2, // Opcode: BITv16i8 + /* 72971 */ MCD_OPC_FilterValue, + 1, + 226, + 0, + 0, // Skip to: 73202 + /* 72976 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 72979 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 73001 + /* 72984 */ MCD_OPC_CheckPredicate, + 21, + 50, + 123, + 0, // Skip to: 104527 + /* 72989 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 43, + 123, + 0, // Skip to: 104527 + /* 72996 */ MCD_OPC_Decode, + 225, + 46, + 179, + 2, // Opcode: USUBLv4i32_v2i64 + /* 73001 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 73023 + /* 73006 */ MCD_OPC_CheckPredicate, + 21, + 28, + 123, + 0, // Skip to: 104527 + /* 73011 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 21, + 123, + 0, // Skip to: 104527 + /* 73018 */ MCD_OPC_Decode, + 131, + 43, + 179, + 2, // Opcode: UHSUBv4i32 + /* 73023 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 73061 + /* 73028 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 73031 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 73046 + /* 73036 */ MCD_OPC_CheckPredicate, + 21, + 254, + 122, + 0, // Skip to: 104527 + /* 73041 */ MCD_OPC_Decode, + 149, + 42, + 184, + 2, // Opcode: UADDLPv4i32_v2i64 + /* 73046 */ MCD_OPC_FilterValue, + 33, + 244, + 122, + 0, // Skip to: 104527 + /* 73051 */ MCD_OPC_CheckPredicate, + 21, + 239, + 122, + 0, // Skip to: 104527 + /* 73056 */ MCD_OPC_Decode, + 174, + 36, + 193, + 2, // Opcode: SQXTUNv4i32 + /* 73061 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 73083 + /* 73066 */ MCD_OPC_CheckPredicate, + 21, + 224, + 122, + 0, // Skip to: 104527 + /* 73071 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 217, + 122, + 0, // Skip to: 104527 + /* 73078 */ MCD_OPC_Decode, + 203, + 45, + 179, + 2, // Opcode: UQSUBv4i32 + /* 73083 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 73105 + /* 73088 */ MCD_OPC_CheckPredicate, + 21, + 202, + 122, + 0, // Skip to: 104527 + /* 73093 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 195, + 122, + 0, // Skip to: 104527 + /* 73100 */ MCD_OPC_Decode, + 237, + 46, + 179, + 2, // Opcode: USUBWv4i32_v2i64 + /* 73105 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 73127 + /* 73110 */ MCD_OPC_CheckPredicate, + 21, + 180, + 122, + 0, // Skip to: 104527 + /* 73115 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 173, + 122, + 0, // Skip to: 104527 + /* 73122 */ MCD_OPC_Decode, + 163, + 10, + 179, + 2, // Opcode: CMHIv4i32 + /* 73127 */ MCD_OPC_FilterValue, + 6, + 48, + 0, + 0, // Skip to: 73180 + /* 73132 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 73135 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 73150 + /* 73140 */ MCD_OPC_CheckPredicate, + 21, + 150, + 122, + 0, // Skip to: 104527 + /* 73145 */ MCD_OPC_Decode, + 201, + 46, + 193, + 2, // Opcode: USQADDv4i32 + /* 73150 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 73165 + /* 73155 */ MCD_OPC_CheckPredicate, + 21, + 135, + 122, + 0, // Skip to: 104527 + /* 73160 */ MCD_OPC_Decode, + 155, + 31, + 184, + 2, // Opcode: SHLLv4i32 + /* 73165 */ MCD_OPC_FilterValue, + 48, + 125, + 122, + 0, // Skip to: 104527 + /* 73170 */ MCD_OPC_CheckPredicate, + 21, + 120, + 122, + 0, // Skip to: 104527 + /* 73175 */ MCD_OPC_Decode, + 157, + 42, + 161, + 2, // Opcode: UADDLVv4i32v + /* 73180 */ MCD_OPC_FilterValue, + 7, + 110, + 122, + 0, // Skip to: 104527 + /* 73185 */ MCD_OPC_CheckPredicate, + 21, + 105, + 122, + 0, // Skip to: 104527 + /* 73190 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 98, + 122, + 0, // Skip to: 104527 + /* 73197 */ MCD_OPC_Decode, + 171, + 10, + 179, + 2, // Opcode: CMHSv4i32 + /* 73202 */ MCD_OPC_FilterValue, + 2, + 173, + 0, + 0, // Skip to: 73380 + /* 73207 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 73210 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 73232 + /* 73215 */ MCD_OPC_CheckPredicate, + 21, + 75, + 122, + 0, // Skip to: 104527 + /* 73220 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 68, + 122, + 0, // Skip to: 104527 + /* 73227 */ MCD_OPC_Decode, + 137, + 29, + 187, + 2, // Opcode: RADDHNv2i64_v4i32 + /* 73232 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 73254 + /* 73237 */ MCD_OPC_CheckPredicate, + 21, + 53, + 122, + 0, // Skip to: 104527 + /* 73242 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 46, + 122, + 0, // Skip to: 104527 + /* 73249 */ MCD_OPC_Decode, + 172, + 46, + 179, + 2, // Opcode: USHLv4i32 + /* 73254 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 73292 + /* 73259 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 73262 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 73277 + /* 73267 */ MCD_OPC_CheckPredicate, + 21, + 23, + 122, + 0, // Skip to: 104527 + /* 73272 */ MCD_OPC_Decode, + 235, + 9, + 184, + 2, // Opcode: CLZv4i32 + /* 73277 */ MCD_OPC_FilterValue, + 33, + 13, + 122, + 0, // Skip to: 104527 + /* 73282 */ MCD_OPC_CheckPredicate, + 21, + 8, + 122, + 0, // Skip to: 104527 + /* 73287 */ MCD_OPC_Decode, + 218, + 45, + 193, + 2, // Opcode: UQXTNv4i32 + /* 73292 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 73314 + /* 73297 */ MCD_OPC_CheckPredicate, + 21, + 249, + 121, + 0, // Skip to: 104527 + /* 73302 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 242, + 121, + 0, // Skip to: 104527 + /* 73309 */ MCD_OPC_Decode, + 158, + 45, + 179, + 2, // Opcode: UQSHLv4i32 + /* 73314 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 73336 + /* 73319 */ MCD_OPC_CheckPredicate, + 21, + 227, + 121, + 0, // Skip to: 104527 + /* 73324 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 220, + 121, + 0, // Skip to: 104527 + /* 73331 */ MCD_OPC_Decode, + 227, + 41, + 187, + 2, // Opcode: UABALv4i32_v2i64 + /* 73336 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 73358 + /* 73341 */ MCD_OPC_CheckPredicate, + 21, + 205, + 121, + 0, // Skip to: 104527 + /* 73346 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 198, + 121, + 0, // Skip to: 104527 + /* 73353 */ MCD_OPC_Decode, + 247, + 45, + 179, + 2, // Opcode: URSHLv4i32 + /* 73358 */ MCD_OPC_FilterValue, + 7, + 188, + 121, + 0, // Skip to: 104527 + /* 73363 */ MCD_OPC_CheckPredicate, + 21, + 183, + 121, + 0, // Skip to: 104527 + /* 73368 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 176, + 121, + 0, // Skip to: 104527 + /* 73375 */ MCD_OPC_Decode, + 240, + 44, + 179, + 2, // Opcode: UQRSHLv4i32 + /* 73380 */ MCD_OPC_FilterValue, + 3, + 179, + 0, + 0, // Skip to: 73564 + /* 73385 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 73388 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 73410 + /* 73393 */ MCD_OPC_CheckPredicate, + 21, + 153, + 121, + 0, // Skip to: 104527 + /* 73398 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 146, + 121, + 0, // Skip to: 104527 + /* 73405 */ MCD_OPC_Decode, + 213, + 29, + 187, + 2, // Opcode: RSUBHNv2i64_v4i32 + /* 73410 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 73432 + /* 73415 */ MCD_OPC_CheckPredicate, + 21, + 131, + 121, + 0, // Skip to: 104527 + /* 73420 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 124, + 121, + 0, // Skip to: 104527 + /* 73427 */ MCD_OPC_Decode, + 165, + 43, + 179, + 2, // Opcode: UMAXv4i32 + /* 73432 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 73454 + /* 73437 */ MCD_OPC_CheckPredicate, + 21, + 109, + 121, + 0, // Skip to: 104527 + /* 73442 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 102, + 121, + 0, // Skip to: 104527 + /* 73449 */ MCD_OPC_Decode, + 140, + 42, + 193, + 2, // Opcode: UADALPv4i32_v2i64 + /* 73454 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 73476 + /* 73459 */ MCD_OPC_CheckPredicate, + 21, + 87, + 121, + 0, // Skip to: 104527 + /* 73464 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 80, + 121, + 0, // Skip to: 104527 + /* 73471 */ MCD_OPC_Decode, + 198, + 43, + 179, + 2, // Opcode: UMINv4i32 + /* 73476 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 73498 + /* 73481 */ MCD_OPC_CheckPredicate, + 21, + 65, + 121, + 0, // Skip to: 104527 + /* 73486 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 58, + 121, + 0, // Skip to: 104527 + /* 73493 */ MCD_OPC_Decode, + 249, + 41, + 179, + 2, // Opcode: UABDLv4i32_v2i64 + /* 73498 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 73520 + /* 73503 */ MCD_OPC_CheckPredicate, + 21, + 43, + 121, + 0, // Skip to: 104527 + /* 73508 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 36, + 121, + 0, // Skip to: 104527 + /* 73515 */ MCD_OPC_Decode, + 131, + 42, + 179, + 2, // Opcode: UABDv4i32 + /* 73520 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 73542 + /* 73525 */ MCD_OPC_CheckPredicate, + 21, + 21, + 121, + 0, // Skip to: 104527 + /* 73530 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 14, + 121, + 0, // Skip to: 104527 + /* 73537 */ MCD_OPC_Decode, + 182, + 34, + 184, + 2, // Opcode: SQNEGv4i32 + /* 73542 */ MCD_OPC_FilterValue, + 7, + 4, + 121, + 0, // Skip to: 104527 + /* 73547 */ MCD_OPC_CheckPredicate, + 21, + 255, + 120, + 0, // Skip to: 104527 + /* 73552 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 248, + 120, + 0, // Skip to: 104527 + /* 73559 */ MCD_OPC_Decode, + 237, + 41, + 187, + 2, // Opcode: UABAv4i32 + /* 73564 */ MCD_OPC_FilterValue, + 4, + 199, + 0, + 0, // Skip to: 73768 + /* 73569 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 73572 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 73594 + /* 73577 */ MCD_OPC_CheckPredicate, + 21, + 225, + 120, + 0, // Skip to: 104527 + /* 73582 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 218, + 120, + 0, // Skip to: 104527 + /* 73589 */ MCD_OPC_Decode, + 217, + 43, + 187, + 2, // Opcode: UMLALv4i32_v2i64 + /* 73594 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 73632 + /* 73599 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 73602 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 73617 + /* 73607 */ MCD_OPC_CheckPredicate, + 28, + 195, + 120, + 0, // Skip to: 104527 + /* 73612 */ MCD_OPC_Decode, + 206, + 34, + 187, + 2, // Opcode: SQRDMLAHv4i32 + /* 73617 */ MCD_OPC_FilterValue, + 1, + 185, + 120, + 0, // Skip to: 104527 + /* 73622 */ MCD_OPC_CheckPredicate, + 21, + 180, + 120, + 0, // Skip to: 104527 + /* 73627 */ MCD_OPC_Decode, + 221, + 40, + 179, + 2, // Opcode: SUBv4i32 + /* 73632 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 73654 + /* 73637 */ MCD_OPC_CheckPredicate, + 21, + 165, + 120, + 0, // Skip to: 104527 + /* 73642 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 158, + 120, + 0, // Skip to: 104527 + /* 73649 */ MCD_OPC_Decode, + 137, + 10, + 184, + 2, // Opcode: CMGEv4i32rz + /* 73654 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 73692 + /* 73659 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 73662 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 73677 + /* 73667 */ MCD_OPC_CheckPredicate, + 28, + 135, + 120, + 0, // Skip to: 104527 + /* 73672 */ MCD_OPC_Decode, + 225, + 34, + 187, + 2, // Opcode: SQRDMLSHv4i32 + /* 73677 */ MCD_OPC_FilterValue, + 1, + 125, + 120, + 0, // Skip to: 104527 + /* 73682 */ MCD_OPC_CheckPredicate, + 21, + 120, + 120, + 0, // Skip to: 104527 + /* 73687 */ MCD_OPC_Decode, + 248, + 9, + 179, + 2, // Opcode: CMEQv4i32 + /* 73692 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 73730 + /* 73697 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 73700 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 73715 + /* 73705 */ MCD_OPC_CheckPredicate, + 32, + 97, + 120, + 0, // Skip to: 104527 + /* 73710 */ MCD_OPC_Decode, + 236, + 42, + 187, + 2, // Opcode: UDOTv16i8 + /* 73715 */ MCD_OPC_FilterValue, + 1, + 87, + 120, + 0, // Skip to: 104527 + /* 73720 */ MCD_OPC_CheckPredicate, + 21, + 82, + 120, + 0, // Skip to: 104527 + /* 73725 */ MCD_OPC_Decode, + 171, + 27, + 187, + 2, // Opcode: MLSv4i32 + /* 73730 */ MCD_OPC_FilterValue, + 6, + 72, + 120, + 0, // Skip to: 104527 + /* 73735 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 73738 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 73753 + /* 73743 */ MCD_OPC_CheckPredicate, + 21, + 59, + 120, + 0, // Skip to: 104527 + /* 73748 */ MCD_OPC_Decode, + 185, + 10, + 184, + 2, // Opcode: CMLEv4i32rz + /* 73753 */ MCD_OPC_FilterValue, + 33, + 49, + 120, + 0, // Skip to: 104527 + /* 73758 */ MCD_OPC_CheckPredicate, + 21, + 44, + 120, + 0, // Skip to: 104527 + /* 73763 */ MCD_OPC_Decode, + 131, + 19, + 184, + 2, // Opcode: FRINTIv4f32 + /* 73768 */ MCD_OPC_FilterValue, + 5, + 198, + 0, + 0, // Skip to: 73971 + /* 73773 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 73776 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 73798 + /* 73781 */ MCD_OPC_CheckPredicate, + 21, + 21, + 120, + 0, // Skip to: 104527 + /* 73786 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 14, + 120, + 0, // Skip to: 104527 + /* 73793 */ MCD_OPC_Decode, + 237, + 43, + 187, + 2, // Opcode: UMLSLv4i32_v2i64 + /* 73798 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 73836 + /* 73803 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 73806 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 73821 + /* 73811 */ MCD_OPC_CheckPredicate, + 33, + 247, + 119, + 0, // Skip to: 104527 + /* 73816 */ MCD_OPC_Decode, + 241, + 43, + 187, + 2, // Opcode: UMMLA + /* 73821 */ MCD_OPC_FilterValue, + 1, + 237, + 119, + 0, // Skip to: 104527 + /* 73826 */ MCD_OPC_CheckPredicate, + 21, + 232, + 119, + 0, // Skip to: 104527 + /* 73831 */ MCD_OPC_Decode, + 142, + 43, + 179, + 2, // Opcode: UMAXPv4i32 + /* 73836 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 73889 + /* 73841 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 73844 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 73859 + /* 73849 */ MCD_OPC_CheckPredicate, + 21, + 209, + 119, + 0, // Skip to: 104527 + /* 73854 */ MCD_OPC_Decode, + 162, + 15, + 184, + 2, // Opcode: FCVTPUv4f32 + /* 73859 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 73874 + /* 73864 */ MCD_OPC_CheckPredicate, + 21, + 194, + 119, + 0, // Skip to: 104527 + /* 73869 */ MCD_OPC_Decode, + 151, + 43, + 207, + 2, // Opcode: UMAXVv4i32v + /* 73874 */ MCD_OPC_FilterValue, + 49, + 184, + 119, + 0, // Skip to: 104527 + /* 73879 */ MCD_OPC_CheckPredicate, + 21, + 179, + 119, + 0, // Skip to: 104527 + /* 73884 */ MCD_OPC_Decode, + 184, + 43, + 207, + 2, // Opcode: UMINVv4i32v + /* 73889 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 73911 + /* 73894 */ MCD_OPC_CheckPredicate, + 21, + 164, + 119, + 0, // Skip to: 104527 + /* 73899 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 157, + 119, + 0, // Skip to: 104527 + /* 73906 */ MCD_OPC_Decode, + 175, + 43, + 179, + 2, // Opcode: UMINPv4i32 + /* 73911 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 73933 + /* 73916 */ MCD_OPC_CheckPredicate, + 21, + 142, + 119, + 0, // Skip to: 104527 + /* 73921 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 135, + 119, + 0, // Skip to: 104527 + /* 73928 */ MCD_OPC_Decode, + 244, + 34, + 179, + 2, // Opcode: SQRDMULHv4i32 + /* 73933 */ MCD_OPC_FilterValue, + 6, + 125, + 119, + 0, // Skip to: 104527 + /* 73938 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 73941 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 73956 + /* 73946 */ MCD_OPC_CheckPredicate, + 21, + 112, + 119, + 0, // Skip to: 104527 + /* 73951 */ MCD_OPC_Decode, + 255, + 27, + 184, + 2, // Opcode: NEGv4i32 + /* 73956 */ MCD_OPC_FilterValue, + 33, + 102, + 119, + 0, // Skip to: 104527 + /* 73961 */ MCD_OPC_CheckPredicate, + 21, + 97, + 119, + 0, // Skip to: 104527 + /* 73966 */ MCD_OPC_Decode, + 236, + 15, + 184, + 2, // Opcode: FCVTZUv4f32 + /* 73971 */ MCD_OPC_FilterValue, + 6, + 200, + 0, + 0, // Skip to: 74176 + /* 73976 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 73979 */ MCD_OPC_FilterValue, + 0, + 116, + 0, + 0, // Skip to: 74100 + /* 73984 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 73987 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 74009 + /* 73992 */ MCD_OPC_CheckPredicate, + 21, + 66, + 119, + 0, // Skip to: 104527 + /* 73997 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 59, + 119, + 0, // Skip to: 104527 + /* 74004 */ MCD_OPC_Decode, + 153, + 44, + 179, + 2, // Opcode: UMULLv4i32_v2i64 + /* 74009 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 74062 + /* 74014 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 74017 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 74032 + /* 74022 */ MCD_OPC_CheckPredicate, + 21, + 36, + 119, + 0, // Skip to: 104527 + /* 74027 */ MCD_OPC_Decode, + 205, + 13, + 184, + 2, // Opcode: FCMGEv4i32rz + /* 74032 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 74047 + /* 74037 */ MCD_OPC_CheckPredicate, + 21, + 21, + 119, + 0, // Skip to: 104527 + /* 74042 */ MCD_OPC_Decode, + 136, + 46, + 184, + 2, // Opcode: URSQRTEv4i32 + /* 74047 */ MCD_OPC_FilterValue, + 48, + 11, + 119, + 0, // Skip to: 104527 + /* 74052 */ MCD_OPC_CheckPredicate, + 21, + 6, + 119, + 0, // Skip to: 104527 + /* 74057 */ MCD_OPC_Decode, + 231, + 16, + 207, + 2, // Opcode: FMINNMVv4i32v + /* 74062 */ MCD_OPC_FilterValue, + 3, + 252, + 118, + 0, // Skip to: 104527 + /* 74067 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 74070 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 74085 + /* 74075 */ MCD_OPC_CheckPredicate, + 21, + 239, + 118, + 0, // Skip to: 104527 + /* 74080 */ MCD_OPC_Decode, + 252, + 13, + 184, + 2, // Opcode: FCMLEv4i32rz + /* 74085 */ MCD_OPC_FilterValue, + 33, + 229, + 118, + 0, // Skip to: 104527 + /* 74090 */ MCD_OPC_CheckPredicate, + 21, + 224, + 118, + 0, // Skip to: 104527 + /* 74095 */ MCD_OPC_Decode, + 197, + 19, + 184, + 2, // Opcode: FRSQRTEv4f32 + /* 74100 */ MCD_OPC_FilterValue, + 1, + 214, + 118, + 0, // Skip to: 104527 + /* 74105 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 74108 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 74123 + /* 74113 */ MCD_OPC_CheckPredicate, + 34, + 201, + 118, + 0, // Skip to: 104527 + /* 74118 */ MCD_OPC_Decode, + 239, + 13, + 216, + 2, // Opcode: FCMLAv4f32 + /* 74123 */ MCD_OPC_FilterValue, + 1, + 191, + 118, + 0, // Skip to: 104527 + /* 74128 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 74131 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 74146 + /* 74136 */ MCD_OPC_CheckPredicate, + 21, + 178, + 118, + 0, // Skip to: 104527 + /* 74141 */ MCD_OPC_Decode, + 224, + 16, + 179, + 2, // Opcode: FMINNMPv4f32 + /* 74146 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 74161 + /* 74151 */ MCD_OPC_CheckPredicate, + 25, + 163, + 118, + 0, // Skip to: 104527 + /* 74156 */ MCD_OPC_Decode, + 179, + 17, + 187, + 2, // Opcode: FMLSL2v8f16 + /* 74161 */ MCD_OPC_FilterValue, + 2, + 153, + 118, + 0, // Skip to: 104527 + /* 74166 */ MCD_OPC_CheckPredicate, + 21, + 148, + 118, + 0, // Skip to: 104527 + /* 74171 */ MCD_OPC_Decode, + 209, + 12, + 179, + 2, // Opcode: FABDv4f32 + /* 74176 */ MCD_OPC_FilterValue, + 7, + 138, + 118, + 0, // Skip to: 104527 + /* 74181 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 74184 */ MCD_OPC_FilterValue, + 1, + 56, + 0, + 0, // Skip to: 74245 + /* 74189 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 74192 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 74207 + /* 74197 */ MCD_OPC_CheckPredicate, + 34, + 117, + 118, + 0, // Skip to: 104527 + /* 74202 */ MCD_OPC_Decode, + 156, + 13, + 217, + 2, // Opcode: FCADDv4f32 + /* 74207 */ MCD_OPC_FilterValue, + 1, + 107, + 118, + 0, // Skip to: 104527 + /* 74212 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 74215 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 74230 + /* 74220 */ MCD_OPC_CheckPredicate, + 21, + 94, + 118, + 0, // Skip to: 104527 + /* 74225 */ MCD_OPC_Decode, + 225, + 13, + 179, + 2, // Opcode: FCMGTv4f32 + /* 74230 */ MCD_OPC_FilterValue, + 1, + 84, + 118, + 0, // Skip to: 104527 + /* 74235 */ MCD_OPC_CheckPredicate, + 21, + 79, + 118, + 0, // Skip to: 104527 + /* 74240 */ MCD_OPC_Decode, + 253, + 16, + 179, + 2, // Opcode: FMINPv4f32 + /* 74245 */ MCD_OPC_FilterValue, + 2, + 69, + 0, + 0, // Skip to: 74319 + /* 74250 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 74253 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 74275 + /* 74258 */ MCD_OPC_CheckPredicate, + 21, + 56, + 118, + 0, // Skip to: 104527 + /* 74263 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 49, + 118, + 0, // Skip to: 104527 + /* 74270 */ MCD_OPC_Decode, + 168, + 18, + 184, + 2, // Opcode: FNEGv4f32 + /* 74275 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 74297 + /* 74280 */ MCD_OPC_CheckPredicate, + 21, + 34, + 118, + 0, // Skip to: 104527 + /* 74285 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 27, + 118, + 0, // Skip to: 104527 + /* 74292 */ MCD_OPC_Decode, + 222, + 19, + 184, + 2, // Opcode: FSQRTv4f32 + /* 74297 */ MCD_OPC_FilterValue, + 48, + 17, + 118, + 0, // Skip to: 104527 + /* 74302 */ MCD_OPC_CheckPredicate, + 21, + 12, + 118, + 0, // Skip to: 104527 + /* 74307 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 5, + 118, + 0, // Skip to: 104527 + /* 74314 */ MCD_OPC_Decode, + 132, + 17, + 207, + 2, // Opcode: FMINVv4i32v + /* 74319 */ MCD_OPC_FilterValue, + 3, + 251, + 117, + 0, // Skip to: 104527 + /* 74324 */ MCD_OPC_CheckPredicate, + 21, + 246, + 117, + 0, // Skip to: 104527 + /* 74329 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 239, + 117, + 0, // Skip to: 104527 + /* 74336 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 232, + 117, + 0, // Skip to: 104527 + /* 74343 */ MCD_OPC_Decode, + 242, + 12, + 179, + 2, // Opcode: FACGTv4f32 + /* 74348 */ MCD_OPC_FilterValue, + 6, + 222, + 117, + 0, // Skip to: 104527 + /* 74353 */ MCD_OPC_CheckPredicate, + 27, + 217, + 117, + 0, // Skip to: 104527 + /* 74358 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 210, + 117, + 0, // Skip to: 104527 + /* 74365 */ MCD_OPC_Decode, + 232, + 47, + 219, + 2, // Opcode: XAR + /* 74370 */ MCD_OPC_FilterValue, + 11, + 66, + 12, + 0, // Skip to: 77513 + /* 74375 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 74378 */ MCD_OPC_FilterValue, + 0, + 154, + 1, + 0, // Skip to: 74793 + /* 74383 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 74386 */ MCD_OPC_FilterValue, + 1, + 91, + 0, + 0, // Skip to: 74482 + /* 74391 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 74394 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 74416 + /* 74399 */ MCD_OPC_CheckPredicate, + 23, + 171, + 117, + 0, // Skip to: 104527 + /* 74404 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 164, + 117, + 0, // Skip to: 104527 + /* 74411 */ MCD_OPC_Decode, + 241, + 16, + 155, + 2, // Opcode: FMINNMv4f16 + /* 74416 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 74438 + /* 74421 */ MCD_OPC_CheckPredicate, + 23, + 149, + 117, + 0, // Skip to: 104527 + /* 74426 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 142, + 117, + 0, // Skip to: 104527 + /* 74433 */ MCD_OPC_Decode, + 223, + 16, + 155, + 2, // Opcode: FMINNMPv4f16 + /* 74438 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 74460 + /* 74443 */ MCD_OPC_CheckPredicate, + 23, + 127, + 117, + 0, // Skip to: 104527 + /* 74448 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 120, + 117, + 0, // Skip to: 104527 + /* 74455 */ MCD_OPC_Decode, + 243, + 16, + 179, + 2, // Opcode: FMINNMv8f16 + /* 74460 */ MCD_OPC_FilterValue, + 3, + 110, + 117, + 0, // Skip to: 104527 + /* 74465 */ MCD_OPC_CheckPredicate, + 23, + 105, + 117, + 0, // Skip to: 104527 + /* 74470 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 98, + 117, + 0, // Skip to: 104527 + /* 74477 */ MCD_OPC_Decode, + 225, + 16, + 179, + 2, // Opcode: FMINNMPv8f16 + /* 74482 */ MCD_OPC_FilterValue, + 3, + 85, + 0, + 0, // Skip to: 74572 + /* 74487 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 74490 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 74512 + /* 74495 */ MCD_OPC_CheckPredicate, + 23, + 75, + 117, + 0, // Skip to: 104527 + /* 74500 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 68, + 117, + 0, // Skip to: 104527 + /* 74507 */ MCD_OPC_Decode, + 201, + 17, + 176, + 2, // Opcode: FMLSv4f16 + /* 74512 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 74550 + /* 74517 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 74520 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 74535 + /* 74525 */ MCD_OPC_CheckPredicate, + 23, + 45, + 117, + 0, // Skip to: 104527 + /* 74530 */ MCD_OPC_Decode, + 205, + 17, + 187, + 2, // Opcode: FMLSv8f16 + /* 74535 */ MCD_OPC_FilterValue, + 1, + 35, + 117, + 0, // Skip to: 104527 + /* 74540 */ MCD_OPC_CheckPredicate, + 21, + 30, + 117, + 0, // Skip to: 104527 + /* 74545 */ MCD_OPC_Decode, + 154, + 33, + 179, + 2, // Opcode: SQADDv2i64 + /* 74550 */ MCD_OPC_FilterValue, + 3, + 20, + 117, + 0, // Skip to: 104527 + /* 74555 */ MCD_OPC_CheckPredicate, + 21, + 15, + 117, + 0, // Skip to: 104527 + /* 74560 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 8, + 117, + 0, // Skip to: 104527 + /* 74567 */ MCD_OPC_Decode, + 175, + 44, + 179, + 2, // Opcode: UQADDv2i64 + /* 74572 */ MCD_OPC_FilterValue, + 5, + 91, + 0, + 0, // Skip to: 74668 + /* 74577 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 74580 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 74602 + /* 74585 */ MCD_OPC_CheckPredicate, + 23, + 241, + 116, + 0, // Skip to: 104527 + /* 74590 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 234, + 116, + 0, // Skip to: 104527 + /* 74597 */ MCD_OPC_Decode, + 244, + 19, + 155, + 2, // Opcode: FSUBv4f16 + /* 74602 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 74624 + /* 74607 */ MCD_OPC_CheckPredicate, + 23, + 219, + 116, + 0, // Skip to: 104527 + /* 74612 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 212, + 116, + 0, // Skip to: 104527 + /* 74619 */ MCD_OPC_Decode, + 208, + 12, + 155, + 2, // Opcode: FABDv4f16 + /* 74624 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 74646 + /* 74629 */ MCD_OPC_CheckPredicate, + 23, + 197, + 116, + 0, // Skip to: 104527 + /* 74634 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 190, + 116, + 0, // Skip to: 104527 + /* 74641 */ MCD_OPC_Decode, + 246, + 19, + 179, + 2, // Opcode: FSUBv8f16 + /* 74646 */ MCD_OPC_FilterValue, + 3, + 180, + 116, + 0, // Skip to: 104527 + /* 74651 */ MCD_OPC_CheckPredicate, + 23, + 175, + 116, + 0, // Skip to: 104527 + /* 74656 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 168, + 116, + 0, // Skip to: 104527 + /* 74663 */ MCD_OPC_Decode, + 210, + 12, + 179, + 2, // Opcode: FABDv8f16 + /* 74668 */ MCD_OPC_FilterValue, + 6, + 24, + 0, + 0, // Skip to: 74697 + /* 74673 */ MCD_OPC_CheckPredicate, + 21, + 153, + 116, + 0, // Skip to: 104527 + /* 74678 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 146, + 116, + 0, // Skip to: 104527 + /* 74685 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 139, + 116, + 0, // Skip to: 104527 + /* 74692 */ MCD_OPC_Decode, + 135, + 47, + 179, + 2, // Opcode: UZP1v2i64 + /* 74697 */ MCD_OPC_FilterValue, + 7, + 129, + 116, + 0, // Skip to: 104527 + /* 74702 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 74705 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 74727 + /* 74710 */ MCD_OPC_CheckPredicate, + 21, + 116, + 116, + 0, // Skip to: 104527 + /* 74715 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 109, + 116, + 0, // Skip to: 104527 + /* 74722 */ MCD_OPC_Decode, + 145, + 28, + 155, + 2, // Opcode: ORNv8i8 + /* 74727 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 74749 + /* 74732 */ MCD_OPC_CheckPredicate, + 21, + 94, + 116, + 0, // Skip to: 104527 + /* 74737 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 87, + 116, + 0, // Skip to: 104527 + /* 74744 */ MCD_OPC_Decode, + 237, + 8, + 176, + 2, // Opcode: BIFv8i8 + /* 74749 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 74771 + /* 74754 */ MCD_OPC_CheckPredicate, + 21, + 72, + 116, + 0, // Skip to: 104527 + /* 74759 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 65, + 116, + 0, // Skip to: 104527 + /* 74766 */ MCD_OPC_Decode, + 144, + 28, + 179, + 2, // Opcode: ORNv16i8 + /* 74771 */ MCD_OPC_FilterValue, + 3, + 55, + 116, + 0, // Skip to: 104527 + /* 74776 */ MCD_OPC_CheckPredicate, + 21, + 50, + 116, + 0, // Skip to: 104527 + /* 74781 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 43, + 116, + 0, // Skip to: 104527 + /* 74788 */ MCD_OPC_Decode, + 236, + 8, + 187, + 2, // Opcode: BIFv16i8 + /* 74793 */ MCD_OPC_FilterValue, + 1, + 218, + 1, + 0, // Skip to: 75272 + /* 74798 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 74801 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 74853 + /* 74806 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 74809 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 74831 + /* 74814 */ MCD_OPC_CheckPredicate, + 23, + 12, + 116, + 0, // Skip to: 104527 + /* 74819 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 5, + 116, + 0, // Skip to: 104527 + /* 74826 */ MCD_OPC_Decode, + 224, + 13, + 155, + 2, // Opcode: FCMGTv4f16 + /* 74831 */ MCD_OPC_FilterValue, + 3, + 251, + 115, + 0, // Skip to: 104527 + /* 74836 */ MCD_OPC_CheckPredicate, + 23, + 246, + 115, + 0, // Skip to: 104527 + /* 74841 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 239, + 115, + 0, // Skip to: 104527 + /* 74848 */ MCD_OPC_Decode, + 228, + 13, + 179, + 2, // Opcode: FCMGTv8f16 + /* 74853 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 74882 + /* 74858 */ MCD_OPC_CheckPredicate, + 21, + 224, + 115, + 0, // Skip to: 104527 + /* 74863 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 217, + 115, + 0, // Skip to: 104527 + /* 74870 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 210, + 115, + 0, // Skip to: 104527 + /* 74877 */ MCD_OPC_Decode, + 194, + 41, + 179, + 2, // Opcode: TRN1v2i64 + /* 74882 */ MCD_OPC_FilterValue, + 3, + 85, + 0, + 0, // Skip to: 74972 + /* 74887 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 74890 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 74912 + /* 74895 */ MCD_OPC_CheckPredicate, + 23, + 187, + 115, + 0, // Skip to: 104527 + /* 74900 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 180, + 115, + 0, // Skip to: 104527 + /* 74907 */ MCD_OPC_Decode, + 241, + 12, + 155, + 2, // Opcode: FACGTv4f16 + /* 74912 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 74934 + /* 74917 */ MCD_OPC_CheckPredicate, + 21, + 165, + 115, + 0, // Skip to: 104527 + /* 74922 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 158, + 115, + 0, // Skip to: 104527 + /* 74929 */ MCD_OPC_Decode, + 142, + 36, + 179, + 2, // Opcode: SQSUBv2i64 + /* 74934 */ MCD_OPC_FilterValue, + 3, + 148, + 115, + 0, // Skip to: 104527 + /* 74939 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 74942 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 74957 + /* 74947 */ MCD_OPC_CheckPredicate, + 23, + 135, + 115, + 0, // Skip to: 104527 + /* 74952 */ MCD_OPC_Decode, + 243, + 12, + 179, + 2, // Opcode: FACGTv8f16 + /* 74957 */ MCD_OPC_FilterValue, + 1, + 125, + 115, + 0, // Skip to: 104527 + /* 74962 */ MCD_OPC_CheckPredicate, + 21, + 120, + 115, + 0, // Skip to: 104527 + /* 74967 */ MCD_OPC_Decode, + 201, + 45, + 179, + 2, // Opcode: UQSUBv2i64 + /* 74972 */ MCD_OPC_FilterValue, + 5, + 123, + 0, + 0, // Skip to: 75100 + /* 74977 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 74980 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 75002 + /* 74985 */ MCD_OPC_CheckPredicate, + 23, + 97, + 115, + 0, // Skip to: 104527 + /* 74990 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 90, + 115, + 0, // Skip to: 104527 + /* 74997 */ MCD_OPC_Decode, + 142, + 17, + 155, + 2, // Opcode: FMINv4f16 + /* 75002 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 75024 + /* 75007 */ MCD_OPC_CheckPredicate, + 23, + 75, + 115, + 0, // Skip to: 104527 + /* 75012 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 68, + 115, + 0, // Skip to: 104527 + /* 75019 */ MCD_OPC_Decode, + 252, + 16, + 155, + 2, // Opcode: FMINPv4f16 + /* 75024 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 75062 + /* 75029 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 75032 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 75047 + /* 75037 */ MCD_OPC_CheckPredicate, + 23, + 45, + 115, + 0, // Skip to: 104527 + /* 75042 */ MCD_OPC_Decode, + 144, + 17, + 179, + 2, // Opcode: FMINv8f16 + /* 75047 */ MCD_OPC_FilterValue, + 1, + 35, + 115, + 0, // Skip to: 104527 + /* 75052 */ MCD_OPC_CheckPredicate, + 21, + 30, + 115, + 0, // Skip to: 104527 + /* 75057 */ MCD_OPC_Decode, + 148, + 10, + 179, + 2, // Opcode: CMGTv2i64 + /* 75062 */ MCD_OPC_FilterValue, + 3, + 20, + 115, + 0, // Skip to: 104527 + /* 75067 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 75070 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 75085 + /* 75075 */ MCD_OPC_CheckPredicate, + 23, + 7, + 115, + 0, // Skip to: 104527 + /* 75080 */ MCD_OPC_Decode, + 254, + 16, + 179, + 2, // Opcode: FMINPv8f16 + /* 75085 */ MCD_OPC_FilterValue, + 1, + 253, + 114, + 0, // Skip to: 104527 + /* 75090 */ MCD_OPC_CheckPredicate, + 21, + 248, + 114, + 0, // Skip to: 104527 + /* 75095 */ MCD_OPC_Decode, + 161, + 10, + 179, + 2, // Opcode: CMHIv2i64 + /* 75100 */ MCD_OPC_FilterValue, + 6, + 77, + 0, + 0, // Skip to: 75182 + /* 75105 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 75108 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 75130 + /* 75113 */ MCD_OPC_CheckPredicate, + 21, + 225, + 114, + 0, // Skip to: 104527 + /* 75118 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 218, + 114, + 0, // Skip to: 104527 + /* 75125 */ MCD_OPC_Decode, + 130, + 48, + 179, + 2, // Opcode: ZIP1v2i64 + /* 75130 */ MCD_OPC_FilterValue, + 1, + 208, + 114, + 0, // Skip to: 104527 + /* 75135 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75138 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 75160 + /* 75143 */ MCD_OPC_CheckPredicate, + 21, + 195, + 114, + 0, // Skip to: 104527 + /* 75148 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 188, + 114, + 0, // Skip to: 104527 + /* 75155 */ MCD_OPC_Decode, + 247, + 40, + 193, + 2, // Opcode: SUQADDv2i64 + /* 75160 */ MCD_OPC_FilterValue, + 3, + 178, + 114, + 0, // Skip to: 104527 + /* 75165 */ MCD_OPC_CheckPredicate, + 21, + 173, + 114, + 0, // Skip to: 104527 + /* 75170 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 166, + 114, + 0, // Skip to: 104527 + /* 75177 */ MCD_OPC_Decode, + 199, + 46, + 193, + 2, // Opcode: USQADDv2i64 + /* 75182 */ MCD_OPC_FilterValue, + 7, + 156, + 114, + 0, // Skip to: 104527 + /* 75187 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75190 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 75212 + /* 75195 */ MCD_OPC_CheckPredicate, + 23, + 143, + 114, + 0, // Skip to: 104527 + /* 75200 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 136, + 114, + 0, // Skip to: 104527 + /* 75207 */ MCD_OPC_Decode, + 207, + 19, + 155, + 2, // Opcode: FRSQRTSv4f16 + /* 75212 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 75250 + /* 75217 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 75220 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 75235 + /* 75225 */ MCD_OPC_CheckPredicate, + 23, + 113, + 114, + 0, // Skip to: 104527 + /* 75230 */ MCD_OPC_Decode, + 209, + 19, + 179, + 2, // Opcode: FRSQRTSv8f16 + /* 75235 */ MCD_OPC_FilterValue, + 1, + 103, + 114, + 0, // Skip to: 104527 + /* 75240 */ MCD_OPC_CheckPredicate, + 21, + 98, + 114, + 0, // Skip to: 104527 + /* 75245 */ MCD_OPC_Decode, + 132, + 10, + 179, + 2, // Opcode: CMGEv2i64 + /* 75250 */ MCD_OPC_FilterValue, + 3, + 88, + 114, + 0, // Skip to: 104527 + /* 75255 */ MCD_OPC_CheckPredicate, + 21, + 83, + 114, + 0, // Skip to: 104527 + /* 75260 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 76, + 114, + 0, // Skip to: 104527 + /* 75267 */ MCD_OPC_Decode, + 169, + 10, + 179, + 2, // Opcode: CMHSv2i64 + /* 75272 */ MCD_OPC_FilterValue, + 2, + 240, + 0, + 0, // Skip to: 75517 + /* 75277 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 75280 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 75332 + /* 75285 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75288 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 75310 + /* 75293 */ MCD_OPC_CheckPredicate, + 21, + 45, + 114, + 0, // Skip to: 104527 + /* 75298 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 38, + 114, + 0, // Skip to: 104527 + /* 75305 */ MCD_OPC_Decode, + 254, + 36, + 179, + 2, // Opcode: SSHLv2i64 + /* 75310 */ MCD_OPC_FilterValue, + 3, + 28, + 114, + 0, // Skip to: 104527 + /* 75315 */ MCD_OPC_CheckPredicate, + 21, + 23, + 114, + 0, // Skip to: 104527 + /* 75320 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 16, + 114, + 0, // Skip to: 104527 + /* 75327 */ MCD_OPC_Decode, + 170, + 46, + 179, + 2, // Opcode: USHLv2i64 + /* 75332 */ MCD_OPC_FilterValue, + 3, + 47, + 0, + 0, // Skip to: 75384 + /* 75337 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75340 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 75362 + /* 75345 */ MCD_OPC_CheckPredicate, + 21, + 249, + 113, + 0, // Skip to: 104527 + /* 75350 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 242, + 113, + 0, // Skip to: 104527 + /* 75357 */ MCD_OPC_Decode, + 208, + 35, + 179, + 2, // Opcode: SQSHLv2i64 + /* 75362 */ MCD_OPC_FilterValue, + 3, + 232, + 113, + 0, // Skip to: 104527 + /* 75367 */ MCD_OPC_CheckPredicate, + 21, + 227, + 113, + 0, // Skip to: 104527 + /* 75372 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 220, + 113, + 0, // Skip to: 104527 + /* 75379 */ MCD_OPC_Decode, + 154, + 45, + 179, + 2, // Opcode: UQSHLv2i64 + /* 75384 */ MCD_OPC_FilterValue, + 5, + 47, + 0, + 0, // Skip to: 75436 + /* 75389 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75392 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 75414 + /* 75397 */ MCD_OPC_CheckPredicate, + 21, + 197, + 113, + 0, // Skip to: 104527 + /* 75402 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 190, + 113, + 0, // Skip to: 104527 + /* 75409 */ MCD_OPC_Decode, + 210, + 36, + 179, + 2, // Opcode: SRSHLv2i64 + /* 75414 */ MCD_OPC_FilterValue, + 3, + 180, + 113, + 0, // Skip to: 104527 + /* 75419 */ MCD_OPC_CheckPredicate, + 21, + 175, + 113, + 0, // Skip to: 104527 + /* 75424 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 168, + 113, + 0, // Skip to: 104527 + /* 75431 */ MCD_OPC_Decode, + 245, + 45, + 179, + 2, // Opcode: URSHLv2i64 + /* 75436 */ MCD_OPC_FilterValue, + 6, + 24, + 0, + 0, // Skip to: 75465 + /* 75441 */ MCD_OPC_CheckPredicate, + 21, + 153, + 113, + 0, // Skip to: 104527 + /* 75446 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 146, + 113, + 0, // Skip to: 104527 + /* 75453 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 139, + 113, + 0, // Skip to: 104527 + /* 75460 */ MCD_OPC_Decode, + 151, + 47, + 179, + 2, // Opcode: UZP2v2i64 + /* 75465 */ MCD_OPC_FilterValue, + 7, + 129, + 113, + 0, // Skip to: 104527 + /* 75470 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75473 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 75495 + /* 75478 */ MCD_OPC_CheckPredicate, + 21, + 116, + 113, + 0, // Skip to: 104527 + /* 75483 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 109, + 113, + 0, // Skip to: 104527 + /* 75490 */ MCD_OPC_Decode, + 134, + 35, + 179, + 2, // Opcode: SQRSHLv2i64 + /* 75495 */ MCD_OPC_FilterValue, + 3, + 99, + 113, + 0, // Skip to: 104527 + /* 75500 */ MCD_OPC_CheckPredicate, + 21, + 94, + 113, + 0, // Skip to: 104527 + /* 75505 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 87, + 113, + 0, // Skip to: 104527 + /* 75512 */ MCD_OPC_Decode, + 238, + 44, + 179, + 2, // Opcode: UQRSHLv2i64 + /* 75517 */ MCD_OPC_FilterValue, + 3, + 114, + 0, + 0, // Skip to: 75636 + /* 75522 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 75525 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 75554 + /* 75530 */ MCD_OPC_CheckPredicate, + 21, + 64, + 113, + 0, // Skip to: 104527 + /* 75535 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 57, + 113, + 0, // Skip to: 104527 + /* 75542 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 50, + 113, + 0, // Skip to: 104527 + /* 75549 */ MCD_OPC_Decode, + 210, + 41, + 179, + 2, // Opcode: TRN2v2i64 + /* 75554 */ MCD_OPC_FilterValue, + 6, + 40, + 113, + 0, // Skip to: 104527 + /* 75559 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 75562 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 75584 + /* 75567 */ MCD_OPC_CheckPredicate, + 21, + 27, + 113, + 0, // Skip to: 104527 + /* 75572 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 20, + 113, + 0, // Skip to: 104527 + /* 75579 */ MCD_OPC_Decode, + 146, + 48, + 179, + 2, // Opcode: ZIP2v2i64 + /* 75584 */ MCD_OPC_FilterValue, + 1, + 10, + 113, + 0, // Skip to: 104527 + /* 75589 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75592 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 75614 + /* 75597 */ MCD_OPC_CheckPredicate, + 21, + 253, + 112, + 0, // Skip to: 104527 + /* 75602 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 246, + 112, + 0, // Skip to: 104527 + /* 75609 */ MCD_OPC_Decode, + 131, + 33, + 184, + 2, // Opcode: SQABSv2i64 + /* 75614 */ MCD_OPC_FilterValue, + 3, + 236, + 112, + 0, // Skip to: 104527 + /* 75619 */ MCD_OPC_CheckPredicate, + 21, + 231, + 112, + 0, // Skip to: 104527 + /* 75624 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 224, + 112, + 0, // Skip to: 104527 + /* 75631 */ MCD_OPC_Decode, + 180, + 34, + 184, + 2, // Opcode: SQNEGv2i64 + /* 75636 */ MCD_OPC_FilterValue, + 4, + 166, + 1, + 0, // Skip to: 76063 + /* 75641 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 75644 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 75673 + /* 75649 */ MCD_OPC_CheckPredicate, + 27, + 201, + 112, + 0, // Skip to: 104527 + /* 75654 */ MCD_OPC_CheckField, + 29, + 3, + 6, + 194, + 112, + 0, // Skip to: 104527 + /* 75661 */ MCD_OPC_CheckField, + 16, + 6, + 0, + 187, + 112, + 0, // Skip to: 104527 + /* 75668 */ MCD_OPC_Decode, + 140, + 31, + 193, + 2, // Opcode: SHA512SU0 + /* 75673 */ MCD_OPC_FilterValue, + 1, + 69, + 0, + 0, // Skip to: 75747 + /* 75678 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75681 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 75703 + /* 75686 */ MCD_OPC_CheckPredicate, + 21, + 164, + 112, + 0, // Skip to: 104527 + /* 75691 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 157, + 112, + 0, // Skip to: 104527 + /* 75698 */ MCD_OPC_Decode, + 213, + 7, + 179, + 2, // Opcode: ADDv2i64 + /* 75703 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 75725 + /* 75708 */ MCD_OPC_CheckPredicate, + 21, + 142, + 112, + 0, // Skip to: 104527 + /* 75713 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 135, + 112, + 0, // Skip to: 104527 + /* 75720 */ MCD_OPC_Decode, + 219, + 40, + 179, + 2, // Opcode: SUBv2i64 + /* 75725 */ MCD_OPC_FilterValue, + 6, + 125, + 112, + 0, // Skip to: 104527 + /* 75730 */ MCD_OPC_CheckPredicate, + 31, + 120, + 112, + 0, // Skip to: 104527 + /* 75735 */ MCD_OPC_CheckField, + 16, + 6, + 0, + 113, + 112, + 0, // Skip to: 104527 + /* 75742 */ MCD_OPC_Decode, + 211, + 31, + 193, + 2, // Opcode: SM4E + /* 75747 */ MCD_OPC_FilterValue, + 2, + 101, + 0, + 0, // Skip to: 75853 + /* 75752 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 75755 */ MCD_OPC_FilterValue, + 32, + 33, + 0, + 0, // Skip to: 75793 + /* 75760 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75763 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 75778 + /* 75768 */ MCD_OPC_CheckPredicate, + 21, + 82, + 112, + 0, // Skip to: 104527 + /* 75773 */ MCD_OPC_Decode, + 149, + 10, + 184, + 2, // Opcode: CMGTv2i64rz + /* 75778 */ MCD_OPC_FilterValue, + 3, + 72, + 112, + 0, // Skip to: 104527 + /* 75783 */ MCD_OPC_CheckPredicate, + 21, + 67, + 112, + 0, // Skip to: 104527 + /* 75788 */ MCD_OPC_Decode, + 133, + 10, + 184, + 2, // Opcode: CMGEv2i64rz + /* 75793 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 75815 + /* 75798 */ MCD_OPC_CheckPredicate, + 21, + 52, + 112, + 0, // Skip to: 104527 + /* 75803 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 45, + 112, + 0, // Skip to: 104527 + /* 75810 */ MCD_OPC_Decode, + 162, + 19, + 184, + 2, // Opcode: FRINTPv2f64 + /* 75815 */ MCD_OPC_FilterValue, + 57, + 35, + 112, + 0, // Skip to: 104527 + /* 75820 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75823 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 75838 + /* 75828 */ MCD_OPC_CheckPredicate, + 23, + 22, + 112, + 0, // Skip to: 104527 + /* 75833 */ MCD_OPC_Decode, + 163, + 19, + 156, + 2, // Opcode: FRINTPv4f16 + /* 75838 */ MCD_OPC_FilterValue, + 2, + 12, + 112, + 0, // Skip to: 104527 + /* 75843 */ MCD_OPC_CheckPredicate, + 23, + 7, + 112, + 0, // Skip to: 104527 + /* 75848 */ MCD_OPC_Decode, + 165, + 19, + 184, + 2, // Opcode: FRINTPv8f16 + /* 75853 */ MCD_OPC_FilterValue, + 3, + 47, + 0, + 0, // Skip to: 75905 + /* 75858 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75861 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 75883 + /* 75866 */ MCD_OPC_CheckPredicate, + 21, + 240, + 111, + 0, // Skip to: 104527 + /* 75871 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 233, + 111, + 0, // Skip to: 104527 + /* 75878 */ MCD_OPC_Decode, + 165, + 11, + 179, + 2, // Opcode: CMTSTv2i64 + /* 75883 */ MCD_OPC_FilterValue, + 3, + 223, + 111, + 0, // Skip to: 104527 + /* 75888 */ MCD_OPC_CheckPredicate, + 21, + 218, + 111, + 0, // Skip to: 104527 + /* 75893 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 211, + 111, + 0, // Skip to: 104527 + /* 75900 */ MCD_OPC_Decode, + 244, + 9, + 179, + 2, // Opcode: CMEQv2i64 + /* 75905 */ MCD_OPC_FilterValue, + 6, + 201, + 111, + 0, // Skip to: 104527 + /* 75910 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 75913 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 75935 + /* 75918 */ MCD_OPC_CheckPredicate, + 23, + 188, + 111, + 0, // Skip to: 104527 + /* 75923 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 181, + 111, + 0, // Skip to: 104527 + /* 75930 */ MCD_OPC_Decode, + 185, + 19, + 156, + 2, // Opcode: FRINTZv4f16 + /* 75935 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 75957 + /* 75940 */ MCD_OPC_CheckPredicate, + 23, + 166, + 111, + 0, // Skip to: 104527 + /* 75945 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 159, + 111, + 0, // Skip to: 104527 + /* 75952 */ MCD_OPC_Decode, + 130, + 19, + 156, + 2, // Opcode: FRINTIv4f16 + /* 75957 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 76010 + /* 75962 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 75965 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 75980 + /* 75970 */ MCD_OPC_CheckPredicate, + 21, + 136, + 111, + 0, // Skip to: 104527 + /* 75975 */ MCD_OPC_Decode, + 245, + 9, + 184, + 2, // Opcode: CMEQv2i64rz + /* 75980 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 75995 + /* 75985 */ MCD_OPC_CheckPredicate, + 21, + 121, + 111, + 0, // Skip to: 104527 + /* 75990 */ MCD_OPC_Decode, + 184, + 19, + 184, + 2, // Opcode: FRINTZv2f64 + /* 75995 */ MCD_OPC_FilterValue, + 57, + 111, + 111, + 0, // Skip to: 104527 + /* 76000 */ MCD_OPC_CheckPredicate, + 23, + 106, + 111, + 0, // Skip to: 104527 + /* 76005 */ MCD_OPC_Decode, + 187, + 19, + 184, + 2, // Opcode: FRINTZv8f16 + /* 76010 */ MCD_OPC_FilterValue, + 3, + 96, + 111, + 0, // Skip to: 104527 + /* 76015 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 76018 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 76033 + /* 76023 */ MCD_OPC_CheckPredicate, + 21, + 83, + 111, + 0, // Skip to: 104527 + /* 76028 */ MCD_OPC_Decode, + 183, + 10, + 184, + 2, // Opcode: CMLEv2i64rz + /* 76033 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 76048 + /* 76038 */ MCD_OPC_CheckPredicate, + 21, + 68, + 111, + 0, // Skip to: 104527 + /* 76043 */ MCD_OPC_Decode, + 129, + 19, + 184, + 2, // Opcode: FRINTIv2f64 + /* 76048 */ MCD_OPC_FilterValue, + 57, + 58, + 111, + 0, // Skip to: 104527 + /* 76053 */ MCD_OPC_CheckPredicate, + 23, + 53, + 111, + 0, // Skip to: 104527 + /* 76058 */ MCD_OPC_Decode, + 132, + 19, + 184, + 2, // Opcode: FRINTIv8f16 + /* 76063 */ MCD_OPC_FilterValue, + 5, + 93, + 1, + 0, // Skip to: 76417 + /* 76068 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 76071 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 76123 + /* 76076 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 76079 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 76101 + /* 76084 */ MCD_OPC_CheckPredicate, + 23, + 22, + 111, + 0, // Skip to: 104527 + /* 76089 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 15, + 111, + 0, // Skip to: 104527 + /* 76096 */ MCD_OPC_Decode, + 147, + 15, + 156, + 2, // Opcode: FCVTPSv4f16 + /* 76101 */ MCD_OPC_FilterValue, + 6, + 5, + 111, + 0, // Skip to: 104527 + /* 76106 */ MCD_OPC_CheckPredicate, + 23, + 0, + 111, + 0, // Skip to: 104527 + /* 76111 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 249, + 110, + 0, // Skip to: 104527 + /* 76118 */ MCD_OPC_Decode, + 200, + 15, + 156, + 2, // Opcode: FCVTZSv4f16 + /* 76123 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 76175 + /* 76128 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 76131 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 76153 + /* 76136 */ MCD_OPC_CheckPredicate, + 23, + 226, + 110, + 0, // Skip to: 104527 + /* 76141 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 219, + 110, + 0, // Skip to: 104527 + /* 76148 */ MCD_OPC_Decode, + 161, + 15, + 156, + 2, // Opcode: FCVTPUv4f16 + /* 76153 */ MCD_OPC_FilterValue, + 6, + 209, + 110, + 0, // Skip to: 104527 + /* 76158 */ MCD_OPC_CheckPredicate, + 23, + 204, + 110, + 0, // Skip to: 104527 + /* 76163 */ MCD_OPC_CheckField, + 16, + 6, + 57, + 197, + 110, + 0, // Skip to: 104527 + /* 76170 */ MCD_OPC_Decode, + 235, + 15, + 156, + 2, // Opcode: FCVTZUv4f16 + /* 76175 */ MCD_OPC_FilterValue, + 2, + 131, + 0, + 0, // Skip to: 76311 + /* 76180 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 76183 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 76236 + /* 76188 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 76191 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 76206 + /* 76196 */ MCD_OPC_CheckPredicate, + 21, + 166, + 110, + 0, // Skip to: 104527 + /* 76201 */ MCD_OPC_Decode, + 191, + 10, + 184, + 2, // Opcode: CMLTv2i64rz + /* 76206 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 76221 + /* 76211 */ MCD_OPC_CheckPredicate, + 21, + 151, + 110, + 0, // Skip to: 104527 + /* 76216 */ MCD_OPC_Decode, + 146, + 15, + 184, + 2, // Opcode: FCVTPSv2f64 + /* 76221 */ MCD_OPC_FilterValue, + 57, + 141, + 110, + 0, // Skip to: 104527 + /* 76226 */ MCD_OPC_CheckPredicate, + 23, + 136, + 110, + 0, // Skip to: 104527 + /* 76231 */ MCD_OPC_Decode, + 149, + 15, + 184, + 2, // Opcode: FCVTPSv8f16 + /* 76236 */ MCD_OPC_FilterValue, + 6, + 48, + 0, + 0, // Skip to: 76289 + /* 76241 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 76244 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 76259 + /* 76249 */ MCD_OPC_CheckPredicate, + 21, + 113, + 110, + 0, // Skip to: 104527 + /* 76254 */ MCD_OPC_Decode, + 135, + 7, + 184, + 2, // Opcode: ABSv2i64 + /* 76259 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 76274 + /* 76264 */ MCD_OPC_CheckPredicate, + 21, + 98, + 110, + 0, // Skip to: 104527 + /* 76269 */ MCD_OPC_Decode, + 197, + 15, + 184, + 2, // Opcode: FCVTZSv2f64 + /* 76274 */ MCD_OPC_FilterValue, + 57, + 88, + 110, + 0, // Skip to: 104527 + /* 76279 */ MCD_OPC_CheckPredicate, + 23, + 83, + 110, + 0, // Skip to: 104527 + /* 76284 */ MCD_OPC_Decode, + 204, + 15, + 184, + 2, // Opcode: FCVTZSv8f16 + /* 76289 */ MCD_OPC_FilterValue, + 7, + 73, + 110, + 0, // Skip to: 104527 + /* 76294 */ MCD_OPC_CheckPredicate, + 21, + 68, + 110, + 0, // Skip to: 104527 + /* 76299 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 61, + 110, + 0, // Skip to: 104527 + /* 76306 */ MCD_OPC_Decode, + 170, + 7, + 179, + 2, // Opcode: ADDPv2i64 + /* 76311 */ MCD_OPC_FilterValue, + 3, + 51, + 110, + 0, // Skip to: 104527 + /* 76316 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 76319 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 76341 + /* 76324 */ MCD_OPC_CheckPredicate, + 21, + 38, + 110, + 0, // Skip to: 104527 + /* 76329 */ MCD_OPC_CheckField, + 10, + 3, + 6, + 31, + 110, + 0, // Skip to: 104527 + /* 76336 */ MCD_OPC_Decode, + 253, + 27, + 184, + 2, // Opcode: NEGv2i64 + /* 76341 */ MCD_OPC_FilterValue, + 33, + 33, + 0, + 0, // Skip to: 76379 + /* 76346 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 76349 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 76364 + /* 76354 */ MCD_OPC_CheckPredicate, + 21, + 8, + 110, + 0, // Skip to: 104527 + /* 76359 */ MCD_OPC_Decode, + 160, + 15, + 184, + 2, // Opcode: FCVTPUv2f64 + /* 76364 */ MCD_OPC_FilterValue, + 6, + 254, + 109, + 0, // Skip to: 104527 + /* 76369 */ MCD_OPC_CheckPredicate, + 21, + 249, + 109, + 0, // Skip to: 104527 + /* 76374 */ MCD_OPC_Decode, + 232, + 15, + 184, + 2, // Opcode: FCVTZUv2f64 + /* 76379 */ MCD_OPC_FilterValue, + 57, + 239, + 109, + 0, // Skip to: 104527 + /* 76384 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 76387 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 76402 + /* 76392 */ MCD_OPC_CheckPredicate, + 23, + 226, + 109, + 0, // Skip to: 104527 + /* 76397 */ MCD_OPC_Decode, + 163, + 15, + 184, + 2, // Opcode: FCVTPUv8f16 + /* 76402 */ MCD_OPC_FilterValue, + 6, + 216, + 109, + 0, // Skip to: 104527 + /* 76407 */ MCD_OPC_CheckPredicate, + 23, + 211, + 109, + 0, // Skip to: 104527 + /* 76412 */ MCD_OPC_Decode, + 239, + 15, + 184, + 2, // Opcode: FCVTZUv8f16 + /* 76417 */ MCD_OPC_FilterValue, + 6, + 4, + 2, + 0, // Skip to: 76938 + /* 76422 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 76425 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 76493 + /* 76430 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 76433 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 76455 + /* 76438 */ MCD_OPC_CheckPredicate, + 23, + 180, + 109, + 0, // Skip to: 104527 + /* 76443 */ MCD_OPC_CheckField, + 16, + 6, + 56, + 173, + 109, + 0, // Skip to: 104527 + /* 76450 */ MCD_OPC_Decode, + 226, + 13, + 156, + 2, // Opcode: FCMGTv4i16rz + /* 76455 */ MCD_OPC_FilterValue, + 6, + 163, + 109, + 0, // Skip to: 104527 + /* 76460 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 76463 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 76478 + /* 76468 */ MCD_OPC_CheckPredicate, + 23, + 150, + 109, + 0, // Skip to: 104527 + /* 76473 */ MCD_OPC_Decode, + 182, + 13, + 156, + 2, // Opcode: FCMEQv4i16rz + /* 76478 */ MCD_OPC_FilterValue, + 57, + 140, + 109, + 0, // Skip to: 104527 + /* 76483 */ MCD_OPC_CheckPredicate, + 23, + 135, + 109, + 0, // Skip to: 104527 + /* 76488 */ MCD_OPC_Decode, + 199, + 18, + 156, + 2, // Opcode: FRECPEv4f16 + /* 76493 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 76561 + /* 76498 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 76501 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 76523 + /* 76506 */ MCD_OPC_CheckPredicate, + 23, + 112, + 109, + 0, // Skip to: 104527 + /* 76511 */ MCD_OPC_CheckField, + 16, + 6, + 56, + 105, + 109, + 0, // Skip to: 104527 + /* 76518 */ MCD_OPC_Decode, + 204, + 13, + 156, + 2, // Opcode: FCMGEv4i16rz + /* 76523 */ MCD_OPC_FilterValue, + 6, + 95, + 109, + 0, // Skip to: 104527 + /* 76528 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 76531 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 76546 + /* 76536 */ MCD_OPC_CheckPredicate, + 23, + 82, + 109, + 0, // Skip to: 104527 + /* 76541 */ MCD_OPC_Decode, + 251, + 13, + 156, + 2, // Opcode: FCMLEv4i16rz + /* 76546 */ MCD_OPC_FilterValue, + 57, + 72, + 109, + 0, // Skip to: 104527 + /* 76551 */ MCD_OPC_CheckPredicate, + 23, + 67, + 109, + 0, // Skip to: 104527 + /* 76556 */ MCD_OPC_Decode, + 196, + 19, + 156, + 2, // Opcode: FRSQRTEv4f16 + /* 76561 */ MCD_OPC_FilterValue, + 2, + 175, + 0, + 0, // Skip to: 76741 + /* 76566 */ MCD_OPC_ExtractField, + 10, + 3, // Inst{12-10} ... + /* 76569 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 76591 + /* 76574 */ MCD_OPC_CheckPredicate, + 21, + 44, + 109, + 0, // Skip to: 104527 + /* 76579 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 37, + 109, + 0, // Skip to: 104527 + /* 76586 */ MCD_OPC_Decode, + 240, + 16, + 179, + 2, // Opcode: FMINNMv2f64 + /* 76591 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 76629 + /* 76596 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 76599 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 76614 + /* 76604 */ MCD_OPC_CheckPredicate, + 21, + 14, + 109, + 0, // Skip to: 104527 + /* 76609 */ MCD_OPC_Decode, + 223, + 13, + 184, + 2, // Opcode: FCMGTv2i64rz + /* 76614 */ MCD_OPC_FilterValue, + 56, + 4, + 109, + 0, // Skip to: 104527 + /* 76619 */ MCD_OPC_CheckPredicate, + 23, + 255, + 108, + 0, // Skip to: 104527 + /* 76624 */ MCD_OPC_Decode, + 229, + 13, + 184, + 2, // Opcode: FCMGTv8i16rz + /* 76629 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 76651 + /* 76634 */ MCD_OPC_CheckPredicate, + 21, + 240, + 108, + 0, // Skip to: 104527 + /* 76639 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 233, + 108, + 0, // Skip to: 104527 + /* 76646 */ MCD_OPC_Decode, + 198, + 17, + 187, + 2, // Opcode: FMLSv2f64 + /* 76651 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 76673 + /* 76656 */ MCD_OPC_CheckPredicate, + 21, + 218, + 108, + 0, // Skip to: 104527 + /* 76661 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 211, + 108, + 0, // Skip to: 104527 + /* 76668 */ MCD_OPC_Decode, + 243, + 19, + 179, + 2, // Opcode: FSUBv2f64 + /* 76673 */ MCD_OPC_FilterValue, + 6, + 201, + 108, + 0, // Skip to: 104527 + /* 76678 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 76681 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 76696 + /* 76686 */ MCD_OPC_CheckPredicate, + 21, + 188, + 108, + 0, // Skip to: 104527 + /* 76691 */ MCD_OPC_Decode, + 179, + 13, + 184, + 2, // Opcode: FCMEQv2i64rz + /* 76696 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 76711 + /* 76701 */ MCD_OPC_CheckPredicate, + 21, + 173, + 108, + 0, // Skip to: 104527 + /* 76706 */ MCD_OPC_Decode, + 198, + 18, + 184, + 2, // Opcode: FRECPEv2f64 + /* 76711 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 76726 + /* 76716 */ MCD_OPC_CheckPredicate, + 23, + 158, + 108, + 0, // Skip to: 104527 + /* 76721 */ MCD_OPC_Decode, + 185, + 13, + 184, + 2, // Opcode: FCMEQv8i16rz + /* 76726 */ MCD_OPC_FilterValue, + 57, + 148, + 108, + 0, // Skip to: 104527 + /* 76731 */ MCD_OPC_CheckPredicate, + 23, + 143, + 108, + 0, // Skip to: 104527 + /* 76736 */ MCD_OPC_Decode, + 201, + 18, + 184, + 2, // Opcode: FRECPEv8f16 + /* 76741 */ MCD_OPC_FilterValue, + 3, + 133, + 108, + 0, // Skip to: 104527 + /* 76746 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 76749 */ MCD_OPC_FilterValue, + 0, + 123, + 0, + 0, // Skip to: 76877 + /* 76754 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 76757 */ MCD_OPC_FilterValue, + 32, + 33, + 0, + 0, // Skip to: 76795 + /* 76762 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 76765 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 76780 + /* 76770 */ MCD_OPC_CheckPredicate, + 21, + 104, + 108, + 0, // Skip to: 104527 + /* 76775 */ MCD_OPC_Decode, + 201, + 13, + 184, + 2, // Opcode: FCMGEv2i64rz + /* 76780 */ MCD_OPC_FilterValue, + 3, + 94, + 108, + 0, // Skip to: 104527 + /* 76785 */ MCD_OPC_CheckPredicate, + 21, + 89, + 108, + 0, // Skip to: 104527 + /* 76790 */ MCD_OPC_Decode, + 250, + 13, + 184, + 2, // Opcode: FCMLEv2i64rz + /* 76795 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 76817 + /* 76800 */ MCD_OPC_CheckPredicate, + 21, + 74, + 108, + 0, // Skip to: 104527 + /* 76805 */ MCD_OPC_CheckField, + 11, + 2, + 3, + 67, + 108, + 0, // Skip to: 104527 + /* 76812 */ MCD_OPC_Decode, + 195, + 19, + 184, + 2, // Opcode: FRSQRTEv2f64 + /* 76817 */ MCD_OPC_FilterValue, + 56, + 33, + 0, + 0, // Skip to: 76855 + /* 76822 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 76825 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 76840 + /* 76830 */ MCD_OPC_CheckPredicate, + 23, + 44, + 108, + 0, // Skip to: 104527 + /* 76835 */ MCD_OPC_Decode, + 207, + 13, + 184, + 2, // Opcode: FCMGEv8i16rz + /* 76840 */ MCD_OPC_FilterValue, + 3, + 34, + 108, + 0, // Skip to: 104527 + /* 76845 */ MCD_OPC_CheckPredicate, + 23, + 29, + 108, + 0, // Skip to: 104527 + /* 76850 */ MCD_OPC_Decode, + 253, + 13, + 184, + 2, // Opcode: FCMLEv8i16rz + /* 76855 */ MCD_OPC_FilterValue, + 57, + 19, + 108, + 0, // Skip to: 104527 + /* 76860 */ MCD_OPC_CheckPredicate, + 23, + 14, + 108, + 0, // Skip to: 104527 + /* 76865 */ MCD_OPC_CheckField, + 11, + 2, + 3, + 7, + 108, + 0, // Skip to: 104527 + /* 76872 */ MCD_OPC_Decode, + 198, + 19, + 184, + 2, // Opcode: FRSQRTEv8f16 + /* 76877 */ MCD_OPC_FilterValue, + 1, + 253, + 107, + 0, // Skip to: 104527 + /* 76882 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 76885 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 76900 + /* 76890 */ MCD_OPC_CheckPredicate, + 34, + 240, + 107, + 0, // Skip to: 104527 + /* 76895 */ MCD_OPC_Decode, + 236, + 13, + 216, + 2, // Opcode: FCMLAv2f64 + /* 76900 */ MCD_OPC_FilterValue, + 1, + 230, + 107, + 0, // Skip to: 104527 + /* 76905 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 76908 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 76923 + /* 76913 */ MCD_OPC_CheckPredicate, + 21, + 217, + 107, + 0, // Skip to: 104527 + /* 76918 */ MCD_OPC_Decode, + 219, + 16, + 179, + 2, // Opcode: FMINNMPv2f64 + /* 76923 */ MCD_OPC_FilterValue, + 2, + 207, + 107, + 0, // Skip to: 104527 + /* 76928 */ MCD_OPC_CheckPredicate, + 21, + 202, + 107, + 0, // Skip to: 104527 + /* 76933 */ MCD_OPC_Decode, + 207, + 12, + 179, + 2, // Opcode: FABDv2f64 + /* 76938 */ MCD_OPC_FilterValue, + 7, + 192, + 107, + 0, // Skip to: 104527 + /* 76943 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 76946 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 77012 + /* 76951 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 76954 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 76983 + /* 76959 */ MCD_OPC_CheckPredicate, + 26, + 171, + 107, + 0, // Skip to: 104527 + /* 76964 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 164, + 107, + 0, // Skip to: 104527 + /* 76971 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 157, + 107, + 0, // Skip to: 104527 + /* 76978 */ MCD_OPC_Decode, + 192, + 28, + 151, + 2, // Opcode: PMULLv1i64 + /* 76983 */ MCD_OPC_FilterValue, + 2, + 147, + 107, + 0, // Skip to: 104527 + /* 76988 */ MCD_OPC_CheckPredicate, + 26, + 142, + 107, + 0, // Skip to: 104527 + /* 76993 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 135, + 107, + 0, // Skip to: 104527 + /* 77000 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 128, + 107, + 0, // Skip to: 104527 + /* 77007 */ MCD_OPC_Decode, + 193, + 28, + 179, + 2, // Opcode: PMULLv2i64 + /* 77012 */ MCD_OPC_FilterValue, + 1, + 93, + 0, + 0, // Skip to: 77110 + /* 77017 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 77020 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 77042 + /* 77025 */ MCD_OPC_CheckPredicate, + 34, + 105, + 107, + 0, // Skip to: 104527 + /* 77030 */ MCD_OPC_CheckField, + 29, + 3, + 3, + 98, + 107, + 0, // Skip to: 104527 + /* 77037 */ MCD_OPC_Decode, + 154, + 13, + 217, + 2, // Opcode: FCADDv2f64 + /* 77042 */ MCD_OPC_FilterValue, + 1, + 88, + 107, + 0, // Skip to: 104527 + /* 77047 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 77050 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 77072 + /* 77055 */ MCD_OPC_CheckPredicate, + 21, + 75, + 107, + 0, // Skip to: 104527 + /* 77060 */ MCD_OPC_CheckField, + 29, + 3, + 3, + 68, + 107, + 0, // Skip to: 104527 + /* 77067 */ MCD_OPC_Decode, + 221, + 13, + 179, + 2, // Opcode: FCMGTv2f64 + /* 77072 */ MCD_OPC_FilterValue, + 1, + 58, + 107, + 0, // Skip to: 104527 + /* 77077 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 77080 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 77095 + /* 77085 */ MCD_OPC_CheckPredicate, + 21, + 45, + 107, + 0, // Skip to: 104527 + /* 77090 */ MCD_OPC_Decode, + 141, + 17, + 179, + 2, // Opcode: FMINv2f64 + /* 77095 */ MCD_OPC_FilterValue, + 3, + 35, + 107, + 0, // Skip to: 104527 + /* 77100 */ MCD_OPC_CheckPredicate, + 21, + 30, + 107, + 0, // Skip to: 104527 + /* 77105 */ MCD_OPC_Decode, + 248, + 16, + 179, + 2, // Opcode: FMINPv2f64 + /* 77110 */ MCD_OPC_FilterValue, + 2, + 24, + 1, + 0, // Skip to: 77395 + /* 77115 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 77118 */ MCD_OPC_FilterValue, + 32, + 63, + 0, + 0, // Skip to: 77186 + /* 77123 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 77126 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 77148 + /* 77131 */ MCD_OPC_CheckPredicate, + 21, + 255, + 106, + 0, // Skip to: 104527 + /* 77136 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 248, + 106, + 0, // Skip to: 104527 + /* 77143 */ MCD_OPC_Decode, + 133, + 14, + 184, + 2, // Opcode: FCMLTv2i64rz + /* 77148 */ MCD_OPC_FilterValue, + 1, + 238, + 106, + 0, // Skip to: 104527 + /* 77153 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 77156 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 77171 + /* 77161 */ MCD_OPC_CheckPredicate, + 21, + 225, + 106, + 0, // Skip to: 104527 + /* 77166 */ MCD_OPC_Decode, + 218, + 12, + 184, + 2, // Opcode: FABSv2f64 + /* 77171 */ MCD_OPC_FilterValue, + 3, + 215, + 106, + 0, // Skip to: 104527 + /* 77176 */ MCD_OPC_CheckPredicate, + 21, + 210, + 106, + 0, // Skip to: 104527 + /* 77181 */ MCD_OPC_Decode, + 166, + 18, + 184, + 2, // Opcode: FNEGv2f64 + /* 77186 */ MCD_OPC_FilterValue, + 33, + 24, + 0, + 0, // Skip to: 77215 + /* 77191 */ MCD_OPC_CheckPredicate, + 21, + 195, + 106, + 0, // Skip to: 104527 + /* 77196 */ MCD_OPC_CheckField, + 29, + 3, + 3, + 188, + 106, + 0, // Skip to: 104527 + /* 77203 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 181, + 106, + 0, // Skip to: 104527 + /* 77210 */ MCD_OPC_Decode, + 220, + 19, + 184, + 2, // Opcode: FSQRTv2f64 + /* 77215 */ MCD_OPC_FilterValue, + 56, + 123, + 0, + 0, // Skip to: 77343 + /* 77220 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 77223 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 77261 + /* 77228 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 77231 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77246 + /* 77236 */ MCD_OPC_CheckPredicate, + 23, + 150, + 106, + 0, // Skip to: 104527 + /* 77241 */ MCD_OPC_Decode, + 134, + 14, + 156, + 2, // Opcode: FCMLTv4i16rz + /* 77246 */ MCD_OPC_FilterValue, + 1, + 140, + 106, + 0, // Skip to: 104527 + /* 77251 */ MCD_OPC_CheckPredicate, + 23, + 135, + 106, + 0, // Skip to: 104527 + /* 77256 */ MCD_OPC_Decode, + 219, + 12, + 156, + 2, // Opcode: FABSv4f16 + /* 77261 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 77283 + /* 77266 */ MCD_OPC_CheckPredicate, + 23, + 120, + 106, + 0, // Skip to: 104527 + /* 77271 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 113, + 106, + 0, // Skip to: 104527 + /* 77278 */ MCD_OPC_Decode, + 167, + 18, + 156, + 2, // Opcode: FNEGv4f16 + /* 77283 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 77321 + /* 77288 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 77291 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77306 + /* 77296 */ MCD_OPC_CheckPredicate, + 23, + 90, + 106, + 0, // Skip to: 104527 + /* 77301 */ MCD_OPC_Decode, + 136, + 14, + 184, + 2, // Opcode: FCMLTv8i16rz + /* 77306 */ MCD_OPC_FilterValue, + 1, + 80, + 106, + 0, // Skip to: 104527 + /* 77311 */ MCD_OPC_CheckPredicate, + 23, + 75, + 106, + 0, // Skip to: 104527 + /* 77316 */ MCD_OPC_Decode, + 221, + 12, + 184, + 2, // Opcode: FABSv8f16 + /* 77321 */ MCD_OPC_FilterValue, + 3, + 65, + 106, + 0, // Skip to: 104527 + /* 77326 */ MCD_OPC_CheckPredicate, + 23, + 60, + 106, + 0, // Skip to: 104527 + /* 77331 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 53, + 106, + 0, // Skip to: 104527 + /* 77338 */ MCD_OPC_Decode, + 169, + 18, + 184, + 2, // Opcode: FNEGv8f16 + /* 77343 */ MCD_OPC_FilterValue, + 57, + 43, + 106, + 0, // Skip to: 104527 + /* 77348 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 77351 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 77373 + /* 77356 */ MCD_OPC_CheckPredicate, + 23, + 30, + 106, + 0, // Skip to: 104527 + /* 77361 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 23, + 106, + 0, // Skip to: 104527 + /* 77368 */ MCD_OPC_Decode, + 221, + 19, + 156, + 2, // Opcode: FSQRTv4f16 + /* 77373 */ MCD_OPC_FilterValue, + 3, + 13, + 106, + 0, // Skip to: 104527 + /* 77378 */ MCD_OPC_CheckPredicate, + 23, + 8, + 106, + 0, // Skip to: 104527 + /* 77383 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 1, + 106, + 0, // Skip to: 104527 + /* 77390 */ MCD_OPC_Decode, + 223, + 19, + 184, + 2, // Opcode: FSQRTv8f16 + /* 77395 */ MCD_OPC_FilterValue, + 3, + 247, + 105, + 0, // Skip to: 104527 + /* 77400 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 77403 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 77432 + /* 77408 */ MCD_OPC_CheckPredicate, + 30, + 234, + 105, + 0, // Skip to: 104527 + /* 77413 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 227, + 105, + 0, // Skip to: 104527 + /* 77420 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 220, + 105, + 0, // Skip to: 104527 + /* 77427 */ MCD_OPC_Decode, + 203, + 8, + 187, + 2, // Opcode: BFMLALB + /* 77432 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 77461 + /* 77437 */ MCD_OPC_CheckPredicate, + 21, + 205, + 105, + 0, // Skip to: 104527 + /* 77442 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 198, + 105, + 0, // Skip to: 104527 + /* 77449 */ MCD_OPC_CheckField, + 12, + 1, + 1, + 191, + 105, + 0, // Skip to: 104527 + /* 77456 */ MCD_OPC_Decode, + 206, + 19, + 179, + 2, // Opcode: FRSQRTSv2f64 + /* 77461 */ MCD_OPC_FilterValue, + 3, + 181, + 105, + 0, // Skip to: 104527 + /* 77466 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 77469 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 77491 + /* 77474 */ MCD_OPC_CheckPredicate, + 21, + 168, + 105, + 0, // Skip to: 104527 + /* 77479 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 161, + 105, + 0, // Skip to: 104527 + /* 77486 */ MCD_OPC_Decode, + 240, + 12, + 179, + 2, // Opcode: FACGTv2f64 + /* 77491 */ MCD_OPC_FilterValue, + 1, + 151, + 105, + 0, // Skip to: 104527 + /* 77496 */ MCD_OPC_CheckPredicate, + 30, + 146, + 105, + 0, // Skip to: 104527 + /* 77501 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 139, + 105, + 0, // Skip to: 104527 + /* 77508 */ MCD_OPC_Decode, + 205, + 8, + 187, + 2, // Opcode: BFMLALT + /* 77513 */ MCD_OPC_FilterValue, + 12, + 124, + 17, + 0, // Skip to: 81994 + /* 77518 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 77521 */ MCD_OPC_FilterValue, + 0, + 81, + 4, + 0, // Skip to: 78631 + /* 77526 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 77529 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 77597 + /* 77534 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 77537 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 77552 + /* 77542 */ MCD_OPC_CheckPredicate, + 23, + 100, + 105, + 0, // Skip to: 104527 + /* 77547 */ MCD_OPC_Decode, + 172, + 17, + 220, + 2, // Opcode: FMLAv4i16_indexed + /* 77552 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 77567 + /* 77557 */ MCD_OPC_CheckPredicate, + 23, + 85, + 105, + 0, // Skip to: 104527 + /* 77562 */ MCD_OPC_Decode, + 203, + 17, + 220, + 2, // Opcode: FMLSv4i16_indexed + /* 77567 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 77582 + /* 77572 */ MCD_OPC_CheckPredicate, + 23, + 70, + 105, + 0, // Skip to: 104527 + /* 77577 */ MCD_OPC_Decode, + 155, + 18, + 221, + 2, // Opcode: FMULv4i16_indexed + /* 77582 */ MCD_OPC_FilterValue, + 15, + 60, + 105, + 0, // Skip to: 104527 + /* 77587 */ MCD_OPC_CheckPredicate, + 33, + 55, + 105, + 0, // Skip to: 104527 + /* 77592 */ MCD_OPC_Decode, + 226, + 40, + 222, + 2, // Opcode: SUDOTlanev8i8 + /* 77597 */ MCD_OPC_FilterValue, + 1, + 45, + 105, + 0, // Skip to: 104527 + /* 77602 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 77605 */ MCD_OPC_FilterValue, + 0, + 41, + 3, + 0, // Skip to: 78419 + /* 77610 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 77613 */ MCD_OPC_FilterValue, + 0, + 143, + 1, + 0, // Skip to: 78017 + /* 77618 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 77621 */ MCD_OPC_FilterValue, + 0, + 148, + 0, + 0, // Skip to: 77774 + /* 77626 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 77629 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 77736 + /* 77634 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 77637 */ MCD_OPC_FilterValue, + 0, + 56, + 0, + 0, // Skip to: 77698 + /* 77642 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 77645 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77660 + /* 77650 */ MCD_OPC_CheckPredicate, + 21, + 248, + 104, + 0, // Skip to: 104527 + /* 77655 */ MCD_OPC_Decode, + 179, + 27, + 223, + 2, // Opcode: MOVIv2i32 + /* 77660 */ MCD_OPC_FilterValue, + 1, + 238, + 104, + 0, // Skip to: 104527 + /* 77665 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 77668 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77683 + /* 77673 */ MCD_OPC_CheckPredicate, + 21, + 225, + 104, + 0, // Skip to: 104527 + /* 77678 */ MCD_OPC_Decode, + 138, + 37, + 224, + 2, // Opcode: SSHRv8i8_shift + /* 77683 */ MCD_OPC_FilterValue, + 1, + 215, + 104, + 0, // Skip to: 104527 + /* 77688 */ MCD_OPC_CheckPredicate, + 21, + 210, + 104, + 0, // Skip to: 104527 + /* 77693 */ MCD_OPC_Decode, + 226, + 36, + 224, + 2, // Opcode: SRSHRv8i8_shift + /* 77698 */ MCD_OPC_FilterValue, + 1, + 200, + 104, + 0, // Skip to: 104527 + /* 77703 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 77706 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77721 + /* 77711 */ MCD_OPC_CheckPredicate, + 21, + 187, + 104, + 0, // Skip to: 104527 + /* 77716 */ MCD_OPC_Decode, + 135, + 37, + 225, + 2, // Opcode: SSHRv4i16_shift + /* 77721 */ MCD_OPC_FilterValue, + 1, + 177, + 104, + 0, // Skip to: 104527 + /* 77726 */ MCD_OPC_CheckPredicate, + 21, + 172, + 104, + 0, // Skip to: 104527 + /* 77731 */ MCD_OPC_Decode, + 223, + 36, + 225, + 2, // Opcode: SRSHRv4i16_shift + /* 77736 */ MCD_OPC_FilterValue, + 1, + 162, + 104, + 0, // Skip to: 104527 + /* 77741 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 77744 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77759 + /* 77749 */ MCD_OPC_CheckPredicate, + 21, + 149, + 104, + 0, // Skip to: 104527 + /* 77754 */ MCD_OPC_Decode, + 133, + 37, + 226, + 2, // Opcode: SSHRv2i32_shift + /* 77759 */ MCD_OPC_FilterValue, + 1, + 139, + 104, + 0, // Skip to: 104527 + /* 77764 */ MCD_OPC_CheckPredicate, + 21, + 134, + 104, + 0, // Skip to: 104527 + /* 77769 */ MCD_OPC_Decode, + 221, + 36, + 226, + 2, // Opcode: SRSHRv2i32_shift + /* 77774 */ MCD_OPC_FilterValue, + 1, + 124, + 104, + 0, // Skip to: 104527 + /* 77779 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 77782 */ MCD_OPC_FilterValue, + 0, + 162, + 0, + 0, // Skip to: 77949 + /* 77787 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 77790 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 77881 + /* 77795 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 77798 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77813 + /* 77803 */ MCD_OPC_CheckPredicate, + 21, + 95, + 104, + 0, // Skip to: 104527 + /* 77808 */ MCD_OPC_Decode, + 159, + 28, + 227, + 2, // Opcode: ORRv2i32 + /* 77813 */ MCD_OPC_FilterValue, + 1, + 85, + 104, + 0, // Skip to: 104527 + /* 77818 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 77821 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77836 + /* 77826 */ MCD_OPC_CheckPredicate, + 21, + 72, + 104, + 0, // Skip to: 104527 + /* 77831 */ MCD_OPC_Decode, + 150, + 37, + 228, + 2, // Opcode: SSRAv8i8_shift + /* 77836 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 77851 + /* 77841 */ MCD_OPC_CheckPredicate, + 21, + 57, + 104, + 0, // Skip to: 104527 + /* 77846 */ MCD_OPC_Decode, + 238, + 36, + 228, + 2, // Opcode: SRSRAv8i8_shift + /* 77851 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 77866 + /* 77856 */ MCD_OPC_CheckPredicate, + 21, + 42, + 104, + 0, // Skip to: 104527 + /* 77861 */ MCD_OPC_Decode, + 165, + 31, + 229, + 2, // Opcode: SHLv8i8_shift + /* 77866 */ MCD_OPC_FilterValue, + 3, + 32, + 104, + 0, // Skip to: 104527 + /* 77871 */ MCD_OPC_CheckPredicate, + 21, + 27, + 104, + 0, // Skip to: 104527 + /* 77876 */ MCD_OPC_Decode, + 217, + 35, + 229, + 2, // Opcode: SQSHLv8i8_shift + /* 77881 */ MCD_OPC_FilterValue, + 1, + 17, + 104, + 0, // Skip to: 104527 + /* 77886 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 77889 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77904 + /* 77894 */ MCD_OPC_CheckPredicate, + 21, + 4, + 104, + 0, // Skip to: 104527 + /* 77899 */ MCD_OPC_Decode, + 147, + 37, + 230, + 2, // Opcode: SSRAv4i16_shift + /* 77904 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 77919 + /* 77909 */ MCD_OPC_CheckPredicate, + 21, + 245, + 103, + 0, // Skip to: 104527 + /* 77914 */ MCD_OPC_Decode, + 235, + 36, + 230, + 2, // Opcode: SRSRAv4i16_shift + /* 77919 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 77934 + /* 77924 */ MCD_OPC_CheckPredicate, + 21, + 230, + 103, + 0, // Skip to: 104527 + /* 77929 */ MCD_OPC_Decode, + 162, + 31, + 231, + 2, // Opcode: SHLv4i16_shift + /* 77934 */ MCD_OPC_FilterValue, + 3, + 220, + 103, + 0, // Skip to: 104527 + /* 77939 */ MCD_OPC_CheckPredicate, + 21, + 215, + 103, + 0, // Skip to: 104527 + /* 77944 */ MCD_OPC_Decode, + 211, + 35, + 231, + 2, // Opcode: SQSHLv4i16_shift + /* 77949 */ MCD_OPC_FilterValue, + 1, + 205, + 103, + 0, // Skip to: 104527 + /* 77954 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 77957 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 77972 + /* 77962 */ MCD_OPC_CheckPredicate, + 21, + 192, + 103, + 0, // Skip to: 104527 + /* 77967 */ MCD_OPC_Decode, + 145, + 37, + 232, + 2, // Opcode: SSRAv2i32_shift + /* 77972 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 77987 + /* 77977 */ MCD_OPC_CheckPredicate, + 21, + 177, + 103, + 0, // Skip to: 104527 + /* 77982 */ MCD_OPC_Decode, + 233, + 36, + 232, + 2, // Opcode: SRSRAv2i32_shift + /* 77987 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 78002 + /* 77992 */ MCD_OPC_CheckPredicate, + 21, + 162, + 103, + 0, // Skip to: 104527 + /* 77997 */ MCD_OPC_Decode, + 160, + 31, + 233, + 2, // Opcode: SHLv2i32_shift + /* 78002 */ MCD_OPC_FilterValue, + 3, + 152, + 103, + 0, // Skip to: 104527 + /* 78007 */ MCD_OPC_CheckPredicate, + 21, + 147, + 103, + 0, // Skip to: 104527 + /* 78012 */ MCD_OPC_Decode, + 207, + 35, + 233, + 2, // Opcode: SQSHLv2i32_shift + /* 78017 */ MCD_OPC_FilterValue, + 1, + 137, + 103, + 0, // Skip to: 104527 + /* 78022 */ MCD_OPC_ExtractField, + 14, + 1, // Inst{14} ... + /* 78025 */ MCD_OPC_FilterValue, + 0, + 5, + 1, + 0, // Skip to: 78291 + /* 78030 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 78033 */ MCD_OPC_FilterValue, + 0, + 148, + 0, + 0, // Skip to: 78186 + /* 78038 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 78041 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 78148 + /* 78046 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 78049 */ MCD_OPC_FilterValue, + 0, + 56, + 0, + 0, // Skip to: 78110 + /* 78054 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 78057 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78072 + /* 78062 */ MCD_OPC_CheckPredicate, + 21, + 92, + 103, + 0, // Skip to: 104527 + /* 78067 */ MCD_OPC_Decode, + 181, + 27, + 223, + 2, // Opcode: MOVIv4i16 + /* 78072 */ MCD_OPC_FilterValue, + 1, + 82, + 103, + 0, // Skip to: 104527 + /* 78077 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 78080 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78095 + /* 78085 */ MCD_OPC_CheckPredicate, + 21, + 69, + 103, + 0, // Skip to: 104527 + /* 78090 */ MCD_OPC_Decode, + 177, + 31, + 234, + 2, // Opcode: SHRNv8i8_shift + /* 78095 */ MCD_OPC_FilterValue, + 1, + 59, + 103, + 0, // Skip to: 104527 + /* 78100 */ MCD_OPC_CheckPredicate, + 21, + 54, + 103, + 0, // Skip to: 104527 + /* 78105 */ MCD_OPC_Decode, + 250, + 36, + 235, + 2, // Opcode: SSHLLv8i8_shift + /* 78110 */ MCD_OPC_FilterValue, + 1, + 44, + 103, + 0, // Skip to: 104527 + /* 78115 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 78118 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78133 + /* 78123 */ MCD_OPC_CheckPredicate, + 21, + 31, + 103, + 0, // Skip to: 104527 + /* 78128 */ MCD_OPC_Decode, + 174, + 31, + 236, + 2, // Opcode: SHRNv4i16_shift + /* 78133 */ MCD_OPC_FilterValue, + 1, + 21, + 103, + 0, // Skip to: 104527 + /* 78138 */ MCD_OPC_CheckPredicate, + 21, + 16, + 103, + 0, // Skip to: 104527 + /* 78143 */ MCD_OPC_Decode, + 247, + 36, + 237, + 2, // Opcode: SSHLLv4i16_shift + /* 78148 */ MCD_OPC_FilterValue, + 1, + 6, + 103, + 0, // Skip to: 104527 + /* 78153 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 78156 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78171 + /* 78161 */ MCD_OPC_CheckPredicate, + 21, + 249, + 102, + 0, // Skip to: 104527 + /* 78166 */ MCD_OPC_Decode, + 173, + 31, + 238, + 2, // Opcode: SHRNv2i32_shift + /* 78171 */ MCD_OPC_FilterValue, + 1, + 239, + 102, + 0, // Skip to: 104527 + /* 78176 */ MCD_OPC_CheckPredicate, + 21, + 234, + 102, + 0, // Skip to: 104527 + /* 78181 */ MCD_OPC_Decode, + 246, + 36, + 239, + 2, // Opcode: SSHLLv2i32_shift + /* 78186 */ MCD_OPC_FilterValue, + 1, + 224, + 102, + 0, // Skip to: 104527 + /* 78191 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 78194 */ MCD_OPC_FilterValue, + 0, + 70, + 0, + 0, // Skip to: 78269 + /* 78199 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 78202 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 78247 + /* 78207 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 78210 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78225 + /* 78215 */ MCD_OPC_CheckPredicate, + 21, + 195, + 102, + 0, // Skip to: 104527 + /* 78220 */ MCD_OPC_Decode, + 160, + 28, + 227, + 2, // Opcode: ORRv4i16 + /* 78225 */ MCD_OPC_FilterValue, + 1, + 185, + 102, + 0, // Skip to: 104527 + /* 78230 */ MCD_OPC_CheckPredicate, + 21, + 180, + 102, + 0, // Skip to: 104527 + /* 78235 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 173, + 102, + 0, // Skip to: 104527 + /* 78242 */ MCD_OPC_Decode, + 232, + 35, + 234, + 2, // Opcode: SQSHRNv8i8_shift + /* 78247 */ MCD_OPC_FilterValue, + 1, + 163, + 102, + 0, // Skip to: 104527 + /* 78252 */ MCD_OPC_CheckPredicate, + 21, + 158, + 102, + 0, // Skip to: 104527 + /* 78257 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 151, + 102, + 0, // Skip to: 104527 + /* 78264 */ MCD_OPC_Decode, + 229, + 35, + 236, + 2, // Opcode: SQSHRNv4i16_shift + /* 78269 */ MCD_OPC_FilterValue, + 1, + 141, + 102, + 0, // Skip to: 104527 + /* 78274 */ MCD_OPC_CheckPredicate, + 21, + 136, + 102, + 0, // Skip to: 104527 + /* 78279 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 129, + 102, + 0, // Skip to: 104527 + /* 78286 */ MCD_OPC_Decode, + 228, + 35, + 238, + 2, // Opcode: SQSHRNv2i32_shift + /* 78291 */ MCD_OPC_FilterValue, + 1, + 119, + 102, + 0, // Skip to: 104527 + /* 78296 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 78299 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 78321 + /* 78304 */ MCD_OPC_CheckPredicate, + 21, + 106, + 102, + 0, // Skip to: 104527 + /* 78309 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 99, + 102, + 0, // Skip to: 104527 + /* 78316 */ MCD_OPC_Decode, + 180, + 27, + 223, + 2, // Opcode: MOVIv2s_msl + /* 78321 */ MCD_OPC_FilterValue, + 1, + 89, + 102, + 0, // Skip to: 104527 + /* 78326 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 78329 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 78397 + /* 78334 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 78337 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 78382 + /* 78342 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 78345 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 78367 + /* 78350 */ MCD_OPC_CheckPredicate, + 21, + 60, + 102, + 0, // Skip to: 104527 + /* 78355 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 53, + 102, + 0, // Skip to: 104527 + /* 78362 */ MCD_OPC_Decode, + 184, + 27, + 223, + 2, // Opcode: MOVIv8b_ns + /* 78367 */ MCD_OPC_FilterValue, + 1, + 43, + 102, + 0, // Skip to: 104527 + /* 78372 */ MCD_OPC_CheckPredicate, + 23, + 38, + 102, + 0, // Skip to: 104527 + /* 78377 */ MCD_OPC_Decode, + 230, + 30, + 225, + 2, // Opcode: SCVTFv4i16_shift + /* 78382 */ MCD_OPC_FilterValue, + 1, + 28, + 102, + 0, // Skip to: 104527 + /* 78387 */ MCD_OPC_CheckPredicate, + 21, + 23, + 102, + 0, // Skip to: 104527 + /* 78392 */ MCD_OPC_Decode, + 226, + 30, + 226, + 2, // Opcode: SCVTFv2i32_shift + /* 78397 */ MCD_OPC_FilterValue, + 1, + 13, + 102, + 0, // Skip to: 104527 + /* 78402 */ MCD_OPC_CheckPredicate, + 21, + 8, + 102, + 0, // Skip to: 104527 + /* 78407 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 1, + 102, + 0, // Skip to: 104527 + /* 78414 */ MCD_OPC_Decode, + 229, + 17, + 223, + 2, // Opcode: FMOVv2f32_ns + /* 78419 */ MCD_OPC_FilterValue, + 1, + 247, + 101, + 0, // Skip to: 104527 + /* 78424 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 78427 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 78495 + /* 78432 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 78435 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 78480 + /* 78440 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 78443 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 78465 + /* 78448 */ MCD_OPC_CheckPredicate, + 21, + 218, + 101, + 0, // Skip to: 104527 + /* 78453 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 211, + 101, + 0, // Skip to: 104527 + /* 78460 */ MCD_OPC_Decode, + 205, + 29, + 234, + 2, // Opcode: RSHRNv8i8_shift + /* 78465 */ MCD_OPC_FilterValue, + 1, + 201, + 101, + 0, // Skip to: 104527 + /* 78470 */ MCD_OPC_CheckPredicate, + 21, + 196, + 101, + 0, // Skip to: 104527 + /* 78475 */ MCD_OPC_Decode, + 202, + 29, + 236, + 2, // Opcode: RSHRNv4i16_shift + /* 78480 */ MCD_OPC_FilterValue, + 1, + 186, + 101, + 0, // Skip to: 104527 + /* 78485 */ MCD_OPC_CheckPredicate, + 21, + 181, + 101, + 0, // Skip to: 104527 + /* 78490 */ MCD_OPC_Decode, + 201, + 29, + 238, + 2, // Opcode: RSHRNv2i32_shift + /* 78495 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 78563 + /* 78500 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 78503 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 78548 + /* 78508 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 78511 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 78533 + /* 78516 */ MCD_OPC_CheckPredicate, + 21, + 150, + 101, + 0, // Skip to: 104527 + /* 78521 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 143, + 101, + 0, // Skip to: 104527 + /* 78528 */ MCD_OPC_Decode, + 153, + 35, + 234, + 2, // Opcode: SQRSHRNv8i8_shift + /* 78533 */ MCD_OPC_FilterValue, + 1, + 133, + 101, + 0, // Skip to: 104527 + /* 78538 */ MCD_OPC_CheckPredicate, + 21, + 128, + 101, + 0, // Skip to: 104527 + /* 78543 */ MCD_OPC_Decode, + 150, + 35, + 236, + 2, // Opcode: SQRSHRNv4i16_shift + /* 78548 */ MCD_OPC_FilterValue, + 1, + 118, + 101, + 0, // Skip to: 104527 + /* 78553 */ MCD_OPC_CheckPredicate, + 21, + 113, + 101, + 0, // Skip to: 104527 + /* 78558 */ MCD_OPC_Decode, + 149, + 35, + 238, + 2, // Opcode: SQRSHRNv2i32_shift + /* 78563 */ MCD_OPC_FilterValue, + 15, + 103, + 101, + 0, // Skip to: 104527 + /* 78568 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 78571 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 78616 + /* 78576 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 78579 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 78601 + /* 78584 */ MCD_OPC_CheckPredicate, + 23, + 82, + 101, + 0, // Skip to: 104527 + /* 78589 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 75, + 101, + 0, // Skip to: 104527 + /* 78596 */ MCD_OPC_Decode, + 231, + 17, + 223, + 2, // Opcode: FMOVv4f16_ns + /* 78601 */ MCD_OPC_FilterValue, + 1, + 65, + 101, + 0, // Skip to: 104527 + /* 78606 */ MCD_OPC_CheckPredicate, + 23, + 60, + 101, + 0, // Skip to: 104527 + /* 78611 */ MCD_OPC_Decode, + 202, + 15, + 225, + 2, // Opcode: FCVTZSv4i16_shift + /* 78616 */ MCD_OPC_FilterValue, + 1, + 50, + 101, + 0, // Skip to: 104527 + /* 78621 */ MCD_OPC_CheckPredicate, + 21, + 45, + 101, + 0, // Skip to: 104527 + /* 78626 */ MCD_OPC_Decode, + 198, + 15, + 226, + 2, // Opcode: FCVTZSv2i32_shift + /* 78631 */ MCD_OPC_FilterValue, + 1, + 93, + 4, + 0, // Skip to: 79753 + /* 78636 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 78639 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 78661 + /* 78644 */ MCD_OPC_CheckPredicate, + 23, + 22, + 101, + 0, // Skip to: 104527 + /* 78649 */ MCD_OPC_CheckField, + 12, + 4, + 9, + 15, + 101, + 0, // Skip to: 104527 + /* 78656 */ MCD_OPC_Decode, + 130, + 18, + 221, + 2, // Opcode: FMULXv4i16_indexed + /* 78661 */ MCD_OPC_FilterValue, + 1, + 5, + 101, + 0, // Skip to: 104527 + /* 78666 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 78669 */ MCD_OPC_FilterValue, + 0, + 122, + 3, + 0, // Skip to: 79564 + /* 78674 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 78677 */ MCD_OPC_FilterValue, + 0, + 233, + 1, + 0, // Skip to: 79171 + /* 78682 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 78685 */ MCD_OPC_FilterValue, + 0, + 238, + 0, + 0, // Skip to: 78928 + /* 78690 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 78693 */ MCD_OPC_FilterValue, + 0, + 162, + 0, + 0, // Skip to: 78860 + /* 78698 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 78701 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 78792 + /* 78706 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 78709 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78724 + /* 78714 */ MCD_OPC_CheckPredicate, + 21, + 208, + 100, + 0, // Skip to: 104527 + /* 78719 */ MCD_OPC_Decode, + 237, + 27, + 223, + 2, // Opcode: MVNIv2i32 + /* 78724 */ MCD_OPC_FilterValue, + 1, + 198, + 100, + 0, // Skip to: 104527 + /* 78729 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 78732 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78747 + /* 78737 */ MCD_OPC_CheckPredicate, + 21, + 185, + 100, + 0, // Skip to: 104527 + /* 78742 */ MCD_OPC_Decode, + 182, + 46, + 224, + 2, // Opcode: USHRv8i8_shift + /* 78747 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 78762 + /* 78752 */ MCD_OPC_CheckPredicate, + 21, + 170, + 100, + 0, // Skip to: 104527 + /* 78757 */ MCD_OPC_Decode, + 133, + 46, + 224, + 2, // Opcode: URSHRv8i8_shift + /* 78762 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 78777 + /* 78767 */ MCD_OPC_CheckPredicate, + 21, + 155, + 100, + 0, // Skip to: 104527 + /* 78772 */ MCD_OPC_Decode, + 198, + 36, + 228, + 2, // Opcode: SRIv8i8_shift + /* 78777 */ MCD_OPC_FilterValue, + 3, + 145, + 100, + 0, // Skip to: 104527 + /* 78782 */ MCD_OPC_CheckPredicate, + 21, + 140, + 100, + 0, // Skip to: 104527 + /* 78787 */ MCD_OPC_Decode, + 187, + 35, + 229, + 2, // Opcode: SQSHLUv8i8_shift + /* 78792 */ MCD_OPC_FilterValue, + 1, + 130, + 100, + 0, // Skip to: 104527 + /* 78797 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 78800 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78815 + /* 78805 */ MCD_OPC_CheckPredicate, + 21, + 117, + 100, + 0, // Skip to: 104527 + /* 78810 */ MCD_OPC_Decode, + 179, + 46, + 225, + 2, // Opcode: USHRv4i16_shift + /* 78815 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 78830 + /* 78820 */ MCD_OPC_CheckPredicate, + 21, + 102, + 100, + 0, // Skip to: 104527 + /* 78825 */ MCD_OPC_Decode, + 130, + 46, + 225, + 2, // Opcode: URSHRv4i16_shift + /* 78830 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 78845 + /* 78835 */ MCD_OPC_CheckPredicate, + 21, + 87, + 100, + 0, // Skip to: 104527 + /* 78840 */ MCD_OPC_Decode, + 195, + 36, + 230, + 2, // Opcode: SRIv4i16_shift + /* 78845 */ MCD_OPC_FilterValue, + 3, + 77, + 100, + 0, // Skip to: 104527 + /* 78850 */ MCD_OPC_CheckPredicate, + 21, + 72, + 100, + 0, // Skip to: 104527 + /* 78855 */ MCD_OPC_Decode, + 184, + 35, + 231, + 2, // Opcode: SQSHLUv4i16_shift + /* 78860 */ MCD_OPC_FilterValue, + 1, + 62, + 100, + 0, // Skip to: 104527 + /* 78865 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 78868 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78883 + /* 78873 */ MCD_OPC_CheckPredicate, + 21, + 49, + 100, + 0, // Skip to: 104527 + /* 78878 */ MCD_OPC_Decode, + 177, + 46, + 226, + 2, // Opcode: USHRv2i32_shift + /* 78883 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 78898 + /* 78888 */ MCD_OPC_CheckPredicate, + 21, + 34, + 100, + 0, // Skip to: 104527 + /* 78893 */ MCD_OPC_Decode, + 128, + 46, + 226, + 2, // Opcode: URSHRv2i32_shift + /* 78898 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 78913 + /* 78903 */ MCD_OPC_CheckPredicate, + 21, + 19, + 100, + 0, // Skip to: 104527 + /* 78908 */ MCD_OPC_Decode, + 193, + 36, + 232, + 2, // Opcode: SRIv2i32_shift + /* 78913 */ MCD_OPC_FilterValue, + 3, + 9, + 100, + 0, // Skip to: 104527 + /* 78918 */ MCD_OPC_CheckPredicate, + 21, + 4, + 100, + 0, // Skip to: 104527 + /* 78923 */ MCD_OPC_Decode, + 182, + 35, + 233, + 2, // Opcode: SQSHLUv2i32_shift + /* 78928 */ MCD_OPC_FilterValue, + 1, + 250, + 99, + 0, // Skip to: 104527 + /* 78933 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 78936 */ MCD_OPC_FilterValue, + 0, + 162, + 0, + 0, // Skip to: 79103 + /* 78941 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 78944 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 79035 + /* 78949 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 78952 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78967 + /* 78957 */ MCD_OPC_CheckPredicate, + 21, + 221, + 99, + 0, // Skip to: 104527 + /* 78962 */ MCD_OPC_Decode, + 231, + 8, + 227, + 2, // Opcode: BICv2i32 + /* 78967 */ MCD_OPC_FilterValue, + 1, + 211, + 99, + 0, // Skip to: 104527 + /* 78972 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 78975 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 78990 + /* 78980 */ MCD_OPC_CheckPredicate, + 21, + 198, + 99, + 0, // Skip to: 104527 + /* 78985 */ MCD_OPC_Decode, + 215, + 46, + 228, + 2, // Opcode: USRAv8i8_shift + /* 78990 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 79005 + /* 78995 */ MCD_OPC_CheckPredicate, + 21, + 183, + 99, + 0, // Skip to: 104527 + /* 79000 */ MCD_OPC_Decode, + 148, + 46, + 228, + 2, // Opcode: URSRAv8i8_shift + /* 79005 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 79020 + /* 79010 */ MCD_OPC_CheckPredicate, + 21, + 168, + 99, + 0, // Skip to: 104527 + /* 79015 */ MCD_OPC_Decode, + 203, + 31, + 240, + 2, // Opcode: SLIv8i8_shift + /* 79020 */ MCD_OPC_FilterValue, + 3, + 158, + 99, + 0, // Skip to: 104527 + /* 79025 */ MCD_OPC_CheckPredicate, + 21, + 153, + 99, + 0, // Skip to: 104527 + /* 79030 */ MCD_OPC_Decode, + 163, + 45, + 229, + 2, // Opcode: UQSHLv8i8_shift + /* 79035 */ MCD_OPC_FilterValue, + 1, + 143, + 99, + 0, // Skip to: 104527 + /* 79040 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 79043 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79058 + /* 79048 */ MCD_OPC_CheckPredicate, + 21, + 130, + 99, + 0, // Skip to: 104527 + /* 79053 */ MCD_OPC_Decode, + 212, + 46, + 230, + 2, // Opcode: USRAv4i16_shift + /* 79058 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 79073 + /* 79063 */ MCD_OPC_CheckPredicate, + 21, + 115, + 99, + 0, // Skip to: 104527 + /* 79068 */ MCD_OPC_Decode, + 145, + 46, + 230, + 2, // Opcode: URSRAv4i16_shift + /* 79073 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 79088 + /* 79078 */ MCD_OPC_CheckPredicate, + 21, + 100, + 99, + 0, // Skip to: 104527 + /* 79083 */ MCD_OPC_Decode, + 200, + 31, + 241, + 2, // Opcode: SLIv4i16_shift + /* 79088 */ MCD_OPC_FilterValue, + 3, + 90, + 99, + 0, // Skip to: 104527 + /* 79093 */ MCD_OPC_CheckPredicate, + 21, + 85, + 99, + 0, // Skip to: 104527 + /* 79098 */ MCD_OPC_Decode, + 157, + 45, + 231, + 2, // Opcode: UQSHLv4i16_shift + /* 79103 */ MCD_OPC_FilterValue, + 1, + 75, + 99, + 0, // Skip to: 104527 + /* 79108 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 79111 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79126 + /* 79116 */ MCD_OPC_CheckPredicate, + 21, + 62, + 99, + 0, // Skip to: 104527 + /* 79121 */ MCD_OPC_Decode, + 210, + 46, + 232, + 2, // Opcode: USRAv2i32_shift + /* 79126 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 79141 + /* 79131 */ MCD_OPC_CheckPredicate, + 21, + 47, + 99, + 0, // Skip to: 104527 + /* 79136 */ MCD_OPC_Decode, + 143, + 46, + 232, + 2, // Opcode: URSRAv2i32_shift + /* 79141 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 79156 + /* 79146 */ MCD_OPC_CheckPredicate, + 21, + 32, + 99, + 0, // Skip to: 104527 + /* 79151 */ MCD_OPC_Decode, + 198, + 31, + 242, + 2, // Opcode: SLIv2i32_shift + /* 79156 */ MCD_OPC_FilterValue, + 3, + 22, + 99, + 0, // Skip to: 104527 + /* 79161 */ MCD_OPC_CheckPredicate, + 21, + 17, + 99, + 0, // Skip to: 104527 + /* 79166 */ MCD_OPC_Decode, + 153, + 45, + 233, + 2, // Opcode: UQSHLv2i32_shift + /* 79171 */ MCD_OPC_FilterValue, + 1, + 7, + 99, + 0, // Skip to: 104527 + /* 79176 */ MCD_OPC_ExtractField, + 14, + 1, // Inst{14} ... + /* 79179 */ MCD_OPC_FilterValue, + 0, + 5, + 1, + 0, // Skip to: 79445 + /* 79184 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 79187 */ MCD_OPC_FilterValue, + 0, + 148, + 0, + 0, // Skip to: 79340 + /* 79192 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 79195 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 79302 + /* 79200 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 79203 */ MCD_OPC_FilterValue, + 0, + 56, + 0, + 0, // Skip to: 79264 + /* 79208 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 79211 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79226 + /* 79216 */ MCD_OPC_CheckPredicate, + 21, + 218, + 98, + 0, // Skip to: 104527 + /* 79221 */ MCD_OPC_Decode, + 239, + 27, + 223, + 2, // Opcode: MVNIv4i16 + /* 79226 */ MCD_OPC_FilterValue, + 1, + 208, + 98, + 0, // Skip to: 104527 + /* 79231 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 79234 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79249 + /* 79239 */ MCD_OPC_CheckPredicate, + 21, + 195, + 98, + 0, // Skip to: 104527 + /* 79244 */ MCD_OPC_Decode, + 247, + 35, + 234, + 2, // Opcode: SQSHRUNv8i8_shift + /* 79249 */ MCD_OPC_FilterValue, + 1, + 185, + 98, + 0, // Skip to: 104527 + /* 79254 */ MCD_OPC_CheckPredicate, + 21, + 180, + 98, + 0, // Skip to: 104527 + /* 79259 */ MCD_OPC_Decode, + 166, + 46, + 235, + 2, // Opcode: USHLLv8i8_shift + /* 79264 */ MCD_OPC_FilterValue, + 1, + 170, + 98, + 0, // Skip to: 104527 + /* 79269 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 79272 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79287 + /* 79277 */ MCD_OPC_CheckPredicate, + 21, + 157, + 98, + 0, // Skip to: 104527 + /* 79282 */ MCD_OPC_Decode, + 244, + 35, + 236, + 2, // Opcode: SQSHRUNv4i16_shift + /* 79287 */ MCD_OPC_FilterValue, + 1, + 147, + 98, + 0, // Skip to: 104527 + /* 79292 */ MCD_OPC_CheckPredicate, + 21, + 142, + 98, + 0, // Skip to: 104527 + /* 79297 */ MCD_OPC_Decode, + 163, + 46, + 237, + 2, // Opcode: USHLLv4i16_shift + /* 79302 */ MCD_OPC_FilterValue, + 1, + 132, + 98, + 0, // Skip to: 104527 + /* 79307 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 79310 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79325 + /* 79315 */ MCD_OPC_CheckPredicate, + 21, + 119, + 98, + 0, // Skip to: 104527 + /* 79320 */ MCD_OPC_Decode, + 243, + 35, + 238, + 2, // Opcode: SQSHRUNv2i32_shift + /* 79325 */ MCD_OPC_FilterValue, + 1, + 109, + 98, + 0, // Skip to: 104527 + /* 79330 */ MCD_OPC_CheckPredicate, + 21, + 104, + 98, + 0, // Skip to: 104527 + /* 79335 */ MCD_OPC_Decode, + 162, + 46, + 239, + 2, // Opcode: USHLLv2i32_shift + /* 79340 */ MCD_OPC_FilterValue, + 1, + 94, + 98, + 0, // Skip to: 104527 + /* 79345 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 79348 */ MCD_OPC_FilterValue, + 0, + 70, + 0, + 0, // Skip to: 79423 + /* 79353 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 79356 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 79401 + /* 79361 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 79364 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79379 + /* 79369 */ MCD_OPC_CheckPredicate, + 21, + 65, + 98, + 0, // Skip to: 104527 + /* 79374 */ MCD_OPC_Decode, + 232, + 8, + 227, + 2, // Opcode: BICv4i16 + /* 79379 */ MCD_OPC_FilterValue, + 1, + 55, + 98, + 0, // Skip to: 104527 + /* 79384 */ MCD_OPC_CheckPredicate, + 21, + 50, + 98, + 0, // Skip to: 104527 + /* 79389 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 43, + 98, + 0, // Skip to: 104527 + /* 79396 */ MCD_OPC_Decode, + 178, + 45, + 234, + 2, // Opcode: UQSHRNv8i8_shift + /* 79401 */ MCD_OPC_FilterValue, + 1, + 33, + 98, + 0, // Skip to: 104527 + /* 79406 */ MCD_OPC_CheckPredicate, + 21, + 28, + 98, + 0, // Skip to: 104527 + /* 79411 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 21, + 98, + 0, // Skip to: 104527 + /* 79418 */ MCD_OPC_Decode, + 175, + 45, + 236, + 2, // Opcode: UQSHRNv4i16_shift + /* 79423 */ MCD_OPC_FilterValue, + 1, + 11, + 98, + 0, // Skip to: 104527 + /* 79428 */ MCD_OPC_CheckPredicate, + 21, + 6, + 98, + 0, // Skip to: 104527 + /* 79433 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 255, + 97, + 0, // Skip to: 104527 + /* 79440 */ MCD_OPC_Decode, + 174, + 45, + 238, + 2, // Opcode: UQSHRNv2i32_shift + /* 79445 */ MCD_OPC_FilterValue, + 1, + 245, + 97, + 0, // Skip to: 104527 + /* 79450 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 79453 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 79475 + /* 79458 */ MCD_OPC_CheckPredicate, + 21, + 232, + 97, + 0, // Skip to: 104527 + /* 79463 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 225, + 97, + 0, // Skip to: 104527 + /* 79470 */ MCD_OPC_Decode, + 238, + 27, + 223, + 2, // Opcode: MVNIv2s_msl + /* 79475 */ MCD_OPC_FilterValue, + 1, + 215, + 97, + 0, // Skip to: 104527 + /* 79480 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 79483 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 79542 + /* 79488 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 79491 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 79520 + /* 79496 */ MCD_OPC_CheckPredicate, + 21, + 194, + 97, + 0, // Skip to: 104527 + /* 79501 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 187, + 97, + 0, // Skip to: 104527 + /* 79508 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 180, + 97, + 0, // Skip to: 104527 + /* 79515 */ MCD_OPC_Decode, + 176, + 27, + 223, + 2, // Opcode: MOVID + /* 79520 */ MCD_OPC_FilterValue, + 1, + 170, + 97, + 0, // Skip to: 104527 + /* 79525 */ MCD_OPC_CheckPredicate, + 23, + 165, + 97, + 0, // Skip to: 104527 + /* 79530 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 158, + 97, + 0, // Skip to: 104527 + /* 79537 */ MCD_OPC_Decode, + 219, + 42, + 225, + 2, // Opcode: UCVTFv4i16_shift + /* 79542 */ MCD_OPC_FilterValue, + 1, + 148, + 97, + 0, // Skip to: 104527 + /* 79547 */ MCD_OPC_CheckPredicate, + 21, + 143, + 97, + 0, // Skip to: 104527 + /* 79552 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 136, + 97, + 0, // Skip to: 104527 + /* 79559 */ MCD_OPC_Decode, + 215, + 42, + 226, + 2, // Opcode: UCVTFv2i32_shift + /* 79564 */ MCD_OPC_FilterValue, + 1, + 126, + 97, + 0, // Skip to: 104527 + /* 79569 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 79572 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 79640 + /* 79577 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 79580 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 79625 + /* 79585 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 79588 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 79610 + /* 79593 */ MCD_OPC_CheckPredicate, + 21, + 97, + 97, + 0, // Skip to: 104527 + /* 79598 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 90, + 97, + 0, // Skip to: 104527 + /* 79605 */ MCD_OPC_Decode, + 168, + 35, + 234, + 2, // Opcode: SQRSHRUNv8i8_shift + /* 79610 */ MCD_OPC_FilterValue, + 1, + 80, + 97, + 0, // Skip to: 104527 + /* 79615 */ MCD_OPC_CheckPredicate, + 21, + 75, + 97, + 0, // Skip to: 104527 + /* 79620 */ MCD_OPC_Decode, + 165, + 35, + 236, + 2, // Opcode: SQRSHRUNv4i16_shift + /* 79625 */ MCD_OPC_FilterValue, + 1, + 65, + 97, + 0, // Skip to: 104527 + /* 79630 */ MCD_OPC_CheckPredicate, + 21, + 60, + 97, + 0, // Skip to: 104527 + /* 79635 */ MCD_OPC_Decode, + 164, + 35, + 238, + 2, // Opcode: SQRSHRUNv2i32_shift + /* 79640 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 79708 + /* 79645 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 79648 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 79693 + /* 79653 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 79656 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 79678 + /* 79661 */ MCD_OPC_CheckPredicate, + 21, + 29, + 97, + 0, // Skip to: 104527 + /* 79666 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 22, + 97, + 0, // Skip to: 104527 + /* 79673 */ MCD_OPC_Decode, + 129, + 45, + 234, + 2, // Opcode: UQRSHRNv8i8_shift + /* 79678 */ MCD_OPC_FilterValue, + 1, + 12, + 97, + 0, // Skip to: 104527 + /* 79683 */ MCD_OPC_CheckPredicate, + 21, + 7, + 97, + 0, // Skip to: 104527 + /* 79688 */ MCD_OPC_Decode, + 254, + 44, + 236, + 2, // Opcode: UQRSHRNv4i16_shift + /* 79693 */ MCD_OPC_FilterValue, + 1, + 253, + 96, + 0, // Skip to: 104527 + /* 79698 */ MCD_OPC_CheckPredicate, + 21, + 248, + 96, + 0, // Skip to: 104527 + /* 79703 */ MCD_OPC_Decode, + 253, + 44, + 238, + 2, // Opcode: UQRSHRNv2i32_shift + /* 79708 */ MCD_OPC_FilterValue, + 15, + 238, + 96, + 0, // Skip to: 104527 + /* 79713 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 79716 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 79738 + /* 79721 */ MCD_OPC_CheckPredicate, + 23, + 225, + 96, + 0, // Skip to: 104527 + /* 79726 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 218, + 96, + 0, // Skip to: 104527 + /* 79733 */ MCD_OPC_Decode, + 237, + 15, + 225, + 2, // Opcode: FCVTZUv4i16_shift + /* 79738 */ MCD_OPC_FilterValue, + 1, + 208, + 96, + 0, // Skip to: 104527 + /* 79743 */ MCD_OPC_CheckPredicate, + 21, + 203, + 96, + 0, // Skip to: 104527 + /* 79748 */ MCD_OPC_Decode, + 233, + 15, + 226, + 2, // Opcode: FCVTZUv2i32_shift + /* 79753 */ MCD_OPC_FilterValue, + 2, + 81, + 4, + 0, // Skip to: 80863 + /* 79758 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 79761 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 79829 + /* 79766 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 79769 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 79784 + /* 79774 */ MCD_OPC_CheckPredicate, + 23, + 172, + 96, + 0, // Skip to: 104527 + /* 79779 */ MCD_OPC_Decode, + 175, + 17, + 243, + 2, // Opcode: FMLAv8i16_indexed + /* 79784 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 79799 + /* 79789 */ MCD_OPC_CheckPredicate, + 23, + 157, + 96, + 0, // Skip to: 104527 + /* 79794 */ MCD_OPC_Decode, + 206, + 17, + 243, + 2, // Opcode: FMLSv8i16_indexed + /* 79799 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 79814 + /* 79804 */ MCD_OPC_CheckPredicate, + 23, + 142, + 96, + 0, // Skip to: 104527 + /* 79809 */ MCD_OPC_Decode, + 158, + 18, + 244, + 2, // Opcode: FMULv8i16_indexed + /* 79814 */ MCD_OPC_FilterValue, + 15, + 132, + 96, + 0, // Skip to: 104527 + /* 79819 */ MCD_OPC_CheckPredicate, + 33, + 127, + 96, + 0, // Skip to: 104527 + /* 79824 */ MCD_OPC_Decode, + 225, + 40, + 245, + 2, // Opcode: SUDOTlanev16i8 + /* 79829 */ MCD_OPC_FilterValue, + 1, + 117, + 96, + 0, // Skip to: 104527 + /* 79834 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 79837 */ MCD_OPC_FilterValue, + 0, + 41, + 3, + 0, // Skip to: 80651 + /* 79842 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 79845 */ MCD_OPC_FilterValue, + 0, + 143, + 1, + 0, // Skip to: 80249 + /* 79850 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 79853 */ MCD_OPC_FilterValue, + 0, + 148, + 0, + 0, // Skip to: 80006 + /* 79858 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 79861 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 79968 + /* 79866 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 79869 */ MCD_OPC_FilterValue, + 0, + 56, + 0, + 0, // Skip to: 79930 + /* 79874 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 79877 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79892 + /* 79882 */ MCD_OPC_CheckPredicate, + 21, + 64, + 96, + 0, // Skip to: 104527 + /* 79887 */ MCD_OPC_Decode, + 182, + 27, + 223, + 2, // Opcode: MOVIv4i32 + /* 79892 */ MCD_OPC_FilterValue, + 1, + 54, + 96, + 0, // Skip to: 104527 + /* 79897 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 79900 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79915 + /* 79905 */ MCD_OPC_CheckPredicate, + 21, + 41, + 96, + 0, // Skip to: 104527 + /* 79910 */ MCD_OPC_Decode, + 132, + 37, + 246, + 2, // Opcode: SSHRv16i8_shift + /* 79915 */ MCD_OPC_FilterValue, + 1, + 31, + 96, + 0, // Skip to: 104527 + /* 79920 */ MCD_OPC_CheckPredicate, + 21, + 26, + 96, + 0, // Skip to: 104527 + /* 79925 */ MCD_OPC_Decode, + 220, + 36, + 246, + 2, // Opcode: SRSHRv16i8_shift + /* 79930 */ MCD_OPC_FilterValue, + 1, + 16, + 96, + 0, // Skip to: 104527 + /* 79935 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 79938 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79953 + /* 79943 */ MCD_OPC_CheckPredicate, + 21, + 3, + 96, + 0, // Skip to: 104527 + /* 79948 */ MCD_OPC_Decode, + 137, + 37, + 247, + 2, // Opcode: SSHRv8i16_shift + /* 79953 */ MCD_OPC_FilterValue, + 1, + 249, + 95, + 0, // Skip to: 104527 + /* 79958 */ MCD_OPC_CheckPredicate, + 21, + 244, + 95, + 0, // Skip to: 104527 + /* 79963 */ MCD_OPC_Decode, + 225, + 36, + 247, + 2, // Opcode: SRSHRv8i16_shift + /* 79968 */ MCD_OPC_FilterValue, + 1, + 234, + 95, + 0, // Skip to: 104527 + /* 79973 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 79976 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 79991 + /* 79981 */ MCD_OPC_CheckPredicate, + 21, + 221, + 95, + 0, // Skip to: 104527 + /* 79986 */ MCD_OPC_Decode, + 136, + 37, + 248, + 2, // Opcode: SSHRv4i32_shift + /* 79991 */ MCD_OPC_FilterValue, + 1, + 211, + 95, + 0, // Skip to: 104527 + /* 79996 */ MCD_OPC_CheckPredicate, + 21, + 206, + 95, + 0, // Skip to: 104527 + /* 80001 */ MCD_OPC_Decode, + 224, + 36, + 248, + 2, // Opcode: SRSHRv4i32_shift + /* 80006 */ MCD_OPC_FilterValue, + 1, + 196, + 95, + 0, // Skip to: 104527 + /* 80011 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 80014 */ MCD_OPC_FilterValue, + 0, + 162, + 0, + 0, // Skip to: 80181 + /* 80019 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 80022 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 80113 + /* 80027 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 80030 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80045 + /* 80035 */ MCD_OPC_CheckPredicate, + 21, + 167, + 95, + 0, // Skip to: 104527 + /* 80040 */ MCD_OPC_Decode, + 161, + 28, + 227, + 2, // Opcode: ORRv4i32 + /* 80045 */ MCD_OPC_FilterValue, + 1, + 157, + 95, + 0, // Skip to: 104527 + /* 80050 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 80053 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80068 + /* 80058 */ MCD_OPC_CheckPredicate, + 21, + 144, + 95, + 0, // Skip to: 104527 + /* 80063 */ MCD_OPC_Decode, + 144, + 37, + 249, + 2, // Opcode: SSRAv16i8_shift + /* 80068 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 80083 + /* 80073 */ MCD_OPC_CheckPredicate, + 21, + 129, + 95, + 0, // Skip to: 104527 + /* 80078 */ MCD_OPC_Decode, + 232, + 36, + 249, + 2, // Opcode: SRSRAv16i8_shift + /* 80083 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 80098 + /* 80088 */ MCD_OPC_CheckPredicate, + 21, + 114, + 95, + 0, // Skip to: 104527 + /* 80093 */ MCD_OPC_Decode, + 159, + 31, + 250, + 2, // Opcode: SHLv16i8_shift + /* 80098 */ MCD_OPC_FilterValue, + 3, + 104, + 95, + 0, // Skip to: 104527 + /* 80103 */ MCD_OPC_CheckPredicate, + 21, + 99, + 95, + 0, // Skip to: 104527 + /* 80108 */ MCD_OPC_Decode, + 201, + 35, + 250, + 2, // Opcode: SQSHLv16i8_shift + /* 80113 */ MCD_OPC_FilterValue, + 1, + 89, + 95, + 0, // Skip to: 104527 + /* 80118 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 80121 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80136 + /* 80126 */ MCD_OPC_CheckPredicate, + 21, + 76, + 95, + 0, // Skip to: 104527 + /* 80131 */ MCD_OPC_Decode, + 149, + 37, + 251, + 2, // Opcode: SSRAv8i16_shift + /* 80136 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 80151 + /* 80141 */ MCD_OPC_CheckPredicate, + 21, + 61, + 95, + 0, // Skip to: 104527 + /* 80146 */ MCD_OPC_Decode, + 237, + 36, + 251, + 2, // Opcode: SRSRAv8i16_shift + /* 80151 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 80166 + /* 80156 */ MCD_OPC_CheckPredicate, + 21, + 46, + 95, + 0, // Skip to: 104527 + /* 80161 */ MCD_OPC_Decode, + 164, + 31, + 252, + 2, // Opcode: SHLv8i16_shift + /* 80166 */ MCD_OPC_FilterValue, + 3, + 36, + 95, + 0, // Skip to: 104527 + /* 80171 */ MCD_OPC_CheckPredicate, + 21, + 31, + 95, + 0, // Skip to: 104527 + /* 80176 */ MCD_OPC_Decode, + 215, + 35, + 252, + 2, // Opcode: SQSHLv8i16_shift + /* 80181 */ MCD_OPC_FilterValue, + 1, + 21, + 95, + 0, // Skip to: 104527 + /* 80186 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 80189 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80204 + /* 80194 */ MCD_OPC_CheckPredicate, + 21, + 8, + 95, + 0, // Skip to: 104527 + /* 80199 */ MCD_OPC_Decode, + 148, + 37, + 253, + 2, // Opcode: SSRAv4i32_shift + /* 80204 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 80219 + /* 80209 */ MCD_OPC_CheckPredicate, + 21, + 249, + 94, + 0, // Skip to: 104527 + /* 80214 */ MCD_OPC_Decode, + 236, + 36, + 253, + 2, // Opcode: SRSRAv4i32_shift + /* 80219 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 80234 + /* 80224 */ MCD_OPC_CheckPredicate, + 21, + 234, + 94, + 0, // Skip to: 104527 + /* 80229 */ MCD_OPC_Decode, + 163, + 31, + 254, + 2, // Opcode: SHLv4i32_shift + /* 80234 */ MCD_OPC_FilterValue, + 3, + 224, + 94, + 0, // Skip to: 104527 + /* 80239 */ MCD_OPC_CheckPredicate, + 21, + 219, + 94, + 0, // Skip to: 104527 + /* 80244 */ MCD_OPC_Decode, + 213, + 35, + 254, + 2, // Opcode: SQSHLv4i32_shift + /* 80249 */ MCD_OPC_FilterValue, + 1, + 209, + 94, + 0, // Skip to: 104527 + /* 80254 */ MCD_OPC_ExtractField, + 14, + 1, // Inst{14} ... + /* 80257 */ MCD_OPC_FilterValue, + 0, + 5, + 1, + 0, // Skip to: 80523 + /* 80262 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 80265 */ MCD_OPC_FilterValue, + 0, + 148, + 0, + 0, // Skip to: 80418 + /* 80270 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 80273 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 80380 + /* 80278 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 80281 */ MCD_OPC_FilterValue, + 0, + 56, + 0, + 0, // Skip to: 80342 + /* 80286 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 80289 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80304 + /* 80294 */ MCD_OPC_CheckPredicate, + 21, + 164, + 94, + 0, // Skip to: 104527 + /* 80299 */ MCD_OPC_Decode, + 185, + 27, + 223, + 2, // Opcode: MOVIv8i16 + /* 80304 */ MCD_OPC_FilterValue, + 1, + 154, + 94, + 0, // Skip to: 104527 + /* 80309 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 80312 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80327 + /* 80317 */ MCD_OPC_CheckPredicate, + 21, + 141, + 94, + 0, // Skip to: 104527 + /* 80322 */ MCD_OPC_Decode, + 172, + 31, + 255, + 2, // Opcode: SHRNv16i8_shift + /* 80327 */ MCD_OPC_FilterValue, + 1, + 131, + 94, + 0, // Skip to: 104527 + /* 80332 */ MCD_OPC_CheckPredicate, + 21, + 126, + 94, + 0, // Skip to: 104527 + /* 80337 */ MCD_OPC_Decode, + 245, + 36, + 250, + 2, // Opcode: SSHLLv16i8_shift + /* 80342 */ MCD_OPC_FilterValue, + 1, + 116, + 94, + 0, // Skip to: 104527 + /* 80347 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 80350 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80365 + /* 80355 */ MCD_OPC_CheckPredicate, + 21, + 103, + 94, + 0, // Skip to: 104527 + /* 80360 */ MCD_OPC_Decode, + 176, + 31, + 128, + 3, // Opcode: SHRNv8i16_shift + /* 80365 */ MCD_OPC_FilterValue, + 1, + 93, + 94, + 0, // Skip to: 104527 + /* 80370 */ MCD_OPC_CheckPredicate, + 21, + 88, + 94, + 0, // Skip to: 104527 + /* 80375 */ MCD_OPC_Decode, + 249, + 36, + 252, + 2, // Opcode: SSHLLv8i16_shift + /* 80380 */ MCD_OPC_FilterValue, + 1, + 78, + 94, + 0, // Skip to: 104527 + /* 80385 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 80388 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80403 + /* 80393 */ MCD_OPC_CheckPredicate, + 21, + 65, + 94, + 0, // Skip to: 104527 + /* 80398 */ MCD_OPC_Decode, + 175, + 31, + 129, + 3, // Opcode: SHRNv4i32_shift + /* 80403 */ MCD_OPC_FilterValue, + 1, + 55, + 94, + 0, // Skip to: 104527 + /* 80408 */ MCD_OPC_CheckPredicate, + 21, + 50, + 94, + 0, // Skip to: 104527 + /* 80413 */ MCD_OPC_Decode, + 248, + 36, + 254, + 2, // Opcode: SSHLLv4i32_shift + /* 80418 */ MCD_OPC_FilterValue, + 1, + 40, + 94, + 0, // Skip to: 104527 + /* 80423 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 80426 */ MCD_OPC_FilterValue, + 0, + 70, + 0, + 0, // Skip to: 80501 + /* 80431 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 80434 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 80479 + /* 80439 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 80442 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80457 + /* 80447 */ MCD_OPC_CheckPredicate, + 21, + 11, + 94, + 0, // Skip to: 104527 + /* 80452 */ MCD_OPC_Decode, + 162, + 28, + 227, + 2, // Opcode: ORRv8i16 + /* 80457 */ MCD_OPC_FilterValue, + 1, + 1, + 94, + 0, // Skip to: 104527 + /* 80462 */ MCD_OPC_CheckPredicate, + 21, + 252, + 93, + 0, // Skip to: 104527 + /* 80467 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 245, + 93, + 0, // Skip to: 104527 + /* 80474 */ MCD_OPC_Decode, + 227, + 35, + 255, + 2, // Opcode: SQSHRNv16i8_shift + /* 80479 */ MCD_OPC_FilterValue, + 1, + 235, + 93, + 0, // Skip to: 104527 + /* 80484 */ MCD_OPC_CheckPredicate, + 21, + 230, + 93, + 0, // Skip to: 104527 + /* 80489 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 223, + 93, + 0, // Skip to: 104527 + /* 80496 */ MCD_OPC_Decode, + 231, + 35, + 128, + 3, // Opcode: SQSHRNv8i16_shift + /* 80501 */ MCD_OPC_FilterValue, + 1, + 213, + 93, + 0, // Skip to: 104527 + /* 80506 */ MCD_OPC_CheckPredicate, + 21, + 208, + 93, + 0, // Skip to: 104527 + /* 80511 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 201, + 93, + 0, // Skip to: 104527 + /* 80518 */ MCD_OPC_Decode, + 230, + 35, + 129, + 3, // Opcode: SQSHRNv4i32_shift + /* 80523 */ MCD_OPC_FilterValue, + 1, + 191, + 93, + 0, // Skip to: 104527 + /* 80528 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 80531 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 80553 + /* 80536 */ MCD_OPC_CheckPredicate, + 21, + 178, + 93, + 0, // Skip to: 104527 + /* 80541 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 171, + 93, + 0, // Skip to: 104527 + /* 80548 */ MCD_OPC_Decode, + 183, + 27, + 223, + 2, // Opcode: MOVIv4s_msl + /* 80553 */ MCD_OPC_FilterValue, + 1, + 161, + 93, + 0, // Skip to: 104527 + /* 80558 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 80561 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 80629 + /* 80566 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 80569 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 80614 + /* 80574 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 80577 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 80599 + /* 80582 */ MCD_OPC_CheckPredicate, + 21, + 132, + 93, + 0, // Skip to: 104527 + /* 80587 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 125, + 93, + 0, // Skip to: 104527 + /* 80594 */ MCD_OPC_Decode, + 177, + 27, + 223, + 2, // Opcode: MOVIv16b_ns + /* 80599 */ MCD_OPC_FilterValue, + 1, + 115, + 93, + 0, // Skip to: 104527 + /* 80604 */ MCD_OPC_CheckPredicate, + 23, + 110, + 93, + 0, // Skip to: 104527 + /* 80609 */ MCD_OPC_Decode, + 233, + 30, + 247, + 2, // Opcode: SCVTFv8i16_shift + /* 80614 */ MCD_OPC_FilterValue, + 1, + 100, + 93, + 0, // Skip to: 104527 + /* 80619 */ MCD_OPC_CheckPredicate, + 21, + 95, + 93, + 0, // Skip to: 104527 + /* 80624 */ MCD_OPC_Decode, + 231, + 30, + 248, + 2, // Opcode: SCVTFv4i32_shift + /* 80629 */ MCD_OPC_FilterValue, + 1, + 85, + 93, + 0, // Skip to: 104527 + /* 80634 */ MCD_OPC_CheckPredicate, + 21, + 80, + 93, + 0, // Skip to: 104527 + /* 80639 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 73, + 93, + 0, // Skip to: 104527 + /* 80646 */ MCD_OPC_Decode, + 232, + 17, + 223, + 2, // Opcode: FMOVv4f32_ns + /* 80651 */ MCD_OPC_FilterValue, + 1, + 63, + 93, + 0, // Skip to: 104527 + /* 80656 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 80659 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 80727 + /* 80664 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 80667 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 80712 + /* 80672 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 80675 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 80697 + /* 80680 */ MCD_OPC_CheckPredicate, + 21, + 34, + 93, + 0, // Skip to: 104527 + /* 80685 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 27, + 93, + 0, // Skip to: 104527 + /* 80692 */ MCD_OPC_Decode, + 200, + 29, + 255, + 2, // Opcode: RSHRNv16i8_shift + /* 80697 */ MCD_OPC_FilterValue, + 1, + 17, + 93, + 0, // Skip to: 104527 + /* 80702 */ MCD_OPC_CheckPredicate, + 21, + 12, + 93, + 0, // Skip to: 104527 + /* 80707 */ MCD_OPC_Decode, + 204, + 29, + 128, + 3, // Opcode: RSHRNv8i16_shift + /* 80712 */ MCD_OPC_FilterValue, + 1, + 2, + 93, + 0, // Skip to: 104527 + /* 80717 */ MCD_OPC_CheckPredicate, + 21, + 253, + 92, + 0, // Skip to: 104527 + /* 80722 */ MCD_OPC_Decode, + 203, + 29, + 129, + 3, // Opcode: RSHRNv4i32_shift + /* 80727 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 80795 + /* 80732 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 80735 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 80780 + /* 80740 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 80743 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 80765 + /* 80748 */ MCD_OPC_CheckPredicate, + 21, + 222, + 92, + 0, // Skip to: 104527 + /* 80753 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 215, + 92, + 0, // Skip to: 104527 + /* 80760 */ MCD_OPC_Decode, + 148, + 35, + 255, + 2, // Opcode: SQRSHRNv16i8_shift + /* 80765 */ MCD_OPC_FilterValue, + 1, + 205, + 92, + 0, // Skip to: 104527 + /* 80770 */ MCD_OPC_CheckPredicate, + 21, + 200, + 92, + 0, // Skip to: 104527 + /* 80775 */ MCD_OPC_Decode, + 152, + 35, + 128, + 3, // Opcode: SQRSHRNv8i16_shift + /* 80780 */ MCD_OPC_FilterValue, + 1, + 190, + 92, + 0, // Skip to: 104527 + /* 80785 */ MCD_OPC_CheckPredicate, + 21, + 185, + 92, + 0, // Skip to: 104527 + /* 80790 */ MCD_OPC_Decode, + 151, + 35, + 129, + 3, // Opcode: SQRSHRNv4i32_shift + /* 80795 */ MCD_OPC_FilterValue, + 15, + 175, + 92, + 0, // Skip to: 104527 + /* 80800 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 80803 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 80848 + /* 80808 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 80811 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 80833 + /* 80816 */ MCD_OPC_CheckPredicate, + 23, + 154, + 92, + 0, // Skip to: 104527 + /* 80821 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 147, + 92, + 0, // Skip to: 104527 + /* 80828 */ MCD_OPC_Decode, + 233, + 17, + 223, + 2, // Opcode: FMOVv8f16_ns + /* 80833 */ MCD_OPC_FilterValue, + 1, + 137, + 92, + 0, // Skip to: 104527 + /* 80838 */ MCD_OPC_CheckPredicate, + 23, + 132, + 92, + 0, // Skip to: 104527 + /* 80843 */ MCD_OPC_Decode, + 205, + 15, + 247, + 2, // Opcode: FCVTZSv8i16_shift + /* 80848 */ MCD_OPC_FilterValue, + 1, + 122, + 92, + 0, // Skip to: 104527 + /* 80853 */ MCD_OPC_CheckPredicate, + 21, + 117, + 92, + 0, // Skip to: 104527 + /* 80858 */ MCD_OPC_Decode, + 203, + 15, + 248, + 2, // Opcode: FCVTZSv4i32_shift + /* 80863 */ MCD_OPC_FilterValue, + 3, + 107, + 92, + 0, // Skip to: 104527 + /* 80868 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 80871 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 80893 + /* 80876 */ MCD_OPC_CheckPredicate, + 23, + 94, + 92, + 0, // Skip to: 104527 + /* 80881 */ MCD_OPC_CheckField, + 12, + 4, + 9, + 87, + 92, + 0, // Skip to: 104527 + /* 80888 */ MCD_OPC_Decode, + 133, + 18, + 244, + 2, // Opcode: FMULXv8i16_indexed + /* 80893 */ MCD_OPC_FilterValue, + 1, + 77, + 92, + 0, // Skip to: 104527 + /* 80898 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 80901 */ MCD_OPC_FilterValue, + 0, + 131, + 3, + 0, // Skip to: 81805 + /* 80906 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 80909 */ MCD_OPC_FilterValue, + 0, + 233, + 1, + 0, // Skip to: 81403 + /* 80914 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 80917 */ MCD_OPC_FilterValue, + 0, + 238, + 0, + 0, // Skip to: 81160 + /* 80922 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 80925 */ MCD_OPC_FilterValue, + 0, + 162, + 0, + 0, // Skip to: 81092 + /* 80930 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 80933 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 81024 + /* 80938 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 80941 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80956 + /* 80946 */ MCD_OPC_CheckPredicate, + 21, + 24, + 92, + 0, // Skip to: 104527 + /* 80951 */ MCD_OPC_Decode, + 240, + 27, + 223, + 2, // Opcode: MVNIv4i32 + /* 80956 */ MCD_OPC_FilterValue, + 1, + 14, + 92, + 0, // Skip to: 104527 + /* 80961 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 80964 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 80979 + /* 80969 */ MCD_OPC_CheckPredicate, + 21, + 1, + 92, + 0, // Skip to: 104527 + /* 80974 */ MCD_OPC_Decode, + 176, + 46, + 246, + 2, // Opcode: USHRv16i8_shift + /* 80979 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 80994 + /* 80984 */ MCD_OPC_CheckPredicate, + 21, + 242, + 91, + 0, // Skip to: 104527 + /* 80989 */ MCD_OPC_Decode, + 255, + 45, + 246, + 2, // Opcode: URSHRv16i8_shift + /* 80994 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 81009 + /* 80999 */ MCD_OPC_CheckPredicate, + 21, + 227, + 91, + 0, // Skip to: 104527 + /* 81004 */ MCD_OPC_Decode, + 192, + 36, + 249, + 2, // Opcode: SRIv16i8_shift + /* 81009 */ MCD_OPC_FilterValue, + 3, + 217, + 91, + 0, // Skip to: 104527 + /* 81014 */ MCD_OPC_CheckPredicate, + 21, + 212, + 91, + 0, // Skip to: 104527 + /* 81019 */ MCD_OPC_Decode, + 181, + 35, + 250, + 2, // Opcode: SQSHLUv16i8_shift + /* 81024 */ MCD_OPC_FilterValue, + 1, + 202, + 91, + 0, // Skip to: 104527 + /* 81029 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 81032 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81047 + /* 81037 */ MCD_OPC_CheckPredicate, + 21, + 189, + 91, + 0, // Skip to: 104527 + /* 81042 */ MCD_OPC_Decode, + 181, + 46, + 247, + 2, // Opcode: USHRv8i16_shift + /* 81047 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 81062 + /* 81052 */ MCD_OPC_CheckPredicate, + 21, + 174, + 91, + 0, // Skip to: 104527 + /* 81057 */ MCD_OPC_Decode, + 132, + 46, + 247, + 2, // Opcode: URSHRv8i16_shift + /* 81062 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 81077 + /* 81067 */ MCD_OPC_CheckPredicate, + 21, + 159, + 91, + 0, // Skip to: 104527 + /* 81072 */ MCD_OPC_Decode, + 197, + 36, + 251, + 2, // Opcode: SRIv8i16_shift + /* 81077 */ MCD_OPC_FilterValue, + 3, + 149, + 91, + 0, // Skip to: 104527 + /* 81082 */ MCD_OPC_CheckPredicate, + 21, + 144, + 91, + 0, // Skip to: 104527 + /* 81087 */ MCD_OPC_Decode, + 186, + 35, + 252, + 2, // Opcode: SQSHLUv8i16_shift + /* 81092 */ MCD_OPC_FilterValue, + 1, + 134, + 91, + 0, // Skip to: 104527 + /* 81097 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 81100 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81115 + /* 81105 */ MCD_OPC_CheckPredicate, + 21, + 121, + 91, + 0, // Skip to: 104527 + /* 81110 */ MCD_OPC_Decode, + 180, + 46, + 248, + 2, // Opcode: USHRv4i32_shift + /* 81115 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 81130 + /* 81120 */ MCD_OPC_CheckPredicate, + 21, + 106, + 91, + 0, // Skip to: 104527 + /* 81125 */ MCD_OPC_Decode, + 131, + 46, + 248, + 2, // Opcode: URSHRv4i32_shift + /* 81130 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 81145 + /* 81135 */ MCD_OPC_CheckPredicate, + 21, + 91, + 91, + 0, // Skip to: 104527 + /* 81140 */ MCD_OPC_Decode, + 196, + 36, + 253, + 2, // Opcode: SRIv4i32_shift + /* 81145 */ MCD_OPC_FilterValue, + 3, + 81, + 91, + 0, // Skip to: 104527 + /* 81150 */ MCD_OPC_CheckPredicate, + 21, + 76, + 91, + 0, // Skip to: 104527 + /* 81155 */ MCD_OPC_Decode, + 185, + 35, + 254, + 2, // Opcode: SQSHLUv4i32_shift + /* 81160 */ MCD_OPC_FilterValue, + 1, + 66, + 91, + 0, // Skip to: 104527 + /* 81165 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 81168 */ MCD_OPC_FilterValue, + 0, + 162, + 0, + 0, // Skip to: 81335 + /* 81173 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 81176 */ MCD_OPC_FilterValue, + 0, + 86, + 0, + 0, // Skip to: 81267 + /* 81181 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 81184 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81199 + /* 81189 */ MCD_OPC_CheckPredicate, + 21, + 37, + 91, + 0, // Skip to: 104527 + /* 81194 */ MCD_OPC_Decode, + 233, + 8, + 227, + 2, // Opcode: BICv4i32 + /* 81199 */ MCD_OPC_FilterValue, + 1, + 27, + 91, + 0, // Skip to: 104527 + /* 81204 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 81207 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81222 + /* 81212 */ MCD_OPC_CheckPredicate, + 21, + 14, + 91, + 0, // Skip to: 104527 + /* 81217 */ MCD_OPC_Decode, + 209, + 46, + 249, + 2, // Opcode: USRAv16i8_shift + /* 81222 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 81237 + /* 81227 */ MCD_OPC_CheckPredicate, + 21, + 255, + 90, + 0, // Skip to: 104527 + /* 81232 */ MCD_OPC_Decode, + 142, + 46, + 249, + 2, // Opcode: URSRAv16i8_shift + /* 81237 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 81252 + /* 81242 */ MCD_OPC_CheckPredicate, + 21, + 240, + 90, + 0, // Skip to: 104527 + /* 81247 */ MCD_OPC_Decode, + 197, + 31, + 130, + 3, // Opcode: SLIv16i8_shift + /* 81252 */ MCD_OPC_FilterValue, + 3, + 230, + 90, + 0, // Skip to: 104527 + /* 81257 */ MCD_OPC_CheckPredicate, + 21, + 225, + 90, + 0, // Skip to: 104527 + /* 81262 */ MCD_OPC_Decode, + 147, + 45, + 250, + 2, // Opcode: UQSHLv16i8_shift + /* 81267 */ MCD_OPC_FilterValue, + 1, + 215, + 90, + 0, // Skip to: 104527 + /* 81272 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 81275 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81290 + /* 81280 */ MCD_OPC_CheckPredicate, + 21, + 202, + 90, + 0, // Skip to: 104527 + /* 81285 */ MCD_OPC_Decode, + 214, + 46, + 251, + 2, // Opcode: USRAv8i16_shift + /* 81290 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 81305 + /* 81295 */ MCD_OPC_CheckPredicate, + 21, + 187, + 90, + 0, // Skip to: 104527 + /* 81300 */ MCD_OPC_Decode, + 147, + 46, + 251, + 2, // Opcode: URSRAv8i16_shift + /* 81305 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 81320 + /* 81310 */ MCD_OPC_CheckPredicate, + 21, + 172, + 90, + 0, // Skip to: 104527 + /* 81315 */ MCD_OPC_Decode, + 202, + 31, + 131, + 3, // Opcode: SLIv8i16_shift + /* 81320 */ MCD_OPC_FilterValue, + 3, + 162, + 90, + 0, // Skip to: 104527 + /* 81325 */ MCD_OPC_CheckPredicate, + 21, + 157, + 90, + 0, // Skip to: 104527 + /* 81330 */ MCD_OPC_Decode, + 161, + 45, + 252, + 2, // Opcode: UQSHLv8i16_shift + /* 81335 */ MCD_OPC_FilterValue, + 1, + 147, + 90, + 0, // Skip to: 104527 + /* 81340 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 81343 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81358 + /* 81348 */ MCD_OPC_CheckPredicate, + 21, + 134, + 90, + 0, // Skip to: 104527 + /* 81353 */ MCD_OPC_Decode, + 213, + 46, + 253, + 2, // Opcode: USRAv4i32_shift + /* 81358 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 81373 + /* 81363 */ MCD_OPC_CheckPredicate, + 21, + 119, + 90, + 0, // Skip to: 104527 + /* 81368 */ MCD_OPC_Decode, + 146, + 46, + 253, + 2, // Opcode: URSRAv4i32_shift + /* 81373 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 81388 + /* 81378 */ MCD_OPC_CheckPredicate, + 21, + 104, + 90, + 0, // Skip to: 104527 + /* 81383 */ MCD_OPC_Decode, + 201, + 31, + 132, + 3, // Opcode: SLIv4i32_shift + /* 81388 */ MCD_OPC_FilterValue, + 3, + 94, + 90, + 0, // Skip to: 104527 + /* 81393 */ MCD_OPC_CheckPredicate, + 21, + 89, + 90, + 0, // Skip to: 104527 + /* 81398 */ MCD_OPC_Decode, + 159, + 45, + 254, + 2, // Opcode: UQSHLv4i32_shift + /* 81403 */ MCD_OPC_FilterValue, + 1, + 79, + 90, + 0, // Skip to: 104527 + /* 81408 */ MCD_OPC_ExtractField, + 14, + 1, // Inst{14} ... + /* 81411 */ MCD_OPC_FilterValue, + 0, + 5, + 1, + 0, // Skip to: 81677 + /* 81416 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 81419 */ MCD_OPC_FilterValue, + 0, + 148, + 0, + 0, // Skip to: 81572 + /* 81424 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 81427 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 81534 + /* 81432 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 81435 */ MCD_OPC_FilterValue, + 0, + 56, + 0, + 0, // Skip to: 81496 + /* 81440 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 81443 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81458 + /* 81448 */ MCD_OPC_CheckPredicate, + 21, + 34, + 90, + 0, // Skip to: 104527 + /* 81453 */ MCD_OPC_Decode, + 242, + 27, + 223, + 2, // Opcode: MVNIv8i16 + /* 81458 */ MCD_OPC_FilterValue, + 1, + 24, + 90, + 0, // Skip to: 104527 + /* 81463 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 81466 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81481 + /* 81471 */ MCD_OPC_CheckPredicate, + 21, + 11, + 90, + 0, // Skip to: 104527 + /* 81476 */ MCD_OPC_Decode, + 242, + 35, + 255, + 2, // Opcode: SQSHRUNv16i8_shift + /* 81481 */ MCD_OPC_FilterValue, + 1, + 1, + 90, + 0, // Skip to: 104527 + /* 81486 */ MCD_OPC_CheckPredicate, + 21, + 252, + 89, + 0, // Skip to: 104527 + /* 81491 */ MCD_OPC_Decode, + 161, + 46, + 250, + 2, // Opcode: USHLLv16i8_shift + /* 81496 */ MCD_OPC_FilterValue, + 1, + 242, + 89, + 0, // Skip to: 104527 + /* 81501 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 81504 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81519 + /* 81509 */ MCD_OPC_CheckPredicate, + 21, + 229, + 89, + 0, // Skip to: 104527 + /* 81514 */ MCD_OPC_Decode, + 246, + 35, + 128, + 3, // Opcode: SQSHRUNv8i16_shift + /* 81519 */ MCD_OPC_FilterValue, + 1, + 219, + 89, + 0, // Skip to: 104527 + /* 81524 */ MCD_OPC_CheckPredicate, + 21, + 214, + 89, + 0, // Skip to: 104527 + /* 81529 */ MCD_OPC_Decode, + 165, + 46, + 252, + 2, // Opcode: USHLLv8i16_shift + /* 81534 */ MCD_OPC_FilterValue, + 1, + 204, + 89, + 0, // Skip to: 104527 + /* 81539 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 81542 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81557 + /* 81547 */ MCD_OPC_CheckPredicate, + 21, + 191, + 89, + 0, // Skip to: 104527 + /* 81552 */ MCD_OPC_Decode, + 245, + 35, + 129, + 3, // Opcode: SQSHRUNv4i32_shift + /* 81557 */ MCD_OPC_FilterValue, + 1, + 181, + 89, + 0, // Skip to: 104527 + /* 81562 */ MCD_OPC_CheckPredicate, + 21, + 176, + 89, + 0, // Skip to: 104527 + /* 81567 */ MCD_OPC_Decode, + 164, + 46, + 254, + 2, // Opcode: USHLLv4i32_shift + /* 81572 */ MCD_OPC_FilterValue, + 1, + 166, + 89, + 0, // Skip to: 104527 + /* 81577 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 81580 */ MCD_OPC_FilterValue, + 0, + 70, + 0, + 0, // Skip to: 81655 + /* 81585 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 81588 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 81633 + /* 81593 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 81596 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 81611 + /* 81601 */ MCD_OPC_CheckPredicate, + 21, + 137, + 89, + 0, // Skip to: 104527 + /* 81606 */ MCD_OPC_Decode, + 234, + 8, + 227, + 2, // Opcode: BICv8i16 + /* 81611 */ MCD_OPC_FilterValue, + 1, + 127, + 89, + 0, // Skip to: 104527 + /* 81616 */ MCD_OPC_CheckPredicate, + 21, + 122, + 89, + 0, // Skip to: 104527 + /* 81621 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 115, + 89, + 0, // Skip to: 104527 + /* 81628 */ MCD_OPC_Decode, + 173, + 45, + 255, + 2, // Opcode: UQSHRNv16i8_shift + /* 81633 */ MCD_OPC_FilterValue, + 1, + 105, + 89, + 0, // Skip to: 104527 + /* 81638 */ MCD_OPC_CheckPredicate, + 21, + 100, + 89, + 0, // Skip to: 104527 + /* 81643 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 93, + 89, + 0, // Skip to: 104527 + /* 81650 */ MCD_OPC_Decode, + 177, + 45, + 128, + 3, // Opcode: UQSHRNv8i16_shift + /* 81655 */ MCD_OPC_FilterValue, + 1, + 83, + 89, + 0, // Skip to: 104527 + /* 81660 */ MCD_OPC_CheckPredicate, + 21, + 78, + 89, + 0, // Skip to: 104527 + /* 81665 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 71, + 89, + 0, // Skip to: 104527 + /* 81672 */ MCD_OPC_Decode, + 176, + 45, + 129, + 3, // Opcode: UQSHRNv4i32_shift + /* 81677 */ MCD_OPC_FilterValue, + 1, + 61, + 89, + 0, // Skip to: 104527 + /* 81682 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 81685 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 81707 + /* 81690 */ MCD_OPC_CheckPredicate, + 21, + 48, + 89, + 0, // Skip to: 104527 + /* 81695 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 41, + 89, + 0, // Skip to: 104527 + /* 81702 */ MCD_OPC_Decode, + 241, + 27, + 223, + 2, // Opcode: MVNIv4s_msl + /* 81707 */ MCD_OPC_FilterValue, + 1, + 31, + 89, + 0, // Skip to: 104527 + /* 81712 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 81715 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 81783 + /* 81720 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 81723 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 81768 + /* 81728 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 81731 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 81753 + /* 81736 */ MCD_OPC_CheckPredicate, + 21, + 2, + 89, + 0, // Skip to: 104527 + /* 81741 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 251, + 88, + 0, // Skip to: 104527 + /* 81748 */ MCD_OPC_Decode, + 178, + 27, + 223, + 2, // Opcode: MOVIv2d_ns + /* 81753 */ MCD_OPC_FilterValue, + 1, + 241, + 88, + 0, // Skip to: 104527 + /* 81758 */ MCD_OPC_CheckPredicate, + 23, + 236, + 88, + 0, // Skip to: 104527 + /* 81763 */ MCD_OPC_Decode, + 222, + 42, + 247, + 2, // Opcode: UCVTFv8i16_shift + /* 81768 */ MCD_OPC_FilterValue, + 1, + 226, + 88, + 0, // Skip to: 104527 + /* 81773 */ MCD_OPC_CheckPredicate, + 21, + 221, + 88, + 0, // Skip to: 104527 + /* 81778 */ MCD_OPC_Decode, + 220, + 42, + 248, + 2, // Opcode: UCVTFv4i32_shift + /* 81783 */ MCD_OPC_FilterValue, + 1, + 211, + 88, + 0, // Skip to: 104527 + /* 81788 */ MCD_OPC_CheckPredicate, + 21, + 206, + 88, + 0, // Skip to: 104527 + /* 81793 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 199, + 88, + 0, // Skip to: 104527 + /* 81800 */ MCD_OPC_Decode, + 230, + 17, + 223, + 2, // Opcode: FMOVv2f64_ns + /* 81805 */ MCD_OPC_FilterValue, + 1, + 189, + 88, + 0, // Skip to: 104527 + /* 81810 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 81813 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 81881 + /* 81818 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 81821 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 81866 + /* 81826 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 81829 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 81851 + /* 81834 */ MCD_OPC_CheckPredicate, + 21, + 160, + 88, + 0, // Skip to: 104527 + /* 81839 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 153, + 88, + 0, // Skip to: 104527 + /* 81846 */ MCD_OPC_Decode, + 163, + 35, + 255, + 2, // Opcode: SQRSHRUNv16i8_shift + /* 81851 */ MCD_OPC_FilterValue, + 1, + 143, + 88, + 0, // Skip to: 104527 + /* 81856 */ MCD_OPC_CheckPredicate, + 21, + 138, + 88, + 0, // Skip to: 104527 + /* 81861 */ MCD_OPC_Decode, + 167, + 35, + 128, + 3, // Opcode: SQRSHRUNv8i16_shift + /* 81866 */ MCD_OPC_FilterValue, + 1, + 128, + 88, + 0, // Skip to: 104527 + /* 81871 */ MCD_OPC_CheckPredicate, + 21, + 123, + 88, + 0, // Skip to: 104527 + /* 81876 */ MCD_OPC_Decode, + 166, + 35, + 129, + 3, // Opcode: SQRSHRUNv4i32_shift + /* 81881 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 81949 + /* 81886 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 81889 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 81934 + /* 81894 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 81897 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 81919 + /* 81902 */ MCD_OPC_CheckPredicate, + 21, + 92, + 88, + 0, // Skip to: 104527 + /* 81907 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 85, + 88, + 0, // Skip to: 104527 + /* 81914 */ MCD_OPC_Decode, + 252, + 44, + 255, + 2, // Opcode: UQRSHRNv16i8_shift + /* 81919 */ MCD_OPC_FilterValue, + 1, + 75, + 88, + 0, // Skip to: 104527 + /* 81924 */ MCD_OPC_CheckPredicate, + 21, + 70, + 88, + 0, // Skip to: 104527 + /* 81929 */ MCD_OPC_Decode, + 128, + 45, + 128, + 3, // Opcode: UQRSHRNv8i16_shift + /* 81934 */ MCD_OPC_FilterValue, + 1, + 60, + 88, + 0, // Skip to: 104527 + /* 81939 */ MCD_OPC_CheckPredicate, + 21, + 55, + 88, + 0, // Skip to: 104527 + /* 81944 */ MCD_OPC_Decode, + 255, + 44, + 129, + 3, // Opcode: UQRSHRNv4i32_shift + /* 81949 */ MCD_OPC_FilterValue, + 15, + 45, + 88, + 0, // Skip to: 104527 + /* 81954 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 81957 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 81979 + /* 81962 */ MCD_OPC_CheckPredicate, + 23, + 32, + 88, + 0, // Skip to: 104527 + /* 81967 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 25, + 88, + 0, // Skip to: 104527 + /* 81974 */ MCD_OPC_Decode, + 240, + 15, + 247, + 2, // Opcode: FCVTZUv8i16_shift + /* 81979 */ MCD_OPC_FilterValue, + 1, + 15, + 88, + 0, // Skip to: 104527 + /* 81984 */ MCD_OPC_CheckPredicate, + 21, + 10, + 88, + 0, // Skip to: 104527 + /* 81989 */ MCD_OPC_Decode, + 238, + 15, + 248, + 2, // Opcode: FCVTZUv4i32_shift + /* 81994 */ MCD_OPC_FilterValue, + 13, + 141, + 4, + 0, // Skip to: 83164 + /* 81999 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 82002 */ MCD_OPC_FilterValue, + 0, + 223, + 0, + 0, // Skip to: 82230 + /* 82007 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 82010 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 82032 + /* 82015 */ MCD_OPC_CheckPredicate, + 21, + 235, + 87, + 0, // Skip to: 104527 + /* 82020 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 228, + 87, + 0, // Skip to: 104527 + /* 82027 */ MCD_OPC_Decode, + 168, + 32, + 133, + 3, // Opcode: SMLALv4i16_indexed + /* 82032 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 82054 + /* 82037 */ MCD_OPC_CheckPredicate, + 21, + 213, + 87, + 0, // Skip to: 104527 + /* 82042 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 206, + 87, + 0, // Skip to: 104527 + /* 82049 */ MCD_OPC_Decode, + 204, + 33, + 133, + 3, // Opcode: SQDMLALv4i16_indexed + /* 82054 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 82076 + /* 82059 */ MCD_OPC_CheckPredicate, + 21, + 191, + 87, + 0, // Skip to: 104527 + /* 82064 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 184, + 87, + 0, // Skip to: 104527 + /* 82071 */ MCD_OPC_Decode, + 188, + 32, + 133, + 3, // Opcode: SMLSLv4i16_indexed + /* 82076 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 82098 + /* 82081 */ MCD_OPC_CheckPredicate, + 21, + 169, + 87, + 0, // Skip to: 104527 + /* 82086 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 162, + 87, + 0, // Skip to: 104527 + /* 82093 */ MCD_OPC_Decode, + 229, + 33, + 133, + 3, // Opcode: SQDMLSLv4i16_indexed + /* 82098 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 82120 + /* 82103 */ MCD_OPC_CheckPredicate, + 21, + 147, + 87, + 0, // Skip to: 104527 + /* 82108 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 140, + 87, + 0, // Skip to: 104527 + /* 82115 */ MCD_OPC_Decode, + 231, + 27, + 221, + 2, // Opcode: MULv4i16_indexed + /* 82120 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 82142 + /* 82125 */ MCD_OPC_CheckPredicate, + 21, + 125, + 87, + 0, // Skip to: 104527 + /* 82130 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 118, + 87, + 0, // Skip to: 104527 + /* 82137 */ MCD_OPC_Decode, + 234, + 32, + 134, + 3, // Opcode: SMULLv4i16_indexed + /* 82142 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 82164 + /* 82147 */ MCD_OPC_CheckPredicate, + 21, + 103, + 87, + 0, // Skip to: 104527 + /* 82152 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 96, + 87, + 0, // Skip to: 104527 + /* 82159 */ MCD_OPC_Decode, + 142, + 34, + 134, + 3, // Opcode: SQDMULLv4i16_indexed + /* 82164 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 82186 + /* 82169 */ MCD_OPC_CheckPredicate, + 21, + 81, + 87, + 0, // Skip to: 104527 + /* 82174 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 74, + 87, + 0, // Skip to: 104527 + /* 82181 */ MCD_OPC_Decode, + 249, + 33, + 221, + 2, // Opcode: SQDMULHv4i16_indexed + /* 82186 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 82208 + /* 82191 */ MCD_OPC_CheckPredicate, + 21, + 59, + 87, + 0, // Skip to: 104527 + /* 82196 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 52, + 87, + 0, // Skip to: 104527 + /* 82203 */ MCD_OPC_Decode, + 243, + 34, + 221, + 2, // Opcode: SQRDMULHv4i16_indexed + /* 82208 */ MCD_OPC_FilterValue, + 15, + 42, + 87, + 0, // Skip to: 104527 + /* 82213 */ MCD_OPC_CheckPredicate, + 30, + 37, + 87, + 0, // Skip to: 104527 + /* 82218 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 30, + 87, + 0, // Skip to: 104527 + /* 82225 */ MCD_OPC_Decode, + 192, + 8, + 222, + 2, // Opcode: BF16DOTlanev4bf16 + /* 82230 */ MCD_OPC_FilterValue, + 1, + 203, + 0, + 0, // Skip to: 82438 + /* 82235 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 82238 */ MCD_OPC_FilterValue, + 0, + 113, + 0, + 0, // Skip to: 82356 + /* 82243 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 82246 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 82268 + /* 82251 */ MCD_OPC_CheckPredicate, + 21, + 255, + 86, + 0, // Skip to: 104527 + /* 82256 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 248, + 86, + 0, // Skip to: 104527 + /* 82263 */ MCD_OPC_Decode, + 153, + 27, + 220, + 2, // Opcode: MLAv4i16_indexed + /* 82268 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 82290 + /* 82273 */ MCD_OPC_CheckPredicate, + 21, + 233, + 86, + 0, // Skip to: 104527 + /* 82278 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 226, + 86, + 0, // Skip to: 104527 + /* 82285 */ MCD_OPC_Decode, + 214, + 43, + 133, + 3, // Opcode: UMLALv4i16_indexed + /* 82290 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 82312 + /* 82295 */ MCD_OPC_CheckPredicate, + 21, + 211, + 86, + 0, // Skip to: 104527 + /* 82300 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 204, + 86, + 0, // Skip to: 104527 + /* 82307 */ MCD_OPC_Decode, + 170, + 27, + 220, + 2, // Opcode: MLSv4i16_indexed + /* 82312 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 82334 + /* 82317 */ MCD_OPC_CheckPredicate, + 21, + 189, + 86, + 0, // Skip to: 104527 + /* 82322 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 182, + 86, + 0, // Skip to: 104527 + /* 82329 */ MCD_OPC_Decode, + 234, + 43, + 133, + 3, // Opcode: UMLSLv4i16_indexed + /* 82334 */ MCD_OPC_FilterValue, + 5, + 172, + 86, + 0, // Skip to: 104527 + /* 82339 */ MCD_OPC_CheckPredicate, + 21, + 167, + 86, + 0, // Skip to: 104527 + /* 82344 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 160, + 86, + 0, // Skip to: 104527 + /* 82351 */ MCD_OPC_Decode, + 150, + 44, + 134, + 3, // Opcode: UMULLv4i16_indexed + /* 82356 */ MCD_OPC_FilterValue, + 1, + 150, + 86, + 0, // Skip to: 104527 + /* 82361 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 82364 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 82386 + /* 82369 */ MCD_OPC_CheckPredicate, + 29, + 137, + 86, + 0, // Skip to: 104527 + /* 82374 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 130, + 86, + 0, // Skip to: 104527 + /* 82381 */ MCD_OPC_Decode, + 238, + 13, + 135, + 3, // Opcode: FCMLAv4f16_indexed + /* 82386 */ MCD_OPC_FilterValue, + 1, + 120, + 86, + 0, // Skip to: 104527 + /* 82391 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 82394 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 82416 + /* 82399 */ MCD_OPC_CheckPredicate, + 28, + 107, + 86, + 0, // Skip to: 104527 + /* 82404 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 100, + 86, + 0, // Skip to: 104527 + /* 82411 */ MCD_OPC_Decode, + 205, + 34, + 220, + 2, // Opcode: SQRDMLAHv4i16_indexed + /* 82416 */ MCD_OPC_FilterValue, + 3, + 90, + 86, + 0, // Skip to: 104527 + /* 82421 */ MCD_OPC_CheckPredicate, + 28, + 85, + 86, + 0, // Skip to: 104527 + /* 82426 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 78, + 86, + 0, // Skip to: 104527 + /* 82433 */ MCD_OPC_Decode, + 224, + 34, + 220, + 2, // Opcode: SQRDMLSHv4i16_indexed + /* 82438 */ MCD_OPC_FilterValue, + 2, + 147, + 1, + 0, // Skip to: 82846 + /* 82443 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 82446 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 82468 + /* 82451 */ MCD_OPC_CheckPredicate, + 21, + 55, + 86, + 0, // Skip to: 104527 + /* 82456 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 48, + 86, + 0, // Skip to: 104527 + /* 82463 */ MCD_OPC_Decode, + 134, + 37, + 136, + 3, // Opcode: SSHRv2i64_shift + /* 82468 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 82490 + /* 82473 */ MCD_OPC_CheckPredicate, + 21, + 33, + 86, + 0, // Skip to: 104527 + /* 82478 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 26, + 86, + 0, // Skip to: 104527 + /* 82485 */ MCD_OPC_Decode, + 146, + 37, + 137, + 3, // Opcode: SSRAv2i64_shift + /* 82490 */ MCD_OPC_FilterValue, + 2, + 40, + 0, + 0, // Skip to: 82535 + /* 82495 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 82498 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 82513 + /* 82503 */ MCD_OPC_CheckPredicate, + 21, + 3, + 86, + 0, // Skip to: 104527 + /* 82508 */ MCD_OPC_Decode, + 172, + 32, + 243, + 2, // Opcode: SMLALv8i16_indexed + /* 82513 */ MCD_OPC_FilterValue, + 1, + 249, + 85, + 0, // Skip to: 104527 + /* 82518 */ MCD_OPC_CheckPredicate, + 21, + 244, + 85, + 0, // Skip to: 104527 + /* 82523 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 237, + 85, + 0, // Skip to: 104527 + /* 82530 */ MCD_OPC_Decode, + 222, + 36, + 136, + 3, // Opcode: SRSHRv2i64_shift + /* 82535 */ MCD_OPC_FilterValue, + 3, + 40, + 0, + 0, // Skip to: 82580 + /* 82540 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 82543 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 82558 + /* 82548 */ MCD_OPC_CheckPredicate, + 21, + 214, + 85, + 0, // Skip to: 104527 + /* 82553 */ MCD_OPC_Decode, + 208, + 33, + 243, + 2, // Opcode: SQDMLALv8i16_indexed + /* 82558 */ MCD_OPC_FilterValue, + 1, + 204, + 85, + 0, // Skip to: 104527 + /* 82563 */ MCD_OPC_CheckPredicate, + 21, + 199, + 85, + 0, // Skip to: 104527 + /* 82568 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 192, + 85, + 0, // Skip to: 104527 + /* 82575 */ MCD_OPC_Decode, + 234, + 36, + 137, + 3, // Opcode: SRSRAv2i64_shift + /* 82580 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 82602 + /* 82585 */ MCD_OPC_CheckPredicate, + 21, + 177, + 85, + 0, // Skip to: 104527 + /* 82590 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 170, + 85, + 0, // Skip to: 104527 + /* 82597 */ MCD_OPC_Decode, + 161, + 31, + 138, + 3, // Opcode: SHLv2i64_shift + /* 82602 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 82624 + /* 82607 */ MCD_OPC_CheckPredicate, + 21, + 155, + 85, + 0, // Skip to: 104527 + /* 82612 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 148, + 85, + 0, // Skip to: 104527 + /* 82619 */ MCD_OPC_Decode, + 192, + 32, + 243, + 2, // Opcode: SMLSLv8i16_indexed + /* 82624 */ MCD_OPC_FilterValue, + 7, + 40, + 0, + 0, // Skip to: 82669 + /* 82629 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 82632 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 82647 + /* 82637 */ MCD_OPC_CheckPredicate, + 21, + 125, + 85, + 0, // Skip to: 104527 + /* 82642 */ MCD_OPC_Decode, + 233, + 33, + 243, + 2, // Opcode: SQDMLSLv8i16_indexed + /* 82647 */ MCD_OPC_FilterValue, + 1, + 115, + 85, + 0, // Skip to: 104527 + /* 82652 */ MCD_OPC_CheckPredicate, + 21, + 110, + 85, + 0, // Skip to: 104527 + /* 82657 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 103, + 85, + 0, // Skip to: 104527 + /* 82664 */ MCD_OPC_Decode, + 209, + 35, + 138, + 3, // Opcode: SQSHLv2i64_shift + /* 82669 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 82691 + /* 82674 */ MCD_OPC_CheckPredicate, + 21, + 88, + 85, + 0, // Skip to: 104527 + /* 82679 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 81, + 85, + 0, // Skip to: 104527 + /* 82686 */ MCD_OPC_Decode, + 235, + 27, + 244, + 2, // Opcode: MULv8i16_indexed + /* 82691 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 82713 + /* 82696 */ MCD_OPC_CheckPredicate, + 21, + 66, + 85, + 0, // Skip to: 104527 + /* 82701 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 59, + 85, + 0, // Skip to: 104527 + /* 82708 */ MCD_OPC_Decode, + 238, + 32, + 244, + 2, // Opcode: SMULLv8i16_indexed + /* 82713 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 82735 + /* 82718 */ MCD_OPC_CheckPredicate, + 21, + 44, + 85, + 0, // Skip to: 104527 + /* 82723 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 37, + 85, + 0, // Skip to: 104527 + /* 82730 */ MCD_OPC_Decode, + 146, + 34, + 244, + 2, // Opcode: SQDMULLv8i16_indexed + /* 82735 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 82757 + /* 82740 */ MCD_OPC_CheckPredicate, + 21, + 22, + 85, + 0, // Skip to: 104527 + /* 82745 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 15, + 85, + 0, // Skip to: 104527 + /* 82752 */ MCD_OPC_Decode, + 253, + 33, + 244, + 2, // Opcode: SQDMULHv8i16_indexed + /* 82757 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 82779 + /* 82762 */ MCD_OPC_CheckPredicate, + 21, + 0, + 85, + 0, // Skip to: 104527 + /* 82767 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 249, + 84, + 0, // Skip to: 104527 + /* 82774 */ MCD_OPC_Decode, + 247, + 34, + 244, + 2, // Opcode: SQRDMULHv8i16_indexed + /* 82779 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 82801 + /* 82784 */ MCD_OPC_CheckPredicate, + 21, + 234, + 84, + 0, // Skip to: 104527 + /* 82789 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 227, + 84, + 0, // Skip to: 104527 + /* 82796 */ MCD_OPC_Decode, + 227, + 30, + 136, + 3, // Opcode: SCVTFv2i64_shift + /* 82801 */ MCD_OPC_FilterValue, + 15, + 217, + 84, + 0, // Skip to: 104527 + /* 82806 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 82809 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 82824 + /* 82814 */ MCD_OPC_CheckPredicate, + 30, + 204, + 84, + 0, // Skip to: 104527 + /* 82819 */ MCD_OPC_Decode, + 193, + 8, + 245, + 2, // Opcode: BF16DOTlanev8bf16 + /* 82824 */ MCD_OPC_FilterValue, + 1, + 194, + 84, + 0, // Skip to: 104527 + /* 82829 */ MCD_OPC_CheckPredicate, + 21, + 189, + 84, + 0, // Skip to: 104527 + /* 82834 */ MCD_OPC_CheckField, + 11, + 1, + 1, + 182, + 84, + 0, // Skip to: 104527 + /* 82841 */ MCD_OPC_Decode, + 199, + 15, + 136, + 3, // Opcode: FCVTZSv2i64_shift + /* 82846 */ MCD_OPC_FilterValue, + 3, + 172, + 84, + 0, // Skip to: 104527 + /* 82851 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 82854 */ MCD_OPC_FilterValue, + 0, + 147, + 0, + 0, // Skip to: 83006 + /* 82859 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 82862 */ MCD_OPC_FilterValue, + 0, + 78, + 0, + 0, // Skip to: 82945 + /* 82867 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 82870 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 82885 + /* 82875 */ MCD_OPC_CheckPredicate, + 21, + 143, + 84, + 0, // Skip to: 104527 + /* 82880 */ MCD_OPC_Decode, + 157, + 27, + 243, + 2, // Opcode: MLAv8i16_indexed + /* 82885 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 82900 + /* 82890 */ MCD_OPC_CheckPredicate, + 21, + 128, + 84, + 0, // Skip to: 104527 + /* 82895 */ MCD_OPC_Decode, + 218, + 43, + 243, + 2, // Opcode: UMLALv8i16_indexed + /* 82900 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 82915 + /* 82905 */ MCD_OPC_CheckPredicate, + 21, + 113, + 84, + 0, // Skip to: 104527 + /* 82910 */ MCD_OPC_Decode, + 174, + 27, + 243, + 2, // Opcode: MLSv8i16_indexed + /* 82915 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 82930 + /* 82920 */ MCD_OPC_CheckPredicate, + 21, + 98, + 84, + 0, // Skip to: 104527 + /* 82925 */ MCD_OPC_Decode, + 238, + 43, + 243, + 2, // Opcode: UMLSLv8i16_indexed + /* 82930 */ MCD_OPC_FilterValue, + 5, + 88, + 84, + 0, // Skip to: 104527 + /* 82935 */ MCD_OPC_CheckPredicate, + 21, + 83, + 84, + 0, // Skip to: 104527 + /* 82940 */ MCD_OPC_Decode, + 154, + 44, + 244, + 2, // Opcode: UMULLv8i16_indexed + /* 82945 */ MCD_OPC_FilterValue, + 1, + 73, + 84, + 0, // Skip to: 104527 + /* 82950 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 82953 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 82968 + /* 82958 */ MCD_OPC_CheckPredicate, + 29, + 60, + 84, + 0, // Skip to: 104527 + /* 82963 */ MCD_OPC_Decode, + 242, + 13, + 139, + 3, // Opcode: FCMLAv8f16_indexed + /* 82968 */ MCD_OPC_FilterValue, + 1, + 50, + 84, + 0, // Skip to: 104527 + /* 82973 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 82976 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 82991 + /* 82981 */ MCD_OPC_CheckPredicate, + 28, + 37, + 84, + 0, // Skip to: 104527 + /* 82986 */ MCD_OPC_Decode, + 209, + 34, + 243, + 2, // Opcode: SQRDMLAHv8i16_indexed + /* 82991 */ MCD_OPC_FilterValue, + 3, + 27, + 84, + 0, // Skip to: 104527 + /* 82996 */ MCD_OPC_CheckPredicate, + 28, + 22, + 84, + 0, // Skip to: 104527 + /* 83001 */ MCD_OPC_Decode, + 228, + 34, + 243, + 2, // Opcode: SQRDMLSHv8i16_indexed + /* 83006 */ MCD_OPC_FilterValue, + 1, + 12, + 84, + 0, // Skip to: 104527 + /* 83011 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 83014 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 83029 + /* 83019 */ MCD_OPC_CheckPredicate, + 21, + 255, + 83, + 0, // Skip to: 104527 + /* 83024 */ MCD_OPC_Decode, + 178, + 46, + 136, + 3, // Opcode: USHRv2i64_shift + /* 83029 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 83044 + /* 83034 */ MCD_OPC_CheckPredicate, + 21, + 240, + 83, + 0, // Skip to: 104527 + /* 83039 */ MCD_OPC_Decode, + 211, + 46, + 137, + 3, // Opcode: USRAv2i64_shift + /* 83044 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 83059 + /* 83049 */ MCD_OPC_CheckPredicate, + 21, + 225, + 83, + 0, // Skip to: 104527 + /* 83054 */ MCD_OPC_Decode, + 129, + 46, + 136, + 3, // Opcode: URSHRv2i64_shift + /* 83059 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 83074 + /* 83064 */ MCD_OPC_CheckPredicate, + 21, + 210, + 83, + 0, // Skip to: 104527 + /* 83069 */ MCD_OPC_Decode, + 144, + 46, + 137, + 3, // Opcode: URSRAv2i64_shift + /* 83074 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 83089 + /* 83079 */ MCD_OPC_CheckPredicate, + 21, + 195, + 83, + 0, // Skip to: 104527 + /* 83084 */ MCD_OPC_Decode, + 194, + 36, + 137, + 3, // Opcode: SRIv2i64_shift + /* 83089 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 83104 + /* 83094 */ MCD_OPC_CheckPredicate, + 21, + 180, + 83, + 0, // Skip to: 104527 + /* 83099 */ MCD_OPC_Decode, + 199, + 31, + 140, + 3, // Opcode: SLIv2i64_shift + /* 83104 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 83119 + /* 83109 */ MCD_OPC_CheckPredicate, + 21, + 165, + 83, + 0, // Skip to: 104527 + /* 83114 */ MCD_OPC_Decode, + 183, + 35, + 138, + 3, // Opcode: SQSHLUv2i64_shift + /* 83119 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 83134 + /* 83124 */ MCD_OPC_CheckPredicate, + 21, + 150, + 83, + 0, // Skip to: 104527 + /* 83129 */ MCD_OPC_Decode, + 155, + 45, + 138, + 3, // Opcode: UQSHLv2i64_shift + /* 83134 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 83149 + /* 83139 */ MCD_OPC_CheckPredicate, + 21, + 135, + 83, + 0, // Skip to: 104527 + /* 83144 */ MCD_OPC_Decode, + 216, + 42, + 136, + 3, // Opcode: UCVTFv2i64_shift + /* 83149 */ MCD_OPC_FilterValue, + 31, + 125, + 83, + 0, // Skip to: 104527 + /* 83154 */ MCD_OPC_CheckPredicate, + 21, + 120, + 83, + 0, // Skip to: 104527 + /* 83159 */ MCD_OPC_Decode, + 234, + 15, + 136, + 3, // Opcode: FCVTZUv2i64_shift + /* 83164 */ MCD_OPC_FilterValue, + 14, + 252, + 4, + 0, // Skip to: 84445 + /* 83169 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 83172 */ MCD_OPC_FilterValue, + 0, + 99, + 1, + 0, // Skip to: 83532 + /* 83177 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 83180 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 83202 + /* 83185 */ MCD_OPC_CheckPredicate, + 25, + 89, + 83, + 0, // Skip to: 104527 + /* 83190 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 82, + 83, + 0, // Skip to: 104527 + /* 83197 */ MCD_OPC_Decode, + 153, + 17, + 141, + 3, // Opcode: FMLALlanev4f16 + /* 83202 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 83224 + /* 83207 */ MCD_OPC_CheckPredicate, + 21, + 67, + 83, + 0, // Skip to: 104527 + /* 83212 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 60, + 83, + 0, // Skip to: 104527 + /* 83219 */ MCD_OPC_Decode, + 168, + 17, + 222, + 2, // Opcode: FMLAv2i32_indexed + /* 83224 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 83246 + /* 83229 */ MCD_OPC_CheckPredicate, + 21, + 45, + 83, + 0, // Skip to: 104527 + /* 83234 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 38, + 83, + 0, // Skip to: 104527 + /* 83241 */ MCD_OPC_Decode, + 166, + 32, + 142, + 3, // Opcode: SMLALv2i32_indexed + /* 83246 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 83268 + /* 83251 */ MCD_OPC_CheckPredicate, + 21, + 23, + 83, + 0, // Skip to: 104527 + /* 83256 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 16, + 83, + 0, // Skip to: 104527 + /* 83263 */ MCD_OPC_Decode, + 202, + 33, + 142, + 3, // Opcode: SQDMLALv2i32_indexed + /* 83268 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 83290 + /* 83273 */ MCD_OPC_CheckPredicate, + 25, + 1, + 83, + 0, // Skip to: 104527 + /* 83278 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 250, + 82, + 0, // Skip to: 104527 + /* 83285 */ MCD_OPC_Decode, + 184, + 17, + 141, + 3, // Opcode: FMLSLlanev4f16 + /* 83290 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 83312 + /* 83295 */ MCD_OPC_CheckPredicate, + 21, + 235, + 82, + 0, // Skip to: 104527 + /* 83300 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 228, + 82, + 0, // Skip to: 104527 + /* 83307 */ MCD_OPC_Decode, + 199, + 17, + 222, + 2, // Opcode: FMLSv2i32_indexed + /* 83312 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 83334 + /* 83317 */ MCD_OPC_CheckPredicate, + 21, + 213, + 82, + 0, // Skip to: 104527 + /* 83322 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 206, + 82, + 0, // Skip to: 104527 + /* 83329 */ MCD_OPC_Decode, + 186, + 32, + 142, + 3, // Opcode: SMLSLv2i32_indexed + /* 83334 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 83356 + /* 83339 */ MCD_OPC_CheckPredicate, + 21, + 191, + 82, + 0, // Skip to: 104527 + /* 83344 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 184, + 82, + 0, // Skip to: 104527 + /* 83351 */ MCD_OPC_Decode, + 227, + 33, + 142, + 3, // Opcode: SQDMLSLv2i32_indexed + /* 83356 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 83378 + /* 83361 */ MCD_OPC_CheckPredicate, + 21, + 169, + 82, + 0, // Skip to: 104527 + /* 83366 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 162, + 82, + 0, // Skip to: 104527 + /* 83373 */ MCD_OPC_Decode, + 229, + 27, + 143, + 3, // Opcode: MULv2i32_indexed + /* 83378 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 83400 + /* 83383 */ MCD_OPC_CheckPredicate, + 21, + 147, + 82, + 0, // Skip to: 104527 + /* 83388 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 140, + 82, + 0, // Skip to: 104527 + /* 83395 */ MCD_OPC_Decode, + 151, + 18, + 143, + 3, // Opcode: FMULv2i32_indexed + /* 83400 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 83422 + /* 83405 */ MCD_OPC_CheckPredicate, + 21, + 125, + 82, + 0, // Skip to: 104527 + /* 83410 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 118, + 82, + 0, // Skip to: 104527 + /* 83417 */ MCD_OPC_Decode, + 232, + 32, + 144, + 3, // Opcode: SMULLv2i32_indexed + /* 83422 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 83444 + /* 83427 */ MCD_OPC_CheckPredicate, + 21, + 103, + 82, + 0, // Skip to: 104527 + /* 83432 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 96, + 82, + 0, // Skip to: 104527 + /* 83439 */ MCD_OPC_Decode, + 140, + 34, + 144, + 3, // Opcode: SQDMULLv2i32_indexed + /* 83444 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 83466 + /* 83449 */ MCD_OPC_CheckPredicate, + 21, + 81, + 82, + 0, // Skip to: 104527 + /* 83454 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 74, + 82, + 0, // Skip to: 104527 + /* 83461 */ MCD_OPC_Decode, + 247, + 33, + 143, + 3, // Opcode: SQDMULHv2i32_indexed + /* 83466 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 83488 + /* 83471 */ MCD_OPC_CheckPredicate, + 21, + 59, + 82, + 0, // Skip to: 104527 + /* 83476 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 52, + 82, + 0, // Skip to: 104527 + /* 83483 */ MCD_OPC_Decode, + 241, + 34, + 143, + 3, // Opcode: SQRDMULHv2i32_indexed + /* 83488 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 83510 + /* 83493 */ MCD_OPC_CheckPredicate, + 32, + 37, + 82, + 0, // Skip to: 104527 + /* 83498 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 30, + 82, + 0, // Skip to: 104527 + /* 83505 */ MCD_OPC_Decode, + 245, + 30, + 222, + 2, // Opcode: SDOTlanev8i8 + /* 83510 */ MCD_OPC_FilterValue, + 15, + 20, + 82, + 0, // Skip to: 104527 + /* 83515 */ MCD_OPC_CheckPredicate, + 33, + 15, + 82, + 0, // Skip to: 104527 + /* 83520 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 8, + 82, + 0, // Skip to: 104527 + /* 83527 */ MCD_OPC_Decode, + 152, + 46, + 222, + 2, // Opcode: USDOTlanev8i8 + /* 83532 */ MCD_OPC_FilterValue, + 1, + 245, + 0, + 0, // Skip to: 83782 + /* 83537 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 83540 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 83562 + /* 83545 */ MCD_OPC_CheckPredicate, + 21, + 241, + 81, + 0, // Skip to: 104527 + /* 83550 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 234, + 81, + 0, // Skip to: 104527 + /* 83557 */ MCD_OPC_Decode, + 151, + 27, + 222, + 2, // Opcode: MLAv2i32_indexed + /* 83562 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 83584 + /* 83567 */ MCD_OPC_CheckPredicate, + 21, + 219, + 81, + 0, // Skip to: 104527 + /* 83572 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 212, + 81, + 0, // Skip to: 104527 + /* 83579 */ MCD_OPC_Decode, + 212, + 43, + 142, + 3, // Opcode: UMLALv2i32_indexed + /* 83584 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 83606 + /* 83589 */ MCD_OPC_CheckPredicate, + 21, + 197, + 81, + 0, // Skip to: 104527 + /* 83594 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 190, + 81, + 0, // Skip to: 104527 + /* 83601 */ MCD_OPC_Decode, + 168, + 27, + 222, + 2, // Opcode: MLSv2i32_indexed + /* 83606 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 83628 + /* 83611 */ MCD_OPC_CheckPredicate, + 21, + 175, + 81, + 0, // Skip to: 104527 + /* 83616 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 168, + 81, + 0, // Skip to: 104527 + /* 83623 */ MCD_OPC_Decode, + 232, + 43, + 142, + 3, // Opcode: UMLSLv2i32_indexed + /* 83628 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 83650 + /* 83633 */ MCD_OPC_CheckPredicate, + 25, + 153, + 81, + 0, // Skip to: 104527 + /* 83638 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 146, + 81, + 0, // Skip to: 104527 + /* 83645 */ MCD_OPC_Decode, + 145, + 17, + 141, + 3, // Opcode: FMLAL2lanev4f16 + /* 83650 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 83672 + /* 83655 */ MCD_OPC_CheckPredicate, + 21, + 131, + 81, + 0, // Skip to: 104527 + /* 83660 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 124, + 81, + 0, // Skip to: 104527 + /* 83667 */ MCD_OPC_Decode, + 254, + 17, + 143, + 3, // Opcode: FMULXv2i32_indexed + /* 83672 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 83694 + /* 83677 */ MCD_OPC_CheckPredicate, + 21, + 109, + 81, + 0, // Skip to: 104527 + /* 83682 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 102, + 81, + 0, // Skip to: 104527 + /* 83689 */ MCD_OPC_Decode, + 148, + 44, + 144, + 3, // Opcode: UMULLv2i32_indexed + /* 83694 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 83716 + /* 83699 */ MCD_OPC_CheckPredicate, + 25, + 87, + 81, + 0, // Skip to: 104527 + /* 83704 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 80, + 81, + 0, // Skip to: 104527 + /* 83711 */ MCD_OPC_Decode, + 176, + 17, + 141, + 3, // Opcode: FMLSL2lanev4f16 + /* 83716 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 83738 + /* 83721 */ MCD_OPC_CheckPredicate, + 28, + 65, + 81, + 0, // Skip to: 104527 + /* 83726 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 58, + 81, + 0, // Skip to: 104527 + /* 83733 */ MCD_OPC_Decode, + 203, + 34, + 222, + 2, // Opcode: SQRDMLAHv2i32_indexed + /* 83738 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 83760 + /* 83743 */ MCD_OPC_CheckPredicate, + 32, + 43, + 81, + 0, // Skip to: 104527 + /* 83748 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 36, + 81, + 0, // Skip to: 104527 + /* 83755 */ MCD_OPC_Decode, + 235, + 42, + 222, + 2, // Opcode: UDOTlanev8i8 + /* 83760 */ MCD_OPC_FilterValue, + 15, + 26, + 81, + 0, // Skip to: 104527 + /* 83765 */ MCD_OPC_CheckPredicate, + 28, + 21, + 81, + 0, // Skip to: 104527 + /* 83770 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 14, + 81, + 0, // Skip to: 104527 + /* 83777 */ MCD_OPC_Decode, + 222, + 34, + 222, + 2, // Opcode: SQRDMLSHv2i32_indexed + /* 83782 */ MCD_OPC_FilterValue, + 2, + 99, + 1, + 0, // Skip to: 84142 + /* 83787 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 83790 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 83812 + /* 83795 */ MCD_OPC_CheckPredicate, + 25, + 247, + 80, + 0, // Skip to: 104527 + /* 83800 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 240, + 80, + 0, // Skip to: 104527 + /* 83807 */ MCD_OPC_Decode, + 154, + 17, + 145, + 3, // Opcode: FMLALlanev8f16 + /* 83812 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 83834 + /* 83817 */ MCD_OPC_CheckPredicate, + 21, + 225, + 80, + 0, // Skip to: 104527 + /* 83822 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 218, + 80, + 0, // Skip to: 104527 + /* 83829 */ MCD_OPC_Decode, + 173, + 17, + 245, + 2, // Opcode: FMLAv4i32_indexed + /* 83834 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 83856 + /* 83839 */ MCD_OPC_CheckPredicate, + 21, + 203, + 80, + 0, // Skip to: 104527 + /* 83844 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 196, + 80, + 0, // Skip to: 104527 + /* 83851 */ MCD_OPC_Decode, + 170, + 32, + 245, + 2, // Opcode: SMLALv4i32_indexed + /* 83856 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 83878 + /* 83861 */ MCD_OPC_CheckPredicate, + 21, + 181, + 80, + 0, // Skip to: 104527 + /* 83866 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 174, + 80, + 0, // Skip to: 104527 + /* 83873 */ MCD_OPC_Decode, + 206, + 33, + 245, + 2, // Opcode: SQDMLALv4i32_indexed + /* 83878 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 83900 + /* 83883 */ MCD_OPC_CheckPredicate, + 25, + 159, + 80, + 0, // Skip to: 104527 + /* 83888 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 152, + 80, + 0, // Skip to: 104527 + /* 83895 */ MCD_OPC_Decode, + 185, + 17, + 145, + 3, // Opcode: FMLSLlanev8f16 + /* 83900 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 83922 + /* 83905 */ MCD_OPC_CheckPredicate, + 21, + 137, + 80, + 0, // Skip to: 104527 + /* 83910 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 130, + 80, + 0, // Skip to: 104527 + /* 83917 */ MCD_OPC_Decode, + 204, + 17, + 245, + 2, // Opcode: FMLSv4i32_indexed + /* 83922 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 83944 + /* 83927 */ MCD_OPC_CheckPredicate, + 21, + 115, + 80, + 0, // Skip to: 104527 + /* 83932 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 108, + 80, + 0, // Skip to: 104527 + /* 83939 */ MCD_OPC_Decode, + 190, + 32, + 245, + 2, // Opcode: SMLSLv4i32_indexed + /* 83944 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 83966 + /* 83949 */ MCD_OPC_CheckPredicate, + 21, + 93, + 80, + 0, // Skip to: 104527 + /* 83954 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 86, + 80, + 0, // Skip to: 104527 + /* 83961 */ MCD_OPC_Decode, + 231, + 33, + 245, + 2, // Opcode: SQDMLSLv4i32_indexed + /* 83966 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 83988 + /* 83971 */ MCD_OPC_CheckPredicate, + 21, + 71, + 80, + 0, // Skip to: 104527 + /* 83976 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 64, + 80, + 0, // Skip to: 104527 + /* 83983 */ MCD_OPC_Decode, + 233, + 27, + 146, + 3, // Opcode: MULv4i32_indexed + /* 83988 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 84010 + /* 83993 */ MCD_OPC_CheckPredicate, + 21, + 49, + 80, + 0, // Skip to: 104527 + /* 83998 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 42, + 80, + 0, // Skip to: 104527 + /* 84005 */ MCD_OPC_Decode, + 156, + 18, + 146, + 3, // Opcode: FMULv4i32_indexed + /* 84010 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 84032 + /* 84015 */ MCD_OPC_CheckPredicate, + 21, + 27, + 80, + 0, // Skip to: 104527 + /* 84020 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 20, + 80, + 0, // Skip to: 104527 + /* 84027 */ MCD_OPC_Decode, + 236, + 32, + 146, + 3, // Opcode: SMULLv4i32_indexed + /* 84032 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 84054 + /* 84037 */ MCD_OPC_CheckPredicate, + 21, + 5, + 80, + 0, // Skip to: 104527 + /* 84042 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 254, + 79, + 0, // Skip to: 104527 + /* 84049 */ MCD_OPC_Decode, + 144, + 34, + 146, + 3, // Opcode: SQDMULLv4i32_indexed + /* 84054 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 84076 + /* 84059 */ MCD_OPC_CheckPredicate, + 21, + 239, + 79, + 0, // Skip to: 104527 + /* 84064 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 232, + 79, + 0, // Skip to: 104527 + /* 84071 */ MCD_OPC_Decode, + 251, + 33, + 146, + 3, // Opcode: SQDMULHv4i32_indexed + /* 84076 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 84098 + /* 84081 */ MCD_OPC_CheckPredicate, + 21, + 217, + 79, + 0, // Skip to: 104527 + /* 84086 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 210, + 79, + 0, // Skip to: 104527 + /* 84093 */ MCD_OPC_Decode, + 245, + 34, + 146, + 3, // Opcode: SQRDMULHv4i32_indexed + /* 84098 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 84120 + /* 84103 */ MCD_OPC_CheckPredicate, + 32, + 195, + 79, + 0, // Skip to: 104527 + /* 84108 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 188, + 79, + 0, // Skip to: 104527 + /* 84115 */ MCD_OPC_Decode, + 244, + 30, + 245, + 2, // Opcode: SDOTlanev16i8 + /* 84120 */ MCD_OPC_FilterValue, + 15, + 178, + 79, + 0, // Skip to: 104527 + /* 84125 */ MCD_OPC_CheckPredicate, + 33, + 173, + 79, + 0, // Skip to: 104527 + /* 84130 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 166, + 79, + 0, // Skip to: 104527 + /* 84137 */ MCD_OPC_Decode, + 151, + 46, + 245, + 2, // Opcode: USDOTlanev16i8 + /* 84142 */ MCD_OPC_FilterValue, + 3, + 156, + 79, + 0, // Skip to: 104527 + /* 84147 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 84150 */ MCD_OPC_FilterValue, + 0, + 179, + 0, + 0, // Skip to: 84334 + /* 84155 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 84158 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 84180 + /* 84163 */ MCD_OPC_CheckPredicate, + 21, + 135, + 79, + 0, // Skip to: 104527 + /* 84168 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 128, + 79, + 0, // Skip to: 104527 + /* 84175 */ MCD_OPC_Decode, + 155, + 27, + 245, + 2, // Opcode: MLAv4i32_indexed + /* 84180 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 84202 + /* 84185 */ MCD_OPC_CheckPredicate, + 21, + 113, + 79, + 0, // Skip to: 104527 + /* 84190 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 106, + 79, + 0, // Skip to: 104527 + /* 84197 */ MCD_OPC_Decode, + 216, + 43, + 245, + 2, // Opcode: UMLALv4i32_indexed + /* 84202 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 84224 + /* 84207 */ MCD_OPC_CheckPredicate, + 21, + 91, + 79, + 0, // Skip to: 104527 + /* 84212 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 84, + 79, + 0, // Skip to: 104527 + /* 84219 */ MCD_OPC_Decode, + 172, + 27, + 245, + 2, // Opcode: MLSv4i32_indexed + /* 84224 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 84246 + /* 84229 */ MCD_OPC_CheckPredicate, + 21, + 69, + 79, + 0, // Skip to: 104527 + /* 84234 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 62, + 79, + 0, // Skip to: 104527 + /* 84241 */ MCD_OPC_Decode, + 236, + 43, + 245, + 2, // Opcode: UMLSLv4i32_indexed + /* 84246 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 84268 + /* 84251 */ MCD_OPC_CheckPredicate, + 25, + 47, + 79, + 0, // Skip to: 104527 + /* 84256 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 40, + 79, + 0, // Skip to: 104527 + /* 84263 */ MCD_OPC_Decode, + 146, + 17, + 145, + 3, // Opcode: FMLAL2lanev8f16 + /* 84268 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 84290 + /* 84273 */ MCD_OPC_CheckPredicate, + 21, + 25, + 79, + 0, // Skip to: 104527 + /* 84278 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 18, + 79, + 0, // Skip to: 104527 + /* 84285 */ MCD_OPC_Decode, + 152, + 44, + 146, + 3, // Opcode: UMULLv4i32_indexed + /* 84290 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 84312 + /* 84295 */ MCD_OPC_CheckPredicate, + 25, + 3, + 79, + 0, // Skip to: 104527 + /* 84300 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 252, + 78, + 0, // Skip to: 104527 + /* 84307 */ MCD_OPC_Decode, + 177, + 17, + 145, + 3, // Opcode: FMLSL2lanev8f16 + /* 84312 */ MCD_OPC_FilterValue, + 7, + 242, + 78, + 0, // Skip to: 104527 + /* 84317 */ MCD_OPC_CheckPredicate, + 32, + 237, + 78, + 0, // Skip to: 104527 + /* 84322 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 230, + 78, + 0, // Skip to: 104527 + /* 84329 */ MCD_OPC_Decode, + 234, + 42, + 245, + 2, // Opcode: UDOTlanev16i8 + /* 84334 */ MCD_OPC_FilterValue, + 1, + 220, + 78, + 0, // Skip to: 104527 + /* 84339 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 84342 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 84371 + /* 84347 */ MCD_OPC_CheckPredicate, + 34, + 207, + 78, + 0, // Skip to: 104527 + /* 84352 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 200, + 78, + 0, // Skip to: 104527 + /* 84359 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 193, + 78, + 0, // Skip to: 104527 + /* 84366 */ MCD_OPC_Decode, + 240, + 13, + 147, + 3, // Opcode: FCMLAv4f32_indexed + /* 84371 */ MCD_OPC_FilterValue, + 1, + 183, + 78, + 0, // Skip to: 104527 + /* 84376 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 84379 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 84401 + /* 84384 */ MCD_OPC_CheckPredicate, + 21, + 170, + 78, + 0, // Skip to: 104527 + /* 84389 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 163, + 78, + 0, // Skip to: 104527 + /* 84396 */ MCD_OPC_Decode, + 131, + 18, + 146, + 3, // Opcode: FMULXv4i32_indexed + /* 84401 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 84423 + /* 84406 */ MCD_OPC_CheckPredicate, + 28, + 148, + 78, + 0, // Skip to: 104527 + /* 84411 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 141, + 78, + 0, // Skip to: 104527 + /* 84418 */ MCD_OPC_Decode, + 207, + 34, + 245, + 2, // Opcode: SQRDMLAHv4i32_indexed + /* 84423 */ MCD_OPC_FilterValue, + 3, + 131, + 78, + 0, // Skip to: 104527 + /* 84428 */ MCD_OPC_CheckPredicate, + 28, + 126, + 78, + 0, // Skip to: 104527 + /* 84433 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 119, + 78, + 0, // Skip to: 104527 + /* 84440 */ MCD_OPC_Decode, + 226, + 34, + 245, + 2, // Opcode: SQRDMLSHv4i32_indexed + /* 84445 */ MCD_OPC_FilterValue, + 15, + 109, + 78, + 0, // Skip to: 104527 + /* 84450 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 84453 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 84489 + /* 84458 */ MCD_OPC_CheckPredicate, + 21, + 96, + 78, + 0, // Skip to: 104527 + /* 84463 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 89, + 78, + 0, // Skip to: 104527 + /* 84470 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 82, + 78, + 0, // Skip to: 104527 + /* 84477 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 75, + 78, + 0, // Skip to: 104527 + /* 84484 */ MCD_OPC_Decode, + 169, + 17, + 148, + 3, // Opcode: FMLAv2i64_indexed + /* 84489 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 84525 + /* 84494 */ MCD_OPC_CheckPredicate, + 21, + 60, + 78, + 0, // Skip to: 104527 + /* 84499 */ MCD_OPC_CheckField, + 29, + 3, + 2, + 53, + 78, + 0, // Skip to: 104527 + /* 84506 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 46, + 78, + 0, // Skip to: 104527 + /* 84513 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 39, + 78, + 0, // Skip to: 104527 + /* 84520 */ MCD_OPC_Decode, + 200, + 17, + 148, + 3, // Opcode: FMLSv2i64_indexed + /* 84525 */ MCD_OPC_FilterValue, + 9, + 61, + 0, + 0, // Skip to: 84591 + /* 84530 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 84533 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 84562 + /* 84538 */ MCD_OPC_CheckPredicate, + 21, + 16, + 78, + 0, // Skip to: 104527 + /* 84543 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 9, + 78, + 0, // Skip to: 104527 + /* 84550 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 2, + 78, + 0, // Skip to: 104527 + /* 84557 */ MCD_OPC_Decode, + 152, + 18, + 149, + 3, // Opcode: FMULv2i64_indexed + /* 84562 */ MCD_OPC_FilterValue, + 3, + 248, + 77, + 0, // Skip to: 104527 + /* 84567 */ MCD_OPC_CheckPredicate, + 21, + 243, + 77, + 0, // Skip to: 104527 + /* 84572 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 236, + 77, + 0, // Skip to: 104527 + /* 84579 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 229, + 77, + 0, // Skip to: 104527 + /* 84586 */ MCD_OPC_Decode, + 255, + 17, + 149, + 3, // Opcode: FMULXv2i64_indexed + /* 84591 */ MCD_OPC_FilterValue, + 15, + 219, + 77, + 0, // Skip to: 104527 + /* 84596 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 84599 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 84621 + /* 84604 */ MCD_OPC_CheckPredicate, + 30, + 206, + 77, + 0, // Skip to: 104527 + /* 84609 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 199, + 77, + 0, // Skip to: 104527 + /* 84616 */ MCD_OPC_Decode, + 204, + 8, + 243, + 2, // Opcode: BFMLALBIdx + /* 84621 */ MCD_OPC_FilterValue, + 2, + 189, + 77, + 0, // Skip to: 104527 + /* 84626 */ MCD_OPC_CheckPredicate, + 30, + 184, + 77, + 0, // Skip to: 104527 + /* 84631 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 177, + 77, + 0, // Skip to: 104527 + /* 84638 */ MCD_OPC_Decode, + 206, + 8, + 243, + 2, // Opcode: BFMLALTIdx + /* 84643 */ MCD_OPC_FilterValue, + 4, + 49, + 2, + 0, // Skip to: 85209 + /* 84648 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 84651 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 84679 + /* 84656 */ MCD_OPC_ExtractField, + 31, + 1, // Inst{31} ... + /* 84659 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 84669 + /* 84664 */ MCD_OPC_Decode, + 218, + 7, + 150, + 3, // Opcode: ADR + /* 84669 */ MCD_OPC_FilterValue, + 1, + 141, + 77, + 0, // Skip to: 104527 + /* 84674 */ MCD_OPC_Decode, + 219, + 7, + 150, + 3, // Opcode: ADRP + /* 84679 */ MCD_OPC_FilterValue, + 1, + 127, + 0, + 0, // Skip to: 84811 + /* 84684 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 84687 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 84697 + /* 84692 */ MCD_OPC_Decode, + 191, + 7, + 151, + 3, // Opcode: ADDWri + /* 84697 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 84707 + /* 84702 */ MCD_OPC_Decode, + 176, + 7, + 151, + 3, // Opcode: ADDSWri + /* 84707 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 84717 + /* 84712 */ MCD_OPC_Decode, + 197, + 40, + 151, + 3, // Opcode: SUBWri + /* 84717 */ MCD_OPC_FilterValue, + 3, + 5, + 0, + 0, // Skip to: 84727 + /* 84722 */ MCD_OPC_Decode, + 190, + 40, + 151, + 3, // Opcode: SUBSWri + /* 84727 */ MCD_OPC_FilterValue, + 4, + 27, + 0, + 0, // Skip to: 84759 + /* 84732 */ MCD_OPC_CheckPredicate, + 20, + 17, + 0, + 0, // Skip to: 84754 + /* 84737 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 10, + 0, + 0, // Skip to: 84754 + /* 84744 */ MCD_OPC_SoftFail, + 128, + 128, + 3 /* 0xc000 */, + 0, + /* 84749 */ MCD_OPC_Decode, + 148, + 7, + 152, + 3, // Opcode: ADDG + /* 84754 */ MCD_OPC_Decode, + 194, + 7, + 151, + 3, // Opcode: ADDXri + /* 84759 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 84769 + /* 84764 */ MCD_OPC_Decode, + 179, + 7, + 151, + 3, // Opcode: ADDSXri + /* 84769 */ MCD_OPC_FilterValue, + 6, + 27, + 0, + 0, // Skip to: 84801 + /* 84774 */ MCD_OPC_CheckPredicate, + 20, + 17, + 0, + 0, // Skip to: 84796 + /* 84779 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 10, + 0, + 0, // Skip to: 84796 + /* 84786 */ MCD_OPC_SoftFail, + 128, + 128, + 3 /* 0xc000 */, + 0, + /* 84791 */ MCD_OPC_Decode, + 167, + 40, + 152, + 3, // Opcode: SUBG + /* 84796 */ MCD_OPC_Decode, + 200, + 40, + 151, + 3, // Opcode: SUBXri + /* 84801 */ MCD_OPC_FilterValue, + 7, + 9, + 77, + 0, // Skip to: 104527 + /* 84806 */ MCD_OPC_Decode, + 193, + 40, + 151, + 3, // Opcode: SUBSXri + /* 84811 */ MCD_OPC_FilterValue, + 2, + 226, + 0, + 0, // Skip to: 85042 + /* 84816 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 84819 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 84854 + /* 84824 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 84827 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 84844 + /* 84832 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 232, + 76, + 0, // Skip to: 104527 + /* 84839 */ MCD_OPC_Decode, + 253, + 7, + 153, + 3, // Opcode: ANDWri + /* 84844 */ MCD_OPC_FilterValue, + 1, + 222, + 76, + 0, // Skip to: 104527 + /* 84849 */ MCD_OPC_Decode, + 188, + 27, + 154, + 3, // Opcode: MOVNWi + /* 84854 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 84871 + /* 84859 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 205, + 76, + 0, // Skip to: 104527 + /* 84866 */ MCD_OPC_Decode, + 147, + 28, + 153, + 3, // Opcode: ORRWri + /* 84871 */ MCD_OPC_FilterValue, + 2, + 30, + 0, + 0, // Skip to: 84906 + /* 84876 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 84879 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 84896 + /* 84884 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 180, + 76, + 0, // Skip to: 104527 + /* 84891 */ MCD_OPC_Decode, + 168, + 12, + 153, + 3, // Opcode: EORWri + /* 84896 */ MCD_OPC_FilterValue, + 1, + 170, + 76, + 0, // Skip to: 104527 + /* 84901 */ MCD_OPC_Decode, + 199, + 27, + 154, + 3, // Opcode: MOVZWi + /* 84906 */ MCD_OPC_FilterValue, + 3, + 30, + 0, + 0, // Skip to: 84941 + /* 84911 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 84914 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 84931 + /* 84919 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 145, + 76, + 0, // Skip to: 104527 + /* 84926 */ MCD_OPC_Decode, + 244, + 7, + 153, + 3, // Opcode: ANDSWri + /* 84931 */ MCD_OPC_FilterValue, + 1, + 135, + 76, + 0, // Skip to: 104527 + /* 84936 */ MCD_OPC_Decode, + 186, + 27, + 154, + 3, // Opcode: MOVKWi + /* 84941 */ MCD_OPC_FilterValue, + 4, + 23, + 0, + 0, // Skip to: 84969 + /* 84946 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 84949 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 84959 + /* 84954 */ MCD_OPC_Decode, + 255, + 7, + 153, + 3, // Opcode: ANDXri + /* 84959 */ MCD_OPC_FilterValue, + 1, + 107, + 76, + 0, // Skip to: 104527 + /* 84964 */ MCD_OPC_Decode, + 189, + 27, + 154, + 3, // Opcode: MOVNXi + /* 84969 */ MCD_OPC_FilterValue, + 5, + 12, + 0, + 0, // Skip to: 84986 + /* 84974 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 90, + 76, + 0, // Skip to: 104527 + /* 84981 */ MCD_OPC_Decode, + 149, + 28, + 153, + 3, // Opcode: ORRXri + /* 84986 */ MCD_OPC_FilterValue, + 6, + 23, + 0, + 0, // Skip to: 85014 + /* 84991 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 84994 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 85004 + /* 84999 */ MCD_OPC_Decode, + 170, + 12, + 153, + 3, // Opcode: EORXri + /* 85004 */ MCD_OPC_FilterValue, + 1, + 62, + 76, + 0, // Skip to: 104527 + /* 85009 */ MCD_OPC_Decode, + 200, + 27, + 154, + 3, // Opcode: MOVZXi + /* 85014 */ MCD_OPC_FilterValue, + 7, + 52, + 76, + 0, // Skip to: 104527 + /* 85019 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 85022 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 85032 + /* 85027 */ MCD_OPC_Decode, + 246, + 7, + 153, + 3, // Opcode: ANDSXri + /* 85032 */ MCD_OPC_FilterValue, + 1, + 34, + 76, + 0, // Skip to: 104527 + /* 85037 */ MCD_OPC_Decode, + 187, + 27, + 154, + 3, // Opcode: MOVKXi + /* 85042 */ MCD_OPC_FilterValue, + 3, + 24, + 76, + 0, // Skip to: 104527 + /* 85047 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 85050 */ MCD_OPC_FilterValue, + 0, + 37, + 0, + 0, // Skip to: 85092 + /* 85055 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 85058 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 85075 + /* 85063 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 1, + 76, + 0, // Skip to: 104527 + /* 85070 */ MCD_OPC_Decode, + 193, + 30, + 155, + 3, // Opcode: SBFMWri + /* 85075 */ MCD_OPC_FilterValue, + 4, + 247, + 75, + 0, // Skip to: 104527 + /* 85080 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 240, + 75, + 0, // Skip to: 104527 + /* 85087 */ MCD_OPC_Decode, + 194, + 12, + 156, + 3, // Opcode: EXTRWrri + /* 85092 */ MCD_OPC_FilterValue, + 1, + 19, + 0, + 0, // Skip to: 85116 + /* 85097 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 223, + 75, + 0, // Skip to: 104527 + /* 85104 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 216, + 75, + 0, // Skip to: 104527 + /* 85111 */ MCD_OPC_Decode, + 213, + 8, + 157, + 3, // Opcode: BFMWri + /* 85116 */ MCD_OPC_FilterValue, + 2, + 19, + 0, + 0, // Skip to: 85140 + /* 85121 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 199, + 75, + 0, // Skip to: 104527 + /* 85128 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 192, + 75, + 0, // Skip to: 104527 + /* 85135 */ MCD_OPC_Decode, + 182, + 42, + 155, + 3, // Opcode: UBFMWri + /* 85140 */ MCD_OPC_FilterValue, + 4, + 30, + 0, + 0, // Skip to: 85175 + /* 85145 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 85148 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 85158 + /* 85153 */ MCD_OPC_Decode, + 194, + 30, + 158, + 3, // Opcode: SBFMXri + /* 85158 */ MCD_OPC_FilterValue, + 3, + 164, + 75, + 0, // Skip to: 104527 + /* 85163 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 157, + 75, + 0, // Skip to: 104527 + /* 85170 */ MCD_OPC_Decode, + 195, + 12, + 159, + 3, // Opcode: EXTRXrri + /* 85175 */ MCD_OPC_FilterValue, + 5, + 12, + 0, + 0, // Skip to: 85192 + /* 85180 */ MCD_OPC_CheckField, + 22, + 2, + 1, + 140, + 75, + 0, // Skip to: 104527 + /* 85187 */ MCD_OPC_Decode, + 214, + 8, + 160, + 3, // Opcode: BFMXri + /* 85192 */ MCD_OPC_FilterValue, + 6, + 130, + 75, + 0, // Skip to: 104527 + /* 85197 */ MCD_OPC_CheckField, + 22, + 2, + 1, + 123, + 75, + 0, // Skip to: 104527 + /* 85204 */ MCD_OPC_Decode, + 183, + 42, + 158, + 3, // Opcode: UBFMXri + /* 85209 */ MCD_OPC_FilterValue, + 5, + 24, + 5, + 0, // Skip to: 86518 + /* 85214 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 85217 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 85227 + /* 85222 */ MCD_OPC_Decode, + 181, + 8, + 161, + 3, // Opcode: B + /* 85227 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 85275 + /* 85232 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 85235 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 85245 + /* 85240 */ MCD_OPC_Decode, + 174, + 9, + 162, + 3, // Opcode: CBZW + /* 85245 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 85255 + /* 85250 */ MCD_OPC_Decode, + 172, + 9, + 162, + 3, // Opcode: CBNZW + /* 85255 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 85265 + /* 85260 */ MCD_OPC_Decode, + 179, + 41, + 163, + 3, // Opcode: TBZW + /* 85265 */ MCD_OPC_FilterValue, + 3, + 57, + 75, + 0, // Skip to: 104527 + /* 85270 */ MCD_OPC_Decode, + 165, + 41, + 163, + 3, // Opcode: TBNZW + /* 85275 */ MCD_OPC_FilterValue, + 2, + 19, + 0, + 0, // Skip to: 85299 + /* 85280 */ MCD_OPC_CheckField, + 24, + 2, + 0, + 40, + 75, + 0, // Skip to: 104527 + /* 85287 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 33, + 75, + 0, // Skip to: 104527 + /* 85294 */ MCD_OPC_Decode, + 143, + 9, + 164, + 3, // Opcode: Bcc + /* 85299 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 85309 + /* 85304 */ MCD_OPC_Decode, + 240, + 8, + 161, + 3, // Opcode: BL + /* 85309 */ MCD_OPC_FilterValue, + 5, + 43, + 0, + 0, // Skip to: 85357 + /* 85314 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 85317 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 85327 + /* 85322 */ MCD_OPC_Decode, + 175, + 9, + 165, + 3, // Opcode: CBZX + /* 85327 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 85337 + /* 85332 */ MCD_OPC_Decode, + 173, + 9, + 165, + 3, // Opcode: CBNZX + /* 85337 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 85347 + /* 85342 */ MCD_OPC_Decode, + 180, + 41, + 163, + 3, // Opcode: TBZX + /* 85347 */ MCD_OPC_FilterValue, + 3, + 231, + 74, + 0, // Skip to: 104527 + /* 85352 */ MCD_OPC_Decode, + 166, + 41, + 163, + 3, // Opcode: TBNZX + /* 85357 */ MCD_OPC_FilterValue, + 6, + 221, + 74, + 0, // Skip to: 104527 + /* 85362 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 85365 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 85408 + /* 85370 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 85373 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 85383 + /* 85378 */ MCD_OPC_Decode, + 252, + 40, + 166, + 3, // Opcode: SVC + /* 85383 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 85393 + /* 85388 */ MCD_OPC_Decode, + 134, + 21, + 166, + 3, // Opcode: HVC + /* 85393 */ MCD_OPC_FilterValue, + 3, + 185, + 74, + 0, // Skip to: 104527 + /* 85398 */ MCD_OPC_CheckPredicate, + 35, + 180, + 74, + 0, // Skip to: 104527 + /* 85403 */ MCD_OPC_Decode, + 249, + 31, + 166, + 3, // Opcode: SMC + /* 85408 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 85425 + /* 85413 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 163, + 74, + 0, // Skip to: 104527 + /* 85420 */ MCD_OPC_Decode, + 253, + 8, + 166, + 3, // Opcode: BRK + /* 85425 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 85442 + /* 85430 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 146, + 74, + 0, // Skip to: 104527 + /* 85437 */ MCD_OPC_Decode, + 133, + 21, + 166, + 3, // Opcode: HLT + /* 85442 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 85464 + /* 85447 */ MCD_OPC_CheckPredicate, + 36, + 131, + 74, + 0, // Skip to: 104527 + /* 85452 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 124, + 74, + 0, // Skip to: 104527 + /* 85459 */ MCD_OPC_Decode, + 181, + 41, + 166, + 3, // Opcode: TCANCEL + /* 85464 */ MCD_OPC_FilterValue, + 5, + 38, + 0, + 0, // Skip to: 85507 + /* 85469 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 85472 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 85482 + /* 85477 */ MCD_OPC_Decode, + 230, + 11, + 166, + 3, // Opcode: DCPS1 + /* 85482 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 85492 + /* 85487 */ MCD_OPC_Decode, + 231, + 11, + 166, + 3, // Opcode: DCPS2 + /* 85492 */ MCD_OPC_FilterValue, + 3, + 86, + 74, + 0, // Skip to: 104527 + /* 85497 */ MCD_OPC_CheckPredicate, + 35, + 81, + 74, + 0, // Skip to: 104527 + /* 85502 */ MCD_OPC_Decode, + 232, + 11, + 166, + 3, // Opcode: DCPS3 + /* 85507 */ MCD_OPC_FilterValue, + 8, + 65, + 2, + 0, // Skip to: 86089 + /* 85512 */ MCD_OPC_ExtractField, + 19, + 2, // Inst{20-19} ... + /* 85515 */ MCD_OPC_FilterValue, + 0, + 10, + 2, + 0, // Skip to: 86042 + /* 85520 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 85523 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 85575 + /* 85528 */ MCD_OPC_ExtractField, + 5, + 7, // Inst{11-5} ... + /* 85531 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 85553 + /* 85536 */ MCD_OPC_CheckPredicate, + 37, + 42, + 74, + 0, // Skip to: 104527 + /* 85541 */ MCD_OPC_CheckField, + 16, + 3, + 3, + 35, + 74, + 0, // Skip to: 104527 + /* 85548 */ MCD_OPC_Decode, + 156, + 47, + 167, + 3, // Opcode: WFET + /* 85553 */ MCD_OPC_FilterValue, + 1, + 25, + 74, + 0, // Skip to: 104527 + /* 85558 */ MCD_OPC_CheckPredicate, + 37, + 20, + 74, + 0, // Skip to: 104527 + /* 85563 */ MCD_OPC_CheckField, + 16, + 3, + 3, + 13, + 74, + 0, // Skip to: 104527 + /* 85570 */ MCD_OPC_Decode, + 157, + 47, + 167, + 3, // Opcode: WFIT + /* 85575 */ MCD_OPC_FilterValue, + 2, + 169, + 0, + 0, // Skip to: 85749 + /* 85580 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 85583 */ MCD_OPC_FilterValue, + 31, + 251, + 73, + 0, // Skip to: 104527 + /* 85588 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 85591 */ MCD_OPC_FilterValue, + 3, + 243, + 73, + 0, // Skip to: 104527 + /* 85596 */ MCD_OPC_ExtractField, + 5, + 7, // Inst{11-5} ... + /* 85599 */ MCD_OPC_FilterValue, + 7, + 5, + 0, + 0, // Skip to: 85609 + /* 85604 */ MCD_OPC_Decode, + 239, + 47, + 133, + 1, // Opcode: XPACLRI + /* 85609 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 85619 + /* 85614 */ MCD_OPC_Decode, + 174, + 28, + 133, + 1, // Opcode: PACIA1716 + /* 85619 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 85629 + /* 85624 */ MCD_OPC_Decode, + 178, + 28, + 133, + 1, // Opcode: PACIB1716 + /* 85629 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 85639 + /* 85634 */ MCD_OPC_Decode, + 171, + 8, + 133, + 1, // Opcode: AUTIA1716 + /* 85639 */ MCD_OPC_FilterValue, + 14, + 5, + 0, + 0, // Skip to: 85649 + /* 85644 */ MCD_OPC_Decode, + 175, + 8, + 133, + 1, // Opcode: AUTIB1716 + /* 85649 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 85664 + /* 85654 */ MCD_OPC_CheckPredicate, + 38, + 85, + 0, + 0, // Skip to: 85744 + /* 85659 */ MCD_OPC_Decode, + 215, + 41, + 133, + 1, // Opcode: TSB + /* 85664 */ MCD_OPC_FilterValue, + 24, + 5, + 0, + 0, // Skip to: 85674 + /* 85669 */ MCD_OPC_Decode, + 176, + 28, + 133, + 1, // Opcode: PACIAZ + /* 85674 */ MCD_OPC_FilterValue, + 25, + 5, + 0, + 0, // Skip to: 85684 + /* 85679 */ MCD_OPC_Decode, + 175, + 28, + 133, + 1, // Opcode: PACIASP + /* 85684 */ MCD_OPC_FilterValue, + 26, + 5, + 0, + 0, // Skip to: 85694 + /* 85689 */ MCD_OPC_Decode, + 180, + 28, + 133, + 1, // Opcode: PACIBZ + /* 85694 */ MCD_OPC_FilterValue, + 27, + 5, + 0, + 0, // Skip to: 85704 + /* 85699 */ MCD_OPC_Decode, + 179, + 28, + 133, + 1, // Opcode: PACIBSP + /* 85704 */ MCD_OPC_FilterValue, + 28, + 5, + 0, + 0, // Skip to: 85714 + /* 85709 */ MCD_OPC_Decode, + 173, + 8, + 133, + 1, // Opcode: AUTIAZ + /* 85714 */ MCD_OPC_FilterValue, + 29, + 5, + 0, + 0, // Skip to: 85724 + /* 85719 */ MCD_OPC_Decode, + 172, + 8, + 133, + 1, // Opcode: AUTIASP + /* 85724 */ MCD_OPC_FilterValue, + 30, + 5, + 0, + 0, // Skip to: 85734 + /* 85729 */ MCD_OPC_Decode, + 177, + 8, + 133, + 1, // Opcode: AUTIBZ + /* 85734 */ MCD_OPC_FilterValue, + 31, + 5, + 0, + 0, // Skip to: 85744 + /* 85739 */ MCD_OPC_Decode, + 176, + 8, + 133, + 1, // Opcode: AUTIBSP + /* 85744 */ MCD_OPC_Decode, + 129, + 21, + 168, + 3, // Opcode: HINT + /* 85749 */ MCD_OPC_FilterValue, + 3, + 159, + 0, + 0, // Skip to: 85913 + /* 85754 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 85757 */ MCD_OPC_FilterValue, + 63, + 24, + 0, + 0, // Skip to: 85786 + /* 85762 */ MCD_OPC_CheckPredicate, + 39, + 72, + 73, + 0, // Skip to: 104527 + /* 85767 */ MCD_OPC_CheckField, + 16, + 3, + 3, + 65, + 73, + 0, // Skip to: 104527 + /* 85774 */ MCD_OPC_CheckField, + 8, + 2, + 2, + 58, + 73, + 0, // Skip to: 104527 + /* 85781 */ MCD_OPC_Decode, + 250, + 11, + 169, + 3, // Opcode: DSBnXS + /* 85786 */ MCD_OPC_FilterValue, + 95, + 12, + 0, + 0, // Skip to: 85803 + /* 85791 */ MCD_OPC_CheckField, + 16, + 3, + 3, + 41, + 73, + 0, // Skip to: 104527 + /* 85798 */ MCD_OPC_Decode, + 213, + 9, + 170, + 3, // Opcode: CLREX + /* 85803 */ MCD_OPC_FilterValue, + 127, + 24, + 0, + 0, // Skip to: 85832 + /* 85808 */ MCD_OPC_CheckPredicate, + 36, + 26, + 73, + 0, // Skip to: 104527 + /* 85813 */ MCD_OPC_CheckField, + 16, + 3, + 3, + 19, + 73, + 0, // Skip to: 104527 + /* 85820 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 12, + 73, + 0, // Skip to: 104527 + /* 85827 */ MCD_OPC_Decode, + 182, + 41, + 133, + 1, // Opcode: TCOMMIT + /* 85832 */ MCD_OPC_FilterValue, + 159, + 1, + 12, + 0, + 0, // Skip to: 85850 + /* 85838 */ MCD_OPC_CheckField, + 16, + 3, + 3, + 250, + 72, + 0, // Skip to: 104527 + /* 85845 */ MCD_OPC_Decode, + 249, + 11, + 170, + 3, // Opcode: DSB + /* 85850 */ MCD_OPC_FilterValue, + 191, + 1, + 12, + 0, + 0, // Skip to: 85868 + /* 85856 */ MCD_OPC_CheckField, + 16, + 3, + 3, + 232, + 72, + 0, // Skip to: 104527 + /* 85863 */ MCD_OPC_Decode, + 247, + 11, + 170, + 3, // Opcode: DMB + /* 85868 */ MCD_OPC_FilterValue, + 223, + 1, + 12, + 0, + 0, // Skip to: 85886 + /* 85874 */ MCD_OPC_CheckField, + 16, + 3, + 3, + 214, + 72, + 0, // Skip to: 104527 + /* 85881 */ MCD_OPC_Decode, + 192, + 21, + 170, + 3, // Opcode: ISB + /* 85886 */ MCD_OPC_FilterValue, + 255, + 1, + 203, + 72, + 0, // Skip to: 104527 + /* 85892 */ MCD_OPC_CheckPredicate, + 40, + 198, + 72, + 0, // Skip to: 104527 + /* 85897 */ MCD_OPC_CheckField, + 16, + 3, + 3, + 191, + 72, + 0, // Skip to: 104527 + /* 85904 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 85908 */ MCD_OPC_Decode, + 184, + 30, + 133, + 1, // Opcode: SB + /* 85913 */ MCD_OPC_FilterValue, + 4, + 177, + 72, + 0, // Skip to: 104527 + /* 85918 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 85921 */ MCD_OPC_FilterValue, + 31, + 169, + 72, + 0, // Skip to: 104527 + /* 85926 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 85929 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 85997 + /* 85934 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 85937 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 85959 + /* 85942 */ MCD_OPC_CheckPredicate, + 41, + 72, + 0, + 0, // Skip to: 86019 + /* 85947 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 65, + 0, + 0, // Skip to: 86019 + /* 85954 */ MCD_OPC_Decode, + 188, + 9, + 133, + 1, // Opcode: CFINV + /* 85959 */ MCD_OPC_FilterValue, + 1, + 14, + 0, + 0, // Skip to: 85978 + /* 85964 */ MCD_OPC_CheckPredicate, + 42, + 50, + 0, + 0, // Skip to: 86019 + /* 85969 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 85973 */ MCD_OPC_Decode, + 231, + 47, + 133, + 1, // Opcode: XAFLAG + /* 85978 */ MCD_OPC_FilterValue, + 2, + 36, + 0, + 0, // Skip to: 86019 + /* 85983 */ MCD_OPC_CheckPredicate, + 42, + 31, + 0, + 0, // Skip to: 86019 + /* 85988 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 85992 */ MCD_OPC_Decode, + 180, + 8, + 133, + 1, // Opcode: AXFLAG + /* 85997 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 86019 + /* 86002 */ MCD_OPC_CheckPredicate, + 0, + 12, + 0, + 0, // Skip to: 86019 + /* 86007 */ MCD_OPC_CheckField, + 5, + 3, + 3, + 5, + 0, + 0, // Skip to: 86019 + /* 86014 */ MCD_OPC_Decode, + 209, + 27, + 171, + 3, // Opcode: MSRpstatesvcrImm1 + /* 86019 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 8, + 0, + 0, // Skip to: 86034 + /* 86026 */ MCD_OPC_TryDecode, + 207, + 27, + 172, + 3, + 0, + 0, + 0, // Opcode: MSRpstateImm1, skip to: 86034 + /* 86034 */ MCD_OPC_TryDecode, + 208, + 27, + 172, + 3, + 53, + 72, + 0, // Opcode: MSRpstateImm4, skip to: 104527 + /* 86042 */ MCD_OPC_FilterValue, + 1, + 48, + 72, + 0, // Skip to: 104527 + /* 86047 */ MCD_OPC_ExtractField, + 0, + 19, // Inst{18-0} ... + /* 86050 */ MCD_OPC_FilterValue, + 159, + 229, + 5, + 10, + 0, + 0, // Skip to: 86067 + /* 86057 */ MCD_OPC_CheckPredicate, + 43, + 22, + 0, + 0, // Skip to: 86084 + /* 86062 */ MCD_OPC_Decode, + 251, + 8, + 133, + 1, // Opcode: BRB_IALL + /* 86067 */ MCD_OPC_FilterValue, + 191, + 229, + 5, + 10, + 0, + 0, // Skip to: 86084 + /* 86074 */ MCD_OPC_CheckPredicate, + 43, + 5, + 0, + 0, // Skip to: 86084 + /* 86079 */ MCD_OPC_Decode, + 252, + 8, + 133, + 1, // Opcode: BRB_INJ + /* 86084 */ MCD_OPC_Decode, + 148, + 41, + 173, + 3, // Opcode: SYSxt + /* 86089 */ MCD_OPC_FilterValue, + 9, + 53, + 0, + 0, // Skip to: 86147 + /* 86094 */ MCD_OPC_ExtractField, + 19, + 2, // Inst{20-19} ... + /* 86097 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 86137 + /* 86102 */ MCD_OPC_ExtractField, + 5, + 14, // Inst{18-5} ... + /* 86105 */ MCD_OPC_FilterValue, + 131, + 51, + 10, + 0, + 0, // Skip to: 86121 + /* 86111 */ MCD_OPC_CheckPredicate, + 36, + 235, + 71, + 0, // Skip to: 104527 + /* 86116 */ MCD_OPC_Decode, + 216, + 41, + 167, + 3, // Opcode: TSTART + /* 86121 */ MCD_OPC_FilterValue, + 139, + 51, + 224, + 71, + 0, // Skip to: 104527 + /* 86127 */ MCD_OPC_CheckPredicate, + 36, + 219, + 71, + 0, // Skip to: 104527 + /* 86132 */ MCD_OPC_Decode, + 217, + 41, + 167, + 3, // Opcode: TTEST + /* 86137 */ MCD_OPC_FilterValue, + 1, + 209, + 71, + 0, // Skip to: 104527 + /* 86142 */ MCD_OPC_Decode, + 147, + 41, + 174, + 3, // Opcode: SYSLxt + /* 86147 */ MCD_OPC_FilterValue, + 16, + 67, + 0, + 0, // Skip to: 86219 + /* 86152 */ MCD_OPC_ExtractField, + 10, + 11, // Inst{20-10} ... + /* 86155 */ MCD_OPC_FilterValue, + 192, + 15, + 12, + 0, + 0, // Skip to: 86173 + /* 86161 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 183, + 71, + 0, // Skip to: 104527 + /* 86168 */ MCD_OPC_Decode, + 246, + 8, + 175, + 3, // Opcode: BR + /* 86173 */ MCD_OPC_FilterValue, + 194, + 15, + 17, + 0, + 0, // Skip to: 86196 + /* 86179 */ MCD_OPC_CheckPredicate, + 44, + 167, + 71, + 0, // Skip to: 104527 + /* 86184 */ MCD_OPC_CheckField, + 0, + 5, + 31, + 160, + 71, + 0, // Skip to: 104527 + /* 86191 */ MCD_OPC_Decode, + 248, + 8, + 175, + 3, // Opcode: BRAAZ + /* 86196 */ MCD_OPC_FilterValue, + 195, + 15, + 149, + 71, + 0, // Skip to: 104527 + /* 86202 */ MCD_OPC_CheckPredicate, + 44, + 144, + 71, + 0, // Skip to: 104527 + /* 86207 */ MCD_OPC_CheckField, + 0, + 5, + 31, + 137, + 71, + 0, // Skip to: 104527 + /* 86214 */ MCD_OPC_Decode, + 250, + 8, + 175, + 3, // Opcode: BRABZ + /* 86219 */ MCD_OPC_FilterValue, + 17, + 67, + 0, + 0, // Skip to: 86291 + /* 86224 */ MCD_OPC_ExtractField, + 10, + 11, // Inst{20-10} ... + /* 86227 */ MCD_OPC_FilterValue, + 192, + 15, + 12, + 0, + 0, // Skip to: 86245 + /* 86233 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 111, + 71, + 0, // Skip to: 104527 + /* 86240 */ MCD_OPC_Decode, + 241, + 8, + 175, + 3, // Opcode: BLR + /* 86245 */ MCD_OPC_FilterValue, + 194, + 15, + 17, + 0, + 0, // Skip to: 86268 + /* 86251 */ MCD_OPC_CheckPredicate, + 44, + 95, + 71, + 0, // Skip to: 104527 + /* 86256 */ MCD_OPC_CheckField, + 0, + 5, + 31, + 88, + 71, + 0, // Skip to: 104527 + /* 86263 */ MCD_OPC_Decode, + 243, + 8, + 175, + 3, // Opcode: BLRAAZ + /* 86268 */ MCD_OPC_FilterValue, + 195, + 15, + 77, + 71, + 0, // Skip to: 104527 + /* 86274 */ MCD_OPC_CheckPredicate, + 44, + 72, + 71, + 0, // Skip to: 104527 + /* 86279 */ MCD_OPC_CheckField, + 0, + 5, + 31, + 65, + 71, + 0, // Skip to: 104527 + /* 86286 */ MCD_OPC_Decode, + 245, + 8, + 175, + 3, // Opcode: BLRABZ + /* 86291 */ MCD_OPC_FilterValue, + 18, + 69, + 0, + 0, // Skip to: 86365 + /* 86296 */ MCD_OPC_ExtractField, + 10, + 11, // Inst{20-10} ... + /* 86299 */ MCD_OPC_FilterValue, + 192, + 15, + 12, + 0, + 0, // Skip to: 86317 + /* 86305 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 39, + 71, + 0, // Skip to: 104527 + /* 86312 */ MCD_OPC_Decode, + 156, + 29, + 175, + 3, // Opcode: RET + /* 86317 */ MCD_OPC_FilterValue, + 194, + 15, + 18, + 0, + 0, // Skip to: 86341 + /* 86323 */ MCD_OPC_CheckPredicate, + 44, + 23, + 71, + 0, // Skip to: 104527 + /* 86328 */ MCD_OPC_CheckField, + 0, + 10, + 255, + 7, + 15, + 71, + 0, // Skip to: 104527 + /* 86336 */ MCD_OPC_Decode, + 157, + 29, + 133, + 1, // Opcode: RETAA + /* 86341 */ MCD_OPC_FilterValue, + 195, + 15, + 4, + 71, + 0, // Skip to: 104527 + /* 86347 */ MCD_OPC_CheckPredicate, + 44, + 255, + 70, + 0, // Skip to: 104527 + /* 86352 */ MCD_OPC_CheckField, + 0, + 10, + 255, + 7, + 247, + 70, + 0, // Skip to: 104527 + /* 86360 */ MCD_OPC_Decode, + 158, + 29, + 133, + 1, // Opcode: RETAB + /* 86365 */ MCD_OPC_FilterValue, + 20, + 49, + 0, + 0, // Skip to: 86419 + /* 86370 */ MCD_OPC_ExtractField, + 0, + 21, // Inst{20-0} ... + /* 86373 */ MCD_OPC_FilterValue, + 224, + 135, + 124, + 5, + 0, + 0, // Skip to: 86385 + /* 86380 */ MCD_OPC_Decode, + 181, + 12, + 133, + 1, // Opcode: ERET + /* 86385 */ MCD_OPC_FilterValue, + 255, + 151, + 124, + 10, + 0, + 0, // Skip to: 86402 + /* 86392 */ MCD_OPC_CheckPredicate, + 44, + 210, + 70, + 0, // Skip to: 104527 + /* 86397 */ MCD_OPC_Decode, + 182, + 12, + 133, + 1, // Opcode: ERETAA + /* 86402 */ MCD_OPC_FilterValue, + 255, + 159, + 124, + 198, + 70, + 0, // Skip to: 104527 + /* 86409 */ MCD_OPC_CheckPredicate, + 44, + 193, + 70, + 0, // Skip to: 104527 + /* 86414 */ MCD_OPC_Decode, + 183, + 12, + 133, + 1, // Opcode: ERETAB + /* 86419 */ MCD_OPC_FilterValue, + 21, + 14, + 0, + 0, // Skip to: 86438 + /* 86424 */ MCD_OPC_CheckField, + 0, + 21, + 224, + 135, + 124, + 174, + 70, + 0, // Skip to: 104527 + /* 86433 */ MCD_OPC_Decode, + 248, + 11, + 133, + 1, // Opcode: DRPS + /* 86438 */ MCD_OPC_FilterValue, + 24, + 35, + 0, + 0, // Skip to: 86478 + /* 86443 */ MCD_OPC_ExtractField, + 10, + 11, // Inst{20-10} ... + /* 86446 */ MCD_OPC_FilterValue, + 194, + 15, + 10, + 0, + 0, // Skip to: 86462 + /* 86452 */ MCD_OPC_CheckPredicate, + 44, + 150, + 70, + 0, // Skip to: 104527 + /* 86457 */ MCD_OPC_Decode, + 247, + 8, + 176, + 3, // Opcode: BRAA + /* 86462 */ MCD_OPC_FilterValue, + 195, + 15, + 139, + 70, + 0, // Skip to: 104527 + /* 86468 */ MCD_OPC_CheckPredicate, + 44, + 134, + 70, + 0, // Skip to: 104527 + /* 86473 */ MCD_OPC_Decode, + 249, + 8, + 176, + 3, // Opcode: BRAB + /* 86478 */ MCD_OPC_FilterValue, + 25, + 124, + 70, + 0, // Skip to: 104527 + /* 86483 */ MCD_OPC_ExtractField, + 10, + 11, // Inst{20-10} ... + /* 86486 */ MCD_OPC_FilterValue, + 194, + 15, + 10, + 0, + 0, // Skip to: 86502 + /* 86492 */ MCD_OPC_CheckPredicate, + 44, + 110, + 70, + 0, // Skip to: 104527 + /* 86497 */ MCD_OPC_Decode, + 242, + 8, + 176, + 3, // Opcode: BLRAA + /* 86502 */ MCD_OPC_FilterValue, + 195, + 15, + 99, + 70, + 0, // Skip to: 104527 + /* 86508 */ MCD_OPC_CheckPredicate, + 44, + 94, + 70, + 0, // Skip to: 104527 + /* 86513 */ MCD_OPC_Decode, + 244, + 8, + 176, + 3, // Opcode: BLRAB + /* 86518 */ MCD_OPC_FilterValue, + 6, + 45, + 26, + 0, // Skip to: 93224 + /* 86523 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 86526 */ MCD_OPC_FilterValue, + 0, + 180, + 1, + 0, // Skip to: 86967 + /* 86531 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 86534 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 86544 + /* 86539 */ MCD_OPC_Decode, + 218, + 25, + 162, + 3, // Opcode: LDRWl + /* 86544 */ MCD_OPC_FilterValue, + 1, + 91, + 0, + 0, // Skip to: 86640 + /* 86549 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 86552 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 86574 + /* 86557 */ MCD_OPC_CheckPredicate, + 45, + 45, + 70, + 0, // Skip to: 104527 + /* 86562 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 38, + 70, + 0, // Skip to: 104527 + /* 86569 */ MCD_OPC_Decode, + 176, + 39, + 177, + 3, // Opcode: STLURBi + /* 86574 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 86596 + /* 86579 */ MCD_OPC_CheckPredicate, + 45, + 23, + 70, + 0, // Skip to: 104527 + /* 86584 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 16, + 70, + 0, // Skip to: 104527 + /* 86591 */ MCD_OPC_Decode, + 146, + 24, + 177, + 3, // Opcode: LDAPURBi + /* 86596 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 86618 + /* 86601 */ MCD_OPC_CheckPredicate, + 45, + 1, + 70, + 0, // Skip to: 104527 + /* 86606 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 250, + 69, + 0, // Skip to: 104527 + /* 86613 */ MCD_OPC_Decode, + 149, + 24, + 177, + 3, // Opcode: LDAPURSBXi + /* 86618 */ MCD_OPC_FilterValue, + 6, + 240, + 69, + 0, // Skip to: 104527 + /* 86623 */ MCD_OPC_CheckPredicate, + 45, + 235, + 69, + 0, // Skip to: 104527 + /* 86628 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 228, + 69, + 0, // Skip to: 104527 + /* 86635 */ MCD_OPC_Decode, + 148, + 24, + 177, + 3, // Opcode: LDAPURSBWi + /* 86640 */ MCD_OPC_FilterValue, + 2, + 24, + 1, + 0, // Skip to: 86925 + /* 86645 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 86648 */ MCD_OPC_FilterValue, + 0, + 78, + 0, + 0, // Skip to: 86731 + /* 86653 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 86656 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 86673 + /* 86661 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 195, + 69, + 0, // Skip to: 104527 + /* 86668 */ MCD_OPC_Decode, + 146, + 7, + 178, + 3, // Opcode: ADCWr + /* 86673 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 86683 + /* 86678 */ MCD_OPC_Decode, + 218, + 11, + 179, + 3, // Opcode: CSELWr + /* 86683 */ MCD_OPC_FilterValue, + 6, + 175, + 69, + 0, // Skip to: 104527 + /* 86688 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 86691 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 86701 + /* 86696 */ MCD_OPC_Decode, + 218, + 26, + 178, + 3, // Opcode: LSLVWr + /* 86701 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 86716 + /* 86706 */ MCD_OPC_CheckPredicate, + 46, + 152, + 69, + 0, // Skip to: 104527 + /* 86711 */ MCD_OPC_Decode, + 210, + 11, + 178, + 3, // Opcode: CRC32Brr + /* 86716 */ MCD_OPC_FilterValue, + 5, + 142, + 69, + 0, // Skip to: 104527 + /* 86721 */ MCD_OPC_CheckPredicate, + 46, + 137, + 69, + 0, // Skip to: 104527 + /* 86726 */ MCD_OPC_Decode, + 211, + 11, + 178, + 3, // Opcode: CRC32CBrr + /* 86731 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 86797 + /* 86736 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 86739 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 86749 + /* 86744 */ MCD_OPC_Decode, + 220, + 11, + 179, + 3, // Opcode: CSINCWr + /* 86749 */ MCD_OPC_FilterValue, + 6, + 109, + 69, + 0, // Skip to: 104527 + /* 86754 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 86757 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 86767 + /* 86762 */ MCD_OPC_Decode, + 242, + 26, + 178, + 3, // Opcode: LSRVWr + /* 86767 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 86782 + /* 86772 */ MCD_OPC_CheckPredicate, + 46, + 86, + 69, + 0, // Skip to: 104527 + /* 86777 */ MCD_OPC_Decode, + 215, + 11, + 178, + 3, // Opcode: CRC32Hrr + /* 86782 */ MCD_OPC_FilterValue, + 5, + 76, + 69, + 0, // Skip to: 104527 + /* 86787 */ MCD_OPC_CheckPredicate, + 46, + 71, + 69, + 0, // Skip to: 104527 + /* 86792 */ MCD_OPC_Decode, + 212, + 11, + 178, + 3, // Opcode: CRC32CHrr + /* 86797 */ MCD_OPC_FilterValue, + 2, + 81, + 0, + 0, // Skip to: 86883 + /* 86802 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 86805 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 86822 + /* 86810 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 46, + 69, + 0, // Skip to: 104527 + /* 86817 */ MCD_OPC_Decode, + 226, + 42, + 178, + 3, // Opcode: UDIVWr + /* 86822 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 86839 + /* 86827 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 29, + 69, + 0, // Skip to: 104527 + /* 86834 */ MCD_OPC_Decode, + 146, + 8, + 178, + 3, // Opcode: ASRVWr + /* 86839 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 86861 + /* 86844 */ MCD_OPC_CheckPredicate, + 46, + 14, + 69, + 0, // Skip to: 104527 + /* 86849 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 7, + 69, + 0, // Skip to: 104527 + /* 86856 */ MCD_OPC_Decode, + 216, + 11, + 178, + 3, // Opcode: CRC32Wrr + /* 86861 */ MCD_OPC_FilterValue, + 5, + 253, + 68, + 0, // Skip to: 104527 + /* 86866 */ MCD_OPC_CheckPredicate, + 46, + 248, + 68, + 0, // Skip to: 104527 + /* 86871 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 241, + 68, + 0, // Skip to: 104527 + /* 86878 */ MCD_OPC_Decode, + 213, + 11, + 178, + 3, // Opcode: CRC32CWrr + /* 86883 */ MCD_OPC_FilterValue, + 3, + 231, + 68, + 0, // Skip to: 104527 + /* 86888 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 86891 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 86908 + /* 86896 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 216, + 68, + 0, // Skip to: 104527 + /* 86903 */ MCD_OPC_Decode, + 236, + 30, + 178, + 3, // Opcode: SDIVWr + /* 86908 */ MCD_OPC_FilterValue, + 2, + 206, + 68, + 0, // Skip to: 104527 + /* 86913 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 199, + 68, + 0, // Skip to: 104527 + /* 86920 */ MCD_OPC_Decode, + 192, + 29, + 178, + 3, // Opcode: RORVWr + /* 86925 */ MCD_OPC_FilterValue, + 3, + 189, + 68, + 0, // Skip to: 104527 + /* 86930 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 86933 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 86950 + /* 86938 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 174, + 68, + 0, // Skip to: 104527 + /* 86945 */ MCD_OPC_Decode, + 134, + 27, + 180, + 3, // Opcode: MADDWrrr + /* 86950 */ MCD_OPC_FilterValue, + 1, + 164, + 68, + 0, // Skip to: 104527 + /* 86955 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 157, + 68, + 0, // Skip to: 104527 + /* 86962 */ MCD_OPC_Decode, + 210, + 27, + 180, + 3, // Opcode: MSUBWrrr + /* 86967 */ MCD_OPC_FilterValue, + 1, + 176, + 4, + 0, // Skip to: 88172 + /* 86972 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 86975 */ MCD_OPC_FilterValue, + 0, + 244, + 0, + 0, // Skip to: 87224 + /* 86980 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 86983 */ MCD_OPC_FilterValue, + 0, + 156, + 0, + 0, // Skip to: 87144 + /* 86988 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 86991 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 87001 + /* 86996 */ MCD_OPC_Decode, + 145, + 40, + 177, + 3, // Opcode: STURBBi + /* 87001 */ MCD_OPC_FilterValue, + 1, + 113, + 68, + 0, // Skip to: 104527 + /* 87006 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 87009 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 87024 + /* 87014 */ MCD_OPC_CheckPredicate, + 18, + 100, + 68, + 0, // Skip to: 104527 + /* 87019 */ MCD_OPC_Decode, + 134, + 24, + 181, + 3, // Opcode: LDADDB + /* 87024 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 87039 + /* 87029 */ MCD_OPC_CheckPredicate, + 18, + 85, + 68, + 0, // Skip to: 104527 + /* 87034 */ MCD_OPC_Decode, + 173, + 24, + 181, + 3, // Opcode: LDCLRB + /* 87039 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 87054 + /* 87044 */ MCD_OPC_CheckPredicate, + 18, + 70, + 68, + 0, // Skip to: 104527 + /* 87049 */ MCD_OPC_Decode, + 189, + 24, + 181, + 3, // Opcode: LDEORB + /* 87054 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 87069 + /* 87059 */ MCD_OPC_CheckPredicate, + 18, + 55, + 68, + 0, // Skip to: 104527 + /* 87064 */ MCD_OPC_Decode, + 241, + 25, + 181, + 3, // Opcode: LDSETB + /* 87069 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 87084 + /* 87074 */ MCD_OPC_CheckPredicate, + 18, + 40, + 68, + 0, // Skip to: 104527 + /* 87079 */ MCD_OPC_Decode, + 129, + 26, + 181, + 3, // Opcode: LDSMAXB + /* 87084 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 87099 + /* 87089 */ MCD_OPC_CheckPredicate, + 18, + 25, + 68, + 0, // Skip to: 104527 + /* 87094 */ MCD_OPC_Decode, + 145, + 26, + 181, + 3, // Opcode: LDSMINB + /* 87099 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 87114 + /* 87104 */ MCD_OPC_CheckPredicate, + 18, + 10, + 68, + 0, // Skip to: 104527 + /* 87109 */ MCD_OPC_Decode, + 170, + 26, + 181, + 3, // Opcode: LDUMAXB + /* 87114 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 87129 + /* 87119 */ MCD_OPC_CheckPredicate, + 18, + 251, + 67, + 0, // Skip to: 104527 + /* 87124 */ MCD_OPC_Decode, + 186, + 26, + 181, + 3, // Opcode: LDUMINB + /* 87129 */ MCD_OPC_FilterValue, + 8, + 241, + 67, + 0, // Skip to: 104527 + /* 87134 */ MCD_OPC_CheckPredicate, + 18, + 236, + 67, + 0, // Skip to: 104527 + /* 87139 */ MCD_OPC_Decode, + 133, + 41, + 181, + 3, // Opcode: SWPB + /* 87144 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 87161 + /* 87149 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 219, + 67, + 0, // Skip to: 104527 + /* 87156 */ MCD_OPC_Decode, + 221, + 39, + 177, + 3, // Opcode: STRBBpost + /* 87161 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 87207 + /* 87166 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 87169 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 87179 + /* 87174 */ MCD_OPC_Decode, + 141, + 40, + 177, + 3, // Opcode: STTRBi + /* 87179 */ MCD_OPC_FilterValue, + 1, + 191, + 67, + 0, // Skip to: 104527 + /* 87184 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 87187 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 87197 + /* 87192 */ MCD_OPC_Decode, + 223, + 39, + 182, + 3, // Opcode: STRBBroW + /* 87197 */ MCD_OPC_FilterValue, + 3, + 173, + 67, + 0, // Skip to: 104527 + /* 87202 */ MCD_OPC_Decode, + 224, + 39, + 183, + 3, // Opcode: STRBBroX + /* 87207 */ MCD_OPC_FilterValue, + 3, + 163, + 67, + 0, // Skip to: 104527 + /* 87212 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 156, + 67, + 0, // Skip to: 104527 + /* 87219 */ MCD_OPC_Decode, + 222, + 39, + 177, + 3, // Opcode: STRBBpre + /* 87224 */ MCD_OPC_FilterValue, + 1, + 244, + 0, + 0, // Skip to: 87473 + /* 87229 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 87232 */ MCD_OPC_FilterValue, + 0, + 156, + 0, + 0, // Skip to: 87393 + /* 87237 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 87240 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 87250 + /* 87245 */ MCD_OPC_Decode, + 194, + 26, + 177, + 3, // Opcode: LDURBBi + /* 87250 */ MCD_OPC_FilterValue, + 1, + 120, + 67, + 0, // Skip to: 104527 + /* 87255 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 87258 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 87273 + /* 87263 */ MCD_OPC_CheckPredicate, + 18, + 107, + 67, + 0, // Skip to: 104527 + /* 87268 */ MCD_OPC_Decode, + 136, + 24, + 181, + 3, // Opcode: LDADDLB + /* 87273 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 87288 + /* 87278 */ MCD_OPC_CheckPredicate, + 18, + 92, + 67, + 0, // Skip to: 104527 + /* 87283 */ MCD_OPC_Decode, + 175, + 24, + 181, + 3, // Opcode: LDCLRLB + /* 87288 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 87303 + /* 87293 */ MCD_OPC_CheckPredicate, + 18, + 77, + 67, + 0, // Skip to: 104527 + /* 87298 */ MCD_OPC_Decode, + 191, + 24, + 181, + 3, // Opcode: LDEORLB + /* 87303 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 87318 + /* 87308 */ MCD_OPC_CheckPredicate, + 18, + 62, + 67, + 0, // Skip to: 104527 + /* 87313 */ MCD_OPC_Decode, + 243, + 25, + 181, + 3, // Opcode: LDSETLB + /* 87318 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 87333 + /* 87323 */ MCD_OPC_CheckPredicate, + 18, + 47, + 67, + 0, // Skip to: 104527 + /* 87328 */ MCD_OPC_Decode, + 131, + 26, + 181, + 3, // Opcode: LDSMAXLB + /* 87333 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 87348 + /* 87338 */ MCD_OPC_CheckPredicate, + 18, + 32, + 67, + 0, // Skip to: 104527 + /* 87343 */ MCD_OPC_Decode, + 147, + 26, + 181, + 3, // Opcode: LDSMINLB + /* 87348 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 87363 + /* 87353 */ MCD_OPC_CheckPredicate, + 18, + 17, + 67, + 0, // Skip to: 104527 + /* 87358 */ MCD_OPC_Decode, + 172, + 26, + 181, + 3, // Opcode: LDUMAXLB + /* 87363 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 87378 + /* 87368 */ MCD_OPC_CheckPredicate, + 18, + 2, + 67, + 0, // Skip to: 104527 + /* 87373 */ MCD_OPC_Decode, + 188, + 26, + 181, + 3, // Opcode: LDUMINLB + /* 87378 */ MCD_OPC_FilterValue, + 8, + 248, + 66, + 0, // Skip to: 104527 + /* 87383 */ MCD_OPC_CheckPredicate, + 18, + 243, + 66, + 0, // Skip to: 104527 + /* 87388 */ MCD_OPC_Decode, + 135, + 41, + 181, + 3, // Opcode: SWPLB + /* 87393 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 87410 + /* 87398 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 226, + 66, + 0, // Skip to: 104527 + /* 87405 */ MCD_OPC_Decode, + 154, + 25, + 177, + 3, // Opcode: LDRBBpost + /* 87410 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 87456 + /* 87415 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 87418 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 87428 + /* 87423 */ MCD_OPC_Decode, + 153, + 26, + 177, + 3, // Opcode: LDTRBi + /* 87428 */ MCD_OPC_FilterValue, + 1, + 198, + 66, + 0, // Skip to: 104527 + /* 87433 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 87436 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 87446 + /* 87441 */ MCD_OPC_Decode, + 156, + 25, + 182, + 3, // Opcode: LDRBBroW + /* 87446 */ MCD_OPC_FilterValue, + 3, + 180, + 66, + 0, // Skip to: 104527 + /* 87451 */ MCD_OPC_Decode, + 157, + 25, + 183, + 3, // Opcode: LDRBBroX + /* 87456 */ MCD_OPC_FilterValue, + 3, + 170, + 66, + 0, // Skip to: 104527 + /* 87461 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 163, + 66, + 0, // Skip to: 104527 + /* 87468 */ MCD_OPC_Decode, + 155, + 25, + 177, + 3, // Opcode: LDRBBpre + /* 87473 */ MCD_OPC_FilterValue, + 2, + 10, + 1, + 0, // Skip to: 87744 + /* 87478 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 87481 */ MCD_OPC_FilterValue, + 0, + 178, + 0, + 0, // Skip to: 87664 + /* 87486 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 87489 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 87499 + /* 87494 */ MCD_OPC_Decode, + 201, + 26, + 177, + 3, // Opcode: LDURSBXi + /* 87499 */ MCD_OPC_FilterValue, + 1, + 127, + 66, + 0, // Skip to: 104527 + /* 87504 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 87507 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 87522 + /* 87512 */ MCD_OPC_CheckPredicate, + 18, + 114, + 66, + 0, // Skip to: 104527 + /* 87517 */ MCD_OPC_Decode, + 254, + 23, + 181, + 3, // Opcode: LDADDAB + /* 87522 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 87537 + /* 87527 */ MCD_OPC_CheckPredicate, + 18, + 99, + 66, + 0, // Skip to: 104527 + /* 87532 */ MCD_OPC_Decode, + 165, + 24, + 181, + 3, // Opcode: LDCLRAB + /* 87537 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 87552 + /* 87542 */ MCD_OPC_CheckPredicate, + 18, + 84, + 66, + 0, // Skip to: 104527 + /* 87547 */ MCD_OPC_Decode, + 181, + 24, + 181, + 3, // Opcode: LDEORAB + /* 87552 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 87567 + /* 87557 */ MCD_OPC_CheckPredicate, + 18, + 69, + 66, + 0, // Skip to: 104527 + /* 87562 */ MCD_OPC_Decode, + 233, + 25, + 181, + 3, // Opcode: LDSETAB + /* 87567 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 87582 + /* 87572 */ MCD_OPC_CheckPredicate, + 18, + 54, + 66, + 0, // Skip to: 104527 + /* 87577 */ MCD_OPC_Decode, + 249, + 25, + 181, + 3, // Opcode: LDSMAXAB + /* 87582 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 87597 + /* 87587 */ MCD_OPC_CheckPredicate, + 18, + 39, + 66, + 0, // Skip to: 104527 + /* 87592 */ MCD_OPC_Decode, + 137, + 26, + 181, + 3, // Opcode: LDSMINAB + /* 87597 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 87612 + /* 87602 */ MCD_OPC_CheckPredicate, + 18, + 24, + 66, + 0, // Skip to: 104527 + /* 87607 */ MCD_OPC_Decode, + 162, + 26, + 181, + 3, // Opcode: LDUMAXAB + /* 87612 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 87627 + /* 87617 */ MCD_OPC_CheckPredicate, + 18, + 9, + 66, + 0, // Skip to: 104527 + /* 87622 */ MCD_OPC_Decode, + 178, + 26, + 181, + 3, // Opcode: LDUMINAB + /* 87627 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 87642 + /* 87632 */ MCD_OPC_CheckPredicate, + 18, + 250, + 65, + 0, // Skip to: 104527 + /* 87637 */ MCD_OPC_Decode, + 253, + 40, + 181, + 3, // Opcode: SWPAB + /* 87642 */ MCD_OPC_FilterValue, + 12, + 240, + 65, + 0, // Skip to: 104527 + /* 87647 */ MCD_OPC_CheckPredicate, + 47, + 235, + 65, + 0, // Skip to: 104527 + /* 87652 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 228, + 65, + 0, // Skip to: 104527 + /* 87659 */ MCD_OPC_Decode, + 142, + 24, + 184, + 3, // Opcode: LDAPRB + /* 87664 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 87681 + /* 87669 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 211, + 65, + 0, // Skip to: 104527 + /* 87676 */ MCD_OPC_Decode, + 191, + 25, + 177, + 3, // Opcode: LDRSBXpost + /* 87681 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 87727 + /* 87686 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 87689 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 87699 + /* 87694 */ MCD_OPC_Decode, + 156, + 26, + 177, + 3, // Opcode: LDTRSBXi + /* 87699 */ MCD_OPC_FilterValue, + 1, + 183, + 65, + 0, // Skip to: 104527 + /* 87704 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 87707 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 87717 + /* 87712 */ MCD_OPC_Decode, + 193, + 25, + 185, + 3, // Opcode: LDRSBXroW + /* 87717 */ MCD_OPC_FilterValue, + 3, + 165, + 65, + 0, // Skip to: 104527 + /* 87722 */ MCD_OPC_Decode, + 194, + 25, + 186, + 3, // Opcode: LDRSBXroX + /* 87727 */ MCD_OPC_FilterValue, + 3, + 155, + 65, + 0, // Skip to: 104527 + /* 87732 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 148, + 65, + 0, // Skip to: 104527 + /* 87739 */ MCD_OPC_Decode, + 192, + 25, + 177, + 3, // Opcode: LDRSBXpre + /* 87744 */ MCD_OPC_FilterValue, + 3, + 244, + 0, + 0, // Skip to: 87993 + /* 87749 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 87752 */ MCD_OPC_FilterValue, + 0, + 156, + 0, + 0, // Skip to: 87913 + /* 87757 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 87760 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 87770 + /* 87765 */ MCD_OPC_Decode, + 200, + 26, + 177, + 3, // Opcode: LDURSBWi + /* 87770 */ MCD_OPC_FilterValue, + 1, + 112, + 65, + 0, // Skip to: 104527 + /* 87775 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 87778 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 87793 + /* 87783 */ MCD_OPC_CheckPredicate, + 18, + 99, + 65, + 0, // Skip to: 104527 + /* 87788 */ MCD_OPC_Decode, + 128, + 24, + 181, + 3, // Opcode: LDADDALB + /* 87793 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 87808 + /* 87798 */ MCD_OPC_CheckPredicate, + 18, + 84, + 65, + 0, // Skip to: 104527 + /* 87803 */ MCD_OPC_Decode, + 167, + 24, + 181, + 3, // Opcode: LDCLRALB + /* 87808 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 87823 + /* 87813 */ MCD_OPC_CheckPredicate, + 18, + 69, + 65, + 0, // Skip to: 104527 + /* 87818 */ MCD_OPC_Decode, + 183, + 24, + 181, + 3, // Opcode: LDEORALB + /* 87823 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 87838 + /* 87828 */ MCD_OPC_CheckPredicate, + 18, + 54, + 65, + 0, // Skip to: 104527 + /* 87833 */ MCD_OPC_Decode, + 235, + 25, + 181, + 3, // Opcode: LDSETALB + /* 87838 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 87853 + /* 87843 */ MCD_OPC_CheckPredicate, + 18, + 39, + 65, + 0, // Skip to: 104527 + /* 87848 */ MCD_OPC_Decode, + 251, + 25, + 181, + 3, // Opcode: LDSMAXALB + /* 87853 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 87868 + /* 87858 */ MCD_OPC_CheckPredicate, + 18, + 24, + 65, + 0, // Skip to: 104527 + /* 87863 */ MCD_OPC_Decode, + 139, + 26, + 181, + 3, // Opcode: LDSMINALB + /* 87868 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 87883 + /* 87873 */ MCD_OPC_CheckPredicate, + 18, + 9, + 65, + 0, // Skip to: 104527 + /* 87878 */ MCD_OPC_Decode, + 164, + 26, + 181, + 3, // Opcode: LDUMAXALB + /* 87883 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 87898 + /* 87888 */ MCD_OPC_CheckPredicate, + 18, + 250, + 64, + 0, // Skip to: 104527 + /* 87893 */ MCD_OPC_Decode, + 180, + 26, + 181, + 3, // Opcode: LDUMINALB + /* 87898 */ MCD_OPC_FilterValue, + 8, + 240, + 64, + 0, // Skip to: 104527 + /* 87903 */ MCD_OPC_CheckPredicate, + 18, + 235, + 64, + 0, // Skip to: 104527 + /* 87908 */ MCD_OPC_Decode, + 255, + 40, + 181, + 3, // Opcode: SWPALB + /* 87913 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 87930 + /* 87918 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 218, + 64, + 0, // Skip to: 104527 + /* 87925 */ MCD_OPC_Decode, + 186, + 25, + 177, + 3, // Opcode: LDRSBWpost + /* 87930 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 87976 + /* 87935 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 87938 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 87948 + /* 87943 */ MCD_OPC_Decode, + 155, + 26, + 177, + 3, // Opcode: LDTRSBWi + /* 87948 */ MCD_OPC_FilterValue, + 1, + 190, + 64, + 0, // Skip to: 104527 + /* 87953 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 87956 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 87966 + /* 87961 */ MCD_OPC_Decode, + 188, + 25, + 182, + 3, // Opcode: LDRSBWroW + /* 87966 */ MCD_OPC_FilterValue, + 3, + 172, + 64, + 0, // Skip to: 104527 + /* 87971 */ MCD_OPC_Decode, + 189, + 25, + 183, + 3, // Opcode: LDRSBWroX + /* 87976 */ MCD_OPC_FilterValue, + 3, + 162, + 64, + 0, // Skip to: 104527 + /* 87981 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 155, + 64, + 0, // Skip to: 104527 + /* 87988 */ MCD_OPC_Decode, + 187, + 25, + 177, + 3, // Opcode: LDRSBWpre + /* 87993 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 88003 + /* 87998 */ MCD_OPC_Decode, + 225, + 39, + 187, + 3, // Opcode: STRBBui + /* 88003 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 88013 + /* 88008 */ MCD_OPC_Decode, + 158, + 25, + 187, + 3, // Opcode: LDRBBui + /* 88013 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 88023 + /* 88018 */ MCD_OPC_Decode, + 195, + 25, + 187, + 3, // Opcode: LDRSBXui + /* 88023 */ MCD_OPC_FilterValue, + 7, + 5, + 0, + 0, // Skip to: 88033 + /* 88028 */ MCD_OPC_Decode, + 190, + 25, + 187, + 3, // Opcode: LDRSBWui + /* 88033 */ MCD_OPC_FilterValue, + 8, + 78, + 0, + 0, // Skip to: 88116 + /* 88038 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 88041 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 88058 + /* 88046 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 90, + 64, + 0, // Skip to: 104527 + /* 88053 */ MCD_OPC_Decode, + 144, + 7, + 178, + 3, // Opcode: ADCSWr + /* 88058 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 88087 + /* 88063 */ MCD_OPC_CheckPredicate, + 41, + 75, + 64, + 0, // Skip to: 104527 + /* 88068 */ MCD_OPC_CheckField, + 16, + 6, + 0, + 68, + 64, + 0, // Skip to: 104527 + /* 88075 */ MCD_OPC_CheckField, + 0, + 5, + 13, + 61, + 64, + 0, // Skip to: 104527 + /* 88082 */ MCD_OPC_Decode, + 254, + 30, + 188, + 3, // Opcode: SETF8 + /* 88087 */ MCD_OPC_FilterValue, + 18, + 51, + 64, + 0, // Skip to: 104527 + /* 88092 */ MCD_OPC_CheckPredicate, + 41, + 46, + 64, + 0, // Skip to: 104527 + /* 88097 */ MCD_OPC_CheckField, + 16, + 6, + 0, + 39, + 64, + 0, // Skip to: 104527 + /* 88104 */ MCD_OPC_CheckField, + 0, + 5, + 13, + 32, + 64, + 0, // Skip to: 104527 + /* 88111 */ MCD_OPC_Decode, + 253, + 30, + 188, + 3, // Opcode: SETF16 + /* 88116 */ MCD_OPC_FilterValue, + 9, + 22, + 64, + 0, // Skip to: 104527 + /* 88121 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 88124 */ MCD_OPC_FilterValue, + 0, + 19, + 0, + 0, // Skip to: 88148 + /* 88129 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 7, + 64, + 0, // Skip to: 104527 + /* 88136 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 0, + 64, + 0, // Skip to: 104527 + /* 88143 */ MCD_OPC_Decode, + 177, + 9, + 189, + 3, // Opcode: CCMNWr + /* 88148 */ MCD_OPC_FilterValue, + 2, + 246, + 63, + 0, // Skip to: 104527 + /* 88153 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 239, + 63, + 0, // Skip to: 104527 + /* 88160 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 232, + 63, + 0, // Skip to: 104527 + /* 88167 */ MCD_OPC_Decode, + 176, + 9, + 190, + 3, // Opcode: CCMNWi + /* 88172 */ MCD_OPC_FilterValue, + 2, + 244, + 0, + 0, // Skip to: 88421 + /* 88177 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 88180 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 88190 + /* 88185 */ MCD_OPC_Decode, + 224, + 25, + 165, + 3, // Opcode: LDRXl + /* 88190 */ MCD_OPC_FilterValue, + 1, + 91, + 0, + 0, // Skip to: 88286 + /* 88195 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 88198 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 88220 + /* 88203 */ MCD_OPC_CheckPredicate, + 45, + 191, + 63, + 0, // Skip to: 104527 + /* 88208 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 184, + 63, + 0, // Skip to: 104527 + /* 88215 */ MCD_OPC_Decode, + 177, + 39, + 177, + 3, // Opcode: STLURHi + /* 88220 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 88242 + /* 88225 */ MCD_OPC_CheckPredicate, + 45, + 169, + 63, + 0, // Skip to: 104527 + /* 88230 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 162, + 63, + 0, // Skip to: 104527 + /* 88237 */ MCD_OPC_Decode, + 147, + 24, + 177, + 3, // Opcode: LDAPURHi + /* 88242 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 88264 + /* 88247 */ MCD_OPC_CheckPredicate, + 45, + 147, + 63, + 0, // Skip to: 104527 + /* 88252 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 140, + 63, + 0, // Skip to: 104527 + /* 88259 */ MCD_OPC_Decode, + 151, + 24, + 177, + 3, // Opcode: LDAPURSHXi + /* 88264 */ MCD_OPC_FilterValue, + 6, + 130, + 63, + 0, // Skip to: 104527 + /* 88269 */ MCD_OPC_CheckPredicate, + 45, + 125, + 63, + 0, // Skip to: 104527 + /* 88274 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 118, + 63, + 0, // Skip to: 104527 + /* 88281 */ MCD_OPC_Decode, + 150, + 24, + 177, + 3, // Opcode: LDAPURSHWi + /* 88286 */ MCD_OPC_FilterValue, + 2, + 108, + 63, + 0, // Skip to: 104527 + /* 88291 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 88294 */ MCD_OPC_FilterValue, + 0, + 58, + 0, + 0, // Skip to: 88357 + /* 88299 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 88302 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 88319 + /* 88307 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 85, + 63, + 0, // Skip to: 104527 + /* 88314 */ MCD_OPC_Decode, + 191, + 30, + 178, + 3, // Opcode: SBCWr + /* 88319 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 88329 + /* 88324 */ MCD_OPC_Decode, + 222, + 11, + 179, + 3, // Opcode: CSINVWr + /* 88329 */ MCD_OPC_FilterValue, + 6, + 65, + 63, + 0, // Skip to: 104527 + /* 88334 */ MCD_OPC_ExtractField, + 12, + 9, // Inst{20-12} ... + /* 88337 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 88347 + /* 88342 */ MCD_OPC_Decode, + 144, + 29, + 191, + 3, // Opcode: RBITWr + /* 88347 */ MCD_OPC_FilterValue, + 1, + 47, + 63, + 0, // Skip to: 104527 + /* 88352 */ MCD_OPC_Decode, + 226, + 9, + 191, + 3, // Opcode: CLZWr + /* 88357 */ MCD_OPC_FilterValue, + 1, + 41, + 0, + 0, // Skip to: 88403 + /* 88362 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 88365 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 88375 + /* 88370 */ MCD_OPC_Decode, + 224, + 11, + 179, + 3, // Opcode: CSNEGWr + /* 88375 */ MCD_OPC_FilterValue, + 6, + 19, + 63, + 0, // Skip to: 104527 + /* 88380 */ MCD_OPC_ExtractField, + 12, + 9, // Inst{20-12} ... + /* 88383 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 88393 + /* 88388 */ MCD_OPC_Decode, + 159, + 29, + 191, + 3, // Opcode: REV16Wr + /* 88393 */ MCD_OPC_FilterValue, + 1, + 1, + 63, + 0, // Skip to: 104527 + /* 88398 */ MCD_OPC_Decode, + 214, + 9, + 191, + 3, // Opcode: CLSWr + /* 88403 */ MCD_OPC_FilterValue, + 2, + 247, + 62, + 0, // Skip to: 104527 + /* 88408 */ MCD_OPC_CheckField, + 12, + 12, + 128, + 24, + 239, + 62, + 0, // Skip to: 104527 + /* 88416 */ MCD_OPC_Decode, + 181, + 29, + 191, + 3, // Opcode: REVWr + /* 88421 */ MCD_OPC_FilterValue, + 3, + 117, + 4, + 0, // Skip to: 89567 + /* 88426 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 88429 */ MCD_OPC_FilterValue, + 0, + 244, + 0, + 0, // Skip to: 88678 + /* 88434 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 88437 */ MCD_OPC_FilterValue, + 0, + 156, + 0, + 0, // Skip to: 88598 + /* 88442 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 88445 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 88455 + /* 88450 */ MCD_OPC_Decode, + 148, + 40, + 177, + 3, // Opcode: STURHHi + /* 88455 */ MCD_OPC_FilterValue, + 1, + 195, + 62, + 0, // Skip to: 104527 + /* 88460 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 88463 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 88478 + /* 88468 */ MCD_OPC_CheckPredicate, + 18, + 182, + 62, + 0, // Skip to: 104527 + /* 88473 */ MCD_OPC_Decode, + 135, + 24, + 181, + 3, // Opcode: LDADDH + /* 88478 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 88493 + /* 88483 */ MCD_OPC_CheckPredicate, + 18, + 167, + 62, + 0, // Skip to: 104527 + /* 88488 */ MCD_OPC_Decode, + 174, + 24, + 181, + 3, // Opcode: LDCLRH + /* 88493 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 88508 + /* 88498 */ MCD_OPC_CheckPredicate, + 18, + 152, + 62, + 0, // Skip to: 104527 + /* 88503 */ MCD_OPC_Decode, + 190, + 24, + 181, + 3, // Opcode: LDEORH + /* 88508 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 88523 + /* 88513 */ MCD_OPC_CheckPredicate, + 18, + 137, + 62, + 0, // Skip to: 104527 + /* 88518 */ MCD_OPC_Decode, + 242, + 25, + 181, + 3, // Opcode: LDSETH + /* 88523 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 88538 + /* 88528 */ MCD_OPC_CheckPredicate, + 18, + 122, + 62, + 0, // Skip to: 104527 + /* 88533 */ MCD_OPC_Decode, + 130, + 26, + 181, + 3, // Opcode: LDSMAXH + /* 88538 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 88553 + /* 88543 */ MCD_OPC_CheckPredicate, + 18, + 107, + 62, + 0, // Skip to: 104527 + /* 88548 */ MCD_OPC_Decode, + 146, + 26, + 181, + 3, // Opcode: LDSMINH + /* 88553 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 88568 + /* 88558 */ MCD_OPC_CheckPredicate, + 18, + 92, + 62, + 0, // Skip to: 104527 + /* 88563 */ MCD_OPC_Decode, + 171, + 26, + 181, + 3, // Opcode: LDUMAXH + /* 88568 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 88583 + /* 88573 */ MCD_OPC_CheckPredicate, + 18, + 77, + 62, + 0, // Skip to: 104527 + /* 88578 */ MCD_OPC_Decode, + 187, + 26, + 181, + 3, // Opcode: LDUMINH + /* 88583 */ MCD_OPC_FilterValue, + 8, + 67, + 62, + 0, // Skip to: 104527 + /* 88588 */ MCD_OPC_CheckPredicate, + 18, + 62, + 62, + 0, // Skip to: 104527 + /* 88593 */ MCD_OPC_Decode, + 134, + 41, + 181, + 3, // Opcode: SWPH + /* 88598 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 88615 + /* 88603 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 45, + 62, + 0, // Skip to: 104527 + /* 88610 */ MCD_OPC_Decode, + 236, + 39, + 177, + 3, // Opcode: STRHHpost + /* 88615 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 88661 + /* 88620 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 88623 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 88633 + /* 88628 */ MCD_OPC_Decode, + 142, + 40, + 177, + 3, // Opcode: STTRHi + /* 88633 */ MCD_OPC_FilterValue, + 1, + 17, + 62, + 0, // Skip to: 104527 + /* 88638 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 88641 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 88651 + /* 88646 */ MCD_OPC_Decode, + 238, + 39, + 182, + 3, // Opcode: STRHHroW + /* 88651 */ MCD_OPC_FilterValue, + 3, + 255, + 61, + 0, // Skip to: 104527 + /* 88656 */ MCD_OPC_Decode, + 239, + 39, + 183, + 3, // Opcode: STRHHroX + /* 88661 */ MCD_OPC_FilterValue, + 3, + 245, + 61, + 0, // Skip to: 104527 + /* 88666 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 238, + 61, + 0, // Skip to: 104527 + /* 88673 */ MCD_OPC_Decode, + 237, + 39, + 177, + 3, // Opcode: STRHHpre + /* 88678 */ MCD_OPC_FilterValue, + 1, + 244, + 0, + 0, // Skip to: 88927 + /* 88683 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 88686 */ MCD_OPC_FilterValue, + 0, + 156, + 0, + 0, // Skip to: 88847 + /* 88691 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 88694 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 88704 + /* 88699 */ MCD_OPC_Decode, + 197, + 26, + 177, + 3, // Opcode: LDURHHi + /* 88704 */ MCD_OPC_FilterValue, + 1, + 202, + 61, + 0, // Skip to: 104527 + /* 88709 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 88712 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 88727 + /* 88717 */ MCD_OPC_CheckPredicate, + 18, + 189, + 61, + 0, // Skip to: 104527 + /* 88722 */ MCD_OPC_Decode, + 137, + 24, + 181, + 3, // Opcode: LDADDLH + /* 88727 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 88742 + /* 88732 */ MCD_OPC_CheckPredicate, + 18, + 174, + 61, + 0, // Skip to: 104527 + /* 88737 */ MCD_OPC_Decode, + 176, + 24, + 181, + 3, // Opcode: LDCLRLH + /* 88742 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 88757 + /* 88747 */ MCD_OPC_CheckPredicate, + 18, + 159, + 61, + 0, // Skip to: 104527 + /* 88752 */ MCD_OPC_Decode, + 192, + 24, + 181, + 3, // Opcode: LDEORLH + /* 88757 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 88772 + /* 88762 */ MCD_OPC_CheckPredicate, + 18, + 144, + 61, + 0, // Skip to: 104527 + /* 88767 */ MCD_OPC_Decode, + 244, + 25, + 181, + 3, // Opcode: LDSETLH + /* 88772 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 88787 + /* 88777 */ MCD_OPC_CheckPredicate, + 18, + 129, + 61, + 0, // Skip to: 104527 + /* 88782 */ MCD_OPC_Decode, + 132, + 26, + 181, + 3, // Opcode: LDSMAXLH + /* 88787 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 88802 + /* 88792 */ MCD_OPC_CheckPredicate, + 18, + 114, + 61, + 0, // Skip to: 104527 + /* 88797 */ MCD_OPC_Decode, + 148, + 26, + 181, + 3, // Opcode: LDSMINLH + /* 88802 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 88817 + /* 88807 */ MCD_OPC_CheckPredicate, + 18, + 99, + 61, + 0, // Skip to: 104527 + /* 88812 */ MCD_OPC_Decode, + 173, + 26, + 181, + 3, // Opcode: LDUMAXLH + /* 88817 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 88832 + /* 88822 */ MCD_OPC_CheckPredicate, + 18, + 84, + 61, + 0, // Skip to: 104527 + /* 88827 */ MCD_OPC_Decode, + 189, + 26, + 181, + 3, // Opcode: LDUMINLH + /* 88832 */ MCD_OPC_FilterValue, + 8, + 74, + 61, + 0, // Skip to: 104527 + /* 88837 */ MCD_OPC_CheckPredicate, + 18, + 69, + 61, + 0, // Skip to: 104527 + /* 88842 */ MCD_OPC_Decode, + 136, + 41, + 181, + 3, // Opcode: SWPLH + /* 88847 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 88864 + /* 88852 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 52, + 61, + 0, // Skip to: 104527 + /* 88859 */ MCD_OPC_Decode, + 170, + 25, + 177, + 3, // Opcode: LDRHHpost + /* 88864 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 88910 + /* 88869 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 88872 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 88882 + /* 88877 */ MCD_OPC_Decode, + 154, + 26, + 177, + 3, // Opcode: LDTRHi + /* 88882 */ MCD_OPC_FilterValue, + 1, + 24, + 61, + 0, // Skip to: 104527 + /* 88887 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 88890 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 88900 + /* 88895 */ MCD_OPC_Decode, + 172, + 25, + 182, + 3, // Opcode: LDRHHroW + /* 88900 */ MCD_OPC_FilterValue, + 3, + 6, + 61, + 0, // Skip to: 104527 + /* 88905 */ MCD_OPC_Decode, + 173, + 25, + 183, + 3, // Opcode: LDRHHroX + /* 88910 */ MCD_OPC_FilterValue, + 3, + 252, + 60, + 0, // Skip to: 104527 + /* 88915 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 245, + 60, + 0, // Skip to: 104527 + /* 88922 */ MCD_OPC_Decode, + 171, + 25, + 177, + 3, // Opcode: LDRHHpre + /* 88927 */ MCD_OPC_FilterValue, + 2, + 10, + 1, + 0, // Skip to: 89198 + /* 88932 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 88935 */ MCD_OPC_FilterValue, + 0, + 178, + 0, + 0, // Skip to: 89118 + /* 88940 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 88943 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 88953 + /* 88948 */ MCD_OPC_Decode, + 203, + 26, + 177, + 3, // Opcode: LDURSHXi + /* 88953 */ MCD_OPC_FilterValue, + 1, + 209, + 60, + 0, // Skip to: 104527 + /* 88958 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 88961 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 88976 + /* 88966 */ MCD_OPC_CheckPredicate, + 18, + 196, + 60, + 0, // Skip to: 104527 + /* 88971 */ MCD_OPC_Decode, + 255, + 23, + 181, + 3, // Opcode: LDADDAH + /* 88976 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 88991 + /* 88981 */ MCD_OPC_CheckPredicate, + 18, + 181, + 60, + 0, // Skip to: 104527 + /* 88986 */ MCD_OPC_Decode, + 166, + 24, + 181, + 3, // Opcode: LDCLRAH + /* 88991 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 89006 + /* 88996 */ MCD_OPC_CheckPredicate, + 18, + 166, + 60, + 0, // Skip to: 104527 + /* 89001 */ MCD_OPC_Decode, + 182, + 24, + 181, + 3, // Opcode: LDEORAH + /* 89006 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 89021 + /* 89011 */ MCD_OPC_CheckPredicate, + 18, + 151, + 60, + 0, // Skip to: 104527 + /* 89016 */ MCD_OPC_Decode, + 234, + 25, + 181, + 3, // Opcode: LDSETAH + /* 89021 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 89036 + /* 89026 */ MCD_OPC_CheckPredicate, + 18, + 136, + 60, + 0, // Skip to: 104527 + /* 89031 */ MCD_OPC_Decode, + 250, + 25, + 181, + 3, // Opcode: LDSMAXAH + /* 89036 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 89051 + /* 89041 */ MCD_OPC_CheckPredicate, + 18, + 121, + 60, + 0, // Skip to: 104527 + /* 89046 */ MCD_OPC_Decode, + 138, + 26, + 181, + 3, // Opcode: LDSMINAH + /* 89051 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 89066 + /* 89056 */ MCD_OPC_CheckPredicate, + 18, + 106, + 60, + 0, // Skip to: 104527 + /* 89061 */ MCD_OPC_Decode, + 163, + 26, + 181, + 3, // Opcode: LDUMAXAH + /* 89066 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 89081 + /* 89071 */ MCD_OPC_CheckPredicate, + 18, + 91, + 60, + 0, // Skip to: 104527 + /* 89076 */ MCD_OPC_Decode, + 179, + 26, + 181, + 3, // Opcode: LDUMINAH + /* 89081 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 89096 + /* 89086 */ MCD_OPC_CheckPredicate, + 18, + 76, + 60, + 0, // Skip to: 104527 + /* 89091 */ MCD_OPC_Decode, + 254, + 40, + 181, + 3, // Opcode: SWPAH + /* 89096 */ MCD_OPC_FilterValue, + 12, + 66, + 60, + 0, // Skip to: 104527 + /* 89101 */ MCD_OPC_CheckPredicate, + 47, + 61, + 60, + 0, // Skip to: 104527 + /* 89106 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 54, + 60, + 0, // Skip to: 104527 + /* 89113 */ MCD_OPC_Decode, + 143, + 24, + 184, + 3, // Opcode: LDAPRH + /* 89118 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 89135 + /* 89123 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 37, + 60, + 0, // Skip to: 104527 + /* 89130 */ MCD_OPC_Decode, + 201, + 25, + 177, + 3, // Opcode: LDRSHXpost + /* 89135 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 89181 + /* 89140 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 89143 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 89153 + /* 89148 */ MCD_OPC_Decode, + 158, + 26, + 177, + 3, // Opcode: LDTRSHXi + /* 89153 */ MCD_OPC_FilterValue, + 1, + 9, + 60, + 0, // Skip to: 104527 + /* 89158 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 89161 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 89171 + /* 89166 */ MCD_OPC_Decode, + 203, + 25, + 185, + 3, // Opcode: LDRSHXroW + /* 89171 */ MCD_OPC_FilterValue, + 3, + 247, + 59, + 0, // Skip to: 104527 + /* 89176 */ MCD_OPC_Decode, + 204, + 25, + 186, + 3, // Opcode: LDRSHXroX + /* 89181 */ MCD_OPC_FilterValue, + 3, + 237, + 59, + 0, // Skip to: 104527 + /* 89186 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 230, + 59, + 0, // Skip to: 104527 + /* 89193 */ MCD_OPC_Decode, + 202, + 25, + 177, + 3, // Opcode: LDRSHXpre + /* 89198 */ MCD_OPC_FilterValue, + 3, + 244, + 0, + 0, // Skip to: 89447 + /* 89203 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 89206 */ MCD_OPC_FilterValue, + 0, + 156, + 0, + 0, // Skip to: 89367 + /* 89211 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 89214 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 89224 + /* 89219 */ MCD_OPC_Decode, + 202, + 26, + 177, + 3, // Opcode: LDURSHWi + /* 89224 */ MCD_OPC_FilterValue, + 1, + 194, + 59, + 0, // Skip to: 104527 + /* 89229 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 89232 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 89247 + /* 89237 */ MCD_OPC_CheckPredicate, + 18, + 181, + 59, + 0, // Skip to: 104527 + /* 89242 */ MCD_OPC_Decode, + 129, + 24, + 181, + 3, // Opcode: LDADDALH + /* 89247 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 89262 + /* 89252 */ MCD_OPC_CheckPredicate, + 18, + 166, + 59, + 0, // Skip to: 104527 + /* 89257 */ MCD_OPC_Decode, + 168, + 24, + 181, + 3, // Opcode: LDCLRALH + /* 89262 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 89277 + /* 89267 */ MCD_OPC_CheckPredicate, + 18, + 151, + 59, + 0, // Skip to: 104527 + /* 89272 */ MCD_OPC_Decode, + 184, + 24, + 181, + 3, // Opcode: LDEORALH + /* 89277 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 89292 + /* 89282 */ MCD_OPC_CheckPredicate, + 18, + 136, + 59, + 0, // Skip to: 104527 + /* 89287 */ MCD_OPC_Decode, + 236, + 25, + 181, + 3, // Opcode: LDSETALH + /* 89292 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 89307 + /* 89297 */ MCD_OPC_CheckPredicate, + 18, + 121, + 59, + 0, // Skip to: 104527 + /* 89302 */ MCD_OPC_Decode, + 252, + 25, + 181, + 3, // Opcode: LDSMAXALH + /* 89307 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 89322 + /* 89312 */ MCD_OPC_CheckPredicate, + 18, + 106, + 59, + 0, // Skip to: 104527 + /* 89317 */ MCD_OPC_Decode, + 140, + 26, + 181, + 3, // Opcode: LDSMINALH + /* 89322 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 89337 + /* 89327 */ MCD_OPC_CheckPredicate, + 18, + 91, + 59, + 0, // Skip to: 104527 + /* 89332 */ MCD_OPC_Decode, + 165, + 26, + 181, + 3, // Opcode: LDUMAXALH + /* 89337 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 89352 + /* 89342 */ MCD_OPC_CheckPredicate, + 18, + 76, + 59, + 0, // Skip to: 104527 + /* 89347 */ MCD_OPC_Decode, + 181, + 26, + 181, + 3, // Opcode: LDUMINALH + /* 89352 */ MCD_OPC_FilterValue, + 8, + 66, + 59, + 0, // Skip to: 104527 + /* 89357 */ MCD_OPC_CheckPredicate, + 18, + 61, + 59, + 0, // Skip to: 104527 + /* 89362 */ MCD_OPC_Decode, + 128, + 41, + 181, + 3, // Opcode: SWPALH + /* 89367 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 89384 + /* 89372 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 44, + 59, + 0, // Skip to: 104527 + /* 89379 */ MCD_OPC_Decode, + 196, + 25, + 177, + 3, // Opcode: LDRSHWpost + /* 89384 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 89430 + /* 89389 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 89392 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 89402 + /* 89397 */ MCD_OPC_Decode, + 157, + 26, + 177, + 3, // Opcode: LDTRSHWi + /* 89402 */ MCD_OPC_FilterValue, + 1, + 16, + 59, + 0, // Skip to: 104527 + /* 89407 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 89410 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 89420 + /* 89415 */ MCD_OPC_Decode, + 198, + 25, + 182, + 3, // Opcode: LDRSHWroW + /* 89420 */ MCD_OPC_FilterValue, + 3, + 254, + 58, + 0, // Skip to: 104527 + /* 89425 */ MCD_OPC_Decode, + 199, + 25, + 183, + 3, // Opcode: LDRSHWroX + /* 89430 */ MCD_OPC_FilterValue, + 3, + 244, + 58, + 0, // Skip to: 104527 + /* 89435 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 237, + 58, + 0, // Skip to: 104527 + /* 89442 */ MCD_OPC_Decode, + 197, + 25, + 177, + 3, // Opcode: LDRSHWpre + /* 89447 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 89457 + /* 89452 */ MCD_OPC_Decode, + 240, + 39, + 187, + 3, // Opcode: STRHHui + /* 89457 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 89467 + /* 89462 */ MCD_OPC_Decode, + 174, + 25, + 187, + 3, // Opcode: LDRHHui + /* 89467 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 89477 + /* 89472 */ MCD_OPC_Decode, + 205, + 25, + 187, + 3, // Opcode: LDRSHXui + /* 89477 */ MCD_OPC_FilterValue, + 7, + 5, + 0, + 0, // Skip to: 89487 + /* 89482 */ MCD_OPC_Decode, + 200, + 25, + 187, + 3, // Opcode: LDRSHWui + /* 89487 */ MCD_OPC_FilterValue, + 8, + 19, + 0, + 0, // Skip to: 89511 + /* 89492 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 180, + 58, + 0, // Skip to: 104527 + /* 89499 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 173, + 58, + 0, // Skip to: 104527 + /* 89506 */ MCD_OPC_Decode, + 189, + 30, + 178, + 3, // Opcode: SBCSWr + /* 89511 */ MCD_OPC_FilterValue, + 9, + 163, + 58, + 0, // Skip to: 104527 + /* 89516 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 89519 */ MCD_OPC_FilterValue, + 0, + 19, + 0, + 0, // Skip to: 89543 + /* 89524 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 148, + 58, + 0, // Skip to: 104527 + /* 89531 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 141, + 58, + 0, // Skip to: 104527 + /* 89538 */ MCD_OPC_Decode, + 181, + 9, + 189, + 3, // Opcode: CCMPWr + /* 89543 */ MCD_OPC_FilterValue, + 2, + 131, + 58, + 0, // Skip to: 104527 + /* 89548 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 124, + 58, + 0, // Skip to: 104527 + /* 89555 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 117, + 58, + 0, // Skip to: 104527 + /* 89562 */ MCD_OPC_Decode, + 180, + 9, + 190, + 3, // Opcode: CCMPWi + /* 89567 */ MCD_OPC_FilterValue, + 4, + 242, + 1, + 0, // Skip to: 90070 + /* 89572 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 89575 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 89585 + /* 89580 */ MCD_OPC_Decode, + 206, + 25, + 165, + 3, // Opcode: LDRSWl + /* 89585 */ MCD_OPC_FilterValue, + 1, + 69, + 0, + 0, // Skip to: 89659 + /* 89590 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 89593 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 89615 + /* 89598 */ MCD_OPC_CheckPredicate, + 45, + 76, + 58, + 0, // Skip to: 104527 + /* 89603 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 69, + 58, + 0, // Skip to: 104527 + /* 89610 */ MCD_OPC_Decode, + 178, + 39, + 177, + 3, // Opcode: STLURWi + /* 89615 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 89637 + /* 89620 */ MCD_OPC_CheckPredicate, + 45, + 54, + 58, + 0, // Skip to: 104527 + /* 89625 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 47, + 58, + 0, // Skip to: 104527 + /* 89632 */ MCD_OPC_Decode, + 154, + 24, + 177, + 3, // Opcode: LDAPURi + /* 89637 */ MCD_OPC_FilterValue, + 4, + 37, + 58, + 0, // Skip to: 104527 + /* 89642 */ MCD_OPC_CheckPredicate, + 45, + 32, + 58, + 0, // Skip to: 104527 + /* 89647 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 25, + 58, + 0, // Skip to: 104527 + /* 89654 */ MCD_OPC_Decode, + 152, + 24, + 177, + 3, // Opcode: LDAPURSWi + /* 89659 */ MCD_OPC_FilterValue, + 2, + 24, + 1, + 0, // Skip to: 89944 + /* 89664 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 89667 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 89765 + /* 89672 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 89675 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 89692 + /* 89680 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 248, + 57, + 0, // Skip to: 104527 + /* 89687 */ MCD_OPC_Decode, + 147, + 7, + 192, + 3, // Opcode: ADCXr + /* 89692 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 89702 + /* 89697 */ MCD_OPC_Decode, + 219, + 11, + 193, + 3, // Opcode: CSELXr + /* 89702 */ MCD_OPC_FilterValue, + 6, + 228, + 57, + 0, // Skip to: 104527 + /* 89707 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 89710 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 89725 + /* 89715 */ MCD_OPC_CheckPredicate, + 20, + 215, + 57, + 0, // Skip to: 104527 + /* 89720 */ MCD_OPC_Decode, + 180, + 40, + 194, + 3, // Opcode: SUBP + /* 89725 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 89740 + /* 89730 */ MCD_OPC_CheckPredicate, + 20, + 200, + 57, + 0, // Skip to: 104527 + /* 89735 */ MCD_OPC_Decode, + 191, + 21, + 195, + 3, // Opcode: IRG + /* 89740 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 89750 + /* 89745 */ MCD_OPC_Decode, + 219, + 26, + 192, + 3, // Opcode: LSLVXr + /* 89750 */ MCD_OPC_FilterValue, + 3, + 180, + 57, + 0, // Skip to: 104527 + /* 89755 */ MCD_OPC_CheckPredicate, + 44, + 175, + 57, + 0, // Skip to: 104527 + /* 89760 */ MCD_OPC_Decode, + 172, + 28, + 196, + 3, // Opcode: PACGA + /* 89765 */ MCD_OPC_FilterValue, + 1, + 46, + 0, + 0, // Skip to: 89816 + /* 89770 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 89773 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 89783 + /* 89778 */ MCD_OPC_Decode, + 221, + 11, + 193, + 3, // Opcode: CSINCXr + /* 89783 */ MCD_OPC_FilterValue, + 6, + 147, + 57, + 0, // Skip to: 104527 + /* 89788 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 89791 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 89806 + /* 89796 */ MCD_OPC_CheckPredicate, + 20, + 134, + 57, + 0, // Skip to: 104527 + /* 89801 */ MCD_OPC_Decode, + 128, + 21, + 197, + 3, // Opcode: GMI + /* 89806 */ MCD_OPC_FilterValue, + 2, + 124, + 57, + 0, // Skip to: 104527 + /* 89811 */ MCD_OPC_Decode, + 243, + 26, + 192, + 3, // Opcode: LSRVXr + /* 89816 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 89858 + /* 89821 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 89824 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 89841 + /* 89829 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 99, + 57, + 0, // Skip to: 104527 + /* 89836 */ MCD_OPC_Decode, + 227, + 42, + 192, + 3, // Opcode: UDIVXr + /* 89841 */ MCD_OPC_FilterValue, + 2, + 89, + 57, + 0, // Skip to: 104527 + /* 89846 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 82, + 57, + 0, // Skip to: 104527 + /* 89853 */ MCD_OPC_Decode, + 147, + 8, + 192, + 3, // Opcode: ASRVXr + /* 89858 */ MCD_OPC_FilterValue, + 3, + 72, + 57, + 0, // Skip to: 104527 + /* 89863 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 89866 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 89883 + /* 89871 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 57, + 57, + 0, // Skip to: 104527 + /* 89878 */ MCD_OPC_Decode, + 237, + 30, + 192, + 3, // Opcode: SDIVXr + /* 89883 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 89900 + /* 89888 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 40, + 57, + 0, // Skip to: 104527 + /* 89895 */ MCD_OPC_Decode, + 193, + 29, + 192, + 3, // Opcode: RORVXr + /* 89900 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 89922 + /* 89905 */ MCD_OPC_CheckPredicate, + 46, + 25, + 57, + 0, // Skip to: 104527 + /* 89910 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 18, + 57, + 0, // Skip to: 104527 + /* 89917 */ MCD_OPC_Decode, + 217, + 11, + 198, + 3, // Opcode: CRC32Xrr + /* 89922 */ MCD_OPC_FilterValue, + 5, + 8, + 57, + 0, // Skip to: 104527 + /* 89927 */ MCD_OPC_CheckPredicate, + 46, + 3, + 57, + 0, // Skip to: 104527 + /* 89932 */ MCD_OPC_CheckField, + 21, + 3, + 6, + 252, + 56, + 0, // Skip to: 104527 + /* 89939 */ MCD_OPC_Decode, + 214, + 11, + 198, + 3, // Opcode: CRC32CXrr + /* 89944 */ MCD_OPC_FilterValue, + 3, + 242, + 56, + 0, // Skip to: 104527 + /* 89949 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 89952 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 89980 + /* 89957 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 89960 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 89970 + /* 89965 */ MCD_OPC_Decode, + 135, + 27, + 199, + 3, // Opcode: MADDXrrr + /* 89970 */ MCD_OPC_FilterValue, + 1, + 216, + 56, + 0, // Skip to: 104527 + /* 89975 */ MCD_OPC_Decode, + 211, + 27, + 199, + 3, // Opcode: MSUBXrrr + /* 89980 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 90008 + /* 89985 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 89988 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 89998 + /* 89993 */ MCD_OPC_Decode, + 215, + 31, + 200, + 3, // Opcode: SMADDLrrr + /* 89998 */ MCD_OPC_FilterValue, + 1, + 188, + 56, + 0, // Skip to: 104527 + /* 90003 */ MCD_OPC_Decode, + 211, + 32, + 200, + 3, // Opcode: SMSUBLrrr + /* 90008 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 90025 + /* 90013 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 171, + 56, + 0, // Skip to: 104527 + /* 90020 */ MCD_OPC_Decode, + 220, + 32, + 192, + 3, // Opcode: SMULHrr + /* 90025 */ MCD_OPC_FilterValue, + 5, + 23, + 0, + 0, // Skip to: 90053 + /* 90030 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 90033 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 90043 + /* 90038 */ MCD_OPC_Decode, + 134, + 43, + 200, + 3, // Opcode: UMADDLrrr + /* 90043 */ MCD_OPC_FilterValue, + 1, + 143, + 56, + 0, // Skip to: 104527 + /* 90048 */ MCD_OPC_Decode, + 255, + 43, + 200, + 3, // Opcode: UMSUBLrrr + /* 90053 */ MCD_OPC_FilterValue, + 6, + 133, + 56, + 0, // Skip to: 104527 + /* 90058 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 126, + 56, + 0, // Skip to: 104527 + /* 90065 */ MCD_OPC_Decode, + 136, + 44, + 192, + 3, // Opcode: UMULHrr + /* 90070 */ MCD_OPC_FilterValue, + 5, + 130, + 4, + 0, // Skip to: 91229 + /* 90075 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 90078 */ MCD_OPC_FilterValue, + 0, + 244, + 0, + 0, // Skip to: 90327 + /* 90083 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 90086 */ MCD_OPC_FilterValue, + 0, + 156, + 0, + 0, // Skip to: 90247 + /* 90091 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 90094 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 90104 + /* 90099 */ MCD_OPC_Decode, + 152, + 40, + 177, + 3, // Opcode: STURWi + /* 90104 */ MCD_OPC_FilterValue, + 1, + 82, + 56, + 0, // Skip to: 104527 + /* 90109 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 90112 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 90127 + /* 90117 */ MCD_OPC_CheckPredicate, + 18, + 69, + 56, + 0, // Skip to: 104527 + /* 90122 */ MCD_OPC_Decode, + 140, + 24, + 181, + 3, // Opcode: LDADDW + /* 90127 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 90142 + /* 90132 */ MCD_OPC_CheckPredicate, + 18, + 54, + 56, + 0, // Skip to: 104527 + /* 90137 */ MCD_OPC_Decode, + 179, + 24, + 181, + 3, // Opcode: LDCLRW + /* 90142 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 90157 + /* 90147 */ MCD_OPC_CheckPredicate, + 18, + 39, + 56, + 0, // Skip to: 104527 + /* 90152 */ MCD_OPC_Decode, + 195, + 24, + 181, + 3, // Opcode: LDEORW + /* 90157 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 90172 + /* 90162 */ MCD_OPC_CheckPredicate, + 18, + 24, + 56, + 0, // Skip to: 104527 + /* 90167 */ MCD_OPC_Decode, + 247, + 25, + 181, + 3, // Opcode: LDSETW + /* 90172 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 90187 + /* 90177 */ MCD_OPC_CheckPredicate, + 18, + 9, + 56, + 0, // Skip to: 104527 + /* 90182 */ MCD_OPC_Decode, + 135, + 26, + 181, + 3, // Opcode: LDSMAXW + /* 90187 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 90202 + /* 90192 */ MCD_OPC_CheckPredicate, + 18, + 250, + 55, + 0, // Skip to: 104527 + /* 90197 */ MCD_OPC_Decode, + 151, + 26, + 181, + 3, // Opcode: LDSMINW + /* 90202 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 90217 + /* 90207 */ MCD_OPC_CheckPredicate, + 18, + 235, + 55, + 0, // Skip to: 104527 + /* 90212 */ MCD_OPC_Decode, + 176, + 26, + 181, + 3, // Opcode: LDUMAXW + /* 90217 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 90232 + /* 90222 */ MCD_OPC_CheckPredicate, + 18, + 220, + 55, + 0, // Skip to: 104527 + /* 90227 */ MCD_OPC_Decode, + 192, + 26, + 181, + 3, // Opcode: LDUMINW + /* 90232 */ MCD_OPC_FilterValue, + 8, + 210, + 55, + 0, // Skip to: 104527 + /* 90237 */ MCD_OPC_CheckPredicate, + 18, + 205, + 55, + 0, // Skip to: 104527 + /* 90242 */ MCD_OPC_Decode, + 139, + 41, + 181, + 3, // Opcode: SWPW + /* 90247 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 90264 + /* 90252 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 188, + 55, + 0, // Skip to: 104527 + /* 90259 */ MCD_OPC_Decode, + 128, + 40, + 177, + 3, // Opcode: STRWpost + /* 90264 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 90310 + /* 90269 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 90272 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 90282 + /* 90277 */ MCD_OPC_Decode, + 143, + 40, + 177, + 3, // Opcode: STTRWi + /* 90282 */ MCD_OPC_FilterValue, + 1, + 160, + 55, + 0, // Skip to: 104527 + /* 90287 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 90290 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 90300 + /* 90295 */ MCD_OPC_Decode, + 130, + 40, + 182, + 3, // Opcode: STRWroW + /* 90300 */ MCD_OPC_FilterValue, + 3, + 142, + 55, + 0, // Skip to: 104527 + /* 90305 */ MCD_OPC_Decode, + 131, + 40, + 183, + 3, // Opcode: STRWroX + /* 90310 */ MCD_OPC_FilterValue, + 3, + 132, + 55, + 0, // Skip to: 104527 + /* 90315 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 125, + 55, + 0, // Skip to: 104527 + /* 90322 */ MCD_OPC_Decode, + 129, + 40, + 177, + 3, // Opcode: STRWpre + /* 90327 */ MCD_OPC_FilterValue, + 1, + 244, + 0, + 0, // Skip to: 90576 + /* 90332 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 90335 */ MCD_OPC_FilterValue, + 0, + 156, + 0, + 0, // Skip to: 90496 + /* 90340 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 90343 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 90353 + /* 90348 */ MCD_OPC_Decode, + 206, + 26, + 177, + 3, // Opcode: LDURWi + /* 90353 */ MCD_OPC_FilterValue, + 1, + 89, + 55, + 0, // Skip to: 104527 + /* 90358 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 90361 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 90376 + /* 90366 */ MCD_OPC_CheckPredicate, + 18, + 76, + 55, + 0, // Skip to: 104527 + /* 90371 */ MCD_OPC_Decode, + 138, + 24, + 181, + 3, // Opcode: LDADDLW + /* 90376 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 90391 + /* 90381 */ MCD_OPC_CheckPredicate, + 18, + 61, + 55, + 0, // Skip to: 104527 + /* 90386 */ MCD_OPC_Decode, + 177, + 24, + 181, + 3, // Opcode: LDCLRLW + /* 90391 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 90406 + /* 90396 */ MCD_OPC_CheckPredicate, + 18, + 46, + 55, + 0, // Skip to: 104527 + /* 90401 */ MCD_OPC_Decode, + 193, + 24, + 181, + 3, // Opcode: LDEORLW + /* 90406 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 90421 + /* 90411 */ MCD_OPC_CheckPredicate, + 18, + 31, + 55, + 0, // Skip to: 104527 + /* 90416 */ MCD_OPC_Decode, + 245, + 25, + 181, + 3, // Opcode: LDSETLW + /* 90421 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 90436 + /* 90426 */ MCD_OPC_CheckPredicate, + 18, + 16, + 55, + 0, // Skip to: 104527 + /* 90431 */ MCD_OPC_Decode, + 133, + 26, + 181, + 3, // Opcode: LDSMAXLW + /* 90436 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 90451 + /* 90441 */ MCD_OPC_CheckPredicate, + 18, + 1, + 55, + 0, // Skip to: 104527 + /* 90446 */ MCD_OPC_Decode, + 149, + 26, + 181, + 3, // Opcode: LDSMINLW + /* 90451 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 90466 + /* 90456 */ MCD_OPC_CheckPredicate, + 18, + 242, + 54, + 0, // Skip to: 104527 + /* 90461 */ MCD_OPC_Decode, + 174, + 26, + 181, + 3, // Opcode: LDUMAXLW + /* 90466 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 90481 + /* 90471 */ MCD_OPC_CheckPredicate, + 18, + 227, + 54, + 0, // Skip to: 104527 + /* 90476 */ MCD_OPC_Decode, + 190, + 26, + 181, + 3, // Opcode: LDUMINLW + /* 90481 */ MCD_OPC_FilterValue, + 8, + 217, + 54, + 0, // Skip to: 104527 + /* 90486 */ MCD_OPC_CheckPredicate, + 18, + 212, + 54, + 0, // Skip to: 104527 + /* 90491 */ MCD_OPC_Decode, + 137, + 41, + 181, + 3, // Opcode: SWPLW + /* 90496 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 90513 + /* 90501 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 195, + 54, + 0, // Skip to: 104527 + /* 90508 */ MCD_OPC_Decode, + 219, + 25, + 177, + 3, // Opcode: LDRWpost + /* 90513 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 90559 + /* 90518 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 90521 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 90531 + /* 90526 */ MCD_OPC_Decode, + 160, + 26, + 177, + 3, // Opcode: LDTRWi + /* 90531 */ MCD_OPC_FilterValue, + 1, + 167, + 54, + 0, // Skip to: 104527 + /* 90536 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 90539 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 90549 + /* 90544 */ MCD_OPC_Decode, + 221, + 25, + 182, + 3, // Opcode: LDRWroW + /* 90549 */ MCD_OPC_FilterValue, + 3, + 149, + 54, + 0, // Skip to: 104527 + /* 90554 */ MCD_OPC_Decode, + 222, + 25, + 183, + 3, // Opcode: LDRWroX + /* 90559 */ MCD_OPC_FilterValue, + 3, + 139, + 54, + 0, // Skip to: 104527 + /* 90564 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 132, + 54, + 0, // Skip to: 104527 + /* 90571 */ MCD_OPC_Decode, + 220, + 25, + 177, + 3, // Opcode: LDRWpre + /* 90576 */ MCD_OPC_FilterValue, + 2, + 10, + 1, + 0, // Skip to: 90847 + /* 90581 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 90584 */ MCD_OPC_FilterValue, + 0, + 178, + 0, + 0, // Skip to: 90767 + /* 90589 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 90592 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 90602 + /* 90597 */ MCD_OPC_Decode, + 204, + 26, + 177, + 3, // Opcode: LDURSWi + /* 90602 */ MCD_OPC_FilterValue, + 1, + 96, + 54, + 0, // Skip to: 104527 + /* 90607 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 90610 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 90625 + /* 90615 */ MCD_OPC_CheckPredicate, + 18, + 83, + 54, + 0, // Skip to: 104527 + /* 90620 */ MCD_OPC_Decode, + 132, + 24, + 181, + 3, // Opcode: LDADDAW + /* 90625 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 90640 + /* 90630 */ MCD_OPC_CheckPredicate, + 18, + 68, + 54, + 0, // Skip to: 104527 + /* 90635 */ MCD_OPC_Decode, + 171, + 24, + 181, + 3, // Opcode: LDCLRAW + /* 90640 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 90655 + /* 90645 */ MCD_OPC_CheckPredicate, + 18, + 53, + 54, + 0, // Skip to: 104527 + /* 90650 */ MCD_OPC_Decode, + 187, + 24, + 181, + 3, // Opcode: LDEORAW + /* 90655 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 90670 + /* 90660 */ MCD_OPC_CheckPredicate, + 18, + 38, + 54, + 0, // Skip to: 104527 + /* 90665 */ MCD_OPC_Decode, + 239, + 25, + 181, + 3, // Opcode: LDSETAW + /* 90670 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 90685 + /* 90675 */ MCD_OPC_CheckPredicate, + 18, + 23, + 54, + 0, // Skip to: 104527 + /* 90680 */ MCD_OPC_Decode, + 255, + 25, + 181, + 3, // Opcode: LDSMAXAW + /* 90685 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 90700 + /* 90690 */ MCD_OPC_CheckPredicate, + 18, + 8, + 54, + 0, // Skip to: 104527 + /* 90695 */ MCD_OPC_Decode, + 143, + 26, + 181, + 3, // Opcode: LDSMINAW + /* 90700 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 90715 + /* 90705 */ MCD_OPC_CheckPredicate, + 18, + 249, + 53, + 0, // Skip to: 104527 + /* 90710 */ MCD_OPC_Decode, + 168, + 26, + 181, + 3, // Opcode: LDUMAXAW + /* 90715 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 90730 + /* 90720 */ MCD_OPC_CheckPredicate, + 18, + 234, + 53, + 0, // Skip to: 104527 + /* 90725 */ MCD_OPC_Decode, + 184, + 26, + 181, + 3, // Opcode: LDUMINAW + /* 90730 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 90745 + /* 90735 */ MCD_OPC_CheckPredicate, + 18, + 219, + 53, + 0, // Skip to: 104527 + /* 90740 */ MCD_OPC_Decode, + 131, + 41, + 181, + 3, // Opcode: SWPAW + /* 90745 */ MCD_OPC_FilterValue, + 12, + 209, + 53, + 0, // Skip to: 104527 + /* 90750 */ MCD_OPC_CheckPredicate, + 47, + 204, + 53, + 0, // Skip to: 104527 + /* 90755 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 197, + 53, + 0, // Skip to: 104527 + /* 90762 */ MCD_OPC_Decode, + 144, + 24, + 184, + 3, // Opcode: LDAPRW + /* 90767 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 90784 + /* 90772 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 180, + 53, + 0, // Skip to: 104527 + /* 90779 */ MCD_OPC_Decode, + 207, + 25, + 177, + 3, // Opcode: LDRSWpost + /* 90784 */ MCD_OPC_FilterValue, + 2, + 41, + 0, + 0, // Skip to: 90830 + /* 90789 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 90792 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 90802 + /* 90797 */ MCD_OPC_Decode, + 159, + 26, + 177, + 3, // Opcode: LDTRSWi + /* 90802 */ MCD_OPC_FilterValue, + 1, + 152, + 53, + 0, // Skip to: 104527 + /* 90807 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 90810 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 90820 + /* 90815 */ MCD_OPC_Decode, + 209, + 25, + 185, + 3, // Opcode: LDRSWroW + /* 90820 */ MCD_OPC_FilterValue, + 3, + 134, + 53, + 0, // Skip to: 104527 + /* 90825 */ MCD_OPC_Decode, + 210, + 25, + 186, + 3, // Opcode: LDRSWroX + /* 90830 */ MCD_OPC_FilterValue, + 3, + 124, + 53, + 0, // Skip to: 104527 + /* 90835 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 117, + 53, + 0, // Skip to: 104527 + /* 90842 */ MCD_OPC_Decode, + 208, + 25, + 177, + 3, // Opcode: LDRSWpre + /* 90847 */ MCD_OPC_FilterValue, + 3, + 201, + 0, + 0, // Skip to: 91053 + /* 90852 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 90855 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 90877 + /* 90860 */ MCD_OPC_CheckPredicate, + 18, + 94, + 53, + 0, // Skip to: 104527 + /* 90865 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 87, + 53, + 0, // Skip to: 104527 + /* 90872 */ MCD_OPC_Decode, + 130, + 24, + 181, + 3, // Opcode: LDADDALW + /* 90877 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 90899 + /* 90882 */ MCD_OPC_CheckPredicate, + 18, + 72, + 53, + 0, // Skip to: 104527 + /* 90887 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 65, + 53, + 0, // Skip to: 104527 + /* 90894 */ MCD_OPC_Decode, + 169, + 24, + 181, + 3, // Opcode: LDCLRALW + /* 90899 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 90921 + /* 90904 */ MCD_OPC_CheckPredicate, + 18, + 50, + 53, + 0, // Skip to: 104527 + /* 90909 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 43, + 53, + 0, // Skip to: 104527 + /* 90916 */ MCD_OPC_Decode, + 185, + 24, + 181, + 3, // Opcode: LDEORALW + /* 90921 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 90943 + /* 90926 */ MCD_OPC_CheckPredicate, + 18, + 28, + 53, + 0, // Skip to: 104527 + /* 90931 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 21, + 53, + 0, // Skip to: 104527 + /* 90938 */ MCD_OPC_Decode, + 237, + 25, + 181, + 3, // Opcode: LDSETALW + /* 90943 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 90965 + /* 90948 */ MCD_OPC_CheckPredicate, + 18, + 6, + 53, + 0, // Skip to: 104527 + /* 90953 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 255, + 52, + 0, // Skip to: 104527 + /* 90960 */ MCD_OPC_Decode, + 253, + 25, + 181, + 3, // Opcode: LDSMAXALW + /* 90965 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 90987 + /* 90970 */ MCD_OPC_CheckPredicate, + 18, + 240, + 52, + 0, // Skip to: 104527 + /* 90975 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 233, + 52, + 0, // Skip to: 104527 + /* 90982 */ MCD_OPC_Decode, + 141, + 26, + 181, + 3, // Opcode: LDSMINALW + /* 90987 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 91009 + /* 90992 */ MCD_OPC_CheckPredicate, + 18, + 218, + 52, + 0, // Skip to: 104527 + /* 90997 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 211, + 52, + 0, // Skip to: 104527 + /* 91004 */ MCD_OPC_Decode, + 166, + 26, + 181, + 3, // Opcode: LDUMAXALW + /* 91009 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 91031 + /* 91014 */ MCD_OPC_CheckPredicate, + 18, + 196, + 52, + 0, // Skip to: 104527 + /* 91019 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 189, + 52, + 0, // Skip to: 104527 + /* 91026 */ MCD_OPC_Decode, + 182, + 26, + 181, + 3, // Opcode: LDUMINALW + /* 91031 */ MCD_OPC_FilterValue, + 32, + 179, + 52, + 0, // Skip to: 104527 + /* 91036 */ MCD_OPC_CheckPredicate, + 18, + 174, + 52, + 0, // Skip to: 104527 + /* 91041 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 167, + 52, + 0, // Skip to: 104527 + /* 91048 */ MCD_OPC_Decode, + 129, + 41, + 181, + 3, // Opcode: SWPALW + /* 91053 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 91063 + /* 91058 */ MCD_OPC_Decode, + 132, + 40, + 187, + 3, // Opcode: STRWui + /* 91063 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 91073 + /* 91068 */ MCD_OPC_Decode, + 223, + 25, + 187, + 3, // Opcode: LDRWui + /* 91073 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 91083 + /* 91078 */ MCD_OPC_Decode, + 211, + 25, + 187, + 3, // Opcode: LDRSWui + /* 91083 */ MCD_OPC_FilterValue, + 8, + 56, + 0, + 0, // Skip to: 91144 + /* 91088 */ MCD_OPC_ExtractField, + 10, + 5, // Inst{14-10} ... + /* 91091 */ MCD_OPC_FilterValue, + 0, + 19, + 0, + 0, // Skip to: 91115 + /* 91096 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 112, + 52, + 0, // Skip to: 104527 + /* 91103 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 105, + 52, + 0, // Skip to: 104527 + /* 91110 */ MCD_OPC_Decode, + 145, + 7, + 192, + 3, // Opcode: ADCSXr + /* 91115 */ MCD_OPC_FilterValue, + 1, + 95, + 52, + 0, // Skip to: 104527 + /* 91120 */ MCD_OPC_CheckPredicate, + 41, + 90, + 52, + 0, // Skip to: 104527 + /* 91125 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 83, + 52, + 0, // Skip to: 104527 + /* 91132 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 76, + 52, + 0, // Skip to: 104527 + /* 91139 */ MCD_OPC_Decode, + 191, + 29, + 201, + 3, // Opcode: RMIF + /* 91144 */ MCD_OPC_FilterValue, + 9, + 51, + 0, + 0, // Skip to: 91200 + /* 91149 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 91152 */ MCD_OPC_FilterValue, + 0, + 19, + 0, + 0, // Skip to: 91176 + /* 91157 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 51, + 52, + 0, // Skip to: 104527 + /* 91164 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 44, + 52, + 0, // Skip to: 104527 + /* 91171 */ MCD_OPC_Decode, + 179, + 9, + 202, + 3, // Opcode: CCMNXr + /* 91176 */ MCD_OPC_FilterValue, + 2, + 34, + 52, + 0, // Skip to: 104527 + /* 91181 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 27, + 52, + 0, // Skip to: 104527 + /* 91188 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 20, + 52, + 0, // Skip to: 104527 + /* 91195 */ MCD_OPC_Decode, + 178, + 9, + 203, + 3, // Opcode: CCMNXi + /* 91200 */ MCD_OPC_FilterValue, + 11, + 10, + 52, + 0, // Skip to: 104527 + /* 91205 */ MCD_OPC_CheckPredicate, + 20, + 5, + 52, + 0, // Skip to: 104527 + /* 91210 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 254, + 51, + 0, // Skip to: 104527 + /* 91217 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 247, + 51, + 0, // Skip to: 104527 + /* 91224 */ MCD_OPC_Decode, + 181, + 40, + 194, + 3, // Opcode: SUBPS + /* 91229 */ MCD_OPC_FilterValue, + 6, + 93, + 3, + 0, // Skip to: 92095 + /* 91234 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 91237 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 91247 + /* 91242 */ MCD_OPC_Decode, + 229, + 28, + 204, + 3, // Opcode: PRFMl + /* 91247 */ MCD_OPC_FilterValue, + 1, + 84, + 1, + 0, // Skip to: 91592 + /* 91252 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 91255 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 91277 + /* 91260 */ MCD_OPC_CheckPredicate, + 45, + 206, + 51, + 0, // Skip to: 104527 + /* 91265 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 199, + 51, + 0, // Skip to: 104527 + /* 91272 */ MCD_OPC_Decode, + 179, + 39, + 177, + 3, // Opcode: STLURXi + /* 91277 */ MCD_OPC_FilterValue, + 1, + 70, + 0, + 0, // Skip to: 91352 + /* 91282 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 91285 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 91307 + /* 91290 */ MCD_OPC_CheckPredicate, + 20, + 176, + 51, + 0, // Skip to: 104527 + /* 91295 */ MCD_OPC_CheckField, + 12, + 9, + 0, + 169, + 51, + 0, // Skip to: 104527 + /* 91302 */ MCD_OPC_Decode, + 163, + 40, + 205, + 3, // Opcode: STZGM + /* 91307 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 91322 + /* 91312 */ MCD_OPC_CheckPredicate, + 20, + 154, + 51, + 0, // Skip to: 104527 + /* 91317 */ MCD_OPC_Decode, + 164, + 39, + 206, + 3, // Opcode: STGPostIndex + /* 91322 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 91337 + /* 91327 */ MCD_OPC_CheckPredicate, + 20, + 139, + 51, + 0, // Skip to: 104527 + /* 91332 */ MCD_OPC_Decode, + 162, + 39, + 207, + 3, // Opcode: STGOffset + /* 91337 */ MCD_OPC_FilterValue, + 3, + 129, + 51, + 0, // Skip to: 104527 + /* 91342 */ MCD_OPC_CheckPredicate, + 20, + 124, + 51, + 0, // Skip to: 104527 + /* 91347 */ MCD_OPC_Decode, + 167, + 39, + 206, + 3, // Opcode: STGPreIndex + /* 91352 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 91374 + /* 91357 */ MCD_OPC_CheckPredicate, + 45, + 109, + 51, + 0, // Skip to: 104527 + /* 91362 */ MCD_OPC_CheckField, + 10, + 2, + 0, + 102, + 51, + 0, // Skip to: 104527 + /* 91369 */ MCD_OPC_Decode, + 153, + 24, + 177, + 3, // Opcode: LDAPURXi + /* 91374 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 91442 + /* 91379 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 91382 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 91397 + /* 91387 */ MCD_OPC_CheckPredicate, + 20, + 79, + 51, + 0, // Skip to: 104527 + /* 91392 */ MCD_OPC_Decode, + 213, + 24, + 208, + 3, // Opcode: LDG + /* 91397 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 91412 + /* 91402 */ MCD_OPC_CheckPredicate, + 20, + 64, + 51, + 0, // Skip to: 104527 + /* 91407 */ MCD_OPC_Decode, + 165, + 40, + 206, + 3, // Opcode: STZGPostIndex + /* 91412 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 91427 + /* 91417 */ MCD_OPC_CheckPredicate, + 20, + 49, + 51, + 0, // Skip to: 104527 + /* 91422 */ MCD_OPC_Decode, + 164, + 40, + 207, + 3, // Opcode: STZGOffset + /* 91427 */ MCD_OPC_FilterValue, + 3, + 39, + 51, + 0, // Skip to: 104527 + /* 91432 */ MCD_OPC_CheckPredicate, + 20, + 34, + 51, + 0, // Skip to: 104527 + /* 91437 */ MCD_OPC_Decode, + 166, + 40, + 206, + 3, // Opcode: STZGPreIndex + /* 91442 */ MCD_OPC_FilterValue, + 5, + 70, + 0, + 0, // Skip to: 91517 + /* 91447 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 91450 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 91472 + /* 91455 */ MCD_OPC_CheckPredicate, + 20, + 11, + 51, + 0, // Skip to: 104527 + /* 91460 */ MCD_OPC_CheckField, + 12, + 9, + 0, + 4, + 51, + 0, // Skip to: 104527 + /* 91467 */ MCD_OPC_Decode, + 161, + 39, + 205, + 3, // Opcode: STGM + /* 91472 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 91487 + /* 91477 */ MCD_OPC_CheckPredicate, + 20, + 245, + 50, + 0, // Skip to: 104527 + /* 91482 */ MCD_OPC_Decode, + 198, + 38, + 206, + 3, // Opcode: ST2GPostIndex + /* 91487 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 91502 + /* 91492 */ MCD_OPC_CheckPredicate, + 20, + 230, + 50, + 0, // Skip to: 104527 + /* 91497 */ MCD_OPC_Decode, + 197, + 38, + 207, + 3, // Opcode: ST2GOffset + /* 91502 */ MCD_OPC_FilterValue, + 3, + 220, + 50, + 0, // Skip to: 104527 + /* 91507 */ MCD_OPC_CheckPredicate, + 20, + 215, + 50, + 0, // Skip to: 104527 + /* 91512 */ MCD_OPC_Decode, + 199, + 38, + 206, + 3, // Opcode: ST2GPreIndex + /* 91517 */ MCD_OPC_FilterValue, + 7, + 205, + 50, + 0, // Skip to: 104527 + /* 91522 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 91525 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 91547 + /* 91530 */ MCD_OPC_CheckPredicate, + 20, + 192, + 50, + 0, // Skip to: 104527 + /* 91535 */ MCD_OPC_CheckField, + 12, + 9, + 0, + 185, + 50, + 0, // Skip to: 104527 + /* 91542 */ MCD_OPC_Decode, + 214, + 24, + 205, + 3, // Opcode: LDGM + /* 91547 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 91562 + /* 91552 */ MCD_OPC_CheckPredicate, + 20, + 170, + 50, + 0, // Skip to: 104527 + /* 91557 */ MCD_OPC_Decode, + 161, + 40, + 206, + 3, // Opcode: STZ2GPostIndex + /* 91562 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 91577 + /* 91567 */ MCD_OPC_CheckPredicate, + 20, + 155, + 50, + 0, // Skip to: 104527 + /* 91572 */ MCD_OPC_Decode, + 160, + 40, + 207, + 3, // Opcode: STZ2GOffset + /* 91577 */ MCD_OPC_FilterValue, + 3, + 145, + 50, + 0, // Skip to: 104527 + /* 91582 */ MCD_OPC_CheckPredicate, + 20, + 140, + 50, + 0, // Skip to: 104527 + /* 91587 */ MCD_OPC_Decode, + 162, + 40, + 206, + 3, // Opcode: STZ2GPreIndex + /* 91592 */ MCD_OPC_FilterValue, + 2, + 130, + 50, + 0, // Skip to: 104527 + /* 91597 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 91600 */ MCD_OPC_FilterValue, + 0, + 154, + 0, + 0, // Skip to: 91759 + /* 91605 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 91608 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 91625 + /* 91613 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 107, + 50, + 0, // Skip to: 104527 + /* 91620 */ MCD_OPC_Decode, + 192, + 30, + 192, + 3, // Opcode: SBCXr + /* 91625 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 91635 + /* 91630 */ MCD_OPC_Decode, + 223, + 11, + 193, + 3, // Opcode: CSINVXr + /* 91635 */ MCD_OPC_FilterValue, + 6, + 87, + 50, + 0, // Skip to: 104527 + /* 91640 */ MCD_OPC_ExtractField, + 12, + 9, // Inst{20-12} ... + /* 91643 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 91653 + /* 91648 */ MCD_OPC_Decode, + 145, + 29, + 209, + 3, // Opcode: RBITXr + /* 91653 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 91663 + /* 91658 */ MCD_OPC_Decode, + 227, + 9, + 209, + 3, // Opcode: CLZXr + /* 91663 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 91678 + /* 91668 */ MCD_OPC_CheckPredicate, + 44, + 54, + 50, + 0, // Skip to: 104527 + /* 91673 */ MCD_OPC_Decode, + 173, + 28, + 210, + 3, // Opcode: PACIA + /* 91678 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 91693 + /* 91683 */ MCD_OPC_CheckPredicate, + 44, + 39, + 50, + 0, // Skip to: 104527 + /* 91688 */ MCD_OPC_Decode, + 170, + 8, + 210, + 3, // Opcode: AUTIA + /* 91693 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 91715 + /* 91698 */ MCD_OPC_CheckPredicate, + 44, + 24, + 50, + 0, // Skip to: 104527 + /* 91703 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 17, + 50, + 0, // Skip to: 104527 + /* 91710 */ MCD_OPC_Decode, + 181, + 28, + 211, + 3, // Opcode: PACIZA + /* 91715 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 91737 + /* 91720 */ MCD_OPC_CheckPredicate, + 44, + 2, + 50, + 0, // Skip to: 104527 + /* 91725 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 251, + 49, + 0, // Skip to: 104527 + /* 91732 */ MCD_OPC_Decode, + 178, + 8, + 211, + 3, // Opcode: AUTIZA + /* 91737 */ MCD_OPC_FilterValue, + 20, + 241, + 49, + 0, // Skip to: 104527 + /* 91742 */ MCD_OPC_CheckPredicate, + 44, + 236, + 49, + 0, // Skip to: 104527 + /* 91747 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 229, + 49, + 0, // Skip to: 104527 + /* 91754 */ MCD_OPC_Decode, + 238, + 47, + 211, + 3, // Opcode: XPACI + /* 91759 */ MCD_OPC_FilterValue, + 1, + 137, + 0, + 0, // Skip to: 91901 + /* 91764 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 91767 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 91777 + /* 91772 */ MCD_OPC_Decode, + 225, + 11, + 193, + 3, // Opcode: CSNEGXr + /* 91777 */ MCD_OPC_FilterValue, + 6, + 201, + 49, + 0, // Skip to: 104527 + /* 91782 */ MCD_OPC_ExtractField, + 12, + 9, // Inst{20-12} ... + /* 91785 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 91795 + /* 91790 */ MCD_OPC_Decode, + 160, + 29, + 209, + 3, // Opcode: REV16Xr + /* 91795 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 91805 + /* 91800 */ MCD_OPC_Decode, + 215, + 9, + 209, + 3, // Opcode: CLSXr + /* 91805 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 91820 + /* 91810 */ MCD_OPC_CheckPredicate, + 44, + 168, + 49, + 0, // Skip to: 104527 + /* 91815 */ MCD_OPC_Decode, + 177, + 28, + 210, + 3, // Opcode: PACIB + /* 91820 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 91835 + /* 91825 */ MCD_OPC_CheckPredicate, + 44, + 153, + 49, + 0, // Skip to: 104527 + /* 91830 */ MCD_OPC_Decode, + 174, + 8, + 210, + 3, // Opcode: AUTIB + /* 91835 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 91857 + /* 91840 */ MCD_OPC_CheckPredicate, + 44, + 138, + 49, + 0, // Skip to: 104527 + /* 91845 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 131, + 49, + 0, // Skip to: 104527 + /* 91852 */ MCD_OPC_Decode, + 182, + 28, + 211, + 3, // Opcode: PACIZB + /* 91857 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 91879 + /* 91862 */ MCD_OPC_CheckPredicate, + 44, + 116, + 49, + 0, // Skip to: 104527 + /* 91867 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 109, + 49, + 0, // Skip to: 104527 + /* 91874 */ MCD_OPC_Decode, + 179, + 8, + 211, + 3, // Opcode: AUTIZB + /* 91879 */ MCD_OPC_FilterValue, + 20, + 99, + 49, + 0, // Skip to: 104527 + /* 91884 */ MCD_OPC_CheckPredicate, + 44, + 94, + 49, + 0, // Skip to: 104527 + /* 91889 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 87, + 49, + 0, // Skip to: 104527 + /* 91896 */ MCD_OPC_Decode, + 237, + 47, + 211, + 3, // Opcode: XPACD + /* 91901 */ MCD_OPC_FilterValue, + 2, + 92, + 0, + 0, // Skip to: 91998 + /* 91906 */ MCD_OPC_ExtractField, + 12, + 12, // Inst{23-12} ... + /* 91909 */ MCD_OPC_FilterValue, + 128, + 24, + 5, + 0, + 0, // Skip to: 91920 + /* 91915 */ MCD_OPC_Decode, + 163, + 29, + 209, + 3, // Opcode: REV32Xr + /* 91920 */ MCD_OPC_FilterValue, + 144, + 24, + 10, + 0, + 0, // Skip to: 91936 + /* 91926 */ MCD_OPC_CheckPredicate, + 44, + 52, + 49, + 0, // Skip to: 104527 + /* 91931 */ MCD_OPC_Decode, + 168, + 28, + 210, + 3, // Opcode: PACDA + /* 91936 */ MCD_OPC_FilterValue, + 145, + 24, + 10, + 0, + 0, // Skip to: 91952 + /* 91942 */ MCD_OPC_CheckPredicate, + 44, + 36, + 49, + 0, // Skip to: 104527 + /* 91947 */ MCD_OPC_Decode, + 166, + 8, + 210, + 3, // Opcode: AUTDA + /* 91952 */ MCD_OPC_FilterValue, + 146, + 24, + 17, + 0, + 0, // Skip to: 91975 + /* 91958 */ MCD_OPC_CheckPredicate, + 44, + 20, + 49, + 0, // Skip to: 104527 + /* 91963 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 13, + 49, + 0, // Skip to: 104527 + /* 91970 */ MCD_OPC_Decode, + 170, + 28, + 211, + 3, // Opcode: PACDZA + /* 91975 */ MCD_OPC_FilterValue, + 147, + 24, + 2, + 49, + 0, // Skip to: 104527 + /* 91981 */ MCD_OPC_CheckPredicate, + 44, + 253, + 48, + 0, // Skip to: 104527 + /* 91986 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 246, + 48, + 0, // Skip to: 104527 + /* 91993 */ MCD_OPC_Decode, + 168, + 8, + 211, + 3, // Opcode: AUTDZA + /* 91998 */ MCD_OPC_FilterValue, + 3, + 236, + 48, + 0, // Skip to: 104527 + /* 92003 */ MCD_OPC_ExtractField, + 12, + 12, // Inst{23-12} ... + /* 92006 */ MCD_OPC_FilterValue, + 128, + 24, + 5, + 0, + 0, // Skip to: 92017 + /* 92012 */ MCD_OPC_Decode, + 182, + 29, + 209, + 3, // Opcode: REVXr + /* 92017 */ MCD_OPC_FilterValue, + 144, + 24, + 10, + 0, + 0, // Skip to: 92033 + /* 92023 */ MCD_OPC_CheckPredicate, + 44, + 211, + 48, + 0, // Skip to: 104527 + /* 92028 */ MCD_OPC_Decode, + 169, + 28, + 210, + 3, // Opcode: PACDB + /* 92033 */ MCD_OPC_FilterValue, + 145, + 24, + 10, + 0, + 0, // Skip to: 92049 + /* 92039 */ MCD_OPC_CheckPredicate, + 44, + 195, + 48, + 0, // Skip to: 104527 + /* 92044 */ MCD_OPC_Decode, + 167, + 8, + 210, + 3, // Opcode: AUTDB + /* 92049 */ MCD_OPC_FilterValue, + 146, + 24, + 17, + 0, + 0, // Skip to: 92072 + /* 92055 */ MCD_OPC_CheckPredicate, + 44, + 179, + 48, + 0, // Skip to: 104527 + /* 92060 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 172, + 48, + 0, // Skip to: 104527 + /* 92067 */ MCD_OPC_Decode, + 171, + 28, + 211, + 3, // Opcode: PACDZB + /* 92072 */ MCD_OPC_FilterValue, + 147, + 24, + 161, + 48, + 0, // Skip to: 104527 + /* 92078 */ MCD_OPC_CheckPredicate, + 44, + 156, + 48, + 0, // Skip to: 104527 + /* 92083 */ MCD_OPC_CheckField, + 5, + 5, + 31, + 149, + 48, + 0, // Skip to: 104527 + /* 92090 */ MCD_OPC_Decode, + 169, + 8, + 211, + 3, // Opcode: AUTDZB + /* 92095 */ MCD_OPC_FilterValue, + 7, + 139, + 48, + 0, // Skip to: 104527 + /* 92100 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 92103 */ MCD_OPC_FilterValue, + 0, + 65, + 2, + 0, // Skip to: 92685 + /* 92108 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 92111 */ MCD_OPC_FilterValue, + 0, + 127, + 1, + 0, // Skip to: 92499 + /* 92116 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 92119 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 92129 + /* 92124 */ MCD_OPC_Decode, + 153, + 40, + 177, + 3, // Opcode: STURXi + /* 92129 */ MCD_OPC_FilterValue, + 1, + 212, + 0, + 0, // Skip to: 92346 + /* 92134 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 92137 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 92152 + /* 92142 */ MCD_OPC_CheckPredicate, + 18, + 92, + 48, + 0, // Skip to: 104527 + /* 92147 */ MCD_OPC_Decode, + 141, + 24, + 212, + 3, // Opcode: LDADDX + /* 92152 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 92167 + /* 92157 */ MCD_OPC_CheckPredicate, + 18, + 77, + 48, + 0, // Skip to: 104527 + /* 92162 */ MCD_OPC_Decode, + 180, + 24, + 212, + 3, // Opcode: LDCLRX + /* 92167 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 92182 + /* 92172 */ MCD_OPC_CheckPredicate, + 18, + 62, + 48, + 0, // Skip to: 104527 + /* 92177 */ MCD_OPC_Decode, + 196, + 24, + 212, + 3, // Opcode: LDEORX + /* 92182 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 92197 + /* 92187 */ MCD_OPC_CheckPredicate, + 18, + 47, + 48, + 0, // Skip to: 104527 + /* 92192 */ MCD_OPC_Decode, + 248, + 25, + 212, + 3, // Opcode: LDSETX + /* 92197 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 92212 + /* 92202 */ MCD_OPC_CheckPredicate, + 18, + 32, + 48, + 0, // Skip to: 104527 + /* 92207 */ MCD_OPC_Decode, + 136, + 26, + 212, + 3, // Opcode: LDSMAXX + /* 92212 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 92227 + /* 92217 */ MCD_OPC_CheckPredicate, + 18, + 17, + 48, + 0, // Skip to: 104527 + /* 92222 */ MCD_OPC_Decode, + 152, + 26, + 212, + 3, // Opcode: LDSMINX + /* 92227 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 92242 + /* 92232 */ MCD_OPC_CheckPredicate, + 18, + 2, + 48, + 0, // Skip to: 104527 + /* 92237 */ MCD_OPC_Decode, + 177, + 26, + 212, + 3, // Opcode: LDUMAXX + /* 92242 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 92257 + /* 92247 */ MCD_OPC_CheckPredicate, + 18, + 243, + 47, + 0, // Skip to: 104527 + /* 92252 */ MCD_OPC_Decode, + 193, + 26, + 212, + 3, // Opcode: LDUMINX + /* 92257 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 92272 + /* 92262 */ MCD_OPC_CheckPredicate, + 18, + 228, + 47, + 0, // Skip to: 104527 + /* 92267 */ MCD_OPC_Decode, + 140, + 41, + 212, + 3, // Opcode: SWPX + /* 92272 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 92294 + /* 92277 */ MCD_OPC_CheckPredicate, + 48, + 213, + 47, + 0, // Skip to: 104527 + /* 92282 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 206, + 47, + 0, // Skip to: 104527 + /* 92289 */ MCD_OPC_Decode, + 158, + 39, + 213, + 3, // Opcode: ST64B + /* 92294 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 92309 + /* 92299 */ MCD_OPC_CheckPredicate, + 48, + 191, + 47, + 0, // Skip to: 104527 + /* 92304 */ MCD_OPC_Decode, + 160, + 39, + 214, + 3, // Opcode: ST64BV0 + /* 92309 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 92324 + /* 92314 */ MCD_OPC_CheckPredicate, + 48, + 176, + 47, + 0, // Skip to: 104527 + /* 92319 */ MCD_OPC_Decode, + 159, + 39, + 214, + 3, // Opcode: ST64BV + /* 92324 */ MCD_OPC_FilterValue, + 13, + 166, + 47, + 0, // Skip to: 104527 + /* 92329 */ MCD_OPC_CheckPredicate, + 48, + 161, + 47, + 0, // Skip to: 104527 + /* 92334 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 154, + 47, + 0, // Skip to: 104527 + /* 92341 */ MCD_OPC_Decode, + 253, + 23, + 213, + 3, // Opcode: LD64B + /* 92346 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 92356 + /* 92351 */ MCD_OPC_Decode, + 207, + 26, + 177, + 3, // Opcode: LDURXi + /* 92356 */ MCD_OPC_FilterValue, + 3, + 134, + 47, + 0, // Skip to: 104527 + /* 92361 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 92364 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 92379 + /* 92369 */ MCD_OPC_CheckPredicate, + 18, + 121, + 47, + 0, // Skip to: 104527 + /* 92374 */ MCD_OPC_Decode, + 139, + 24, + 212, + 3, // Opcode: LDADDLX + /* 92379 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 92394 + /* 92384 */ MCD_OPC_CheckPredicate, + 18, + 106, + 47, + 0, // Skip to: 104527 + /* 92389 */ MCD_OPC_Decode, + 178, + 24, + 212, + 3, // Opcode: LDCLRLX + /* 92394 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 92409 + /* 92399 */ MCD_OPC_CheckPredicate, + 18, + 91, + 47, + 0, // Skip to: 104527 + /* 92404 */ MCD_OPC_Decode, + 194, + 24, + 212, + 3, // Opcode: LDEORLX + /* 92409 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 92424 + /* 92414 */ MCD_OPC_CheckPredicate, + 18, + 76, + 47, + 0, // Skip to: 104527 + /* 92419 */ MCD_OPC_Decode, + 246, + 25, + 212, + 3, // Opcode: LDSETLX + /* 92424 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 92439 + /* 92429 */ MCD_OPC_CheckPredicate, + 18, + 61, + 47, + 0, // Skip to: 104527 + /* 92434 */ MCD_OPC_Decode, + 134, + 26, + 212, + 3, // Opcode: LDSMAXLX + /* 92439 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 92454 + /* 92444 */ MCD_OPC_CheckPredicate, + 18, + 46, + 47, + 0, // Skip to: 104527 + /* 92449 */ MCD_OPC_Decode, + 150, + 26, + 212, + 3, // Opcode: LDSMINLX + /* 92454 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 92469 + /* 92459 */ MCD_OPC_CheckPredicate, + 18, + 31, + 47, + 0, // Skip to: 104527 + /* 92464 */ MCD_OPC_Decode, + 175, + 26, + 212, + 3, // Opcode: LDUMAXLX + /* 92469 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 92484 + /* 92474 */ MCD_OPC_CheckPredicate, + 18, + 16, + 47, + 0, // Skip to: 104527 + /* 92479 */ MCD_OPC_Decode, + 191, + 26, + 212, + 3, // Opcode: LDUMINLX + /* 92484 */ MCD_OPC_FilterValue, + 8, + 6, + 47, + 0, // Skip to: 104527 + /* 92489 */ MCD_OPC_CheckPredicate, + 18, + 1, + 47, + 0, // Skip to: 104527 + /* 92494 */ MCD_OPC_Decode, + 138, + 41, + 212, + 3, // Opcode: SWPLX + /* 92499 */ MCD_OPC_FilterValue, + 1, + 46, + 0, + 0, // Skip to: 92550 + /* 92504 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 92507 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 92535 + /* 92512 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 92515 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 92525 + /* 92520 */ MCD_OPC_Decode, + 133, + 40, + 177, + 3, // Opcode: STRXpost + /* 92525 */ MCD_OPC_FilterValue, + 1, + 221, + 46, + 0, // Skip to: 104527 + /* 92530 */ MCD_OPC_Decode, + 225, + 25, + 177, + 3, // Opcode: LDRXpost + /* 92535 */ MCD_OPC_FilterValue, + 1, + 211, + 46, + 0, // Skip to: 104527 + /* 92540 */ MCD_OPC_CheckPredicate, + 44, + 206, + 46, + 0, // Skip to: 104527 + /* 92545 */ MCD_OPC_Decode, + 150, + 25, + 215, + 3, // Opcode: LDRAAindexed + /* 92550 */ MCD_OPC_FilterValue, + 2, + 79, + 0, + 0, // Skip to: 92634 + /* 92555 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 92558 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 92568 + /* 92563 */ MCD_OPC_Decode, + 144, + 40, + 177, + 3, // Opcode: STTRXi + /* 92568 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 92596 + /* 92573 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 92576 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 92586 + /* 92581 */ MCD_OPC_Decode, + 135, + 40, + 185, + 3, // Opcode: STRXroW + /* 92586 */ MCD_OPC_FilterValue, + 3, + 160, + 46, + 0, // Skip to: 104527 + /* 92591 */ MCD_OPC_Decode, + 136, + 40, + 186, + 3, // Opcode: STRXroX + /* 92596 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 92606 + /* 92601 */ MCD_OPC_Decode, + 161, + 26, + 177, + 3, // Opcode: LDTRXi + /* 92606 */ MCD_OPC_FilterValue, + 3, + 140, + 46, + 0, // Skip to: 104527 + /* 92611 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 92614 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 92624 + /* 92619 */ MCD_OPC_Decode, + 227, + 25, + 185, + 3, // Opcode: LDRXroW + /* 92624 */ MCD_OPC_FilterValue, + 3, + 122, + 46, + 0, // Skip to: 104527 + /* 92629 */ MCD_OPC_Decode, + 228, + 25, + 186, + 3, // Opcode: LDRXroX + /* 92634 */ MCD_OPC_FilterValue, + 3, + 112, + 46, + 0, // Skip to: 104527 + /* 92639 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 92642 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 92670 + /* 92647 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 92650 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 92660 + /* 92655 */ MCD_OPC_Decode, + 134, + 40, + 177, + 3, // Opcode: STRXpre + /* 92660 */ MCD_OPC_FilterValue, + 1, + 86, + 46, + 0, // Skip to: 104527 + /* 92665 */ MCD_OPC_Decode, + 226, + 25, + 177, + 3, // Opcode: LDRXpre + /* 92670 */ MCD_OPC_FilterValue, + 1, + 76, + 46, + 0, // Skip to: 104527 + /* 92675 */ MCD_OPC_CheckPredicate, + 44, + 71, + 46, + 0, // Skip to: 104527 + /* 92680 */ MCD_OPC_Decode, + 151, + 25, + 215, + 3, // Opcode: LDRAAwriteback + /* 92685 */ MCD_OPC_FilterValue, + 1, + 159, + 1, + 0, // Skip to: 93105 + /* 92690 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 92693 */ MCD_OPC_FilterValue, + 0, + 65, + 1, + 0, // Skip to: 93019 + /* 92698 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 92701 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 92711 + /* 92706 */ MCD_OPC_Decode, + 234, + 28, + 177, + 3, // Opcode: PRFUMi + /* 92711 */ MCD_OPC_FilterValue, + 1, + 160, + 0, + 0, // Skip to: 92876 + /* 92716 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 92719 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 92734 + /* 92724 */ MCD_OPC_CheckPredicate, + 18, + 22, + 46, + 0, // Skip to: 104527 + /* 92729 */ MCD_OPC_Decode, + 133, + 24, + 212, + 3, // Opcode: LDADDAX + /* 92734 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 92749 + /* 92739 */ MCD_OPC_CheckPredicate, + 18, + 7, + 46, + 0, // Skip to: 104527 + /* 92744 */ MCD_OPC_Decode, + 172, + 24, + 212, + 3, // Opcode: LDCLRAX + /* 92749 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 92764 + /* 92754 */ MCD_OPC_CheckPredicate, + 18, + 248, + 45, + 0, // Skip to: 104527 + /* 92759 */ MCD_OPC_Decode, + 188, + 24, + 212, + 3, // Opcode: LDEORAX + /* 92764 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 92779 + /* 92769 */ MCD_OPC_CheckPredicate, + 18, + 233, + 45, + 0, // Skip to: 104527 + /* 92774 */ MCD_OPC_Decode, + 240, + 25, + 212, + 3, // Opcode: LDSETAX + /* 92779 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 92794 + /* 92784 */ MCD_OPC_CheckPredicate, + 18, + 218, + 45, + 0, // Skip to: 104527 + /* 92789 */ MCD_OPC_Decode, + 128, + 26, + 212, + 3, // Opcode: LDSMAXAX + /* 92794 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 92809 + /* 92799 */ MCD_OPC_CheckPredicate, + 18, + 203, + 45, + 0, // Skip to: 104527 + /* 92804 */ MCD_OPC_Decode, + 144, + 26, + 212, + 3, // Opcode: LDSMINAX + /* 92809 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 92824 + /* 92814 */ MCD_OPC_CheckPredicate, + 18, + 188, + 45, + 0, // Skip to: 104527 + /* 92819 */ MCD_OPC_Decode, + 169, + 26, + 212, + 3, // Opcode: LDUMAXAX + /* 92824 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 92839 + /* 92829 */ MCD_OPC_CheckPredicate, + 18, + 173, + 45, + 0, // Skip to: 104527 + /* 92834 */ MCD_OPC_Decode, + 185, + 26, + 212, + 3, // Opcode: LDUMINAX + /* 92839 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 92854 + /* 92844 */ MCD_OPC_CheckPredicate, + 18, + 158, + 45, + 0, // Skip to: 104527 + /* 92849 */ MCD_OPC_Decode, + 132, + 41, + 212, + 3, // Opcode: SWPAX + /* 92854 */ MCD_OPC_FilterValue, + 12, + 148, + 45, + 0, // Skip to: 104527 + /* 92859 */ MCD_OPC_CheckPredicate, + 47, + 143, + 45, + 0, // Skip to: 104527 + /* 92864 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 136, + 45, + 0, // Skip to: 104527 + /* 92871 */ MCD_OPC_Decode, + 145, + 24, + 205, + 3, // Opcode: LDAPRX + /* 92876 */ MCD_OPC_FilterValue, + 3, + 126, + 45, + 0, // Skip to: 104527 + /* 92881 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 92884 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 92899 + /* 92889 */ MCD_OPC_CheckPredicate, + 18, + 113, + 45, + 0, // Skip to: 104527 + /* 92894 */ MCD_OPC_Decode, + 131, + 24, + 212, + 3, // Opcode: LDADDALX + /* 92899 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 92914 + /* 92904 */ MCD_OPC_CheckPredicate, + 18, + 98, + 45, + 0, // Skip to: 104527 + /* 92909 */ MCD_OPC_Decode, + 170, + 24, + 212, + 3, // Opcode: LDCLRALX + /* 92914 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 92929 + /* 92919 */ MCD_OPC_CheckPredicate, + 18, + 83, + 45, + 0, // Skip to: 104527 + /* 92924 */ MCD_OPC_Decode, + 186, + 24, + 212, + 3, // Opcode: LDEORALX + /* 92929 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 92944 + /* 92934 */ MCD_OPC_CheckPredicate, + 18, + 68, + 45, + 0, // Skip to: 104527 + /* 92939 */ MCD_OPC_Decode, + 238, + 25, + 212, + 3, // Opcode: LDSETALX + /* 92944 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 92959 + /* 92949 */ MCD_OPC_CheckPredicate, + 18, + 53, + 45, + 0, // Skip to: 104527 + /* 92954 */ MCD_OPC_Decode, + 254, + 25, + 212, + 3, // Opcode: LDSMAXALX + /* 92959 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 92974 + /* 92964 */ MCD_OPC_CheckPredicate, + 18, + 38, + 45, + 0, // Skip to: 104527 + /* 92969 */ MCD_OPC_Decode, + 142, + 26, + 212, + 3, // Opcode: LDSMINALX + /* 92974 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 92989 + /* 92979 */ MCD_OPC_CheckPredicate, + 18, + 23, + 45, + 0, // Skip to: 104527 + /* 92984 */ MCD_OPC_Decode, + 167, + 26, + 212, + 3, // Opcode: LDUMAXALX + /* 92989 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 93004 + /* 92994 */ MCD_OPC_CheckPredicate, + 18, + 8, + 45, + 0, // Skip to: 104527 + /* 92999 */ MCD_OPC_Decode, + 183, + 26, + 212, + 3, // Opcode: LDUMINALX + /* 93004 */ MCD_OPC_FilterValue, + 8, + 254, + 44, + 0, // Skip to: 104527 + /* 93009 */ MCD_OPC_CheckPredicate, + 18, + 249, + 44, + 0, // Skip to: 104527 + /* 93014 */ MCD_OPC_Decode, + 130, + 41, + 212, + 3, // Opcode: SWPALX + /* 93019 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 93041 + /* 93024 */ MCD_OPC_CheckPredicate, + 44, + 234, + 44, + 0, // Skip to: 104527 + /* 93029 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 227, + 44, + 0, // Skip to: 104527 + /* 93036 */ MCD_OPC_Decode, + 152, + 25, + 215, + 3, // Opcode: LDRABindexed + /* 93041 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 93083 + /* 93046 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 93049 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 93066 + /* 93054 */ MCD_OPC_CheckField, + 21, + 2, + 1, + 202, + 44, + 0, // Skip to: 104527 + /* 93061 */ MCD_OPC_Decode, + 230, + 28, + 216, + 3, // Opcode: PRFMroW + /* 93066 */ MCD_OPC_FilterValue, + 3, + 192, + 44, + 0, // Skip to: 104527 + /* 93071 */ MCD_OPC_CheckField, + 21, + 2, + 1, + 185, + 44, + 0, // Skip to: 104527 + /* 93078 */ MCD_OPC_Decode, + 231, + 28, + 217, + 3, // Opcode: PRFMroX + /* 93083 */ MCD_OPC_FilterValue, + 3, + 175, + 44, + 0, // Skip to: 104527 + /* 93088 */ MCD_OPC_CheckPredicate, + 44, + 170, + 44, + 0, // Skip to: 104527 + /* 93093 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 163, + 44, + 0, // Skip to: 104527 + /* 93100 */ MCD_OPC_Decode, + 153, + 25, + 215, + 3, // Opcode: LDRABwriteback + /* 93105 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 93133 + /* 93110 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 93113 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 93123 + /* 93118 */ MCD_OPC_Decode, + 137, + 40, + 187, + 3, // Opcode: STRXui + /* 93123 */ MCD_OPC_FilterValue, + 1, + 135, + 44, + 0, // Skip to: 104527 + /* 93128 */ MCD_OPC_Decode, + 229, + 25, + 187, + 3, // Opcode: LDRXui + /* 93133 */ MCD_OPC_FilterValue, + 3, + 12, + 0, + 0, // Skip to: 93150 + /* 93138 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 118, + 44, + 0, // Skip to: 104527 + /* 93145 */ MCD_OPC_Decode, + 232, + 28, + 187, + 3, // Opcode: PRFMui + /* 93150 */ MCD_OPC_FilterValue, + 4, + 108, + 44, + 0, // Skip to: 104527 + /* 93155 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 93158 */ MCD_OPC_FilterValue, + 0, + 37, + 0, + 0, // Skip to: 93200 + /* 93163 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 93166 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 93183 + /* 93171 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 85, + 44, + 0, // Skip to: 104527 + /* 93178 */ MCD_OPC_Decode, + 190, + 30, + 192, + 3, // Opcode: SBCSXr + /* 93183 */ MCD_OPC_FilterValue, + 2, + 75, + 44, + 0, // Skip to: 104527 + /* 93188 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 68, + 44, + 0, // Skip to: 104527 + /* 93195 */ MCD_OPC_Decode, + 183, + 9, + 202, + 3, // Opcode: CCMPXr + /* 93200 */ MCD_OPC_FilterValue, + 2, + 58, + 44, + 0, // Skip to: 104527 + /* 93205 */ MCD_OPC_CheckField, + 21, + 2, + 2, + 51, + 44, + 0, // Skip to: 104527 + /* 93212 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 44, + 44, + 0, // Skip to: 104527 + /* 93219 */ MCD_OPC_Decode, + 182, + 9, + 203, + 3, // Opcode: CCMPXi + /* 93224 */ MCD_OPC_FilterValue, + 7, + 34, + 44, + 0, // Skip to: 104527 + /* 93229 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 93232 */ MCD_OPC_FilterValue, + 0, + 238, + 10, + 0, // Skip to: 96035 + /* 93237 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 93240 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 93250 + /* 93245 */ MCD_OPC_Decode, + 212, + 25, + 218, + 3, // Opcode: LDRSl + /* 93250 */ MCD_OPC_FilterValue, + 2, + 240, + 9, + 0, // Skip to: 95799 + /* 93255 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 93258 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 93326 + /* 93263 */ MCD_OPC_ExtractField, + 15, + 6, // Inst{20-15} ... + /* 93266 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 93281 + /* 93271 */ MCD_OPC_CheckPredicate, + 49, + 243, + 43, + 0, // Skip to: 104527 + /* 93276 */ MCD_OPC_Decode, + 201, + 30, + 219, + 3, // Opcode: SCVTFSWSri + /* 93281 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 93296 + /* 93286 */ MCD_OPC_CheckPredicate, + 49, + 228, + 43, + 0, // Skip to: 104527 + /* 93291 */ MCD_OPC_Decode, + 190, + 42, + 219, + 3, // Opcode: UCVTFSWSri + /* 93296 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 93311 + /* 93301 */ MCD_OPC_CheckPredicate, + 49, + 213, + 43, + 0, // Skip to: 104527 + /* 93306 */ MCD_OPC_Decode, + 173, + 15, + 220, + 3, // Opcode: FCVTZSSWSri + /* 93311 */ MCD_OPC_FilterValue, + 51, + 203, + 43, + 0, // Skip to: 104527 + /* 93316 */ MCD_OPC_CheckPredicate, + 49, + 198, + 43, + 0, // Skip to: 104527 + /* 93321 */ MCD_OPC_Decode, + 208, + 15, + 220, + 3, // Opcode: FCVTZUSWSri + /* 93326 */ MCD_OPC_FilterValue, + 1, + 26, + 3, + 0, // Skip to: 94125 + /* 93331 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 93334 */ MCD_OPC_FilterValue, + 0, + 78, + 2, + 0, // Skip to: 93929 + /* 93339 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 93342 */ MCD_OPC_FilterValue, + 0, + 48, + 2, + 0, // Skip to: 93907 + /* 93347 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 93350 */ MCD_OPC_FilterValue, + 0, + 213, + 0, + 0, // Skip to: 93568 + /* 93355 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 93358 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 93373 + /* 93363 */ MCD_OPC_CheckPredicate, + 49, + 151, + 43, + 0, // Skip to: 104527 + /* 93368 */ MCD_OPC_Decode, + 232, + 14, + 221, + 3, // Opcode: FCVTNSUWSr + /* 93373 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 93388 + /* 93378 */ MCD_OPC_CheckPredicate, + 49, + 136, + 43, + 0, // Skip to: 104527 + /* 93383 */ MCD_OPC_Decode, + 248, + 14, + 221, + 3, // Opcode: FCVTNUUWSr + /* 93388 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 93403 + /* 93393 */ MCD_OPC_CheckPredicate, + 49, + 121, + 43, + 0, // Skip to: 104527 + /* 93398 */ MCD_OPC_Decode, + 207, + 30, + 222, + 3, // Opcode: SCVTFUWSri + /* 93403 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 93418 + /* 93408 */ MCD_OPC_CheckPredicate, + 49, + 106, + 43, + 0, // Skip to: 104527 + /* 93413 */ MCD_OPC_Decode, + 196, + 42, + 222, + 3, // Opcode: UCVTFUWSri + /* 93418 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 93433 + /* 93423 */ MCD_OPC_CheckPredicate, + 49, + 91, + 43, + 0, // Skip to: 104527 + /* 93428 */ MCD_OPC_Decode, + 166, + 14, + 221, + 3, // Opcode: FCVTASUWSr + /* 93433 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 93448 + /* 93438 */ MCD_OPC_CheckPredicate, + 49, + 76, + 43, + 0, // Skip to: 104527 + /* 93443 */ MCD_OPC_Decode, + 180, + 14, + 221, + 3, // Opcode: FCVTAUUWSr + /* 93448 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 93463 + /* 93453 */ MCD_OPC_CheckPredicate, + 49, + 61, + 43, + 0, // Skip to: 104527 + /* 93458 */ MCD_OPC_Decode, + 221, + 17, + 221, + 3, // Opcode: FMOVSWr + /* 93463 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 93478 + /* 93468 */ MCD_OPC_CheckPredicate, + 49, + 46, + 43, + 0, // Skip to: 104527 + /* 93473 */ MCD_OPC_Decode, + 225, + 17, + 222, + 3, // Opcode: FMOVWSr + /* 93478 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 93493 + /* 93483 */ MCD_OPC_CheckPredicate, + 49, + 31, + 43, + 0, // Skip to: 104527 + /* 93488 */ MCD_OPC_Decode, + 138, + 15, + 221, + 3, // Opcode: FCVTPSUWSr + /* 93493 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 93508 + /* 93498 */ MCD_OPC_CheckPredicate, + 49, + 16, + 43, + 0, // Skip to: 104527 + /* 93503 */ MCD_OPC_Decode, + 152, + 15, + 221, + 3, // Opcode: FCVTPUUWSr + /* 93508 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 93523 + /* 93513 */ MCD_OPC_CheckPredicate, + 49, + 1, + 43, + 0, // Skip to: 104527 + /* 93518 */ MCD_OPC_Decode, + 204, + 14, + 221, + 3, // Opcode: FCVTMSUWSr + /* 93523 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 93538 + /* 93528 */ MCD_OPC_CheckPredicate, + 49, + 242, + 42, + 0, // Skip to: 104527 + /* 93533 */ MCD_OPC_Decode, + 218, + 14, + 221, + 3, // Opcode: FCVTMUUWSr + /* 93538 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 93553 + /* 93543 */ MCD_OPC_CheckPredicate, + 49, + 227, + 42, + 0, // Skip to: 104527 + /* 93548 */ MCD_OPC_Decode, + 179, + 15, + 221, + 3, // Opcode: FCVTZSUWSr + /* 93553 */ MCD_OPC_FilterValue, + 25, + 217, + 42, + 0, // Skip to: 104527 + /* 93558 */ MCD_OPC_CheckPredicate, + 49, + 212, + 42, + 0, // Skip to: 104527 + /* 93563 */ MCD_OPC_Decode, + 214, + 15, + 221, + 3, // Opcode: FCVTZUUWSr + /* 93568 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 93636 + /* 93573 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 93576 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 93591 + /* 93581 */ MCD_OPC_CheckPredicate, + 49, + 189, + 42, + 0, // Skip to: 104527 + /* 93586 */ MCD_OPC_Decode, + 154, + 14, + 223, + 3, // Opcode: FCMPSrr + /* 93591 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 93606 + /* 93596 */ MCD_OPC_CheckPredicate, + 49, + 174, + 42, + 0, // Skip to: 104527 + /* 93601 */ MCD_OPC_Decode, + 153, + 14, + 224, + 3, // Opcode: FCMPSri + /* 93606 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 93621 + /* 93611 */ MCD_OPC_CheckPredicate, + 49, + 159, + 42, + 0, // Skip to: 104527 + /* 93616 */ MCD_OPC_Decode, + 150, + 14, + 223, + 3, // Opcode: FCMPESrr + /* 93621 */ MCD_OPC_FilterValue, + 24, + 149, + 42, + 0, // Skip to: 104527 + /* 93626 */ MCD_OPC_CheckPredicate, + 49, + 144, + 42, + 0, // Skip to: 104527 + /* 93631 */ MCD_OPC_Decode, + 149, + 14, + 224, + 3, // Opcode: FCMPESri + /* 93636 */ MCD_OPC_FilterValue, + 2, + 123, + 0, + 0, // Skip to: 93764 + /* 93641 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 93644 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 93659 + /* 93649 */ MCD_OPC_CheckPredicate, + 49, + 121, + 42, + 0, // Skip to: 104527 + /* 93654 */ MCD_OPC_Decode, + 223, + 17, + 225, + 3, // Opcode: FMOVSr + /* 93659 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 93674 + /* 93664 */ MCD_OPC_CheckPredicate, + 49, + 106, + 42, + 0, // Skip to: 104527 + /* 93669 */ MCD_OPC_Decode, + 161, + 18, + 225, + 3, // Opcode: FNEGSr + /* 93674 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 93689 + /* 93679 */ MCD_OPC_CheckPredicate, + 49, + 91, + 42, + 0, // Skip to: 104527 + /* 93684 */ MCD_OPC_Decode, + 146, + 19, + 225, + 3, // Opcode: FRINTNSr + /* 93689 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 93704 + /* 93694 */ MCD_OPC_CheckPredicate, + 49, + 76, + 42, + 0, // Skip to: 104527 + /* 93699 */ MCD_OPC_Decode, + 135, + 19, + 225, + 3, // Opcode: FRINTMSr + /* 93704 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 93719 + /* 93709 */ MCD_OPC_CheckPredicate, + 49, + 61, + 42, + 0, // Skip to: 104527 + /* 93714 */ MCD_OPC_Decode, + 241, + 18, + 225, + 3, // Opcode: FRINTASr + /* 93719 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 93734 + /* 93724 */ MCD_OPC_CheckPredicate, + 49, + 46, + 42, + 0, // Skip to: 104527 + /* 93729 */ MCD_OPC_Decode, + 168, + 19, + 225, + 3, // Opcode: FRINTXSr + /* 93734 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 93749 + /* 93739 */ MCD_OPC_CheckPredicate, + 24, + 31, + 42, + 0, // Skip to: 104527 + /* 93744 */ MCD_OPC_Decode, + 225, + 18, + 225, + 3, // Opcode: FRINT32ZSr + /* 93749 */ MCD_OPC_FilterValue, + 9, + 21, + 42, + 0, // Skip to: 104527 + /* 93754 */ MCD_OPC_CheckPredicate, + 24, + 16, + 42, + 0, // Skip to: 104527 + /* 93759 */ MCD_OPC_Decode, + 235, + 18, + 225, + 3, // Opcode: FRINT64ZSr + /* 93764 */ MCD_OPC_FilterValue, + 6, + 6, + 42, + 0, // Skip to: 104527 + /* 93769 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 93772 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 93787 + /* 93777 */ MCD_OPC_CheckPredicate, + 49, + 249, + 41, + 0, // Skip to: 104527 + /* 93782 */ MCD_OPC_Decode, + 213, + 12, + 225, + 3, // Opcode: FABSSr + /* 93787 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 93802 + /* 93792 */ MCD_OPC_CheckPredicate, + 49, + 234, + 41, + 0, // Skip to: 104527 + /* 93797 */ MCD_OPC_Decode, + 215, + 19, + 225, + 3, // Opcode: FSQRTSr + /* 93802 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 93817 + /* 93807 */ MCD_OPC_CheckPredicate, + 49, + 219, + 41, + 0, // Skip to: 104527 + /* 93812 */ MCD_OPC_Decode, + 193, + 14, + 226, + 3, // Opcode: FCVTDSr + /* 93817 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 93832 + /* 93822 */ MCD_OPC_CheckPredicate, + 49, + 204, + 41, + 0, // Skip to: 104527 + /* 93827 */ MCD_OPC_Decode, + 195, + 14, + 227, + 3, // Opcode: FCVTHSr + /* 93832 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 93847 + /* 93837 */ MCD_OPC_CheckPredicate, + 49, + 189, + 41, + 0, // Skip to: 104527 + /* 93842 */ MCD_OPC_Decode, + 157, + 19, + 225, + 3, // Opcode: FRINTPSr + /* 93847 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 93862 + /* 93852 */ MCD_OPC_CheckPredicate, + 49, + 174, + 41, + 0, // Skip to: 104527 + /* 93857 */ MCD_OPC_Decode, + 179, + 19, + 225, + 3, // Opcode: FRINTZSr + /* 93862 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 93877 + /* 93867 */ MCD_OPC_CheckPredicate, + 49, + 159, + 41, + 0, // Skip to: 104527 + /* 93872 */ MCD_OPC_Decode, + 252, + 18, + 225, + 3, // Opcode: FRINTISr + /* 93877 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 93892 + /* 93882 */ MCD_OPC_CheckPredicate, + 24, + 144, + 41, + 0, // Skip to: 104527 + /* 93887 */ MCD_OPC_Decode, + 220, + 18, + 225, + 3, // Opcode: FRINT32XSr + /* 93892 */ MCD_OPC_FilterValue, + 9, + 134, + 41, + 0, // Skip to: 104527 + /* 93897 */ MCD_OPC_CheckPredicate, + 24, + 129, + 41, + 0, // Skip to: 104527 + /* 93902 */ MCD_OPC_Decode, + 230, + 18, + 225, + 3, // Opcode: FRINT64XSr + /* 93907 */ MCD_OPC_FilterValue, + 1, + 119, + 41, + 0, // Skip to: 104527 + /* 93912 */ MCD_OPC_CheckPredicate, + 49, + 114, + 41, + 0, // Skip to: 104527 + /* 93917 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 107, + 41, + 0, // Skip to: 104527 + /* 93924 */ MCD_OPC_Decode, + 222, + 17, + 228, + 3, // Opcode: FMOVSi + /* 93929 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 93967 + /* 93934 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 93937 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 93952 + /* 93942 */ MCD_OPC_CheckPredicate, + 49, + 84, + 41, + 0, // Skip to: 104527 + /* 93947 */ MCD_OPC_Decode, + 163, + 13, + 229, + 3, // Opcode: FCCMPSrr + /* 93952 */ MCD_OPC_FilterValue, + 1, + 74, + 41, + 0, // Skip to: 104527 + /* 93957 */ MCD_OPC_CheckPredicate, + 49, + 69, + 41, + 0, // Skip to: 104527 + /* 93962 */ MCD_OPC_Decode, + 161, + 13, + 229, + 3, // Opcode: FCCMPESrr + /* 93967 */ MCD_OPC_FilterValue, + 2, + 138, + 0, + 0, // Skip to: 94110 + /* 93972 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 93975 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 93990 + /* 93980 */ MCD_OPC_CheckPredicate, + 49, + 46, + 41, + 0, // Skip to: 104527 + /* 93985 */ MCD_OPC_Decode, + 242, + 17, + 230, + 3, // Opcode: FMULSrr + /* 93990 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 94005 + /* 93995 */ MCD_OPC_CheckPredicate, + 49, + 31, + 41, + 0, // Skip to: 104527 + /* 94000 */ MCD_OPC_Decode, + 252, + 15, + 230, + 3, // Opcode: FDIVSrr + /* 94005 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 94020 + /* 94010 */ MCD_OPC_CheckPredicate, + 49, + 16, + 41, + 0, // Skip to: 104527 + /* 94015 */ MCD_OPC_Decode, + 132, + 13, + 230, + 3, // Opcode: FADDSrr + /* 94020 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 94035 + /* 94025 */ MCD_OPC_CheckPredicate, + 49, + 1, + 41, + 0, // Skip to: 104527 + /* 94030 */ MCD_OPC_Decode, + 232, + 19, + 230, + 3, // Opcode: FSUBSrr + /* 94035 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 94050 + /* 94040 */ MCD_OPC_CheckPredicate, + 49, + 242, + 40, + 0, // Skip to: 104527 + /* 94045 */ MCD_OPC_Decode, + 193, + 16, + 230, + 3, // Opcode: FMAXSrr + /* 94050 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 94065 + /* 94055 */ MCD_OPC_CheckPredicate, + 49, + 227, + 40, + 0, // Skip to: 104527 + /* 94060 */ MCD_OPC_Decode, + 255, + 16, + 230, + 3, // Opcode: FMINSrr + /* 94065 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 94080 + /* 94070 */ MCD_OPC_CheckPredicate, + 49, + 212, + 40, + 0, // Skip to: 104527 + /* 94075 */ MCD_OPC_Decode, + 164, + 16, + 230, + 3, // Opcode: FMAXNMSrr + /* 94080 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 94095 + /* 94085 */ MCD_OPC_CheckPredicate, + 49, + 197, + 40, + 0, // Skip to: 104527 + /* 94090 */ MCD_OPC_Decode, + 226, + 16, + 230, + 3, // Opcode: FMINNMSrr + /* 94095 */ MCD_OPC_FilterValue, + 8, + 187, + 40, + 0, // Skip to: 104527 + /* 94100 */ MCD_OPC_CheckPredicate, + 49, + 182, + 40, + 0, // Skip to: 104527 + /* 94105 */ MCD_OPC_Decode, + 190, + 18, + 230, + 3, // Opcode: FNMULSrr + /* 94110 */ MCD_OPC_FilterValue, + 3, + 172, + 40, + 0, // Skip to: 104527 + /* 94115 */ MCD_OPC_CheckPredicate, + 49, + 167, + 40, + 0, // Skip to: 104527 + /* 94120 */ MCD_OPC_Decode, + 163, + 14, + 231, + 3, // Opcode: FCSELSrrr + /* 94125 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 94193 + /* 94130 */ MCD_OPC_ExtractField, + 15, + 6, // Inst{20-15} ... + /* 94133 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 94148 + /* 94138 */ MCD_OPC_CheckPredicate, + 49, + 144, + 40, + 0, // Skip to: 104527 + /* 94143 */ MCD_OPC_Decode, + 199, + 30, + 232, + 3, // Opcode: SCVTFSWDri + /* 94148 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 94163 + /* 94153 */ MCD_OPC_CheckPredicate, + 49, + 129, + 40, + 0, // Skip to: 104527 + /* 94158 */ MCD_OPC_Decode, + 188, + 42, + 232, + 3, // Opcode: UCVTFSWDri + /* 94163 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 94178 + /* 94168 */ MCD_OPC_CheckPredicate, + 49, + 114, + 40, + 0, // Skip to: 104527 + /* 94173 */ MCD_OPC_Decode, + 171, + 15, + 233, + 3, // Opcode: FCVTZSSWDri + /* 94178 */ MCD_OPC_FilterValue, + 51, + 104, + 40, + 0, // Skip to: 104527 + /* 94183 */ MCD_OPC_CheckPredicate, + 49, + 99, + 40, + 0, // Skip to: 104527 + /* 94188 */ MCD_OPC_Decode, + 206, + 15, + 233, + 3, // Opcode: FCVTZUSWDri + /* 94193 */ MCD_OPC_FilterValue, + 3, + 26, + 3, + 0, // Skip to: 94992 + /* 94198 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 94201 */ MCD_OPC_FilterValue, + 0, + 78, + 2, + 0, // Skip to: 94796 + /* 94206 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 94209 */ MCD_OPC_FilterValue, + 0, + 48, + 2, + 0, // Skip to: 94774 + /* 94214 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 94217 */ MCD_OPC_FilterValue, + 0, + 198, + 0, + 0, // Skip to: 94420 + /* 94222 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 94225 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 94240 + /* 94230 */ MCD_OPC_CheckPredicate, + 49, + 52, + 40, + 0, // Skip to: 104527 + /* 94235 */ MCD_OPC_Decode, + 230, + 14, + 234, + 3, // Opcode: FCVTNSUWDr + /* 94240 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 94255 + /* 94245 */ MCD_OPC_CheckPredicate, + 49, + 37, + 40, + 0, // Skip to: 104527 + /* 94250 */ MCD_OPC_Decode, + 246, + 14, + 234, + 3, // Opcode: FCVTNUUWDr + /* 94255 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 94270 + /* 94260 */ MCD_OPC_CheckPredicate, + 49, + 22, + 40, + 0, // Skip to: 104527 + /* 94265 */ MCD_OPC_Decode, + 205, + 30, + 157, + 2, // Opcode: SCVTFUWDri + /* 94270 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 94285 + /* 94275 */ MCD_OPC_CheckPredicate, + 49, + 7, + 40, + 0, // Skip to: 104527 + /* 94280 */ MCD_OPC_Decode, + 194, + 42, + 157, + 2, // Opcode: UCVTFUWDri + /* 94285 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 94300 + /* 94290 */ MCD_OPC_CheckPredicate, + 49, + 248, + 39, + 0, // Skip to: 104527 + /* 94295 */ MCD_OPC_Decode, + 164, + 14, + 234, + 3, // Opcode: FCVTASUWDr + /* 94300 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 94315 + /* 94305 */ MCD_OPC_CheckPredicate, + 49, + 233, + 39, + 0, // Skip to: 104527 + /* 94310 */ MCD_OPC_Decode, + 178, + 14, + 234, + 3, // Opcode: FCVTAUUWDr + /* 94315 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 94330 + /* 94320 */ MCD_OPC_CheckPredicate, + 49, + 218, + 39, + 0, // Skip to: 104527 + /* 94325 */ MCD_OPC_Decode, + 136, + 15, + 234, + 3, // Opcode: FCVTPSUWDr + /* 94330 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 94345 + /* 94335 */ MCD_OPC_CheckPredicate, + 49, + 203, + 39, + 0, // Skip to: 104527 + /* 94340 */ MCD_OPC_Decode, + 150, + 15, + 234, + 3, // Opcode: FCVTPUUWDr + /* 94345 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 94360 + /* 94350 */ MCD_OPC_CheckPredicate, + 49, + 188, + 39, + 0, // Skip to: 104527 + /* 94355 */ MCD_OPC_Decode, + 202, + 14, + 234, + 3, // Opcode: FCVTMSUWDr + /* 94360 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 94375 + /* 94365 */ MCD_OPC_CheckPredicate, + 49, + 173, + 39, + 0, // Skip to: 104527 + /* 94370 */ MCD_OPC_Decode, + 216, + 14, + 234, + 3, // Opcode: FCVTMUUWDr + /* 94375 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 94390 + /* 94380 */ MCD_OPC_CheckPredicate, + 49, + 158, + 39, + 0, // Skip to: 104527 + /* 94385 */ MCD_OPC_Decode, + 177, + 15, + 234, + 3, // Opcode: FCVTZSUWDr + /* 94390 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 94405 + /* 94395 */ MCD_OPC_CheckPredicate, + 49, + 143, + 39, + 0, // Skip to: 104527 + /* 94400 */ MCD_OPC_Decode, + 212, + 15, + 234, + 3, // Opcode: FCVTZUUWDr + /* 94405 */ MCD_OPC_FilterValue, + 30, + 133, + 39, + 0, // Skip to: 104527 + /* 94410 */ MCD_OPC_CheckPredicate, + 50, + 128, + 39, + 0, // Skip to: 104527 + /* 94415 */ MCD_OPC_Decode, + 139, + 16, + 234, + 3, // Opcode: FJCVTZS + /* 94420 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 94488 + /* 94425 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 94428 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 94443 + /* 94433 */ MCD_OPC_CheckPredicate, + 49, + 105, + 39, + 0, // Skip to: 104527 + /* 94438 */ MCD_OPC_Decode, + 144, + 14, + 235, + 3, // Opcode: FCMPDrr + /* 94443 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 94458 + /* 94448 */ MCD_OPC_CheckPredicate, + 49, + 90, + 39, + 0, // Skip to: 104527 + /* 94453 */ MCD_OPC_Decode, + 143, + 14, + 236, + 3, // Opcode: FCMPDri + /* 94458 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 94473 + /* 94463 */ MCD_OPC_CheckPredicate, + 49, + 75, + 39, + 0, // Skip to: 104527 + /* 94468 */ MCD_OPC_Decode, + 146, + 14, + 235, + 3, // Opcode: FCMPEDrr + /* 94473 */ MCD_OPC_FilterValue, + 24, + 65, + 39, + 0, // Skip to: 104527 + /* 94478 */ MCD_OPC_CheckPredicate, + 49, + 60, + 39, + 0, // Skip to: 104527 + /* 94483 */ MCD_OPC_Decode, + 145, + 14, + 236, + 3, // Opcode: FCMPEDri + /* 94488 */ MCD_OPC_FilterValue, + 2, + 153, + 0, + 0, // Skip to: 94646 + /* 94493 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 94496 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 94511 + /* 94501 */ MCD_OPC_CheckPredicate, + 49, + 37, + 39, + 0, // Skip to: 104527 + /* 94506 */ MCD_OPC_Decode, + 216, + 17, + 156, + 2, // Opcode: FMOVDr + /* 94511 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 94526 + /* 94516 */ MCD_OPC_CheckPredicate, + 49, + 22, + 39, + 0, // Skip to: 104527 + /* 94521 */ MCD_OPC_Decode, + 159, + 18, + 156, + 2, // Opcode: FNEGDr + /* 94526 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 94541 + /* 94531 */ MCD_OPC_CheckPredicate, + 49, + 7, + 39, + 0, // Skip to: 104527 + /* 94536 */ MCD_OPC_Decode, + 164, + 15, + 213, + 2, // Opcode: FCVTSDr + /* 94541 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 94556 + /* 94546 */ MCD_OPC_CheckPredicate, + 51, + 248, + 38, + 0, // Skip to: 104527 + /* 94551 */ MCD_OPC_Decode, + 194, + 8, + 227, + 3, // Opcode: BFCVT + /* 94556 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 94571 + /* 94561 */ MCD_OPC_CheckPredicate, + 49, + 233, + 38, + 0, // Skip to: 104527 + /* 94566 */ MCD_OPC_Decode, + 144, + 19, + 156, + 2, // Opcode: FRINTNDr + /* 94571 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 94586 + /* 94576 */ MCD_OPC_CheckPredicate, + 49, + 218, + 38, + 0, // Skip to: 104527 + /* 94581 */ MCD_OPC_Decode, + 133, + 19, + 156, + 2, // Opcode: FRINTMDr + /* 94586 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 94601 + /* 94591 */ MCD_OPC_CheckPredicate, + 49, + 203, + 38, + 0, // Skip to: 104527 + /* 94596 */ MCD_OPC_Decode, + 239, + 18, + 156, + 2, // Opcode: FRINTADr + /* 94601 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 94616 + /* 94606 */ MCD_OPC_CheckPredicate, + 49, + 188, + 38, + 0, // Skip to: 104527 + /* 94611 */ MCD_OPC_Decode, + 166, + 19, + 156, + 2, // Opcode: FRINTXDr + /* 94616 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 94631 + /* 94621 */ MCD_OPC_CheckPredicate, + 24, + 173, + 38, + 0, // Skip to: 104527 + /* 94626 */ MCD_OPC_Decode, + 224, + 18, + 156, + 2, // Opcode: FRINT32ZDr + /* 94631 */ MCD_OPC_FilterValue, + 9, + 163, + 38, + 0, // Skip to: 104527 + /* 94636 */ MCD_OPC_CheckPredicate, + 24, + 158, + 38, + 0, // Skip to: 104527 + /* 94641 */ MCD_OPC_Decode, + 234, + 18, + 156, + 2, // Opcode: FRINT64ZDr + /* 94646 */ MCD_OPC_FilterValue, + 6, + 148, + 38, + 0, // Skip to: 104527 + /* 94651 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 94654 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 94669 + /* 94659 */ MCD_OPC_CheckPredicate, + 49, + 135, + 38, + 0, // Skip to: 104527 + /* 94664 */ MCD_OPC_Decode, + 211, + 12, + 156, + 2, // Opcode: FABSDr + /* 94669 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 94684 + /* 94674 */ MCD_OPC_CheckPredicate, + 49, + 120, + 38, + 0, // Skip to: 104527 + /* 94679 */ MCD_OPC_Decode, + 213, + 19, + 156, + 2, // Opcode: FSQRTDr + /* 94684 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 94699 + /* 94689 */ MCD_OPC_CheckPredicate, + 49, + 105, + 38, + 0, // Skip to: 104527 + /* 94694 */ MCD_OPC_Decode, + 194, + 14, + 167, + 2, // Opcode: FCVTHDr + /* 94699 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 94714 + /* 94704 */ MCD_OPC_CheckPredicate, + 49, + 90, + 38, + 0, // Skip to: 104527 + /* 94709 */ MCD_OPC_Decode, + 155, + 19, + 156, + 2, // Opcode: FRINTPDr + /* 94714 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 94729 + /* 94719 */ MCD_OPC_CheckPredicate, + 49, + 75, + 38, + 0, // Skip to: 104527 + /* 94724 */ MCD_OPC_Decode, + 177, + 19, + 156, + 2, // Opcode: FRINTZDr + /* 94729 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 94744 + /* 94734 */ MCD_OPC_CheckPredicate, + 49, + 60, + 38, + 0, // Skip to: 104527 + /* 94739 */ MCD_OPC_Decode, + 250, + 18, + 156, + 2, // Opcode: FRINTIDr + /* 94744 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 94759 + /* 94749 */ MCD_OPC_CheckPredicate, + 24, + 45, + 38, + 0, // Skip to: 104527 + /* 94754 */ MCD_OPC_Decode, + 219, + 18, + 156, + 2, // Opcode: FRINT32XDr + /* 94759 */ MCD_OPC_FilterValue, + 9, + 35, + 38, + 0, // Skip to: 104527 + /* 94764 */ MCD_OPC_CheckPredicate, + 24, + 30, + 38, + 0, // Skip to: 104527 + /* 94769 */ MCD_OPC_Decode, + 229, + 18, + 156, + 2, // Opcode: FRINT64XDr + /* 94774 */ MCD_OPC_FilterValue, + 1, + 20, + 38, + 0, // Skip to: 104527 + /* 94779 */ MCD_OPC_CheckPredicate, + 49, + 15, + 38, + 0, // Skip to: 104527 + /* 94784 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 8, + 38, + 0, // Skip to: 104527 + /* 94791 */ MCD_OPC_Decode, + 215, + 17, + 237, + 3, // Opcode: FMOVDi + /* 94796 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 94834 + /* 94801 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 94804 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 94819 + /* 94809 */ MCD_OPC_CheckPredicate, + 49, + 241, + 37, + 0, // Skip to: 104527 + /* 94814 */ MCD_OPC_Decode, + 158, + 13, + 238, + 3, // Opcode: FCCMPDrr + /* 94819 */ MCD_OPC_FilterValue, + 1, + 231, + 37, + 0, // Skip to: 104527 + /* 94824 */ MCD_OPC_CheckPredicate, + 49, + 226, + 37, + 0, // Skip to: 104527 + /* 94829 */ MCD_OPC_Decode, + 159, + 13, + 238, + 3, // Opcode: FCCMPEDrr + /* 94834 */ MCD_OPC_FilterValue, + 2, + 138, + 0, + 0, // Skip to: 94977 + /* 94839 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 94842 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 94857 + /* 94847 */ MCD_OPC_CheckPredicate, + 49, + 203, + 37, + 0, // Skip to: 104527 + /* 94852 */ MCD_OPC_Decode, + 240, + 17, + 155, + 2, // Opcode: FMULDrr + /* 94857 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 94872 + /* 94862 */ MCD_OPC_CheckPredicate, + 49, + 188, + 37, + 0, // Skip to: 104527 + /* 94867 */ MCD_OPC_Decode, + 247, + 15, + 155, + 2, // Opcode: FDIVDrr + /* 94872 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 94887 + /* 94877 */ MCD_OPC_CheckPredicate, + 49, + 173, + 37, + 0, // Skip to: 104527 + /* 94882 */ MCD_OPC_Decode, + 247, + 12, + 155, + 2, // Opcode: FADDDrr + /* 94887 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 94902 + /* 94892 */ MCD_OPC_CheckPredicate, + 49, + 158, + 37, + 0, // Skip to: 104527 + /* 94897 */ MCD_OPC_Decode, + 224, + 19, + 155, + 2, // Opcode: FSUBDrr + /* 94902 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 94917 + /* 94907 */ MCD_OPC_CheckPredicate, + 49, + 143, + 37, + 0, // Skip to: 104527 + /* 94912 */ MCD_OPC_Decode, + 149, + 16, + 155, + 2, // Opcode: FMAXDrr + /* 94917 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 94932 + /* 94922 */ MCD_OPC_CheckPredicate, + 49, + 128, + 37, + 0, // Skip to: 104527 + /* 94927 */ MCD_OPC_Decode, + 211, + 16, + 155, + 2, // Opcode: FMINDrr + /* 94932 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 94947 + /* 94937 */ MCD_OPC_CheckPredicate, + 49, + 113, + 37, + 0, // Skip to: 104527 + /* 94942 */ MCD_OPC_Decode, + 151, + 16, + 155, + 2, // Opcode: FMAXNMDrr + /* 94947 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 94962 + /* 94952 */ MCD_OPC_CheckPredicate, + 49, + 98, + 37, + 0, // Skip to: 104527 + /* 94957 */ MCD_OPC_Decode, + 213, + 16, + 155, + 2, // Opcode: FMINNMDrr + /* 94962 */ MCD_OPC_FilterValue, + 8, + 88, + 37, + 0, // Skip to: 104527 + /* 94967 */ MCD_OPC_CheckPredicate, + 49, + 83, + 37, + 0, // Skip to: 104527 + /* 94972 */ MCD_OPC_Decode, + 188, + 18, + 155, + 2, // Opcode: FNMULDrr + /* 94977 */ MCD_OPC_FilterValue, + 3, + 73, + 37, + 0, // Skip to: 104527 + /* 94982 */ MCD_OPC_CheckPredicate, + 49, + 68, + 37, + 0, // Skip to: 104527 + /* 94987 */ MCD_OPC_Decode, + 161, + 14, + 239, + 3, // Opcode: FCSELDrrr + /* 94992 */ MCD_OPC_FilterValue, + 6, + 63, + 0, + 0, // Skip to: 95060 + /* 94997 */ MCD_OPC_ExtractField, + 15, + 6, // Inst{20-15} ... + /* 95000 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 95015 + /* 95005 */ MCD_OPC_CheckPredicate, + 52, + 45, + 37, + 0, // Skip to: 104527 + /* 95010 */ MCD_OPC_Decode, + 200, + 30, + 240, + 3, // Opcode: SCVTFSWHri + /* 95015 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 95030 + /* 95020 */ MCD_OPC_CheckPredicate, + 52, + 30, + 37, + 0, // Skip to: 104527 + /* 95025 */ MCD_OPC_Decode, + 189, + 42, + 240, + 3, // Opcode: UCVTFSWHri + /* 95030 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 95045 + /* 95035 */ MCD_OPC_CheckPredicate, + 52, + 15, + 37, + 0, // Skip to: 104527 + /* 95040 */ MCD_OPC_Decode, + 172, + 15, + 241, + 3, // Opcode: FCVTZSSWHri + /* 95045 */ MCD_OPC_FilterValue, + 51, + 5, + 37, + 0, // Skip to: 104527 + /* 95050 */ MCD_OPC_CheckPredicate, + 52, + 0, + 37, + 0, // Skip to: 104527 + /* 95055 */ MCD_OPC_Decode, + 207, + 15, + 241, + 3, // Opcode: FCVTZUSWHri + /* 95060 */ MCD_OPC_FilterValue, + 7, + 246, + 36, + 0, // Skip to: 104527 + /* 95065 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 95068 */ MCD_OPC_FilterValue, + 0, + 18, + 2, + 0, // Skip to: 95603 + /* 95073 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 95076 */ MCD_OPC_FilterValue, + 0, + 244, + 1, + 0, // Skip to: 95581 + /* 95081 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 95084 */ MCD_OPC_FilterValue, + 0, + 213, + 0, + 0, // Skip to: 95302 + /* 95089 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 95092 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95107 + /* 95097 */ MCD_OPC_CheckPredicate, + 52, + 209, + 36, + 0, // Skip to: 104527 + /* 95102 */ MCD_OPC_Decode, + 231, + 14, + 242, + 3, // Opcode: FCVTNSUWHr + /* 95107 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 95122 + /* 95112 */ MCD_OPC_CheckPredicate, + 52, + 194, + 36, + 0, // Skip to: 104527 + /* 95117 */ MCD_OPC_Decode, + 247, + 14, + 242, + 3, // Opcode: FCVTNUUWHr + /* 95122 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 95137 + /* 95127 */ MCD_OPC_CheckPredicate, + 52, + 179, + 36, + 0, // Skip to: 104527 + /* 95132 */ MCD_OPC_Decode, + 206, + 30, + 243, + 3, // Opcode: SCVTFUWHri + /* 95137 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 95152 + /* 95142 */ MCD_OPC_CheckPredicate, + 52, + 164, + 36, + 0, // Skip to: 104527 + /* 95147 */ MCD_OPC_Decode, + 195, + 42, + 243, + 3, // Opcode: UCVTFUWHri + /* 95152 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 95167 + /* 95157 */ MCD_OPC_CheckPredicate, + 52, + 149, + 36, + 0, // Skip to: 104527 + /* 95162 */ MCD_OPC_Decode, + 165, + 14, + 242, + 3, // Opcode: FCVTASUWHr + /* 95167 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 95182 + /* 95172 */ MCD_OPC_CheckPredicate, + 52, + 134, + 36, + 0, // Skip to: 104527 + /* 95177 */ MCD_OPC_Decode, + 179, + 14, + 242, + 3, // Opcode: FCVTAUUWHr + /* 95182 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 95197 + /* 95187 */ MCD_OPC_CheckPredicate, + 52, + 119, + 36, + 0, // Skip to: 104527 + /* 95192 */ MCD_OPC_Decode, + 217, + 17, + 242, + 3, // Opcode: FMOVHWr + /* 95197 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 95212 + /* 95202 */ MCD_OPC_CheckPredicate, + 52, + 104, + 36, + 0, // Skip to: 104527 + /* 95207 */ MCD_OPC_Decode, + 224, + 17, + 243, + 3, // Opcode: FMOVWHr + /* 95212 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 95227 + /* 95217 */ MCD_OPC_CheckPredicate, + 52, + 89, + 36, + 0, // Skip to: 104527 + /* 95222 */ MCD_OPC_Decode, + 137, + 15, + 242, + 3, // Opcode: FCVTPSUWHr + /* 95227 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 95242 + /* 95232 */ MCD_OPC_CheckPredicate, + 52, + 74, + 36, + 0, // Skip to: 104527 + /* 95237 */ MCD_OPC_Decode, + 151, + 15, + 242, + 3, // Opcode: FCVTPUUWHr + /* 95242 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 95257 + /* 95247 */ MCD_OPC_CheckPredicate, + 52, + 59, + 36, + 0, // Skip to: 104527 + /* 95252 */ MCD_OPC_Decode, + 203, + 14, + 242, + 3, // Opcode: FCVTMSUWHr + /* 95257 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 95272 + /* 95262 */ MCD_OPC_CheckPredicate, + 52, + 44, + 36, + 0, // Skip to: 104527 + /* 95267 */ MCD_OPC_Decode, + 217, + 14, + 242, + 3, // Opcode: FCVTMUUWHr + /* 95272 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 95287 + /* 95277 */ MCD_OPC_CheckPredicate, + 52, + 29, + 36, + 0, // Skip to: 104527 + /* 95282 */ MCD_OPC_Decode, + 178, + 15, + 242, + 3, // Opcode: FCVTZSUWHr + /* 95287 */ MCD_OPC_FilterValue, + 25, + 19, + 36, + 0, // Skip to: 104527 + /* 95292 */ MCD_OPC_CheckPredicate, + 52, + 14, + 36, + 0, // Skip to: 104527 + /* 95297 */ MCD_OPC_Decode, + 213, + 15, + 242, + 3, // Opcode: FCVTZUUWHr + /* 95302 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 95370 + /* 95307 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 95310 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95325 + /* 95315 */ MCD_OPC_CheckPredicate, + 52, + 247, + 35, + 0, // Skip to: 104527 + /* 95320 */ MCD_OPC_Decode, + 152, + 14, + 244, + 3, // Opcode: FCMPHrr + /* 95325 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 95340 + /* 95330 */ MCD_OPC_CheckPredicate, + 52, + 232, + 35, + 0, // Skip to: 104527 + /* 95335 */ MCD_OPC_Decode, + 151, + 14, + 245, + 3, // Opcode: FCMPHri + /* 95340 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 95355 + /* 95345 */ MCD_OPC_CheckPredicate, + 52, + 217, + 35, + 0, // Skip to: 104527 + /* 95350 */ MCD_OPC_Decode, + 148, + 14, + 244, + 3, // Opcode: FCMPEHrr + /* 95355 */ MCD_OPC_FilterValue, + 24, + 207, + 35, + 0, // Skip to: 104527 + /* 95360 */ MCD_OPC_CheckPredicate, + 52, + 202, + 35, + 0, // Skip to: 104527 + /* 95365 */ MCD_OPC_Decode, + 147, + 14, + 245, + 3, // Opcode: FCMPEHri + /* 95370 */ MCD_OPC_FilterValue, + 2, + 108, + 0, + 0, // Skip to: 95483 + /* 95375 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 95378 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95393 + /* 95383 */ MCD_OPC_CheckPredicate, + 52, + 179, + 35, + 0, // Skip to: 104527 + /* 95388 */ MCD_OPC_Decode, + 220, + 17, + 246, + 3, // Opcode: FMOVHr + /* 95393 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 95408 + /* 95398 */ MCD_OPC_CheckPredicate, + 52, + 164, + 35, + 0, // Skip to: 104527 + /* 95403 */ MCD_OPC_Decode, + 160, + 18, + 246, + 3, // Opcode: FNEGHr + /* 95408 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 95423 + /* 95413 */ MCD_OPC_CheckPredicate, + 49, + 149, + 35, + 0, // Skip to: 104527 + /* 95418 */ MCD_OPC_Decode, + 165, + 15, + 247, + 3, // Opcode: FCVTSHr + /* 95423 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 95438 + /* 95428 */ MCD_OPC_CheckPredicate, + 52, + 134, + 35, + 0, // Skip to: 104527 + /* 95433 */ MCD_OPC_Decode, + 145, + 19, + 246, + 3, // Opcode: FRINTNHr + /* 95438 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 95453 + /* 95443 */ MCD_OPC_CheckPredicate, + 52, + 119, + 35, + 0, // Skip to: 104527 + /* 95448 */ MCD_OPC_Decode, + 134, + 19, + 246, + 3, // Opcode: FRINTMHr + /* 95453 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 95468 + /* 95458 */ MCD_OPC_CheckPredicate, + 52, + 104, + 35, + 0, // Skip to: 104527 + /* 95463 */ MCD_OPC_Decode, + 240, + 18, + 246, + 3, // Opcode: FRINTAHr + /* 95468 */ MCD_OPC_FilterValue, + 7, + 94, + 35, + 0, // Skip to: 104527 + /* 95473 */ MCD_OPC_CheckPredicate, + 52, + 89, + 35, + 0, // Skip to: 104527 + /* 95478 */ MCD_OPC_Decode, + 167, + 19, + 246, + 3, // Opcode: FRINTXHr + /* 95483 */ MCD_OPC_FilterValue, + 6, + 79, + 35, + 0, // Skip to: 104527 + /* 95488 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 95491 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95506 + /* 95496 */ MCD_OPC_CheckPredicate, + 52, + 66, + 35, + 0, // Skip to: 104527 + /* 95501 */ MCD_OPC_Decode, + 212, + 12, + 246, + 3, // Opcode: FABSHr + /* 95506 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 95521 + /* 95511 */ MCD_OPC_CheckPredicate, + 52, + 51, + 35, + 0, // Skip to: 104527 + /* 95516 */ MCD_OPC_Decode, + 214, + 19, + 246, + 3, // Opcode: FSQRTHr + /* 95521 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 95536 + /* 95526 */ MCD_OPC_CheckPredicate, + 49, + 36, + 35, + 0, // Skip to: 104527 + /* 95531 */ MCD_OPC_Decode, + 192, + 14, + 248, + 3, // Opcode: FCVTDHr + /* 95536 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 95551 + /* 95541 */ MCD_OPC_CheckPredicate, + 52, + 21, + 35, + 0, // Skip to: 104527 + /* 95546 */ MCD_OPC_Decode, + 156, + 19, + 246, + 3, // Opcode: FRINTPHr + /* 95551 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 95566 + /* 95556 */ MCD_OPC_CheckPredicate, + 52, + 6, + 35, + 0, // Skip to: 104527 + /* 95561 */ MCD_OPC_Decode, + 178, + 19, + 246, + 3, // Opcode: FRINTZHr + /* 95566 */ MCD_OPC_FilterValue, + 7, + 252, + 34, + 0, // Skip to: 104527 + /* 95571 */ MCD_OPC_CheckPredicate, + 52, + 247, + 34, + 0, // Skip to: 104527 + /* 95576 */ MCD_OPC_Decode, + 251, + 18, + 246, + 3, // Opcode: FRINTIHr + /* 95581 */ MCD_OPC_FilterValue, + 1, + 237, + 34, + 0, // Skip to: 104527 + /* 95586 */ MCD_OPC_CheckPredicate, + 52, + 232, + 34, + 0, // Skip to: 104527 + /* 95591 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 225, + 34, + 0, // Skip to: 104527 + /* 95598 */ MCD_OPC_Decode, + 219, + 17, + 249, + 3, // Opcode: FMOVHi + /* 95603 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 95641 + /* 95608 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 95611 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95626 + /* 95616 */ MCD_OPC_CheckPredicate, + 52, + 202, + 34, + 0, // Skip to: 104527 + /* 95621 */ MCD_OPC_Decode, + 162, + 13, + 250, + 3, // Opcode: FCCMPHrr + /* 95626 */ MCD_OPC_FilterValue, + 1, + 192, + 34, + 0, // Skip to: 104527 + /* 95631 */ MCD_OPC_CheckPredicate, + 52, + 187, + 34, + 0, // Skip to: 104527 + /* 95636 */ MCD_OPC_Decode, + 160, + 13, + 250, + 3, // Opcode: FCCMPEHrr + /* 95641 */ MCD_OPC_FilterValue, + 2, + 138, + 0, + 0, // Skip to: 95784 + /* 95646 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 95649 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95664 + /* 95654 */ MCD_OPC_CheckPredicate, + 52, + 164, + 34, + 0, // Skip to: 104527 + /* 95659 */ MCD_OPC_Decode, + 241, + 17, + 251, + 3, // Opcode: FMULHrr + /* 95664 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 95679 + /* 95669 */ MCD_OPC_CheckPredicate, + 52, + 149, + 34, + 0, // Skip to: 104527 + /* 95674 */ MCD_OPC_Decode, + 248, + 15, + 251, + 3, // Opcode: FDIVHrr + /* 95679 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 95694 + /* 95684 */ MCD_OPC_CheckPredicate, + 52, + 134, + 34, + 0, // Skip to: 104527 + /* 95689 */ MCD_OPC_Decode, + 248, + 12, + 251, + 3, // Opcode: FADDHrr + /* 95694 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 95709 + /* 95699 */ MCD_OPC_CheckPredicate, + 52, + 119, + 34, + 0, // Skip to: 104527 + /* 95704 */ MCD_OPC_Decode, + 225, + 19, + 251, + 3, // Opcode: FSUBHrr + /* 95709 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 95724 + /* 95714 */ MCD_OPC_CheckPredicate, + 52, + 104, + 34, + 0, // Skip to: 104527 + /* 95719 */ MCD_OPC_Decode, + 150, + 16, + 251, + 3, // Opcode: FMAXHrr + /* 95724 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 95739 + /* 95729 */ MCD_OPC_CheckPredicate, + 52, + 89, + 34, + 0, // Skip to: 104527 + /* 95734 */ MCD_OPC_Decode, + 212, + 16, + 251, + 3, // Opcode: FMINHrr + /* 95739 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 95754 + /* 95744 */ MCD_OPC_CheckPredicate, + 52, + 74, + 34, + 0, // Skip to: 104527 + /* 95749 */ MCD_OPC_Decode, + 152, + 16, + 251, + 3, // Opcode: FMAXNMHrr + /* 95754 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 95769 + /* 95759 */ MCD_OPC_CheckPredicate, + 52, + 59, + 34, + 0, // Skip to: 104527 + /* 95764 */ MCD_OPC_Decode, + 214, + 16, + 251, + 3, // Opcode: FMINNMHrr + /* 95769 */ MCD_OPC_FilterValue, + 8, + 49, + 34, + 0, // Skip to: 104527 + /* 95774 */ MCD_OPC_CheckPredicate, + 52, + 44, + 34, + 0, // Skip to: 104527 + /* 95779 */ MCD_OPC_Decode, + 189, + 18, + 251, + 3, // Opcode: FNMULHrr + /* 95784 */ MCD_OPC_FilterValue, + 3, + 34, + 34, + 0, // Skip to: 104527 + /* 95789 */ MCD_OPC_CheckPredicate, + 52, + 29, + 34, + 0, // Skip to: 104527 + /* 95794 */ MCD_OPC_Decode, + 162, + 14, + 252, + 3, // Opcode: FCSELHrrr + /* 95799 */ MCD_OPC_FilterValue, + 3, + 19, + 34, + 0, // Skip to: 104527 + /* 95804 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 95807 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 95845 + /* 95812 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 95815 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95830 + /* 95820 */ MCD_OPC_CheckPredicate, + 49, + 254, + 33, + 0, // Skip to: 104527 + /* 95825 */ MCD_OPC_Decode, + 145, + 16, + 253, + 3, // Opcode: FMADDSrrr + /* 95830 */ MCD_OPC_FilterValue, + 1, + 244, + 33, + 0, // Skip to: 104527 + /* 95835 */ MCD_OPC_CheckPredicate, + 49, + 239, + 33, + 0, // Skip to: 104527 + /* 95840 */ MCD_OPC_Decode, + 239, + 17, + 253, + 3, // Opcode: FMSUBSrrr + /* 95845 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 95883 + /* 95850 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 95853 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95868 + /* 95858 */ MCD_OPC_CheckPredicate, + 49, + 216, + 33, + 0, // Skip to: 104527 + /* 95863 */ MCD_OPC_Decode, + 172, + 18, + 253, + 3, // Opcode: FNMADDSrrr + /* 95868 */ MCD_OPC_FilterValue, + 1, + 206, + 33, + 0, // Skip to: 104527 + /* 95873 */ MCD_OPC_CheckPredicate, + 49, + 201, + 33, + 0, // Skip to: 104527 + /* 95878 */ MCD_OPC_Decode, + 187, + 18, + 253, + 3, // Opcode: FNMSUBSrrr + /* 95883 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 95921 + /* 95888 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 95891 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95906 + /* 95896 */ MCD_OPC_CheckPredicate, + 49, + 178, + 33, + 0, // Skip to: 104527 + /* 95901 */ MCD_OPC_Decode, + 143, + 16, + 254, + 3, // Opcode: FMADDDrrr + /* 95906 */ MCD_OPC_FilterValue, + 1, + 168, + 33, + 0, // Skip to: 104527 + /* 95911 */ MCD_OPC_CheckPredicate, + 49, + 163, + 33, + 0, // Skip to: 104527 + /* 95916 */ MCD_OPC_Decode, + 237, + 17, + 254, + 3, // Opcode: FMSUBDrrr + /* 95921 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 95959 + /* 95926 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 95929 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95944 + /* 95934 */ MCD_OPC_CheckPredicate, + 49, + 140, + 33, + 0, // Skip to: 104527 + /* 95939 */ MCD_OPC_Decode, + 170, + 18, + 254, + 3, // Opcode: FNMADDDrrr + /* 95944 */ MCD_OPC_FilterValue, + 1, + 130, + 33, + 0, // Skip to: 104527 + /* 95949 */ MCD_OPC_CheckPredicate, + 49, + 125, + 33, + 0, // Skip to: 104527 + /* 95954 */ MCD_OPC_Decode, + 185, + 18, + 254, + 3, // Opcode: FNMSUBDrrr + /* 95959 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 95997 + /* 95964 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 95967 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 95982 + /* 95972 */ MCD_OPC_CheckPredicate, + 52, + 102, + 33, + 0, // Skip to: 104527 + /* 95977 */ MCD_OPC_Decode, + 144, + 16, + 255, + 3, // Opcode: FMADDHrrr + /* 95982 */ MCD_OPC_FilterValue, + 1, + 92, + 33, + 0, // Skip to: 104527 + /* 95987 */ MCD_OPC_CheckPredicate, + 52, + 87, + 33, + 0, // Skip to: 104527 + /* 95992 */ MCD_OPC_Decode, + 238, + 17, + 255, + 3, // Opcode: FMSUBHrrr + /* 95997 */ MCD_OPC_FilterValue, + 7, + 77, + 33, + 0, // Skip to: 104527 + /* 96002 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 96005 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 96020 + /* 96010 */ MCD_OPC_CheckPredicate, + 52, + 64, + 33, + 0, // Skip to: 104527 + /* 96015 */ MCD_OPC_Decode, + 171, + 18, + 255, + 3, // Opcode: FNMADDHrrr + /* 96020 */ MCD_OPC_FilterValue, + 1, + 54, + 33, + 0, // Skip to: 104527 + /* 96025 */ MCD_OPC_CheckPredicate, + 52, + 49, + 33, + 0, // Skip to: 104527 + /* 96030 */ MCD_OPC_Decode, + 186, + 18, + 255, + 3, // Opcode: FNMSUBHrrr + /* 96035 */ MCD_OPC_FilterValue, + 1, + 191, + 1, + 0, // Skip to: 96487 + /* 96040 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 96043 */ MCD_OPC_FilterValue, + 0, + 96, + 0, + 0, // Skip to: 96144 + /* 96048 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 96051 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 96068 + /* 96056 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 16, + 33, + 0, // Skip to: 104527 + /* 96063 */ MCD_OPC_Decode, + 146, + 40, + 177, + 3, // Opcode: STURBi + /* 96068 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 96085 + /* 96073 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 255, + 32, + 0, // Skip to: 104527 + /* 96080 */ MCD_OPC_Decode, + 226, + 39, + 177, + 3, // Opcode: STRBpost + /* 96085 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 96127 + /* 96090 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 96093 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 96110 + /* 96098 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 230, + 32, + 0, // Skip to: 104527 + /* 96105 */ MCD_OPC_Decode, + 228, + 39, + 128, + 4, // Opcode: STRBroW + /* 96110 */ MCD_OPC_FilterValue, + 3, + 220, + 32, + 0, // Skip to: 104527 + /* 96115 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 213, + 32, + 0, // Skip to: 104527 + /* 96122 */ MCD_OPC_Decode, + 229, + 39, + 129, + 4, // Opcode: STRBroX + /* 96127 */ MCD_OPC_FilterValue, + 3, + 203, + 32, + 0, // Skip to: 104527 + /* 96132 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 196, + 32, + 0, // Skip to: 104527 + /* 96139 */ MCD_OPC_Decode, + 227, + 39, + 177, + 3, // Opcode: STRBpre + /* 96144 */ MCD_OPC_FilterValue, + 1, + 96, + 0, + 0, // Skip to: 96245 + /* 96149 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 96152 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 96169 + /* 96157 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 171, + 32, + 0, // Skip to: 104527 + /* 96164 */ MCD_OPC_Decode, + 195, + 26, + 177, + 3, // Opcode: LDURBi + /* 96169 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 96186 + /* 96174 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 154, + 32, + 0, // Skip to: 104527 + /* 96181 */ MCD_OPC_Decode, + 159, + 25, + 177, + 3, // Opcode: LDRBpost + /* 96186 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 96228 + /* 96191 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 96194 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 96211 + /* 96199 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 129, + 32, + 0, // Skip to: 104527 + /* 96206 */ MCD_OPC_Decode, + 161, + 25, + 128, + 4, // Opcode: LDRBroW + /* 96211 */ MCD_OPC_FilterValue, + 3, + 119, + 32, + 0, // Skip to: 104527 + /* 96216 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 112, + 32, + 0, // Skip to: 104527 + /* 96223 */ MCD_OPC_Decode, + 162, + 25, + 129, + 4, // Opcode: LDRBroX + /* 96228 */ MCD_OPC_FilterValue, + 3, + 102, + 32, + 0, // Skip to: 104527 + /* 96233 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 95, + 32, + 0, // Skip to: 104527 + /* 96240 */ MCD_OPC_Decode, + 160, + 25, + 177, + 3, // Opcode: LDRBpre + /* 96245 */ MCD_OPC_FilterValue, + 2, + 96, + 0, + 0, // Skip to: 96346 + /* 96250 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 96253 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 96270 + /* 96258 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 70, + 32, + 0, // Skip to: 104527 + /* 96265 */ MCD_OPC_Decode, + 150, + 40, + 177, + 3, // Opcode: STURQi + /* 96270 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 96287 + /* 96275 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 53, + 32, + 0, // Skip to: 104527 + /* 96282 */ MCD_OPC_Decode, + 246, + 39, + 177, + 3, // Opcode: STRQpost + /* 96287 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 96329 + /* 96292 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 96295 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 96312 + /* 96300 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 28, + 32, + 0, // Skip to: 104527 + /* 96307 */ MCD_OPC_Decode, + 248, + 39, + 130, + 4, // Opcode: STRQroW + /* 96312 */ MCD_OPC_FilterValue, + 3, + 18, + 32, + 0, // Skip to: 104527 + /* 96317 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 11, + 32, + 0, // Skip to: 104527 + /* 96324 */ MCD_OPC_Decode, + 249, + 39, + 131, + 4, // Opcode: STRQroX + /* 96329 */ MCD_OPC_FilterValue, + 3, + 1, + 32, + 0, // Skip to: 104527 + /* 96334 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 250, + 31, + 0, // Skip to: 104527 + /* 96341 */ MCD_OPC_Decode, + 247, + 39, + 177, + 3, // Opcode: STRQpre + /* 96346 */ MCD_OPC_FilterValue, + 3, + 96, + 0, + 0, // Skip to: 96447 + /* 96351 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 96354 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 96371 + /* 96359 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 225, + 31, + 0, // Skip to: 104527 + /* 96366 */ MCD_OPC_Decode, + 199, + 26, + 177, + 3, // Opcode: LDURQi + /* 96371 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 96388 + /* 96376 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 208, + 31, + 0, // Skip to: 104527 + /* 96383 */ MCD_OPC_Decode, + 181, + 25, + 177, + 3, // Opcode: LDRQpost + /* 96388 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 96430 + /* 96393 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 96396 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 96413 + /* 96401 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 183, + 31, + 0, // Skip to: 104527 + /* 96408 */ MCD_OPC_Decode, + 183, + 25, + 130, + 4, // Opcode: LDRQroW + /* 96413 */ MCD_OPC_FilterValue, + 3, + 173, + 31, + 0, // Skip to: 104527 + /* 96418 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 166, + 31, + 0, // Skip to: 104527 + /* 96425 */ MCD_OPC_Decode, + 184, + 25, + 131, + 4, // Opcode: LDRQroX + /* 96430 */ MCD_OPC_FilterValue, + 3, + 156, + 31, + 0, // Skip to: 104527 + /* 96435 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 149, + 31, + 0, // Skip to: 104527 + /* 96442 */ MCD_OPC_Decode, + 182, + 25, + 177, + 3, // Opcode: LDRQpre + /* 96447 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 96457 + /* 96452 */ MCD_OPC_Decode, + 230, + 39, + 187, + 3, // Opcode: STRBui + /* 96457 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 96467 + /* 96462 */ MCD_OPC_Decode, + 163, + 25, + 187, + 3, // Opcode: LDRBui + /* 96467 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 96477 + /* 96472 */ MCD_OPC_Decode, + 250, + 39, + 187, + 3, // Opcode: STRQui + /* 96477 */ MCD_OPC_FilterValue, + 7, + 109, + 31, + 0, // Skip to: 104527 + /* 96482 */ MCD_OPC_Decode, + 185, + 25, + 187, + 3, // Opcode: LDRQui + /* 96487 */ MCD_OPC_FilterValue, + 2, + 63, + 12, + 0, // Skip to: 99627 + /* 96492 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 96495 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 96505 + /* 96500 */ MCD_OPC_Decode, + 164, + 25, + 132, + 4, // Opcode: LDRDl + /* 96505 */ MCD_OPC_FilterValue, + 2, + 254, + 7, + 0, // Skip to: 98556 + /* 96510 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 96513 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 96535 + /* 96518 */ MCD_OPC_CheckPredicate, + 53, + 68, + 31, + 0, // Skip to: 104527 + /* 96523 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 61, + 31, + 0, // Skip to: 104527 + /* 96530 */ MCD_OPC_Decode, + 128, + 31, + 133, + 4, // Opcode: SHA1Crrr + /* 96535 */ MCD_OPC_FilterValue, + 1, + 114, + 0, + 0, // Skip to: 96654 + /* 96540 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 96543 */ MCD_OPC_FilterValue, + 0, + 84, + 0, + 0, // Skip to: 96632 + /* 96548 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 96551 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 96610 + /* 96556 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 96559 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 96588 + /* 96564 */ MCD_OPC_CheckPredicate, + 21, + 22, + 31, + 0, // Skip to: 104527 + /* 96569 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 15, + 31, + 0, // Skip to: 104527 + /* 96576 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 8, + 31, + 0, // Skip to: 104527 + /* 96583 */ MCD_OPC_Decode, + 208, + 11, + 134, + 4, // Opcode: CPYi64 + /* 96588 */ MCD_OPC_FilterValue, + 1, + 254, + 30, + 0, // Skip to: 104527 + /* 96593 */ MCD_OPC_CheckPredicate, + 21, + 249, + 30, + 0, // Skip to: 104527 + /* 96598 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 242, + 30, + 0, // Skip to: 104527 + /* 96605 */ MCD_OPC_Decode, + 207, + 11, + 135, + 4, // Opcode: CPYi32 + /* 96610 */ MCD_OPC_FilterValue, + 1, + 232, + 30, + 0, // Skip to: 104527 + /* 96615 */ MCD_OPC_CheckPredicate, + 21, + 227, + 30, + 0, // Skip to: 104527 + /* 96620 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 220, + 30, + 0, // Skip to: 104527 + /* 96627 */ MCD_OPC_Decode, + 206, + 11, + 136, + 4, // Opcode: CPYi16 + /* 96632 */ MCD_OPC_FilterValue, + 1, + 210, + 30, + 0, // Skip to: 104527 + /* 96637 */ MCD_OPC_CheckPredicate, + 21, + 205, + 30, + 0, // Skip to: 104527 + /* 96642 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 198, + 30, + 0, // Skip to: 104527 + /* 96649 */ MCD_OPC_Decode, + 209, + 11, + 137, + 4, // Opcode: CPYi8 + /* 96654 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 96676 + /* 96659 */ MCD_OPC_CheckPredicate, + 53, + 183, + 30, + 0, // Skip to: 104527 + /* 96664 */ MCD_OPC_CheckField, + 16, + 8, + 40, + 176, + 30, + 0, // Skip to: 104527 + /* 96671 */ MCD_OPC_Decode, + 129, + 31, + 225, + 3, // Opcode: SHA1Hrr + /* 96676 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 96744 + /* 96681 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 96684 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 96699 + /* 96689 */ MCD_OPC_CheckPredicate, + 21, + 153, + 30, + 0, // Skip to: 104527 + /* 96694 */ MCD_OPC_Decode, + 152, + 33, + 138, + 4, // Opcode: SQADDv1i8 + /* 96699 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 96714 + /* 96704 */ MCD_OPC_CheckPredicate, + 21, + 138, + 30, + 0, // Skip to: 104527 + /* 96709 */ MCD_OPC_Decode, + 149, + 33, + 251, + 3, // Opcode: SQADDv1i16 + /* 96714 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 96729 + /* 96719 */ MCD_OPC_CheckPredicate, + 21, + 123, + 30, + 0, // Skip to: 104527 + /* 96724 */ MCD_OPC_Decode, + 150, + 33, + 230, + 3, // Opcode: SQADDv1i32 + /* 96729 */ MCD_OPC_FilterValue, + 7, + 113, + 30, + 0, // Skip to: 104527 + /* 96734 */ MCD_OPC_CheckPredicate, + 21, + 108, + 30, + 0, // Skip to: 104527 + /* 96739 */ MCD_OPC_Decode, + 151, + 33, + 155, + 2, // Opcode: SQADDv1i64 + /* 96744 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 96766 + /* 96749 */ MCD_OPC_CheckPredicate, + 53, + 93, + 30, + 0, // Skip to: 104527 + /* 96754 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 86, + 30, + 0, // Skip to: 104527 + /* 96761 */ MCD_OPC_Decode, + 131, + 31, + 133, + 4, // Opcode: SHA1Prrr + /* 96766 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 96788 + /* 96771 */ MCD_OPC_CheckPredicate, + 53, + 71, + 30, + 0, // Skip to: 104527 + /* 96776 */ MCD_OPC_CheckField, + 16, + 8, + 40, + 64, + 30, + 0, // Skip to: 104527 + /* 96783 */ MCD_OPC_Decode, + 133, + 31, + 193, + 2, // Opcode: SHA1SU1rr + /* 96788 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 96810 + /* 96793 */ MCD_OPC_CheckPredicate, + 54, + 49, + 30, + 0, // Skip to: 104527 + /* 96798 */ MCD_OPC_CheckField, + 21, + 3, + 2, + 42, + 30, + 0, // Skip to: 104527 + /* 96805 */ MCD_OPC_Decode, + 243, + 17, + 251, + 3, // Opcode: FMULX16 + /* 96810 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 96832 + /* 96815 */ MCD_OPC_CheckPredicate, + 53, + 27, + 30, + 0, // Skip to: 104527 + /* 96820 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 20, + 30, + 0, // Skip to: 104527 + /* 96827 */ MCD_OPC_Decode, + 130, + 31, + 133, + 4, // Opcode: SHA1Mrrr + /* 96832 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 96854 + /* 96837 */ MCD_OPC_CheckPredicate, + 23, + 5, + 30, + 0, // Skip to: 104527 + /* 96842 */ MCD_OPC_CheckField, + 21, + 3, + 2, + 254, + 29, + 0, // Skip to: 104527 + /* 96849 */ MCD_OPC_Decode, + 164, + 13, + 251, + 3, // Opcode: FCMEQ16 + /* 96854 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 96876 + /* 96859 */ MCD_OPC_CheckPredicate, + 53, + 239, + 29, + 0, // Skip to: 104527 + /* 96864 */ MCD_OPC_CheckField, + 16, + 8, + 40, + 232, + 29, + 0, // Skip to: 104527 + /* 96871 */ MCD_OPC_Decode, + 136, + 31, + 193, + 2, // Opcode: SHA256SU0rr + /* 96876 */ MCD_OPC_FilterValue, + 11, + 63, + 0, + 0, // Skip to: 96944 + /* 96881 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 96884 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 96899 + /* 96889 */ MCD_OPC_CheckPredicate, + 21, + 209, + 29, + 0, // Skip to: 104527 + /* 96894 */ MCD_OPC_Decode, + 140, + 36, + 138, + 4, // Opcode: SQSUBv1i8 + /* 96899 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 96914 + /* 96904 */ MCD_OPC_CheckPredicate, + 21, + 194, + 29, + 0, // Skip to: 104527 + /* 96909 */ MCD_OPC_Decode, + 137, + 36, + 251, + 3, // Opcode: SQSUBv1i16 + /* 96914 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 96929 + /* 96919 */ MCD_OPC_CheckPredicate, + 21, + 179, + 29, + 0, // Skip to: 104527 + /* 96924 */ MCD_OPC_Decode, + 138, + 36, + 230, + 3, // Opcode: SQSUBv1i32 + /* 96929 */ MCD_OPC_FilterValue, + 7, + 169, + 29, + 0, // Skip to: 104527 + /* 96934 */ MCD_OPC_CheckPredicate, + 21, + 164, + 29, + 0, // Skip to: 104527 + /* 96939 */ MCD_OPC_Decode, + 139, + 36, + 155, + 2, // Opcode: SQSUBv1i64 + /* 96944 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 96966 + /* 96949 */ MCD_OPC_CheckPredicate, + 53, + 149, + 29, + 0, // Skip to: 104527 + /* 96954 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 142, + 29, + 0, // Skip to: 104527 + /* 96961 */ MCD_OPC_Decode, + 132, + 31, + 187, + 2, // Opcode: SHA1SU0rrr + /* 96966 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 96988 + /* 96971 */ MCD_OPC_CheckPredicate, + 21, + 127, + 29, + 0, // Skip to: 104527 + /* 96976 */ MCD_OPC_CheckField, + 21, + 3, + 7, + 120, + 29, + 0, // Skip to: 104527 + /* 96983 */ MCD_OPC_Decode, + 144, + 10, + 155, + 2, // Opcode: CMGTv1i64 + /* 96988 */ MCD_OPC_FilterValue, + 14, + 65, + 0, + 0, // Skip to: 97058 + /* 96993 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 96996 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 97011 + /* 97001 */ MCD_OPC_CheckPredicate, + 21, + 97, + 29, + 0, // Skip to: 104527 + /* 97006 */ MCD_OPC_Decode, + 245, + 40, + 139, + 4, // Opcode: SUQADDv1i8 + /* 97011 */ MCD_OPC_FilterValue, + 96, + 10, + 0, + 0, // Skip to: 97026 + /* 97016 */ MCD_OPC_CheckPredicate, + 21, + 82, + 29, + 0, // Skip to: 104527 + /* 97021 */ MCD_OPC_Decode, + 242, + 40, + 140, + 4, // Opcode: SUQADDv1i16 + /* 97026 */ MCD_OPC_FilterValue, + 160, + 1, + 10, + 0, + 0, // Skip to: 97042 + /* 97032 */ MCD_OPC_CheckPredicate, + 21, + 66, + 29, + 0, // Skip to: 104527 + /* 97037 */ MCD_OPC_Decode, + 243, + 40, + 141, + 4, // Opcode: SUQADDv1i32 + /* 97042 */ MCD_OPC_FilterValue, + 224, + 1, + 55, + 29, + 0, // Skip to: 104527 + /* 97048 */ MCD_OPC_CheckPredicate, + 21, + 50, + 29, + 0, // Skip to: 104527 + /* 97053 */ MCD_OPC_Decode, + 244, + 40, + 166, + 2, // Opcode: SUQADDv1i64 + /* 97058 */ MCD_OPC_FilterValue, + 15, + 48, + 0, + 0, // Skip to: 97111 + /* 97063 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 97066 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 97081 + /* 97071 */ MCD_OPC_CheckPredicate, + 54, + 27, + 29, + 0, // Skip to: 104527 + /* 97076 */ MCD_OPC_Decode, + 202, + 18, + 251, + 3, // Opcode: FRECPS16 + /* 97081 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 97096 + /* 97086 */ MCD_OPC_CheckPredicate, + 54, + 12, + 29, + 0, // Skip to: 104527 + /* 97091 */ MCD_OPC_Decode, + 199, + 19, + 251, + 3, // Opcode: FRSQRTS16 + /* 97096 */ MCD_OPC_FilterValue, + 7, + 2, + 29, + 0, // Skip to: 104527 + /* 97101 */ MCD_OPC_CheckPredicate, + 21, + 253, + 28, + 0, // Skip to: 104527 + /* 97106 */ MCD_OPC_Decode, + 128, + 10, + 155, + 2, // Opcode: CMGEv1i64 + /* 97111 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 97133 + /* 97116 */ MCD_OPC_CheckPredicate, + 53, + 238, + 28, + 0, // Skip to: 104527 + /* 97121 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 231, + 28, + 0, // Skip to: 104527 + /* 97128 */ MCD_OPC_Decode, + 135, + 31, + 187, + 2, // Opcode: SHA256Hrrr + /* 97133 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 97155 + /* 97138 */ MCD_OPC_CheckPredicate, + 21, + 216, + 28, + 0, // Skip to: 104527 + /* 97143 */ MCD_OPC_CheckField, + 21, + 3, + 7, + 209, + 28, + 0, // Skip to: 104527 + /* 97150 */ MCD_OPC_Decode, + 252, + 36, + 155, + 2, // Opcode: SSHLv1i64 + /* 97155 */ MCD_OPC_FilterValue, + 18, + 49, + 0, + 0, // Skip to: 97209 + /* 97160 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 97163 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 97178 + /* 97168 */ MCD_OPC_CheckPredicate, + 21, + 186, + 28, + 0, // Skip to: 104527 + /* 97173 */ MCD_OPC_Decode, + 156, + 36, + 142, + 4, // Opcode: SQXTNv1i8 + /* 97178 */ MCD_OPC_FilterValue, + 97, + 10, + 0, + 0, // Skip to: 97193 + /* 97183 */ MCD_OPC_CheckPredicate, + 21, + 171, + 28, + 0, // Skip to: 104527 + /* 97188 */ MCD_OPC_Decode, + 154, + 36, + 227, + 3, // Opcode: SQXTNv1i16 + /* 97193 */ MCD_OPC_FilterValue, + 161, + 1, + 160, + 28, + 0, // Skip to: 104527 + /* 97199 */ MCD_OPC_CheckPredicate, + 21, + 155, + 28, + 0, // Skip to: 104527 + /* 97204 */ MCD_OPC_Decode, + 155, + 36, + 213, + 2, // Opcode: SQXTNv1i32 + /* 97209 */ MCD_OPC_FilterValue, + 19, + 63, + 0, + 0, // Skip to: 97277 + /* 97214 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 97217 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 97232 + /* 97222 */ MCD_OPC_CheckPredicate, + 21, + 132, + 28, + 0, // Skip to: 104527 + /* 97227 */ MCD_OPC_Decode, + 205, + 35, + 138, + 4, // Opcode: SQSHLv1i8 + /* 97232 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 97247 + /* 97237 */ MCD_OPC_CheckPredicate, + 21, + 117, + 28, + 0, // Skip to: 104527 + /* 97242 */ MCD_OPC_Decode, + 202, + 35, + 251, + 3, // Opcode: SQSHLv1i16 + /* 97247 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 97262 + /* 97252 */ MCD_OPC_CheckPredicate, + 21, + 102, + 28, + 0, // Skip to: 104527 + /* 97257 */ MCD_OPC_Decode, + 203, + 35, + 230, + 3, // Opcode: SQSHLv1i32 + /* 97262 */ MCD_OPC_FilterValue, + 7, + 92, + 28, + 0, // Skip to: 104527 + /* 97267 */ MCD_OPC_CheckPredicate, + 21, + 87, + 28, + 0, // Skip to: 104527 + /* 97272 */ MCD_OPC_Decode, + 204, + 35, + 155, + 2, // Opcode: SQSHLv1i64 + /* 97277 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 97299 + /* 97282 */ MCD_OPC_CheckPredicate, + 53, + 72, + 28, + 0, // Skip to: 104527 + /* 97287 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 65, + 28, + 0, // Skip to: 104527 + /* 97294 */ MCD_OPC_Decode, + 134, + 31, + 187, + 2, // Opcode: SHA256H2rrr + /* 97299 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 97321 + /* 97304 */ MCD_OPC_CheckPredicate, + 21, + 50, + 28, + 0, // Skip to: 104527 + /* 97309 */ MCD_OPC_CheckField, + 21, + 3, + 7, + 43, + 28, + 0, // Skip to: 104527 + /* 97316 */ MCD_OPC_Decode, + 208, + 36, + 155, + 2, // Opcode: SRSHLv1i64 + /* 97321 */ MCD_OPC_FilterValue, + 23, + 63, + 0, + 0, // Skip to: 97389 + /* 97326 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 97329 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 97344 + /* 97334 */ MCD_OPC_CheckPredicate, + 21, + 20, + 28, + 0, // Skip to: 104527 + /* 97339 */ MCD_OPC_Decode, + 132, + 35, + 138, + 4, // Opcode: SQRSHLv1i8 + /* 97344 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 97359 + /* 97349 */ MCD_OPC_CheckPredicate, + 21, + 5, + 28, + 0, // Skip to: 104527 + /* 97354 */ MCD_OPC_Decode, + 129, + 35, + 251, + 3, // Opcode: SQRSHLv1i16 + /* 97359 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 97374 + /* 97364 */ MCD_OPC_CheckPredicate, + 21, + 246, + 27, + 0, // Skip to: 104527 + /* 97369 */ MCD_OPC_Decode, + 130, + 35, + 230, + 3, // Opcode: SQRSHLv1i32 + /* 97374 */ MCD_OPC_FilterValue, + 7, + 236, + 27, + 0, // Skip to: 104527 + /* 97379 */ MCD_OPC_CheckPredicate, + 21, + 231, + 27, + 0, // Skip to: 104527 + /* 97384 */ MCD_OPC_Decode, + 131, + 35, + 155, + 2, // Opcode: SQRSHLv1i64 + /* 97389 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 97411 + /* 97394 */ MCD_OPC_CheckPredicate, + 53, + 216, + 27, + 0, // Skip to: 104527 + /* 97399 */ MCD_OPC_CheckField, + 21, + 3, + 0, + 209, + 27, + 0, // Skip to: 104527 + /* 97406 */ MCD_OPC_Decode, + 137, + 31, + 187, + 2, // Opcode: SHA256SU1rrr + /* 97411 */ MCD_OPC_FilterValue, + 30, + 65, + 0, + 0, // Skip to: 97481 + /* 97416 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 97419 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 97434 + /* 97424 */ MCD_OPC_CheckPredicate, + 21, + 186, + 27, + 0, // Skip to: 104527 + /* 97429 */ MCD_OPC_Decode, + 129, + 33, + 143, + 4, // Opcode: SQABSv1i8 + /* 97434 */ MCD_OPC_FilterValue, + 96, + 10, + 0, + 0, // Skip to: 97449 + /* 97439 */ MCD_OPC_CheckPredicate, + 21, + 171, + 27, + 0, // Skip to: 104527 + /* 97444 */ MCD_OPC_Decode, + 254, + 32, + 246, + 3, // Opcode: SQABSv1i16 + /* 97449 */ MCD_OPC_FilterValue, + 160, + 1, + 10, + 0, + 0, // Skip to: 97465 + /* 97455 */ MCD_OPC_CheckPredicate, + 21, + 155, + 27, + 0, // Skip to: 104527 + /* 97460 */ MCD_OPC_Decode, + 255, + 32, + 225, + 3, // Opcode: SQABSv1i32 + /* 97465 */ MCD_OPC_FilterValue, + 224, + 1, + 144, + 27, + 0, // Skip to: 104527 + /* 97471 */ MCD_OPC_CheckPredicate, + 21, + 139, + 27, + 0, // Skip to: 104527 + /* 97476 */ MCD_OPC_Decode, + 128, + 33, + 156, + 2, // Opcode: SQABSv1i64 + /* 97481 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 97503 + /* 97486 */ MCD_OPC_CheckPredicate, + 21, + 124, + 27, + 0, // Skip to: 104527 + /* 97491 */ MCD_OPC_CheckField, + 21, + 3, + 7, + 117, + 27, + 0, // Skip to: 104527 + /* 97498 */ MCD_OPC_Decode, + 211, + 7, + 155, + 2, // Opcode: ADDv1i64 + /* 97503 */ MCD_OPC_FilterValue, + 34, + 18, + 0, + 0, // Skip to: 97526 + /* 97508 */ MCD_OPC_CheckPredicate, + 21, + 102, + 27, + 0, // Skip to: 104527 + /* 97513 */ MCD_OPC_CheckField, + 16, + 8, + 224, + 1, + 94, + 27, + 0, // Skip to: 104527 + /* 97521 */ MCD_OPC_Decode, + 145, + 10, + 156, + 2, // Opcode: CMGTv1i64rz + /* 97526 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 97548 + /* 97531 */ MCD_OPC_CheckPredicate, + 21, + 79, + 27, + 0, // Skip to: 104527 + /* 97536 */ MCD_OPC_CheckField, + 21, + 3, + 7, + 72, + 27, + 0, // Skip to: 104527 + /* 97543 */ MCD_OPC_Decode, + 163, + 11, + 155, + 2, // Opcode: CMTSTv1i64 + /* 97548 */ MCD_OPC_FilterValue, + 36, + 33, + 0, + 0, // Skip to: 97586 + /* 97553 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 97556 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 97571 + /* 97561 */ MCD_OPC_CheckPredicate, + 21, + 49, + 27, + 0, // Skip to: 104527 + /* 97566 */ MCD_OPC_Decode, + 198, + 33, + 144, + 4, // Opcode: SQDMLALi16 + /* 97571 */ MCD_OPC_FilterValue, + 5, + 39, + 27, + 0, // Skip to: 104527 + /* 97576 */ MCD_OPC_CheckPredicate, + 21, + 34, + 27, + 0, // Skip to: 104527 + /* 97581 */ MCD_OPC_Decode, + 199, + 33, + 145, + 4, // Opcode: SQDMLALi32 + /* 97586 */ MCD_OPC_FilterValue, + 38, + 18, + 0, + 0, // Skip to: 97609 + /* 97591 */ MCD_OPC_CheckPredicate, + 21, + 19, + 27, + 0, // Skip to: 104527 + /* 97596 */ MCD_OPC_CheckField, + 16, + 8, + 224, + 1, + 11, + 27, + 0, // Skip to: 104527 + /* 97604 */ MCD_OPC_Decode, + 241, + 9, + 156, + 2, // Opcode: CMEQv1i64rz + /* 97609 */ MCD_OPC_FilterValue, + 42, + 112, + 0, + 0, // Skip to: 97726 + /* 97614 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 97617 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 97632 + /* 97622 */ MCD_OPC_CheckPredicate, + 21, + 244, + 26, + 0, // Skip to: 104527 + /* 97627 */ MCD_OPC_Decode, + 237, + 14, + 225, + 3, // Opcode: FCVTNSv1i32 + /* 97632 */ MCD_OPC_FilterValue, + 97, + 10, + 0, + 0, // Skip to: 97647 + /* 97637 */ MCD_OPC_CheckPredicate, + 21, + 229, + 26, + 0, // Skip to: 104527 + /* 97642 */ MCD_OPC_Decode, + 238, + 14, + 156, + 2, // Opcode: FCVTNSv1i64 + /* 97647 */ MCD_OPC_FilterValue, + 121, + 10, + 0, + 0, // Skip to: 97662 + /* 97652 */ MCD_OPC_CheckPredicate, + 23, + 214, + 26, + 0, // Skip to: 104527 + /* 97657 */ MCD_OPC_Decode, + 236, + 14, + 246, + 3, // Opcode: FCVTNSv1f16 + /* 97662 */ MCD_OPC_FilterValue, + 161, + 1, + 10, + 0, + 0, // Skip to: 97678 + /* 97668 */ MCD_OPC_CheckPredicate, + 21, + 198, + 26, + 0, // Skip to: 104527 + /* 97673 */ MCD_OPC_Decode, + 143, + 15, + 225, + 3, // Opcode: FCVTPSv1i32 + /* 97678 */ MCD_OPC_FilterValue, + 224, + 1, + 10, + 0, + 0, // Skip to: 97694 + /* 97684 */ MCD_OPC_CheckPredicate, + 21, + 182, + 26, + 0, // Skip to: 104527 + /* 97689 */ MCD_OPC_Decode, + 189, + 10, + 156, + 2, // Opcode: CMLTv1i64rz + /* 97694 */ MCD_OPC_FilterValue, + 225, + 1, + 10, + 0, + 0, // Skip to: 97710 + /* 97700 */ MCD_OPC_CheckPredicate, + 21, + 166, + 26, + 0, // Skip to: 104527 + /* 97705 */ MCD_OPC_Decode, + 144, + 15, + 156, + 2, // Opcode: FCVTPSv1i64 + /* 97710 */ MCD_OPC_FilterValue, + 249, + 1, + 155, + 26, + 0, // Skip to: 104527 + /* 97716 */ MCD_OPC_CheckPredicate, + 23, + 150, + 26, + 0, // Skip to: 104527 + /* 97721 */ MCD_OPC_Decode, + 142, + 15, + 246, + 3, // Opcode: FCVTPSv1f16 + /* 97726 */ MCD_OPC_FilterValue, + 44, + 33, + 0, + 0, // Skip to: 97764 + /* 97731 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 97734 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 97749 + /* 97739 */ MCD_OPC_CheckPredicate, + 21, + 127, + 26, + 0, // Skip to: 104527 + /* 97744 */ MCD_OPC_Decode, + 223, + 33, + 144, + 4, // Opcode: SQDMLSLi16 + /* 97749 */ MCD_OPC_FilterValue, + 5, + 117, + 26, + 0, // Skip to: 104527 + /* 97754 */ MCD_OPC_CheckPredicate, + 21, + 112, + 26, + 0, // Skip to: 104527 + /* 97759 */ MCD_OPC_Decode, + 224, + 33, + 145, + 4, // Opcode: SQDMLSLi32 + /* 97764 */ MCD_OPC_FilterValue, + 45, + 33, + 0, + 0, // Skip to: 97802 + /* 97769 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 97772 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 97787 + /* 97777 */ MCD_OPC_CheckPredicate, + 21, + 89, + 26, + 0, // Skip to: 104527 + /* 97782 */ MCD_OPC_Decode, + 242, + 33, + 251, + 3, // Opcode: SQDMULHv1i16 + /* 97787 */ MCD_OPC_FilterValue, + 5, + 79, + 26, + 0, // Skip to: 104527 + /* 97792 */ MCD_OPC_CheckPredicate, + 21, + 74, + 26, + 0, // Skip to: 104527 + /* 97797 */ MCD_OPC_Decode, + 244, + 33, + 230, + 3, // Opcode: SQDMULHv1i32 + /* 97802 */ MCD_OPC_FilterValue, + 46, + 128, + 0, + 0, // Skip to: 97935 + /* 97807 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 97810 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 97825 + /* 97815 */ MCD_OPC_CheckPredicate, + 21, + 51, + 26, + 0, // Skip to: 104527 + /* 97820 */ MCD_OPC_Decode, + 209, + 14, + 225, + 3, // Opcode: FCVTMSv1i32 + /* 97825 */ MCD_OPC_FilterValue, + 97, + 10, + 0, + 0, // Skip to: 97840 + /* 97830 */ MCD_OPC_CheckPredicate, + 21, + 36, + 26, + 0, // Skip to: 104527 + /* 97835 */ MCD_OPC_Decode, + 210, + 14, + 156, + 2, // Opcode: FCVTMSv1i64 + /* 97840 */ MCD_OPC_FilterValue, + 121, + 10, + 0, + 0, // Skip to: 97855 + /* 97845 */ MCD_OPC_CheckPredicate, + 23, + 21, + 26, + 0, // Skip to: 104527 + /* 97850 */ MCD_OPC_Decode, + 208, + 14, + 246, + 3, // Opcode: FCVTMSv1f16 + /* 97855 */ MCD_OPC_FilterValue, + 161, + 1, + 10, + 0, + 0, // Skip to: 97871 + /* 97861 */ MCD_OPC_CheckPredicate, + 21, + 5, + 26, + 0, // Skip to: 104527 + /* 97866 */ MCD_OPC_Decode, + 194, + 15, + 225, + 3, // Opcode: FCVTZSv1i32 + /* 97871 */ MCD_OPC_FilterValue, + 224, + 1, + 10, + 0, + 0, // Skip to: 97887 + /* 97877 */ MCD_OPC_CheckPredicate, + 21, + 245, + 25, + 0, // Skip to: 104527 + /* 97882 */ MCD_OPC_Decode, + 133, + 7, + 156, + 2, // Opcode: ABSv1i64 + /* 97887 */ MCD_OPC_FilterValue, + 225, + 1, + 10, + 0, + 0, // Skip to: 97903 + /* 97893 */ MCD_OPC_CheckPredicate, + 21, + 229, + 25, + 0, // Skip to: 104527 + /* 97898 */ MCD_OPC_Decode, + 195, + 15, + 156, + 2, // Opcode: FCVTZSv1i64 + /* 97903 */ MCD_OPC_FilterValue, + 241, + 1, + 10, + 0, + 0, // Skip to: 97919 + /* 97909 */ MCD_OPC_CheckPredicate, + 21, + 213, + 25, + 0, // Skip to: 104527 + /* 97914 */ MCD_OPC_Decode, + 171, + 7, + 161, + 2, // Opcode: ADDPv2i64p + /* 97919 */ MCD_OPC_FilterValue, + 249, + 1, + 202, + 25, + 0, // Skip to: 104527 + /* 97925 */ MCD_OPC_CheckPredicate, + 23, + 197, + 25, + 0, // Skip to: 104527 + /* 97930 */ MCD_OPC_Decode, + 193, + 15, + 246, + 3, // Opcode: FCVTZSv1f16 + /* 97935 */ MCD_OPC_FilterValue, + 50, + 127, + 0, + 0, // Skip to: 98067 + /* 97940 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 97943 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 97958 + /* 97948 */ MCD_OPC_CheckPredicate, + 21, + 174, + 25, + 0, // Skip to: 104527 + /* 97953 */ MCD_OPC_Decode, + 171, + 14, + 225, + 3, // Opcode: FCVTASv1i32 + /* 97958 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 97973 + /* 97963 */ MCD_OPC_CheckPredicate, + 23, + 159, + 25, + 0, // Skip to: 104527 + /* 97968 */ MCD_OPC_Decode, + 158, + 16, + 167, + 2, // Opcode: FMAXNMPv2i16p + /* 97973 */ MCD_OPC_FilterValue, + 97, + 10, + 0, + 0, // Skip to: 97988 + /* 97978 */ MCD_OPC_CheckPredicate, + 21, + 144, + 25, + 0, // Skip to: 104527 + /* 97983 */ MCD_OPC_Decode, + 172, + 14, + 156, + 2, // Opcode: FCVTASv1i64 + /* 97988 */ MCD_OPC_FilterValue, + 121, + 10, + 0, + 0, // Skip to: 98003 + /* 97993 */ MCD_OPC_CheckPredicate, + 23, + 129, + 25, + 0, // Skip to: 104527 + /* 97998 */ MCD_OPC_Decode, + 170, + 14, + 246, + 3, // Opcode: FCVTASv1f16 + /* 98003 */ MCD_OPC_FilterValue, + 160, + 1, + 10, + 0, + 0, // Skip to: 98019 + /* 98009 */ MCD_OPC_CheckPredicate, + 21, + 113, + 25, + 0, // Skip to: 104527 + /* 98014 */ MCD_OPC_Decode, + 218, + 13, + 225, + 3, // Opcode: FCMGTv1i32rz + /* 98019 */ MCD_OPC_FilterValue, + 176, + 1, + 10, + 0, + 0, // Skip to: 98035 + /* 98025 */ MCD_OPC_CheckPredicate, + 23, + 97, + 25, + 0, // Skip to: 104527 + /* 98030 */ MCD_OPC_Decode, + 220, + 16, + 167, + 2, // Opcode: FMINNMPv2i16p + /* 98035 */ MCD_OPC_FilterValue, + 224, + 1, + 10, + 0, + 0, // Skip to: 98051 + /* 98041 */ MCD_OPC_CheckPredicate, + 21, + 81, + 25, + 0, // Skip to: 104527 + /* 98046 */ MCD_OPC_Decode, + 219, + 13, + 156, + 2, // Opcode: FCMGTv1i64rz + /* 98051 */ MCD_OPC_FilterValue, + 248, + 1, + 70, + 25, + 0, // Skip to: 104527 + /* 98057 */ MCD_OPC_CheckPredicate, + 23, + 65, + 25, + 0, // Skip to: 104527 + /* 98062 */ MCD_OPC_Decode, + 217, + 13, + 246, + 3, // Opcode: FCMGTv1i16rz + /* 98067 */ MCD_OPC_FilterValue, + 52, + 33, + 0, + 0, // Skip to: 98105 + /* 98072 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 98075 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 98090 + /* 98080 */ MCD_OPC_CheckPredicate, + 21, + 42, + 25, + 0, // Skip to: 104527 + /* 98085 */ MCD_OPC_Decode, + 136, + 34, + 146, + 4, // Opcode: SQDMULLi16 + /* 98090 */ MCD_OPC_FilterValue, + 5, + 32, + 25, + 0, // Skip to: 104527 + /* 98095 */ MCD_OPC_CheckPredicate, + 21, + 27, + 25, + 0, // Skip to: 104527 + /* 98100 */ MCD_OPC_Decode, + 137, + 34, + 147, + 4, // Opcode: SQDMULLi32 + /* 98105 */ MCD_OPC_FilterValue, + 54, + 159, + 0, + 0, // Skip to: 98269 + /* 98110 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 98113 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 98128 + /* 98118 */ MCD_OPC_CheckPredicate, + 21, + 4, + 25, + 0, // Skip to: 104527 + /* 98123 */ MCD_OPC_Decode, + 222, + 30, + 225, + 3, // Opcode: SCVTFv1i32 + /* 98128 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 98143 + /* 98133 */ MCD_OPC_CheckPredicate, + 23, + 245, + 24, + 0, // Skip to: 104527 + /* 98138 */ MCD_OPC_Decode, + 254, + 12, + 167, + 2, // Opcode: FADDPv2i16p + /* 98143 */ MCD_OPC_FilterValue, + 97, + 10, + 0, + 0, // Skip to: 98158 + /* 98148 */ MCD_OPC_CheckPredicate, + 21, + 230, + 24, + 0, // Skip to: 104527 + /* 98153 */ MCD_OPC_Decode, + 223, + 30, + 156, + 2, // Opcode: SCVTFv1i64 + /* 98158 */ MCD_OPC_FilterValue, + 121, + 10, + 0, + 0, // Skip to: 98173 + /* 98163 */ MCD_OPC_CheckPredicate, + 23, + 215, + 24, + 0, // Skip to: 104527 + /* 98168 */ MCD_OPC_Decode, + 221, + 30, + 246, + 3, // Opcode: SCVTFv1i16 + /* 98173 */ MCD_OPC_FilterValue, + 160, + 1, + 10, + 0, + 0, // Skip to: 98189 + /* 98179 */ MCD_OPC_CheckPredicate, + 21, + 199, + 24, + 0, // Skip to: 104527 + /* 98184 */ MCD_OPC_Decode, + 174, + 13, + 225, + 3, // Opcode: FCMEQv1i32rz + /* 98189 */ MCD_OPC_FilterValue, + 161, + 1, + 10, + 0, + 0, // Skip to: 98205 + /* 98195 */ MCD_OPC_CheckPredicate, + 22, + 183, + 24, + 0, // Skip to: 104527 + /* 98200 */ MCD_OPC_Decode, + 195, + 18, + 225, + 3, // Opcode: FRECPEv1i32 + /* 98205 */ MCD_OPC_FilterValue, + 224, + 1, + 10, + 0, + 0, // Skip to: 98221 + /* 98211 */ MCD_OPC_CheckPredicate, + 21, + 167, + 24, + 0, // Skip to: 104527 + /* 98216 */ MCD_OPC_Decode, + 175, + 13, + 156, + 2, // Opcode: FCMEQv1i64rz + /* 98221 */ MCD_OPC_FilterValue, + 225, + 1, + 10, + 0, + 0, // Skip to: 98237 + /* 98227 */ MCD_OPC_CheckPredicate, + 22, + 151, + 24, + 0, // Skip to: 104527 + /* 98232 */ MCD_OPC_Decode, + 196, + 18, + 156, + 2, // Opcode: FRECPEv1i64 + /* 98237 */ MCD_OPC_FilterValue, + 248, + 1, + 10, + 0, + 0, // Skip to: 98253 + /* 98243 */ MCD_OPC_CheckPredicate, + 23, + 135, + 24, + 0, // Skip to: 104527 + /* 98248 */ MCD_OPC_Decode, + 173, + 13, + 246, + 3, // Opcode: FCMEQv1i16rz + /* 98253 */ MCD_OPC_FilterValue, + 249, + 1, + 124, + 24, + 0, // Skip to: 104527 + /* 98259 */ MCD_OPC_CheckPredicate, + 54, + 119, + 24, + 0, // Skip to: 104527 + /* 98264 */ MCD_OPC_Decode, + 194, + 18, + 246, + 3, // Opcode: FRECPEv1f16 + /* 98269 */ MCD_OPC_FilterValue, + 55, + 33, + 0, + 0, // Skip to: 98307 + /* 98274 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 98277 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 98292 + /* 98282 */ MCD_OPC_CheckPredicate, + 22, + 96, + 24, + 0, // Skip to: 104527 + /* 98287 */ MCD_OPC_Decode, + 244, + 17, + 230, + 3, // Opcode: FMULX32 + /* 98292 */ MCD_OPC_FilterValue, + 3, + 86, + 24, + 0, // Skip to: 104527 + /* 98297 */ MCD_OPC_CheckPredicate, + 22, + 81, + 24, + 0, // Skip to: 104527 + /* 98302 */ MCD_OPC_Decode, + 245, + 17, + 155, + 2, // Opcode: FMULX64 + /* 98307 */ MCD_OPC_FilterValue, + 57, + 33, + 0, + 0, // Skip to: 98345 + /* 98312 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 98315 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 98330 + /* 98320 */ MCD_OPC_CheckPredicate, + 21, + 58, + 24, + 0, // Skip to: 104527 + /* 98325 */ MCD_OPC_Decode, + 165, + 13, + 230, + 3, // Opcode: FCMEQ32 + /* 98330 */ MCD_OPC_FilterValue, + 3, + 48, + 24, + 0, // Skip to: 104527 + /* 98335 */ MCD_OPC_CheckPredicate, + 21, + 43, + 24, + 0, // Skip to: 104527 + /* 98340 */ MCD_OPC_Decode, + 166, + 13, + 155, + 2, // Opcode: FCMEQ64 + /* 98345 */ MCD_OPC_FilterValue, + 58, + 51, + 0, + 0, // Skip to: 98401 + /* 98350 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 98353 */ MCD_OPC_FilterValue, + 160, + 1, + 10, + 0, + 0, // Skip to: 98369 + /* 98359 */ MCD_OPC_CheckPredicate, + 21, + 19, + 24, + 0, // Skip to: 104527 + /* 98364 */ MCD_OPC_Decode, + 130, + 14, + 225, + 3, // Opcode: FCMLTv1i32rz + /* 98369 */ MCD_OPC_FilterValue, + 224, + 1, + 10, + 0, + 0, // Skip to: 98385 + /* 98375 */ MCD_OPC_CheckPredicate, + 21, + 3, + 24, + 0, // Skip to: 104527 + /* 98380 */ MCD_OPC_Decode, + 131, + 14, + 156, + 2, // Opcode: FCMLTv1i64rz + /* 98385 */ MCD_OPC_FilterValue, + 248, + 1, + 248, + 23, + 0, // Skip to: 104527 + /* 98391 */ MCD_OPC_CheckPredicate, + 23, + 243, + 23, + 0, // Skip to: 104527 + /* 98396 */ MCD_OPC_Decode, + 129, + 14, + 246, + 3, // Opcode: FCMLTv1i16rz + /* 98401 */ MCD_OPC_FilterValue, + 62, + 82, + 0, + 0, // Skip to: 98488 + /* 98406 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 98409 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 98424 + /* 98414 */ MCD_OPC_CheckPredicate, + 23, + 220, + 23, + 0, // Skip to: 104527 + /* 98419 */ MCD_OPC_Decode, + 187, + 16, + 167, + 2, // Opcode: FMAXPv2i16p + /* 98424 */ MCD_OPC_FilterValue, + 161, + 1, + 10, + 0, + 0, // Skip to: 98440 + /* 98430 */ MCD_OPC_CheckPredicate, + 22, + 204, + 23, + 0, // Skip to: 104527 + /* 98435 */ MCD_OPC_Decode, + 217, + 18, + 225, + 3, // Opcode: FRECPXv1i32 + /* 98440 */ MCD_OPC_FilterValue, + 176, + 1, + 10, + 0, + 0, // Skip to: 98456 + /* 98446 */ MCD_OPC_CheckPredicate, + 23, + 188, + 23, + 0, // Skip to: 104527 + /* 98451 */ MCD_OPC_Decode, + 249, + 16, + 167, + 2, // Opcode: FMINPv2i16p + /* 98456 */ MCD_OPC_FilterValue, + 225, + 1, + 10, + 0, + 0, // Skip to: 98472 + /* 98462 */ MCD_OPC_CheckPredicate, + 22, + 172, + 23, + 0, // Skip to: 104527 + /* 98467 */ MCD_OPC_Decode, + 218, + 18, + 156, + 2, // Opcode: FRECPXv1i64 + /* 98472 */ MCD_OPC_FilterValue, + 249, + 1, + 161, + 23, + 0, // Skip to: 104527 + /* 98478 */ MCD_OPC_CheckPredicate, + 54, + 156, + 23, + 0, // Skip to: 104527 + /* 98483 */ MCD_OPC_Decode, + 216, + 18, + 246, + 3, // Opcode: FRECPXv1f16 + /* 98488 */ MCD_OPC_FilterValue, + 63, + 146, + 23, + 0, // Skip to: 104527 + /* 98493 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 98496 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 98511 + /* 98501 */ MCD_OPC_CheckPredicate, + 22, + 133, + 23, + 0, // Skip to: 104527 + /* 98506 */ MCD_OPC_Decode, + 203, + 18, + 230, + 3, // Opcode: FRECPS32 + /* 98511 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 98526 + /* 98516 */ MCD_OPC_CheckPredicate, + 22, + 118, + 23, + 0, // Skip to: 104527 + /* 98521 */ MCD_OPC_Decode, + 204, + 18, + 155, + 2, // Opcode: FRECPS64 + /* 98526 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 98541 + /* 98531 */ MCD_OPC_CheckPredicate, + 22, + 103, + 23, + 0, // Skip to: 104527 + /* 98536 */ MCD_OPC_Decode, + 200, + 19, + 230, + 3, // Opcode: FRSQRTS32 + /* 98541 */ MCD_OPC_FilterValue, + 7, + 93, + 23, + 0, // Skip to: 104527 + /* 98546 */ MCD_OPC_CheckPredicate, + 22, + 88, + 23, + 0, // Skip to: 104527 + /* 98551 */ MCD_OPC_Decode, + 201, + 19, + 155, + 2, // Opcode: FRSQRTS64 + /* 98556 */ MCD_OPC_FilterValue, + 3, + 78, + 23, + 0, // Skip to: 104527 + /* 98561 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 98564 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 98593 + /* 98569 */ MCD_OPC_CheckPredicate, + 21, + 65, + 23, + 0, // Skip to: 104527 + /* 98574 */ MCD_OPC_CheckField, + 22, + 2, + 1, + 58, + 23, + 0, // Skip to: 104527 + /* 98581 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 51, + 23, + 0, // Skip to: 104527 + /* 98588 */ MCD_OPC_Decode, + 131, + 37, + 148, + 4, // Opcode: SSHRd + /* 98593 */ MCD_OPC_FilterValue, + 1, + 98, + 0, + 0, // Skip to: 98696 + /* 98598 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 98601 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 98623 + /* 98606 */ MCD_OPC_CheckPredicate, + 23, + 28, + 23, + 0, // Skip to: 104527 + /* 98611 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 21, + 23, + 0, // Skip to: 104527 + /* 98618 */ MCD_OPC_Decode, + 163, + 17, + 149, + 4, // Opcode: FMLAv1i16_indexed + /* 98623 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 98645 + /* 98628 */ MCD_OPC_CheckPredicate, + 21, + 6, + 23, + 0, // Skip to: 104527 + /* 98633 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 255, + 22, + 0, // Skip to: 104527 + /* 98640 */ MCD_OPC_Decode, + 143, + 37, + 150, + 4, // Opcode: SSRAd + /* 98645 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 98667 + /* 98650 */ MCD_OPC_CheckPredicate, + 21, + 240, + 22, + 0, // Skip to: 104527 + /* 98655 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 233, + 22, + 0, // Skip to: 104527 + /* 98662 */ MCD_OPC_Decode, + 164, + 17, + 151, + 4, // Opcode: FMLAv1i32_indexed + /* 98667 */ MCD_OPC_FilterValue, + 3, + 223, + 22, + 0, // Skip to: 104527 + /* 98672 */ MCD_OPC_CheckPredicate, + 21, + 218, + 22, + 0, // Skip to: 104527 + /* 98677 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 211, + 22, + 0, // Skip to: 104527 + /* 98684 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 204, + 22, + 0, // Skip to: 104527 + /* 98691 */ MCD_OPC_Decode, + 165, + 17, + 152, + 4, // Opcode: FMLAv1i64_indexed + /* 98696 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 98725 + /* 98701 */ MCD_OPC_CheckPredicate, + 21, + 189, + 22, + 0, // Skip to: 104527 + /* 98706 */ MCD_OPC_CheckField, + 22, + 2, + 1, + 182, + 22, + 0, // Skip to: 104527 + /* 98713 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 175, + 22, + 0, // Skip to: 104527 + /* 98720 */ MCD_OPC_Decode, + 219, + 36, + 148, + 4, // Opcode: SRSHRd + /* 98725 */ MCD_OPC_FilterValue, + 3, + 70, + 0, + 0, // Skip to: 98800 + /* 98730 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 98733 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 98771 + /* 98738 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 98741 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 98756 + /* 98746 */ MCD_OPC_CheckPredicate, + 21, + 144, + 22, + 0, // Skip to: 104527 + /* 98751 */ MCD_OPC_Decode, + 200, + 33, + 153, + 4, // Opcode: SQDMLALv1i32_indexed + /* 98756 */ MCD_OPC_FilterValue, + 2, + 134, + 22, + 0, // Skip to: 104527 + /* 98761 */ MCD_OPC_CheckPredicate, + 21, + 129, + 22, + 0, // Skip to: 104527 + /* 98766 */ MCD_OPC_Decode, + 201, + 33, + 154, + 4, // Opcode: SQDMLALv1i64_indexed + /* 98771 */ MCD_OPC_FilterValue, + 1, + 119, + 22, + 0, // Skip to: 104527 + /* 98776 */ MCD_OPC_CheckPredicate, + 21, + 114, + 22, + 0, // Skip to: 104527 + /* 98781 */ MCD_OPC_CheckField, + 22, + 2, + 1, + 107, + 22, + 0, // Skip to: 104527 + /* 98788 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 100, + 22, + 0, // Skip to: 104527 + /* 98795 */ MCD_OPC_Decode, + 231, + 36, + 150, + 4, // Opcode: SRSRAd + /* 98800 */ MCD_OPC_FilterValue, + 5, + 98, + 0, + 0, // Skip to: 98903 + /* 98805 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 98808 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 98830 + /* 98813 */ MCD_OPC_CheckPredicate, + 23, + 77, + 22, + 0, // Skip to: 104527 + /* 98818 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 70, + 22, + 0, // Skip to: 104527 + /* 98825 */ MCD_OPC_Decode, + 194, + 17, + 149, + 4, // Opcode: FMLSv1i16_indexed + /* 98830 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 98852 + /* 98835 */ MCD_OPC_CheckPredicate, + 21, + 55, + 22, + 0, // Skip to: 104527 + /* 98840 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 48, + 22, + 0, // Skip to: 104527 + /* 98847 */ MCD_OPC_Decode, + 158, + 31, + 155, + 4, // Opcode: SHLd + /* 98852 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 98874 + /* 98857 */ MCD_OPC_CheckPredicate, + 21, + 33, + 22, + 0, // Skip to: 104527 + /* 98862 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 26, + 22, + 0, // Skip to: 104527 + /* 98869 */ MCD_OPC_Decode, + 195, + 17, + 151, + 4, // Opcode: FMLSv1i32_indexed + /* 98874 */ MCD_OPC_FilterValue, + 3, + 16, + 22, + 0, // Skip to: 104527 + /* 98879 */ MCD_OPC_CheckPredicate, + 21, + 11, + 22, + 0, // Skip to: 104527 + /* 98884 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 4, + 22, + 0, // Skip to: 104527 + /* 98891 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 253, + 21, + 0, // Skip to: 104527 + /* 98898 */ MCD_OPC_Decode, + 196, + 17, + 152, + 4, // Opcode: FMLSv1i64_indexed + /* 98903 */ MCD_OPC_FilterValue, + 7, + 159, + 0, + 0, // Skip to: 99067 + /* 98908 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 98911 */ MCD_OPC_FilterValue, + 0, + 84, + 0, + 0, // Skip to: 99000 + /* 98916 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 98919 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 98978 + /* 98924 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 98927 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 98956 + /* 98932 */ MCD_OPC_CheckPredicate, + 21, + 214, + 21, + 0, // Skip to: 104527 + /* 98937 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 207, + 21, + 0, // Skip to: 104527 + /* 98944 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 200, + 21, + 0, // Skip to: 104527 + /* 98951 */ MCD_OPC_Decode, + 196, + 35, + 156, + 4, // Opcode: SQSHLb + /* 98956 */ MCD_OPC_FilterValue, + 1, + 190, + 21, + 0, // Skip to: 104527 + /* 98961 */ MCD_OPC_CheckPredicate, + 21, + 185, + 21, + 0, // Skip to: 104527 + /* 98966 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 178, + 21, + 0, // Skip to: 104527 + /* 98973 */ MCD_OPC_Decode, + 198, + 35, + 157, + 4, // Opcode: SQSHLh + /* 98978 */ MCD_OPC_FilterValue, + 1, + 168, + 21, + 0, // Skip to: 104527 + /* 98983 */ MCD_OPC_CheckPredicate, + 21, + 163, + 21, + 0, // Skip to: 104527 + /* 98988 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 156, + 21, + 0, // Skip to: 104527 + /* 98995 */ MCD_OPC_Decode, + 199, + 35, + 158, + 4, // Opcode: SQSHLs + /* 99000 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 99045 + /* 99005 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 99008 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 99023 + /* 99013 */ MCD_OPC_CheckPredicate, + 21, + 133, + 21, + 0, // Skip to: 104527 + /* 99018 */ MCD_OPC_Decode, + 225, + 33, + 153, + 4, // Opcode: SQDMLSLv1i32_indexed + /* 99023 */ MCD_OPC_FilterValue, + 1, + 123, + 21, + 0, // Skip to: 104527 + /* 99028 */ MCD_OPC_CheckPredicate, + 21, + 118, + 21, + 0, // Skip to: 104527 + /* 99033 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 111, + 21, + 0, // Skip to: 104527 + /* 99040 */ MCD_OPC_Decode, + 197, + 35, + 155, + 4, // Opcode: SQSHLd + /* 99045 */ MCD_OPC_FilterValue, + 2, + 101, + 21, + 0, // Skip to: 104527 + /* 99050 */ MCD_OPC_CheckPredicate, + 21, + 96, + 21, + 0, // Skip to: 104527 + /* 99055 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 89, + 21, + 0, // Skip to: 104527 + /* 99062 */ MCD_OPC_Decode, + 226, + 33, + 154, + 4, // Opcode: SQDMLSLv1i64_indexed + /* 99067 */ MCD_OPC_FilterValue, + 9, + 221, + 0, + 0, // Skip to: 99293 + /* 99072 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 99075 */ MCD_OPC_FilterValue, + 0, + 162, + 0, + 0, // Skip to: 99242 + /* 99080 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 99083 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 99098 + /* 99088 */ MCD_OPC_CheckPredicate, + 23, + 58, + 21, + 0, // Skip to: 104527 + /* 99093 */ MCD_OPC_Decode, + 146, + 18, + 159, + 4, // Opcode: FMULv1i16_indexed + /* 99098 */ MCD_OPC_FilterValue, + 1, + 48, + 21, + 0, // Skip to: 104527 + /* 99103 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 99106 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 99174 + /* 99111 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 99114 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 99159 + /* 99119 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 99122 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 99144 + /* 99127 */ MCD_OPC_CheckPredicate, + 21, + 19, + 21, + 0, // Skip to: 104527 + /* 99132 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 12, + 21, + 0, // Skip to: 104527 + /* 99139 */ MCD_OPC_Decode, + 224, + 35, + 160, + 4, // Opcode: SQSHRNb + /* 99144 */ MCD_OPC_FilterValue, + 1, + 2, + 21, + 0, // Skip to: 104527 + /* 99149 */ MCD_OPC_CheckPredicate, + 21, + 253, + 20, + 0, // Skip to: 104527 + /* 99154 */ MCD_OPC_Decode, + 225, + 35, + 161, + 4, // Opcode: SQSHRNh + /* 99159 */ MCD_OPC_FilterValue, + 1, + 243, + 20, + 0, // Skip to: 104527 + /* 99164 */ MCD_OPC_CheckPredicate, + 21, + 238, + 20, + 0, // Skip to: 104527 + /* 99169 */ MCD_OPC_Decode, + 226, + 35, + 162, + 4, // Opcode: SQSHRNs + /* 99174 */ MCD_OPC_FilterValue, + 1, + 228, + 20, + 0, // Skip to: 104527 + /* 99179 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 99182 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 99227 + /* 99187 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 99190 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 99212 + /* 99195 */ MCD_OPC_CheckPredicate, + 21, + 207, + 20, + 0, // Skip to: 104527 + /* 99200 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 200, + 20, + 0, // Skip to: 104527 + /* 99207 */ MCD_OPC_Decode, + 145, + 35, + 160, + 4, // Opcode: SQRSHRNb + /* 99212 */ MCD_OPC_FilterValue, + 1, + 190, + 20, + 0, // Skip to: 104527 + /* 99217 */ MCD_OPC_CheckPredicate, + 21, + 185, + 20, + 0, // Skip to: 104527 + /* 99222 */ MCD_OPC_Decode, + 146, + 35, + 161, + 4, // Opcode: SQRSHRNh + /* 99227 */ MCD_OPC_FilterValue, + 1, + 175, + 20, + 0, // Skip to: 104527 + /* 99232 */ MCD_OPC_CheckPredicate, + 21, + 170, + 20, + 0, // Skip to: 104527 + /* 99237 */ MCD_OPC_Decode, + 147, + 35, + 162, + 4, // Opcode: SQRSHRNs + /* 99242 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 99264 + /* 99247 */ MCD_OPC_CheckPredicate, + 21, + 155, + 20, + 0, // Skip to: 104527 + /* 99252 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 148, + 20, + 0, // Skip to: 104527 + /* 99259 */ MCD_OPC_Decode, + 147, + 18, + 163, + 4, // Opcode: FMULv1i32_indexed + /* 99264 */ MCD_OPC_FilterValue, + 3, + 138, + 20, + 0, // Skip to: 104527 + /* 99269 */ MCD_OPC_CheckPredicate, + 21, + 133, + 20, + 0, // Skip to: 104527 + /* 99274 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 126, + 20, + 0, // Skip to: 104527 + /* 99281 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 119, + 20, + 0, // Skip to: 104527 + /* 99288 */ MCD_OPC_Decode, + 148, + 18, + 164, + 4, // Opcode: FMULv1i64_indexed + /* 99293 */ MCD_OPC_FilterValue, + 11, + 47, + 0, + 0, // Skip to: 99345 + /* 99298 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 99301 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 99323 + /* 99306 */ MCD_OPC_CheckPredicate, + 21, + 96, + 20, + 0, // Skip to: 104527 + /* 99311 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 89, + 20, + 0, // Skip to: 104527 + /* 99318 */ MCD_OPC_Decode, + 138, + 34, + 165, + 4, // Opcode: SQDMULLv1i32_indexed + /* 99323 */ MCD_OPC_FilterValue, + 2, + 79, + 20, + 0, // Skip to: 104527 + /* 99328 */ MCD_OPC_CheckPredicate, + 21, + 74, + 20, + 0, // Skip to: 104527 + /* 99333 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 67, + 20, + 0, // Skip to: 104527 + /* 99340 */ MCD_OPC_Decode, + 139, + 34, + 166, + 4, // Opcode: SQDMULLv1i64_indexed + /* 99345 */ MCD_OPC_FilterValue, + 12, + 47, + 0, + 0, // Skip to: 99397 + /* 99350 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 99353 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 99375 + /* 99358 */ MCD_OPC_CheckPredicate, + 21, + 44, + 20, + 0, // Skip to: 104527 + /* 99363 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 37, + 20, + 0, // Skip to: 104527 + /* 99370 */ MCD_OPC_Decode, + 243, + 33, + 159, + 4, // Opcode: SQDMULHv1i16_indexed + /* 99375 */ MCD_OPC_FilterValue, + 2, + 27, + 20, + 0, // Skip to: 104527 + /* 99380 */ MCD_OPC_CheckPredicate, + 21, + 22, + 20, + 0, // Skip to: 104527 + /* 99385 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 15, + 20, + 0, // Skip to: 104527 + /* 99392 */ MCD_OPC_Decode, + 245, + 33, + 163, + 4, // Opcode: SQDMULHv1i32_indexed + /* 99397 */ MCD_OPC_FilterValue, + 13, + 47, + 0, + 0, // Skip to: 99449 + /* 99402 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 99405 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 99427 + /* 99410 */ MCD_OPC_CheckPredicate, + 21, + 248, + 19, + 0, // Skip to: 104527 + /* 99415 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 241, + 19, + 0, // Skip to: 104527 + /* 99422 */ MCD_OPC_Decode, + 237, + 34, + 159, + 4, // Opcode: SQRDMULHv1i16_indexed + /* 99427 */ MCD_OPC_FilterValue, + 2, + 231, + 19, + 0, // Skip to: 104527 + /* 99432 */ MCD_OPC_CheckPredicate, + 21, + 226, + 19, + 0, // Skip to: 104527 + /* 99437 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 219, + 19, + 0, // Skip to: 104527 + /* 99444 */ MCD_OPC_Decode, + 239, + 34, + 163, + 4, // Opcode: SQRDMULHv1i32_indexed + /* 99449 */ MCD_OPC_FilterValue, + 14, + 84, + 0, + 0, // Skip to: 99538 + /* 99454 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 99457 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 99516 + /* 99462 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 99465 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 99494 + /* 99470 */ MCD_OPC_CheckPredicate, + 23, + 188, + 19, + 0, // Skip to: 104527 + /* 99475 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 181, + 19, + 0, // Skip to: 104527 + /* 99482 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 174, + 19, + 0, // Skip to: 104527 + /* 99489 */ MCD_OPC_Decode, + 219, + 30, + 167, + 4, // Opcode: SCVTFh + /* 99494 */ MCD_OPC_FilterValue, + 1, + 164, + 19, + 0, // Skip to: 104527 + /* 99499 */ MCD_OPC_CheckPredicate, + 21, + 159, + 19, + 0, // Skip to: 104527 + /* 99504 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 152, + 19, + 0, // Skip to: 104527 + /* 99511 */ MCD_OPC_Decode, + 220, + 30, + 168, + 4, // Opcode: SCVTFs + /* 99516 */ MCD_OPC_FilterValue, + 1, + 142, + 19, + 0, // Skip to: 104527 + /* 99521 */ MCD_OPC_CheckPredicate, + 21, + 137, + 19, + 0, // Skip to: 104527 + /* 99526 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 130, + 19, + 0, // Skip to: 104527 + /* 99533 */ MCD_OPC_Decode, + 218, + 30, + 148, + 4, // Opcode: SCVTFd + /* 99538 */ MCD_OPC_FilterValue, + 15, + 120, + 19, + 0, // Skip to: 104527 + /* 99543 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 99546 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 99605 + /* 99551 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 99554 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 99583 + /* 99559 */ MCD_OPC_CheckPredicate, + 23, + 99, + 19, + 0, // Skip to: 104527 + /* 99564 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 92, + 19, + 0, // Skip to: 104527 + /* 99571 */ MCD_OPC_CheckField, + 10, + 2, + 3, + 85, + 19, + 0, // Skip to: 104527 + /* 99578 */ MCD_OPC_Decode, + 191, + 15, + 167, + 4, // Opcode: FCVTZSh + /* 99583 */ MCD_OPC_FilterValue, + 1, + 75, + 19, + 0, // Skip to: 104527 + /* 99588 */ MCD_OPC_CheckPredicate, + 21, + 70, + 19, + 0, // Skip to: 104527 + /* 99593 */ MCD_OPC_CheckField, + 10, + 2, + 3, + 63, + 19, + 0, // Skip to: 104527 + /* 99600 */ MCD_OPC_Decode, + 192, + 15, + 168, + 4, // Opcode: FCVTZSs + /* 99605 */ MCD_OPC_FilterValue, + 1, + 53, + 19, + 0, // Skip to: 104527 + /* 99610 */ MCD_OPC_CheckPredicate, + 21, + 48, + 19, + 0, // Skip to: 104527 + /* 99615 */ MCD_OPC_CheckField, + 10, + 2, + 3, + 41, + 19, + 0, // Skip to: 104527 + /* 99622 */ MCD_OPC_Decode, + 190, + 15, + 148, + 4, // Opcode: FCVTZSd + /* 99627 */ MCD_OPC_FilterValue, + 3, + 213, + 12, + 0, // Skip to: 102917 + /* 99632 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 99635 */ MCD_OPC_FilterValue, + 0, + 96, + 0, + 0, // Skip to: 99736 + /* 99640 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 99643 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 99660 + /* 99648 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 8, + 19, + 0, // Skip to: 104527 + /* 99655 */ MCD_OPC_Decode, + 149, + 40, + 177, + 3, // Opcode: STURHi + /* 99660 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 99677 + /* 99665 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 247, + 18, + 0, // Skip to: 104527 + /* 99672 */ MCD_OPC_Decode, + 241, + 39, + 177, + 3, // Opcode: STRHpost + /* 99677 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 99719 + /* 99682 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 99685 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 99702 + /* 99690 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 222, + 18, + 0, // Skip to: 104527 + /* 99697 */ MCD_OPC_Decode, + 243, + 39, + 169, + 4, // Opcode: STRHroW + /* 99702 */ MCD_OPC_FilterValue, + 3, + 212, + 18, + 0, // Skip to: 104527 + /* 99707 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 205, + 18, + 0, // Skip to: 104527 + /* 99714 */ MCD_OPC_Decode, + 244, + 39, + 170, + 4, // Opcode: STRHroX + /* 99719 */ MCD_OPC_FilterValue, + 3, + 195, + 18, + 0, // Skip to: 104527 + /* 99724 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 188, + 18, + 0, // Skip to: 104527 + /* 99731 */ MCD_OPC_Decode, + 242, + 39, + 177, + 3, // Opcode: STRHpre + /* 99736 */ MCD_OPC_FilterValue, + 1, + 96, + 0, + 0, // Skip to: 99837 + /* 99741 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 99744 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 99761 + /* 99749 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 163, + 18, + 0, // Skip to: 104527 + /* 99756 */ MCD_OPC_Decode, + 198, + 26, + 177, + 3, // Opcode: LDURHi + /* 99761 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 99778 + /* 99766 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 146, + 18, + 0, // Skip to: 104527 + /* 99773 */ MCD_OPC_Decode, + 175, + 25, + 177, + 3, // Opcode: LDRHpost + /* 99778 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 99820 + /* 99783 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 99786 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 99803 + /* 99791 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 121, + 18, + 0, // Skip to: 104527 + /* 99798 */ MCD_OPC_Decode, + 177, + 25, + 169, + 4, // Opcode: LDRHroW + /* 99803 */ MCD_OPC_FilterValue, + 3, + 111, + 18, + 0, // Skip to: 104527 + /* 99808 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 104, + 18, + 0, // Skip to: 104527 + /* 99815 */ MCD_OPC_Decode, + 178, + 25, + 170, + 4, // Opcode: LDRHroX + /* 99820 */ MCD_OPC_FilterValue, + 3, + 94, + 18, + 0, // Skip to: 104527 + /* 99825 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 87, + 18, + 0, // Skip to: 104527 + /* 99832 */ MCD_OPC_Decode, + 176, + 25, + 177, + 3, // Opcode: LDRHpre + /* 99837 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 99847 + /* 99842 */ MCD_OPC_Decode, + 245, + 39, + 187, + 3, // Opcode: STRHui + /* 99847 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 99857 + /* 99852 */ MCD_OPC_Decode, + 179, + 25, + 187, + 3, // Opcode: LDRHui + /* 99857 */ MCD_OPC_FilterValue, + 8, + 109, + 1, + 0, // Skip to: 100227 + /* 99862 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 99865 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 99887 + /* 99870 */ MCD_OPC_CheckPredicate, + 21, + 44, + 18, + 0, // Skip to: 104527 + /* 99875 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 37, + 18, + 0, // Skip to: 104527 + /* 99882 */ MCD_OPC_Decode, + 173, + 44, + 138, + 4, // Opcode: UQADDv1i8 + /* 99887 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 99909 + /* 99892 */ MCD_OPC_CheckPredicate, + 21, + 22, + 18, + 0, // Skip to: 104527 + /* 99897 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 15, + 18, + 0, // Skip to: 104527 + /* 99904 */ MCD_OPC_Decode, + 171, + 36, + 142, + 4, // Opcode: SQXTUNv1i8 + /* 99909 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 99931 + /* 99914 */ MCD_OPC_CheckPredicate, + 21, + 0, + 18, + 0, // Skip to: 104527 + /* 99919 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 249, + 17, + 0, // Skip to: 104527 + /* 99926 */ MCD_OPC_Decode, + 199, + 45, + 138, + 4, // Opcode: UQSUBv1i8 + /* 99931 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 99953 + /* 99936 */ MCD_OPC_CheckPredicate, + 21, + 234, + 17, + 0, // Skip to: 104527 + /* 99941 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 227, + 17, + 0, // Skip to: 104527 + /* 99948 */ MCD_OPC_Decode, + 197, + 46, + 139, + 4, // Opcode: USQADDv1i8 + /* 99953 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 99975 + /* 99958 */ MCD_OPC_CheckPredicate, + 21, + 212, + 17, + 0, // Skip to: 104527 + /* 99963 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 205, + 17, + 0, // Skip to: 104527 + /* 99970 */ MCD_OPC_Decode, + 215, + 45, + 142, + 4, // Opcode: UQXTNv1i8 + /* 99975 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 99997 + /* 99980 */ MCD_OPC_CheckPredicate, + 21, + 190, + 17, + 0, // Skip to: 104527 + /* 99985 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 183, + 17, + 0, // Skip to: 104527 + /* 99992 */ MCD_OPC_Decode, + 151, + 45, + 138, + 4, // Opcode: UQSHLv1i8 + /* 99997 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 100019 + /* 100002 */ MCD_OPC_CheckPredicate, + 21, + 168, + 17, + 0, // Skip to: 104527 + /* 100007 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 161, + 17, + 0, // Skip to: 104527 + /* 100014 */ MCD_OPC_Decode, + 236, + 44, + 138, + 4, // Opcode: UQRSHLv1i8 + /* 100019 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 100041 + /* 100024 */ MCD_OPC_CheckPredicate, + 21, + 146, + 17, + 0, // Skip to: 104527 + /* 100029 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 139, + 17, + 0, // Skip to: 104527 + /* 100036 */ MCD_OPC_Decode, + 178, + 34, + 143, + 4, // Opcode: SQNEGv1i8 + /* 100041 */ MCD_OPC_FilterValue, + 42, + 17, + 0, + 0, // Skip to: 100063 + /* 100046 */ MCD_OPC_CheckPredicate, + 21, + 124, + 17, + 0, // Skip to: 104527 + /* 100051 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 117, + 17, + 0, // Skip to: 104527 + /* 100058 */ MCD_OPC_Decode, + 253, + 14, + 225, + 3, // Opcode: FCVTNUv1i32 + /* 100063 */ MCD_OPC_FilterValue, + 46, + 17, + 0, + 0, // Skip to: 100085 + /* 100068 */ MCD_OPC_CheckPredicate, + 21, + 102, + 17, + 0, // Skip to: 104527 + /* 100073 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 95, + 17, + 0, // Skip to: 104527 + /* 100080 */ MCD_OPC_Decode, + 223, + 14, + 225, + 3, // Opcode: FCVTMUv1i32 + /* 100085 */ MCD_OPC_FilterValue, + 50, + 33, + 0, + 0, // Skip to: 100123 + /* 100090 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 100093 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 100108 + /* 100098 */ MCD_OPC_CheckPredicate, + 21, + 72, + 17, + 0, // Skip to: 104527 + /* 100103 */ MCD_OPC_Decode, + 185, + 14, + 225, + 3, // Opcode: FCVTAUv1i32 + /* 100108 */ MCD_OPC_FilterValue, + 48, + 62, + 17, + 0, // Skip to: 104527 + /* 100113 */ MCD_OPC_CheckPredicate, + 21, + 57, + 17, + 0, // Skip to: 104527 + /* 100118 */ MCD_OPC_Decode, + 159, + 16, + 213, + 2, // Opcode: FMAXNMPv2i32p + /* 100123 */ MCD_OPC_FilterValue, + 54, + 33, + 0, + 0, // Skip to: 100161 + /* 100128 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 100131 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 100146 + /* 100136 */ MCD_OPC_CheckPredicate, + 21, + 34, + 17, + 0, // Skip to: 104527 + /* 100141 */ MCD_OPC_Decode, + 211, + 42, + 225, + 3, // Opcode: UCVTFv1i32 + /* 100146 */ MCD_OPC_FilterValue, + 48, + 24, + 17, + 0, // Skip to: 104527 + /* 100151 */ MCD_OPC_CheckPredicate, + 21, + 19, + 17, + 0, // Skip to: 104527 + /* 100156 */ MCD_OPC_Decode, + 255, + 12, + 213, + 2, // Opcode: FADDPv2i32p + /* 100161 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 100183 + /* 100166 */ MCD_OPC_CheckPredicate, + 21, + 4, + 17, + 0, // Skip to: 104527 + /* 100171 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 253, + 16, + 0, // Skip to: 104527 + /* 100178 */ MCD_OPC_Decode, + 187, + 13, + 230, + 3, // Opcode: FCMGE32 + /* 100183 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 100205 + /* 100188 */ MCD_OPC_CheckPredicate, + 21, + 238, + 16, + 0, // Skip to: 104527 + /* 100193 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 231, + 16, + 0, // Skip to: 104527 + /* 100200 */ MCD_OPC_Decode, + 223, + 12, + 230, + 3, // Opcode: FACGE32 + /* 100205 */ MCD_OPC_FilterValue, + 62, + 221, + 16, + 0, // Skip to: 104527 + /* 100210 */ MCD_OPC_CheckPredicate, + 21, + 216, + 16, + 0, // Skip to: 104527 + /* 100215 */ MCD_OPC_CheckField, + 16, + 6, + 48, + 209, + 16, + 0, // Skip to: 104527 + /* 100222 */ MCD_OPC_Decode, + 188, + 16, + 213, + 2, // Opcode: FMAXPv2i32p + /* 100227 */ MCD_OPC_FilterValue, + 9, + 41, + 2, + 0, // Skip to: 100785 + /* 100232 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 100235 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 100257 + /* 100240 */ MCD_OPC_CheckPredicate, + 21, + 186, + 16, + 0, // Skip to: 104527 + /* 100245 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 179, + 16, + 0, // Skip to: 104527 + /* 100252 */ MCD_OPC_Decode, + 170, + 44, + 251, + 3, // Opcode: UQADDv1i16 + /* 100257 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 100279 + /* 100262 */ MCD_OPC_CheckPredicate, + 23, + 164, + 16, + 0, // Skip to: 104527 + /* 100267 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 157, + 16, + 0, // Skip to: 104527 + /* 100274 */ MCD_OPC_Decode, + 186, + 13, + 251, + 3, // Opcode: FCMGE16 + /* 100279 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 100301 + /* 100284 */ MCD_OPC_CheckPredicate, + 21, + 142, + 16, + 0, // Skip to: 104527 + /* 100289 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 135, + 16, + 0, // Skip to: 104527 + /* 100296 */ MCD_OPC_Decode, + 169, + 36, + 227, + 3, // Opcode: SQXTUNv1i16 + /* 100301 */ MCD_OPC_FilterValue, + 11, + 33, + 0, + 0, // Skip to: 100339 + /* 100306 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 100309 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 100324 + /* 100314 */ MCD_OPC_CheckPredicate, + 23, + 112, + 16, + 0, // Skip to: 104527 + /* 100319 */ MCD_OPC_Decode, + 222, + 12, + 251, + 3, // Opcode: FACGE16 + /* 100324 */ MCD_OPC_FilterValue, + 1, + 102, + 16, + 0, // Skip to: 104527 + /* 100329 */ MCD_OPC_CheckPredicate, + 21, + 97, + 16, + 0, // Skip to: 104527 + /* 100334 */ MCD_OPC_Decode, + 196, + 45, + 251, + 3, // Opcode: UQSUBv1i16 + /* 100339 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 100361 + /* 100344 */ MCD_OPC_CheckPredicate, + 21, + 82, + 16, + 0, // Skip to: 104527 + /* 100349 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 75, + 16, + 0, // Skip to: 104527 + /* 100356 */ MCD_OPC_Decode, + 194, + 46, + 140, + 4, // Opcode: USQADDv1i16 + /* 100361 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 100383 + /* 100366 */ MCD_OPC_CheckPredicate, + 21, + 60, + 16, + 0, // Skip to: 104527 + /* 100371 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 53, + 16, + 0, // Skip to: 104527 + /* 100378 */ MCD_OPC_Decode, + 213, + 45, + 227, + 3, // Opcode: UQXTNv1i16 + /* 100383 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 100405 + /* 100388 */ MCD_OPC_CheckPredicate, + 21, + 38, + 16, + 0, // Skip to: 104527 + /* 100393 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 31, + 16, + 0, // Skip to: 104527 + /* 100400 */ MCD_OPC_Decode, + 148, + 45, + 251, + 3, // Opcode: UQSHLv1i16 + /* 100405 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 100427 + /* 100410 */ MCD_OPC_CheckPredicate, + 21, + 16, + 16, + 0, // Skip to: 104527 + /* 100415 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 9, + 16, + 0, // Skip to: 104527 + /* 100422 */ MCD_OPC_Decode, + 233, + 44, + 251, + 3, // Opcode: UQRSHLv1i16 + /* 100427 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 100449 + /* 100432 */ MCD_OPC_CheckPredicate, + 21, + 250, + 15, + 0, // Skip to: 104527 + /* 100437 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 243, + 15, + 0, // Skip to: 104527 + /* 100444 */ MCD_OPC_Decode, + 167, + 15, + 213, + 2, // Opcode: FCVTXNv1i64 + /* 100449 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 100471 + /* 100454 */ MCD_OPC_CheckPredicate, + 21, + 228, + 15, + 0, // Skip to: 104527 + /* 100459 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 221, + 15, + 0, // Skip to: 104527 + /* 100466 */ MCD_OPC_Decode, + 175, + 34, + 246, + 3, // Opcode: SQNEGv1i16 + /* 100471 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 100493 + /* 100476 */ MCD_OPC_CheckPredicate, + 55, + 206, + 15, + 0, // Skip to: 104527 + /* 100481 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 199, + 15, + 0, // Skip to: 104527 + /* 100488 */ MCD_OPC_Decode, + 200, + 34, + 171, + 4, // Opcode: SQRDMLAHv1i16 + /* 100493 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 100515 + /* 100498 */ MCD_OPC_CheckPredicate, + 55, + 184, + 15, + 0, // Skip to: 104527 + /* 100503 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 177, + 15, + 0, // Skip to: 104527 + /* 100510 */ MCD_OPC_Decode, + 219, + 34, + 171, + 4, // Opcode: SQRDMLSHv1i16 + /* 100515 */ MCD_OPC_FilterValue, + 42, + 33, + 0, + 0, // Skip to: 100553 + /* 100520 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 100523 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 100538 + /* 100528 */ MCD_OPC_CheckPredicate, + 21, + 154, + 15, + 0, // Skip to: 104527 + /* 100533 */ MCD_OPC_Decode, + 254, + 14, + 156, + 2, // Opcode: FCVTNUv1i64 + /* 100538 */ MCD_OPC_FilterValue, + 57, + 144, + 15, + 0, // Skip to: 104527 + /* 100543 */ MCD_OPC_CheckPredicate, + 23, + 139, + 15, + 0, // Skip to: 104527 + /* 100548 */ MCD_OPC_Decode, + 252, + 14, + 246, + 3, // Opcode: FCVTNUv1f16 + /* 100553 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 100575 + /* 100558 */ MCD_OPC_CheckPredicate, + 21, + 124, + 15, + 0, // Skip to: 104527 + /* 100563 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 117, + 15, + 0, // Skip to: 104527 + /* 100570 */ MCD_OPC_Decode, + 236, + 34, + 251, + 3, // Opcode: SQRDMULHv1i16 + /* 100575 */ MCD_OPC_FilterValue, + 46, + 33, + 0, + 0, // Skip to: 100613 + /* 100580 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 100583 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 100598 + /* 100588 */ MCD_OPC_CheckPredicate, + 21, + 94, + 15, + 0, // Skip to: 104527 + /* 100593 */ MCD_OPC_Decode, + 224, + 14, + 156, + 2, // Opcode: FCVTMUv1i64 + /* 100598 */ MCD_OPC_FilterValue, + 57, + 84, + 15, + 0, // Skip to: 104527 + /* 100603 */ MCD_OPC_CheckPredicate, + 23, + 79, + 15, + 0, // Skip to: 104527 + /* 100608 */ MCD_OPC_Decode, + 222, + 14, + 246, + 3, // Opcode: FCVTMUv1f16 + /* 100613 */ MCD_OPC_FilterValue, + 50, + 48, + 0, + 0, // Skip to: 100666 + /* 100618 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 100621 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 100636 + /* 100626 */ MCD_OPC_CheckPredicate, + 21, + 56, + 15, + 0, // Skip to: 104527 + /* 100631 */ MCD_OPC_Decode, + 186, + 14, + 156, + 2, // Opcode: FCVTAUv1i64 + /* 100636 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 100651 + /* 100641 */ MCD_OPC_CheckPredicate, + 21, + 41, + 15, + 0, // Skip to: 104527 + /* 100646 */ MCD_OPC_Decode, + 160, + 16, + 161, + 2, // Opcode: FMAXNMPv2i64p + /* 100651 */ MCD_OPC_FilterValue, + 57, + 31, + 15, + 0, // Skip to: 104527 + /* 100656 */ MCD_OPC_CheckPredicate, + 23, + 26, + 15, + 0, // Skip to: 104527 + /* 100661 */ MCD_OPC_Decode, + 184, + 14, + 246, + 3, // Opcode: FCVTAUv1f16 + /* 100666 */ MCD_OPC_FilterValue, + 54, + 48, + 0, + 0, // Skip to: 100719 + /* 100671 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 100674 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 100689 + /* 100679 */ MCD_OPC_CheckPredicate, + 21, + 3, + 15, + 0, // Skip to: 104527 + /* 100684 */ MCD_OPC_Decode, + 212, + 42, + 156, + 2, // Opcode: UCVTFv1i64 + /* 100689 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 100704 + /* 100694 */ MCD_OPC_CheckPredicate, + 21, + 244, + 14, + 0, // Skip to: 104527 + /* 100699 */ MCD_OPC_Decode, + 128, + 13, + 161, + 2, // Opcode: FADDPv2i64p + /* 100704 */ MCD_OPC_FilterValue, + 57, + 234, + 14, + 0, // Skip to: 104527 + /* 100709 */ MCD_OPC_CheckPredicate, + 23, + 229, + 14, + 0, // Skip to: 104527 + /* 100714 */ MCD_OPC_Decode, + 210, + 42, + 246, + 3, // Opcode: UCVTFv1i16 + /* 100719 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 100741 + /* 100724 */ MCD_OPC_CheckPredicate, + 21, + 214, + 14, + 0, // Skip to: 104527 + /* 100729 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 207, + 14, + 0, // Skip to: 104527 + /* 100736 */ MCD_OPC_Decode, + 188, + 13, + 155, + 2, // Opcode: FCMGE64 + /* 100741 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 100763 + /* 100746 */ MCD_OPC_CheckPredicate, + 21, + 192, + 14, + 0, // Skip to: 104527 + /* 100751 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 185, + 14, + 0, // Skip to: 104527 + /* 100758 */ MCD_OPC_Decode, + 224, + 12, + 155, + 2, // Opcode: FACGE64 + /* 100763 */ MCD_OPC_FilterValue, + 62, + 175, + 14, + 0, // Skip to: 104527 + /* 100768 */ MCD_OPC_CheckPredicate, + 21, + 170, + 14, + 0, // Skip to: 104527 + /* 100773 */ MCD_OPC_CheckField, + 16, + 6, + 48, + 163, + 14, + 0, // Skip to: 104527 + /* 100780 */ MCD_OPC_Decode, + 189, + 16, + 161, + 2, // Opcode: FMAXPv2i64p + /* 100785 */ MCD_OPC_FilterValue, + 10, + 197, + 1, + 0, // Skip to: 101243 + /* 100790 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 100793 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 100815 + /* 100798 */ MCD_OPC_CheckPredicate, + 21, + 140, + 14, + 0, // Skip to: 104527 + /* 100803 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 133, + 14, + 0, // Skip to: 104527 + /* 100810 */ MCD_OPC_Decode, + 171, + 44, + 230, + 3, // Opcode: UQADDv1i32 + /* 100815 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 100837 + /* 100820 */ MCD_OPC_CheckPredicate, + 21, + 118, + 14, + 0, // Skip to: 104527 + /* 100825 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 111, + 14, + 0, // Skip to: 104527 + /* 100832 */ MCD_OPC_Decode, + 170, + 36, + 213, + 2, // Opcode: SQXTUNv1i32 + /* 100837 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 100859 + /* 100842 */ MCD_OPC_CheckPredicate, + 21, + 96, + 14, + 0, // Skip to: 104527 + /* 100847 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 89, + 14, + 0, // Skip to: 104527 + /* 100854 */ MCD_OPC_Decode, + 197, + 45, + 230, + 3, // Opcode: UQSUBv1i32 + /* 100859 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 100881 + /* 100864 */ MCD_OPC_CheckPredicate, + 21, + 74, + 14, + 0, // Skip to: 104527 + /* 100869 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 67, + 14, + 0, // Skip to: 104527 + /* 100876 */ MCD_OPC_Decode, + 195, + 46, + 141, + 4, // Opcode: USQADDv1i32 + /* 100881 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 100903 + /* 100886 */ MCD_OPC_CheckPredicate, + 21, + 52, + 14, + 0, // Skip to: 104527 + /* 100891 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 45, + 14, + 0, // Skip to: 104527 + /* 100898 */ MCD_OPC_Decode, + 214, + 45, + 213, + 2, // Opcode: UQXTNv1i32 + /* 100903 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 100925 + /* 100908 */ MCD_OPC_CheckPredicate, + 21, + 30, + 14, + 0, // Skip to: 104527 + /* 100913 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 23, + 14, + 0, // Skip to: 104527 + /* 100920 */ MCD_OPC_Decode, + 149, + 45, + 230, + 3, // Opcode: UQSHLv1i32 + /* 100925 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 100947 + /* 100930 */ MCD_OPC_CheckPredicate, + 21, + 8, + 14, + 0, // Skip to: 104527 + /* 100935 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 1, + 14, + 0, // Skip to: 104527 + /* 100942 */ MCD_OPC_Decode, + 234, + 44, + 230, + 3, // Opcode: UQRSHLv1i32 + /* 100947 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 100969 + /* 100952 */ MCD_OPC_CheckPredicate, + 21, + 242, + 13, + 0, // Skip to: 104527 + /* 100957 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 235, + 13, + 0, // Skip to: 104527 + /* 100964 */ MCD_OPC_Decode, + 176, + 34, + 225, + 3, // Opcode: SQNEGv1i32 + /* 100969 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 100991 + /* 100974 */ MCD_OPC_CheckPredicate, + 55, + 220, + 13, + 0, // Skip to: 104527 + /* 100979 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 213, + 13, + 0, // Skip to: 104527 + /* 100986 */ MCD_OPC_Decode, + 201, + 34, + 172, + 4, // Opcode: SQRDMLAHv1i32 + /* 100991 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 101013 + /* 100996 */ MCD_OPC_CheckPredicate, + 55, + 198, + 13, + 0, // Skip to: 104527 + /* 101001 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 191, + 13, + 0, // Skip to: 104527 + /* 101008 */ MCD_OPC_Decode, + 220, + 34, + 172, + 4, // Opcode: SQRDMLSHv1i32 + /* 101013 */ MCD_OPC_FilterValue, + 42, + 17, + 0, + 0, // Skip to: 101035 + /* 101018 */ MCD_OPC_CheckPredicate, + 21, + 176, + 13, + 0, // Skip to: 104527 + /* 101023 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 169, + 13, + 0, // Skip to: 104527 + /* 101030 */ MCD_OPC_Decode, + 157, + 15, + 225, + 3, // Opcode: FCVTPUv1i32 + /* 101035 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 101057 + /* 101040 */ MCD_OPC_CheckPredicate, + 21, + 154, + 13, + 0, // Skip to: 104527 + /* 101045 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 147, + 13, + 0, // Skip to: 104527 + /* 101052 */ MCD_OPC_Decode, + 238, + 34, + 230, + 3, // Opcode: SQRDMULHv1i32 + /* 101057 */ MCD_OPC_FilterValue, + 46, + 17, + 0, + 0, // Skip to: 101079 + /* 101062 */ MCD_OPC_CheckPredicate, + 21, + 132, + 13, + 0, // Skip to: 104527 + /* 101067 */ MCD_OPC_CheckField, + 16, + 6, + 33, + 125, + 13, + 0, // Skip to: 104527 + /* 101074 */ MCD_OPC_Decode, + 229, + 15, + 225, + 3, // Opcode: FCVTZUv1i32 + /* 101079 */ MCD_OPC_FilterValue, + 50, + 33, + 0, + 0, // Skip to: 101117 + /* 101084 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 101087 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 101102 + /* 101092 */ MCD_OPC_CheckPredicate, + 21, + 102, + 13, + 0, // Skip to: 104527 + /* 101097 */ MCD_OPC_Decode, + 196, + 13, + 225, + 3, // Opcode: FCMGEv1i32rz + /* 101102 */ MCD_OPC_FilterValue, + 48, + 92, + 13, + 0, // Skip to: 104527 + /* 101107 */ MCD_OPC_CheckPredicate, + 21, + 87, + 13, + 0, // Skip to: 104527 + /* 101112 */ MCD_OPC_Decode, + 221, + 16, + 213, + 2, // Opcode: FMINNMPv2i32p + /* 101117 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 101139 + /* 101122 */ MCD_OPC_CheckPredicate, + 21, + 72, + 13, + 0, // Skip to: 104527 + /* 101127 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 65, + 13, + 0, // Skip to: 104527 + /* 101134 */ MCD_OPC_Decode, + 201, + 12, + 230, + 3, // Opcode: FABD32 + /* 101139 */ MCD_OPC_FilterValue, + 54, + 33, + 0, + 0, // Skip to: 101177 + /* 101144 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 101147 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 101162 + /* 101152 */ MCD_OPC_CheckPredicate, + 21, + 42, + 13, + 0, // Skip to: 104527 + /* 101157 */ MCD_OPC_Decode, + 247, + 13, + 225, + 3, // Opcode: FCMLEv1i32rz + /* 101162 */ MCD_OPC_FilterValue, + 33, + 32, + 13, + 0, // Skip to: 104527 + /* 101167 */ MCD_OPC_CheckPredicate, + 22, + 27, + 13, + 0, // Skip to: 104527 + /* 101172 */ MCD_OPC_Decode, + 192, + 19, + 225, + 3, // Opcode: FRSQRTEv1i32 + /* 101177 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 101199 + /* 101182 */ MCD_OPC_CheckPredicate, + 21, + 12, + 13, + 0, // Skip to: 104527 + /* 101187 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 5, + 13, + 0, // Skip to: 104527 + /* 101194 */ MCD_OPC_Decode, + 209, + 13, + 230, + 3, // Opcode: FCMGT32 + /* 101199 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 101221 + /* 101204 */ MCD_OPC_CheckPredicate, + 21, + 246, + 12, + 0, // Skip to: 104527 + /* 101209 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 239, + 12, + 0, // Skip to: 104527 + /* 101216 */ MCD_OPC_Decode, + 234, + 12, + 230, + 3, // Opcode: FACGT32 + /* 101221 */ MCD_OPC_FilterValue, + 62, + 229, + 12, + 0, // Skip to: 104527 + /* 101226 */ MCD_OPC_CheckPredicate, + 21, + 224, + 12, + 0, // Skip to: 104527 + /* 101231 */ MCD_OPC_CheckField, + 16, + 6, + 48, + 217, + 12, + 0, // Skip to: 104527 + /* 101238 */ MCD_OPC_Decode, + 250, + 16, + 213, + 2, // Opcode: FMINPv2i32p + /* 101243 */ MCD_OPC_FilterValue, + 11, + 159, + 2, + 0, // Skip to: 101919 + /* 101248 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 101251 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 101273 + /* 101256 */ MCD_OPC_CheckPredicate, + 21, + 194, + 12, + 0, // Skip to: 104527 + /* 101261 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 187, + 12, + 0, // Skip to: 104527 + /* 101268 */ MCD_OPC_Decode, + 172, + 44, + 155, + 2, // Opcode: UQADDv1i64 + /* 101273 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 101295 + /* 101278 */ MCD_OPC_CheckPredicate, + 23, + 172, + 12, + 0, // Skip to: 104527 + /* 101283 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 165, + 12, + 0, // Skip to: 104527 + /* 101290 */ MCD_OPC_Decode, + 200, + 12, + 251, + 3, // Opcode: FABD16 + /* 101295 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 101317 + /* 101300 */ MCD_OPC_CheckPredicate, + 23, + 150, + 12, + 0, // Skip to: 104527 + /* 101305 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 143, + 12, + 0, // Skip to: 104527 + /* 101312 */ MCD_OPC_Decode, + 208, + 13, + 251, + 3, // Opcode: FCMGT16 + /* 101317 */ MCD_OPC_FilterValue, + 11, + 33, + 0, + 0, // Skip to: 101355 + /* 101322 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 101325 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 101340 + /* 101330 */ MCD_OPC_CheckPredicate, + 23, + 120, + 12, + 0, // Skip to: 104527 + /* 101335 */ MCD_OPC_Decode, + 233, + 12, + 251, + 3, // Opcode: FACGT16 + /* 101340 */ MCD_OPC_FilterValue, + 1, + 110, + 12, + 0, // Skip to: 104527 + /* 101345 */ MCD_OPC_CheckPredicate, + 21, + 105, + 12, + 0, // Skip to: 104527 + /* 101350 */ MCD_OPC_Decode, + 198, + 45, + 155, + 2, // Opcode: UQSUBv1i64 + /* 101355 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 101377 + /* 101360 */ MCD_OPC_CheckPredicate, + 21, + 90, + 12, + 0, // Skip to: 104527 + /* 101365 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 83, + 12, + 0, // Skip to: 104527 + /* 101372 */ MCD_OPC_Decode, + 159, + 10, + 155, + 2, // Opcode: CMHIv1i64 + /* 101377 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 101399 + /* 101382 */ MCD_OPC_CheckPredicate, + 21, + 68, + 12, + 0, // Skip to: 104527 + /* 101387 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 61, + 12, + 0, // Skip to: 104527 + /* 101394 */ MCD_OPC_Decode, + 196, + 46, + 166, + 2, // Opcode: USQADDv1i64 + /* 101399 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 101421 + /* 101404 */ MCD_OPC_CheckPredicate, + 21, + 46, + 12, + 0, // Skip to: 104527 + /* 101409 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 39, + 12, + 0, // Skip to: 104527 + /* 101416 */ MCD_OPC_Decode, + 167, + 10, + 155, + 2, // Opcode: CMHSv1i64 + /* 101421 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 101443 + /* 101426 */ MCD_OPC_CheckPredicate, + 21, + 24, + 12, + 0, // Skip to: 104527 + /* 101431 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 17, + 12, + 0, // Skip to: 104527 + /* 101438 */ MCD_OPC_Decode, + 168, + 46, + 155, + 2, // Opcode: USHLv1i64 + /* 101443 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 101465 + /* 101448 */ MCD_OPC_CheckPredicate, + 21, + 2, + 12, + 0, // Skip to: 104527 + /* 101453 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 251, + 11, + 0, // Skip to: 104527 + /* 101460 */ MCD_OPC_Decode, + 150, + 45, + 155, + 2, // Opcode: UQSHLv1i64 + /* 101465 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 101487 + /* 101470 */ MCD_OPC_CheckPredicate, + 21, + 236, + 11, + 0, // Skip to: 104527 + /* 101475 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 229, + 11, + 0, // Skip to: 104527 + /* 101482 */ MCD_OPC_Decode, + 243, + 45, + 155, + 2, // Opcode: URSHLv1i64 + /* 101487 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 101509 + /* 101492 */ MCD_OPC_CheckPredicate, + 21, + 214, + 11, + 0, // Skip to: 104527 + /* 101497 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 207, + 11, + 0, // Skip to: 104527 + /* 101504 */ MCD_OPC_Decode, + 235, + 44, + 155, + 2, // Opcode: UQRSHLv1i64 + /* 101509 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 101531 + /* 101514 */ MCD_OPC_CheckPredicate, + 21, + 192, + 11, + 0, // Skip to: 104527 + /* 101519 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 185, + 11, + 0, // Skip to: 104527 + /* 101526 */ MCD_OPC_Decode, + 177, + 34, + 156, + 2, // Opcode: SQNEGv1i64 + /* 101531 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 101553 + /* 101536 */ MCD_OPC_CheckPredicate, + 21, + 170, + 11, + 0, // Skip to: 104527 + /* 101541 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 163, + 11, + 0, // Skip to: 104527 + /* 101548 */ MCD_OPC_Decode, + 217, + 40, + 155, + 2, // Opcode: SUBv1i64 + /* 101553 */ MCD_OPC_FilterValue, + 34, + 17, + 0, + 0, // Skip to: 101575 + /* 101558 */ MCD_OPC_CheckPredicate, + 21, + 148, + 11, + 0, // Skip to: 104527 + /* 101563 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 141, + 11, + 0, // Skip to: 104527 + /* 101570 */ MCD_OPC_Decode, + 129, + 10, + 156, + 2, // Opcode: CMGEv1i64rz + /* 101575 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 101597 + /* 101580 */ MCD_OPC_CheckPredicate, + 21, + 126, + 11, + 0, // Skip to: 104527 + /* 101585 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 119, + 11, + 0, // Skip to: 104527 + /* 101592 */ MCD_OPC_Decode, + 240, + 9, + 155, + 2, // Opcode: CMEQv1i64 + /* 101597 */ MCD_OPC_FilterValue, + 38, + 17, + 0, + 0, // Skip to: 101619 + /* 101602 */ MCD_OPC_CheckPredicate, + 21, + 104, + 11, + 0, // Skip to: 104527 + /* 101607 */ MCD_OPC_CheckField, + 16, + 6, + 32, + 97, + 11, + 0, // Skip to: 104527 + /* 101614 */ MCD_OPC_Decode, + 181, + 10, + 156, + 2, // Opcode: CMLEv1i64rz + /* 101619 */ MCD_OPC_FilterValue, + 42, + 33, + 0, + 0, // Skip to: 101657 + /* 101624 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 101627 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 101642 + /* 101632 */ MCD_OPC_CheckPredicate, + 21, + 74, + 11, + 0, // Skip to: 104527 + /* 101637 */ MCD_OPC_Decode, + 158, + 15, + 156, + 2, // Opcode: FCVTPUv1i64 + /* 101642 */ MCD_OPC_FilterValue, + 57, + 64, + 11, + 0, // Skip to: 104527 + /* 101647 */ MCD_OPC_CheckPredicate, + 23, + 59, + 11, + 0, // Skip to: 104527 + /* 101652 */ MCD_OPC_Decode, + 156, + 15, + 246, + 3, // Opcode: FCVTPUv1f16 + /* 101657 */ MCD_OPC_FilterValue, + 46, + 48, + 0, + 0, // Skip to: 101710 + /* 101662 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 101665 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 101680 + /* 101670 */ MCD_OPC_CheckPredicate, + 21, + 36, + 11, + 0, // Skip to: 104527 + /* 101675 */ MCD_OPC_Decode, + 251, + 27, + 156, + 2, // Opcode: NEGv1i64 + /* 101680 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 101695 + /* 101685 */ MCD_OPC_CheckPredicate, + 21, + 21, + 11, + 0, // Skip to: 104527 + /* 101690 */ MCD_OPC_Decode, + 230, + 15, + 156, + 2, // Opcode: FCVTZUv1i64 + /* 101695 */ MCD_OPC_FilterValue, + 57, + 11, + 11, + 0, // Skip to: 104527 + /* 101700 */ MCD_OPC_CheckPredicate, + 23, + 6, + 11, + 0, // Skip to: 104527 + /* 101705 */ MCD_OPC_Decode, + 228, + 15, + 246, + 3, // Opcode: FCVTZUv1f16 + /* 101710 */ MCD_OPC_FilterValue, + 50, + 48, + 0, + 0, // Skip to: 101763 + /* 101715 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 101718 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 101733 + /* 101723 */ MCD_OPC_CheckPredicate, + 21, + 239, + 10, + 0, // Skip to: 104527 + /* 101728 */ MCD_OPC_Decode, + 197, + 13, + 156, + 2, // Opcode: FCMGEv1i64rz + /* 101733 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 101748 + /* 101738 */ MCD_OPC_CheckPredicate, + 21, + 224, + 10, + 0, // Skip to: 104527 + /* 101743 */ MCD_OPC_Decode, + 222, + 16, + 161, + 2, // Opcode: FMINNMPv2i64p + /* 101748 */ MCD_OPC_FilterValue, + 56, + 214, + 10, + 0, // Skip to: 104527 + /* 101753 */ MCD_OPC_CheckPredicate, + 23, + 209, + 10, + 0, // Skip to: 104527 + /* 101758 */ MCD_OPC_Decode, + 195, + 13, + 246, + 3, // Opcode: FCMGEv1i16rz + /* 101763 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 101785 + /* 101768 */ MCD_OPC_CheckPredicate, + 21, + 194, + 10, + 0, // Skip to: 104527 + /* 101773 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 187, + 10, + 0, // Skip to: 104527 + /* 101780 */ MCD_OPC_Decode, + 202, + 12, + 155, + 2, // Opcode: FABD64 + /* 101785 */ MCD_OPC_FilterValue, + 54, + 63, + 0, + 0, // Skip to: 101853 + /* 101790 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 101793 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 101808 + /* 101798 */ MCD_OPC_CheckPredicate, + 21, + 164, + 10, + 0, // Skip to: 104527 + /* 101803 */ MCD_OPC_Decode, + 248, + 13, + 156, + 2, // Opcode: FCMLEv1i64rz + /* 101808 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 101823 + /* 101813 */ MCD_OPC_CheckPredicate, + 22, + 149, + 10, + 0, // Skip to: 104527 + /* 101818 */ MCD_OPC_Decode, + 193, + 19, + 156, + 2, // Opcode: FRSQRTEv1i64 + /* 101823 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 101838 + /* 101828 */ MCD_OPC_CheckPredicate, + 23, + 134, + 10, + 0, // Skip to: 104527 + /* 101833 */ MCD_OPC_Decode, + 246, + 13, + 246, + 3, // Opcode: FCMLEv1i16rz + /* 101838 */ MCD_OPC_FilterValue, + 57, + 124, + 10, + 0, // Skip to: 104527 + /* 101843 */ MCD_OPC_CheckPredicate, + 54, + 119, + 10, + 0, // Skip to: 104527 + /* 101848 */ MCD_OPC_Decode, + 191, + 19, + 246, + 3, // Opcode: FRSQRTEv1f16 + /* 101853 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 101875 + /* 101858 */ MCD_OPC_CheckPredicate, + 21, + 104, + 10, + 0, // Skip to: 104527 + /* 101863 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 97, + 10, + 0, // Skip to: 104527 + /* 101870 */ MCD_OPC_Decode, + 210, + 13, + 155, + 2, // Opcode: FCMGT64 + /* 101875 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 101897 + /* 101880 */ MCD_OPC_CheckPredicate, + 21, + 82, + 10, + 0, // Skip to: 104527 + /* 101885 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 75, + 10, + 0, // Skip to: 104527 + /* 101892 */ MCD_OPC_Decode, + 235, + 12, + 155, + 2, // Opcode: FACGT64 + /* 101897 */ MCD_OPC_FilterValue, + 62, + 65, + 10, + 0, // Skip to: 104527 + /* 101902 */ MCD_OPC_CheckPredicate, + 21, + 60, + 10, + 0, // Skip to: 104527 + /* 101907 */ MCD_OPC_CheckField, + 16, + 6, + 48, + 53, + 10, + 0, // Skip to: 104527 + /* 101914 */ MCD_OPC_Decode, + 251, + 16, + 161, + 2, // Opcode: FMINPv2i64p + /* 101919 */ MCD_OPC_FilterValue, + 12, + 98, + 2, + 0, // Skip to: 102534 + /* 101924 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 101927 */ MCD_OPC_FilterValue, + 6, + 84, + 0, + 0, // Skip to: 102016 + /* 101932 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 101935 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 101994 + /* 101940 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 101943 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 101972 + /* 101948 */ MCD_OPC_CheckPredicate, + 21, + 14, + 10, + 0, // Skip to: 104527 + /* 101953 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 7, + 10, + 0, // Skip to: 104527 + /* 101960 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 0, + 10, + 0, // Skip to: 104527 + /* 101967 */ MCD_OPC_Decode, + 177, + 35, + 156, + 4, // Opcode: SQSHLUb + /* 101972 */ MCD_OPC_FilterValue, + 1, + 246, + 9, + 0, // Skip to: 104527 + /* 101977 */ MCD_OPC_CheckPredicate, + 21, + 241, + 9, + 0, // Skip to: 104527 + /* 101982 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 234, + 9, + 0, // Skip to: 104527 + /* 101989 */ MCD_OPC_Decode, + 179, + 35, + 157, + 4, // Opcode: SQSHLUh + /* 101994 */ MCD_OPC_FilterValue, + 1, + 224, + 9, + 0, // Skip to: 104527 + /* 101999 */ MCD_OPC_CheckPredicate, + 21, + 219, + 9, + 0, // Skip to: 104527 + /* 102004 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 212, + 9, + 0, // Skip to: 104527 + /* 102011 */ MCD_OPC_Decode, + 180, + 35, + 158, + 4, // Opcode: SQSHLUs + /* 102016 */ MCD_OPC_FilterValue, + 7, + 84, + 0, + 0, // Skip to: 102105 + /* 102021 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 102024 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 102083 + /* 102029 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 102032 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 102061 + /* 102037 */ MCD_OPC_CheckPredicate, + 21, + 181, + 9, + 0, // Skip to: 104527 + /* 102042 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 174, + 9, + 0, // Skip to: 104527 + /* 102049 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 167, + 9, + 0, // Skip to: 104527 + /* 102056 */ MCD_OPC_Decode, + 142, + 45, + 156, + 4, // Opcode: UQSHLb + /* 102061 */ MCD_OPC_FilterValue, + 1, + 157, + 9, + 0, // Skip to: 104527 + /* 102066 */ MCD_OPC_CheckPredicate, + 21, + 152, + 9, + 0, // Skip to: 104527 + /* 102071 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 145, + 9, + 0, // Skip to: 104527 + /* 102078 */ MCD_OPC_Decode, + 144, + 45, + 157, + 4, // Opcode: UQSHLh + /* 102083 */ MCD_OPC_FilterValue, + 1, + 135, + 9, + 0, // Skip to: 104527 + /* 102088 */ MCD_OPC_CheckPredicate, + 21, + 130, + 9, + 0, // Skip to: 104527 + /* 102093 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 123, + 9, + 0, // Skip to: 104527 + /* 102100 */ MCD_OPC_Decode, + 145, + 45, + 158, + 4, // Opcode: UQSHLs + /* 102105 */ MCD_OPC_FilterValue, + 8, + 139, + 0, + 0, // Skip to: 102249 + /* 102110 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 102113 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 102181 + /* 102118 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 102121 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 102166 + /* 102126 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 102129 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 102151 + /* 102134 */ MCD_OPC_CheckPredicate, + 21, + 84, + 9, + 0, // Skip to: 104527 + /* 102139 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 77, + 9, + 0, // Skip to: 104527 + /* 102146 */ MCD_OPC_Decode, + 239, + 35, + 160, + 4, // Opcode: SQSHRUNb + /* 102151 */ MCD_OPC_FilterValue, + 1, + 67, + 9, + 0, // Skip to: 104527 + /* 102156 */ MCD_OPC_CheckPredicate, + 21, + 62, + 9, + 0, // Skip to: 104527 + /* 102161 */ MCD_OPC_Decode, + 240, + 35, + 161, + 4, // Opcode: SQSHRUNh + /* 102166 */ MCD_OPC_FilterValue, + 1, + 52, + 9, + 0, // Skip to: 104527 + /* 102171 */ MCD_OPC_CheckPredicate, + 21, + 47, + 9, + 0, // Skip to: 104527 + /* 102176 */ MCD_OPC_Decode, + 241, + 35, + 162, + 4, // Opcode: SQSHRUNs + /* 102181 */ MCD_OPC_FilterValue, + 3, + 37, + 9, + 0, // Skip to: 104527 + /* 102186 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 102189 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 102234 + /* 102194 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 102197 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 102219 + /* 102202 */ MCD_OPC_CheckPredicate, + 21, + 16, + 9, + 0, // Skip to: 104527 + /* 102207 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 9, + 9, + 0, // Skip to: 104527 + /* 102214 */ MCD_OPC_Decode, + 160, + 35, + 160, + 4, // Opcode: SQRSHRUNb + /* 102219 */ MCD_OPC_FilterValue, + 1, + 255, + 8, + 0, // Skip to: 104527 + /* 102224 */ MCD_OPC_CheckPredicate, + 21, + 250, + 8, + 0, // Skip to: 104527 + /* 102229 */ MCD_OPC_Decode, + 161, + 35, + 161, + 4, // Opcode: SQRSHRUNh + /* 102234 */ MCD_OPC_FilterValue, + 1, + 240, + 8, + 0, // Skip to: 104527 + /* 102239 */ MCD_OPC_CheckPredicate, + 21, + 235, + 8, + 0, // Skip to: 104527 + /* 102244 */ MCD_OPC_Decode, + 162, + 35, + 162, + 4, // Opcode: SQRSHRUNs + /* 102249 */ MCD_OPC_FilterValue, + 9, + 162, + 0, + 0, // Skip to: 102416 + /* 102254 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 102257 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 102272 + /* 102262 */ MCD_OPC_CheckPredicate, + 23, + 212, + 8, + 0, // Skip to: 104527 + /* 102267 */ MCD_OPC_Decode, + 249, + 17, + 159, + 4, // Opcode: FMULXv1i16_indexed + /* 102272 */ MCD_OPC_FilterValue, + 1, + 202, + 8, + 0, // Skip to: 104527 + /* 102277 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 102280 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 102348 + /* 102285 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 102288 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 102333 + /* 102293 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 102296 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 102318 + /* 102301 */ MCD_OPC_CheckPredicate, + 21, + 173, + 8, + 0, // Skip to: 104527 + /* 102306 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 166, + 8, + 0, // Skip to: 104527 + /* 102313 */ MCD_OPC_Decode, + 170, + 45, + 160, + 4, // Opcode: UQSHRNb + /* 102318 */ MCD_OPC_FilterValue, + 1, + 156, + 8, + 0, // Skip to: 104527 + /* 102323 */ MCD_OPC_CheckPredicate, + 21, + 151, + 8, + 0, // Skip to: 104527 + /* 102328 */ MCD_OPC_Decode, + 171, + 45, + 161, + 4, // Opcode: UQSHRNh + /* 102333 */ MCD_OPC_FilterValue, + 1, + 141, + 8, + 0, // Skip to: 104527 + /* 102338 */ MCD_OPC_CheckPredicate, + 21, + 136, + 8, + 0, // Skip to: 104527 + /* 102343 */ MCD_OPC_Decode, + 172, + 45, + 162, + 4, // Opcode: UQSHRNs + /* 102348 */ MCD_OPC_FilterValue, + 1, + 126, + 8, + 0, // Skip to: 104527 + /* 102353 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 102356 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 102401 + /* 102361 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 102364 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 102386 + /* 102369 */ MCD_OPC_CheckPredicate, + 21, + 105, + 8, + 0, // Skip to: 104527 + /* 102374 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 98, + 8, + 0, // Skip to: 104527 + /* 102381 */ MCD_OPC_Decode, + 249, + 44, + 160, + 4, // Opcode: UQRSHRNb + /* 102386 */ MCD_OPC_FilterValue, + 1, + 88, + 8, + 0, // Skip to: 104527 + /* 102391 */ MCD_OPC_CheckPredicate, + 21, + 83, + 8, + 0, // Skip to: 104527 + /* 102396 */ MCD_OPC_Decode, + 250, + 44, + 161, + 4, // Opcode: UQRSHRNh + /* 102401 */ MCD_OPC_FilterValue, + 1, + 73, + 8, + 0, // Skip to: 104527 + /* 102406 */ MCD_OPC_CheckPredicate, + 21, + 68, + 8, + 0, // Skip to: 104527 + /* 102411 */ MCD_OPC_Decode, + 251, + 44, + 162, + 4, // Opcode: UQRSHRNs + /* 102416 */ MCD_OPC_FilterValue, + 14, + 54, + 0, + 0, // Skip to: 102475 + /* 102421 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 102424 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 102453 + /* 102429 */ MCD_OPC_CheckPredicate, + 23, + 45, + 8, + 0, // Skip to: 104527 + /* 102434 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 38, + 8, + 0, // Skip to: 104527 + /* 102441 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 31, + 8, + 0, // Skip to: 104527 + /* 102448 */ MCD_OPC_Decode, + 208, + 42, + 167, + 4, // Opcode: UCVTFh + /* 102453 */ MCD_OPC_FilterValue, + 1, + 21, + 8, + 0, // Skip to: 104527 + /* 102458 */ MCD_OPC_CheckPredicate, + 21, + 16, + 8, + 0, // Skip to: 104527 + /* 102463 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 9, + 8, + 0, // Skip to: 104527 + /* 102470 */ MCD_OPC_Decode, + 209, + 42, + 168, + 4, // Opcode: UCVTFs + /* 102475 */ MCD_OPC_FilterValue, + 15, + 255, + 7, + 0, // Skip to: 104527 + /* 102480 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 102483 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 102512 + /* 102488 */ MCD_OPC_CheckPredicate, + 23, + 242, + 7, + 0, // Skip to: 104527 + /* 102493 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 235, + 7, + 0, // Skip to: 104527 + /* 102500 */ MCD_OPC_CheckField, + 10, + 2, + 3, + 228, + 7, + 0, // Skip to: 104527 + /* 102507 */ MCD_OPC_Decode, + 226, + 15, + 167, + 4, // Opcode: FCVTZUh + /* 102512 */ MCD_OPC_FilterValue, + 1, + 218, + 7, + 0, // Skip to: 104527 + /* 102517 */ MCD_OPC_CheckPredicate, + 21, + 213, + 7, + 0, // Skip to: 104527 + /* 102522 */ MCD_OPC_CheckField, + 10, + 2, + 3, + 206, + 7, + 0, // Skip to: 104527 + /* 102529 */ MCD_OPC_Decode, + 227, + 15, + 168, + 4, // Opcode: FCVTZUs + /* 102534 */ MCD_OPC_FilterValue, + 13, + 12, + 1, + 0, // Skip to: 102807 + /* 102539 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 102542 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 102564 + /* 102547 */ MCD_OPC_CheckPredicate, + 21, + 183, + 7, + 0, // Skip to: 104527 + /* 102552 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 176, + 7, + 0, // Skip to: 104527 + /* 102559 */ MCD_OPC_Decode, + 175, + 46, + 148, + 4, // Opcode: USHRd + /* 102564 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 102586 + /* 102569 */ MCD_OPC_CheckPredicate, + 21, + 161, + 7, + 0, // Skip to: 104527 + /* 102574 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 154, + 7, + 0, // Skip to: 104527 + /* 102581 */ MCD_OPC_Decode, + 208, + 46, + 150, + 4, // Opcode: USRAd + /* 102586 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 102608 + /* 102591 */ MCD_OPC_CheckPredicate, + 21, + 139, + 7, + 0, // Skip to: 104527 + /* 102596 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 132, + 7, + 0, // Skip to: 104527 + /* 102603 */ MCD_OPC_Decode, + 254, + 45, + 148, + 4, // Opcode: URSHRd + /* 102608 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 102630 + /* 102613 */ MCD_OPC_CheckPredicate, + 21, + 117, + 7, + 0, // Skip to: 104527 + /* 102618 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 110, + 7, + 0, // Skip to: 104527 + /* 102625 */ MCD_OPC_Decode, + 141, + 46, + 150, + 4, // Opcode: URSRAd + /* 102630 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 102652 + /* 102635 */ MCD_OPC_CheckPredicate, + 21, + 95, + 7, + 0, // Skip to: 104527 + /* 102640 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 88, + 7, + 0, // Skip to: 104527 + /* 102647 */ MCD_OPC_Decode, + 191, + 36, + 150, + 4, // Opcode: SRId + /* 102652 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 102674 + /* 102657 */ MCD_OPC_CheckPredicate, + 21, + 73, + 7, + 0, // Skip to: 104527 + /* 102662 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 66, + 7, + 0, // Skip to: 104527 + /* 102669 */ MCD_OPC_Decode, + 196, + 31, + 173, + 4, // Opcode: SLId + /* 102674 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 102696 + /* 102679 */ MCD_OPC_CheckPredicate, + 21, + 51, + 7, + 0, // Skip to: 104527 + /* 102684 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 44, + 7, + 0, // Skip to: 104527 + /* 102691 */ MCD_OPC_Decode, + 178, + 35, + 155, + 4, // Opcode: SQSHLUd + /* 102696 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 102718 + /* 102701 */ MCD_OPC_CheckPredicate, + 21, + 29, + 7, + 0, // Skip to: 104527 + /* 102706 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 22, + 7, + 0, // Skip to: 104527 + /* 102713 */ MCD_OPC_Decode, + 143, + 45, + 155, + 4, // Opcode: UQSHLd + /* 102718 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 102740 + /* 102723 */ MCD_OPC_CheckPredicate, + 28, + 7, + 7, + 0, // Skip to: 104527 + /* 102728 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 0, + 7, + 0, // Skip to: 104527 + /* 102735 */ MCD_OPC_Decode, + 198, + 34, + 149, + 4, // Opcode: SQRDMLAHi16_indexed + /* 102740 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 102762 + /* 102745 */ MCD_OPC_CheckPredicate, + 21, + 241, + 6, + 0, // Skip to: 104527 + /* 102750 */ MCD_OPC_CheckField, + 10, + 2, + 1, + 234, + 6, + 0, // Skip to: 104527 + /* 102757 */ MCD_OPC_Decode, + 207, + 42, + 148, + 4, // Opcode: UCVTFd + /* 102762 */ MCD_OPC_FilterValue, + 15, + 224, + 6, + 0, // Skip to: 104527 + /* 102767 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 102770 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 102785 + /* 102775 */ MCD_OPC_CheckPredicate, + 28, + 211, + 6, + 0, // Skip to: 104527 + /* 102780 */ MCD_OPC_Decode, + 217, + 34, + 149, + 4, // Opcode: SQRDMLSHi16_indexed + /* 102785 */ MCD_OPC_FilterValue, + 1, + 201, + 6, + 0, // Skip to: 104527 + /* 102790 */ MCD_OPC_CheckPredicate, + 21, + 196, + 6, + 0, // Skip to: 104527 + /* 102795 */ MCD_OPC_CheckField, + 11, + 1, + 1, + 189, + 6, + 0, // Skip to: 104527 + /* 102802 */ MCD_OPC_Decode, + 225, + 15, + 148, + 4, // Opcode: FCVTZUd + /* 102807 */ MCD_OPC_FilterValue, + 14, + 69, + 0, + 0, // Skip to: 102881 + /* 102812 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 102815 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 102837 + /* 102820 */ MCD_OPC_CheckPredicate, + 21, + 166, + 6, + 0, // Skip to: 104527 + /* 102825 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 159, + 6, + 0, // Skip to: 104527 + /* 102832 */ MCD_OPC_Decode, + 250, + 17, + 163, + 4, // Opcode: FMULXv1i32_indexed + /* 102837 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 102859 + /* 102842 */ MCD_OPC_CheckPredicate, + 28, + 144, + 6, + 0, // Skip to: 104527 + /* 102847 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 137, + 6, + 0, // Skip to: 104527 + /* 102854 */ MCD_OPC_Decode, + 199, + 34, + 151, + 4, // Opcode: SQRDMLAHi32_indexed + /* 102859 */ MCD_OPC_FilterValue, + 15, + 127, + 6, + 0, // Skip to: 104527 + /* 102864 */ MCD_OPC_CheckPredicate, + 28, + 122, + 6, + 0, // Skip to: 104527 + /* 102869 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 115, + 6, + 0, // Skip to: 104527 + /* 102876 */ MCD_OPC_Decode, + 218, + 34, + 151, + 4, // Opcode: SQRDMLSHi32_indexed + /* 102881 */ MCD_OPC_FilterValue, + 15, + 105, + 6, + 0, // Skip to: 104527 + /* 102886 */ MCD_OPC_CheckPredicate, + 21, + 100, + 6, + 0, // Skip to: 104527 + /* 102891 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 93, + 6, + 0, // Skip to: 104527 + /* 102898 */ MCD_OPC_CheckField, + 12, + 4, + 9, + 86, + 6, + 0, // Skip to: 104527 + /* 102905 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 79, + 6, + 0, // Skip to: 104527 + /* 102912 */ MCD_OPC_Decode, + 251, + 17, + 164, + 4, // Opcode: FMULXv1i64_indexed + /* 102917 */ MCD_OPC_FilterValue, + 4, + 121, + 4, + 0, // Skip to: 104067 + /* 102922 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 102925 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 102935 + /* 102930 */ MCD_OPC_Decode, + 180, + 25, + 174, + 4, // Opcode: LDRQl + /* 102935 */ MCD_OPC_FilterValue, + 2, + 51, + 6, + 0, // Skip to: 104527 + /* 102940 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 102943 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 102958 + /* 102948 */ MCD_OPC_CheckPredicate, + 49, + 38, + 6, + 0, // Skip to: 104527 + /* 102953 */ MCD_OPC_Decode, + 204, + 30, + 175, + 4, // Opcode: SCVTFSXSri + /* 102958 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 102973 + /* 102963 */ MCD_OPC_CheckPredicate, + 49, + 23, + 6, + 0, // Skip to: 104527 + /* 102968 */ MCD_OPC_Decode, + 193, + 42, + 175, + 4, // Opcode: UCVTFSXSri + /* 102973 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 102988 + /* 102978 */ MCD_OPC_CheckPredicate, + 49, + 8, + 6, + 0, // Skip to: 104527 + /* 102983 */ MCD_OPC_Decode, + 176, + 15, + 176, + 4, // Opcode: FCVTZSSXSri + /* 102988 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 103003 + /* 102993 */ MCD_OPC_CheckPredicate, + 49, + 249, + 5, + 0, // Skip to: 104527 + /* 102998 */ MCD_OPC_Decode, + 211, + 15, + 176, + 4, // Opcode: FCVTZUSXSri + /* 103003 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 103025 + /* 103008 */ MCD_OPC_CheckPredicate, + 49, + 234, + 5, + 0, // Skip to: 104527 + /* 103013 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 227, + 5, + 0, // Skip to: 104527 + /* 103020 */ MCD_OPC_Decode, + 235, + 14, + 177, + 4, // Opcode: FCVTNSUXSr + /* 103025 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 103047 + /* 103030 */ MCD_OPC_CheckPredicate, + 49, + 212, + 5, + 0, // Skip to: 104527 + /* 103035 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 205, + 5, + 0, // Skip to: 104527 + /* 103042 */ MCD_OPC_Decode, + 251, + 14, + 177, + 4, // Opcode: FCVTNUUXSr + /* 103047 */ MCD_OPC_FilterValue, + 34, + 17, + 0, + 0, // Skip to: 103069 + /* 103052 */ MCD_OPC_CheckPredicate, + 49, + 190, + 5, + 0, // Skip to: 104527 + /* 103057 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 183, + 5, + 0, // Skip to: 104527 + /* 103064 */ MCD_OPC_Decode, + 210, + 30, + 178, + 4, // Opcode: SCVTFUXSri + /* 103069 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 103091 + /* 103074 */ MCD_OPC_CheckPredicate, + 49, + 168, + 5, + 0, // Skip to: 104527 + /* 103079 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 161, + 5, + 0, // Skip to: 104527 + /* 103086 */ MCD_OPC_Decode, + 199, + 42, + 178, + 4, // Opcode: UCVTFUXSri + /* 103091 */ MCD_OPC_FilterValue, + 36, + 17, + 0, + 0, // Skip to: 103113 + /* 103096 */ MCD_OPC_CheckPredicate, + 49, + 146, + 5, + 0, // Skip to: 104527 + /* 103101 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 139, + 5, + 0, // Skip to: 104527 + /* 103108 */ MCD_OPC_Decode, + 169, + 14, + 177, + 4, // Opcode: FCVTASUXSr + /* 103113 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 103135 + /* 103118 */ MCD_OPC_CheckPredicate, + 49, + 124, + 5, + 0, // Skip to: 104527 + /* 103123 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 117, + 5, + 0, // Skip to: 104527 + /* 103130 */ MCD_OPC_Decode, + 183, + 14, + 177, + 4, // Opcode: FCVTAUUXSr + /* 103135 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 103157 + /* 103140 */ MCD_OPC_CheckPredicate, + 49, + 102, + 5, + 0, // Skip to: 104527 + /* 103145 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 95, + 5, + 0, // Skip to: 104527 + /* 103152 */ MCD_OPC_Decode, + 141, + 15, + 177, + 4, // Opcode: FCVTPSUXSr + /* 103157 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 103179 + /* 103162 */ MCD_OPC_CheckPredicate, + 49, + 80, + 5, + 0, // Skip to: 104527 + /* 103167 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 73, + 5, + 0, // Skip to: 104527 + /* 103174 */ MCD_OPC_Decode, + 155, + 15, + 177, + 4, // Opcode: FCVTPUUXSr + /* 103179 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 103201 + /* 103184 */ MCD_OPC_CheckPredicate, + 49, + 58, + 5, + 0, // Skip to: 104527 + /* 103189 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 51, + 5, + 0, // Skip to: 104527 + /* 103196 */ MCD_OPC_Decode, + 207, + 14, + 177, + 4, // Opcode: FCVTMSUXSr + /* 103201 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 103223 + /* 103206 */ MCD_OPC_CheckPredicate, + 49, + 36, + 5, + 0, // Skip to: 104527 + /* 103211 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 29, + 5, + 0, // Skip to: 104527 + /* 103218 */ MCD_OPC_Decode, + 221, + 14, + 177, + 4, // Opcode: FCVTMUUXSr + /* 103223 */ MCD_OPC_FilterValue, + 56, + 17, + 0, + 0, // Skip to: 103245 + /* 103228 */ MCD_OPC_CheckPredicate, + 49, + 14, + 5, + 0, // Skip to: 104527 + /* 103233 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 7, + 5, + 0, // Skip to: 104527 + /* 103240 */ MCD_OPC_Decode, + 182, + 15, + 177, + 4, // Opcode: FCVTZSUXSr + /* 103245 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 103267 + /* 103250 */ MCD_OPC_CheckPredicate, + 49, + 248, + 4, + 0, // Skip to: 104527 + /* 103255 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 241, + 4, + 0, // Skip to: 104527 + /* 103262 */ MCD_OPC_Decode, + 217, + 15, + 177, + 4, // Opcode: FCVTZUUXSr + /* 103267 */ MCD_OPC_FilterValue, + 66, + 10, + 0, + 0, // Skip to: 103282 + /* 103272 */ MCD_OPC_CheckPredicate, + 49, + 226, + 4, + 0, // Skip to: 104527 + /* 103277 */ MCD_OPC_Decode, + 202, + 30, + 179, + 4, // Opcode: SCVTFSXDri + /* 103282 */ MCD_OPC_FilterValue, + 67, + 10, + 0, + 0, // Skip to: 103297 + /* 103287 */ MCD_OPC_CheckPredicate, + 49, + 211, + 4, + 0, // Skip to: 104527 + /* 103292 */ MCD_OPC_Decode, + 191, + 42, + 179, + 4, // Opcode: UCVTFSXDri + /* 103297 */ MCD_OPC_FilterValue, + 88, + 10, + 0, + 0, // Skip to: 103312 + /* 103302 */ MCD_OPC_CheckPredicate, + 49, + 196, + 4, + 0, // Skip to: 104527 + /* 103307 */ MCD_OPC_Decode, + 174, + 15, + 180, + 4, // Opcode: FCVTZSSXDri + /* 103312 */ MCD_OPC_FilterValue, + 89, + 10, + 0, + 0, // Skip to: 103327 + /* 103317 */ MCD_OPC_CheckPredicate, + 49, + 181, + 4, + 0, // Skip to: 104527 + /* 103322 */ MCD_OPC_Decode, + 209, + 15, + 180, + 4, // Opcode: FCVTZUSXDri + /* 103327 */ MCD_OPC_FilterValue, + 96, + 17, + 0, + 0, // Skip to: 103349 + /* 103332 */ MCD_OPC_CheckPredicate, + 49, + 166, + 4, + 0, // Skip to: 104527 + /* 103337 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 159, + 4, + 0, // Skip to: 104527 + /* 103344 */ MCD_OPC_Decode, + 233, + 14, + 181, + 4, // Opcode: FCVTNSUXDr + /* 103349 */ MCD_OPC_FilterValue, + 97, + 17, + 0, + 0, // Skip to: 103371 + /* 103354 */ MCD_OPC_CheckPredicate, + 49, + 144, + 4, + 0, // Skip to: 104527 + /* 103359 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 137, + 4, + 0, // Skip to: 104527 + /* 103366 */ MCD_OPC_Decode, + 249, + 14, + 181, + 4, // Opcode: FCVTNUUXDr + /* 103371 */ MCD_OPC_FilterValue, + 98, + 17, + 0, + 0, // Skip to: 103393 + /* 103376 */ MCD_OPC_CheckPredicate, + 49, + 122, + 4, + 0, // Skip to: 104527 + /* 103381 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 115, + 4, + 0, // Skip to: 104527 + /* 103388 */ MCD_OPC_Decode, + 208, + 30, + 182, + 4, // Opcode: SCVTFUXDri + /* 103393 */ MCD_OPC_FilterValue, + 99, + 17, + 0, + 0, // Skip to: 103415 + /* 103398 */ MCD_OPC_CheckPredicate, + 49, + 100, + 4, + 0, // Skip to: 104527 + /* 103403 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 93, + 4, + 0, // Skip to: 104527 + /* 103410 */ MCD_OPC_Decode, + 197, + 42, + 182, + 4, // Opcode: UCVTFUXDri + /* 103415 */ MCD_OPC_FilterValue, + 100, + 17, + 0, + 0, // Skip to: 103437 + /* 103420 */ MCD_OPC_CheckPredicate, + 49, + 78, + 4, + 0, // Skip to: 104527 + /* 103425 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 71, + 4, + 0, // Skip to: 104527 + /* 103432 */ MCD_OPC_Decode, + 167, + 14, + 181, + 4, // Opcode: FCVTASUXDr + /* 103437 */ MCD_OPC_FilterValue, + 101, + 17, + 0, + 0, // Skip to: 103459 + /* 103442 */ MCD_OPC_CheckPredicate, + 49, + 56, + 4, + 0, // Skip to: 104527 + /* 103447 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 49, + 4, + 0, // Skip to: 104527 + /* 103454 */ MCD_OPC_Decode, + 181, + 14, + 181, + 4, // Opcode: FCVTAUUXDr + /* 103459 */ MCD_OPC_FilterValue, + 102, + 17, + 0, + 0, // Skip to: 103481 + /* 103464 */ MCD_OPC_CheckPredicate, + 49, + 34, + 4, + 0, // Skip to: 104527 + /* 103469 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 27, + 4, + 0, // Skip to: 104527 + /* 103476 */ MCD_OPC_Decode, + 214, + 17, + 181, + 4, // Opcode: FMOVDXr + /* 103481 */ MCD_OPC_FilterValue, + 103, + 17, + 0, + 0, // Skip to: 103503 + /* 103486 */ MCD_OPC_CheckPredicate, + 49, + 12, + 4, + 0, // Skip to: 104527 + /* 103491 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 5, + 4, + 0, // Skip to: 104527 + /* 103498 */ MCD_OPC_Decode, + 227, + 17, + 182, + 4, // Opcode: FMOVXDr + /* 103503 */ MCD_OPC_FilterValue, + 104, + 17, + 0, + 0, // Skip to: 103525 + /* 103508 */ MCD_OPC_CheckPredicate, + 49, + 246, + 3, + 0, // Skip to: 104527 + /* 103513 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 239, + 3, + 0, // Skip to: 104527 + /* 103520 */ MCD_OPC_Decode, + 139, + 15, + 181, + 4, // Opcode: FCVTPSUXDr + /* 103525 */ MCD_OPC_FilterValue, + 105, + 17, + 0, + 0, // Skip to: 103547 + /* 103530 */ MCD_OPC_CheckPredicate, + 49, + 224, + 3, + 0, // Skip to: 104527 + /* 103535 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 217, + 3, + 0, // Skip to: 104527 + /* 103542 */ MCD_OPC_Decode, + 153, + 15, + 181, + 4, // Opcode: FCVTPUUXDr + /* 103547 */ MCD_OPC_FilterValue, + 112, + 17, + 0, + 0, // Skip to: 103569 + /* 103552 */ MCD_OPC_CheckPredicate, + 49, + 202, + 3, + 0, // Skip to: 104527 + /* 103557 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 195, + 3, + 0, // Skip to: 104527 + /* 103564 */ MCD_OPC_Decode, + 205, + 14, + 181, + 4, // Opcode: FCVTMSUXDr + /* 103569 */ MCD_OPC_FilterValue, + 113, + 17, + 0, + 0, // Skip to: 103591 + /* 103574 */ MCD_OPC_CheckPredicate, + 49, + 180, + 3, + 0, // Skip to: 104527 + /* 103579 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 173, + 3, + 0, // Skip to: 104527 + /* 103586 */ MCD_OPC_Decode, + 219, + 14, + 181, + 4, // Opcode: FCVTMUUXDr + /* 103591 */ MCD_OPC_FilterValue, + 120, + 17, + 0, + 0, // Skip to: 103613 + /* 103596 */ MCD_OPC_CheckPredicate, + 49, + 158, + 3, + 0, // Skip to: 104527 + /* 103601 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 151, + 3, + 0, // Skip to: 104527 + /* 103608 */ MCD_OPC_Decode, + 180, + 15, + 181, + 4, // Opcode: FCVTZSUXDr + /* 103613 */ MCD_OPC_FilterValue, + 121, + 17, + 0, + 0, // Skip to: 103635 + /* 103618 */ MCD_OPC_CheckPredicate, + 49, + 136, + 3, + 0, // Skip to: 104527 + /* 103623 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 129, + 3, + 0, // Skip to: 104527 + /* 103630 */ MCD_OPC_Decode, + 215, + 15, + 181, + 4, // Opcode: FCVTZUUXDr + /* 103635 */ MCD_OPC_FilterValue, + 174, + 1, + 17, + 0, + 0, // Skip to: 103658 + /* 103641 */ MCD_OPC_CheckPredicate, + 49, + 113, + 3, + 0, // Skip to: 104527 + /* 103646 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 106, + 3, + 0, // Skip to: 104527 + /* 103653 */ MCD_OPC_Decode, + 213, + 17, + 183, + 4, // Opcode: FMOVDXHighr + /* 103658 */ MCD_OPC_FilterValue, + 175, + 1, + 17, + 0, + 0, // Skip to: 103681 + /* 103664 */ MCD_OPC_CheckPredicate, + 49, + 90, + 3, + 0, // Skip to: 104527 + /* 103669 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 83, + 3, + 0, // Skip to: 104527 + /* 103676 */ MCD_OPC_Decode, + 226, + 17, + 183, + 4, // Opcode: FMOVXDHighr + /* 103681 */ MCD_OPC_FilterValue, + 194, + 1, + 10, + 0, + 0, // Skip to: 103697 + /* 103687 */ MCD_OPC_CheckPredicate, + 52, + 67, + 3, + 0, // Skip to: 104527 + /* 103692 */ MCD_OPC_Decode, + 203, + 30, + 184, + 4, // Opcode: SCVTFSXHri + /* 103697 */ MCD_OPC_FilterValue, + 195, + 1, + 10, + 0, + 0, // Skip to: 103713 + /* 103703 */ MCD_OPC_CheckPredicate, + 52, + 51, + 3, + 0, // Skip to: 104527 + /* 103708 */ MCD_OPC_Decode, + 192, + 42, + 184, + 4, // Opcode: UCVTFSXHri + /* 103713 */ MCD_OPC_FilterValue, + 216, + 1, + 10, + 0, + 0, // Skip to: 103729 + /* 103719 */ MCD_OPC_CheckPredicate, + 52, + 35, + 3, + 0, // Skip to: 104527 + /* 103724 */ MCD_OPC_Decode, + 175, + 15, + 185, + 4, // Opcode: FCVTZSSXHri + /* 103729 */ MCD_OPC_FilterValue, + 217, + 1, + 10, + 0, + 0, // Skip to: 103745 + /* 103735 */ MCD_OPC_CheckPredicate, + 52, + 19, + 3, + 0, // Skip to: 104527 + /* 103740 */ MCD_OPC_Decode, + 210, + 15, + 185, + 4, // Opcode: FCVTZUSXHri + /* 103745 */ MCD_OPC_FilterValue, + 224, + 1, + 17, + 0, + 0, // Skip to: 103768 + /* 103751 */ MCD_OPC_CheckPredicate, + 52, + 3, + 3, + 0, // Skip to: 104527 + /* 103756 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 252, + 2, + 0, // Skip to: 104527 + /* 103763 */ MCD_OPC_Decode, + 234, + 14, + 186, + 4, // Opcode: FCVTNSUXHr + /* 103768 */ MCD_OPC_FilterValue, + 225, + 1, + 17, + 0, + 0, // Skip to: 103791 + /* 103774 */ MCD_OPC_CheckPredicate, + 52, + 236, + 2, + 0, // Skip to: 104527 + /* 103779 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 229, + 2, + 0, // Skip to: 104527 + /* 103786 */ MCD_OPC_Decode, + 250, + 14, + 186, + 4, // Opcode: FCVTNUUXHr + /* 103791 */ MCD_OPC_FilterValue, + 226, + 1, + 17, + 0, + 0, // Skip to: 103814 + /* 103797 */ MCD_OPC_CheckPredicate, + 52, + 213, + 2, + 0, // Skip to: 104527 + /* 103802 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 206, + 2, + 0, // Skip to: 104527 + /* 103809 */ MCD_OPC_Decode, + 209, + 30, + 187, + 4, // Opcode: SCVTFUXHri + /* 103814 */ MCD_OPC_FilterValue, + 227, + 1, + 17, + 0, + 0, // Skip to: 103837 + /* 103820 */ MCD_OPC_CheckPredicate, + 52, + 190, + 2, + 0, // Skip to: 104527 + /* 103825 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 183, + 2, + 0, // Skip to: 104527 + /* 103832 */ MCD_OPC_Decode, + 198, + 42, + 187, + 4, // Opcode: UCVTFUXHri + /* 103837 */ MCD_OPC_FilterValue, + 228, + 1, + 17, + 0, + 0, // Skip to: 103860 + /* 103843 */ MCD_OPC_CheckPredicate, + 52, + 167, + 2, + 0, // Skip to: 104527 + /* 103848 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 160, + 2, + 0, // Skip to: 104527 + /* 103855 */ MCD_OPC_Decode, + 168, + 14, + 186, + 4, // Opcode: FCVTASUXHr + /* 103860 */ MCD_OPC_FilterValue, + 229, + 1, + 17, + 0, + 0, // Skip to: 103883 + /* 103866 */ MCD_OPC_CheckPredicate, + 52, + 144, + 2, + 0, // Skip to: 104527 + /* 103871 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 137, + 2, + 0, // Skip to: 104527 + /* 103878 */ MCD_OPC_Decode, + 182, + 14, + 186, + 4, // Opcode: FCVTAUUXHr + /* 103883 */ MCD_OPC_FilterValue, + 230, + 1, + 17, + 0, + 0, // Skip to: 103906 + /* 103889 */ MCD_OPC_CheckPredicate, + 52, + 121, + 2, + 0, // Skip to: 104527 + /* 103894 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 114, + 2, + 0, // Skip to: 104527 + /* 103901 */ MCD_OPC_Decode, + 218, + 17, + 186, + 4, // Opcode: FMOVHXr + /* 103906 */ MCD_OPC_FilterValue, + 231, + 1, + 17, + 0, + 0, // Skip to: 103929 + /* 103912 */ MCD_OPC_CheckPredicate, + 52, + 98, + 2, + 0, // Skip to: 104527 + /* 103917 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 91, + 2, + 0, // Skip to: 104527 + /* 103924 */ MCD_OPC_Decode, + 228, + 17, + 187, + 4, // Opcode: FMOVXHr + /* 103929 */ MCD_OPC_FilterValue, + 232, + 1, + 17, + 0, + 0, // Skip to: 103952 + /* 103935 */ MCD_OPC_CheckPredicate, + 52, + 75, + 2, + 0, // Skip to: 104527 + /* 103940 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 68, + 2, + 0, // Skip to: 104527 + /* 103947 */ MCD_OPC_Decode, + 140, + 15, + 186, + 4, // Opcode: FCVTPSUXHr + /* 103952 */ MCD_OPC_FilterValue, + 233, + 1, + 17, + 0, + 0, // Skip to: 103975 + /* 103958 */ MCD_OPC_CheckPredicate, + 52, + 52, + 2, + 0, // Skip to: 104527 + /* 103963 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 45, + 2, + 0, // Skip to: 104527 + /* 103970 */ MCD_OPC_Decode, + 154, + 15, + 186, + 4, // Opcode: FCVTPUUXHr + /* 103975 */ MCD_OPC_FilterValue, + 240, + 1, + 17, + 0, + 0, // Skip to: 103998 + /* 103981 */ MCD_OPC_CheckPredicate, + 52, + 29, + 2, + 0, // Skip to: 104527 + /* 103986 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 22, + 2, + 0, // Skip to: 104527 + /* 103993 */ MCD_OPC_Decode, + 206, + 14, + 186, + 4, // Opcode: FCVTMSUXHr + /* 103998 */ MCD_OPC_FilterValue, + 241, + 1, + 17, + 0, + 0, // Skip to: 104021 + /* 104004 */ MCD_OPC_CheckPredicate, + 52, + 6, + 2, + 0, // Skip to: 104527 + /* 104009 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 255, + 1, + 0, // Skip to: 104527 + /* 104016 */ MCD_OPC_Decode, + 220, + 14, + 186, + 4, // Opcode: FCVTMUUXHr + /* 104021 */ MCD_OPC_FilterValue, + 248, + 1, + 17, + 0, + 0, // Skip to: 104044 + /* 104027 */ MCD_OPC_CheckPredicate, + 52, + 239, + 1, + 0, // Skip to: 104527 + /* 104032 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 232, + 1, + 0, // Skip to: 104527 + /* 104039 */ MCD_OPC_Decode, + 181, + 15, + 186, + 4, // Opcode: FCVTZSUXHr + /* 104044 */ MCD_OPC_FilterValue, + 249, + 1, + 221, + 1, + 0, // Skip to: 104527 + /* 104050 */ MCD_OPC_CheckPredicate, + 52, + 216, + 1, + 0, // Skip to: 104527 + /* 104055 */ MCD_OPC_CheckField, + 10, + 6, + 0, + 209, + 1, + 0, // Skip to: 104527 + /* 104062 */ MCD_OPC_Decode, + 216, + 15, + 186, + 4, // Opcode: FCVTZUUXHr + /* 104067 */ MCD_OPC_FilterValue, + 5, + 225, + 0, + 0, // Skip to: 104297 + /* 104072 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 104075 */ MCD_OPC_FilterValue, + 0, + 96, + 0, + 0, // Skip to: 104176 + /* 104080 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 104083 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 104100 + /* 104088 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 176, + 1, + 0, // Skip to: 104527 + /* 104095 */ MCD_OPC_Decode, + 151, + 40, + 177, + 3, // Opcode: STURSi + /* 104100 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 104117 + /* 104105 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 159, + 1, + 0, // Skip to: 104527 + /* 104112 */ MCD_OPC_Decode, + 251, + 39, + 177, + 3, // Opcode: STRSpost + /* 104117 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 104159 + /* 104122 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 104125 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 104142 + /* 104130 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 134, + 1, + 0, // Skip to: 104527 + /* 104137 */ MCD_OPC_Decode, + 253, + 39, + 188, + 4, // Opcode: STRSroW + /* 104142 */ MCD_OPC_FilterValue, + 3, + 124, + 1, + 0, // Skip to: 104527 + /* 104147 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 117, + 1, + 0, // Skip to: 104527 + /* 104154 */ MCD_OPC_Decode, + 254, + 39, + 189, + 4, // Opcode: STRSroX + /* 104159 */ MCD_OPC_FilterValue, + 3, + 107, + 1, + 0, // Skip to: 104527 + /* 104164 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 100, + 1, + 0, // Skip to: 104527 + /* 104171 */ MCD_OPC_Decode, + 252, + 39, + 177, + 3, // Opcode: STRSpre + /* 104176 */ MCD_OPC_FilterValue, + 1, + 96, + 0, + 0, // Skip to: 104277 + /* 104181 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 104184 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 104201 + /* 104189 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 75, + 1, + 0, // Skip to: 104527 + /* 104196 */ MCD_OPC_Decode, + 205, + 26, + 177, + 3, // Opcode: LDURSi + /* 104201 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 104218 + /* 104206 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 58, + 1, + 0, // Skip to: 104527 + /* 104213 */ MCD_OPC_Decode, + 213, + 25, + 177, + 3, // Opcode: LDRSpost + /* 104218 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 104260 + /* 104223 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 104226 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 104243 + /* 104231 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 33, + 1, + 0, // Skip to: 104527 + /* 104238 */ MCD_OPC_Decode, + 215, + 25, + 188, + 4, // Opcode: LDRSroW + /* 104243 */ MCD_OPC_FilterValue, + 3, + 23, + 1, + 0, // Skip to: 104527 + /* 104248 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 16, + 1, + 0, // Skip to: 104527 + /* 104255 */ MCD_OPC_Decode, + 216, + 25, + 189, + 4, // Opcode: LDRSroX + /* 104260 */ MCD_OPC_FilterValue, + 3, + 6, + 1, + 0, // Skip to: 104527 + /* 104265 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 255, + 0, + 0, // Skip to: 104527 + /* 104272 */ MCD_OPC_Decode, + 214, + 25, + 177, + 3, // Opcode: LDRSpre + /* 104277 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 104287 + /* 104282 */ MCD_OPC_Decode, + 255, + 39, + 187, + 3, // Opcode: STRSui + /* 104287 */ MCD_OPC_FilterValue, + 5, + 235, + 0, + 0, // Skip to: 104527 + /* 104292 */ MCD_OPC_Decode, + 217, + 25, + 187, + 3, // Opcode: LDRSui + /* 104297 */ MCD_OPC_FilterValue, + 7, + 225, + 0, + 0, // Skip to: 104527 + /* 104302 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 104305 */ MCD_OPC_FilterValue, + 0, + 96, + 0, + 0, // Skip to: 104406 + /* 104310 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 104313 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 104330 + /* 104318 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 202, + 0, + 0, // Skip to: 104527 + /* 104325 */ MCD_OPC_Decode, + 147, + 40, + 177, + 3, // Opcode: STURDi + /* 104330 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 104347 + /* 104335 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 185, + 0, + 0, // Skip to: 104527 + /* 104342 */ MCD_OPC_Decode, + 231, + 39, + 177, + 3, // Opcode: STRDpost + /* 104347 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 104389 + /* 104352 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 104355 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 104372 + /* 104360 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 160, + 0, + 0, // Skip to: 104527 + /* 104367 */ MCD_OPC_Decode, + 233, + 39, + 190, + 4, // Opcode: STRDroW + /* 104372 */ MCD_OPC_FilterValue, + 3, + 150, + 0, + 0, // Skip to: 104527 + /* 104377 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 143, + 0, + 0, // Skip to: 104527 + /* 104384 */ MCD_OPC_Decode, + 234, + 39, + 191, + 4, // Opcode: STRDroX + /* 104389 */ MCD_OPC_FilterValue, + 3, + 133, + 0, + 0, // Skip to: 104527 + /* 104394 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 126, + 0, + 0, // Skip to: 104527 + /* 104401 */ MCD_OPC_Decode, + 232, + 39, + 177, + 3, // Opcode: STRDpre + /* 104406 */ MCD_OPC_FilterValue, + 1, + 96, + 0, + 0, // Skip to: 104507 + /* 104411 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 104414 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 104431 + /* 104419 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 101, + 0, + 0, // Skip to: 104527 + /* 104426 */ MCD_OPC_Decode, + 196, + 26, + 177, + 3, // Opcode: LDURDi + /* 104431 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 104448 + /* 104436 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 84, + 0, + 0, // Skip to: 104527 + /* 104443 */ MCD_OPC_Decode, + 165, + 25, + 177, + 3, // Opcode: LDRDpost + /* 104448 */ MCD_OPC_FilterValue, + 2, + 37, + 0, + 0, // Skip to: 104490 + /* 104453 */ MCD_OPC_ExtractField, + 13, + 2, // Inst{14-13} ... + /* 104456 */ MCD_OPC_FilterValue, + 2, + 12, + 0, + 0, // Skip to: 104473 + /* 104461 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 59, + 0, + 0, // Skip to: 104527 + /* 104468 */ MCD_OPC_Decode, + 167, + 25, + 190, + 4, // Opcode: LDRDroW + /* 104473 */ MCD_OPC_FilterValue, + 3, + 49, + 0, + 0, // Skip to: 104527 + /* 104478 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 42, + 0, + 0, // Skip to: 104527 + /* 104485 */ MCD_OPC_Decode, + 168, + 25, + 191, + 4, // Opcode: LDRDroX + /* 104490 */ MCD_OPC_FilterValue, + 3, + 32, + 0, + 0, // Skip to: 104527 + /* 104495 */ MCD_OPC_CheckField, + 21, + 1, + 0, + 25, + 0, + 0, // Skip to: 104527 + /* 104502 */ MCD_OPC_Decode, + 166, + 25, + 177, + 3, // Opcode: LDRDpre + /* 104507 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 104517 + /* 104512 */ MCD_OPC_Decode, + 235, + 39, + 187, + 3, // Opcode: STRDui + /* 104517 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 104527 + /* 104522 */ MCD_OPC_Decode, + 169, + 25, + 187, + 3, // Opcode: LDRDui + /* 104527 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableFallback32[] = { + /* 0 */ MCD_OPC_ExtractField, 21, 11, // Inst{31-21} ... + /* 3 */ MCD_OPC_FilterValue, 168, 13, 5, 0, 0, // Skip to: 14 + /* 9 */ MCD_OPC_Decode, 206, 27, 192, 4, // Opcode: MSR + /* 14 */ MCD_OPC_FilterValue, 169, 13, 5, 0, 0, // Skip to: 25 + /* 20 */ MCD_OPC_Decode, 201, 27, 193, 4, // Opcode: MRS + /* 25 */ MCD_OPC_Fail, 0}; + +static bool getbool(uint64_t b) { return b != 0; } +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { - default: /* llvm_unreachable("Invalid index!");*/ + default: + llvm_unreachable("Invalid index!"); case 0: - return (AArch64_getFeatureBits(AArch64_FeatureSVE)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSME, 1)); case 1: - return (AArch64_getFeatureBits(AArch64_FeatureLSE)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSMEF64, 1)); case 2: - return (AArch64_getFeatureBits(AArch64_HasV8_1aOps)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSMEI64, 1)); case 3: - return (AArch64_getFeatureBits(AArch64_FeatureNEON)); + return getbool( + (checkFeatureRequired(Bits, AArch64_FeatureSVE, 1) || + checkFeatureRequired(Bits, AArch64_FeatureStreamingSVE, 1))); case 4: - return (AArch64_getFeatureBits(AArch64_FeatureNEON) && AArch64_getFeatureBits(AArch64_FeatureFullFP16)); + return getbool( + (checkFeatureRequired(Bits, AArch64_FeatureSVE2, 1) || + checkFeatureRequired(Bits, AArch64_FeatureStreamingSVE, 1))); case 5: - return (AArch64_getFeatureBits(AArch64_FeatureAES)); + return getbool( + (checkFeatureRequired(Bits, AArch64_FeatureSVE, 1) || + checkFeatureRequired(Bits, AArch64_FeatureStreamingSVE, 1)) && + checkFeatureRequired(Bits, AArch64_FeatureMatMulFP64, 1)); case 6: - return (AArch64_getFeatureBits(AArch64_FeatureSHA3)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSVE, 1)); case 7: - return (AArch64_getFeatureBits(AArch64_FeatureNEON) && AArch64_getFeatureBits(AArch64_FeatureRDM)); + return getbool( + (checkFeatureRequired(Bits, AArch64_FeatureSVE, 1) || + checkFeatureRequired(Bits, AArch64_FeatureStreamingSVE, 1)) && + checkFeatureRequired(Bits, AArch64_FeatureMatMulInt8, 1)); case 8: - return (AArch64_getFeatureBits(AArch64_HasV8_3aOps) && AArch64_getFeatureBits(AArch64_FeatureNEON) && AArch64_getFeatureBits(AArch64_FeatureFullFP16)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSVE2AES, 1)); case 9: - return (AArch64_getFeatureBits(AArch64_FeatureSM4)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSVE, 1) && + checkFeatureRequired(Bits, AArch64_FeatureMatMulInt8, 1)); case 10: - return (AArch64_getFeatureBits(AArch64_FeatureDotProd)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSVE2, 1)); case 11: - return (AArch64_getFeatureBits(AArch64_HasV8_3aOps) && AArch64_getFeatureBits(AArch64_FeatureNEON)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSVE2BitPerm, 1)); case 12: - return (AArch64_getFeatureBits(AArch64_HasV8_4aOps)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSVE2SM4, 1)); case 13: - return (AArch64_getFeatureBits(AArch64_HasV8_3aOps)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSVE2SHA3, 1)); case 14: - return (AArch64_getFeatureBits(AArch64_FeatureCRC)); + return getbool( + checkFeatureRequired(Bits, AArch64_FeatureBF16, 1) && + (checkFeatureRequired(Bits, AArch64_FeatureSVE, 1) || + checkFeatureRequired(Bits, AArch64_FeatureStreamingSVE, 1))); case 15: - return (AArch64_getFeatureBits(AArch64_FeatureRCPC)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureBF16, 1) && + checkFeatureRequired(Bits, AArch64_FeatureSVE, 1)); case 16: - return (AArch64_getFeatureBits(AArch64_FeatureFPARMv8)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSVE, 1) && + checkFeatureRequired(Bits, AArch64_FeatureMatMulFP32, 1)); case 17: - return (AArch64_getFeatureBits(AArch64_HasV8_3aOps) && AArch64_getFeatureBits(AArch64_FeatureFPARMv8)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSVE, 1) && + checkFeatureRequired(Bits, AArch64_FeatureMatMulFP64, 1)); case 18: - return (AArch64_getFeatureBits(AArch64_FeatureFullFP16)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureLSE, 1)); case 19: - return (AArch64_getFeatureBits(AArch64_FeatureSHA2)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureLOR, 1)); case 20: - return (AArch64_getFeatureBits(AArch64_FeatureRDM)); + return getbool(checkFeatureRequired(Bits, AArch64_FeatureMTE, 1)); + case 21: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureNEON, 1)); + case 22: + return getbool( + (checkFeatureRequired(Bits, AArch64_FeatureNEON, 1) || + checkFeatureRequired(Bits, AArch64_FeatureStreamingSVE, 1))); + case 23: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureNEON, 1) && + checkFeatureRequired(Bits, AArch64_FeatureFullFP16, 1)); + case 24: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureFRInt3264, 1)); + case 25: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureNEON, 1) && + checkFeatureRequired(Bits, AArch64_FeatureFP16FML, 1)); + case 26: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureAES, 1)); + case 27: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSHA3, 1)); + case 28: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureNEON, 1) && + checkFeatureRequired(Bits, AArch64_FeatureRDM, 1)); + case 29: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureComplxNum, 1) && + checkFeatureRequired(Bits, AArch64_FeatureNEON, 1) && + checkFeatureRequired(Bits, AArch64_FeatureFullFP16, 1)); + case 30: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureNEON, 1) && + checkFeatureRequired(Bits, AArch64_FeatureBF16, 1)); + case 31: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSM4, 1)); + case 32: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureDotProd, 1)); + case 33: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureMatMulInt8, 1)); + case 34: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureComplxNum, 1) && + checkFeatureRequired(Bits, AArch64_FeatureNEON, 1)); + case 35: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureEL3, 1)); + case 36: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureTME, 1)); + case 37: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureWFxT, 1)); + case 38: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureTRACEV8_4, 1)); + case 39: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureXS, 1)); + case 40: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSB, 1)); + case 41: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureFlagM, 1)); + case 42: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureAltFPCmp, 1)); + case 43: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureBRBE, 1)); + case 44: + return getbool(checkFeatureRequired(Bits, AArch64_FeaturePAuth, 1)); + case 45: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureRCPC_IMMO, 1)); + case 46: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureCRC, 1)); + case 47: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureRCPC, 1)); + case 48: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureLS64, 1)); + case 49: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureFPARMv8, 1)); + case 50: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureJS, 1) && + checkFeatureRequired(Bits, AArch64_FeatureFPARMv8, 1)); + case 51: + return getbool( + (checkFeatureRequired(Bits, AArch64_FeatureNEON, 1) || + checkFeatureRequired(Bits, AArch64_FeatureStreamingSVE, 1)) && + checkFeatureRequired(Bits, AArch64_FeatureBF16, 1)); + case 52: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureFullFP16, 1)); + case 53: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureSHA2, 1)); + case 54: + return getbool( + (checkFeatureRequired(Bits, AArch64_FeatureNEON, 1) || + checkFeatureRequired(Bits, AArch64_FeatureStreamingSVE, 1)) && + checkFeatureRequired(Bits, AArch64_FeatureFullFP16, 1)); + case 55: + return getbool(checkFeatureRequired(Bits, AArch64_FeatureRDM, 1)); } } -#define DecodeToMCInst(fname, fieldname, InsnType) \ -static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, bool *Decoder) \ -{ \ - InsnType tmp; \ - switch (Idx) { \ - default: /* llvm_unreachable("Invalid index!");*/ \ - case 0: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 1: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 2: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 3: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 4: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 5: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 6: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 7: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 8: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 9: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 10: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 11: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 12: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 13: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 14: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 15: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 5) << 0; \ - tmp |= fieldname(insn, 22, 1) << 5; \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 16: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 5) << 0; \ - tmp |= fieldname(insn, 22, 1) << 5; \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 17: \ - if (!Check(&S, DecodeSVELogicalImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 18: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ - return S; \ - case 19: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ - return S; \ - case 20: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ - return S; \ - case 21: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ - return S; \ - case 22: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 23: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ - return S; \ - case 24: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ - return S; \ - case 25: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ - return S; \ - case 26: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ - return S; \ - case 27: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 28: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 16, 5) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 29: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 22, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 30: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 20, 1) << 0; \ - tmp |= fieldname(insn, 22, 2) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 31: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 19, 2) << 0; \ - tmp |= fieldname(insn, 22, 2) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 32: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 18, 3) << 0; \ - tmp |= fieldname(insn, 22, 2) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 33: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 17, 4) << 0; \ - tmp |= fieldname(insn, 22, 2) << 4; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 34: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 35: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 36: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 37: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 38: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 39: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 40: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 41: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 42: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 43: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ - return S; \ - case 44: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ - return S; \ - case 45: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 46: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 47: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 6); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 6))) { return MCDisassembler_Fail; } \ - return S; \ - case 48: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 6); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 6))) { return MCDisassembler_Fail; } \ - return S; \ - case 49: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ - return S; \ - case 50: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 51: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 52: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 53: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 54: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 55: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 56: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 57: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 58: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 59: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 60: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - tmp |= fieldname(insn, 22, 1) << 5; \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 61: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - tmp |= fieldname(insn, 22, 1) << 5; \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 62: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 63: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 64: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 65: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 66: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 67: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 68: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 69: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 70: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 71: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 72: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 73: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 74: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 75: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 76: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 77: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 78: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 79: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 80: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 81: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 82: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 14, 7); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 83: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ - return S; \ - case 84: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 85: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 86: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 87: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 88: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 89: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 90: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 91: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 92: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 93: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 94: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 95: \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 96: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 97: \ - return S; \ - case 98: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ - return S; \ - case 99: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 8); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ - return S; \ - case 100: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 101: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ - return S; \ - case 102: \ - tmp = fieldname(insn, 10, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 103: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 104: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ - return S; \ - case 105: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ - return S; \ - case 106: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 107: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 108: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ - return S; \ - case 109: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ - return S; \ - case 110: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 111: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ - return S; \ - case 112: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 9); \ - if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ - return S; \ - case 113: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 114: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 115: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 116: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 13, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 117: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 19, 2) << 0; \ - tmp |= fieldname(insn, 22, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 118: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 19, 2) << 0; \ - tmp |= fieldname(insn, 22, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 119: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 120: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 121: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 122: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 123: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 124: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 125: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 126: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 127: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 128: \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 129: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 16, 6) << 3; \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 9))) { return MCDisassembler_Fail; } \ - return S; \ - case 130: \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 6))) { return MCDisassembler_Fail; } \ - return S; \ - case 131: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 16, 6) << 3; \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 9))) { return MCDisassembler_Fail; } \ - return S; \ - case 132: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 133: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 134: \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 135: \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 136: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 137: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ - return S; \ - case 138: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 139: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 140: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ - return S; \ - case 141: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPR3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 142: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPR3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ - return S; \ - case 143: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 144: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeZPR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 3); \ - if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ - return S; \ - case 145: \ - if (!Check(&S, DecodeExclusiveLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 146: \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 147: \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 148: \ - if (!Check(&S, DecodeThreeAddrSRegInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 149: \ - if (!Check(&S, DecodeAddSubERegInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 150: \ - if (!Check(&S, DecodePairLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 151: \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 152: \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 153: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 154: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 155: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 156: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 157: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 158: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 159: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 160: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 161: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 162: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 163: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 164: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 165: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 166: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 167: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 168: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 169: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 170: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 171: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 172: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 173: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 174: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 175: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 176: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 177: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 178: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 179: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 180: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 181: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 182: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 183: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 184: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 185: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 186: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 187: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 188: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 189: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 190: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 191: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 192: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 193: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 194: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 195: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 196: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 197: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 198: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 199: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 200: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 201: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 202: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 203: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 204: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 205: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 206: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 207: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 208: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 209: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 210: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 211: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 212: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 213: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 214: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 215: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 216: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 217: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 218: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 219: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 220: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 221: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 222: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 223: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 224: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 225: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 226: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 227: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 228: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 229: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 230: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 231: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 232: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 233: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 234: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 235: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 236: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 237: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 238: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 239: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 240: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 241: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 242: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 243: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 244: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 245: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 246: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 247: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 248: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 249: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 250: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 251: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 252: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 253: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 254: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 255: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 256: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 257: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 258: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 259: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 260: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 261: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 262: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 263: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 264: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 265: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 266: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 267: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 268: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 269: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 270: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 271: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 272: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 273: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 274: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 275: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 276: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 277: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 278: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 279: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 280: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 281: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 282: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 283: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 284: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 285: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 286: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 287: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 288: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 289: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 14, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 290: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 13, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 291: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 292: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 293: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 294: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 295: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 296: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 297: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 298: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 299: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 300: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 301: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 302: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 303: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 304: \ - if (!Check(&S, DecodeModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 305: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 306: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 307: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 308: \ - if (!Check(&S, DecodeModImmTiedInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 309: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 310: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 311: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 312: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 313: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 314: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 315: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 316: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 317: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 318: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 319: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 320: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 321: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 322: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 323: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 324: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 325: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 326: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 327: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 328: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 329: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 330: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 331: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 332: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 333: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 334: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 335: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 336: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 337: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 338: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 339: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 340: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 341: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 342: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 343: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 13, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 344: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 345: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 346: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 347: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 13, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 348: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 349: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 350: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 351: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 352: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 353: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 354: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 355: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 13, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 356: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 357: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 358: \ - if (!Check(&S, DecodeAdrInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 359: \ - if (!Check(&S, DecodeBaseAddSubImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 360: \ - if (!Check(&S, DecodeLogicalImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 361: \ - if (!Check(&S, DecodeMoveImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 362: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 363: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 364: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 365: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 366: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 367: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 368: \ - if (!Check(&S, DecodeUnconditionalBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 369: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 370: \ - if (!Check(&S, DecodeTestAndBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 371: \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 372: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 373: \ - tmp = fieldname(insn, 5, 16); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 374: \ - tmp = fieldname(insn, 8, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 375: \ - tmp = fieldname(insn, 5, 7); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 376: \ - if (!Check(&S, DecodeSystemPStateInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 377: \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 8, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 378: \ - tmp = fieldname(insn, 5, 16); \ - if (!Check(&S, DecodeMSRSystemRegister(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 379: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 8, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 380: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 16); \ - if (!Check(&S, DecodeMRSSystemRegister(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 381: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 382: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 383: \ - if (!Check(&S, DecodeSignedLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 384: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 385: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 386: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 387: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 388: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 389: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 390: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 391: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 392: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 393: \ - if (!Check(&S, DecodeUnsignedLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 394: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 395: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 396: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 397: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 398: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 399: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 400: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 401: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 402: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 403: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 404: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 15, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 405: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 406: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 407: \ - tmp = fieldname(insn, 0, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 408: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 409: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 410: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 411: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 412: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 9) << 0; \ - tmp |= fieldname(insn, 22, 1) << 9; \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 10))) { return MCDisassembler_Fail; } \ - return S; \ - case 413: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 9) << 0; \ - tmp |= fieldname(insn, 22, 1) << 9; \ - if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 10))) { return MCDisassembler_Fail; } \ - return S; \ - case 414: \ - tmp = fieldname(insn, 0, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 415: \ - tmp = fieldname(insn, 0, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 416: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 417: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 418: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 419: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 420: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 421: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 422: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 423: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 424: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 425: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 426: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 13, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 427: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 428: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 429: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 430: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 431: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 432: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 433: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 434: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 435: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 13, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 436: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 437: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 438: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 439: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 440: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 441: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 442: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 443: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 444: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 445: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 446: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 447: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 13, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 448: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 449: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 450: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 451: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 452: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 453: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 454: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 455: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 456: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 457: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 458: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 459: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 460: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 461: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 462: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 463: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 464: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 465: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 466: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 467: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 468: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 469: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 470: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 471: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 472: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 473: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 474: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 475: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 476: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 477: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 478: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 479: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 480: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 481: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 482: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 483: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 484: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 485: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 486: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 487: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 488: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 489: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 490: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 491: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 492: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 493: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 494: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 495: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 496: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 497: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 498: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 499: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 500: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 501: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 502: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 503: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 504: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 505: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 506: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 507: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 508: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 509: \ - if (!Check(&S, DecodeFMOVLaneInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 510: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 511: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 512: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 513: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 514: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 515: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 516: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 517: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - } \ -} +#define DecodeToMCInst(fname, fieldname, InsnType) \ + static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, \ + MCInst *MI, uint64_t Address, bool *Decoder) { \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + llvm_unreachable("Invalid index!"); \ + case 0: \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 1: \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 2: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 3: \ + tmp = fieldname(insn, 0, 8); \ + if (DecodeMatrixTileListRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 5: \ + tmp = fieldname(insn, 3, 1); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 6: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 1); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 7: \ + tmp = fieldname(insn, 3, 1); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 8: \ + tmp = fieldname(insn, 0, 2); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 2) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 9: \ + tmp = fieldname(insn, 2, 2); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 2) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 10: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 2); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 2) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 11: \ + tmp = fieldname(insn, 0, 2); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 2) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 12: \ + tmp = fieldname(insn, 2, 2); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 2) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 13: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 3) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 14: \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 3) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 15: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 16: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 3); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 3) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 17: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 3) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 3) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 21: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeMatrixTile(MI, tmp, Address, Decoder, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 26: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeVecShiftR8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 27: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodeVecShiftR16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeVecShiftR32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeVecShiftL8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodeVecShiftL16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 31: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeVecShiftL32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (DecodeVecShiftR64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 34: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (DecodeVecShiftL64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 35: \ + if (DecodeSVELogicalImmInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 37: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 41: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 42: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 45: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 46: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 16, 5) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 47: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPR2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 16, 5) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 48: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 22, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 49: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 20, 1) << 0; \ + tmp |= fieldname(insn, 22, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 50: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 2) << 0; \ + tmp |= fieldname(insn, 22, 2) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 51: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 18, 3) << 0; \ + tmp |= fieldname(insn, 22, 2) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 52: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 17, 4) << 0; \ + tmp |= fieldname(insn, 22, 2) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 53: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPR2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 55: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftR8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 57: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 58: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (DecodeVecShiftR64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 59: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 60: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 61: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 62: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 64: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 65: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 66: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 68: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 69: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 70: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 6); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 6); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 72: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 73: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 74: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 75: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 76: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 77: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftR8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 78: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 79: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 80: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftL8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftL16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 82: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftL32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 83: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (DecodeVecShiftR64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 84: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (DecodeVecShiftL64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 85: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 86: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 87: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 88: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 89: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 90: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 91: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 92: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 93: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPR2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 94: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 95: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 96: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 97: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 98: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 99: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 100: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 101: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 102: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 103: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 104: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeSVEIncDecImm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 105: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeSVEIncDecImm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 106: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeSVEIncDecImm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 107: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeSVEIncDecImm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 108: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 109: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 110: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 111: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 112: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 113: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 114: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 115: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 116: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 117: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 118: \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 119: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 7); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 120: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 121: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 122: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 123: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 124: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 23, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 125: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 22, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 126: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 20, 1) << 0; \ + tmp |= fieldname(insn, 22, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 127: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + if (DecodeMatrixIndexGPR32_12_15RegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 2) << 0; \ + tmp |= fieldname(insn, 22, 2) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 128: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 129: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 130: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 131: \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 132: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 133: \ + return S; \ + case 134: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 135: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 136: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 137: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 138: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 8); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 139: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 140: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 141: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 142: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 143: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 9); \ + if (DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 144: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 145: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 2) << 0; \ + tmp |= fieldname(insn, 22, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 146: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 147: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 148: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 149: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 19, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 150: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 20, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 151: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 152: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 153: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 154: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 19, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 155: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 20, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 156: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 157: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 158: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 19, 2) << 0; \ + tmp |= fieldname(insn, 22, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 159: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 160: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 161: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 162: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftL8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 163: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftL16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 164: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftL32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 165: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (DecodeVecShiftL64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 166: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 167: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 168: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 169: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 170: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 171: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 172: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 173: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodePPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 16, 6) << 3; \ + if (DecodeSImm(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 174: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 175: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 16, 6) << 3; \ + if (DecodeSImm(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 176: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 177: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 178: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 179: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 180: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 181: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 182: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 183: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 184: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPR2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 185: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPR2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 186: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPR3RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 187: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPR3RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 188: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPR4RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 189: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeZPR4RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 3); \ + if (DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 190: \ + if (DecodeExclusiveLdStInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 191: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 192: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 193: \ + if (DecodeThreeAddrSRegInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 194: \ + if (DecodeAddSubERegInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 195: \ + if (DecodePairLdStInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 196: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 197: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 198: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDDDDRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 199: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDDDRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 200: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 201: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDDRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 202: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 203: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 204: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 205: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 206: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDDDDRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 207: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDDDRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 208: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 209: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDDRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 210: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 211: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 212: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 213: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 214: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 215: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 216: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 217: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 218: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 219: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 220: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 221: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 222: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 223: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 224: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 225: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 226: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 227: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 228: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 229: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 230: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 231: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 232: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 233: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 234: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 235: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 236: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 237: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 238: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 239: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 240: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 241: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 242: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 243: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 244: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 245: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 246: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 247: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 248: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 249: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 250: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 251: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 252: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 253: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 254: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 255: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 256: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 257: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 258: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 259: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 260: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 261: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 262: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 263: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 264: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 265: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 266: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 267: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 268: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 269: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 270: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 271: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 272: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 273: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 274: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 275: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 276: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 277: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 278: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 279: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 280: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 281: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 282: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 283: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 284: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 285: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 286: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 287: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 288: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 289: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 290: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 291: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 292: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 293: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 294: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 295: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 296: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 297: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 298: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 299: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 300: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 301: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 302: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 303: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 304: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 305: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 306: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 307: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 308: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 309: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 310: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 311: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 312: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 313: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 314: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 315: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 316: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 317: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 318: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 319: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 320: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 321: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 322: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 323: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 324: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 325: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 326: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 327: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 328: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 329: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 330: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 331: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 332: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeQQQQRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 333: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 334: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 335: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 336: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 337: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 338: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 339: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 340: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 341: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 342: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 343: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 344: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 345: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 346: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 347: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 348: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 349: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 350: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 351: \ + if (DecodeModImmInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 352: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftR8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 353: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 354: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 355: \ + if (DecodeModImmTiedInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 356: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftR8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 357: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftL8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 358: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 359: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftL16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 360: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 361: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftL32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 362: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 363: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftL8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 364: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 365: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftL16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 366: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 367: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftL32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 368: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftL8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 369: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftL16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 370: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftL32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 371: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 372: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 373: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 374: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftR8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 375: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 376: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 377: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftR8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 378: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftL8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 379: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 380: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftL16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 381: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 382: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftL32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 383: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 384: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 385: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 386: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftL8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 387: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftL16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 388: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftL32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 389: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 390: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 391: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 392: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeVecShiftR64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 393: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeVecShiftR64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 394: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeVecShiftL64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 395: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 396: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeVecShiftL64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 397: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 398: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 399: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 400: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 401: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 402: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 403: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 404: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 405: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 406: \ + if (DecodeAdrInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 407: \ + if (DecodeAddSubImmShift(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 408: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 409: \ + if (DecodeLogicalImmInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 410: \ + if (DecodeMoveImmInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 411: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 412: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 413: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 414: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 415: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 416: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 417: \ + if (DecodeUnconditionalBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 418: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 19); \ + if (DecodePCRelLabel19(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 419: \ + if (DecodeTestAndBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 420: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 19); \ + if (DecodePCRelLabel19(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 421: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 19); \ + if (DecodePCRelLabel19(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 422: \ + tmp = fieldname(insn, 5, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 423: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 424: \ + tmp = fieldname(insn, 5, 7); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 425: \ + tmp = 0x3; \ + tmp |= fieldname(insn, 10, 2) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 426: \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 427: \ + tmp = fieldname(insn, 9, 3); \ + if (DecodeSVCROp(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 428: \ + if (DecodeSystemPStateInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + *Decoder = false; \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 429: \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 430: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 431: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 432: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 433: \ + if (DecodeSignedLdStInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 434: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 435: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 436: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 437: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 438: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 439: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 440: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 441: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 442: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 443: \ + if (DecodeUnsignedLdStInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 444: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 445: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 446: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 447: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 448: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 449: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 450: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 451: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 452: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 453: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 454: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 455: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 456: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 457: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 458: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 459: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 460: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 19); \ + if (DecodePCRelLabel19(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 461: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 462: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 9); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 463: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 9); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 464: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 9); \ + if (DecodeSImm(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 465: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 466: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 467: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 468: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 469: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64x8ClassRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 470: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64x8ClassRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 471: \ + if (DecodeAuthLoadInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 472: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 473: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 474: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 19); \ + if (DecodePCRelLabel19(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 475: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x20; \ + tmp |= fieldname(insn, 10, 5) << 0; \ + if (DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 476: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x20; \ + tmp |= fieldname(insn, 10, 5) << 0; \ + if (DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 477: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 478: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 479: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 480: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 481: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 482: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 483: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 484: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 485: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 486: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 487: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 488: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x20; \ + tmp |= fieldname(insn, 10, 5) << 0; \ + if (DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 489: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x20; \ + tmp |= fieldname(insn, 10, 5) << 0; \ + if (DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 490: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 491: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 492: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 493: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 494: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 495: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 496: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x20; \ + tmp |= fieldname(insn, 10, 5) << 0; \ + if (DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 497: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x20; \ + tmp |= fieldname(insn, 10, 5) << 0; \ + if (DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 498: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 499: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 500: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 501: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 502: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 503: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 504: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 505: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 506: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 507: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 508: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 509: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 510: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 511: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 512: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 513: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 514: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 515: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 516: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 19); \ + if (DecodePCRelLabel19(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 517: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 518: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 519: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 520: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 521: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 522: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 523: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 524: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 525: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 526: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 527: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 528: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 529: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 530: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 531: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 532: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeVecShiftR64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 533: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 534: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeVecShiftR64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 535: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 536: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 537: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 538: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 539: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeVecShiftL64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 540: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftL8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 541: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftL16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 542: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftL32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 543: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 544: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeVecShiftR8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 545: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 546: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 547: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 548: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 549: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 550: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 551: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeVecShiftR16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 552: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeVecShiftR32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 553: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 554: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 555: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 556: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 557: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeVecShiftL64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 558: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR128RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 19); \ + if (DecodePCRelLabel19(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 559: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 6); \ + if (DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 560: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 6); \ + if (DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 561: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 562: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 563: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 6); \ + if (DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 564: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 6); \ + if (DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 565: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 566: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 567: \ + if (DecodeFMOVLaneInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 568: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 6); \ + if (DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 569: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 6); \ + if (DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 570: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 571: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 572: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 573: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 574: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 575: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (DecodeMemExtend(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 576: \ + tmp = fieldname(insn, 5, 16); \ + if (DecodeMSRSystemRegister(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 577: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 16); \ + if (DecodeMRSSystemRegister(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + } \ + } -#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address) \ -{ \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail, DecodeComplete = true; \ - uint32_t ExpectedValue; \ - const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0; \ - DecodeStatus S = MCDisassembler_Success; \ - while (true) { \ - switch (*Ptr) { \ - default: \ - return MCDisassembler_Fail; \ - case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - ++Ptr; \ - CurFieldValue = fieldname(insn, Start, Len); \ - break; \ - } \ - case MCD_OPC_FilterValue: { \ - /* Decode the field value. */ \ - Val = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - /* NumToSkip is a plain 24-bit integer. */ \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - NumToSkip |= (*Ptr++) << 16; \ - /* Perform the filter operation. */ \ - if (Val != CurFieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - /* Decode the field value. */ \ - ExpectedValue = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - /* NumToSkip is a plain 24-bit integer. */ \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - NumToSkip |= (*Ptr++) << 16; \ - /* If the actual and expected values don't match, skip. */ \ - if (ExpectedValue != FieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckPredicate: { \ - /* Decode the Predicate Index value. */ \ - PIdx = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - /* NumToSkip is a plain 24-bit integer. */ \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - NumToSkip |= (*Ptr++) << 16; \ - /* Check the predicate. */ \ - if (!(Pred = checkDecoderPredicate(PIdx, MI))) \ - Ptr += NumToSkip; \ - (void)Pred; \ - break; \ - } \ - case MCD_OPC_Decode: { \ - /* Decode the Opcode value. */ \ - Opc = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - DecodeIdx = decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - MCInst_clear(MI); \ - MCInst_setOpcode(MI, Opc); \ - S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ - /* assert(DecodeComplete); */ \ - return S; \ - } \ - case MCD_OPC_TryDecode: { \ - /* Decode the Opcode value. */ \ - Opc = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - DecodeIdx = decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - /* NumToSkip is a plain 24-bit integer. */ \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - NumToSkip |= (*Ptr++) << 16; \ - /* Perform the decode operation. */ \ - MCInst_setOpcode(MI, Opc); \ - S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ - if (DecodeComplete) { \ - /* Decoding complete. */ \ - return S; \ - } else { \ - /* assert(S == MCDisassembler_Fail); */ \ - /* If the decoding was incomplete, skip. */ \ - Ptr += NumToSkip; \ - /* Reset decode status. This also drops a SoftFail status that could be */ \ - /* set before the decode attempt. */ \ - S = MCDisassembler_Success; \ - } \ - break; \ - } \ - case MCD_OPC_SoftFail: { \ - /* Decode the mask values. */ \ - PositiveMask = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NegativeMask = decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ - if (Fail) \ - S = MCDisassembler_SoftFail; \ - break; \ - } \ - case MCD_OPC_Fail: { \ - return MCDisassembler_Fail; \ - } \ - } \ - } \ - /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ -} +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ + static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + MCRegisterInfo *MRI, int feature) { \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, feature))) \ + Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could \ + * be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ + } + +FieldFromInstruction(fieldFromInstruction, uint32_t) + DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) + DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) + +#endif // MIPS_GET_DISASSEMBLER +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +#define AArch64_FFR 1 +#define AArch64_FP 2 +#define AArch64_LR 3 +#define AArch64_NZCV 4 +#define AArch64_SP 5 +#define AArch64_VG 6 +#define AArch64_WSP 7 +#define AArch64_WZR 8 +#define AArch64_XZR 9 +#define AArch64_ZA 10 +#define AArch64_B0 11 +#define AArch64_B1 12 +#define AArch64_B2 13 +#define AArch64_B3 14 +#define AArch64_B4 15 +#define AArch64_B5 16 +#define AArch64_B6 17 +#define AArch64_B7 18 +#define AArch64_B8 19 +#define AArch64_B9 20 +#define AArch64_B10 21 +#define AArch64_B11 22 +#define AArch64_B12 23 +#define AArch64_B13 24 +#define AArch64_B14 25 +#define AArch64_B15 26 +#define AArch64_B16 27 +#define AArch64_B17 28 +#define AArch64_B18 29 +#define AArch64_B19 30 +#define AArch64_B20 31 +#define AArch64_B21 32 +#define AArch64_B22 33 +#define AArch64_B23 34 +#define AArch64_B24 35 +#define AArch64_B25 36 +#define AArch64_B26 37 +#define AArch64_B27 38 +#define AArch64_B28 39 +#define AArch64_B29 40 +#define AArch64_B30 41 +#define AArch64_B31 42 +#define AArch64_D0 43 +#define AArch64_D1 44 +#define AArch64_D2 45 +#define AArch64_D3 46 +#define AArch64_D4 47 +#define AArch64_D5 48 +#define AArch64_D6 49 +#define AArch64_D7 50 +#define AArch64_D8 51 +#define AArch64_D9 52 +#define AArch64_D10 53 +#define AArch64_D11 54 +#define AArch64_D12 55 +#define AArch64_D13 56 +#define AArch64_D14 57 +#define AArch64_D15 58 +#define AArch64_D16 59 +#define AArch64_D17 60 +#define AArch64_D18 61 +#define AArch64_D19 62 +#define AArch64_D20 63 +#define AArch64_D21 64 +#define AArch64_D22 65 +#define AArch64_D23 66 +#define AArch64_D24 67 +#define AArch64_D25 68 +#define AArch64_D26 69 +#define AArch64_D27 70 +#define AArch64_D28 71 +#define AArch64_D29 72 +#define AArch64_D30 73 +#define AArch64_D31 74 +#define AArch64_H0 75 +#define AArch64_H1 76 +#define AArch64_H2 77 +#define AArch64_H3 78 +#define AArch64_H4 79 +#define AArch64_H5 80 +#define AArch64_H6 81 +#define AArch64_H7 82 +#define AArch64_H8 83 +#define AArch64_H9 84 +#define AArch64_H10 85 +#define AArch64_H11 86 +#define AArch64_H12 87 +#define AArch64_H13 88 +#define AArch64_H14 89 +#define AArch64_H15 90 +#define AArch64_H16 91 +#define AArch64_H17 92 +#define AArch64_H18 93 +#define AArch64_H19 94 +#define AArch64_H20 95 +#define AArch64_H21 96 +#define AArch64_H22 97 +#define AArch64_H23 98 +#define AArch64_H24 99 +#define AArch64_H25 100 +#define AArch64_H26 101 +#define AArch64_H27 102 +#define AArch64_H28 103 +#define AArch64_H29 104 +#define AArch64_H30 105 +#define AArch64_H31 106 +#define AArch64_P0 107 +#define AArch64_P1 108 +#define AArch64_P2 109 +#define AArch64_P3 110 +#define AArch64_P4 111 +#define AArch64_P5 112 +#define AArch64_P6 113 +#define AArch64_P7 114 +#define AArch64_P8 115 +#define AArch64_P9 116 +#define AArch64_P10 117 +#define AArch64_P11 118 +#define AArch64_P12 119 +#define AArch64_P13 120 +#define AArch64_P14 121 +#define AArch64_P15 122 +#define AArch64_Q0 123 +#define AArch64_Q1 124 +#define AArch64_Q2 125 +#define AArch64_Q3 126 +#define AArch64_Q4 127 +#define AArch64_Q5 128 +#define AArch64_Q6 129 +#define AArch64_Q7 130 +#define AArch64_Q8 131 +#define AArch64_Q9 132 +#define AArch64_Q10 133 +#define AArch64_Q11 134 +#define AArch64_Q12 135 +#define AArch64_Q13 136 +#define AArch64_Q14 137 +#define AArch64_Q15 138 +#define AArch64_Q16 139 +#define AArch64_Q17 140 +#define AArch64_Q18 141 +#define AArch64_Q19 142 +#define AArch64_Q20 143 +#define AArch64_Q21 144 +#define AArch64_Q22 145 +#define AArch64_Q23 146 +#define AArch64_Q24 147 +#define AArch64_Q25 148 +#define AArch64_Q26 149 +#define AArch64_Q27 150 +#define AArch64_Q28 151 +#define AArch64_Q29 152 +#define AArch64_Q30 153 +#define AArch64_Q31 154 +#define AArch64_S0 155 +#define AArch64_S1 156 +#define AArch64_S2 157 +#define AArch64_S3 158 +#define AArch64_S4 159 +#define AArch64_S5 160 +#define AArch64_S6 161 +#define AArch64_S7 162 +#define AArch64_S8 163 +#define AArch64_S9 164 +#define AArch64_S10 165 +#define AArch64_S11 166 +#define AArch64_S12 167 +#define AArch64_S13 168 +#define AArch64_S14 169 +#define AArch64_S15 170 +#define AArch64_S16 171 +#define AArch64_S17 172 +#define AArch64_S18 173 +#define AArch64_S19 174 +#define AArch64_S20 175 +#define AArch64_S21 176 +#define AArch64_S22 177 +#define AArch64_S23 178 +#define AArch64_S24 179 +#define AArch64_S25 180 +#define AArch64_S26 181 +#define AArch64_S27 182 +#define AArch64_S28 183 +#define AArch64_S29 184 +#define AArch64_S30 185 +#define AArch64_S31 186 +#define AArch64_W0 187 +#define AArch64_W1 188 +#define AArch64_W2 189 +#define AArch64_W3 190 +#define AArch64_W4 191 +#define AArch64_W5 192 +#define AArch64_W6 193 +#define AArch64_W7 194 +#define AArch64_W8 195 +#define AArch64_W9 196 +#define AArch64_W10 197 +#define AArch64_W11 198 +#define AArch64_W12 199 +#define AArch64_W13 200 +#define AArch64_W14 201 +#define AArch64_W15 202 +#define AArch64_W16 203 +#define AArch64_W17 204 +#define AArch64_W18 205 +#define AArch64_W19 206 +#define AArch64_W20 207 +#define AArch64_W21 208 +#define AArch64_W22 209 +#define AArch64_W23 210 +#define AArch64_W24 211 +#define AArch64_W25 212 +#define AArch64_W26 213 +#define AArch64_W27 214 +#define AArch64_W28 215 +#define AArch64_W29 216 +#define AArch64_W30 217 +#define AArch64_X0 218 +#define AArch64_X1 219 +#define AArch64_X2 220 +#define AArch64_X3 221 +#define AArch64_X4 222 +#define AArch64_X5 223 +#define AArch64_X6 224 +#define AArch64_X7 225 +#define AArch64_X8 226 +#define AArch64_X9 227 +#define AArch64_X10 228 +#define AArch64_X11 229 +#define AArch64_X12 230 +#define AArch64_X13 231 +#define AArch64_X14 232 +#define AArch64_X15 233 +#define AArch64_X16 234 +#define AArch64_X17 235 +#define AArch64_X18 236 +#define AArch64_X19 237 +#define AArch64_X20 238 +#define AArch64_X21 239 +#define AArch64_X22 240 +#define AArch64_X23 241 +#define AArch64_X24 242 +#define AArch64_X25 243 +#define AArch64_X26 244 +#define AArch64_X27 245 +#define AArch64_X28 246 +#define AArch64_Z0 247 +#define AArch64_Z1 248 +#define AArch64_Z2 249 +#define AArch64_Z3 250 +#define AArch64_Z4 251 +#define AArch64_Z5 252 +#define AArch64_Z6 253 +#define AArch64_Z7 254 +#define AArch64_Z8 255 +#define AArch64_Z9 256 +#define AArch64_Z10 257 +#define AArch64_Z11 258 +#define AArch64_Z12 259 +#define AArch64_Z13 260 +#define AArch64_Z14 261 +#define AArch64_Z15 262 +#define AArch64_Z16 263 +#define AArch64_Z17 264 +#define AArch64_Z18 265 +#define AArch64_Z19 266 +#define AArch64_Z20 267 +#define AArch64_Z21 268 +#define AArch64_Z22 269 +#define AArch64_Z23 270 +#define AArch64_Z24 271 +#define AArch64_Z25 272 +#define AArch64_Z26 273 +#define AArch64_Z27 274 +#define AArch64_Z28 275 +#define AArch64_Z29 276 +#define AArch64_Z30 277 +#define AArch64_Z31 278 +#define AArch64_ZAB0 279 +#define AArch64_ZAD0 280 +#define AArch64_ZAD1 281 +#define AArch64_ZAD2 282 +#define AArch64_ZAD3 283 +#define AArch64_ZAD4 284 +#define AArch64_ZAD5 285 +#define AArch64_ZAD6 286 +#define AArch64_ZAD7 287 +#define AArch64_ZAH0 288 +#define AArch64_ZAH1 289 +#define AArch64_ZAQ0 290 +#define AArch64_ZAQ1 291 +#define AArch64_ZAQ2 292 +#define AArch64_ZAQ3 293 +#define AArch64_ZAQ4 294 +#define AArch64_ZAQ5 295 +#define AArch64_ZAQ6 296 +#define AArch64_ZAQ7 297 +#define AArch64_ZAQ8 298 +#define AArch64_ZAQ9 299 +#define AArch64_ZAQ10 300 +#define AArch64_ZAQ11 301 +#define AArch64_ZAQ12 302 +#define AArch64_ZAQ13 303 +#define AArch64_ZAQ14 304 +#define AArch64_ZAQ15 305 +#define AArch64_ZAS0 306 +#define AArch64_ZAS1 307 +#define AArch64_ZAS2 308 +#define AArch64_ZAS3 309 +#define AArch64_Z0_HI 310 +#define AArch64_Z1_HI 311 +#define AArch64_Z2_HI 312 +#define AArch64_Z3_HI 313 +#define AArch64_Z4_HI 314 +#define AArch64_Z5_HI 315 +#define AArch64_Z6_HI 316 +#define AArch64_Z7_HI 317 +#define AArch64_Z8_HI 318 +#define AArch64_Z9_HI 319 +#define AArch64_Z10_HI 320 +#define AArch64_Z11_HI 321 +#define AArch64_Z12_HI 322 +#define AArch64_Z13_HI 323 +#define AArch64_Z14_HI 324 +#define AArch64_Z15_HI 325 +#define AArch64_Z16_HI 326 +#define AArch64_Z17_HI 327 +#define AArch64_Z18_HI 328 +#define AArch64_Z19_HI 329 +#define AArch64_Z20_HI 330 +#define AArch64_Z21_HI 331 +#define AArch64_Z22_HI 332 +#define AArch64_Z23_HI 333 +#define AArch64_Z24_HI 334 +#define AArch64_Z25_HI 335 +#define AArch64_Z26_HI 336 +#define AArch64_Z27_HI 337 +#define AArch64_Z28_HI 338 +#define AArch64_Z29_HI 339 +#define AArch64_Z30_HI 340 +#define AArch64_Z31_HI 341 +#define AArch64_D0_D1 342 +#define AArch64_D1_D2 343 +#define AArch64_D2_D3 344 +#define AArch64_D3_D4 345 +#define AArch64_D4_D5 346 +#define AArch64_D5_D6 347 +#define AArch64_D6_D7 348 +#define AArch64_D7_D8 349 +#define AArch64_D8_D9 350 +#define AArch64_D9_D10 351 +#define AArch64_D10_D11 352 +#define AArch64_D11_D12 353 +#define AArch64_D12_D13 354 +#define AArch64_D13_D14 355 +#define AArch64_D14_D15 356 +#define AArch64_D15_D16 357 +#define AArch64_D16_D17 358 +#define AArch64_D17_D18 359 +#define AArch64_D18_D19 360 +#define AArch64_D19_D20 361 +#define AArch64_D20_D21 362 +#define AArch64_D21_D22 363 +#define AArch64_D22_D23 364 +#define AArch64_D23_D24 365 +#define AArch64_D24_D25 366 +#define AArch64_D25_D26 367 +#define AArch64_D26_D27 368 +#define AArch64_D27_D28 369 +#define AArch64_D28_D29 370 +#define AArch64_D29_D30 371 +#define AArch64_D30_D31 372 +#define AArch64_D31_D0 373 +#define AArch64_D0_D1_D2_D3 374 +#define AArch64_D1_D2_D3_D4 375 +#define AArch64_D2_D3_D4_D5 376 +#define AArch64_D3_D4_D5_D6 377 +#define AArch64_D4_D5_D6_D7 378 +#define AArch64_D5_D6_D7_D8 379 +#define AArch64_D6_D7_D8_D9 380 +#define AArch64_D7_D8_D9_D10 381 +#define AArch64_D8_D9_D10_D11 382 +#define AArch64_D9_D10_D11_D12 383 +#define AArch64_D10_D11_D12_D13 384 +#define AArch64_D11_D12_D13_D14 385 +#define AArch64_D12_D13_D14_D15 386 +#define AArch64_D13_D14_D15_D16 387 +#define AArch64_D14_D15_D16_D17 388 +#define AArch64_D15_D16_D17_D18 389 +#define AArch64_D16_D17_D18_D19 390 +#define AArch64_D17_D18_D19_D20 391 +#define AArch64_D18_D19_D20_D21 392 +#define AArch64_D19_D20_D21_D22 393 +#define AArch64_D20_D21_D22_D23 394 +#define AArch64_D21_D22_D23_D24 395 +#define AArch64_D22_D23_D24_D25 396 +#define AArch64_D23_D24_D25_D26 397 +#define AArch64_D24_D25_D26_D27 398 +#define AArch64_D25_D26_D27_D28 399 +#define AArch64_D26_D27_D28_D29 400 +#define AArch64_D27_D28_D29_D30 401 +#define AArch64_D28_D29_D30_D31 402 +#define AArch64_D29_D30_D31_D0 403 +#define AArch64_D30_D31_D0_D1 404 +#define AArch64_D31_D0_D1_D2 405 +#define AArch64_D0_D1_D2 406 +#define AArch64_D1_D2_D3 407 +#define AArch64_D2_D3_D4 408 +#define AArch64_D3_D4_D5 409 +#define AArch64_D4_D5_D6 410 +#define AArch64_D5_D6_D7 411 +#define AArch64_D6_D7_D8 412 +#define AArch64_D7_D8_D9 413 +#define AArch64_D8_D9_D10 414 +#define AArch64_D9_D10_D11 415 +#define AArch64_D10_D11_D12 416 +#define AArch64_D11_D12_D13 417 +#define AArch64_D12_D13_D14 418 +#define AArch64_D13_D14_D15 419 +#define AArch64_D14_D15_D16 420 +#define AArch64_D15_D16_D17 421 +#define AArch64_D16_D17_D18 422 +#define AArch64_D17_D18_D19 423 +#define AArch64_D18_D19_D20 424 +#define AArch64_D19_D20_D21 425 +#define AArch64_D20_D21_D22 426 +#define AArch64_D21_D22_D23 427 +#define AArch64_D22_D23_D24 428 +#define AArch64_D23_D24_D25 429 +#define AArch64_D24_D25_D26 430 +#define AArch64_D25_D26_D27 431 +#define AArch64_D26_D27_D28 432 +#define AArch64_D27_D28_D29 433 +#define AArch64_D28_D29_D30 434 +#define AArch64_D29_D30_D31 435 +#define AArch64_D30_D31_D0 436 +#define AArch64_D31_D0_D1 437 +#define AArch64_Q0_Q1 438 +#define AArch64_Q1_Q2 439 +#define AArch64_Q2_Q3 440 +#define AArch64_Q3_Q4 441 +#define AArch64_Q4_Q5 442 +#define AArch64_Q5_Q6 443 +#define AArch64_Q6_Q7 444 +#define AArch64_Q7_Q8 445 +#define AArch64_Q8_Q9 446 +#define AArch64_Q9_Q10 447 +#define AArch64_Q10_Q11 448 +#define AArch64_Q11_Q12 449 +#define AArch64_Q12_Q13 450 +#define AArch64_Q13_Q14 451 +#define AArch64_Q14_Q15 452 +#define AArch64_Q15_Q16 453 +#define AArch64_Q16_Q17 454 +#define AArch64_Q17_Q18 455 +#define AArch64_Q18_Q19 456 +#define AArch64_Q19_Q20 457 +#define AArch64_Q20_Q21 458 +#define AArch64_Q21_Q22 459 +#define AArch64_Q22_Q23 460 +#define AArch64_Q23_Q24 461 +#define AArch64_Q24_Q25 462 +#define AArch64_Q25_Q26 463 +#define AArch64_Q26_Q27 464 +#define AArch64_Q27_Q28 465 +#define AArch64_Q28_Q29 466 +#define AArch64_Q29_Q30 467 +#define AArch64_Q30_Q31 468 +#define AArch64_Q31_Q0 469 +#define AArch64_Q0_Q1_Q2_Q3 470 +#define AArch64_Q1_Q2_Q3_Q4 471 +#define AArch64_Q2_Q3_Q4_Q5 472 +#define AArch64_Q3_Q4_Q5_Q6 473 +#define AArch64_Q4_Q5_Q6_Q7 474 +#define AArch64_Q5_Q6_Q7_Q8 475 +#define AArch64_Q6_Q7_Q8_Q9 476 +#define AArch64_Q7_Q8_Q9_Q10 477 +#define AArch64_Q8_Q9_Q10_Q11 478 +#define AArch64_Q9_Q10_Q11_Q12 479 +#define AArch64_Q10_Q11_Q12_Q13 480 +#define AArch64_Q11_Q12_Q13_Q14 481 +#define AArch64_Q12_Q13_Q14_Q15 482 +#define AArch64_Q13_Q14_Q15_Q16 483 +#define AArch64_Q14_Q15_Q16_Q17 484 +#define AArch64_Q15_Q16_Q17_Q18 485 +#define AArch64_Q16_Q17_Q18_Q19 486 +#define AArch64_Q17_Q18_Q19_Q20 487 +#define AArch64_Q18_Q19_Q20_Q21 488 +#define AArch64_Q19_Q20_Q21_Q22 489 +#define AArch64_Q20_Q21_Q22_Q23 490 +#define AArch64_Q21_Q22_Q23_Q24 491 +#define AArch64_Q22_Q23_Q24_Q25 492 +#define AArch64_Q23_Q24_Q25_Q26 493 +#define AArch64_Q24_Q25_Q26_Q27 494 +#define AArch64_Q25_Q26_Q27_Q28 495 +#define AArch64_Q26_Q27_Q28_Q29 496 +#define AArch64_Q27_Q28_Q29_Q30 497 +#define AArch64_Q28_Q29_Q30_Q31 498 +#define AArch64_Q29_Q30_Q31_Q0 499 +#define AArch64_Q30_Q31_Q0_Q1 500 +#define AArch64_Q31_Q0_Q1_Q2 501 +#define AArch64_Q0_Q1_Q2 502 +#define AArch64_Q1_Q2_Q3 503 +#define AArch64_Q2_Q3_Q4 504 +#define AArch64_Q3_Q4_Q5 505 +#define AArch64_Q4_Q5_Q6 506 +#define AArch64_Q5_Q6_Q7 507 +#define AArch64_Q6_Q7_Q8 508 +#define AArch64_Q7_Q8_Q9 509 +#define AArch64_Q8_Q9_Q10 510 +#define AArch64_Q9_Q10_Q11 511 +#define AArch64_Q10_Q11_Q12 512 +#define AArch64_Q11_Q12_Q13 513 +#define AArch64_Q12_Q13_Q14 514 +#define AArch64_Q13_Q14_Q15 515 +#define AArch64_Q14_Q15_Q16 516 +#define AArch64_Q15_Q16_Q17 517 +#define AArch64_Q16_Q17_Q18 518 +#define AArch64_Q17_Q18_Q19 519 +#define AArch64_Q18_Q19_Q20 520 +#define AArch64_Q19_Q20_Q21 521 +#define AArch64_Q20_Q21_Q22 522 +#define AArch64_Q21_Q22_Q23 523 +#define AArch64_Q22_Q23_Q24 524 +#define AArch64_Q23_Q24_Q25 525 +#define AArch64_Q24_Q25_Q26 526 +#define AArch64_Q25_Q26_Q27 527 +#define AArch64_Q26_Q27_Q28 528 +#define AArch64_Q27_Q28_Q29 529 +#define AArch64_Q28_Q29_Q30 530 +#define AArch64_Q29_Q30_Q31 531 +#define AArch64_Q30_Q31_Q0 532 +#define AArch64_Q31_Q0_Q1 533 +#define AArch64_X22_X23_X24_X25_X26_X27_X28_FP 534 +#define AArch64_X0_X1_X2_X3_X4_X5_X6_X7 535 +#define AArch64_X2_X3_X4_X5_X6_X7_X8_X9 536 +#define AArch64_X4_X5_X6_X7_X8_X9_X10_X11 537 +#define AArch64_X6_X7_X8_X9_X10_X11_X12_X13 538 +#define AArch64_X8_X9_X10_X11_X12_X13_X14_X15 539 +#define AArch64_X10_X11_X12_X13_X14_X15_X16_X17 540 +#define AArch64_X12_X13_X14_X15_X16_X17_X18_X19 541 +#define AArch64_X14_X15_X16_X17_X18_X19_X20_X21 542 +#define AArch64_X16_X17_X18_X19_X20_X21_X22_X23 543 +#define AArch64_X18_X19_X20_X21_X22_X23_X24_X25 544 +#define AArch64_X20_X21_X22_X23_X24_X25_X26_X27 545 +#define AArch64_W30_WZR 546 +#define AArch64_W0_W1 547 +#define AArch64_W2_W3 548 +#define AArch64_W4_W5 549 +#define AArch64_W6_W7 550 +#define AArch64_W8_W9 551 +#define AArch64_W10_W11 552 +#define AArch64_W12_W13 553 +#define AArch64_W14_W15 554 +#define AArch64_W16_W17 555 +#define AArch64_W18_W19 556 +#define AArch64_W20_W21 557 +#define AArch64_W22_W23 558 +#define AArch64_W24_W25 559 +#define AArch64_W26_W27 560 +#define AArch64_W28_W29 561 +#define AArch64_LR_XZR 562 +#define AArch64_X28_FP 563 +#define AArch64_X0_X1 564 +#define AArch64_X2_X3 565 +#define AArch64_X4_X5 566 +#define AArch64_X6_X7 567 +#define AArch64_X8_X9 568 +#define AArch64_X10_X11 569 +#define AArch64_X12_X13 570 +#define AArch64_X14_X15 571 +#define AArch64_X16_X17 572 +#define AArch64_X18_X19 573 +#define AArch64_X20_X21 574 +#define AArch64_X22_X23 575 +#define AArch64_X24_X25 576 +#define AArch64_X26_X27 577 +#define AArch64_Z0_Z1 578 +#define AArch64_Z1_Z2 579 +#define AArch64_Z2_Z3 580 +#define AArch64_Z3_Z4 581 +#define AArch64_Z4_Z5 582 +#define AArch64_Z5_Z6 583 +#define AArch64_Z6_Z7 584 +#define AArch64_Z7_Z8 585 +#define AArch64_Z8_Z9 586 +#define AArch64_Z9_Z10 587 +#define AArch64_Z10_Z11 588 +#define AArch64_Z11_Z12 589 +#define AArch64_Z12_Z13 590 +#define AArch64_Z13_Z14 591 +#define AArch64_Z14_Z15 592 +#define AArch64_Z15_Z16 593 +#define AArch64_Z16_Z17 594 +#define AArch64_Z17_Z18 595 +#define AArch64_Z18_Z19 596 +#define AArch64_Z19_Z20 597 +#define AArch64_Z20_Z21 598 +#define AArch64_Z21_Z22 599 +#define AArch64_Z22_Z23 600 +#define AArch64_Z23_Z24 601 +#define AArch64_Z24_Z25 602 +#define AArch64_Z25_Z26 603 +#define AArch64_Z26_Z27 604 +#define AArch64_Z27_Z28 605 +#define AArch64_Z28_Z29 606 +#define AArch64_Z29_Z30 607 +#define AArch64_Z30_Z31 608 +#define AArch64_Z31_Z0 609 +#define AArch64_Z0_Z1_Z2_Z3 610 +#define AArch64_Z1_Z2_Z3_Z4 611 +#define AArch64_Z2_Z3_Z4_Z5 612 +#define AArch64_Z3_Z4_Z5_Z6 613 +#define AArch64_Z4_Z5_Z6_Z7 614 +#define AArch64_Z5_Z6_Z7_Z8 615 +#define AArch64_Z6_Z7_Z8_Z9 616 +#define AArch64_Z7_Z8_Z9_Z10 617 +#define AArch64_Z8_Z9_Z10_Z11 618 +#define AArch64_Z9_Z10_Z11_Z12 619 +#define AArch64_Z10_Z11_Z12_Z13 620 +#define AArch64_Z11_Z12_Z13_Z14 621 +#define AArch64_Z12_Z13_Z14_Z15 622 +#define AArch64_Z13_Z14_Z15_Z16 623 +#define AArch64_Z14_Z15_Z16_Z17 624 +#define AArch64_Z15_Z16_Z17_Z18 625 +#define AArch64_Z16_Z17_Z18_Z19 626 +#define AArch64_Z17_Z18_Z19_Z20 627 +#define AArch64_Z18_Z19_Z20_Z21 628 +#define AArch64_Z19_Z20_Z21_Z22 629 +#define AArch64_Z20_Z21_Z22_Z23 630 +#define AArch64_Z21_Z22_Z23_Z24 631 +#define AArch64_Z22_Z23_Z24_Z25 632 +#define AArch64_Z23_Z24_Z25_Z26 633 +#define AArch64_Z24_Z25_Z26_Z27 634 +#define AArch64_Z25_Z26_Z27_Z28 635 +#define AArch64_Z26_Z27_Z28_Z29 636 +#define AArch64_Z27_Z28_Z29_Z30 637 +#define AArch64_Z28_Z29_Z30_Z31 638 +#define AArch64_Z29_Z30_Z31_Z0 639 +#define AArch64_Z30_Z31_Z0_Z1 640 +#define AArch64_Z31_Z0_Z1_Z2 641 +#define AArch64_Z0_Z1_Z2 642 +#define AArch64_Z1_Z2_Z3 643 +#define AArch64_Z2_Z3_Z4 644 +#define AArch64_Z3_Z4_Z5 645 +#define AArch64_Z4_Z5_Z6 646 +#define AArch64_Z5_Z6_Z7 647 +#define AArch64_Z6_Z7_Z8 648 +#define AArch64_Z7_Z8_Z9 649 +#define AArch64_Z8_Z9_Z10 650 +#define AArch64_Z9_Z10_Z11 651 +#define AArch64_Z10_Z11_Z12 652 +#define AArch64_Z11_Z12_Z13 653 +#define AArch64_Z12_Z13_Z14 654 +#define AArch64_Z13_Z14_Z15 655 +#define AArch64_Z14_Z15_Z16 656 +#define AArch64_Z15_Z16_Z17 657 +#define AArch64_Z16_Z17_Z18 658 +#define AArch64_Z17_Z18_Z19 659 +#define AArch64_Z18_Z19_Z20 660 +#define AArch64_Z19_Z20_Z21 661 +#define AArch64_Z20_Z21_Z22 662 +#define AArch64_Z21_Z22_Z23 663 +#define AArch64_Z22_Z23_Z24 664 +#define AArch64_Z23_Z24_Z25 665 +#define AArch64_Z24_Z25_Z26 666 +#define AArch64_Z25_Z26_Z27 667 +#define AArch64_Z26_Z27_Z28 668 +#define AArch64_Z27_Z28_Z29 669 +#define AArch64_Z28_Z29_Z30 670 +#define AArch64_Z29_Z30_Z31 671 +#define AArch64_Z30_Z31_Z0 672 +#define AArch64_Z31_Z0_Z1 673 +#define AArch64_NUM_TARGET_REGS 674 + +// Register classes + +#define AArch64_FPR8RegClassID 0 +#define AArch64_FPR16RegClassID 1 +#define AArch64_FPR16_loRegClassID 2 +#define AArch64_PPRRegClassID 3 +#define AArch64_PPR_3bRegClassID 4 +#define AArch64_GPR32allRegClassID 5 +#define AArch64_FPR32RegClassID 6 +#define AArch64_GPR32RegClassID 7 +#define AArch64_GPR32spRegClassID 8 +#define AArch64_GPR32commonRegClassID 9 +#define AArch64_FPR32_with_hsub_in_FPR16_loRegClassID 10 +#define AArch64_GPR32argRegClassID 11 +#define AArch64_MatrixIndexGPR32_12_15RegClassID 12 +#define AArch64_CCRRegClassID 13 +#define AArch64_GPR32sponlyRegClassID 14 +#define AArch64_WSeqPairsClassRegClassID 15 +#define AArch64_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID 16 +#define AArch64_WSeqPairsClass_with_sube32_in_GPR32argRegClassID 17 +#define AArch64_WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID \ + 18 +#define AArch64_GPR64allRegClassID 19 +#define AArch64_FPR64RegClassID 20 +#define AArch64_GPR64RegClassID 21 +#define AArch64_GPR64spRegClassID 22 +#define AArch64_GPR64commonRegClassID 23 +#define AArch64_GPR64noipRegClassID 24 +#define AArch64_GPR64common_and_GPR64noipRegClassID 25 +#define AArch64_tcGPR64RegClassID 26 +#define AArch64_GPR64noip_and_tcGPR64RegClassID 27 +#define AArch64_FPR64_loRegClassID 28 +#define AArch64_GPR64argRegClassID 29 +#define AArch64_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID 30 +#define AArch64_rtcGPR64RegClassID 31 +#define AArch64_GPR64sponlyRegClassID 32 +#define AArch64_DDRegClassID 33 +#define AArch64_DD_with_dsub0_in_FPR64_loRegClassID 34 +#define AArch64_DD_with_dsub1_in_FPR64_loRegClassID 35 +#define AArch64_XSeqPairsClassRegClassID 36 +#define AArch64_DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID \ + 37 +#define AArch64_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID 38 +#define AArch64_XSeqPairsClass_with_subo64_in_GPR64noipRegClassID 39 +#define AArch64_XSeqPairsClass_with_sube64_in_GPR64noipRegClassID 40 +#define AArch64_XSeqPairsClass_with_sube64_in_tcGPR64RegClassID 41 +#define AArch64_XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID 42 +#define AArch64_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID 43 +#define AArch64_XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID 44 +#define AArch64_XSeqPairsClass_with_sub_32_in_GPR32argRegClassID 45 +#define AArch64_XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID \ + 46 +#define AArch64_XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID 47 +#define AArch64_FPR128RegClassID 48 +#define AArch64_ZPRRegClassID 49 +#define AArch64_FPR128_loRegClassID 50 +#define AArch64_MPR128RegClassID 51 +#define AArch64_ZPR_4bRegClassID 52 +#define AArch64_ZPR_3bRegClassID 53 +#define AArch64_DDDRegClassID 54 +#define AArch64_DDD_with_dsub0_in_FPR64_loRegClassID 55 +#define AArch64_DDD_with_dsub1_in_FPR64_loRegClassID 56 +#define AArch64_DDD_with_dsub2_in_FPR64_loRegClassID 57 +#define AArch64_DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID \ + 58 +#define AArch64_DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID \ + 59 +#define AArch64_DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID \ + 60 +#define AArch64_DDDDRegClassID 61 +#define AArch64_DDDD_with_dsub0_in_FPR64_loRegClassID 62 +#define AArch64_DDDD_with_dsub1_in_FPR64_loRegClassID 63 +#define AArch64_DDDD_with_dsub2_in_FPR64_loRegClassID 64 +#define AArch64_DDDD_with_dsub3_in_FPR64_loRegClassID 65 +#define AArch64_DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID \ + 66 +#define AArch64_DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID \ + 67 +#define AArch64_DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID \ + 68 +#define AArch64_DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID \ + 69 +#define AArch64_DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID \ + 70 +#define AArch64_DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID \ + 71 +#define AArch64_QQRegClassID 72 +#define AArch64_ZPR2RegClassID 73 +#define AArch64_QQ_with_dsub_in_FPR64_loRegClassID 74 +#define AArch64_QQ_with_qsub1_in_FPR128_loRegClassID 75 +#define AArch64_ZPR2_with_dsub_in_FPR64_loRegClassID 76 +#define AArch64_ZPR2_with_zsub1_in_ZPR_4bRegClassID 77 +#define AArch64_QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID \ + 78 +#define AArch64_ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID \ + 79 +#define AArch64_ZPR2_with_zsub0_in_ZPR_3bRegClassID 80 +#define AArch64_ZPR2_with_zsub1_in_ZPR_3bRegClassID 81 +#define AArch64_ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID \ + 82 +#define AArch64_MPR64RegClassID 83 +#define AArch64_QQQRegClassID 84 +#define AArch64_ZPR3RegClassID 85 +#define AArch64_QQQ_with_dsub_in_FPR64_loRegClassID 86 +#define AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID 87 +#define AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID 88 +#define AArch64_ZPR3_with_dsub_in_FPR64_loRegClassID 89 +#define AArch64_ZPR3_with_zsub1_in_ZPR_4bRegClassID 90 +#define AArch64_ZPR3_with_zsub2_in_ZPR_4bRegClassID 91 +#define AArch64_QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID \ + 92 +#define AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID \ + 93 +#define AArch64_ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID \ + 94 +#define AArch64_ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID \ + 95 +#define AArch64_QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID \ + 96 +#define AArch64_ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID \ + 97 +#define AArch64_ZPR3_with_zsub0_in_ZPR_3bRegClassID 98 +#define AArch64_ZPR3_with_zsub1_in_ZPR_3bRegClassID 99 +#define AArch64_ZPR3_with_zsub2_in_ZPR_3bRegClassID 100 +#define AArch64_ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID \ + 101 +#define AArch64_ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID \ + 102 +#define AArch64_ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID \ + 103 +#define AArch64_QQQQRegClassID 104 +#define AArch64_ZPR4RegClassID 105 +#define AArch64_QQQQ_with_dsub_in_FPR64_loRegClassID 106 +#define AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID 107 +#define AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID 108 +#define AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID 109 +#define AArch64_ZPR4_with_dsub_in_FPR64_loRegClassID 110 +#define AArch64_ZPR4_with_zsub1_in_ZPR_4bRegClassID 111 +#define AArch64_ZPR4_with_zsub2_in_ZPR_4bRegClassID 112 +#define AArch64_ZPR4_with_zsub3_in_ZPR_4bRegClassID 113 +#define AArch64_QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID \ + 114 +#define AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID \ + 115 +#define AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID \ + 116 +#define AArch64_ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID \ + 117 +#define AArch64_ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID \ + 118 +#define AArch64_ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID \ + 119 +#define AArch64_QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID \ + 120 +#define AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID \ + 121 +#define AArch64_ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID \ + 122 +#define AArch64_ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID \ + 123 +#define AArch64_QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID \ + 124 +#define AArch64_ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID \ + 125 +#define AArch64_ZPR4_with_zsub0_in_ZPR_3bRegClassID 126 +#define AArch64_ZPR4_with_zsub1_in_ZPR_3bRegClassID 127 +#define AArch64_ZPR4_with_zsub2_in_ZPR_3bRegClassID 128 +#define AArch64_ZPR4_with_zsub3_in_ZPR_3bRegClassID 129 +#define AArch64_ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID \ + 130 +#define AArch64_ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID \ + 131 +#define AArch64_ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID \ + 132 +#define AArch64_ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID \ + 133 +#define AArch64_ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID \ + 134 +#define AArch64_ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID \ + 135 +#define AArch64_GPR64x8ClassRegClassID 136 +#define AArch64_GPR64x8Class_with_x8sub_0_in_GPR64noipRegClassID 137 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID 138 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID 139 +#define AArch64_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID 140 +#define AArch64_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID \ + 141 +#define AArch64_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID \ + 142 +#define AArch64_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 143 +#define AArch64_GPR64x8Class_with_x8sub_0_in_tcGPR64RegClassID 144 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID \ + 145 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 146 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 147 +#define AArch64_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClassID 148 +#define AArch64_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID \ + 149 +#define AArch64_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID \ + 150 +#define AArch64_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 151 +#define AArch64_GPR64x8Class_with_x8sub_1_in_tcGPR64RegClassID 152 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID \ + 153 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 154 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 155 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 156 +#define AArch64_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID \ + 157 +#define AArch64_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID \ + 158 +#define AArch64_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 159 +#define AArch64_GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClassID 160 +#define AArch64_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID \ + 161 +#define AArch64_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 162 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID \ + 163 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 164 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClassID 165 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 166 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 167 +#define AArch64_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 168 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID \ + 169 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 170 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID \ + 171 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 172 +#define AArch64_GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClassID 173 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 174 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 175 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 176 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClassID 177 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 178 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 179 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 180 +#define AArch64_GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClassID 181 +#define AArch64_GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClassID 182 +#define AArch64_GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClassID 183 +#define AArch64_GPR64x8Class_with_sub_32_in_GPR32argRegClassID 184 +#define AArch64_MPR32RegClassID 185 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64argRegClassID 186 +#define AArch64_GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID 187 +#define AArch64_GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID \ + 188 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID \ + 189 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64argRegClassID 190 +#define AArch64_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID \ + 191 +#define AArch64_GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID \ + 192 +#define AArch64_GPR64x8Class_with_x8sub_0_in_rtcGPR64RegClassID 193 +#define AArch64_GPR64x8Class_with_x8sub_2_in_rtcGPR64RegClassID 194 +#define AArch64_GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID \ + 195 +#define AArch64_GPR64x8Class_with_x8sub_4_in_rtcGPR64RegClassID 196 +#define AArch64_GPR64x8Class_with_x8sub_6_in_GPR64argRegClassID 197 +#define AArch64_GPR64x8Class_with_x8sub_6_in_rtcGPR64RegClassID 198 +#define AArch64_MPR16RegClassID 199 +#define AArch64_MPRRegClassID 200 +#define AArch64_MPR8RegClassID 201 + +#endif // GET_REGINFO_ENUM + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +#define AArch64_PHI 0 +#define AArch64_INLINEASM 1 +#define AArch64_INLINEASM_BR 2 +#define AArch64_CFI_INSTRUCTION 3 +#define AArch64_EH_LABEL 4 +#define AArch64_GC_LABEL 5 +#define AArch64_ANNOTATION_LABEL 6 +#define AArch64_KILL 7 +#define AArch64_EXTRACT_SUBREG 8 +#define AArch64_INSERT_SUBREG 9 +#define AArch64_IMPLICIT_DEF 10 +#define AArch64_SUBREG_TO_REG 11 +#define AArch64_COPY_TO_REGCLASS 12 +#define AArch64_DBG_VALUE 13 +#define AArch64_DBG_VALUE_LIST 14 +#define AArch64_DBG_INSTR_REF 15 +#define AArch64_DBG_PHI 16 +#define AArch64_DBG_LABEL 17 +#define AArch64_REG_SEQUENCE 18 +#define AArch64_COPY 19 +#define AArch64_BUNDLE 20 +#define AArch64_LIFETIME_START 21 +#define AArch64_LIFETIME_END 22 +#define AArch64_PSEUDO_PROBE 23 +#define AArch64_ARITH_FENCE 24 +#define AArch64_STACKMAP 25 +#define AArch64_FENTRY_CALL 26 +#define AArch64_PATCHPOINT 27 +#define AArch64_LOAD_STACK_GUARD 28 +#define AArch64_PREALLOCATED_SETUP 29 +#define AArch64_PREALLOCATED_ARG 30 +#define AArch64_STATEPOINT 31 +#define AArch64_LOCAL_ESCAPE 32 +#define AArch64_FAULTING_OP 33 +#define AArch64_PATCHABLE_OP 34 +#define AArch64_PATCHABLE_FUNCTION_ENTER 35 +#define AArch64_PATCHABLE_RET 36 +#define AArch64_PATCHABLE_FUNCTION_EXIT 37 +#define AArch64_PATCHABLE_TAIL_CALL 38 +#define AArch64_PATCHABLE_EVENT_CALL 39 +#define AArch64_PATCHABLE_TYPED_EVENT_CALL 40 +#define AArch64_ICALL_BRANCH_FUNNEL 41 +#define AArch64_G_ASSERT_SEXT 42 +#define AArch64_G_ASSERT_ZEXT 43 +#define AArch64_G_ADD 44 +#define AArch64_G_SUB 45 +#define AArch64_G_MUL 46 +#define AArch64_G_SDIV 47 +#define AArch64_G_UDIV 48 +#define AArch64_G_SREM 49 +#define AArch64_G_UREM 50 +#define AArch64_G_SDIVREM 51 +#define AArch64_G_UDIVREM 52 +#define AArch64_G_AND 53 +#define AArch64_G_OR 54 +#define AArch64_G_XOR 55 +#define AArch64_G_IMPLICIT_DEF 56 +#define AArch64_G_PHI 57 +#define AArch64_G_FRAME_INDEX 58 +#define AArch64_G_GLOBAL_VALUE 59 +#define AArch64_G_EXTRACT 60 +#define AArch64_G_UNMERGE_VALUES 61 +#define AArch64_G_INSERT 62 +#define AArch64_G_MERGE_VALUES 63 +#define AArch64_G_BUILD_VECTOR 64 +#define AArch64_G_BUILD_VECTOR_TRUNC 65 +#define AArch64_G_CONCAT_VECTORS 66 +#define AArch64_G_PTRTOINT 67 +#define AArch64_G_INTTOPTR 68 +#define AArch64_G_BITCAST 69 +#define AArch64_G_FREEZE 70 +#define AArch64_G_INTRINSIC_TRUNC 71 +#define AArch64_G_INTRINSIC_ROUND 72 +#define AArch64_G_INTRINSIC_LRINT 73 +#define AArch64_G_INTRINSIC_ROUNDEVEN 74 +#define AArch64_G_READCYCLECOUNTER 75 +#define AArch64_G_LOAD 76 +#define AArch64_G_SEXTLOAD 77 +#define AArch64_G_ZEXTLOAD 78 +#define AArch64_G_INDEXED_LOAD 79 +#define AArch64_G_INDEXED_SEXTLOAD 80 +#define AArch64_G_INDEXED_ZEXTLOAD 81 +#define AArch64_G_STORE 82 +#define AArch64_G_INDEXED_STORE 83 +#define AArch64_G_ATOMIC_CMPXCHG_WITH_SUCCESS 84 +#define AArch64_G_ATOMIC_CMPXCHG 85 +#define AArch64_G_ATOMICRMW_XCHG 86 +#define AArch64_G_ATOMICRMW_ADD 87 +#define AArch64_G_ATOMICRMW_SUB 88 +#define AArch64_G_ATOMICRMW_AND 89 +#define AArch64_G_ATOMICRMW_NAND 90 +#define AArch64_G_ATOMICRMW_OR 91 +#define AArch64_G_ATOMICRMW_XOR 92 +#define AArch64_G_ATOMICRMW_MAX 93 +#define AArch64_G_ATOMICRMW_MIN 94 +#define AArch64_G_ATOMICRMW_UMAX 95 +#define AArch64_G_ATOMICRMW_UMIN 96 +#define AArch64_G_ATOMICRMW_FADD 97 +#define AArch64_G_ATOMICRMW_FSUB 98 +#define AArch64_G_FENCE 99 +#define AArch64_G_BRCOND 100 +#define AArch64_G_BRINDIRECT 101 +#define AArch64_G_INTRINSIC 102 +#define AArch64_G_INTRINSIC_W_SIDE_EFFECTS 103 +#define AArch64_G_ANYEXT 104 +#define AArch64_G_TRUNC 105 +#define AArch64_G_CONSTANT 106 +#define AArch64_G_FCONSTANT 107 +#define AArch64_G_VASTART 108 +#define AArch64_G_VAARG 109 +#define AArch64_G_SEXT 110 +#define AArch64_G_SEXT_INREG 111 +#define AArch64_G_ZEXT 112 +#define AArch64_G_SHL 113 +#define AArch64_G_LSHR 114 +#define AArch64_G_ASHR 115 +#define AArch64_G_FSHL 116 +#define AArch64_G_FSHR 117 +#define AArch64_G_ROTR 118 +#define AArch64_G_ROTL 119 +#define AArch64_G_ICMP 120 +#define AArch64_G_FCMP 121 +#define AArch64_G_SELECT 122 +#define AArch64_G_UADDO 123 +#define AArch64_G_UADDE 124 +#define AArch64_G_USUBO 125 +#define AArch64_G_USUBE 126 +#define AArch64_G_SADDO 127 +#define AArch64_G_SADDE 128 +#define AArch64_G_SSUBO 129 +#define AArch64_G_SSUBE 130 +#define AArch64_G_UMULO 131 +#define AArch64_G_SMULO 132 +#define AArch64_G_UMULH 133 +#define AArch64_G_SMULH 134 +#define AArch64_G_UADDSAT 135 +#define AArch64_G_SADDSAT 136 +#define AArch64_G_USUBSAT 137 +#define AArch64_G_SSUBSAT 138 +#define AArch64_G_USHLSAT 139 +#define AArch64_G_SSHLSAT 140 +#define AArch64_G_SMULFIX 141 +#define AArch64_G_UMULFIX 142 +#define AArch64_G_SMULFIXSAT 143 +#define AArch64_G_UMULFIXSAT 144 +#define AArch64_G_SDIVFIX 145 +#define AArch64_G_UDIVFIX 146 +#define AArch64_G_SDIVFIXSAT 147 +#define AArch64_G_UDIVFIXSAT 148 +#define AArch64_G_FADD 149 +#define AArch64_G_FSUB 150 +#define AArch64_G_FMUL 151 +#define AArch64_G_FMA 152 +#define AArch64_G_FMAD 153 +#define AArch64_G_FDIV 154 +#define AArch64_G_FREM 155 +#define AArch64_G_FPOW 156 +#define AArch64_G_FPOWI 157 +#define AArch64_G_FEXP 158 +#define AArch64_G_FEXP2 159 +#define AArch64_G_FLOG 160 +#define AArch64_G_FLOG2 161 +#define AArch64_G_FLOG10 162 +#define AArch64_G_FNEG 163 +#define AArch64_G_FPEXT 164 +#define AArch64_G_FPTRUNC 165 +#define AArch64_G_FPTOSI 166 +#define AArch64_G_FPTOUI 167 +#define AArch64_G_SITOFP 168 +#define AArch64_G_UITOFP 169 +#define AArch64_G_FABS 170 +#define AArch64_G_FCOPYSIGN 171 +#define AArch64_G_FCANONICALIZE 172 +#define AArch64_G_FMINNUM 173 +#define AArch64_G_FMAXNUM 174 +#define AArch64_G_FMINNUM_IEEE 175 +#define AArch64_G_FMAXNUM_IEEE 176 +#define AArch64_G_FMINIMUM 177 +#define AArch64_G_FMAXIMUM 178 +#define AArch64_G_PTR_ADD 179 +#define AArch64_G_PTRMASK 180 +#define AArch64_G_SMIN 181 +#define AArch64_G_SMAX 182 +#define AArch64_G_UMIN 183 +#define AArch64_G_UMAX 184 +#define AArch64_G_ABS 185 +#define AArch64_G_LROUND 186 +#define AArch64_G_LLROUND 187 +#define AArch64_G_BR 188 +#define AArch64_G_BRJT 189 +#define AArch64_G_INSERT_VECTOR_ELT 190 +#define AArch64_G_EXTRACT_VECTOR_ELT 191 +#define AArch64_G_SHUFFLE_VECTOR 192 +#define AArch64_G_CTTZ 193 +#define AArch64_G_CTTZ_ZERO_UNDEF 194 +#define AArch64_G_CTLZ 195 +#define AArch64_G_CTLZ_ZERO_UNDEF 196 +#define AArch64_G_CTPOP 197 +#define AArch64_G_BSWAP 198 +#define AArch64_G_BITREVERSE 199 +#define AArch64_G_FCEIL 200 +#define AArch64_G_FCOS 201 +#define AArch64_G_FSIN 202 +#define AArch64_G_FSQRT 203 +#define AArch64_G_FFLOOR 204 +#define AArch64_G_FRINT 205 +#define AArch64_G_FNEARBYINT 206 +#define AArch64_G_ADDRSPACE_CAST 207 +#define AArch64_G_BLOCK_ADDR 208 +#define AArch64_G_JUMP_TABLE 209 +#define AArch64_G_DYN_STACKALLOC 210 +#define AArch64_G_STRICT_FADD 211 +#define AArch64_G_STRICT_FSUB 212 +#define AArch64_G_STRICT_FMUL 213 +#define AArch64_G_STRICT_FDIV 214 +#define AArch64_G_STRICT_FREM 215 +#define AArch64_G_STRICT_FMA 216 +#define AArch64_G_STRICT_FSQRT 217 +#define AArch64_G_READ_REGISTER 218 +#define AArch64_G_WRITE_REGISTER 219 +#define AArch64_G_MEMCPY 220 +#define AArch64_G_MEMCPY_INLINE 221 +#define AArch64_G_MEMMOVE 222 +#define AArch64_G_MEMSET 223 +#define AArch64_G_BZERO 224 +#define AArch64_G_VECREDUCE_SEQ_FADD 225 +#define AArch64_G_VECREDUCE_SEQ_FMUL 226 +#define AArch64_G_VECREDUCE_FADD 227 +#define AArch64_G_VECREDUCE_FMUL 228 +#define AArch64_G_VECREDUCE_FMAX 229 +#define AArch64_G_VECREDUCE_FMIN 230 +#define AArch64_G_VECREDUCE_ADD 231 +#define AArch64_G_VECREDUCE_MUL 232 +#define AArch64_G_VECREDUCE_AND 233 +#define AArch64_G_VECREDUCE_OR 234 +#define AArch64_G_VECREDUCE_XOR 235 +#define AArch64_G_VECREDUCE_SMAX 236 +#define AArch64_G_VECREDUCE_SMIN 237 +#define AArch64_G_VECREDUCE_UMAX 238 +#define AArch64_G_VECREDUCE_UMIN 239 +#define AArch64_G_SBFX 240 +#define AArch64_G_UBFX 241 +#define AArch64_ABS_ZPmZ_UNDEF_B 242 +#define AArch64_ABS_ZPmZ_UNDEF_D 243 +#define AArch64_ABS_ZPmZ_UNDEF_H 244 +#define AArch64_ABS_ZPmZ_UNDEF_S 245 +#define AArch64_ADDSWrr 246 +#define AArch64_ADDSXrr 247 +#define AArch64_ADDWrr 248 +#define AArch64_ADDXrr 249 +#define AArch64_ADD_ZPZZ_UNDEF_B 250 +#define AArch64_ADD_ZPZZ_UNDEF_D 251 +#define AArch64_ADD_ZPZZ_UNDEF_H 252 +#define AArch64_ADD_ZPZZ_UNDEF_S 253 +#define AArch64_ADD_ZPZZ_ZERO_B 254 +#define AArch64_ADD_ZPZZ_ZERO_D 255 +#define AArch64_ADD_ZPZZ_ZERO_H 256 +#define AArch64_ADD_ZPZZ_ZERO_S 257 +#define AArch64_ADDlowTLS 258 +#define AArch64_ADJCALLSTACKDOWN 259 +#define AArch64_ADJCALLSTACKUP 260 +#define AArch64_AESIMCrrTied 261 +#define AArch64_AESMCrrTied 262 +#define AArch64_ANDSWrr 263 +#define AArch64_ANDSXrr 264 +#define AArch64_ANDWrr 265 +#define AArch64_ANDXrr 266 +#define AArch64_ASRD_ZPZI_ZERO_B 267 +#define AArch64_ASRD_ZPZI_ZERO_D 268 +#define AArch64_ASRD_ZPZI_ZERO_H 269 +#define AArch64_ASRD_ZPZI_ZERO_S 270 +#define AArch64_ASR_ZPZI_UNDEF_B 271 +#define AArch64_ASR_ZPZI_UNDEF_D 272 +#define AArch64_ASR_ZPZI_UNDEF_H 273 +#define AArch64_ASR_ZPZI_UNDEF_S 274 +#define AArch64_ASR_ZPZZ_UNDEF_B 275 +#define AArch64_ASR_ZPZZ_UNDEF_D 276 +#define AArch64_ASR_ZPZZ_UNDEF_H 277 +#define AArch64_ASR_ZPZZ_UNDEF_S 278 +#define AArch64_ASR_ZPZZ_ZERO_B 279 +#define AArch64_ASR_ZPZZ_ZERO_D 280 +#define AArch64_ASR_ZPZZ_ZERO_H 281 +#define AArch64_ASR_ZPZZ_ZERO_S 282 +#define AArch64_BICSWrr 283 +#define AArch64_BICSXrr 284 +#define AArch64_BICWrr 285 +#define AArch64_BICXrr 286 +#define AArch64_BLRNoIP 287 +#define AArch64_BLR_RVMARKER 288 +#define AArch64_BSPv16i8 289 +#define AArch64_BSPv8i8 290 +#define AArch64_CATCHRET 291 +#define AArch64_CLEANUPRET 292 +#define AArch64_CLS_ZPmZ_UNDEF_B 293 +#define AArch64_CLS_ZPmZ_UNDEF_D 294 +#define AArch64_CLS_ZPmZ_UNDEF_H 295 +#define AArch64_CLS_ZPmZ_UNDEF_S 296 +#define AArch64_CLZ_ZPmZ_UNDEF_B 297 +#define AArch64_CLZ_ZPmZ_UNDEF_D 298 +#define AArch64_CLZ_ZPmZ_UNDEF_H 299 +#define AArch64_CLZ_ZPmZ_UNDEF_S 300 +#define AArch64_CMP_SWAP_128 301 +#define AArch64_CMP_SWAP_128_ACQUIRE 302 +#define AArch64_CMP_SWAP_128_MONOTONIC 303 +#define AArch64_CMP_SWAP_128_RELEASE 304 +#define AArch64_CMP_SWAP_16 305 +#define AArch64_CMP_SWAP_32 306 +#define AArch64_CMP_SWAP_64 307 +#define AArch64_CMP_SWAP_8 308 +#define AArch64_CNOT_ZPmZ_UNDEF_B 309 +#define AArch64_CNOT_ZPmZ_UNDEF_D 310 +#define AArch64_CNOT_ZPmZ_UNDEF_H 311 +#define AArch64_CNOT_ZPmZ_UNDEF_S 312 +#define AArch64_CNT_ZPmZ_UNDEF_B 313 +#define AArch64_CNT_ZPmZ_UNDEF_D 314 +#define AArch64_CNT_ZPmZ_UNDEF_H 315 +#define AArch64_CNT_ZPmZ_UNDEF_S 316 +#define AArch64_CompilerBarrier 317 +#define AArch64_EMITBKEY 318 +#define AArch64_EONWrr 319 +#define AArch64_EONXrr 320 +#define AArch64_EORWrr 321 +#define AArch64_EORXrr 322 +#define AArch64_F128CSEL 323 +#define AArch64_FABD_ZPZZ_ZERO_D 324 +#define AArch64_FABD_ZPZZ_ZERO_H 325 +#define AArch64_FABD_ZPZZ_ZERO_S 326 +#define AArch64_FABS_ZPmZ_UNDEF_D 327 +#define AArch64_FABS_ZPmZ_UNDEF_H 328 +#define AArch64_FABS_ZPmZ_UNDEF_S 329 +#define AArch64_FADD_ZPZI_UNDEF_D 330 +#define AArch64_FADD_ZPZI_UNDEF_H 331 +#define AArch64_FADD_ZPZI_UNDEF_S 332 +#define AArch64_FADD_ZPZI_ZERO_D 333 +#define AArch64_FADD_ZPZI_ZERO_H 334 +#define AArch64_FADD_ZPZI_ZERO_S 335 +#define AArch64_FADD_ZPZZ_UNDEF_D 336 +#define AArch64_FADD_ZPZZ_UNDEF_H 337 +#define AArch64_FADD_ZPZZ_UNDEF_S 338 +#define AArch64_FADD_ZPZZ_ZERO_D 339 +#define AArch64_FADD_ZPZZ_ZERO_H 340 +#define AArch64_FADD_ZPZZ_ZERO_S 341 +#define AArch64_FDIVR_ZPZZ_ZERO_D 342 +#define AArch64_FDIVR_ZPZZ_ZERO_H 343 +#define AArch64_FDIVR_ZPZZ_ZERO_S 344 +#define AArch64_FDIV_ZPZZ_UNDEF_D 345 +#define AArch64_FDIV_ZPZZ_UNDEF_H 346 +#define AArch64_FDIV_ZPZZ_UNDEF_S 347 +#define AArch64_FDIV_ZPZZ_ZERO_D 348 +#define AArch64_FDIV_ZPZZ_ZERO_H 349 +#define AArch64_FDIV_ZPZZ_ZERO_S 350 +#define AArch64_FMAXNM_ZPZI_UNDEF_D 351 +#define AArch64_FMAXNM_ZPZI_UNDEF_H 352 +#define AArch64_FMAXNM_ZPZI_UNDEF_S 353 +#define AArch64_FMAXNM_ZPZI_ZERO_D 354 +#define AArch64_FMAXNM_ZPZI_ZERO_H 355 +#define AArch64_FMAXNM_ZPZI_ZERO_S 356 +#define AArch64_FMAXNM_ZPZZ_UNDEF_D 357 +#define AArch64_FMAXNM_ZPZZ_UNDEF_H 358 +#define AArch64_FMAXNM_ZPZZ_UNDEF_S 359 +#define AArch64_FMAXNM_ZPZZ_ZERO_D 360 +#define AArch64_FMAXNM_ZPZZ_ZERO_H 361 +#define AArch64_FMAXNM_ZPZZ_ZERO_S 362 +#define AArch64_FMAX_ZPZI_UNDEF_D 363 +#define AArch64_FMAX_ZPZI_UNDEF_H 364 +#define AArch64_FMAX_ZPZI_UNDEF_S 365 +#define AArch64_FMAX_ZPZI_ZERO_D 366 +#define AArch64_FMAX_ZPZI_ZERO_H 367 +#define AArch64_FMAX_ZPZI_ZERO_S 368 +#define AArch64_FMAX_ZPZZ_UNDEF_D 369 +#define AArch64_FMAX_ZPZZ_UNDEF_H 370 +#define AArch64_FMAX_ZPZZ_UNDEF_S 371 +#define AArch64_FMAX_ZPZZ_ZERO_D 372 +#define AArch64_FMAX_ZPZZ_ZERO_H 373 +#define AArch64_FMAX_ZPZZ_ZERO_S 374 +#define AArch64_FMINNM_ZPZI_UNDEF_D 375 +#define AArch64_FMINNM_ZPZI_UNDEF_H 376 +#define AArch64_FMINNM_ZPZI_UNDEF_S 377 +#define AArch64_FMINNM_ZPZI_ZERO_D 378 +#define AArch64_FMINNM_ZPZI_ZERO_H 379 +#define AArch64_FMINNM_ZPZI_ZERO_S 380 +#define AArch64_FMINNM_ZPZZ_UNDEF_D 381 +#define AArch64_FMINNM_ZPZZ_UNDEF_H 382 +#define AArch64_FMINNM_ZPZZ_UNDEF_S 383 +#define AArch64_FMINNM_ZPZZ_ZERO_D 384 +#define AArch64_FMINNM_ZPZZ_ZERO_H 385 +#define AArch64_FMINNM_ZPZZ_ZERO_S 386 +#define AArch64_FMIN_ZPZI_UNDEF_D 387 +#define AArch64_FMIN_ZPZI_UNDEF_H 388 +#define AArch64_FMIN_ZPZI_UNDEF_S 389 +#define AArch64_FMIN_ZPZI_ZERO_D 390 +#define AArch64_FMIN_ZPZI_ZERO_H 391 +#define AArch64_FMIN_ZPZI_ZERO_S 392 +#define AArch64_FMIN_ZPZZ_UNDEF_D 393 +#define AArch64_FMIN_ZPZZ_UNDEF_H 394 +#define AArch64_FMIN_ZPZZ_UNDEF_S 395 +#define AArch64_FMIN_ZPZZ_ZERO_D 396 +#define AArch64_FMIN_ZPZZ_ZERO_H 397 +#define AArch64_FMIN_ZPZZ_ZERO_S 398 +#define AArch64_FMLA_ZPZZZ_UNDEF_D 399 +#define AArch64_FMLA_ZPZZZ_UNDEF_H 400 +#define AArch64_FMLA_ZPZZZ_UNDEF_S 401 +#define AArch64_FMLS_ZPZZZ_UNDEF_D 402 +#define AArch64_FMLS_ZPZZZ_UNDEF_H 403 +#define AArch64_FMLS_ZPZZZ_UNDEF_S 404 +#define AArch64_FMOVD0 405 +#define AArch64_FMOVH0 406 +#define AArch64_FMOVS0 407 +#define AArch64_FMULX_ZPZZ_ZERO_D 408 +#define AArch64_FMULX_ZPZZ_ZERO_H 409 +#define AArch64_FMULX_ZPZZ_ZERO_S 410 +#define AArch64_FMUL_ZPZI_UNDEF_D 411 +#define AArch64_FMUL_ZPZI_UNDEF_H 412 +#define AArch64_FMUL_ZPZI_UNDEF_S 413 +#define AArch64_FMUL_ZPZI_ZERO_D 414 +#define AArch64_FMUL_ZPZI_ZERO_H 415 +#define AArch64_FMUL_ZPZI_ZERO_S 416 +#define AArch64_FMUL_ZPZZ_UNDEF_D 417 +#define AArch64_FMUL_ZPZZ_UNDEF_H 418 +#define AArch64_FMUL_ZPZZ_UNDEF_S 419 +#define AArch64_FMUL_ZPZZ_ZERO_D 420 +#define AArch64_FMUL_ZPZZ_ZERO_H 421 +#define AArch64_FMUL_ZPZZ_ZERO_S 422 +#define AArch64_FNEG_ZPmZ_UNDEF_D 423 +#define AArch64_FNEG_ZPmZ_UNDEF_H 424 +#define AArch64_FNEG_ZPmZ_UNDEF_S 425 +#define AArch64_FNMLA_ZPZZZ_UNDEF_D 426 +#define AArch64_FNMLA_ZPZZZ_UNDEF_H 427 +#define AArch64_FNMLA_ZPZZZ_UNDEF_S 428 +#define AArch64_FNMLS_ZPZZZ_UNDEF_D 429 +#define AArch64_FNMLS_ZPZZZ_UNDEF_H 430 +#define AArch64_FNMLS_ZPZZZ_UNDEF_S 431 +#define AArch64_FRECPX_ZPmZ_UNDEF_D 432 +#define AArch64_FRECPX_ZPmZ_UNDEF_H 433 +#define AArch64_FRECPX_ZPmZ_UNDEF_S 434 +#define AArch64_FRINTA_ZPmZ_UNDEF_D 435 +#define AArch64_FRINTA_ZPmZ_UNDEF_H 436 +#define AArch64_FRINTA_ZPmZ_UNDEF_S 437 +#define AArch64_FRINTI_ZPmZ_UNDEF_D 438 +#define AArch64_FRINTI_ZPmZ_UNDEF_H 439 +#define AArch64_FRINTI_ZPmZ_UNDEF_S 440 +#define AArch64_FRINTM_ZPmZ_UNDEF_D 441 +#define AArch64_FRINTM_ZPmZ_UNDEF_H 442 +#define AArch64_FRINTM_ZPmZ_UNDEF_S 443 +#define AArch64_FRINTN_ZPmZ_UNDEF_D 444 +#define AArch64_FRINTN_ZPmZ_UNDEF_H 445 +#define AArch64_FRINTN_ZPmZ_UNDEF_S 446 +#define AArch64_FRINTP_ZPmZ_UNDEF_D 447 +#define AArch64_FRINTP_ZPmZ_UNDEF_H 448 +#define AArch64_FRINTP_ZPmZ_UNDEF_S 449 +#define AArch64_FRINTX_ZPmZ_UNDEF_D 450 +#define AArch64_FRINTX_ZPmZ_UNDEF_H 451 +#define AArch64_FRINTX_ZPmZ_UNDEF_S 452 +#define AArch64_FRINTZ_ZPmZ_UNDEF_D 453 +#define AArch64_FRINTZ_ZPmZ_UNDEF_H 454 +#define AArch64_FRINTZ_ZPmZ_UNDEF_S 455 +#define AArch64_FSQRT_ZPmZ_UNDEF_D 456 +#define AArch64_FSQRT_ZPmZ_UNDEF_H 457 +#define AArch64_FSQRT_ZPmZ_UNDEF_S 458 +#define AArch64_FSUBR_ZPZI_UNDEF_D 459 +#define AArch64_FSUBR_ZPZI_UNDEF_H 460 +#define AArch64_FSUBR_ZPZI_UNDEF_S 461 +#define AArch64_FSUBR_ZPZI_ZERO_D 462 +#define AArch64_FSUBR_ZPZI_ZERO_H 463 +#define AArch64_FSUBR_ZPZI_ZERO_S 464 +#define AArch64_FSUBR_ZPZZ_ZERO_D 465 +#define AArch64_FSUBR_ZPZZ_ZERO_H 466 +#define AArch64_FSUBR_ZPZZ_ZERO_S 467 +#define AArch64_FSUB_ZPZI_UNDEF_D 468 +#define AArch64_FSUB_ZPZI_UNDEF_H 469 +#define AArch64_FSUB_ZPZI_UNDEF_S 470 +#define AArch64_FSUB_ZPZI_ZERO_D 471 +#define AArch64_FSUB_ZPZI_ZERO_H 472 +#define AArch64_FSUB_ZPZI_ZERO_S 473 +#define AArch64_FSUB_ZPZZ_UNDEF_D 474 +#define AArch64_FSUB_ZPZZ_UNDEF_H 475 +#define AArch64_FSUB_ZPZZ_UNDEF_S 476 +#define AArch64_FSUB_ZPZZ_ZERO_D 477 +#define AArch64_FSUB_ZPZZ_ZERO_H 478 +#define AArch64_FSUB_ZPZZ_ZERO_S 479 +#define AArch64_GLD1B_D 480 +#define AArch64_GLD1B_D_IMM 481 +#define AArch64_GLD1B_D_SXTW 482 +#define AArch64_GLD1B_D_UXTW 483 +#define AArch64_GLD1B_S_IMM 484 +#define AArch64_GLD1B_S_SXTW 485 +#define AArch64_GLD1B_S_UXTW 486 +#define AArch64_GLD1D 487 +#define AArch64_GLD1D_IMM 488 +#define AArch64_GLD1D_SCALED 489 +#define AArch64_GLD1D_SXTW 490 +#define AArch64_GLD1D_SXTW_SCALED 491 +#define AArch64_GLD1D_UXTW 492 +#define AArch64_GLD1D_UXTW_SCALED 493 +#define AArch64_GLD1H_D 494 +#define AArch64_GLD1H_D_IMM 495 +#define AArch64_GLD1H_D_SCALED 496 +#define AArch64_GLD1H_D_SXTW 497 +#define AArch64_GLD1H_D_SXTW_SCALED 498 +#define AArch64_GLD1H_D_UXTW 499 +#define AArch64_GLD1H_D_UXTW_SCALED 500 +#define AArch64_GLD1H_S_IMM 501 +#define AArch64_GLD1H_S_SXTW 502 +#define AArch64_GLD1H_S_SXTW_SCALED 503 +#define AArch64_GLD1H_S_UXTW 504 +#define AArch64_GLD1H_S_UXTW_SCALED 505 +#define AArch64_GLD1SB_D 506 +#define AArch64_GLD1SB_D_IMM 507 +#define AArch64_GLD1SB_D_SXTW 508 +#define AArch64_GLD1SB_D_UXTW 509 +#define AArch64_GLD1SB_S_IMM 510 +#define AArch64_GLD1SB_S_SXTW 511 +#define AArch64_GLD1SB_S_UXTW 512 +#define AArch64_GLD1SH_D 513 +#define AArch64_GLD1SH_D_IMM 514 +#define AArch64_GLD1SH_D_SCALED 515 +#define AArch64_GLD1SH_D_SXTW 516 +#define AArch64_GLD1SH_D_SXTW_SCALED 517 +#define AArch64_GLD1SH_D_UXTW 518 +#define AArch64_GLD1SH_D_UXTW_SCALED 519 +#define AArch64_GLD1SH_S_IMM 520 +#define AArch64_GLD1SH_S_SXTW 521 +#define AArch64_GLD1SH_S_SXTW_SCALED 522 +#define AArch64_GLD1SH_S_UXTW 523 +#define AArch64_GLD1SH_S_UXTW_SCALED 524 +#define AArch64_GLD1SW_D 525 +#define AArch64_GLD1SW_D_IMM 526 +#define AArch64_GLD1SW_D_SCALED 527 +#define AArch64_GLD1SW_D_SXTW 528 +#define AArch64_GLD1SW_D_SXTW_SCALED 529 +#define AArch64_GLD1SW_D_UXTW 530 +#define AArch64_GLD1SW_D_UXTW_SCALED 531 +#define AArch64_GLD1W_D 532 +#define AArch64_GLD1W_D_IMM 533 +#define AArch64_GLD1W_D_SCALED 534 +#define AArch64_GLD1W_D_SXTW 535 +#define AArch64_GLD1W_D_SXTW_SCALED 536 +#define AArch64_GLD1W_D_UXTW 537 +#define AArch64_GLD1W_D_UXTW_SCALED 538 +#define AArch64_GLD1W_IMM 539 +#define AArch64_GLD1W_SXTW 540 +#define AArch64_GLD1W_SXTW_SCALED 541 +#define AArch64_GLD1W_UXTW 542 +#define AArch64_GLD1W_UXTW_SCALED 543 +#define AArch64_GLDFF1B_D 544 +#define AArch64_GLDFF1B_D_IMM 545 +#define AArch64_GLDFF1B_D_SXTW 546 +#define AArch64_GLDFF1B_D_UXTW 547 +#define AArch64_GLDFF1B_S_IMM 548 +#define AArch64_GLDFF1B_S_SXTW 549 +#define AArch64_GLDFF1B_S_UXTW 550 +#define AArch64_GLDFF1D 551 +#define AArch64_GLDFF1D_IMM 552 +#define AArch64_GLDFF1D_SCALED 553 +#define AArch64_GLDFF1D_SXTW 554 +#define AArch64_GLDFF1D_SXTW_SCALED 555 +#define AArch64_GLDFF1D_UXTW 556 +#define AArch64_GLDFF1D_UXTW_SCALED 557 +#define AArch64_GLDFF1H_D 558 +#define AArch64_GLDFF1H_D_IMM 559 +#define AArch64_GLDFF1H_D_SCALED 560 +#define AArch64_GLDFF1H_D_SXTW 561 +#define AArch64_GLDFF1H_D_SXTW_SCALED 562 +#define AArch64_GLDFF1H_D_UXTW 563 +#define AArch64_GLDFF1H_D_UXTW_SCALED 564 +#define AArch64_GLDFF1H_S_IMM 565 +#define AArch64_GLDFF1H_S_SXTW 566 +#define AArch64_GLDFF1H_S_SXTW_SCALED 567 +#define AArch64_GLDFF1H_S_UXTW 568 +#define AArch64_GLDFF1H_S_UXTW_SCALED 569 +#define AArch64_GLDFF1SB_D 570 +#define AArch64_GLDFF1SB_D_IMM 571 +#define AArch64_GLDFF1SB_D_SXTW 572 +#define AArch64_GLDFF1SB_D_UXTW 573 +#define AArch64_GLDFF1SB_S_IMM 574 +#define AArch64_GLDFF1SB_S_SXTW 575 +#define AArch64_GLDFF1SB_S_UXTW 576 +#define AArch64_GLDFF1SH_D 577 +#define AArch64_GLDFF1SH_D_IMM 578 +#define AArch64_GLDFF1SH_D_SCALED 579 +#define AArch64_GLDFF1SH_D_SXTW 580 +#define AArch64_GLDFF1SH_D_SXTW_SCALED 581 +#define AArch64_GLDFF1SH_D_UXTW 582 +#define AArch64_GLDFF1SH_D_UXTW_SCALED 583 +#define AArch64_GLDFF1SH_S_IMM 584 +#define AArch64_GLDFF1SH_S_SXTW 585 +#define AArch64_GLDFF1SH_S_SXTW_SCALED 586 +#define AArch64_GLDFF1SH_S_UXTW 587 +#define AArch64_GLDFF1SH_S_UXTW_SCALED 588 +#define AArch64_GLDFF1SW_D 589 +#define AArch64_GLDFF1SW_D_IMM 590 +#define AArch64_GLDFF1SW_D_SCALED 591 +#define AArch64_GLDFF1SW_D_SXTW 592 +#define AArch64_GLDFF1SW_D_SXTW_SCALED 593 +#define AArch64_GLDFF1SW_D_UXTW 594 +#define AArch64_GLDFF1SW_D_UXTW_SCALED 595 +#define AArch64_GLDFF1W_D 596 +#define AArch64_GLDFF1W_D_IMM 597 +#define AArch64_GLDFF1W_D_SCALED 598 +#define AArch64_GLDFF1W_D_SXTW 599 +#define AArch64_GLDFF1W_D_SXTW_SCALED 600 +#define AArch64_GLDFF1W_D_UXTW 601 +#define AArch64_GLDFF1W_D_UXTW_SCALED 602 +#define AArch64_GLDFF1W_IMM 603 +#define AArch64_GLDFF1W_SXTW 604 +#define AArch64_GLDFF1W_SXTW_SCALED 605 +#define AArch64_GLDFF1W_UXTW 606 +#define AArch64_GLDFF1W_UXTW_SCALED 607 +#define AArch64_G_ADD_LOW 608 +#define AArch64_G_DUP 609 +#define AArch64_G_DUPLANE16 610 +#define AArch64_G_DUPLANE32 611 +#define AArch64_G_DUPLANE64 612 +#define AArch64_G_DUPLANE8 613 +#define AArch64_G_EXT 614 +#define AArch64_G_FCMEQ 615 +#define AArch64_G_FCMEQZ 616 +#define AArch64_G_FCMGE 617 +#define AArch64_G_FCMGEZ 618 +#define AArch64_G_FCMGT 619 +#define AArch64_G_FCMGTZ 620 +#define AArch64_G_FCMLEZ 621 +#define AArch64_G_FCMLTZ 622 +#define AArch64_G_REV16 623 +#define AArch64_G_REV32 624 +#define AArch64_G_REV64 625 +#define AArch64_G_SITOF 626 +#define AArch64_G_TRN1 627 +#define AArch64_G_TRN2 628 +#define AArch64_G_UITOF 629 +#define AArch64_G_UZP1 630 +#define AArch64_G_UZP2 631 +#define AArch64_G_VASHR 632 +#define AArch64_G_VLSHR 633 +#define AArch64_G_ZIP1 634 +#define AArch64_G_ZIP2 635 +#define AArch64_HOM_Epilog 636 +#define AArch64_HOM_Prolog 637 +#define AArch64_HWASAN_CHECK_MEMACCESS 638 +#define AArch64_HWASAN_CHECK_MEMACCESS_SHORTGRANULES 639 +#define AArch64_IRGstack 640 +#define AArch64_JumpTableDest16 641 +#define AArch64_JumpTableDest32 642 +#define AArch64_JumpTableDest8 643 +#define AArch64_LD1B_D_IMM 644 +#define AArch64_LD1B_H_IMM 645 +#define AArch64_LD1B_IMM 646 +#define AArch64_LD1B_S_IMM 647 +#define AArch64_LD1D_IMM 648 +#define AArch64_LD1H_D_IMM 649 +#define AArch64_LD1H_IMM 650 +#define AArch64_LD1H_S_IMM 651 +#define AArch64_LD1SB_D_IMM 652 +#define AArch64_LD1SB_H_IMM 653 +#define AArch64_LD1SB_S_IMM 654 +#define AArch64_LD1SH_D_IMM 655 +#define AArch64_LD1SH_S_IMM 656 +#define AArch64_LD1SW_D_IMM 657 +#define AArch64_LD1W_D_IMM 658 +#define AArch64_LD1W_IMM 659 +#define AArch64_LDFF1B 660 +#define AArch64_LDFF1B_D 661 +#define AArch64_LDFF1B_H 662 +#define AArch64_LDFF1B_S 663 +#define AArch64_LDFF1D 664 +#define AArch64_LDFF1H 665 +#define AArch64_LDFF1H_D 666 +#define AArch64_LDFF1H_S 667 +#define AArch64_LDFF1SB_D 668 +#define AArch64_LDFF1SB_H 669 +#define AArch64_LDFF1SB_S 670 +#define AArch64_LDFF1SH_D 671 +#define AArch64_LDFF1SH_S 672 +#define AArch64_LDFF1SW_D 673 +#define AArch64_LDFF1W 674 +#define AArch64_LDFF1W_D 675 +#define AArch64_LDNF1B_D_IMM 676 +#define AArch64_LDNF1B_H_IMM 677 +#define AArch64_LDNF1B_IMM 678 +#define AArch64_LDNF1B_S_IMM 679 +#define AArch64_LDNF1D_IMM 680 +#define AArch64_LDNF1H_D_IMM 681 +#define AArch64_LDNF1H_IMM 682 +#define AArch64_LDNF1H_S_IMM 683 +#define AArch64_LDNF1SB_D_IMM 684 +#define AArch64_LDNF1SB_H_IMM 685 +#define AArch64_LDNF1SB_S_IMM 686 +#define AArch64_LDNF1SH_D_IMM 687 +#define AArch64_LDNF1SH_S_IMM 688 +#define AArch64_LDNF1SW_D_IMM 689 +#define AArch64_LDNF1W_D_IMM 690 +#define AArch64_LDNF1W_IMM 691 +#define AArch64_LDR_ZZXI 692 +#define AArch64_LDR_ZZZXI 693 +#define AArch64_LDR_ZZZZXI 694 +#define AArch64_LOADgot 695 +#define AArch64_LSL_ZPZI_UNDEF_B 696 +#define AArch64_LSL_ZPZI_UNDEF_D 697 +#define AArch64_LSL_ZPZI_UNDEF_H 698 +#define AArch64_LSL_ZPZI_UNDEF_S 699 +#define AArch64_LSL_ZPZZ_UNDEF_B 700 +#define AArch64_LSL_ZPZZ_UNDEF_D 701 +#define AArch64_LSL_ZPZZ_UNDEF_H 702 +#define AArch64_LSL_ZPZZ_UNDEF_S 703 +#define AArch64_LSL_ZPZZ_ZERO_B 704 +#define AArch64_LSL_ZPZZ_ZERO_D 705 +#define AArch64_LSL_ZPZZ_ZERO_H 706 +#define AArch64_LSL_ZPZZ_ZERO_S 707 +#define AArch64_LSR_ZPZI_UNDEF_B 708 +#define AArch64_LSR_ZPZI_UNDEF_D 709 +#define AArch64_LSR_ZPZI_UNDEF_H 710 +#define AArch64_LSR_ZPZI_UNDEF_S 711 +#define AArch64_LSR_ZPZZ_UNDEF_B 712 +#define AArch64_LSR_ZPZZ_UNDEF_D 713 +#define AArch64_LSR_ZPZZ_UNDEF_H 714 +#define AArch64_LSR_ZPZZ_UNDEF_S 715 +#define AArch64_LSR_ZPZZ_ZERO_B 716 +#define AArch64_LSR_ZPZZ_ZERO_D 717 +#define AArch64_LSR_ZPZZ_ZERO_H 718 +#define AArch64_LSR_ZPZZ_ZERO_S 719 +#define AArch64_MOVMCSym 720 +#define AArch64_MOVaddr 721 +#define AArch64_MOVaddrBA 722 +#define AArch64_MOVaddrCP 723 +#define AArch64_MOVaddrEXT 724 +#define AArch64_MOVaddrJT 725 +#define AArch64_MOVaddrTLS 726 +#define AArch64_MOVbaseTLS 727 +#define AArch64_MOVi32imm 728 +#define AArch64_MOVi64imm 729 +#define AArch64_MUL_ZPZZ_UNDEF_B 730 +#define AArch64_MUL_ZPZZ_UNDEF_D 731 +#define AArch64_MUL_ZPZZ_UNDEF_H 732 +#define AArch64_MUL_ZPZZ_UNDEF_S 733 +#define AArch64_NEG_ZPmZ_UNDEF_B 734 +#define AArch64_NEG_ZPmZ_UNDEF_D 735 +#define AArch64_NEG_ZPmZ_UNDEF_H 736 +#define AArch64_NEG_ZPmZ_UNDEF_S 737 +#define AArch64_NOT_ZPmZ_UNDEF_B 738 +#define AArch64_NOT_ZPmZ_UNDEF_D 739 +#define AArch64_NOT_ZPmZ_UNDEF_H 740 +#define AArch64_NOT_ZPmZ_UNDEF_S 741 +#define AArch64_ORNWrr 742 +#define AArch64_ORNXrr 743 +#define AArch64_ORRWrr 744 +#define AArch64_ORRXrr 745 +#define AArch64_RDFFR_P 746 +#define AArch64_RDFFR_PPz 747 +#define AArch64_RET_ReallyLR 748 +#define AArch64_SDIV_ZPZZ_UNDEF_D 749 +#define AArch64_SDIV_ZPZZ_UNDEF_S 750 +#define AArch64_SEH_AddFP 751 +#define AArch64_SEH_EpilogEnd 752 +#define AArch64_SEH_EpilogStart 753 +#define AArch64_SEH_Nop 754 +#define AArch64_SEH_PrologEnd 755 +#define AArch64_SEH_SaveFPLR 756 +#define AArch64_SEH_SaveFPLR_X 757 +#define AArch64_SEH_SaveFReg 758 +#define AArch64_SEH_SaveFRegP 759 +#define AArch64_SEH_SaveFRegP_X 760 +#define AArch64_SEH_SaveFReg_X 761 +#define AArch64_SEH_SaveReg 762 +#define AArch64_SEH_SaveRegP 763 +#define AArch64_SEH_SaveRegP_X 764 +#define AArch64_SEH_SaveReg_X 765 +#define AArch64_SEH_SetFP 766 +#define AArch64_SEH_StackAlloc 767 +#define AArch64_SMAX_ZPZZ_UNDEF_B 768 +#define AArch64_SMAX_ZPZZ_UNDEF_D 769 +#define AArch64_SMAX_ZPZZ_UNDEF_H 770 +#define AArch64_SMAX_ZPZZ_UNDEF_S 771 +#define AArch64_SMIN_ZPZZ_UNDEF_B 772 +#define AArch64_SMIN_ZPZZ_UNDEF_D 773 +#define AArch64_SMIN_ZPZZ_UNDEF_H 774 +#define AArch64_SMIN_ZPZZ_UNDEF_S 775 +#define AArch64_SMULH_ZPZZ_UNDEF_B 776 +#define AArch64_SMULH_ZPZZ_UNDEF_D 777 +#define AArch64_SMULH_ZPZZ_UNDEF_H 778 +#define AArch64_SMULH_ZPZZ_UNDEF_S 779 +#define AArch64_SPACE 780 +#define AArch64_SQABS_ZPmZ_UNDEF_B 781 +#define AArch64_SQABS_ZPmZ_UNDEF_D 782 +#define AArch64_SQABS_ZPmZ_UNDEF_H 783 +#define AArch64_SQABS_ZPmZ_UNDEF_S 784 +#define AArch64_SQNEG_ZPmZ_UNDEF_B 785 +#define AArch64_SQNEG_ZPmZ_UNDEF_D 786 +#define AArch64_SQNEG_ZPmZ_UNDEF_H 787 +#define AArch64_SQNEG_ZPmZ_UNDEF_S 788 +#define AArch64_SQRSHL_ZPZZ_UNDEF_B 789 +#define AArch64_SQRSHL_ZPZZ_UNDEF_D 790 +#define AArch64_SQRSHL_ZPZZ_UNDEF_H 791 +#define AArch64_SQRSHL_ZPZZ_UNDEF_S 792 +#define AArch64_SQSHLU_ZPZI_ZERO_B 793 +#define AArch64_SQSHLU_ZPZI_ZERO_D 794 +#define AArch64_SQSHLU_ZPZI_ZERO_H 795 +#define AArch64_SQSHLU_ZPZI_ZERO_S 796 +#define AArch64_SQSHL_ZPZI_ZERO_B 797 +#define AArch64_SQSHL_ZPZI_ZERO_D 798 +#define AArch64_SQSHL_ZPZI_ZERO_H 799 +#define AArch64_SQSHL_ZPZI_ZERO_S 800 +#define AArch64_SQSHL_ZPZZ_UNDEF_B 801 +#define AArch64_SQSHL_ZPZZ_UNDEF_D 802 +#define AArch64_SQSHL_ZPZZ_UNDEF_H 803 +#define AArch64_SQSHL_ZPZZ_UNDEF_S 804 +#define AArch64_SRSHL_ZPZZ_UNDEF_B 805 +#define AArch64_SRSHL_ZPZZ_UNDEF_D 806 +#define AArch64_SRSHL_ZPZZ_UNDEF_H 807 +#define AArch64_SRSHL_ZPZZ_UNDEF_S 808 +#define AArch64_SRSHR_ZPZI_ZERO_B 809 +#define AArch64_SRSHR_ZPZI_ZERO_D 810 +#define AArch64_SRSHR_ZPZI_ZERO_H 811 +#define AArch64_SRSHR_ZPZI_ZERO_S 812 +#define AArch64_STGloop 813 +#define AArch64_STGloop_wback 814 +#define AArch64_STR_ZZXI 815 +#define AArch64_STR_ZZZXI 816 +#define AArch64_STR_ZZZZXI 817 +#define AArch64_STZGloop 818 +#define AArch64_STZGloop_wback 819 +#define AArch64_SUBR_ZPZZ_ZERO_B 820 +#define AArch64_SUBR_ZPZZ_ZERO_D 821 +#define AArch64_SUBR_ZPZZ_ZERO_H 822 +#define AArch64_SUBR_ZPZZ_ZERO_S 823 +#define AArch64_SUBSWrr 824 +#define AArch64_SUBSXrr 825 +#define AArch64_SUBWrr 826 +#define AArch64_SUBXrr 827 +#define AArch64_SUB_ZPZZ_UNDEF_B 828 +#define AArch64_SUB_ZPZZ_UNDEF_D 829 +#define AArch64_SUB_ZPZZ_UNDEF_H 830 +#define AArch64_SUB_ZPZZ_UNDEF_S 831 +#define AArch64_SUB_ZPZZ_ZERO_B 832 +#define AArch64_SUB_ZPZZ_ZERO_D 833 +#define AArch64_SUB_ZPZZ_ZERO_H 834 +#define AArch64_SUB_ZPZZ_ZERO_S 835 +#define AArch64_SXTB_ZPmZ_UNDEF_D 836 +#define AArch64_SXTB_ZPmZ_UNDEF_H 837 +#define AArch64_SXTB_ZPmZ_UNDEF_S 838 +#define AArch64_SXTH_ZPmZ_UNDEF_D 839 +#define AArch64_SXTH_ZPmZ_UNDEF_S 840 +#define AArch64_SXTW_ZPmZ_UNDEF_D 841 +#define AArch64_SpeculationBarrierISBDSBEndBB 842 +#define AArch64_SpeculationBarrierSBEndBB 843 +#define AArch64_SpeculationSafeValueW 844 +#define AArch64_SpeculationSafeValueX 845 +#define AArch64_StoreSwiftAsyncContext 846 +#define AArch64_TAGPstack 847 +#define AArch64_TCRETURNdi 848 +#define AArch64_TCRETURNri 849 +#define AArch64_TCRETURNriALL 850 +#define AArch64_TCRETURNriBTI 851 +#define AArch64_TLSDESCCALL 852 +#define AArch64_TLSDESC_CALLSEQ 853 +#define AArch64_UDIV_ZPZZ_UNDEF_D 854 +#define AArch64_UDIV_ZPZZ_UNDEF_S 855 +#define AArch64_UMAX_ZPZZ_UNDEF_B 856 +#define AArch64_UMAX_ZPZZ_UNDEF_D 857 +#define AArch64_UMAX_ZPZZ_UNDEF_H 858 +#define AArch64_UMAX_ZPZZ_UNDEF_S 859 +#define AArch64_UMIN_ZPZZ_UNDEF_B 860 +#define AArch64_UMIN_ZPZZ_UNDEF_D 861 +#define AArch64_UMIN_ZPZZ_UNDEF_H 862 +#define AArch64_UMIN_ZPZZ_UNDEF_S 863 +#define AArch64_UMULH_ZPZZ_UNDEF_B 864 +#define AArch64_UMULH_ZPZZ_UNDEF_D 865 +#define AArch64_UMULH_ZPZZ_UNDEF_H 866 +#define AArch64_UMULH_ZPZZ_UNDEF_S 867 +#define AArch64_UQRSHL_ZPZZ_UNDEF_B 868 +#define AArch64_UQRSHL_ZPZZ_UNDEF_D 869 +#define AArch64_UQRSHL_ZPZZ_UNDEF_H 870 +#define AArch64_UQRSHL_ZPZZ_UNDEF_S 871 +#define AArch64_UQSHL_ZPZI_ZERO_B 872 +#define AArch64_UQSHL_ZPZI_ZERO_D 873 +#define AArch64_UQSHL_ZPZI_ZERO_H 874 +#define AArch64_UQSHL_ZPZI_ZERO_S 875 +#define AArch64_UQSHL_ZPZZ_UNDEF_B 876 +#define AArch64_UQSHL_ZPZZ_UNDEF_D 877 +#define AArch64_UQSHL_ZPZZ_UNDEF_H 878 +#define AArch64_UQSHL_ZPZZ_UNDEF_S 879 +#define AArch64_URECPE_ZPmZ_UNDEF_S 880 +#define AArch64_URSHL_ZPZZ_UNDEF_B 881 +#define AArch64_URSHL_ZPZZ_UNDEF_D 882 +#define AArch64_URSHL_ZPZZ_UNDEF_H 883 +#define AArch64_URSHL_ZPZZ_UNDEF_S 884 +#define AArch64_URSHR_ZPZI_ZERO_B 885 +#define AArch64_URSHR_ZPZI_ZERO_D 886 +#define AArch64_URSHR_ZPZI_ZERO_H 887 +#define AArch64_URSHR_ZPZI_ZERO_S 888 +#define AArch64_URSQRTE_ZPmZ_UNDEF_S 889 +#define AArch64_UXTB_ZPmZ_UNDEF_D 890 +#define AArch64_UXTB_ZPmZ_UNDEF_H 891 +#define AArch64_UXTB_ZPmZ_UNDEF_S 892 +#define AArch64_UXTH_ZPmZ_UNDEF_D 893 +#define AArch64_UXTH_ZPmZ_UNDEF_S 894 +#define AArch64_UXTW_ZPmZ_UNDEF_D 895 +#define AArch64_ABS_ZPmZ_B 896 +#define AArch64_ABS_ZPmZ_D 897 +#define AArch64_ABS_ZPmZ_H 898 +#define AArch64_ABS_ZPmZ_S 899 +#define AArch64_ABSv16i8 900 +#define AArch64_ABSv1i64 901 +#define AArch64_ABSv2i32 902 +#define AArch64_ABSv2i64 903 +#define AArch64_ABSv4i16 904 +#define AArch64_ABSv4i32 905 +#define AArch64_ABSv8i16 906 +#define AArch64_ABSv8i8 907 +#define AArch64_ADCLB_ZZZ_D 908 +#define AArch64_ADCLB_ZZZ_S 909 +#define AArch64_ADCLT_ZZZ_D 910 +#define AArch64_ADCLT_ZZZ_S 911 +#define AArch64_ADCSWr 912 +#define AArch64_ADCSXr 913 +#define AArch64_ADCWr 914 +#define AArch64_ADCXr 915 +#define AArch64_ADDG 916 +#define AArch64_ADDHA_MPPZ_D 917 +#define AArch64_ADDHA_MPPZ_S 918 +#define AArch64_ADDHNB_ZZZ_B 919 +#define AArch64_ADDHNB_ZZZ_H 920 +#define AArch64_ADDHNB_ZZZ_S 921 +#define AArch64_ADDHNT_ZZZ_B 922 +#define AArch64_ADDHNT_ZZZ_H 923 +#define AArch64_ADDHNT_ZZZ_S 924 +#define AArch64_ADDHNv2i64_v2i32 925 +#define AArch64_ADDHNv2i64_v4i32 926 +#define AArch64_ADDHNv4i32_v4i16 927 +#define AArch64_ADDHNv4i32_v8i16 928 +#define AArch64_ADDHNv8i16_v16i8 929 +#define AArch64_ADDHNv8i16_v8i8 930 +#define AArch64_ADDPL_XXI 931 +#define AArch64_ADDP_ZPmZ_B 932 +#define AArch64_ADDP_ZPmZ_D 933 +#define AArch64_ADDP_ZPmZ_H 934 +#define AArch64_ADDP_ZPmZ_S 935 +#define AArch64_ADDPv16i8 936 +#define AArch64_ADDPv2i32 937 +#define AArch64_ADDPv2i64 938 +#define AArch64_ADDPv2i64p 939 +#define AArch64_ADDPv4i16 940 +#define AArch64_ADDPv4i32 941 +#define AArch64_ADDPv8i16 942 +#define AArch64_ADDPv8i8 943 +#define AArch64_ADDSWri 944 +#define AArch64_ADDSWrs 945 +#define AArch64_ADDSWrx 946 +#define AArch64_ADDSXri 947 +#define AArch64_ADDSXrs 948 +#define AArch64_ADDSXrx 949 +#define AArch64_ADDSXrx64 950 +#define AArch64_ADDVA_MPPZ_D 951 +#define AArch64_ADDVA_MPPZ_S 952 +#define AArch64_ADDVL_XXI 953 +#define AArch64_ADDVv16i8v 954 +#define AArch64_ADDVv4i16v 955 +#define AArch64_ADDVv4i32v 956 +#define AArch64_ADDVv8i16v 957 +#define AArch64_ADDVv8i8v 958 +#define AArch64_ADDWri 959 +#define AArch64_ADDWrs 960 +#define AArch64_ADDWrx 961 +#define AArch64_ADDXri 962 +#define AArch64_ADDXrs 963 +#define AArch64_ADDXrx 964 +#define AArch64_ADDXrx64 965 +#define AArch64_ADD_ZI_B 966 +#define AArch64_ADD_ZI_D 967 +#define AArch64_ADD_ZI_H 968 +#define AArch64_ADD_ZI_S 969 +#define AArch64_ADD_ZPmZ_B 970 +#define AArch64_ADD_ZPmZ_D 971 +#define AArch64_ADD_ZPmZ_H 972 +#define AArch64_ADD_ZPmZ_S 973 +#define AArch64_ADD_ZZZ_B 974 +#define AArch64_ADD_ZZZ_D 975 +#define AArch64_ADD_ZZZ_H 976 +#define AArch64_ADD_ZZZ_S 977 +#define AArch64_ADDv16i8 978 +#define AArch64_ADDv1i64 979 +#define AArch64_ADDv2i32 980 +#define AArch64_ADDv2i64 981 +#define AArch64_ADDv4i16 982 +#define AArch64_ADDv4i32 983 +#define AArch64_ADDv8i16 984 +#define AArch64_ADDv8i8 985 +#define AArch64_ADR 986 +#define AArch64_ADRP 987 +#define AArch64_ADR_LSL_ZZZ_D_0 988 +#define AArch64_ADR_LSL_ZZZ_D_1 989 +#define AArch64_ADR_LSL_ZZZ_D_2 990 +#define AArch64_ADR_LSL_ZZZ_D_3 991 +#define AArch64_ADR_LSL_ZZZ_S_0 992 +#define AArch64_ADR_LSL_ZZZ_S_1 993 +#define AArch64_ADR_LSL_ZZZ_S_2 994 +#define AArch64_ADR_LSL_ZZZ_S_3 995 +#define AArch64_ADR_SXTW_ZZZ_D_0 996 +#define AArch64_ADR_SXTW_ZZZ_D_1 997 +#define AArch64_ADR_SXTW_ZZZ_D_2 998 +#define AArch64_ADR_SXTW_ZZZ_D_3 999 +#define AArch64_ADR_UXTW_ZZZ_D_0 1000 +#define AArch64_ADR_UXTW_ZZZ_D_1 1001 +#define AArch64_ADR_UXTW_ZZZ_D_2 1002 +#define AArch64_ADR_UXTW_ZZZ_D_3 1003 +#define AArch64_AESD_ZZZ_B 1004 +#define AArch64_AESDrr 1005 +#define AArch64_AESE_ZZZ_B 1006 +#define AArch64_AESErr 1007 +#define AArch64_AESIMC_ZZ_B 1008 +#define AArch64_AESIMCrr 1009 +#define AArch64_AESMC_ZZ_B 1010 +#define AArch64_AESMCrr 1011 +#define AArch64_ANDSWri 1012 +#define AArch64_ANDSWrs 1013 +#define AArch64_ANDSXri 1014 +#define AArch64_ANDSXrs 1015 +#define AArch64_ANDS_PPzPP 1016 +#define AArch64_ANDV_VPZ_B 1017 +#define AArch64_ANDV_VPZ_D 1018 +#define AArch64_ANDV_VPZ_H 1019 +#define AArch64_ANDV_VPZ_S 1020 +#define AArch64_ANDWri 1021 +#define AArch64_ANDWrs 1022 +#define AArch64_ANDXri 1023 +#define AArch64_ANDXrs 1024 +#define AArch64_AND_PPzPP 1025 +#define AArch64_AND_ZI 1026 +#define AArch64_AND_ZPmZ_B 1027 +#define AArch64_AND_ZPmZ_D 1028 +#define AArch64_AND_ZPmZ_H 1029 +#define AArch64_AND_ZPmZ_S 1030 +#define AArch64_AND_ZZZ 1031 +#define AArch64_ANDv16i8 1032 +#define AArch64_ANDv8i8 1033 +#define AArch64_ASRD_ZPmI_B 1034 +#define AArch64_ASRD_ZPmI_D 1035 +#define AArch64_ASRD_ZPmI_H 1036 +#define AArch64_ASRD_ZPmI_S 1037 +#define AArch64_ASRR_ZPmZ_B 1038 +#define AArch64_ASRR_ZPmZ_D 1039 +#define AArch64_ASRR_ZPmZ_H 1040 +#define AArch64_ASRR_ZPmZ_S 1041 +#define AArch64_ASRVWr 1042 +#define AArch64_ASRVXr 1043 +#define AArch64_ASR_WIDE_ZPmZ_B 1044 +#define AArch64_ASR_WIDE_ZPmZ_H 1045 +#define AArch64_ASR_WIDE_ZPmZ_S 1046 +#define AArch64_ASR_WIDE_ZZZ_B 1047 +#define AArch64_ASR_WIDE_ZZZ_H 1048 +#define AArch64_ASR_WIDE_ZZZ_S 1049 +#define AArch64_ASR_ZPmI_B 1050 +#define AArch64_ASR_ZPmI_D 1051 +#define AArch64_ASR_ZPmI_H 1052 +#define AArch64_ASR_ZPmI_S 1053 +#define AArch64_ASR_ZPmZ_B 1054 +#define AArch64_ASR_ZPmZ_D 1055 +#define AArch64_ASR_ZPmZ_H 1056 +#define AArch64_ASR_ZPmZ_S 1057 +#define AArch64_ASR_ZZI_B 1058 +#define AArch64_ASR_ZZI_D 1059 +#define AArch64_ASR_ZZI_H 1060 +#define AArch64_ASR_ZZI_S 1061 +#define AArch64_AUTDA 1062 +#define AArch64_AUTDB 1063 +#define AArch64_AUTDZA 1064 +#define AArch64_AUTDZB 1065 +#define AArch64_AUTIA 1066 +#define AArch64_AUTIA1716 1067 +#define AArch64_AUTIASP 1068 +#define AArch64_AUTIAZ 1069 +#define AArch64_AUTIB 1070 +#define AArch64_AUTIB1716 1071 +#define AArch64_AUTIBSP 1072 +#define AArch64_AUTIBZ 1073 +#define AArch64_AUTIZA 1074 +#define AArch64_AUTIZB 1075 +#define AArch64_AXFLAG 1076 +#define AArch64_B 1077 +#define AArch64_BCAX 1078 +#define AArch64_BCAX_ZZZZ 1079 +#define AArch64_BDEP_ZZZ_B 1080 +#define AArch64_BDEP_ZZZ_D 1081 +#define AArch64_BDEP_ZZZ_H 1082 +#define AArch64_BDEP_ZZZ_S 1083 +#define AArch64_BEXT_ZZZ_B 1084 +#define AArch64_BEXT_ZZZ_D 1085 +#define AArch64_BEXT_ZZZ_H 1086 +#define AArch64_BEXT_ZZZ_S 1087 +#define AArch64_BF16DOTlanev4bf16 1088 +#define AArch64_BF16DOTlanev8bf16 1089 +#define AArch64_BFCVT 1090 +#define AArch64_BFCVTN 1091 +#define AArch64_BFCVTN2 1092 +#define AArch64_BFCVTNT_ZPmZ 1093 +#define AArch64_BFCVT_ZPmZ 1094 +#define AArch64_BFDOT_ZZI 1095 +#define AArch64_BFDOT_ZZZ 1096 +#define AArch64_BFDOTv4bf16 1097 +#define AArch64_BFDOTv8bf16 1098 +#define AArch64_BFMLALB 1099 +#define AArch64_BFMLALBIdx 1100 +#define AArch64_BFMLALT 1101 +#define AArch64_BFMLALTIdx 1102 +#define AArch64_BFMMLA 1103 +#define AArch64_BFMMLA_B_ZZI 1104 +#define AArch64_BFMMLA_B_ZZZ 1105 +#define AArch64_BFMMLA_T_ZZI 1106 +#define AArch64_BFMMLA_T_ZZZ 1107 +#define AArch64_BFMMLA_ZZZ 1108 +#define AArch64_BFMWri 1109 +#define AArch64_BFMXri 1110 +#define AArch64_BGRP_ZZZ_B 1111 +#define AArch64_BGRP_ZZZ_D 1112 +#define AArch64_BGRP_ZZZ_H 1113 +#define AArch64_BGRP_ZZZ_S 1114 +#define AArch64_BICSWrs 1115 +#define AArch64_BICSXrs 1116 +#define AArch64_BICS_PPzPP 1117 +#define AArch64_BICWrs 1118 +#define AArch64_BICXrs 1119 +#define AArch64_BIC_PPzPP 1120 +#define AArch64_BIC_ZPmZ_B 1121 +#define AArch64_BIC_ZPmZ_D 1122 +#define AArch64_BIC_ZPmZ_H 1123 +#define AArch64_BIC_ZPmZ_S 1124 +#define AArch64_BIC_ZZZ 1125 +#define AArch64_BICv16i8 1126 +#define AArch64_BICv2i32 1127 +#define AArch64_BICv4i16 1128 +#define AArch64_BICv4i32 1129 +#define AArch64_BICv8i16 1130 +#define AArch64_BICv8i8 1131 +#define AArch64_BIFv16i8 1132 +#define AArch64_BIFv8i8 1133 +#define AArch64_BITv16i8 1134 +#define AArch64_BITv8i8 1135 +#define AArch64_BL 1136 +#define AArch64_BLR 1137 +#define AArch64_BLRAA 1138 +#define AArch64_BLRAAZ 1139 +#define AArch64_BLRAB 1140 +#define AArch64_BLRABZ 1141 +#define AArch64_BR 1142 +#define AArch64_BRAA 1143 +#define AArch64_BRAAZ 1144 +#define AArch64_BRAB 1145 +#define AArch64_BRABZ 1146 +#define AArch64_BRB_IALL 1147 +#define AArch64_BRB_INJ 1148 +#define AArch64_BRK 1149 +#define AArch64_BRKAS_PPzP 1150 +#define AArch64_BRKA_PPmP 1151 +#define AArch64_BRKA_PPzP 1152 +#define AArch64_BRKBS_PPzP 1153 +#define AArch64_BRKB_PPmP 1154 +#define AArch64_BRKB_PPzP 1155 +#define AArch64_BRKNS_PPzP 1156 +#define AArch64_BRKN_PPzP 1157 +#define AArch64_BRKPAS_PPzPP 1158 +#define AArch64_BRKPA_PPzPP 1159 +#define AArch64_BRKPBS_PPzPP 1160 +#define AArch64_BRKPB_PPzPP 1161 +#define AArch64_BSL1N_ZZZZ 1162 +#define AArch64_BSL2N_ZZZZ 1163 +#define AArch64_BSL_ZZZZ 1164 +#define AArch64_BSLv16i8 1165 +#define AArch64_BSLv8i8 1166 +#define AArch64_Bcc 1167 +#define AArch64_CADD_ZZI_B 1168 +#define AArch64_CADD_ZZI_D 1169 +#define AArch64_CADD_ZZI_H 1170 +#define AArch64_CADD_ZZI_S 1171 +#define AArch64_CASAB 1172 +#define AArch64_CASAH 1173 +#define AArch64_CASALB 1174 +#define AArch64_CASALH 1175 +#define AArch64_CASALW 1176 +#define AArch64_CASALX 1177 +#define AArch64_CASAW 1178 +#define AArch64_CASAX 1179 +#define AArch64_CASB 1180 +#define AArch64_CASH 1181 +#define AArch64_CASLB 1182 +#define AArch64_CASLH 1183 +#define AArch64_CASLW 1184 +#define AArch64_CASLX 1185 +#define AArch64_CASPALW 1186 +#define AArch64_CASPALX 1187 +#define AArch64_CASPAW 1188 +#define AArch64_CASPAX 1189 +#define AArch64_CASPLW 1190 +#define AArch64_CASPLX 1191 +#define AArch64_CASPW 1192 +#define AArch64_CASPX 1193 +#define AArch64_CASW 1194 +#define AArch64_CASX 1195 +#define AArch64_CBNZW 1196 +#define AArch64_CBNZX 1197 +#define AArch64_CBZW 1198 +#define AArch64_CBZX 1199 +#define AArch64_CCMNWi 1200 +#define AArch64_CCMNWr 1201 +#define AArch64_CCMNXi 1202 +#define AArch64_CCMNXr 1203 +#define AArch64_CCMPWi 1204 +#define AArch64_CCMPWr 1205 +#define AArch64_CCMPXi 1206 +#define AArch64_CCMPXr 1207 +#define AArch64_CDOT_ZZZI_D 1208 +#define AArch64_CDOT_ZZZI_S 1209 +#define AArch64_CDOT_ZZZ_D 1210 +#define AArch64_CDOT_ZZZ_S 1211 +#define AArch64_CFINV 1212 +#define AArch64_CLASTA_RPZ_B 1213 +#define AArch64_CLASTA_RPZ_D 1214 +#define AArch64_CLASTA_RPZ_H 1215 +#define AArch64_CLASTA_RPZ_S 1216 +#define AArch64_CLASTA_VPZ_B 1217 +#define AArch64_CLASTA_VPZ_D 1218 +#define AArch64_CLASTA_VPZ_H 1219 +#define AArch64_CLASTA_VPZ_S 1220 +#define AArch64_CLASTA_ZPZ_B 1221 +#define AArch64_CLASTA_ZPZ_D 1222 +#define AArch64_CLASTA_ZPZ_H 1223 +#define AArch64_CLASTA_ZPZ_S 1224 +#define AArch64_CLASTB_RPZ_B 1225 +#define AArch64_CLASTB_RPZ_D 1226 +#define AArch64_CLASTB_RPZ_H 1227 +#define AArch64_CLASTB_RPZ_S 1228 +#define AArch64_CLASTB_VPZ_B 1229 +#define AArch64_CLASTB_VPZ_D 1230 +#define AArch64_CLASTB_VPZ_H 1231 +#define AArch64_CLASTB_VPZ_S 1232 +#define AArch64_CLASTB_ZPZ_B 1233 +#define AArch64_CLASTB_ZPZ_D 1234 +#define AArch64_CLASTB_ZPZ_H 1235 +#define AArch64_CLASTB_ZPZ_S 1236 +#define AArch64_CLREX 1237 +#define AArch64_CLSWr 1238 +#define AArch64_CLSXr 1239 +#define AArch64_CLS_ZPmZ_B 1240 +#define AArch64_CLS_ZPmZ_D 1241 +#define AArch64_CLS_ZPmZ_H 1242 +#define AArch64_CLS_ZPmZ_S 1243 +#define AArch64_CLSv16i8 1244 +#define AArch64_CLSv2i32 1245 +#define AArch64_CLSv4i16 1246 +#define AArch64_CLSv4i32 1247 +#define AArch64_CLSv8i16 1248 +#define AArch64_CLSv8i8 1249 +#define AArch64_CLZWr 1250 +#define AArch64_CLZXr 1251 +#define AArch64_CLZ_ZPmZ_B 1252 +#define AArch64_CLZ_ZPmZ_D 1253 +#define AArch64_CLZ_ZPmZ_H 1254 +#define AArch64_CLZ_ZPmZ_S 1255 +#define AArch64_CLZv16i8 1256 +#define AArch64_CLZv2i32 1257 +#define AArch64_CLZv4i16 1258 +#define AArch64_CLZv4i32 1259 +#define AArch64_CLZv8i16 1260 +#define AArch64_CLZv8i8 1261 +#define AArch64_CMEQv16i8 1262 +#define AArch64_CMEQv16i8rz 1263 +#define AArch64_CMEQv1i64 1264 +#define AArch64_CMEQv1i64rz 1265 +#define AArch64_CMEQv2i32 1266 +#define AArch64_CMEQv2i32rz 1267 +#define AArch64_CMEQv2i64 1268 +#define AArch64_CMEQv2i64rz 1269 +#define AArch64_CMEQv4i16 1270 +#define AArch64_CMEQv4i16rz 1271 +#define AArch64_CMEQv4i32 1272 +#define AArch64_CMEQv4i32rz 1273 +#define AArch64_CMEQv8i16 1274 +#define AArch64_CMEQv8i16rz 1275 +#define AArch64_CMEQv8i8 1276 +#define AArch64_CMEQv8i8rz 1277 +#define AArch64_CMGEv16i8 1278 +#define AArch64_CMGEv16i8rz 1279 +#define AArch64_CMGEv1i64 1280 +#define AArch64_CMGEv1i64rz 1281 +#define AArch64_CMGEv2i32 1282 +#define AArch64_CMGEv2i32rz 1283 +#define AArch64_CMGEv2i64 1284 +#define AArch64_CMGEv2i64rz 1285 +#define AArch64_CMGEv4i16 1286 +#define AArch64_CMGEv4i16rz 1287 +#define AArch64_CMGEv4i32 1288 +#define AArch64_CMGEv4i32rz 1289 +#define AArch64_CMGEv8i16 1290 +#define AArch64_CMGEv8i16rz 1291 +#define AArch64_CMGEv8i8 1292 +#define AArch64_CMGEv8i8rz 1293 +#define AArch64_CMGTv16i8 1294 +#define AArch64_CMGTv16i8rz 1295 +#define AArch64_CMGTv1i64 1296 +#define AArch64_CMGTv1i64rz 1297 +#define AArch64_CMGTv2i32 1298 +#define AArch64_CMGTv2i32rz 1299 +#define AArch64_CMGTv2i64 1300 +#define AArch64_CMGTv2i64rz 1301 +#define AArch64_CMGTv4i16 1302 +#define AArch64_CMGTv4i16rz 1303 +#define AArch64_CMGTv4i32 1304 +#define AArch64_CMGTv4i32rz 1305 +#define AArch64_CMGTv8i16 1306 +#define AArch64_CMGTv8i16rz 1307 +#define AArch64_CMGTv8i8 1308 +#define AArch64_CMGTv8i8rz 1309 +#define AArch64_CMHIv16i8 1310 +#define AArch64_CMHIv1i64 1311 +#define AArch64_CMHIv2i32 1312 +#define AArch64_CMHIv2i64 1313 +#define AArch64_CMHIv4i16 1314 +#define AArch64_CMHIv4i32 1315 +#define AArch64_CMHIv8i16 1316 +#define AArch64_CMHIv8i8 1317 +#define AArch64_CMHSv16i8 1318 +#define AArch64_CMHSv1i64 1319 +#define AArch64_CMHSv2i32 1320 +#define AArch64_CMHSv2i64 1321 +#define AArch64_CMHSv4i16 1322 +#define AArch64_CMHSv4i32 1323 +#define AArch64_CMHSv8i16 1324 +#define AArch64_CMHSv8i8 1325 +#define AArch64_CMLA_ZZZI_H 1326 +#define AArch64_CMLA_ZZZI_S 1327 +#define AArch64_CMLA_ZZZ_B 1328 +#define AArch64_CMLA_ZZZ_D 1329 +#define AArch64_CMLA_ZZZ_H 1330 +#define AArch64_CMLA_ZZZ_S 1331 +#define AArch64_CMLEv16i8rz 1332 +#define AArch64_CMLEv1i64rz 1333 +#define AArch64_CMLEv2i32rz 1334 +#define AArch64_CMLEv2i64rz 1335 +#define AArch64_CMLEv4i16rz 1336 +#define AArch64_CMLEv4i32rz 1337 +#define AArch64_CMLEv8i16rz 1338 +#define AArch64_CMLEv8i8rz 1339 +#define AArch64_CMLTv16i8rz 1340 +#define AArch64_CMLTv1i64rz 1341 +#define AArch64_CMLTv2i32rz 1342 +#define AArch64_CMLTv2i64rz 1343 +#define AArch64_CMLTv4i16rz 1344 +#define AArch64_CMLTv4i32rz 1345 +#define AArch64_CMLTv8i16rz 1346 +#define AArch64_CMLTv8i8rz 1347 +#define AArch64_CMPEQ_PPzZI_B 1348 +#define AArch64_CMPEQ_PPzZI_D 1349 +#define AArch64_CMPEQ_PPzZI_H 1350 +#define AArch64_CMPEQ_PPzZI_S 1351 +#define AArch64_CMPEQ_PPzZZ_B 1352 +#define AArch64_CMPEQ_PPzZZ_D 1353 +#define AArch64_CMPEQ_PPzZZ_H 1354 +#define AArch64_CMPEQ_PPzZZ_S 1355 +#define AArch64_CMPEQ_WIDE_PPzZZ_B 1356 +#define AArch64_CMPEQ_WIDE_PPzZZ_H 1357 +#define AArch64_CMPEQ_WIDE_PPzZZ_S 1358 +#define AArch64_CMPGE_PPzZI_B 1359 +#define AArch64_CMPGE_PPzZI_D 1360 +#define AArch64_CMPGE_PPzZI_H 1361 +#define AArch64_CMPGE_PPzZI_S 1362 +#define AArch64_CMPGE_PPzZZ_B 1363 +#define AArch64_CMPGE_PPzZZ_D 1364 +#define AArch64_CMPGE_PPzZZ_H 1365 +#define AArch64_CMPGE_PPzZZ_S 1366 +#define AArch64_CMPGE_WIDE_PPzZZ_B 1367 +#define AArch64_CMPGE_WIDE_PPzZZ_H 1368 +#define AArch64_CMPGE_WIDE_PPzZZ_S 1369 +#define AArch64_CMPGT_PPzZI_B 1370 +#define AArch64_CMPGT_PPzZI_D 1371 +#define AArch64_CMPGT_PPzZI_H 1372 +#define AArch64_CMPGT_PPzZI_S 1373 +#define AArch64_CMPGT_PPzZZ_B 1374 +#define AArch64_CMPGT_PPzZZ_D 1375 +#define AArch64_CMPGT_PPzZZ_H 1376 +#define AArch64_CMPGT_PPzZZ_S 1377 +#define AArch64_CMPGT_WIDE_PPzZZ_B 1378 +#define AArch64_CMPGT_WIDE_PPzZZ_H 1379 +#define AArch64_CMPGT_WIDE_PPzZZ_S 1380 +#define AArch64_CMPHI_PPzZI_B 1381 +#define AArch64_CMPHI_PPzZI_D 1382 +#define AArch64_CMPHI_PPzZI_H 1383 +#define AArch64_CMPHI_PPzZI_S 1384 +#define AArch64_CMPHI_PPzZZ_B 1385 +#define AArch64_CMPHI_PPzZZ_D 1386 +#define AArch64_CMPHI_PPzZZ_H 1387 +#define AArch64_CMPHI_PPzZZ_S 1388 +#define AArch64_CMPHI_WIDE_PPzZZ_B 1389 +#define AArch64_CMPHI_WIDE_PPzZZ_H 1390 +#define AArch64_CMPHI_WIDE_PPzZZ_S 1391 +#define AArch64_CMPHS_PPzZI_B 1392 +#define AArch64_CMPHS_PPzZI_D 1393 +#define AArch64_CMPHS_PPzZI_H 1394 +#define AArch64_CMPHS_PPzZI_S 1395 +#define AArch64_CMPHS_PPzZZ_B 1396 +#define AArch64_CMPHS_PPzZZ_D 1397 +#define AArch64_CMPHS_PPzZZ_H 1398 +#define AArch64_CMPHS_PPzZZ_S 1399 +#define AArch64_CMPHS_WIDE_PPzZZ_B 1400 +#define AArch64_CMPHS_WIDE_PPzZZ_H 1401 +#define AArch64_CMPHS_WIDE_PPzZZ_S 1402 +#define AArch64_CMPLE_PPzZI_B 1403 +#define AArch64_CMPLE_PPzZI_D 1404 +#define AArch64_CMPLE_PPzZI_H 1405 +#define AArch64_CMPLE_PPzZI_S 1406 +#define AArch64_CMPLE_WIDE_PPzZZ_B 1407 +#define AArch64_CMPLE_WIDE_PPzZZ_H 1408 +#define AArch64_CMPLE_WIDE_PPzZZ_S 1409 +#define AArch64_CMPLO_PPzZI_B 1410 +#define AArch64_CMPLO_PPzZI_D 1411 +#define AArch64_CMPLO_PPzZI_H 1412 +#define AArch64_CMPLO_PPzZI_S 1413 +#define AArch64_CMPLO_WIDE_PPzZZ_B 1414 +#define AArch64_CMPLO_WIDE_PPzZZ_H 1415 +#define AArch64_CMPLO_WIDE_PPzZZ_S 1416 +#define AArch64_CMPLS_PPzZI_B 1417 +#define AArch64_CMPLS_PPzZI_D 1418 +#define AArch64_CMPLS_PPzZI_H 1419 +#define AArch64_CMPLS_PPzZI_S 1420 +#define AArch64_CMPLS_WIDE_PPzZZ_B 1421 +#define AArch64_CMPLS_WIDE_PPzZZ_H 1422 +#define AArch64_CMPLS_WIDE_PPzZZ_S 1423 +#define AArch64_CMPLT_PPzZI_B 1424 +#define AArch64_CMPLT_PPzZI_D 1425 +#define AArch64_CMPLT_PPzZI_H 1426 +#define AArch64_CMPLT_PPzZI_S 1427 +#define AArch64_CMPLT_WIDE_PPzZZ_B 1428 +#define AArch64_CMPLT_WIDE_PPzZZ_H 1429 +#define AArch64_CMPLT_WIDE_PPzZZ_S 1430 +#define AArch64_CMPNE_PPzZI_B 1431 +#define AArch64_CMPNE_PPzZI_D 1432 +#define AArch64_CMPNE_PPzZI_H 1433 +#define AArch64_CMPNE_PPzZI_S 1434 +#define AArch64_CMPNE_PPzZZ_B 1435 +#define AArch64_CMPNE_PPzZZ_D 1436 +#define AArch64_CMPNE_PPzZZ_H 1437 +#define AArch64_CMPNE_PPzZZ_S 1438 +#define AArch64_CMPNE_WIDE_PPzZZ_B 1439 +#define AArch64_CMPNE_WIDE_PPzZZ_H 1440 +#define AArch64_CMPNE_WIDE_PPzZZ_S 1441 +#define AArch64_CMTSTv16i8 1442 +#define AArch64_CMTSTv1i64 1443 +#define AArch64_CMTSTv2i32 1444 +#define AArch64_CMTSTv2i64 1445 +#define AArch64_CMTSTv4i16 1446 +#define AArch64_CMTSTv4i32 1447 +#define AArch64_CMTSTv8i16 1448 +#define AArch64_CMTSTv8i8 1449 +#define AArch64_CNOT_ZPmZ_B 1450 +#define AArch64_CNOT_ZPmZ_D 1451 +#define AArch64_CNOT_ZPmZ_H 1452 +#define AArch64_CNOT_ZPmZ_S 1453 +#define AArch64_CNTB_XPiI 1454 +#define AArch64_CNTD_XPiI 1455 +#define AArch64_CNTH_XPiI 1456 +#define AArch64_CNTP_XPP_B 1457 +#define AArch64_CNTP_XPP_D 1458 +#define AArch64_CNTP_XPP_H 1459 +#define AArch64_CNTP_XPP_S 1460 +#define AArch64_CNTW_XPiI 1461 +#define AArch64_CNT_ZPmZ_B 1462 +#define AArch64_CNT_ZPmZ_D 1463 +#define AArch64_CNT_ZPmZ_H 1464 +#define AArch64_CNT_ZPmZ_S 1465 +#define AArch64_CNTv16i8 1466 +#define AArch64_CNTv8i8 1467 +#define AArch64_COMPACT_ZPZ_D 1468 +#define AArch64_COMPACT_ZPZ_S 1469 +#define AArch64_CPY_ZPmI_B 1470 +#define AArch64_CPY_ZPmI_D 1471 +#define AArch64_CPY_ZPmI_H 1472 +#define AArch64_CPY_ZPmI_S 1473 +#define AArch64_CPY_ZPmR_B 1474 +#define AArch64_CPY_ZPmR_D 1475 +#define AArch64_CPY_ZPmR_H 1476 +#define AArch64_CPY_ZPmR_S 1477 +#define AArch64_CPY_ZPmV_B 1478 +#define AArch64_CPY_ZPmV_D 1479 +#define AArch64_CPY_ZPmV_H 1480 +#define AArch64_CPY_ZPmV_S 1481 +#define AArch64_CPY_ZPzI_B 1482 +#define AArch64_CPY_ZPzI_D 1483 +#define AArch64_CPY_ZPzI_H 1484 +#define AArch64_CPY_ZPzI_S 1485 +#define AArch64_CPYi16 1486 +#define AArch64_CPYi32 1487 +#define AArch64_CPYi64 1488 +#define AArch64_CPYi8 1489 +#define AArch64_CRC32Brr 1490 +#define AArch64_CRC32CBrr 1491 +#define AArch64_CRC32CHrr 1492 +#define AArch64_CRC32CWrr 1493 +#define AArch64_CRC32CXrr 1494 +#define AArch64_CRC32Hrr 1495 +#define AArch64_CRC32Wrr 1496 +#define AArch64_CRC32Xrr 1497 +#define AArch64_CSELWr 1498 +#define AArch64_CSELXr 1499 +#define AArch64_CSINCWr 1500 +#define AArch64_CSINCXr 1501 +#define AArch64_CSINVWr 1502 +#define AArch64_CSINVXr 1503 +#define AArch64_CSNEGWr 1504 +#define AArch64_CSNEGXr 1505 +#define AArch64_CTERMEQ_WW 1506 +#define AArch64_CTERMEQ_XX 1507 +#define AArch64_CTERMNE_WW 1508 +#define AArch64_CTERMNE_XX 1509 +#define AArch64_DCPS1 1510 +#define AArch64_DCPS2 1511 +#define AArch64_DCPS3 1512 +#define AArch64_DECB_XPiI 1513 +#define AArch64_DECD_XPiI 1514 +#define AArch64_DECD_ZPiI 1515 +#define AArch64_DECH_XPiI 1516 +#define AArch64_DECH_ZPiI 1517 +#define AArch64_DECP_XP_B 1518 +#define AArch64_DECP_XP_D 1519 +#define AArch64_DECP_XP_H 1520 +#define AArch64_DECP_XP_S 1521 +#define AArch64_DECP_ZP_D 1522 +#define AArch64_DECP_ZP_H 1523 +#define AArch64_DECP_ZP_S 1524 +#define AArch64_DECW_XPiI 1525 +#define AArch64_DECW_ZPiI 1526 +#define AArch64_DMB 1527 +#define AArch64_DRPS 1528 +#define AArch64_DSB 1529 +#define AArch64_DSBnXS 1530 +#define AArch64_DUPM_ZI 1531 +#define AArch64_DUP_ZI_B 1532 +#define AArch64_DUP_ZI_D 1533 +#define AArch64_DUP_ZI_H 1534 +#define AArch64_DUP_ZI_S 1535 +#define AArch64_DUP_ZR_B 1536 +#define AArch64_DUP_ZR_D 1537 +#define AArch64_DUP_ZR_H 1538 +#define AArch64_DUP_ZR_S 1539 +#define AArch64_DUP_ZZI_B 1540 +#define AArch64_DUP_ZZI_D 1541 +#define AArch64_DUP_ZZI_H 1542 +#define AArch64_DUP_ZZI_Q 1543 +#define AArch64_DUP_ZZI_S 1544 +#define AArch64_DUPv16i8gpr 1545 +#define AArch64_DUPv16i8lane 1546 +#define AArch64_DUPv2i32gpr 1547 +#define AArch64_DUPv2i32lane 1548 +#define AArch64_DUPv2i64gpr 1549 +#define AArch64_DUPv2i64lane 1550 +#define AArch64_DUPv4i16gpr 1551 +#define AArch64_DUPv4i16lane 1552 +#define AArch64_DUPv4i32gpr 1553 +#define AArch64_DUPv4i32lane 1554 +#define AArch64_DUPv8i16gpr 1555 +#define AArch64_DUPv8i16lane 1556 +#define AArch64_DUPv8i8gpr 1557 +#define AArch64_DUPv8i8lane 1558 +#define AArch64_EONWrs 1559 +#define AArch64_EONXrs 1560 +#define AArch64_EOR3 1561 +#define AArch64_EOR3_ZZZZ 1562 +#define AArch64_EORBT_ZZZ_B 1563 +#define AArch64_EORBT_ZZZ_D 1564 +#define AArch64_EORBT_ZZZ_H 1565 +#define AArch64_EORBT_ZZZ_S 1566 +#define AArch64_EORS_PPzPP 1567 +#define AArch64_EORTB_ZZZ_B 1568 +#define AArch64_EORTB_ZZZ_D 1569 +#define AArch64_EORTB_ZZZ_H 1570 +#define AArch64_EORTB_ZZZ_S 1571 +#define AArch64_EORV_VPZ_B 1572 +#define AArch64_EORV_VPZ_D 1573 +#define AArch64_EORV_VPZ_H 1574 +#define AArch64_EORV_VPZ_S 1575 +#define AArch64_EORWri 1576 +#define AArch64_EORWrs 1577 +#define AArch64_EORXri 1578 +#define AArch64_EORXrs 1579 +#define AArch64_EOR_PPzPP 1580 +#define AArch64_EOR_ZI 1581 +#define AArch64_EOR_ZPmZ_B 1582 +#define AArch64_EOR_ZPmZ_D 1583 +#define AArch64_EOR_ZPmZ_H 1584 +#define AArch64_EOR_ZPmZ_S 1585 +#define AArch64_EOR_ZZZ 1586 +#define AArch64_EORv16i8 1587 +#define AArch64_EORv8i8 1588 +#define AArch64_ERET 1589 +#define AArch64_ERETAA 1590 +#define AArch64_ERETAB 1591 +#define AArch64_EXTRACT_ZPMXI_H_B 1592 +#define AArch64_EXTRACT_ZPMXI_H_D 1593 +#define AArch64_EXTRACT_ZPMXI_H_H 1594 +#define AArch64_EXTRACT_ZPMXI_H_Q 1595 +#define AArch64_EXTRACT_ZPMXI_H_S 1596 +#define AArch64_EXTRACT_ZPMXI_V_B 1597 +#define AArch64_EXTRACT_ZPMXI_V_D 1598 +#define AArch64_EXTRACT_ZPMXI_V_H 1599 +#define AArch64_EXTRACT_ZPMXI_V_Q 1600 +#define AArch64_EXTRACT_ZPMXI_V_S 1601 +#define AArch64_EXTRWrri 1602 +#define AArch64_EXTRXrri 1603 +#define AArch64_EXT_ZZI 1604 +#define AArch64_EXT_ZZI_B 1605 +#define AArch64_EXTv16i8 1606 +#define AArch64_EXTv8i8 1607 +#define AArch64_FABD16 1608 +#define AArch64_FABD32 1609 +#define AArch64_FABD64 1610 +#define AArch64_FABD_ZPmZ_D 1611 +#define AArch64_FABD_ZPmZ_H 1612 +#define AArch64_FABD_ZPmZ_S 1613 +#define AArch64_FABDv2f32 1614 +#define AArch64_FABDv2f64 1615 +#define AArch64_FABDv4f16 1616 +#define AArch64_FABDv4f32 1617 +#define AArch64_FABDv8f16 1618 +#define AArch64_FABSDr 1619 +#define AArch64_FABSHr 1620 +#define AArch64_FABSSr 1621 +#define AArch64_FABS_ZPmZ_D 1622 +#define AArch64_FABS_ZPmZ_H 1623 +#define AArch64_FABS_ZPmZ_S 1624 +#define AArch64_FABSv2f32 1625 +#define AArch64_FABSv2f64 1626 +#define AArch64_FABSv4f16 1627 +#define AArch64_FABSv4f32 1628 +#define AArch64_FABSv8f16 1629 +#define AArch64_FACGE16 1630 +#define AArch64_FACGE32 1631 +#define AArch64_FACGE64 1632 +#define AArch64_FACGE_PPzZZ_D 1633 +#define AArch64_FACGE_PPzZZ_H 1634 +#define AArch64_FACGE_PPzZZ_S 1635 +#define AArch64_FACGEv2f32 1636 +#define AArch64_FACGEv2f64 1637 +#define AArch64_FACGEv4f16 1638 +#define AArch64_FACGEv4f32 1639 +#define AArch64_FACGEv8f16 1640 +#define AArch64_FACGT16 1641 +#define AArch64_FACGT32 1642 +#define AArch64_FACGT64 1643 +#define AArch64_FACGT_PPzZZ_D 1644 +#define AArch64_FACGT_PPzZZ_H 1645 +#define AArch64_FACGT_PPzZZ_S 1646 +#define AArch64_FACGTv2f32 1647 +#define AArch64_FACGTv2f64 1648 +#define AArch64_FACGTv4f16 1649 +#define AArch64_FACGTv4f32 1650 +#define AArch64_FACGTv8f16 1651 +#define AArch64_FADDA_VPZ_D 1652 +#define AArch64_FADDA_VPZ_H 1653 +#define AArch64_FADDA_VPZ_S 1654 +#define AArch64_FADDDrr 1655 +#define AArch64_FADDHrr 1656 +#define AArch64_FADDP_ZPmZZ_D 1657 +#define AArch64_FADDP_ZPmZZ_H 1658 +#define AArch64_FADDP_ZPmZZ_S 1659 +#define AArch64_FADDPv2f32 1660 +#define AArch64_FADDPv2f64 1661 +#define AArch64_FADDPv2i16p 1662 +#define AArch64_FADDPv2i32p 1663 +#define AArch64_FADDPv2i64p 1664 +#define AArch64_FADDPv4f16 1665 +#define AArch64_FADDPv4f32 1666 +#define AArch64_FADDPv8f16 1667 +#define AArch64_FADDSrr 1668 +#define AArch64_FADDV_VPZ_D 1669 +#define AArch64_FADDV_VPZ_H 1670 +#define AArch64_FADDV_VPZ_S 1671 +#define AArch64_FADD_ZPmI_D 1672 +#define AArch64_FADD_ZPmI_H 1673 +#define AArch64_FADD_ZPmI_S 1674 +#define AArch64_FADD_ZPmZ_D 1675 +#define AArch64_FADD_ZPmZ_H 1676 +#define AArch64_FADD_ZPmZ_S 1677 +#define AArch64_FADD_ZZZ_D 1678 +#define AArch64_FADD_ZZZ_H 1679 +#define AArch64_FADD_ZZZ_S 1680 +#define AArch64_FADDv2f32 1681 +#define AArch64_FADDv2f64 1682 +#define AArch64_FADDv4f16 1683 +#define AArch64_FADDv4f32 1684 +#define AArch64_FADDv8f16 1685 +#define AArch64_FCADD_ZPmZ_D 1686 +#define AArch64_FCADD_ZPmZ_H 1687 +#define AArch64_FCADD_ZPmZ_S 1688 +#define AArch64_FCADDv2f32 1689 +#define AArch64_FCADDv2f64 1690 +#define AArch64_FCADDv4f16 1691 +#define AArch64_FCADDv4f32 1692 +#define AArch64_FCADDv8f16 1693 +#define AArch64_FCCMPDrr 1694 +#define AArch64_FCCMPEDrr 1695 +#define AArch64_FCCMPEHrr 1696 +#define AArch64_FCCMPESrr 1697 +#define AArch64_FCCMPHrr 1698 +#define AArch64_FCCMPSrr 1699 +#define AArch64_FCMEQ16 1700 +#define AArch64_FCMEQ32 1701 +#define AArch64_FCMEQ64 1702 +#define AArch64_FCMEQ_PPzZ0_D 1703 +#define AArch64_FCMEQ_PPzZ0_H 1704 +#define AArch64_FCMEQ_PPzZ0_S 1705 +#define AArch64_FCMEQ_PPzZZ_D 1706 +#define AArch64_FCMEQ_PPzZZ_H 1707 +#define AArch64_FCMEQ_PPzZZ_S 1708 +#define AArch64_FCMEQv1i16rz 1709 +#define AArch64_FCMEQv1i32rz 1710 +#define AArch64_FCMEQv1i64rz 1711 +#define AArch64_FCMEQv2f32 1712 +#define AArch64_FCMEQv2f64 1713 +#define AArch64_FCMEQv2i32rz 1714 +#define AArch64_FCMEQv2i64rz 1715 +#define AArch64_FCMEQv4f16 1716 +#define AArch64_FCMEQv4f32 1717 +#define AArch64_FCMEQv4i16rz 1718 +#define AArch64_FCMEQv4i32rz 1719 +#define AArch64_FCMEQv8f16 1720 +#define AArch64_FCMEQv8i16rz 1721 +#define AArch64_FCMGE16 1722 +#define AArch64_FCMGE32 1723 +#define AArch64_FCMGE64 1724 +#define AArch64_FCMGE_PPzZ0_D 1725 +#define AArch64_FCMGE_PPzZ0_H 1726 +#define AArch64_FCMGE_PPzZ0_S 1727 +#define AArch64_FCMGE_PPzZZ_D 1728 +#define AArch64_FCMGE_PPzZZ_H 1729 +#define AArch64_FCMGE_PPzZZ_S 1730 +#define AArch64_FCMGEv1i16rz 1731 +#define AArch64_FCMGEv1i32rz 1732 +#define AArch64_FCMGEv1i64rz 1733 +#define AArch64_FCMGEv2f32 1734 +#define AArch64_FCMGEv2f64 1735 +#define AArch64_FCMGEv2i32rz 1736 +#define AArch64_FCMGEv2i64rz 1737 +#define AArch64_FCMGEv4f16 1738 +#define AArch64_FCMGEv4f32 1739 +#define AArch64_FCMGEv4i16rz 1740 +#define AArch64_FCMGEv4i32rz 1741 +#define AArch64_FCMGEv8f16 1742 +#define AArch64_FCMGEv8i16rz 1743 +#define AArch64_FCMGT16 1744 +#define AArch64_FCMGT32 1745 +#define AArch64_FCMGT64 1746 +#define AArch64_FCMGT_PPzZ0_D 1747 +#define AArch64_FCMGT_PPzZ0_H 1748 +#define AArch64_FCMGT_PPzZ0_S 1749 +#define AArch64_FCMGT_PPzZZ_D 1750 +#define AArch64_FCMGT_PPzZZ_H 1751 +#define AArch64_FCMGT_PPzZZ_S 1752 +#define AArch64_FCMGTv1i16rz 1753 +#define AArch64_FCMGTv1i32rz 1754 +#define AArch64_FCMGTv1i64rz 1755 +#define AArch64_FCMGTv2f32 1756 +#define AArch64_FCMGTv2f64 1757 +#define AArch64_FCMGTv2i32rz 1758 +#define AArch64_FCMGTv2i64rz 1759 +#define AArch64_FCMGTv4f16 1760 +#define AArch64_FCMGTv4f32 1761 +#define AArch64_FCMGTv4i16rz 1762 +#define AArch64_FCMGTv4i32rz 1763 +#define AArch64_FCMGTv8f16 1764 +#define AArch64_FCMGTv8i16rz 1765 +#define AArch64_FCMLA_ZPmZZ_D 1766 +#define AArch64_FCMLA_ZPmZZ_H 1767 +#define AArch64_FCMLA_ZPmZZ_S 1768 +#define AArch64_FCMLA_ZZZI_H 1769 +#define AArch64_FCMLA_ZZZI_S 1770 +#define AArch64_FCMLAv2f32 1771 +#define AArch64_FCMLAv2f64 1772 +#define AArch64_FCMLAv4f16 1773 +#define AArch64_FCMLAv4f16_indexed 1774 +#define AArch64_FCMLAv4f32 1775 +#define AArch64_FCMLAv4f32_indexed 1776 +#define AArch64_FCMLAv8f16 1777 +#define AArch64_FCMLAv8f16_indexed 1778 +#define AArch64_FCMLE_PPzZ0_D 1779 +#define AArch64_FCMLE_PPzZ0_H 1780 +#define AArch64_FCMLE_PPzZ0_S 1781 +#define AArch64_FCMLEv1i16rz 1782 +#define AArch64_FCMLEv1i32rz 1783 +#define AArch64_FCMLEv1i64rz 1784 +#define AArch64_FCMLEv2i32rz 1785 +#define AArch64_FCMLEv2i64rz 1786 +#define AArch64_FCMLEv4i16rz 1787 +#define AArch64_FCMLEv4i32rz 1788 +#define AArch64_FCMLEv8i16rz 1789 +#define AArch64_FCMLT_PPzZ0_D 1790 +#define AArch64_FCMLT_PPzZ0_H 1791 +#define AArch64_FCMLT_PPzZ0_S 1792 +#define AArch64_FCMLTv1i16rz 1793 +#define AArch64_FCMLTv1i32rz 1794 +#define AArch64_FCMLTv1i64rz 1795 +#define AArch64_FCMLTv2i32rz 1796 +#define AArch64_FCMLTv2i64rz 1797 +#define AArch64_FCMLTv4i16rz 1798 +#define AArch64_FCMLTv4i32rz 1799 +#define AArch64_FCMLTv8i16rz 1800 +#define AArch64_FCMNE_PPzZ0_D 1801 +#define AArch64_FCMNE_PPzZ0_H 1802 +#define AArch64_FCMNE_PPzZ0_S 1803 +#define AArch64_FCMNE_PPzZZ_D 1804 +#define AArch64_FCMNE_PPzZZ_H 1805 +#define AArch64_FCMNE_PPzZZ_S 1806 +#define AArch64_FCMPDri 1807 +#define AArch64_FCMPDrr 1808 +#define AArch64_FCMPEDri 1809 +#define AArch64_FCMPEDrr 1810 +#define AArch64_FCMPEHri 1811 +#define AArch64_FCMPEHrr 1812 +#define AArch64_FCMPESri 1813 +#define AArch64_FCMPESrr 1814 +#define AArch64_FCMPHri 1815 +#define AArch64_FCMPHrr 1816 +#define AArch64_FCMPSri 1817 +#define AArch64_FCMPSrr 1818 +#define AArch64_FCMUO_PPzZZ_D 1819 +#define AArch64_FCMUO_PPzZZ_H 1820 +#define AArch64_FCMUO_PPzZZ_S 1821 +#define AArch64_FCPY_ZPmI_D 1822 +#define AArch64_FCPY_ZPmI_H 1823 +#define AArch64_FCPY_ZPmI_S 1824 +#define AArch64_FCSELDrrr 1825 +#define AArch64_FCSELHrrr 1826 +#define AArch64_FCSELSrrr 1827 +#define AArch64_FCVTASUWDr 1828 +#define AArch64_FCVTASUWHr 1829 +#define AArch64_FCVTASUWSr 1830 +#define AArch64_FCVTASUXDr 1831 +#define AArch64_FCVTASUXHr 1832 +#define AArch64_FCVTASUXSr 1833 +#define AArch64_FCVTASv1f16 1834 +#define AArch64_FCVTASv1i32 1835 +#define AArch64_FCVTASv1i64 1836 +#define AArch64_FCVTASv2f32 1837 +#define AArch64_FCVTASv2f64 1838 +#define AArch64_FCVTASv4f16 1839 +#define AArch64_FCVTASv4f32 1840 +#define AArch64_FCVTASv8f16 1841 +#define AArch64_FCVTAUUWDr 1842 +#define AArch64_FCVTAUUWHr 1843 +#define AArch64_FCVTAUUWSr 1844 +#define AArch64_FCVTAUUXDr 1845 +#define AArch64_FCVTAUUXHr 1846 +#define AArch64_FCVTAUUXSr 1847 +#define AArch64_FCVTAUv1f16 1848 +#define AArch64_FCVTAUv1i32 1849 +#define AArch64_FCVTAUv1i64 1850 +#define AArch64_FCVTAUv2f32 1851 +#define AArch64_FCVTAUv2f64 1852 +#define AArch64_FCVTAUv4f16 1853 +#define AArch64_FCVTAUv4f32 1854 +#define AArch64_FCVTAUv8f16 1855 +#define AArch64_FCVTDHr 1856 +#define AArch64_FCVTDSr 1857 +#define AArch64_FCVTHDr 1858 +#define AArch64_FCVTHSr 1859 +#define AArch64_FCVTLT_ZPmZ_HtoS 1860 +#define AArch64_FCVTLT_ZPmZ_StoD 1861 +#define AArch64_FCVTLv2i32 1862 +#define AArch64_FCVTLv4i16 1863 +#define AArch64_FCVTLv4i32 1864 +#define AArch64_FCVTLv8i16 1865 +#define AArch64_FCVTMSUWDr 1866 +#define AArch64_FCVTMSUWHr 1867 +#define AArch64_FCVTMSUWSr 1868 +#define AArch64_FCVTMSUXDr 1869 +#define AArch64_FCVTMSUXHr 1870 +#define AArch64_FCVTMSUXSr 1871 +#define AArch64_FCVTMSv1f16 1872 +#define AArch64_FCVTMSv1i32 1873 +#define AArch64_FCVTMSv1i64 1874 +#define AArch64_FCVTMSv2f32 1875 +#define AArch64_FCVTMSv2f64 1876 +#define AArch64_FCVTMSv4f16 1877 +#define AArch64_FCVTMSv4f32 1878 +#define AArch64_FCVTMSv8f16 1879 +#define AArch64_FCVTMUUWDr 1880 +#define AArch64_FCVTMUUWHr 1881 +#define AArch64_FCVTMUUWSr 1882 +#define AArch64_FCVTMUUXDr 1883 +#define AArch64_FCVTMUUXHr 1884 +#define AArch64_FCVTMUUXSr 1885 +#define AArch64_FCVTMUv1f16 1886 +#define AArch64_FCVTMUv1i32 1887 +#define AArch64_FCVTMUv1i64 1888 +#define AArch64_FCVTMUv2f32 1889 +#define AArch64_FCVTMUv2f64 1890 +#define AArch64_FCVTMUv4f16 1891 +#define AArch64_FCVTMUv4f32 1892 +#define AArch64_FCVTMUv8f16 1893 +#define AArch64_FCVTNSUWDr 1894 +#define AArch64_FCVTNSUWHr 1895 +#define AArch64_FCVTNSUWSr 1896 +#define AArch64_FCVTNSUXDr 1897 +#define AArch64_FCVTNSUXHr 1898 +#define AArch64_FCVTNSUXSr 1899 +#define AArch64_FCVTNSv1f16 1900 +#define AArch64_FCVTNSv1i32 1901 +#define AArch64_FCVTNSv1i64 1902 +#define AArch64_FCVTNSv2f32 1903 +#define AArch64_FCVTNSv2f64 1904 +#define AArch64_FCVTNSv4f16 1905 +#define AArch64_FCVTNSv4f32 1906 +#define AArch64_FCVTNSv8f16 1907 +#define AArch64_FCVTNT_ZPmZ_DtoS 1908 +#define AArch64_FCVTNT_ZPmZ_StoH 1909 +#define AArch64_FCVTNUUWDr 1910 +#define AArch64_FCVTNUUWHr 1911 +#define AArch64_FCVTNUUWSr 1912 +#define AArch64_FCVTNUUXDr 1913 +#define AArch64_FCVTNUUXHr 1914 +#define AArch64_FCVTNUUXSr 1915 +#define AArch64_FCVTNUv1f16 1916 +#define AArch64_FCVTNUv1i32 1917 +#define AArch64_FCVTNUv1i64 1918 +#define AArch64_FCVTNUv2f32 1919 +#define AArch64_FCVTNUv2f64 1920 +#define AArch64_FCVTNUv4f16 1921 +#define AArch64_FCVTNUv4f32 1922 +#define AArch64_FCVTNUv8f16 1923 +#define AArch64_FCVTNv2i32 1924 +#define AArch64_FCVTNv4i16 1925 +#define AArch64_FCVTNv4i32 1926 +#define AArch64_FCVTNv8i16 1927 +#define AArch64_FCVTPSUWDr 1928 +#define AArch64_FCVTPSUWHr 1929 +#define AArch64_FCVTPSUWSr 1930 +#define AArch64_FCVTPSUXDr 1931 +#define AArch64_FCVTPSUXHr 1932 +#define AArch64_FCVTPSUXSr 1933 +#define AArch64_FCVTPSv1f16 1934 +#define AArch64_FCVTPSv1i32 1935 +#define AArch64_FCVTPSv1i64 1936 +#define AArch64_FCVTPSv2f32 1937 +#define AArch64_FCVTPSv2f64 1938 +#define AArch64_FCVTPSv4f16 1939 +#define AArch64_FCVTPSv4f32 1940 +#define AArch64_FCVTPSv8f16 1941 +#define AArch64_FCVTPUUWDr 1942 +#define AArch64_FCVTPUUWHr 1943 +#define AArch64_FCVTPUUWSr 1944 +#define AArch64_FCVTPUUXDr 1945 +#define AArch64_FCVTPUUXHr 1946 +#define AArch64_FCVTPUUXSr 1947 +#define AArch64_FCVTPUv1f16 1948 +#define AArch64_FCVTPUv1i32 1949 +#define AArch64_FCVTPUv1i64 1950 +#define AArch64_FCVTPUv2f32 1951 +#define AArch64_FCVTPUv2f64 1952 +#define AArch64_FCVTPUv4f16 1953 +#define AArch64_FCVTPUv4f32 1954 +#define AArch64_FCVTPUv8f16 1955 +#define AArch64_FCVTSDr 1956 +#define AArch64_FCVTSHr 1957 +#define AArch64_FCVTXNT_ZPmZ_DtoS 1958 +#define AArch64_FCVTXNv1i64 1959 +#define AArch64_FCVTXNv2f32 1960 +#define AArch64_FCVTXNv4f32 1961 +#define AArch64_FCVTX_ZPmZ_DtoS 1962 +#define AArch64_FCVTZSSWDri 1963 +#define AArch64_FCVTZSSWHri 1964 +#define AArch64_FCVTZSSWSri 1965 +#define AArch64_FCVTZSSXDri 1966 +#define AArch64_FCVTZSSXHri 1967 +#define AArch64_FCVTZSSXSri 1968 +#define AArch64_FCVTZSUWDr 1969 +#define AArch64_FCVTZSUWHr 1970 +#define AArch64_FCVTZSUWSr 1971 +#define AArch64_FCVTZSUXDr 1972 +#define AArch64_FCVTZSUXHr 1973 +#define AArch64_FCVTZSUXSr 1974 +#define AArch64_FCVTZS_ZPmZ_DtoD 1975 +#define AArch64_FCVTZS_ZPmZ_DtoS 1976 +#define AArch64_FCVTZS_ZPmZ_HtoD 1977 +#define AArch64_FCVTZS_ZPmZ_HtoH 1978 +#define AArch64_FCVTZS_ZPmZ_HtoS 1979 +#define AArch64_FCVTZS_ZPmZ_StoD 1980 +#define AArch64_FCVTZS_ZPmZ_StoS 1981 +#define AArch64_FCVTZSd 1982 +#define AArch64_FCVTZSh 1983 +#define AArch64_FCVTZSs 1984 +#define AArch64_FCVTZSv1f16 1985 +#define AArch64_FCVTZSv1i32 1986 +#define AArch64_FCVTZSv1i64 1987 +#define AArch64_FCVTZSv2f32 1988 +#define AArch64_FCVTZSv2f64 1989 +#define AArch64_FCVTZSv2i32_shift 1990 +#define AArch64_FCVTZSv2i64_shift 1991 +#define AArch64_FCVTZSv4f16 1992 +#define AArch64_FCVTZSv4f32 1993 +#define AArch64_FCVTZSv4i16_shift 1994 +#define AArch64_FCVTZSv4i32_shift 1995 +#define AArch64_FCVTZSv8f16 1996 +#define AArch64_FCVTZSv8i16_shift 1997 +#define AArch64_FCVTZUSWDri 1998 +#define AArch64_FCVTZUSWHri 1999 +#define AArch64_FCVTZUSWSri 2000 +#define AArch64_FCVTZUSXDri 2001 +#define AArch64_FCVTZUSXHri 2002 +#define AArch64_FCVTZUSXSri 2003 +#define AArch64_FCVTZUUWDr 2004 +#define AArch64_FCVTZUUWHr 2005 +#define AArch64_FCVTZUUWSr 2006 +#define AArch64_FCVTZUUXDr 2007 +#define AArch64_FCVTZUUXHr 2008 +#define AArch64_FCVTZUUXSr 2009 +#define AArch64_FCVTZU_ZPmZ_DtoD 2010 +#define AArch64_FCVTZU_ZPmZ_DtoS 2011 +#define AArch64_FCVTZU_ZPmZ_HtoD 2012 +#define AArch64_FCVTZU_ZPmZ_HtoH 2013 +#define AArch64_FCVTZU_ZPmZ_HtoS 2014 +#define AArch64_FCVTZU_ZPmZ_StoD 2015 +#define AArch64_FCVTZU_ZPmZ_StoS 2016 +#define AArch64_FCVTZUd 2017 +#define AArch64_FCVTZUh 2018 +#define AArch64_FCVTZUs 2019 +#define AArch64_FCVTZUv1f16 2020 +#define AArch64_FCVTZUv1i32 2021 +#define AArch64_FCVTZUv1i64 2022 +#define AArch64_FCVTZUv2f32 2023 +#define AArch64_FCVTZUv2f64 2024 +#define AArch64_FCVTZUv2i32_shift 2025 +#define AArch64_FCVTZUv2i64_shift 2026 +#define AArch64_FCVTZUv4f16 2027 +#define AArch64_FCVTZUv4f32 2028 +#define AArch64_FCVTZUv4i16_shift 2029 +#define AArch64_FCVTZUv4i32_shift 2030 +#define AArch64_FCVTZUv8f16 2031 +#define AArch64_FCVTZUv8i16_shift 2032 +#define AArch64_FCVT_ZPmZ_DtoH 2033 +#define AArch64_FCVT_ZPmZ_DtoS 2034 +#define AArch64_FCVT_ZPmZ_HtoD 2035 +#define AArch64_FCVT_ZPmZ_HtoS 2036 +#define AArch64_FCVT_ZPmZ_StoD 2037 +#define AArch64_FCVT_ZPmZ_StoH 2038 +#define AArch64_FDIVDrr 2039 +#define AArch64_FDIVHrr 2040 +#define AArch64_FDIVR_ZPmZ_D 2041 +#define AArch64_FDIVR_ZPmZ_H 2042 +#define AArch64_FDIVR_ZPmZ_S 2043 +#define AArch64_FDIVSrr 2044 +#define AArch64_FDIV_ZPmZ_D 2045 +#define AArch64_FDIV_ZPmZ_H 2046 +#define AArch64_FDIV_ZPmZ_S 2047 +#define AArch64_FDIVv2f32 2048 +#define AArch64_FDIVv2f64 2049 +#define AArch64_FDIVv4f16 2050 +#define AArch64_FDIVv4f32 2051 +#define AArch64_FDIVv8f16 2052 +#define AArch64_FDUP_ZI_D 2053 +#define AArch64_FDUP_ZI_H 2054 +#define AArch64_FDUP_ZI_S 2055 +#define AArch64_FEXPA_ZZ_D 2056 +#define AArch64_FEXPA_ZZ_H 2057 +#define AArch64_FEXPA_ZZ_S 2058 +#define AArch64_FJCVTZS 2059 +#define AArch64_FLOGB_ZPmZ_D 2060 +#define AArch64_FLOGB_ZPmZ_H 2061 +#define AArch64_FLOGB_ZPmZ_S 2062 +#define AArch64_FMADDDrrr 2063 +#define AArch64_FMADDHrrr 2064 +#define AArch64_FMADDSrrr 2065 +#define AArch64_FMAD_ZPmZZ_D 2066 +#define AArch64_FMAD_ZPmZZ_H 2067 +#define AArch64_FMAD_ZPmZZ_S 2068 +#define AArch64_FMAXDrr 2069 +#define AArch64_FMAXHrr 2070 +#define AArch64_FMAXNMDrr 2071 +#define AArch64_FMAXNMHrr 2072 +#define AArch64_FMAXNMP_ZPmZZ_D 2073 +#define AArch64_FMAXNMP_ZPmZZ_H 2074 +#define AArch64_FMAXNMP_ZPmZZ_S 2075 +#define AArch64_FMAXNMPv2f32 2076 +#define AArch64_FMAXNMPv2f64 2077 +#define AArch64_FMAXNMPv2i16p 2078 +#define AArch64_FMAXNMPv2i32p 2079 +#define AArch64_FMAXNMPv2i64p 2080 +#define AArch64_FMAXNMPv4f16 2081 +#define AArch64_FMAXNMPv4f32 2082 +#define AArch64_FMAXNMPv8f16 2083 +#define AArch64_FMAXNMSrr 2084 +#define AArch64_FMAXNMV_VPZ_D 2085 +#define AArch64_FMAXNMV_VPZ_H 2086 +#define AArch64_FMAXNMV_VPZ_S 2087 +#define AArch64_FMAXNMVv4i16v 2088 +#define AArch64_FMAXNMVv4i32v 2089 +#define AArch64_FMAXNMVv8i16v 2090 +#define AArch64_FMAXNM_ZPmI_D 2091 +#define AArch64_FMAXNM_ZPmI_H 2092 +#define AArch64_FMAXNM_ZPmI_S 2093 +#define AArch64_FMAXNM_ZPmZ_D 2094 +#define AArch64_FMAXNM_ZPmZ_H 2095 +#define AArch64_FMAXNM_ZPmZ_S 2096 +#define AArch64_FMAXNMv2f32 2097 +#define AArch64_FMAXNMv2f64 2098 +#define AArch64_FMAXNMv4f16 2099 +#define AArch64_FMAXNMv4f32 2100 +#define AArch64_FMAXNMv8f16 2101 +#define AArch64_FMAXP_ZPmZZ_D 2102 +#define AArch64_FMAXP_ZPmZZ_H 2103 +#define AArch64_FMAXP_ZPmZZ_S 2104 +#define AArch64_FMAXPv2f32 2105 +#define AArch64_FMAXPv2f64 2106 +#define AArch64_FMAXPv2i16p 2107 +#define AArch64_FMAXPv2i32p 2108 +#define AArch64_FMAXPv2i64p 2109 +#define AArch64_FMAXPv4f16 2110 +#define AArch64_FMAXPv4f32 2111 +#define AArch64_FMAXPv8f16 2112 +#define AArch64_FMAXSrr 2113 +#define AArch64_FMAXV_VPZ_D 2114 +#define AArch64_FMAXV_VPZ_H 2115 +#define AArch64_FMAXV_VPZ_S 2116 +#define AArch64_FMAXVv4i16v 2117 +#define AArch64_FMAXVv4i32v 2118 +#define AArch64_FMAXVv8i16v 2119 +#define AArch64_FMAX_ZPmI_D 2120 +#define AArch64_FMAX_ZPmI_H 2121 +#define AArch64_FMAX_ZPmI_S 2122 +#define AArch64_FMAX_ZPmZ_D 2123 +#define AArch64_FMAX_ZPmZ_H 2124 +#define AArch64_FMAX_ZPmZ_S 2125 +#define AArch64_FMAXv2f32 2126 +#define AArch64_FMAXv2f64 2127 +#define AArch64_FMAXv4f16 2128 +#define AArch64_FMAXv4f32 2129 +#define AArch64_FMAXv8f16 2130 +#define AArch64_FMINDrr 2131 +#define AArch64_FMINHrr 2132 +#define AArch64_FMINNMDrr 2133 +#define AArch64_FMINNMHrr 2134 +#define AArch64_FMINNMP_ZPmZZ_D 2135 +#define AArch64_FMINNMP_ZPmZZ_H 2136 +#define AArch64_FMINNMP_ZPmZZ_S 2137 +#define AArch64_FMINNMPv2f32 2138 +#define AArch64_FMINNMPv2f64 2139 +#define AArch64_FMINNMPv2i16p 2140 +#define AArch64_FMINNMPv2i32p 2141 +#define AArch64_FMINNMPv2i64p 2142 +#define AArch64_FMINNMPv4f16 2143 +#define AArch64_FMINNMPv4f32 2144 +#define AArch64_FMINNMPv8f16 2145 +#define AArch64_FMINNMSrr 2146 +#define AArch64_FMINNMV_VPZ_D 2147 +#define AArch64_FMINNMV_VPZ_H 2148 +#define AArch64_FMINNMV_VPZ_S 2149 +#define AArch64_FMINNMVv4i16v 2150 +#define AArch64_FMINNMVv4i32v 2151 +#define AArch64_FMINNMVv8i16v 2152 +#define AArch64_FMINNM_ZPmI_D 2153 +#define AArch64_FMINNM_ZPmI_H 2154 +#define AArch64_FMINNM_ZPmI_S 2155 +#define AArch64_FMINNM_ZPmZ_D 2156 +#define AArch64_FMINNM_ZPmZ_H 2157 +#define AArch64_FMINNM_ZPmZ_S 2158 +#define AArch64_FMINNMv2f32 2159 +#define AArch64_FMINNMv2f64 2160 +#define AArch64_FMINNMv4f16 2161 +#define AArch64_FMINNMv4f32 2162 +#define AArch64_FMINNMv8f16 2163 +#define AArch64_FMINP_ZPmZZ_D 2164 +#define AArch64_FMINP_ZPmZZ_H 2165 +#define AArch64_FMINP_ZPmZZ_S 2166 +#define AArch64_FMINPv2f32 2167 +#define AArch64_FMINPv2f64 2168 +#define AArch64_FMINPv2i16p 2169 +#define AArch64_FMINPv2i32p 2170 +#define AArch64_FMINPv2i64p 2171 +#define AArch64_FMINPv4f16 2172 +#define AArch64_FMINPv4f32 2173 +#define AArch64_FMINPv8f16 2174 +#define AArch64_FMINSrr 2175 +#define AArch64_FMINV_VPZ_D 2176 +#define AArch64_FMINV_VPZ_H 2177 +#define AArch64_FMINV_VPZ_S 2178 +#define AArch64_FMINVv4i16v 2179 +#define AArch64_FMINVv4i32v 2180 +#define AArch64_FMINVv8i16v 2181 +#define AArch64_FMIN_ZPmI_D 2182 +#define AArch64_FMIN_ZPmI_H 2183 +#define AArch64_FMIN_ZPmI_S 2184 +#define AArch64_FMIN_ZPmZ_D 2185 +#define AArch64_FMIN_ZPmZ_H 2186 +#define AArch64_FMIN_ZPmZ_S 2187 +#define AArch64_FMINv2f32 2188 +#define AArch64_FMINv2f64 2189 +#define AArch64_FMINv4f16 2190 +#define AArch64_FMINv4f32 2191 +#define AArch64_FMINv8f16 2192 +#define AArch64_FMLAL2lanev4f16 2193 +#define AArch64_FMLAL2lanev8f16 2194 +#define AArch64_FMLAL2v4f16 2195 +#define AArch64_FMLAL2v8f16 2196 +#define AArch64_FMLALB_ZZZI_SHH 2197 +#define AArch64_FMLALB_ZZZ_SHH 2198 +#define AArch64_FMLALT_ZZZI_SHH 2199 +#define AArch64_FMLALT_ZZZ_SHH 2200 +#define AArch64_FMLALlanev4f16 2201 +#define AArch64_FMLALlanev8f16 2202 +#define AArch64_FMLALv4f16 2203 +#define AArch64_FMLALv8f16 2204 +#define AArch64_FMLA_ZPmZZ_D 2205 +#define AArch64_FMLA_ZPmZZ_H 2206 +#define AArch64_FMLA_ZPmZZ_S 2207 +#define AArch64_FMLA_ZZZI_D 2208 +#define AArch64_FMLA_ZZZI_H 2209 +#define AArch64_FMLA_ZZZI_S 2210 +#define AArch64_FMLAv1i16_indexed 2211 +#define AArch64_FMLAv1i32_indexed 2212 +#define AArch64_FMLAv1i64_indexed 2213 +#define AArch64_FMLAv2f32 2214 +#define AArch64_FMLAv2f64 2215 +#define AArch64_FMLAv2i32_indexed 2216 +#define AArch64_FMLAv2i64_indexed 2217 +#define AArch64_FMLAv4f16 2218 +#define AArch64_FMLAv4f32 2219 +#define AArch64_FMLAv4i16_indexed 2220 +#define AArch64_FMLAv4i32_indexed 2221 +#define AArch64_FMLAv8f16 2222 +#define AArch64_FMLAv8i16_indexed 2223 +#define AArch64_FMLSL2lanev4f16 2224 +#define AArch64_FMLSL2lanev8f16 2225 +#define AArch64_FMLSL2v4f16 2226 +#define AArch64_FMLSL2v8f16 2227 +#define AArch64_FMLSLB_ZZZI_SHH 2228 +#define AArch64_FMLSLB_ZZZ_SHH 2229 +#define AArch64_FMLSLT_ZZZI_SHH 2230 +#define AArch64_FMLSLT_ZZZ_SHH 2231 +#define AArch64_FMLSLlanev4f16 2232 +#define AArch64_FMLSLlanev8f16 2233 +#define AArch64_FMLSLv4f16 2234 +#define AArch64_FMLSLv8f16 2235 +#define AArch64_FMLS_ZPmZZ_D 2236 +#define AArch64_FMLS_ZPmZZ_H 2237 +#define AArch64_FMLS_ZPmZZ_S 2238 +#define AArch64_FMLS_ZZZI_D 2239 +#define AArch64_FMLS_ZZZI_H 2240 +#define AArch64_FMLS_ZZZI_S 2241 +#define AArch64_FMLSv1i16_indexed 2242 +#define AArch64_FMLSv1i32_indexed 2243 +#define AArch64_FMLSv1i64_indexed 2244 +#define AArch64_FMLSv2f32 2245 +#define AArch64_FMLSv2f64 2246 +#define AArch64_FMLSv2i32_indexed 2247 +#define AArch64_FMLSv2i64_indexed 2248 +#define AArch64_FMLSv4f16 2249 +#define AArch64_FMLSv4f32 2250 +#define AArch64_FMLSv4i16_indexed 2251 +#define AArch64_FMLSv4i32_indexed 2252 +#define AArch64_FMLSv8f16 2253 +#define AArch64_FMLSv8i16_indexed 2254 +#define AArch64_FMMLA_ZZZ_D 2255 +#define AArch64_FMMLA_ZZZ_S 2256 +#define AArch64_FMOPA_MPPZZ_D 2257 +#define AArch64_FMOPA_MPPZZ_S 2258 +#define AArch64_FMOPS_MPPZZ_D 2259 +#define AArch64_FMOPS_MPPZZ_S 2260 +#define AArch64_FMOVDXHighr 2261 +#define AArch64_FMOVDXr 2262 +#define AArch64_FMOVDi 2263 +#define AArch64_FMOVDr 2264 +#define AArch64_FMOVHWr 2265 +#define AArch64_FMOVHXr 2266 +#define AArch64_FMOVHi 2267 +#define AArch64_FMOVHr 2268 +#define AArch64_FMOVSWr 2269 +#define AArch64_FMOVSi 2270 +#define AArch64_FMOVSr 2271 +#define AArch64_FMOVWHr 2272 +#define AArch64_FMOVWSr 2273 +#define AArch64_FMOVXDHighr 2274 +#define AArch64_FMOVXDr 2275 +#define AArch64_FMOVXHr 2276 +#define AArch64_FMOVv2f32_ns 2277 +#define AArch64_FMOVv2f64_ns 2278 +#define AArch64_FMOVv4f16_ns 2279 +#define AArch64_FMOVv4f32_ns 2280 +#define AArch64_FMOVv8f16_ns 2281 +#define AArch64_FMSB_ZPmZZ_D 2282 +#define AArch64_FMSB_ZPmZZ_H 2283 +#define AArch64_FMSB_ZPmZZ_S 2284 +#define AArch64_FMSUBDrrr 2285 +#define AArch64_FMSUBHrrr 2286 +#define AArch64_FMSUBSrrr 2287 +#define AArch64_FMULDrr 2288 +#define AArch64_FMULHrr 2289 +#define AArch64_FMULSrr 2290 +#define AArch64_FMULX16 2291 +#define AArch64_FMULX32 2292 +#define AArch64_FMULX64 2293 +#define AArch64_FMULX_ZPmZ_D 2294 +#define AArch64_FMULX_ZPmZ_H 2295 +#define AArch64_FMULX_ZPmZ_S 2296 +#define AArch64_FMULXv1i16_indexed 2297 +#define AArch64_FMULXv1i32_indexed 2298 +#define AArch64_FMULXv1i64_indexed 2299 +#define AArch64_FMULXv2f32 2300 +#define AArch64_FMULXv2f64 2301 +#define AArch64_FMULXv2i32_indexed 2302 +#define AArch64_FMULXv2i64_indexed 2303 +#define AArch64_FMULXv4f16 2304 +#define AArch64_FMULXv4f32 2305 +#define AArch64_FMULXv4i16_indexed 2306 +#define AArch64_FMULXv4i32_indexed 2307 +#define AArch64_FMULXv8f16 2308 +#define AArch64_FMULXv8i16_indexed 2309 +#define AArch64_FMUL_ZPmI_D 2310 +#define AArch64_FMUL_ZPmI_H 2311 +#define AArch64_FMUL_ZPmI_S 2312 +#define AArch64_FMUL_ZPmZ_D 2313 +#define AArch64_FMUL_ZPmZ_H 2314 +#define AArch64_FMUL_ZPmZ_S 2315 +#define AArch64_FMUL_ZZZI_D 2316 +#define AArch64_FMUL_ZZZI_H 2317 +#define AArch64_FMUL_ZZZI_S 2318 +#define AArch64_FMUL_ZZZ_D 2319 +#define AArch64_FMUL_ZZZ_H 2320 +#define AArch64_FMUL_ZZZ_S 2321 +#define AArch64_FMULv1i16_indexed 2322 +#define AArch64_FMULv1i32_indexed 2323 +#define AArch64_FMULv1i64_indexed 2324 +#define AArch64_FMULv2f32 2325 +#define AArch64_FMULv2f64 2326 +#define AArch64_FMULv2i32_indexed 2327 +#define AArch64_FMULv2i64_indexed 2328 +#define AArch64_FMULv4f16 2329 +#define AArch64_FMULv4f32 2330 +#define AArch64_FMULv4i16_indexed 2331 +#define AArch64_FMULv4i32_indexed 2332 +#define AArch64_FMULv8f16 2333 +#define AArch64_FMULv8i16_indexed 2334 +#define AArch64_FNEGDr 2335 +#define AArch64_FNEGHr 2336 +#define AArch64_FNEGSr 2337 +#define AArch64_FNEG_ZPmZ_D 2338 +#define AArch64_FNEG_ZPmZ_H 2339 +#define AArch64_FNEG_ZPmZ_S 2340 +#define AArch64_FNEGv2f32 2341 +#define AArch64_FNEGv2f64 2342 +#define AArch64_FNEGv4f16 2343 +#define AArch64_FNEGv4f32 2344 +#define AArch64_FNEGv8f16 2345 +#define AArch64_FNMADDDrrr 2346 +#define AArch64_FNMADDHrrr 2347 +#define AArch64_FNMADDSrrr 2348 +#define AArch64_FNMAD_ZPmZZ_D 2349 +#define AArch64_FNMAD_ZPmZZ_H 2350 +#define AArch64_FNMAD_ZPmZZ_S 2351 +#define AArch64_FNMLA_ZPmZZ_D 2352 +#define AArch64_FNMLA_ZPmZZ_H 2353 +#define AArch64_FNMLA_ZPmZZ_S 2354 +#define AArch64_FNMLS_ZPmZZ_D 2355 +#define AArch64_FNMLS_ZPmZZ_H 2356 +#define AArch64_FNMLS_ZPmZZ_S 2357 +#define AArch64_FNMSB_ZPmZZ_D 2358 +#define AArch64_FNMSB_ZPmZZ_H 2359 +#define AArch64_FNMSB_ZPmZZ_S 2360 +#define AArch64_FNMSUBDrrr 2361 +#define AArch64_FNMSUBHrrr 2362 +#define AArch64_FNMSUBSrrr 2363 +#define AArch64_FNMULDrr 2364 +#define AArch64_FNMULHrr 2365 +#define AArch64_FNMULSrr 2366 +#define AArch64_FRECPE_ZZ_D 2367 +#define AArch64_FRECPE_ZZ_H 2368 +#define AArch64_FRECPE_ZZ_S 2369 +#define AArch64_FRECPEv1f16 2370 +#define AArch64_FRECPEv1i32 2371 +#define AArch64_FRECPEv1i64 2372 +#define AArch64_FRECPEv2f32 2373 +#define AArch64_FRECPEv2f64 2374 +#define AArch64_FRECPEv4f16 2375 +#define AArch64_FRECPEv4f32 2376 +#define AArch64_FRECPEv8f16 2377 +#define AArch64_FRECPS16 2378 +#define AArch64_FRECPS32 2379 +#define AArch64_FRECPS64 2380 +#define AArch64_FRECPS_ZZZ_D 2381 +#define AArch64_FRECPS_ZZZ_H 2382 +#define AArch64_FRECPS_ZZZ_S 2383 +#define AArch64_FRECPSv2f32 2384 +#define AArch64_FRECPSv2f64 2385 +#define AArch64_FRECPSv4f16 2386 +#define AArch64_FRECPSv4f32 2387 +#define AArch64_FRECPSv8f16 2388 +#define AArch64_FRECPX_ZPmZ_D 2389 +#define AArch64_FRECPX_ZPmZ_H 2390 +#define AArch64_FRECPX_ZPmZ_S 2391 +#define AArch64_FRECPXv1f16 2392 +#define AArch64_FRECPXv1i32 2393 +#define AArch64_FRECPXv1i64 2394 +#define AArch64_FRINT32XDr 2395 +#define AArch64_FRINT32XSr 2396 +#define AArch64_FRINT32Xv2f32 2397 +#define AArch64_FRINT32Xv2f64 2398 +#define AArch64_FRINT32Xv4f32 2399 +#define AArch64_FRINT32ZDr 2400 +#define AArch64_FRINT32ZSr 2401 +#define AArch64_FRINT32Zv2f32 2402 +#define AArch64_FRINT32Zv2f64 2403 +#define AArch64_FRINT32Zv4f32 2404 +#define AArch64_FRINT64XDr 2405 +#define AArch64_FRINT64XSr 2406 +#define AArch64_FRINT64Xv2f32 2407 +#define AArch64_FRINT64Xv2f64 2408 +#define AArch64_FRINT64Xv4f32 2409 +#define AArch64_FRINT64ZDr 2410 +#define AArch64_FRINT64ZSr 2411 +#define AArch64_FRINT64Zv2f32 2412 +#define AArch64_FRINT64Zv2f64 2413 +#define AArch64_FRINT64Zv4f32 2414 +#define AArch64_FRINTADr 2415 +#define AArch64_FRINTAHr 2416 +#define AArch64_FRINTASr 2417 +#define AArch64_FRINTA_ZPmZ_D 2418 +#define AArch64_FRINTA_ZPmZ_H 2419 +#define AArch64_FRINTA_ZPmZ_S 2420 +#define AArch64_FRINTAv2f32 2421 +#define AArch64_FRINTAv2f64 2422 +#define AArch64_FRINTAv4f16 2423 +#define AArch64_FRINTAv4f32 2424 +#define AArch64_FRINTAv8f16 2425 +#define AArch64_FRINTIDr 2426 +#define AArch64_FRINTIHr 2427 +#define AArch64_FRINTISr 2428 +#define AArch64_FRINTI_ZPmZ_D 2429 +#define AArch64_FRINTI_ZPmZ_H 2430 +#define AArch64_FRINTI_ZPmZ_S 2431 +#define AArch64_FRINTIv2f32 2432 +#define AArch64_FRINTIv2f64 2433 +#define AArch64_FRINTIv4f16 2434 +#define AArch64_FRINTIv4f32 2435 +#define AArch64_FRINTIv8f16 2436 +#define AArch64_FRINTMDr 2437 +#define AArch64_FRINTMHr 2438 +#define AArch64_FRINTMSr 2439 +#define AArch64_FRINTM_ZPmZ_D 2440 +#define AArch64_FRINTM_ZPmZ_H 2441 +#define AArch64_FRINTM_ZPmZ_S 2442 +#define AArch64_FRINTMv2f32 2443 +#define AArch64_FRINTMv2f64 2444 +#define AArch64_FRINTMv4f16 2445 +#define AArch64_FRINTMv4f32 2446 +#define AArch64_FRINTMv8f16 2447 +#define AArch64_FRINTNDr 2448 +#define AArch64_FRINTNHr 2449 +#define AArch64_FRINTNSr 2450 +#define AArch64_FRINTN_ZPmZ_D 2451 +#define AArch64_FRINTN_ZPmZ_H 2452 +#define AArch64_FRINTN_ZPmZ_S 2453 +#define AArch64_FRINTNv2f32 2454 +#define AArch64_FRINTNv2f64 2455 +#define AArch64_FRINTNv4f16 2456 +#define AArch64_FRINTNv4f32 2457 +#define AArch64_FRINTNv8f16 2458 +#define AArch64_FRINTPDr 2459 +#define AArch64_FRINTPHr 2460 +#define AArch64_FRINTPSr 2461 +#define AArch64_FRINTP_ZPmZ_D 2462 +#define AArch64_FRINTP_ZPmZ_H 2463 +#define AArch64_FRINTP_ZPmZ_S 2464 +#define AArch64_FRINTPv2f32 2465 +#define AArch64_FRINTPv2f64 2466 +#define AArch64_FRINTPv4f16 2467 +#define AArch64_FRINTPv4f32 2468 +#define AArch64_FRINTPv8f16 2469 +#define AArch64_FRINTXDr 2470 +#define AArch64_FRINTXHr 2471 +#define AArch64_FRINTXSr 2472 +#define AArch64_FRINTX_ZPmZ_D 2473 +#define AArch64_FRINTX_ZPmZ_H 2474 +#define AArch64_FRINTX_ZPmZ_S 2475 +#define AArch64_FRINTXv2f32 2476 +#define AArch64_FRINTXv2f64 2477 +#define AArch64_FRINTXv4f16 2478 +#define AArch64_FRINTXv4f32 2479 +#define AArch64_FRINTXv8f16 2480 +#define AArch64_FRINTZDr 2481 +#define AArch64_FRINTZHr 2482 +#define AArch64_FRINTZSr 2483 +#define AArch64_FRINTZ_ZPmZ_D 2484 +#define AArch64_FRINTZ_ZPmZ_H 2485 +#define AArch64_FRINTZ_ZPmZ_S 2486 +#define AArch64_FRINTZv2f32 2487 +#define AArch64_FRINTZv2f64 2488 +#define AArch64_FRINTZv4f16 2489 +#define AArch64_FRINTZv4f32 2490 +#define AArch64_FRINTZv8f16 2491 +#define AArch64_FRSQRTE_ZZ_D 2492 +#define AArch64_FRSQRTE_ZZ_H 2493 +#define AArch64_FRSQRTE_ZZ_S 2494 +#define AArch64_FRSQRTEv1f16 2495 +#define AArch64_FRSQRTEv1i32 2496 +#define AArch64_FRSQRTEv1i64 2497 +#define AArch64_FRSQRTEv2f32 2498 +#define AArch64_FRSQRTEv2f64 2499 +#define AArch64_FRSQRTEv4f16 2500 +#define AArch64_FRSQRTEv4f32 2501 +#define AArch64_FRSQRTEv8f16 2502 +#define AArch64_FRSQRTS16 2503 +#define AArch64_FRSQRTS32 2504 +#define AArch64_FRSQRTS64 2505 +#define AArch64_FRSQRTS_ZZZ_D 2506 +#define AArch64_FRSQRTS_ZZZ_H 2507 +#define AArch64_FRSQRTS_ZZZ_S 2508 +#define AArch64_FRSQRTSv2f32 2509 +#define AArch64_FRSQRTSv2f64 2510 +#define AArch64_FRSQRTSv4f16 2511 +#define AArch64_FRSQRTSv4f32 2512 +#define AArch64_FRSQRTSv8f16 2513 +#define AArch64_FSCALE_ZPmZ_D 2514 +#define AArch64_FSCALE_ZPmZ_H 2515 +#define AArch64_FSCALE_ZPmZ_S 2516 +#define AArch64_FSQRTDr 2517 +#define AArch64_FSQRTHr 2518 +#define AArch64_FSQRTSr 2519 +#define AArch64_FSQRT_ZPmZ_D 2520 +#define AArch64_FSQRT_ZPmZ_H 2521 +#define AArch64_FSQRT_ZPmZ_S 2522 +#define AArch64_FSQRTv2f32 2523 +#define AArch64_FSQRTv2f64 2524 +#define AArch64_FSQRTv4f16 2525 +#define AArch64_FSQRTv4f32 2526 +#define AArch64_FSQRTv8f16 2527 +#define AArch64_FSUBDrr 2528 +#define AArch64_FSUBHrr 2529 +#define AArch64_FSUBR_ZPmI_D 2530 +#define AArch64_FSUBR_ZPmI_H 2531 +#define AArch64_FSUBR_ZPmI_S 2532 +#define AArch64_FSUBR_ZPmZ_D 2533 +#define AArch64_FSUBR_ZPmZ_H 2534 +#define AArch64_FSUBR_ZPmZ_S 2535 +#define AArch64_FSUBSrr 2536 +#define AArch64_FSUB_ZPmI_D 2537 +#define AArch64_FSUB_ZPmI_H 2538 +#define AArch64_FSUB_ZPmI_S 2539 +#define AArch64_FSUB_ZPmZ_D 2540 +#define AArch64_FSUB_ZPmZ_H 2541 +#define AArch64_FSUB_ZPmZ_S 2542 +#define AArch64_FSUB_ZZZ_D 2543 +#define AArch64_FSUB_ZZZ_H 2544 +#define AArch64_FSUB_ZZZ_S 2545 +#define AArch64_FSUBv2f32 2546 +#define AArch64_FSUBv2f64 2547 +#define AArch64_FSUBv4f16 2548 +#define AArch64_FSUBv4f32 2549 +#define AArch64_FSUBv8f16 2550 +#define AArch64_FTMAD_ZZI_D 2551 +#define AArch64_FTMAD_ZZI_H 2552 +#define AArch64_FTMAD_ZZI_S 2553 +#define AArch64_FTSMUL_ZZZ_D 2554 +#define AArch64_FTSMUL_ZZZ_H 2555 +#define AArch64_FTSMUL_ZZZ_S 2556 +#define AArch64_FTSSEL_ZZZ_D 2557 +#define AArch64_FTSSEL_ZZZ_H 2558 +#define AArch64_FTSSEL_ZZZ_S 2559 +#define AArch64_GLD1B_D_IMM_REAL 2560 +#define AArch64_GLD1B_D_REAL 2561 +#define AArch64_GLD1B_D_SXTW_REAL 2562 +#define AArch64_GLD1B_D_UXTW_REAL 2563 +#define AArch64_GLD1B_S_IMM_REAL 2564 +#define AArch64_GLD1B_S_SXTW_REAL 2565 +#define AArch64_GLD1B_S_UXTW_REAL 2566 +#define AArch64_GLD1D_IMM_REAL 2567 +#define AArch64_GLD1D_REAL 2568 +#define AArch64_GLD1D_SCALED_REAL 2569 +#define AArch64_GLD1D_SXTW_REAL 2570 +#define AArch64_GLD1D_SXTW_SCALED_REAL 2571 +#define AArch64_GLD1D_UXTW_REAL 2572 +#define AArch64_GLD1D_UXTW_SCALED_REAL 2573 +#define AArch64_GLD1H_D_IMM_REAL 2574 +#define AArch64_GLD1H_D_REAL 2575 +#define AArch64_GLD1H_D_SCALED_REAL 2576 +#define AArch64_GLD1H_D_SXTW_REAL 2577 +#define AArch64_GLD1H_D_SXTW_SCALED_REAL 2578 +#define AArch64_GLD1H_D_UXTW_REAL 2579 +#define AArch64_GLD1H_D_UXTW_SCALED_REAL 2580 +#define AArch64_GLD1H_S_IMM_REAL 2581 +#define AArch64_GLD1H_S_SXTW_REAL 2582 +#define AArch64_GLD1H_S_SXTW_SCALED_REAL 2583 +#define AArch64_GLD1H_S_UXTW_REAL 2584 +#define AArch64_GLD1H_S_UXTW_SCALED_REAL 2585 +#define AArch64_GLD1SB_D_IMM_REAL 2586 +#define AArch64_GLD1SB_D_REAL 2587 +#define AArch64_GLD1SB_D_SXTW_REAL 2588 +#define AArch64_GLD1SB_D_UXTW_REAL 2589 +#define AArch64_GLD1SB_S_IMM_REAL 2590 +#define AArch64_GLD1SB_S_SXTW_REAL 2591 +#define AArch64_GLD1SB_S_UXTW_REAL 2592 +#define AArch64_GLD1SH_D_IMM_REAL 2593 +#define AArch64_GLD1SH_D_REAL 2594 +#define AArch64_GLD1SH_D_SCALED_REAL 2595 +#define AArch64_GLD1SH_D_SXTW_REAL 2596 +#define AArch64_GLD1SH_D_SXTW_SCALED_REAL 2597 +#define AArch64_GLD1SH_D_UXTW_REAL 2598 +#define AArch64_GLD1SH_D_UXTW_SCALED_REAL 2599 +#define AArch64_GLD1SH_S_IMM_REAL 2600 +#define AArch64_GLD1SH_S_SXTW_REAL 2601 +#define AArch64_GLD1SH_S_SXTW_SCALED_REAL 2602 +#define AArch64_GLD1SH_S_UXTW_REAL 2603 +#define AArch64_GLD1SH_S_UXTW_SCALED_REAL 2604 +#define AArch64_GLD1SW_D_IMM_REAL 2605 +#define AArch64_GLD1SW_D_REAL 2606 +#define AArch64_GLD1SW_D_SCALED_REAL 2607 +#define AArch64_GLD1SW_D_SXTW_REAL 2608 +#define AArch64_GLD1SW_D_SXTW_SCALED_REAL 2609 +#define AArch64_GLD1SW_D_UXTW_REAL 2610 +#define AArch64_GLD1SW_D_UXTW_SCALED_REAL 2611 +#define AArch64_GLD1W_D_IMM_REAL 2612 +#define AArch64_GLD1W_D_REAL 2613 +#define AArch64_GLD1W_D_SCALED_REAL 2614 +#define AArch64_GLD1W_D_SXTW_REAL 2615 +#define AArch64_GLD1W_D_SXTW_SCALED_REAL 2616 +#define AArch64_GLD1W_D_UXTW_REAL 2617 +#define AArch64_GLD1W_D_UXTW_SCALED_REAL 2618 +#define AArch64_GLD1W_IMM_REAL 2619 +#define AArch64_GLD1W_SXTW_REAL 2620 +#define AArch64_GLD1W_SXTW_SCALED_REAL 2621 +#define AArch64_GLD1W_UXTW_REAL 2622 +#define AArch64_GLD1W_UXTW_SCALED_REAL 2623 +#define AArch64_GLDFF1B_D_IMM_REAL 2624 +#define AArch64_GLDFF1B_D_REAL 2625 +#define AArch64_GLDFF1B_D_SXTW_REAL 2626 +#define AArch64_GLDFF1B_D_UXTW_REAL 2627 +#define AArch64_GLDFF1B_S_IMM_REAL 2628 +#define AArch64_GLDFF1B_S_SXTW_REAL 2629 +#define AArch64_GLDFF1B_S_UXTW_REAL 2630 +#define AArch64_GLDFF1D_IMM_REAL 2631 +#define AArch64_GLDFF1D_REAL 2632 +#define AArch64_GLDFF1D_SCALED_REAL 2633 +#define AArch64_GLDFF1D_SXTW_REAL 2634 +#define AArch64_GLDFF1D_SXTW_SCALED_REAL 2635 +#define AArch64_GLDFF1D_UXTW_REAL 2636 +#define AArch64_GLDFF1D_UXTW_SCALED_REAL 2637 +#define AArch64_GLDFF1H_D_IMM_REAL 2638 +#define AArch64_GLDFF1H_D_REAL 2639 +#define AArch64_GLDFF1H_D_SCALED_REAL 2640 +#define AArch64_GLDFF1H_D_SXTW_REAL 2641 +#define AArch64_GLDFF1H_D_SXTW_SCALED_REAL 2642 +#define AArch64_GLDFF1H_D_UXTW_REAL 2643 +#define AArch64_GLDFF1H_D_UXTW_SCALED_REAL 2644 +#define AArch64_GLDFF1H_S_IMM_REAL 2645 +#define AArch64_GLDFF1H_S_SXTW_REAL 2646 +#define AArch64_GLDFF1H_S_SXTW_SCALED_REAL 2647 +#define AArch64_GLDFF1H_S_UXTW_REAL 2648 +#define AArch64_GLDFF1H_S_UXTW_SCALED_REAL 2649 +#define AArch64_GLDFF1SB_D_IMM_REAL 2650 +#define AArch64_GLDFF1SB_D_REAL 2651 +#define AArch64_GLDFF1SB_D_SXTW_REAL 2652 +#define AArch64_GLDFF1SB_D_UXTW_REAL 2653 +#define AArch64_GLDFF1SB_S_IMM_REAL 2654 +#define AArch64_GLDFF1SB_S_SXTW_REAL 2655 +#define AArch64_GLDFF1SB_S_UXTW_REAL 2656 +#define AArch64_GLDFF1SH_D_IMM_REAL 2657 +#define AArch64_GLDFF1SH_D_REAL 2658 +#define AArch64_GLDFF1SH_D_SCALED_REAL 2659 +#define AArch64_GLDFF1SH_D_SXTW_REAL 2660 +#define AArch64_GLDFF1SH_D_SXTW_SCALED_REAL 2661 +#define AArch64_GLDFF1SH_D_UXTW_REAL 2662 +#define AArch64_GLDFF1SH_D_UXTW_SCALED_REAL 2663 +#define AArch64_GLDFF1SH_S_IMM_REAL 2664 +#define AArch64_GLDFF1SH_S_SXTW_REAL 2665 +#define AArch64_GLDFF1SH_S_SXTW_SCALED_REAL 2666 +#define AArch64_GLDFF1SH_S_UXTW_REAL 2667 +#define AArch64_GLDFF1SH_S_UXTW_SCALED_REAL 2668 +#define AArch64_GLDFF1SW_D_IMM_REAL 2669 +#define AArch64_GLDFF1SW_D_REAL 2670 +#define AArch64_GLDFF1SW_D_SCALED_REAL 2671 +#define AArch64_GLDFF1SW_D_SXTW_REAL 2672 +#define AArch64_GLDFF1SW_D_SXTW_SCALED_REAL 2673 +#define AArch64_GLDFF1SW_D_UXTW_REAL 2674 +#define AArch64_GLDFF1SW_D_UXTW_SCALED_REAL 2675 +#define AArch64_GLDFF1W_D_IMM_REAL 2676 +#define AArch64_GLDFF1W_D_REAL 2677 +#define AArch64_GLDFF1W_D_SCALED_REAL 2678 +#define AArch64_GLDFF1W_D_SXTW_REAL 2679 +#define AArch64_GLDFF1W_D_SXTW_SCALED_REAL 2680 +#define AArch64_GLDFF1W_D_UXTW_REAL 2681 +#define AArch64_GLDFF1W_D_UXTW_SCALED_REAL 2682 +#define AArch64_GLDFF1W_IMM_REAL 2683 +#define AArch64_GLDFF1W_SXTW_REAL 2684 +#define AArch64_GLDFF1W_SXTW_SCALED_REAL 2685 +#define AArch64_GLDFF1W_UXTW_REAL 2686 +#define AArch64_GLDFF1W_UXTW_SCALED_REAL 2687 +#define AArch64_GMI 2688 +#define AArch64_HINT 2689 +#define AArch64_HISTCNT_ZPzZZ_D 2690 +#define AArch64_HISTCNT_ZPzZZ_S 2691 +#define AArch64_HISTSEG_ZZZ 2692 +#define AArch64_HLT 2693 +#define AArch64_HVC 2694 +#define AArch64_INCB_XPiI 2695 +#define AArch64_INCD_XPiI 2696 +#define AArch64_INCD_ZPiI 2697 +#define AArch64_INCH_XPiI 2698 +#define AArch64_INCH_ZPiI 2699 +#define AArch64_INCP_XP_B 2700 +#define AArch64_INCP_XP_D 2701 +#define AArch64_INCP_XP_H 2702 +#define AArch64_INCP_XP_S 2703 +#define AArch64_INCP_ZP_D 2704 +#define AArch64_INCP_ZP_H 2705 +#define AArch64_INCP_ZP_S 2706 +#define AArch64_INCW_XPiI 2707 +#define AArch64_INCW_ZPiI 2708 +#define AArch64_INDEX_II_B 2709 +#define AArch64_INDEX_II_D 2710 +#define AArch64_INDEX_II_H 2711 +#define AArch64_INDEX_II_S 2712 +#define AArch64_INDEX_IR_B 2713 +#define AArch64_INDEX_IR_D 2714 +#define AArch64_INDEX_IR_H 2715 +#define AArch64_INDEX_IR_S 2716 +#define AArch64_INDEX_RI_B 2717 +#define AArch64_INDEX_RI_D 2718 +#define AArch64_INDEX_RI_H 2719 +#define AArch64_INDEX_RI_S 2720 +#define AArch64_INDEX_RR_B 2721 +#define AArch64_INDEX_RR_D 2722 +#define AArch64_INDEX_RR_H 2723 +#define AArch64_INDEX_RR_S 2724 +#define AArch64_INSERT_MXIPZ_H_B 2725 +#define AArch64_INSERT_MXIPZ_H_D 2726 +#define AArch64_INSERT_MXIPZ_H_H 2727 +#define AArch64_INSERT_MXIPZ_H_Q 2728 +#define AArch64_INSERT_MXIPZ_H_S 2729 +#define AArch64_INSERT_MXIPZ_V_B 2730 +#define AArch64_INSERT_MXIPZ_V_D 2731 +#define AArch64_INSERT_MXIPZ_V_H 2732 +#define AArch64_INSERT_MXIPZ_V_Q 2733 +#define AArch64_INSERT_MXIPZ_V_S 2734 +#define AArch64_INSR_ZR_B 2735 +#define AArch64_INSR_ZR_D 2736 +#define AArch64_INSR_ZR_H 2737 +#define AArch64_INSR_ZR_S 2738 +#define AArch64_INSR_ZV_B 2739 +#define AArch64_INSR_ZV_D 2740 +#define AArch64_INSR_ZV_H 2741 +#define AArch64_INSR_ZV_S 2742 +#define AArch64_INSvi16gpr 2743 +#define AArch64_INSvi16lane 2744 +#define AArch64_INSvi32gpr 2745 +#define AArch64_INSvi32lane 2746 +#define AArch64_INSvi64gpr 2747 +#define AArch64_INSvi64lane 2748 +#define AArch64_INSvi8gpr 2749 +#define AArch64_INSvi8lane 2750 +#define AArch64_IRG 2751 +#define AArch64_ISB 2752 +#define AArch64_LASTA_RPZ_B 2753 +#define AArch64_LASTA_RPZ_D 2754 +#define AArch64_LASTA_RPZ_H 2755 +#define AArch64_LASTA_RPZ_S 2756 +#define AArch64_LASTA_VPZ_B 2757 +#define AArch64_LASTA_VPZ_D 2758 +#define AArch64_LASTA_VPZ_H 2759 +#define AArch64_LASTA_VPZ_S 2760 +#define AArch64_LASTB_RPZ_B 2761 +#define AArch64_LASTB_RPZ_D 2762 +#define AArch64_LASTB_RPZ_H 2763 +#define AArch64_LASTB_RPZ_S 2764 +#define AArch64_LASTB_VPZ_B 2765 +#define AArch64_LASTB_VPZ_D 2766 +#define AArch64_LASTB_VPZ_H 2767 +#define AArch64_LASTB_VPZ_S 2768 +#define AArch64_LD1B 2769 +#define AArch64_LD1B_D 2770 +#define AArch64_LD1B_D_IMM_REAL 2771 +#define AArch64_LD1B_H 2772 +#define AArch64_LD1B_H_IMM_REAL 2773 +#define AArch64_LD1B_IMM_REAL 2774 +#define AArch64_LD1B_S 2775 +#define AArch64_LD1B_S_IMM_REAL 2776 +#define AArch64_LD1D 2777 +#define AArch64_LD1D_IMM_REAL 2778 +#define AArch64_LD1Fourv16b 2779 +#define AArch64_LD1Fourv16b_POST 2780 +#define AArch64_LD1Fourv1d 2781 +#define AArch64_LD1Fourv1d_POST 2782 +#define AArch64_LD1Fourv2d 2783 +#define AArch64_LD1Fourv2d_POST 2784 +#define AArch64_LD1Fourv2s 2785 +#define AArch64_LD1Fourv2s_POST 2786 +#define AArch64_LD1Fourv4h 2787 +#define AArch64_LD1Fourv4h_POST 2788 +#define AArch64_LD1Fourv4s 2789 +#define AArch64_LD1Fourv4s_POST 2790 +#define AArch64_LD1Fourv8b 2791 +#define AArch64_LD1Fourv8b_POST 2792 +#define AArch64_LD1Fourv8h 2793 +#define AArch64_LD1Fourv8h_POST 2794 +#define AArch64_LD1H 2795 +#define AArch64_LD1H_D 2796 +#define AArch64_LD1H_D_IMM_REAL 2797 +#define AArch64_LD1H_IMM_REAL 2798 +#define AArch64_LD1H_S 2799 +#define AArch64_LD1H_S_IMM_REAL 2800 +#define AArch64_LD1Onev16b 2801 +#define AArch64_LD1Onev16b_POST 2802 +#define AArch64_LD1Onev1d 2803 +#define AArch64_LD1Onev1d_POST 2804 +#define AArch64_LD1Onev2d 2805 +#define AArch64_LD1Onev2d_POST 2806 +#define AArch64_LD1Onev2s 2807 +#define AArch64_LD1Onev2s_POST 2808 +#define AArch64_LD1Onev4h 2809 +#define AArch64_LD1Onev4h_POST 2810 +#define AArch64_LD1Onev4s 2811 +#define AArch64_LD1Onev4s_POST 2812 +#define AArch64_LD1Onev8b 2813 +#define AArch64_LD1Onev8b_POST 2814 +#define AArch64_LD1Onev8h 2815 +#define AArch64_LD1Onev8h_POST 2816 +#define AArch64_LD1RB_D_IMM 2817 +#define AArch64_LD1RB_H_IMM 2818 +#define AArch64_LD1RB_IMM 2819 +#define AArch64_LD1RB_S_IMM 2820 +#define AArch64_LD1RD_IMM 2821 +#define AArch64_LD1RH_D_IMM 2822 +#define AArch64_LD1RH_IMM 2823 +#define AArch64_LD1RH_S_IMM 2824 +#define AArch64_LD1RO_B 2825 +#define AArch64_LD1RO_B_IMM 2826 +#define AArch64_LD1RO_D 2827 +#define AArch64_LD1RO_D_IMM 2828 +#define AArch64_LD1RO_H 2829 +#define AArch64_LD1RO_H_IMM 2830 +#define AArch64_LD1RO_W 2831 +#define AArch64_LD1RO_W_IMM 2832 +#define AArch64_LD1RQ_B 2833 +#define AArch64_LD1RQ_B_IMM 2834 +#define AArch64_LD1RQ_D 2835 +#define AArch64_LD1RQ_D_IMM 2836 +#define AArch64_LD1RQ_H 2837 +#define AArch64_LD1RQ_H_IMM 2838 +#define AArch64_LD1RQ_W 2839 +#define AArch64_LD1RQ_W_IMM 2840 +#define AArch64_LD1RSB_D_IMM 2841 +#define AArch64_LD1RSB_H_IMM 2842 +#define AArch64_LD1RSB_S_IMM 2843 +#define AArch64_LD1RSH_D_IMM 2844 +#define AArch64_LD1RSH_S_IMM 2845 +#define AArch64_LD1RSW_IMM 2846 +#define AArch64_LD1RW_D_IMM 2847 +#define AArch64_LD1RW_IMM 2848 +#define AArch64_LD1Rv16b 2849 +#define AArch64_LD1Rv16b_POST 2850 +#define AArch64_LD1Rv1d 2851 +#define AArch64_LD1Rv1d_POST 2852 +#define AArch64_LD1Rv2d 2853 +#define AArch64_LD1Rv2d_POST 2854 +#define AArch64_LD1Rv2s 2855 +#define AArch64_LD1Rv2s_POST 2856 +#define AArch64_LD1Rv4h 2857 +#define AArch64_LD1Rv4h_POST 2858 +#define AArch64_LD1Rv4s 2859 +#define AArch64_LD1Rv4s_POST 2860 +#define AArch64_LD1Rv8b 2861 +#define AArch64_LD1Rv8b_POST 2862 +#define AArch64_LD1Rv8h 2863 +#define AArch64_LD1Rv8h_POST 2864 +#define AArch64_LD1SB_D 2865 +#define AArch64_LD1SB_D_IMM_REAL 2866 +#define AArch64_LD1SB_H 2867 +#define AArch64_LD1SB_H_IMM_REAL 2868 +#define AArch64_LD1SB_S 2869 +#define AArch64_LD1SB_S_IMM_REAL 2870 +#define AArch64_LD1SH_D 2871 +#define AArch64_LD1SH_D_IMM_REAL 2872 +#define AArch64_LD1SH_S 2873 +#define AArch64_LD1SH_S_IMM_REAL 2874 +#define AArch64_LD1SW_D 2875 +#define AArch64_LD1SW_D_IMM_REAL 2876 +#define AArch64_LD1Threev16b 2877 +#define AArch64_LD1Threev16b_POST 2878 +#define AArch64_LD1Threev1d 2879 +#define AArch64_LD1Threev1d_POST 2880 +#define AArch64_LD1Threev2d 2881 +#define AArch64_LD1Threev2d_POST 2882 +#define AArch64_LD1Threev2s 2883 +#define AArch64_LD1Threev2s_POST 2884 +#define AArch64_LD1Threev4h 2885 +#define AArch64_LD1Threev4h_POST 2886 +#define AArch64_LD1Threev4s 2887 +#define AArch64_LD1Threev4s_POST 2888 +#define AArch64_LD1Threev8b 2889 +#define AArch64_LD1Threev8b_POST 2890 +#define AArch64_LD1Threev8h 2891 +#define AArch64_LD1Threev8h_POST 2892 +#define AArch64_LD1Twov16b 2893 +#define AArch64_LD1Twov16b_POST 2894 +#define AArch64_LD1Twov1d 2895 +#define AArch64_LD1Twov1d_POST 2896 +#define AArch64_LD1Twov2d 2897 +#define AArch64_LD1Twov2d_POST 2898 +#define AArch64_LD1Twov2s 2899 +#define AArch64_LD1Twov2s_POST 2900 +#define AArch64_LD1Twov4h 2901 +#define AArch64_LD1Twov4h_POST 2902 +#define AArch64_LD1Twov4s 2903 +#define AArch64_LD1Twov4s_POST 2904 +#define AArch64_LD1Twov8b 2905 +#define AArch64_LD1Twov8b_POST 2906 +#define AArch64_LD1Twov8h 2907 +#define AArch64_LD1Twov8h_POST 2908 +#define AArch64_LD1W 2909 +#define AArch64_LD1W_D 2910 +#define AArch64_LD1W_D_IMM_REAL 2911 +#define AArch64_LD1W_IMM_REAL 2912 +#define AArch64_LD1_MXIPXX_H_B 2913 +#define AArch64_LD1_MXIPXX_H_D 2914 +#define AArch64_LD1_MXIPXX_H_H 2915 +#define AArch64_LD1_MXIPXX_H_Q 2916 +#define AArch64_LD1_MXIPXX_H_S 2917 +#define AArch64_LD1_MXIPXX_V_B 2918 +#define AArch64_LD1_MXIPXX_V_D 2919 +#define AArch64_LD1_MXIPXX_V_H 2920 +#define AArch64_LD1_MXIPXX_V_Q 2921 +#define AArch64_LD1_MXIPXX_V_S 2922 +#define AArch64_LD1i16 2923 +#define AArch64_LD1i16_POST 2924 +#define AArch64_LD1i32 2925 +#define AArch64_LD1i32_POST 2926 +#define AArch64_LD1i64 2927 +#define AArch64_LD1i64_POST 2928 +#define AArch64_LD1i8 2929 +#define AArch64_LD1i8_POST 2930 +#define AArch64_LD2B 2931 +#define AArch64_LD2B_IMM 2932 +#define AArch64_LD2D 2933 +#define AArch64_LD2D_IMM 2934 +#define AArch64_LD2H 2935 +#define AArch64_LD2H_IMM 2936 +#define AArch64_LD2Rv16b 2937 +#define AArch64_LD2Rv16b_POST 2938 +#define AArch64_LD2Rv1d 2939 +#define AArch64_LD2Rv1d_POST 2940 +#define AArch64_LD2Rv2d 2941 +#define AArch64_LD2Rv2d_POST 2942 +#define AArch64_LD2Rv2s 2943 +#define AArch64_LD2Rv2s_POST 2944 +#define AArch64_LD2Rv4h 2945 +#define AArch64_LD2Rv4h_POST 2946 +#define AArch64_LD2Rv4s 2947 +#define AArch64_LD2Rv4s_POST 2948 +#define AArch64_LD2Rv8b 2949 +#define AArch64_LD2Rv8b_POST 2950 +#define AArch64_LD2Rv8h 2951 +#define AArch64_LD2Rv8h_POST 2952 +#define AArch64_LD2Twov16b 2953 +#define AArch64_LD2Twov16b_POST 2954 +#define AArch64_LD2Twov2d 2955 +#define AArch64_LD2Twov2d_POST 2956 +#define AArch64_LD2Twov2s 2957 +#define AArch64_LD2Twov2s_POST 2958 +#define AArch64_LD2Twov4h 2959 +#define AArch64_LD2Twov4h_POST 2960 +#define AArch64_LD2Twov4s 2961 +#define AArch64_LD2Twov4s_POST 2962 +#define AArch64_LD2Twov8b 2963 +#define AArch64_LD2Twov8b_POST 2964 +#define AArch64_LD2Twov8h 2965 +#define AArch64_LD2Twov8h_POST 2966 +#define AArch64_LD2W 2967 +#define AArch64_LD2W_IMM 2968 +#define AArch64_LD2i16 2969 +#define AArch64_LD2i16_POST 2970 +#define AArch64_LD2i32 2971 +#define AArch64_LD2i32_POST 2972 +#define AArch64_LD2i64 2973 +#define AArch64_LD2i64_POST 2974 +#define AArch64_LD2i8 2975 +#define AArch64_LD2i8_POST 2976 +#define AArch64_LD3B 2977 +#define AArch64_LD3B_IMM 2978 +#define AArch64_LD3D 2979 +#define AArch64_LD3D_IMM 2980 +#define AArch64_LD3H 2981 +#define AArch64_LD3H_IMM 2982 +#define AArch64_LD3Rv16b 2983 +#define AArch64_LD3Rv16b_POST 2984 +#define AArch64_LD3Rv1d 2985 +#define AArch64_LD3Rv1d_POST 2986 +#define AArch64_LD3Rv2d 2987 +#define AArch64_LD3Rv2d_POST 2988 +#define AArch64_LD3Rv2s 2989 +#define AArch64_LD3Rv2s_POST 2990 +#define AArch64_LD3Rv4h 2991 +#define AArch64_LD3Rv4h_POST 2992 +#define AArch64_LD3Rv4s 2993 +#define AArch64_LD3Rv4s_POST 2994 +#define AArch64_LD3Rv8b 2995 +#define AArch64_LD3Rv8b_POST 2996 +#define AArch64_LD3Rv8h 2997 +#define AArch64_LD3Rv8h_POST 2998 +#define AArch64_LD3Threev16b 2999 +#define AArch64_LD3Threev16b_POST 3000 +#define AArch64_LD3Threev2d 3001 +#define AArch64_LD3Threev2d_POST 3002 +#define AArch64_LD3Threev2s 3003 +#define AArch64_LD3Threev2s_POST 3004 +#define AArch64_LD3Threev4h 3005 +#define AArch64_LD3Threev4h_POST 3006 +#define AArch64_LD3Threev4s 3007 +#define AArch64_LD3Threev4s_POST 3008 +#define AArch64_LD3Threev8b 3009 +#define AArch64_LD3Threev8b_POST 3010 +#define AArch64_LD3Threev8h 3011 +#define AArch64_LD3Threev8h_POST 3012 +#define AArch64_LD3W 3013 +#define AArch64_LD3W_IMM 3014 +#define AArch64_LD3i16 3015 +#define AArch64_LD3i16_POST 3016 +#define AArch64_LD3i32 3017 +#define AArch64_LD3i32_POST 3018 +#define AArch64_LD3i64 3019 +#define AArch64_LD3i64_POST 3020 +#define AArch64_LD3i8 3021 +#define AArch64_LD3i8_POST 3022 +#define AArch64_LD4B 3023 +#define AArch64_LD4B_IMM 3024 +#define AArch64_LD4D 3025 +#define AArch64_LD4D_IMM 3026 +#define AArch64_LD4Fourv16b 3027 +#define AArch64_LD4Fourv16b_POST 3028 +#define AArch64_LD4Fourv2d 3029 +#define AArch64_LD4Fourv2d_POST 3030 +#define AArch64_LD4Fourv2s 3031 +#define AArch64_LD4Fourv2s_POST 3032 +#define AArch64_LD4Fourv4h 3033 +#define AArch64_LD4Fourv4h_POST 3034 +#define AArch64_LD4Fourv4s 3035 +#define AArch64_LD4Fourv4s_POST 3036 +#define AArch64_LD4Fourv8b 3037 +#define AArch64_LD4Fourv8b_POST 3038 +#define AArch64_LD4Fourv8h 3039 +#define AArch64_LD4Fourv8h_POST 3040 +#define AArch64_LD4H 3041 +#define AArch64_LD4H_IMM 3042 +#define AArch64_LD4Rv16b 3043 +#define AArch64_LD4Rv16b_POST 3044 +#define AArch64_LD4Rv1d 3045 +#define AArch64_LD4Rv1d_POST 3046 +#define AArch64_LD4Rv2d 3047 +#define AArch64_LD4Rv2d_POST 3048 +#define AArch64_LD4Rv2s 3049 +#define AArch64_LD4Rv2s_POST 3050 +#define AArch64_LD4Rv4h 3051 +#define AArch64_LD4Rv4h_POST 3052 +#define AArch64_LD4Rv4s 3053 +#define AArch64_LD4Rv4s_POST 3054 +#define AArch64_LD4Rv8b 3055 +#define AArch64_LD4Rv8b_POST 3056 +#define AArch64_LD4Rv8h 3057 +#define AArch64_LD4Rv8h_POST 3058 +#define AArch64_LD4W 3059 +#define AArch64_LD4W_IMM 3060 +#define AArch64_LD4i16 3061 +#define AArch64_LD4i16_POST 3062 +#define AArch64_LD4i32 3063 +#define AArch64_LD4i32_POST 3064 +#define AArch64_LD4i64 3065 +#define AArch64_LD4i64_POST 3066 +#define AArch64_LD4i8 3067 +#define AArch64_LD4i8_POST 3068 +#define AArch64_LD64B 3069 +#define AArch64_LDADDAB 3070 +#define AArch64_LDADDAH 3071 +#define AArch64_LDADDALB 3072 +#define AArch64_LDADDALH 3073 +#define AArch64_LDADDALW 3074 +#define AArch64_LDADDALX 3075 +#define AArch64_LDADDAW 3076 +#define AArch64_LDADDAX 3077 +#define AArch64_LDADDB 3078 +#define AArch64_LDADDH 3079 +#define AArch64_LDADDLB 3080 +#define AArch64_LDADDLH 3081 +#define AArch64_LDADDLW 3082 +#define AArch64_LDADDLX 3083 +#define AArch64_LDADDW 3084 +#define AArch64_LDADDX 3085 +#define AArch64_LDAPRB 3086 +#define AArch64_LDAPRH 3087 +#define AArch64_LDAPRW 3088 +#define AArch64_LDAPRX 3089 +#define AArch64_LDAPURBi 3090 +#define AArch64_LDAPURHi 3091 +#define AArch64_LDAPURSBWi 3092 +#define AArch64_LDAPURSBXi 3093 +#define AArch64_LDAPURSHWi 3094 +#define AArch64_LDAPURSHXi 3095 +#define AArch64_LDAPURSWi 3096 +#define AArch64_LDAPURXi 3097 +#define AArch64_LDAPURi 3098 +#define AArch64_LDARB 3099 +#define AArch64_LDARH 3100 +#define AArch64_LDARW 3101 +#define AArch64_LDARX 3102 +#define AArch64_LDAXPW 3103 +#define AArch64_LDAXPX 3104 +#define AArch64_LDAXRB 3105 +#define AArch64_LDAXRH 3106 +#define AArch64_LDAXRW 3107 +#define AArch64_LDAXRX 3108 +#define AArch64_LDCLRAB 3109 +#define AArch64_LDCLRAH 3110 +#define AArch64_LDCLRALB 3111 +#define AArch64_LDCLRALH 3112 +#define AArch64_LDCLRALW 3113 +#define AArch64_LDCLRALX 3114 +#define AArch64_LDCLRAW 3115 +#define AArch64_LDCLRAX 3116 +#define AArch64_LDCLRB 3117 +#define AArch64_LDCLRH 3118 +#define AArch64_LDCLRLB 3119 +#define AArch64_LDCLRLH 3120 +#define AArch64_LDCLRLW 3121 +#define AArch64_LDCLRLX 3122 +#define AArch64_LDCLRW 3123 +#define AArch64_LDCLRX 3124 +#define AArch64_LDEORAB 3125 +#define AArch64_LDEORAH 3126 +#define AArch64_LDEORALB 3127 +#define AArch64_LDEORALH 3128 +#define AArch64_LDEORALW 3129 +#define AArch64_LDEORALX 3130 +#define AArch64_LDEORAW 3131 +#define AArch64_LDEORAX 3132 +#define AArch64_LDEORB 3133 +#define AArch64_LDEORH 3134 +#define AArch64_LDEORLB 3135 +#define AArch64_LDEORLH 3136 +#define AArch64_LDEORLW 3137 +#define AArch64_LDEORLX 3138 +#define AArch64_LDEORW 3139 +#define AArch64_LDEORX 3140 +#define AArch64_LDFF1B_D_REAL 3141 +#define AArch64_LDFF1B_H_REAL 3142 +#define AArch64_LDFF1B_REAL 3143 +#define AArch64_LDFF1B_S_REAL 3144 +#define AArch64_LDFF1D_REAL 3145 +#define AArch64_LDFF1H_D_REAL 3146 +#define AArch64_LDFF1H_REAL 3147 +#define AArch64_LDFF1H_S_REAL 3148 +#define AArch64_LDFF1SB_D_REAL 3149 +#define AArch64_LDFF1SB_H_REAL 3150 +#define AArch64_LDFF1SB_S_REAL 3151 +#define AArch64_LDFF1SH_D_REAL 3152 +#define AArch64_LDFF1SH_S_REAL 3153 +#define AArch64_LDFF1SW_D_REAL 3154 +#define AArch64_LDFF1W_D_REAL 3155 +#define AArch64_LDFF1W_REAL 3156 +#define AArch64_LDG 3157 +#define AArch64_LDGM 3158 +#define AArch64_LDLARB 3159 +#define AArch64_LDLARH 3160 +#define AArch64_LDLARW 3161 +#define AArch64_LDLARX 3162 +#define AArch64_LDNF1B_D_IMM_REAL 3163 +#define AArch64_LDNF1B_H_IMM_REAL 3164 +#define AArch64_LDNF1B_IMM_REAL 3165 +#define AArch64_LDNF1B_S_IMM_REAL 3166 +#define AArch64_LDNF1D_IMM_REAL 3167 +#define AArch64_LDNF1H_D_IMM_REAL 3168 +#define AArch64_LDNF1H_IMM_REAL 3169 +#define AArch64_LDNF1H_S_IMM_REAL 3170 +#define AArch64_LDNF1SB_D_IMM_REAL 3171 +#define AArch64_LDNF1SB_H_IMM_REAL 3172 +#define AArch64_LDNF1SB_S_IMM_REAL 3173 +#define AArch64_LDNF1SH_D_IMM_REAL 3174 +#define AArch64_LDNF1SH_S_IMM_REAL 3175 +#define AArch64_LDNF1SW_D_IMM_REAL 3176 +#define AArch64_LDNF1W_D_IMM_REAL 3177 +#define AArch64_LDNF1W_IMM_REAL 3178 +#define AArch64_LDNPDi 3179 +#define AArch64_LDNPQi 3180 +#define AArch64_LDNPSi 3181 +#define AArch64_LDNPWi 3182 +#define AArch64_LDNPXi 3183 +#define AArch64_LDNT1B_ZRI 3184 +#define AArch64_LDNT1B_ZRR 3185 +#define AArch64_LDNT1B_ZZR_D_REAL 3186 +#define AArch64_LDNT1B_ZZR_S_REAL 3187 +#define AArch64_LDNT1D_ZRI 3188 +#define AArch64_LDNT1D_ZRR 3189 +#define AArch64_LDNT1D_ZZR_D_REAL 3190 +#define AArch64_LDNT1H_ZRI 3191 +#define AArch64_LDNT1H_ZRR 3192 +#define AArch64_LDNT1H_ZZR_D_REAL 3193 +#define AArch64_LDNT1H_ZZR_S_REAL 3194 +#define AArch64_LDNT1SB_ZZR_D_REAL 3195 +#define AArch64_LDNT1SB_ZZR_S_REAL 3196 +#define AArch64_LDNT1SH_ZZR_D_REAL 3197 +#define AArch64_LDNT1SH_ZZR_S_REAL 3198 +#define AArch64_LDNT1SW_ZZR_D_REAL 3199 +#define AArch64_LDNT1W_ZRI 3200 +#define AArch64_LDNT1W_ZRR 3201 +#define AArch64_LDNT1W_ZZR_D_REAL 3202 +#define AArch64_LDNT1W_ZZR_S_REAL 3203 +#define AArch64_LDPDi 3204 +#define AArch64_LDPDpost 3205 +#define AArch64_LDPDpre 3206 +#define AArch64_LDPQi 3207 +#define AArch64_LDPQpost 3208 +#define AArch64_LDPQpre 3209 +#define AArch64_LDPSWi 3210 +#define AArch64_LDPSWpost 3211 +#define AArch64_LDPSWpre 3212 +#define AArch64_LDPSi 3213 +#define AArch64_LDPSpost 3214 +#define AArch64_LDPSpre 3215 +#define AArch64_LDPWi 3216 +#define AArch64_LDPWpost 3217 +#define AArch64_LDPWpre 3218 +#define AArch64_LDPXi 3219 +#define AArch64_LDPXpost 3220 +#define AArch64_LDPXpre 3221 +#define AArch64_LDRAAindexed 3222 +#define AArch64_LDRAAwriteback 3223 +#define AArch64_LDRABindexed 3224 +#define AArch64_LDRABwriteback 3225 +#define AArch64_LDRBBpost 3226 +#define AArch64_LDRBBpre 3227 +#define AArch64_LDRBBroW 3228 +#define AArch64_LDRBBroX 3229 +#define AArch64_LDRBBui 3230 +#define AArch64_LDRBpost 3231 +#define AArch64_LDRBpre 3232 +#define AArch64_LDRBroW 3233 +#define AArch64_LDRBroX 3234 +#define AArch64_LDRBui 3235 +#define AArch64_LDRDl 3236 +#define AArch64_LDRDpost 3237 +#define AArch64_LDRDpre 3238 +#define AArch64_LDRDroW 3239 +#define AArch64_LDRDroX 3240 +#define AArch64_LDRDui 3241 +#define AArch64_LDRHHpost 3242 +#define AArch64_LDRHHpre 3243 +#define AArch64_LDRHHroW 3244 +#define AArch64_LDRHHroX 3245 +#define AArch64_LDRHHui 3246 +#define AArch64_LDRHpost 3247 +#define AArch64_LDRHpre 3248 +#define AArch64_LDRHroW 3249 +#define AArch64_LDRHroX 3250 +#define AArch64_LDRHui 3251 +#define AArch64_LDRQl 3252 +#define AArch64_LDRQpost 3253 +#define AArch64_LDRQpre 3254 +#define AArch64_LDRQroW 3255 +#define AArch64_LDRQroX 3256 +#define AArch64_LDRQui 3257 +#define AArch64_LDRSBWpost 3258 +#define AArch64_LDRSBWpre 3259 +#define AArch64_LDRSBWroW 3260 +#define AArch64_LDRSBWroX 3261 +#define AArch64_LDRSBWui 3262 +#define AArch64_LDRSBXpost 3263 +#define AArch64_LDRSBXpre 3264 +#define AArch64_LDRSBXroW 3265 +#define AArch64_LDRSBXroX 3266 +#define AArch64_LDRSBXui 3267 +#define AArch64_LDRSHWpost 3268 +#define AArch64_LDRSHWpre 3269 +#define AArch64_LDRSHWroW 3270 +#define AArch64_LDRSHWroX 3271 +#define AArch64_LDRSHWui 3272 +#define AArch64_LDRSHXpost 3273 +#define AArch64_LDRSHXpre 3274 +#define AArch64_LDRSHXroW 3275 +#define AArch64_LDRSHXroX 3276 +#define AArch64_LDRSHXui 3277 +#define AArch64_LDRSWl 3278 +#define AArch64_LDRSWpost 3279 +#define AArch64_LDRSWpre 3280 +#define AArch64_LDRSWroW 3281 +#define AArch64_LDRSWroX 3282 +#define AArch64_LDRSWui 3283 +#define AArch64_LDRSl 3284 +#define AArch64_LDRSpost 3285 +#define AArch64_LDRSpre 3286 +#define AArch64_LDRSroW 3287 +#define AArch64_LDRSroX 3288 +#define AArch64_LDRSui 3289 +#define AArch64_LDRWl 3290 +#define AArch64_LDRWpost 3291 +#define AArch64_LDRWpre 3292 +#define AArch64_LDRWroW 3293 +#define AArch64_LDRWroX 3294 +#define AArch64_LDRWui 3295 +#define AArch64_LDRXl 3296 +#define AArch64_LDRXpost 3297 +#define AArch64_LDRXpre 3298 +#define AArch64_LDRXroW 3299 +#define AArch64_LDRXroX 3300 +#define AArch64_LDRXui 3301 +#define AArch64_LDR_PXI 3302 +#define AArch64_LDR_ZA 3303 +#define AArch64_LDR_ZXI 3304 +#define AArch64_LDSETAB 3305 +#define AArch64_LDSETAH 3306 +#define AArch64_LDSETALB 3307 +#define AArch64_LDSETALH 3308 +#define AArch64_LDSETALW 3309 +#define AArch64_LDSETALX 3310 +#define AArch64_LDSETAW 3311 +#define AArch64_LDSETAX 3312 +#define AArch64_LDSETB 3313 +#define AArch64_LDSETH 3314 +#define AArch64_LDSETLB 3315 +#define AArch64_LDSETLH 3316 +#define AArch64_LDSETLW 3317 +#define AArch64_LDSETLX 3318 +#define AArch64_LDSETW 3319 +#define AArch64_LDSETX 3320 +#define AArch64_LDSMAXAB 3321 +#define AArch64_LDSMAXAH 3322 +#define AArch64_LDSMAXALB 3323 +#define AArch64_LDSMAXALH 3324 +#define AArch64_LDSMAXALW 3325 +#define AArch64_LDSMAXALX 3326 +#define AArch64_LDSMAXAW 3327 +#define AArch64_LDSMAXAX 3328 +#define AArch64_LDSMAXB 3329 +#define AArch64_LDSMAXH 3330 +#define AArch64_LDSMAXLB 3331 +#define AArch64_LDSMAXLH 3332 +#define AArch64_LDSMAXLW 3333 +#define AArch64_LDSMAXLX 3334 +#define AArch64_LDSMAXW 3335 +#define AArch64_LDSMAXX 3336 +#define AArch64_LDSMINAB 3337 +#define AArch64_LDSMINAH 3338 +#define AArch64_LDSMINALB 3339 +#define AArch64_LDSMINALH 3340 +#define AArch64_LDSMINALW 3341 +#define AArch64_LDSMINALX 3342 +#define AArch64_LDSMINAW 3343 +#define AArch64_LDSMINAX 3344 +#define AArch64_LDSMINB 3345 +#define AArch64_LDSMINH 3346 +#define AArch64_LDSMINLB 3347 +#define AArch64_LDSMINLH 3348 +#define AArch64_LDSMINLW 3349 +#define AArch64_LDSMINLX 3350 +#define AArch64_LDSMINW 3351 +#define AArch64_LDSMINX 3352 +#define AArch64_LDTRBi 3353 +#define AArch64_LDTRHi 3354 +#define AArch64_LDTRSBWi 3355 +#define AArch64_LDTRSBXi 3356 +#define AArch64_LDTRSHWi 3357 +#define AArch64_LDTRSHXi 3358 +#define AArch64_LDTRSWi 3359 +#define AArch64_LDTRWi 3360 +#define AArch64_LDTRXi 3361 +#define AArch64_LDUMAXAB 3362 +#define AArch64_LDUMAXAH 3363 +#define AArch64_LDUMAXALB 3364 +#define AArch64_LDUMAXALH 3365 +#define AArch64_LDUMAXALW 3366 +#define AArch64_LDUMAXALX 3367 +#define AArch64_LDUMAXAW 3368 +#define AArch64_LDUMAXAX 3369 +#define AArch64_LDUMAXB 3370 +#define AArch64_LDUMAXH 3371 +#define AArch64_LDUMAXLB 3372 +#define AArch64_LDUMAXLH 3373 +#define AArch64_LDUMAXLW 3374 +#define AArch64_LDUMAXLX 3375 +#define AArch64_LDUMAXW 3376 +#define AArch64_LDUMAXX 3377 +#define AArch64_LDUMINAB 3378 +#define AArch64_LDUMINAH 3379 +#define AArch64_LDUMINALB 3380 +#define AArch64_LDUMINALH 3381 +#define AArch64_LDUMINALW 3382 +#define AArch64_LDUMINALX 3383 +#define AArch64_LDUMINAW 3384 +#define AArch64_LDUMINAX 3385 +#define AArch64_LDUMINB 3386 +#define AArch64_LDUMINH 3387 +#define AArch64_LDUMINLB 3388 +#define AArch64_LDUMINLH 3389 +#define AArch64_LDUMINLW 3390 +#define AArch64_LDUMINLX 3391 +#define AArch64_LDUMINW 3392 +#define AArch64_LDUMINX 3393 +#define AArch64_LDURBBi 3394 +#define AArch64_LDURBi 3395 +#define AArch64_LDURDi 3396 +#define AArch64_LDURHHi 3397 +#define AArch64_LDURHi 3398 +#define AArch64_LDURQi 3399 +#define AArch64_LDURSBWi 3400 +#define AArch64_LDURSBXi 3401 +#define AArch64_LDURSHWi 3402 +#define AArch64_LDURSHXi 3403 +#define AArch64_LDURSWi 3404 +#define AArch64_LDURSi 3405 +#define AArch64_LDURWi 3406 +#define AArch64_LDURXi 3407 +#define AArch64_LDXPW 3408 +#define AArch64_LDXPX 3409 +#define AArch64_LDXRB 3410 +#define AArch64_LDXRH 3411 +#define AArch64_LDXRW 3412 +#define AArch64_LDXRX 3413 +#define AArch64_LSLR_ZPmZ_B 3414 +#define AArch64_LSLR_ZPmZ_D 3415 +#define AArch64_LSLR_ZPmZ_H 3416 +#define AArch64_LSLR_ZPmZ_S 3417 +#define AArch64_LSLVWr 3418 +#define AArch64_LSLVXr 3419 +#define AArch64_LSL_WIDE_ZPmZ_B 3420 +#define AArch64_LSL_WIDE_ZPmZ_H 3421 +#define AArch64_LSL_WIDE_ZPmZ_S 3422 +#define AArch64_LSL_WIDE_ZZZ_B 3423 +#define AArch64_LSL_WIDE_ZZZ_H 3424 +#define AArch64_LSL_WIDE_ZZZ_S 3425 +#define AArch64_LSL_ZPmI_B 3426 +#define AArch64_LSL_ZPmI_D 3427 +#define AArch64_LSL_ZPmI_H 3428 +#define AArch64_LSL_ZPmI_S 3429 +#define AArch64_LSL_ZPmZ_B 3430 +#define AArch64_LSL_ZPmZ_D 3431 +#define AArch64_LSL_ZPmZ_H 3432 +#define AArch64_LSL_ZPmZ_S 3433 +#define AArch64_LSL_ZZI_B 3434 +#define AArch64_LSL_ZZI_D 3435 +#define AArch64_LSL_ZZI_H 3436 +#define AArch64_LSL_ZZI_S 3437 +#define AArch64_LSRR_ZPmZ_B 3438 +#define AArch64_LSRR_ZPmZ_D 3439 +#define AArch64_LSRR_ZPmZ_H 3440 +#define AArch64_LSRR_ZPmZ_S 3441 +#define AArch64_LSRVWr 3442 +#define AArch64_LSRVXr 3443 +#define AArch64_LSR_WIDE_ZPmZ_B 3444 +#define AArch64_LSR_WIDE_ZPmZ_H 3445 +#define AArch64_LSR_WIDE_ZPmZ_S 3446 +#define AArch64_LSR_WIDE_ZZZ_B 3447 +#define AArch64_LSR_WIDE_ZZZ_H 3448 +#define AArch64_LSR_WIDE_ZZZ_S 3449 +#define AArch64_LSR_ZPmI_B 3450 +#define AArch64_LSR_ZPmI_D 3451 +#define AArch64_LSR_ZPmI_H 3452 +#define AArch64_LSR_ZPmI_S 3453 +#define AArch64_LSR_ZPmZ_B 3454 +#define AArch64_LSR_ZPmZ_D 3455 +#define AArch64_LSR_ZPmZ_H 3456 +#define AArch64_LSR_ZPmZ_S 3457 +#define AArch64_LSR_ZZI_B 3458 +#define AArch64_LSR_ZZI_D 3459 +#define AArch64_LSR_ZZI_H 3460 +#define AArch64_LSR_ZZI_S 3461 +#define AArch64_MADDWrrr 3462 +#define AArch64_MADDXrrr 3463 +#define AArch64_MAD_ZPmZZ_B 3464 +#define AArch64_MAD_ZPmZZ_D 3465 +#define AArch64_MAD_ZPmZZ_H 3466 +#define AArch64_MAD_ZPmZZ_S 3467 +#define AArch64_MATCH_PPzZZ_B 3468 +#define AArch64_MATCH_PPzZZ_H 3469 +#define AArch64_MLA_ZPmZZ_B 3470 +#define AArch64_MLA_ZPmZZ_D 3471 +#define AArch64_MLA_ZPmZZ_H 3472 +#define AArch64_MLA_ZPmZZ_S 3473 +#define AArch64_MLA_ZZZI_D 3474 +#define AArch64_MLA_ZZZI_H 3475 +#define AArch64_MLA_ZZZI_S 3476 +#define AArch64_MLAv16i8 3477 +#define AArch64_MLAv2i32 3478 +#define AArch64_MLAv2i32_indexed 3479 +#define AArch64_MLAv4i16 3480 +#define AArch64_MLAv4i16_indexed 3481 +#define AArch64_MLAv4i32 3482 +#define AArch64_MLAv4i32_indexed 3483 +#define AArch64_MLAv8i16 3484 +#define AArch64_MLAv8i16_indexed 3485 +#define AArch64_MLAv8i8 3486 +#define AArch64_MLS_ZPmZZ_B 3487 +#define AArch64_MLS_ZPmZZ_D 3488 +#define AArch64_MLS_ZPmZZ_H 3489 +#define AArch64_MLS_ZPmZZ_S 3490 +#define AArch64_MLS_ZZZI_D 3491 +#define AArch64_MLS_ZZZI_H 3492 +#define AArch64_MLS_ZZZI_S 3493 +#define AArch64_MLSv16i8 3494 +#define AArch64_MLSv2i32 3495 +#define AArch64_MLSv2i32_indexed 3496 +#define AArch64_MLSv4i16 3497 +#define AArch64_MLSv4i16_indexed 3498 +#define AArch64_MLSv4i32 3499 +#define AArch64_MLSv4i32_indexed 3500 +#define AArch64_MLSv8i16 3501 +#define AArch64_MLSv8i16_indexed 3502 +#define AArch64_MLSv8i8 3503 +#define AArch64_MOVID 3504 +#define AArch64_MOVIv16b_ns 3505 +#define AArch64_MOVIv2d_ns 3506 +#define AArch64_MOVIv2i32 3507 +#define AArch64_MOVIv2s_msl 3508 +#define AArch64_MOVIv4i16 3509 +#define AArch64_MOVIv4i32 3510 +#define AArch64_MOVIv4s_msl 3511 +#define AArch64_MOVIv8b_ns 3512 +#define AArch64_MOVIv8i16 3513 +#define AArch64_MOVKWi 3514 +#define AArch64_MOVKXi 3515 +#define AArch64_MOVNWi 3516 +#define AArch64_MOVNXi 3517 +#define AArch64_MOVPRFX_ZPmZ_B 3518 +#define AArch64_MOVPRFX_ZPmZ_D 3519 +#define AArch64_MOVPRFX_ZPmZ_H 3520 +#define AArch64_MOVPRFX_ZPmZ_S 3521 +#define AArch64_MOVPRFX_ZPzZ_B 3522 +#define AArch64_MOVPRFX_ZPzZ_D 3523 +#define AArch64_MOVPRFX_ZPzZ_H 3524 +#define AArch64_MOVPRFX_ZPzZ_S 3525 +#define AArch64_MOVPRFX_ZZ 3526 +#define AArch64_MOVZWi 3527 +#define AArch64_MOVZXi 3528 +#define AArch64_MRS 3529 +#define AArch64_MSB_ZPmZZ_B 3530 +#define AArch64_MSB_ZPmZZ_D 3531 +#define AArch64_MSB_ZPmZZ_H 3532 +#define AArch64_MSB_ZPmZZ_S 3533 +#define AArch64_MSR 3534 +#define AArch64_MSRpstateImm1 3535 +#define AArch64_MSRpstateImm4 3536 +#define AArch64_MSRpstatesvcrImm1 3537 +#define AArch64_MSUBWrrr 3538 +#define AArch64_MSUBXrrr 3539 +#define AArch64_MUL_ZI_B 3540 +#define AArch64_MUL_ZI_D 3541 +#define AArch64_MUL_ZI_H 3542 +#define AArch64_MUL_ZI_S 3543 +#define AArch64_MUL_ZPmZ_B 3544 +#define AArch64_MUL_ZPmZ_D 3545 +#define AArch64_MUL_ZPmZ_H 3546 +#define AArch64_MUL_ZPmZ_S 3547 +#define AArch64_MUL_ZZZI_D 3548 +#define AArch64_MUL_ZZZI_H 3549 +#define AArch64_MUL_ZZZI_S 3550 +#define AArch64_MUL_ZZZ_B 3551 +#define AArch64_MUL_ZZZ_D 3552 +#define AArch64_MUL_ZZZ_H 3553 +#define AArch64_MUL_ZZZ_S 3554 +#define AArch64_MULv16i8 3555 +#define AArch64_MULv2i32 3556 +#define AArch64_MULv2i32_indexed 3557 +#define AArch64_MULv4i16 3558 +#define AArch64_MULv4i16_indexed 3559 +#define AArch64_MULv4i32 3560 +#define AArch64_MULv4i32_indexed 3561 +#define AArch64_MULv8i16 3562 +#define AArch64_MULv8i16_indexed 3563 +#define AArch64_MULv8i8 3564 +#define AArch64_MVNIv2i32 3565 +#define AArch64_MVNIv2s_msl 3566 +#define AArch64_MVNIv4i16 3567 +#define AArch64_MVNIv4i32 3568 +#define AArch64_MVNIv4s_msl 3569 +#define AArch64_MVNIv8i16 3570 +#define AArch64_NANDS_PPzPP 3571 +#define AArch64_NAND_PPzPP 3572 +#define AArch64_NBSL_ZZZZ 3573 +#define AArch64_NEG_ZPmZ_B 3574 +#define AArch64_NEG_ZPmZ_D 3575 +#define AArch64_NEG_ZPmZ_H 3576 +#define AArch64_NEG_ZPmZ_S 3577 +#define AArch64_NEGv16i8 3578 +#define AArch64_NEGv1i64 3579 +#define AArch64_NEGv2i32 3580 +#define AArch64_NEGv2i64 3581 +#define AArch64_NEGv4i16 3582 +#define AArch64_NEGv4i32 3583 +#define AArch64_NEGv8i16 3584 +#define AArch64_NEGv8i8 3585 +#define AArch64_NMATCH_PPzZZ_B 3586 +#define AArch64_NMATCH_PPzZZ_H 3587 +#define AArch64_NORS_PPzPP 3588 +#define AArch64_NOR_PPzPP 3589 +#define AArch64_NOT_ZPmZ_B 3590 +#define AArch64_NOT_ZPmZ_D 3591 +#define AArch64_NOT_ZPmZ_H 3592 +#define AArch64_NOT_ZPmZ_S 3593 +#define AArch64_NOTv16i8 3594 +#define AArch64_NOTv8i8 3595 +#define AArch64_ORNS_PPzPP 3596 +#define AArch64_ORNWrs 3597 +#define AArch64_ORNXrs 3598 +#define AArch64_ORN_PPzPP 3599 +#define AArch64_ORNv16i8 3600 +#define AArch64_ORNv8i8 3601 +#define AArch64_ORRS_PPzPP 3602 +#define AArch64_ORRWri 3603 +#define AArch64_ORRWrs 3604 +#define AArch64_ORRXri 3605 +#define AArch64_ORRXrs 3606 +#define AArch64_ORR_PPzPP 3607 +#define AArch64_ORR_ZI 3608 +#define AArch64_ORR_ZPmZ_B 3609 +#define AArch64_ORR_ZPmZ_D 3610 +#define AArch64_ORR_ZPmZ_H 3611 +#define AArch64_ORR_ZPmZ_S 3612 +#define AArch64_ORR_ZZZ 3613 +#define AArch64_ORRv16i8 3614 +#define AArch64_ORRv2i32 3615 +#define AArch64_ORRv4i16 3616 +#define AArch64_ORRv4i32 3617 +#define AArch64_ORRv8i16 3618 +#define AArch64_ORRv8i8 3619 +#define AArch64_ORV_VPZ_B 3620 +#define AArch64_ORV_VPZ_D 3621 +#define AArch64_ORV_VPZ_H 3622 +#define AArch64_ORV_VPZ_S 3623 +#define AArch64_PACDA 3624 +#define AArch64_PACDB 3625 +#define AArch64_PACDZA 3626 +#define AArch64_PACDZB 3627 +#define AArch64_PACGA 3628 +#define AArch64_PACIA 3629 +#define AArch64_PACIA1716 3630 +#define AArch64_PACIASP 3631 +#define AArch64_PACIAZ 3632 +#define AArch64_PACIB 3633 +#define AArch64_PACIB1716 3634 +#define AArch64_PACIBSP 3635 +#define AArch64_PACIBZ 3636 +#define AArch64_PACIZA 3637 +#define AArch64_PACIZB 3638 +#define AArch64_PFALSE 3639 +#define AArch64_PFIRST_B 3640 +#define AArch64_PMULLB_ZZZ_D 3641 +#define AArch64_PMULLB_ZZZ_H 3642 +#define AArch64_PMULLB_ZZZ_Q 3643 +#define AArch64_PMULLT_ZZZ_D 3644 +#define AArch64_PMULLT_ZZZ_H 3645 +#define AArch64_PMULLT_ZZZ_Q 3646 +#define AArch64_PMULLv16i8 3647 +#define AArch64_PMULLv1i64 3648 +#define AArch64_PMULLv2i64 3649 +#define AArch64_PMULLv8i8 3650 +#define AArch64_PMUL_ZZZ_B 3651 +#define AArch64_PMULv16i8 3652 +#define AArch64_PMULv8i8 3653 +#define AArch64_PNEXT_B 3654 +#define AArch64_PNEXT_D 3655 +#define AArch64_PNEXT_H 3656 +#define AArch64_PNEXT_S 3657 +#define AArch64_PRFB_D_PZI 3658 +#define AArch64_PRFB_D_SCALED 3659 +#define AArch64_PRFB_D_SXTW_SCALED 3660 +#define AArch64_PRFB_D_UXTW_SCALED 3661 +#define AArch64_PRFB_PRI 3662 +#define AArch64_PRFB_PRR 3663 +#define AArch64_PRFB_S_PZI 3664 +#define AArch64_PRFB_S_SXTW_SCALED 3665 +#define AArch64_PRFB_S_UXTW_SCALED 3666 +#define AArch64_PRFD_D_PZI 3667 +#define AArch64_PRFD_D_SCALED 3668 +#define AArch64_PRFD_D_SXTW_SCALED 3669 +#define AArch64_PRFD_D_UXTW_SCALED 3670 +#define AArch64_PRFD_PRI 3671 +#define AArch64_PRFD_PRR 3672 +#define AArch64_PRFD_S_PZI 3673 +#define AArch64_PRFD_S_SXTW_SCALED 3674 +#define AArch64_PRFD_S_UXTW_SCALED 3675 +#define AArch64_PRFH_D_PZI 3676 +#define AArch64_PRFH_D_SCALED 3677 +#define AArch64_PRFH_D_SXTW_SCALED 3678 +#define AArch64_PRFH_D_UXTW_SCALED 3679 +#define AArch64_PRFH_PRI 3680 +#define AArch64_PRFH_PRR 3681 +#define AArch64_PRFH_S_PZI 3682 +#define AArch64_PRFH_S_SXTW_SCALED 3683 +#define AArch64_PRFH_S_UXTW_SCALED 3684 +#define AArch64_PRFMl 3685 +#define AArch64_PRFMroW 3686 +#define AArch64_PRFMroX 3687 +#define AArch64_PRFMui 3688 +#define AArch64_PRFS_PRR 3689 +#define AArch64_PRFUMi 3690 +#define AArch64_PRFW_D_PZI 3691 +#define AArch64_PRFW_D_SCALED 3692 +#define AArch64_PRFW_D_SXTW_SCALED 3693 +#define AArch64_PRFW_D_UXTW_SCALED 3694 +#define AArch64_PRFW_PRI 3695 +#define AArch64_PRFW_S_PZI 3696 +#define AArch64_PRFW_S_SXTW_SCALED 3697 +#define AArch64_PRFW_S_UXTW_SCALED 3698 +#define AArch64_PSEL_PPPRI_B 3699 +#define AArch64_PSEL_PPPRI_D 3700 +#define AArch64_PSEL_PPPRI_H 3701 +#define AArch64_PSEL_PPPRI_S 3702 +#define AArch64_PTEST_PP 3703 +#define AArch64_PTRUES_B 3704 +#define AArch64_PTRUES_D 3705 +#define AArch64_PTRUES_H 3706 +#define AArch64_PTRUES_S 3707 +#define AArch64_PTRUE_B 3708 +#define AArch64_PTRUE_D 3709 +#define AArch64_PTRUE_H 3710 +#define AArch64_PTRUE_S 3711 +#define AArch64_PUNPKHI_PP 3712 +#define AArch64_PUNPKLO_PP 3713 +#define AArch64_RADDHNB_ZZZ_B 3714 +#define AArch64_RADDHNB_ZZZ_H 3715 +#define AArch64_RADDHNB_ZZZ_S 3716 +#define AArch64_RADDHNT_ZZZ_B 3717 +#define AArch64_RADDHNT_ZZZ_H 3718 +#define AArch64_RADDHNT_ZZZ_S 3719 +#define AArch64_RADDHNv2i64_v2i32 3720 +#define AArch64_RADDHNv2i64_v4i32 3721 +#define AArch64_RADDHNv4i32_v4i16 3722 +#define AArch64_RADDHNv4i32_v8i16 3723 +#define AArch64_RADDHNv8i16_v16i8 3724 +#define AArch64_RADDHNv8i16_v8i8 3725 +#define AArch64_RAX1 3726 +#define AArch64_RAX1_ZZZ_D 3727 +#define AArch64_RBITWr 3728 +#define AArch64_RBITXr 3729 +#define AArch64_RBIT_ZPmZ_B 3730 +#define AArch64_RBIT_ZPmZ_D 3731 +#define AArch64_RBIT_ZPmZ_H 3732 +#define AArch64_RBIT_ZPmZ_S 3733 +#define AArch64_RBITv16i8 3734 +#define AArch64_RBITv8i8 3735 +#define AArch64_RDFFRS_PPz 3736 +#define AArch64_RDFFR_PPz_REAL 3737 +#define AArch64_RDFFR_P_REAL 3738 +#define AArch64_RDVLI_XI 3739 +#define AArch64_RET 3740 +#define AArch64_RETAA 3741 +#define AArch64_RETAB 3742 +#define AArch64_REV16Wr 3743 +#define AArch64_REV16Xr 3744 +#define AArch64_REV16v16i8 3745 +#define AArch64_REV16v8i8 3746 +#define AArch64_REV32Xr 3747 +#define AArch64_REV32v16i8 3748 +#define AArch64_REV32v4i16 3749 +#define AArch64_REV32v8i16 3750 +#define AArch64_REV32v8i8 3751 +#define AArch64_REV64v16i8 3752 +#define AArch64_REV64v2i32 3753 +#define AArch64_REV64v4i16 3754 +#define AArch64_REV64v4i32 3755 +#define AArch64_REV64v8i16 3756 +#define AArch64_REV64v8i8 3757 +#define AArch64_REVB_ZPmZ_D 3758 +#define AArch64_REVB_ZPmZ_H 3759 +#define AArch64_REVB_ZPmZ_S 3760 +#define AArch64_REVD_ZPmZ 3761 +#define AArch64_REVH_ZPmZ_D 3762 +#define AArch64_REVH_ZPmZ_S 3763 +#define AArch64_REVW_ZPmZ_D 3764 +#define AArch64_REVWr 3765 +#define AArch64_REVXr 3766 +#define AArch64_REV_PP_B 3767 +#define AArch64_REV_PP_D 3768 +#define AArch64_REV_PP_H 3769 +#define AArch64_REV_PP_S 3770 +#define AArch64_REV_ZZ_B 3771 +#define AArch64_REV_ZZ_D 3772 +#define AArch64_REV_ZZ_H 3773 +#define AArch64_REV_ZZ_S 3774 +#define AArch64_RMIF 3775 +#define AArch64_RORVWr 3776 +#define AArch64_RORVXr 3777 +#define AArch64_RSHRNB_ZZI_B 3778 +#define AArch64_RSHRNB_ZZI_H 3779 +#define AArch64_RSHRNB_ZZI_S 3780 +#define AArch64_RSHRNT_ZZI_B 3781 +#define AArch64_RSHRNT_ZZI_H 3782 +#define AArch64_RSHRNT_ZZI_S 3783 +#define AArch64_RSHRNv16i8_shift 3784 +#define AArch64_RSHRNv2i32_shift 3785 +#define AArch64_RSHRNv4i16_shift 3786 +#define AArch64_RSHRNv4i32_shift 3787 +#define AArch64_RSHRNv8i16_shift 3788 +#define AArch64_RSHRNv8i8_shift 3789 +#define AArch64_RSUBHNB_ZZZ_B 3790 +#define AArch64_RSUBHNB_ZZZ_H 3791 +#define AArch64_RSUBHNB_ZZZ_S 3792 +#define AArch64_RSUBHNT_ZZZ_B 3793 +#define AArch64_RSUBHNT_ZZZ_H 3794 +#define AArch64_RSUBHNT_ZZZ_S 3795 +#define AArch64_RSUBHNv2i64_v2i32 3796 +#define AArch64_RSUBHNv2i64_v4i32 3797 +#define AArch64_RSUBHNv4i32_v4i16 3798 +#define AArch64_RSUBHNv4i32_v8i16 3799 +#define AArch64_RSUBHNv8i16_v16i8 3800 +#define AArch64_RSUBHNv8i16_v8i8 3801 +#define AArch64_SABALB_ZZZ_D 3802 +#define AArch64_SABALB_ZZZ_H 3803 +#define AArch64_SABALB_ZZZ_S 3804 +#define AArch64_SABALT_ZZZ_D 3805 +#define AArch64_SABALT_ZZZ_H 3806 +#define AArch64_SABALT_ZZZ_S 3807 +#define AArch64_SABALv16i8_v8i16 3808 +#define AArch64_SABALv2i32_v2i64 3809 +#define AArch64_SABALv4i16_v4i32 3810 +#define AArch64_SABALv4i32_v2i64 3811 +#define AArch64_SABALv8i16_v4i32 3812 +#define AArch64_SABALv8i8_v8i16 3813 +#define AArch64_SABA_ZZZ_B 3814 +#define AArch64_SABA_ZZZ_D 3815 +#define AArch64_SABA_ZZZ_H 3816 +#define AArch64_SABA_ZZZ_S 3817 +#define AArch64_SABAv16i8 3818 +#define AArch64_SABAv2i32 3819 +#define AArch64_SABAv4i16 3820 +#define AArch64_SABAv4i32 3821 +#define AArch64_SABAv8i16 3822 +#define AArch64_SABAv8i8 3823 +#define AArch64_SABDLB_ZZZ_D 3824 +#define AArch64_SABDLB_ZZZ_H 3825 +#define AArch64_SABDLB_ZZZ_S 3826 +#define AArch64_SABDLT_ZZZ_D 3827 +#define AArch64_SABDLT_ZZZ_H 3828 +#define AArch64_SABDLT_ZZZ_S 3829 +#define AArch64_SABDLv16i8_v8i16 3830 +#define AArch64_SABDLv2i32_v2i64 3831 +#define AArch64_SABDLv4i16_v4i32 3832 +#define AArch64_SABDLv4i32_v2i64 3833 +#define AArch64_SABDLv8i16_v4i32 3834 +#define AArch64_SABDLv8i8_v8i16 3835 +#define AArch64_SABD_ZPmZ_B 3836 +#define AArch64_SABD_ZPmZ_D 3837 +#define AArch64_SABD_ZPmZ_H 3838 +#define AArch64_SABD_ZPmZ_S 3839 +#define AArch64_SABDv16i8 3840 +#define AArch64_SABDv2i32 3841 +#define AArch64_SABDv4i16 3842 +#define AArch64_SABDv4i32 3843 +#define AArch64_SABDv8i16 3844 +#define AArch64_SABDv8i8 3845 +#define AArch64_SADALP_ZPmZ_D 3846 +#define AArch64_SADALP_ZPmZ_H 3847 +#define AArch64_SADALP_ZPmZ_S 3848 +#define AArch64_SADALPv16i8_v8i16 3849 +#define AArch64_SADALPv2i32_v1i64 3850 +#define AArch64_SADALPv4i16_v2i32 3851 +#define AArch64_SADALPv4i32_v2i64 3852 +#define AArch64_SADALPv8i16_v4i32 3853 +#define AArch64_SADALPv8i8_v4i16 3854 +#define AArch64_SADDLBT_ZZZ_D 3855 +#define AArch64_SADDLBT_ZZZ_H 3856 +#define AArch64_SADDLBT_ZZZ_S 3857 +#define AArch64_SADDLB_ZZZ_D 3858 +#define AArch64_SADDLB_ZZZ_H 3859 +#define AArch64_SADDLB_ZZZ_S 3860 +#define AArch64_SADDLPv16i8_v8i16 3861 +#define AArch64_SADDLPv2i32_v1i64 3862 +#define AArch64_SADDLPv4i16_v2i32 3863 +#define AArch64_SADDLPv4i32_v2i64 3864 +#define AArch64_SADDLPv8i16_v4i32 3865 +#define AArch64_SADDLPv8i8_v4i16 3866 +#define AArch64_SADDLT_ZZZ_D 3867 +#define AArch64_SADDLT_ZZZ_H 3868 +#define AArch64_SADDLT_ZZZ_S 3869 +#define AArch64_SADDLVv16i8v 3870 +#define AArch64_SADDLVv4i16v 3871 +#define AArch64_SADDLVv4i32v 3872 +#define AArch64_SADDLVv8i16v 3873 +#define AArch64_SADDLVv8i8v 3874 +#define AArch64_SADDLv16i8_v8i16 3875 +#define AArch64_SADDLv2i32_v2i64 3876 +#define AArch64_SADDLv4i16_v4i32 3877 +#define AArch64_SADDLv4i32_v2i64 3878 +#define AArch64_SADDLv8i16_v4i32 3879 +#define AArch64_SADDLv8i8_v8i16 3880 +#define AArch64_SADDV_VPZ_B 3881 +#define AArch64_SADDV_VPZ_H 3882 +#define AArch64_SADDV_VPZ_S 3883 +#define AArch64_SADDWB_ZZZ_D 3884 +#define AArch64_SADDWB_ZZZ_H 3885 +#define AArch64_SADDWB_ZZZ_S 3886 +#define AArch64_SADDWT_ZZZ_D 3887 +#define AArch64_SADDWT_ZZZ_H 3888 +#define AArch64_SADDWT_ZZZ_S 3889 +#define AArch64_SADDWv16i8_v8i16 3890 +#define AArch64_SADDWv2i32_v2i64 3891 +#define AArch64_SADDWv4i16_v4i32 3892 +#define AArch64_SADDWv4i32_v2i64 3893 +#define AArch64_SADDWv8i16_v4i32 3894 +#define AArch64_SADDWv8i8_v8i16 3895 +#define AArch64_SB 3896 +#define AArch64_SBCLB_ZZZ_D 3897 +#define AArch64_SBCLB_ZZZ_S 3898 +#define AArch64_SBCLT_ZZZ_D 3899 +#define AArch64_SBCLT_ZZZ_S 3900 +#define AArch64_SBCSWr 3901 +#define AArch64_SBCSXr 3902 +#define AArch64_SBCWr 3903 +#define AArch64_SBCXr 3904 +#define AArch64_SBFMWri 3905 +#define AArch64_SBFMXri 3906 +#define AArch64_SCLAMP_ZZZ_B 3907 +#define AArch64_SCLAMP_ZZZ_D 3908 +#define AArch64_SCLAMP_ZZZ_H 3909 +#define AArch64_SCLAMP_ZZZ_S 3910 +#define AArch64_SCVTFSWDri 3911 +#define AArch64_SCVTFSWHri 3912 +#define AArch64_SCVTFSWSri 3913 +#define AArch64_SCVTFSXDri 3914 +#define AArch64_SCVTFSXHri 3915 +#define AArch64_SCVTFSXSri 3916 +#define AArch64_SCVTFUWDri 3917 +#define AArch64_SCVTFUWHri 3918 +#define AArch64_SCVTFUWSri 3919 +#define AArch64_SCVTFUXDri 3920 +#define AArch64_SCVTFUXHri 3921 +#define AArch64_SCVTFUXSri 3922 +#define AArch64_SCVTF_ZPmZ_DtoD 3923 +#define AArch64_SCVTF_ZPmZ_DtoH 3924 +#define AArch64_SCVTF_ZPmZ_DtoS 3925 +#define AArch64_SCVTF_ZPmZ_HtoH 3926 +#define AArch64_SCVTF_ZPmZ_StoD 3927 +#define AArch64_SCVTF_ZPmZ_StoH 3928 +#define AArch64_SCVTF_ZPmZ_StoS 3929 +#define AArch64_SCVTFd 3930 +#define AArch64_SCVTFh 3931 +#define AArch64_SCVTFs 3932 +#define AArch64_SCVTFv1i16 3933 +#define AArch64_SCVTFv1i32 3934 +#define AArch64_SCVTFv1i64 3935 +#define AArch64_SCVTFv2f32 3936 +#define AArch64_SCVTFv2f64 3937 +#define AArch64_SCVTFv2i32_shift 3938 +#define AArch64_SCVTFv2i64_shift 3939 +#define AArch64_SCVTFv4f16 3940 +#define AArch64_SCVTFv4f32 3941 +#define AArch64_SCVTFv4i16_shift 3942 +#define AArch64_SCVTFv4i32_shift 3943 +#define AArch64_SCVTFv8f16 3944 +#define AArch64_SCVTFv8i16_shift 3945 +#define AArch64_SDIVR_ZPmZ_D 3946 +#define AArch64_SDIVR_ZPmZ_S 3947 +#define AArch64_SDIVWr 3948 +#define AArch64_SDIVXr 3949 +#define AArch64_SDIV_ZPmZ_D 3950 +#define AArch64_SDIV_ZPmZ_S 3951 +#define AArch64_SDOT_ZZZI_D 3952 +#define AArch64_SDOT_ZZZI_S 3953 +#define AArch64_SDOT_ZZZ_D 3954 +#define AArch64_SDOT_ZZZ_S 3955 +#define AArch64_SDOTlanev16i8 3956 +#define AArch64_SDOTlanev8i8 3957 +#define AArch64_SDOTv16i8 3958 +#define AArch64_SDOTv8i8 3959 +#define AArch64_SEL_PPPP 3960 +#define AArch64_SEL_ZPZZ_B 3961 +#define AArch64_SEL_ZPZZ_D 3962 +#define AArch64_SEL_ZPZZ_H 3963 +#define AArch64_SEL_ZPZZ_S 3964 +#define AArch64_SETF16 3965 +#define AArch64_SETF8 3966 +#define AArch64_SETFFR 3967 +#define AArch64_SHA1Crrr 3968 +#define AArch64_SHA1Hrr 3969 +#define AArch64_SHA1Mrrr 3970 +#define AArch64_SHA1Prrr 3971 +#define AArch64_SHA1SU0rrr 3972 +#define AArch64_SHA1SU1rr 3973 +#define AArch64_SHA256H2rrr 3974 +#define AArch64_SHA256Hrrr 3975 +#define AArch64_SHA256SU0rr 3976 +#define AArch64_SHA256SU1rrr 3977 +#define AArch64_SHA512H 3978 +#define AArch64_SHA512H2 3979 +#define AArch64_SHA512SU0 3980 +#define AArch64_SHA512SU1 3981 +#define AArch64_SHADD_ZPmZ_B 3982 +#define AArch64_SHADD_ZPmZ_D 3983 +#define AArch64_SHADD_ZPmZ_H 3984 +#define AArch64_SHADD_ZPmZ_S 3985 +#define AArch64_SHADDv16i8 3986 +#define AArch64_SHADDv2i32 3987 +#define AArch64_SHADDv4i16 3988 +#define AArch64_SHADDv4i32 3989 +#define AArch64_SHADDv8i16 3990 +#define AArch64_SHADDv8i8 3991 +#define AArch64_SHLLv16i8 3992 +#define AArch64_SHLLv2i32 3993 +#define AArch64_SHLLv4i16 3994 +#define AArch64_SHLLv4i32 3995 +#define AArch64_SHLLv8i16 3996 +#define AArch64_SHLLv8i8 3997 +#define AArch64_SHLd 3998 +#define AArch64_SHLv16i8_shift 3999 +#define AArch64_SHLv2i32_shift 4000 +#define AArch64_SHLv2i64_shift 4001 +#define AArch64_SHLv4i16_shift 4002 +#define AArch64_SHLv4i32_shift 4003 +#define AArch64_SHLv8i16_shift 4004 +#define AArch64_SHLv8i8_shift 4005 +#define AArch64_SHRNB_ZZI_B 4006 +#define AArch64_SHRNB_ZZI_H 4007 +#define AArch64_SHRNB_ZZI_S 4008 +#define AArch64_SHRNT_ZZI_B 4009 +#define AArch64_SHRNT_ZZI_H 4010 +#define AArch64_SHRNT_ZZI_S 4011 +#define AArch64_SHRNv16i8_shift 4012 +#define AArch64_SHRNv2i32_shift 4013 +#define AArch64_SHRNv4i16_shift 4014 +#define AArch64_SHRNv4i32_shift 4015 +#define AArch64_SHRNv8i16_shift 4016 +#define AArch64_SHRNv8i8_shift 4017 +#define AArch64_SHSUBR_ZPmZ_B 4018 +#define AArch64_SHSUBR_ZPmZ_D 4019 +#define AArch64_SHSUBR_ZPmZ_H 4020 +#define AArch64_SHSUBR_ZPmZ_S 4021 +#define AArch64_SHSUB_ZPmZ_B 4022 +#define AArch64_SHSUB_ZPmZ_D 4023 +#define AArch64_SHSUB_ZPmZ_H 4024 +#define AArch64_SHSUB_ZPmZ_S 4025 +#define AArch64_SHSUBv16i8 4026 +#define AArch64_SHSUBv2i32 4027 +#define AArch64_SHSUBv4i16 4028 +#define AArch64_SHSUBv4i32 4029 +#define AArch64_SHSUBv8i16 4030 +#define AArch64_SHSUBv8i8 4031 +#define AArch64_SLI_ZZI_B 4032 +#define AArch64_SLI_ZZI_D 4033 +#define AArch64_SLI_ZZI_H 4034 +#define AArch64_SLI_ZZI_S 4035 +#define AArch64_SLId 4036 +#define AArch64_SLIv16i8_shift 4037 +#define AArch64_SLIv2i32_shift 4038 +#define AArch64_SLIv2i64_shift 4039 +#define AArch64_SLIv4i16_shift 4040 +#define AArch64_SLIv4i32_shift 4041 +#define AArch64_SLIv8i16_shift 4042 +#define AArch64_SLIv8i8_shift 4043 +#define AArch64_SM3PARTW1 4044 +#define AArch64_SM3PARTW2 4045 +#define AArch64_SM3SS1 4046 +#define AArch64_SM3TT1A 4047 +#define AArch64_SM3TT1B 4048 +#define AArch64_SM3TT2A 4049 +#define AArch64_SM3TT2B 4050 +#define AArch64_SM4E 4051 +#define AArch64_SM4EKEY_ZZZ_S 4052 +#define AArch64_SM4ENCKEY 4053 +#define AArch64_SM4E_ZZZ_S 4054 +#define AArch64_SMADDLrrr 4055 +#define AArch64_SMAXP_ZPmZ_B 4056 +#define AArch64_SMAXP_ZPmZ_D 4057 +#define AArch64_SMAXP_ZPmZ_H 4058 +#define AArch64_SMAXP_ZPmZ_S 4059 +#define AArch64_SMAXPv16i8 4060 +#define AArch64_SMAXPv2i32 4061 +#define AArch64_SMAXPv4i16 4062 +#define AArch64_SMAXPv4i32 4063 +#define AArch64_SMAXPv8i16 4064 +#define AArch64_SMAXPv8i8 4065 +#define AArch64_SMAXV_VPZ_B 4066 +#define AArch64_SMAXV_VPZ_D 4067 +#define AArch64_SMAXV_VPZ_H 4068 +#define AArch64_SMAXV_VPZ_S 4069 +#define AArch64_SMAXVv16i8v 4070 +#define AArch64_SMAXVv4i16v 4071 +#define AArch64_SMAXVv4i32v 4072 +#define AArch64_SMAXVv8i16v 4073 +#define AArch64_SMAXVv8i8v 4074 +#define AArch64_SMAX_ZI_B 4075 +#define AArch64_SMAX_ZI_D 4076 +#define AArch64_SMAX_ZI_H 4077 +#define AArch64_SMAX_ZI_S 4078 +#define AArch64_SMAX_ZPmZ_B 4079 +#define AArch64_SMAX_ZPmZ_D 4080 +#define AArch64_SMAX_ZPmZ_H 4081 +#define AArch64_SMAX_ZPmZ_S 4082 +#define AArch64_SMAXv16i8 4083 +#define AArch64_SMAXv2i32 4084 +#define AArch64_SMAXv4i16 4085 +#define AArch64_SMAXv4i32 4086 +#define AArch64_SMAXv8i16 4087 +#define AArch64_SMAXv8i8 4088 +#define AArch64_SMC 4089 +#define AArch64_SMINP_ZPmZ_B 4090 +#define AArch64_SMINP_ZPmZ_D 4091 +#define AArch64_SMINP_ZPmZ_H 4092 +#define AArch64_SMINP_ZPmZ_S 4093 +#define AArch64_SMINPv16i8 4094 +#define AArch64_SMINPv2i32 4095 +#define AArch64_SMINPv4i16 4096 +#define AArch64_SMINPv4i32 4097 +#define AArch64_SMINPv8i16 4098 +#define AArch64_SMINPv8i8 4099 +#define AArch64_SMINV_VPZ_B 4100 +#define AArch64_SMINV_VPZ_D 4101 +#define AArch64_SMINV_VPZ_H 4102 +#define AArch64_SMINV_VPZ_S 4103 +#define AArch64_SMINVv16i8v 4104 +#define AArch64_SMINVv4i16v 4105 +#define AArch64_SMINVv4i32v 4106 +#define AArch64_SMINVv8i16v 4107 +#define AArch64_SMINVv8i8v 4108 +#define AArch64_SMIN_ZI_B 4109 +#define AArch64_SMIN_ZI_D 4110 +#define AArch64_SMIN_ZI_H 4111 +#define AArch64_SMIN_ZI_S 4112 +#define AArch64_SMIN_ZPmZ_B 4113 +#define AArch64_SMIN_ZPmZ_D 4114 +#define AArch64_SMIN_ZPmZ_H 4115 +#define AArch64_SMIN_ZPmZ_S 4116 +#define AArch64_SMINv16i8 4117 +#define AArch64_SMINv2i32 4118 +#define AArch64_SMINv4i16 4119 +#define AArch64_SMINv4i32 4120 +#define AArch64_SMINv8i16 4121 +#define AArch64_SMINv8i8 4122 +#define AArch64_SMLALB_ZZZI_D 4123 +#define AArch64_SMLALB_ZZZI_S 4124 +#define AArch64_SMLALB_ZZZ_D 4125 +#define AArch64_SMLALB_ZZZ_H 4126 +#define AArch64_SMLALB_ZZZ_S 4127 +#define AArch64_SMLALT_ZZZI_D 4128 +#define AArch64_SMLALT_ZZZI_S 4129 +#define AArch64_SMLALT_ZZZ_D 4130 +#define AArch64_SMLALT_ZZZ_H 4131 +#define AArch64_SMLALT_ZZZ_S 4132 +#define AArch64_SMLALv16i8_v8i16 4133 +#define AArch64_SMLALv2i32_indexed 4134 +#define AArch64_SMLALv2i32_v2i64 4135 +#define AArch64_SMLALv4i16_indexed 4136 +#define AArch64_SMLALv4i16_v4i32 4137 +#define AArch64_SMLALv4i32_indexed 4138 +#define AArch64_SMLALv4i32_v2i64 4139 +#define AArch64_SMLALv8i16_indexed 4140 +#define AArch64_SMLALv8i16_v4i32 4141 +#define AArch64_SMLALv8i8_v8i16 4142 +#define AArch64_SMLSLB_ZZZI_D 4143 +#define AArch64_SMLSLB_ZZZI_S 4144 +#define AArch64_SMLSLB_ZZZ_D 4145 +#define AArch64_SMLSLB_ZZZ_H 4146 +#define AArch64_SMLSLB_ZZZ_S 4147 +#define AArch64_SMLSLT_ZZZI_D 4148 +#define AArch64_SMLSLT_ZZZI_S 4149 +#define AArch64_SMLSLT_ZZZ_D 4150 +#define AArch64_SMLSLT_ZZZ_H 4151 +#define AArch64_SMLSLT_ZZZ_S 4152 +#define AArch64_SMLSLv16i8_v8i16 4153 +#define AArch64_SMLSLv2i32_indexed 4154 +#define AArch64_SMLSLv2i32_v2i64 4155 +#define AArch64_SMLSLv4i16_indexed 4156 +#define AArch64_SMLSLv4i16_v4i32 4157 +#define AArch64_SMLSLv4i32_indexed 4158 +#define AArch64_SMLSLv4i32_v2i64 4159 +#define AArch64_SMLSLv8i16_indexed 4160 +#define AArch64_SMLSLv8i16_v4i32 4161 +#define AArch64_SMLSLv8i8_v8i16 4162 +#define AArch64_SMMLA 4163 +#define AArch64_SMMLA_ZZZ 4164 +#define AArch64_SMOPA_MPPZZ_D 4165 +#define AArch64_SMOPA_MPPZZ_S 4166 +#define AArch64_SMOPS_MPPZZ_D 4167 +#define AArch64_SMOPS_MPPZZ_S 4168 +#define AArch64_SMOVvi16to32 4169 +#define AArch64_SMOVvi16to32_idx0 4170 +#define AArch64_SMOVvi16to64 4171 +#define AArch64_SMOVvi16to64_idx0 4172 +#define AArch64_SMOVvi32to64 4173 +#define AArch64_SMOVvi32to64_idx0 4174 +#define AArch64_SMOVvi8to32 4175 +#define AArch64_SMOVvi8to32_idx0 4176 +#define AArch64_SMOVvi8to64 4177 +#define AArch64_SMOVvi8to64_idx0 4178 +#define AArch64_SMSUBLrrr 4179 +#define AArch64_SMULH_ZPmZ_B 4180 +#define AArch64_SMULH_ZPmZ_D 4181 +#define AArch64_SMULH_ZPmZ_H 4182 +#define AArch64_SMULH_ZPmZ_S 4183 +#define AArch64_SMULH_ZZZ_B 4184 +#define AArch64_SMULH_ZZZ_D 4185 +#define AArch64_SMULH_ZZZ_H 4186 +#define AArch64_SMULH_ZZZ_S 4187 +#define AArch64_SMULHrr 4188 +#define AArch64_SMULLB_ZZZI_D 4189 +#define AArch64_SMULLB_ZZZI_S 4190 +#define AArch64_SMULLB_ZZZ_D 4191 +#define AArch64_SMULLB_ZZZ_H 4192 +#define AArch64_SMULLB_ZZZ_S 4193 +#define AArch64_SMULLT_ZZZI_D 4194 +#define AArch64_SMULLT_ZZZI_S 4195 +#define AArch64_SMULLT_ZZZ_D 4196 +#define AArch64_SMULLT_ZZZ_H 4197 +#define AArch64_SMULLT_ZZZ_S 4198 +#define AArch64_SMULLv16i8_v8i16 4199 +#define AArch64_SMULLv2i32_indexed 4200 +#define AArch64_SMULLv2i32_v2i64 4201 +#define AArch64_SMULLv4i16_indexed 4202 +#define AArch64_SMULLv4i16_v4i32 4203 +#define AArch64_SMULLv4i32_indexed 4204 +#define AArch64_SMULLv4i32_v2i64 4205 +#define AArch64_SMULLv8i16_indexed 4206 +#define AArch64_SMULLv8i16_v4i32 4207 +#define AArch64_SMULLv8i8_v8i16 4208 +#define AArch64_SPLICE_ZPZZ_B 4209 +#define AArch64_SPLICE_ZPZZ_D 4210 +#define AArch64_SPLICE_ZPZZ_H 4211 +#define AArch64_SPLICE_ZPZZ_S 4212 +#define AArch64_SPLICE_ZPZ_B 4213 +#define AArch64_SPLICE_ZPZ_D 4214 +#define AArch64_SPLICE_ZPZ_H 4215 +#define AArch64_SPLICE_ZPZ_S 4216 +#define AArch64_SQABS_ZPmZ_B 4217 +#define AArch64_SQABS_ZPmZ_D 4218 +#define AArch64_SQABS_ZPmZ_H 4219 +#define AArch64_SQABS_ZPmZ_S 4220 +#define AArch64_SQABSv16i8 4221 +#define AArch64_SQABSv1i16 4222 +#define AArch64_SQABSv1i32 4223 +#define AArch64_SQABSv1i64 4224 +#define AArch64_SQABSv1i8 4225 +#define AArch64_SQABSv2i32 4226 +#define AArch64_SQABSv2i64 4227 +#define AArch64_SQABSv4i16 4228 +#define AArch64_SQABSv4i32 4229 +#define AArch64_SQABSv8i16 4230 +#define AArch64_SQABSv8i8 4231 +#define AArch64_SQADD_ZI_B 4232 +#define AArch64_SQADD_ZI_D 4233 +#define AArch64_SQADD_ZI_H 4234 +#define AArch64_SQADD_ZI_S 4235 +#define AArch64_SQADD_ZPmZ_B 4236 +#define AArch64_SQADD_ZPmZ_D 4237 +#define AArch64_SQADD_ZPmZ_H 4238 +#define AArch64_SQADD_ZPmZ_S 4239 +#define AArch64_SQADD_ZZZ_B 4240 +#define AArch64_SQADD_ZZZ_D 4241 +#define AArch64_SQADD_ZZZ_H 4242 +#define AArch64_SQADD_ZZZ_S 4243 +#define AArch64_SQADDv16i8 4244 +#define AArch64_SQADDv1i16 4245 +#define AArch64_SQADDv1i32 4246 +#define AArch64_SQADDv1i64 4247 +#define AArch64_SQADDv1i8 4248 +#define AArch64_SQADDv2i32 4249 +#define AArch64_SQADDv2i64 4250 +#define AArch64_SQADDv4i16 4251 +#define AArch64_SQADDv4i32 4252 +#define AArch64_SQADDv8i16 4253 +#define AArch64_SQADDv8i8 4254 +#define AArch64_SQCADD_ZZI_B 4255 +#define AArch64_SQCADD_ZZI_D 4256 +#define AArch64_SQCADD_ZZI_H 4257 +#define AArch64_SQCADD_ZZI_S 4258 +#define AArch64_SQDECB_XPiI 4259 +#define AArch64_SQDECB_XPiWdI 4260 +#define AArch64_SQDECD_XPiI 4261 +#define AArch64_SQDECD_XPiWdI 4262 +#define AArch64_SQDECD_ZPiI 4263 +#define AArch64_SQDECH_XPiI 4264 +#define AArch64_SQDECH_XPiWdI 4265 +#define AArch64_SQDECH_ZPiI 4266 +#define AArch64_SQDECP_XPWd_B 4267 +#define AArch64_SQDECP_XPWd_D 4268 +#define AArch64_SQDECP_XPWd_H 4269 +#define AArch64_SQDECP_XPWd_S 4270 +#define AArch64_SQDECP_XP_B 4271 +#define AArch64_SQDECP_XP_D 4272 +#define AArch64_SQDECP_XP_H 4273 +#define AArch64_SQDECP_XP_S 4274 +#define AArch64_SQDECP_ZP_D 4275 +#define AArch64_SQDECP_ZP_H 4276 +#define AArch64_SQDECP_ZP_S 4277 +#define AArch64_SQDECW_XPiI 4278 +#define AArch64_SQDECW_XPiWdI 4279 +#define AArch64_SQDECW_ZPiI 4280 +#define AArch64_SQDMLALBT_ZZZ_D 4281 +#define AArch64_SQDMLALBT_ZZZ_H 4282 +#define AArch64_SQDMLALBT_ZZZ_S 4283 +#define AArch64_SQDMLALB_ZZZI_D 4284 +#define AArch64_SQDMLALB_ZZZI_S 4285 +#define AArch64_SQDMLALB_ZZZ_D 4286 +#define AArch64_SQDMLALB_ZZZ_H 4287 +#define AArch64_SQDMLALB_ZZZ_S 4288 +#define AArch64_SQDMLALT_ZZZI_D 4289 +#define AArch64_SQDMLALT_ZZZI_S 4290 +#define AArch64_SQDMLALT_ZZZ_D 4291 +#define AArch64_SQDMLALT_ZZZ_H 4292 +#define AArch64_SQDMLALT_ZZZ_S 4293 +#define AArch64_SQDMLALi16 4294 +#define AArch64_SQDMLALi32 4295 +#define AArch64_SQDMLALv1i32_indexed 4296 +#define AArch64_SQDMLALv1i64_indexed 4297 +#define AArch64_SQDMLALv2i32_indexed 4298 +#define AArch64_SQDMLALv2i32_v2i64 4299 +#define AArch64_SQDMLALv4i16_indexed 4300 +#define AArch64_SQDMLALv4i16_v4i32 4301 +#define AArch64_SQDMLALv4i32_indexed 4302 +#define AArch64_SQDMLALv4i32_v2i64 4303 +#define AArch64_SQDMLALv8i16_indexed 4304 +#define AArch64_SQDMLALv8i16_v4i32 4305 +#define AArch64_SQDMLSLBT_ZZZ_D 4306 +#define AArch64_SQDMLSLBT_ZZZ_H 4307 +#define AArch64_SQDMLSLBT_ZZZ_S 4308 +#define AArch64_SQDMLSLB_ZZZI_D 4309 +#define AArch64_SQDMLSLB_ZZZI_S 4310 +#define AArch64_SQDMLSLB_ZZZ_D 4311 +#define AArch64_SQDMLSLB_ZZZ_H 4312 +#define AArch64_SQDMLSLB_ZZZ_S 4313 +#define AArch64_SQDMLSLT_ZZZI_D 4314 +#define AArch64_SQDMLSLT_ZZZI_S 4315 +#define AArch64_SQDMLSLT_ZZZ_D 4316 +#define AArch64_SQDMLSLT_ZZZ_H 4317 +#define AArch64_SQDMLSLT_ZZZ_S 4318 +#define AArch64_SQDMLSLi16 4319 +#define AArch64_SQDMLSLi32 4320 +#define AArch64_SQDMLSLv1i32_indexed 4321 +#define AArch64_SQDMLSLv1i64_indexed 4322 +#define AArch64_SQDMLSLv2i32_indexed 4323 +#define AArch64_SQDMLSLv2i32_v2i64 4324 +#define AArch64_SQDMLSLv4i16_indexed 4325 +#define AArch64_SQDMLSLv4i16_v4i32 4326 +#define AArch64_SQDMLSLv4i32_indexed 4327 +#define AArch64_SQDMLSLv4i32_v2i64 4328 +#define AArch64_SQDMLSLv8i16_indexed 4329 +#define AArch64_SQDMLSLv8i16_v4i32 4330 +#define AArch64_SQDMULH_ZZZI_D 4331 +#define AArch64_SQDMULH_ZZZI_H 4332 +#define AArch64_SQDMULH_ZZZI_S 4333 +#define AArch64_SQDMULH_ZZZ_B 4334 +#define AArch64_SQDMULH_ZZZ_D 4335 +#define AArch64_SQDMULH_ZZZ_H 4336 +#define AArch64_SQDMULH_ZZZ_S 4337 +#define AArch64_SQDMULHv1i16 4338 +#define AArch64_SQDMULHv1i16_indexed 4339 +#define AArch64_SQDMULHv1i32 4340 +#define AArch64_SQDMULHv1i32_indexed 4341 +#define AArch64_SQDMULHv2i32 4342 +#define AArch64_SQDMULHv2i32_indexed 4343 +#define AArch64_SQDMULHv4i16 4344 +#define AArch64_SQDMULHv4i16_indexed 4345 +#define AArch64_SQDMULHv4i32 4346 +#define AArch64_SQDMULHv4i32_indexed 4347 +#define AArch64_SQDMULHv8i16 4348 +#define AArch64_SQDMULHv8i16_indexed 4349 +#define AArch64_SQDMULLB_ZZZI_D 4350 +#define AArch64_SQDMULLB_ZZZI_S 4351 +#define AArch64_SQDMULLB_ZZZ_D 4352 +#define AArch64_SQDMULLB_ZZZ_H 4353 +#define AArch64_SQDMULLB_ZZZ_S 4354 +#define AArch64_SQDMULLT_ZZZI_D 4355 +#define AArch64_SQDMULLT_ZZZI_S 4356 +#define AArch64_SQDMULLT_ZZZ_D 4357 +#define AArch64_SQDMULLT_ZZZ_H 4358 +#define AArch64_SQDMULLT_ZZZ_S 4359 +#define AArch64_SQDMULLi16 4360 +#define AArch64_SQDMULLi32 4361 +#define AArch64_SQDMULLv1i32_indexed 4362 +#define AArch64_SQDMULLv1i64_indexed 4363 +#define AArch64_SQDMULLv2i32_indexed 4364 +#define AArch64_SQDMULLv2i32_v2i64 4365 +#define AArch64_SQDMULLv4i16_indexed 4366 +#define AArch64_SQDMULLv4i16_v4i32 4367 +#define AArch64_SQDMULLv4i32_indexed 4368 +#define AArch64_SQDMULLv4i32_v2i64 4369 +#define AArch64_SQDMULLv8i16_indexed 4370 +#define AArch64_SQDMULLv8i16_v4i32 4371 +#define AArch64_SQINCB_XPiI 4372 +#define AArch64_SQINCB_XPiWdI 4373 +#define AArch64_SQINCD_XPiI 4374 +#define AArch64_SQINCD_XPiWdI 4375 +#define AArch64_SQINCD_ZPiI 4376 +#define AArch64_SQINCH_XPiI 4377 +#define AArch64_SQINCH_XPiWdI 4378 +#define AArch64_SQINCH_ZPiI 4379 +#define AArch64_SQINCP_XPWd_B 4380 +#define AArch64_SQINCP_XPWd_D 4381 +#define AArch64_SQINCP_XPWd_H 4382 +#define AArch64_SQINCP_XPWd_S 4383 +#define AArch64_SQINCP_XP_B 4384 +#define AArch64_SQINCP_XP_D 4385 +#define AArch64_SQINCP_XP_H 4386 +#define AArch64_SQINCP_XP_S 4387 +#define AArch64_SQINCP_ZP_D 4388 +#define AArch64_SQINCP_ZP_H 4389 +#define AArch64_SQINCP_ZP_S 4390 +#define AArch64_SQINCW_XPiI 4391 +#define AArch64_SQINCW_XPiWdI 4392 +#define AArch64_SQINCW_ZPiI 4393 +#define AArch64_SQNEG_ZPmZ_B 4394 +#define AArch64_SQNEG_ZPmZ_D 4395 +#define AArch64_SQNEG_ZPmZ_H 4396 +#define AArch64_SQNEG_ZPmZ_S 4397 +#define AArch64_SQNEGv16i8 4398 +#define AArch64_SQNEGv1i16 4399 +#define AArch64_SQNEGv1i32 4400 +#define AArch64_SQNEGv1i64 4401 +#define AArch64_SQNEGv1i8 4402 +#define AArch64_SQNEGv2i32 4403 +#define AArch64_SQNEGv2i64 4404 +#define AArch64_SQNEGv4i16 4405 +#define AArch64_SQNEGv4i32 4406 +#define AArch64_SQNEGv8i16 4407 +#define AArch64_SQNEGv8i8 4408 +#define AArch64_SQRDCMLAH_ZZZI_H 4409 +#define AArch64_SQRDCMLAH_ZZZI_S 4410 +#define AArch64_SQRDCMLAH_ZZZ_B 4411 +#define AArch64_SQRDCMLAH_ZZZ_D 4412 +#define AArch64_SQRDCMLAH_ZZZ_H 4413 +#define AArch64_SQRDCMLAH_ZZZ_S 4414 +#define AArch64_SQRDMLAH_ZZZI_D 4415 +#define AArch64_SQRDMLAH_ZZZI_H 4416 +#define AArch64_SQRDMLAH_ZZZI_S 4417 +#define AArch64_SQRDMLAH_ZZZ_B 4418 +#define AArch64_SQRDMLAH_ZZZ_D 4419 +#define AArch64_SQRDMLAH_ZZZ_H 4420 +#define AArch64_SQRDMLAH_ZZZ_S 4421 +#define AArch64_SQRDMLAHi16_indexed 4422 +#define AArch64_SQRDMLAHi32_indexed 4423 +#define AArch64_SQRDMLAHv1i16 4424 +#define AArch64_SQRDMLAHv1i32 4425 +#define AArch64_SQRDMLAHv2i32 4426 +#define AArch64_SQRDMLAHv2i32_indexed 4427 +#define AArch64_SQRDMLAHv4i16 4428 +#define AArch64_SQRDMLAHv4i16_indexed 4429 +#define AArch64_SQRDMLAHv4i32 4430 +#define AArch64_SQRDMLAHv4i32_indexed 4431 +#define AArch64_SQRDMLAHv8i16 4432 +#define AArch64_SQRDMLAHv8i16_indexed 4433 +#define AArch64_SQRDMLSH_ZZZI_D 4434 +#define AArch64_SQRDMLSH_ZZZI_H 4435 +#define AArch64_SQRDMLSH_ZZZI_S 4436 +#define AArch64_SQRDMLSH_ZZZ_B 4437 +#define AArch64_SQRDMLSH_ZZZ_D 4438 +#define AArch64_SQRDMLSH_ZZZ_H 4439 +#define AArch64_SQRDMLSH_ZZZ_S 4440 +#define AArch64_SQRDMLSHi16_indexed 4441 +#define AArch64_SQRDMLSHi32_indexed 4442 +#define AArch64_SQRDMLSHv1i16 4443 +#define AArch64_SQRDMLSHv1i32 4444 +#define AArch64_SQRDMLSHv2i32 4445 +#define AArch64_SQRDMLSHv2i32_indexed 4446 +#define AArch64_SQRDMLSHv4i16 4447 +#define AArch64_SQRDMLSHv4i16_indexed 4448 +#define AArch64_SQRDMLSHv4i32 4449 +#define AArch64_SQRDMLSHv4i32_indexed 4450 +#define AArch64_SQRDMLSHv8i16 4451 +#define AArch64_SQRDMLSHv8i16_indexed 4452 +#define AArch64_SQRDMULH_ZZZI_D 4453 +#define AArch64_SQRDMULH_ZZZI_H 4454 +#define AArch64_SQRDMULH_ZZZI_S 4455 +#define AArch64_SQRDMULH_ZZZ_B 4456 +#define AArch64_SQRDMULH_ZZZ_D 4457 +#define AArch64_SQRDMULH_ZZZ_H 4458 +#define AArch64_SQRDMULH_ZZZ_S 4459 +#define AArch64_SQRDMULHv1i16 4460 +#define AArch64_SQRDMULHv1i16_indexed 4461 +#define AArch64_SQRDMULHv1i32 4462 +#define AArch64_SQRDMULHv1i32_indexed 4463 +#define AArch64_SQRDMULHv2i32 4464 +#define AArch64_SQRDMULHv2i32_indexed 4465 +#define AArch64_SQRDMULHv4i16 4466 +#define AArch64_SQRDMULHv4i16_indexed 4467 +#define AArch64_SQRDMULHv4i32 4468 +#define AArch64_SQRDMULHv4i32_indexed 4469 +#define AArch64_SQRDMULHv8i16 4470 +#define AArch64_SQRDMULHv8i16_indexed 4471 +#define AArch64_SQRSHLR_ZPmZ_B 4472 +#define AArch64_SQRSHLR_ZPmZ_D 4473 +#define AArch64_SQRSHLR_ZPmZ_H 4474 +#define AArch64_SQRSHLR_ZPmZ_S 4475 +#define AArch64_SQRSHL_ZPmZ_B 4476 +#define AArch64_SQRSHL_ZPmZ_D 4477 +#define AArch64_SQRSHL_ZPmZ_H 4478 +#define AArch64_SQRSHL_ZPmZ_S 4479 +#define AArch64_SQRSHLv16i8 4480 +#define AArch64_SQRSHLv1i16 4481 +#define AArch64_SQRSHLv1i32 4482 +#define AArch64_SQRSHLv1i64 4483 +#define AArch64_SQRSHLv1i8 4484 +#define AArch64_SQRSHLv2i32 4485 +#define AArch64_SQRSHLv2i64 4486 +#define AArch64_SQRSHLv4i16 4487 +#define AArch64_SQRSHLv4i32 4488 +#define AArch64_SQRSHLv8i16 4489 +#define AArch64_SQRSHLv8i8 4490 +#define AArch64_SQRSHRNB_ZZI_B 4491 +#define AArch64_SQRSHRNB_ZZI_H 4492 +#define AArch64_SQRSHRNB_ZZI_S 4493 +#define AArch64_SQRSHRNT_ZZI_B 4494 +#define AArch64_SQRSHRNT_ZZI_H 4495 +#define AArch64_SQRSHRNT_ZZI_S 4496 +#define AArch64_SQRSHRNb 4497 +#define AArch64_SQRSHRNh 4498 +#define AArch64_SQRSHRNs 4499 +#define AArch64_SQRSHRNv16i8_shift 4500 +#define AArch64_SQRSHRNv2i32_shift 4501 +#define AArch64_SQRSHRNv4i16_shift 4502 +#define AArch64_SQRSHRNv4i32_shift 4503 +#define AArch64_SQRSHRNv8i16_shift 4504 +#define AArch64_SQRSHRNv8i8_shift 4505 +#define AArch64_SQRSHRUNB_ZZI_B 4506 +#define AArch64_SQRSHRUNB_ZZI_H 4507 +#define AArch64_SQRSHRUNB_ZZI_S 4508 +#define AArch64_SQRSHRUNT_ZZI_B 4509 +#define AArch64_SQRSHRUNT_ZZI_H 4510 +#define AArch64_SQRSHRUNT_ZZI_S 4511 +#define AArch64_SQRSHRUNb 4512 +#define AArch64_SQRSHRUNh 4513 +#define AArch64_SQRSHRUNs 4514 +#define AArch64_SQRSHRUNv16i8_shift 4515 +#define AArch64_SQRSHRUNv2i32_shift 4516 +#define AArch64_SQRSHRUNv4i16_shift 4517 +#define AArch64_SQRSHRUNv4i32_shift 4518 +#define AArch64_SQRSHRUNv8i16_shift 4519 +#define AArch64_SQRSHRUNv8i8_shift 4520 +#define AArch64_SQSHLR_ZPmZ_B 4521 +#define AArch64_SQSHLR_ZPmZ_D 4522 +#define AArch64_SQSHLR_ZPmZ_H 4523 +#define AArch64_SQSHLR_ZPmZ_S 4524 +#define AArch64_SQSHLU_ZPmI_B 4525 +#define AArch64_SQSHLU_ZPmI_D 4526 +#define AArch64_SQSHLU_ZPmI_H 4527 +#define AArch64_SQSHLU_ZPmI_S 4528 +#define AArch64_SQSHLUb 4529 +#define AArch64_SQSHLUd 4530 +#define AArch64_SQSHLUh 4531 +#define AArch64_SQSHLUs 4532 +#define AArch64_SQSHLUv16i8_shift 4533 +#define AArch64_SQSHLUv2i32_shift 4534 +#define AArch64_SQSHLUv2i64_shift 4535 +#define AArch64_SQSHLUv4i16_shift 4536 +#define AArch64_SQSHLUv4i32_shift 4537 +#define AArch64_SQSHLUv8i16_shift 4538 +#define AArch64_SQSHLUv8i8_shift 4539 +#define AArch64_SQSHL_ZPmI_B 4540 +#define AArch64_SQSHL_ZPmI_D 4541 +#define AArch64_SQSHL_ZPmI_H 4542 +#define AArch64_SQSHL_ZPmI_S 4543 +#define AArch64_SQSHL_ZPmZ_B 4544 +#define AArch64_SQSHL_ZPmZ_D 4545 +#define AArch64_SQSHL_ZPmZ_H 4546 +#define AArch64_SQSHL_ZPmZ_S 4547 +#define AArch64_SQSHLb 4548 +#define AArch64_SQSHLd 4549 +#define AArch64_SQSHLh 4550 +#define AArch64_SQSHLs 4551 +#define AArch64_SQSHLv16i8 4552 +#define AArch64_SQSHLv16i8_shift 4553 +#define AArch64_SQSHLv1i16 4554 +#define AArch64_SQSHLv1i32 4555 +#define AArch64_SQSHLv1i64 4556 +#define AArch64_SQSHLv1i8 4557 +#define AArch64_SQSHLv2i32 4558 +#define AArch64_SQSHLv2i32_shift 4559 +#define AArch64_SQSHLv2i64 4560 +#define AArch64_SQSHLv2i64_shift 4561 +#define AArch64_SQSHLv4i16 4562 +#define AArch64_SQSHLv4i16_shift 4563 +#define AArch64_SQSHLv4i32 4564 +#define AArch64_SQSHLv4i32_shift 4565 +#define AArch64_SQSHLv8i16 4566 +#define AArch64_SQSHLv8i16_shift 4567 +#define AArch64_SQSHLv8i8 4568 +#define AArch64_SQSHLv8i8_shift 4569 +#define AArch64_SQSHRNB_ZZI_B 4570 +#define AArch64_SQSHRNB_ZZI_H 4571 +#define AArch64_SQSHRNB_ZZI_S 4572 +#define AArch64_SQSHRNT_ZZI_B 4573 +#define AArch64_SQSHRNT_ZZI_H 4574 +#define AArch64_SQSHRNT_ZZI_S 4575 +#define AArch64_SQSHRNb 4576 +#define AArch64_SQSHRNh 4577 +#define AArch64_SQSHRNs 4578 +#define AArch64_SQSHRNv16i8_shift 4579 +#define AArch64_SQSHRNv2i32_shift 4580 +#define AArch64_SQSHRNv4i16_shift 4581 +#define AArch64_SQSHRNv4i32_shift 4582 +#define AArch64_SQSHRNv8i16_shift 4583 +#define AArch64_SQSHRNv8i8_shift 4584 +#define AArch64_SQSHRUNB_ZZI_B 4585 +#define AArch64_SQSHRUNB_ZZI_H 4586 +#define AArch64_SQSHRUNB_ZZI_S 4587 +#define AArch64_SQSHRUNT_ZZI_B 4588 +#define AArch64_SQSHRUNT_ZZI_H 4589 +#define AArch64_SQSHRUNT_ZZI_S 4590 +#define AArch64_SQSHRUNb 4591 +#define AArch64_SQSHRUNh 4592 +#define AArch64_SQSHRUNs 4593 +#define AArch64_SQSHRUNv16i8_shift 4594 +#define AArch64_SQSHRUNv2i32_shift 4595 +#define AArch64_SQSHRUNv4i16_shift 4596 +#define AArch64_SQSHRUNv4i32_shift 4597 +#define AArch64_SQSHRUNv8i16_shift 4598 +#define AArch64_SQSHRUNv8i8_shift 4599 +#define AArch64_SQSUBR_ZPmZ_B 4600 +#define AArch64_SQSUBR_ZPmZ_D 4601 +#define AArch64_SQSUBR_ZPmZ_H 4602 +#define AArch64_SQSUBR_ZPmZ_S 4603 +#define AArch64_SQSUB_ZI_B 4604 +#define AArch64_SQSUB_ZI_D 4605 +#define AArch64_SQSUB_ZI_H 4606 +#define AArch64_SQSUB_ZI_S 4607 +#define AArch64_SQSUB_ZPmZ_B 4608 +#define AArch64_SQSUB_ZPmZ_D 4609 +#define AArch64_SQSUB_ZPmZ_H 4610 +#define AArch64_SQSUB_ZPmZ_S 4611 +#define AArch64_SQSUB_ZZZ_B 4612 +#define AArch64_SQSUB_ZZZ_D 4613 +#define AArch64_SQSUB_ZZZ_H 4614 +#define AArch64_SQSUB_ZZZ_S 4615 +#define AArch64_SQSUBv16i8 4616 +#define AArch64_SQSUBv1i16 4617 +#define AArch64_SQSUBv1i32 4618 +#define AArch64_SQSUBv1i64 4619 +#define AArch64_SQSUBv1i8 4620 +#define AArch64_SQSUBv2i32 4621 +#define AArch64_SQSUBv2i64 4622 +#define AArch64_SQSUBv4i16 4623 +#define AArch64_SQSUBv4i32 4624 +#define AArch64_SQSUBv8i16 4625 +#define AArch64_SQSUBv8i8 4626 +#define AArch64_SQXTNB_ZZ_B 4627 +#define AArch64_SQXTNB_ZZ_H 4628 +#define AArch64_SQXTNB_ZZ_S 4629 +#define AArch64_SQXTNT_ZZ_B 4630 +#define AArch64_SQXTNT_ZZ_H 4631 +#define AArch64_SQXTNT_ZZ_S 4632 +#define AArch64_SQXTNv16i8 4633 +#define AArch64_SQXTNv1i16 4634 +#define AArch64_SQXTNv1i32 4635 +#define AArch64_SQXTNv1i8 4636 +#define AArch64_SQXTNv2i32 4637 +#define AArch64_SQXTNv4i16 4638 +#define AArch64_SQXTNv4i32 4639 +#define AArch64_SQXTNv8i16 4640 +#define AArch64_SQXTNv8i8 4641 +#define AArch64_SQXTUNB_ZZ_B 4642 +#define AArch64_SQXTUNB_ZZ_H 4643 +#define AArch64_SQXTUNB_ZZ_S 4644 +#define AArch64_SQXTUNT_ZZ_B 4645 +#define AArch64_SQXTUNT_ZZ_H 4646 +#define AArch64_SQXTUNT_ZZ_S 4647 +#define AArch64_SQXTUNv16i8 4648 +#define AArch64_SQXTUNv1i16 4649 +#define AArch64_SQXTUNv1i32 4650 +#define AArch64_SQXTUNv1i8 4651 +#define AArch64_SQXTUNv2i32 4652 +#define AArch64_SQXTUNv4i16 4653 +#define AArch64_SQXTUNv4i32 4654 +#define AArch64_SQXTUNv8i16 4655 +#define AArch64_SQXTUNv8i8 4656 +#define AArch64_SRHADD_ZPmZ_B 4657 +#define AArch64_SRHADD_ZPmZ_D 4658 +#define AArch64_SRHADD_ZPmZ_H 4659 +#define AArch64_SRHADD_ZPmZ_S 4660 +#define AArch64_SRHADDv16i8 4661 +#define AArch64_SRHADDv2i32 4662 +#define AArch64_SRHADDv4i16 4663 +#define AArch64_SRHADDv4i32 4664 +#define AArch64_SRHADDv8i16 4665 +#define AArch64_SRHADDv8i8 4666 +#define AArch64_SRI_ZZI_B 4667 +#define AArch64_SRI_ZZI_D 4668 +#define AArch64_SRI_ZZI_H 4669 +#define AArch64_SRI_ZZI_S 4670 +#define AArch64_SRId 4671 +#define AArch64_SRIv16i8_shift 4672 +#define AArch64_SRIv2i32_shift 4673 +#define AArch64_SRIv2i64_shift 4674 +#define AArch64_SRIv4i16_shift 4675 +#define AArch64_SRIv4i32_shift 4676 +#define AArch64_SRIv8i16_shift 4677 +#define AArch64_SRIv8i8_shift 4678 +#define AArch64_SRSHLR_ZPmZ_B 4679 +#define AArch64_SRSHLR_ZPmZ_D 4680 +#define AArch64_SRSHLR_ZPmZ_H 4681 +#define AArch64_SRSHLR_ZPmZ_S 4682 +#define AArch64_SRSHL_ZPmZ_B 4683 +#define AArch64_SRSHL_ZPmZ_D 4684 +#define AArch64_SRSHL_ZPmZ_H 4685 +#define AArch64_SRSHL_ZPmZ_S 4686 +#define AArch64_SRSHLv16i8 4687 +#define AArch64_SRSHLv1i64 4688 +#define AArch64_SRSHLv2i32 4689 +#define AArch64_SRSHLv2i64 4690 +#define AArch64_SRSHLv4i16 4691 +#define AArch64_SRSHLv4i32 4692 +#define AArch64_SRSHLv8i16 4693 +#define AArch64_SRSHLv8i8 4694 +#define AArch64_SRSHR_ZPmI_B 4695 +#define AArch64_SRSHR_ZPmI_D 4696 +#define AArch64_SRSHR_ZPmI_H 4697 +#define AArch64_SRSHR_ZPmI_S 4698 +#define AArch64_SRSHRd 4699 +#define AArch64_SRSHRv16i8_shift 4700 +#define AArch64_SRSHRv2i32_shift 4701 +#define AArch64_SRSHRv2i64_shift 4702 +#define AArch64_SRSHRv4i16_shift 4703 +#define AArch64_SRSHRv4i32_shift 4704 +#define AArch64_SRSHRv8i16_shift 4705 +#define AArch64_SRSHRv8i8_shift 4706 +#define AArch64_SRSRA_ZZI_B 4707 +#define AArch64_SRSRA_ZZI_D 4708 +#define AArch64_SRSRA_ZZI_H 4709 +#define AArch64_SRSRA_ZZI_S 4710 +#define AArch64_SRSRAd 4711 +#define AArch64_SRSRAv16i8_shift 4712 +#define AArch64_SRSRAv2i32_shift 4713 +#define AArch64_SRSRAv2i64_shift 4714 +#define AArch64_SRSRAv4i16_shift 4715 +#define AArch64_SRSRAv4i32_shift 4716 +#define AArch64_SRSRAv8i16_shift 4717 +#define AArch64_SRSRAv8i8_shift 4718 +#define AArch64_SSHLLB_ZZI_D 4719 +#define AArch64_SSHLLB_ZZI_H 4720 +#define AArch64_SSHLLB_ZZI_S 4721 +#define AArch64_SSHLLT_ZZI_D 4722 +#define AArch64_SSHLLT_ZZI_H 4723 +#define AArch64_SSHLLT_ZZI_S 4724 +#define AArch64_SSHLLv16i8_shift 4725 +#define AArch64_SSHLLv2i32_shift 4726 +#define AArch64_SSHLLv4i16_shift 4727 +#define AArch64_SSHLLv4i32_shift 4728 +#define AArch64_SSHLLv8i16_shift 4729 +#define AArch64_SSHLLv8i8_shift 4730 +#define AArch64_SSHLv16i8 4731 +#define AArch64_SSHLv1i64 4732 +#define AArch64_SSHLv2i32 4733 +#define AArch64_SSHLv2i64 4734 +#define AArch64_SSHLv4i16 4735 +#define AArch64_SSHLv4i32 4736 +#define AArch64_SSHLv8i16 4737 +#define AArch64_SSHLv8i8 4738 +#define AArch64_SSHRd 4739 +#define AArch64_SSHRv16i8_shift 4740 +#define AArch64_SSHRv2i32_shift 4741 +#define AArch64_SSHRv2i64_shift 4742 +#define AArch64_SSHRv4i16_shift 4743 +#define AArch64_SSHRv4i32_shift 4744 +#define AArch64_SSHRv8i16_shift 4745 +#define AArch64_SSHRv8i8_shift 4746 +#define AArch64_SSRA_ZZI_B 4747 +#define AArch64_SSRA_ZZI_D 4748 +#define AArch64_SSRA_ZZI_H 4749 +#define AArch64_SSRA_ZZI_S 4750 +#define AArch64_SSRAd 4751 +#define AArch64_SSRAv16i8_shift 4752 +#define AArch64_SSRAv2i32_shift 4753 +#define AArch64_SSRAv2i64_shift 4754 +#define AArch64_SSRAv4i16_shift 4755 +#define AArch64_SSRAv4i32_shift 4756 +#define AArch64_SSRAv8i16_shift 4757 +#define AArch64_SSRAv8i8_shift 4758 +#define AArch64_SST1B_D_IMM 4759 +#define AArch64_SST1B_D_REAL 4760 +#define AArch64_SST1B_D_SXTW 4761 +#define AArch64_SST1B_D_UXTW 4762 +#define AArch64_SST1B_S_IMM 4763 +#define AArch64_SST1B_S_SXTW 4764 +#define AArch64_SST1B_S_UXTW 4765 +#define AArch64_SST1D_IMM 4766 +#define AArch64_SST1D_REAL 4767 +#define AArch64_SST1D_SCALED_SCALED_REAL 4768 +#define AArch64_SST1D_SXTW 4769 +#define AArch64_SST1D_SXTW_SCALED 4770 +#define AArch64_SST1D_UXTW 4771 +#define AArch64_SST1D_UXTW_SCALED 4772 +#define AArch64_SST1H_D_IMM 4773 +#define AArch64_SST1H_D_REAL 4774 +#define AArch64_SST1H_D_SCALED_SCALED_REAL 4775 +#define AArch64_SST1H_D_SXTW 4776 +#define AArch64_SST1H_D_SXTW_SCALED 4777 +#define AArch64_SST1H_D_UXTW 4778 +#define AArch64_SST1H_D_UXTW_SCALED 4779 +#define AArch64_SST1H_S_IMM 4780 +#define AArch64_SST1H_S_SXTW 4781 +#define AArch64_SST1H_S_SXTW_SCALED 4782 +#define AArch64_SST1H_S_UXTW 4783 +#define AArch64_SST1H_S_UXTW_SCALED 4784 +#define AArch64_SST1W_D_IMM 4785 +#define AArch64_SST1W_D_REAL 4786 +#define AArch64_SST1W_D_SCALED_SCALED_REAL 4787 +#define AArch64_SST1W_D_SXTW 4788 +#define AArch64_SST1W_D_SXTW_SCALED 4789 +#define AArch64_SST1W_D_UXTW 4790 +#define AArch64_SST1W_D_UXTW_SCALED 4791 +#define AArch64_SST1W_IMM 4792 +#define AArch64_SST1W_SXTW 4793 +#define AArch64_SST1W_SXTW_SCALED 4794 +#define AArch64_SST1W_UXTW 4795 +#define AArch64_SST1W_UXTW_SCALED 4796 +#define AArch64_SSUBLBT_ZZZ_D 4797 +#define AArch64_SSUBLBT_ZZZ_H 4798 +#define AArch64_SSUBLBT_ZZZ_S 4799 +#define AArch64_SSUBLB_ZZZ_D 4800 +#define AArch64_SSUBLB_ZZZ_H 4801 +#define AArch64_SSUBLB_ZZZ_S 4802 +#define AArch64_SSUBLTB_ZZZ_D 4803 +#define AArch64_SSUBLTB_ZZZ_H 4804 +#define AArch64_SSUBLTB_ZZZ_S 4805 +#define AArch64_SSUBLT_ZZZ_D 4806 +#define AArch64_SSUBLT_ZZZ_H 4807 +#define AArch64_SSUBLT_ZZZ_S 4808 +#define AArch64_SSUBLv16i8_v8i16 4809 +#define AArch64_SSUBLv2i32_v2i64 4810 +#define AArch64_SSUBLv4i16_v4i32 4811 +#define AArch64_SSUBLv4i32_v2i64 4812 +#define AArch64_SSUBLv8i16_v4i32 4813 +#define AArch64_SSUBLv8i8_v8i16 4814 +#define AArch64_SSUBWB_ZZZ_D 4815 +#define AArch64_SSUBWB_ZZZ_H 4816 +#define AArch64_SSUBWB_ZZZ_S 4817 +#define AArch64_SSUBWT_ZZZ_D 4818 +#define AArch64_SSUBWT_ZZZ_H 4819 +#define AArch64_SSUBWT_ZZZ_S 4820 +#define AArch64_SSUBWv16i8_v8i16 4821 +#define AArch64_SSUBWv2i32_v2i64 4822 +#define AArch64_SSUBWv4i16_v4i32 4823 +#define AArch64_SSUBWv4i32_v2i64 4824 +#define AArch64_SSUBWv8i16_v4i32 4825 +#define AArch64_SSUBWv8i8_v8i16 4826 +#define AArch64_ST1B 4827 +#define AArch64_ST1B_D 4828 +#define AArch64_ST1B_D_IMM 4829 +#define AArch64_ST1B_H 4830 +#define AArch64_ST1B_H_IMM 4831 +#define AArch64_ST1B_IMM 4832 +#define AArch64_ST1B_S 4833 +#define AArch64_ST1B_S_IMM 4834 +#define AArch64_ST1D 4835 +#define AArch64_ST1D_IMM 4836 +#define AArch64_ST1Fourv16b 4837 +#define AArch64_ST1Fourv16b_POST 4838 +#define AArch64_ST1Fourv1d 4839 +#define AArch64_ST1Fourv1d_POST 4840 +#define AArch64_ST1Fourv2d 4841 +#define AArch64_ST1Fourv2d_POST 4842 +#define AArch64_ST1Fourv2s 4843 +#define AArch64_ST1Fourv2s_POST 4844 +#define AArch64_ST1Fourv4h 4845 +#define AArch64_ST1Fourv4h_POST 4846 +#define AArch64_ST1Fourv4s 4847 +#define AArch64_ST1Fourv4s_POST 4848 +#define AArch64_ST1Fourv8b 4849 +#define AArch64_ST1Fourv8b_POST 4850 +#define AArch64_ST1Fourv8h 4851 +#define AArch64_ST1Fourv8h_POST 4852 +#define AArch64_ST1H 4853 +#define AArch64_ST1H_D 4854 +#define AArch64_ST1H_D_IMM 4855 +#define AArch64_ST1H_IMM 4856 +#define AArch64_ST1H_S 4857 +#define AArch64_ST1H_S_IMM 4858 +#define AArch64_ST1Onev16b 4859 +#define AArch64_ST1Onev16b_POST 4860 +#define AArch64_ST1Onev1d 4861 +#define AArch64_ST1Onev1d_POST 4862 +#define AArch64_ST1Onev2d 4863 +#define AArch64_ST1Onev2d_POST 4864 +#define AArch64_ST1Onev2s 4865 +#define AArch64_ST1Onev2s_POST 4866 +#define AArch64_ST1Onev4h 4867 +#define AArch64_ST1Onev4h_POST 4868 +#define AArch64_ST1Onev4s 4869 +#define AArch64_ST1Onev4s_POST 4870 +#define AArch64_ST1Onev8b 4871 +#define AArch64_ST1Onev8b_POST 4872 +#define AArch64_ST1Onev8h 4873 +#define AArch64_ST1Onev8h_POST 4874 +#define AArch64_ST1Threev16b 4875 +#define AArch64_ST1Threev16b_POST 4876 +#define AArch64_ST1Threev1d 4877 +#define AArch64_ST1Threev1d_POST 4878 +#define AArch64_ST1Threev2d 4879 +#define AArch64_ST1Threev2d_POST 4880 +#define AArch64_ST1Threev2s 4881 +#define AArch64_ST1Threev2s_POST 4882 +#define AArch64_ST1Threev4h 4883 +#define AArch64_ST1Threev4h_POST 4884 +#define AArch64_ST1Threev4s 4885 +#define AArch64_ST1Threev4s_POST 4886 +#define AArch64_ST1Threev8b 4887 +#define AArch64_ST1Threev8b_POST 4888 +#define AArch64_ST1Threev8h 4889 +#define AArch64_ST1Threev8h_POST 4890 +#define AArch64_ST1Twov16b 4891 +#define AArch64_ST1Twov16b_POST 4892 +#define AArch64_ST1Twov1d 4893 +#define AArch64_ST1Twov1d_POST 4894 +#define AArch64_ST1Twov2d 4895 +#define AArch64_ST1Twov2d_POST 4896 +#define AArch64_ST1Twov2s 4897 +#define AArch64_ST1Twov2s_POST 4898 +#define AArch64_ST1Twov4h 4899 +#define AArch64_ST1Twov4h_POST 4900 +#define AArch64_ST1Twov4s 4901 +#define AArch64_ST1Twov4s_POST 4902 +#define AArch64_ST1Twov8b 4903 +#define AArch64_ST1Twov8b_POST 4904 +#define AArch64_ST1Twov8h 4905 +#define AArch64_ST1Twov8h_POST 4906 +#define AArch64_ST1W 4907 +#define AArch64_ST1W_D 4908 +#define AArch64_ST1W_D_IMM 4909 +#define AArch64_ST1W_IMM 4910 +#define AArch64_ST1_MXIPXX_H_B 4911 +#define AArch64_ST1_MXIPXX_H_D 4912 +#define AArch64_ST1_MXIPXX_H_H 4913 +#define AArch64_ST1_MXIPXX_H_Q 4914 +#define AArch64_ST1_MXIPXX_H_S 4915 +#define AArch64_ST1_MXIPXX_V_B 4916 +#define AArch64_ST1_MXIPXX_V_D 4917 +#define AArch64_ST1_MXIPXX_V_H 4918 +#define AArch64_ST1_MXIPXX_V_Q 4919 +#define AArch64_ST1_MXIPXX_V_S 4920 +#define AArch64_ST1i16 4921 +#define AArch64_ST1i16_POST 4922 +#define AArch64_ST1i32 4923 +#define AArch64_ST1i32_POST 4924 +#define AArch64_ST1i64 4925 +#define AArch64_ST1i64_POST 4926 +#define AArch64_ST1i8 4927 +#define AArch64_ST1i8_POST 4928 +#define AArch64_ST2B 4929 +#define AArch64_ST2B_IMM 4930 +#define AArch64_ST2D 4931 +#define AArch64_ST2D_IMM 4932 +#define AArch64_ST2GOffset 4933 +#define AArch64_ST2GPostIndex 4934 +#define AArch64_ST2GPreIndex 4935 +#define AArch64_ST2H 4936 +#define AArch64_ST2H_IMM 4937 +#define AArch64_ST2Twov16b 4938 +#define AArch64_ST2Twov16b_POST 4939 +#define AArch64_ST2Twov2d 4940 +#define AArch64_ST2Twov2d_POST 4941 +#define AArch64_ST2Twov2s 4942 +#define AArch64_ST2Twov2s_POST 4943 +#define AArch64_ST2Twov4h 4944 +#define AArch64_ST2Twov4h_POST 4945 +#define AArch64_ST2Twov4s 4946 +#define AArch64_ST2Twov4s_POST 4947 +#define AArch64_ST2Twov8b 4948 +#define AArch64_ST2Twov8b_POST 4949 +#define AArch64_ST2Twov8h 4950 +#define AArch64_ST2Twov8h_POST 4951 +#define AArch64_ST2W 4952 +#define AArch64_ST2W_IMM 4953 +#define AArch64_ST2i16 4954 +#define AArch64_ST2i16_POST 4955 +#define AArch64_ST2i32 4956 +#define AArch64_ST2i32_POST 4957 +#define AArch64_ST2i64 4958 +#define AArch64_ST2i64_POST 4959 +#define AArch64_ST2i8 4960 +#define AArch64_ST2i8_POST 4961 +#define AArch64_ST3B 4962 +#define AArch64_ST3B_IMM 4963 +#define AArch64_ST3D 4964 +#define AArch64_ST3D_IMM 4965 +#define AArch64_ST3H 4966 +#define AArch64_ST3H_IMM 4967 +#define AArch64_ST3Threev16b 4968 +#define AArch64_ST3Threev16b_POST 4969 +#define AArch64_ST3Threev2d 4970 +#define AArch64_ST3Threev2d_POST 4971 +#define AArch64_ST3Threev2s 4972 +#define AArch64_ST3Threev2s_POST 4973 +#define AArch64_ST3Threev4h 4974 +#define AArch64_ST3Threev4h_POST 4975 +#define AArch64_ST3Threev4s 4976 +#define AArch64_ST3Threev4s_POST 4977 +#define AArch64_ST3Threev8b 4978 +#define AArch64_ST3Threev8b_POST 4979 +#define AArch64_ST3Threev8h 4980 +#define AArch64_ST3Threev8h_POST 4981 +#define AArch64_ST3W 4982 +#define AArch64_ST3W_IMM 4983 +#define AArch64_ST3i16 4984 +#define AArch64_ST3i16_POST 4985 +#define AArch64_ST3i32 4986 +#define AArch64_ST3i32_POST 4987 +#define AArch64_ST3i64 4988 +#define AArch64_ST3i64_POST 4989 +#define AArch64_ST3i8 4990 +#define AArch64_ST3i8_POST 4991 +#define AArch64_ST4B 4992 +#define AArch64_ST4B_IMM 4993 +#define AArch64_ST4D 4994 +#define AArch64_ST4D_IMM 4995 +#define AArch64_ST4Fourv16b 4996 +#define AArch64_ST4Fourv16b_POST 4997 +#define AArch64_ST4Fourv2d 4998 +#define AArch64_ST4Fourv2d_POST 4999 +#define AArch64_ST4Fourv2s 5000 +#define AArch64_ST4Fourv2s_POST 5001 +#define AArch64_ST4Fourv4h 5002 +#define AArch64_ST4Fourv4h_POST 5003 +#define AArch64_ST4Fourv4s 5004 +#define AArch64_ST4Fourv4s_POST 5005 +#define AArch64_ST4Fourv8b 5006 +#define AArch64_ST4Fourv8b_POST 5007 +#define AArch64_ST4Fourv8h 5008 +#define AArch64_ST4Fourv8h_POST 5009 +#define AArch64_ST4H 5010 +#define AArch64_ST4H_IMM 5011 +#define AArch64_ST4W 5012 +#define AArch64_ST4W_IMM 5013 +#define AArch64_ST4i16 5014 +#define AArch64_ST4i16_POST 5015 +#define AArch64_ST4i32 5016 +#define AArch64_ST4i32_POST 5017 +#define AArch64_ST4i64 5018 +#define AArch64_ST4i64_POST 5019 +#define AArch64_ST4i8 5020 +#define AArch64_ST4i8_POST 5021 +#define AArch64_ST64B 5022 +#define AArch64_ST64BV 5023 +#define AArch64_ST64BV0 5024 +#define AArch64_STGM 5025 +#define AArch64_STGOffset 5026 +#define AArch64_STGPi 5027 +#define AArch64_STGPostIndex 5028 +#define AArch64_STGPpost 5029 +#define AArch64_STGPpre 5030 +#define AArch64_STGPreIndex 5031 +#define AArch64_STLLRB 5032 +#define AArch64_STLLRH 5033 +#define AArch64_STLLRW 5034 +#define AArch64_STLLRX 5035 +#define AArch64_STLRB 5036 +#define AArch64_STLRH 5037 +#define AArch64_STLRW 5038 +#define AArch64_STLRX 5039 +#define AArch64_STLURBi 5040 +#define AArch64_STLURHi 5041 +#define AArch64_STLURWi 5042 +#define AArch64_STLURXi 5043 +#define AArch64_STLXPW 5044 +#define AArch64_STLXPX 5045 +#define AArch64_STLXRB 5046 +#define AArch64_STLXRH 5047 +#define AArch64_STLXRW 5048 +#define AArch64_STLXRX 5049 +#define AArch64_STNPDi 5050 +#define AArch64_STNPQi 5051 +#define AArch64_STNPSi 5052 +#define AArch64_STNPWi 5053 +#define AArch64_STNPXi 5054 +#define AArch64_STNT1B_ZRI 5055 +#define AArch64_STNT1B_ZRR 5056 +#define AArch64_STNT1B_ZZR_D_REAL 5057 +#define AArch64_STNT1B_ZZR_S_REAL 5058 +#define AArch64_STNT1D_ZRI 5059 +#define AArch64_STNT1D_ZRR 5060 +#define AArch64_STNT1D_ZZR_D_REAL 5061 +#define AArch64_STNT1H_ZRI 5062 +#define AArch64_STNT1H_ZRR 5063 +#define AArch64_STNT1H_ZZR_D_REAL 5064 +#define AArch64_STNT1H_ZZR_S_REAL 5065 +#define AArch64_STNT1W_ZRI 5066 +#define AArch64_STNT1W_ZRR 5067 +#define AArch64_STNT1W_ZZR_D_REAL 5068 +#define AArch64_STNT1W_ZZR_S_REAL 5069 +#define AArch64_STPDi 5070 +#define AArch64_STPDpost 5071 +#define AArch64_STPDpre 5072 +#define AArch64_STPQi 5073 +#define AArch64_STPQpost 5074 +#define AArch64_STPQpre 5075 +#define AArch64_STPSi 5076 +#define AArch64_STPSpost 5077 +#define AArch64_STPSpre 5078 +#define AArch64_STPWi 5079 +#define AArch64_STPWpost 5080 +#define AArch64_STPWpre 5081 +#define AArch64_STPXi 5082 +#define AArch64_STPXpost 5083 +#define AArch64_STPXpre 5084 +#define AArch64_STRBBpost 5085 +#define AArch64_STRBBpre 5086 +#define AArch64_STRBBroW 5087 +#define AArch64_STRBBroX 5088 +#define AArch64_STRBBui 5089 +#define AArch64_STRBpost 5090 +#define AArch64_STRBpre 5091 +#define AArch64_STRBroW 5092 +#define AArch64_STRBroX 5093 +#define AArch64_STRBui 5094 +#define AArch64_STRDpost 5095 +#define AArch64_STRDpre 5096 +#define AArch64_STRDroW 5097 +#define AArch64_STRDroX 5098 +#define AArch64_STRDui 5099 +#define AArch64_STRHHpost 5100 +#define AArch64_STRHHpre 5101 +#define AArch64_STRHHroW 5102 +#define AArch64_STRHHroX 5103 +#define AArch64_STRHHui 5104 +#define AArch64_STRHpost 5105 +#define AArch64_STRHpre 5106 +#define AArch64_STRHroW 5107 +#define AArch64_STRHroX 5108 +#define AArch64_STRHui 5109 +#define AArch64_STRQpost 5110 +#define AArch64_STRQpre 5111 +#define AArch64_STRQroW 5112 +#define AArch64_STRQroX 5113 +#define AArch64_STRQui 5114 +#define AArch64_STRSpost 5115 +#define AArch64_STRSpre 5116 +#define AArch64_STRSroW 5117 +#define AArch64_STRSroX 5118 +#define AArch64_STRSui 5119 +#define AArch64_STRWpost 5120 +#define AArch64_STRWpre 5121 +#define AArch64_STRWroW 5122 +#define AArch64_STRWroX 5123 +#define AArch64_STRWui 5124 +#define AArch64_STRXpost 5125 +#define AArch64_STRXpre 5126 +#define AArch64_STRXroW 5127 +#define AArch64_STRXroX 5128 +#define AArch64_STRXui 5129 +#define AArch64_STR_PXI 5130 +#define AArch64_STR_ZA 5131 +#define AArch64_STR_ZXI 5132 +#define AArch64_STTRBi 5133 +#define AArch64_STTRHi 5134 +#define AArch64_STTRWi 5135 +#define AArch64_STTRXi 5136 +#define AArch64_STURBBi 5137 +#define AArch64_STURBi 5138 +#define AArch64_STURDi 5139 +#define AArch64_STURHHi 5140 +#define AArch64_STURHi 5141 +#define AArch64_STURQi 5142 +#define AArch64_STURSi 5143 +#define AArch64_STURWi 5144 +#define AArch64_STURXi 5145 +#define AArch64_STXPW 5146 +#define AArch64_STXPX 5147 +#define AArch64_STXRB 5148 +#define AArch64_STXRH 5149 +#define AArch64_STXRW 5150 +#define AArch64_STXRX 5151 +#define AArch64_STZ2GOffset 5152 +#define AArch64_STZ2GPostIndex 5153 +#define AArch64_STZ2GPreIndex 5154 +#define AArch64_STZGM 5155 +#define AArch64_STZGOffset 5156 +#define AArch64_STZGPostIndex 5157 +#define AArch64_STZGPreIndex 5158 +#define AArch64_SUBG 5159 +#define AArch64_SUBHNB_ZZZ_B 5160 +#define AArch64_SUBHNB_ZZZ_H 5161 +#define AArch64_SUBHNB_ZZZ_S 5162 +#define AArch64_SUBHNT_ZZZ_B 5163 +#define AArch64_SUBHNT_ZZZ_H 5164 +#define AArch64_SUBHNT_ZZZ_S 5165 +#define AArch64_SUBHNv2i64_v2i32 5166 +#define AArch64_SUBHNv2i64_v4i32 5167 +#define AArch64_SUBHNv4i32_v4i16 5168 +#define AArch64_SUBHNv4i32_v8i16 5169 +#define AArch64_SUBHNv8i16_v16i8 5170 +#define AArch64_SUBHNv8i16_v8i8 5171 +#define AArch64_SUBP 5172 +#define AArch64_SUBPS 5173 +#define AArch64_SUBR_ZI_B 5174 +#define AArch64_SUBR_ZI_D 5175 +#define AArch64_SUBR_ZI_H 5176 +#define AArch64_SUBR_ZI_S 5177 +#define AArch64_SUBR_ZPmZ_B 5178 +#define AArch64_SUBR_ZPmZ_D 5179 +#define AArch64_SUBR_ZPmZ_H 5180 +#define AArch64_SUBR_ZPmZ_S 5181 +#define AArch64_SUBSWri 5182 +#define AArch64_SUBSWrs 5183 +#define AArch64_SUBSWrx 5184 +#define AArch64_SUBSXri 5185 +#define AArch64_SUBSXrs 5186 +#define AArch64_SUBSXrx 5187 +#define AArch64_SUBSXrx64 5188 +#define AArch64_SUBWri 5189 +#define AArch64_SUBWrs 5190 +#define AArch64_SUBWrx 5191 +#define AArch64_SUBXri 5192 +#define AArch64_SUBXrs 5193 +#define AArch64_SUBXrx 5194 +#define AArch64_SUBXrx64 5195 +#define AArch64_SUB_ZI_B 5196 +#define AArch64_SUB_ZI_D 5197 +#define AArch64_SUB_ZI_H 5198 +#define AArch64_SUB_ZI_S 5199 +#define AArch64_SUB_ZPmZ_B 5200 +#define AArch64_SUB_ZPmZ_D 5201 +#define AArch64_SUB_ZPmZ_H 5202 +#define AArch64_SUB_ZPmZ_S 5203 +#define AArch64_SUB_ZZZ_B 5204 +#define AArch64_SUB_ZZZ_D 5205 +#define AArch64_SUB_ZZZ_H 5206 +#define AArch64_SUB_ZZZ_S 5207 +#define AArch64_SUBv16i8 5208 +#define AArch64_SUBv1i64 5209 +#define AArch64_SUBv2i32 5210 +#define AArch64_SUBv2i64 5211 +#define AArch64_SUBv4i16 5212 +#define AArch64_SUBv4i32 5213 +#define AArch64_SUBv8i16 5214 +#define AArch64_SUBv8i8 5215 +#define AArch64_SUDOT_ZZZI 5216 +#define AArch64_SUDOTlanev16i8 5217 +#define AArch64_SUDOTlanev8i8 5218 +#define AArch64_SUMOPA_MPPZZ_D 5219 +#define AArch64_SUMOPA_MPPZZ_S 5220 +#define AArch64_SUMOPS_MPPZZ_D 5221 +#define AArch64_SUMOPS_MPPZZ_S 5222 +#define AArch64_SUNPKHI_ZZ_D 5223 +#define AArch64_SUNPKHI_ZZ_H 5224 +#define AArch64_SUNPKHI_ZZ_S 5225 +#define AArch64_SUNPKLO_ZZ_D 5226 +#define AArch64_SUNPKLO_ZZ_H 5227 +#define AArch64_SUNPKLO_ZZ_S 5228 +#define AArch64_SUQADD_ZPmZ_B 5229 +#define AArch64_SUQADD_ZPmZ_D 5230 +#define AArch64_SUQADD_ZPmZ_H 5231 +#define AArch64_SUQADD_ZPmZ_S 5232 +#define AArch64_SUQADDv16i8 5233 +#define AArch64_SUQADDv1i16 5234 +#define AArch64_SUQADDv1i32 5235 +#define AArch64_SUQADDv1i64 5236 +#define AArch64_SUQADDv1i8 5237 +#define AArch64_SUQADDv2i32 5238 +#define AArch64_SUQADDv2i64 5239 +#define AArch64_SUQADDv4i16 5240 +#define AArch64_SUQADDv4i32 5241 +#define AArch64_SUQADDv8i16 5242 +#define AArch64_SUQADDv8i8 5243 +#define AArch64_SVC 5244 +#define AArch64_SWPAB 5245 +#define AArch64_SWPAH 5246 +#define AArch64_SWPALB 5247 +#define AArch64_SWPALH 5248 +#define AArch64_SWPALW 5249 +#define AArch64_SWPALX 5250 +#define AArch64_SWPAW 5251 +#define AArch64_SWPAX 5252 +#define AArch64_SWPB 5253 +#define AArch64_SWPH 5254 +#define AArch64_SWPLB 5255 +#define AArch64_SWPLH 5256 +#define AArch64_SWPLW 5257 +#define AArch64_SWPLX 5258 +#define AArch64_SWPW 5259 +#define AArch64_SWPX 5260 +#define AArch64_SXTB_ZPmZ_D 5261 +#define AArch64_SXTB_ZPmZ_H 5262 +#define AArch64_SXTB_ZPmZ_S 5263 +#define AArch64_SXTH_ZPmZ_D 5264 +#define AArch64_SXTH_ZPmZ_S 5265 +#define AArch64_SXTW_ZPmZ_D 5266 +#define AArch64_SYSLxt 5267 +#define AArch64_SYSxt 5268 +#define AArch64_TBL_ZZZZ_B 5269 +#define AArch64_TBL_ZZZZ_D 5270 +#define AArch64_TBL_ZZZZ_H 5271 +#define AArch64_TBL_ZZZZ_S 5272 +#define AArch64_TBL_ZZZ_B 5273 +#define AArch64_TBL_ZZZ_D 5274 +#define AArch64_TBL_ZZZ_H 5275 +#define AArch64_TBL_ZZZ_S 5276 +#define AArch64_TBLv16i8Four 5277 +#define AArch64_TBLv16i8One 5278 +#define AArch64_TBLv16i8Three 5279 +#define AArch64_TBLv16i8Two 5280 +#define AArch64_TBLv8i8Four 5281 +#define AArch64_TBLv8i8One 5282 +#define AArch64_TBLv8i8Three 5283 +#define AArch64_TBLv8i8Two 5284 +#define AArch64_TBNZW 5285 +#define AArch64_TBNZX 5286 +#define AArch64_TBX_ZZZ_B 5287 +#define AArch64_TBX_ZZZ_D 5288 +#define AArch64_TBX_ZZZ_H 5289 +#define AArch64_TBX_ZZZ_S 5290 +#define AArch64_TBXv16i8Four 5291 +#define AArch64_TBXv16i8One 5292 +#define AArch64_TBXv16i8Three 5293 +#define AArch64_TBXv16i8Two 5294 +#define AArch64_TBXv8i8Four 5295 +#define AArch64_TBXv8i8One 5296 +#define AArch64_TBXv8i8Three 5297 +#define AArch64_TBXv8i8Two 5298 +#define AArch64_TBZW 5299 +#define AArch64_TBZX 5300 +#define AArch64_TCANCEL 5301 +#define AArch64_TCOMMIT 5302 +#define AArch64_TRN1_PPP_B 5303 +#define AArch64_TRN1_PPP_D 5304 +#define AArch64_TRN1_PPP_H 5305 +#define AArch64_TRN1_PPP_S 5306 +#define AArch64_TRN1_ZZZ_B 5307 +#define AArch64_TRN1_ZZZ_D 5308 +#define AArch64_TRN1_ZZZ_H 5309 +#define AArch64_TRN1_ZZZ_Q 5310 +#define AArch64_TRN1_ZZZ_S 5311 +#define AArch64_TRN1v16i8 5312 +#define AArch64_TRN1v2i32 5313 +#define AArch64_TRN1v2i64 5314 +#define AArch64_TRN1v4i16 5315 +#define AArch64_TRN1v4i32 5316 +#define AArch64_TRN1v8i16 5317 +#define AArch64_TRN1v8i8 5318 +#define AArch64_TRN2_PPP_B 5319 +#define AArch64_TRN2_PPP_D 5320 +#define AArch64_TRN2_PPP_H 5321 +#define AArch64_TRN2_PPP_S 5322 +#define AArch64_TRN2_ZZZ_B 5323 +#define AArch64_TRN2_ZZZ_D 5324 +#define AArch64_TRN2_ZZZ_H 5325 +#define AArch64_TRN2_ZZZ_Q 5326 +#define AArch64_TRN2_ZZZ_S 5327 +#define AArch64_TRN2v16i8 5328 +#define AArch64_TRN2v2i32 5329 +#define AArch64_TRN2v2i64 5330 +#define AArch64_TRN2v4i16 5331 +#define AArch64_TRN2v4i32 5332 +#define AArch64_TRN2v8i16 5333 +#define AArch64_TRN2v8i8 5334 +#define AArch64_TSB 5335 +#define AArch64_TSTART 5336 +#define AArch64_TTEST 5337 +#define AArch64_UABALB_ZZZ_D 5338 +#define AArch64_UABALB_ZZZ_H 5339 +#define AArch64_UABALB_ZZZ_S 5340 +#define AArch64_UABALT_ZZZ_D 5341 +#define AArch64_UABALT_ZZZ_H 5342 +#define AArch64_UABALT_ZZZ_S 5343 +#define AArch64_UABALv16i8_v8i16 5344 +#define AArch64_UABALv2i32_v2i64 5345 +#define AArch64_UABALv4i16_v4i32 5346 +#define AArch64_UABALv4i32_v2i64 5347 +#define AArch64_UABALv8i16_v4i32 5348 +#define AArch64_UABALv8i8_v8i16 5349 +#define AArch64_UABA_ZZZ_B 5350 +#define AArch64_UABA_ZZZ_D 5351 +#define AArch64_UABA_ZZZ_H 5352 +#define AArch64_UABA_ZZZ_S 5353 +#define AArch64_UABAv16i8 5354 +#define AArch64_UABAv2i32 5355 +#define AArch64_UABAv4i16 5356 +#define AArch64_UABAv4i32 5357 +#define AArch64_UABAv8i16 5358 +#define AArch64_UABAv8i8 5359 +#define AArch64_UABDLB_ZZZ_D 5360 +#define AArch64_UABDLB_ZZZ_H 5361 +#define AArch64_UABDLB_ZZZ_S 5362 +#define AArch64_UABDLT_ZZZ_D 5363 +#define AArch64_UABDLT_ZZZ_H 5364 +#define AArch64_UABDLT_ZZZ_S 5365 +#define AArch64_UABDLv16i8_v8i16 5366 +#define AArch64_UABDLv2i32_v2i64 5367 +#define AArch64_UABDLv4i16_v4i32 5368 +#define AArch64_UABDLv4i32_v2i64 5369 +#define AArch64_UABDLv8i16_v4i32 5370 +#define AArch64_UABDLv8i8_v8i16 5371 +#define AArch64_UABD_ZPmZ_B 5372 +#define AArch64_UABD_ZPmZ_D 5373 +#define AArch64_UABD_ZPmZ_H 5374 +#define AArch64_UABD_ZPmZ_S 5375 +#define AArch64_UABDv16i8 5376 +#define AArch64_UABDv2i32 5377 +#define AArch64_UABDv4i16 5378 +#define AArch64_UABDv4i32 5379 +#define AArch64_UABDv8i16 5380 +#define AArch64_UABDv8i8 5381 +#define AArch64_UADALP_ZPmZ_D 5382 +#define AArch64_UADALP_ZPmZ_H 5383 +#define AArch64_UADALP_ZPmZ_S 5384 +#define AArch64_UADALPv16i8_v8i16 5385 +#define AArch64_UADALPv2i32_v1i64 5386 +#define AArch64_UADALPv4i16_v2i32 5387 +#define AArch64_UADALPv4i32_v2i64 5388 +#define AArch64_UADALPv8i16_v4i32 5389 +#define AArch64_UADALPv8i8_v4i16 5390 +#define AArch64_UADDLB_ZZZ_D 5391 +#define AArch64_UADDLB_ZZZ_H 5392 +#define AArch64_UADDLB_ZZZ_S 5393 +#define AArch64_UADDLPv16i8_v8i16 5394 +#define AArch64_UADDLPv2i32_v1i64 5395 +#define AArch64_UADDLPv4i16_v2i32 5396 +#define AArch64_UADDLPv4i32_v2i64 5397 +#define AArch64_UADDLPv8i16_v4i32 5398 +#define AArch64_UADDLPv8i8_v4i16 5399 +#define AArch64_UADDLT_ZZZ_D 5400 +#define AArch64_UADDLT_ZZZ_H 5401 +#define AArch64_UADDLT_ZZZ_S 5402 +#define AArch64_UADDLVv16i8v 5403 +#define AArch64_UADDLVv4i16v 5404 +#define AArch64_UADDLVv4i32v 5405 +#define AArch64_UADDLVv8i16v 5406 +#define AArch64_UADDLVv8i8v 5407 +#define AArch64_UADDLv16i8_v8i16 5408 +#define AArch64_UADDLv2i32_v2i64 5409 +#define AArch64_UADDLv4i16_v4i32 5410 +#define AArch64_UADDLv4i32_v2i64 5411 +#define AArch64_UADDLv8i16_v4i32 5412 +#define AArch64_UADDLv8i8_v8i16 5413 +#define AArch64_UADDV_VPZ_B 5414 +#define AArch64_UADDV_VPZ_D 5415 +#define AArch64_UADDV_VPZ_H 5416 +#define AArch64_UADDV_VPZ_S 5417 +#define AArch64_UADDWB_ZZZ_D 5418 +#define AArch64_UADDWB_ZZZ_H 5419 +#define AArch64_UADDWB_ZZZ_S 5420 +#define AArch64_UADDWT_ZZZ_D 5421 +#define AArch64_UADDWT_ZZZ_H 5422 +#define AArch64_UADDWT_ZZZ_S 5423 +#define AArch64_UADDWv16i8_v8i16 5424 +#define AArch64_UADDWv2i32_v2i64 5425 +#define AArch64_UADDWv4i16_v4i32 5426 +#define AArch64_UADDWv4i32_v2i64 5427 +#define AArch64_UADDWv8i16_v4i32 5428 +#define AArch64_UADDWv8i8_v8i16 5429 +#define AArch64_UBFMWri 5430 +#define AArch64_UBFMXri 5431 +#define AArch64_UCLAMP_ZZZ_B 5432 +#define AArch64_UCLAMP_ZZZ_D 5433 +#define AArch64_UCLAMP_ZZZ_H 5434 +#define AArch64_UCLAMP_ZZZ_S 5435 +#define AArch64_UCVTFSWDri 5436 +#define AArch64_UCVTFSWHri 5437 +#define AArch64_UCVTFSWSri 5438 +#define AArch64_UCVTFSXDri 5439 +#define AArch64_UCVTFSXHri 5440 +#define AArch64_UCVTFSXSri 5441 +#define AArch64_UCVTFUWDri 5442 +#define AArch64_UCVTFUWHri 5443 +#define AArch64_UCVTFUWSri 5444 +#define AArch64_UCVTFUXDri 5445 +#define AArch64_UCVTFUXHri 5446 +#define AArch64_UCVTFUXSri 5447 +#define AArch64_UCVTF_ZPmZ_DtoD 5448 +#define AArch64_UCVTF_ZPmZ_DtoH 5449 +#define AArch64_UCVTF_ZPmZ_DtoS 5450 +#define AArch64_UCVTF_ZPmZ_HtoH 5451 +#define AArch64_UCVTF_ZPmZ_StoD 5452 +#define AArch64_UCVTF_ZPmZ_StoH 5453 +#define AArch64_UCVTF_ZPmZ_StoS 5454 +#define AArch64_UCVTFd 5455 +#define AArch64_UCVTFh 5456 +#define AArch64_UCVTFs 5457 +#define AArch64_UCVTFv1i16 5458 +#define AArch64_UCVTFv1i32 5459 +#define AArch64_UCVTFv1i64 5460 +#define AArch64_UCVTFv2f32 5461 +#define AArch64_UCVTFv2f64 5462 +#define AArch64_UCVTFv2i32_shift 5463 +#define AArch64_UCVTFv2i64_shift 5464 +#define AArch64_UCVTFv4f16 5465 +#define AArch64_UCVTFv4f32 5466 +#define AArch64_UCVTFv4i16_shift 5467 +#define AArch64_UCVTFv4i32_shift 5468 +#define AArch64_UCVTFv8f16 5469 +#define AArch64_UCVTFv8i16_shift 5470 +#define AArch64_UDF 5471 +#define AArch64_UDIVR_ZPmZ_D 5472 +#define AArch64_UDIVR_ZPmZ_S 5473 +#define AArch64_UDIVWr 5474 +#define AArch64_UDIVXr 5475 +#define AArch64_UDIV_ZPmZ_D 5476 +#define AArch64_UDIV_ZPmZ_S 5477 +#define AArch64_UDOT_ZZZI_D 5478 +#define AArch64_UDOT_ZZZI_S 5479 +#define AArch64_UDOT_ZZZ_D 5480 +#define AArch64_UDOT_ZZZ_S 5481 +#define AArch64_UDOTlanev16i8 5482 +#define AArch64_UDOTlanev8i8 5483 +#define AArch64_UDOTv16i8 5484 +#define AArch64_UDOTv8i8 5485 +#define AArch64_UHADD_ZPmZ_B 5486 +#define AArch64_UHADD_ZPmZ_D 5487 +#define AArch64_UHADD_ZPmZ_H 5488 +#define AArch64_UHADD_ZPmZ_S 5489 +#define AArch64_UHADDv16i8 5490 +#define AArch64_UHADDv2i32 5491 +#define AArch64_UHADDv4i16 5492 +#define AArch64_UHADDv4i32 5493 +#define AArch64_UHADDv8i16 5494 +#define AArch64_UHADDv8i8 5495 +#define AArch64_UHSUBR_ZPmZ_B 5496 +#define AArch64_UHSUBR_ZPmZ_D 5497 +#define AArch64_UHSUBR_ZPmZ_H 5498 +#define AArch64_UHSUBR_ZPmZ_S 5499 +#define AArch64_UHSUB_ZPmZ_B 5500 +#define AArch64_UHSUB_ZPmZ_D 5501 +#define AArch64_UHSUB_ZPmZ_H 5502 +#define AArch64_UHSUB_ZPmZ_S 5503 +#define AArch64_UHSUBv16i8 5504 +#define AArch64_UHSUBv2i32 5505 +#define AArch64_UHSUBv4i16 5506 +#define AArch64_UHSUBv4i32 5507 +#define AArch64_UHSUBv8i16 5508 +#define AArch64_UHSUBv8i8 5509 +#define AArch64_UMADDLrrr 5510 +#define AArch64_UMAXP_ZPmZ_B 5511 +#define AArch64_UMAXP_ZPmZ_D 5512 +#define AArch64_UMAXP_ZPmZ_H 5513 +#define AArch64_UMAXP_ZPmZ_S 5514 +#define AArch64_UMAXPv16i8 5515 +#define AArch64_UMAXPv2i32 5516 +#define AArch64_UMAXPv4i16 5517 +#define AArch64_UMAXPv4i32 5518 +#define AArch64_UMAXPv8i16 5519 +#define AArch64_UMAXPv8i8 5520 +#define AArch64_UMAXV_VPZ_B 5521 +#define AArch64_UMAXV_VPZ_D 5522 +#define AArch64_UMAXV_VPZ_H 5523 +#define AArch64_UMAXV_VPZ_S 5524 +#define AArch64_UMAXVv16i8v 5525 +#define AArch64_UMAXVv4i16v 5526 +#define AArch64_UMAXVv4i32v 5527 +#define AArch64_UMAXVv8i16v 5528 +#define AArch64_UMAXVv8i8v 5529 +#define AArch64_UMAX_ZI_B 5530 +#define AArch64_UMAX_ZI_D 5531 +#define AArch64_UMAX_ZI_H 5532 +#define AArch64_UMAX_ZI_S 5533 +#define AArch64_UMAX_ZPmZ_B 5534 +#define AArch64_UMAX_ZPmZ_D 5535 +#define AArch64_UMAX_ZPmZ_H 5536 +#define AArch64_UMAX_ZPmZ_S 5537 +#define AArch64_UMAXv16i8 5538 +#define AArch64_UMAXv2i32 5539 +#define AArch64_UMAXv4i16 5540 +#define AArch64_UMAXv4i32 5541 +#define AArch64_UMAXv8i16 5542 +#define AArch64_UMAXv8i8 5543 +#define AArch64_UMINP_ZPmZ_B 5544 +#define AArch64_UMINP_ZPmZ_D 5545 +#define AArch64_UMINP_ZPmZ_H 5546 +#define AArch64_UMINP_ZPmZ_S 5547 +#define AArch64_UMINPv16i8 5548 +#define AArch64_UMINPv2i32 5549 +#define AArch64_UMINPv4i16 5550 +#define AArch64_UMINPv4i32 5551 +#define AArch64_UMINPv8i16 5552 +#define AArch64_UMINPv8i8 5553 +#define AArch64_UMINV_VPZ_B 5554 +#define AArch64_UMINV_VPZ_D 5555 +#define AArch64_UMINV_VPZ_H 5556 +#define AArch64_UMINV_VPZ_S 5557 +#define AArch64_UMINVv16i8v 5558 +#define AArch64_UMINVv4i16v 5559 +#define AArch64_UMINVv4i32v 5560 +#define AArch64_UMINVv8i16v 5561 +#define AArch64_UMINVv8i8v 5562 +#define AArch64_UMIN_ZI_B 5563 +#define AArch64_UMIN_ZI_D 5564 +#define AArch64_UMIN_ZI_H 5565 +#define AArch64_UMIN_ZI_S 5566 +#define AArch64_UMIN_ZPmZ_B 5567 +#define AArch64_UMIN_ZPmZ_D 5568 +#define AArch64_UMIN_ZPmZ_H 5569 +#define AArch64_UMIN_ZPmZ_S 5570 +#define AArch64_UMINv16i8 5571 +#define AArch64_UMINv2i32 5572 +#define AArch64_UMINv4i16 5573 +#define AArch64_UMINv4i32 5574 +#define AArch64_UMINv8i16 5575 +#define AArch64_UMINv8i8 5576 +#define AArch64_UMLALB_ZZZI_D 5577 +#define AArch64_UMLALB_ZZZI_S 5578 +#define AArch64_UMLALB_ZZZ_D 5579 +#define AArch64_UMLALB_ZZZ_H 5580 +#define AArch64_UMLALB_ZZZ_S 5581 +#define AArch64_UMLALT_ZZZI_D 5582 +#define AArch64_UMLALT_ZZZI_S 5583 +#define AArch64_UMLALT_ZZZ_D 5584 +#define AArch64_UMLALT_ZZZ_H 5585 +#define AArch64_UMLALT_ZZZ_S 5586 +#define AArch64_UMLALv16i8_v8i16 5587 +#define AArch64_UMLALv2i32_indexed 5588 +#define AArch64_UMLALv2i32_v2i64 5589 +#define AArch64_UMLALv4i16_indexed 5590 +#define AArch64_UMLALv4i16_v4i32 5591 +#define AArch64_UMLALv4i32_indexed 5592 +#define AArch64_UMLALv4i32_v2i64 5593 +#define AArch64_UMLALv8i16_indexed 5594 +#define AArch64_UMLALv8i16_v4i32 5595 +#define AArch64_UMLALv8i8_v8i16 5596 +#define AArch64_UMLSLB_ZZZI_D 5597 +#define AArch64_UMLSLB_ZZZI_S 5598 +#define AArch64_UMLSLB_ZZZ_D 5599 +#define AArch64_UMLSLB_ZZZ_H 5600 +#define AArch64_UMLSLB_ZZZ_S 5601 +#define AArch64_UMLSLT_ZZZI_D 5602 +#define AArch64_UMLSLT_ZZZI_S 5603 +#define AArch64_UMLSLT_ZZZ_D 5604 +#define AArch64_UMLSLT_ZZZ_H 5605 +#define AArch64_UMLSLT_ZZZ_S 5606 +#define AArch64_UMLSLv16i8_v8i16 5607 +#define AArch64_UMLSLv2i32_indexed 5608 +#define AArch64_UMLSLv2i32_v2i64 5609 +#define AArch64_UMLSLv4i16_indexed 5610 +#define AArch64_UMLSLv4i16_v4i32 5611 +#define AArch64_UMLSLv4i32_indexed 5612 +#define AArch64_UMLSLv4i32_v2i64 5613 +#define AArch64_UMLSLv8i16_indexed 5614 +#define AArch64_UMLSLv8i16_v4i32 5615 +#define AArch64_UMLSLv8i8_v8i16 5616 +#define AArch64_UMMLA 5617 +#define AArch64_UMMLA_ZZZ 5618 +#define AArch64_UMOPA_MPPZZ_D 5619 +#define AArch64_UMOPA_MPPZZ_S 5620 +#define AArch64_UMOPS_MPPZZ_D 5621 +#define AArch64_UMOPS_MPPZZ_S 5622 +#define AArch64_UMOVvi16 5623 +#define AArch64_UMOVvi16_idx0 5624 +#define AArch64_UMOVvi32 5625 +#define AArch64_UMOVvi32_idx0 5626 +#define AArch64_UMOVvi64 5627 +#define AArch64_UMOVvi64_idx0 5628 +#define AArch64_UMOVvi8 5629 +#define AArch64_UMOVvi8_idx0 5630 +#define AArch64_UMSUBLrrr 5631 +#define AArch64_UMULH_ZPmZ_B 5632 +#define AArch64_UMULH_ZPmZ_D 5633 +#define AArch64_UMULH_ZPmZ_H 5634 +#define AArch64_UMULH_ZPmZ_S 5635 +#define AArch64_UMULH_ZZZ_B 5636 +#define AArch64_UMULH_ZZZ_D 5637 +#define AArch64_UMULH_ZZZ_H 5638 +#define AArch64_UMULH_ZZZ_S 5639 +#define AArch64_UMULHrr 5640 +#define AArch64_UMULLB_ZZZI_D 5641 +#define AArch64_UMULLB_ZZZI_S 5642 +#define AArch64_UMULLB_ZZZ_D 5643 +#define AArch64_UMULLB_ZZZ_H 5644 +#define AArch64_UMULLB_ZZZ_S 5645 +#define AArch64_UMULLT_ZZZI_D 5646 +#define AArch64_UMULLT_ZZZI_S 5647 +#define AArch64_UMULLT_ZZZ_D 5648 +#define AArch64_UMULLT_ZZZ_H 5649 +#define AArch64_UMULLT_ZZZ_S 5650 +#define AArch64_UMULLv16i8_v8i16 5651 +#define AArch64_UMULLv2i32_indexed 5652 +#define AArch64_UMULLv2i32_v2i64 5653 +#define AArch64_UMULLv4i16_indexed 5654 +#define AArch64_UMULLv4i16_v4i32 5655 +#define AArch64_UMULLv4i32_indexed 5656 +#define AArch64_UMULLv4i32_v2i64 5657 +#define AArch64_UMULLv8i16_indexed 5658 +#define AArch64_UMULLv8i16_v4i32 5659 +#define AArch64_UMULLv8i8_v8i16 5660 +#define AArch64_UQADD_ZI_B 5661 +#define AArch64_UQADD_ZI_D 5662 +#define AArch64_UQADD_ZI_H 5663 +#define AArch64_UQADD_ZI_S 5664 +#define AArch64_UQADD_ZPmZ_B 5665 +#define AArch64_UQADD_ZPmZ_D 5666 +#define AArch64_UQADD_ZPmZ_H 5667 +#define AArch64_UQADD_ZPmZ_S 5668 +#define AArch64_UQADD_ZZZ_B 5669 +#define AArch64_UQADD_ZZZ_D 5670 +#define AArch64_UQADD_ZZZ_H 5671 +#define AArch64_UQADD_ZZZ_S 5672 +#define AArch64_UQADDv16i8 5673 +#define AArch64_UQADDv1i16 5674 +#define AArch64_UQADDv1i32 5675 +#define AArch64_UQADDv1i64 5676 +#define AArch64_UQADDv1i8 5677 +#define AArch64_UQADDv2i32 5678 +#define AArch64_UQADDv2i64 5679 +#define AArch64_UQADDv4i16 5680 +#define AArch64_UQADDv4i32 5681 +#define AArch64_UQADDv8i16 5682 +#define AArch64_UQADDv8i8 5683 +#define AArch64_UQDECB_WPiI 5684 +#define AArch64_UQDECB_XPiI 5685 +#define AArch64_UQDECD_WPiI 5686 +#define AArch64_UQDECD_XPiI 5687 +#define AArch64_UQDECD_ZPiI 5688 +#define AArch64_UQDECH_WPiI 5689 +#define AArch64_UQDECH_XPiI 5690 +#define AArch64_UQDECH_ZPiI 5691 +#define AArch64_UQDECP_WP_B 5692 +#define AArch64_UQDECP_WP_D 5693 +#define AArch64_UQDECP_WP_H 5694 +#define AArch64_UQDECP_WP_S 5695 +#define AArch64_UQDECP_XP_B 5696 +#define AArch64_UQDECP_XP_D 5697 +#define AArch64_UQDECP_XP_H 5698 +#define AArch64_UQDECP_XP_S 5699 +#define AArch64_UQDECP_ZP_D 5700 +#define AArch64_UQDECP_ZP_H 5701 +#define AArch64_UQDECP_ZP_S 5702 +#define AArch64_UQDECW_WPiI 5703 +#define AArch64_UQDECW_XPiI 5704 +#define AArch64_UQDECW_ZPiI 5705 +#define AArch64_UQINCB_WPiI 5706 +#define AArch64_UQINCB_XPiI 5707 +#define AArch64_UQINCD_WPiI 5708 +#define AArch64_UQINCD_XPiI 5709 +#define AArch64_UQINCD_ZPiI 5710 +#define AArch64_UQINCH_WPiI 5711 +#define AArch64_UQINCH_XPiI 5712 +#define AArch64_UQINCH_ZPiI 5713 +#define AArch64_UQINCP_WP_B 5714 +#define AArch64_UQINCP_WP_D 5715 +#define AArch64_UQINCP_WP_H 5716 +#define AArch64_UQINCP_WP_S 5717 +#define AArch64_UQINCP_XP_B 5718 +#define AArch64_UQINCP_XP_D 5719 +#define AArch64_UQINCP_XP_H 5720 +#define AArch64_UQINCP_XP_S 5721 +#define AArch64_UQINCP_ZP_D 5722 +#define AArch64_UQINCP_ZP_H 5723 +#define AArch64_UQINCP_ZP_S 5724 +#define AArch64_UQINCW_WPiI 5725 +#define AArch64_UQINCW_XPiI 5726 +#define AArch64_UQINCW_ZPiI 5727 +#define AArch64_UQRSHLR_ZPmZ_B 5728 +#define AArch64_UQRSHLR_ZPmZ_D 5729 +#define AArch64_UQRSHLR_ZPmZ_H 5730 +#define AArch64_UQRSHLR_ZPmZ_S 5731 +#define AArch64_UQRSHL_ZPmZ_B 5732 +#define AArch64_UQRSHL_ZPmZ_D 5733 +#define AArch64_UQRSHL_ZPmZ_H 5734 +#define AArch64_UQRSHL_ZPmZ_S 5735 +#define AArch64_UQRSHLv16i8 5736 +#define AArch64_UQRSHLv1i16 5737 +#define AArch64_UQRSHLv1i32 5738 +#define AArch64_UQRSHLv1i64 5739 +#define AArch64_UQRSHLv1i8 5740 +#define AArch64_UQRSHLv2i32 5741 +#define AArch64_UQRSHLv2i64 5742 +#define AArch64_UQRSHLv4i16 5743 +#define AArch64_UQRSHLv4i32 5744 +#define AArch64_UQRSHLv8i16 5745 +#define AArch64_UQRSHLv8i8 5746 +#define AArch64_UQRSHRNB_ZZI_B 5747 +#define AArch64_UQRSHRNB_ZZI_H 5748 +#define AArch64_UQRSHRNB_ZZI_S 5749 +#define AArch64_UQRSHRNT_ZZI_B 5750 +#define AArch64_UQRSHRNT_ZZI_H 5751 +#define AArch64_UQRSHRNT_ZZI_S 5752 +#define AArch64_UQRSHRNb 5753 +#define AArch64_UQRSHRNh 5754 +#define AArch64_UQRSHRNs 5755 +#define AArch64_UQRSHRNv16i8_shift 5756 +#define AArch64_UQRSHRNv2i32_shift 5757 +#define AArch64_UQRSHRNv4i16_shift 5758 +#define AArch64_UQRSHRNv4i32_shift 5759 +#define AArch64_UQRSHRNv8i16_shift 5760 +#define AArch64_UQRSHRNv8i8_shift 5761 +#define AArch64_UQSHLR_ZPmZ_B 5762 +#define AArch64_UQSHLR_ZPmZ_D 5763 +#define AArch64_UQSHLR_ZPmZ_H 5764 +#define AArch64_UQSHLR_ZPmZ_S 5765 +#define AArch64_UQSHL_ZPmI_B 5766 +#define AArch64_UQSHL_ZPmI_D 5767 +#define AArch64_UQSHL_ZPmI_H 5768 +#define AArch64_UQSHL_ZPmI_S 5769 +#define AArch64_UQSHL_ZPmZ_B 5770 +#define AArch64_UQSHL_ZPmZ_D 5771 +#define AArch64_UQSHL_ZPmZ_H 5772 +#define AArch64_UQSHL_ZPmZ_S 5773 +#define AArch64_UQSHLb 5774 +#define AArch64_UQSHLd 5775 +#define AArch64_UQSHLh 5776 +#define AArch64_UQSHLs 5777 +#define AArch64_UQSHLv16i8 5778 +#define AArch64_UQSHLv16i8_shift 5779 +#define AArch64_UQSHLv1i16 5780 +#define AArch64_UQSHLv1i32 5781 +#define AArch64_UQSHLv1i64 5782 +#define AArch64_UQSHLv1i8 5783 +#define AArch64_UQSHLv2i32 5784 +#define AArch64_UQSHLv2i32_shift 5785 +#define AArch64_UQSHLv2i64 5786 +#define AArch64_UQSHLv2i64_shift 5787 +#define AArch64_UQSHLv4i16 5788 +#define AArch64_UQSHLv4i16_shift 5789 +#define AArch64_UQSHLv4i32 5790 +#define AArch64_UQSHLv4i32_shift 5791 +#define AArch64_UQSHLv8i16 5792 +#define AArch64_UQSHLv8i16_shift 5793 +#define AArch64_UQSHLv8i8 5794 +#define AArch64_UQSHLv8i8_shift 5795 +#define AArch64_UQSHRNB_ZZI_B 5796 +#define AArch64_UQSHRNB_ZZI_H 5797 +#define AArch64_UQSHRNB_ZZI_S 5798 +#define AArch64_UQSHRNT_ZZI_B 5799 +#define AArch64_UQSHRNT_ZZI_H 5800 +#define AArch64_UQSHRNT_ZZI_S 5801 +#define AArch64_UQSHRNb 5802 +#define AArch64_UQSHRNh 5803 +#define AArch64_UQSHRNs 5804 +#define AArch64_UQSHRNv16i8_shift 5805 +#define AArch64_UQSHRNv2i32_shift 5806 +#define AArch64_UQSHRNv4i16_shift 5807 +#define AArch64_UQSHRNv4i32_shift 5808 +#define AArch64_UQSHRNv8i16_shift 5809 +#define AArch64_UQSHRNv8i8_shift 5810 +#define AArch64_UQSUBR_ZPmZ_B 5811 +#define AArch64_UQSUBR_ZPmZ_D 5812 +#define AArch64_UQSUBR_ZPmZ_H 5813 +#define AArch64_UQSUBR_ZPmZ_S 5814 +#define AArch64_UQSUB_ZI_B 5815 +#define AArch64_UQSUB_ZI_D 5816 +#define AArch64_UQSUB_ZI_H 5817 +#define AArch64_UQSUB_ZI_S 5818 +#define AArch64_UQSUB_ZPmZ_B 5819 +#define AArch64_UQSUB_ZPmZ_D 5820 +#define AArch64_UQSUB_ZPmZ_H 5821 +#define AArch64_UQSUB_ZPmZ_S 5822 +#define AArch64_UQSUB_ZZZ_B 5823 +#define AArch64_UQSUB_ZZZ_D 5824 +#define AArch64_UQSUB_ZZZ_H 5825 +#define AArch64_UQSUB_ZZZ_S 5826 +#define AArch64_UQSUBv16i8 5827 +#define AArch64_UQSUBv1i16 5828 +#define AArch64_UQSUBv1i32 5829 +#define AArch64_UQSUBv1i64 5830 +#define AArch64_UQSUBv1i8 5831 +#define AArch64_UQSUBv2i32 5832 +#define AArch64_UQSUBv2i64 5833 +#define AArch64_UQSUBv4i16 5834 +#define AArch64_UQSUBv4i32 5835 +#define AArch64_UQSUBv8i16 5836 +#define AArch64_UQSUBv8i8 5837 +#define AArch64_UQXTNB_ZZ_B 5838 +#define AArch64_UQXTNB_ZZ_H 5839 +#define AArch64_UQXTNB_ZZ_S 5840 +#define AArch64_UQXTNT_ZZ_B 5841 +#define AArch64_UQXTNT_ZZ_H 5842 +#define AArch64_UQXTNT_ZZ_S 5843 +#define AArch64_UQXTNv16i8 5844 +#define AArch64_UQXTNv1i16 5845 +#define AArch64_UQXTNv1i32 5846 +#define AArch64_UQXTNv1i8 5847 +#define AArch64_UQXTNv2i32 5848 +#define AArch64_UQXTNv4i16 5849 +#define AArch64_UQXTNv4i32 5850 +#define AArch64_UQXTNv8i16 5851 +#define AArch64_UQXTNv8i8 5852 +#define AArch64_URECPE_ZPmZ_S 5853 +#define AArch64_URECPEv2i32 5854 +#define AArch64_URECPEv4i32 5855 +#define AArch64_URHADD_ZPmZ_B 5856 +#define AArch64_URHADD_ZPmZ_D 5857 +#define AArch64_URHADD_ZPmZ_H 5858 +#define AArch64_URHADD_ZPmZ_S 5859 +#define AArch64_URHADDv16i8 5860 +#define AArch64_URHADDv2i32 5861 +#define AArch64_URHADDv4i16 5862 +#define AArch64_URHADDv4i32 5863 +#define AArch64_URHADDv8i16 5864 +#define AArch64_URHADDv8i8 5865 +#define AArch64_URSHLR_ZPmZ_B 5866 +#define AArch64_URSHLR_ZPmZ_D 5867 +#define AArch64_URSHLR_ZPmZ_H 5868 +#define AArch64_URSHLR_ZPmZ_S 5869 +#define AArch64_URSHL_ZPmZ_B 5870 +#define AArch64_URSHL_ZPmZ_D 5871 +#define AArch64_URSHL_ZPmZ_H 5872 +#define AArch64_URSHL_ZPmZ_S 5873 +#define AArch64_URSHLv16i8 5874 +#define AArch64_URSHLv1i64 5875 +#define AArch64_URSHLv2i32 5876 +#define AArch64_URSHLv2i64 5877 +#define AArch64_URSHLv4i16 5878 +#define AArch64_URSHLv4i32 5879 +#define AArch64_URSHLv8i16 5880 +#define AArch64_URSHLv8i8 5881 +#define AArch64_URSHR_ZPmI_B 5882 +#define AArch64_URSHR_ZPmI_D 5883 +#define AArch64_URSHR_ZPmI_H 5884 +#define AArch64_URSHR_ZPmI_S 5885 +#define AArch64_URSHRd 5886 +#define AArch64_URSHRv16i8_shift 5887 +#define AArch64_URSHRv2i32_shift 5888 +#define AArch64_URSHRv2i64_shift 5889 +#define AArch64_URSHRv4i16_shift 5890 +#define AArch64_URSHRv4i32_shift 5891 +#define AArch64_URSHRv8i16_shift 5892 +#define AArch64_URSHRv8i8_shift 5893 +#define AArch64_URSQRTE_ZPmZ_S 5894 +#define AArch64_URSQRTEv2i32 5895 +#define AArch64_URSQRTEv4i32 5896 +#define AArch64_URSRA_ZZI_B 5897 +#define AArch64_URSRA_ZZI_D 5898 +#define AArch64_URSRA_ZZI_H 5899 +#define AArch64_URSRA_ZZI_S 5900 +#define AArch64_URSRAd 5901 +#define AArch64_URSRAv16i8_shift 5902 +#define AArch64_URSRAv2i32_shift 5903 +#define AArch64_URSRAv2i64_shift 5904 +#define AArch64_URSRAv4i16_shift 5905 +#define AArch64_URSRAv4i32_shift 5906 +#define AArch64_URSRAv8i16_shift 5907 +#define AArch64_URSRAv8i8_shift 5908 +#define AArch64_USDOT_ZZZ 5909 +#define AArch64_USDOT_ZZZI 5910 +#define AArch64_USDOTlanev16i8 5911 +#define AArch64_USDOTlanev8i8 5912 +#define AArch64_USDOTv16i8 5913 +#define AArch64_USDOTv8i8 5914 +#define AArch64_USHLLB_ZZI_D 5915 +#define AArch64_USHLLB_ZZI_H 5916 +#define AArch64_USHLLB_ZZI_S 5917 +#define AArch64_USHLLT_ZZI_D 5918 +#define AArch64_USHLLT_ZZI_H 5919 +#define AArch64_USHLLT_ZZI_S 5920 +#define AArch64_USHLLv16i8_shift 5921 +#define AArch64_USHLLv2i32_shift 5922 +#define AArch64_USHLLv4i16_shift 5923 +#define AArch64_USHLLv4i32_shift 5924 +#define AArch64_USHLLv8i16_shift 5925 +#define AArch64_USHLLv8i8_shift 5926 +#define AArch64_USHLv16i8 5927 +#define AArch64_USHLv1i64 5928 +#define AArch64_USHLv2i32 5929 +#define AArch64_USHLv2i64 5930 +#define AArch64_USHLv4i16 5931 +#define AArch64_USHLv4i32 5932 +#define AArch64_USHLv8i16 5933 +#define AArch64_USHLv8i8 5934 +#define AArch64_USHRd 5935 +#define AArch64_USHRv16i8_shift 5936 +#define AArch64_USHRv2i32_shift 5937 +#define AArch64_USHRv2i64_shift 5938 +#define AArch64_USHRv4i16_shift 5939 +#define AArch64_USHRv4i32_shift 5940 +#define AArch64_USHRv8i16_shift 5941 +#define AArch64_USHRv8i8_shift 5942 +#define AArch64_USMMLA 5943 +#define AArch64_USMMLA_ZZZ 5944 +#define AArch64_USMOPA_MPPZZ_D 5945 +#define AArch64_USMOPA_MPPZZ_S 5946 +#define AArch64_USMOPS_MPPZZ_D 5947 +#define AArch64_USMOPS_MPPZZ_S 5948 +#define AArch64_USQADD_ZPmZ_B 5949 +#define AArch64_USQADD_ZPmZ_D 5950 +#define AArch64_USQADD_ZPmZ_H 5951 +#define AArch64_USQADD_ZPmZ_S 5952 +#define AArch64_USQADDv16i8 5953 +#define AArch64_USQADDv1i16 5954 +#define AArch64_USQADDv1i32 5955 +#define AArch64_USQADDv1i64 5956 +#define AArch64_USQADDv1i8 5957 +#define AArch64_USQADDv2i32 5958 +#define AArch64_USQADDv2i64 5959 +#define AArch64_USQADDv4i16 5960 +#define AArch64_USQADDv4i32 5961 +#define AArch64_USQADDv8i16 5962 +#define AArch64_USQADDv8i8 5963 +#define AArch64_USRA_ZZI_B 5964 +#define AArch64_USRA_ZZI_D 5965 +#define AArch64_USRA_ZZI_H 5966 +#define AArch64_USRA_ZZI_S 5967 +#define AArch64_USRAd 5968 +#define AArch64_USRAv16i8_shift 5969 +#define AArch64_USRAv2i32_shift 5970 +#define AArch64_USRAv2i64_shift 5971 +#define AArch64_USRAv4i16_shift 5972 +#define AArch64_USRAv4i32_shift 5973 +#define AArch64_USRAv8i16_shift 5974 +#define AArch64_USRAv8i8_shift 5975 +#define AArch64_USUBLB_ZZZ_D 5976 +#define AArch64_USUBLB_ZZZ_H 5977 +#define AArch64_USUBLB_ZZZ_S 5978 +#define AArch64_USUBLT_ZZZ_D 5979 +#define AArch64_USUBLT_ZZZ_H 5980 +#define AArch64_USUBLT_ZZZ_S 5981 +#define AArch64_USUBLv16i8_v8i16 5982 +#define AArch64_USUBLv2i32_v2i64 5983 +#define AArch64_USUBLv4i16_v4i32 5984 +#define AArch64_USUBLv4i32_v2i64 5985 +#define AArch64_USUBLv8i16_v4i32 5986 +#define AArch64_USUBLv8i8_v8i16 5987 +#define AArch64_USUBWB_ZZZ_D 5988 +#define AArch64_USUBWB_ZZZ_H 5989 +#define AArch64_USUBWB_ZZZ_S 5990 +#define AArch64_USUBWT_ZZZ_D 5991 +#define AArch64_USUBWT_ZZZ_H 5992 +#define AArch64_USUBWT_ZZZ_S 5993 +#define AArch64_USUBWv16i8_v8i16 5994 +#define AArch64_USUBWv2i32_v2i64 5995 +#define AArch64_USUBWv4i16_v4i32 5996 +#define AArch64_USUBWv4i32_v2i64 5997 +#define AArch64_USUBWv8i16_v4i32 5998 +#define AArch64_USUBWv8i8_v8i16 5999 +#define AArch64_UUNPKHI_ZZ_D 6000 +#define AArch64_UUNPKHI_ZZ_H 6001 +#define AArch64_UUNPKHI_ZZ_S 6002 +#define AArch64_UUNPKLO_ZZ_D 6003 +#define AArch64_UUNPKLO_ZZ_H 6004 +#define AArch64_UUNPKLO_ZZ_S 6005 +#define AArch64_UXTB_ZPmZ_D 6006 +#define AArch64_UXTB_ZPmZ_H 6007 +#define AArch64_UXTB_ZPmZ_S 6008 +#define AArch64_UXTH_ZPmZ_D 6009 +#define AArch64_UXTH_ZPmZ_S 6010 +#define AArch64_UXTW_ZPmZ_D 6011 +#define AArch64_UZP1_PPP_B 6012 +#define AArch64_UZP1_PPP_D 6013 +#define AArch64_UZP1_PPP_H 6014 +#define AArch64_UZP1_PPP_S 6015 +#define AArch64_UZP1_ZZZ_B 6016 +#define AArch64_UZP1_ZZZ_D 6017 +#define AArch64_UZP1_ZZZ_H 6018 +#define AArch64_UZP1_ZZZ_Q 6019 +#define AArch64_UZP1_ZZZ_S 6020 +#define AArch64_UZP1v16i8 6021 +#define AArch64_UZP1v2i32 6022 +#define AArch64_UZP1v2i64 6023 +#define AArch64_UZP1v4i16 6024 +#define AArch64_UZP1v4i32 6025 +#define AArch64_UZP1v8i16 6026 +#define AArch64_UZP1v8i8 6027 +#define AArch64_UZP2_PPP_B 6028 +#define AArch64_UZP2_PPP_D 6029 +#define AArch64_UZP2_PPP_H 6030 +#define AArch64_UZP2_PPP_S 6031 +#define AArch64_UZP2_ZZZ_B 6032 +#define AArch64_UZP2_ZZZ_D 6033 +#define AArch64_UZP2_ZZZ_H 6034 +#define AArch64_UZP2_ZZZ_Q 6035 +#define AArch64_UZP2_ZZZ_S 6036 +#define AArch64_UZP2v16i8 6037 +#define AArch64_UZP2v2i32 6038 +#define AArch64_UZP2v2i64 6039 +#define AArch64_UZP2v4i16 6040 +#define AArch64_UZP2v4i32 6041 +#define AArch64_UZP2v8i16 6042 +#define AArch64_UZP2v8i8 6043 +#define AArch64_WFET 6044 +#define AArch64_WFIT 6045 +#define AArch64_WHILEGE_PWW_B 6046 +#define AArch64_WHILEGE_PWW_D 6047 +#define AArch64_WHILEGE_PWW_H 6048 +#define AArch64_WHILEGE_PWW_S 6049 +#define AArch64_WHILEGE_PXX_B 6050 +#define AArch64_WHILEGE_PXX_D 6051 +#define AArch64_WHILEGE_PXX_H 6052 +#define AArch64_WHILEGE_PXX_S 6053 +#define AArch64_WHILEGT_PWW_B 6054 +#define AArch64_WHILEGT_PWW_D 6055 +#define AArch64_WHILEGT_PWW_H 6056 +#define AArch64_WHILEGT_PWW_S 6057 +#define AArch64_WHILEGT_PXX_B 6058 +#define AArch64_WHILEGT_PXX_D 6059 +#define AArch64_WHILEGT_PXX_H 6060 +#define AArch64_WHILEGT_PXX_S 6061 +#define AArch64_WHILEHI_PWW_B 6062 +#define AArch64_WHILEHI_PWW_D 6063 +#define AArch64_WHILEHI_PWW_H 6064 +#define AArch64_WHILEHI_PWW_S 6065 +#define AArch64_WHILEHI_PXX_B 6066 +#define AArch64_WHILEHI_PXX_D 6067 +#define AArch64_WHILEHI_PXX_H 6068 +#define AArch64_WHILEHI_PXX_S 6069 +#define AArch64_WHILEHS_PWW_B 6070 +#define AArch64_WHILEHS_PWW_D 6071 +#define AArch64_WHILEHS_PWW_H 6072 +#define AArch64_WHILEHS_PWW_S 6073 +#define AArch64_WHILEHS_PXX_B 6074 +#define AArch64_WHILEHS_PXX_D 6075 +#define AArch64_WHILEHS_PXX_H 6076 +#define AArch64_WHILEHS_PXX_S 6077 +#define AArch64_WHILELE_PWW_B 6078 +#define AArch64_WHILELE_PWW_D 6079 +#define AArch64_WHILELE_PWW_H 6080 +#define AArch64_WHILELE_PWW_S 6081 +#define AArch64_WHILELE_PXX_B 6082 +#define AArch64_WHILELE_PXX_D 6083 +#define AArch64_WHILELE_PXX_H 6084 +#define AArch64_WHILELE_PXX_S 6085 +#define AArch64_WHILELO_PWW_B 6086 +#define AArch64_WHILELO_PWW_D 6087 +#define AArch64_WHILELO_PWW_H 6088 +#define AArch64_WHILELO_PWW_S 6089 +#define AArch64_WHILELO_PXX_B 6090 +#define AArch64_WHILELO_PXX_D 6091 +#define AArch64_WHILELO_PXX_H 6092 +#define AArch64_WHILELO_PXX_S 6093 +#define AArch64_WHILELS_PWW_B 6094 +#define AArch64_WHILELS_PWW_D 6095 +#define AArch64_WHILELS_PWW_H 6096 +#define AArch64_WHILELS_PWW_S 6097 +#define AArch64_WHILELS_PXX_B 6098 +#define AArch64_WHILELS_PXX_D 6099 +#define AArch64_WHILELS_PXX_H 6100 +#define AArch64_WHILELS_PXX_S 6101 +#define AArch64_WHILELT_PWW_B 6102 +#define AArch64_WHILELT_PWW_D 6103 +#define AArch64_WHILELT_PWW_H 6104 +#define AArch64_WHILELT_PWW_S 6105 +#define AArch64_WHILELT_PXX_B 6106 +#define AArch64_WHILELT_PXX_D 6107 +#define AArch64_WHILELT_PXX_H 6108 +#define AArch64_WHILELT_PXX_S 6109 +#define AArch64_WHILERW_PXX_B 6110 +#define AArch64_WHILERW_PXX_D 6111 +#define AArch64_WHILERW_PXX_H 6112 +#define AArch64_WHILERW_PXX_S 6113 +#define AArch64_WHILEWR_PXX_B 6114 +#define AArch64_WHILEWR_PXX_D 6115 +#define AArch64_WHILEWR_PXX_H 6116 +#define AArch64_WHILEWR_PXX_S 6117 +#define AArch64_WRFFR 6118 +#define AArch64_XAFLAG 6119 +#define AArch64_XAR 6120 +#define AArch64_XAR_ZZZI_B 6121 +#define AArch64_XAR_ZZZI_D 6122 +#define AArch64_XAR_ZZZI_H 6123 +#define AArch64_XAR_ZZZI_S 6124 +#define AArch64_XPACD 6125 +#define AArch64_XPACI 6126 +#define AArch64_XPACLRI 6127 +#define AArch64_XTNv16i8 6128 +#define AArch64_XTNv2i32 6129 +#define AArch64_XTNv4i16 6130 +#define AArch64_XTNv4i32 6131 +#define AArch64_XTNv8i16 6132 +#define AArch64_XTNv8i8 6133 +#define AArch64_ZERO_M 6134 +#define AArch64_ZIP1_PPP_B 6135 +#define AArch64_ZIP1_PPP_D 6136 +#define AArch64_ZIP1_PPP_H 6137 +#define AArch64_ZIP1_PPP_S 6138 +#define AArch64_ZIP1_ZZZ_B 6139 +#define AArch64_ZIP1_ZZZ_D 6140 +#define AArch64_ZIP1_ZZZ_H 6141 +#define AArch64_ZIP1_ZZZ_Q 6142 +#define AArch64_ZIP1_ZZZ_S 6143 +#define AArch64_ZIP1v16i8 6144 +#define AArch64_ZIP1v2i32 6145 +#define AArch64_ZIP1v2i64 6146 +#define AArch64_ZIP1v4i16 6147 +#define AArch64_ZIP1v4i32 6148 +#define AArch64_ZIP1v8i16 6149 +#define AArch64_ZIP1v8i8 6150 +#define AArch64_ZIP2_PPP_B 6151 +#define AArch64_ZIP2_PPP_D 6152 +#define AArch64_ZIP2_PPP_H 6153 +#define AArch64_ZIP2_PPP_S 6154 +#define AArch64_ZIP2_ZZZ_B 6155 +#define AArch64_ZIP2_ZZZ_D 6156 +#define AArch64_ZIP2_ZZZ_H 6157 +#define AArch64_ZIP2_ZZZ_Q 6158 +#define AArch64_ZIP2_ZZZ_S 6159 +#define AArch64_ZIP2v16i8 6160 +#define AArch64_ZIP2v2i32 6161 +#define AArch64_ZIP2v2i64 6162 +#define AArch64_ZIP2v4i16 6163 +#define AArch64_ZIP2v4i32 6164 +#define AArch64_ZIP2v8i16 6165 +#define AArch64_ZIP2v8i8 6166 +#define AArch64_anonymous_13653 6167 +#define AArch64_anonymous_13654 6168 +#define AArch64_anonymous_5364 6169 +#define AArch64_anonymous_5365 6170 +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_REGINFO_EXTRA +#undef GET_REGINFO_EXTRA + + // Register alternate name indices + + enum { + AArch64_NoRegAltName, // 0 + AArch64_vlist1, // 1 + AArch64_vreg, // 2 + AArch64_NUM_TARGET_REG_ALT_NAMES = 3 + }; + +// Subregister indices + +enum { + NoSubRegister, + AArch64_bsub, // 1 + AArch64_dsub, // 2 + AArch64_dsub0, // 3 + AArch64_dsub1, // 4 + AArch64_dsub2, // 5 + AArch64_dsub3, // 6 + AArch64_hsub, // 7 + AArch64_qsub0, // 8 + AArch64_qsub1, // 9 + AArch64_qsub2, // 10 + AArch64_qsub3, // 11 + AArch64_ssub, // 12 + AArch64_sub_32, // 13 + AArch64_sube32, // 14 + AArch64_sube64, // 15 + AArch64_subo32, // 16 + AArch64_subo64, // 17 + AArch64_x8sub_0, // 18 + AArch64_x8sub_1, // 19 + AArch64_x8sub_2, // 20 + AArch64_x8sub_3, // 21 + AArch64_x8sub_4, // 22 + AArch64_x8sub_5, // 23 + AArch64_x8sub_6, // 24 + AArch64_x8sub_7, // 25 + AArch64_zasubb, // 26 + AArch64_zasubd0, // 27 + AArch64_zasubd1, // 28 + AArch64_zasubh0, // 29 + AArch64_zasubh1, // 30 + AArch64_zasubq0, // 31 + AArch64_zasubq1, // 32 + AArch64_zasubs0, // 33 + AArch64_zasubs1, // 34 + AArch64_zsub, // 35 + AArch64_zsub0, // 36 + AArch64_zsub1, // 37 + AArch64_zsub2, // 38 + AArch64_zsub3, // 39 + AArch64_zsub_hi, // 40 + AArch64_zasubd1_then_zasubq0, // 41 + AArch64_zasubd1_then_zasubq1, // 42 + AArch64_zasubs1_then_zasubd0, // 43 + AArch64_zasubs1_then_zasubd1, // 44 + AArch64_zasubs1_then_zasubq0, // 45 + AArch64_zasubs1_then_zasubq1, // 46 + AArch64_zasubs1_then_zasubd1_then_zasubq0, // 47 + AArch64_zasubs1_then_zasubd1_then_zasubq1, // 48 + AArch64_zasubh1_then_zasubd0, // 49 + AArch64_zasubh1_then_zasubd1, // 50 + AArch64_zasubh1_then_zasubq0, // 51 + AArch64_zasubh1_then_zasubq1, // 52 + AArch64_zasubh1_then_zasubs0, // 53 + AArch64_zasubh1_then_zasubs1, // 54 + AArch64_zasubh1_then_zasubd1_then_zasubq0, // 55 + AArch64_zasubh1_then_zasubd1_then_zasubq1, // 56 + AArch64_zasubh1_then_zasubs1_then_zasubd0, // 57 + AArch64_zasubh1_then_zasubs1_then_zasubd1, // 58 + AArch64_zasubh1_then_zasubs1_then_zasubq0, // 59 + AArch64_zasubh1_then_zasubs1_then_zasubq1, // 60 + AArch64_zasubh1_then_zasubs1_then_zasubd1_then_zasubq0, // 61 + AArch64_zasubh1_then_zasubs1_then_zasubd1_then_zasubq1, // 62 + AArch64_dsub1_then_bsub, // 63 + AArch64_dsub1_then_hsub, // 64 + AArch64_dsub1_then_ssub, // 65 + AArch64_dsub3_then_bsub, // 66 + AArch64_dsub3_then_hsub, // 67 + AArch64_dsub3_then_ssub, // 68 + AArch64_dsub2_then_bsub, // 69 + AArch64_dsub2_then_hsub, // 70 + AArch64_dsub2_then_ssub, // 71 + AArch64_qsub1_then_bsub, // 72 + AArch64_qsub1_then_dsub, // 73 + AArch64_qsub1_then_hsub, // 74 + AArch64_qsub1_then_ssub, // 75 + AArch64_qsub3_then_bsub, // 76 + AArch64_qsub3_then_dsub, // 77 + AArch64_qsub3_then_hsub, // 78 + AArch64_qsub3_then_ssub, // 79 + AArch64_qsub2_then_bsub, // 80 + AArch64_qsub2_then_dsub, // 81 + AArch64_qsub2_then_hsub, // 82 + AArch64_qsub2_then_ssub, // 83 + AArch64_x8sub_7_then_sub_32, // 84 + AArch64_x8sub_6_then_sub_32, // 85 + AArch64_x8sub_5_then_sub_32, // 86 + AArch64_x8sub_4_then_sub_32, // 87 + AArch64_x8sub_3_then_sub_32, // 88 + AArch64_x8sub_2_then_sub_32, // 89 + AArch64_x8sub_1_then_sub_32, // 90 + AArch64_subo64_then_sub_32, // 91 + AArch64_zsub1_then_bsub, // 92 + AArch64_zsub1_then_dsub, // 93 + AArch64_zsub1_then_hsub, // 94 + AArch64_zsub1_then_ssub, // 95 + AArch64_zsub1_then_zsub, // 96 + AArch64_zsub1_then_zsub_hi, // 97 + AArch64_zsub3_then_bsub, // 98 + AArch64_zsub3_then_dsub, // 99 + AArch64_zsub3_then_hsub, // 100 + AArch64_zsub3_then_ssub, // 101 + AArch64_zsub3_then_zsub, // 102 + AArch64_zsub3_then_zsub_hi, // 103 + AArch64_zsub2_then_bsub, // 104 + AArch64_zsub2_then_dsub, // 105 + AArch64_zsub2_then_hsub, // 106 + AArch64_zsub2_then_ssub, // 107 + AArch64_zsub2_then_zsub, // 108 + AArch64_zsub2_then_zsub_hi, // 109 + AArch64_dsub0_dsub1, // 110 + AArch64_dsub0_dsub1_dsub2, // 111 + AArch64_dsub1_dsub2, // 112 + AArch64_dsub1_dsub2_dsub3, // 113 + AArch64_dsub2_dsub3, // 114 + AArch64_dsub_qsub1_then_dsub, // 115 + AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 116 + AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub, // 117 + AArch64_qsub0_qsub1, // 118 + AArch64_qsub0_qsub1_qsub2, // 119 + AArch64_qsub1_qsub2, // 120 + AArch64_qsub1_qsub2_qsub3, // 121 + AArch64_qsub2_qsub3, // 122 + AArch64_qsub1_then_dsub_qsub2_then_dsub, // 123 + AArch64_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 124 + AArch64_qsub2_then_dsub_qsub3_then_dsub, // 125 + AArch64_sub_32_x8sub_1_then_sub_32, // 126 + AArch64_x8sub_0_x8sub_1, // 127 + AArch64_x8sub_2_x8sub_3, // 128 + AArch64_x8sub_4_x8sub_5, // 129 + AArch64_x8sub_6_x8sub_7, // 130 + AArch64_x8sub_6_then_sub_32_x8sub_7_then_sub_32, // 131 + AArch64_x8sub_4_then_sub_32_x8sub_5_then_sub_32, // 132 + AArch64_x8sub_2_then_sub_32_x8sub_3_then_sub_32, // 133 + AArch64_sub_32_subo64_then_sub_32, // 134 + AArch64_dsub_zsub1_then_dsub, // 135 + AArch64_zsub_zsub1_then_zsub, // 136 + AArch64_dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 137 + AArch64_dsub_zsub1_then_dsub_zsub2_then_dsub, // 138 + AArch64_zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 139 + AArch64_zsub_zsub1_then_zsub_zsub2_then_zsub, // 140 + AArch64_zsub0_zsub1, // 141 + AArch64_zsub0_zsub1_zsub2, // 142 + AArch64_zsub1_zsub2, // 143 + AArch64_zsub1_zsub2_zsub3, // 144 + AArch64_zsub2_zsub3, // 145 + AArch64_zsub1_then_dsub_zsub2_then_dsub, // 146 + AArch64_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 147 + AArch64_zsub1_then_zsub_zsub2_then_zsub, // 148 + AArch64_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 149 + AArch64_zsub2_then_dsub_zsub3_then_dsub, // 150 + AArch64_zsub2_then_zsub_zsub3_then_zsub, // 151 + AArch64_NUM_TARGET_SUBREGS +}; +#endif // GET_REGINFO_EXTRA + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg AArch64RegDiffLists[] = { + /* 0 */ 7, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 17 */ 63239, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 26 */ 64537, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 35 */ 1, + 92, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 44 */ 64949, + 1, + 1, + 1, + 74, + 1, + 1, + 1, + 0, + /* 53 */ 63083, + 1, + 1, + 1, + 0, + /* 58 */ 63095, + 1, + 1, + 1, + 0, + /* 63 */ 65089, + 1, + 1, + 1, + 0, + /* 68 */ 65185, + 1, + 1, + 1, + 0, + /* 73 */ 31, + 318, + 17, + 65504, + 1, + 1, + 1, + 0, + /* 81 */ 31, + 319, + 17, + 65504, + 1, + 1, + 1, + 0, + /* 89 */ 31, + 320, + 17, + 65504, + 1, + 1, + 1, + 0, + /* 97 */ 31, + 321, + 17, + 65504, + 1, + 1, + 1, + 0, + /* 105 */ 31, + 322, + 17, + 65504, + 1, + 1, + 1, + 0, + /* 113 */ 31, + 323, + 17, + 65504, + 1, + 1, + 1, + 0, + /* 121 */ 31, + 324, + 17, + 65504, + 1, + 1, + 1, + 0, + /* 129 */ 31, + 325, + 17, + 65504, + 1, + 1, + 1, + 0, + /* 137 */ 31, + 326, + 17, + 65504, + 1, + 1, + 1, + 0, + /* 145 */ 335, + 65504, + 1, + 1, + 1, + 0, + /* 151 */ 336, + 65504, + 1, + 1, + 1, + 0, + /* 157 */ 337, + 65504, + 1, + 1, + 1, + 0, + /* 163 */ 338, + 65504, + 1, + 1, + 1, + 0, + /* 169 */ 339, + 65504, + 1, + 1, + 1, + 0, + /* 175 */ 340, + 65504, + 1, + 1, + 1, + 0, + /* 181 */ 341, + 65504, + 1, + 1, + 1, + 0, + /* 187 */ 342, + 65504, + 1, + 1, + 1, + 0, + /* 193 */ 343, + 65504, + 1, + 1, + 1, + 0, + /* 199 */ 31, + 317, + 17, + 65495, + 9, + 1, + 1, + 0, + /* 207 */ 31, + 318, + 17, + 65495, + 9, + 1, + 1, + 0, + /* 215 */ 334, + 65495, + 9, + 1, + 1, + 0, + /* 221 */ 335, + 65495, + 9, + 1, + 1, + 0, + /* 227 */ 23, + 29, + 1, + 1, + 0, + /* 232 */ 23, + 29, + 1, + 1, + 46, + 29, + 1, + 1, + 0, + /* 241 */ 64917, + 1, + 1, + 75, + 1, + 1, + 0, + /* 248 */ 65057, + 1, + 1, + 0, + /* 252 */ 65153, + 1, + 1, + 0, + /* 256 */ 31, + 326, + 17, + 65505, + 1, + 1, + 0, + /* 263 */ 31, + 327, + 17, + 65505, + 1, + 1, + 0, + /* 270 */ 343, + 65505, + 1, + 1, + 0, + /* 275 */ 344, + 65505, + 1, + 1, + 0, + /* 280 */ 31, + 316, + 17, + 65494, + 10, + 1, + 0, + /* 287 */ 31, + 317, + 17, + 65494, + 10, + 1, + 0, + /* 294 */ 333, + 65494, + 10, + 1, + 0, + /* 299 */ 334, + 65494, + 10, + 1, + 0, + /* 304 */ 23, + 1, + 29, + 1, + 0, + /* 309 */ 23, + 1, + 29, + 1, + 46, + 1, + 29, + 1, + 0, + /* 318 */ 23, + 30, + 1, + 0, + /* 322 */ 23, + 30, + 1, + 46, + 30, + 1, + 0, + /* 329 */ 64981, + 1, + 76, + 1, + 0, + /* 334 */ 65173, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 329, + 1, + 0, + /* 349 */ 65173, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 1, + 112, + 65456, + 65472, + 361, + 1, + 0, + /* 364 */ 63261, + 1, + 0, + /* 367 */ 63273, + 1, + 0, + /* 370 */ 63291, + 1, + 0, + /* 373 */ 63303, + 1, + 0, + /* 376 */ 64479, + 1, + 0, + /* 379 */ 64513, + 1, + 0, + /* 382 */ 65121, + 1, + 0, + /* 385 */ 65176, + 1, + 0, + /* 388 */ 65177, + 1, + 0, + /* 391 */ 65178, + 1, + 0, + /* 394 */ 65179, + 1, + 0, + /* 397 */ 65180, + 1, + 0, + /* 400 */ 65181, + 1, + 0, + /* 403 */ 65182, + 1, + 0, + /* 406 */ 65183, + 1, + 0, + /* 409 */ 65184, + 1, + 0, + /* 412 */ 65185, + 1, + 0, + /* 415 */ 65186, + 1, + 0, + /* 418 */ 65187, + 1, + 0, + /* 421 */ 65188, + 1, + 0, + /* 424 */ 65189, + 1, + 0, + /* 427 */ 65190, + 1, + 0, + /* 430 */ 65217, + 1, + 0, + /* 433 */ 64, + 80, + 65424, + 80, + 124, + 94, + 1, + 62, + 65503, + 34, + 65503, + 34, + 65503, + 1, + 63, + 1, + 62, + 65503, + 34, + 65503, + 34, + 65503, + 1, + 107, + 1, + 62, + 65503, + 34, + 65503, + 34, + 65503, + 1, + 0, + /* 466 */ 124, + 190, + 1, + 62, + 65503, + 34, + 65503, + 34, + 65503, + 1, + 107, + 1, + 62, + 65503, + 34, + 65503, + 34, + 65503, + 1, + 0, + /* 486 */ 65473, + 330, + 1, + 62, + 65503, + 34, + 65503, + 34, + 65503, + 1, + 0, + /* 497 */ 64, + 80, + 65424, + 80, + 124, + 95, + 31, + 33, + 65504, + 62, + 65503, + 34, + 65503, + 1, + 33, + 31, + 33, + 65504, + 62, + 65503, + 34, + 65503, + 1, + 77, + 31, + 33, + 65504, + 62, + 65503, + 34, + 65503, + 1, + 0, + /* 530 */ 124, + 191, + 31, + 33, + 65504, + 62, + 65503, + 34, + 65503, + 1, + 77, + 31, + 33, + 65504, + 62, + 65503, + 34, + 65503, + 1, + 0, + /* 550 */ 65473, + 331, + 31, + 33, + 65504, + 62, + 65503, + 34, + 65503, + 1, + 0, + /* 561 */ 63, + 65503, + 34, + 65503, + 1, + 64, + 63, + 65503, + 34, + 65503, + 1, + 108, + 63, + 65503, + 34, + 65503, + 1, + 0, + /* 579 */ 64, + 80, + 65424, + 80, + 124, + 94, + 1, + 63, + 1, + 65503, + 1, + 62, + 65503, + 1, + 33, + 1, + 63, + 1, + 65503, + 1, + 62, + 65503, + 1, + 77, + 1, + 63, + 1, + 65503, + 1, + 62, + 65503, + 1, + 0, + /* 612 */ 124, + 190, + 1, + 63, + 1, + 65503, + 1, + 62, + 65503, + 1, + 77, + 1, + 63, + 1, + 65503, + 1, + 62, + 65503, + 1, + 0, + /* 632 */ 65473, + 330, + 1, + 63, + 1, + 65503, + 1, + 62, + 65503, + 1, + 0, + /* 643 */ 64, + 65504, + 63, + 65503, + 1, + 33, + 64, + 65504, + 63, + 65503, + 1, + 77, + 64, + 65504, + 63, + 65503, + 1, + 0, + /* 661 */ 65503, + 1, + 128, + 65503, + 1, + 172, + 65503, + 1, + 0, + /* 670 */ 31, + 327, + 17, + 65506, + 1, + 0, + /* 676 */ 31, + 328, + 17, + 65506, + 1, + 0, + /* 682 */ 344, + 65506, + 1, + 0, + /* 686 */ 345, + 65506, + 1, + 0, + /* 690 */ 2, + 0, + /* 692 */ 2, + 4, + 0, + /* 695 */ 64976, + 4, + 0, + /* 698 */ 6, + 0, + /* 700 */ 269, + 9, + 18, + 65510, + 10, + 8, + 65522, + 10, + 8, + 6, + 65510, + 10, + 8, + 65522, + 10, + 8, + 65521, + 18, + 65510, + 10, + 8, + 65522, + 10, + 8, + 6, + 65510, + 10, + 8, + 65522, + 10, + 8, + 0, + /* 732 */ 31, + 315, + 17, + 65493, + 11, + 0, + /* 738 */ 31, + 316, + 17, + 65493, + 11, + 0, + /* 744 */ 332, + 65493, + 11, + 0, + /* 748 */ 333, + 65493, + 11, + 0, + /* 752 */ 12, + 0, + /* 754 */ 1, + 537, + 16, + 0, + /* 758 */ 65322, + 543, + 16, + 0, + /* 762 */ 23, + 1, + 1, + 29, + 0, + /* 767 */ 23, + 1, + 1, + 29, + 46, + 1, + 1, + 29, + 0, + /* 776 */ 64, + 80, + 65424, + 80, + 124, + 94, + 1, + 62, + 1, + 65503, + 34, + 65503, + 1, + 29, + 34, + 1, + 62, + 1, + 65503, + 34, + 65503, + 1, + 29, + 78, + 1, + 62, + 1, + 65503, + 34, + 65503, + 1, + 29, + 0, + /* 809 */ 124, + 190, + 1, + 62, + 1, + 65503, + 34, + 65503, + 1, + 29, + 78, + 1, + 62, + 1, + 65503, + 34, + 65503, + 1, + 29, + 0, + /* 829 */ 65473, + 330, + 1, + 62, + 1, + 65503, + 34, + 65503, + 1, + 29, + 0, + /* 840 */ 23, + 1, + 30, + 0, + /* 844 */ 23, + 1, + 30, + 46, + 1, + 30, + 0, + /* 851 */ 63, + 1, + 65503, + 1, + 30, + 34, + 63, + 1, + 65503, + 1, + 30, + 78, + 63, + 1, + 65503, + 1, + 30, + 0, + /* 869 */ 23, + 31, + 0, + /* 872 */ 23, + 31, + 46, + 31, + 0, + /* 877 */ 65504, + 31, + 97, + 65504, + 31, + 141, + 65504, + 31, + 0, + /* 886 */ 65312, + 77, + 0, + /* 889 */ 65205, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 31, + 96, + 0, + /* 906 */ 65205, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65442, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 63, + 96, + 0, + /* 923 */ 65141, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 30, + 96, + 65504, + 96, + 76, + 1, + 65300, + 96, + 0, + /* 953 */ 65141, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65442, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 62, + 96, + 65504, + 96, + 76, + 1, + 65300, + 96, + 0, + /* 983 */ 65141, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65442, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 62, + 96, + 65504, + 96, + 76, + 65505, + 65300, + 96, + 0, + /* 1013 */ 65173, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65442, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 61, + 96, + 65472, + 32, + 64, + 32, + 76, + 64, + 65473, + 64, + 65441, + 65331, + 64, + 32, + 64, + 65345, + 96, + 0, + /* 1059 */ 65173, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65442, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 61, + 96, + 65472, + 32, + 64, + 32, + 76, + 64, + 65441, + 64, + 65473, + 65299, + 64, + 32, + 64, + 65377, + 96, + 0, + /* 1105 */ 65173, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 29, + 96, + 65472, + 32, + 64, + 32, + 76, + 64, + 65473, + 64, + 65473, + 65299, + 64, + 32, + 64, + 65377, + 96, + 0, + /* 1151 */ 65173, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65474, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 65442, + 65412, + 65456, + 112, + 65456, + 65472, + 299, + 61, + 96, + 65472, + 32, + 64, + 32, + 76, + 64, + 65473, + 64, + 65473, + 65299, + 64, + 32, + 64, + 65377, + 96, + 0, + /* 1197 */ 1, + 98, + 0, + /* 1200 */ 64976, + 98, + 0, + /* 1203 */ 96, + 140, + 0, + /* 1206 */ 214, + 0, + /* 1208 */ 65412, + 65456, + 112, + 65456, + 65472, + 299, + 0, + /* 1215 */ 65221, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 330, + 0, + /* 1227 */ 65219, + 65505, + 65323, + 214, + 345, + 0, + /* 1233 */ 65203, + 65505, + 32, + 65505, + 346, + 0, + /* 1239 */ 65202, + 65505, + 32, + 65505, + 347, + 0, + /* 1245 */ 65201, + 65505, + 32, + 65505, + 348, + 0, + /* 1251 */ 65200, + 65505, + 32, + 65505, + 349, + 0, + /* 1257 */ 65199, + 65505, + 32, + 65505, + 350, + 0, + /* 1263 */ 65198, + 65505, + 32, + 65505, + 351, + 0, + /* 1269 */ 65197, + 65505, + 32, + 65505, + 352, + 0, + /* 1275 */ 65196, + 65505, + 32, + 65505, + 353, + 0, + /* 1281 */ 65195, + 65505, + 32, + 65505, + 354, + 0, + /* 1287 */ 65194, + 65505, + 32, + 65505, + 355, + 0, + /* 1293 */ 65193, + 65505, + 32, + 65505, + 356, + 0, + /* 1299 */ 65192, + 65505, + 32, + 65505, + 357, + 0, + /* 1305 */ 65191, + 65505, + 32, + 65505, + 358, + 0, + /* 1311 */ 65190, + 65505, + 32, + 65505, + 359, + 0, + /* 1317 */ 65221, + 65456, + 112, + 65456, + 65472, + 81, + 65456, + 112, + 65456, + 65472, + 362, + 0, + /* 1329 */ 64977, + 214, + 65328, + 65535, + 538, + 0, + /* 1335 */ 553, + 0, + /* 1337 */ 559, + 0, + /* 1339 */ 63118, + 0, + /* 1341 */ 63130, + 0, + /* 1343 */ 63148, + 0, + /* 1345 */ 63160, + 0, + /* 1347 */ 63181, + 0, + /* 1349 */ 63193, + 0, + /* 1351 */ 63211, + 0, + /* 1353 */ 63223, + 0, + /* 1355 */ 65518, + 22, + 65516, + 65526, + 65267, + 0, + /* 1361 */ 65526, + 22, + 65516, + 65526, + 65267, + 0, + /* 1367 */ 65518, + 26, + 65516, + 65526, + 65267, + 0, + /* 1373 */ 65526, + 26, + 65516, + 65526, + 65267, + 0, + /* 1379 */ 65518, + 22, + 65518, + 65526, + 65267, + 0, + /* 1385 */ 65526, + 22, + 65518, + 65526, + 65267, + 0, + /* 1391 */ 65518, + 26, + 65518, + 65526, + 65267, + 0, + /* 1397 */ 65526, + 26, + 65518, + 65526, + 65267, + 0, + /* 1403 */ 65518, + 22, + 65516, + 65527, + 65267, + 0, + /* 1409 */ 65526, + 22, + 65516, + 65527, + 65267, + 0, + /* 1415 */ 65518, + 26, + 65516, + 65527, + 65267, + 0, + /* 1421 */ 65526, + 26, + 65516, + 65527, + 65267, + 0, + /* 1427 */ 65518, + 22, + 65518, + 65527, + 65267, + 0, + /* 1433 */ 65526, + 22, + 65518, + 65527, + 65267, + 0, + /* 1439 */ 65518, + 26, + 65518, + 65527, + 65267, + 0, + /* 1445 */ 65526, + 26, + 65518, + 65527, + 65267, + 0, + /* 1451 */ 65321, + 0, + /* 1453 */ 65326, + 0, + /* 1455 */ 65207, + 65327, + 0, + /* 1458 */ 65389, + 0, + /* 1460 */ 65404, + 0, + /* 1462 */ 65420, + 0, + /* 1464 */ 65436, + 0, + /* 1466 */ 65157, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 329, + 64, + 32, + 1, + 65440, + 0, + /* 1487 */ 65157, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 81, + 65456, + 112, + 65456, + 65472, + 361, + 64, + 32, + 1, + 65440, + 0, + /* 1508 */ 65157, + 65456, + 112, + 65456, + 65472, + 81, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 361, + 64, + 32, + 65505, + 65440, + 0, + /* 1529 */ 65189, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 81, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 360, + 32, + 32, + 32, + 64, + 65473, + 64, + 65441, + 65471, + 64, + 65441, + 0, + /* 1561 */ 65205, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 1, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 360, + 64, + 65473, + 64, + 65441, + 0, + /* 1583 */ 65237, + 112, + 65456, + 65472, + 1, + 112, + 65456, + 65472, + 0, + /* 1592 */ 65237, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 0, + /* 1601 */ 65456, + 112, + 65456, + 65472, + 0, + /* 1606 */ 65189, + 65456, + 112, + 65456, + 65472, + 81, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 360, + 32, + 32, + 32, + 64, + 65441, + 64, + 65473, + 65439, + 64, + 65473, + 0, + /* 1638 */ 65189, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 328, + 32, + 32, + 32, + 64, + 65473, + 64, + 65473, + 65439, + 64, + 65473, + 0, + /* 1670 */ 65189, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 113, + 65456, + 112, + 65456, + 65472, + 81, + 65456, + 112, + 65456, + 65472, + 360, + 32, + 32, + 32, + 64, + 65473, + 64, + 65473, + 65439, + 64, + 65473, + 0, + /* 1702 */ 65205, + 112, + 65456, + 65472, + 1, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 360, + 64, + 65441, + 64, + 65473, + 0, + /* 1724 */ 65205, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 328, + 64, + 65473, + 64, + 65473, + 0, + /* 1746 */ 65205, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 1, + 112, + 65456, + 65472, + 360, + 64, + 65473, + 64, + 65473, + 0, + /* 1768 */ 65484, + 0, + /* 1770 */ 65173, + 112, + 65456, + 65472, + 1, + 112, + 65456, + 65472, + 33, + 112, + 65456, + 65472, + 361, + 65505, + 0, + /* 1785 */ 31, + 315, + 2, + 65507, + 0, + /* 1790 */ 65322, + 559, + 2, + 65507, + 0, + /* 1795 */ 31, + 328, + 17, + 65507, + 0, + /* 1800 */ 31, + 329, + 17, + 65507, + 0, + /* 1805 */ 317, + 65507, + 0, + /* 1808 */ 345, + 65507, + 0, + /* 1811 */ 346, + 65507, + 0, + /* 1814 */ 561, + 65507, + 0, + /* 1817 */ 65516, + 0, + /* 1819 */ 65526, + 0, + /* 1821 */ 65534, + 0, + /* 1823 */ 65229, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 343, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 1848 */ 65228, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 344, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 1873 */ 65227, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 345, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 1898 */ 65226, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 346, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 1923 */ 65225, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 347, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 1948 */ 65224, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 348, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 1973 */ 65223, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 349, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 1998 */ 65222, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 350, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 2023 */ 65221, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 351, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 2048 */ 65220, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 352, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 2073 */ 65219, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 353, + 17, + 1, + 1, + 1, + 65519, + 65535, + 65535, + 0, + /* 2098 */ 65242, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 32, + 65505, + 65323, + 214, + 342, + 17, + 1, + 1, + 65522, + 65534, + 65535, + 65535, + 0, +}; + +static const uint16_t AArch64SubRegIdxLists[] = { + /* 0 */ 2, + 12, + 7, + 1, + 0, + /* 5 */ 13, + 0, + /* 7 */ 14, + 16, + 0, + /* 10 */ 31, + 32, + 0, + /* 13 */ 35, + 2, + 12, + 7, + 1, + 40, + 0, + /* 20 */ 27, + 31, + 32, + 28, + 41, + 42, + 0, + /* 27 */ 33, + 27, + 31, + 32, + 28, + 41, + 42, + 34, + 43, + 45, + 46, + 44, + 47, + 48, + 0, + /* 42 */ 26, + 29, + 33, + 27, + 31, + 32, + 28, + 41, + 42, + 34, + 43, + 45, + 46, + 44, + 47, + 48, + 30, + 53, + 49, + 51, + 52, + 50, + 55, + 56, + 54, + 57, + 59, + 60, + 58, + 61, + 62, + 0, + /* 74 */ 3, + 12, + 7, + 1, + 4, + 65, + 64, + 63, + 0, + /* 83 */ 3, + 12, + 7, + 1, + 4, + 65, + 64, + 63, + 5, + 71, + 70, + 69, + 110, + 112, + 0, + /* 98 */ 3, + 12, + 7, + 1, + 4, + 65, + 64, + 63, + 5, + 71, + 70, + 69, + 6, + 68, + 67, + 66, + 110, + 111, + 112, + 113, + 114, + 0, + /* 120 */ 8, + 2, + 12, + 7, + 1, + 9, + 73, + 75, + 74, + 72, + 115, + 0, + /* 132 */ 8, + 2, + 12, + 7, + 1, + 9, + 73, + 75, + 74, + 72, + 10, + 81, + 83, + 82, + 80, + 115, + 117, + 118, + 120, + 123, + 0, + /* 153 */ 8, + 2, + 12, + 7, + 1, + 9, + 73, + 75, + 74, + 72, + 10, + 81, + 83, + 82, + 80, + 11, + 77, + 79, + 78, + 76, + 115, + 116, + 117, + 118, + 119, + 120, + 121, + 122, + 123, + 124, + 125, + 0, + /* 185 */ 18, + 13, + 19, + 90, + 20, + 89, + 21, + 88, + 22, + 87, + 23, + 86, + 24, + 85, + 25, + 84, + 126, + 127, + 128, + 129, + 130, + 131, + 132, + 133, + 0, + /* 210 */ 15, + 13, + 17, + 91, + 134, + 0, + /* 216 */ 36, + 35, + 2, + 12, + 7, + 1, + 40, + 37, + 96, + 93, + 95, + 94, + 92, + 97, + 135, + 136, + 0, + /* 233 */ 36, + 35, + 2, + 12, + 7, + 1, + 40, + 37, + 96, + 93, + 95, + 94, + 92, + 97, + 38, + 108, + 105, + 107, + 106, + 104, + 109, + 135, + 136, + 138, + 140, + 141, + 143, + 146, + 148, + 0, + /* 263 */ 36, + 35, + 2, + 12, + 7, + 1, + 40, + 37, + 96, + 93, + 95, + 94, + 92, + 97, + 38, + 108, + 105, + 107, + 106, + 104, + 109, + 39, + 102, + 99, + 101, + 100, + 98, + 103, + 135, + 136, + 137, + 138, + 139, + 140, + 141, + 142, + 143, + 144, + 145, + 146, + 147, + 148, + 149, + 150, + 151, + 0, +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char AArch64RegStrings[] = { + /* 0 */ "B10\0" + /* 4 */ "D7_D8_D9_D10\0" + /* 17 */ "H10\0" + /* 21 */ "P10\0" + /* 25 */ "ZAQ10\0" + /* 31 */ "Q7_Q8_Q9_Q10\0" + /* 44 */ "S10\0" + /* 48 */ "W10\0" + /* 52 */ "X10\0" + /* 56 */ "Z7_Z8_Z9_Z10\0" + /* 69 */ "B20\0" + /* 73 */ "D17_D18_D19_D20\0" + /* 89 */ "H20\0" + /* 93 */ "Q17_Q18_Q19_Q20\0" + /* 109 */ "S20\0" + /* 113 */ "W20\0" + /* 117 */ "X20\0" + /* 121 */ "Z17_Z18_Z19_Z20\0" + /* 137 */ "B30\0" + /* 141 */ "D27_D28_D29_D30\0" + /* 157 */ "H30\0" + /* 161 */ "Q27_Q28_Q29_Q30\0" + /* 177 */ "S30\0" + /* 181 */ "W30\0" + /* 185 */ "Z27_Z28_Z29_Z30\0" + /* 201 */ "ZAB0\0" + /* 206 */ "ZAD0\0" + /* 211 */ "D29_D30_D31_D0\0" + /* 226 */ "ZAH0\0" + /* 231 */ "P0\0" + /* 234 */ "ZAQ0\0" + /* 239 */ "Q29_Q30_Q31_Q0\0" + /* 254 */ "ZAS0\0" + /* 259 */ "W0\0" + /* 262 */ "X0\0" + /* 265 */ "Z29_Z30_Z31_Z0\0" + /* 280 */ "B11\0" + /* 284 */ "D8_D9_D10_D11\0" + /* 298 */ "H11\0" + /* 302 */ "P11\0" + /* 306 */ "ZAQ11\0" + /* 312 */ "Q8_Q9_Q10_Q11\0" + /* 326 */ "S11\0" + /* 330 */ "W10_W11\0" + /* 338 */ "X4_X5_X6_X7_X8_X9_X10_X11\0" + /* 364 */ "Z8_Z9_Z10_Z11\0" + /* 378 */ "B21\0" + /* 382 */ "D18_D19_D20_D21\0" + /* 398 */ "H21\0" + /* 402 */ "Q18_Q19_Q20_Q21\0" + /* 418 */ "S21\0" + /* 422 */ "W20_W21\0" + /* 430 */ "X14_X15_X16_X17_X18_X19_X20_X21\0" + /* 462 */ "Z18_Z19_Z20_Z21\0" + /* 478 */ "B31\0" + /* 482 */ "D28_D29_D30_D31\0" + /* 498 */ "H31\0" + /* 502 */ "Q28_Q29_Q30_Q31\0" + /* 518 */ "S31\0" + /* 522 */ "Z28_Z29_Z30_Z31\0" + /* 538 */ "B1\0" + /* 541 */ "ZAD1\0" + /* 546 */ "D30_D31_D0_D1\0" + /* 560 */ "ZAH1\0" + /* 565 */ "P1\0" + /* 568 */ "ZAQ1\0" + /* 573 */ "Q30_Q31_Q0_Q1\0" + /* 587 */ "ZAS1\0" + /* 592 */ "W0_W1\0" + /* 598 */ "X0_X1\0" + /* 604 */ "Z30_Z31_Z0_Z1\0" + /* 618 */ "B12\0" + /* 622 */ "D9_D10_D11_D12\0" + /* 637 */ "H12\0" + /* 641 */ "P12\0" + /* 645 */ "ZAQ12\0" + /* 651 */ "Q9_Q10_Q11_Q12\0" + /* 666 */ "S12\0" + /* 670 */ "W12\0" + /* 674 */ "X12\0" + /* 678 */ "Z9_Z10_Z11_Z12\0" + /* 693 */ "B22\0" + /* 697 */ "D19_D20_D21_D22\0" + /* 713 */ "H22\0" + /* 717 */ "Q19_Q20_Q21_Q22\0" + /* 733 */ "S22\0" + /* 737 */ "W22\0" + /* 741 */ "X22\0" + /* 745 */ "Z19_Z20_Z21_Z22\0" + /* 761 */ "B2\0" + /* 764 */ "ZAD2\0" + /* 769 */ "D31_D0_D1_D2\0" + /* 782 */ "H2\0" + /* 785 */ "P2\0" + /* 788 */ "ZAQ2\0" + /* 793 */ "Q31_Q0_Q1_Q2\0" + /* 806 */ "ZAS2\0" + /* 811 */ "W2\0" + /* 814 */ "X2\0" + /* 817 */ "Z31_Z0_Z1_Z2\0" + /* 830 */ "B13\0" + /* 834 */ "D10_D11_D12_D13\0" + /* 850 */ "H13\0" + /* 854 */ "P13\0" + /* 858 */ "ZAQ13\0" + /* 864 */ "Q10_Q11_Q12_Q13\0" + /* 880 */ "S13\0" + /* 884 */ "W12_W13\0" + /* 892 */ "X6_X7_X8_X9_X10_X11_X12_X13\0" + /* 920 */ "Z10_Z11_Z12_Z13\0" + /* 936 */ "B23\0" + /* 940 */ "D20_D21_D22_D23\0" + /* 956 */ "H23\0" + /* 960 */ "Q20_Q21_Q22_Q23\0" + /* 976 */ "S23\0" + /* 980 */ "W22_W23\0" + /* 988 */ "X16_X17_X18_X19_X20_X21_X22_X23\0" + /* 1020 */ "Z20_Z21_Z22_Z23\0" + /* 1036 */ "B3\0" + /* 1039 */ "ZAD3\0" + /* 1044 */ "D0_D1_D2_D3\0" + /* 1056 */ "H3\0" + /* 1059 */ "P3\0" + /* 1062 */ "ZAQ3\0" + /* 1067 */ "Q0_Q1_Q2_Q3\0" + /* 1079 */ "ZAS3\0" + /* 1084 */ "W2_W3\0" + /* 1090 */ "X2_X3\0" + /* 1096 */ "Z0_Z1_Z2_Z3\0" + /* 1108 */ "B14\0" + /* 1112 */ "D11_D12_D13_D14\0" + /* 1128 */ "H14\0" + /* 1132 */ "P14\0" + /* 1136 */ "ZAQ14\0" + /* 1142 */ "Q11_Q12_Q13_Q14\0" + /* 1158 */ "S14\0" + /* 1162 */ "W14\0" + /* 1166 */ "X14\0" + /* 1170 */ "Z11_Z12_Z13_Z14\0" + /* 1186 */ "B24\0" + /* 1190 */ "D21_D22_D23_D24\0" + /* 1206 */ "H24\0" + /* 1210 */ "Q21_Q22_Q23_Q24\0" + /* 1226 */ "S24\0" + /* 1230 */ "W24\0" + /* 1234 */ "X24\0" + /* 1238 */ "Z21_Z22_Z23_Z24\0" + /* 1254 */ "B4\0" + /* 1257 */ "ZAD4\0" + /* 1262 */ "D1_D2_D3_D4\0" + /* 1274 */ "H4\0" + /* 1277 */ "P4\0" + /* 1280 */ "ZAQ4\0" + /* 1285 */ "Q1_Q2_Q3_Q4\0" + /* 1297 */ "S4\0" + /* 1300 */ "W4\0" + /* 1303 */ "X4\0" + /* 1306 */ "Z1_Z2_Z3_Z4\0" + /* 1318 */ "B15\0" + /* 1322 */ "D12_D13_D14_D15\0" + /* 1338 */ "H15\0" + /* 1342 */ "P15\0" + /* 1346 */ "ZAQ15\0" + /* 1352 */ "Q12_Q13_Q14_Q15\0" + /* 1368 */ "S15\0" + /* 1372 */ "W14_W15\0" + /* 1380 */ "X8_X9_X10_X11_X12_X13_X14_X15\0" + /* 1410 */ "Z12_Z13_Z14_Z15\0" + /* 1426 */ "B25\0" + /* 1430 */ "D22_D23_D24_D25\0" + /* 1446 */ "H25\0" + /* 1450 */ "Q22_Q23_Q24_Q25\0" + /* 1466 */ "S25\0" + /* 1470 */ "W24_W25\0" + /* 1478 */ "X18_X19_X20_X21_X22_X23_X24_X25\0" + /* 1510 */ "Z22_Z23_Z24_Z25\0" + /* 1526 */ "B5\0" + /* 1529 */ "ZAD5\0" + /* 1534 */ "D2_D3_D4_D5\0" + /* 1546 */ "H5\0" + /* 1549 */ "P5\0" + /* 1552 */ "ZAQ5\0" + /* 1557 */ "Q2_Q3_Q4_Q5\0" + /* 1569 */ "S5\0" + /* 1572 */ "W4_W5\0" + /* 1578 */ "X4_X5\0" + /* 1584 */ "Z2_Z3_Z4_Z5\0" + /* 1596 */ "B16\0" + /* 1600 */ "D13_D14_D15_D16\0" + /* 1616 */ "H16\0" + /* 1620 */ "Q13_Q14_Q15_Q16\0" + /* 1636 */ "S16\0" + /* 1640 */ "W16\0" + /* 1644 */ "X16\0" + /* 1648 */ "Z13_Z14_Z15_Z16\0" + /* 1664 */ "B26\0" + /* 1668 */ "D23_D24_D25_D26\0" + /* 1684 */ "H26\0" + /* 1688 */ "Q23_Q24_Q25_Q26\0" + /* 1704 */ "S26\0" + /* 1708 */ "W26\0" + /* 1712 */ "X26\0" + /* 1716 */ "Z23_Z24_Z25_Z26\0" + /* 1732 */ "B6\0" + /* 1735 */ "ZAD6\0" + /* 1740 */ "D3_D4_D5_D6\0" + /* 1752 */ "H6\0" + /* 1755 */ "P6\0" + /* 1758 */ "ZAQ6\0" + /* 1763 */ "Q3_Q4_Q5_Q6\0" + /* 1775 */ "S6\0" + /* 1778 */ "W6\0" + /* 1781 */ "X6\0" + /* 1784 */ "Z3_Z4_Z5_Z6\0" + /* 1796 */ "B17\0" + /* 1800 */ "D14_D15_D16_D17\0" + /* 1816 */ "H17\0" + /* 1820 */ "Q14_Q15_Q16_Q17\0" + /* 1836 */ "S17\0" + /* 1840 */ "W16_W17\0" + /* 1848 */ "X10_X11_X12_X13_X14_X15_X16_X17\0" + /* 1880 */ "Z14_Z15_Z16_Z17\0" + /* 1896 */ "B27\0" + /* 1900 */ "D24_D25_D26_D27\0" + /* 1916 */ "H27\0" + /* 1920 */ "Q24_Q25_Q26_Q27\0" + /* 1936 */ "S27\0" + /* 1940 */ "W26_W27\0" + /* 1948 */ "X20_X21_X22_X23_X24_X25_X26_X27\0" + /* 1980 */ "Z24_Z25_Z26_Z27\0" + /* 1996 */ "B7\0" + /* 1999 */ "ZAD7\0" + /* 2004 */ "D4_D5_D6_D7\0" + /* 2016 */ "H7\0" + /* 2019 */ "P7\0" + /* 2022 */ "ZAQ7\0" + /* 2027 */ "Q4_Q5_Q6_Q7\0" + /* 2039 */ "S7\0" + /* 2042 */ "W6_W7\0" + /* 2048 */ "X0_X1_X2_X3_X4_X5_X6_X7\0" + /* 2072 */ "Z4_Z5_Z6_Z7\0" + /* 2084 */ "B18\0" + /* 2088 */ "D15_D16_D17_D18\0" + /* 2104 */ "H18\0" + /* 2108 */ "Q15_Q16_Q17_Q18\0" + /* 2124 */ "S18\0" + /* 2128 */ "W18\0" + /* 2132 */ "X18\0" + /* 2136 */ "Z15_Z16_Z17_Z18\0" + /* 2152 */ "B28\0" + /* 2156 */ "D25_D26_D27_D28\0" + /* 2172 */ "H28\0" + /* 2176 */ "Q25_Q26_Q27_Q28\0" + /* 2192 */ "S28\0" + /* 2196 */ "W28\0" + /* 2200 */ "X28\0" + /* 2204 */ "Z25_Z26_Z27_Z28\0" + /* 2220 */ "B8\0" + /* 2223 */ "D5_D6_D7_D8\0" + /* 2235 */ "H8\0" + /* 2238 */ "P8\0" + /* 2241 */ "ZAQ8\0" + /* 2246 */ "Q5_Q6_Q7_Q8\0" + /* 2258 */ "S8\0" + /* 2261 */ "W8\0" + /* 2264 */ "X8\0" + /* 2267 */ "Z5_Z6_Z7_Z8\0" + /* 2279 */ "B19\0" + /* 2283 */ "D16_D17_D18_D19\0" + /* 2299 */ "H19\0" + /* 2303 */ "Q16_Q17_Q18_Q19\0" + /* 2319 */ "S19\0" + /* 2323 */ "W18_W19\0" + /* 2331 */ "X12_X13_X14_X15_X16_X17_X18_X19\0" + /* 2363 */ "Z16_Z17_Z18_Z19\0" + /* 2379 */ "B29\0" + /* 2383 */ "D26_D27_D28_D29\0" + /* 2399 */ "H29\0" + /* 2403 */ "Q26_Q27_Q28_Q29\0" + /* 2419 */ "S29\0" + /* 2423 */ "W28_W29\0" + /* 2431 */ "Z26_Z27_Z28_Z29\0" + /* 2447 */ "B9\0" + /* 2450 */ "D6_D7_D8_D9\0" + /* 2462 */ "H9\0" + /* 2465 */ "P9\0" + /* 2468 */ "ZAQ9\0" + /* 2473 */ "Q6_Q7_Q8_Q9\0" + /* 2485 */ "S9\0" + /* 2488 */ "W8_W9\0" + /* 2494 */ "X2_X3_X4_X5_X6_X7_X8_X9\0" + /* 2518 */ "Z6_Z7_Z8_Z9\0" + /* 2530 */ "ZA\0" + /* 2533 */ "VG\0" + /* 2536 */ "Z10_HI\0" + /* 2543 */ "Z20_HI\0" + /* 2550 */ "Z30_HI\0" + /* 2557 */ "Z0_HI\0" + /* 2563 */ "Z11_HI\0" + /* 2570 */ "Z21_HI\0" + /* 2577 */ "Z31_HI\0" + /* 2584 */ "Z1_HI\0" + /* 2590 */ "Z12_HI\0" + /* 2597 */ "Z22_HI\0" + /* 2604 */ "Z2_HI\0" + /* 2610 */ "Z13_HI\0" + /* 2617 */ "Z23_HI\0" + /* 2624 */ "Z3_HI\0" + /* 2630 */ "Z14_HI\0" + /* 2637 */ "Z24_HI\0" + /* 2644 */ "Z4_HI\0" + /* 2650 */ "Z15_HI\0" + /* 2657 */ "Z25_HI\0" + /* 2664 */ "Z5_HI\0" + /* 2670 */ "Z16_HI\0" + /* 2677 */ "Z26_HI\0" + /* 2684 */ "Z6_HI\0" + /* 2690 */ "Z17_HI\0" + /* 2697 */ "Z27_HI\0" + /* 2704 */ "Z7_HI\0" + /* 2710 */ "Z18_HI\0" + /* 2717 */ "Z28_HI\0" + /* 2724 */ "Z8_HI\0" + /* 2730 */ "Z19_HI\0" + /* 2737 */ "Z29_HI\0" + /* 2744 */ "Z9_HI\0" + /* 2750 */ "X22_X23_X24_X25_X26_X27_X28_FP\0" + /* 2781 */ "WSP\0" + /* 2785 */ "FFR\0" + /* 2789 */ "LR\0" + /* 2792 */ "W30_WZR\0" + /* 2800 */ "LR_XZR\0" + /* 2807 */ "NZCV\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterDesc AArch64RegDesc[] = { + // Descriptors + {3, 0, 0, 0, 0, 0}, + {2785, 16, 16, 4, 29537, 1865}, + {2778, 1206, 1814, 5, 29537, 1867}, + {2789, 1206, 1337, 5, 29537, 3}, + {2807, 16, 16, 4, 29537, 662}, + {2782, 690, 16, 5, 29537, 662}, + {2533, 16, 16, 4, 29537, 3}, + {2781, 16, 1821, 4, 29106, 1780}, + {2796, 16, 754, 4, 11168, 3}, + {2803, 1846, 1335, 5, 11168, 1773}, + {2530, 700, 16, 42, 0, 1173}, + {203, 16, 497, 4, 12033, 1197}, + {538, 16, 579, 4, 12033, 1195}, + {761, 16, 776, 4, 12033, 1724}, + {1036, 16, 433, 4, 12033, 3}, + {1254, 16, 433, 4, 12033, 1234}, + {1526, 16, 433, 4, 12033, 1767}, + {1732, 16, 433, 4, 12033, 662}, + {1996, 16, 433, 4, 12033, 662}, + {2220, 16, 433, 4, 12033, 3}, + {2447, 16, 433, 4, 12033, 3}, + {0, 16, 433, 4, 12033, 1765}, + {280, 16, 433, 4, 12033, 821}, + {618, 16, 433, 4, 12033, 480}, + {830, 16, 433, 4, 12033, 3}, + {1108, 16, 433, 4, 12033, 1716}, + {1318, 16, 433, 4, 12033, 1714}, + {1596, 16, 433, 4, 12033, 3}, + {1796, 16, 433, 4, 12033, 1718}, + {2084, 16, 433, 4, 12033, 662}, + {2279, 16, 433, 4, 12033, 3}, + {69, 16, 433, 4, 12033, 1720}, + {378, 16, 433, 4, 12033, 220}, + {693, 16, 433, 4, 12033, 1722}, + {936, 16, 433, 4, 12033, 892}, + {1186, 16, 433, 4, 12033, 868}, + {1426, 16, 433, 4, 12033, 769}, + {1664, 16, 433, 4, 12033, 767}, + {1896, 16, 433, 4, 12033, 866}, + {2152, 16, 433, 4, 12033, 874}, + {2379, 16, 433, 4, 12033, 909}, + {137, 16, 433, 4, 12033, 799}, + {478, 16, 433, 4, 12033, 903}, + {208, 1588, 500, 1, 29073, 441}, + {543, 1588, 582, 1, 29073, 662}, + {766, 1588, 779, 1, 29073, 662}, + {1041, 1588, 436, 1, 29073, 793}, + {1259, 1588, 436, 1, 29073, 777}, + {1531, 1588, 436, 1, 29073, 3}, + {1737, 1588, 436, 1, 29073, 779}, + {2001, 1588, 436, 1, 29073, 791}, + {2232, 1588, 436, 1, 29073, 832}, + {2459, 1588, 436, 1, 29073, 870}, + {13, 1588, 436, 1, 29073, 3}, + {294, 1588, 436, 1, 29073, 905}, + {633, 1588, 436, 1, 29073, 913}, + {846, 1588, 436, 1, 29073, 395}, + {1124, 1588, 436, 1, 29073, 901}, + {1334, 1588, 436, 1, 29073, 915}, + {1612, 1588, 436, 1, 29073, 944}, + {1812, 1588, 436, 1, 29073, 911}, + {2100, 1588, 436, 1, 29073, 917}, + {2295, 1588, 436, 1, 29073, 3}, + {85, 1588, 436, 1, 29073, 3}, + {394, 1588, 436, 1, 29073, 557}, + {709, 1588, 436, 1, 29073, 919}, + {952, 1588, 436, 1, 29073, 921}, + {1202, 1588, 436, 1, 29073, 923}, + {1442, 1588, 436, 1, 29073, 925}, + {1680, 1588, 436, 1, 29073, 1646}, + {1912, 1588, 436, 1, 29073, 3}, + {2168, 1588, 436, 1, 29073, 1648}, + {2395, 1588, 436, 1, 29073, 1859}, + {153, 1588, 436, 1, 29073, 662}, + {494, 1588, 436, 1, 29073, 1652}, + {228, 1590, 498, 3, 28289, 1638}, + {562, 1590, 580, 3, 28289, 395}, + {782, 1590, 777, 3, 28289, 3}, + {1056, 1590, 434, 3, 28289, 1658}, + {1274, 1590, 434, 3, 28289, 1656}, + {1546, 1590, 434, 3, 28289, 3}, + {1752, 1590, 434, 3, 28289, 1654}, + {2016, 1590, 434, 3, 28289, 3}, + {2235, 1590, 434, 3, 28289, 3}, + {2462, 1590, 434, 3, 28289, 464}, + {17, 1590, 434, 3, 28289, 1628}, + {298, 1590, 434, 3, 28289, 212}, + {637, 1590, 434, 3, 28289, 662}, + {850, 1590, 434, 3, 28289, 216}, + {1128, 1590, 434, 3, 28289, 1634}, + {1338, 1590, 434, 3, 28289, 662}, + {1616, 1590, 434, 3, 28289, 662}, + {1816, 1590, 434, 3, 28289, 1630}, + {2104, 1590, 434, 3, 28289, 1632}, + {2299, 1590, 434, 3, 28289, 3}, + {89, 1590, 434, 3, 28289, 3}, + {398, 1590, 434, 3, 28289, 1640}, + {713, 1590, 434, 3, 28289, 1642}, + {956, 1590, 434, 3, 28289, 1644}, + {1206, 1590, 434, 3, 28289, 876}, + {1446, 1590, 434, 3, 28289, 888}, + {1684, 1590, 434, 3, 28289, 886}, + {1916, 1590, 434, 3, 28289, 3}, + {2172, 1590, 434, 3, 28289, 250}, + {2399, 1590, 434, 3, 28289, 662}, + {157, 1590, 434, 3, 28289, 3}, + {498, 1590, 434, 3, 28289, 1668}, + {231, 16, 16, 4, 28289, 1171}, + {565, 16, 16, 4, 28289, 1636}, + {785, 16, 16, 4, 28289, 226}, + {1059, 16, 16, 4, 28289, 1674}, + {1277, 16, 16, 4, 28289, 1678}, + {1549, 16, 16, 4, 28289, 168}, + {1755, 16, 16, 4, 28289, 168}, + {2019, 16, 16, 4, 28289, 1859}, + {2238, 16, 16, 4, 28289, 662}, + {2465, 16, 16, 4, 28289, 572}, + {21, 16, 16, 4, 28289, 662}, + {302, 16, 16, 4, 28289, 3}, + {641, 16, 16, 4, 28289, 1676}, + {854, 16, 16, 4, 28289, 557}, + {1132, 16, 16, 4, 28289, 3}, + {1342, 16, 16, 4, 28289, 1680}, + {236, 1601, 530, 0, 23425, 168}, + {570, 1601, 612, 0, 23425, 257}, + {790, 1601, 809, 0, 23425, 1682}, + {1064, 1601, 466, 0, 23425, 901}, + {1282, 1601, 466, 0, 23425, 1684}, + {1554, 1601, 466, 0, 23425, 3}, + {1760, 1601, 466, 0, 23425, 3}, + {2024, 1601, 466, 0, 23425, 1688}, + {2243, 1601, 466, 0, 23425, 662}, + {2470, 1601, 466, 0, 23425, 1700}, + {27, 1601, 466, 0, 23425, 1660}, + {308, 1601, 466, 0, 23425, 168}, + {647, 1601, 466, 0, 23425, 168}, + {860, 1601, 466, 0, 23425, 1859}, + {1138, 1601, 466, 0, 23425, 662}, + {1348, 1601, 466, 0, 23425, 618}, + {1632, 1601, 466, 0, 23425, 662}, + {1832, 1601, 466, 0, 23425, 246}, + {2120, 1601, 466, 0, 23425, 3}, + {2315, 1601, 466, 0, 23425, 572}, + {105, 1601, 466, 0, 23425, 246}, + {414, 1601, 466, 0, 23425, 662}, + {729, 1601, 466, 0, 23425, 618}, + {972, 1601, 466, 0, 23425, 3}, + {1222, 1601, 466, 0, 23425, 1664}, + {1462, 1601, 466, 0, 23425, 1662}, + {1700, 1601, 466, 0, 23425, 3}, + {1932, 1601, 466, 0, 23425, 222}, + {2188, 1601, 466, 0, 23425, 3}, + {2415, 1601, 466, 0, 23425, 3}, + {173, 1601, 466, 0, 23425, 3}, + {514, 1601, 466, 0, 23425, 3}, + {256, 1589, 499, 2, 23361, 1910}, + {589, 1589, 581, 2, 23361, 1884}, + {808, 1589, 778, 2, 23361, 1916}, + {1081, 1589, 435, 2, 23361, 1894}, + {1297, 1589, 435, 2, 23361, 1894}, + {1569, 1589, 435, 2, 23361, 1896}, + {1775, 1589, 435, 2, 23361, 1902}, + {2039, 1589, 435, 2, 23361, 1886}, + {2258, 1589, 435, 2, 23361, 1906}, + {2485, 1589, 435, 2, 23361, 1888}, + {44, 1589, 435, 2, 23361, 1914}, + {326, 1589, 435, 2, 23361, 1904}, + {666, 1589, 435, 2, 23361, 1869}, + {880, 1589, 435, 2, 23361, 1879}, + {1158, 1589, 435, 2, 23361, 1900}, + {1368, 1589, 435, 2, 23361, 1892}, + {1636, 1589, 435, 2, 23361, 1877}, + {1836, 1589, 435, 2, 23361, 1908}, + {2124, 1589, 435, 2, 23361, 1873}, + {2319, 1589, 435, 2, 23361, 1912}, + {109, 1589, 435, 2, 23361, 1898}, + {418, 1589, 435, 2, 23361, 1875}, + {733, 1589, 435, 2, 23361, 1890}, + {976, 1589, 435, 2, 23361, 1890}, + {1226, 1589, 435, 2, 23361, 1871}, + {1466, 1589, 435, 2, 23361, 3}, + {1704, 1589, 435, 2, 23361, 1169}, + {1936, 1589, 435, 2, 23361, 852}, + {2192, 1589, 435, 2, 23361, 572}, + {2419, 1589, 435, 2, 23361, 1690}, + {177, 1589, 435, 2, 23361, 478}, + {518, 1589, 435, 2, 23361, 3}, + {259, 16, 1800, 4, 23393, 1692}, + {595, 16, 1795, 4, 23393, 3}, + {811, 16, 676, 4, 23393, 1859}, + {1087, 16, 670, 4, 23393, 1698}, + {1300, 16, 263, 4, 23393, 859}, + {1575, 16, 256, 4, 23393, 1666}, + {1778, 16, 137, 4, 23393, 662}, + {2045, 16, 129, 4, 23393, 3}, + {2261, 16, 129, 4, 23393, 1707}, + {2491, 16, 121, 4, 23393, 876}, + {48, 16, 121, 4, 23393, 880}, + {334, 16, 113, 4, 23393, 890}, + {670, 16, 113, 4, 23393, 878}, + {888, 16, 105, 4, 23393, 884}, + {1162, 16, 105, 4, 23393, 882}, + {1376, 16, 97, 4, 23393, 572}, + {1640, 16, 97, 4, 23393, 927}, + {1844, 16, 89, 4, 23393, 3}, + {2128, 16, 89, 4, 23393, 168}, + {2327, 16, 81, 4, 23393, 931}, + {113, 16, 81, 4, 23393, 1859}, + {426, 16, 73, 4, 23393, 3}, + {737, 16, 207, 4, 23393, 929}, + {984, 16, 199, 4, 23393, 933}, + {1230, 16, 287, 4, 23393, 935}, + {1474, 16, 280, 4, 23393, 937}, + {1708, 16, 738, 4, 23393, 3}, + {1944, 16, 732, 4, 23393, 248}, + {2196, 16, 1785, 4, 23393, 907}, + {2427, 16, 1790, 4, 23217, 1686}, + {181, 16, 758, 4, 23217, 3}, + {262, 1783, 1811, 5, 23329, 3}, + {601, 1783, 1808, 5, 23329, 3}, + {814, 1783, 686, 5, 23329, 395}, + {1093, 1783, 682, 5, 23329, 662}, + {1303, 1783, 275, 5, 23329, 901}, + {1581, 1783, 270, 5, 23329, 3}, + {1781, 1783, 193, 5, 23329, 830}, + {2069, 1783, 187, 5, 23329, 823}, + {2264, 1783, 187, 5, 23329, 662}, + {2515, 1783, 181, 5, 23329, 946}, + {52, 1783, 181, 5, 23329, 395}, + {360, 1783, 175, 5, 23329, 3}, + {674, 1783, 175, 5, 23329, 662}, + {916, 1783, 169, 5, 23329, 1726}, + {1166, 1783, 169, 5, 23329, 1730}, + {1406, 1783, 163, 5, 23329, 1734}, + {1644, 1783, 163, 5, 23329, 1728}, + {1876, 1783, 157, 5, 23329, 3}, + {2132, 1783, 157, 5, 23329, 1732}, + {2359, 1783, 151, 5, 23329, 3}, + {117, 1783, 151, 5, 23329, 3}, + {458, 1783, 145, 5, 23329, 1736}, + {741, 1783, 221, 5, 23329, 216}, + {1016, 1783, 215, 5, 23329, 1738}, + {1234, 1783, 299, 5, 23329, 3}, + {1506, 1783, 294, 5, 23329, 1740}, + {1712, 1783, 748, 5, 23329, 1859}, + {1976, 1783, 744, 5, 23329, 662}, + {2200, 1783, 1805, 5, 23329, 662}, + {277, 1208, 551, 13, 14177, 597}, + {615, 1208, 633, 13, 14177, 179}, + {827, 1208, 830, 13, 14177, 1742}, + {1105, 1208, 487, 13, 14177, 1745}, + {1315, 1208, 487, 13, 14177, 548}, + {1593, 1208, 487, 13, 14177, 2}, + {1793, 1208, 487, 13, 14177, 1748}, + {2081, 1208, 487, 13, 14177, 417}, + {2276, 1208, 487, 13, 14177, 668}, + {2527, 1208, 487, 13, 14177, 668}, + {65, 1208, 487, 13, 14177, 126}, + {374, 1208, 487, 13, 14177, 179}, + {689, 1208, 487, 13, 14177, 1754}, + {932, 1208, 487, 13, 14177, 1751}, + {1182, 1208, 487, 13, 14177, 551}, + {1422, 1208, 487, 13, 14177, 2}, + {1660, 1208, 487, 13, 14177, 1762}, + {1892, 1208, 487, 13, 14177, 417}, + {2148, 1208, 487, 13, 14177, 554}, + {2375, 1208, 487, 13, 14177, 1562}, + {133, 1208, 487, 13, 14177, 759}, + {474, 1208, 487, 13, 14177, 668}, + {757, 1208, 487, 13, 14177, 1565}, + {1032, 1208, 487, 13, 14177, 545}, + {1250, 1208, 487, 13, 14177, 1572}, + {1522, 1208, 487, 13, 14177, 657}, + {1728, 1208, 487, 13, 14177, 617}, + {1992, 1208, 487, 13, 14177, 668}, + {2216, 1208, 487, 13, 14177, 1575}, + {2443, 1208, 487, 13, 14177, 118}, + {197, 1208, 487, 13, 14177, 310}, + {534, 1208, 487, 13, 14177, 1854}, + {201, 701, 1359, 43, 0, 447}, + {206, 729, 1440, 10, 5976, 2}, + {541, 729, 1392, 10, 5976, 1581}, + {764, 729, 1416, 10, 5928, 1578}, + {1039, 729, 1368, 10, 5928, 854}, + {1257, 729, 1428, 10, 5880, 654}, + {1529, 729, 1380, 10, 5880, 1584}, + {1735, 729, 1404, 10, 5832, 1589}, + {1999, 729, 1356, 10, 5832, 668}, + {226, 717, 1406, 27, 280, 1606}, + {560, 717, 1358, 27, 280, 144}, + {234, 16, 1445, 4, 21656, 1587}, + {568, 16, 1397, 4, 21656, 572}, + {788, 16, 1421, 4, 21624, 3}, + {1062, 16, 1373, 4, 21624, 3}, + {1280, 16, 1433, 4, 21592, 1592}, + {1552, 16, 1385, 4, 21592, 662}, + {1758, 16, 1409, 4, 21560, 857}, + {2022, 16, 1361, 4, 21560, 3}, + {2241, 16, 1439, 4, 21528, 3}, + {2468, 16, 1391, 4, 21528, 572}, + {25, 16, 1415, 4, 21496, 662}, + {306, 16, 1367, 4, 21496, 901}, + {645, 16, 1427, 4, 21464, 1615}, + {858, 16, 1379, 4, 21464, 1604}, + {1136, 16, 1403, 4, 21432, 224}, + {1346, 16, 1355, 4, 21432, 848}, + {254, 725, 1429, 20, 936, 330}, + {587, 725, 1381, 20, 936, 14}, + {806, 725, 1405, 20, 856, 762}, + {1079, 725, 1357, 20, 856, 834}, + {2557, 16, 550, 4, 23249, 1624}, + {2584, 16, 632, 4, 23249, 3}, + {2604, 16, 829, 4, 23249, 3}, + {2624, 16, 486, 4, 23249, 1617}, + {2644, 16, 486, 4, 23249, 1626}, + {2664, 16, 486, 4, 23249, 572}, + {2684, 16, 486, 4, 23249, 3}, + {2704, 16, 486, 4, 23249, 168}, + {2724, 16, 486, 4, 23249, 3}, + {2744, 16, 486, 4, 23249, 391}, + {2536, 16, 486, 4, 23249, 819}, + {2563, 16, 486, 4, 23249, 3}, + {2590, 16, 486, 4, 23249, 784}, + {2610, 16, 486, 4, 23249, 797}, + {2630, 16, 486, 4, 23249, 3}, + {2650, 16, 486, 4, 23249, 775}, + {2670, 16, 486, 4, 23249, 850}, + {2690, 16, 486, 4, 23249, 3}, + {2710, 16, 486, 4, 23249, 771}, + {2730, 16, 486, 4, 23249, 872}, + {2543, 16, 486, 4, 23249, 3}, + {2570, 16, 486, 4, 23249, 1169}, + {2597, 16, 486, 4, 23249, 773}, + {2617, 16, 486, 4, 23249, 795}, + {2637, 16, 486, 4, 23249, 3}, + {2657, 16, 486, 4, 23249, 1650}, + {2677, 16, 486, 4, 23249, 430}, + {2697, 16, 486, 4, 23249, 168}, + {2717, 16, 486, 4, 23249, 466}, + {2737, 16, 486, 4, 23249, 1236}, + {2550, 16, 486, 4, 23249, 662}, + {2577, 16, 486, 4, 23249, 618}, + {554, 1592, 643, 74, 6881, 1238}, + {776, 1592, 851, 74, 6881, 622}, + {1050, 1592, 561, 74, 6881, 1241}, + {1268, 1592, 561, 74, 6881, 1249}, + {1540, 1592, 561, 74, 6881, 1252}, + {1746, 1592, 561, 74, 6881, 1255}, + {2010, 1592, 561, 74, 6881, 1822}, + {2229, 1592, 561, 74, 6881, 1813}, + {2456, 1592, 561, 74, 6881, 1819}, + {10, 1592, 561, 74, 6881, 1816}, + {290, 1592, 561, 74, 6881, 1825}, + {629, 1592, 561, 74, 6881, 1261}, + {842, 1592, 561, 74, 6881, 2}, + {1120, 1592, 561, 74, 6881, 1258}, + {1330, 1592, 561, 74, 6881, 1264}, + {1608, 1592, 561, 74, 6881, 489}, + {1808, 1592, 561, 74, 6881, 781}, + {2096, 1592, 561, 74, 6881, 1271}, + {2291, 1592, 561, 74, 6881, 403}, + {81, 1592, 561, 74, 6881, 299}, + {390, 1592, 561, 74, 6881, 1796}, + {705, 1592, 561, 74, 6881, 302}, + {948, 1592, 561, 74, 6881, 948}, + {1198, 1592, 561, 74, 6881, 121}, + {1438, 1592, 561, 74, 6881, 2}, + {1676, 1592, 561, 74, 6881, 2}, + {1908, 1592, 561, 74, 6881, 951}, + {2164, 1592, 561, 74, 6881, 2}, + {2391, 1592, 561, 74, 6881, 495}, + {149, 1592, 561, 74, 6881, 498}, + {490, 1592, 561, 74, 6881, 2}, + {219, 1583, 561, 74, 13904, 954}, + {1044, 1724, 1203, 98, 1089, 24}, + {1262, 1724, 1203, 98, 1089, 962}, + {1534, 1724, 1203, 98, 1089, 692}, + {1740, 1724, 1203, 98, 1089, 957}, + {2004, 1724, 1203, 98, 1089, 473}, + {2223, 1724, 1203, 98, 1089, 967}, + {2450, 1724, 1203, 98, 1089, 972}, + {4, 1724, 1203, 98, 1089, 338}, + {284, 1724, 1203, 98, 1089, 1799}, + {622, 1724, 1203, 98, 1089, 284}, + {834, 1724, 1203, 98, 1089, 501}, + {1112, 1724, 1203, 98, 1089, 1757}, + {1322, 1724, 1203, 98, 1089, 638}, + {1600, 1724, 1203, 98, 1089, 1709}, + {1800, 1724, 1203, 98, 1089, 939}, + {2088, 1724, 1203, 98, 1089, 894}, + {2283, 1724, 1203, 98, 1089, 1244}, + {73, 1724, 1203, 98, 1089, 1190}, + {382, 1724, 1203, 98, 1089, 1775}, + {697, 1724, 1203, 98, 1089, 1619}, + {940, 1724, 1203, 98, 1089, 1599}, + {1190, 1724, 1203, 98, 1089, 1702}, + {1430, 1724, 1203, 98, 1089, 1594}, + {1668, 1724, 1203, 98, 1089, 977}, + {1900, 1724, 1203, 98, 1089, 343}, + {2156, 1724, 1203, 98, 1089, 29}, + {2383, 1724, 1203, 98, 1089, 252}, + {141, 1724, 1203, 98, 1089, 861}, + {482, 1724, 1203, 98, 1089, 786}, + {211, 1746, 1203, 98, 3632, 825}, + {546, 1561, 1203, 98, 4864, 801}, + {769, 1702, 1203, 98, 12192, 810}, + {773, 334, 877, 83, 4033, 815}, + {1047, 334, 661, 83, 4033, 563}, + {1265, 334, 661, 83, 4033, 1064}, + {1537, 334, 661, 83, 4033, 707}, + {1743, 334, 661, 83, 4033, 650}, + {2007, 334, 661, 83, 4033, 660}, + {2226, 334, 661, 83, 4033, 1060}, + {2453, 334, 661, 83, 4033, 1072}, + {7, 334, 661, 83, 4033, 1068}, + {287, 334, 661, 83, 4033, 715}, + {625, 334, 661, 83, 4033, 646}, + {838, 334, 661, 83, 4033, 1076}, + {1116, 334, 661, 83, 4033, 443}, + {1326, 334, 661, 83, 4033, 161}, + {1604, 334, 661, 83, 4033, 1080}, + {1804, 334, 661, 83, 4033, 1857}, + {2092, 334, 661, 83, 4033, 711}, + {2287, 334, 661, 83, 4033, 157}, + {77, 334, 661, 83, 4033, 1084}, + {386, 334, 661, 83, 4033, 1092}, + {701, 334, 661, 83, 4033, 1861}, + {944, 334, 661, 83, 4033, 1088}, + {1194, 334, 661, 83, 4033, 1056}, + {1434, 334, 661, 83, 4033, 104}, + {1672, 334, 661, 83, 4033, 210}, + {1904, 334, 661, 83, 4033, 153}, + {2160, 334, 661, 83, 4033, 129}, + {2387, 334, 661, 83, 4033, 1769}, + {145, 334, 661, 83, 4033, 1670}, + {486, 334, 661, 83, 4033, 1694}, + {215, 349, 661, 83, 5088, 1568}, + {550, 1770, 661, 83, 13440, 1267}, + {581, 1215, 649, 120, 6113, 1881}, + {800, 1215, 857, 120, 6113, 2}, + {1073, 1215, 567, 120, 6113, 2}, + {1291, 1215, 567, 120, 6113, 2}, + {1563, 1215, 567, 120, 6113, 2}, + {1769, 1215, 567, 120, 6113, 2}, + {2033, 1215, 567, 120, 6113, 2}, + {2252, 1215, 567, 120, 6113, 2}, + {2479, 1215, 567, 120, 6113, 2}, + {37, 1215, 567, 120, 6113, 2}, + {318, 1215, 567, 120, 6113, 2}, + {658, 1215, 567, 120, 6113, 2}, + {872, 1215, 567, 120, 6113, 2}, + {1150, 1215, 567, 120, 6113, 2}, + {1360, 1215, 567, 120, 6113, 2}, + {1628, 1215, 567, 120, 6113, 2}, + {1828, 1215, 567, 120, 6113, 2}, + {2116, 1215, 567, 120, 6113, 2}, + {2311, 1215, 567, 120, 6113, 2}, + {101, 1215, 567, 120, 6113, 2}, + {410, 1215, 567, 120, 6113, 2}, + {725, 1215, 567, 120, 6113, 2}, + {968, 1215, 567, 120, 6113, 2}, + {1218, 1215, 567, 120, 6113, 2}, + {1458, 1215, 567, 120, 6113, 2}, + {1696, 1215, 567, 120, 6113, 2}, + {1928, 1215, 567, 120, 6113, 2}, + {2184, 1215, 567, 120, 6113, 2}, + {2411, 1215, 567, 120, 6113, 2}, + {169, 1215, 567, 120, 6113, 2}, + {510, 1215, 567, 120, 6113, 2}, + {247, 1317, 567, 120, 13904, 1096}, + {1067, 1638, 1204, 153, 1009, 1099}, + {1285, 1638, 1204, 153, 1009, 415}, + {1557, 1638, 1204, 153, 1009, 1104}, + {1763, 1638, 1204, 153, 1009, 1109}, + {2027, 1638, 1204, 153, 1009, 228}, + {2246, 1638, 1204, 153, 1009, 1114}, + {2473, 1638, 1204, 153, 1009, 1119}, + {31, 1638, 1204, 153, 1009, 0}, + {312, 1638, 1204, 153, 1009, 5}, + {651, 1638, 1204, 153, 1009, 1791}, + {864, 1638, 1204, 153, 1009, 64}, + {1142, 1638, 1204, 153, 1009, 401}, + {1352, 1638, 1204, 153, 1009, 1124}, + {1620, 1638, 1204, 153, 1009, 574}, + {1820, 1638, 1204, 153, 1009, 165}, + {2108, 1638, 1204, 153, 1009, 1134}, + {2303, 1638, 1204, 153, 1009, 1139}, + {93, 1638, 1204, 153, 1009, 1129}, + {402, 1638, 1204, 153, 1009, 468}, + {717, 1638, 1204, 153, 1009, 189}, + {960, 1638, 1204, 153, 1009, 52}, + {1210, 1638, 1204, 153, 1009, 1144}, + {1450, 1638, 1204, 153, 1009, 1154}, + {1688, 1638, 1204, 153, 1009, 1149}, + {1920, 1638, 1204, 153, 1009, 678}, + {2176, 1638, 1204, 153, 1009, 69}, + {2403, 1638, 1204, 153, 1009, 401}, + {161, 1638, 1204, 153, 1009, 1159}, + {502, 1638, 1204, 153, 1009, 506}, + {239, 1670, 1204, 153, 3632, 74}, + {573, 1529, 1204, 153, 4864, 1164}, + {793, 1606, 1204, 153, 12192, 420}, + {797, 1466, 880, 132, 3969, 719}, + {1070, 1466, 664, 132, 3969, 986}, + {1288, 1466, 664, 132, 3969, 10}, + {1560, 1466, 664, 132, 3969, 994}, + {1766, 1466, 664, 132, 3969, 990}, + {2030, 1466, 664, 132, 3969, 899}, + {2249, 1466, 664, 132, 3969, 133}, + {2476, 1466, 664, 132, 3969, 982}, + {34, 1466, 664, 132, 3969, 806}, + {315, 1466, 664, 132, 3969, 679}, + {654, 1466, 664, 132, 3969, 1002}, + {868, 1466, 664, 132, 3969, 998}, + {1146, 1466, 664, 132, 3969, 625}, + {1356, 1466, 664, 132, 3969, 1010}, + {1624, 1466, 664, 132, 3969, 1018}, + {1824, 1466, 664, 132, 3969, 1006}, + {2112, 1466, 664, 132, 3969, 600}, + {2307, 1466, 664, 132, 3969, 214}, + {97, 1466, 664, 132, 3969, 108}, + {406, 1466, 664, 132, 3969, 1014}, + {721, 1466, 664, 132, 3969, 559}, + {964, 1466, 664, 132, 3969, 679}, + {1214, 1466, 664, 132, 3969, 397}, + {1454, 1466, 664, 132, 3969, 108}, + {1692, 1466, 664, 132, 3969, 137}, + {1924, 1466, 664, 132, 3969, 1022}, + {2180, 1466, 664, 132, 3969, 1034}, + {2407, 1466, 664, 132, 3969, 679}, + {165, 1466, 664, 132, 3969, 393}, + {506, 1466, 664, 132, 3969, 1026}, + {243, 1487, 664, 132, 5088, 218}, + {577, 1508, 664, 132, 13440, 1030}, + {2750, 2098, 16, 185, 560, 629}, + {2048, 2073, 16, 185, 418, 1782}, + {2494, 2048, 16, 185, 418, 839}, + {338, 2023, 16, 185, 418, 194}, + {892, 1998, 16, 185, 418, 683}, + {1380, 1973, 16, 185, 418, 173}, + {1848, 1948, 16, 185, 418, 1038}, + {2331, 1923, 16, 185, 418, 43}, + {430, 1898, 16, 185, 418, 366}, + {988, 1873, 16, 185, 418, 1804}, + {1478, 1848, 16, 185, 418, 1047}, + {1948, 1823, 16, 185, 418, 34}, + {2792, 1455, 756, 7, 11072, 141}, + {592, 385, 1797, 7, 6066, 1199}, + {1084, 388, 672, 7, 6066, 2}, + {1572, 391, 258, 7, 6066, 233}, + {2042, 394, 75, 7, 6066, 1202}, + {2488, 397, 75, 7, 6066, 1205}, + {330, 400, 75, 7, 6066, 1208}, + {884, 403, 75, 7, 6066, 412}, + {1372, 406, 75, 7, 6066, 492}, + {1840, 409, 75, 7, 6066, 296}, + {2323, 412, 75, 7, 6066, 2}, + {422, 415, 75, 7, 6066, 170}, + {980, 418, 201, 7, 6066, 2}, + {1470, 421, 282, 7, 6066, 1211}, + {1940, 424, 734, 7, 6066, 126}, + {2423, 427, 1787, 7, 19201, 121}, + {2800, 1329, 16, 210, 11121, 1214}, + {2774, 1227, 1788, 210, 19152, 1217}, + {598, 1311, 1788, 210, 6018, 635}, + {1090, 1305, 673, 210, 6018, 1220}, + {1578, 1299, 259, 210, 6018, 1223}, + {2066, 1293, 76, 210, 6018, 635}, + {2512, 1287, 76, 210, 6018, 668}, + {356, 1281, 76, 210, 6018, 186}, + {912, 1275, 76, 210, 6018, 263}, + {1402, 1269, 76, 210, 6018, 2}, + {1872, 1263, 76, 210, 6018, 335}, + {2355, 1257, 76, 210, 6018, 1226}, + {454, 1251, 76, 210, 6018, 643}, + {1012, 1245, 202, 210, 6018, 245}, + {1502, 1239, 283, 210, 6018, 186}, + {1972, 1233, 735, 210, 6018, 263}, + {612, 889, 655, 216, 5265, 1229}, + {824, 889, 863, 216, 5265, 19}, + {1102, 889, 573, 216, 5265, 243}, + {1312, 889, 573, 216, 5265, 1279}, + {1590, 889, 573, 216, 5265, 1284}, + {1790, 889, 573, 216, 5265, 1289}, + {2078, 889, 573, 216, 5265, 305}, + {2273, 889, 573, 216, 5265, 1828}, + {2524, 889, 573, 216, 5265, 1294}, + {62, 889, 573, 216, 5265, 735}, + {370, 889, 573, 216, 5265, 723}, + {685, 889, 573, 216, 5265, 620}, + {928, 889, 573, 216, 5265, 574}, + {1178, 889, 573, 216, 5265, 1314}, + {1418, 889, 573, 216, 5265, 1304}, + {1656, 889, 573, 216, 5265, 1309}, + {1888, 889, 573, 216, 5265, 313}, + {2144, 889, 573, 216, 5265, 1833}, + {2371, 889, 573, 216, 5265, 1319}, + {129, 889, 573, 216, 5265, 740}, + {470, 889, 573, 216, 5265, 1299}, + {753, 889, 573, 216, 5265, 1324}, + {1028, 889, 573, 216, 5265, 1329}, + {1246, 889, 573, 216, 5265, 425}, + {1518, 889, 573, 216, 5265, 697}, + {1724, 889, 573, 216, 5265, 124}, + {1988, 889, 573, 216, 5265, 1274}, + {2212, 889, 573, 216, 5265, 318}, + {2439, 889, 573, 216, 5265, 702}, + {193, 889, 573, 216, 5265, 1334}, + {530, 889, 573, 216, 5265, 198}, + {273, 906, 573, 216, 13952, 671}, + {1096, 1105, 16, 263, 705, 275}, + {1306, 1105, 16, 263, 705, 1348}, + {1584, 1105, 16, 263, 705, 112}, + {1784, 1105, 16, 263, 705, 1339}, + {2072, 1105, 16, 263, 705, 79}, + {2267, 1105, 16, 263, 705, 511}, + {2518, 1105, 16, 263, 705, 1838}, + {56, 1105, 16, 263, 705, 348}, + {364, 1105, 16, 263, 705, 520}, + {678, 1105, 16, 263, 705, 1357}, + {920, 1105, 16, 263, 705, 357}, + {1170, 1105, 16, 263, 705, 1384}, + {1410, 1105, 16, 263, 705, 1366}, + {1648, 1105, 16, 263, 705, 1375}, + {1880, 1105, 16, 263, 705, 1393}, + {2136, 1105, 16, 263, 705, 406}, + {2363, 1105, 16, 263, 705, 1402}, + {121, 1105, 16, 263, 705, 1438}, + {462, 1105, 16, 263, 705, 1411}, + {745, 1105, 16, 263, 705, 1420}, + {1020, 1105, 16, 263, 705, 1429}, + {1238, 1105, 16, 263, 705, 1483}, + {1510, 1105, 16, 263, 705, 1474}, + {1716, 1105, 16, 263, 705, 266}, + {1980, 1105, 16, 263, 705, 1447}, + {2204, 1105, 16, 263, 705, 1456}, + {2431, 1105, 16, 263, 705, 604}, + {185, 1105, 16, 263, 705, 1465}, + {522, 1105, 16, 263, 705, 88}, + {265, 1151, 16, 263, 3712, 529}, + {604, 1013, 16, 263, 4944, 432}, + {817, 1059, 16, 263, 12272, 375}, + {821, 923, 883, 233, 3857, 538}, + {1099, 923, 463, 233, 3857, 613}, + {1309, 923, 463, 233, 3857, 482}, + {1587, 923, 463, 233, 3857, 57}, + {1787, 923, 463, 233, 3857, 323}, + {2075, 923, 463, 233, 3857, 593}, + {2270, 923, 463, 233, 3857, 664}, + {2521, 923, 463, 233, 3857, 97}, + {59, 923, 463, 233, 3857, 203}, + {367, 923, 463, 233, 3857, 236}, + {681, 923, 463, 233, 3857, 1492}, + {924, 923, 463, 233, 3857, 728}, + {1174, 923, 463, 233, 3857, 384}, + {1414, 923, 463, 233, 3857, 586}, + {1652, 923, 463, 233, 3857, 1499}, + {1884, 923, 463, 233, 3857, 676}, + {2140, 923, 463, 233, 3857, 1506}, + {2367, 923, 463, 233, 3857, 1520}, + {125, 923, 463, 233, 3857, 745}, + {466, 923, 463, 233, 3857, 1513}, + {749, 923, 463, 233, 3857, 1527}, + {1024, 923, 463, 233, 3857, 567}, + {1242, 923, 463, 233, 3857, 579}, + {1514, 923, 463, 233, 3857, 182}, + {1720, 923, 463, 233, 3857, 1548}, + {1984, 923, 463, 233, 3857, 259}, + {2208, 923, 463, 233, 3857, 1534}, + {2435, 923, 463, 233, 3857, 289}, + {189, 923, 463, 233, 3857, 1847}, + {526, 923, 463, 233, 3857, 1541}, + {269, 953, 463, 233, 5152, 752}, + {608, 983, 463, 233, 13504, 1555}, +}; + +// FPR8 Register Class... +static const MCPhysReg FPR8[] = { + AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, + AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, + AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, + AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, + AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, + AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, + AArch64_B30, AArch64_B31, +}; + +// FPR8 Bit set. +static const uint8_t FPR8Bits[] = { + 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// FPR16 Register Class... +static const MCPhysReg FPR16[] = { + AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, + AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, + AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, + AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, + AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, + AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, + AArch64_H30, AArch64_H31, +}; + +// FPR16 Bit set. +static const uint8_t FPR16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// FPR16_lo Register Class... +static const MCPhysReg FPR16_lo[] = { + AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, + AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, + AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, + AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, +}; + +// FPR16_lo Bit set. +static const uint8_t FPR16_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// PPR Register Class... +static const MCPhysReg PPR[] = { + AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, + AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, + AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11, + AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15, +}; + +// PPR Bit set. +static const uint8_t PPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// PPR_3b Register Class... +static const MCPhysReg PPR_3b[] = { + AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, + AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, +}; + +// PPR_3b Bit set. +static const uint8_t PPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, +}; + +// GPR32all Register Class... +static const MCPhysReg GPR32all[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, + AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, + AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, + AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, + AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, + AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, + AArch64_W30, AArch64_WZR, AArch64_WSP, +}; + +// GPR32all Bit set. +static const uint8_t GPR32allBits[] = { + 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x03, +}; + +// FPR32 Register Class... +static const MCPhysReg FPR32[] = { + AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, + AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, + AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, + AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, + AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, + AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, + AArch64_S30, AArch64_S31, +}; + +// FPR32 Bit set. +static const uint8_t FPR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// GPR32 Register Class... +static const MCPhysReg GPR32[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, + AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, + AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, + AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, + AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, + AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, + AArch64_W30, AArch64_WZR, +}; + +// GPR32 Bit set. +static const uint8_t GPR32Bits[] = { + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x03, +}; + +// GPR32sp Register Class... +static const MCPhysReg GPR32sp[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, + AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, + AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, + AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, + AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, + AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, + AArch64_W30, AArch64_WSP, +}; + +// GPR32sp Bit set. +static const uint8_t GPR32spBits[] = { + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x03, +}; + +// GPR32common Register Class... +static const MCPhysReg GPR32common[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, + AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, + AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, + AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, + AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, + AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, + AArch64_W30, +}; + +// GPR32common Bit set. +static const uint8_t GPR32commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x03, +}; + +// FPR32_with_hsub_in_FPR16_lo Register Class... +static const MCPhysReg FPR32_with_hsub_in_FPR16_lo[] = { + AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, + AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, + AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, + AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, +}; + +// FPR32_with_hsub_in_FPR16_lo Bit set. +static const uint8_t FPR32_with_hsub_in_FPR16_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// GPR32arg Register Class... +static const MCPhysReg GPR32arg[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, + AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, +}; + +// GPR32arg Bit set. +static const uint8_t GPR32argBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, +}; + +// MatrixIndexGPR32_12_15 Register Class... +static const MCPhysReg MatrixIndexGPR32_12_15[] = { + AArch64_W12, + AArch64_W13, + AArch64_W14, + AArch64_W15, +}; + +// MatrixIndexGPR32_12_15 Bit set. +static const uint8_t MatrixIndexGPR32_12_15Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, +}; + +// CCR Register Class... +static const MCPhysReg CCR[] = { + AArch64_NZCV, +}; + +// CCR Bit set. +static const uint8_t CCRBits[] = { + 0x10, +}; + +// GPR32sponly Register Class... +static const MCPhysReg GPR32sponly[] = { + AArch64_WSP, +}; + +// GPR32sponly Bit set. +static const uint8_t GPR32sponlyBits[] = { + 0x80, +}; + +// WSeqPairsClass Register Class... +static const MCPhysReg WSeqPairsClass[] = { + AArch64_W0_W1, AArch64_W2_W3, AArch64_W4_W5, AArch64_W6_W7, + AArch64_W8_W9, AArch64_W10_W11, AArch64_W12_W13, AArch64_W14_W15, + AArch64_W16_W17, AArch64_W18_W19, AArch64_W20_W21, AArch64_W22_W23, + AArch64_W24_W25, AArch64_W26_W27, AArch64_W28_W29, AArch64_W30_WZR, +}; + +// WSeqPairsClass Bit set. +static const uint8_t WSeqPairsClassBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// WSeqPairsClass_with_subo32_in_GPR32common Register Class... +static const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = { + AArch64_W0_W1, AArch64_W2_W3, AArch64_W4_W5, AArch64_W6_W7, + AArch64_W8_W9, AArch64_W10_W11, AArch64_W12_W13, AArch64_W14_W15, + AArch64_W16_W17, AArch64_W18_W19, AArch64_W20_W21, AArch64_W22_W23, + AArch64_W24_W25, AArch64_W26_W27, AArch64_W28_W29, +}; + +// WSeqPairsClass_with_subo32_in_GPR32common Bit set. +static const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, +}; + +// WSeqPairsClass_with_sube32_in_GPR32arg Register Class... +static const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32arg[] = { + AArch64_W0_W1, + AArch64_W2_W3, + AArch64_W4_W5, + AArch64_W6_W7, +}; + +// WSeqPairsClass_with_sube32_in_GPR32arg Bit set. +static const uint8_t WSeqPairsClass_with_sube32_in_GPR32argBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, +}; + +// WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 Register Class... +static const MCPhysReg WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15[] = + { + AArch64_W12_W13, + AArch64_W14_W15, +}; + +// WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 Bit set. +static const uint8_t + WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, +}; + +// GPR64all Register Class... +static const MCPhysReg GPR64all[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, + AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, + AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, + AArch64_LR, AArch64_XZR, AArch64_SP, +}; + +// GPR64all Bit set. +static const uint8_t GPR64allBits[] = { + 0x2c, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x7f, +}; + +// FPR64 Register Class... +static const MCPhysReg FPR64[] = { + AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, + AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, + AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, + AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, + AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, + AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, + AArch64_D30, AArch64_D31, +}; + +// FPR64 Bit set. +static const uint8_t FPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// GPR64 Register Class... +static const MCPhysReg GPR64[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, + AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, + AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, + AArch64_LR, AArch64_XZR, +}; + +// GPR64 Bit set. +static const uint8_t GPR64Bits[] = { + 0x0c, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x7f, +}; + +// GPR64sp Register Class... +static const MCPhysReg GPR64sp[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, + AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, + AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, + AArch64_LR, AArch64_SP, +}; + +// GPR64sp Bit set. +static const uint8_t GPR64spBits[] = { + 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x7f, +}; + +// GPR64common Register Class... +static const MCPhysReg GPR64common[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, + AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, + AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, + AArch64_LR, +}; + +// GPR64common Bit set. +static const uint8_t GPR64commonBits[] = { + 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x7f, +}; +// GPR64noip Register Class... +static const MCPhysReg GPR64noip[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, + AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, + AArch64_X27, AArch64_X28, AArch64_FP, AArch64_XZR, +}; + +// GPR64noip Bit set. +static const uint8_t GPR64noipBits[] = { + 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xf3, 0x7f, +}; + +// GPR64common_and_GPR64noip Register Class... +static const MCPhysReg GPR64common_and_GPR64noip[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, + AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, + AArch64_X27, AArch64_X28, AArch64_FP, +}; + +// GPR64common_and_GPR64noip Bit set. +static const uint8_t GPR64common_and_GPR64noipBits[] = { + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xf3, 0x7f, +}; + +// tcGPR64 Register Class... +static const MCPhysReg tcGPR64[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, +}; + +// tcGPR64 Bit set. +static const uint8_t tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x1f, +}; + +// GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg GPR64noip_and_tcGPR64[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X18, +}; + +// GPR64noip_and_tcGPR64 Bit set. +static const uint8_t GPR64noip_and_tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x13, +}; + +// FPR64_lo Register Class... +static const MCPhysReg FPR64_lo[] = { + AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, + AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, + AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, + AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, +}; + +// FPR64_lo Bit set. +static const uint8_t FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// GPR64arg Register Class... +static const MCPhysReg GPR64arg[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, + AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, +}; + +// GPR64arg Bit set. +static const uint8_t GPR64argBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, +}; + +// GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Register Class... +static const MCPhysReg GPR64_with_sub_32_in_MatrixIndexGPR32_12_15[] = { + AArch64_X12, + AArch64_X13, + AArch64_X14, + AArch64_X15, +}; + +// GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Bit set. +static const uint8_t GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, +}; + +// rtcGPR64 Register Class... +static const MCPhysReg rtcGPR64[] = { + AArch64_X16, + AArch64_X17, +}; + +// rtcGPR64 Bit set. +static const uint8_t rtcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, +}; + +// GPR64sponly Register Class... +static const MCPhysReg GPR64sponly[] = { + AArch64_SP, +}; + +// GPR64sponly Bit set. +static const uint8_t GPR64sponlyBits[] = { + 0x20, +}; + +// DD Register Class... +static const MCPhysReg DD[] = { + AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, + AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, + AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, + AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, + AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, + AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, + AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, + AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0, +}; + +// DD Bit set. +static const uint8_t DDBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, +}; + +// DD_with_dsub0_in_FPR64_lo Register Class... +static const MCPhysReg DD_with_dsub0_in_FPR64_lo[] = { + AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, + AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, + AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, + AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, +}; + +// DD_with_dsub0_in_FPR64_lo Bit set. +static const uint8_t DD_with_dsub0_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, +}; + +// DD_with_dsub1_in_FPR64_lo Register Class... +static const MCPhysReg DD_with_dsub1_in_FPR64_lo[] = { + AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, + AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, + AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, + AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D31_D0, +}; + +// DD_with_dsub1_in_FPR64_lo Bit set. +static const uint8_t DD_with_dsub1_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, +}; + +// XSeqPairsClass Register Class... +static const MCPhysReg XSeqPairsClass[] = { + AArch64_X0_X1, AArch64_X2_X3, AArch64_X4_X5, AArch64_X6_X7, + AArch64_X8_X9, AArch64_X10_X11, AArch64_X12_X13, AArch64_X14_X15, + AArch64_X16_X17, AArch64_X18_X19, AArch64_X20_X21, AArch64_X22_X23, + AArch64_X24_X25, AArch64_X26_X27, AArch64_X28_FP, AArch64_LR_XZR, +}; + +// XSeqPairsClass Bit set. +static const uint8_t XSeqPairsClassBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo Register Class... +static const MCPhysReg + DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo[] = { + AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, + AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, + AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, + AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, +}; + +// DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo Bit set. +static const uint8_t + DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, +}; + +// XSeqPairsClass_with_subo64_in_GPR64common Register Class... +static const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = { + AArch64_X0_X1, AArch64_X2_X3, AArch64_X4_X5, AArch64_X6_X7, + AArch64_X8_X9, AArch64_X10_X11, AArch64_X12_X13, AArch64_X14_X15, + AArch64_X16_X17, AArch64_X18_X19, AArch64_X20_X21, AArch64_X22_X23, + AArch64_X24_X25, AArch64_X26_X27, AArch64_X28_FP, +}; + +// XSeqPairsClass_with_subo64_in_GPR64common Bit set. +static const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, +}; + +// XSeqPairsClass_with_subo64_in_GPR64noip Register Class... +static const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip[] = { + AArch64_X0_X1, AArch64_X2_X3, AArch64_X4_X5, AArch64_X6_X7, + AArch64_X8_X9, AArch64_X10_X11, AArch64_X12_X13, AArch64_X14_X15, + AArch64_X18_X19, AArch64_X20_X21, AArch64_X22_X23, AArch64_X24_X25, + AArch64_X26_X27, AArch64_X28_FP, AArch64_LR_XZR, +}; + +// XSeqPairsClass_with_subo64_in_GPR64noip Bit set. +static const uint8_t XSeqPairsClass_with_subo64_in_GPR64noipBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xef, 0x03, +}; + +// XSeqPairsClass_with_sube64_in_GPR64noip Register Class... +static const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip[] = { + AArch64_X0_X1, AArch64_X2_X3, AArch64_X4_X5, AArch64_X6_X7, + AArch64_X8_X9, AArch64_X10_X11, AArch64_X12_X13, AArch64_X14_X15, + AArch64_X18_X19, AArch64_X20_X21, AArch64_X22_X23, AArch64_X24_X25, + AArch64_X26_X27, AArch64_X28_FP, +}; + +// XSeqPairsClass_with_sube64_in_GPR64noip Bit set. +static const uint8_t XSeqPairsClass_with_sube64_in_GPR64noipBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xef, 0x03, +}; + +// XSeqPairsClass_with_sube64_in_tcGPR64 Register Class... +static const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = { + AArch64_X0_X1, AArch64_X2_X3, AArch64_X4_X5, AArch64_X6_X7, + AArch64_X8_X9, AArch64_X10_X11, AArch64_X12_X13, AArch64_X14_X15, + AArch64_X16_X17, AArch64_X18_X19, +}; + +// XSeqPairsClass_with_sube64_in_tcGPR64 Bit set. +static const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f, +}; + +// XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1, AArch64_X2_X3, AArch64_X4_X5, + AArch64_X6_X7, AArch64_X8_X9, AArch64_X10_X11, + AArch64_X12_X13, AArch64_X14_X15, AArch64_X18_X19, +}; + +// XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x2f, +}; + +// XSeqPairsClass_with_subo64_in_tcGPR64 Register Class... +static const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = { + AArch64_X0_X1, AArch64_X2_X3, AArch64_X4_X5, + AArch64_X6_X7, AArch64_X8_X9, AArch64_X10_X11, + AArch64_X12_X13, AArch64_X14_X15, AArch64_X16_X17, +}; + +// XSeqPairsClass_with_subo64_in_tcGPR64 Bit set. +static const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x1f, +}; + +// XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1, AArch64_X2_X3, AArch64_X4_X5, AArch64_X6_X7, + AArch64_X8_X9, AArch64_X10_X11, AArch64_X12_X13, AArch64_X14_X15, +}; + +// XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, +}; + +// XSeqPairsClass_with_sub_32_in_GPR32arg Register Class... +static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32arg[] = { + AArch64_X0_X1, + AArch64_X2_X3, + AArch64_X4_X5, + AArch64_X6_X7, +}; + +// XSeqPairsClass_with_sub_32_in_GPR32arg Bit set. +static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32argBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, +}; + +// XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15 Register Class... +static const MCPhysReg XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15[] = + { + AArch64_X12_X13, + AArch64_X14_X15, +}; + +// XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15 Bit set. +static const uint8_t + XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, +}; + +// XSeqPairsClass_with_sube64_in_rtcGPR64 Register Class... +static const MCPhysReg XSeqPairsClass_with_sube64_in_rtcGPR64[] = { + AArch64_X16_X17, +}; + +// XSeqPairsClass_with_sube64_in_rtcGPR64 Bit set. +static const uint8_t XSeqPairsClass_with_sube64_in_rtcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, +}; + +// FPR128 Register Class... +static const MCPhysReg FPR128[] = { + AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, + AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, + AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, + AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, + AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, + AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, + AArch64_Q30, AArch64_Q31, +}; + +// FPR128 Bit set. +static const uint8_t FPR128Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// ZPR Register Class... +static const MCPhysReg ZPR[] = { + AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, + AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, + AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, + AArch64_Z15, AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19, + AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, AArch64_Z24, + AArch64_Z25, AArch64_Z26, AArch64_Z27, AArch64_Z28, AArch64_Z29, + AArch64_Z30, AArch64_Z31, +}; + +// ZPR Bit set. +static const uint8_t ZPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, +}; + +// FPR128_lo Register Class... +static const MCPhysReg FPR128_lo[] = { + AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, + AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, + AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, + AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, +}; + +// FPR128_lo Bit set. +static const uint8_t FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// MPR128 Register Class... +static const MCPhysReg MPR128[] = { + AArch64_ZAQ0, AArch64_ZAQ1, AArch64_ZAQ2, AArch64_ZAQ3, + AArch64_ZAQ4, AArch64_ZAQ5, AArch64_ZAQ6, AArch64_ZAQ7, + AArch64_ZAQ8, AArch64_ZAQ9, AArch64_ZAQ10, AArch64_ZAQ11, + AArch64_ZAQ12, AArch64_ZAQ13, AArch64_ZAQ14, AArch64_ZAQ15, +}; + +// MPR128 Bit set. +static const uint8_t MPR128Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// ZPR_4b Register Class... +static const MCPhysReg ZPR_4b[] = { + AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, + AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, + AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, + AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15, +}; + +// ZPR_4b Bit set. +static const uint8_t ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, +}; + +// ZPR_3b Register Class... +static const MCPhysReg ZPR_3b[] = { + AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, + AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, +}; + +// ZPR_3b Bit set. +static const uint8_t ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, +}; + +// DDD Register Class... +static const MCPhysReg DDD[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, + AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, + AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, + AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, + AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, + AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, + AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, + AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, + AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, + AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, + AArch64_D30_D31_D0, AArch64_D31_D0_D1, +}; + +// DDD Bit set. +static const uint8_t DDDBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, +}; + +// DDD_with_dsub0_in_FPR64_lo Register Class... +static const MCPhysReg DDD_with_dsub0_in_FPR64_lo[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, + AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, + AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, + AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, + AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, + AArch64_D15_D16_D17, +}; + +// DDD_with_dsub0_in_FPR64_lo Bit set. +static const uint8_t DDD_with_dsub0_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, +}; +// DDD_with_dsub1_in_FPR64_lo Register Class... +static const MCPhysReg DDD_with_dsub1_in_FPR64_lo[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, + AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, + AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, + AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, + AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, + AArch64_D31_D0_D1, +}; -FieldFromInstruction(fieldFromInstruction_4, uint32_t) -DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) -DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) +// DDD_with_dsub1_in_FPR64_lo Bit set. +static const uint8_t DDD_with_dsub1_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, +}; + +// DDD_with_dsub2_in_FPR64_lo Register Class... +static const MCPhysReg DDD_with_dsub2_in_FPR64_lo[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, + AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, + AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, + AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, + AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D30_D31_D0, + AArch64_D31_D0_D1, +}; + +// DDD_with_dsub2_in_FPR64_lo Bit set. +static const uint8_t DDD_with_dsub2_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x30, +}; + +// DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo Register Class... +static const MCPhysReg + DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, + AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, + AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, + AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, + AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, +}; + +// DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo Bit set. +static const uint8_t + DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, +}; + +// DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Register Class... +static const MCPhysReg + DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, + AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, + AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, + AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, + AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D31_D0_D1, +}; + +// DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Bit set. +static const uint8_t + DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x20, +}; + +// DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Register Class... +static const MCPhysReg + DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, + AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, + AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, + AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, + AArch64_D12_D13_D14, AArch64_D13_D14_D15, +}; + +// DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Bit set. +static const uint8_t + DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, +}; + +// DDDD Register Class... +static const MCPhysReg DDDD[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, + AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, + AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, + AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, + AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, + AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, + AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, + AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, + AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2, +}; + +// DDDD Bit set. +static const uint8_t DDDDBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, +}; + +// DDDD_with_dsub0_in_FPR64_lo Register Class... +static const MCPhysReg DDDD_with_dsub0_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, + AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, + AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, + AArch64_D15_D16_D17_D18, +}; + +// DDDD_with_dsub0_in_FPR64_lo Bit set. +static const uint8_t DDDD_with_dsub0_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, +}; + +// DDDD_with_dsub1_in_FPR64_lo Register Class... +static const MCPhysReg DDDD_with_dsub1_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, + AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, + AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, + AArch64_D31_D0_D1_D2, +}; + +// DDDD_with_dsub1_in_FPR64_lo Bit set. +static const uint8_t DDDD_with_dsub1_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, +}; + +// DDDD_with_dsub2_in_FPR64_lo Register Class... +static const MCPhysReg DDDD_with_dsub2_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, + AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, + AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D30_D31_D0_D1, + AArch64_D31_D0_D1_D2, +}; + +// DDDD_with_dsub2_in_FPR64_lo Bit set. +static const uint8_t DDDD_with_dsub2_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x30, +}; + +// DDDD_with_dsub3_in_FPR64_lo Register Class... +static const MCPhysReg DDDD_with_dsub3_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, + AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, + AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, + AArch64_D31_D0_D1_D2, +}; + +// DDDD_with_dsub3_in_FPR64_lo Bit set. +static const uint8_t DDDD_with_dsub3_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x38, +}; + +// DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo Register Class... +static const MCPhysReg + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, + AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, + AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, + AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, + AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, + AArch64_D14_D15_D16_D17, +}; + +// DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo Bit set. +static const uint8_t + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, +}; + +// DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Register Class... +static const MCPhysReg + DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, + AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, + AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, + AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, + AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, + AArch64_D31_D0_D1_D2, +}; + +// DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Bit set. +static const uint8_t + DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x20, +}; + +// DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Register Class... +static const MCPhysReg + DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, + AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, + AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, + AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, + AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D30_D31_D0_D1, + AArch64_D31_D0_D1_D2, +}; + +// DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Bit set. +static const uint8_t + DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x30, +}; + +// DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Register Class... +static const MCPhysReg + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, + AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, + AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, + AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, + AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, +}; + +// DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Bit set. +static const uint8_t + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, +}; + +// DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Register Class... +static const MCPhysReg + DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, + AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, + AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, + AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, + AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D31_D0_D1_D2, +}; + +// DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Bit set. +static const uint8_t + DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x20, +}; + +// DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Register Class... +static const MCPhysReg + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, + AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, + AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, + AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, + AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, +}; + +// DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Bit set. +static const uint8_t + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, +}; + +// QQ Register Class... +static const MCPhysReg QQ[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, + AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, + AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, + AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, + AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, + AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, + AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, + AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0, +}; + +// QQ Bit set. +static const uint8_t QQBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, +}; + +// ZPR2 Register Class... +static const MCPhysReg ZPR2[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, + AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, + AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, + AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, + AArch64_Z16_Z17, AArch64_Z17_Z18, AArch64_Z18_Z19, AArch64_Z19_Z20, + AArch64_Z20_Z21, AArch64_Z21_Z22, AArch64_Z22_Z23, AArch64_Z23_Z24, + AArch64_Z24_Z25, AArch64_Z25_Z26, AArch64_Z26_Z27, AArch64_Z27_Z28, + AArch64_Z28_Z29, AArch64_Z29_Z30, AArch64_Z30_Z31, AArch64_Z31_Z0, +}; + +// ZPR2 Bit set. +static const uint8_t ZPR2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, +}; + +// QQ_with_dsub_in_FPR64_lo Register Class... +static const MCPhysReg QQ_with_dsub_in_FPR64_lo[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, + AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, + AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, + AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, +}; + +// QQ_with_dsub_in_FPR64_lo Bit set. +static const uint8_t QQ_with_dsub_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, +}; + +// QQ_with_qsub1_in_FPR128_lo Register Class... +static const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, + AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, + AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, + AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q31_Q0, +}; + +// QQ_with_qsub1_in_FPR128_lo Bit set. +static const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, +}; + +// ZPR2_with_dsub_in_FPR64_lo Register Class... +static const MCPhysReg ZPR2_with_dsub_in_FPR64_lo[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, + AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, + AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, + AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, +}; + +// ZPR2_with_dsub_in_FPR64_lo Bit set. +static const uint8_t ZPR2_with_dsub_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// ZPR2_with_zsub1_in_ZPR_4b Register Class... +static const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, + AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, + AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, + AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z31_Z0, +}; + +// ZPR2_with_zsub1_in_ZPR_4b Bit set. +static const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, 0x00, 0x02, +}; + +// QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class... +static const MCPhysReg + QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, + AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, + AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, + AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, +}; + +// QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set. +static const uint8_t + QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, +}; + +// ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, + AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, + AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, + AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, +}; + +// ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set. +static const uint8_t + ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, +}; + +// ZPR2_with_zsub0_in_ZPR_3b Register Class... +static const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, + AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, +}; + +// ZPR2_with_zsub0_in_ZPR_3b Bit set. +static const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, +}; + +// ZPR2_with_zsub1_in_ZPR_3b Register Class... +static const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, + AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z31_Z0, +}; + +// ZPR2_with_zsub1_in_ZPR_3b Bit set. +static const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x02, +}; + +// ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, + AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, +}; + +// ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set. +static const uint8_t + ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, +}; + +// MPR64 Register Class... +static const MCPhysReg MPR64[] = { + AArch64_ZAD0, AArch64_ZAD1, AArch64_ZAD2, AArch64_ZAD3, + AArch64_ZAD4, AArch64_ZAD5, AArch64_ZAD6, AArch64_ZAD7, +}; + +// MPR64 Bit set. +static const uint8_t MPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, +}; + +// QQQ Register Class... +static const MCPhysReg QQQ[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, + AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, + AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, + AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, + AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, + AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, + AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, + AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, + AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, + AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, + AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1, +}; + +// QQQ Bit set. +static const uint8_t QQQBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, +}; + +// ZPR3 Register Class... +static const MCPhysReg ZPR3[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, + AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, + AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, + AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, + AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, + AArch64_Z15_Z16_Z17, AArch64_Z16_Z17_Z18, AArch64_Z17_Z18_Z19, + AArch64_Z18_Z19_Z20, AArch64_Z19_Z20_Z21, AArch64_Z20_Z21_Z22, + AArch64_Z21_Z22_Z23, AArch64_Z22_Z23_Z24, AArch64_Z23_Z24_Z25, + AArch64_Z24_Z25_Z26, AArch64_Z25_Z26_Z27, AArch64_Z26_Z27_Z28, + AArch64_Z27_Z28_Z29, AArch64_Z28_Z29_Z30, AArch64_Z29_Z30_Z31, + AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1, +}; + +// ZPR3 Bit set. +static const uint8_t ZPR3Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, +}; + +// QQQ_with_dsub_in_FPR64_lo Register Class... +static const MCPhysReg QQQ_with_dsub_in_FPR64_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, + AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, + AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, + AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, + AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, + AArch64_Q15_Q16_Q17, +}; + +// QQQ_with_dsub_in_FPR64_lo Bit set. +static const uint8_t QQQ_with_dsub_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, +}; + +// QQQ_with_qsub1_in_FPR128_lo Register Class... +static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, + AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, + AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, + AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, + AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, + AArch64_Q31_Q0_Q1, +}; + +// QQQ_with_qsub1_in_FPR128_lo Bit set. +static const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, +}; + +// QQQ_with_qsub2_in_FPR128_lo Register Class... +static const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, + AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, + AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, + AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, + AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q30_Q31_Q0, + AArch64_Q31_Q0_Q1, +}; + +// QQQ_with_qsub2_in_FPR128_lo Bit set. +static const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x30, +}; + +// ZPR3_with_dsub_in_FPR64_lo Register Class... +static const MCPhysReg ZPR3_with_dsub_in_FPR64_lo[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, + AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, + AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, + AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, + AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, + AArch64_Z15_Z16_Z17, +}; + +// ZPR3_with_dsub_in_FPR64_lo Bit set. +static const uint8_t ZPR3_with_dsub_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// ZPR3_with_zsub1_in_ZPR_4b Register Class... +static const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, + AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, + AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, + AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, + AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, + AArch64_Z31_Z0_Z1, +}; + +// ZPR3_with_zsub1_in_ZPR_4b Bit set. +static const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, 0x00, 0x02, +}; + +// ZPR3_with_zsub2_in_ZPR_4b Register Class... +static const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, + AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, + AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, + AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, + AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z30_Z31_Z0, + AArch64_Z31_Z0_Z1, +}; + +// ZPR3_with_zsub2_in_ZPR_4b Bit set. +static const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0xff, 0x00, 0x00, 0x03, +}; + +// QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class... +static const MCPhysReg + QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, + AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, + AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, + AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, + AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, +}; + +// QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set. +static const uint8_t + QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, +}; + +// QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... +static const MCPhysReg + QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, + AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, + AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, + AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, + AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q31_Q0_Q1, +}; + +// QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. +static const uint8_t + QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x20, +}; + +// ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, + AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, + AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, + AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, + AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, +}; + +// ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set. +static const uint8_t + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, +}; + +// ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, + AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, + AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, + AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, + AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z31_Z0_Z1, +}; + +// ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set. +static const uint8_t + ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0xff, 0x00, 0x00, 0x02, +}; + +// QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... +static const MCPhysReg + QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, + AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, + AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, + AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, + AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, +}; + +// QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. +static const uint8_t + QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, +}; + +// ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, + AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, + AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, + AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, + AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, +}; + +// ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set. +static const uint8_t + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, +}; + +// ZPR3_with_zsub0_in_ZPR_3b Register Class... +static const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, + AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, +}; + +// ZPR3_with_zsub0_in_ZPR_3b Bit set. +static const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, +}; + +// ZPR3_with_zsub1_in_ZPR_3b Register Class... +static const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, + AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z31_Z0_Z1, +}; + +// ZPR3_with_zsub1_in_ZPR_3b Bit set. +static const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x02, +}; + +// ZPR3_with_zsub2_in_ZPR_3b Register Class... +static const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, + AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1, +}; + +// ZPR3_with_zsub2_in_ZPR_3b Bit set. +static const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x03, +}; + +// ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, + AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, +}; + +// ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set. +static const uint8_t + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, +}; + +// ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, + AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z31_Z0_Z1, +}; + +// ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set. +static const uint8_t + ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x02, +}; + +// ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, + AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, +}; + +// ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set. +static const uint8_t + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, +}; + +// QQQQ Register Class... +static const MCPhysReg QQQQ[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, + AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, + AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, + AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, + AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, + AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, + AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, + AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, + AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, +}; + +// QQQQ Bit set. +static const uint8_t QQQQBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, +}; + +// ZPR4 Register Class... +static const MCPhysReg ZPR4[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, + AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, + AArch64_Z15_Z16_Z17_Z18, AArch64_Z16_Z17_Z18_Z19, AArch64_Z17_Z18_Z19_Z20, + AArch64_Z18_Z19_Z20_Z21, AArch64_Z19_Z20_Z21_Z22, AArch64_Z20_Z21_Z22_Z23, + AArch64_Z21_Z22_Z23_Z24, AArch64_Z22_Z23_Z24_Z25, AArch64_Z23_Z24_Z25_Z26, + AArch64_Z24_Z25_Z26_Z27, AArch64_Z25_Z26_Z27_Z28, AArch64_Z26_Z27_Z28_Z29, + AArch64_Z27_Z28_Z29_Z30, AArch64_Z28_Z29_Z30_Z31, AArch64_Z29_Z30_Z31_Z0, + AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4 Bit set. +static const uint8_t ZPR4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, +}; + +// QQQQ_with_dsub_in_FPR64_lo Register Class... +static const MCPhysReg QQQQ_with_dsub_in_FPR64_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, + AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, + AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, + AArch64_Q15_Q16_Q17_Q18, +}; + +// QQQQ_with_dsub_in_FPR64_lo Bit set. +static const uint8_t QQQQ_with_dsub_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, +}; + +// QQQQ_with_qsub1_in_FPR128_lo Register Class... +static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, + AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, + AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, + AArch64_Q31_Q0_Q1_Q2, +}; + +// QQQQ_with_qsub1_in_FPR128_lo Bit set. +static const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, +}; + +// QQQQ_with_qsub2_in_FPR128_lo Register Class... +static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, + AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, + AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q30_Q31_Q0_Q1, + AArch64_Q31_Q0_Q1_Q2, +}; + +// QQQQ_with_qsub2_in_FPR128_lo Bit set. +static const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x30, +}; + +// QQQQ_with_qsub3_in_FPR128_lo Register Class... +static const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, + AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, + AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, + AArch64_Q31_Q0_Q1_Q2, +}; + +// QQQQ_with_qsub3_in_FPR128_lo Bit set. +static const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x38, +}; + +// ZPR4_with_dsub_in_FPR64_lo Register Class... +static const MCPhysReg ZPR4_with_dsub_in_FPR64_lo[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, + AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, + AArch64_Z15_Z16_Z17_Z18, +}; + +// ZPR4_with_dsub_in_FPR64_lo Bit set. +static const uint8_t ZPR4_with_dsub_in_FPR64_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// ZPR4_with_zsub1_in_ZPR_4b Register Class... +static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, + AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, + AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub1_in_ZPR_4b Bit set. +static const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, 0x00, 0x02, +}; + +// ZPR4_with_zsub2_in_ZPR_4b Register Class... +static const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, + AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z30_Z31_Z0_Z1, + AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub2_in_ZPR_4b Bit set. +static const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x00, 0x00, 0x03, +}; + +// ZPR4_with_zsub3_in_ZPR_4b Register Class... +static const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, + AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, + AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub3_in_ZPR_4b Bit set. +static const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 0x00, 0x80, 0x03, +}; + +// QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class... +static const MCPhysReg + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, + AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, + AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, + AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, + AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, + AArch64_Q14_Q15_Q16_Q17, +}; + +// QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set. +static const uint8_t + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, +}; + +// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register +// Class... +static const MCPhysReg + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, + AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, + AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, + AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, + AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, + AArch64_Q31_Q0_Q1_Q2, +}; + +// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. +static const uint8_t + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x20, +}; + +// QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register +// Class... +static const MCPhysReg + QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, + AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, + AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, + AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, + AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q30_Q31_Q0_Q1, + AArch64_Q31_Q0_Q1_Q2, +}; + +// QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. +static const uint8_t + QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x30, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, + AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, + AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, + AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, + AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, + AArch64_Z14_Z15_Z16_Z17, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set. +static const uint8_t + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, +}; + +// ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, + AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, + AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, + AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, + AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, + AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set. +static const uint8_t + ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x00, 0x00, 0x02, +}; + +// ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, + AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, + AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, + AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, + AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z30_Z31_Z0_Z1, + AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. +static const uint8_t + ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 0x00, 0x00, 0x03, +}; + +// QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... +static const MCPhysReg + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, + AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, + AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, + AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, + AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, +}; + +// QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. +static const uint8_t + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, +}; + +// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register +// Class... +static const MCPhysReg + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, + AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, + AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, + AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, + AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q31_Q0_Q1_Q2, +}; + +// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. +static const uint8_t + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x20, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, + AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, + AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, + AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, + AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set. +static const uint8_t + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, +}; + +// ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, + AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, + AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, + AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, + AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. +static const uint8_t + ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 0x00, 0x00, 0x02, +}; + +// QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... +static const MCPhysReg + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, + AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, + AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, + AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, + AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, +}; + +// QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. +static const uint8_t + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... +static const MCPhysReg + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, + AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, + AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, + AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, + AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. +static const uint8_t + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, +}; + +// ZPR4_with_zsub0_in_ZPR_3b Register Class... +static const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, +}; + +// ZPR4_with_zsub0_in_ZPR_3b Bit set. +static const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, +}; + +// ZPR4_with_zsub1_in_ZPR_3b Register Class... +static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub1_in_ZPR_3b Bit set. +static const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x02, +}; + +// ZPR4_with_zsub2_in_ZPR_3b Register Class... +static const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub2_in_ZPR_3b Bit set. +static const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x03, +}; + +// ZPR4_with_zsub3_in_ZPR_3b Register Class... +static const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z29_Z30_Z31_Z0, + AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub3_in_ZPR_3b Bit set. +static const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x80, 0x03, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set. +static const uint8_t + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, +}; + +// ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set. +static const uint8_t + ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x02, +}; + +// ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z30_Z31_Z0_Z1, + AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. +static const uint8_t + ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x03, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set. +static const uint8_t + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, +}; + +// ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z31_Z0_Z1_Z2, +}; + +// ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. +static const uint8_t + ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x02, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... +static const MCPhysReg + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, +}; + +// ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. +static const uint8_t + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, +}; + +// GPR64x8Class Register Class... +static const MCPhysReg GPR64x8Class[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class Bit set. +static const uint8_t GPR64x8ClassBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip Bit set. +static const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noipBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, 0x03, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip Bit set. +static const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noipBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0x03, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. +static const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xdf, 0x03, +}; + +// GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. +static const uint8_t GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xef, 0x03, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 0x03, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x5f, 0x03, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x6f, 0x03, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x9f, 0x03, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xaf, 0x03, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xcf, 0x03, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x01, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xdf, 0x01, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xef, 0x01, +}; + +// GPR64x8Class_with_x8sub_1_in_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, +}; + +// GPR64x8Class_with_x8sub_1_in_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 0x03, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x2f, 0x03, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x4f, 0x03, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x8f, 0x03, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x01, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x5f, 0x01, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x6f, 0x01, +}; + +// GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, +}; + +// GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, +}; + +// GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, +}; + +// GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xdf, +}; + +// GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, +}; + +// GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xef, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaf, 0x01, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xcf, 0x01, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0x03, +}; + +// GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, +}; + +// GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x6f, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x01, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2f, 0x01, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaf, +}; + +// GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, +}; + +// GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x4f, 0x01, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xcf, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x8f, 0x01, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x5f, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x4f, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x01, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x8f, +}; + +// GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, +}; + +// GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, +}; + +// GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, +}; + +// GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2f, +}; + +// GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, +}; + +// GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, +}; + +// GPR64x8Class_with_sub_32_in_GPR32arg Register Class... +static const MCPhysReg GPR64x8Class_with_sub_32_in_GPR32arg[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, +}; + +// GPR64x8Class_with_sub_32_in_GPR32arg Bit set. +static const uint8_t GPR64x8Class_with_sub_32_in_GPR32argBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, +}; + +// MPR32 Register Class... +static const MCPhysReg MPR32[] = { + AArch64_ZAS0, + AArch64_ZAS1, + AArch64_ZAS2, + AArch64_ZAS3, +}; + +// MPR32 Bit set. +static const uint8_t MPR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64arg Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64arg[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64arg Bit set. +static const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64argBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, +}; + +// GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15 Register Class... +static const MCPhysReg GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15[] = { + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, +}; + +// GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15 Bit set. +static const uint8_t GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15Bits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15[] = + { + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, +}; + +// GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Bit +// set. +static const uint8_t + GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15[] = + { + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Bit +// set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64arg Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64arg[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64arg Bit set. +static const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64argBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, +}; + +// GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15[] = + { + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, +}; + +// GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 Bit +// set. +static const uint8_t + GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, +}; + +// GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 +// Register Class... +static const MCPhysReg + GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 + [] = { + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, +}; + +// GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15 +// Bit set. +static const uint8_t + GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, +}; + +// GPR64x8Class_with_x8sub_0_in_rtcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_0_in_rtcGPR64[] = { + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, +}; + +// GPR64x8Class_with_x8sub_0_in_rtcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_0_in_rtcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, +}; + +// GPR64x8Class_with_x8sub_2_in_rtcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_2_in_rtcGPR64[] = { + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, +}; + +// GPR64x8Class_with_x8sub_2_in_rtcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_2_in_rtcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Register Class... +static const MCPhysReg + GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15_and_GPR64x8Class_with_x8sub_6_in_GPR64noip + [] = { + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, +}; + +// GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15_and_GPR64x8Class_with_x8sub_6_in_GPR64noip +// Bit set. +static const uint8_t + GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, +}; + +// GPR64x8Class_with_x8sub_4_in_rtcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_4_in_rtcGPR64[] = { + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, +}; + +// GPR64x8Class_with_x8sub_4_in_rtcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_4_in_rtcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// GPR64x8Class_with_x8sub_6_in_GPR64arg Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_6_in_GPR64arg[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, +}; + +// GPR64x8Class_with_x8sub_6_in_GPR64arg Bit set. +static const uint8_t GPR64x8Class_with_x8sub_6_in_GPR64argBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, +}; + +// GPR64x8Class_with_x8sub_6_in_rtcGPR64 Register Class... +static const MCPhysReg GPR64x8Class_with_x8sub_6_in_rtcGPR64[] = { + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, +}; + +// GPR64x8Class_with_x8sub_6_in_rtcGPR64 Bit set. +static const uint8_t GPR64x8Class_with_x8sub_6_in_rtcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, +}; + +// MPR16 Register Class... +static const MCPhysReg MPR16[] = { + AArch64_ZAH0, + AArch64_ZAH1, +}; + +// MPR16 Bit set. +static const uint8_t MPR16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, +}; + +// MPR Register Class... +static const MCPhysReg MPR[] = { + AArch64_ZA, +}; + +// MPR Bit set. +static const uint8_t MPRBits[] = { + 0x00, + 0x04, +}; + +// MPR8 Register Class... +static const MCPhysReg MPR8[] = { + AArch64_ZAB0, +}; + +// MPR8 Bit set. +static const uint8_t MPR8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, +}; + +// end of register classes misc + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char AArch64RegClassStrings[] = { + /* 0 */ + "FPR32\0" + /* 6 */ "GPR32\0" + /* 12 */ "MPR32\0" + /* 18 */ "ZPR2\0" + /* 23 */ "ZPR3\0" + /* 28 */ "FPR64\0" + /* 34 */ "GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64\0" + /* 85 */ "GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64\0" + /* 136 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64\0" + /* 187 */ "GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64\0" + /* 238 */ "XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64\0" + /* 290 */ "XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64\0" + /* 342 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64\0" + /* 393 */ "GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64\0" + /* 444 */ "GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64\0" + /* 495 */ "GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64\0" + /* 546 */ "GPR64x8Class_with_x8sub_0_in_tcGPR64\0" + /* 583 */ "GPR64x8Class_with_x8sub_1_in_tcGPR64\0" + /* 620 */ "XSeqPairsClass_with_sube64_in_tcGPR64\0" + /* 658 */ "XSeqPairsClass_with_subo64_in_tcGPR64\0" + /* 696 */ "GPR64x8Class_with_x8sub_0_in_rtcGPR64\0" + /* 734 */ "GPR64x8Class_with_x8sub_2_in_rtcGPR64\0" + /* 772 */ "XSeqPairsClass_with_sube64_in_rtcGPR64\0" + /* 811 */ "GPR64x8Class_with_x8sub_4_in_rtcGPR64\0" + /* 849 */ "GPR64x8Class_with_x8sub_6_in_rtcGPR64\0" + /* 887 */ "MPR64\0" + /* 893 */ "ZPR4\0" + /* 898 */ "GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_" + "MatrixIndexGPR32_12_15\0" + /* 971 */ "GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_" + "MatrixIndexGPR32_12_15\0" + /* 1044 */ "GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_" + "x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15\0" + /* 1158 */ "GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15\0" + /* 1209 */ "XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15\0" + /* 1262 */ "WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15\0" + /* 1315 */ "FPR16\0" + /* 1321 */ "MPR16\0" + /* 1327 */ "FPR128\0" + /* 1334 */ "MPR128\0" + /* 1341 */ "FPR8\0" + /* 1346 */ "MPR8\0" + /* 1351 */ "DDDD\0" + /* 1356 */ "QQQQ\0" + /* 1361 */ "CCR\0" + /* 1365 */ "MPR\0" + /* 1369 */ "PPR\0" + /* 1373 */ "ZPR\0" + /* 1377 */ "PPR_3b\0" + /* 1384 */ "ZPR2_with_zsub0_in_ZPR_3b\0" + /* 1410 */ "ZPR3_with_zsub0_in_ZPR_3b\0" + /* 1436 */ "ZPR4_with_zsub0_in_ZPR_3b\0" + /* 1462 */ "ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b\0" + /* 1519 */ "ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b\0" + /* 1576 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b\0" + /* 1633 */ "ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b\0" + /* 1689 */ "ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b\0" + /* 1746 */ "ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b\0" + /* 1802 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b\0" + /* 1859 */ "ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b\0" + /* 1915 */ "ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b\0" + /* 1971 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b\0" + /* 2028 */ "ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b\0" + /* 2085 */ "ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b\0" + /* 2142 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b\0" + /* 2199 */ "ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b\0" + /* 2255 */ "ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b\0" + /* 2312 */ "ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b\0" + /* 2368 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b\0" + /* 2425 */ "ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b\0" + /* 2481 */ "ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b\0" + /* 2537 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b\0" + /* 2594 */ "GPR64x8Class_with_sub_32_in_GPR32arg\0" + /* 2631 */ "XSeqPairsClass_with_sub_32_in_GPR32arg\0" + /* 2670 */ "WSeqPairsClass_with_sube32_in_GPR32arg\0" + /* 2709 */ "GPR64x8Class_with_x8sub_2_in_GPR64arg\0" + /* 2747 */ "GPR64x8Class_with_x8sub_4_in_GPR64arg\0" + /* 2785 */ "GPR64x8Class_with_x8sub_6_in_GPR64arg\0" + /* 2823 */ "GPR32all\0" + /* 2832 */ "GPR64all\0" + /* 2841 */ "WSeqPairsClass_with_subo32_in_GPR32common\0" + /* 2883 */ "XSeqPairsClass_with_subo64_in_GPR64common\0" + /* 2925 */ "DDDD_with_dsub0_in_FPR64_lo\0" + /* 2953 */ "DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo\0" + /* 3013 */ "DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo\0" + /* 3071 */ "DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo\0" + /* 3127 */ "DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo\0" + /* 3187 */ "DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo\0" + /* 3247 */ "DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo\0" + /* 3305 */ "DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo\0" + /* 3363 */ "DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo\0" + /* 3423 */ "DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo\0" + /* 3483 */ "DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo\0" + /* 3543 */ "ZPR2_with_dsub_in_FPR64_lo\0" + /* 3570 */ "ZPR3_with_dsub_in_FPR64_lo\0" + /* 3597 */ "ZPR4_with_dsub_in_FPR64_lo\0" + /* 3624 */ "QQQQ_with_dsub_in_FPR64_lo\0" + /* 3651 */ "FPR32_with_hsub_in_FPR16_lo\0" + /* 3679 */ "QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo\0" + /* 3739 */ "QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo\0" + /* 3797 */ "QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo\0" + /* 3853 */ "QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo\0" + /* 3913 */ "QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo\0" + /* 3975 */ "QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo\0" + /* 4033 */ "QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo\0" + /* 4093 */ "QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo\0" + /* 4153 */ "QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo\0" + /* 4215 */ "QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo\0" + /* 4277 */ "GPR64common_and_GPR64noip\0" + /* 4303 */ "GPR64x8Class_with_x8sub_0_in_GPR64noip\0" + /* 4342 */ "GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_" + "x8sub_2_in_GPR64noip\0" + /* 4422 */ "GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_" + "x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_" + "GPR64noip\0" + /* 4545 */ "XSeqPairsClass_with_sube64_in_GPR64noip\0" + /* 4585 */ "XSeqPairsClass_with_subo64_in_GPR64noip\0" + /* 4625 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\0" + /* 4748 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\0" + /* 4871 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_" + "and_GPR64x8Class_with_x8sub_4_in_GPR64noip\0" + /* 5037 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_" + "GPR64noip\0" + /* 5162 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_4_in_GPR64noip\0" + /* 5244 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_" + "and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" + /* 5410 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" + /* 5533 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_" + "and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" + /* 5699 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" + /* 5822 */ "GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_" + "MatrixIndexGPR32_12_15_and_GPR64x8Class_with_x8sub_6_in_" + "GPR64noip\0" + /* 5938 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_" + "and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_" + "with_x8sub_6_in_GPR64noip\0" + /* 6147 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_" + "and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" + /* 6313 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_" + "and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" + /* 6479 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_" + "GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" + /* 6647 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_" + "GPR64noip\0" + /* 6772 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_" + "GPR64noip\0" + /* 6897 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_" + "x8sub_6_in_GPR64noip\0" + /* 6979 */ "GPR32sp\0" + /* 6987 */ "GPR64sp\0" + /* 6995 */ "GPR64x8Class\0" + /* 7008 */ "WSeqPairsClass\0" + /* 7023 */ "XSeqPairsClass\0" + /* 7038 */ "GPR32sponly\0" + /* 7050 */ "GPR64sponly\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterClass AArch64MCRegisterClasses[] = + { + {FPR8, FPR8Bits, sizeof(FPR8Bits)}, + {FPR16, FPR16Bits, sizeof(FPR16Bits)}, + {FPR16_lo, FPR16_loBits, sizeof(FPR16_loBits)}, + {PPR, PPRBits, sizeof(PPRBits)}, + {PPR_3b, PPR_3bBits, sizeof(PPR_3bBits)}, + {GPR32all, GPR32allBits, sizeof(GPR32allBits)}, + {FPR32, FPR32Bits, sizeof(FPR32Bits)}, + {GPR32, GPR32Bits, sizeof(GPR32Bits)}, + {GPR32sp, GPR32spBits, sizeof(GPR32spBits)}, + {GPR32common, GPR32commonBits, sizeof(GPR32commonBits)}, + {FPR32_with_hsub_in_FPR16_lo, FPR32_with_hsub_in_FPR16_loBits, + sizeof(FPR32_with_hsub_in_FPR16_loBits)}, + {GPR32arg, GPR32argBits, sizeof(GPR32argBits)}, + {MatrixIndexGPR32_12_15, MatrixIndexGPR32_12_15Bits, + sizeof(MatrixIndexGPR32_12_15Bits)}, + {CCR, CCRBits, sizeof(CCRBits)}, + {GPR32sponly, GPR32sponlyBits, sizeof(GPR32sponlyBits)}, + {WSeqPairsClass, WSeqPairsClassBits, sizeof(WSeqPairsClassBits)}, + {WSeqPairsClass_with_subo32_in_GPR32common, + WSeqPairsClass_with_subo32_in_GPR32commonBits, + sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits)}, + {WSeqPairsClass_with_sube32_in_GPR32arg, + WSeqPairsClass_with_sube32_in_GPR32argBits, + sizeof(WSeqPairsClass_with_sube32_in_GPR32argBits)}, + {WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15, + WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15Bits, + sizeof(WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15Bits)}, + {GPR64all, GPR64allBits, sizeof(GPR64allBits)}, + {FPR64, FPR64Bits, sizeof(FPR64Bits)}, + {GPR64, GPR64Bits, sizeof(GPR64Bits)}, + {GPR64sp, GPR64spBits, sizeof(GPR64spBits)}, + {GPR64common, GPR64commonBits, sizeof(GPR64commonBits)}, + {GPR64noip, GPR64noipBits, sizeof(GPR64noipBits)}, + {GPR64common_and_GPR64noip, GPR64common_and_GPR64noipBits, + sizeof(GPR64common_and_GPR64noipBits)}, + {tcGPR64, tcGPR64Bits, sizeof(tcGPR64Bits)}, + {GPR64noip_and_tcGPR64, GPR64noip_and_tcGPR64Bits, + sizeof(GPR64noip_and_tcGPR64Bits)}, + {FPR64_lo, FPR64_loBits, sizeof(FPR64_loBits)}, + {GPR64arg, GPR64argBits, sizeof(GPR64argBits)}, + {GPR64_with_sub_32_in_MatrixIndexGPR32_12_15, + GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits, + sizeof(GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits)}, + {rtcGPR64, rtcGPR64Bits, sizeof(rtcGPR64Bits)}, + {GPR64sponly, GPR64sponlyBits, sizeof(GPR64sponlyBits)}, + {DD, DDBits, sizeof(DDBits)}, + {DD_with_dsub0_in_FPR64_lo, DD_with_dsub0_in_FPR64_loBits, + sizeof(DD_with_dsub0_in_FPR64_loBits)}, + {DD_with_dsub1_in_FPR64_lo, DD_with_dsub1_in_FPR64_loBits, + sizeof(DD_with_dsub1_in_FPR64_loBits)}, + {XSeqPairsClass, XSeqPairsClassBits, sizeof(XSeqPairsClassBits)}, + {DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo, + DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loBits, + sizeof(DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loBits)}, + {XSeqPairsClass_with_subo64_in_GPR64common, + XSeqPairsClass_with_subo64_in_GPR64commonBits, + sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits)}, + {XSeqPairsClass_with_subo64_in_GPR64noip, + XSeqPairsClass_with_subo64_in_GPR64noipBits, + sizeof(XSeqPairsClass_with_subo64_in_GPR64noipBits)}, + {XSeqPairsClass_with_sube64_in_GPR64noip, + XSeqPairsClass_with_sube64_in_GPR64noipBits, + sizeof(XSeqPairsClass_with_sube64_in_GPR64noipBits)}, + {XSeqPairsClass_with_sube64_in_tcGPR64, + XSeqPairsClass_with_sube64_in_tcGPR64Bits, + sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits)}, + {XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64, + XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits, + sizeof(XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits)}, + {XSeqPairsClass_with_subo64_in_tcGPR64, + XSeqPairsClass_with_subo64_in_tcGPR64Bits, + sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits)}, + {XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64, + XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits, + sizeof(XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits)}, + {XSeqPairsClass_with_sub_32_in_GPR32arg, + XSeqPairsClass_with_sub_32_in_GPR32argBits, + sizeof(XSeqPairsClass_with_sub_32_in_GPR32argBits)}, + {XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15, + XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15Bits, + sizeof(XSeqPairsClass_with_sub_32_in_MatrixIndexGPR32_12_15Bits)}, + {XSeqPairsClass_with_sube64_in_rtcGPR64, + XSeqPairsClass_with_sube64_in_rtcGPR64Bits, + sizeof(XSeqPairsClass_with_sube64_in_rtcGPR64Bits)}, + {FPR128, FPR128Bits, sizeof(FPR128Bits)}, + {ZPR, ZPRBits, sizeof(ZPRBits)}, + {FPR128_lo, FPR128_loBits, sizeof(FPR128_loBits)}, + {MPR128, MPR128Bits, sizeof(MPR128Bits)}, + {ZPR_4b, ZPR_4bBits, sizeof(ZPR_4bBits)}, + {ZPR_3b, ZPR_3bBits, sizeof(ZPR_3bBits)}, + {DDD, DDDBits, sizeof(DDDBits)}, + {DDD_with_dsub0_in_FPR64_lo, DDD_with_dsub0_in_FPR64_loBits, + sizeof(DDD_with_dsub0_in_FPR64_loBits)}, + {DDD_with_dsub1_in_FPR64_lo, DDD_with_dsub1_in_FPR64_loBits, + sizeof(DDD_with_dsub1_in_FPR64_loBits)}, + {DDD_with_dsub2_in_FPR64_lo, DDD_with_dsub2_in_FPR64_loBits, + sizeof(DDD_with_dsub2_in_FPR64_loBits)}, + {DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo, + DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loBits, + sizeof(DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loBits)}, + {DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo, + DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits, + sizeof(DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits)}, + {DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo, + DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits, + sizeof(DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits)}, + {DDDD, DDDDBits, sizeof(DDDDBits)}, + {DDDD_with_dsub0_in_FPR64_lo, DDDD_with_dsub0_in_FPR64_loBits, + sizeof(DDDD_with_dsub0_in_FPR64_loBits)}, + {DDDD_with_dsub1_in_FPR64_lo, DDDD_with_dsub1_in_FPR64_loBits, + sizeof(DDDD_with_dsub1_in_FPR64_loBits)}, + {DDDD_with_dsub2_in_FPR64_lo, DDDD_with_dsub2_in_FPR64_loBits, + sizeof(DDDD_with_dsub2_in_FPR64_loBits)}, + {DDDD_with_dsub3_in_FPR64_lo, DDDD_with_dsub3_in_FPR64_loBits, + sizeof(DDDD_with_dsub3_in_FPR64_loBits)}, + {DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo, + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loBits, + sizeof( + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loBits)}, + {DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo, + DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits, + sizeof( + DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits)}, + {DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo, + DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits, + sizeof( + DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits)}, + {DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo, + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits, + sizeof( + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits)}, + {DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo, + DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits, + sizeof( + DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits)}, + {DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo, + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits, + sizeof( + DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits)}, + {QQ, QQBits, sizeof(QQBits)}, + {ZPR2, ZPR2Bits, sizeof(ZPR2Bits)}, + {QQ_with_dsub_in_FPR64_lo, QQ_with_dsub_in_FPR64_loBits, + sizeof(QQ_with_dsub_in_FPR64_loBits)}, + {QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, + sizeof(QQ_with_qsub1_in_FPR128_loBits)}, + {ZPR2_with_dsub_in_FPR64_lo, ZPR2_with_dsub_in_FPR64_loBits, + sizeof(ZPR2_with_dsub_in_FPR64_loBits)}, + {ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, + sizeof(ZPR2_with_zsub1_in_ZPR_4bBits)}, + {QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo, + QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loBits, + sizeof(QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loBits)}, + {ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b, + ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, + sizeof(ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits)}, + {ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, + sizeof(ZPR2_with_zsub0_in_ZPR_3bBits)}, + {ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, + sizeof(ZPR2_with_zsub1_in_ZPR_3bBits)}, + {ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b, + ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, + sizeof(ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits)}, + {MPR64, MPR64Bits, sizeof(MPR64Bits)}, + {QQQ, QQQBits, sizeof(QQQBits)}, + {ZPR3, ZPR3Bits, sizeof(ZPR3Bits)}, + {QQQ_with_dsub_in_FPR64_lo, QQQ_with_dsub_in_FPR64_loBits, + sizeof(QQQ_with_dsub_in_FPR64_loBits)}, + {QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, + sizeof(QQQ_with_qsub1_in_FPR128_loBits)}, + {QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, + sizeof(QQQ_with_qsub2_in_FPR128_loBits)}, + {ZPR3_with_dsub_in_FPR64_lo, ZPR3_with_dsub_in_FPR64_loBits, + sizeof(ZPR3_with_dsub_in_FPR64_loBits)}, + {ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, + sizeof(ZPR3_with_zsub1_in_ZPR_4bBits)}, + {ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, + sizeof(ZPR3_with_zsub2_in_ZPR_4bBits)}, + {QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo, + QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loBits, + sizeof(QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loBits)}, + {QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, + QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, + sizeof( + QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits)}, + {ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b, + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, + sizeof(ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits)}, + {ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, + ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, + sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits)}, + {QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo, + QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loBits, + sizeof(QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loBits)}, + {ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b, + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, + sizeof(ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits)}, + {ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, + sizeof(ZPR3_with_zsub0_in_ZPR_3bBits)}, + {ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, + sizeof(ZPR3_with_zsub1_in_ZPR_3bBits)}, + {ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, + sizeof(ZPR3_with_zsub2_in_ZPR_3bBits)}, + {ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b, + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, + sizeof(ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits)}, + {ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, + ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, + sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits)}, + {ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b, + ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, + sizeof(ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits)}, + {QQQQ, QQQQBits, sizeof(QQQQBits)}, + {ZPR4, ZPR4Bits, sizeof(ZPR4Bits)}, + {QQQQ_with_dsub_in_FPR64_lo, QQQQ_with_dsub_in_FPR64_loBits, + sizeof(QQQQ_with_dsub_in_FPR64_loBits)}, + {QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, + sizeof(QQQQ_with_qsub1_in_FPR128_loBits)}, + {QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, + sizeof(QQQQ_with_qsub2_in_FPR128_loBits)}, + {QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, + sizeof(QQQQ_with_qsub3_in_FPR128_loBits)}, + {ZPR4_with_dsub_in_FPR64_lo, ZPR4_with_dsub_in_FPR64_loBits, + sizeof(ZPR4_with_dsub_in_FPR64_loBits)}, + {ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, + sizeof(ZPR4_with_zsub1_in_ZPR_4bBits)}, + {ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, + sizeof(ZPR4_with_zsub2_in_ZPR_4bBits)}, + {ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, + sizeof(ZPR4_with_zsub3_in_ZPR_4bBits)}, + {QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo, + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, + sizeof( + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loBits)}, + {QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, + sizeof( + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits)}, + {QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, + QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, + sizeof( + QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits)}, + {ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b, + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, + sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits)}, + {ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, + ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, + sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits)}, + {ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, + ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, + sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits)}, + {QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo, + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, + sizeof( + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loBits)}, + {QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, + sizeof( + QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits)}, + {ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b, + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, + sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits)}, + {ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, + ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, + sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits)}, + {QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo, + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, + sizeof( + QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loBits)}, + {ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b, + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, + sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits)}, + {ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, + sizeof(ZPR4_with_zsub0_in_ZPR_3bBits)}, + {ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, + sizeof(ZPR4_with_zsub1_in_ZPR_3bBits)}, + {ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, + sizeof(ZPR4_with_zsub2_in_ZPR_3bBits)}, + {ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, + sizeof(ZPR4_with_zsub3_in_ZPR_3bBits)}, + {ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b, + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, + sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits)}, + {ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, + ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, + sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits)}, + {ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, + ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, + sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits)}, + {ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b, + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, + sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits)}, + {ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, + ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, + sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits)}, + {ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b, + ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, + sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits)}, + {GPR64x8Class, GPR64x8ClassBits, sizeof(GPR64x8ClassBits)}, + {GPR64x8Class_with_x8sub_0_in_GPR64noip, + GPR64x8Class_with_x8sub_0_in_GPR64noipBits, + sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noipBits, + sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof(GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip, + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_tcGPR64, + GPR64x8Class_with_x8sub_0_in_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64Bits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64, + GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64Bits)}, + {GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip, + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_1_in_tcGPR64, + GPR64x8Class_with_x8sub_1_in_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_1_in_tcGPR64Bits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip, + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64, + GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64Bits)}, + {GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64Bits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64, + GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64Bits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64Bits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64, + GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64Bits)}, + {GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64, + GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64Bits)}, + {GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64, + GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64Bits)}, + {GPR64x8Class_with_sub_32_in_GPR32arg, + GPR64x8Class_with_sub_32_in_GPR32argBits, + sizeof(GPR64x8Class_with_sub_32_in_GPR32argBits)}, + {MPR32, MPR32Bits, sizeof(MPR32Bits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64arg, + GPR64x8Class_with_x8sub_2_in_GPR64argBits, + sizeof(GPR64x8Class_with_x8sub_2_in_GPR64argBits)}, + {GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15, + GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15Bits, + sizeof(GPR64x8Class_with_sub_32_in_MatrixIndexGPR32_12_15Bits)}, + {GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15, + GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits, + sizeof( + GPR64x8Class_with_x8sub_2_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15, + GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64arg, + GPR64x8Class_with_x8sub_4_in_GPR64argBits, + sizeof(GPR64x8Class_with_x8sub_4_in_GPR64argBits)}, + {GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15, + GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits, + sizeof( + GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits)}, + {GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15, + GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits, + sizeof( + GPR64x8Class_with_sub_32_in_GPR32arg_and_GPR64x8Class_with_x8sub_6_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15Bits)}, + {GPR64x8Class_with_x8sub_0_in_rtcGPR64, + GPR64x8Class_with_x8sub_0_in_rtcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_0_in_rtcGPR64Bits)}, + {GPR64x8Class_with_x8sub_2_in_rtcGPR64, + GPR64x8Class_with_x8sub_2_in_rtcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_2_in_rtcGPR64Bits)}, + {GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, + GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, + sizeof( + GPR64x8Class_with_x8sub_4_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits)}, + {GPR64x8Class_with_x8sub_4_in_rtcGPR64, + GPR64x8Class_with_x8sub_4_in_rtcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_4_in_rtcGPR64Bits)}, + {GPR64x8Class_with_x8sub_6_in_GPR64arg, + GPR64x8Class_with_x8sub_6_in_GPR64argBits, + sizeof(GPR64x8Class_with_x8sub_6_in_GPR64argBits)}, + {GPR64x8Class_with_x8sub_6_in_rtcGPR64, + GPR64x8Class_with_x8sub_6_in_rtcGPR64Bits, + sizeof(GPR64x8Class_with_x8sub_6_in_rtcGPR64Bits)}, + {MPR16, MPR16Bits, sizeof(MPR16Bits)}, + {MPR, MPRBits, sizeof(MPRBits)}, + {MPR8, MPR8Bits, sizeof(MPR8Bits)}, +}; + +#endif // GET_REGINFO_MC_DESC + +#ifdef GET_ASM_WRITER +#undef GET_ASM_WRITER + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +typedef struct MCMnemonic { + const char *first; + uint64_t second; +} MCMnemonic; + +static MCMnemonic createMnemonic(const char *first, uint64_t second) { + MCMnemonic mnemonic; + mnemonic.first = first; + mnemonic.second = second; + return mnemonic; +} + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +MCMnemonic AArch64_getMnemonic(const MCInst *MI) { + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "sha1su0\t\0" + /* 9 */ "sha512su0\t\0" + /* 20 */ "sha256su0\t\0" + /* 31 */ "st64bv0\t\0" + /* 40 */ "ld1\t\0" + /* 45 */ "trn1\t\0" + /* 51 */ "zip1\t\0" + /* 57 */ "uzp1\t\0" + /* 63 */ "dcps1\t\0" + /* 70 */ "sm3ss1\t\0" + /* 78 */ "st1\t\0" + /* 83 */ "sha1su1\t\0" + /* 92 */ "sha512su1\t\0" + /* 103 */ "sha256su1\t\0" + /* 114 */ "sm3partw1\t\0" + /* 125 */ "rax1\t\0" + /* 131 */ "rev32\t\0" + /* 138 */ "ld2\t\0" + /* 143 */ "sha512h2\t\0" + /* 153 */ "sha256h2\t\0" + /* 163 */ "sabal2\t\0" + /* 171 */ "uabal2\t\0" + /* 179 */ "sqdmlal2\t\0" + /* 189 */ "fmlal2\t\0" + /* 197 */ "smlal2\t\0" + /* 205 */ "umlal2\t\0" + /* 213 */ "ssubl2\t\0" + /* 221 */ "usubl2\t\0" + /* 229 */ "sabdl2\t\0" + /* 237 */ "uabdl2\t\0" + /* 245 */ "saddl2\t\0" + /* 253 */ "uaddl2\t\0" + /* 261 */ "sshll2\t\0" + /* 269 */ "ushll2\t\0" + /* 277 */ "sqdmull2\t\0" + /* 287 */ "pmull2\t\0" + /* 295 */ "smull2\t\0" + /* 303 */ "umull2\t\0" + /* 311 */ "sqdmlsl2\t\0" + /* 321 */ "fmlsl2\t\0" + /* 329 */ "smlsl2\t\0" + /* 337 */ "umlsl2\t\0" + /* 345 */ "fcvtl2\t\0" + /* 353 */ "rsubhn2\t\0" + /* 362 */ "raddhn2\t\0" + /* 371 */ "sqshrn2\t\0" + /* 380 */ "uqshrn2\t\0" + /* 389 */ "sqrshrn2\t\0" + /* 399 */ "uqrshrn2\t\0" + /* 409 */ "trn2\t\0" + /* 415 */ "bfcvtn2\t\0" + /* 424 */ "sqxtn2\t\0" + /* 432 */ "uqxtn2\t\0" + /* 440 */ "sqshrun2\t\0" + /* 450 */ "sqrshrun2\t\0" + /* 461 */ "sqxtun2\t\0" + /* 470 */ "fcvtxn2\t\0" + /* 479 */ "zip2\t\0" + /* 485 */ "uzp2\t\0" + /* 491 */ "dcps2\t\0" + /* 498 */ "st2\t\0" + /* 503 */ "ssubw2\t\0" + /* 511 */ "usubw2\t\0" + /* 519 */ "saddw2\t\0" + /* 527 */ "uaddw2\t\0" + /* 535 */ "sm3partw2\t\0" + /* 546 */ "ld3\t\0" + /* 551 */ "eor3\t\0" + /* 557 */ "dcps3\t\0" + /* 564 */ "st3\t\0" + /* 569 */ "rev64\t\0" + /* 576 */ "ld4\t\0" + /* 581 */ "st4\t\0" + /* 586 */ "setf16\t\0" + /* 594 */ "rev16\t\0" + /* 601 */ "setf8\t\0" + /* 608 */ "sm3tt1a\t\0" + /* 617 */ "sm3tt2a\t\0" + /* 626 */ "braa\t\0" + /* 632 */ "ldraa\t\0" + /* 639 */ "blraa\t\0" + /* 646 */ "saba\t\0" + /* 652 */ "uaba\t\0" + /* 658 */ "pacda\t\0" + /* 665 */ "ldadda\t\0" + /* 673 */ "fadda\t\0" + /* 680 */ "autda\t\0" + /* 687 */ "pacga\t\0" + /* 694 */ "addha\t\0" + /* 701 */ "pacia\t\0" + /* 708 */ "autia\t\0" + /* 715 */ "brka\t\0" + /* 721 */ "fcmla\t\0" + /* 728 */ "fmla\t\0" + /* 734 */ "bfmmla\t\0" + /* 742 */ "usmmla\t\0" + /* 750 */ "ummla\t\0" + /* 757 */ "fnmla\t\0" + /* 764 */ "ldsmina\t\0" + /* 773 */ "ldumina\t\0" + /* 782 */ "brkpa\t\0" + /* 789 */ "bfmopa\t\0" + /* 797 */ "usmopa\t\0" + /* 805 */ "sumopa\t\0" + /* 813 */ "caspa\t\0" + /* 820 */ "swpa\t\0" + /* 826 */ "fexpa\t\0" + /* 833 */ "ldclra\t\0" + /* 841 */ "ldeora\t\0" + /* 849 */ "srsra\t\0" + /* 856 */ "ursra\t\0" + /* 863 */ "ssra\t\0" + /* 869 */ "usra\t\0" + /* 875 */ "casa\t\0" + /* 881 */ "ldseta\t\0" + /* 889 */ "frinta\t\0" + /* 897 */ "clasta\t\0" + /* 905 */ "addva\t\0" + /* 912 */ "mova\t\0" + /* 918 */ "ldsmaxa\t\0" + /* 927 */ "ldumaxa\t\0" + /* 936 */ "pacdza\t\0" + /* 944 */ "autdza\t\0" + /* 952 */ "paciza\t\0" + /* 960 */ "autiza\t\0" + /* 968 */ "ld1b\t\0" + /* 974 */ "ldff1b\t\0" + /* 982 */ "ldnf1b\t\0" + /* 990 */ "ldnt1b\t\0" + /* 998 */ "stnt1b\t\0" + /* 1006 */ "st1b\t\0" + /* 1012 */ "sm3tt1b\t\0" + /* 1021 */ "crc32b\t\0" + /* 1029 */ "ld2b\t\0" + /* 1035 */ "st2b\t\0" + /* 1041 */ "sm3tt2b\t\0" + /* 1050 */ "ld3b\t\0" + /* 1056 */ "st3b\t\0" + /* 1062 */ "ld64b\t\0" + /* 1069 */ "st64b\t\0" + /* 1076 */ "ld4b\t\0" + /* 1082 */ "st4b\t\0" + /* 1088 */ "ldaddab\t\0" + /* 1097 */ "ldsminab\t\0" + /* 1107 */ "lduminab\t\0" + /* 1117 */ "swpab\t\0" + /* 1124 */ "brab\t\0" + /* 1130 */ "ldrab\t\0" + /* 1137 */ "blrab\t\0" + /* 1144 */ "ldclrab\t\0" + /* 1153 */ "ldeorab\t\0" + /* 1162 */ "casab\t\0" + /* 1169 */ "ldsetab\t\0" + /* 1178 */ "ldsmaxab\t\0" + /* 1188 */ "ldumaxab\t\0" + /* 1198 */ "crc32cb\t\0" + /* 1207 */ "sqdecb\t\0" + /* 1215 */ "uqdecb\t\0" + /* 1223 */ "sqincb\t\0" + /* 1231 */ "uqincb\t\0" + /* 1239 */ "pacdb\t\0" + /* 1246 */ "ldaddb\t\0" + /* 1254 */ "autdb\t\0" + /* 1261 */ "prfb\t\0" + /* 1267 */ "flogb\t\0" + /* 1274 */ "pacib\t\0" + /* 1281 */ "autib\t\0" + /* 1288 */ "brkb\t\0" + /* 1294 */ "sabalb\t\0" + /* 1302 */ "uabalb\t\0" + /* 1310 */ "ldaddalb\t\0" + /* 1320 */ "sqdmlalb\t\0" + /* 1330 */ "bfmlalb\t\0" + /* 1339 */ "smlalb\t\0" + /* 1347 */ "umlalb\t\0" + /* 1355 */ "ldsminalb\t\0" + /* 1366 */ "lduminalb\t\0" + /* 1377 */ "swpalb\t\0" + /* 1385 */ "ldclralb\t\0" + /* 1395 */ "ldeoralb\t\0" + /* 1405 */ "casalb\t\0" + /* 1413 */ "ldsetalb\t\0" + /* 1423 */ "ldsmaxalb\t\0" + /* 1434 */ "ldumaxalb\t\0" + /* 1445 */ "ssublb\t\0" + /* 1453 */ "usublb\t\0" + /* 1461 */ "sbclb\t\0" + /* 1468 */ "adclb\t\0" + /* 1475 */ "sabdlb\t\0" + /* 1483 */ "uabdlb\t\0" + /* 1491 */ "ldaddlb\t\0" + /* 1500 */ "saddlb\t\0" + /* 1508 */ "uaddlb\t\0" + /* 1516 */ "sshllb\t\0" + /* 1524 */ "ushllb\t\0" + /* 1532 */ "sqdmullb\t\0" + /* 1542 */ "pmullb\t\0" + /* 1550 */ "smullb\t\0" + /* 1558 */ "umullb\t\0" + /* 1566 */ "ldsminlb\t\0" + /* 1576 */ "lduminlb\t\0" + /* 1586 */ "swplb\t\0" + /* 1593 */ "ldclrlb\t\0" + /* 1602 */ "ldeorlb\t\0" + /* 1611 */ "caslb\t\0" + /* 1618 */ "sqdmlslb\t\0" + /* 1628 */ "fmlslb\t\0" + /* 1636 */ "smlslb\t\0" + /* 1644 */ "umlslb\t\0" + /* 1652 */ "ldsetlb\t\0" + /* 1661 */ "ldsmaxlb\t\0" + /* 1671 */ "ldumaxlb\t\0" + /* 1681 */ "dmb\t\0" + /* 1686 */ "rsubhnb\t\0" + /* 1695 */ "raddhnb\t\0" + /* 1704 */ "ldsminb\t\0" + /* 1713 */ "lduminb\t\0" + /* 1722 */ "sqshrnb\t\0" + /* 1731 */ "uqshrnb\t\0" + /* 1740 */ "sqrshrnb\t\0" + /* 1750 */ "uqrshrnb\t\0" + /* 1760 */ "sqxtnb\t\0" + /* 1768 */ "uqxtnb\t\0" + /* 1776 */ "sqshrunb\t\0" + /* 1786 */ "sqrshrunb\t\0" + /* 1797 */ "sqxtunb\t\0" + /* 1806 */ "ld1rob\t\0" + /* 1814 */ "brkpb\t\0" + /* 1821 */ "swpb\t\0" + /* 1827 */ "ld1rqb\t\0" + /* 1835 */ "ld1rb\t\0" + /* 1842 */ "ldarb\t\0" + /* 1849 */ "ldlarb\t\0" + /* 1857 */ "ldrb\t\0" + /* 1863 */ "ldclrb\t\0" + /* 1871 */ "stllrb\t\0" + /* 1879 */ "stlrb\t\0" + /* 1886 */ "ldeorb\t\0" + /* 1894 */ "ldaprb\t\0" + /* 1902 */ "ldtrb\t\0" + /* 1909 */ "strb\t\0" + /* 1915 */ "sttrb\t\0" + /* 1922 */ "ldurb\t\0" + /* 1929 */ "stlurb\t\0" + /* 1937 */ "ldapurb\t\0" + /* 1946 */ "sturb\t\0" + /* 1953 */ "ldaxrb\t\0" + /* 1961 */ "ldxrb\t\0" + /* 1968 */ "stlxrb\t\0" + /* 1976 */ "stxrb\t\0" + /* 1983 */ "ld1sb\t\0" + /* 1990 */ "ldff1sb\t\0" + /* 1999 */ "ldnf1sb\t\0" + /* 2008 */ "ldnt1sb\t\0" + /* 2017 */ "casb\t\0" + /* 2023 */ "dsb\t\0" + /* 2028 */ "isb\t\0" + /* 2033 */ "fmsb\t\0" + /* 2039 */ "fnmsb\t\0" + /* 2046 */ "ld1rsb\t\0" + /* 2054 */ "ldrsb\t\0" + /* 2061 */ "ldtrsb\t\0" + /* 2069 */ "ldursb\t\0" + /* 2077 */ "ldapursb\t\0" + /* 2087 */ "tsb\t\0" + /* 2092 */ "ldsetb\t\0" + /* 2100 */ "ssubltb\t\0" + /* 2109 */ "cntb\t\0" + /* 2115 */ "eortb\t\0" + /* 2122 */ "clastb\t\0" + /* 2130 */ "sxtb\t\0" + /* 2136 */ "uxtb\t\0" + /* 2142 */ "fsub\t\0" + /* 2148 */ "shsub\t\0" + /* 2155 */ "uhsub\t\0" + /* 2162 */ "fmsub\t\0" + /* 2169 */ "fnmsub\t\0" + /* 2177 */ "sqsub\t\0" + /* 2184 */ "uqsub\t\0" + /* 2191 */ "revb\t\0" + /* 2197 */ "ssubwb\t\0" + /* 2205 */ "usubwb\t\0" + /* 2213 */ "saddwb\t\0" + /* 2221 */ "uaddwb\t\0" + /* 2229 */ "ldsmaxb\t\0" + /* 2238 */ "ldumaxb\t\0" + /* 2247 */ "pacdzb\t\0" + /* 2255 */ "autdzb\t\0" + /* 2263 */ "pacizb\t\0" + /* 2271 */ "autizb\t\0" + /* 2279 */ "sha1c\t\0" + /* 2286 */ "sbc\t\0" + /* 2291 */ "adc\t\0" + /* 2296 */ "bic\t\0" + /* 2301 */ "aesimc\t\0" + /* 2309 */ "aesmc\t\0" + /* 2316 */ "csinc\t\0" + /* 2323 */ "hvc\t\0" + /* 2328 */ "svc\t\0" + /* 2333 */ "ld1d\t\0" + /* 2339 */ "ldff1d\t\0" + /* 2347 */ "ldnf1d\t\0" + /* 2355 */ "ldnt1d\t\0" + /* 2363 */ "stnt1d\t\0" + /* 2371 */ "st1d\t\0" + /* 2377 */ "ld2d\t\0" + /* 2383 */ "st2d\t\0" + /* 2389 */ "ld3d\t\0" + /* 2395 */ "st3d\t\0" + /* 2401 */ "ld4d\t\0" + /* 2407 */ "st4d\t\0" + /* 2413 */ "fmad\t\0" + /* 2419 */ "fnmad\t\0" + /* 2426 */ "ftmad\t\0" + /* 2433 */ "fabd\t\0" + /* 2439 */ "sabd\t\0" + /* 2445 */ "uabd\t\0" + /* 2451 */ "xpacd\t\0" + /* 2458 */ "sqdecd\t\0" + /* 2466 */ "uqdecd\t\0" + /* 2474 */ "sqincd\t\0" + /* 2482 */ "uqincd\t\0" + /* 2490 */ "fcadd\t\0" + /* 2497 */ "sqcadd\t\0" + /* 2505 */ "ldadd\t\0" + /* 2512 */ "fadd\t\0" + /* 2518 */ "srhadd\t\0" + /* 2526 */ "urhadd\t\0" + /* 2534 */ "shadd\t\0" + /* 2541 */ "uhadd\t\0" + /* 2548 */ "fmadd\t\0" + /* 2555 */ "fnmadd\t\0" + /* 2563 */ "usqadd\t\0" + /* 2571 */ "suqadd\t\0" + /* 2579 */ "prfd\t\0" + /* 2585 */ "nand\t\0" + /* 2591 */ "ld1rod\t\0" + /* 2599 */ "ld1rqd\t\0" + /* 2607 */ "ld1rd\t\0" + /* 2614 */ "asrd\t\0" + /* 2620 */ "aesd\t\0" + /* 2626 */ "cntd\t\0" + /* 2632 */ "revd\t\0" + /* 2638 */ "sm4e\t\0" + /* 2644 */ "splice\t\0" + /* 2652 */ "facge\t\0" + /* 2659 */ "whilege\t\0" + /* 2668 */ "fcmge\t\0" + /* 2675 */ "cmpge\t\0" + /* 2682 */ "fscale\t\0" + /* 2690 */ "whilele\t\0" + /* 2699 */ "fcmle\t\0" + /* 2706 */ "cmple\t\0" + /* 2713 */ "fcmne\t\0" + /* 2720 */ "ctermne\t\0" + /* 2729 */ "cmpne\t\0" + /* 2736 */ "frecpe\t\0" + /* 2744 */ "urecpe\t\0" + /* 2752 */ "fccmpe\t\0" + /* 2760 */ "fcmpe\t\0" + /* 2767 */ "aese\t\0" + /* 2773 */ "pfalse\t\0" + /* 2781 */ "frsqrte\t\0" + /* 2790 */ "ursqrte\t\0" + /* 2799 */ "ptrue\t\0" + /* 2806 */ "udf\t\0" + /* 2811 */ "bif\t\0" + /* 2816 */ "rmif\t\0" + /* 2822 */ "scvtf\t\0" + /* 2829 */ "ucvtf\t\0" + /* 2836 */ "st2g\t\0" + /* 2842 */ "stz2g\t\0" + /* 2849 */ "subg\t\0" + /* 2855 */ "addg\t\0" + /* 2861 */ "ldg\t\0" + /* 2866 */ "fneg\t\0" + /* 2872 */ "sqneg\t\0" + /* 2879 */ "csneg\t\0" + /* 2886 */ "histseg\t\0" + /* 2895 */ "irg\t\0" + /* 2900 */ "stg\t\0" + /* 2905 */ "stzg\t\0" + /* 2911 */ "sha1h\t\0" + /* 2918 */ "ld1h\t\0" + /* 2924 */ "ldff1h\t\0" + /* 2932 */ "ldnf1h\t\0" + /* 2940 */ "ldnt1h\t\0" + /* 2948 */ "stnt1h\t\0" + /* 2956 */ "st1h\t\0" + /* 2962 */ "sha512h\t\0" + /* 2971 */ "crc32h\t\0" + /* 2979 */ "ld2h\t\0" + /* 2985 */ "st2h\t\0" + /* 2991 */ "ld3h\t\0" + /* 2997 */ "st3h\t\0" + /* 3003 */ "ld4h\t\0" + /* 3009 */ "st4h\t\0" + /* 3015 */ "sha256h\t\0" + /* 3024 */ "ldaddah\t\0" + /* 3033 */ "sqrdcmlah\t\0" + /* 3044 */ "sqrdmlah\t\0" + /* 3054 */ "ldsminah\t\0" + /* 3064 */ "lduminah\t\0" + /* 3074 */ "swpah\t\0" + /* 3081 */ "ldclrah\t\0" + /* 3090 */ "ldeorah\t\0" + /* 3099 */ "casah\t\0" + /* 3106 */ "ldsetah\t\0" + /* 3115 */ "ldsmaxah\t\0" + /* 3125 */ "ldumaxah\t\0" + /* 3135 */ "crc32ch\t\0" + /* 3144 */ "sqdech\t\0" + /* 3152 */ "uqdech\t\0" + /* 3160 */ "sqinch\t\0" + /* 3168 */ "uqinch\t\0" + /* 3176 */ "nmatch\t\0" + /* 3184 */ "ldaddh\t\0" + /* 3192 */ "prfh\t\0" + /* 3198 */ "ldaddalh\t\0" + /* 3208 */ "ldsminalh\t\0" + /* 3219 */ "lduminalh\t\0" + /* 3230 */ "swpalh\t\0" + /* 3238 */ "ldclralh\t\0" + /* 3248 */ "ldeoralh\t\0" + /* 3258 */ "casalh\t\0" + /* 3266 */ "ldsetalh\t\0" + /* 3276 */ "ldsmaxalh\t\0" + /* 3287 */ "ldumaxalh\t\0" + /* 3298 */ "ldaddlh\t\0" + /* 3307 */ "ldsminlh\t\0" + /* 3317 */ "lduminlh\t\0" + /* 3327 */ "swplh\t\0" + /* 3334 */ "ldclrlh\t\0" + /* 3343 */ "ldeorlh\t\0" + /* 3352 */ "caslh\t\0" + /* 3359 */ "ldsetlh\t\0" + /* 3368 */ "sqdmulh\t\0" + /* 3377 */ "sqrdmulh\t\0" + /* 3387 */ "smulh\t\0" + /* 3394 */ "umulh\t\0" + /* 3401 */ "ldsmaxlh\t\0" + /* 3411 */ "ldumaxlh\t\0" + /* 3421 */ "ldsminh\t\0" + /* 3430 */ "lduminh\t\0" + /* 3439 */ "ld1roh\t\0" + /* 3447 */ "swph\t\0" + /* 3453 */ "ld1rqh\t\0" + /* 3461 */ "ld1rh\t\0" + /* 3468 */ "ldarh\t\0" + /* 3475 */ "ldlarh\t\0" + /* 3483 */ "ldrh\t\0" + /* 3489 */ "ldclrh\t\0" + /* 3497 */ "stllrh\t\0" + /* 3505 */ "stlrh\t\0" + /* 3512 */ "ldeorh\t\0" + /* 3520 */ "ldaprh\t\0" + /* 3528 */ "ldtrh\t\0" + /* 3535 */ "strh\t\0" + /* 3541 */ "sttrh\t\0" + /* 3548 */ "ldurh\t\0" + /* 3555 */ "stlurh\t\0" + /* 3563 */ "ldapurh\t\0" + /* 3572 */ "sturh\t\0" + /* 3579 */ "ldaxrh\t\0" + /* 3587 */ "ldxrh\t\0" + /* 3594 */ "stlxrh\t\0" + /* 3602 */ "stxrh\t\0" + /* 3609 */ "ld1sh\t\0" + /* 3616 */ "ldff1sh\t\0" + /* 3625 */ "ldnf1sh\t\0" + /* 3634 */ "ldnt1sh\t\0" + /* 3643 */ "cash\t\0" + /* 3649 */ "sqrdmlsh\t\0" + /* 3659 */ "ld1rsh\t\0" + /* 3667 */ "ldrsh\t\0" + /* 3674 */ "ldtrsh\t\0" + /* 3682 */ "ldursh\t\0" + /* 3690 */ "ldapursh\t\0" + /* 3700 */ "ldseth\t\0" + /* 3708 */ "cnth\t\0" + /* 3714 */ "sxth\t\0" + /* 3720 */ "uxth\t\0" + /* 3726 */ "revh\t\0" + /* 3732 */ "ldsmaxh\t\0" + /* 3741 */ "ldumaxh\t\0" + /* 3750 */ "xpaci\t\0" + /* 3757 */ "whilehi\t\0" + /* 3766 */ "punpkhi\t\0" + /* 3775 */ "sunpkhi\t\0" + /* 3784 */ "uunpkhi\t\0" + /* 3793 */ "cmhi\t\0" + /* 3799 */ "cmphi\t\0" + /* 3806 */ "sli\t\0" + /* 3811 */ "gmi\t\0" + /* 3816 */ "mvni\t\0" + /* 3822 */ "sri\t\0" + /* 3827 */ "frinti\t\0" + /* 3835 */ "movi\t\0" + /* 3841 */ "brk\t\0" + /* 3846 */ "movk\t\0" + /* 3852 */ "sabal\t\0" + /* 3859 */ "uabal\t\0" + /* 3866 */ "ldaddal\t\0" + /* 3875 */ "sqdmlal\t\0" + /* 3884 */ "fmlal\t\0" + /* 3891 */ "smlal\t\0" + /* 3898 */ "umlal\t\0" + /* 3905 */ "ldsminal\t\0" + /* 3915 */ "lduminal\t\0" + /* 3925 */ "caspal\t\0" + /* 3933 */ "swpal\t\0" + /* 3940 */ "ldclral\t\0" + /* 3949 */ "ldeoral\t\0" + /* 3958 */ "casal\t\0" + /* 3965 */ "ldsetal\t\0" + /* 3974 */ "ldsmaxal\t\0" + /* 3984 */ "ldumaxal\t\0" + /* 3994 */ "tbl\t\0" + /* 3999 */ "smsubl\t\0" + /* 4007 */ "umsubl\t\0" + /* 4015 */ "ssubl\t\0" + /* 4022 */ "usubl\t\0" + /* 4029 */ "sabdl\t\0" + /* 4036 */ "uabdl\t\0" + /* 4043 */ "ldaddl\t\0" + /* 4051 */ "smaddl\t\0" + /* 4059 */ "umaddl\t\0" + /* 4067 */ "saddl\t\0" + /* 4074 */ "uaddl\t\0" + /* 4081 */ "tcancel\t\0" + /* 4090 */ "fcsel\t\0" + /* 4097 */ "psel\t\0" + /* 4103 */ "ftssel\t\0" + /* 4111 */ "sqshl\t\0" + /* 4118 */ "uqshl\t\0" + /* 4125 */ "sqrshl\t\0" + /* 4133 */ "uqrshl\t\0" + /* 4141 */ "srshl\t\0" + /* 4148 */ "urshl\t\0" + /* 4155 */ "sshl\t\0" + /* 4161 */ "ushl\t\0" + /* 4167 */ "sshll\t\0" + /* 4174 */ "ushll\t\0" + /* 4181 */ "sqdmull\t\0" + /* 4190 */ "pmull\t\0" + /* 4197 */ "smull\t\0" + /* 4204 */ "umull\t\0" + /* 4211 */ "ldsminl\t\0" + /* 4220 */ "lduminl\t\0" + /* 4229 */ "addpl\t\0" + /* 4236 */ "caspl\t\0" + /* 4243 */ "swpl\t\0" + /* 4249 */ "ldclrl\t\0" + /* 4257 */ "ldeorl\t\0" + /* 4265 */ "casl\t\0" + /* 4271 */ "nbsl\t\0" + /* 4277 */ "sqdmlsl\t\0" + /* 4286 */ "fmlsl\t\0" + /* 4293 */ "smlsl\t\0" + /* 4300 */ "umlsl\t\0" + /* 4307 */ "sysl\t\0" + /* 4313 */ "ldsetl\t\0" + /* 4321 */ "fcvtl\t\0" + /* 4328 */ "fmul\t\0" + /* 4334 */ "fnmul\t\0" + /* 4341 */ "pmul\t\0" + /* 4347 */ "ftsmul\t\0" + /* 4355 */ "addvl\t\0" + /* 4362 */ "rdvl\t\0" + /* 4368 */ "ldsmaxl\t\0" + /* 4377 */ "ldumaxl\t\0" + /* 4386 */ "sha1m\t\0" + /* 4393 */ "sbfm\t\0" + /* 4399 */ "ubfm\t\0" + /* 4405 */ "prfm\t\0" + /* 4411 */ "ldgm\t\0" + /* 4417 */ "stgm\t\0" + /* 4423 */ "stzgm\t\0" + /* 4430 */ "fminnm\t\0" + /* 4438 */ "fmaxnm\t\0" + /* 4446 */ "dupm\t\0" + /* 4452 */ "frintm\t\0" + /* 4460 */ "prfum\t\0" + /* 4467 */ "bsl1n\t\0" + /* 4474 */ "bsl2n\t\0" + /* 4481 */ "rsubhn\t\0" + /* 4489 */ "raddhn\t\0" + /* 4497 */ "fmin\t\0" + /* 4503 */ "ldsmin\t\0" + /* 4511 */ "ldumin\t\0" + /* 4519 */ "brkn\t\0" + /* 4525 */ "ccmn\t\0" + /* 4531 */ "eon\t\0" + /* 4536 */ "sqshrn\t\0" + /* 4544 */ "uqshrn\t\0" + /* 4552 */ "sqrshrn\t\0" + /* 4561 */ "uqrshrn\t\0" + /* 4570 */ "orn\t\0" + /* 4575 */ "frintn\t\0" + /* 4583 */ "bfcvtn\t\0" + /* 4591 */ "sqxtn\t\0" + /* 4598 */ "uqxtn\t\0" + /* 4605 */ "sqshrun\t\0" + /* 4614 */ "sqrshrun\t\0" + /* 4624 */ "sqxtun\t\0" + /* 4632 */ "movn\t\0" + /* 4638 */ "fcvtxn\t\0" + /* 4646 */ "whilelo\t\0" + /* 4655 */ "punpklo\t\0" + /* 4664 */ "sunpklo\t\0" + /* 4673 */ "uunpklo\t\0" + /* 4682 */ "cmplo\t\0" + /* 4689 */ "zero\t\0" + /* 4695 */ "fcmuo\t\0" + /* 4702 */ "sha1p\t\0" + /* 4709 */ "subp\t\0" + /* 4715 */ "sqdecp\t\0" + /* 4723 */ "uqdecp\t\0" + /* 4731 */ "sqincp\t\0" + /* 4739 */ "uqincp\t\0" + /* 4747 */ "faddp\t\0" + /* 4754 */ "ldp\t\0" + /* 4759 */ "bdep\t\0" + /* 4765 */ "stgp\t\0" + /* 4771 */ "sadalp\t\0" + /* 4779 */ "uadalp\t\0" + /* 4787 */ "saddlp\t\0" + /* 4795 */ "uaddlp\t\0" + /* 4803 */ "sclamp\t\0" + /* 4811 */ "uclamp\t\0" + /* 4819 */ "fccmp\t\0" + /* 4826 */ "fcmp\t\0" + /* 4832 */ "fminnmp\t\0" + /* 4841 */ "fmaxnmp\t\0" + /* 4850 */ "ldnp\t\0" + /* 4856 */ "fminp\t\0" + /* 4863 */ "sminp\t\0" + /* 4870 */ "uminp\t\0" + /* 4877 */ "stnp\t\0" + /* 4883 */ "adrp\t\0" + /* 4889 */ "bgrp\t\0" + /* 4895 */ "casp\t\0" + /* 4901 */ "cntp\t\0" + /* 4907 */ "frintp\t\0" + /* 4915 */ "stp\t\0" + /* 4920 */ "fdup\t\0" + /* 4926 */ "swp\t\0" + /* 4931 */ "ldaxp\t\0" + /* 4938 */ "fmaxp\t\0" + /* 4945 */ "smaxp\t\0" + /* 4952 */ "umaxp\t\0" + /* 4959 */ "ldxp\t\0" + /* 4965 */ "stlxp\t\0" + /* 4972 */ "stxp\t\0" + /* 4978 */ "fcmeq\t\0" + /* 4985 */ "ctermeq\t\0" + /* 4994 */ "cmpeq\t\0" + /* 5001 */ "ld1r\t\0" + /* 5007 */ "ld2r\t\0" + /* 5013 */ "ld3r\t\0" + /* 5019 */ "ld4r\t\0" + /* 5025 */ "ldar\t\0" + /* 5031 */ "ldlar\t\0" + /* 5038 */ "xar\t\0" + /* 5043 */ "fsubr\t\0" + /* 5050 */ "shsubr\t\0" + /* 5058 */ "uhsubr\t\0" + /* 5066 */ "sqsubr\t\0" + /* 5074 */ "uqsubr\t\0" + /* 5082 */ "adr\t\0" + /* 5087 */ "ldr\t\0" + /* 5092 */ "rdffr\t\0" + /* 5099 */ "wrffr\t\0" + /* 5106 */ "srshr\t\0" + /* 5113 */ "urshr\t\0" + /* 5120 */ "sshr\t\0" + /* 5126 */ "ushr\t\0" + /* 5132 */ "blr\t\0" + /* 5137 */ "ldclr\t\0" + /* 5144 */ "sqshlr\t\0" + /* 5152 */ "uqshlr\t\0" + /* 5160 */ "sqrshlr\t\0" + /* 5169 */ "uqrshlr\t\0" + /* 5178 */ "srshlr\t\0" + /* 5186 */ "urshlr\t\0" + /* 5194 */ "stllr\t\0" + /* 5201 */ "lslr\t\0" + /* 5207 */ "stlr\t\0" + /* 5213 */ "ldeor\t\0" + /* 5220 */ "nor\t\0" + /* 5225 */ "ror\t\0" + /* 5230 */ "ldapr\t\0" + /* 5237 */ "orr\t\0" + /* 5242 */ "asrr\t\0" + /* 5248 */ "lsrr\t\0" + /* 5254 */ "asr\t\0" + /* 5259 */ "lsr\t\0" + /* 5264 */ "msr\t\0" + /* 5269 */ "insr\t\0" + /* 5275 */ "ldtr\t\0" + /* 5281 */ "str\t\0" + /* 5286 */ "sttr\t\0" + /* 5292 */ "extr\t\0" + /* 5298 */ "ldur\t\0" + /* 5304 */ "stlur\t\0" + /* 5311 */ "ldapur\t\0" + /* 5319 */ "stur\t\0" + /* 5325 */ "fdivr\t\0" + /* 5332 */ "sdivr\t\0" + /* 5339 */ "udivr\t\0" + /* 5346 */ "whilewr\t\0" + /* 5355 */ "ldaxr\t\0" + /* 5362 */ "ldxr\t\0" + /* 5368 */ "stlxr\t\0" + /* 5375 */ "stxr\t\0" + /* 5381 */ "cas\t\0" + /* 5386 */ "brkas\t\0" + /* 5393 */ "brkpas\t\0" + /* 5401 */ "fcvtas\t\0" + /* 5409 */ "fabs\t\0" + /* 5415 */ "sqabs\t\0" + /* 5422 */ "brkbs\t\0" + /* 5429 */ "brkpbs\t\0" + /* 5437 */ "subs\t\0" + /* 5443 */ "sbcs\t\0" + /* 5449 */ "adcs\t\0" + /* 5455 */ "bics\t\0" + /* 5461 */ "adds\t\0" + /* 5467 */ "nands\t\0" + /* 5474 */ "ptrues\t\0" + /* 5482 */ "whilehs\t\0" + /* 5491 */ "cmhs\t\0" + /* 5497 */ "cmphs\t\0" + /* 5504 */ "cls\t\0" + /* 5509 */ "whilels\t\0" + /* 5518 */ "fmls\t\0" + /* 5524 */ "fnmls\t\0" + /* 5531 */ "cmpls\t\0" + /* 5538 */ "fcvtms\t\0" + /* 5546 */ "ins\t\0" + /* 5551 */ "brkns\t\0" + /* 5558 */ "orns\t\0" + /* 5564 */ "fcvtns\t\0" + /* 5572 */ "subps\t\0" + /* 5579 */ "frecps\t\0" + /* 5587 */ "bfmops\t\0" + /* 5595 */ "usmops\t\0" + /* 5603 */ "sumops\t\0" + /* 5611 */ "fcvtps\t\0" + /* 5619 */ "rdffrs\t\0" + /* 5627 */ "mrs\t\0" + /* 5632 */ "eors\t\0" + /* 5638 */ "nors\t\0" + /* 5644 */ "orrs\t\0" + /* 5650 */ "frsqrts\t\0" + /* 5659 */ "sys\t\0" + /* 5664 */ "fcvtzs\t\0" + /* 5672 */ "fjcvtzs\t\0" + /* 5681 */ "sqdmlalbt\t\0" + /* 5692 */ "ssublbt\t\0" + /* 5701 */ "saddlbt\t\0" + /* 5710 */ "sqdmlslbt\t\0" + /* 5721 */ "eorbt\t\0" + /* 5728 */ "compact\t\0" + /* 5737 */ "wfet\t\0" + /* 5743 */ "ret\t\0" + /* 5748 */ "ldset\t\0" + /* 5755 */ "facgt\t\0" + /* 5762 */ "whilegt\t\0" + /* 5771 */ "fcmgt\t\0" + /* 5778 */ "cmpgt\t\0" + /* 5785 */ "rbit\t\0" + /* 5791 */ "wfit\t\0" + /* 5797 */ "sabalt\t\0" + /* 5805 */ "uabalt\t\0" + /* 5813 */ "sqdmlalt\t\0" + /* 5823 */ "bfmlalt\t\0" + /* 5832 */ "smlalt\t\0" + /* 5840 */ "umlalt\t\0" + /* 5848 */ "ssublt\t\0" + /* 5856 */ "usublt\t\0" + /* 5864 */ "sbclt\t\0" + /* 5871 */ "adclt\t\0" + /* 5878 */ "sabdlt\t\0" + /* 5886 */ "uabdlt\t\0" + /* 5894 */ "saddlt\t\0" + /* 5902 */ "uaddlt\t\0" + /* 5910 */ "whilelt\t\0" + /* 5919 */ "hlt\t\0" + /* 5924 */ "sshllt\t\0" + /* 5932 */ "ushllt\t\0" + /* 5940 */ "sqdmullt\t\0" + /* 5950 */ "pmullt\t\0" + /* 5958 */ "smullt\t\0" + /* 5966 */ "umullt\t\0" + /* 5974 */ "fcmlt\t\0" + /* 5981 */ "cmplt\t\0" + /* 5988 */ "sqdmlslt\t\0" + /* 5998 */ "fmlslt\t\0" + /* 6006 */ "smlslt\t\0" + /* 6014 */ "umlslt\t\0" + /* 6022 */ "fcvtlt\t\0" + /* 6030 */ "histcnt\t\0" + /* 6039 */ "rsubhnt\t\0" + /* 6048 */ "raddhnt\t\0" + /* 6057 */ "hint\t\0" + /* 6063 */ "sqshrnt\t\0" + /* 6072 */ "uqshrnt\t\0" + /* 6081 */ "sqrshrnt\t\0" + /* 6091 */ "uqrshrnt\t\0" + /* 6101 */ "bfcvtnt\t\0" + /* 6110 */ "sqxtnt\t\0" + /* 6118 */ "uqxtnt\t\0" + /* 6126 */ "sqshrunt\t\0" + /* 6136 */ "sqrshrunt\t\0" + /* 6147 */ "sqxtunt\t\0" + /* 6156 */ "fcvtxnt\t\0" + /* 6165 */ "cdot\t\0" + /* 6171 */ "bfdot\t\0" + /* 6178 */ "usdot\t\0" + /* 6185 */ "sudot\t\0" + /* 6192 */ "cnot\t\0" + /* 6198 */ "tstart\t\0" + /* 6206 */ "fsqrt\t\0" + /* 6213 */ "ptest\t\0" + /* 6220 */ "ttest\t\0" + /* 6227 */ "pfirst\t\0" + /* 6235 */ "cmtst\t\0" + /* 6242 */ "bfcvt\t\0" + /* 6249 */ "ssubwt\t\0" + /* 6257 */ "usubwt\t\0" + /* 6265 */ "saddwt\t\0" + /* 6273 */ "uaddwt\t\0" + /* 6281 */ "bext\t\0" + /* 6287 */ "pnext\t\0" + /* 6294 */ "fcvtau\t\0" + /* 6302 */ "sqshlu\t\0" + /* 6310 */ "fcvtmu\t\0" + /* 6318 */ "fcvtnu\t\0" + /* 6326 */ "fcvtpu\t\0" + /* 6334 */ "fcvtzu\t\0" + /* 6342 */ "st64bv\t\0" + /* 6350 */ "faddv\t\0" + /* 6357 */ "saddv\t\0" + /* 6364 */ "uaddv\t\0" + /* 6371 */ "andv\t\0" + /* 6377 */ "rev\t\0" + /* 6382 */ "fdiv\t\0" + /* 6388 */ "sdiv\t\0" + /* 6394 */ "udiv\t\0" + /* 6400 */ "saddlv\t\0" + /* 6408 */ "uaddlv\t\0" + /* 6416 */ "fminnmv\t\0" + /* 6425 */ "fmaxnmv\t\0" + /* 6434 */ "fminv\t\0" + /* 6441 */ "sminv\t\0" + /* 6448 */ "uminv\t\0" + /* 6455 */ "csinv\t\0" + /* 6462 */ "fmov\t\0" + /* 6468 */ "smov\t\0" + /* 6474 */ "umov\t\0" + /* 6480 */ "eorv\t\0" + /* 6486 */ "fmaxv\t\0" + /* 6493 */ "smaxv\t\0" + /* 6500 */ "umaxv\t\0" + /* 6507 */ "ld1w\t\0" + /* 6513 */ "ldff1w\t\0" + /* 6521 */ "ldnf1w\t\0" + /* 6529 */ "ldnt1w\t\0" + /* 6537 */ "stnt1w\t\0" + /* 6545 */ "st1w\t\0" + /* 6551 */ "crc32w\t\0" + /* 6559 */ "ld2w\t\0" + /* 6565 */ "st2w\t\0" + /* 6571 */ "ld3w\t\0" + /* 6577 */ "st3w\t\0" + /* 6583 */ "ld4w\t\0" + /* 6589 */ "st4w\t\0" + /* 6595 */ "ssubw\t\0" + /* 6602 */ "usubw\t\0" + /* 6609 */ "crc32cw\t\0" + /* 6618 */ "sqdecw\t\0" + /* 6626 */ "uqdecw\t\0" + /* 6634 */ "sqincw\t\0" + /* 6642 */ "uqincw\t\0" + /* 6650 */ "saddw\t\0" + /* 6657 */ "uaddw\t\0" + /* 6664 */ "prfw\t\0" + /* 6670 */ "ld1row\t\0" + /* 6678 */ "ld1rqw\t\0" + /* 6686 */ "ld1rw\t\0" + /* 6693 */ "whilerw\t\0" + /* 6702 */ "ld1sw\t\0" + /* 6709 */ "ldff1sw\t\0" + /* 6718 */ "ldnf1sw\t\0" + /* 6727 */ "ldnt1sw\t\0" + /* 6736 */ "ldpsw\t\0" + /* 6743 */ "ld1rsw\t\0" + /* 6751 */ "ldrsw\t\0" + /* 6758 */ "ldtrsw\t\0" + /* 6766 */ "ldursw\t\0" + /* 6774 */ "ldapursw\t\0" + /* 6784 */ "cntw\t\0" + /* 6790 */ "sxtw\t\0" + /* 6796 */ "uxtw\t\0" + /* 6802 */ "revw\t\0" + /* 6808 */ "crc32x\t\0" + /* 6816 */ "frint32x\t\0" + /* 6826 */ "frint64x\t\0" + /* 6836 */ "bcax\t\0" + /* 6842 */ "fmax\t\0" + /* 6848 */ "ldsmax\t\0" + /* 6856 */ "ldumax\t\0" + /* 6864 */ "tbx\t\0" + /* 6869 */ "crc32cx\t\0" + /* 6878 */ "index\t\0" + /* 6885 */ "clrex\t\0" + /* 6892 */ "movprfx\t\0" + /* 6901 */ "fmulx\t\0" + /* 6908 */ "frecpx\t\0" + /* 6916 */ "frintx\t\0" + /* 6924 */ "fcvtx\t\0" + /* 6931 */ "sm4ekey\t\0" + /* 6940 */ "fcpy\t\0" + /* 6946 */ "frint32z\t\0" + /* 6956 */ "frint64z\t\0" + /* 6966 */ "braaz\t\0" + /* 6973 */ "blraaz\t\0" + /* 6981 */ "brabz\t\0" + /* 6988 */ "blrabz\t\0" + /* 6996 */ "cbz\t\0" + /* 7001 */ "tbz\t\0" + /* 7006 */ "clz\t\0" + /* 7011 */ "cbnz\t\0" + /* 7017 */ "tbnz\t\0" + /* 7023 */ "frintz\t\0" + /* 7031 */ "movz\t\0" + /* 7037 */ ".tlsdesccall \0" + /* 7051 */ "# XRay Function Patchable RET.\0" + /* 7082 */ "b.\0" + /* 7085 */ "# XRay Typed Event Log.\0" + /* 7109 */ "# XRay Custom Event Log.\0" + /* 7134 */ "# XRay Function Enter.\0" + /* 7157 */ "# XRay Tail Call Exit.\0" + /* 7180 */ "# XRay Function Exit.\0" + /* 7202 */ "hint\t#10\0" + /* 7211 */ "hint\t#30\0" + /* 7220 */ "hint\t#31\0" + /* 7229 */ "hint\t#12\0" + /* 7238 */ "hint\t#14\0" + /* 7247 */ "hint\t#24\0" + /* 7256 */ "hint\t#25\0" + /* 7265 */ "hint\t#26\0" + /* 7274 */ "hint\t#7\0" + /* 7282 */ "hint\t#27\0" + /* 7291 */ "hint\t#8\0" + /* 7299 */ "hint\t#28\0" + /* 7308 */ "hint\t#29\0" + /* 7317 */ "LIFETIME_END\0" + /* 7330 */ "PSEUDO_PROBE\0" + /* 7343 */ "BUNDLE\0" + /* 7350 */ "DBG_VALUE\0" + /* 7360 */ "DBG_INSTR_REF\0" + /* 7374 */ "DBG_PHI\0" + /* 7382 */ "DBG_LABEL\0" + /* 7392 */ "LIFETIME_START\0" + /* 7407 */ "DBG_VALUE_LIST\0" + /* 7422 */ "eretaa\0" + /* 7429 */ "eretab\0" + /* 7436 */ "sb\0" + /* 7439 */ "xaflag\0" + /* 7446 */ "axflag\0" + /* 7453 */ "brb\tinj\0" + /* 7461 */ "# FEntry call\0" + /* 7475 */ "brb\tiall\0" + /* 7484 */ "setffr\0" + /* 7491 */ "drps\0" + /* 7496 */ "eret\0" + /* 7501 */ "tcommit\0" + /* 7509 */ "cfinv\0" + /* 7515 */ "ld1b\t{\0" + /* 7522 */ "st1b\t{\0" + /* 7529 */ "ld1d\t{\0" + /* 7536 */ "st1d\t{\0" + /* 7543 */ "ld1h\t{\0" + /* 7550 */ "st1h\t{\0" + /* 7557 */ "ld1q\t{\0" + /* 7564 */ "st1q\t{\0" + /* 7571 */ "ld1w\t{\0" + /* 7578 */ "st1w\t{\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 7351U, // DBG_VALUE + 7408U, // DBG_VALUE_LIST + 7361U, // DBG_INSTR_REF + 7375U, // DBG_PHI + 7383U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 7344U, // BUNDLE + 7393U, // LIFETIME_START + 7318U, // LIFETIME_END + 7331U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 7462U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 7135U, // PATCHABLE_FUNCTION_ENTER + 7052U, // PATCHABLE_RET + 7181U, // PATCHABLE_FUNCTION_EXIT + 7158U, // PATCHABLE_TAIL_CALL + 7110U, // PATCHABLE_EVENT_CALL + 7086U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABS_ZPmZ_UNDEF_B + 0U, // ABS_ZPmZ_UNDEF_D + 0U, // ABS_ZPmZ_UNDEF_H + 0U, // ABS_ZPmZ_UNDEF_S + 0U, // ADDSWrr + 0U, // ADDSXrr + 0U, // ADDWrr + 0U, // ADDXrr + 0U, // ADD_ZPZZ_UNDEF_B + 0U, // ADD_ZPZZ_UNDEF_D + 0U, // ADD_ZPZZ_UNDEF_H + 0U, // ADD_ZPZZ_UNDEF_S + 0U, // ADD_ZPZZ_ZERO_B + 0U, // ADD_ZPZZ_ZERO_D + 0U, // ADD_ZPZZ_ZERO_H + 0U, // ADD_ZPZZ_ZERO_S + 0U, // ADDlowTLS + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // AESIMCrrTied + 0U, // AESMCrrTied + 0U, // ANDSWrr + 0U, // ANDSXrr + 0U, // ANDWrr + 0U, // ANDXrr + 0U, // ASRD_ZPZI_ZERO_B + 0U, // ASRD_ZPZI_ZERO_D + 0U, // ASRD_ZPZI_ZERO_H + 0U, // ASRD_ZPZI_ZERO_S + 0U, // ASR_ZPZI_UNDEF_B + 0U, // ASR_ZPZI_UNDEF_D + 0U, // ASR_ZPZI_UNDEF_H + 0U, // ASR_ZPZI_UNDEF_S + 0U, // ASR_ZPZZ_UNDEF_B + 0U, // ASR_ZPZZ_UNDEF_D + 0U, // ASR_ZPZZ_UNDEF_H + 0U, // ASR_ZPZZ_UNDEF_S + 0U, // ASR_ZPZZ_ZERO_B + 0U, // ASR_ZPZZ_ZERO_D + 0U, // ASR_ZPZZ_ZERO_H + 0U, // ASR_ZPZZ_ZERO_S + 0U, // BICSWrr + 0U, // BICSXrr + 0U, // BICWrr + 0U, // BICXrr + 0U, // BLRNoIP + 0U, // BLR_RVMARKER + 0U, // BSPv16i8 + 0U, // BSPv8i8 + 0U, // CATCHRET + 0U, // CLEANUPRET + 0U, // CLS_ZPmZ_UNDEF_B + 0U, // CLS_ZPmZ_UNDEF_D + 0U, // CLS_ZPmZ_UNDEF_H + 0U, // CLS_ZPmZ_UNDEF_S + 0U, // CLZ_ZPmZ_UNDEF_B + 0U, // CLZ_ZPmZ_UNDEF_D + 0U, // CLZ_ZPmZ_UNDEF_H + 0U, // CLZ_ZPmZ_UNDEF_S + 0U, // CMP_SWAP_128 + 0U, // CMP_SWAP_128_ACQUIRE + 0U, // CMP_SWAP_128_MONOTONIC + 0U, // CMP_SWAP_128_RELEASE + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CNOT_ZPmZ_UNDEF_B + 0U, // CNOT_ZPmZ_UNDEF_D + 0U, // CNOT_ZPmZ_UNDEF_H + 0U, // CNOT_ZPmZ_UNDEF_S + 0U, // CNT_ZPmZ_UNDEF_B + 0U, // CNT_ZPmZ_UNDEF_D + 0U, // CNT_ZPmZ_UNDEF_H + 0U, // CNT_ZPmZ_UNDEF_S + 0U, // CompilerBarrier + 0U, // EMITBKEY + 0U, // EONWrr + 0U, // EONXrr + 0U, // EORWrr + 0U, // EORXrr + 0U, // F128CSEL + 0U, // FABD_ZPZZ_ZERO_D + 0U, // FABD_ZPZZ_ZERO_H + 0U, // FABD_ZPZZ_ZERO_S + 0U, // FABS_ZPmZ_UNDEF_D + 0U, // FABS_ZPmZ_UNDEF_H + 0U, // FABS_ZPmZ_UNDEF_S + 0U, // FADD_ZPZI_UNDEF_D + 0U, // FADD_ZPZI_UNDEF_H + 0U, // FADD_ZPZI_UNDEF_S + 0U, // FADD_ZPZI_ZERO_D + 0U, // FADD_ZPZI_ZERO_H + 0U, // FADD_ZPZI_ZERO_S + 0U, // FADD_ZPZZ_UNDEF_D + 0U, // FADD_ZPZZ_UNDEF_H + 0U, // FADD_ZPZZ_UNDEF_S + 0U, // FADD_ZPZZ_ZERO_D + 0U, // FADD_ZPZZ_ZERO_H + 0U, // FADD_ZPZZ_ZERO_S + 0U, // FDIVR_ZPZZ_ZERO_D + 0U, // FDIVR_ZPZZ_ZERO_H + 0U, // FDIVR_ZPZZ_ZERO_S + 0U, // FDIV_ZPZZ_UNDEF_D + 0U, // FDIV_ZPZZ_UNDEF_H + 0U, // FDIV_ZPZZ_UNDEF_S + 0U, // FDIV_ZPZZ_ZERO_D + 0U, // FDIV_ZPZZ_ZERO_H + 0U, // FDIV_ZPZZ_ZERO_S + 0U, // FMAXNM_ZPZI_UNDEF_D + 0U, // FMAXNM_ZPZI_UNDEF_H + 0U, // FMAXNM_ZPZI_UNDEF_S + 0U, // FMAXNM_ZPZI_ZERO_D + 0U, // FMAXNM_ZPZI_ZERO_H + 0U, // FMAXNM_ZPZI_ZERO_S + 0U, // FMAXNM_ZPZZ_UNDEF_D + 0U, // FMAXNM_ZPZZ_UNDEF_H + 0U, // FMAXNM_ZPZZ_UNDEF_S + 0U, // FMAXNM_ZPZZ_ZERO_D + 0U, // FMAXNM_ZPZZ_ZERO_H + 0U, // FMAXNM_ZPZZ_ZERO_S + 0U, // FMAX_ZPZI_UNDEF_D + 0U, // FMAX_ZPZI_UNDEF_H + 0U, // FMAX_ZPZI_UNDEF_S + 0U, // FMAX_ZPZI_ZERO_D + 0U, // FMAX_ZPZI_ZERO_H + 0U, // FMAX_ZPZI_ZERO_S + 0U, // FMAX_ZPZZ_UNDEF_D + 0U, // FMAX_ZPZZ_UNDEF_H + 0U, // FMAX_ZPZZ_UNDEF_S + 0U, // FMAX_ZPZZ_ZERO_D + 0U, // FMAX_ZPZZ_ZERO_H + 0U, // FMAX_ZPZZ_ZERO_S + 0U, // FMINNM_ZPZI_UNDEF_D + 0U, // FMINNM_ZPZI_UNDEF_H + 0U, // FMINNM_ZPZI_UNDEF_S + 0U, // FMINNM_ZPZI_ZERO_D + 0U, // FMINNM_ZPZI_ZERO_H + 0U, // FMINNM_ZPZI_ZERO_S + 0U, // FMINNM_ZPZZ_UNDEF_D + 0U, // FMINNM_ZPZZ_UNDEF_H + 0U, // FMINNM_ZPZZ_UNDEF_S + 0U, // FMINNM_ZPZZ_ZERO_D + 0U, // FMINNM_ZPZZ_ZERO_H + 0U, // FMINNM_ZPZZ_ZERO_S + 0U, // FMIN_ZPZI_UNDEF_D + 0U, // FMIN_ZPZI_UNDEF_H + 0U, // FMIN_ZPZI_UNDEF_S + 0U, // FMIN_ZPZI_ZERO_D + 0U, // FMIN_ZPZI_ZERO_H + 0U, // FMIN_ZPZI_ZERO_S + 0U, // FMIN_ZPZZ_UNDEF_D + 0U, // FMIN_ZPZZ_UNDEF_H + 0U, // FMIN_ZPZZ_UNDEF_S + 0U, // FMIN_ZPZZ_ZERO_D + 0U, // FMIN_ZPZZ_ZERO_H + 0U, // FMIN_ZPZZ_ZERO_S + 0U, // FMLA_ZPZZZ_UNDEF_D + 0U, // FMLA_ZPZZZ_UNDEF_H + 0U, // FMLA_ZPZZZ_UNDEF_S + 0U, // FMLS_ZPZZZ_UNDEF_D + 0U, // FMLS_ZPZZZ_UNDEF_H + 0U, // FMLS_ZPZZZ_UNDEF_S + 0U, // FMOVD0 + 0U, // FMOVH0 + 0U, // FMOVS0 + 0U, // FMULX_ZPZZ_ZERO_D + 0U, // FMULX_ZPZZ_ZERO_H + 0U, // FMULX_ZPZZ_ZERO_S + 0U, // FMUL_ZPZI_UNDEF_D + 0U, // FMUL_ZPZI_UNDEF_H + 0U, // FMUL_ZPZI_UNDEF_S + 0U, // FMUL_ZPZI_ZERO_D + 0U, // FMUL_ZPZI_ZERO_H + 0U, // FMUL_ZPZI_ZERO_S + 0U, // FMUL_ZPZZ_UNDEF_D + 0U, // FMUL_ZPZZ_UNDEF_H + 0U, // FMUL_ZPZZ_UNDEF_S + 0U, // FMUL_ZPZZ_ZERO_D + 0U, // FMUL_ZPZZ_ZERO_H + 0U, // FMUL_ZPZZ_ZERO_S + 0U, // FNEG_ZPmZ_UNDEF_D + 0U, // FNEG_ZPmZ_UNDEF_H + 0U, // FNEG_ZPmZ_UNDEF_S + 0U, // FNMLA_ZPZZZ_UNDEF_D + 0U, // FNMLA_ZPZZZ_UNDEF_H + 0U, // FNMLA_ZPZZZ_UNDEF_S + 0U, // FNMLS_ZPZZZ_UNDEF_D + 0U, // FNMLS_ZPZZZ_UNDEF_H + 0U, // FNMLS_ZPZZZ_UNDEF_S + 0U, // FRECPX_ZPmZ_UNDEF_D + 0U, // FRECPX_ZPmZ_UNDEF_H + 0U, // FRECPX_ZPmZ_UNDEF_S + 0U, // FRINTA_ZPmZ_UNDEF_D + 0U, // FRINTA_ZPmZ_UNDEF_H + 0U, // FRINTA_ZPmZ_UNDEF_S + 0U, // FRINTI_ZPmZ_UNDEF_D + 0U, // FRINTI_ZPmZ_UNDEF_H + 0U, // FRINTI_ZPmZ_UNDEF_S + 0U, // FRINTM_ZPmZ_UNDEF_D + 0U, // FRINTM_ZPmZ_UNDEF_H + 0U, // FRINTM_ZPmZ_UNDEF_S + 0U, // FRINTN_ZPmZ_UNDEF_D + 0U, // FRINTN_ZPmZ_UNDEF_H + 0U, // FRINTN_ZPmZ_UNDEF_S + 0U, // FRINTP_ZPmZ_UNDEF_D + 0U, // FRINTP_ZPmZ_UNDEF_H + 0U, // FRINTP_ZPmZ_UNDEF_S + 0U, // FRINTX_ZPmZ_UNDEF_D + 0U, // FRINTX_ZPmZ_UNDEF_H + 0U, // FRINTX_ZPmZ_UNDEF_S + 0U, // FRINTZ_ZPmZ_UNDEF_D + 0U, // FRINTZ_ZPmZ_UNDEF_H + 0U, // FRINTZ_ZPmZ_UNDEF_S + 0U, // FSQRT_ZPmZ_UNDEF_D + 0U, // FSQRT_ZPmZ_UNDEF_H + 0U, // FSQRT_ZPmZ_UNDEF_S + 0U, // FSUBR_ZPZI_UNDEF_D + 0U, // FSUBR_ZPZI_UNDEF_H + 0U, // FSUBR_ZPZI_UNDEF_S + 0U, // FSUBR_ZPZI_ZERO_D + 0U, // FSUBR_ZPZI_ZERO_H + 0U, // FSUBR_ZPZI_ZERO_S + 0U, // FSUBR_ZPZZ_ZERO_D + 0U, // FSUBR_ZPZZ_ZERO_H + 0U, // FSUBR_ZPZZ_ZERO_S + 0U, // FSUB_ZPZI_UNDEF_D + 0U, // FSUB_ZPZI_UNDEF_H + 0U, // FSUB_ZPZI_UNDEF_S + 0U, // FSUB_ZPZI_ZERO_D + 0U, // FSUB_ZPZI_ZERO_H + 0U, // FSUB_ZPZI_ZERO_S + 0U, // FSUB_ZPZZ_UNDEF_D + 0U, // FSUB_ZPZZ_UNDEF_H + 0U, // FSUB_ZPZZ_UNDEF_S + 0U, // FSUB_ZPZZ_ZERO_D + 0U, // FSUB_ZPZZ_ZERO_H + 0U, // FSUB_ZPZZ_ZERO_S + 0U, // GLD1B_D + 0U, // GLD1B_D_IMM + 0U, // GLD1B_D_SXTW + 0U, // GLD1B_D_UXTW + 0U, // GLD1B_S_IMM + 0U, // GLD1B_S_SXTW + 0U, // GLD1B_S_UXTW + 0U, // GLD1D + 0U, // GLD1D_IMM + 0U, // GLD1D_SCALED + 0U, // GLD1D_SXTW + 0U, // GLD1D_SXTW_SCALED + 0U, // GLD1D_UXTW + 0U, // GLD1D_UXTW_SCALED + 0U, // GLD1H_D + 0U, // GLD1H_D_IMM + 0U, // GLD1H_D_SCALED + 0U, // GLD1H_D_SXTW + 0U, // GLD1H_D_SXTW_SCALED + 0U, // GLD1H_D_UXTW + 0U, // GLD1H_D_UXTW_SCALED + 0U, // GLD1H_S_IMM + 0U, // GLD1H_S_SXTW + 0U, // GLD1H_S_SXTW_SCALED + 0U, // GLD1H_S_UXTW + 0U, // GLD1H_S_UXTW_SCALED + 0U, // GLD1SB_D + 0U, // GLD1SB_D_IMM + 0U, // GLD1SB_D_SXTW + 0U, // GLD1SB_D_UXTW + 0U, // GLD1SB_S_IMM + 0U, // GLD1SB_S_SXTW + 0U, // GLD1SB_S_UXTW + 0U, // GLD1SH_D + 0U, // GLD1SH_D_IMM + 0U, // GLD1SH_D_SCALED + 0U, // GLD1SH_D_SXTW + 0U, // GLD1SH_D_SXTW_SCALED + 0U, // GLD1SH_D_UXTW + 0U, // GLD1SH_D_UXTW_SCALED + 0U, // GLD1SH_S_IMM + 0U, // GLD1SH_S_SXTW + 0U, // GLD1SH_S_SXTW_SCALED + 0U, // GLD1SH_S_UXTW + 0U, // GLD1SH_S_UXTW_SCALED + 0U, // GLD1SW_D + 0U, // GLD1SW_D_IMM + 0U, // GLD1SW_D_SCALED + 0U, // GLD1SW_D_SXTW + 0U, // GLD1SW_D_SXTW_SCALED + 0U, // GLD1SW_D_UXTW + 0U, // GLD1SW_D_UXTW_SCALED + 0U, // GLD1W_D + 0U, // GLD1W_D_IMM + 0U, // GLD1W_D_SCALED + 0U, // GLD1W_D_SXTW + 0U, // GLD1W_D_SXTW_SCALED + 0U, // GLD1W_D_UXTW + 0U, // GLD1W_D_UXTW_SCALED + 0U, // GLD1W_IMM + 0U, // GLD1W_SXTW + 0U, // GLD1W_SXTW_SCALED + 0U, // GLD1W_UXTW + 0U, // GLD1W_UXTW_SCALED + 0U, // GLDFF1B_D + 0U, // GLDFF1B_D_IMM + 0U, // GLDFF1B_D_SXTW + 0U, // GLDFF1B_D_UXTW + 0U, // GLDFF1B_S_IMM + 0U, // GLDFF1B_S_SXTW + 0U, // GLDFF1B_S_UXTW + 0U, // GLDFF1D + 0U, // GLDFF1D_IMM + 0U, // GLDFF1D_SCALED + 0U, // GLDFF1D_SXTW + 0U, // GLDFF1D_SXTW_SCALED + 0U, // GLDFF1D_UXTW + 0U, // GLDFF1D_UXTW_SCALED + 0U, // GLDFF1H_D + 0U, // GLDFF1H_D_IMM + 0U, // GLDFF1H_D_SCALED + 0U, // GLDFF1H_D_SXTW + 0U, // GLDFF1H_D_SXTW_SCALED + 0U, // GLDFF1H_D_UXTW + 0U, // GLDFF1H_D_UXTW_SCALED + 0U, // GLDFF1H_S_IMM + 0U, // GLDFF1H_S_SXTW + 0U, // GLDFF1H_S_SXTW_SCALED + 0U, // GLDFF1H_S_UXTW + 0U, // GLDFF1H_S_UXTW_SCALED + 0U, // GLDFF1SB_D + 0U, // GLDFF1SB_D_IMM + 0U, // GLDFF1SB_D_SXTW + 0U, // GLDFF1SB_D_UXTW + 0U, // GLDFF1SB_S_IMM + 0U, // GLDFF1SB_S_SXTW + 0U, // GLDFF1SB_S_UXTW + 0U, // GLDFF1SH_D + 0U, // GLDFF1SH_D_IMM + 0U, // GLDFF1SH_D_SCALED + 0U, // GLDFF1SH_D_SXTW + 0U, // GLDFF1SH_D_SXTW_SCALED + 0U, // GLDFF1SH_D_UXTW + 0U, // GLDFF1SH_D_UXTW_SCALED + 0U, // GLDFF1SH_S_IMM + 0U, // GLDFF1SH_S_SXTW + 0U, // GLDFF1SH_S_SXTW_SCALED + 0U, // GLDFF1SH_S_UXTW + 0U, // GLDFF1SH_S_UXTW_SCALED + 0U, // GLDFF1SW_D + 0U, // GLDFF1SW_D_IMM + 0U, // GLDFF1SW_D_SCALED + 0U, // GLDFF1SW_D_SXTW + 0U, // GLDFF1SW_D_SXTW_SCALED + 0U, // GLDFF1SW_D_UXTW + 0U, // GLDFF1SW_D_UXTW_SCALED + 0U, // GLDFF1W_D + 0U, // GLDFF1W_D_IMM + 0U, // GLDFF1W_D_SCALED + 0U, // GLDFF1W_D_SXTW + 0U, // GLDFF1W_D_SXTW_SCALED + 0U, // GLDFF1W_D_UXTW + 0U, // GLDFF1W_D_UXTW_SCALED + 0U, // GLDFF1W_IMM + 0U, // GLDFF1W_SXTW + 0U, // GLDFF1W_SXTW_SCALED + 0U, // GLDFF1W_UXTW + 0U, // GLDFF1W_UXTW_SCALED + 0U, // G_ADD_LOW + 0U, // G_DUP + 0U, // G_DUPLANE16 + 0U, // G_DUPLANE32 + 0U, // G_DUPLANE64 + 0U, // G_DUPLANE8 + 0U, // G_EXT + 0U, // G_FCMEQ + 0U, // G_FCMEQZ + 0U, // G_FCMGE + 0U, // G_FCMGEZ + 0U, // G_FCMGT + 0U, // G_FCMGTZ + 0U, // G_FCMLEZ + 0U, // G_FCMLTZ + 0U, // G_REV16 + 0U, // G_REV32 + 0U, // G_REV64 + 0U, // G_SITOF + 0U, // G_TRN1 + 0U, // G_TRN2 + 0U, // G_UITOF + 0U, // G_UZP1 + 0U, // G_UZP2 + 0U, // G_VASHR + 0U, // G_VLSHR + 0U, // G_ZIP1 + 0U, // G_ZIP2 + 0U, // HOM_Epilog + 0U, // HOM_Prolog + 0U, // HWASAN_CHECK_MEMACCESS + 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES + 0U, // IRGstack + 0U, // JumpTableDest16 + 0U, // JumpTableDest32 + 0U, // JumpTableDest8 + 0U, // LD1B_D_IMM + 0U, // LD1B_H_IMM + 0U, // LD1B_IMM + 0U, // LD1B_S_IMM + 0U, // LD1D_IMM + 0U, // LD1H_D_IMM + 0U, // LD1H_IMM + 0U, // LD1H_S_IMM + 0U, // LD1SB_D_IMM + 0U, // LD1SB_H_IMM + 0U, // LD1SB_S_IMM + 0U, // LD1SH_D_IMM + 0U, // LD1SH_S_IMM + 0U, // LD1SW_D_IMM + 0U, // LD1W_D_IMM + 0U, // LD1W_IMM + 0U, // LDFF1B + 0U, // LDFF1B_D + 0U, // LDFF1B_H + 0U, // LDFF1B_S + 0U, // LDFF1D + 0U, // LDFF1H + 0U, // LDFF1H_D + 0U, // LDFF1H_S + 0U, // LDFF1SB_D + 0U, // LDFF1SB_H + 0U, // LDFF1SB_S + 0U, // LDFF1SH_D + 0U, // LDFF1SH_S + 0U, // LDFF1SW_D + 0U, // LDFF1W + 0U, // LDFF1W_D + 0U, // LDNF1B_D_IMM + 0U, // LDNF1B_H_IMM + 0U, // LDNF1B_IMM + 0U, // LDNF1B_S_IMM + 0U, // LDNF1D_IMM + 0U, // LDNF1H_D_IMM + 0U, // LDNF1H_IMM + 0U, // LDNF1H_S_IMM + 0U, // LDNF1SB_D_IMM + 0U, // LDNF1SB_H_IMM + 0U, // LDNF1SB_S_IMM + 0U, // LDNF1SH_D_IMM + 0U, // LDNF1SH_S_IMM + 0U, // LDNF1SW_D_IMM + 0U, // LDNF1W_D_IMM + 0U, // LDNF1W_IMM + 0U, // LDR_ZZXI + 0U, // LDR_ZZZXI + 0U, // LDR_ZZZZXI + 0U, // LOADgot + 0U, // LSL_ZPZI_UNDEF_B + 0U, // LSL_ZPZI_UNDEF_D + 0U, // LSL_ZPZI_UNDEF_H + 0U, // LSL_ZPZI_UNDEF_S + 0U, // LSL_ZPZZ_UNDEF_B + 0U, // LSL_ZPZZ_UNDEF_D + 0U, // LSL_ZPZZ_UNDEF_H + 0U, // LSL_ZPZZ_UNDEF_S + 0U, // LSL_ZPZZ_ZERO_B + 0U, // LSL_ZPZZ_ZERO_D + 0U, // LSL_ZPZZ_ZERO_H + 0U, // LSL_ZPZZ_ZERO_S + 0U, // LSR_ZPZI_UNDEF_B + 0U, // LSR_ZPZI_UNDEF_D + 0U, // LSR_ZPZI_UNDEF_H + 0U, // LSR_ZPZI_UNDEF_S + 0U, // LSR_ZPZZ_UNDEF_B + 0U, // LSR_ZPZZ_UNDEF_D + 0U, // LSR_ZPZZ_UNDEF_H + 0U, // LSR_ZPZZ_UNDEF_S + 0U, // LSR_ZPZZ_ZERO_B + 0U, // LSR_ZPZZ_ZERO_D + 0U, // LSR_ZPZZ_ZERO_H + 0U, // LSR_ZPZZ_ZERO_S + 0U, // MOVMCSym + 0U, // MOVaddr + 0U, // MOVaddrBA + 0U, // MOVaddrCP + 0U, // MOVaddrEXT + 0U, // MOVaddrJT + 0U, // MOVaddrTLS + 0U, // MOVbaseTLS + 0U, // MOVi32imm + 0U, // MOVi64imm + 0U, // MUL_ZPZZ_UNDEF_B + 0U, // MUL_ZPZZ_UNDEF_D + 0U, // MUL_ZPZZ_UNDEF_H + 0U, // MUL_ZPZZ_UNDEF_S + 0U, // NEG_ZPmZ_UNDEF_B + 0U, // NEG_ZPmZ_UNDEF_D + 0U, // NEG_ZPmZ_UNDEF_H + 0U, // NEG_ZPmZ_UNDEF_S + 0U, // NOT_ZPmZ_UNDEF_B + 0U, // NOT_ZPmZ_UNDEF_D + 0U, // NOT_ZPmZ_UNDEF_H + 0U, // NOT_ZPmZ_UNDEF_S + 0U, // ORNWrr + 0U, // ORNXrr + 0U, // ORRWrr + 0U, // ORRXrr + 0U, // RDFFR_P + 0U, // RDFFR_PPz + 0U, // RET_ReallyLR + 0U, // SDIV_ZPZZ_UNDEF_D + 0U, // SDIV_ZPZZ_UNDEF_S + 0U, // SEH_AddFP + 0U, // SEH_EpilogEnd + 0U, // SEH_EpilogStart + 0U, // SEH_Nop + 0U, // SEH_PrologEnd + 0U, // SEH_SaveFPLR + 0U, // SEH_SaveFPLR_X + 0U, // SEH_SaveFReg + 0U, // SEH_SaveFRegP + 0U, // SEH_SaveFRegP_X + 0U, // SEH_SaveFReg_X + 0U, // SEH_SaveReg + 0U, // SEH_SaveRegP + 0U, // SEH_SaveRegP_X + 0U, // SEH_SaveReg_X + 0U, // SEH_SetFP + 0U, // SEH_StackAlloc + 0U, // SMAX_ZPZZ_UNDEF_B + 0U, // SMAX_ZPZZ_UNDEF_D + 0U, // SMAX_ZPZZ_UNDEF_H + 0U, // SMAX_ZPZZ_UNDEF_S + 0U, // SMIN_ZPZZ_UNDEF_B + 0U, // SMIN_ZPZZ_UNDEF_D + 0U, // SMIN_ZPZZ_UNDEF_H + 0U, // SMIN_ZPZZ_UNDEF_S + 0U, // SMULH_ZPZZ_UNDEF_B + 0U, // SMULH_ZPZZ_UNDEF_D + 0U, // SMULH_ZPZZ_UNDEF_H + 0U, // SMULH_ZPZZ_UNDEF_S + 0U, // SPACE + 0U, // SQABS_ZPmZ_UNDEF_B + 0U, // SQABS_ZPmZ_UNDEF_D + 0U, // SQABS_ZPmZ_UNDEF_H + 0U, // SQABS_ZPmZ_UNDEF_S + 0U, // SQNEG_ZPmZ_UNDEF_B + 0U, // SQNEG_ZPmZ_UNDEF_D + 0U, // SQNEG_ZPmZ_UNDEF_H + 0U, // SQNEG_ZPmZ_UNDEF_S + 0U, // SQRSHL_ZPZZ_UNDEF_B + 0U, // SQRSHL_ZPZZ_UNDEF_D + 0U, // SQRSHL_ZPZZ_UNDEF_H + 0U, // SQRSHL_ZPZZ_UNDEF_S + 0U, // SQSHLU_ZPZI_ZERO_B + 0U, // SQSHLU_ZPZI_ZERO_D + 0U, // SQSHLU_ZPZI_ZERO_H + 0U, // SQSHLU_ZPZI_ZERO_S + 0U, // SQSHL_ZPZI_ZERO_B + 0U, // SQSHL_ZPZI_ZERO_D + 0U, // SQSHL_ZPZI_ZERO_H + 0U, // SQSHL_ZPZI_ZERO_S + 0U, // SQSHL_ZPZZ_UNDEF_B + 0U, // SQSHL_ZPZZ_UNDEF_D + 0U, // SQSHL_ZPZZ_UNDEF_H + 0U, // SQSHL_ZPZZ_UNDEF_S + 0U, // SRSHL_ZPZZ_UNDEF_B + 0U, // SRSHL_ZPZZ_UNDEF_D + 0U, // SRSHL_ZPZZ_UNDEF_H + 0U, // SRSHL_ZPZZ_UNDEF_S + 0U, // SRSHR_ZPZI_ZERO_B + 0U, // SRSHR_ZPZI_ZERO_D + 0U, // SRSHR_ZPZI_ZERO_H + 0U, // SRSHR_ZPZI_ZERO_S + 0U, // STGloop + 0U, // STGloop_wback + 0U, // STR_ZZXI + 0U, // STR_ZZZXI + 0U, // STR_ZZZZXI + 0U, // STZGloop + 0U, // STZGloop_wback + 0U, // SUBR_ZPZZ_ZERO_B + 0U, // SUBR_ZPZZ_ZERO_D + 0U, // SUBR_ZPZZ_ZERO_H + 0U, // SUBR_ZPZZ_ZERO_S + 0U, // SUBSWrr + 0U, // SUBSXrr + 0U, // SUBWrr + 0U, // SUBXrr + 0U, // SUB_ZPZZ_UNDEF_B + 0U, // SUB_ZPZZ_UNDEF_D + 0U, // SUB_ZPZZ_UNDEF_H + 0U, // SUB_ZPZZ_UNDEF_S + 0U, // SUB_ZPZZ_ZERO_B + 0U, // SUB_ZPZZ_ZERO_D + 0U, // SUB_ZPZZ_ZERO_H + 0U, // SUB_ZPZZ_ZERO_S + 0U, // SXTB_ZPmZ_UNDEF_D + 0U, // SXTB_ZPmZ_UNDEF_H + 0U, // SXTB_ZPmZ_UNDEF_S + 0U, // SXTH_ZPmZ_UNDEF_D + 0U, // SXTH_ZPmZ_UNDEF_S + 0U, // SXTW_ZPmZ_UNDEF_D + 0U, // SpeculationBarrierISBDSBEndBB + 0U, // SpeculationBarrierSBEndBB + 0U, // SpeculationSafeValueW + 0U, // SpeculationSafeValueX + 0U, // StoreSwiftAsyncContext + 0U, // TAGPstack + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TCRETURNriALL + 0U, // TCRETURNriBTI + 15230U, // TLSDESCCALL + 0U, // TLSDESC_CALLSEQ + 0U, // UDIV_ZPZZ_UNDEF_D + 0U, // UDIV_ZPZZ_UNDEF_S + 0U, // UMAX_ZPZZ_UNDEF_B + 0U, // UMAX_ZPZZ_UNDEF_D + 0U, // UMAX_ZPZZ_UNDEF_H + 0U, // UMAX_ZPZZ_UNDEF_S + 0U, // UMIN_ZPZZ_UNDEF_B + 0U, // UMIN_ZPZZ_UNDEF_D + 0U, // UMIN_ZPZZ_UNDEF_H + 0U, // UMIN_ZPZZ_UNDEF_S + 0U, // UMULH_ZPZZ_UNDEF_B + 0U, // UMULH_ZPZZ_UNDEF_D + 0U, // UMULH_ZPZZ_UNDEF_H + 0U, // UMULH_ZPZZ_UNDEF_S + 0U, // UQRSHL_ZPZZ_UNDEF_B + 0U, // UQRSHL_ZPZZ_UNDEF_D + 0U, // UQRSHL_ZPZZ_UNDEF_H + 0U, // UQRSHL_ZPZZ_UNDEF_S + 0U, // UQSHL_ZPZI_ZERO_B + 0U, // UQSHL_ZPZI_ZERO_D + 0U, // UQSHL_ZPZI_ZERO_H + 0U, // UQSHL_ZPZI_ZERO_S + 0U, // UQSHL_ZPZZ_UNDEF_B + 0U, // UQSHL_ZPZZ_UNDEF_D + 0U, // UQSHL_ZPZZ_UNDEF_H + 0U, // UQSHL_ZPZZ_UNDEF_S + 0U, // URECPE_ZPmZ_UNDEF_S + 0U, // URSHL_ZPZZ_UNDEF_B + 0U, // URSHL_ZPZZ_UNDEF_D + 0U, // URSHL_ZPZZ_UNDEF_H + 0U, // URSHL_ZPZZ_UNDEF_S + 0U, // URSHR_ZPZI_ZERO_B + 0U, // URSHR_ZPZI_ZERO_D + 0U, // URSHR_ZPZI_ZERO_H + 0U, // URSHR_ZPZI_ZERO_S + 0U, // URSQRTE_ZPmZ_UNDEF_S + 0U, // UXTB_ZPmZ_UNDEF_D + 0U, // UXTB_ZPmZ_UNDEF_H + 0U, // UXTB_ZPmZ_UNDEF_S + 0U, // UXTH_ZPmZ_UNDEF_D + 0U, // UXTH_ZPmZ_UNDEF_S + 0U, // UXTW_ZPmZ_UNDEF_D + 1070371U, // ABS_ZPmZ_B + 1078563U, // ABS_ZPmZ_D + 136353059U, // ABS_ZPmZ_H + 1094947U, // ABS_ZPmZ_S + 271635747U, // ABSv16i8 + 403715363U, // ABSv1i64 + 272684323U, // ABSv2i32 + 273732899U, // ABSv2i64 + 274781475U, // ABSv4i16 + 275830051U, // ABSv4i32 + 276878627U, // ABSv8i16 + 277927203U, // ABSv8i8 + 537945533U, // ADCLB_ZZZ_D + 672179645U, // ADCLB_ZZZ_S + 537949936U, // ADCLT_ZZZ_D + 672184048U, // ADCLT_ZZZ_S + 403715402U, // ADCSWr + 403715402U, // ADCSXr + 403712244U, // ADCWr + 403712244U, // ADCXr + 403712808U, // ADDG + 815850167U, // ADDHA_MPPZ_D + 816898743U, // ADDHA_MPPZ_S + 940590753U, // ADDHNB_ZZZ_B + 1086359201U, // ADDHNB_ZZZ_H + 1209050785U, // ADDHNB_ZZZ_S + 1343248290U, // ADDHNT_ZZZ_B + 1087412130U, // ADDHNT_ZZZ_H + 537966498U, // ADDHNT_ZZZ_S + 272683403U, // ADDHNv2i64_v2i32 + 1483800940U, // ADDHNv2i64_v4i32 + 274780555U, // ADDHNv4i32_v4i16 + 1484849516U, // ADDHNv4i32_v8i16 + 1479606636U, // ADDHNv8i16_v16i8 + 277926283U, // ADDHNv8i16_v8i8 + 403714182U, // ADDPL_XXI + 1611682445U, // ADDP_ZPmZ_B + 1611690637U, // ADDP_ZPmZ_D + 1759548045U, // ADDP_ZPmZ_H + 1611707021U, // ADDP_ZPmZ_S + 271635085U, // ADDPv16i8 + 272683661U, // ADDPv2i32 + 273732237U, // ADDPv2i64 + 269496973U, // ADDPv2i64p + 274780813U, // ADDPv4i16 + 275829389U, // ADDPv4i32 + 276877965U, // ADDPv8i16 + 277926541U, // ADDPv8i8 + 403715414U, // ADDSWri + 403715414U, // ADDSWrs + 403715414U, // ADDSWrx + 403715414U, // ADDSXri + 403715414U, // ADDSXrs + 403715414U, // ADDSXrx + 403715414U, // ADDSXrx64 + 815850378U, // ADDVA_MPPZ_D + 816898954U, // ADDVA_MPPZ_S + 403714308U, // ADDVL_XXI + 269498576U, // ADDVv16i8v + 269498576U, // ADDVv4i16v + 269498576U, // ADDVv4i32v + 269498576U, // ADDVv8i16v + 269498576U, // ADDVv8i8v + 403712445U, // ADDWri + 403712445U, // ADDWrs + 403712445U, // ADDWrx + 403712445U, // ADDXri + 403712445U, // ADDXrs + 403712445U, // ADDXrx + 403712445U, // ADDXrx64 + 1880115645U, // ADD_ZI_B + 1209035197U, // ADD_ZI_D + 1089505725U, // ADD_ZI_H + 2014357949U, // ADD_ZI_S + 1611680189U, // ADD_ZPmZ_B + 1611688381U, // ADD_ZPmZ_D + 1759545789U, // ADD_ZPmZ_H + 1611704765U, // ADD_ZPmZ_S + 1880115645U, // ADD_ZZZ_B + 1209035197U, // ADD_ZZZ_D + 1089505725U, // ADD_ZZZ_H + 2014357949U, // ADD_ZZZ_S + 271632829U, // ADDv16i8 + 403712445U, // ADDv1i64 + 272681405U, // ADDv2i32 + 273729981U, // ADDv2i64 + 274778557U, // ADDv4i16 + 275827133U, // ADDv4i32 + 276875709U, // ADDv8i16 + 277924285U, // ADDv8i8 + 403715035U, // ADR + 2148545300U, // ADRP + 1224766427U, // ADR_LSL_ZZZ_D_0 + 1224766427U, // ADR_LSL_ZZZ_D_1 + 1224766427U, // ADR_LSL_ZZZ_D_2 + 1224766427U, // ADR_LSL_ZZZ_D_3 + 2030089179U, // ADR_LSL_ZZZ_S_0 + 2030089179U, // ADR_LSL_ZZZ_S_1 + 2030089179U, // ADR_LSL_ZZZ_S_2 + 2030089179U, // ADR_LSL_ZZZ_S_3 + 1224766427U, // ADR_SXTW_ZZZ_D_0 + 1224766427U, // ADR_SXTW_ZZZ_D_1 + 1224766427U, // ADR_SXTW_ZZZ_D_2 + 1224766427U, // ADR_SXTW_ZZZ_D_3 + 1224766427U, // ADR_UXTW_ZZZ_D_0 + 1224766427U, // ADR_UXTW_ZZZ_D_1 + 1224766427U, // ADR_UXTW_ZZZ_D_2 + 1224766427U, // ADR_UXTW_ZZZ_D_3 + 1880115773U, // AESD_ZZZ_B + 1479608893U, // AESDrr + 1880115920U, // AESE_ZZZ_B + 1479609040U, // AESErr + 1880115454U, // AESIMC_ZZ_B + 271632638U, // AESIMCrr + 1880115462U, // AESMC_ZZ_B + 271632646U, // AESMCrr + 403715421U, // ANDSWri + 403715421U, // ANDSWrs + 403715421U, // ANDSXri + 403715421U, // ANDSXrs + 1611683165U, // ANDS_PPzPP + 80100U, // ANDV_VPZ_B + 823220452U, // ANDV_VPZ_D + 824277220U, // ANDV_VPZ_H + 819042532U, // ANDV_VPZ_S + 403712539U, // ANDWri + 403712539U, // ANDWrs + 403712539U, // ANDXri + 403712539U, // ANDXrs + 1611680283U, // AND_PPzPP + 1209035291U, // AND_ZI + 1611680283U, // AND_ZPmZ_B + 1611688475U, // AND_ZPmZ_D + 1759545883U, // AND_ZPmZ_H + 1611704859U, // AND_ZPmZ_S + 1209035291U, // AND_ZZZ + 271632923U, // ANDv16i8 + 277924379U, // ANDv8i8 + 1611680311U, // ASRD_ZPmI_B + 1611688503U, // ASRD_ZPmI_D + 1759545911U, // ASRD_ZPmI_H + 1611704887U, // ASRD_ZPmI_S + 1611682939U, // ASRR_ZPmZ_B + 1611691131U, // ASRR_ZPmZ_D + 1759548539U, // ASRR_ZPmZ_H + 1611707515U, // ASRR_ZPmZ_S + 403715207U, // ASRVWr + 403715207U, // ASRVXr + 1611682951U, // ASR_WIDE_ZPmZ_B + 1759548551U, // ASR_WIDE_ZPmZ_H + 1611707527U, // ASR_WIDE_ZPmZ_S + 1880118407U, // ASR_WIDE_ZZZ_B + 1089508487U, // ASR_WIDE_ZZZ_H + 2014360711U, // ASR_WIDE_ZZZ_S + 1611682951U, // ASR_ZPmI_B + 1611691143U, // ASR_ZPmI_D + 1759548551U, // ASR_ZPmI_H + 1611707527U, // ASR_ZPmI_S + 1611682951U, // ASR_ZPmZ_B + 1611691143U, // ASR_ZPmZ_D + 1759548551U, // ASR_ZPmZ_H + 1611707527U, // ASR_ZPmZ_S + 1880118407U, // ASR_ZZI_B + 1209037959U, // ASR_ZZI_D + 1089508487U, // ASR_ZZI_H + 2014360711U, // ASR_ZZI_S + 2282857129U, // AUTDA + 2282857703U, // AUTDB + 107441U, // AUTDZA + 108752U, // AUTDZB + 2282857157U, // AUTIA + 7230U, // AUTIA1716 + 7309U, // AUTIASP + 7300U, // AUTIAZ + 2282857730U, // AUTIB + 7239U, // AUTIB1716 + 7221U, // AUTIBSP + 7212U, // AUTIBZ + 107457U, // AUTIZA + 108768U, // AUTIZB + 7447U, // AXFLAG + 115660U, // B + 271637173U, // BCAX + 1209039541U, // BCAX_ZZZZ + 1880117912U, // BDEP_ZZZ_B + 1209037464U, // BDEP_ZZZ_D + 1089507992U, // BDEP_ZZZ_H + 2014360216U, // BDEP_ZZZ_S + 1880119434U, // BEXT_ZZZ_B + 1209038986U, // BEXT_ZZZ_D + 1089509514U, // BEXT_ZZZ_H + 2014361738U, // BEXT_ZZZ_S + 1480661020U, // BF16DOTlanev4bf16 + 1483806748U, // BF16DOTlanev8bf16 + 403716195U, // BFCVT + 274780648U, // BFCVTN + 1484849568U, // BFCVTN2 + 2418055126U, // BFCVTNT_ZPmZ + 2418055267U, // BFCVT_ZPmZ + 1343272988U, // BFDOT_ZZI + 1343272988U, // BFDOT_ZZZ + 1480661020U, // BFDOTv4bf16 + 1483806748U, // BFDOTv8bf16 + 1483801907U, // BFMLALB + 1483801907U, // BFMLALBIdx + 1483806400U, // BFMLALT + 1483806400U, // BFMLALTIdx + 1483801311U, // BFMMLA + 1343268147U, // BFMMLA_B_ZZI + 1343268147U, // BFMMLA_B_ZZZ + 1343272640U, // BFMMLA_T_ZZI + 1343272640U, // BFMMLA_T_ZZZ + 1343267551U, // BFMMLA_ZZZ + 2282762539U, // BFMWri + 2282762539U, // BFMXri + 1880118042U, // BGRP_ZZZ_B + 1209037594U, // BGRP_ZZZ_D + 1089508122U, // BGRP_ZZZ_H + 2014360346U, // BGRP_ZZZ_S + 403715408U, // BICSWrs + 403715408U, // BICSXrs + 1611683152U, // BICS_PPzPP + 403712249U, // BICWrs + 403712249U, // BICXrs + 1611679993U, // BIC_PPzPP + 1611679993U, // BIC_ZPmZ_B + 1611688185U, // BIC_ZPmZ_D + 1759545593U, // BIC_ZPmZ_H + 1611704569U, // BIC_ZPmZ_S + 1209035001U, // BIC_ZZZ + 271632633U, // BICv16i8 + 2554398969U, // BICv2i32 + 2556496121U, // BICv4i16 + 2557544697U, // BICv4i32 + 2558593273U, // BICv8i16 + 277924089U, // BICv8i8 + 1479609084U, // BIFv16i8 + 1485900540U, // BIFv8i8 + 1479612059U, // BITv16i8 + 1485903515U, // BITv8i8 + 118684U, // BL + 13325U, // BLR + 403710592U, // BLRAA + 15166U, // BLRAAZ + 403711090U, // BLRAB + 15181U, // BLRABZ + 13239U, // BR + 403710579U, // BRAA + 15159U, // BRAAZ + 403711077U, // BRAB + 15174U, // BRABZ + 7476U, // BRB_IALL + 7454U, // BRB_INJ + 126722U, // BRK + 1611683083U, // BRKAS_PPzP + 1065676U, // BRKA_PPmP + 1611678412U, // BRKA_PPzP + 1611683119U, // BRKBS_PPzP + 1066249U, // BRKB_PPmP + 1611678985U, // BRKB_PPzP + 1611683248U, // BRKNS_PPzP + 1611682216U, // BRKN_PPzP + 1611683090U, // BRKPAS_PPzPP + 1611678479U, // BRKPA_PPzPP + 1611683126U, // BRKPBS_PPzPP + 1611679511U, // BRKPB_PPzPP + 1209037172U, // BSL1N_ZZZZ + 1209037179U, // BSL2N_ZZZZ + 1209036977U, // BSL_ZZZZ + 1479610545U, // BSLv16i8 + 1485902001U, // BSLv8i8 + 138155U, // Bcc + 1880115644U, // CADD_ZZI_B + 1209035196U, // CADD_ZZI_D + 1089505724U, // CADD_ZZI_H + 2014357948U, // CADD_ZZI_S + 2282857611U, // CASAB + 2282859548U, // CASAH + 2282857854U, // CASALB + 2282859707U, // CASALH + 2282860407U, // CASALW + 2282860407U, // CASALX + 2282857324U, // CASAW + 2282857324U, // CASAX + 2282858466U, // CASB + 2282860092U, // CASH + 2282858060U, // CASLB + 2282859801U, // CASLH + 2282860714U, // CASLW + 2282860714U, // CASLX + 143190U, // CASPALW + 151382U, // CASPALX + 140078U, // CASPAW + 148270U, // CASPAX + 143501U, // CASPLW + 151693U, // CASPLX + 144160U, // CASPW + 152352U, // CASPX + 2282861830U, // CASW + 2282861830U, // CASX + 2685418340U, // CBNZW + 2685418340U, // CBNZX + 2685418325U, // CBZW + 2685418325U, // CBZX + 403714478U, // CCMNWi + 403714478U, // CCMNWr + 403714478U, // CCMNXi + 403714478U, // CCMNXr + 403714773U, // CCMPWi + 403714773U, // CCMPWr + 403714773U, // CCMPXi + 403714773U, // CCMPXr + 1343256598U, // CDOT_ZZZI_D + 2819667990U, // CDOT_ZZZI_S + 1343256598U, // CDOT_ZZZ_D + 2819667990U, // CDOT_ZZZ_S + 7510U, // CFINV + 1611670402U, // CLASTA_RPZ_B + 1611670402U, // CLASTA_RPZ_D + 1611670402U, // CLASTA_RPZ_H + 1611670402U, // CLASTA_RPZ_S + 1611670402U, // CLASTA_VPZ_B + 1611670402U, // CLASTA_VPZ_D + 1611670402U, // CLASTA_VPZ_H + 1611670402U, // CLASTA_VPZ_S + 1611678594U, // CLASTA_ZPZ_B + 1611686786U, // CLASTA_ZPZ_D + 1088455554U, // CLASTA_ZPZ_H + 1611703170U, // CLASTA_ZPZ_S + 1611671627U, // CLASTB_RPZ_B + 1611671627U, // CLASTB_RPZ_D + 1611671627U, // CLASTB_RPZ_H + 1611671627U, // CLASTB_RPZ_S + 1611671627U, // CLASTB_VPZ_B + 1611671627U, // CLASTB_VPZ_D + 1611671627U, // CLASTB_VPZ_H + 1611671627U, // CLASTB_VPZ_S + 1611679819U, // CLASTB_ZPZ_B + 1611688011U, // CLASTB_ZPZ_D + 1088456779U, // CLASTB_ZPZ_H + 1611704395U, // CLASTB_ZPZ_S + 15078U, // CLREX + 403715457U, // CLSWr + 403715457U, // CLSXr + 1070465U, // CLS_ZPmZ_B + 1078657U, // CLS_ZPmZ_D + 136353153U, // CLS_ZPmZ_H + 1095041U, // CLS_ZPmZ_S + 271635841U, // CLSv16i8 + 272684417U, // CLSv2i32 + 274781569U, // CLSv4i16 + 275830145U, // CLSv4i32 + 276878721U, // CLSv8i16 + 277927297U, // CLSv8i8 + 403716959U, // CLZWr + 403716959U, // CLZXr + 1071967U, // CLZ_ZPmZ_B + 1080159U, // CLZ_ZPmZ_D + 136354655U, // CLZ_ZPmZ_H + 1096543U, // CLZ_ZPmZ_S + 271637343U, // CLZv16i8 + 272685919U, // CLZv2i32 + 274783071U, // CLZv4i16 + 275831647U, // CLZv4i32 + 276880223U, // CLZv8i16 + 277928799U, // CLZv8i8 + 271635316U, // CMEQv16i8 + 271635316U, // CMEQv16i8rz + 403714932U, // CMEQv1i64 + 403714932U, // CMEQv1i64rz + 272683892U, // CMEQv2i32 + 272683892U, // CMEQv2i32rz + 273732468U, // CMEQv2i64 + 273732468U, // CMEQv2i64rz + 274781044U, // CMEQv4i16 + 274781044U, // CMEQv4i16rz + 275829620U, // CMEQv4i32 + 275829620U, // CMEQv4i32rz + 276878196U, // CMEQv8i16 + 276878196U, // CMEQv8i16rz + 277926772U, // CMEQv8i8 + 277926772U, // CMEQv8i8rz + 271633006U, // CMGEv16i8 + 271633006U, // CMGEv16i8rz + 403712622U, // CMGEv1i64 + 403712622U, // CMGEv1i64rz + 272681582U, // CMGEv2i32 + 272681582U, // CMGEv2i32rz + 273730158U, // CMGEv2i64 + 273730158U, // CMGEv2i64rz + 274778734U, // CMGEv4i16 + 274778734U, // CMGEv4i16rz + 275827310U, // CMGEv4i32 + 275827310U, // CMGEv4i32rz + 276875886U, // CMGEv8i16 + 276875886U, // CMGEv8i16rz + 277924462U, // CMGEv8i8 + 277924462U, // CMGEv8i8rz + 271636109U, // CMGTv16i8 + 271636109U, // CMGTv16i8rz + 403715725U, // CMGTv1i64 + 403715725U, // CMGTv1i64rz + 272684685U, // CMGTv2i32 + 272684685U, // CMGTv2i32rz + 273733261U, // CMGTv2i64 + 273733261U, // CMGTv2i64rz + 274781837U, // CMGTv4i16 + 274781837U, // CMGTv4i16rz + 275830413U, // CMGTv4i32 + 275830413U, // CMGTv4i32rz + 276878989U, // CMGTv8i16 + 276878989U, // CMGTv8i16rz + 277927565U, // CMGTv8i8 + 277927565U, // CMGTv8i8rz + 271634130U, // CMHIv16i8 + 403713746U, // CMHIv1i64 + 272682706U, // CMHIv2i32 + 273731282U, // CMHIv2i64 + 274779858U, // CMHIv4i16 + 275828434U, // CMHIv4i32 + 276877010U, // CMHIv8i16 + 277925586U, // CMHIv8i8 + 271635828U, // CMHSv16i8 + 403715444U, // CMHSv1i64 + 272684404U, // CMHSv2i32 + 273732980U, // CMHSv2i64 + 274781556U, // CMHSv4i16 + 275830132U, // CMHSv4i32 + 276878708U, // CMHSv8i16 + 277927284U, // CMHSv8i8 + 1092649683U, // CMLA_ZZZI_H + 672178899U, // CMLA_ZZZI_S + 2819637971U, // CMLA_ZZZ_B + 537944787U, // CMLA_ZZZ_D + 1092649683U, // CMLA_ZZZ_H + 672178899U, // CMLA_ZZZ_S + 271633037U, // CMLEv16i8rz + 403712653U, // CMLEv1i64rz + 272681613U, // CMLEv2i32rz + 273730189U, // CMLEv2i64rz + 274778765U, // CMLEv4i16rz + 275827341U, // CMLEv4i32rz + 276875917U, // CMLEv8i16rz + 277924493U, // CMLEv8i8rz + 271636312U, // CMLTv16i8rz + 403715928U, // CMLTv1i64rz + 272684888U, // CMLTv2i32rz + 273733464U, // CMLTv2i64rz + 274782040U, // CMLTv4i16rz + 275830616U, // CMLTv4i32rz + 276879192U, // CMLTv8i16rz + 277927768U, // CMLTv8i8rz + 1611682691U, // CMPEQ_PPzZI_B + 1611690883U, // CMPEQ_PPzZI_D + 2967507843U, // CMPEQ_PPzZI_H + 1611707267U, // CMPEQ_PPzZI_S + 1611682691U, // CMPEQ_PPzZZ_B + 1611690883U, // CMPEQ_PPzZZ_D + 2967507843U, // CMPEQ_PPzZZ_H + 1611707267U, // CMPEQ_PPzZZ_S + 1611682691U, // CMPEQ_WIDE_PPzZZ_B + 2967507843U, // CMPEQ_WIDE_PPzZZ_H + 1611707267U, // CMPEQ_WIDE_PPzZZ_S + 1611680372U, // CMPGE_PPzZI_B + 1611688564U, // CMPGE_PPzZI_D + 2967505524U, // CMPGE_PPzZI_H + 1611704948U, // CMPGE_PPzZI_S + 1611680372U, // CMPGE_PPzZZ_B + 1611688564U, // CMPGE_PPzZZ_D + 2967505524U, // CMPGE_PPzZZ_H + 1611704948U, // CMPGE_PPzZZ_S + 1611680372U, // CMPGE_WIDE_PPzZZ_B + 2967505524U, // CMPGE_WIDE_PPzZZ_H + 1611704948U, // CMPGE_WIDE_PPzZZ_S + 1611683475U, // CMPGT_PPzZI_B + 1611691667U, // CMPGT_PPzZI_D + 2967508627U, // CMPGT_PPzZI_H + 1611708051U, // CMPGT_PPzZI_S + 1611683475U, // CMPGT_PPzZZ_B + 1611691667U, // CMPGT_PPzZZ_D + 2967508627U, // CMPGT_PPzZZ_H + 1611708051U, // CMPGT_PPzZZ_S + 1611683475U, // CMPGT_WIDE_PPzZZ_B + 2967508627U, // CMPGT_WIDE_PPzZZ_H + 1611708051U, // CMPGT_WIDE_PPzZZ_S + 1611681496U, // CMPHI_PPzZI_B + 1611689688U, // CMPHI_PPzZI_D + 2967506648U, // CMPHI_PPzZI_H + 1611706072U, // CMPHI_PPzZI_S + 1611681496U, // CMPHI_PPzZZ_B + 1611689688U, // CMPHI_PPzZZ_D + 2967506648U, // CMPHI_PPzZZ_H + 1611706072U, // CMPHI_PPzZZ_S + 1611681496U, // CMPHI_WIDE_PPzZZ_B + 2967506648U, // CMPHI_WIDE_PPzZZ_H + 1611706072U, // CMPHI_WIDE_PPzZZ_S + 1611683194U, // CMPHS_PPzZI_B + 1611691386U, // CMPHS_PPzZI_D + 2967508346U, // CMPHS_PPzZI_H + 1611707770U, // CMPHS_PPzZI_S + 1611683194U, // CMPHS_PPzZZ_B + 1611691386U, // CMPHS_PPzZZ_D + 2967508346U, // CMPHS_PPzZZ_H + 1611707770U, // CMPHS_PPzZZ_S + 1611683194U, // CMPHS_WIDE_PPzZZ_B + 2967508346U, // CMPHS_WIDE_PPzZZ_H + 1611707770U, // CMPHS_WIDE_PPzZZ_S + 1611680403U, // CMPLE_PPzZI_B + 1611688595U, // CMPLE_PPzZI_D + 2967505555U, // CMPLE_PPzZI_H + 1611704979U, // CMPLE_PPzZI_S + 1611680403U, // CMPLE_WIDE_PPzZZ_B + 2967505555U, // CMPLE_WIDE_PPzZZ_H + 1611704979U, // CMPLE_WIDE_PPzZZ_S + 1611682379U, // CMPLO_PPzZI_B + 1611690571U, // CMPLO_PPzZI_D + 2967507531U, // CMPLO_PPzZI_H + 1611706955U, // CMPLO_PPzZI_S + 1611682379U, // CMPLO_WIDE_PPzZZ_B + 2967507531U, // CMPLO_WIDE_PPzZZ_H + 1611706955U, // CMPLO_WIDE_PPzZZ_S + 1611683228U, // CMPLS_PPzZI_B + 1611691420U, // CMPLS_PPzZI_D + 2967508380U, // CMPLS_PPzZI_H + 1611707804U, // CMPLS_PPzZI_S + 1611683228U, // CMPLS_WIDE_PPzZZ_B + 2967508380U, // CMPLS_WIDE_PPzZZ_H + 1611707804U, // CMPLS_WIDE_PPzZZ_S + 1611683678U, // CMPLT_PPzZI_B + 1611691870U, // CMPLT_PPzZI_D + 2967508830U, // CMPLT_PPzZI_H + 1611708254U, // CMPLT_PPzZI_S + 1611683678U, // CMPLT_WIDE_PPzZZ_B + 2967508830U, // CMPLT_WIDE_PPzZZ_H + 1611708254U, // CMPLT_WIDE_PPzZZ_S + 1611680426U, // CMPNE_PPzZI_B + 1611688618U, // CMPNE_PPzZI_D + 2967505578U, // CMPNE_PPzZI_H + 1611705002U, // CMPNE_PPzZI_S + 1611680426U, // CMPNE_PPzZZ_B + 1611688618U, // CMPNE_PPzZZ_D + 2967505578U, // CMPNE_PPzZZ_H + 1611705002U, // CMPNE_PPzZZ_S + 1611680426U, // CMPNE_WIDE_PPzZZ_B + 2967505578U, // CMPNE_WIDE_PPzZZ_H + 1611705002U, // CMPNE_WIDE_PPzZZ_S + 271636572U, // CMTSTv16i8 + 403716188U, // CMTSTv1i64 + 272685148U, // CMTSTv2i32 + 273733724U, // CMTSTv2i64 + 274782300U, // CMTSTv4i16 + 275830876U, // CMTSTv4i32 + 276879452U, // CMTSTv8i16 + 277928028U, // CMTSTv8i8 + 1071153U, // CNOT_ZPmZ_B + 1079345U, // CNOT_ZPmZ_D + 136353841U, // CNOT_ZPmZ_H + 1095729U, // CNOT_ZPmZ_S + 3088066622U, // CNTB_XPiI + 3088067139U, // CNTD_XPiI + 3088068221U, // CNTH_XPiI + 1611674406U, // CNTP_XPP_B + 1611674406U, // CNTP_XPP_D + 1611674406U, // CNTP_XPP_H + 1611674406U, // CNTP_XPP_S + 3088071297U, // CNTW_XPiI + 1070995U, // CNT_ZPmZ_B + 1079187U, // CNT_ZPmZ_D + 136353683U, // CNT_ZPmZ_H + 1095571U, // CNT_ZPmZ_S + 271636371U, // CNTv16i8 + 277927827U, // CNTv8i8 + 1611691617U, // COMPACT_ZPZ_D + 1611708001U, // COMPACT_ZPZ_S + 1071902U, // CPY_ZPmI_B + 1080094U, // CPY_ZPmI_D + 3223362334U, // CPY_ZPmI_H + 1096478U, // CPY_ZPmI_S + 1071902U, // CPY_ZPmR_B + 1080094U, // CPY_ZPmR_D + 3357580062U, // CPY_ZPmR_H + 1096478U, // CPY_ZPmR_S + 1071902U, // CPY_ZPmV_B + 1080094U, // CPY_ZPmV_D + 3357580062U, // CPY_ZPmV_H + 1096478U, // CPY_ZPmV_S + 1611684638U, // CPY_ZPzI_B + 1611692830U, // CPY_ZPzI_D + 2967509790U, // CPY_ZPzI_H + 1611709214U, // CPY_ZPzI_S + 269498688U, // CPYi16 + 269498688U, // CPYi32 + 269498688U, // CPYi64 + 269498688U, // CPYi8 + 403710974U, // CRC32Brr + 403711151U, // CRC32CBrr + 403713088U, // CRC32CHrr + 403716562U, // CRC32CWrr + 403716822U, // CRC32CXrr + 403712924U, // CRC32Hrr + 403716504U, // CRC32Wrr + 403716761U, // CRC32Xrr + 403714044U, // CSELWr + 403714044U, // CSELXr + 403712269U, // CSINCWr + 403712269U, // CSINCXr + 403716408U, // CSINVWr + 403716408U, // CSINVXr + 403712832U, // CSNEGWr + 403712832U, // CSNEGXr + 403714938U, // CTERMEQ_WW + 403714938U, // CTERMEQ_XX + 403712673U, // CTERMNE_WW + 403712673U, // CTERMNE_XX + 122944U, // DCPS1 + 123372U, // DCPS2 + 123438U, // DCPS3 + 3490718906U, // DECB_XPiI + 3490720157U, // DECD_XPiI + 3490736541U, // DECD_ZPiI + 3490720843U, // DECH_XPiI + 19958859U, // DECH_ZPiI + 1880109678U, // DECP_XP_B + 1209021038U, // DECP_XP_D + 940585582U, // DECP_XP_H + 2014327406U, // DECP_XP_S + 537948782U, // DECP_ZP_D + 824218222U, // DECP_ZP_H + 672182894U, // DECP_ZP_S + 3490724317U, // DECW_XPiI + 3490757085U, // DECW_ZPiI + 157330U, // DMB + 7492U, // DRPS + 157672U, // DSB + 165864U, // DSBnXS + 3624956255U, // DUPM_ZI + 3759166266U, // DUP_ZI_B + 3893392186U, // DUP_ZI_D + 21009210U, // DUP_ZI_H + 4027626298U, // DUP_ZI_S + 403723066U, // DUP_ZR_B + 403731258U, // DUP_ZR_D + 827364154U, // DUP_ZR_H + 403747642U, // DUP_ZR_S + 1880118074U, // DUP_ZZI_B + 1209037626U, // DUP_ZZI_D + 4176515898U, // DUP_ZZI_H + 4183995194U, // DUP_ZZI_Q + 2014360378U, // DUP_ZZI_S + 405852986U, // DUPv16i8gpr + 271635258U, // DUPv16i8lane + 406901562U, // DUPv2i32gpr + 272683834U, // DUPv2i32lane + 407950138U, // DUPv2i64gpr + 273732410U, // DUPv2i64lane + 408998714U, // DUPv4i16gpr + 274780986U, // DUPv4i16lane + 410047290U, // DUPv4i32gpr + 275829562U, // DUPv4i32lane + 411095866U, // DUPv8i16gpr + 276878138U, // DUPv8i16lane + 412144442U, // DUPv8i8gpr + 277926714U, // DUPv8i8lane + 403714484U, // EONWrs + 403714484U, // EONXrs + 271630888U, // EOR3 + 1209033256U, // EOR3_ZZZZ + 2819642970U, // EORBT_ZZZ_B + 537949786U, // EORBT_ZZZ_D + 1092654682U, // EORBT_ZZZ_H + 672183898U, // EORBT_ZZZ_S + 1611683329U, // EORS_PPzPP + 2819639364U, // EORTB_ZZZ_B + 537946180U, // EORTB_ZZZ_D + 1092651076U, // EORTB_ZZZ_H + 672180292U, // EORTB_ZZZ_S + 80209U, // EORV_VPZ_B + 823220561U, // EORV_VPZ_D + 824277329U, // EORV_VPZ_H + 819042641U, // EORV_VPZ_S + 403715168U, // EORWri + 403715168U, // EORWrs + 403715168U, // EORXri + 403715168U, // EORXrs + 1611682912U, // EOR_PPzPP + 1209037920U, // EOR_ZI + 1611682912U, // EOR_ZPmZ_B + 1611691104U, // EOR_ZPmZ_D + 1759548512U, // EOR_ZPmZ_H + 1611707488U, // EOR_ZPmZ_S + 1209037920U, // EOR_ZZZ + 271635552U, // EORv16i8 + 277927008U, // EORv8i8 + 7497U, // ERET + 7423U, // ERETAA + 7430U, // ERETAB + 1611678609U, // EXTRACT_ZPMXI_H_B + 1611686801U, // EXTRACT_ZPMXI_H_D + 1759544209U, // EXTRACT_ZPMXI_H_H + 1759683473U, // EXTRACT_ZPMXI_H_Q + 1611703185U, // EXTRACT_ZPMXI_H_S + 1611678609U, // EXTRACT_ZPMXI_V_B + 1611686801U, // EXTRACT_ZPMXI_V_D + 1759544209U, // EXTRACT_ZPMXI_V_H + 1759683473U, // EXTRACT_ZPMXI_V_Q + 1611703185U, // EXTRACT_ZPMXI_V_S + 403715245U, // EXTRWrri + 403715245U, // EXTRXrri + 1880119435U, // EXT_ZZI + 1071243U, // EXT_ZZI_B + 271636619U, // EXTv16i8 + 277928075U, // EXTv8i8 + 403712386U, // FABD16 + 403712386U, // FABD32 + 403712386U, // FABD64 + 1611688322U, // FABD_ZPmZ_D + 1759545730U, // FABD_ZPmZ_H + 1611704706U, // FABD_ZPmZ_S + 272681346U, // FABDv2f32 + 273729922U, // FABDv2f64 + 274778498U, // FABDv4f16 + 275827074U, // FABDv4f32 + 276875650U, // FABDv8f16 + 403715362U, // FABSDr + 403715362U, // FABSHr + 403715362U, // FABSSr + 1078562U, // FABS_ZPmZ_D + 136353058U, // FABS_ZPmZ_H + 1094946U, // FABS_ZPmZ_S + 272684322U, // FABSv2f32 + 273732898U, // FABSv2f64 + 274781474U, // FABSv4f16 + 275830050U, // FABSv4f32 + 276878626U, // FABSv8f16 + 403712605U, // FACGE16 + 403712605U, // FACGE32 + 403712605U, // FACGE64 + 1611688541U, // FACGE_PPzZZ_D + 2967505501U, // FACGE_PPzZZ_H + 1611704925U, // FACGE_PPzZZ_S + 272681565U, // FACGEv2f32 + 273730141U, // FACGEv2f64 + 274778717U, // FACGEv4f16 + 275827293U, // FACGEv4f32 + 276875869U, // FACGEv8f16 + 403715708U, // FACGT16 + 403715708U, // FACGT32 + 403715708U, // FACGT64 + 1611691644U, // FACGT_PPzZZ_D + 2967508604U, // FACGT_PPzZZ_H + 1611708028U, // FACGT_PPzZZ_S + 272684668U, // FACGTv2f32 + 273733244U, // FACGTv2f64 + 274781820U, // FACGTv4f16 + 275830396U, // FACGTv4f32 + 276878972U, // FACGTv8f16 + 24199842U, // FADDA_VPZ_D + 1098998434U, // FADDA_VPZ_H + 26313378U, // FADDA_VPZ_S + 403712465U, // FADDDrr + 403712465U, // FADDHrr + 1611690636U, // FADDP_ZPmZZ_D + 1759548044U, // FADDP_ZPmZZ_H + 1611707020U, // FADDP_ZPmZZ_S + 272683660U, // FADDPv2f32 + 273732236U, // FADDPv2f64 + 269496972U, // FADDPv2i16p + 269496972U, // FADDPv2i32p + 269496972U, // FADDPv2i64p + 274780812U, // FADDPv4f16 + 275829388U, // FADDPv4f32 + 276877964U, // FADDPv8f16 + 403712465U, // FADDSrr + 823220431U, // FADDV_VPZ_D + 824277199U, // FADDV_VPZ_H + 819042511U, // FADDV_VPZ_S + 1611688401U, // FADD_ZPmI_D + 1759545809U, // FADD_ZPmI_H + 1611704785U, // FADD_ZPmI_S + 1611688401U, // FADD_ZPmZ_D + 1759545809U, // FADD_ZPmZ_H + 1611704785U, // FADD_ZPmZ_S + 1209035217U, // FADD_ZZZ_D + 1089505745U, // FADD_ZZZ_H + 2014357969U, // FADD_ZZZ_S + 272681425U, // FADDv2f32 + 273730001U, // FADDv2f64 + 274778577U, // FADDv4f16 + 275827153U, // FADDv4f32 + 276875729U, // FADDv8f16 + 1611688379U, // FCADD_ZPmZ_D + 1759545787U, // FCADD_ZPmZ_H + 1611704763U, // FCADD_ZPmZ_S + 272681403U, // FCADDv2f32 + 273729979U, // FCADDv2f64 + 274778555U, // FCADDv4f16 + 275827131U, // FCADDv4f32 + 276875707U, // FCADDv8f16 + 403714772U, // FCCMPDrr + 403712705U, // FCCMPEDrr + 403712705U, // FCCMPEHrr + 403712705U, // FCCMPESrr + 403714772U, // FCCMPHrr + 403714772U, // FCCMPSrr + 403714931U, // FCMEQ16 + 403714931U, // FCMEQ32 + 403714931U, // FCMEQ64 + 1611690867U, // FCMEQ_PPzZ0_D + 2967507827U, // FCMEQ_PPzZ0_H + 1611707251U, // FCMEQ_PPzZ0_S + 1611690867U, // FCMEQ_PPzZZ_D + 2967507827U, // FCMEQ_PPzZZ_H + 1611707251U, // FCMEQ_PPzZZ_S + 403714931U, // FCMEQv1i16rz + 403714931U, // FCMEQv1i32rz + 403714931U, // FCMEQv1i64rz + 272683891U, // FCMEQv2f32 + 273732467U, // FCMEQv2f64 + 272683891U, // FCMEQv2i32rz + 273732467U, // FCMEQv2i64rz + 274781043U, // FCMEQv4f16 + 275829619U, // FCMEQv4f32 + 274781043U, // FCMEQv4i16rz + 275829619U, // FCMEQv4i32rz + 276878195U, // FCMEQv8f16 + 276878195U, // FCMEQv8i16rz + 403712621U, // FCMGE16 + 403712621U, // FCMGE32 + 403712621U, // FCMGE64 + 1611688557U, // FCMGE_PPzZ0_D + 2967505517U, // FCMGE_PPzZ0_H + 1611704941U, // FCMGE_PPzZ0_S + 1611688557U, // FCMGE_PPzZZ_D + 2967505517U, // FCMGE_PPzZZ_H + 1611704941U, // FCMGE_PPzZZ_S + 403712621U, // FCMGEv1i16rz + 403712621U, // FCMGEv1i32rz + 403712621U, // FCMGEv1i64rz + 272681581U, // FCMGEv2f32 + 273730157U, // FCMGEv2f64 + 272681581U, // FCMGEv2i32rz + 273730157U, // FCMGEv2i64rz + 274778733U, // FCMGEv4f16 + 275827309U, // FCMGEv4f32 + 274778733U, // FCMGEv4i16rz + 275827309U, // FCMGEv4i32rz + 276875885U, // FCMGEv8f16 + 276875885U, // FCMGEv8i16rz + 403715724U, // FCMGT16 + 403715724U, // FCMGT32 + 403715724U, // FCMGT64 + 1611691660U, // FCMGT_PPzZ0_D + 2967508620U, // FCMGT_PPzZ0_H + 1611708044U, // FCMGT_PPzZ0_S + 1611691660U, // FCMGT_PPzZZ_D + 2967508620U, // FCMGT_PPzZZ_H + 1611708044U, // FCMGT_PPzZZ_S + 403715724U, // FCMGTv1i16rz + 403715724U, // FCMGTv1i32rz + 403715724U, // FCMGTv1i64rz + 272684684U, // FCMGTv2f32 + 273733260U, // FCMGTv2f64 + 272684684U, // FCMGTv2i32rz + 273733260U, // FCMGTv2i64rz + 274781836U, // FCMGTv4f16 + 275830412U, // FCMGTv4f32 + 274781836U, // FCMGTv4i16rz + 275830412U, // FCMGTv4i32rz + 276878988U, // FCMGTv8f16 + 276878988U, // FCMGTv8i16rz + 1611686610U, // FCMLA_ZPmZZ_D + 1759544018U, // FCMLA_ZPmZZ_H + 1611702994U, // FCMLA_ZPmZZ_S + 1092649682U, // FCMLA_ZZZI_H + 672178898U, // FCMLA_ZZZI_S + 1480655570U, // FCMLAv2f32 + 1481704146U, // FCMLAv2f64 + 1482752722U, // FCMLAv4f16 + 1482752722U, // FCMLAv4f16_indexed + 1483801298U, // FCMLAv4f32 + 1483801298U, // FCMLAv4f32_indexed + 1484849874U, // FCMLAv8f16 + 1484849874U, // FCMLAv8f16_indexed + 1611688588U, // FCMLE_PPzZ0_D + 2967505548U, // FCMLE_PPzZ0_H + 1611704972U, // FCMLE_PPzZ0_S + 403712652U, // FCMLEv1i16rz + 403712652U, // FCMLEv1i32rz + 403712652U, // FCMLEv1i64rz + 272681612U, // FCMLEv2i32rz + 273730188U, // FCMLEv2i64rz + 274778764U, // FCMLEv4i16rz + 275827340U, // FCMLEv4i32rz + 276875916U, // FCMLEv8i16rz + 1611691863U, // FCMLT_PPzZ0_D + 2967508823U, // FCMLT_PPzZ0_H + 1611708247U, // FCMLT_PPzZ0_S + 403715927U, // FCMLTv1i16rz + 403715927U, // FCMLTv1i32rz + 403715927U, // FCMLTv1i64rz + 272684887U, // FCMLTv2i32rz + 273733463U, // FCMLTv2i64rz + 274782039U, // FCMLTv4i16rz + 275830615U, // FCMLTv4i32rz + 276879191U, // FCMLTv8i16rz + 1611688602U, // FCMNE_PPzZ0_D + 2967505562U, // FCMNE_PPzZ0_H + 1611704986U, // FCMNE_PPzZ0_S + 1611688602U, // FCMNE_PPzZZ_D + 2967505562U, // FCMNE_PPzZZ_H + 1611704986U, // FCMNE_PPzZZ_S + 27275995U, // FCMPDri + 403714779U, // FCMPDrr + 27273929U, // FCMPEDri + 403712713U, // FCMPEDrr + 27273929U, // FCMPEHri + 403712713U, // FCMPEHrr + 27273929U, // FCMPESri + 403712713U, // FCMPESrr + 27275995U, // FCMPHri + 403714779U, // FCMPHrr + 27275995U, // FCMPSri + 403714779U, // FCMPSrr + 1611690584U, // FCMUO_PPzZZ_D + 2967507544U, // FCMUO_PPzZZ_H + 1611706968U, // FCMUO_PPzZZ_S + 1080093U, // FCPY_ZPmI_D + 136354589U, // FCPY_ZPmI_H + 1096477U, // FCPY_ZPmI_S + 403714043U, // FCSELDrrr + 403714043U, // FCSELHrrr + 403714043U, // FCSELSrrr + 403715354U, // FCVTASUWDr + 403715354U, // FCVTASUWHr + 403715354U, // FCVTASUWSr + 403715354U, // FCVTASUXDr + 403715354U, // FCVTASUXHr + 403715354U, // FCVTASUXSr + 403715354U, // FCVTASv1f16 + 403715354U, // FCVTASv1i32 + 403715354U, // FCVTASv1i64 + 272684314U, // FCVTASv2f32 + 273732890U, // FCVTASv2f64 + 274781466U, // FCVTASv4f16 + 275830042U, // FCVTASv4f32 + 276878618U, // FCVTASv8f16 + 403716247U, // FCVTAUUWDr + 403716247U, // FCVTAUUWHr + 403716247U, // FCVTAUUWSr + 403716247U, // FCVTAUUXDr + 403716247U, // FCVTAUUXHr + 403716247U, // FCVTAUUXSr + 403716247U, // FCVTAUv1f16 + 403716247U, // FCVTAUv1i32 + 403716247U, // FCVTAUv1i64 + 272685207U, // FCVTAUv2f32 + 273733783U, // FCVTAUv2f64 + 274782359U, // FCVTAUv4f16 + 275830935U, // FCVTAUv4f32 + 276879511U, // FCVTAUv8f16 + 403716196U, // FCVTDHr + 403716196U, // FCVTDSr + 403716196U, // FCVTHDr + 403716196U, // FCVTHSr + 1095559U, // FCVTLT_ZPmZ_HtoS + 1079175U, // FCVTLT_ZPmZ_StoD + 273731810U, // FCVTLv2i32 + 275828962U, // FCVTLv4i16 + 273727834U, // FCVTLv4i32 + 275824986U, // FCVTLv8i16 + 403715491U, // FCVTMSUWDr + 403715491U, // FCVTMSUWHr + 403715491U, // FCVTMSUWSr + 403715491U, // FCVTMSUXDr + 403715491U, // FCVTMSUXHr + 403715491U, // FCVTMSUXSr + 403715491U, // FCVTMSv1f16 + 403715491U, // FCVTMSv1i32 + 403715491U, // FCVTMSv1i64 + 272684451U, // FCVTMSv2f32 + 273733027U, // FCVTMSv2f64 + 274781603U, // FCVTMSv4f16 + 275830179U, // FCVTMSv4f32 + 276878755U, // FCVTMSv8f16 + 403716263U, // FCVTMUUWDr + 403716263U, // FCVTMUUWHr + 403716263U, // FCVTMUUWSr + 403716263U, // FCVTMUUXDr + 403716263U, // FCVTMUUXHr + 403716263U, // FCVTMUUXSr + 403716263U, // FCVTMUv1f16 + 403716263U, // FCVTMUv1i32 + 403716263U, // FCVTMUv1i64 + 272685223U, // FCVTMUv2f32 + 273733799U, // FCVTMUv2f64 + 274782375U, // FCVTMUv4f16 + 275830951U, // FCVTMUv4f32 + 276879527U, // FCVTMUv8f16 + 403715517U, // FCVTNSUWDr + 403715517U, // FCVTNSUWHr + 403715517U, // FCVTNSUWSr + 403715517U, // FCVTNSUXDr + 403715517U, // FCVTNSUXHr + 403715517U, // FCVTNSUXSr + 403715517U, // FCVTNSv1f16 + 403715517U, // FCVTNSv1i32 + 403715517U, // FCVTNSv1i64 + 272684477U, // FCVTNSv2f32 + 273733053U, // FCVTNSv2f64 + 274781629U, // FCVTNSv4f16 + 275830205U, // FCVTNSv4f32 + 276878781U, // FCVTNSv8f16 + 1095639U, // FCVTNT_ZPmZ_DtoS + 2418055127U, // FCVTNT_ZPmZ_StoH + 403716271U, // FCVTNUUWDr + 403716271U, // FCVTNUUWHr + 403716271U, // FCVTNUUWSr + 403716271U, // FCVTNUUXDr + 403716271U, // FCVTNUUXHr + 403716271U, // FCVTNUUXSr + 403716271U, // FCVTNUv1f16 + 403716271U, // FCVTNUv1i32 + 403716271U, // FCVTNUv1i64 + 272685231U, // FCVTNUv2f32 + 273733807U, // FCVTNUv2f64 + 274782383U, // FCVTNUv4f16 + 275830959U, // FCVTNUv4f32 + 276879535U, // FCVTNUv8f16 + 272683497U, // FCVTNv2i32 + 274780649U, // FCVTNv4i16 + 1483800993U, // FCVTNv4i32 + 1484849569U, // FCVTNv8i16 + 403715564U, // FCVTPSUWDr + 403715564U, // FCVTPSUWHr + 403715564U, // FCVTPSUWSr + 403715564U, // FCVTPSUXDr + 403715564U, // FCVTPSUXHr + 403715564U, // FCVTPSUXSr + 403715564U, // FCVTPSv1f16 + 403715564U, // FCVTPSv1i32 + 403715564U, // FCVTPSv1i64 + 272684524U, // FCVTPSv2f32 + 273733100U, // FCVTPSv2f64 + 274781676U, // FCVTPSv4f16 + 275830252U, // FCVTPSv4f32 + 276878828U, // FCVTPSv8f16 + 403716279U, // FCVTPUUWDr + 403716279U, // FCVTPUUWHr + 403716279U, // FCVTPUUWSr + 403716279U, // FCVTPUUXDr + 403716279U, // FCVTPUUXHr + 403716279U, // FCVTPUUXSr + 403716279U, // FCVTPUv1f16 + 403716279U, // FCVTPUv1i32 + 403716279U, // FCVTPUv1i64 + 272685239U, // FCVTPUv2f32 + 273733815U, // FCVTPUv2f64 + 274782391U, // FCVTPUv4f16 + 275830967U, // FCVTPUv4f32 + 276879543U, // FCVTPUv8f16 + 403716196U, // FCVTSDr + 403716196U, // FCVTSHr + 1095693U, // FCVTXNT_ZPmZ_DtoS + 403714591U, // FCVTXNv1i64 + 272683551U, // FCVTXNv2f32 + 1483801047U, // FCVTXNv4f32 + 1096461U, // FCVTX_ZPmZ_DtoS + 403715617U, // FCVTZSSWDri + 403715617U, // FCVTZSSWHri + 403715617U, // FCVTZSSWSri + 403715617U, // FCVTZSSXDri + 403715617U, // FCVTZSSXHri + 403715617U, // FCVTZSSXSri + 403715617U, // FCVTZSUWDr + 403715617U, // FCVTZSUWHr + 403715617U, // FCVTZSUWSr + 403715617U, // FCVTZSUXDr + 403715617U, // FCVTZSUXHr + 403715617U, // FCVTZSUXSr + 1078817U, // FCVTZS_ZPmZ_DtoD + 1095201U, // FCVTZS_ZPmZ_DtoS + 1078817U, // FCVTZS_ZPmZ_HtoD + 136353313U, // FCVTZS_ZPmZ_HtoH + 1095201U, // FCVTZS_ZPmZ_HtoS + 1078817U, // FCVTZS_ZPmZ_StoD + 1095201U, // FCVTZS_ZPmZ_StoS + 403715617U, // FCVTZSd + 403715617U, // FCVTZSh + 403715617U, // FCVTZSs + 403715617U, // FCVTZSv1f16 + 403715617U, // FCVTZSv1i32 + 403715617U, // FCVTZSv1i64 + 272684577U, // FCVTZSv2f32 + 273733153U, // FCVTZSv2f64 + 272684577U, // FCVTZSv2i32_shift + 273733153U, // FCVTZSv2i64_shift + 274781729U, // FCVTZSv4f16 + 275830305U, // FCVTZSv4f32 + 274781729U, // FCVTZSv4i16_shift + 275830305U, // FCVTZSv4i32_shift + 276878881U, // FCVTZSv8f16 + 276878881U, // FCVTZSv8i16_shift + 403716287U, // FCVTZUSWDri + 403716287U, // FCVTZUSWHri + 403716287U, // FCVTZUSWSri + 403716287U, // FCVTZUSXDri + 403716287U, // FCVTZUSXHri + 403716287U, // FCVTZUSXSri + 403716287U, // FCVTZUUWDr + 403716287U, // FCVTZUUWHr + 403716287U, // FCVTZUUWSr + 403716287U, // FCVTZUUXDr + 403716287U, // FCVTZUUXHr + 403716287U, // FCVTZUUXSr + 1079487U, // FCVTZU_ZPmZ_DtoD + 1095871U, // FCVTZU_ZPmZ_DtoS + 1079487U, // FCVTZU_ZPmZ_HtoD + 136353983U, // FCVTZU_ZPmZ_HtoH + 1095871U, // FCVTZU_ZPmZ_HtoS + 1079487U, // FCVTZU_ZPmZ_StoD + 1095871U, // FCVTZU_ZPmZ_StoS + 403716287U, // FCVTZUd + 403716287U, // FCVTZUh + 403716287U, // FCVTZUs + 403716287U, // FCVTZUv1f16 + 403716287U, // FCVTZUv1i32 + 403716287U, // FCVTZUv1i64 + 272685247U, // FCVTZUv2f32 + 273733823U, // FCVTZUv2f64 + 272685247U, // FCVTZUv2i32_shift + 273733823U, // FCVTZUv2i64_shift + 274782399U, // FCVTZUv4f16 + 275830975U, // FCVTZUv4f32 + 274782399U, // FCVTZUv4i16_shift + 275830975U, // FCVTZUv4i32_shift + 276879551U, // FCVTZUv8f16 + 276879551U, // FCVTZUv8i16_shift + 270571620U, // FCVT_ZPmZ_DtoH + 1095780U, // FCVT_ZPmZ_DtoS + 1079396U, // FCVT_ZPmZ_HtoD + 1095780U, // FCVT_ZPmZ_HtoS + 1079396U, // FCVT_ZPmZ_StoD + 2418055268U, // FCVT_ZPmZ_StoH + 403716335U, // FDIVDrr + 403716335U, // FDIVHrr + 1611691214U, // FDIVR_ZPmZ_D + 1759548622U, // FDIVR_ZPmZ_H + 1611707598U, // FDIVR_ZPmZ_S + 403716335U, // FDIVSrr + 1611692271U, // FDIV_ZPmZ_D + 1759549679U, // FDIV_ZPmZ_H + 1611708655U, // FDIV_ZPmZ_S + 272685295U, // FDIVv2f32 + 273733871U, // FDIVv2f64 + 274782447U, // FDIVv4f16 + 275831023U, // FDIVv4f32 + 276879599U, // FDIVv8f16 + 403731257U, // FDUP_ZI_D + 28349241U, // FDUP_ZI_H + 403747641U, // FDUP_ZI_S + 1209033531U, // FEXPA_ZZ_D + 821068603U, // FEXPA_ZZ_H + 2014356283U, // FEXPA_ZZ_S + 403715625U, // FJCVTZS + 1074420U, // FLOGB_ZPmZ_D + 136348916U, // FLOGB_ZPmZ_H + 1090804U, // FLOGB_ZPmZ_S + 403712501U, // FMADDDrrr + 403712501U, // FMADDHrrr + 403712501U, // FMADDSrrr + 1611688302U, // FMAD_ZPmZZ_D + 1759545710U, // FMAD_ZPmZZ_H + 1611704686U, // FMAD_ZPmZZ_S + 403716795U, // FMAXDrr + 403716795U, // FMAXHrr + 403714391U, // FMAXNMDrr + 403714391U, // FMAXNMHrr + 1611690730U, // FMAXNMP_ZPmZZ_D + 1759548138U, // FMAXNMP_ZPmZZ_H + 1611707114U, // FMAXNMP_ZPmZZ_S + 272683754U, // FMAXNMPv2f32 + 273732330U, // FMAXNMPv2f64 + 269497066U, // FMAXNMPv2i16p + 269497066U, // FMAXNMPv2i32p + 269497066U, // FMAXNMPv2i64p + 274780906U, // FMAXNMPv4f16 + 275829482U, // FMAXNMPv4f32 + 276878058U, // FMAXNMPv8f16 + 403714391U, // FMAXNMSrr + 823220506U, // FMAXNMV_VPZ_D + 824277274U, // FMAXNMV_VPZ_H + 819042586U, // FMAXNMV_VPZ_S + 269498650U, // FMAXNMVv4i16v + 269498650U, // FMAXNMVv4i32v + 269498650U, // FMAXNMVv8i16v + 1611690327U, // FMAXNM_ZPmI_D + 1759547735U, // FMAXNM_ZPmI_H + 1611706711U, // FMAXNM_ZPmI_S + 1611690327U, // FMAXNM_ZPmZ_D + 1759547735U, // FMAXNM_ZPmZ_H + 1611706711U, // FMAXNM_ZPmZ_S + 272683351U, // FMAXNMv2f32 + 273731927U, // FMAXNMv2f64 + 274780503U, // FMAXNMv4f16 + 275829079U, // FMAXNMv4f32 + 276877655U, // FMAXNMv8f16 + 1611690827U, // FMAXP_ZPmZZ_D + 1759548235U, // FMAXP_ZPmZZ_H + 1611707211U, // FMAXP_ZPmZZ_S + 272683851U, // FMAXPv2f32 + 273732427U, // FMAXPv2f64 + 269497163U, // FMAXPv2i16p + 269497163U, // FMAXPv2i32p + 269497163U, // FMAXPv2i64p + 274781003U, // FMAXPv4f16 + 275829579U, // FMAXPv4f32 + 276878155U, // FMAXPv8f16 + 403716795U, // FMAXSrr + 823220567U, // FMAXV_VPZ_D + 824277335U, // FMAXV_VPZ_H + 819042647U, // FMAXV_VPZ_S + 269498711U, // FMAXVv4i16v + 269498711U, // FMAXVv4i32v + 269498711U, // FMAXVv8i16v + 1611692731U, // FMAX_ZPmI_D + 1759550139U, // FMAX_ZPmI_H + 1611709115U, // FMAX_ZPmI_S + 1611692731U, // FMAX_ZPmZ_D + 1759550139U, // FMAX_ZPmZ_H + 1611709115U, // FMAX_ZPmZ_S + 272685755U, // FMAXv2f32 + 273734331U, // FMAXv2f64 + 274782907U, // FMAXv4f16 + 275831483U, // FMAXv4f32 + 276880059U, // FMAXv8f16 + 403714450U, // FMINDrr + 403714450U, // FMINHrr + 403714383U, // FMINNMDrr + 403714383U, // FMINNMHrr + 1611690721U, // FMINNMP_ZPmZZ_D + 1759548129U, // FMINNMP_ZPmZZ_H + 1611707105U, // FMINNMP_ZPmZZ_S + 272683745U, // FMINNMPv2f32 + 273732321U, // FMINNMPv2f64 + 269497057U, // FMINNMPv2i16p + 269497057U, // FMINNMPv2i32p + 269497057U, // FMINNMPv2i64p + 274780897U, // FMINNMPv4f16 + 275829473U, // FMINNMPv4f32 + 276878049U, // FMINNMPv8f16 + 403714383U, // FMINNMSrr + 823220497U, // FMINNMV_VPZ_D + 824277265U, // FMINNMV_VPZ_H + 819042577U, // FMINNMV_VPZ_S + 269498641U, // FMINNMVv4i16v + 269498641U, // FMINNMVv4i32v + 269498641U, // FMINNMVv8i16v + 1611690319U, // FMINNM_ZPmI_D + 1759547727U, // FMINNM_ZPmI_H + 1611706703U, // FMINNM_ZPmI_S + 1611690319U, // FMINNM_ZPmZ_D + 1759547727U, // FMINNM_ZPmZ_H + 1611706703U, // FMINNM_ZPmZ_S + 272683343U, // FMINNMv2f32 + 273731919U, // FMINNMv2f64 + 274780495U, // FMINNMv4f16 + 275829071U, // FMINNMv4f32 + 276877647U, // FMINNMv8f16 + 1611690745U, // FMINP_ZPmZZ_D + 1759548153U, // FMINP_ZPmZZ_H + 1611707129U, // FMINP_ZPmZZ_S + 272683769U, // FMINPv2f32 + 273732345U, // FMINPv2f64 + 269497081U, // FMINPv2i16p + 269497081U, // FMINPv2i32p + 269497081U, // FMINPv2i64p + 274780921U, // FMINPv4f16 + 275829497U, // FMINPv4f32 + 276878073U, // FMINPv8f16 + 403714450U, // FMINSrr + 823220515U, // FMINV_VPZ_D + 824277283U, // FMINV_VPZ_H + 819042595U, // FMINV_VPZ_S + 269498659U, // FMINVv4i16v + 269498659U, // FMINVv4i32v + 269498659U, // FMINVv8i16v + 1611690386U, // FMIN_ZPmI_D + 1759547794U, // FMIN_ZPmI_H + 1611706770U, // FMIN_ZPmI_S + 1611690386U, // FMIN_ZPmZ_D + 1759547794U, // FMIN_ZPmZ_H + 1611706770U, // FMIN_ZPmZ_S + 272683410U, // FMINv2f32 + 273731986U, // FMINv2f64 + 274780562U, // FMINv4f16 + 275829138U, // FMINv4f32 + 276877714U, // FMINv8f16 + 1480655038U, // FMLAL2lanev4f16 + 1483800766U, // FMLAL2lanev8f16 + 1480655038U, // FMLAL2v4f16 + 1483800766U, // FMLAL2v8f16 + 1343268148U, // FMLALB_ZZZI_SHH + 1343268148U, // FMLALB_ZZZ_SHH + 1343272641U, // FMLALT_ZZZI_SHH + 1343272641U, // FMLALT_ZZZ_SHH + 1480658733U, // FMLALlanev4f16 + 1483804461U, // FMLALlanev8f16 + 1480658733U, // FMLALv4f16 + 1483804461U, // FMLALv8f16 + 1611686617U, // FMLA_ZPmZZ_D + 1759544025U, // FMLA_ZPmZZ_H + 1611703001U, // FMLA_ZPmZZ_S + 537944793U, // FMLA_ZZZI_D + 1092649689U, // FMLA_ZZZI_H + 672178905U, // FMLA_ZZZI_S + 2282857177U, // FMLAv1i16_indexed + 2282857177U, // FMLAv1i32_indexed + 2282857177U, // FMLAv1i64_indexed + 1480655577U, // FMLAv2f32 + 1481704153U, // FMLAv2f64 + 1480655577U, // FMLAv2i32_indexed + 1481704153U, // FMLAv2i64_indexed + 1482752729U, // FMLAv4f16 + 1483801305U, // FMLAv4f32 + 1482752729U, // FMLAv4i16_indexed + 1483801305U, // FMLAv4i32_indexed + 1484849881U, // FMLAv8f16 + 1484849881U, // FMLAv8i16_indexed + 1480655170U, // FMLSL2lanev4f16 + 1483800898U, // FMLSL2lanev8f16 + 1480655170U, // FMLSL2v4f16 + 1483800898U, // FMLSL2v8f16 + 1343268445U, // FMLSLB_ZZZI_SHH + 1343268445U, // FMLSLB_ZZZ_SHH + 1343272815U, // FMLSLT_ZZZI_SHH + 1343272815U, // FMLSLT_ZZZ_SHH + 1480659135U, // FMLSLlanev4f16 + 1483804863U, // FMLSLlanev8f16 + 1480659135U, // FMLSLv4f16 + 1483804863U, // FMLSLv8f16 + 1611691407U, // FMLS_ZPmZZ_D + 1759548815U, // FMLS_ZPmZZ_H + 1611707791U, // FMLS_ZPmZZ_S + 537949583U, // FMLS_ZZZI_D + 1092654479U, // FMLS_ZZZI_H + 672183695U, // FMLS_ZZZI_S + 2282861967U, // FMLSv1i16_indexed + 2282861967U, // FMLSv1i32_indexed + 2282861967U, // FMLSv1i64_indexed + 1480660367U, // FMLSv2f32 + 1481708943U, // FMLSv2f64 + 1480660367U, // FMLSv2i32_indexed + 1481708943U, // FMLSv2i64_indexed + 1482757519U, // FMLSv4f16 + 1483806095U, // FMLSv4f32 + 1482757519U, // FMLSv4i16_indexed + 1483806095U, // FMLSv4i32_indexed + 1484854671U, // FMLSv8f16 + 1484854671U, // FMLSv8i16_indexed + 537944800U, // FMMLA_ZZZ_D + 672178912U, // FMMLA_ZZZ_S + 1084285719U, // FMOPA_MPPZZ_D + 1085334295U, // FMOPA_MPPZZ_S + 1084290517U, // FMOPS_MPPZZ_D + 1085339093U, // FMOPS_MPPZZ_S + 269498687U, // FMOVDXHighr + 403716415U, // FMOVDXr + 403716415U, // FMOVDi + 403716415U, // FMOVDr + 403716415U, // FMOVHWr + 403716415U, // FMOVHXr + 403716415U, // FMOVHi + 403716415U, // FMOVHr + 403716415U, // FMOVSWr + 403716415U, // FMOVSi + 403716415U, // FMOVSr + 403716415U, // FMOVWHr + 403716415U, // FMOVWSr + 432068927U, // FMOVXDHighr + 403716415U, // FMOVXDr + 403716415U, // FMOVXHr + 406903103U, // FMOVv2f32_ns + 407951679U, // FMOVv2f64_ns + 409000255U, // FMOVv4f16_ns + 410048831U, // FMOVv4f32_ns + 411097407U, // FMOVv8f16_ns + 1611687922U, // FMSB_ZPmZZ_D + 1759545330U, // FMSB_ZPmZZ_H + 1611704306U, // FMSB_ZPmZZ_S + 403712115U, // FMSUBDrrr + 403712115U, // FMSUBHrrr + 403712115U, // FMSUBSrrr + 403714281U, // FMULDrr + 403714281U, // FMULHrr + 403714281U, // FMULSrr + 403716854U, // FMULX16 + 403716854U, // FMULX32 + 403716854U, // FMULX64 + 1611692790U, // FMULX_ZPmZ_D + 1759550198U, // FMULX_ZPmZ_H + 1611709174U, // FMULX_ZPmZ_S + 403716854U, // FMULXv1i16_indexed + 403716854U, // FMULXv1i32_indexed + 403716854U, // FMULXv1i64_indexed + 272685814U, // FMULXv2f32 + 273734390U, // FMULXv2f64 + 272685814U, // FMULXv2i32_indexed + 273734390U, // FMULXv2i64_indexed + 274782966U, // FMULXv4f16 + 275831542U, // FMULXv4f32 + 274782966U, // FMULXv4i16_indexed + 275831542U, // FMULXv4i32_indexed + 276880118U, // FMULXv8f16 + 276880118U, // FMULXv8i16_indexed + 1611690217U, // FMUL_ZPmI_D + 1759547625U, // FMUL_ZPmI_H + 1611706601U, // FMUL_ZPmI_S + 1611690217U, // FMUL_ZPmZ_D + 1759547625U, // FMUL_ZPmZ_H + 1611706601U, // FMUL_ZPmZ_S + 1209037033U, // FMUL_ZZZI_D + 1089507561U, // FMUL_ZZZI_H + 2014359785U, // FMUL_ZZZI_S + 1209037033U, // FMUL_ZZZ_D + 1089507561U, // FMUL_ZZZ_H + 2014359785U, // FMUL_ZZZ_S + 403714281U, // FMULv1i16_indexed + 403714281U, // FMULv1i32_indexed + 403714281U, // FMULv1i64_indexed + 272683241U, // FMULv2f32 + 273731817U, // FMULv2f64 + 272683241U, // FMULv2i32_indexed + 273731817U, // FMULv2i64_indexed + 274780393U, // FMULv4f16 + 275828969U, // FMULv4f32 + 274780393U, // FMULv4i16_indexed + 275828969U, // FMULv4i32_indexed + 276877545U, // FMULv8f16 + 276877545U, // FMULv8i16_indexed + 403712819U, // FNEGDr + 403712819U, // FNEGHr + 403712819U, // FNEGSr + 1076019U, // FNEG_ZPmZ_D + 136350515U, // FNEG_ZPmZ_H + 1092403U, // FNEG_ZPmZ_S + 272681779U, // FNEGv2f32 + 273730355U, // FNEGv2f64 + 274778931U, // FNEGv4f16 + 275827507U, // FNEGv4f32 + 276876083U, // FNEGv8f16 + 403712508U, // FNMADDDrrr + 403712508U, // FNMADDHrrr + 403712508U, // FNMADDSrrr + 1611688308U, // FNMAD_ZPmZZ_D + 1759545716U, // FNMAD_ZPmZZ_H + 1611704692U, // FNMAD_ZPmZZ_S + 1611686646U, // FNMLA_ZPmZZ_D + 1759544054U, // FNMLA_ZPmZZ_H + 1611703030U, // FNMLA_ZPmZZ_S + 1611691413U, // FNMLS_ZPmZZ_D + 1759548821U, // FNMLS_ZPmZZ_H + 1611707797U, // FNMLS_ZPmZZ_S + 1611687928U, // FNMSB_ZPmZZ_D + 1759545336U, // FNMSB_ZPmZZ_H + 1611704312U, // FNMSB_ZPmZZ_S + 403712122U, // FNMSUBDrrr + 403712122U, // FNMSUBHrrr + 403712122U, // FNMSUBSrrr + 403714287U, // FNMULDrr + 403714287U, // FNMULHrr + 403714287U, // FNMULSrr + 1209035441U, // FRECPE_ZZ_D + 821070513U, // FRECPE_ZZ_H + 2014358193U, // FRECPE_ZZ_S + 403712689U, // FRECPEv1f16 + 403712689U, // FRECPEv1i32 + 403712689U, // FRECPEv1i64 + 272681649U, // FRECPEv2f32 + 273730225U, // FRECPEv2f64 + 274778801U, // FRECPEv4f16 + 275827377U, // FRECPEv4f32 + 276875953U, // FRECPEv8f16 + 403715532U, // FRECPS16 + 403715532U, // FRECPS32 + 403715532U, // FRECPS64 + 1209038284U, // FRECPS_ZZZ_D + 1089508812U, // FRECPS_ZZZ_H + 2014361036U, // FRECPS_ZZZ_S + 272684492U, // FRECPSv2f32 + 273733068U, // FRECPSv2f64 + 274781644U, // FRECPSv4f16 + 275830220U, // FRECPSv4f32 + 276878796U, // FRECPSv8f16 + 1080061U, // FRECPX_ZPmZ_D + 136354557U, // FRECPX_ZPmZ_H + 1096445U, // FRECPX_ZPmZ_S + 403716861U, // FRECPXv1f16 + 403716861U, // FRECPXv1i32 + 403716861U, // FRECPXv1i64 + 403716769U, // FRINT32XDr + 403716769U, // FRINT32XSr + 272685729U, // FRINT32Xv2f32 + 273734305U, // FRINT32Xv2f64 + 275831457U, // FRINT32Xv4f32 + 403716899U, // FRINT32ZDr + 403716899U, // FRINT32ZSr + 272685859U, // FRINT32Zv2f32 + 273734435U, // FRINT32Zv2f64 + 275831587U, // FRINT32Zv4f32 + 403716779U, // FRINT64XDr + 403716779U, // FRINT64XSr + 272685739U, // FRINT64Xv2f32 + 273734315U, // FRINT64Xv2f64 + 275831467U, // FRINT64Xv4f32 + 403716909U, // FRINT64ZDr + 403716909U, // FRINT64ZSr + 272685869U, // FRINT64Zv2f32 + 273734445U, // FRINT64Zv2f64 + 275831597U, // FRINT64Zv4f32 + 403710842U, // FRINTADr + 403710842U, // FRINTAHr + 403710842U, // FRINTASr + 1074042U, // FRINTA_ZPmZ_D + 136348538U, // FRINTA_ZPmZ_H + 1090426U, // FRINTA_ZPmZ_S + 272679802U, // FRINTAv2f32 + 273728378U, // FRINTAv2f64 + 274776954U, // FRINTAv4f16 + 275825530U, // FRINTAv4f32 + 276874106U, // FRINTAv8f16 + 403713780U, // FRINTIDr + 403713780U, // FRINTIHr + 403713780U, // FRINTISr + 1076980U, // FRINTI_ZPmZ_D + 136351476U, // FRINTI_ZPmZ_H + 1093364U, // FRINTI_ZPmZ_S + 272682740U, // FRINTIv2f32 + 273731316U, // FRINTIv2f64 + 274779892U, // FRINTIv4f16 + 275828468U, // FRINTIv4f32 + 276877044U, // FRINTIv8f16 + 403714405U, // FRINTMDr + 403714405U, // FRINTMHr + 403714405U, // FRINTMSr + 1077605U, // FRINTM_ZPmZ_D + 136352101U, // FRINTM_ZPmZ_H + 1093989U, // FRINTM_ZPmZ_S + 272683365U, // FRINTMv2f32 + 273731941U, // FRINTMv2f64 + 274780517U, // FRINTMv4f16 + 275829093U, // FRINTMv4f32 + 276877669U, // FRINTMv8f16 + 403714528U, // FRINTNDr + 403714528U, // FRINTNHr + 403714528U, // FRINTNSr + 1077728U, // FRINTN_ZPmZ_D + 136352224U, // FRINTN_ZPmZ_H + 1094112U, // FRINTN_ZPmZ_S + 272683488U, // FRINTNv2f32 + 273732064U, // FRINTNv2f64 + 274780640U, // FRINTNv4f16 + 275829216U, // FRINTNv4f32 + 276877792U, // FRINTNv8f16 + 403714860U, // FRINTPDr + 403714860U, // FRINTPHr + 403714860U, // FRINTPSr + 1078060U, // FRINTP_ZPmZ_D + 136352556U, // FRINTP_ZPmZ_H + 1094444U, // FRINTP_ZPmZ_S + 272683820U, // FRINTPv2f32 + 273732396U, // FRINTPv2f64 + 274780972U, // FRINTPv4f16 + 275829548U, // FRINTPv4f32 + 276878124U, // FRINTPv8f16 + 403716869U, // FRINTXDr + 403716869U, // FRINTXHr + 403716869U, // FRINTXSr + 1080069U, // FRINTX_ZPmZ_D + 136354565U, // FRINTX_ZPmZ_H + 1096453U, // FRINTX_ZPmZ_S + 272685829U, // FRINTXv2f32 + 273734405U, // FRINTXv2f64 + 274782981U, // FRINTXv4f16 + 275831557U, // FRINTXv4f32 + 276880133U, // FRINTXv8f16 + 403716976U, // FRINTZDr + 403716976U, // FRINTZHr + 403716976U, // FRINTZSr + 1080176U, // FRINTZ_ZPmZ_D + 136354672U, // FRINTZ_ZPmZ_H + 1096560U, // FRINTZ_ZPmZ_S + 272685936U, // FRINTZv2f32 + 273734512U, // FRINTZv2f64 + 274783088U, // FRINTZv4f16 + 275831664U, // FRINTZv4f32 + 276880240U, // FRINTZv8f16 + 1209035486U, // FRSQRTE_ZZ_D + 821070558U, // FRSQRTE_ZZ_H + 2014358238U, // FRSQRTE_ZZ_S + 403712734U, // FRSQRTEv1f16 + 403712734U, // FRSQRTEv1i32 + 403712734U, // FRSQRTEv1i64 + 272681694U, // FRSQRTEv2f32 + 273730270U, // FRSQRTEv2f64 + 274778846U, // FRSQRTEv4f16 + 275827422U, // FRSQRTEv4f32 + 276875998U, // FRSQRTEv8f16 + 403715603U, // FRSQRTS16 + 403715603U, // FRSQRTS32 + 403715603U, // FRSQRTS64 + 1209038355U, // FRSQRTS_ZZZ_D + 1089508883U, // FRSQRTS_ZZZ_H + 2014361107U, // FRSQRTS_ZZZ_S + 272684563U, // FRSQRTSv2f32 + 273733139U, // FRSQRTSv2f64 + 274781715U, // FRSQRTSv4f16 + 275830291U, // FRSQRTSv4f32 + 276878867U, // FRSQRTSv8f16 + 1611688571U, // FSCALE_ZPmZ_D + 1759545979U, // FSCALE_ZPmZ_H + 1611704955U, // FSCALE_ZPmZ_S + 403716159U, // FSQRTDr + 403716159U, // FSQRTHr + 403716159U, // FSQRTSr + 1079359U, // FSQRT_ZPmZ_D + 136353855U, // FSQRT_ZPmZ_H + 1095743U, // FSQRT_ZPmZ_S + 272685119U, // FSQRTv2f32 + 273733695U, // FSQRTv2f64 + 274782271U, // FSQRTv4f16 + 275830847U, // FSQRTv4f32 + 276879423U, // FSQRTv8f16 + 403712095U, // FSUBDrr + 403712095U, // FSUBHrr + 1611690932U, // FSUBR_ZPmI_D + 1759548340U, // FSUBR_ZPmI_H + 1611707316U, // FSUBR_ZPmI_S + 1611690932U, // FSUBR_ZPmZ_D + 1759548340U, // FSUBR_ZPmZ_H + 1611707316U, // FSUBR_ZPmZ_S + 403712095U, // FSUBSrr + 1611688031U, // FSUB_ZPmI_D + 1759545439U, // FSUB_ZPmI_H + 1611704415U, // FSUB_ZPmI_S + 1611688031U, // FSUB_ZPmZ_D + 1759545439U, // FSUB_ZPmZ_H + 1611704415U, // FSUB_ZPmZ_S + 1209034847U, // FSUB_ZZZ_D + 1089505375U, // FSUB_ZZZ_H + 2014357599U, // FSUB_ZZZ_S + 272681055U, // FSUBv2f32 + 273729631U, // FSUBv2f64 + 274778207U, // FSUBv4f16 + 275826783U, // FSUBv4f32 + 276875359U, // FSUBv8f16 + 1209035131U, // FTMAD_ZZI_D + 1089505659U, // FTMAD_ZZI_H + 2014357883U, // FTMAD_ZZI_S + 1209037052U, // FTSMUL_ZZZ_D + 1089507580U, // FTSMUL_ZZZ_H + 2014359804U, // FTSMUL_ZZZ_S + 1209036808U, // FTSSEL_ZZZ_D + 1089507336U, // FTSSEL_ZZZ_H + 2014359560U, // FTSSEL_ZZZ_S + 567460809U, // GLD1B_D_IMM_REAL + 2312291273U, // GLD1B_D_REAL + 2312291273U, // GLD1B_D_SXTW_REAL + 2312291273U, // GLD1B_D_UXTW_REAL + 701686729U, // GLD1B_S_IMM_REAL + 2312299465U, // GLD1B_S_SXTW_REAL + 2312299465U, // GLD1B_S_UXTW_REAL + 567462174U, // GLD1D_IMM_REAL + 2312292638U, // GLD1D_REAL + 2312292638U, // GLD1D_SCALED_REAL + 2312292638U, // GLD1D_SXTW_REAL + 2312292638U, // GLD1D_SXTW_SCALED_REAL + 2312292638U, // GLD1D_UXTW_REAL + 2312292638U, // GLD1D_UXTW_SCALED_REAL + 567462759U, // GLD1H_D_IMM_REAL + 2312293223U, // GLD1H_D_REAL + 2312293223U, // GLD1H_D_SCALED_REAL + 2312293223U, // GLD1H_D_SXTW_REAL + 2312293223U, // GLD1H_D_SXTW_SCALED_REAL + 2312293223U, // GLD1H_D_UXTW_REAL + 2312293223U, // GLD1H_D_UXTW_SCALED_REAL + 701688679U, // GLD1H_S_IMM_REAL + 2312301415U, // GLD1H_S_SXTW_REAL + 2312301415U, // GLD1H_S_SXTW_SCALED_REAL + 2312301415U, // GLD1H_S_UXTW_REAL + 2312301415U, // GLD1H_S_UXTW_SCALED_REAL + 567461824U, // GLD1SB_D_IMM_REAL + 2312292288U, // GLD1SB_D_REAL + 2312292288U, // GLD1SB_D_SXTW_REAL + 2312292288U, // GLD1SB_D_UXTW_REAL + 701687744U, // GLD1SB_S_IMM_REAL + 2312300480U, // GLD1SB_S_SXTW_REAL + 2312300480U, // GLD1SB_S_UXTW_REAL + 567463450U, // GLD1SH_D_IMM_REAL + 2312293914U, // GLD1SH_D_REAL + 2312293914U, // GLD1SH_D_SCALED_REAL + 2312293914U, // GLD1SH_D_SXTW_REAL + 2312293914U, // GLD1SH_D_SXTW_SCALED_REAL + 2312293914U, // GLD1SH_D_UXTW_REAL + 2312293914U, // GLD1SH_D_UXTW_SCALED_REAL + 701689370U, // GLD1SH_S_IMM_REAL + 2312302106U, // GLD1SH_S_SXTW_REAL + 2312302106U, // GLD1SH_S_SXTW_SCALED_REAL + 2312302106U, // GLD1SH_S_UXTW_REAL + 2312302106U, // GLD1SH_S_UXTW_SCALED_REAL + 567466543U, // GLD1SW_D_IMM_REAL + 2312297007U, // GLD1SW_D_REAL + 2312297007U, // GLD1SW_D_SCALED_REAL + 2312297007U, // GLD1SW_D_SXTW_REAL + 2312297007U, // GLD1SW_D_SXTW_SCALED_REAL + 2312297007U, // GLD1SW_D_UXTW_REAL + 2312297007U, // GLD1SW_D_UXTW_SCALED_REAL + 567466348U, // GLD1W_D_IMM_REAL + 2312296812U, // GLD1W_D_REAL + 2312296812U, // GLD1W_D_SCALED_REAL + 2312296812U, // GLD1W_D_SXTW_REAL + 2312296812U, // GLD1W_D_SXTW_SCALED_REAL + 2312296812U, // GLD1W_D_UXTW_REAL + 2312296812U, // GLD1W_D_UXTW_SCALED_REAL + 701692268U, // GLD1W_IMM_REAL + 2312305004U, // GLD1W_SXTW_REAL + 2312305004U, // GLD1W_SXTW_SCALED_REAL + 2312305004U, // GLD1W_UXTW_REAL + 2312305004U, // GLD1W_UXTW_SCALED_REAL + 567460815U, // GLDFF1B_D_IMM_REAL + 2312291279U, // GLDFF1B_D_REAL + 2312291279U, // GLDFF1B_D_SXTW_REAL + 2312291279U, // GLDFF1B_D_UXTW_REAL + 701686735U, // GLDFF1B_S_IMM_REAL + 2312299471U, // GLDFF1B_S_SXTW_REAL + 2312299471U, // GLDFF1B_S_UXTW_REAL + 567462180U, // GLDFF1D_IMM_REAL + 2312292644U, // GLDFF1D_REAL + 2312292644U, // GLDFF1D_SCALED_REAL + 2312292644U, // GLDFF1D_SXTW_REAL + 2312292644U, // GLDFF1D_SXTW_SCALED_REAL + 2312292644U, // GLDFF1D_UXTW_REAL + 2312292644U, // GLDFF1D_UXTW_SCALED_REAL + 567462765U, // GLDFF1H_D_IMM_REAL + 2312293229U, // GLDFF1H_D_REAL + 2312293229U, // GLDFF1H_D_SCALED_REAL + 2312293229U, // GLDFF1H_D_SXTW_REAL + 2312293229U, // GLDFF1H_D_SXTW_SCALED_REAL + 2312293229U, // GLDFF1H_D_UXTW_REAL + 2312293229U, // GLDFF1H_D_UXTW_SCALED_REAL + 701688685U, // GLDFF1H_S_IMM_REAL + 2312301421U, // GLDFF1H_S_SXTW_REAL + 2312301421U, // GLDFF1H_S_SXTW_SCALED_REAL + 2312301421U, // GLDFF1H_S_UXTW_REAL + 2312301421U, // GLDFF1H_S_UXTW_SCALED_REAL + 567461831U, // GLDFF1SB_D_IMM_REAL + 2312292295U, // GLDFF1SB_D_REAL + 2312292295U, // GLDFF1SB_D_SXTW_REAL + 2312292295U, // GLDFF1SB_D_UXTW_REAL + 701687751U, // GLDFF1SB_S_IMM_REAL + 2312300487U, // GLDFF1SB_S_SXTW_REAL + 2312300487U, // GLDFF1SB_S_UXTW_REAL + 567463457U, // GLDFF1SH_D_IMM_REAL + 2312293921U, // GLDFF1SH_D_REAL + 2312293921U, // GLDFF1SH_D_SCALED_REAL + 2312293921U, // GLDFF1SH_D_SXTW_REAL + 2312293921U, // GLDFF1SH_D_SXTW_SCALED_REAL + 2312293921U, // GLDFF1SH_D_UXTW_REAL + 2312293921U, // GLDFF1SH_D_UXTW_SCALED_REAL + 701689377U, // GLDFF1SH_S_IMM_REAL + 2312302113U, // GLDFF1SH_S_SXTW_REAL + 2312302113U, // GLDFF1SH_S_SXTW_SCALED_REAL + 2312302113U, // GLDFF1SH_S_UXTW_REAL + 2312302113U, // GLDFF1SH_S_UXTW_SCALED_REAL + 567466550U, // GLDFF1SW_D_IMM_REAL + 2312297014U, // GLDFF1SW_D_REAL + 2312297014U, // GLDFF1SW_D_SCALED_REAL + 2312297014U, // GLDFF1SW_D_SXTW_REAL + 2312297014U, // GLDFF1SW_D_SXTW_SCALED_REAL + 2312297014U, // GLDFF1SW_D_UXTW_REAL + 2312297014U, // GLDFF1SW_D_UXTW_SCALED_REAL + 567466354U, // GLDFF1W_D_IMM_REAL + 2312296818U, // GLDFF1W_D_REAL + 2312296818U, // GLDFF1W_D_SCALED_REAL + 2312296818U, // GLDFF1W_D_SXTW_REAL + 2312296818U, // GLDFF1W_D_SXTW_SCALED_REAL + 2312296818U, // GLDFF1W_D_UXTW_REAL + 2312296818U, // GLDFF1W_D_UXTW_SCALED_REAL + 701692274U, // GLDFF1W_IMM_REAL + 2312305010U, // GLDFF1W_SXTW_REAL + 2312305010U, // GLDFF1W_SXTW_SCALED_REAL + 2312305010U, // GLDFF1W_UXTW_REAL + 2312305010U, // GLDFF1W_UXTW_SCALED_REAL + 403713764U, // GMI + 202666U, // HINT + 1611691919U, // HISTCNT_ZPzZZ_D + 1611708303U, // HISTCNT_ZPzZZ_S + 1880116039U, // HISTSEG_ZZZ + 128800U, // HLT + 125204U, // HVC + 3490718922U, // INCB_XPiI + 3490720173U, // INCD_XPiI + 3490736557U, // INCD_ZPiI + 3490720859U, // INCH_XPiI + 19958875U, // INCH_ZPiI + 1880109694U, // INCP_XP_B + 1209021054U, // INCP_XP_D + 940585598U, // INCP_XP_H + 2014327422U, // INCP_XP_S + 537948798U, // INCP_ZP_D + 824218238U, // INCP_ZP_H + 672182910U, // INCP_ZP_S + 3490724333U, // INCW_XPiI + 3490757101U, // INCW_ZPiI + 537942751U, // INDEX_II_B + 403733215U, // INDEX_II_D + 702585567U, // INDEX_II_H + 403749599U, // INDEX_II_S + 537942751U, // INDEX_IR_B + 403733215U, // INDEX_IR_D + 2313198303U, // INDEX_IR_H + 403749599U, // INDEX_IR_S + 403725023U, // INDEX_RI_B + 403733215U, // INDEX_RI_D + 1095801567U, // INDEX_RI_H + 403749599U, // INDEX_RI_S + 403725023U, // INDEX_RR_B + 403733215U, // INDEX_RR_D + 1095801567U, // INDEX_RR_H + 403749599U, // INDEX_RR_S + 838017937U, // INSERT_MXIPZ_H_B + 838017937U, // INSERT_MXIPZ_H_D + 838017937U, // INSERT_MXIPZ_H_H + 838017937U, // INSERT_MXIPZ_H_Q + 838017937U, // INSERT_MXIPZ_H_S + 838026129U, // INSERT_MXIPZ_V_B + 838026129U, // INSERT_MXIPZ_V_D + 838026129U, // INSERT_MXIPZ_V_H + 838026129U, // INSERT_MXIPZ_V_Q + 838026129U, // INSERT_MXIPZ_V_S + 2282771606U, // INSR_ZR_B + 2282779798U, // INSR_ZR_D + 838898838U, // INSR_ZR_H + 2282796182U, // INSR_ZR_S + 940594326U, // INSR_ZV_B + 1074820246U, // INSR_ZV_D + 830510230U, // INSR_ZV_H + 1209054358U, // INSR_ZV_S + 3390117291U, // INSvi16gpr + 1376851371U, // INSvi16lane + 3391165867U, // INSvi32gpr + 1377899947U, // INSvi32lane + 3384874411U, // INSvi64gpr + 1371608491U, // INSvi64lane + 3392214443U, // INSvi8gpr + 1378948523U, // INSvi8lane + 403712848U, // IRG + 157677U, // ISB + 1611670403U, // LASTA_RPZ_B + 1611670403U, // LASTA_RPZ_D + 1611670403U, // LASTA_RPZ_H + 1611670403U, // LASTA_RPZ_S + 1611670403U, // LASTA_VPZ_B + 1611670403U, // LASTA_VPZ_D + 1611670403U, // LASTA_VPZ_H + 1611670403U, // LASTA_VPZ_S + 1611671628U, // LASTB_RPZ_B + 1611671628U, // LASTB_RPZ_D + 1611671628U, // LASTB_RPZ_H + 1611671628U, // LASTB_RPZ_S + 1611671628U, // LASTB_VPZ_B + 1611671628U, // LASTB_VPZ_D + 1611671628U, // LASTB_VPZ_H + 1611671628U, // LASTB_VPZ_S + 2312332233U, // LD1B + 2312291273U, // LD1B_D + 2312291273U, // LD1B_D_IMM_REAL + 2312340425U, // LD1B_H + 2312340425U, // LD1B_H_IMM_REAL + 2312332233U, // LD1B_IMM_REAL + 2312299465U, // LD1B_S + 2312299465U, // LD1B_S_IMM_REAL + 2312292638U, // LD1D + 2312292638U, // LD1D_IMM_REAL + 237609U, // LD1Fourv16b + 37994537U, // LD1Fourv16b_POST + 253993U, // LD1Fourv1d + 39059497U, // LD1Fourv1d_POST + 270377U, // LD1Fourv2d + 38027305U, // LD1Fourv2d_POST + 286761U, // LD1Fourv2s + 39092265U, // LD1Fourv2s_POST + 303145U, // LD1Fourv4h + 39108649U, // LD1Fourv4h_POST + 319529U, // LD1Fourv4s + 38076457U, // LD1Fourv4s_POST + 335913U, // LD1Fourv8b + 39141417U, // LD1Fourv8b_POST + 352297U, // LD1Fourv8h + 38109225U, // LD1Fourv8h_POST + 2312342375U, // LD1H + 2312293223U, // LD1H_D + 2312293223U, // LD1H_D_IMM_REAL + 2312342375U, // LD1H_IMM_REAL + 2312301415U, // LD1H_S + 2312301415U, // LD1H_S_IMM_REAL + 237609U, // LD1Onev16b + 40091689U, // LD1Onev16b_POST + 253993U, // LD1Onev1d + 41156649U, // LD1Onev1d_POST + 270377U, // LD1Onev2d + 40124457U, // LD1Onev2d_POST + 286761U, // LD1Onev2s + 41189417U, // LD1Onev2s_POST + 303145U, // LD1Onev4h + 41205801U, // LD1Onev4h_POST + 319529U, // LD1Onev4s + 40173609U, // LD1Onev4s_POST + 335913U, // LD1Onev8b + 41238569U, // LD1Onev8b_POST + 352297U, // LD1Onev8h + 40206377U, // LD1Onev8h_POST + 2312292140U, // LD1RB_D_IMM + 2312341292U, // LD1RB_H_IMM + 2312333100U, // LD1RB_IMM + 2312300332U, // LD1RB_S_IMM + 2312292912U, // LD1RD_IMM + 2312293766U, // LD1RH_D_IMM + 2312342918U, // LD1RH_IMM + 2312301958U, // LD1RH_S_IMM + 2312333071U, // LD1RO_B + 2312333071U, // LD1RO_B_IMM + 2312292896U, // LD1RO_D + 2312292896U, // LD1RO_D_IMM + 2312342896U, // LD1RO_H + 2312342896U, // LD1RO_H_IMM + 2312305167U, // LD1RO_W + 2312305167U, // LD1RO_W_IMM + 2312333092U, // LD1RQ_B + 2312333092U, // LD1RQ_B_IMM + 2312292904U, // LD1RQ_D + 2312292904U, // LD1RQ_D_IMM + 2312342910U, // LD1RQ_H + 2312342910U, // LD1RQ_H_IMM + 2312305175U, // LD1RQ_W + 2312305175U, // LD1RQ_W_IMM + 2312292351U, // LD1RSB_D_IMM + 2312341503U, // LD1RSB_H_IMM + 2312300543U, // LD1RSB_S_IMM + 2312293964U, // LD1RSH_D_IMM + 2312302156U, // LD1RSH_S_IMM + 2312297048U, // LD1RSW_IMM + 2312296991U, // LD1RW_D_IMM + 2312305183U, // LD1RW_IMM + 242570U, // LD1Rv16b + 42193802U, // LD1Rv16b_POST + 258954U, // LD1Rv1d + 41161610U, // LD1Rv1d_POST + 275338U, // LD1Rv2d + 41177994U, // LD1Rv2d_POST + 291722U, // LD1Rv2s + 43291530U, // LD1Rv2s_POST + 308106U, // LD1Rv4h + 44356490U, // LD1Rv4h_POST + 324490U, // LD1Rv4s + 43324298U, // LD1Rv4s_POST + 340874U, // LD1Rv8b + 42292106U, // LD1Rv8b_POST + 357258U, // LD1Rv8h + 44405642U, // LD1Rv8h_POST + 2312292288U, // LD1SB_D + 2312292288U, // LD1SB_D_IMM_REAL + 2312341440U, // LD1SB_H + 2312341440U, // LD1SB_H_IMM_REAL + 2312300480U, // LD1SB_S + 2312300480U, // LD1SB_S_IMM_REAL + 2312293914U, // LD1SH_D + 2312293914U, // LD1SH_D_IMM_REAL + 2312302106U, // LD1SH_S + 2312302106U, // LD1SH_S_IMM_REAL + 2312297007U, // LD1SW_D + 2312297007U, // LD1SW_D_IMM_REAL + 237609U, // LD1Threev16b + 45334569U, // LD1Threev16b_POST + 253993U, // LD1Threev1d + 46399529U, // LD1Threev1d_POST + 270377U, // LD1Threev2d + 45367337U, // LD1Threev2d_POST + 286761U, // LD1Threev2s + 46432297U, // LD1Threev2s_POST + 303145U, // LD1Threev4h + 46448681U, // LD1Threev4h_POST + 319529U, // LD1Threev4s + 45416489U, // LD1Threev4s_POST + 335913U, // LD1Threev8b + 46481449U, // LD1Threev8b_POST + 352297U, // LD1Threev8h + 45449257U, // LD1Threev8h_POST + 237609U, // LD1Twov16b + 39043113U, // LD1Twov16b_POST + 253993U, // LD1Twov1d + 40108073U, // LD1Twov1d_POST + 270377U, // LD1Twov2d + 39075881U, // LD1Twov2d_POST + 286761U, // LD1Twov2s + 40140841U, // LD1Twov2s_POST + 303145U, // LD1Twov4h + 40157225U, // LD1Twov4h_POST + 319529U, // LD1Twov4s + 39125033U, // LD1Twov4s_POST + 335913U, // LD1Twov8b + 40189993U, // LD1Twov8b_POST + 352297U, // LD1Twov8h + 39157801U, // LD1Twov8h_POST + 2312305004U, // LD1W + 2312296812U, // LD1W_D + 2312296812U, // LD1W_D_IMM_REAL + 2312305004U, // LD1W_IMM_REAL + 1523793244U, // LD1_MXIPXX_H_B + 1523793258U, // LD1_MXIPXX_H_D + 1523793272U, // LD1_MXIPXX_H_H + 1523793286U, // LD1_MXIPXX_H_Q + 1523793300U, // LD1_MXIPXX_H_S + 1523801436U, // LD1_MXIPXX_V_B + 1523801450U, // LD1_MXIPXX_V_D + 1523801464U, // LD1_MXIPXX_V_H + 1523801478U, // LD1_MXIPXX_V_Q + 1523801492U, // LD1_MXIPXX_V_S + 48603177U, // LD1i16 + 49659945U, // LD1i16_POST + 48619561U, // LD1i32 + 50724905U, // LD1i32_POST + 48635945U, // LD1i64 + 51789865U, // LD1i64_POST + 48652329U, // LD1i8 + 52854825U, // LD1i8_POST + 2312332294U, // LD2B + 2312332294U, // LD2B_IMM + 2312292682U, // LD2D + 2312292682U, // LD2D_IMM + 2312342436U, // LD2H + 2312342436U, // LD2H_IMM + 242576U, // LD2Rv16b + 44290960U, // LD2Rv16b_POST + 258960U, // LD2Rv1d + 40113040U, // LD2Rv1d_POST + 275344U, // LD2Rv2d + 40129424U, // LD2Rv2d_POST + 291728U, // LD2Rv2s + 41194384U, // LD2Rv2s_POST + 308112U, // LD2Rv4h + 43307920U, // LD2Rv4h_POST + 324496U, // LD2Rv4s + 41227152U, // LD2Rv4s_POST + 340880U, // LD2Rv8b + 44389264U, // LD2Rv8b_POST + 357264U, // LD2Rv8h + 43357072U, // LD2Rv8h_POST + 237707U, // LD2Twov16b + 39043211U, // LD2Twov16b_POST + 270475U, // LD2Twov2d + 39075979U, // LD2Twov2d_POST + 286859U, // LD2Twov2s + 40140939U, // LD2Twov2s_POST + 303243U, // LD2Twov4h + 40157323U, // LD2Twov4h_POST + 319627U, // LD2Twov4s + 39125131U, // LD2Twov4s_POST + 336011U, // LD2Twov8b + 40190091U, // LD2Twov8b_POST + 352395U, // LD2Twov8h + 39157899U, // LD2Twov8h_POST + 2312305056U, // LD2W + 2312305056U, // LD2W_IMM + 48603275U, // LD2i16 + 50708619U, // LD2i16_POST + 48619659U, // LD2i32 + 51773579U, // LD2i32_POST + 48636043U, // LD2i64 + 53887115U, // LD2i64_POST + 48652427U, // LD2i8 + 49709195U, // LD2i8_POST + 2312332315U, // LD3B + 2312332315U, // LD3B_IMM + 2312292694U, // LD3D + 2312292694U, // LD3D_IMM + 2312342448U, // LD3H + 2312342448U, // LD3H_IMM + 242582U, // LD3Rv16b + 54776726U, // LD3Rv16b_POST + 258966U, // LD3Rv1d + 46404502U, // LD3Rv1d_POST + 275350U, // LD3Rv2d + 46420886U, // LD3Rv2d_POST + 291734U, // LD3Rv2s + 55874454U, // LD3Rv2s_POST + 308118U, // LD3Rv4h + 56939414U, // LD3Rv4h_POST + 324502U, // LD3Rv4s + 55907222U, // LD3Rv4s_POST + 340886U, // LD3Rv8b + 54875030U, // LD3Rv8b_POST + 357270U, // LD3Rv8h + 56988566U, // LD3Rv8h_POST + 238115U, // LD3Threev16b + 45335075U, // LD3Threev16b_POST + 270883U, // LD3Threev2d + 45367843U, // LD3Threev2d_POST + 287267U, // LD3Threev2s + 46432803U, // LD3Threev2s_POST + 303651U, // LD3Threev4h + 46449187U, // LD3Threev4h_POST + 320035U, // LD3Threev4s + 45416995U, // LD3Threev4s_POST + 336419U, // LD3Threev8b + 46481955U, // LD3Threev8b_POST + 352803U, // LD3Threev8h + 45449763U, // LD3Threev8h_POST + 2312305068U, // LD3W + 2312305068U, // LD3W_IMM + 48603683U, // LD3i16 + 58049059U, // LD3i16_POST + 48620067U, // LD3i32 + 59114019U, // LD3i32_POST + 48636451U, // LD3i64 + 60178979U, // LD3i64_POST + 48652835U, // LD3i8 + 61243939U, // LD3i8_POST + 2312332341U, // LD4B + 2312332341U, // LD4B_IMM + 2312292706U, // LD4D + 2312292706U, // LD4D_IMM + 238145U, // LD4Fourv16b + 37995073U, // LD4Fourv16b_POST + 270913U, // LD4Fourv2d + 38027841U, // LD4Fourv2d_POST + 287297U, // LD4Fourv2s + 39092801U, // LD4Fourv2s_POST + 303681U, // LD4Fourv4h + 39109185U, // LD4Fourv4h_POST + 320065U, // LD4Fourv4s + 38076993U, // LD4Fourv4s_POST + 336449U, // LD4Fourv8b + 39141953U, // LD4Fourv8b_POST + 352833U, // LD4Fourv8h + 38109761U, // LD4Fourv8h_POST + 2312342460U, // LD4H + 2312342460U, // LD4H_IMM + 242588U, // LD4Rv16b + 43242396U, // LD4Rv16b_POST + 258972U, // LD4Rv1d + 39064476U, // LD4Rv1d_POST + 275356U, // LD4Rv2d + 39080860U, // LD4Rv2d_POST + 291740U, // LD4Rv2s + 40145820U, // LD4Rv2s_POST + 308124U, // LD4Rv4h + 41210780U, // LD4Rv4h_POST + 324508U, // LD4Rv4s + 40178588U, // LD4Rv4s_POST + 340892U, // LD4Rv8b + 43340700U, // LD4Rv8b_POST + 357276U, // LD4Rv8h + 41259932U, // LD4Rv8h_POST + 2312305080U, // LD4W + 2312305080U, // LD4W_IMM + 48603713U, // LD4i16 + 51757633U, // LD4i16_POST + 48620097U, // LD4i32 + 53871169U, // LD4i32_POST + 48636481U, // LD4i64 + 62276161U, // LD4i64_POST + 48652865U, // LD4i8 + 50758209U, // LD4i8_POST + 435239U, // LD64B + 1611768897U, // LDADDAB + 1611770833U, // LDADDAH + 1611769119U, // LDADDALB + 1611771007U, // LDADDALH + 1611771675U, // LDADDALW + 1611771675U, // LDADDALX + 1611768474U, // LDADDAW + 1611768474U, // LDADDAX + 1611769055U, // LDADDB + 1611770993U, // LDADDH + 1611769300U, // LDADDLB + 1611771107U, // LDADDLH + 1611771852U, // LDADDLW + 1611771852U, // LDADDLX + 1611770314U, // LDADDW + 1611770314U, // LDADDX + 419440487U, // LDAPRB + 419442113U, // LDAPRH + 419443823U, // LDAPRW + 419443823U, // LDAPRX + 419440530U, // LDAPURBi + 419442156U, // LDAPURHi + 419440670U, // LDAPURSBWi + 419440670U, // LDAPURSBXi + 419442283U, // LDAPURSHWi + 419442283U, // LDAPURSHXi + 419445367U, // LDAPURSWi + 419443904U, // LDAPURXi + 419443904U, // LDAPURi + 419440435U, // LDARB + 419442061U, // LDARH + 419443618U, // LDARW + 419443618U, // LDARX + 403714884U, // LDAXPW + 403714884U, // LDAXPX + 419440546U, // LDAXRB + 419442172U, // LDAXRH + 419443948U, // LDAXRW + 419443948U, // LDAXRX + 1611768953U, // LDCLRAB + 1611770890U, // LDCLRAH + 1611769194U, // LDCLRALB + 1611771047U, // LDCLRALH + 1611771749U, // LDCLRALW + 1611771749U, // LDCLRALX + 1611768642U, // LDCLRAW + 1611768642U, // LDCLRAX + 1611769672U, // LDCLRB + 1611771298U, // LDCLRH + 1611769402U, // LDCLRLB + 1611771143U, // LDCLRLH + 1611772058U, // LDCLRLW + 1611772058U, // LDCLRLX + 1611772946U, // LDCLRW + 1611772946U, // LDCLRX + 1611768962U, // LDEORAB + 1611770899U, // LDEORAH + 1611769204U, // LDEORALB + 1611771057U, // LDEORALH + 1611771758U, // LDEORALW + 1611771758U, // LDEORALX + 1611768650U, // LDEORAW + 1611768650U, // LDEORAX + 1611769695U, // LDEORB + 1611771321U, // LDEORH + 1611769411U, // LDEORLB + 1611771152U, // LDEORLH + 1611772066U, // LDEORLW + 1611772066U, // LDEORLX + 1611773022U, // LDEORW + 1611773022U, // LDEORX + 2312291279U, // LDFF1B_D_REAL + 2312340431U, // LDFF1B_H_REAL + 2312332239U, // LDFF1B_REAL + 2312299471U, // LDFF1B_S_REAL + 2312292644U, // LDFF1D_REAL + 2312293229U, // LDFF1H_D_REAL + 2312342381U, // LDFF1H_REAL + 2312301421U, // LDFF1H_S_REAL + 2312292295U, // LDFF1SB_D_REAL + 2312341447U, // LDFF1SB_H_REAL + 2312300487U, // LDFF1SB_S_REAL + 2312293921U, // LDFF1SH_D_REAL + 2312302113U, // LDFF1SH_S_REAL + 2312297014U, // LDFF1SW_D_REAL + 2312296818U, // LDFF1W_D_REAL + 2312305010U, // LDFF1W_REAL + 2298587950U, // LDG + 419443004U, // LDGM + 419440442U, // LDLARB + 419442068U, // LDLARH + 419443624U, // LDLARW + 419443624U, // LDLARX + 2312291287U, // LDNF1B_D_IMM_REAL + 2312340439U, // LDNF1B_H_IMM_REAL + 2312332247U, // LDNF1B_IMM_REAL + 2312299479U, // LDNF1B_S_IMM_REAL + 2312292652U, // LDNF1D_IMM_REAL + 2312293237U, // LDNF1H_D_IMM_REAL + 2312342389U, // LDNF1H_IMM_REAL + 2312301429U, // LDNF1H_S_IMM_REAL + 2312292304U, // LDNF1SB_D_IMM_REAL + 2312341456U, // LDNF1SB_H_IMM_REAL + 2312300496U, // LDNF1SB_S_IMM_REAL + 2312293930U, // LDNF1SH_D_IMM_REAL + 2312302122U, // LDNF1SH_S_IMM_REAL + 2312297023U, // LDNF1SW_D_IMM_REAL + 2312296826U, // LDNF1W_D_IMM_REAL + 2312305018U, // LDNF1W_IMM_REAL + 403714803U, // LDNPDi + 403714803U, // LDNPQi + 403714803U, // LDNPSi + 403714803U, // LDNPWi + 403714803U, // LDNPXi + 2312332255U, // LDNT1B_ZRI + 2312332255U, // LDNT1B_ZRR + 567460831U, // LDNT1B_ZZR_D_REAL + 701686751U, // LDNT1B_ZZR_S_REAL + 2312292660U, // LDNT1D_ZRI + 2312292660U, // LDNT1D_ZRR + 567462196U, // LDNT1D_ZZR_D_REAL + 2312342397U, // LDNT1H_ZRI + 2312342397U, // LDNT1H_ZRR + 567462781U, // LDNT1H_ZZR_D_REAL + 701688701U, // LDNT1H_ZZR_S_REAL + 567461849U, // LDNT1SB_ZZR_D_REAL + 701687769U, // LDNT1SB_ZZR_S_REAL + 567463475U, // LDNT1SH_ZZR_D_REAL + 701689395U, // LDNT1SH_ZZR_S_REAL + 567466568U, // LDNT1SW_ZZR_D_REAL + 2312305026U, // LDNT1W_ZRI + 2312305026U, // LDNT1W_ZRR + 567466370U, // LDNT1W_ZZR_D_REAL + 701692290U, // LDNT1W_ZZR_S_REAL + 403714707U, // LDPDi + 2282861203U, // LDPDpost + 2282861203U, // LDPDpre + 403714707U, // LDPQi + 2282861203U, // LDPQpost + 2282861203U, // LDPQpre + 403716689U, // LDPSWi + 2282863185U, // LDPSWpost + 2282863185U, // LDPSWpre + 403714707U, // LDPSi + 2282861203U, // LDPSpost + 2282861203U, // LDPSpre + 403714707U, // LDPWi + 2282861203U, // LDPWpost + 2282861203U, // LDPWpre + 403714707U, // LDPXi + 2282861203U, // LDPXpost + 2282861203U, // LDPXpre + 419439225U, // LDRAAindexed + 2298585721U, // LDRAAwriteback + 419439723U, // LDRABindexed + 2298586219U, // LDRABwriteback + 2298586946U, // LDRBBpost + 2298586946U, // LDRBBpre + 419440450U, // LDRBBroW + 419440450U, // LDRBBroX + 419440450U, // LDRBBui + 2298590176U, // LDRBpost + 2298590176U, // LDRBpre + 419443680U, // LDRBroW + 419443680U, // LDRBroX + 419443680U, // LDRBui + 2685416416U, // LDRDl + 2298590176U, // LDRDpost + 2298590176U, // LDRDpre + 419443680U, // LDRDroW + 419443680U, // LDRDroX + 419443680U, // LDRDui + 2298588572U, // LDRHHpost + 2298588572U, // LDRHHpre + 419442076U, // LDRHHroW + 419442076U, // LDRHHroX + 419442076U, // LDRHHui + 2298590176U, // LDRHpost + 2298590176U, // LDRHpre + 419443680U, // LDRHroW + 419443680U, // LDRHroX + 419443680U, // LDRHui + 2685416416U, // LDRQl + 2298590176U, // LDRQpost + 2298590176U, // LDRQpre + 419443680U, // LDRQroW + 419443680U, // LDRQroX + 419443680U, // LDRQui + 2298587143U, // LDRSBWpost + 2298587143U, // LDRSBWpre + 419440647U, // LDRSBWroW + 419440647U, // LDRSBWroX + 419440647U, // LDRSBWui + 2298587143U, // LDRSBXpost + 2298587143U, // LDRSBXpre + 419440647U, // LDRSBXroW + 419440647U, // LDRSBXroX + 419440647U, // LDRSBXui + 2298588756U, // LDRSHWpost + 2298588756U, // LDRSHWpre + 419442260U, // LDRSHWroW + 419442260U, // LDRSHWroX + 419442260U, // LDRSHWui + 2298588756U, // LDRSHXpost + 2298588756U, // LDRSHXpre + 419442260U, // LDRSHXroW + 419442260U, // LDRSHXroX + 419442260U, // LDRSHXui + 2685418080U, // LDRSWl + 2298591840U, // LDRSWpost + 2298591840U, // LDRSWpre + 419445344U, // LDRSWroW + 419445344U, // LDRSWroX + 419445344U, // LDRSWui + 2685416416U, // LDRSl + 2298590176U, // LDRSpost + 2298590176U, // LDRSpre + 419443680U, // LDRSroW + 419443680U, // LDRSroX + 419443680U, // LDRSui + 2685416416U, // LDRWl + 2298590176U, // LDRWpost + 2298590176U, // LDRWpre + 419443680U, // LDRWroW + 419443680U, // LDRWroX + 419443680U, // LDRWui + 2685416416U, // LDRXl + 2298590176U, // LDRXpost + 2298590176U, // LDRXpre + 419443680U, // LDRXroW + 419443680U, // LDRXroX + 419443680U, // LDRXui + 419877856U, // LDR_PXI + 455648U, // LDR_ZA + 419877856U, // LDR_ZXI + 1611768978U, // LDSETAB + 1611770915U, // LDSETAH + 1611769222U, // LDSETALB + 1611771075U, // LDSETALH + 1611771774U, // LDSETALW + 1611771774U, // LDSETALX + 1611768690U, // LDSETAW + 1611768690U, // LDSETAX + 1611769901U, // LDSETB + 1611771509U, // LDSETH + 1611769461U, // LDSETLB + 1611771168U, // LDSETLH + 1611772122U, // LDSETLW + 1611772122U, // LDSETLX + 1611773557U, // LDSETW + 1611773557U, // LDSETX + 1611768987U, // LDSMAXAB + 1611770924U, // LDSMAXAH + 1611769232U, // LDSMAXALB + 1611771085U, // LDSMAXALH + 1611771783U, // LDSMAXALW + 1611771783U, // LDSMAXALX + 1611768727U, // LDSMAXAW + 1611768727U, // LDSMAXAX + 1611770038U, // LDSMAXB + 1611771541U, // LDSMAXH + 1611769470U, // LDSMAXLB + 1611771210U, // LDSMAXLH + 1611772177U, // LDSMAXLW + 1611772177U, // LDSMAXLX + 1611774657U, // LDSMAXW + 1611774657U, // LDSMAXX + 1611768906U, // LDSMINAB + 1611770863U, // LDSMINAH + 1611769164U, // LDSMINALB + 1611771017U, // LDSMINALH + 1611771714U, // LDSMINALW + 1611771714U, // LDSMINALX + 1611768573U, // LDSMINAW + 1611768573U, // LDSMINAX + 1611769513U, // LDSMINB + 1611771230U, // LDSMINH + 1611769375U, // LDSMINLB + 1611771116U, // LDSMINLH + 1611772020U, // LDSMINLW + 1611772020U, // LDSMINLX + 1611772312U, // LDSMINW + 1611772312U, // LDSMINX + 419440495U, // LDTRBi + 419442121U, // LDTRHi + 419440654U, // LDTRSBWi + 419440654U, // LDTRSBXi + 419442267U, // LDTRSHWi + 419442267U, // LDTRSHXi + 419445351U, // LDTRSWi + 419443868U, // LDTRWi + 419443868U, // LDTRXi + 1611768997U, // LDUMAXAB + 1611770934U, // LDUMAXAH + 1611769243U, // LDUMAXALB + 1611771096U, // LDUMAXALH + 1611771793U, // LDUMAXALW + 1611771793U, // LDUMAXALX + 1611768736U, // LDUMAXAW + 1611768736U, // LDUMAXAX + 1611770047U, // LDUMAXB + 1611771550U, // LDUMAXH + 1611769480U, // LDUMAXLB + 1611771220U, // LDUMAXLH + 1611772186U, // LDUMAXLW + 1611772186U, // LDUMAXLX + 1611774665U, // LDUMAXW + 1611774665U, // LDUMAXX + 1611768916U, // LDUMINAB + 1611770873U, // LDUMINAH + 1611769175U, // LDUMINALB + 1611771028U, // LDUMINALH + 1611771724U, // LDUMINALW + 1611771724U, // LDUMINALX + 1611768582U, // LDUMINAW + 1611768582U, // LDUMINAX + 1611769522U, // LDUMINB + 1611771239U, // LDUMINH + 1611769385U, // LDUMINLB + 1611771126U, // LDUMINLH + 1611772029U, // LDUMINLW + 1611772029U, // LDUMINLX + 1611772320U, // LDUMINW + 1611772320U, // LDUMINX + 419440515U, // LDURBBi + 419443891U, // LDURBi + 419443891U, // LDURDi + 419442141U, // LDURHHi + 419443891U, // LDURHi + 419443891U, // LDURQi + 419440662U, // LDURSBWi + 419440662U, // LDURSBXi + 419442275U, // LDURSHWi + 419442275U, // LDURSHXi + 419445359U, // LDURSWi + 419443891U, // LDURSi + 419443891U, // LDURWi + 419443891U, // LDURXi + 403714912U, // LDXPW + 403714912U, // LDXPX + 419440554U, // LDXRB + 419442180U, // LDXRH + 419443955U, // LDXRW + 419443955U, // LDXRX + 1611682898U, // LSLR_ZPmZ_B + 1611691090U, // LSLR_ZPmZ_D + 1759548498U, // LSLR_ZPmZ_H + 1611707474U, // LSLR_ZPmZ_S + 403714234U, // LSLVWr + 403714234U, // LSLVXr + 1611681978U, // LSL_WIDE_ZPmZ_B + 1759547578U, // LSL_WIDE_ZPmZ_H + 1611706554U, // LSL_WIDE_ZPmZ_S + 1880117434U, // LSL_WIDE_ZZZ_B + 1089507514U, // LSL_WIDE_ZZZ_H + 2014359738U, // LSL_WIDE_ZZZ_S + 1611681978U, // LSL_ZPmI_B + 1611690170U, // LSL_ZPmI_D + 1759547578U, // LSL_ZPmI_H + 1611706554U, // LSL_ZPmI_S + 1611681978U, // LSL_ZPmZ_B + 1611690170U, // LSL_ZPmZ_D + 1759547578U, // LSL_ZPmZ_H + 1611706554U, // LSL_ZPmZ_S + 1880117434U, // LSL_ZZI_B + 1209036986U, // LSL_ZZI_D + 1089507514U, // LSL_ZZI_H + 2014359738U, // LSL_ZZI_S + 1611682945U, // LSRR_ZPmZ_B + 1611691137U, // LSRR_ZPmZ_D + 1759548545U, // LSRR_ZPmZ_H + 1611707521U, // LSRR_ZPmZ_S + 403715212U, // LSRVWr + 403715212U, // LSRVXr + 1611682956U, // LSR_WIDE_ZPmZ_B + 1759548556U, // LSR_WIDE_ZPmZ_H + 1611707532U, // LSR_WIDE_ZPmZ_S + 1880118412U, // LSR_WIDE_ZZZ_B + 1089508492U, // LSR_WIDE_ZZZ_H + 2014360716U, // LSR_WIDE_ZZZ_S + 1611682956U, // LSR_ZPmI_B + 1611691148U, // LSR_ZPmI_D + 1759548556U, // LSR_ZPmI_H + 1611707532U, // LSR_ZPmI_S + 1611682956U, // LSR_ZPmZ_B + 1611691148U, // LSR_ZPmZ_D + 1759548556U, // LSR_ZPmZ_H + 1611707532U, // LSR_ZPmZ_S + 1880118412U, // LSR_ZZI_B + 1209037964U, // LSR_ZZI_D + 1089508492U, // LSR_ZZI_H + 2014360716U, // LSR_ZZI_S + 403712502U, // MADDWrrr + 403712502U, // MADDXrrr + 1611680111U, // MAD_ZPmZZ_B + 1611688303U, // MAD_ZPmZZ_D + 1759545711U, // MAD_ZPmZZ_H + 1611704687U, // MAD_ZPmZZ_S + 1611680874U, // MATCH_PPzZZ_B + 2967506026U, // MATCH_PPzZZ_H + 1611678420U, // MLA_ZPmZZ_B + 1611686612U, // MLA_ZPmZZ_D + 1759544020U, // MLA_ZPmZZ_H + 1611702996U, // MLA_ZPmZZ_S + 537944788U, // MLA_ZZZI_D + 1092649684U, // MLA_ZZZI_H + 672178900U, // MLA_ZZZI_S + 1479606996U, // MLAv16i8 + 1480655572U, // MLAv2i32 + 1480655572U, // MLAv2i32_indexed + 1482752724U, // MLAv4i16 + 1482752724U, // MLAv4i16_indexed + 1483801300U, // MLAv4i32 + 1483801300U, // MLAv4i32_indexed + 1484849876U, // MLAv8i16 + 1484849876U, // MLAv8i16_indexed + 1485898452U, // MLAv8i8 + 1611683216U, // MLS_ZPmZZ_B + 1611691408U, // MLS_ZPmZZ_D + 1759548816U, // MLS_ZPmZZ_H + 1611707792U, // MLS_ZPmZZ_S + 537949584U, // MLS_ZZZI_D + 1092654480U, // MLS_ZZZI_H + 672183696U, // MLS_ZZZI_S + 1479611792U, // MLSv16i8 + 1480660368U, // MLSv2i32 + 1480660368U, // MLSv2i32_indexed + 1482757520U, // MLSv4i16 + 1482757520U, // MLSv4i16_indexed + 1483806096U, // MLSv4i32 + 1483806096U, // MLSv4i32_indexed + 1484854672U, // MLSv8i16 + 1484854672U, // MLSv8i16_indexed + 1485903248U, // MLSv8i8 + 1745891068U, // MOVID + 1882246908U, // MOVIv16b_ns + 1750126332U, // MOVIv2d_ns + 1883295484U, // MOVIv2i32 + 1883295484U, // MOVIv2s_msl + 1885392636U, // MOVIv4i16 + 1886441212U, // MOVIv4i32 + 1886441212U, // MOVIv4s_msl + 1888538364U, // MOVIv8b_ns + 1887489788U, // MOVIv8i16 + 2551197447U, // MOVKWi + 2551197447U, // MOVKXi + 1880109593U, // MOVNWi + 1880109593U, // MOVNXi + 1071853U, // MOVPRFX_ZPmZ_B + 1080045U, // MOVPRFX_ZPmZ_D + 136354541U, // MOVPRFX_ZPmZ_H + 1096429U, // MOVPRFX_ZPmZ_S + 1611684589U, // MOVPRFX_ZPzZ_B + 1611692781U, // MOVPRFX_ZPzZ_D + 2967509741U, // MOVPRFX_ZPzZ_H + 1611709165U, // MOVPRFX_ZPzZ_S + 1612110573U, // MOVPRFX_ZZ + 1880111992U, // MOVZWi + 1880111992U, // MOVZXi + 2014328316U, // MRS + 1611679731U, // MSB_ZPmZZ_B + 1611687923U, // MSB_ZPmZZ_D + 1759545331U, // MSB_ZPmZZ_H + 1611704307U, // MSB_ZPmZZ_S + 464017U, // MSR + 472209U, // MSRpstateImm1 + 472209U, // MSRpstateImm4 + 480401U, // MSRpstatesvcrImm1 + 403712116U, // MSUBWrrr + 403712116U, // MSUBXrrr + 1880117482U, // MUL_ZI_B + 1209037034U, // MUL_ZI_D + 1089507562U, // MUL_ZI_H + 2014359786U, // MUL_ZI_S + 1611682026U, // MUL_ZPmZ_B + 1611690218U, // MUL_ZPmZ_D + 1759547626U, // MUL_ZPmZ_H + 1611706602U, // MUL_ZPmZ_S + 1209037034U, // MUL_ZZZI_D + 1089507562U, // MUL_ZZZI_H + 2014359786U, // MUL_ZZZI_S + 1880117482U, // MUL_ZZZ_B + 1209037034U, // MUL_ZZZ_D + 1089507562U, // MUL_ZZZ_H + 2014359786U, // MUL_ZZZ_S + 271634666U, // MULv16i8 + 272683242U, // MULv2i32 + 272683242U, // MULv2i32_indexed + 274780394U, // MULv4i16 + 274780394U, // MULv4i16_indexed + 275828970U, // MULv4i32 + 275828970U, // MULv4i32_indexed + 276877546U, // MULv8i16 + 276877546U, // MULv8i16_indexed + 277926122U, // MULv8i8 + 1883295465U, // MVNIv2i32 + 1883295465U, // MVNIv2s_msl + 1885392617U, // MVNIv4i16 + 1886441193U, // MVNIv4i32 + 1886441193U, // MVNIv4s_msl + 1887489769U, // MVNIv8i16 + 1611683164U, // NANDS_PPzPP + 1611680282U, // NAND_PPzPP + 1209036976U, // NBSL_ZZZZ + 1067828U, // NEG_ZPmZ_B + 1076020U, // NEG_ZPmZ_D + 136350516U, // NEG_ZPmZ_H + 1092404U, // NEG_ZPmZ_S + 271633204U, // NEGv16i8 + 403712820U, // NEGv1i64 + 272681780U, // NEGv2i32 + 273730356U, // NEGv2i64 + 274778932U, // NEGv4i16 + 275827508U, // NEGv4i32 + 276876084U, // NEGv8i16 + 277924660U, // NEGv8i8 + 1611680873U, // NMATCH_PPzZZ_B + 2967506025U, // NMATCH_PPzZZ_H + 1611683335U, // NORS_PPzPP + 1611682917U, // NOR_PPzPP + 1071154U, // NOT_ZPmZ_B + 1079346U, // NOT_ZPmZ_D + 136353842U, // NOT_ZPmZ_H + 1095730U, // NOT_ZPmZ_S + 271636530U, // NOTv16i8 + 277927986U, // NOTv8i8 + 1611683255U, // ORNS_PPzPP + 403714523U, // ORNWrs + 403714523U, // ORNXrs + 1611682267U, // ORN_PPzPP + 271634907U, // ORNv16i8 + 277926363U, // ORNv8i8 + 1611683341U, // ORRS_PPzPP + 403715190U, // ORRWri + 403715190U, // ORRWrs + 403715190U, // ORRXri + 403715190U, // ORRXrs + 1611682934U, // ORR_PPzPP + 1209037942U, // ORR_ZI + 1611682934U, // ORR_ZPmZ_B + 1611691126U, // ORR_ZPmZ_D + 1759548534U, // ORR_ZPmZ_H + 1611707510U, // ORR_ZPmZ_S + 1209037942U, // ORR_ZZZ + 271635574U, // ORRv16i8 + 2554401910U, // ORRv2i32 + 2556499062U, // ORRv4i16 + 2557547638U, // ORRv4i32 + 2558596214U, // ORRv8i16 + 277927030U, // ORRv8i8 + 80210U, // ORV_VPZ_B + 823220562U, // ORV_VPZ_D + 824277330U, // ORV_VPZ_H + 819042642U, // ORV_VPZ_S + 2282857107U, // PACDA + 2282857688U, // PACDB + 107433U, // PACDZA + 108744U, // PACDZB + 403710640U, // PACGA + 2282857150U, // PACIA + 7292U, // PACIA1716 + 7257U, // PACIASP + 7248U, // PACIAZ + 2282857723U, // PACIB + 7203U, // PACIB1716 + 7283U, // PACIBSP + 7266U, // PACIBZ + 107449U, // PACIZA + 108760U, // PACIZB + 19158U, // PFALSE + 1611683924U, // PFIRST_B + 2014340615U, // PMULLB_ZZZ_D + 1136690695U, // PMULLB_ZZZ_H + 64136711U, // PMULLB_ZZZ_Q + 2014345023U, // PMULLT_ZZZ_D + 1136695103U, // PMULLT_ZZZ_H + 64141119U, // PMULLT_ZZZ_Q + 276873504U, // PMULLv16i8 + 2212548703U, // PMULLv1i64 + 2346762528U, // PMULLv2i64 + 276877407U, // PMULLv8i8 + 1880117494U, // PMUL_ZZZ_B + 271634678U, // PMULv16i8 + 277926134U, // PMULv8i8 + 1611683984U, // PNEXT_B + 1611692176U, // PNEXT_D + 1088460944U, // PNEXT_H + 1611708560U, // PNEXT_S + 1092052206U, // PRFB_D_PZI + 1107780846U, // PRFB_D_SCALED + 1107780846U, // PRFB_D_SXTW_SCALED + 1107780846U, // PRFB_D_UXTW_SCALED + 1107780846U, // PRFB_PRI + 1107780846U, // PRFB_PRR + 1087857902U, // PRFB_S_PZI + 1107780846U, // PRFB_S_SXTW_SCALED + 1107780846U, // PRFB_S_UXTW_SCALED + 1092053524U, // PRFD_D_PZI + 1107782164U, // PRFD_D_SCALED + 1107782164U, // PRFD_D_SXTW_SCALED + 1107782164U, // PRFD_D_UXTW_SCALED + 1107782164U, // PRFD_PRI + 1107782164U, // PRFD_PRR + 1087859220U, // PRFD_S_PZI + 1107782164U, // PRFD_S_SXTW_SCALED + 1107782164U, // PRFD_S_UXTW_SCALED + 1092054137U, // PRFH_D_PZI + 1107782777U, // PRFH_D_SCALED + 1107782777U, // PRFH_D_SXTW_SCALED + 1107782777U, // PRFH_D_UXTW_SCALED + 1107782777U, // PRFH_PRI + 1107782777U, // PRFH_PRR + 1087859833U, // PRFH_S_PZI + 1107782777U, // PRFH_S_SXTW_SCALED + 1107782777U, // PRFH_S_UXTW_SCALED + 2685899062U, // PRFMl + 419926326U, // PRFMroW + 419926326U, // PRFMroX + 419926326U, // PRFMui + 1107786249U, // PRFS_PRR + 419926381U, // PRFUMi + 1092057609U, // PRFW_D_PZI + 1107786249U, // PRFW_D_SCALED + 1107786249U, // PRFW_D_SXTW_SCALED + 1107786249U, // PRFW_D_UXTW_SCALED + 1107786249U, // PRFW_PRI + 1087863305U, // PRFW_S_PZI + 1107786249U, // PRFW_S_SXTW_SCALED + 1107786249U, // PRFW_S_UXTW_SCALED + 1612107778U, // PSEL_PPPRI_B + 1612107778U, // PSEL_PPPRI_D + 1612107778U, // PSEL_PPPRI_H + 1612107778U, // PSEL_PPPRI_S + 1880545350U, // PTEST_PP + 3088078179U, // PTRUES_B + 3088086371U, // PTRUES_D + 66098531U, // PTRUES_H + 3088102755U, // PTRUES_S + 3088075504U, // PTRUE_B + 3088083696U, // PTRUE_D + 66095856U, // PTRUE_H + 3088100080U, // PTRUE_S + 868257463U, // PUNPKHI_PP + 868258352U, // PUNPKLO_PP + 940590752U, // RADDHNB_ZZZ_B + 1086359200U, // RADDHNB_ZZZ_H + 1209050784U, // RADDHNB_ZZZ_S + 1343248289U, // RADDHNT_ZZZ_B + 1087412129U, // RADDHNT_ZZZ_H + 537966497U, // RADDHNT_ZZZ_S + 272683402U, // RADDHNv2i64_v2i32 + 1483800939U, // RADDHNv2i64_v4i32 + 274780554U, // RADDHNv4i32_v4i16 + 1484849515U, // RADDHNv4i32_v8i16 + 1479606635U, // RADDHNv8i16_v16i8 + 277926282U, // RADDHNv8i16_v8i8 + 273727614U, // RAX1 + 1209032830U, // RAX1_ZZZ_D + 403715738U, // RBITWr + 403715738U, // RBITXr + 1070746U, // RBIT_ZPmZ_B + 1078938U, // RBIT_ZPmZ_D + 136353434U, // RBIT_ZPmZ_H + 1095322U, // RBIT_ZPmZ_S + 271636122U, // RBITv16i8 + 277927578U, // RBITv8i8 + 1611683316U, // RDFFRS_PPz + 1611682789U, // RDFFR_PPz_REAL + 21477U, // RDFFR_P_REAL + 403714315U, // RDVLI_XI + 13936U, // RET + 7424U, // RETAA + 7431U, // RETAB + 403710547U, // REV16Wr + 403710547U, // REV16Xr + 271630931U, // REV16v16i8 + 277922387U, // REV16v8i8 + 403710084U, // REV32Xr + 271630468U, // REV32v16i8 + 274776196U, // REV32v4i16 + 276873348U, // REV32v8i16 + 277921924U, // REV32v8i8 + 271630906U, // REV64v16i8 + 272679482U, // REV64v2i32 + 274776634U, // REV64v4i16 + 275825210U, // REV64v4i32 + 276873786U, // REV64v8i16 + 277922362U, // REV64v8i8 + 1075344U, // REVB_ZPmZ_D + 136349840U, // REVB_ZPmZ_H + 1091728U, // REVB_ZPmZ_S + 2418190921U, // REVD_ZPmZ + 1076879U, // REVH_ZPmZ_D + 1093263U, // REVH_ZPmZ_S + 1079955U, // REVW_ZPmZ_D + 403716330U, // REVWr + 403716330U, // REVXr + 1880119530U, // REV_PP_B + 1209039082U, // REV_PP_D + 821074154U, // REV_PP_H + 2014361834U, // REV_PP_S + 1880119530U, // REV_ZZ_B + 1209039082U, // REV_ZZ_D + 821074154U, // REV_ZZ_H + 2014361834U, // REV_ZZ_S + 403712769U, // RMIF + 403715178U, // RORVWr + 403715178U, // RORVXr + 940590799U, // RSHRNB_ZZI_B + 1086359247U, // RSHRNB_ZZI_H + 1209050831U, // RSHRNB_ZZI_S + 1343248324U, // RSHRNT_ZZI_B + 1087412164U, // RSHRNT_ZZI_H + 537966532U, // RSHRNT_ZZI_S + 1479606664U, // RSHRNv16i8_shift + 272683467U, // RSHRNv2i32_shift + 274780619U, // RSHRNv4i16_shift + 1483800968U, // RSHRNv4i32_shift + 1484849544U, // RSHRNv8i16_shift + 277926347U, // RSHRNv8i8_shift + 940590743U, // RSUBHNB_ZZZ_B + 1086359191U, // RSUBHNB_ZZZ_H + 1209050775U, // RSUBHNB_ZZZ_S + 1343248280U, // RSUBHNT_ZZZ_B + 1087412120U, // RSUBHNT_ZZZ_H + 537966488U, // RSUBHNT_ZZZ_S + 272683394U, // RSUBHNv2i64_v2i32 + 1483800930U, // RSUBHNv2i64_v4i32 + 274780546U, // RSUBHNv4i32_v4i16 + 1484849506U, // RSUBHNv4i32_v8i16 + 1479606626U, // RSUBHNv8i16_v16i8 + 277926274U, // RSUBHNv8i16_v8i8 + 672163087U, // SABALB_ZZZ_D + 1140884751U, // SABALB_ZZZ_H + 1343268111U, // SABALB_ZZZ_S + 672167590U, // SABALT_ZZZ_D + 1140889254U, // SABALT_ZZZ_H + 1343272614U, // SABALT_ZZZ_S + 1484849316U, // SABALv16i8_v8i16 + 1481707277U, // SABALv2i32_v2i64 + 1483804429U, // SABALv4i16_v4i32 + 1481703588U, // SABALv4i32_v2i64 + 1483800740U, // SABALv8i16_v4i32 + 1484853005U, // SABALv8i8_v8i16 + 2819637895U, // SABA_ZZZ_B + 537944711U, // SABA_ZZZ_D + 1092649607U, // SABA_ZZZ_H + 672178823U, // SABA_ZZZ_S + 1479606919U, // SABAv16i8 + 1480655495U, // SABAv2i32 + 1482752647U, // SABAv4i16 + 1483801223U, // SABAv4i32 + 1484849799U, // SABAv8i16 + 1485898375U, // SABAv8i8 + 2014340548U, // SABDLB_ZZZ_D + 1136690628U, // SABDLB_ZZZ_H + 940615108U, // SABDLB_ZZZ_S + 2014344951U, // SABDLT_ZZZ_D + 1136695031U, // SABDLT_ZZZ_H + 940619511U, // SABDLT_ZZZ_S + 276873446U, // SABDLv16i8_v8i16 + 273731518U, // SABDLv2i32_v2i64 + 275828670U, // SABDLv4i16_v4i32 + 273727718U, // SABDLv4i32_v2i64 + 275824870U, // SABDLv8i16_v4i32 + 276877246U, // SABDLv8i8_v8i16 + 1611680136U, // SABD_ZPmZ_B + 1611688328U, // SABD_ZPmZ_D + 1759545736U, // SABD_ZPmZ_H + 1611704712U, // SABD_ZPmZ_S + 271632776U, // SABDv16i8 + 272681352U, // SABDv2i32 + 274778504U, // SABDv4i16 + 275827080U, // SABDv4i32 + 276875656U, // SABDv8i16 + 277924232U, // SABDv8i8 + 1611690660U, // SADALP_ZPmZ_D + 1759548068U, // SADALP_ZPmZ_H + 1611707044U, // SADALP_ZPmZ_S + 1484853924U, // SADALPv16i8_v8i16 + 1544622756U, // SADALPv2i32_v1i64 + 1480659620U, // SADALPv4i16_v2i32 + 1481708196U, // SADALPv4i32_v2i64 + 1483805348U, // SADALPv8i16_v4i32 + 1482756772U, // SADALPv8i8_v4i16 + 2014344774U, // SADDLBT_ZZZ_D + 1136694854U, // SADDLBT_ZZZ_H + 940619334U, // SADDLBT_ZZZ_S + 2014340573U, // SADDLB_ZZZ_D + 1136690653U, // SADDLB_ZZZ_H + 940615133U, // SADDLB_ZZZ_S + 276878004U, // SADDLPv16i8_v8i16 + 336646836U, // SADDLPv2i32_v1i64 + 272683700U, // SADDLPv4i16_v2i32 + 273732276U, // SADDLPv4i32_v2i64 + 275829428U, // SADDLPv8i16_v4i32 + 274780852U, // SADDLPv8i8_v4i16 + 2014344967U, // SADDLT_ZZZ_D + 1136695047U, // SADDLT_ZZZ_H + 940619527U, // SADDLT_ZZZ_S + 269498625U, // SADDLVv16i8v + 269498625U, // SADDLVv4i16v + 269498625U, // SADDLVv4i32v + 269498625U, // SADDLVv8i16v + 269498625U, // SADDLVv8i8v + 276873462U, // SADDLv16i8_v8i16 + 273731556U, // SADDLv2i32_v2i64 + 275828708U, // SADDLv4i16_v4i32 + 273727734U, // SADDLv4i32_v2i64 + 275824886U, // SADDLv8i16_v4i32 + 276877284U, // SADDLv8i8_v8i16 + 872503510U, // SADDV_VPZ_B + 824269014U, // SADDV_VPZ_H + 819026134U, // SADDV_VPZ_S + 1209034918U, // SADDWB_ZZZ_D + 1089505446U, // SADDWB_ZZZ_H + 2014357670U, // SADDWB_ZZZ_S + 1209038970U, // SADDWT_ZZZ_D + 1089509498U, // SADDWT_ZZZ_H + 2014361722U, // SADDWT_ZZZ_S + 276873736U, // SADDWv16i8_v8i16 + 273734139U, // SADDWv2i32_v2i64 + 275831291U, // SADDWv4i16_v4i32 + 273728008U, // SADDWv4i32_v2i64 + 275825160U, // SADDWv8i16_v4i32 + 276879867U, // SADDWv8i8_v8i16 + 7437U, // SB + 537945526U, // SBCLB_ZZZ_D + 672179638U, // SBCLB_ZZZ_S + 537949929U, // SBCLT_ZZZ_D + 672184041U, // SBCLT_ZZZ_S + 403715396U, // SBCSWr + 403715396U, // SBCSXr + 403712239U, // SBCWr + 403712239U, // SBCXr + 403714346U, // SBFMWri + 403714346U, // SBFMXri + 1880117956U, // SCLAMP_ZZZ_B + 1209037508U, // SCLAMP_ZZZ_D + 1089508036U, // SCLAMP_ZZZ_H + 2014360260U, // SCLAMP_ZZZ_S + 403712775U, // SCVTFSWDri + 403712775U, // SCVTFSWHri + 403712775U, // SCVTFSWSri + 403712775U, // SCVTFSXDri + 403712775U, // SCVTFSXHri + 403712775U, // SCVTFSXSri + 403712775U, // SCVTFUWDri + 403712775U, // SCVTFUWHri + 403712775U, // SCVTFUWSri + 403712775U, // SCVTFUXDri + 403712775U, // SCVTFUXHri + 403712775U, // SCVTFUXSri + 1075975U, // SCVTF_ZPmZ_DtoD + 270568199U, // SCVTF_ZPmZ_DtoH + 1092359U, // SCVTF_ZPmZ_DtoS + 136350471U, // SCVTF_ZPmZ_HtoH + 1075975U, // SCVTF_ZPmZ_StoD + 2418051847U, // SCVTF_ZPmZ_StoH + 1092359U, // SCVTF_ZPmZ_StoS + 403712775U, // SCVTFd + 403712775U, // SCVTFh + 403712775U, // SCVTFs + 403712775U, // SCVTFv1i16 + 403712775U, // SCVTFv1i32 + 403712775U, // SCVTFv1i64 + 272681735U, // SCVTFv2f32 + 273730311U, // SCVTFv2f64 + 272681735U, // SCVTFv2i32_shift + 273730311U, // SCVTFv2i64_shift + 274778887U, // SCVTFv4f16 + 275827463U, // SCVTFv4f32 + 274778887U, // SCVTFv4i16_shift + 275827463U, // SCVTFv4i32_shift + 276876039U, // SCVTFv8f16 + 276876039U, // SCVTFv8i16_shift + 1611691221U, // SDIVR_ZPmZ_D + 1611707605U, // SDIVR_ZPmZ_S + 403716341U, // SDIVWr + 403716341U, // SDIVXr + 1611692277U, // SDIV_ZPmZ_D + 1611708661U, // SDIV_ZPmZ_S + 1343256612U, // SDOT_ZZZI_D + 2819668004U, // SDOT_ZZZI_S + 1343256612U, // SDOT_ZZZ_D + 2819668004U, // SDOT_ZZZ_S + 1483806756U, // SDOTlanev16i8 + 1480661028U, // SDOTlanev8i8 + 1483806756U, // SDOTv16i8 + 1480661028U, // SDOTv8i8 + 1611681789U, // SEL_PPPP + 1611681789U, // SEL_ZPZZ_B + 1611689981U, // SEL_ZPZZ_D + 1088458749U, // SEL_ZPZZ_H + 1611706365U, // SEL_ZPZZ_S + 8779U, // SETF16 + 8794U, // SETF8 + 7485U, // SETFFR + 2282858728U, // SHA1Crrr + 403712864U, // SHA1Hrr + 2282860835U, // SHA1Mrrr + 2282861151U, // SHA1Prrr + 1483800577U, // SHA1SU0rrr + 1483800660U, // SHA1SU1rr + 2282856602U, // SHA256H2rrr + 2282859464U, // SHA256Hrrr + 1483800597U, // SHA256SU0rr + 1483800680U, // SHA256SU1rrr + 2282859411U, // SHA512H + 2282856592U, // SHA512H2 + 1481703434U, // SHA512SU0 + 1481703517U, // SHA512SU1 + 1611680231U, // SHADD_ZPmZ_B + 1611688423U, // SHADD_ZPmZ_D + 1759545831U, // SHADD_ZPmZ_H + 1611704807U, // SHADD_ZPmZ_S + 271632871U, // SHADDv16i8 + 272681447U, // SHADDv2i32 + 274778599U, // SHADDv4i16 + 275827175U, // SHADDv4i32 + 276875751U, // SHADDv8i16 + 277924327U, // SHADDv8i8 + 276873479U, // SHLLv16i8 + 273731657U, // SHLLv2i32 + 275828809U, // SHLLv4i16 + 273727751U, // SHLLv4i32 + 275824903U, // SHLLv8i16 + 276877385U, // SHLLv8i8 + 403714066U, // SHLd + 271634450U, // SHLv16i8_shift + 272683026U, // SHLv2i32_shift + 273731602U, // SHLv2i64_shift + 274780178U, // SHLv4i16_shift + 275828754U, // SHLv4i32_shift + 276877330U, // SHLv8i16_shift + 277925906U, // SHLv8i8_shift + 940590781U, // SHRNB_ZZI_B + 1086359229U, // SHRNB_ZZI_H + 1209050813U, // SHRNB_ZZI_S + 1343248306U, // SHRNT_ZZI_B + 1087412146U, // SHRNT_ZZI_H + 537966514U, // SHRNT_ZZI_S + 1479606646U, // SHRNv16i8_shift + 272683451U, // SHRNv2i32_shift + 274780603U, // SHRNv4i16_shift + 1483800950U, // SHRNv4i32_shift + 1484849526U, // SHRNv8i16_shift + 277926331U, // SHRNv8i8_shift + 1611682747U, // SHSUBR_ZPmZ_B + 1611690939U, // SHSUBR_ZPmZ_D + 1759548347U, // SHSUBR_ZPmZ_H + 1611707323U, // SHSUBR_ZPmZ_S + 1611679845U, // SHSUB_ZPmZ_B + 1611688037U, // SHSUB_ZPmZ_D + 1759545445U, // SHSUB_ZPmZ_H + 1611704421U, // SHSUB_ZPmZ_S + 271632485U, // SHSUBv16i8 + 272681061U, // SHSUBv2i32 + 274778213U, // SHSUBv4i16 + 275826789U, // SHSUBv4i32 + 276875365U, // SHSUBv8i16 + 277923941U, // SHSUBv8i8 + 2819641055U, // SLI_ZZI_B + 537947871U, // SLI_ZZI_D + 1092652767U, // SLI_ZZI_H + 672181983U, // SLI_ZZI_S + 2282860255U, // SLId + 1479610079U, // SLIv16i8_shift + 1480658655U, // SLIv2i32_shift + 1481707231U, // SLIv2i64_shift + 1482755807U, // SLIv4i16_shift + 1483804383U, // SLIv4i32_shift + 1484852959U, // SLIv8i16_shift + 1485901535U, // SLIv8i8_shift + 1483800691U, // SM3PARTW1 + 1483801112U, // SM3PARTW2 + 275824711U, // SM3SS1 + 1483801185U, // SM3TT1A + 1483801589U, // SM3TT1B + 1483801194U, // SM3TT2A + 1483801618U, // SM3TT2B + 1483803215U, // SM4E + 2014362388U, // SM4EKEY_ZZZ_S + 275831572U, // SM4ENCKEY + 2014358095U, // SM4E_ZZZ_S + 403714004U, // SMADDLrrr + 1611682642U, // SMAXP_ZPmZ_B + 1611690834U, // SMAXP_ZPmZ_D + 1759548242U, // SMAXP_ZPmZ_H + 1611707218U, // SMAXP_ZPmZ_S + 271635282U, // SMAXPv16i8 + 272683858U, // SMAXPv2i32 + 274781010U, // SMAXPv4i16 + 275829586U, // SMAXPv4i32 + 276878162U, // SMAXPv8i16 + 277926738U, // SMAXPv8i8 + 80222U, // SMAXV_VPZ_B + 823220574U, // SMAXV_VPZ_D + 824277342U, // SMAXV_VPZ_H + 819042654U, // SMAXV_VPZ_S + 269498718U, // SMAXVv16i8v + 269498718U, // SMAXVv4i16v + 269498718U, // SMAXVv4i32v + 269498718U, // SMAXVv8i16v + 269498718U, // SMAXVv8i8v + 1880120003U, // SMAX_ZI_B + 1209039555U, // SMAX_ZI_D + 1089510083U, // SMAX_ZI_H + 2014362307U, // SMAX_ZI_S + 1611684547U, // SMAX_ZPmZ_B + 1611692739U, // SMAX_ZPmZ_D + 1759550147U, // SMAX_ZPmZ_H + 1611709123U, // SMAX_ZPmZ_S + 271637187U, // SMAXv16i8 + 272685763U, // SMAXv2i32 + 274782915U, // SMAXv4i16 + 275831491U, // SMAXv4i32 + 276880067U, // SMAXv8i16 + 277928643U, // SMAXv8i8 + 125192U, // SMC + 1611682560U, // SMINP_ZPmZ_B + 1611690752U, // SMINP_ZPmZ_D + 1759548160U, // SMINP_ZPmZ_H + 1611707136U, // SMINP_ZPmZ_S + 271635200U, // SMINPv16i8 + 272683776U, // SMINPv2i32 + 274780928U, // SMINPv4i16 + 275829504U, // SMINPv4i32 + 276878080U, // SMINPv8i16 + 277926656U, // SMINPv8i8 + 80170U, // SMINV_VPZ_B + 823220522U, // SMINV_VPZ_D + 824277290U, // SMINV_VPZ_H + 819042602U, // SMINV_VPZ_S + 269498666U, // SMINVv16i8v + 269498666U, // SMINVv4i16v + 269498666U, // SMINVv4i32v + 269498666U, // SMINVv8i16v + 269498666U, // SMINVv8i8v + 1880117658U, // SMIN_ZI_B + 1209037210U, // SMIN_ZI_D + 1089507738U, // SMIN_ZI_H + 2014359962U, // SMIN_ZI_S + 1611682202U, // SMIN_ZPmZ_B + 1611690394U, // SMIN_ZPmZ_D + 1759547802U, // SMIN_ZPmZ_H + 1611706778U, // SMIN_ZPmZ_S + 271634842U, // SMINv16i8 + 272683418U, // SMINv2i32 + 274780570U, // SMINv4i16 + 275829146U, // SMINv4i32 + 276877722U, // SMINv8i16 + 277926298U, // SMINv8i8 + 672163132U, // SMLALB_ZZZI_D + 1343268156U, // SMLALB_ZZZI_S + 672163132U, // SMLALB_ZZZ_D + 1140884796U, // SMLALB_ZZZ_H + 1343268156U, // SMLALB_ZZZ_S + 672167625U, // SMLALT_ZZZI_D + 1343272649U, // SMLALT_ZZZI_S + 672167625U, // SMLALT_ZZZ_D + 1140889289U, // SMLALT_ZZZ_H + 1343272649U, // SMLALT_ZZZ_S + 1484849350U, // SMLALv16i8_v8i16 + 1481707316U, // SMLALv2i32_indexed + 1481707316U, // SMLALv2i32_v2i64 + 1483804468U, // SMLALv4i16_indexed + 1483804468U, // SMLALv4i16_v4i32 + 1481703622U, // SMLALv4i32_indexed + 1481703622U, // SMLALv4i32_v2i64 + 1483800774U, // SMLALv8i16_indexed + 1483800774U, // SMLALv8i16_v4i32 + 1484853044U, // SMLALv8i8_v8i16 + 672163429U, // SMLSLB_ZZZI_D + 1343268453U, // SMLSLB_ZZZI_S + 672163429U, // SMLSLB_ZZZ_D + 1140885093U, // SMLSLB_ZZZ_H + 1343268453U, // SMLSLB_ZZZ_S + 672167799U, // SMLSLT_ZZZI_D + 1343272823U, // SMLSLT_ZZZI_S + 672167799U, // SMLSLT_ZZZ_D + 1140889463U, // SMLSLT_ZZZ_H + 1343272823U, // SMLSLT_ZZZ_S + 1484849482U, // SMLSLv16i8_v8i16 + 1481707718U, // SMLSLv2i32_indexed + 1481707718U, // SMLSLv2i32_v2i64 + 1483804870U, // SMLSLv4i16_indexed + 1483804870U, // SMLSLv4i16_v4i32 + 1481703754U, // SMLSLv4i32_indexed + 1481703754U, // SMLSLv4i32_v2i64 + 1483800906U, // SMLSLv8i16_indexed + 1483800906U, // SMLSLv8i16_v4i32 + 1484853446U, // SMLSLv8i8_v8i16 + 1483801320U, // SMMLA + 2819662568U, // SMMLA_ZZZ + 69264159U, // SMOPA_MPPZZ_D + 70312735U, // SMOPA_MPPZZ_S + 69268957U, // SMOPS_MPPZZ_D + 70317533U, // SMOPS_MPPZZ_S + 269498693U, // SMOVvi16to32 + 269498693U, // SMOVvi16to32_idx0 + 269498693U, // SMOVvi16to64 + 269498693U, // SMOVvi16to64_idx0 + 269498693U, // SMOVvi32to64 + 269498693U, // SMOVvi32to64_idx0 + 269498693U, // SMOVvi8to32 + 269498693U, // SMOVvi8to32_idx0 + 269498693U, // SMOVvi8to64 + 269498693U, // SMOVvi8to64_idx0 + 403713952U, // SMSUBLrrr + 1611681084U, // SMULH_ZPmZ_B + 1611689276U, // SMULH_ZPmZ_D + 1759546684U, // SMULH_ZPmZ_H + 1611705660U, // SMULH_ZPmZ_S + 1880116540U, // SMULH_ZZZ_B + 1209036092U, // SMULH_ZZZ_D + 1089506620U, // SMULH_ZZZ_H + 2014358844U, // SMULH_ZZZ_S + 403713340U, // SMULHrr + 2014340623U, // SMULLB_ZZZI_D + 940615183U, // SMULLB_ZZZI_S + 2014340623U, // SMULLB_ZZZ_D + 1136690703U, // SMULLB_ZZZ_H + 940615183U, // SMULLB_ZZZ_S + 2014345031U, // SMULLT_ZZZI_D + 940619591U, // SMULLT_ZZZI_S + 2014345031U, // SMULLT_ZZZ_D + 1136695111U, // SMULLT_ZZZ_H + 940619591U, // SMULLT_ZZZ_S + 276873512U, // SMULLv16i8_v8i16 + 273731686U, // SMULLv2i32_indexed + 273731686U, // SMULLv2i32_v2i64 + 275828838U, // SMULLv4i16_indexed + 275828838U, // SMULLv4i16_v4i32 + 273727784U, // SMULLv4i32_indexed + 273727784U, // SMULLv4i32_v2i64 + 275824936U, // SMULLv8i16_indexed + 275824936U, // SMULLv8i16_v4i32 + 276877414U, // SMULLv8i8_v8i16 + 1611680341U, // SPLICE_ZPZZ_B + 1611688533U, // SPLICE_ZPZZ_D + 1088457301U, // SPLICE_ZPZZ_H + 1611704917U, // SPLICE_ZPZZ_S + 1611680341U, // SPLICE_ZPZ_B + 1611688533U, // SPLICE_ZPZ_D + 1088457301U, // SPLICE_ZPZ_H + 1611704917U, // SPLICE_ZPZ_S + 1070376U, // SQABS_ZPmZ_B + 1078568U, // SQABS_ZPmZ_D + 136353064U, // SQABS_ZPmZ_H + 1094952U, // SQABS_ZPmZ_S + 271635752U, // SQABSv16i8 + 403715368U, // SQABSv1i16 + 403715368U, // SQABSv1i32 + 403715368U, // SQABSv1i64 + 403715368U, // SQABSv1i8 + 272684328U, // SQABSv2i32 + 273732904U, // SQABSv2i64 + 274781480U, // SQABSv4i16 + 275830056U, // SQABSv4i32 + 276878632U, // SQABSv8i16 + 277927208U, // SQABSv8i8 + 1880115717U, // SQADD_ZI_B + 1209035269U, // SQADD_ZI_D + 1089505797U, // SQADD_ZI_H + 2014358021U, // SQADD_ZI_S + 1611680261U, // SQADD_ZPmZ_B + 1611688453U, // SQADD_ZPmZ_D + 1759545861U, // SQADD_ZPmZ_H + 1611704837U, // SQADD_ZPmZ_S + 1880115717U, // SQADD_ZZZ_B + 1209035269U, // SQADD_ZZZ_D + 1089505797U, // SQADD_ZZZ_H + 2014358021U, // SQADD_ZZZ_S + 271632901U, // SQADDv16i8 + 403712517U, // SQADDv1i16 + 403712517U, // SQADDv1i32 + 403712517U, // SQADDv1i64 + 403712517U, // SQADDv1i8 + 272681477U, // SQADDv2i32 + 273730053U, // SQADDv2i64 + 274778629U, // SQADDv4i16 + 275827205U, // SQADDv4i32 + 276875781U, // SQADDv8i16 + 277924357U, // SQADDv8i8 + 1880115650U, // SQCADD_ZZI_B + 1209035202U, // SQCADD_ZZI_D + 1089505730U, // SQCADD_ZZI_H + 2014357954U, // SQCADD_ZZI_S + 3490718904U, // SQDECB_XPiI + 2551194808U, // SQDECB_XPiWdI + 3490720155U, // SQDECD_XPiI + 2551196059U, // SQDECD_XPiWdI + 3490736539U, // SQDECD_ZPiI + 3490720841U, // SQDECH_XPiI + 2551196745U, // SQDECH_XPiWdI + 19958857U, // SQDECH_ZPiI + 1880109676U, // SQDECP_XPWd_B + 1209021036U, // SQDECP_XPWd_D + 940585580U, // SQDECP_XPWd_H + 2014327404U, // SQDECP_XPWd_S + 1880109676U, // SQDECP_XP_B + 1209021036U, // SQDECP_XP_D + 940585580U, // SQDECP_XP_H + 2014327404U, // SQDECP_XP_S + 537948780U, // SQDECP_ZP_D + 824218220U, // SQDECP_ZP_H + 672182892U, // SQDECP_ZP_S + 3490724315U, // SQDECW_XPiI + 2551200219U, // SQDECW_XPiWdI + 3490757083U, // SQDECW_ZPiI + 672167474U, // SQDMLALBT_ZZZ_D + 1140889138U, // SQDMLALBT_ZZZ_H + 1343272498U, // SQDMLALBT_ZZZ_S + 672163113U, // SQDMLALB_ZZZI_D + 1343268137U, // SQDMLALB_ZZZI_S + 672163113U, // SQDMLALB_ZZZ_D + 1140884777U, // SQDMLALB_ZZZ_H + 1343268137U, // SQDMLALB_ZZZ_S + 672167606U, // SQDMLALT_ZZZI_D + 1343272630U, // SQDMLALT_ZZZI_S + 672167606U, // SQDMLALT_ZZZ_D + 1140889270U, // SQDMLALT_ZZZ_H + 1343272630U, // SQDMLALT_ZZZ_S + 2282860324U, // SQDMLALi16 + 2282860324U, // SQDMLALi32 + 2282860324U, // SQDMLALv1i32_indexed + 2282860324U, // SQDMLALv1i64_indexed + 1481707300U, // SQDMLALv2i32_indexed + 1481707300U, // SQDMLALv2i32_v2i64 + 1483804452U, // SQDMLALv4i16_indexed + 1483804452U, // SQDMLALv4i16_v4i32 + 1481703604U, // SQDMLALv4i32_indexed + 1481703604U, // SQDMLALv4i32_v2i64 + 1483800756U, // SQDMLALv8i16_indexed + 1483800756U, // SQDMLALv8i16_v4i32 + 672167503U, // SQDMLSLBT_ZZZ_D + 1140889167U, // SQDMLSLBT_ZZZ_H + 1343272527U, // SQDMLSLBT_ZZZ_S + 672163411U, // SQDMLSLB_ZZZI_D + 1343268435U, // SQDMLSLB_ZZZI_S + 672163411U, // SQDMLSLB_ZZZ_D + 1140885075U, // SQDMLSLB_ZZZ_H + 1343268435U, // SQDMLSLB_ZZZ_S + 672167781U, // SQDMLSLT_ZZZI_D + 1343272805U, // SQDMLSLT_ZZZI_S + 672167781U, // SQDMLSLT_ZZZ_D + 1140889445U, // SQDMLSLT_ZZZ_H + 1343272805U, // SQDMLSLT_ZZZ_S + 2282860726U, // SQDMLSLi16 + 2282860726U, // SQDMLSLi32 + 2282860726U, // SQDMLSLv1i32_indexed + 2282860726U, // SQDMLSLv1i64_indexed + 1481707702U, // SQDMLSLv2i32_indexed + 1481707702U, // SQDMLSLv2i32_v2i64 + 1483804854U, // SQDMLSLv4i16_indexed + 1483804854U, // SQDMLSLv4i16_v4i32 + 1481703736U, // SQDMLSLv4i32_indexed + 1481703736U, // SQDMLSLv4i32_v2i64 + 1483800888U, // SQDMLSLv8i16_indexed + 1483800888U, // SQDMLSLv8i16_v4i32 + 1209036073U, // SQDMULH_ZZZI_D + 1089506601U, // SQDMULH_ZZZI_H + 2014358825U, // SQDMULH_ZZZI_S + 1880116521U, // SQDMULH_ZZZ_B + 1209036073U, // SQDMULH_ZZZ_D + 1089506601U, // SQDMULH_ZZZ_H + 2014358825U, // SQDMULH_ZZZ_S + 403713321U, // SQDMULHv1i16 + 403713321U, // SQDMULHv1i16_indexed + 403713321U, // SQDMULHv1i32 + 403713321U, // SQDMULHv1i32_indexed + 272682281U, // SQDMULHv2i32 + 272682281U, // SQDMULHv2i32_indexed + 274779433U, // SQDMULHv4i16 + 274779433U, // SQDMULHv4i16_indexed + 275828009U, // SQDMULHv4i32 + 275828009U, // SQDMULHv4i32_indexed + 276876585U, // SQDMULHv8i16 + 276876585U, // SQDMULHv8i16_indexed + 2014340605U, // SQDMULLB_ZZZI_D + 940615165U, // SQDMULLB_ZZZI_S + 2014340605U, // SQDMULLB_ZZZ_D + 1136690685U, // SQDMULLB_ZZZ_H + 940615165U, // SQDMULLB_ZZZ_S + 2014345013U, // SQDMULLT_ZZZI_D + 940619573U, // SQDMULLT_ZZZI_S + 2014345013U, // SQDMULLT_ZZZ_D + 1136695093U, // SQDMULLT_ZZZ_H + 940619573U, // SQDMULLT_ZZZ_S + 403714134U, // SQDMULLi16 + 403714134U, // SQDMULLi32 + 403714134U, // SQDMULLv1i32_indexed + 403714134U, // SQDMULLv1i64_indexed + 273731670U, // SQDMULLv2i32_indexed + 273731670U, // SQDMULLv2i32_v2i64 + 275828822U, // SQDMULLv4i16_indexed + 275828822U, // SQDMULLv4i16_v4i32 + 273727766U, // SQDMULLv4i32_indexed + 273727766U, // SQDMULLv4i32_v2i64 + 275824918U, // SQDMULLv8i16_indexed + 275824918U, // SQDMULLv8i16_v4i32 + 3490718920U, // SQINCB_XPiI + 2551194824U, // SQINCB_XPiWdI + 3490720171U, // SQINCD_XPiI + 2551196075U, // SQINCD_XPiWdI + 3490736555U, // SQINCD_ZPiI + 3490720857U, // SQINCH_XPiI + 2551196761U, // SQINCH_XPiWdI + 19958873U, // SQINCH_ZPiI + 1880109692U, // SQINCP_XPWd_B + 1209021052U, // SQINCP_XPWd_D + 940585596U, // SQINCP_XPWd_H + 2014327420U, // SQINCP_XPWd_S + 1880109692U, // SQINCP_XP_B + 1209021052U, // SQINCP_XP_D + 940585596U, // SQINCP_XP_H + 2014327420U, // SQINCP_XP_S + 537948796U, // SQINCP_ZP_D + 824218236U, // SQINCP_ZP_H + 672182908U, // SQINCP_ZP_S + 3490724331U, // SQINCW_XPiI + 2551200235U, // SQINCW_XPiWdI + 3490757099U, // SQINCW_ZPiI + 1067833U, // SQNEG_ZPmZ_B + 1076025U, // SQNEG_ZPmZ_D + 136350521U, // SQNEG_ZPmZ_H + 1092409U, // SQNEG_ZPmZ_S + 271633209U, // SQNEGv16i8 + 403712825U, // SQNEGv1i16 + 403712825U, // SQNEGv1i32 + 403712825U, // SQNEGv1i64 + 403712825U, // SQNEGv1i8 + 272681785U, // SQNEGv2i32 + 273730361U, // SQNEGv2i64 + 274778937U, // SQNEGv4i16 + 275827513U, // SQNEGv4i32 + 276876089U, // SQNEGv8i16 + 277924665U, // SQNEGv8i8 + 1092651994U, // SQRDCMLAH_ZZZI_H + 672181210U, // SQRDCMLAH_ZZZI_S + 2819640282U, // SQRDCMLAH_ZZZ_B + 537947098U, // SQRDCMLAH_ZZZ_D + 1092651994U, // SQRDCMLAH_ZZZ_H + 672181210U, // SQRDCMLAH_ZZZ_S + 537947109U, // SQRDMLAH_ZZZI_D + 1092652005U, // SQRDMLAH_ZZZI_H + 672181221U, // SQRDMLAH_ZZZI_S + 2819640293U, // SQRDMLAH_ZZZ_B + 537947109U, // SQRDMLAH_ZZZ_D + 1092652005U, // SQRDMLAH_ZZZ_H + 672181221U, // SQRDMLAH_ZZZ_S + 2282859493U, // SQRDMLAHi16_indexed + 2282859493U, // SQRDMLAHi32_indexed + 2282859493U, // SQRDMLAHv1i16 + 2282859493U, // SQRDMLAHv1i32 + 1480657893U, // SQRDMLAHv2i32 + 1480657893U, // SQRDMLAHv2i32_indexed + 1482755045U, // SQRDMLAHv4i16 + 1482755045U, // SQRDMLAHv4i16_indexed + 1483803621U, // SQRDMLAHv4i32 + 1483803621U, // SQRDMLAHv4i32_indexed + 1484852197U, // SQRDMLAHv8i16 + 1484852197U, // SQRDMLAHv8i16_indexed + 537947714U, // SQRDMLSH_ZZZI_D + 1092652610U, // SQRDMLSH_ZZZI_H + 672181826U, // SQRDMLSH_ZZZI_S + 2819640898U, // SQRDMLSH_ZZZ_B + 537947714U, // SQRDMLSH_ZZZ_D + 1092652610U, // SQRDMLSH_ZZZ_H + 672181826U, // SQRDMLSH_ZZZ_S + 2282860098U, // SQRDMLSHi16_indexed + 2282860098U, // SQRDMLSHi32_indexed + 2282860098U, // SQRDMLSHv1i16 + 2282860098U, // SQRDMLSHv1i32 + 1480658498U, // SQRDMLSHv2i32 + 1480658498U, // SQRDMLSHv2i32_indexed + 1482755650U, // SQRDMLSHv4i16 + 1482755650U, // SQRDMLSHv4i16_indexed + 1483804226U, // SQRDMLSHv4i32 + 1483804226U, // SQRDMLSHv4i32_indexed + 1484852802U, // SQRDMLSHv8i16 + 1484852802U, // SQRDMLSHv8i16_indexed + 1209036082U, // SQRDMULH_ZZZI_D + 1089506610U, // SQRDMULH_ZZZI_H + 2014358834U, // SQRDMULH_ZZZI_S + 1880116530U, // SQRDMULH_ZZZ_B + 1209036082U, // SQRDMULH_ZZZ_D + 1089506610U, // SQRDMULH_ZZZ_H + 2014358834U, // SQRDMULH_ZZZ_S + 403713330U, // SQRDMULHv1i16 + 403713330U, // SQRDMULHv1i16_indexed + 403713330U, // SQRDMULHv1i32 + 403713330U, // SQRDMULHv1i32_indexed + 272682290U, // SQRDMULHv2i32 + 272682290U, // SQRDMULHv2i32_indexed + 274779442U, // SQRDMULHv4i16 + 274779442U, // SQRDMULHv4i16_indexed + 275828018U, // SQRDMULHv4i32 + 275828018U, // SQRDMULHv4i32_indexed + 276876594U, // SQRDMULHv8i16 + 276876594U, // SQRDMULHv8i16_indexed + 1611682857U, // SQRSHLR_ZPmZ_B + 1611691049U, // SQRSHLR_ZPmZ_D + 1759548457U, // SQRSHLR_ZPmZ_H + 1611707433U, // SQRSHLR_ZPmZ_S + 1611681822U, // SQRSHL_ZPmZ_B + 1611690014U, // SQRSHL_ZPmZ_D + 1759547422U, // SQRSHL_ZPmZ_H + 1611706398U, // SQRSHL_ZPmZ_S + 271634462U, // SQRSHLv16i8 + 403714078U, // SQRSHLv1i16 + 403714078U, // SQRSHLv1i32 + 403714078U, // SQRSHLv1i64 + 403714078U, // SQRSHLv1i8 + 272683038U, // SQRSHLv2i32 + 273731614U, // SQRSHLv2i64 + 274780190U, // SQRSHLv4i16 + 275828766U, // SQRSHLv4i32 + 276877342U, // SQRSHLv8i16 + 277925918U, // SQRSHLv8i8 + 940590797U, // SQRSHRNB_ZZI_B + 1086359245U, // SQRSHRNB_ZZI_H + 1209050829U, // SQRSHRNB_ZZI_S + 1343248322U, // SQRSHRNT_ZZI_B + 1087412162U, // SQRSHRNT_ZZI_H + 537966530U, // SQRSHRNT_ZZI_S + 403714505U, // SQRSHRNb + 403714505U, // SQRSHRNh + 403714505U, // SQRSHRNs + 1479606662U, // SQRSHRNv16i8_shift + 272683465U, // SQRSHRNv2i32_shift + 274780617U, // SQRSHRNv4i16_shift + 1483800966U, // SQRSHRNv4i32_shift + 1484849542U, // SQRSHRNv8i16_shift + 277926345U, // SQRSHRNv8i8_shift + 940590843U, // SQRSHRUNB_ZZI_B + 1086359291U, // SQRSHRUNB_ZZI_H + 1209050875U, // SQRSHRUNB_ZZI_S + 1343248377U, // SQRSHRUNT_ZZI_B + 1087412217U, // SQRSHRUNT_ZZI_H + 537966585U, // SQRSHRUNT_ZZI_S + 403714567U, // SQRSHRUNb + 403714567U, // SQRSHRUNh + 403714567U, // SQRSHRUNs + 1479606723U, // SQRSHRUNv16i8_shift + 272683527U, // SQRSHRUNv2i32_shift + 274780679U, // SQRSHRUNv4i16_shift + 1483801027U, // SQRSHRUNv4i32_shift + 1484849603U, // SQRSHRUNv8i16_shift + 277926407U, // SQRSHRUNv8i8_shift + 1611682841U, // SQSHLR_ZPmZ_B + 1611691033U, // SQSHLR_ZPmZ_D + 1759548441U, // SQSHLR_ZPmZ_H + 1611707417U, // SQSHLR_ZPmZ_S + 1611683999U, // SQSHLU_ZPmI_B + 1611692191U, // SQSHLU_ZPmI_D + 1759549599U, // SQSHLU_ZPmI_H + 1611708575U, // SQSHLU_ZPmI_S + 403716255U, // SQSHLUb + 403716255U, // SQSHLUd + 403716255U, // SQSHLUh + 403716255U, // SQSHLUs + 271636639U, // SQSHLUv16i8_shift + 272685215U, // SQSHLUv2i32_shift + 273733791U, // SQSHLUv2i64_shift + 274782367U, // SQSHLUv4i16_shift + 275830943U, // SQSHLUv4i32_shift + 276879519U, // SQSHLUv8i16_shift + 277928095U, // SQSHLUv8i8_shift + 1611681808U, // SQSHL_ZPmI_B + 1611690000U, // SQSHL_ZPmI_D + 1759547408U, // SQSHL_ZPmI_H + 1611706384U, // SQSHL_ZPmI_S + 1611681808U, // SQSHL_ZPmZ_B + 1611690000U, // SQSHL_ZPmZ_D + 1759547408U, // SQSHL_ZPmZ_H + 1611706384U, // SQSHL_ZPmZ_S + 403714064U, // SQSHLb + 403714064U, // SQSHLd + 403714064U, // SQSHLh + 403714064U, // SQSHLs + 271634448U, // SQSHLv16i8 + 271634448U, // SQSHLv16i8_shift + 403714064U, // SQSHLv1i16 + 403714064U, // SQSHLv1i32 + 403714064U, // SQSHLv1i64 + 403714064U, // SQSHLv1i8 + 272683024U, // SQSHLv2i32 + 272683024U, // SQSHLv2i32_shift + 273731600U, // SQSHLv2i64 + 273731600U, // SQSHLv2i64_shift + 274780176U, // SQSHLv4i16 + 274780176U, // SQSHLv4i16_shift + 275828752U, // SQSHLv4i32 + 275828752U, // SQSHLv4i32_shift + 276877328U, // SQSHLv8i16 + 276877328U, // SQSHLv8i16_shift + 277925904U, // SQSHLv8i8 + 277925904U, // SQSHLv8i8_shift + 940590779U, // SQSHRNB_ZZI_B + 1086359227U, // SQSHRNB_ZZI_H + 1209050811U, // SQSHRNB_ZZI_S + 1343248304U, // SQSHRNT_ZZI_B + 1087412144U, // SQSHRNT_ZZI_H + 537966512U, // SQSHRNT_ZZI_S + 403714489U, // SQSHRNb + 403714489U, // SQSHRNh + 403714489U, // SQSHRNs + 1479606644U, // SQSHRNv16i8_shift + 272683449U, // SQSHRNv2i32_shift + 274780601U, // SQSHRNv4i16_shift + 1483800948U, // SQSHRNv4i32_shift + 1484849524U, // SQSHRNv8i16_shift + 277926329U, // SQSHRNv8i8_shift + 940590833U, // SQSHRUNB_ZZI_B + 1086359281U, // SQSHRUNB_ZZI_H + 1209050865U, // SQSHRUNB_ZZI_S + 1343248367U, // SQSHRUNT_ZZI_B + 1087412207U, // SQSHRUNT_ZZI_H + 537966575U, // SQSHRUNT_ZZI_S + 403714558U, // SQSHRUNb + 403714558U, // SQSHRUNh + 403714558U, // SQSHRUNs + 1479606713U, // SQSHRUNv16i8_shift + 272683518U, // SQSHRUNv2i32_shift + 274780670U, // SQSHRUNv4i16_shift + 1483801017U, // SQSHRUNv4i32_shift + 1484849593U, // SQSHRUNv8i16_shift + 277926398U, // SQSHRUNv8i8_shift + 1611682763U, // SQSUBR_ZPmZ_B + 1611690955U, // SQSUBR_ZPmZ_D + 1759548363U, // SQSUBR_ZPmZ_H + 1611707339U, // SQSUBR_ZPmZ_S + 1880115330U, // SQSUB_ZI_B + 1209034882U, // SQSUB_ZI_D + 1089505410U, // SQSUB_ZI_H + 2014357634U, // SQSUB_ZI_S + 1611679874U, // SQSUB_ZPmZ_B + 1611688066U, // SQSUB_ZPmZ_D + 1759545474U, // SQSUB_ZPmZ_H + 1611704450U, // SQSUB_ZPmZ_S + 1880115330U, // SQSUB_ZZZ_B + 1209034882U, // SQSUB_ZZZ_D + 1089505410U, // SQSUB_ZZZ_H + 2014357634U, // SQSUB_ZZZ_S + 271632514U, // SQSUBv16i8 + 403712130U, // SQSUBv1i16 + 403712130U, // SQSUBv1i32 + 403712130U, // SQSUBv1i64 + 403712130U, // SQSUBv1i8 + 272681090U, // SQSUBv2i32 + 273729666U, // SQSUBv2i64 + 274778242U, // SQSUBv4i16 + 275826818U, // SQSUBv4i32 + 276875394U, // SQSUBv8i16 + 277923970U, // SQSUBv8i8 + 940590817U, // SQXTNB_ZZ_B + 817923809U, // SQXTNB_ZZ_H + 1209050849U, // SQXTNB_ZZ_S + 1343248351U, // SQXTNT_ZZ_B + 818976735U, // SQXTNT_ZZ_H + 537966559U, // SQXTNT_ZZ_S + 1479606697U, // SQXTNv16i8 + 403714544U, // SQXTNv1i16 + 403714544U, // SQXTNv1i32 + 403714544U, // SQXTNv1i8 + 272683504U, // SQXTNv2i32 + 274780656U, // SQXTNv4i16 + 1483801001U, // SQXTNv4i32 + 1484849577U, // SQXTNv8i16 + 277926384U, // SQXTNv8i8 + 940590854U, // SQXTUNB_ZZ_B + 817923846U, // SQXTUNB_ZZ_H + 1209050886U, // SQXTUNB_ZZ_S + 1343248388U, // SQXTUNT_ZZ_B + 818976772U, // SQXTUNT_ZZ_H + 537966596U, // SQXTUNT_ZZ_S + 1479606734U, // SQXTUNv16i8 + 403714577U, // SQXTUNv1i16 + 403714577U, // SQXTUNv1i32 + 403714577U, // SQXTUNv1i8 + 272683537U, // SQXTUNv2i32 + 274780689U, // SQXTUNv4i16 + 1483801038U, // SQXTUNv4i32 + 1484849614U, // SQXTUNv8i16 + 277926417U, // SQXTUNv8i8 + 1611680215U, // SRHADD_ZPmZ_B + 1611688407U, // SRHADD_ZPmZ_D + 1759545815U, // SRHADD_ZPmZ_H + 1611704791U, // SRHADD_ZPmZ_S + 271632855U, // SRHADDv16i8 + 272681431U, // SRHADDv2i32 + 274778583U, // SRHADDv4i16 + 275827159U, // SRHADDv4i32 + 276875735U, // SRHADDv8i16 + 277924311U, // SRHADDv8i8 + 2819641071U, // SRI_ZZI_B + 537947887U, // SRI_ZZI_D + 1092652783U, // SRI_ZZI_H + 672181999U, // SRI_ZZI_S + 2282860271U, // SRId + 1479610095U, // SRIv16i8_shift + 1480658671U, // SRIv2i32_shift + 1481707247U, // SRIv2i64_shift + 1482755823U, // SRIv4i16_shift + 1483804399U, // SRIv4i32_shift + 1484852975U, // SRIv8i16_shift + 1485901551U, // SRIv8i8_shift + 1611682875U, // SRSHLR_ZPmZ_B + 1611691067U, // SRSHLR_ZPmZ_D + 1759548475U, // SRSHLR_ZPmZ_H + 1611707451U, // SRSHLR_ZPmZ_S + 1611681838U, // SRSHL_ZPmZ_B + 1611690030U, // SRSHL_ZPmZ_D + 1759547438U, // SRSHL_ZPmZ_H + 1611706414U, // SRSHL_ZPmZ_S + 271634478U, // SRSHLv16i8 + 403714094U, // SRSHLv1i64 + 272683054U, // SRSHLv2i32 + 273731630U, // SRSHLv2i64 + 274780206U, // SRSHLv4i16 + 275828782U, // SRSHLv4i32 + 276877358U, // SRSHLv8i16 + 277925934U, // SRSHLv8i8 + 1611682803U, // SRSHR_ZPmI_B + 1611690995U, // SRSHR_ZPmI_D + 1759548403U, // SRSHR_ZPmI_H + 1611707379U, // SRSHR_ZPmI_S + 403715059U, // SRSHRd + 271635443U, // SRSHRv16i8_shift + 272684019U, // SRSHRv2i32_shift + 273732595U, // SRSHRv2i64_shift + 274781171U, // SRSHRv4i16_shift + 275829747U, // SRSHRv4i32_shift + 276878323U, // SRSHRv8i16_shift + 277926899U, // SRSHRv8i8_shift + 2819638098U, // SRSRA_ZZI_B + 537944914U, // SRSRA_ZZI_D + 1092649810U, // SRSRA_ZZI_H + 672179026U, // SRSRA_ZZI_S + 2282857298U, // SRSRAd + 1479607122U, // SRSRAv16i8_shift + 1480655698U, // SRSRAv2i32_shift + 1481704274U, // SRSRAv2i64_shift + 1482752850U, // SRSRAv4i16_shift + 1483801426U, // SRSRAv4i32_shift + 1484850002U, // SRSRAv8i16_shift + 1485898578U, // SRSRAv8i8_shift + 2014340589U, // SSHLLB_ZZI_D + 1136690669U, // SSHLLB_ZZI_H + 940615149U, // SSHLLB_ZZI_S + 2014344997U, // SSHLLT_ZZI_D + 1136695077U, // SSHLLT_ZZI_H + 940619557U, // SSHLLT_ZZI_S + 276873478U, // SSHLLv16i8_shift + 273731656U, // SSHLLv2i32_shift + 275828808U, // SSHLLv4i16_shift + 273727750U, // SSHLLv4i32_shift + 275824902U, // SSHLLv8i16_shift + 276877384U, // SSHLLv8i8_shift + 271634492U, // SSHLv16i8 + 403714108U, // SSHLv1i64 + 272683068U, // SSHLv2i32 + 273731644U, // SSHLv2i64 + 274780220U, // SSHLv4i16 + 275828796U, // SSHLv4i32 + 276877372U, // SSHLv8i16 + 277925948U, // SSHLv8i8 + 403715073U, // SSHRd + 271635457U, // SSHRv16i8_shift + 272684033U, // SSHRv2i32_shift + 273732609U, // SSHRv2i64_shift + 274781185U, // SSHRv4i16_shift + 275829761U, // SSHRv4i32_shift + 276878337U, // SSHRv8i16_shift + 277926913U, // SSHRv8i8_shift + 2819638112U, // SSRA_ZZI_B + 537944928U, // SSRA_ZZI_D + 1092649824U, // SSRA_ZZI_H + 672179040U, // SSRA_ZZI_S + 2282857312U, // SSRAd + 1479607136U, // SSRAv16i8_shift + 1480655712U, // SSRAv2i32_shift + 1481704288U, // SSRAv2i64_shift + 1482752864U, // SSRAv4i16_shift + 1483801440U, // SSRAv4i32_shift + 1484850016U, // SSRAv8i16_shift + 1485898592U, // SSRAv8i8_shift + 553829359U, // SST1B_D_IMM + 2298659823U, // SST1B_D_REAL + 2298659823U, // SST1B_D_SXTW + 2298659823U, // SST1B_D_UXTW + 688055279U, // SST1B_S_IMM + 2298668015U, // SST1B_S_SXTW + 2298668015U, // SST1B_S_UXTW + 553830724U, // SST1D_IMM + 2298661188U, // SST1D_REAL + 2298661188U, // SST1D_SCALED_SCALED_REAL + 2298661188U, // SST1D_SXTW + 2298661188U, // SST1D_SXTW_SCALED + 2298661188U, // SST1D_UXTW + 2298661188U, // SST1D_UXTW_SCALED + 553831309U, // SST1H_D_IMM + 2298661773U, // SST1H_D_REAL + 2298661773U, // SST1H_D_SCALED_SCALED_REAL + 2298661773U, // SST1H_D_SXTW + 2298661773U, // SST1H_D_SXTW_SCALED + 2298661773U, // SST1H_D_UXTW + 2298661773U, // SST1H_D_UXTW_SCALED + 688057229U, // SST1H_S_IMM + 2298669965U, // SST1H_S_SXTW + 2298669965U, // SST1H_S_SXTW_SCALED + 2298669965U, // SST1H_S_UXTW + 2298669965U, // SST1H_S_UXTW_SCALED + 553834898U, // SST1W_D_IMM + 2298665362U, // SST1W_D_REAL + 2298665362U, // SST1W_D_SCALED_SCALED_REAL + 2298665362U, // SST1W_D_SXTW + 2298665362U, // SST1W_D_SXTW_SCALED + 2298665362U, // SST1W_D_UXTW + 2298665362U, // SST1W_D_UXTW_SCALED + 688060818U, // SST1W_IMM + 2298673554U, // SST1W_SXTW + 2298673554U, // SST1W_SXTW_SCALED + 2298673554U, // SST1W_UXTW + 2298673554U, // SST1W_UXTW_SCALED + 2014344765U, // SSUBLBT_ZZZ_D + 1136694845U, // SSUBLBT_ZZZ_H + 940619325U, // SSUBLBT_ZZZ_S + 2014340518U, // SSUBLB_ZZZ_D + 1136690598U, // SSUBLB_ZZZ_H + 940615078U, // SSUBLB_ZZZ_S + 2014341173U, // SSUBLTB_ZZZ_D + 1136691253U, // SSUBLTB_ZZZ_H + 940615733U, // SSUBLTB_ZZZ_S + 2014344921U, // SSUBLT_ZZZ_D + 1136695001U, // SSUBLT_ZZZ_H + 940619481U, // SSUBLT_ZZZ_S + 276873430U, // SSUBLv16i8_v8i16 + 273731504U, // SSUBLv2i32_v2i64 + 275828656U, // SSUBLv4i16_v4i32 + 273727702U, // SSUBLv4i32_v2i64 + 275824854U, // SSUBLv8i16_v4i32 + 276877232U, // SSUBLv8i8_v8i16 + 1209034902U, // SSUBWB_ZZZ_D + 1089505430U, // SSUBWB_ZZZ_H + 2014357654U, // SSUBWB_ZZZ_S + 1209038954U, // SSUBWT_ZZZ_D + 1089509482U, // SSUBWT_ZZZ_H + 2014361706U, // SSUBWT_ZZZ_S + 276873720U, // SSUBWv16i8_v8i16 + 273734084U, // SSUBWv2i32_v2i64 + 275831236U, // SSUBWv4i16_v4i32 + 273727992U, // SSUBWv4i32_v2i64 + 275825144U, // SSUBWv8i16_v4i32 + 276879812U, // SSUBWv8i8_v8i16 + 2298700783U, // ST1B + 2298659823U, // ST1B_D + 2298659823U, // ST1B_D_IMM + 2298708975U, // ST1B_H + 2298708975U, // ST1B_H_IMM + 2298700783U, // ST1B_IMM + 2298668015U, // ST1B_S + 2298668015U, // ST1B_S_IMM + 2298661188U, // ST1D + 2298661188U, // ST1D_IMM + 237647U, // ST1Fourv16b + 37994575U, // ST1Fourv16b_POST + 254031U, // ST1Fourv1d + 39059535U, // ST1Fourv1d_POST + 270415U, // ST1Fourv2d + 38027343U, // ST1Fourv2d_POST + 286799U, // ST1Fourv2s + 39092303U, // ST1Fourv2s_POST + 303183U, // ST1Fourv4h + 39108687U, // ST1Fourv4h_POST + 319567U, // ST1Fourv4s + 38076495U, // ST1Fourv4s_POST + 335951U, // ST1Fourv8b + 39141455U, // ST1Fourv8b_POST + 352335U, // ST1Fourv8h + 38109263U, // ST1Fourv8h_POST + 2298710925U, // ST1H + 2298661773U, // ST1H_D + 2298661773U, // ST1H_D_IMM + 2298710925U, // ST1H_IMM + 2298669965U, // ST1H_S + 2298669965U, // ST1H_S_IMM + 237647U, // ST1Onev16b + 40091727U, // ST1Onev16b_POST + 254031U, // ST1Onev1d + 41156687U, // ST1Onev1d_POST + 270415U, // ST1Onev2d + 40124495U, // ST1Onev2d_POST + 286799U, // ST1Onev2s + 41189455U, // ST1Onev2s_POST + 303183U, // ST1Onev4h + 41205839U, // ST1Onev4h_POST + 319567U, // ST1Onev4s + 40173647U, // ST1Onev4s_POST + 335951U, // ST1Onev8b + 41238607U, // ST1Onev8b_POST + 352335U, // ST1Onev8h + 40206415U, // ST1Onev8h_POST + 237647U, // ST1Threev16b + 45334607U, // ST1Threev16b_POST + 254031U, // ST1Threev1d + 46399567U, // ST1Threev1d_POST + 270415U, // ST1Threev2d + 45367375U, // ST1Threev2d_POST + 286799U, // ST1Threev2s + 46432335U, // ST1Threev2s_POST + 303183U, // ST1Threev4h + 46448719U, // ST1Threev4h_POST + 319567U, // ST1Threev4s + 45416527U, // ST1Threev4s_POST + 335951U, // ST1Threev8b + 46481487U, // ST1Threev8b_POST + 352335U, // ST1Threev8h + 45449295U, // ST1Threev8h_POST + 237647U, // ST1Twov16b + 39043151U, // ST1Twov16b_POST + 254031U, // ST1Twov1d + 40108111U, // ST1Twov1d_POST + 270415U, // ST1Twov2d + 39075919U, // ST1Twov2d_POST + 286799U, // ST1Twov2s + 40140879U, // ST1Twov2s_POST + 303183U, // ST1Twov4h + 40157263U, // ST1Twov4h_POST + 319567U, // ST1Twov4s + 39125071U, // ST1Twov4s_POST + 335951U, // ST1Twov8b + 40190031U, // ST1Twov8b_POST + 352335U, // ST1Twov8h + 39157839U, // ST1Twov8h_POST + 2298673554U, // ST1W + 2298665362U, // ST1W_D + 2298665362U, // ST1W_D_IMM + 2298673554U, // ST1W_IMM + 2731752803U, // ST1_MXIPXX_H_B + 2731752817U, // ST1_MXIPXX_H_D + 2731752831U, // ST1_MXIPXX_H_H + 2731752845U, // ST1_MXIPXX_H_Q + 2731752859U, // ST1_MXIPXX_H_S + 2731760995U, // ST1_MXIPXX_V_B + 2731761009U, // ST1_MXIPXX_V_D + 2731761023U, // ST1_MXIPXX_V_H + 2731761037U, // ST1_MXIPXX_V_Q + 2731761051U, // ST1_MXIPXX_V_S + 499791U, // ST1i16 + 2851446863U, // ST1i16_POST + 507983U, // ST1i32 + 2985680975U, // ST1i32_POST + 516175U, // ST1i64 + 3119915087U, // ST1i64_POST + 524367U, // ST1i8 + 3254149199U, // ST1i8_POST + 2298700812U, // ST2B + 2298700812U, // ST2B_IMM + 2298661200U, // ST2D + 2298661200U, // ST2D_IMM + 419441429U, // ST2GOffset + 2298587925U, // ST2GPostIndex + 2298587925U, // ST2GPreIndex + 2298710954U, // ST2H + 2298710954U, // ST2H_IMM + 238067U, // ST2Twov16b + 39043571U, // ST2Twov16b_POST + 270835U, // ST2Twov2d + 39076339U, // ST2Twov2d_POST + 287219U, // ST2Twov2s + 40141299U, // ST2Twov2s_POST + 303603U, // ST2Twov4h + 40157683U, // ST2Twov4h_POST + 319987U, // ST2Twov4s + 39125491U, // ST2Twov4s_POST + 336371U, // ST2Twov8b + 40190451U, // ST2Twov8b_POST + 352755U, // ST2Twov8h + 39158259U, // ST2Twov8h_POST + 2298673574U, // ST2W + 2298673574U, // ST2W_IMM + 500211U, // ST2i16 + 2985665011U, // ST2i16_POST + 508403U, // ST2i32 + 3119899123U, // ST2i32_POST + 516595U, // ST2i64 + 3388350963U, // ST2i64_POST + 524787U, // ST2i8 + 2851496435U, // ST2i8_POST + 2298700833U, // ST3B + 2298700833U, // ST3B_IMM + 2298661212U, // ST3D + 2298661212U, // ST3D_IMM + 2298710966U, // ST3H + 2298710966U, // ST3H_IMM + 238133U, // ST3Threev16b + 45335093U, // ST3Threev16b_POST + 270901U, // ST3Threev2d + 45367861U, // ST3Threev2d_POST + 287285U, // ST3Threev2s + 46432821U, // ST3Threev2s_POST + 303669U, // ST3Threev4h + 46449205U, // ST3Threev4h_POST + 320053U, // ST3Threev4s + 45417013U, // ST3Threev4s_POST + 336437U, // ST3Threev8b + 46481973U, // ST3Threev8b_POST + 352821U, // ST3Threev8h + 45449781U, // ST3Threev8h_POST + 2298673586U, // ST3W + 2298673586U, // ST3W_IMM + 500277U, // ST3i16 + 3522535989U, // ST3i16_POST + 508469U, // ST3i32 + 3656770101U, // ST3i32_POST + 516661U, // ST3i64 + 3791004213U, // ST3i64_POST + 524853U, // ST3i8 + 3925238325U, // ST3i8_POST + 2298700859U, // ST4B + 2298700859U, // ST4B_IMM + 2298661224U, // ST4D + 2298661224U, // ST4D_IMM + 238150U, // ST4Fourv16b + 37995078U, // ST4Fourv16b_POST + 270918U, // ST4Fourv2d + 38027846U, // ST4Fourv2d_POST + 287302U, // ST4Fourv2s + 39092806U, // ST4Fourv2s_POST + 303686U, // ST4Fourv4h + 39109190U, // ST4Fourv4h_POST + 320070U, // ST4Fourv4s + 38076998U, // ST4Fourv4s_POST + 336454U, // ST4Fourv8b + 39141958U, // ST4Fourv8b_POST + 352838U, // ST4Fourv8h + 38109766U, // ST4Fourv8h_POST + 2298710978U, // ST4H + 2298710978U, // ST4H_IMM + 2298673598U, // ST4W + 2298673598U, // ST4W_IMM + 500294U, // ST4i16 + 3119882822U, // ST4i16_POST + 508486U, // ST4i32 + 3388334662U, // ST4i32_POST + 516678U, // ST4i64 + 4059439686U, // ST4i64_POST + 524870U, // ST4i8 + 2985714246U, // ST4i8_POST + 435246U, // ST64B + 4161812679U, // ST64BV + 4161806368U, // ST64BV0 + 419443010U, // STGM + 419441493U, // STGOffset + 403714718U, // STGPi + 2298587989U, // STGPostIndex + 2282861214U, // STGPpost + 2282861214U, // STGPpre + 2298587989U, // STGPreIndex + 419440464U, // STLLRB + 419442090U, // STLLRH + 419443787U, // STLLRW + 419443787U, // STLLRX + 419440472U, // STLRB + 419442098U, // STLRH + 419443800U, // STLRW + 419443800U, // STLRX + 419440522U, // STLURBi + 419442148U, // STLURHi + 419443897U, // STLURWi + 419443897U, // STLURXi + 403714918U, // STLXPW + 403714918U, // STLXPX + 403711921U, // STLXRB + 403713547U, // STLXRH + 403715321U, // STLXRW + 403715321U, // STLXRX + 403714830U, // STNPDi + 403714830U, // STNPQi + 403714830U, // STNPSi + 403714830U, // STNPWi + 403714830U, // STNPXi + 2298700775U, // STNT1B_ZRI + 2298700775U, // STNT1B_ZRR + 553829351U, // STNT1B_ZZR_D_REAL + 688055271U, // STNT1B_ZZR_S_REAL + 2298661180U, // STNT1D_ZRI + 2298661180U, // STNT1D_ZRR + 553830716U, // STNT1D_ZZR_D_REAL + 2298710917U, // STNT1H_ZRI + 2298710917U, // STNT1H_ZRR + 553831301U, // STNT1H_ZZR_D_REAL + 688057221U, // STNT1H_ZZR_S_REAL + 2298673546U, // STNT1W_ZRI + 2298673546U, // STNT1W_ZRR + 553834890U, // STNT1W_ZZR_D_REAL + 688060810U, // STNT1W_ZZR_S_REAL + 403714868U, // STPDi + 2282861364U, // STPDpost + 2282861364U, // STPDpre + 403714868U, // STPQi + 2282861364U, // STPQpost + 2282861364U, // STPQpre + 403714868U, // STPSi + 2282861364U, // STPSpost + 2282861364U, // STPSpre + 403714868U, // STPWi + 2282861364U, // STPWpost + 2282861364U, // STPWpre + 403714868U, // STPXi + 2282861364U, // STPXpost + 2282861364U, // STPXpre + 2298586998U, // STRBBpost + 2298586998U, // STRBBpre + 419440502U, // STRBBroW + 419440502U, // STRBBroX + 419440502U, // STRBBui + 2298590370U, // STRBpost + 2298590370U, // STRBpre + 419443874U, // STRBroW + 419443874U, // STRBroX + 419443874U, // STRBui + 2298590370U, // STRDpost + 2298590370U, // STRDpre + 419443874U, // STRDroW + 419443874U, // STRDroX + 419443874U, // STRDui + 2298588624U, // STRHHpost + 2298588624U, // STRHHpre + 419442128U, // STRHHroW + 419442128U, // STRHHroX + 419442128U, // STRHHui + 2298590370U, // STRHpost + 2298590370U, // STRHpre + 419443874U, // STRHroW + 419443874U, // STRHroX + 419443874U, // STRHui + 2298590370U, // STRQpost + 2298590370U, // STRQpre + 419443874U, // STRQroW + 419443874U, // STRQroX + 419443874U, // STRQui + 2298590370U, // STRSpost + 2298590370U, // STRSpre + 419443874U, // STRSroW + 419443874U, // STRSroX + 419443874U, // STRSui + 2298590370U, // STRWpost + 2298590370U, // STRWpre + 419443874U, // STRWroW + 419443874U, // STRWroX + 419443874U, // STRWui + 2298590370U, // STRXpost + 2298590370U, // STRXpre + 419443874U, // STRXroW + 419443874U, // STRXroX + 419443874U, // STRXui + 419878050U, // STR_PXI + 455842U, // STR_ZA + 419878050U, // STR_ZXI + 419440508U, // STTRBi + 419442134U, // STTRHi + 419443879U, // STTRWi + 419443879U, // STTRXi + 419440539U, // STURBBi + 419443912U, // STURBi + 419443912U, // STURDi + 419442165U, // STURHHi + 419443912U, // STURHi + 419443912U, // STURQi + 419443912U, // STURSi + 419443912U, // STURWi + 419443912U, // STURXi + 403714925U, // STXPW + 403714925U, // STXPX + 403711929U, // STXRB + 403713555U, // STXRH + 403715328U, // STXRW + 403715328U, // STXRX + 419441435U, // STZ2GOffset + 2298587931U, // STZ2GPostIndex + 2298587931U, // STZ2GPreIndex + 419443016U, // STZGM + 419441498U, // STZGOffset + 2298587994U, // STZGPostIndex + 2298587994U, // STZGPreIndex + 403712802U, // SUBG + 940590744U, // SUBHNB_ZZZ_B + 1086359192U, // SUBHNB_ZZZ_H + 1209050776U, // SUBHNB_ZZZ_S + 1343248281U, // SUBHNT_ZZZ_B + 1087412121U, // SUBHNT_ZZZ_H + 537966489U, // SUBHNT_ZZZ_S + 272683395U, // SUBHNv2i64_v2i32 + 1483800931U, // SUBHNv2i64_v4i32 + 274780547U, // SUBHNv4i32_v4i16 + 1484849507U, // SUBHNv4i32_v8i16 + 1479606627U, // SUBHNv8i16_v16i8 + 277926275U, // SUBHNv8i16_v8i8 + 403714662U, // SUBP + 403715525U, // SUBPS + 1880118197U, // SUBR_ZI_B + 1209037749U, // SUBR_ZI_D + 1089508277U, // SUBR_ZI_H + 2014360501U, // SUBR_ZI_S + 1611682741U, // SUBR_ZPmZ_B + 1611690933U, // SUBR_ZPmZ_D + 1759548341U, // SUBR_ZPmZ_H + 1611707317U, // SUBR_ZPmZ_S + 403715390U, // SUBSWri + 403715390U, // SUBSWrs + 403715390U, // SUBSWrx + 403715390U, // SUBSXri + 403715390U, // SUBSXrs + 403715390U, // SUBSXrx + 403715390U, // SUBSXrx64 + 403712096U, // SUBWri + 403712096U, // SUBWrs + 403712096U, // SUBWrx + 403712096U, // SUBXri + 403712096U, // SUBXrs + 403712096U, // SUBXrx + 403712096U, // SUBXrx64 + 1880115296U, // SUB_ZI_B + 1209034848U, // SUB_ZI_D + 1089505376U, // SUB_ZI_H + 2014357600U, // SUB_ZI_S + 1611679840U, // SUB_ZPmZ_B + 1611688032U, // SUB_ZPmZ_D + 1759545440U, // SUB_ZPmZ_H + 1611704416U, // SUB_ZPmZ_S + 1880115296U, // SUB_ZZZ_B + 1209034848U, // SUB_ZZZ_D + 1089505376U, // SUB_ZZZ_H + 2014357600U, // SUB_ZZZ_S + 271632480U, // SUBv16i8 + 403712096U, // SUBv1i64 + 272681056U, // SUBv2i32 + 273729632U, // SUBv2i64 + 274778208U, // SUBv4i16 + 275826784U, // SUBv4i32 + 276875360U, // SUBv8i16 + 277923936U, // SUBv8i8 + 2819668010U, // SUDOT_ZZZI + 1483806762U, // SUDOTlanev16i8 + 1480661034U, // SUDOTlanev8i8 + 69264166U, // SUMOPA_MPPZZ_D + 70312742U, // SUMOPA_MPPZZ_S + 69268964U, // SUMOPS_MPPZZ_D + 70317540U, // SUMOPS_MPPZZ_S + 2014342848U, // SUNPKHI_ZZ_D + 868257472U, // SUNPKHI_ZZ_H + 940617408U, // SUNPKHI_ZZ_S + 2014343737U, // SUNPKLO_ZZ_D + 868258361U, // SUNPKLO_ZZ_H + 940618297U, // SUNPKLO_ZZ_S + 1611680268U, // SUQADD_ZPmZ_B + 1611688460U, // SUQADD_ZPmZ_D + 1759545868U, // SUQADD_ZPmZ_H + 1611704844U, // SUQADD_ZPmZ_S + 1479608844U, // SUQADDv16i8 + 2282859020U, // SUQADDv1i16 + 2282859020U, // SUQADDv1i32 + 2282859020U, // SUQADDv1i64 + 2282859020U, // SUQADDv1i8 + 1480657420U, // SUQADDv2i32 + 1481705996U, // SUQADDv2i64 + 1482754572U, // SUQADDv4i16 + 1483803148U, // SUQADDv4i32 + 1484851724U, // SUQADDv8i16 + 1485900300U, // SUQADDv8i8 + 125209U, // SVC + 1611768926U, // SWPAB + 1611770883U, // SWPAH + 1611769186U, // SWPALB + 1611771039U, // SWPALH + 1611771742U, // SWPALW + 1611771742U, // SWPALX + 1611768629U, // SWPAW + 1611768629U, // SWPAX + 1611769630U, // SWPB + 1611771256U, // SWPH + 1611769395U, // SWPLB + 1611771136U, // SWPLH + 1611772052U, // SWPLW + 1611772052U, // SWPLX + 1611772735U, // SWPW + 1611772735U, // SWPX + 1075283U, // SXTB_ZPmZ_D + 136349779U, // SXTB_ZPmZ_H + 1091667U, // SXTB_ZPmZ_S + 1076867U, // SXTH_ZPmZ_D + 1093251U, // SXTH_ZPmZ_S + 1079943U, // SXTW_ZPmZ_D + 403714260U, // SYSLxt + 1062428U, // SYSxt + 1068955U, // TBL_ZZZZ_B + 135294875U, // TBL_ZZZZ_D + 71339931U, // TBL_ZZZZ_H + 269528987U, // TBL_ZZZZ_S + 1068955U, // TBL_ZZZ_B + 135294875U, // TBL_ZZZ_D + 71339931U, // TBL_ZZZ_H + 269528987U, // TBL_ZZZ_S + 405852059U, // TBLv16i8Four + 405852059U, // TBLv16i8One + 405852059U, // TBLv16i8Three + 405852059U, // TBLv16i8Two + 412143515U, // TBLv8i8Four + 412143515U, // TBLv8i8One + 412143515U, // TBLv8i8Three + 412143515U, // TBLv8i8Two + 403716970U, // TBNZW + 403716970U, // TBNZX + 2819644113U, // TBX_ZZZ_B + 537950929U, // TBX_ZZZ_D + 1092655825U, // TBX_ZZZ_H + 672185041U, // TBX_ZZZ_S + 540089041U, // TBXv16i8Four + 540089041U, // TBXv16i8One + 540089041U, // TBXv16i8Three + 540089041U, // TBXv16i8Two + 546380497U, // TBXv8i8Four + 546380497U, // TBXv8i8One + 546380497U, // TBXv8i8Three + 546380497U, // TBXv8i8Two + 403716954U, // TBZW + 403716954U, // TBZX + 126962U, // TCANCEL + 7502U, // TCOMMIT + 1880113198U, // TRN1_PPP_B + 1209032750U, // TRN1_PPP_D + 1089503278U, // TRN1_PPP_H + 2014355502U, // TRN1_PPP_S + 1880113198U, // TRN1_ZZZ_B + 1209032750U, // TRN1_ZZZ_D + 1089503278U, // TRN1_ZZZ_H + 1096982574U, // TRN1_ZZZ_Q + 2014355502U, // TRN1_ZZZ_S + 271630382U, // TRN1v16i8 + 272678958U, // TRN1v2i32 + 273727534U, // TRN1v2i64 + 274776110U, // TRN1v4i16 + 275824686U, // TRN1v4i32 + 276873262U, // TRN1v8i16 + 277921838U, // TRN1v8i8 + 1880113562U, // TRN2_PPP_B + 1209033114U, // TRN2_PPP_D + 1089503642U, // TRN2_PPP_H + 2014355866U, // TRN2_PPP_S + 1880113562U, // TRN2_ZZZ_B + 1209033114U, // TRN2_ZZZ_D + 1089503642U, // TRN2_ZZZ_H + 1096982938U, // TRN2_ZZZ_Q + 2014355866U, // TRN2_ZZZ_S + 271630746U, // TRN2v16i8 + 272679322U, // TRN2v2i32 + 273727898U, // TRN2v2i64 + 274776474U, // TRN2v4i16 + 275825050U, // TRN2v4i32 + 276873626U, // TRN2v8i16 + 277922202U, // TRN2v8i8 + 157736U, // TSB + 14391U, // TSTART + 14413U, // TTEST + 672163095U, // UABALB_ZZZ_D + 1140884759U, // UABALB_ZZZ_H + 1343268119U, // UABALB_ZZZ_S + 672167598U, // UABALT_ZZZ_D + 1140889262U, // UABALT_ZZZ_H + 1343272622U, // UABALT_ZZZ_S + 1484849324U, // UABALv16i8_v8i16 + 1481707284U, // UABALv2i32_v2i64 + 1483804436U, // UABALv4i16_v4i32 + 1481703596U, // UABALv4i32_v2i64 + 1483800748U, // UABALv8i16_v4i32 + 1484853012U, // UABALv8i8_v8i16 + 2819637901U, // UABA_ZZZ_B + 537944717U, // UABA_ZZZ_D + 1092649613U, // UABA_ZZZ_H + 672178829U, // UABA_ZZZ_S + 1479606925U, // UABAv16i8 + 1480655501U, // UABAv2i32 + 1482752653U, // UABAv4i16 + 1483801229U, // UABAv4i32 + 1484849805U, // UABAv8i16 + 1485898381U, // UABAv8i8 + 2014340556U, // UABDLB_ZZZ_D + 1136690636U, // UABDLB_ZZZ_H + 940615116U, // UABDLB_ZZZ_S + 2014344959U, // UABDLT_ZZZ_D + 1136695039U, // UABDLT_ZZZ_H + 940619519U, // UABDLT_ZZZ_S + 276873454U, // UABDLv16i8_v8i16 + 273731525U, // UABDLv2i32_v2i64 + 275828677U, // UABDLv4i16_v4i32 + 273727726U, // UABDLv4i32_v2i64 + 275824878U, // UABDLv8i16_v4i32 + 276877253U, // UABDLv8i8_v8i16 + 1611680142U, // UABD_ZPmZ_B + 1611688334U, // UABD_ZPmZ_D + 1759545742U, // UABD_ZPmZ_H + 1611704718U, // UABD_ZPmZ_S + 271632782U, // UABDv16i8 + 272681358U, // UABDv2i32 + 274778510U, // UABDv4i16 + 275827086U, // UABDv4i32 + 276875662U, // UABDv8i16 + 277924238U, // UABDv8i8 + 1611690668U, // UADALP_ZPmZ_D + 1759548076U, // UADALP_ZPmZ_H + 1611707052U, // UADALP_ZPmZ_S + 1484853932U, // UADALPv16i8_v8i16 + 1544622764U, // UADALPv2i32_v1i64 + 1480659628U, // UADALPv4i16_v2i32 + 1481708204U, // UADALPv4i32_v2i64 + 1483805356U, // UADALPv8i16_v4i32 + 1482756780U, // UADALPv8i8_v4i16 + 2014340581U, // UADDLB_ZZZ_D + 1136690661U, // UADDLB_ZZZ_H + 940615141U, // UADDLB_ZZZ_S + 276878012U, // UADDLPv16i8_v8i16 + 336646844U, // UADDLPv2i32_v1i64 + 272683708U, // UADDLPv4i16_v2i32 + 273732284U, // UADDLPv4i32_v2i64 + 275829436U, // UADDLPv8i16_v4i32 + 274780860U, // UADDLPv8i8_v4i16 + 2014344975U, // UADDLT_ZZZ_D + 1136695055U, // UADDLT_ZZZ_H + 940619535U, // UADDLT_ZZZ_S + 269498633U, // UADDLVv16i8v + 269498633U, // UADDLVv4i16v + 269498633U, // UADDLVv4i32v + 269498633U, // UADDLVv8i16v + 269498633U, // UADDLVv8i8v + 276873470U, // UADDLv16i8_v8i16 + 273731563U, // UADDLv2i32_v2i64 + 275828715U, // UADDLv4i16_v4i32 + 273727742U, // UADDLv4i32_v2i64 + 275824894U, // UADDLv8i16_v4i32 + 276877291U, // UADDLv8i8_v8i16 + 872503517U, // UADDV_VPZ_B + 823220445U, // UADDV_VPZ_D + 824269021U, // UADDV_VPZ_H + 819026141U, // UADDV_VPZ_S + 1209034926U, // UADDWB_ZZZ_D + 1089505454U, // UADDWB_ZZZ_H + 2014357678U, // UADDWB_ZZZ_S + 1209038978U, // UADDWT_ZZZ_D + 1089509506U, // UADDWT_ZZZ_H + 2014361730U, // UADDWT_ZZZ_S + 276873744U, // UADDWv16i8_v8i16 + 273734146U, // UADDWv2i32_v2i64 + 275831298U, // UADDWv4i16_v4i32 + 273728016U, // UADDWv4i32_v2i64 + 275825168U, // UADDWv8i16_v4i32 + 276879874U, // UADDWv8i8_v8i16 + 403714352U, // UBFMWri + 403714352U, // UBFMXri + 1880117964U, // UCLAMP_ZZZ_B + 1209037516U, // UCLAMP_ZZZ_D + 1089508044U, // UCLAMP_ZZZ_H + 2014360268U, // UCLAMP_ZZZ_S + 403712782U, // UCVTFSWDri + 403712782U, // UCVTFSWHri + 403712782U, // UCVTFSWSri + 403712782U, // UCVTFSXDri + 403712782U, // UCVTFSXHri + 403712782U, // UCVTFSXSri + 403712782U, // UCVTFUWDri + 403712782U, // UCVTFUWHri + 403712782U, // UCVTFUWSri + 403712782U, // UCVTFUXDri + 403712782U, // UCVTFUXHri + 403712782U, // UCVTFUXSri + 1075982U, // UCVTF_ZPmZ_DtoD + 270568206U, // UCVTF_ZPmZ_DtoH + 1092366U, // UCVTF_ZPmZ_DtoS + 136350478U, // UCVTF_ZPmZ_HtoH + 1075982U, // UCVTF_ZPmZ_StoD + 2418051854U, // UCVTF_ZPmZ_StoH + 1092366U, // UCVTF_ZPmZ_StoS + 403712782U, // UCVTFd + 403712782U, // UCVTFh + 403712782U, // UCVTFs + 403712782U, // UCVTFv1i16 + 403712782U, // UCVTFv1i32 + 403712782U, // UCVTFv1i64 + 272681742U, // UCVTFv2f32 + 273730318U, // UCVTFv2f64 + 272681742U, // UCVTFv2i32_shift + 273730318U, // UCVTFv2i64_shift + 274778894U, // UCVTFv4f16 + 275827470U, // UCVTFv4f32 + 274778894U, // UCVTFv4i16_shift + 275827470U, // UCVTFv4i32_shift + 276876046U, // UCVTFv8f16 + 276876046U, // UCVTFv8i16_shift + 10999U, // UDF + 1611691228U, // UDIVR_ZPmZ_D + 1611707612U, // UDIVR_ZPmZ_S + 403716347U, // UDIVWr + 403716347U, // UDIVXr + 1611692283U, // UDIV_ZPmZ_D + 1611708667U, // UDIV_ZPmZ_S + 1343256619U, // UDOT_ZZZI_D + 2819668011U, // UDOT_ZZZI_S + 1343256619U, // UDOT_ZZZ_D + 2819668011U, // UDOT_ZZZ_S + 1483806763U, // UDOTlanev16i8 + 1480661035U, // UDOTlanev8i8 + 1483806763U, // UDOTv16i8 + 1480661035U, // UDOTv8i8 + 1611680238U, // UHADD_ZPmZ_B + 1611688430U, // UHADD_ZPmZ_D + 1759545838U, // UHADD_ZPmZ_H + 1611704814U, // UHADD_ZPmZ_S + 271632878U, // UHADDv16i8 + 272681454U, // UHADDv2i32 + 274778606U, // UHADDv4i16 + 275827182U, // UHADDv4i32 + 276875758U, // UHADDv8i16 + 277924334U, // UHADDv8i8 + 1611682755U, // UHSUBR_ZPmZ_B + 1611690947U, // UHSUBR_ZPmZ_D + 1759548355U, // UHSUBR_ZPmZ_H + 1611707331U, // UHSUBR_ZPmZ_S + 1611679852U, // UHSUB_ZPmZ_B + 1611688044U, // UHSUB_ZPmZ_D + 1759545452U, // UHSUB_ZPmZ_H + 1611704428U, // UHSUB_ZPmZ_S + 271632492U, // UHSUBv16i8 + 272681068U, // UHSUBv2i32 + 274778220U, // UHSUBv4i16 + 275826796U, // UHSUBv4i32 + 276875372U, // UHSUBv8i16 + 277923948U, // UHSUBv8i8 + 403714012U, // UMADDLrrr + 1611682649U, // UMAXP_ZPmZ_B + 1611690841U, // UMAXP_ZPmZ_D + 1759548249U, // UMAXP_ZPmZ_H + 1611707225U, // UMAXP_ZPmZ_S + 271635289U, // UMAXPv16i8 + 272683865U, // UMAXPv2i32 + 274781017U, // UMAXPv4i16 + 275829593U, // UMAXPv4i32 + 276878169U, // UMAXPv8i16 + 277926745U, // UMAXPv8i8 + 80229U, // UMAXV_VPZ_B + 823220581U, // UMAXV_VPZ_D + 824277349U, // UMAXV_VPZ_H + 819042661U, // UMAXV_VPZ_S + 269498725U, // UMAXVv16i8v + 269498725U, // UMAXVv4i16v + 269498725U, // UMAXVv4i32v + 269498725U, // UMAXVv8i16v + 269498725U, // UMAXVv8i8v + 1880120011U, // UMAX_ZI_B + 1209039563U, // UMAX_ZI_D + 1089510091U, // UMAX_ZI_H + 2014362315U, // UMAX_ZI_S + 1611684555U, // UMAX_ZPmZ_B + 1611692747U, // UMAX_ZPmZ_D + 1759550155U, // UMAX_ZPmZ_H + 1611709131U, // UMAX_ZPmZ_S + 271637195U, // UMAXv16i8 + 272685771U, // UMAXv2i32 + 274782923U, // UMAXv4i16 + 275831499U, // UMAXv4i32 + 276880075U, // UMAXv8i16 + 277928651U, // UMAXv8i8 + 1611682567U, // UMINP_ZPmZ_B + 1611690759U, // UMINP_ZPmZ_D + 1759548167U, // UMINP_ZPmZ_H + 1611707143U, // UMINP_ZPmZ_S + 271635207U, // UMINPv16i8 + 272683783U, // UMINPv2i32 + 274780935U, // UMINPv4i16 + 275829511U, // UMINPv4i32 + 276878087U, // UMINPv8i16 + 277926663U, // UMINPv8i8 + 80177U, // UMINV_VPZ_B + 823220529U, // UMINV_VPZ_D + 824277297U, // UMINV_VPZ_H + 819042609U, // UMINV_VPZ_S + 269498673U, // UMINVv16i8v + 269498673U, // UMINVv4i16v + 269498673U, // UMINVv4i32v + 269498673U, // UMINVv8i16v + 269498673U, // UMINVv8i8v + 1880117666U, // UMIN_ZI_B + 1209037218U, // UMIN_ZI_D + 1089507746U, // UMIN_ZI_H + 2014359970U, // UMIN_ZI_S + 1611682210U, // UMIN_ZPmZ_B + 1611690402U, // UMIN_ZPmZ_D + 1759547810U, // UMIN_ZPmZ_H + 1611706786U, // UMIN_ZPmZ_S + 271634850U, // UMINv16i8 + 272683426U, // UMINv2i32 + 274780578U, // UMINv4i16 + 275829154U, // UMINv4i32 + 276877730U, // UMINv8i16 + 277926306U, // UMINv8i8 + 672163140U, // UMLALB_ZZZI_D + 1343268164U, // UMLALB_ZZZI_S + 672163140U, // UMLALB_ZZZ_D + 1140884804U, // UMLALB_ZZZ_H + 1343268164U, // UMLALB_ZZZ_S + 672167633U, // UMLALT_ZZZI_D + 1343272657U, // UMLALT_ZZZI_S + 672167633U, // UMLALT_ZZZ_D + 1140889297U, // UMLALT_ZZZ_H + 1343272657U, // UMLALT_ZZZ_S + 1484849358U, // UMLALv16i8_v8i16 + 1481707323U, // UMLALv2i32_indexed + 1481707323U, // UMLALv2i32_v2i64 + 1483804475U, // UMLALv4i16_indexed + 1483804475U, // UMLALv4i16_v4i32 + 1481703630U, // UMLALv4i32_indexed + 1481703630U, // UMLALv4i32_v2i64 + 1483800782U, // UMLALv8i16_indexed + 1483800782U, // UMLALv8i16_v4i32 + 1484853051U, // UMLALv8i8_v8i16 + 672163437U, // UMLSLB_ZZZI_D + 1343268461U, // UMLSLB_ZZZI_S + 672163437U, // UMLSLB_ZZZ_D + 1140885101U, // UMLSLB_ZZZ_H + 1343268461U, // UMLSLB_ZZZ_S + 672167807U, // UMLSLT_ZZZI_D + 1343272831U, // UMLSLT_ZZZI_S + 672167807U, // UMLSLT_ZZZ_D + 1140889471U, // UMLSLT_ZZZ_H + 1343272831U, // UMLSLT_ZZZ_S + 1484849490U, // UMLSLv16i8_v8i16 + 1481707725U, // UMLSLv2i32_indexed + 1481707725U, // UMLSLv2i32_v2i64 + 1483804877U, // UMLSLv4i16_indexed + 1483804877U, // UMLSLv4i16_v4i32 + 1481703762U, // UMLSLv4i32_indexed + 1481703762U, // UMLSLv4i32_v2i64 + 1483800914U, // UMLSLv8i16_indexed + 1483800914U, // UMLSLv8i16_v4i32 + 1484853453U, // UMLSLv8i8_v8i16 + 1483801327U, // UMMLA + 2819662575U, // UMMLA_ZZZ + 69264167U, // UMOPA_MPPZZ_D + 70312743U, // UMOPA_MPPZZ_S + 69268965U, // UMOPS_MPPZZ_D + 70317541U, // UMOPS_MPPZZ_S + 269498699U, // UMOVvi16 + 269498699U, // UMOVvi16_idx0 + 269498699U, // UMOVvi32 + 269498699U, // UMOVvi32_idx0 + 269498699U, // UMOVvi64 + 269498699U, // UMOVvi64_idx0 + 269498699U, // UMOVvi8 + 269498699U, // UMOVvi8_idx0 + 403713960U, // UMSUBLrrr + 1611681091U, // UMULH_ZPmZ_B + 1611689283U, // UMULH_ZPmZ_D + 1759546691U, // UMULH_ZPmZ_H + 1611705667U, // UMULH_ZPmZ_S + 1880116547U, // UMULH_ZZZ_B + 1209036099U, // UMULH_ZZZ_D + 1089506627U, // UMULH_ZZZ_H + 2014358851U, // UMULH_ZZZ_S + 403713347U, // UMULHrr + 2014340631U, // UMULLB_ZZZI_D + 940615191U, // UMULLB_ZZZI_S + 2014340631U, // UMULLB_ZZZ_D + 1136690711U, // UMULLB_ZZZ_H + 940615191U, // UMULLB_ZZZ_S + 2014345039U, // UMULLT_ZZZI_D + 940619599U, // UMULLT_ZZZI_S + 2014345039U, // UMULLT_ZZZ_D + 1136695119U, // UMULLT_ZZZ_H + 940619599U, // UMULLT_ZZZ_S + 276873520U, // UMULLv16i8_v8i16 + 273731693U, // UMULLv2i32_indexed + 273731693U, // UMULLv2i32_v2i64 + 275828845U, // UMULLv4i16_indexed + 275828845U, // UMULLv4i16_v4i32 + 273727792U, // UMULLv4i32_indexed + 273727792U, // UMULLv4i32_v2i64 + 275824944U, // UMULLv8i16_indexed + 275824944U, // UMULLv8i16_v4i32 + 276877421U, // UMULLv8i8_v8i16 + 1880115725U, // UQADD_ZI_B + 1209035277U, // UQADD_ZI_D + 1089505805U, // UQADD_ZI_H + 2014358029U, // UQADD_ZI_S + 1611680269U, // UQADD_ZPmZ_B + 1611688461U, // UQADD_ZPmZ_D + 1759545869U, // UQADD_ZPmZ_H + 1611704845U, // UQADD_ZPmZ_S + 1880115725U, // UQADD_ZZZ_B + 1209035277U, // UQADD_ZZZ_D + 1089505805U, // UQADD_ZZZ_H + 2014358029U, // UQADD_ZZZ_S + 271632909U, // UQADDv16i8 + 403712525U, // UQADDv1i16 + 403712525U, // UQADDv1i32 + 403712525U, // UQADDv1i64 + 403712525U, // UQADDv1i8 + 272681485U, // UQADDv2i32 + 273730061U, // UQADDv2i64 + 274778637U, // UQADDv4i16 + 275827213U, // UQADDv4i32 + 276875789U, // UQADDv8i16 + 277924365U, // UQADDv8i8 + 3490718912U, // UQDECB_WPiI + 3490718912U, // UQDECB_XPiI + 3490720163U, // UQDECD_WPiI + 3490720163U, // UQDECD_XPiI + 3490736547U, // UQDECD_ZPiI + 3490720849U, // UQDECH_WPiI + 3490720849U, // UQDECH_XPiI + 19958865U, // UQDECH_ZPiI + 1880109684U, // UQDECP_WP_B + 1209021044U, // UQDECP_WP_D + 940585588U, // UQDECP_WP_H + 2014327412U, // UQDECP_WP_S + 1880109684U, // UQDECP_XP_B + 1209021044U, // UQDECP_XP_D + 940585588U, // UQDECP_XP_H + 2014327412U, // UQDECP_XP_S + 537948788U, // UQDECP_ZP_D + 824218228U, // UQDECP_ZP_H + 672182900U, // UQDECP_ZP_S + 3490724323U, // UQDECW_WPiI + 3490724323U, // UQDECW_XPiI + 3490757091U, // UQDECW_ZPiI + 3490718928U, // UQINCB_WPiI + 3490718928U, // UQINCB_XPiI + 3490720179U, // UQINCD_WPiI + 3490720179U, // UQINCD_XPiI + 3490736563U, // UQINCD_ZPiI + 3490720865U, // UQINCH_WPiI + 3490720865U, // UQINCH_XPiI + 19958881U, // UQINCH_ZPiI + 1880109700U, // UQINCP_WP_B + 1209021060U, // UQINCP_WP_D + 940585604U, // UQINCP_WP_H + 2014327428U, // UQINCP_WP_S + 1880109700U, // UQINCP_XP_B + 1209021060U, // UQINCP_XP_D + 940585604U, // UQINCP_XP_H + 2014327428U, // UQINCP_XP_S + 537948804U, // UQINCP_ZP_D + 824218244U, // UQINCP_ZP_H + 672182916U, // UQINCP_ZP_S + 3490724339U, // UQINCW_WPiI + 3490724339U, // UQINCW_XPiI + 3490757107U, // UQINCW_ZPiI + 1611682866U, // UQRSHLR_ZPmZ_B + 1611691058U, // UQRSHLR_ZPmZ_D + 1759548466U, // UQRSHLR_ZPmZ_H + 1611707442U, // UQRSHLR_ZPmZ_S + 1611681830U, // UQRSHL_ZPmZ_B + 1611690022U, // UQRSHL_ZPmZ_D + 1759547430U, // UQRSHL_ZPmZ_H + 1611706406U, // UQRSHL_ZPmZ_S + 271634470U, // UQRSHLv16i8 + 403714086U, // UQRSHLv1i16 + 403714086U, // UQRSHLv1i32 + 403714086U, // UQRSHLv1i64 + 403714086U, // UQRSHLv1i8 + 272683046U, // UQRSHLv2i32 + 273731622U, // UQRSHLv2i64 + 274780198U, // UQRSHLv4i16 + 275828774U, // UQRSHLv4i32 + 276877350U, // UQRSHLv8i16 + 277925926U, // UQRSHLv8i8 + 940590807U, // UQRSHRNB_ZZI_B + 1086359255U, // UQRSHRNB_ZZI_H + 1209050839U, // UQRSHRNB_ZZI_S + 1343248332U, // UQRSHRNT_ZZI_B + 1087412172U, // UQRSHRNT_ZZI_H + 537966540U, // UQRSHRNT_ZZI_S + 403714514U, // UQRSHRNb + 403714514U, // UQRSHRNh + 403714514U, // UQRSHRNs + 1479606672U, // UQRSHRNv16i8_shift + 272683474U, // UQRSHRNv2i32_shift + 274780626U, // UQRSHRNv4i16_shift + 1483800976U, // UQRSHRNv4i32_shift + 1484849552U, // UQRSHRNv8i16_shift + 277926354U, // UQRSHRNv8i8_shift + 1611682849U, // UQSHLR_ZPmZ_B + 1611691041U, // UQSHLR_ZPmZ_D + 1759548449U, // UQSHLR_ZPmZ_H + 1611707425U, // UQSHLR_ZPmZ_S + 1611681815U, // UQSHL_ZPmI_B + 1611690007U, // UQSHL_ZPmI_D + 1759547415U, // UQSHL_ZPmI_H + 1611706391U, // UQSHL_ZPmI_S + 1611681815U, // UQSHL_ZPmZ_B + 1611690007U, // UQSHL_ZPmZ_D + 1759547415U, // UQSHL_ZPmZ_H + 1611706391U, // UQSHL_ZPmZ_S + 403714071U, // UQSHLb + 403714071U, // UQSHLd + 403714071U, // UQSHLh + 403714071U, // UQSHLs + 271634455U, // UQSHLv16i8 + 271634455U, // UQSHLv16i8_shift + 403714071U, // UQSHLv1i16 + 403714071U, // UQSHLv1i32 + 403714071U, // UQSHLv1i64 + 403714071U, // UQSHLv1i8 + 272683031U, // UQSHLv2i32 + 272683031U, // UQSHLv2i32_shift + 273731607U, // UQSHLv2i64 + 273731607U, // UQSHLv2i64_shift + 274780183U, // UQSHLv4i16 + 274780183U, // UQSHLv4i16_shift + 275828759U, // UQSHLv4i32 + 275828759U, // UQSHLv4i32_shift + 276877335U, // UQSHLv8i16 + 276877335U, // UQSHLv8i16_shift + 277925911U, // UQSHLv8i8 + 277925911U, // UQSHLv8i8_shift + 940590788U, // UQSHRNB_ZZI_B + 1086359236U, // UQSHRNB_ZZI_H + 1209050820U, // UQSHRNB_ZZI_S + 1343248313U, // UQSHRNT_ZZI_B + 1087412153U, // UQSHRNT_ZZI_H + 537966521U, // UQSHRNT_ZZI_S + 403714497U, // UQSHRNb + 403714497U, // UQSHRNh + 403714497U, // UQSHRNs + 1479606653U, // UQSHRNv16i8_shift + 272683457U, // UQSHRNv2i32_shift + 274780609U, // UQSHRNv4i16_shift + 1483800957U, // UQSHRNv4i32_shift + 1484849533U, // UQSHRNv8i16_shift + 277926337U, // UQSHRNv8i8_shift + 1611682771U, // UQSUBR_ZPmZ_B + 1611690963U, // UQSUBR_ZPmZ_D + 1759548371U, // UQSUBR_ZPmZ_H + 1611707347U, // UQSUBR_ZPmZ_S + 1880115337U, // UQSUB_ZI_B + 1209034889U, // UQSUB_ZI_D + 1089505417U, // UQSUB_ZI_H + 2014357641U, // UQSUB_ZI_S + 1611679881U, // UQSUB_ZPmZ_B + 1611688073U, // UQSUB_ZPmZ_D + 1759545481U, // UQSUB_ZPmZ_H + 1611704457U, // UQSUB_ZPmZ_S + 1880115337U, // UQSUB_ZZZ_B + 1209034889U, // UQSUB_ZZZ_D + 1089505417U, // UQSUB_ZZZ_H + 2014357641U, // UQSUB_ZZZ_S + 271632521U, // UQSUBv16i8 + 403712137U, // UQSUBv1i16 + 403712137U, // UQSUBv1i32 + 403712137U, // UQSUBv1i64 + 403712137U, // UQSUBv1i8 + 272681097U, // UQSUBv2i32 + 273729673U, // UQSUBv2i64 + 274778249U, // UQSUBv4i16 + 275826825U, // UQSUBv4i32 + 276875401U, // UQSUBv8i16 + 277923977U, // UQSUBv8i8 + 940590825U, // UQXTNB_ZZ_B + 817923817U, // UQXTNB_ZZ_H + 1209050857U, // UQXTNB_ZZ_S + 1343248359U, // UQXTNT_ZZ_B + 818976743U, // UQXTNT_ZZ_H + 537966567U, // UQXTNT_ZZ_S + 1479606705U, // UQXTNv16i8 + 403714551U, // UQXTNv1i16 + 403714551U, // UQXTNv1i32 + 403714551U, // UQXTNv1i8 + 272683511U, // UQXTNv2i32 + 274780663U, // UQXTNv4i16 + 1483801009U, // UQXTNv4i32 + 1484849585U, // UQXTNv8i16 + 277926391U, // UQXTNv8i8 + 1092281U, // URECPE_ZPmZ_S + 272681657U, // URECPEv2i32 + 275827385U, // URECPEv4i32 + 1611680223U, // URHADD_ZPmZ_B + 1611688415U, // URHADD_ZPmZ_D + 1759545823U, // URHADD_ZPmZ_H + 1611704799U, // URHADD_ZPmZ_S + 271632863U, // URHADDv16i8 + 272681439U, // URHADDv2i32 + 274778591U, // URHADDv4i16 + 275827167U, // URHADDv4i32 + 276875743U, // URHADDv8i16 + 277924319U, // URHADDv8i8 + 1611682883U, // URSHLR_ZPmZ_B + 1611691075U, // URSHLR_ZPmZ_D + 1759548483U, // URSHLR_ZPmZ_H + 1611707459U, // URSHLR_ZPmZ_S + 1611681845U, // URSHL_ZPmZ_B + 1611690037U, // URSHL_ZPmZ_D + 1759547445U, // URSHL_ZPmZ_H + 1611706421U, // URSHL_ZPmZ_S + 271634485U, // URSHLv16i8 + 403714101U, // URSHLv1i64 + 272683061U, // URSHLv2i32 + 273731637U, // URSHLv2i64 + 274780213U, // URSHLv4i16 + 275828789U, // URSHLv4i32 + 276877365U, // URSHLv8i16 + 277925941U, // URSHLv8i8 + 1611682810U, // URSHR_ZPmI_B + 1611691002U, // URSHR_ZPmI_D + 1759548410U, // URSHR_ZPmI_H + 1611707386U, // URSHR_ZPmI_S + 403715066U, // URSHRd + 271635450U, // URSHRv16i8_shift + 272684026U, // URSHRv2i32_shift + 273732602U, // URSHRv2i64_shift + 274781178U, // URSHRv4i16_shift + 275829754U, // URSHRv4i32_shift + 276878330U, // URSHRv8i16_shift + 277926906U, // URSHRv8i8_shift + 1092327U, // URSQRTE_ZPmZ_S + 272681703U, // URSQRTEv2i32 + 275827431U, // URSQRTEv4i32 + 2819638105U, // URSRA_ZZI_B + 537944921U, // URSRA_ZZI_D + 1092649817U, // URSRA_ZZI_H + 672179033U, // URSRA_ZZI_S + 2282857305U, // URSRAd + 1479607129U, // URSRAv16i8_shift + 1480655705U, // URSRAv2i32_shift + 1481704281U, // URSRAv2i64_shift + 1482752857U, // URSRAv4i16_shift + 1483801433U, // URSRAv4i32_shift + 1484850009U, // URSRAv8i16_shift + 1485898585U, // URSRAv8i8_shift + 2819668003U, // USDOT_ZZZ + 2819668003U, // USDOT_ZZZI + 1483806755U, // USDOTlanev16i8 + 1480661027U, // USDOTlanev8i8 + 1483806755U, // USDOTv16i8 + 1480661027U, // USDOTv8i8 + 2014340597U, // USHLLB_ZZI_D + 1136690677U, // USHLLB_ZZI_H + 940615157U, // USHLLB_ZZI_S + 2014345005U, // USHLLT_ZZI_D + 1136695085U, // USHLLT_ZZI_H + 940619565U, // USHLLT_ZZI_S + 276873486U, // USHLLv16i8_shift + 273731663U, // USHLLv2i32_shift + 275828815U, // USHLLv4i16_shift + 273727758U, // USHLLv4i32_shift + 275824910U, // USHLLv8i16_shift + 276877391U, // USHLLv8i8_shift + 271634498U, // USHLv16i8 + 403714114U, // USHLv1i64 + 272683074U, // USHLv2i32 + 273731650U, // USHLv2i64 + 274780226U, // USHLv4i16 + 275828802U, // USHLv4i32 + 276877378U, // USHLv8i16 + 277925954U, // USHLv8i8 + 403715079U, // USHRd + 271635463U, // USHRv16i8_shift + 272684039U, // USHRv2i32_shift + 273732615U, // USHRv2i64_shift + 274781191U, // USHRv4i16_shift + 275829767U, // USHRv4i32_shift + 276878343U, // USHRv8i16_shift + 277926919U, // USHRv8i8_shift + 1483801319U, // USMMLA + 2819662567U, // USMMLA_ZZZ + 69264158U, // USMOPA_MPPZZ_D + 70312734U, // USMOPA_MPPZZ_S + 69268956U, // USMOPS_MPPZZ_D + 70317532U, // USMOPS_MPPZZ_S + 1611680260U, // USQADD_ZPmZ_B + 1611688452U, // USQADD_ZPmZ_D + 1759545860U, // USQADD_ZPmZ_H + 1611704836U, // USQADD_ZPmZ_S + 1479608836U, // USQADDv16i8 + 2282859012U, // USQADDv1i16 + 2282859012U, // USQADDv1i32 + 2282859012U, // USQADDv1i64 + 2282859012U, // USQADDv1i8 + 1480657412U, // USQADDv2i32 + 1481705988U, // USQADDv2i64 + 1482754564U, // USQADDv4i16 + 1483803140U, // USQADDv4i32 + 1484851716U, // USQADDv8i16 + 1485900292U, // USQADDv8i8 + 2819638118U, // USRA_ZZI_B + 537944934U, // USRA_ZZI_D + 1092649830U, // USRA_ZZI_H + 672179046U, // USRA_ZZI_S + 2282857318U, // USRAd + 1479607142U, // USRAv16i8_shift + 1480655718U, // USRAv2i32_shift + 1481704294U, // USRAv2i64_shift + 1482752870U, // USRAv4i16_shift + 1483801446U, // USRAv4i32_shift + 1484850022U, // USRAv8i16_shift + 1485898598U, // USRAv8i8_shift + 2014340526U, // USUBLB_ZZZ_D + 1136690606U, // USUBLB_ZZZ_H + 940615086U, // USUBLB_ZZZ_S + 2014344929U, // USUBLT_ZZZ_D + 1136695009U, // USUBLT_ZZZ_H + 940619489U, // USUBLT_ZZZ_S + 276873438U, // USUBLv16i8_v8i16 + 273731511U, // USUBLv2i32_v2i64 + 275828663U, // USUBLv4i16_v4i32 + 273727710U, // USUBLv4i32_v2i64 + 275824862U, // USUBLv8i16_v4i32 + 276877239U, // USUBLv8i8_v8i16 + 1209034910U, // USUBWB_ZZZ_D + 1089505438U, // USUBWB_ZZZ_H + 2014357662U, // USUBWB_ZZZ_S + 1209038962U, // USUBWT_ZZZ_D + 1089509490U, // USUBWT_ZZZ_H + 2014361714U, // USUBWT_ZZZ_S + 276873728U, // USUBWv16i8_v8i16 + 273734091U, // USUBWv2i32_v2i64 + 275831243U, // USUBWv4i16_v4i32 + 273728000U, // USUBWv4i32_v2i64 + 275825152U, // USUBWv8i16_v4i32 + 276879819U, // USUBWv8i8_v8i16 + 2014342857U, // UUNPKHI_ZZ_D + 868257481U, // UUNPKHI_ZZ_H + 940617417U, // UUNPKHI_ZZ_S + 2014343746U, // UUNPKLO_ZZ_D + 868258370U, // UUNPKLO_ZZ_H + 940618306U, // UUNPKLO_ZZ_S + 1075289U, // UXTB_ZPmZ_D + 136349785U, // UXTB_ZPmZ_H + 1091673U, // UXTB_ZPmZ_S + 1076873U, // UXTH_ZPmZ_D + 1093257U, // UXTH_ZPmZ_S + 1079949U, // UXTW_ZPmZ_D + 1880113210U, // UZP1_PPP_B + 1209032762U, // UZP1_PPP_D + 1089503290U, // UZP1_PPP_H + 2014355514U, // UZP1_PPP_S + 1880113210U, // UZP1_ZZZ_B + 1209032762U, // UZP1_ZZZ_D + 1089503290U, // UZP1_ZZZ_H + 1096982586U, // UZP1_ZZZ_Q + 2014355514U, // UZP1_ZZZ_S + 271630394U, // UZP1v16i8 + 272678970U, // UZP1v2i32 + 273727546U, // UZP1v2i64 + 274776122U, // UZP1v4i16 + 275824698U, // UZP1v4i32 + 276873274U, // UZP1v8i16 + 277921850U, // UZP1v8i8 + 1880113638U, // UZP2_PPP_B + 1209033190U, // UZP2_PPP_D + 1089503718U, // UZP2_PPP_H + 2014355942U, // UZP2_PPP_S + 1880113638U, // UZP2_ZZZ_B + 1209033190U, // UZP2_ZZZ_D + 1089503718U, // UZP2_ZZZ_H + 1096983014U, // UZP2_ZZZ_Q + 2014355942U, // UZP2_ZZZ_S + 271630822U, // UZP2v16i8 + 272679398U, // UZP2v2i32 + 273727974U, // UZP2v2i64 + 274776550U, // UZP2v4i16 + 275825126U, // UZP2v4i32 + 276873702U, // UZP2v8i16 + 277922278U, // UZP2v8i8 + 13930U, // WFET + 13984U, // WFIT + 403720804U, // WHILEGE_PWW_B + 403728996U, // WHILEGE_PWW_D + 1095797348U, // WHILEGE_PWW_H + 403745380U, // WHILEGE_PWW_S + 403720804U, // WHILEGE_PXX_B + 403728996U, // WHILEGE_PXX_D + 1095797348U, // WHILEGE_PXX_H + 403745380U, // WHILEGE_PXX_S + 403723907U, // WHILEGT_PWW_B + 403732099U, // WHILEGT_PWW_D + 1095800451U, // WHILEGT_PWW_H + 403748483U, // WHILEGT_PWW_S + 403723907U, // WHILEGT_PXX_B + 403732099U, // WHILEGT_PXX_D + 1095800451U, // WHILEGT_PXX_H + 403748483U, // WHILEGT_PXX_S + 403721902U, // WHILEHI_PWW_B + 403730094U, // WHILEHI_PWW_D + 1095798446U, // WHILEHI_PWW_H + 403746478U, // WHILEHI_PWW_S + 403721902U, // WHILEHI_PXX_B + 403730094U, // WHILEHI_PXX_D + 1095798446U, // WHILEHI_PXX_H + 403746478U, // WHILEHI_PXX_S + 403723627U, // WHILEHS_PWW_B + 403731819U, // WHILEHS_PWW_D + 1095800171U, // WHILEHS_PWW_H + 403748203U, // WHILEHS_PWW_S + 403723627U, // WHILEHS_PXX_B + 403731819U, // WHILEHS_PXX_D + 1095800171U, // WHILEHS_PXX_H + 403748203U, // WHILEHS_PXX_S + 403720835U, // WHILELE_PWW_B + 403729027U, // WHILELE_PWW_D + 1095797379U, // WHILELE_PWW_H + 403745411U, // WHILELE_PWW_S + 403720835U, // WHILELE_PXX_B + 403729027U, // WHILELE_PXX_D + 1095797379U, // WHILELE_PXX_H + 403745411U, // WHILELE_PXX_S + 403722791U, // WHILELO_PWW_B + 403730983U, // WHILELO_PWW_D + 1095799335U, // WHILELO_PWW_H + 403747367U, // WHILELO_PWW_S + 403722791U, // WHILELO_PXX_B + 403730983U, // WHILELO_PXX_D + 1095799335U, // WHILELO_PXX_H + 403747367U, // WHILELO_PXX_S + 403723654U, // WHILELS_PWW_B + 403731846U, // WHILELS_PWW_D + 1095800198U, // WHILELS_PWW_H + 403748230U, // WHILELS_PWW_S + 403723654U, // WHILELS_PXX_B + 403731846U, // WHILELS_PXX_D + 1095800198U, // WHILELS_PXX_H + 403748230U, // WHILELS_PXX_S + 403724055U, // WHILELT_PWW_B + 403732247U, // WHILELT_PWW_D + 1095800599U, // WHILELT_PWW_H + 403748631U, // WHILELT_PWW_S + 403724055U, // WHILELT_PXX_B + 403732247U, // WHILELT_PXX_D + 1095800599U, // WHILELT_PXX_H + 403748631U, // WHILELT_PXX_S + 403724838U, // WHILERW_PXX_B + 403733030U, // WHILERW_PXX_D + 1095801382U, // WHILERW_PXX_H + 403749414U, // WHILERW_PXX_S + 403723491U, // WHILEWR_PXX_B + 403731683U, // WHILEWR_PXX_D + 1095800035U, // WHILEWR_PXX_H + 403748067U, // WHILEWR_PXX_S + 21484U, // WRFFR + 7440U, // XAFLAG + 273732527U, // XAR + 1880118191U, // XAR_ZZZI_B + 1209037743U, // XAR_ZZZI_D + 1089508271U, // XAR_ZZZI_H + 2014360495U, // XAR_ZZZI_S + 10644U, // XPACD + 11943U, // XPACI + 7275U, // XPACLRI + 1479606699U, // XTNv16i8 + 272683506U, // XTNv2i32 + 274780658U, // XTNv4i16 + 1483801003U, // XTNv4i32 + 1484849579U, // XTNv8i16 + 277926386U, // XTNv8i8 + 537170U, // ZERO_M + 1880113204U, // ZIP1_PPP_B + 1209032756U, // ZIP1_PPP_D + 1089503284U, // ZIP1_PPP_H + 2014355508U, // ZIP1_PPP_S + 1880113204U, // ZIP1_ZZZ_B + 1209032756U, // ZIP1_ZZZ_D + 1089503284U, // ZIP1_ZZZ_H + 1096982580U, // ZIP1_ZZZ_Q + 2014355508U, // ZIP1_ZZZ_S + 271630388U, // ZIP1v16i8 + 272678964U, // ZIP1v2i32 + 273727540U, // ZIP1v2i64 + 274776116U, // ZIP1v4i16 + 275824692U, // ZIP1v4i32 + 276873268U, // ZIP1v8i16 + 277921844U, // ZIP1v8i8 + 1880113632U, // ZIP2_PPP_B + 1209033184U, // ZIP2_PPP_D + 1089503712U, // ZIP2_PPP_H + 2014355936U, // ZIP2_PPP_S + 1880113632U, // ZIP2_ZZZ_B + 1209033184U, // ZIP2_ZZZ_D + 1089503712U, // ZIP2_ZZZ_H + 1096983008U, // ZIP2_ZZZ_Q + 2014355936U, // ZIP2_ZZZ_S + 271630816U, // ZIP2v16i8 + 272679392U, // ZIP2v2i32 + 273727968U, // ZIP2v2i64 + 274776544U, // ZIP2v4i16 + 275825120U, // ZIP2v4i32 + 276873696U, // ZIP2v8i16 + 277922272U, // ZIP2v8i8 + 69268948U, // anonymous_13653 + 69268949U, // anonymous_13654 + 69264150U, // anonymous_5364 + 69264151U, // anonymous_5365 + }; + + static const uint32_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABS_ZPmZ_UNDEF_B + 0U, // ABS_ZPmZ_UNDEF_D + 0U, // ABS_ZPmZ_UNDEF_H + 0U, // ABS_ZPmZ_UNDEF_S + 0U, // ADDSWrr + 0U, // ADDSXrr + 0U, // ADDWrr + 0U, // ADDXrr + 0U, // ADD_ZPZZ_UNDEF_B + 0U, // ADD_ZPZZ_UNDEF_D + 0U, // ADD_ZPZZ_UNDEF_H + 0U, // ADD_ZPZZ_UNDEF_S + 0U, // ADD_ZPZZ_ZERO_B + 0U, // ADD_ZPZZ_ZERO_D + 0U, // ADD_ZPZZ_ZERO_H + 0U, // ADD_ZPZZ_ZERO_S + 0U, // ADDlowTLS + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // AESIMCrrTied + 0U, // AESMCrrTied + 0U, // ANDSWrr + 0U, // ANDSXrr + 0U, // ANDWrr + 0U, // ANDXrr + 0U, // ASRD_ZPZI_ZERO_B + 0U, // ASRD_ZPZI_ZERO_D + 0U, // ASRD_ZPZI_ZERO_H + 0U, // ASRD_ZPZI_ZERO_S + 0U, // ASR_ZPZI_UNDEF_B + 0U, // ASR_ZPZI_UNDEF_D + 0U, // ASR_ZPZI_UNDEF_H + 0U, // ASR_ZPZI_UNDEF_S + 0U, // ASR_ZPZZ_UNDEF_B + 0U, // ASR_ZPZZ_UNDEF_D + 0U, // ASR_ZPZZ_UNDEF_H + 0U, // ASR_ZPZZ_UNDEF_S + 0U, // ASR_ZPZZ_ZERO_B + 0U, // ASR_ZPZZ_ZERO_D + 0U, // ASR_ZPZZ_ZERO_H + 0U, // ASR_ZPZZ_ZERO_S + 0U, // BICSWrr + 0U, // BICSXrr + 0U, // BICWrr + 0U, // BICXrr + 0U, // BLRNoIP + 0U, // BLR_RVMARKER + 0U, // BSPv16i8 + 0U, // BSPv8i8 + 0U, // CATCHRET + 0U, // CLEANUPRET + 0U, // CLS_ZPmZ_UNDEF_B + 0U, // CLS_ZPmZ_UNDEF_D + 0U, // CLS_ZPmZ_UNDEF_H + 0U, // CLS_ZPmZ_UNDEF_S + 0U, // CLZ_ZPmZ_UNDEF_B + 0U, // CLZ_ZPmZ_UNDEF_D + 0U, // CLZ_ZPmZ_UNDEF_H + 0U, // CLZ_ZPmZ_UNDEF_S + 0U, // CMP_SWAP_128 + 0U, // CMP_SWAP_128_ACQUIRE + 0U, // CMP_SWAP_128_MONOTONIC + 0U, // CMP_SWAP_128_RELEASE + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CNOT_ZPmZ_UNDEF_B + 0U, // CNOT_ZPmZ_UNDEF_D + 0U, // CNOT_ZPmZ_UNDEF_H + 0U, // CNOT_ZPmZ_UNDEF_S + 0U, // CNT_ZPmZ_UNDEF_B + 0U, // CNT_ZPmZ_UNDEF_D + 0U, // CNT_ZPmZ_UNDEF_H + 0U, // CNT_ZPmZ_UNDEF_S + 0U, // CompilerBarrier + 0U, // EMITBKEY + 0U, // EONWrr + 0U, // EONXrr + 0U, // EORWrr + 0U, // EORXrr + 0U, // F128CSEL + 0U, // FABD_ZPZZ_ZERO_D + 0U, // FABD_ZPZZ_ZERO_H + 0U, // FABD_ZPZZ_ZERO_S + 0U, // FABS_ZPmZ_UNDEF_D + 0U, // FABS_ZPmZ_UNDEF_H + 0U, // FABS_ZPmZ_UNDEF_S + 0U, // FADD_ZPZI_UNDEF_D + 0U, // FADD_ZPZI_UNDEF_H + 0U, // FADD_ZPZI_UNDEF_S + 0U, // FADD_ZPZI_ZERO_D + 0U, // FADD_ZPZI_ZERO_H + 0U, // FADD_ZPZI_ZERO_S + 0U, // FADD_ZPZZ_UNDEF_D + 0U, // FADD_ZPZZ_UNDEF_H + 0U, // FADD_ZPZZ_UNDEF_S + 0U, // FADD_ZPZZ_ZERO_D + 0U, // FADD_ZPZZ_ZERO_H + 0U, // FADD_ZPZZ_ZERO_S + 0U, // FDIVR_ZPZZ_ZERO_D + 0U, // FDIVR_ZPZZ_ZERO_H + 0U, // FDIVR_ZPZZ_ZERO_S + 0U, // FDIV_ZPZZ_UNDEF_D + 0U, // FDIV_ZPZZ_UNDEF_H + 0U, // FDIV_ZPZZ_UNDEF_S + 0U, // FDIV_ZPZZ_ZERO_D + 0U, // FDIV_ZPZZ_ZERO_H + 0U, // FDIV_ZPZZ_ZERO_S + 0U, // FMAXNM_ZPZI_UNDEF_D + 0U, // FMAXNM_ZPZI_UNDEF_H + 0U, // FMAXNM_ZPZI_UNDEF_S + 0U, // FMAXNM_ZPZI_ZERO_D + 0U, // FMAXNM_ZPZI_ZERO_H + 0U, // FMAXNM_ZPZI_ZERO_S + 0U, // FMAXNM_ZPZZ_UNDEF_D + 0U, // FMAXNM_ZPZZ_UNDEF_H + 0U, // FMAXNM_ZPZZ_UNDEF_S + 0U, // FMAXNM_ZPZZ_ZERO_D + 0U, // FMAXNM_ZPZZ_ZERO_H + 0U, // FMAXNM_ZPZZ_ZERO_S + 0U, // FMAX_ZPZI_UNDEF_D + 0U, // FMAX_ZPZI_UNDEF_H + 0U, // FMAX_ZPZI_UNDEF_S + 0U, // FMAX_ZPZI_ZERO_D + 0U, // FMAX_ZPZI_ZERO_H + 0U, // FMAX_ZPZI_ZERO_S + 0U, // FMAX_ZPZZ_UNDEF_D + 0U, // FMAX_ZPZZ_UNDEF_H + 0U, // FMAX_ZPZZ_UNDEF_S + 0U, // FMAX_ZPZZ_ZERO_D + 0U, // FMAX_ZPZZ_ZERO_H + 0U, // FMAX_ZPZZ_ZERO_S + 0U, // FMINNM_ZPZI_UNDEF_D + 0U, // FMINNM_ZPZI_UNDEF_H + 0U, // FMINNM_ZPZI_UNDEF_S + 0U, // FMINNM_ZPZI_ZERO_D + 0U, // FMINNM_ZPZI_ZERO_H + 0U, // FMINNM_ZPZI_ZERO_S + 0U, // FMINNM_ZPZZ_UNDEF_D + 0U, // FMINNM_ZPZZ_UNDEF_H + 0U, // FMINNM_ZPZZ_UNDEF_S + 0U, // FMINNM_ZPZZ_ZERO_D + 0U, // FMINNM_ZPZZ_ZERO_H + 0U, // FMINNM_ZPZZ_ZERO_S + 0U, // FMIN_ZPZI_UNDEF_D + 0U, // FMIN_ZPZI_UNDEF_H + 0U, // FMIN_ZPZI_UNDEF_S + 0U, // FMIN_ZPZI_ZERO_D + 0U, // FMIN_ZPZI_ZERO_H + 0U, // FMIN_ZPZI_ZERO_S + 0U, // FMIN_ZPZZ_UNDEF_D + 0U, // FMIN_ZPZZ_UNDEF_H + 0U, // FMIN_ZPZZ_UNDEF_S + 0U, // FMIN_ZPZZ_ZERO_D + 0U, // FMIN_ZPZZ_ZERO_H + 0U, // FMIN_ZPZZ_ZERO_S + 0U, // FMLA_ZPZZZ_UNDEF_D + 0U, // FMLA_ZPZZZ_UNDEF_H + 0U, // FMLA_ZPZZZ_UNDEF_S + 0U, // FMLS_ZPZZZ_UNDEF_D + 0U, // FMLS_ZPZZZ_UNDEF_H + 0U, // FMLS_ZPZZZ_UNDEF_S + 0U, // FMOVD0 + 0U, // FMOVH0 + 0U, // FMOVS0 + 0U, // FMULX_ZPZZ_ZERO_D + 0U, // FMULX_ZPZZ_ZERO_H + 0U, // FMULX_ZPZZ_ZERO_S + 0U, // FMUL_ZPZI_UNDEF_D + 0U, // FMUL_ZPZI_UNDEF_H + 0U, // FMUL_ZPZI_UNDEF_S + 0U, // FMUL_ZPZI_ZERO_D + 0U, // FMUL_ZPZI_ZERO_H + 0U, // FMUL_ZPZI_ZERO_S + 0U, // FMUL_ZPZZ_UNDEF_D + 0U, // FMUL_ZPZZ_UNDEF_H + 0U, // FMUL_ZPZZ_UNDEF_S + 0U, // FMUL_ZPZZ_ZERO_D + 0U, // FMUL_ZPZZ_ZERO_H + 0U, // FMUL_ZPZZ_ZERO_S + 0U, // FNEG_ZPmZ_UNDEF_D + 0U, // FNEG_ZPmZ_UNDEF_H + 0U, // FNEG_ZPmZ_UNDEF_S + 0U, // FNMLA_ZPZZZ_UNDEF_D + 0U, // FNMLA_ZPZZZ_UNDEF_H + 0U, // FNMLA_ZPZZZ_UNDEF_S + 0U, // FNMLS_ZPZZZ_UNDEF_D + 0U, // FNMLS_ZPZZZ_UNDEF_H + 0U, // FNMLS_ZPZZZ_UNDEF_S + 0U, // FRECPX_ZPmZ_UNDEF_D + 0U, // FRECPX_ZPmZ_UNDEF_H + 0U, // FRECPX_ZPmZ_UNDEF_S + 0U, // FRINTA_ZPmZ_UNDEF_D + 0U, // FRINTA_ZPmZ_UNDEF_H + 0U, // FRINTA_ZPmZ_UNDEF_S + 0U, // FRINTI_ZPmZ_UNDEF_D + 0U, // FRINTI_ZPmZ_UNDEF_H + 0U, // FRINTI_ZPmZ_UNDEF_S + 0U, // FRINTM_ZPmZ_UNDEF_D + 0U, // FRINTM_ZPmZ_UNDEF_H + 0U, // FRINTM_ZPmZ_UNDEF_S + 0U, // FRINTN_ZPmZ_UNDEF_D + 0U, // FRINTN_ZPmZ_UNDEF_H + 0U, // FRINTN_ZPmZ_UNDEF_S + 0U, // FRINTP_ZPmZ_UNDEF_D + 0U, // FRINTP_ZPmZ_UNDEF_H + 0U, // FRINTP_ZPmZ_UNDEF_S + 0U, // FRINTX_ZPmZ_UNDEF_D + 0U, // FRINTX_ZPmZ_UNDEF_H + 0U, // FRINTX_ZPmZ_UNDEF_S + 0U, // FRINTZ_ZPmZ_UNDEF_D + 0U, // FRINTZ_ZPmZ_UNDEF_H + 0U, // FRINTZ_ZPmZ_UNDEF_S + 0U, // FSQRT_ZPmZ_UNDEF_D + 0U, // FSQRT_ZPmZ_UNDEF_H + 0U, // FSQRT_ZPmZ_UNDEF_S + 0U, // FSUBR_ZPZI_UNDEF_D + 0U, // FSUBR_ZPZI_UNDEF_H + 0U, // FSUBR_ZPZI_UNDEF_S + 0U, // FSUBR_ZPZI_ZERO_D + 0U, // FSUBR_ZPZI_ZERO_H + 0U, // FSUBR_ZPZI_ZERO_S + 0U, // FSUBR_ZPZZ_ZERO_D + 0U, // FSUBR_ZPZZ_ZERO_H + 0U, // FSUBR_ZPZZ_ZERO_S + 0U, // FSUB_ZPZI_UNDEF_D + 0U, // FSUB_ZPZI_UNDEF_H + 0U, // FSUB_ZPZI_UNDEF_S + 0U, // FSUB_ZPZI_ZERO_D + 0U, // FSUB_ZPZI_ZERO_H + 0U, // FSUB_ZPZI_ZERO_S + 0U, // FSUB_ZPZZ_UNDEF_D + 0U, // FSUB_ZPZZ_UNDEF_H + 0U, // FSUB_ZPZZ_UNDEF_S + 0U, // FSUB_ZPZZ_ZERO_D + 0U, // FSUB_ZPZZ_ZERO_H + 0U, // FSUB_ZPZZ_ZERO_S + 0U, // GLD1B_D + 0U, // GLD1B_D_IMM + 0U, // GLD1B_D_SXTW + 0U, // GLD1B_D_UXTW + 0U, // GLD1B_S_IMM + 0U, // GLD1B_S_SXTW + 0U, // GLD1B_S_UXTW + 0U, // GLD1D + 0U, // GLD1D_IMM + 0U, // GLD1D_SCALED + 0U, // GLD1D_SXTW + 0U, // GLD1D_SXTW_SCALED + 0U, // GLD1D_UXTW + 0U, // GLD1D_UXTW_SCALED + 0U, // GLD1H_D + 0U, // GLD1H_D_IMM + 0U, // GLD1H_D_SCALED + 0U, // GLD1H_D_SXTW + 0U, // GLD1H_D_SXTW_SCALED + 0U, // GLD1H_D_UXTW + 0U, // GLD1H_D_UXTW_SCALED + 0U, // GLD1H_S_IMM + 0U, // GLD1H_S_SXTW + 0U, // GLD1H_S_SXTW_SCALED + 0U, // GLD1H_S_UXTW + 0U, // GLD1H_S_UXTW_SCALED + 0U, // GLD1SB_D + 0U, // GLD1SB_D_IMM + 0U, // GLD1SB_D_SXTW + 0U, // GLD1SB_D_UXTW + 0U, // GLD1SB_S_IMM + 0U, // GLD1SB_S_SXTW + 0U, // GLD1SB_S_UXTW + 0U, // GLD1SH_D + 0U, // GLD1SH_D_IMM + 0U, // GLD1SH_D_SCALED + 0U, // GLD1SH_D_SXTW + 0U, // GLD1SH_D_SXTW_SCALED + 0U, // GLD1SH_D_UXTW + 0U, // GLD1SH_D_UXTW_SCALED + 0U, // GLD1SH_S_IMM + 0U, // GLD1SH_S_SXTW + 0U, // GLD1SH_S_SXTW_SCALED + 0U, // GLD1SH_S_UXTW + 0U, // GLD1SH_S_UXTW_SCALED + 0U, // GLD1SW_D + 0U, // GLD1SW_D_IMM + 0U, // GLD1SW_D_SCALED + 0U, // GLD1SW_D_SXTW + 0U, // GLD1SW_D_SXTW_SCALED + 0U, // GLD1SW_D_UXTW + 0U, // GLD1SW_D_UXTW_SCALED + 0U, // GLD1W_D + 0U, // GLD1W_D_IMM + 0U, // GLD1W_D_SCALED + 0U, // GLD1W_D_SXTW + 0U, // GLD1W_D_SXTW_SCALED + 0U, // GLD1W_D_UXTW + 0U, // GLD1W_D_UXTW_SCALED + 0U, // GLD1W_IMM + 0U, // GLD1W_SXTW + 0U, // GLD1W_SXTW_SCALED + 0U, // GLD1W_UXTW + 0U, // GLD1W_UXTW_SCALED + 0U, // GLDFF1B_D + 0U, // GLDFF1B_D_IMM + 0U, // GLDFF1B_D_SXTW + 0U, // GLDFF1B_D_UXTW + 0U, // GLDFF1B_S_IMM + 0U, // GLDFF1B_S_SXTW + 0U, // GLDFF1B_S_UXTW + 0U, // GLDFF1D + 0U, // GLDFF1D_IMM + 0U, // GLDFF1D_SCALED + 0U, // GLDFF1D_SXTW + 0U, // GLDFF1D_SXTW_SCALED + 0U, // GLDFF1D_UXTW + 0U, // GLDFF1D_UXTW_SCALED + 0U, // GLDFF1H_D + 0U, // GLDFF1H_D_IMM + 0U, // GLDFF1H_D_SCALED + 0U, // GLDFF1H_D_SXTW + 0U, // GLDFF1H_D_SXTW_SCALED + 0U, // GLDFF1H_D_UXTW + 0U, // GLDFF1H_D_UXTW_SCALED + 0U, // GLDFF1H_S_IMM + 0U, // GLDFF1H_S_SXTW + 0U, // GLDFF1H_S_SXTW_SCALED + 0U, // GLDFF1H_S_UXTW + 0U, // GLDFF1H_S_UXTW_SCALED + 0U, // GLDFF1SB_D + 0U, // GLDFF1SB_D_IMM + 0U, // GLDFF1SB_D_SXTW + 0U, // GLDFF1SB_D_UXTW + 0U, // GLDFF1SB_S_IMM + 0U, // GLDFF1SB_S_SXTW + 0U, // GLDFF1SB_S_UXTW + 0U, // GLDFF1SH_D + 0U, // GLDFF1SH_D_IMM + 0U, // GLDFF1SH_D_SCALED + 0U, // GLDFF1SH_D_SXTW + 0U, // GLDFF1SH_D_SXTW_SCALED + 0U, // GLDFF1SH_D_UXTW + 0U, // GLDFF1SH_D_UXTW_SCALED + 0U, // GLDFF1SH_S_IMM + 0U, // GLDFF1SH_S_SXTW + 0U, // GLDFF1SH_S_SXTW_SCALED + 0U, // GLDFF1SH_S_UXTW + 0U, // GLDFF1SH_S_UXTW_SCALED + 0U, // GLDFF1SW_D + 0U, // GLDFF1SW_D_IMM + 0U, // GLDFF1SW_D_SCALED + 0U, // GLDFF1SW_D_SXTW + 0U, // GLDFF1SW_D_SXTW_SCALED + 0U, // GLDFF1SW_D_UXTW + 0U, // GLDFF1SW_D_UXTW_SCALED + 0U, // GLDFF1W_D + 0U, // GLDFF1W_D_IMM + 0U, // GLDFF1W_D_SCALED + 0U, // GLDFF1W_D_SXTW + 0U, // GLDFF1W_D_SXTW_SCALED + 0U, // GLDFF1W_D_UXTW + 0U, // GLDFF1W_D_UXTW_SCALED + 0U, // GLDFF1W_IMM + 0U, // GLDFF1W_SXTW + 0U, // GLDFF1W_SXTW_SCALED + 0U, // GLDFF1W_UXTW + 0U, // GLDFF1W_UXTW_SCALED + 0U, // G_ADD_LOW + 0U, // G_DUP + 0U, // G_DUPLANE16 + 0U, // G_DUPLANE32 + 0U, // G_DUPLANE64 + 0U, // G_DUPLANE8 + 0U, // G_EXT + 0U, // G_FCMEQ + 0U, // G_FCMEQZ + 0U, // G_FCMGE + 0U, // G_FCMGEZ + 0U, // G_FCMGT + 0U, // G_FCMGTZ + 0U, // G_FCMLEZ + 0U, // G_FCMLTZ + 0U, // G_REV16 + 0U, // G_REV32 + 0U, // G_REV64 + 0U, // G_SITOF + 0U, // G_TRN1 + 0U, // G_TRN2 + 0U, // G_UITOF + 0U, // G_UZP1 + 0U, // G_UZP2 + 0U, // G_VASHR + 0U, // G_VLSHR + 0U, // G_ZIP1 + 0U, // G_ZIP2 + 0U, // HOM_Epilog + 0U, // HOM_Prolog + 0U, // HWASAN_CHECK_MEMACCESS + 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES + 0U, // IRGstack + 0U, // JumpTableDest16 + 0U, // JumpTableDest32 + 0U, // JumpTableDest8 + 0U, // LD1B_D_IMM + 0U, // LD1B_H_IMM + 0U, // LD1B_IMM + 0U, // LD1B_S_IMM + 0U, // LD1D_IMM + 0U, // LD1H_D_IMM + 0U, // LD1H_IMM + 0U, // LD1H_S_IMM + 0U, // LD1SB_D_IMM + 0U, // LD1SB_H_IMM + 0U, // LD1SB_S_IMM + 0U, // LD1SH_D_IMM + 0U, // LD1SH_S_IMM + 0U, // LD1SW_D_IMM + 0U, // LD1W_D_IMM + 0U, // LD1W_IMM + 0U, // LDFF1B + 0U, // LDFF1B_D + 0U, // LDFF1B_H + 0U, // LDFF1B_S + 0U, // LDFF1D + 0U, // LDFF1H + 0U, // LDFF1H_D + 0U, // LDFF1H_S + 0U, // LDFF1SB_D + 0U, // LDFF1SB_H + 0U, // LDFF1SB_S + 0U, // LDFF1SH_D + 0U, // LDFF1SH_S + 0U, // LDFF1SW_D + 0U, // LDFF1W + 0U, // LDFF1W_D + 0U, // LDNF1B_D_IMM + 0U, // LDNF1B_H_IMM + 0U, // LDNF1B_IMM + 0U, // LDNF1B_S_IMM + 0U, // LDNF1D_IMM + 0U, // LDNF1H_D_IMM + 0U, // LDNF1H_IMM + 0U, // LDNF1H_S_IMM + 0U, // LDNF1SB_D_IMM + 0U, // LDNF1SB_H_IMM + 0U, // LDNF1SB_S_IMM + 0U, // LDNF1SH_D_IMM + 0U, // LDNF1SH_S_IMM + 0U, // LDNF1SW_D_IMM + 0U, // LDNF1W_D_IMM + 0U, // LDNF1W_IMM + 0U, // LDR_ZZXI + 0U, // LDR_ZZZXI + 0U, // LDR_ZZZZXI + 0U, // LOADgot + 0U, // LSL_ZPZI_UNDEF_B + 0U, // LSL_ZPZI_UNDEF_D + 0U, // LSL_ZPZI_UNDEF_H + 0U, // LSL_ZPZI_UNDEF_S + 0U, // LSL_ZPZZ_UNDEF_B + 0U, // LSL_ZPZZ_UNDEF_D + 0U, // LSL_ZPZZ_UNDEF_H + 0U, // LSL_ZPZZ_UNDEF_S + 0U, // LSL_ZPZZ_ZERO_B + 0U, // LSL_ZPZZ_ZERO_D + 0U, // LSL_ZPZZ_ZERO_H + 0U, // LSL_ZPZZ_ZERO_S + 0U, // LSR_ZPZI_UNDEF_B + 0U, // LSR_ZPZI_UNDEF_D + 0U, // LSR_ZPZI_UNDEF_H + 0U, // LSR_ZPZI_UNDEF_S + 0U, // LSR_ZPZZ_UNDEF_B + 0U, // LSR_ZPZZ_UNDEF_D + 0U, // LSR_ZPZZ_UNDEF_H + 0U, // LSR_ZPZZ_UNDEF_S + 0U, // LSR_ZPZZ_ZERO_B + 0U, // LSR_ZPZZ_ZERO_D + 0U, // LSR_ZPZZ_ZERO_H + 0U, // LSR_ZPZZ_ZERO_S + 0U, // MOVMCSym + 0U, // MOVaddr + 0U, // MOVaddrBA + 0U, // MOVaddrCP + 0U, // MOVaddrEXT + 0U, // MOVaddrJT + 0U, // MOVaddrTLS + 0U, // MOVbaseTLS + 0U, // MOVi32imm + 0U, // MOVi64imm + 0U, // MUL_ZPZZ_UNDEF_B + 0U, // MUL_ZPZZ_UNDEF_D + 0U, // MUL_ZPZZ_UNDEF_H + 0U, // MUL_ZPZZ_UNDEF_S + 0U, // NEG_ZPmZ_UNDEF_B + 0U, // NEG_ZPmZ_UNDEF_D + 0U, // NEG_ZPmZ_UNDEF_H + 0U, // NEG_ZPmZ_UNDEF_S + 0U, // NOT_ZPmZ_UNDEF_B + 0U, // NOT_ZPmZ_UNDEF_D + 0U, // NOT_ZPmZ_UNDEF_H + 0U, // NOT_ZPmZ_UNDEF_S + 0U, // ORNWrr + 0U, // ORNXrr + 0U, // ORRWrr + 0U, // ORRXrr + 0U, // RDFFR_P + 0U, // RDFFR_PPz + 0U, // RET_ReallyLR + 0U, // SDIV_ZPZZ_UNDEF_D + 0U, // SDIV_ZPZZ_UNDEF_S + 0U, // SEH_AddFP + 0U, // SEH_EpilogEnd + 0U, // SEH_EpilogStart + 0U, // SEH_Nop + 0U, // SEH_PrologEnd + 0U, // SEH_SaveFPLR + 0U, // SEH_SaveFPLR_X + 0U, // SEH_SaveFReg + 0U, // SEH_SaveFRegP + 0U, // SEH_SaveFRegP_X + 0U, // SEH_SaveFReg_X + 0U, // SEH_SaveReg + 0U, // SEH_SaveRegP + 0U, // SEH_SaveRegP_X + 0U, // SEH_SaveReg_X + 0U, // SEH_SetFP + 0U, // SEH_StackAlloc + 0U, // SMAX_ZPZZ_UNDEF_B + 0U, // SMAX_ZPZZ_UNDEF_D + 0U, // SMAX_ZPZZ_UNDEF_H + 0U, // SMAX_ZPZZ_UNDEF_S + 0U, // SMIN_ZPZZ_UNDEF_B + 0U, // SMIN_ZPZZ_UNDEF_D + 0U, // SMIN_ZPZZ_UNDEF_H + 0U, // SMIN_ZPZZ_UNDEF_S + 0U, // SMULH_ZPZZ_UNDEF_B + 0U, // SMULH_ZPZZ_UNDEF_D + 0U, // SMULH_ZPZZ_UNDEF_H + 0U, // SMULH_ZPZZ_UNDEF_S + 0U, // SPACE + 0U, // SQABS_ZPmZ_UNDEF_B + 0U, // SQABS_ZPmZ_UNDEF_D + 0U, // SQABS_ZPmZ_UNDEF_H + 0U, // SQABS_ZPmZ_UNDEF_S + 0U, // SQNEG_ZPmZ_UNDEF_B + 0U, // SQNEG_ZPmZ_UNDEF_D + 0U, // SQNEG_ZPmZ_UNDEF_H + 0U, // SQNEG_ZPmZ_UNDEF_S + 0U, // SQRSHL_ZPZZ_UNDEF_B + 0U, // SQRSHL_ZPZZ_UNDEF_D + 0U, // SQRSHL_ZPZZ_UNDEF_H + 0U, // SQRSHL_ZPZZ_UNDEF_S + 0U, // SQSHLU_ZPZI_ZERO_B + 0U, // SQSHLU_ZPZI_ZERO_D + 0U, // SQSHLU_ZPZI_ZERO_H + 0U, // SQSHLU_ZPZI_ZERO_S + 0U, // SQSHL_ZPZI_ZERO_B + 0U, // SQSHL_ZPZI_ZERO_D + 0U, // SQSHL_ZPZI_ZERO_H + 0U, // SQSHL_ZPZI_ZERO_S + 0U, // SQSHL_ZPZZ_UNDEF_B + 0U, // SQSHL_ZPZZ_UNDEF_D + 0U, // SQSHL_ZPZZ_UNDEF_H + 0U, // SQSHL_ZPZZ_UNDEF_S + 0U, // SRSHL_ZPZZ_UNDEF_B + 0U, // SRSHL_ZPZZ_UNDEF_D + 0U, // SRSHL_ZPZZ_UNDEF_H + 0U, // SRSHL_ZPZZ_UNDEF_S + 0U, // SRSHR_ZPZI_ZERO_B + 0U, // SRSHR_ZPZI_ZERO_D + 0U, // SRSHR_ZPZI_ZERO_H + 0U, // SRSHR_ZPZI_ZERO_S + 0U, // STGloop + 0U, // STGloop_wback + 0U, // STR_ZZXI + 0U, // STR_ZZZXI + 0U, // STR_ZZZZXI + 0U, // STZGloop + 0U, // STZGloop_wback + 0U, // SUBR_ZPZZ_ZERO_B + 0U, // SUBR_ZPZZ_ZERO_D + 0U, // SUBR_ZPZZ_ZERO_H + 0U, // SUBR_ZPZZ_ZERO_S + 0U, // SUBSWrr + 0U, // SUBSXrr + 0U, // SUBWrr + 0U, // SUBXrr + 0U, // SUB_ZPZZ_UNDEF_B + 0U, // SUB_ZPZZ_UNDEF_D + 0U, // SUB_ZPZZ_UNDEF_H + 0U, // SUB_ZPZZ_UNDEF_S + 0U, // SUB_ZPZZ_ZERO_B + 0U, // SUB_ZPZZ_ZERO_D + 0U, // SUB_ZPZZ_ZERO_H + 0U, // SUB_ZPZZ_ZERO_S + 0U, // SXTB_ZPmZ_UNDEF_D + 0U, // SXTB_ZPmZ_UNDEF_H + 0U, // SXTB_ZPmZ_UNDEF_S + 0U, // SXTH_ZPmZ_UNDEF_D + 0U, // SXTH_ZPmZ_UNDEF_S + 0U, // SXTW_ZPmZ_UNDEF_D + 0U, // SpeculationBarrierISBDSBEndBB + 0U, // SpeculationBarrierSBEndBB + 0U, // SpeculationSafeValueW + 0U, // SpeculationSafeValueX + 0U, // StoreSwiftAsyncContext + 0U, // TAGPstack + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TCRETURNriALL + 0U, // TCRETURNriBTI + 0U, // TLSDESCCALL + 0U, // TLSDESC_CALLSEQ + 0U, // UDIV_ZPZZ_UNDEF_D + 0U, // UDIV_ZPZZ_UNDEF_S + 0U, // UMAX_ZPZZ_UNDEF_B + 0U, // UMAX_ZPZZ_UNDEF_D + 0U, // UMAX_ZPZZ_UNDEF_H + 0U, // UMAX_ZPZZ_UNDEF_S + 0U, // UMIN_ZPZZ_UNDEF_B + 0U, // UMIN_ZPZZ_UNDEF_D + 0U, // UMIN_ZPZZ_UNDEF_H + 0U, // UMIN_ZPZZ_UNDEF_S + 0U, // UMULH_ZPZZ_UNDEF_B + 0U, // UMULH_ZPZZ_UNDEF_D + 0U, // UMULH_ZPZZ_UNDEF_H + 0U, // UMULH_ZPZZ_UNDEF_S + 0U, // UQRSHL_ZPZZ_UNDEF_B + 0U, // UQRSHL_ZPZZ_UNDEF_D + 0U, // UQRSHL_ZPZZ_UNDEF_H + 0U, // UQRSHL_ZPZZ_UNDEF_S + 0U, // UQSHL_ZPZI_ZERO_B + 0U, // UQSHL_ZPZI_ZERO_D + 0U, // UQSHL_ZPZI_ZERO_H + 0U, // UQSHL_ZPZI_ZERO_S + 0U, // UQSHL_ZPZZ_UNDEF_B + 0U, // UQSHL_ZPZZ_UNDEF_D + 0U, // UQSHL_ZPZZ_UNDEF_H + 0U, // UQSHL_ZPZZ_UNDEF_S + 0U, // URECPE_ZPmZ_UNDEF_S + 0U, // URSHL_ZPZZ_UNDEF_B + 0U, // URSHL_ZPZZ_UNDEF_D + 0U, // URSHL_ZPZZ_UNDEF_H + 0U, // URSHL_ZPZZ_UNDEF_S + 0U, // URSHR_ZPZI_ZERO_B + 0U, // URSHR_ZPZI_ZERO_D + 0U, // URSHR_ZPZI_ZERO_H + 0U, // URSHR_ZPZI_ZERO_S + 0U, // URSQRTE_ZPmZ_UNDEF_S + 0U, // UXTB_ZPmZ_UNDEF_D + 0U, // UXTB_ZPmZ_UNDEF_H + 0U, // UXTB_ZPmZ_UNDEF_S + 0U, // UXTH_ZPmZ_UNDEF_D + 0U, // UXTH_ZPmZ_UNDEF_S + 0U, // UXTW_ZPmZ_UNDEF_D + 0U, // ABS_ZPmZ_B + 4U, // ABS_ZPmZ_D + 0U, // ABS_ZPmZ_H + 8U, // ABS_ZPmZ_S + 12U, // ABSv16i8 + 16U, // ABSv1i64 + 20U, // ABSv2i32 + 24U, // ABSv2i64 + 28U, // ABSv4i16 + 32U, // ABSv4i32 + 36U, // ABSv8i16 + 40U, // ABSv8i8 + 556U, // ADCLB_ZZZ_D + 1068U, // ADCLB_ZZZ_S + 556U, // ADCLT_ZZZ_D + 1068U, // ADCLT_ZZZ_S + 1580U, // ADCSWr + 1580U, // ADCSXr + 1580U, // ADCWr + 1580U, // ADCXr + 67628U, // ADDG + 0U, // ADDHA_MPPZ_D + 0U, // ADDHA_MPPZ_S + 2604U, // ADDHNB_ZZZ_B + 48U, // ADDHNB_ZZZ_H + 3116U, // ADDHNB_ZZZ_S + 3628U, // ADDHNT_ZZZ_B + 8U, // ADDHNT_ZZZ_H + 556U, // ADDHNT_ZZZ_S + 135220U, // ADDHNv2i64_v2i32 + 135732U, // ADDHNv2i64_v4i32 + 200760U, // ADDHNv4i32_v4i16 + 201272U, // ADDHNv4i32_v8i16 + 266812U, // ADDHNv8i16_v16i8 + 266300U, // ADDHNv8i16_v8i8 + 1580U, // ADDPL_XXI + 4265024U, // ADDP_ZPmZ_B + 8457280U, // ADDP_ZPmZ_D + 12916292U, // ADDP_ZPmZ_H + 16848960U, // ADDP_ZPmZ_S + 397384U, // ADDPv16i8 + 462924U, // ADDPv2i32 + 135220U, // ADDPv2i64 + 24U, // ADDPv2i64p + 528464U, // ADDPv4i16 + 200760U, // ADDPv4i32 + 266300U, // ADDPv8i16 + 594004U, // ADDPv8i8 + 6700U, // ADDSWri + 7212U, // ADDSWrs + 7724U, // ADDSWrx + 6700U, // ADDSXri + 7212U, // ADDSXrs + 7724U, // ADDSXrx + 656940U, // ADDSXrx64 + 0U, // ADDVA_MPPZ_D + 0U, // ADDVA_MPPZ_S + 1580U, // ADDVL_XXI + 12U, // ADDVv16i8v + 28U, // ADDVv4i16v + 32U, // ADDVv4i32v + 36U, // ADDVv8i16v + 40U, // ADDVv8i8v + 6700U, // ADDWri + 7212U, // ADDWrs + 7724U, // ADDWrx + 6700U, // ADDXri + 7212U, // ADDXrs + 7724U, // ADDXrx + 656940U, // ADDXrx64 + 8236U, // ADD_ZI_B + 8748U, // ADD_ZI_D + 88U, // ADD_ZI_H + 9260U, // ADD_ZI_S + 4265024U, // ADD_ZPmZ_B + 8457280U, // ADD_ZPmZ_D + 12916292U, // ADD_ZPmZ_H + 16848960U, // ADD_ZPmZ_S + 5164U, // ADD_ZZZ_B + 3116U, // ADD_ZZZ_D + 68U, // ADD_ZZZ_H + 6188U, // ADD_ZZZ_S + 397384U, // ADDv16i8 + 1580U, // ADDv1i64 + 462924U, // ADDv2i32 + 135220U, // ADDv2i64 + 528464U, // ADDv4i16 + 200760U, // ADDv4i32 + 266300U, // ADDv8i16 + 594004U, // ADDv8i8 + 16U, // ADR + 0U, // ADRP + 9772U, // ADR_LSL_ZZZ_D_0 + 10284U, // ADR_LSL_ZZZ_D_1 + 10796U, // ADR_LSL_ZZZ_D_2 + 11308U, // ADR_LSL_ZZZ_D_3 + 11820U, // ADR_LSL_ZZZ_S_0 + 12332U, // ADR_LSL_ZZZ_S_1 + 12844U, // ADR_LSL_ZZZ_S_2 + 13356U, // ADR_LSL_ZZZ_S_3 + 13868U, // ADR_SXTW_ZZZ_D_0 + 14380U, // ADR_SXTW_ZZZ_D_1 + 14892U, // ADR_SXTW_ZZZ_D_2 + 15404U, // ADR_SXTW_ZZZ_D_3 + 15916U, // ADR_UXTW_ZZZ_D_0 + 16428U, // ADR_UXTW_ZZZ_D_1 + 16940U, // ADR_UXTW_ZZZ_D_2 + 17452U, // ADR_UXTW_ZZZ_D_3 + 5164U, // AESD_ZZZ_B + 12U, // AESDrr + 5164U, // AESE_ZZZ_B + 12U, // AESErr + 16U, // AESIMC_ZZ_B + 12U, // AESIMCrr + 16U, // AESMC_ZZ_B + 12U, // AESMCrr + 17964U, // ANDSWri + 7212U, // ANDSWrs + 18476U, // ANDSXri + 7212U, // ANDSXrs + 4265052U, // ANDS_PPzPP + 0U, // ANDV_VPZ_B + 0U, // ANDV_VPZ_D + 0U, // ANDV_VPZ_H + 0U, // ANDV_VPZ_S + 17964U, // ANDWri + 7212U, // ANDWrs + 18476U, // ANDXri + 7212U, // ANDXrs + 4265052U, // AND_PPzPP + 18476U, // AND_ZI + 4265024U, // AND_ZPmZ_B + 8457280U, // AND_ZPmZ_D + 12916292U, // AND_ZPmZ_H + 16848960U, // AND_ZPmZ_S + 3116U, // AND_ZZZ + 397384U, // ANDv16i8 + 594004U, // ANDv8i8 + 70720U, // ASRD_ZPmI_B + 68672U, // ASRD_ZPmI_D + 726596U, // ASRD_ZPmI_H + 71744U, // ASRD_ZPmI_S + 4265024U, // ASRR_ZPmZ_B + 8457280U, // ASRR_ZPmZ_D + 12916292U, // ASRR_ZPmZ_H + 16848960U, // ASRR_ZPmZ_S + 1580U, // ASRVWr + 1580U, // ASRVXr + 8459328U, // ASR_WIDE_ZPmZ_B + 792132U, // ASR_WIDE_ZPmZ_H + 8460352U, // ASR_WIDE_ZPmZ_S + 3116U, // ASR_WIDE_ZZZ_B + 96U, // ASR_WIDE_ZZZ_H + 3116U, // ASR_WIDE_ZZZ_S + 70720U, // ASR_ZPmI_B + 68672U, // ASR_ZPmI_D + 726596U, // ASR_ZPmI_H + 71744U, // ASR_ZPmI_S + 4265024U, // ASR_ZPmZ_B + 8457280U, // ASR_ZPmZ_D + 12916292U, // ASR_ZPmZ_H + 16848960U, // ASR_ZPmZ_S + 1580U, // ASR_ZZI_B + 1580U, // ASR_ZZI_D + 100U, // ASR_ZZI_H + 1580U, // ASR_ZZI_S + 16U, // AUTDA + 16U, // AUTDB + 0U, // AUTDZA + 0U, // AUTDZB + 16U, // AUTIA + 0U, // AUTIA1716 + 0U, // AUTIASP + 0U, // AUTIAZ + 16U, // AUTIB + 0U, // AUTIB1716 + 0U, // AUTIBSP + 0U, // AUTIBZ + 0U, // AUTIZA + 0U, // AUTIZB + 0U, // AXFLAG + 0U, // B + 290263112U, // BCAX + 8457260U, // BCAX_ZZZZ + 5164U, // BDEP_ZZZ_B + 3116U, // BDEP_ZZZ_D + 68U, // BDEP_ZZZ_H + 6188U, // BDEP_ZZZ_S + 5164U, // BEXT_ZZZ_B + 3116U, // BEXT_ZZZ_D + 68U, // BEXT_ZZZ_H + 6188U, // BEXT_ZZZ_S + 922192U, // BF16DOTlanev4bf16 + 922172U, // BF16DOTlanev8bf16 + 16U, // BFCVT + 32U, // BFCVTN + 32U, // BFCVTN2 + 0U, // BFCVTNT_ZPmZ + 0U, // BFCVT_ZPmZ + 13569580U, // BFDOT_ZZI + 3628U, // BFDOT_ZZZ + 528976U, // BFDOTv4bf16 + 266812U, // BFDOTv8bf16 + 266812U, // BFMLALB + 26219068U, // BFMLALBIdx + 266812U, // BFMLALT + 26219068U, // BFMLALTIdx + 266812U, // BFMMLA + 13569580U, // BFMMLA_B_ZZI + 3628U, // BFMMLA_B_ZZZ + 13569580U, // BFMMLA_T_ZZI + 3628U, // BFMMLA_T_ZZZ + 3628U, // BFMMLA_ZZZ + 29444652U, // BFMWri + 29444652U, // BFMXri + 5164U, // BGRP_ZZZ_B + 3116U, // BGRP_ZZZ_D + 68U, // BGRP_ZZZ_H + 6188U, // BGRP_ZZZ_S + 7212U, // BICSWrs + 7212U, // BICSXrs + 4265052U, // BICS_PPzPP + 7212U, // BICWrs + 7212U, // BICXrs + 4265052U, // BIC_PPzPP + 4265024U, // BIC_ZPmZ_B + 8457280U, // BIC_ZPmZ_D + 12916292U, // BIC_ZPmZ_H + 16848960U, // BIC_ZPmZ_S + 3116U, // BIC_ZZZ + 397384U, // BICv16i8 + 0U, // BICv2i32 + 0U, // BICv4i16 + 0U, // BICv4i32 + 0U, // BICv8i16 + 594004U, // BICv8i8 + 397896U, // BIFv16i8 + 594516U, // BIFv8i8 + 397896U, // BITv16i8 + 594516U, // BITv8i8 + 0U, // BL + 0U, // BLR + 16U, // BLRAA + 0U, // BLRAAZ + 16U, // BLRAB + 0U, // BLRABZ + 0U, // BR + 16U, // BRAA + 0U, // BRAAZ + 16U, // BRAB + 0U, // BRABZ + 0U, // BRB_IALL + 0U, // BRB_INJ + 0U, // BRK + 5212U, // BRKAS_PPzP + 0U, // BRKA_PPmP + 5212U, // BRKA_PPzP + 5212U, // BRKBS_PPzP + 0U, // BRKB_PPmP + 5212U, // BRKB_PPzP + 4265052U, // BRKNS_PPzP + 4265052U, // BRKN_PPzP + 4265052U, // BRKPAS_PPzPP + 4265052U, // BRKPA_PPzPP + 4265052U, // BRKPBS_PPzPP + 4265052U, // BRKPB_PPzPP + 8457260U, // BSL1N_ZZZZ + 8457260U, // BSL2N_ZZZZ + 8457260U, // BSL_ZZZZ + 397896U, // BSLv16i8 + 594516U, // BSLv8i8 + 0U, // Bcc + 33625132U, // CADD_ZZI_B + 33623084U, // CADD_ZZI_D + 1119812U, // CADD_ZZI_H + 33626156U, // CADD_ZZI_S + 1198696U, // CASAB + 1198696U, // CASAH + 1198696U, // CASALB + 1198696U, // CASALH + 1198696U, // CASALW + 1198696U, // CASALX + 1198696U, // CASAW + 1198696U, // CASAX + 1198696U, // CASB + 1198696U, // CASH + 1198696U, // CASLB + 1198696U, // CASLH + 1198696U, // CASLW + 1198696U, // CASLX + 0U, // CASPALW + 0U, // CASPALX + 0U, // CASPAW + 0U, // CASPAX + 0U, // CASPLW + 0U, // CASPLX + 0U, // CASPW + 0U, // CASPX + 1198696U, // CASW + 1198696U, // CASX + 0U, // CBNZW + 0U, // CBNZX + 0U, // CBZW + 0U, // CBZX + 37815852U, // CCMNWi + 37815852U, // CCMNWr + 37815852U, // CCMNXi + 37815852U, // CCMNXr + 37815852U, // CCMPWi + 37815852U, // CCMPWr + 37815852U, // CCMPXi + 37815852U, // CCMPXr + 579800620U, // CDOT_ZZZI_D + 46222336U, // CDOT_ZZZI_S + 50400812U, // CDOT_ZZZ_D + 1250816U, // CDOT_ZZZ_S + 0U, // CFINV + 4261420U, // CLASTA_RPZ_B + 8455724U, // CLASTA_RPZ_D + 54593068U, // CLASTA_RPZ_H + 16844332U, // CLASTA_RPZ_S + 4261420U, // CLASTA_VPZ_B + 8455724U, // CLASTA_VPZ_D + 54593068U, // CLASTA_VPZ_H + 16844332U, // CLASTA_VPZ_S + 4265004U, // CLASTA_ZPZ_B + 8457260U, // CLASTA_ZPZ_D + 12916292U, // CLASTA_ZPZ_H + 16848940U, // CLASTA_ZPZ_S + 4261420U, // CLASTB_RPZ_B + 8455724U, // CLASTB_RPZ_D + 54593068U, // CLASTB_RPZ_H + 16844332U, // CLASTB_RPZ_S + 4261420U, // CLASTB_VPZ_B + 8455724U, // CLASTB_VPZ_D + 54593068U, // CLASTB_VPZ_H + 16844332U, // CLASTB_VPZ_S + 4265004U, // CLASTB_ZPZ_B + 8457260U, // CLASTB_ZPZ_D + 12916292U, // CLASTB_ZPZ_H + 16848940U, // CLASTB_ZPZ_S + 0U, // CLREX + 16U, // CLSWr + 16U, // CLSXr + 0U, // CLS_ZPmZ_B + 4U, // CLS_ZPmZ_D + 0U, // CLS_ZPmZ_H + 8U, // CLS_ZPmZ_S + 12U, // CLSv16i8 + 20U, // CLSv2i32 + 28U, // CLSv4i16 + 32U, // CLSv4i32 + 36U, // CLSv8i16 + 40U, // CLSv8i8 + 16U, // CLZWr + 16U, // CLZXr + 0U, // CLZ_ZPmZ_B + 4U, // CLZ_ZPmZ_D + 0U, // CLZ_ZPmZ_H + 8U, // CLZ_ZPmZ_S + 12U, // CLZv16i8 + 20U, // CLZv2i32 + 28U, // CLZv4i16 + 32U, // CLZv4i32 + 36U, // CLZv8i16 + 40U, // CLZv8i8 + 397384U, // CMEQv16i8 + 108U, // CMEQv16i8rz + 1580U, // CMEQv1i64 + 112U, // CMEQv1i64rz + 462924U, // CMEQv2i32 + 116U, // CMEQv2i32rz + 135220U, // CMEQv2i64 + 120U, // CMEQv2i64rz + 528464U, // CMEQv4i16 + 124U, // CMEQv4i16rz + 200760U, // CMEQv4i32 + 128U, // CMEQv4i32rz + 266300U, // CMEQv8i16 + 132U, // CMEQv8i16rz + 594004U, // CMEQv8i8 + 136U, // CMEQv8i8rz + 397384U, // CMGEv16i8 + 108U, // CMGEv16i8rz + 1580U, // CMGEv1i64 + 112U, // CMGEv1i64rz + 462924U, // CMGEv2i32 + 116U, // CMGEv2i32rz + 135220U, // CMGEv2i64 + 120U, // CMGEv2i64rz + 528464U, // CMGEv4i16 + 124U, // CMGEv4i16rz + 200760U, // CMGEv4i32 + 128U, // CMGEv4i32rz + 266300U, // CMGEv8i16 + 132U, // CMGEv8i16rz + 594004U, // CMGEv8i8 + 136U, // CMGEv8i8rz + 397384U, // CMGTv16i8 + 108U, // CMGTv16i8rz + 1580U, // CMGTv1i64 + 112U, // CMGTv1i64rz + 462924U, // CMGTv2i32 + 116U, // CMGTv2i32rz + 135220U, // CMGTv2i64 + 120U, // CMGTv2i64rz + 528464U, // CMGTv4i16 + 124U, // CMGTv4i16rz + 200760U, // CMGTv4i32 + 128U, // CMGTv4i32rz + 266300U, // CMGTv8i16 + 132U, // CMGTv8i16rz + 594004U, // CMGTv8i8 + 136U, // CMGTv8i8rz + 397384U, // CMHIv16i8 + 1580U, // CMHIv1i64 + 462924U, // CMHIv2i32 + 135220U, // CMHIv2i64 + 528464U, // CMHIv4i16 + 200760U, // CMHIv4i32 + 266300U, // CMHIv8i16 + 594004U, // CMHIv8i8 + 397384U, // CMHSv16i8 + 1580U, // CMHSv1i64 + 462924U, // CMHSv2i32 + 135220U, // CMHSv2i64 + 528464U, // CMHSv4i16 + 200760U, // CMHSv4i32 + 266300U, // CMHSv8i16 + 594004U, // CMHSv8i8 + 46222476U, // CMLA_ZZZI_H + 579798060U, // CMLA_ZZZI_S + 1250816U, // CMLA_ZZZ_B + 50397740U, // CMLA_ZZZ_D + 1250956U, // CMLA_ZZZ_H + 50398252U, // CMLA_ZZZ_S + 108U, // CMLEv16i8rz + 112U, // CMLEv1i64rz + 116U, // CMLEv2i32rz + 120U, // CMLEv2i64rz + 124U, // CMLEv4i16rz + 128U, // CMLEv4i32rz + 132U, // CMLEv8i16rz + 136U, // CMLEv8i8rz + 108U, // CMLTv16i8rz + 112U, // CMLTv1i64rz + 116U, // CMLTv2i32rz + 120U, // CMLTv2i64rz + 124U, // CMLTv4i16rz + 128U, // CMLTv4i32rz + 132U, // CMLTv8i16rz + 136U, // CMLTv8i8rz + 70748U, // CMPEQ_PPzZI_B + 68700U, // CMPEQ_PPzZI_D + 726596U, // CMPEQ_PPzZI_H + 71772U, // CMPEQ_PPzZI_S + 4265052U, // CMPEQ_PPzZZ_B + 8457308U, // CMPEQ_PPzZZ_D + 12916292U, // CMPEQ_PPzZZ_H + 16848988U, // CMPEQ_PPzZZ_S + 8459356U, // CMPEQ_WIDE_PPzZZ_B + 792132U, // CMPEQ_WIDE_PPzZZ_H + 8460380U, // CMPEQ_WIDE_PPzZZ_S + 70748U, // CMPGE_PPzZI_B + 68700U, // CMPGE_PPzZI_D + 726596U, // CMPGE_PPzZI_H + 71772U, // CMPGE_PPzZI_S + 4265052U, // CMPGE_PPzZZ_B + 8457308U, // CMPGE_PPzZZ_D + 12916292U, // CMPGE_PPzZZ_H + 16848988U, // CMPGE_PPzZZ_S + 8459356U, // CMPGE_WIDE_PPzZZ_B + 792132U, // CMPGE_WIDE_PPzZZ_H + 8460380U, // CMPGE_WIDE_PPzZZ_S + 70748U, // CMPGT_PPzZI_B + 68700U, // CMPGT_PPzZI_D + 726596U, // CMPGT_PPzZI_H + 71772U, // CMPGT_PPzZI_S + 4265052U, // CMPGT_PPzZZ_B + 8457308U, // CMPGT_PPzZZ_D + 12916292U, // CMPGT_PPzZZ_H + 16848988U, // CMPGT_PPzZZ_S + 8459356U, // CMPGT_WIDE_PPzZZ_B + 792132U, // CMPGT_WIDE_PPzZZ_H + 8460380U, // CMPGT_WIDE_PPzZZ_S + 58791004U, // CMPHI_PPzZI_B + 58788956U, // CMPHI_PPzZI_D + 1316420U, // CMPHI_PPzZI_H + 58792028U, // CMPHI_PPzZI_S + 4265052U, // CMPHI_PPzZZ_B + 8457308U, // CMPHI_PPzZZ_D + 12916292U, // CMPHI_PPzZZ_H + 16848988U, // CMPHI_PPzZZ_S + 8459356U, // CMPHI_WIDE_PPzZZ_B + 792132U, // CMPHI_WIDE_PPzZZ_H + 8460380U, // CMPHI_WIDE_PPzZZ_S + 58791004U, // CMPHS_PPzZI_B + 58788956U, // CMPHS_PPzZI_D + 1316420U, // CMPHS_PPzZI_H + 58792028U, // CMPHS_PPzZI_S + 4265052U, // CMPHS_PPzZZ_B + 8457308U, // CMPHS_PPzZZ_D + 12916292U, // CMPHS_PPzZZ_H + 16848988U, // CMPHS_PPzZZ_S + 8459356U, // CMPHS_WIDE_PPzZZ_B + 792132U, // CMPHS_WIDE_PPzZZ_H + 8460380U, // CMPHS_WIDE_PPzZZ_S + 70748U, // CMPLE_PPzZI_B + 68700U, // CMPLE_PPzZI_D + 726596U, // CMPLE_PPzZI_H + 71772U, // CMPLE_PPzZI_S + 8459356U, // CMPLE_WIDE_PPzZZ_B + 792132U, // CMPLE_WIDE_PPzZZ_H + 8460380U, // CMPLE_WIDE_PPzZZ_S + 58791004U, // CMPLO_PPzZI_B + 58788956U, // CMPLO_PPzZI_D + 1316420U, // CMPLO_PPzZI_H + 58792028U, // CMPLO_PPzZI_S + 8459356U, // CMPLO_WIDE_PPzZZ_B + 792132U, // CMPLO_WIDE_PPzZZ_H + 8460380U, // CMPLO_WIDE_PPzZZ_S + 58791004U, // CMPLS_PPzZI_B + 58788956U, // CMPLS_PPzZI_D + 1316420U, // CMPLS_PPzZI_H + 58792028U, // CMPLS_PPzZI_S + 8459356U, // CMPLS_WIDE_PPzZZ_B + 792132U, // CMPLS_WIDE_PPzZZ_H + 8460380U, // CMPLS_WIDE_PPzZZ_S + 70748U, // CMPLT_PPzZI_B + 68700U, // CMPLT_PPzZI_D + 726596U, // CMPLT_PPzZI_H + 71772U, // CMPLT_PPzZI_S + 8459356U, // CMPLT_WIDE_PPzZZ_B + 792132U, // CMPLT_WIDE_PPzZZ_H + 8460380U, // CMPLT_WIDE_PPzZZ_S + 70748U, // CMPNE_PPzZI_B + 68700U, // CMPNE_PPzZI_D + 726596U, // CMPNE_PPzZI_H + 71772U, // CMPNE_PPzZI_S + 4265052U, // CMPNE_PPzZZ_B + 8457308U, // CMPNE_PPzZZ_D + 12916292U, // CMPNE_PPzZZ_H + 16848988U, // CMPNE_PPzZZ_S + 8459356U, // CMPNE_WIDE_PPzZZ_B + 792132U, // CMPNE_WIDE_PPzZZ_H + 8460380U, // CMPNE_WIDE_PPzZZ_S + 397384U, // CMTSTv16i8 + 1580U, // CMTSTv1i64 + 462924U, // CMTSTv2i32 + 135220U, // CMTSTv2i64 + 528464U, // CMTSTv4i16 + 200760U, // CMTSTv4i32 + 266300U, // CMTSTv8i16 + 594004U, // CMTSTv8i8 + 0U, // CNOT_ZPmZ_B + 4U, // CNOT_ZPmZ_D + 0U, // CNOT_ZPmZ_H + 8U, // CNOT_ZPmZ_S + 144U, // CNTB_XPiI + 144U, // CNTD_XPiI + 144U, // CNTH_XPiI + 5164U, // CNTP_XPP_B + 3116U, // CNTP_XPP_D + 2604U, // CNTP_XPP_H + 6188U, // CNTP_XPP_S + 144U, // CNTW_XPiI + 0U, // CNT_ZPmZ_B + 4U, // CNT_ZPmZ_D + 0U, // CNT_ZPmZ_H + 8U, // CNT_ZPmZ_S + 12U, // CNTv16i8 + 40U, // CNTv8i8 + 3116U, // COMPACT_ZPZ_D + 6188U, // COMPACT_ZPZ_S + 148U, // CPY_ZPmI_B + 152U, // CPY_ZPmI_D + 0U, // CPY_ZPmI_H + 156U, // CPY_ZPmI_S + 160U, // CPY_ZPmR_B + 160U, // CPY_ZPmR_D + 0U, // CPY_ZPmR_H + 160U, // CPY_ZPmR_S + 160U, // CPY_ZPmV_B + 160U, // CPY_ZPmV_D + 0U, // CPY_ZPmV_H + 160U, // CPY_ZPmV_S + 20060U, // CPY_ZPzI_B + 20572U, // CPY_ZPzI_D + 164U, // CPY_ZPzI_H + 21084U, // CPY_ZPzI_S + 21672U, // CPYi16 + 21676U, // CPYi32 + 21680U, // CPYi64 + 21684U, // CPYi8 + 1580U, // CRC32Brr + 1580U, // CRC32CBrr + 1580U, // CRC32CHrr + 1580U, // CRC32CWrr + 1580U, // CRC32CXrr + 1580U, // CRC32Hrr + 1580U, // CRC32Wrr + 1580U, // CRC32Xrr + 37815852U, // CSELWr + 37815852U, // CSELXr + 37815852U, // CSINCWr + 37815852U, // CSINCXr + 37815852U, // CSINVWr + 37815852U, // CSINVXr + 37815852U, // CSNEGWr + 37815852U, // CSNEGXr + 16U, // CTERMEQ_WW + 16U, // CTERMEQ_XX + 16U, // CTERMNE_WW + 16U, // CTERMNE_XX + 0U, // DCPS1 + 0U, // DCPS2 + 0U, // DCPS3 + 0U, // DECB_XPiI + 0U, // DECD_XPiI + 0U, // DECD_ZPiI + 0U, // DECH_XPiI + 0U, // DECH_ZPiI + 16U, // DECP_XP_B + 16U, // DECP_XP_D + 16U, // DECP_XP_H + 16U, // DECP_XP_S + 16U, // DECP_ZP_D + 0U, // DECP_ZP_H + 16U, // DECP_ZP_S + 0U, // DECW_XPiI + 0U, // DECW_ZPiI + 0U, // DMB + 0U, // DRPS + 0U, // DSB + 0U, // DSBnXS + 0U, // DUPM_ZI + 0U, // DUP_ZI_B + 0U, // DUP_ZI_D + 0U, // DUP_ZI_H + 0U, // DUP_ZI_S + 16U, // DUP_ZR_B + 16U, // DUP_ZR_D + 0U, // DUP_ZR_H + 16U, // DUP_ZR_S + 184U, // DUP_ZZI_B + 184U, // DUP_ZZI_D + 0U, // DUP_ZZI_H + 0U, // DUP_ZZI_Q + 184U, // DUP_ZZI_S + 16U, // DUPv16i8gpr + 21684U, // DUPv16i8lane + 16U, // DUPv2i32gpr + 21676U, // DUPv2i32lane + 16U, // DUPv2i64gpr + 21680U, // DUPv2i64lane + 16U, // DUPv4i16gpr + 21672U, // DUPv4i16lane + 16U, // DUPv4i32gpr + 21676U, // DUPv4i32lane + 16U, // DUPv8i16gpr + 21672U, // DUPv8i16lane + 16U, // DUPv8i8gpr + 21684U, // DUPv8i8lane + 7212U, // EONWrs + 7212U, // EONXrs + 290263112U, // EOR3 + 8457260U, // EOR3_ZZZZ + 0U, // EORBT_ZZZ_B + 556U, // EORBT_ZZZ_D + 140U, // EORBT_ZZZ_H + 1068U, // EORBT_ZZZ_S + 4265052U, // EORS_PPzPP + 0U, // EORTB_ZZZ_B + 556U, // EORTB_ZZZ_D + 140U, // EORTB_ZZZ_H + 1068U, // EORTB_ZZZ_S + 0U, // EORV_VPZ_B + 0U, // EORV_VPZ_D + 0U, // EORV_VPZ_H + 0U, // EORV_VPZ_S + 17964U, // EORWri + 7212U, // EORWrs + 18476U, // EORXri + 7212U, // EORXrs + 4265052U, // EOR_PPzPP + 18476U, // EOR_ZI + 4265024U, // EOR_ZPmZ_B + 8457280U, // EOR_ZPmZ_D + 12916292U, // EOR_ZPmZ_H + 16848960U, // EOR_ZPmZ_S + 3116U, // EOR_ZZZ + 397384U, // EORv16i8 + 594004U, // EORv8i8 + 0U, // ERET + 0U, // ERETAA + 0U, // ERETAB + 22080U, // EXTRACT_ZPMXI_H_B + 22080U, // EXTRACT_ZPMXI_H_D + 188U, // EXTRACT_ZPMXI_H_H + 188U, // EXTRACT_ZPMXI_H_Q + 22080U, // EXTRACT_ZPMXI_H_S + 22592U, // EXTRACT_ZPMXI_V_B + 22592U, // EXTRACT_ZPMXI_V_D + 192U, // EXTRACT_ZPMXI_V_H + 192U, // EXTRACT_ZPMXI_V_Q + 22592U, // EXTRACT_ZPMXI_V_S + 67116U, // EXTRWrri + 67116U, // EXTRXrri + 58790956U, // EXT_ZZI + 197U, // EXT_ZZI_B + 856136U, // EXTv16i8 + 1380436U, // EXTv8i8 + 1580U, // FABD16 + 1580U, // FABD32 + 1580U, // FABD64 + 8457280U, // FABD_ZPmZ_D + 12916292U, // FABD_ZPmZ_H + 16848960U, // FABD_ZPmZ_S + 462924U, // FABDv2f32 + 135220U, // FABDv2f64 + 528464U, // FABDv4f16 + 200760U, // FABDv4f32 + 266300U, // FABDv8f16 + 16U, // FABSDr + 16U, // FABSHr + 16U, // FABSSr + 4U, // FABS_ZPmZ_D + 0U, // FABS_ZPmZ_H + 8U, // FABS_ZPmZ_S + 20U, // FABSv2f32 + 24U, // FABSv2f64 + 28U, // FABSv4f16 + 32U, // FABSv4f32 + 36U, // FABSv8f16 + 1580U, // FACGE16 + 1580U, // FACGE32 + 1580U, // FACGE64 + 8457308U, // FACGE_PPzZZ_D + 12916292U, // FACGE_PPzZZ_H + 16848988U, // FACGE_PPzZZ_S + 462924U, // FACGEv2f32 + 135220U, // FACGEv2f64 + 528464U, // FACGEv4f16 + 200760U, // FACGEv4f32 + 266300U, // FACGEv8f16 + 1580U, // FACGT16 + 1580U, // FACGT32 + 1580U, // FACGT64 + 8457308U, // FACGT_PPzZZ_D + 12916292U, // FACGT_PPzZZ_H + 16848988U, // FACGT_PPzZZ_S + 462924U, // FACGTv2f32 + 135220U, // FACGTv2f64 + 528464U, // FACGTv4f16 + 200760U, // FACGTv4f32 + 266300U, // FACGTv8f16 + 0U, // FADDA_VPZ_D + 140U, // FADDA_VPZ_H + 0U, // FADDA_VPZ_S + 1580U, // FADDDrr + 1580U, // FADDHrr + 8457280U, // FADDP_ZPmZZ_D + 12916292U, // FADDP_ZPmZZ_H + 16848960U, // FADDP_ZPmZZ_S + 462924U, // FADDPv2f32 + 135220U, // FADDPv2f64 + 200U, // FADDPv2i16p + 20U, // FADDPv2i32p + 24U, // FADDPv2i64p + 528464U, // FADDPv4f16 + 200760U, // FADDPv4f32 + 266300U, // FADDPv8f16 + 1580U, // FADDSrr + 0U, // FADDV_VPZ_D + 0U, // FADDV_VPZ_H + 0U, // FADDV_VPZ_S + 62983232U, // FADD_ZPmI_D + 1447492U, // FADD_ZPmI_H + 62986304U, // FADD_ZPmI_S + 8457280U, // FADD_ZPmZ_D + 12916292U, // FADD_ZPmZ_H + 16848960U, // FADD_ZPmZ_S + 3116U, // FADD_ZZZ_D + 68U, // FADD_ZZZ_H + 6188U, // FADD_ZZZ_S + 462924U, // FADDv2f32 + 135220U, // FADDv2f64 + 528464U, // FADDv4f16 + 200760U, // FADDv4f32 + 266300U, // FADDv8f16 + 813763648U, // FCADD_ZPmZ_D + 1116018244U, // FCADD_ZPmZ_H + 822155328U, // FCADD_ZPmZ_S + 35065932U, // FCADDv2f32 + 35131444U, // FCADDv2f64 + 35197008U, // FCADDv4f16 + 35262520U, // FCADDv4f32 + 35328060U, // FCADDv8f16 + 37815852U, // FCCMPDrr + 37815852U, // FCCMPEDrr + 37815852U, // FCCMPEHrr + 37815852U, // FCCMPESrr + 37815852U, // FCCMPHrr + 37815852U, // FCCMPSrr + 1580U, // FCMEQ16 + 1580U, // FCMEQ32 + 1580U, // FCMEQ64 + 1838172U, // FCMEQ_PPzZ0_D + 23108U, // FCMEQ_PPzZ0_H + 1841244U, // FCMEQ_PPzZ0_S + 8457308U, // FCMEQ_PPzZZ_D + 12916292U, // FCMEQ_PPzZZ_H + 16848988U, // FCMEQ_PPzZZ_S + 204U, // FCMEQv1i16rz + 204U, // FCMEQv1i32rz + 204U, // FCMEQv1i64rz + 462924U, // FCMEQv2f32 + 135220U, // FCMEQv2f64 + 208U, // FCMEQv2i32rz + 212U, // FCMEQv2i64rz + 528464U, // FCMEQv4f16 + 200760U, // FCMEQv4f32 + 216U, // FCMEQv4i16rz + 220U, // FCMEQv4i32rz + 266300U, // FCMEQv8f16 + 224U, // FCMEQv8i16rz + 1580U, // FCMGE16 + 1580U, // FCMGE32 + 1580U, // FCMGE64 + 1838172U, // FCMGE_PPzZ0_D + 23108U, // FCMGE_PPzZ0_H + 1841244U, // FCMGE_PPzZ0_S + 8457308U, // FCMGE_PPzZZ_D + 12916292U, // FCMGE_PPzZZ_H + 16848988U, // FCMGE_PPzZZ_S + 204U, // FCMGEv1i16rz + 204U, // FCMGEv1i32rz + 204U, // FCMGEv1i64rz + 462924U, // FCMGEv2f32 + 135220U, // FCMGEv2f64 + 208U, // FCMGEv2i32rz + 212U, // FCMGEv2i64rz + 528464U, // FCMGEv4f16 + 200760U, // FCMGEv4f32 + 216U, // FCMGEv4i16rz + 220U, // FCMGEv4i32rz + 266300U, // FCMGEv8f16 + 224U, // FCMGEv8i16rz + 1580U, // FCMGT16 + 1580U, // FCMGT32 + 1580U, // FCMGT64 + 1838172U, // FCMGT_PPzZ0_D + 23108U, // FCMGT_PPzZ0_H + 1841244U, // FCMGT_PPzZ0_S + 8457308U, // FCMGT_PPzZZ_D + 12916292U, // FCMGT_PPzZZ_H + 16848988U, // FCMGT_PPzZZ_S + 204U, // FCMGTv1i16rz + 204U, // FCMGTv1i32rz + 204U, // FCMGTv1i64rz + 462924U, // FCMGTv2f32 + 135220U, // FCMGTv2f64 + 208U, // FCMGTv2i32rz + 212U, // FCMGTv2i64rz + 528464U, // FCMGTv4f16 + 200760U, // FCMGTv4f32 + 216U, // FCMGTv4i16rz + 220U, // FCMGTv4i32rz + 266300U, // FCMGTv8f16 + 224U, // FCMGTv8i16rz + 3019964992U, // FCMLA_ZPmZZ_D + 580720268U, // FCMLA_ZPmZZ_H + 3024159808U, // FCMLA_ZPmZZ_S + 46222476U, // FCMLA_ZZZI_H + 579798060U, // FCMLA_ZZZI_S + 51843660U, // FCMLAv2f32 + 51909172U, // FCMLAv2f64 + 51974736U, // FCMLAv4f16 + 2979009104U, // FCMLAv4f16_indexed + 52040248U, // FCMLAv4f32 + 2979926584U, // FCMLAv4f32_indexed + 52105788U, // FCMLAv8f16 + 2979009084U, // FCMLAv8f16_indexed + 1838172U, // FCMLE_PPzZ0_D + 23108U, // FCMLE_PPzZ0_H + 1841244U, // FCMLE_PPzZ0_S + 204U, // FCMLEv1i16rz + 204U, // FCMLEv1i32rz + 204U, // FCMLEv1i64rz + 208U, // FCMLEv2i32rz + 212U, // FCMLEv2i64rz + 216U, // FCMLEv4i16rz + 220U, // FCMLEv4i32rz + 224U, // FCMLEv8i16rz + 1838172U, // FCMLT_PPzZ0_D + 23108U, // FCMLT_PPzZ0_H + 1841244U, // FCMLT_PPzZ0_S + 204U, // FCMLTv1i16rz + 204U, // FCMLTv1i32rz + 204U, // FCMLTv1i64rz + 208U, // FCMLTv2i32rz + 212U, // FCMLTv2i64rz + 216U, // FCMLTv4i16rz + 220U, // FCMLTv4i32rz + 224U, // FCMLTv8i16rz + 1838172U, // FCMNE_PPzZ0_D + 23108U, // FCMNE_PPzZ0_H + 1841244U, // FCMNE_PPzZ0_S + 8457308U, // FCMNE_PPzZZ_D + 12916292U, // FCMNE_PPzZZ_H + 16848988U, // FCMNE_PPzZZ_S + 0U, // FCMPDri + 16U, // FCMPDrr + 0U, // FCMPEDri + 16U, // FCMPEDrr + 0U, // FCMPEHri + 16U, // FCMPEHrr + 0U, // FCMPESri + 16U, // FCMPESrr + 0U, // FCMPHri + 16U, // FCMPHrr + 0U, // FCMPSri + 16U, // FCMPSrr + 8457308U, // FCMUO_PPzZZ_D + 12916292U, // FCMUO_PPzZZ_H + 16848988U, // FCMUO_PPzZZ_S + 228U, // FCPY_ZPmI_D + 1U, // FCPY_ZPmI_H + 228U, // FCPY_ZPmI_S + 37815852U, // FCSELDrrr + 37815852U, // FCSELHrrr + 37815852U, // FCSELSrrr + 16U, // FCVTASUWDr + 16U, // FCVTASUWHr + 16U, // FCVTASUWSr + 16U, // FCVTASUXDr + 16U, // FCVTASUXHr + 16U, // FCVTASUXSr + 16U, // FCVTASv1f16 + 16U, // FCVTASv1i32 + 16U, // FCVTASv1i64 + 20U, // FCVTASv2f32 + 24U, // FCVTASv2f64 + 28U, // FCVTASv4f16 + 32U, // FCVTASv4f32 + 36U, // FCVTASv8f16 + 16U, // FCVTAUUWDr + 16U, // FCVTAUUWHr + 16U, // FCVTAUUWSr + 16U, // FCVTAUUXDr + 16U, // FCVTAUUXHr + 16U, // FCVTAUUXSr + 16U, // FCVTAUv1f16 + 16U, // FCVTAUv1i32 + 16U, // FCVTAUv1i64 + 20U, // FCVTAUv2f32 + 24U, // FCVTAUv2f64 + 28U, // FCVTAUv4f16 + 32U, // FCVTAUv4f32 + 36U, // FCVTAUv8f16 + 16U, // FCVTDHr + 16U, // FCVTDSr + 16U, // FCVTHDr + 16U, // FCVTHSr + 140U, // FCVTLT_ZPmZ_HtoS + 8U, // FCVTLT_ZPmZ_StoD + 20U, // FCVTLv2i32 + 28U, // FCVTLv4i16 + 32U, // FCVTLv4i32 + 36U, // FCVTLv8i16 + 16U, // FCVTMSUWDr + 16U, // FCVTMSUWHr + 16U, // FCVTMSUWSr + 16U, // FCVTMSUXDr + 16U, // FCVTMSUXHr + 16U, // FCVTMSUXSr + 16U, // FCVTMSv1f16 + 16U, // FCVTMSv1i32 + 16U, // FCVTMSv1i64 + 20U, // FCVTMSv2f32 + 24U, // FCVTMSv2f64 + 28U, // FCVTMSv4f16 + 32U, // FCVTMSv4f32 + 36U, // FCVTMSv8f16 + 16U, // FCVTMUUWDr + 16U, // FCVTMUUWHr + 16U, // FCVTMUUWSr + 16U, // FCVTMUUXDr + 16U, // FCVTMUUXHr + 16U, // FCVTMUUXSr + 16U, // FCVTMUv1f16 + 16U, // FCVTMUv1i32 + 16U, // FCVTMUv1i64 + 20U, // FCVTMUv2f32 + 24U, // FCVTMUv2f64 + 28U, // FCVTMUv4f16 + 32U, // FCVTMUv4f32 + 36U, // FCVTMUv8f16 + 16U, // FCVTNSUWDr + 16U, // FCVTNSUWHr + 16U, // FCVTNSUWSr + 16U, // FCVTNSUXDr + 16U, // FCVTNSUXHr + 16U, // FCVTNSUXSr + 16U, // FCVTNSv1f16 + 16U, // FCVTNSv1i32 + 16U, // FCVTNSv1i64 + 20U, // FCVTNSv2f32 + 24U, // FCVTNSv2f64 + 28U, // FCVTNSv4f16 + 32U, // FCVTNSv4f32 + 36U, // FCVTNSv8f16 + 4U, // FCVTNT_ZPmZ_DtoS + 0U, // FCVTNT_ZPmZ_StoH + 16U, // FCVTNUUWDr + 16U, // FCVTNUUWHr + 16U, // FCVTNUUWSr + 16U, // FCVTNUUXDr + 16U, // FCVTNUUXHr + 16U, // FCVTNUUXSr + 16U, // FCVTNUv1f16 + 16U, // FCVTNUv1i32 + 16U, // FCVTNUv1i64 + 20U, // FCVTNUv2f32 + 24U, // FCVTNUv2f64 + 28U, // FCVTNUv4f16 + 32U, // FCVTNUv4f32 + 36U, // FCVTNUv8f16 + 24U, // FCVTNv2i32 + 32U, // FCVTNv4i16 + 24U, // FCVTNv4i32 + 32U, // FCVTNv8i16 + 16U, // FCVTPSUWDr + 16U, // FCVTPSUWHr + 16U, // FCVTPSUWSr + 16U, // FCVTPSUXDr + 16U, // FCVTPSUXHr + 16U, // FCVTPSUXSr + 16U, // FCVTPSv1f16 + 16U, // FCVTPSv1i32 + 16U, // FCVTPSv1i64 + 20U, // FCVTPSv2f32 + 24U, // FCVTPSv2f64 + 28U, // FCVTPSv4f16 + 32U, // FCVTPSv4f32 + 36U, // FCVTPSv8f16 + 16U, // FCVTPUUWDr + 16U, // FCVTPUUWHr + 16U, // FCVTPUUWSr + 16U, // FCVTPUUXDr + 16U, // FCVTPUUXHr + 16U, // FCVTPUUXSr + 16U, // FCVTPUv1f16 + 16U, // FCVTPUv1i32 + 16U, // FCVTPUv1i64 + 20U, // FCVTPUv2f32 + 24U, // FCVTPUv2f64 + 28U, // FCVTPUv4f16 + 32U, // FCVTPUv4f32 + 36U, // FCVTPUv8f16 + 16U, // FCVTSDr + 16U, // FCVTSHr + 4U, // FCVTXNT_ZPmZ_DtoS + 16U, // FCVTXNv1i64 + 24U, // FCVTXNv2f32 + 24U, // FCVTXNv4f32 + 4U, // FCVTX_ZPmZ_DtoS + 1580U, // FCVTZSSWDri + 1580U, // FCVTZSSWHri + 1580U, // FCVTZSSWSri + 1580U, // FCVTZSSXDri + 1580U, // FCVTZSSXHri + 1580U, // FCVTZSSXSri + 16U, // FCVTZSUWDr + 16U, // FCVTZSUWHr + 16U, // FCVTZSUWSr + 16U, // FCVTZSUXDr + 16U, // FCVTZSUXHr + 16U, // FCVTZSUXSr + 4U, // FCVTZS_ZPmZ_DtoD + 4U, // FCVTZS_ZPmZ_DtoS + 140U, // FCVTZS_ZPmZ_HtoD + 0U, // FCVTZS_ZPmZ_HtoH + 140U, // FCVTZS_ZPmZ_HtoS + 8U, // FCVTZS_ZPmZ_StoD + 8U, // FCVTZS_ZPmZ_StoS + 1580U, // FCVTZSd + 1580U, // FCVTZSh + 1580U, // FCVTZSs + 16U, // FCVTZSv1f16 + 16U, // FCVTZSv1i32 + 16U, // FCVTZSv1i64 + 20U, // FCVTZSv2f32 + 24U, // FCVTZSv2f64 + 1612U, // FCVTZSv2i32_shift + 1588U, // FCVTZSv2i64_shift + 28U, // FCVTZSv4f16 + 32U, // FCVTZSv4f32 + 1616U, // FCVTZSv4i16_shift + 1592U, // FCVTZSv4i32_shift + 36U, // FCVTZSv8f16 + 1596U, // FCVTZSv8i16_shift + 1580U, // FCVTZUSWDri + 1580U, // FCVTZUSWHri + 1580U, // FCVTZUSWSri + 1580U, // FCVTZUSXDri + 1580U, // FCVTZUSXHri + 1580U, // FCVTZUSXSri + 16U, // FCVTZUUWDr + 16U, // FCVTZUUWHr + 16U, // FCVTZUUWSr + 16U, // FCVTZUUXDr + 16U, // FCVTZUUXHr + 16U, // FCVTZUUXSr + 4U, // FCVTZU_ZPmZ_DtoD + 4U, // FCVTZU_ZPmZ_DtoS + 140U, // FCVTZU_ZPmZ_HtoD + 0U, // FCVTZU_ZPmZ_HtoH + 140U, // FCVTZU_ZPmZ_HtoS + 8U, // FCVTZU_ZPmZ_StoD + 8U, // FCVTZU_ZPmZ_StoS + 1580U, // FCVTZUd + 1580U, // FCVTZUh + 1580U, // FCVTZUs + 16U, // FCVTZUv1f16 + 16U, // FCVTZUv1i32 + 16U, // FCVTZUv1i64 + 20U, // FCVTZUv2f32 + 24U, // FCVTZUv2f64 + 1612U, // FCVTZUv2i32_shift + 1588U, // FCVTZUv2i64_shift + 28U, // FCVTZUv4f16 + 32U, // FCVTZUv4f32 + 1616U, // FCVTZUv4i16_shift + 1592U, // FCVTZUv4i32_shift + 36U, // FCVTZUv8f16 + 1596U, // FCVTZUv8i16_shift + 1U, // FCVT_ZPmZ_DtoH + 4U, // FCVT_ZPmZ_DtoS + 140U, // FCVT_ZPmZ_HtoD + 140U, // FCVT_ZPmZ_HtoS + 8U, // FCVT_ZPmZ_StoD + 0U, // FCVT_ZPmZ_StoH + 1580U, // FDIVDrr + 1580U, // FDIVHrr + 8457280U, // FDIVR_ZPmZ_D + 12916292U, // FDIVR_ZPmZ_H + 16848960U, // FDIVR_ZPmZ_S + 1580U, // FDIVSrr + 8457280U, // FDIV_ZPmZ_D + 12916292U, // FDIV_ZPmZ_H + 16848960U, // FDIV_ZPmZ_S + 462924U, // FDIVv2f32 + 135220U, // FDIVv2f64 + 528464U, // FDIVv4f16 + 200760U, // FDIVv4f32 + 266300U, // FDIVv8f16 + 1U, // FDUP_ZI_D + 0U, // FDUP_ZI_H + 1U, // FDUP_ZI_S + 16U, // FEXPA_ZZ_D + 0U, // FEXPA_ZZ_H + 16U, // FEXPA_ZZ_S + 16U, // FJCVTZS + 4U, // FLOGB_ZPmZ_D + 0U, // FLOGB_ZPmZ_H + 8U, // FLOGB_ZPmZ_S + 67116U, // FMADDDrrr + 67116U, // FMADDHrrr + 67116U, // FMADDSrrr + 67174976U, // FMAD_ZPmZZ_D + 14489228U, // FMAD_ZPmZZ_H + 71369792U, // FMAD_ZPmZZ_S + 1580U, // FMAXDrr + 1580U, // FMAXHrr + 1580U, // FMAXNMDrr + 1580U, // FMAXNMHrr + 8457280U, // FMAXNMP_ZPmZZ_D + 12916292U, // FMAXNMP_ZPmZZ_H + 16848960U, // FMAXNMP_ZPmZZ_S + 462924U, // FMAXNMPv2f32 + 135220U, // FMAXNMPv2f64 + 200U, // FMAXNMPv2i16p + 20U, // FMAXNMPv2i32p + 24U, // FMAXNMPv2i64p + 528464U, // FMAXNMPv4f16 + 200760U, // FMAXNMPv4f32 + 266300U, // FMAXNMPv8f16 + 1580U, // FMAXNMSrr + 0U, // FMAXNMV_VPZ_D + 0U, // FMAXNMV_VPZ_H + 0U, // FMAXNMV_VPZ_S + 28U, // FMAXNMVv4i16v + 32U, // FMAXNMVv4i32v + 36U, // FMAXNMVv8i16v + 75566144U, // FMAXNM_ZPmI_D + 2037316U, // FMAXNM_ZPmI_H + 75569216U, // FMAXNM_ZPmI_S + 8457280U, // FMAXNM_ZPmZ_D + 12916292U, // FMAXNM_ZPmZ_H + 16848960U, // FMAXNM_ZPmZ_S + 462924U, // FMAXNMv2f32 + 135220U, // FMAXNMv2f64 + 528464U, // FMAXNMv4f16 + 200760U, // FMAXNMv4f32 + 266300U, // FMAXNMv8f16 + 8457280U, // FMAXP_ZPmZZ_D + 12916292U, // FMAXP_ZPmZZ_H + 16848960U, // FMAXP_ZPmZZ_S + 462924U, // FMAXPv2f32 + 135220U, // FMAXPv2f64 + 200U, // FMAXPv2i16p + 20U, // FMAXPv2i32p + 24U, // FMAXPv2i64p + 528464U, // FMAXPv4f16 + 200760U, // FMAXPv4f32 + 266300U, // FMAXPv8f16 + 1580U, // FMAXSrr + 0U, // FMAXV_VPZ_D + 0U, // FMAXV_VPZ_H + 0U, // FMAXV_VPZ_S + 28U, // FMAXVv4i16v + 32U, // FMAXVv4i32v + 36U, // FMAXVv8i16v + 75566144U, // FMAX_ZPmI_D + 2037316U, // FMAX_ZPmI_H + 75569216U, // FMAX_ZPmI_S + 8457280U, // FMAX_ZPmZ_D + 12916292U, // FMAX_ZPmZ_H + 16848960U, // FMAX_ZPmZ_S + 462924U, // FMAXv2f32 + 135220U, // FMAXv2f64 + 528464U, // FMAXv4f16 + 200760U, // FMAXv4f32 + 266300U, // FMAXv8f16 + 1580U, // FMINDrr + 1580U, // FMINHrr + 1580U, // FMINNMDrr + 1580U, // FMINNMHrr + 8457280U, // FMINNMP_ZPmZZ_D + 12916292U, // FMINNMP_ZPmZZ_H + 16848960U, // FMINNMP_ZPmZZ_S + 462924U, // FMINNMPv2f32 + 135220U, // FMINNMPv2f64 + 200U, // FMINNMPv2i16p + 20U, // FMINNMPv2i32p + 24U, // FMINNMPv2i64p + 528464U, // FMINNMPv4f16 + 200760U, // FMINNMPv4f32 + 266300U, // FMINNMPv8f16 + 1580U, // FMINNMSrr + 0U, // FMINNMV_VPZ_D + 0U, // FMINNMV_VPZ_H + 0U, // FMINNMV_VPZ_S + 28U, // FMINNMVv4i16v + 32U, // FMINNMVv4i32v + 36U, // FMINNMVv8i16v + 75566144U, // FMINNM_ZPmI_D + 2037316U, // FMINNM_ZPmI_H + 75569216U, // FMINNM_ZPmI_S + 8457280U, // FMINNM_ZPmZ_D + 12916292U, // FMINNM_ZPmZ_H + 16848960U, // FMINNM_ZPmZ_S + 462924U, // FMINNMv2f32 + 135220U, // FMINNMv2f64 + 528464U, // FMINNMv4f16 + 200760U, // FMINNMv4f32 + 266300U, // FMINNMv8f16 + 8457280U, // FMINP_ZPmZZ_D + 12916292U, // FMINP_ZPmZZ_H + 16848960U, // FMINP_ZPmZZ_S + 462924U, // FMINPv2f32 + 135220U, // FMINPv2f64 + 200U, // FMINPv2i16p + 20U, // FMINPv2i32p + 24U, // FMINPv2i64p + 528464U, // FMINPv4f16 + 200760U, // FMINPv4f32 + 266300U, // FMINPv8f16 + 1580U, // FMINSrr + 0U, // FMINV_VPZ_D + 0U, // FMINV_VPZ_H + 0U, // FMINV_VPZ_S + 28U, // FMINVv4i16v + 32U, // FMINVv4i32v + 36U, // FMINVv8i16v + 75566144U, // FMIN_ZPmI_D + 2037316U, // FMIN_ZPmI_H + 75569216U, // FMIN_ZPmI_S + 8457280U, // FMIN_ZPmZ_D + 12916292U, // FMIN_ZPmZ_H + 16848960U, // FMIN_ZPmZ_S + 462924U, // FMINv2f32 + 135220U, // FMINv2f64 + 528464U, // FMINv4f16 + 200760U, // FMINv4f32 + 266300U, // FMINv8f16 + 23784U, // FMLAL2lanev4f16 + 26219088U, // FMLAL2lanev8f16 + 24296U, // FMLAL2v4f16 + 528976U, // FMLAL2v8f16 + 13569580U, // FMLALB_ZZZI_SHH + 3628U, // FMLALB_ZZZ_SHH + 13569580U, // FMLALT_ZZZI_SHH + 3628U, // FMLALT_ZZZ_SHH + 23784U, // FMLALlanev4f16 + 26219088U, // FMLALlanev8f16 + 24296U, // FMLALv4f16 + 528976U, // FMLALv8f16 + 67174976U, // FMLA_ZPmZZ_D + 14489228U, // FMLA_ZPmZZ_H + 71369792U, // FMLA_ZPmZZ_S + 13566508U, // FMLA_ZZZI_D + 19596U, // FMLA_ZZZI_H + 13567020U, // FMLA_ZZZI_S + 26219052U, // FMLAv1i16_indexed + 27136556U, // FMLAv1i32_indexed + 27267628U, // FMLAv1i64_indexed + 463436U, // FMLAv2f32 + 135732U, // FMLAv2f64 + 27136588U, // FMLAv2i32_indexed + 27267636U, // FMLAv2i64_indexed + 528976U, // FMLAv4f16 + 201272U, // FMLAv4f32 + 26219088U, // FMLAv4i16_indexed + 27136568U, // FMLAv4i32_indexed + 266812U, // FMLAv8f16 + 26219068U, // FMLAv8i16_indexed + 23784U, // FMLSL2lanev4f16 + 26219088U, // FMLSL2lanev8f16 + 24296U, // FMLSL2v4f16 + 528976U, // FMLSL2v8f16 + 13569580U, // FMLSLB_ZZZI_SHH + 3628U, // FMLSLB_ZZZ_SHH + 13569580U, // FMLSLT_ZZZI_SHH + 3628U, // FMLSLT_ZZZ_SHH + 23784U, // FMLSLlanev4f16 + 26219088U, // FMLSLlanev8f16 + 24296U, // FMLSLv4f16 + 528976U, // FMLSLv8f16 + 67174976U, // FMLS_ZPmZZ_D + 14489228U, // FMLS_ZPmZZ_H + 71369792U, // FMLS_ZPmZZ_S + 13566508U, // FMLS_ZZZI_D + 19596U, // FMLS_ZZZI_H + 13567020U, // FMLS_ZZZI_S + 26219052U, // FMLSv1i16_indexed + 27136556U, // FMLSv1i32_indexed + 27267628U, // FMLSv1i64_indexed + 463436U, // FMLSv2f32 + 135732U, // FMLSv2f64 + 27136588U, // FMLSv2i32_indexed + 27267636U, // FMLSv2i64_indexed + 528976U, // FMLSv4f16 + 201272U, // FMLSv4f32 + 26219088U, // FMLSv4i16_indexed + 27136568U, // FMLSv4i32_indexed + 266812U, // FMLSv8f16 + 26219068U, // FMLSv8i16_indexed + 556U, // FMMLA_ZZZ_D + 1068U, // FMMLA_ZZZ_S + 236U, // FMOPA_MPPZZ_D + 240U, // FMOPA_MPPZZ_S + 236U, // FMOPS_MPPZZ_D + 240U, // FMOPS_MPPZZ_S + 21680U, // FMOVDXHighr + 16U, // FMOVDXr + 1U, // FMOVDi + 16U, // FMOVDr + 16U, // FMOVHWr + 16U, // FMOVHXr + 1U, // FMOVHi + 16U, // FMOVHr + 16U, // FMOVSWr + 1U, // FMOVSi + 16U, // FMOVSr + 16U, // FMOVWHr + 16U, // FMOVWSr + 16U, // FMOVXDHighr + 16U, // FMOVXDr + 16U, // FMOVXHr + 1U, // FMOVv2f32_ns + 1U, // FMOVv2f64_ns + 1U, // FMOVv4f16_ns + 1U, // FMOVv4f32_ns + 1U, // FMOVv8f16_ns + 67174976U, // FMSB_ZPmZZ_D + 14489228U, // FMSB_ZPmZZ_H + 71369792U, // FMSB_ZPmZZ_S + 67116U, // FMSUBDrrr + 67116U, // FMSUBHrrr + 67116U, // FMSUBSrrr + 1580U, // FMULDrr + 1580U, // FMULHrr + 1580U, // FMULSrr + 1580U, // FMULX16 + 1580U, // FMULX32 + 1580U, // FMULX64 + 8457280U, // FMULX_ZPmZ_D + 12916292U, // FMULX_ZPmZ_H + 16848960U, // FMULX_ZPmZ_S + 80744492U, // FMULXv1i16_indexed + 81661996U, // FMULXv1i32_indexed + 81793068U, // FMULXv1i64_indexed + 462924U, // FMULXv2f32 + 135220U, // FMULXv2f64 + 81662028U, // FMULXv2i32_indexed + 81793076U, // FMULXv2i64_indexed + 528464U, // FMULXv4f16 + 200760U, // FMULXv4f32 + 80744528U, // FMULXv4i16_indexed + 81662008U, // FMULXv4i32_indexed + 266300U, // FMULXv8f16 + 80744508U, // FMULXv8i16_indexed + 83954752U, // FMUL_ZPmI_D + 2168388U, // FMUL_ZPmI_H + 83957824U, // FMUL_ZPmI_S + 8457280U, // FMUL_ZPmZ_D + 12916292U, // FMUL_ZPmZ_H + 16848960U, // FMUL_ZPmZ_S + 2231340U, // FMUL_ZZZI_D + 24644U, // FMUL_ZZZI_H + 2234412U, // FMUL_ZZZI_S + 3116U, // FMUL_ZZZ_D + 68U, // FMUL_ZZZ_H + 6188U, // FMUL_ZZZ_S + 80744492U, // FMULv1i16_indexed + 81661996U, // FMULv1i32_indexed + 81793068U, // FMULv1i64_indexed + 462924U, // FMULv2f32 + 135220U, // FMULv2f64 + 81662028U, // FMULv2i32_indexed + 81793076U, // FMULv2i64_indexed + 528464U, // FMULv4f16 + 200760U, // FMULv4f32 + 80744528U, // FMULv4i16_indexed + 81662008U, // FMULv4i32_indexed + 266300U, // FMULv8f16 + 80744508U, // FMULv8i16_indexed + 16U, // FNEGDr + 16U, // FNEGHr + 16U, // FNEGSr + 4U, // FNEG_ZPmZ_D + 0U, // FNEG_ZPmZ_H + 8U, // FNEG_ZPmZ_S + 20U, // FNEGv2f32 + 24U, // FNEGv2f64 + 28U, // FNEGv4f16 + 32U, // FNEGv4f32 + 36U, // FNEGv8f16 + 67116U, // FNMADDDrrr + 67116U, // FNMADDHrrr + 67116U, // FNMADDSrrr + 67174976U, // FNMAD_ZPmZZ_D + 14489228U, // FNMAD_ZPmZZ_H + 71369792U, // FNMAD_ZPmZZ_S + 67174976U, // FNMLA_ZPmZZ_D + 14489228U, // FNMLA_ZPmZZ_H + 71369792U, // FNMLA_ZPmZZ_S + 67174976U, // FNMLS_ZPmZZ_D + 14489228U, // FNMLS_ZPmZZ_H + 71369792U, // FNMLS_ZPmZZ_S + 67174976U, // FNMSB_ZPmZZ_D + 14489228U, // FNMSB_ZPmZZ_H + 71369792U, // FNMSB_ZPmZZ_S + 67116U, // FNMSUBDrrr + 67116U, // FNMSUBHrrr + 67116U, // FNMSUBSrrr + 1580U, // FNMULDrr + 1580U, // FNMULHrr + 1580U, // FNMULSrr + 16U, // FRECPE_ZZ_D + 0U, // FRECPE_ZZ_H + 16U, // FRECPE_ZZ_S + 16U, // FRECPEv1f16 + 16U, // FRECPEv1i32 + 16U, // FRECPEv1i64 + 20U, // FRECPEv2f32 + 24U, // FRECPEv2f64 + 28U, // FRECPEv4f16 + 32U, // FRECPEv4f32 + 36U, // FRECPEv8f16 + 1580U, // FRECPS16 + 1580U, // FRECPS32 + 1580U, // FRECPS64 + 3116U, // FRECPS_ZZZ_D + 68U, // FRECPS_ZZZ_H + 6188U, // FRECPS_ZZZ_S + 462924U, // FRECPSv2f32 + 135220U, // FRECPSv2f64 + 528464U, // FRECPSv4f16 + 200760U, // FRECPSv4f32 + 266300U, // FRECPSv8f16 + 4U, // FRECPX_ZPmZ_D + 0U, // FRECPX_ZPmZ_H + 8U, // FRECPX_ZPmZ_S + 16U, // FRECPXv1f16 + 16U, // FRECPXv1i32 + 16U, // FRECPXv1i64 + 16U, // FRINT32XDr + 16U, // FRINT32XSr + 20U, // FRINT32Xv2f32 + 24U, // FRINT32Xv2f64 + 32U, // FRINT32Xv4f32 + 16U, // FRINT32ZDr + 16U, // FRINT32ZSr + 20U, // FRINT32Zv2f32 + 24U, // FRINT32Zv2f64 + 32U, // FRINT32Zv4f32 + 16U, // FRINT64XDr + 16U, // FRINT64XSr + 20U, // FRINT64Xv2f32 + 24U, // FRINT64Xv2f64 + 32U, // FRINT64Xv4f32 + 16U, // FRINT64ZDr + 16U, // FRINT64ZSr + 20U, // FRINT64Zv2f32 + 24U, // FRINT64Zv2f64 + 32U, // FRINT64Zv4f32 + 16U, // FRINTADr + 16U, // FRINTAHr + 16U, // FRINTASr + 4U, // FRINTA_ZPmZ_D + 0U, // FRINTA_ZPmZ_H + 8U, // FRINTA_ZPmZ_S + 20U, // FRINTAv2f32 + 24U, // FRINTAv2f64 + 28U, // FRINTAv4f16 + 32U, // FRINTAv4f32 + 36U, // FRINTAv8f16 + 16U, // FRINTIDr + 16U, // FRINTIHr + 16U, // FRINTISr + 4U, // FRINTI_ZPmZ_D + 0U, // FRINTI_ZPmZ_H + 8U, // FRINTI_ZPmZ_S + 20U, // FRINTIv2f32 + 24U, // FRINTIv2f64 + 28U, // FRINTIv4f16 + 32U, // FRINTIv4f32 + 36U, // FRINTIv8f16 + 16U, // FRINTMDr + 16U, // FRINTMHr + 16U, // FRINTMSr + 4U, // FRINTM_ZPmZ_D + 0U, // FRINTM_ZPmZ_H + 8U, // FRINTM_ZPmZ_S + 20U, // FRINTMv2f32 + 24U, // FRINTMv2f64 + 28U, // FRINTMv4f16 + 32U, // FRINTMv4f32 + 36U, // FRINTMv8f16 + 16U, // FRINTNDr + 16U, // FRINTNHr + 16U, // FRINTNSr + 4U, // FRINTN_ZPmZ_D + 0U, // FRINTN_ZPmZ_H + 8U, // FRINTN_ZPmZ_S + 20U, // FRINTNv2f32 + 24U, // FRINTNv2f64 + 28U, // FRINTNv4f16 + 32U, // FRINTNv4f32 + 36U, // FRINTNv8f16 + 16U, // FRINTPDr + 16U, // FRINTPHr + 16U, // FRINTPSr + 4U, // FRINTP_ZPmZ_D + 0U, // FRINTP_ZPmZ_H + 8U, // FRINTP_ZPmZ_S + 20U, // FRINTPv2f32 + 24U, // FRINTPv2f64 + 28U, // FRINTPv4f16 + 32U, // FRINTPv4f32 + 36U, // FRINTPv8f16 + 16U, // FRINTXDr + 16U, // FRINTXHr + 16U, // FRINTXSr + 4U, // FRINTX_ZPmZ_D + 0U, // FRINTX_ZPmZ_H + 8U, // FRINTX_ZPmZ_S + 20U, // FRINTXv2f32 + 24U, // FRINTXv2f64 + 28U, // FRINTXv4f16 + 32U, // FRINTXv4f32 + 36U, // FRINTXv8f16 + 16U, // FRINTZDr + 16U, // FRINTZHr + 16U, // FRINTZSr + 4U, // FRINTZ_ZPmZ_D + 0U, // FRINTZ_ZPmZ_H + 8U, // FRINTZ_ZPmZ_S + 20U, // FRINTZv2f32 + 24U, // FRINTZv2f64 + 28U, // FRINTZv4f16 + 32U, // FRINTZv4f32 + 36U, // FRINTZv8f16 + 16U, // FRSQRTE_ZZ_D + 0U, // FRSQRTE_ZZ_H + 16U, // FRSQRTE_ZZ_S + 16U, // FRSQRTEv1f16 + 16U, // FRSQRTEv1i32 + 16U, // FRSQRTEv1i64 + 20U, // FRSQRTEv2f32 + 24U, // FRSQRTEv2f64 + 28U, // FRSQRTEv4f16 + 32U, // FRSQRTEv4f32 + 36U, // FRSQRTEv8f16 + 1580U, // FRSQRTS16 + 1580U, // FRSQRTS32 + 1580U, // FRSQRTS64 + 3116U, // FRSQRTS_ZZZ_D + 68U, // FRSQRTS_ZZZ_H + 6188U, // FRSQRTS_ZZZ_S + 462924U, // FRSQRTSv2f32 + 135220U, // FRSQRTSv2f64 + 528464U, // FRSQRTSv4f16 + 200760U, // FRSQRTSv4f32 + 266300U, // FRSQRTSv8f16 + 8457280U, // FSCALE_ZPmZ_D + 12916292U, // FSCALE_ZPmZ_H + 16848960U, // FSCALE_ZPmZ_S + 16U, // FSQRTDr + 16U, // FSQRTHr + 16U, // FSQRTSr + 4U, // FSQRT_ZPmZ_D + 0U, // FSQRT_ZPmZ_H + 8U, // FSQRT_ZPmZ_S + 20U, // FSQRTv2f32 + 24U, // FSQRTv2f64 + 28U, // FSQRTv4f16 + 32U, // FSQRTv4f32 + 36U, // FSQRTv8f16 + 1580U, // FSUBDrr + 1580U, // FSUBHrr + 62983232U, // FSUBR_ZPmI_D + 1447492U, // FSUBR_ZPmI_H + 62986304U, // FSUBR_ZPmI_S + 8457280U, // FSUBR_ZPmZ_D + 12916292U, // FSUBR_ZPmZ_H + 16848960U, // FSUBR_ZPmZ_S + 1580U, // FSUBSrr + 62983232U, // FSUB_ZPmI_D + 1447492U, // FSUB_ZPmI_H + 62986304U, // FSUB_ZPmI_S + 8457280U, // FSUB_ZPmZ_D + 12916292U, // FSUB_ZPmZ_H + 16848960U, // FSUB_ZPmZ_S + 3116U, // FSUB_ZZZ_D + 68U, // FSUB_ZZZ_H + 6188U, // FSUB_ZZZ_S + 462924U, // FSUBv2f32 + 135220U, // FSUBv2f64 + 528464U, // FSUBv4f16 + 200760U, // FSUBv4f32 + 266300U, // FSUBv8f16 + 68652U, // FTMAD_ZZI_D + 726596U, // FTMAD_ZZI_H + 71724U, // FTMAD_ZZI_S + 3116U, // FTSMUL_ZZZ_D + 68U, // FTSMUL_ZZZ_H + 6188U, // FTSMUL_ZZZ_S + 3116U, // FTSSEL_ZZZ_D + 68U, // FTSSEL_ZZZ_H + 6188U, // FTSSEL_ZZZ_S + 1198636U, // GLD1B_D_IMM_REAL + 25132U, // GLD1B_D_REAL + 25644U, // GLD1B_D_SXTW_REAL + 26156U, // GLD1B_D_UXTW_REAL + 1198636U, // GLD1B_S_IMM_REAL + 26668U, // GLD1B_S_SXTW_REAL + 27180U, // GLD1B_S_UXTW_REAL + 1207340U, // GLD1D_IMM_REAL + 25132U, // GLD1D_REAL + 28204U, // GLD1D_SCALED_REAL + 25644U, // GLD1D_SXTW_REAL + 28716U, // GLD1D_SXTW_SCALED_REAL + 26156U, // GLD1D_UXTW_REAL + 29228U, // GLD1D_UXTW_SCALED_REAL + 1209388U, // GLD1H_D_IMM_REAL + 25132U, // GLD1H_D_REAL + 30252U, // GLD1H_D_SCALED_REAL + 25644U, // GLD1H_D_SXTW_REAL + 30764U, // GLD1H_D_SXTW_SCALED_REAL + 26156U, // GLD1H_D_UXTW_REAL + 31276U, // GLD1H_D_UXTW_SCALED_REAL + 1209388U, // GLD1H_S_IMM_REAL + 26668U, // GLD1H_S_SXTW_REAL + 31788U, // GLD1H_S_SXTW_SCALED_REAL + 27180U, // GLD1H_S_UXTW_REAL + 32300U, // GLD1H_S_UXTW_SCALED_REAL + 1198636U, // GLD1SB_D_IMM_REAL + 25132U, // GLD1SB_D_REAL + 25644U, // GLD1SB_D_SXTW_REAL + 26156U, // GLD1SB_D_UXTW_REAL + 1198636U, // GLD1SB_S_IMM_REAL + 26668U, // GLD1SB_S_SXTW_REAL + 27180U, // GLD1SB_S_UXTW_REAL + 1209388U, // GLD1SH_D_IMM_REAL + 25132U, // GLD1SH_D_REAL + 30252U, // GLD1SH_D_SCALED_REAL + 25644U, // GLD1SH_D_SXTW_REAL + 30764U, // GLD1SH_D_SXTW_SCALED_REAL + 26156U, // GLD1SH_D_UXTW_REAL + 31276U, // GLD1SH_D_UXTW_SCALED_REAL + 1209388U, // GLD1SH_S_IMM_REAL + 26668U, // GLD1SH_S_SXTW_REAL + 31788U, // GLD1SH_S_SXTW_SCALED_REAL + 27180U, // GLD1SH_S_UXTW_REAL + 32300U, // GLD1SH_S_UXTW_SCALED_REAL + 1212460U, // GLD1SW_D_IMM_REAL + 25132U, // GLD1SW_D_REAL + 33324U, // GLD1SW_D_SCALED_REAL + 25644U, // GLD1SW_D_SXTW_REAL + 33836U, // GLD1SW_D_SXTW_SCALED_REAL + 26156U, // GLD1SW_D_UXTW_REAL + 34348U, // GLD1SW_D_UXTW_SCALED_REAL + 1212460U, // GLD1W_D_IMM_REAL + 25132U, // GLD1W_D_REAL + 33324U, // GLD1W_D_SCALED_REAL + 25644U, // GLD1W_D_SXTW_REAL + 33836U, // GLD1W_D_SXTW_SCALED_REAL + 26156U, // GLD1W_D_UXTW_REAL + 34348U, // GLD1W_D_UXTW_SCALED_REAL + 1212460U, // GLD1W_IMM_REAL + 26668U, // GLD1W_SXTW_REAL + 34860U, // GLD1W_SXTW_SCALED_REAL + 27180U, // GLD1W_UXTW_REAL + 35372U, // GLD1W_UXTW_SCALED_REAL + 1198636U, // GLDFF1B_D_IMM_REAL + 25132U, // GLDFF1B_D_REAL + 25644U, // GLDFF1B_D_SXTW_REAL + 26156U, // GLDFF1B_D_UXTW_REAL + 1198636U, // GLDFF1B_S_IMM_REAL + 26668U, // GLDFF1B_S_SXTW_REAL + 27180U, // GLDFF1B_S_UXTW_REAL + 1207340U, // GLDFF1D_IMM_REAL + 25132U, // GLDFF1D_REAL + 28204U, // GLDFF1D_SCALED_REAL + 25644U, // GLDFF1D_SXTW_REAL + 28716U, // GLDFF1D_SXTW_SCALED_REAL + 26156U, // GLDFF1D_UXTW_REAL + 29228U, // GLDFF1D_UXTW_SCALED_REAL + 1209388U, // GLDFF1H_D_IMM_REAL + 25132U, // GLDFF1H_D_REAL + 30252U, // GLDFF1H_D_SCALED_REAL + 25644U, // GLDFF1H_D_SXTW_REAL + 30764U, // GLDFF1H_D_SXTW_SCALED_REAL + 26156U, // GLDFF1H_D_UXTW_REAL + 31276U, // GLDFF1H_D_UXTW_SCALED_REAL + 1209388U, // GLDFF1H_S_IMM_REAL + 26668U, // GLDFF1H_S_SXTW_REAL + 31788U, // GLDFF1H_S_SXTW_SCALED_REAL + 27180U, // GLDFF1H_S_UXTW_REAL + 32300U, // GLDFF1H_S_UXTW_SCALED_REAL + 1198636U, // GLDFF1SB_D_IMM_REAL + 25132U, // GLDFF1SB_D_REAL + 25644U, // GLDFF1SB_D_SXTW_REAL + 26156U, // GLDFF1SB_D_UXTW_REAL + 1198636U, // GLDFF1SB_S_IMM_REAL + 26668U, // GLDFF1SB_S_SXTW_REAL + 27180U, // GLDFF1SB_S_UXTW_REAL + 1209388U, // GLDFF1SH_D_IMM_REAL + 25132U, // GLDFF1SH_D_REAL + 30252U, // GLDFF1SH_D_SCALED_REAL + 25644U, // GLDFF1SH_D_SXTW_REAL + 30764U, // GLDFF1SH_D_SXTW_SCALED_REAL + 26156U, // GLDFF1SH_D_UXTW_REAL + 31276U, // GLDFF1SH_D_UXTW_SCALED_REAL + 1209388U, // GLDFF1SH_S_IMM_REAL + 26668U, // GLDFF1SH_S_SXTW_REAL + 31788U, // GLDFF1SH_S_SXTW_SCALED_REAL + 27180U, // GLDFF1SH_S_UXTW_REAL + 32300U, // GLDFF1SH_S_UXTW_SCALED_REAL + 1212460U, // GLDFF1SW_D_IMM_REAL + 25132U, // GLDFF1SW_D_REAL + 33324U, // GLDFF1SW_D_SCALED_REAL + 25644U, // GLDFF1SW_D_SXTW_REAL + 33836U, // GLDFF1SW_D_SXTW_SCALED_REAL + 26156U, // GLDFF1SW_D_UXTW_REAL + 34348U, // GLDFF1SW_D_UXTW_SCALED_REAL + 1212460U, // GLDFF1W_D_IMM_REAL + 25132U, // GLDFF1W_D_REAL + 33324U, // GLDFF1W_D_SCALED_REAL + 25644U, // GLDFF1W_D_SXTW_REAL + 33836U, // GLDFF1W_D_SXTW_SCALED_REAL + 26156U, // GLDFF1W_D_UXTW_REAL + 34348U, // GLDFF1W_D_UXTW_SCALED_REAL + 1212460U, // GLDFF1W_IMM_REAL + 26668U, // GLDFF1W_SXTW_REAL + 34860U, // GLDFF1W_SXTW_SCALED_REAL + 27180U, // GLDFF1W_UXTW_REAL + 35372U, // GLDFF1W_UXTW_SCALED_REAL + 1580U, // GMI + 0U, // HINT + 8457308U, // HISTCNT_ZPzZZ_D + 16848988U, // HISTCNT_ZPzZZ_S + 5164U, // HISTSEG_ZZZ + 0U, // HLT + 0U, // HVC + 0U, // INCB_XPiI + 0U, // INCD_XPiI + 0U, // INCD_ZPiI + 0U, // INCH_XPiI + 0U, // INCH_ZPiI + 16U, // INCP_XP_B + 16U, // INCP_XP_D + 16U, // INCP_XP_H + 16U, // INCP_XP_S + 16U, // INCP_ZP_D + 0U, // INCP_ZP_H + 16U, // INCP_ZP_S + 0U, // INCW_XPiI + 0U, // INCW_ZPiI + 245U, // INDEX_II_B + 1580U, // INDEX_II_D + 1U, // INDEX_II_H + 1580U, // INDEX_II_S + 101U, // INDEX_IR_B + 1580U, // INDEX_IR_D + 16U, // INDEX_IR_H + 1580U, // INDEX_IR_S + 35884U, // INDEX_RI_B + 1580U, // INDEX_RI_D + 248U, // INDEX_RI_H + 1580U, // INDEX_RI_S + 1580U, // INDEX_RR_B + 1580U, // INDEX_RR_D + 100U, // INDEX_RR_H + 1580U, // INDEX_RR_S + 253U, // INSERT_MXIPZ_H_B + 237U, // INSERT_MXIPZ_H_D + 257U, // INSERT_MXIPZ_H_H + 261U, // INSERT_MXIPZ_H_Q + 241U, // INSERT_MXIPZ_H_S + 253U, // INSERT_MXIPZ_V_B + 237U, // INSERT_MXIPZ_V_D + 257U, // INSERT_MXIPZ_V_H + 261U, // INSERT_MXIPZ_V_Q + 241U, // INSERT_MXIPZ_V_S + 16U, // INSR_ZR_B + 16U, // INSR_ZR_D + 0U, // INSR_ZR_H + 16U, // INSR_ZR_S + 1U, // INSR_ZV_B + 1U, // INSR_ZV_D + 0U, // INSR_ZV_H + 1U, // INSR_ZV_S + 0U, // INSvi16gpr + 19625U, // INSvi16lane + 0U, // INSvi32gpr + 19629U, // INSvi32lane + 0U, // INSvi64gpr + 19633U, // INSvi64lane + 0U, // INSvi8gpr + 19637U, // INSvi8lane + 1580U, // IRG + 0U, // ISB + 5164U, // LASTA_RPZ_B + 3116U, // LASTA_RPZ_D + 2604U, // LASTA_RPZ_H + 6188U, // LASTA_RPZ_S + 5164U, // LASTA_VPZ_B + 3116U, // LASTA_VPZ_D + 2604U, // LASTA_VPZ_H + 6188U, // LASTA_VPZ_S + 5164U, // LASTB_RPZ_B + 3116U, // LASTB_RPZ_D + 2604U, // LASTB_RPZ_H + 6188U, // LASTB_RPZ_S + 5164U, // LASTB_VPZ_B + 3116U, // LASTB_VPZ_D + 2604U, // LASTB_VPZ_H + 6188U, // LASTB_VPZ_S + 36396U, // LD1B + 36396U, // LD1B_D + 2312748U, // LD1B_D_IMM_REAL + 36396U, // LD1B_H + 2312748U, // LD1B_H_IMM_REAL + 2312748U, // LD1B_IMM_REAL + 36396U, // LD1B_S + 2312748U, // LD1B_S_IMM_REAL + 36908U, // LD1D + 2312748U, // LD1D_IMM_REAL + 0U, // LD1Fourv16b + 0U, // LD1Fourv16b_POST + 0U, // LD1Fourv1d + 0U, // LD1Fourv1d_POST + 0U, // LD1Fourv2d + 0U, // LD1Fourv2d_POST + 0U, // LD1Fourv2s + 0U, // LD1Fourv2s_POST + 0U, // LD1Fourv4h + 0U, // LD1Fourv4h_POST + 0U, // LD1Fourv4s + 0U, // LD1Fourv4s_POST + 0U, // LD1Fourv8b + 0U, // LD1Fourv8b_POST + 0U, // LD1Fourv8h + 0U, // LD1Fourv8h_POST + 37420U, // LD1H + 37420U, // LD1H_D + 2312748U, // LD1H_D_IMM_REAL + 2312748U, // LD1H_IMM_REAL + 37420U, // LD1H_S + 2312748U, // LD1H_S_IMM_REAL + 0U, // LD1Onev16b + 0U, // LD1Onev16b_POST + 0U, // LD1Onev1d + 0U, // LD1Onev1d_POST + 0U, // LD1Onev2d + 0U, // LD1Onev2d_POST + 0U, // LD1Onev2s + 0U, // LD1Onev2s_POST + 0U, // LD1Onev4h + 0U, // LD1Onev4h_POST + 0U, // LD1Onev4s + 0U, // LD1Onev4s_POST + 0U, // LD1Onev8b + 0U, // LD1Onev8b_POST + 0U, // LD1Onev8h + 0U, // LD1Onev8h_POST + 1198636U, // LD1RB_D_IMM + 1198636U, // LD1RB_H_IMM + 1198636U, // LD1RB_IMM + 1198636U, // LD1RB_S_IMM + 1207340U, // LD1RD_IMM + 1209388U, // LD1RH_D_IMM + 1209388U, // LD1RH_IMM + 1209388U, // LD1RH_S_IMM + 36396U, // LD1RO_B + 37932U, // LD1RO_B_IMM + 36908U, // LD1RO_D + 37932U, // LD1RO_D_IMM + 37420U, // LD1RO_H + 37932U, // LD1RO_H_IMM + 38444U, // LD1RO_W + 37932U, // LD1RO_W_IMM + 36396U, // LD1RQ_B + 1218604U, // LD1RQ_B_IMM + 36908U, // LD1RQ_D + 1218604U, // LD1RQ_D_IMM + 37420U, // LD1RQ_H + 1218604U, // LD1RQ_H_IMM + 38444U, // LD1RQ_W + 1218604U, // LD1RQ_W_IMM + 1198636U, // LD1RSB_D_IMM + 1198636U, // LD1RSB_H_IMM + 1198636U, // LD1RSB_S_IMM + 1209388U, // LD1RSH_D_IMM + 1209388U, // LD1RSH_S_IMM + 1212460U, // LD1RSW_IMM + 1212460U, // LD1RW_D_IMM + 1212460U, // LD1RW_IMM + 0U, // LD1Rv16b + 0U, // LD1Rv16b_POST + 0U, // LD1Rv1d + 0U, // LD1Rv1d_POST + 0U, // LD1Rv2d + 0U, // LD1Rv2d_POST + 0U, // LD1Rv2s + 0U, // LD1Rv2s_POST + 0U, // LD1Rv4h + 0U, // LD1Rv4h_POST + 0U, // LD1Rv4s + 0U, // LD1Rv4s_POST + 0U, // LD1Rv8b + 0U, // LD1Rv8b_POST + 0U, // LD1Rv8h + 0U, // LD1Rv8h_POST + 36396U, // LD1SB_D + 2312748U, // LD1SB_D_IMM_REAL + 36396U, // LD1SB_H + 2312748U, // LD1SB_H_IMM_REAL + 36396U, // LD1SB_S + 2312748U, // LD1SB_S_IMM_REAL + 37420U, // LD1SH_D + 2312748U, // LD1SH_D_IMM_REAL + 37420U, // LD1SH_S + 2312748U, // LD1SH_S_IMM_REAL + 38444U, // LD1SW_D + 2312748U, // LD1SW_D_IMM_REAL + 0U, // LD1Threev16b + 0U, // LD1Threev16b_POST + 0U, // LD1Threev1d + 0U, // LD1Threev1d_POST + 0U, // LD1Threev2d + 0U, // LD1Threev2d_POST + 0U, // LD1Threev2s + 0U, // LD1Threev2s_POST + 0U, // LD1Threev4h + 0U, // LD1Threev4h_POST + 0U, // LD1Threev4s + 0U, // LD1Threev4s_POST + 0U, // LD1Threev8b + 0U, // LD1Threev8b_POST + 0U, // LD1Threev8h + 0U, // LD1Threev8h_POST + 0U, // LD1Twov16b + 0U, // LD1Twov16b_POST + 0U, // LD1Twov1d + 0U, // LD1Twov1d_POST + 0U, // LD1Twov2d + 0U, // LD1Twov2d_POST + 0U, // LD1Twov2s + 0U, // LD1Twov2s_POST + 0U, // LD1Twov4h + 0U, // LD1Twov4h_POST + 0U, // LD1Twov4s + 0U, // LD1Twov4s_POST + 0U, // LD1Twov8b + 0U, // LD1Twov8b_POST + 0U, // LD1Twov8h + 0U, // LD1Twov8h_POST + 38444U, // LD1W + 38444U, // LD1W_D + 2312748U, // LD1W_D_IMM_REAL + 2312748U, // LD1W_IMM_REAL + 265U, // LD1_MXIPXX_H_B + 269U, // LD1_MXIPXX_H_D + 273U, // LD1_MXIPXX_H_H + 277U, // LD1_MXIPXX_H_Q + 281U, // LD1_MXIPXX_H_S + 265U, // LD1_MXIPXX_V_B + 269U, // LD1_MXIPXX_V_D + 273U, // LD1_MXIPXX_V_H + 277U, // LD1_MXIPXX_V_Q + 281U, // LD1_MXIPXX_V_S + 0U, // LD1i16 + 0U, // LD1i16_POST + 0U, // LD1i32 + 0U, // LD1i32_POST + 0U, // LD1i64 + 0U, // LD1i64_POST + 0U, // LD1i8 + 0U, // LD1i8_POST + 36396U, // LD2B + 2323500U, // LD2B_IMM + 36908U, // LD2D + 2323500U, // LD2D_IMM + 37420U, // LD2H + 2323500U, // LD2H_IMM + 0U, // LD2Rv16b + 0U, // LD2Rv16b_POST + 0U, // LD2Rv1d + 0U, // LD2Rv1d_POST + 0U, // LD2Rv2d + 0U, // LD2Rv2d_POST + 0U, // LD2Rv2s + 0U, // LD2Rv2s_POST + 0U, // LD2Rv4h + 0U, // LD2Rv4h_POST + 0U, // LD2Rv4s + 0U, // LD2Rv4s_POST + 0U, // LD2Rv8b + 0U, // LD2Rv8b_POST + 0U, // LD2Rv8h + 0U, // LD2Rv8h_POST + 0U, // LD2Twov16b + 0U, // LD2Twov16b_POST + 0U, // LD2Twov2d + 0U, // LD2Twov2d_POST + 0U, // LD2Twov2s + 0U, // LD2Twov2s_POST + 0U, // LD2Twov4h + 0U, // LD2Twov4h_POST + 0U, // LD2Twov4s + 0U, // LD2Twov4s_POST + 0U, // LD2Twov8b + 0U, // LD2Twov8b_POST + 0U, // LD2Twov8h + 0U, // LD2Twov8h_POST + 38444U, // LD2W + 2323500U, // LD2W_IMM + 0U, // LD2i16 + 0U, // LD2i16_POST + 0U, // LD2i32 + 0U, // LD2i32_POST + 0U, // LD2i64 + 0U, // LD2i64_POST + 0U, // LD2i8 + 0U, // LD2i8_POST + 36396U, // LD3B + 39468U, // LD3B_IMM + 36908U, // LD3D + 39468U, // LD3D_IMM + 37420U, // LD3H + 39468U, // LD3H_IMM + 0U, // LD3Rv16b + 0U, // LD3Rv16b_POST + 0U, // LD3Rv1d + 0U, // LD3Rv1d_POST + 0U, // LD3Rv2d + 0U, // LD3Rv2d_POST + 0U, // LD3Rv2s + 0U, // LD3Rv2s_POST + 0U, // LD3Rv4h + 0U, // LD3Rv4h_POST + 0U, // LD3Rv4s + 0U, // LD3Rv4s_POST + 0U, // LD3Rv8b + 0U, // LD3Rv8b_POST + 0U, // LD3Rv8h + 0U, // LD3Rv8h_POST + 0U, // LD3Threev16b + 0U, // LD3Threev16b_POST + 0U, // LD3Threev2d + 0U, // LD3Threev2d_POST + 0U, // LD3Threev2s + 0U, // LD3Threev2s_POST + 0U, // LD3Threev4h + 0U, // LD3Threev4h_POST + 0U, // LD3Threev4s + 0U, // LD3Threev4s_POST + 0U, // LD3Threev8b + 0U, // LD3Threev8b_POST + 0U, // LD3Threev8h + 0U, // LD3Threev8h_POST + 38444U, // LD3W + 39468U, // LD3W_IMM + 0U, // LD3i16 + 0U, // LD3i16_POST + 0U, // LD3i32 + 0U, // LD3i32_POST + 0U, // LD3i64 + 0U, // LD3i64_POST + 0U, // LD3i8 + 0U, // LD3i8_POST + 36396U, // LD4B + 2326572U, // LD4B_IMM + 36908U, // LD4D + 2326572U, // LD4D_IMM + 0U, // LD4Fourv16b + 0U, // LD4Fourv16b_POST + 0U, // LD4Fourv2d + 0U, // LD4Fourv2d_POST + 0U, // LD4Fourv2s + 0U, // LD4Fourv2s_POST + 0U, // LD4Fourv4h + 0U, // LD4Fourv4h_POST + 0U, // LD4Fourv4s + 0U, // LD4Fourv4s_POST + 0U, // LD4Fourv8b + 0U, // LD4Fourv8b_POST + 0U, // LD4Fourv8h + 0U, // LD4Fourv8h_POST + 37420U, // LD4H + 2326572U, // LD4H_IMM + 0U, // LD4Rv16b + 0U, // LD4Rv16b_POST + 0U, // LD4Rv1d + 0U, // LD4Rv1d_POST + 0U, // LD4Rv2d + 0U, // LD4Rv2d_POST + 0U, // LD4Rv2s + 0U, // LD4Rv2s_POST + 0U, // LD4Rv4h + 0U, // LD4Rv4h_POST + 0U, // LD4Rv4s + 0U, // LD4Rv4s_POST + 0U, // LD4Rv8b + 0U, // LD4Rv8b_POST + 0U, // LD4Rv8h + 0U, // LD4Rv8h_POST + 38444U, // LD4W + 2326572U, // LD4W_IMM + 0U, // LD4i16 + 0U, // LD4i16_POST + 0U, // LD4i32 + 0U, // LD4i32_POST + 0U, // LD4i64 + 0U, // LD4i64_POST + 0U, // LD4i8 + 0U, // LD4i8_POST + 0U, // LD64B + 1U, // LDADDAB + 1U, // LDADDAH + 1U, // LDADDALB + 1U, // LDADDALH + 1U, // LDADDALW + 1U, // LDADDALX + 1U, // LDADDAW + 1U, // LDADDAX + 1U, // LDADDB + 1U, // LDADDH + 1U, // LDADDLB + 1U, // LDADDLH + 1U, // LDADDLW + 1U, // LDADDLX + 1U, // LDADDW + 1U, // LDADDX + 284U, // LDAPRB + 284U, // LDAPRH + 284U, // LDAPRW + 284U, // LDAPRX + 1181228U, // LDAPURBi + 1181228U, // LDAPURHi + 1181228U, // LDAPURSBWi + 1181228U, // LDAPURSBXi + 1181228U, // LDAPURSHWi + 1181228U, // LDAPURSHXi + 1181228U, // LDAPURSWi + 1181228U, // LDAPURXi + 1181228U, // LDAPURi + 284U, // LDARB + 284U, // LDARH + 284U, // LDARW + 284U, // LDARX + 1181288U, // LDAXPW + 1181288U, // LDAXPX + 284U, // LDAXRB + 284U, // LDAXRH + 284U, // LDAXRW + 284U, // LDAXRX + 1U, // LDCLRAB + 1U, // LDCLRAH + 1U, // LDCLRALB + 1U, // LDCLRALH + 1U, // LDCLRALW + 1U, // LDCLRALX + 1U, // LDCLRAW + 1U, // LDCLRAX + 1U, // LDCLRB + 1U, // LDCLRH + 1U, // LDCLRLB + 1U, // LDCLRLH + 1U, // LDCLRLW + 1U, // LDCLRLX + 1U, // LDCLRW + 1U, // LDCLRX + 1U, // LDEORAB + 1U, // LDEORAH + 1U, // LDEORALB + 1U, // LDEORALH + 1U, // LDEORALW + 1U, // LDEORALX + 1U, // LDEORAW + 1U, // LDEORAX + 1U, // LDEORB + 1U, // LDEORH + 1U, // LDEORLB + 1U, // LDEORLH + 1U, // LDEORLW + 1U, // LDEORLX + 1U, // LDEORW + 1U, // LDEORX + 36396U, // LDFF1B_D_REAL + 36396U, // LDFF1B_H_REAL + 36396U, // LDFF1B_REAL + 36396U, // LDFF1B_S_REAL + 36908U, // LDFF1D_REAL + 37420U, // LDFF1H_D_REAL + 37420U, // LDFF1H_REAL + 37420U, // LDFF1H_S_REAL + 36396U, // LDFF1SB_D_REAL + 36396U, // LDFF1SB_H_REAL + 36396U, // LDFF1SB_S_REAL + 37420U, // LDFF1SH_D_REAL + 37420U, // LDFF1SH_S_REAL + 38444U, // LDFF1SW_D_REAL + 38444U, // LDFF1W_D_REAL + 38444U, // LDFF1W_REAL + 1218604U, // LDG + 284U, // LDGM + 284U, // LDLARB + 284U, // LDLARH + 284U, // LDLARW + 284U, // LDLARX + 2312748U, // LDNF1B_D_IMM_REAL + 2312748U, // LDNF1B_H_IMM_REAL + 2312748U, // LDNF1B_IMM_REAL + 2312748U, // LDNF1B_S_IMM_REAL + 2312748U, // LDNF1D_IMM_REAL + 2312748U, // LDNF1H_D_IMM_REAL + 2312748U, // LDNF1H_IMM_REAL + 2312748U, // LDNF1H_S_IMM_REAL + 2312748U, // LDNF1SB_D_IMM_REAL + 2312748U, // LDNF1SB_H_IMM_REAL + 2312748U, // LDNF1SB_S_IMM_REAL + 2312748U, // LDNF1SH_D_IMM_REAL + 2312748U, // LDNF1SH_S_IMM_REAL + 2312748U, // LDNF1SW_D_IMM_REAL + 2312748U, // LDNF1W_D_IMM_REAL + 2312748U, // LDNF1W_IMM_REAL + 88147560U, // LDNPDi + 92341864U, // LDNPQi + 96536168U, // LDNPSi + 96536168U, // LDNPWi + 88147560U, // LDNPXi + 2312748U, // LDNT1B_ZRI + 36396U, // LDNT1B_ZRR + 1198636U, // LDNT1B_ZZR_D_REAL + 1198636U, // LDNT1B_ZZR_S_REAL + 2312748U, // LDNT1D_ZRI + 36908U, // LDNT1D_ZRR + 1198636U, // LDNT1D_ZZR_D_REAL + 2312748U, // LDNT1H_ZRI + 37420U, // LDNT1H_ZRR + 1198636U, // LDNT1H_ZZR_D_REAL + 1198636U, // LDNT1H_ZZR_S_REAL + 1198636U, // LDNT1SB_ZZR_D_REAL + 1198636U, // LDNT1SB_ZZR_S_REAL + 1198636U, // LDNT1SH_ZZR_D_REAL + 1198636U, // LDNT1SH_ZZR_S_REAL + 1198636U, // LDNT1SW_ZZR_D_REAL + 2312748U, // LDNT1W_ZRI + 38444U, // LDNT1W_ZRR + 1198636U, // LDNT1W_ZZR_D_REAL + 1198636U, // LDNT1W_ZZR_S_REAL + 88147560U, // LDPDi + 103041640U, // LDPDpost + 1442925160U, // LDPDpre + 92341864U, // LDPQi + 107235944U, // LDPQpost + 1447119464U, // LDPQpre + 96536168U, // LDPSWi + 111430248U, // LDPSWpost + 1451313768U, // LDPSWpre + 96536168U, // LDPSi + 111430248U, // LDPSpost + 1451313768U, // LDPSpre + 96536168U, // LDPWi + 111430248U, // LDPWpost + 1451313768U, // LDPWpre + 88147560U, // LDPXi + 103041640U, // LDPXpost + 1442925160U, // LDPXpre + 39980U, // LDRAAindexed + 2452524U, // LDRAAwriteback + 39980U, // LDRABindexed + 2452524U, // LDRABwriteback + 19232U, // LDRBBpost + 2443820U, // LDRBBpre + 113313324U, // LDRBBroW + 117507628U, // LDRBBroX + 40492U, // LDRBBui + 19232U, // LDRBpost + 2443820U, // LDRBpre + 113313324U, // LDRBroW + 117507628U, // LDRBroX + 40492U, // LDRBui + 0U, // LDRDl + 19232U, // LDRDpost + 2443820U, // LDRDpre + 121701932U, // LDRDroW + 125896236U, // LDRDroX + 41004U, // LDRDui + 19232U, // LDRHHpost + 2443820U, // LDRHHpre + 130090540U, // LDRHHroW + 134284844U, // LDRHHroX + 41516U, // LDRHHui + 19232U, // LDRHpost + 2443820U, // LDRHpre + 130090540U, // LDRHroW + 134284844U, // LDRHroX + 41516U, // LDRHui + 0U, // LDRQl + 19232U, // LDRQpost + 2443820U, // LDRQpre + 138479148U, // LDRQroW + 142673452U, // LDRQroX + 42028U, // LDRQui + 19232U, // LDRSBWpost + 2443820U, // LDRSBWpre + 113313324U, // LDRSBWroW + 117507628U, // LDRSBWroX + 40492U, // LDRSBWui + 19232U, // LDRSBXpost + 2443820U, // LDRSBXpre + 113313324U, // LDRSBXroW + 117507628U, // LDRSBXroX + 40492U, // LDRSBXui + 19232U, // LDRSHWpost + 2443820U, // LDRSHWpre + 130090540U, // LDRSHWroW + 134284844U, // LDRSHWroX + 41516U, // LDRSHWui + 19232U, // LDRSHXpost + 2443820U, // LDRSHXpre + 130090540U, // LDRSHXroW + 134284844U, // LDRSHXroX + 41516U, // LDRSHXui + 0U, // LDRSWl + 19232U, // LDRSWpost + 2443820U, // LDRSWpre + 146867756U, // LDRSWroW + 151062060U, // LDRSWroX + 42540U, // LDRSWui + 0U, // LDRSl + 19232U, // LDRSpost + 2443820U, // LDRSpre + 146867756U, // LDRSroW + 151062060U, // LDRSroX + 42540U, // LDRSui + 0U, // LDRWl + 19232U, // LDRWpost + 2443820U, // LDRWpre + 146867756U, // LDRWroW + 151062060U, // LDRWroX + 42540U, // LDRWui + 0U, // LDRXl + 19232U, // LDRXpost + 2443820U, // LDRXpre + 121701932U, // LDRXroW + 125896236U, // LDRXroX + 41004U, // LDRXui + 2295340U, // LDR_PXI + 0U, // LDR_ZA + 2295340U, // LDR_ZXI + 1U, // LDSETAB + 1U, // LDSETAH + 1U, // LDSETALB + 1U, // LDSETALH + 1U, // LDSETALW + 1U, // LDSETALX + 1U, // LDSETAW + 1U, // LDSETAX + 1U, // LDSETB + 1U, // LDSETH + 1U, // LDSETLB + 1U, // LDSETLH + 1U, // LDSETLW + 1U, // LDSETLX + 1U, // LDSETW + 1U, // LDSETX + 1U, // LDSMAXAB + 1U, // LDSMAXAH + 1U, // LDSMAXALB + 1U, // LDSMAXALH + 1U, // LDSMAXALW + 1U, // LDSMAXALX + 1U, // LDSMAXAW + 1U, // LDSMAXAX + 1U, // LDSMAXB + 1U, // LDSMAXH + 1U, // LDSMAXLB + 1U, // LDSMAXLH + 1U, // LDSMAXLW + 1U, // LDSMAXLX + 1U, // LDSMAXW + 1U, // LDSMAXX + 1U, // LDSMINAB + 1U, // LDSMINAH + 1U, // LDSMINALB + 1U, // LDSMINALH + 1U, // LDSMINALW + 1U, // LDSMINALX + 1U, // LDSMINAW + 1U, // LDSMINAX + 1U, // LDSMINB + 1U, // LDSMINH + 1U, // LDSMINLB + 1U, // LDSMINLH + 1U, // LDSMINLW + 1U, // LDSMINLX + 1U, // LDSMINW + 1U, // LDSMINX + 1181228U, // LDTRBi + 1181228U, // LDTRHi + 1181228U, // LDTRSBWi + 1181228U, // LDTRSBXi + 1181228U, // LDTRSHWi + 1181228U, // LDTRSHXi + 1181228U, // LDTRSWi + 1181228U, // LDTRWi + 1181228U, // LDTRXi + 1U, // LDUMAXAB + 1U, // LDUMAXAH + 1U, // LDUMAXALB + 1U, // LDUMAXALH + 1U, // LDUMAXALW + 1U, // LDUMAXALX + 1U, // LDUMAXAW + 1U, // LDUMAXAX + 1U, // LDUMAXB + 1U, // LDUMAXH + 1U, // LDUMAXLB + 1U, // LDUMAXLH + 1U, // LDUMAXLW + 1U, // LDUMAXLX + 1U, // LDUMAXW + 1U, // LDUMAXX + 1U, // LDUMINAB + 1U, // LDUMINAH + 1U, // LDUMINALB + 1U, // LDUMINALH + 1U, // LDUMINALW + 1U, // LDUMINALX + 1U, // LDUMINAW + 1U, // LDUMINAX + 1U, // LDUMINB + 1U, // LDUMINH + 1U, // LDUMINLB + 1U, // LDUMINLH + 1U, // LDUMINLW + 1U, // LDUMINLX + 1U, // LDUMINW + 1U, // LDUMINX + 1181228U, // LDURBBi + 1181228U, // LDURBi + 1181228U, // LDURDi + 1181228U, // LDURHHi + 1181228U, // LDURHi + 1181228U, // LDURQi + 1181228U, // LDURSBWi + 1181228U, // LDURSBXi + 1181228U, // LDURSHWi + 1181228U, // LDURSHXi + 1181228U, // LDURSWi + 1181228U, // LDURSi + 1181228U, // LDURWi + 1181228U, // LDURXi + 1181288U, // LDXPW + 1181288U, // LDXPX + 284U, // LDXRB + 284U, // LDXRH + 284U, // LDXRW + 284U, // LDXRX + 4265024U, // LSLR_ZPmZ_B + 8457280U, // LSLR_ZPmZ_D + 12916292U, // LSLR_ZPmZ_H + 16848960U, // LSLR_ZPmZ_S + 1580U, // LSLVWr + 1580U, // LSLVXr + 8459328U, // LSL_WIDE_ZPmZ_B + 792132U, // LSL_WIDE_ZPmZ_H + 8460352U, // LSL_WIDE_ZPmZ_S + 3116U, // LSL_WIDE_ZZZ_B + 96U, // LSL_WIDE_ZZZ_H + 3116U, // LSL_WIDE_ZZZ_S + 70720U, // LSL_ZPmI_B + 68672U, // LSL_ZPmI_D + 726596U, // LSL_ZPmI_H + 71744U, // LSL_ZPmI_S + 4265024U, // LSL_ZPmZ_B + 8457280U, // LSL_ZPmZ_D + 12916292U, // LSL_ZPmZ_H + 16848960U, // LSL_ZPmZ_S + 1580U, // LSL_ZZI_B + 1580U, // LSL_ZZI_D + 100U, // LSL_ZZI_H + 1580U, // LSL_ZZI_S + 4265024U, // LSRR_ZPmZ_B + 8457280U, // LSRR_ZPmZ_D + 12916292U, // LSRR_ZPmZ_H + 16848960U, // LSRR_ZPmZ_S + 1580U, // LSRVWr + 1580U, // LSRVXr + 8459328U, // LSR_WIDE_ZPmZ_B + 792132U, // LSR_WIDE_ZPmZ_H + 8460352U, // LSR_WIDE_ZPmZ_S + 3116U, // LSR_WIDE_ZZZ_B + 96U, // LSR_WIDE_ZZZ_H + 3116U, // LSR_WIDE_ZZZ_S + 70720U, // LSR_ZPmI_B + 68672U, // LSR_ZPmI_D + 726596U, // LSR_ZPmI_H + 71744U, // LSR_ZPmI_S + 4265024U, // LSR_ZPmZ_B + 8457280U, // LSR_ZPmZ_D + 12916292U, // LSR_ZPmZ_H + 16848960U, // LSR_ZPmZ_S + 1580U, // LSR_ZZI_B + 1580U, // LSR_ZZI_D + 100U, // LSR_ZZI_H + 1580U, // LSR_ZZI_S + 67116U, // MADDWrrr + 67116U, // MADDXrrr + 43072U, // MAD_ZPmZZ_B + 67174976U, // MAD_ZPmZZ_D + 14489228U, // MAD_ZPmZZ_H + 71369792U, // MAD_ZPmZZ_S + 4265052U, // MATCH_PPzZZ_B + 12916292U, // MATCH_PPzZZ_H + 43072U, // MLA_ZPmZZ_B + 67174976U, // MLA_ZPmZZ_D + 14489228U, // MLA_ZPmZZ_H + 71369792U, // MLA_ZPmZZ_S + 13566508U, // MLA_ZZZI_D + 19596U, // MLA_ZZZI_H + 13567020U, // MLA_ZZZI_S + 397896U, // MLAv16i8 + 463436U, // MLAv2i32 + 27136588U, // MLAv2i32_indexed + 528976U, // MLAv4i16 + 26219088U, // MLAv4i16_indexed + 201272U, // MLAv4i32 + 27136568U, // MLAv4i32_indexed + 266812U, // MLAv8i16 + 26219068U, // MLAv8i16_indexed + 594516U, // MLAv8i8 + 43072U, // MLS_ZPmZZ_B + 67174976U, // MLS_ZPmZZ_D + 14489228U, // MLS_ZPmZZ_H + 71369792U, // MLS_ZPmZZ_S + 13566508U, // MLS_ZZZI_D + 19596U, // MLS_ZZZI_H + 13567020U, // MLS_ZZZI_S + 397896U, // MLSv16i8 + 463436U, // MLSv2i32 + 27136588U, // MLSv2i32_indexed + 528976U, // MLSv4i16 + 26219088U, // MLSv4i16_indexed + 201272U, // MLSv4i32 + 27136568U, // MLSv4i32_indexed + 266812U, // MLSv8i16 + 26219068U, // MLSv8i16_indexed + 594516U, // MLSv8i8 + 1U, // MOVID + 17U, // MOVIv16b_ns + 1U, // MOVIv2d_ns + 293U, // MOVIv2i32 + 293U, // MOVIv2s_msl + 293U, // MOVIv4i16 + 293U, // MOVIv4i32 + 293U, // MOVIv4s_msl + 17U, // MOVIv8b_ns + 293U, // MOVIv8i16 + 0U, // MOVKWi + 0U, // MOVKXi + 293U, // MOVNWi + 293U, // MOVNXi + 0U, // MOVPRFX_ZPmZ_B + 4U, // MOVPRFX_ZPmZ_D + 0U, // MOVPRFX_ZPmZ_H + 8U, // MOVPRFX_ZPmZ_S + 5212U, // MOVPRFX_ZPzZ_B + 3164U, // MOVPRFX_ZPzZ_D + 68U, // MOVPRFX_ZPzZ_H + 6236U, // MOVPRFX_ZPzZ_S + 16U, // MOVPRFX_ZZ + 293U, // MOVZWi + 293U, // MOVZXi + 1U, // MRS + 43072U, // MSB_ZPmZZ_B + 67174976U, // MSB_ZPmZZ_D + 14489228U, // MSB_ZPmZZ_H + 71369792U, // MSB_ZPmZZ_S + 0U, // MSR + 0U, // MSRpstateImm1 + 0U, // MSRpstateImm4 + 0U, // MSRpstatesvcrImm1 + 67116U, // MSUBWrrr + 67116U, // MSUBXrrr + 1580U, // MUL_ZI_B + 1580U, // MUL_ZI_D + 100U, // MUL_ZI_H + 1580U, // MUL_ZI_S + 4265024U, // MUL_ZPmZ_B + 8457280U, // MUL_ZPmZ_D + 12916292U, // MUL_ZPmZ_H + 16848960U, // MUL_ZPmZ_S + 2231340U, // MUL_ZZZI_D + 24644U, // MUL_ZZZI_H + 2234412U, // MUL_ZZZI_S + 5164U, // MUL_ZZZ_B + 3116U, // MUL_ZZZ_D + 68U, // MUL_ZZZ_H + 6188U, // MUL_ZZZ_S + 397384U, // MULv16i8 + 462924U, // MULv2i32 + 81662028U, // MULv2i32_indexed + 528464U, // MULv4i16 + 80744528U, // MULv4i16_indexed + 200760U, // MULv4i32 + 81662008U, // MULv4i32_indexed + 266300U, // MULv8i16 + 80744508U, // MULv8i16_indexed + 594004U, // MULv8i8 + 293U, // MVNIv2i32 + 293U, // MVNIv2s_msl + 293U, // MVNIv4i16 + 293U, // MVNIv4i32 + 293U, // MVNIv4s_msl + 293U, // MVNIv8i16 + 4265052U, // NANDS_PPzPP + 4265052U, // NAND_PPzPP + 8457260U, // NBSL_ZZZZ + 0U, // NEG_ZPmZ_B + 4U, // NEG_ZPmZ_D + 0U, // NEG_ZPmZ_H + 8U, // NEG_ZPmZ_S + 12U, // NEGv16i8 + 16U, // NEGv1i64 + 20U, // NEGv2i32 + 24U, // NEGv2i64 + 28U, // NEGv4i16 + 32U, // NEGv4i32 + 36U, // NEGv8i16 + 40U, // NEGv8i8 + 4265052U, // NMATCH_PPzZZ_B + 12916292U, // NMATCH_PPzZZ_H + 4265052U, // NORS_PPzPP + 4265052U, // NOR_PPzPP + 0U, // NOT_ZPmZ_B + 4U, // NOT_ZPmZ_D + 0U, // NOT_ZPmZ_H + 8U, // NOT_ZPmZ_S + 12U, // NOTv16i8 + 40U, // NOTv8i8 + 4265052U, // ORNS_PPzPP + 7212U, // ORNWrs + 7212U, // ORNXrs + 4265052U, // ORN_PPzPP + 397384U, // ORNv16i8 + 594004U, // ORNv8i8 + 4265052U, // ORRS_PPzPP + 17964U, // ORRWri + 7212U, // ORRWrs + 18476U, // ORRXri + 7212U, // ORRXrs + 4265052U, // ORR_PPzPP + 18476U, // ORR_ZI + 4265024U, // ORR_ZPmZ_B + 8457280U, // ORR_ZPmZ_D + 12916292U, // ORR_ZPmZ_H + 16848960U, // ORR_ZPmZ_S + 3116U, // ORR_ZZZ + 397384U, // ORRv16i8 + 0U, // ORRv2i32 + 0U, // ORRv4i16 + 0U, // ORRv4i32 + 0U, // ORRv8i16 + 594004U, // ORRv8i8 + 0U, // ORV_VPZ_B + 0U, // ORV_VPZ_D + 0U, // ORV_VPZ_H + 0U, // ORV_VPZ_S + 16U, // PACDA + 16U, // PACDB + 0U, // PACDZA + 0U, // PACDZB + 1580U, // PACGA + 16U, // PACIA + 0U, // PACIA1716 + 0U, // PACIASP + 0U, // PACIAZ + 16U, // PACIB + 0U, // PACIB1716 + 0U, // PACIBSP + 0U, // PACIBZ + 0U, // PACIZA + 0U, // PACIZB + 0U, // PFALSE + 5164U, // PFIRST_B + 6188U, // PMULLB_ZZZ_D + 296U, // PMULLB_ZZZ_H + 0U, // PMULLB_ZZZ_Q + 6188U, // PMULLT_ZZZ_D + 296U, // PMULLT_ZZZ_H + 0U, // PMULLT_ZZZ_Q + 397384U, // PMULLv16i8 + 1U, // PMULLv1i64 + 1U, // PMULLv2i64 + 594004U, // PMULLv8i8 + 5164U, // PMUL_ZZZ_B + 397384U, // PMULv16i8 + 594004U, // PMULv8i8 + 5164U, // PNEXT_B + 3116U, // PNEXT_D + 68U, // PNEXT_H + 6188U, // PNEXT_S + 43680U, // PRFB_D_PZI + 300U, // PRFB_D_SCALED + 304U, // PRFB_D_SXTW_SCALED + 308U, // PRFB_D_UXTW_SCALED + 44192U, // PRFB_PRI + 312U, // PRFB_PRR + 43680U, // PRFB_S_PZI + 316U, // PRFB_S_SXTW_SCALED + 320U, // PRFB_S_UXTW_SCALED + 324U, // PRFD_D_PZI + 328U, // PRFD_D_SCALED + 332U, // PRFD_D_SXTW_SCALED + 336U, // PRFD_D_UXTW_SCALED + 44192U, // PRFD_PRI + 340U, // PRFD_PRR + 324U, // PRFD_S_PZI + 344U, // PRFD_S_SXTW_SCALED + 348U, // PRFD_S_UXTW_SCALED + 352U, // PRFH_D_PZI + 356U, // PRFH_D_SCALED + 360U, // PRFH_D_SXTW_SCALED + 364U, // PRFH_D_UXTW_SCALED + 44192U, // PRFH_PRI + 368U, // PRFH_PRR + 352U, // PRFH_S_PZI + 372U, // PRFH_S_SXTW_SCALED + 376U, // PRFH_S_UXTW_SCALED + 0U, // PRFMl + 121701932U, // PRFMroW + 125896236U, // PRFMroX + 41004U, // PRFMui + 380U, // PRFS_PRR + 1181228U, // PRFUMi + 384U, // PRFW_D_PZI + 388U, // PRFW_D_SCALED + 392U, // PRFW_D_SXTW_SCALED + 396U, // PRFW_D_UXTW_SCALED + 44192U, // PRFW_PRI + 384U, // PRFW_S_PZI + 400U, // PRFW_S_SXTW_SCALED + 404U, // PRFW_S_UXTW_SCALED + 2495532U, // PSEL_PPPRI_B + 2493484U, // PSEL_PPPRI_D + 2492972U, // PSEL_PPPRI_H + 2496556U, // PSEL_PPPRI_S + 16U, // PTEST_PP + 16U, // PTRUES_B + 16U, // PTRUES_D + 0U, // PTRUES_H + 16U, // PTRUES_S + 16U, // PTRUE_B + 16U, // PTRUE_D + 0U, // PTRUE_H + 16U, // PTRUE_S + 0U, // PUNPKHI_PP + 0U, // PUNPKLO_PP + 2604U, // RADDHNB_ZZZ_B + 48U, // RADDHNB_ZZZ_H + 3116U, // RADDHNB_ZZZ_S + 3628U, // RADDHNT_ZZZ_B + 8U, // RADDHNT_ZZZ_H + 556U, // RADDHNT_ZZZ_S + 135220U, // RADDHNv2i64_v2i32 + 135732U, // RADDHNv2i64_v4i32 + 200760U, // RADDHNv4i32_v4i16 + 201272U, // RADDHNv4i32_v8i16 + 266812U, // RADDHNv8i16_v16i8 + 266300U, // RADDHNv8i16_v8i8 + 135220U, // RAX1 + 3116U, // RAX1_ZZZ_D + 16U, // RBITWr + 16U, // RBITXr + 0U, // RBIT_ZPmZ_B + 4U, // RBIT_ZPmZ_D + 0U, // RBIT_ZPmZ_H + 8U, // RBIT_ZPmZ_S + 12U, // RBITv16i8 + 40U, // RBITv8i8 + 408U, // RDFFRS_PPz + 408U, // RDFFR_PPz_REAL + 0U, // RDFFR_P_REAL + 16U, // RDVLI_XI + 0U, // RET + 0U, // RETAA + 0U, // RETAB + 16U, // REV16Wr + 16U, // REV16Xr + 12U, // REV16v16i8 + 40U, // REV16v8i8 + 16U, // REV32Xr + 12U, // REV32v16i8 + 28U, // REV32v4i16 + 36U, // REV32v8i16 + 40U, // REV32v8i8 + 12U, // REV64v16i8 + 20U, // REV64v2i32 + 28U, // REV64v4i16 + 32U, // REV64v4i32 + 36U, // REV64v8i16 + 40U, // REV64v8i8 + 4U, // REVB_ZPmZ_D + 0U, // REVB_ZPmZ_H + 8U, // REVB_ZPmZ_S + 1U, // REVD_ZPmZ + 4U, // REVH_ZPmZ_D + 8U, // REVH_ZPmZ_S + 4U, // REVW_ZPmZ_D + 16U, // REVWr + 16U, // REVXr + 16U, // REV_PP_B + 16U, // REV_PP_D + 0U, // REV_PP_H + 16U, // REV_PP_S + 16U, // REV_ZZ_B + 16U, // REV_ZZ_D + 0U, // REV_ZZ_H + 16U, // REV_ZZ_S + 1580U, // RMIF + 1580U, // RORVWr + 1580U, // RORVXr + 1580U, // RSHRNB_ZZI_B + 100U, // RSHRNB_ZZI_H + 1580U, // RSHRNB_ZZI_S + 18988U, // RSHRNT_ZZI_B + 160U, // RSHRNT_ZZI_H + 18988U, // RSHRNT_ZZI_S + 19004U, // RSHRNv16i8_shift + 1588U, // RSHRNv2i32_shift + 1592U, // RSHRNv4i16_shift + 18996U, // RSHRNv4i32_shift + 19000U, // RSHRNv8i16_shift + 1596U, // RSHRNv8i8_shift + 2604U, // RSUBHNB_ZZZ_B + 48U, // RSUBHNB_ZZZ_H + 3116U, // RSUBHNB_ZZZ_S + 3628U, // RSUBHNT_ZZZ_B + 8U, // RSUBHNT_ZZZ_H + 556U, // RSUBHNT_ZZZ_S + 135220U, // RSUBHNv2i64_v2i32 + 135732U, // RSUBHNv2i64_v4i32 + 200760U, // RSUBHNv4i32_v4i16 + 201272U, // RSUBHNv4i32_v8i16 + 266812U, // RSUBHNv8i16_v16i8 + 266300U, // RSUBHNv8i16_v8i8 + 1068U, // SABALB_ZZZ_D + 0U, // SABALB_ZZZ_H + 3628U, // SABALB_ZZZ_S + 1068U, // SABALT_ZZZ_D + 0U, // SABALT_ZZZ_H + 3628U, // SABALT_ZZZ_S + 397896U, // SABALv16i8_v8i16 + 463436U, // SABALv2i32_v2i64 + 528976U, // SABALv4i16_v4i32 + 201272U, // SABALv4i32_v2i64 + 266812U, // SABALv8i16_v4i32 + 594516U, // SABALv8i8_v8i16 + 0U, // SABA_ZZZ_B + 556U, // SABA_ZZZ_D + 140U, // SABA_ZZZ_H + 1068U, // SABA_ZZZ_S + 397896U, // SABAv16i8 + 463436U, // SABAv2i32 + 528976U, // SABAv4i16 + 201272U, // SABAv4i32 + 266812U, // SABAv8i16 + 594516U, // SABAv8i8 + 6188U, // SABDLB_ZZZ_D + 296U, // SABDLB_ZZZ_H + 2604U, // SABDLB_ZZZ_S + 6188U, // SABDLT_ZZZ_D + 296U, // SABDLT_ZZZ_H + 2604U, // SABDLT_ZZZ_S + 397384U, // SABDLv16i8_v8i16 + 462924U, // SABDLv2i32_v2i64 + 528464U, // SABDLv4i16_v4i32 + 200760U, // SABDLv4i32_v2i64 + 266300U, // SABDLv8i16_v4i32 + 594004U, // SABDLv8i8_v8i16 + 4265024U, // SABD_ZPmZ_B + 8457280U, // SABD_ZPmZ_D + 12916292U, // SABD_ZPmZ_H + 16848960U, // SABD_ZPmZ_S + 397384U, // SABDv16i8 + 462924U, // SABDv2i32 + 528464U, // SABDv4i16 + 200760U, // SABDv4i32 + 266300U, // SABDv8i16 + 594004U, // SABDv8i8 + 1088U, // SADALP_ZPmZ_D + 0U, // SADALP_ZPmZ_H + 3648U, // SADALP_ZPmZ_S + 12U, // SADALPv16i8_v8i16 + 20U, // SADALPv2i32_v1i64 + 28U, // SADALPv4i16_v2i32 + 32U, // SADALPv4i32_v2i64 + 36U, // SADALPv8i16_v4i32 + 40U, // SADALPv8i8_v4i16 + 6188U, // SADDLBT_ZZZ_D + 296U, // SADDLBT_ZZZ_H + 2604U, // SADDLBT_ZZZ_S + 6188U, // SADDLB_ZZZ_D + 296U, // SADDLB_ZZZ_H + 2604U, // SADDLB_ZZZ_S + 12U, // SADDLPv16i8_v8i16 + 20U, // SADDLPv2i32_v1i64 + 28U, // SADDLPv4i16_v2i32 + 32U, // SADDLPv4i32_v2i64 + 36U, // SADDLPv8i16_v4i32 + 40U, // SADDLPv8i8_v4i16 + 6188U, // SADDLT_ZZZ_D + 296U, // SADDLT_ZZZ_H + 2604U, // SADDLT_ZZZ_S + 12U, // SADDLVv16i8v + 28U, // SADDLVv4i16v + 32U, // SADDLVv4i32v + 36U, // SADDLVv8i16v + 40U, // SADDLVv8i8v + 397384U, // SADDLv16i8_v8i16 + 462924U, // SADDLv2i32_v2i64 + 528464U, // SADDLv4i16_v4i32 + 200760U, // SADDLv4i32_v2i64 + 266300U, // SADDLv8i16_v4i32 + 594004U, // SADDLv8i8_v8i16 + 0U, // SADDV_VPZ_B + 0U, // SADDV_VPZ_H + 0U, // SADDV_VPZ_S + 6188U, // SADDWB_ZZZ_D + 296U, // SADDWB_ZZZ_H + 2604U, // SADDWB_ZZZ_S + 6188U, // SADDWT_ZZZ_D + 296U, // SADDWT_ZZZ_H + 2604U, // SADDWT_ZZZ_S + 397372U, // SADDWv16i8_v8i16 + 462900U, // SADDWv2i32_v2i64 + 528440U, // SADDWv4i16_v4i32 + 200756U, // SADDWv4i32_v2i64 + 266296U, // SADDWv8i16_v4i32 + 593980U, // SADDWv8i8_v8i16 + 0U, // SB + 556U, // SBCLB_ZZZ_D + 1068U, // SBCLB_ZZZ_S + 556U, // SBCLT_ZZZ_D + 1068U, // SBCLT_ZZZ_S + 1580U, // SBCSWr + 1580U, // SBCSXr + 1580U, // SBCWr + 1580U, // SBCXr + 67116U, // SBFMWri + 67116U, // SBFMXri + 5164U, // SCLAMP_ZZZ_B + 3116U, // SCLAMP_ZZZ_D + 68U, // SCLAMP_ZZZ_H + 6188U, // SCLAMP_ZZZ_S + 1580U, // SCVTFSWDri + 1580U, // SCVTFSWHri + 1580U, // SCVTFSWSri + 1580U, // SCVTFSXDri + 1580U, // SCVTFSXHri + 1580U, // SCVTFSXSri + 16U, // SCVTFUWDri + 16U, // SCVTFUWHri + 16U, // SCVTFUWSri + 16U, // SCVTFUXDri + 16U, // SCVTFUXHri + 16U, // SCVTFUXSri + 4U, // SCVTF_ZPmZ_DtoD + 1U, // SCVTF_ZPmZ_DtoH + 4U, // SCVTF_ZPmZ_DtoS + 0U, // SCVTF_ZPmZ_HtoH + 8U, // SCVTF_ZPmZ_StoD + 0U, // SCVTF_ZPmZ_StoH + 8U, // SCVTF_ZPmZ_StoS + 1580U, // SCVTFd + 1580U, // SCVTFh + 1580U, // SCVTFs + 16U, // SCVTFv1i16 + 16U, // SCVTFv1i32 + 16U, // SCVTFv1i64 + 20U, // SCVTFv2f32 + 24U, // SCVTFv2f64 + 1612U, // SCVTFv2i32_shift + 1588U, // SCVTFv2i64_shift + 28U, // SCVTFv4f16 + 32U, // SCVTFv4f32 + 1616U, // SCVTFv4i16_shift + 1592U, // SCVTFv4i32_shift + 36U, // SCVTFv8f16 + 1596U, // SCVTFv8i16_shift + 8457280U, // SDIVR_ZPmZ_D + 16848960U, // SDIVR_ZPmZ_S + 1580U, // SDIVWr + 1580U, // SDIVXr + 8457280U, // SDIV_ZPmZ_D + 16848960U, // SDIV_ZPmZ_S + 13569580U, // SDOT_ZZZI_D + 19456U, // SDOT_ZZZI_S + 3628U, // SDOT_ZZZ_D + 0U, // SDOT_ZZZ_S + 2560584U, // SDOTlanev16i8 + 2560596U, // SDOTlanev8i8 + 397896U, // SDOTv16i8 + 594516U, // SDOTv8i8 + 4265004U, // SEL_PPPP + 4265004U, // SEL_ZPZZ_B + 8457260U, // SEL_ZPZZ_D + 12916292U, // SEL_ZPZZ_H + 16848940U, // SEL_ZPZZ_S + 0U, // SETF16 + 0U, // SETF8 + 0U, // SETFFR + 201260U, // SHA1Crrr + 16U, // SHA1Hrr + 201260U, // SHA1Mrrr + 201260U, // SHA1Prrr + 201272U, // SHA1SU0rrr + 32U, // SHA1SU1rr + 201260U, // SHA256H2rrr + 201260U, // SHA256Hrrr + 32U, // SHA256SU0rr + 201272U, // SHA256SU1rrr + 135724U, // SHA512H + 135724U, // SHA512H2 + 24U, // SHA512SU0 + 135732U, // SHA512SU1 + 4265024U, // SHADD_ZPmZ_B + 8457280U, // SHADD_ZPmZ_D + 12916292U, // SHADD_ZPmZ_H + 16848960U, // SHADD_ZPmZ_S + 397384U, // SHADDv16i8 + 462924U, // SHADDv2i32 + 528464U, // SHADDv4i16 + 200760U, // SHADDv4i32 + 266300U, // SHADDv8i16 + 594004U, // SHADDv8i8 + 412U, // SHLLv16i8 + 416U, // SHLLv2i32 + 420U, // SHLLv4i16 + 424U, // SHLLv4i32 + 428U, // SHLLv8i16 + 432U, // SHLLv8i8 + 1580U, // SHLd + 1608U, // SHLv16i8_shift + 1612U, // SHLv2i32_shift + 1588U, // SHLv2i64_shift + 1616U, // SHLv4i16_shift + 1592U, // SHLv4i32_shift + 1596U, // SHLv8i16_shift + 1620U, // SHLv8i8_shift + 1580U, // SHRNB_ZZI_B + 100U, // SHRNB_ZZI_H + 1580U, // SHRNB_ZZI_S + 18988U, // SHRNT_ZZI_B + 160U, // SHRNT_ZZI_H + 18988U, // SHRNT_ZZI_S + 19004U, // SHRNv16i8_shift + 1588U, // SHRNv2i32_shift + 1592U, // SHRNv4i16_shift + 18996U, // SHRNv4i32_shift + 19000U, // SHRNv8i16_shift + 1596U, // SHRNv8i8_shift + 4265024U, // SHSUBR_ZPmZ_B + 8457280U, // SHSUBR_ZPmZ_D + 12916292U, // SHSUBR_ZPmZ_H + 16848960U, // SHSUBR_ZPmZ_S + 4265024U, // SHSUB_ZPmZ_B + 8457280U, // SHSUB_ZPmZ_D + 12916292U, // SHSUB_ZPmZ_H + 16848960U, // SHSUB_ZPmZ_S + 397384U, // SHSUBv16i8 + 462924U, // SHSUBv2i32 + 528464U, // SHSUBv4i16 + 200760U, // SHSUBv4i32 + 266300U, // SHSUBv8i16 + 594004U, // SHSUBv8i8 + 160U, // SLI_ZZI_B + 18988U, // SLI_ZZI_D + 160U, // SLI_ZZI_H + 18988U, // SLI_ZZI_S + 18988U, // SLId + 19016U, // SLIv16i8_shift + 19020U, // SLIv2i32_shift + 18996U, // SLIv2i64_shift + 19024U, // SLIv4i16_shift + 19000U, // SLIv4i32_shift + 19004U, // SLIv8i16_shift + 19028U, // SLIv8i8_shift + 201272U, // SM3PARTW1 + 201272U, // SM3PARTW2 + 1633292344U, // SM3SS1 + 27136568U, // SM3TT1A + 27136568U, // SM3TT1B + 27136568U, // SM3TT2A + 27136568U, // SM3TT2B + 32U, // SM4E + 6188U, // SM4EKEY_ZZZ_S + 200760U, // SM4ENCKEY + 6188U, // SM4E_ZZZ_S + 67116U, // SMADDLrrr + 4265024U, // SMAXP_ZPmZ_B + 8457280U, // SMAXP_ZPmZ_D + 12916292U, // SMAXP_ZPmZ_H + 16848960U, // SMAXP_ZPmZ_S + 397384U, // SMAXPv16i8 + 462924U, // SMAXPv2i32 + 528464U, // SMAXPv4i16 + 200760U, // SMAXPv4i32 + 266300U, // SMAXPv8i16 + 594004U, // SMAXPv8i8 + 0U, // SMAXV_VPZ_B + 0U, // SMAXV_VPZ_D + 0U, // SMAXV_VPZ_H + 0U, // SMAXV_VPZ_S + 12U, // SMAXVv16i8v + 28U, // SMAXVv4i16v + 32U, // SMAXVv4i32v + 36U, // SMAXVv8i16v + 40U, // SMAXVv8i8v + 1580U, // SMAX_ZI_B + 1580U, // SMAX_ZI_D + 100U, // SMAX_ZI_H + 1580U, // SMAX_ZI_S + 4265024U, // SMAX_ZPmZ_B + 8457280U, // SMAX_ZPmZ_D + 12916292U, // SMAX_ZPmZ_H + 16848960U, // SMAX_ZPmZ_S + 397384U, // SMAXv16i8 + 462924U, // SMAXv2i32 + 528464U, // SMAXv4i16 + 200760U, // SMAXv4i32 + 266300U, // SMAXv8i16 + 594004U, // SMAXv8i8 + 0U, // SMC + 4265024U, // SMINP_ZPmZ_B + 8457280U, // SMINP_ZPmZ_D + 12916292U, // SMINP_ZPmZ_H + 16848960U, // SMINP_ZPmZ_S + 397384U, // SMINPv16i8 + 462924U, // SMINPv2i32 + 528464U, // SMINPv4i16 + 200760U, // SMINPv4i32 + 266300U, // SMINPv8i16 + 594004U, // SMINPv8i8 + 0U, // SMINV_VPZ_B + 0U, // SMINV_VPZ_D + 0U, // SMINV_VPZ_H + 0U, // SMINV_VPZ_S + 12U, // SMINVv16i8v + 28U, // SMINVv4i16v + 32U, // SMINVv4i32v + 36U, // SMINVv8i16v + 40U, // SMINVv8i8v + 1580U, // SMIN_ZI_B + 1580U, // SMIN_ZI_D + 100U, // SMIN_ZI_H + 1580U, // SMIN_ZI_S + 4265024U, // SMIN_ZPmZ_B + 8457280U, // SMIN_ZPmZ_D + 12916292U, // SMIN_ZPmZ_H + 16848960U, // SMIN_ZPmZ_S + 397384U, // SMINv16i8 + 462924U, // SMINv2i32 + 528464U, // SMINv4i16 + 200760U, // SMINv4i32 + 266300U, // SMINv8i16 + 594004U, // SMINv8i8 + 13567020U, // SMLALB_ZZZI_D + 13569580U, // SMLALB_ZZZI_S + 1068U, // SMLALB_ZZZ_D + 0U, // SMLALB_ZZZ_H + 3628U, // SMLALB_ZZZ_S + 13567020U, // SMLALT_ZZZI_D + 13569580U, // SMLALT_ZZZI_S + 1068U, // SMLALT_ZZZ_D + 0U, // SMLALT_ZZZ_H + 3628U, // SMLALT_ZZZ_S + 397896U, // SMLALv16i8_v8i16 + 27136588U, // SMLALv2i32_indexed + 463436U, // SMLALv2i32_v2i64 + 26219088U, // SMLALv4i16_indexed + 528976U, // SMLALv4i16_v4i32 + 27136568U, // SMLALv4i32_indexed + 201272U, // SMLALv4i32_v2i64 + 26219068U, // SMLALv8i16_indexed + 266812U, // SMLALv8i16_v4i32 + 594516U, // SMLALv8i8_v8i16 + 13567020U, // SMLSLB_ZZZI_D + 13569580U, // SMLSLB_ZZZI_S + 1068U, // SMLSLB_ZZZ_D + 0U, // SMLSLB_ZZZ_H + 3628U, // SMLSLB_ZZZ_S + 13567020U, // SMLSLT_ZZZI_D + 13569580U, // SMLSLT_ZZZI_S + 1068U, // SMLSLT_ZZZ_D + 0U, // SMLSLT_ZZZ_H + 3628U, // SMLSLT_ZZZ_S + 397896U, // SMLSLv16i8_v8i16 + 27136588U, // SMLSLv2i32_indexed + 463436U, // SMLSLv2i32_v2i64 + 26219088U, // SMLSLv4i16_indexed + 528976U, // SMLSLv4i16_v4i32 + 27136568U, // SMLSLv4i32_indexed + 201272U, // SMLSLv4i32_v2i64 + 26219068U, // SMLSLv8i16_indexed + 266812U, // SMLSLv8i16_v4i32 + 594516U, // SMLSLv8i8_v8i16 + 397896U, // SMMLA + 0U, // SMMLA_ZZZ + 0U, // SMOPA_MPPZZ_D + 0U, // SMOPA_MPPZZ_S + 0U, // SMOPS_MPPZZ_D + 0U, // SMOPS_MPPZZ_S + 21672U, // SMOVvi16to32 + 21672U, // SMOVvi16to32_idx0 + 21672U, // SMOVvi16to64 + 21672U, // SMOVvi16to64_idx0 + 21676U, // SMOVvi32to64 + 21676U, // SMOVvi32to64_idx0 + 21684U, // SMOVvi8to32 + 21684U, // SMOVvi8to32_idx0 + 21684U, // SMOVvi8to64 + 21684U, // SMOVvi8to64_idx0 + 67116U, // SMSUBLrrr + 4265024U, // SMULH_ZPmZ_B + 8457280U, // SMULH_ZPmZ_D + 12916292U, // SMULH_ZPmZ_H + 16848960U, // SMULH_ZPmZ_S + 5164U, // SMULH_ZZZ_B + 3116U, // SMULH_ZZZ_D + 68U, // SMULH_ZZZ_H + 6188U, // SMULH_ZZZ_S + 1580U, // SMULHrr + 2234412U, // SMULLB_ZZZI_D + 2230828U, // SMULLB_ZZZI_S + 6188U, // SMULLB_ZZZ_D + 296U, // SMULLB_ZZZ_H + 2604U, // SMULLB_ZZZ_S + 2234412U, // SMULLT_ZZZI_D + 2230828U, // SMULLT_ZZZI_S + 6188U, // SMULLT_ZZZ_D + 296U, // SMULLT_ZZZ_H + 2604U, // SMULLT_ZZZ_S + 397384U, // SMULLv16i8_v8i16 + 81662028U, // SMULLv2i32_indexed + 462924U, // SMULLv2i32_v2i64 + 80744528U, // SMULLv4i16_indexed + 528464U, // SMULLv4i16_v4i32 + 81662008U, // SMULLv4i32_indexed + 200760U, // SMULLv4i32_v2i64 + 80744508U, // SMULLv8i16_indexed + 266300U, // SMULLv8i16_v4i32 + 594004U, // SMULLv8i8_v8i16 + 44588U, // SPLICE_ZPZZ_B + 45100U, // SPLICE_ZPZZ_D + 436U, // SPLICE_ZPZZ_H + 45612U, // SPLICE_ZPZZ_S + 4265004U, // SPLICE_ZPZ_B + 8457260U, // SPLICE_ZPZ_D + 12916292U, // SPLICE_ZPZ_H + 16848940U, // SPLICE_ZPZ_S + 0U, // SQABS_ZPmZ_B + 4U, // SQABS_ZPmZ_D + 0U, // SQABS_ZPmZ_H + 8U, // SQABS_ZPmZ_S + 12U, // SQABSv16i8 + 16U, // SQABSv1i16 + 16U, // SQABSv1i32 + 16U, // SQABSv1i64 + 16U, // SQABSv1i8 + 20U, // SQABSv2i32 + 24U, // SQABSv2i64 + 28U, // SQABSv4i16 + 32U, // SQABSv4i32 + 36U, // SQABSv8i16 + 40U, // SQABSv8i8 + 8236U, // SQADD_ZI_B + 8748U, // SQADD_ZI_D + 88U, // SQADD_ZI_H + 9260U, // SQADD_ZI_S + 4265024U, // SQADD_ZPmZ_B + 8457280U, // SQADD_ZPmZ_D + 12916292U, // SQADD_ZPmZ_H + 16848960U, // SQADD_ZPmZ_S + 5164U, // SQADD_ZZZ_B + 3116U, // SQADD_ZZZ_D + 68U, // SQADD_ZZZ_H + 6188U, // SQADD_ZZZ_S + 397384U, // SQADDv16i8 + 1580U, // SQADDv1i16 + 1580U, // SQADDv1i32 + 1580U, // SQADDv1i64 + 1580U, // SQADDv1i8 + 462924U, // SQADDv2i32 + 135220U, // SQADDv2i64 + 528464U, // SQADDv4i16 + 200760U, // SQADDv4i32 + 266300U, // SQADDv8i16 + 594004U, // SQADDv8i8 + 33625132U, // SQCADD_ZZI_B + 33623084U, // SQCADD_ZZI_D + 1119812U, // SQCADD_ZZI_H + 33626156U, // SQCADD_ZZI_S + 0U, // SQDECB_XPiI + 1U, // SQDECB_XPiWdI + 0U, // SQDECD_XPiI + 1U, // SQDECD_XPiWdI + 0U, // SQDECD_ZPiI + 0U, // SQDECH_XPiI + 1U, // SQDECH_XPiWdI + 0U, // SQDECH_ZPiI + 46124U, // SQDECP_XPWd_B + 46124U, // SQDECP_XPWd_D + 46124U, // SQDECP_XPWd_H + 46124U, // SQDECP_XPWd_S + 16U, // SQDECP_XP_B + 16U, // SQDECP_XP_D + 16U, // SQDECP_XP_H + 16U, // SQDECP_XP_S + 16U, // SQDECP_ZP_D + 0U, // SQDECP_ZP_H + 16U, // SQDECP_ZP_S + 0U, // SQDECW_XPiI + 1U, // SQDECW_XPiWdI + 0U, // SQDECW_ZPiI + 1068U, // SQDMLALBT_ZZZ_D + 0U, // SQDMLALBT_ZZZ_H + 3628U, // SQDMLALBT_ZZZ_S + 13567020U, // SQDMLALB_ZZZI_D + 13569580U, // SQDMLALB_ZZZI_S + 1068U, // SQDMLALB_ZZZ_D + 0U, // SQDMLALB_ZZZ_H + 3628U, // SQDMLALB_ZZZ_S + 13567020U, // SQDMLALT_ZZZI_D + 13569580U, // SQDMLALT_ZZZI_S + 1068U, // SQDMLALT_ZZZ_D + 0U, // SQDMLALT_ZZZ_H + 3628U, // SQDMLALT_ZZZ_S + 18988U, // SQDMLALi16 + 18988U, // SQDMLALi32 + 26219052U, // SQDMLALv1i32_indexed + 27136556U, // SQDMLALv1i64_indexed + 27136588U, // SQDMLALv2i32_indexed + 463436U, // SQDMLALv2i32_v2i64 + 26219088U, // SQDMLALv4i16_indexed + 528976U, // SQDMLALv4i16_v4i32 + 27136568U, // SQDMLALv4i32_indexed + 201272U, // SQDMLALv4i32_v2i64 + 26219068U, // SQDMLALv8i16_indexed + 266812U, // SQDMLALv8i16_v4i32 + 1068U, // SQDMLSLBT_ZZZ_D + 0U, // SQDMLSLBT_ZZZ_H + 3628U, // SQDMLSLBT_ZZZ_S + 13567020U, // SQDMLSLB_ZZZI_D + 13569580U, // SQDMLSLB_ZZZI_S + 1068U, // SQDMLSLB_ZZZ_D + 0U, // SQDMLSLB_ZZZ_H + 3628U, // SQDMLSLB_ZZZ_S + 13567020U, // SQDMLSLT_ZZZI_D + 13569580U, // SQDMLSLT_ZZZI_S + 1068U, // SQDMLSLT_ZZZ_D + 0U, // SQDMLSLT_ZZZ_H + 3628U, // SQDMLSLT_ZZZ_S + 18988U, // SQDMLSLi16 + 18988U, // SQDMLSLi32 + 26219052U, // SQDMLSLv1i32_indexed + 27136556U, // SQDMLSLv1i64_indexed + 27136588U, // SQDMLSLv2i32_indexed + 463436U, // SQDMLSLv2i32_v2i64 + 26219088U, // SQDMLSLv4i16_indexed + 528976U, // SQDMLSLv4i16_v4i32 + 27136568U, // SQDMLSLv4i32_indexed + 201272U, // SQDMLSLv4i32_v2i64 + 26219068U, // SQDMLSLv8i16_indexed + 266812U, // SQDMLSLv8i16_v4i32 + 2231340U, // SQDMULH_ZZZI_D + 24644U, // SQDMULH_ZZZI_H + 2234412U, // SQDMULH_ZZZI_S + 5164U, // SQDMULH_ZZZ_B + 3116U, // SQDMULH_ZZZ_D + 68U, // SQDMULH_ZZZ_H + 6188U, // SQDMULH_ZZZ_S + 1580U, // SQDMULHv1i16 + 80744492U, // SQDMULHv1i16_indexed + 1580U, // SQDMULHv1i32 + 81661996U, // SQDMULHv1i32_indexed + 462924U, // SQDMULHv2i32 + 81662028U, // SQDMULHv2i32_indexed + 528464U, // SQDMULHv4i16 + 80744528U, // SQDMULHv4i16_indexed + 200760U, // SQDMULHv4i32 + 81662008U, // SQDMULHv4i32_indexed + 266300U, // SQDMULHv8i16 + 80744508U, // SQDMULHv8i16_indexed + 2234412U, // SQDMULLB_ZZZI_D + 2230828U, // SQDMULLB_ZZZI_S + 6188U, // SQDMULLB_ZZZ_D + 296U, // SQDMULLB_ZZZ_H + 2604U, // SQDMULLB_ZZZ_S + 2234412U, // SQDMULLT_ZZZI_D + 2230828U, // SQDMULLT_ZZZI_S + 6188U, // SQDMULLT_ZZZ_D + 296U, // SQDMULLT_ZZZ_H + 2604U, // SQDMULLT_ZZZ_S + 1580U, // SQDMULLi16 + 1580U, // SQDMULLi32 + 80744492U, // SQDMULLv1i32_indexed + 81661996U, // SQDMULLv1i64_indexed + 81662028U, // SQDMULLv2i32_indexed + 462924U, // SQDMULLv2i32_v2i64 + 80744528U, // SQDMULLv4i16_indexed + 528464U, // SQDMULLv4i16_v4i32 + 81662008U, // SQDMULLv4i32_indexed + 200760U, // SQDMULLv4i32_v2i64 + 80744508U, // SQDMULLv8i16_indexed + 266300U, // SQDMULLv8i16_v4i32 + 0U, // SQINCB_XPiI + 1U, // SQINCB_XPiWdI + 0U, // SQINCD_XPiI + 1U, // SQINCD_XPiWdI + 0U, // SQINCD_ZPiI + 0U, // SQINCH_XPiI + 1U, // SQINCH_XPiWdI + 0U, // SQINCH_ZPiI + 46124U, // SQINCP_XPWd_B + 46124U, // SQINCP_XPWd_D + 46124U, // SQINCP_XPWd_H + 46124U, // SQINCP_XPWd_S + 16U, // SQINCP_XP_B + 16U, // SQINCP_XP_D + 16U, // SQINCP_XP_H + 16U, // SQINCP_XP_S + 16U, // SQINCP_ZP_D + 0U, // SQINCP_ZP_H + 16U, // SQINCP_ZP_S + 0U, // SQINCW_XPiI + 1U, // SQINCW_XPiWdI + 0U, // SQINCW_ZPiI + 0U, // SQNEG_ZPmZ_B + 4U, // SQNEG_ZPmZ_D + 0U, // SQNEG_ZPmZ_H + 8U, // SQNEG_ZPmZ_S + 12U, // SQNEGv16i8 + 16U, // SQNEGv1i16 + 16U, // SQNEGv1i32 + 16U, // SQNEGv1i64 + 16U, // SQNEGv1i8 + 20U, // SQNEGv2i32 + 24U, // SQNEGv2i64 + 28U, // SQNEGv4i16 + 32U, // SQNEGv4i32 + 36U, // SQNEGv8i16 + 40U, // SQNEGv8i8 + 46222476U, // SQRDCMLAH_ZZZI_H + 579798060U, // SQRDCMLAH_ZZZI_S + 1250816U, // SQRDCMLAH_ZZZ_B + 50397740U, // SQRDCMLAH_ZZZ_D + 1250956U, // SQRDCMLAH_ZZZ_H + 50398252U, // SQRDCMLAH_ZZZ_S + 13566508U, // SQRDMLAH_ZZZI_D + 19596U, // SQRDMLAH_ZZZI_H + 13567020U, // SQRDMLAH_ZZZI_S + 0U, // SQRDMLAH_ZZZ_B + 556U, // SQRDMLAH_ZZZ_D + 140U, // SQRDMLAH_ZZZ_H + 1068U, // SQRDMLAH_ZZZ_S + 26219052U, // SQRDMLAHi16_indexed + 27136556U, // SQRDMLAHi32_indexed + 18988U, // SQRDMLAHv1i16 + 18988U, // SQRDMLAHv1i32 + 463436U, // SQRDMLAHv2i32 + 27136588U, // SQRDMLAHv2i32_indexed + 528976U, // SQRDMLAHv4i16 + 26219088U, // SQRDMLAHv4i16_indexed + 201272U, // SQRDMLAHv4i32 + 27136568U, // SQRDMLAHv4i32_indexed + 266812U, // SQRDMLAHv8i16 + 26219068U, // SQRDMLAHv8i16_indexed + 13566508U, // SQRDMLSH_ZZZI_D + 19596U, // SQRDMLSH_ZZZI_H + 13567020U, // SQRDMLSH_ZZZI_S + 0U, // SQRDMLSH_ZZZ_B + 556U, // SQRDMLSH_ZZZ_D + 140U, // SQRDMLSH_ZZZ_H + 1068U, // SQRDMLSH_ZZZ_S + 26219052U, // SQRDMLSHi16_indexed + 27136556U, // SQRDMLSHi32_indexed + 18988U, // SQRDMLSHv1i16 + 18988U, // SQRDMLSHv1i32 + 463436U, // SQRDMLSHv2i32 + 27136588U, // SQRDMLSHv2i32_indexed + 528976U, // SQRDMLSHv4i16 + 26219088U, // SQRDMLSHv4i16_indexed + 201272U, // SQRDMLSHv4i32 + 27136568U, // SQRDMLSHv4i32_indexed + 266812U, // SQRDMLSHv8i16 + 26219068U, // SQRDMLSHv8i16_indexed + 2231340U, // SQRDMULH_ZZZI_D + 24644U, // SQRDMULH_ZZZI_H + 2234412U, // SQRDMULH_ZZZI_S + 5164U, // SQRDMULH_ZZZ_B + 3116U, // SQRDMULH_ZZZ_D + 68U, // SQRDMULH_ZZZ_H + 6188U, // SQRDMULH_ZZZ_S + 1580U, // SQRDMULHv1i16 + 80744492U, // SQRDMULHv1i16_indexed + 1580U, // SQRDMULHv1i32 + 81661996U, // SQRDMULHv1i32_indexed + 462924U, // SQRDMULHv2i32 + 81662028U, // SQRDMULHv2i32_indexed + 528464U, // SQRDMULHv4i16 + 80744528U, // SQRDMULHv4i16_indexed + 200760U, // SQRDMULHv4i32 + 81662008U, // SQRDMULHv4i32_indexed + 266300U, // SQRDMULHv8i16 + 80744508U, // SQRDMULHv8i16_indexed + 4265024U, // SQRSHLR_ZPmZ_B + 8457280U, // SQRSHLR_ZPmZ_D + 12916292U, // SQRSHLR_ZPmZ_H + 16848960U, // SQRSHLR_ZPmZ_S + 4265024U, // SQRSHL_ZPmZ_B + 8457280U, // SQRSHL_ZPmZ_D + 12916292U, // SQRSHL_ZPmZ_H + 16848960U, // SQRSHL_ZPmZ_S + 397384U, // SQRSHLv16i8 + 1580U, // SQRSHLv1i16 + 1580U, // SQRSHLv1i32 + 1580U, // SQRSHLv1i64 + 1580U, // SQRSHLv1i8 + 462924U, // SQRSHLv2i32 + 135220U, // SQRSHLv2i64 + 528464U, // SQRSHLv4i16 + 200760U, // SQRSHLv4i32 + 266300U, // SQRSHLv8i16 + 594004U, // SQRSHLv8i8 + 1580U, // SQRSHRNB_ZZI_B + 100U, // SQRSHRNB_ZZI_H + 1580U, // SQRSHRNB_ZZI_S + 18988U, // SQRSHRNT_ZZI_B + 160U, // SQRSHRNT_ZZI_H + 18988U, // SQRSHRNT_ZZI_S + 1580U, // SQRSHRNb + 1580U, // SQRSHRNh + 1580U, // SQRSHRNs + 19004U, // SQRSHRNv16i8_shift + 1588U, // SQRSHRNv2i32_shift + 1592U, // SQRSHRNv4i16_shift + 18996U, // SQRSHRNv4i32_shift + 19000U, // SQRSHRNv8i16_shift + 1596U, // SQRSHRNv8i8_shift + 1580U, // SQRSHRUNB_ZZI_B + 100U, // SQRSHRUNB_ZZI_H + 1580U, // SQRSHRUNB_ZZI_S + 18988U, // SQRSHRUNT_ZZI_B + 160U, // SQRSHRUNT_ZZI_H + 18988U, // SQRSHRUNT_ZZI_S + 1580U, // SQRSHRUNb + 1580U, // SQRSHRUNh + 1580U, // SQRSHRUNs + 19004U, // SQRSHRUNv16i8_shift + 1588U, // SQRSHRUNv2i32_shift + 1592U, // SQRSHRUNv4i16_shift + 18996U, // SQRSHRUNv4i32_shift + 19000U, // SQRSHRUNv8i16_shift + 1596U, // SQRSHRUNv8i8_shift + 4265024U, // SQSHLR_ZPmZ_B + 8457280U, // SQSHLR_ZPmZ_D + 12916292U, // SQSHLR_ZPmZ_H + 16848960U, // SQSHLR_ZPmZ_S + 70720U, // SQSHLU_ZPmI_B + 68672U, // SQSHLU_ZPmI_D + 726596U, // SQSHLU_ZPmI_H + 71744U, // SQSHLU_ZPmI_S + 1580U, // SQSHLUb + 1580U, // SQSHLUd + 1580U, // SQSHLUh + 1580U, // SQSHLUs + 1608U, // SQSHLUv16i8_shift + 1612U, // SQSHLUv2i32_shift + 1588U, // SQSHLUv2i64_shift + 1616U, // SQSHLUv4i16_shift + 1592U, // SQSHLUv4i32_shift + 1596U, // SQSHLUv8i16_shift + 1620U, // SQSHLUv8i8_shift + 70720U, // SQSHL_ZPmI_B + 68672U, // SQSHL_ZPmI_D + 726596U, // SQSHL_ZPmI_H + 71744U, // SQSHL_ZPmI_S + 4265024U, // SQSHL_ZPmZ_B + 8457280U, // SQSHL_ZPmZ_D + 12916292U, // SQSHL_ZPmZ_H + 16848960U, // SQSHL_ZPmZ_S + 1580U, // SQSHLb + 1580U, // SQSHLd + 1580U, // SQSHLh + 1580U, // SQSHLs + 397384U, // SQSHLv16i8 + 1608U, // SQSHLv16i8_shift + 1580U, // SQSHLv1i16 + 1580U, // SQSHLv1i32 + 1580U, // SQSHLv1i64 + 1580U, // SQSHLv1i8 + 462924U, // SQSHLv2i32 + 1612U, // SQSHLv2i32_shift + 135220U, // SQSHLv2i64 + 1588U, // SQSHLv2i64_shift + 528464U, // SQSHLv4i16 + 1616U, // SQSHLv4i16_shift + 200760U, // SQSHLv4i32 + 1592U, // SQSHLv4i32_shift + 266300U, // SQSHLv8i16 + 1596U, // SQSHLv8i16_shift + 594004U, // SQSHLv8i8 + 1620U, // SQSHLv8i8_shift + 1580U, // SQSHRNB_ZZI_B + 100U, // SQSHRNB_ZZI_H + 1580U, // SQSHRNB_ZZI_S + 18988U, // SQSHRNT_ZZI_B + 160U, // SQSHRNT_ZZI_H + 18988U, // SQSHRNT_ZZI_S + 1580U, // SQSHRNb + 1580U, // SQSHRNh + 1580U, // SQSHRNs + 19004U, // SQSHRNv16i8_shift + 1588U, // SQSHRNv2i32_shift + 1592U, // SQSHRNv4i16_shift + 18996U, // SQSHRNv4i32_shift + 19000U, // SQSHRNv8i16_shift + 1596U, // SQSHRNv8i8_shift + 1580U, // SQSHRUNB_ZZI_B + 100U, // SQSHRUNB_ZZI_H + 1580U, // SQSHRUNB_ZZI_S + 18988U, // SQSHRUNT_ZZI_B + 160U, // SQSHRUNT_ZZI_H + 18988U, // SQSHRUNT_ZZI_S + 1580U, // SQSHRUNb + 1580U, // SQSHRUNh + 1580U, // SQSHRUNs + 19004U, // SQSHRUNv16i8_shift + 1588U, // SQSHRUNv2i32_shift + 1592U, // SQSHRUNv4i16_shift + 18996U, // SQSHRUNv4i32_shift + 19000U, // SQSHRUNv8i16_shift + 1596U, // SQSHRUNv8i8_shift + 4265024U, // SQSUBR_ZPmZ_B + 8457280U, // SQSUBR_ZPmZ_D + 12916292U, // SQSUBR_ZPmZ_H + 16848960U, // SQSUBR_ZPmZ_S + 8236U, // SQSUB_ZI_B + 8748U, // SQSUB_ZI_D + 88U, // SQSUB_ZI_H + 9260U, // SQSUB_ZI_S + 4265024U, // SQSUB_ZPmZ_B + 8457280U, // SQSUB_ZPmZ_D + 12916292U, // SQSUB_ZPmZ_H + 16848960U, // SQSUB_ZPmZ_S + 5164U, // SQSUB_ZZZ_B + 3116U, // SQSUB_ZZZ_D + 68U, // SQSUB_ZZZ_H + 6188U, // SQSUB_ZZZ_S + 397384U, // SQSUBv16i8 + 1580U, // SQSUBv1i16 + 1580U, // SQSUBv1i32 + 1580U, // SQSUBv1i64 + 1580U, // SQSUBv1i8 + 462924U, // SQSUBv2i32 + 135220U, // SQSUBv2i64 + 528464U, // SQSUBv4i16 + 200760U, // SQSUBv4i32 + 266300U, // SQSUBv8i16 + 594004U, // SQSUBv8i8 + 16U, // SQXTNB_ZZ_B + 0U, // SQXTNB_ZZ_H + 16U, // SQXTNB_ZZ_S + 16U, // SQXTNT_ZZ_B + 0U, // SQXTNT_ZZ_H + 16U, // SQXTNT_ZZ_S + 36U, // SQXTNv16i8 + 16U, // SQXTNv1i16 + 16U, // SQXTNv1i32 + 16U, // SQXTNv1i8 + 24U, // SQXTNv2i32 + 32U, // SQXTNv4i16 + 24U, // SQXTNv4i32 + 32U, // SQXTNv8i16 + 36U, // SQXTNv8i8 + 16U, // SQXTUNB_ZZ_B + 0U, // SQXTUNB_ZZ_H + 16U, // SQXTUNB_ZZ_S + 16U, // SQXTUNT_ZZ_B + 0U, // SQXTUNT_ZZ_H + 16U, // SQXTUNT_ZZ_S + 36U, // SQXTUNv16i8 + 16U, // SQXTUNv1i16 + 16U, // SQXTUNv1i32 + 16U, // SQXTUNv1i8 + 24U, // SQXTUNv2i32 + 32U, // SQXTUNv4i16 + 24U, // SQXTUNv4i32 + 32U, // SQXTUNv8i16 + 36U, // SQXTUNv8i8 + 4265024U, // SRHADD_ZPmZ_B + 8457280U, // SRHADD_ZPmZ_D + 12916292U, // SRHADD_ZPmZ_H + 16848960U, // SRHADD_ZPmZ_S + 397384U, // SRHADDv16i8 + 462924U, // SRHADDv2i32 + 528464U, // SRHADDv4i16 + 200760U, // SRHADDv4i32 + 266300U, // SRHADDv8i16 + 594004U, // SRHADDv8i8 + 160U, // SRI_ZZI_B + 18988U, // SRI_ZZI_D + 160U, // SRI_ZZI_H + 18988U, // SRI_ZZI_S + 18988U, // SRId + 19016U, // SRIv16i8_shift + 19020U, // SRIv2i32_shift + 18996U, // SRIv2i64_shift + 19024U, // SRIv4i16_shift + 19000U, // SRIv4i32_shift + 19004U, // SRIv8i16_shift + 19028U, // SRIv8i8_shift + 4265024U, // SRSHLR_ZPmZ_B + 8457280U, // SRSHLR_ZPmZ_D + 12916292U, // SRSHLR_ZPmZ_H + 16848960U, // SRSHLR_ZPmZ_S + 4265024U, // SRSHL_ZPmZ_B + 8457280U, // SRSHL_ZPmZ_D + 12916292U, // SRSHL_ZPmZ_H + 16848960U, // SRSHL_ZPmZ_S + 397384U, // SRSHLv16i8 + 1580U, // SRSHLv1i64 + 462924U, // SRSHLv2i32 + 135220U, // SRSHLv2i64 + 528464U, // SRSHLv4i16 + 200760U, // SRSHLv4i32 + 266300U, // SRSHLv8i16 + 594004U, // SRSHLv8i8 + 70720U, // SRSHR_ZPmI_B + 68672U, // SRSHR_ZPmI_D + 726596U, // SRSHR_ZPmI_H + 71744U, // SRSHR_ZPmI_S + 1580U, // SRSHRd + 1608U, // SRSHRv16i8_shift + 1612U, // SRSHRv2i32_shift + 1588U, // SRSHRv2i64_shift + 1616U, // SRSHRv4i16_shift + 1592U, // SRSHRv4i32_shift + 1596U, // SRSHRv8i16_shift + 1620U, // SRSHRv8i8_shift + 160U, // SRSRA_ZZI_B + 18988U, // SRSRA_ZZI_D + 160U, // SRSRA_ZZI_H + 18988U, // SRSRA_ZZI_S + 18988U, // SRSRAd + 19016U, // SRSRAv16i8_shift + 19020U, // SRSRAv2i32_shift + 18996U, // SRSRAv2i64_shift + 19024U, // SRSRAv4i16_shift + 19000U, // SRSRAv4i32_shift + 19004U, // SRSRAv8i16_shift + 19028U, // SRSRAv8i8_shift + 1580U, // SSHLLB_ZZI_D + 100U, // SSHLLB_ZZI_H + 1580U, // SSHLLB_ZZI_S + 1580U, // SSHLLT_ZZI_D + 100U, // SSHLLT_ZZI_H + 1580U, // SSHLLT_ZZI_S + 1608U, // SSHLLv16i8_shift + 1612U, // SSHLLv2i32_shift + 1616U, // SSHLLv4i16_shift + 1592U, // SSHLLv4i32_shift + 1596U, // SSHLLv8i16_shift + 1620U, // SSHLLv8i8_shift + 397384U, // SSHLv16i8 + 1580U, // SSHLv1i64 + 462924U, // SSHLv2i32 + 135220U, // SSHLv2i64 + 528464U, // SSHLv4i16 + 200760U, // SSHLv4i32 + 266300U, // SSHLv8i16 + 594004U, // SSHLv8i8 + 1580U, // SSHRd + 1608U, // SSHRv16i8_shift + 1612U, // SSHRv2i32_shift + 1588U, // SSHRv2i64_shift + 1616U, // SSHRv4i16_shift + 1592U, // SSHRv4i32_shift + 1596U, // SSHRv8i16_shift + 1620U, // SSHRv8i8_shift + 160U, // SSRA_ZZI_B + 18988U, // SSRA_ZZI_D + 160U, // SSRA_ZZI_H + 18988U, // SSRA_ZZI_S + 18988U, // SSRAd + 19016U, // SSRAv16i8_shift + 19020U, // SSRAv2i32_shift + 18996U, // SSRAv2i64_shift + 19024U, // SSRAv4i16_shift + 19000U, // SSRAv4i32_shift + 19004U, // SSRAv8i16_shift + 19028U, // SSRAv8i8_shift + 1198636U, // SST1B_D_IMM + 25132U, // SST1B_D_REAL + 25644U, // SST1B_D_SXTW + 26156U, // SST1B_D_UXTW + 1198636U, // SST1B_S_IMM + 26668U, // SST1B_S_SXTW + 27180U, // SST1B_S_UXTW + 1207340U, // SST1D_IMM + 25132U, // SST1D_REAL + 28204U, // SST1D_SCALED_SCALED_REAL + 25644U, // SST1D_SXTW + 28716U, // SST1D_SXTW_SCALED + 26156U, // SST1D_UXTW + 29228U, // SST1D_UXTW_SCALED + 1209388U, // SST1H_D_IMM + 25132U, // SST1H_D_REAL + 30252U, // SST1H_D_SCALED_SCALED_REAL + 25644U, // SST1H_D_SXTW + 30764U, // SST1H_D_SXTW_SCALED + 26156U, // SST1H_D_UXTW + 31276U, // SST1H_D_UXTW_SCALED + 1209388U, // SST1H_S_IMM + 26668U, // SST1H_S_SXTW + 31788U, // SST1H_S_SXTW_SCALED + 27180U, // SST1H_S_UXTW + 32300U, // SST1H_S_UXTW_SCALED + 1212460U, // SST1W_D_IMM + 25132U, // SST1W_D_REAL + 33324U, // SST1W_D_SCALED_SCALED_REAL + 25644U, // SST1W_D_SXTW + 33836U, // SST1W_D_SXTW_SCALED + 26156U, // SST1W_D_UXTW + 34348U, // SST1W_D_UXTW_SCALED + 1212460U, // SST1W_IMM + 26668U, // SST1W_SXTW + 34860U, // SST1W_SXTW_SCALED + 27180U, // SST1W_UXTW + 35372U, // SST1W_UXTW_SCALED + 6188U, // SSUBLBT_ZZZ_D + 296U, // SSUBLBT_ZZZ_H + 2604U, // SSUBLBT_ZZZ_S + 6188U, // SSUBLB_ZZZ_D + 296U, // SSUBLB_ZZZ_H + 2604U, // SSUBLB_ZZZ_S + 6188U, // SSUBLTB_ZZZ_D + 296U, // SSUBLTB_ZZZ_H + 2604U, // SSUBLTB_ZZZ_S + 6188U, // SSUBLT_ZZZ_D + 296U, // SSUBLT_ZZZ_H + 2604U, // SSUBLT_ZZZ_S + 397384U, // SSUBLv16i8_v8i16 + 462924U, // SSUBLv2i32_v2i64 + 528464U, // SSUBLv4i16_v4i32 + 200760U, // SSUBLv4i32_v2i64 + 266300U, // SSUBLv8i16_v4i32 + 594004U, // SSUBLv8i8_v8i16 + 6188U, // SSUBWB_ZZZ_D + 296U, // SSUBWB_ZZZ_H + 2604U, // SSUBWB_ZZZ_S + 6188U, // SSUBWT_ZZZ_D + 296U, // SSUBWT_ZZZ_H + 2604U, // SSUBWT_ZZZ_S + 397372U, // SSUBWv16i8_v8i16 + 462900U, // SSUBWv2i32_v2i64 + 528440U, // SSUBWv4i16_v4i32 + 200756U, // SSUBWv4i32_v2i64 + 266296U, // SSUBWv8i16_v4i32 + 593980U, // SSUBWv8i8_v8i16 + 36396U, // ST1B + 36396U, // ST1B_D + 2312748U, // ST1B_D_IMM + 36396U, // ST1B_H + 2312748U, // ST1B_H_IMM + 2312748U, // ST1B_IMM + 36396U, // ST1B_S + 2312748U, // ST1B_S_IMM + 36908U, // ST1D + 2312748U, // ST1D_IMM + 0U, // ST1Fourv16b + 0U, // ST1Fourv16b_POST + 0U, // ST1Fourv1d + 0U, // ST1Fourv1d_POST + 0U, // ST1Fourv2d + 0U, // ST1Fourv2d_POST + 0U, // ST1Fourv2s + 0U, // ST1Fourv2s_POST + 0U, // ST1Fourv4h + 0U, // ST1Fourv4h_POST + 0U, // ST1Fourv4s + 0U, // ST1Fourv4s_POST + 0U, // ST1Fourv8b + 0U, // ST1Fourv8b_POST + 0U, // ST1Fourv8h + 0U, // ST1Fourv8h_POST + 37420U, // ST1H + 37420U, // ST1H_D + 2312748U, // ST1H_D_IMM + 2312748U, // ST1H_IMM + 37420U, // ST1H_S + 2312748U, // ST1H_S_IMM + 0U, // ST1Onev16b + 0U, // ST1Onev16b_POST + 0U, // ST1Onev1d + 0U, // ST1Onev1d_POST + 0U, // ST1Onev2d + 0U, // ST1Onev2d_POST + 0U, // ST1Onev2s + 0U, // ST1Onev2s_POST + 0U, // ST1Onev4h + 0U, // ST1Onev4h_POST + 0U, // ST1Onev4s + 0U, // ST1Onev4s_POST + 0U, // ST1Onev8b + 0U, // ST1Onev8b_POST + 0U, // ST1Onev8h + 0U, // ST1Onev8h_POST + 0U, // ST1Threev16b + 0U, // ST1Threev16b_POST + 0U, // ST1Threev1d + 0U, // ST1Threev1d_POST + 0U, // ST1Threev2d + 0U, // ST1Threev2d_POST + 0U, // ST1Threev2s + 0U, // ST1Threev2s_POST + 0U, // ST1Threev4h + 0U, // ST1Threev4h_POST + 0U, // ST1Threev4s + 0U, // ST1Threev4s_POST + 0U, // ST1Threev8b + 0U, // ST1Threev8b_POST + 0U, // ST1Threev8h + 0U, // ST1Threev8h_POST + 0U, // ST1Twov16b + 0U, // ST1Twov16b_POST + 0U, // ST1Twov1d + 0U, // ST1Twov1d_POST + 0U, // ST1Twov2d + 0U, // ST1Twov2d_POST + 0U, // ST1Twov2s + 0U, // ST1Twov2s_POST + 0U, // ST1Twov4h + 0U, // ST1Twov4h_POST + 0U, // ST1Twov4s + 0U, // ST1Twov4s_POST + 0U, // ST1Twov8b + 0U, // ST1Twov8b_POST + 0U, // ST1Twov8h + 0U, // ST1Twov8h_POST + 38444U, // ST1W + 38444U, // ST1W_D + 2312748U, // ST1W_D_IMM + 2312748U, // ST1W_IMM + 265U, // ST1_MXIPXX_H_B + 269U, // ST1_MXIPXX_H_D + 273U, // ST1_MXIPXX_H_H + 277U, // ST1_MXIPXX_H_Q + 281U, // ST1_MXIPXX_H_S + 265U, // ST1_MXIPXX_V_B + 269U, // ST1_MXIPXX_V_D + 273U, // ST1_MXIPXX_V_H + 277U, // ST1_MXIPXX_V_Q + 281U, // ST1_MXIPXX_V_S + 0U, // ST1i16 + 1U, // ST1i16_POST + 0U, // ST1i32 + 1U, // ST1i32_POST + 0U, // ST1i64 + 1U, // ST1i64_POST + 0U, // ST1i8 + 1U, // ST1i8_POST + 36396U, // ST2B + 2323500U, // ST2B_IMM + 36908U, // ST2D + 2323500U, // ST2D_IMM + 1181740U, // ST2GOffset + 39200U, // ST2GPostIndex + 2463788U, // ST2GPreIndex + 37420U, // ST2H + 2323500U, // ST2H_IMM + 0U, // ST2Twov16b + 0U, // ST2Twov16b_POST + 0U, // ST2Twov2d + 0U, // ST2Twov2d_POST + 0U, // ST2Twov2s + 0U, // ST2Twov2s_POST + 0U, // ST2Twov4h + 0U, // ST2Twov4h_POST + 0U, // ST2Twov4s + 0U, // ST2Twov4s_POST + 0U, // ST2Twov8b + 0U, // ST2Twov8b_POST + 0U, // ST2Twov8h + 0U, // ST2Twov8h_POST + 38444U, // ST2W + 2323500U, // ST2W_IMM + 0U, // ST2i16 + 1U, // ST2i16_POST + 0U, // ST2i32 + 1U, // ST2i32_POST + 0U, // ST2i64 + 1U, // ST2i64_POST + 0U, // ST2i8 + 1U, // ST2i8_POST + 36396U, // ST3B + 39468U, // ST3B_IMM + 36908U, // ST3D + 39468U, // ST3D_IMM + 37420U, // ST3H + 39468U, // ST3H_IMM + 0U, // ST3Threev16b + 0U, // ST3Threev16b_POST + 0U, // ST3Threev2d + 0U, // ST3Threev2d_POST + 0U, // ST3Threev2s + 0U, // ST3Threev2s_POST + 0U, // ST3Threev4h + 0U, // ST3Threev4h_POST + 0U, // ST3Threev4s + 0U, // ST3Threev4s_POST + 0U, // ST3Threev8b + 0U, // ST3Threev8b_POST + 0U, // ST3Threev8h + 0U, // ST3Threev8h_POST + 38444U, // ST3W + 39468U, // ST3W_IMM + 0U, // ST3i16 + 1U, // ST3i16_POST + 0U, // ST3i32 + 1U, // ST3i32_POST + 0U, // ST3i64 + 1U, // ST3i64_POST + 0U, // ST3i8 + 1U, // ST3i8_POST + 36396U, // ST4B + 2326572U, // ST4B_IMM + 36908U, // ST4D + 2326572U, // ST4D_IMM + 0U, // ST4Fourv16b + 0U, // ST4Fourv16b_POST + 0U, // ST4Fourv2d + 0U, // ST4Fourv2d_POST + 0U, // ST4Fourv2s + 0U, // ST4Fourv2s_POST + 0U, // ST4Fourv4h + 0U, // ST4Fourv4h_POST + 0U, // ST4Fourv4s + 0U, // ST4Fourv4s_POST + 0U, // ST4Fourv8b + 0U, // ST4Fourv8b_POST + 0U, // ST4Fourv8h + 0U, // ST4Fourv8h_POST + 37420U, // ST4H + 2326572U, // ST4H_IMM + 38444U, // ST4W + 2326572U, // ST4W_IMM + 0U, // ST4i16 + 1U, // ST4i16_POST + 0U, // ST4i32 + 1U, // ST4i32_POST + 0U, // ST4i64 + 1U, // ST4i64_POST + 0U, // ST4i8 + 1U, // ST4i8_POST + 0U, // ST64B + 1U, // ST64BV + 1U, // ST64BV0 + 284U, // STGM + 1181740U, // STGOffset + 92341864U, // STGPi + 39200U, // STGPostIndex + 107235944U, // STGPpost + 1447119464U, // STGPpre + 2463788U, // STGPreIndex + 284U, // STLLRB + 284U, // STLLRH + 284U, // STLLRW + 284U, // STLLRX + 284U, // STLRB + 284U, // STLRH + 284U, // STLRW + 284U, // STLRX + 1181228U, // STLURBi + 1181228U, // STLURHi + 1181228U, // STLURWi + 1181228U, // STLURXi + 2623020U, // STLXPW + 2623020U, // STLXPX + 1181288U, // STLXRB + 1181288U, // STLXRH + 1181288U, // STLXRW + 1181288U, // STLXRX + 88147560U, // STNPDi + 92341864U, // STNPQi + 96536168U, // STNPSi + 96536168U, // STNPWi + 88147560U, // STNPXi + 2312748U, // STNT1B_ZRI + 36396U, // STNT1B_ZRR + 1198636U, // STNT1B_ZZR_D_REAL + 1198636U, // STNT1B_ZZR_S_REAL + 2312748U, // STNT1D_ZRI + 36908U, // STNT1D_ZRR + 1198636U, // STNT1D_ZZR_D_REAL + 2312748U, // STNT1H_ZRI + 37420U, // STNT1H_ZRR + 1198636U, // STNT1H_ZZR_D_REAL + 1198636U, // STNT1H_ZZR_S_REAL + 2312748U, // STNT1W_ZRI + 38444U, // STNT1W_ZRR + 1198636U, // STNT1W_ZZR_D_REAL + 1198636U, // STNT1W_ZZR_S_REAL + 88147560U, // STPDi + 103041640U, // STPDpost + 1442925160U, // STPDpre + 92341864U, // STPQi + 107235944U, // STPQpost + 1447119464U, // STPQpre + 96536168U, // STPSi + 111430248U, // STPSpost + 1451313768U, // STPSpre + 96536168U, // STPWi + 111430248U, // STPWpost + 1451313768U, // STPWpre + 88147560U, // STPXi + 103041640U, // STPXpost + 1442925160U, // STPXpre + 19232U, // STRBBpost + 2443820U, // STRBBpre + 113313324U, // STRBBroW + 117507628U, // STRBBroX + 40492U, // STRBBui + 19232U, // STRBpost + 2443820U, // STRBpre + 113313324U, // STRBroW + 117507628U, // STRBroX + 40492U, // STRBui + 19232U, // STRDpost + 2443820U, // STRDpre + 121701932U, // STRDroW + 125896236U, // STRDroX + 41004U, // STRDui + 19232U, // STRHHpost + 2443820U, // STRHHpre + 130090540U, // STRHHroW + 134284844U, // STRHHroX + 41516U, // STRHHui + 19232U, // STRHpost + 2443820U, // STRHpre + 130090540U, // STRHroW + 134284844U, // STRHroX + 41516U, // STRHui + 19232U, // STRQpost + 2443820U, // STRQpre + 138479148U, // STRQroW + 142673452U, // STRQroX + 42028U, // STRQui + 19232U, // STRSpost + 2443820U, // STRSpre + 146867756U, // STRSroW + 151062060U, // STRSroX + 42540U, // STRSui + 19232U, // STRWpost + 2443820U, // STRWpre + 146867756U, // STRWroW + 151062060U, // STRWroX + 42540U, // STRWui + 19232U, // STRXpost + 2443820U, // STRXpre + 121701932U, // STRXroW + 125896236U, // STRXroX + 41004U, // STRXui + 2295340U, // STR_PXI + 0U, // STR_ZA + 2295340U, // STR_ZXI + 1181228U, // STTRBi + 1181228U, // STTRHi + 1181228U, // STTRWi + 1181228U, // STTRXi + 1181228U, // STURBBi + 1181228U, // STURBi + 1181228U, // STURDi + 1181228U, // STURHHi + 1181228U, // STURHi + 1181228U, // STURQi + 1181228U, // STURSi + 1181228U, // STURWi + 1181228U, // STURXi + 2623020U, // STXPW + 2623020U, // STXPX + 1181288U, // STXRB + 1181288U, // STXRH + 1181288U, // STXRW + 1181288U, // STXRX + 1181740U, // STZ2GOffset + 39200U, // STZ2GPostIndex + 2463788U, // STZ2GPreIndex + 284U, // STZGM + 1181740U, // STZGOffset + 39200U, // STZGPostIndex + 2463788U, // STZGPreIndex + 67628U, // SUBG + 2604U, // SUBHNB_ZZZ_B + 48U, // SUBHNB_ZZZ_H + 3116U, // SUBHNB_ZZZ_S + 3628U, // SUBHNT_ZZZ_B + 8U, // SUBHNT_ZZZ_H + 556U, // SUBHNT_ZZZ_S + 135220U, // SUBHNv2i64_v2i32 + 135732U, // SUBHNv2i64_v4i32 + 200760U, // SUBHNv4i32_v4i16 + 201272U, // SUBHNv4i32_v8i16 + 266812U, // SUBHNv8i16_v16i8 + 266300U, // SUBHNv8i16_v8i8 + 1580U, // SUBP + 1580U, // SUBPS + 8236U, // SUBR_ZI_B + 8748U, // SUBR_ZI_D + 88U, // SUBR_ZI_H + 9260U, // SUBR_ZI_S + 4265024U, // SUBR_ZPmZ_B + 8457280U, // SUBR_ZPmZ_D + 12916292U, // SUBR_ZPmZ_H + 16848960U, // SUBR_ZPmZ_S + 6700U, // SUBSWri + 7212U, // SUBSWrs + 7724U, // SUBSWrx + 6700U, // SUBSXri + 7212U, // SUBSXrs + 7724U, // SUBSXrx + 656940U, // SUBSXrx64 + 6700U, // SUBWri + 7212U, // SUBWrs + 7724U, // SUBWrx + 6700U, // SUBXri + 7212U, // SUBXrs + 7724U, // SUBXrx + 656940U, // SUBXrx64 + 8236U, // SUB_ZI_B + 8748U, // SUB_ZI_D + 88U, // SUB_ZI_H + 9260U, // SUB_ZI_S + 4265024U, // SUB_ZPmZ_B + 8457280U, // SUB_ZPmZ_D + 12916292U, // SUB_ZPmZ_H + 16848960U, // SUB_ZPmZ_S + 5164U, // SUB_ZZZ_B + 3116U, // SUB_ZZZ_D + 68U, // SUB_ZZZ_H + 6188U, // SUB_ZZZ_S + 397384U, // SUBv16i8 + 1580U, // SUBv1i64 + 462924U, // SUBv2i32 + 135220U, // SUBv2i64 + 528464U, // SUBv4i16 + 200760U, // SUBv4i32 + 266300U, // SUBv8i16 + 594004U, // SUBv8i8 + 19456U, // SUDOT_ZZZI + 2560584U, // SUDOTlanev16i8 + 2560596U, // SUDOTlanev8i8 + 0U, // SUMOPA_MPPZZ_D + 0U, // SUMOPA_MPPZZ_S + 0U, // SUMOPS_MPPZZ_D + 0U, // SUMOPS_MPPZZ_S + 16U, // SUNPKHI_ZZ_D + 0U, // SUNPKHI_ZZ_H + 16U, // SUNPKHI_ZZ_S + 16U, // SUNPKLO_ZZ_D + 0U, // SUNPKLO_ZZ_H + 16U, // SUNPKLO_ZZ_S + 4265024U, // SUQADD_ZPmZ_B + 8457280U, // SUQADD_ZPmZ_D + 12916292U, // SUQADD_ZPmZ_H + 16848960U, // SUQADD_ZPmZ_S + 12U, // SUQADDv16i8 + 16U, // SUQADDv1i16 + 16U, // SUQADDv1i32 + 16U, // SUQADDv1i64 + 16U, // SUQADDv1i8 + 20U, // SUQADDv2i32 + 24U, // SUQADDv2i64 + 28U, // SUQADDv4i16 + 32U, // SUQADDv4i32 + 36U, // SUQADDv8i16 + 40U, // SUQADDv8i8 + 0U, // SVC + 1U, // SWPAB + 1U, // SWPAH + 1U, // SWPALB + 1U, // SWPALH + 1U, // SWPALW + 1U, // SWPALX + 1U, // SWPAW + 1U, // SWPAX + 1U, // SWPB + 1U, // SWPH + 1U, // SWPLB + 1U, // SWPLH + 1U, // SWPLW + 1U, // SWPLX + 1U, // SWPW + 1U, // SWPX + 4U, // SXTB_ZPmZ_D + 0U, // SXTB_ZPmZ_H + 8U, // SXTB_ZPmZ_S + 4U, // SXTH_ZPmZ_D + 8U, // SXTH_ZPmZ_S + 4U, // SXTW_ZPmZ_D + 46636U, // SYSLxt + 2U, // SYSxt + 297U, // TBL_ZZZZ_B + 2U, // TBL_ZZZZ_D + 0U, // TBL_ZZZZ_H + 2U, // TBL_ZZZZ_S + 297U, // TBL_ZZZ_B + 2U, // TBL_ZZZ_D + 0U, // TBL_ZZZ_H + 2U, // TBL_ZZZ_S + 14U, // TBLv16i8Four + 14U, // TBLv16i8One + 14U, // TBLv16i8Three + 14U, // TBLv16i8Two + 42U, // TBLv8i8Four + 42U, // TBLv8i8One + 42U, // TBLv8i8Three + 42U, // TBLv8i8Two + 47148U, // TBNZW + 47148U, // TBNZX + 0U, // TBX_ZZZ_B + 556U, // TBX_ZZZ_D + 140U, // TBX_ZZZ_H + 1068U, // TBX_ZZZ_S + 14U, // TBXv16i8Four + 14U, // TBXv16i8One + 14U, // TBXv16i8Three + 14U, // TBXv16i8Two + 42U, // TBXv8i8Four + 42U, // TBXv8i8One + 42U, // TBXv8i8Three + 42U, // TBXv8i8Two + 47148U, // TBZW + 47148U, // TBZX + 0U, // TCANCEL + 0U, // TCOMMIT + 5164U, // TRN1_PPP_B + 3116U, // TRN1_PPP_D + 68U, // TRN1_PPP_H + 6188U, // TRN1_PPP_S + 5164U, // TRN1_ZZZ_B + 3116U, // TRN1_ZZZ_D + 68U, // TRN1_ZZZ_H + 440U, // TRN1_ZZZ_Q + 6188U, // TRN1_ZZZ_S + 397384U, // TRN1v16i8 + 462924U, // TRN1v2i32 + 135220U, // TRN1v2i64 + 528464U, // TRN1v4i16 + 200760U, // TRN1v4i32 + 266300U, // TRN1v8i16 + 594004U, // TRN1v8i8 + 5164U, // TRN2_PPP_B + 3116U, // TRN2_PPP_D + 68U, // TRN2_PPP_H + 6188U, // TRN2_PPP_S + 5164U, // TRN2_ZZZ_B + 3116U, // TRN2_ZZZ_D + 68U, // TRN2_ZZZ_H + 440U, // TRN2_ZZZ_Q + 6188U, // TRN2_ZZZ_S + 397384U, // TRN2v16i8 + 462924U, // TRN2v2i32 + 135220U, // TRN2v2i64 + 528464U, // TRN2v4i16 + 200760U, // TRN2v4i32 + 266300U, // TRN2v8i16 + 594004U, // TRN2v8i8 + 0U, // TSB + 0U, // TSTART + 0U, // TTEST + 1068U, // UABALB_ZZZ_D + 0U, // UABALB_ZZZ_H + 3628U, // UABALB_ZZZ_S + 1068U, // UABALT_ZZZ_D + 0U, // UABALT_ZZZ_H + 3628U, // UABALT_ZZZ_S + 397896U, // UABALv16i8_v8i16 + 463436U, // UABALv2i32_v2i64 + 528976U, // UABALv4i16_v4i32 + 201272U, // UABALv4i32_v2i64 + 266812U, // UABALv8i16_v4i32 + 594516U, // UABALv8i8_v8i16 + 0U, // UABA_ZZZ_B + 556U, // UABA_ZZZ_D + 140U, // UABA_ZZZ_H + 1068U, // UABA_ZZZ_S + 397896U, // UABAv16i8 + 463436U, // UABAv2i32 + 528976U, // UABAv4i16 + 201272U, // UABAv4i32 + 266812U, // UABAv8i16 + 594516U, // UABAv8i8 + 6188U, // UABDLB_ZZZ_D + 296U, // UABDLB_ZZZ_H + 2604U, // UABDLB_ZZZ_S + 6188U, // UABDLT_ZZZ_D + 296U, // UABDLT_ZZZ_H + 2604U, // UABDLT_ZZZ_S + 397384U, // UABDLv16i8_v8i16 + 462924U, // UABDLv2i32_v2i64 + 528464U, // UABDLv4i16_v4i32 + 200760U, // UABDLv4i32_v2i64 + 266300U, // UABDLv8i16_v4i32 + 594004U, // UABDLv8i8_v8i16 + 4265024U, // UABD_ZPmZ_B + 8457280U, // UABD_ZPmZ_D + 12916292U, // UABD_ZPmZ_H + 16848960U, // UABD_ZPmZ_S + 397384U, // UABDv16i8 + 462924U, // UABDv2i32 + 528464U, // UABDv4i16 + 200760U, // UABDv4i32 + 266300U, // UABDv8i16 + 594004U, // UABDv8i8 + 1088U, // UADALP_ZPmZ_D + 0U, // UADALP_ZPmZ_H + 3648U, // UADALP_ZPmZ_S + 12U, // UADALPv16i8_v8i16 + 20U, // UADALPv2i32_v1i64 + 28U, // UADALPv4i16_v2i32 + 32U, // UADALPv4i32_v2i64 + 36U, // UADALPv8i16_v4i32 + 40U, // UADALPv8i8_v4i16 + 6188U, // UADDLB_ZZZ_D + 296U, // UADDLB_ZZZ_H + 2604U, // UADDLB_ZZZ_S + 12U, // UADDLPv16i8_v8i16 + 20U, // UADDLPv2i32_v1i64 + 28U, // UADDLPv4i16_v2i32 + 32U, // UADDLPv4i32_v2i64 + 36U, // UADDLPv8i16_v4i32 + 40U, // UADDLPv8i8_v4i16 + 6188U, // UADDLT_ZZZ_D + 296U, // UADDLT_ZZZ_H + 2604U, // UADDLT_ZZZ_S + 12U, // UADDLVv16i8v + 28U, // UADDLVv4i16v + 32U, // UADDLVv4i32v + 36U, // UADDLVv8i16v + 40U, // UADDLVv8i8v + 397384U, // UADDLv16i8_v8i16 + 462924U, // UADDLv2i32_v2i64 + 528464U, // UADDLv4i16_v4i32 + 200760U, // UADDLv4i32_v2i64 + 266300U, // UADDLv8i16_v4i32 + 594004U, // UADDLv8i8_v8i16 + 0U, // UADDV_VPZ_B + 0U, // UADDV_VPZ_D + 0U, // UADDV_VPZ_H + 0U, // UADDV_VPZ_S + 6188U, // UADDWB_ZZZ_D + 296U, // UADDWB_ZZZ_H + 2604U, // UADDWB_ZZZ_S + 6188U, // UADDWT_ZZZ_D + 296U, // UADDWT_ZZZ_H + 2604U, // UADDWT_ZZZ_S + 397372U, // UADDWv16i8_v8i16 + 462900U, // UADDWv2i32_v2i64 + 528440U, // UADDWv4i16_v4i32 + 200756U, // UADDWv4i32_v2i64 + 266296U, // UADDWv8i16_v4i32 + 593980U, // UADDWv8i8_v8i16 + 67116U, // UBFMWri + 67116U, // UBFMXri + 5164U, // UCLAMP_ZZZ_B + 3116U, // UCLAMP_ZZZ_D + 68U, // UCLAMP_ZZZ_H + 6188U, // UCLAMP_ZZZ_S + 1580U, // UCVTFSWDri + 1580U, // UCVTFSWHri + 1580U, // UCVTFSWSri + 1580U, // UCVTFSXDri + 1580U, // UCVTFSXHri + 1580U, // UCVTFSXSri + 16U, // UCVTFUWDri + 16U, // UCVTFUWHri + 16U, // UCVTFUWSri + 16U, // UCVTFUXDri + 16U, // UCVTFUXHri + 16U, // UCVTFUXSri + 4U, // UCVTF_ZPmZ_DtoD + 1U, // UCVTF_ZPmZ_DtoH + 4U, // UCVTF_ZPmZ_DtoS + 0U, // UCVTF_ZPmZ_HtoH + 8U, // UCVTF_ZPmZ_StoD + 0U, // UCVTF_ZPmZ_StoH + 8U, // UCVTF_ZPmZ_StoS + 1580U, // UCVTFd + 1580U, // UCVTFh + 1580U, // UCVTFs + 16U, // UCVTFv1i16 + 16U, // UCVTFv1i32 + 16U, // UCVTFv1i64 + 20U, // UCVTFv2f32 + 24U, // UCVTFv2f64 + 1612U, // UCVTFv2i32_shift + 1588U, // UCVTFv2i64_shift + 28U, // UCVTFv4f16 + 32U, // UCVTFv4f32 + 1616U, // UCVTFv4i16_shift + 1592U, // UCVTFv4i32_shift + 36U, // UCVTFv8f16 + 1596U, // UCVTFv8i16_shift + 0U, // UDF + 8457280U, // UDIVR_ZPmZ_D + 16848960U, // UDIVR_ZPmZ_S + 1580U, // UDIVWr + 1580U, // UDIVXr + 8457280U, // UDIV_ZPmZ_D + 16848960U, // UDIV_ZPmZ_S + 13569580U, // UDOT_ZZZI_D + 19456U, // UDOT_ZZZI_S + 3628U, // UDOT_ZZZ_D + 0U, // UDOT_ZZZ_S + 2560584U, // UDOTlanev16i8 + 2560596U, // UDOTlanev8i8 + 397896U, // UDOTv16i8 + 594516U, // UDOTv8i8 + 4265024U, // UHADD_ZPmZ_B + 8457280U, // UHADD_ZPmZ_D + 12916292U, // UHADD_ZPmZ_H + 16848960U, // UHADD_ZPmZ_S + 397384U, // UHADDv16i8 + 462924U, // UHADDv2i32 + 528464U, // UHADDv4i16 + 200760U, // UHADDv4i32 + 266300U, // UHADDv8i16 + 594004U, // UHADDv8i8 + 4265024U, // UHSUBR_ZPmZ_B + 8457280U, // UHSUBR_ZPmZ_D + 12916292U, // UHSUBR_ZPmZ_H + 16848960U, // UHSUBR_ZPmZ_S + 4265024U, // UHSUB_ZPmZ_B + 8457280U, // UHSUB_ZPmZ_D + 12916292U, // UHSUB_ZPmZ_H + 16848960U, // UHSUB_ZPmZ_S + 397384U, // UHSUBv16i8 + 462924U, // UHSUBv2i32 + 528464U, // UHSUBv4i16 + 200760U, // UHSUBv4i32 + 266300U, // UHSUBv8i16 + 594004U, // UHSUBv8i8 + 67116U, // UMADDLrrr + 4265024U, // UMAXP_ZPmZ_B + 8457280U, // UMAXP_ZPmZ_D + 12916292U, // UMAXP_ZPmZ_H + 16848960U, // UMAXP_ZPmZ_S + 397384U, // UMAXPv16i8 + 462924U, // UMAXPv2i32 + 528464U, // UMAXPv4i16 + 200760U, // UMAXPv4i32 + 266300U, // UMAXPv8i16 + 594004U, // UMAXPv8i8 + 0U, // UMAXV_VPZ_B + 0U, // UMAXV_VPZ_D + 0U, // UMAXV_VPZ_H + 0U, // UMAXV_VPZ_S + 12U, // UMAXVv16i8v + 28U, // UMAXVv4i16v + 32U, // UMAXVv4i32v + 36U, // UMAXVv8i16v + 40U, // UMAXVv8i8v + 47660U, // UMAX_ZI_B + 47660U, // UMAX_ZI_D + 196U, // UMAX_ZI_H + 47660U, // UMAX_ZI_S + 4265024U, // UMAX_ZPmZ_B + 8457280U, // UMAX_ZPmZ_D + 12916292U, // UMAX_ZPmZ_H + 16848960U, // UMAX_ZPmZ_S + 397384U, // UMAXv16i8 + 462924U, // UMAXv2i32 + 528464U, // UMAXv4i16 + 200760U, // UMAXv4i32 + 266300U, // UMAXv8i16 + 594004U, // UMAXv8i8 + 4265024U, // UMINP_ZPmZ_B + 8457280U, // UMINP_ZPmZ_D + 12916292U, // UMINP_ZPmZ_H + 16848960U, // UMINP_ZPmZ_S + 397384U, // UMINPv16i8 + 462924U, // UMINPv2i32 + 528464U, // UMINPv4i16 + 200760U, // UMINPv4i32 + 266300U, // UMINPv8i16 + 594004U, // UMINPv8i8 + 0U, // UMINV_VPZ_B + 0U, // UMINV_VPZ_D + 0U, // UMINV_VPZ_H + 0U, // UMINV_VPZ_S + 12U, // UMINVv16i8v + 28U, // UMINVv4i16v + 32U, // UMINVv4i32v + 36U, // UMINVv8i16v + 40U, // UMINVv8i8v + 47660U, // UMIN_ZI_B + 47660U, // UMIN_ZI_D + 196U, // UMIN_ZI_H + 47660U, // UMIN_ZI_S + 4265024U, // UMIN_ZPmZ_B + 8457280U, // UMIN_ZPmZ_D + 12916292U, // UMIN_ZPmZ_H + 16848960U, // UMIN_ZPmZ_S + 397384U, // UMINv16i8 + 462924U, // UMINv2i32 + 528464U, // UMINv4i16 + 200760U, // UMINv4i32 + 266300U, // UMINv8i16 + 594004U, // UMINv8i8 + 13567020U, // UMLALB_ZZZI_D + 13569580U, // UMLALB_ZZZI_S + 1068U, // UMLALB_ZZZ_D + 0U, // UMLALB_ZZZ_H + 3628U, // UMLALB_ZZZ_S + 13567020U, // UMLALT_ZZZI_D + 13569580U, // UMLALT_ZZZI_S + 1068U, // UMLALT_ZZZ_D + 0U, // UMLALT_ZZZ_H + 3628U, // UMLALT_ZZZ_S + 397896U, // UMLALv16i8_v8i16 + 27136588U, // UMLALv2i32_indexed + 463436U, // UMLALv2i32_v2i64 + 26219088U, // UMLALv4i16_indexed + 528976U, // UMLALv4i16_v4i32 + 27136568U, // UMLALv4i32_indexed + 201272U, // UMLALv4i32_v2i64 + 26219068U, // UMLALv8i16_indexed + 266812U, // UMLALv8i16_v4i32 + 594516U, // UMLALv8i8_v8i16 + 13567020U, // UMLSLB_ZZZI_D + 13569580U, // UMLSLB_ZZZI_S + 1068U, // UMLSLB_ZZZ_D + 0U, // UMLSLB_ZZZ_H + 3628U, // UMLSLB_ZZZ_S + 13567020U, // UMLSLT_ZZZI_D + 13569580U, // UMLSLT_ZZZI_S + 1068U, // UMLSLT_ZZZ_D + 0U, // UMLSLT_ZZZ_H + 3628U, // UMLSLT_ZZZ_S + 397896U, // UMLSLv16i8_v8i16 + 27136588U, // UMLSLv2i32_indexed + 463436U, // UMLSLv2i32_v2i64 + 26219088U, // UMLSLv4i16_indexed + 528976U, // UMLSLv4i16_v4i32 + 27136568U, // UMLSLv4i32_indexed + 201272U, // UMLSLv4i32_v2i64 + 26219068U, // UMLSLv8i16_indexed + 266812U, // UMLSLv8i16_v4i32 + 594516U, // UMLSLv8i8_v8i16 + 397896U, // UMMLA + 0U, // UMMLA_ZZZ + 0U, // UMOPA_MPPZZ_D + 0U, // UMOPA_MPPZZ_S + 0U, // UMOPS_MPPZZ_D + 0U, // UMOPS_MPPZZ_S + 21672U, // UMOVvi16 + 21672U, // UMOVvi16_idx0 + 21676U, // UMOVvi32 + 21676U, // UMOVvi32_idx0 + 21680U, // UMOVvi64 + 21680U, // UMOVvi64_idx0 + 21684U, // UMOVvi8 + 21684U, // UMOVvi8_idx0 + 67116U, // UMSUBLrrr + 4265024U, // UMULH_ZPmZ_B + 8457280U, // UMULH_ZPmZ_D + 12916292U, // UMULH_ZPmZ_H + 16848960U, // UMULH_ZPmZ_S + 5164U, // UMULH_ZZZ_B + 3116U, // UMULH_ZZZ_D + 68U, // UMULH_ZZZ_H + 6188U, // UMULH_ZZZ_S + 1580U, // UMULHrr + 2234412U, // UMULLB_ZZZI_D + 2230828U, // UMULLB_ZZZI_S + 6188U, // UMULLB_ZZZ_D + 296U, // UMULLB_ZZZ_H + 2604U, // UMULLB_ZZZ_S + 2234412U, // UMULLT_ZZZI_D + 2230828U, // UMULLT_ZZZI_S + 6188U, // UMULLT_ZZZ_D + 296U, // UMULLT_ZZZ_H + 2604U, // UMULLT_ZZZ_S + 397384U, // UMULLv16i8_v8i16 + 81662028U, // UMULLv2i32_indexed + 462924U, // UMULLv2i32_v2i64 + 80744528U, // UMULLv4i16_indexed + 528464U, // UMULLv4i16_v4i32 + 81662008U, // UMULLv4i32_indexed + 200760U, // UMULLv4i32_v2i64 + 80744508U, // UMULLv8i16_indexed + 266300U, // UMULLv8i16_v4i32 + 594004U, // UMULLv8i8_v8i16 + 8236U, // UQADD_ZI_B + 8748U, // UQADD_ZI_D + 88U, // UQADD_ZI_H + 9260U, // UQADD_ZI_S + 4265024U, // UQADD_ZPmZ_B + 8457280U, // UQADD_ZPmZ_D + 12916292U, // UQADD_ZPmZ_H + 16848960U, // UQADD_ZPmZ_S + 5164U, // UQADD_ZZZ_B + 3116U, // UQADD_ZZZ_D + 68U, // UQADD_ZZZ_H + 6188U, // UQADD_ZZZ_S + 397384U, // UQADDv16i8 + 1580U, // UQADDv1i16 + 1580U, // UQADDv1i32 + 1580U, // UQADDv1i64 + 1580U, // UQADDv1i8 + 462924U, // UQADDv2i32 + 135220U, // UQADDv2i64 + 528464U, // UQADDv4i16 + 200760U, // UQADDv4i32 + 266300U, // UQADDv8i16 + 594004U, // UQADDv8i8 + 0U, // UQDECB_WPiI + 0U, // UQDECB_XPiI + 0U, // UQDECD_WPiI + 0U, // UQDECD_XPiI + 0U, // UQDECD_ZPiI + 0U, // UQDECH_WPiI + 0U, // UQDECH_XPiI + 0U, // UQDECH_ZPiI + 16U, // UQDECP_WP_B + 16U, // UQDECP_WP_D + 16U, // UQDECP_WP_H + 16U, // UQDECP_WP_S + 16U, // UQDECP_XP_B + 16U, // UQDECP_XP_D + 16U, // UQDECP_XP_H + 16U, // UQDECP_XP_S + 16U, // UQDECP_ZP_D + 0U, // UQDECP_ZP_H + 16U, // UQDECP_ZP_S + 0U, // UQDECW_WPiI + 0U, // UQDECW_XPiI + 0U, // UQDECW_ZPiI + 0U, // UQINCB_WPiI + 0U, // UQINCB_XPiI + 0U, // UQINCD_WPiI + 0U, // UQINCD_XPiI + 0U, // UQINCD_ZPiI + 0U, // UQINCH_WPiI + 0U, // UQINCH_XPiI + 0U, // UQINCH_ZPiI + 16U, // UQINCP_WP_B + 16U, // UQINCP_WP_D + 16U, // UQINCP_WP_H + 16U, // UQINCP_WP_S + 16U, // UQINCP_XP_B + 16U, // UQINCP_XP_D + 16U, // UQINCP_XP_H + 16U, // UQINCP_XP_S + 16U, // UQINCP_ZP_D + 0U, // UQINCP_ZP_H + 16U, // UQINCP_ZP_S + 0U, // UQINCW_WPiI + 0U, // UQINCW_XPiI + 0U, // UQINCW_ZPiI + 4265024U, // UQRSHLR_ZPmZ_B + 8457280U, // UQRSHLR_ZPmZ_D + 12916292U, // UQRSHLR_ZPmZ_H + 16848960U, // UQRSHLR_ZPmZ_S + 4265024U, // UQRSHL_ZPmZ_B + 8457280U, // UQRSHL_ZPmZ_D + 12916292U, // UQRSHL_ZPmZ_H + 16848960U, // UQRSHL_ZPmZ_S + 397384U, // UQRSHLv16i8 + 1580U, // UQRSHLv1i16 + 1580U, // UQRSHLv1i32 + 1580U, // UQRSHLv1i64 + 1580U, // UQRSHLv1i8 + 462924U, // UQRSHLv2i32 + 135220U, // UQRSHLv2i64 + 528464U, // UQRSHLv4i16 + 200760U, // UQRSHLv4i32 + 266300U, // UQRSHLv8i16 + 594004U, // UQRSHLv8i8 + 1580U, // UQRSHRNB_ZZI_B + 100U, // UQRSHRNB_ZZI_H + 1580U, // UQRSHRNB_ZZI_S + 18988U, // UQRSHRNT_ZZI_B + 160U, // UQRSHRNT_ZZI_H + 18988U, // UQRSHRNT_ZZI_S + 1580U, // UQRSHRNb + 1580U, // UQRSHRNh + 1580U, // UQRSHRNs + 19004U, // UQRSHRNv16i8_shift + 1588U, // UQRSHRNv2i32_shift + 1592U, // UQRSHRNv4i16_shift + 18996U, // UQRSHRNv4i32_shift + 19000U, // UQRSHRNv8i16_shift + 1596U, // UQRSHRNv8i8_shift + 4265024U, // UQSHLR_ZPmZ_B + 8457280U, // UQSHLR_ZPmZ_D + 12916292U, // UQSHLR_ZPmZ_H + 16848960U, // UQSHLR_ZPmZ_S + 70720U, // UQSHL_ZPmI_B + 68672U, // UQSHL_ZPmI_D + 726596U, // UQSHL_ZPmI_H + 71744U, // UQSHL_ZPmI_S + 4265024U, // UQSHL_ZPmZ_B + 8457280U, // UQSHL_ZPmZ_D + 12916292U, // UQSHL_ZPmZ_H + 16848960U, // UQSHL_ZPmZ_S + 1580U, // UQSHLb + 1580U, // UQSHLd + 1580U, // UQSHLh + 1580U, // UQSHLs + 397384U, // UQSHLv16i8 + 1608U, // UQSHLv16i8_shift + 1580U, // UQSHLv1i16 + 1580U, // UQSHLv1i32 + 1580U, // UQSHLv1i64 + 1580U, // UQSHLv1i8 + 462924U, // UQSHLv2i32 + 1612U, // UQSHLv2i32_shift + 135220U, // UQSHLv2i64 + 1588U, // UQSHLv2i64_shift + 528464U, // UQSHLv4i16 + 1616U, // UQSHLv4i16_shift + 200760U, // UQSHLv4i32 + 1592U, // UQSHLv4i32_shift + 266300U, // UQSHLv8i16 + 1596U, // UQSHLv8i16_shift + 594004U, // UQSHLv8i8 + 1620U, // UQSHLv8i8_shift + 1580U, // UQSHRNB_ZZI_B + 100U, // UQSHRNB_ZZI_H + 1580U, // UQSHRNB_ZZI_S + 18988U, // UQSHRNT_ZZI_B + 160U, // UQSHRNT_ZZI_H + 18988U, // UQSHRNT_ZZI_S + 1580U, // UQSHRNb + 1580U, // UQSHRNh + 1580U, // UQSHRNs + 19004U, // UQSHRNv16i8_shift + 1588U, // UQSHRNv2i32_shift + 1592U, // UQSHRNv4i16_shift + 18996U, // UQSHRNv4i32_shift + 19000U, // UQSHRNv8i16_shift + 1596U, // UQSHRNv8i8_shift + 4265024U, // UQSUBR_ZPmZ_B + 8457280U, // UQSUBR_ZPmZ_D + 12916292U, // UQSUBR_ZPmZ_H + 16848960U, // UQSUBR_ZPmZ_S + 8236U, // UQSUB_ZI_B + 8748U, // UQSUB_ZI_D + 88U, // UQSUB_ZI_H + 9260U, // UQSUB_ZI_S + 4265024U, // UQSUB_ZPmZ_B + 8457280U, // UQSUB_ZPmZ_D + 12916292U, // UQSUB_ZPmZ_H + 16848960U, // UQSUB_ZPmZ_S + 5164U, // UQSUB_ZZZ_B + 3116U, // UQSUB_ZZZ_D + 68U, // UQSUB_ZZZ_H + 6188U, // UQSUB_ZZZ_S + 397384U, // UQSUBv16i8 + 1580U, // UQSUBv1i16 + 1580U, // UQSUBv1i32 + 1580U, // UQSUBv1i64 + 1580U, // UQSUBv1i8 + 462924U, // UQSUBv2i32 + 135220U, // UQSUBv2i64 + 528464U, // UQSUBv4i16 + 200760U, // UQSUBv4i32 + 266300U, // UQSUBv8i16 + 594004U, // UQSUBv8i8 + 16U, // UQXTNB_ZZ_B + 0U, // UQXTNB_ZZ_H + 16U, // UQXTNB_ZZ_S + 16U, // UQXTNT_ZZ_B + 0U, // UQXTNT_ZZ_H + 16U, // UQXTNT_ZZ_S + 36U, // UQXTNv16i8 + 16U, // UQXTNv1i16 + 16U, // UQXTNv1i32 + 16U, // UQXTNv1i8 + 24U, // UQXTNv2i32 + 32U, // UQXTNv4i16 + 24U, // UQXTNv4i32 + 32U, // UQXTNv8i16 + 36U, // UQXTNv8i8 + 8U, // URECPE_ZPmZ_S + 20U, // URECPEv2i32 + 32U, // URECPEv4i32 + 4265024U, // URHADD_ZPmZ_B + 8457280U, // URHADD_ZPmZ_D + 12916292U, // URHADD_ZPmZ_H + 16848960U, // URHADD_ZPmZ_S + 397384U, // URHADDv16i8 + 462924U, // URHADDv2i32 + 528464U, // URHADDv4i16 + 200760U, // URHADDv4i32 + 266300U, // URHADDv8i16 + 594004U, // URHADDv8i8 + 4265024U, // URSHLR_ZPmZ_B + 8457280U, // URSHLR_ZPmZ_D + 12916292U, // URSHLR_ZPmZ_H + 16848960U, // URSHLR_ZPmZ_S + 4265024U, // URSHL_ZPmZ_B + 8457280U, // URSHL_ZPmZ_D + 12916292U, // URSHL_ZPmZ_H + 16848960U, // URSHL_ZPmZ_S + 397384U, // URSHLv16i8 + 1580U, // URSHLv1i64 + 462924U, // URSHLv2i32 + 135220U, // URSHLv2i64 + 528464U, // URSHLv4i16 + 200760U, // URSHLv4i32 + 266300U, // URSHLv8i16 + 594004U, // URSHLv8i8 + 70720U, // URSHR_ZPmI_B + 68672U, // URSHR_ZPmI_D + 726596U, // URSHR_ZPmI_H + 71744U, // URSHR_ZPmI_S + 1580U, // URSHRd + 1608U, // URSHRv16i8_shift + 1612U, // URSHRv2i32_shift + 1588U, // URSHRv2i64_shift + 1616U, // URSHRv4i16_shift + 1592U, // URSHRv4i32_shift + 1596U, // URSHRv8i16_shift + 1620U, // URSHRv8i8_shift + 8U, // URSQRTE_ZPmZ_S + 20U, // URSQRTEv2i32 + 32U, // URSQRTEv4i32 + 160U, // URSRA_ZZI_B + 18988U, // URSRA_ZZI_D + 160U, // URSRA_ZZI_H + 18988U, // URSRA_ZZI_S + 18988U, // URSRAd + 19016U, // URSRAv16i8_shift + 19020U, // URSRAv2i32_shift + 18996U, // URSRAv2i64_shift + 19024U, // URSRAv4i16_shift + 19000U, // URSRAv4i32_shift + 19004U, // URSRAv8i16_shift + 19028U, // URSRAv8i8_shift + 0U, // USDOT_ZZZ + 19456U, // USDOT_ZZZI + 2560584U, // USDOTlanev16i8 + 2560596U, // USDOTlanev8i8 + 397896U, // USDOTv16i8 + 594516U, // USDOTv8i8 + 1580U, // USHLLB_ZZI_D + 100U, // USHLLB_ZZI_H + 1580U, // USHLLB_ZZI_S + 1580U, // USHLLT_ZZI_D + 100U, // USHLLT_ZZI_H + 1580U, // USHLLT_ZZI_S + 1608U, // USHLLv16i8_shift + 1612U, // USHLLv2i32_shift + 1616U, // USHLLv4i16_shift + 1592U, // USHLLv4i32_shift + 1596U, // USHLLv8i16_shift + 1620U, // USHLLv8i8_shift + 397384U, // USHLv16i8 + 1580U, // USHLv1i64 + 462924U, // USHLv2i32 + 135220U, // USHLv2i64 + 528464U, // USHLv4i16 + 200760U, // USHLv4i32 + 266300U, // USHLv8i16 + 594004U, // USHLv8i8 + 1580U, // USHRd + 1608U, // USHRv16i8_shift + 1612U, // USHRv2i32_shift + 1588U, // USHRv2i64_shift + 1616U, // USHRv4i16_shift + 1592U, // USHRv4i32_shift + 1596U, // USHRv8i16_shift + 1620U, // USHRv8i8_shift + 397896U, // USMMLA + 0U, // USMMLA_ZZZ + 0U, // USMOPA_MPPZZ_D + 0U, // USMOPA_MPPZZ_S + 0U, // USMOPS_MPPZZ_D + 0U, // USMOPS_MPPZZ_S + 4265024U, // USQADD_ZPmZ_B + 8457280U, // USQADD_ZPmZ_D + 12916292U, // USQADD_ZPmZ_H + 16848960U, // USQADD_ZPmZ_S + 12U, // USQADDv16i8 + 16U, // USQADDv1i16 + 16U, // USQADDv1i32 + 16U, // USQADDv1i64 + 16U, // USQADDv1i8 + 20U, // USQADDv2i32 + 24U, // USQADDv2i64 + 28U, // USQADDv4i16 + 32U, // USQADDv4i32 + 36U, // USQADDv8i16 + 40U, // USQADDv8i8 + 160U, // USRA_ZZI_B + 18988U, // USRA_ZZI_D + 160U, // USRA_ZZI_H + 18988U, // USRA_ZZI_S + 18988U, // USRAd + 19016U, // USRAv16i8_shift + 19020U, // USRAv2i32_shift + 18996U, // USRAv2i64_shift + 19024U, // USRAv4i16_shift + 19000U, // USRAv4i32_shift + 19004U, // USRAv8i16_shift + 19028U, // USRAv8i8_shift + 6188U, // USUBLB_ZZZ_D + 296U, // USUBLB_ZZZ_H + 2604U, // USUBLB_ZZZ_S + 6188U, // USUBLT_ZZZ_D + 296U, // USUBLT_ZZZ_H + 2604U, // USUBLT_ZZZ_S + 397384U, // USUBLv16i8_v8i16 + 462924U, // USUBLv2i32_v2i64 + 528464U, // USUBLv4i16_v4i32 + 200760U, // USUBLv4i32_v2i64 + 266300U, // USUBLv8i16_v4i32 + 594004U, // USUBLv8i8_v8i16 + 6188U, // USUBWB_ZZZ_D + 296U, // USUBWB_ZZZ_H + 2604U, // USUBWB_ZZZ_S + 6188U, // USUBWT_ZZZ_D + 296U, // USUBWT_ZZZ_H + 2604U, // USUBWT_ZZZ_S + 397372U, // USUBWv16i8_v8i16 + 462900U, // USUBWv2i32_v2i64 + 528440U, // USUBWv4i16_v4i32 + 200756U, // USUBWv4i32_v2i64 + 266296U, // USUBWv8i16_v4i32 + 593980U, // USUBWv8i8_v8i16 + 16U, // UUNPKHI_ZZ_D + 0U, // UUNPKHI_ZZ_H + 16U, // UUNPKHI_ZZ_S + 16U, // UUNPKLO_ZZ_D + 0U, // UUNPKLO_ZZ_H + 16U, // UUNPKLO_ZZ_S + 4U, // UXTB_ZPmZ_D + 0U, // UXTB_ZPmZ_H + 8U, // UXTB_ZPmZ_S + 4U, // UXTH_ZPmZ_D + 8U, // UXTH_ZPmZ_S + 4U, // UXTW_ZPmZ_D + 5164U, // UZP1_PPP_B + 3116U, // UZP1_PPP_D + 68U, // UZP1_PPP_H + 6188U, // UZP1_PPP_S + 5164U, // UZP1_ZZZ_B + 3116U, // UZP1_ZZZ_D + 68U, // UZP1_ZZZ_H + 440U, // UZP1_ZZZ_Q + 6188U, // UZP1_ZZZ_S + 397384U, // UZP1v16i8 + 462924U, // UZP1v2i32 + 135220U, // UZP1v2i64 + 528464U, // UZP1v4i16 + 200760U, // UZP1v4i32 + 266300U, // UZP1v8i16 + 594004U, // UZP1v8i8 + 5164U, // UZP2_PPP_B + 3116U, // UZP2_PPP_D + 68U, // UZP2_PPP_H + 6188U, // UZP2_PPP_S + 5164U, // UZP2_ZZZ_B + 3116U, // UZP2_ZZZ_D + 68U, // UZP2_ZZZ_H + 440U, // UZP2_ZZZ_Q + 6188U, // UZP2_ZZZ_S + 397384U, // UZP2v16i8 + 462924U, // UZP2v2i32 + 135220U, // UZP2v2i64 + 528464U, // UZP2v4i16 + 200760U, // UZP2v4i32 + 266300U, // UZP2v8i16 + 594004U, // UZP2v8i8 + 0U, // WFET + 0U, // WFIT + 1580U, // WHILEGE_PWW_B + 1580U, // WHILEGE_PWW_D + 100U, // WHILEGE_PWW_H + 1580U, // WHILEGE_PWW_S + 1580U, // WHILEGE_PXX_B + 1580U, // WHILEGE_PXX_D + 100U, // WHILEGE_PXX_H + 1580U, // WHILEGE_PXX_S + 1580U, // WHILEGT_PWW_B + 1580U, // WHILEGT_PWW_D + 100U, // WHILEGT_PWW_H + 1580U, // WHILEGT_PWW_S + 1580U, // WHILEGT_PXX_B + 1580U, // WHILEGT_PXX_D + 100U, // WHILEGT_PXX_H + 1580U, // WHILEGT_PXX_S + 1580U, // WHILEHI_PWW_B + 1580U, // WHILEHI_PWW_D + 100U, // WHILEHI_PWW_H + 1580U, // WHILEHI_PWW_S + 1580U, // WHILEHI_PXX_B + 1580U, // WHILEHI_PXX_D + 100U, // WHILEHI_PXX_H + 1580U, // WHILEHI_PXX_S + 1580U, // WHILEHS_PWW_B + 1580U, // WHILEHS_PWW_D + 100U, // WHILEHS_PWW_H + 1580U, // WHILEHS_PWW_S + 1580U, // WHILEHS_PXX_B + 1580U, // WHILEHS_PXX_D + 100U, // WHILEHS_PXX_H + 1580U, // WHILEHS_PXX_S + 1580U, // WHILELE_PWW_B + 1580U, // WHILELE_PWW_D + 100U, // WHILELE_PWW_H + 1580U, // WHILELE_PWW_S + 1580U, // WHILELE_PXX_B + 1580U, // WHILELE_PXX_D + 100U, // WHILELE_PXX_H + 1580U, // WHILELE_PXX_S + 1580U, // WHILELO_PWW_B + 1580U, // WHILELO_PWW_D + 100U, // WHILELO_PWW_H + 1580U, // WHILELO_PWW_S + 1580U, // WHILELO_PXX_B + 1580U, // WHILELO_PXX_D + 100U, // WHILELO_PXX_H + 1580U, // WHILELO_PXX_S + 1580U, // WHILELS_PWW_B + 1580U, // WHILELS_PWW_D + 100U, // WHILELS_PWW_H + 1580U, // WHILELS_PWW_S + 1580U, // WHILELS_PXX_B + 1580U, // WHILELS_PXX_D + 100U, // WHILELS_PXX_H + 1580U, // WHILELS_PXX_S + 1580U, // WHILELT_PWW_B + 1580U, // WHILELT_PWW_D + 100U, // WHILELT_PWW_H + 1580U, // WHILELT_PWW_S + 1580U, // WHILELT_PXX_B + 1580U, // WHILELT_PXX_D + 100U, // WHILELT_PXX_H + 1580U, // WHILELT_PXX_S + 1580U, // WHILERW_PXX_B + 1580U, // WHILERW_PXX_D + 100U, // WHILERW_PXX_H + 1580U, // WHILERW_PXX_S + 1580U, // WHILEWR_PXX_B + 1580U, // WHILEWR_PXX_D + 100U, // WHILEWR_PXX_H + 1580U, // WHILEWR_PXX_S + 0U, // WRFFR + 0U, // XAFLAG + 1577012U, // XAR + 70700U, // XAR_ZZZI_B + 68652U, // XAR_ZZZI_D + 726596U, // XAR_ZZZI_H + 71724U, // XAR_ZZZI_S + 0U, // XPACD + 0U, // XPACI + 0U, // XPACLRI + 36U, // XTNv16i8 + 24U, // XTNv2i32 + 32U, // XTNv4i16 + 24U, // XTNv4i32 + 32U, // XTNv8i16 + 36U, // XTNv8i8 + 0U, // ZERO_M + 5164U, // ZIP1_PPP_B + 3116U, // ZIP1_PPP_D + 68U, // ZIP1_PPP_H + 6188U, // ZIP1_PPP_S + 5164U, // ZIP1_ZZZ_B + 3116U, // ZIP1_ZZZ_D + 68U, // ZIP1_ZZZ_H + 440U, // ZIP1_ZZZ_Q + 6188U, // ZIP1_ZZZ_S + 397384U, // ZIP1v16i8 + 462924U, // ZIP1v2i32 + 135220U, // ZIP1v2i64 + 528464U, // ZIP1v4i16 + 200760U, // ZIP1v4i32 + 266300U, // ZIP1v8i16 + 594004U, // ZIP1v8i8 + 5164U, // ZIP2_PPP_B + 3116U, // ZIP2_PPP_D + 68U, // ZIP2_PPP_H + 6188U, // ZIP2_PPP_S + 5164U, // ZIP2_ZZZ_B + 3116U, // ZIP2_ZZZ_D + 68U, // ZIP2_ZZZ_H + 440U, // ZIP2_ZZZ_Q + 6188U, // ZIP2_ZZZ_S + 397384U, // ZIP2v16i8 + 462924U, // ZIP2v2i32 + 135220U, // ZIP2v2i64 + 528464U, // ZIP2v4i16 + 200760U, // ZIP2v4i32 + 266300U, // ZIP2v8i16 + 594004U, // ZIP2v8i8 + 0U, // anonymous_13653 + 0U, // anonymous_13654 + 0U, // anonymous_5364 + 0U, // anonymous_5365 + }; + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + return createMnemonic(AsmStrs + (Bits & 8191) - 1, Bits); +} +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) { + MCMnemonic MnemonicInfo = AArch64_getMnemonic(MI); + +#ifndef CAPSTONE_DIET + + SStream_concat0(O, MnemonicInfo.first); +#endif + + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 7 bits for 66 unique commands. + switch ((Bits >> 13) & 127) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // TLSDESCCALL, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 2: + // ABS_ZPmZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADD_ZI_B, ADD_ZPm... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 0, O, 'b'); + break; + case 3: + // ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 0, O, 'd'); + break; + case 4: + // ABS_ZPmZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADD_ZI_H, ADD_ZPm... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 0, O, 'h'); + SStream_concat0(O, ", "); + break; + case 5: + // ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT_ZZZ_S, ADDP... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 0, O, 's'); + break; + case 6: + // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... + printVRegOperand /* printVRegOperand (+ ) */ (MI, 0, O); + break; + case 7: + // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, FMOPA_MPPZZ_D,... + printMatrixTile /* printMatrixTile (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + SStream_concat0(O, "/m, "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 2, O, 0); + SStream_concat0(O, "/m, "); + break; + case 8: + // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... + printVRegOperand /* printVRegOperand (+ ) */ (MI, 1, O); + break; + case 9: + // ANDV_VPZ_B, EORV_VPZ_B, ORV_VPZ_B, SMAXV_VPZ_B, SMINV_VPZ_B, UMAXV_VPZ... + printZPRasFPR /* printZPRasFPR<8> (+ ) */ (MI, 0, O, 8); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 2, O, 'b'); + return; + break; + case 10: + // ANDV_VPZ_D, EORV_VPZ_D, FADDA_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV... + printZPRasFPR /* printZPRasFPR<64> (+ ) */ (MI, 0, O, 64); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + SStream_concat0(O, ", "); + break; + case 11: + // ANDV_VPZ_H, EORV_VPZ_H, FADDA_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV... + printZPRasFPR /* printZPRasFPR<16> (+ ) */ (MI, 0, O, 16); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + SStream_concat0(O, ", "); + break; + case 12: + // ANDV_VPZ_S, EORV_VPZ_S, FADDA_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAXV... + printZPRasFPR /* printZPRasFPR<32> (+ ) */ (MI, 0, O, 32); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + SStream_concat0(O, ", "); + break; + case 13: + // AUTDA, AUTDB, AUTDZA, AUTDZB, AUTIA, AUTIB, AUTIZA, AUTIZB, CASAB, CAS... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 14: + // B, BL + printAlignedLabel /* printAlignedLabel (+ ) */ (MI, 0, O); + return; + break; + case 15: + // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL + printImmHex /* printImmHex (+ ) */ (MI, 0, O); + return; + break; + case 16: + // Bcc + printCondCode /* printCondCode (+ ) */ (MI, 0, O); + SStream_concat0(O, "\t"); + printAlignedLabel /* printAlignedLabel (+ ) */ (MI, 1, O); + return; + break; + case 17: + // CASPALW, CASPAW, CASPLW, CASPW + printGPRSeqPairsClassOperand /* printGPRSeqPairsClassOperand<32> (+ ) */ ( + MI, 1, O, 32); + SStream_concat0(O, ", "); + printGPRSeqPairsClassOperand /* printGPRSeqPairsClassOperand<32> (+ ) */ ( + MI, 2, O, 32); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "]"); + return; + break; + case 18: + // CASPALX, CASPAX, CASPLX, CASPX + printGPRSeqPairsClassOperand /* printGPRSeqPairsClassOperand<64> (+ ) */ ( + MI, 1, O, 64); + SStream_concat0(O, ", "); + printGPRSeqPairsClassOperand /* printGPRSeqPairsClassOperand<64> (+ ) */ ( + MI, 2, O, 64); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "]"); + return; + break; + case 19: + // DMB, DSB, ISB, TSB + printBarrierOption /* printBarrierOption (+ ) */ (MI, 0, O); + return; + break; + case 20: + // DSBnXS + printBarriernXSOption /* printBarriernXSOption (+ ) */ (MI, 0, O); + return; + break; + case 21: + // DUP_ZZI_Q, EXTRACT_ZPMXI_H_Q, EXTRACT_ZPMXI_V_Q, PMULLB_ZZZ_Q, PMULLT_... + printSVERegOp /* printSVERegOp<'q'> (+ ) */ (MI, 0, O, 'q'); + SStream_concat0(O, ", "); + break; + case 22: + // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... + printTypedVectorList /* printTypedVectorList<0,'d'> (+ ) */ (MI, 0, O, 0, + 'd'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + break; + case 23: + // GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE... + printTypedVectorList /* printTypedVectorList<0,'s'> (+ ) */ (MI, 0, O, 0, + 's'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + break; + case 24: + // HINT + printImm /* printImm (+ ) */ (MI, 0, O); + return; + break; + case 25: + // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... + printMatrixTileVector /* printMatrixTileVector<0> (+ ) */ (MI, 0, O, 0); + SStream_concat0(O, "["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printMatrixIndex /* printMatrixIndex (+ ) */ (MI, 2, O); + break; + case 26: + // INSERT_MXIPZ_V_B, INSERT_MXIPZ_V_D, INSERT_MXIPZ_V_H, INSERT_MXIPZ_V_Q... + printMatrixTileVector /* printMatrixTileVector<1> (+ ) */ (MI, 0, O, 1); + SStream_concat0(O, "["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printMatrixIndex /* printMatrixIndex (+ ) */ (MI, 2, O); + break; + case 27: + // LD1B, LD1B_IMM_REAL, LD1RB_IMM, LD1RO_B, LD1RO_B_IMM, LD1RQ_B, LD1RQ_B... + printTypedVectorList /* printTypedVectorList<0,'b'> (+ ) */ (MI, 0, O, 0, + 'b'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + break; + case 28: + // LD1B_H, LD1B_H_IMM_REAL, LD1H, LD1H_IMM_REAL, LD1RB_H_IMM, LD1RH_IMM, ... + printTypedVectorList /* printTypedVectorList<0,'h'> (+ ) */ (MI, 0, O, 0, + 'h'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + break; + case 29: + // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... + printTypedVectorList /* printTypedVectorList<16, 'b'> (+ ) */ (MI, 0, O, 16, + 'b'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 30: + // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... + printTypedVectorList /* printTypedVectorList<16, 'b'> (+ ) */ (MI, 1, O, 16, + 'b'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "], "); + break; + case 31: + // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... + printTypedVectorList /* printTypedVectorList<1, 'd'> (+ ) */ (MI, 0, O, 1, + 'd'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 32: + // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... + printTypedVectorList /* printTypedVectorList<1, 'd'> (+ ) */ (MI, 1, O, 1, + 'd'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "], "); + break; + case 33: + // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... + printTypedVectorList /* printTypedVectorList<2, 'd'> (+ ) */ (MI, 0, O, 2, + 'd'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 34: + // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... + printTypedVectorList /* printTypedVectorList<2, 'd'> (+ ) */ (MI, 1, O, 2, + 'd'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "], "); + break; + case 35: + // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... + printTypedVectorList /* printTypedVectorList<2, 's'> (+ ) */ (MI, 0, O, 2, + 's'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 36: + // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... + printTypedVectorList /* printTypedVectorList<2, 's'> (+ ) */ (MI, 1, O, 2, + 's'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "], "); + break; + case 37: + // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... + printTypedVectorList /* printTypedVectorList<4, 'h'> (+ ) */ (MI, 0, O, 4, + 'h'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 38: + // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... + printTypedVectorList /* printTypedVectorList<4, 'h'> (+ ) */ (MI, 1, O, 4, + 'h'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "], "); + break; + case 39: + // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... + printTypedVectorList /* printTypedVectorList<4, 's'> (+ ) */ (MI, 0, O, 4, + 's'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 40: + // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... + printTypedVectorList /* printTypedVectorList<4, 's'> (+ ) */ (MI, 1, O, 4, + 's'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "], "); + break; + case 41: + // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... + printTypedVectorList /* printTypedVectorList<8, 'b'> (+ ) */ (MI, 0, O, 8, + 'b'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 42: + // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... + printTypedVectorList /* printTypedVectorList<8, 'b'> (+ ) */ (MI, 1, O, 8, + 'b'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "], "); + break; + case 43: + // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... + printTypedVectorList /* printTypedVectorList<8, 'h'> (+ ) */ (MI, 0, O, 8, + 'h'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 44: + // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... + printTypedVectorList /* printTypedVectorList<8, 'h'> (+ ) */ (MI, 1, O, 8, + 'h'); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "], "); + break; + case 45: + // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... + printTypedVectorList /* printTypedVectorList<0, 'h'> (+ ) */ (MI, 1, O, 0, + 'h'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 46: + // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST + printTypedVectorList /* printTypedVectorList<0, 'h'> (+ ) */ (MI, 2, O, 0, + 'h'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, "], "); + break; + case 47: + // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... + printTypedVectorList /* printTypedVectorList<0, 's'> (+ ) */ (MI, 1, O, 0, + 's'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 48: + // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST + printTypedVectorList /* printTypedVectorList<0, 's'> (+ ) */ (MI, 2, O, 0, + 's'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, "], "); + break; + case 49: + // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... + printTypedVectorList /* printTypedVectorList<0, 'd'> (+ ) */ (MI, 1, O, 0, + 'd'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 50: + // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST + printTypedVectorList /* printTypedVectorList<0, 'd'> (+ ) */ (MI, 2, O, 0, + 'd'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, "], "); + break; + case 51: + // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... + printTypedVectorList /* printTypedVectorList<0, 'b'> (+ ) */ (MI, 1, O, 0, + 'b'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 52: + // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST + printTypedVectorList /* printTypedVectorList<0, 'b'> (+ ) */ (MI, 2, O, 0, + 'b'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, "], "); + break; + case 53: + // LD64B, ST64B + printGPR64x8 /* printGPR64x8 (+ ) */ (MI, 0, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 54: + // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PSEL_PPPRI_B, PSEL_PPPRI_D, PSEL_PPPRI_H... + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 0, O, 0); + break; + case 55: + // LDR_ZA, STR_ZA + printMatrix /* printMatrix<0> (+ ) */ (MI, 0, O, 0); + SStream_concat0(O, "["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printMatrixIndex /* printMatrixIndex (+ ) */ (MI, 2, O); + SStream_concat0(O, "], ["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, ", mul vl]"); + return; + break; + case 56: + // MSR + printMSRSystemRegister /* printMSRSystemRegister (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 57: + // MSRpstateImm1, MSRpstateImm4 + printSystemPStateField /* printSystemPStateField (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 58: + // MSRpstatesvcrImm1 + printSVCROp /* printSVCROp (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 59: + // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... + printPrefetchOp /* printPrefetchOp (+ ) */ (MI, 0, O, true); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + SStream_concat0(O, ", ["); + break; + case 60: + // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi + printPrefetchOp /* printPrefetchOp (+ ) */ (MI, 0, O, false); + break; + case 61: + // ST1i16, ST2i16, ST3i16, ST4i16 + printTypedVectorList /* printTypedVectorList<0, 'h'> (+ ) */ (MI, 0, O, 0, + 'h'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 1, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "]"); + return; + break; + case 62: + // ST1i32, ST2i32, ST3i32, ST4i32 + printTypedVectorList /* printTypedVectorList<0, 's'> (+ ) */ (MI, 0, O, 0, + 's'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 1, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "]"); + return; + break; + case 63: + // ST1i64, ST2i64, ST3i64, ST4i64 + printTypedVectorList /* printTypedVectorList<0, 'd'> (+ ) */ (MI, 0, O, 0, + 'd'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 1, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "]"); + return; + break; + case 64: + // ST1i8, ST2i8, ST3i8, ST4i8 + printTypedVectorList /* printTypedVectorList<0, 'b'> (+ ) */ (MI, 0, O, 0, + 'b'); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 1, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "]"); + return; + break; + case 65: + // ZERO_M + printMatrixTileList /* printMatrixTileList (+ ) */ (MI, 0, O); + return; + break; + } + + // Fragment 1 encoded into 7 bits for 69 unique commands. + switch ((Bits >> 20) & 127) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // TLSDESCCALL, AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, ... + return; + break; + case 1: + // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv1i64, ADCLB_ZZZ_D, ADCLB_ZZZ_S... + SStream_concat0(O, ", "); + break; + case 2: + // ABS_ZPmZ_H, BFCVTNT_ZPmZ, BFCVT_ZPmZ, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPm... + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 2, O, 0); + SStream_concat0(O, "/m, "); + break; + case 3: + // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... + SStream_concat0(O, ".16b, "); + break; + case 4: + // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BF16DOTlanev4bf16, BF... + SStream_concat0(O, ".2s, "); + break; + case 5: + // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... + SStream_concat0(O, ".2d, "); + break; + case 6: + // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BFCVTN, BICv4i16, CLS... + SStream_concat0(O, ".4h, "); + break; + case 7: + // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BF16DOTlanev8bf16, BF... + SStream_concat0(O, ".4s, "); + break; + case 8: + // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BFCVTN2, BICv8i16, CL... + SStream_concat0(O, ".8h, "); + break; + case 9: + // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... + SStream_concat0(O, ".8b, "); + break; + case 10: + // ADDHA_MPPZ_D, ADDVA_MPPZ_D, FMOPA_MPPZZ_D, FMOPS_MPPZZ_D + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 3, O, 'd'); + break; + case 11: + // ADDHA_MPPZ_S, ADDVA_MPPZ_S, FMOPA_MPPZZ_S, FMOPS_MPPZZ_S + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 3, O, 's'); + break; + case 12: + // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 1, O, 's'); + break; + case 13: + // ADDHNT_ZZZ_H, ANDV_VPZ_S, EORV_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAX... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 2, O, 's'); + break; + case 14: + // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + break; + case 15: + // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, BDEP_ZZZ_H, BEXT_ZZZ_H... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 1, O, 'h'); + break; + case 16: + // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... + SStream_concat0(O, ", ["); + break; + case 17: + // ANDV_VPZ_D, EORV_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV_VPZ_D, FMINN... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 2, O, 'd'); + break; + case 18: + // ANDV_VPZ_H, CMLA_ZZZI_H, CMLA_ZZZ_H, DECP_ZP_H, EORBT_ZZZ_H, EORTB_ZZZ... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 2, O, 'h'); + break; + case 19: + // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... + printSVEPattern /* printSVEPattern (+ ) */ (MI, 2, O); + SStream_concat0(O, ", mul "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 20: + // DUP_ZI_H + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 1, O); + return; + break; + case 21: + // DUP_ZR_H, INDEX_RI_H, INDEX_RR_H, WHILEGE_PWW_H, WHILEGE_PXX_H, WHILEG... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 22: + // DUP_ZZI_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, ZIP1_ZZZ_Q,... + printSVERegOp /* printSVERegOp<'q'> (+ ) */ (MI, 1, O, 'q'); + break; + case 23: + // FADDA_VPZ_D + printZPRasFPR /* printZPRasFPR<64> (+ ) */ (MI, 2, O, 64); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 3, O, 'd'); + return; + break; + case 24: + // FADDA_VPZ_H, INSR_ZV_H + printZPRasFPR /* printZPRasFPR<16> (+ ) */ (MI, 2, O, 16); + break; + case 25: + // FADDA_VPZ_S + printZPRasFPR /* printZPRasFPR<32> (+ ) */ (MI, 2, O, 32); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 3, O, 's'); + return; + break; + case 26: + // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri + SStream_concat0(O, ", #0.0"); + return; + break; + case 27: + // FDUP_ZI_H + printFPImmOperand /* printFPImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 28: + // FMOVXDHighr, INSvi64gpr, INSvi64lane + SStream_concat0(O, ".d"); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + break; + case 29: + // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... + SStream_concat0(O, "/z, ["); + break; + case 30: + // INDEX_II_H, INDEX_IR_H + printSImm /* printSImm<16> (+ ) */ (MI, 1, O, 16); + SStream_concat0(O, ", "); + break; + case 31: + // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... + SStream_concat0(O, "], "); + break; + case 32: + // INSR_ZR_H, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRFB... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 33: + // INSvi16gpr, INSvi16lane + SStream_concat0(O, ".h"); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + break; + case 34: + // INSvi32gpr, INSvi32lane + SStream_concat0(O, ".s"); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + break; + case 35: + // INSvi8gpr, INSvi8lane + SStream_concat0(O, ".b"); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + break; + case 36: + // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... + printPostIncOperand /* printPostIncOperand<64> (+ ) */ (MI, 3, O, 64); + return; + break; + case 37: + // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... + printPostIncOperand /* printPostIncOperand<32> (+ ) */ (MI, 3, O, 32); + return; + break; + case 38: + // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... + printPostIncOperand /* printPostIncOperand<16> (+ ) */ (MI, 3, O, 16); + return; + break; + case 39: + // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... + printPostIncOperand /* printPostIncOperand<8> (+ ) */ (MI, 3, O, 8); + return; + break; + case 40: + // LD1Rv16b_POST, LD1Rv8b_POST + printPostIncOperand /* printPostIncOperand<1> (+ ) */ (MI, 3, O, 1); + return; + break; + case 41: + // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... + printPostIncOperand /* printPostIncOperand<4> (+ ) */ (MI, 3, O, 4); + return; + break; + case 42: + // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST + printPostIncOperand /* printPostIncOperand<2> (+ ) */ (MI, 3, O, 2); + return; + break; + case 43: + // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... + printPostIncOperand /* printPostIncOperand<48> (+ ) */ (MI, 3, O, 48); + return; + break; + case 44: + // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... + printPostIncOperand /* printPostIncOperand<24> (+ ) */ (MI, 3, O, 24); + return; + break; + case 45: + // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... + SStream_concat0(O, "]}, "); + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 3, O, 0); + break; + case 46: + // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... + SStream_concat0(O, "]"); + return; + break; + case 47: + // LD1i16_POST, LD2i8_POST + printPostIncOperand /* printPostIncOperand<2> (+ ) */ (MI, 5, O, 2); + return; + break; + case 48: + // LD1i32_POST, LD2i16_POST, LD4i8_POST + printPostIncOperand /* printPostIncOperand<4> (+ ) */ (MI, 5, O, 4); + return; + break; + case 49: + // LD1i64_POST, LD2i32_POST, LD4i16_POST + printPostIncOperand /* printPostIncOperand<8> (+ ) */ (MI, 5, O, 8); + return; + break; + case 50: + // LD1i8_POST + printPostIncOperand /* printPostIncOperand<1> (+ ) */ (MI, 5, O, 1); + return; + break; + case 51: + // LD2i64_POST, LD4i32_POST + printPostIncOperand /* printPostIncOperand<16> (+ ) */ (MI, 5, O, 16); + return; + break; + case 52: + // LD3Rv16b_POST, LD3Rv8b_POST + printPostIncOperand /* printPostIncOperand<3> (+ ) */ (MI, 3, O, 3); + return; + break; + case 53: + // LD3Rv2s_POST, LD3Rv4s_POST + printPostIncOperand /* printPostIncOperand<12> (+ ) */ (MI, 3, O, 12); + return; + break; + case 54: + // LD3Rv4h_POST, LD3Rv8h_POST + printPostIncOperand /* printPostIncOperand<6> (+ ) */ (MI, 3, O, 6); + return; + break; + case 55: + // LD3i16_POST + printPostIncOperand /* printPostIncOperand<6> (+ ) */ (MI, 5, O, 6); + return; + break; + case 56: + // LD3i32_POST + printPostIncOperand /* printPostIncOperand<12> (+ ) */ (MI, 5, O, 12); + return; + break; + case 57: + // LD3i64_POST + printPostIncOperand /* printPostIncOperand<24> (+ ) */ (MI, 5, O, 24); + return; + break; + case 58: + // LD3i8_POST + printPostIncOperand /* printPostIncOperand<3> (+ ) */ (MI, 5, O, 3); + return; + break; + case 59: + // LD4i64_POST + printPostIncOperand /* printPostIncOperand<32> (+ ) */ (MI, 5, O, 32); + return; + break; + case 60: + // PMULLB_ZZZ_H, PMULLT_ZZZ_H, PUNPKHI_PP, PUNPKLO_PP, SABDLB_ZZZ_H, SABD... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 1, O, 'b'); + break; + case 61: + // PMULLB_ZZZ_Q, PMULLT_ZZZ_Q + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 1, O, 'd'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 2, O, 'd'); + return; + break; + case 62: + // PMULLv1i64, PMULLv2i64 + SStream_concat0(O, ".1q, "); + printVRegOperand /* printVRegOperand (+ ) */ (MI, 1, O); + break; + case 63: + // PTRUES_H, PTRUE_H + printSVEPattern /* printSVEPattern (+ ) */ (MI, 1, O); + return; + break; + case 64: + // SABALB_ZZZ_H, SABALT_ZZZ_H, SADDV_VPZ_B, SMLALB_ZZZ_H, SMLALT_ZZZ_H, S... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 2, O, 'b'); + break; + case 65: + // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... + SStream_concat0(O, ".1d, "); + break; + case 66: + // SMOPA_MPPZZ_D, SMOPS_MPPZZ_D, SUMOPA_MPPZZ_D, SUMOPS_MPPZZ_D, UMOPA_MP... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 3, O, 'h'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 4, O, 'h'); + return; + break; + case 67: + // SMOPA_MPPZZ_S, SMOPS_MPPZZ_S, SUMOPA_MPPZZ_S, SUMOPS_MPPZZ_S, UMOPA_MP... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 3, O, 'b'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 4, O, 'b'); + return; + break; + case 68: + // TBL_ZZZZ_H, TBL_ZZZ_H + printTypedVectorList /* printTypedVectorList<0,'h'> (+ ) */ (MI, 1, O, 0, + 'h'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 2, O, 'h'); + return; + break; + } + + // Fragment 2 encoded into 7 bits for 69 unique commands. + switch ((Bits >> 27) & 127) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 2, O, 0); + SStream_concat0(O, "/m, "); + break; + case 1: + // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 3, O, 'h'); + return; + break; + case 2: + // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... + printVRegOperand /* printVRegOperand (+ ) */ (MI, 1, O); + break; + case 3: + // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ADDSWri, ADDS... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 4: + // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 2, O, 'd'); + break; + case 5: + // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 2, O, 's'); + break; + case 6: + // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, ANDV_VPZ_D, AN... + return; + break; + case 7: + // ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 1, O, 'h'); + break; + case 8: + // ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_Z... + SStream_concat0(O, ", "); + break; + case 9: + // ADDHNB_ZZZ_S, ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, A... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 1, O, 'd'); + break; + case 10: + // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMMLA_B_ZZI, BFMMLA_B_ZZZ, BFMMLA... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 2, O, 'h'); + break; + case 11: + // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... + printVRegOperand /* printVRegOperand (+ ) */ (MI, 2, O); + break; + case 12: + // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm... + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 1, O, 0); + break; + case 13: + // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... + SStream_concat0(O, "/m, "); + break; + case 14: + // ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, AESIMC_ZZ_B, AESMC_ZZ_B, ... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 1, O, 'b'); + break; + case 15: + // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 1, O, 's'); + break; + case 16: + // ADRP + printAdrpLabel /* printAdrpLabel (+ ) */ (MI, 1, O); + return; + break; + case 17: + // AUTDA, AUTDB, AUTIA, AUTIB, BFMWri, BFMXri, CASAB, CASAH, CASALB, CASA... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 18: + // BFCVTNT_ZPmZ, BFCVT_ZPmZ, FCVTNT_ZPmZ_StoH, FCVT_ZPmZ_StoH, SCVTF_ZPmZ... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 3, O, 's'); + return; + break; + case 19: + // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... + printImm /* printImm (+ ) */ (MI, 2, O); + printShifter /* printShifter (+ ) */ (MI, 3, O); + return; + break; + case 20: + // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... + printAlignedLabel /* printAlignedLabel (+ ) */ (MI, 1, O); + return; + break; + case 21: + // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, SABA_ZZ... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 2, O, 'b'); + SStream_concat0(O, ", "); + break; + case 22: + // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE... + SStream_concat0(O, "/z, "); + break; + case 23: + // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... + printSVEPattern /* printSVEPattern (+ ) */ (MI, 1, O); + break; + case 24: + // CPY_ZPmI_H + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 3, O); + return; + break; + case 25: + // CPY_ZPmR_H, CPY_ZPmV_H, INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 26: + // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... + printSVEPattern /* printSVEPattern (+ ) */ (MI, 2, O); + SStream_concat0(O, ", mul "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 27: + // DUPM_ZI + printLogicalImm64 /* printLogicalImm (+ ) */ (MI, 1, O); + return; + break; + case 28: + // DUP_ZI_B + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 1, O); + return; + break; + case 29: + // DUP_ZI_D + printImm8OptLsl64 /* printImm8OptLsl (+ ) */ (MI, 1, O); + return; + break; + case 30: + // DUP_ZI_S + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 1, O); + return; + break; + case 31: + // DUP_ZZI_H, DUP_ZZI_Q + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + return; + break; + case 32: + // EXT_ZZI_B, TBL_ZZZZ_B, TBL_ZZZ_B + printTypedVectorList /* printTypedVectorList<0,'b'> (+ ) */ (MI, 1, O, 0, + 'b'); + SStream_concat0(O, ", "); + break; + case 33: + // FCPY_ZPmI_H + printFPImmOperand /* printFPImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 34: + // FCVT_ZPmZ_DtoH, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_DtoH + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 3, O, 'd'); + return; + break; + case 35: + // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... + printFPImmOperand /* printFPImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 36: + // INDEX_II_B, INDEX_IR_B + printSImm /* printSImm<8> (+ ) */ (MI, 1, O, 8); + SStream_concat0(O, ", "); + break; + case 37: + // INDEX_II_H + printSImm /* printSImm<16> (+ ) */ (MI, 2, O, 16); + return; + break; + case 38: + // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... + printSVERegOp /* printSVERegOp<> (+ ) */ (MI, 3, O, 0); + SStream_concat0(O, "/m, "); + break; + case 39: + // INSR_ZV_B + printZPRasFPR /* printZPRasFPR<8> (+ ) */ (MI, 2, O, 8); + return; + break; + case 40: + // INSR_ZV_D + printZPRasFPR /* printZPRasFPR<64> (+ ) */ (MI, 2, O, 64); + return; + break; + case 41: + // INSR_ZV_S + printZPRasFPR /* printZPRasFPR<32> (+ ) */ (MI, 2, O, 32); + return; + break; + case 42: + // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane + printVRegOperand /* printVRegOperand (+ ) */ (MI, 3, O); + break; + case 43: + // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... + SStream_concat0(O, "/z, ["); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + break; + case 44: + // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "]"); + return; + break; + case 45: + // MOVID, MOVIv2d_ns + printSIMDType10Operand /* printSIMDType10Operand (+ ) */ (MI, 1, O); + return; + break; + case 46: + // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... + printImm /* printImm (+ ) */ (MI, 1, O); + break; + case 47: + // MRS + printMRSSystemRegister /* printMRSSystemRegister (+ ) */ (MI, 1, O); + return; + break; + case 48: + // PMULLv1i64 + SStream_concat0(O, ".1d, "); + printVRegOperand /* printVRegOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ".1d"); + return; + break; + case 49: + // PMULLv2i64 + SStream_concat0(O, ".2d, "); + printVRegOperand /* printVRegOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ".2d"); + return; + break; + case 50: + // REVD_ZPmZ + printSVERegOp /* printSVERegOp<'q'> (+ ) */ (MI, 3, O, 'q'); + return; + break; + case 51: + // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... + printGPR64as32 /* printGPR64as32 (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printSVEPattern /* printSVEPattern (+ ) */ (MI, 2, O); + SStream_concat0(O, ", mul "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 52: + // ST1_MXIPXX_H_B, ST1_MXIPXX_H_D, ST1_MXIPXX_H_H, ST1_MXIPXX_H_Q, ST1_MX... + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + break; + case 53: + // ST1i16_POST, ST2i8_POST + printPostIncOperand /* printPostIncOperand<2> (+ ) */ (MI, 4, O, 2); + return; + break; + case 54: + // ST1i32_POST, ST2i16_POST, ST4i8_POST + printPostIncOperand /* printPostIncOperand<4> (+ ) */ (MI, 4, O, 4); + return; + break; + case 55: + // ST1i64_POST, ST2i32_POST, ST4i16_POST + printPostIncOperand /* printPostIncOperand<8> (+ ) */ (MI, 4, O, 8); + return; + break; + case 56: + // ST1i8_POST + printPostIncOperand /* printPostIncOperand<1> (+ ) */ (MI, 4, O, 1); + return; + break; + case 57: + // ST2i64_POST, ST4i32_POST + printPostIncOperand /* printPostIncOperand<16> (+ ) */ (MI, 4, O, 16); + return; + break; + case 58: + // ST3i16_POST + printPostIncOperand /* printPostIncOperand<6> (+ ) */ (MI, 4, O, 6); + return; + break; + case 59: + // ST3i32_POST + printPostIncOperand /* printPostIncOperand<12> (+ ) */ (MI, 4, O, 12); + return; + break; + case 60: + // ST3i64_POST + printPostIncOperand /* printPostIncOperand<24> (+ ) */ (MI, 4, O, 24); + return; + break; + case 61: + // ST3i8_POST + printPostIncOperand /* printPostIncOperand<3> (+ ) */ (MI, 4, O, 3); + return; + break; + case 62: + // ST4i64_POST + printPostIncOperand /* printPostIncOperand<32> (+ ) */ (MI, 4, O, 32); + return; + break; + case 63: + // ST64BV, ST64BV0 + printGPR64x8 /* printGPR64x8 (+ ) */ (MI, 1, O); + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "]"); + return; + break; + case 64: + // SYSxt + printSysCROperand /* printSysCROperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printSysCROperand /* printSysCROperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + return; + break; + case 65: + // TBL_ZZZZ_D, TBL_ZZZ_D + printTypedVectorList /* printTypedVectorList<0,'d'> (+ ) */ (MI, 1, O, 0, + 'd'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 2, O, 'd'); + return; + break; + case 66: + // TBL_ZZZZ_S, TBL_ZZZ_S + printTypedVectorList /* printTypedVectorList<0,'s'> (+ ) */ (MI, 1, O, 0, + 's'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 2, O, 's'); + return; + break; + case 67: + // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... + printTypedVectorList /* printTypedVectorList<16, 'b'> (+ ) */ (MI, 1, O, 16, + 'b'); + SStream_concat0(O, ", "); + printVRegOperand /* printVRegOperand (+ ) */ (MI, 2, O); + break; + case 68: + // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... + printTypedVectorList /* printTypedVectorList<16, 'b'> (+ ) */ (MI, 2, O, 16, + 'b'); + SStream_concat0(O, ", "); + printVRegOperand /* printVRegOperand (+ ) */ (MI, 3, O); + break; + } + + // Fragment 3 encoded into 7 bits for 111 unique commands. + switch ((Bits >> 34) & 127) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CDOT_ZZZI_S, CDOT_ZZZ_S, CLS_ZPmZ_B,... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 3, O, 'b'); + break; + case 1: + // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 3, O, 'd'); + return; + break; + case 2: + // ABS_ZPmZ_S, ADDHNT_ZZZ_H, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPm... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 3, O, 's'); + return; + break; + case 3: + // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... + SStream_concat0(O, ".16b"); + return; + break; + case 4: + // ABSv1i64, ADR, AESIMC_ZZ_B, AESMC_ZZ_B, AUTDA, AUTDB, AUTIA, AUTIB, BF... + return; + break; + case 5: + // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... + SStream_concat0(O, ".2s"); + return; + break; + case 6: + // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... + SStream_concat0(O, ".2d"); + return; + break; + case 7: + // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT... + SStream_concat0(O, ".4h"); + return; + break; + case 8: + // ABSv4i32, ADDVv4i32v, BFCVTN, BFCVTN2, CLSv4i32, CLZv4i32, FABSv4f32, ... + SStream_concat0(O, ".4s"); + return; + break; + case 9: + // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT... + SStream_concat0(O, ".8h"); + return; + break; + case 10: + // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... + SStream_concat0(O, ".8b"); + return; + break; + case 11: + // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... + SStream_concat0(O, ", "); + break; + case 12: + // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSUBHNB_ZZZ_H, SUBHNB_ZZZ_H + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 2, O, 's'); + return; + break; + case 13: + // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... + SStream_concat0(O, ".2d, "); + break; + case 14: + // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... + SStream_concat0(O, ".4s, "); + break; + case 15: + // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BF16DOTlanev8b... + SStream_concat0(O, ".8h, "); + break; + case 16: + // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm... + SStream_concat0(O, "/m, "); + break; + case 17: + // ADDP_ZPmZ_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 2, O, 'h'); + break; + case 18: + // ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL... + SStream_concat0(O, ".16b, "); + break; + case 19: + // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... + SStream_concat0(O, ".2s, "); + break; + case 20: + // ADDPv4i16, ADDv4i16, BF16DOTlanev4bf16, BFDOTv4bf16, CMEQv4i16, CMGEv4... + SStream_concat0(O, ".4h, "); + break; + case 21: + // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... + SStream_concat0(O, ".8b, "); + break; + case 22: + // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 2, O); + return; + break; + case 23: + // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B... + SStream_concat0(O, "/z, "); + break; + case 24: + // ASR_WIDE_ZZZ_H, LSL_WIDE_ZZZ_H, LSR_WIDE_ZZZ_H + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 2, O, 'd'); + return; + break; + case 25: + // ASR_ZZI_H, INDEX_IR_B, INDEX_RR_H, LSL_ZZI_H, LSR_ZZI_H, MUL_ZI_H, RSH... + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 26: + // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... + SStream_concat0(O, ", ["); + break; + case 27: + // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz + SStream_concat0(O, ".16b, #0"); + return; + break; + case 28: + // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz + SStream_concat0(O, ", #0"); + return; + break; + case 29: + // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz + SStream_concat0(O, ".2s, #0"); + return; + break; + case 30: + // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz + SStream_concat0(O, ".2d, #0"); + return; + break; + case 31: + // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz + SStream_concat0(O, ".4h, #0"); + return; + break; + case 32: + // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz + SStream_concat0(O, ".4s, #0"); + return; + break; + case 33: + // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz + SStream_concat0(O, ".8h, #0"); + return; + break; + case 34: + // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz + SStream_concat0(O, ".8b, #0"); + return; + break; + case 35: + // CMLA_ZZZI_H, CMLA_ZZZ_H, EORBT_ZZZ_H, EORTB_ZZZ_H, FADDA_VPZ_H, FCMLA_... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 3, O, 'h'); + break; + case 36: + // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI + SStream_concat0(O, ", mul "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 37: + // CPY_ZPmI_B + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 3, O); + return; + break; + case 38: + // CPY_ZPmI_D + printImm8OptLsl64 /* printImm8OptLsl (+ ) */ (MI, 3, O); + return; + break; + case 39: + // CPY_ZPmI_S + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 3, O); + return; + break; + case 40: + // CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_S... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 41: + // CPY_ZPzI_H + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 2, O); + return; + break; + case 42: + // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... + SStream_concat0(O, ".h"); + break; + case 43: + // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, SMOVvi3... + SStream_concat0(O, ".s"); + break; + case 44: + // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64, UMOVvi64_idx... + SStream_concat0(O, ".d"); + break; + case 45: + // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to32... + SStream_concat0(O, ".b"); + break; + case 46: + // DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + return; + break; + case 47: + // EXTRACT_ZPMXI_H_H, EXTRACT_ZPMXI_H_Q + printMatrixTileVector /* printMatrixTileVector<0> (+ ) */ (MI, 2, O, 0); + SStream_concat0(O, "["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printMatrixIndex /* printMatrixIndex (+ ) */ (MI, 4, O); + SStream_concat0(O, "]"); + return; + break; + case 48: + // EXTRACT_ZPMXI_V_H, EXTRACT_ZPMXI_V_Q + printMatrixTileVector /* printMatrixTileVector<1> (+ ) */ (MI, 2, O, 1); + SStream_concat0(O, "["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printMatrixIndex /* printMatrixIndex (+ ) */ (MI, 4, O); + SStream_concat0(O, "]"); + return; + break; + case 49: + // EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H + printImm /* printImm (+ ) */ (MI, 2, O); + return; + break; + case 50: + // FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p + SStream_concat0(O, ".2h"); + return; + break; + case 51: + // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ... + SStream_concat0(O, ", #0.0"); + return; + break; + case 52: + // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz + SStream_concat0(O, ".2s, #0.0"); + return; + break; + case 53: + // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz + SStream_concat0(O, ".2d, #0.0"); + return; + break; + case 54: + // FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz + SStream_concat0(O, ".4h, #0.0"); + return; + break; + case 55: + // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz + SStream_concat0(O, ".4s, #0.0"); + return; + break; + case 56: + // FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz + SStream_concat0(O, ".8h, #0.0"); + return; + break; + case 57: + // FCPY_ZPmI_D, FCPY_ZPmI_S + printFPImmOperand /* printFPImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 58: + // FMLAL2lanev4f16, FMLAL2v4f16, FMLALlanev4f16, FMLALv4f16, FMLSL2lanev4... + SStream_concat0(O, ".2h, "); + printVRegOperand /* printVRegOperand (+ ) */ (MI, 3, O); + break; + case 59: + // FMOPA_MPPZZ_D, FMOPS_MPPZZ_D, INSERT_MXIPZ_H_D, INSERT_MXIPZ_V_D + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 4, O, 'd'); + return; + break; + case 60: + // FMOPA_MPPZZ_S, FMOPS_MPPZZ_S, INSERT_MXIPZ_H_S, INSERT_MXIPZ_V_S + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 4, O, 's'); + return; + break; + case 61: + // INDEX_II_B + printSImm /* printSImm<8> (+ ) */ (MI, 2, O, 8); + return; + break; + case 62: + // INDEX_RI_H + printSImm /* printSImm<16> (+ ) */ (MI, 2, O, 16); + return; + break; + case 63: + // INSERT_MXIPZ_H_B, INSERT_MXIPZ_V_B + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 4, O, 'b'); + return; + break; + case 64: + // INSERT_MXIPZ_H_H, INSERT_MXIPZ_V_H + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 4, O, 'h'); + return; + break; + case 65: + // INSERT_MXIPZ_H_Q, INSERT_MXIPZ_V_Q + printSVERegOp /* printSVERegOp<'q'> (+ ) */ (MI, 4, O, 'q'); + return; + break; + case 66: + // LD1_MXIPXX_H_B, LD1_MXIPXX_V_B, ST1_MXIPXX_H_B, ST1_MXIPXX_V_B + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) */ + (MI, 5, O, false, 8, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 67: + // LD1_MXIPXX_H_D, LD1_MXIPXX_V_D, ST1_MXIPXX_H_D, ST1_MXIPXX_V_D + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 5, O, false, 64, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 68: + // LD1_MXIPXX_H_H, LD1_MXIPXX_V_H, ST1_MXIPXX_H_H, ST1_MXIPXX_V_H + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 5, O, false, 16, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 69: + // LD1_MXIPXX_H_Q, LD1_MXIPXX_V_Q, ST1_MXIPXX_H_Q, ST1_MXIPXX_V_Q + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 5, O, false, 128, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 70: + // LD1_MXIPXX_H_S, LD1_MXIPXX_V_S, ST1_MXIPXX_H_S, ST1_MXIPXX_V_S + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 5, O, false, 32, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 71: + // LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD... + SStream_concat0(O, "]"); + return; + break; + case 72: + // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... + SStream_concat0(O, "], "); + break; + case 73: + // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... + printShifter /* printShifter (+ ) */ (MI, 2, O); + return; + break; + case 74: + // PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H, SABDLT_ZZZ_H, SADDLBT_ZZZ_H,... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 2, O, 'b'); + return; + break; + case 75: + // PRFB_D_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 8, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 76: + // PRFB_D_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 8, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 77: + // PRFB_D_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 8, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 78: + // PRFB_PRR + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) */ + (MI, 3, O, false, 8, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 79: + // PRFB_S_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 8, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 80: + // PRFB_S_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 8, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 81: + // PRFD_D_PZI, PRFD_S_PZI + printImmScale /* printImmScale<8> (+ ) */ (MI, 3, O, 8); + SStream_concat0(O, "]"); + return; + break; + case 82: + // PRFD_D_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 64, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 83: + // PRFD_D_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 64, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 84: + // PRFD_D_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 64, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 85: + // PRFD_PRR + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 64, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 86: + // PRFD_S_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 64, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 87: + // PRFD_S_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 64, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 88: + // PRFH_D_PZI, PRFH_S_PZI + printImmScale /* printImmScale<2> (+ ) */ (MI, 3, O, 2); + SStream_concat0(O, "]"); + return; + break; + case 89: + // PRFH_D_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 16, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 90: + // PRFH_D_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 16, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 91: + // PRFH_D_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 16, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 92: + // PRFH_PRR + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 16, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 93: + // PRFH_S_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 16, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 94: + // PRFH_S_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 16, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 95: + // PRFS_PRR + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 32, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 96: + // PRFW_D_PZI, PRFW_S_PZI + printImmScale /* printImmScale<4> (+ ) */ (MI, 3, O, 4); + SStream_concat0(O, "]"); + return; + break; + case 97: + // PRFW_D_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 32, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 98: + // PRFW_D_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 32, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 99: + // PRFW_D_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 32, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 100: + // PRFW_S_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 32, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 101: + // PRFW_S_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 32, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 102: + // RDFFRS_PPz, RDFFR_PPz_REAL + SStream_concat0(O, "/z"); + return; + break; + case 103: + // SHLLv16i8 + SStream_concat0(O, ".16b, #8"); + return; + break; + case 104: + // SHLLv2i32 + SStream_concat0(O, ".2s, #32"); + return; + break; + case 105: + // SHLLv4i16 + SStream_concat0(O, ".4h, #16"); + return; + break; + case 106: + // SHLLv4i32 + SStream_concat0(O, ".4s, #32"); + return; + break; + case 107: + // SHLLv8i16 + SStream_concat0(O, ".8h, #16"); + return; + break; + case 108: + // SHLLv8i8 + SStream_concat0(O, ".8b, #8"); + return; + break; + case 109: + // SPLICE_ZPZZ_H + printTypedVectorList /* printTypedVectorList<0,'h'> (+ ) */ (MI, 2, O, 0, + 'h'); + return; + break; + case 110: + // TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, ZIP1_ZZZ_Q, ZIP2_ZZZ_Q + printSVERegOp /* printSVERegOp<'q'> (+ ) */ (MI, 2, O, 'q'); + return; + break; + } + + // Fragment 4 encoded into 7 bits for 94 unique commands. + switch ((Bits >> 41) & 127) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ABS_ZPmZ_B, ADD_ZZZ_H, BDEP_ZZZ_H, BEXT_ZZZ_H, BGRP_ZZZ_H, BRKA_PPmP, ... + return; + break; + case 1: + // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, EORBT_ZZZ_D, EORTB... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 3, O, 'd'); + break; + case 2: + // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, EORBT_ZZZ_S, EORTB_... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 3, O, 's'); + break; + case 3: + // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSXrx64, ADDVL_XXI, ADDXrx6... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 4: + // ADDG, ST2GOffset, STGOffset, STZ2GOffset, STZGOffset, SUBG + printImmScale /* printImmScale<16> (+ ) */ (MI, 2, O, 16); + break; + case 5: + // ADDHNB_ZZZ_B, CNTP_XPP_H, LASTA_RPZ_H, LASTA_VPZ_H, LASTB_RPZ_H, LASTB... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 2, O, 'h'); + break; + case 6: + // ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADD_ZPmZ_D, ADD_ZZZ_D, AND_ZPmZ_D, AND_ZZZ,... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 2, O, 'd'); + break; + case 7: + // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMMLA_B_ZZI, BFMMLA_B_ZZZ, BFMMLA... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 3, O, 'h'); + break; + case 8: + // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... + printVRegOperand /* printVRegOperand (+ ) */ (MI, 2, O); + break; + case 9: + // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BF16DOTlanev4bf1... + printVRegOperand /* printVRegOperand (+ ) */ (MI, 3, O); + break; + case 10: + // ADDP_ZPmZ_B, ADD_ZPmZ_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, ANDS_PPzPP... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 2, O, 'b'); + break; + case 11: + // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... + SStream_concat0(O, ", "); + break; + case 12: + // ADDP_ZPmZ_S, ADD_ZPmZ_S, ADD_ZZZ_S, AND_ZPmZ_S, ASRD_ZPmI_S, ASRR_ZPmZ... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 2, O, 's'); + break; + case 13: + // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri + printAddSubImm /* printAddSubImm (+ ) */ (MI, 2, O); + return; + break; + case 14: + // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... + printShiftedRegister /* printShiftedRegister (+ ) */ (MI, 2, O); + return; + break; + case 15: + // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx + printExtendedRegister /* printExtendedRegister (+ ) */ (MI, 2, O); + return; + break; + case 16: + // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 2, O); + return; + break; + case 17: + // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... + printImm8OptLsl64 /* printImm8OptLsl (+ ) */ (MI, 2, O); + return; + break; + case 18: + // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 2, O); + return; + break; + case 19: + // ADR_LSL_ZZZ_D_0 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 8, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 20: + // ADR_LSL_ZZZ_D_1 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 16, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 21: + // ADR_LSL_ZZZ_D_2 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 32, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 22: + // ADR_LSL_ZZZ_D_3 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 64, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 23: + // ADR_LSL_ZZZ_S_0 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 8, 'x', 's'); + SStream_concat0(O, "]"); + return; + break; + case 24: + // ADR_LSL_ZZZ_S_1 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 16, 'x', 's'); + SStream_concat0(O, "]"); + return; + break; + case 25: + // ADR_LSL_ZZZ_S_2 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 32, 'x', 's'); + SStream_concat0(O, "]"); + return; + break; + case 26: + // ADR_LSL_ZZZ_S_3 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 64, 'x', 's'); + SStream_concat0(O, "]"); + return; + break; + case 27: + // ADR_SXTW_ZZZ_D_0 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, true, 8, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 28: + // ADR_SXTW_ZZZ_D_1 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, true, 16, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 29: + // ADR_SXTW_ZZZ_D_2 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, true, 32, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 30: + // ADR_SXTW_ZZZ_D_3 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, true, 64, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 31: + // ADR_UXTW_ZZZ_D_0 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 8, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 32: + // ADR_UXTW_ZZZ_D_1 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 16, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 33: + // ADR_UXTW_ZZZ_D_2 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 32, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 34: + // ADR_UXTW_ZZZ_D_3 + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 2, O, false, 64, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 35: + // ANDSWri, ANDWri, EORWri, ORRWri + printLogicalImm32 /* printLogicalImm (+ ) */ (MI, 2, O); + return; + break; + case 36: + // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI + printLogicalImm64 /* printLogicalImm (+ ) */ (MI, 2, O); + return; + break; + case 37: + // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 38: + // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FMLA_ZZZI_H, FMLS_ZZZI_H, INSv... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + break; + case 39: + // CPY_ZPzI_B + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 2, O); + return; + break; + case 40: + // CPY_ZPzI_D + printImm8OptLsl64 /* printImm8OptLsl (+ ) */ (MI, 2, O); + return; + break; + case 41: + // CPY_ZPzI_S + printImm8OptLsl32 /* printImm8OptLsl (+ ) */ (MI, 2, O); + return; + break; + case 42: + // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + return; + break; + case 43: + // EXTRACT_ZPMXI_H_B, EXTRACT_ZPMXI_H_D, EXTRACT_ZPMXI_H_S + printMatrixTileVector /* printMatrixTileVector<0> (+ ) */ (MI, 2, O, 0); + SStream_concat0(O, "["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printMatrixIndex /* printMatrixIndex (+ ) */ (MI, 4, O); + SStream_concat0(O, "]"); + return; + break; + case 44: + // EXTRACT_ZPMXI_V_B, EXTRACT_ZPMXI_V_D, EXTRACT_ZPMXI_V_S + printMatrixTileVector /* printMatrixTileVector<1> (+ ) */ (MI, 2, O, 1); + SStream_concat0(O, "["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printMatrixIndex /* printMatrixIndex (+ ) */ (MI, 4, O); + SStream_concat0(O, "]"); + return; + break; + case 45: + // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... + SStream_concat0(O, ", #0.0"); + return; + break; + case 46: + // FMLAL2lanev4f16, FMLALlanev4f16, FMLSL2lanev4f16, FMLSLlanev4f16 + SStream_concat0(O, ".h"); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + return; + break; + case 47: + // FMLAL2v4f16, FMLALv4f16, FMLSL2v4f16, FMLSLv4f16 + SStream_concat0(O, ".2h"); + return; + break; + case 48: + // FMUL_ZZZI_H, MUL_ZZZI_H, SQDMULH_ZZZI_H, SQRDMULH_ZZZI_H + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + return; + break; + case 49: + // GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 8, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 50: + // GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 8, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 51: + // GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 8, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 52: + // GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 8, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 53: + // GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 8, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 54: + // GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, LD1RD_IMM, LDRAAwriteback, LDRABwrit... + printImmScale /* printImmScale<8> (+ ) */ (MI, 3, O, 8); + break; + case 55: + // GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED_SCALED_REAL + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 64, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 56: + // GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 64, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 57: + // GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 64, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 58: + // GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE... + printImmScale /* printImmScale<2> (+ ) */ (MI, 3, O, 2); + break; + case 59: + // GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 16, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 60: + // GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 16, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 61: + // GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 16, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 62: + // GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 16, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 63: + // GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 16, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 64: + // GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE... + printImmScale /* printImmScale<4> (+ ) */ (MI, 3, O, 4); + break; + case 65: + // GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 32, 'x', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 66: + // GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 32, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 67: + // GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 32, 'w', 'd'); + SStream_concat0(O, "]"); + return; + break; + case 68: + // GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, true, 32, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 69: + // GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 32, 'w', 's'); + SStream_concat0(O, "]"); + return; + break; + case 70: + // INDEX_RI_B + printSImm /* printSImm<8> (+ ) */ (MI, 2, O, 8); + return; + break; + case 71: + // LD1B, LD1B_D, LD1B_H, LD1B_S, LD1RO_B, LD1RQ_B, LD1SB_D, LD1SB_H, LD1S... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) */ + (MI, 3, O, false, 8, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 72: + // LD1D, LD1RO_D, LD1RQ_D, LD2D, LD3D, LD4D, LDFF1D_REAL, LDNT1D_ZRR, ST1... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 64, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 73: + // LD1H, LD1H_D, LD1H_S, LD1RO_H, LD1RQ_H, LD1SH_D, LD1SH_S, LD2H, LD3H, ... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 16, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 74: + // LD1RO_B_IMM, LD1RO_D_IMM, LD1RO_H_IMM, LD1RO_W_IMM + printImmScale /* printImmScale<32> (+ ) */ (MI, 3, O, 32); + SStream_concat0(O, "]"); + return; + break; + case 75: + // LD1RO_W, LD1RQ_W, LD1SW_D, LD1W, LD1W_D, LD2W, LD3W, LD4W, LDFF1SW_D_R... + printRegWithShiftExtend /* printRegWithShiftExtend (+ ) + */ + (MI, 3, O, false, 32, 'x', 0); + SStream_concat0(O, "]"); + return; + break; + case 76: + // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM, LDG, ST2GPostIndex... + printImmScale /* printImmScale<16> (+ ) */ (MI, 3, O, 16); + break; + case 77: + // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ST3H_IMM, ... + printImmScale /* printImmScale<3> (+ ) */ (MI, 3, O, 3); + SStream_concat0(O, ", mul vl]"); + return; + break; + case 78: + // LDRAAindexed, LDRABindexed + printImmScale /* printImmScale<8> (+ ) */ (MI, 2, O, 8); + SStream_concat0(O, "]"); + return; + break; + case 79: + // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui + printUImm12Offset /* printUImm12Offset<1> (+ ) */ (MI, 2, O, 1); + SStream_concat0(O, "]"); + return; + break; + case 80: + // LDRDui, LDRXui, PRFMui, STRDui, STRXui + printUImm12Offset /* printUImm12Offset<8> (+ ) */ (MI, 2, O, 8); + SStream_concat0(O, "]"); + return; + break; + case 81: + // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui + printUImm12Offset /* printUImm12Offset<2> (+ ) */ (MI, 2, O, 2); + SStream_concat0(O, "]"); + return; + break; + case 82: + // LDRQui, STRQui + printUImm12Offset /* printUImm12Offset<16> (+ ) */ (MI, 2, O, 16); + SStream_concat0(O, "]"); + return; + break; + case 83: + // LDRSWui, LDRSui, LDRWui, STRSui, STRWui + printUImm12Offset /* printUImm12Offset<4> (+ ) */ (MI, 2, O, 4); + SStream_concat0(O, "]"); + return; + break; + case 84: + // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 3, O, 'b'); + SStream_concat0(O, ", "); + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 4, O, 'b'); + return; + break; + case 85: + // PRFB_D_PZI, PRFB_S_PZI + SStream_concat0(O, "]"); + return; + break; + case 86: + // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI + SStream_concat0(O, ", mul vl]"); + return; + break; + case 87: + // SPLICE_ZPZZ_B + printTypedVectorList /* printTypedVectorList<0,'b'> (+ ) */ (MI, 2, O, 0, + 'b'); + return; + break; + case 88: + // SPLICE_ZPZZ_D + printTypedVectorList /* printTypedVectorList<0,'d'> (+ ) */ (MI, 2, O, 0, + 'd'); + return; + break; + case 89: + // SPLICE_ZPZZ_S + printTypedVectorList /* printTypedVectorList<0,'s'> (+ ) */ (MI, 2, O, 0, + 's'); + return; + break; + case 90: + // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... + printGPR64as32 /* printGPR64as32 (+ ) */ (MI, 2, O); + return; + break; + case 91: + // SYSLxt + printSysCROperand /* printSysCROperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printSysCROperand /* printSysCROperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + return; + break; + case 92: + // TBNZW, TBNZX, TBZW, TBZX + printAlignedLabel /* printAlignedLabel (+ ) */ (MI, 2, O); + return; + break; + case 93: + // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S + printImm /* printImm (+ ) */ (MI, 2, O); + return; + break; + } + + // Fragment 5 encoded into 6 bits for 41 unique commands. + switch ((Bits >> 48) & 63) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... + return; + break; + case 1: + // ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, A... + SStream_concat0(O, ", "); + break; + case 2: + // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... + SStream_concat0(O, ".2d"); + return; + break; + case 3: + // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... + SStream_concat0(O, ".4s"); + return; + break; + case 4: + // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, BFDOTv8bf16, B... + SStream_concat0(O, ".8h"); + return; + break; + case 5: + // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 3, O, 'h'); + break; + case 6: + // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... + SStream_concat0(O, ".16b"); + return; + break; + case 7: + // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... + SStream_concat0(O, ".2s"); + return; + break; + case 8: + // ADDPv4i16, ADDv4i16, BFDOTv4bf16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMH... + SStream_concat0(O, ".4h"); + return; + break; + case 9: + // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... + SStream_concat0(O, ".8b"); + return; + break; + case 10: + // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 + printArithExtend /* printArithExtend (+ ) */ (MI, 3, O); + return; + break; + case 11: + // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 12: + // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 3, O, 'd'); + return; + break; + case 13: + // BCAX, EOR3, EXTv16i8 + SStream_concat0(O, ".16b, "); + break; + case 14: + // BF16DOTlanev4bf16, BF16DOTlanev8bf16 + SStream_concat0(O, ".2h"); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + return; + break; + case 15: + // BFDOT_ZZI, BFMMLA_B_ZZI, BFMMLA_T_ZZI, CDOT_ZZZI_D, CMLA_ZZZI_S, FCMLA... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + break; + case 16: + // BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAL2... + SStream_concat0(O, ".h"); + break; + case 17: + // CADD_ZZI_H, SQCADD_ZZI_H + printComplexRotationOp /* printComplexRotationOp<180, 90> (+ ) */ (MI, 3, O, + 180, 90); + return; + break; + case 18: + // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... + SStream_concat0(O, "]"); + return; + break; + case 19: + // CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H + printComplexRotationOp /* printComplexRotationOp<90, 0> (+ ) */ (MI, 4, O, + 90, 0); + return; + break; + case 20: + // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H + printImm /* printImm (+ ) */ (MI, 3, O); + return; + break; + case 21: + // EXTv8i8 + SStream_concat0(O, ".8b, "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 22: + // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H + printExactFPImm /* printExactFPImm (+ ) */ + (MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_one); + return; + break; + case 23: + // FCADDv2f32, FCMLAv2f32 + SStream_concat0(O, ".2s, "); + break; + case 24: + // FCADDv2f64, FCMLAv2f64, XAR + SStream_concat0(O, ".2d, "); + break; + case 25: + // FCADDv4f16, FCMLAv4f16 + SStream_concat0(O, ".4h, "); + break; + case 26: + // FCADDv4f32, FCMLAv4f32, SM3SS1 + SStream_concat0(O, ".4s, "); + break; + case 27: + // FCADDv8f16, FCMLAv8f16 + SStream_concat0(O, ".8h, "); + break; + case 28: + // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... + SStream_concat0(O, ", #0.0"); + return; + break; + case 29: + // FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, FMLS_ZPmZZ_H, FMSB_ZPmZZ_H,... + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 4, O, 'h'); + break; + case 30: + // FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in... + SStream_concat0(O, ".s"); + break; + case 31: + // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H + printExactFPImm /* printExactFPImm (+ ) */ + (MI, 3, O, AArch64ExactFPImm_zero, AArch64ExactFPImm_one); + return; + break; + case 32: + // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... + SStream_concat0(O, ".d"); + break; + case 33: + // FMUL_ZPmI_H + printExactFPImm /* printExactFPImm (+ ) */ + (MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_two); + return; + break; + case 34: + // FMUL_ZZZI_D, FMUL_ZZZI_S, MUL_ZZZI_D, MUL_ZZZI_S, SMULLB_ZZZI_D, SMULL... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + return; + break; + case 35: + // LD1B_D_IMM_REAL, LD1B_H_IMM_REAL, LD1B_IMM_REAL, LD1B_S_IMM_REAL, LD1D... + SStream_concat0(O, ", mul vl]"); + return; + break; + case 36: + // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STGPpost,... + SStream_concat0(O, "], "); + break; + case 37: + // LDRAAwriteback, LDRABwriteback, LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, ... + SStream_concat0(O, "]!"); + return; + break; + case 38: + // PSEL_PPPRI_B, PSEL_PPPRI_D, PSEL_PPPRI_H, PSEL_PPPRI_S + SStream_concat0(O, "["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printMatrixIndex /* printMatrixIndex (+ ) */ (MI, 4, O); + SStream_concat0(O, "]"); + return; + break; + case 39: + // SDOTlanev16i8, SDOTlanev8i8, SUDOTlanev16i8, SUDOTlanev8i8, UDOTlanev1... + SStream_concat0(O, ".4b"); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + return; + break; + case 40: + // STLXPW, STLXPX, STXPW, STXPX + SStream_concat0(O, ", ["); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "]"); + return; + break; + } + + // Fragment 6 encoded into 6 bits for 37 unique commands. + switch ((Bits >> 54) & 63) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A... + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 1: + // ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_... + printSVERegOp /* printSVERegOp<'b'> (+ ) */ (MI, 3, O, 'b'); + return; + break; + case 2: + // ADDP_ZPmZ_D, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 3, O, 'd'); + break; + case 3: + // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BFDOT_ZZ... + return; + break; + case 4: + // ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 3, O, 's'); + break; + case 5: + // BCAX, EOR3, SM3SS1 + printVRegOperand /* printVRegOperand (+ ) */ (MI, 3, O); + break; + case 6: + // BFMLALBIdx, BFMLALTIdx, FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + break; + case 7: + // BFMWri, BFMXri + printOperand /* printOperand (+ ) */ (MI, 4, O); + return; + break; + case 8: + // CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16... + printComplexRotationOp /* printComplexRotationOp<180, 90> (+ ) */ (MI, 3, O, + 180, 90); + return; + break; + case 9: + // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... + printCondCode /* printCondCode (+ ) */ (MI, 3, O); + return; + break; + case 10: + // CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, S... + SStream_concat0(O, ", "); + break; + case 11: + // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H + printComplexRotationOp /* printComplexRotationOp<90, 0> (+ ) */ (MI, 5, O, + 90, 0); + return; + break; + case 12: + // CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16... + printComplexRotationOp /* printComplexRotationOp<90, 0> (+ ) */ (MI, 4, O, + 90, 0); + return; + break; + case 13: + // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H + printSVERegOp /* printSVERegOp<'h'> (+ ) */ (MI, 3, O, 'h'); + return; + break; + case 14: + // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... + printImm /* printImm (+ ) */ (MI, 3, O); + return; + break; + case 15: + // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... + printExactFPImm /* printExactFPImm (+ ) */ + (MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_one); + return; + break; + case 16: + // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... + printSVERegOp /* printSVERegOp<'d'> (+ ) */ (MI, 4, O, 'd'); + break; + case 17: + // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... + printSVERegOp /* printSVERegOp<'s'> (+ ) */ (MI, 4, O, 's'); + break; + case 18: + // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... + printExactFPImm /* printExactFPImm (+ ) */ + (MI, 3, O, AArch64ExactFPImm_zero, AArch64ExactFPImm_one); + return; + break; + case 19: + // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + return; + break; + case 20: + // FMUL_ZPmI_D, FMUL_ZPmI_S + printExactFPImm /* printExactFPImm (+ ) */ + (MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_two); + return; + break; + case 21: + // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi + printImmScale /* printImmScale<8> (+ ) */ (MI, 3, O, 8); + SStream_concat0(O, "]"); + return; + break; + case 22: + // LDNPQi, LDPQi, STGPi, STNPQi, STPQi + printImmScale /* printImmScale<16> (+ ) */ (MI, 3, O, 16); + SStream_concat0(O, "]"); + return; + break; + case 23: + // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi + printImmScale /* printImmScale<4> (+ ) */ (MI, 3, O, 4); + SStream_concat0(O, "]"); + return; + break; + case 24: + // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... + printImmScale /* printImmScale<8> (+ ) */ (MI, 4, O, 8); + break; + case 25: + // LDPQpost, LDPQpre, STGPpost, STGPpre, STPQpost, STPQpre + printImmScale /* printImmScale<16> (+ ) */ (MI, 4, O, 16); + break; + case 26: + // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... + printImmScale /* printImmScale<4> (+ ) */ (MI, 4, O, 4); + break; + case 27: + // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW + printMemExtend /* printMemExtend<'w', 8> (+ ) */ (MI, 3, O, 'w', 8); + SStream_concat0(O, "]"); + return; + break; + case 28: + // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX + printMemExtend /* printMemExtend<'x', 8> (+ ) */ (MI, 3, O, 'x', 8); + SStream_concat0(O, "]"); + return; + break; + case 29: + // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW + printMemExtend /* printMemExtend<'w', 64> (+ ) */ (MI, 3, O, 'w', 64); + SStream_concat0(O, "]"); + return; + break; + case 30: + // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX + printMemExtend /* printMemExtend<'x', 64> (+ ) */ (MI, 3, O, 'x', 64); + SStream_concat0(O, "]"); + return; + break; + case 31: + // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW + printMemExtend /* printMemExtend<'w', 16> (+ ) */ (MI, 3, O, 'w', 16); + SStream_concat0(O, "]"); + return; + break; + case 32: + // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX + printMemExtend /* printMemExtend<'x', 16> (+ ) */ (MI, 3, O, 'x', 16); + SStream_concat0(O, "]"); + return; + break; + case 33: + // LDRQroW, STRQroW + printMemExtend /* printMemExtend<'w', 128> (+ ) */ (MI, 3, O, 'w', 128); + SStream_concat0(O, "]"); + return; + break; + case 34: + // LDRQroX, STRQroX + printMemExtend /* printMemExtend<'x', 128> (+ ) */ (MI, 3, O, 'x', 128); + SStream_concat0(O, "]"); + return; + break; + case 35: + // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW + printMemExtend /* printMemExtend<'w', 32> (+ ) */ (MI, 3, O, 'w', 32); + SStream_concat0(O, "]"); + return; + break; + case 36: + // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX + printMemExtend /* printMemExtend<'x', 32> (+ ) */ (MI, 3, O, 'x', 32); + SStream_concat0(O, "]"); + return; + break; + } + + // Fragment 7 encoded into 3 bits for 7 unique commands. + switch ((Bits >> 60) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_D, ADD_ZPmZ_S, AND_ZPmZ_D, AND_ZPmZ... + return; + break; + case 1: + // BCAX, EOR3 + SStream_concat0(O, ".16b"); + return; + break; + case 2: + // CDOT_ZZZI_D, CMLA_ZZZI_S, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, SQRDCMLAH_ZZZI_... + printComplexRotationOp /* printComplexRotationOp<90, 0> (+ ) */ (MI, 5, O, + 90, 0); + return; + break; + case 3: + // FCADD_ZPmZ_D, FCADD_ZPmZ_S, FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_i... + SStream_concat0(O, ", "); + break; + case 4: + // FCADD_ZPmZ_H + printComplexRotationOp /* printComplexRotationOp<180, 90> (+ ) */ (MI, 4, O, + 180, 90); + return; + break; + case 5: + // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STGPpre, STPDpr... + SStream_concat0(O, "]!"); + return; + break; + case 6: + // SM3SS1 + SStream_concat0(O, ".4s"); + return; + break; + } + + // Fragment 8 encoded into 1 bits for 2 unique commands. + if ((Bits >> 63) & 1) { + // FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_indexed, FCMLAv4f32_indexed, ... + printComplexRotationOp /* printComplexRotationOp<90, 0> (+ ) */ (MI, 5, O, + 90, 0); + return; + } else { + // FCADD_ZPmZ_D, FCADD_ZPmZ_S + printComplexRotationOp /* printComplexRotationOp<180, 90> (+ ) */ (MI, 4, O, + 180, 90); + return; + } +} + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo, unsigned AltIdx) { + assert(RegNo && RegNo < 674 && "Invalid register number!"); + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrsNoRegAltName[] = { + /* 0 */ "D7_D8_D9_D10\0" + /* 13 */ "Q7_Q8_Q9_Q10\0" + /* 26 */ "Z7_Z8_Z9_Z10\0" + /* 39 */ "b10\0" + /* 43 */ "d10\0" + /* 47 */ "h10\0" + /* 51 */ "p10\0" + /* 55 */ "q10\0" + /* 59 */ "s10\0" + /* 63 */ "w10\0" + /* 67 */ "x10\0" + /* 71 */ "z10\0" + /* 75 */ "D17_D18_D19_D20\0" + /* 91 */ "Q17_Q18_Q19_Q20\0" + /* 107 */ "Z17_Z18_Z19_Z20\0" + /* 123 */ "b20\0" + /* 127 */ "d20\0" + /* 131 */ "h20\0" + /* 135 */ "q20\0" + /* 139 */ "s20\0" + /* 143 */ "w20\0" + /* 147 */ "x20\0" + /* 151 */ "z20\0" + /* 155 */ "D27_D28_D29_D30\0" + /* 171 */ "Q27_Q28_Q29_Q30\0" + /* 187 */ "Z27_Z28_Z29_Z30\0" + /* 203 */ "b30\0" + /* 207 */ "d30\0" + /* 211 */ "h30\0" + /* 215 */ "q30\0" + /* 219 */ "s30\0" + /* 223 */ "w30\0" + /* 227 */ "x30\0" + /* 231 */ "z30\0" + /* 235 */ "D29_D30_D31_D0\0" + /* 250 */ "Q29_Q30_Q31_Q0\0" + /* 265 */ "Z29_Z30_Z31_Z0\0" + /* 280 */ "b0\0" + /* 283 */ "d0\0" + /* 286 */ "h0\0" + /* 289 */ "p0\0" + /* 292 */ "q0\0" + /* 295 */ "s0\0" + /* 298 */ "w0\0" + /* 301 */ "x0\0" + /* 304 */ "z0\0" + /* 307 */ "D8_D9_D10_D11\0" + /* 321 */ "Q8_Q9_Q10_Q11\0" + /* 335 */ "W10_W11\0" + /* 343 */ "X4_X5_X6_X7_X8_X9_X10_X11\0" + /* 369 */ "Z8_Z9_Z10_Z11\0" + /* 383 */ "b11\0" + /* 387 */ "d11\0" + /* 391 */ "h11\0" + /* 395 */ "p11\0" + /* 399 */ "q11\0" + /* 403 */ "s11\0" + /* 407 */ "w11\0" + /* 411 */ "x11\0" + /* 415 */ "z11\0" + /* 419 */ "D18_D19_D20_D21\0" + /* 435 */ "Q18_Q19_Q20_Q21\0" + /* 451 */ "W20_W21\0" + /* 459 */ "X14_X15_X16_X17_X18_X19_X20_X21\0" + /* 491 */ "Z18_Z19_Z20_Z21\0" + /* 507 */ "b21\0" + /* 511 */ "d21\0" + /* 515 */ "h21\0" + /* 519 */ "q21\0" + /* 523 */ "s21\0" + /* 527 */ "w21\0" + /* 531 */ "x21\0" + /* 535 */ "z21\0" + /* 539 */ "D28_D29_D30_D31\0" + /* 555 */ "Q28_Q29_Q30_Q31\0" + /* 571 */ "Z28_Z29_Z30_Z31\0" + /* 587 */ "b31\0" + /* 591 */ "d31\0" + /* 595 */ "h31\0" + /* 599 */ "q31\0" + /* 603 */ "s31\0" + /* 607 */ "z31\0" + /* 611 */ "D30_D31_D0_D1\0" + /* 625 */ "Q30_Q31_Q0_Q1\0" + /* 639 */ "W0_W1\0" + /* 645 */ "X0_X1\0" + /* 651 */ "Z30_Z31_Z0_Z1\0" + /* 665 */ "b1\0" + /* 668 */ "d1\0" + /* 671 */ "h1\0" + /* 674 */ "p1\0" + /* 677 */ "q1\0" + /* 680 */ "s1\0" + /* 683 */ "w1\0" + /* 686 */ "x1\0" + /* 689 */ "z1\0" + /* 692 */ "D9_D10_D11_D12\0" + /* 707 */ "Q9_Q10_Q11_Q12\0" + /* 722 */ "Z9_Z10_Z11_Z12\0" + /* 737 */ "b12\0" + /* 741 */ "d12\0" + /* 745 */ "h12\0" + /* 749 */ "p12\0" + /* 753 */ "q12\0" + /* 757 */ "s12\0" + /* 761 */ "w12\0" + /* 765 */ "x12\0" + /* 769 */ "z12\0" + /* 773 */ "D19_D20_D21_D22\0" + /* 789 */ "Q19_Q20_Q21_Q22\0" + /* 805 */ "Z19_Z20_Z21_Z22\0" + /* 821 */ "b22\0" + /* 825 */ "d22\0" + /* 829 */ "h22\0" + /* 833 */ "q22\0" + /* 837 */ "s22\0" + /* 841 */ "w22\0" + /* 845 */ "x22\0" + /* 849 */ "z22\0" + /* 853 */ "D31_D0_D1_D2\0" + /* 866 */ "Q31_Q0_Q1_Q2\0" + /* 879 */ "Z31_Z0_Z1_Z2\0" + /* 892 */ "b2\0" + /* 895 */ "d2\0" + /* 898 */ "h2\0" + /* 901 */ "p2\0" + /* 904 */ "q2\0" + /* 907 */ "s2\0" + /* 910 */ "w2\0" + /* 913 */ "x2\0" + /* 916 */ "z2\0" + /* 919 */ "D10_D11_D12_D13\0" + /* 935 */ "Q10_Q11_Q12_Q13\0" + /* 951 */ "W12_W13\0" + /* 959 */ "X6_X7_X8_X9_X10_X11_X12_X13\0" + /* 987 */ "Z10_Z11_Z12_Z13\0" + /* 1003 */ "b13\0" + /* 1007 */ "d13\0" + /* 1011 */ "h13\0" + /* 1015 */ "p13\0" + /* 1019 */ "q13\0" + /* 1023 */ "s13\0" + /* 1027 */ "w13\0" + /* 1031 */ "x13\0" + /* 1035 */ "z13\0" + /* 1039 */ "D20_D21_D22_D23\0" + /* 1055 */ "Q20_Q21_Q22_Q23\0" + /* 1071 */ "W22_W23\0" + /* 1079 */ "X16_X17_X18_X19_X20_X21_X22_X23\0" + /* 1111 */ "Z20_Z21_Z22_Z23\0" + /* 1127 */ "b23\0" + /* 1131 */ "d23\0" + /* 1135 */ "h23\0" + /* 1139 */ "q23\0" + /* 1143 */ "s23\0" + /* 1147 */ "w23\0" + /* 1151 */ "x23\0" + /* 1155 */ "z23\0" + /* 1159 */ "D0_D1_D2_D3\0" + /* 1171 */ "Q0_Q1_Q2_Q3\0" + /* 1183 */ "W2_W3\0" + /* 1189 */ "X2_X3\0" + /* 1195 */ "Z0_Z1_Z2_Z3\0" + /* 1207 */ "b3\0" + /* 1210 */ "d3\0" + /* 1213 */ "h3\0" + /* 1216 */ "p3\0" + /* 1219 */ "q3\0" + /* 1222 */ "s3\0" + /* 1225 */ "w3\0" + /* 1228 */ "x3\0" + /* 1231 */ "z3\0" + /* 1234 */ "D11_D12_D13_D14\0" + /* 1250 */ "Q11_Q12_Q13_Q14\0" + /* 1266 */ "Z11_Z12_Z13_Z14\0" + /* 1282 */ "b14\0" + /* 1286 */ "d14\0" + /* 1290 */ "h14\0" + /* 1294 */ "p14\0" + /* 1298 */ "q14\0" + /* 1302 */ "s14\0" + /* 1306 */ "w14\0" + /* 1310 */ "x14\0" + /* 1314 */ "z14\0" + /* 1318 */ "D21_D22_D23_D24\0" + /* 1334 */ "Q21_Q22_Q23_Q24\0" + /* 1350 */ "Z21_Z22_Z23_Z24\0" + /* 1366 */ "b24\0" + /* 1370 */ "d24\0" + /* 1374 */ "h24\0" + /* 1378 */ "q24\0" + /* 1382 */ "s24\0" + /* 1386 */ "w24\0" + /* 1390 */ "x24\0" + /* 1394 */ "z24\0" + /* 1398 */ "D1_D2_D3_D4\0" + /* 1410 */ "Q1_Q2_Q3_Q4\0" + /* 1422 */ "Z1_Z2_Z3_Z4\0" + /* 1434 */ "b4\0" + /* 1437 */ "d4\0" + /* 1440 */ "h4\0" + /* 1443 */ "p4\0" + /* 1446 */ "q4\0" + /* 1449 */ "s4\0" + /* 1452 */ "w4\0" + /* 1455 */ "x4\0" + /* 1458 */ "z4\0" + /* 1461 */ "D12_D13_D14_D15\0" + /* 1477 */ "Q12_Q13_Q14_Q15\0" + /* 1493 */ "W14_W15\0" + /* 1501 */ "X8_X9_X10_X11_X12_X13_X14_X15\0" + /* 1531 */ "Z12_Z13_Z14_Z15\0" + /* 1547 */ "b15\0" + /* 1551 */ "d15\0" + /* 1555 */ "h15\0" + /* 1559 */ "p15\0" + /* 1563 */ "q15\0" + /* 1567 */ "s15\0" + /* 1571 */ "w15\0" + /* 1575 */ "x15\0" + /* 1579 */ "z15\0" + /* 1583 */ "D22_D23_D24_D25\0" + /* 1599 */ "Q22_Q23_Q24_Q25\0" + /* 1615 */ "W24_W25\0" + /* 1623 */ "X18_X19_X20_X21_X22_X23_X24_X25\0" + /* 1655 */ "Z22_Z23_Z24_Z25\0" + /* 1671 */ "b25\0" + /* 1675 */ "d25\0" + /* 1679 */ "h25\0" + /* 1683 */ "q25\0" + /* 1687 */ "s25\0" + /* 1691 */ "w25\0" + /* 1695 */ "x25\0" + /* 1699 */ "z25\0" + /* 1703 */ "D2_D3_D4_D5\0" + /* 1715 */ "Q2_Q3_Q4_Q5\0" + /* 1727 */ "W4_W5\0" + /* 1733 */ "X4_X5\0" + /* 1739 */ "Z2_Z3_Z4_Z5\0" + /* 1751 */ "b5\0" + /* 1754 */ "d5\0" + /* 1757 */ "h5\0" + /* 1760 */ "p5\0" + /* 1763 */ "q5\0" + /* 1766 */ "s5\0" + /* 1769 */ "w5\0" + /* 1772 */ "x5\0" + /* 1775 */ "z5\0" + /* 1778 */ "D13_D14_D15_D16\0" + /* 1794 */ "Q13_Q14_Q15_Q16\0" + /* 1810 */ "Z13_Z14_Z15_Z16\0" + /* 1826 */ "b16\0" + /* 1830 */ "d16\0" + /* 1834 */ "h16\0" + /* 1838 */ "q16\0" + /* 1842 */ "s16\0" + /* 1846 */ "w16\0" + /* 1850 */ "x16\0" + /* 1854 */ "z16\0" + /* 1858 */ "D23_D24_D25_D26\0" + /* 1874 */ "Q23_Q24_Q25_Q26\0" + /* 1890 */ "Z23_Z24_Z25_Z26\0" + /* 1906 */ "b26\0" + /* 1910 */ "d26\0" + /* 1914 */ "h26\0" + /* 1918 */ "q26\0" + /* 1922 */ "s26\0" + /* 1926 */ "w26\0" + /* 1930 */ "x26\0" + /* 1934 */ "z26\0" + /* 1938 */ "D3_D4_D5_D6\0" + /* 1950 */ "Q3_Q4_Q5_Q6\0" + /* 1962 */ "Z3_Z4_Z5_Z6\0" + /* 1974 */ "b6\0" + /* 1977 */ "d6\0" + /* 1980 */ "h6\0" + /* 1983 */ "p6\0" + /* 1986 */ "q6\0" + /* 1989 */ "s6\0" + /* 1992 */ "w6\0" + /* 1995 */ "x6\0" + /* 1998 */ "z6\0" + /* 2001 */ "D14_D15_D16_D17\0" + /* 2017 */ "Q14_Q15_Q16_Q17\0" + /* 2033 */ "W16_W17\0" + /* 2041 */ "X10_X11_X12_X13_X14_X15_X16_X17\0" + /* 2073 */ "Z14_Z15_Z16_Z17\0" + /* 2089 */ "b17\0" + /* 2093 */ "d17\0" + /* 2097 */ "h17\0" + /* 2101 */ "q17\0" + /* 2105 */ "s17\0" + /* 2109 */ "w17\0" + /* 2113 */ "x17\0" + /* 2117 */ "z17\0" + /* 2121 */ "D24_D25_D26_D27\0" + /* 2137 */ "Q24_Q25_Q26_Q27\0" + /* 2153 */ "W26_W27\0" + /* 2161 */ "X20_X21_X22_X23_X24_X25_X26_X27\0" + /* 2193 */ "Z24_Z25_Z26_Z27\0" + /* 2209 */ "b27\0" + /* 2213 */ "d27\0" + /* 2217 */ "h27\0" + /* 2221 */ "q27\0" + /* 2225 */ "s27\0" + /* 2229 */ "w27\0" + /* 2233 */ "x27\0" + /* 2237 */ "z27\0" + /* 2241 */ "D4_D5_D6_D7\0" + /* 2253 */ "Q4_Q5_Q6_Q7\0" + /* 2265 */ "W6_W7\0" + /* 2271 */ "X0_X1_X2_X3_X4_X5_X6_X7\0" + /* 2295 */ "Z4_Z5_Z6_Z7\0" + /* 2307 */ "b7\0" + /* 2310 */ "d7\0" + /* 2313 */ "h7\0" + /* 2316 */ "p7\0" + /* 2319 */ "q7\0" + /* 2322 */ "s7\0" + /* 2325 */ "w7\0" + /* 2328 */ "x7\0" + /* 2331 */ "z7\0" + /* 2334 */ "D15_D16_D17_D18\0" + /* 2350 */ "Q15_Q16_Q17_Q18\0" + /* 2366 */ "Z15_Z16_Z17_Z18\0" + /* 2382 */ "b18\0" + /* 2386 */ "d18\0" + /* 2390 */ "h18\0" + /* 2394 */ "q18\0" + /* 2398 */ "s18\0" + /* 2402 */ "w18\0" + /* 2406 */ "x18\0" + /* 2410 */ "z18\0" + /* 2414 */ "D25_D26_D27_D28\0" + /* 2430 */ "Q25_Q26_Q27_Q28\0" + /* 2446 */ "Z25_Z26_Z27_Z28\0" + /* 2462 */ "b28\0" + /* 2466 */ "d28\0" + /* 2470 */ "h28\0" + /* 2474 */ "q28\0" + /* 2478 */ "s28\0" + /* 2482 */ "w28\0" + /* 2486 */ "x28\0" + /* 2490 */ "z28\0" + /* 2494 */ "D5_D6_D7_D8\0" + /* 2506 */ "Q5_Q6_Q7_Q8\0" + /* 2518 */ "Z5_Z6_Z7_Z8\0" + /* 2530 */ "b8\0" + /* 2533 */ "d8\0" + /* 2536 */ "h8\0" + /* 2539 */ "p8\0" + /* 2542 */ "q8\0" + /* 2545 */ "s8\0" + /* 2548 */ "w8\0" + /* 2551 */ "x8\0" + /* 2554 */ "z8\0" + /* 2557 */ "D16_D17_D18_D19\0" + /* 2573 */ "Q16_Q17_Q18_Q19\0" + /* 2589 */ "W18_W19\0" + /* 2597 */ "X12_X13_X14_X15_X16_X17_X18_X19\0" + /* 2629 */ "Z16_Z17_Z18_Z19\0" + /* 2645 */ "b19\0" + /* 2649 */ "d19\0" + /* 2653 */ "h19\0" + /* 2657 */ "q19\0" + /* 2661 */ "s19\0" + /* 2665 */ "w19\0" + /* 2669 */ "x19\0" + /* 2673 */ "z19\0" + /* 2677 */ "D26_D27_D28_D29\0" + /* 2693 */ "Q26_Q27_Q28_Q29\0" + /* 2709 */ "W28_W29\0" + /* 2717 */ "Z26_Z27_Z28_Z29\0" + /* 2733 */ "b29\0" + /* 2737 */ "d29\0" + /* 2741 */ "h29\0" + /* 2745 */ "q29\0" + /* 2749 */ "s29\0" + /* 2753 */ "w29\0" + /* 2757 */ "x29\0" + /* 2761 */ "z29\0" + /* 2765 */ "D6_D7_D8_D9\0" + /* 2777 */ "Q6_Q7_Q8_Q9\0" + /* 2789 */ "W8_W9\0" + /* 2795 */ "X2_X3_X4_X5_X6_X7_X8_X9\0" + /* 2819 */ "Z6_Z7_Z8_Z9\0" + /* 2831 */ "b9\0" + /* 2834 */ "d9\0" + /* 2837 */ "h9\0" + /* 2840 */ "p9\0" + /* 2843 */ "q9\0" + /* 2846 */ "s9\0" + /* 2849 */ "w9\0" + /* 2852 */ "x9\0" + /* 2855 */ "z9\0" + /* 2858 */ "X22_X23_X24_X25_X26_X27_X28_FP\0" + /* 2889 */ "W30_WZR\0" + /* 2897 */ "LR_XZR\0" + /* 2904 */ "za\0" + /* 2907 */ "za0.b\0" + /* 2913 */ "za0.d\0" + /* 2919 */ "za1.d\0" + /* 2925 */ "za2.d\0" + /* 2931 */ "za3.d\0" + /* 2937 */ "za4.d\0" + /* 2943 */ "za5.d\0" + /* 2949 */ "za6.d\0" + /* 2955 */ "za7.d\0" + /* 2961 */ "vg\0" + /* 2964 */ "za0.h\0" + /* 2970 */ "za1.h\0" + /* 2976 */ "z10_hi\0" + /* 2983 */ "z20_hi\0" + /* 2990 */ "z30_hi\0" + /* 2997 */ "z0_hi\0" + /* 3003 */ "z11_hi\0" + /* 3010 */ "z21_hi\0" + /* 3017 */ "z31_hi\0" + /* 3024 */ "z1_hi\0" + /* 3030 */ "z12_hi\0" + /* 3037 */ "z22_hi\0" + /* 3044 */ "z2_hi\0" + /* 3050 */ "z13_hi\0" + /* 3057 */ "z23_hi\0" + /* 3064 */ "z3_hi\0" + /* 3070 */ "z14_hi\0" + /* 3077 */ "z24_hi\0" + /* 3084 */ "z4_hi\0" + /* 3090 */ "z15_hi\0" + /* 3097 */ "z25_hi\0" + /* 3104 */ "z5_hi\0" + /* 3110 */ "z16_hi\0" + /* 3117 */ "z26_hi\0" + /* 3124 */ "z6_hi\0" + /* 3130 */ "z17_hi\0" + /* 3137 */ "z27_hi\0" + /* 3144 */ "z7_hi\0" + /* 3150 */ "z18_hi\0" + /* 3157 */ "z28_hi\0" + /* 3164 */ "z8_hi\0" + /* 3170 */ "z19_hi\0" + /* 3177 */ "z29_hi\0" + /* 3184 */ "z9_hi\0" + /* 3190 */ "wsp\0" + /* 3194 */ "za10.q\0" + /* 3201 */ "za0.q\0" + /* 3207 */ "za11.q\0" + /* 3214 */ "za1.q\0" + /* 3220 */ "za12.q\0" + /* 3227 */ "za2.q\0" + /* 3233 */ "za13.q\0" + /* 3240 */ "za3.q\0" + /* 3246 */ "za14.q\0" + /* 3253 */ "za4.q\0" + /* 3259 */ "za15.q\0" + /* 3266 */ "za5.q\0" + /* 3272 */ "za6.q\0" + /* 3278 */ "za7.q\0" + /* 3284 */ "za8.q\0" + /* 3290 */ "za9.q\0" + /* 3296 */ "ffr\0" + /* 3300 */ "wzr\0" + /* 3304 */ "xzr\0" + /* 3308 */ "za0.s\0" + /* 3314 */ "za1.s\0" + /* 3320 */ "za2.s\0" + /* 3326 */ "za3.s\0" + /* 3332 */ "nzcv\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint16_t RegAsmOffsetNoRegAltName[] = { + 3296, 2757, 227, 3332, 3191, 2961, 3190, 3300, 3304, 2904, 280, 665, + 892, 1207, 1434, 1751, 1974, 2307, 2530, 2831, 39, 383, 737, 1003, + 1282, 1547, 1826, 2089, 2382, 2645, 123, 507, 821, 1127, 1366, 1671, + 1906, 2209, 2462, 2733, 203, 587, 283, 668, 895, 1210, 1437, 1754, + 1977, 2310, 2533, 2834, 43, 387, 741, 1007, 1286, 1551, 1830, 2093, + 2386, 2649, 127, 511, 825, 1131, 1370, 1675, 1910, 2213, 2466, 2737, + 207, 591, 286, 671, 898, 1213, 1440, 1757, 1980, 2313, 2536, 2837, + 47, 391, 745, 1011, 1290, 1555, 1834, 2097, 2390, 2653, 131, 515, + 829, 1135, 1374, 1679, 1914, 2217, 2470, 2741, 211, 595, 289, 674, + 901, 1216, 1443, 1760, 1983, 2316, 2539, 2840, 51, 395, 749, 1015, + 1294, 1559, 292, 677, 904, 1219, 1446, 1763, 1986, 2319, 2542, 2843, + 55, 399, 753, 1019, 1298, 1563, 1838, 2101, 2394, 2657, 135, 519, + 833, 1139, 1378, 1683, 1918, 2221, 2474, 2745, 215, 599, 295, 680, + 907, 1222, 1449, 1766, 1989, 2322, 2545, 2846, 59, 403, 757, 1023, + 1302, 1567, 1842, 2105, 2398, 2661, 139, 523, 837, 1143, 1382, 1687, + 1922, 2225, 2478, 2749, 219, 603, 298, 683, 910, 1225, 1452, 1769, + 1992, 2325, 2548, 2849, 63, 407, 761, 1027, 1306, 1571, 1846, 2109, + 2402, 2665, 143, 527, 841, 1147, 1386, 1691, 1926, 2229, 2482, 2753, + 223, 301, 686, 913, 1228, 1455, 1772, 1995, 2328, 2551, 2852, 67, + 411, 765, 1031, 1310, 1575, 1850, 2113, 2406, 2669, 147, 531, 845, + 1151, 1390, 1695, 1930, 2233, 2486, 304, 689, 916, 1231, 1458, 1775, + 1998, 2331, 2554, 2855, 71, 415, 769, 1035, 1314, 1579, 1854, 2117, + 2410, 2673, 151, 535, 849, 1155, 1394, 1699, 1934, 2237, 2490, 2761, + 231, 607, 2907, 2913, 2919, 2925, 2931, 2937, 2943, 2949, 2955, 2964, + 2970, 3201, 3214, 3227, 3240, 3253, 3266, 3272, 3278, 3284, 3290, 3194, + 3207, 3220, 3233, 3246, 3259, 3308, 3314, 3320, 3326, 2997, 3024, 3044, + 3064, 3084, 3104, 3124, 3144, 3164, 3184, 2976, 3003, 3030, 3050, 3070, + 3090, 3110, 3130, 3150, 3170, 2983, 3010, 3037, 3057, 3077, 3097, 3117, + 3137, 3157, 3177, 2990, 3017, 619, 860, 1165, 1404, 1709, 1944, 2247, + 2500, 2771, 6, 313, 699, 927, 1242, 1469, 1786, 2009, 2342, 2565, + 83, 427, 781, 1047, 1326, 1591, 1866, 2129, 2422, 2685, 163, 547, + 243, 1159, 1398, 1703, 1938, 2241, 2494, 2765, 0, 307, 692, 919, + 1234, 1461, 1778, 2001, 2334, 2557, 75, 419, 773, 1039, 1318, 1583, + 1858, 2121, 2414, 2677, 155, 539, 235, 611, 853, 857, 1162, 1401, + 1706, 1941, 2244, 2497, 2768, 3, 310, 695, 923, 1238, 1465, 1782, + 2005, 2338, 2561, 79, 423, 777, 1043, 1322, 1587, 1862, 2125, 2418, + 2681, 159, 543, 239, 615, 633, 873, 1177, 1416, 1721, 1956, 2259, + 2512, 2783, 19, 327, 714, 943, 1258, 1485, 1802, 2025, 2358, 2581, + 99, 443, 797, 1063, 1342, 1607, 1882, 2145, 2438, 2701, 179, 563, + 258, 1171, 1410, 1715, 1950, 2253, 2506, 2777, 13, 321, 707, 935, + 1250, 1477, 1794, 2017, 2350, 2573, 91, 435, 789, 1055, 1334, 1599, + 1874, 2137, 2430, 2693, 171, 555, 250, 625, 866, 870, 1174, 1413, + 1718, 1953, 2256, 2509, 2780, 16, 324, 710, 939, 1254, 1481, 1798, + 2021, 2354, 2577, 95, 439, 793, 1059, 1338, 1603, 1878, 2141, 2434, + 2697, 175, 559, 254, 629, 2858, 2271, 2795, 343, 959, 1501, 2041, + 2597, 459, 1079, 1623, 2161, 2889, 639, 1183, 1727, 2265, 2789, 335, + 951, 1493, 2033, 2589, 451, 1071, 1615, 2153, 2709, 2897, 2882, 645, + 1189, 1733, 2289, 2813, 361, 979, 1523, 2065, 2621, 483, 1103, 1647, + 2185, 659, 886, 1201, 1428, 1745, 1968, 2301, 2524, 2825, 32, 375, + 729, 995, 1274, 1539, 1818, 2081, 2374, 2637, 115, 499, 813, 1119, + 1358, 1663, 1898, 2201, 2454, 2725, 195, 579, 273, 1195, 1422, 1739, + 1962, 2295, 2518, 2819, 26, 369, 722, 987, 1266, 1531, 1810, 2073, + 2366, 2629, 107, 491, 805, 1111, 1350, 1655, 1890, 2193, 2446, 2717, + 187, 571, 265, 651, 879, 883, 1198, 1425, 1742, 1965, 2298, 2521, + 2822, 29, 372, 725, 991, 1270, 1535, 1814, 2077, 2370, 2633, 111, + 495, 809, 1115, 1354, 1659, 1894, 2197, 2450, 2721, 191, 575, 269, + 655, + }; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrsvlist1[] = {/* 0 */ "\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint8_t RegAsmOffsetvlist1[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrsvreg[] = {/* 0 */ "v10\0" + /* 4 */ "v20\0" + /* 8 */ "v30\0" + /* 12 */ "v0\0" + /* 15 */ "v11\0" + /* 19 */ "v21\0" + /* 23 */ "v31\0" + /* 27 */ "v1\0" + /* 30 */ "v12\0" + /* 34 */ "v22\0" + /* 38 */ "v2\0" + /* 41 */ "v13\0" + /* 45 */ "v23\0" + /* 49 */ "v3\0" + /* 52 */ "v14\0" + /* 56 */ "v24\0" + /* 60 */ "v4\0" + /* 63 */ "v15\0" + /* 67 */ "v25\0" + /* 71 */ "v5\0" + /* 74 */ "v16\0" + /* 78 */ "v26\0" + /* 82 */ "v6\0" + /* 85 */ "v17\0" + /* 89 */ "v27\0" + /* 93 */ "v7\0" + /* 96 */ "v18\0" + /* 100 */ "v28\0" + /* 104 */ "v8\0" + /* 107 */ "v19\0" + /* 111 */ "v29\0" + /* 115 */ "v9\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint8_t RegAsmOffsetvreg[] = { + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, + 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, + 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, + 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, + 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, + 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, + 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, + 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, + 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, + 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, + 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, + 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, + 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, + 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, + 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, + 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, + 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, + }; + + switch (AltIdx) { + default: + llvm_unreachable("Invalid register alt name index!"); + case AArch64_NoRegAltName: + assert(*(AsmStrsNoRegAltName + RegAsmOffsetNoRegAltName[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrsNoRegAltName + RegAsmOffsetNoRegAltName[RegNo - 1]; + case AArch64_vlist1: + assert(*(AsmStrsvlist1 + RegAsmOffsetvlist1[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrsvlist1 + RegAsmOffsetvlist1[RegNo - 1]; + case AArch64_vreg: + assert(*(AsmStrsvreg + RegAsmOffsetvreg[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrsvreg + RegAsmOffsetvreg[RegNo - 1]; + } +} +#endif +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +static char *printAliasInstr(MCInst *MI, SStream *OS) { + static const PatternsForOpcode OpToPatterns[] = { + {AArch64_ADDSWri, 0, 1}, + {AArch64_ADDSWrs, 1, 3}, + {AArch64_ADDSWrx, 4, 3}, + {AArch64_ADDSXri, 7, 1}, + {AArch64_ADDSXrs, 8, 3}, + {AArch64_ADDSXrx, 11, 1}, + {AArch64_ADDSXrx64, 12, 3}, + {AArch64_ADDWri, 15, 2}, + {AArch64_ADDWrs, 17, 1}, + {AArch64_ADDWrx, 18, 2}, + {AArch64_ADDXri, 20, 2}, + {AArch64_ADDXrs, 22, 1}, + {AArch64_ADDXrx64, 23, 2}, + {AArch64_ANDSWri, 25, 1}, + {AArch64_ANDSWrs, 26, 3}, + {AArch64_ANDSXri, 29, 1}, + {AArch64_ANDSXrs, 30, 3}, + {AArch64_ANDS_PPzPP, 33, 1}, + {AArch64_ANDWrs, 34, 1}, + {AArch64_ANDXrs, 35, 1}, + {AArch64_AND_PPzPP, 36, 1}, + {AArch64_AND_ZI, 37, 3}, + {AArch64_AUTIA1716, 40, 1}, + {AArch64_AUTIASP, 41, 1}, + {AArch64_AUTIAZ, 42, 1}, + {AArch64_AUTIB1716, 43, 1}, + {AArch64_AUTIBSP, 44, 1}, + {AArch64_AUTIBZ, 45, 1}, + {AArch64_BICSWrs, 46, 1}, + {AArch64_BICSXrs, 47, 1}, + {AArch64_BICWrs, 48, 1}, + {AArch64_BICXrs, 49, 1}, + {AArch64_CLREX, 50, 1}, + {AArch64_CNTB_XPiI, 51, 2}, + {AArch64_CNTD_XPiI, 53, 2}, + {AArch64_CNTH_XPiI, 55, 2}, + {AArch64_CNTW_XPiI, 57, 2}, + {AArch64_CPY_ZPmI_B, 59, 1}, + {AArch64_CPY_ZPmI_D, 60, 1}, + {AArch64_CPY_ZPmI_H, 61, 1}, + {AArch64_CPY_ZPmI_S, 62, 1}, + {AArch64_CPY_ZPmR_B, 63, 1}, + {AArch64_CPY_ZPmR_D, 64, 1}, + {AArch64_CPY_ZPmR_H, 65, 1}, + {AArch64_CPY_ZPmR_S, 66, 1}, + {AArch64_CPY_ZPmV_B, 67, 1}, + {AArch64_CPY_ZPmV_D, 68, 1}, + {AArch64_CPY_ZPmV_H, 69, 1}, + {AArch64_CPY_ZPmV_S, 70, 1}, + {AArch64_CPY_ZPzI_B, 71, 1}, + {AArch64_CPY_ZPzI_D, 72, 1}, + {AArch64_CPY_ZPzI_H, 73, 1}, + {AArch64_CPY_ZPzI_S, 74, 1}, + {AArch64_CSINCWr, 75, 2}, + {AArch64_CSINCXr, 77, 2}, + {AArch64_CSINVWr, 79, 2}, + {AArch64_CSINVXr, 81, 2}, + {AArch64_CSNEGWr, 83, 1}, + {AArch64_CSNEGXr, 84, 1}, + {AArch64_DCPS1, 85, 1}, + {AArch64_DCPS2, 86, 1}, + {AArch64_DCPS3, 87, 1}, + {AArch64_DECB_XPiI, 88, 2}, + {AArch64_DECD_XPiI, 90, 2}, + {AArch64_DECD_ZPiI, 92, 2}, + {AArch64_DECH_XPiI, 94, 2}, + {AArch64_DECH_ZPiI, 96, 2}, + {AArch64_DECW_XPiI, 98, 2}, + {AArch64_DECW_ZPiI, 100, 2}, + {AArch64_DSB, 102, 3}, + {AArch64_DUPM_ZI, 105, 6}, + {AArch64_DUP_ZI_B, 111, 1}, + {AArch64_DUP_ZI_D, 112, 2}, + {AArch64_DUP_ZI_H, 114, 2}, + {AArch64_DUP_ZI_S, 116, 2}, + {AArch64_DUP_ZR_B, 118, 1}, + {AArch64_DUP_ZR_D, 119, 1}, + {AArch64_DUP_ZR_H, 120, 1}, + {AArch64_DUP_ZR_S, 121, 1}, + {AArch64_DUP_ZZI_B, 122, 2}, + {AArch64_DUP_ZZI_D, 124, 2}, + {AArch64_DUP_ZZI_H, 126, 2}, + {AArch64_DUP_ZZI_Q, 128, 2}, + {AArch64_DUP_ZZI_S, 130, 2}, + {AArch64_EONWrs, 132, 1}, + {AArch64_EONXrs, 133, 1}, + {AArch64_EORS_PPzPP, 134, 1}, + {AArch64_EORWrs, 135, 1}, + {AArch64_EORXrs, 136, 1}, + {AArch64_EOR_PPzPP, 137, 1}, + {AArch64_EOR_ZI, 138, 3}, + {AArch64_EXTRACT_ZPMXI_H_B, 141, 1}, + {AArch64_EXTRACT_ZPMXI_H_D, 142, 1}, + {AArch64_EXTRACT_ZPMXI_H_H, 143, 1}, + {AArch64_EXTRACT_ZPMXI_H_Q, 144, 1}, + {AArch64_EXTRACT_ZPMXI_H_S, 145, 1}, + {AArch64_EXTRACT_ZPMXI_V_B, 146, 1}, + {AArch64_EXTRACT_ZPMXI_V_D, 147, 1}, + {AArch64_EXTRACT_ZPMXI_V_H, 148, 1}, + {AArch64_EXTRACT_ZPMXI_V_Q, 149, 1}, + {AArch64_EXTRACT_ZPMXI_V_S, 150, 1}, + {AArch64_EXTRWrri, 151, 1}, + {AArch64_EXTRXrri, 152, 1}, + {AArch64_FCPY_ZPmI_D, 153, 1}, + {AArch64_FCPY_ZPmI_H, 154, 1}, + {AArch64_FCPY_ZPmI_S, 155, 1}, + {AArch64_FDUP_ZI_D, 156, 1}, + {AArch64_FDUP_ZI_H, 157, 1}, + {AArch64_FDUP_ZI_S, 158, 1}, + {AArch64_GLD1B_D_IMM_REAL, 159, 1}, + {AArch64_GLD1B_S_IMM_REAL, 160, 1}, + {AArch64_GLD1D_IMM_REAL, 161, 1}, + {AArch64_GLD1H_D_IMM_REAL, 162, 1}, + {AArch64_GLD1H_S_IMM_REAL, 163, 1}, + {AArch64_GLD1SB_D_IMM_REAL, 164, 1}, + {AArch64_GLD1SB_S_IMM_REAL, 165, 1}, + {AArch64_GLD1SH_D_IMM_REAL, 166, 1}, + {AArch64_GLD1SH_S_IMM_REAL, 167, 1}, + {AArch64_GLD1SW_D_IMM_REAL, 168, 1}, + {AArch64_GLD1W_D_IMM_REAL, 169, 1}, + {AArch64_GLD1W_IMM_REAL, 170, 1}, + {AArch64_GLDFF1B_D_IMM_REAL, 171, 1}, + {AArch64_GLDFF1B_S_IMM_REAL, 172, 1}, + {AArch64_GLDFF1D_IMM_REAL, 173, 1}, + {AArch64_GLDFF1H_D_IMM_REAL, 174, 1}, + {AArch64_GLDFF1H_S_IMM_REAL, 175, 1}, + {AArch64_GLDFF1SB_D_IMM_REAL, 176, 1}, + {AArch64_GLDFF1SB_S_IMM_REAL, 177, 1}, + {AArch64_GLDFF1SH_D_IMM_REAL, 178, 1}, + {AArch64_GLDFF1SH_S_IMM_REAL, 179, 1}, + {AArch64_GLDFF1SW_D_IMM_REAL, 180, 1}, + {AArch64_GLDFF1W_D_IMM_REAL, 181, 1}, + {AArch64_GLDFF1W_IMM_REAL, 182, 1}, + {AArch64_HINT, 183, 12}, + {AArch64_INCB_XPiI, 195, 2}, + {AArch64_INCD_XPiI, 197, 2}, + {AArch64_INCD_ZPiI, 199, 2}, + {AArch64_INCH_XPiI, 201, 2}, + {AArch64_INCH_ZPiI, 203, 2}, + {AArch64_INCW_XPiI, 205, 2}, + {AArch64_INCW_ZPiI, 207, 2}, + {AArch64_INSERT_MXIPZ_H_B, 209, 1}, + {AArch64_INSERT_MXIPZ_H_D, 210, 1}, + {AArch64_INSERT_MXIPZ_H_H, 211, 1}, + {AArch64_INSERT_MXIPZ_H_Q, 212, 1}, + {AArch64_INSERT_MXIPZ_H_S, 213, 1}, + {AArch64_INSERT_MXIPZ_V_B, 214, 1}, + {AArch64_INSERT_MXIPZ_V_D, 215, 1}, + {AArch64_INSERT_MXIPZ_V_H, 216, 1}, + {AArch64_INSERT_MXIPZ_V_Q, 217, 1}, + {AArch64_INSERT_MXIPZ_V_S, 218, 1}, + {AArch64_INSvi16gpr, 219, 1}, + {AArch64_INSvi16lane, 220, 1}, + {AArch64_INSvi32gpr, 221, 1}, + {AArch64_INSvi32lane, 222, 1}, + {AArch64_INSvi64gpr, 223, 1}, + {AArch64_INSvi64lane, 224, 1}, + {AArch64_INSvi8gpr, 225, 1}, + {AArch64_INSvi8lane, 226, 1}, + {AArch64_IRG, 227, 1}, + {AArch64_ISB, 228, 1}, + {AArch64_LD1B_D_IMM_REAL, 229, 1}, + {AArch64_LD1B_H_IMM_REAL, 230, 1}, + {AArch64_LD1B_IMM_REAL, 231, 1}, + {AArch64_LD1B_S_IMM_REAL, 232, 1}, + {AArch64_LD1D_IMM_REAL, 233, 1}, + {AArch64_LD1Fourv16b_POST, 234, 1}, + {AArch64_LD1Fourv1d_POST, 235, 1}, + {AArch64_LD1Fourv2d_POST, 236, 1}, + {AArch64_LD1Fourv2s_POST, 237, 1}, + {AArch64_LD1Fourv4h_POST, 238, 1}, + {AArch64_LD1Fourv4s_POST, 239, 1}, + {AArch64_LD1Fourv8b_POST, 240, 1}, + {AArch64_LD1Fourv8h_POST, 241, 1}, + {AArch64_LD1H_D_IMM_REAL, 242, 1}, + {AArch64_LD1H_IMM_REAL, 243, 1}, + {AArch64_LD1H_S_IMM_REAL, 244, 1}, + {AArch64_LD1Onev16b_POST, 245, 1}, + {AArch64_LD1Onev1d_POST, 246, 1}, + {AArch64_LD1Onev2d_POST, 247, 1}, + {AArch64_LD1Onev2s_POST, 248, 1}, + {AArch64_LD1Onev4h_POST, 249, 1}, + {AArch64_LD1Onev4s_POST, 250, 1}, + {AArch64_LD1Onev8b_POST, 251, 1}, + {AArch64_LD1Onev8h_POST, 252, 1}, + {AArch64_LD1RB_D_IMM, 253, 1}, + {AArch64_LD1RB_H_IMM, 254, 1}, + {AArch64_LD1RB_IMM, 255, 1}, + {AArch64_LD1RB_S_IMM, 256, 1}, + {AArch64_LD1RD_IMM, 257, 1}, + {AArch64_LD1RH_D_IMM, 258, 1}, + {AArch64_LD1RH_IMM, 259, 1}, + {AArch64_LD1RH_S_IMM, 260, 1}, + {AArch64_LD1RO_B_IMM, 261, 1}, + {AArch64_LD1RO_D_IMM, 262, 1}, + {AArch64_LD1RO_H_IMM, 263, 1}, + {AArch64_LD1RO_W_IMM, 264, 1}, + {AArch64_LD1RQ_B_IMM, 265, 1}, + {AArch64_LD1RQ_D_IMM, 266, 1}, + {AArch64_LD1RQ_H_IMM, 267, 1}, + {AArch64_LD1RQ_W_IMM, 268, 1}, + {AArch64_LD1RSB_D_IMM, 269, 1}, + {AArch64_LD1RSB_H_IMM, 270, 1}, + {AArch64_LD1RSB_S_IMM, 271, 1}, + {AArch64_LD1RSH_D_IMM, 272, 1}, + {AArch64_LD1RSH_S_IMM, 273, 1}, + {AArch64_LD1RSW_IMM, 274, 1}, + {AArch64_LD1RW_D_IMM, 275, 1}, + {AArch64_LD1RW_IMM, 276, 1}, + {AArch64_LD1Rv16b_POST, 277, 1}, + {AArch64_LD1Rv1d_POST, 278, 1}, + {AArch64_LD1Rv2d_POST, 279, 1}, + {AArch64_LD1Rv2s_POST, 280, 1}, + {AArch64_LD1Rv4h_POST, 281, 1}, + {AArch64_LD1Rv4s_POST, 282, 1}, + {AArch64_LD1Rv8b_POST, 283, 1}, + {AArch64_LD1Rv8h_POST, 284, 1}, + {AArch64_LD1SB_D_IMM_REAL, 285, 1}, + {AArch64_LD1SB_H_IMM_REAL, 286, 1}, + {AArch64_LD1SB_S_IMM_REAL, 287, 1}, + {AArch64_LD1SH_D_IMM_REAL, 288, 1}, + {AArch64_LD1SH_S_IMM_REAL, 289, 1}, + {AArch64_LD1SW_D_IMM_REAL, 290, 1}, + {AArch64_LD1Threev16b_POST, 291, 1}, + {AArch64_LD1Threev1d_POST, 292, 1}, + {AArch64_LD1Threev2d_POST, 293, 1}, + {AArch64_LD1Threev2s_POST, 294, 1}, + {AArch64_LD1Threev4h_POST, 295, 1}, + {AArch64_LD1Threev4s_POST, 296, 1}, + {AArch64_LD1Threev8b_POST, 297, 1}, + {AArch64_LD1Threev8h_POST, 298, 1}, + {AArch64_LD1Twov16b_POST, 299, 1}, + {AArch64_LD1Twov1d_POST, 300, 1}, + {AArch64_LD1Twov2d_POST, 301, 1}, + {AArch64_LD1Twov2s_POST, 302, 1}, + {AArch64_LD1Twov4h_POST, 303, 1}, + {AArch64_LD1Twov4s_POST, 304, 1}, + {AArch64_LD1Twov8b_POST, 305, 1}, + {AArch64_LD1Twov8h_POST, 306, 1}, + {AArch64_LD1W_D_IMM_REAL, 307, 1}, + {AArch64_LD1W_IMM_REAL, 308, 1}, + {AArch64_LD1_MXIPXX_H_B, 309, 1}, + {AArch64_LD1_MXIPXX_H_D, 310, 1}, + {AArch64_LD1_MXIPXX_H_H, 311, 1}, + {AArch64_LD1_MXIPXX_H_Q, 312, 1}, + {AArch64_LD1_MXIPXX_H_S, 313, 1}, + {AArch64_LD1_MXIPXX_V_B, 314, 1}, + {AArch64_LD1_MXIPXX_V_D, 315, 1}, + {AArch64_LD1_MXIPXX_V_H, 316, 1}, + {AArch64_LD1_MXIPXX_V_Q, 317, 1}, + {AArch64_LD1_MXIPXX_V_S, 318, 1}, + {AArch64_LD1i16_POST, 319, 1}, + {AArch64_LD1i32_POST, 320, 1}, + {AArch64_LD1i64_POST, 321, 1}, + {AArch64_LD1i8_POST, 322, 1}, + {AArch64_LD2B_IMM, 323, 1}, + {AArch64_LD2D_IMM, 324, 1}, + {AArch64_LD2H_IMM, 325, 1}, + {AArch64_LD2Rv16b_POST, 326, 1}, + {AArch64_LD2Rv1d_POST, 327, 1}, + {AArch64_LD2Rv2d_POST, 328, 1}, + {AArch64_LD2Rv2s_POST, 329, 1}, + {AArch64_LD2Rv4h_POST, 330, 1}, + {AArch64_LD2Rv4s_POST, 331, 1}, + {AArch64_LD2Rv8b_POST, 332, 1}, + {AArch64_LD2Rv8h_POST, 333, 1}, + {AArch64_LD2Twov16b_POST, 334, 1}, + {AArch64_LD2Twov2d_POST, 335, 1}, + {AArch64_LD2Twov2s_POST, 336, 1}, + {AArch64_LD2Twov4h_POST, 337, 1}, + {AArch64_LD2Twov4s_POST, 338, 1}, + {AArch64_LD2Twov8b_POST, 339, 1}, + {AArch64_LD2Twov8h_POST, 340, 1}, + {AArch64_LD2W_IMM, 341, 1}, + {AArch64_LD2i16_POST, 342, 1}, + {AArch64_LD2i32_POST, 343, 1}, + {AArch64_LD2i64_POST, 344, 1}, + {AArch64_LD2i8_POST, 345, 1}, + {AArch64_LD3B_IMM, 346, 1}, + {AArch64_LD3D_IMM, 347, 1}, + {AArch64_LD3H_IMM, 348, 1}, + {AArch64_LD3Rv16b_POST, 349, 1}, + {AArch64_LD3Rv1d_POST, 350, 1}, + {AArch64_LD3Rv2d_POST, 351, 1}, + {AArch64_LD3Rv2s_POST, 352, 1}, + {AArch64_LD3Rv4h_POST, 353, 1}, + {AArch64_LD3Rv4s_POST, 354, 1}, + {AArch64_LD3Rv8b_POST, 355, 1}, + {AArch64_LD3Rv8h_POST, 356, 1}, + {AArch64_LD3Threev16b_POST, 357, 1}, + {AArch64_LD3Threev2d_POST, 358, 1}, + {AArch64_LD3Threev2s_POST, 359, 1}, + {AArch64_LD3Threev4h_POST, 360, 1}, + {AArch64_LD3Threev4s_POST, 361, 1}, + {AArch64_LD3Threev8b_POST, 362, 1}, + {AArch64_LD3Threev8h_POST, 363, 1}, + {AArch64_LD3W_IMM, 364, 1}, + {AArch64_LD3i16_POST, 365, 1}, + {AArch64_LD3i32_POST, 366, 1}, + {AArch64_LD3i64_POST, 367, 1}, + {AArch64_LD3i8_POST, 368, 1}, + {AArch64_LD4B_IMM, 369, 1}, + {AArch64_LD4D_IMM, 370, 1}, + {AArch64_LD4Fourv16b_POST, 371, 1}, + {AArch64_LD4Fourv2d_POST, 372, 1}, + {AArch64_LD4Fourv2s_POST, 373, 1}, + {AArch64_LD4Fourv4h_POST, 374, 1}, + {AArch64_LD4Fourv4s_POST, 375, 1}, + {AArch64_LD4Fourv8b_POST, 376, 1}, + {AArch64_LD4Fourv8h_POST, 377, 1}, + {AArch64_LD4H_IMM, 378, 1}, + {AArch64_LD4Rv16b_POST, 379, 1}, + {AArch64_LD4Rv1d_POST, 380, 1}, + {AArch64_LD4Rv2d_POST, 381, 1}, + {AArch64_LD4Rv2s_POST, 382, 1}, + {AArch64_LD4Rv4h_POST, 383, 1}, + {AArch64_LD4Rv4s_POST, 384, 1}, + {AArch64_LD4Rv8b_POST, 385, 1}, + {AArch64_LD4Rv8h_POST, 386, 1}, + {AArch64_LD4W_IMM, 387, 1}, + {AArch64_LD4i16_POST, 388, 1}, + {AArch64_LD4i32_POST, 389, 1}, + {AArch64_LD4i64_POST, 390, 1}, + {AArch64_LD4i8_POST, 391, 1}, + {AArch64_LDADDB, 392, 1}, + {AArch64_LDADDH, 393, 1}, + {AArch64_LDADDLB, 394, 1}, + {AArch64_LDADDLH, 395, 1}, + {AArch64_LDADDLW, 396, 1}, + {AArch64_LDADDLX, 397, 1}, + {AArch64_LDADDW, 398, 1}, + {AArch64_LDADDX, 399, 1}, + {AArch64_LDAPURBi, 400, 1}, + {AArch64_LDAPURHi, 401, 1}, + {AArch64_LDAPURSBWi, 402, 1}, + {AArch64_LDAPURSBXi, 403, 1}, + {AArch64_LDAPURSHWi, 404, 1}, + {AArch64_LDAPURSHXi, 405, 1}, + {AArch64_LDAPURSWi, 406, 1}, + {AArch64_LDAPURXi, 407, 1}, + {AArch64_LDAPURi, 408, 1}, + {AArch64_LDCLRB, 409, 1}, + {AArch64_LDCLRH, 410, 1}, + {AArch64_LDCLRLB, 411, 1}, + {AArch64_LDCLRLH, 412, 1}, + {AArch64_LDCLRLW, 413, 1}, + {AArch64_LDCLRLX, 414, 1}, + {AArch64_LDCLRW, 415, 1}, + {AArch64_LDCLRX, 416, 1}, + {AArch64_LDEORB, 417, 1}, + {AArch64_LDEORH, 418, 1}, + {AArch64_LDEORLB, 419, 1}, + {AArch64_LDEORLH, 420, 1}, + {AArch64_LDEORLW, 421, 1}, + {AArch64_LDEORLX, 422, 1}, + {AArch64_LDEORW, 423, 1}, + {AArch64_LDEORX, 424, 1}, + {AArch64_LDFF1B_D_REAL, 425, 1}, + {AArch64_LDFF1B_H_REAL, 426, 1}, + {AArch64_LDFF1B_REAL, 427, 1}, + {AArch64_LDFF1B_S_REAL, 428, 1}, + {AArch64_LDFF1D_REAL, 429, 1}, + {AArch64_LDFF1H_D_REAL, 430, 1}, + {AArch64_LDFF1H_REAL, 431, 1}, + {AArch64_LDFF1H_S_REAL, 432, 1}, + {AArch64_LDFF1SB_D_REAL, 433, 1}, + {AArch64_LDFF1SB_H_REAL, 434, 1}, + {AArch64_LDFF1SB_S_REAL, 435, 1}, + {AArch64_LDFF1SH_D_REAL, 436, 1}, + {AArch64_LDFF1SH_S_REAL, 437, 1}, + {AArch64_LDFF1SW_D_REAL, 438, 1}, + {AArch64_LDFF1W_D_REAL, 439, 1}, + {AArch64_LDFF1W_REAL, 440, 1}, + {AArch64_LDG, 441, 1}, + {AArch64_LDNF1B_D_IMM_REAL, 442, 1}, + {AArch64_LDNF1B_H_IMM_REAL, 443, 1}, + {AArch64_LDNF1B_IMM_REAL, 444, 1}, + {AArch64_LDNF1B_S_IMM_REAL, 445, 1}, + {AArch64_LDNF1D_IMM_REAL, 446, 1}, + {AArch64_LDNF1H_D_IMM_REAL, 447, 1}, + {AArch64_LDNF1H_IMM_REAL, 448, 1}, + {AArch64_LDNF1H_S_IMM_REAL, 449, 1}, + {AArch64_LDNF1SB_D_IMM_REAL, 450, 1}, + {AArch64_LDNF1SB_H_IMM_REAL, 451, 1}, + {AArch64_LDNF1SB_S_IMM_REAL, 452, 1}, + {AArch64_LDNF1SH_D_IMM_REAL, 453, 1}, + {AArch64_LDNF1SH_S_IMM_REAL, 454, 1}, + {AArch64_LDNF1SW_D_IMM_REAL, 455, 1}, + {AArch64_LDNF1W_D_IMM_REAL, 456, 1}, + {AArch64_LDNF1W_IMM_REAL, 457, 1}, + {AArch64_LDNPDi, 458, 1}, + {AArch64_LDNPQi, 459, 1}, + {AArch64_LDNPSi, 460, 1}, + {AArch64_LDNPWi, 461, 1}, + {AArch64_LDNPXi, 462, 1}, + {AArch64_LDNT1B_ZRI, 463, 1}, + {AArch64_LDNT1B_ZZR_D_REAL, 464, 1}, + {AArch64_LDNT1B_ZZR_S_REAL, 465, 1}, + {AArch64_LDNT1D_ZRI, 466, 1}, + {AArch64_LDNT1D_ZZR_D_REAL, 467, 1}, + {AArch64_LDNT1H_ZRI, 468, 1}, + {AArch64_LDNT1H_ZZR_D_REAL, 469, 1}, + {AArch64_LDNT1H_ZZR_S_REAL, 470, 1}, + {AArch64_LDNT1SB_ZZR_D_REAL, 471, 1}, + {AArch64_LDNT1SB_ZZR_S_REAL, 472, 1}, + {AArch64_LDNT1SH_ZZR_D_REAL, 473, 1}, + {AArch64_LDNT1SH_ZZR_S_REAL, 474, 1}, + {AArch64_LDNT1SW_ZZR_D_REAL, 475, 1}, + {AArch64_LDNT1W_ZRI, 476, 1}, + {AArch64_LDNT1W_ZZR_D_REAL, 477, 1}, + {AArch64_LDNT1W_ZZR_S_REAL, 478, 1}, + {AArch64_LDPDi, 479, 1}, + {AArch64_LDPQi, 480, 1}, + {AArch64_LDPSWi, 481, 1}, + {AArch64_LDPSi, 482, 1}, + {AArch64_LDPWi, 483, 1}, + {AArch64_LDPXi, 484, 1}, + {AArch64_LDRAAindexed, 485, 1}, + {AArch64_LDRABindexed, 486, 1}, + {AArch64_LDRBBroX, 487, 1}, + {AArch64_LDRBBui, 488, 1}, + {AArch64_LDRBroX, 489, 1}, + {AArch64_LDRBui, 490, 1}, + {AArch64_LDRDroX, 491, 1}, + {AArch64_LDRDui, 492, 1}, + {AArch64_LDRHHroX, 493, 1}, + {AArch64_LDRHHui, 494, 1}, + {AArch64_LDRHroX, 495, 1}, + {AArch64_LDRHui, 496, 1}, + {AArch64_LDRQroX, 497, 1}, + {AArch64_LDRQui, 498, 1}, + {AArch64_LDRSBWroX, 499, 1}, + {AArch64_LDRSBWui, 500, 1}, + {AArch64_LDRSBXroX, 501, 1}, + {AArch64_LDRSBXui, 502, 1}, + {AArch64_LDRSHWroX, 503, 1}, + {AArch64_LDRSHWui, 504, 1}, + {AArch64_LDRSHXroX, 505, 1}, + {AArch64_LDRSHXui, 506, 1}, + {AArch64_LDRSWroX, 507, 1}, + {AArch64_LDRSWui, 508, 1}, + {AArch64_LDRSroX, 509, 1}, + {AArch64_LDRSui, 510, 1}, + {AArch64_LDRWroX, 511, 1}, + {AArch64_LDRWui, 512, 1}, + {AArch64_LDRXroX, 513, 1}, + {AArch64_LDRXui, 514, 1}, + {AArch64_LDR_PXI, 515, 1}, + {AArch64_LDR_ZA, 516, 1}, + {AArch64_LDR_ZXI, 517, 1}, + {AArch64_LDSETB, 518, 1}, + {AArch64_LDSETH, 519, 1}, + {AArch64_LDSETLB, 520, 1}, + {AArch64_LDSETLH, 521, 1}, + {AArch64_LDSETLW, 522, 1}, + {AArch64_LDSETLX, 523, 1}, + {AArch64_LDSETW, 524, 1}, + {AArch64_LDSETX, 525, 1}, + {AArch64_LDSMAXB, 526, 1}, + {AArch64_LDSMAXH, 527, 1}, + {AArch64_LDSMAXLB, 528, 1}, + {AArch64_LDSMAXLH, 529, 1}, + {AArch64_LDSMAXLW, 530, 1}, + {AArch64_LDSMAXLX, 531, 1}, + {AArch64_LDSMAXW, 532, 1}, + {AArch64_LDSMAXX, 533, 1}, + {AArch64_LDSMINB, 534, 1}, + {AArch64_LDSMINH, 535, 1}, + {AArch64_LDSMINLB, 536, 1}, + {AArch64_LDSMINLH, 537, 1}, + {AArch64_LDSMINLW, 538, 1}, + {AArch64_LDSMINLX, 539, 1}, + {AArch64_LDSMINW, 540, 1}, + {AArch64_LDSMINX, 541, 1}, + {AArch64_LDTRBi, 542, 1}, + {AArch64_LDTRHi, 543, 1}, + {AArch64_LDTRSBWi, 544, 1}, + {AArch64_LDTRSBXi, 545, 1}, + {AArch64_LDTRSHWi, 546, 1}, + {AArch64_LDTRSHXi, 547, 1}, + {AArch64_LDTRSWi, 548, 1}, + {AArch64_LDTRWi, 549, 1}, + {AArch64_LDTRXi, 550, 1}, + {AArch64_LDUMAXB, 551, 1}, + {AArch64_LDUMAXH, 552, 1}, + {AArch64_LDUMAXLB, 553, 1}, + {AArch64_LDUMAXLH, 554, 1}, + {AArch64_LDUMAXLW, 555, 1}, + {AArch64_LDUMAXLX, 556, 1}, + {AArch64_LDUMAXW, 557, 1}, + {AArch64_LDUMAXX, 558, 1}, + {AArch64_LDUMINB, 559, 1}, + {AArch64_LDUMINH, 560, 1}, + {AArch64_LDUMINLB, 561, 1}, + {AArch64_LDUMINLH, 562, 1}, + {AArch64_LDUMINLW, 563, 1}, + {AArch64_LDUMINLX, 564, 1}, + {AArch64_LDUMINW, 565, 1}, + {AArch64_LDUMINX, 566, 1}, + {AArch64_LDURBBi, 567, 1}, + {AArch64_LDURBi, 568, 1}, + {AArch64_LDURDi, 569, 1}, + {AArch64_LDURHHi, 570, 1}, + {AArch64_LDURHi, 571, 1}, + {AArch64_LDURQi, 572, 1}, + {AArch64_LDURSBWi, 573, 1}, + {AArch64_LDURSBXi, 574, 1}, + {AArch64_LDURSHWi, 575, 1}, + {AArch64_LDURSHXi, 576, 1}, + {AArch64_LDURSWi, 577, 1}, + {AArch64_LDURSi, 578, 1}, + {AArch64_LDURWi, 579, 1}, + {AArch64_LDURXi, 580, 1}, + {AArch64_MADDWrrr, 581, 1}, + {AArch64_MADDXrrr, 582, 1}, + {AArch64_MSRpstatesvcrImm1, 583, 6}, + {AArch64_MSUBWrrr, 589, 1}, + {AArch64_MSUBXrrr, 590, 1}, + {AArch64_NOTv16i8, 591, 1}, + {AArch64_NOTv8i8, 592, 1}, + {AArch64_ORNWrs, 593, 3}, + {AArch64_ORNXrs, 596, 3}, + {AArch64_ORRS_PPzPP, 599, 1}, + {AArch64_ORRWrs, 600, 2}, + {AArch64_ORRXrs, 602, 2}, + {AArch64_ORR_PPzPP, 604, 1}, + {AArch64_ORR_ZI, 605, 3}, + {AArch64_ORR_ZZZ, 608, 1}, + {AArch64_ORRv16i8, 609, 1}, + {AArch64_ORRv8i8, 610, 1}, + {AArch64_PACIA1716, 611, 1}, + {AArch64_PACIASP, 612, 1}, + {AArch64_PACIAZ, 613, 1}, + {AArch64_PACIB1716, 614, 1}, + {AArch64_PACIBSP, 615, 1}, + {AArch64_PACIBZ, 616, 1}, + {AArch64_PRFB_D_PZI, 617, 1}, + {AArch64_PRFB_PRI, 618, 1}, + {AArch64_PRFB_S_PZI, 619, 1}, + {AArch64_PRFD_D_PZI, 620, 1}, + {AArch64_PRFD_PRI, 621, 1}, + {AArch64_PRFD_S_PZI, 622, 1}, + {AArch64_PRFH_D_PZI, 623, 1}, + {AArch64_PRFH_PRI, 624, 1}, + {AArch64_PRFH_S_PZI, 625, 1}, + {AArch64_PRFMroX, 626, 1}, + {AArch64_PRFMui, 627, 1}, + {AArch64_PRFUMi, 628, 1}, + {AArch64_PRFW_D_PZI, 629, 1}, + {AArch64_PRFW_PRI, 630, 1}, + {AArch64_PRFW_S_PZI, 631, 1}, + {AArch64_PTRUES_B, 632, 1}, + {AArch64_PTRUES_D, 633, 1}, + {AArch64_PTRUES_H, 634, 1}, + {AArch64_PTRUES_S, 635, 1}, + {AArch64_PTRUE_B, 636, 1}, + {AArch64_PTRUE_D, 637, 1}, + {AArch64_PTRUE_H, 638, 1}, + {AArch64_PTRUE_S, 639, 1}, + {AArch64_RET, 640, 1}, + {AArch64_SBCSWr, 641, 1}, + {AArch64_SBCSXr, 642, 1}, + {AArch64_SBCWr, 643, 1}, + {AArch64_SBCXr, 644, 1}, + {AArch64_SBFMWri, 645, 3}, + {AArch64_SBFMXri, 648, 4}, + {AArch64_SEL_PPPP, 652, 1}, + {AArch64_SEL_ZPZZ_B, 653, 1}, + {AArch64_SEL_ZPZZ_D, 654, 1}, + {AArch64_SEL_ZPZZ_H, 655, 1}, + {AArch64_SEL_ZPZZ_S, 656, 1}, + {AArch64_SMADDLrrr, 657, 1}, + {AArch64_SMSUBLrrr, 658, 1}, + {AArch64_SQDECB_XPiI, 659, 2}, + {AArch64_SQDECB_XPiWdI, 661, 2}, + {AArch64_SQDECD_XPiI, 663, 2}, + {AArch64_SQDECD_XPiWdI, 665, 2}, + {AArch64_SQDECD_ZPiI, 667, 2}, + {AArch64_SQDECH_XPiI, 669, 2}, + {AArch64_SQDECH_XPiWdI, 671, 2}, + {AArch64_SQDECH_ZPiI, 673, 2}, + {AArch64_SQDECW_XPiI, 675, 2}, + {AArch64_SQDECW_XPiWdI, 677, 2}, + {AArch64_SQDECW_ZPiI, 679, 2}, + {AArch64_SQINCB_XPiI, 681, 2}, + {AArch64_SQINCB_XPiWdI, 683, 2}, + {AArch64_SQINCD_XPiI, 685, 2}, + {AArch64_SQINCD_XPiWdI, 687, 2}, + {AArch64_SQINCD_ZPiI, 689, 2}, + {AArch64_SQINCH_XPiI, 691, 2}, + {AArch64_SQINCH_XPiWdI, 693, 2}, + {AArch64_SQINCH_ZPiI, 695, 2}, + {AArch64_SQINCW_XPiI, 697, 2}, + {AArch64_SQINCW_XPiWdI, 699, 2}, + {AArch64_SQINCW_ZPiI, 701, 2}, + {AArch64_SST1B_D_IMM, 703, 1}, + {AArch64_SST1B_S_IMM, 704, 1}, + {AArch64_SST1D_IMM, 705, 1}, + {AArch64_SST1H_D_IMM, 706, 1}, + {AArch64_SST1H_S_IMM, 707, 1}, + {AArch64_SST1W_D_IMM, 708, 1}, + {AArch64_SST1W_IMM, 709, 1}, + {AArch64_ST1B_D_IMM, 710, 1}, + {AArch64_ST1B_H_IMM, 711, 1}, + {AArch64_ST1B_IMM, 712, 1}, + {AArch64_ST1B_S_IMM, 713, 1}, + {AArch64_ST1D_IMM, 714, 1}, + {AArch64_ST1Fourv16b_POST, 715, 1}, + {AArch64_ST1Fourv1d_POST, 716, 1}, + {AArch64_ST1Fourv2d_POST, 717, 1}, + {AArch64_ST1Fourv2s_POST, 718, 1}, + {AArch64_ST1Fourv4h_POST, 719, 1}, + {AArch64_ST1Fourv4s_POST, 720, 1}, + {AArch64_ST1Fourv8b_POST, 721, 1}, + {AArch64_ST1Fourv8h_POST, 722, 1}, + {AArch64_ST1H_D_IMM, 723, 1}, + {AArch64_ST1H_IMM, 724, 1}, + {AArch64_ST1H_S_IMM, 725, 1}, + {AArch64_ST1Onev16b_POST, 726, 1}, + {AArch64_ST1Onev1d_POST, 727, 1}, + {AArch64_ST1Onev2d_POST, 728, 1}, + {AArch64_ST1Onev2s_POST, 729, 1}, + {AArch64_ST1Onev4h_POST, 730, 1}, + {AArch64_ST1Onev4s_POST, 731, 1}, + {AArch64_ST1Onev8b_POST, 732, 1}, + {AArch64_ST1Onev8h_POST, 733, 1}, + {AArch64_ST1Threev16b_POST, 734, 1}, + {AArch64_ST1Threev1d_POST, 735, 1}, + {AArch64_ST1Threev2d_POST, 736, 1}, + {AArch64_ST1Threev2s_POST, 737, 1}, + {AArch64_ST1Threev4h_POST, 738, 1}, + {AArch64_ST1Threev4s_POST, 739, 1}, + {AArch64_ST1Threev8b_POST, 740, 1}, + {AArch64_ST1Threev8h_POST, 741, 1}, + {AArch64_ST1Twov16b_POST, 742, 1}, + {AArch64_ST1Twov1d_POST, 743, 1}, + {AArch64_ST1Twov2d_POST, 744, 1}, + {AArch64_ST1Twov2s_POST, 745, 1}, + {AArch64_ST1Twov4h_POST, 746, 1}, + {AArch64_ST1Twov4s_POST, 747, 1}, + {AArch64_ST1Twov8b_POST, 748, 1}, + {AArch64_ST1Twov8h_POST, 749, 1}, + {AArch64_ST1W_D_IMM, 750, 1}, + {AArch64_ST1W_IMM, 751, 1}, + {AArch64_ST1_MXIPXX_H_B, 752, 1}, + {AArch64_ST1_MXIPXX_H_D, 753, 1}, + {AArch64_ST1_MXIPXX_H_H, 754, 1}, + {AArch64_ST1_MXIPXX_H_Q, 755, 1}, + {AArch64_ST1_MXIPXX_H_S, 756, 1}, + {AArch64_ST1_MXIPXX_V_B, 757, 1}, + {AArch64_ST1_MXIPXX_V_D, 758, 1}, + {AArch64_ST1_MXIPXX_V_H, 759, 1}, + {AArch64_ST1_MXIPXX_V_Q, 760, 1}, + {AArch64_ST1_MXIPXX_V_S, 761, 1}, + {AArch64_ST1i16_POST, 762, 1}, + {AArch64_ST1i32_POST, 763, 1}, + {AArch64_ST1i64_POST, 764, 1}, + {AArch64_ST1i8_POST, 765, 1}, + {AArch64_ST2B_IMM, 766, 1}, + {AArch64_ST2D_IMM, 767, 1}, + {AArch64_ST2GOffset, 768, 1}, + {AArch64_ST2H_IMM, 769, 1}, + {AArch64_ST2Twov16b_POST, 770, 1}, + {AArch64_ST2Twov2d_POST, 771, 1}, + {AArch64_ST2Twov2s_POST, 772, 1}, + {AArch64_ST2Twov4h_POST, 773, 1}, + {AArch64_ST2Twov4s_POST, 774, 1}, + {AArch64_ST2Twov8b_POST, 775, 1}, + {AArch64_ST2Twov8h_POST, 776, 1}, + {AArch64_ST2W_IMM, 777, 1}, + {AArch64_ST2i16_POST, 778, 1}, + {AArch64_ST2i32_POST, 779, 1}, + {AArch64_ST2i64_POST, 780, 1}, + {AArch64_ST2i8_POST, 781, 1}, + {AArch64_ST3B_IMM, 782, 1}, + {AArch64_ST3D_IMM, 783, 1}, + {AArch64_ST3H_IMM, 784, 1}, + {AArch64_ST3Threev16b_POST, 785, 1}, + {AArch64_ST3Threev2d_POST, 786, 1}, + {AArch64_ST3Threev2s_POST, 787, 1}, + {AArch64_ST3Threev4h_POST, 788, 1}, + {AArch64_ST3Threev4s_POST, 789, 1}, + {AArch64_ST3Threev8b_POST, 790, 1}, + {AArch64_ST3Threev8h_POST, 791, 1}, + {AArch64_ST3W_IMM, 792, 1}, + {AArch64_ST3i16_POST, 793, 1}, + {AArch64_ST3i32_POST, 794, 1}, + {AArch64_ST3i64_POST, 795, 1}, + {AArch64_ST3i8_POST, 796, 1}, + {AArch64_ST4B_IMM, 797, 1}, + {AArch64_ST4D_IMM, 798, 1}, + {AArch64_ST4Fourv16b_POST, 799, 1}, + {AArch64_ST4Fourv2d_POST, 800, 1}, + {AArch64_ST4Fourv2s_POST, 801, 1}, + {AArch64_ST4Fourv4h_POST, 802, 1}, + {AArch64_ST4Fourv4s_POST, 803, 1}, + {AArch64_ST4Fourv8b_POST, 804, 1}, + {AArch64_ST4Fourv8h_POST, 805, 1}, + {AArch64_ST4H_IMM, 806, 1}, + {AArch64_ST4W_IMM, 807, 1}, + {AArch64_ST4i16_POST, 808, 1}, + {AArch64_ST4i32_POST, 809, 1}, + {AArch64_ST4i64_POST, 810, 1}, + {AArch64_ST4i8_POST, 811, 1}, + {AArch64_STGOffset, 812, 1}, + {AArch64_STGPi, 813, 1}, + {AArch64_STLURBi, 814, 1}, + {AArch64_STLURHi, 815, 1}, + {AArch64_STLURWi, 816, 1}, + {AArch64_STLURXi, 817, 1}, + {AArch64_STNPDi, 818, 1}, + {AArch64_STNPQi, 819, 1}, + {AArch64_STNPSi, 820, 1}, + {AArch64_STNPWi, 821, 1}, + {AArch64_STNPXi, 822, 1}, + {AArch64_STNT1B_ZRI, 823, 1}, + {AArch64_STNT1B_ZZR_D_REAL, 824, 1}, + {AArch64_STNT1B_ZZR_S_REAL, 825, 1}, + {AArch64_STNT1D_ZRI, 826, 1}, + {AArch64_STNT1D_ZZR_D_REAL, 827, 1}, + {AArch64_STNT1H_ZRI, 828, 1}, + {AArch64_STNT1H_ZZR_D_REAL, 829, 1}, + {AArch64_STNT1H_ZZR_S_REAL, 830, 1}, + {AArch64_STNT1W_ZRI, 831, 1}, + {AArch64_STNT1W_ZZR_D_REAL, 832, 1}, + {AArch64_STNT1W_ZZR_S_REAL, 833, 1}, + {AArch64_STPDi, 834, 1}, + {AArch64_STPQi, 835, 1}, + {AArch64_STPSi, 836, 1}, + {AArch64_STPWi, 837, 1}, + {AArch64_STPXi, 838, 1}, + {AArch64_STRBBroX, 839, 1}, + {AArch64_STRBBui, 840, 1}, + {AArch64_STRBroX, 841, 1}, + {AArch64_STRBui, 842, 1}, + {AArch64_STRDroX, 843, 1}, + {AArch64_STRDui, 844, 1}, + {AArch64_STRHHroX, 845, 1}, + {AArch64_STRHHui, 846, 1}, + {AArch64_STRHroX, 847, 1}, + {AArch64_STRHui, 848, 1}, + {AArch64_STRQroX, 849, 1}, + {AArch64_STRQui, 850, 1}, + {AArch64_STRSroX, 851, 1}, + {AArch64_STRSui, 852, 1}, + {AArch64_STRWroX, 853, 1}, + {AArch64_STRWui, 854, 1}, + {AArch64_STRXroX, 855, 1}, + {AArch64_STRXui, 856, 1}, + {AArch64_STR_PXI, 857, 1}, + {AArch64_STR_ZA, 858, 1}, + {AArch64_STR_ZXI, 859, 1}, + {AArch64_STTRBi, 860, 1}, + {AArch64_STTRHi, 861, 1}, + {AArch64_STTRWi, 862, 1}, + {AArch64_STTRXi, 863, 1}, + {AArch64_STURBBi, 864, 1}, + {AArch64_STURBi, 865, 1}, + {AArch64_STURDi, 866, 1}, + {AArch64_STURHHi, 867, 1}, + {AArch64_STURHi, 868, 1}, + {AArch64_STURQi, 869, 1}, + {AArch64_STURSi, 870, 1}, + {AArch64_STURWi, 871, 1}, + {AArch64_STURXi, 872, 1}, + {AArch64_STZ2GOffset, 873, 1}, + {AArch64_STZGOffset, 874, 1}, + {AArch64_SUBSWri, 875, 1}, + {AArch64_SUBSWrs, 876, 5}, + {AArch64_SUBSWrx, 881, 3}, + {AArch64_SUBSXri, 884, 1}, + {AArch64_SUBSXrs, 885, 5}, + {AArch64_SUBSXrx, 890, 1}, + {AArch64_SUBSXrx64, 891, 3}, + {AArch64_SUBWrs, 894, 3}, + {AArch64_SUBWrx, 897, 2}, + {AArch64_SUBXrs, 899, 3}, + {AArch64_SUBXrx64, 902, 2}, + {AArch64_SYSxt, 904, 1}, + {AArch64_UBFMWri, 905, 3}, + {AArch64_UBFMXri, 908, 4}, + {AArch64_UMADDLrrr, 912, 1}, + {AArch64_UMOVvi32, 913, 1}, + {AArch64_UMOVvi32_idx0, 914, 1}, + {AArch64_UMOVvi64, 915, 1}, + {AArch64_UMOVvi64_idx0, 916, 1}, + {AArch64_UMSUBLrrr, 917, 1}, + {AArch64_UQDECB_WPiI, 918, 2}, + {AArch64_UQDECB_XPiI, 920, 2}, + {AArch64_UQDECD_WPiI, 922, 2}, + {AArch64_UQDECD_XPiI, 924, 2}, + {AArch64_UQDECD_ZPiI, 926, 2}, + {AArch64_UQDECH_WPiI, 928, 2}, + {AArch64_UQDECH_XPiI, 930, 2}, + {AArch64_UQDECH_ZPiI, 932, 2}, + {AArch64_UQDECW_WPiI, 934, 2}, + {AArch64_UQDECW_XPiI, 936, 2}, + {AArch64_UQDECW_ZPiI, 938, 2}, + {AArch64_UQINCB_WPiI, 940, 2}, + {AArch64_UQINCB_XPiI, 942, 2}, + {AArch64_UQINCD_WPiI, 944, 2}, + {AArch64_UQINCD_XPiI, 946, 2}, + {AArch64_UQINCD_ZPiI, 948, 2}, + {AArch64_UQINCH_WPiI, 950, 2}, + {AArch64_UQINCH_XPiI, 952, 2}, + {AArch64_UQINCH_ZPiI, 954, 2}, + {AArch64_UQINCW_WPiI, 956, 2}, + {AArch64_UQINCW_XPiI, 958, 2}, + {AArch64_UQINCW_ZPiI, 960, 2}, + {AArch64_XPACLRI, 962, 1}, + {AArch64_ZERO_M, 963, 15}, + }; + + static const AliasPattern Patterns[] = { + // AArch64::ADDSWri - 0 + {0, 0, 4, 2}, + // AArch64::ADDSWrs - 1 + {13, 2, 4, 4}, + {24, 6, 4, 3}, + {39, 9, 4, 4}, + // AArch64::ADDSWrx - 4 + {13, 13, 4, 4}, + {55, 17, 4, 3}, + {39, 20, 4, 4}, + // AArch64::ADDSXri - 7 + {0, 24, 4, 2}, + // AArch64::ADDSXrs - 8 + {13, 26, 4, 4}, + {24, 30, 4, 3}, + {39, 33, 4, 4}, + // AArch64::ADDSXrx - 11 + {55, 37, 4, 3}, + // AArch64::ADDSXrx64 - 12 + {13, 40, 4, 4}, + {55, 44, 4, 3}, + {39, 47, 4, 4}, + // AArch64::ADDWri - 15 + {70, 51, 4, 4}, + {70, 55, 4, 4}, + // AArch64::ADDWrs - 17 + {81, 59, 4, 4}, + // AArch64::ADDWrx - 18 + {81, 63, 4, 4}, + {81, 67, 4, 4}, + // AArch64::ADDXri - 20 + {70, 71, 4, 4}, + {70, 75, 4, 4}, + // AArch64::ADDXrs - 22 + {81, 79, 4, 4}, + // AArch64::ADDXrx64 - 23 + {81, 83, 4, 4}, + {81, 87, 4, 4}, + // AArch64::ANDSWri - 25 + {96, 91, 3, 2}, + // AArch64::ANDSWrs - 26 + {109, 93, 4, 4}, + {120, 97, 4, 3}, + {135, 100, 4, 4}, + // AArch64::ANDSXri - 29 + {151, 104, 3, 2}, + // AArch64::ANDSXrs - 30 + {109, 106, 4, 4}, + {120, 110, 4, 3}, + {135, 113, 4, 4}, + // AArch64::ANDS_PPzPP - 33 + {164, 117, 4, 7}, + // AArch64::ANDWrs - 34 + {188, 124, 4, 4}, + // AArch64::ANDXrs - 35 + {188, 128, 4, 4}, + // AArch64::AND_PPzPP - 36 + {203, 132, 4, 7}, + // AArch64::AND_ZI - 37 + {226, 139, 3, 6}, + {247, 145, 3, 6}, + {268, 151, 3, 6}, + // AArch64::AUTIA1716 - 40 + {289, 157, 0, 1}, + // AArch64::AUTIASP - 41 + {299, 158, 0, 1}, + // AArch64::AUTIAZ - 42 + {307, 159, 0, 1}, + // AArch64::AUTIB1716 - 43 + {314, 160, 0, 1}, + // AArch64::AUTIBSP - 44 + {324, 161, 0, 1}, + // AArch64::AUTIBZ - 45 + {332, 162, 0, 1}, + // AArch64::BICSWrs - 46 + {339, 163, 4, 4}, + // AArch64::BICSXrs - 47 + {339, 167, 4, 4}, + // AArch64::BICWrs - 48 + {355, 171, 4, 4}, + // AArch64::BICXrs - 49 + {355, 175, 4, 4}, + // AArch64::CLREX - 50 + {370, 179, 1, 1}, + // AArch64::CNTB_XPiI - 51 + {376, 180, 3, 6}, + {384, 186, 3, 6}, + // AArch64::CNTD_XPiI - 53 + {398, 192, 3, 6}, + {406, 198, 3, 6}, + // AArch64::CNTH_XPiI - 55 + {420, 204, 3, 6}, + {428, 210, 3, 6}, + // AArch64::CNTW_XPiI - 57 + {442, 216, 3, 6}, + {450, 222, 3, 6}, + // AArch64::CPY_ZPmI_B - 59 + {464, 228, 5, 6}, + // AArch64::CPY_ZPmI_D - 60 + {487, 234, 5, 6}, + // AArch64::CPY_ZPmI_H - 61 + {510, 240, 5, 6}, + // AArch64::CPY_ZPmI_S - 62 + {533, 246, 5, 6}, + // AArch64::CPY_ZPmR_B - 63 + {556, 252, 4, 7}, + // AArch64::CPY_ZPmR_D - 64 + {577, 259, 4, 7}, + // AArch64::CPY_ZPmR_H - 65 + {598, 266, 4, 7}, + // AArch64::CPY_ZPmR_S - 66 + {619, 273, 4, 7}, + // AArch64::CPY_ZPmV_B - 67 + {556, 280, 4, 7}, + // AArch64::CPY_ZPmV_D - 68 + {577, 287, 4, 7}, + // AArch64::CPY_ZPmV_H - 69 + {598, 294, 4, 7}, + // AArch64::CPY_ZPmV_S - 70 + {619, 301, 4, 7}, + // AArch64::CPY_ZPzI_B - 71 + {640, 308, 4, 5}, + // AArch64::CPY_ZPzI_D - 72 + {663, 313, 4, 5}, + // AArch64::CPY_ZPzI_H - 73 + {686, 318, 4, 5}, + // AArch64::CPY_ZPzI_S - 74 + {709, 323, 4, 5}, + // AArch64::CSINCWr - 75 + {732, 328, 4, 4}, + {746, 332, 4, 4}, + // AArch64::CSINCXr - 77 + {732, 336, 4, 4}, + {746, 340, 4, 4}, + // AArch64::CSINVWr - 79 + {764, 344, 4, 4}, + {779, 348, 4, 4}, + // AArch64::CSINVXr - 81 + {764, 352, 4, 4}, + {779, 356, 4, 4}, + // AArch64::CSNEGWr - 83 + {797, 360, 4, 4}, + // AArch64::CSNEGXr - 84 + {797, 364, 4, 4}, + // AArch64::DCPS1 - 85 + {815, 368, 1, 1}, + // AArch64::DCPS2 - 86 + {821, 369, 1, 1}, + // AArch64::DCPS3 - 87 + {827, 370, 1, 2}, + // AArch64::DECB_XPiI - 88 + {833, 372, 4, 7}, + {841, 379, 4, 7}, + // AArch64::DECD_XPiI - 90 + {855, 386, 4, 7}, + {863, 393, 4, 7}, + // AArch64::DECD_ZPiI - 92 + {877, 400, 4, 7}, + {887, 407, 4, 7}, + // AArch64::DECH_XPiI - 94 + {903, 414, 4, 7}, + {911, 421, 4, 7}, + // AArch64::DECH_ZPiI - 96 + {925, 428, 4, 7}, + {935, 435, 4, 7}, + // AArch64::DECW_XPiI - 98 + {951, 442, 4, 7}, + {959, 449, 4, 7}, + // AArch64::DECW_ZPiI - 100 + {973, 456, 4, 7}, + {983, 463, 4, 7}, + // AArch64::DSB - 102 + {999, 470, 1, 1}, + {1004, 471, 1, 1}, + {1010, 472, 1, 2}, + // AArch64::DUPM_ZI - 105 + {1014, 474, 2, 5}, + {1029, 479, 2, 5}, + {1044, 484, 2, 5}, + {1059, 489, 2, 5}, + {1075, 494, 2, 5}, + {1091, 499, 2, 5}, + // AArch64::DUP_ZI_B - 111 + {1107, 504, 3, 4}, + // AArch64::DUP_ZI_D - 112 + {1122, 508, 3, 4}, + {1137, 512, 3, 6}, + // AArch64::DUP_ZI_H - 114 + {1153, 518, 3, 4}, + {1168, 522, 3, 6}, + // AArch64::DUP_ZI_S - 116 + {1184, 528, 3, 4}, + {1199, 532, 3, 6}, + // AArch64::DUP_ZR_B - 118 + {1215, 538, 2, 5}, + // AArch64::DUP_ZR_D - 119 + {1228, 543, 2, 5}, + // AArch64::DUP_ZR_H - 120 + {1241, 548, 2, 5}, + // AArch64::DUP_ZR_S - 121 + {1254, 553, 2, 5}, + // AArch64::DUP_ZZI_B - 122 + {1267, 558, 3, 6}, + {1282, 564, 3, 5}, + // AArch64::DUP_ZZI_D - 124 + {1301, 569, 3, 6}, + {1316, 575, 3, 5}, + // AArch64::DUP_ZZI_H - 126 + {1335, 580, 3, 6}, + {1350, 586, 3, 5}, + // AArch64::DUP_ZZI_Q - 128 + {1369, 591, 3, 6}, + {1384, 597, 3, 5}, + // AArch64::DUP_ZZI_S - 130 + {1403, 602, 3, 6}, + {1418, 608, 3, 5}, + // AArch64::EONWrs - 132 + {1437, 613, 4, 4}, + // AArch64::EONXrs - 133 + {1437, 617, 4, 4}, + // AArch64::EORS_PPzPP - 134 + {1452, 621, 4, 7}, + // AArch64::EORWrs - 135 + {1476, 628, 4, 4}, + // AArch64::EORXrs - 136 + {1476, 632, 4, 4}, + // AArch64::EOR_PPzPP - 137 + {1491, 636, 4, 7}, + // AArch64::EOR_ZI - 138 + {1514, 643, 3, 6}, + {1535, 649, 3, 6}, + {1556, 655, 3, 6}, + // AArch64::EXTRACT_ZPMXI_H_B - 141 + {1577, 661, 5, 5}, + // AArch64::EXTRACT_ZPMXI_H_D - 142 + {1610, 666, 5, 5}, + // AArch64::EXTRACT_ZPMXI_H_H - 143 + {1643, 671, 5, 5}, + // AArch64::EXTRACT_ZPMXI_H_Q - 144 + {1676, 676, 5, 5}, + // AArch64::EXTRACT_ZPMXI_H_S - 145 + {1709, 681, 5, 5}, + // AArch64::EXTRACT_ZPMXI_V_B - 146 + {1742, 686, 5, 5}, + // AArch64::EXTRACT_ZPMXI_V_D - 147 + {1775, 691, 5, 5}, + // AArch64::EXTRACT_ZPMXI_V_H - 148 + {1808, 696, 5, 5}, + // AArch64::EXTRACT_ZPMXI_V_Q - 149 + {1841, 701, 5, 5}, + // AArch64::EXTRACT_ZPMXI_V_S - 150 + {1874, 706, 5, 5}, + // AArch64::EXTRWrri - 151 + {1907, 711, 4, 3}, + // AArch64::EXTRXrri - 152 + {1907, 714, 4, 3}, + // AArch64::FCPY_ZPmI_D - 153 + {1922, 717, 4, 6}, + // AArch64::FCPY_ZPmI_H - 154 + {1946, 723, 4, 6}, + // AArch64::FCPY_ZPmI_S - 155 + {1970, 729, 4, 6}, + // AArch64::FDUP_ZI_D - 156 + {1994, 735, 2, 4}, + // AArch64::FDUP_ZI_H - 157 + {2010, 739, 2, 4}, + // AArch64::FDUP_ZI_S - 158 + {2026, 743, 2, 4}, + // AArch64::GLD1B_D_IMM_REAL - 159 + {2042, 747, 4, 5}, + // AArch64::GLD1B_S_IMM_REAL - 160 + {2068, 752, 4, 5}, + // AArch64::GLD1D_IMM_REAL - 161 + {2094, 757, 4, 5}, + // AArch64::GLD1H_D_IMM_REAL - 162 + {2120, 762, 4, 5}, + // AArch64::GLD1H_S_IMM_REAL - 163 + {2146, 767, 4, 5}, + // AArch64::GLD1SB_D_IMM_REAL - 164 + {2172, 772, 4, 5}, + // AArch64::GLD1SB_S_IMM_REAL - 165 + {2199, 777, 4, 5}, + // AArch64::GLD1SH_D_IMM_REAL - 166 + {2226, 782, 4, 5}, + // AArch64::GLD1SH_S_IMM_REAL - 167 + {2253, 787, 4, 5}, + // AArch64::GLD1SW_D_IMM_REAL - 168 + {2280, 792, 4, 5}, + // AArch64::GLD1W_D_IMM_REAL - 169 + {2307, 797, 4, 5}, + // AArch64::GLD1W_IMM_REAL - 170 + {2333, 802, 4, 5}, + // AArch64::GLDFF1B_D_IMM_REAL - 171 + {2359, 807, 4, 5}, + // AArch64::GLDFF1B_S_IMM_REAL - 172 + {2387, 812, 4, 5}, + // AArch64::GLDFF1D_IMM_REAL - 173 + {2415, 817, 4, 5}, + // AArch64::GLDFF1H_D_IMM_REAL - 174 + {2443, 822, 4, 5}, + // AArch64::GLDFF1H_S_IMM_REAL - 175 + {2471, 827, 4, 5}, + // AArch64::GLDFF1SB_D_IMM_REAL - 176 + {2499, 832, 4, 5}, + // AArch64::GLDFF1SB_S_IMM_REAL - 177 + {2528, 837, 4, 5}, + // AArch64::GLDFF1SH_D_IMM_REAL - 178 + {2557, 842, 4, 5}, + // AArch64::GLDFF1SH_S_IMM_REAL - 179 + {2586, 847, 4, 5}, + // AArch64::GLDFF1SW_D_IMM_REAL - 180 + {2615, 852, 4, 5}, + // AArch64::GLDFF1W_D_IMM_REAL - 181 + {2644, 857, 4, 5}, + // AArch64::GLDFF1W_IMM_REAL - 182 + {2672, 862, 4, 5}, + // AArch64::HINT - 183 + {2700, 867, 1, 1}, + {2704, 868, 1, 1}, + {2710, 869, 1, 1}, + {2714, 870, 1, 1}, + {2718, 871, 1, 1}, + {2722, 872, 1, 1}, + {2727, 873, 1, 1}, + {2731, 874, 1, 2}, + {2735, 876, 1, 1}, + {2740, 877, 1, 2}, + {2744, 879, 1, 2}, + {2753, 881, 1, 2}, + // AArch64::INCB_XPiI - 195 + {2762, 883, 4, 7}, + {2770, 890, 4, 7}, + // AArch64::INCD_XPiI - 197 + {2784, 897, 4, 7}, + {2792, 904, 4, 7}, + // AArch64::INCD_ZPiI - 199 + {2806, 911, 4, 7}, + {2816, 918, 4, 7}, + // AArch64::INCH_XPiI - 201 + {2832, 925, 4, 7}, + {2840, 932, 4, 7}, + // AArch64::INCH_ZPiI - 203 + {2854, 939, 4, 7}, + {2864, 946, 4, 7}, + // AArch64::INCW_XPiI - 205 + {2880, 953, 4, 7}, + {2888, 960, 4, 7}, + // AArch64::INCW_ZPiI - 207 + {2902, 967, 4, 7}, + {2912, 974, 4, 7}, + // AArch64::INSERT_MXIPZ_H_B - 209 + {2928, 981, 5, 6}, + // AArch64::INSERT_MXIPZ_H_D - 210 + {2961, 987, 5, 6}, + // AArch64::INSERT_MXIPZ_H_H - 211 + {2994, 993, 5, 6}, + // AArch64::INSERT_MXIPZ_H_Q - 212 + {3027, 999, 5, 6}, + // AArch64::INSERT_MXIPZ_H_S - 213 + {3060, 1005, 5, 6}, + // AArch64::INSERT_MXIPZ_V_B - 214 + {3093, 1011, 5, 6}, + // AArch64::INSERT_MXIPZ_V_D - 215 + {3126, 1017, 5, 6}, + // AArch64::INSERT_MXIPZ_V_H - 216 + {3159, 1023, 5, 6}, + // AArch64::INSERT_MXIPZ_V_Q - 217 + {3192, 1029, 5, 6}, + // AArch64::INSERT_MXIPZ_V_S - 218 + {3225, 1035, 5, 6}, + // AArch64::INSvi16gpr - 219 + {3258, 1041, 4, 5}, + // AArch64::INSvi16lane - 220 + {3277, 1046, 5, 5}, + // AArch64::INSvi32gpr - 221 + {3304, 1051, 4, 5}, + // AArch64::INSvi32lane - 222 + {3323, 1056, 5, 5}, + // AArch64::INSvi64gpr - 223 + {3350, 1061, 4, 5}, + // AArch64::INSvi64lane - 224 + {3369, 1066, 5, 5}, + // AArch64::INSvi8gpr - 225 + {3396, 1071, 4, 5}, + // AArch64::INSvi8lane - 226 + {3415, 1076, 5, 5}, + // AArch64::IRG - 227 + {3442, 1081, 3, 4}, + // AArch64::ISB - 228 + {3453, 1085, 1, 1}, + // AArch64::LD1B_D_IMM_REAL - 229 + {3457, 1086, 4, 7}, + // AArch64::LD1B_H_IMM_REAL - 230 + {3481, 1093, 4, 7}, + // AArch64::LD1B_IMM_REAL - 231 + {3505, 1100, 4, 7}, + // AArch64::LD1B_S_IMM_REAL - 232 + {3529, 1107, 4, 7}, + // AArch64::LD1D_IMM_REAL - 233 + {3553, 1114, 4, 7}, + // AArch64::LD1Fourv16b_POST - 234 + {3577, 1121, 4, 5}, + // AArch64::LD1Fourv1d_POST - 235 + {3597, 1126, 4, 5}, + // AArch64::LD1Fourv2d_POST - 236 + {3617, 1131, 4, 5}, + // AArch64::LD1Fourv2s_POST - 237 + {3637, 1136, 4, 5}, + // AArch64::LD1Fourv4h_POST - 238 + {3657, 1141, 4, 5}, + // AArch64::LD1Fourv4s_POST - 239 + {3677, 1146, 4, 5}, + // AArch64::LD1Fourv8b_POST - 240 + {3697, 1151, 4, 5}, + // AArch64::LD1Fourv8h_POST - 241 + {3717, 1156, 4, 5}, + // AArch64::LD1H_D_IMM_REAL - 242 + {3737, 1161, 4, 7}, + // AArch64::LD1H_IMM_REAL - 243 + {3761, 1168, 4, 7}, + // AArch64::LD1H_S_IMM_REAL - 244 + {3785, 1175, 4, 7}, + // AArch64::LD1Onev16b_POST - 245 + {3809, 1182, 4, 5}, + // AArch64::LD1Onev1d_POST - 246 + {3829, 1187, 4, 5}, + // AArch64::LD1Onev2d_POST - 247 + {3848, 1192, 4, 5}, + // AArch64::LD1Onev2s_POST - 248 + {3868, 1197, 4, 5}, + // AArch64::LD1Onev4h_POST - 249 + {3887, 1202, 4, 5}, + // AArch64::LD1Onev4s_POST - 250 + {3906, 1207, 4, 5}, + // AArch64::LD1Onev8b_POST - 251 + {3926, 1212, 4, 5}, + // AArch64::LD1Onev8h_POST - 252 + {3945, 1217, 4, 5}, + // AArch64::LD1RB_D_IMM - 253 + {3965, 1222, 4, 7}, + // AArch64::LD1RB_H_IMM - 254 + {3990, 1229, 4, 7}, + // AArch64::LD1RB_IMM - 255 + {4015, 1236, 4, 7}, + // AArch64::LD1RB_S_IMM - 256 + {4040, 1243, 4, 7}, + // AArch64::LD1RD_IMM - 257 + {4065, 1250, 4, 7}, + // AArch64::LD1RH_D_IMM - 258 + {4090, 1257, 4, 7}, + // AArch64::LD1RH_IMM - 259 + {4115, 1264, 4, 7}, + // AArch64::LD1RH_S_IMM - 260 + {4140, 1271, 4, 7}, + // AArch64::LD1RO_B_IMM - 261 + {4165, 1278, 4, 6}, + // AArch64::LD1RO_D_IMM - 262 + {4191, 1284, 4, 6}, + // AArch64::LD1RO_H_IMM - 263 + {4217, 1290, 4, 6}, + // AArch64::LD1RO_W_IMM - 264 + {4243, 1296, 4, 6}, + // AArch64::LD1RQ_B_IMM - 265 + {4269, 1302, 4, 7}, + // AArch64::LD1RQ_D_IMM - 266 + {4295, 1309, 4, 7}, + // AArch64::LD1RQ_H_IMM - 267 + {4321, 1316, 4, 7}, + // AArch64::LD1RQ_W_IMM - 268 + {4347, 1323, 4, 7}, + // AArch64::LD1RSB_D_IMM - 269 + {4373, 1330, 4, 7}, + // AArch64::LD1RSB_H_IMM - 270 + {4399, 1337, 4, 7}, + // AArch64::LD1RSB_S_IMM - 271 + {4425, 1344, 4, 7}, + // AArch64::LD1RSH_D_IMM - 272 + {4451, 1351, 4, 7}, + // AArch64::LD1RSH_S_IMM - 273 + {4477, 1358, 4, 7}, + // AArch64::LD1RSW_IMM - 274 + {4503, 1365, 4, 7}, + // AArch64::LD1RW_D_IMM - 275 + {4529, 1372, 4, 7}, + // AArch64::LD1RW_IMM - 276 + {4554, 1379, 4, 7}, + // AArch64::LD1Rv16b_POST - 277 + {4579, 1386, 4, 5}, + // AArch64::LD1Rv1d_POST - 278 + {4599, 1391, 4, 5}, + // AArch64::LD1Rv2d_POST - 279 + {4619, 1396, 4, 5}, + // AArch64::LD1Rv2s_POST - 280 + {4639, 1401, 4, 5}, + // AArch64::LD1Rv4h_POST - 281 + {4659, 1406, 4, 5}, + // AArch64::LD1Rv4s_POST - 282 + {4679, 1411, 4, 5}, + // AArch64::LD1Rv8b_POST - 283 + {4699, 1416, 4, 5}, + // AArch64::LD1Rv8h_POST - 284 + {4719, 1421, 4, 5}, + // AArch64::LD1SB_D_IMM_REAL - 285 + {4739, 1426, 4, 7}, + // AArch64::LD1SB_H_IMM_REAL - 286 + {4764, 1433, 4, 7}, + // AArch64::LD1SB_S_IMM_REAL - 287 + {4789, 1440, 4, 7}, + // AArch64::LD1SH_D_IMM_REAL - 288 + {4814, 1447, 4, 7}, + // AArch64::LD1SH_S_IMM_REAL - 289 + {4839, 1454, 4, 7}, + // AArch64::LD1SW_D_IMM_REAL - 290 + {4864, 1461, 4, 7}, + // AArch64::LD1Threev16b_POST - 291 + {4889, 1468, 4, 5}, + // AArch64::LD1Threev1d_POST - 292 + {4909, 1473, 4, 5}, + // AArch64::LD1Threev2d_POST - 293 + {4929, 1478, 4, 5}, + // AArch64::LD1Threev2s_POST - 294 + {4949, 1483, 4, 5}, + // AArch64::LD1Threev4h_POST - 295 + {4969, 1488, 4, 5}, + // AArch64::LD1Threev4s_POST - 296 + {4989, 1493, 4, 5}, + // AArch64::LD1Threev8b_POST - 297 + {5009, 1498, 4, 5}, + // AArch64::LD1Threev8h_POST - 298 + {5029, 1503, 4, 5}, + // AArch64::LD1Twov16b_POST - 299 + {5049, 1508, 4, 5}, + // AArch64::LD1Twov1d_POST - 300 + {5069, 1513, 4, 5}, + // AArch64::LD1Twov2d_POST - 301 + {5089, 1518, 4, 5}, + // AArch64::LD1Twov2s_POST - 302 + {5109, 1523, 4, 5}, + // AArch64::LD1Twov4h_POST - 303 + {5129, 1528, 4, 5}, + // AArch64::LD1Twov4s_POST - 304 + {5149, 1533, 4, 5}, + // AArch64::LD1Twov8b_POST - 305 + {5169, 1538, 4, 5}, + // AArch64::LD1Twov8h_POST - 306 + {5189, 1543, 4, 5}, + // AArch64::LD1W_D_IMM_REAL - 307 + {5209, 1548, 4, 7}, + // AArch64::LD1W_IMM_REAL - 308 + {5233, 1555, 4, 7}, + // AArch64::LD1_MXIPXX_H_B - 309 + {5257, 1562, 6, 7}, + // AArch64::LD1_MXIPXX_H_D - 310 + {5293, 1569, 6, 7}, + // AArch64::LD1_MXIPXX_H_H - 311 + {5329, 1576, 6, 7}, + // AArch64::LD1_MXIPXX_H_Q - 312 + {5365, 1583, 6, 7}, + // AArch64::LD1_MXIPXX_H_S - 313 + {5401, 1590, 6, 7}, + // AArch64::LD1_MXIPXX_V_B - 314 + {5437, 1597, 6, 7}, + // AArch64::LD1_MXIPXX_V_D - 315 + {5473, 1604, 6, 7}, + // AArch64::LD1_MXIPXX_V_H - 316 + {5509, 1611, 6, 7}, + // AArch64::LD1_MXIPXX_V_Q - 317 + {5545, 1618, 6, 7}, + // AArch64::LD1_MXIPXX_V_S - 318 + {5581, 1625, 6, 7}, + // AArch64::LD1i16_POST - 319 + {5617, 1632, 6, 7}, + // AArch64::LD1i32_POST - 320 + {5640, 1639, 6, 7}, + // AArch64::LD1i64_POST - 321 + {5663, 1646, 6, 7}, + // AArch64::LD1i8_POST - 322 + {5686, 1653, 6, 7}, + // AArch64::LD2B_IMM - 323 + {5709, 1660, 4, 7}, + // AArch64::LD2D_IMM - 324 + {5733, 1667, 4, 7}, + // AArch64::LD2H_IMM - 325 + {5757, 1674, 4, 7}, + // AArch64::LD2Rv16b_POST - 326 + {5781, 1681, 4, 5}, + // AArch64::LD2Rv1d_POST - 327 + {5801, 1686, 4, 5}, + // AArch64::LD2Rv2d_POST - 328 + {5822, 1691, 4, 5}, + // AArch64::LD2Rv2s_POST - 329 + {5843, 1696, 4, 5}, + // AArch64::LD2Rv4h_POST - 330 + {5863, 1701, 4, 5}, + // AArch64::LD2Rv4s_POST - 331 + {5883, 1706, 4, 5}, + // AArch64::LD2Rv8b_POST - 332 + {5903, 1711, 4, 5}, + // AArch64::LD2Rv8h_POST - 333 + {5923, 1716, 4, 5}, + // AArch64::LD2Twov16b_POST - 334 + {5943, 1721, 4, 5}, + // AArch64::LD2Twov2d_POST - 335 + {5963, 1726, 4, 5}, + // AArch64::LD2Twov2s_POST - 336 + {5983, 1731, 4, 5}, + // AArch64::LD2Twov4h_POST - 337 + {6003, 1736, 4, 5}, + // AArch64::LD2Twov4s_POST - 338 + {6023, 1741, 4, 5}, + // AArch64::LD2Twov8b_POST - 339 + {6043, 1746, 4, 5}, + // AArch64::LD2Twov8h_POST - 340 + {6063, 1751, 4, 5}, + // AArch64::LD2W_IMM - 341 + {6083, 1756, 4, 7}, + // AArch64::LD2i16_POST - 342 + {6107, 1763, 6, 7}, + // AArch64::LD2i32_POST - 343 + {6130, 1770, 6, 7}, + // AArch64::LD2i64_POST - 344 + {6153, 1777, 6, 7}, + // AArch64::LD2i8_POST - 345 + {6177, 1784, 6, 7}, + // AArch64::LD3B_IMM - 346 + {6200, 1791, 4, 7}, + // AArch64::LD3D_IMM - 347 + {6224, 1798, 4, 7}, + // AArch64::LD3H_IMM - 348 + {6248, 1805, 4, 7}, + // AArch64::LD3Rv16b_POST - 349 + {6272, 1812, 4, 5}, + // AArch64::LD3Rv1d_POST - 350 + {6292, 1817, 4, 5}, + // AArch64::LD3Rv2d_POST - 351 + {6313, 1822, 4, 5}, + // AArch64::LD3Rv2s_POST - 352 + {6334, 1827, 4, 5}, + // AArch64::LD3Rv4h_POST - 353 + {6355, 1832, 4, 5}, + // AArch64::LD3Rv4s_POST - 354 + {6375, 1837, 4, 5}, + // AArch64::LD3Rv8b_POST - 355 + {6396, 1842, 4, 5}, + // AArch64::LD3Rv8h_POST - 356 + {6416, 1847, 4, 5}, + // AArch64::LD3Threev16b_POST - 357 + {6436, 1852, 4, 5}, + // AArch64::LD3Threev2d_POST - 358 + {6456, 1857, 4, 5}, + // AArch64::LD3Threev2s_POST - 359 + {6476, 1862, 4, 5}, + // AArch64::LD3Threev4h_POST - 360 + {6496, 1867, 4, 5}, + // AArch64::LD3Threev4s_POST - 361 + {6516, 1872, 4, 5}, + // AArch64::LD3Threev8b_POST - 362 + {6536, 1877, 4, 5}, + // AArch64::LD3Threev8h_POST - 363 + {6556, 1882, 4, 5}, + // AArch64::LD3W_IMM - 364 + {6576, 1887, 4, 7}, + // AArch64::LD3i16_POST - 365 + {6600, 1894, 6, 7}, + // AArch64::LD3i32_POST - 366 + {6623, 1901, 6, 7}, + // AArch64::LD3i64_POST - 367 + {6647, 1908, 6, 7}, + // AArch64::LD3i8_POST - 368 + {6671, 1915, 6, 7}, + // AArch64::LD4B_IMM - 369 + {6694, 1922, 4, 7}, + // AArch64::LD4D_IMM - 370 + {6718, 1929, 4, 7}, + // AArch64::LD4Fourv16b_POST - 371 + {6742, 1936, 4, 5}, + // AArch64::LD4Fourv2d_POST - 372 + {6762, 1941, 4, 5}, + // AArch64::LD4Fourv2s_POST - 373 + {6782, 1946, 4, 5}, + // AArch64::LD4Fourv4h_POST - 374 + {6802, 1951, 4, 5}, + // AArch64::LD4Fourv4s_POST - 375 + {6822, 1956, 4, 5}, + // AArch64::LD4Fourv8b_POST - 376 + {6842, 1961, 4, 5}, + // AArch64::LD4Fourv8h_POST - 377 + {6862, 1966, 4, 5}, + // AArch64::LD4H_IMM - 378 + {6882, 1971, 4, 7}, + // AArch64::LD4Rv16b_POST - 379 + {6906, 1978, 4, 5}, + // AArch64::LD4Rv1d_POST - 380 + {6926, 1983, 4, 5}, + // AArch64::LD4Rv2d_POST - 381 + {6947, 1988, 4, 5}, + // AArch64::LD4Rv2s_POST - 382 + {6968, 1993, 4, 5}, + // AArch64::LD4Rv4h_POST - 383 + {6989, 1998, 4, 5}, + // AArch64::LD4Rv4s_POST - 384 + {7009, 2003, 4, 5}, + // AArch64::LD4Rv8b_POST - 385 + {7030, 2008, 4, 5}, + // AArch64::LD4Rv8h_POST - 386 + {7050, 2013, 4, 5}, + // AArch64::LD4W_IMM - 387 + {7070, 2018, 4, 7}, + // AArch64::LD4i16_POST - 388 + {7094, 2025, 6, 7}, + // AArch64::LD4i32_POST - 389 + {7117, 2032, 6, 7}, + // AArch64::LD4i64_POST - 390 + {7141, 2039, 6, 7}, + // AArch64::LD4i8_POST - 391 + {7165, 2046, 6, 7}, + // AArch64::LDADDB - 392 + {7188, 2053, 3, 4}, + // AArch64::LDADDH - 393 + {7204, 2057, 3, 4}, + // AArch64::LDADDLB - 394 + {7220, 2061, 3, 4}, + // AArch64::LDADDLH - 395 + {7237, 2065, 3, 4}, + // AArch64::LDADDLW - 396 + {7254, 2069, 3, 4}, + // AArch64::LDADDLX - 397 + {7254, 2073, 3, 4}, + // AArch64::LDADDW - 398 + {7270, 2077, 3, 4}, + // AArch64::LDADDX - 399 + {7270, 2081, 3, 4}, + // AArch64::LDAPURBi - 400 + {7285, 2085, 3, 4}, + // AArch64::LDAPURHi - 401 + {7302, 2089, 3, 4}, + // AArch64::LDAPURSBWi - 402 + {7319, 2093, 3, 4}, + // AArch64::LDAPURSBXi - 403 + {7319, 2097, 3, 4}, + // AArch64::LDAPURSHWi - 404 + {7337, 2101, 3, 4}, + // AArch64::LDAPURSHXi - 405 + {7337, 2105, 3, 4}, + // AArch64::LDAPURSWi - 406 + {7355, 2109, 3, 4}, + // AArch64::LDAPURXi - 407 + {7373, 2113, 3, 4}, + // AArch64::LDAPURi - 408 + {7373, 2117, 3, 4}, + // AArch64::LDCLRB - 409 + {7389, 2121, 3, 4}, + // AArch64::LDCLRH - 410 + {7405, 2125, 3, 4}, + // AArch64::LDCLRLB - 411 + {7421, 2129, 3, 4}, + // AArch64::LDCLRLH - 412 + {7438, 2133, 3, 4}, + // AArch64::LDCLRLW - 413 + {7455, 2137, 3, 4}, + // AArch64::LDCLRLX - 414 + {7455, 2141, 3, 4}, + // AArch64::LDCLRW - 415 + {7471, 2145, 3, 4}, + // AArch64::LDCLRX - 416 + {7471, 2149, 3, 4}, + // AArch64::LDEORB - 417 + {7486, 2153, 3, 4}, + // AArch64::LDEORH - 418 + {7502, 2157, 3, 4}, + // AArch64::LDEORLB - 419 + {7518, 2161, 3, 4}, + // AArch64::LDEORLH - 420 + {7535, 2165, 3, 4}, + // AArch64::LDEORLW - 421 + {7552, 2169, 3, 4}, + // AArch64::LDEORLX - 422 + {7552, 2173, 3, 4}, + // AArch64::LDEORW - 423 + {7568, 2177, 3, 4}, + // AArch64::LDEORX - 424 + {7568, 2181, 3, 4}, + // AArch64::LDFF1B_D_REAL - 425 + {7583, 2185, 4, 5}, + // AArch64::LDFF1B_H_REAL - 426 + {7609, 2190, 4, 5}, + // AArch64::LDFF1B_REAL - 427 + {7635, 2195, 4, 5}, + // AArch64::LDFF1B_S_REAL - 428 + {7661, 2200, 4, 5}, + // AArch64::LDFF1D_REAL - 429 + {7687, 2205, 4, 5}, + // AArch64::LDFF1H_D_REAL - 430 + {7713, 2210, 4, 5}, + // AArch64::LDFF1H_REAL - 431 + {7739, 2215, 4, 5}, + // AArch64::LDFF1H_S_REAL - 432 + {7765, 2220, 4, 5}, + // AArch64::LDFF1SB_D_REAL - 433 + {7791, 2225, 4, 5}, + // AArch64::LDFF1SB_H_REAL - 434 + {7818, 2230, 4, 5}, + // AArch64::LDFF1SB_S_REAL - 435 + {7845, 2235, 4, 5}, + // AArch64::LDFF1SH_D_REAL - 436 + {7872, 2240, 4, 5}, + // AArch64::LDFF1SH_S_REAL - 437 + {7899, 2245, 4, 5}, + // AArch64::LDFF1SW_D_REAL - 438 + {7926, 2250, 4, 5}, + // AArch64::LDFF1W_D_REAL - 439 + {7953, 2255, 4, 5}, + // AArch64::LDFF1W_REAL - 440 + {7979, 2260, 4, 5}, + // AArch64::LDG - 441 + {8005, 2265, 4, 5}, + // AArch64::LDNF1B_D_IMM_REAL - 442 + {8018, 2270, 4, 5}, + // AArch64::LDNF1B_H_IMM_REAL - 443 + {8044, 2275, 4, 5}, + // AArch64::LDNF1B_IMM_REAL - 444 + {8070, 2280, 4, 5}, + // AArch64::LDNF1B_S_IMM_REAL - 445 + {8096, 2285, 4, 5}, + // AArch64::LDNF1D_IMM_REAL - 446 + {8122, 2290, 4, 5}, + // AArch64::LDNF1H_D_IMM_REAL - 447 + {8148, 2295, 4, 5}, + // AArch64::LDNF1H_IMM_REAL - 448 + {8174, 2300, 4, 5}, + // AArch64::LDNF1H_S_IMM_REAL - 449 + {8200, 2305, 4, 5}, + // AArch64::LDNF1SB_D_IMM_REAL - 450 + {8226, 2310, 4, 5}, + // AArch64::LDNF1SB_H_IMM_REAL - 451 + {8253, 2315, 4, 5}, + // AArch64::LDNF1SB_S_IMM_REAL - 452 + {8280, 2320, 4, 5}, + // AArch64::LDNF1SH_D_IMM_REAL - 453 + {8307, 2325, 4, 5}, + // AArch64::LDNF1SH_S_IMM_REAL - 454 + {8334, 2330, 4, 5}, + // AArch64::LDNF1SW_D_IMM_REAL - 455 + {8361, 2335, 4, 5}, + // AArch64::LDNF1W_D_IMM_REAL - 456 + {8388, 2340, 4, 5}, + // AArch64::LDNF1W_IMM_REAL - 457 + {8414, 2345, 4, 5}, + // AArch64::LDNPDi - 458 + {8440, 2350, 4, 4}, + // AArch64::LDNPQi - 459 + {8440, 2354, 4, 4}, + // AArch64::LDNPSi - 460 + {8440, 2358, 4, 4}, + // AArch64::LDNPWi - 461 + {8440, 2362, 4, 4}, + // AArch64::LDNPXi - 462 + {8440, 2366, 4, 4}, + // AArch64::LDNT1B_ZRI - 463 + {8458, 2370, 4, 7}, + // AArch64::LDNT1B_ZZR_D_REAL - 464 + {8484, 2377, 4, 5}, + // AArch64::LDNT1B_ZZR_S_REAL - 465 + {8512, 2382, 4, 5}, + // AArch64::LDNT1D_ZRI - 466 + {8540, 2387, 4, 7}, + // AArch64::LDNT1D_ZZR_D_REAL - 467 + {8566, 2394, 4, 5}, + // AArch64::LDNT1H_ZRI - 468 + {8594, 2399, 4, 7}, + // AArch64::LDNT1H_ZZR_D_REAL - 469 + {8620, 2406, 4, 5}, + // AArch64::LDNT1H_ZZR_S_REAL - 470 + {8648, 2411, 4, 5}, + // AArch64::LDNT1SB_ZZR_D_REAL - 471 + {8676, 2416, 4, 5}, + // AArch64::LDNT1SB_ZZR_S_REAL - 472 + {8705, 2421, 4, 5}, + // AArch64::LDNT1SH_ZZR_D_REAL - 473 + {8734, 2426, 4, 5}, + // AArch64::LDNT1SH_ZZR_S_REAL - 474 + {8763, 2431, 4, 5}, + // AArch64::LDNT1SW_ZZR_D_REAL - 475 + {8792, 2436, 4, 5}, + // AArch64::LDNT1W_ZRI - 476 + {8821, 2441, 4, 7}, + // AArch64::LDNT1W_ZZR_D_REAL - 477 + {8847, 2448, 4, 5}, + // AArch64::LDNT1W_ZZR_S_REAL - 478 + {8875, 2453, 4, 5}, + // AArch64::LDPDi - 479 + {8903, 2458, 4, 4}, + // AArch64::LDPQi - 480 + {8903, 2462, 4, 4}, + // AArch64::LDPSWi - 481 + {8920, 2466, 4, 4}, + // AArch64::LDPSi - 482 + {8903, 2470, 4, 4}, + // AArch64::LDPWi - 483 + {8903, 2474, 4, 4}, + // AArch64::LDPXi - 484 + {8903, 2478, 4, 4}, + // AArch64::LDRAAindexed - 485 + {8939, 2482, 3, 4}, + // AArch64::LDRABindexed - 486 + {8954, 2486, 3, 4}, + // AArch64::LDRBBroX - 487 + {8969, 2490, 5, 5}, + // AArch64::LDRBBui - 488 + {8987, 2495, 3, 3}, + // AArch64::LDRBroX - 489 + {9001, 2498, 5, 5}, + // AArch64::LDRBui - 490 + {9018, 2503, 3, 3}, + // AArch64::LDRDroX - 491 + {9001, 2506, 5, 5}, + // AArch64::LDRDui - 492 + {9018, 2511, 3, 3}, + // AArch64::LDRHHroX - 493 + {9031, 2514, 5, 5}, + // AArch64::LDRHHui - 494 + {9049, 2519, 3, 3}, + // AArch64::LDRHroX - 495 + {9001, 2522, 5, 5}, + // AArch64::LDRHui - 496 + {9018, 2527, 3, 3}, + // AArch64::LDRQroX - 497 + {9001, 2530, 5, 5}, + // AArch64::LDRQui - 498 + {9018, 2535, 3, 3}, + // AArch64::LDRSBWroX - 499 + {9063, 2538, 5, 5}, + // AArch64::LDRSBWui - 500 + {9082, 2543, 3, 3}, + // AArch64::LDRSBXroX - 501 + {9063, 2546, 5, 5}, + // AArch64::LDRSBXui - 502 + {9082, 2551, 3, 3}, + // AArch64::LDRSHWroX - 503 + {9097, 2554, 5, 5}, + // AArch64::LDRSHWui - 504 + {9116, 2559, 3, 3}, + // AArch64::LDRSHXroX - 505 + {9097, 2562, 5, 5}, + // AArch64::LDRSHXui - 506 + {9116, 2567, 3, 3}, + // AArch64::LDRSWroX - 507 + {9131, 2570, 5, 5}, + // AArch64::LDRSWui - 508 + {9150, 2575, 3, 3}, + // AArch64::LDRSroX - 509 + {9001, 2578, 5, 5}, + // AArch64::LDRSui - 510 + {9018, 2583, 3, 3}, + // AArch64::LDRWroX - 511 + {9001, 2586, 5, 5}, + // AArch64::LDRWui - 512 + {9018, 2591, 3, 3}, + // AArch64::LDRXroX - 513 + {9001, 2594, 5, 5}, + // AArch64::LDRXui - 514 + {9018, 2599, 3, 3}, + // AArch64::LDR_PXI - 515 + {9165, 2602, 3, 6}, + // AArch64::LDR_ZA - 516 + {9180, 2608, 5, 6}, + // AArch64::LDR_ZXI - 517 + {9165, 2614, 3, 6}, + // AArch64::LDSETB - 518 + {9205, 2620, 3, 4}, + // AArch64::LDSETH - 519 + {9221, 2624, 3, 4}, + // AArch64::LDSETLB - 520 + {9237, 2628, 3, 4}, + // AArch64::LDSETLH - 521 + {9254, 2632, 3, 4}, + // AArch64::LDSETLW - 522 + {9271, 2636, 3, 4}, + // AArch64::LDSETLX - 523 + {9271, 2640, 3, 4}, + // AArch64::LDSETW - 524 + {9287, 2644, 3, 4}, + // AArch64::LDSETX - 525 + {9287, 2648, 3, 4}, + // AArch64::LDSMAXB - 526 + {9302, 2652, 3, 4}, + // AArch64::LDSMAXH - 527 + {9319, 2656, 3, 4}, + // AArch64::LDSMAXLB - 528 + {9336, 2660, 3, 4}, + // AArch64::LDSMAXLH - 529 + {9354, 2664, 3, 4}, + // AArch64::LDSMAXLW - 530 + {9372, 2668, 3, 4}, + // AArch64::LDSMAXLX - 531 + {9372, 2672, 3, 4}, + // AArch64::LDSMAXW - 532 + {9389, 2676, 3, 4}, + // AArch64::LDSMAXX - 533 + {9389, 2680, 3, 4}, + // AArch64::LDSMINB - 534 + {9405, 2684, 3, 4}, + // AArch64::LDSMINH - 535 + {9422, 2688, 3, 4}, + // AArch64::LDSMINLB - 536 + {9439, 2692, 3, 4}, + // AArch64::LDSMINLH - 537 + {9457, 2696, 3, 4}, + // AArch64::LDSMINLW - 538 + {9475, 2700, 3, 4}, + // AArch64::LDSMINLX - 539 + {9475, 2704, 3, 4}, + // AArch64::LDSMINW - 540 + {9492, 2708, 3, 4}, + // AArch64::LDSMINX - 541 + {9492, 2712, 3, 4}, + // AArch64::LDTRBi - 542 + {9508, 2716, 3, 3}, + // AArch64::LDTRHi - 543 + {9523, 2719, 3, 3}, + // AArch64::LDTRSBWi - 544 + {9538, 2722, 3, 3}, + // AArch64::LDTRSBXi - 545 + {9538, 2725, 3, 3}, + // AArch64::LDTRSHWi - 546 + {9554, 2728, 3, 3}, + // AArch64::LDTRSHXi - 547 + {9554, 2731, 3, 3}, + // AArch64::LDTRSWi - 548 + {9570, 2734, 3, 3}, + // AArch64::LDTRWi - 549 + {9586, 2737, 3, 3}, + // AArch64::LDTRXi - 550 + {9586, 2740, 3, 3}, + // AArch64::LDUMAXB - 551 + {9600, 2743, 3, 4}, + // AArch64::LDUMAXH - 552 + {9617, 2747, 3, 4}, + // AArch64::LDUMAXLB - 553 + {9634, 2751, 3, 4}, + // AArch64::LDUMAXLH - 554 + {9652, 2755, 3, 4}, + // AArch64::LDUMAXLW - 555 + {9670, 2759, 3, 4}, + // AArch64::LDUMAXLX - 556 + {9670, 2763, 3, 4}, + // AArch64::LDUMAXW - 557 + {9687, 2767, 3, 4}, + // AArch64::LDUMAXX - 558 + {9687, 2771, 3, 4}, + // AArch64::LDUMINB - 559 + {9703, 2775, 3, 4}, + // AArch64::LDUMINH - 560 + {9720, 2779, 3, 4}, + // AArch64::LDUMINLB - 561 + {9737, 2783, 3, 4}, + // AArch64::LDUMINLH - 562 + {9755, 2787, 3, 4}, + // AArch64::LDUMINLW - 563 + {9773, 2791, 3, 4}, + // AArch64::LDUMINLX - 564 + {9773, 2795, 3, 4}, + // AArch64::LDUMINW - 565 + {9790, 2799, 3, 4}, + // AArch64::LDUMINX - 566 + {9790, 2803, 3, 4}, + // AArch64::LDURBBi - 567 + {9806, 2807, 3, 3}, + // AArch64::LDURBi - 568 + {9821, 2810, 3, 3}, + // AArch64::LDURDi - 569 + {9821, 2813, 3, 3}, + // AArch64::LDURHHi - 570 + {9835, 2816, 3, 3}, + // AArch64::LDURHi - 571 + {9821, 2819, 3, 3}, + // AArch64::LDURQi - 572 + {9821, 2822, 3, 3}, + // AArch64::LDURSBWi - 573 + {9850, 2825, 3, 3}, + // AArch64::LDURSBXi - 574 + {9850, 2828, 3, 3}, + // AArch64::LDURSHWi - 575 + {9866, 2831, 3, 3}, + // AArch64::LDURSHXi - 576 + {9866, 2834, 3, 3}, + // AArch64::LDURSWi - 577 + {9882, 2837, 3, 3}, + // AArch64::LDURSi - 578 + {9821, 2840, 3, 3}, + // AArch64::LDURWi - 579 + {9821, 2843, 3, 3}, + // AArch64::LDURXi - 580 + {9821, 2846, 3, 3}, + // AArch64::MADDWrrr - 581 + {9898, 2849, 4, 4}, + // AArch64::MADDXrrr - 582 + {9898, 2853, 4, 4}, + // AArch64::MSRpstatesvcrImm1 - 583 + {9913, 2857, 2, 3}, + {9921, 2860, 2, 3}, + {9932, 2863, 2, 3}, + {9943, 2866, 2, 3}, + {9950, 2869, 2, 3}, + {9960, 2872, 2, 3}, + // AArch64::MSUBWrrr - 589 + {9970, 2875, 4, 4}, + // AArch64::MSUBXrrr - 590 + {9970, 2879, 4, 4}, + // AArch64::NOTv16i8 - 591 + {9986, 2883, 2, 2}, + // AArch64::NOTv8i8 - 592 + {10009, 2885, 2, 2}, + // AArch64::ORNWrs - 593 + {10030, 2887, 4, 4}, + {10041, 2891, 4, 3}, + {10056, 2894, 4, 4}, + // AArch64::ORNXrs - 596 + {10030, 2898, 4, 4}, + {10041, 2902, 4, 3}, + {10056, 2905, 4, 4}, + // AArch64::ORRS_PPzPP - 599 + {10071, 2909, 4, 7}, + // AArch64::ORRWrs - 600 + {10087, 2916, 4, 4}, + {10098, 2920, 4, 4}, + // AArch64::ORRXrs - 602 + {10087, 2924, 4, 4}, + {10098, 2928, 4, 4}, + // AArch64::ORR_PPzPP - 604 + {10113, 2932, 4, 7}, + // AArch64::ORR_ZI - 605 + {10128, 2939, 3, 6}, + {10149, 2945, 3, 6}, + {10170, 2951, 3, 6}, + // AArch64::ORR_ZZZ - 608 + {10191, 2957, 3, 6}, + // AArch64::ORRv16i8 - 609 + {10206, 2963, 3, 3}, + // AArch64::ORRv8i8 - 610 + {10229, 2966, 3, 3}, + // AArch64::PACIA1716 - 611 + {10250, 2969, 0, 1}, + // AArch64::PACIASP - 612 + {10260, 2970, 0, 1}, + // AArch64::PACIAZ - 613 + {10268, 2971, 0, 1}, + // AArch64::PACIB1716 - 614 + {10275, 2972, 0, 1}, + // AArch64::PACIBSP - 615 + {10285, 2973, 0, 1}, + // AArch64::PACIBZ - 616 + {10293, 2974, 0, 1}, + // AArch64::PRFB_D_PZI - 617 + {10300, 2975, 4, 5}, + // AArch64::PRFB_PRI - 618 + {10324, 2980, 4, 7}, + // AArch64::PRFB_S_PZI - 619 + {10346, 2987, 4, 5}, + // AArch64::PRFD_D_PZI - 620 + {10370, 2992, 4, 5}, + // AArch64::PRFD_PRI - 621 + {10394, 2997, 4, 7}, + // AArch64::PRFD_S_PZI - 622 + {10416, 3004, 4, 5}, + // AArch64::PRFH_D_PZI - 623 + {10440, 3009, 4, 5}, + // AArch64::PRFH_PRI - 624 + {10464, 3014, 4, 7}, + // AArch64::PRFH_S_PZI - 625 + {10486, 3021, 4, 5}, + // AArch64::PRFMroX - 626 + {10510, 3026, 5, 5}, + // AArch64::PRFMui - 627 + {10530, 3031, 3, 3}, + // AArch64::PRFUMi - 628 + {10546, 3034, 3, 3}, + // AArch64::PRFW_D_PZI - 629 + {10563, 3037, 4, 5}, + // AArch64::PRFW_PRI - 630 + {10587, 3042, 4, 7}, + // AArch64::PRFW_S_PZI - 631 + {10609, 3049, 4, 5}, + // AArch64::PTRUES_B - 632 + {10633, 3054, 2, 5}, + // AArch64::PTRUES_D - 633 + {10645, 3059, 2, 5}, + // AArch64::PTRUES_H - 634 + {10657, 3064, 2, 5}, + // AArch64::PTRUES_S - 635 + {10669, 3069, 2, 5}, + // AArch64::PTRUE_B - 636 + {10681, 3074, 2, 5}, + // AArch64::PTRUE_D - 637 + {10692, 3079, 2, 5}, + // AArch64::PTRUE_H - 638 + {10703, 3084, 2, 5}, + // AArch64::PTRUE_S - 639 + {10714, 3089, 2, 5}, + // AArch64::RET - 640 + {10725, 3094, 1, 1}, + // AArch64::SBCSWr - 641 + {10729, 3095, 3, 3}, + // AArch64::SBCSXr - 642 + {10729, 3098, 3, 3}, + // AArch64::SBCWr - 643 + {10741, 3101, 3, 3}, + // AArch64::SBCXr - 644 + {10741, 3104, 3, 3}, + // AArch64::SBFMWri - 645 + {10752, 3107, 4, 4}, + {10767, 3111, 4, 4}, + {10779, 3115, 4, 4}, + // AArch64::SBFMXri - 648 + {10752, 3119, 4, 4}, + {10767, 3123, 4, 4}, + {10779, 3127, 4, 4}, + {10791, 3131, 4, 4}, + // AArch64::SEL_PPPP - 652 + {10803, 3135, 4, 7}, + // AArch64::SEL_ZPZZ_B - 653 + {10803, 3142, 4, 7}, + // AArch64::SEL_ZPZZ_D - 654 + {10826, 3149, 4, 7}, + // AArch64::SEL_ZPZZ_H - 655 + {10849, 3156, 4, 7}, + // AArch64::SEL_ZPZZ_S - 656 + {10872, 3163, 4, 7}, + // AArch64::SMADDLrrr - 657 + {10895, 3170, 4, 4}, + // AArch64::SMSUBLrrr - 658 + {10912, 3174, 4, 4}, + // AArch64::SQDECB_XPiI - 659 + {10930, 3178, 4, 7}, + {10940, 3185, 4, 7}, + // AArch64::SQDECB_XPiWdI - 661 + {10956, 3192, 4, 7}, + {10972, 3199, 4, 7}, + // AArch64::SQDECD_XPiI - 663 + {10994, 3206, 4, 7}, + {11004, 3213, 4, 7}, + // AArch64::SQDECD_XPiWdI - 665 + {11020, 3220, 4, 7}, + {11036, 3227, 4, 7}, + // AArch64::SQDECD_ZPiI - 667 + {11058, 3234, 4, 7}, + {11070, 3241, 4, 7}, + // AArch64::SQDECH_XPiI - 669 + {11088, 3248, 4, 7}, + {11098, 3255, 4, 7}, + // AArch64::SQDECH_XPiWdI - 671 + {11114, 3262, 4, 7}, + {11130, 3269, 4, 7}, + // AArch64::SQDECH_ZPiI - 673 + {11152, 3276, 4, 7}, + {11164, 3283, 4, 7}, + // AArch64::SQDECW_XPiI - 675 + {11182, 3290, 4, 7}, + {11192, 3297, 4, 7}, + // AArch64::SQDECW_XPiWdI - 677 + {11208, 3304, 4, 7}, + {11224, 3311, 4, 7}, + // AArch64::SQDECW_ZPiI - 679 + {11246, 3318, 4, 7}, + {11258, 3325, 4, 7}, + // AArch64::SQINCB_XPiI - 681 + {11276, 3332, 4, 7}, + {11286, 3339, 4, 7}, + // AArch64::SQINCB_XPiWdI - 683 + {11302, 3346, 4, 7}, + {11318, 3353, 4, 7}, + // AArch64::SQINCD_XPiI - 685 + {11340, 3360, 4, 7}, + {11350, 3367, 4, 7}, + // AArch64::SQINCD_XPiWdI - 687 + {11366, 3374, 4, 7}, + {11382, 3381, 4, 7}, + // AArch64::SQINCD_ZPiI - 689 + {11404, 3388, 4, 7}, + {11416, 3395, 4, 7}, + // AArch64::SQINCH_XPiI - 691 + {11434, 3402, 4, 7}, + {11444, 3409, 4, 7}, + // AArch64::SQINCH_XPiWdI - 693 + {11460, 3416, 4, 7}, + {11476, 3423, 4, 7}, + // AArch64::SQINCH_ZPiI - 695 + {11498, 3430, 4, 7}, + {11510, 3437, 4, 7}, + // AArch64::SQINCW_XPiI - 697 + {11528, 3444, 4, 7}, + {11538, 3451, 4, 7}, + // AArch64::SQINCW_XPiWdI - 699 + {11554, 3458, 4, 7}, + {11570, 3465, 4, 7}, + // AArch64::SQINCW_ZPiI - 701 + {11592, 3472, 4, 7}, + {11604, 3479, 4, 7}, + // AArch64::SST1B_D_IMM - 703 + {11622, 3486, 4, 5}, + // AArch64::SST1B_S_IMM - 704 + {11646, 3491, 4, 5}, + // AArch64::SST1D_IMM - 705 + {11670, 3496, 4, 5}, + // AArch64::SST1H_D_IMM - 706 + {11694, 3501, 4, 5}, + // AArch64::SST1H_S_IMM - 707 + {11718, 3506, 4, 5}, + // AArch64::SST1W_D_IMM - 708 + {11742, 3511, 4, 5}, + // AArch64::SST1W_IMM - 709 + {11766, 3516, 4, 5}, + // AArch64::ST1B_D_IMM - 710 + {11790, 3521, 4, 7}, + // AArch64::ST1B_H_IMM - 711 + {11812, 3528, 4, 7}, + // AArch64::ST1B_IMM - 712 + {11834, 3535, 4, 7}, + // AArch64::ST1B_S_IMM - 713 + {11856, 3542, 4, 7}, + // AArch64::ST1D_IMM - 714 + {11878, 3549, 4, 7}, + // AArch64::ST1Fourv16b_POST - 715 + {11900, 3556, 4, 5}, + // AArch64::ST1Fourv1d_POST - 716 + {11920, 3561, 4, 5}, + // AArch64::ST1Fourv2d_POST - 717 + {11940, 3566, 4, 5}, + // AArch64::ST1Fourv2s_POST - 718 + {11960, 3571, 4, 5}, + // AArch64::ST1Fourv4h_POST - 719 + {11980, 3576, 4, 5}, + // AArch64::ST1Fourv4s_POST - 720 + {12000, 3581, 4, 5}, + // AArch64::ST1Fourv8b_POST - 721 + {12020, 3586, 4, 5}, + // AArch64::ST1Fourv8h_POST - 722 + {12040, 3591, 4, 5}, + // AArch64::ST1H_D_IMM - 723 + {12060, 3596, 4, 7}, + // AArch64::ST1H_IMM - 724 + {12082, 3603, 4, 7}, + // AArch64::ST1H_S_IMM - 725 + {12104, 3610, 4, 7}, + // AArch64::ST1Onev16b_POST - 726 + {12126, 3617, 4, 5}, + // AArch64::ST1Onev1d_POST - 727 + {12146, 3622, 4, 5}, + // AArch64::ST1Onev2d_POST - 728 + {12165, 3627, 4, 5}, + // AArch64::ST1Onev2s_POST - 729 + {12185, 3632, 4, 5}, + // AArch64::ST1Onev4h_POST - 730 + {12204, 3637, 4, 5}, + // AArch64::ST1Onev4s_POST - 731 + {12223, 3642, 4, 5}, + // AArch64::ST1Onev8b_POST - 732 + {12243, 3647, 4, 5}, + // AArch64::ST1Onev8h_POST - 733 + {12262, 3652, 4, 5}, + // AArch64::ST1Threev16b_POST - 734 + {12282, 3657, 4, 5}, + // AArch64::ST1Threev1d_POST - 735 + {12302, 3662, 4, 5}, + // AArch64::ST1Threev2d_POST - 736 + {12322, 3667, 4, 5}, + // AArch64::ST1Threev2s_POST - 737 + {12342, 3672, 4, 5}, + // AArch64::ST1Threev4h_POST - 738 + {12362, 3677, 4, 5}, + // AArch64::ST1Threev4s_POST - 739 + {12382, 3682, 4, 5}, + // AArch64::ST1Threev8b_POST - 740 + {12402, 3687, 4, 5}, + // AArch64::ST1Threev8h_POST - 741 + {12422, 3692, 4, 5}, + // AArch64::ST1Twov16b_POST - 742 + {12442, 3697, 4, 5}, + // AArch64::ST1Twov1d_POST - 743 + {12462, 3702, 4, 5}, + // AArch64::ST1Twov2d_POST - 744 + {12482, 3707, 4, 5}, + // AArch64::ST1Twov2s_POST - 745 + {12502, 3712, 4, 5}, + // AArch64::ST1Twov4h_POST - 746 + {12522, 3717, 4, 5}, + // AArch64::ST1Twov4s_POST - 747 + {12542, 3722, 4, 5}, + // AArch64::ST1Twov8b_POST - 748 + {12562, 3727, 4, 5}, + // AArch64::ST1Twov8h_POST - 749 + {12582, 3732, 4, 5}, + // AArch64::ST1W_D_IMM - 750 + {12602, 3737, 4, 7}, + // AArch64::ST1W_IMM - 751 + {12624, 3744, 4, 7}, + // AArch64::ST1_MXIPXX_H_B - 752 + {12646, 3751, 6, 7}, + // AArch64::ST1_MXIPXX_H_D - 753 + {12680, 3758, 6, 7}, + // AArch64::ST1_MXIPXX_H_H - 754 + {12714, 3765, 6, 7}, + // AArch64::ST1_MXIPXX_H_Q - 755 + {12748, 3772, 6, 7}, + // AArch64::ST1_MXIPXX_H_S - 756 + {12782, 3779, 6, 7}, + // AArch64::ST1_MXIPXX_V_B - 757 + {12816, 3786, 6, 7}, + // AArch64::ST1_MXIPXX_V_D - 758 + {12850, 3793, 6, 7}, + // AArch64::ST1_MXIPXX_V_H - 759 + {12884, 3800, 6, 7}, + // AArch64::ST1_MXIPXX_V_Q - 760 + {12918, 3807, 6, 7}, + // AArch64::ST1_MXIPXX_V_S - 761 + {12952, 3814, 6, 7}, + // AArch64::ST1i16_POST - 762 + {12986, 3821, 5, 6}, + // AArch64::ST1i32_POST - 763 + {13009, 3827, 5, 6}, + // AArch64::ST1i64_POST - 764 + {13032, 3833, 5, 6}, + // AArch64::ST1i8_POST - 765 + {13055, 3839, 5, 6}, + // AArch64::ST2B_IMM - 766 + {13078, 3845, 4, 7}, + // AArch64::ST2D_IMM - 767 + {13100, 3852, 4, 7}, + // AArch64::ST2GOffset - 768 + {13122, 3859, 3, 4}, + // AArch64::ST2H_IMM - 769 + {13136, 3863, 4, 7}, + // AArch64::ST2Twov16b_POST - 770 + {13158, 3870, 4, 5}, + // AArch64::ST2Twov2d_POST - 771 + {13178, 3875, 4, 5}, + // AArch64::ST2Twov2s_POST - 772 + {13198, 3880, 4, 5}, + // AArch64::ST2Twov4h_POST - 773 + {13218, 3885, 4, 5}, + // AArch64::ST2Twov4s_POST - 774 + {13238, 3890, 4, 5}, + // AArch64::ST2Twov8b_POST - 775 + {13258, 3895, 4, 5}, + // AArch64::ST2Twov8h_POST - 776 + {13278, 3900, 4, 5}, + // AArch64::ST2W_IMM - 777 + {13298, 3905, 4, 7}, + // AArch64::ST2i16_POST - 778 + {13320, 3912, 5, 6}, + // AArch64::ST2i32_POST - 779 + {13343, 3918, 5, 6}, + // AArch64::ST2i64_POST - 780 + {13366, 3924, 5, 6}, + // AArch64::ST2i8_POST - 781 + {13390, 3930, 5, 6}, + // AArch64::ST3B_IMM - 782 + {13413, 3936, 4, 7}, + // AArch64::ST3D_IMM - 783 + {13435, 3943, 4, 7}, + // AArch64::ST3H_IMM - 784 + {13457, 3950, 4, 7}, + // AArch64::ST3Threev16b_POST - 785 + {13479, 3957, 4, 5}, + // AArch64::ST3Threev2d_POST - 786 + {13499, 3962, 4, 5}, + // AArch64::ST3Threev2s_POST - 787 + {13519, 3967, 4, 5}, + // AArch64::ST3Threev4h_POST - 788 + {13539, 3972, 4, 5}, + // AArch64::ST3Threev4s_POST - 789 + {13559, 3977, 4, 5}, + // AArch64::ST3Threev8b_POST - 790 + {13579, 3982, 4, 5}, + // AArch64::ST3Threev8h_POST - 791 + {13599, 3987, 4, 5}, + // AArch64::ST3W_IMM - 792 + {13619, 3992, 4, 7}, + // AArch64::ST3i16_POST - 793 + {13641, 3999, 5, 6}, + // AArch64::ST3i32_POST - 794 + {13664, 4005, 5, 6}, + // AArch64::ST3i64_POST - 795 + {13688, 4011, 5, 6}, + // AArch64::ST3i8_POST - 796 + {13712, 4017, 5, 6}, + // AArch64::ST4B_IMM - 797 + {13735, 4023, 4, 7}, + // AArch64::ST4D_IMM - 798 + {13757, 4030, 4, 7}, + // AArch64::ST4Fourv16b_POST - 799 + {13779, 4037, 4, 5}, + // AArch64::ST4Fourv2d_POST - 800 + {13799, 4042, 4, 5}, + // AArch64::ST4Fourv2s_POST - 801 + {13819, 4047, 4, 5}, + // AArch64::ST4Fourv4h_POST - 802 + {13839, 4052, 4, 5}, + // AArch64::ST4Fourv4s_POST - 803 + {13859, 4057, 4, 5}, + // AArch64::ST4Fourv8b_POST - 804 + {13879, 4062, 4, 5}, + // AArch64::ST4Fourv8h_POST - 805 + {13899, 4067, 4, 5}, + // AArch64::ST4H_IMM - 806 + {13919, 4072, 4, 7}, + // AArch64::ST4W_IMM - 807 + {13941, 4079, 4, 7}, + // AArch64::ST4i16_POST - 808 + {13963, 4086, 5, 6}, + // AArch64::ST4i32_POST - 809 + {13986, 4092, 5, 6}, + // AArch64::ST4i64_POST - 810 + {14010, 4098, 5, 6}, + // AArch64::ST4i8_POST - 811 + {14034, 4104, 5, 6}, + // AArch64::STGOffset - 812 + {14057, 4110, 3, 4}, + // AArch64::STGPi - 813 + {14070, 4114, 4, 5}, + // AArch64::STLURBi - 814 + {14088, 4119, 3, 4}, + // AArch64::STLURHi - 815 + {14104, 4123, 3, 4}, + // AArch64::STLURWi - 816 + {14120, 4127, 3, 4}, + // AArch64::STLURXi - 817 + {14120, 4131, 3, 4}, + // AArch64::STNPDi - 818 + {14135, 4135, 4, 4}, + // AArch64::STNPQi - 819 + {14135, 4139, 4, 4}, + // AArch64::STNPSi - 820 + {14135, 4143, 4, 4}, + // AArch64::STNPWi - 821 + {14135, 4147, 4, 4}, + // AArch64::STNPXi - 822 + {14135, 4151, 4, 4}, + // AArch64::STNT1B_ZRI - 823 + {14153, 4155, 4, 7}, + // AArch64::STNT1B_ZZR_D_REAL - 824 + {14177, 4162, 4, 5}, + // AArch64::STNT1B_ZZR_S_REAL - 825 + {14203, 4167, 4, 5}, + // AArch64::STNT1D_ZRI - 826 + {14229, 4172, 4, 7}, + // AArch64::STNT1D_ZZR_D_REAL - 827 + {14253, 4179, 4, 5}, + // AArch64::STNT1H_ZRI - 828 + {14279, 4184, 4, 7}, + // AArch64::STNT1H_ZZR_D_REAL - 829 + {14303, 4191, 4, 5}, + // AArch64::STNT1H_ZZR_S_REAL - 830 + {14329, 4196, 4, 5}, + // AArch64::STNT1W_ZRI - 831 + {14355, 4201, 4, 7}, + // AArch64::STNT1W_ZZR_D_REAL - 832 + {14379, 4208, 4, 5}, + // AArch64::STNT1W_ZZR_S_REAL - 833 + {14405, 4213, 4, 5}, + // AArch64::STPDi - 834 + {14431, 4218, 4, 4}, + // AArch64::STPQi - 835 + {14431, 4222, 4, 4}, + // AArch64::STPSi - 836 + {14431, 4226, 4, 4}, + // AArch64::STPWi - 837 + {14431, 4230, 4, 4}, + // AArch64::STPXi - 838 + {14431, 4234, 4, 4}, + // AArch64::STRBBroX - 839 + {14448, 4238, 5, 5}, + // AArch64::STRBBui - 840 + {14466, 4243, 3, 3}, + // AArch64::STRBroX - 841 + {14480, 4246, 5, 5}, + // AArch64::STRBui - 842 + {14497, 4251, 3, 3}, + // AArch64::STRDroX - 843 + {14480, 4254, 5, 5}, + // AArch64::STRDui - 844 + {14497, 4259, 3, 3}, + // AArch64::STRHHroX - 845 + {14510, 4262, 5, 5}, + // AArch64::STRHHui - 846 + {14528, 4267, 3, 3}, + // AArch64::STRHroX - 847 + {14480, 4270, 5, 5}, + // AArch64::STRHui - 848 + {14497, 4275, 3, 3}, + // AArch64::STRQroX - 849 + {14480, 4278, 5, 5}, + // AArch64::STRQui - 850 + {14497, 4283, 3, 3}, + // AArch64::STRSroX - 851 + {14480, 4286, 5, 5}, + // AArch64::STRSui - 852 + {14497, 4291, 3, 3}, + // AArch64::STRWroX - 853 + {14480, 4294, 5, 5}, + // AArch64::STRWui - 854 + {14497, 4299, 3, 3}, + // AArch64::STRXroX - 855 + {14480, 4302, 5, 5}, + // AArch64::STRXui - 856 + {14497, 4307, 3, 3}, + // AArch64::STR_PXI - 857 + {14542, 4310, 3, 6}, + // AArch64::STR_ZA - 858 + {14557, 4316, 5, 6}, + // AArch64::STR_ZXI - 859 + {14542, 4322, 3, 6}, + // AArch64::STTRBi - 860 + {14582, 4328, 3, 3}, + // AArch64::STTRHi - 861 + {14597, 4331, 3, 3}, + // AArch64::STTRWi - 862 + {14612, 4334, 3, 3}, + // AArch64::STTRXi - 863 + {14612, 4337, 3, 3}, + // AArch64::STURBBi - 864 + {14626, 4340, 3, 3}, + // AArch64::STURBi - 865 + {14641, 4343, 3, 3}, + // AArch64::STURDi - 866 + {14641, 4346, 3, 3}, + // AArch64::STURHHi - 867 + {14655, 4349, 3, 3}, + // AArch64::STURHi - 868 + {14641, 4352, 3, 3}, + // AArch64::STURQi - 869 + {14641, 4355, 3, 3}, + // AArch64::STURSi - 870 + {14641, 4358, 3, 3}, + // AArch64::STURWi - 871 + {14641, 4361, 3, 3}, + // AArch64::STURXi - 872 + {14641, 4364, 3, 3}, + // AArch64::STZ2GOffset - 873 + {14670, 4367, 3, 4}, + // AArch64::STZGOffset - 874 + {14685, 4371, 3, 4}, + // AArch64::SUBSWri - 875 + {14699, 4375, 4, 2}, + // AArch64::SUBSWrs - 876 + {14712, 4377, 4, 4}, + {14723, 4381, 4, 3}, + {14738, 4384, 4, 4}, + {14750, 4388, 4, 3}, + {14766, 4391, 4, 4}, + // AArch64::SUBSWrx - 881 + {14712, 4395, 4, 4}, + {14782, 4399, 4, 3}, + {14766, 4402, 4, 4}, + // AArch64::SUBSXri - 884 + {14699, 4406, 4, 2}, + // AArch64::SUBSXrs - 885 + {14712, 4408, 4, 4}, + {14723, 4412, 4, 3}, + {14738, 4415, 4, 4}, + {14750, 4419, 4, 3}, + {14766, 4422, 4, 4}, + // AArch64::SUBSXrx - 890 + {14782, 4426, 4, 3}, + // AArch64::SUBSXrx64 - 891 + {14712, 4429, 4, 4}, + {14782, 4433, 4, 3}, + {14766, 4436, 4, 4}, + // AArch64::SUBWrs - 894 + {14797, 4440, 4, 4}, + {14808, 4444, 4, 3}, + {14823, 4447, 4, 4}, + // AArch64::SUBWrx - 897 + {14823, 4451, 4, 4}, + {14823, 4455, 4, 4}, + // AArch64::SUBXrs - 899 + {14797, 4459, 4, 4}, + {14808, 4463, 4, 3}, + {14823, 4466, 4, 4}, + // AArch64::SUBXrx64 - 902 + {14823, 4470, 4, 4}, + {14823, 4474, 4, 4}, + // AArch64::SYSxt - 904 + {14838, 4478, 5, 5}, + // AArch64::UBFMWri - 905 + {14861, 4483, 4, 4}, + {14876, 4487, 4, 4}, + {14888, 4491, 4, 4}, + // AArch64::UBFMXri - 908 + {14861, 4495, 4, 4}, + {14876, 4499, 4, 4}, + {14888, 4503, 4, 4}, + {14900, 4507, 4, 4}, + // AArch64::UMADDLrrr - 912 + {14912, 4511, 4, 4}, + // AArch64::UMOVvi32 - 913 + {14929, 4515, 3, 3}, + // AArch64::UMOVvi32_idx0 - 914 + {14929, 4518, 3, 5}, + // AArch64::UMOVvi64 - 915 + {14948, 4523, 3, 3}, + // AArch64::UMOVvi64_idx0 - 916 + {14948, 4526, 3, 5}, + // AArch64::UMSUBLrrr - 917 + {14967, 4531, 4, 4}, + // AArch64::UQDECB_WPiI - 918 + {14985, 4535, 4, 7}, + {14995, 4542, 4, 7}, + // AArch64::UQDECB_XPiI - 920 + {14985, 4549, 4, 7}, + {14995, 4556, 4, 7}, + // AArch64::UQDECD_WPiI - 922 + {15011, 4563, 4, 7}, + {15021, 4570, 4, 7}, + // AArch64::UQDECD_XPiI - 924 + {15011, 4577, 4, 7}, + {15021, 4584, 4, 7}, + // AArch64::UQDECD_ZPiI - 926 + {15037, 4591, 4, 7}, + {15049, 4598, 4, 7}, + // AArch64::UQDECH_WPiI - 928 + {15067, 4605, 4, 7}, + {15077, 4612, 4, 7}, + // AArch64::UQDECH_XPiI - 930 + {15067, 4619, 4, 7}, + {15077, 4626, 4, 7}, + // AArch64::UQDECH_ZPiI - 932 + {15093, 4633, 4, 7}, + {15105, 4640, 4, 7}, + // AArch64::UQDECW_WPiI - 934 + {15123, 4647, 4, 7}, + {15133, 4654, 4, 7}, + // AArch64::UQDECW_XPiI - 936 + {15123, 4661, 4, 7}, + {15133, 4668, 4, 7}, + // AArch64::UQDECW_ZPiI - 938 + {15149, 4675, 4, 7}, + {15161, 4682, 4, 7}, + // AArch64::UQINCB_WPiI - 940 + {15179, 4689, 4, 7}, + {15189, 4696, 4, 7}, + // AArch64::UQINCB_XPiI - 942 + {15179, 4703, 4, 7}, + {15189, 4710, 4, 7}, + // AArch64::UQINCD_WPiI - 944 + {15205, 4717, 4, 7}, + {15215, 4724, 4, 7}, + // AArch64::UQINCD_XPiI - 946 + {15205, 4731, 4, 7}, + {15215, 4738, 4, 7}, + // AArch64::UQINCD_ZPiI - 948 + {15231, 4745, 4, 7}, + {15243, 4752, 4, 7}, + // AArch64::UQINCH_WPiI - 950 + {15261, 4759, 4, 7}, + {15271, 4766, 4, 7}, + // AArch64::UQINCH_XPiI - 952 + {15261, 4773, 4, 7}, + {15271, 4780, 4, 7}, + // AArch64::UQINCH_ZPiI - 954 + {15287, 4787, 4, 7}, + {15299, 4794, 4, 7}, + // AArch64::UQINCW_WPiI - 956 + {15317, 4801, 4, 7}, + {15327, 4808, 4, 7}, + // AArch64::UQINCW_XPiI - 958 + {15317, 4815, 4, 7}, + {15327, 4822, 4, 7}, + // AArch64::UQINCW_ZPiI - 960 + {15343, 4829, 4, 7}, + {15355, 4836, 4, 7}, + // AArch64::XPACLRI - 962 + {15373, 4843, 0, 1}, + // AArch64::ZERO_M - 963 + {15381, 4844, 1, 2}, + {15391, 4846, 1, 2}, + {15404, 4848, 1, 2}, + {15417, 4850, 1, 2}, + {15430, 4852, 1, 2}, + {15443, 4854, 1, 2}, + {15456, 4856, 1, 2}, + {15469, 4858, 1, 2}, + {15488, 4860, 1, 2}, + {15507, 4862, 1, 2}, + {15526, 4864, 1, 2}, + {15545, 4866, 1, 2}, + {15570, 4868, 1, 2}, + {15595, 4870, 1, 2}, + {15620, 4872, 1, 2}, + }; + + static const AliasPatternCond Conds[] = { + // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 0 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 2 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 6 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 9 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 13 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 17 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 20 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 24 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 26 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 30 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 33 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 37 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 40 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 44 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 47 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) - 51 + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) - 55 + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 59 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 63 + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 67 + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) - 71 + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) - 75 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 79 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 83 + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 87 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 91 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 93 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) - 97 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 100 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 104 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 106 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) - 110 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 113 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 117 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_TiedReg, 2}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 124 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 128 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 132 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_TiedReg, 2}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 139 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Custom, 1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 145 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Custom, 2}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 151 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Custom, 3}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (AUTIA1716) - 157 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (AUTIASP) - 158 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (AUTIAZ) - 159 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (AUTIB1716) - 160 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (AUTIBSP) - 161 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (AUTIBZ) - 162 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 163 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 167 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 171 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 175 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (CLREX 15) - 179 + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 180 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 186 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 192 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 198 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 204 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 210 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 216 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 222 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 228 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 234 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 240 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 246 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 252 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 259 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 266 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 273 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 280 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 287 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 294 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 301 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 308 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 313 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 318 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 323 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 328 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_Custom, 4}, + // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 332 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Custom, 4}, + // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 336 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Custom, 4}, + // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 340 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Custom, 4}, + // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 344 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_Custom, 4}, + // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 348 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Custom, 4}, + // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 352 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Custom, 4}, + // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 356 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Custom, 4}, + // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 360 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Custom, 4}, + // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 364 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Custom, 4}, + // (DCPS1 0) - 368 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (DCPS2 0) - 369 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (DCPS3 0) - 370 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureEL3}, + // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 372 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 379 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 386 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 393 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 400 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 407 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 414 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 421 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 428 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 435 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 442 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 449 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 456 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 463 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DSB 0) - 470 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (DSB 4) - 471 + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (DSB { 1, 1, 0, 0 }) - 472 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, AArch64_HasV8_0rOps}, + // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 474 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Custom, 5}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 479 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Custom, 6}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 484 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Custom, 7}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 489 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Custom, 1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 494 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Custom, 2}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 499 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Custom, 3}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 504 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 508 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZI_D ZPR64:$Zd, 0, 0) - 512 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 518 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZI_H ZPR16:$Zd, 0, 0) - 522 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 528 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZI_S ZPR32:$Zd, 0, 0) - 532 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 538 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 543 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 548 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 553 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 558 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 564 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 569 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 575 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 580 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 586 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 591 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 597 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 602 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 608 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 613 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 617 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 621 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 628 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 632 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 636 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 643 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Custom, 1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 649 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Custom, 2}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 655 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Custom, 3}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (EXTRACT_ZPMXI_H_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpH8:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 661 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRACT_ZPMXI_H_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpH64:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 666 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRACT_ZPMXI_H_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpH16:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 671 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRACT_ZPMXI_H_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpH128:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 676 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRACT_ZPMXI_H_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpH32:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 681 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRACT_ZPMXI_V_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpV8:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 686 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRACT_ZPMXI_V_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpV64:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 691 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRACT_ZPMXI_V_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpV16:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 696 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRACT_ZPMXI_V_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpV128:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 701 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRACT_ZPMXI_V_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpV32:$ZAn, + // MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 706 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 711 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 714 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 717 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 723 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 729 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 735 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 739 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 743 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 747 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 752 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 757 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 762 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 767 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 772 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 777 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 782 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 787 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 792 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 797 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 802 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 807 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 812 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 817 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 822 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 827 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 832 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 837 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 842 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 847 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 852 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 857 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 862 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (HINT { 0, 0, 0 }) - 867 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (HINT { 0, 0, 1 }) - 868 + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (HINT { 0, 1, 0 }) - 869 + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (HINT { 0, 1, 1 }) - 870 + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (HINT { 1, 0, 0 }) - 871 + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (HINT { 1, 0, 1 }) - 872 + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (HINT { 1, 1, 0 }) - 873 + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (HINT { 1, 0, 0, 0, 0 }) - 874 + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, AArch64_FeatureRAS}, + // (HINT 20) - 876 + {AliasPatternCond_K_Imm, (uint32_t)20}, + // (HINT 32) - 877 + {AliasPatternCond_K_Imm, (uint32_t)32}, + {AliasPatternCond_K_Feature, AArch64_FeatureBranchTargetId}, + // (HINT btihint_op:$op) - 879 + {AliasPatternCond_K_Custom, 8}, + {AliasPatternCond_K_Feature, AArch64_FeatureBranchTargetId}, + // (HINT psbhint_op:$op) - 881 + {AliasPatternCond_K_Custom, 9}, + {AliasPatternCond_K_Feature, AArch64_FeatureSPE}, + // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 883 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 890 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 897 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 904 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 911 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 918 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 925 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 932 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 939 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 946 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 953 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 960 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 967 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 974 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (INSERT_MXIPZ_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 981 + {AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSERT_MXIPZ_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 987 + {AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSERT_MXIPZ_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 993 + {AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSERT_MXIPZ_H_Q TileVectorOpH128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 999 + {AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSERT_MXIPZ_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1005 + {AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSERT_MXIPZ_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1011 + {AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSERT_MXIPZ_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1017 + {AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSERT_MXIPZ_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1023 + {AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSERT_MXIPZ_V_Q TileVectorOpV128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1029 + {AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSERT_MXIPZ_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1035 + {AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 1041 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, + // VectorIndexH:$idx2) - 1046 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 1051 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, + // VectorIndexS:$idx2) - 1056 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 1061 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, + // VectorIndexD:$idx2) - 1066 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 1071 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, + // VectorIndexB:$idx2) - 1076 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 1081 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureMTE}, + // (ISB 15) - 1085 + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (LD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1086 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1093 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1100 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1107 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1114 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1121 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1126 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1131 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1136 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1141 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1146 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1151 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1156 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1161 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1168 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1175 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1182 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1187 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1192 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1197 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1202 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1207 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1212 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1217 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1222 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1229 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1236 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1243 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1250 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1257 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1264 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1271 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RO_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1278 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + {AliasPatternCond_K_Feature, AArch64_FeatureMatMulFP64}, + // (LD1RO_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1284 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + {AliasPatternCond_K_Feature, AArch64_FeatureMatMulFP64}, + // (LD1RO_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1290 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + {AliasPatternCond_K_Feature, AArch64_FeatureMatMulFP64}, + // (LD1RO_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1296 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + {AliasPatternCond_K_Feature, AArch64_FeatureMatMulFP64}, + // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1302 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1309 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1316 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1323 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1330 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1337 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1344 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1351 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1358 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1365 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1372 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1379 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1386 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1391 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1396 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1401 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1406 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1411 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1416 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1421 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1426 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1433 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1440 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1447 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1454 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1461 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1468 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1473 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1478 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1483 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1488 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1493 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1498 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1503 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1508 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1513 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1518 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1523 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1528 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1533 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1538 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1543 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1548 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1555 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1562 + {AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1569 + {AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1576 + {AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1583 + {AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1590 + {AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1597 + {AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1604 + {AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1611 + {AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1618 + {AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1625 + {AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - + // 1632 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - + // 1639 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - + // 1646 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - + // 1653 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1660 + {AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1667 + {AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1674 + {AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1681 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1686 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1691 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1696 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1701 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1706 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1711 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1716 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1721 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1726 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1731 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1736 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1741 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1746 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1751 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1756 + {AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - + // 1763 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - + // 1770 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - + // 1777 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - + // 1784 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1791 + {AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1798 + {AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1805 + {AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1812 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1817 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1822 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1827 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1832 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1837 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1842 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1847 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1852 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1857 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1862 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1867 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1872 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1877 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1882 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1887 + {AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - + // 1894 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - + // 1901 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - + // 1908 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - + // 1915 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1922 + {AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1929 + {AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1936 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1941 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1946 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1951 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1956 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1961 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1966 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1971 + {AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1978 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1983 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1988 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1993 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1998 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2003 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2008 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2013 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2018 + {AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - + // 2025 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - + // 2032 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - + // 2039 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - + // 2046 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2053 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2057 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2061 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2065 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2069 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2073 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2077 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2081 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2085 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2089 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2093 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2097 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2101 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2105 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2109 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2113 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 2117 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2121 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2125 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2129 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2133 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2137 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2141 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2145 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2149 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2153 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2157 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2161 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2165 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2169 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2173 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2177 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2181 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2185 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2190 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2195 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2200 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2205 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2210 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2215 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2220 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2225 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2230 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2235 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2240 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2245 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2250 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2255 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2260 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 2265 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureMTE}, + // (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2270 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2275 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2280 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2285 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2290 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2295 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2300 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2305 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2310 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2315 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2320 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2325 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2330 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2335 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2340 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2345 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 2350 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 2354 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 2358 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 2362 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 2366 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2370 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LDNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2377 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2382 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2387 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LDNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2394 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2399 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LDNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2406 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2411 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1SB_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2416 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1SB_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2421 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1SH_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2426 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1SH_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2431 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1SW_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2436 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2441 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LDNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 2448 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 2453 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 2458 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 2462 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 2466 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 2470 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 2474 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 2478 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 2482 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 2486 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2490 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 2495 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2498 + {AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2503 + {AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2506 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2511 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2514 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 2519 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2522 + {AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2527 + {AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2530 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2535 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2538 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2543 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2546 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2551 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2554 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2559 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2562 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2567 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2570 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 2575 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2578 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2583 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2586 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 2591 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2594 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 2599 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 2602 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LDR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 2608 + {AliasPatternCond_K_RegClass, AArch64_MPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 2614 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2620 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2624 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2628 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2632 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2636 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2640 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2644 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2648 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2652 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2656 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2660 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2664 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2668 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2672 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2676 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2680 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2684 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2688 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2692 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2696 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2700 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2704 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2708 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2712 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2716 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2719 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2722 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2725 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2728 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2731 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2734 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2737 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2740 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2743 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2747 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2751 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2755 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2759 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2763 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2767 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2771 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2775 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2779 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2783 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2787 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2791 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2795 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2799 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2803 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureLSE}, + // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2807 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2810 + {AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2813 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2816 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2819 + {AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2822 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2825 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2828 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2831 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2834 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2837 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2840 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 2843 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 2846 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2849 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2853 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 1 }) - 2857 + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 1 }) - 2860 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 1 }) - 2863 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 0 }) - 2866 + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 0 }) - 2869 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 0 }) - 2872 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2875 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2879 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + // (NOTv16i8 V128:$Vd, V128:$Vn) - 2883 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + // (NOTv8i8 V64:$Vd, V64:$Vn) - 2885 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) - 2887 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) - 2891 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2894 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) - 2898 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) - 2902 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2905 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2909 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) - 2916 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2920 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) - 2924 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2928 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2932 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 2939 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Custom, 1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 2945 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Custom, 2}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 2951 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Custom, 3}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 2957 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 2963 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 2966 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (PACIA1716) - 2969 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (PACIASP) - 2970 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (PACIAZ) - 2971 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (PACIB1716) - 2972 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (PACIBSP) - 2973 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (PACIBZ) - 2974 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2975 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2980 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2987 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2992 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2997 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3004 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3009 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3014 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3021 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3026 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 3031 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 3034 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3037 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3042 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3049 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 3054 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 3059 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 3064 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 3069 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 3074 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 3079 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 3084 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 3089 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (RET LR) - 3094 + {AliasPatternCond_K_Reg, AArch64_LR}, + // (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 3095 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 3098 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (SBCWr GPR32:$dst, WZR, GPR32:$src) - 3101 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (SBCXr GPR64:$dst, XZR, GPR64:$src) - 3104 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 3107 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 3111 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 3115 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 3119 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)63}, + // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 3123 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 3127 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 3131 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 3135 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 3142 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 3149 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 3156 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 3163 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3170 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3174 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3178 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3185 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3192 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - + // 3199 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3206 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3213 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3220 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - + // 3227 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3234 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3241 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3248 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3255 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3262 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - + // 3269 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3276 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3283 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3290 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3297 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3304 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - + // 3311 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3318 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3325 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3332 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3339 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3346 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - + // 3353 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3360 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3367 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3374 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - + // 3381 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3388 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3395 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3402 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3409 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3416 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - + // 3423 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3430 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3437 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3444 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3451 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 3458 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - + // 3465 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3472 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3479 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3486 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3491 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3496 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3501 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3506 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 3511 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 3516 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE}, + // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3521 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3528 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3535 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3542 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3549 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 3556 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 3561 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 3566 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 3571 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 3576 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 3581 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 3586 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 3591 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3596 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3603 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3610 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 3617 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 3622 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 3627 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 3632 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 3637 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 3642 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 3647 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 3652 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 3657 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 3662 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 3667 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 3672 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 3677 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3682 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3687 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3692 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3697 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 3702 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3707 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3712 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3717 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3722 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3727 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3732 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3737 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3744 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3751 + {AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3758 + {AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3765 + {AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3772 + {AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3779 + {AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3786 + {AliasPatternCond_K_RegClass, AArch64_MPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3793 + {AliasPatternCond_K_RegClass, AArch64_MPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3800 + {AliasPatternCond_K_RegClass, AArch64_MPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3807 + {AliasPatternCond_K_RegClass, AArch64_MPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3814 + {AliasPatternCond_K_RegClass, AArch64_MPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - + // 3821 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - + // 3827 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - + // 3833 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - + // 3839 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3845 + {AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3852 + {AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3859 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureMTE}, + // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3863 + {AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3870 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3875 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3880 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3885 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3890 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3895 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3900 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3905 + {AliasPatternCond_K_RegClass, AArch64_ZPR2RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - + // 3912 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - + // 3918 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - + // 3924 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - + // 3930 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3936 + {AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3943 + {AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3950 + {AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 3957 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 3962 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 3967 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 3972 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3977 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3982 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3987 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3992 + {AliasPatternCond_K_RegClass, AArch64_ZPR3RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - + // 3999 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - + // 4005 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - + // 4011 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - + // 4017 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4023 + {AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4030 + {AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 4037 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 4042 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 4047 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 4052 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 4057 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 4062 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_DDDDRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 4067 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4072 + {AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4079 + {AliasPatternCond_K_RegClass, AArch64_ZPR4RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - + // 4086 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - + // 4092 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - + // 4098 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - + // 4104 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_QQQQRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (STGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 4110 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureMTE}, + // (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 4114 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureMTE}, + // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 4119 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 4123 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4127 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4131 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureRCPC_IMMO}, + // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 4135 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 4139 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 4143 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 4147 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 4151 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4155 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (STNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 4162 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (STNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 4167 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4172 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (STNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 4179 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4184 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (STNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 4191 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (STNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 4196 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4201 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (STNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 4208 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (STNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 4213 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_PPR_3bRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_Feature, AArch64_FeatureSVE2}, + // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 4218 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 4222 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 4226 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 4230 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 4234 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4238 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 4243 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4246 + {AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 4251 + {AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4254 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 4259 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4262 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 4267 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4270 + {AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 4275 + {AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4278 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 4283 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4286 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 4291 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4294 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 4299 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4302 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 4307 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 4310 + {AliasPatternCond_K_RegClass, AArch64_PPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (STR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, + // sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 4316 + {AliasPatternCond_K_RegClass, AArch64_MPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_MatrixIndexGPR32_12_15RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 4322 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 4328 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 4331 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 4334 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 4337 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4340 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 4343 + {AliasPatternCond_K_RegClass, AArch64_FPR8RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 4346 + {AliasPatternCond_K_RegClass, AArch64_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4349 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 4352 + {AliasPatternCond_K_RegClass, AArch64_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 4355 + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 4358 + {AliasPatternCond_K_RegClass, AArch64_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 4361 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 4364 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (STZ2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 4367 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureMTE}, + // (STZGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 4371 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, AArch64_FeatureMTE}, + // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 4375 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 4377 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 4381 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) - 4384 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 4388 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4391 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 4395 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 4399 + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 4402 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 4406 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 4408 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 4412 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) - 4415 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 4419 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4422 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 4426 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 4429 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - + // 4433 + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 4436 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) - 4440 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 4444 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_WZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4447 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 4451 + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 4455 + {AliasPatternCond_K_RegClass, AArch64_GPR32spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) - 4459 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 4463 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4466 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 4470 + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 4474 + {AliasPatternCond_K_RegClass, AArch64_GPR64spRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64sponlyRegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - + // 4478 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 4483 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 4487 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 4491 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 4495 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)63}, + // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 4499 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 4503 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 4507 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4511 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 4515 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (UMOVvi32_idx0 GPR32:$dst, V128:$src, VectorIndex0:$idx) - 4518 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureNEON}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 4523 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_Feature, AArch64_FeatureNEON}, + // (UMOVvi64_idx0 GPR64:$dst, V128:$src, VectorIndex0:$idx) - 4526 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_FPR128RegClassID}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureNEON}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4531 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Reg, AArch64_XZR}, + // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4535 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4542 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4549 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4556 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4563 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4570 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4577 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4584 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4591 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4598 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4605 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4612 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4619 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4626 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4633 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4640 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4647 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4654 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4661 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4668 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4675 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 4682 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4689 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4696 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4703 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4710 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4717 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4724 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4731 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4738 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4745 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4752 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4759 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4766 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4773 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4780 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4787 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4794 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4801 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 4808 + {AliasPatternCond_K_RegClass, AArch64_GPR32RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4815 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4822 + {AliasPatternCond_K_RegClass, AArch64_GPR64RegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4829 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 4836 + {AliasPatternCond_K_RegClass, AArch64_ZPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureSVE}, + {AliasPatternCond_K_OrFeature, AArch64_FeatureStreamingSVE}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (XPACLRI) - 4843 + {AliasPatternCond_K_Feature, AArch64_FeaturePAuth}, + // (ZERO_M { 1, 1, 1, 1, 1, 1, 1, 1 }) - 4844 + {AliasPatternCond_K_Imm, (uint32_t)255}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 0, 1, 0, 1, 0, 1, 0, 1 }) - 4846 + {AliasPatternCond_K_Imm, (uint32_t)85}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 1, 0, 1, 0, 1, 0, 1, 0 }) - 4848 + {AliasPatternCond_K_Imm, (uint32_t)170}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 0, 0, 0, 1, 0, 0, 0, 1 }) - 4850 + {AliasPatternCond_K_Imm, (uint32_t)17}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 0, 0, 1, 0, 0, 0, 1, 0 }) - 4852 + {AliasPatternCond_K_Imm, (uint32_t)34}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 0, 1, 0, 0, 0, 1, 0, 0 }) - 4854 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 1, 0, 0, 0, 1, 0, 0, 0 }) - 4856 + {AliasPatternCond_K_Imm, (uint32_t)136}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 0, 0, 1, 1, 0, 0, 1, 1 }) - 4858 + {AliasPatternCond_K_Imm, (uint32_t)51}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 1, 0, 0, 1, 1, 0, 0, 1 }) - 4860 + {AliasPatternCond_K_Imm, (uint32_t)153}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 0, 1, 1, 0, 0, 1, 1, 0 }) - 4862 + {AliasPatternCond_K_Imm, (uint32_t)102}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 1, 1, 0, 0, 1, 1, 0, 0 }) - 4864 + {AliasPatternCond_K_Imm, (uint32_t)204}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 0, 1, 1, 1, 0, 1, 1, 1 }) - 4866 + {AliasPatternCond_K_Imm, (uint32_t)119}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 1, 0, 1, 1, 1, 0, 1, 1 }) - 4868 + {AliasPatternCond_K_Imm, (uint32_t)187}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 1, 1, 0, 1, 1, 1, 0, 1 }) - 4870 + {AliasPatternCond_K_Imm, (uint32_t)221}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + // (ZERO_M { 1, 1, 1, 0, 1, 1, 1, 0 }) - 4872 + {AliasPatternCond_K_Imm, (uint32_t)238}, + {AliasPatternCond_K_Feature, AArch64_FeatureSME}, + }; + + static const char *AsmStrings[] = { + /* 0 */ + "cmn $\x02, $\xFF\x03\x01\0" + /* 13 */ "cmn $\x02, $\x03\0" + /* 24 */ "cmn $\x02, $\x03$\xFF\x04\x02\0" + /* 39 */ "adds $\x01, $\x02, $\x03\0" + /* 55 */ "cmn $\x02, $\x03$\xFF\x04\x03\0" + /* 70 */ "mov $\x01, $\x02\0" + /* 81 */ "add $\x01, $\x02, $\x03\0" + /* 96 */ "tst $\x02, $\xFF\x03\x04\0" + /* 109 */ "tst $\x02, $\x03\0" + /* 120 */ "tst $\x02, $\x03$\xFF\x04\x02\0" + /* 135 */ "ands $\x01, $\x02, $\x03\0" + /* 151 */ "tst $\x02, $\xFF\x03\x05\0" + /* 164 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" + /* 188 */ "and $\x01, $\x02, $\x03\0" + /* 203 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" + /* 226 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" + /* 247 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" + /* 268 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" + /* 289 */ "autia1716\0" + /* 299 */ "autiasp\0" + /* 307 */ "autiaz\0" + /* 314 */ "autib1716\0" + /* 324 */ "autibsp\0" + /* 332 */ "autibz\0" + /* 339 */ "bics $\x01, $\x02, $\x03\0" + /* 355 */ "bic $\x01, $\x02, $\x03\0" + /* 370 */ "clrex\0" + /* 376 */ "cntb $\x01\0" + /* 384 */ "cntb $\x01, $\xFF\x02\x0E\0" + /* 398 */ "cntd $\x01\0" + /* 406 */ "cntd $\x01, $\xFF\x02\x0E\0" + /* 420 */ "cnth $\x01\0" + /* 428 */ "cnth $\x01, $\xFF\x02\x0E\0" + /* 442 */ "cntw $\x01\0" + /* 450 */ "cntw $\x01, $\xFF\x02\x0E\0" + /* 464 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0" + /* 487 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0" + /* 510 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0" + /* 533 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0" + /* 556 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0" + /* 577 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0" + /* 598 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0" + /* 619 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0" + /* 640 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0" + /* 663 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0" + /* 686 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0" + /* 709 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0" + /* 732 */ "cset $\x01, $\xFF\x04\x14\0" + /* 746 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0" + /* 764 */ "csetm $\x01, $\xFF\x04\x14\0" + /* 779 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0" + /* 797 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0" + /* 815 */ "dcps1\0" + /* 821 */ "dcps2\0" + /* 827 */ "dcps3\0" + /* 833 */ "decb $\x01\0" + /* 841 */ "decb $\x01, $\xFF\x03\x0E\0" + /* 855 */ "decd $\x01\0" + /* 863 */ "decd $\x01, $\xFF\x03\x0E\0" + /* 877 */ "decd $\xFF\x01\x10\0" + /* 887 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0" + /* 903 */ "dech $\x01\0" + /* 911 */ "dech $\x01, $\xFF\x03\x0E\0" + /* 925 */ "dech $\xFF\x01\x09\0" + /* 935 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0" + /* 951 */ "decw $\x01\0" + /* 959 */ "decw $\x01, $\xFF\x03\x0E\0" + /* 973 */ "decw $\xFF\x01\x0B\0" + /* 983 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0" + /* 999 */ "ssbb\0" + /* 1004 */ "pssbb\0" + /* 1010 */ "dfb\0" + /* 1014 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0" + /* 1029 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0" + /* 1044 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0" + /* 1059 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0" + /* 1075 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0" + /* 1091 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0" + /* 1107 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0" + /* 1122 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0" + /* 1137 */ "fmov $\xFF\x01\x10, #0.0\0" + /* 1153 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0" + /* 1168 */ "fmov $\xFF\x01\x09, #0.0\0" + /* 1184 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0" + /* 1199 */ "fmov $\xFF\x01\x0B, #0.0\0" + /* 1215 */ "mov $\xFF\x01\x06, $\x02\0" + /* 1228 */ "mov $\xFF\x01\x10, $\x02\0" + /* 1241 */ "mov $\xFF\x01\x09, $\x02\0" + /* 1254 */ "mov $\xFF\x01\x0B, $\x02\0" + /* 1267 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0" + /* 1282 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0" + /* 1301 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0" + /* 1316 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0" + /* 1335 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0" + /* 1350 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0" + /* 1369 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0" + /* 1384 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0" + /* 1403 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0" + /* 1418 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0" + /* 1437 */ "eon $\x01, $\x02, $\x03\0" + /* 1452 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" + /* 1476 */ "eor $\x01, $\x02, $\x03\0" + /* 1491 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" + /* 1514 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" + /* 1535 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" + /* 1556 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" + /* 1577 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, " + "$\xFF\x05\x20]\0" + /* 1610 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, " + "$\xFF\x05\x20]\0" + /* 1643 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, " + "$\xFF\x05\x20]\0" + /* 1676 */ "mov $\xFF\x01\x1C, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, " + "$\xFF\x05\x20]\0" + /* 1709 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x1F[$\x04, " + "$\xFF\x05\x20]\0" + /* 1742 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, " + "$\xFF\x05\x20]\0" + /* 1775 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, " + "$\xFF\x05\x20]\0" + /* 1808 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, " + "$\xFF\x05\x20]\0" + /* 1841 */ "mov $\xFF\x01\x1C, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, " + "$\xFF\x05\x20]\0" + /* 1874 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x21[$\x04, " + "$\xFF\x05\x20]\0" + /* 1907 */ "ror $\x01, $\x02, $\x04\0" + /* 1922 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x22\0" + /* 1946 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x22\0" + /* 1970 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x22\0" + /* 1994 */ "fmov $\xFF\x01\x10, $\xFF\x02\x22\0" + /* 2010 */ "fmov $\xFF\x01\x09, $\xFF\x02\x22\0" + /* 2026 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x22\0" + /* 2042 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" + /* 2068 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" + /* 2094 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" + /* 2120 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" + /* 2146 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" + /* 2172 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" + /* 2199 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" + /* 2226 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" + /* 2253 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" + /* 2280 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" + /* 2307 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" + /* 2333 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" + /* 2359 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 2387 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 2415 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 2443 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 2471 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 2499 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 2528 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 2557 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 2586 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 2615 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 2644 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 2672 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 2700 */ "nop\0" + /* 2704 */ "yield\0" + /* 2710 */ "wfe\0" + /* 2714 */ "wfi\0" + /* 2718 */ "sev\0" + /* 2722 */ "sevl\0" + /* 2727 */ "dgh\0" + /* 2731 */ "esb\0" + /* 2735 */ "csdb\0" + /* 2740 */ "bti\0" + /* 2744 */ "bti $\xFF\x01\x25\0" + /* 2753 */ "psb $\xFF\x01\x26\0" + /* 2762 */ "incb $\x01\0" + /* 2770 */ "incb $\x01, $\xFF\x03\x0E\0" + /* 2784 */ "incd $\x01\0" + /* 2792 */ "incd $\x01, $\xFF\x03\x0E\0" + /* 2806 */ "incd $\xFF\x01\x10\0" + /* 2816 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0" + /* 2832 */ "inch $\x01\0" + /* 2840 */ "inch $\x01, $\xFF\x03\x0E\0" + /* 2854 */ "inch $\xFF\x01\x09\0" + /* 2864 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0" + /* 2880 */ "incw $\x01\0" + /* 2888 */ "incw $\x01, $\xFF\x03\x0E\0" + /* 2902 */ "incw $\xFF\x01\x0B\0" + /* 2912 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0" + /* 2928 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x06\0" + /* 2961 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x10\0" + /* 2994 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x09\0" + /* 3027 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x1C\0" + /* 3060 */ "mov $\xFF\x01\x1F[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x0B\0" + /* 3093 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x06\0" + /* 3126 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x10\0" + /* 3159 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x09\0" + /* 3192 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x1C\0" + /* 3225 */ "mov $\xFF\x01\x21[$\x02, $\xFF\x03\x20], $\xFF\x04\x07/m, " + "$\xFF\x05\x0B\0" + /* 3258 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04\0" + /* 3277 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, " + "$\xFF\x04\x0C.h$\xFF\x05\x19\0" + /* 3304 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04\0" + /* 3323 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, " + "$\xFF\x04\x0C.s$\xFF\x05\x19\0" + /* 3350 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04\0" + /* 3369 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, " + "$\xFF\x04\x0C.d$\xFF\x05\x19\0" + /* 3396 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04\0" + /* 3415 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, " + "$\xFF\x04\x0C.b$\xFF\x05\x19\0" + /* 3442 */ "irg $\x01, $\x02\0" + /* 3453 */ "isb\0" + /* 3457 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 3481 */ "ld1b $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 3505 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 3529 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 3553 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 3577 */ "ld1 $\xFF\x02\x29, [$\x01], #64\0" + /* 3597 */ "ld1 $\xFF\x02\x2A, [$\x01], #32\0" + /* 3617 */ "ld1 $\xFF\x02\x2B, [$\x01], #64\0" + /* 3637 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0" + /* 3657 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0" + /* 3677 */ "ld1 $\xFF\x02\x2E, [$\x01], #64\0" + /* 3697 */ "ld1 $\xFF\x02\x2F, [$\x01], #32\0" + /* 3717 */ "ld1 $\xFF\x02\x30, [$\x01], #64\0" + /* 3737 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 3761 */ "ld1h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 3785 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 3809 */ "ld1 $\xFF\x02\x29, [$\x01], #16\0" + /* 3829 */ "ld1 $\xFF\x02\x2A, [$\x01], #8\0" + /* 3848 */ "ld1 $\xFF\x02\x2B, [$\x01], #16\0" + /* 3868 */ "ld1 $\xFF\x02\x2C, [$\x01], #8\0" + /* 3887 */ "ld1 $\xFF\x02\x2D, [$\x01], #8\0" + /* 3906 */ "ld1 $\xFF\x02\x2E, [$\x01], #16\0" + /* 3926 */ "ld1 $\xFF\x02\x2F, [$\x01], #8\0" + /* 3945 */ "ld1 $\xFF\x02\x30, [$\x01], #16\0" + /* 3965 */ "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 3990 */ "ld1rb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 4015 */ "ld1rb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 4040 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 4065 */ "ld1rd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4090 */ "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4115 */ "ld1rh $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 4140 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 4165 */ "ld1rob $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 4191 */ "ld1rod $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4217 */ "ld1roh $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 4243 */ "ld1row $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 4269 */ "ld1rqb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 4295 */ "ld1rqd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4321 */ "ld1rqh $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 4347 */ "ld1rqw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 4373 */ "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4399 */ "ld1rsb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 4425 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 4451 */ "ld1rsh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4477 */ "ld1rsh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 4503 */ "ld1rsw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4529 */ "ld1rw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4554 */ "ld1rw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 4579 */ "ld1r $\xFF\x02\x29, [$\x01], #1\0" + /* 4599 */ "ld1r $\xFF\x02\x2A, [$\x01], #8\0" + /* 4619 */ "ld1r $\xFF\x02\x2B, [$\x01], #8\0" + /* 4639 */ "ld1r $\xFF\x02\x2C, [$\x01], #4\0" + /* 4659 */ "ld1r $\xFF\x02\x2D, [$\x01], #2\0" + /* 4679 */ "ld1r $\xFF\x02\x2E, [$\x01], #4\0" + /* 4699 */ "ld1r $\xFF\x02\x2F, [$\x01], #1\0" + /* 4719 */ "ld1r $\xFF\x02\x30, [$\x01], #2\0" + /* 4739 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4764 */ "ld1sb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 4789 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 4814 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4839 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 4864 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 4889 */ "ld1 $\xFF\x02\x29, [$\x01], #48\0" + /* 4909 */ "ld1 $\xFF\x02\x2A, [$\x01], #24\0" + /* 4929 */ "ld1 $\xFF\x02\x2B, [$\x01], #48\0" + /* 4949 */ "ld1 $\xFF\x02\x2C, [$\x01], #24\0" + /* 4969 */ "ld1 $\xFF\x02\x2D, [$\x01], #24\0" + /* 4989 */ "ld1 $\xFF\x02\x2E, [$\x01], #48\0" + /* 5009 */ "ld1 $\xFF\x02\x2F, [$\x01], #24\0" + /* 5029 */ "ld1 $\xFF\x02\x30, [$\x01], #48\0" + /* 5049 */ "ld1 $\xFF\x02\x29, [$\x01], #32\0" + /* 5069 */ "ld1 $\xFF\x02\x2A, [$\x01], #16\0" + /* 5089 */ "ld1 $\xFF\x02\x2B, [$\x01], #32\0" + /* 5109 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0" + /* 5129 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0" + /* 5149 */ "ld1 $\xFF\x02\x2E, [$\x01], #32\0" + /* 5169 */ "ld1 $\xFF\x02\x2F, [$\x01], #16\0" + /* 5189 */ "ld1 $\xFF\x02\x30, [$\x01], #32\0" + /* 5209 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 5233 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 5257 */ "ld1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5293 */ "ld1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5329 */ "ld1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5365 */ "ld1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5401 */ "ld1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5437 */ "ld1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5473 */ "ld1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5509 */ "ld1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5545 */ "ld1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5581 */ "ld1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, " + "$\xFF\x04\x07/z, [$\x05]\0" + /* 5617 */ "ld1 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #2\0" + /* 5640 */ "ld1 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #4\0" + /* 5663 */ "ld1 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #8\0" + /* 5686 */ "ld1 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #1\0" + /* 5709 */ "ld2b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 5733 */ "ld2d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 5757 */ "ld2h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 5781 */ "ld2r $\xFF\x02\x29, [$\x01], #2\0" + /* 5801 */ "ld2r $\xFF\x02\x2A, [$\x01], #16\0" + /* 5822 */ "ld2r $\xFF\x02\x2B, [$\x01], #16\0" + /* 5843 */ "ld2r $\xFF\x02\x2C, [$\x01], #8\0" + /* 5863 */ "ld2r $\xFF\x02\x2D, [$\x01], #4\0" + /* 5883 */ "ld2r $\xFF\x02\x2E, [$\x01], #8\0" + /* 5903 */ "ld2r $\xFF\x02\x2F, [$\x01], #2\0" + /* 5923 */ "ld2r $\xFF\x02\x30, [$\x01], #4\0" + /* 5943 */ "ld2 $\xFF\x02\x29, [$\x01], #32\0" + /* 5963 */ "ld2 $\xFF\x02\x2B, [$\x01], #32\0" + /* 5983 */ "ld2 $\xFF\x02\x2C, [$\x01], #16\0" + /* 6003 */ "ld2 $\xFF\x02\x2D, [$\x01], #16\0" + /* 6023 */ "ld2 $\xFF\x02\x2E, [$\x01], #32\0" + /* 6043 */ "ld2 $\xFF\x02\x2F, [$\x01], #16\0" + /* 6063 */ "ld2 $\xFF\x02\x30, [$\x01], #32\0" + /* 6083 */ "ld2w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 6107 */ "ld2 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #4\0" + /* 6130 */ "ld2 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #8\0" + /* 6153 */ "ld2 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #16\0" + /* 6177 */ "ld2 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #2\0" + /* 6200 */ "ld3b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 6224 */ "ld3d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 6248 */ "ld3h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 6272 */ "ld3r $\xFF\x02\x29, [$\x01], #3\0" + /* 6292 */ "ld3r $\xFF\x02\x2A, [$\x01], #24\0" + /* 6313 */ "ld3r $\xFF\x02\x2B, [$\x01], #24\0" + /* 6334 */ "ld3r $\xFF\x02\x2C, [$\x01], #12\0" + /* 6355 */ "ld3r $\xFF\x02\x2D, [$\x01], #6\0" + /* 6375 */ "ld3r $\xFF\x02\x2E, [$\x01], #12\0" + /* 6396 */ "ld3r $\xFF\x02\x2F, [$\x01], #3\0" + /* 6416 */ "ld3r $\xFF\x02\x30, [$\x01], #6\0" + /* 6436 */ "ld3 $\xFF\x02\x29, [$\x01], #48\0" + /* 6456 */ "ld3 $\xFF\x02\x2B, [$\x01], #48\0" + /* 6476 */ "ld3 $\xFF\x02\x2C, [$\x01], #24\0" + /* 6496 */ "ld3 $\xFF\x02\x2D, [$\x01], #24\0" + /* 6516 */ "ld3 $\xFF\x02\x2E, [$\x01], #48\0" + /* 6536 */ "ld3 $\xFF\x02\x2F, [$\x01], #24\0" + /* 6556 */ "ld3 $\xFF\x02\x30, [$\x01], #48\0" + /* 6576 */ "ld3w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 6600 */ "ld3 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #6\0" + /* 6623 */ "ld3 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #12\0" + /* 6647 */ "ld3 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #24\0" + /* 6671 */ "ld3 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #3\0" + /* 6694 */ "ld4b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 6718 */ "ld4d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 6742 */ "ld4 $\xFF\x02\x29, [$\x01], #64\0" + /* 6762 */ "ld4 $\xFF\x02\x2B, [$\x01], #64\0" + /* 6782 */ "ld4 $\xFF\x02\x2C, [$\x01], #32\0" + /* 6802 */ "ld4 $\xFF\x02\x2D, [$\x01], #32\0" + /* 6822 */ "ld4 $\xFF\x02\x2E, [$\x01], #64\0" + /* 6842 */ "ld4 $\xFF\x02\x2F, [$\x01], #32\0" + /* 6862 */ "ld4 $\xFF\x02\x30, [$\x01], #64\0" + /* 6882 */ "ld4h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 6906 */ "ld4r $\xFF\x02\x29, [$\x01], #4\0" + /* 6926 */ "ld4r $\xFF\x02\x2A, [$\x01], #32\0" + /* 6947 */ "ld4r $\xFF\x02\x2B, [$\x01], #32\0" + /* 6968 */ "ld4r $\xFF\x02\x2C, [$\x01], #16\0" + /* 6989 */ "ld4r $\xFF\x02\x2D, [$\x01], #8\0" + /* 7009 */ "ld4r $\xFF\x02\x2E, [$\x01], #16\0" + /* 7030 */ "ld4r $\xFF\x02\x2F, [$\x01], #4\0" + /* 7050 */ "ld4r $\xFF\x02\x30, [$\x01], #8\0" + /* 7070 */ "ld4w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 7094 */ "ld4 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #8\0" + /* 7117 */ "ld4 $\xFF\x02\x32$\xFF\x04\x19, [$\x01], #16\0" + /* 7141 */ "ld4 $\xFF\x02\x33$\xFF\x04\x19, [$\x01], #32\0" + /* 7165 */ "ld4 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #4\0" + /* 7188 */ "staddb $\x02, [$\x03]\0" + /* 7204 */ "staddh $\x02, [$\x03]\0" + /* 7220 */ "staddlb $\x02, [$\x03]\0" + /* 7237 */ "staddlh $\x02, [$\x03]\0" + /* 7254 */ "staddl $\x02, [$\x03]\0" + /* 7270 */ "stadd $\x02, [$\x03]\0" + /* 7285 */ "ldapurb $\x01, [$\x02]\0" + /* 7302 */ "ldapurh $\x01, [$\x02]\0" + /* 7319 */ "ldapursb $\x01, [$\x02]\0" + /* 7337 */ "ldapursh $\x01, [$\x02]\0" + /* 7355 */ "ldapursw $\x01, [$\x02]\0" + /* 7373 */ "ldapur $\x01, [$\x02]\0" + /* 7389 */ "stclrb $\x02, [$\x03]\0" + /* 7405 */ "stclrh $\x02, [$\x03]\0" + /* 7421 */ "stclrlb $\x02, [$\x03]\0" + /* 7438 */ "stclrlh $\x02, [$\x03]\0" + /* 7455 */ "stclrl $\x02, [$\x03]\0" + /* 7471 */ "stclr $\x02, [$\x03]\0" + /* 7486 */ "steorb $\x02, [$\x03]\0" + /* 7502 */ "steorh $\x02, [$\x03]\0" + /* 7518 */ "steorlb $\x02, [$\x03]\0" + /* 7535 */ "steorlh $\x02, [$\x03]\0" + /* 7552 */ "steorl $\x02, [$\x03]\0" + /* 7568 */ "steor $\x02, [$\x03]\0" + /* 7583 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 7609 */ "ldff1b $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 7635 */ "ldff1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 7661 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 7687 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 7713 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 7739 */ "ldff1h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 7765 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 7791 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 7818 */ "ldff1sb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 7845 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 7872 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 7899 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 7926 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 7953 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 7979 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 8005 */ "ldg $\x01, [$\x03]\0" + /* 8018 */ "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 8044 */ "ldnf1b $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 8070 */ "ldnf1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 8096 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 8122 */ "ldnf1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 8148 */ "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 8174 */ "ldnf1h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 8200 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 8226 */ "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 8253 */ "ldnf1sb $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 8280 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 8307 */ "ldnf1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 8334 */ "ldnf1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 8361 */ "ldnf1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 8388 */ "ldnf1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 8414 */ "ldnf1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 8440 */ "ldnp $\x01, $\x02, [$\x03]\0" + /* 8458 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" + /* 8484 */ "ldnt1b $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 8512 */ "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 8540 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" + /* 8566 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 8594 */ "ldnt1h $\xFF\x01\x27, $\xFF\x02\x07/z, [$\x03]\0" + /* 8620 */ "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 8648 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 8676 */ "ldnt1sb $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 8705 */ "ldnt1sb $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 8734 */ "ldnt1sh $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 8763 */ "ldnt1sh $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 8792 */ "ldnt1sw $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 8821 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" + /* 8847 */ "ldnt1w $\xFF\x01\x23, $\xFF\x02\x07/z, " + "[$\xFF\x03\x10]\0" + /* 8875 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, " + "[$\xFF\x03\x0B]\0" + /* 8903 */ "ldp $\x01, $\x02, [$\x03]\0" + /* 8920 */ "ldpsw $\x01, $\x02, [$\x03]\0" + /* 8939 */ "ldraa $\x01, [$\x02]\0" + /* 8954 */ "ldrab $\x01, [$\x02]\0" + /* 8969 */ "ldrb $\x01, [$\x02, $\x03]\0" + /* 8987 */ "ldrb $\x01, [$\x02]\0" + /* 9001 */ "ldr $\x01, [$\x02, $\x03]\0" + /* 9018 */ "ldr $\x01, [$\x02]\0" + /* 9031 */ "ldrh $\x01, [$\x02, $\x03]\0" + /* 9049 */ "ldrh $\x01, [$\x02]\0" + /* 9063 */ "ldrsb $\x01, [$\x02, $\x03]\0" + /* 9082 */ "ldrsb $\x01, [$\x02]\0" + /* 9097 */ "ldrsh $\x01, [$\x02, $\x03]\0" + /* 9116 */ "ldrsh $\x01, [$\x02]\0" + /* 9131 */ "ldrsw $\x01, [$\x02, $\x03]\0" + /* 9150 */ "ldrsw $\x01, [$\x02]\0" + /* 9165 */ "ldr $\xFF\x01\x07, [$\x02]\0" + /* 9180 */ "ldr $\xFF\x01\x35[$\x02, $\xFF\x03\x20], [$\x04]\0" + /* 9205 */ "stsetb $\x02, [$\x03]\0" + /* 9221 */ "stseth $\x02, [$\x03]\0" + /* 9237 */ "stsetlb $\x02, [$\x03]\0" + /* 9254 */ "stsetlh $\x02, [$\x03]\0" + /* 9271 */ "stsetl $\x02, [$\x03]\0" + /* 9287 */ "stset $\x02, [$\x03]\0" + /* 9302 */ "stsmaxb $\x02, [$\x03]\0" + /* 9319 */ "stsmaxh $\x02, [$\x03]\0" + /* 9336 */ "stsmaxlb $\x02, [$\x03]\0" + /* 9354 */ "stsmaxlh $\x02, [$\x03]\0" + /* 9372 */ "stsmaxl $\x02, [$\x03]\0" + /* 9389 */ "stsmax $\x02, [$\x03]\0" + /* 9405 */ "stsminb $\x02, [$\x03]\0" + /* 9422 */ "stsminh $\x02, [$\x03]\0" + /* 9439 */ "stsminlb $\x02, [$\x03]\0" + /* 9457 */ "stsminlh $\x02, [$\x03]\0" + /* 9475 */ "stsminl $\x02, [$\x03]\0" + /* 9492 */ "stsmin $\x02, [$\x03]\0" + /* 9508 */ "ldtrb $\x01, [$\x02]\0" + /* 9523 */ "ldtrh $\x01, [$\x02]\0" + /* 9538 */ "ldtrsb $\x01, [$\x02]\0" + /* 9554 */ "ldtrsh $\x01, [$\x02]\0" + /* 9570 */ "ldtrsw $\x01, [$\x02]\0" + /* 9586 */ "ldtr $\x01, [$\x02]\0" + /* 9600 */ "stumaxb $\x02, [$\x03]\0" + /* 9617 */ "stumaxh $\x02, [$\x03]\0" + /* 9634 */ "stumaxlb $\x02, [$\x03]\0" + /* 9652 */ "stumaxlh $\x02, [$\x03]\0" + /* 9670 */ "stumaxl $\x02, [$\x03]\0" + /* 9687 */ "stumax $\x02, [$\x03]\0" + /* 9703 */ "stuminb $\x02, [$\x03]\0" + /* 9720 */ "stuminh $\x02, [$\x03]\0" + /* 9737 */ "stuminlb $\x02, [$\x03]\0" + /* 9755 */ "stuminlh $\x02, [$\x03]\0" + /* 9773 */ "stuminl $\x02, [$\x03]\0" + /* 9790 */ "stumin $\x02, [$\x03]\0" + /* 9806 */ "ldurb $\x01, [$\x02]\0" + /* 9821 */ "ldur $\x01, [$\x02]\0" + /* 9835 */ "ldurh $\x01, [$\x02]\0" + /* 9850 */ "ldursb $\x01, [$\x02]\0" + /* 9866 */ "ldursh $\x01, [$\x02]\0" + /* 9882 */ "ldursw $\x01, [$\x02]\0" + /* 9898 */ "mul $\x01, $\x02, $\x03\0" + /* 9913 */ "smstart\0" + /* 9921 */ "smstart sm\0" + /* 9932 */ "smstart za\0" + /* 9943 */ "smstop\0" + /* 9950 */ "smstop sm\0" + /* 9960 */ "smstop za\0" + /* 9970 */ "mneg $\x01, $\x02, $\x03\0" + /* 9986 */ "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0" + /* 10009 */ "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0" + /* 10030 */ "mvn $\x01, $\x03\0" + /* 10041 */ "mvn $\x01, $\x03$\xFF\x04\x02\0" + /* 10056 */ "orn $\x01, $\x02, $\x03\0" + /* 10071 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0" + /* 10087 */ "mov $\x01, $\x03\0" + /* 10098 */ "orr $\x01, $\x02, $\x03\0" + /* 10113 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0" + /* 10128 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" + /* 10149 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" + /* 10170 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" + /* 10191 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0" + /* 10206 */ "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0" + /* 10229 */ "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0" + /* 10250 */ "pacia1716\0" + /* 10260 */ "paciasp\0" + /* 10268 */ "paciaz\0" + /* 10275 */ "pacib1716\0" + /* 10285 */ "pacibsp\0" + /* 10293 */ "pacibz\0" + /* 10300 */ "prfb $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 10324 */ "prfb $\xFF\x01\x37, $\xFF\x02\x07, [$\x03]\0" + /* 10346 */ "prfb $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 10370 */ "prfd $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 10394 */ "prfd $\xFF\x01\x37, $\xFF\x02\x07, [$\x03]\0" + /* 10416 */ "prfd $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 10440 */ "prfh $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 10464 */ "prfh $\xFF\x01\x37, $\xFF\x02\x07, [$\x03]\0" + /* 10486 */ "prfh $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 10510 */ "prfm $\xFF\x01\x38, [$\x02, $\x03]\0" + /* 10530 */ "prfm $\xFF\x01\x38, [$\x02]\0" + /* 10546 */ "prfum $\xFF\x01\x38, [$\x02]\0" + /* 10563 */ "prfw $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 10587 */ "prfw $\xFF\x01\x37, $\xFF\x02\x07, [$\x03]\0" + /* 10609 */ "prfw $\xFF\x01\x37, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 10633 */ "ptrues $\xFF\x01\x06\0" + /* 10645 */ "ptrues $\xFF\x01\x10\0" + /* 10657 */ "ptrues $\xFF\x01\x09\0" + /* 10669 */ "ptrues $\xFF\x01\x0B\0" + /* 10681 */ "ptrue $\xFF\x01\x06\0" + /* 10692 */ "ptrue $\xFF\x01\x10\0" + /* 10703 */ "ptrue $\xFF\x01\x09\0" + /* 10714 */ "ptrue $\xFF\x01\x0B\0" + /* 10725 */ "ret\0" + /* 10729 */ "ngcs $\x01, $\x03\0" + /* 10741 */ "ngc $\x01, $\x03\0" + /* 10752 */ "asr $\x01, $\x02, $\x03\0" + /* 10767 */ "sxtb $\x01, $\x02\0" + /* 10779 */ "sxth $\x01, $\x02\0" + /* 10791 */ "sxtw $\x01, $\x02\0" + /* 10803 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0" + /* 10826 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0" + /* 10849 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0" + /* 10872 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0" + /* 10895 */ "smull $\x01, $\x02, $\x03\0" + /* 10912 */ "smnegl $\x01, $\x02, $\x03\0" + /* 10930 */ "sqdecb $\x01\0" + /* 10940 */ "sqdecb $\x01, $\xFF\x03\x0E\0" + /* 10956 */ "sqdecb $\x01, $\xFF\x02\x39\0" + /* 10972 */ "sqdecb $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0" + /* 10994 */ "sqdecd $\x01\0" + /* 11004 */ "sqdecd $\x01, $\xFF\x03\x0E\0" + /* 11020 */ "sqdecd $\x01, $\xFF\x02\x39\0" + /* 11036 */ "sqdecd $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0" + /* 11058 */ "sqdecd $\xFF\x01\x10\0" + /* 11070 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" + /* 11088 */ "sqdech $\x01\0" + /* 11098 */ "sqdech $\x01, $\xFF\x03\x0E\0" + /* 11114 */ "sqdech $\x01, $\xFF\x02\x39\0" + /* 11130 */ "sqdech $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0" + /* 11152 */ "sqdech $\xFF\x01\x09\0" + /* 11164 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" + /* 11182 */ "sqdecw $\x01\0" + /* 11192 */ "sqdecw $\x01, $\xFF\x03\x0E\0" + /* 11208 */ "sqdecw $\x01, $\xFF\x02\x39\0" + /* 11224 */ "sqdecw $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0" + /* 11246 */ "sqdecw $\xFF\x01\x0B\0" + /* 11258 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" + /* 11276 */ "sqincb $\x01\0" + /* 11286 */ "sqincb $\x01, $\xFF\x03\x0E\0" + /* 11302 */ "sqincb $\x01, $\xFF\x02\x39\0" + /* 11318 */ "sqincb $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0" + /* 11340 */ "sqincd $\x01\0" + /* 11350 */ "sqincd $\x01, $\xFF\x03\x0E\0" + /* 11366 */ "sqincd $\x01, $\xFF\x02\x39\0" + /* 11382 */ "sqincd $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0" + /* 11404 */ "sqincd $\xFF\x01\x10\0" + /* 11416 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" + /* 11434 */ "sqinch $\x01\0" + /* 11444 */ "sqinch $\x01, $\xFF\x03\x0E\0" + /* 11460 */ "sqinch $\x01, $\xFF\x02\x39\0" + /* 11476 */ "sqinch $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0" + /* 11498 */ "sqinch $\xFF\x01\x09\0" + /* 11510 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" + /* 11528 */ "sqincw $\x01\0" + /* 11538 */ "sqincw $\x01, $\xFF\x03\x0E\0" + /* 11554 */ "sqincw $\x01, $\xFF\x02\x39\0" + /* 11570 */ "sqincw $\x01, $\xFF\x02\x39, $\xFF\x03\x0E\0" + /* 11592 */ "sqincw $\xFF\x01\x0B\0" + /* 11604 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" + /* 11622 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 11646 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 11670 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 11694 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 11718 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 11742 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 11766 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 11790 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" + /* 11812 */ "st1b $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0" + /* 11834 */ "st1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" + /* 11856 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" + /* 11878 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" + /* 11900 */ "st1 $\xFF\x02\x29, [$\x01], #64\0" + /* 11920 */ "st1 $\xFF\x02\x2A, [$\x01], #32\0" + /* 11940 */ "st1 $\xFF\x02\x2B, [$\x01], #64\0" + /* 11960 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0" + /* 11980 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0" + /* 12000 */ "st1 $\xFF\x02\x2E, [$\x01], #64\0" + /* 12020 */ "st1 $\xFF\x02\x2F, [$\x01], #32\0" + /* 12040 */ "st1 $\xFF\x02\x30, [$\x01], #64\0" + /* 12060 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" + /* 12082 */ "st1h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0" + /* 12104 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" + /* 12126 */ "st1 $\xFF\x02\x29, [$\x01], #16\0" + /* 12146 */ "st1 $\xFF\x02\x2A, [$\x01], #8\0" + /* 12165 */ "st1 $\xFF\x02\x2B, [$\x01], #16\0" + /* 12185 */ "st1 $\xFF\x02\x2C, [$\x01], #8\0" + /* 12204 */ "st1 $\xFF\x02\x2D, [$\x01], #8\0" + /* 12223 */ "st1 $\xFF\x02\x2E, [$\x01], #16\0" + /* 12243 */ "st1 $\xFF\x02\x2F, [$\x01], #8\0" + /* 12262 */ "st1 $\xFF\x02\x30, [$\x01], #16\0" + /* 12282 */ "st1 $\xFF\x02\x29, [$\x01], #48\0" + /* 12302 */ "st1 $\xFF\x02\x2A, [$\x01], #24\0" + /* 12322 */ "st1 $\xFF\x02\x2B, [$\x01], #48\0" + /* 12342 */ "st1 $\xFF\x02\x2C, [$\x01], #24\0" + /* 12362 */ "st1 $\xFF\x02\x2D, [$\x01], #24\0" + /* 12382 */ "st1 $\xFF\x02\x2E, [$\x01], #48\0" + /* 12402 */ "st1 $\xFF\x02\x2F, [$\x01], #24\0" + /* 12422 */ "st1 $\xFF\x02\x30, [$\x01], #48\0" + /* 12442 */ "st1 $\xFF\x02\x29, [$\x01], #32\0" + /* 12462 */ "st1 $\xFF\x02\x2A, [$\x01], #16\0" + /* 12482 */ "st1 $\xFF\x02\x2B, [$\x01], #32\0" + /* 12502 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0" + /* 12522 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0" + /* 12542 */ "st1 $\xFF\x02\x2E, [$\x01], #32\0" + /* 12562 */ "st1 $\xFF\x02\x2F, [$\x01], #16\0" + /* 12582 */ "st1 $\xFF\x02\x30, [$\x01], #32\0" + /* 12602 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" + /* 12624 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" + /* 12646 */ "st1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12680 */ "st1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12714 */ "st1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12748 */ "st1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12782 */ "st1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12816 */ "st1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12850 */ "st1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12884 */ "st1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12918 */ "st1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12952 */ "st1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, " + "[$\x05]\0" + /* 12986 */ "st1 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #2\0" + /* 13009 */ "st1 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #4\0" + /* 13032 */ "st1 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #8\0" + /* 13055 */ "st1 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #1\0" + /* 13078 */ "st2b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" + /* 13100 */ "st2d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" + /* 13122 */ "st2g $\x01, [$\x02]\0" + /* 13136 */ "st2h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0" + /* 13158 */ "st2 $\xFF\x02\x29, [$\x01], #32\0" + /* 13178 */ "st2 $\xFF\x02\x2B, [$\x01], #32\0" + /* 13198 */ "st2 $\xFF\x02\x2C, [$\x01], #16\0" + /* 13218 */ "st2 $\xFF\x02\x2D, [$\x01], #16\0" + /* 13238 */ "st2 $\xFF\x02\x2E, [$\x01], #32\0" + /* 13258 */ "st2 $\xFF\x02\x2F, [$\x01], #16\0" + /* 13278 */ "st2 $\xFF\x02\x30, [$\x01], #32\0" + /* 13298 */ "st2w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" + /* 13320 */ "st2 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #4\0" + /* 13343 */ "st2 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #8\0" + /* 13366 */ "st2 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #16\0" + /* 13390 */ "st2 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #2\0" + /* 13413 */ "st3b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" + /* 13435 */ "st3d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" + /* 13457 */ "st3h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0" + /* 13479 */ "st3 $\xFF\x02\x29, [$\x01], #48\0" + /* 13499 */ "st3 $\xFF\x02\x2B, [$\x01], #48\0" + /* 13519 */ "st3 $\xFF\x02\x2C, [$\x01], #24\0" + /* 13539 */ "st3 $\xFF\x02\x2D, [$\x01], #24\0" + /* 13559 */ "st3 $\xFF\x02\x2E, [$\x01], #48\0" + /* 13579 */ "st3 $\xFF\x02\x2F, [$\x01], #24\0" + /* 13599 */ "st3 $\xFF\x02\x30, [$\x01], #48\0" + /* 13619 */ "st3w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" + /* 13641 */ "st3 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #6\0" + /* 13664 */ "st3 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #12\0" + /* 13688 */ "st3 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #24\0" + /* 13712 */ "st3 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #3\0" + /* 13735 */ "st4b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" + /* 13757 */ "st4d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" + /* 13779 */ "st4 $\xFF\x02\x29, [$\x01], #64\0" + /* 13799 */ "st4 $\xFF\x02\x2B, [$\x01], #64\0" + /* 13819 */ "st4 $\xFF\x02\x2C, [$\x01], #32\0" + /* 13839 */ "st4 $\xFF\x02\x2D, [$\x01], #32\0" + /* 13859 */ "st4 $\xFF\x02\x2E, [$\x01], #64\0" + /* 13879 */ "st4 $\xFF\x02\x2F, [$\x01], #32\0" + /* 13899 */ "st4 $\xFF\x02\x30, [$\x01], #64\0" + /* 13919 */ "st4h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0" + /* 13941 */ "st4w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" + /* 13963 */ "st4 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #8\0" + /* 13986 */ "st4 $\xFF\x02\x32$\xFF\x03\x19, [$\x01], #16\0" + /* 14010 */ "st4 $\xFF\x02\x33$\xFF\x03\x19, [$\x01], #32\0" + /* 14034 */ "st4 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #4\0" + /* 14057 */ "stg $\x01, [$\x02]\0" + /* 14070 */ "stgp $\x01, $\x02, [$\x03]\0" + /* 14088 */ "stlurb $\x01, [$\x02]\0" + /* 14104 */ "stlurh $\x01, [$\x02]\0" + /* 14120 */ "stlur $\x01, [$\x02]\0" + /* 14135 */ "stnp $\x01, $\x02, [$\x03]\0" + /* 14153 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" + /* 14177 */ "stnt1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 14203 */ "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 14229 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" + /* 14253 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 14279 */ "stnt1h $\xFF\x01\x27, $\xFF\x02\x07, [$\x03]\0" + /* 14303 */ "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 14329 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 14355 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" + /* 14379 */ "stnt1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" + /* 14405 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" + /* 14431 */ "stp $\x01, $\x02, [$\x03]\0" + /* 14448 */ "strb $\x01, [$\x02, $\x03]\0" + /* 14466 */ "strb $\x01, [$\x02]\0" + /* 14480 */ "str $\x01, [$\x02, $\x03]\0" + /* 14497 */ "str $\x01, [$\x02]\0" + /* 14510 */ "strh $\x01, [$\x02, $\x03]\0" + /* 14528 */ "strh $\x01, [$\x02]\0" + /* 14542 */ "str $\xFF\x01\x07, [$\x02]\0" + /* 14557 */ "str $\xFF\x01\x35[$\x02, $\xFF\x03\x20], [$\x04]\0" + /* 14582 */ "sttrb $\x01, [$\x02]\0" + /* 14597 */ "sttrh $\x01, [$\x02]\0" + /* 14612 */ "sttr $\x01, [$\x02]\0" + /* 14626 */ "sturb $\x01, [$\x02]\0" + /* 14641 */ "stur $\x01, [$\x02]\0" + /* 14655 */ "sturh $\x01, [$\x02]\0" + /* 14670 */ "stz2g $\x01, [$\x02]\0" + /* 14685 */ "stzg $\x01, [$\x02]\0" + /* 14699 */ "cmp $\x02, $\xFF\x03\x01\0" + /* 14712 */ "cmp $\x02, $\x03\0" + /* 14723 */ "cmp $\x02, $\x03$\xFF\x04\x02\0" + /* 14738 */ "negs $\x01, $\x03\0" + /* 14750 */ "negs $\x01, $\x03$\xFF\x04\x02\0" + /* 14766 */ "subs $\x01, $\x02, $\x03\0" + /* 14782 */ "cmp $\x02, $\x03$\xFF\x04\x03\0" + /* 14797 */ "neg $\x01, $\x03\0" + /* 14808 */ "neg $\x01, $\x03$\xFF\x04\x02\0" + /* 14823 */ "sub $\x01, $\x02, $\x03\0" + /* 14838 */ "sys $\x01, $\xFF\x02\x3A, $\xFF\x03\x3A, $\x04\0" + /* 14861 */ "lsr $\x01, $\x02, $\x03\0" + /* 14876 */ "uxtb $\x01, $\x02\0" + /* 14888 */ "uxth $\x01, $\x02\0" + /* 14900 */ "uxtw $\x01, $\x02\0" + /* 14912 */ "umull $\x01, $\x02, $\x03\0" + /* 14929 */ "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19\0" + /* 14948 */ "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19\0" + /* 14967 */ "umnegl $\x01, $\x02, $\x03\0" + /* 14985 */ "uqdecb $\x01\0" + /* 14995 */ "uqdecb $\x01, $\xFF\x03\x0E\0" + /* 15011 */ "uqdecd $\x01\0" + /* 15021 */ "uqdecd $\x01, $\xFF\x03\x0E\0" + /* 15037 */ "uqdecd $\xFF\x01\x10\0" + /* 15049 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" + /* 15067 */ "uqdech $\x01\0" + /* 15077 */ "uqdech $\x01, $\xFF\x03\x0E\0" + /* 15093 */ "uqdech $\xFF\x01\x09\0" + /* 15105 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" + /* 15123 */ "uqdecw $\x01\0" + /* 15133 */ "uqdecw $\x01, $\xFF\x03\x0E\0" + /* 15149 */ "uqdecw $\xFF\x01\x0B\0" + /* 15161 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" + /* 15179 */ "uqincb $\x01\0" + /* 15189 */ "uqincb $\x01, $\xFF\x03\x0E\0" + /* 15205 */ "uqincd $\x01\0" + /* 15215 */ "uqincd $\x01, $\xFF\x03\x0E\0" + /* 15231 */ "uqincd $\xFF\x01\x10\0" + /* 15243 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" + /* 15261 */ "uqinch $\x01\0" + /* 15271 */ "uqinch $\x01, $\xFF\x03\x0E\0" + /* 15287 */ "uqinch $\xFF\x01\x09\0" + /* 15299 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" + /* 15317 */ "uqincw $\x01\0" + /* 15327 */ "uqincw $\x01, $\xFF\x03\x0E\0" + /* 15343 */ "uqincw $\xFF\x01\x0B\0" + /* 15355 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" + /* 15373 */ "xpaclri\0" + /* 15381 */ "zero {za}\0" + /* 15391 */ "zero {za0.h}\0" + /* 15404 */ "zero {za1.h}\0" + /* 15417 */ "zero {za0.s}\0" + /* 15430 */ "zero {za1.s}\0" + /* 15443 */ "zero {za2.s}\0" + /* 15456 */ "zero {za3.s}\0" + /* 15469 */ "zero {za0.s,za1.s}\0" + /* 15488 */ "zero {za0.s,za3.s}\0" + /* 15507 */ "zero {za1.s,za2.s}\0" + /* 15526 */ "zero {za2.s,za3.s}\0" + /* 15545 */ "zero {za0.s,za1.s,za2.s}\0" + /* 15570 */ "zero {za0.s,za1.s,za3.s}\0" + /* 15595 */ "zero {za0.s,za2.s,za3.s}\0" + /* 15620 */ "zero {za1.s,za2.s,za3.s}\0"}; + + const char *AsmString = MCInstPrinter_matchAliasPatterns( + MI, OpToPatterns, Patterns, Conds, AsmStrings, 811); + if (!AsmString) + return false; + + char *tmpString = cs_strdup(AsmString); + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, "\t"); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, *(tmpString + (I++))); + } + } while (AsmString[I] != '\0'); + } + + return tmpString; +} + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { + switch (PrintMethodIdx) { + default: + llvm_unreachable("Unknown PrintMethod kind"); + break; + // printAddSubImm + case 0: + printAddSubImm(MI, OpIdx, OS); + break; + // printShifter + case 1: + printShifter(MI, OpIdx, OS); + break; + // printArithExtend + case 2: + printArithExtend(MI, OpIdx, OS); + break; + // printLogicalImm + case 3: + printLogicalImm32(MI, OpIdx, OS); + break; + // printLogicalImm + case 4: + printLogicalImm64(MI, OpIdx, OS); + break; + // printSVERegOp<'b'> + case 5: + printSVERegOp(MI, OpIdx, OS, 'b'); + break; + // printSVERegOp<> + case 6: + printSVERegOp(MI, OpIdx, OS, 0); + break; + // printLogicalImm + case 7: + printLogicalImm32(MI, OpIdx, OS); + break; + // printSVERegOp<'h'> + case 8: + printSVERegOp(MI, OpIdx, OS, 'h'); + break; + // printLogicalImm + case 9: + printLogicalImm32(MI, OpIdx, OS); + break; + // printSVERegOp<'s'> + case 10: + printSVERegOp(MI, OpIdx, OS, 's'); + break; + // printVRegOperand + case 11: + printVRegOperand(MI, OpIdx, OS); + break; + // printImm + case 12: + printImm(MI, OpIdx, OS); + break; + // printSVEPattern + case 13: + printSVEPattern(MI, OpIdx, OS); + break; + // printImm8OptLsl + case 14: + printImm8OptLsl32(MI, OpIdx, OS); + break; + // printSVERegOp<'d'> + case 15: + printSVERegOp(MI, OpIdx, OS, 'd'); + break; + // printImm8OptLsl + case 16: + printImm8OptLsl64(MI, OpIdx, OS); + break; + // printImm8OptLsl + case 17: + printImm8OptLsl32(MI, OpIdx, OS); + break; + // printImm8OptLsl + case 18: + printImm8OptLsl32(MI, OpIdx, OS); + break; + // printInverseCondCode + case 19: + printInverseCondCode(MI, OpIdx, OS); + break; + // printSVELogicalImm + case 20: + printSVELogicalImm32(MI, OpIdx, OS); + break; + // printSVELogicalImm + case 21: + printSVELogicalImm32(MI, OpIdx, OS); + break; + // printSVELogicalImm + case 22: + printSVELogicalImm64(MI, OpIdx, OS); + break; + // printZPRasFPR<8> + case 23: + printZPRasFPR(MI, OpIdx, OS, 8); + break; + // printVectorIndex + case 24: + printVectorIndex(MI, OpIdx, OS); + break; + // printZPRasFPR<64> + case 25: + printZPRasFPR(MI, OpIdx, OS, 64); + break; + // printZPRasFPR<16> + case 26: + printZPRasFPR(MI, OpIdx, OS, 16); + break; + // printSVERegOp<'q'> + case 27: + printSVERegOp(MI, OpIdx, OS, 'q'); + break; + // printZPRasFPR<128> + case 28: + printZPRasFPR(MI, OpIdx, OS, 128); + break; + // printZPRasFPR<32> + case 29: + printZPRasFPR(MI, OpIdx, OS, 32); + break; + // printMatrixTileVector<0> + case 30: + printMatrixTileVector(MI, OpIdx, OS, 0); + break; + // printMatrixIndex + case 31: + printMatrixIndex(MI, OpIdx, OS); + break; + // printMatrixTileVector<1> + case 32: + printMatrixTileVector(MI, OpIdx, OS, 1); + break; + // printFPImmOperand + case 33: + printFPImmOperand(MI, OpIdx, OS); + break; + // printTypedVectorList<0,'d'> + case 34: + printTypedVectorList(MI, OpIdx, OS, 0, 'd'); + break; + // printTypedVectorList<0,'s'> + case 35: + printTypedVectorList(MI, OpIdx, OS, 0, 's'); + break; + // printBTIHintOp + case 36: + printBTIHintOp(MI, OpIdx, OS); + break; + // printPSBHintOp + case 37: + printPSBHintOp(MI, OpIdx, OS); + break; + // printTypedVectorList<0,'h'> + case 38: + printTypedVectorList(MI, OpIdx, OS, 0, 'h'); + break; + // printTypedVectorList<0,'b'> + case 39: + printTypedVectorList(MI, OpIdx, OS, 0, 'b'); + break; + // printTypedVectorList<16, 'b'> + case 40: + printTypedVectorList(MI, OpIdx, OS, 16, 'b'); + break; + // printTypedVectorList<1, 'd'> + case 41: + printTypedVectorList(MI, OpIdx, OS, 1, 'd'); + break; + // printTypedVectorList<2, 'd'> + case 42: + printTypedVectorList(MI, OpIdx, OS, 2, 'd'); + break; + // printTypedVectorList<2, 's'> + case 43: + printTypedVectorList(MI, OpIdx, OS, 2, 's'); + break; + // printTypedVectorList<4, 'h'> + case 44: + printTypedVectorList(MI, OpIdx, OS, 4, 'h'); + break; + // printTypedVectorList<4, 's'> + case 45: + printTypedVectorList(MI, OpIdx, OS, 4, 's'); + break; + // printTypedVectorList<8, 'b'> + case 46: + printTypedVectorList(MI, OpIdx, OS, 8, 'b'); + break; + // printTypedVectorList<8, 'h'> + case 47: + printTypedVectorList(MI, OpIdx, OS, 8, 'h'); + break; + // printTypedVectorList<0, 'h'> + case 48: + printTypedVectorList(MI, OpIdx, OS, 0, 'h'); + break; + // printTypedVectorList<0, 's'> + case 49: + printTypedVectorList(MI, OpIdx, OS, 0, 's'); + break; + // printTypedVectorList<0, 'd'> + case 50: + printTypedVectorList(MI, OpIdx, OS, 0, 'd'); + break; + // printTypedVectorList<0, 'b'> + case 51: + printTypedVectorList(MI, OpIdx, OS, 0, 'b'); + break; + // printMatrix<0> + case 52: + printMatrix(MI, OpIdx, OS, 0); + break; + // printImmHex + case 53: + printImmHex(MI, OpIdx, OS); + break; + // printPrefetchOp + case 54: + printPrefetchOp(MI, OpIdx, OS, true); + break; + // printPrefetchOp + case 55: + printPrefetchOp(MI, OpIdx, OS, false); + break; + // printGPR64as32 + case 56: + printGPR64as32(MI, OpIdx, OS); + break; + // printSysCROperand + case 57: + printSysCROperand(MI, OpIdx, OS); + break; + } +} + +#endif // PRINT_ALIAS_INSTR +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo3[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo4[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo5[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo6[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo7[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo8[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo9[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo10[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo11[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo12[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo13[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo14[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo15[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo16[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo17[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo18[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo19[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo20[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo21[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo22[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo23[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo24[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo25[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo26[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo27[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo28[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo29[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo30[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo31[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo32[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo33[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo34[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo35[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo36[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo37[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo38[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo39[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo40[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo41[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo42[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo43[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo44[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo45[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo46[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo47[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo48[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo49[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo50[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo51[] = { + {AArch64_GPR64noipRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo52[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo53[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo54[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo55[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR32commonRegClassID, 0, MCOI_OPERAND_REGISTER, + MCOI_EARLY_CLOBBER}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo56[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo57[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo58[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo59[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo60[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo61[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo62[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo63[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo64[] = { + {AArch64_GPR64noipRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo65[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo66[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo67[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo68[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo69[] = { + {AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo70[] = { + {AArch64_ZPR3RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo71[] = { + {AArch64_ZPR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo72[] = { + {AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo73[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo74[] = { + {AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo75[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo76[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo77[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo78[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo79[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo80[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo81[] = { + {AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, + MCOI_EARLY_CLOBBER}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo82[] = { + {AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, + MCOI_EARLY_CLOBBER}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, +}; +static const MCOperandInfo OperandInfo83[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo84[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo85[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo86[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo87[] = { + {AArch64_tcGPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo88[] = { + {AArch64_rtcGPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo89[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo90[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo91[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo92[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo93[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo94[] = { + {AArch64_MPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo95[] = { + {AArch64_MPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo96[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo97[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo98[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo99[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo100[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo101[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo102[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo103[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo104[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo105[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo106[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo107[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo108[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo109[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo110[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo111[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo112[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo113[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo114[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo115[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo116[] = { + {AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo117[] = { + {AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo118[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo119[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo120[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo121[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo122[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo123[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo124[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo125[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo126[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo127[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo128[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo129[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo130[] = { + {AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo131[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo132[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo133[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo134[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo135[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo136[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo137[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo138[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo139[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo140[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo141[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo142[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo143[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo144[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo145[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo146[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo147[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo148[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo149[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo150[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo151[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo152[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo153[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo154[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo155[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo156[] = { + {AArch64_WSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_WSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, + MCOI_TIED_TO /*0*/}, + {AArch64_WSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo157[] = { + {AArch64_XSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_XSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, + MCOI_TIED_TO /*0*/}, + {AArch64_XSeqPairsClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo158[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo159[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo160[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo161[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo162[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo163[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPR_4bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo164[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo165[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo166[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo167[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo168[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo169[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo170[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo171[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo172[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo173[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo174[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo175[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo176[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo177[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo178[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo179[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo180[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo181[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo182[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo183[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo184[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo185[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo186[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo187[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo188[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo189[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo190[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo191[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo192[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo193[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo194[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo195[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo196[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo197[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo198[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo199[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo200[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo201[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo202[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo203[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo204[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo205[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo206[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo207[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo208[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo209[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo210[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo211[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo212[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo213[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo214[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo215[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo216[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo217[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo218[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo219[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo220[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo221[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo222[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo223[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo224[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo225[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo226[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo227[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo228[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo229[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo230[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo231[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo232[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo233[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo234[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo235[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo236[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo237[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo238[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo239[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo240[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo241[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo242[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo243[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo244[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo245[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo246[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo247[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo248[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo249[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo250[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo251[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPR_4bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo252[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo253[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo254[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo255[] = { + {AArch64_MPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo256[] = { + {AArch64_MPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo257[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo258[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo259[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo260[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo261[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo262[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo263[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo264[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo265[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo266[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo267[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo268[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo269[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo270[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo271[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo272[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPR_4bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo273[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo274[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo275[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo276[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo277[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo278[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo279[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo280[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo281[] = { + {AArch64_MPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo282[] = { + {AArch64_MPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo283[] = { + {AArch64_MPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo284[] = { + {AArch64_MPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo285[] = { + {AArch64_MPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo286[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo287[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo288[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo289[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo290[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo291[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo292[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo293[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo294[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo295[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo296[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo297[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo298[] = { + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo299[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo300[] = { + {AArch64_DDDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo301[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_DDDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo302[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo303[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo304[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo305[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo306[] = { + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo307[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo308[] = { + {AArch64_DDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo309[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_DDDRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo310[] = { + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo311[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo312[] = { + {AArch64_DDRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo313[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_DDRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo314[] = { + {AArch64_MPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo315[] = { + {AArch64_MPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo316[] = { + {AArch64_MPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo317[] = { + {AArch64_MPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo318[] = { + {AArch64_MPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo319[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo320[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo321[] = { + {AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo322[] = { + {AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo323[] = { + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo324[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo325[] = { + {AArch64_ZPR3RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo326[] = { + {AArch64_ZPR3RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo327[] = { + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo328[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo329[] = { + {AArch64_ZPR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo330[] = { + {AArch64_ZPR4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo331[] = { + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo332[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo333[] = { + {AArch64_GPR64x8ClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo334[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo335[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo336[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo337[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo338[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo339[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo340[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo341[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo342[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo343[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo344[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo345[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo346[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo347[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo348[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo349[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo350[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo351[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo352[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo353[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo354[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo355[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo356[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo357[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo358[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo359[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo360[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo361[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo362[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo363[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo364[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo365[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo366[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo367[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo368[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo369[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo370[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo371[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo372[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo373[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo374[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo375[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo376[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo377[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo378[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo379[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo380[] = { + {AArch64_MPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo381[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo382[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo383[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo384[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo385[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo386[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo387[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo388[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo389[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo390[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo391[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo392[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo393[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo394[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64commonRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo395[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo396[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo397[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo398[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_MatrixIndexGPR32_12_15RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo399[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo400[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo401[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo402[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo403[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo404[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo405[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo406[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo407[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo408[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo409[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo410[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo411[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo412[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo413[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo414[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo415[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo416[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo417[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo418[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo419[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo420[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo421[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo422[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPR_3bRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo423[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo424[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo425[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo426[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo427[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo428[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo429[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo430[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo431[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128_loRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo432[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo433[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo434[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo435[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo436[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo437[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo438[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo439[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo440[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo441[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo442[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo443[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo444[] = { + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo445[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo446[] = { + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo447[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo448[] = { + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo449[] = { + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo450[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64x8ClassRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo451[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo452[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo453[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo454[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo455[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64spRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo456[] = { + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo457[] = { + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo458[] = { + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo459[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo460[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo461[] = { + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPR2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_ZPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo462[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo463[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo464[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo465[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo466[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo467[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo468[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo469[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo470[] = { + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo471[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo472[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo473[] = { + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo474[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_QQQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo475[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_FPR128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo476[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_QQQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo477[] = { + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {AArch64_QQRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo478[] = { + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo479[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo480[] = { + {AArch64_PPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {AArch64_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; + +extern const MCInstrDesc AArch64Insts[] = { + {1, OperandInfo2}, // Inst #0 = PHI + {0, NULL}, // Inst #1 = INLINEASM + {0, NULL}, // Inst #2 = INLINEASM_BR + {1, OperandInfo3}, // Inst #3 = CFI_INSTRUCTION + {1, OperandInfo3}, // Inst #4 = EH_LABEL + {1, OperandInfo3}, // Inst #5 = GC_LABEL + {1, OperandInfo3}, // Inst #6 = ANNOTATION_LABEL + {0, NULL}, // Inst #7 = KILL + {3, OperandInfo4}, // Inst #8 = EXTRACT_SUBREG + {4, OperandInfo5}, // Inst #9 = INSERT_SUBREG + {1, OperandInfo2}, // Inst #10 = IMPLICIT_DEF + {4, OperandInfo6}, // Inst #11 = SUBREG_TO_REG + {3, OperandInfo4}, // Inst #12 = COPY_TO_REGCLASS + {0, NULL}, // Inst #13 = DBG_VALUE + {0, NULL}, // Inst #14 = DBG_VALUE_LIST + {0, NULL}, // Inst #15 = DBG_INSTR_REF + {0, NULL}, // Inst #16 = DBG_PHI + {1, OperandInfo2}, // Inst #17 = DBG_LABEL + {2, OperandInfo7}, // Inst #18 = REG_SEQUENCE + {2, OperandInfo7}, // Inst #19 = COPY + {0, NULL}, // Inst #20 = BUNDLE + {1, OperandInfo3}, // Inst #21 = LIFETIME_START + {1, OperandInfo3}, // Inst #22 = LIFETIME_END + {4, OperandInfo8}, // Inst #23 = PSEUDO_PROBE + {2, OperandInfo9}, // Inst #24 = ARITH_FENCE + {2, OperandInfo10}, // Inst #25 = STACKMAP + {0, NULL}, // Inst #26 = FENTRY_CALL + {6, OperandInfo11}, // Inst #27 = PATCHPOINT + {1, OperandInfo12}, // Inst #28 = LOAD_STACK_GUARD + {1, OperandInfo3}, // Inst #29 = PREALLOCATED_SETUP + {3, OperandInfo13}, // Inst #30 = PREALLOCATED_ARG + {0, NULL}, // Inst #31 = STATEPOINT + {2, OperandInfo14}, // Inst #32 = LOCAL_ESCAPE + {1, OperandInfo2}, // Inst #33 = FAULTING_OP + {0, NULL}, // Inst #34 = PATCHABLE_OP + {0, NULL}, // Inst #35 = PATCHABLE_FUNCTION_ENTER + {0, NULL}, // Inst #36 = PATCHABLE_RET + {0, NULL}, // Inst #37 = PATCHABLE_FUNCTION_EXIT + {0, NULL}, // Inst #38 = PATCHABLE_TAIL_CALL + {2, OperandInfo15}, // Inst #39 = PATCHABLE_EVENT_CALL + {3, OperandInfo16}, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + {0, NULL}, // Inst #41 = ICALL_BRANCH_FUNNEL + {3, OperandInfo17}, // Inst #42 = G_ASSERT_SEXT + {3, OperandInfo17}, // Inst #43 = G_ASSERT_ZEXT + {3, OperandInfo18}, // Inst #44 = G_ADD + {3, OperandInfo18}, // Inst #45 = G_SUB + {3, OperandInfo18}, // Inst #46 = G_MUL + {3, OperandInfo18}, // Inst #47 = G_SDIV + {3, OperandInfo18}, // Inst #48 = G_UDIV + {3, OperandInfo18}, // Inst #49 = G_SREM + {3, OperandInfo18}, // Inst #50 = G_UREM + {4, OperandInfo19}, // Inst #51 = G_SDIVREM + {4, OperandInfo19}, // Inst #52 = G_UDIVREM + {3, OperandInfo18}, // Inst #53 = G_AND + {3, OperandInfo18}, // Inst #54 = G_OR + {3, OperandInfo18}, // Inst #55 = G_XOR + {1, OperandInfo20}, // Inst #56 = G_IMPLICIT_DEF + {1, OperandInfo20}, // Inst #57 = G_PHI + {2, OperandInfo21}, // Inst #58 = G_FRAME_INDEX + {2, OperandInfo21}, // Inst #59 = G_GLOBAL_VALUE + {3, OperandInfo22}, // Inst #60 = G_EXTRACT + {2, OperandInfo23}, // Inst #61 = G_UNMERGE_VALUES + {4, OperandInfo24}, // Inst #62 = G_INSERT + {2, OperandInfo23}, // Inst #63 = G_MERGE_VALUES + {2, OperandInfo23}, // Inst #64 = G_BUILD_VECTOR + {2, OperandInfo23}, // Inst #65 = G_BUILD_VECTOR_TRUNC + {2, OperandInfo23}, // Inst #66 = G_CONCAT_VECTORS + {2, OperandInfo23}, // Inst #67 = G_PTRTOINT + {2, OperandInfo23}, // Inst #68 = G_INTTOPTR + {2, OperandInfo23}, // Inst #69 = G_BITCAST + {2, OperandInfo25}, // Inst #70 = G_FREEZE + {2, OperandInfo25}, // Inst #71 = G_INTRINSIC_TRUNC + {2, OperandInfo25}, // Inst #72 = G_INTRINSIC_ROUND + {2, OperandInfo23}, // Inst #73 = G_INTRINSIC_LRINT + {2, OperandInfo25}, // Inst #74 = G_INTRINSIC_ROUNDEVEN + {1, OperandInfo20}, // Inst #75 = G_READCYCLECOUNTER + {2, OperandInfo23}, // Inst #76 = G_LOAD + {2, OperandInfo23}, // Inst #77 = G_SEXTLOAD + {2, OperandInfo23}, // Inst #78 = G_ZEXTLOAD + {5, OperandInfo26}, // Inst #79 = G_INDEXED_LOAD + {5, OperandInfo26}, // Inst #80 = G_INDEXED_SEXTLOAD + {5, OperandInfo26}, // Inst #81 = G_INDEXED_ZEXTLOAD + {2, OperandInfo23}, // Inst #82 = G_STORE + {5, OperandInfo27}, // Inst #83 = G_INDEXED_STORE + {5, OperandInfo28}, // Inst #84 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + {4, OperandInfo29}, // Inst #85 = G_ATOMIC_CMPXCHG + {3, OperandInfo30}, // Inst #86 = G_ATOMICRMW_XCHG + {3, OperandInfo30}, // Inst #87 = G_ATOMICRMW_ADD + {3, OperandInfo30}, // Inst #88 = G_ATOMICRMW_SUB + {3, OperandInfo30}, // Inst #89 = G_ATOMICRMW_AND + {3, OperandInfo30}, // Inst #90 = G_ATOMICRMW_NAND + {3, OperandInfo30}, // Inst #91 = G_ATOMICRMW_OR + {3, OperandInfo30}, // Inst #92 = G_ATOMICRMW_XOR + {3, OperandInfo30}, // Inst #93 = G_ATOMICRMW_MAX + {3, OperandInfo30}, // Inst #94 = G_ATOMICRMW_MIN + {3, OperandInfo30}, // Inst #95 = G_ATOMICRMW_UMAX + {3, OperandInfo30}, // Inst #96 = G_ATOMICRMW_UMIN + {3, OperandInfo30}, // Inst #97 = G_ATOMICRMW_FADD + {3, OperandInfo30}, // Inst #98 = G_ATOMICRMW_FSUB + {2, OperandInfo10}, // Inst #99 = G_FENCE + {2, OperandInfo21}, // Inst #100 = G_BRCOND + {1, OperandInfo20}, // Inst #101 = G_BRINDIRECT + {1, OperandInfo2}, // Inst #102 = G_INTRINSIC + {1, OperandInfo2}, // Inst #103 = G_INTRINSIC_W_SIDE_EFFECTS + {2, OperandInfo23}, // Inst #104 = G_ANYEXT + {2, OperandInfo23}, // Inst #105 = G_TRUNC + {2, OperandInfo21}, // Inst #106 = G_CONSTANT + {2, OperandInfo21}, // Inst #107 = G_FCONSTANT + {1, OperandInfo20}, // Inst #108 = G_VASTART + {3, OperandInfo31}, // Inst #109 = G_VAARG + {2, OperandInfo23}, // Inst #110 = G_SEXT + {3, OperandInfo17}, // Inst #111 = G_SEXT_INREG + {2, OperandInfo23}, // Inst #112 = G_ZEXT + {3, OperandInfo32}, // Inst #113 = G_SHL + {3, OperandInfo32}, // Inst #114 = G_LSHR + {3, OperandInfo32}, // Inst #115 = G_ASHR + {4, OperandInfo33}, // Inst #116 = G_FSHL + {4, OperandInfo33}, // Inst #117 = G_FSHR + {3, OperandInfo32}, // Inst #118 = G_ROTR + {3, OperandInfo32}, // Inst #119 = G_ROTL + {4, OperandInfo34}, // Inst #120 = G_ICMP + {4, OperandInfo34}, // Inst #121 = G_FCMP + {4, OperandInfo29}, // Inst #122 = G_SELECT + {4, OperandInfo29}, // Inst #123 = G_UADDO + {5, OperandInfo35}, // Inst #124 = G_UADDE + {4, OperandInfo29}, // Inst #125 = G_USUBO + {5, OperandInfo35}, // Inst #126 = G_USUBE + {4, OperandInfo29}, // Inst #127 = G_SADDO + {5, OperandInfo35}, // Inst #128 = G_SADDE + {4, OperandInfo29}, // Inst #129 = G_SSUBO + {5, OperandInfo35}, // Inst #130 = G_SSUBE + {4, OperandInfo29}, // Inst #131 = G_UMULO + {4, OperandInfo29}, // Inst #132 = G_SMULO + {3, OperandInfo18}, // Inst #133 = G_UMULH + {3, OperandInfo18}, // Inst #134 = G_SMULH + {3, OperandInfo18}, // Inst #135 = G_UADDSAT + {3, OperandInfo18}, // Inst #136 = G_SADDSAT + {3, OperandInfo18}, // Inst #137 = G_USUBSAT + {3, OperandInfo18}, // Inst #138 = G_SSUBSAT + {3, OperandInfo32}, // Inst #139 = G_USHLSAT + {3, OperandInfo32}, // Inst #140 = G_SSHLSAT + {4, OperandInfo36}, // Inst #141 = G_SMULFIX + {4, OperandInfo36}, // Inst #142 = G_UMULFIX + {4, OperandInfo36}, // Inst #143 = G_SMULFIXSAT + {4, OperandInfo36}, // Inst #144 = G_UMULFIXSAT + {4, OperandInfo36}, // Inst #145 = G_SDIVFIX + {4, OperandInfo36}, // Inst #146 = G_UDIVFIX + {4, OperandInfo36}, // Inst #147 = G_SDIVFIXSAT + {4, OperandInfo36}, // Inst #148 = G_UDIVFIXSAT + {3, OperandInfo18}, // Inst #149 = G_FADD + {3, OperandInfo18}, // Inst #150 = G_FSUB + {3, OperandInfo18}, // Inst #151 = G_FMUL + {4, OperandInfo19}, // Inst #152 = G_FMA + {4, OperandInfo19}, // Inst #153 = G_FMAD + {3, OperandInfo18}, // Inst #154 = G_FDIV + {3, OperandInfo18}, // Inst #155 = G_FREM + {3, OperandInfo18}, // Inst #156 = G_FPOW + {3, OperandInfo32}, // Inst #157 = G_FPOWI + {2, OperandInfo25}, // Inst #158 = G_FEXP + {2, OperandInfo25}, // Inst #159 = G_FEXP2 + {2, OperandInfo25}, // Inst #160 = G_FLOG + {2, OperandInfo25}, // Inst #161 = G_FLOG2 + {2, OperandInfo25}, // Inst #162 = G_FLOG10 + {2, OperandInfo25}, // Inst #163 = G_FNEG + {2, OperandInfo23}, // Inst #164 = G_FPEXT + {2, OperandInfo23}, // Inst #165 = G_FPTRUNC + {2, OperandInfo23}, // Inst #166 = G_FPTOSI + {2, OperandInfo23}, // Inst #167 = G_FPTOUI + {2, OperandInfo23}, // Inst #168 = G_SITOFP + {2, OperandInfo23}, // Inst #169 = G_UITOFP + {2, OperandInfo25}, // Inst #170 = G_FABS + {3, OperandInfo32}, // Inst #171 = G_FCOPYSIGN + {2, OperandInfo25}, // Inst #172 = G_FCANONICALIZE + {3, OperandInfo18}, // Inst #173 = G_FMINNUM + {3, OperandInfo18}, // Inst #174 = G_FMAXNUM + {3, OperandInfo18}, // Inst #175 = G_FMINNUM_IEEE + {3, OperandInfo18}, // Inst #176 = G_FMAXNUM_IEEE + {3, OperandInfo18}, // Inst #177 = G_FMINIMUM + {3, OperandInfo18}, // Inst #178 = G_FMAXIMUM + {3, OperandInfo32}, // Inst #179 = G_PTR_ADD + {3, OperandInfo32}, // Inst #180 = G_PTRMASK + {3, OperandInfo18}, // Inst #181 = G_SMIN + {3, OperandInfo18}, // Inst #182 = G_SMAX + {3, OperandInfo18}, // Inst #183 = G_UMIN + {3, OperandInfo18}, // Inst #184 = G_UMAX + {2, OperandInfo25}, // Inst #185 = G_ABS + {2, OperandInfo23}, // Inst #186 = G_LROUND + {2, OperandInfo23}, // Inst #187 = G_LLROUND + {1, OperandInfo2}, // Inst #188 = G_BR + {3, OperandInfo37}, // Inst #189 = G_BRJT + {4, OperandInfo38}, // Inst #190 = G_INSERT_VECTOR_ELT + {3, OperandInfo39}, // Inst #191 = G_EXTRACT_VECTOR_ELT + {4, OperandInfo40}, // Inst #192 = G_SHUFFLE_VECTOR + {2, OperandInfo23}, // Inst #193 = G_CTTZ + {2, OperandInfo23}, // Inst #194 = G_CTTZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #195 = G_CTLZ + {2, OperandInfo23}, // Inst #196 = G_CTLZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #197 = G_CTPOP + {2, OperandInfo25}, // Inst #198 = G_BSWAP + {2, OperandInfo25}, // Inst #199 = G_BITREVERSE + {2, OperandInfo25}, // Inst #200 = G_FCEIL + {2, OperandInfo25}, // Inst #201 = G_FCOS + {2, OperandInfo25}, // Inst #202 = G_FSIN + {2, OperandInfo25}, // Inst #203 = G_FSQRT + {2, OperandInfo25}, // Inst #204 = G_FFLOOR + {2, OperandInfo25}, // Inst #205 = G_FRINT + {2, OperandInfo25}, // Inst #206 = G_FNEARBYINT + {2, OperandInfo23}, // Inst #207 = G_ADDRSPACE_CAST + {2, OperandInfo21}, // Inst #208 = G_BLOCK_ADDR + {2, OperandInfo21}, // Inst #209 = G_JUMP_TABLE + {3, OperandInfo22}, // Inst #210 = G_DYN_STACKALLOC + {3, OperandInfo18}, // Inst #211 = G_STRICT_FADD + {3, OperandInfo18}, // Inst #212 = G_STRICT_FSUB + {3, OperandInfo18}, // Inst #213 = G_STRICT_FMUL + {3, OperandInfo18}, // Inst #214 = G_STRICT_FDIV + {3, OperandInfo18}, // Inst #215 = G_STRICT_FREM + {4, OperandInfo19}, // Inst #216 = G_STRICT_FMA + {2, OperandInfo25}, // Inst #217 = G_STRICT_FSQRT + {2, OperandInfo21}, // Inst #218 = G_READ_REGISTER + {2, OperandInfo41}, // Inst #219 = G_WRITE_REGISTER + {4, OperandInfo42}, // Inst #220 = G_MEMCPY + {3, OperandInfo39}, // Inst #221 = G_MEMCPY_INLINE + {4, OperandInfo42}, // Inst #222 = G_MEMMOVE + {4, OperandInfo42}, // Inst #223 = G_MEMSET + {3, OperandInfo22}, // Inst #224 = G_BZERO + {3, OperandInfo39}, // Inst #225 = G_VECREDUCE_SEQ_FADD + {3, OperandInfo39}, // Inst #226 = G_VECREDUCE_SEQ_FMUL + {2, OperandInfo23}, // Inst #227 = G_VECREDUCE_FADD + {2, OperandInfo23}, // Inst #228 = G_VECREDUCE_FMUL + {2, OperandInfo23}, // Inst #229 = G_VECREDUCE_FMAX + {2, OperandInfo23}, // Inst #230 = G_VECREDUCE_FMIN + {2, OperandInfo23}, // Inst #231 = G_VECREDUCE_ADD + {2, OperandInfo23}, // Inst #232 = G_VECREDUCE_MUL + {2, OperandInfo23}, // Inst #233 = G_VECREDUCE_AND + {2, OperandInfo23}, // Inst #234 = G_VECREDUCE_OR + {2, OperandInfo23}, // Inst #235 = G_VECREDUCE_XOR + {2, OperandInfo23}, // Inst #236 = G_VECREDUCE_SMAX + {2, OperandInfo23}, // Inst #237 = G_VECREDUCE_SMIN + {2, OperandInfo23}, // Inst #238 = G_VECREDUCE_UMAX + {2, OperandInfo23}, // Inst #239 = G_VECREDUCE_UMIN + {4, OperandInfo43}, // Inst #240 = G_SBFX + {4, OperandInfo43}, // Inst #241 = G_UBFX + {4, OperandInfo44}, // Inst #242 = ABS_ZPmZ_UNDEF_B + {4, OperandInfo44}, // Inst #243 = ABS_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #244 = ABS_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #245 = ABS_ZPmZ_UNDEF_S + {3, OperandInfo45}, // Inst #246 = ADDSWrr + {3, OperandInfo46}, // Inst #247 = ADDSXrr + {3, OperandInfo45}, // Inst #248 = ADDWrr + {3, OperandInfo46}, // Inst #249 = ADDXrr + {4, OperandInfo47}, // Inst #250 = ADD_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #251 = ADD_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #252 = ADD_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #253 = ADD_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #254 = ADD_ZPZZ_ZERO_B + {4, OperandInfo47}, // Inst #255 = ADD_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #256 = ADD_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #257 = ADD_ZPZZ_ZERO_S + {3, OperandInfo48}, // Inst #258 = ADDlowTLS + {2, OperandInfo10}, // Inst #259 = ADJCALLSTACKDOWN + {2, OperandInfo10}, // Inst #260 = ADJCALLSTACKUP + {2, OperandInfo49}, // Inst #261 = AESIMCrrTied + {2, OperandInfo49}, // Inst #262 = AESMCrrTied + {3, OperandInfo45}, // Inst #263 = ANDSWrr + {3, OperandInfo46}, // Inst #264 = ANDSXrr + {3, OperandInfo45}, // Inst #265 = ANDWrr + {3, OperandInfo46}, // Inst #266 = ANDXrr + {4, OperandInfo50}, // Inst #267 = ASRD_ZPZI_ZERO_B + {4, OperandInfo50}, // Inst #268 = ASRD_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #269 = ASRD_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #270 = ASRD_ZPZI_ZERO_S + {4, OperandInfo50}, // Inst #271 = ASR_ZPZI_UNDEF_B + {4, OperandInfo50}, // Inst #272 = ASR_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #273 = ASR_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #274 = ASR_ZPZI_UNDEF_S + {4, OperandInfo47}, // Inst #275 = ASR_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #276 = ASR_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #277 = ASR_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #278 = ASR_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #279 = ASR_ZPZZ_ZERO_B + {4, OperandInfo47}, // Inst #280 = ASR_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #281 = ASR_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #282 = ASR_ZPZZ_ZERO_S + {3, OperandInfo45}, // Inst #283 = BICSWrr + {3, OperandInfo46}, // Inst #284 = BICSXrr + {3, OperandInfo45}, // Inst #285 = BICWrr + {3, OperandInfo46}, // Inst #286 = BICXrr + {1, OperandInfo51}, // Inst #287 = BLRNoIP + {0, NULL}, // Inst #288 = BLR_RVMARKER + {4, OperandInfo52}, // Inst #289 = BSPv16i8 + {4, OperandInfo53}, // Inst #290 = BSPv8i8 + {2, OperandInfo54}, // Inst #291 = CATCHRET + {0, NULL}, // Inst #292 = CLEANUPRET + {4, OperandInfo44}, // Inst #293 = CLS_ZPmZ_UNDEF_B + {4, OperandInfo44}, // Inst #294 = CLS_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #295 = CLS_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #296 = CLS_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #297 = CLZ_ZPmZ_UNDEF_B + {4, OperandInfo44}, // Inst #298 = CLZ_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #299 = CLZ_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #300 = CLZ_ZPmZ_UNDEF_S + {8, OperandInfo55}, // Inst #301 = CMP_SWAP_128 + {8, OperandInfo55}, // Inst #302 = CMP_SWAP_128_ACQUIRE + {8, OperandInfo55}, // Inst #303 = CMP_SWAP_128_MONOTONIC + {8, OperandInfo55}, // Inst #304 = CMP_SWAP_128_RELEASE + {5, OperandInfo56}, // Inst #305 = CMP_SWAP_16 + {5, OperandInfo56}, // Inst #306 = CMP_SWAP_32 + {5, OperandInfo57}, // Inst #307 = CMP_SWAP_64 + {5, OperandInfo56}, // Inst #308 = CMP_SWAP_8 + {4, OperandInfo44}, // Inst #309 = CNOT_ZPmZ_UNDEF_B + {4, OperandInfo44}, // Inst #310 = CNOT_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #311 = CNOT_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #312 = CNOT_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #313 = CNT_ZPmZ_UNDEF_B + {4, OperandInfo44}, // Inst #314 = CNT_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #315 = CNT_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #316 = CNT_ZPmZ_UNDEF_S + {1, OperandInfo3}, // Inst #317 = CompilerBarrier + {0, NULL}, // Inst #318 = EMITBKEY + {3, OperandInfo45}, // Inst #319 = EONWrr + {3, OperandInfo46}, // Inst #320 = EONXrr + {3, OperandInfo45}, // Inst #321 = EORWrr + {3, OperandInfo46}, // Inst #322 = EORXrr + {4, OperandInfo58}, // Inst #323 = F128CSEL + {4, OperandInfo47}, // Inst #324 = FABD_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #325 = FABD_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #326 = FABD_ZPZZ_ZERO_S + {4, OperandInfo44}, // Inst #327 = FABS_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #328 = FABS_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #329 = FABS_ZPmZ_UNDEF_S + {4, OperandInfo50}, // Inst #330 = FADD_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #331 = FADD_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #332 = FADD_ZPZI_UNDEF_S + {4, OperandInfo50}, // Inst #333 = FADD_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #334 = FADD_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #335 = FADD_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #336 = FADD_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #337 = FADD_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #338 = FADD_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #339 = FADD_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #340 = FADD_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #341 = FADD_ZPZZ_ZERO_S + {4, OperandInfo47}, // Inst #342 = FDIVR_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #343 = FDIVR_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #344 = FDIVR_ZPZZ_ZERO_S + {4, OperandInfo47}, // Inst #345 = FDIV_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #346 = FDIV_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #347 = FDIV_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #348 = FDIV_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #349 = FDIV_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #350 = FDIV_ZPZZ_ZERO_S + {4, OperandInfo50}, // Inst #351 = FMAXNM_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #352 = FMAXNM_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #353 = FMAXNM_ZPZI_UNDEF_S + {4, OperandInfo50}, // Inst #354 = FMAXNM_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #355 = FMAXNM_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #356 = FMAXNM_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #357 = FMAXNM_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #358 = FMAXNM_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #359 = FMAXNM_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #360 = FMAXNM_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #361 = FMAXNM_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #362 = FMAXNM_ZPZZ_ZERO_S + {4, OperandInfo50}, // Inst #363 = FMAX_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #364 = FMAX_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #365 = FMAX_ZPZI_UNDEF_S + {4, OperandInfo50}, // Inst #366 = FMAX_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #367 = FMAX_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #368 = FMAX_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #369 = FMAX_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #370 = FMAX_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #371 = FMAX_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #372 = FMAX_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #373 = FMAX_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #374 = FMAX_ZPZZ_ZERO_S + {4, OperandInfo50}, // Inst #375 = FMINNM_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #376 = FMINNM_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #377 = FMINNM_ZPZI_UNDEF_S + {4, OperandInfo50}, // Inst #378 = FMINNM_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #379 = FMINNM_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #380 = FMINNM_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #381 = FMINNM_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #382 = FMINNM_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #383 = FMINNM_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #384 = FMINNM_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #385 = FMINNM_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #386 = FMINNM_ZPZZ_ZERO_S + {4, OperandInfo50}, // Inst #387 = FMIN_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #388 = FMIN_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #389 = FMIN_ZPZI_UNDEF_S + {4, OperandInfo50}, // Inst #390 = FMIN_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #391 = FMIN_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #392 = FMIN_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #393 = FMIN_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #394 = FMIN_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #395 = FMIN_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #396 = FMIN_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #397 = FMIN_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #398 = FMIN_ZPZZ_ZERO_S + {5, OperandInfo59}, // Inst #399 = FMLA_ZPZZZ_UNDEF_D + {5, OperandInfo59}, // Inst #400 = FMLA_ZPZZZ_UNDEF_H + {5, OperandInfo59}, // Inst #401 = FMLA_ZPZZZ_UNDEF_S + {5, OperandInfo59}, // Inst #402 = FMLS_ZPZZZ_UNDEF_D + {5, OperandInfo59}, // Inst #403 = FMLS_ZPZZZ_UNDEF_H + {5, OperandInfo59}, // Inst #404 = FMLS_ZPZZZ_UNDEF_S + {1, OperandInfo60}, // Inst #405 = FMOVD0 + {1, OperandInfo61}, // Inst #406 = FMOVH0 + {1, OperandInfo62}, // Inst #407 = FMOVS0 + {4, OperandInfo47}, // Inst #408 = FMULX_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #409 = FMULX_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #410 = FMULX_ZPZZ_ZERO_S + {4, OperandInfo50}, // Inst #411 = FMUL_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #412 = FMUL_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #413 = FMUL_ZPZI_UNDEF_S + {4, OperandInfo50}, // Inst #414 = FMUL_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #415 = FMUL_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #416 = FMUL_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #417 = FMUL_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #418 = FMUL_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #419 = FMUL_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #420 = FMUL_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #421 = FMUL_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #422 = FMUL_ZPZZ_ZERO_S + {4, OperandInfo44}, // Inst #423 = FNEG_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #424 = FNEG_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #425 = FNEG_ZPmZ_UNDEF_S + {5, OperandInfo59}, // Inst #426 = FNMLA_ZPZZZ_UNDEF_D + {5, OperandInfo59}, // Inst #427 = FNMLA_ZPZZZ_UNDEF_H + {5, OperandInfo59}, // Inst #428 = FNMLA_ZPZZZ_UNDEF_S + {5, OperandInfo59}, // Inst #429 = FNMLS_ZPZZZ_UNDEF_D + {5, OperandInfo59}, // Inst #430 = FNMLS_ZPZZZ_UNDEF_H + {5, OperandInfo59}, // Inst #431 = FNMLS_ZPZZZ_UNDEF_S + {4, OperandInfo44}, // Inst #432 = FRECPX_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #433 = FRECPX_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #434 = FRECPX_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #435 = FRINTA_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #436 = FRINTA_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #437 = FRINTA_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #438 = FRINTI_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #439 = FRINTI_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #440 = FRINTI_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #441 = FRINTM_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #442 = FRINTM_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #443 = FRINTM_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #444 = FRINTN_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #445 = FRINTN_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #446 = FRINTN_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #447 = FRINTP_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #448 = FRINTP_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #449 = FRINTP_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #450 = FRINTX_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #451 = FRINTX_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #452 = FRINTX_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #453 = FRINTZ_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #454 = FRINTZ_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #455 = FRINTZ_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #456 = FSQRT_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #457 = FSQRT_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #458 = FSQRT_ZPmZ_UNDEF_S + {4, OperandInfo50}, // Inst #459 = FSUBR_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #460 = FSUBR_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #461 = FSUBR_ZPZI_UNDEF_S + {4, OperandInfo50}, // Inst #462 = FSUBR_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #463 = FSUBR_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #464 = FSUBR_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #465 = FSUBR_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #466 = FSUBR_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #467 = FSUBR_ZPZZ_ZERO_S + {4, OperandInfo50}, // Inst #468 = FSUB_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #469 = FSUB_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #470 = FSUB_ZPZI_UNDEF_S + {4, OperandInfo50}, // Inst #471 = FSUB_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #472 = FSUB_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #473 = FSUB_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #474 = FSUB_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #475 = FSUB_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #476 = FSUB_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #477 = FSUB_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #478 = FSUB_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #479 = FSUB_ZPZZ_ZERO_S + {4, OperandInfo63}, // Inst #480 = GLD1B_D + {4, OperandInfo50}, // Inst #481 = GLD1B_D_IMM + {4, OperandInfo63}, // Inst #482 = GLD1B_D_SXTW + {4, OperandInfo63}, // Inst #483 = GLD1B_D_UXTW + {4, OperandInfo50}, // Inst #484 = GLD1B_S_IMM + {4, OperandInfo63}, // Inst #485 = GLD1B_S_SXTW + {4, OperandInfo63}, // Inst #486 = GLD1B_S_UXTW + {4, OperandInfo63}, // Inst #487 = GLD1D + {4, OperandInfo50}, // Inst #488 = GLD1D_IMM + {4, OperandInfo63}, // Inst #489 = GLD1D_SCALED + {4, OperandInfo63}, // Inst #490 = GLD1D_SXTW + {4, OperandInfo63}, // Inst #491 = GLD1D_SXTW_SCALED + {4, OperandInfo63}, // Inst #492 = GLD1D_UXTW + {4, OperandInfo63}, // Inst #493 = GLD1D_UXTW_SCALED + {4, OperandInfo63}, // Inst #494 = GLD1H_D + {4, OperandInfo50}, // Inst #495 = GLD1H_D_IMM + {4, OperandInfo63}, // Inst #496 = GLD1H_D_SCALED + {4, OperandInfo63}, // Inst #497 = GLD1H_D_SXTW + {4, OperandInfo63}, // Inst #498 = GLD1H_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #499 = GLD1H_D_UXTW + {4, OperandInfo63}, // Inst #500 = GLD1H_D_UXTW_SCALED + {4, OperandInfo50}, // Inst #501 = GLD1H_S_IMM + {4, OperandInfo63}, // Inst #502 = GLD1H_S_SXTW + {4, OperandInfo63}, // Inst #503 = GLD1H_S_SXTW_SCALED + {4, OperandInfo63}, // Inst #504 = GLD1H_S_UXTW + {4, OperandInfo63}, // Inst #505 = GLD1H_S_UXTW_SCALED + {4, OperandInfo63}, // Inst #506 = GLD1SB_D + {4, OperandInfo50}, // Inst #507 = GLD1SB_D_IMM + {4, OperandInfo63}, // Inst #508 = GLD1SB_D_SXTW + {4, OperandInfo63}, // Inst #509 = GLD1SB_D_UXTW + {4, OperandInfo50}, // Inst #510 = GLD1SB_S_IMM + {4, OperandInfo63}, // Inst #511 = GLD1SB_S_SXTW + {4, OperandInfo63}, // Inst #512 = GLD1SB_S_UXTW + {4, OperandInfo63}, // Inst #513 = GLD1SH_D + {4, OperandInfo50}, // Inst #514 = GLD1SH_D_IMM + {4, OperandInfo63}, // Inst #515 = GLD1SH_D_SCALED + {4, OperandInfo63}, // Inst #516 = GLD1SH_D_SXTW + {4, OperandInfo63}, // Inst #517 = GLD1SH_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #518 = GLD1SH_D_UXTW + {4, OperandInfo63}, // Inst #519 = GLD1SH_D_UXTW_SCALED + {4, OperandInfo50}, // Inst #520 = GLD1SH_S_IMM + {4, OperandInfo63}, // Inst #521 = GLD1SH_S_SXTW + {4, OperandInfo63}, // Inst #522 = GLD1SH_S_SXTW_SCALED + {4, OperandInfo63}, // Inst #523 = GLD1SH_S_UXTW + {4, OperandInfo63}, // Inst #524 = GLD1SH_S_UXTW_SCALED + {4, OperandInfo63}, // Inst #525 = GLD1SW_D + {4, OperandInfo50}, // Inst #526 = GLD1SW_D_IMM + {4, OperandInfo63}, // Inst #527 = GLD1SW_D_SCALED + {4, OperandInfo63}, // Inst #528 = GLD1SW_D_SXTW + {4, OperandInfo63}, // Inst #529 = GLD1SW_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #530 = GLD1SW_D_UXTW + {4, OperandInfo63}, // Inst #531 = GLD1SW_D_UXTW_SCALED + {4, OperandInfo63}, // Inst #532 = GLD1W_D + {4, OperandInfo50}, // Inst #533 = GLD1W_D_IMM + {4, OperandInfo63}, // Inst #534 = GLD1W_D_SCALED + {4, OperandInfo63}, // Inst #535 = GLD1W_D_SXTW + {4, OperandInfo63}, // Inst #536 = GLD1W_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #537 = GLD1W_D_UXTW + {4, OperandInfo63}, // Inst #538 = GLD1W_D_UXTW_SCALED + {4, OperandInfo50}, // Inst #539 = GLD1W_IMM + {4, OperandInfo63}, // Inst #540 = GLD1W_SXTW + {4, OperandInfo63}, // Inst #541 = GLD1W_SXTW_SCALED + {4, OperandInfo63}, // Inst #542 = GLD1W_UXTW + {4, OperandInfo63}, // Inst #543 = GLD1W_UXTW_SCALED + {4, OperandInfo63}, // Inst #544 = GLDFF1B_D + {4, OperandInfo50}, // Inst #545 = GLDFF1B_D_IMM + {4, OperandInfo63}, // Inst #546 = GLDFF1B_D_SXTW + {4, OperandInfo63}, // Inst #547 = GLDFF1B_D_UXTW + {4, OperandInfo50}, // Inst #548 = GLDFF1B_S_IMM + {4, OperandInfo63}, // Inst #549 = GLDFF1B_S_SXTW + {4, OperandInfo63}, // Inst #550 = GLDFF1B_S_UXTW + {4, OperandInfo63}, // Inst #551 = GLDFF1D + {4, OperandInfo50}, // Inst #552 = GLDFF1D_IMM + {4, OperandInfo63}, // Inst #553 = GLDFF1D_SCALED + {4, OperandInfo63}, // Inst #554 = GLDFF1D_SXTW + {4, OperandInfo63}, // Inst #555 = GLDFF1D_SXTW_SCALED + {4, OperandInfo63}, // Inst #556 = GLDFF1D_UXTW + {4, OperandInfo63}, // Inst #557 = GLDFF1D_UXTW_SCALED + {4, OperandInfo63}, // Inst #558 = GLDFF1H_D + {4, OperandInfo50}, // Inst #559 = GLDFF1H_D_IMM + {4, OperandInfo63}, // Inst #560 = GLDFF1H_D_SCALED + {4, OperandInfo63}, // Inst #561 = GLDFF1H_D_SXTW + {4, OperandInfo63}, // Inst #562 = GLDFF1H_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #563 = GLDFF1H_D_UXTW + {4, OperandInfo63}, // Inst #564 = GLDFF1H_D_UXTW_SCALED + {4, OperandInfo50}, // Inst #565 = GLDFF1H_S_IMM + {4, OperandInfo63}, // Inst #566 = GLDFF1H_S_SXTW + {4, OperandInfo63}, // Inst #567 = GLDFF1H_S_SXTW_SCALED + {4, OperandInfo63}, // Inst #568 = GLDFF1H_S_UXTW + {4, OperandInfo63}, // Inst #569 = GLDFF1H_S_UXTW_SCALED + {4, OperandInfo63}, // Inst #570 = GLDFF1SB_D + {4, OperandInfo50}, // Inst #571 = GLDFF1SB_D_IMM + {4, OperandInfo63}, // Inst #572 = GLDFF1SB_D_SXTW + {4, OperandInfo63}, // Inst #573 = GLDFF1SB_D_UXTW + {4, OperandInfo50}, // Inst #574 = GLDFF1SB_S_IMM + {4, OperandInfo63}, // Inst #575 = GLDFF1SB_S_SXTW + {4, OperandInfo63}, // Inst #576 = GLDFF1SB_S_UXTW + {4, OperandInfo63}, // Inst #577 = GLDFF1SH_D + {4, OperandInfo50}, // Inst #578 = GLDFF1SH_D_IMM + {4, OperandInfo63}, // Inst #579 = GLDFF1SH_D_SCALED + {4, OperandInfo63}, // Inst #580 = GLDFF1SH_D_SXTW + {4, OperandInfo63}, // Inst #581 = GLDFF1SH_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #582 = GLDFF1SH_D_UXTW + {4, OperandInfo63}, // Inst #583 = GLDFF1SH_D_UXTW_SCALED + {4, OperandInfo50}, // Inst #584 = GLDFF1SH_S_IMM + {4, OperandInfo63}, // Inst #585 = GLDFF1SH_S_SXTW + {4, OperandInfo63}, // Inst #586 = GLDFF1SH_S_SXTW_SCALED + {4, OperandInfo63}, // Inst #587 = GLDFF1SH_S_UXTW + {4, OperandInfo63}, // Inst #588 = GLDFF1SH_S_UXTW_SCALED + {4, OperandInfo63}, // Inst #589 = GLDFF1SW_D + {4, OperandInfo50}, // Inst #590 = GLDFF1SW_D_IMM + {4, OperandInfo63}, // Inst #591 = GLDFF1SW_D_SCALED + {4, OperandInfo63}, // Inst #592 = GLDFF1SW_D_SXTW + {4, OperandInfo63}, // Inst #593 = GLDFF1SW_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #594 = GLDFF1SW_D_UXTW + {4, OperandInfo63}, // Inst #595 = GLDFF1SW_D_UXTW_SCALED + {4, OperandInfo63}, // Inst #596 = GLDFF1W_D + {4, OperandInfo50}, // Inst #597 = GLDFF1W_D_IMM + {4, OperandInfo63}, // Inst #598 = GLDFF1W_D_SCALED + {4, OperandInfo63}, // Inst #599 = GLDFF1W_D_SXTW + {4, OperandInfo63}, // Inst #600 = GLDFF1W_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #601 = GLDFF1W_D_UXTW + {4, OperandInfo63}, // Inst #602 = GLDFF1W_D_UXTW_SCALED + {4, OperandInfo50}, // Inst #603 = GLDFF1W_IMM + {4, OperandInfo63}, // Inst #604 = GLDFF1W_SXTW + {4, OperandInfo63}, // Inst #605 = GLDFF1W_SXTW_SCALED + {4, OperandInfo63}, // Inst #606 = GLDFF1W_UXTW + {4, OperandInfo63}, // Inst #607 = GLDFF1W_UXTW_SCALED + {3, OperandInfo39}, // Inst #608 = G_ADD_LOW + {2, OperandInfo23}, // Inst #609 = G_DUP + {3, OperandInfo32}, // Inst #610 = G_DUPLANE16 + {3, OperandInfo32}, // Inst #611 = G_DUPLANE32 + {3, OperandInfo32}, // Inst #612 = G_DUPLANE64 + {3, OperandInfo32}, // Inst #613 = G_DUPLANE8 + {4, OperandInfo36}, // Inst #614 = G_EXT + {3, OperandInfo32}, // Inst #615 = G_FCMEQ + {2, OperandInfo25}, // Inst #616 = G_FCMEQZ + {3, OperandInfo32}, // Inst #617 = G_FCMGE + {2, OperandInfo25}, // Inst #618 = G_FCMGEZ + {3, OperandInfo32}, // Inst #619 = G_FCMGT + {2, OperandInfo25}, // Inst #620 = G_FCMGTZ + {2, OperandInfo25}, // Inst #621 = G_FCMLEZ + {2, OperandInfo25}, // Inst #622 = G_FCMLTZ + {2, OperandInfo25}, // Inst #623 = G_REV16 + {2, OperandInfo25}, // Inst #624 = G_REV32 + {2, OperandInfo25}, // Inst #625 = G_REV64 + {2, OperandInfo25}, // Inst #626 = G_SITOF + {3, OperandInfo18}, // Inst #627 = G_TRN1 + {3, OperandInfo18}, // Inst #628 = G_TRN2 + {2, OperandInfo25}, // Inst #629 = G_UITOF + {3, OperandInfo18}, // Inst #630 = G_UZP1 + {3, OperandInfo18}, // Inst #631 = G_UZP2 + {3, OperandInfo17}, // Inst #632 = G_VASHR + {3, OperandInfo17}, // Inst #633 = G_VLSHR + {3, OperandInfo18}, // Inst #634 = G_ZIP1 + {3, OperandInfo18}, // Inst #635 = G_ZIP2 + {0, NULL}, // Inst #636 = HOM_Epilog + {0, NULL}, // Inst #637 = HOM_Prolog + {2, OperandInfo64}, // Inst #638 = HWASAN_CHECK_MEMACCESS + {2, OperandInfo64}, // Inst #639 = HWASAN_CHECK_MEMACCESS_SHORTGRANULES + {3, OperandInfo65}, // Inst #640 = IRGstack + {5, OperandInfo66}, // Inst #641 = JumpTableDest16 + {5, OperandInfo66}, // Inst #642 = JumpTableDest32 + {5, OperandInfo66}, // Inst #643 = JumpTableDest8 + {4, OperandInfo67}, // Inst #644 = LD1B_D_IMM + {4, OperandInfo67}, // Inst #645 = LD1B_H_IMM + {4, OperandInfo67}, // Inst #646 = LD1B_IMM + {4, OperandInfo67}, // Inst #647 = LD1B_S_IMM + {4, OperandInfo67}, // Inst #648 = LD1D_IMM + {4, OperandInfo67}, // Inst #649 = LD1H_D_IMM + {4, OperandInfo67}, // Inst #650 = LD1H_IMM + {4, OperandInfo67}, // Inst #651 = LD1H_S_IMM + {4, OperandInfo67}, // Inst #652 = LD1SB_D_IMM + {4, OperandInfo67}, // Inst #653 = LD1SB_H_IMM + {4, OperandInfo67}, // Inst #654 = LD1SB_S_IMM + {4, OperandInfo67}, // Inst #655 = LD1SH_D_IMM + {4, OperandInfo67}, // Inst #656 = LD1SH_S_IMM + {4, OperandInfo67}, // Inst #657 = LD1SW_D_IMM + {4, OperandInfo67}, // Inst #658 = LD1W_D_IMM + {4, OperandInfo67}, // Inst #659 = LD1W_IMM + {4, OperandInfo68}, // Inst #660 = LDFF1B + {4, OperandInfo68}, // Inst #661 = LDFF1B_D + {4, OperandInfo68}, // Inst #662 = LDFF1B_H + {4, OperandInfo68}, // Inst #663 = LDFF1B_S + {4, OperandInfo68}, // Inst #664 = LDFF1D + {4, OperandInfo68}, // Inst #665 = LDFF1H + {4, OperandInfo68}, // Inst #666 = LDFF1H_D + {4, OperandInfo68}, // Inst #667 = LDFF1H_S + {4, OperandInfo68}, // Inst #668 = LDFF1SB_D + {4, OperandInfo68}, // Inst #669 = LDFF1SB_H + {4, OperandInfo68}, // Inst #670 = LDFF1SB_S + {4, OperandInfo68}, // Inst #671 = LDFF1SH_D + {4, OperandInfo68}, // Inst #672 = LDFF1SH_S + {4, OperandInfo68}, // Inst #673 = LDFF1SW_D + {4, OperandInfo68}, // Inst #674 = LDFF1W + {4, OperandInfo68}, // Inst #675 = LDFF1W_D + {4, OperandInfo67}, // Inst #676 = LDNF1B_D_IMM + {4, OperandInfo67}, // Inst #677 = LDNF1B_H_IMM + {4, OperandInfo67}, // Inst #678 = LDNF1B_IMM + {4, OperandInfo67}, // Inst #679 = LDNF1B_S_IMM + {4, OperandInfo67}, // Inst #680 = LDNF1D_IMM + {4, OperandInfo67}, // Inst #681 = LDNF1H_D_IMM + {4, OperandInfo67}, // Inst #682 = LDNF1H_IMM + {4, OperandInfo67}, // Inst #683 = LDNF1H_S_IMM + {4, OperandInfo67}, // Inst #684 = LDNF1SB_D_IMM + {4, OperandInfo67}, // Inst #685 = LDNF1SB_H_IMM + {4, OperandInfo67}, // Inst #686 = LDNF1SB_S_IMM + {4, OperandInfo67}, // Inst #687 = LDNF1SH_D_IMM + {4, OperandInfo67}, // Inst #688 = LDNF1SH_S_IMM + {4, OperandInfo67}, // Inst #689 = LDNF1SW_D_IMM + {4, OperandInfo67}, // Inst #690 = LDNF1W_D_IMM + {4, OperandInfo67}, // Inst #691 = LDNF1W_IMM + {3, OperandInfo69}, // Inst #692 = LDR_ZZXI + {3, OperandInfo70}, // Inst #693 = LDR_ZZZXI + {3, OperandInfo71}, // Inst #694 = LDR_ZZZZXI + {2, OperandInfo72}, // Inst #695 = LOADgot + {4, OperandInfo50}, // Inst #696 = LSL_ZPZI_UNDEF_B + {4, OperandInfo50}, // Inst #697 = LSL_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #698 = LSL_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #699 = LSL_ZPZI_UNDEF_S + {4, OperandInfo47}, // Inst #700 = LSL_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #701 = LSL_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #702 = LSL_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #703 = LSL_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #704 = LSL_ZPZZ_ZERO_B + {4, OperandInfo47}, // Inst #705 = LSL_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #706 = LSL_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #707 = LSL_ZPZZ_ZERO_S + {4, OperandInfo50}, // Inst #708 = LSR_ZPZI_UNDEF_B + {4, OperandInfo50}, // Inst #709 = LSR_ZPZI_UNDEF_D + {4, OperandInfo50}, // Inst #710 = LSR_ZPZI_UNDEF_H + {4, OperandInfo50}, // Inst #711 = LSR_ZPZI_UNDEF_S + {4, OperandInfo47}, // Inst #712 = LSR_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #713 = LSR_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #714 = LSR_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #715 = LSR_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #716 = LSR_ZPZZ_ZERO_B + {4, OperandInfo47}, // Inst #717 = LSR_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #718 = LSR_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #719 = LSR_ZPZZ_ZERO_S + {2, OperandInfo73}, // Inst #720 = MOVMCSym + {3, OperandInfo74}, // Inst #721 = MOVaddr + {3, OperandInfo74}, // Inst #722 = MOVaddrBA + {3, OperandInfo74}, // Inst #723 = MOVaddrCP + {3, OperandInfo74}, // Inst #724 = MOVaddrEXT + {3, OperandInfo74}, // Inst #725 = MOVaddrJT + {3, OperandInfo74}, // Inst #726 = MOVaddrTLS + {1, OperandInfo75}, // Inst #727 = MOVbaseTLS + {2, OperandInfo76}, // Inst #728 = MOVi32imm + {2, OperandInfo73}, // Inst #729 = MOVi64imm + {4, OperandInfo47}, // Inst #730 = MUL_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #731 = MUL_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #732 = MUL_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #733 = MUL_ZPZZ_UNDEF_S + {4, OperandInfo44}, // Inst #734 = NEG_ZPmZ_UNDEF_B + {4, OperandInfo44}, // Inst #735 = NEG_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #736 = NEG_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #737 = NEG_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #738 = NOT_ZPmZ_UNDEF_B + {4, OperandInfo44}, // Inst #739 = NOT_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #740 = NOT_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #741 = NOT_ZPmZ_UNDEF_S + {3, OperandInfo45}, // Inst #742 = ORNWrr + {3, OperandInfo46}, // Inst #743 = ORNXrr + {3, OperandInfo45}, // Inst #744 = ORRWrr + {3, OperandInfo46}, // Inst #745 = ORRXrr + {1, OperandInfo77}, // Inst #746 = RDFFR_P + {2, OperandInfo78}, // Inst #747 = RDFFR_PPz + {0, NULL}, // Inst #748 = RET_ReallyLR + {4, OperandInfo47}, // Inst #749 = SDIV_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #750 = SDIV_ZPZZ_UNDEF_S + {1, OperandInfo3}, // Inst #751 = SEH_AddFP + {0, NULL}, // Inst #752 = SEH_EpilogEnd + {0, NULL}, // Inst #753 = SEH_EpilogStart + {0, NULL}, // Inst #754 = SEH_Nop + {0, NULL}, // Inst #755 = SEH_PrologEnd + {1, OperandInfo3}, // Inst #756 = SEH_SaveFPLR + {1, OperandInfo3}, // Inst #757 = SEH_SaveFPLR_X + {2, OperandInfo10}, // Inst #758 = SEH_SaveFReg + {3, OperandInfo79}, // Inst #759 = SEH_SaveFRegP + {3, OperandInfo79}, // Inst #760 = SEH_SaveFRegP_X + {2, OperandInfo10}, // Inst #761 = SEH_SaveFReg_X + {2, OperandInfo10}, // Inst #762 = SEH_SaveReg + {3, OperandInfo79}, // Inst #763 = SEH_SaveRegP + {3, OperandInfo79}, // Inst #764 = SEH_SaveRegP_X + {2, OperandInfo10}, // Inst #765 = SEH_SaveReg_X + {0, NULL}, // Inst #766 = SEH_SetFP + {1, OperandInfo3}, // Inst #767 = SEH_StackAlloc + {4, OperandInfo47}, // Inst #768 = SMAX_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #769 = SMAX_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #770 = SMAX_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #771 = SMAX_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #772 = SMIN_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #773 = SMIN_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #774 = SMIN_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #775 = SMIN_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #776 = SMULH_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #777 = SMULH_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #778 = SMULH_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #779 = SMULH_ZPZZ_UNDEF_S + {3, OperandInfo80}, // Inst #780 = SPACE + {4, OperandInfo44}, // Inst #781 = SQABS_ZPmZ_UNDEF_B + {4, OperandInfo44}, // Inst #782 = SQABS_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #783 = SQABS_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #784 = SQABS_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #785 = SQNEG_ZPmZ_UNDEF_B + {4, OperandInfo44}, // Inst #786 = SQNEG_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #787 = SQNEG_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #788 = SQNEG_ZPmZ_UNDEF_S + {4, OperandInfo47}, // Inst #789 = SQRSHL_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #790 = SQRSHL_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #791 = SQRSHL_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #792 = SQRSHL_ZPZZ_UNDEF_S + {4, OperandInfo50}, // Inst #793 = SQSHLU_ZPZI_ZERO_B + {4, OperandInfo50}, // Inst #794 = SQSHLU_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #795 = SQSHLU_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #796 = SQSHLU_ZPZI_ZERO_S + {4, OperandInfo50}, // Inst #797 = SQSHL_ZPZI_ZERO_B + {4, OperandInfo50}, // Inst #798 = SQSHL_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #799 = SQSHL_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #800 = SQSHL_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #801 = SQSHL_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #802 = SQSHL_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #803 = SQSHL_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #804 = SQSHL_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #805 = SRSHL_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #806 = SRSHL_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #807 = SRSHL_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #808 = SRSHL_ZPZZ_UNDEF_S + {4, OperandInfo50}, // Inst #809 = SRSHR_ZPZI_ZERO_B + {4, OperandInfo50}, // Inst #810 = SRSHR_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #811 = SRSHR_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #812 = SRSHR_ZPZI_ZERO_S + {4, OperandInfo81}, // Inst #813 = STGloop + {4, OperandInfo82}, // Inst #814 = STGloop_wback + {3, OperandInfo69}, // Inst #815 = STR_ZZXI + {3, OperandInfo70}, // Inst #816 = STR_ZZZXI + {3, OperandInfo71}, // Inst #817 = STR_ZZZZXI + {4, OperandInfo81}, // Inst #818 = STZGloop + {4, OperandInfo82}, // Inst #819 = STZGloop_wback + {4, OperandInfo47}, // Inst #820 = SUBR_ZPZZ_ZERO_B + {4, OperandInfo47}, // Inst #821 = SUBR_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #822 = SUBR_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #823 = SUBR_ZPZZ_ZERO_S + {3, OperandInfo45}, // Inst #824 = SUBSWrr + {3, OperandInfo46}, // Inst #825 = SUBSXrr + {3, OperandInfo45}, // Inst #826 = SUBWrr + {3, OperandInfo46}, // Inst #827 = SUBXrr + {4, OperandInfo47}, // Inst #828 = SUB_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #829 = SUB_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #830 = SUB_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #831 = SUB_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #832 = SUB_ZPZZ_ZERO_B + {4, OperandInfo47}, // Inst #833 = SUB_ZPZZ_ZERO_D + {4, OperandInfo47}, // Inst #834 = SUB_ZPZZ_ZERO_H + {4, OperandInfo47}, // Inst #835 = SUB_ZPZZ_ZERO_S + {4, OperandInfo44}, // Inst #836 = SXTB_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #837 = SXTB_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #838 = SXTB_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #839 = SXTH_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #840 = SXTH_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #841 = SXTW_ZPmZ_UNDEF_D + {0, NULL}, // Inst #842 = SpeculationBarrierISBDSBEndBB + {0, NULL}, // Inst #843 = SpeculationBarrierSBEndBB + {2, OperandInfo83}, // Inst #844 = SpeculationSafeValueW + {2, OperandInfo84}, // Inst #845 = SpeculationSafeValueX + {3, OperandInfo85}, // Inst #846 = StoreSwiftAsyncContext + {5, OperandInfo86}, // Inst #847 = TAGPstack + {2, OperandInfo10}, // Inst #848 = TCRETURNdi + {2, OperandInfo87}, // Inst #849 = TCRETURNri + {2, OperandInfo73}, // Inst #850 = TCRETURNriALL + {2, OperandInfo88}, // Inst #851 = TCRETURNriBTI + {1, OperandInfo3}, // Inst #852 = TLSDESCCALL + {1, OperandInfo3}, // Inst #853 = TLSDESC_CALLSEQ + {4, OperandInfo47}, // Inst #854 = UDIV_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #855 = UDIV_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #856 = UMAX_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #857 = UMAX_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #858 = UMAX_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #859 = UMAX_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #860 = UMIN_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #861 = UMIN_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #862 = UMIN_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #863 = UMIN_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #864 = UMULH_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #865 = UMULH_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #866 = UMULH_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #867 = UMULH_ZPZZ_UNDEF_S + {4, OperandInfo47}, // Inst #868 = UQRSHL_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #869 = UQRSHL_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #870 = UQRSHL_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #871 = UQRSHL_ZPZZ_UNDEF_S + {4, OperandInfo50}, // Inst #872 = UQSHL_ZPZI_ZERO_B + {4, OperandInfo50}, // Inst #873 = UQSHL_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #874 = UQSHL_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #875 = UQSHL_ZPZI_ZERO_S + {4, OperandInfo47}, // Inst #876 = UQSHL_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #877 = UQSHL_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #878 = UQSHL_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #879 = UQSHL_ZPZZ_UNDEF_S + {4, OperandInfo44}, // Inst #880 = URECPE_ZPmZ_UNDEF_S + {4, OperandInfo47}, // Inst #881 = URSHL_ZPZZ_UNDEF_B + {4, OperandInfo47}, // Inst #882 = URSHL_ZPZZ_UNDEF_D + {4, OperandInfo47}, // Inst #883 = URSHL_ZPZZ_UNDEF_H + {4, OperandInfo47}, // Inst #884 = URSHL_ZPZZ_UNDEF_S + {4, OperandInfo50}, // Inst #885 = URSHR_ZPZI_ZERO_B + {4, OperandInfo50}, // Inst #886 = URSHR_ZPZI_ZERO_D + {4, OperandInfo50}, // Inst #887 = URSHR_ZPZI_ZERO_H + {4, OperandInfo50}, // Inst #888 = URSHR_ZPZI_ZERO_S + {4, OperandInfo44}, // Inst #889 = URSQRTE_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #890 = UXTB_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #891 = UXTB_ZPmZ_UNDEF_H + {4, OperandInfo44}, // Inst #892 = UXTB_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #893 = UXTH_ZPmZ_UNDEF_D + {4, OperandInfo44}, // Inst #894 = UXTH_ZPmZ_UNDEF_S + {4, OperandInfo44}, // Inst #895 = UXTW_ZPmZ_UNDEF_D + {4, OperandInfo89}, // Inst #896 = ABS_ZPmZ_B + {4, OperandInfo89}, // Inst #897 = ABS_ZPmZ_D + {4, OperandInfo89}, // Inst #898 = ABS_ZPmZ_H + {4, OperandInfo89}, // Inst #899 = ABS_ZPmZ_S + {2, OperandInfo90}, // Inst #900 = ABSv16i8 + {2, OperandInfo91}, // Inst #901 = ABSv1i64 + {2, OperandInfo91}, // Inst #902 = ABSv2i32 + {2, OperandInfo90}, // Inst #903 = ABSv2i64 + {2, OperandInfo91}, // Inst #904 = ABSv4i16 + {2, OperandInfo90}, // Inst #905 = ABSv4i32 + {2, OperandInfo90}, // Inst #906 = ABSv8i16 + {2, OperandInfo91}, // Inst #907 = ABSv8i8 + {4, OperandInfo92}, // Inst #908 = ADCLB_ZZZ_D + {4, OperandInfo92}, // Inst #909 = ADCLB_ZZZ_S + {4, OperandInfo92}, // Inst #910 = ADCLT_ZZZ_D + {4, OperandInfo92}, // Inst #911 = ADCLT_ZZZ_S + {3, OperandInfo45}, // Inst #912 = ADCSWr + {3, OperandInfo46}, // Inst #913 = ADCSXr + {3, OperandInfo45}, // Inst #914 = ADCWr + {3, OperandInfo46}, // Inst #915 = ADCXr + {4, OperandInfo93}, // Inst #916 = ADDG + {4, OperandInfo94}, // Inst #917 = ADDHA_MPPZ_D + {4, OperandInfo95}, // Inst #918 = ADDHA_MPPZ_S + {3, OperandInfo96}, // Inst #919 = ADDHNB_ZZZ_B + {3, OperandInfo96}, // Inst #920 = ADDHNB_ZZZ_H + {3, OperandInfo96}, // Inst #921 = ADDHNB_ZZZ_S + {4, OperandInfo92}, // Inst #922 = ADDHNT_ZZZ_B + {4, OperandInfo92}, // Inst #923 = ADDHNT_ZZZ_H + {4, OperandInfo92}, // Inst #924 = ADDHNT_ZZZ_S + {3, OperandInfo97}, // Inst #925 = ADDHNv2i64_v2i32 + {4, OperandInfo98}, // Inst #926 = ADDHNv2i64_v4i32 + {3, OperandInfo97}, // Inst #927 = ADDHNv4i32_v4i16 + {4, OperandInfo98}, // Inst #928 = ADDHNv4i32_v8i16 + {4, OperandInfo98}, // Inst #929 = ADDHNv8i16_v16i8 + {3, OperandInfo97}, // Inst #930 = ADDHNv8i16_v8i8 + {3, OperandInfo99}, // Inst #931 = ADDPL_XXI + {4, OperandInfo100}, // Inst #932 = ADDP_ZPmZ_B + {4, OperandInfo100}, // Inst #933 = ADDP_ZPmZ_D + {4, OperandInfo100}, // Inst #934 = ADDP_ZPmZ_H + {4, OperandInfo100}, // Inst #935 = ADDP_ZPmZ_S + {3, OperandInfo101}, // Inst #936 = ADDPv16i8 + {3, OperandInfo102}, // Inst #937 = ADDPv2i32 + {3, OperandInfo101}, // Inst #938 = ADDPv2i64 + {2, OperandInfo103}, // Inst #939 = ADDPv2i64p + {3, OperandInfo102}, // Inst #940 = ADDPv4i16 + {3, OperandInfo101}, // Inst #941 = ADDPv4i32 + {3, OperandInfo101}, // Inst #942 = ADDPv8i16 + {3, OperandInfo102}, // Inst #943 = ADDPv8i8 + {4, OperandInfo104}, // Inst #944 = ADDSWri + {4, OperandInfo105}, // Inst #945 = ADDSWrs + {4, OperandInfo106}, // Inst #946 = ADDSWrx + {4, OperandInfo107}, // Inst #947 = ADDSXri + {4, OperandInfo108}, // Inst #948 = ADDSXrs + {4, OperandInfo109}, // Inst #949 = ADDSXrx + {4, OperandInfo110}, // Inst #950 = ADDSXrx64 + {4, OperandInfo94}, // Inst #951 = ADDVA_MPPZ_D + {4, OperandInfo95}, // Inst #952 = ADDVA_MPPZ_S + {3, OperandInfo99}, // Inst #953 = ADDVL_XXI + {2, OperandInfo111}, // Inst #954 = ADDVv16i8v + {2, OperandInfo112}, // Inst #955 = ADDVv4i16v + {2, OperandInfo113}, // Inst #956 = ADDVv4i32v + {2, OperandInfo114}, // Inst #957 = ADDVv8i16v + {2, OperandInfo115}, // Inst #958 = ADDVv8i8v + {4, OperandInfo116}, // Inst #959 = ADDWri + {4, OperandInfo105}, // Inst #960 = ADDWrs + {4, OperandInfo117}, // Inst #961 = ADDWrx + {4, OperandInfo93}, // Inst #962 = ADDXri + {4, OperandInfo108}, // Inst #963 = ADDXrs + {4, OperandInfo118}, // Inst #964 = ADDXrx + {4, OperandInfo119}, // Inst #965 = ADDXrx64 + {4, OperandInfo120}, // Inst #966 = ADD_ZI_B + {4, OperandInfo120}, // Inst #967 = ADD_ZI_D + {4, OperandInfo120}, // Inst #968 = ADD_ZI_H + {4, OperandInfo120}, // Inst #969 = ADD_ZI_S + {4, OperandInfo100}, // Inst #970 = ADD_ZPmZ_B + {4, OperandInfo100}, // Inst #971 = ADD_ZPmZ_D + {4, OperandInfo100}, // Inst #972 = ADD_ZPmZ_H + {4, OperandInfo100}, // Inst #973 = ADD_ZPmZ_S + {3, OperandInfo96}, // Inst #974 = ADD_ZZZ_B + {3, OperandInfo96}, // Inst #975 = ADD_ZZZ_D + {3, OperandInfo96}, // Inst #976 = ADD_ZZZ_H + {3, OperandInfo96}, // Inst #977 = ADD_ZZZ_S + {3, OperandInfo101}, // Inst #978 = ADDv16i8 + {3, OperandInfo102}, // Inst #979 = ADDv1i64 + {3, OperandInfo102}, // Inst #980 = ADDv2i32 + {3, OperandInfo101}, // Inst #981 = ADDv2i64 + {3, OperandInfo102}, // Inst #982 = ADDv4i16 + {3, OperandInfo101}, // Inst #983 = ADDv4i32 + {3, OperandInfo101}, // Inst #984 = ADDv8i16 + {3, OperandInfo102}, // Inst #985 = ADDv8i8 + {2, OperandInfo121}, // Inst #986 = ADR + {2, OperandInfo122}, // Inst #987 = ADRP + {3, OperandInfo96}, // Inst #988 = ADR_LSL_ZZZ_D_0 + {3, OperandInfo96}, // Inst #989 = ADR_LSL_ZZZ_D_1 + {3, OperandInfo96}, // Inst #990 = ADR_LSL_ZZZ_D_2 + {3, OperandInfo96}, // Inst #991 = ADR_LSL_ZZZ_D_3 + {3, OperandInfo96}, // Inst #992 = ADR_LSL_ZZZ_S_0 + {3, OperandInfo96}, // Inst #993 = ADR_LSL_ZZZ_S_1 + {3, OperandInfo96}, // Inst #994 = ADR_LSL_ZZZ_S_2 + {3, OperandInfo96}, // Inst #995 = ADR_LSL_ZZZ_S_3 + {3, OperandInfo96}, // Inst #996 = ADR_SXTW_ZZZ_D_0 + {3, OperandInfo96}, // Inst #997 = ADR_SXTW_ZZZ_D_1 + {3, OperandInfo96}, // Inst #998 = ADR_SXTW_ZZZ_D_2 + {3, OperandInfo96}, // Inst #999 = ADR_SXTW_ZZZ_D_3 + {3, OperandInfo96}, // Inst #1000 = ADR_UXTW_ZZZ_D_0 + {3, OperandInfo96}, // Inst #1001 = ADR_UXTW_ZZZ_D_1 + {3, OperandInfo96}, // Inst #1002 = ADR_UXTW_ZZZ_D_2 + {3, OperandInfo96}, // Inst #1003 = ADR_UXTW_ZZZ_D_3 + {3, OperandInfo123}, // Inst #1004 = AESD_ZZZ_B + {3, OperandInfo124}, // Inst #1005 = AESDrr + {3, OperandInfo123}, // Inst #1006 = AESE_ZZZ_B + {3, OperandInfo124}, // Inst #1007 = AESErr + {2, OperandInfo125}, // Inst #1008 = AESIMC_ZZ_B + {2, OperandInfo90}, // Inst #1009 = AESIMCrr + {2, OperandInfo125}, // Inst #1010 = AESMC_ZZ_B + {2, OperandInfo90}, // Inst #1011 = AESMCrr + {3, OperandInfo126}, // Inst #1012 = ANDSWri + {4, OperandInfo105}, // Inst #1013 = ANDSWrs + {3, OperandInfo127}, // Inst #1014 = ANDSXri + {4, OperandInfo108}, // Inst #1015 = ANDSXrs + {4, OperandInfo128}, // Inst #1016 = ANDS_PPzPP + {3, OperandInfo129}, // Inst #1017 = ANDV_VPZ_B + {3, OperandInfo129}, // Inst #1018 = ANDV_VPZ_D + {3, OperandInfo129}, // Inst #1019 = ANDV_VPZ_H + {3, OperandInfo129}, // Inst #1020 = ANDV_VPZ_S + {3, OperandInfo130}, // Inst #1021 = ANDWri + {4, OperandInfo105}, // Inst #1022 = ANDWrs + {3, OperandInfo131}, // Inst #1023 = ANDXri + {4, OperandInfo108}, // Inst #1024 = ANDXrs + {4, OperandInfo128}, // Inst #1025 = AND_PPzPP + {3, OperandInfo132}, // Inst #1026 = AND_ZI + {4, OperandInfo100}, // Inst #1027 = AND_ZPmZ_B + {4, OperandInfo100}, // Inst #1028 = AND_ZPmZ_D + {4, OperandInfo100}, // Inst #1029 = AND_ZPmZ_H + {4, OperandInfo100}, // Inst #1030 = AND_ZPmZ_S + {3, OperandInfo96}, // Inst #1031 = AND_ZZZ + {3, OperandInfo101}, // Inst #1032 = ANDv16i8 + {3, OperandInfo102}, // Inst #1033 = ANDv8i8 + {4, OperandInfo133}, // Inst #1034 = ASRD_ZPmI_B + {4, OperandInfo133}, // Inst #1035 = ASRD_ZPmI_D + {4, OperandInfo133}, // Inst #1036 = ASRD_ZPmI_H + {4, OperandInfo133}, // Inst #1037 = ASRD_ZPmI_S + {4, OperandInfo100}, // Inst #1038 = ASRR_ZPmZ_B + {4, OperandInfo100}, // Inst #1039 = ASRR_ZPmZ_D + {4, OperandInfo100}, // Inst #1040 = ASRR_ZPmZ_H + {4, OperandInfo100}, // Inst #1041 = ASRR_ZPmZ_S + {3, OperandInfo45}, // Inst #1042 = ASRVWr + {3, OperandInfo46}, // Inst #1043 = ASRVXr + {4, OperandInfo100}, // Inst #1044 = ASR_WIDE_ZPmZ_B + {4, OperandInfo100}, // Inst #1045 = ASR_WIDE_ZPmZ_H + {4, OperandInfo100}, // Inst #1046 = ASR_WIDE_ZPmZ_S + {3, OperandInfo96}, // Inst #1047 = ASR_WIDE_ZZZ_B + {3, OperandInfo96}, // Inst #1048 = ASR_WIDE_ZZZ_H + {3, OperandInfo96}, // Inst #1049 = ASR_WIDE_ZZZ_S + {4, OperandInfo133}, // Inst #1050 = ASR_ZPmI_B + {4, OperandInfo133}, // Inst #1051 = ASR_ZPmI_D + {4, OperandInfo133}, // Inst #1052 = ASR_ZPmI_H + {4, OperandInfo133}, // Inst #1053 = ASR_ZPmI_S + {4, OperandInfo100}, // Inst #1054 = ASR_ZPmZ_B + {4, OperandInfo100}, // Inst #1055 = ASR_ZPmZ_D + {4, OperandInfo100}, // Inst #1056 = ASR_ZPmZ_H + {4, OperandInfo100}, // Inst #1057 = ASR_ZPmZ_S + {3, OperandInfo134}, // Inst #1058 = ASR_ZZI_B + {3, OperandInfo134}, // Inst #1059 = ASR_ZZI_D + {3, OperandInfo134}, // Inst #1060 = ASR_ZZI_H + {3, OperandInfo134}, // Inst #1061 = ASR_ZZI_S + {3, OperandInfo135}, // Inst #1062 = AUTDA + {3, OperandInfo135}, // Inst #1063 = AUTDB + {2, OperandInfo136}, // Inst #1064 = AUTDZA + {2, OperandInfo136}, // Inst #1065 = AUTDZB + {3, OperandInfo135}, // Inst #1066 = AUTIA + {0, NULL}, // Inst #1067 = AUTIA1716 + {0, NULL}, // Inst #1068 = AUTIASP + {0, NULL}, // Inst #1069 = AUTIAZ + {3, OperandInfo135}, // Inst #1070 = AUTIB + {0, NULL}, // Inst #1071 = AUTIB1716 + {0, NULL}, // Inst #1072 = AUTIBSP + {0, NULL}, // Inst #1073 = AUTIBZ + {2, OperandInfo136}, // Inst #1074 = AUTIZA + {2, OperandInfo136}, // Inst #1075 = AUTIZB + {0, NULL}, // Inst #1076 = AXFLAG + {1, OperandInfo137}, // Inst #1077 = B + {4, OperandInfo52}, // Inst #1078 = BCAX + {4, OperandInfo92}, // Inst #1079 = BCAX_ZZZZ + {3, OperandInfo96}, // Inst #1080 = BDEP_ZZZ_B + {3, OperandInfo96}, // Inst #1081 = BDEP_ZZZ_D + {3, OperandInfo96}, // Inst #1082 = BDEP_ZZZ_H + {3, OperandInfo96}, // Inst #1083 = BDEP_ZZZ_S + {3, OperandInfo96}, // Inst #1084 = BEXT_ZZZ_B + {3, OperandInfo96}, // Inst #1085 = BEXT_ZZZ_D + {3, OperandInfo96}, // Inst #1086 = BEXT_ZZZ_H + {3, OperandInfo96}, // Inst #1087 = BEXT_ZZZ_S + {5, OperandInfo138}, // Inst #1088 = BF16DOTlanev4bf16 + {5, OperandInfo139}, // Inst #1089 = BF16DOTlanev8bf16 + {2, OperandInfo140}, // Inst #1090 = BFCVT + {2, OperandInfo90}, // Inst #1091 = BFCVTN + {3, OperandInfo124}, // Inst #1092 = BFCVTN2 + {4, OperandInfo89}, // Inst #1093 = BFCVTNT_ZPmZ + {4, OperandInfo89}, // Inst #1094 = BFCVT_ZPmZ + {5, OperandInfo141}, // Inst #1095 = BFDOT_ZZI + {4, OperandInfo92}, // Inst #1096 = BFDOT_ZZZ + {4, OperandInfo142}, // Inst #1097 = BFDOTv4bf16 + {4, OperandInfo98}, // Inst #1098 = BFDOTv8bf16 + {4, OperandInfo98}, // Inst #1099 = BFMLALB + {5, OperandInfo143}, // Inst #1100 = BFMLALBIdx + {4, OperandInfo98}, // Inst #1101 = BFMLALT + {5, OperandInfo143}, // Inst #1102 = BFMLALTIdx + {4, OperandInfo98}, // Inst #1103 = BFMMLA + {5, OperandInfo141}, // Inst #1104 = BFMMLA_B_ZZI + {4, OperandInfo92}, // Inst #1105 = BFMMLA_B_ZZZ + {5, OperandInfo141}, // Inst #1106 = BFMMLA_T_ZZI + {4, OperandInfo92}, // Inst #1107 = BFMMLA_T_ZZZ + {4, OperandInfo92}, // Inst #1108 = BFMMLA_ZZZ + {5, OperandInfo144}, // Inst #1109 = BFMWri + {5, OperandInfo145}, // Inst #1110 = BFMXri + {3, OperandInfo96}, // Inst #1111 = BGRP_ZZZ_B + {3, OperandInfo96}, // Inst #1112 = BGRP_ZZZ_D + {3, OperandInfo96}, // Inst #1113 = BGRP_ZZZ_H + {3, OperandInfo96}, // Inst #1114 = BGRP_ZZZ_S + {4, OperandInfo105}, // Inst #1115 = BICSWrs + {4, OperandInfo108}, // Inst #1116 = BICSXrs + {4, OperandInfo128}, // Inst #1117 = BICS_PPzPP + {4, OperandInfo105}, // Inst #1118 = BICWrs + {4, OperandInfo108}, // Inst #1119 = BICXrs + {4, OperandInfo128}, // Inst #1120 = BIC_PPzPP + {4, OperandInfo100}, // Inst #1121 = BIC_ZPmZ_B + {4, OperandInfo100}, // Inst #1122 = BIC_ZPmZ_D + {4, OperandInfo100}, // Inst #1123 = BIC_ZPmZ_H + {4, OperandInfo100}, // Inst #1124 = BIC_ZPmZ_S + {3, OperandInfo96}, // Inst #1125 = BIC_ZZZ + {3, OperandInfo101}, // Inst #1126 = BICv16i8 + {4, OperandInfo146}, // Inst #1127 = BICv2i32 + {4, OperandInfo146}, // Inst #1128 = BICv4i16 + {4, OperandInfo147}, // Inst #1129 = BICv4i32 + {4, OperandInfo147}, // Inst #1130 = BICv8i16 + {3, OperandInfo102}, // Inst #1131 = BICv8i8 + {4, OperandInfo98}, // Inst #1132 = BIFv16i8 + {4, OperandInfo142}, // Inst #1133 = BIFv8i8 + {4, OperandInfo98}, // Inst #1134 = BITv16i8 + {4, OperandInfo142}, // Inst #1135 = BITv8i8 + {1, OperandInfo137}, // Inst #1136 = BL + {1, OperandInfo75}, // Inst #1137 = BLR + {2, OperandInfo148}, // Inst #1138 = BLRAA + {1, OperandInfo75}, // Inst #1139 = BLRAAZ + {2, OperandInfo148}, // Inst #1140 = BLRAB + {1, OperandInfo75}, // Inst #1141 = BLRABZ + {1, OperandInfo75}, // Inst #1142 = BR + {2, OperandInfo148}, // Inst #1143 = BRAA + {1, OperandInfo75}, // Inst #1144 = BRAAZ + {2, OperandInfo148}, // Inst #1145 = BRAB + {1, OperandInfo75}, // Inst #1146 = BRABZ + {0, NULL}, // Inst #1147 = BRB_IALL + {0, NULL}, // Inst #1148 = BRB_INJ + {1, OperandInfo2}, // Inst #1149 = BRK + {3, OperandInfo149}, // Inst #1150 = BRKAS_PPzP + {4, OperandInfo150}, // Inst #1151 = BRKA_PPmP + {3, OperandInfo149}, // Inst #1152 = BRKA_PPzP + {3, OperandInfo149}, // Inst #1153 = BRKBS_PPzP + {4, OperandInfo150}, // Inst #1154 = BRKB_PPmP + {3, OperandInfo149}, // Inst #1155 = BRKB_PPzP + {4, OperandInfo151}, // Inst #1156 = BRKNS_PPzP + {4, OperandInfo151}, // Inst #1157 = BRKN_PPzP + {4, OperandInfo128}, // Inst #1158 = BRKPAS_PPzPP + {4, OperandInfo128}, // Inst #1159 = BRKPA_PPzPP + {4, OperandInfo128}, // Inst #1160 = BRKPBS_PPzPP + {4, OperandInfo128}, // Inst #1161 = BRKPB_PPzPP + {4, OperandInfo92}, // Inst #1162 = BSL1N_ZZZZ + {4, OperandInfo92}, // Inst #1163 = BSL2N_ZZZZ + {4, OperandInfo92}, // Inst #1164 = BSL_ZZZZ + {4, OperandInfo98}, // Inst #1165 = BSLv16i8 + {4, OperandInfo142}, // Inst #1166 = BSLv8i8 + {2, OperandInfo152}, // Inst #1167 = Bcc + {4, OperandInfo153}, // Inst #1168 = CADD_ZZI_B + {4, OperandInfo153}, // Inst #1169 = CADD_ZZI_D + {4, OperandInfo153}, // Inst #1170 = CADD_ZZI_H + {4, OperandInfo153}, // Inst #1171 = CADD_ZZI_S + {4, OperandInfo154}, // Inst #1172 = CASAB + {4, OperandInfo154}, // Inst #1173 = CASAH + {4, OperandInfo154}, // Inst #1174 = CASALB + {4, OperandInfo154}, // Inst #1175 = CASALH + {4, OperandInfo154}, // Inst #1176 = CASALW + {4, OperandInfo155}, // Inst #1177 = CASALX + {4, OperandInfo154}, // Inst #1178 = CASAW + {4, OperandInfo155}, // Inst #1179 = CASAX + {4, OperandInfo154}, // Inst #1180 = CASB + {4, OperandInfo154}, // Inst #1181 = CASH + {4, OperandInfo154}, // Inst #1182 = CASLB + {4, OperandInfo154}, // Inst #1183 = CASLH + {4, OperandInfo154}, // Inst #1184 = CASLW + {4, OperandInfo155}, // Inst #1185 = CASLX + {4, OperandInfo156}, // Inst #1186 = CASPALW + {4, OperandInfo157}, // Inst #1187 = CASPALX + {4, OperandInfo156}, // Inst #1188 = CASPAW + {4, OperandInfo157}, // Inst #1189 = CASPAX + {4, OperandInfo156}, // Inst #1190 = CASPLW + {4, OperandInfo157}, // Inst #1191 = CASPLX + {4, OperandInfo156}, // Inst #1192 = CASPW + {4, OperandInfo157}, // Inst #1193 = CASPX + {4, OperandInfo154}, // Inst #1194 = CASW + {4, OperandInfo155}, // Inst #1195 = CASX + {2, OperandInfo158}, // Inst #1196 = CBNZW + {2, OperandInfo122}, // Inst #1197 = CBNZX + {2, OperandInfo158}, // Inst #1198 = CBZW + {2, OperandInfo122}, // Inst #1199 = CBZX + {4, OperandInfo159}, // Inst #1200 = CCMNWi + {4, OperandInfo160}, // Inst #1201 = CCMNWr + {4, OperandInfo161}, // Inst #1202 = CCMNXi + {4, OperandInfo162}, // Inst #1203 = CCMNXr + {4, OperandInfo159}, // Inst #1204 = CCMPWi + {4, OperandInfo160}, // Inst #1205 = CCMPWr + {4, OperandInfo161}, // Inst #1206 = CCMPXi + {4, OperandInfo162}, // Inst #1207 = CCMPXr + {6, OperandInfo163}, // Inst #1208 = CDOT_ZZZI_D + {6, OperandInfo164}, // Inst #1209 = CDOT_ZZZI_S + {5, OperandInfo165}, // Inst #1210 = CDOT_ZZZ_D + {5, OperandInfo165}, // Inst #1211 = CDOT_ZZZ_S + {0, NULL}, // Inst #1212 = CFINV + {4, OperandInfo166}, // Inst #1213 = CLASTA_RPZ_B + {4, OperandInfo167}, // Inst #1214 = CLASTA_RPZ_D + {4, OperandInfo166}, // Inst #1215 = CLASTA_RPZ_H + {4, OperandInfo166}, // Inst #1216 = CLASTA_RPZ_S + {4, OperandInfo168}, // Inst #1217 = CLASTA_VPZ_B + {4, OperandInfo169}, // Inst #1218 = CLASTA_VPZ_D + {4, OperandInfo170}, // Inst #1219 = CLASTA_VPZ_H + {4, OperandInfo171}, // Inst #1220 = CLASTA_VPZ_S + {4, OperandInfo100}, // Inst #1221 = CLASTA_ZPZ_B + {4, OperandInfo100}, // Inst #1222 = CLASTA_ZPZ_D + {4, OperandInfo100}, // Inst #1223 = CLASTA_ZPZ_H + {4, OperandInfo100}, // Inst #1224 = CLASTA_ZPZ_S + {4, OperandInfo166}, // Inst #1225 = CLASTB_RPZ_B + {4, OperandInfo167}, // Inst #1226 = CLASTB_RPZ_D + {4, OperandInfo166}, // Inst #1227 = CLASTB_RPZ_H + {4, OperandInfo166}, // Inst #1228 = CLASTB_RPZ_S + {4, OperandInfo168}, // Inst #1229 = CLASTB_VPZ_B + {4, OperandInfo169}, // Inst #1230 = CLASTB_VPZ_D + {4, OperandInfo170}, // Inst #1231 = CLASTB_VPZ_H + {4, OperandInfo171}, // Inst #1232 = CLASTB_VPZ_S + {4, OperandInfo100}, // Inst #1233 = CLASTB_ZPZ_B + {4, OperandInfo100}, // Inst #1234 = CLASTB_ZPZ_D + {4, OperandInfo100}, // Inst #1235 = CLASTB_ZPZ_H + {4, OperandInfo100}, // Inst #1236 = CLASTB_ZPZ_S + {1, OperandInfo2}, // Inst #1237 = CLREX + {2, OperandInfo83}, // Inst #1238 = CLSWr + {2, OperandInfo84}, // Inst #1239 = CLSXr + {4, OperandInfo89}, // Inst #1240 = CLS_ZPmZ_B + {4, OperandInfo89}, // Inst #1241 = CLS_ZPmZ_D + {4, OperandInfo89}, // Inst #1242 = CLS_ZPmZ_H + {4, OperandInfo89}, // Inst #1243 = CLS_ZPmZ_S + {2, OperandInfo90}, // Inst #1244 = CLSv16i8 + {2, OperandInfo91}, // Inst #1245 = CLSv2i32 + {2, OperandInfo91}, // Inst #1246 = CLSv4i16 + {2, OperandInfo90}, // Inst #1247 = CLSv4i32 + {2, OperandInfo90}, // Inst #1248 = CLSv8i16 + {2, OperandInfo91}, // Inst #1249 = CLSv8i8 + {2, OperandInfo83}, // Inst #1250 = CLZWr + {2, OperandInfo84}, // Inst #1251 = CLZXr + {4, OperandInfo89}, // Inst #1252 = CLZ_ZPmZ_B + {4, OperandInfo89}, // Inst #1253 = CLZ_ZPmZ_D + {4, OperandInfo89}, // Inst #1254 = CLZ_ZPmZ_H + {4, OperandInfo89}, // Inst #1255 = CLZ_ZPmZ_S + {2, OperandInfo90}, // Inst #1256 = CLZv16i8 + {2, OperandInfo91}, // Inst #1257 = CLZv2i32 + {2, OperandInfo91}, // Inst #1258 = CLZv4i16 + {2, OperandInfo90}, // Inst #1259 = CLZv4i32 + {2, OperandInfo90}, // Inst #1260 = CLZv8i16 + {2, OperandInfo91}, // Inst #1261 = CLZv8i8 + {3, OperandInfo101}, // Inst #1262 = CMEQv16i8 + {2, OperandInfo90}, // Inst #1263 = CMEQv16i8rz + {3, OperandInfo102}, // Inst #1264 = CMEQv1i64 + {2, OperandInfo91}, // Inst #1265 = CMEQv1i64rz + {3, OperandInfo102}, // Inst #1266 = CMEQv2i32 + {2, OperandInfo91}, // Inst #1267 = CMEQv2i32rz + {3, OperandInfo101}, // Inst #1268 = CMEQv2i64 + {2, OperandInfo90}, // Inst #1269 = CMEQv2i64rz + {3, OperandInfo102}, // Inst #1270 = CMEQv4i16 + {2, OperandInfo91}, // Inst #1271 = CMEQv4i16rz + {3, OperandInfo101}, // Inst #1272 = CMEQv4i32 + {2, OperandInfo90}, // Inst #1273 = CMEQv4i32rz + {3, OperandInfo101}, // Inst #1274 = CMEQv8i16 + {2, OperandInfo90}, // Inst #1275 = CMEQv8i16rz + {3, OperandInfo102}, // Inst #1276 = CMEQv8i8 + {2, OperandInfo91}, // Inst #1277 = CMEQv8i8rz + {3, OperandInfo101}, // Inst #1278 = CMGEv16i8 + {2, OperandInfo90}, // Inst #1279 = CMGEv16i8rz + {3, OperandInfo102}, // Inst #1280 = CMGEv1i64 + {2, OperandInfo91}, // Inst #1281 = CMGEv1i64rz + {3, OperandInfo102}, // Inst #1282 = CMGEv2i32 + {2, OperandInfo91}, // Inst #1283 = CMGEv2i32rz + {3, OperandInfo101}, // Inst #1284 = CMGEv2i64 + {2, OperandInfo90}, // Inst #1285 = CMGEv2i64rz + {3, OperandInfo102}, // Inst #1286 = CMGEv4i16 + {2, OperandInfo91}, // Inst #1287 = CMGEv4i16rz + {3, OperandInfo101}, // Inst #1288 = CMGEv4i32 + {2, OperandInfo90}, // Inst #1289 = CMGEv4i32rz + {3, OperandInfo101}, // Inst #1290 = CMGEv8i16 + {2, OperandInfo90}, // Inst #1291 = CMGEv8i16rz + {3, OperandInfo102}, // Inst #1292 = CMGEv8i8 + {2, OperandInfo91}, // Inst #1293 = CMGEv8i8rz + {3, OperandInfo101}, // Inst #1294 = CMGTv16i8 + {2, OperandInfo90}, // Inst #1295 = CMGTv16i8rz + {3, OperandInfo102}, // Inst #1296 = CMGTv1i64 + {2, OperandInfo91}, // Inst #1297 = CMGTv1i64rz + {3, OperandInfo102}, // Inst #1298 = CMGTv2i32 + {2, OperandInfo91}, // Inst #1299 = CMGTv2i32rz + {3, OperandInfo101}, // Inst #1300 = CMGTv2i64 + {2, OperandInfo90}, // Inst #1301 = CMGTv2i64rz + {3, OperandInfo102}, // Inst #1302 = CMGTv4i16 + {2, OperandInfo91}, // Inst #1303 = CMGTv4i16rz + {3, OperandInfo101}, // Inst #1304 = CMGTv4i32 + {2, OperandInfo90}, // Inst #1305 = CMGTv4i32rz + {3, OperandInfo101}, // Inst #1306 = CMGTv8i16 + {2, OperandInfo90}, // Inst #1307 = CMGTv8i16rz + {3, OperandInfo102}, // Inst #1308 = CMGTv8i8 + {2, OperandInfo91}, // Inst #1309 = CMGTv8i8rz + {3, OperandInfo101}, // Inst #1310 = CMHIv16i8 + {3, OperandInfo102}, // Inst #1311 = CMHIv1i64 + {3, OperandInfo102}, // Inst #1312 = CMHIv2i32 + {3, OperandInfo101}, // Inst #1313 = CMHIv2i64 + {3, OperandInfo102}, // Inst #1314 = CMHIv4i16 + {3, OperandInfo101}, // Inst #1315 = CMHIv4i32 + {3, OperandInfo101}, // Inst #1316 = CMHIv8i16 + {3, OperandInfo102}, // Inst #1317 = CMHIv8i8 + {3, OperandInfo101}, // Inst #1318 = CMHSv16i8 + {3, OperandInfo102}, // Inst #1319 = CMHSv1i64 + {3, OperandInfo102}, // Inst #1320 = CMHSv2i32 + {3, OperandInfo101}, // Inst #1321 = CMHSv2i64 + {3, OperandInfo102}, // Inst #1322 = CMHSv4i16 + {3, OperandInfo101}, // Inst #1323 = CMHSv4i32 + {3, OperandInfo101}, // Inst #1324 = CMHSv8i16 + {3, OperandInfo102}, // Inst #1325 = CMHSv8i8 + {6, OperandInfo164}, // Inst #1326 = CMLA_ZZZI_H + {6, OperandInfo163}, // Inst #1327 = CMLA_ZZZI_S + {5, OperandInfo165}, // Inst #1328 = CMLA_ZZZ_B + {5, OperandInfo165}, // Inst #1329 = CMLA_ZZZ_D + {5, OperandInfo165}, // Inst #1330 = CMLA_ZZZ_H + {5, OperandInfo165}, // Inst #1331 = CMLA_ZZZ_S + {2, OperandInfo90}, // Inst #1332 = CMLEv16i8rz + {2, OperandInfo91}, // Inst #1333 = CMLEv1i64rz + {2, OperandInfo91}, // Inst #1334 = CMLEv2i32rz + {2, OperandInfo90}, // Inst #1335 = CMLEv2i64rz + {2, OperandInfo91}, // Inst #1336 = CMLEv4i16rz + {2, OperandInfo90}, // Inst #1337 = CMLEv4i32rz + {2, OperandInfo90}, // Inst #1338 = CMLEv8i16rz + {2, OperandInfo91}, // Inst #1339 = CMLEv8i8rz + {2, OperandInfo90}, // Inst #1340 = CMLTv16i8rz + {2, OperandInfo91}, // Inst #1341 = CMLTv1i64rz + {2, OperandInfo91}, // Inst #1342 = CMLTv2i32rz + {2, OperandInfo90}, // Inst #1343 = CMLTv2i64rz + {2, OperandInfo91}, // Inst #1344 = CMLTv4i16rz + {2, OperandInfo90}, // Inst #1345 = CMLTv4i32rz + {2, OperandInfo90}, // Inst #1346 = CMLTv8i16rz + {2, OperandInfo91}, // Inst #1347 = CMLTv8i8rz + {4, OperandInfo172}, // Inst #1348 = CMPEQ_PPzZI_B + {4, OperandInfo172}, // Inst #1349 = CMPEQ_PPzZI_D + {4, OperandInfo172}, // Inst #1350 = CMPEQ_PPzZI_H + {4, OperandInfo172}, // Inst #1351 = CMPEQ_PPzZI_S + {4, OperandInfo173}, // Inst #1352 = CMPEQ_PPzZZ_B + {4, OperandInfo173}, // Inst #1353 = CMPEQ_PPzZZ_D + {4, OperandInfo173}, // Inst #1354 = CMPEQ_PPzZZ_H + {4, OperandInfo173}, // Inst #1355 = CMPEQ_PPzZZ_S + {4, OperandInfo173}, // Inst #1356 = CMPEQ_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1357 = CMPEQ_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1358 = CMPEQ_WIDE_PPzZZ_S + {4, OperandInfo172}, // Inst #1359 = CMPGE_PPzZI_B + {4, OperandInfo172}, // Inst #1360 = CMPGE_PPzZI_D + {4, OperandInfo172}, // Inst #1361 = CMPGE_PPzZI_H + {4, OperandInfo172}, // Inst #1362 = CMPGE_PPzZI_S + {4, OperandInfo173}, // Inst #1363 = CMPGE_PPzZZ_B + {4, OperandInfo173}, // Inst #1364 = CMPGE_PPzZZ_D + {4, OperandInfo173}, // Inst #1365 = CMPGE_PPzZZ_H + {4, OperandInfo173}, // Inst #1366 = CMPGE_PPzZZ_S + {4, OperandInfo173}, // Inst #1367 = CMPGE_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1368 = CMPGE_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1369 = CMPGE_WIDE_PPzZZ_S + {4, OperandInfo172}, // Inst #1370 = CMPGT_PPzZI_B + {4, OperandInfo172}, // Inst #1371 = CMPGT_PPzZI_D + {4, OperandInfo172}, // Inst #1372 = CMPGT_PPzZI_H + {4, OperandInfo172}, // Inst #1373 = CMPGT_PPzZI_S + {4, OperandInfo173}, // Inst #1374 = CMPGT_PPzZZ_B + {4, OperandInfo173}, // Inst #1375 = CMPGT_PPzZZ_D + {4, OperandInfo173}, // Inst #1376 = CMPGT_PPzZZ_H + {4, OperandInfo173}, // Inst #1377 = CMPGT_PPzZZ_S + {4, OperandInfo173}, // Inst #1378 = CMPGT_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1379 = CMPGT_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1380 = CMPGT_WIDE_PPzZZ_S + {4, OperandInfo172}, // Inst #1381 = CMPHI_PPzZI_B + {4, OperandInfo172}, // Inst #1382 = CMPHI_PPzZI_D + {4, OperandInfo172}, // Inst #1383 = CMPHI_PPzZI_H + {4, OperandInfo172}, // Inst #1384 = CMPHI_PPzZI_S + {4, OperandInfo173}, // Inst #1385 = CMPHI_PPzZZ_B + {4, OperandInfo173}, // Inst #1386 = CMPHI_PPzZZ_D + {4, OperandInfo173}, // Inst #1387 = CMPHI_PPzZZ_H + {4, OperandInfo173}, // Inst #1388 = CMPHI_PPzZZ_S + {4, OperandInfo173}, // Inst #1389 = CMPHI_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1390 = CMPHI_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1391 = CMPHI_WIDE_PPzZZ_S + {4, OperandInfo172}, // Inst #1392 = CMPHS_PPzZI_B + {4, OperandInfo172}, // Inst #1393 = CMPHS_PPzZI_D + {4, OperandInfo172}, // Inst #1394 = CMPHS_PPzZI_H + {4, OperandInfo172}, // Inst #1395 = CMPHS_PPzZI_S + {4, OperandInfo173}, // Inst #1396 = CMPHS_PPzZZ_B + {4, OperandInfo173}, // Inst #1397 = CMPHS_PPzZZ_D + {4, OperandInfo173}, // Inst #1398 = CMPHS_PPzZZ_H + {4, OperandInfo173}, // Inst #1399 = CMPHS_PPzZZ_S + {4, OperandInfo173}, // Inst #1400 = CMPHS_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1401 = CMPHS_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1402 = CMPHS_WIDE_PPzZZ_S + {4, OperandInfo172}, // Inst #1403 = CMPLE_PPzZI_B + {4, OperandInfo172}, // Inst #1404 = CMPLE_PPzZI_D + {4, OperandInfo172}, // Inst #1405 = CMPLE_PPzZI_H + {4, OperandInfo172}, // Inst #1406 = CMPLE_PPzZI_S + {4, OperandInfo173}, // Inst #1407 = CMPLE_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1408 = CMPLE_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1409 = CMPLE_WIDE_PPzZZ_S + {4, OperandInfo172}, // Inst #1410 = CMPLO_PPzZI_B + {4, OperandInfo172}, // Inst #1411 = CMPLO_PPzZI_D + {4, OperandInfo172}, // Inst #1412 = CMPLO_PPzZI_H + {4, OperandInfo172}, // Inst #1413 = CMPLO_PPzZI_S + {4, OperandInfo173}, // Inst #1414 = CMPLO_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1415 = CMPLO_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1416 = CMPLO_WIDE_PPzZZ_S + {4, OperandInfo172}, // Inst #1417 = CMPLS_PPzZI_B + {4, OperandInfo172}, // Inst #1418 = CMPLS_PPzZI_D + {4, OperandInfo172}, // Inst #1419 = CMPLS_PPzZI_H + {4, OperandInfo172}, // Inst #1420 = CMPLS_PPzZI_S + {4, OperandInfo173}, // Inst #1421 = CMPLS_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1422 = CMPLS_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1423 = CMPLS_WIDE_PPzZZ_S + {4, OperandInfo172}, // Inst #1424 = CMPLT_PPzZI_B + {4, OperandInfo172}, // Inst #1425 = CMPLT_PPzZI_D + {4, OperandInfo172}, // Inst #1426 = CMPLT_PPzZI_H + {4, OperandInfo172}, // Inst #1427 = CMPLT_PPzZI_S + {4, OperandInfo173}, // Inst #1428 = CMPLT_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1429 = CMPLT_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1430 = CMPLT_WIDE_PPzZZ_S + {4, OperandInfo172}, // Inst #1431 = CMPNE_PPzZI_B + {4, OperandInfo172}, // Inst #1432 = CMPNE_PPzZI_D + {4, OperandInfo172}, // Inst #1433 = CMPNE_PPzZI_H + {4, OperandInfo172}, // Inst #1434 = CMPNE_PPzZI_S + {4, OperandInfo173}, // Inst #1435 = CMPNE_PPzZZ_B + {4, OperandInfo173}, // Inst #1436 = CMPNE_PPzZZ_D + {4, OperandInfo173}, // Inst #1437 = CMPNE_PPzZZ_H + {4, OperandInfo173}, // Inst #1438 = CMPNE_PPzZZ_S + {4, OperandInfo173}, // Inst #1439 = CMPNE_WIDE_PPzZZ_B + {4, OperandInfo173}, // Inst #1440 = CMPNE_WIDE_PPzZZ_H + {4, OperandInfo173}, // Inst #1441 = CMPNE_WIDE_PPzZZ_S + {3, OperandInfo101}, // Inst #1442 = CMTSTv16i8 + {3, OperandInfo102}, // Inst #1443 = CMTSTv1i64 + {3, OperandInfo102}, // Inst #1444 = CMTSTv2i32 + {3, OperandInfo101}, // Inst #1445 = CMTSTv2i64 + {3, OperandInfo102}, // Inst #1446 = CMTSTv4i16 + {3, OperandInfo101}, // Inst #1447 = CMTSTv4i32 + {3, OperandInfo101}, // Inst #1448 = CMTSTv8i16 + {3, OperandInfo102}, // Inst #1449 = CMTSTv8i8 + {4, OperandInfo89}, // Inst #1450 = CNOT_ZPmZ_B + {4, OperandInfo89}, // Inst #1451 = CNOT_ZPmZ_D + {4, OperandInfo89}, // Inst #1452 = CNOT_ZPmZ_H + {4, OperandInfo89}, // Inst #1453 = CNOT_ZPmZ_S + {3, OperandInfo174}, // Inst #1454 = CNTB_XPiI + {3, OperandInfo174}, // Inst #1455 = CNTD_XPiI + {3, OperandInfo174}, // Inst #1456 = CNTH_XPiI + {3, OperandInfo175}, // Inst #1457 = CNTP_XPP_B + {3, OperandInfo175}, // Inst #1458 = CNTP_XPP_D + {3, OperandInfo175}, // Inst #1459 = CNTP_XPP_H + {3, OperandInfo175}, // Inst #1460 = CNTP_XPP_S + {3, OperandInfo174}, // Inst #1461 = CNTW_XPiI + {4, OperandInfo89}, // Inst #1462 = CNT_ZPmZ_B + {4, OperandInfo89}, // Inst #1463 = CNT_ZPmZ_D + {4, OperandInfo89}, // Inst #1464 = CNT_ZPmZ_H + {4, OperandInfo89}, // Inst #1465 = CNT_ZPmZ_S + {2, OperandInfo90}, // Inst #1466 = CNTv16i8 + {2, OperandInfo91}, // Inst #1467 = CNTv8i8 + {3, OperandInfo129}, // Inst #1468 = COMPACT_ZPZ_D + {3, OperandInfo129}, // Inst #1469 = COMPACT_ZPZ_S + {5, OperandInfo176}, // Inst #1470 = CPY_ZPmI_B + {5, OperandInfo176}, // Inst #1471 = CPY_ZPmI_D + {5, OperandInfo176}, // Inst #1472 = CPY_ZPmI_H + {5, OperandInfo176}, // Inst #1473 = CPY_ZPmI_S + {4, OperandInfo177}, // Inst #1474 = CPY_ZPmR_B + {4, OperandInfo178}, // Inst #1475 = CPY_ZPmR_D + {4, OperandInfo177}, // Inst #1476 = CPY_ZPmR_H + {4, OperandInfo177}, // Inst #1477 = CPY_ZPmR_S + {4, OperandInfo179}, // Inst #1478 = CPY_ZPmV_B + {4, OperandInfo180}, // Inst #1479 = CPY_ZPmV_D + {4, OperandInfo181}, // Inst #1480 = CPY_ZPmV_H + {4, OperandInfo182}, // Inst #1481 = CPY_ZPmV_S + {4, OperandInfo183}, // Inst #1482 = CPY_ZPzI_B + {4, OperandInfo183}, // Inst #1483 = CPY_ZPzI_D + {4, OperandInfo183}, // Inst #1484 = CPY_ZPzI_H + {4, OperandInfo183}, // Inst #1485 = CPY_ZPzI_S + {3, OperandInfo184}, // Inst #1486 = CPYi16 + {3, OperandInfo185}, // Inst #1487 = CPYi32 + {3, OperandInfo186}, // Inst #1488 = CPYi64 + {3, OperandInfo187}, // Inst #1489 = CPYi8 + {3, OperandInfo45}, // Inst #1490 = CRC32Brr + {3, OperandInfo45}, // Inst #1491 = CRC32CBrr + {3, OperandInfo45}, // Inst #1492 = CRC32CHrr + {3, OperandInfo45}, // Inst #1493 = CRC32CWrr + {3, OperandInfo188}, // Inst #1494 = CRC32CXrr + {3, OperandInfo45}, // Inst #1495 = CRC32Hrr + {3, OperandInfo45}, // Inst #1496 = CRC32Wrr + {3, OperandInfo188}, // Inst #1497 = CRC32Xrr + {4, OperandInfo189}, // Inst #1498 = CSELWr + {4, OperandInfo190}, // Inst #1499 = CSELXr + {4, OperandInfo189}, // Inst #1500 = CSINCWr + {4, OperandInfo190}, // Inst #1501 = CSINCXr + {4, OperandInfo189}, // Inst #1502 = CSINVWr + {4, OperandInfo190}, // Inst #1503 = CSINVXr + {4, OperandInfo189}, // Inst #1504 = CSNEGWr + {4, OperandInfo190}, // Inst #1505 = CSNEGXr + {2, OperandInfo83}, // Inst #1506 = CTERMEQ_WW + {2, OperandInfo84}, // Inst #1507 = CTERMEQ_XX + {2, OperandInfo83}, // Inst #1508 = CTERMNE_WW + {2, OperandInfo84}, // Inst #1509 = CTERMNE_XX + {1, OperandInfo2}, // Inst #1510 = DCPS1 + {1, OperandInfo2}, // Inst #1511 = DCPS2 + {1, OperandInfo2}, // Inst #1512 = DCPS3 + {4, OperandInfo191}, // Inst #1513 = DECB_XPiI + {4, OperandInfo191}, // Inst #1514 = DECD_XPiI + {4, OperandInfo120}, // Inst #1515 = DECD_ZPiI + {4, OperandInfo191}, // Inst #1516 = DECH_XPiI + {4, OperandInfo120}, // Inst #1517 = DECH_ZPiI + {3, OperandInfo192}, // Inst #1518 = DECP_XP_B + {3, OperandInfo192}, // Inst #1519 = DECP_XP_D + {3, OperandInfo192}, // Inst #1520 = DECP_XP_H + {3, OperandInfo192}, // Inst #1521 = DECP_XP_S + {3, OperandInfo193}, // Inst #1522 = DECP_ZP_D + {3, OperandInfo193}, // Inst #1523 = DECP_ZP_H + {3, OperandInfo193}, // Inst #1524 = DECP_ZP_S + {4, OperandInfo191}, // Inst #1525 = DECW_XPiI + {4, OperandInfo120}, // Inst #1526 = DECW_ZPiI + {1, OperandInfo2}, // Inst #1527 = DMB + {0, NULL}, // Inst #1528 = DRPS + {1, OperandInfo2}, // Inst #1529 = DSB + {1, OperandInfo2}, // Inst #1530 = DSBnXS + {2, OperandInfo194}, // Inst #1531 = DUPM_ZI + {3, OperandInfo195}, // Inst #1532 = DUP_ZI_B + {3, OperandInfo195}, // Inst #1533 = DUP_ZI_D + {3, OperandInfo195}, // Inst #1534 = DUP_ZI_H + {3, OperandInfo195}, // Inst #1535 = DUP_ZI_S + {2, OperandInfo196}, // Inst #1536 = DUP_ZR_B + {2, OperandInfo197}, // Inst #1537 = DUP_ZR_D + {2, OperandInfo196}, // Inst #1538 = DUP_ZR_H + {2, OperandInfo196}, // Inst #1539 = DUP_ZR_S + {3, OperandInfo134}, // Inst #1540 = DUP_ZZI_B + {3, OperandInfo134}, // Inst #1541 = DUP_ZZI_D + {3, OperandInfo134}, // Inst #1542 = DUP_ZZI_H + {3, OperandInfo134}, // Inst #1543 = DUP_ZZI_Q + {3, OperandInfo134}, // Inst #1544 = DUP_ZZI_S + {2, OperandInfo198}, // Inst #1545 = DUPv16i8gpr + {3, OperandInfo199}, // Inst #1546 = DUPv16i8lane + {2, OperandInfo200}, // Inst #1547 = DUPv2i32gpr + {3, OperandInfo186}, // Inst #1548 = DUPv2i32lane + {2, OperandInfo201}, // Inst #1549 = DUPv2i64gpr + {3, OperandInfo199}, // Inst #1550 = DUPv2i64lane + {2, OperandInfo200}, // Inst #1551 = DUPv4i16gpr + {3, OperandInfo186}, // Inst #1552 = DUPv4i16lane + {2, OperandInfo198}, // Inst #1553 = DUPv4i32gpr + {3, OperandInfo199}, // Inst #1554 = DUPv4i32lane + {2, OperandInfo198}, // Inst #1555 = DUPv8i16gpr + {3, OperandInfo199}, // Inst #1556 = DUPv8i16lane + {2, OperandInfo200}, // Inst #1557 = DUPv8i8gpr + {3, OperandInfo186}, // Inst #1558 = DUPv8i8lane + {4, OperandInfo105}, // Inst #1559 = EONWrs + {4, OperandInfo108}, // Inst #1560 = EONXrs + {4, OperandInfo52}, // Inst #1561 = EOR3 + {4, OperandInfo92}, // Inst #1562 = EOR3_ZZZZ + {4, OperandInfo92}, // Inst #1563 = EORBT_ZZZ_B + {4, OperandInfo92}, // Inst #1564 = EORBT_ZZZ_D + {4, OperandInfo92}, // Inst #1565 = EORBT_ZZZ_H + {4, OperandInfo92}, // Inst #1566 = EORBT_ZZZ_S + {4, OperandInfo128}, // Inst #1567 = EORS_PPzPP + {4, OperandInfo92}, // Inst #1568 = EORTB_ZZZ_B + {4, OperandInfo92}, // Inst #1569 = EORTB_ZZZ_D + {4, OperandInfo92}, // Inst #1570 = EORTB_ZZZ_H + {4, OperandInfo92}, // Inst #1571 = EORTB_ZZZ_S + {3, OperandInfo129}, // Inst #1572 = EORV_VPZ_B + {3, OperandInfo129}, // Inst #1573 = EORV_VPZ_D + {3, OperandInfo129}, // Inst #1574 = EORV_VPZ_H + {3, OperandInfo129}, // Inst #1575 = EORV_VPZ_S + {3, OperandInfo130}, // Inst #1576 = EORWri + {4, OperandInfo105}, // Inst #1577 = EORWrs + {3, OperandInfo131}, // Inst #1578 = EORXri + {4, OperandInfo108}, // Inst #1579 = EORXrs + {4, OperandInfo128}, // Inst #1580 = EOR_PPzPP + {3, OperandInfo132}, // Inst #1581 = EOR_ZI + {4, OperandInfo100}, // Inst #1582 = EOR_ZPmZ_B + {4, OperandInfo100}, // Inst #1583 = EOR_ZPmZ_D + {4, OperandInfo100}, // Inst #1584 = EOR_ZPmZ_H + {4, OperandInfo100}, // Inst #1585 = EOR_ZPmZ_S + {3, OperandInfo96}, // Inst #1586 = EOR_ZZZ + {3, OperandInfo101}, // Inst #1587 = EORv16i8 + {3, OperandInfo102}, // Inst #1588 = EORv8i8 + {0, NULL}, // Inst #1589 = ERET + {0, NULL}, // Inst #1590 = ERETAA + {0, NULL}, // Inst #1591 = ERETAB + {5, OperandInfo202}, // Inst #1592 = EXTRACT_ZPMXI_H_B + {5, OperandInfo203}, // Inst #1593 = EXTRACT_ZPMXI_H_D + {5, OperandInfo204}, // Inst #1594 = EXTRACT_ZPMXI_H_H + {5, OperandInfo205}, // Inst #1595 = EXTRACT_ZPMXI_H_Q + {5, OperandInfo206}, // Inst #1596 = EXTRACT_ZPMXI_H_S + {5, OperandInfo202}, // Inst #1597 = EXTRACT_ZPMXI_V_B + {5, OperandInfo203}, // Inst #1598 = EXTRACT_ZPMXI_V_D + {5, OperandInfo204}, // Inst #1599 = EXTRACT_ZPMXI_V_H + {5, OperandInfo205}, // Inst #1600 = EXTRACT_ZPMXI_V_Q + {5, OperandInfo206}, // Inst #1601 = EXTRACT_ZPMXI_V_S + {4, OperandInfo189}, // Inst #1602 = EXTRWrri + {4, OperandInfo190}, // Inst #1603 = EXTRXrri + {4, OperandInfo153}, // Inst #1604 = EXT_ZZI + {3, OperandInfo207}, // Inst #1605 = EXT_ZZI_B + {4, OperandInfo208}, // Inst #1606 = EXTv16i8 + {4, OperandInfo209}, // Inst #1607 = EXTv8i8 + {3, OperandInfo210}, // Inst #1608 = FABD16 + {3, OperandInfo211}, // Inst #1609 = FABD32 + {3, OperandInfo102}, // Inst #1610 = FABD64 + {4, OperandInfo100}, // Inst #1611 = FABD_ZPmZ_D + {4, OperandInfo100}, // Inst #1612 = FABD_ZPmZ_H + {4, OperandInfo100}, // Inst #1613 = FABD_ZPmZ_S + {3, OperandInfo102}, // Inst #1614 = FABDv2f32 + {3, OperandInfo101}, // Inst #1615 = FABDv2f64 + {3, OperandInfo102}, // Inst #1616 = FABDv4f16 + {3, OperandInfo101}, // Inst #1617 = FABDv4f32 + {3, OperandInfo101}, // Inst #1618 = FABDv8f16 + {2, OperandInfo91}, // Inst #1619 = FABSDr + {2, OperandInfo212}, // Inst #1620 = FABSHr + {2, OperandInfo213}, // Inst #1621 = FABSSr + {4, OperandInfo89}, // Inst #1622 = FABS_ZPmZ_D + {4, OperandInfo89}, // Inst #1623 = FABS_ZPmZ_H + {4, OperandInfo89}, // Inst #1624 = FABS_ZPmZ_S + {2, OperandInfo91}, // Inst #1625 = FABSv2f32 + {2, OperandInfo90}, // Inst #1626 = FABSv2f64 + {2, OperandInfo91}, // Inst #1627 = FABSv4f16 + {2, OperandInfo90}, // Inst #1628 = FABSv4f32 + {2, OperandInfo90}, // Inst #1629 = FABSv8f16 + {3, OperandInfo210}, // Inst #1630 = FACGE16 + {3, OperandInfo211}, // Inst #1631 = FACGE32 + {3, OperandInfo102}, // Inst #1632 = FACGE64 + {4, OperandInfo173}, // Inst #1633 = FACGE_PPzZZ_D + {4, OperandInfo173}, // Inst #1634 = FACGE_PPzZZ_H + {4, OperandInfo173}, // Inst #1635 = FACGE_PPzZZ_S + {3, OperandInfo102}, // Inst #1636 = FACGEv2f32 + {3, OperandInfo101}, // Inst #1637 = FACGEv2f64 + {3, OperandInfo102}, // Inst #1638 = FACGEv4f16 + {3, OperandInfo101}, // Inst #1639 = FACGEv4f32 + {3, OperandInfo101}, // Inst #1640 = FACGEv8f16 + {3, OperandInfo210}, // Inst #1641 = FACGT16 + {3, OperandInfo211}, // Inst #1642 = FACGT32 + {3, OperandInfo102}, // Inst #1643 = FACGT64 + {4, OperandInfo173}, // Inst #1644 = FACGT_PPzZZ_D + {4, OperandInfo173}, // Inst #1645 = FACGT_PPzZZ_H + {4, OperandInfo173}, // Inst #1646 = FACGT_PPzZZ_S + {3, OperandInfo102}, // Inst #1647 = FACGTv2f32 + {3, OperandInfo101}, // Inst #1648 = FACGTv2f64 + {3, OperandInfo102}, // Inst #1649 = FACGTv4f16 + {3, OperandInfo101}, // Inst #1650 = FACGTv4f32 + {3, OperandInfo101}, // Inst #1651 = FACGTv8f16 + {4, OperandInfo100}, // Inst #1652 = FADDA_VPZ_D + {4, OperandInfo100}, // Inst #1653 = FADDA_VPZ_H + {4, OperandInfo100}, // Inst #1654 = FADDA_VPZ_S + {3, OperandInfo102}, // Inst #1655 = FADDDrr + {3, OperandInfo210}, // Inst #1656 = FADDHrr + {4, OperandInfo100}, // Inst #1657 = FADDP_ZPmZZ_D + {4, OperandInfo100}, // Inst #1658 = FADDP_ZPmZZ_H + {4, OperandInfo100}, // Inst #1659 = FADDP_ZPmZZ_S + {3, OperandInfo102}, // Inst #1660 = FADDPv2f32 + {3, OperandInfo101}, // Inst #1661 = FADDPv2f64 + {2, OperandInfo112}, // Inst #1662 = FADDPv2i16p + {2, OperandInfo214}, // Inst #1663 = FADDPv2i32p + {2, OperandInfo103}, // Inst #1664 = FADDPv2i64p + {3, OperandInfo102}, // Inst #1665 = FADDPv4f16 + {3, OperandInfo101}, // Inst #1666 = FADDPv4f32 + {3, OperandInfo101}, // Inst #1667 = FADDPv8f16 + {3, OperandInfo211}, // Inst #1668 = FADDSrr + {3, OperandInfo129}, // Inst #1669 = FADDV_VPZ_D + {3, OperandInfo129}, // Inst #1670 = FADDV_VPZ_H + {3, OperandInfo129}, // Inst #1671 = FADDV_VPZ_S + {4, OperandInfo133}, // Inst #1672 = FADD_ZPmI_D + {4, OperandInfo133}, // Inst #1673 = FADD_ZPmI_H + {4, OperandInfo133}, // Inst #1674 = FADD_ZPmI_S + {4, OperandInfo100}, // Inst #1675 = FADD_ZPmZ_D + {4, OperandInfo100}, // Inst #1676 = FADD_ZPmZ_H + {4, OperandInfo100}, // Inst #1677 = FADD_ZPmZ_S + {3, OperandInfo96}, // Inst #1678 = FADD_ZZZ_D + {3, OperandInfo96}, // Inst #1679 = FADD_ZZZ_H + {3, OperandInfo96}, // Inst #1680 = FADD_ZZZ_S + {3, OperandInfo102}, // Inst #1681 = FADDv2f32 + {3, OperandInfo101}, // Inst #1682 = FADDv2f64 + {3, OperandInfo102}, // Inst #1683 = FADDv4f16 + {3, OperandInfo101}, // Inst #1684 = FADDv4f32 + {3, OperandInfo101}, // Inst #1685 = FADDv8f16 + {5, OperandInfo215}, // Inst #1686 = FCADD_ZPmZ_D + {5, OperandInfo215}, // Inst #1687 = FCADD_ZPmZ_H + {5, OperandInfo215}, // Inst #1688 = FCADD_ZPmZ_S + {4, OperandInfo216}, // Inst #1689 = FCADDv2f32 + {4, OperandInfo58}, // Inst #1690 = FCADDv2f64 + {4, OperandInfo216}, // Inst #1691 = FCADDv4f16 + {4, OperandInfo58}, // Inst #1692 = FCADDv4f32 + {4, OperandInfo58}, // Inst #1693 = FCADDv8f16 + {4, OperandInfo217}, // Inst #1694 = FCCMPDrr + {4, OperandInfo217}, // Inst #1695 = FCCMPEDrr + {4, OperandInfo218}, // Inst #1696 = FCCMPEHrr + {4, OperandInfo219}, // Inst #1697 = FCCMPESrr + {4, OperandInfo218}, // Inst #1698 = FCCMPHrr + {4, OperandInfo219}, // Inst #1699 = FCCMPSrr + {3, OperandInfo210}, // Inst #1700 = FCMEQ16 + {3, OperandInfo211}, // Inst #1701 = FCMEQ32 + {3, OperandInfo102}, // Inst #1702 = FCMEQ64 + {3, OperandInfo220}, // Inst #1703 = FCMEQ_PPzZ0_D + {3, OperandInfo220}, // Inst #1704 = FCMEQ_PPzZ0_H + {3, OperandInfo220}, // Inst #1705 = FCMEQ_PPzZ0_S + {4, OperandInfo173}, // Inst #1706 = FCMEQ_PPzZZ_D + {4, OperandInfo173}, // Inst #1707 = FCMEQ_PPzZZ_H + {4, OperandInfo173}, // Inst #1708 = FCMEQ_PPzZZ_S + {2, OperandInfo212}, // Inst #1709 = FCMEQv1i16rz + {2, OperandInfo213}, // Inst #1710 = FCMEQv1i32rz + {2, OperandInfo91}, // Inst #1711 = FCMEQv1i64rz + {3, OperandInfo102}, // Inst #1712 = FCMEQv2f32 + {3, OperandInfo101}, // Inst #1713 = FCMEQv2f64 + {2, OperandInfo91}, // Inst #1714 = FCMEQv2i32rz + {2, OperandInfo90}, // Inst #1715 = FCMEQv2i64rz + {3, OperandInfo102}, // Inst #1716 = FCMEQv4f16 + {3, OperandInfo101}, // Inst #1717 = FCMEQv4f32 + {2, OperandInfo91}, // Inst #1718 = FCMEQv4i16rz + {2, OperandInfo90}, // Inst #1719 = FCMEQv4i32rz + {3, OperandInfo101}, // Inst #1720 = FCMEQv8f16 + {2, OperandInfo90}, // Inst #1721 = FCMEQv8i16rz + {3, OperandInfo210}, // Inst #1722 = FCMGE16 + {3, OperandInfo211}, // Inst #1723 = FCMGE32 + {3, OperandInfo102}, // Inst #1724 = FCMGE64 + {3, OperandInfo220}, // Inst #1725 = FCMGE_PPzZ0_D + {3, OperandInfo220}, // Inst #1726 = FCMGE_PPzZ0_H + {3, OperandInfo220}, // Inst #1727 = FCMGE_PPzZ0_S + {4, OperandInfo173}, // Inst #1728 = FCMGE_PPzZZ_D + {4, OperandInfo173}, // Inst #1729 = FCMGE_PPzZZ_H + {4, OperandInfo173}, // Inst #1730 = FCMGE_PPzZZ_S + {2, OperandInfo212}, // Inst #1731 = FCMGEv1i16rz + {2, OperandInfo213}, // Inst #1732 = FCMGEv1i32rz + {2, OperandInfo91}, // Inst #1733 = FCMGEv1i64rz + {3, OperandInfo102}, // Inst #1734 = FCMGEv2f32 + {3, OperandInfo101}, // Inst #1735 = FCMGEv2f64 + {2, OperandInfo91}, // Inst #1736 = FCMGEv2i32rz + {2, OperandInfo90}, // Inst #1737 = FCMGEv2i64rz + {3, OperandInfo102}, // Inst #1738 = FCMGEv4f16 + {3, OperandInfo101}, // Inst #1739 = FCMGEv4f32 + {2, OperandInfo91}, // Inst #1740 = FCMGEv4i16rz + {2, OperandInfo90}, // Inst #1741 = FCMGEv4i32rz + {3, OperandInfo101}, // Inst #1742 = FCMGEv8f16 + {2, OperandInfo90}, // Inst #1743 = FCMGEv8i16rz + {3, OperandInfo210}, // Inst #1744 = FCMGT16 + {3, OperandInfo211}, // Inst #1745 = FCMGT32 + {3, OperandInfo102}, // Inst #1746 = FCMGT64 + {3, OperandInfo220}, // Inst #1747 = FCMGT_PPzZ0_D + {3, OperandInfo220}, // Inst #1748 = FCMGT_PPzZ0_H + {3, OperandInfo220}, // Inst #1749 = FCMGT_PPzZ0_S + {4, OperandInfo173}, // Inst #1750 = FCMGT_PPzZZ_D + {4, OperandInfo173}, // Inst #1751 = FCMGT_PPzZZ_H + {4, OperandInfo173}, // Inst #1752 = FCMGT_PPzZZ_S + {2, OperandInfo212}, // Inst #1753 = FCMGTv1i16rz + {2, OperandInfo213}, // Inst #1754 = FCMGTv1i32rz + {2, OperandInfo91}, // Inst #1755 = FCMGTv1i64rz + {3, OperandInfo102}, // Inst #1756 = FCMGTv2f32 + {3, OperandInfo101}, // Inst #1757 = FCMGTv2f64 + {2, OperandInfo91}, // Inst #1758 = FCMGTv2i32rz + {2, OperandInfo90}, // Inst #1759 = FCMGTv2i64rz + {3, OperandInfo102}, // Inst #1760 = FCMGTv4f16 + {3, OperandInfo101}, // Inst #1761 = FCMGTv4f32 + {2, OperandInfo91}, // Inst #1762 = FCMGTv4i16rz + {2, OperandInfo90}, // Inst #1763 = FCMGTv4i32rz + {3, OperandInfo101}, // Inst #1764 = FCMGTv8f16 + {2, OperandInfo90}, // Inst #1765 = FCMGTv8i16rz + {6, OperandInfo221}, // Inst #1766 = FCMLA_ZPmZZ_D + {6, OperandInfo221}, // Inst #1767 = FCMLA_ZPmZZ_H + {6, OperandInfo221}, // Inst #1768 = FCMLA_ZPmZZ_S + {6, OperandInfo164}, // Inst #1769 = FCMLA_ZZZI_H + {6, OperandInfo163}, // Inst #1770 = FCMLA_ZZZI_S + {5, OperandInfo222}, // Inst #1771 = FCMLAv2f32 + {5, OperandInfo139}, // Inst #1772 = FCMLAv2f64 + {5, OperandInfo222}, // Inst #1773 = FCMLAv4f16 + {6, OperandInfo223}, // Inst #1774 = FCMLAv4f16_indexed + {5, OperandInfo139}, // Inst #1775 = FCMLAv4f32 + {6, OperandInfo224}, // Inst #1776 = FCMLAv4f32_indexed + {5, OperandInfo139}, // Inst #1777 = FCMLAv8f16 + {6, OperandInfo224}, // Inst #1778 = FCMLAv8f16_indexed + {3, OperandInfo220}, // Inst #1779 = FCMLE_PPzZ0_D + {3, OperandInfo220}, // Inst #1780 = FCMLE_PPzZ0_H + {3, OperandInfo220}, // Inst #1781 = FCMLE_PPzZ0_S + {2, OperandInfo212}, // Inst #1782 = FCMLEv1i16rz + {2, OperandInfo213}, // Inst #1783 = FCMLEv1i32rz + {2, OperandInfo91}, // Inst #1784 = FCMLEv1i64rz + {2, OperandInfo91}, // Inst #1785 = FCMLEv2i32rz + {2, OperandInfo90}, // Inst #1786 = FCMLEv2i64rz + {2, OperandInfo91}, // Inst #1787 = FCMLEv4i16rz + {2, OperandInfo90}, // Inst #1788 = FCMLEv4i32rz + {2, OperandInfo90}, // Inst #1789 = FCMLEv8i16rz + {3, OperandInfo220}, // Inst #1790 = FCMLT_PPzZ0_D + {3, OperandInfo220}, // Inst #1791 = FCMLT_PPzZ0_H + {3, OperandInfo220}, // Inst #1792 = FCMLT_PPzZ0_S + {2, OperandInfo212}, // Inst #1793 = FCMLTv1i16rz + {2, OperandInfo213}, // Inst #1794 = FCMLTv1i32rz + {2, OperandInfo91}, // Inst #1795 = FCMLTv1i64rz + {2, OperandInfo91}, // Inst #1796 = FCMLTv2i32rz + {2, OperandInfo90}, // Inst #1797 = FCMLTv2i64rz + {2, OperandInfo91}, // Inst #1798 = FCMLTv4i16rz + {2, OperandInfo90}, // Inst #1799 = FCMLTv4i32rz + {2, OperandInfo90}, // Inst #1800 = FCMLTv8i16rz + {3, OperandInfo220}, // Inst #1801 = FCMNE_PPzZ0_D + {3, OperandInfo220}, // Inst #1802 = FCMNE_PPzZ0_H + {3, OperandInfo220}, // Inst #1803 = FCMNE_PPzZ0_S + {4, OperandInfo173}, // Inst #1804 = FCMNE_PPzZZ_D + {4, OperandInfo173}, // Inst #1805 = FCMNE_PPzZZ_H + {4, OperandInfo173}, // Inst #1806 = FCMNE_PPzZZ_S + {1, OperandInfo60}, // Inst #1807 = FCMPDri + {2, OperandInfo91}, // Inst #1808 = FCMPDrr + {1, OperandInfo60}, // Inst #1809 = FCMPEDri + {2, OperandInfo91}, // Inst #1810 = FCMPEDrr + {1, OperandInfo61}, // Inst #1811 = FCMPEHri + {2, OperandInfo212}, // Inst #1812 = FCMPEHrr + {1, OperandInfo62}, // Inst #1813 = FCMPESri + {2, OperandInfo213}, // Inst #1814 = FCMPESrr + {1, OperandInfo61}, // Inst #1815 = FCMPHri + {2, OperandInfo212}, // Inst #1816 = FCMPHrr + {1, OperandInfo62}, // Inst #1817 = FCMPSri + {2, OperandInfo213}, // Inst #1818 = FCMPSrr + {4, OperandInfo173}, // Inst #1819 = FCMUO_PPzZZ_D + {4, OperandInfo173}, // Inst #1820 = FCMUO_PPzZZ_H + {4, OperandInfo173}, // Inst #1821 = FCMUO_PPzZZ_S + {4, OperandInfo225}, // Inst #1822 = FCPY_ZPmI_D + {4, OperandInfo225}, // Inst #1823 = FCPY_ZPmI_H + {4, OperandInfo225}, // Inst #1824 = FCPY_ZPmI_S + {4, OperandInfo216}, // Inst #1825 = FCSELDrrr + {4, OperandInfo226}, // Inst #1826 = FCSELHrrr + {4, OperandInfo227}, // Inst #1827 = FCSELSrrr + {2, OperandInfo228}, // Inst #1828 = FCVTASUWDr + {2, OperandInfo229}, // Inst #1829 = FCVTASUWHr + {2, OperandInfo230}, // Inst #1830 = FCVTASUWSr + {2, OperandInfo231}, // Inst #1831 = FCVTASUXDr + {2, OperandInfo232}, // Inst #1832 = FCVTASUXHr + {2, OperandInfo233}, // Inst #1833 = FCVTASUXSr + {2, OperandInfo212}, // Inst #1834 = FCVTASv1f16 + {2, OperandInfo213}, // Inst #1835 = FCVTASv1i32 + {2, OperandInfo91}, // Inst #1836 = FCVTASv1i64 + {2, OperandInfo91}, // Inst #1837 = FCVTASv2f32 + {2, OperandInfo90}, // Inst #1838 = FCVTASv2f64 + {2, OperandInfo91}, // Inst #1839 = FCVTASv4f16 + {2, OperandInfo90}, // Inst #1840 = FCVTASv4f32 + {2, OperandInfo90}, // Inst #1841 = FCVTASv8f16 + {2, OperandInfo228}, // Inst #1842 = FCVTAUUWDr + {2, OperandInfo229}, // Inst #1843 = FCVTAUUWHr + {2, OperandInfo230}, // Inst #1844 = FCVTAUUWSr + {2, OperandInfo231}, // Inst #1845 = FCVTAUUXDr + {2, OperandInfo232}, // Inst #1846 = FCVTAUUXHr + {2, OperandInfo233}, // Inst #1847 = FCVTAUUXSr + {2, OperandInfo212}, // Inst #1848 = FCVTAUv1f16 + {2, OperandInfo213}, // Inst #1849 = FCVTAUv1i32 + {2, OperandInfo91}, // Inst #1850 = FCVTAUv1i64 + {2, OperandInfo91}, // Inst #1851 = FCVTAUv2f32 + {2, OperandInfo90}, // Inst #1852 = FCVTAUv2f64 + {2, OperandInfo91}, // Inst #1853 = FCVTAUv4f16 + {2, OperandInfo90}, // Inst #1854 = FCVTAUv4f32 + {2, OperandInfo90}, // Inst #1855 = FCVTAUv8f16 + {2, OperandInfo234}, // Inst #1856 = FCVTDHr + {2, OperandInfo235}, // Inst #1857 = FCVTDSr + {2, OperandInfo112}, // Inst #1858 = FCVTHDr + {2, OperandInfo140}, // Inst #1859 = FCVTHSr + {4, OperandInfo89}, // Inst #1860 = FCVTLT_ZPmZ_HtoS + {4, OperandInfo89}, // Inst #1861 = FCVTLT_ZPmZ_StoD + {2, OperandInfo236}, // Inst #1862 = FCVTLv2i32 + {2, OperandInfo236}, // Inst #1863 = FCVTLv4i16 + {2, OperandInfo90}, // Inst #1864 = FCVTLv4i32 + {2, OperandInfo90}, // Inst #1865 = FCVTLv8i16 + {2, OperandInfo228}, // Inst #1866 = FCVTMSUWDr + {2, OperandInfo229}, // Inst #1867 = FCVTMSUWHr + {2, OperandInfo230}, // Inst #1868 = FCVTMSUWSr + {2, OperandInfo231}, // Inst #1869 = FCVTMSUXDr + {2, OperandInfo232}, // Inst #1870 = FCVTMSUXHr + {2, OperandInfo233}, // Inst #1871 = FCVTMSUXSr + {2, OperandInfo212}, // Inst #1872 = FCVTMSv1f16 + {2, OperandInfo213}, // Inst #1873 = FCVTMSv1i32 + {2, OperandInfo91}, // Inst #1874 = FCVTMSv1i64 + {2, OperandInfo91}, // Inst #1875 = FCVTMSv2f32 + {2, OperandInfo90}, // Inst #1876 = FCVTMSv2f64 + {2, OperandInfo91}, // Inst #1877 = FCVTMSv4f16 + {2, OperandInfo90}, // Inst #1878 = FCVTMSv4f32 + {2, OperandInfo90}, // Inst #1879 = FCVTMSv8f16 + {2, OperandInfo228}, // Inst #1880 = FCVTMUUWDr + {2, OperandInfo229}, // Inst #1881 = FCVTMUUWHr + {2, OperandInfo230}, // Inst #1882 = FCVTMUUWSr + {2, OperandInfo231}, // Inst #1883 = FCVTMUUXDr + {2, OperandInfo232}, // Inst #1884 = FCVTMUUXHr + {2, OperandInfo233}, // Inst #1885 = FCVTMUUXSr + {2, OperandInfo212}, // Inst #1886 = FCVTMUv1f16 + {2, OperandInfo213}, // Inst #1887 = FCVTMUv1i32 + {2, OperandInfo91}, // Inst #1888 = FCVTMUv1i64 + {2, OperandInfo91}, // Inst #1889 = FCVTMUv2f32 + {2, OperandInfo90}, // Inst #1890 = FCVTMUv2f64 + {2, OperandInfo91}, // Inst #1891 = FCVTMUv4f16 + {2, OperandInfo90}, // Inst #1892 = FCVTMUv4f32 + {2, OperandInfo90}, // Inst #1893 = FCVTMUv8f16 + {2, OperandInfo228}, // Inst #1894 = FCVTNSUWDr + {2, OperandInfo229}, // Inst #1895 = FCVTNSUWHr + {2, OperandInfo230}, // Inst #1896 = FCVTNSUWSr + {2, OperandInfo231}, // Inst #1897 = FCVTNSUXDr + {2, OperandInfo232}, // Inst #1898 = FCVTNSUXHr + {2, OperandInfo233}, // Inst #1899 = FCVTNSUXSr + {2, OperandInfo212}, // Inst #1900 = FCVTNSv1f16 + {2, OperandInfo213}, // Inst #1901 = FCVTNSv1i32 + {2, OperandInfo91}, // Inst #1902 = FCVTNSv1i64 + {2, OperandInfo91}, // Inst #1903 = FCVTNSv2f32 + {2, OperandInfo90}, // Inst #1904 = FCVTNSv2f64 + {2, OperandInfo91}, // Inst #1905 = FCVTNSv4f16 + {2, OperandInfo90}, // Inst #1906 = FCVTNSv4f32 + {2, OperandInfo90}, // Inst #1907 = FCVTNSv8f16 + {4, OperandInfo89}, // Inst #1908 = FCVTNT_ZPmZ_DtoS + {4, OperandInfo89}, // Inst #1909 = FCVTNT_ZPmZ_StoH + {2, OperandInfo228}, // Inst #1910 = FCVTNUUWDr + {2, OperandInfo229}, // Inst #1911 = FCVTNUUWHr + {2, OperandInfo230}, // Inst #1912 = FCVTNUUWSr + {2, OperandInfo231}, // Inst #1913 = FCVTNUUXDr + {2, OperandInfo232}, // Inst #1914 = FCVTNUUXHr + {2, OperandInfo233}, // Inst #1915 = FCVTNUUXSr + {2, OperandInfo212}, // Inst #1916 = FCVTNUv1f16 + {2, OperandInfo213}, // Inst #1917 = FCVTNUv1i32 + {2, OperandInfo91}, // Inst #1918 = FCVTNUv1i64 + {2, OperandInfo91}, // Inst #1919 = FCVTNUv2f32 + {2, OperandInfo90}, // Inst #1920 = FCVTNUv2f64 + {2, OperandInfo91}, // Inst #1921 = FCVTNUv4f16 + {2, OperandInfo90}, // Inst #1922 = FCVTNUv4f32 + {2, OperandInfo90}, // Inst #1923 = FCVTNUv8f16 + {2, OperandInfo103}, // Inst #1924 = FCVTNv2i32 + {2, OperandInfo103}, // Inst #1925 = FCVTNv4i16 + {3, OperandInfo124}, // Inst #1926 = FCVTNv4i32 + {3, OperandInfo124}, // Inst #1927 = FCVTNv8i16 + {2, OperandInfo228}, // Inst #1928 = FCVTPSUWDr + {2, OperandInfo229}, // Inst #1929 = FCVTPSUWHr + {2, OperandInfo230}, // Inst #1930 = FCVTPSUWSr + {2, OperandInfo231}, // Inst #1931 = FCVTPSUXDr + {2, OperandInfo232}, // Inst #1932 = FCVTPSUXHr + {2, OperandInfo233}, // Inst #1933 = FCVTPSUXSr + {2, OperandInfo212}, // Inst #1934 = FCVTPSv1f16 + {2, OperandInfo213}, // Inst #1935 = FCVTPSv1i32 + {2, OperandInfo91}, // Inst #1936 = FCVTPSv1i64 + {2, OperandInfo91}, // Inst #1937 = FCVTPSv2f32 + {2, OperandInfo90}, // Inst #1938 = FCVTPSv2f64 + {2, OperandInfo91}, // Inst #1939 = FCVTPSv4f16 + {2, OperandInfo90}, // Inst #1940 = FCVTPSv4f32 + {2, OperandInfo90}, // Inst #1941 = FCVTPSv8f16 + {2, OperandInfo228}, // Inst #1942 = FCVTPUUWDr + {2, OperandInfo229}, // Inst #1943 = FCVTPUUWHr + {2, OperandInfo230}, // Inst #1944 = FCVTPUUWSr + {2, OperandInfo231}, // Inst #1945 = FCVTPUUXDr + {2, OperandInfo232}, // Inst #1946 = FCVTPUUXHr + {2, OperandInfo233}, // Inst #1947 = FCVTPUUXSr + {2, OperandInfo212}, // Inst #1948 = FCVTPUv1f16 + {2, OperandInfo213}, // Inst #1949 = FCVTPUv1i32 + {2, OperandInfo91}, // Inst #1950 = FCVTPUv1i64 + {2, OperandInfo91}, // Inst #1951 = FCVTPUv2f32 + {2, OperandInfo90}, // Inst #1952 = FCVTPUv2f64 + {2, OperandInfo91}, // Inst #1953 = FCVTPUv4f16 + {2, OperandInfo90}, // Inst #1954 = FCVTPUv4f32 + {2, OperandInfo90}, // Inst #1955 = FCVTPUv8f16 + {2, OperandInfo214}, // Inst #1956 = FCVTSDr + {2, OperandInfo237}, // Inst #1957 = FCVTSHr + {4, OperandInfo89}, // Inst #1958 = FCVTXNT_ZPmZ_DtoS + {2, OperandInfo214}, // Inst #1959 = FCVTXNv1i64 + {2, OperandInfo103}, // Inst #1960 = FCVTXNv2f32 + {3, OperandInfo124}, // Inst #1961 = FCVTXNv4f32 + {4, OperandInfo89}, // Inst #1962 = FCVTX_ZPmZ_DtoS + {3, OperandInfo238}, // Inst #1963 = FCVTZSSWDri + {3, OperandInfo239}, // Inst #1964 = FCVTZSSWHri + {3, OperandInfo240}, // Inst #1965 = FCVTZSSWSri + {3, OperandInfo241}, // Inst #1966 = FCVTZSSXDri + {3, OperandInfo242}, // Inst #1967 = FCVTZSSXHri + {3, OperandInfo243}, // Inst #1968 = FCVTZSSXSri + {2, OperandInfo228}, // Inst #1969 = FCVTZSUWDr + {2, OperandInfo229}, // Inst #1970 = FCVTZSUWHr + {2, OperandInfo230}, // Inst #1971 = FCVTZSUWSr + {2, OperandInfo231}, // Inst #1972 = FCVTZSUXDr + {2, OperandInfo232}, // Inst #1973 = FCVTZSUXHr + {2, OperandInfo233}, // Inst #1974 = FCVTZSUXSr + {4, OperandInfo89}, // Inst #1975 = FCVTZS_ZPmZ_DtoD + {4, OperandInfo89}, // Inst #1976 = FCVTZS_ZPmZ_DtoS + {4, OperandInfo89}, // Inst #1977 = FCVTZS_ZPmZ_HtoD + {4, OperandInfo89}, // Inst #1978 = FCVTZS_ZPmZ_HtoH + {4, OperandInfo89}, // Inst #1979 = FCVTZS_ZPmZ_HtoS + {4, OperandInfo89}, // Inst #1980 = FCVTZS_ZPmZ_StoD + {4, OperandInfo89}, // Inst #1981 = FCVTZS_ZPmZ_StoS + {3, OperandInfo244}, // Inst #1982 = FCVTZSd + {3, OperandInfo245}, // Inst #1983 = FCVTZSh + {3, OperandInfo246}, // Inst #1984 = FCVTZSs + {2, OperandInfo212}, // Inst #1985 = FCVTZSv1f16 + {2, OperandInfo213}, // Inst #1986 = FCVTZSv1i32 + {2, OperandInfo91}, // Inst #1987 = FCVTZSv1i64 + {2, OperandInfo91}, // Inst #1988 = FCVTZSv2f32 + {2, OperandInfo90}, // Inst #1989 = FCVTZSv2f64 + {3, OperandInfo244}, // Inst #1990 = FCVTZSv2i32_shift + {3, OperandInfo199}, // Inst #1991 = FCVTZSv2i64_shift + {2, OperandInfo91}, // Inst #1992 = FCVTZSv4f16 + {2, OperandInfo90}, // Inst #1993 = FCVTZSv4f32 + {3, OperandInfo244}, // Inst #1994 = FCVTZSv4i16_shift + {3, OperandInfo199}, // Inst #1995 = FCVTZSv4i32_shift + {2, OperandInfo90}, // Inst #1996 = FCVTZSv8f16 + {3, OperandInfo199}, // Inst #1997 = FCVTZSv8i16_shift + {3, OperandInfo238}, // Inst #1998 = FCVTZUSWDri + {3, OperandInfo239}, // Inst #1999 = FCVTZUSWHri + {3, OperandInfo240}, // Inst #2000 = FCVTZUSWSri + {3, OperandInfo241}, // Inst #2001 = FCVTZUSXDri + {3, OperandInfo242}, // Inst #2002 = FCVTZUSXHri + {3, OperandInfo243}, // Inst #2003 = FCVTZUSXSri + {2, OperandInfo228}, // Inst #2004 = FCVTZUUWDr + {2, OperandInfo229}, // Inst #2005 = FCVTZUUWHr + {2, OperandInfo230}, // Inst #2006 = FCVTZUUWSr + {2, OperandInfo231}, // Inst #2007 = FCVTZUUXDr + {2, OperandInfo232}, // Inst #2008 = FCVTZUUXHr + {2, OperandInfo233}, // Inst #2009 = FCVTZUUXSr + {4, OperandInfo89}, // Inst #2010 = FCVTZU_ZPmZ_DtoD + {4, OperandInfo89}, // Inst #2011 = FCVTZU_ZPmZ_DtoS + {4, OperandInfo89}, // Inst #2012 = FCVTZU_ZPmZ_HtoD + {4, OperandInfo89}, // Inst #2013 = FCVTZU_ZPmZ_HtoH + {4, OperandInfo89}, // Inst #2014 = FCVTZU_ZPmZ_HtoS + {4, OperandInfo89}, // Inst #2015 = FCVTZU_ZPmZ_StoD + {4, OperandInfo89}, // Inst #2016 = FCVTZU_ZPmZ_StoS + {3, OperandInfo244}, // Inst #2017 = FCVTZUd + {3, OperandInfo245}, // Inst #2018 = FCVTZUh + {3, OperandInfo246}, // Inst #2019 = FCVTZUs + {2, OperandInfo212}, // Inst #2020 = FCVTZUv1f16 + {2, OperandInfo213}, // Inst #2021 = FCVTZUv1i32 + {2, OperandInfo91}, // Inst #2022 = FCVTZUv1i64 + {2, OperandInfo91}, // Inst #2023 = FCVTZUv2f32 + {2, OperandInfo90}, // Inst #2024 = FCVTZUv2f64 + {3, OperandInfo244}, // Inst #2025 = FCVTZUv2i32_shift + {3, OperandInfo199}, // Inst #2026 = FCVTZUv2i64_shift + {2, OperandInfo91}, // Inst #2027 = FCVTZUv4f16 + {2, OperandInfo90}, // Inst #2028 = FCVTZUv4f32 + {3, OperandInfo244}, // Inst #2029 = FCVTZUv4i16_shift + {3, OperandInfo199}, // Inst #2030 = FCVTZUv4i32_shift + {2, OperandInfo90}, // Inst #2031 = FCVTZUv8f16 + {3, OperandInfo199}, // Inst #2032 = FCVTZUv8i16_shift + {4, OperandInfo89}, // Inst #2033 = FCVT_ZPmZ_DtoH + {4, OperandInfo89}, // Inst #2034 = FCVT_ZPmZ_DtoS + {4, OperandInfo89}, // Inst #2035 = FCVT_ZPmZ_HtoD + {4, OperandInfo89}, // Inst #2036 = FCVT_ZPmZ_HtoS + {4, OperandInfo89}, // Inst #2037 = FCVT_ZPmZ_StoD + {4, OperandInfo89}, // Inst #2038 = FCVT_ZPmZ_StoH + {3, OperandInfo102}, // Inst #2039 = FDIVDrr + {3, OperandInfo210}, // Inst #2040 = FDIVHrr + {4, OperandInfo100}, // Inst #2041 = FDIVR_ZPmZ_D + {4, OperandInfo100}, // Inst #2042 = FDIVR_ZPmZ_H + {4, OperandInfo100}, // Inst #2043 = FDIVR_ZPmZ_S + {3, OperandInfo211}, // Inst #2044 = FDIVSrr + {4, OperandInfo100}, // Inst #2045 = FDIV_ZPmZ_D + {4, OperandInfo100}, // Inst #2046 = FDIV_ZPmZ_H + {4, OperandInfo100}, // Inst #2047 = FDIV_ZPmZ_S + {3, OperandInfo102}, // Inst #2048 = FDIVv2f32 + {3, OperandInfo101}, // Inst #2049 = FDIVv2f64 + {3, OperandInfo102}, // Inst #2050 = FDIVv4f16 + {3, OperandInfo101}, // Inst #2051 = FDIVv4f32 + {3, OperandInfo101}, // Inst #2052 = FDIVv8f16 + {2, OperandInfo194}, // Inst #2053 = FDUP_ZI_D + {2, OperandInfo194}, // Inst #2054 = FDUP_ZI_H + {2, OperandInfo194}, // Inst #2055 = FDUP_ZI_S + {2, OperandInfo247}, // Inst #2056 = FEXPA_ZZ_D + {2, OperandInfo247}, // Inst #2057 = FEXPA_ZZ_H + {2, OperandInfo247}, // Inst #2058 = FEXPA_ZZ_S + {2, OperandInfo228}, // Inst #2059 = FJCVTZS + {4, OperandInfo89}, // Inst #2060 = FLOGB_ZPmZ_D + {4, OperandInfo89}, // Inst #2061 = FLOGB_ZPmZ_H + {4, OperandInfo89}, // Inst #2062 = FLOGB_ZPmZ_S + {4, OperandInfo53}, // Inst #2063 = FMADDDrrr + {4, OperandInfo248}, // Inst #2064 = FMADDHrrr + {4, OperandInfo249}, // Inst #2065 = FMADDSrrr + {5, OperandInfo250}, // Inst #2066 = FMAD_ZPmZZ_D + {5, OperandInfo250}, // Inst #2067 = FMAD_ZPmZZ_H + {5, OperandInfo250}, // Inst #2068 = FMAD_ZPmZZ_S + {3, OperandInfo102}, // Inst #2069 = FMAXDrr + {3, OperandInfo210}, // Inst #2070 = FMAXHrr + {3, OperandInfo102}, // Inst #2071 = FMAXNMDrr + {3, OperandInfo210}, // Inst #2072 = FMAXNMHrr + {4, OperandInfo100}, // Inst #2073 = FMAXNMP_ZPmZZ_D + {4, OperandInfo100}, // Inst #2074 = FMAXNMP_ZPmZZ_H + {4, OperandInfo100}, // Inst #2075 = FMAXNMP_ZPmZZ_S + {3, OperandInfo102}, // Inst #2076 = FMAXNMPv2f32 + {3, OperandInfo101}, // Inst #2077 = FMAXNMPv2f64 + {2, OperandInfo112}, // Inst #2078 = FMAXNMPv2i16p + {2, OperandInfo214}, // Inst #2079 = FMAXNMPv2i32p + {2, OperandInfo103}, // Inst #2080 = FMAXNMPv2i64p + {3, OperandInfo102}, // Inst #2081 = FMAXNMPv4f16 + {3, OperandInfo101}, // Inst #2082 = FMAXNMPv4f32 + {3, OperandInfo101}, // Inst #2083 = FMAXNMPv8f16 + {3, OperandInfo211}, // Inst #2084 = FMAXNMSrr + {3, OperandInfo129}, // Inst #2085 = FMAXNMV_VPZ_D + {3, OperandInfo129}, // Inst #2086 = FMAXNMV_VPZ_H + {3, OperandInfo129}, // Inst #2087 = FMAXNMV_VPZ_S + {2, OperandInfo112}, // Inst #2088 = FMAXNMVv4i16v + {2, OperandInfo113}, // Inst #2089 = FMAXNMVv4i32v + {2, OperandInfo114}, // Inst #2090 = FMAXNMVv8i16v + {4, OperandInfo133}, // Inst #2091 = FMAXNM_ZPmI_D + {4, OperandInfo133}, // Inst #2092 = FMAXNM_ZPmI_H + {4, OperandInfo133}, // Inst #2093 = FMAXNM_ZPmI_S + {4, OperandInfo100}, // Inst #2094 = FMAXNM_ZPmZ_D + {4, OperandInfo100}, // Inst #2095 = FMAXNM_ZPmZ_H + {4, OperandInfo100}, // Inst #2096 = FMAXNM_ZPmZ_S + {3, OperandInfo102}, // Inst #2097 = FMAXNMv2f32 + {3, OperandInfo101}, // Inst #2098 = FMAXNMv2f64 + {3, OperandInfo102}, // Inst #2099 = FMAXNMv4f16 + {3, OperandInfo101}, // Inst #2100 = FMAXNMv4f32 + {3, OperandInfo101}, // Inst #2101 = FMAXNMv8f16 + {4, OperandInfo100}, // Inst #2102 = FMAXP_ZPmZZ_D + {4, OperandInfo100}, // Inst #2103 = FMAXP_ZPmZZ_H + {4, OperandInfo100}, // Inst #2104 = FMAXP_ZPmZZ_S + {3, OperandInfo102}, // Inst #2105 = FMAXPv2f32 + {3, OperandInfo101}, // Inst #2106 = FMAXPv2f64 + {2, OperandInfo112}, // Inst #2107 = FMAXPv2i16p + {2, OperandInfo214}, // Inst #2108 = FMAXPv2i32p + {2, OperandInfo103}, // Inst #2109 = FMAXPv2i64p + {3, OperandInfo102}, // Inst #2110 = FMAXPv4f16 + {3, OperandInfo101}, // Inst #2111 = FMAXPv4f32 + {3, OperandInfo101}, // Inst #2112 = FMAXPv8f16 + {3, OperandInfo211}, // Inst #2113 = FMAXSrr + {3, OperandInfo129}, // Inst #2114 = FMAXV_VPZ_D + {3, OperandInfo129}, // Inst #2115 = FMAXV_VPZ_H + {3, OperandInfo129}, // Inst #2116 = FMAXV_VPZ_S + {2, OperandInfo112}, // Inst #2117 = FMAXVv4i16v + {2, OperandInfo113}, // Inst #2118 = FMAXVv4i32v + {2, OperandInfo114}, // Inst #2119 = FMAXVv8i16v + {4, OperandInfo133}, // Inst #2120 = FMAX_ZPmI_D + {4, OperandInfo133}, // Inst #2121 = FMAX_ZPmI_H + {4, OperandInfo133}, // Inst #2122 = FMAX_ZPmI_S + {4, OperandInfo100}, // Inst #2123 = FMAX_ZPmZ_D + {4, OperandInfo100}, // Inst #2124 = FMAX_ZPmZ_H + {4, OperandInfo100}, // Inst #2125 = FMAX_ZPmZ_S + {3, OperandInfo102}, // Inst #2126 = FMAXv2f32 + {3, OperandInfo101}, // Inst #2127 = FMAXv2f64 + {3, OperandInfo102}, // Inst #2128 = FMAXv4f16 + {3, OperandInfo101}, // Inst #2129 = FMAXv4f32 + {3, OperandInfo101}, // Inst #2130 = FMAXv8f16 + {3, OperandInfo102}, // Inst #2131 = FMINDrr + {3, OperandInfo210}, // Inst #2132 = FMINHrr + {3, OperandInfo102}, // Inst #2133 = FMINNMDrr + {3, OperandInfo210}, // Inst #2134 = FMINNMHrr + {4, OperandInfo100}, // Inst #2135 = FMINNMP_ZPmZZ_D + {4, OperandInfo100}, // Inst #2136 = FMINNMP_ZPmZZ_H + {4, OperandInfo100}, // Inst #2137 = FMINNMP_ZPmZZ_S + {3, OperandInfo102}, // Inst #2138 = FMINNMPv2f32 + {3, OperandInfo101}, // Inst #2139 = FMINNMPv2f64 + {2, OperandInfo112}, // Inst #2140 = FMINNMPv2i16p + {2, OperandInfo214}, // Inst #2141 = FMINNMPv2i32p + {2, OperandInfo103}, // Inst #2142 = FMINNMPv2i64p + {3, OperandInfo102}, // Inst #2143 = FMINNMPv4f16 + {3, OperandInfo101}, // Inst #2144 = FMINNMPv4f32 + {3, OperandInfo101}, // Inst #2145 = FMINNMPv8f16 + {3, OperandInfo211}, // Inst #2146 = FMINNMSrr + {3, OperandInfo129}, // Inst #2147 = FMINNMV_VPZ_D + {3, OperandInfo129}, // Inst #2148 = FMINNMV_VPZ_H + {3, OperandInfo129}, // Inst #2149 = FMINNMV_VPZ_S + {2, OperandInfo112}, // Inst #2150 = FMINNMVv4i16v + {2, OperandInfo113}, // Inst #2151 = FMINNMVv4i32v + {2, OperandInfo114}, // Inst #2152 = FMINNMVv8i16v + {4, OperandInfo133}, // Inst #2153 = FMINNM_ZPmI_D + {4, OperandInfo133}, // Inst #2154 = FMINNM_ZPmI_H + {4, OperandInfo133}, // Inst #2155 = FMINNM_ZPmI_S + {4, OperandInfo100}, // Inst #2156 = FMINNM_ZPmZ_D + {4, OperandInfo100}, // Inst #2157 = FMINNM_ZPmZ_H + {4, OperandInfo100}, // Inst #2158 = FMINNM_ZPmZ_S + {3, OperandInfo102}, // Inst #2159 = FMINNMv2f32 + {3, OperandInfo101}, // Inst #2160 = FMINNMv2f64 + {3, OperandInfo102}, // Inst #2161 = FMINNMv4f16 + {3, OperandInfo101}, // Inst #2162 = FMINNMv4f32 + {3, OperandInfo101}, // Inst #2163 = FMINNMv8f16 + {4, OperandInfo100}, // Inst #2164 = FMINP_ZPmZZ_D + {4, OperandInfo100}, // Inst #2165 = FMINP_ZPmZZ_H + {4, OperandInfo100}, // Inst #2166 = FMINP_ZPmZZ_S + {3, OperandInfo102}, // Inst #2167 = FMINPv2f32 + {3, OperandInfo101}, // Inst #2168 = FMINPv2f64 + {2, OperandInfo112}, // Inst #2169 = FMINPv2i16p + {2, OperandInfo214}, // Inst #2170 = FMINPv2i32p + {2, OperandInfo103}, // Inst #2171 = FMINPv2i64p + {3, OperandInfo102}, // Inst #2172 = FMINPv4f16 + {3, OperandInfo101}, // Inst #2173 = FMINPv4f32 + {3, OperandInfo101}, // Inst #2174 = FMINPv8f16 + {3, OperandInfo211}, // Inst #2175 = FMINSrr + {3, OperandInfo129}, // Inst #2176 = FMINV_VPZ_D + {3, OperandInfo129}, // Inst #2177 = FMINV_VPZ_H + {3, OperandInfo129}, // Inst #2178 = FMINV_VPZ_S + {2, OperandInfo112}, // Inst #2179 = FMINVv4i16v + {2, OperandInfo113}, // Inst #2180 = FMINVv4i32v + {2, OperandInfo114}, // Inst #2181 = FMINVv8i16v + {4, OperandInfo133}, // Inst #2182 = FMIN_ZPmI_D + {4, OperandInfo133}, // Inst #2183 = FMIN_ZPmI_H + {4, OperandInfo133}, // Inst #2184 = FMIN_ZPmI_S + {4, OperandInfo100}, // Inst #2185 = FMIN_ZPmZ_D + {4, OperandInfo100}, // Inst #2186 = FMIN_ZPmZ_H + {4, OperandInfo100}, // Inst #2187 = FMIN_ZPmZ_S + {3, OperandInfo102}, // Inst #2188 = FMINv2f32 + {3, OperandInfo101}, // Inst #2189 = FMINv2f64 + {3, OperandInfo102}, // Inst #2190 = FMINv4f16 + {3, OperandInfo101}, // Inst #2191 = FMINv4f32 + {3, OperandInfo101}, // Inst #2192 = FMINv8f16 + {5, OperandInfo138}, // Inst #2193 = FMLAL2lanev4f16 + {5, OperandInfo139}, // Inst #2194 = FMLAL2lanev8f16 + {4, OperandInfo142}, // Inst #2195 = FMLAL2v4f16 + {4, OperandInfo98}, // Inst #2196 = FMLAL2v8f16 + {5, OperandInfo141}, // Inst #2197 = FMLALB_ZZZI_SHH + {4, OperandInfo92}, // Inst #2198 = FMLALB_ZZZ_SHH + {5, OperandInfo141}, // Inst #2199 = FMLALT_ZZZI_SHH + {4, OperandInfo92}, // Inst #2200 = FMLALT_ZZZ_SHH + {5, OperandInfo138}, // Inst #2201 = FMLALlanev4f16 + {5, OperandInfo139}, // Inst #2202 = FMLALlanev8f16 + {4, OperandInfo142}, // Inst #2203 = FMLALv4f16 + {4, OperandInfo98}, // Inst #2204 = FMLALv8f16 + {5, OperandInfo250}, // Inst #2205 = FMLA_ZPmZZ_D + {5, OperandInfo250}, // Inst #2206 = FMLA_ZPmZZ_H + {5, OperandInfo250}, // Inst #2207 = FMLA_ZPmZZ_S + {5, OperandInfo251}, // Inst #2208 = FMLA_ZZZI_D + {5, OperandInfo141}, // Inst #2209 = FMLA_ZZZI_H + {5, OperandInfo141}, // Inst #2210 = FMLA_ZZZI_S + {5, OperandInfo252}, // Inst #2211 = FMLAv1i16_indexed + {5, OperandInfo253}, // Inst #2212 = FMLAv1i32_indexed + {5, OperandInfo138}, // Inst #2213 = FMLAv1i64_indexed + {4, OperandInfo142}, // Inst #2214 = FMLAv2f32 + {4, OperandInfo98}, // Inst #2215 = FMLAv2f64 + {5, OperandInfo138}, // Inst #2216 = FMLAv2i32_indexed + {5, OperandInfo139}, // Inst #2217 = FMLAv2i64_indexed + {4, OperandInfo142}, // Inst #2218 = FMLAv4f16 + {4, OperandInfo98}, // Inst #2219 = FMLAv4f32 + {5, OperandInfo254}, // Inst #2220 = FMLAv4i16_indexed + {5, OperandInfo139}, // Inst #2221 = FMLAv4i32_indexed + {4, OperandInfo98}, // Inst #2222 = FMLAv8f16 + {5, OperandInfo143}, // Inst #2223 = FMLAv8i16_indexed + {5, OperandInfo138}, // Inst #2224 = FMLSL2lanev4f16 + {5, OperandInfo139}, // Inst #2225 = FMLSL2lanev8f16 + {4, OperandInfo142}, // Inst #2226 = FMLSL2v4f16 + {4, OperandInfo98}, // Inst #2227 = FMLSL2v8f16 + {5, OperandInfo141}, // Inst #2228 = FMLSLB_ZZZI_SHH + {4, OperandInfo92}, // Inst #2229 = FMLSLB_ZZZ_SHH + {5, OperandInfo141}, // Inst #2230 = FMLSLT_ZZZI_SHH + {4, OperandInfo92}, // Inst #2231 = FMLSLT_ZZZ_SHH + {5, OperandInfo138}, // Inst #2232 = FMLSLlanev4f16 + {5, OperandInfo139}, // Inst #2233 = FMLSLlanev8f16 + {4, OperandInfo142}, // Inst #2234 = FMLSLv4f16 + {4, OperandInfo98}, // Inst #2235 = FMLSLv8f16 + {5, OperandInfo250}, // Inst #2236 = FMLS_ZPmZZ_D + {5, OperandInfo250}, // Inst #2237 = FMLS_ZPmZZ_H + {5, OperandInfo250}, // Inst #2238 = FMLS_ZPmZZ_S + {5, OperandInfo251}, // Inst #2239 = FMLS_ZZZI_D + {5, OperandInfo141}, // Inst #2240 = FMLS_ZZZI_H + {5, OperandInfo141}, // Inst #2241 = FMLS_ZZZI_S + {5, OperandInfo252}, // Inst #2242 = FMLSv1i16_indexed + {5, OperandInfo253}, // Inst #2243 = FMLSv1i32_indexed + {5, OperandInfo138}, // Inst #2244 = FMLSv1i64_indexed + {4, OperandInfo142}, // Inst #2245 = FMLSv2f32 + {4, OperandInfo98}, // Inst #2246 = FMLSv2f64 + {5, OperandInfo138}, // Inst #2247 = FMLSv2i32_indexed + {5, OperandInfo139}, // Inst #2248 = FMLSv2i64_indexed + {4, OperandInfo142}, // Inst #2249 = FMLSv4f16 + {4, OperandInfo98}, // Inst #2250 = FMLSv4f32 + {5, OperandInfo254}, // Inst #2251 = FMLSv4i16_indexed + {5, OperandInfo139}, // Inst #2252 = FMLSv4i32_indexed + {4, OperandInfo98}, // Inst #2253 = FMLSv8f16 + {5, OperandInfo143}, // Inst #2254 = FMLSv8i16_indexed + {4, OperandInfo92}, // Inst #2255 = FMMLA_ZZZ_D + {4, OperandInfo92}, // Inst #2256 = FMMLA_ZZZ_S + {5, OperandInfo255}, // Inst #2257 = FMOPA_MPPZZ_D + {5, OperandInfo256}, // Inst #2258 = FMOPA_MPPZZ_S + {5, OperandInfo255}, // Inst #2259 = FMOPS_MPPZZ_D + {5, OperandInfo256}, // Inst #2260 = FMOPS_MPPZZ_S + {3, OperandInfo257}, // Inst #2261 = FMOVDXHighr + {2, OperandInfo231}, // Inst #2262 = FMOVDXr + {2, OperandInfo258}, // Inst #2263 = FMOVDi + {2, OperandInfo91}, // Inst #2264 = FMOVDr + {2, OperandInfo229}, // Inst #2265 = FMOVHWr + {2, OperandInfo232}, // Inst #2266 = FMOVHXr + {2, OperandInfo259}, // Inst #2267 = FMOVHi + {2, OperandInfo212}, // Inst #2268 = FMOVHr + {2, OperandInfo230}, // Inst #2269 = FMOVSWr + {2, OperandInfo260}, // Inst #2270 = FMOVSi + {2, OperandInfo213}, // Inst #2271 = FMOVSr + {2, OperandInfo261}, // Inst #2272 = FMOVWHr + {2, OperandInfo262}, // Inst #2273 = FMOVWSr + {3, OperandInfo263}, // Inst #2274 = FMOVXDHighr + {2, OperandInfo264}, // Inst #2275 = FMOVXDr + {2, OperandInfo265}, // Inst #2276 = FMOVXHr + {2, OperandInfo258}, // Inst #2277 = FMOVv2f32_ns + {2, OperandInfo266}, // Inst #2278 = FMOVv2f64_ns + {2, OperandInfo258}, // Inst #2279 = FMOVv4f16_ns + {2, OperandInfo266}, // Inst #2280 = FMOVv4f32_ns + {2, OperandInfo266}, // Inst #2281 = FMOVv8f16_ns + {5, OperandInfo250}, // Inst #2282 = FMSB_ZPmZZ_D + {5, OperandInfo250}, // Inst #2283 = FMSB_ZPmZZ_H + {5, OperandInfo250}, // Inst #2284 = FMSB_ZPmZZ_S + {4, OperandInfo53}, // Inst #2285 = FMSUBDrrr + {4, OperandInfo248}, // Inst #2286 = FMSUBHrrr + {4, OperandInfo249}, // Inst #2287 = FMSUBSrrr + {3, OperandInfo102}, // Inst #2288 = FMULDrr + {3, OperandInfo210}, // Inst #2289 = FMULHrr + {3, OperandInfo211}, // Inst #2290 = FMULSrr + {3, OperandInfo210}, // Inst #2291 = FMULX16 + {3, OperandInfo211}, // Inst #2292 = FMULX32 + {3, OperandInfo102}, // Inst #2293 = FMULX64 + {4, OperandInfo100}, // Inst #2294 = FMULX_ZPmZ_D + {4, OperandInfo100}, // Inst #2295 = FMULX_ZPmZ_H + {4, OperandInfo100}, // Inst #2296 = FMULX_ZPmZ_S + {4, OperandInfo267}, // Inst #2297 = FMULXv1i16_indexed + {4, OperandInfo268}, // Inst #2298 = FMULXv1i32_indexed + {4, OperandInfo269}, // Inst #2299 = FMULXv1i64_indexed + {3, OperandInfo102}, // Inst #2300 = FMULXv2f32 + {3, OperandInfo101}, // Inst #2301 = FMULXv2f64 + {4, OperandInfo269}, // Inst #2302 = FMULXv2i32_indexed + {4, OperandInfo58}, // Inst #2303 = FMULXv2i64_indexed + {3, OperandInfo102}, // Inst #2304 = FMULXv4f16 + {3, OperandInfo101}, // Inst #2305 = FMULXv4f32 + {4, OperandInfo270}, // Inst #2306 = FMULXv4i16_indexed + {4, OperandInfo58}, // Inst #2307 = FMULXv4i32_indexed + {3, OperandInfo101}, // Inst #2308 = FMULXv8f16 + {4, OperandInfo271}, // Inst #2309 = FMULXv8i16_indexed + {4, OperandInfo133}, // Inst #2310 = FMUL_ZPmI_D + {4, OperandInfo133}, // Inst #2311 = FMUL_ZPmI_H + {4, OperandInfo133}, // Inst #2312 = FMUL_ZPmI_S + {4, OperandInfo100}, // Inst #2313 = FMUL_ZPmZ_D + {4, OperandInfo100}, // Inst #2314 = FMUL_ZPmZ_H + {4, OperandInfo100}, // Inst #2315 = FMUL_ZPmZ_S + {4, OperandInfo272}, // Inst #2316 = FMUL_ZZZI_D + {4, OperandInfo273}, // Inst #2317 = FMUL_ZZZI_H + {4, OperandInfo273}, // Inst #2318 = FMUL_ZZZI_S + {3, OperandInfo96}, // Inst #2319 = FMUL_ZZZ_D + {3, OperandInfo96}, // Inst #2320 = FMUL_ZZZ_H + {3, OperandInfo96}, // Inst #2321 = FMUL_ZZZ_S + {4, OperandInfo267}, // Inst #2322 = FMULv1i16_indexed + {4, OperandInfo268}, // Inst #2323 = FMULv1i32_indexed + {4, OperandInfo269}, // Inst #2324 = FMULv1i64_indexed + {3, OperandInfo102}, // Inst #2325 = FMULv2f32 + {3, OperandInfo101}, // Inst #2326 = FMULv2f64 + {4, OperandInfo269}, // Inst #2327 = FMULv2i32_indexed + {4, OperandInfo58}, // Inst #2328 = FMULv2i64_indexed + {3, OperandInfo102}, // Inst #2329 = FMULv4f16 + {3, OperandInfo101}, // Inst #2330 = FMULv4f32 + {4, OperandInfo270}, // Inst #2331 = FMULv4i16_indexed + {4, OperandInfo58}, // Inst #2332 = FMULv4i32_indexed + {3, OperandInfo101}, // Inst #2333 = FMULv8f16 + {4, OperandInfo271}, // Inst #2334 = FMULv8i16_indexed + {2, OperandInfo91}, // Inst #2335 = FNEGDr + {2, OperandInfo212}, // Inst #2336 = FNEGHr + {2, OperandInfo213}, // Inst #2337 = FNEGSr + {4, OperandInfo89}, // Inst #2338 = FNEG_ZPmZ_D + {4, OperandInfo89}, // Inst #2339 = FNEG_ZPmZ_H + {4, OperandInfo89}, // Inst #2340 = FNEG_ZPmZ_S + {2, OperandInfo91}, // Inst #2341 = FNEGv2f32 + {2, OperandInfo90}, // Inst #2342 = FNEGv2f64 + {2, OperandInfo91}, // Inst #2343 = FNEGv4f16 + {2, OperandInfo90}, // Inst #2344 = FNEGv4f32 + {2, OperandInfo90}, // Inst #2345 = FNEGv8f16 + {4, OperandInfo53}, // Inst #2346 = FNMADDDrrr + {4, OperandInfo248}, // Inst #2347 = FNMADDHrrr + {4, OperandInfo249}, // Inst #2348 = FNMADDSrrr + {5, OperandInfo250}, // Inst #2349 = FNMAD_ZPmZZ_D + {5, OperandInfo250}, // Inst #2350 = FNMAD_ZPmZZ_H + {5, OperandInfo250}, // Inst #2351 = FNMAD_ZPmZZ_S + {5, OperandInfo250}, // Inst #2352 = FNMLA_ZPmZZ_D + {5, OperandInfo250}, // Inst #2353 = FNMLA_ZPmZZ_H + {5, OperandInfo250}, // Inst #2354 = FNMLA_ZPmZZ_S + {5, OperandInfo250}, // Inst #2355 = FNMLS_ZPmZZ_D + {5, OperandInfo250}, // Inst #2356 = FNMLS_ZPmZZ_H + {5, OperandInfo250}, // Inst #2357 = FNMLS_ZPmZZ_S + {5, OperandInfo250}, // Inst #2358 = FNMSB_ZPmZZ_D + {5, OperandInfo250}, // Inst #2359 = FNMSB_ZPmZZ_H + {5, OperandInfo250}, // Inst #2360 = FNMSB_ZPmZZ_S + {4, OperandInfo53}, // Inst #2361 = FNMSUBDrrr + {4, OperandInfo248}, // Inst #2362 = FNMSUBHrrr + {4, OperandInfo249}, // Inst #2363 = FNMSUBSrrr + {3, OperandInfo102}, // Inst #2364 = FNMULDrr + {3, OperandInfo210}, // Inst #2365 = FNMULHrr + {3, OperandInfo211}, // Inst #2366 = FNMULSrr + {2, OperandInfo247}, // Inst #2367 = FRECPE_ZZ_D + {2, OperandInfo247}, // Inst #2368 = FRECPE_ZZ_H + {2, OperandInfo247}, // Inst #2369 = FRECPE_ZZ_S + {2, OperandInfo212}, // Inst #2370 = FRECPEv1f16 + {2, OperandInfo213}, // Inst #2371 = FRECPEv1i32 + {2, OperandInfo91}, // Inst #2372 = FRECPEv1i64 + {2, OperandInfo91}, // Inst #2373 = FRECPEv2f32 + {2, OperandInfo90}, // Inst #2374 = FRECPEv2f64 + {2, OperandInfo91}, // Inst #2375 = FRECPEv4f16 + {2, OperandInfo90}, // Inst #2376 = FRECPEv4f32 + {2, OperandInfo90}, // Inst #2377 = FRECPEv8f16 + {3, OperandInfo210}, // Inst #2378 = FRECPS16 + {3, OperandInfo211}, // Inst #2379 = FRECPS32 + {3, OperandInfo102}, // Inst #2380 = FRECPS64 + {3, OperandInfo96}, // Inst #2381 = FRECPS_ZZZ_D + {3, OperandInfo96}, // Inst #2382 = FRECPS_ZZZ_H + {3, OperandInfo96}, // Inst #2383 = FRECPS_ZZZ_S + {3, OperandInfo102}, // Inst #2384 = FRECPSv2f32 + {3, OperandInfo101}, // Inst #2385 = FRECPSv2f64 + {3, OperandInfo102}, // Inst #2386 = FRECPSv4f16 + {3, OperandInfo101}, // Inst #2387 = FRECPSv4f32 + {3, OperandInfo101}, // Inst #2388 = FRECPSv8f16 + {4, OperandInfo89}, // Inst #2389 = FRECPX_ZPmZ_D + {4, OperandInfo89}, // Inst #2390 = FRECPX_ZPmZ_H + {4, OperandInfo89}, // Inst #2391 = FRECPX_ZPmZ_S + {2, OperandInfo212}, // Inst #2392 = FRECPXv1f16 + {2, OperandInfo213}, // Inst #2393 = FRECPXv1i32 + {2, OperandInfo91}, // Inst #2394 = FRECPXv1i64 + {2, OperandInfo91}, // Inst #2395 = FRINT32XDr + {2, OperandInfo213}, // Inst #2396 = FRINT32XSr + {2, OperandInfo91}, // Inst #2397 = FRINT32Xv2f32 + {2, OperandInfo90}, // Inst #2398 = FRINT32Xv2f64 + {2, OperandInfo90}, // Inst #2399 = FRINT32Xv4f32 + {2, OperandInfo91}, // Inst #2400 = FRINT32ZDr + {2, OperandInfo213}, // Inst #2401 = FRINT32ZSr + {2, OperandInfo91}, // Inst #2402 = FRINT32Zv2f32 + {2, OperandInfo90}, // Inst #2403 = FRINT32Zv2f64 + {2, OperandInfo90}, // Inst #2404 = FRINT32Zv4f32 + {2, OperandInfo91}, // Inst #2405 = FRINT64XDr + {2, OperandInfo213}, // Inst #2406 = FRINT64XSr + {2, OperandInfo91}, // Inst #2407 = FRINT64Xv2f32 + {2, OperandInfo90}, // Inst #2408 = FRINT64Xv2f64 + {2, OperandInfo90}, // Inst #2409 = FRINT64Xv4f32 + {2, OperandInfo91}, // Inst #2410 = FRINT64ZDr + {2, OperandInfo213}, // Inst #2411 = FRINT64ZSr + {2, OperandInfo91}, // Inst #2412 = FRINT64Zv2f32 + {2, OperandInfo90}, // Inst #2413 = FRINT64Zv2f64 + {2, OperandInfo90}, // Inst #2414 = FRINT64Zv4f32 + {2, OperandInfo91}, // Inst #2415 = FRINTADr + {2, OperandInfo212}, // Inst #2416 = FRINTAHr + {2, OperandInfo213}, // Inst #2417 = FRINTASr + {4, OperandInfo89}, // Inst #2418 = FRINTA_ZPmZ_D + {4, OperandInfo89}, // Inst #2419 = FRINTA_ZPmZ_H + {4, OperandInfo89}, // Inst #2420 = FRINTA_ZPmZ_S + {2, OperandInfo91}, // Inst #2421 = FRINTAv2f32 + {2, OperandInfo90}, // Inst #2422 = FRINTAv2f64 + {2, OperandInfo91}, // Inst #2423 = FRINTAv4f16 + {2, OperandInfo90}, // Inst #2424 = FRINTAv4f32 + {2, OperandInfo90}, // Inst #2425 = FRINTAv8f16 + {2, OperandInfo91}, // Inst #2426 = FRINTIDr + {2, OperandInfo212}, // Inst #2427 = FRINTIHr + {2, OperandInfo213}, // Inst #2428 = FRINTISr + {4, OperandInfo89}, // Inst #2429 = FRINTI_ZPmZ_D + {4, OperandInfo89}, // Inst #2430 = FRINTI_ZPmZ_H + {4, OperandInfo89}, // Inst #2431 = FRINTI_ZPmZ_S + {2, OperandInfo91}, // Inst #2432 = FRINTIv2f32 + {2, OperandInfo90}, // Inst #2433 = FRINTIv2f64 + {2, OperandInfo91}, // Inst #2434 = FRINTIv4f16 + {2, OperandInfo90}, // Inst #2435 = FRINTIv4f32 + {2, OperandInfo90}, // Inst #2436 = FRINTIv8f16 + {2, OperandInfo91}, // Inst #2437 = FRINTMDr + {2, OperandInfo212}, // Inst #2438 = FRINTMHr + {2, OperandInfo213}, // Inst #2439 = FRINTMSr + {4, OperandInfo89}, // Inst #2440 = FRINTM_ZPmZ_D + {4, OperandInfo89}, // Inst #2441 = FRINTM_ZPmZ_H + {4, OperandInfo89}, // Inst #2442 = FRINTM_ZPmZ_S + {2, OperandInfo91}, // Inst #2443 = FRINTMv2f32 + {2, OperandInfo90}, // Inst #2444 = FRINTMv2f64 + {2, OperandInfo91}, // Inst #2445 = FRINTMv4f16 + {2, OperandInfo90}, // Inst #2446 = FRINTMv4f32 + {2, OperandInfo90}, // Inst #2447 = FRINTMv8f16 + {2, OperandInfo91}, // Inst #2448 = FRINTNDr + {2, OperandInfo212}, // Inst #2449 = FRINTNHr + {2, OperandInfo213}, // Inst #2450 = FRINTNSr + {4, OperandInfo89}, // Inst #2451 = FRINTN_ZPmZ_D + {4, OperandInfo89}, // Inst #2452 = FRINTN_ZPmZ_H + {4, OperandInfo89}, // Inst #2453 = FRINTN_ZPmZ_S + {2, OperandInfo91}, // Inst #2454 = FRINTNv2f32 + {2, OperandInfo90}, // Inst #2455 = FRINTNv2f64 + {2, OperandInfo91}, // Inst #2456 = FRINTNv4f16 + {2, OperandInfo90}, // Inst #2457 = FRINTNv4f32 + {2, OperandInfo90}, // Inst #2458 = FRINTNv8f16 + {2, OperandInfo91}, // Inst #2459 = FRINTPDr + {2, OperandInfo212}, // Inst #2460 = FRINTPHr + {2, OperandInfo213}, // Inst #2461 = FRINTPSr + {4, OperandInfo89}, // Inst #2462 = FRINTP_ZPmZ_D + {4, OperandInfo89}, // Inst #2463 = FRINTP_ZPmZ_H + {4, OperandInfo89}, // Inst #2464 = FRINTP_ZPmZ_S + {2, OperandInfo91}, // Inst #2465 = FRINTPv2f32 + {2, OperandInfo90}, // Inst #2466 = FRINTPv2f64 + {2, OperandInfo91}, // Inst #2467 = FRINTPv4f16 + {2, OperandInfo90}, // Inst #2468 = FRINTPv4f32 + {2, OperandInfo90}, // Inst #2469 = FRINTPv8f16 + {2, OperandInfo91}, // Inst #2470 = FRINTXDr + {2, OperandInfo212}, // Inst #2471 = FRINTXHr + {2, OperandInfo213}, // Inst #2472 = FRINTXSr + {4, OperandInfo89}, // Inst #2473 = FRINTX_ZPmZ_D + {4, OperandInfo89}, // Inst #2474 = FRINTX_ZPmZ_H + {4, OperandInfo89}, // Inst #2475 = FRINTX_ZPmZ_S + {2, OperandInfo91}, // Inst #2476 = FRINTXv2f32 + {2, OperandInfo90}, // Inst #2477 = FRINTXv2f64 + {2, OperandInfo91}, // Inst #2478 = FRINTXv4f16 + {2, OperandInfo90}, // Inst #2479 = FRINTXv4f32 + {2, OperandInfo90}, // Inst #2480 = FRINTXv8f16 + {2, OperandInfo91}, // Inst #2481 = FRINTZDr + {2, OperandInfo212}, // Inst #2482 = FRINTZHr + {2, OperandInfo213}, // Inst #2483 = FRINTZSr + {4, OperandInfo89}, // Inst #2484 = FRINTZ_ZPmZ_D + {4, OperandInfo89}, // Inst #2485 = FRINTZ_ZPmZ_H + {4, OperandInfo89}, // Inst #2486 = FRINTZ_ZPmZ_S + {2, OperandInfo91}, // Inst #2487 = FRINTZv2f32 + {2, OperandInfo90}, // Inst #2488 = FRINTZv2f64 + {2, OperandInfo91}, // Inst #2489 = FRINTZv4f16 + {2, OperandInfo90}, // Inst #2490 = FRINTZv4f32 + {2, OperandInfo90}, // Inst #2491 = FRINTZv8f16 + {2, OperandInfo247}, // Inst #2492 = FRSQRTE_ZZ_D + {2, OperandInfo247}, // Inst #2493 = FRSQRTE_ZZ_H + {2, OperandInfo247}, // Inst #2494 = FRSQRTE_ZZ_S + {2, OperandInfo212}, // Inst #2495 = FRSQRTEv1f16 + {2, OperandInfo213}, // Inst #2496 = FRSQRTEv1i32 + {2, OperandInfo91}, // Inst #2497 = FRSQRTEv1i64 + {2, OperandInfo91}, // Inst #2498 = FRSQRTEv2f32 + {2, OperandInfo90}, // Inst #2499 = FRSQRTEv2f64 + {2, OperandInfo91}, // Inst #2500 = FRSQRTEv4f16 + {2, OperandInfo90}, // Inst #2501 = FRSQRTEv4f32 + {2, OperandInfo90}, // Inst #2502 = FRSQRTEv8f16 + {3, OperandInfo210}, // Inst #2503 = FRSQRTS16 + {3, OperandInfo211}, // Inst #2504 = FRSQRTS32 + {3, OperandInfo102}, // Inst #2505 = FRSQRTS64 + {3, OperandInfo96}, // Inst #2506 = FRSQRTS_ZZZ_D + {3, OperandInfo96}, // Inst #2507 = FRSQRTS_ZZZ_H + {3, OperandInfo96}, // Inst #2508 = FRSQRTS_ZZZ_S + {3, OperandInfo102}, // Inst #2509 = FRSQRTSv2f32 + {3, OperandInfo101}, // Inst #2510 = FRSQRTSv2f64 + {3, OperandInfo102}, // Inst #2511 = FRSQRTSv4f16 + {3, OperandInfo101}, // Inst #2512 = FRSQRTSv4f32 + {3, OperandInfo101}, // Inst #2513 = FRSQRTSv8f16 + {4, OperandInfo100}, // Inst #2514 = FSCALE_ZPmZ_D + {4, OperandInfo100}, // Inst #2515 = FSCALE_ZPmZ_H + {4, OperandInfo100}, // Inst #2516 = FSCALE_ZPmZ_S + {2, OperandInfo91}, // Inst #2517 = FSQRTDr + {2, OperandInfo212}, // Inst #2518 = FSQRTHr + {2, OperandInfo213}, // Inst #2519 = FSQRTSr + {4, OperandInfo89}, // Inst #2520 = FSQRT_ZPmZ_D + {4, OperandInfo89}, // Inst #2521 = FSQRT_ZPmZ_H + {4, OperandInfo89}, // Inst #2522 = FSQRT_ZPmZ_S + {2, OperandInfo91}, // Inst #2523 = FSQRTv2f32 + {2, OperandInfo90}, // Inst #2524 = FSQRTv2f64 + {2, OperandInfo91}, // Inst #2525 = FSQRTv4f16 + {2, OperandInfo90}, // Inst #2526 = FSQRTv4f32 + {2, OperandInfo90}, // Inst #2527 = FSQRTv8f16 + {3, OperandInfo102}, // Inst #2528 = FSUBDrr + {3, OperandInfo210}, // Inst #2529 = FSUBHrr + {4, OperandInfo133}, // Inst #2530 = FSUBR_ZPmI_D + {4, OperandInfo133}, // Inst #2531 = FSUBR_ZPmI_H + {4, OperandInfo133}, // Inst #2532 = FSUBR_ZPmI_S + {4, OperandInfo100}, // Inst #2533 = FSUBR_ZPmZ_D + {4, OperandInfo100}, // Inst #2534 = FSUBR_ZPmZ_H + {4, OperandInfo100}, // Inst #2535 = FSUBR_ZPmZ_S + {3, OperandInfo211}, // Inst #2536 = FSUBSrr + {4, OperandInfo133}, // Inst #2537 = FSUB_ZPmI_D + {4, OperandInfo133}, // Inst #2538 = FSUB_ZPmI_H + {4, OperandInfo133}, // Inst #2539 = FSUB_ZPmI_S + {4, OperandInfo100}, // Inst #2540 = FSUB_ZPmZ_D + {4, OperandInfo100}, // Inst #2541 = FSUB_ZPmZ_H + {4, OperandInfo100}, // Inst #2542 = FSUB_ZPmZ_S + {3, OperandInfo96}, // Inst #2543 = FSUB_ZZZ_D + {3, OperandInfo96}, // Inst #2544 = FSUB_ZZZ_H + {3, OperandInfo96}, // Inst #2545 = FSUB_ZZZ_S + {3, OperandInfo102}, // Inst #2546 = FSUBv2f32 + {3, OperandInfo101}, // Inst #2547 = FSUBv2f64 + {3, OperandInfo102}, // Inst #2548 = FSUBv4f16 + {3, OperandInfo101}, // Inst #2549 = FSUBv4f32 + {3, OperandInfo101}, // Inst #2550 = FSUBv8f16 + {4, OperandInfo153}, // Inst #2551 = FTMAD_ZZI_D + {4, OperandInfo153}, // Inst #2552 = FTMAD_ZZI_H + {4, OperandInfo153}, // Inst #2553 = FTMAD_ZZI_S + {3, OperandInfo96}, // Inst #2554 = FTSMUL_ZZZ_D + {3, OperandInfo96}, // Inst #2555 = FTSMUL_ZZZ_H + {3, OperandInfo96}, // Inst #2556 = FTSMUL_ZZZ_S + {3, OperandInfo96}, // Inst #2557 = FTSSEL_ZZZ_D + {3, OperandInfo96}, // Inst #2558 = FTSSEL_ZZZ_H + {3, OperandInfo96}, // Inst #2559 = FTSSEL_ZZZ_S + {4, OperandInfo50}, // Inst #2560 = GLD1B_D_IMM_REAL + {4, OperandInfo63}, // Inst #2561 = GLD1B_D_REAL + {4, OperandInfo63}, // Inst #2562 = GLD1B_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2563 = GLD1B_D_UXTW_REAL + {4, OperandInfo50}, // Inst #2564 = GLD1B_S_IMM_REAL + {4, OperandInfo63}, // Inst #2565 = GLD1B_S_SXTW_REAL + {4, OperandInfo63}, // Inst #2566 = GLD1B_S_UXTW_REAL + {4, OperandInfo50}, // Inst #2567 = GLD1D_IMM_REAL + {4, OperandInfo63}, // Inst #2568 = GLD1D_REAL + {4, OperandInfo63}, // Inst #2569 = GLD1D_SCALED_REAL + {4, OperandInfo63}, // Inst #2570 = GLD1D_SXTW_REAL + {4, OperandInfo63}, // Inst #2571 = GLD1D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2572 = GLD1D_UXTW_REAL + {4, OperandInfo63}, // Inst #2573 = GLD1D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2574 = GLD1H_D_IMM_REAL + {4, OperandInfo63}, // Inst #2575 = GLD1H_D_REAL + {4, OperandInfo63}, // Inst #2576 = GLD1H_D_SCALED_REAL + {4, OperandInfo63}, // Inst #2577 = GLD1H_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2578 = GLD1H_D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2579 = GLD1H_D_UXTW_REAL + {4, OperandInfo63}, // Inst #2580 = GLD1H_D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2581 = GLD1H_S_IMM_REAL + {4, OperandInfo63}, // Inst #2582 = GLD1H_S_SXTW_REAL + {4, OperandInfo63}, // Inst #2583 = GLD1H_S_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2584 = GLD1H_S_UXTW_REAL + {4, OperandInfo63}, // Inst #2585 = GLD1H_S_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2586 = GLD1SB_D_IMM_REAL + {4, OperandInfo63}, // Inst #2587 = GLD1SB_D_REAL + {4, OperandInfo63}, // Inst #2588 = GLD1SB_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2589 = GLD1SB_D_UXTW_REAL + {4, OperandInfo50}, // Inst #2590 = GLD1SB_S_IMM_REAL + {4, OperandInfo63}, // Inst #2591 = GLD1SB_S_SXTW_REAL + {4, OperandInfo63}, // Inst #2592 = GLD1SB_S_UXTW_REAL + {4, OperandInfo50}, // Inst #2593 = GLD1SH_D_IMM_REAL + {4, OperandInfo63}, // Inst #2594 = GLD1SH_D_REAL + {4, OperandInfo63}, // Inst #2595 = GLD1SH_D_SCALED_REAL + {4, OperandInfo63}, // Inst #2596 = GLD1SH_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2597 = GLD1SH_D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2598 = GLD1SH_D_UXTW_REAL + {4, OperandInfo63}, // Inst #2599 = GLD1SH_D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2600 = GLD1SH_S_IMM_REAL + {4, OperandInfo63}, // Inst #2601 = GLD1SH_S_SXTW_REAL + {4, OperandInfo63}, // Inst #2602 = GLD1SH_S_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2603 = GLD1SH_S_UXTW_REAL + {4, OperandInfo63}, // Inst #2604 = GLD1SH_S_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2605 = GLD1SW_D_IMM_REAL + {4, OperandInfo63}, // Inst #2606 = GLD1SW_D_REAL + {4, OperandInfo63}, // Inst #2607 = GLD1SW_D_SCALED_REAL + {4, OperandInfo63}, // Inst #2608 = GLD1SW_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2609 = GLD1SW_D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2610 = GLD1SW_D_UXTW_REAL + {4, OperandInfo63}, // Inst #2611 = GLD1SW_D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2612 = GLD1W_D_IMM_REAL + {4, OperandInfo63}, // Inst #2613 = GLD1W_D_REAL + {4, OperandInfo63}, // Inst #2614 = GLD1W_D_SCALED_REAL + {4, OperandInfo63}, // Inst #2615 = GLD1W_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2616 = GLD1W_D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2617 = GLD1W_D_UXTW_REAL + {4, OperandInfo63}, // Inst #2618 = GLD1W_D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2619 = GLD1W_IMM_REAL + {4, OperandInfo63}, // Inst #2620 = GLD1W_SXTW_REAL + {4, OperandInfo63}, // Inst #2621 = GLD1W_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2622 = GLD1W_UXTW_REAL + {4, OperandInfo63}, // Inst #2623 = GLD1W_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2624 = GLDFF1B_D_IMM_REAL + {4, OperandInfo63}, // Inst #2625 = GLDFF1B_D_REAL + {4, OperandInfo63}, // Inst #2626 = GLDFF1B_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2627 = GLDFF1B_D_UXTW_REAL + {4, OperandInfo50}, // Inst #2628 = GLDFF1B_S_IMM_REAL + {4, OperandInfo63}, // Inst #2629 = GLDFF1B_S_SXTW_REAL + {4, OperandInfo63}, // Inst #2630 = GLDFF1B_S_UXTW_REAL + {4, OperandInfo50}, // Inst #2631 = GLDFF1D_IMM_REAL + {4, OperandInfo63}, // Inst #2632 = GLDFF1D_REAL + {4, OperandInfo63}, // Inst #2633 = GLDFF1D_SCALED_REAL + {4, OperandInfo63}, // Inst #2634 = GLDFF1D_SXTW_REAL + {4, OperandInfo63}, // Inst #2635 = GLDFF1D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2636 = GLDFF1D_UXTW_REAL + {4, OperandInfo63}, // Inst #2637 = GLDFF1D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2638 = GLDFF1H_D_IMM_REAL + {4, OperandInfo63}, // Inst #2639 = GLDFF1H_D_REAL + {4, OperandInfo63}, // Inst #2640 = GLDFF1H_D_SCALED_REAL + {4, OperandInfo63}, // Inst #2641 = GLDFF1H_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2642 = GLDFF1H_D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2643 = GLDFF1H_D_UXTW_REAL + {4, OperandInfo63}, // Inst #2644 = GLDFF1H_D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2645 = GLDFF1H_S_IMM_REAL + {4, OperandInfo63}, // Inst #2646 = GLDFF1H_S_SXTW_REAL + {4, OperandInfo63}, // Inst #2647 = GLDFF1H_S_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2648 = GLDFF1H_S_UXTW_REAL + {4, OperandInfo63}, // Inst #2649 = GLDFF1H_S_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2650 = GLDFF1SB_D_IMM_REAL + {4, OperandInfo63}, // Inst #2651 = GLDFF1SB_D_REAL + {4, OperandInfo63}, // Inst #2652 = GLDFF1SB_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2653 = GLDFF1SB_D_UXTW_REAL + {4, OperandInfo50}, // Inst #2654 = GLDFF1SB_S_IMM_REAL + {4, OperandInfo63}, // Inst #2655 = GLDFF1SB_S_SXTW_REAL + {4, OperandInfo63}, // Inst #2656 = GLDFF1SB_S_UXTW_REAL + {4, OperandInfo50}, // Inst #2657 = GLDFF1SH_D_IMM_REAL + {4, OperandInfo63}, // Inst #2658 = GLDFF1SH_D_REAL + {4, OperandInfo63}, // Inst #2659 = GLDFF1SH_D_SCALED_REAL + {4, OperandInfo63}, // Inst #2660 = GLDFF1SH_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2661 = GLDFF1SH_D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2662 = GLDFF1SH_D_UXTW_REAL + {4, OperandInfo63}, // Inst #2663 = GLDFF1SH_D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2664 = GLDFF1SH_S_IMM_REAL + {4, OperandInfo63}, // Inst #2665 = GLDFF1SH_S_SXTW_REAL + {4, OperandInfo63}, // Inst #2666 = GLDFF1SH_S_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2667 = GLDFF1SH_S_UXTW_REAL + {4, OperandInfo63}, // Inst #2668 = GLDFF1SH_S_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2669 = GLDFF1SW_D_IMM_REAL + {4, OperandInfo63}, // Inst #2670 = GLDFF1SW_D_REAL + {4, OperandInfo63}, // Inst #2671 = GLDFF1SW_D_SCALED_REAL + {4, OperandInfo63}, // Inst #2672 = GLDFF1SW_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2673 = GLDFF1SW_D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2674 = GLDFF1SW_D_UXTW_REAL + {4, OperandInfo63}, // Inst #2675 = GLDFF1SW_D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2676 = GLDFF1W_D_IMM_REAL + {4, OperandInfo63}, // Inst #2677 = GLDFF1W_D_REAL + {4, OperandInfo63}, // Inst #2678 = GLDFF1W_D_SCALED_REAL + {4, OperandInfo63}, // Inst #2679 = GLDFF1W_D_SXTW_REAL + {4, OperandInfo63}, // Inst #2680 = GLDFF1W_D_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2681 = GLDFF1W_D_UXTW_REAL + {4, OperandInfo63}, // Inst #2682 = GLDFF1W_D_UXTW_SCALED_REAL + {4, OperandInfo50}, // Inst #2683 = GLDFF1W_IMM_REAL + {4, OperandInfo63}, // Inst #2684 = GLDFF1W_SXTW_REAL + {4, OperandInfo63}, // Inst #2685 = GLDFF1W_SXTW_SCALED_REAL + {4, OperandInfo63}, // Inst #2686 = GLDFF1W_UXTW_REAL + {4, OperandInfo63}, // Inst #2687 = GLDFF1W_UXTW_SCALED_REAL + {3, OperandInfo274}, // Inst #2688 = GMI + {1, OperandInfo2}, // Inst #2689 = HINT + {4, OperandInfo47}, // Inst #2690 = HISTCNT_ZPzZZ_D + {4, OperandInfo47}, // Inst #2691 = HISTCNT_ZPzZZ_S + {3, OperandInfo96}, // Inst #2692 = HISTSEG_ZZZ + {1, OperandInfo2}, // Inst #2693 = HLT + {1, OperandInfo2}, // Inst #2694 = HVC + {4, OperandInfo191}, // Inst #2695 = INCB_XPiI + {4, OperandInfo191}, // Inst #2696 = INCD_XPiI + {4, OperandInfo120}, // Inst #2697 = INCD_ZPiI + {4, OperandInfo191}, // Inst #2698 = INCH_XPiI + {4, OperandInfo120}, // Inst #2699 = INCH_ZPiI + {3, OperandInfo192}, // Inst #2700 = INCP_XP_B + {3, OperandInfo192}, // Inst #2701 = INCP_XP_D + {3, OperandInfo192}, // Inst #2702 = INCP_XP_H + {3, OperandInfo192}, // Inst #2703 = INCP_XP_S + {3, OperandInfo193}, // Inst #2704 = INCP_ZP_D + {3, OperandInfo193}, // Inst #2705 = INCP_ZP_H + {3, OperandInfo193}, // Inst #2706 = INCP_ZP_S + {4, OperandInfo191}, // Inst #2707 = INCW_XPiI + {4, OperandInfo120}, // Inst #2708 = INCW_ZPiI + {3, OperandInfo195}, // Inst #2709 = INDEX_II_B + {3, OperandInfo195}, // Inst #2710 = INDEX_II_D + {3, OperandInfo195}, // Inst #2711 = INDEX_II_H + {3, OperandInfo195}, // Inst #2712 = INDEX_II_S + {3, OperandInfo275}, // Inst #2713 = INDEX_IR_B + {3, OperandInfo276}, // Inst #2714 = INDEX_IR_D + {3, OperandInfo275}, // Inst #2715 = INDEX_IR_H + {3, OperandInfo275}, // Inst #2716 = INDEX_IR_S + {3, OperandInfo277}, // Inst #2717 = INDEX_RI_B + {3, OperandInfo278}, // Inst #2718 = INDEX_RI_D + {3, OperandInfo277}, // Inst #2719 = INDEX_RI_H + {3, OperandInfo277}, // Inst #2720 = INDEX_RI_S + {3, OperandInfo279}, // Inst #2721 = INDEX_RR_B + {3, OperandInfo280}, // Inst #2722 = INDEX_RR_D + {3, OperandInfo279}, // Inst #2723 = INDEX_RR_H + {3, OperandInfo279}, // Inst #2724 = INDEX_RR_S + {5, OperandInfo281}, // Inst #2725 = INSERT_MXIPZ_H_B + {5, OperandInfo282}, // Inst #2726 = INSERT_MXIPZ_H_D + {5, OperandInfo283}, // Inst #2727 = INSERT_MXIPZ_H_H + {5, OperandInfo284}, // Inst #2728 = INSERT_MXIPZ_H_Q + {5, OperandInfo285}, // Inst #2729 = INSERT_MXIPZ_H_S + {5, OperandInfo281}, // Inst #2730 = INSERT_MXIPZ_V_B + {5, OperandInfo282}, // Inst #2731 = INSERT_MXIPZ_V_D + {5, OperandInfo283}, // Inst #2732 = INSERT_MXIPZ_V_H + {5, OperandInfo284}, // Inst #2733 = INSERT_MXIPZ_V_Q + {5, OperandInfo285}, // Inst #2734 = INSERT_MXIPZ_V_S + {3, OperandInfo286}, // Inst #2735 = INSR_ZR_B + {3, OperandInfo287}, // Inst #2736 = INSR_ZR_D + {3, OperandInfo286}, // Inst #2737 = INSR_ZR_H + {3, OperandInfo286}, // Inst #2738 = INSR_ZR_S + {3, OperandInfo123}, // Inst #2739 = INSR_ZV_B + {3, OperandInfo123}, // Inst #2740 = INSR_ZV_D + {3, OperandInfo123}, // Inst #2741 = INSR_ZV_H + {3, OperandInfo123}, // Inst #2742 = INSR_ZV_S + {4, OperandInfo288}, // Inst #2743 = INSvi16gpr + {5, OperandInfo289}, // Inst #2744 = INSvi16lane + {4, OperandInfo288}, // Inst #2745 = INSvi32gpr + {5, OperandInfo289}, // Inst #2746 = INSvi32lane + {4, OperandInfo290}, // Inst #2747 = INSvi64gpr + {5, OperandInfo289}, // Inst #2748 = INSvi64lane + {4, OperandInfo288}, // Inst #2749 = INSvi8gpr + {5, OperandInfo289}, // Inst #2750 = INSvi8lane + {3, OperandInfo65}, // Inst #2751 = IRG + {1, OperandInfo2}, // Inst #2752 = ISB + {3, OperandInfo291}, // Inst #2753 = LASTA_RPZ_B + {3, OperandInfo292}, // Inst #2754 = LASTA_RPZ_D + {3, OperandInfo291}, // Inst #2755 = LASTA_RPZ_H + {3, OperandInfo291}, // Inst #2756 = LASTA_RPZ_S + {3, OperandInfo293}, // Inst #2757 = LASTA_VPZ_B + {3, OperandInfo294}, // Inst #2758 = LASTA_VPZ_D + {3, OperandInfo295}, // Inst #2759 = LASTA_VPZ_H + {3, OperandInfo296}, // Inst #2760 = LASTA_VPZ_S + {3, OperandInfo291}, // Inst #2761 = LASTB_RPZ_B + {3, OperandInfo292}, // Inst #2762 = LASTB_RPZ_D + {3, OperandInfo291}, // Inst #2763 = LASTB_RPZ_H + {3, OperandInfo291}, // Inst #2764 = LASTB_RPZ_S + {3, OperandInfo293}, // Inst #2765 = LASTB_VPZ_B + {3, OperandInfo294}, // Inst #2766 = LASTB_VPZ_D + {3, OperandInfo295}, // Inst #2767 = LASTB_VPZ_H + {3, OperandInfo296}, // Inst #2768 = LASTB_VPZ_S + {4, OperandInfo297}, // Inst #2769 = LD1B + {4, OperandInfo297}, // Inst #2770 = LD1B_D + {4, OperandInfo67}, // Inst #2771 = LD1B_D_IMM_REAL + {4, OperandInfo297}, // Inst #2772 = LD1B_H + {4, OperandInfo67}, // Inst #2773 = LD1B_H_IMM_REAL + {4, OperandInfo67}, // Inst #2774 = LD1B_IMM_REAL + {4, OperandInfo297}, // Inst #2775 = LD1B_S + {4, OperandInfo67}, // Inst #2776 = LD1B_S_IMM_REAL + {4, OperandInfo297}, // Inst #2777 = LD1D + {4, OperandInfo67}, // Inst #2778 = LD1D_IMM_REAL + {2, OperandInfo298}, // Inst #2779 = LD1Fourv16b + {4, OperandInfo299}, // Inst #2780 = LD1Fourv16b_POST + {2, OperandInfo300}, // Inst #2781 = LD1Fourv1d + {4, OperandInfo301}, // Inst #2782 = LD1Fourv1d_POST + {2, OperandInfo298}, // Inst #2783 = LD1Fourv2d + {4, OperandInfo299}, // Inst #2784 = LD1Fourv2d_POST + {2, OperandInfo300}, // Inst #2785 = LD1Fourv2s + {4, OperandInfo301}, // Inst #2786 = LD1Fourv2s_POST + {2, OperandInfo300}, // Inst #2787 = LD1Fourv4h + {4, OperandInfo301}, // Inst #2788 = LD1Fourv4h_POST + {2, OperandInfo298}, // Inst #2789 = LD1Fourv4s + {4, OperandInfo299}, // Inst #2790 = LD1Fourv4s_POST + {2, OperandInfo300}, // Inst #2791 = LD1Fourv8b + {4, OperandInfo301}, // Inst #2792 = LD1Fourv8b_POST + {2, OperandInfo298}, // Inst #2793 = LD1Fourv8h + {4, OperandInfo299}, // Inst #2794 = LD1Fourv8h_POST + {4, OperandInfo297}, // Inst #2795 = LD1H + {4, OperandInfo297}, // Inst #2796 = LD1H_D + {4, OperandInfo67}, // Inst #2797 = LD1H_D_IMM_REAL + {4, OperandInfo67}, // Inst #2798 = LD1H_IMM_REAL + {4, OperandInfo297}, // Inst #2799 = LD1H_S + {4, OperandInfo67}, // Inst #2800 = LD1H_S_IMM_REAL + {2, OperandInfo302}, // Inst #2801 = LD1Onev16b + {4, OperandInfo303}, // Inst #2802 = LD1Onev16b_POST + {2, OperandInfo304}, // Inst #2803 = LD1Onev1d + {4, OperandInfo305}, // Inst #2804 = LD1Onev1d_POST + {2, OperandInfo302}, // Inst #2805 = LD1Onev2d + {4, OperandInfo303}, // Inst #2806 = LD1Onev2d_POST + {2, OperandInfo304}, // Inst #2807 = LD1Onev2s + {4, OperandInfo305}, // Inst #2808 = LD1Onev2s_POST + {2, OperandInfo304}, // Inst #2809 = LD1Onev4h + {4, OperandInfo305}, // Inst #2810 = LD1Onev4h_POST + {2, OperandInfo302}, // Inst #2811 = LD1Onev4s + {4, OperandInfo303}, // Inst #2812 = LD1Onev4s_POST + {2, OperandInfo304}, // Inst #2813 = LD1Onev8b + {4, OperandInfo305}, // Inst #2814 = LD1Onev8b_POST + {2, OperandInfo302}, // Inst #2815 = LD1Onev8h + {4, OperandInfo303}, // Inst #2816 = LD1Onev8h_POST + {4, OperandInfo67}, // Inst #2817 = LD1RB_D_IMM + {4, OperandInfo67}, // Inst #2818 = LD1RB_H_IMM + {4, OperandInfo67}, // Inst #2819 = LD1RB_IMM + {4, OperandInfo67}, // Inst #2820 = LD1RB_S_IMM + {4, OperandInfo67}, // Inst #2821 = LD1RD_IMM + {4, OperandInfo67}, // Inst #2822 = LD1RH_D_IMM + {4, OperandInfo67}, // Inst #2823 = LD1RH_IMM + {4, OperandInfo67}, // Inst #2824 = LD1RH_S_IMM + {4, OperandInfo297}, // Inst #2825 = LD1RO_B + {4, OperandInfo67}, // Inst #2826 = LD1RO_B_IMM + {4, OperandInfo297}, // Inst #2827 = LD1RO_D + {4, OperandInfo67}, // Inst #2828 = LD1RO_D_IMM + {4, OperandInfo297}, // Inst #2829 = LD1RO_H + {4, OperandInfo67}, // Inst #2830 = LD1RO_H_IMM + {4, OperandInfo297}, // Inst #2831 = LD1RO_W + {4, OperandInfo67}, // Inst #2832 = LD1RO_W_IMM + {4, OperandInfo297}, // Inst #2833 = LD1RQ_B + {4, OperandInfo67}, // Inst #2834 = LD1RQ_B_IMM + {4, OperandInfo297}, // Inst #2835 = LD1RQ_D + {4, OperandInfo67}, // Inst #2836 = LD1RQ_D_IMM + {4, OperandInfo297}, // Inst #2837 = LD1RQ_H + {4, OperandInfo67}, // Inst #2838 = LD1RQ_H_IMM + {4, OperandInfo297}, // Inst #2839 = LD1RQ_W + {4, OperandInfo67}, // Inst #2840 = LD1RQ_W_IMM + {4, OperandInfo67}, // Inst #2841 = LD1RSB_D_IMM + {4, OperandInfo67}, // Inst #2842 = LD1RSB_H_IMM + {4, OperandInfo67}, // Inst #2843 = LD1RSB_S_IMM + {4, OperandInfo67}, // Inst #2844 = LD1RSH_D_IMM + {4, OperandInfo67}, // Inst #2845 = LD1RSH_S_IMM + {4, OperandInfo67}, // Inst #2846 = LD1RSW_IMM + {4, OperandInfo67}, // Inst #2847 = LD1RW_D_IMM + {4, OperandInfo67}, // Inst #2848 = LD1RW_IMM + {2, OperandInfo302}, // Inst #2849 = LD1Rv16b + {4, OperandInfo303}, // Inst #2850 = LD1Rv16b_POST + {2, OperandInfo304}, // Inst #2851 = LD1Rv1d + {4, OperandInfo305}, // Inst #2852 = LD1Rv1d_POST + {2, OperandInfo302}, // Inst #2853 = LD1Rv2d + {4, OperandInfo303}, // Inst #2854 = LD1Rv2d_POST + {2, OperandInfo304}, // Inst #2855 = LD1Rv2s + {4, OperandInfo305}, // Inst #2856 = LD1Rv2s_POST + {2, OperandInfo304}, // Inst #2857 = LD1Rv4h + {4, OperandInfo305}, // Inst #2858 = LD1Rv4h_POST + {2, OperandInfo302}, // Inst #2859 = LD1Rv4s + {4, OperandInfo303}, // Inst #2860 = LD1Rv4s_POST + {2, OperandInfo304}, // Inst #2861 = LD1Rv8b + {4, OperandInfo305}, // Inst #2862 = LD1Rv8b_POST + {2, OperandInfo302}, // Inst #2863 = LD1Rv8h + {4, OperandInfo303}, // Inst #2864 = LD1Rv8h_POST + {4, OperandInfo297}, // Inst #2865 = LD1SB_D + {4, OperandInfo67}, // Inst #2866 = LD1SB_D_IMM_REAL + {4, OperandInfo297}, // Inst #2867 = LD1SB_H + {4, OperandInfo67}, // Inst #2868 = LD1SB_H_IMM_REAL + {4, OperandInfo297}, // Inst #2869 = LD1SB_S + {4, OperandInfo67}, // Inst #2870 = LD1SB_S_IMM_REAL + {4, OperandInfo297}, // Inst #2871 = LD1SH_D + {4, OperandInfo67}, // Inst #2872 = LD1SH_D_IMM_REAL + {4, OperandInfo297}, // Inst #2873 = LD1SH_S + {4, OperandInfo67}, // Inst #2874 = LD1SH_S_IMM_REAL + {4, OperandInfo297}, // Inst #2875 = LD1SW_D + {4, OperandInfo67}, // Inst #2876 = LD1SW_D_IMM_REAL + {2, OperandInfo306}, // Inst #2877 = LD1Threev16b + {4, OperandInfo307}, // Inst #2878 = LD1Threev16b_POST + {2, OperandInfo308}, // Inst #2879 = LD1Threev1d + {4, OperandInfo309}, // Inst #2880 = LD1Threev1d_POST + {2, OperandInfo306}, // Inst #2881 = LD1Threev2d + {4, OperandInfo307}, // Inst #2882 = LD1Threev2d_POST + {2, OperandInfo308}, // Inst #2883 = LD1Threev2s + {4, OperandInfo309}, // Inst #2884 = LD1Threev2s_POST + {2, OperandInfo308}, // Inst #2885 = LD1Threev4h + {4, OperandInfo309}, // Inst #2886 = LD1Threev4h_POST + {2, OperandInfo306}, // Inst #2887 = LD1Threev4s + {4, OperandInfo307}, // Inst #2888 = LD1Threev4s_POST + {2, OperandInfo308}, // Inst #2889 = LD1Threev8b + {4, OperandInfo309}, // Inst #2890 = LD1Threev8b_POST + {2, OperandInfo306}, // Inst #2891 = LD1Threev8h + {4, OperandInfo307}, // Inst #2892 = LD1Threev8h_POST + {2, OperandInfo310}, // Inst #2893 = LD1Twov16b + {4, OperandInfo311}, // Inst #2894 = LD1Twov16b_POST + {2, OperandInfo312}, // Inst #2895 = LD1Twov1d + {4, OperandInfo313}, // Inst #2896 = LD1Twov1d_POST + {2, OperandInfo310}, // Inst #2897 = LD1Twov2d + {4, OperandInfo311}, // Inst #2898 = LD1Twov2d_POST + {2, OperandInfo312}, // Inst #2899 = LD1Twov2s + {4, OperandInfo313}, // Inst #2900 = LD1Twov2s_POST + {2, OperandInfo312}, // Inst #2901 = LD1Twov4h + {4, OperandInfo313}, // Inst #2902 = LD1Twov4h_POST + {2, OperandInfo310}, // Inst #2903 = LD1Twov4s + {4, OperandInfo311}, // Inst #2904 = LD1Twov4s_POST + {2, OperandInfo312}, // Inst #2905 = LD1Twov8b + {4, OperandInfo313}, // Inst #2906 = LD1Twov8b_POST + {2, OperandInfo310}, // Inst #2907 = LD1Twov8h + {4, OperandInfo311}, // Inst #2908 = LD1Twov8h_POST + {4, OperandInfo297}, // Inst #2909 = LD1W + {4, OperandInfo297}, // Inst #2910 = LD1W_D + {4, OperandInfo67}, // Inst #2911 = LD1W_D_IMM_REAL + {4, OperandInfo67}, // Inst #2912 = LD1W_IMM_REAL + {6, OperandInfo314}, // Inst #2913 = LD1_MXIPXX_H_B + {6, OperandInfo315}, // Inst #2914 = LD1_MXIPXX_H_D + {6, OperandInfo316}, // Inst #2915 = LD1_MXIPXX_H_H + {6, OperandInfo317}, // Inst #2916 = LD1_MXIPXX_H_Q + {6, OperandInfo318}, // Inst #2917 = LD1_MXIPXX_H_S + {6, OperandInfo314}, // Inst #2918 = LD1_MXIPXX_V_B + {6, OperandInfo315}, // Inst #2919 = LD1_MXIPXX_V_D + {6, OperandInfo316}, // Inst #2920 = LD1_MXIPXX_V_H + {6, OperandInfo317}, // Inst #2921 = LD1_MXIPXX_V_Q + {6, OperandInfo318}, // Inst #2922 = LD1_MXIPXX_V_S + {4, OperandInfo319}, // Inst #2923 = LD1i16 + {6, OperandInfo320}, // Inst #2924 = LD1i16_POST + {4, OperandInfo319}, // Inst #2925 = LD1i32 + {6, OperandInfo320}, // Inst #2926 = LD1i32_POST + {4, OperandInfo319}, // Inst #2927 = LD1i64 + {6, OperandInfo320}, // Inst #2928 = LD1i64_POST + {4, OperandInfo319}, // Inst #2929 = LD1i8 + {6, OperandInfo320}, // Inst #2930 = LD1i8_POST + {4, OperandInfo321}, // Inst #2931 = LD2B + {4, OperandInfo322}, // Inst #2932 = LD2B_IMM + {4, OperandInfo321}, // Inst #2933 = LD2D + {4, OperandInfo322}, // Inst #2934 = LD2D_IMM + {4, OperandInfo321}, // Inst #2935 = LD2H + {4, OperandInfo322}, // Inst #2936 = LD2H_IMM + {2, OperandInfo310}, // Inst #2937 = LD2Rv16b + {4, OperandInfo311}, // Inst #2938 = LD2Rv16b_POST + {2, OperandInfo312}, // Inst #2939 = LD2Rv1d + {4, OperandInfo313}, // Inst #2940 = LD2Rv1d_POST + {2, OperandInfo310}, // Inst #2941 = LD2Rv2d + {4, OperandInfo311}, // Inst #2942 = LD2Rv2d_POST + {2, OperandInfo312}, // Inst #2943 = LD2Rv2s + {4, OperandInfo313}, // Inst #2944 = LD2Rv2s_POST + {2, OperandInfo312}, // Inst #2945 = LD2Rv4h + {4, OperandInfo313}, // Inst #2946 = LD2Rv4h_POST + {2, OperandInfo310}, // Inst #2947 = LD2Rv4s + {4, OperandInfo311}, // Inst #2948 = LD2Rv4s_POST + {2, OperandInfo312}, // Inst #2949 = LD2Rv8b + {4, OperandInfo313}, // Inst #2950 = LD2Rv8b_POST + {2, OperandInfo310}, // Inst #2951 = LD2Rv8h + {4, OperandInfo311}, // Inst #2952 = LD2Rv8h_POST + {2, OperandInfo310}, // Inst #2953 = LD2Twov16b + {4, OperandInfo311}, // Inst #2954 = LD2Twov16b_POST + {2, OperandInfo310}, // Inst #2955 = LD2Twov2d + {4, OperandInfo311}, // Inst #2956 = LD2Twov2d_POST + {2, OperandInfo312}, // Inst #2957 = LD2Twov2s + {4, OperandInfo313}, // Inst #2958 = LD2Twov2s_POST + {2, OperandInfo312}, // Inst #2959 = LD2Twov4h + {4, OperandInfo313}, // Inst #2960 = LD2Twov4h_POST + {2, OperandInfo310}, // Inst #2961 = LD2Twov4s + {4, OperandInfo311}, // Inst #2962 = LD2Twov4s_POST + {2, OperandInfo312}, // Inst #2963 = LD2Twov8b + {4, OperandInfo313}, // Inst #2964 = LD2Twov8b_POST + {2, OperandInfo310}, // Inst #2965 = LD2Twov8h + {4, OperandInfo311}, // Inst #2966 = LD2Twov8h_POST + {4, OperandInfo321}, // Inst #2967 = LD2W + {4, OperandInfo322}, // Inst #2968 = LD2W_IMM + {4, OperandInfo323}, // Inst #2969 = LD2i16 + {6, OperandInfo324}, // Inst #2970 = LD2i16_POST + {4, OperandInfo323}, // Inst #2971 = LD2i32 + {6, OperandInfo324}, // Inst #2972 = LD2i32_POST + {4, OperandInfo323}, // Inst #2973 = LD2i64 + {6, OperandInfo324}, // Inst #2974 = LD2i64_POST + {4, OperandInfo323}, // Inst #2975 = LD2i8 + {6, OperandInfo324}, // Inst #2976 = LD2i8_POST + {4, OperandInfo325}, // Inst #2977 = LD3B + {4, OperandInfo326}, // Inst #2978 = LD3B_IMM + {4, OperandInfo325}, // Inst #2979 = LD3D + {4, OperandInfo326}, // Inst #2980 = LD3D_IMM + {4, OperandInfo325}, // Inst #2981 = LD3H + {4, OperandInfo326}, // Inst #2982 = LD3H_IMM + {2, OperandInfo306}, // Inst #2983 = LD3Rv16b + {4, OperandInfo307}, // Inst #2984 = LD3Rv16b_POST + {2, OperandInfo308}, // Inst #2985 = LD3Rv1d + {4, OperandInfo309}, // Inst #2986 = LD3Rv1d_POST + {2, OperandInfo306}, // Inst #2987 = LD3Rv2d + {4, OperandInfo307}, // Inst #2988 = LD3Rv2d_POST + {2, OperandInfo308}, // Inst #2989 = LD3Rv2s + {4, OperandInfo309}, // Inst #2990 = LD3Rv2s_POST + {2, OperandInfo308}, // Inst #2991 = LD3Rv4h + {4, OperandInfo309}, // Inst #2992 = LD3Rv4h_POST + {2, OperandInfo306}, // Inst #2993 = LD3Rv4s + {4, OperandInfo307}, // Inst #2994 = LD3Rv4s_POST + {2, OperandInfo308}, // Inst #2995 = LD3Rv8b + {4, OperandInfo309}, // Inst #2996 = LD3Rv8b_POST + {2, OperandInfo306}, // Inst #2997 = LD3Rv8h + {4, OperandInfo307}, // Inst #2998 = LD3Rv8h_POST + {2, OperandInfo306}, // Inst #2999 = LD3Threev16b + {4, OperandInfo307}, // Inst #3000 = LD3Threev16b_POST + {2, OperandInfo306}, // Inst #3001 = LD3Threev2d + {4, OperandInfo307}, // Inst #3002 = LD3Threev2d_POST + {2, OperandInfo308}, // Inst #3003 = LD3Threev2s + {4, OperandInfo309}, // Inst #3004 = LD3Threev2s_POST + {2, OperandInfo308}, // Inst #3005 = LD3Threev4h + {4, OperandInfo309}, // Inst #3006 = LD3Threev4h_POST + {2, OperandInfo306}, // Inst #3007 = LD3Threev4s + {4, OperandInfo307}, // Inst #3008 = LD3Threev4s_POST + {2, OperandInfo308}, // Inst #3009 = LD3Threev8b + {4, OperandInfo309}, // Inst #3010 = LD3Threev8b_POST + {2, OperandInfo306}, // Inst #3011 = LD3Threev8h + {4, OperandInfo307}, // Inst #3012 = LD3Threev8h_POST + {4, OperandInfo325}, // Inst #3013 = LD3W + {4, OperandInfo326}, // Inst #3014 = LD3W_IMM + {4, OperandInfo327}, // Inst #3015 = LD3i16 + {6, OperandInfo328}, // Inst #3016 = LD3i16_POST + {4, OperandInfo327}, // Inst #3017 = LD3i32 + {6, OperandInfo328}, // Inst #3018 = LD3i32_POST + {4, OperandInfo327}, // Inst #3019 = LD3i64 + {6, OperandInfo328}, // Inst #3020 = LD3i64_POST + {4, OperandInfo327}, // Inst #3021 = LD3i8 + {6, OperandInfo328}, // Inst #3022 = LD3i8_POST + {4, OperandInfo329}, // Inst #3023 = LD4B + {4, OperandInfo330}, // Inst #3024 = LD4B_IMM + {4, OperandInfo329}, // Inst #3025 = LD4D + {4, OperandInfo330}, // Inst #3026 = LD4D_IMM + {2, OperandInfo298}, // Inst #3027 = LD4Fourv16b + {4, OperandInfo299}, // Inst #3028 = LD4Fourv16b_POST + {2, OperandInfo298}, // Inst #3029 = LD4Fourv2d + {4, OperandInfo299}, // Inst #3030 = LD4Fourv2d_POST + {2, OperandInfo300}, // Inst #3031 = LD4Fourv2s + {4, OperandInfo301}, // Inst #3032 = LD4Fourv2s_POST + {2, OperandInfo300}, // Inst #3033 = LD4Fourv4h + {4, OperandInfo301}, // Inst #3034 = LD4Fourv4h_POST + {2, OperandInfo298}, // Inst #3035 = LD4Fourv4s + {4, OperandInfo299}, // Inst #3036 = LD4Fourv4s_POST + {2, OperandInfo300}, // Inst #3037 = LD4Fourv8b + {4, OperandInfo301}, // Inst #3038 = LD4Fourv8b_POST + {2, OperandInfo298}, // Inst #3039 = LD4Fourv8h + {4, OperandInfo299}, // Inst #3040 = LD4Fourv8h_POST + {4, OperandInfo329}, // Inst #3041 = LD4H + {4, OperandInfo330}, // Inst #3042 = LD4H_IMM + {2, OperandInfo298}, // Inst #3043 = LD4Rv16b + {4, OperandInfo299}, // Inst #3044 = LD4Rv16b_POST + {2, OperandInfo300}, // Inst #3045 = LD4Rv1d + {4, OperandInfo301}, // Inst #3046 = LD4Rv1d_POST + {2, OperandInfo298}, // Inst #3047 = LD4Rv2d + {4, OperandInfo299}, // Inst #3048 = LD4Rv2d_POST + {2, OperandInfo300}, // Inst #3049 = LD4Rv2s + {4, OperandInfo301}, // Inst #3050 = LD4Rv2s_POST + {2, OperandInfo300}, // Inst #3051 = LD4Rv4h + {4, OperandInfo301}, // Inst #3052 = LD4Rv4h_POST + {2, OperandInfo298}, // Inst #3053 = LD4Rv4s + {4, OperandInfo299}, // Inst #3054 = LD4Rv4s_POST + {2, OperandInfo300}, // Inst #3055 = LD4Rv8b + {4, OperandInfo301}, // Inst #3056 = LD4Rv8b_POST + {2, OperandInfo298}, // Inst #3057 = LD4Rv8h + {4, OperandInfo299}, // Inst #3058 = LD4Rv8h_POST + {4, OperandInfo329}, // Inst #3059 = LD4W + {4, OperandInfo330}, // Inst #3060 = LD4W_IMM + {4, OperandInfo331}, // Inst #3061 = LD4i16 + {6, OperandInfo332}, // Inst #3062 = LD4i16_POST + {4, OperandInfo331}, // Inst #3063 = LD4i32 + {6, OperandInfo332}, // Inst #3064 = LD4i32_POST + {4, OperandInfo331}, // Inst #3065 = LD4i64 + {6, OperandInfo332}, // Inst #3066 = LD4i64_POST + {4, OperandInfo331}, // Inst #3067 = LD4i8 + {6, OperandInfo332}, // Inst #3068 = LD4i8_POST + {2, OperandInfo333}, // Inst #3069 = LD64B + {3, OperandInfo334}, // Inst #3070 = LDADDAB + {3, OperandInfo334}, // Inst #3071 = LDADDAH + {3, OperandInfo334}, // Inst #3072 = LDADDALB + {3, OperandInfo334}, // Inst #3073 = LDADDALH + {3, OperandInfo334}, // Inst #3074 = LDADDALW + {3, OperandInfo335}, // Inst #3075 = LDADDALX + {3, OperandInfo334}, // Inst #3076 = LDADDAW + {3, OperandInfo335}, // Inst #3077 = LDADDAX + {3, OperandInfo334}, // Inst #3078 = LDADDB + {3, OperandInfo334}, // Inst #3079 = LDADDH + {3, OperandInfo334}, // Inst #3080 = LDADDLB + {3, OperandInfo334}, // Inst #3081 = LDADDLH + {3, OperandInfo334}, // Inst #3082 = LDADDLW + {3, OperandInfo335}, // Inst #3083 = LDADDLX + {3, OperandInfo334}, // Inst #3084 = LDADDW + {3, OperandInfo335}, // Inst #3085 = LDADDX + {2, OperandInfo336}, // Inst #3086 = LDAPRB + {2, OperandInfo336}, // Inst #3087 = LDAPRH + {2, OperandInfo336}, // Inst #3088 = LDAPRW + {2, OperandInfo148}, // Inst #3089 = LDAPRX + {3, OperandInfo337}, // Inst #3090 = LDAPURBi + {3, OperandInfo337}, // Inst #3091 = LDAPURHi + {3, OperandInfo337}, // Inst #3092 = LDAPURSBWi + {3, OperandInfo85}, // Inst #3093 = LDAPURSBXi + {3, OperandInfo337}, // Inst #3094 = LDAPURSHWi + {3, OperandInfo85}, // Inst #3095 = LDAPURSHXi + {3, OperandInfo85}, // Inst #3096 = LDAPURSWi + {3, OperandInfo85}, // Inst #3097 = LDAPURXi + {3, OperandInfo337}, // Inst #3098 = LDAPURi + {2, OperandInfo336}, // Inst #3099 = LDARB + {2, OperandInfo336}, // Inst #3100 = LDARH + {2, OperandInfo336}, // Inst #3101 = LDARW + {2, OperandInfo148}, // Inst #3102 = LDARX + {3, OperandInfo334}, // Inst #3103 = LDAXPW + {3, OperandInfo335}, // Inst #3104 = LDAXPX + {2, OperandInfo336}, // Inst #3105 = LDAXRB + {2, OperandInfo336}, // Inst #3106 = LDAXRH + {2, OperandInfo336}, // Inst #3107 = LDAXRW + {2, OperandInfo148}, // Inst #3108 = LDAXRX + {3, OperandInfo334}, // Inst #3109 = LDCLRAB + {3, OperandInfo334}, // Inst #3110 = LDCLRAH + {3, OperandInfo334}, // Inst #3111 = LDCLRALB + {3, OperandInfo334}, // Inst #3112 = LDCLRALH + {3, OperandInfo334}, // Inst #3113 = LDCLRALW + {3, OperandInfo335}, // Inst #3114 = LDCLRALX + {3, OperandInfo334}, // Inst #3115 = LDCLRAW + {3, OperandInfo335}, // Inst #3116 = LDCLRAX + {3, OperandInfo334}, // Inst #3117 = LDCLRB + {3, OperandInfo334}, // Inst #3118 = LDCLRH + {3, OperandInfo334}, // Inst #3119 = LDCLRLB + {3, OperandInfo334}, // Inst #3120 = LDCLRLH + {3, OperandInfo334}, // Inst #3121 = LDCLRLW + {3, OperandInfo335}, // Inst #3122 = LDCLRLX + {3, OperandInfo334}, // Inst #3123 = LDCLRW + {3, OperandInfo335}, // Inst #3124 = LDCLRX + {3, OperandInfo334}, // Inst #3125 = LDEORAB + {3, OperandInfo334}, // Inst #3126 = LDEORAH + {3, OperandInfo334}, // Inst #3127 = LDEORALB + {3, OperandInfo334}, // Inst #3128 = LDEORALH + {3, OperandInfo334}, // Inst #3129 = LDEORALW + {3, OperandInfo335}, // Inst #3130 = LDEORALX + {3, OperandInfo334}, // Inst #3131 = LDEORAW + {3, OperandInfo335}, // Inst #3132 = LDEORAX + {3, OperandInfo334}, // Inst #3133 = LDEORB + {3, OperandInfo334}, // Inst #3134 = LDEORH + {3, OperandInfo334}, // Inst #3135 = LDEORLB + {3, OperandInfo334}, // Inst #3136 = LDEORLH + {3, OperandInfo334}, // Inst #3137 = LDEORLW + {3, OperandInfo335}, // Inst #3138 = LDEORLX + {3, OperandInfo334}, // Inst #3139 = LDEORW + {3, OperandInfo335}, // Inst #3140 = LDEORX + {4, OperandInfo68}, // Inst #3141 = LDFF1B_D_REAL + {4, OperandInfo68}, // Inst #3142 = LDFF1B_H_REAL + {4, OperandInfo68}, // Inst #3143 = LDFF1B_REAL + {4, OperandInfo68}, // Inst #3144 = LDFF1B_S_REAL + {4, OperandInfo68}, // Inst #3145 = LDFF1D_REAL + {4, OperandInfo68}, // Inst #3146 = LDFF1H_D_REAL + {4, OperandInfo68}, // Inst #3147 = LDFF1H_REAL + {4, OperandInfo68}, // Inst #3148 = LDFF1H_S_REAL + {4, OperandInfo68}, // Inst #3149 = LDFF1SB_D_REAL + {4, OperandInfo68}, // Inst #3150 = LDFF1SB_H_REAL + {4, OperandInfo68}, // Inst #3151 = LDFF1SB_S_REAL + {4, OperandInfo68}, // Inst #3152 = LDFF1SH_D_REAL + {4, OperandInfo68}, // Inst #3153 = LDFF1SH_S_REAL + {4, OperandInfo68}, // Inst #3154 = LDFF1SW_D_REAL + {4, OperandInfo68}, // Inst #3155 = LDFF1W_D_REAL + {4, OperandInfo68}, // Inst #3156 = LDFF1W_REAL + {4, OperandInfo338}, // Inst #3157 = LDG + {2, OperandInfo148}, // Inst #3158 = LDGM + {2, OperandInfo336}, // Inst #3159 = LDLARB + {2, OperandInfo336}, // Inst #3160 = LDLARH + {2, OperandInfo336}, // Inst #3161 = LDLARW + {2, OperandInfo148}, // Inst #3162 = LDLARX + {4, OperandInfo67}, // Inst #3163 = LDNF1B_D_IMM_REAL + {4, OperandInfo67}, // Inst #3164 = LDNF1B_H_IMM_REAL + {4, OperandInfo67}, // Inst #3165 = LDNF1B_IMM_REAL + {4, OperandInfo67}, // Inst #3166 = LDNF1B_S_IMM_REAL + {4, OperandInfo67}, // Inst #3167 = LDNF1D_IMM_REAL + {4, OperandInfo67}, // Inst #3168 = LDNF1H_D_IMM_REAL + {4, OperandInfo67}, // Inst #3169 = LDNF1H_IMM_REAL + {4, OperandInfo67}, // Inst #3170 = LDNF1H_S_IMM_REAL + {4, OperandInfo67}, // Inst #3171 = LDNF1SB_D_IMM_REAL + {4, OperandInfo67}, // Inst #3172 = LDNF1SB_H_IMM_REAL + {4, OperandInfo67}, // Inst #3173 = LDNF1SB_S_IMM_REAL + {4, OperandInfo67}, // Inst #3174 = LDNF1SH_D_IMM_REAL + {4, OperandInfo67}, // Inst #3175 = LDNF1SH_S_IMM_REAL + {4, OperandInfo67}, // Inst #3176 = LDNF1SW_D_IMM_REAL + {4, OperandInfo67}, // Inst #3177 = LDNF1W_D_IMM_REAL + {4, OperandInfo67}, // Inst #3178 = LDNF1W_IMM_REAL + {4, OperandInfo339}, // Inst #3179 = LDNPDi + {4, OperandInfo340}, // Inst #3180 = LDNPQi + {4, OperandInfo341}, // Inst #3181 = LDNPSi + {4, OperandInfo342}, // Inst #3182 = LDNPWi + {4, OperandInfo343}, // Inst #3183 = LDNPXi + {4, OperandInfo67}, // Inst #3184 = LDNT1B_ZRI + {4, OperandInfo297}, // Inst #3185 = LDNT1B_ZRR + {4, OperandInfo344}, // Inst #3186 = LDNT1B_ZZR_D_REAL + {4, OperandInfo344}, // Inst #3187 = LDNT1B_ZZR_S_REAL + {4, OperandInfo67}, // Inst #3188 = LDNT1D_ZRI + {4, OperandInfo297}, // Inst #3189 = LDNT1D_ZRR + {4, OperandInfo344}, // Inst #3190 = LDNT1D_ZZR_D_REAL + {4, OperandInfo67}, // Inst #3191 = LDNT1H_ZRI + {4, OperandInfo297}, // Inst #3192 = LDNT1H_ZRR + {4, OperandInfo344}, // Inst #3193 = LDNT1H_ZZR_D_REAL + {4, OperandInfo344}, // Inst #3194 = LDNT1H_ZZR_S_REAL + {4, OperandInfo344}, // Inst #3195 = LDNT1SB_ZZR_D_REAL + {4, OperandInfo344}, // Inst #3196 = LDNT1SB_ZZR_S_REAL + {4, OperandInfo344}, // Inst #3197 = LDNT1SH_ZZR_D_REAL + {4, OperandInfo344}, // Inst #3198 = LDNT1SH_ZZR_S_REAL + {4, OperandInfo344}, // Inst #3199 = LDNT1SW_ZZR_D_REAL + {4, OperandInfo67}, // Inst #3200 = LDNT1W_ZRI + {4, OperandInfo297}, // Inst #3201 = LDNT1W_ZRR + {4, OperandInfo344}, // Inst #3202 = LDNT1W_ZZR_D_REAL + {4, OperandInfo344}, // Inst #3203 = LDNT1W_ZZR_S_REAL + {4, OperandInfo339}, // Inst #3204 = LDPDi + {5, OperandInfo345}, // Inst #3205 = LDPDpost + {5, OperandInfo345}, // Inst #3206 = LDPDpre + {4, OperandInfo340}, // Inst #3207 = LDPQi + {5, OperandInfo346}, // Inst #3208 = LDPQpost + {5, OperandInfo346}, // Inst #3209 = LDPQpre + {4, OperandInfo343}, // Inst #3210 = LDPSWi + {5, OperandInfo347}, // Inst #3211 = LDPSWpost + {5, OperandInfo347}, // Inst #3212 = LDPSWpre + {4, OperandInfo341}, // Inst #3213 = LDPSi + {5, OperandInfo348}, // Inst #3214 = LDPSpost + {5, OperandInfo348}, // Inst #3215 = LDPSpre + {4, OperandInfo342}, // Inst #3216 = LDPWi + {5, OperandInfo349}, // Inst #3217 = LDPWpost + {5, OperandInfo349}, // Inst #3218 = LDPWpre + {4, OperandInfo343}, // Inst #3219 = LDPXi + {5, OperandInfo347}, // Inst #3220 = LDPXpost + {5, OperandInfo347}, // Inst #3221 = LDPXpre + {3, OperandInfo85}, // Inst #3222 = LDRAAindexed + {4, OperandInfo350}, // Inst #3223 = LDRAAwriteback + {3, OperandInfo85}, // Inst #3224 = LDRABindexed + {4, OperandInfo350}, // Inst #3225 = LDRABwriteback + {4, OperandInfo351}, // Inst #3226 = LDRBBpost + {4, OperandInfo351}, // Inst #3227 = LDRBBpre + {5, OperandInfo352}, // Inst #3228 = LDRBBroW + {5, OperandInfo353}, // Inst #3229 = LDRBBroX + {3, OperandInfo337}, // Inst #3230 = LDRBBui + {4, OperandInfo354}, // Inst #3231 = LDRBpost + {4, OperandInfo354}, // Inst #3232 = LDRBpre + {5, OperandInfo355}, // Inst #3233 = LDRBroW + {5, OperandInfo356}, // Inst #3234 = LDRBroX + {3, OperandInfo357}, // Inst #3235 = LDRBui + {2, OperandInfo358}, // Inst #3236 = LDRDl + {4, OperandInfo359}, // Inst #3237 = LDRDpost + {4, OperandInfo359}, // Inst #3238 = LDRDpre + {5, OperandInfo360}, // Inst #3239 = LDRDroW + {5, OperandInfo361}, // Inst #3240 = LDRDroX + {3, OperandInfo362}, // Inst #3241 = LDRDui + {4, OperandInfo351}, // Inst #3242 = LDRHHpost + {4, OperandInfo351}, // Inst #3243 = LDRHHpre + {5, OperandInfo352}, // Inst #3244 = LDRHHroW + {5, OperandInfo353}, // Inst #3245 = LDRHHroX + {3, OperandInfo337}, // Inst #3246 = LDRHHui + {4, OperandInfo363}, // Inst #3247 = LDRHpost + {4, OperandInfo363}, // Inst #3248 = LDRHpre + {5, OperandInfo364}, // Inst #3249 = LDRHroW + {5, OperandInfo365}, // Inst #3250 = LDRHroX + {3, OperandInfo366}, // Inst #3251 = LDRHui + {2, OperandInfo367}, // Inst #3252 = LDRQl + {4, OperandInfo368}, // Inst #3253 = LDRQpost + {4, OperandInfo368}, // Inst #3254 = LDRQpre + {5, OperandInfo369}, // Inst #3255 = LDRQroW + {5, OperandInfo370}, // Inst #3256 = LDRQroX + {3, OperandInfo371}, // Inst #3257 = LDRQui + {4, OperandInfo351}, // Inst #3258 = LDRSBWpost + {4, OperandInfo351}, // Inst #3259 = LDRSBWpre + {5, OperandInfo352}, // Inst #3260 = LDRSBWroW + {5, OperandInfo353}, // Inst #3261 = LDRSBWroX + {3, OperandInfo337}, // Inst #3262 = LDRSBWui + {4, OperandInfo350}, // Inst #3263 = LDRSBXpost + {4, OperandInfo350}, // Inst #3264 = LDRSBXpre + {5, OperandInfo372}, // Inst #3265 = LDRSBXroW + {5, OperandInfo373}, // Inst #3266 = LDRSBXroX + {3, OperandInfo85}, // Inst #3267 = LDRSBXui + {4, OperandInfo351}, // Inst #3268 = LDRSHWpost + {4, OperandInfo351}, // Inst #3269 = LDRSHWpre + {5, OperandInfo352}, // Inst #3270 = LDRSHWroW + {5, OperandInfo353}, // Inst #3271 = LDRSHWroX + {3, OperandInfo337}, // Inst #3272 = LDRSHWui + {4, OperandInfo350}, // Inst #3273 = LDRSHXpost + {4, OperandInfo350}, // Inst #3274 = LDRSHXpre + {5, OperandInfo372}, // Inst #3275 = LDRSHXroW + {5, OperandInfo373}, // Inst #3276 = LDRSHXroX + {3, OperandInfo85}, // Inst #3277 = LDRSHXui + {2, OperandInfo122}, // Inst #3278 = LDRSWl + {4, OperandInfo350}, // Inst #3279 = LDRSWpost + {4, OperandInfo350}, // Inst #3280 = LDRSWpre + {5, OperandInfo372}, // Inst #3281 = LDRSWroW + {5, OperandInfo373}, // Inst #3282 = LDRSWroX + {3, OperandInfo85}, // Inst #3283 = LDRSWui + {2, OperandInfo374}, // Inst #3284 = LDRSl + {4, OperandInfo375}, // Inst #3285 = LDRSpost + {4, OperandInfo375}, // Inst #3286 = LDRSpre + {5, OperandInfo376}, // Inst #3287 = LDRSroW + {5, OperandInfo377}, // Inst #3288 = LDRSroX + {3, OperandInfo378}, // Inst #3289 = LDRSui + {2, OperandInfo158}, // Inst #3290 = LDRWl + {4, OperandInfo351}, // Inst #3291 = LDRWpost + {4, OperandInfo351}, // Inst #3292 = LDRWpre + {5, OperandInfo352}, // Inst #3293 = LDRWroW + {5, OperandInfo353}, // Inst #3294 = LDRWroX + {3, OperandInfo337}, // Inst #3295 = LDRWui + {2, OperandInfo122}, // Inst #3296 = LDRXl + {4, OperandInfo350}, // Inst #3297 = LDRXpost + {4, OperandInfo350}, // Inst #3298 = LDRXpre + {5, OperandInfo372}, // Inst #3299 = LDRXroW + {5, OperandInfo373}, // Inst #3300 = LDRXroX + {3, OperandInfo85}, // Inst #3301 = LDRXui + {3, OperandInfo379}, // Inst #3302 = LDR_PXI + {5, OperandInfo380}, // Inst #3303 = LDR_ZA + {3, OperandInfo381}, // Inst #3304 = LDR_ZXI + {3, OperandInfo334}, // Inst #3305 = LDSETAB + {3, OperandInfo334}, // Inst #3306 = LDSETAH + {3, OperandInfo334}, // Inst #3307 = LDSETALB + {3, OperandInfo334}, // Inst #3308 = LDSETALH + {3, OperandInfo334}, // Inst #3309 = LDSETALW + {3, OperandInfo335}, // Inst #3310 = LDSETALX + {3, OperandInfo334}, // Inst #3311 = LDSETAW + {3, OperandInfo335}, // Inst #3312 = LDSETAX + {3, OperandInfo334}, // Inst #3313 = LDSETB + {3, OperandInfo334}, // Inst #3314 = LDSETH + {3, OperandInfo334}, // Inst #3315 = LDSETLB + {3, OperandInfo334}, // Inst #3316 = LDSETLH + {3, OperandInfo334}, // Inst #3317 = LDSETLW + {3, OperandInfo335}, // Inst #3318 = LDSETLX + {3, OperandInfo334}, // Inst #3319 = LDSETW + {3, OperandInfo335}, // Inst #3320 = LDSETX + {3, OperandInfo334}, // Inst #3321 = LDSMAXAB + {3, OperandInfo334}, // Inst #3322 = LDSMAXAH + {3, OperandInfo334}, // Inst #3323 = LDSMAXALB + {3, OperandInfo334}, // Inst #3324 = LDSMAXALH + {3, OperandInfo334}, // Inst #3325 = LDSMAXALW + {3, OperandInfo335}, // Inst #3326 = LDSMAXALX + {3, OperandInfo334}, // Inst #3327 = LDSMAXAW + {3, OperandInfo335}, // Inst #3328 = LDSMAXAX + {3, OperandInfo334}, // Inst #3329 = LDSMAXB + {3, OperandInfo334}, // Inst #3330 = LDSMAXH + {3, OperandInfo334}, // Inst #3331 = LDSMAXLB + {3, OperandInfo334}, // Inst #3332 = LDSMAXLH + {3, OperandInfo334}, // Inst #3333 = LDSMAXLW + {3, OperandInfo335}, // Inst #3334 = LDSMAXLX + {3, OperandInfo334}, // Inst #3335 = LDSMAXW + {3, OperandInfo335}, // Inst #3336 = LDSMAXX + {3, OperandInfo334}, // Inst #3337 = LDSMINAB + {3, OperandInfo334}, // Inst #3338 = LDSMINAH + {3, OperandInfo334}, // Inst #3339 = LDSMINALB + {3, OperandInfo334}, // Inst #3340 = LDSMINALH + {3, OperandInfo334}, // Inst #3341 = LDSMINALW + {3, OperandInfo335}, // Inst #3342 = LDSMINALX + {3, OperandInfo334}, // Inst #3343 = LDSMINAW + {3, OperandInfo335}, // Inst #3344 = LDSMINAX + {3, OperandInfo334}, // Inst #3345 = LDSMINB + {3, OperandInfo334}, // Inst #3346 = LDSMINH + {3, OperandInfo334}, // Inst #3347 = LDSMINLB + {3, OperandInfo334}, // Inst #3348 = LDSMINLH + {3, OperandInfo334}, // Inst #3349 = LDSMINLW + {3, OperandInfo335}, // Inst #3350 = LDSMINLX + {3, OperandInfo334}, // Inst #3351 = LDSMINW + {3, OperandInfo335}, // Inst #3352 = LDSMINX + {3, OperandInfo337}, // Inst #3353 = LDTRBi + {3, OperandInfo337}, // Inst #3354 = LDTRHi + {3, OperandInfo337}, // Inst #3355 = LDTRSBWi + {3, OperandInfo85}, // Inst #3356 = LDTRSBXi + {3, OperandInfo337}, // Inst #3357 = LDTRSHWi + {3, OperandInfo85}, // Inst #3358 = LDTRSHXi + {3, OperandInfo85}, // Inst #3359 = LDTRSWi + {3, OperandInfo337}, // Inst #3360 = LDTRWi + {3, OperandInfo85}, // Inst #3361 = LDTRXi + {3, OperandInfo334}, // Inst #3362 = LDUMAXAB + {3, OperandInfo334}, // Inst #3363 = LDUMAXAH + {3, OperandInfo334}, // Inst #3364 = LDUMAXALB + {3, OperandInfo334}, // Inst #3365 = LDUMAXALH + {3, OperandInfo334}, // Inst #3366 = LDUMAXALW + {3, OperandInfo335}, // Inst #3367 = LDUMAXALX + {3, OperandInfo334}, // Inst #3368 = LDUMAXAW + {3, OperandInfo335}, // Inst #3369 = LDUMAXAX + {3, OperandInfo334}, // Inst #3370 = LDUMAXB + {3, OperandInfo334}, // Inst #3371 = LDUMAXH + {3, OperandInfo334}, // Inst #3372 = LDUMAXLB + {3, OperandInfo334}, // Inst #3373 = LDUMAXLH + {3, OperandInfo334}, // Inst #3374 = LDUMAXLW + {3, OperandInfo335}, // Inst #3375 = LDUMAXLX + {3, OperandInfo334}, // Inst #3376 = LDUMAXW + {3, OperandInfo335}, // Inst #3377 = LDUMAXX + {3, OperandInfo334}, // Inst #3378 = LDUMINAB + {3, OperandInfo334}, // Inst #3379 = LDUMINAH + {3, OperandInfo334}, // Inst #3380 = LDUMINALB + {3, OperandInfo334}, // Inst #3381 = LDUMINALH + {3, OperandInfo334}, // Inst #3382 = LDUMINALW + {3, OperandInfo335}, // Inst #3383 = LDUMINALX + {3, OperandInfo334}, // Inst #3384 = LDUMINAW + {3, OperandInfo335}, // Inst #3385 = LDUMINAX + {3, OperandInfo334}, // Inst #3386 = LDUMINB + {3, OperandInfo334}, // Inst #3387 = LDUMINH + {3, OperandInfo334}, // Inst #3388 = LDUMINLB + {3, OperandInfo334}, // Inst #3389 = LDUMINLH + {3, OperandInfo334}, // Inst #3390 = LDUMINLW + {3, OperandInfo335}, // Inst #3391 = LDUMINLX + {3, OperandInfo334}, // Inst #3392 = LDUMINW + {3, OperandInfo335}, // Inst #3393 = LDUMINX + {3, OperandInfo337}, // Inst #3394 = LDURBBi + {3, OperandInfo357}, // Inst #3395 = LDURBi + {3, OperandInfo362}, // Inst #3396 = LDURDi + {3, OperandInfo337}, // Inst #3397 = LDURHHi + {3, OperandInfo366}, // Inst #3398 = LDURHi + {3, OperandInfo371}, // Inst #3399 = LDURQi + {3, OperandInfo337}, // Inst #3400 = LDURSBWi + {3, OperandInfo85}, // Inst #3401 = LDURSBXi + {3, OperandInfo337}, // Inst #3402 = LDURSHWi + {3, OperandInfo85}, // Inst #3403 = LDURSHXi + {3, OperandInfo85}, // Inst #3404 = LDURSWi + {3, OperandInfo378}, // Inst #3405 = LDURSi + {3, OperandInfo337}, // Inst #3406 = LDURWi + {3, OperandInfo85}, // Inst #3407 = LDURXi + {3, OperandInfo334}, // Inst #3408 = LDXPW + {3, OperandInfo335}, // Inst #3409 = LDXPX + {2, OperandInfo336}, // Inst #3410 = LDXRB + {2, OperandInfo336}, // Inst #3411 = LDXRH + {2, OperandInfo336}, // Inst #3412 = LDXRW + {2, OperandInfo148}, // Inst #3413 = LDXRX + {4, OperandInfo100}, // Inst #3414 = LSLR_ZPmZ_B + {4, OperandInfo100}, // Inst #3415 = LSLR_ZPmZ_D + {4, OperandInfo100}, // Inst #3416 = LSLR_ZPmZ_H + {4, OperandInfo100}, // Inst #3417 = LSLR_ZPmZ_S + {3, OperandInfo45}, // Inst #3418 = LSLVWr + {3, OperandInfo46}, // Inst #3419 = LSLVXr + {4, OperandInfo100}, // Inst #3420 = LSL_WIDE_ZPmZ_B + {4, OperandInfo100}, // Inst #3421 = LSL_WIDE_ZPmZ_H + {4, OperandInfo100}, // Inst #3422 = LSL_WIDE_ZPmZ_S + {3, OperandInfo96}, // Inst #3423 = LSL_WIDE_ZZZ_B + {3, OperandInfo96}, // Inst #3424 = LSL_WIDE_ZZZ_H + {3, OperandInfo96}, // Inst #3425 = LSL_WIDE_ZZZ_S + {4, OperandInfo133}, // Inst #3426 = LSL_ZPmI_B + {4, OperandInfo133}, // Inst #3427 = LSL_ZPmI_D + {4, OperandInfo133}, // Inst #3428 = LSL_ZPmI_H + {4, OperandInfo133}, // Inst #3429 = LSL_ZPmI_S + {4, OperandInfo100}, // Inst #3430 = LSL_ZPmZ_B + {4, OperandInfo100}, // Inst #3431 = LSL_ZPmZ_D + {4, OperandInfo100}, // Inst #3432 = LSL_ZPmZ_H + {4, OperandInfo100}, // Inst #3433 = LSL_ZPmZ_S + {3, OperandInfo134}, // Inst #3434 = LSL_ZZI_B + {3, OperandInfo134}, // Inst #3435 = LSL_ZZI_D + {3, OperandInfo134}, // Inst #3436 = LSL_ZZI_H + {3, OperandInfo134}, // Inst #3437 = LSL_ZZI_S + {4, OperandInfo100}, // Inst #3438 = LSRR_ZPmZ_B + {4, OperandInfo100}, // Inst #3439 = LSRR_ZPmZ_D + {4, OperandInfo100}, // Inst #3440 = LSRR_ZPmZ_H + {4, OperandInfo100}, // Inst #3441 = LSRR_ZPmZ_S + {3, OperandInfo45}, // Inst #3442 = LSRVWr + {3, OperandInfo46}, // Inst #3443 = LSRVXr + {4, OperandInfo100}, // Inst #3444 = LSR_WIDE_ZPmZ_B + {4, OperandInfo100}, // Inst #3445 = LSR_WIDE_ZPmZ_H + {4, OperandInfo100}, // Inst #3446 = LSR_WIDE_ZPmZ_S + {3, OperandInfo96}, // Inst #3447 = LSR_WIDE_ZZZ_B + {3, OperandInfo96}, // Inst #3448 = LSR_WIDE_ZZZ_H + {3, OperandInfo96}, // Inst #3449 = LSR_WIDE_ZZZ_S + {4, OperandInfo133}, // Inst #3450 = LSR_ZPmI_B + {4, OperandInfo133}, // Inst #3451 = LSR_ZPmI_D + {4, OperandInfo133}, // Inst #3452 = LSR_ZPmI_H + {4, OperandInfo133}, // Inst #3453 = LSR_ZPmI_S + {4, OperandInfo100}, // Inst #3454 = LSR_ZPmZ_B + {4, OperandInfo100}, // Inst #3455 = LSR_ZPmZ_D + {4, OperandInfo100}, // Inst #3456 = LSR_ZPmZ_H + {4, OperandInfo100}, // Inst #3457 = LSR_ZPmZ_S + {3, OperandInfo134}, // Inst #3458 = LSR_ZZI_B + {3, OperandInfo134}, // Inst #3459 = LSR_ZZI_D + {3, OperandInfo134}, // Inst #3460 = LSR_ZZI_H + {3, OperandInfo134}, // Inst #3461 = LSR_ZZI_S + {4, OperandInfo382}, // Inst #3462 = MADDWrrr + {4, OperandInfo383}, // Inst #3463 = MADDXrrr + {5, OperandInfo250}, // Inst #3464 = MAD_ZPmZZ_B + {5, OperandInfo250}, // Inst #3465 = MAD_ZPmZZ_D + {5, OperandInfo250}, // Inst #3466 = MAD_ZPmZZ_H + {5, OperandInfo250}, // Inst #3467 = MAD_ZPmZZ_S + {4, OperandInfo173}, // Inst #3468 = MATCH_PPzZZ_B + {4, OperandInfo173}, // Inst #3469 = MATCH_PPzZZ_H + {5, OperandInfo250}, // Inst #3470 = MLA_ZPmZZ_B + {5, OperandInfo250}, // Inst #3471 = MLA_ZPmZZ_D + {5, OperandInfo250}, // Inst #3472 = MLA_ZPmZZ_H + {5, OperandInfo250}, // Inst #3473 = MLA_ZPmZZ_S + {5, OperandInfo251}, // Inst #3474 = MLA_ZZZI_D + {5, OperandInfo141}, // Inst #3475 = MLA_ZZZI_H + {5, OperandInfo141}, // Inst #3476 = MLA_ZZZI_S + {4, OperandInfo98}, // Inst #3477 = MLAv16i8 + {4, OperandInfo142}, // Inst #3478 = MLAv2i32 + {5, OperandInfo138}, // Inst #3479 = MLAv2i32_indexed + {4, OperandInfo142}, // Inst #3480 = MLAv4i16 + {5, OperandInfo254}, // Inst #3481 = MLAv4i16_indexed + {4, OperandInfo98}, // Inst #3482 = MLAv4i32 + {5, OperandInfo139}, // Inst #3483 = MLAv4i32_indexed + {4, OperandInfo98}, // Inst #3484 = MLAv8i16 + {5, OperandInfo143}, // Inst #3485 = MLAv8i16_indexed + {4, OperandInfo142}, // Inst #3486 = MLAv8i8 + {5, OperandInfo250}, // Inst #3487 = MLS_ZPmZZ_B + {5, OperandInfo250}, // Inst #3488 = MLS_ZPmZZ_D + {5, OperandInfo250}, // Inst #3489 = MLS_ZPmZZ_H + {5, OperandInfo250}, // Inst #3490 = MLS_ZPmZZ_S + {5, OperandInfo251}, // Inst #3491 = MLS_ZZZI_D + {5, OperandInfo141}, // Inst #3492 = MLS_ZZZI_H + {5, OperandInfo141}, // Inst #3493 = MLS_ZZZI_S + {4, OperandInfo98}, // Inst #3494 = MLSv16i8 + {4, OperandInfo142}, // Inst #3495 = MLSv2i32 + {5, OperandInfo138}, // Inst #3496 = MLSv2i32_indexed + {4, OperandInfo142}, // Inst #3497 = MLSv4i16 + {5, OperandInfo254}, // Inst #3498 = MLSv4i16_indexed + {4, OperandInfo98}, // Inst #3499 = MLSv4i32 + {5, OperandInfo139}, // Inst #3500 = MLSv4i32_indexed + {4, OperandInfo98}, // Inst #3501 = MLSv8i16 + {5, OperandInfo143}, // Inst #3502 = MLSv8i16_indexed + {4, OperandInfo142}, // Inst #3503 = MLSv8i8 + {2, OperandInfo258}, // Inst #3504 = MOVID + {2, OperandInfo266}, // Inst #3505 = MOVIv16b_ns + {2, OperandInfo266}, // Inst #3506 = MOVIv2d_ns + {3, OperandInfo384}, // Inst #3507 = MOVIv2i32 + {3, OperandInfo384}, // Inst #3508 = MOVIv2s_msl + {3, OperandInfo384}, // Inst #3509 = MOVIv4i16 + {3, OperandInfo385}, // Inst #3510 = MOVIv4i32 + {3, OperandInfo385}, // Inst #3511 = MOVIv4s_msl + {2, OperandInfo258}, // Inst #3512 = MOVIv8b_ns + {3, OperandInfo385}, // Inst #3513 = MOVIv8i16 + {4, OperandInfo386}, // Inst #3514 = MOVKWi + {4, OperandInfo191}, // Inst #3515 = MOVKXi + {3, OperandInfo387}, // Inst #3516 = MOVNWi + {3, OperandInfo174}, // Inst #3517 = MOVNXi + {4, OperandInfo89}, // Inst #3518 = MOVPRFX_ZPmZ_B + {4, OperandInfo89}, // Inst #3519 = MOVPRFX_ZPmZ_D + {4, OperandInfo89}, // Inst #3520 = MOVPRFX_ZPmZ_H + {4, OperandInfo89}, // Inst #3521 = MOVPRFX_ZPmZ_S + {3, OperandInfo129}, // Inst #3522 = MOVPRFX_ZPzZ_B + {3, OperandInfo129}, // Inst #3523 = MOVPRFX_ZPzZ_D + {3, OperandInfo129}, // Inst #3524 = MOVPRFX_ZPzZ_H + {3, OperandInfo129}, // Inst #3525 = MOVPRFX_ZPzZ_S + {2, OperandInfo247}, // Inst #3526 = MOVPRFX_ZZ + {3, OperandInfo387}, // Inst #3527 = MOVZWi + {3, OperandInfo174}, // Inst #3528 = MOVZXi + {2, OperandInfo121}, // Inst #3529 = MRS + {5, OperandInfo250}, // Inst #3530 = MSB_ZPmZZ_B + {5, OperandInfo250}, // Inst #3531 = MSB_ZPmZZ_D + {5, OperandInfo250}, // Inst #3532 = MSB_ZPmZZ_H + {5, OperandInfo250}, // Inst #3533 = MSB_ZPmZZ_S + {2, OperandInfo388}, // Inst #3534 = MSR + {2, OperandInfo7}, // Inst #3535 = MSRpstateImm1 + {2, OperandInfo7}, // Inst #3536 = MSRpstateImm4 + {2, OperandInfo7}, // Inst #3537 = MSRpstatesvcrImm1 + {4, OperandInfo382}, // Inst #3538 = MSUBWrrr + {4, OperandInfo383}, // Inst #3539 = MSUBXrrr + {3, OperandInfo132}, // Inst #3540 = MUL_ZI_B + {3, OperandInfo132}, // Inst #3541 = MUL_ZI_D + {3, OperandInfo132}, // Inst #3542 = MUL_ZI_H + {3, OperandInfo132}, // Inst #3543 = MUL_ZI_S + {4, OperandInfo100}, // Inst #3544 = MUL_ZPmZ_B + {4, OperandInfo100}, // Inst #3545 = MUL_ZPmZ_D + {4, OperandInfo100}, // Inst #3546 = MUL_ZPmZ_H + {4, OperandInfo100}, // Inst #3547 = MUL_ZPmZ_S + {4, OperandInfo272}, // Inst #3548 = MUL_ZZZI_D + {4, OperandInfo273}, // Inst #3549 = MUL_ZZZI_H + {4, OperandInfo273}, // Inst #3550 = MUL_ZZZI_S + {3, OperandInfo96}, // Inst #3551 = MUL_ZZZ_B + {3, OperandInfo96}, // Inst #3552 = MUL_ZZZ_D + {3, OperandInfo96}, // Inst #3553 = MUL_ZZZ_H + {3, OperandInfo96}, // Inst #3554 = MUL_ZZZ_S + {3, OperandInfo101}, // Inst #3555 = MULv16i8 + {3, OperandInfo102}, // Inst #3556 = MULv2i32 + {4, OperandInfo269}, // Inst #3557 = MULv2i32_indexed + {3, OperandInfo102}, // Inst #3558 = MULv4i16 + {4, OperandInfo270}, // Inst #3559 = MULv4i16_indexed + {3, OperandInfo101}, // Inst #3560 = MULv4i32 + {4, OperandInfo58}, // Inst #3561 = MULv4i32_indexed + {3, OperandInfo101}, // Inst #3562 = MULv8i16 + {4, OperandInfo271}, // Inst #3563 = MULv8i16_indexed + {3, OperandInfo102}, // Inst #3564 = MULv8i8 + {3, OperandInfo384}, // Inst #3565 = MVNIv2i32 + {3, OperandInfo384}, // Inst #3566 = MVNIv2s_msl + {3, OperandInfo384}, // Inst #3567 = MVNIv4i16 + {3, OperandInfo385}, // Inst #3568 = MVNIv4i32 + {3, OperandInfo385}, // Inst #3569 = MVNIv4s_msl + {3, OperandInfo385}, // Inst #3570 = MVNIv8i16 + {4, OperandInfo128}, // Inst #3571 = NANDS_PPzPP + {4, OperandInfo128}, // Inst #3572 = NAND_PPzPP + {4, OperandInfo92}, // Inst #3573 = NBSL_ZZZZ + {4, OperandInfo89}, // Inst #3574 = NEG_ZPmZ_B + {4, OperandInfo89}, // Inst #3575 = NEG_ZPmZ_D + {4, OperandInfo89}, // Inst #3576 = NEG_ZPmZ_H + {4, OperandInfo89}, // Inst #3577 = NEG_ZPmZ_S + {2, OperandInfo90}, // Inst #3578 = NEGv16i8 + {2, OperandInfo91}, // Inst #3579 = NEGv1i64 + {2, OperandInfo91}, // Inst #3580 = NEGv2i32 + {2, OperandInfo90}, // Inst #3581 = NEGv2i64 + {2, OperandInfo91}, // Inst #3582 = NEGv4i16 + {2, OperandInfo90}, // Inst #3583 = NEGv4i32 + {2, OperandInfo90}, // Inst #3584 = NEGv8i16 + {2, OperandInfo91}, // Inst #3585 = NEGv8i8 + {4, OperandInfo173}, // Inst #3586 = NMATCH_PPzZZ_B + {4, OperandInfo173}, // Inst #3587 = NMATCH_PPzZZ_H + {4, OperandInfo128}, // Inst #3588 = NORS_PPzPP + {4, OperandInfo128}, // Inst #3589 = NOR_PPzPP + {4, OperandInfo89}, // Inst #3590 = NOT_ZPmZ_B + {4, OperandInfo89}, // Inst #3591 = NOT_ZPmZ_D + {4, OperandInfo89}, // Inst #3592 = NOT_ZPmZ_H + {4, OperandInfo89}, // Inst #3593 = NOT_ZPmZ_S + {2, OperandInfo90}, // Inst #3594 = NOTv16i8 + {2, OperandInfo91}, // Inst #3595 = NOTv8i8 + {4, OperandInfo128}, // Inst #3596 = ORNS_PPzPP + {4, OperandInfo105}, // Inst #3597 = ORNWrs + {4, OperandInfo108}, // Inst #3598 = ORNXrs + {4, OperandInfo128}, // Inst #3599 = ORN_PPzPP + {3, OperandInfo101}, // Inst #3600 = ORNv16i8 + {3, OperandInfo102}, // Inst #3601 = ORNv8i8 + {4, OperandInfo128}, // Inst #3602 = ORRS_PPzPP + {3, OperandInfo130}, // Inst #3603 = ORRWri + {4, OperandInfo105}, // Inst #3604 = ORRWrs + {3, OperandInfo131}, // Inst #3605 = ORRXri + {4, OperandInfo108}, // Inst #3606 = ORRXrs + {4, OperandInfo128}, // Inst #3607 = ORR_PPzPP + {3, OperandInfo132}, // Inst #3608 = ORR_ZI + {4, OperandInfo100}, // Inst #3609 = ORR_ZPmZ_B + {4, OperandInfo100}, // Inst #3610 = ORR_ZPmZ_D + {4, OperandInfo100}, // Inst #3611 = ORR_ZPmZ_H + {4, OperandInfo100}, // Inst #3612 = ORR_ZPmZ_S + {3, OperandInfo96}, // Inst #3613 = ORR_ZZZ + {3, OperandInfo101}, // Inst #3614 = ORRv16i8 + {4, OperandInfo146}, // Inst #3615 = ORRv2i32 + {4, OperandInfo146}, // Inst #3616 = ORRv4i16 + {4, OperandInfo147}, // Inst #3617 = ORRv4i32 + {4, OperandInfo147}, // Inst #3618 = ORRv8i16 + {3, OperandInfo102}, // Inst #3619 = ORRv8i8 + {3, OperandInfo129}, // Inst #3620 = ORV_VPZ_B + {3, OperandInfo129}, // Inst #3621 = ORV_VPZ_D + {3, OperandInfo129}, // Inst #3622 = ORV_VPZ_H + {3, OperandInfo129}, // Inst #3623 = ORV_VPZ_S + {3, OperandInfo135}, // Inst #3624 = PACDA + {3, OperandInfo135}, // Inst #3625 = PACDB + {2, OperandInfo136}, // Inst #3626 = PACDZA + {2, OperandInfo136}, // Inst #3627 = PACDZB + {3, OperandInfo335}, // Inst #3628 = PACGA + {3, OperandInfo135}, // Inst #3629 = PACIA + {0, NULL}, // Inst #3630 = PACIA1716 + {0, NULL}, // Inst #3631 = PACIASP + {0, NULL}, // Inst #3632 = PACIAZ + {3, OperandInfo135}, // Inst #3633 = PACIB + {0, NULL}, // Inst #3634 = PACIB1716 + {0, NULL}, // Inst #3635 = PACIBSP + {0, NULL}, // Inst #3636 = PACIBZ + {2, OperandInfo136}, // Inst #3637 = PACIZA + {2, OperandInfo136}, // Inst #3638 = PACIZB + {1, OperandInfo77}, // Inst #3639 = PFALSE + {3, OperandInfo389}, // Inst #3640 = PFIRST_B + {3, OperandInfo96}, // Inst #3641 = PMULLB_ZZZ_D + {3, OperandInfo96}, // Inst #3642 = PMULLB_ZZZ_H + {3, OperandInfo96}, // Inst #3643 = PMULLB_ZZZ_Q + {3, OperandInfo96}, // Inst #3644 = PMULLT_ZZZ_D + {3, OperandInfo96}, // Inst #3645 = PMULLT_ZZZ_H + {3, OperandInfo96}, // Inst #3646 = PMULLT_ZZZ_Q + {3, OperandInfo101}, // Inst #3647 = PMULLv16i8 + {3, OperandInfo390}, // Inst #3648 = PMULLv1i64 + {3, OperandInfo101}, // Inst #3649 = PMULLv2i64 + {3, OperandInfo390}, // Inst #3650 = PMULLv8i8 + {3, OperandInfo96}, // Inst #3651 = PMUL_ZZZ_B + {3, OperandInfo101}, // Inst #3652 = PMULv16i8 + {3, OperandInfo102}, // Inst #3653 = PMULv8i8 + {3, OperandInfo389}, // Inst #3654 = PNEXT_B + {3, OperandInfo389}, // Inst #3655 = PNEXT_D + {3, OperandInfo389}, // Inst #3656 = PNEXT_H + {3, OperandInfo389}, // Inst #3657 = PNEXT_S + {4, OperandInfo391}, // Inst #3658 = PRFB_D_PZI + {4, OperandInfo392}, // Inst #3659 = PRFB_D_SCALED + {4, OperandInfo392}, // Inst #3660 = PRFB_D_SXTW_SCALED + {4, OperandInfo392}, // Inst #3661 = PRFB_D_UXTW_SCALED + {4, OperandInfo393}, // Inst #3662 = PRFB_PRI + {4, OperandInfo394}, // Inst #3663 = PRFB_PRR + {4, OperandInfo391}, // Inst #3664 = PRFB_S_PZI + {4, OperandInfo392}, // Inst #3665 = PRFB_S_SXTW_SCALED + {4, OperandInfo392}, // Inst #3666 = PRFB_S_UXTW_SCALED + {4, OperandInfo391}, // Inst #3667 = PRFD_D_PZI + {4, OperandInfo392}, // Inst #3668 = PRFD_D_SCALED + {4, OperandInfo392}, // Inst #3669 = PRFD_D_SXTW_SCALED + {4, OperandInfo392}, // Inst #3670 = PRFD_D_UXTW_SCALED + {4, OperandInfo393}, // Inst #3671 = PRFD_PRI + {4, OperandInfo394}, // Inst #3672 = PRFD_PRR + {4, OperandInfo391}, // Inst #3673 = PRFD_S_PZI + {4, OperandInfo392}, // Inst #3674 = PRFD_S_SXTW_SCALED + {4, OperandInfo392}, // Inst #3675 = PRFD_S_UXTW_SCALED + {4, OperandInfo391}, // Inst #3676 = PRFH_D_PZI + {4, OperandInfo392}, // Inst #3677 = PRFH_D_SCALED + {4, OperandInfo392}, // Inst #3678 = PRFH_D_SXTW_SCALED + {4, OperandInfo392}, // Inst #3679 = PRFH_D_UXTW_SCALED + {4, OperandInfo393}, // Inst #3680 = PRFH_PRI + {4, OperandInfo394}, // Inst #3681 = PRFH_PRR + {4, OperandInfo391}, // Inst #3682 = PRFH_S_PZI + {4, OperandInfo392}, // Inst #3683 = PRFH_S_SXTW_SCALED + {4, OperandInfo392}, // Inst #3684 = PRFH_S_UXTW_SCALED + {2, OperandInfo152}, // Inst #3685 = PRFMl + {5, OperandInfo395}, // Inst #3686 = PRFMroW + {5, OperandInfo396}, // Inst #3687 = PRFMroX + {3, OperandInfo397}, // Inst #3688 = PRFMui + {4, OperandInfo394}, // Inst #3689 = PRFS_PRR + {3, OperandInfo397}, // Inst #3690 = PRFUMi + {4, OperandInfo391}, // Inst #3691 = PRFW_D_PZI + {4, OperandInfo392}, // Inst #3692 = PRFW_D_SCALED + {4, OperandInfo392}, // Inst #3693 = PRFW_D_SXTW_SCALED + {4, OperandInfo392}, // Inst #3694 = PRFW_D_UXTW_SCALED + {4, OperandInfo393}, // Inst #3695 = PRFW_PRI + {4, OperandInfo391}, // Inst #3696 = PRFW_S_PZI + {4, OperandInfo392}, // Inst #3697 = PRFW_S_SXTW_SCALED + {4, OperandInfo392}, // Inst #3698 = PRFW_S_UXTW_SCALED + {5, OperandInfo398}, // Inst #3699 = PSEL_PPPRI_B + {5, OperandInfo398}, // Inst #3700 = PSEL_PPPRI_D + {5, OperandInfo398}, // Inst #3701 = PSEL_PPPRI_H + {5, OperandInfo398}, // Inst #3702 = PSEL_PPPRI_S + {2, OperandInfo78}, // Inst #3703 = PTEST_PP + {2, OperandInfo399}, // Inst #3704 = PTRUES_B + {2, OperandInfo399}, // Inst #3705 = PTRUES_D + {2, OperandInfo399}, // Inst #3706 = PTRUES_H + {2, OperandInfo399}, // Inst #3707 = PTRUES_S + {2, OperandInfo399}, // Inst #3708 = PTRUE_B + {2, OperandInfo399}, // Inst #3709 = PTRUE_D + {2, OperandInfo399}, // Inst #3710 = PTRUE_H + {2, OperandInfo399}, // Inst #3711 = PTRUE_S + {2, OperandInfo78}, // Inst #3712 = PUNPKHI_PP + {2, OperandInfo78}, // Inst #3713 = PUNPKLO_PP + {3, OperandInfo96}, // Inst #3714 = RADDHNB_ZZZ_B + {3, OperandInfo96}, // Inst #3715 = RADDHNB_ZZZ_H + {3, OperandInfo96}, // Inst #3716 = RADDHNB_ZZZ_S + {4, OperandInfo92}, // Inst #3717 = RADDHNT_ZZZ_B + {4, OperandInfo92}, // Inst #3718 = RADDHNT_ZZZ_H + {4, OperandInfo92}, // Inst #3719 = RADDHNT_ZZZ_S + {3, OperandInfo97}, // Inst #3720 = RADDHNv2i64_v2i32 + {4, OperandInfo98}, // Inst #3721 = RADDHNv2i64_v4i32 + {3, OperandInfo97}, // Inst #3722 = RADDHNv4i32_v4i16 + {4, OperandInfo98}, // Inst #3723 = RADDHNv4i32_v8i16 + {4, OperandInfo98}, // Inst #3724 = RADDHNv8i16_v16i8 + {3, OperandInfo97}, // Inst #3725 = RADDHNv8i16_v8i8 + {3, OperandInfo101}, // Inst #3726 = RAX1 + {3, OperandInfo96}, // Inst #3727 = RAX1_ZZZ_D + {2, OperandInfo83}, // Inst #3728 = RBITWr + {2, OperandInfo84}, // Inst #3729 = RBITXr + {4, OperandInfo89}, // Inst #3730 = RBIT_ZPmZ_B + {4, OperandInfo89}, // Inst #3731 = RBIT_ZPmZ_D + {4, OperandInfo89}, // Inst #3732 = RBIT_ZPmZ_H + {4, OperandInfo89}, // Inst #3733 = RBIT_ZPmZ_S + {2, OperandInfo90}, // Inst #3734 = RBITv16i8 + {2, OperandInfo91}, // Inst #3735 = RBITv8i8 + {2, OperandInfo78}, // Inst #3736 = RDFFRS_PPz + {2, OperandInfo78}, // Inst #3737 = RDFFR_PPz_REAL + {1, OperandInfo77}, // Inst #3738 = RDFFR_P_REAL + {2, OperandInfo121}, // Inst #3739 = RDVLI_XI + {1, OperandInfo75}, // Inst #3740 = RET + {0, NULL}, // Inst #3741 = RETAA + {0, NULL}, // Inst #3742 = RETAB + {2, OperandInfo83}, // Inst #3743 = REV16Wr + {2, OperandInfo84}, // Inst #3744 = REV16Xr + {2, OperandInfo90}, // Inst #3745 = REV16v16i8 + {2, OperandInfo91}, // Inst #3746 = REV16v8i8 + {2, OperandInfo84}, // Inst #3747 = REV32Xr + {2, OperandInfo90}, // Inst #3748 = REV32v16i8 + {2, OperandInfo91}, // Inst #3749 = REV32v4i16 + {2, OperandInfo90}, // Inst #3750 = REV32v8i16 + {2, OperandInfo91}, // Inst #3751 = REV32v8i8 + {2, OperandInfo90}, // Inst #3752 = REV64v16i8 + {2, OperandInfo91}, // Inst #3753 = REV64v2i32 + {2, OperandInfo91}, // Inst #3754 = REV64v4i16 + {2, OperandInfo90}, // Inst #3755 = REV64v4i32 + {2, OperandInfo90}, // Inst #3756 = REV64v8i16 + {2, OperandInfo91}, // Inst #3757 = REV64v8i8 + {4, OperandInfo89}, // Inst #3758 = REVB_ZPmZ_D + {4, OperandInfo89}, // Inst #3759 = REVB_ZPmZ_H + {4, OperandInfo89}, // Inst #3760 = REVB_ZPmZ_S + {4, OperandInfo89}, // Inst #3761 = REVD_ZPmZ + {4, OperandInfo89}, // Inst #3762 = REVH_ZPmZ_D + {4, OperandInfo89}, // Inst #3763 = REVH_ZPmZ_S + {4, OperandInfo89}, // Inst #3764 = REVW_ZPmZ_D + {2, OperandInfo83}, // Inst #3765 = REVWr + {2, OperandInfo84}, // Inst #3766 = REVXr + {2, OperandInfo78}, // Inst #3767 = REV_PP_B + {2, OperandInfo78}, // Inst #3768 = REV_PP_D + {2, OperandInfo78}, // Inst #3769 = REV_PP_H + {2, OperandInfo78}, // Inst #3770 = REV_PP_S + {2, OperandInfo247}, // Inst #3771 = REV_ZZ_B + {2, OperandInfo247}, // Inst #3772 = REV_ZZ_D + {2, OperandInfo247}, // Inst #3773 = REV_ZZ_H + {2, OperandInfo247}, // Inst #3774 = REV_ZZ_S + {3, OperandInfo174}, // Inst #3775 = RMIF + {3, OperandInfo45}, // Inst #3776 = RORVWr + {3, OperandInfo46}, // Inst #3777 = RORVXr + {3, OperandInfo134}, // Inst #3778 = RSHRNB_ZZI_B + {3, OperandInfo134}, // Inst #3779 = RSHRNB_ZZI_H + {3, OperandInfo134}, // Inst #3780 = RSHRNB_ZZI_S + {4, OperandInfo153}, // Inst #3781 = RSHRNT_ZZI_B + {4, OperandInfo153}, // Inst #3782 = RSHRNT_ZZI_H + {4, OperandInfo153}, // Inst #3783 = RSHRNT_ZZI_S + {4, OperandInfo400}, // Inst #3784 = RSHRNv16i8_shift + {3, OperandInfo186}, // Inst #3785 = RSHRNv2i32_shift + {3, OperandInfo186}, // Inst #3786 = RSHRNv4i16_shift + {4, OperandInfo400}, // Inst #3787 = RSHRNv4i32_shift + {4, OperandInfo400}, // Inst #3788 = RSHRNv8i16_shift + {3, OperandInfo186}, // Inst #3789 = RSHRNv8i8_shift + {3, OperandInfo96}, // Inst #3790 = RSUBHNB_ZZZ_B + {3, OperandInfo96}, // Inst #3791 = RSUBHNB_ZZZ_H + {3, OperandInfo96}, // Inst #3792 = RSUBHNB_ZZZ_S + {4, OperandInfo92}, // Inst #3793 = RSUBHNT_ZZZ_B + {4, OperandInfo92}, // Inst #3794 = RSUBHNT_ZZZ_H + {4, OperandInfo92}, // Inst #3795 = RSUBHNT_ZZZ_S + {3, OperandInfo97}, // Inst #3796 = RSUBHNv2i64_v2i32 + {4, OperandInfo98}, // Inst #3797 = RSUBHNv2i64_v4i32 + {3, OperandInfo97}, // Inst #3798 = RSUBHNv4i32_v4i16 + {4, OperandInfo98}, // Inst #3799 = RSUBHNv4i32_v8i16 + {4, OperandInfo98}, // Inst #3800 = RSUBHNv8i16_v16i8 + {3, OperandInfo97}, // Inst #3801 = RSUBHNv8i16_v8i8 + {4, OperandInfo92}, // Inst #3802 = SABALB_ZZZ_D + {4, OperandInfo92}, // Inst #3803 = SABALB_ZZZ_H + {4, OperandInfo92}, // Inst #3804 = SABALB_ZZZ_S + {4, OperandInfo92}, // Inst #3805 = SABALT_ZZZ_D + {4, OperandInfo92}, // Inst #3806 = SABALT_ZZZ_H + {4, OperandInfo92}, // Inst #3807 = SABALT_ZZZ_S + {4, OperandInfo98}, // Inst #3808 = SABALv16i8_v8i16 + {4, OperandInfo401}, // Inst #3809 = SABALv2i32_v2i64 + {4, OperandInfo401}, // Inst #3810 = SABALv4i16_v4i32 + {4, OperandInfo98}, // Inst #3811 = SABALv4i32_v2i64 + {4, OperandInfo98}, // Inst #3812 = SABALv8i16_v4i32 + {4, OperandInfo401}, // Inst #3813 = SABALv8i8_v8i16 + {4, OperandInfo92}, // Inst #3814 = SABA_ZZZ_B + {4, OperandInfo92}, // Inst #3815 = SABA_ZZZ_D + {4, OperandInfo92}, // Inst #3816 = SABA_ZZZ_H + {4, OperandInfo92}, // Inst #3817 = SABA_ZZZ_S + {4, OperandInfo98}, // Inst #3818 = SABAv16i8 + {4, OperandInfo142}, // Inst #3819 = SABAv2i32 + {4, OperandInfo142}, // Inst #3820 = SABAv4i16 + {4, OperandInfo98}, // Inst #3821 = SABAv4i32 + {4, OperandInfo98}, // Inst #3822 = SABAv8i16 + {4, OperandInfo142}, // Inst #3823 = SABAv8i8 + {3, OperandInfo96}, // Inst #3824 = SABDLB_ZZZ_D + {3, OperandInfo96}, // Inst #3825 = SABDLB_ZZZ_H + {3, OperandInfo96}, // Inst #3826 = SABDLB_ZZZ_S + {3, OperandInfo96}, // Inst #3827 = SABDLT_ZZZ_D + {3, OperandInfo96}, // Inst #3828 = SABDLT_ZZZ_H + {3, OperandInfo96}, // Inst #3829 = SABDLT_ZZZ_S + {3, OperandInfo101}, // Inst #3830 = SABDLv16i8_v8i16 + {3, OperandInfo390}, // Inst #3831 = SABDLv2i32_v2i64 + {3, OperandInfo390}, // Inst #3832 = SABDLv4i16_v4i32 + {3, OperandInfo101}, // Inst #3833 = SABDLv4i32_v2i64 + {3, OperandInfo101}, // Inst #3834 = SABDLv8i16_v4i32 + {3, OperandInfo390}, // Inst #3835 = SABDLv8i8_v8i16 + {4, OperandInfo100}, // Inst #3836 = SABD_ZPmZ_B + {4, OperandInfo100}, // Inst #3837 = SABD_ZPmZ_D + {4, OperandInfo100}, // Inst #3838 = SABD_ZPmZ_H + {4, OperandInfo100}, // Inst #3839 = SABD_ZPmZ_S + {3, OperandInfo101}, // Inst #3840 = SABDv16i8 + {3, OperandInfo102}, // Inst #3841 = SABDv2i32 + {3, OperandInfo102}, // Inst #3842 = SABDv4i16 + {3, OperandInfo101}, // Inst #3843 = SABDv4i32 + {3, OperandInfo101}, // Inst #3844 = SABDv8i16 + {3, OperandInfo102}, // Inst #3845 = SABDv8i8 + {4, OperandInfo100}, // Inst #3846 = SADALP_ZPmZ_D + {4, OperandInfo100}, // Inst #3847 = SADALP_ZPmZ_H + {4, OperandInfo100}, // Inst #3848 = SADALP_ZPmZ_S + {3, OperandInfo124}, // Inst #3849 = SADALPv16i8_v8i16 + {3, OperandInfo402}, // Inst #3850 = SADALPv2i32_v1i64 + {3, OperandInfo402}, // Inst #3851 = SADALPv4i16_v2i32 + {3, OperandInfo124}, // Inst #3852 = SADALPv4i32_v2i64 + {3, OperandInfo124}, // Inst #3853 = SADALPv8i16_v4i32 + {3, OperandInfo402}, // Inst #3854 = SADALPv8i8_v4i16 + {3, OperandInfo96}, // Inst #3855 = SADDLBT_ZZZ_D + {3, OperandInfo96}, // Inst #3856 = SADDLBT_ZZZ_H + {3, OperandInfo96}, // Inst #3857 = SADDLBT_ZZZ_S + {3, OperandInfo96}, // Inst #3858 = SADDLB_ZZZ_D + {3, OperandInfo96}, // Inst #3859 = SADDLB_ZZZ_H + {3, OperandInfo96}, // Inst #3860 = SADDLB_ZZZ_S + {2, OperandInfo90}, // Inst #3861 = SADDLPv16i8_v8i16 + {2, OperandInfo91}, // Inst #3862 = SADDLPv2i32_v1i64 + {2, OperandInfo91}, // Inst #3863 = SADDLPv4i16_v2i32 + {2, OperandInfo90}, // Inst #3864 = SADDLPv4i32_v2i64 + {2, OperandInfo90}, // Inst #3865 = SADDLPv8i16_v4i32 + {2, OperandInfo91}, // Inst #3866 = SADDLPv8i8_v4i16 + {3, OperandInfo96}, // Inst #3867 = SADDLT_ZZZ_D + {3, OperandInfo96}, // Inst #3868 = SADDLT_ZZZ_H + {3, OperandInfo96}, // Inst #3869 = SADDLT_ZZZ_S + {2, OperandInfo114}, // Inst #3870 = SADDLVv16i8v + {2, OperandInfo214}, // Inst #3871 = SADDLVv4i16v + {2, OperandInfo103}, // Inst #3872 = SADDLVv4i32v + {2, OperandInfo113}, // Inst #3873 = SADDLVv8i16v + {2, OperandInfo112}, // Inst #3874 = SADDLVv8i8v + {3, OperandInfo101}, // Inst #3875 = SADDLv16i8_v8i16 + {3, OperandInfo390}, // Inst #3876 = SADDLv2i32_v2i64 + {3, OperandInfo390}, // Inst #3877 = SADDLv4i16_v4i32 + {3, OperandInfo101}, // Inst #3878 = SADDLv4i32_v2i64 + {3, OperandInfo101}, // Inst #3879 = SADDLv8i16_v4i32 + {3, OperandInfo390}, // Inst #3880 = SADDLv8i8_v8i16 + {3, OperandInfo129}, // Inst #3881 = SADDV_VPZ_B + {3, OperandInfo129}, // Inst #3882 = SADDV_VPZ_H + {3, OperandInfo129}, // Inst #3883 = SADDV_VPZ_S + {3, OperandInfo96}, // Inst #3884 = SADDWB_ZZZ_D + {3, OperandInfo96}, // Inst #3885 = SADDWB_ZZZ_H + {3, OperandInfo96}, // Inst #3886 = SADDWB_ZZZ_S + {3, OperandInfo96}, // Inst #3887 = SADDWT_ZZZ_D + {3, OperandInfo96}, // Inst #3888 = SADDWT_ZZZ_H + {3, OperandInfo96}, // Inst #3889 = SADDWT_ZZZ_S + {3, OperandInfo101}, // Inst #3890 = SADDWv16i8_v8i16 + {3, OperandInfo403}, // Inst #3891 = SADDWv2i32_v2i64 + {3, OperandInfo403}, // Inst #3892 = SADDWv4i16_v4i32 + {3, OperandInfo101}, // Inst #3893 = SADDWv4i32_v2i64 + {3, OperandInfo101}, // Inst #3894 = SADDWv8i16_v4i32 + {3, OperandInfo403}, // Inst #3895 = SADDWv8i8_v8i16 + {0, NULL}, // Inst #3896 = SB + {4, OperandInfo92}, // Inst #3897 = SBCLB_ZZZ_D + {4, OperandInfo92}, // Inst #3898 = SBCLB_ZZZ_S + {4, OperandInfo92}, // Inst #3899 = SBCLT_ZZZ_D + {4, OperandInfo92}, // Inst #3900 = SBCLT_ZZZ_S + {3, OperandInfo45}, // Inst #3901 = SBCSWr + {3, OperandInfo46}, // Inst #3902 = SBCSXr + {3, OperandInfo45}, // Inst #3903 = SBCWr + {3, OperandInfo46}, // Inst #3904 = SBCXr + {4, OperandInfo160}, // Inst #3905 = SBFMWri + {4, OperandInfo162}, // Inst #3906 = SBFMXri + {4, OperandInfo404}, // Inst #3907 = SCLAMP_ZZZ_B + {4, OperandInfo404}, // Inst #3908 = SCLAMP_ZZZ_D + {4, OperandInfo404}, // Inst #3909 = SCLAMP_ZZZ_H + {4, OperandInfo404}, // Inst #3910 = SCLAMP_ZZZ_S + {3, OperandInfo405}, // Inst #3911 = SCVTFSWDri + {3, OperandInfo406}, // Inst #3912 = SCVTFSWHri + {3, OperandInfo407}, // Inst #3913 = SCVTFSWSri + {3, OperandInfo408}, // Inst #3914 = SCVTFSXDri + {3, OperandInfo409}, // Inst #3915 = SCVTFSXHri + {3, OperandInfo410}, // Inst #3916 = SCVTFSXSri + {2, OperandInfo200}, // Inst #3917 = SCVTFUWDri + {2, OperandInfo261}, // Inst #3918 = SCVTFUWHri + {2, OperandInfo262}, // Inst #3919 = SCVTFUWSri + {2, OperandInfo264}, // Inst #3920 = SCVTFUXDri + {2, OperandInfo265}, // Inst #3921 = SCVTFUXHri + {2, OperandInfo411}, // Inst #3922 = SCVTFUXSri + {4, OperandInfo89}, // Inst #3923 = SCVTF_ZPmZ_DtoD + {4, OperandInfo89}, // Inst #3924 = SCVTF_ZPmZ_DtoH + {4, OperandInfo89}, // Inst #3925 = SCVTF_ZPmZ_DtoS + {4, OperandInfo89}, // Inst #3926 = SCVTF_ZPmZ_HtoH + {4, OperandInfo89}, // Inst #3927 = SCVTF_ZPmZ_StoD + {4, OperandInfo89}, // Inst #3928 = SCVTF_ZPmZ_StoH + {4, OperandInfo89}, // Inst #3929 = SCVTF_ZPmZ_StoS + {3, OperandInfo244}, // Inst #3930 = SCVTFd + {3, OperandInfo245}, // Inst #3931 = SCVTFh + {3, OperandInfo246}, // Inst #3932 = SCVTFs + {2, OperandInfo212}, // Inst #3933 = SCVTFv1i16 + {2, OperandInfo213}, // Inst #3934 = SCVTFv1i32 + {2, OperandInfo91}, // Inst #3935 = SCVTFv1i64 + {2, OperandInfo91}, // Inst #3936 = SCVTFv2f32 + {2, OperandInfo90}, // Inst #3937 = SCVTFv2f64 + {3, OperandInfo244}, // Inst #3938 = SCVTFv2i32_shift + {3, OperandInfo199}, // Inst #3939 = SCVTFv2i64_shift + {2, OperandInfo91}, // Inst #3940 = SCVTFv4f16 + {2, OperandInfo90}, // Inst #3941 = SCVTFv4f32 + {3, OperandInfo244}, // Inst #3942 = SCVTFv4i16_shift + {3, OperandInfo199}, // Inst #3943 = SCVTFv4i32_shift + {2, OperandInfo90}, // Inst #3944 = SCVTFv8f16 + {3, OperandInfo199}, // Inst #3945 = SCVTFv8i16_shift + {4, OperandInfo100}, // Inst #3946 = SDIVR_ZPmZ_D + {4, OperandInfo100}, // Inst #3947 = SDIVR_ZPmZ_S + {3, OperandInfo45}, // Inst #3948 = SDIVWr + {3, OperandInfo46}, // Inst #3949 = SDIVXr + {4, OperandInfo100}, // Inst #3950 = SDIV_ZPmZ_D + {4, OperandInfo100}, // Inst #3951 = SDIV_ZPmZ_S + {5, OperandInfo251}, // Inst #3952 = SDOT_ZZZI_D + {5, OperandInfo141}, // Inst #3953 = SDOT_ZZZI_S + {4, OperandInfo92}, // Inst #3954 = SDOT_ZZZ_D + {4, OperandInfo92}, // Inst #3955 = SDOT_ZZZ_S + {5, OperandInfo139}, // Inst #3956 = SDOTlanev16i8 + {5, OperandInfo138}, // Inst #3957 = SDOTlanev8i8 + {4, OperandInfo98}, // Inst #3958 = SDOTv16i8 + {4, OperandInfo142}, // Inst #3959 = SDOTv8i8 + {4, OperandInfo128}, // Inst #3960 = SEL_PPPP + {4, OperandInfo412}, // Inst #3961 = SEL_ZPZZ_B + {4, OperandInfo412}, // Inst #3962 = SEL_ZPZZ_D + {4, OperandInfo412}, // Inst #3963 = SEL_ZPZZ_H + {4, OperandInfo412}, // Inst #3964 = SEL_ZPZZ_S + {1, OperandInfo413}, // Inst #3965 = SETF16 + {1, OperandInfo413}, // Inst #3966 = SETF8 + {0, NULL}, // Inst #3967 = SETFFR + {4, OperandInfo414}, // Inst #3968 = SHA1Crrr + {2, OperandInfo213}, // Inst #3969 = SHA1Hrr + {4, OperandInfo414}, // Inst #3970 = SHA1Mrrr + {4, OperandInfo414}, // Inst #3971 = SHA1Prrr + {4, OperandInfo98}, // Inst #3972 = SHA1SU0rrr + {3, OperandInfo124}, // Inst #3973 = SHA1SU1rr + {4, OperandInfo98}, // Inst #3974 = SHA256H2rrr + {4, OperandInfo98}, // Inst #3975 = SHA256Hrrr + {3, OperandInfo124}, // Inst #3976 = SHA256SU0rr + {4, OperandInfo98}, // Inst #3977 = SHA256SU1rrr + {4, OperandInfo98}, // Inst #3978 = SHA512H + {4, OperandInfo98}, // Inst #3979 = SHA512H2 + {3, OperandInfo124}, // Inst #3980 = SHA512SU0 + {4, OperandInfo98}, // Inst #3981 = SHA512SU1 + {4, OperandInfo100}, // Inst #3982 = SHADD_ZPmZ_B + {4, OperandInfo100}, // Inst #3983 = SHADD_ZPmZ_D + {4, OperandInfo100}, // Inst #3984 = SHADD_ZPmZ_H + {4, OperandInfo100}, // Inst #3985 = SHADD_ZPmZ_S + {3, OperandInfo101}, // Inst #3986 = SHADDv16i8 + {3, OperandInfo102}, // Inst #3987 = SHADDv2i32 + {3, OperandInfo102}, // Inst #3988 = SHADDv4i16 + {3, OperandInfo101}, // Inst #3989 = SHADDv4i32 + {3, OperandInfo101}, // Inst #3990 = SHADDv8i16 + {3, OperandInfo102}, // Inst #3991 = SHADDv8i8 + {2, OperandInfo90}, // Inst #3992 = SHLLv16i8 + {2, OperandInfo236}, // Inst #3993 = SHLLv2i32 + {2, OperandInfo236}, // Inst #3994 = SHLLv4i16 + {2, OperandInfo90}, // Inst #3995 = SHLLv4i32 + {2, OperandInfo90}, // Inst #3996 = SHLLv8i16 + {2, OperandInfo236}, // Inst #3997 = SHLLv8i8 + {3, OperandInfo244}, // Inst #3998 = SHLd + {3, OperandInfo199}, // Inst #3999 = SHLv16i8_shift + {3, OperandInfo244}, // Inst #4000 = SHLv2i32_shift + {3, OperandInfo199}, // Inst #4001 = SHLv2i64_shift + {3, OperandInfo244}, // Inst #4002 = SHLv4i16_shift + {3, OperandInfo199}, // Inst #4003 = SHLv4i32_shift + {3, OperandInfo199}, // Inst #4004 = SHLv8i16_shift + {3, OperandInfo244}, // Inst #4005 = SHLv8i8_shift + {3, OperandInfo134}, // Inst #4006 = SHRNB_ZZI_B + {3, OperandInfo134}, // Inst #4007 = SHRNB_ZZI_H + {3, OperandInfo134}, // Inst #4008 = SHRNB_ZZI_S + {4, OperandInfo153}, // Inst #4009 = SHRNT_ZZI_B + {4, OperandInfo153}, // Inst #4010 = SHRNT_ZZI_H + {4, OperandInfo153}, // Inst #4011 = SHRNT_ZZI_S + {4, OperandInfo400}, // Inst #4012 = SHRNv16i8_shift + {3, OperandInfo186}, // Inst #4013 = SHRNv2i32_shift + {3, OperandInfo186}, // Inst #4014 = SHRNv4i16_shift + {4, OperandInfo400}, // Inst #4015 = SHRNv4i32_shift + {4, OperandInfo400}, // Inst #4016 = SHRNv8i16_shift + {3, OperandInfo186}, // Inst #4017 = SHRNv8i8_shift + {4, OperandInfo100}, // Inst #4018 = SHSUBR_ZPmZ_B + {4, OperandInfo100}, // Inst #4019 = SHSUBR_ZPmZ_D + {4, OperandInfo100}, // Inst #4020 = SHSUBR_ZPmZ_H + {4, OperandInfo100}, // Inst #4021 = SHSUBR_ZPmZ_S + {4, OperandInfo100}, // Inst #4022 = SHSUB_ZPmZ_B + {4, OperandInfo100}, // Inst #4023 = SHSUB_ZPmZ_D + {4, OperandInfo100}, // Inst #4024 = SHSUB_ZPmZ_H + {4, OperandInfo100}, // Inst #4025 = SHSUB_ZPmZ_S + {3, OperandInfo101}, // Inst #4026 = SHSUBv16i8 + {3, OperandInfo102}, // Inst #4027 = SHSUBv2i32 + {3, OperandInfo102}, // Inst #4028 = SHSUBv4i16 + {3, OperandInfo101}, // Inst #4029 = SHSUBv4i32 + {3, OperandInfo101}, // Inst #4030 = SHSUBv8i16 + {3, OperandInfo102}, // Inst #4031 = SHSUBv8i8 + {4, OperandInfo153}, // Inst #4032 = SLI_ZZI_B + {4, OperandInfo153}, // Inst #4033 = SLI_ZZI_D + {4, OperandInfo153}, // Inst #4034 = SLI_ZZI_H + {4, OperandInfo153}, // Inst #4035 = SLI_ZZI_S + {4, OperandInfo415}, // Inst #4036 = SLId + {4, OperandInfo400}, // Inst #4037 = SLIv16i8_shift + {4, OperandInfo415}, // Inst #4038 = SLIv2i32_shift + {4, OperandInfo400}, // Inst #4039 = SLIv2i64_shift + {4, OperandInfo415}, // Inst #4040 = SLIv4i16_shift + {4, OperandInfo400}, // Inst #4041 = SLIv4i32_shift + {4, OperandInfo400}, // Inst #4042 = SLIv8i16_shift + {4, OperandInfo415}, // Inst #4043 = SLIv8i8_shift + {4, OperandInfo98}, // Inst #4044 = SM3PARTW1 + {4, OperandInfo98}, // Inst #4045 = SM3PARTW2 + {4, OperandInfo52}, // Inst #4046 = SM3SS1 + {5, OperandInfo139}, // Inst #4047 = SM3TT1A + {5, OperandInfo139}, // Inst #4048 = SM3TT1B + {5, OperandInfo139}, // Inst #4049 = SM3TT2A + {5, OperandInfo139}, // Inst #4050 = SM3TT2B + {3, OperandInfo124}, // Inst #4051 = SM4E + {3, OperandInfo96}, // Inst #4052 = SM4EKEY_ZZZ_S + {3, OperandInfo101}, // Inst #4053 = SM4ENCKEY + {3, OperandInfo123}, // Inst #4054 = SM4E_ZZZ_S + {4, OperandInfo416}, // Inst #4055 = SMADDLrrr + {4, OperandInfo100}, // Inst #4056 = SMAXP_ZPmZ_B + {4, OperandInfo100}, // Inst #4057 = SMAXP_ZPmZ_D + {4, OperandInfo100}, // Inst #4058 = SMAXP_ZPmZ_H + {4, OperandInfo100}, // Inst #4059 = SMAXP_ZPmZ_S + {3, OperandInfo101}, // Inst #4060 = SMAXPv16i8 + {3, OperandInfo102}, // Inst #4061 = SMAXPv2i32 + {3, OperandInfo102}, // Inst #4062 = SMAXPv4i16 + {3, OperandInfo101}, // Inst #4063 = SMAXPv4i32 + {3, OperandInfo101}, // Inst #4064 = SMAXPv8i16 + {3, OperandInfo102}, // Inst #4065 = SMAXPv8i8 + {3, OperandInfo129}, // Inst #4066 = SMAXV_VPZ_B + {3, OperandInfo129}, // Inst #4067 = SMAXV_VPZ_D + {3, OperandInfo129}, // Inst #4068 = SMAXV_VPZ_H + {3, OperandInfo129}, // Inst #4069 = SMAXV_VPZ_S + {2, OperandInfo111}, // Inst #4070 = SMAXVv16i8v + {2, OperandInfo112}, // Inst #4071 = SMAXVv4i16v + {2, OperandInfo113}, // Inst #4072 = SMAXVv4i32v + {2, OperandInfo114}, // Inst #4073 = SMAXVv8i16v + {2, OperandInfo115}, // Inst #4074 = SMAXVv8i8v + {3, OperandInfo132}, // Inst #4075 = SMAX_ZI_B + {3, OperandInfo132}, // Inst #4076 = SMAX_ZI_D + {3, OperandInfo132}, // Inst #4077 = SMAX_ZI_H + {3, OperandInfo132}, // Inst #4078 = SMAX_ZI_S + {4, OperandInfo100}, // Inst #4079 = SMAX_ZPmZ_B + {4, OperandInfo100}, // Inst #4080 = SMAX_ZPmZ_D + {4, OperandInfo100}, // Inst #4081 = SMAX_ZPmZ_H + {4, OperandInfo100}, // Inst #4082 = SMAX_ZPmZ_S + {3, OperandInfo101}, // Inst #4083 = SMAXv16i8 + {3, OperandInfo102}, // Inst #4084 = SMAXv2i32 + {3, OperandInfo102}, // Inst #4085 = SMAXv4i16 + {3, OperandInfo101}, // Inst #4086 = SMAXv4i32 + {3, OperandInfo101}, // Inst #4087 = SMAXv8i16 + {3, OperandInfo102}, // Inst #4088 = SMAXv8i8 + {1, OperandInfo2}, // Inst #4089 = SMC + {4, OperandInfo100}, // Inst #4090 = SMINP_ZPmZ_B + {4, OperandInfo100}, // Inst #4091 = SMINP_ZPmZ_D + {4, OperandInfo100}, // Inst #4092 = SMINP_ZPmZ_H + {4, OperandInfo100}, // Inst #4093 = SMINP_ZPmZ_S + {3, OperandInfo101}, // Inst #4094 = SMINPv16i8 + {3, OperandInfo102}, // Inst #4095 = SMINPv2i32 + {3, OperandInfo102}, // Inst #4096 = SMINPv4i16 + {3, OperandInfo101}, // Inst #4097 = SMINPv4i32 + {3, OperandInfo101}, // Inst #4098 = SMINPv8i16 + {3, OperandInfo102}, // Inst #4099 = SMINPv8i8 + {3, OperandInfo129}, // Inst #4100 = SMINV_VPZ_B + {3, OperandInfo129}, // Inst #4101 = SMINV_VPZ_D + {3, OperandInfo129}, // Inst #4102 = SMINV_VPZ_H + {3, OperandInfo129}, // Inst #4103 = SMINV_VPZ_S + {2, OperandInfo111}, // Inst #4104 = SMINVv16i8v + {2, OperandInfo112}, // Inst #4105 = SMINVv4i16v + {2, OperandInfo113}, // Inst #4106 = SMINVv4i32v + {2, OperandInfo114}, // Inst #4107 = SMINVv8i16v + {2, OperandInfo115}, // Inst #4108 = SMINVv8i8v + {3, OperandInfo132}, // Inst #4109 = SMIN_ZI_B + {3, OperandInfo132}, // Inst #4110 = SMIN_ZI_D + {3, OperandInfo132}, // Inst #4111 = SMIN_ZI_H + {3, OperandInfo132}, // Inst #4112 = SMIN_ZI_S + {4, OperandInfo100}, // Inst #4113 = SMIN_ZPmZ_B + {4, OperandInfo100}, // Inst #4114 = SMIN_ZPmZ_D + {4, OperandInfo100}, // Inst #4115 = SMIN_ZPmZ_H + {4, OperandInfo100}, // Inst #4116 = SMIN_ZPmZ_S + {3, OperandInfo101}, // Inst #4117 = SMINv16i8 + {3, OperandInfo102}, // Inst #4118 = SMINv2i32 + {3, OperandInfo102}, // Inst #4119 = SMINv4i16 + {3, OperandInfo101}, // Inst #4120 = SMINv4i32 + {3, OperandInfo101}, // Inst #4121 = SMINv8i16 + {3, OperandInfo102}, // Inst #4122 = SMINv8i8 + {5, OperandInfo251}, // Inst #4123 = SMLALB_ZZZI_D + {5, OperandInfo141}, // Inst #4124 = SMLALB_ZZZI_S + {4, OperandInfo92}, // Inst #4125 = SMLALB_ZZZ_D + {4, OperandInfo92}, // Inst #4126 = SMLALB_ZZZ_H + {4, OperandInfo92}, // Inst #4127 = SMLALB_ZZZ_S + {5, OperandInfo251}, // Inst #4128 = SMLALT_ZZZI_D + {5, OperandInfo141}, // Inst #4129 = SMLALT_ZZZI_S + {4, OperandInfo92}, // Inst #4130 = SMLALT_ZZZ_D + {4, OperandInfo92}, // Inst #4131 = SMLALT_ZZZ_H + {4, OperandInfo92}, // Inst #4132 = SMLALT_ZZZ_S + {4, OperandInfo98}, // Inst #4133 = SMLALv16i8_v8i16 + {5, OperandInfo417}, // Inst #4134 = SMLALv2i32_indexed + {4, OperandInfo401}, // Inst #4135 = SMLALv2i32_v2i64 + {5, OperandInfo418}, // Inst #4136 = SMLALv4i16_indexed + {4, OperandInfo401}, // Inst #4137 = SMLALv4i16_v4i32 + {5, OperandInfo139}, // Inst #4138 = SMLALv4i32_indexed + {4, OperandInfo98}, // Inst #4139 = SMLALv4i32_v2i64 + {5, OperandInfo143}, // Inst #4140 = SMLALv8i16_indexed + {4, OperandInfo98}, // Inst #4141 = SMLALv8i16_v4i32 + {4, OperandInfo401}, // Inst #4142 = SMLALv8i8_v8i16 + {5, OperandInfo251}, // Inst #4143 = SMLSLB_ZZZI_D + {5, OperandInfo141}, // Inst #4144 = SMLSLB_ZZZI_S + {4, OperandInfo92}, // Inst #4145 = SMLSLB_ZZZ_D + {4, OperandInfo92}, // Inst #4146 = SMLSLB_ZZZ_H + {4, OperandInfo92}, // Inst #4147 = SMLSLB_ZZZ_S + {5, OperandInfo251}, // Inst #4148 = SMLSLT_ZZZI_D + {5, OperandInfo141}, // Inst #4149 = SMLSLT_ZZZI_S + {4, OperandInfo92}, // Inst #4150 = SMLSLT_ZZZ_D + {4, OperandInfo92}, // Inst #4151 = SMLSLT_ZZZ_H + {4, OperandInfo92}, // Inst #4152 = SMLSLT_ZZZ_S + {4, OperandInfo98}, // Inst #4153 = SMLSLv16i8_v8i16 + {5, OperandInfo417}, // Inst #4154 = SMLSLv2i32_indexed + {4, OperandInfo401}, // Inst #4155 = SMLSLv2i32_v2i64 + {5, OperandInfo418}, // Inst #4156 = SMLSLv4i16_indexed + {4, OperandInfo401}, // Inst #4157 = SMLSLv4i16_v4i32 + {5, OperandInfo139}, // Inst #4158 = SMLSLv4i32_indexed + {4, OperandInfo98}, // Inst #4159 = SMLSLv4i32_v2i64 + {5, OperandInfo143}, // Inst #4160 = SMLSLv8i16_indexed + {4, OperandInfo98}, // Inst #4161 = SMLSLv8i16_v4i32 + {4, OperandInfo401}, // Inst #4162 = SMLSLv8i8_v8i16 + {4, OperandInfo98}, // Inst #4163 = SMMLA + {4, OperandInfo92}, // Inst #4164 = SMMLA_ZZZ + {5, OperandInfo255}, // Inst #4165 = SMOPA_MPPZZ_D + {5, OperandInfo256}, // Inst #4166 = SMOPA_MPPZZ_S + {5, OperandInfo255}, // Inst #4167 = SMOPS_MPPZZ_D + {5, OperandInfo256}, // Inst #4168 = SMOPS_MPPZZ_S + {3, OperandInfo419}, // Inst #4169 = SMOVvi16to32 + {3, OperandInfo419}, // Inst #4170 = SMOVvi16to32_idx0 + {3, OperandInfo257}, // Inst #4171 = SMOVvi16to64 + {3, OperandInfo257}, // Inst #4172 = SMOVvi16to64_idx0 + {3, OperandInfo257}, // Inst #4173 = SMOVvi32to64 + {3, OperandInfo257}, // Inst #4174 = SMOVvi32to64_idx0 + {3, OperandInfo419}, // Inst #4175 = SMOVvi8to32 + {3, OperandInfo419}, // Inst #4176 = SMOVvi8to32_idx0 + {3, OperandInfo257}, // Inst #4177 = SMOVvi8to64 + {3, OperandInfo257}, // Inst #4178 = SMOVvi8to64_idx0 + {4, OperandInfo416}, // Inst #4179 = SMSUBLrrr + {4, OperandInfo100}, // Inst #4180 = SMULH_ZPmZ_B + {4, OperandInfo100}, // Inst #4181 = SMULH_ZPmZ_D + {4, OperandInfo100}, // Inst #4182 = SMULH_ZPmZ_H + {4, OperandInfo100}, // Inst #4183 = SMULH_ZPmZ_S + {3, OperandInfo96}, // Inst #4184 = SMULH_ZZZ_B + {3, OperandInfo96}, // Inst #4185 = SMULH_ZZZ_D + {3, OperandInfo96}, // Inst #4186 = SMULH_ZZZ_H + {3, OperandInfo96}, // Inst #4187 = SMULH_ZZZ_S + {3, OperandInfo46}, // Inst #4188 = SMULHrr + {4, OperandInfo272}, // Inst #4189 = SMULLB_ZZZI_D + {4, OperandInfo273}, // Inst #4190 = SMULLB_ZZZI_S + {3, OperandInfo96}, // Inst #4191 = SMULLB_ZZZ_D + {3, OperandInfo96}, // Inst #4192 = SMULLB_ZZZ_H + {3, OperandInfo96}, // Inst #4193 = SMULLB_ZZZ_S + {4, OperandInfo272}, // Inst #4194 = SMULLT_ZZZI_D + {4, OperandInfo273}, // Inst #4195 = SMULLT_ZZZI_S + {3, OperandInfo96}, // Inst #4196 = SMULLT_ZZZ_D + {3, OperandInfo96}, // Inst #4197 = SMULLT_ZZZ_H + {3, OperandInfo96}, // Inst #4198 = SMULLT_ZZZ_S + {3, OperandInfo101}, // Inst #4199 = SMULLv16i8_v8i16 + {4, OperandInfo420}, // Inst #4200 = SMULLv2i32_indexed + {3, OperandInfo390}, // Inst #4201 = SMULLv2i32_v2i64 + {4, OperandInfo421}, // Inst #4202 = SMULLv4i16_indexed + {3, OperandInfo390}, // Inst #4203 = SMULLv4i16_v4i32 + {4, OperandInfo58}, // Inst #4204 = SMULLv4i32_indexed + {3, OperandInfo101}, // Inst #4205 = SMULLv4i32_v2i64 + {4, OperandInfo271}, // Inst #4206 = SMULLv8i16_indexed + {3, OperandInfo101}, // Inst #4207 = SMULLv8i16_v4i32 + {3, OperandInfo390}, // Inst #4208 = SMULLv8i8_v8i16 + {3, OperandInfo422}, // Inst #4209 = SPLICE_ZPZZ_B + {3, OperandInfo422}, // Inst #4210 = SPLICE_ZPZZ_D + {3, OperandInfo422}, // Inst #4211 = SPLICE_ZPZZ_H + {3, OperandInfo422}, // Inst #4212 = SPLICE_ZPZZ_S + {4, OperandInfo100}, // Inst #4213 = SPLICE_ZPZ_B + {4, OperandInfo100}, // Inst #4214 = SPLICE_ZPZ_D + {4, OperandInfo100}, // Inst #4215 = SPLICE_ZPZ_H + {4, OperandInfo100}, // Inst #4216 = SPLICE_ZPZ_S + {4, OperandInfo89}, // Inst #4217 = SQABS_ZPmZ_B + {4, OperandInfo89}, // Inst #4218 = SQABS_ZPmZ_D + {4, OperandInfo89}, // Inst #4219 = SQABS_ZPmZ_H + {4, OperandInfo89}, // Inst #4220 = SQABS_ZPmZ_S + {2, OperandInfo90}, // Inst #4221 = SQABSv16i8 + {2, OperandInfo212}, // Inst #4222 = SQABSv1i16 + {2, OperandInfo213}, // Inst #4223 = SQABSv1i32 + {2, OperandInfo91}, // Inst #4224 = SQABSv1i64 + {2, OperandInfo423}, // Inst #4225 = SQABSv1i8 + {2, OperandInfo91}, // Inst #4226 = SQABSv2i32 + {2, OperandInfo90}, // Inst #4227 = SQABSv2i64 + {2, OperandInfo91}, // Inst #4228 = SQABSv4i16 + {2, OperandInfo90}, // Inst #4229 = SQABSv4i32 + {2, OperandInfo90}, // Inst #4230 = SQABSv8i16 + {2, OperandInfo91}, // Inst #4231 = SQABSv8i8 + {4, OperandInfo120}, // Inst #4232 = SQADD_ZI_B + {4, OperandInfo120}, // Inst #4233 = SQADD_ZI_D + {4, OperandInfo120}, // Inst #4234 = SQADD_ZI_H + {4, OperandInfo120}, // Inst #4235 = SQADD_ZI_S + {4, OperandInfo100}, // Inst #4236 = SQADD_ZPmZ_B + {4, OperandInfo100}, // Inst #4237 = SQADD_ZPmZ_D + {4, OperandInfo100}, // Inst #4238 = SQADD_ZPmZ_H + {4, OperandInfo100}, // Inst #4239 = SQADD_ZPmZ_S + {3, OperandInfo96}, // Inst #4240 = SQADD_ZZZ_B + {3, OperandInfo96}, // Inst #4241 = SQADD_ZZZ_D + {3, OperandInfo96}, // Inst #4242 = SQADD_ZZZ_H + {3, OperandInfo96}, // Inst #4243 = SQADD_ZZZ_S + {3, OperandInfo101}, // Inst #4244 = SQADDv16i8 + {3, OperandInfo210}, // Inst #4245 = SQADDv1i16 + {3, OperandInfo211}, // Inst #4246 = SQADDv1i32 + {3, OperandInfo102}, // Inst #4247 = SQADDv1i64 + {3, OperandInfo424}, // Inst #4248 = SQADDv1i8 + {3, OperandInfo102}, // Inst #4249 = SQADDv2i32 + {3, OperandInfo101}, // Inst #4250 = SQADDv2i64 + {3, OperandInfo102}, // Inst #4251 = SQADDv4i16 + {3, OperandInfo101}, // Inst #4252 = SQADDv4i32 + {3, OperandInfo101}, // Inst #4253 = SQADDv8i16 + {3, OperandInfo102}, // Inst #4254 = SQADDv8i8 + {4, OperandInfo153}, // Inst #4255 = SQCADD_ZZI_B + {4, OperandInfo153}, // Inst #4256 = SQCADD_ZZI_D + {4, OperandInfo153}, // Inst #4257 = SQCADD_ZZI_H + {4, OperandInfo153}, // Inst #4258 = SQCADD_ZZI_S + {4, OperandInfo191}, // Inst #4259 = SQDECB_XPiI + {4, OperandInfo191}, // Inst #4260 = SQDECB_XPiWdI + {4, OperandInfo191}, // Inst #4261 = SQDECD_XPiI + {4, OperandInfo191}, // Inst #4262 = SQDECD_XPiWdI + {4, OperandInfo120}, // Inst #4263 = SQDECD_ZPiI + {4, OperandInfo191}, // Inst #4264 = SQDECH_XPiI + {4, OperandInfo191}, // Inst #4265 = SQDECH_XPiWdI + {4, OperandInfo120}, // Inst #4266 = SQDECH_ZPiI + {3, OperandInfo192}, // Inst #4267 = SQDECP_XPWd_B + {3, OperandInfo192}, // Inst #4268 = SQDECP_XPWd_D + {3, OperandInfo192}, // Inst #4269 = SQDECP_XPWd_H + {3, OperandInfo192}, // Inst #4270 = SQDECP_XPWd_S + {3, OperandInfo192}, // Inst #4271 = SQDECP_XP_B + {3, OperandInfo192}, // Inst #4272 = SQDECP_XP_D + {3, OperandInfo192}, // Inst #4273 = SQDECP_XP_H + {3, OperandInfo192}, // Inst #4274 = SQDECP_XP_S + {3, OperandInfo193}, // Inst #4275 = SQDECP_ZP_D + {3, OperandInfo193}, // Inst #4276 = SQDECP_ZP_H + {3, OperandInfo193}, // Inst #4277 = SQDECP_ZP_S + {4, OperandInfo191}, // Inst #4278 = SQDECW_XPiI + {4, OperandInfo191}, // Inst #4279 = SQDECW_XPiWdI + {4, OperandInfo120}, // Inst #4280 = SQDECW_ZPiI + {4, OperandInfo92}, // Inst #4281 = SQDMLALBT_ZZZ_D + {4, OperandInfo92}, // Inst #4282 = SQDMLALBT_ZZZ_H + {4, OperandInfo92}, // Inst #4283 = SQDMLALBT_ZZZ_S + {5, OperandInfo251}, // Inst #4284 = SQDMLALB_ZZZI_D + {5, OperandInfo141}, // Inst #4285 = SQDMLALB_ZZZI_S + {4, OperandInfo92}, // Inst #4286 = SQDMLALB_ZZZ_D + {4, OperandInfo92}, // Inst #4287 = SQDMLALB_ZZZ_H + {4, OperandInfo92}, // Inst #4288 = SQDMLALB_ZZZ_S + {5, OperandInfo251}, // Inst #4289 = SQDMLALT_ZZZI_D + {5, OperandInfo141}, // Inst #4290 = SQDMLALT_ZZZI_S + {4, OperandInfo92}, // Inst #4291 = SQDMLALT_ZZZ_D + {4, OperandInfo92}, // Inst #4292 = SQDMLALT_ZZZ_H + {4, OperandInfo92}, // Inst #4293 = SQDMLALT_ZZZ_S + {4, OperandInfo425}, // Inst #4294 = SQDMLALi16 + {4, OperandInfo426}, // Inst #4295 = SQDMLALi32 + {5, OperandInfo427}, // Inst #4296 = SQDMLALv1i32_indexed + {5, OperandInfo428}, // Inst #4297 = SQDMLALv1i64_indexed + {5, OperandInfo417}, // Inst #4298 = SQDMLALv2i32_indexed + {4, OperandInfo401}, // Inst #4299 = SQDMLALv2i32_v2i64 + {5, OperandInfo418}, // Inst #4300 = SQDMLALv4i16_indexed + {4, OperandInfo401}, // Inst #4301 = SQDMLALv4i16_v4i32 + {5, OperandInfo139}, // Inst #4302 = SQDMLALv4i32_indexed + {4, OperandInfo98}, // Inst #4303 = SQDMLALv4i32_v2i64 + {5, OperandInfo143}, // Inst #4304 = SQDMLALv8i16_indexed + {4, OperandInfo98}, // Inst #4305 = SQDMLALv8i16_v4i32 + {4, OperandInfo92}, // Inst #4306 = SQDMLSLBT_ZZZ_D + {4, OperandInfo92}, // Inst #4307 = SQDMLSLBT_ZZZ_H + {4, OperandInfo92}, // Inst #4308 = SQDMLSLBT_ZZZ_S + {5, OperandInfo251}, // Inst #4309 = SQDMLSLB_ZZZI_D + {5, OperandInfo141}, // Inst #4310 = SQDMLSLB_ZZZI_S + {4, OperandInfo92}, // Inst #4311 = SQDMLSLB_ZZZ_D + {4, OperandInfo92}, // Inst #4312 = SQDMLSLB_ZZZ_H + {4, OperandInfo92}, // Inst #4313 = SQDMLSLB_ZZZ_S + {5, OperandInfo251}, // Inst #4314 = SQDMLSLT_ZZZI_D + {5, OperandInfo141}, // Inst #4315 = SQDMLSLT_ZZZI_S + {4, OperandInfo92}, // Inst #4316 = SQDMLSLT_ZZZ_D + {4, OperandInfo92}, // Inst #4317 = SQDMLSLT_ZZZ_H + {4, OperandInfo92}, // Inst #4318 = SQDMLSLT_ZZZ_S + {4, OperandInfo425}, // Inst #4319 = SQDMLSLi16 + {4, OperandInfo426}, // Inst #4320 = SQDMLSLi32 + {5, OperandInfo427}, // Inst #4321 = SQDMLSLv1i32_indexed + {5, OperandInfo428}, // Inst #4322 = SQDMLSLv1i64_indexed + {5, OperandInfo417}, // Inst #4323 = SQDMLSLv2i32_indexed + {4, OperandInfo401}, // Inst #4324 = SQDMLSLv2i32_v2i64 + {5, OperandInfo418}, // Inst #4325 = SQDMLSLv4i16_indexed + {4, OperandInfo401}, // Inst #4326 = SQDMLSLv4i16_v4i32 + {5, OperandInfo139}, // Inst #4327 = SQDMLSLv4i32_indexed + {4, OperandInfo98}, // Inst #4328 = SQDMLSLv4i32_v2i64 + {5, OperandInfo143}, // Inst #4329 = SQDMLSLv8i16_indexed + {4, OperandInfo98}, // Inst #4330 = SQDMLSLv8i16_v4i32 + {4, OperandInfo272}, // Inst #4331 = SQDMULH_ZZZI_D + {4, OperandInfo273}, // Inst #4332 = SQDMULH_ZZZI_H + {4, OperandInfo273}, // Inst #4333 = SQDMULH_ZZZI_S + {3, OperandInfo96}, // Inst #4334 = SQDMULH_ZZZ_B + {3, OperandInfo96}, // Inst #4335 = SQDMULH_ZZZ_D + {3, OperandInfo96}, // Inst #4336 = SQDMULH_ZZZ_H + {3, OperandInfo96}, // Inst #4337 = SQDMULH_ZZZ_S + {3, OperandInfo210}, // Inst #4338 = SQDMULHv1i16 + {4, OperandInfo267}, // Inst #4339 = SQDMULHv1i16_indexed + {3, OperandInfo211}, // Inst #4340 = SQDMULHv1i32 + {4, OperandInfo268}, // Inst #4341 = SQDMULHv1i32_indexed + {3, OperandInfo102}, // Inst #4342 = SQDMULHv2i32 + {4, OperandInfo269}, // Inst #4343 = SQDMULHv2i32_indexed + {3, OperandInfo102}, // Inst #4344 = SQDMULHv4i16 + {4, OperandInfo270}, // Inst #4345 = SQDMULHv4i16_indexed + {3, OperandInfo101}, // Inst #4346 = SQDMULHv4i32 + {4, OperandInfo58}, // Inst #4347 = SQDMULHv4i32_indexed + {3, OperandInfo101}, // Inst #4348 = SQDMULHv8i16 + {4, OperandInfo271}, // Inst #4349 = SQDMULHv8i16_indexed + {4, OperandInfo272}, // Inst #4350 = SQDMULLB_ZZZI_D + {4, OperandInfo273}, // Inst #4351 = SQDMULLB_ZZZI_S + {3, OperandInfo96}, // Inst #4352 = SQDMULLB_ZZZ_D + {3, OperandInfo96}, // Inst #4353 = SQDMULLB_ZZZ_H + {3, OperandInfo96}, // Inst #4354 = SQDMULLB_ZZZ_S + {4, OperandInfo272}, // Inst #4355 = SQDMULLT_ZZZI_D + {4, OperandInfo273}, // Inst #4356 = SQDMULLT_ZZZI_S + {3, OperandInfo96}, // Inst #4357 = SQDMULLT_ZZZ_D + {3, OperandInfo96}, // Inst #4358 = SQDMULLT_ZZZ_H + {3, OperandInfo96}, // Inst #4359 = SQDMULLT_ZZZ_S + {3, OperandInfo429}, // Inst #4360 = SQDMULLi16 + {3, OperandInfo430}, // Inst #4361 = SQDMULLi32 + {4, OperandInfo431}, // Inst #4362 = SQDMULLv1i32_indexed + {4, OperandInfo432}, // Inst #4363 = SQDMULLv1i64_indexed + {4, OperandInfo420}, // Inst #4364 = SQDMULLv2i32_indexed + {3, OperandInfo390}, // Inst #4365 = SQDMULLv2i32_v2i64 + {4, OperandInfo421}, // Inst #4366 = SQDMULLv4i16_indexed + {3, OperandInfo390}, // Inst #4367 = SQDMULLv4i16_v4i32 + {4, OperandInfo58}, // Inst #4368 = SQDMULLv4i32_indexed + {3, OperandInfo101}, // Inst #4369 = SQDMULLv4i32_v2i64 + {4, OperandInfo271}, // Inst #4370 = SQDMULLv8i16_indexed + {3, OperandInfo101}, // Inst #4371 = SQDMULLv8i16_v4i32 + {4, OperandInfo191}, // Inst #4372 = SQINCB_XPiI + {4, OperandInfo191}, // Inst #4373 = SQINCB_XPiWdI + {4, OperandInfo191}, // Inst #4374 = SQINCD_XPiI + {4, OperandInfo191}, // Inst #4375 = SQINCD_XPiWdI + {4, OperandInfo120}, // Inst #4376 = SQINCD_ZPiI + {4, OperandInfo191}, // Inst #4377 = SQINCH_XPiI + {4, OperandInfo191}, // Inst #4378 = SQINCH_XPiWdI + {4, OperandInfo120}, // Inst #4379 = SQINCH_ZPiI + {3, OperandInfo192}, // Inst #4380 = SQINCP_XPWd_B + {3, OperandInfo192}, // Inst #4381 = SQINCP_XPWd_D + {3, OperandInfo192}, // Inst #4382 = SQINCP_XPWd_H + {3, OperandInfo192}, // Inst #4383 = SQINCP_XPWd_S + {3, OperandInfo192}, // Inst #4384 = SQINCP_XP_B + {3, OperandInfo192}, // Inst #4385 = SQINCP_XP_D + {3, OperandInfo192}, // Inst #4386 = SQINCP_XP_H + {3, OperandInfo192}, // Inst #4387 = SQINCP_XP_S + {3, OperandInfo193}, // Inst #4388 = SQINCP_ZP_D + {3, OperandInfo193}, // Inst #4389 = SQINCP_ZP_H + {3, OperandInfo193}, // Inst #4390 = SQINCP_ZP_S + {4, OperandInfo191}, // Inst #4391 = SQINCW_XPiI + {4, OperandInfo191}, // Inst #4392 = SQINCW_XPiWdI + {4, OperandInfo120}, // Inst #4393 = SQINCW_ZPiI + {4, OperandInfo89}, // Inst #4394 = SQNEG_ZPmZ_B + {4, OperandInfo89}, // Inst #4395 = SQNEG_ZPmZ_D + {4, OperandInfo89}, // Inst #4396 = SQNEG_ZPmZ_H + {4, OperandInfo89}, // Inst #4397 = SQNEG_ZPmZ_S + {2, OperandInfo90}, // Inst #4398 = SQNEGv16i8 + {2, OperandInfo212}, // Inst #4399 = SQNEGv1i16 + {2, OperandInfo213}, // Inst #4400 = SQNEGv1i32 + {2, OperandInfo91}, // Inst #4401 = SQNEGv1i64 + {2, OperandInfo423}, // Inst #4402 = SQNEGv1i8 + {2, OperandInfo91}, // Inst #4403 = SQNEGv2i32 + {2, OperandInfo90}, // Inst #4404 = SQNEGv2i64 + {2, OperandInfo91}, // Inst #4405 = SQNEGv4i16 + {2, OperandInfo90}, // Inst #4406 = SQNEGv4i32 + {2, OperandInfo90}, // Inst #4407 = SQNEGv8i16 + {2, OperandInfo91}, // Inst #4408 = SQNEGv8i8 + {6, OperandInfo164}, // Inst #4409 = SQRDCMLAH_ZZZI_H + {6, OperandInfo163}, // Inst #4410 = SQRDCMLAH_ZZZI_S + {5, OperandInfo165}, // Inst #4411 = SQRDCMLAH_ZZZ_B + {5, OperandInfo165}, // Inst #4412 = SQRDCMLAH_ZZZ_D + {5, OperandInfo165}, // Inst #4413 = SQRDCMLAH_ZZZ_H + {5, OperandInfo165}, // Inst #4414 = SQRDCMLAH_ZZZ_S + {5, OperandInfo251}, // Inst #4415 = SQRDMLAH_ZZZI_D + {5, OperandInfo141}, // Inst #4416 = SQRDMLAH_ZZZI_H + {5, OperandInfo141}, // Inst #4417 = SQRDMLAH_ZZZI_S + {4, OperandInfo92}, // Inst #4418 = SQRDMLAH_ZZZ_B + {4, OperandInfo92}, // Inst #4419 = SQRDMLAH_ZZZ_D + {4, OperandInfo92}, // Inst #4420 = SQRDMLAH_ZZZ_H + {4, OperandInfo92}, // Inst #4421 = SQRDMLAH_ZZZ_S + {5, OperandInfo252}, // Inst #4422 = SQRDMLAHi16_indexed + {5, OperandInfo253}, // Inst #4423 = SQRDMLAHi32_indexed + {4, OperandInfo433}, // Inst #4424 = SQRDMLAHv1i16 + {4, OperandInfo434}, // Inst #4425 = SQRDMLAHv1i32 + {4, OperandInfo142}, // Inst #4426 = SQRDMLAHv2i32 + {5, OperandInfo138}, // Inst #4427 = SQRDMLAHv2i32_indexed + {4, OperandInfo142}, // Inst #4428 = SQRDMLAHv4i16 + {5, OperandInfo254}, // Inst #4429 = SQRDMLAHv4i16_indexed + {4, OperandInfo98}, // Inst #4430 = SQRDMLAHv4i32 + {5, OperandInfo139}, // Inst #4431 = SQRDMLAHv4i32_indexed + {4, OperandInfo98}, // Inst #4432 = SQRDMLAHv8i16 + {5, OperandInfo143}, // Inst #4433 = SQRDMLAHv8i16_indexed + {5, OperandInfo251}, // Inst #4434 = SQRDMLSH_ZZZI_D + {5, OperandInfo141}, // Inst #4435 = SQRDMLSH_ZZZI_H + {5, OperandInfo141}, // Inst #4436 = SQRDMLSH_ZZZI_S + {4, OperandInfo92}, // Inst #4437 = SQRDMLSH_ZZZ_B + {4, OperandInfo92}, // Inst #4438 = SQRDMLSH_ZZZ_D + {4, OperandInfo92}, // Inst #4439 = SQRDMLSH_ZZZ_H + {4, OperandInfo92}, // Inst #4440 = SQRDMLSH_ZZZ_S + {5, OperandInfo252}, // Inst #4441 = SQRDMLSHi16_indexed + {5, OperandInfo253}, // Inst #4442 = SQRDMLSHi32_indexed + {4, OperandInfo433}, // Inst #4443 = SQRDMLSHv1i16 + {4, OperandInfo434}, // Inst #4444 = SQRDMLSHv1i32 + {4, OperandInfo142}, // Inst #4445 = SQRDMLSHv2i32 + {5, OperandInfo138}, // Inst #4446 = SQRDMLSHv2i32_indexed + {4, OperandInfo142}, // Inst #4447 = SQRDMLSHv4i16 + {5, OperandInfo254}, // Inst #4448 = SQRDMLSHv4i16_indexed + {4, OperandInfo98}, // Inst #4449 = SQRDMLSHv4i32 + {5, OperandInfo139}, // Inst #4450 = SQRDMLSHv4i32_indexed + {4, OperandInfo98}, // Inst #4451 = SQRDMLSHv8i16 + {5, OperandInfo143}, // Inst #4452 = SQRDMLSHv8i16_indexed + {4, OperandInfo272}, // Inst #4453 = SQRDMULH_ZZZI_D + {4, OperandInfo273}, // Inst #4454 = SQRDMULH_ZZZI_H + {4, OperandInfo273}, // Inst #4455 = SQRDMULH_ZZZI_S + {3, OperandInfo96}, // Inst #4456 = SQRDMULH_ZZZ_B + {3, OperandInfo96}, // Inst #4457 = SQRDMULH_ZZZ_D + {3, OperandInfo96}, // Inst #4458 = SQRDMULH_ZZZ_H + {3, OperandInfo96}, // Inst #4459 = SQRDMULH_ZZZ_S + {3, OperandInfo210}, // Inst #4460 = SQRDMULHv1i16 + {4, OperandInfo267}, // Inst #4461 = SQRDMULHv1i16_indexed + {3, OperandInfo211}, // Inst #4462 = SQRDMULHv1i32 + {4, OperandInfo268}, // Inst #4463 = SQRDMULHv1i32_indexed + {3, OperandInfo102}, // Inst #4464 = SQRDMULHv2i32 + {4, OperandInfo269}, // Inst #4465 = SQRDMULHv2i32_indexed + {3, OperandInfo102}, // Inst #4466 = SQRDMULHv4i16 + {4, OperandInfo270}, // Inst #4467 = SQRDMULHv4i16_indexed + {3, OperandInfo101}, // Inst #4468 = SQRDMULHv4i32 + {4, OperandInfo58}, // Inst #4469 = SQRDMULHv4i32_indexed + {3, OperandInfo101}, // Inst #4470 = SQRDMULHv8i16 + {4, OperandInfo271}, // Inst #4471 = SQRDMULHv8i16_indexed + {4, OperandInfo100}, // Inst #4472 = SQRSHLR_ZPmZ_B + {4, OperandInfo100}, // Inst #4473 = SQRSHLR_ZPmZ_D + {4, OperandInfo100}, // Inst #4474 = SQRSHLR_ZPmZ_H + {4, OperandInfo100}, // Inst #4475 = SQRSHLR_ZPmZ_S + {4, OperandInfo100}, // Inst #4476 = SQRSHL_ZPmZ_B + {4, OperandInfo100}, // Inst #4477 = SQRSHL_ZPmZ_D + {4, OperandInfo100}, // Inst #4478 = SQRSHL_ZPmZ_H + {4, OperandInfo100}, // Inst #4479 = SQRSHL_ZPmZ_S + {3, OperandInfo101}, // Inst #4480 = SQRSHLv16i8 + {3, OperandInfo210}, // Inst #4481 = SQRSHLv1i16 + {3, OperandInfo211}, // Inst #4482 = SQRSHLv1i32 + {3, OperandInfo102}, // Inst #4483 = SQRSHLv1i64 + {3, OperandInfo424}, // Inst #4484 = SQRSHLv1i8 + {3, OperandInfo102}, // Inst #4485 = SQRSHLv2i32 + {3, OperandInfo101}, // Inst #4486 = SQRSHLv2i64 + {3, OperandInfo102}, // Inst #4487 = SQRSHLv4i16 + {3, OperandInfo101}, // Inst #4488 = SQRSHLv4i32 + {3, OperandInfo101}, // Inst #4489 = SQRSHLv8i16 + {3, OperandInfo102}, // Inst #4490 = SQRSHLv8i8 + {3, OperandInfo134}, // Inst #4491 = SQRSHRNB_ZZI_B + {3, OperandInfo134}, // Inst #4492 = SQRSHRNB_ZZI_H + {3, OperandInfo134}, // Inst #4493 = SQRSHRNB_ZZI_S + {4, OperandInfo153}, // Inst #4494 = SQRSHRNT_ZZI_B + {4, OperandInfo153}, // Inst #4495 = SQRSHRNT_ZZI_H + {4, OperandInfo153}, // Inst #4496 = SQRSHRNT_ZZI_S + {3, OperandInfo435}, // Inst #4497 = SQRSHRNb + {3, OperandInfo436}, // Inst #4498 = SQRSHRNh + {3, OperandInfo437}, // Inst #4499 = SQRSHRNs + {4, OperandInfo400}, // Inst #4500 = SQRSHRNv16i8_shift + {3, OperandInfo186}, // Inst #4501 = SQRSHRNv2i32_shift + {3, OperandInfo186}, // Inst #4502 = SQRSHRNv4i16_shift + {4, OperandInfo400}, // Inst #4503 = SQRSHRNv4i32_shift + {4, OperandInfo400}, // Inst #4504 = SQRSHRNv8i16_shift + {3, OperandInfo186}, // Inst #4505 = SQRSHRNv8i8_shift + {3, OperandInfo134}, // Inst #4506 = SQRSHRUNB_ZZI_B + {3, OperandInfo134}, // Inst #4507 = SQRSHRUNB_ZZI_H + {3, OperandInfo134}, // Inst #4508 = SQRSHRUNB_ZZI_S + {4, OperandInfo153}, // Inst #4509 = SQRSHRUNT_ZZI_B + {4, OperandInfo153}, // Inst #4510 = SQRSHRUNT_ZZI_H + {4, OperandInfo153}, // Inst #4511 = SQRSHRUNT_ZZI_S + {3, OperandInfo435}, // Inst #4512 = SQRSHRUNb + {3, OperandInfo436}, // Inst #4513 = SQRSHRUNh + {3, OperandInfo437}, // Inst #4514 = SQRSHRUNs + {4, OperandInfo400}, // Inst #4515 = SQRSHRUNv16i8_shift + {3, OperandInfo186}, // Inst #4516 = SQRSHRUNv2i32_shift + {3, OperandInfo186}, // Inst #4517 = SQRSHRUNv4i16_shift + {4, OperandInfo400}, // Inst #4518 = SQRSHRUNv4i32_shift + {4, OperandInfo400}, // Inst #4519 = SQRSHRUNv8i16_shift + {3, OperandInfo186}, // Inst #4520 = SQRSHRUNv8i8_shift + {4, OperandInfo100}, // Inst #4521 = SQSHLR_ZPmZ_B + {4, OperandInfo100}, // Inst #4522 = SQSHLR_ZPmZ_D + {4, OperandInfo100}, // Inst #4523 = SQSHLR_ZPmZ_H + {4, OperandInfo100}, // Inst #4524 = SQSHLR_ZPmZ_S + {4, OperandInfo133}, // Inst #4525 = SQSHLU_ZPmI_B + {4, OperandInfo133}, // Inst #4526 = SQSHLU_ZPmI_D + {4, OperandInfo133}, // Inst #4527 = SQSHLU_ZPmI_H + {4, OperandInfo133}, // Inst #4528 = SQSHLU_ZPmI_S + {3, OperandInfo438}, // Inst #4529 = SQSHLUb + {3, OperandInfo244}, // Inst #4530 = SQSHLUd + {3, OperandInfo245}, // Inst #4531 = SQSHLUh + {3, OperandInfo246}, // Inst #4532 = SQSHLUs + {3, OperandInfo199}, // Inst #4533 = SQSHLUv16i8_shift + {3, OperandInfo244}, // Inst #4534 = SQSHLUv2i32_shift + {3, OperandInfo199}, // Inst #4535 = SQSHLUv2i64_shift + {3, OperandInfo244}, // Inst #4536 = SQSHLUv4i16_shift + {3, OperandInfo199}, // Inst #4537 = SQSHLUv4i32_shift + {3, OperandInfo199}, // Inst #4538 = SQSHLUv8i16_shift + {3, OperandInfo244}, // Inst #4539 = SQSHLUv8i8_shift + {4, OperandInfo133}, // Inst #4540 = SQSHL_ZPmI_B + {4, OperandInfo133}, // Inst #4541 = SQSHL_ZPmI_D + {4, OperandInfo133}, // Inst #4542 = SQSHL_ZPmI_H + {4, OperandInfo133}, // Inst #4543 = SQSHL_ZPmI_S + {4, OperandInfo100}, // Inst #4544 = SQSHL_ZPmZ_B + {4, OperandInfo100}, // Inst #4545 = SQSHL_ZPmZ_D + {4, OperandInfo100}, // Inst #4546 = SQSHL_ZPmZ_H + {4, OperandInfo100}, // Inst #4547 = SQSHL_ZPmZ_S + {3, OperandInfo438}, // Inst #4548 = SQSHLb + {3, OperandInfo244}, // Inst #4549 = SQSHLd + {3, OperandInfo245}, // Inst #4550 = SQSHLh + {3, OperandInfo246}, // Inst #4551 = SQSHLs + {3, OperandInfo101}, // Inst #4552 = SQSHLv16i8 + {3, OperandInfo199}, // Inst #4553 = SQSHLv16i8_shift + {3, OperandInfo210}, // Inst #4554 = SQSHLv1i16 + {3, OperandInfo211}, // Inst #4555 = SQSHLv1i32 + {3, OperandInfo102}, // Inst #4556 = SQSHLv1i64 + {3, OperandInfo424}, // Inst #4557 = SQSHLv1i8 + {3, OperandInfo102}, // Inst #4558 = SQSHLv2i32 + {3, OperandInfo244}, // Inst #4559 = SQSHLv2i32_shift + {3, OperandInfo101}, // Inst #4560 = SQSHLv2i64 + {3, OperandInfo199}, // Inst #4561 = SQSHLv2i64_shift + {3, OperandInfo102}, // Inst #4562 = SQSHLv4i16 + {3, OperandInfo244}, // Inst #4563 = SQSHLv4i16_shift + {3, OperandInfo101}, // Inst #4564 = SQSHLv4i32 + {3, OperandInfo199}, // Inst #4565 = SQSHLv4i32_shift + {3, OperandInfo101}, // Inst #4566 = SQSHLv8i16 + {3, OperandInfo199}, // Inst #4567 = SQSHLv8i16_shift + {3, OperandInfo102}, // Inst #4568 = SQSHLv8i8 + {3, OperandInfo244}, // Inst #4569 = SQSHLv8i8_shift + {3, OperandInfo134}, // Inst #4570 = SQSHRNB_ZZI_B + {3, OperandInfo134}, // Inst #4571 = SQSHRNB_ZZI_H + {3, OperandInfo134}, // Inst #4572 = SQSHRNB_ZZI_S + {4, OperandInfo153}, // Inst #4573 = SQSHRNT_ZZI_B + {4, OperandInfo153}, // Inst #4574 = SQSHRNT_ZZI_H + {4, OperandInfo153}, // Inst #4575 = SQSHRNT_ZZI_S + {3, OperandInfo435}, // Inst #4576 = SQSHRNb + {3, OperandInfo436}, // Inst #4577 = SQSHRNh + {3, OperandInfo437}, // Inst #4578 = SQSHRNs + {4, OperandInfo400}, // Inst #4579 = SQSHRNv16i8_shift + {3, OperandInfo186}, // Inst #4580 = SQSHRNv2i32_shift + {3, OperandInfo186}, // Inst #4581 = SQSHRNv4i16_shift + {4, OperandInfo400}, // Inst #4582 = SQSHRNv4i32_shift + {4, OperandInfo400}, // Inst #4583 = SQSHRNv8i16_shift + {3, OperandInfo186}, // Inst #4584 = SQSHRNv8i8_shift + {3, OperandInfo134}, // Inst #4585 = SQSHRUNB_ZZI_B + {3, OperandInfo134}, // Inst #4586 = SQSHRUNB_ZZI_H + {3, OperandInfo134}, // Inst #4587 = SQSHRUNB_ZZI_S + {4, OperandInfo153}, // Inst #4588 = SQSHRUNT_ZZI_B + {4, OperandInfo153}, // Inst #4589 = SQSHRUNT_ZZI_H + {4, OperandInfo153}, // Inst #4590 = SQSHRUNT_ZZI_S + {3, OperandInfo435}, // Inst #4591 = SQSHRUNb + {3, OperandInfo436}, // Inst #4592 = SQSHRUNh + {3, OperandInfo437}, // Inst #4593 = SQSHRUNs + {4, OperandInfo400}, // Inst #4594 = SQSHRUNv16i8_shift + {3, OperandInfo186}, // Inst #4595 = SQSHRUNv2i32_shift + {3, OperandInfo186}, // Inst #4596 = SQSHRUNv4i16_shift + {4, OperandInfo400}, // Inst #4597 = SQSHRUNv4i32_shift + {4, OperandInfo400}, // Inst #4598 = SQSHRUNv8i16_shift + {3, OperandInfo186}, // Inst #4599 = SQSHRUNv8i8_shift + {4, OperandInfo100}, // Inst #4600 = SQSUBR_ZPmZ_B + {4, OperandInfo100}, // Inst #4601 = SQSUBR_ZPmZ_D + {4, OperandInfo100}, // Inst #4602 = SQSUBR_ZPmZ_H + {4, OperandInfo100}, // Inst #4603 = SQSUBR_ZPmZ_S + {4, OperandInfo120}, // Inst #4604 = SQSUB_ZI_B + {4, OperandInfo120}, // Inst #4605 = SQSUB_ZI_D + {4, OperandInfo120}, // Inst #4606 = SQSUB_ZI_H + {4, OperandInfo120}, // Inst #4607 = SQSUB_ZI_S + {4, OperandInfo100}, // Inst #4608 = SQSUB_ZPmZ_B + {4, OperandInfo100}, // Inst #4609 = SQSUB_ZPmZ_D + {4, OperandInfo100}, // Inst #4610 = SQSUB_ZPmZ_H + {4, OperandInfo100}, // Inst #4611 = SQSUB_ZPmZ_S + {3, OperandInfo96}, // Inst #4612 = SQSUB_ZZZ_B + {3, OperandInfo96}, // Inst #4613 = SQSUB_ZZZ_D + {3, OperandInfo96}, // Inst #4614 = SQSUB_ZZZ_H + {3, OperandInfo96}, // Inst #4615 = SQSUB_ZZZ_S + {3, OperandInfo101}, // Inst #4616 = SQSUBv16i8 + {3, OperandInfo210}, // Inst #4617 = SQSUBv1i16 + {3, OperandInfo211}, // Inst #4618 = SQSUBv1i32 + {3, OperandInfo102}, // Inst #4619 = SQSUBv1i64 + {3, OperandInfo424}, // Inst #4620 = SQSUBv1i8 + {3, OperandInfo102}, // Inst #4621 = SQSUBv2i32 + {3, OperandInfo101}, // Inst #4622 = SQSUBv2i64 + {3, OperandInfo102}, // Inst #4623 = SQSUBv4i16 + {3, OperandInfo101}, // Inst #4624 = SQSUBv4i32 + {3, OperandInfo101}, // Inst #4625 = SQSUBv8i16 + {3, OperandInfo102}, // Inst #4626 = SQSUBv8i8 + {2, OperandInfo247}, // Inst #4627 = SQXTNB_ZZ_B + {2, OperandInfo247}, // Inst #4628 = SQXTNB_ZZ_H + {2, OperandInfo247}, // Inst #4629 = SQXTNB_ZZ_S + {3, OperandInfo123}, // Inst #4630 = SQXTNT_ZZ_B + {3, OperandInfo123}, // Inst #4631 = SQXTNT_ZZ_H + {3, OperandInfo123}, // Inst #4632 = SQXTNT_ZZ_S + {3, OperandInfo124}, // Inst #4633 = SQXTNv16i8 + {2, OperandInfo140}, // Inst #4634 = SQXTNv1i16 + {2, OperandInfo214}, // Inst #4635 = SQXTNv1i32 + {2, OperandInfo439}, // Inst #4636 = SQXTNv1i8 + {2, OperandInfo103}, // Inst #4637 = SQXTNv2i32 + {2, OperandInfo103}, // Inst #4638 = SQXTNv4i16 + {3, OperandInfo124}, // Inst #4639 = SQXTNv4i32 + {3, OperandInfo124}, // Inst #4640 = SQXTNv8i16 + {2, OperandInfo103}, // Inst #4641 = SQXTNv8i8 + {2, OperandInfo247}, // Inst #4642 = SQXTUNB_ZZ_B + {2, OperandInfo247}, // Inst #4643 = SQXTUNB_ZZ_H + {2, OperandInfo247}, // Inst #4644 = SQXTUNB_ZZ_S + {3, OperandInfo123}, // Inst #4645 = SQXTUNT_ZZ_B + {3, OperandInfo123}, // Inst #4646 = SQXTUNT_ZZ_H + {3, OperandInfo123}, // Inst #4647 = SQXTUNT_ZZ_S + {3, OperandInfo124}, // Inst #4648 = SQXTUNv16i8 + {2, OperandInfo140}, // Inst #4649 = SQXTUNv1i16 + {2, OperandInfo214}, // Inst #4650 = SQXTUNv1i32 + {2, OperandInfo439}, // Inst #4651 = SQXTUNv1i8 + {2, OperandInfo103}, // Inst #4652 = SQXTUNv2i32 + {2, OperandInfo103}, // Inst #4653 = SQXTUNv4i16 + {3, OperandInfo124}, // Inst #4654 = SQXTUNv4i32 + {3, OperandInfo124}, // Inst #4655 = SQXTUNv8i16 + {2, OperandInfo103}, // Inst #4656 = SQXTUNv8i8 + {4, OperandInfo100}, // Inst #4657 = SRHADD_ZPmZ_B + {4, OperandInfo100}, // Inst #4658 = SRHADD_ZPmZ_D + {4, OperandInfo100}, // Inst #4659 = SRHADD_ZPmZ_H + {4, OperandInfo100}, // Inst #4660 = SRHADD_ZPmZ_S + {3, OperandInfo101}, // Inst #4661 = SRHADDv16i8 + {3, OperandInfo102}, // Inst #4662 = SRHADDv2i32 + {3, OperandInfo102}, // Inst #4663 = SRHADDv4i16 + {3, OperandInfo101}, // Inst #4664 = SRHADDv4i32 + {3, OperandInfo101}, // Inst #4665 = SRHADDv8i16 + {3, OperandInfo102}, // Inst #4666 = SRHADDv8i8 + {4, OperandInfo153}, // Inst #4667 = SRI_ZZI_B + {4, OperandInfo153}, // Inst #4668 = SRI_ZZI_D + {4, OperandInfo153}, // Inst #4669 = SRI_ZZI_H + {4, OperandInfo153}, // Inst #4670 = SRI_ZZI_S + {4, OperandInfo415}, // Inst #4671 = SRId + {4, OperandInfo400}, // Inst #4672 = SRIv16i8_shift + {4, OperandInfo415}, // Inst #4673 = SRIv2i32_shift + {4, OperandInfo400}, // Inst #4674 = SRIv2i64_shift + {4, OperandInfo415}, // Inst #4675 = SRIv4i16_shift + {4, OperandInfo400}, // Inst #4676 = SRIv4i32_shift + {4, OperandInfo400}, // Inst #4677 = SRIv8i16_shift + {4, OperandInfo415}, // Inst #4678 = SRIv8i8_shift + {4, OperandInfo100}, // Inst #4679 = SRSHLR_ZPmZ_B + {4, OperandInfo100}, // Inst #4680 = SRSHLR_ZPmZ_D + {4, OperandInfo100}, // Inst #4681 = SRSHLR_ZPmZ_H + {4, OperandInfo100}, // Inst #4682 = SRSHLR_ZPmZ_S + {4, OperandInfo100}, // Inst #4683 = SRSHL_ZPmZ_B + {4, OperandInfo100}, // Inst #4684 = SRSHL_ZPmZ_D + {4, OperandInfo100}, // Inst #4685 = SRSHL_ZPmZ_H + {4, OperandInfo100}, // Inst #4686 = SRSHL_ZPmZ_S + {3, OperandInfo101}, // Inst #4687 = SRSHLv16i8 + {3, OperandInfo102}, // Inst #4688 = SRSHLv1i64 + {3, OperandInfo102}, // Inst #4689 = SRSHLv2i32 + {3, OperandInfo101}, // Inst #4690 = SRSHLv2i64 + {3, OperandInfo102}, // Inst #4691 = SRSHLv4i16 + {3, OperandInfo101}, // Inst #4692 = SRSHLv4i32 + {3, OperandInfo101}, // Inst #4693 = SRSHLv8i16 + {3, OperandInfo102}, // Inst #4694 = SRSHLv8i8 + {4, OperandInfo133}, // Inst #4695 = SRSHR_ZPmI_B + {4, OperandInfo133}, // Inst #4696 = SRSHR_ZPmI_D + {4, OperandInfo133}, // Inst #4697 = SRSHR_ZPmI_H + {4, OperandInfo133}, // Inst #4698 = SRSHR_ZPmI_S + {3, OperandInfo244}, // Inst #4699 = SRSHRd + {3, OperandInfo199}, // Inst #4700 = SRSHRv16i8_shift + {3, OperandInfo244}, // Inst #4701 = SRSHRv2i32_shift + {3, OperandInfo199}, // Inst #4702 = SRSHRv2i64_shift + {3, OperandInfo244}, // Inst #4703 = SRSHRv4i16_shift + {3, OperandInfo199}, // Inst #4704 = SRSHRv4i32_shift + {3, OperandInfo199}, // Inst #4705 = SRSHRv8i16_shift + {3, OperandInfo244}, // Inst #4706 = SRSHRv8i8_shift + {4, OperandInfo153}, // Inst #4707 = SRSRA_ZZI_B + {4, OperandInfo153}, // Inst #4708 = SRSRA_ZZI_D + {4, OperandInfo153}, // Inst #4709 = SRSRA_ZZI_H + {4, OperandInfo153}, // Inst #4710 = SRSRA_ZZI_S + {4, OperandInfo415}, // Inst #4711 = SRSRAd + {4, OperandInfo400}, // Inst #4712 = SRSRAv16i8_shift + {4, OperandInfo415}, // Inst #4713 = SRSRAv2i32_shift + {4, OperandInfo400}, // Inst #4714 = SRSRAv2i64_shift + {4, OperandInfo415}, // Inst #4715 = SRSRAv4i16_shift + {4, OperandInfo400}, // Inst #4716 = SRSRAv4i32_shift + {4, OperandInfo400}, // Inst #4717 = SRSRAv8i16_shift + {4, OperandInfo415}, // Inst #4718 = SRSRAv8i8_shift + {3, OperandInfo134}, // Inst #4719 = SSHLLB_ZZI_D + {3, OperandInfo134}, // Inst #4720 = SSHLLB_ZZI_H + {3, OperandInfo134}, // Inst #4721 = SSHLLB_ZZI_S + {3, OperandInfo134}, // Inst #4722 = SSHLLT_ZZI_D + {3, OperandInfo134}, // Inst #4723 = SSHLLT_ZZI_H + {3, OperandInfo134}, // Inst #4724 = SSHLLT_ZZI_S + {3, OperandInfo199}, // Inst #4725 = SSHLLv16i8_shift + {3, OperandInfo440}, // Inst #4726 = SSHLLv2i32_shift + {3, OperandInfo440}, // Inst #4727 = SSHLLv4i16_shift + {3, OperandInfo199}, // Inst #4728 = SSHLLv4i32_shift + {3, OperandInfo199}, // Inst #4729 = SSHLLv8i16_shift + {3, OperandInfo440}, // Inst #4730 = SSHLLv8i8_shift + {3, OperandInfo101}, // Inst #4731 = SSHLv16i8 + {3, OperandInfo102}, // Inst #4732 = SSHLv1i64 + {3, OperandInfo102}, // Inst #4733 = SSHLv2i32 + {3, OperandInfo101}, // Inst #4734 = SSHLv2i64 + {3, OperandInfo102}, // Inst #4735 = SSHLv4i16 + {3, OperandInfo101}, // Inst #4736 = SSHLv4i32 + {3, OperandInfo101}, // Inst #4737 = SSHLv8i16 + {3, OperandInfo102}, // Inst #4738 = SSHLv8i8 + {3, OperandInfo244}, // Inst #4739 = SSHRd + {3, OperandInfo199}, // Inst #4740 = SSHRv16i8_shift + {3, OperandInfo244}, // Inst #4741 = SSHRv2i32_shift + {3, OperandInfo199}, // Inst #4742 = SSHRv2i64_shift + {3, OperandInfo244}, // Inst #4743 = SSHRv4i16_shift + {3, OperandInfo199}, // Inst #4744 = SSHRv4i32_shift + {3, OperandInfo199}, // Inst #4745 = SSHRv8i16_shift + {3, OperandInfo244}, // Inst #4746 = SSHRv8i8_shift + {4, OperandInfo153}, // Inst #4747 = SSRA_ZZI_B + {4, OperandInfo153}, // Inst #4748 = SSRA_ZZI_D + {4, OperandInfo153}, // Inst #4749 = SSRA_ZZI_H + {4, OperandInfo153}, // Inst #4750 = SSRA_ZZI_S + {4, OperandInfo415}, // Inst #4751 = SSRAd + {4, OperandInfo400}, // Inst #4752 = SSRAv16i8_shift + {4, OperandInfo415}, // Inst #4753 = SSRAv2i32_shift + {4, OperandInfo400}, // Inst #4754 = SSRAv2i64_shift + {4, OperandInfo415}, // Inst #4755 = SSRAv4i16_shift + {4, OperandInfo400}, // Inst #4756 = SSRAv4i32_shift + {4, OperandInfo400}, // Inst #4757 = SSRAv8i16_shift + {4, OperandInfo415}, // Inst #4758 = SSRAv8i8_shift + {4, OperandInfo50}, // Inst #4759 = SST1B_D_IMM + {4, OperandInfo63}, // Inst #4760 = SST1B_D_REAL + {4, OperandInfo63}, // Inst #4761 = SST1B_D_SXTW + {4, OperandInfo63}, // Inst #4762 = SST1B_D_UXTW + {4, OperandInfo50}, // Inst #4763 = SST1B_S_IMM + {4, OperandInfo63}, // Inst #4764 = SST1B_S_SXTW + {4, OperandInfo63}, // Inst #4765 = SST1B_S_UXTW + {4, OperandInfo50}, // Inst #4766 = SST1D_IMM + {4, OperandInfo63}, // Inst #4767 = SST1D_REAL + {4, OperandInfo63}, // Inst #4768 = SST1D_SCALED_SCALED_REAL + {4, OperandInfo63}, // Inst #4769 = SST1D_SXTW + {4, OperandInfo63}, // Inst #4770 = SST1D_SXTW_SCALED + {4, OperandInfo63}, // Inst #4771 = SST1D_UXTW + {4, OperandInfo63}, // Inst #4772 = SST1D_UXTW_SCALED + {4, OperandInfo50}, // Inst #4773 = SST1H_D_IMM + {4, OperandInfo63}, // Inst #4774 = SST1H_D_REAL + {4, OperandInfo63}, // Inst #4775 = SST1H_D_SCALED_SCALED_REAL + {4, OperandInfo63}, // Inst #4776 = SST1H_D_SXTW + {4, OperandInfo63}, // Inst #4777 = SST1H_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #4778 = SST1H_D_UXTW + {4, OperandInfo63}, // Inst #4779 = SST1H_D_UXTW_SCALED + {4, OperandInfo50}, // Inst #4780 = SST1H_S_IMM + {4, OperandInfo63}, // Inst #4781 = SST1H_S_SXTW + {4, OperandInfo63}, // Inst #4782 = SST1H_S_SXTW_SCALED + {4, OperandInfo63}, // Inst #4783 = SST1H_S_UXTW + {4, OperandInfo63}, // Inst #4784 = SST1H_S_UXTW_SCALED + {4, OperandInfo50}, // Inst #4785 = SST1W_D_IMM + {4, OperandInfo63}, // Inst #4786 = SST1W_D_REAL + {4, OperandInfo63}, // Inst #4787 = SST1W_D_SCALED_SCALED_REAL + {4, OperandInfo63}, // Inst #4788 = SST1W_D_SXTW + {4, OperandInfo63}, // Inst #4789 = SST1W_D_SXTW_SCALED + {4, OperandInfo63}, // Inst #4790 = SST1W_D_UXTW + {4, OperandInfo63}, // Inst #4791 = SST1W_D_UXTW_SCALED + {4, OperandInfo50}, // Inst #4792 = SST1W_IMM + {4, OperandInfo63}, // Inst #4793 = SST1W_SXTW + {4, OperandInfo63}, // Inst #4794 = SST1W_SXTW_SCALED + {4, OperandInfo63}, // Inst #4795 = SST1W_UXTW + {4, OperandInfo63}, // Inst #4796 = SST1W_UXTW_SCALED + {3, OperandInfo96}, // Inst #4797 = SSUBLBT_ZZZ_D + {3, OperandInfo96}, // Inst #4798 = SSUBLBT_ZZZ_H + {3, OperandInfo96}, // Inst #4799 = SSUBLBT_ZZZ_S + {3, OperandInfo96}, // Inst #4800 = SSUBLB_ZZZ_D + {3, OperandInfo96}, // Inst #4801 = SSUBLB_ZZZ_H + {3, OperandInfo96}, // Inst #4802 = SSUBLB_ZZZ_S + {3, OperandInfo96}, // Inst #4803 = SSUBLTB_ZZZ_D + {3, OperandInfo96}, // Inst #4804 = SSUBLTB_ZZZ_H + {3, OperandInfo96}, // Inst #4805 = SSUBLTB_ZZZ_S + {3, OperandInfo96}, // Inst #4806 = SSUBLT_ZZZ_D + {3, OperandInfo96}, // Inst #4807 = SSUBLT_ZZZ_H + {3, OperandInfo96}, // Inst #4808 = SSUBLT_ZZZ_S + {3, OperandInfo101}, // Inst #4809 = SSUBLv16i8_v8i16 + {3, OperandInfo390}, // Inst #4810 = SSUBLv2i32_v2i64 + {3, OperandInfo390}, // Inst #4811 = SSUBLv4i16_v4i32 + {3, OperandInfo101}, // Inst #4812 = SSUBLv4i32_v2i64 + {3, OperandInfo101}, // Inst #4813 = SSUBLv8i16_v4i32 + {3, OperandInfo390}, // Inst #4814 = SSUBLv8i8_v8i16 + {3, OperandInfo96}, // Inst #4815 = SSUBWB_ZZZ_D + {3, OperandInfo96}, // Inst #4816 = SSUBWB_ZZZ_H + {3, OperandInfo96}, // Inst #4817 = SSUBWB_ZZZ_S + {3, OperandInfo96}, // Inst #4818 = SSUBWT_ZZZ_D + {3, OperandInfo96}, // Inst #4819 = SSUBWT_ZZZ_H + {3, OperandInfo96}, // Inst #4820 = SSUBWT_ZZZ_S + {3, OperandInfo101}, // Inst #4821 = SSUBWv16i8_v8i16 + {3, OperandInfo403}, // Inst #4822 = SSUBWv2i32_v2i64 + {3, OperandInfo403}, // Inst #4823 = SSUBWv4i16_v4i32 + {3, OperandInfo101}, // Inst #4824 = SSUBWv4i32_v2i64 + {3, OperandInfo101}, // Inst #4825 = SSUBWv8i16_v4i32 + {3, OperandInfo403}, // Inst #4826 = SSUBWv8i8_v8i16 + {4, OperandInfo297}, // Inst #4827 = ST1B + {4, OperandInfo297}, // Inst #4828 = ST1B_D + {4, OperandInfo67}, // Inst #4829 = ST1B_D_IMM + {4, OperandInfo297}, // Inst #4830 = ST1B_H + {4, OperandInfo67}, // Inst #4831 = ST1B_H_IMM + {4, OperandInfo67}, // Inst #4832 = ST1B_IMM + {4, OperandInfo297}, // Inst #4833 = ST1B_S + {4, OperandInfo67}, // Inst #4834 = ST1B_S_IMM + {4, OperandInfo297}, // Inst #4835 = ST1D + {4, OperandInfo67}, // Inst #4836 = ST1D_IMM + {2, OperandInfo298}, // Inst #4837 = ST1Fourv16b + {4, OperandInfo299}, // Inst #4838 = ST1Fourv16b_POST + {2, OperandInfo300}, // Inst #4839 = ST1Fourv1d + {4, OperandInfo301}, // Inst #4840 = ST1Fourv1d_POST + {2, OperandInfo298}, // Inst #4841 = ST1Fourv2d + {4, OperandInfo299}, // Inst #4842 = ST1Fourv2d_POST + {2, OperandInfo300}, // Inst #4843 = ST1Fourv2s + {4, OperandInfo301}, // Inst #4844 = ST1Fourv2s_POST + {2, OperandInfo300}, // Inst #4845 = ST1Fourv4h + {4, OperandInfo301}, // Inst #4846 = ST1Fourv4h_POST + {2, OperandInfo298}, // Inst #4847 = ST1Fourv4s + {4, OperandInfo299}, // Inst #4848 = ST1Fourv4s_POST + {2, OperandInfo300}, // Inst #4849 = ST1Fourv8b + {4, OperandInfo301}, // Inst #4850 = ST1Fourv8b_POST + {2, OperandInfo298}, // Inst #4851 = ST1Fourv8h + {4, OperandInfo299}, // Inst #4852 = ST1Fourv8h_POST + {4, OperandInfo297}, // Inst #4853 = ST1H + {4, OperandInfo297}, // Inst #4854 = ST1H_D + {4, OperandInfo67}, // Inst #4855 = ST1H_D_IMM + {4, OperandInfo67}, // Inst #4856 = ST1H_IMM + {4, OperandInfo297}, // Inst #4857 = ST1H_S + {4, OperandInfo67}, // Inst #4858 = ST1H_S_IMM + {2, OperandInfo302}, // Inst #4859 = ST1Onev16b + {4, OperandInfo303}, // Inst #4860 = ST1Onev16b_POST + {2, OperandInfo304}, // Inst #4861 = ST1Onev1d + {4, OperandInfo305}, // Inst #4862 = ST1Onev1d_POST + {2, OperandInfo302}, // Inst #4863 = ST1Onev2d + {4, OperandInfo303}, // Inst #4864 = ST1Onev2d_POST + {2, OperandInfo304}, // Inst #4865 = ST1Onev2s + {4, OperandInfo305}, // Inst #4866 = ST1Onev2s_POST + {2, OperandInfo304}, // Inst #4867 = ST1Onev4h + {4, OperandInfo305}, // Inst #4868 = ST1Onev4h_POST + {2, OperandInfo302}, // Inst #4869 = ST1Onev4s + {4, OperandInfo303}, // Inst #4870 = ST1Onev4s_POST + {2, OperandInfo304}, // Inst #4871 = ST1Onev8b + {4, OperandInfo305}, // Inst #4872 = ST1Onev8b_POST + {2, OperandInfo302}, // Inst #4873 = ST1Onev8h + {4, OperandInfo303}, // Inst #4874 = ST1Onev8h_POST + {2, OperandInfo306}, // Inst #4875 = ST1Threev16b + {4, OperandInfo307}, // Inst #4876 = ST1Threev16b_POST + {2, OperandInfo308}, // Inst #4877 = ST1Threev1d + {4, OperandInfo309}, // Inst #4878 = ST1Threev1d_POST + {2, OperandInfo306}, // Inst #4879 = ST1Threev2d + {4, OperandInfo307}, // Inst #4880 = ST1Threev2d_POST + {2, OperandInfo308}, // Inst #4881 = ST1Threev2s + {4, OperandInfo309}, // Inst #4882 = ST1Threev2s_POST + {2, OperandInfo308}, // Inst #4883 = ST1Threev4h + {4, OperandInfo309}, // Inst #4884 = ST1Threev4h_POST + {2, OperandInfo306}, // Inst #4885 = ST1Threev4s + {4, OperandInfo307}, // Inst #4886 = ST1Threev4s_POST + {2, OperandInfo308}, // Inst #4887 = ST1Threev8b + {4, OperandInfo309}, // Inst #4888 = ST1Threev8b_POST + {2, OperandInfo306}, // Inst #4889 = ST1Threev8h + {4, OperandInfo307}, // Inst #4890 = ST1Threev8h_POST + {2, OperandInfo310}, // Inst #4891 = ST1Twov16b + {4, OperandInfo311}, // Inst #4892 = ST1Twov16b_POST + {2, OperandInfo312}, // Inst #4893 = ST1Twov1d + {4, OperandInfo313}, // Inst #4894 = ST1Twov1d_POST + {2, OperandInfo310}, // Inst #4895 = ST1Twov2d + {4, OperandInfo311}, // Inst #4896 = ST1Twov2d_POST + {2, OperandInfo312}, // Inst #4897 = ST1Twov2s + {4, OperandInfo313}, // Inst #4898 = ST1Twov2s_POST + {2, OperandInfo312}, // Inst #4899 = ST1Twov4h + {4, OperandInfo313}, // Inst #4900 = ST1Twov4h_POST + {2, OperandInfo310}, // Inst #4901 = ST1Twov4s + {4, OperandInfo311}, // Inst #4902 = ST1Twov4s_POST + {2, OperandInfo312}, // Inst #4903 = ST1Twov8b + {4, OperandInfo313}, // Inst #4904 = ST1Twov8b_POST + {2, OperandInfo310}, // Inst #4905 = ST1Twov8h + {4, OperandInfo311}, // Inst #4906 = ST1Twov8h_POST + {4, OperandInfo297}, // Inst #4907 = ST1W + {4, OperandInfo297}, // Inst #4908 = ST1W_D + {4, OperandInfo67}, // Inst #4909 = ST1W_D_IMM + {4, OperandInfo67}, // Inst #4910 = ST1W_IMM + {6, OperandInfo314}, // Inst #4911 = ST1_MXIPXX_H_B + {6, OperandInfo315}, // Inst #4912 = ST1_MXIPXX_H_D + {6, OperandInfo316}, // Inst #4913 = ST1_MXIPXX_H_H + {6, OperandInfo317}, // Inst #4914 = ST1_MXIPXX_H_Q + {6, OperandInfo318}, // Inst #4915 = ST1_MXIPXX_H_S + {6, OperandInfo314}, // Inst #4916 = ST1_MXIPXX_V_B + {6, OperandInfo315}, // Inst #4917 = ST1_MXIPXX_V_D + {6, OperandInfo316}, // Inst #4918 = ST1_MXIPXX_V_H + {6, OperandInfo317}, // Inst #4919 = ST1_MXIPXX_V_Q + {6, OperandInfo318}, // Inst #4920 = ST1_MXIPXX_V_S + {3, OperandInfo441}, // Inst #4921 = ST1i16 + {5, OperandInfo442}, // Inst #4922 = ST1i16_POST + {3, OperandInfo441}, // Inst #4923 = ST1i32 + {5, OperandInfo442}, // Inst #4924 = ST1i32_POST + {3, OperandInfo441}, // Inst #4925 = ST1i64 + {5, OperandInfo442}, // Inst #4926 = ST1i64_POST + {3, OperandInfo441}, // Inst #4927 = ST1i8 + {5, OperandInfo442}, // Inst #4928 = ST1i8_POST + {4, OperandInfo321}, // Inst #4929 = ST2B + {4, OperandInfo322}, // Inst #4930 = ST2B_IMM + {4, OperandInfo321}, // Inst #4931 = ST2D + {4, OperandInfo322}, // Inst #4932 = ST2D_IMM + {3, OperandInfo99}, // Inst #4933 = ST2GOffset + {4, OperandInfo443}, // Inst #4934 = ST2GPostIndex + {4, OperandInfo443}, // Inst #4935 = ST2GPreIndex + {4, OperandInfo321}, // Inst #4936 = ST2H + {4, OperandInfo322}, // Inst #4937 = ST2H_IMM + {2, OperandInfo310}, // Inst #4938 = ST2Twov16b + {4, OperandInfo311}, // Inst #4939 = ST2Twov16b_POST + {2, OperandInfo310}, // Inst #4940 = ST2Twov2d + {4, OperandInfo311}, // Inst #4941 = ST2Twov2d_POST + {2, OperandInfo312}, // Inst #4942 = ST2Twov2s + {4, OperandInfo313}, // Inst #4943 = ST2Twov2s_POST + {2, OperandInfo312}, // Inst #4944 = ST2Twov4h + {4, OperandInfo313}, // Inst #4945 = ST2Twov4h_POST + {2, OperandInfo310}, // Inst #4946 = ST2Twov4s + {4, OperandInfo311}, // Inst #4947 = ST2Twov4s_POST + {2, OperandInfo312}, // Inst #4948 = ST2Twov8b + {4, OperandInfo313}, // Inst #4949 = ST2Twov8b_POST + {2, OperandInfo310}, // Inst #4950 = ST2Twov8h + {4, OperandInfo311}, // Inst #4951 = ST2Twov8h_POST + {4, OperandInfo321}, // Inst #4952 = ST2W + {4, OperandInfo322}, // Inst #4953 = ST2W_IMM + {3, OperandInfo444}, // Inst #4954 = ST2i16 + {5, OperandInfo445}, // Inst #4955 = ST2i16_POST + {3, OperandInfo444}, // Inst #4956 = ST2i32 + {5, OperandInfo445}, // Inst #4957 = ST2i32_POST + {3, OperandInfo444}, // Inst #4958 = ST2i64 + {5, OperandInfo445}, // Inst #4959 = ST2i64_POST + {3, OperandInfo444}, // Inst #4960 = ST2i8 + {5, OperandInfo445}, // Inst #4961 = ST2i8_POST + {4, OperandInfo325}, // Inst #4962 = ST3B + {4, OperandInfo326}, // Inst #4963 = ST3B_IMM + {4, OperandInfo325}, // Inst #4964 = ST3D + {4, OperandInfo326}, // Inst #4965 = ST3D_IMM + {4, OperandInfo325}, // Inst #4966 = ST3H + {4, OperandInfo326}, // Inst #4967 = ST3H_IMM + {2, OperandInfo306}, // Inst #4968 = ST3Threev16b + {4, OperandInfo307}, // Inst #4969 = ST3Threev16b_POST + {2, OperandInfo306}, // Inst #4970 = ST3Threev2d + {4, OperandInfo307}, // Inst #4971 = ST3Threev2d_POST + {2, OperandInfo308}, // Inst #4972 = ST3Threev2s + {4, OperandInfo309}, // Inst #4973 = ST3Threev2s_POST + {2, OperandInfo308}, // Inst #4974 = ST3Threev4h + {4, OperandInfo309}, // Inst #4975 = ST3Threev4h_POST + {2, OperandInfo306}, // Inst #4976 = ST3Threev4s + {4, OperandInfo307}, // Inst #4977 = ST3Threev4s_POST + {2, OperandInfo308}, // Inst #4978 = ST3Threev8b + {4, OperandInfo309}, // Inst #4979 = ST3Threev8b_POST + {2, OperandInfo306}, // Inst #4980 = ST3Threev8h + {4, OperandInfo307}, // Inst #4981 = ST3Threev8h_POST + {4, OperandInfo325}, // Inst #4982 = ST3W + {4, OperandInfo326}, // Inst #4983 = ST3W_IMM + {3, OperandInfo446}, // Inst #4984 = ST3i16 + {5, OperandInfo447}, // Inst #4985 = ST3i16_POST + {3, OperandInfo446}, // Inst #4986 = ST3i32 + {5, OperandInfo447}, // Inst #4987 = ST3i32_POST + {3, OperandInfo446}, // Inst #4988 = ST3i64 + {5, OperandInfo447}, // Inst #4989 = ST3i64_POST + {3, OperandInfo446}, // Inst #4990 = ST3i8 + {5, OperandInfo447}, // Inst #4991 = ST3i8_POST + {4, OperandInfo329}, // Inst #4992 = ST4B + {4, OperandInfo330}, // Inst #4993 = ST4B_IMM + {4, OperandInfo329}, // Inst #4994 = ST4D + {4, OperandInfo330}, // Inst #4995 = ST4D_IMM + {2, OperandInfo298}, // Inst #4996 = ST4Fourv16b + {4, OperandInfo299}, // Inst #4997 = ST4Fourv16b_POST + {2, OperandInfo298}, // Inst #4998 = ST4Fourv2d + {4, OperandInfo299}, // Inst #4999 = ST4Fourv2d_POST + {2, OperandInfo300}, // Inst #5000 = ST4Fourv2s + {4, OperandInfo301}, // Inst #5001 = ST4Fourv2s_POST + {2, OperandInfo300}, // Inst #5002 = ST4Fourv4h + {4, OperandInfo301}, // Inst #5003 = ST4Fourv4h_POST + {2, OperandInfo298}, // Inst #5004 = ST4Fourv4s + {4, OperandInfo299}, // Inst #5005 = ST4Fourv4s_POST + {2, OperandInfo300}, // Inst #5006 = ST4Fourv8b + {4, OperandInfo301}, // Inst #5007 = ST4Fourv8b_POST + {2, OperandInfo298}, // Inst #5008 = ST4Fourv8h + {4, OperandInfo299}, // Inst #5009 = ST4Fourv8h_POST + {4, OperandInfo329}, // Inst #5010 = ST4H + {4, OperandInfo330}, // Inst #5011 = ST4H_IMM + {4, OperandInfo329}, // Inst #5012 = ST4W + {4, OperandInfo330}, // Inst #5013 = ST4W_IMM + {3, OperandInfo448}, // Inst #5014 = ST4i16 + {5, OperandInfo449}, // Inst #5015 = ST4i16_POST + {3, OperandInfo448}, // Inst #5016 = ST4i32 + {5, OperandInfo449}, // Inst #5017 = ST4i32_POST + {3, OperandInfo448}, // Inst #5018 = ST4i64 + {5, OperandInfo449}, // Inst #5019 = ST4i64_POST + {3, OperandInfo448}, // Inst #5020 = ST4i8 + {5, OperandInfo449}, // Inst #5021 = ST4i8_POST + {2, OperandInfo333}, // Inst #5022 = ST64B + {3, OperandInfo450}, // Inst #5023 = ST64BV + {3, OperandInfo450}, // Inst #5024 = ST64BV0 + {2, OperandInfo148}, // Inst #5025 = STGM + {3, OperandInfo99}, // Inst #5026 = STGOffset + {4, OperandInfo343}, // Inst #5027 = STGPi + {4, OperandInfo443}, // Inst #5028 = STGPostIndex + {5, OperandInfo347}, // Inst #5029 = STGPpost + {5, OperandInfo347}, // Inst #5030 = STGPpre + {4, OperandInfo443}, // Inst #5031 = STGPreIndex + {2, OperandInfo336}, // Inst #5032 = STLLRB + {2, OperandInfo336}, // Inst #5033 = STLLRH + {2, OperandInfo336}, // Inst #5034 = STLLRW + {2, OperandInfo148}, // Inst #5035 = STLLRX + {2, OperandInfo336}, // Inst #5036 = STLRB + {2, OperandInfo336}, // Inst #5037 = STLRH + {2, OperandInfo336}, // Inst #5038 = STLRW + {2, OperandInfo148}, // Inst #5039 = STLRX + {3, OperandInfo337}, // Inst #5040 = STLURBi + {3, OperandInfo337}, // Inst #5041 = STLURHi + {3, OperandInfo337}, // Inst #5042 = STLURWi + {3, OperandInfo85}, // Inst #5043 = STLURXi + {4, OperandInfo451}, // Inst #5044 = STLXPW + {4, OperandInfo452}, // Inst #5045 = STLXPX + {3, OperandInfo453}, // Inst #5046 = STLXRB + {3, OperandInfo453}, // Inst #5047 = STLXRH + {3, OperandInfo453}, // Inst #5048 = STLXRW + {3, OperandInfo454}, // Inst #5049 = STLXRX + {4, OperandInfo339}, // Inst #5050 = STNPDi + {4, OperandInfo340}, // Inst #5051 = STNPQi + {4, OperandInfo341}, // Inst #5052 = STNPSi + {4, OperandInfo342}, // Inst #5053 = STNPWi + {4, OperandInfo343}, // Inst #5054 = STNPXi + {4, OperandInfo67}, // Inst #5055 = STNT1B_ZRI + {4, OperandInfo297}, // Inst #5056 = STNT1B_ZRR + {4, OperandInfo344}, // Inst #5057 = STNT1B_ZZR_D_REAL + {4, OperandInfo344}, // Inst #5058 = STNT1B_ZZR_S_REAL + {4, OperandInfo67}, // Inst #5059 = STNT1D_ZRI + {4, OperandInfo297}, // Inst #5060 = STNT1D_ZRR + {4, OperandInfo344}, // Inst #5061 = STNT1D_ZZR_D_REAL + {4, OperandInfo67}, // Inst #5062 = STNT1H_ZRI + {4, OperandInfo297}, // Inst #5063 = STNT1H_ZRR + {4, OperandInfo344}, // Inst #5064 = STNT1H_ZZR_D_REAL + {4, OperandInfo344}, // Inst #5065 = STNT1H_ZZR_S_REAL + {4, OperandInfo67}, // Inst #5066 = STNT1W_ZRI + {4, OperandInfo297}, // Inst #5067 = STNT1W_ZRR + {4, OperandInfo344}, // Inst #5068 = STNT1W_ZZR_D_REAL + {4, OperandInfo344}, // Inst #5069 = STNT1W_ZZR_S_REAL + {4, OperandInfo339}, // Inst #5070 = STPDi + {5, OperandInfo345}, // Inst #5071 = STPDpost + {5, OperandInfo345}, // Inst #5072 = STPDpre + {4, OperandInfo340}, // Inst #5073 = STPQi + {5, OperandInfo346}, // Inst #5074 = STPQpost + {5, OperandInfo346}, // Inst #5075 = STPQpre + {4, OperandInfo341}, // Inst #5076 = STPSi + {5, OperandInfo348}, // Inst #5077 = STPSpost + {5, OperandInfo348}, // Inst #5078 = STPSpre + {4, OperandInfo342}, // Inst #5079 = STPWi + {5, OperandInfo349}, // Inst #5080 = STPWpost + {5, OperandInfo349}, // Inst #5081 = STPWpre + {4, OperandInfo343}, // Inst #5082 = STPXi + {5, OperandInfo347}, // Inst #5083 = STPXpost + {5, OperandInfo347}, // Inst #5084 = STPXpre + {4, OperandInfo351}, // Inst #5085 = STRBBpost + {4, OperandInfo351}, // Inst #5086 = STRBBpre + {5, OperandInfo352}, // Inst #5087 = STRBBroW + {5, OperandInfo353}, // Inst #5088 = STRBBroX + {3, OperandInfo337}, // Inst #5089 = STRBBui + {4, OperandInfo354}, // Inst #5090 = STRBpost + {4, OperandInfo354}, // Inst #5091 = STRBpre + {5, OperandInfo355}, // Inst #5092 = STRBroW + {5, OperandInfo356}, // Inst #5093 = STRBroX + {3, OperandInfo357}, // Inst #5094 = STRBui + {4, OperandInfo359}, // Inst #5095 = STRDpost + {4, OperandInfo359}, // Inst #5096 = STRDpre + {5, OperandInfo360}, // Inst #5097 = STRDroW + {5, OperandInfo361}, // Inst #5098 = STRDroX + {3, OperandInfo362}, // Inst #5099 = STRDui + {4, OperandInfo351}, // Inst #5100 = STRHHpost + {4, OperandInfo351}, // Inst #5101 = STRHHpre + {5, OperandInfo352}, // Inst #5102 = STRHHroW + {5, OperandInfo353}, // Inst #5103 = STRHHroX + {3, OperandInfo337}, // Inst #5104 = STRHHui + {4, OperandInfo363}, // Inst #5105 = STRHpost + {4, OperandInfo363}, // Inst #5106 = STRHpre + {5, OperandInfo364}, // Inst #5107 = STRHroW + {5, OperandInfo365}, // Inst #5108 = STRHroX + {3, OperandInfo366}, // Inst #5109 = STRHui + {4, OperandInfo368}, // Inst #5110 = STRQpost + {4, OperandInfo368}, // Inst #5111 = STRQpre + {5, OperandInfo369}, // Inst #5112 = STRQroW + {5, OperandInfo370}, // Inst #5113 = STRQroX + {3, OperandInfo371}, // Inst #5114 = STRQui + {4, OperandInfo375}, // Inst #5115 = STRSpost + {4, OperandInfo375}, // Inst #5116 = STRSpre + {5, OperandInfo376}, // Inst #5117 = STRSroW + {5, OperandInfo377}, // Inst #5118 = STRSroX + {3, OperandInfo378}, // Inst #5119 = STRSui + {4, OperandInfo351}, // Inst #5120 = STRWpost + {4, OperandInfo351}, // Inst #5121 = STRWpre + {5, OperandInfo352}, // Inst #5122 = STRWroW + {5, OperandInfo353}, // Inst #5123 = STRWroX + {3, OperandInfo337}, // Inst #5124 = STRWui + {4, OperandInfo350}, // Inst #5125 = STRXpost + {4, OperandInfo350}, // Inst #5126 = STRXpre + {5, OperandInfo372}, // Inst #5127 = STRXroW + {5, OperandInfo373}, // Inst #5128 = STRXroX + {3, OperandInfo85}, // Inst #5129 = STRXui + {3, OperandInfo379}, // Inst #5130 = STR_PXI + {5, OperandInfo380}, // Inst #5131 = STR_ZA + {3, OperandInfo381}, // Inst #5132 = STR_ZXI + {3, OperandInfo337}, // Inst #5133 = STTRBi + {3, OperandInfo337}, // Inst #5134 = STTRHi + {3, OperandInfo337}, // Inst #5135 = STTRWi + {3, OperandInfo85}, // Inst #5136 = STTRXi + {3, OperandInfo337}, // Inst #5137 = STURBBi + {3, OperandInfo357}, // Inst #5138 = STURBi + {3, OperandInfo362}, // Inst #5139 = STURDi + {3, OperandInfo337}, // Inst #5140 = STURHHi + {3, OperandInfo366}, // Inst #5141 = STURHi + {3, OperandInfo371}, // Inst #5142 = STURQi + {3, OperandInfo378}, // Inst #5143 = STURSi + {3, OperandInfo337}, // Inst #5144 = STURWi + {3, OperandInfo85}, // Inst #5145 = STURXi + {4, OperandInfo451}, // Inst #5146 = STXPW + {4, OperandInfo452}, // Inst #5147 = STXPX + {3, OperandInfo453}, // Inst #5148 = STXRB + {3, OperandInfo453}, // Inst #5149 = STXRH + {3, OperandInfo453}, // Inst #5150 = STXRW + {3, OperandInfo454}, // Inst #5151 = STXRX + {3, OperandInfo99}, // Inst #5152 = STZ2GOffset + {4, OperandInfo443}, // Inst #5153 = STZ2GPostIndex + {4, OperandInfo443}, // Inst #5154 = STZ2GPreIndex + {2, OperandInfo148}, // Inst #5155 = STZGM + {3, OperandInfo99}, // Inst #5156 = STZGOffset + {4, OperandInfo443}, // Inst #5157 = STZGPostIndex + {4, OperandInfo443}, // Inst #5158 = STZGPreIndex + {4, OperandInfo93}, // Inst #5159 = SUBG + {3, OperandInfo96}, // Inst #5160 = SUBHNB_ZZZ_B + {3, OperandInfo96}, // Inst #5161 = SUBHNB_ZZZ_H + {3, OperandInfo96}, // Inst #5162 = SUBHNB_ZZZ_S + {4, OperandInfo92}, // Inst #5163 = SUBHNT_ZZZ_B + {4, OperandInfo92}, // Inst #5164 = SUBHNT_ZZZ_H + {4, OperandInfo92}, // Inst #5165 = SUBHNT_ZZZ_S + {3, OperandInfo97}, // Inst #5166 = SUBHNv2i64_v2i32 + {4, OperandInfo98}, // Inst #5167 = SUBHNv2i64_v4i32 + {3, OperandInfo97}, // Inst #5168 = SUBHNv4i32_v4i16 + {4, OperandInfo98}, // Inst #5169 = SUBHNv4i32_v8i16 + {4, OperandInfo98}, // Inst #5170 = SUBHNv8i16_v16i8 + {3, OperandInfo97}, // Inst #5171 = SUBHNv8i16_v8i8 + {3, OperandInfo455}, // Inst #5172 = SUBP + {3, OperandInfo455}, // Inst #5173 = SUBPS + {4, OperandInfo120}, // Inst #5174 = SUBR_ZI_B + {4, OperandInfo120}, // Inst #5175 = SUBR_ZI_D + {4, OperandInfo120}, // Inst #5176 = SUBR_ZI_H + {4, OperandInfo120}, // Inst #5177 = SUBR_ZI_S + {4, OperandInfo100}, // Inst #5178 = SUBR_ZPmZ_B + {4, OperandInfo100}, // Inst #5179 = SUBR_ZPmZ_D + {4, OperandInfo100}, // Inst #5180 = SUBR_ZPmZ_H + {4, OperandInfo100}, // Inst #5181 = SUBR_ZPmZ_S + {4, OperandInfo104}, // Inst #5182 = SUBSWri + {4, OperandInfo105}, // Inst #5183 = SUBSWrs + {4, OperandInfo106}, // Inst #5184 = SUBSWrx + {4, OperandInfo107}, // Inst #5185 = SUBSXri + {4, OperandInfo108}, // Inst #5186 = SUBSXrs + {4, OperandInfo109}, // Inst #5187 = SUBSXrx + {4, OperandInfo110}, // Inst #5188 = SUBSXrx64 + {4, OperandInfo116}, // Inst #5189 = SUBWri + {4, OperandInfo105}, // Inst #5190 = SUBWrs + {4, OperandInfo117}, // Inst #5191 = SUBWrx + {4, OperandInfo93}, // Inst #5192 = SUBXri + {4, OperandInfo108}, // Inst #5193 = SUBXrs + {4, OperandInfo118}, // Inst #5194 = SUBXrx + {4, OperandInfo119}, // Inst #5195 = SUBXrx64 + {4, OperandInfo120}, // Inst #5196 = SUB_ZI_B + {4, OperandInfo120}, // Inst #5197 = SUB_ZI_D + {4, OperandInfo120}, // Inst #5198 = SUB_ZI_H + {4, OperandInfo120}, // Inst #5199 = SUB_ZI_S + {4, OperandInfo100}, // Inst #5200 = SUB_ZPmZ_B + {4, OperandInfo100}, // Inst #5201 = SUB_ZPmZ_D + {4, OperandInfo100}, // Inst #5202 = SUB_ZPmZ_H + {4, OperandInfo100}, // Inst #5203 = SUB_ZPmZ_S + {3, OperandInfo96}, // Inst #5204 = SUB_ZZZ_B + {3, OperandInfo96}, // Inst #5205 = SUB_ZZZ_D + {3, OperandInfo96}, // Inst #5206 = SUB_ZZZ_H + {3, OperandInfo96}, // Inst #5207 = SUB_ZZZ_S + {3, OperandInfo101}, // Inst #5208 = SUBv16i8 + {3, OperandInfo102}, // Inst #5209 = SUBv1i64 + {3, OperandInfo102}, // Inst #5210 = SUBv2i32 + {3, OperandInfo101}, // Inst #5211 = SUBv2i64 + {3, OperandInfo102}, // Inst #5212 = SUBv4i16 + {3, OperandInfo101}, // Inst #5213 = SUBv4i32 + {3, OperandInfo101}, // Inst #5214 = SUBv8i16 + {3, OperandInfo102}, // Inst #5215 = SUBv8i8 + {5, OperandInfo141}, // Inst #5216 = SUDOT_ZZZI + {5, OperandInfo139}, // Inst #5217 = SUDOTlanev16i8 + {5, OperandInfo138}, // Inst #5218 = SUDOTlanev8i8 + {5, OperandInfo255}, // Inst #5219 = SUMOPA_MPPZZ_D + {5, OperandInfo256}, // Inst #5220 = SUMOPA_MPPZZ_S + {5, OperandInfo255}, // Inst #5221 = SUMOPS_MPPZZ_D + {5, OperandInfo256}, // Inst #5222 = SUMOPS_MPPZZ_S + {2, OperandInfo247}, // Inst #5223 = SUNPKHI_ZZ_D + {2, OperandInfo247}, // Inst #5224 = SUNPKHI_ZZ_H + {2, OperandInfo247}, // Inst #5225 = SUNPKHI_ZZ_S + {2, OperandInfo247}, // Inst #5226 = SUNPKLO_ZZ_D + {2, OperandInfo247}, // Inst #5227 = SUNPKLO_ZZ_H + {2, OperandInfo247}, // Inst #5228 = SUNPKLO_ZZ_S + {4, OperandInfo100}, // Inst #5229 = SUQADD_ZPmZ_B + {4, OperandInfo100}, // Inst #5230 = SUQADD_ZPmZ_D + {4, OperandInfo100}, // Inst #5231 = SUQADD_ZPmZ_H + {4, OperandInfo100}, // Inst #5232 = SUQADD_ZPmZ_S + {3, OperandInfo124}, // Inst #5233 = SUQADDv16i8 + {3, OperandInfo456}, // Inst #5234 = SUQADDv1i16 + {3, OperandInfo457}, // Inst #5235 = SUQADDv1i32 + {3, OperandInfo402}, // Inst #5236 = SUQADDv1i64 + {3, OperandInfo458}, // Inst #5237 = SUQADDv1i8 + {3, OperandInfo402}, // Inst #5238 = SUQADDv2i32 + {3, OperandInfo124}, // Inst #5239 = SUQADDv2i64 + {3, OperandInfo402}, // Inst #5240 = SUQADDv4i16 + {3, OperandInfo124}, // Inst #5241 = SUQADDv4i32 + {3, OperandInfo124}, // Inst #5242 = SUQADDv8i16 + {3, OperandInfo402}, // Inst #5243 = SUQADDv8i8 + {1, OperandInfo2}, // Inst #5244 = SVC + {3, OperandInfo334}, // Inst #5245 = SWPAB + {3, OperandInfo334}, // Inst #5246 = SWPAH + {3, OperandInfo334}, // Inst #5247 = SWPALB + {3, OperandInfo334}, // Inst #5248 = SWPALH + {3, OperandInfo334}, // Inst #5249 = SWPALW + {3, OperandInfo335}, // Inst #5250 = SWPALX + {3, OperandInfo334}, // Inst #5251 = SWPAW + {3, OperandInfo335}, // Inst #5252 = SWPAX + {3, OperandInfo334}, // Inst #5253 = SWPB + {3, OperandInfo334}, // Inst #5254 = SWPH + {3, OperandInfo334}, // Inst #5255 = SWPLB + {3, OperandInfo334}, // Inst #5256 = SWPLH + {3, OperandInfo334}, // Inst #5257 = SWPLW + {3, OperandInfo335}, // Inst #5258 = SWPLX + {3, OperandInfo334}, // Inst #5259 = SWPW + {3, OperandInfo335}, // Inst #5260 = SWPX + {4, OperandInfo89}, // Inst #5261 = SXTB_ZPmZ_D + {4, OperandInfo89}, // Inst #5262 = SXTB_ZPmZ_H + {4, OperandInfo89}, // Inst #5263 = SXTB_ZPmZ_S + {4, OperandInfo89}, // Inst #5264 = SXTH_ZPmZ_D + {4, OperandInfo89}, // Inst #5265 = SXTH_ZPmZ_S + {4, OperandInfo89}, // Inst #5266 = SXTW_ZPmZ_D + {5, OperandInfo459}, // Inst #5267 = SYSLxt + {5, OperandInfo460}, // Inst #5268 = SYSxt + {3, OperandInfo461}, // Inst #5269 = TBL_ZZZZ_B + {3, OperandInfo461}, // Inst #5270 = TBL_ZZZZ_D + {3, OperandInfo461}, // Inst #5271 = TBL_ZZZZ_H + {3, OperandInfo461}, // Inst #5272 = TBL_ZZZZ_S + {3, OperandInfo96}, // Inst #5273 = TBL_ZZZ_B + {3, OperandInfo96}, // Inst #5274 = TBL_ZZZ_D + {3, OperandInfo96}, // Inst #5275 = TBL_ZZZ_H + {3, OperandInfo96}, // Inst #5276 = TBL_ZZZ_S + {3, OperandInfo462}, // Inst #5277 = TBLv16i8Four + {3, OperandInfo101}, // Inst #5278 = TBLv16i8One + {3, OperandInfo463}, // Inst #5279 = TBLv16i8Three + {3, OperandInfo464}, // Inst #5280 = TBLv16i8Two + {3, OperandInfo465}, // Inst #5281 = TBLv8i8Four + {3, OperandInfo466}, // Inst #5282 = TBLv8i8One + {3, OperandInfo467}, // Inst #5283 = TBLv8i8Three + {3, OperandInfo468}, // Inst #5284 = TBLv8i8Two + {3, OperandInfo469}, // Inst #5285 = TBNZW + {3, OperandInfo470}, // Inst #5286 = TBNZX + {4, OperandInfo92}, // Inst #5287 = TBX_ZZZ_B + {4, OperandInfo92}, // Inst #5288 = TBX_ZZZ_D + {4, OperandInfo92}, // Inst #5289 = TBX_ZZZ_H + {4, OperandInfo92}, // Inst #5290 = TBX_ZZZ_S + {4, OperandInfo471}, // Inst #5291 = TBXv16i8Four + {4, OperandInfo98}, // Inst #5292 = TBXv16i8One + {4, OperandInfo472}, // Inst #5293 = TBXv16i8Three + {4, OperandInfo473}, // Inst #5294 = TBXv16i8Two + {4, OperandInfo474}, // Inst #5295 = TBXv8i8Four + {4, OperandInfo475}, // Inst #5296 = TBXv8i8One + {4, OperandInfo476}, // Inst #5297 = TBXv8i8Three + {4, OperandInfo477}, // Inst #5298 = TBXv8i8Two + {3, OperandInfo469}, // Inst #5299 = TBZW + {3, OperandInfo470}, // Inst #5300 = TBZX + {1, OperandInfo2}, // Inst #5301 = TCANCEL + {0, NULL}, // Inst #5302 = TCOMMIT + {3, OperandInfo149}, // Inst #5303 = TRN1_PPP_B + {3, OperandInfo149}, // Inst #5304 = TRN1_PPP_D + {3, OperandInfo149}, // Inst #5305 = TRN1_PPP_H + {3, OperandInfo149}, // Inst #5306 = TRN1_PPP_S + {3, OperandInfo96}, // Inst #5307 = TRN1_ZZZ_B + {3, OperandInfo96}, // Inst #5308 = TRN1_ZZZ_D + {3, OperandInfo96}, // Inst #5309 = TRN1_ZZZ_H + {3, OperandInfo96}, // Inst #5310 = TRN1_ZZZ_Q + {3, OperandInfo96}, // Inst #5311 = TRN1_ZZZ_S + {3, OperandInfo101}, // Inst #5312 = TRN1v16i8 + {3, OperandInfo102}, // Inst #5313 = TRN1v2i32 + {3, OperandInfo101}, // Inst #5314 = TRN1v2i64 + {3, OperandInfo102}, // Inst #5315 = TRN1v4i16 + {3, OperandInfo101}, // Inst #5316 = TRN1v4i32 + {3, OperandInfo101}, // Inst #5317 = TRN1v8i16 + {3, OperandInfo102}, // Inst #5318 = TRN1v8i8 + {3, OperandInfo149}, // Inst #5319 = TRN2_PPP_B + {3, OperandInfo149}, // Inst #5320 = TRN2_PPP_D + {3, OperandInfo149}, // Inst #5321 = TRN2_PPP_H + {3, OperandInfo149}, // Inst #5322 = TRN2_PPP_S + {3, OperandInfo96}, // Inst #5323 = TRN2_ZZZ_B + {3, OperandInfo96}, // Inst #5324 = TRN2_ZZZ_D + {3, OperandInfo96}, // Inst #5325 = TRN2_ZZZ_H + {3, OperandInfo96}, // Inst #5326 = TRN2_ZZZ_Q + {3, OperandInfo96}, // Inst #5327 = TRN2_ZZZ_S + {3, OperandInfo101}, // Inst #5328 = TRN2v16i8 + {3, OperandInfo102}, // Inst #5329 = TRN2v2i32 + {3, OperandInfo101}, // Inst #5330 = TRN2v2i64 + {3, OperandInfo102}, // Inst #5331 = TRN2v4i16 + {3, OperandInfo101}, // Inst #5332 = TRN2v4i32 + {3, OperandInfo101}, // Inst #5333 = TRN2v8i16 + {3, OperandInfo102}, // Inst #5334 = TRN2v8i8 + {1, OperandInfo2}, // Inst #5335 = TSB + {1, OperandInfo75}, // Inst #5336 = TSTART + {1, OperandInfo75}, // Inst #5337 = TTEST + {4, OperandInfo92}, // Inst #5338 = UABALB_ZZZ_D + {4, OperandInfo92}, // Inst #5339 = UABALB_ZZZ_H + {4, OperandInfo92}, // Inst #5340 = UABALB_ZZZ_S + {4, OperandInfo92}, // Inst #5341 = UABALT_ZZZ_D + {4, OperandInfo92}, // Inst #5342 = UABALT_ZZZ_H + {4, OperandInfo92}, // Inst #5343 = UABALT_ZZZ_S + {4, OperandInfo98}, // Inst #5344 = UABALv16i8_v8i16 + {4, OperandInfo401}, // Inst #5345 = UABALv2i32_v2i64 + {4, OperandInfo401}, // Inst #5346 = UABALv4i16_v4i32 + {4, OperandInfo98}, // Inst #5347 = UABALv4i32_v2i64 + {4, OperandInfo98}, // Inst #5348 = UABALv8i16_v4i32 + {4, OperandInfo401}, // Inst #5349 = UABALv8i8_v8i16 + {4, OperandInfo92}, // Inst #5350 = UABA_ZZZ_B + {4, OperandInfo92}, // Inst #5351 = UABA_ZZZ_D + {4, OperandInfo92}, // Inst #5352 = UABA_ZZZ_H + {4, OperandInfo92}, // Inst #5353 = UABA_ZZZ_S + {4, OperandInfo98}, // Inst #5354 = UABAv16i8 + {4, OperandInfo142}, // Inst #5355 = UABAv2i32 + {4, OperandInfo142}, // Inst #5356 = UABAv4i16 + {4, OperandInfo98}, // Inst #5357 = UABAv4i32 + {4, OperandInfo98}, // Inst #5358 = UABAv8i16 + {4, OperandInfo142}, // Inst #5359 = UABAv8i8 + {3, OperandInfo96}, // Inst #5360 = UABDLB_ZZZ_D + {3, OperandInfo96}, // Inst #5361 = UABDLB_ZZZ_H + {3, OperandInfo96}, // Inst #5362 = UABDLB_ZZZ_S + {3, OperandInfo96}, // Inst #5363 = UABDLT_ZZZ_D + {3, OperandInfo96}, // Inst #5364 = UABDLT_ZZZ_H + {3, OperandInfo96}, // Inst #5365 = UABDLT_ZZZ_S + {3, OperandInfo101}, // Inst #5366 = UABDLv16i8_v8i16 + {3, OperandInfo390}, // Inst #5367 = UABDLv2i32_v2i64 + {3, OperandInfo390}, // Inst #5368 = UABDLv4i16_v4i32 + {3, OperandInfo101}, // Inst #5369 = UABDLv4i32_v2i64 + {3, OperandInfo101}, // Inst #5370 = UABDLv8i16_v4i32 + {3, OperandInfo390}, // Inst #5371 = UABDLv8i8_v8i16 + {4, OperandInfo100}, // Inst #5372 = UABD_ZPmZ_B + {4, OperandInfo100}, // Inst #5373 = UABD_ZPmZ_D + {4, OperandInfo100}, // Inst #5374 = UABD_ZPmZ_H + {4, OperandInfo100}, // Inst #5375 = UABD_ZPmZ_S + {3, OperandInfo101}, // Inst #5376 = UABDv16i8 + {3, OperandInfo102}, // Inst #5377 = UABDv2i32 + {3, OperandInfo102}, // Inst #5378 = UABDv4i16 + {3, OperandInfo101}, // Inst #5379 = UABDv4i32 + {3, OperandInfo101}, // Inst #5380 = UABDv8i16 + {3, OperandInfo102}, // Inst #5381 = UABDv8i8 + {4, OperandInfo100}, // Inst #5382 = UADALP_ZPmZ_D + {4, OperandInfo100}, // Inst #5383 = UADALP_ZPmZ_H + {4, OperandInfo100}, // Inst #5384 = UADALP_ZPmZ_S + {3, OperandInfo124}, // Inst #5385 = UADALPv16i8_v8i16 + {3, OperandInfo402}, // Inst #5386 = UADALPv2i32_v1i64 + {3, OperandInfo402}, // Inst #5387 = UADALPv4i16_v2i32 + {3, OperandInfo124}, // Inst #5388 = UADALPv4i32_v2i64 + {3, OperandInfo124}, // Inst #5389 = UADALPv8i16_v4i32 + {3, OperandInfo402}, // Inst #5390 = UADALPv8i8_v4i16 + {3, OperandInfo96}, // Inst #5391 = UADDLB_ZZZ_D + {3, OperandInfo96}, // Inst #5392 = UADDLB_ZZZ_H + {3, OperandInfo96}, // Inst #5393 = UADDLB_ZZZ_S + {2, OperandInfo90}, // Inst #5394 = UADDLPv16i8_v8i16 + {2, OperandInfo91}, // Inst #5395 = UADDLPv2i32_v1i64 + {2, OperandInfo91}, // Inst #5396 = UADDLPv4i16_v2i32 + {2, OperandInfo90}, // Inst #5397 = UADDLPv4i32_v2i64 + {2, OperandInfo90}, // Inst #5398 = UADDLPv8i16_v4i32 + {2, OperandInfo91}, // Inst #5399 = UADDLPv8i8_v4i16 + {3, OperandInfo96}, // Inst #5400 = UADDLT_ZZZ_D + {3, OperandInfo96}, // Inst #5401 = UADDLT_ZZZ_H + {3, OperandInfo96}, // Inst #5402 = UADDLT_ZZZ_S + {2, OperandInfo114}, // Inst #5403 = UADDLVv16i8v + {2, OperandInfo214}, // Inst #5404 = UADDLVv4i16v + {2, OperandInfo103}, // Inst #5405 = UADDLVv4i32v + {2, OperandInfo113}, // Inst #5406 = UADDLVv8i16v + {2, OperandInfo112}, // Inst #5407 = UADDLVv8i8v + {3, OperandInfo101}, // Inst #5408 = UADDLv16i8_v8i16 + {3, OperandInfo390}, // Inst #5409 = UADDLv2i32_v2i64 + {3, OperandInfo390}, // Inst #5410 = UADDLv4i16_v4i32 + {3, OperandInfo101}, // Inst #5411 = UADDLv4i32_v2i64 + {3, OperandInfo101}, // Inst #5412 = UADDLv8i16_v4i32 + {3, OperandInfo390}, // Inst #5413 = UADDLv8i8_v8i16 + {3, OperandInfo129}, // Inst #5414 = UADDV_VPZ_B + {3, OperandInfo129}, // Inst #5415 = UADDV_VPZ_D + {3, OperandInfo129}, // Inst #5416 = UADDV_VPZ_H + {3, OperandInfo129}, // Inst #5417 = UADDV_VPZ_S + {3, OperandInfo96}, // Inst #5418 = UADDWB_ZZZ_D + {3, OperandInfo96}, // Inst #5419 = UADDWB_ZZZ_H + {3, OperandInfo96}, // Inst #5420 = UADDWB_ZZZ_S + {3, OperandInfo96}, // Inst #5421 = UADDWT_ZZZ_D + {3, OperandInfo96}, // Inst #5422 = UADDWT_ZZZ_H + {3, OperandInfo96}, // Inst #5423 = UADDWT_ZZZ_S + {3, OperandInfo101}, // Inst #5424 = UADDWv16i8_v8i16 + {3, OperandInfo403}, // Inst #5425 = UADDWv2i32_v2i64 + {3, OperandInfo403}, // Inst #5426 = UADDWv4i16_v4i32 + {3, OperandInfo101}, // Inst #5427 = UADDWv4i32_v2i64 + {3, OperandInfo101}, // Inst #5428 = UADDWv8i16_v4i32 + {3, OperandInfo403}, // Inst #5429 = UADDWv8i8_v8i16 + {4, OperandInfo160}, // Inst #5430 = UBFMWri + {4, OperandInfo162}, // Inst #5431 = UBFMXri + {4, OperandInfo404}, // Inst #5432 = UCLAMP_ZZZ_B + {4, OperandInfo404}, // Inst #5433 = UCLAMP_ZZZ_D + {4, OperandInfo404}, // Inst #5434 = UCLAMP_ZZZ_H + {4, OperandInfo404}, // Inst #5435 = UCLAMP_ZZZ_S + {3, OperandInfo405}, // Inst #5436 = UCVTFSWDri + {3, OperandInfo406}, // Inst #5437 = UCVTFSWHri + {3, OperandInfo407}, // Inst #5438 = UCVTFSWSri + {3, OperandInfo408}, // Inst #5439 = UCVTFSXDri + {3, OperandInfo409}, // Inst #5440 = UCVTFSXHri + {3, OperandInfo410}, // Inst #5441 = UCVTFSXSri + {2, OperandInfo200}, // Inst #5442 = UCVTFUWDri + {2, OperandInfo261}, // Inst #5443 = UCVTFUWHri + {2, OperandInfo262}, // Inst #5444 = UCVTFUWSri + {2, OperandInfo264}, // Inst #5445 = UCVTFUXDri + {2, OperandInfo265}, // Inst #5446 = UCVTFUXHri + {2, OperandInfo411}, // Inst #5447 = UCVTFUXSri + {4, OperandInfo89}, // Inst #5448 = UCVTF_ZPmZ_DtoD + {4, OperandInfo89}, // Inst #5449 = UCVTF_ZPmZ_DtoH + {4, OperandInfo89}, // Inst #5450 = UCVTF_ZPmZ_DtoS + {4, OperandInfo89}, // Inst #5451 = UCVTF_ZPmZ_HtoH + {4, OperandInfo89}, // Inst #5452 = UCVTF_ZPmZ_StoD + {4, OperandInfo89}, // Inst #5453 = UCVTF_ZPmZ_StoH + {4, OperandInfo89}, // Inst #5454 = UCVTF_ZPmZ_StoS + {3, OperandInfo244}, // Inst #5455 = UCVTFd + {3, OperandInfo245}, // Inst #5456 = UCVTFh + {3, OperandInfo246}, // Inst #5457 = UCVTFs + {2, OperandInfo212}, // Inst #5458 = UCVTFv1i16 + {2, OperandInfo213}, // Inst #5459 = UCVTFv1i32 + {2, OperandInfo91}, // Inst #5460 = UCVTFv1i64 + {2, OperandInfo91}, // Inst #5461 = UCVTFv2f32 + {2, OperandInfo90}, // Inst #5462 = UCVTFv2f64 + {3, OperandInfo244}, // Inst #5463 = UCVTFv2i32_shift + {3, OperandInfo199}, // Inst #5464 = UCVTFv2i64_shift + {2, OperandInfo91}, // Inst #5465 = UCVTFv4f16 + {2, OperandInfo90}, // Inst #5466 = UCVTFv4f32 + {3, OperandInfo244}, // Inst #5467 = UCVTFv4i16_shift + {3, OperandInfo199}, // Inst #5468 = UCVTFv4i32_shift + {2, OperandInfo90}, // Inst #5469 = UCVTFv8f16 + {3, OperandInfo199}, // Inst #5470 = UCVTFv8i16_shift + {1, OperandInfo2}, // Inst #5471 = UDF + {4, OperandInfo100}, // Inst #5472 = UDIVR_ZPmZ_D + {4, OperandInfo100}, // Inst #5473 = UDIVR_ZPmZ_S + {3, OperandInfo45}, // Inst #5474 = UDIVWr + {3, OperandInfo46}, // Inst #5475 = UDIVXr + {4, OperandInfo100}, // Inst #5476 = UDIV_ZPmZ_D + {4, OperandInfo100}, // Inst #5477 = UDIV_ZPmZ_S + {5, OperandInfo251}, // Inst #5478 = UDOT_ZZZI_D + {5, OperandInfo141}, // Inst #5479 = UDOT_ZZZI_S + {4, OperandInfo92}, // Inst #5480 = UDOT_ZZZ_D + {4, OperandInfo92}, // Inst #5481 = UDOT_ZZZ_S + {5, OperandInfo139}, // Inst #5482 = UDOTlanev16i8 + {5, OperandInfo138}, // Inst #5483 = UDOTlanev8i8 + {4, OperandInfo98}, // Inst #5484 = UDOTv16i8 + {4, OperandInfo142}, // Inst #5485 = UDOTv8i8 + {4, OperandInfo100}, // Inst #5486 = UHADD_ZPmZ_B + {4, OperandInfo100}, // Inst #5487 = UHADD_ZPmZ_D + {4, OperandInfo100}, // Inst #5488 = UHADD_ZPmZ_H + {4, OperandInfo100}, // Inst #5489 = UHADD_ZPmZ_S + {3, OperandInfo101}, // Inst #5490 = UHADDv16i8 + {3, OperandInfo102}, // Inst #5491 = UHADDv2i32 + {3, OperandInfo102}, // Inst #5492 = UHADDv4i16 + {3, OperandInfo101}, // Inst #5493 = UHADDv4i32 + {3, OperandInfo101}, // Inst #5494 = UHADDv8i16 + {3, OperandInfo102}, // Inst #5495 = UHADDv8i8 + {4, OperandInfo100}, // Inst #5496 = UHSUBR_ZPmZ_B + {4, OperandInfo100}, // Inst #5497 = UHSUBR_ZPmZ_D + {4, OperandInfo100}, // Inst #5498 = UHSUBR_ZPmZ_H + {4, OperandInfo100}, // Inst #5499 = UHSUBR_ZPmZ_S + {4, OperandInfo100}, // Inst #5500 = UHSUB_ZPmZ_B + {4, OperandInfo100}, // Inst #5501 = UHSUB_ZPmZ_D + {4, OperandInfo100}, // Inst #5502 = UHSUB_ZPmZ_H + {4, OperandInfo100}, // Inst #5503 = UHSUB_ZPmZ_S + {3, OperandInfo101}, // Inst #5504 = UHSUBv16i8 + {3, OperandInfo102}, // Inst #5505 = UHSUBv2i32 + {3, OperandInfo102}, // Inst #5506 = UHSUBv4i16 + {3, OperandInfo101}, // Inst #5507 = UHSUBv4i32 + {3, OperandInfo101}, // Inst #5508 = UHSUBv8i16 + {3, OperandInfo102}, // Inst #5509 = UHSUBv8i8 + {4, OperandInfo416}, // Inst #5510 = UMADDLrrr + {4, OperandInfo100}, // Inst #5511 = UMAXP_ZPmZ_B + {4, OperandInfo100}, // Inst #5512 = UMAXP_ZPmZ_D + {4, OperandInfo100}, // Inst #5513 = UMAXP_ZPmZ_H + {4, OperandInfo100}, // Inst #5514 = UMAXP_ZPmZ_S + {3, OperandInfo101}, // Inst #5515 = UMAXPv16i8 + {3, OperandInfo102}, // Inst #5516 = UMAXPv2i32 + {3, OperandInfo102}, // Inst #5517 = UMAXPv4i16 + {3, OperandInfo101}, // Inst #5518 = UMAXPv4i32 + {3, OperandInfo101}, // Inst #5519 = UMAXPv8i16 + {3, OperandInfo102}, // Inst #5520 = UMAXPv8i8 + {3, OperandInfo129}, // Inst #5521 = UMAXV_VPZ_B + {3, OperandInfo129}, // Inst #5522 = UMAXV_VPZ_D + {3, OperandInfo129}, // Inst #5523 = UMAXV_VPZ_H + {3, OperandInfo129}, // Inst #5524 = UMAXV_VPZ_S + {2, OperandInfo111}, // Inst #5525 = UMAXVv16i8v + {2, OperandInfo112}, // Inst #5526 = UMAXVv4i16v + {2, OperandInfo113}, // Inst #5527 = UMAXVv4i32v + {2, OperandInfo114}, // Inst #5528 = UMAXVv8i16v + {2, OperandInfo115}, // Inst #5529 = UMAXVv8i8v + {3, OperandInfo132}, // Inst #5530 = UMAX_ZI_B + {3, OperandInfo132}, // Inst #5531 = UMAX_ZI_D + {3, OperandInfo132}, // Inst #5532 = UMAX_ZI_H + {3, OperandInfo132}, // Inst #5533 = UMAX_ZI_S + {4, OperandInfo100}, // Inst #5534 = UMAX_ZPmZ_B + {4, OperandInfo100}, // Inst #5535 = UMAX_ZPmZ_D + {4, OperandInfo100}, // Inst #5536 = UMAX_ZPmZ_H + {4, OperandInfo100}, // Inst #5537 = UMAX_ZPmZ_S + {3, OperandInfo101}, // Inst #5538 = UMAXv16i8 + {3, OperandInfo102}, // Inst #5539 = UMAXv2i32 + {3, OperandInfo102}, // Inst #5540 = UMAXv4i16 + {3, OperandInfo101}, // Inst #5541 = UMAXv4i32 + {3, OperandInfo101}, // Inst #5542 = UMAXv8i16 + {3, OperandInfo102}, // Inst #5543 = UMAXv8i8 + {4, OperandInfo100}, // Inst #5544 = UMINP_ZPmZ_B + {4, OperandInfo100}, // Inst #5545 = UMINP_ZPmZ_D + {4, OperandInfo100}, // Inst #5546 = UMINP_ZPmZ_H + {4, OperandInfo100}, // Inst #5547 = UMINP_ZPmZ_S + {3, OperandInfo101}, // Inst #5548 = UMINPv16i8 + {3, OperandInfo102}, // Inst #5549 = UMINPv2i32 + {3, OperandInfo102}, // Inst #5550 = UMINPv4i16 + {3, OperandInfo101}, // Inst #5551 = UMINPv4i32 + {3, OperandInfo101}, // Inst #5552 = UMINPv8i16 + {3, OperandInfo102}, // Inst #5553 = UMINPv8i8 + {3, OperandInfo129}, // Inst #5554 = UMINV_VPZ_B + {3, OperandInfo129}, // Inst #5555 = UMINV_VPZ_D + {3, OperandInfo129}, // Inst #5556 = UMINV_VPZ_H + {3, OperandInfo129}, // Inst #5557 = UMINV_VPZ_S + {2, OperandInfo111}, // Inst #5558 = UMINVv16i8v + {2, OperandInfo112}, // Inst #5559 = UMINVv4i16v + {2, OperandInfo113}, // Inst #5560 = UMINVv4i32v + {2, OperandInfo114}, // Inst #5561 = UMINVv8i16v + {2, OperandInfo115}, // Inst #5562 = UMINVv8i8v + {3, OperandInfo132}, // Inst #5563 = UMIN_ZI_B + {3, OperandInfo132}, // Inst #5564 = UMIN_ZI_D + {3, OperandInfo132}, // Inst #5565 = UMIN_ZI_H + {3, OperandInfo132}, // Inst #5566 = UMIN_ZI_S + {4, OperandInfo100}, // Inst #5567 = UMIN_ZPmZ_B + {4, OperandInfo100}, // Inst #5568 = UMIN_ZPmZ_D + {4, OperandInfo100}, // Inst #5569 = UMIN_ZPmZ_H + {4, OperandInfo100}, // Inst #5570 = UMIN_ZPmZ_S + {3, OperandInfo101}, // Inst #5571 = UMINv16i8 + {3, OperandInfo102}, // Inst #5572 = UMINv2i32 + {3, OperandInfo102}, // Inst #5573 = UMINv4i16 + {3, OperandInfo101}, // Inst #5574 = UMINv4i32 + {3, OperandInfo101}, // Inst #5575 = UMINv8i16 + {3, OperandInfo102}, // Inst #5576 = UMINv8i8 + {5, OperandInfo251}, // Inst #5577 = UMLALB_ZZZI_D + {5, OperandInfo141}, // Inst #5578 = UMLALB_ZZZI_S + {4, OperandInfo92}, // Inst #5579 = UMLALB_ZZZ_D + {4, OperandInfo92}, // Inst #5580 = UMLALB_ZZZ_H + {4, OperandInfo92}, // Inst #5581 = UMLALB_ZZZ_S + {5, OperandInfo251}, // Inst #5582 = UMLALT_ZZZI_D + {5, OperandInfo141}, // Inst #5583 = UMLALT_ZZZI_S + {4, OperandInfo92}, // Inst #5584 = UMLALT_ZZZ_D + {4, OperandInfo92}, // Inst #5585 = UMLALT_ZZZ_H + {4, OperandInfo92}, // Inst #5586 = UMLALT_ZZZ_S + {4, OperandInfo98}, // Inst #5587 = UMLALv16i8_v8i16 + {5, OperandInfo417}, // Inst #5588 = UMLALv2i32_indexed + {4, OperandInfo401}, // Inst #5589 = UMLALv2i32_v2i64 + {5, OperandInfo418}, // Inst #5590 = UMLALv4i16_indexed + {4, OperandInfo401}, // Inst #5591 = UMLALv4i16_v4i32 + {5, OperandInfo139}, // Inst #5592 = UMLALv4i32_indexed + {4, OperandInfo98}, // Inst #5593 = UMLALv4i32_v2i64 + {5, OperandInfo143}, // Inst #5594 = UMLALv8i16_indexed + {4, OperandInfo98}, // Inst #5595 = UMLALv8i16_v4i32 + {4, OperandInfo401}, // Inst #5596 = UMLALv8i8_v8i16 + {5, OperandInfo251}, // Inst #5597 = UMLSLB_ZZZI_D + {5, OperandInfo141}, // Inst #5598 = UMLSLB_ZZZI_S + {4, OperandInfo92}, // Inst #5599 = UMLSLB_ZZZ_D + {4, OperandInfo92}, // Inst #5600 = UMLSLB_ZZZ_H + {4, OperandInfo92}, // Inst #5601 = UMLSLB_ZZZ_S + {5, OperandInfo251}, // Inst #5602 = UMLSLT_ZZZI_D + {5, OperandInfo141}, // Inst #5603 = UMLSLT_ZZZI_S + {4, OperandInfo92}, // Inst #5604 = UMLSLT_ZZZ_D + {4, OperandInfo92}, // Inst #5605 = UMLSLT_ZZZ_H + {4, OperandInfo92}, // Inst #5606 = UMLSLT_ZZZ_S + {4, OperandInfo98}, // Inst #5607 = UMLSLv16i8_v8i16 + {5, OperandInfo417}, // Inst #5608 = UMLSLv2i32_indexed + {4, OperandInfo401}, // Inst #5609 = UMLSLv2i32_v2i64 + {5, OperandInfo418}, // Inst #5610 = UMLSLv4i16_indexed + {4, OperandInfo401}, // Inst #5611 = UMLSLv4i16_v4i32 + {5, OperandInfo139}, // Inst #5612 = UMLSLv4i32_indexed + {4, OperandInfo98}, // Inst #5613 = UMLSLv4i32_v2i64 + {5, OperandInfo143}, // Inst #5614 = UMLSLv8i16_indexed + {4, OperandInfo98}, // Inst #5615 = UMLSLv8i16_v4i32 + {4, OperandInfo401}, // Inst #5616 = UMLSLv8i8_v8i16 + {4, OperandInfo98}, // Inst #5617 = UMMLA + {4, OperandInfo92}, // Inst #5618 = UMMLA_ZZZ + {5, OperandInfo255}, // Inst #5619 = UMOPA_MPPZZ_D + {5, OperandInfo256}, // Inst #5620 = UMOPA_MPPZZ_S + {5, OperandInfo255}, // Inst #5621 = UMOPS_MPPZZ_D + {5, OperandInfo256}, // Inst #5622 = UMOPS_MPPZZ_S + {3, OperandInfo419}, // Inst #5623 = UMOVvi16 + {3, OperandInfo419}, // Inst #5624 = UMOVvi16_idx0 + {3, OperandInfo419}, // Inst #5625 = UMOVvi32 + {3, OperandInfo419}, // Inst #5626 = UMOVvi32_idx0 + {3, OperandInfo257}, // Inst #5627 = UMOVvi64 + {3, OperandInfo257}, // Inst #5628 = UMOVvi64_idx0 + {3, OperandInfo419}, // Inst #5629 = UMOVvi8 + {3, OperandInfo419}, // Inst #5630 = UMOVvi8_idx0 + {4, OperandInfo416}, // Inst #5631 = UMSUBLrrr + {4, OperandInfo100}, // Inst #5632 = UMULH_ZPmZ_B + {4, OperandInfo100}, // Inst #5633 = UMULH_ZPmZ_D + {4, OperandInfo100}, // Inst #5634 = UMULH_ZPmZ_H + {4, OperandInfo100}, // Inst #5635 = UMULH_ZPmZ_S + {3, OperandInfo96}, // Inst #5636 = UMULH_ZZZ_B + {3, OperandInfo96}, // Inst #5637 = UMULH_ZZZ_D + {3, OperandInfo96}, // Inst #5638 = UMULH_ZZZ_H + {3, OperandInfo96}, // Inst #5639 = UMULH_ZZZ_S + {3, OperandInfo46}, // Inst #5640 = UMULHrr + {4, OperandInfo272}, // Inst #5641 = UMULLB_ZZZI_D + {4, OperandInfo273}, // Inst #5642 = UMULLB_ZZZI_S + {3, OperandInfo96}, // Inst #5643 = UMULLB_ZZZ_D + {3, OperandInfo96}, // Inst #5644 = UMULLB_ZZZ_H + {3, OperandInfo96}, // Inst #5645 = UMULLB_ZZZ_S + {4, OperandInfo272}, // Inst #5646 = UMULLT_ZZZI_D + {4, OperandInfo273}, // Inst #5647 = UMULLT_ZZZI_S + {3, OperandInfo96}, // Inst #5648 = UMULLT_ZZZ_D + {3, OperandInfo96}, // Inst #5649 = UMULLT_ZZZ_H + {3, OperandInfo96}, // Inst #5650 = UMULLT_ZZZ_S + {3, OperandInfo101}, // Inst #5651 = UMULLv16i8_v8i16 + {4, OperandInfo420}, // Inst #5652 = UMULLv2i32_indexed + {3, OperandInfo390}, // Inst #5653 = UMULLv2i32_v2i64 + {4, OperandInfo421}, // Inst #5654 = UMULLv4i16_indexed + {3, OperandInfo390}, // Inst #5655 = UMULLv4i16_v4i32 + {4, OperandInfo58}, // Inst #5656 = UMULLv4i32_indexed + {3, OperandInfo101}, // Inst #5657 = UMULLv4i32_v2i64 + {4, OperandInfo271}, // Inst #5658 = UMULLv8i16_indexed + {3, OperandInfo101}, // Inst #5659 = UMULLv8i16_v4i32 + {3, OperandInfo390}, // Inst #5660 = UMULLv8i8_v8i16 + {4, OperandInfo120}, // Inst #5661 = UQADD_ZI_B + {4, OperandInfo120}, // Inst #5662 = UQADD_ZI_D + {4, OperandInfo120}, // Inst #5663 = UQADD_ZI_H + {4, OperandInfo120}, // Inst #5664 = UQADD_ZI_S + {4, OperandInfo100}, // Inst #5665 = UQADD_ZPmZ_B + {4, OperandInfo100}, // Inst #5666 = UQADD_ZPmZ_D + {4, OperandInfo100}, // Inst #5667 = UQADD_ZPmZ_H + {4, OperandInfo100}, // Inst #5668 = UQADD_ZPmZ_S + {3, OperandInfo96}, // Inst #5669 = UQADD_ZZZ_B + {3, OperandInfo96}, // Inst #5670 = UQADD_ZZZ_D + {3, OperandInfo96}, // Inst #5671 = UQADD_ZZZ_H + {3, OperandInfo96}, // Inst #5672 = UQADD_ZZZ_S + {3, OperandInfo101}, // Inst #5673 = UQADDv16i8 + {3, OperandInfo210}, // Inst #5674 = UQADDv1i16 + {3, OperandInfo211}, // Inst #5675 = UQADDv1i32 + {3, OperandInfo102}, // Inst #5676 = UQADDv1i64 + {3, OperandInfo424}, // Inst #5677 = UQADDv1i8 + {3, OperandInfo102}, // Inst #5678 = UQADDv2i32 + {3, OperandInfo101}, // Inst #5679 = UQADDv2i64 + {3, OperandInfo102}, // Inst #5680 = UQADDv4i16 + {3, OperandInfo101}, // Inst #5681 = UQADDv4i32 + {3, OperandInfo101}, // Inst #5682 = UQADDv8i16 + {3, OperandInfo102}, // Inst #5683 = UQADDv8i8 + {4, OperandInfo386}, // Inst #5684 = UQDECB_WPiI + {4, OperandInfo191}, // Inst #5685 = UQDECB_XPiI + {4, OperandInfo386}, // Inst #5686 = UQDECD_WPiI + {4, OperandInfo191}, // Inst #5687 = UQDECD_XPiI + {4, OperandInfo120}, // Inst #5688 = UQDECD_ZPiI + {4, OperandInfo386}, // Inst #5689 = UQDECH_WPiI + {4, OperandInfo191}, // Inst #5690 = UQDECH_XPiI + {4, OperandInfo120}, // Inst #5691 = UQDECH_ZPiI + {3, OperandInfo478}, // Inst #5692 = UQDECP_WP_B + {3, OperandInfo478}, // Inst #5693 = UQDECP_WP_D + {3, OperandInfo478}, // Inst #5694 = UQDECP_WP_H + {3, OperandInfo478}, // Inst #5695 = UQDECP_WP_S + {3, OperandInfo192}, // Inst #5696 = UQDECP_XP_B + {3, OperandInfo192}, // Inst #5697 = UQDECP_XP_D + {3, OperandInfo192}, // Inst #5698 = UQDECP_XP_H + {3, OperandInfo192}, // Inst #5699 = UQDECP_XP_S + {3, OperandInfo193}, // Inst #5700 = UQDECP_ZP_D + {3, OperandInfo193}, // Inst #5701 = UQDECP_ZP_H + {3, OperandInfo193}, // Inst #5702 = UQDECP_ZP_S + {4, OperandInfo386}, // Inst #5703 = UQDECW_WPiI + {4, OperandInfo191}, // Inst #5704 = UQDECW_XPiI + {4, OperandInfo120}, // Inst #5705 = UQDECW_ZPiI + {4, OperandInfo386}, // Inst #5706 = UQINCB_WPiI + {4, OperandInfo191}, // Inst #5707 = UQINCB_XPiI + {4, OperandInfo386}, // Inst #5708 = UQINCD_WPiI + {4, OperandInfo191}, // Inst #5709 = UQINCD_XPiI + {4, OperandInfo120}, // Inst #5710 = UQINCD_ZPiI + {4, OperandInfo386}, // Inst #5711 = UQINCH_WPiI + {4, OperandInfo191}, // Inst #5712 = UQINCH_XPiI + {4, OperandInfo120}, // Inst #5713 = UQINCH_ZPiI + {3, OperandInfo478}, // Inst #5714 = UQINCP_WP_B + {3, OperandInfo478}, // Inst #5715 = UQINCP_WP_D + {3, OperandInfo478}, // Inst #5716 = UQINCP_WP_H + {3, OperandInfo478}, // Inst #5717 = UQINCP_WP_S + {3, OperandInfo192}, // Inst #5718 = UQINCP_XP_B + {3, OperandInfo192}, // Inst #5719 = UQINCP_XP_D + {3, OperandInfo192}, // Inst #5720 = UQINCP_XP_H + {3, OperandInfo192}, // Inst #5721 = UQINCP_XP_S + {3, OperandInfo193}, // Inst #5722 = UQINCP_ZP_D + {3, OperandInfo193}, // Inst #5723 = UQINCP_ZP_H + {3, OperandInfo193}, // Inst #5724 = UQINCP_ZP_S + {4, OperandInfo386}, // Inst #5725 = UQINCW_WPiI + {4, OperandInfo191}, // Inst #5726 = UQINCW_XPiI + {4, OperandInfo120}, // Inst #5727 = UQINCW_ZPiI + {4, OperandInfo100}, // Inst #5728 = UQRSHLR_ZPmZ_B + {4, OperandInfo100}, // Inst #5729 = UQRSHLR_ZPmZ_D + {4, OperandInfo100}, // Inst #5730 = UQRSHLR_ZPmZ_H + {4, OperandInfo100}, // Inst #5731 = UQRSHLR_ZPmZ_S + {4, OperandInfo100}, // Inst #5732 = UQRSHL_ZPmZ_B + {4, OperandInfo100}, // Inst #5733 = UQRSHL_ZPmZ_D + {4, OperandInfo100}, // Inst #5734 = UQRSHL_ZPmZ_H + {4, OperandInfo100}, // Inst #5735 = UQRSHL_ZPmZ_S + {3, OperandInfo101}, // Inst #5736 = UQRSHLv16i8 + {3, OperandInfo210}, // Inst #5737 = UQRSHLv1i16 + {3, OperandInfo211}, // Inst #5738 = UQRSHLv1i32 + {3, OperandInfo102}, // Inst #5739 = UQRSHLv1i64 + {3, OperandInfo424}, // Inst #5740 = UQRSHLv1i8 + {3, OperandInfo102}, // Inst #5741 = UQRSHLv2i32 + {3, OperandInfo101}, // Inst #5742 = UQRSHLv2i64 + {3, OperandInfo102}, // Inst #5743 = UQRSHLv4i16 + {3, OperandInfo101}, // Inst #5744 = UQRSHLv4i32 + {3, OperandInfo101}, // Inst #5745 = UQRSHLv8i16 + {3, OperandInfo102}, // Inst #5746 = UQRSHLv8i8 + {3, OperandInfo134}, // Inst #5747 = UQRSHRNB_ZZI_B + {3, OperandInfo134}, // Inst #5748 = UQRSHRNB_ZZI_H + {3, OperandInfo134}, // Inst #5749 = UQRSHRNB_ZZI_S + {4, OperandInfo153}, // Inst #5750 = UQRSHRNT_ZZI_B + {4, OperandInfo153}, // Inst #5751 = UQRSHRNT_ZZI_H + {4, OperandInfo153}, // Inst #5752 = UQRSHRNT_ZZI_S + {3, OperandInfo435}, // Inst #5753 = UQRSHRNb + {3, OperandInfo436}, // Inst #5754 = UQRSHRNh + {3, OperandInfo437}, // Inst #5755 = UQRSHRNs + {4, OperandInfo400}, // Inst #5756 = UQRSHRNv16i8_shift + {3, OperandInfo186}, // Inst #5757 = UQRSHRNv2i32_shift + {3, OperandInfo186}, // Inst #5758 = UQRSHRNv4i16_shift + {4, OperandInfo400}, // Inst #5759 = UQRSHRNv4i32_shift + {4, OperandInfo400}, // Inst #5760 = UQRSHRNv8i16_shift + {3, OperandInfo186}, // Inst #5761 = UQRSHRNv8i8_shift + {4, OperandInfo100}, // Inst #5762 = UQSHLR_ZPmZ_B + {4, OperandInfo100}, // Inst #5763 = UQSHLR_ZPmZ_D + {4, OperandInfo100}, // Inst #5764 = UQSHLR_ZPmZ_H + {4, OperandInfo100}, // Inst #5765 = UQSHLR_ZPmZ_S + {4, OperandInfo133}, // Inst #5766 = UQSHL_ZPmI_B + {4, OperandInfo133}, // Inst #5767 = UQSHL_ZPmI_D + {4, OperandInfo133}, // Inst #5768 = UQSHL_ZPmI_H + {4, OperandInfo133}, // Inst #5769 = UQSHL_ZPmI_S + {4, OperandInfo100}, // Inst #5770 = UQSHL_ZPmZ_B + {4, OperandInfo100}, // Inst #5771 = UQSHL_ZPmZ_D + {4, OperandInfo100}, // Inst #5772 = UQSHL_ZPmZ_H + {4, OperandInfo100}, // Inst #5773 = UQSHL_ZPmZ_S + {3, OperandInfo438}, // Inst #5774 = UQSHLb + {3, OperandInfo244}, // Inst #5775 = UQSHLd + {3, OperandInfo245}, // Inst #5776 = UQSHLh + {3, OperandInfo246}, // Inst #5777 = UQSHLs + {3, OperandInfo101}, // Inst #5778 = UQSHLv16i8 + {3, OperandInfo199}, // Inst #5779 = UQSHLv16i8_shift + {3, OperandInfo210}, // Inst #5780 = UQSHLv1i16 + {3, OperandInfo211}, // Inst #5781 = UQSHLv1i32 + {3, OperandInfo102}, // Inst #5782 = UQSHLv1i64 + {3, OperandInfo424}, // Inst #5783 = UQSHLv1i8 + {3, OperandInfo102}, // Inst #5784 = UQSHLv2i32 + {3, OperandInfo244}, // Inst #5785 = UQSHLv2i32_shift + {3, OperandInfo101}, // Inst #5786 = UQSHLv2i64 + {3, OperandInfo199}, // Inst #5787 = UQSHLv2i64_shift + {3, OperandInfo102}, // Inst #5788 = UQSHLv4i16 + {3, OperandInfo244}, // Inst #5789 = UQSHLv4i16_shift + {3, OperandInfo101}, // Inst #5790 = UQSHLv4i32 + {3, OperandInfo199}, // Inst #5791 = UQSHLv4i32_shift + {3, OperandInfo101}, // Inst #5792 = UQSHLv8i16 + {3, OperandInfo199}, // Inst #5793 = UQSHLv8i16_shift + {3, OperandInfo102}, // Inst #5794 = UQSHLv8i8 + {3, OperandInfo244}, // Inst #5795 = UQSHLv8i8_shift + {3, OperandInfo134}, // Inst #5796 = UQSHRNB_ZZI_B + {3, OperandInfo134}, // Inst #5797 = UQSHRNB_ZZI_H + {3, OperandInfo134}, // Inst #5798 = UQSHRNB_ZZI_S + {4, OperandInfo153}, // Inst #5799 = UQSHRNT_ZZI_B + {4, OperandInfo153}, // Inst #5800 = UQSHRNT_ZZI_H + {4, OperandInfo153}, // Inst #5801 = UQSHRNT_ZZI_S + {3, OperandInfo435}, // Inst #5802 = UQSHRNb + {3, OperandInfo436}, // Inst #5803 = UQSHRNh + {3, OperandInfo437}, // Inst #5804 = UQSHRNs + {4, OperandInfo400}, // Inst #5805 = UQSHRNv16i8_shift + {3, OperandInfo186}, // Inst #5806 = UQSHRNv2i32_shift + {3, OperandInfo186}, // Inst #5807 = UQSHRNv4i16_shift + {4, OperandInfo400}, // Inst #5808 = UQSHRNv4i32_shift + {4, OperandInfo400}, // Inst #5809 = UQSHRNv8i16_shift + {3, OperandInfo186}, // Inst #5810 = UQSHRNv8i8_shift + {4, OperandInfo100}, // Inst #5811 = UQSUBR_ZPmZ_B + {4, OperandInfo100}, // Inst #5812 = UQSUBR_ZPmZ_D + {4, OperandInfo100}, // Inst #5813 = UQSUBR_ZPmZ_H + {4, OperandInfo100}, // Inst #5814 = UQSUBR_ZPmZ_S + {4, OperandInfo120}, // Inst #5815 = UQSUB_ZI_B + {4, OperandInfo120}, // Inst #5816 = UQSUB_ZI_D + {4, OperandInfo120}, // Inst #5817 = UQSUB_ZI_H + {4, OperandInfo120}, // Inst #5818 = UQSUB_ZI_S + {4, OperandInfo100}, // Inst #5819 = UQSUB_ZPmZ_B + {4, OperandInfo100}, // Inst #5820 = UQSUB_ZPmZ_D + {4, OperandInfo100}, // Inst #5821 = UQSUB_ZPmZ_H + {4, OperandInfo100}, // Inst #5822 = UQSUB_ZPmZ_S + {3, OperandInfo96}, // Inst #5823 = UQSUB_ZZZ_B + {3, OperandInfo96}, // Inst #5824 = UQSUB_ZZZ_D + {3, OperandInfo96}, // Inst #5825 = UQSUB_ZZZ_H + {3, OperandInfo96}, // Inst #5826 = UQSUB_ZZZ_S + {3, OperandInfo101}, // Inst #5827 = UQSUBv16i8 + {3, OperandInfo210}, // Inst #5828 = UQSUBv1i16 + {3, OperandInfo211}, // Inst #5829 = UQSUBv1i32 + {3, OperandInfo102}, // Inst #5830 = UQSUBv1i64 + {3, OperandInfo424}, // Inst #5831 = UQSUBv1i8 + {3, OperandInfo102}, // Inst #5832 = UQSUBv2i32 + {3, OperandInfo101}, // Inst #5833 = UQSUBv2i64 + {3, OperandInfo102}, // Inst #5834 = UQSUBv4i16 + {3, OperandInfo101}, // Inst #5835 = UQSUBv4i32 + {3, OperandInfo101}, // Inst #5836 = UQSUBv8i16 + {3, OperandInfo102}, // Inst #5837 = UQSUBv8i8 + {2, OperandInfo247}, // Inst #5838 = UQXTNB_ZZ_B + {2, OperandInfo247}, // Inst #5839 = UQXTNB_ZZ_H + {2, OperandInfo247}, // Inst #5840 = UQXTNB_ZZ_S + {3, OperandInfo123}, // Inst #5841 = UQXTNT_ZZ_B + {3, OperandInfo123}, // Inst #5842 = UQXTNT_ZZ_H + {3, OperandInfo123}, // Inst #5843 = UQXTNT_ZZ_S + {3, OperandInfo124}, // Inst #5844 = UQXTNv16i8 + {2, OperandInfo140}, // Inst #5845 = UQXTNv1i16 + {2, OperandInfo214}, // Inst #5846 = UQXTNv1i32 + {2, OperandInfo439}, // Inst #5847 = UQXTNv1i8 + {2, OperandInfo103}, // Inst #5848 = UQXTNv2i32 + {2, OperandInfo103}, // Inst #5849 = UQXTNv4i16 + {3, OperandInfo124}, // Inst #5850 = UQXTNv4i32 + {3, OperandInfo124}, // Inst #5851 = UQXTNv8i16 + {2, OperandInfo103}, // Inst #5852 = UQXTNv8i8 + {4, OperandInfo89}, // Inst #5853 = URECPE_ZPmZ_S + {2, OperandInfo91}, // Inst #5854 = URECPEv2i32 + {2, OperandInfo90}, // Inst #5855 = URECPEv4i32 + {4, OperandInfo100}, // Inst #5856 = URHADD_ZPmZ_B + {4, OperandInfo100}, // Inst #5857 = URHADD_ZPmZ_D + {4, OperandInfo100}, // Inst #5858 = URHADD_ZPmZ_H + {4, OperandInfo100}, // Inst #5859 = URHADD_ZPmZ_S + {3, OperandInfo101}, // Inst #5860 = URHADDv16i8 + {3, OperandInfo102}, // Inst #5861 = URHADDv2i32 + {3, OperandInfo102}, // Inst #5862 = URHADDv4i16 + {3, OperandInfo101}, // Inst #5863 = URHADDv4i32 + {3, OperandInfo101}, // Inst #5864 = URHADDv8i16 + {3, OperandInfo102}, // Inst #5865 = URHADDv8i8 + {4, OperandInfo100}, // Inst #5866 = URSHLR_ZPmZ_B + {4, OperandInfo100}, // Inst #5867 = URSHLR_ZPmZ_D + {4, OperandInfo100}, // Inst #5868 = URSHLR_ZPmZ_H + {4, OperandInfo100}, // Inst #5869 = URSHLR_ZPmZ_S + {4, OperandInfo100}, // Inst #5870 = URSHL_ZPmZ_B + {4, OperandInfo100}, // Inst #5871 = URSHL_ZPmZ_D + {4, OperandInfo100}, // Inst #5872 = URSHL_ZPmZ_H + {4, OperandInfo100}, // Inst #5873 = URSHL_ZPmZ_S + {3, OperandInfo101}, // Inst #5874 = URSHLv16i8 + {3, OperandInfo102}, // Inst #5875 = URSHLv1i64 + {3, OperandInfo102}, // Inst #5876 = URSHLv2i32 + {3, OperandInfo101}, // Inst #5877 = URSHLv2i64 + {3, OperandInfo102}, // Inst #5878 = URSHLv4i16 + {3, OperandInfo101}, // Inst #5879 = URSHLv4i32 + {3, OperandInfo101}, // Inst #5880 = URSHLv8i16 + {3, OperandInfo102}, // Inst #5881 = URSHLv8i8 + {4, OperandInfo133}, // Inst #5882 = URSHR_ZPmI_B + {4, OperandInfo133}, // Inst #5883 = URSHR_ZPmI_D + {4, OperandInfo133}, // Inst #5884 = URSHR_ZPmI_H + {4, OperandInfo133}, // Inst #5885 = URSHR_ZPmI_S + {3, OperandInfo244}, // Inst #5886 = URSHRd + {3, OperandInfo199}, // Inst #5887 = URSHRv16i8_shift + {3, OperandInfo244}, // Inst #5888 = URSHRv2i32_shift + {3, OperandInfo199}, // Inst #5889 = URSHRv2i64_shift + {3, OperandInfo244}, // Inst #5890 = URSHRv4i16_shift + {3, OperandInfo199}, // Inst #5891 = URSHRv4i32_shift + {3, OperandInfo199}, // Inst #5892 = URSHRv8i16_shift + {3, OperandInfo244}, // Inst #5893 = URSHRv8i8_shift + {4, OperandInfo89}, // Inst #5894 = URSQRTE_ZPmZ_S + {2, OperandInfo91}, // Inst #5895 = URSQRTEv2i32 + {2, OperandInfo90}, // Inst #5896 = URSQRTEv4i32 + {4, OperandInfo153}, // Inst #5897 = URSRA_ZZI_B + {4, OperandInfo153}, // Inst #5898 = URSRA_ZZI_D + {4, OperandInfo153}, // Inst #5899 = URSRA_ZZI_H + {4, OperandInfo153}, // Inst #5900 = URSRA_ZZI_S + {4, OperandInfo415}, // Inst #5901 = URSRAd + {4, OperandInfo400}, // Inst #5902 = URSRAv16i8_shift + {4, OperandInfo415}, // Inst #5903 = URSRAv2i32_shift + {4, OperandInfo400}, // Inst #5904 = URSRAv2i64_shift + {4, OperandInfo415}, // Inst #5905 = URSRAv4i16_shift + {4, OperandInfo400}, // Inst #5906 = URSRAv4i32_shift + {4, OperandInfo400}, // Inst #5907 = URSRAv8i16_shift + {4, OperandInfo415}, // Inst #5908 = URSRAv8i8_shift + {4, OperandInfo92}, // Inst #5909 = USDOT_ZZZ + {5, OperandInfo141}, // Inst #5910 = USDOT_ZZZI + {5, OperandInfo139}, // Inst #5911 = USDOTlanev16i8 + {5, OperandInfo138}, // Inst #5912 = USDOTlanev8i8 + {4, OperandInfo98}, // Inst #5913 = USDOTv16i8 + {4, OperandInfo142}, // Inst #5914 = USDOTv8i8 + {3, OperandInfo134}, // Inst #5915 = USHLLB_ZZI_D + {3, OperandInfo134}, // Inst #5916 = USHLLB_ZZI_H + {3, OperandInfo134}, // Inst #5917 = USHLLB_ZZI_S + {3, OperandInfo134}, // Inst #5918 = USHLLT_ZZI_D + {3, OperandInfo134}, // Inst #5919 = USHLLT_ZZI_H + {3, OperandInfo134}, // Inst #5920 = USHLLT_ZZI_S + {3, OperandInfo199}, // Inst #5921 = USHLLv16i8_shift + {3, OperandInfo440}, // Inst #5922 = USHLLv2i32_shift + {3, OperandInfo440}, // Inst #5923 = USHLLv4i16_shift + {3, OperandInfo199}, // Inst #5924 = USHLLv4i32_shift + {3, OperandInfo199}, // Inst #5925 = USHLLv8i16_shift + {3, OperandInfo440}, // Inst #5926 = USHLLv8i8_shift + {3, OperandInfo101}, // Inst #5927 = USHLv16i8 + {3, OperandInfo102}, // Inst #5928 = USHLv1i64 + {3, OperandInfo102}, // Inst #5929 = USHLv2i32 + {3, OperandInfo101}, // Inst #5930 = USHLv2i64 + {3, OperandInfo102}, // Inst #5931 = USHLv4i16 + {3, OperandInfo101}, // Inst #5932 = USHLv4i32 + {3, OperandInfo101}, // Inst #5933 = USHLv8i16 + {3, OperandInfo102}, // Inst #5934 = USHLv8i8 + {3, OperandInfo244}, // Inst #5935 = USHRd + {3, OperandInfo199}, // Inst #5936 = USHRv16i8_shift + {3, OperandInfo244}, // Inst #5937 = USHRv2i32_shift + {3, OperandInfo199}, // Inst #5938 = USHRv2i64_shift + {3, OperandInfo244}, // Inst #5939 = USHRv4i16_shift + {3, OperandInfo199}, // Inst #5940 = USHRv4i32_shift + {3, OperandInfo199}, // Inst #5941 = USHRv8i16_shift + {3, OperandInfo244}, // Inst #5942 = USHRv8i8_shift + {4, OperandInfo98}, // Inst #5943 = USMMLA + {4, OperandInfo92}, // Inst #5944 = USMMLA_ZZZ + {5, OperandInfo255}, // Inst #5945 = USMOPA_MPPZZ_D + {5, OperandInfo256}, // Inst #5946 = USMOPA_MPPZZ_S + {5, OperandInfo255}, // Inst #5947 = USMOPS_MPPZZ_D + {5, OperandInfo256}, // Inst #5948 = USMOPS_MPPZZ_S + {4, OperandInfo100}, // Inst #5949 = USQADD_ZPmZ_B + {4, OperandInfo100}, // Inst #5950 = USQADD_ZPmZ_D + {4, OperandInfo100}, // Inst #5951 = USQADD_ZPmZ_H + {4, OperandInfo100}, // Inst #5952 = USQADD_ZPmZ_S + {3, OperandInfo124}, // Inst #5953 = USQADDv16i8 + {3, OperandInfo456}, // Inst #5954 = USQADDv1i16 + {3, OperandInfo457}, // Inst #5955 = USQADDv1i32 + {3, OperandInfo402}, // Inst #5956 = USQADDv1i64 + {3, OperandInfo458}, // Inst #5957 = USQADDv1i8 + {3, OperandInfo402}, // Inst #5958 = USQADDv2i32 + {3, OperandInfo124}, // Inst #5959 = USQADDv2i64 + {3, OperandInfo402}, // Inst #5960 = USQADDv4i16 + {3, OperandInfo124}, // Inst #5961 = USQADDv4i32 + {3, OperandInfo124}, // Inst #5962 = USQADDv8i16 + {3, OperandInfo402}, // Inst #5963 = USQADDv8i8 + {4, OperandInfo153}, // Inst #5964 = USRA_ZZI_B + {4, OperandInfo153}, // Inst #5965 = USRA_ZZI_D + {4, OperandInfo153}, // Inst #5966 = USRA_ZZI_H + {4, OperandInfo153}, // Inst #5967 = USRA_ZZI_S + {4, OperandInfo415}, // Inst #5968 = USRAd + {4, OperandInfo400}, // Inst #5969 = USRAv16i8_shift + {4, OperandInfo415}, // Inst #5970 = USRAv2i32_shift + {4, OperandInfo400}, // Inst #5971 = USRAv2i64_shift + {4, OperandInfo415}, // Inst #5972 = USRAv4i16_shift + {4, OperandInfo400}, // Inst #5973 = USRAv4i32_shift + {4, OperandInfo400}, // Inst #5974 = USRAv8i16_shift + {4, OperandInfo415}, // Inst #5975 = USRAv8i8_shift + {3, OperandInfo96}, // Inst #5976 = USUBLB_ZZZ_D + {3, OperandInfo96}, // Inst #5977 = USUBLB_ZZZ_H + {3, OperandInfo96}, // Inst #5978 = USUBLB_ZZZ_S + {3, OperandInfo96}, // Inst #5979 = USUBLT_ZZZ_D + {3, OperandInfo96}, // Inst #5980 = USUBLT_ZZZ_H + {3, OperandInfo96}, // Inst #5981 = USUBLT_ZZZ_S + {3, OperandInfo101}, // Inst #5982 = USUBLv16i8_v8i16 + {3, OperandInfo390}, // Inst #5983 = USUBLv2i32_v2i64 + {3, OperandInfo390}, // Inst #5984 = USUBLv4i16_v4i32 + {3, OperandInfo101}, // Inst #5985 = USUBLv4i32_v2i64 + {3, OperandInfo101}, // Inst #5986 = USUBLv8i16_v4i32 + {3, OperandInfo390}, // Inst #5987 = USUBLv8i8_v8i16 + {3, OperandInfo96}, // Inst #5988 = USUBWB_ZZZ_D + {3, OperandInfo96}, // Inst #5989 = USUBWB_ZZZ_H + {3, OperandInfo96}, // Inst #5990 = USUBWB_ZZZ_S + {3, OperandInfo96}, // Inst #5991 = USUBWT_ZZZ_D + {3, OperandInfo96}, // Inst #5992 = USUBWT_ZZZ_H + {3, OperandInfo96}, // Inst #5993 = USUBWT_ZZZ_S + {3, OperandInfo101}, // Inst #5994 = USUBWv16i8_v8i16 + {3, OperandInfo403}, // Inst #5995 = USUBWv2i32_v2i64 + {3, OperandInfo403}, // Inst #5996 = USUBWv4i16_v4i32 + {3, OperandInfo101}, // Inst #5997 = USUBWv4i32_v2i64 + {3, OperandInfo101}, // Inst #5998 = USUBWv8i16_v4i32 + {3, OperandInfo403}, // Inst #5999 = USUBWv8i8_v8i16 + {2, OperandInfo247}, // Inst #6000 = UUNPKHI_ZZ_D + {2, OperandInfo247}, // Inst #6001 = UUNPKHI_ZZ_H + {2, OperandInfo247}, // Inst #6002 = UUNPKHI_ZZ_S + {2, OperandInfo247}, // Inst #6003 = UUNPKLO_ZZ_D + {2, OperandInfo247}, // Inst #6004 = UUNPKLO_ZZ_H + {2, OperandInfo247}, // Inst #6005 = UUNPKLO_ZZ_S + {4, OperandInfo89}, // Inst #6006 = UXTB_ZPmZ_D + {4, OperandInfo89}, // Inst #6007 = UXTB_ZPmZ_H + {4, OperandInfo89}, // Inst #6008 = UXTB_ZPmZ_S + {4, OperandInfo89}, // Inst #6009 = UXTH_ZPmZ_D + {4, OperandInfo89}, // Inst #6010 = UXTH_ZPmZ_S + {4, OperandInfo89}, // Inst #6011 = UXTW_ZPmZ_D + {3, OperandInfo149}, // Inst #6012 = UZP1_PPP_B + {3, OperandInfo149}, // Inst #6013 = UZP1_PPP_D + {3, OperandInfo149}, // Inst #6014 = UZP1_PPP_H + {3, OperandInfo149}, // Inst #6015 = UZP1_PPP_S + {3, OperandInfo96}, // Inst #6016 = UZP1_ZZZ_B + {3, OperandInfo96}, // Inst #6017 = UZP1_ZZZ_D + {3, OperandInfo96}, // Inst #6018 = UZP1_ZZZ_H + {3, OperandInfo96}, // Inst #6019 = UZP1_ZZZ_Q + {3, OperandInfo96}, // Inst #6020 = UZP1_ZZZ_S + {3, OperandInfo101}, // Inst #6021 = UZP1v16i8 + {3, OperandInfo102}, // Inst #6022 = UZP1v2i32 + {3, OperandInfo101}, // Inst #6023 = UZP1v2i64 + {3, OperandInfo102}, // Inst #6024 = UZP1v4i16 + {3, OperandInfo101}, // Inst #6025 = UZP1v4i32 + {3, OperandInfo101}, // Inst #6026 = UZP1v8i16 + {3, OperandInfo102}, // Inst #6027 = UZP1v8i8 + {3, OperandInfo149}, // Inst #6028 = UZP2_PPP_B + {3, OperandInfo149}, // Inst #6029 = UZP2_PPP_D + {3, OperandInfo149}, // Inst #6030 = UZP2_PPP_H + {3, OperandInfo149}, // Inst #6031 = UZP2_PPP_S + {3, OperandInfo96}, // Inst #6032 = UZP2_ZZZ_B + {3, OperandInfo96}, // Inst #6033 = UZP2_ZZZ_D + {3, OperandInfo96}, // Inst #6034 = UZP2_ZZZ_H + {3, OperandInfo96}, // Inst #6035 = UZP2_ZZZ_Q + {3, OperandInfo96}, // Inst #6036 = UZP2_ZZZ_S + {3, OperandInfo101}, // Inst #6037 = UZP2v16i8 + {3, OperandInfo102}, // Inst #6038 = UZP2v2i32 + {3, OperandInfo101}, // Inst #6039 = UZP2v2i64 + {3, OperandInfo102}, // Inst #6040 = UZP2v4i16 + {3, OperandInfo101}, // Inst #6041 = UZP2v4i32 + {3, OperandInfo101}, // Inst #6042 = UZP2v8i16 + {3, OperandInfo102}, // Inst #6043 = UZP2v8i8 + {1, OperandInfo75}, // Inst #6044 = WFET + {1, OperandInfo75}, // Inst #6045 = WFIT + {3, OperandInfo479}, // Inst #6046 = WHILEGE_PWW_B + {3, OperandInfo479}, // Inst #6047 = WHILEGE_PWW_D + {3, OperandInfo479}, // Inst #6048 = WHILEGE_PWW_H + {3, OperandInfo479}, // Inst #6049 = WHILEGE_PWW_S + {3, OperandInfo480}, // Inst #6050 = WHILEGE_PXX_B + {3, OperandInfo480}, // Inst #6051 = WHILEGE_PXX_D + {3, OperandInfo480}, // Inst #6052 = WHILEGE_PXX_H + {3, OperandInfo480}, // Inst #6053 = WHILEGE_PXX_S + {3, OperandInfo479}, // Inst #6054 = WHILEGT_PWW_B + {3, OperandInfo479}, // Inst #6055 = WHILEGT_PWW_D + {3, OperandInfo479}, // Inst #6056 = WHILEGT_PWW_H + {3, OperandInfo479}, // Inst #6057 = WHILEGT_PWW_S + {3, OperandInfo480}, // Inst #6058 = WHILEGT_PXX_B + {3, OperandInfo480}, // Inst #6059 = WHILEGT_PXX_D + {3, OperandInfo480}, // Inst #6060 = WHILEGT_PXX_H + {3, OperandInfo480}, // Inst #6061 = WHILEGT_PXX_S + {3, OperandInfo479}, // Inst #6062 = WHILEHI_PWW_B + {3, OperandInfo479}, // Inst #6063 = WHILEHI_PWW_D + {3, OperandInfo479}, // Inst #6064 = WHILEHI_PWW_H + {3, OperandInfo479}, // Inst #6065 = WHILEHI_PWW_S + {3, OperandInfo480}, // Inst #6066 = WHILEHI_PXX_B + {3, OperandInfo480}, // Inst #6067 = WHILEHI_PXX_D + {3, OperandInfo480}, // Inst #6068 = WHILEHI_PXX_H + {3, OperandInfo480}, // Inst #6069 = WHILEHI_PXX_S + {3, OperandInfo479}, // Inst #6070 = WHILEHS_PWW_B + {3, OperandInfo479}, // Inst #6071 = WHILEHS_PWW_D + {3, OperandInfo479}, // Inst #6072 = WHILEHS_PWW_H + {3, OperandInfo479}, // Inst #6073 = WHILEHS_PWW_S + {3, OperandInfo480}, // Inst #6074 = WHILEHS_PXX_B + {3, OperandInfo480}, // Inst #6075 = WHILEHS_PXX_D + {3, OperandInfo480}, // Inst #6076 = WHILEHS_PXX_H + {3, OperandInfo480}, // Inst #6077 = WHILEHS_PXX_S + {3, OperandInfo479}, // Inst #6078 = WHILELE_PWW_B + {3, OperandInfo479}, // Inst #6079 = WHILELE_PWW_D + {3, OperandInfo479}, // Inst #6080 = WHILELE_PWW_H + {3, OperandInfo479}, // Inst #6081 = WHILELE_PWW_S + {3, OperandInfo480}, // Inst #6082 = WHILELE_PXX_B + {3, OperandInfo480}, // Inst #6083 = WHILELE_PXX_D + {3, OperandInfo480}, // Inst #6084 = WHILELE_PXX_H + {3, OperandInfo480}, // Inst #6085 = WHILELE_PXX_S + {3, OperandInfo479}, // Inst #6086 = WHILELO_PWW_B + {3, OperandInfo479}, // Inst #6087 = WHILELO_PWW_D + {3, OperandInfo479}, // Inst #6088 = WHILELO_PWW_H + {3, OperandInfo479}, // Inst #6089 = WHILELO_PWW_S + {3, OperandInfo480}, // Inst #6090 = WHILELO_PXX_B + {3, OperandInfo480}, // Inst #6091 = WHILELO_PXX_D + {3, OperandInfo480}, // Inst #6092 = WHILELO_PXX_H + {3, OperandInfo480}, // Inst #6093 = WHILELO_PXX_S + {3, OperandInfo479}, // Inst #6094 = WHILELS_PWW_B + {3, OperandInfo479}, // Inst #6095 = WHILELS_PWW_D + {3, OperandInfo479}, // Inst #6096 = WHILELS_PWW_H + {3, OperandInfo479}, // Inst #6097 = WHILELS_PWW_S + {3, OperandInfo480}, // Inst #6098 = WHILELS_PXX_B + {3, OperandInfo480}, // Inst #6099 = WHILELS_PXX_D + {3, OperandInfo480}, // Inst #6100 = WHILELS_PXX_H + {3, OperandInfo480}, // Inst #6101 = WHILELS_PXX_S + {3, OperandInfo479}, // Inst #6102 = WHILELT_PWW_B + {3, OperandInfo479}, // Inst #6103 = WHILELT_PWW_D + {3, OperandInfo479}, // Inst #6104 = WHILELT_PWW_H + {3, OperandInfo479}, // Inst #6105 = WHILELT_PWW_S + {3, OperandInfo480}, // Inst #6106 = WHILELT_PXX_B + {3, OperandInfo480}, // Inst #6107 = WHILELT_PXX_D + {3, OperandInfo480}, // Inst #6108 = WHILELT_PXX_H + {3, OperandInfo480}, // Inst #6109 = WHILELT_PXX_S + {3, OperandInfo480}, // Inst #6110 = WHILERW_PXX_B + {3, OperandInfo480}, // Inst #6111 = WHILERW_PXX_D + {3, OperandInfo480}, // Inst #6112 = WHILERW_PXX_H + {3, OperandInfo480}, // Inst #6113 = WHILERW_PXX_S + {3, OperandInfo480}, // Inst #6114 = WHILEWR_PXX_B + {3, OperandInfo480}, // Inst #6115 = WHILEWR_PXX_D + {3, OperandInfo480}, // Inst #6116 = WHILEWR_PXX_H + {3, OperandInfo480}, // Inst #6117 = WHILEWR_PXX_S + {1, OperandInfo77}, // Inst #6118 = WRFFR + {0, NULL}, // Inst #6119 = XAFLAG + {4, OperandInfo58}, // Inst #6120 = XAR + {4, OperandInfo153}, // Inst #6121 = XAR_ZZZI_B + {4, OperandInfo153}, // Inst #6122 = XAR_ZZZI_D + {4, OperandInfo153}, // Inst #6123 = XAR_ZZZI_H + {4, OperandInfo153}, // Inst #6124 = XAR_ZZZI_S + {2, OperandInfo136}, // Inst #6125 = XPACD + {2, OperandInfo136}, // Inst #6126 = XPACI + {0, NULL}, // Inst #6127 = XPACLRI + {3, OperandInfo124}, // Inst #6128 = XTNv16i8 + {2, OperandInfo103}, // Inst #6129 = XTNv2i32 + {2, OperandInfo103}, // Inst #6130 = XTNv4i16 + {3, OperandInfo124}, // Inst #6131 = XTNv4i32 + {3, OperandInfo124}, // Inst #6132 = XTNv8i16 + {2, OperandInfo103}, // Inst #6133 = XTNv8i8 + {1, OperandInfo2}, // Inst #6134 = ZERO_M + {3, OperandInfo149}, // Inst #6135 = ZIP1_PPP_B + {3, OperandInfo149}, // Inst #6136 = ZIP1_PPP_D + {3, OperandInfo149}, // Inst #6137 = ZIP1_PPP_H + {3, OperandInfo149}, // Inst #6138 = ZIP1_PPP_S + {3, OperandInfo96}, // Inst #6139 = ZIP1_ZZZ_B + {3, OperandInfo96}, // Inst #6140 = ZIP1_ZZZ_D + {3, OperandInfo96}, // Inst #6141 = ZIP1_ZZZ_H + {3, OperandInfo96}, // Inst #6142 = ZIP1_ZZZ_Q + {3, OperandInfo96}, // Inst #6143 = ZIP1_ZZZ_S + {3, OperandInfo101}, // Inst #6144 = ZIP1v16i8 + {3, OperandInfo102}, // Inst #6145 = ZIP1v2i32 + {3, OperandInfo101}, // Inst #6146 = ZIP1v2i64 + {3, OperandInfo102}, // Inst #6147 = ZIP1v4i16 + {3, OperandInfo101}, // Inst #6148 = ZIP1v4i32 + {3, OperandInfo101}, // Inst #6149 = ZIP1v8i16 + {3, OperandInfo102}, // Inst #6150 = ZIP1v8i8 + {3, OperandInfo149}, // Inst #6151 = ZIP2_PPP_B + {3, OperandInfo149}, // Inst #6152 = ZIP2_PPP_D + {3, OperandInfo149}, // Inst #6153 = ZIP2_PPP_H + {3, OperandInfo149}, // Inst #6154 = ZIP2_PPP_S + {3, OperandInfo96}, // Inst #6155 = ZIP2_ZZZ_B + {3, OperandInfo96}, // Inst #6156 = ZIP2_ZZZ_D + {3, OperandInfo96}, // Inst #6157 = ZIP2_ZZZ_H + {3, OperandInfo96}, // Inst #6158 = ZIP2_ZZZ_Q + {3, OperandInfo96}, // Inst #6159 = ZIP2_ZZZ_S + {3, OperandInfo101}, // Inst #6160 = ZIP2v16i8 + {3, OperandInfo102}, // Inst #6161 = ZIP2v2i32 + {3, OperandInfo101}, // Inst #6162 = ZIP2v2i64 + {3, OperandInfo102}, // Inst #6163 = ZIP2v4i16 + {3, OperandInfo101}, // Inst #6164 = ZIP2v4i32 + {3, OperandInfo101}, // Inst #6165 = ZIP2v8i16 + {3, OperandInfo102}, // Inst #6166 = ZIP2v8i8 + {5, OperandInfo256}, // Inst #6167 = anonymous_13653 + {5, OperandInfo256}, // Inst #6168 = anonymous_13654 + {5, OperandInfo256}, // Inst #6169 = anonymous_5364 + {5, OperandInfo256}, // Inst #6170 = anonymous_5365 +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +extern const char AArch64InstrNameData[] = { + /* 0 */ "G_FLOG10\0" + /* 9 */ "FMOVD0\0" + /* 16 */ "FMOVH0\0" + /* 23 */ "FMOVS0\0" + /* 30 */ "SHA512SU0\0" + /* 40 */ "ST64BV0\0" + /* 48 */ "ADR_LSL_ZZZ_D_0\0" + /* 64 */ "ADR_SXTW_ZZZ_D_0\0" + /* 81 */ "ADR_UXTW_ZZZ_D_0\0" + /* 98 */ "ADR_LSL_ZZZ_S_0\0" + /* 114 */ "UMOVvi32_idx0\0" + /* 128 */ "SMOVvi16to32_idx0\0" + /* 146 */ "SMOVvi8to32_idx0\0" + /* 163 */ "UMOVvi64_idx0\0" + /* 177 */ "SMOVvi32to64_idx0\0" + /* 195 */ "SMOVvi16to64_idx0\0" + /* 213 */ "SMOVvi8to64_idx0\0" + /* 230 */ "UMOVvi16_idx0\0" + /* 244 */ "UMOVvi8_idx0\0" + /* 257 */ "G_TRN1\0" + /* 264 */ "G_ZIP1\0" + /* 271 */ "G_UZP1\0" + /* 278 */ "DCPS1\0" + /* 284 */ "SM3SS1\0" + /* 291 */ "SHA512SU1\0" + /* 301 */ "SM3PARTW1\0" + /* 311 */ "RAX1\0" + /* 316 */ "ADR_LSL_ZZZ_D_1\0" + /* 332 */ "ADR_SXTW_ZZZ_D_1\0" + /* 349 */ "ADR_UXTW_ZZZ_D_1\0" + /* 366 */ "ADR_LSL_ZZZ_S_1\0" + /* 382 */ "MSRpstateImm1\0" + /* 396 */ "MSRpstatesvcrImm1\0" + /* 414 */ "FABD32\0" + /* 421 */ "FACGE32\0" + /* 429 */ "FCMGE32\0" + /* 437 */ "G_DUPLANE32\0" + /* 449 */ "FCMEQ32\0" + /* 457 */ "FRECPS32\0" + /* 466 */ "FRSQRTS32\0" + /* 476 */ "FACGT32\0" + /* 484 */ "FCMGT32\0" + /* 492 */ "G_REV32\0" + /* 500 */ "FMULX32\0" + /* 508 */ "CMP_SWAP_32\0" + /* 520 */ "FCMLAv2f32\0" + /* 531 */ "FMLAv2f32\0" + /* 541 */ "FRINTAv2f32\0" + /* 553 */ "FSUBv2f32\0" + /* 563 */ "FABDv2f32\0" + /* 573 */ "FCADDv2f32\0" + /* 584 */ "FADDv2f32\0" + /* 594 */ "FACGEv2f32\0" + /* 605 */ "FCMGEv2f32\0" + /* 616 */ "FRECPEv2f32\0" + /* 628 */ "FRSQRTEv2f32\0" + /* 641 */ "SCVTFv2f32\0" + /* 652 */ "UCVTFv2f32\0" + /* 663 */ "FNEGv2f32\0" + /* 673 */ "FRINTIv2f32\0" + /* 685 */ "FMULv2f32\0" + /* 695 */ "FMINNMv2f32\0" + /* 707 */ "FMAXNMv2f32\0" + /* 719 */ "FRINTMv2f32\0" + /* 731 */ "FMINv2f32\0" + /* 741 */ "FRINTNv2f32\0" + /* 753 */ "FCVTXNv2f32\0" + /* 765 */ "FADDPv2f32\0" + /* 776 */ "FMINNMPv2f32\0" + /* 789 */ "FMAXNMPv2f32\0" + /* 802 */ "FMINPv2f32\0" + /* 813 */ "FRINTPv2f32\0" + /* 825 */ "FMAXPv2f32\0" + /* 836 */ "FCMEQv2f32\0" + /* 847 */ "FCVTASv2f32\0" + /* 859 */ "FABSv2f32\0" + /* 869 */ "FMLSv2f32\0" + /* 879 */ "FCVTMSv2f32\0" + /* 891 */ "FCVTNSv2f32\0" + /* 903 */ "FRECPSv2f32\0" + /* 915 */ "FCVTPSv2f32\0" + /* 927 */ "FRSQRTSv2f32\0" + /* 940 */ "FCVTZSv2f32\0" + /* 952 */ "FACGTv2f32\0" + /* 963 */ "FCMGTv2f32\0" + /* 974 */ "FSQRTv2f32\0" + /* 985 */ "FCVTAUv2f32\0" + /* 997 */ "FCVTMUv2f32\0" + /* 1009 */ "FCVTNUv2f32\0" + /* 1021 */ "FCVTPUv2f32\0" + /* 1033 */ "FCVTZUv2f32\0" + /* 1045 */ "FDIVv2f32\0" + /* 1055 */ "FRINT32Xv2f32\0" + /* 1069 */ "FRINT64Xv2f32\0" + /* 1083 */ "FMAXv2f32\0" + /* 1093 */ "FMULXv2f32\0" + /* 1104 */ "FRINTXv2f32\0" + /* 1116 */ "FRINT32Zv2f32\0" + /* 1130 */ "FRINT64Zv2f32\0" + /* 1144 */ "FRINTZv2f32\0" + /* 1156 */ "FCMLAv4f32\0" + /* 1167 */ "FMLAv4f32\0" + /* 1177 */ "FRINTAv4f32\0" + /* 1189 */ "FSUBv4f32\0" + /* 1199 */ "FABDv4f32\0" + /* 1209 */ "FCADDv4f32\0" + /* 1220 */ "FADDv4f32\0" + /* 1230 */ "FACGEv4f32\0" + /* 1241 */ "FCMGEv4f32\0" + /* 1252 */ "FRECPEv4f32\0" + /* 1264 */ "FRSQRTEv4f32\0" + /* 1277 */ "SCVTFv4f32\0" + /* 1288 */ "UCVTFv4f32\0" + /* 1299 */ "FNEGv4f32\0" + /* 1309 */ "FRINTIv4f32\0" + /* 1321 */ "FMULv4f32\0" + /* 1331 */ "FMINNMv4f32\0" + /* 1343 */ "FMAXNMv4f32\0" + /* 1355 */ "FRINTMv4f32\0" + /* 1367 */ "FMINv4f32\0" + /* 1377 */ "FRINTNv4f32\0" + /* 1389 */ "FCVTXNv4f32\0" + /* 1401 */ "FADDPv4f32\0" + /* 1412 */ "FMINNMPv4f32\0" + /* 1425 */ "FMAXNMPv4f32\0" + /* 1438 */ "FMINPv4f32\0" + /* 1449 */ "FRINTPv4f32\0" + /* 1461 */ "FMAXPv4f32\0" + /* 1472 */ "FCMEQv4f32\0" + /* 1483 */ "FCVTASv4f32\0" + /* 1495 */ "FABSv4f32\0" + /* 1505 */ "FMLSv4f32\0" + /* 1515 */ "FCVTMSv4f32\0" + /* 1527 */ "FCVTNSv4f32\0" + /* 1539 */ "FRECPSv4f32\0" + /* 1551 */ "FCVTPSv4f32\0" + /* 1563 */ "FRSQRTSv4f32\0" + /* 1576 */ "FCVTZSv4f32\0" + /* 1588 */ "FACGTv4f32\0" + /* 1599 */ "FCMGTv4f32\0" + /* 1610 */ "FSQRTv4f32\0" + /* 1621 */ "FCVTAUv4f32\0" + /* 1633 */ "FCVTMUv4f32\0" + /* 1645 */ "FCVTNUv4f32\0" + /* 1657 */ "FCVTPUv4f32\0" + /* 1669 */ "FCVTZUv4f32\0" + /* 1681 */ "FDIVv4f32\0" + /* 1691 */ "FRINT32Xv4f32\0" + /* 1705 */ "FRINT64Xv4f32\0" + /* 1719 */ "FMAXv4f32\0" + /* 1729 */ "FMULXv4f32\0" + /* 1740 */ "FRINTXv4f32\0" + /* 1752 */ "FRINT32Zv4f32\0" + /* 1766 */ "FRINT64Zv4f32\0" + /* 1780 */ "FRINTZv4f32\0" + /* 1792 */ "LD1i32\0" + /* 1799 */ "ST1i32\0" + /* 1806 */ "SQSUBv1i32\0" + /* 1817 */ "UQSUBv1i32\0" + /* 1828 */ "USQADDv1i32\0" + /* 1840 */ "SUQADDv1i32\0" + /* 1852 */ "FRECPEv1i32\0" + /* 1864 */ "FRSQRTEv1i32\0" + /* 1877 */ "SCVTFv1i32\0" + /* 1888 */ "UCVTFv1i32\0" + /* 1899 */ "SQNEGv1i32\0" + /* 1910 */ "SQRDMLAHv1i32\0" + /* 1924 */ "SQDMULHv1i32\0" + /* 1937 */ "SQRDMULHv1i32\0" + /* 1951 */ "SQRDMLSHv1i32\0" + /* 1965 */ "SQSHLv1i32\0" + /* 1976 */ "UQSHLv1i32\0" + /* 1987 */ "SQRSHLv1i32\0" + /* 1999 */ "UQRSHLv1i32\0" + /* 2011 */ "SQXTNv1i32\0" + /* 2022 */ "UQXTNv1i32\0" + /* 2033 */ "SQXTUNv1i32\0" + /* 2045 */ "FCVTASv1i32\0" + /* 2057 */ "SQABSv1i32\0" + /* 2068 */ "FCVTMSv1i32\0" + /* 2080 */ "FCVTNSv1i32\0" + /* 2092 */ "FCVTPSv1i32\0" + /* 2104 */ "FCVTZSv1i32\0" + /* 2116 */ "FCVTAUv1i32\0" + /* 2128 */ "FCVTMUv1i32\0" + /* 2140 */ "FCVTNUv1i32\0" + /* 2152 */ "FCVTPUv1i32\0" + /* 2164 */ "FCVTZUv1i32\0" + /* 2176 */ "FRECPXv1i32\0" + /* 2188 */ "LD2i32\0" + /* 2195 */ "ST2i32\0" + /* 2202 */ "TRN1v2i32\0" + /* 2212 */ "ZIP1v2i32\0" + /* 2222 */ "UZP1v2i32\0" + /* 2232 */ "TRN2v2i32\0" + /* 2242 */ "ZIP2v2i32\0" + /* 2252 */ "UZP2v2i32\0" + /* 2262 */ "REV64v2i32\0" + /* 2273 */ "SABAv2i32\0" + /* 2283 */ "UABAv2i32\0" + /* 2293 */ "MLAv2i32\0" + /* 2302 */ "SHSUBv2i32\0" + /* 2313 */ "UHSUBv2i32\0" + /* 2324 */ "SQSUBv2i32\0" + /* 2335 */ "UQSUBv2i32\0" + /* 2346 */ "BICv2i32\0" + /* 2355 */ "SABDv2i32\0" + /* 2365 */ "UABDv2i32\0" + /* 2375 */ "SRHADDv2i32\0" + /* 2387 */ "URHADDv2i32\0" + /* 2399 */ "SHADDv2i32\0" + /* 2410 */ "UHADDv2i32\0" + /* 2421 */ "USQADDv2i32\0" + /* 2433 */ "SUQADDv2i32\0" + /* 2445 */ "CMGEv2i32\0" + /* 2455 */ "URECPEv2i32\0" + /* 2467 */ "URSQRTEv2i32\0" + /* 2480 */ "SQNEGv2i32\0" + /* 2491 */ "SQRDMLAHv2i32\0" + /* 2505 */ "SQDMULHv2i32\0" + /* 2518 */ "SQRDMULHv2i32\0" + /* 2532 */ "SQRDMLSHv2i32\0" + /* 2546 */ "CMHIv2i32\0" + /* 2556 */ "MVNIv2i32\0" + /* 2566 */ "MOVIv2i32\0" + /* 2576 */ "SQSHLv2i32\0" + /* 2587 */ "UQSHLv2i32\0" + /* 2598 */ "SQRSHLv2i32\0" + /* 2610 */ "UQRSHLv2i32\0" + /* 2622 */ "SRSHLv2i32\0" + /* 2633 */ "URSHLv2i32\0" + /* 2644 */ "SSHLv2i32\0" + /* 2654 */ "USHLv2i32\0" + /* 2664 */ "SHLLv2i32\0" + /* 2674 */ "FCVTLv2i32\0" + /* 2685 */ "MULv2i32\0" + /* 2694 */ "SMINv2i32\0" + /* 2704 */ "UMINv2i32\0" + /* 2714 */ "FCVTNv2i32\0" + /* 2725 */ "SQXTNv2i32\0" + /* 2736 */ "UQXTNv2i32\0" + /* 2747 */ "SQXTUNv2i32\0" + /* 2759 */ "ADDPv2i32\0" + /* 2769 */ "SMINPv2i32\0" + /* 2780 */ "UMINPv2i32\0" + /* 2791 */ "SMAXPv2i32\0" + /* 2802 */ "UMAXPv2i32\0" + /* 2813 */ "CMEQv2i32\0" + /* 2823 */ "ORRv2i32\0" + /* 2832 */ "SQABSv2i32\0" + /* 2843 */ "CMHSv2i32\0" + /* 2853 */ "CLSv2i32\0" + /* 2862 */ "MLSv2i32\0" + /* 2871 */ "CMGTv2i32\0" + /* 2881 */ "CMTSTv2i32\0" + /* 2892 */ "SMAXv2i32\0" + /* 2902 */ "UMAXv2i32\0" + /* 2912 */ "CLZv2i32\0" + /* 2921 */ "RSUBHNv2i64_v2i32\0" + /* 2939 */ "RADDHNv2i64_v2i32\0" + /* 2957 */ "SADALPv4i16_v2i32\0" + /* 2975 */ "UADALPv4i16_v2i32\0" + /* 2993 */ "SADDLPv4i16_v2i32\0" + /* 3011 */ "UADDLPv4i16_v2i32\0" + /* 3029 */ "LD3i32\0" + /* 3036 */ "ST3i32\0" + /* 3043 */ "LD4i32\0" + /* 3050 */ "ST4i32\0" + /* 3057 */ "TRN1v4i32\0" + /* 3067 */ "ZIP1v4i32\0" + /* 3077 */ "UZP1v4i32\0" + /* 3087 */ "TRN2v4i32\0" + /* 3097 */ "ZIP2v4i32\0" + /* 3107 */ "UZP2v4i32\0" + /* 3117 */ "REV64v4i32\0" + /* 3128 */ "SABAv4i32\0" + /* 3138 */ "UABAv4i32\0" + /* 3148 */ "MLAv4i32\0" + /* 3157 */ "SHSUBv4i32\0" + /* 3168 */ "UHSUBv4i32\0" + /* 3179 */ "SQSUBv4i32\0" + /* 3190 */ "UQSUBv4i32\0" + /* 3201 */ "BICv4i32\0" + /* 3210 */ "SABDv4i32\0" + /* 3220 */ "UABDv4i32\0" + /* 3230 */ "SRHADDv4i32\0" + /* 3242 */ "URHADDv4i32\0" + /* 3254 */ "SHADDv4i32\0" + /* 3265 */ "UHADDv4i32\0" + /* 3276 */ "USQADDv4i32\0" + /* 3288 */ "SUQADDv4i32\0" + /* 3300 */ "CMGEv4i32\0" + /* 3310 */ "URECPEv4i32\0" + /* 3322 */ "URSQRTEv4i32\0" + /* 3335 */ "SQNEGv4i32\0" + /* 3346 */ "SQRDMLAHv4i32\0" + /* 3360 */ "SQDMULHv4i32\0" + /* 3373 */ "SQRDMULHv4i32\0" + /* 3387 */ "SQRDMLSHv4i32\0" + /* 3401 */ "CMHIv4i32\0" + /* 3411 */ "MVNIv4i32\0" + /* 3421 */ "MOVIv4i32\0" + /* 3431 */ "SQSHLv4i32\0" + /* 3442 */ "UQSHLv4i32\0" + /* 3453 */ "SQRSHLv4i32\0" + /* 3465 */ "UQRSHLv4i32\0" + /* 3477 */ "SRSHLv4i32\0" + /* 3488 */ "URSHLv4i32\0" + /* 3499 */ "SSHLv4i32\0" + /* 3509 */ "USHLv4i32\0" + /* 3519 */ "SHLLv4i32\0" + /* 3529 */ "FCVTLv4i32\0" + /* 3540 */ "MULv4i32\0" + /* 3549 */ "SMINv4i32\0" + /* 3559 */ "UMINv4i32\0" + /* 3569 */ "FCVTNv4i32\0" + /* 3580 */ "SQXTNv4i32\0" + /* 3591 */ "UQXTNv4i32\0" + /* 3602 */ "SQXTUNv4i32\0" + /* 3614 */ "ADDPv4i32\0" + /* 3624 */ "SMINPv4i32\0" + /* 3635 */ "UMINPv4i32\0" + /* 3646 */ "SMAXPv4i32\0" + /* 3657 */ "UMAXPv4i32\0" + /* 3668 */ "CMEQv4i32\0" + /* 3678 */ "ORRv4i32\0" + /* 3687 */ "SQABSv4i32\0" + /* 3698 */ "CMHSv4i32\0" + /* 3708 */ "CLSv4i32\0" + /* 3717 */ "MLSv4i32\0" + /* 3726 */ "CMGTv4i32\0" + /* 3736 */ "CMTSTv4i32\0" + /* 3747 */ "SMAXv4i32\0" + /* 3757 */ "UMAXv4i32\0" + /* 3767 */ "CLZv4i32\0" + /* 3776 */ "RSUBHNv2i64_v4i32\0" + /* 3794 */ "RADDHNv2i64_v4i32\0" + /* 3812 */ "SABALv4i16_v4i32\0" + /* 3829 */ "UABALv4i16_v4i32\0" + /* 3846 */ "SQDMLALv4i16_v4i32\0" + /* 3865 */ "SMLALv4i16_v4i32\0" + /* 3882 */ "UMLALv4i16_v4i32\0" + /* 3899 */ "SSUBLv4i16_v4i32\0" + /* 3916 */ "USUBLv4i16_v4i32\0" + /* 3933 */ "SABDLv4i16_v4i32\0" + /* 3950 */ "UABDLv4i16_v4i32\0" + /* 3967 */ "SADDLv4i16_v4i32\0" + /* 3984 */ "UADDLv4i16_v4i32\0" + /* 4001 */ "SQDMULLv4i16_v4i32\0" + /* 4020 */ "SMULLv4i16_v4i32\0" + /* 4037 */ "UMULLv4i16_v4i32\0" + /* 4054 */ "SQDMLSLv4i16_v4i32\0" + /* 4073 */ "SMLSLv4i16_v4i32\0" + /* 4090 */ "UMLSLv4i16_v4i32\0" + /* 4107 */ "SSUBWv4i16_v4i32\0" + /* 4124 */ "USUBWv4i16_v4i32\0" + /* 4141 */ "SADDWv4i16_v4i32\0" + /* 4158 */ "UADDWv4i16_v4i32\0" + /* 4175 */ "SABALv8i16_v4i32\0" + /* 4192 */ "UABALv8i16_v4i32\0" + /* 4209 */ "SQDMLALv8i16_v4i32\0" + /* 4228 */ "SMLALv8i16_v4i32\0" + /* 4245 */ "UMLALv8i16_v4i32\0" + /* 4262 */ "SSUBLv8i16_v4i32\0" + /* 4279 */ "USUBLv8i16_v4i32\0" + /* 4296 */ "SABDLv8i16_v4i32\0" + /* 4313 */ "UABDLv8i16_v4i32\0" + /* 4330 */ "SADDLv8i16_v4i32\0" + /* 4347 */ "UADDLv8i16_v4i32\0" + /* 4364 */ "SQDMULLv8i16_v4i32\0" + /* 4383 */ "SMULLv8i16_v4i32\0" + /* 4400 */ "UMULLv8i16_v4i32\0" + /* 4417 */ "SQDMLSLv8i16_v4i32\0" + /* 4436 */ "SMLSLv8i16_v4i32\0" + /* 4453 */ "UMLSLv8i16_v4i32\0" + /* 4470 */ "SADALPv8i16_v4i32\0" + /* 4488 */ "UADALPv8i16_v4i32\0" + /* 4506 */ "SADDLPv8i16_v4i32\0" + /* 4524 */ "UADDLPv8i16_v4i32\0" + /* 4542 */ "SSUBWv8i16_v4i32\0" + /* 4559 */ "USUBWv8i16_v4i32\0" + /* 4576 */ "SADDWv8i16_v4i32\0" + /* 4593 */ "UADDWv8i16_v4i32\0" + /* 4610 */ "SQDMLALi32\0" + /* 4621 */ "SQDMULLi32\0" + /* 4632 */ "SQDMLSLi32\0" + /* 4643 */ "CPYi32\0" + /* 4650 */ "UMOVvi32\0" + /* 4659 */ "SMOVvi16to32\0" + /* 4672 */ "SMOVvi8to32\0" + /* 4684 */ "JumpTableDest32\0" + /* 4700 */ "G_FLOG2\0" + /* 4708 */ "SHA512H2\0" + /* 4717 */ "G_TRN2\0" + /* 4724 */ "BFCVTN2\0" + /* 4732 */ "G_ZIP2\0" + /* 4739 */ "G_FEXP2\0" + /* 4747 */ "G_UZP2\0" + /* 4754 */ "DCPS2\0" + /* 4760 */ "SM3PARTW2\0" + /* 4770 */ "ADR_LSL_ZZZ_D_2\0" + /* 4786 */ "ADR_SXTW_ZZZ_D_2\0" + /* 4803 */ "ADR_UXTW_ZZZ_D_2\0" + /* 4820 */ "ADR_LSL_ZZZ_S_2\0" + /* 4836 */ "anonymous_13653\0" + /* 4852 */ "EOR3\0" + /* 4857 */ "DCPS3\0" + /* 4863 */ "ADR_LSL_ZZZ_D_3\0" + /* 4879 */ "ADR_SXTW_ZZZ_D_3\0" + /* 4896 */ "ADR_UXTW_ZZZ_D_3\0" + /* 4913 */ "ADR_LSL_ZZZ_S_3\0" + /* 4929 */ "anonymous_13654\0" + /* 4945 */ "anonymous_5364\0" + /* 4960 */ "FABD64\0" + /* 4967 */ "FACGE64\0" + /* 4975 */ "FCMGE64\0" + /* 4983 */ "G_DUPLANE64\0" + /* 4995 */ "FCMEQ64\0" + /* 5003 */ "FRECPS64\0" + /* 5012 */ "FRSQRTS64\0" + /* 5022 */ "FACGT64\0" + /* 5030 */ "FCMGT64\0" + /* 5038 */ "G_REV64\0" + /* 5046 */ "FMULX64\0" + /* 5054 */ "CMP_SWAP_64\0" + /* 5066 */ "FCMLAv2f64\0" + /* 5077 */ "FMLAv2f64\0" + /* 5087 */ "FRINTAv2f64\0" + /* 5099 */ "FSUBv2f64\0" + /* 5109 */ "FABDv2f64\0" + /* 5119 */ "FCADDv2f64\0" + /* 5130 */ "FADDv2f64\0" + /* 5140 */ "FACGEv2f64\0" + /* 5151 */ "FCMGEv2f64\0" + /* 5162 */ "FRECPEv2f64\0" + /* 5174 */ "FRSQRTEv2f64\0" + /* 5187 */ "SCVTFv2f64\0" + /* 5198 */ "UCVTFv2f64\0" + /* 5209 */ "FNEGv2f64\0" + /* 5219 */ "FRINTIv2f64\0" + /* 5231 */ "FMULv2f64\0" + /* 5241 */ "FMINNMv2f64\0" + /* 5253 */ "FMAXNMv2f64\0" + /* 5265 */ "FRINTMv2f64\0" + /* 5277 */ "FMINv2f64\0" + /* 5287 */ "FRINTNv2f64\0" + /* 5299 */ "FADDPv2f64\0" + /* 5310 */ "FMINNMPv2f64\0" + /* 5323 */ "FMAXNMPv2f64\0" + /* 5336 */ "FMINPv2f64\0" + /* 5347 */ "FRINTPv2f64\0" + /* 5359 */ "FMAXPv2f64\0" + /* 5370 */ "FCMEQv2f64\0" + /* 5381 */ "FCVTASv2f64\0" + /* 5393 */ "FABSv2f64\0" + /* 5403 */ "FMLSv2f64\0" + /* 5413 */ "FCVTMSv2f64\0" + /* 5425 */ "FCVTNSv2f64\0" + /* 5437 */ "FRECPSv2f64\0" + /* 5449 */ "FCVTPSv2f64\0" + /* 5461 */ "FRSQRTSv2f64\0" + /* 5474 */ "FCVTZSv2f64\0" + /* 5486 */ "FACGTv2f64\0" + /* 5497 */ "FCMGTv2f64\0" + /* 5508 */ "FSQRTv2f64\0" + /* 5519 */ "FCVTAUv2f64\0" + /* 5531 */ "FCVTMUv2f64\0" + /* 5543 */ "FCVTNUv2f64\0" + /* 5555 */ "FCVTPUv2f64\0" + /* 5567 */ "FCVTZUv2f64\0" + /* 5579 */ "FDIVv2f64\0" + /* 5589 */ "FRINT32Xv2f64\0" + /* 5603 */ "FRINT64Xv2f64\0" + /* 5617 */ "FMAXv2f64\0" + /* 5627 */ "FMULXv2f64\0" + /* 5638 */ "FRINTXv2f64\0" + /* 5650 */ "FRINT32Zv2f64\0" + /* 5664 */ "FRINT64Zv2f64\0" + /* 5678 */ "FRINTZv2f64\0" + /* 5690 */ "LD1i64\0" + /* 5697 */ "ST1i64\0" + /* 5704 */ "SQSUBv1i64\0" + /* 5715 */ "UQSUBv1i64\0" + /* 5726 */ "USQADDv1i64\0" + /* 5738 */ "SUQADDv1i64\0" + /* 5750 */ "CMGEv1i64\0" + /* 5760 */ "FRECPEv1i64\0" + /* 5772 */ "FRSQRTEv1i64\0" + /* 5785 */ "SCVTFv1i64\0" + /* 5796 */ "UCVTFv1i64\0" + /* 5807 */ "SQNEGv1i64\0" + /* 5818 */ "CMHIv1i64\0" + /* 5828 */ "SQSHLv1i64\0" + /* 5839 */ "UQSHLv1i64\0" + /* 5850 */ "SQRSHLv1i64\0" + /* 5862 */ "UQRSHLv1i64\0" + /* 5874 */ "SRSHLv1i64\0" + /* 5885 */ "URSHLv1i64\0" + /* 5896 */ "SSHLv1i64\0" + /* 5906 */ "USHLv1i64\0" + /* 5916 */ "PMULLv1i64\0" + /* 5927 */ "FCVTXNv1i64\0" + /* 5939 */ "CMEQv1i64\0" + /* 5949 */ "FCVTASv1i64\0" + /* 5961 */ "SQABSv1i64\0" + /* 5972 */ "CMHSv1i64\0" + /* 5982 */ "FCVTMSv1i64\0" + /* 5994 */ "FCVTNSv1i64\0" + /* 6006 */ "FCVTPSv1i64\0" + /* 6018 */ "FCVTZSv1i64\0" + /* 6030 */ "CMGTv1i64\0" + /* 6040 */ "CMTSTv1i64\0" + /* 6051 */ "FCVTAUv1i64\0" + /* 6063 */ "FCVTMUv1i64\0" + /* 6075 */ "FCVTNUv1i64\0" + /* 6087 */ "FCVTPUv1i64\0" + /* 6099 */ "FCVTZUv1i64\0" + /* 6111 */ "FRECPXv1i64\0" + /* 6123 */ "SADALPv2i32_v1i64\0" + /* 6141 */ "UADALPv2i32_v1i64\0" + /* 6159 */ "SADDLPv2i32_v1i64\0" + /* 6177 */ "UADDLPv2i32_v1i64\0" + /* 6195 */ "LD2i64\0" + /* 6202 */ "ST2i64\0" + /* 6209 */ "TRN1v2i64\0" + /* 6219 */ "ZIP1v2i64\0" + /* 6229 */ "UZP1v2i64\0" + /* 6239 */ "TRN2v2i64\0" + /* 6249 */ "ZIP2v2i64\0" + /* 6259 */ "UZP2v2i64\0" + /* 6269 */ "SQSUBv2i64\0" + /* 6280 */ "UQSUBv2i64\0" + /* 6291 */ "USQADDv2i64\0" + /* 6303 */ "SUQADDv2i64\0" + /* 6315 */ "CMGEv2i64\0" + /* 6325 */ "SQNEGv2i64\0" + /* 6336 */ "CMHIv2i64\0" + /* 6346 */ "SQSHLv2i64\0" + /* 6357 */ "UQSHLv2i64\0" + /* 6368 */ "SQRSHLv2i64\0" + /* 6380 */ "UQRSHLv2i64\0" + /* 6392 */ "SRSHLv2i64\0" + /* 6403 */ "URSHLv2i64\0" + /* 6414 */ "SSHLv2i64\0" + /* 6424 */ "USHLv2i64\0" + /* 6434 */ "PMULLv2i64\0" + /* 6445 */ "ADDPv2i64\0" + /* 6455 */ "CMEQv2i64\0" + /* 6465 */ "SQABSv2i64\0" + /* 6476 */ "CMHSv2i64\0" + /* 6486 */ "CMGTv2i64\0" + /* 6496 */ "CMTSTv2i64\0" + /* 6507 */ "SABALv2i32_v2i64\0" + /* 6524 */ "UABALv2i32_v2i64\0" + /* 6541 */ "SQDMLALv2i32_v2i64\0" + /* 6560 */ "SMLALv2i32_v2i64\0" + /* 6577 */ "UMLALv2i32_v2i64\0" + /* 6594 */ "SSUBLv2i32_v2i64\0" + /* 6611 */ "USUBLv2i32_v2i64\0" + /* 6628 */ "SABDLv2i32_v2i64\0" + /* 6645 */ "UABDLv2i32_v2i64\0" + /* 6662 */ "SADDLv2i32_v2i64\0" + /* 6679 */ "UADDLv2i32_v2i64\0" + /* 6696 */ "SQDMULLv2i32_v2i64\0" + /* 6715 */ "SMULLv2i32_v2i64\0" + /* 6732 */ "UMULLv2i32_v2i64\0" + /* 6749 */ "SQDMLSLv2i32_v2i64\0" + /* 6768 */ "SMLSLv2i32_v2i64\0" + /* 6785 */ "UMLSLv2i32_v2i64\0" + /* 6802 */ "SSUBWv2i32_v2i64\0" + /* 6819 */ "USUBWv2i32_v2i64\0" + /* 6836 */ "SADDWv2i32_v2i64\0" + /* 6853 */ "UADDWv2i32_v2i64\0" + /* 6870 */ "SABALv4i32_v2i64\0" + /* 6887 */ "UABALv4i32_v2i64\0" + /* 6904 */ "SQDMLALv4i32_v2i64\0" + /* 6923 */ "SMLALv4i32_v2i64\0" + /* 6940 */ "UMLALv4i32_v2i64\0" + /* 6957 */ "SSUBLv4i32_v2i64\0" + /* 6974 */ "USUBLv4i32_v2i64\0" + /* 6991 */ "SABDLv4i32_v2i64\0" + /* 7008 */ "UABDLv4i32_v2i64\0" + /* 7025 */ "SADDLv4i32_v2i64\0" + /* 7042 */ "UADDLv4i32_v2i64\0" + /* 7059 */ "SQDMULLv4i32_v2i64\0" + /* 7078 */ "SMULLv4i32_v2i64\0" + /* 7095 */ "UMULLv4i32_v2i64\0" + /* 7112 */ "SQDMLSLv4i32_v2i64\0" + /* 7131 */ "SMLSLv4i32_v2i64\0" + /* 7148 */ "UMLSLv4i32_v2i64\0" + /* 7165 */ "SADALPv4i32_v2i64\0" + /* 7183 */ "UADALPv4i32_v2i64\0" + /* 7201 */ "SADDLPv4i32_v2i64\0" + /* 7219 */ "UADDLPv4i32_v2i64\0" + /* 7237 */ "SSUBWv4i32_v2i64\0" + /* 7254 */ "USUBWv4i32_v2i64\0" + /* 7271 */ "SADDWv4i32_v2i64\0" + /* 7288 */ "UADDWv4i32_v2i64\0" + /* 7305 */ "LD3i64\0" + /* 7312 */ "ST3i64\0" + /* 7319 */ "LD4i64\0" + /* 7326 */ "ST4i64\0" + /* 7333 */ "CPYi64\0" + /* 7340 */ "UMOVvi64\0" + /* 7349 */ "SMOVvi32to64\0" + /* 7362 */ "SMOVvi16to64\0" + /* 7375 */ "SMOVvi8to64\0" + /* 7387 */ "SUBXrx64\0" + /* 7396 */ "ADDXrx64\0" + /* 7405 */ "SUBSXrx64\0" + /* 7415 */ "ADDSXrx64\0" + /* 7425 */ "MSRpstateImm4\0" + /* 7439 */ "anonymous_5365\0" + /* 7454 */ "PACIA1716\0" + /* 7464 */ "AUTIA1716\0" + /* 7474 */ "PACIB1716\0" + /* 7484 */ "AUTIB1716\0" + /* 7494 */ "FABD16\0" + /* 7501 */ "FACGE16\0" + /* 7509 */ "FCMGE16\0" + /* 7517 */ "G_DUPLANE16\0" + /* 7529 */ "SETF16\0" + /* 7536 */ "FCMEQ16\0" + /* 7544 */ "FRECPS16\0" + /* 7553 */ "FRSQRTS16\0" + /* 7563 */ "FACGT16\0" + /* 7571 */ "FCMGT16\0" + /* 7579 */ "G_REV16\0" + /* 7587 */ "FMULX16\0" + /* 7595 */ "CMP_SWAP_16\0" + /* 7607 */ "FRECPEv1f16\0" + /* 7619 */ "FRSQRTEv1f16\0" + /* 7632 */ "FCVTASv1f16\0" + /* 7644 */ "FCVTMSv1f16\0" + /* 7656 */ "FCVTNSv1f16\0" + /* 7668 */ "FCVTPSv1f16\0" + /* 7680 */ "FCVTZSv1f16\0" + /* 7692 */ "FCVTAUv1f16\0" + /* 7704 */ "FCVTMUv1f16\0" + /* 7716 */ "FCVTNUv1f16\0" + /* 7728 */ "FCVTPUv1f16\0" + /* 7740 */ "FCVTZUv1f16\0" + /* 7752 */ "FRECPXv1f16\0" + /* 7764 */ "FMLAL2v4f16\0" + /* 7776 */ "FMLSL2v4f16\0" + /* 7788 */ "FCMLAv4f16\0" + /* 7799 */ "FMLAv4f16\0" + /* 7809 */ "FRINTAv4f16\0" + /* 7821 */ "FSUBv4f16\0" + /* 7831 */ "FABDv4f16\0" + /* 7841 */ "FCADDv4f16\0" + /* 7852 */ "FADDv4f16\0" + /* 7862 */ "FACGEv4f16\0" + /* 7873 */ "FCMGEv4f16\0" + /* 7884 */ "FRECPEv4f16\0" + /* 7896 */ "FRSQRTEv4f16\0" + /* 7909 */ "SCVTFv4f16\0" + /* 7920 */ "UCVTFv4f16\0" + /* 7931 */ "FNEGv4f16\0" + /* 7941 */ "FRINTIv4f16\0" + /* 7953 */ "FMLALv4f16\0" + /* 7964 */ "FMLSLv4f16\0" + /* 7975 */ "FMULv4f16\0" + /* 7985 */ "FMINNMv4f16\0" + /* 7997 */ "FMAXNMv4f16\0" + /* 8009 */ "FRINTMv4f16\0" + /* 8021 */ "FMINv4f16\0" + /* 8031 */ "FRINTNv4f16\0" + /* 8043 */ "FADDPv4f16\0" + /* 8054 */ "FMINNMPv4f16\0" + /* 8067 */ "FMAXNMPv4f16\0" + /* 8080 */ "FMINPv4f16\0" + /* 8091 */ "FRINTPv4f16\0" + /* 8103 */ "FMAXPv4f16\0" + /* 8114 */ "FCMEQv4f16\0" + /* 8125 */ "FCVTASv4f16\0" + /* 8137 */ "FABSv4f16\0" + /* 8147 */ "FMLSv4f16\0" + /* 8157 */ "FCVTMSv4f16\0" + /* 8169 */ "FCVTNSv4f16\0" + /* 8181 */ "FRECPSv4f16\0" + /* 8193 */ "FCVTPSv4f16\0" + /* 8205 */ "FRSQRTSv4f16\0" + /* 8218 */ "FCVTZSv4f16\0" + /* 8230 */ "FACGTv4f16\0" + /* 8241 */ "FCMGTv4f16\0" + /* 8252 */ "FSQRTv4f16\0" + /* 8263 */ "FCVTAUv4f16\0" + /* 8275 */ "FCVTMUv4f16\0" + /* 8287 */ "FCVTNUv4f16\0" + /* 8299 */ "FCVTPUv4f16\0" + /* 8311 */ "FCVTZUv4f16\0" + /* 8323 */ "FDIVv4f16\0" + /* 8333 */ "FMAXv4f16\0" + /* 8343 */ "FMULXv4f16\0" + /* 8354 */ "FRINTXv4f16\0" + /* 8366 */ "FRINTZv4f16\0" + /* 8378 */ "FMLAL2lanev4f16\0" + /* 8394 */ "FMLSL2lanev4f16\0" + /* 8410 */ "FMLALlanev4f16\0" + /* 8425 */ "FMLSLlanev4f16\0" + /* 8440 */ "FMLAL2v8f16\0" + /* 8452 */ "FMLSL2v8f16\0" + /* 8464 */ "FCMLAv8f16\0" + /* 8475 */ "FMLAv8f16\0" + /* 8485 */ "FRINTAv8f16\0" + /* 8497 */ "FSUBv8f16\0" + /* 8507 */ "FABDv8f16\0" + /* 8517 */ "FCADDv8f16\0" + /* 8528 */ "FADDv8f16\0" + /* 8538 */ "FACGEv8f16\0" + /* 8549 */ "FCMGEv8f16\0" + /* 8560 */ "FRECPEv8f16\0" + /* 8572 */ "FRSQRTEv8f16\0" + /* 8585 */ "SCVTFv8f16\0" + /* 8596 */ "UCVTFv8f16\0" + /* 8607 */ "FNEGv8f16\0" + /* 8617 */ "FRINTIv8f16\0" + /* 8629 */ "FMLALv8f16\0" + /* 8640 */ "FMLSLv8f16\0" + /* 8651 */ "FMULv8f16\0" + /* 8661 */ "FMINNMv8f16\0" + /* 8673 */ "FMAXNMv8f16\0" + /* 8685 */ "FRINTMv8f16\0" + /* 8697 */ "FMINv8f16\0" + /* 8707 */ "FRINTNv8f16\0" + /* 8719 */ "FADDPv8f16\0" + /* 8730 */ "FMINNMPv8f16\0" + /* 8743 */ "FMAXNMPv8f16\0" + /* 8756 */ "FMINPv8f16\0" + /* 8767 */ "FRINTPv8f16\0" + /* 8779 */ "FMAXPv8f16\0" + /* 8790 */ "FCMEQv8f16\0" + /* 8801 */ "FCVTASv8f16\0" + /* 8813 */ "FABSv8f16\0" + /* 8823 */ "FMLSv8f16\0" + /* 8833 */ "FCVTMSv8f16\0" + /* 8845 */ "FCVTNSv8f16\0" + /* 8857 */ "FRECPSv8f16\0" + /* 8869 */ "FCVTPSv8f16\0" + /* 8881 */ "FRSQRTSv8f16\0" + /* 8894 */ "FCVTZSv8f16\0" + /* 8906 */ "FACGTv8f16\0" + /* 8917 */ "FCMGTv8f16\0" + /* 8928 */ "FSQRTv8f16\0" + /* 8939 */ "FCVTAUv8f16\0" + /* 8951 */ "FCVTMUv8f16\0" + /* 8963 */ "FCVTNUv8f16\0" + /* 8975 */ "FCVTPUv8f16\0" + /* 8987 */ "FCVTZUv8f16\0" + /* 8999 */ "FDIVv8f16\0" + /* 9009 */ "FMAXv8f16\0" + /* 9019 */ "FMULXv8f16\0" + /* 9030 */ "FRINTXv8f16\0" + /* 9042 */ "FRINTZv8f16\0" + /* 9054 */ "FMLAL2lanev8f16\0" + /* 9070 */ "FMLSL2lanev8f16\0" + /* 9086 */ "FMLALlanev8f16\0" + /* 9101 */ "FMLSLlanev8f16\0" + /* 9116 */ "BFDOTv4bf16\0" + /* 9128 */ "BF16DOTlanev4bf16\0" + /* 9146 */ "BFDOTv8bf16\0" + /* 9158 */ "BF16DOTlanev8bf16\0" + /* 9176 */ "LD1i16\0" + /* 9183 */ "ST1i16\0" + /* 9190 */ "SQSUBv1i16\0" + /* 9201 */ "UQSUBv1i16\0" + /* 9212 */ "USQADDv1i16\0" + /* 9224 */ "SUQADDv1i16\0" + /* 9236 */ "SCVTFv1i16\0" + /* 9247 */ "UCVTFv1i16\0" + /* 9258 */ "SQNEGv1i16\0" + /* 9269 */ "SQRDMLAHv1i16\0" + /* 9283 */ "SQDMULHv1i16\0" + /* 9296 */ "SQRDMULHv1i16\0" + /* 9310 */ "SQRDMLSHv1i16\0" + /* 9324 */ "SQSHLv1i16\0" + /* 9335 */ "UQSHLv1i16\0" + /* 9346 */ "SQRSHLv1i16\0" + /* 9358 */ "UQRSHLv1i16\0" + /* 9370 */ "SQXTNv1i16\0" + /* 9381 */ "UQXTNv1i16\0" + /* 9392 */ "SQXTUNv1i16\0" + /* 9404 */ "SQABSv1i16\0" + /* 9415 */ "LD2i16\0" + /* 9422 */ "ST2i16\0" + /* 9429 */ "LD3i16\0" + /* 9436 */ "ST3i16\0" + /* 9443 */ "LD4i16\0" + /* 9450 */ "ST4i16\0" + /* 9457 */ "TRN1v4i16\0" + /* 9467 */ "ZIP1v4i16\0" + /* 9477 */ "UZP1v4i16\0" + /* 9487 */ "REV32v4i16\0" + /* 9498 */ "TRN2v4i16\0" + /* 9508 */ "ZIP2v4i16\0" + /* 9518 */ "UZP2v4i16\0" + /* 9528 */ "REV64v4i16\0" + /* 9539 */ "SABAv4i16\0" + /* 9549 */ "UABAv4i16\0" + /* 9559 */ "MLAv4i16\0" + /* 9568 */ "SHSUBv4i16\0" + /* 9579 */ "UHSUBv4i16\0" + /* 9590 */ "SQSUBv4i16\0" + /* 9601 */ "UQSUBv4i16\0" + /* 9612 */ "BICv4i16\0" + /* 9621 */ "SABDv4i16\0" + /* 9631 */ "UABDv4i16\0" + /* 9641 */ "SRHADDv4i16\0" + /* 9653 */ "URHADDv4i16\0" + /* 9665 */ "SHADDv4i16\0" + /* 9676 */ "UHADDv4i16\0" + /* 9687 */ "USQADDv4i16\0" + /* 9699 */ "SUQADDv4i16\0" + /* 9711 */ "CMGEv4i16\0" + /* 9721 */ "SQNEGv4i16\0" + /* 9732 */ "SQRDMLAHv4i16\0" + /* 9746 */ "SQDMULHv4i16\0" + /* 9759 */ "SQRDMULHv4i16\0" + /* 9773 */ "SQRDMLSHv4i16\0" + /* 9787 */ "CMHIv4i16\0" + /* 9797 */ "MVNIv4i16\0" + /* 9807 */ "MOVIv4i16\0" + /* 9817 */ "SQSHLv4i16\0" + /* 9828 */ "UQSHLv4i16\0" + /* 9839 */ "SQRSHLv4i16\0" + /* 9851 */ "UQRSHLv4i16\0" + /* 9863 */ "SRSHLv4i16\0" + /* 9874 */ "URSHLv4i16\0" + /* 9885 */ "SSHLv4i16\0" + /* 9895 */ "USHLv4i16\0" + /* 9905 */ "SHLLv4i16\0" + /* 9915 */ "FCVTLv4i16\0" + /* 9926 */ "MULv4i16\0" + /* 9935 */ "SMINv4i16\0" + /* 9945 */ "UMINv4i16\0" + /* 9955 */ "FCVTNv4i16\0" + /* 9966 */ "SQXTNv4i16\0" + /* 9977 */ "UQXTNv4i16\0" + /* 9988 */ "SQXTUNv4i16\0" + /* 10000 */ "ADDPv4i16\0" + /* 10010 */ "SMINPv4i16\0" + /* 10021 */ "UMINPv4i16\0" + /* 10032 */ "SMAXPv4i16\0" + /* 10043 */ "UMAXPv4i16\0" + /* 10054 */ "CMEQv4i16\0" + /* 10064 */ "ORRv4i16\0" + /* 10073 */ "SQABSv4i16\0" + /* 10084 */ "CMHSv4i16\0" + /* 10094 */ "CLSv4i16\0" + /* 10103 */ "MLSv4i16\0" + /* 10112 */ "CMGTv4i16\0" + /* 10122 */ "CMTSTv4i16\0" + /* 10133 */ "SMAXv4i16\0" + /* 10143 */ "UMAXv4i16\0" + /* 10153 */ "CLZv4i16\0" + /* 10162 */ "RSUBHNv4i32_v4i16\0" + /* 10180 */ "RADDHNv4i32_v4i16\0" + /* 10198 */ "SADALPv8i8_v4i16\0" + /* 10215 */ "UADALPv8i8_v4i16\0" + /* 10232 */ "SADDLPv8i8_v4i16\0" + /* 10249 */ "UADDLPv8i8_v4i16\0" + /* 10266 */ "TRN1v8i16\0" + /* 10276 */ "ZIP1v8i16\0" + /* 10286 */ "UZP1v8i16\0" + /* 10296 */ "REV32v8i16\0" + /* 10307 */ "TRN2v8i16\0" + /* 10317 */ "ZIP2v8i16\0" + /* 10327 */ "UZP2v8i16\0" + /* 10337 */ "REV64v8i16\0" + /* 10348 */ "SABAv8i16\0" + /* 10358 */ "UABAv8i16\0" + /* 10368 */ "MLAv8i16\0" + /* 10377 */ "SHSUBv8i16\0" + /* 10388 */ "UHSUBv8i16\0" + /* 10399 */ "SQSUBv8i16\0" + /* 10410 */ "UQSUBv8i16\0" + /* 10421 */ "BICv8i16\0" + /* 10430 */ "SABDv8i16\0" + /* 10440 */ "UABDv8i16\0" + /* 10450 */ "SRHADDv8i16\0" + /* 10462 */ "URHADDv8i16\0" + /* 10474 */ "SHADDv8i16\0" + /* 10485 */ "UHADDv8i16\0" + /* 10496 */ "USQADDv8i16\0" + /* 10508 */ "SUQADDv8i16\0" + /* 10520 */ "CMGEv8i16\0" + /* 10530 */ "SQNEGv8i16\0" + /* 10541 */ "SQRDMLAHv8i16\0" + /* 10555 */ "SQDMULHv8i16\0" + /* 10568 */ "SQRDMULHv8i16\0" + /* 10582 */ "SQRDMLSHv8i16\0" + /* 10596 */ "CMHIv8i16\0" + /* 10606 */ "MVNIv8i16\0" + /* 10616 */ "MOVIv8i16\0" + /* 10626 */ "SQSHLv8i16\0" + /* 10637 */ "UQSHLv8i16\0" + /* 10648 */ "SQRSHLv8i16\0" + /* 10660 */ "UQRSHLv8i16\0" + /* 10672 */ "SRSHLv8i16\0" + /* 10683 */ "URSHLv8i16\0" + /* 10694 */ "SSHLv8i16\0" + /* 10704 */ "USHLv8i16\0" + /* 10714 */ "SHLLv8i16\0" + /* 10724 */ "FCVTLv8i16\0" + /* 10735 */ "MULv8i16\0" + /* 10744 */ "SMINv8i16\0" + /* 10754 */ "UMINv8i16\0" + /* 10764 */ "FCVTNv8i16\0" + /* 10775 */ "SQXTNv8i16\0" + /* 10786 */ "UQXTNv8i16\0" + /* 10797 */ "SQXTUNv8i16\0" + /* 10809 */ "ADDPv8i16\0" + /* 10819 */ "SMINPv8i16\0" + /* 10830 */ "UMINPv8i16\0" + /* 10841 */ "SMAXPv8i16\0" + /* 10852 */ "UMAXPv8i16\0" + /* 10863 */ "CMEQv8i16\0" + /* 10873 */ "ORRv8i16\0" + /* 10882 */ "SQABSv8i16\0" + /* 10893 */ "CMHSv8i16\0" + /* 10903 */ "CLSv8i16\0" + /* 10912 */ "MLSv8i16\0" + /* 10921 */ "CMGTv8i16\0" + /* 10931 */ "CMTSTv8i16\0" + /* 10942 */ "SMAXv8i16\0" + /* 10952 */ "UMAXv8i16\0" + /* 10962 */ "CLZv8i16\0" + /* 10971 */ "RSUBHNv4i32_v8i16\0" + /* 10989 */ "RADDHNv4i32_v8i16\0" + /* 11007 */ "SABALv16i8_v8i16\0" + /* 11024 */ "UABALv16i8_v8i16\0" + /* 11041 */ "SMLALv16i8_v8i16\0" + /* 11058 */ "UMLALv16i8_v8i16\0" + /* 11075 */ "SSUBLv16i8_v8i16\0" + /* 11092 */ "USUBLv16i8_v8i16\0" + /* 11109 */ "SABDLv16i8_v8i16\0" + /* 11126 */ "UABDLv16i8_v8i16\0" + /* 11143 */ "SADDLv16i8_v8i16\0" + /* 11160 */ "UADDLv16i8_v8i16\0" + /* 11177 */ "SMULLv16i8_v8i16\0" + /* 11194 */ "UMULLv16i8_v8i16\0" + /* 11211 */ "SMLSLv16i8_v8i16\0" + /* 11228 */ "UMLSLv16i8_v8i16\0" + /* 11245 */ "SADALPv16i8_v8i16\0" + /* 11263 */ "UADALPv16i8_v8i16\0" + /* 11281 */ "SADDLPv16i8_v8i16\0" + /* 11299 */ "UADDLPv16i8_v8i16\0" + /* 11317 */ "SSUBWv16i8_v8i16\0" + /* 11334 */ "USUBWv16i8_v8i16\0" + /* 11351 */ "SADDWv16i8_v8i16\0" + /* 11368 */ "UADDWv16i8_v8i16\0" + /* 11385 */ "SABALv8i8_v8i16\0" + /* 11401 */ "UABALv8i8_v8i16\0" + /* 11417 */ "SMLALv8i8_v8i16\0" + /* 11433 */ "UMLALv8i8_v8i16\0" + /* 11449 */ "SSUBLv8i8_v8i16\0" + /* 11465 */ "USUBLv8i8_v8i16\0" + /* 11481 */ "SABDLv8i8_v8i16\0" + /* 11497 */ "UABDLv8i8_v8i16\0" + /* 11513 */ "SADDLv8i8_v8i16\0" + /* 11529 */ "UADDLv8i8_v8i16\0" + /* 11545 */ "SMULLv8i8_v8i16\0" + /* 11561 */ "UMULLv8i8_v8i16\0" + /* 11577 */ "SMLSLv8i8_v8i16\0" + /* 11593 */ "UMLSLv8i8_v8i16\0" + /* 11609 */ "SSUBWv8i8_v8i16\0" + /* 11625 */ "USUBWv8i8_v8i16\0" + /* 11641 */ "SADDWv8i8_v8i16\0" + /* 11657 */ "UADDWv8i8_v8i16\0" + /* 11673 */ "SQDMLALi16\0" + /* 11684 */ "SQDMULLi16\0" + /* 11695 */ "SQDMLSLi16\0" + /* 11706 */ "CPYi16\0" + /* 11713 */ "UMOVvi16\0" + /* 11722 */ "JumpTableDest16\0" + /* 11738 */ "CMP_SWAP_128\0" + /* 11751 */ "G_DUPLANE8\0" + /* 11762 */ "SETF8\0" + /* 11768 */ "CMP_SWAP_8\0" + /* 11779 */ "LD1i8\0" + /* 11785 */ "ST1i8\0" + /* 11791 */ "SQSUBv1i8\0" + /* 11801 */ "UQSUBv1i8\0" + /* 11811 */ "USQADDv1i8\0" + /* 11822 */ "SUQADDv1i8\0" + /* 11833 */ "SQNEGv1i8\0" + /* 11843 */ "SQSHLv1i8\0" + /* 11853 */ "UQSHLv1i8\0" + /* 11863 */ "SQRSHLv1i8\0" + /* 11874 */ "UQRSHLv1i8\0" + /* 11885 */ "SQXTNv1i8\0" + /* 11895 */ "UQXTNv1i8\0" + /* 11905 */ "SQXTUNv1i8\0" + /* 11916 */ "SQABSv1i8\0" + /* 11926 */ "LD2i8\0" + /* 11932 */ "ST2i8\0" + /* 11938 */ "LD3i8\0" + /* 11944 */ "ST3i8\0" + /* 11950 */ "LD4i8\0" + /* 11956 */ "ST4i8\0" + /* 11962 */ "TRN1v16i8\0" + /* 11972 */ "ZIP1v16i8\0" + /* 11982 */ "UZP1v16i8\0" + /* 11992 */ "REV32v16i8\0" + /* 12003 */ "TRN2v16i8\0" + /* 12013 */ "ZIP2v16i8\0" + /* 12023 */ "UZP2v16i8\0" + /* 12033 */ "REV64v16i8\0" + /* 12044 */ "REV16v16i8\0" + /* 12055 */ "SABAv16i8\0" + /* 12065 */ "UABAv16i8\0" + /* 12075 */ "MLAv16i8\0" + /* 12084 */ "SHSUBv16i8\0" + /* 12095 */ "UHSUBv16i8\0" + /* 12106 */ "SQSUBv16i8\0" + /* 12117 */ "UQSUBv16i8\0" + /* 12128 */ "BICv16i8\0" + /* 12137 */ "SABDv16i8\0" + /* 12147 */ "UABDv16i8\0" + /* 12157 */ "SRHADDv16i8\0" + /* 12169 */ "URHADDv16i8\0" + /* 12181 */ "SHADDv16i8\0" + /* 12192 */ "UHADDv16i8\0" + /* 12203 */ "USQADDv16i8\0" + /* 12215 */ "SUQADDv16i8\0" + /* 12227 */ "ANDv16i8\0" + /* 12236 */ "CMGEv16i8\0" + /* 12246 */ "BIFv16i8\0" + /* 12255 */ "SQNEGv16i8\0" + /* 12266 */ "CMHIv16i8\0" + /* 12276 */ "SQSHLv16i8\0" + /* 12287 */ "UQSHLv16i8\0" + /* 12298 */ "SQRSHLv16i8\0" + /* 12310 */ "UQRSHLv16i8\0" + /* 12322 */ "SRSHLv16i8\0" + /* 12333 */ "URSHLv16i8\0" + /* 12344 */ "SSHLv16i8\0" + /* 12354 */ "USHLv16i8\0" + /* 12364 */ "SHLLv16i8\0" + /* 12374 */ "PMULLv16i8\0" + /* 12385 */ "BSLv16i8\0" + /* 12394 */ "PMULv16i8\0" + /* 12404 */ "SMINv16i8\0" + /* 12414 */ "UMINv16i8\0" + /* 12424 */ "ORNv16i8\0" + /* 12433 */ "SQXTNv16i8\0" + /* 12444 */ "UQXTNv16i8\0" + /* 12455 */ "SQXTUNv16i8\0" + /* 12467 */ "ADDPv16i8\0" + /* 12477 */ "SMINPv16i8\0" + /* 12488 */ "UMINPv16i8\0" + /* 12499 */ "BSPv16i8\0" + /* 12508 */ "SMAXPv16i8\0" + /* 12519 */ "UMAXPv16i8\0" + /* 12530 */ "CMEQv16i8\0" + /* 12540 */ "EORv16i8\0" + /* 12549 */ "ORRv16i8\0" + /* 12558 */ "SQABSv16i8\0" + /* 12569 */ "CMHSv16i8\0" + /* 12579 */ "CLSv16i8\0" + /* 12588 */ "MLSv16i8\0" + /* 12597 */ "CMGTv16i8\0" + /* 12607 */ "RBITv16i8\0" + /* 12617 */ "CNTv16i8\0" + /* 12626 */ "USDOTv16i8\0" + /* 12637 */ "UDOTv16i8\0" + /* 12647 */ "NOTv16i8\0" + /* 12656 */ "CMTSTv16i8\0" + /* 12667 */ "EXTv16i8\0" + /* 12676 */ "SMAXv16i8\0" + /* 12686 */ "UMAXv16i8\0" + /* 12696 */ "CLZv16i8\0" + /* 12705 */ "RSUBHNv8i16_v16i8\0" + /* 12723 */ "RADDHNv8i16_v16i8\0" + /* 12741 */ "USDOTlanev16i8\0" + /* 12756 */ "SUDOTlanev16i8\0" + /* 12771 */ "TRN1v8i8\0" + /* 12780 */ "ZIP1v8i8\0" + /* 12789 */ "UZP1v8i8\0" + /* 12798 */ "REV32v8i8\0" + /* 12808 */ "TRN2v8i8\0" + /* 12817 */ "ZIP2v8i8\0" + /* 12826 */ "UZP2v8i8\0" + /* 12835 */ "REV64v8i8\0" + /* 12845 */ "REV16v8i8\0" + /* 12855 */ "SABAv8i8\0" + /* 12864 */ "UABAv8i8\0" + /* 12873 */ "MLAv8i8\0" + /* 12881 */ "SHSUBv8i8\0" + /* 12891 */ "UHSUBv8i8\0" + /* 12901 */ "SQSUBv8i8\0" + /* 12911 */ "UQSUBv8i8\0" + /* 12921 */ "BICv8i8\0" + /* 12929 */ "SABDv8i8\0" + /* 12938 */ "UABDv8i8\0" + /* 12947 */ "SRHADDv8i8\0" + /* 12958 */ "URHADDv8i8\0" + /* 12969 */ "SHADDv8i8\0" + /* 12979 */ "UHADDv8i8\0" + /* 12989 */ "USQADDv8i8\0" + /* 13000 */ "SUQADDv8i8\0" + /* 13011 */ "ANDv8i8\0" + /* 13019 */ "CMGEv8i8\0" + /* 13028 */ "BIFv8i8\0" + /* 13036 */ "SQNEGv8i8\0" + /* 13046 */ "CMHIv8i8\0" + /* 13055 */ "SQSHLv8i8\0" + /* 13065 */ "UQSHLv8i8\0" + /* 13075 */ "SQRSHLv8i8\0" + /* 13086 */ "UQRSHLv8i8\0" + /* 13097 */ "SRSHLv8i8\0" + /* 13107 */ "URSHLv8i8\0" + /* 13117 */ "SSHLv8i8\0" + /* 13126 */ "USHLv8i8\0" + /* 13135 */ "SHLLv8i8\0" + /* 13144 */ "PMULLv8i8\0" + /* 13154 */ "BSLv8i8\0" + /* 13162 */ "PMULv8i8\0" + /* 13171 */ "SMINv8i8\0" + /* 13180 */ "UMINv8i8\0" + /* 13189 */ "ORNv8i8\0" + /* 13197 */ "SQXTNv8i8\0" + /* 13207 */ "UQXTNv8i8\0" + /* 13217 */ "SQXTUNv8i8\0" + /* 13228 */ "ADDPv8i8\0" + /* 13237 */ "SMINPv8i8\0" + /* 13247 */ "UMINPv8i8\0" + /* 13257 */ "BSPv8i8\0" + /* 13265 */ "SMAXPv8i8\0" + /* 13275 */ "UMAXPv8i8\0" + /* 13285 */ "CMEQv8i8\0" + /* 13294 */ "EORv8i8\0" + /* 13302 */ "ORRv8i8\0" + /* 13310 */ "SQABSv8i8\0" + /* 13320 */ "CMHSv8i8\0" + /* 13329 */ "CLSv8i8\0" + /* 13337 */ "MLSv8i8\0" + /* 13345 */ "CMGTv8i8\0" + /* 13354 */ "RBITv8i8\0" + /* 13363 */ "CNTv8i8\0" + /* 13371 */ "USDOTv8i8\0" + /* 13381 */ "UDOTv8i8\0" + /* 13390 */ "NOTv8i8\0" + /* 13398 */ "CMTSTv8i8\0" + /* 13408 */ "EXTv8i8\0" + /* 13416 */ "SMAXv8i8\0" + /* 13425 */ "UMAXv8i8\0" + /* 13434 */ "CLZv8i8\0" + /* 13442 */ "RSUBHNv8i16_v8i8\0" + /* 13459 */ "RADDHNv8i16_v8i8\0" + /* 13476 */ "USDOTlanev8i8\0" + /* 13490 */ "SUDOTlanev8i8\0" + /* 13504 */ "CPYi8\0" + /* 13510 */ "UMOVvi8\0" + /* 13518 */ "JumpTableDest8\0" + /* 13533 */ "SM3TT1A\0" + /* 13541 */ "SM3TT2A\0" + /* 13549 */ "BRAA\0" + /* 13554 */ "BLRAA\0" + /* 13560 */ "ERETAA\0" + /* 13567 */ "MOVaddrBA\0" + /* 13577 */ "PACDA\0" + /* 13583 */ "AUTDA\0" + /* 13589 */ "PACGA\0" + /* 13595 */ "PACIA\0" + /* 13601 */ "AUTIA\0" + /* 13607 */ "BFMMLA\0" + /* 13614 */ "USMMLA\0" + /* 13621 */ "UMMLA\0" + /* 13627 */ "G_FMA\0" + /* 13633 */ "G_STRICT_FMA\0" + /* 13646 */ "PACDZA\0" + /* 13653 */ "AUTDZA\0" + /* 13660 */ "PACIZA\0" + /* 13667 */ "AUTIZA\0" + /* 13674 */ "LDR_ZA\0" + /* 13681 */ "STR_ZA\0" + /* 13688 */ "LD1B\0" + /* 13693 */ "LDFF1B\0" + /* 13700 */ "ST1B\0" + /* 13705 */ "SM3TT1B\0" + /* 13713 */ "LD2B\0" + /* 13718 */ "ST2B\0" + /* 13723 */ "SM3TT2B\0" + /* 13731 */ "LD3B\0" + /* 13736 */ "ST3B\0" + /* 13741 */ "LD64B\0" + /* 13747 */ "ST64B\0" + /* 13753 */ "LD4B\0" + /* 13758 */ "ST4B\0" + /* 13763 */ "LDADDAB\0" + /* 13771 */ "LDSMINAB\0" + /* 13780 */ "LDUMINAB\0" + /* 13789 */ "SWPAB\0" + /* 13795 */ "BRAB\0" + /* 13800 */ "BLRAB\0" + /* 13806 */ "LDCLRAB\0" + /* 13814 */ "LDEORAB\0" + /* 13822 */ "CASAB\0" + /* 13828 */ "ERETAB\0" + /* 13835 */ "LDSETAB\0" + /* 13843 */ "LDSMAXAB\0" + /* 13852 */ "LDUMAXAB\0" + /* 13861 */ "SpeculationBarrierISBDSBEndBB\0" + /* 13891 */ "SpeculationBarrierSBEndBB\0" + /* 13917 */ "PACDB\0" + /* 13923 */ "LDADDB\0" + /* 13930 */ "AUTDB\0" + /* 13936 */ "PACIB\0" + /* 13942 */ "AUTIB\0" + /* 13948 */ "LDADDALB\0" + /* 13957 */ "BFMLALB\0" + /* 13965 */ "LDSMINALB\0" + /* 13975 */ "LDUMINALB\0" + /* 13985 */ "SWPALB\0" + /* 13992 */ "LDCLRALB\0" + /* 14001 */ "LDEORALB\0" + /* 14010 */ "CASALB\0" + /* 14017 */ "LDSETALB\0" + /* 14026 */ "LDSMAXALB\0" + /* 14036 */ "LDUMAXALB\0" + /* 14046 */ "LDADDLB\0" + /* 14054 */ "LDSMINLB\0" + /* 14063 */ "LDUMINLB\0" + /* 14072 */ "SWPLB\0" + /* 14078 */ "LDCLRLB\0" + /* 14086 */ "LDEORLB\0" + /* 14094 */ "CASLB\0" + /* 14100 */ "LDSETLB\0" + /* 14108 */ "LDSMAXLB\0" + /* 14117 */ "LDUMAXLB\0" + /* 14126 */ "DMB\0" + /* 14130 */ "LDSMINB\0" + /* 14138 */ "LDUMINB\0" + /* 14146 */ "SWPB\0" + /* 14151 */ "LDARB\0" + /* 14157 */ "LDLARB\0" + /* 14164 */ "LDCLRB\0" + /* 14171 */ "STLLRB\0" + /* 14178 */ "STLRB\0" + /* 14184 */ "LDEORB\0" + /* 14191 */ "LDAPRB\0" + /* 14198 */ "LDAXRB\0" + /* 14205 */ "LDXRB\0" + /* 14211 */ "STLXRB\0" + /* 14218 */ "STXRB\0" + /* 14224 */ "CASB\0" + /* 14229 */ "DSB\0" + /* 14233 */ "ISB\0" + /* 14237 */ "TSB\0" + /* 14241 */ "LDSETB\0" + /* 14248 */ "G_FSUB\0" + /* 14255 */ "G_STRICT_FSUB\0" + /* 14269 */ "G_ATOMICRMW_FSUB\0" + /* 14286 */ "G_SUB\0" + /* 14292 */ "G_ATOMICRMW_SUB\0" + /* 14308 */ "LDSMAXB\0" + /* 14316 */ "LDUMAXB\0" + /* 14324 */ "PACDZB\0" + /* 14331 */ "AUTDZB\0" + /* 14338 */ "PACIZB\0" + /* 14345 */ "AUTIZB\0" + /* 14352 */ "PTRUE_B\0" + /* 14360 */ "LSL_ZPZI_UNDEF_B\0" + /* 14377 */ "ASR_ZPZI_UNDEF_B\0" + /* 14394 */ "LSR_ZPZI_UNDEF_B\0" + /* 14411 */ "SUB_ZPZZ_UNDEF_B\0" + /* 14428 */ "ADD_ZPZZ_UNDEF_B\0" + /* 14445 */ "SMULH_ZPZZ_UNDEF_B\0" + /* 14464 */ "UMULH_ZPZZ_UNDEF_B\0" + /* 14483 */ "SQSHL_ZPZZ_UNDEF_B\0" + /* 14502 */ "UQSHL_ZPZZ_UNDEF_B\0" + /* 14521 */ "SQRSHL_ZPZZ_UNDEF_B\0" + /* 14541 */ "UQRSHL_ZPZZ_UNDEF_B\0" + /* 14561 */ "SRSHL_ZPZZ_UNDEF_B\0" + /* 14580 */ "URSHL_ZPZZ_UNDEF_B\0" + /* 14599 */ "LSL_ZPZZ_UNDEF_B\0" + /* 14616 */ "MUL_ZPZZ_UNDEF_B\0" + /* 14633 */ "SMIN_ZPZZ_UNDEF_B\0" + /* 14651 */ "UMIN_ZPZZ_UNDEF_B\0" + /* 14669 */ "ASR_ZPZZ_UNDEF_B\0" + /* 14686 */ "LSR_ZPZZ_UNDEF_B\0" + /* 14703 */ "SMAX_ZPZZ_UNDEF_B\0" + /* 14721 */ "UMAX_ZPZZ_UNDEF_B\0" + /* 14739 */ "SQNEG_ZPmZ_UNDEF_B\0" + /* 14758 */ "SQABS_ZPmZ_UNDEF_B\0" + /* 14777 */ "CLS_ZPmZ_UNDEF_B\0" + /* 14794 */ "CNT_ZPmZ_UNDEF_B\0" + /* 14811 */ "CNOT_ZPmZ_UNDEF_B\0" + /* 14829 */ "CLZ_ZPmZ_UNDEF_B\0" + /* 14846 */ "EXTRACT_ZPMXI_H_B\0" + /* 14864 */ "LD1_MXIPXX_H_B\0" + /* 14879 */ "ST1_MXIPXX_H_B\0" + /* 14894 */ "INSERT_MXIPZ_H_B\0" + /* 14911 */ "INDEX_II_B\0" + /* 14922 */ "PSEL_PPPRI_B\0" + /* 14935 */ "INDEX_RI_B\0" + /* 14946 */ "XAR_ZZZI_B\0" + /* 14957 */ "SRSRA_ZZI_B\0" + /* 14969 */ "URSRA_ZZI_B\0" + /* 14981 */ "SSRA_ZZI_B\0" + /* 14992 */ "USRA_ZZI_B\0" + /* 15003 */ "SQSHRNB_ZZI_B\0" + /* 15017 */ "UQSHRNB_ZZI_B\0" + /* 15031 */ "SQRSHRNB_ZZI_B\0" + /* 15046 */ "UQRSHRNB_ZZI_B\0" + /* 15061 */ "SQSHRUNB_ZZI_B\0" + /* 15076 */ "SQRSHRUNB_ZZI_B\0" + /* 15092 */ "SQCADD_ZZI_B\0" + /* 15105 */ "SLI_ZZI_B\0" + /* 15115 */ "SRI_ZZI_B\0" + /* 15125 */ "LSL_ZZI_B\0" + /* 15135 */ "DUP_ZZI_B\0" + /* 15145 */ "ASR_ZZI_B\0" + /* 15155 */ "LSR_ZZI_B\0" + /* 15165 */ "SQSHRNT_ZZI_B\0" + /* 15179 */ "UQSHRNT_ZZI_B\0" + /* 15193 */ "SQRSHRNT_ZZI_B\0" + /* 15208 */ "UQRSHRNT_ZZI_B\0" + /* 15223 */ "SQSHRUNT_ZZI_B\0" + /* 15238 */ "SQRSHRUNT_ZZI_B\0" + /* 15254 */ "EXT_ZZI_B\0" + /* 15264 */ "SQSUB_ZI_B\0" + /* 15275 */ "UQSUB_ZI_B\0" + /* 15286 */ "SQADD_ZI_B\0" + /* 15297 */ "UQADD_ZI_B\0" + /* 15308 */ "MUL_ZI_B\0" + /* 15317 */ "SMIN_ZI_B\0" + /* 15327 */ "UMIN_ZI_B\0" + /* 15337 */ "DUP_ZI_B\0" + /* 15346 */ "SUBR_ZI_B\0" + /* 15356 */ "SMAX_ZI_B\0" + /* 15366 */ "UMAX_ZI_B\0" + /* 15376 */ "CMPGE_PPzZI_B\0" + /* 15390 */ "CMPLE_PPzZI_B\0" + /* 15404 */ "CMPNE_PPzZI_B\0" + /* 15418 */ "CMPHI_PPzZI_B\0" + /* 15432 */ "CMPLO_PPzZI_B\0" + /* 15446 */ "CMPEQ_PPzZI_B\0" + /* 15460 */ "CMPHS_PPzZI_B\0" + /* 15474 */ "CMPLS_PPzZI_B\0" + /* 15488 */ "CMPGT_PPzZI_B\0" + /* 15502 */ "CMPLT_PPzZI_B\0" + /* 15516 */ "ASRD_ZPmI_B\0" + /* 15528 */ "SQSHL_ZPmI_B\0" + /* 15541 */ "UQSHL_ZPmI_B\0" + /* 15554 */ "LSL_ZPmI_B\0" + /* 15565 */ "SRSHR_ZPmI_B\0" + /* 15578 */ "URSHR_ZPmI_B\0" + /* 15591 */ "ASR_ZPmI_B\0" + /* 15602 */ "LSR_ZPmI_B\0" + /* 15613 */ "SQSHLU_ZPmI_B\0" + /* 15627 */ "CPY_ZPmI_B\0" + /* 15638 */ "CPY_ZPzI_B\0" + /* 15649 */ "LD1RO_B\0" + /* 15657 */ "ASRD_ZPZI_ZERO_B\0" + /* 15674 */ "SQSHL_ZPZI_ZERO_B\0" + /* 15692 */ "UQSHL_ZPZI_ZERO_B\0" + /* 15710 */ "SRSHR_ZPZI_ZERO_B\0" + /* 15728 */ "URSHR_ZPZI_ZERO_B\0" + /* 15746 */ "SQSHLU_ZPZI_ZERO_B\0" + /* 15765 */ "SUB_ZPZZ_ZERO_B\0" + /* 15781 */ "ADD_ZPZZ_ZERO_B\0" + /* 15797 */ "LSL_ZPZZ_ZERO_B\0" + /* 15813 */ "SUBR_ZPZZ_ZERO_B\0" + /* 15830 */ "ASR_ZPZZ_ZERO_B\0" + /* 15846 */ "LSR_ZPZZ_ZERO_B\0" + /* 15862 */ "TRN1_PPP_B\0" + /* 15873 */ "ZIP1_PPP_B\0" + /* 15884 */ "UZP1_PPP_B\0" + /* 15895 */ "TRN2_PPP_B\0" + /* 15906 */ "ZIP2_PPP_B\0" + /* 15917 */ "UZP2_PPP_B\0" + /* 15928 */ "CNTP_XPP_B\0" + /* 15939 */ "REV_PP_B\0" + /* 15948 */ "UQDECP_WP_B\0" + /* 15960 */ "UQINCP_WP_B\0" + /* 15972 */ "SQDECP_XP_B\0" + /* 15984 */ "UQDECP_XP_B\0" + /* 15996 */ "SQINCP_XP_B\0" + /* 16008 */ "UQINCP_XP_B\0" + /* 16020 */ "LD1RQ_B\0" + /* 16028 */ "INDEX_IR_B\0" + /* 16039 */ "INDEX_RR_B\0" + /* 16050 */ "DUP_ZR_B\0" + /* 16059 */ "INSR_ZR_B\0" + /* 16069 */ "CPY_ZPmR_B\0" + /* 16080 */ "PTRUES_B\0" + /* 16089 */ "PFIRST_B\0" + /* 16098 */ "PNEXT_B\0" + /* 16106 */ "INSR_ZV_B\0" + /* 16116 */ "EXTRACT_ZPMXI_V_B\0" + /* 16134 */ "LD1_MXIPXX_V_B\0" + /* 16149 */ "ST1_MXIPXX_V_B\0" + /* 16164 */ "INSERT_MXIPZ_V_B\0" + /* 16181 */ "CPY_ZPmV_B\0" + /* 16192 */ "WHILEGE_PWW_B\0" + /* 16206 */ "WHILELE_PWW_B\0" + /* 16220 */ "WHILEHI_PWW_B\0" + /* 16234 */ "WHILELO_PWW_B\0" + /* 16248 */ "WHILEHS_PWW_B\0" + /* 16262 */ "WHILELS_PWW_B\0" + /* 16276 */ "WHILEGT_PWW_B\0" + /* 16290 */ "WHILELT_PWW_B\0" + /* 16304 */ "WHILEGE_PXX_B\0" + /* 16318 */ "WHILELE_PXX_B\0" + /* 16332 */ "WHILEHI_PXX_B\0" + /* 16346 */ "WHILELO_PXX_B\0" + /* 16360 */ "WHILEWR_PXX_B\0" + /* 16374 */ "WHILEHS_PXX_B\0" + /* 16388 */ "WHILELS_PXX_B\0" + /* 16402 */ "WHILEGT_PXX_B\0" + /* 16416 */ "WHILELT_PXX_B\0" + /* 16430 */ "WHILERW_PXX_B\0" + /* 16444 */ "CLASTA_RPZ_B\0" + /* 16457 */ "CLASTB_RPZ_B\0" + /* 16470 */ "CLASTA_VPZ_B\0" + /* 16483 */ "CLASTB_VPZ_B\0" + /* 16496 */ "SADDV_VPZ_B\0" + /* 16508 */ "UADDV_VPZ_B\0" + /* 16520 */ "ANDV_VPZ_B\0" + /* 16531 */ "SMINV_VPZ_B\0" + /* 16543 */ "UMINV_VPZ_B\0" + /* 16555 */ "EORV_VPZ_B\0" + /* 16566 */ "SMAXV_VPZ_B\0" + /* 16578 */ "UMAXV_VPZ_B\0" + /* 16590 */ "CLASTA_ZPZ_B\0" + /* 16603 */ "CLASTB_ZPZ_B\0" + /* 16616 */ "SPLICE_ZPZ_B\0" + /* 16629 */ "SPLICE_ZPZZ_B\0" + /* 16643 */ "SEL_ZPZZ_B\0" + /* 16654 */ "TBL_ZZZZ_B\0" + /* 16665 */ "TRN1_ZZZ_B\0" + /* 16676 */ "ZIP1_ZZZ_B\0" + /* 16687 */ "UZP1_ZZZ_B\0" + /* 16698 */ "TRN2_ZZZ_B\0" + /* 16709 */ "ZIP2_ZZZ_B\0" + /* 16720 */ "UZP2_ZZZ_B\0" + /* 16731 */ "SABA_ZZZ_B\0" + /* 16742 */ "UABA_ZZZ_B\0" + /* 16753 */ "CMLA_ZZZ_B\0" + /* 16764 */ "RSUBHNB_ZZZ_B\0" + /* 16778 */ "RADDHNB_ZZZ_B\0" + /* 16792 */ "EORTB_ZZZ_B\0" + /* 16804 */ "SQSUB_ZZZ_B\0" + /* 16816 */ "UQSUB_ZZZ_B\0" + /* 16828 */ "SQADD_ZZZ_B\0" + /* 16840 */ "UQADD_ZZZ_B\0" + /* 16852 */ "AESD_ZZZ_B\0" + /* 16863 */ "LSL_WIDE_ZZZ_B\0" + /* 16878 */ "ASR_WIDE_ZZZ_B\0" + /* 16893 */ "LSR_WIDE_ZZZ_B\0" + /* 16908 */ "AESE_ZZZ_B\0" + /* 16919 */ "SQRDCMLAH_ZZZ_B\0" + /* 16935 */ "SQRDMLAH_ZZZ_B\0" + /* 16950 */ "SQDMULH_ZZZ_B\0" + /* 16964 */ "SQRDMULH_ZZZ_B\0" + /* 16979 */ "SMULH_ZZZ_B\0" + /* 16991 */ "UMULH_ZZZ_B\0" + /* 17003 */ "SQRDMLSH_ZZZ_B\0" + /* 17018 */ "TBL_ZZZ_B\0" + /* 17028 */ "PMUL_ZZZ_B\0" + /* 17039 */ "BDEP_ZZZ_B\0" + /* 17050 */ "SCLAMP_ZZZ_B\0" + /* 17063 */ "UCLAMP_ZZZ_B\0" + /* 17076 */ "BGRP_ZZZ_B\0" + /* 17087 */ "EORBT_ZZZ_B\0" + /* 17099 */ "RSUBHNT_ZZZ_B\0" + /* 17113 */ "RADDHNT_ZZZ_B\0" + /* 17127 */ "BEXT_ZZZ_B\0" + /* 17138 */ "TBX_ZZZ_B\0" + /* 17148 */ "SQXTNB_ZZ_B\0" + /* 17160 */ "UQXTNB_ZZ_B\0" + /* 17172 */ "SQXTUNB_ZZ_B\0" + /* 17185 */ "AESIMC_ZZ_B\0" + /* 17197 */ "AESMC_ZZ_B\0" + /* 17208 */ "SQXTNT_ZZ_B\0" + /* 17220 */ "UQXTNT_ZZ_B\0" + /* 17232 */ "SQXTUNT_ZZ_B\0" + /* 17245 */ "REV_ZZ_B\0" + /* 17254 */ "MLA_ZPmZZ_B\0" + /* 17266 */ "MSB_ZPmZZ_B\0" + /* 17278 */ "MAD_ZPmZZ_B\0" + /* 17290 */ "MLS_ZPmZZ_B\0" + /* 17302 */ "CMPGE_WIDE_PPzZZ_B\0" + /* 17321 */ "CMPLE_WIDE_PPzZZ_B\0" + /* 17340 */ "CMPNE_WIDE_PPzZZ_B\0" + /* 17359 */ "CMPHI_WIDE_PPzZZ_B\0" + /* 17378 */ "CMPLO_WIDE_PPzZZ_B\0" + /* 17397 */ "CMPEQ_WIDE_PPzZZ_B\0" + /* 17416 */ "CMPHS_WIDE_PPzZZ_B\0" + /* 17435 */ "CMPLS_WIDE_PPzZZ_B\0" + /* 17454 */ "CMPGT_WIDE_PPzZZ_B\0" + /* 17473 */ "CMPLT_WIDE_PPzZZ_B\0" + /* 17492 */ "CMPGE_PPzZZ_B\0" + /* 17506 */ "CMPNE_PPzZZ_B\0" + /* 17520 */ "NMATCH_PPzZZ_B\0" + /* 17535 */ "CMPHI_PPzZZ_B\0" + /* 17549 */ "CMPEQ_PPzZZ_B\0" + /* 17563 */ "CMPHS_PPzZZ_B\0" + /* 17577 */ "CMPGT_PPzZZ_B\0" + /* 17591 */ "SHSUB_ZPmZ_B\0" + /* 17604 */ "UHSUB_ZPmZ_B\0" + /* 17617 */ "SQSUB_ZPmZ_B\0" + /* 17630 */ "UQSUB_ZPmZ_B\0" + /* 17643 */ "BIC_ZPmZ_B\0" + /* 17654 */ "SABD_ZPmZ_B\0" + /* 17666 */ "UABD_ZPmZ_B\0" + /* 17678 */ "SRHADD_ZPmZ_B\0" + /* 17692 */ "URHADD_ZPmZ_B\0" + /* 17706 */ "SHADD_ZPmZ_B\0" + /* 17719 */ "UHADD_ZPmZ_B\0" + /* 17732 */ "USQADD_ZPmZ_B\0" + /* 17746 */ "SUQADD_ZPmZ_B\0" + /* 17760 */ "AND_ZPmZ_B\0" + /* 17771 */ "LSL_WIDE_ZPmZ_B\0" + /* 17787 */ "ASR_WIDE_ZPmZ_B\0" + /* 17803 */ "LSR_WIDE_ZPmZ_B\0" + /* 17819 */ "SQNEG_ZPmZ_B\0" + /* 17832 */ "SMULH_ZPmZ_B\0" + /* 17845 */ "UMULH_ZPmZ_B\0" + /* 17858 */ "SQSHL_ZPmZ_B\0" + /* 17871 */ "UQSHL_ZPmZ_B\0" + /* 17884 */ "SQRSHL_ZPmZ_B\0" + /* 17898 */ "UQRSHL_ZPmZ_B\0" + /* 17912 */ "SRSHL_ZPmZ_B\0" + /* 17925 */ "URSHL_ZPmZ_B\0" + /* 17938 */ "LSL_ZPmZ_B\0" + /* 17949 */ "MUL_ZPmZ_B\0" + /* 17960 */ "SMIN_ZPmZ_B\0" + /* 17972 */ "UMIN_ZPmZ_B\0" + /* 17984 */ "ADDP_ZPmZ_B\0" + /* 17996 */ "SMINP_ZPmZ_B\0" + /* 18009 */ "UMINP_ZPmZ_B\0" + /* 18022 */ "SMAXP_ZPmZ_B\0" + /* 18035 */ "UMAXP_ZPmZ_B\0" + /* 18048 */ "SHSUBR_ZPmZ_B\0" + /* 18062 */ "UHSUBR_ZPmZ_B\0" + /* 18076 */ "SQSUBR_ZPmZ_B\0" + /* 18090 */ "UQSUBR_ZPmZ_B\0" + /* 18104 */ "SQSHLR_ZPmZ_B\0" + /* 18118 */ "UQSHLR_ZPmZ_B\0" + /* 18132 */ "SQRSHLR_ZPmZ_B\0" + /* 18147 */ "UQRSHLR_ZPmZ_B\0" + /* 18162 */ "SRSHLR_ZPmZ_B\0" + /* 18176 */ "URSHLR_ZPmZ_B\0" + /* 18190 */ "LSLR_ZPmZ_B\0" + /* 18202 */ "EOR_ZPmZ_B\0" + /* 18213 */ "ORR_ZPmZ_B\0" + /* 18224 */ "ASRR_ZPmZ_B\0" + /* 18236 */ "LSRR_ZPmZ_B\0" + /* 18248 */ "ASR_ZPmZ_B\0" + /* 18259 */ "LSR_ZPmZ_B\0" + /* 18270 */ "SQABS_ZPmZ_B\0" + /* 18283 */ "CLS_ZPmZ_B\0" + /* 18294 */ "RBIT_ZPmZ_B\0" + /* 18306 */ "CNT_ZPmZ_B\0" + /* 18317 */ "CNOT_ZPmZ_B\0" + /* 18329 */ "SMAX_ZPmZ_B\0" + /* 18341 */ "UMAX_ZPmZ_B\0" + /* 18353 */ "MOVPRFX_ZPmZ_B\0" + /* 18368 */ "CLZ_ZPmZ_B\0" + /* 18379 */ "MOVPRFX_ZPzZ_B\0" + /* 18394 */ "SQDECP_XPWd_B\0" + /* 18408 */ "SQINCP_XPWd_B\0" + /* 18422 */ "CMP_SWAP_128_MONOTONIC\0" + /* 18445 */ "G_INTRINSIC\0" + /* 18457 */ "SMC\0" + /* 18461 */ "G_FPTRUNC\0" + /* 18471 */ "G_INTRINSIC_TRUNC\0" + /* 18489 */ "G_TRUNC\0" + /* 18497 */ "G_BUILD_VECTOR_TRUNC\0" + /* 18518 */ "G_DYN_STACKALLOC\0" + /* 18535 */ "HVC\0" + /* 18539 */ "SVC\0" + /* 18543 */ "GLD1D\0" + /* 18549 */ "GLDFF1D\0" + /* 18557 */ "ST1D\0" + /* 18562 */ "LD2D\0" + /* 18567 */ "ST2D\0" + /* 18572 */ "LD3D\0" + /* 18577 */ "ST3D\0" + /* 18582 */ "LD4D\0" + /* 18587 */ "ST4D\0" + /* 18592 */ "G_FMAD\0" + /* 18599 */ "G_INDEXED_SEXTLOAD\0" + /* 18618 */ "G_SEXTLOAD\0" + /* 18629 */ "G_INDEXED_ZEXTLOAD\0" + /* 18648 */ "G_ZEXTLOAD\0" + /* 18659 */ "G_INDEXED_LOAD\0" + /* 18674 */ "G_LOAD\0" + /* 18681 */ "XPACD\0" + /* 18687 */ "G_VECREDUCE_FADD\0" + /* 18704 */ "G_FADD\0" + /* 18711 */ "G_VECREDUCE_SEQ_FADD\0" + /* 18732 */ "G_STRICT_FADD\0" + /* 18746 */ "G_ATOMICRMW_FADD\0" + /* 18763 */ "G_VECREDUCE_ADD\0" + /* 18779 */ "G_ADD\0" + /* 18785 */ "G_PTR_ADD\0" + /* 18795 */ "G_ATOMICRMW_ADD\0" + /* 18811 */ "GLD1D_SCALED\0" + /* 18824 */ "GLDFF1D_SCALED\0" + /* 18839 */ "PRFB_D_SCALED\0" + /* 18853 */ "PRFD_D_SCALED\0" + /* 18867 */ "GLD1H_D_SCALED\0" + /* 18882 */ "GLDFF1H_D_SCALED\0" + /* 18899 */ "PRFH_D_SCALED\0" + /* 18913 */ "GLD1SH_D_SCALED\0" + /* 18929 */ "GLDFF1SH_D_SCALED\0" + /* 18947 */ "GLD1W_D_SCALED\0" + /* 18962 */ "GLDFF1W_D_SCALED\0" + /* 18979 */ "PRFW_D_SCALED\0" + /* 18993 */ "GLD1SW_D_SCALED\0" + /* 19009 */ "GLDFF1SW_D_SCALED\0" + /* 19027 */ "GLD1D_SXTW_SCALED\0" + /* 19045 */ "GLDFF1D_SXTW_SCALED\0" + /* 19065 */ "SST1D_SXTW_SCALED\0" + /* 19083 */ "PRFB_D_SXTW_SCALED\0" + /* 19102 */ "PRFD_D_SXTW_SCALED\0" + /* 19121 */ "GLD1H_D_SXTW_SCALED\0" + /* 19141 */ "GLDFF1H_D_SXTW_SCALED\0" + /* 19163 */ "SST1H_D_SXTW_SCALED\0" + /* 19183 */ "PRFH_D_SXTW_SCALED\0" + /* 19202 */ "GLD1SH_D_SXTW_SCALED\0" + /* 19223 */ "GLDFF1SH_D_SXTW_SCALED\0" + /* 19246 */ "GLD1W_D_SXTW_SCALED\0" + /* 19266 */ "GLDFF1W_D_SXTW_SCALED\0" + /* 19288 */ "SST1W_D_SXTW_SCALED\0" + /* 19308 */ "PRFW_D_SXTW_SCALED\0" + /* 19327 */ "GLD1SW_D_SXTW_SCALED\0" + /* 19348 */ "GLDFF1SW_D_SXTW_SCALED\0" + /* 19371 */ "PRFB_S_SXTW_SCALED\0" + /* 19390 */ "PRFD_S_SXTW_SCALED\0" + /* 19409 */ "GLD1H_S_SXTW_SCALED\0" + /* 19429 */ "GLDFF1H_S_SXTW_SCALED\0" + /* 19451 */ "SST1H_S_SXTW_SCALED\0" + /* 19471 */ "PRFH_S_SXTW_SCALED\0" + /* 19490 */ "GLD1SH_S_SXTW_SCALED\0" + /* 19511 */ "GLDFF1SH_S_SXTW_SCALED\0" + /* 19534 */ "PRFW_S_SXTW_SCALED\0" + /* 19553 */ "GLD1W_SXTW_SCALED\0" + /* 19571 */ "GLDFF1W_SXTW_SCALED\0" + /* 19591 */ "SST1W_SXTW_SCALED\0" + /* 19609 */ "GLD1D_UXTW_SCALED\0" + /* 19627 */ "GLDFF1D_UXTW_SCALED\0" + /* 19647 */ "SST1D_UXTW_SCALED\0" + /* 19665 */ "PRFB_D_UXTW_SCALED\0" + /* 19684 */ "PRFD_D_UXTW_SCALED\0" + /* 19703 */ "GLD1H_D_UXTW_SCALED\0" + /* 19723 */ "GLDFF1H_D_UXTW_SCALED\0" + /* 19745 */ "SST1H_D_UXTW_SCALED\0" + /* 19765 */ "PRFH_D_UXTW_SCALED\0" + /* 19784 */ "GLD1SH_D_UXTW_SCALED\0" + /* 19805 */ "GLDFF1SH_D_UXTW_SCALED\0" + /* 19828 */ "GLD1W_D_UXTW_SCALED\0" + /* 19848 */ "GLDFF1W_D_UXTW_SCALED\0" + /* 19870 */ "SST1W_D_UXTW_SCALED\0" + /* 19890 */ "PRFW_D_UXTW_SCALED\0" + /* 19909 */ "GLD1SW_D_UXTW_SCALED\0" + /* 19930 */ "GLDFF1SW_D_UXTW_SCALED\0" + /* 19953 */ "PRFB_S_UXTW_SCALED\0" + /* 19972 */ "PRFD_S_UXTW_SCALED\0" + /* 19991 */ "GLD1H_S_UXTW_SCALED\0" + /* 20011 */ "GLDFF1H_S_UXTW_SCALED\0" + /* 20033 */ "SST1H_S_UXTW_SCALED\0" + /* 20053 */ "PRFH_S_UXTW_SCALED\0" + /* 20072 */ "GLD1SH_S_UXTW_SCALED\0" + /* 20093 */ "GLDFF1SH_S_UXTW_SCALED\0" + /* 20116 */ "PRFW_S_UXTW_SCALED\0" + /* 20135 */ "GLD1W_UXTW_SCALED\0" + /* 20153 */ "GLDFF1W_UXTW_SCALED\0" + /* 20173 */ "SST1W_UXTW_SCALED\0" + /* 20191 */ "MOVID\0" + /* 20197 */ "G_ATOMICRMW_NAND\0" + /* 20214 */ "G_VECREDUCE_AND\0" + /* 20230 */ "G_AND\0" + /* 20236 */ "G_ATOMICRMW_AND\0" + /* 20252 */ "LIFETIME_END\0" + /* 20265 */ "G_BRCOND\0" + /* 20274 */ "G_LLROUND\0" + /* 20284 */ "G_LROUND\0" + /* 20293 */ "G_INTRINSIC_ROUND\0" + /* 20311 */ "LOAD_STACK_GUARD\0" + /* 20328 */ "FCMGE_PPzZ0_D\0" + /* 20342 */ "FCMLE_PPzZ0_D\0" + /* 20356 */ "FCMNE_PPzZ0_D\0" + /* 20370 */ "FCMEQ_PPzZ0_D\0" + /* 20384 */ "FCMGT_PPzZ0_D\0" + /* 20398 */ "FCMLT_PPzZ0_D\0" + /* 20412 */ "GLD1B_D\0" + /* 20420 */ "GLDFF1B_D\0" + /* 20430 */ "ST1B_D\0" + /* 20437 */ "GLD1SB_D\0" + /* 20446 */ "GLDFF1SB_D\0" + /* 20457 */ "PTRUE_D\0" + /* 20465 */ "FSUB_ZPZI_UNDEF_D\0" + /* 20483 */ "FADD_ZPZI_UNDEF_D\0" + /* 20501 */ "LSL_ZPZI_UNDEF_D\0" + /* 20518 */ "FMUL_ZPZI_UNDEF_D\0" + /* 20536 */ "FMINNM_ZPZI_UNDEF_D\0" + /* 20556 */ "FMAXNM_ZPZI_UNDEF_D\0" + /* 20576 */ "FMIN_ZPZI_UNDEF_D\0" + /* 20594 */ "FSUBR_ZPZI_UNDEF_D\0" + /* 20613 */ "ASR_ZPZI_UNDEF_D\0" + /* 20630 */ "LSR_ZPZI_UNDEF_D\0" + /* 20647 */ "FMAX_ZPZI_UNDEF_D\0" + /* 20665 */ "FSUB_ZPZZ_UNDEF_D\0" + /* 20683 */ "FADD_ZPZZ_UNDEF_D\0" + /* 20701 */ "SMULH_ZPZZ_UNDEF_D\0" + /* 20720 */ "UMULH_ZPZZ_UNDEF_D\0" + /* 20739 */ "SQSHL_ZPZZ_UNDEF_D\0" + /* 20758 */ "UQSHL_ZPZZ_UNDEF_D\0" + /* 20777 */ "SQRSHL_ZPZZ_UNDEF_D\0" + /* 20797 */ "UQRSHL_ZPZZ_UNDEF_D\0" + /* 20817 */ "SRSHL_ZPZZ_UNDEF_D\0" + /* 20836 */ "URSHL_ZPZZ_UNDEF_D\0" + /* 20855 */ "LSL_ZPZZ_UNDEF_D\0" + /* 20872 */ "FMUL_ZPZZ_UNDEF_D\0" + /* 20890 */ "FMINNM_ZPZZ_UNDEF_D\0" + /* 20910 */ "FMAXNM_ZPZZ_UNDEF_D\0" + /* 20930 */ "FMIN_ZPZZ_UNDEF_D\0" + /* 20948 */ "SMIN_ZPZZ_UNDEF_D\0" + /* 20966 */ "UMIN_ZPZZ_UNDEF_D\0" + /* 20984 */ "ASR_ZPZZ_UNDEF_D\0" + /* 21001 */ "LSR_ZPZZ_UNDEF_D\0" + /* 21018 */ "FDIV_ZPZZ_UNDEF_D\0" + /* 21036 */ "SDIV_ZPZZ_UNDEF_D\0" + /* 21054 */ "UDIV_ZPZZ_UNDEF_D\0" + /* 21072 */ "FMAX_ZPZZ_UNDEF_D\0" + /* 21090 */ "SMAX_ZPZZ_UNDEF_D\0" + /* 21108 */ "UMAX_ZPZZ_UNDEF_D\0" + /* 21126 */ "FMLA_ZPZZZ_UNDEF_D\0" + /* 21145 */ "FNMLA_ZPZZZ_UNDEF_D\0" + /* 21165 */ "FMLS_ZPZZZ_UNDEF_D\0" + /* 21184 */ "FNMLS_ZPZZZ_UNDEF_D\0" + /* 21204 */ "FRINTA_ZPmZ_UNDEF_D\0" + /* 21224 */ "SXTB_ZPmZ_UNDEF_D\0" + /* 21242 */ "UXTB_ZPmZ_UNDEF_D\0" + /* 21260 */ "FNEG_ZPmZ_UNDEF_D\0" + /* 21278 */ "SQNEG_ZPmZ_UNDEF_D\0" + /* 21297 */ "SXTH_ZPmZ_UNDEF_D\0" + /* 21315 */ "UXTH_ZPmZ_UNDEF_D\0" + /* 21333 */ "FRINTI_ZPmZ_UNDEF_D\0" + /* 21353 */ "FRINTM_ZPmZ_UNDEF_D\0" + /* 21373 */ "FRINTN_ZPmZ_UNDEF_D\0" + /* 21393 */ "FRINTP_ZPmZ_UNDEF_D\0" + /* 21413 */ "FABS_ZPmZ_UNDEF_D\0" + /* 21431 */ "SQABS_ZPmZ_UNDEF_D\0" + /* 21450 */ "CLS_ZPmZ_UNDEF_D\0" + /* 21467 */ "CNT_ZPmZ_UNDEF_D\0" + /* 21484 */ "CNOT_ZPmZ_UNDEF_D\0" + /* 21502 */ "FSQRT_ZPmZ_UNDEF_D\0" + /* 21521 */ "SXTW_ZPmZ_UNDEF_D\0" + /* 21539 */ "UXTW_ZPmZ_UNDEF_D\0" + /* 21557 */ "FRECPX_ZPmZ_UNDEF_D\0" + /* 21577 */ "FRINTX_ZPmZ_UNDEF_D\0" + /* 21597 */ "CLZ_ZPmZ_UNDEF_D\0" + /* 21614 */ "FRINTZ_ZPmZ_UNDEF_D\0" + /* 21634 */ "GLD1H_D\0" + /* 21642 */ "GLDFF1H_D\0" + /* 21652 */ "ST1H_D\0" + /* 21659 */ "GLD1SH_D\0" + /* 21668 */ "GLDFF1SH_D\0" + /* 21679 */ "EXTRACT_ZPMXI_H_D\0" + /* 21697 */ "LD1_MXIPXX_H_D\0" + /* 21712 */ "ST1_MXIPXX_H_D\0" + /* 21727 */ "INSERT_MXIPZ_H_D\0" + /* 21744 */ "INDEX_II_D\0" + /* 21755 */ "PSEL_PPPRI_D\0" + /* 21768 */ "INDEX_RI_D\0" + /* 21779 */ "FMLA_ZZZI_D\0" + /* 21791 */ "SQDMLALB_ZZZI_D\0" + /* 21807 */ "SMLALB_ZZZI_D\0" + /* 21821 */ "UMLALB_ZZZI_D\0" + /* 21835 */ "SQDMULLB_ZZZI_D\0" + /* 21851 */ "SMULLB_ZZZI_D\0" + /* 21865 */ "UMULLB_ZZZI_D\0" + /* 21879 */ "SQDMLSLB_ZZZI_D\0" + /* 21895 */ "SMLSLB_ZZZI_D\0" + /* 21909 */ "UMLSLB_ZZZI_D\0" + /* 21923 */ "SQRDMLAH_ZZZI_D\0" + /* 21939 */ "SQDMULH_ZZZI_D\0" + /* 21954 */ "SQRDMULH_ZZZI_D\0" + /* 21970 */ "SQRDMLSH_ZZZI_D\0" + /* 21986 */ "FMUL_ZZZI_D\0" + /* 21998 */ "XAR_ZZZI_D\0" + /* 22009 */ "FMLS_ZZZI_D\0" + /* 22021 */ "SQDMLALT_ZZZI_D\0" + /* 22037 */ "SMLALT_ZZZI_D\0" + /* 22051 */ "UMLALT_ZZZI_D\0" + /* 22065 */ "SQDMULLT_ZZZI_D\0" + /* 22081 */ "SMULLT_ZZZI_D\0" + /* 22095 */ "UMULLT_ZZZI_D\0" + /* 22109 */ "SQDMLSLT_ZZZI_D\0" + /* 22125 */ "SMLSLT_ZZZI_D\0" + /* 22139 */ "UMLSLT_ZZZI_D\0" + /* 22153 */ "CDOT_ZZZI_D\0" + /* 22165 */ "SDOT_ZZZI_D\0" + /* 22177 */ "UDOT_ZZZI_D\0" + /* 22189 */ "SRSRA_ZZI_D\0" + /* 22201 */ "URSRA_ZZI_D\0" + /* 22213 */ "SSRA_ZZI_D\0" + /* 22224 */ "USRA_ZZI_D\0" + /* 22235 */ "SSHLLB_ZZI_D\0" + /* 22248 */ "USHLLB_ZZI_D\0" + /* 22261 */ "FTMAD_ZZI_D\0" + /* 22273 */ "SQCADD_ZZI_D\0" + /* 22286 */ "SLI_ZZI_D\0" + /* 22296 */ "SRI_ZZI_D\0" + /* 22306 */ "LSL_ZZI_D\0" + /* 22316 */ "DUP_ZZI_D\0" + /* 22326 */ "ASR_ZZI_D\0" + /* 22336 */ "LSR_ZZI_D\0" + /* 22346 */ "SSHLLT_ZZI_D\0" + /* 22359 */ "USHLLT_ZZI_D\0" + /* 22372 */ "SQSUB_ZI_D\0" + /* 22383 */ "UQSUB_ZI_D\0" + /* 22394 */ "SQADD_ZI_D\0" + /* 22405 */ "UQADD_ZI_D\0" + /* 22416 */ "MUL_ZI_D\0" + /* 22425 */ "SMIN_ZI_D\0" + /* 22435 */ "UMIN_ZI_D\0" + /* 22445 */ "FDUP_ZI_D\0" + /* 22455 */ "SUBR_ZI_D\0" + /* 22465 */ "SMAX_ZI_D\0" + /* 22475 */ "UMAX_ZI_D\0" + /* 22485 */ "CMPGE_PPzZI_D\0" + /* 22499 */ "CMPLE_PPzZI_D\0" + /* 22513 */ "CMPNE_PPzZI_D\0" + /* 22527 */ "CMPHI_PPzZI_D\0" + /* 22541 */ "CMPLO_PPzZI_D\0" + /* 22555 */ "CMPEQ_PPzZI_D\0" + /* 22569 */ "CMPHS_PPzZI_D\0" + /* 22583 */ "CMPLS_PPzZI_D\0" + /* 22597 */ "CMPGT_PPzZI_D\0" + /* 22611 */ "CMPLT_PPzZI_D\0" + /* 22625 */ "FSUB_ZPmI_D\0" + /* 22637 */ "FADD_ZPmI_D\0" + /* 22649 */ "ASRD_ZPmI_D\0" + /* 22661 */ "SQSHL_ZPmI_D\0" + /* 22674 */ "UQSHL_ZPmI_D\0" + /* 22687 */ "LSL_ZPmI_D\0" + /* 22698 */ "FMUL_ZPmI_D\0" + /* 22710 */ "FMINNM_ZPmI_D\0" + /* 22724 */ "FMAXNM_ZPmI_D\0" + /* 22738 */ "FMIN_ZPmI_D\0" + /* 22750 */ "FSUBR_ZPmI_D\0" + /* 22763 */ "SRSHR_ZPmI_D\0" + /* 22776 */ "URSHR_ZPmI_D\0" + /* 22789 */ "ASR_ZPmI_D\0" + /* 22800 */ "LSR_ZPmI_D\0" + /* 22811 */ "SQSHLU_ZPmI_D\0" + /* 22825 */ "FMAX_ZPmI_D\0" + /* 22837 */ "FCPY_ZPmI_D\0" + /* 22849 */ "CPY_ZPzI_D\0" + /* 22860 */ "LD1RO_D\0" + /* 22868 */ "FSUB_ZPZI_ZERO_D\0" + /* 22885 */ "FADD_ZPZI_ZERO_D\0" + /* 22902 */ "ASRD_ZPZI_ZERO_D\0" + /* 22919 */ "SQSHL_ZPZI_ZERO_D\0" + /* 22937 */ "UQSHL_ZPZI_ZERO_D\0" + /* 22955 */ "FMUL_ZPZI_ZERO_D\0" + /* 22972 */ "FMINNM_ZPZI_ZERO_D\0" + /* 22991 */ "FMAXNM_ZPZI_ZERO_D\0" + /* 23010 */ "FMIN_ZPZI_ZERO_D\0" + /* 23027 */ "FSUBR_ZPZI_ZERO_D\0" + /* 23045 */ "SRSHR_ZPZI_ZERO_D\0" + /* 23063 */ "URSHR_ZPZI_ZERO_D\0" + /* 23081 */ "SQSHLU_ZPZI_ZERO_D\0" + /* 23100 */ "FMAX_ZPZI_ZERO_D\0" + /* 23117 */ "FSUB_ZPZZ_ZERO_D\0" + /* 23134 */ "FABD_ZPZZ_ZERO_D\0" + /* 23151 */ "FADD_ZPZZ_ZERO_D\0" + /* 23168 */ "LSL_ZPZZ_ZERO_D\0" + /* 23184 */ "FMUL_ZPZZ_ZERO_D\0" + /* 23201 */ "FMINNM_ZPZZ_ZERO_D\0" + /* 23220 */ "FMAXNM_ZPZZ_ZERO_D\0" + /* 23239 */ "FMIN_ZPZZ_ZERO_D\0" + /* 23256 */ "FSUBR_ZPZZ_ZERO_D\0" + /* 23274 */ "ASR_ZPZZ_ZERO_D\0" + /* 23290 */ "LSR_ZPZZ_ZERO_D\0" + /* 23306 */ "FDIVR_ZPZZ_ZERO_D\0" + /* 23324 */ "FDIV_ZPZZ_ZERO_D\0" + /* 23341 */ "FMAX_ZPZZ_ZERO_D\0" + /* 23358 */ "FMULX_ZPZZ_ZERO_D\0" + /* 23376 */ "TRN1_PPP_D\0" + /* 23387 */ "ZIP1_PPP_D\0" + /* 23398 */ "UZP1_PPP_D\0" + /* 23409 */ "TRN2_PPP_D\0" + /* 23420 */ "ZIP2_PPP_D\0" + /* 23431 */ "UZP2_PPP_D\0" + /* 23442 */ "CNTP_XPP_D\0" + /* 23453 */ "REV_PP_D\0" + /* 23462 */ "UQDECP_WP_D\0" + /* 23474 */ "UQINCP_WP_D\0" + /* 23486 */ "SQDECP_XP_D\0" + /* 23498 */ "UQDECP_XP_D\0" + /* 23510 */ "SQINCP_XP_D\0" + /* 23522 */ "UQINCP_XP_D\0" + /* 23534 */ "SQDECP_ZP_D\0" + /* 23546 */ "UQDECP_ZP_D\0" + /* 23558 */ "SQINCP_ZP_D\0" + /* 23570 */ "UQINCP_ZP_D\0" + /* 23582 */ "LD1RQ_D\0" + /* 23590 */ "INDEX_IR_D\0" + /* 23601 */ "INDEX_RR_D\0" + /* 23612 */ "DUP_ZR_D\0" + /* 23621 */ "INSR_ZR_D\0" + /* 23631 */ "CPY_ZPmR_D\0" + /* 23642 */ "PTRUES_D\0" + /* 23651 */ "PNEXT_D\0" + /* 23659 */ "INSR_ZV_D\0" + /* 23669 */ "EXTRACT_ZPMXI_V_D\0" + /* 23687 */ "LD1_MXIPXX_V_D\0" + /* 23702 */ "ST1_MXIPXX_V_D\0" + /* 23717 */ "INSERT_MXIPZ_V_D\0" + /* 23734 */ "CPY_ZPmV_D\0" + /* 23745 */ "GLD1W_D\0" + /* 23753 */ "GLDFF1W_D\0" + /* 23763 */ "ST1W_D\0" + /* 23770 */ "GLD1SW_D\0" + /* 23779 */ "GLDFF1SW_D\0" + /* 23790 */ "WHILEGE_PWW_D\0" + /* 23804 */ "WHILELE_PWW_D\0" + /* 23818 */ "WHILEHI_PWW_D\0" + /* 23832 */ "WHILELO_PWW_D\0" + /* 23846 */ "WHILEHS_PWW_D\0" + /* 23860 */ "WHILELS_PWW_D\0" + /* 23874 */ "WHILEGT_PWW_D\0" + /* 23888 */ "WHILELT_PWW_D\0" + /* 23902 */ "WHILEGE_PXX_D\0" + /* 23916 */ "WHILELE_PXX_D\0" + /* 23930 */ "WHILEHI_PXX_D\0" + /* 23944 */ "WHILELO_PXX_D\0" + /* 23958 */ "WHILEWR_PXX_D\0" + /* 23972 */ "WHILEHS_PXX_D\0" + /* 23986 */ "WHILELS_PXX_D\0" + /* 24000 */ "WHILEGT_PXX_D\0" + /* 24014 */ "WHILELT_PXX_D\0" + /* 24028 */ "WHILERW_PXX_D\0" + /* 24042 */ "ADDHA_MPPZ_D\0" + /* 24055 */ "ADDVA_MPPZ_D\0" + /* 24068 */ "CLASTA_RPZ_D\0" + /* 24081 */ "CLASTB_RPZ_D\0" + /* 24094 */ "FADDA_VPZ_D\0" + /* 24106 */ "CLASTA_VPZ_D\0" + /* 24119 */ "CLASTB_VPZ_D\0" + /* 24132 */ "FADDV_VPZ_D\0" + /* 24144 */ "UADDV_VPZ_D\0" + /* 24156 */ "ANDV_VPZ_D\0" + /* 24167 */ "FMINNMV_VPZ_D\0" + /* 24181 */ "FMAXNMV_VPZ_D\0" + /* 24195 */ "FMINV_VPZ_D\0" + /* 24207 */ "SMINV_VPZ_D\0" + /* 24219 */ "UMINV_VPZ_D\0" + /* 24231 */ "EORV_VPZ_D\0" + /* 24242 */ "FMAXV_VPZ_D\0" + /* 24254 */ "SMAXV_VPZ_D\0" + /* 24266 */ "UMAXV_VPZ_D\0" + /* 24278 */ "CLASTA_ZPZ_D\0" + /* 24291 */ "CLASTB_ZPZ_D\0" + /* 24304 */ "SPLICE_ZPZ_D\0" + /* 24317 */ "COMPACT_ZPZ_D\0" + /* 24331 */ "FMOPA_MPPZZ_D\0" + /* 24345 */ "USMOPA_MPPZZ_D\0" + /* 24360 */ "SUMOPA_MPPZZ_D\0" + /* 24375 */ "FMOPS_MPPZZ_D\0" + /* 24389 */ "USMOPS_MPPZZ_D\0" + /* 24404 */ "SUMOPS_MPPZZ_D\0" + /* 24419 */ "SPLICE_ZPZZ_D\0" + /* 24433 */ "SEL_ZPZZ_D\0" + /* 24444 */ "TBL_ZZZZ_D\0" + /* 24455 */ "TRN1_ZZZ_D\0" + /* 24466 */ "ZIP1_ZZZ_D\0" + /* 24477 */ "UZP1_ZZZ_D\0" + /* 24488 */ "RAX1_ZZZ_D\0" + /* 24499 */ "TRN2_ZZZ_D\0" + /* 24510 */ "ZIP2_ZZZ_D\0" + /* 24521 */ "UZP2_ZZZ_D\0" + /* 24532 */ "SABA_ZZZ_D\0" + /* 24543 */ "UABA_ZZZ_D\0" + /* 24554 */ "CMLA_ZZZ_D\0" + /* 24565 */ "FMMLA_ZZZ_D\0" + /* 24577 */ "SABALB_ZZZ_D\0" + /* 24590 */ "UABALB_ZZZ_D\0" + /* 24603 */ "SQDMLALB_ZZZ_D\0" + /* 24618 */ "SMLALB_ZZZ_D\0" + /* 24631 */ "UMLALB_ZZZ_D\0" + /* 24644 */ "SSUBLB_ZZZ_D\0" + /* 24657 */ "USUBLB_ZZZ_D\0" + /* 24670 */ "SBCLB_ZZZ_D\0" + /* 24682 */ "ADCLB_ZZZ_D\0" + /* 24694 */ "SABDLB_ZZZ_D\0" + /* 24707 */ "UABDLB_ZZZ_D\0" + /* 24720 */ "SADDLB_ZZZ_D\0" + /* 24733 */ "UADDLB_ZZZ_D\0" + /* 24746 */ "SQDMULLB_ZZZ_D\0" + /* 24761 */ "PMULLB_ZZZ_D\0" + /* 24774 */ "SMULLB_ZZZ_D\0" + /* 24787 */ "UMULLB_ZZZ_D\0" + /* 24800 */ "SQDMLSLB_ZZZ_D\0" + /* 24815 */ "SMLSLB_ZZZ_D\0" + /* 24828 */ "UMLSLB_ZZZ_D\0" + /* 24841 */ "SSUBLTB_ZZZ_D\0" + /* 24855 */ "EORTB_ZZZ_D\0" + /* 24867 */ "FSUB_ZZZ_D\0" + /* 24878 */ "SQSUB_ZZZ_D\0" + /* 24890 */ "UQSUB_ZZZ_D\0" + /* 24902 */ "SSUBWB_ZZZ_D\0" + /* 24915 */ "USUBWB_ZZZ_D\0" + /* 24928 */ "SADDWB_ZZZ_D\0" + /* 24941 */ "UADDWB_ZZZ_D\0" + /* 24954 */ "FADD_ZZZ_D\0" + /* 24965 */ "SQADD_ZZZ_D\0" + /* 24977 */ "UQADD_ZZZ_D\0" + /* 24989 */ "SQRDCMLAH_ZZZ_D\0" + /* 25005 */ "SQRDMLAH_ZZZ_D\0" + /* 25020 */ "SQDMULH_ZZZ_D\0" + /* 25034 */ "SQRDMULH_ZZZ_D\0" + /* 25049 */ "SMULH_ZZZ_D\0" + /* 25061 */ "UMULH_ZZZ_D\0" + /* 25073 */ "SQRDMLSH_ZZZ_D\0" + /* 25088 */ "TBL_ZZZ_D\0" + /* 25098 */ "FTSSEL_ZZZ_D\0" + /* 25111 */ "FMUL_ZZZ_D\0" + /* 25122 */ "FTSMUL_ZZZ_D\0" + /* 25135 */ "BDEP_ZZZ_D\0" + /* 25146 */ "SCLAMP_ZZZ_D\0" + /* 25159 */ "UCLAMP_ZZZ_D\0" + /* 25172 */ "BGRP_ZZZ_D\0" + /* 25183 */ "FRECPS_ZZZ_D\0" + /* 25196 */ "FRSQRTS_ZZZ_D\0" + /* 25210 */ "SQDMLALBT_ZZZ_D\0" + /* 25226 */ "SSUBLBT_ZZZ_D\0" + /* 25240 */ "SADDLBT_ZZZ_D\0" + /* 25254 */ "SQDMLSLBT_ZZZ_D\0" + /* 25270 */ "EORBT_ZZZ_D\0" + /* 25282 */ "SABALT_ZZZ_D\0" + /* 25295 */ "UABALT_ZZZ_D\0" + /* 25308 */ "SQDMLALT_ZZZ_D\0" + /* 25323 */ "SMLALT_ZZZ_D\0" + /* 25336 */ "UMLALT_ZZZ_D\0" + /* 25349 */ "SSUBLT_ZZZ_D\0" + /* 25362 */ "USUBLT_ZZZ_D\0" + /* 25375 */ "SBCLT_ZZZ_D\0" + /* 25387 */ "ADCLT_ZZZ_D\0" + /* 25399 */ "SABDLT_ZZZ_D\0" + /* 25412 */ "UABDLT_ZZZ_D\0" + /* 25425 */ "SADDLT_ZZZ_D\0" + /* 25438 */ "UADDLT_ZZZ_D\0" + /* 25451 */ "SQDMULLT_ZZZ_D\0" + /* 25466 */ "PMULLT_ZZZ_D\0" + /* 25479 */ "SMULLT_ZZZ_D\0" + /* 25492 */ "UMULLT_ZZZ_D\0" + /* 25505 */ "SQDMLSLT_ZZZ_D\0" + /* 25520 */ "SMLSLT_ZZZ_D\0" + /* 25533 */ "UMLSLT_ZZZ_D\0" + /* 25546 */ "CDOT_ZZZ_D\0" + /* 25557 */ "SDOT_ZZZ_D\0" + /* 25568 */ "UDOT_ZZZ_D\0" + /* 25579 */ "SSUBWT_ZZZ_D\0" + /* 25592 */ "USUBWT_ZZZ_D\0" + /* 25605 */ "SADDWT_ZZZ_D\0" + /* 25618 */ "UADDWT_ZZZ_D\0" + /* 25631 */ "BEXT_ZZZ_D\0" + /* 25642 */ "TBX_ZZZ_D\0" + /* 25652 */ "FEXPA_ZZ_D\0" + /* 25663 */ "FRECPE_ZZ_D\0" + /* 25675 */ "FRSQRTE_ZZ_D\0" + /* 25688 */ "SUNPKHI_ZZ_D\0" + /* 25701 */ "UUNPKHI_ZZ_D\0" + /* 25714 */ "SUNPKLO_ZZ_D\0" + /* 25727 */ "UUNPKLO_ZZ_D\0" + /* 25740 */ "REV_ZZ_D\0" + /* 25749 */ "FCMLA_ZPmZZ_D\0" + /* 25763 */ "FMLA_ZPmZZ_D\0" + /* 25776 */ "FNMLA_ZPmZZ_D\0" + /* 25790 */ "FMSB_ZPmZZ_D\0" + /* 25803 */ "FNMSB_ZPmZZ_D\0" + /* 25817 */ "FMAD_ZPmZZ_D\0" + /* 25830 */ "FNMAD_ZPmZZ_D\0" + /* 25844 */ "FADDP_ZPmZZ_D\0" + /* 25858 */ "FMINNMP_ZPmZZ_D\0" + /* 25874 */ "FMAXNMP_ZPmZZ_D\0" + /* 25890 */ "FMINP_ZPmZZ_D\0" + /* 25904 */ "FMAXP_ZPmZZ_D\0" + /* 25918 */ "FMLS_ZPmZZ_D\0" + /* 25931 */ "FNMLS_ZPmZZ_D\0" + /* 25945 */ "FACGE_PPzZZ_D\0" + /* 25959 */ "FCMGE_PPzZZ_D\0" + /* 25973 */ "CMPGE_PPzZZ_D\0" + /* 25987 */ "FCMNE_PPzZZ_D\0" + /* 26001 */ "CMPNE_PPzZZ_D\0" + /* 26015 */ "CMPHI_PPzZZ_D\0" + /* 26029 */ "FCMUO_PPzZZ_D\0" + /* 26043 */ "FCMEQ_PPzZZ_D\0" + /* 26057 */ "CMPEQ_PPzZZ_D\0" + /* 26071 */ "CMPHS_PPzZZ_D\0" + /* 26085 */ "FACGT_PPzZZ_D\0" + /* 26099 */ "FCMGT_PPzZZ_D\0" + /* 26113 */ "CMPGT_PPzZZ_D\0" + /* 26127 */ "HISTCNT_ZPzZZ_D\0" + /* 26143 */ "FRINTA_ZPmZ_D\0" + /* 26157 */ "FLOGB_ZPmZ_D\0" + /* 26170 */ "SXTB_ZPmZ_D\0" + /* 26182 */ "UXTB_ZPmZ_D\0" + /* 26194 */ "FSUB_ZPmZ_D\0" + /* 26206 */ "SHSUB_ZPmZ_D\0" + /* 26219 */ "UHSUB_ZPmZ_D\0" + /* 26232 */ "SQSUB_ZPmZ_D\0" + /* 26245 */ "UQSUB_ZPmZ_D\0" + /* 26258 */ "REVB_ZPmZ_D\0" + /* 26270 */ "BIC_ZPmZ_D\0" + /* 26281 */ "FABD_ZPmZ_D\0" + /* 26293 */ "SABD_ZPmZ_D\0" + /* 26305 */ "UABD_ZPmZ_D\0" + /* 26317 */ "FCADD_ZPmZ_D\0" + /* 26330 */ "FADD_ZPmZ_D\0" + /* 26342 */ "SRHADD_ZPmZ_D\0" + /* 26356 */ "URHADD_ZPmZ_D\0" + /* 26370 */ "SHADD_ZPmZ_D\0" + /* 26383 */ "UHADD_ZPmZ_D\0" + /* 26396 */ "USQADD_ZPmZ_D\0" + /* 26410 */ "SUQADD_ZPmZ_D\0" + /* 26424 */ "AND_ZPmZ_D\0" + /* 26435 */ "FSCALE_ZPmZ_D\0" + /* 26449 */ "FNEG_ZPmZ_D\0" + /* 26461 */ "SQNEG_ZPmZ_D\0" + /* 26474 */ "SMULH_ZPmZ_D\0" + /* 26487 */ "UMULH_ZPmZ_D\0" + /* 26500 */ "SXTH_ZPmZ_D\0" + /* 26512 */ "UXTH_ZPmZ_D\0" + /* 26524 */ "REVH_ZPmZ_D\0" + /* 26536 */ "FRINTI_ZPmZ_D\0" + /* 26550 */ "SQSHL_ZPmZ_D\0" + /* 26563 */ "UQSHL_ZPmZ_D\0" + /* 26576 */ "SQRSHL_ZPmZ_D\0" + /* 26590 */ "UQRSHL_ZPmZ_D\0" + /* 26604 */ "SRSHL_ZPmZ_D\0" + /* 26617 */ "URSHL_ZPmZ_D\0" + /* 26630 */ "LSL_ZPmZ_D\0" + /* 26641 */ "FMUL_ZPmZ_D\0" + /* 26653 */ "FMINNM_ZPmZ_D\0" + /* 26667 */ "FMAXNM_ZPmZ_D\0" + /* 26681 */ "FRINTM_ZPmZ_D\0" + /* 26695 */ "FMIN_ZPmZ_D\0" + /* 26707 */ "SMIN_ZPmZ_D\0" + /* 26719 */ "UMIN_ZPmZ_D\0" + /* 26731 */ "FRINTN_ZPmZ_D\0" + /* 26745 */ "ADDP_ZPmZ_D\0" + /* 26757 */ "SADALP_ZPmZ_D\0" + /* 26771 */ "UADALP_ZPmZ_D\0" + /* 26785 */ "SMINP_ZPmZ_D\0" + /* 26798 */ "UMINP_ZPmZ_D\0" + /* 26811 */ "FRINTP_ZPmZ_D\0" + /* 26825 */ "SMAXP_ZPmZ_D\0" + /* 26838 */ "UMAXP_ZPmZ_D\0" + /* 26851 */ "FSUBR_ZPmZ_D\0" + /* 26864 */ "SHSUBR_ZPmZ_D\0" + /* 26878 */ "UHSUBR_ZPmZ_D\0" + /* 26892 */ "SQSUBR_ZPmZ_D\0" + /* 26906 */ "UQSUBR_ZPmZ_D\0" + /* 26920 */ "SQSHLR_ZPmZ_D\0" + /* 26934 */ "UQSHLR_ZPmZ_D\0" + /* 26948 */ "SQRSHLR_ZPmZ_D\0" + /* 26963 */ "UQRSHLR_ZPmZ_D\0" + /* 26978 */ "SRSHLR_ZPmZ_D\0" + /* 26992 */ "URSHLR_ZPmZ_D\0" + /* 27006 */ "LSLR_ZPmZ_D\0" + /* 27018 */ "EOR_ZPmZ_D\0" + /* 27029 */ "ORR_ZPmZ_D\0" + /* 27040 */ "ASRR_ZPmZ_D\0" + /* 27052 */ "LSRR_ZPmZ_D\0" + /* 27064 */ "ASR_ZPmZ_D\0" + /* 27075 */ "LSR_ZPmZ_D\0" + /* 27086 */ "FDIVR_ZPmZ_D\0" + /* 27099 */ "SDIVR_ZPmZ_D\0" + /* 27112 */ "UDIVR_ZPmZ_D\0" + /* 27125 */ "FABS_ZPmZ_D\0" + /* 27137 */ "SQABS_ZPmZ_D\0" + /* 27150 */ "CLS_ZPmZ_D\0" + /* 27161 */ "RBIT_ZPmZ_D\0" + /* 27173 */ "CNT_ZPmZ_D\0" + /* 27184 */ "CNOT_ZPmZ_D\0" + /* 27196 */ "FSQRT_ZPmZ_D\0" + /* 27209 */ "FDIV_ZPmZ_D\0" + /* 27221 */ "SDIV_ZPmZ_D\0" + /* 27233 */ "UDIV_ZPmZ_D\0" + /* 27245 */ "SXTW_ZPmZ_D\0" + /* 27257 */ "UXTW_ZPmZ_D\0" + /* 27269 */ "REVW_ZPmZ_D\0" + /* 27281 */ "FMAX_ZPmZ_D\0" + /* 27293 */ "SMAX_ZPmZ_D\0" + /* 27305 */ "UMAX_ZPmZ_D\0" + /* 27317 */ "MOVPRFX_ZPmZ_D\0" + /* 27332 */ "FMULX_ZPmZ_D\0" + /* 27345 */ "FRECPX_ZPmZ_D\0" + /* 27359 */ "FRINTX_ZPmZ_D\0" + /* 27373 */ "CLZ_ZPmZ_D\0" + /* 27384 */ "FRINTZ_ZPmZ_D\0" + /* 27398 */ "MOVPRFX_ZPzZ_D\0" + /* 27413 */ "SQDECP_XPWd_D\0" + /* 27427 */ "SQINCP_XPWd_D\0" + /* 27441 */ "SCVTF_ZPmZ_DtoD\0" + /* 27457 */ "UCVTF_ZPmZ_DtoD\0" + /* 27473 */ "FCVTZS_ZPmZ_DtoD\0" + /* 27490 */ "FCVTZU_ZPmZ_DtoD\0" + /* 27507 */ "FCVTZS_ZPmZ_HtoD\0" + /* 27524 */ "FCVT_ZPmZ_HtoD\0" + /* 27539 */ "FCVTZU_ZPmZ_HtoD\0" + /* 27556 */ "SCVTF_ZPmZ_StoD\0" + /* 27572 */ "UCVTF_ZPmZ_StoD\0" + /* 27588 */ "FCVTZS_ZPmZ_StoD\0" + /* 27605 */ "FCVTLT_ZPmZ_StoD\0" + /* 27622 */ "FCVT_ZPmZ_StoD\0" + /* 27637 */ "FCVTZU_ZPmZ_StoD\0" + /* 27654 */ "SM4E\0" + /* 27659 */ "PSEUDO_PROBE\0" + /* 27672 */ "G_SSUBE\0" + /* 27680 */ "G_USUBE\0" + /* 27688 */ "SPACE\0" + /* 27694 */ "G_FENCE\0" + /* 27702 */ "ARITH_FENCE\0" + /* 27714 */ "REG_SEQUENCE\0" + /* 27727 */ "G_SADDE\0" + /* 27735 */ "G_UADDE\0" + /* 27743 */ "G_FMINNUM_IEEE\0" + /* 27758 */ "G_FMAXNUM_IEEE\0" + /* 27773 */ "G_FCMGE\0" + /* 27781 */ "G_JUMP_TABLE\0" + /* 27794 */ "BUNDLE\0" + /* 27801 */ "G_MEMCPY_INLINE\0" + /* 27817 */ "LOCAL_ESCAPE\0" + /* 27830 */ "CMP_SWAP_128_ACQUIRE\0" + /* 27851 */ "G_INDEXED_STORE\0" + /* 27867 */ "G_STORE\0" + /* 27875 */ "CMP_SWAP_128_RELEASE\0" + /* 27896 */ "PFALSE\0" + /* 27903 */ "G_BITREVERSE\0" + /* 27916 */ "DBG_VALUE\0" + /* 27926 */ "G_GLOBAL_VALUE\0" + /* 27941 */ "G_MEMMOVE\0" + /* 27951 */ "G_FREEZE\0" + /* 27960 */ "G_FCANONICALIZE\0" + /* 27976 */ "UDF\0" + /* 27980 */ "G_CTLZ_ZERO_UNDEF\0" + /* 27998 */ "G_CTTZ_ZERO_UNDEF\0" + /* 28016 */ "G_IMPLICIT_DEF\0" + /* 28031 */ "DBG_INSTR_REF\0" + /* 28045 */ "RMIF\0" + /* 28050 */ "G_SITOF\0" + /* 28058 */ "G_UITOF\0" + /* 28066 */ "XAFLAG\0" + /* 28073 */ "AXFLAG\0" + /* 28080 */ "SUBG\0" + /* 28085 */ "ADDG\0" + /* 28090 */ "LDG\0" + /* 28094 */ "G_FNEG\0" + /* 28101 */ "EXTRACT_SUBREG\0" + /* 28116 */ "INSERT_SUBREG\0" + /* 28130 */ "G_SEXT_INREG\0" + /* 28143 */ "SUBREG_TO_REG\0" + /* 28157 */ "G_ATOMIC_CMPXCHG\0" + /* 28174 */ "G_ATOMICRMW_XCHG\0" + /* 28191 */ "G_FLOG\0" + /* 28198 */ "G_VAARG\0" + /* 28206 */ "PREALLOCATED_ARG\0" + /* 28223 */ "IRG\0" + /* 28227 */ "LD1H\0" + /* 28232 */ "LDFF1H\0" + /* 28239 */ "ST1H\0" + /* 28244 */ "SHA512H\0" + /* 28252 */ "LD2H\0" + /* 28257 */ "ST2H\0" + /* 28262 */ "LD3H\0" + /* 28267 */ "ST3H\0" + /* 28272 */ "LD4H\0" + /* 28277 */ "ST4H\0" + /* 28282 */ "LDADDAH\0" + /* 28290 */ "LDSMINAH\0" + /* 28299 */ "LDUMINAH\0" + /* 28308 */ "SWPAH\0" + /* 28314 */ "LDCLRAH\0" + /* 28322 */ "LDEORAH\0" + /* 28330 */ "CASAH\0" + /* 28336 */ "LDSETAH\0" + /* 28344 */ "LDSMAXAH\0" + /* 28353 */ "LDUMAXAH\0" + /* 28362 */ "LDADDH\0" + /* 28369 */ "FMLALB_ZZZI_SHH\0" + /* 28385 */ "FMLSLB_ZZZI_SHH\0" + /* 28401 */ "FMLALT_ZZZI_SHH\0" + /* 28417 */ "FMLSLT_ZZZI_SHH\0" + /* 28433 */ "FMLALB_ZZZ_SHH\0" + /* 28448 */ "FMLSLB_ZZZ_SHH\0" + /* 28463 */ "FMLALT_ZZZ_SHH\0" + /* 28478 */ "FMLSLT_ZZZ_SHH\0" + /* 28493 */ "LDADDALH\0" + /* 28502 */ "LDSMINALH\0" + /* 28512 */ "LDUMINALH\0" + /* 28522 */ "SWPALH\0" + /* 28529 */ "LDCLRALH\0" + /* 28538 */ "LDEORALH\0" + /* 28547 */ "CASALH\0" + /* 28554 */ "LDSETALH\0" + /* 28563 */ "LDSMAXALH\0" + /* 28573 */ "LDUMAXALH\0" + /* 28583 */ "LDADDLH\0" + /* 28591 */ "LDSMINLH\0" + /* 28600 */ "LDUMINLH\0" + /* 28609 */ "SWPLH\0" + /* 28615 */ "LDCLRLH\0" + /* 28623 */ "LDEORLH\0" + /* 28631 */ "CASLH\0" + /* 28637 */ "LDSETLH\0" + /* 28645 */ "G_SMULH\0" + /* 28653 */ "G_UMULH\0" + /* 28661 */ "LDSMAXLH\0" + /* 28670 */ "LDUMAXLH\0" + /* 28679 */ "LDSMINH\0" + /* 28687 */ "LDUMINH\0" + /* 28695 */ "SWPH\0" + /* 28700 */ "LDARH\0" + /* 28706 */ "LDLARH\0" + /* 28713 */ "LDCLRH\0" + /* 28720 */ "STLLRH\0" + /* 28727 */ "STLRH\0" + /* 28733 */ "LDEORH\0" + /* 28740 */ "LDAPRH\0" + /* 28747 */ "LDAXRH\0" + /* 28754 */ "LDXRH\0" + /* 28760 */ "STLXRH\0" + /* 28767 */ "STXRH\0" + /* 28773 */ "CASH\0" + /* 28778 */ "LDSETH\0" + /* 28785 */ "LDSMAXH\0" + /* 28793 */ "LDUMAXH\0" + /* 28801 */ "FCMGE_PPzZ0_H\0" + /* 28815 */ "FCMLE_PPzZ0_H\0" + /* 28829 */ "FCMNE_PPzZ0_H\0" + /* 28843 */ "FCMEQ_PPzZ0_H\0" + /* 28857 */ "FCMGT_PPzZ0_H\0" + /* 28871 */ "FCMLT_PPzZ0_H\0" + /* 28885 */ "LD1B_H\0" + /* 28892 */ "LDFF1B_H\0" + /* 28901 */ "ST1B_H\0" + /* 28908 */ "LD1SB_H\0" + /* 28916 */ "LDFF1SB_H\0" + /* 28926 */ "PTRUE_H\0" + /* 28934 */ "FSUB_ZPZI_UNDEF_H\0" + /* 28952 */ "FADD_ZPZI_UNDEF_H\0" + /* 28970 */ "LSL_ZPZI_UNDEF_H\0" + /* 28987 */ "FMUL_ZPZI_UNDEF_H\0" + /* 29005 */ "FMINNM_ZPZI_UNDEF_H\0" + /* 29025 */ "FMAXNM_ZPZI_UNDEF_H\0" + /* 29045 */ "FMIN_ZPZI_UNDEF_H\0" + /* 29063 */ "FSUBR_ZPZI_UNDEF_H\0" + /* 29082 */ "ASR_ZPZI_UNDEF_H\0" + /* 29099 */ "LSR_ZPZI_UNDEF_H\0" + /* 29116 */ "FMAX_ZPZI_UNDEF_H\0" + /* 29134 */ "FSUB_ZPZZ_UNDEF_H\0" + /* 29152 */ "FADD_ZPZZ_UNDEF_H\0" + /* 29170 */ "SMULH_ZPZZ_UNDEF_H\0" + /* 29189 */ "UMULH_ZPZZ_UNDEF_H\0" + /* 29208 */ "SQSHL_ZPZZ_UNDEF_H\0" + /* 29227 */ "UQSHL_ZPZZ_UNDEF_H\0" + /* 29246 */ "SQRSHL_ZPZZ_UNDEF_H\0" + /* 29266 */ "UQRSHL_ZPZZ_UNDEF_H\0" + /* 29286 */ "SRSHL_ZPZZ_UNDEF_H\0" + /* 29305 */ "URSHL_ZPZZ_UNDEF_H\0" + /* 29324 */ "LSL_ZPZZ_UNDEF_H\0" + /* 29341 */ "FMUL_ZPZZ_UNDEF_H\0" + /* 29359 */ "FMINNM_ZPZZ_UNDEF_H\0" + /* 29379 */ "FMAXNM_ZPZZ_UNDEF_H\0" + /* 29399 */ "FMIN_ZPZZ_UNDEF_H\0" + /* 29417 */ "SMIN_ZPZZ_UNDEF_H\0" + /* 29435 */ "UMIN_ZPZZ_UNDEF_H\0" + /* 29453 */ "ASR_ZPZZ_UNDEF_H\0" + /* 29470 */ "LSR_ZPZZ_UNDEF_H\0" + /* 29487 */ "FDIV_ZPZZ_UNDEF_H\0" + /* 29505 */ "FMAX_ZPZZ_UNDEF_H\0" + /* 29523 */ "SMAX_ZPZZ_UNDEF_H\0" + /* 29541 */ "UMAX_ZPZZ_UNDEF_H\0" + /* 29559 */ "FMLA_ZPZZZ_UNDEF_H\0" + /* 29578 */ "FNMLA_ZPZZZ_UNDEF_H\0" + /* 29598 */ "FMLS_ZPZZZ_UNDEF_H\0" + /* 29617 */ "FNMLS_ZPZZZ_UNDEF_H\0" + /* 29637 */ "FRINTA_ZPmZ_UNDEF_H\0" + /* 29657 */ "SXTB_ZPmZ_UNDEF_H\0" + /* 29675 */ "UXTB_ZPmZ_UNDEF_H\0" + /* 29693 */ "FNEG_ZPmZ_UNDEF_H\0" + /* 29711 */ "SQNEG_ZPmZ_UNDEF_H\0" + /* 29730 */ "FRINTI_ZPmZ_UNDEF_H\0" + /* 29750 */ "FRINTM_ZPmZ_UNDEF_H\0" + /* 29770 */ "FRINTN_ZPmZ_UNDEF_H\0" + /* 29790 */ "FRINTP_ZPmZ_UNDEF_H\0" + /* 29810 */ "FABS_ZPmZ_UNDEF_H\0" + /* 29828 */ "SQABS_ZPmZ_UNDEF_H\0" + /* 29847 */ "CLS_ZPmZ_UNDEF_H\0" + /* 29864 */ "CNT_ZPmZ_UNDEF_H\0" + /* 29881 */ "CNOT_ZPmZ_UNDEF_H\0" + /* 29899 */ "FSQRT_ZPmZ_UNDEF_H\0" + /* 29918 */ "FRECPX_ZPmZ_UNDEF_H\0" + /* 29938 */ "FRINTX_ZPmZ_UNDEF_H\0" + /* 29958 */ "CLZ_ZPmZ_UNDEF_H\0" + /* 29975 */ "FRINTZ_ZPmZ_UNDEF_H\0" + /* 29995 */ "EXTRACT_ZPMXI_H_H\0" + /* 30013 */ "LD1_MXIPXX_H_H\0" + /* 30028 */ "ST1_MXIPXX_H_H\0" + /* 30043 */ "INSERT_MXIPZ_H_H\0" + /* 30060 */ "INDEX_II_H\0" + /* 30071 */ "PSEL_PPPRI_H\0" + /* 30084 */ "INDEX_RI_H\0" + /* 30095 */ "FCMLA_ZZZI_H\0" + /* 30108 */ "FMLA_ZZZI_H\0" + /* 30120 */ "SQRDCMLAH_ZZZI_H\0" + /* 30137 */ "SQRDMLAH_ZZZI_H\0" + /* 30153 */ "SQDMULH_ZZZI_H\0" + /* 30168 */ "SQRDMULH_ZZZI_H\0" + /* 30184 */ "SQRDMLSH_ZZZI_H\0" + /* 30200 */ "FMUL_ZZZI_H\0" + /* 30212 */ "XAR_ZZZI_H\0" + /* 30223 */ "FMLS_ZZZI_H\0" + /* 30235 */ "SRSRA_ZZI_H\0" + /* 30247 */ "URSRA_ZZI_H\0" + /* 30259 */ "SSRA_ZZI_H\0" + /* 30270 */ "USRA_ZZI_H\0" + /* 30281 */ "SSHLLB_ZZI_H\0" + /* 30294 */ "USHLLB_ZZI_H\0" + /* 30307 */ "SQSHRNB_ZZI_H\0" + /* 30321 */ "UQSHRNB_ZZI_H\0" + /* 30335 */ "SQRSHRNB_ZZI_H\0" + /* 30350 */ "UQRSHRNB_ZZI_H\0" + /* 30365 */ "SQSHRUNB_ZZI_H\0" + /* 30380 */ "SQRSHRUNB_ZZI_H\0" + /* 30396 */ "FTMAD_ZZI_H\0" + /* 30408 */ "SQCADD_ZZI_H\0" + /* 30421 */ "SLI_ZZI_H\0" + /* 30431 */ "SRI_ZZI_H\0" + /* 30441 */ "LSL_ZZI_H\0" + /* 30451 */ "DUP_ZZI_H\0" + /* 30461 */ "ASR_ZZI_H\0" + /* 30471 */ "LSR_ZZI_H\0" + /* 30481 */ "SSHLLT_ZZI_H\0" + /* 30494 */ "USHLLT_ZZI_H\0" + /* 30507 */ "SQSHRNT_ZZI_H\0" + /* 30521 */ "UQSHRNT_ZZI_H\0" + /* 30535 */ "SQRSHRNT_ZZI_H\0" + /* 30550 */ "UQRSHRNT_ZZI_H\0" + /* 30565 */ "SQSHRUNT_ZZI_H\0" + /* 30580 */ "SQRSHRUNT_ZZI_H\0" + /* 30596 */ "SQSUB_ZI_H\0" + /* 30607 */ "UQSUB_ZI_H\0" + /* 30618 */ "SQADD_ZI_H\0" + /* 30629 */ "UQADD_ZI_H\0" + /* 30640 */ "MUL_ZI_H\0" + /* 30649 */ "SMIN_ZI_H\0" + /* 30659 */ "UMIN_ZI_H\0" + /* 30669 */ "FDUP_ZI_H\0" + /* 30679 */ "SUBR_ZI_H\0" + /* 30689 */ "SMAX_ZI_H\0" + /* 30699 */ "UMAX_ZI_H\0" + /* 30709 */ "CMPGE_PPzZI_H\0" + /* 30723 */ "CMPLE_PPzZI_H\0" + /* 30737 */ "CMPNE_PPzZI_H\0" + /* 30751 */ "CMPHI_PPzZI_H\0" + /* 30765 */ "CMPLO_PPzZI_H\0" + /* 30779 */ "CMPEQ_PPzZI_H\0" + /* 30793 */ "CMPHS_PPzZI_H\0" + /* 30807 */ "CMPLS_PPzZI_H\0" + /* 30821 */ "CMPGT_PPzZI_H\0" + /* 30835 */ "CMPLT_PPzZI_H\0" + /* 30849 */ "FSUB_ZPmI_H\0" + /* 30861 */ "FADD_ZPmI_H\0" + /* 30873 */ "ASRD_ZPmI_H\0" + /* 30885 */ "SQSHL_ZPmI_H\0" + /* 30898 */ "UQSHL_ZPmI_H\0" + /* 30911 */ "LSL_ZPmI_H\0" + /* 30922 */ "FMUL_ZPmI_H\0" + /* 30934 */ "FMINNM_ZPmI_H\0" + /* 30948 */ "FMAXNM_ZPmI_H\0" + /* 30962 */ "FMIN_ZPmI_H\0" + /* 30974 */ "FSUBR_ZPmI_H\0" + /* 30987 */ "SRSHR_ZPmI_H\0" + /* 31000 */ "URSHR_ZPmI_H\0" + /* 31013 */ "ASR_ZPmI_H\0" + /* 31024 */ "LSR_ZPmI_H\0" + /* 31035 */ "SQSHLU_ZPmI_H\0" + /* 31049 */ "FMAX_ZPmI_H\0" + /* 31061 */ "FCPY_ZPmI_H\0" + /* 31073 */ "CPY_ZPzI_H\0" + /* 31084 */ "LD1RO_H\0" + /* 31092 */ "FSUB_ZPZI_ZERO_H\0" + /* 31109 */ "FADD_ZPZI_ZERO_H\0" + /* 31126 */ "ASRD_ZPZI_ZERO_H\0" + /* 31143 */ "SQSHL_ZPZI_ZERO_H\0" + /* 31161 */ "UQSHL_ZPZI_ZERO_H\0" + /* 31179 */ "FMUL_ZPZI_ZERO_H\0" + /* 31196 */ "FMINNM_ZPZI_ZERO_H\0" + /* 31215 */ "FMAXNM_ZPZI_ZERO_H\0" + /* 31234 */ "FMIN_ZPZI_ZERO_H\0" + /* 31251 */ "FSUBR_ZPZI_ZERO_H\0" + /* 31269 */ "SRSHR_ZPZI_ZERO_H\0" + /* 31287 */ "URSHR_ZPZI_ZERO_H\0" + /* 31305 */ "SQSHLU_ZPZI_ZERO_H\0" + /* 31324 */ "FMAX_ZPZI_ZERO_H\0" + /* 31341 */ "FSUB_ZPZZ_ZERO_H\0" + /* 31358 */ "FABD_ZPZZ_ZERO_H\0" + /* 31375 */ "FADD_ZPZZ_ZERO_H\0" + /* 31392 */ "LSL_ZPZZ_ZERO_H\0" + /* 31408 */ "FMUL_ZPZZ_ZERO_H\0" + /* 31425 */ "FMINNM_ZPZZ_ZERO_H\0" + /* 31444 */ "FMAXNM_ZPZZ_ZERO_H\0" + /* 31463 */ "FMIN_ZPZZ_ZERO_H\0" + /* 31480 */ "FSUBR_ZPZZ_ZERO_H\0" + /* 31498 */ "ASR_ZPZZ_ZERO_H\0" + /* 31514 */ "LSR_ZPZZ_ZERO_H\0" + /* 31530 */ "FDIVR_ZPZZ_ZERO_H\0" + /* 31548 */ "FDIV_ZPZZ_ZERO_H\0" + /* 31565 */ "FMAX_ZPZZ_ZERO_H\0" + /* 31582 */ "FMULX_ZPZZ_ZERO_H\0" + /* 31600 */ "TRN1_PPP_H\0" + /* 31611 */ "ZIP1_PPP_H\0" + /* 31622 */ "UZP1_PPP_H\0" + /* 31633 */ "TRN2_PPP_H\0" + /* 31644 */ "ZIP2_PPP_H\0" + /* 31655 */ "UZP2_PPP_H\0" + /* 31666 */ "CNTP_XPP_H\0" + /* 31677 */ "REV_PP_H\0" + /* 31686 */ "UQDECP_WP_H\0" + /* 31698 */ "UQINCP_WP_H\0" + /* 31710 */ "SQDECP_XP_H\0" + /* 31722 */ "UQDECP_XP_H\0" + /* 31734 */ "SQINCP_XP_H\0" + /* 31746 */ "UQINCP_XP_H\0" + /* 31758 */ "SQDECP_ZP_H\0" + /* 31770 */ "UQDECP_ZP_H\0" + /* 31782 */ "SQINCP_ZP_H\0" + /* 31794 */ "UQINCP_ZP_H\0" + /* 31806 */ "LD1RQ_H\0" + /* 31814 */ "INDEX_IR_H\0" + /* 31825 */ "INDEX_RR_H\0" + /* 31836 */ "DUP_ZR_H\0" + /* 31845 */ "INSR_ZR_H\0" + /* 31855 */ "CPY_ZPmR_H\0" + /* 31866 */ "PTRUES_H\0" + /* 31875 */ "PNEXT_H\0" + /* 31883 */ "INSR_ZV_H\0" + /* 31893 */ "EXTRACT_ZPMXI_V_H\0" + /* 31911 */ "LD1_MXIPXX_V_H\0" + /* 31926 */ "ST1_MXIPXX_V_H\0" + /* 31941 */ "INSERT_MXIPZ_V_H\0" + /* 31958 */ "CPY_ZPmV_H\0" + /* 31969 */ "WHILEGE_PWW_H\0" + /* 31983 */ "WHILELE_PWW_H\0" + /* 31997 */ "WHILEHI_PWW_H\0" + /* 32011 */ "WHILELO_PWW_H\0" + /* 32025 */ "WHILEHS_PWW_H\0" + /* 32039 */ "WHILELS_PWW_H\0" + /* 32053 */ "WHILEGT_PWW_H\0" + /* 32067 */ "WHILELT_PWW_H\0" + /* 32081 */ "WHILEGE_PXX_H\0" + /* 32095 */ "WHILELE_PXX_H\0" + /* 32109 */ "WHILEHI_PXX_H\0" + /* 32123 */ "WHILELO_PXX_H\0" + /* 32137 */ "WHILEWR_PXX_H\0" + /* 32151 */ "WHILEHS_PXX_H\0" + /* 32165 */ "WHILELS_PXX_H\0" + /* 32179 */ "WHILEGT_PXX_H\0" + /* 32193 */ "WHILELT_PXX_H\0" + /* 32207 */ "WHILERW_PXX_H\0" + /* 32221 */ "CLASTA_RPZ_H\0" + /* 32234 */ "CLASTB_RPZ_H\0" + /* 32247 */ "FADDA_VPZ_H\0" + /* 32259 */ "CLASTA_VPZ_H\0" + /* 32272 */ "CLASTB_VPZ_H\0" + /* 32285 */ "FADDV_VPZ_H\0" + /* 32297 */ "SADDV_VPZ_H\0" + /* 32309 */ "UADDV_VPZ_H\0" + /* 32321 */ "ANDV_VPZ_H\0" + /* 32332 */ "FMINNMV_VPZ_H\0" + /* 32346 */ "FMAXNMV_VPZ_H\0" + /* 32360 */ "FMINV_VPZ_H\0" + /* 32372 */ "SMINV_VPZ_H\0" + /* 32384 */ "UMINV_VPZ_H\0" + /* 32396 */ "EORV_VPZ_H\0" + /* 32407 */ "FMAXV_VPZ_H\0" + /* 32419 */ "SMAXV_VPZ_H\0" + /* 32431 */ "UMAXV_VPZ_H\0" + /* 32443 */ "CLASTA_ZPZ_H\0" + /* 32456 */ "CLASTB_ZPZ_H\0" + /* 32469 */ "SPLICE_ZPZ_H\0" + /* 32482 */ "SPLICE_ZPZZ_H\0" + /* 32496 */ "SEL_ZPZZ_H\0" + /* 32507 */ "TBL_ZZZZ_H\0" + /* 32518 */ "TRN1_ZZZ_H\0" + /* 32529 */ "ZIP1_ZZZ_H\0" + /* 32540 */ "UZP1_ZZZ_H\0" + /* 32551 */ "TRN2_ZZZ_H\0" + /* 32562 */ "ZIP2_ZZZ_H\0" + /* 32573 */ "UZP2_ZZZ_H\0" + /* 32584 */ "SABA_ZZZ_H\0" + /* 32595 */ "UABA_ZZZ_H\0" + /* 32606 */ "CMLA_ZZZ_H\0" + /* 32617 */ "SABALB_ZZZ_H\0" + /* 32630 */ "UABALB_ZZZ_H\0" + /* 32643 */ "SQDMLALB_ZZZ_H\0" + /* 32658 */ "SMLALB_ZZZ_H\0" + /* 32671 */ "UMLALB_ZZZ_H\0" + /* 32684 */ "SSUBLB_ZZZ_H\0" + /* 32697 */ "USUBLB_ZZZ_H\0" + /* 32710 */ "SABDLB_ZZZ_H\0" + /* 32723 */ "UABDLB_ZZZ_H\0" + /* 32736 */ "SADDLB_ZZZ_H\0" + /* 32749 */ "UADDLB_ZZZ_H\0" + /* 32762 */ "SQDMULLB_ZZZ_H\0" + /* 32777 */ "PMULLB_ZZZ_H\0" + /* 32790 */ "SMULLB_ZZZ_H\0" + /* 32803 */ "UMULLB_ZZZ_H\0" + /* 32816 */ "SQDMLSLB_ZZZ_H\0" + /* 32831 */ "SMLSLB_ZZZ_H\0" + /* 32844 */ "UMLSLB_ZZZ_H\0" + /* 32857 */ "RSUBHNB_ZZZ_H\0" + /* 32871 */ "RADDHNB_ZZZ_H\0" + /* 32885 */ "SSUBLTB_ZZZ_H\0" + /* 32899 */ "EORTB_ZZZ_H\0" + /* 32911 */ "FSUB_ZZZ_H\0" + /* 32922 */ "SQSUB_ZZZ_H\0" + /* 32934 */ "UQSUB_ZZZ_H\0" + /* 32946 */ "SSUBWB_ZZZ_H\0" + /* 32959 */ "USUBWB_ZZZ_H\0" + /* 32972 */ "SADDWB_ZZZ_H\0" + /* 32985 */ "UADDWB_ZZZ_H\0" + /* 32998 */ "FADD_ZZZ_H\0" + /* 33009 */ "SQADD_ZZZ_H\0" + /* 33021 */ "UQADD_ZZZ_H\0" + /* 33033 */ "LSL_WIDE_ZZZ_H\0" + /* 33048 */ "ASR_WIDE_ZZZ_H\0" + /* 33063 */ "LSR_WIDE_ZZZ_H\0" + /* 33078 */ "SQRDCMLAH_ZZZ_H\0" + /* 33094 */ "SQRDMLAH_ZZZ_H\0" + /* 33109 */ "SQDMULH_ZZZ_H\0" + /* 33123 */ "SQRDMULH_ZZZ_H\0" + /* 33138 */ "SMULH_ZZZ_H\0" + /* 33150 */ "UMULH_ZZZ_H\0" + /* 33162 */ "SQRDMLSH_ZZZ_H\0" + /* 33177 */ "TBL_ZZZ_H\0" + /* 33187 */ "FTSSEL_ZZZ_H\0" + /* 33200 */ "FMUL_ZZZ_H\0" + /* 33211 */ "FTSMUL_ZZZ_H\0" + /* 33224 */ "BDEP_ZZZ_H\0" + /* 33235 */ "SCLAMP_ZZZ_H\0" + /* 33248 */ "UCLAMP_ZZZ_H\0" + /* 33261 */ "BGRP_ZZZ_H\0" + /* 33272 */ "FRECPS_ZZZ_H\0" + /* 33285 */ "FRSQRTS_ZZZ_H\0" + /* 33299 */ "SQDMLALBT_ZZZ_H\0" + /* 33315 */ "SSUBLBT_ZZZ_H\0" + /* 33329 */ "SADDLBT_ZZZ_H\0" + /* 33343 */ "SQDMLSLBT_ZZZ_H\0" + /* 33359 */ "EORBT_ZZZ_H\0" + /* 33371 */ "SABALT_ZZZ_H\0" + /* 33384 */ "UABALT_ZZZ_H\0" + /* 33397 */ "SQDMLALT_ZZZ_H\0" + /* 33412 */ "SMLALT_ZZZ_H\0" + /* 33425 */ "UMLALT_ZZZ_H\0" + /* 33438 */ "SSUBLT_ZZZ_H\0" + /* 33451 */ "USUBLT_ZZZ_H\0" + /* 33464 */ "SABDLT_ZZZ_H\0" + /* 33477 */ "UABDLT_ZZZ_H\0" + /* 33490 */ "SADDLT_ZZZ_H\0" + /* 33503 */ "UADDLT_ZZZ_H\0" + /* 33516 */ "SQDMULLT_ZZZ_H\0" + /* 33531 */ "PMULLT_ZZZ_H\0" + /* 33544 */ "SMULLT_ZZZ_H\0" + /* 33557 */ "UMULLT_ZZZ_H\0" + /* 33570 */ "SQDMLSLT_ZZZ_H\0" + /* 33585 */ "SMLSLT_ZZZ_H\0" + /* 33598 */ "UMLSLT_ZZZ_H\0" + /* 33611 */ "RSUBHNT_ZZZ_H\0" + /* 33625 */ "RADDHNT_ZZZ_H\0" + /* 33639 */ "SSUBWT_ZZZ_H\0" + /* 33652 */ "USUBWT_ZZZ_H\0" + /* 33665 */ "SADDWT_ZZZ_H\0" + /* 33678 */ "UADDWT_ZZZ_H\0" + /* 33691 */ "BEXT_ZZZ_H\0" + /* 33702 */ "TBX_ZZZ_H\0" + /* 33712 */ "FEXPA_ZZ_H\0" + /* 33723 */ "SQXTNB_ZZ_H\0" + /* 33735 */ "UQXTNB_ZZ_H\0" + /* 33747 */ "SQXTUNB_ZZ_H\0" + /* 33760 */ "FRECPE_ZZ_H\0" + /* 33772 */ "FRSQRTE_ZZ_H\0" + /* 33785 */ "SUNPKHI_ZZ_H\0" + /* 33798 */ "UUNPKHI_ZZ_H\0" + /* 33811 */ "SUNPKLO_ZZ_H\0" + /* 33824 */ "UUNPKLO_ZZ_H\0" + /* 33837 */ "SQXTNT_ZZ_H\0" + /* 33849 */ "UQXTNT_ZZ_H\0" + /* 33861 */ "SQXTUNT_ZZ_H\0" + /* 33874 */ "REV_ZZ_H\0" + /* 33883 */ "FCMLA_ZPmZZ_H\0" + /* 33897 */ "FMLA_ZPmZZ_H\0" + /* 33910 */ "FNMLA_ZPmZZ_H\0" + /* 33924 */ "FMSB_ZPmZZ_H\0" + /* 33937 */ "FNMSB_ZPmZZ_H\0" + /* 33951 */ "FMAD_ZPmZZ_H\0" + /* 33964 */ "FNMAD_ZPmZZ_H\0" + /* 33978 */ "FADDP_ZPmZZ_H\0" + /* 33992 */ "FMINNMP_ZPmZZ_H\0" + /* 34008 */ "FMAXNMP_ZPmZZ_H\0" + /* 34024 */ "FMINP_ZPmZZ_H\0" + /* 34038 */ "FMAXP_ZPmZZ_H\0" + /* 34052 */ "FMLS_ZPmZZ_H\0" + /* 34065 */ "FNMLS_ZPmZZ_H\0" + /* 34079 */ "CMPGE_WIDE_PPzZZ_H\0" + /* 34098 */ "CMPLE_WIDE_PPzZZ_H\0" + /* 34117 */ "CMPNE_WIDE_PPzZZ_H\0" + /* 34136 */ "CMPHI_WIDE_PPzZZ_H\0" + /* 34155 */ "CMPLO_WIDE_PPzZZ_H\0" + /* 34174 */ "CMPEQ_WIDE_PPzZZ_H\0" + /* 34193 */ "CMPHS_WIDE_PPzZZ_H\0" + /* 34212 */ "CMPLS_WIDE_PPzZZ_H\0" + /* 34231 */ "CMPGT_WIDE_PPzZZ_H\0" + /* 34250 */ "CMPLT_WIDE_PPzZZ_H\0" + /* 34269 */ "FACGE_PPzZZ_H\0" + /* 34283 */ "FCMGE_PPzZZ_H\0" + /* 34297 */ "CMPGE_PPzZZ_H\0" + /* 34311 */ "FCMNE_PPzZZ_H\0" + /* 34325 */ "CMPNE_PPzZZ_H\0" + /* 34339 */ "NMATCH_PPzZZ_H\0" + /* 34354 */ "CMPHI_PPzZZ_H\0" + /* 34368 */ "FCMUO_PPzZZ_H\0" + /* 34382 */ "FCMEQ_PPzZZ_H\0" + /* 34396 */ "CMPEQ_PPzZZ_H\0" + /* 34410 */ "CMPHS_PPzZZ_H\0" + /* 34424 */ "FACGT_PPzZZ_H\0" + /* 34438 */ "FCMGT_PPzZZ_H\0" + /* 34452 */ "CMPGT_PPzZZ_H\0" + /* 34466 */ "FRINTA_ZPmZ_H\0" + /* 34480 */ "FLOGB_ZPmZ_H\0" + /* 34493 */ "SXTB_ZPmZ_H\0" + /* 34505 */ "UXTB_ZPmZ_H\0" + /* 34517 */ "FSUB_ZPmZ_H\0" + /* 34529 */ "SHSUB_ZPmZ_H\0" + /* 34542 */ "UHSUB_ZPmZ_H\0" + /* 34555 */ "SQSUB_ZPmZ_H\0" + /* 34568 */ "UQSUB_ZPmZ_H\0" + /* 34581 */ "REVB_ZPmZ_H\0" + /* 34593 */ "BIC_ZPmZ_H\0" + /* 34604 */ "FABD_ZPmZ_H\0" + /* 34616 */ "SABD_ZPmZ_H\0" + /* 34628 */ "UABD_ZPmZ_H\0" + /* 34640 */ "FCADD_ZPmZ_H\0" + /* 34653 */ "FADD_ZPmZ_H\0" + /* 34665 */ "SRHADD_ZPmZ_H\0" + /* 34679 */ "URHADD_ZPmZ_H\0" + /* 34693 */ "SHADD_ZPmZ_H\0" + /* 34706 */ "UHADD_ZPmZ_H\0" + /* 34719 */ "USQADD_ZPmZ_H\0" + /* 34733 */ "SUQADD_ZPmZ_H\0" + /* 34747 */ "AND_ZPmZ_H\0" + /* 34758 */ "LSL_WIDE_ZPmZ_H\0" + /* 34774 */ "ASR_WIDE_ZPmZ_H\0" + /* 34790 */ "LSR_WIDE_ZPmZ_H\0" + /* 34806 */ "FSCALE_ZPmZ_H\0" + /* 34820 */ "FNEG_ZPmZ_H\0" + /* 34832 */ "SQNEG_ZPmZ_H\0" + /* 34845 */ "SMULH_ZPmZ_H\0" + /* 34858 */ "UMULH_ZPmZ_H\0" + /* 34871 */ "FRINTI_ZPmZ_H\0" + /* 34885 */ "SQSHL_ZPmZ_H\0" + /* 34898 */ "UQSHL_ZPmZ_H\0" + /* 34911 */ "SQRSHL_ZPmZ_H\0" + /* 34925 */ "UQRSHL_ZPmZ_H\0" + /* 34939 */ "SRSHL_ZPmZ_H\0" + /* 34952 */ "URSHL_ZPmZ_H\0" + /* 34965 */ "LSL_ZPmZ_H\0" + /* 34976 */ "FMUL_ZPmZ_H\0" + /* 34988 */ "FMINNM_ZPmZ_H\0" + /* 35002 */ "FMAXNM_ZPmZ_H\0" + /* 35016 */ "FRINTM_ZPmZ_H\0" + /* 35030 */ "FMIN_ZPmZ_H\0" + /* 35042 */ "SMIN_ZPmZ_H\0" + /* 35054 */ "UMIN_ZPmZ_H\0" + /* 35066 */ "FRINTN_ZPmZ_H\0" + /* 35080 */ "ADDP_ZPmZ_H\0" + /* 35092 */ "SADALP_ZPmZ_H\0" + /* 35106 */ "UADALP_ZPmZ_H\0" + /* 35120 */ "SMINP_ZPmZ_H\0" + /* 35133 */ "UMINP_ZPmZ_H\0" + /* 35146 */ "FRINTP_ZPmZ_H\0" + /* 35160 */ "SMAXP_ZPmZ_H\0" + /* 35173 */ "UMAXP_ZPmZ_H\0" + /* 35186 */ "FSUBR_ZPmZ_H\0" + /* 35199 */ "SHSUBR_ZPmZ_H\0" + /* 35213 */ "UHSUBR_ZPmZ_H\0" + /* 35227 */ "SQSUBR_ZPmZ_H\0" + /* 35241 */ "UQSUBR_ZPmZ_H\0" + /* 35255 */ "SQSHLR_ZPmZ_H\0" + /* 35269 */ "UQSHLR_ZPmZ_H\0" + /* 35283 */ "SQRSHLR_ZPmZ_H\0" + /* 35298 */ "UQRSHLR_ZPmZ_H\0" + /* 35313 */ "SRSHLR_ZPmZ_H\0" + /* 35327 */ "URSHLR_ZPmZ_H\0" + /* 35341 */ "LSLR_ZPmZ_H\0" + /* 35353 */ "EOR_ZPmZ_H\0" + /* 35364 */ "ORR_ZPmZ_H\0" + /* 35375 */ "ASRR_ZPmZ_H\0" + /* 35387 */ "LSRR_ZPmZ_H\0" + /* 35399 */ "ASR_ZPmZ_H\0" + /* 35410 */ "LSR_ZPmZ_H\0" + /* 35421 */ "FDIVR_ZPmZ_H\0" + /* 35434 */ "FABS_ZPmZ_H\0" + /* 35446 */ "SQABS_ZPmZ_H\0" + /* 35459 */ "CLS_ZPmZ_H\0" + /* 35470 */ "RBIT_ZPmZ_H\0" + /* 35482 */ "CNT_ZPmZ_H\0" + /* 35493 */ "CNOT_ZPmZ_H\0" + /* 35505 */ "FSQRT_ZPmZ_H\0" + /* 35518 */ "FDIV_ZPmZ_H\0" + /* 35530 */ "FMAX_ZPmZ_H\0" + /* 35542 */ "SMAX_ZPmZ_H\0" + /* 35554 */ "UMAX_ZPmZ_H\0" + /* 35566 */ "MOVPRFX_ZPmZ_H\0" + /* 35581 */ "FMULX_ZPmZ_H\0" + /* 35594 */ "FRECPX_ZPmZ_H\0" + /* 35608 */ "FRINTX_ZPmZ_H\0" + /* 35622 */ "CLZ_ZPmZ_H\0" + /* 35633 */ "FRINTZ_ZPmZ_H\0" + /* 35647 */ "MOVPRFX_ZPzZ_H\0" + /* 35662 */ "SQDECP_XPWd_H\0" + /* 35676 */ "SQINCP_XPWd_H\0" + /* 35690 */ "SCVTF_ZPmZ_DtoH\0" + /* 35706 */ "UCVTF_ZPmZ_DtoH\0" + /* 35722 */ "FCVT_ZPmZ_DtoH\0" + /* 35737 */ "SCVTF_ZPmZ_HtoH\0" + /* 35753 */ "UCVTF_ZPmZ_HtoH\0" + /* 35769 */ "FCVTZS_ZPmZ_HtoH\0" + /* 35786 */ "FCVTZU_ZPmZ_HtoH\0" + /* 35803 */ "SCVTF_ZPmZ_StoH\0" + /* 35819 */ "UCVTF_ZPmZ_StoH\0" + /* 35835 */ "FCVTNT_ZPmZ_StoH\0" + /* 35852 */ "FCVT_ZPmZ_StoH\0" + /* 35867 */ "XPACI\0" + /* 35873 */ "DBG_PHI\0" + /* 35881 */ "GMI\0" + /* 35885 */ "XPACLRI\0" + /* 35893 */ "PRFB_PRI\0" + /* 35902 */ "PRFD_PRI\0" + /* 35911 */ "PRFH_PRI\0" + /* 35920 */ "PRFW_PRI\0" + /* 35929 */ "LDNT1B_ZRI\0" + /* 35940 */ "STNT1B_ZRI\0" + /* 35951 */ "LDNT1D_ZRI\0" + /* 35962 */ "STNT1D_ZRI\0" + /* 35973 */ "LDNT1H_ZRI\0" + /* 35984 */ "STNT1H_ZRI\0" + /* 35995 */ "LDNT1W_ZRI\0" + /* 36006 */ "STNT1W_ZRI\0" + /* 36017 */ "G_FPTOSI\0" + /* 36026 */ "TCRETURNriBTI\0" + /* 36040 */ "G_FPTOUI\0" + /* 36049 */ "G_FPOWI\0" + /* 36057 */ "LDR_PXI\0" + /* 36065 */ "STR_PXI\0" + /* 36073 */ "ADDPL_XXI\0" + /* 36083 */ "ADDVL_XXI\0" + /* 36093 */ "LDR_ZZZZXI\0" + /* 36104 */ "STR_ZZZZXI\0" + /* 36115 */ "LDR_ZZZXI\0" + /* 36125 */ "STR_ZZZXI\0" + /* 36135 */ "LDR_ZZXI\0" + /* 36144 */ "STR_ZZXI\0" + /* 36153 */ "LDR_ZXI\0" + /* 36161 */ "STR_ZXI\0" + /* 36169 */ "RDVLI_XI\0" + /* 36178 */ "PRFB_D_PZI\0" + /* 36189 */ "PRFD_D_PZI\0" + /* 36200 */ "PRFH_D_PZI\0" + /* 36211 */ "PRFW_D_PZI\0" + /* 36222 */ "PRFB_S_PZI\0" + /* 36233 */ "PRFD_S_PZI\0" + /* 36244 */ "PRFH_S_PZI\0" + /* 36255 */ "PRFW_S_PZI\0" + /* 36266 */ "USDOT_ZZZI\0" + /* 36277 */ "SUDOT_ZZZI\0" + /* 36288 */ "BFMMLA_B_ZZI\0" + /* 36301 */ "BFDOT_ZZI\0" + /* 36311 */ "EXT_ZZI\0" + /* 36319 */ "BFMMLA_T_ZZI\0" + /* 36332 */ "AND_ZI\0" + /* 36339 */ "DUPM_ZI\0" + /* 36347 */ "EOR_ZI\0" + /* 36354 */ "ORR_ZI\0" + /* 36361 */ "SQDECB_XPiWdI\0" + /* 36375 */ "SQINCB_XPiWdI\0" + /* 36389 */ "SQDECD_XPiWdI\0" + /* 36403 */ "SQINCD_XPiWdI\0" + /* 36417 */ "SQDECH_XPiWdI\0" + /* 36431 */ "SQINCH_XPiWdI\0" + /* 36445 */ "SQDECW_XPiWdI\0" + /* 36459 */ "SQINCW_XPiWdI\0" + /* 36473 */ "UQDECB_WPiI\0" + /* 36485 */ "UQINCB_WPiI\0" + /* 36497 */ "UQDECD_WPiI\0" + /* 36509 */ "UQINCD_WPiI\0" + /* 36521 */ "UQDECH_WPiI\0" + /* 36533 */ "UQINCH_WPiI\0" + /* 36545 */ "UQDECW_WPiI\0" + /* 36557 */ "UQINCW_WPiI\0" + /* 36569 */ "SQDECB_XPiI\0" + /* 36581 */ "UQDECB_XPiI\0" + /* 36593 */ "SQINCB_XPiI\0" + /* 36605 */ "UQINCB_XPiI\0" + /* 36617 */ "CNTB_XPiI\0" + /* 36627 */ "SQDECD_XPiI\0" + /* 36639 */ "UQDECD_XPiI\0" + /* 36651 */ "SQINCD_XPiI\0" + /* 36663 */ "UQINCD_XPiI\0" + /* 36675 */ "CNTD_XPiI\0" + /* 36685 */ "SQDECH_XPiI\0" + /* 36697 */ "UQDECH_XPiI\0" + /* 36709 */ "SQINCH_XPiI\0" + /* 36721 */ "UQINCH_XPiI\0" + /* 36733 */ "CNTH_XPiI\0" + /* 36743 */ "SQDECW_XPiI\0" + /* 36755 */ "UQDECW_XPiI\0" + /* 36767 */ "SQINCW_XPiI\0" + /* 36779 */ "UQINCW_XPiI\0" + /* 36791 */ "CNTW_XPiI\0" + /* 36801 */ "SQDECD_ZPiI\0" + /* 36813 */ "UQDECD_ZPiI\0" + /* 36825 */ "SQINCD_ZPiI\0" + /* 36837 */ "UQINCD_ZPiI\0" + /* 36849 */ "SQDECH_ZPiI\0" + /* 36861 */ "UQDECH_ZPiI\0" + /* 36873 */ "SQINCH_ZPiI\0" + /* 36885 */ "UQINCH_ZPiI\0" + /* 36897 */ "SQDECW_ZPiI\0" + /* 36909 */ "UQDECW_ZPiI\0" + /* 36921 */ "SQINCW_ZPiI\0" + /* 36933 */ "UQINCW_ZPiI\0" + /* 36945 */ "BRB_INJ\0" + /* 36953 */ "BRK\0" + /* 36957 */ "G_PTRMASK\0" + /* 36967 */ "LDFF1B_REAL\0" + /* 36979 */ "GLD1D_REAL\0" + /* 36990 */ "GLDFF1D_REAL\0" + /* 37003 */ "SST1D_REAL\0" + /* 37014 */ "GLD1D_SCALED_REAL\0" + /* 37032 */ "GLDFF1D_SCALED_REAL\0" + /* 37052 */ "SST1D_SCALED_SCALED_REAL\0" + /* 37077 */ "SST1H_D_SCALED_SCALED_REAL\0" + /* 37104 */ "SST1W_D_SCALED_SCALED_REAL\0" + /* 37131 */ "GLD1H_D_SCALED_REAL\0" + /* 37151 */ "GLDFF1H_D_SCALED_REAL\0" + /* 37173 */ "GLD1SH_D_SCALED_REAL\0" + /* 37194 */ "GLDFF1SH_D_SCALED_REAL\0" + /* 37217 */ "GLD1W_D_SCALED_REAL\0" + /* 37237 */ "GLDFF1W_D_SCALED_REAL\0" + /* 37259 */ "GLD1SW_D_SCALED_REAL\0" + /* 37280 */ "GLDFF1SW_D_SCALED_REAL\0" + /* 37303 */ "GLD1D_SXTW_SCALED_REAL\0" + /* 37326 */ "GLDFF1D_SXTW_SCALED_REAL\0" + /* 37351 */ "GLD1H_D_SXTW_SCALED_REAL\0" + /* 37376 */ "GLDFF1H_D_SXTW_SCALED_REAL\0" + /* 37403 */ "GLD1SH_D_SXTW_SCALED_REAL\0" + /* 37429 */ "GLDFF1SH_D_SXTW_SCALED_REAL\0" + /* 37457 */ "GLD1W_D_SXTW_SCALED_REAL\0" + /* 37482 */ "GLDFF1W_D_SXTW_SCALED_REAL\0" + /* 37509 */ "GLD1SW_D_SXTW_SCALED_REAL\0" + /* 37535 */ "GLDFF1SW_D_SXTW_SCALED_REAL\0" + /* 37563 */ "GLD1H_S_SXTW_SCALED_REAL\0" + /* 37588 */ "GLDFF1H_S_SXTW_SCALED_REAL\0" + /* 37615 */ "GLD1SH_S_SXTW_SCALED_REAL\0" + /* 37641 */ "GLDFF1SH_S_SXTW_SCALED_REAL\0" + /* 37669 */ "GLD1W_SXTW_SCALED_REAL\0" + /* 37692 */ "GLDFF1W_SXTW_SCALED_REAL\0" + /* 37717 */ "GLD1D_UXTW_SCALED_REAL\0" + /* 37740 */ "GLDFF1D_UXTW_SCALED_REAL\0" + /* 37765 */ "GLD1H_D_UXTW_SCALED_REAL\0" + /* 37790 */ "GLDFF1H_D_UXTW_SCALED_REAL\0" + /* 37817 */ "GLD1SH_D_UXTW_SCALED_REAL\0" + /* 37843 */ "GLDFF1SH_D_UXTW_SCALED_REAL\0" + /* 37871 */ "GLD1W_D_UXTW_SCALED_REAL\0" + /* 37896 */ "GLDFF1W_D_UXTW_SCALED_REAL\0" + /* 37923 */ "GLD1SW_D_UXTW_SCALED_REAL\0" + /* 37949 */ "GLDFF1SW_D_UXTW_SCALED_REAL\0" + /* 37977 */ "GLD1H_S_UXTW_SCALED_REAL\0" + /* 38002 */ "GLDFF1H_S_UXTW_SCALED_REAL\0" + /* 38029 */ "GLD1SH_S_UXTW_SCALED_REAL\0" + /* 38055 */ "GLDFF1SH_S_UXTW_SCALED_REAL\0" + /* 38083 */ "GLD1W_UXTW_SCALED_REAL\0" + /* 38106 */ "GLDFF1W_UXTW_SCALED_REAL\0" + /* 38131 */ "GLD1B_D_REAL\0" + /* 38144 */ "GLDFF1B_D_REAL\0" + /* 38159 */ "SST1B_D_REAL\0" + /* 38172 */ "GLD1SB_D_REAL\0" + /* 38186 */ "GLDFF1SB_D_REAL\0" + /* 38202 */ "GLD1H_D_REAL\0" + /* 38215 */ "GLDFF1H_D_REAL\0" + /* 38230 */ "SST1H_D_REAL\0" + /* 38243 */ "GLD1SH_D_REAL\0" + /* 38257 */ "GLDFF1SH_D_REAL\0" + /* 38273 */ "LDNT1B_ZZR_D_REAL\0" + /* 38291 */ "STNT1B_ZZR_D_REAL\0" + /* 38309 */ "LDNT1SB_ZZR_D_REAL\0" + /* 38328 */ "LDNT1D_ZZR_D_REAL\0" + /* 38346 */ "STNT1D_ZZR_D_REAL\0" + /* 38364 */ "LDNT1H_ZZR_D_REAL\0" + /* 38382 */ "STNT1H_ZZR_D_REAL\0" + /* 38400 */ "LDNT1SH_ZZR_D_REAL\0" + /* 38419 */ "LDNT1W_ZZR_D_REAL\0" + /* 38437 */ "STNT1W_ZZR_D_REAL\0" + /* 38455 */ "LDNT1SW_ZZR_D_REAL\0" + /* 38474 */ "GLD1W_D_REAL\0" + /* 38487 */ "GLDFF1W_D_REAL\0" + /* 38502 */ "SST1W_D_REAL\0" + /* 38515 */ "GLD1SW_D_REAL\0" + /* 38529 */ "GLDFF1SW_D_REAL\0" + /* 38545 */ "LDFF1H_REAL\0" + /* 38557 */ "LDFF1B_H_REAL\0" + /* 38571 */ "LDFF1SB_H_REAL\0" + /* 38586 */ "LD1B_IMM_REAL\0" + /* 38600 */ "LDNF1B_IMM_REAL\0" + /* 38616 */ "GLD1D_IMM_REAL\0" + /* 38631 */ "GLDFF1D_IMM_REAL\0" + /* 38648 */ "LDNF1D_IMM_REAL\0" + /* 38664 */ "GLD1B_D_IMM_REAL\0" + /* 38681 */ "GLDFF1B_D_IMM_REAL\0" + /* 38700 */ "LDNF1B_D_IMM_REAL\0" + /* 38718 */ "GLD1SB_D_IMM_REAL\0" + /* 38736 */ "GLDFF1SB_D_IMM_REAL\0" + /* 38756 */ "LDNF1SB_D_IMM_REAL\0" + /* 38775 */ "GLD1H_D_IMM_REAL\0" + /* 38792 */ "GLDFF1H_D_IMM_REAL\0" + /* 38811 */ "LDNF1H_D_IMM_REAL\0" + /* 38829 */ "GLD1SH_D_IMM_REAL\0" + /* 38847 */ "GLDFF1SH_D_IMM_REAL\0" + /* 38867 */ "LDNF1SH_D_IMM_REAL\0" + /* 38886 */ "GLD1W_D_IMM_REAL\0" + /* 38903 */ "GLDFF1W_D_IMM_REAL\0" + /* 38922 */ "LDNF1W_D_IMM_REAL\0" + /* 38940 */ "GLD1SW_D_IMM_REAL\0" + /* 38958 */ "GLDFF1SW_D_IMM_REAL\0" + /* 38978 */ "LDNF1SW_D_IMM_REAL\0" + /* 38997 */ "LD1H_IMM_REAL\0" + /* 39011 */ "LDNF1H_IMM_REAL\0" + /* 39027 */ "LD1B_H_IMM_REAL\0" + /* 39043 */ "LDNF1B_H_IMM_REAL\0" + /* 39061 */ "LD1SB_H_IMM_REAL\0" + /* 39078 */ "LDNF1SB_H_IMM_REAL\0" + /* 39097 */ "GLD1B_S_IMM_REAL\0" + /* 39114 */ "GLDFF1B_S_IMM_REAL\0" + /* 39133 */ "LDNF1B_S_IMM_REAL\0" + /* 39151 */ "GLD1SB_S_IMM_REAL\0" + /* 39169 */ "GLDFF1SB_S_IMM_REAL\0" + /* 39189 */ "LDNF1SB_S_IMM_REAL\0" + /* 39208 */ "GLD1H_S_IMM_REAL\0" + /* 39225 */ "GLDFF1H_S_IMM_REAL\0" + /* 39244 */ "LDNF1H_S_IMM_REAL\0" + /* 39262 */ "GLD1SH_S_IMM_REAL\0" + /* 39280 */ "GLDFF1SH_S_IMM_REAL\0" + /* 39300 */ "LDNF1SH_S_IMM_REAL\0" + /* 39319 */ "GLD1W_IMM_REAL\0" + /* 39334 */ "GLDFF1W_IMM_REAL\0" + /* 39351 */ "LDNF1W_IMM_REAL\0" + /* 39367 */ "RDFFR_P_REAL\0" + /* 39380 */ "LDFF1B_S_REAL\0" + /* 39394 */ "LDFF1SB_S_REAL\0" + /* 39409 */ "LDFF1H_S_REAL\0" + /* 39423 */ "LDFF1SH_S_REAL\0" + /* 39438 */ "LDNT1B_ZZR_S_REAL\0" + /* 39456 */ "STNT1B_ZZR_S_REAL\0" + /* 39474 */ "LDNT1SB_ZZR_S_REAL\0" + /* 39493 */ "LDNT1H_ZZR_S_REAL\0" + /* 39511 */ "STNT1H_ZZR_S_REAL\0" + /* 39529 */ "LDNT1SH_ZZR_S_REAL\0" + /* 39548 */ "LDNT1W_ZZR_S_REAL\0" + /* 39566 */ "STNT1W_ZZR_S_REAL\0" + /* 39584 */ "LDFF1W_REAL\0" + /* 39596 */ "GLD1D_SXTW_REAL\0" + /* 39612 */ "GLDFF1D_SXTW_REAL\0" + /* 39630 */ "GLD1B_D_SXTW_REAL\0" + /* 39648 */ "GLDFF1B_D_SXTW_REAL\0" + /* 39668 */ "GLD1SB_D_SXTW_REAL\0" + /* 39687 */ "GLDFF1SB_D_SXTW_REAL\0" + /* 39708 */ "GLD1H_D_SXTW_REAL\0" + /* 39726 */ "GLDFF1H_D_SXTW_REAL\0" + /* 39746 */ "GLD1SH_D_SXTW_REAL\0" + /* 39765 */ "GLDFF1SH_D_SXTW_REAL\0" + /* 39786 */ "GLD1W_D_SXTW_REAL\0" + /* 39804 */ "GLDFF1W_D_SXTW_REAL\0" + /* 39824 */ "GLD1SW_D_SXTW_REAL\0" + /* 39843 */ "GLDFF1SW_D_SXTW_REAL\0" + /* 39864 */ "GLD1B_S_SXTW_REAL\0" + /* 39882 */ "GLDFF1B_S_SXTW_REAL\0" + /* 39902 */ "GLD1SB_S_SXTW_REAL\0" + /* 39921 */ "GLDFF1SB_S_SXTW_REAL\0" + /* 39942 */ "GLD1H_S_SXTW_REAL\0" + /* 39960 */ "GLDFF1H_S_SXTW_REAL\0" + /* 39980 */ "GLD1SH_S_SXTW_REAL\0" + /* 39999 */ "GLDFF1SH_S_SXTW_REAL\0" + /* 40020 */ "GLD1W_SXTW_REAL\0" + /* 40036 */ "GLDFF1W_SXTW_REAL\0" + /* 40054 */ "GLD1D_UXTW_REAL\0" + /* 40070 */ "GLDFF1D_UXTW_REAL\0" + /* 40088 */ "GLD1B_D_UXTW_REAL\0" + /* 40106 */ "GLDFF1B_D_UXTW_REAL\0" + /* 40126 */ "GLD1SB_D_UXTW_REAL\0" + /* 40145 */ "GLDFF1SB_D_UXTW_REAL\0" + /* 40166 */ "GLD1H_D_UXTW_REAL\0" + /* 40184 */ "GLDFF1H_D_UXTW_REAL\0" + /* 40204 */ "GLD1SH_D_UXTW_REAL\0" + /* 40223 */ "GLDFF1SH_D_UXTW_REAL\0" + /* 40244 */ "GLD1W_D_UXTW_REAL\0" + /* 40262 */ "GLDFF1W_D_UXTW_REAL\0" + /* 40282 */ "GLD1SW_D_UXTW_REAL\0" + /* 40301 */ "GLDFF1SW_D_UXTW_REAL\0" + /* 40322 */ "GLD1B_S_UXTW_REAL\0" + /* 40340 */ "GLDFF1B_S_UXTW_REAL\0" + /* 40360 */ "GLD1SB_S_UXTW_REAL\0" + /* 40379 */ "GLDFF1SB_S_UXTW_REAL\0" + /* 40400 */ "GLD1H_S_UXTW_REAL\0" + /* 40418 */ "GLDFF1H_S_UXTW_REAL\0" + /* 40438 */ "GLD1SH_S_UXTW_REAL\0" + /* 40457 */ "GLDFF1SH_S_UXTW_REAL\0" + /* 40478 */ "GLD1W_UXTW_REAL\0" + /* 40494 */ "GLDFF1W_UXTW_REAL\0" + /* 40512 */ "RDFFR_PPz_REAL\0" + /* 40527 */ "BL\0" + /* 40530 */ "GC_LABEL\0" + /* 40539 */ "DBG_LABEL\0" + /* 40549 */ "EH_LABEL\0" + /* 40558 */ "ANNOTATION_LABEL\0" + /* 40575 */ "TCANCEL\0" + /* 40583 */ "ICALL_BRANCH_FUNNEL\0" + /* 40603 */ "F128CSEL\0" + /* 40612 */ "G_FSHL\0" + /* 40619 */ "G_SHL\0" + /* 40625 */ "G_FCEIL\0" + /* 40633 */ "TLSDESCCALL\0" + /* 40645 */ "PATCHABLE_TAIL_CALL\0" + /* 40665 */ "PATCHABLE_TYPED_EVENT_CALL\0" + /* 40692 */ "PATCHABLE_EVENT_CALL\0" + /* 40713 */ "FENTRY_CALL\0" + /* 40725 */ "BRB_IALL\0" + /* 40734 */ "TCRETURNriALL\0" + /* 40748 */ "KILL\0" + /* 40753 */ "G_ROTL\0" + /* 40760 */ "G_VECREDUCE_FMUL\0" + /* 40777 */ "G_FMUL\0" + /* 40784 */ "G_VECREDUCE_SEQ_FMUL\0" + /* 40805 */ "G_STRICT_FMUL\0" + /* 40819 */ "G_VECREDUCE_MUL\0" + /* 40835 */ "G_MUL\0" + /* 40841 */ "G_FREM\0" + /* 40848 */ "G_STRICT_FREM\0" + /* 40862 */ "G_SREM\0" + /* 40869 */ "G_UREM\0" + /* 40876 */ "G_SDIVREM\0" + /* 40886 */ "G_UDIVREM\0" + /* 40896 */ "LDGM\0" + /* 40901 */ "STGM\0" + /* 40906 */ "STZGM\0" + /* 40912 */ "LD1B_IMM\0" + /* 40921 */ "LDNF1B_IMM\0" + /* 40932 */ "ST1B_IMM\0" + /* 40941 */ "LD2B_IMM\0" + /* 40950 */ "ST2B_IMM\0" + /* 40959 */ "LD3B_IMM\0" + /* 40968 */ "ST3B_IMM\0" + /* 40977 */ "LD4B_IMM\0" + /* 40986 */ "ST4B_IMM\0" + /* 40995 */ "LD1RB_IMM\0" + /* 41005 */ "LD1RO_B_IMM\0" + /* 41017 */ "LD1RQ_B_IMM\0" + /* 41029 */ "GLD1D_IMM\0" + /* 41039 */ "GLDFF1D_IMM\0" + /* 41051 */ "LDNF1D_IMM\0" + /* 41062 */ "SST1D_IMM\0" + /* 41072 */ "LD2D_IMM\0" + /* 41081 */ "ST2D_IMM\0" + /* 41090 */ "LD3D_IMM\0" + /* 41099 */ "ST3D_IMM\0" + /* 41108 */ "LD4D_IMM\0" + /* 41117 */ "ST4D_IMM\0" + /* 41126 */ "LD1RD_IMM\0" + /* 41136 */ "GLD1B_D_IMM\0" + /* 41148 */ "GLDFF1B_D_IMM\0" + /* 41162 */ "LDNF1B_D_IMM\0" + /* 41175 */ "SST1B_D_IMM\0" + /* 41187 */ "LD1RB_D_IMM\0" + /* 41199 */ "GLD1SB_D_IMM\0" + /* 41212 */ "GLDFF1SB_D_IMM\0" + /* 41227 */ "LDNF1SB_D_IMM\0" + /* 41241 */ "LD1RSB_D_IMM\0" + /* 41254 */ "GLD1H_D_IMM\0" + /* 41266 */ "GLDFF1H_D_IMM\0" + /* 41280 */ "LDNF1H_D_IMM\0" + /* 41293 */ "SST1H_D_IMM\0" + /* 41305 */ "LD1RH_D_IMM\0" + /* 41317 */ "GLD1SH_D_IMM\0" + /* 41330 */ "GLDFF1SH_D_IMM\0" + /* 41345 */ "LDNF1SH_D_IMM\0" + /* 41359 */ "LD1RSH_D_IMM\0" + /* 41372 */ "LD1RO_D_IMM\0" + /* 41384 */ "LD1RQ_D_IMM\0" + /* 41396 */ "GLD1W_D_IMM\0" + /* 41408 */ "GLDFF1W_D_IMM\0" + /* 41422 */ "LDNF1W_D_IMM\0" + /* 41435 */ "SST1W_D_IMM\0" + /* 41447 */ "LD1RW_D_IMM\0" + /* 41459 */ "GLD1SW_D_IMM\0" + /* 41472 */ "GLDFF1SW_D_IMM\0" + /* 41487 */ "LDNF1SW_D_IMM\0" + /* 41501 */ "LD1H_IMM\0" + /* 41510 */ "LDNF1H_IMM\0" + /* 41521 */ "ST1H_IMM\0" + /* 41530 */ "LD2H_IMM\0" + /* 41539 */ "ST2H_IMM\0" + /* 41548 */ "LD3H_IMM\0" + /* 41557 */ "ST3H_IMM\0" + /* 41566 */ "LD4H_IMM\0" + /* 41575 */ "ST4H_IMM\0" + /* 41584 */ "LD1RH_IMM\0" + /* 41594 */ "LD1B_H_IMM\0" + /* 41605 */ "LDNF1B_H_IMM\0" + /* 41618 */ "ST1B_H_IMM\0" + /* 41629 */ "LD1RB_H_IMM\0" + /* 41641 */ "LD1SB_H_IMM\0" + /* 41653 */ "LDNF1SB_H_IMM\0" + /* 41667 */ "LD1RSB_H_IMM\0" + /* 41680 */ "LD1RO_H_IMM\0" + /* 41692 */ "LD1RQ_H_IMM\0" + /* 41704 */ "GLD1B_S_IMM\0" + /* 41716 */ "GLDFF1B_S_IMM\0" + /* 41730 */ "LDNF1B_S_IMM\0" + /* 41743 */ "SST1B_S_IMM\0" + /* 41755 */ "LD1RB_S_IMM\0" + /* 41767 */ "GLD1SB_S_IMM\0" + /* 41780 */ "GLDFF1SB_S_IMM\0" + /* 41795 */ "LDNF1SB_S_IMM\0" + /* 41809 */ "LD1RSB_S_IMM\0" + /* 41822 */ "GLD1H_S_IMM\0" + /* 41834 */ "GLDFF1H_S_IMM\0" + /* 41848 */ "LDNF1H_S_IMM\0" + /* 41861 */ "SST1H_S_IMM\0" + /* 41873 */ "LD1RH_S_IMM\0" + /* 41885 */ "GLD1SH_S_IMM\0" + /* 41898 */ "GLDFF1SH_S_IMM\0" + /* 41913 */ "LDNF1SH_S_IMM\0" + /* 41927 */ "LD1RSH_S_IMM\0" + /* 41940 */ "GLD1W_IMM\0" + /* 41950 */ "GLDFF1W_IMM\0" + /* 41962 */ "LDNF1W_IMM\0" + /* 41973 */ "SST1W_IMM\0" + /* 41983 */ "LD2W_IMM\0" + /* 41992 */ "ST2W_IMM\0" + /* 42001 */ "LD3W_IMM\0" + /* 42010 */ "ST3W_IMM\0" + /* 42019 */ "LD4W_IMM\0" + /* 42028 */ "ST4W_IMM\0" + /* 42037 */ "LD1RW_IMM\0" + /* 42047 */ "LD1RSW_IMM\0" + /* 42058 */ "LD1RO_W_IMM\0" + /* 42070 */ "LD1RQ_W_IMM\0" + /* 42082 */ "INLINEASM\0" + /* 42092 */ "G_FMINIMUM\0" + /* 42103 */ "G_FMAXIMUM\0" + /* 42114 */ "G_FMINNUM\0" + /* 42124 */ "G_FMAXNUM\0" + /* 42134 */ "ZERO_M\0" + /* 42141 */ "G_INTRINSIC_ROUNDEVEN\0" + /* 42163 */ "G_FCOPYSIGN\0" + /* 42175 */ "G_VECREDUCE_FMIN\0" + /* 42192 */ "G_VECREDUCE_SMIN\0" + /* 42209 */ "G_SMIN\0" + /* 42216 */ "G_VECREDUCE_UMIN\0" + /* 42233 */ "G_UMIN\0" + /* 42240 */ "G_ATOMICRMW_UMIN\0" + /* 42257 */ "G_ATOMICRMW_MIN\0" + /* 42273 */ "G_FSIN\0" + /* 42280 */ "CFI_INSTRUCTION\0" + /* 42296 */ "BFCVTN\0" + /* 42303 */ "ADJCALLSTACKDOWN\0" + /* 42320 */ "G_SSUBO\0" + /* 42328 */ "G_USUBO\0" + /* 42336 */ "G_SADDO\0" + /* 42344 */ "G_UADDO\0" + /* 42352 */ "G_SMULO\0" + /* 42360 */ "G_UMULO\0" + /* 42368 */ "G_BZERO\0" + /* 42376 */ "STACKMAP\0" + /* 42385 */ "G_BSWAP\0" + /* 42393 */ "SUBP\0" + /* 42398 */ "MOVaddrCP\0" + /* 42408 */ "G_SITOFP\0" + /* 42417 */ "G_UITOFP\0" + /* 42426 */ "SEH_AddFP\0" + /* 42436 */ "SEH_SetFP\0" + /* 42446 */ "BLRNoIP\0" + /* 42454 */ "G_FCMP\0" + /* 42461 */ "G_ICMP\0" + /* 42468 */ "G_CTPOP\0" + /* 42476 */ "PATCHABLE_OP\0" + /* 42489 */ "FAULTING_OP\0" + /* 42501 */ "SEL_PPPP\0" + /* 42510 */ "PUNPKHI_PP\0" + /* 42521 */ "PUNPKLO_PP\0" + /* 42532 */ "PTEST_PP\0" + /* 42541 */ "BRKPA_PPzPP\0" + /* 42553 */ "BRKPB_PPzPP\0" + /* 42565 */ "BIC_PPzPP\0" + /* 42575 */ "NAND_PPzPP\0" + /* 42586 */ "ORN_PPzPP\0" + /* 42596 */ "EOR_PPzPP\0" + /* 42606 */ "NOR_PPzPP\0" + /* 42616 */ "ORR_PPzPP\0" + /* 42626 */ "BRKPAS_PPzPP\0" + /* 42639 */ "BRKPBS_PPzPP\0" + /* 42652 */ "BICS_PPzPP\0" + /* 42663 */ "NANDS_PPzPP\0" + /* 42675 */ "ORNS_PPzPP\0" + /* 42686 */ "EORS_PPzPP\0" + /* 42697 */ "NORS_PPzPP\0" + /* 42708 */ "ORRS_PPzPP\0" + /* 42719 */ "ADRP\0" + /* 42724 */ "PACIASP\0" + /* 42732 */ "AUTIASP\0" + /* 42740 */ "PACIBSP\0" + /* 42748 */ "AUTIBSP\0" + /* 42756 */ "G_DUP\0" + /* 42762 */ "ADJCALLSTACKUP\0" + /* 42777 */ "PREALLOCATED_SETUP\0" + /* 42796 */ "G_FEXP\0" + /* 42803 */ "RDFFR_P\0" + /* 42811 */ "SEH_SaveFRegP\0" + /* 42825 */ "SEH_SaveRegP\0" + /* 42838 */ "BRKA_PPmP\0" + /* 42848 */ "BRKB_PPmP\0" + /* 42858 */ "BRKA_PPzP\0" + /* 42868 */ "BRKB_PPzP\0" + /* 42878 */ "BRKN_PPzP\0" + /* 42888 */ "BRKAS_PPzP\0" + /* 42899 */ "BRKBS_PPzP\0" + /* 42910 */ "BRKNS_PPzP\0" + /* 42921 */ "G_FCMEQ\0" + /* 42929 */ "TLSDESC_CALLSEQ\0" + /* 42945 */ "EXTRACT_ZPMXI_H_Q\0" + /* 42963 */ "LD1_MXIPXX_H_Q\0" + /* 42978 */ "ST1_MXIPXX_H_Q\0" + /* 42993 */ "INSERT_MXIPZ_H_Q\0" + /* 43010 */ "DUP_ZZI_Q\0" + /* 43020 */ "EXTRACT_ZPMXI_V_Q\0" + /* 43038 */ "LD1_MXIPXX_V_Q\0" + /* 43053 */ "ST1_MXIPXX_V_Q\0" + /* 43068 */ "INSERT_MXIPZ_V_Q\0" + /* 43085 */ "TRN1_ZZZ_Q\0" + /* 43096 */ "ZIP1_ZZZ_Q\0" + /* 43107 */ "UZP1_ZZZ_Q\0" + /* 43118 */ "TRN2_ZZZ_Q\0" + /* 43129 */ "ZIP2_ZZZ_Q\0" + /* 43140 */ "UZP2_ZZZ_Q\0" + /* 43151 */ "PMULLB_ZZZ_Q\0" + /* 43164 */ "PMULLT_ZZZ_Q\0" + /* 43177 */ "XAR\0" + /* 43181 */ "G_BR\0" + /* 43186 */ "INLINEASM_BR\0" + /* 43199 */ "ADR\0" + /* 43203 */ "G_BLOCK_ADDR\0" + /* 43216 */ "BLR_RVMARKER\0" + /* 43229 */ "PATCHABLE_FUNCTION_ENTER\0" + /* 43254 */ "G_READCYCLECOUNTER\0" + /* 43273 */ "G_READ_REGISTER\0" + /* 43289 */ "G_WRITE_REGISTER\0" + /* 43306 */ "WRFFR\0" + /* 43312 */ "SETFFR\0" + /* 43319 */ "G_VASHR\0" + /* 43327 */ "G_ASHR\0" + /* 43334 */ "G_FSHR\0" + /* 43341 */ "G_VLSHR\0" + /* 43349 */ "G_LSHR\0" + /* 43356 */ "BLR\0" + /* 43360 */ "SEH_SaveFPLR\0" + /* 43373 */ "RET_ReallyLR\0" + /* 43386 */ "G_FFLOOR\0" + /* 43395 */ "G_BUILD_VECTOR\0" + /* 43410 */ "G_SHUFFLE_VECTOR\0" + /* 43427 */ "G_VECREDUCE_XOR\0" + /* 43443 */ "G_XOR\0" + /* 43449 */ "G_ATOMICRMW_XOR\0" + /* 43465 */ "G_VECREDUCE_OR\0" + /* 43480 */ "G_OR\0" + /* 43485 */ "G_ATOMICRMW_OR\0" + /* 43500 */ "PRFB_PRR\0" + /* 43509 */ "PRFD_PRR\0" + /* 43518 */ "PRFH_PRR\0" + /* 43527 */ "PRFS_PRR\0" + /* 43536 */ "LDNT1B_ZRR\0" + /* 43547 */ "STNT1B_ZRR\0" + /* 43558 */ "LDNT1D_ZRR\0" + /* 43569 */ "STNT1D_ZRR\0" + /* 43580 */ "LDNT1H_ZRR\0" + /* 43591 */ "STNT1H_ZRR\0" + /* 43602 */ "LDNT1W_ZRR\0" + /* 43613 */ "STNT1W_ZRR\0" + /* 43624 */ "MSR\0" + /* 43628 */ "G_ROTR\0" + /* 43635 */ "G_INTTOPTR\0" + /* 43646 */ "G_FABS\0" + /* 43653 */ "G_ABS\0" + /* 43659 */ "HWASAN_CHECK_MEMACCESS_SHORTGRANULES\0" + /* 43696 */ "G_UNMERGE_VALUES\0" + /* 43713 */ "G_MERGE_VALUES\0" + /* 43728 */ "MOVbaseTLS\0" + /* 43739 */ "MOVaddrTLS\0" + /* 43750 */ "ADDlowTLS\0" + /* 43760 */ "G_FCOS\0" + /* 43767 */ "SUBPS\0" + /* 43773 */ "DRPS\0" + /* 43778 */ "MRS\0" + /* 43782 */ "G_CONCAT_VECTORS\0" + /* 43799 */ "COPY_TO_REGCLASS\0" + /* 43816 */ "HWASAN_CHECK_MEMACCESS\0" + /* 43839 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" + /* 43869 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" + /* 43896 */ "DSBnXS\0" + /* 43903 */ "FJCVTZS\0" + /* 43911 */ "FCMGE_PPzZ0_S\0" + /* 43925 */ "FCMLE_PPzZ0_S\0" + /* 43939 */ "FCMNE_PPzZ0_S\0" + /* 43953 */ "FCMEQ_PPzZ0_S\0" + /* 43967 */ "FCMGT_PPzZ0_S\0" + /* 43981 */ "FCMLT_PPzZ0_S\0" + /* 43995 */ "LD1B_S\0" + /* 44002 */ "LDFF1B_S\0" + /* 44011 */ "ST1B_S\0" + /* 44018 */ "LD1SB_S\0" + /* 44026 */ "LDFF1SB_S\0" + /* 44036 */ "PTRUE_S\0" + /* 44044 */ "FSUB_ZPZI_UNDEF_S\0" + /* 44062 */ "FADD_ZPZI_UNDEF_S\0" + /* 44080 */ "LSL_ZPZI_UNDEF_S\0" + /* 44097 */ "FMUL_ZPZI_UNDEF_S\0" + /* 44115 */ "FMINNM_ZPZI_UNDEF_S\0" + /* 44135 */ "FMAXNM_ZPZI_UNDEF_S\0" + /* 44155 */ "FMIN_ZPZI_UNDEF_S\0" + /* 44173 */ "FSUBR_ZPZI_UNDEF_S\0" + /* 44192 */ "ASR_ZPZI_UNDEF_S\0" + /* 44209 */ "LSR_ZPZI_UNDEF_S\0" + /* 44226 */ "FMAX_ZPZI_UNDEF_S\0" + /* 44244 */ "FSUB_ZPZZ_UNDEF_S\0" + /* 44262 */ "FADD_ZPZZ_UNDEF_S\0" + /* 44280 */ "SMULH_ZPZZ_UNDEF_S\0" + /* 44299 */ "UMULH_ZPZZ_UNDEF_S\0" + /* 44318 */ "SQSHL_ZPZZ_UNDEF_S\0" + /* 44337 */ "UQSHL_ZPZZ_UNDEF_S\0" + /* 44356 */ "SQRSHL_ZPZZ_UNDEF_S\0" + /* 44376 */ "UQRSHL_ZPZZ_UNDEF_S\0" + /* 44396 */ "SRSHL_ZPZZ_UNDEF_S\0" + /* 44415 */ "URSHL_ZPZZ_UNDEF_S\0" + /* 44434 */ "LSL_ZPZZ_UNDEF_S\0" + /* 44451 */ "FMUL_ZPZZ_UNDEF_S\0" + /* 44469 */ "FMINNM_ZPZZ_UNDEF_S\0" + /* 44489 */ "FMAXNM_ZPZZ_UNDEF_S\0" + /* 44509 */ "FMIN_ZPZZ_UNDEF_S\0" + /* 44527 */ "SMIN_ZPZZ_UNDEF_S\0" + /* 44545 */ "UMIN_ZPZZ_UNDEF_S\0" + /* 44563 */ "ASR_ZPZZ_UNDEF_S\0" + /* 44580 */ "LSR_ZPZZ_UNDEF_S\0" + /* 44597 */ "FDIV_ZPZZ_UNDEF_S\0" + /* 44615 */ "SDIV_ZPZZ_UNDEF_S\0" + /* 44633 */ "UDIV_ZPZZ_UNDEF_S\0" + /* 44651 */ "FMAX_ZPZZ_UNDEF_S\0" + /* 44669 */ "SMAX_ZPZZ_UNDEF_S\0" + /* 44687 */ "UMAX_ZPZZ_UNDEF_S\0" + /* 44705 */ "FMLA_ZPZZZ_UNDEF_S\0" + /* 44724 */ "FNMLA_ZPZZZ_UNDEF_S\0" + /* 44744 */ "FMLS_ZPZZZ_UNDEF_S\0" + /* 44763 */ "FNMLS_ZPZZZ_UNDEF_S\0" + /* 44783 */ "FRINTA_ZPmZ_UNDEF_S\0" + /* 44803 */ "SXTB_ZPmZ_UNDEF_S\0" + /* 44821 */ "UXTB_ZPmZ_UNDEF_S\0" + /* 44839 */ "URECPE_ZPmZ_UNDEF_S\0" + /* 44859 */ "URSQRTE_ZPmZ_UNDEF_S\0" + /* 44880 */ "FNEG_ZPmZ_UNDEF_S\0" + /* 44898 */ "SQNEG_ZPmZ_UNDEF_S\0" + /* 44917 */ "SXTH_ZPmZ_UNDEF_S\0" + /* 44935 */ "UXTH_ZPmZ_UNDEF_S\0" + /* 44953 */ "FRINTI_ZPmZ_UNDEF_S\0" + /* 44973 */ "FRINTM_ZPmZ_UNDEF_S\0" + /* 44993 */ "FRINTN_ZPmZ_UNDEF_S\0" + /* 45013 */ "FRINTP_ZPmZ_UNDEF_S\0" + /* 45033 */ "FABS_ZPmZ_UNDEF_S\0" + /* 45051 */ "SQABS_ZPmZ_UNDEF_S\0" + /* 45070 */ "CLS_ZPmZ_UNDEF_S\0" + /* 45087 */ "CNT_ZPmZ_UNDEF_S\0" + /* 45104 */ "CNOT_ZPmZ_UNDEF_S\0" + /* 45122 */ "FSQRT_ZPmZ_UNDEF_S\0" + /* 45141 */ "FRECPX_ZPmZ_UNDEF_S\0" + /* 45161 */ "FRINTX_ZPmZ_UNDEF_S\0" + /* 45181 */ "CLZ_ZPmZ_UNDEF_S\0" + /* 45198 */ "FRINTZ_ZPmZ_UNDEF_S\0" + /* 45218 */ "LD1H_S\0" + /* 45225 */ "LDFF1H_S\0" + /* 45234 */ "ST1H_S\0" + /* 45241 */ "LD1SH_S\0" + /* 45249 */ "LDFF1SH_S\0" + /* 45259 */ "EXTRACT_ZPMXI_H_S\0" + /* 45277 */ "LD1_MXIPXX_H_S\0" + /* 45292 */ "ST1_MXIPXX_H_S\0" + /* 45307 */ "INSERT_MXIPZ_H_S\0" + /* 45324 */ "INDEX_II_S\0" + /* 45335 */ "PSEL_PPPRI_S\0" + /* 45348 */ "INDEX_RI_S\0" + /* 45359 */ "FCMLA_ZZZI_S\0" + /* 45372 */ "FMLA_ZZZI_S\0" + /* 45384 */ "SQDMLALB_ZZZI_S\0" + /* 45400 */ "SMLALB_ZZZI_S\0" + /* 45414 */ "UMLALB_ZZZI_S\0" + /* 45428 */ "SQDMULLB_ZZZI_S\0" + /* 45444 */ "SMULLB_ZZZI_S\0" + /* 45458 */ "UMULLB_ZZZI_S\0" + /* 45472 */ "SQDMLSLB_ZZZI_S\0" + /* 45488 */ "SMLSLB_ZZZI_S\0" + /* 45502 */ "UMLSLB_ZZZI_S\0" + /* 45516 */ "SQRDCMLAH_ZZZI_S\0" + /* 45533 */ "SQRDMLAH_ZZZI_S\0" + /* 45549 */ "SQDMULH_ZZZI_S\0" + /* 45564 */ "SQRDMULH_ZZZI_S\0" + /* 45580 */ "SQRDMLSH_ZZZI_S\0" + /* 45596 */ "FMUL_ZZZI_S\0" + /* 45608 */ "XAR_ZZZI_S\0" + /* 45619 */ "FMLS_ZZZI_S\0" + /* 45631 */ "SQDMLALT_ZZZI_S\0" + /* 45647 */ "SMLALT_ZZZI_S\0" + /* 45661 */ "UMLALT_ZZZI_S\0" + /* 45675 */ "SQDMULLT_ZZZI_S\0" + /* 45691 */ "SMULLT_ZZZI_S\0" + /* 45705 */ "UMULLT_ZZZI_S\0" + /* 45719 */ "SQDMLSLT_ZZZI_S\0" + /* 45735 */ "SMLSLT_ZZZI_S\0" + /* 45749 */ "UMLSLT_ZZZI_S\0" + /* 45763 */ "CDOT_ZZZI_S\0" + /* 45775 */ "SDOT_ZZZI_S\0" + /* 45787 */ "UDOT_ZZZI_S\0" + /* 45799 */ "SRSRA_ZZI_S\0" + /* 45811 */ "URSRA_ZZI_S\0" + /* 45823 */ "SSRA_ZZI_S\0" + /* 45834 */ "USRA_ZZI_S\0" + /* 45845 */ "SSHLLB_ZZI_S\0" + /* 45858 */ "USHLLB_ZZI_S\0" + /* 45871 */ "SQSHRNB_ZZI_S\0" + /* 45885 */ "UQSHRNB_ZZI_S\0" + /* 45899 */ "SQRSHRNB_ZZI_S\0" + /* 45914 */ "UQRSHRNB_ZZI_S\0" + /* 45929 */ "SQSHRUNB_ZZI_S\0" + /* 45944 */ "SQRSHRUNB_ZZI_S\0" + /* 45960 */ "FTMAD_ZZI_S\0" + /* 45972 */ "SQCADD_ZZI_S\0" + /* 45985 */ "SLI_ZZI_S\0" + /* 45995 */ "SRI_ZZI_S\0" + /* 46005 */ "LSL_ZZI_S\0" + /* 46015 */ "DUP_ZZI_S\0" + /* 46025 */ "ASR_ZZI_S\0" + /* 46035 */ "LSR_ZZI_S\0" + /* 46045 */ "SSHLLT_ZZI_S\0" + /* 46058 */ "USHLLT_ZZI_S\0" + /* 46071 */ "SQSHRNT_ZZI_S\0" + /* 46085 */ "UQSHRNT_ZZI_S\0" + /* 46099 */ "SQRSHRNT_ZZI_S\0" + /* 46114 */ "UQRSHRNT_ZZI_S\0" + /* 46129 */ "SQSHRUNT_ZZI_S\0" + /* 46144 */ "SQRSHRUNT_ZZI_S\0" + /* 46160 */ "SQSUB_ZI_S\0" + /* 46171 */ "UQSUB_ZI_S\0" + /* 46182 */ "SQADD_ZI_S\0" + /* 46193 */ "UQADD_ZI_S\0" + /* 46204 */ "MUL_ZI_S\0" + /* 46213 */ "SMIN_ZI_S\0" + /* 46223 */ "UMIN_ZI_S\0" + /* 46233 */ "FDUP_ZI_S\0" + /* 46243 */ "SUBR_ZI_S\0" + /* 46253 */ "SMAX_ZI_S\0" + /* 46263 */ "UMAX_ZI_S\0" + /* 46273 */ "CMPGE_PPzZI_S\0" + /* 46287 */ "CMPLE_PPzZI_S\0" + /* 46301 */ "CMPNE_PPzZI_S\0" + /* 46315 */ "CMPHI_PPzZI_S\0" + /* 46329 */ "CMPLO_PPzZI_S\0" + /* 46343 */ "CMPEQ_PPzZI_S\0" + /* 46357 */ "CMPHS_PPzZI_S\0" + /* 46371 */ "CMPLS_PPzZI_S\0" + /* 46385 */ "CMPGT_PPzZI_S\0" + /* 46399 */ "CMPLT_PPzZI_S\0" + /* 46413 */ "FSUB_ZPmI_S\0" + /* 46425 */ "FADD_ZPmI_S\0" + /* 46437 */ "ASRD_ZPmI_S\0" + /* 46449 */ "SQSHL_ZPmI_S\0" + /* 46462 */ "UQSHL_ZPmI_S\0" + /* 46475 */ "LSL_ZPmI_S\0" + /* 46486 */ "FMUL_ZPmI_S\0" + /* 46498 */ "FMINNM_ZPmI_S\0" + /* 46512 */ "FMAXNM_ZPmI_S\0" + /* 46526 */ "FMIN_ZPmI_S\0" + /* 46538 */ "FSUBR_ZPmI_S\0" + /* 46551 */ "SRSHR_ZPmI_S\0" + /* 46564 */ "URSHR_ZPmI_S\0" + /* 46577 */ "ASR_ZPmI_S\0" + /* 46588 */ "LSR_ZPmI_S\0" + /* 46599 */ "SQSHLU_ZPmI_S\0" + /* 46613 */ "FMAX_ZPmI_S\0" + /* 46625 */ "FCPY_ZPmI_S\0" + /* 46637 */ "CPY_ZPzI_S\0" + /* 46648 */ "FSUB_ZPZI_ZERO_S\0" + /* 46665 */ "FADD_ZPZI_ZERO_S\0" + /* 46682 */ "ASRD_ZPZI_ZERO_S\0" + /* 46699 */ "SQSHL_ZPZI_ZERO_S\0" + /* 46717 */ "UQSHL_ZPZI_ZERO_S\0" + /* 46735 */ "FMUL_ZPZI_ZERO_S\0" + /* 46752 */ "FMINNM_ZPZI_ZERO_S\0" + /* 46771 */ "FMAXNM_ZPZI_ZERO_S\0" + /* 46790 */ "FMIN_ZPZI_ZERO_S\0" + /* 46807 */ "FSUBR_ZPZI_ZERO_S\0" + /* 46825 */ "SRSHR_ZPZI_ZERO_S\0" + /* 46843 */ "URSHR_ZPZI_ZERO_S\0" + /* 46861 */ "SQSHLU_ZPZI_ZERO_S\0" + /* 46880 */ "FMAX_ZPZI_ZERO_S\0" + /* 46897 */ "FSUB_ZPZZ_ZERO_S\0" + /* 46914 */ "FABD_ZPZZ_ZERO_S\0" + /* 46931 */ "FADD_ZPZZ_ZERO_S\0" + /* 46948 */ "LSL_ZPZZ_ZERO_S\0" + /* 46964 */ "FMUL_ZPZZ_ZERO_S\0" + /* 46981 */ "FMINNM_ZPZZ_ZERO_S\0" + /* 47000 */ "FMAXNM_ZPZZ_ZERO_S\0" + /* 47019 */ "FMIN_ZPZZ_ZERO_S\0" + /* 47036 */ "FSUBR_ZPZZ_ZERO_S\0" + /* 47054 */ "ASR_ZPZZ_ZERO_S\0" + /* 47070 */ "LSR_ZPZZ_ZERO_S\0" + /* 47086 */ "FDIVR_ZPZZ_ZERO_S\0" + /* 47104 */ "FDIV_ZPZZ_ZERO_S\0" + /* 47121 */ "FMAX_ZPZZ_ZERO_S\0" + /* 47138 */ "FMULX_ZPZZ_ZERO_S\0" + /* 47156 */ "TRN1_PPP_S\0" + /* 47167 */ "ZIP1_PPP_S\0" + /* 47178 */ "UZP1_PPP_S\0" + /* 47189 */ "TRN2_PPP_S\0" + /* 47200 */ "ZIP2_PPP_S\0" + /* 47211 */ "UZP2_PPP_S\0" + /* 47222 */ "CNTP_XPP_S\0" + /* 47233 */ "REV_PP_S\0" + /* 47242 */ "UQDECP_WP_S\0" + /* 47254 */ "UQINCP_WP_S\0" + /* 47266 */ "SQDECP_XP_S\0" + /* 47278 */ "UQDECP_XP_S\0" + /* 47290 */ "SQINCP_XP_S\0" + /* 47302 */ "UQINCP_XP_S\0" + /* 47314 */ "SQDECP_ZP_S\0" + /* 47326 */ "UQDECP_ZP_S\0" + /* 47338 */ "SQINCP_ZP_S\0" + /* 47350 */ "UQINCP_ZP_S\0" + /* 47362 */ "INDEX_IR_S\0" + /* 47373 */ "INDEX_RR_S\0" + /* 47384 */ "DUP_ZR_S\0" + /* 47393 */ "INSR_ZR_S\0" + /* 47403 */ "CPY_ZPmR_S\0" + /* 47414 */ "PTRUES_S\0" + /* 47423 */ "PNEXT_S\0" + /* 47431 */ "INSR_ZV_S\0" + /* 47441 */ "EXTRACT_ZPMXI_V_S\0" + /* 47459 */ "LD1_MXIPXX_V_S\0" + /* 47474 */ "ST1_MXIPXX_V_S\0" + /* 47489 */ "INSERT_MXIPZ_V_S\0" + /* 47506 */ "CPY_ZPmV_S\0" + /* 47517 */ "WHILEGE_PWW_S\0" + /* 47531 */ "WHILELE_PWW_S\0" + /* 47545 */ "WHILEHI_PWW_S\0" + /* 47559 */ "WHILELO_PWW_S\0" + /* 47573 */ "WHILEHS_PWW_S\0" + /* 47587 */ "WHILELS_PWW_S\0" + /* 47601 */ "WHILEGT_PWW_S\0" + /* 47615 */ "WHILELT_PWW_S\0" + /* 47629 */ "WHILEGE_PXX_S\0" + /* 47643 */ "WHILELE_PXX_S\0" + /* 47657 */ "WHILEHI_PXX_S\0" + /* 47671 */ "WHILELO_PXX_S\0" + /* 47685 */ "WHILEWR_PXX_S\0" + /* 47699 */ "WHILEHS_PXX_S\0" + /* 47713 */ "WHILELS_PXX_S\0" + /* 47727 */ "WHILEGT_PXX_S\0" + /* 47741 */ "WHILELT_PXX_S\0" + /* 47755 */ "WHILERW_PXX_S\0" + /* 47769 */ "ADDHA_MPPZ_S\0" + /* 47782 */ "ADDVA_MPPZ_S\0" + /* 47795 */ "CLASTA_RPZ_S\0" + /* 47808 */ "CLASTB_RPZ_S\0" + /* 47821 */ "FADDA_VPZ_S\0" + /* 47833 */ "CLASTA_VPZ_S\0" + /* 47846 */ "CLASTB_VPZ_S\0" + /* 47859 */ "FADDV_VPZ_S\0" + /* 47871 */ "SADDV_VPZ_S\0" + /* 47883 */ "UADDV_VPZ_S\0" + /* 47895 */ "ANDV_VPZ_S\0" + /* 47906 */ "FMINNMV_VPZ_S\0" + /* 47920 */ "FMAXNMV_VPZ_S\0" + /* 47934 */ "FMINV_VPZ_S\0" + /* 47946 */ "SMINV_VPZ_S\0" + /* 47958 */ "UMINV_VPZ_S\0" + /* 47970 */ "EORV_VPZ_S\0" + /* 47981 */ "FMAXV_VPZ_S\0" + /* 47993 */ "SMAXV_VPZ_S\0" + /* 48005 */ "UMAXV_VPZ_S\0" + /* 48017 */ "CLASTA_ZPZ_S\0" + /* 48030 */ "CLASTB_ZPZ_S\0" + /* 48043 */ "SPLICE_ZPZ_S\0" + /* 48056 */ "COMPACT_ZPZ_S\0" + /* 48070 */ "FMOPA_MPPZZ_S\0" + /* 48084 */ "USMOPA_MPPZZ_S\0" + /* 48099 */ "SUMOPA_MPPZZ_S\0" + /* 48114 */ "FMOPS_MPPZZ_S\0" + /* 48128 */ "USMOPS_MPPZZ_S\0" + /* 48143 */ "SUMOPS_MPPZZ_S\0" + /* 48158 */ "SPLICE_ZPZZ_S\0" + /* 48172 */ "SEL_ZPZZ_S\0" + /* 48183 */ "TBL_ZZZZ_S\0" + /* 48194 */ "TRN1_ZZZ_S\0" + /* 48205 */ "ZIP1_ZZZ_S\0" + /* 48216 */ "UZP1_ZZZ_S\0" + /* 48227 */ "TRN2_ZZZ_S\0" + /* 48238 */ "ZIP2_ZZZ_S\0" + /* 48249 */ "UZP2_ZZZ_S\0" + /* 48260 */ "SABA_ZZZ_S\0" + /* 48271 */ "UABA_ZZZ_S\0" + /* 48282 */ "CMLA_ZZZ_S\0" + /* 48293 */ "FMMLA_ZZZ_S\0" + /* 48305 */ "SABALB_ZZZ_S\0" + /* 48318 */ "UABALB_ZZZ_S\0" + /* 48331 */ "SQDMLALB_ZZZ_S\0" + /* 48346 */ "SMLALB_ZZZ_S\0" + /* 48359 */ "UMLALB_ZZZ_S\0" + /* 48372 */ "SSUBLB_ZZZ_S\0" + /* 48385 */ "USUBLB_ZZZ_S\0" + /* 48398 */ "SBCLB_ZZZ_S\0" + /* 48410 */ "ADCLB_ZZZ_S\0" + /* 48422 */ "SABDLB_ZZZ_S\0" + /* 48435 */ "UABDLB_ZZZ_S\0" + /* 48448 */ "SADDLB_ZZZ_S\0" + /* 48461 */ "UADDLB_ZZZ_S\0" + /* 48474 */ "SQDMULLB_ZZZ_S\0" + /* 48489 */ "SMULLB_ZZZ_S\0" + /* 48502 */ "UMULLB_ZZZ_S\0" + /* 48515 */ "SQDMLSLB_ZZZ_S\0" + /* 48530 */ "SMLSLB_ZZZ_S\0" + /* 48543 */ "UMLSLB_ZZZ_S\0" + /* 48556 */ "RSUBHNB_ZZZ_S\0" + /* 48570 */ "RADDHNB_ZZZ_S\0" + /* 48584 */ "SSUBLTB_ZZZ_S\0" + /* 48598 */ "EORTB_ZZZ_S\0" + /* 48610 */ "FSUB_ZZZ_S\0" + /* 48621 */ "SQSUB_ZZZ_S\0" + /* 48633 */ "UQSUB_ZZZ_S\0" + /* 48645 */ "SSUBWB_ZZZ_S\0" + /* 48658 */ "USUBWB_ZZZ_S\0" + /* 48671 */ "SADDWB_ZZZ_S\0" + /* 48684 */ "UADDWB_ZZZ_S\0" + /* 48697 */ "FADD_ZZZ_S\0" + /* 48708 */ "SQADD_ZZZ_S\0" + /* 48720 */ "UQADD_ZZZ_S\0" + /* 48732 */ "SM4E_ZZZ_S\0" + /* 48743 */ "LSL_WIDE_ZZZ_S\0" + /* 48758 */ "ASR_WIDE_ZZZ_S\0" + /* 48773 */ "LSR_WIDE_ZZZ_S\0" + /* 48788 */ "SQRDCMLAH_ZZZ_S\0" + /* 48804 */ "SQRDMLAH_ZZZ_S\0" + /* 48819 */ "SQDMULH_ZZZ_S\0" + /* 48833 */ "SQRDMULH_ZZZ_S\0" + /* 48848 */ "SMULH_ZZZ_S\0" + /* 48860 */ "UMULH_ZZZ_S\0" + /* 48872 */ "SQRDMLSH_ZZZ_S\0" + /* 48887 */ "TBL_ZZZ_S\0" + /* 48897 */ "FTSSEL_ZZZ_S\0" + /* 48910 */ "FMUL_ZZZ_S\0" + /* 48921 */ "FTSMUL_ZZZ_S\0" + /* 48934 */ "BDEP_ZZZ_S\0" + /* 48945 */ "SCLAMP_ZZZ_S\0" + /* 48958 */ "UCLAMP_ZZZ_S\0" + /* 48971 */ "BGRP_ZZZ_S\0" + /* 48982 */ "FRECPS_ZZZ_S\0" + /* 48995 */ "FRSQRTS_ZZZ_S\0" + /* 49009 */ "SQDMLALBT_ZZZ_S\0" + /* 49025 */ "SSUBLBT_ZZZ_S\0" + /* 49039 */ "SADDLBT_ZZZ_S\0" + /* 49053 */ "SQDMLSLBT_ZZZ_S\0" + /* 49069 */ "EORBT_ZZZ_S\0" + /* 49081 */ "SABALT_ZZZ_S\0" + /* 49094 */ "UABALT_ZZZ_S\0" + /* 49107 */ "SQDMLALT_ZZZ_S\0" + /* 49122 */ "SMLALT_ZZZ_S\0" + /* 49135 */ "UMLALT_ZZZ_S\0" + /* 49148 */ "SSUBLT_ZZZ_S\0" + /* 49161 */ "USUBLT_ZZZ_S\0" + /* 49174 */ "SBCLT_ZZZ_S\0" + /* 49186 */ "ADCLT_ZZZ_S\0" + /* 49198 */ "SABDLT_ZZZ_S\0" + /* 49211 */ "UABDLT_ZZZ_S\0" + /* 49224 */ "SADDLT_ZZZ_S\0" + /* 49237 */ "UADDLT_ZZZ_S\0" + /* 49250 */ "SQDMULLT_ZZZ_S\0" + /* 49265 */ "SMULLT_ZZZ_S\0" + /* 49278 */ "UMULLT_ZZZ_S\0" + /* 49291 */ "SQDMLSLT_ZZZ_S\0" + /* 49306 */ "SMLSLT_ZZZ_S\0" + /* 49319 */ "UMLSLT_ZZZ_S\0" + /* 49332 */ "RSUBHNT_ZZZ_S\0" + /* 49346 */ "RADDHNT_ZZZ_S\0" + /* 49360 */ "CDOT_ZZZ_S\0" + /* 49371 */ "SDOT_ZZZ_S\0" + /* 49382 */ "UDOT_ZZZ_S\0" + /* 49393 */ "SSUBWT_ZZZ_S\0" + /* 49406 */ "USUBWT_ZZZ_S\0" + /* 49419 */ "SADDWT_ZZZ_S\0" + /* 49432 */ "UADDWT_ZZZ_S\0" + /* 49445 */ "BEXT_ZZZ_S\0" + /* 49456 */ "TBX_ZZZ_S\0" + /* 49466 */ "SM4EKEY_ZZZ_S\0" + /* 49480 */ "FEXPA_ZZ_S\0" + /* 49491 */ "SQXTNB_ZZ_S\0" + /* 49503 */ "UQXTNB_ZZ_S\0" + /* 49515 */ "SQXTUNB_ZZ_S\0" + /* 49528 */ "FRECPE_ZZ_S\0" + /* 49540 */ "FRSQRTE_ZZ_S\0" + /* 49553 */ "SUNPKHI_ZZ_S\0" + /* 49566 */ "UUNPKHI_ZZ_S\0" + /* 49579 */ "SUNPKLO_ZZ_S\0" + /* 49592 */ "UUNPKLO_ZZ_S\0" + /* 49605 */ "SQXTNT_ZZ_S\0" + /* 49617 */ "UQXTNT_ZZ_S\0" + /* 49629 */ "SQXTUNT_ZZ_S\0" + /* 49642 */ "REV_ZZ_S\0" + /* 49651 */ "FCMLA_ZPmZZ_S\0" + /* 49665 */ "FMLA_ZPmZZ_S\0" + /* 49678 */ "FNMLA_ZPmZZ_S\0" + /* 49692 */ "FMSB_ZPmZZ_S\0" + /* 49705 */ "FNMSB_ZPmZZ_S\0" + /* 49719 */ "FMAD_ZPmZZ_S\0" + /* 49732 */ "FNMAD_ZPmZZ_S\0" + /* 49746 */ "FADDP_ZPmZZ_S\0" + /* 49760 */ "FMINNMP_ZPmZZ_S\0" + /* 49776 */ "FMAXNMP_ZPmZZ_S\0" + /* 49792 */ "FMINP_ZPmZZ_S\0" + /* 49806 */ "FMAXP_ZPmZZ_S\0" + /* 49820 */ "FMLS_ZPmZZ_S\0" + /* 49833 */ "FNMLS_ZPmZZ_S\0" + /* 49847 */ "CMPGE_WIDE_PPzZZ_S\0" + /* 49866 */ "CMPLE_WIDE_PPzZZ_S\0" + /* 49885 */ "CMPNE_WIDE_PPzZZ_S\0" + /* 49904 */ "CMPHI_WIDE_PPzZZ_S\0" + /* 49923 */ "CMPLO_WIDE_PPzZZ_S\0" + /* 49942 */ "CMPEQ_WIDE_PPzZZ_S\0" + /* 49961 */ "CMPHS_WIDE_PPzZZ_S\0" + /* 49980 */ "CMPLS_WIDE_PPzZZ_S\0" + /* 49999 */ "CMPGT_WIDE_PPzZZ_S\0" + /* 50018 */ "CMPLT_WIDE_PPzZZ_S\0" + /* 50037 */ "FACGE_PPzZZ_S\0" + /* 50051 */ "FCMGE_PPzZZ_S\0" + /* 50065 */ "CMPGE_PPzZZ_S\0" + /* 50079 */ "FCMNE_PPzZZ_S\0" + /* 50093 */ "CMPNE_PPzZZ_S\0" + /* 50107 */ "CMPHI_PPzZZ_S\0" + /* 50121 */ "FCMUO_PPzZZ_S\0" + /* 50135 */ "FCMEQ_PPzZZ_S\0" + /* 50149 */ "CMPEQ_PPzZZ_S\0" + /* 50163 */ "CMPHS_PPzZZ_S\0" + /* 50177 */ "FACGT_PPzZZ_S\0" + /* 50191 */ "FCMGT_PPzZZ_S\0" + /* 50205 */ "CMPGT_PPzZZ_S\0" + /* 50219 */ "HISTCNT_ZPzZZ_S\0" + /* 50235 */ "FRINTA_ZPmZ_S\0" + /* 50249 */ "FLOGB_ZPmZ_S\0" + /* 50262 */ "SXTB_ZPmZ_S\0" + /* 50274 */ "UXTB_ZPmZ_S\0" + /* 50286 */ "FSUB_ZPmZ_S\0" + /* 50298 */ "SHSUB_ZPmZ_S\0" + /* 50311 */ "UHSUB_ZPmZ_S\0" + /* 50324 */ "SQSUB_ZPmZ_S\0" + /* 50337 */ "UQSUB_ZPmZ_S\0" + /* 50350 */ "REVB_ZPmZ_S\0" + /* 50362 */ "BIC_ZPmZ_S\0" + /* 50373 */ "FABD_ZPmZ_S\0" + /* 50385 */ "SABD_ZPmZ_S\0" + /* 50397 */ "UABD_ZPmZ_S\0" + /* 50409 */ "FCADD_ZPmZ_S\0" + /* 50422 */ "FADD_ZPmZ_S\0" + /* 50434 */ "SRHADD_ZPmZ_S\0" + /* 50448 */ "URHADD_ZPmZ_S\0" + /* 50462 */ "SHADD_ZPmZ_S\0" + /* 50475 */ "UHADD_ZPmZ_S\0" + /* 50488 */ "USQADD_ZPmZ_S\0" + /* 50502 */ "SUQADD_ZPmZ_S\0" + /* 50516 */ "AND_ZPmZ_S\0" + /* 50527 */ "LSL_WIDE_ZPmZ_S\0" + /* 50543 */ "ASR_WIDE_ZPmZ_S\0" + /* 50559 */ "LSR_WIDE_ZPmZ_S\0" + /* 50575 */ "FSCALE_ZPmZ_S\0" + /* 50589 */ "URECPE_ZPmZ_S\0" + /* 50603 */ "URSQRTE_ZPmZ_S\0" + /* 50618 */ "FNEG_ZPmZ_S\0" + /* 50630 */ "SQNEG_ZPmZ_S\0" + /* 50643 */ "SMULH_ZPmZ_S\0" + /* 50656 */ "UMULH_ZPmZ_S\0" + /* 50669 */ "SXTH_ZPmZ_S\0" + /* 50681 */ "UXTH_ZPmZ_S\0" + /* 50693 */ "REVH_ZPmZ_S\0" + /* 50705 */ "FRINTI_ZPmZ_S\0" + /* 50719 */ "SQSHL_ZPmZ_S\0" + /* 50732 */ "UQSHL_ZPmZ_S\0" + /* 50745 */ "SQRSHL_ZPmZ_S\0" + /* 50759 */ "UQRSHL_ZPmZ_S\0" + /* 50773 */ "SRSHL_ZPmZ_S\0" + /* 50786 */ "URSHL_ZPmZ_S\0" + /* 50799 */ "LSL_ZPmZ_S\0" + /* 50810 */ "FMUL_ZPmZ_S\0" + /* 50822 */ "FMINNM_ZPmZ_S\0" + /* 50836 */ "FMAXNM_ZPmZ_S\0" + /* 50850 */ "FRINTM_ZPmZ_S\0" + /* 50864 */ "FMIN_ZPmZ_S\0" + /* 50876 */ "SMIN_ZPmZ_S\0" + /* 50888 */ "UMIN_ZPmZ_S\0" + /* 50900 */ "FRINTN_ZPmZ_S\0" + /* 50914 */ "ADDP_ZPmZ_S\0" + /* 50926 */ "SADALP_ZPmZ_S\0" + /* 50940 */ "UADALP_ZPmZ_S\0" + /* 50954 */ "SMINP_ZPmZ_S\0" + /* 50967 */ "UMINP_ZPmZ_S\0" + /* 50980 */ "FRINTP_ZPmZ_S\0" + /* 50994 */ "SMAXP_ZPmZ_S\0" + /* 51007 */ "UMAXP_ZPmZ_S\0" + /* 51020 */ "FSUBR_ZPmZ_S\0" + /* 51033 */ "SHSUBR_ZPmZ_S\0" + /* 51047 */ "UHSUBR_ZPmZ_S\0" + /* 51061 */ "SQSUBR_ZPmZ_S\0" + /* 51075 */ "UQSUBR_ZPmZ_S\0" + /* 51089 */ "SQSHLR_ZPmZ_S\0" + /* 51103 */ "UQSHLR_ZPmZ_S\0" + /* 51117 */ "SQRSHLR_ZPmZ_S\0" + /* 51132 */ "UQRSHLR_ZPmZ_S\0" + /* 51147 */ "SRSHLR_ZPmZ_S\0" + /* 51161 */ "URSHLR_ZPmZ_S\0" + /* 51175 */ "LSLR_ZPmZ_S\0" + /* 51187 */ "EOR_ZPmZ_S\0" + /* 51198 */ "ORR_ZPmZ_S\0" + /* 51209 */ "ASRR_ZPmZ_S\0" + /* 51221 */ "LSRR_ZPmZ_S\0" + /* 51233 */ "ASR_ZPmZ_S\0" + /* 51244 */ "LSR_ZPmZ_S\0" + /* 51255 */ "FDIVR_ZPmZ_S\0" + /* 51268 */ "SDIVR_ZPmZ_S\0" + /* 51281 */ "UDIVR_ZPmZ_S\0" + /* 51294 */ "FABS_ZPmZ_S\0" + /* 51306 */ "SQABS_ZPmZ_S\0" + /* 51319 */ "CLS_ZPmZ_S\0" + /* 51330 */ "RBIT_ZPmZ_S\0" + /* 51342 */ "CNT_ZPmZ_S\0" + /* 51353 */ "CNOT_ZPmZ_S\0" + /* 51365 */ "FSQRT_ZPmZ_S\0" + /* 51378 */ "FDIV_ZPmZ_S\0" + /* 51390 */ "SDIV_ZPmZ_S\0" + /* 51402 */ "UDIV_ZPmZ_S\0" + /* 51414 */ "FMAX_ZPmZ_S\0" + /* 51426 */ "SMAX_ZPmZ_S\0" + /* 51438 */ "UMAX_ZPmZ_S\0" + /* 51450 */ "MOVPRFX_ZPmZ_S\0" + /* 51465 */ "FMULX_ZPmZ_S\0" + /* 51478 */ "FRECPX_ZPmZ_S\0" + /* 51492 */ "FRINTX_ZPmZ_S\0" + /* 51506 */ "CLZ_ZPmZ_S\0" + /* 51517 */ "FRINTZ_ZPmZ_S\0" + /* 51531 */ "MOVPRFX_ZPzZ_S\0" + /* 51546 */ "SQDECP_XPWd_S\0" + /* 51560 */ "SQINCP_XPWd_S\0" + /* 51574 */ "SCVTF_ZPmZ_DtoS\0" + /* 51590 */ "UCVTF_ZPmZ_DtoS\0" + /* 51606 */ "FCVTZS_ZPmZ_DtoS\0" + /* 51623 */ "FCVTNT_ZPmZ_DtoS\0" + /* 51640 */ "FCVTXNT_ZPmZ_DtoS\0" + /* 51658 */ "FCVT_ZPmZ_DtoS\0" + /* 51673 */ "FCVTZU_ZPmZ_DtoS\0" + /* 51690 */ "FCVTX_ZPmZ_DtoS\0" + /* 51706 */ "FCVTZS_ZPmZ_HtoS\0" + /* 51723 */ "FCVTLT_ZPmZ_HtoS\0" + /* 51740 */ "FCVT_ZPmZ_HtoS\0" + /* 51755 */ "FCVTZU_ZPmZ_HtoS\0" + /* 51772 */ "SCVTF_ZPmZ_StoS\0" + /* 51788 */ "UCVTF_ZPmZ_StoS\0" + /* 51804 */ "FCVTZS_ZPmZ_StoS\0" + /* 51821 */ "FCVTZU_ZPmZ_StoS\0" + /* 51838 */ "G_SSUBSAT\0" + /* 51848 */ "G_USUBSAT\0" + /* 51858 */ "G_SADDSAT\0" + /* 51868 */ "G_UADDSAT\0" + /* 51878 */ "G_SSHLSAT\0" + /* 51888 */ "G_USHLSAT\0" + /* 51898 */ "G_SMULFIXSAT\0" + /* 51911 */ "G_UMULFIXSAT\0" + /* 51924 */ "G_SDIVFIXSAT\0" + /* 51937 */ "G_UDIVFIXSAT\0" + /* 51950 */ "G_EXTRACT\0" + /* 51960 */ "G_SELECT\0" + /* 51969 */ "G_BRINDIRECT\0" + /* 51982 */ "WFET\0" + /* 51987 */ "ERET\0" + /* 51992 */ "CATCHRET\0" + /* 52001 */ "CLEANUPRET\0" + /* 52012 */ "PATCHABLE_RET\0" + /* 52026 */ "G_MEMSET\0" + /* 52035 */ "G_FCMGT\0" + /* 52043 */ "WFIT\0" + /* 52048 */ "TCOMMIT\0" + /* 52056 */ "PATCHABLE_FUNCTION_EXIT\0" + /* 52080 */ "G_BRJT\0" + /* 52087 */ "MOVaddrJT\0" + /* 52097 */ "BFMLALT\0" + /* 52105 */ "G_EXTRACT_VECTOR_ELT\0" + /* 52126 */ "G_INSERT_VECTOR_ELT\0" + /* 52146 */ "HLT\0" + /* 52150 */ "G_FCONSTANT\0" + /* 52162 */ "G_CONSTANT\0" + /* 52173 */ "HINT\0" + /* 52178 */ "STATEPOINT\0" + /* 52189 */ "PATCHPOINT\0" + /* 52200 */ "G_PTRTOINT\0" + /* 52211 */ "G_FRINT\0" + /* 52219 */ "G_INTRINSIC_LRINT\0" + /* 52237 */ "G_FNEARBYINT\0" + /* 52250 */ "G_VASTART\0" + /* 52260 */ "TSTART\0" + /* 52267 */ "LIFETIME_START\0" + /* 52282 */ "G_INSERT\0" + /* 52291 */ "G_FSQRT\0" + /* 52299 */ "G_STRICT_FSQRT\0" + /* 52314 */ "G_BITCAST\0" + /* 52324 */ "G_ADDRSPACE_CAST\0" + /* 52341 */ "TTEST\0" + /* 52347 */ "DBG_VALUE_LIST\0" + /* 52362 */ "LD1i32_POST\0" + /* 52374 */ "ST1i32_POST\0" + /* 52386 */ "LD2i32_POST\0" + /* 52398 */ "ST2i32_POST\0" + /* 52410 */ "LD3i32_POST\0" + /* 52422 */ "ST3i32_POST\0" + /* 52434 */ "LD4i32_POST\0" + /* 52446 */ "ST4i32_POST\0" + /* 52458 */ "LD1i64_POST\0" + /* 52470 */ "ST1i64_POST\0" + /* 52482 */ "LD2i64_POST\0" + /* 52494 */ "ST2i64_POST\0" + /* 52506 */ "LD3i64_POST\0" + /* 52518 */ "ST3i64_POST\0" + /* 52530 */ "LD4i64_POST\0" + /* 52542 */ "ST4i64_POST\0" + /* 52554 */ "LD1i16_POST\0" + /* 52566 */ "ST1i16_POST\0" + /* 52578 */ "LD2i16_POST\0" + /* 52590 */ "ST2i16_POST\0" + /* 52602 */ "LD3i16_POST\0" + /* 52614 */ "ST3i16_POST\0" + /* 52626 */ "LD4i16_POST\0" + /* 52638 */ "ST4i16_POST\0" + /* 52650 */ "LD1i8_POST\0" + /* 52661 */ "ST1i8_POST\0" + /* 52672 */ "LD2i8_POST\0" + /* 52683 */ "ST2i8_POST\0" + /* 52694 */ "LD3i8_POST\0" + /* 52705 */ "ST3i8_POST\0" + /* 52716 */ "LD4i8_POST\0" + /* 52727 */ "ST4i8_POST\0" + /* 52738 */ "LD1Rv16b_POST\0" + /* 52752 */ "LD2Rv16b_POST\0" + /* 52766 */ "LD3Rv16b_POST\0" + /* 52780 */ "LD4Rv16b_POST\0" + /* 52794 */ "LD1Threev16b_POST\0" + /* 52812 */ "ST1Threev16b_POST\0" + /* 52830 */ "LD3Threev16b_POST\0" + /* 52848 */ "ST3Threev16b_POST\0" + /* 52866 */ "LD1Onev16b_POST\0" + /* 52882 */ "ST1Onev16b_POST\0" + /* 52898 */ "LD1Twov16b_POST\0" + /* 52914 */ "ST1Twov16b_POST\0" + /* 52930 */ "LD2Twov16b_POST\0" + /* 52946 */ "ST2Twov16b_POST\0" + /* 52962 */ "LD1Fourv16b_POST\0" + /* 52979 */ "ST1Fourv16b_POST\0" + /* 52996 */ "LD4Fourv16b_POST\0" + /* 53013 */ "ST4Fourv16b_POST\0" + /* 53030 */ "LD1Rv8b_POST\0" + /* 53043 */ "LD2Rv8b_POST\0" + /* 53056 */ "LD3Rv8b_POST\0" + /* 53069 */ "LD4Rv8b_POST\0" + /* 53082 */ "LD1Threev8b_POST\0" + /* 53099 */ "ST1Threev8b_POST\0" + /* 53116 */ "LD3Threev8b_POST\0" + /* 53133 */ "ST3Threev8b_POST\0" + /* 53150 */ "LD1Onev8b_POST\0" + /* 53165 */ "ST1Onev8b_POST\0" + /* 53180 */ "LD1Twov8b_POST\0" + /* 53195 */ "ST1Twov8b_POST\0" + /* 53210 */ "LD2Twov8b_POST\0" + /* 53225 */ "ST2Twov8b_POST\0" + /* 53240 */ "LD1Fourv8b_POST\0" + /* 53256 */ "ST1Fourv8b_POST\0" + /* 53272 */ "LD4Fourv8b_POST\0" + /* 53288 */ "ST4Fourv8b_POST\0" + /* 53304 */ "LD1Rv1d_POST\0" + /* 53317 */ "LD2Rv1d_POST\0" + /* 53330 */ "LD3Rv1d_POST\0" + /* 53343 */ "LD4Rv1d_POST\0" + /* 53356 */ "LD1Threev1d_POST\0" + /* 53373 */ "ST1Threev1d_POST\0" + /* 53390 */ "LD1Onev1d_POST\0" + /* 53405 */ "ST1Onev1d_POST\0" + /* 53420 */ "LD1Twov1d_POST\0" + /* 53435 */ "ST1Twov1d_POST\0" + /* 53450 */ "LD1Fourv1d_POST\0" + /* 53466 */ "ST1Fourv1d_POST\0" + /* 53482 */ "LD1Rv2d_POST\0" + /* 53495 */ "LD2Rv2d_POST\0" + /* 53508 */ "LD3Rv2d_POST\0" + /* 53521 */ "LD4Rv2d_POST\0" + /* 53534 */ "LD1Threev2d_POST\0" + /* 53551 */ "ST1Threev2d_POST\0" + /* 53568 */ "LD3Threev2d_POST\0" + /* 53585 */ "ST3Threev2d_POST\0" + /* 53602 */ "LD1Onev2d_POST\0" + /* 53617 */ "ST1Onev2d_POST\0" + /* 53632 */ "LD1Twov2d_POST\0" + /* 53647 */ "ST1Twov2d_POST\0" + /* 53662 */ "LD2Twov2d_POST\0" + /* 53677 */ "ST2Twov2d_POST\0" + /* 53692 */ "LD1Fourv2d_POST\0" + /* 53708 */ "ST1Fourv2d_POST\0" + /* 53724 */ "LD4Fourv2d_POST\0" + /* 53740 */ "ST4Fourv2d_POST\0" + /* 53756 */ "LD1Rv4h_POST\0" + /* 53769 */ "LD2Rv4h_POST\0" + /* 53782 */ "LD3Rv4h_POST\0" + /* 53795 */ "LD4Rv4h_POST\0" + /* 53808 */ "LD1Threev4h_POST\0" + /* 53825 */ "ST1Threev4h_POST\0" + /* 53842 */ "LD3Threev4h_POST\0" + /* 53859 */ "ST3Threev4h_POST\0" + /* 53876 */ "LD1Onev4h_POST\0" + /* 53891 */ "ST1Onev4h_POST\0" + /* 53906 */ "LD1Twov4h_POST\0" + /* 53921 */ "ST1Twov4h_POST\0" + /* 53936 */ "LD2Twov4h_POST\0" + /* 53951 */ "ST2Twov4h_POST\0" + /* 53966 */ "LD1Fourv4h_POST\0" + /* 53982 */ "ST1Fourv4h_POST\0" + /* 53998 */ "LD4Fourv4h_POST\0" + /* 54014 */ "ST4Fourv4h_POST\0" + /* 54030 */ "LD1Rv8h_POST\0" + /* 54043 */ "LD2Rv8h_POST\0" + /* 54056 */ "LD3Rv8h_POST\0" + /* 54069 */ "LD4Rv8h_POST\0" + /* 54082 */ "LD1Threev8h_POST\0" + /* 54099 */ "ST1Threev8h_POST\0" + /* 54116 */ "LD3Threev8h_POST\0" + /* 54133 */ "ST3Threev8h_POST\0" + /* 54150 */ "LD1Onev8h_POST\0" + /* 54165 */ "ST1Onev8h_POST\0" + /* 54180 */ "LD1Twov8h_POST\0" + /* 54195 */ "ST1Twov8h_POST\0" + /* 54210 */ "LD2Twov8h_POST\0" + /* 54225 */ "ST2Twov8h_POST\0" + /* 54240 */ "LD1Fourv8h_POST\0" + /* 54256 */ "ST1Fourv8h_POST\0" + /* 54272 */ "LD4Fourv8h_POST\0" + /* 54288 */ "ST4Fourv8h_POST\0" + /* 54304 */ "LD1Rv2s_POST\0" + /* 54317 */ "LD2Rv2s_POST\0" + /* 54330 */ "LD3Rv2s_POST\0" + /* 54343 */ "LD4Rv2s_POST\0" + /* 54356 */ "LD1Threev2s_POST\0" + /* 54373 */ "ST1Threev2s_POST\0" + /* 54390 */ "LD3Threev2s_POST\0" + /* 54407 */ "ST3Threev2s_POST\0" + /* 54424 */ "LD1Onev2s_POST\0" + /* 54439 */ "ST1Onev2s_POST\0" + /* 54454 */ "LD1Twov2s_POST\0" + /* 54469 */ "ST1Twov2s_POST\0" + /* 54484 */ "LD2Twov2s_POST\0" + /* 54499 */ "ST2Twov2s_POST\0" + /* 54514 */ "LD1Fourv2s_POST\0" + /* 54530 */ "ST1Fourv2s_POST\0" + /* 54546 */ "LD4Fourv2s_POST\0" + /* 54562 */ "ST4Fourv2s_POST\0" + /* 54578 */ "LD1Rv4s_POST\0" + /* 54591 */ "LD2Rv4s_POST\0" + /* 54604 */ "LD3Rv4s_POST\0" + /* 54617 */ "LD4Rv4s_POST\0" + /* 54630 */ "LD1Threev4s_POST\0" + /* 54647 */ "ST1Threev4s_POST\0" + /* 54664 */ "LD3Threev4s_POST\0" + /* 54681 */ "ST3Threev4s_POST\0" + /* 54698 */ "LD1Onev4s_POST\0" + /* 54713 */ "ST1Onev4s_POST\0" + /* 54728 */ "LD1Twov4s_POST\0" + /* 54743 */ "ST1Twov4s_POST\0" + /* 54758 */ "LD2Twov4s_POST\0" + /* 54773 */ "ST2Twov4s_POST\0" + /* 54788 */ "LD1Fourv4s_POST\0" + /* 54804 */ "ST1Fourv4s_POST\0" + /* 54820 */ "LD4Fourv4s_POST\0" + /* 54836 */ "ST4Fourv4s_POST\0" + /* 54852 */ "BFCVT\0" + /* 54858 */ "G_FPEXT\0" + /* 54866 */ "G_SEXT\0" + /* 54873 */ "G_ASSERT_SEXT\0" + /* 54887 */ "G_ANYEXT\0" + /* 54896 */ "G_ZEXT\0" + /* 54903 */ "G_ASSERT_ZEXT\0" + /* 54917 */ "G_EXT\0" + /* 54923 */ "MOVaddrEXT\0" + /* 54934 */ "ST64BV\0" + /* 54941 */ "G_FDIV\0" + /* 54948 */ "G_STRICT_FDIV\0" + /* 54962 */ "G_SDIV\0" + /* 54969 */ "G_UDIV\0" + /* 54976 */ "CFINV\0" + /* 54982 */ "LD1W\0" + /* 54987 */ "LDFF1W\0" + /* 54994 */ "ST1W\0" + /* 54999 */ "LD2W\0" + /* 55004 */ "ST2W\0" + /* 55009 */ "LD3W\0" + /* 55014 */ "ST3W\0" + /* 55019 */ "LD4W\0" + /* 55024 */ "ST4W\0" + /* 55029 */ "LDADDAW\0" + /* 55037 */ "LDSMINAW\0" + /* 55046 */ "LDUMINAW\0" + /* 55055 */ "CASPAW\0" + /* 55062 */ "SWPAW\0" + /* 55068 */ "LDCLRAW\0" + /* 55076 */ "LDEORAW\0" + /* 55084 */ "CASAW\0" + /* 55090 */ "LDSETAW\0" + /* 55098 */ "LDSMAXAW\0" + /* 55107 */ "LDUMAXAW\0" + /* 55116 */ "LDADDW\0" + /* 55123 */ "LDADDALW\0" + /* 55132 */ "LDSMINALW\0" + /* 55142 */ "LDUMINALW\0" + /* 55152 */ "CASPALW\0" + /* 55160 */ "SWPALW\0" + /* 55167 */ "LDCLRALW\0" + /* 55176 */ "LDEORALW\0" + /* 55185 */ "CASALW\0" + /* 55192 */ "LDSETALW\0" + /* 55201 */ "LDSMAXALW\0" + /* 55211 */ "LDUMAXALW\0" + /* 55221 */ "LDADDLW\0" + /* 55229 */ "LDSMINLW\0" + /* 55238 */ "LDUMINLW\0" + /* 55247 */ "CASPLW\0" + /* 55254 */ "SWPLW\0" + /* 55260 */ "LDCLRLW\0" + /* 55268 */ "LDEORLW\0" + /* 55276 */ "CASLW\0" + /* 55282 */ "LDSETLW\0" + /* 55290 */ "LDSMAXLW\0" + /* 55299 */ "LDUMAXLW\0" + /* 55308 */ "LDSMINW\0" + /* 55316 */ "LDUMINW\0" + /* 55324 */ "G_ADD_LOW\0" + /* 55334 */ "G_FPOW\0" + /* 55341 */ "CASPW\0" + /* 55347 */ "SWPW\0" + /* 55352 */ "LDAXPW\0" + /* 55359 */ "LDXPW\0" + /* 55365 */ "STLXPW\0" + /* 55372 */ "STXPW\0" + /* 55378 */ "LDARW\0" + /* 55384 */ "LDLARW\0" + /* 55391 */ "LDCLRW\0" + /* 55398 */ "STLLRW\0" + /* 55405 */ "STLRW\0" + /* 55411 */ "LDEORW\0" + /* 55418 */ "LDAPRW\0" + /* 55425 */ "LDAXRW\0" + /* 55432 */ "LDXRW\0" + /* 55438 */ "STLXRW\0" + /* 55445 */ "STXRW\0" + /* 55451 */ "CASW\0" + /* 55456 */ "LDSETW\0" + /* 55463 */ "GLD1D_SXTW\0" + /* 55474 */ "GLDFF1D_SXTW\0" + /* 55487 */ "SST1D_SXTW\0" + /* 55498 */ "GLD1B_D_SXTW\0" + /* 55511 */ "GLDFF1B_D_SXTW\0" + /* 55526 */ "SST1B_D_SXTW\0" + /* 55539 */ "GLD1SB_D_SXTW\0" + /* 55553 */ "GLDFF1SB_D_SXTW\0" + /* 55569 */ "GLD1H_D_SXTW\0" + /* 55582 */ "GLDFF1H_D_SXTW\0" + /* 55597 */ "SST1H_D_SXTW\0" + /* 55610 */ "GLD1SH_D_SXTW\0" + /* 55624 */ "GLDFF1SH_D_SXTW\0" + /* 55640 */ "GLD1W_D_SXTW\0" + /* 55653 */ "GLDFF1W_D_SXTW\0" + /* 55668 */ "SST1W_D_SXTW\0" + /* 55681 */ "GLD1SW_D_SXTW\0" + /* 55695 */ "GLDFF1SW_D_SXTW\0" + /* 55711 */ "GLD1B_S_SXTW\0" + /* 55724 */ "GLDFF1B_S_SXTW\0" + /* 55739 */ "SST1B_S_SXTW\0" + /* 55752 */ "GLD1SB_S_SXTW\0" + /* 55766 */ "GLDFF1SB_S_SXTW\0" + /* 55782 */ "GLD1H_S_SXTW\0" + /* 55795 */ "GLDFF1H_S_SXTW\0" + /* 55810 */ "SST1H_S_SXTW\0" + /* 55823 */ "GLD1SH_S_SXTW\0" + /* 55837 */ "GLDFF1SH_S_SXTW\0" + /* 55853 */ "GLD1W_SXTW\0" + /* 55864 */ "GLDFF1W_SXTW\0" + /* 55877 */ "SST1W_SXTW\0" + /* 55888 */ "GLD1D_UXTW\0" + /* 55899 */ "GLDFF1D_UXTW\0" + /* 55912 */ "SST1D_UXTW\0" + /* 55923 */ "GLD1B_D_UXTW\0" + /* 55936 */ "GLDFF1B_D_UXTW\0" + /* 55951 */ "SST1B_D_UXTW\0" + /* 55964 */ "GLD1SB_D_UXTW\0" + /* 55978 */ "GLDFF1SB_D_UXTW\0" + /* 55994 */ "GLD1H_D_UXTW\0" + /* 56007 */ "GLDFF1H_D_UXTW\0" + /* 56022 */ "SST1H_D_UXTW\0" + /* 56035 */ "GLD1SH_D_UXTW\0" + /* 56049 */ "GLDFF1SH_D_UXTW\0" + /* 56065 */ "GLD1W_D_UXTW\0" + /* 56078 */ "GLDFF1W_D_UXTW\0" + /* 56093 */ "SST1W_D_UXTW\0" + /* 56106 */ "GLD1SW_D_UXTW\0" + /* 56120 */ "GLDFF1SW_D_UXTW\0" + /* 56136 */ "GLD1B_S_UXTW\0" + /* 56149 */ "GLDFF1B_S_UXTW\0" + /* 56164 */ "SST1B_S_UXTW\0" + /* 56177 */ "GLD1SB_S_UXTW\0" + /* 56191 */ "GLDFF1SB_S_UXTW\0" + /* 56207 */ "GLD1H_S_UXTW\0" + /* 56220 */ "GLDFF1H_S_UXTW\0" + /* 56235 */ "SST1H_S_UXTW\0" + /* 56248 */ "GLD1SH_S_UXTW\0" + /* 56262 */ "GLDFF1SH_S_UXTW\0" + /* 56278 */ "GLD1W_UXTW\0" + /* 56289 */ "GLDFF1W_UXTW\0" + /* 56302 */ "SST1W_UXTW\0" + /* 56313 */ "CTERMNE_WW\0" + /* 56324 */ "CTERMEQ_WW\0" + /* 56335 */ "LDSMAXW\0" + /* 56343 */ "LDUMAXW\0" + /* 56351 */ "CBZW\0" + /* 56356 */ "TBZW\0" + /* 56361 */ "CBNZW\0" + /* 56367 */ "TBNZW\0" + /* 56373 */ "LD1RO_W\0" + /* 56381 */ "LD1RQ_W\0" + /* 56389 */ "SpeculationSafeValueW\0" + /* 56411 */ "LDRBBroW\0" + /* 56420 */ "STRBBroW\0" + /* 56429 */ "LDRBroW\0" + /* 56437 */ "STRBroW\0" + /* 56445 */ "LDRDroW\0" + /* 56453 */ "STRDroW\0" + /* 56461 */ "LDRHHroW\0" + /* 56470 */ "STRHHroW\0" + /* 56479 */ "LDRHroW\0" + /* 56487 */ "STRHroW\0" + /* 56495 */ "PRFMroW\0" + /* 56503 */ "LDRQroW\0" + /* 56511 */ "STRQroW\0" + /* 56519 */ "LDRSroW\0" + /* 56527 */ "STRSroW\0" + /* 56535 */ "LDRSBWroW\0" + /* 56545 */ "LDRSHWroW\0" + /* 56555 */ "LDRWroW\0" + /* 56563 */ "STRWroW\0" + /* 56571 */ "LDRSWroW\0" + /* 56580 */ "LDRSBXroW\0" + /* 56590 */ "LDRSHXroW\0" + /* 56600 */ "LDRXroW\0" + /* 56608 */ "STRXroW\0" + /* 56616 */ "BCAX\0" + /* 56621 */ "LDADDAX\0" + /* 56629 */ "G_VECREDUCE_FMAX\0" + /* 56646 */ "G_VECREDUCE_SMAX\0" + /* 56663 */ "G_SMAX\0" + /* 56670 */ "G_VECREDUCE_UMAX\0" + /* 56687 */ "G_UMAX\0" + /* 56694 */ "G_ATOMICRMW_UMAX\0" + /* 56711 */ "G_ATOMICRMW_MAX\0" + /* 56727 */ "LDSMINAX\0" + /* 56736 */ "LDUMINAX\0" + /* 56745 */ "CASPAX\0" + /* 56752 */ "SWPAX\0" + /* 56758 */ "LDCLRAX\0" + /* 56766 */ "LDEORAX\0" + /* 56774 */ "CASAX\0" + /* 56780 */ "LDSETAX\0" + /* 56788 */ "LDSMAXAX\0" + /* 56797 */ "LDUMAXAX\0" + /* 56806 */ "LDADDX\0" + /* 56813 */ "G_FRAME_INDEX\0" + /* 56827 */ "CLREX\0" + /* 56833 */ "G_SBFX\0" + /* 56840 */ "G_UBFX\0" + /* 56847 */ "G_SMULFIX\0" + /* 56857 */ "G_UMULFIX\0" + /* 56867 */ "G_SDIVFIX\0" + /* 56877 */ "G_UDIVFIX\0" + /* 56887 */ "LDADDALX\0" + /* 56896 */ "LDSMINALX\0" + /* 56906 */ "LDUMINALX\0" + /* 56916 */ "CASPALX\0" + /* 56924 */ "SWPALX\0" + /* 56931 */ "LDCLRALX\0" + /* 56940 */ "LDEORALX\0" + /* 56949 */ "CASALX\0" + /* 56956 */ "LDSETALX\0" + /* 56965 */ "LDSMAXALX\0" + /* 56975 */ "LDUMAXALX\0" + /* 56985 */ "LDADDLX\0" + /* 56993 */ "LDSMINLX\0" + /* 57002 */ "LDUMINLX\0" + /* 57011 */ "CASPLX\0" + /* 57018 */ "SWPLX\0" + /* 57024 */ "LDCLRLX\0" + /* 57032 */ "LDEORLX\0" + /* 57040 */ "CASLX\0" + /* 57046 */ "LDSETLX\0" + /* 57054 */ "LDSMAXLX\0" + /* 57063 */ "LDUMAXLX\0" + /* 57072 */ "LDSMINX\0" + /* 57080 */ "LDUMINX\0" + /* 57088 */ "CASPX\0" + /* 57094 */ "SWPX\0" + /* 57099 */ "LDAXPX\0" + /* 57106 */ "LDXPX\0" + /* 57112 */ "STLXPX\0" + /* 57119 */ "STXPX\0" + /* 57125 */ "LDARX\0" + /* 57131 */ "LDLARX\0" + /* 57138 */ "LDCLRX\0" + /* 57145 */ "STLLRX\0" + /* 57152 */ "STLRX\0" + /* 57158 */ "LDEORX\0" + /* 57165 */ "LDAPRX\0" + /* 57172 */ "LDAXRX\0" + /* 57179 */ "LDXRX\0" + /* 57185 */ "STLXRX\0" + /* 57192 */ "STXRX\0" + /* 57198 */ "CASX\0" + /* 57203 */ "LDSETX\0" + /* 57210 */ "LDSMAXX\0" + /* 57218 */ "LDUMAXX\0" + /* 57226 */ "CTERMNE_XX\0" + /* 57237 */ "CTERMEQ_XX\0" + /* 57248 */ "CBZX\0" + /* 57253 */ "TBZX\0" + /* 57258 */ "CBNZX\0" + /* 57264 */ "TBNZX\0" + /* 57270 */ "SEH_SaveFRegP_X\0" + /* 57286 */ "SEH_SaveRegP_X\0" + /* 57301 */ "SEH_SaveFPLR_X\0" + /* 57316 */ "SEH_SaveFReg_X\0" + /* 57331 */ "SEH_SaveReg_X\0" + /* 57345 */ "SpeculationSafeValueX\0" + /* 57367 */ "LDRBBroX\0" + /* 57376 */ "STRBBroX\0" + /* 57385 */ "LDRBroX\0" + /* 57393 */ "STRBroX\0" + /* 57401 */ "LDRDroX\0" + /* 57409 */ "STRDroX\0" + /* 57417 */ "LDRHHroX\0" + /* 57426 */ "STRHHroX\0" + /* 57435 */ "LDRHroX\0" + /* 57443 */ "STRHroX\0" + /* 57451 */ "PRFMroX\0" + /* 57459 */ "LDRQroX\0" + /* 57467 */ "STRQroX\0" + /* 57475 */ "LDRSroX\0" + /* 57483 */ "STRSroX\0" + /* 57491 */ "LDRSBWroX\0" + /* 57501 */ "LDRSHWroX\0" + /* 57511 */ "LDRWroX\0" + /* 57519 */ "STRWroX\0" + /* 57527 */ "LDRSWroX\0" + /* 57536 */ "LDRSBXroX\0" + /* 57546 */ "LDRSHXroX\0" + /* 57556 */ "LDRXroX\0" + /* 57564 */ "STRXroX\0" + /* 57572 */ "EMITBKEY\0" + /* 57581 */ "SM4ENCKEY\0" + /* 57591 */ "G_MEMCPY\0" + /* 57600 */ "COPY\0" + /* 57605 */ "BRAAZ\0" + /* 57611 */ "BLRAAZ\0" + /* 57618 */ "PACIAZ\0" + /* 57625 */ "AUTIAZ\0" + /* 57632 */ "BRABZ\0" + /* 57638 */ "BLRABZ\0" + /* 57645 */ "PACIBZ\0" + /* 57652 */ "AUTIBZ\0" + /* 57659 */ "G_FCMGEZ\0" + /* 57668 */ "G_FCMLEZ\0" + /* 57677 */ "G_CTLZ\0" + /* 57684 */ "G_FCMEQZ\0" + /* 57693 */ "G_FCMGTZ\0" + /* 57702 */ "G_FCMLTZ\0" + /* 57711 */ "G_CTTZ\0" + /* 57718 */ "EOR3_ZZZZ\0" + /* 57728 */ "NBSL_ZZZZ\0" + /* 57738 */ "BSL1N_ZZZZ\0" + /* 57749 */ "BSL2N_ZZZZ\0" + /* 57760 */ "BCAX_ZZZZ\0" + /* 57770 */ "BFMMLA_ZZZ\0" + /* 57781 */ "USMMLA_ZZZ\0" + /* 57792 */ "UMMLA_ZZZ\0" + /* 57802 */ "BFMMLA_B_ZZZ\0" + /* 57815 */ "BIC_ZZZ\0" + /* 57823 */ "AND_ZZZ\0" + /* 57831 */ "HISTSEG_ZZZ\0" + /* 57843 */ "EOR_ZZZ\0" + /* 57851 */ "ORR_ZZZ\0" + /* 57859 */ "BFDOT_ZZZ\0" + /* 57869 */ "USDOT_ZZZ\0" + /* 57879 */ "BFMMLA_T_ZZZ\0" + /* 57892 */ "MOVPRFX_ZZ\0" + /* 57903 */ "REVD_ZPmZ\0" + /* 57913 */ "BFCVTNT_ZPmZ\0" + /* 57926 */ "BFCVT_ZPmZ\0" + /* 57937 */ "LD1Rv16b\0" + /* 57946 */ "LD2Rv16b\0" + /* 57955 */ "LD3Rv16b\0" + /* 57964 */ "LD4Rv16b\0" + /* 57973 */ "LD1Threev16b\0" + /* 57986 */ "ST1Threev16b\0" + /* 57999 */ "LD3Threev16b\0" + /* 58012 */ "ST3Threev16b\0" + /* 58025 */ "LD1Onev16b\0" + /* 58036 */ "ST1Onev16b\0" + /* 58047 */ "LD1Twov16b\0" + /* 58058 */ "ST1Twov16b\0" + /* 58069 */ "LD2Twov16b\0" + /* 58080 */ "ST2Twov16b\0" + /* 58091 */ "LD1Fourv16b\0" + /* 58103 */ "ST1Fourv16b\0" + /* 58115 */ "LD4Fourv16b\0" + /* 58127 */ "ST4Fourv16b\0" + /* 58139 */ "LD1Rv8b\0" + /* 58147 */ "LD2Rv8b\0" + /* 58155 */ "LD3Rv8b\0" + /* 58163 */ "LD4Rv8b\0" + /* 58171 */ "LD1Threev8b\0" + /* 58183 */ "ST1Threev8b\0" + /* 58195 */ "LD3Threev8b\0" + /* 58207 */ "ST3Threev8b\0" + /* 58219 */ "LD1Onev8b\0" + /* 58229 */ "ST1Onev8b\0" + /* 58239 */ "LD1Twov8b\0" + /* 58249 */ "ST1Twov8b\0" + /* 58259 */ "LD2Twov8b\0" + /* 58269 */ "ST2Twov8b\0" + /* 58279 */ "LD1Fourv8b\0" + /* 58290 */ "ST1Fourv8b\0" + /* 58301 */ "LD4Fourv8b\0" + /* 58312 */ "ST4Fourv8b\0" + /* 58323 */ "SQSHLb\0" + /* 58330 */ "UQSHLb\0" + /* 58337 */ "SQSHRNb\0" + /* 58345 */ "UQSHRNb\0" + /* 58353 */ "SQRSHRNb\0" + /* 58362 */ "UQRSHRNb\0" + /* 58371 */ "SQSHRUNb\0" + /* 58380 */ "SQRSHRUNb\0" + /* 58390 */ "SQSHLUb\0" + /* 58398 */ "Bcc\0" + /* 58402 */ "SEH_StackAlloc\0" + /* 58417 */ "LD1Rv1d\0" + /* 58425 */ "LD2Rv1d\0" + /* 58433 */ "LD3Rv1d\0" + /* 58441 */ "LD4Rv1d\0" + /* 58449 */ "LD1Threev1d\0" + /* 58461 */ "ST1Threev1d\0" + /* 58473 */ "LD1Onev1d\0" + /* 58483 */ "ST1Onev1d\0" + /* 58493 */ "LD1Twov1d\0" + /* 58503 */ "ST1Twov1d\0" + /* 58513 */ "LD1Fourv1d\0" + /* 58524 */ "ST1Fourv1d\0" + /* 58535 */ "LD1Rv2d\0" + /* 58543 */ "LD2Rv2d\0" + /* 58551 */ "LD3Rv2d\0" + /* 58559 */ "LD4Rv2d\0" + /* 58567 */ "LD1Threev2d\0" + /* 58579 */ "ST1Threev2d\0" + /* 58591 */ "LD3Threev2d\0" + /* 58603 */ "ST3Threev2d\0" + /* 58615 */ "LD1Onev2d\0" + /* 58625 */ "ST1Onev2d\0" + /* 58635 */ "LD1Twov2d\0" + /* 58645 */ "ST1Twov2d\0" + /* 58655 */ "LD2Twov2d\0" + /* 58665 */ "ST2Twov2d\0" + /* 58675 */ "LD1Fourv2d\0" + /* 58686 */ "ST1Fourv2d\0" + /* 58697 */ "LD4Fourv2d\0" + /* 58708 */ "ST4Fourv2d\0" + /* 58719 */ "SRSRAd\0" + /* 58726 */ "URSRAd\0" + /* 58733 */ "SSRAd\0" + /* 58739 */ "USRAd\0" + /* 58745 */ "SCVTFd\0" + /* 58752 */ "UCVTFd\0" + /* 58759 */ "SLId\0" + /* 58764 */ "SRId\0" + /* 58769 */ "SQSHLd\0" + /* 58776 */ "UQSHLd\0" + /* 58783 */ "SRSHRd\0" + /* 58790 */ "URSHRd\0" + /* 58797 */ "SSHRd\0" + /* 58803 */ "USHRd\0" + /* 58809 */ "FCVTZSd\0" + /* 58817 */ "SQSHLUd\0" + /* 58825 */ "FCVTZUd\0" + /* 58833 */ "AESIMCrrTied\0" + /* 58846 */ "AESMCrrTied\0" + /* 58858 */ "LDRAAindexed\0" + /* 58871 */ "LDRABindexed\0" + /* 58884 */ "FCMLAv4f32_indexed\0" + /* 58903 */ "FMLAv1i32_indexed\0" + /* 58921 */ "SQDMULHv1i32_indexed\0" + /* 58942 */ "SQRDMULHv1i32_indexed\0" + /* 58964 */ "SQDMLALv1i32_indexed\0" + /* 58985 */ "SQDMULLv1i32_indexed\0" + /* 59006 */ "SQDMLSLv1i32_indexed\0" + /* 59027 */ "FMULv1i32_indexed\0" + /* 59045 */ "FMLSv1i32_indexed\0" + /* 59063 */ "FMULXv1i32_indexed\0" + /* 59082 */ "FMLAv2i32_indexed\0" + /* 59100 */ "SQRDMLAHv2i32_indexed\0" + /* 59122 */ "SQDMULHv2i32_indexed\0" + /* 59143 */ "SQRDMULHv2i32_indexed\0" + /* 59165 */ "SQRDMLSHv2i32_indexed\0" + /* 59187 */ "SQDMLALv2i32_indexed\0" + /* 59208 */ "SMLALv2i32_indexed\0" + /* 59227 */ "UMLALv2i32_indexed\0" + /* 59246 */ "SQDMULLv2i32_indexed\0" + /* 59267 */ "SMULLv2i32_indexed\0" + /* 59286 */ "UMULLv2i32_indexed\0" + /* 59305 */ "SQDMLSLv2i32_indexed\0" + /* 59326 */ "SMLSLv2i32_indexed\0" + /* 59345 */ "UMLSLv2i32_indexed\0" + /* 59364 */ "FMULv2i32_indexed\0" + /* 59382 */ "FMLSv2i32_indexed\0" + /* 59400 */ "FMULXv2i32_indexed\0" + /* 59419 */ "FMLAv4i32_indexed\0" + /* 59437 */ "SQRDMLAHv4i32_indexed\0" + /* 59459 */ "SQDMULHv4i32_indexed\0" + /* 59480 */ "SQRDMULHv4i32_indexed\0" + /* 59502 */ "SQRDMLSHv4i32_indexed\0" + /* 59524 */ "SQDMLALv4i32_indexed\0" + /* 59545 */ "SMLALv4i32_indexed\0" + /* 59564 */ "UMLALv4i32_indexed\0" + /* 59583 */ "SQDMULLv4i32_indexed\0" + /* 59604 */ "SMULLv4i32_indexed\0" + /* 59623 */ "UMULLv4i32_indexed\0" + /* 59642 */ "SQDMLSLv4i32_indexed\0" + /* 59663 */ "SMLSLv4i32_indexed\0" + /* 59682 */ "UMLSLv4i32_indexed\0" + /* 59701 */ "FMULv4i32_indexed\0" + /* 59719 */ "FMLSv4i32_indexed\0" + /* 59737 */ "FMULXv4i32_indexed\0" + /* 59756 */ "SQRDMLAHi32_indexed\0" + /* 59776 */ "SQRDMLSHi32_indexed\0" + /* 59796 */ "FMLAv1i64_indexed\0" + /* 59814 */ "SQDMLALv1i64_indexed\0" + /* 59835 */ "SQDMULLv1i64_indexed\0" + /* 59856 */ "SQDMLSLv1i64_indexed\0" + /* 59877 */ "FMULv1i64_indexed\0" + /* 59895 */ "FMLSv1i64_indexed\0" + /* 59913 */ "FMULXv1i64_indexed\0" + /* 59932 */ "FMLAv2i64_indexed\0" + /* 59950 */ "FMULv2i64_indexed\0" + /* 59968 */ "FMLSv2i64_indexed\0" + /* 59986 */ "FMULXv2i64_indexed\0" + /* 60005 */ "FCMLAv4f16_indexed\0" + /* 60024 */ "FCMLAv8f16_indexed\0" + /* 60043 */ "FMLAv1i16_indexed\0" + /* 60061 */ "SQDMULHv1i16_indexed\0" + /* 60082 */ "SQRDMULHv1i16_indexed\0" + /* 60104 */ "FMULv1i16_indexed\0" + /* 60122 */ "FMLSv1i16_indexed\0" + /* 60140 */ "FMULXv1i16_indexed\0" + /* 60159 */ "FMLAv4i16_indexed\0" + /* 60177 */ "SQRDMLAHv4i16_indexed\0" + /* 60199 */ "SQDMULHv4i16_indexed\0" + /* 60220 */ "SQRDMULHv4i16_indexed\0" + /* 60242 */ "SQRDMLSHv4i16_indexed\0" + /* 60264 */ "SQDMLALv4i16_indexed\0" + /* 60285 */ "SMLALv4i16_indexed\0" + /* 60304 */ "UMLALv4i16_indexed\0" + /* 60323 */ "SQDMULLv4i16_indexed\0" + /* 60344 */ "SMULLv4i16_indexed\0" + /* 60363 */ "UMULLv4i16_indexed\0" + /* 60382 */ "SQDMLSLv4i16_indexed\0" + /* 60403 */ "SMLSLv4i16_indexed\0" + /* 60422 */ "UMLSLv4i16_indexed\0" + /* 60441 */ "FMULv4i16_indexed\0" + /* 60459 */ "FMLSv4i16_indexed\0" + /* 60477 */ "FMULXv4i16_indexed\0" + /* 60496 */ "FMLAv8i16_indexed\0" + /* 60514 */ "SQRDMLAHv8i16_indexed\0" + /* 60536 */ "SQDMULHv8i16_indexed\0" + /* 60557 */ "SQRDMULHv8i16_indexed\0" + /* 60579 */ "SQRDMLSHv8i16_indexed\0" + /* 60601 */ "SQDMLALv8i16_indexed\0" + /* 60622 */ "SMLALv8i16_indexed\0" + /* 60641 */ "UMLALv8i16_indexed\0" + /* 60660 */ "SQDMULLv8i16_indexed\0" + /* 60681 */ "SMULLv8i16_indexed\0" + /* 60700 */ "UMULLv8i16_indexed\0" + /* 60719 */ "SQDMLSLv8i16_indexed\0" + /* 60740 */ "SMLSLv8i16_indexed\0" + /* 60759 */ "UMLSLv8i16_indexed\0" + /* 60778 */ "FMULv8i16_indexed\0" + /* 60796 */ "FMLSv8i16_indexed\0" + /* 60814 */ "FMULXv8i16_indexed\0" + /* 60833 */ "SQRDMLAHi16_indexed\0" + /* 60853 */ "SQRDMLSHi16_indexed\0" + /* 60873 */ "SEH_EpilogEnd\0" + /* 60887 */ "SEH_PrologEnd\0" + /* 60901 */ "TBLv16i8Three\0" + /* 60915 */ "TBXv16i8Three\0" + /* 60929 */ "TBLv8i8Three\0" + /* 60942 */ "TBXv8i8Three\0" + /* 60955 */ "TBLv16i8One\0" + /* 60967 */ "TBXv16i8One\0" + /* 60979 */ "TBLv8i8One\0" + /* 60990 */ "TBXv8i8One\0" + /* 61001 */ "DUPv2i32lane\0" + /* 61014 */ "DUPv4i32lane\0" + /* 61027 */ "INSvi32lane\0" + /* 61039 */ "DUPv2i64lane\0" + /* 61052 */ "INSvi64lane\0" + /* 61064 */ "DUPv4i16lane\0" + /* 61077 */ "DUPv8i16lane\0" + /* 61090 */ "INSvi16lane\0" + /* 61102 */ "DUPv16i8lane\0" + /* 61115 */ "DUPv8i8lane\0" + /* 61127 */ "INSvi8lane\0" + /* 61138 */ "LDRBBpre\0" + /* 61147 */ "STRBBpre\0" + /* 61156 */ "LDRBpre\0" + /* 61164 */ "STRBpre\0" + /* 61172 */ "LDPDpre\0" + /* 61180 */ "STPDpre\0" + /* 61188 */ "LDRDpre\0" + /* 61196 */ "STRDpre\0" + /* 61204 */ "LDRHHpre\0" + /* 61213 */ "STRHHpre\0" + /* 61222 */ "LDRHpre\0" + /* 61230 */ "STRHpre\0" + /* 61238 */ "STGPpre\0" + /* 61246 */ "LDPQpre\0" + /* 61254 */ "STPQpre\0" + /* 61262 */ "LDRQpre\0" + /* 61270 */ "STRQpre\0" + /* 61278 */ "LDPSpre\0" + /* 61286 */ "STPSpre\0" + /* 61294 */ "LDRSpre\0" + /* 61302 */ "STRSpre\0" + /* 61310 */ "LDRSBWpre\0" + /* 61320 */ "LDRSHWpre\0" + /* 61330 */ "LDPWpre\0" + /* 61338 */ "STPWpre\0" + /* 61346 */ "LDRWpre\0" + /* 61354 */ "STRWpre\0" + /* 61362 */ "LDPSWpre\0" + /* 61371 */ "LDRSWpre\0" + /* 61380 */ "LDRSBXpre\0" + /* 61390 */ "LDRSHXpre\0" + /* 61400 */ "LDPXpre\0" + /* 61408 */ "STPXpre\0" + /* 61416 */ "LDRXpre\0" + /* 61424 */ "STRXpre\0" + /* 61432 */ "SEH_SaveFReg\0" + /* 61445 */ "SEH_SaveReg\0" + /* 61457 */ "HOM_Epilog\0" + /* 61468 */ "HOM_Prolog\0" + /* 61479 */ "LD1Rv4h\0" + /* 61487 */ "LD2Rv4h\0" + /* 61495 */ "LD3Rv4h\0" + /* 61503 */ "LD4Rv4h\0" + /* 61511 */ "LD1Threev4h\0" + /* 61523 */ "ST1Threev4h\0" + /* 61535 */ "LD3Threev4h\0" + /* 61547 */ "ST3Threev4h\0" + /* 61559 */ "LD1Onev4h\0" + /* 61569 */ "ST1Onev4h\0" + /* 61579 */ "LD1Twov4h\0" + /* 61589 */ "ST1Twov4h\0" + /* 61599 */ "LD2Twov4h\0" + /* 61609 */ "ST2Twov4h\0" + /* 61619 */ "LD1Fourv4h\0" + /* 61630 */ "ST1Fourv4h\0" + /* 61641 */ "LD4Fourv4h\0" + /* 61652 */ "ST4Fourv4h\0" + /* 61663 */ "LD1Rv8h\0" + /* 61671 */ "LD2Rv8h\0" + /* 61679 */ "LD3Rv8h\0" + /* 61687 */ "LD4Rv8h\0" + /* 61695 */ "LD1Threev8h\0" + /* 61707 */ "ST1Threev8h\0" + /* 61719 */ "LD3Threev8h\0" + /* 61731 */ "ST3Threev8h\0" + /* 61743 */ "LD1Onev8h\0" + /* 61753 */ "ST1Onev8h\0" + /* 61763 */ "LD1Twov8h\0" + /* 61773 */ "ST1Twov8h\0" + /* 61783 */ "LD2Twov8h\0" + /* 61793 */ "ST2Twov8h\0" + /* 61803 */ "LD1Fourv8h\0" + /* 61814 */ "ST1Fourv8h\0" + /* 61825 */ "LD4Fourv8h\0" + /* 61836 */ "ST4Fourv8h\0" + /* 61847 */ "SCVTFh\0" + /* 61854 */ "UCVTFh\0" + /* 61861 */ "SQSHLh\0" + /* 61868 */ "UQSHLh\0" + /* 61875 */ "SQSHRNh\0" + /* 61883 */ "UQSHRNh\0" + /* 61891 */ "SQRSHRNh\0" + /* 61900 */ "UQRSHRNh\0" + /* 61909 */ "SQSHRUNh\0" + /* 61918 */ "SQRSHRUNh\0" + /* 61928 */ "FCVTZSh\0" + /* 61936 */ "SQSHLUh\0" + /* 61944 */ "FCVTZUh\0" + /* 61952 */ "LDURBBi\0" + /* 61960 */ "STURBBi\0" + /* 61968 */ "LDTRBi\0" + /* 61975 */ "STTRBi\0" + /* 61982 */ "LDURBi\0" + /* 61989 */ "STLURBi\0" + /* 61997 */ "LDAPURBi\0" + /* 62006 */ "STURBi\0" + /* 62013 */ "LDPDi\0" + /* 62019 */ "LDNPDi\0" + /* 62026 */ "STNPDi\0" + /* 62033 */ "STPDi\0" + /* 62039 */ "LDURDi\0" + /* 62046 */ "STURDi\0" + /* 62053 */ "FMOVDi\0" + /* 62060 */ "LDURHHi\0" + /* 62068 */ "STURHHi\0" + /* 62076 */ "LDTRHi\0" + /* 62083 */ "STTRHi\0" + /* 62090 */ "LDURHi\0" + /* 62097 */ "STLURHi\0" + /* 62105 */ "LDAPURHi\0" + /* 62114 */ "STURHi\0" + /* 62121 */ "FMOVHi\0" + /* 62128 */ "PRFUMi\0" + /* 62135 */ "STGPi\0" + /* 62141 */ "LDPQi\0" + /* 62147 */ "LDNPQi\0" + /* 62154 */ "STNPQi\0" + /* 62161 */ "STPQi\0" + /* 62167 */ "LDURQi\0" + /* 62174 */ "STURQi\0" + /* 62181 */ "LDAPURi\0" + /* 62189 */ "LDPSi\0" + /* 62195 */ "LDNPSi\0" + /* 62202 */ "STNPSi\0" + /* 62209 */ "STPSi\0" + /* 62215 */ "LDURSi\0" + /* 62222 */ "STURSi\0" + /* 62229 */ "FMOVSi\0" + /* 62236 */ "LDTRSBWi\0" + /* 62245 */ "LDURSBWi\0" + /* 62254 */ "LDAPURSBWi\0" + /* 62265 */ "LDTRSHWi\0" + /* 62274 */ "LDURSHWi\0" + /* 62283 */ "LDAPURSHWi\0" + /* 62294 */ "MOVKWi\0" + /* 62301 */ "CCMNWi\0" + /* 62308 */ "MOVNWi\0" + /* 62315 */ "LDPWi\0" + /* 62321 */ "CCMPWi\0" + /* 62328 */ "LDNPWi\0" + /* 62335 */ "STNPWi\0" + /* 62342 */ "STPWi\0" + /* 62348 */ "LDTRWi\0" + /* 62355 */ "STTRWi\0" + /* 62362 */ "LDURWi\0" + /* 62369 */ "STLURWi\0" + /* 62377 */ "STURWi\0" + /* 62384 */ "LDPSWi\0" + /* 62391 */ "LDTRSWi\0" + /* 62399 */ "LDURSWi\0" + /* 62407 */ "LDAPURSWi\0" + /* 62417 */ "MOVZWi\0" + /* 62424 */ "LDTRSBXi\0" + /* 62433 */ "LDURSBXi\0" + /* 62442 */ "LDAPURSBXi\0" + /* 62453 */ "LDTRSHXi\0" + /* 62462 */ "LDURSHXi\0" + /* 62471 */ "LDAPURSHXi\0" + /* 62482 */ "MOVKXi\0" + /* 62489 */ "CCMNXi\0" + /* 62496 */ "MOVNXi\0" + /* 62503 */ "LDPXi\0" + /* 62509 */ "CCMPXi\0" + /* 62516 */ "LDNPXi\0" + /* 62523 */ "STNPXi\0" + /* 62530 */ "STPXi\0" + /* 62536 */ "LDTRXi\0" + /* 62543 */ "STTRXi\0" + /* 62550 */ "LDURXi\0" + /* 62557 */ "STLURXi\0" + /* 62565 */ "LDAPURXi\0" + /* 62574 */ "STURXi\0" + /* 62581 */ "MOVZXi\0" + /* 62588 */ "TCRETURNdi\0" + /* 62599 */ "FCMPEDri\0" + /* 62608 */ "FCMPDri\0" + /* 62616 */ "SCVTFSWDri\0" + /* 62627 */ "UCVTFSWDri\0" + /* 62638 */ "FCVTZSSWDri\0" + /* 62650 */ "FCVTZUSWDri\0" + /* 62662 */ "SCVTFUWDri\0" + /* 62673 */ "UCVTFUWDri\0" + /* 62684 */ "SCVTFSXDri\0" + /* 62695 */ "UCVTFSXDri\0" + /* 62706 */ "FCVTZSSXDri\0" + /* 62718 */ "FCVTZUSXDri\0" + /* 62730 */ "SCVTFUXDri\0" + /* 62741 */ "UCVTFUXDri\0" + /* 62752 */ "FCMPEHri\0" + /* 62761 */ "FCMPHri\0" + /* 62769 */ "SCVTFSWHri\0" + /* 62780 */ "UCVTFSWHri\0" + /* 62791 */ "FCVTZSSWHri\0" + /* 62803 */ "FCVTZUSWHri\0" + /* 62815 */ "SCVTFUWHri\0" + /* 62826 */ "UCVTFUWHri\0" + /* 62837 */ "SCVTFSXHri\0" + /* 62848 */ "UCVTFSXHri\0" + /* 62859 */ "FCVTZSSXHri\0" + /* 62871 */ "FCVTZUSXHri\0" + /* 62883 */ "SCVTFUXHri\0" + /* 62894 */ "UCVTFUXHri\0" + /* 62905 */ "TCRETURNri\0" + /* 62916 */ "FCMPESri\0" + /* 62925 */ "FCMPSri\0" + /* 62933 */ "SCVTFSWSri\0" + /* 62944 */ "UCVTFSWSri\0" + /* 62955 */ "FCVTZSSWSri\0" + /* 62967 */ "FCVTZUSWSri\0" + /* 62979 */ "SCVTFUWSri\0" + /* 62990 */ "UCVTFUWSri\0" + /* 63001 */ "SCVTFSXSri\0" + /* 63012 */ "UCVTFSXSri\0" + /* 63023 */ "FCVTZSSXSri\0" + /* 63035 */ "FCVTZUSXSri\0" + /* 63047 */ "SCVTFUXSri\0" + /* 63058 */ "UCVTFUXSri\0" + /* 63069 */ "SUBWri\0" + /* 63076 */ "ADDWri\0" + /* 63083 */ "ANDWri\0" + /* 63090 */ "SBFMWri\0" + /* 63098 */ "UBFMWri\0" + /* 63106 */ "EORWri\0" + /* 63113 */ "ORRWri\0" + /* 63120 */ "SUBSWri\0" + /* 63128 */ "ADDSWri\0" + /* 63136 */ "ANDSWri\0" + /* 63144 */ "SUBXri\0" + /* 63151 */ "ADDXri\0" + /* 63158 */ "ANDXri\0" + /* 63165 */ "SBFMXri\0" + /* 63173 */ "UBFMXri\0" + /* 63181 */ "EORXri\0" + /* 63188 */ "ORRXri\0" + /* 63195 */ "SUBSXri\0" + /* 63203 */ "ADDSXri\0" + /* 63211 */ "ANDSXri\0" + /* 63219 */ "EXTRWrri\0" + /* 63228 */ "EXTRXrri\0" + /* 63237 */ "LDRBBui\0" + /* 63245 */ "STRBBui\0" + /* 63253 */ "LDRBui\0" + /* 63260 */ "STRBui\0" + /* 63267 */ "LDRDui\0" + /* 63274 */ "STRDui\0" + /* 63281 */ "LDRHHui\0" + /* 63289 */ "STRHHui\0" + /* 63297 */ "LDRHui\0" + /* 63304 */ "STRHui\0" + /* 63311 */ "PRFMui\0" + /* 63318 */ "LDRQui\0" + /* 63325 */ "STRQui\0" + /* 63332 */ "LDRSui\0" + /* 63339 */ "STRSui\0" + /* 63346 */ "LDRSBWui\0" + /* 63355 */ "LDRSHWui\0" + /* 63364 */ "LDRWui\0" + /* 63371 */ "STRWui\0" + /* 63378 */ "LDRSWui\0" + /* 63386 */ "LDRSBXui\0" + /* 63395 */ "LDRSHXui\0" + /* 63404 */ "LDRXui\0" + /* 63411 */ "STRXui\0" + /* 63418 */ "LDRAAwriteback\0" + /* 63433 */ "LDRABwriteback\0" + /* 63448 */ "STGloop_wback\0" + /* 63462 */ "STZGloop_wback\0" + /* 63477 */ "IRGstack\0" + /* 63486 */ "TAGPstack\0" + /* 63496 */ "LDRDl\0" + /* 63502 */ "PRFMl\0" + /* 63508 */ "LDRQl\0" + /* 63514 */ "LDRSl\0" + /* 63520 */ "LDRWl\0" + /* 63526 */ "LDRSWl\0" + /* 63533 */ "LDRXl\0" + /* 63539 */ "MVNIv2s_msl\0" + /* 63551 */ "MOVIv2s_msl\0" + /* 63563 */ "MVNIv4s_msl\0" + /* 63575 */ "MOVIv4s_msl\0" + /* 63587 */ "MOVi32imm\0" + /* 63597 */ "MOVi64imm\0" + /* 63607 */ "MOVMCSym\0" + /* 63616 */ "TBLv16i8Two\0" + /* 63628 */ "TBXv16i8Two\0" + /* 63640 */ "TBLv8i8Two\0" + /* 63651 */ "TBXv8i8Two\0" + /* 63662 */ "FADDPv2i32p\0" + /* 63674 */ "FMINNMPv2i32p\0" + /* 63688 */ "FMAXNMPv2i32p\0" + /* 63702 */ "FMINPv2i32p\0" + /* 63714 */ "FMAXPv2i32p\0" + /* 63726 */ "FADDPv2i64p\0" + /* 63738 */ "FMINNMPv2i64p\0" + /* 63752 */ "FMAXNMPv2i64p\0" + /* 63766 */ "FMINPv2i64p\0" + /* 63778 */ "FMAXPv2i64p\0" + /* 63790 */ "FADDPv2i16p\0" + /* 63802 */ "FMINNMPv2i16p\0" + /* 63816 */ "FMAXNMPv2i16p\0" + /* 63830 */ "FMINPv2i16p\0" + /* 63842 */ "FMAXPv2i16p\0" + /* 63854 */ "SEH_Nop\0" + /* 63862 */ "STGloop\0" + /* 63870 */ "STZGloop\0" + /* 63879 */ "FRINTADr\0" + /* 63888 */ "FNEGDr\0" + /* 63895 */ "FCVTHDr\0" + /* 63903 */ "FRINTIDr\0" + /* 63912 */ "FRINTMDr\0" + /* 63921 */ "FRINTNDr\0" + /* 63930 */ "FRINTPDr\0" + /* 63939 */ "FABSDr\0" + /* 63946 */ "FCVTSDr\0" + /* 63954 */ "FSQRTDr\0" + /* 63962 */ "FMOVDr\0" + /* 63969 */ "FCVTASUWDr\0" + /* 63980 */ "FCVTMSUWDr\0" + /* 63991 */ "FCVTNSUWDr\0" + /* 64002 */ "FCVTPSUWDr\0" + /* 64013 */ "FCVTZSUWDr\0" + /* 64024 */ "FCVTAUUWDr\0" + /* 64035 */ "FCVTMUUWDr\0" + /* 64046 */ "FCVTNUUWDr\0" + /* 64057 */ "FCVTPUUWDr\0" + /* 64068 */ "FCVTZUUWDr\0" + /* 64079 */ "FRINT32XDr\0" + /* 64090 */ "FRINT64XDr\0" + /* 64101 */ "FRINTXDr\0" + /* 64110 */ "FCVTASUXDr\0" + /* 64121 */ "FCVTMSUXDr\0" + /* 64132 */ "FCVTNSUXDr\0" + /* 64143 */ "FCVTPSUXDr\0" + /* 64154 */ "FCVTZSUXDr\0" + /* 64165 */ "FCVTAUUXDr\0" + /* 64176 */ "FCVTMUUXDr\0" + /* 64187 */ "FCVTNUUXDr\0" + /* 64198 */ "FCVTPUUXDr\0" + /* 64209 */ "FCVTZUUXDr\0" + /* 64220 */ "FMOVXDr\0" + /* 64228 */ "FRINT32ZDr\0" + /* 64239 */ "FRINT64ZDr\0" + /* 64250 */ "FRINTZDr\0" + /* 64259 */ "FRINTAHr\0" + /* 64268 */ "FCVTDHr\0" + /* 64276 */ "FNEGHr\0" + /* 64283 */ "FRINTIHr\0" + /* 64292 */ "FRINTMHr\0" + /* 64301 */ "FRINTNHr\0" + /* 64310 */ "FRINTPHr\0" + /* 64319 */ "FABSHr\0" + /* 64326 */ "FCVTSHr\0" + /* 64334 */ "FSQRTHr\0" + /* 64342 */ "FMOVHr\0" + /* 64349 */ "FCVTASUWHr\0" + /* 64360 */ "FCVTMSUWHr\0" + /* 64371 */ "FCVTNSUWHr\0" + /* 64382 */ "FCVTPSUWHr\0" + /* 64393 */ "FCVTZSUWHr\0" + /* 64404 */ "FCVTAUUWHr\0" + /* 64415 */ "FCVTMUUWHr\0" + /* 64426 */ "FCVTNUUWHr\0" + /* 64437 */ "FCVTPUUWHr\0" + /* 64448 */ "FCVTZUUWHr\0" + /* 64459 */ "FMOVWHr\0" + /* 64467 */ "FRINTXHr\0" + /* 64476 */ "FCVTASUXHr\0" + /* 64487 */ "FCVTMSUXHr\0" + /* 64498 */ "FCVTNSUXHr\0" + /* 64509 */ "FCVTPSUXHr\0" + /* 64520 */ "FCVTZSUXHr\0" + /* 64531 */ "FCVTAUUXHr\0" + /* 64542 */ "FCVTMUUXHr\0" + /* 64553 */ "FCVTNUUXHr\0" + /* 64564 */ "FCVTPUUXHr\0" + /* 64575 */ "FCVTZUUXHr\0" + /* 64586 */ "FMOVXHr\0" + /* 64594 */ "FRINTZHr\0" + /* 64603 */ "FRINTASr\0" + /* 64612 */ "FCVTDSr\0" + /* 64620 */ "FNEGSr\0" + /* 64627 */ "FCVTHSr\0" + /* 64635 */ "FRINTISr\0" + /* 64644 */ "FRINTMSr\0" + /* 64653 */ "FRINTNSr\0" + /* 64662 */ "FRINTPSr\0" + /* 64671 */ "FABSSr\0" + /* 64678 */ "FSQRTSr\0" + /* 64686 */ "FMOVSr\0" + /* 64693 */ "FCVTASUWSr\0" + /* 64704 */ "FCVTMSUWSr\0" + /* 64715 */ "FCVTNSUWSr\0" + /* 64726 */ "FCVTPSUWSr\0" + /* 64737 */ "FCVTZSUWSr\0" + /* 64748 */ "FCVTAUUWSr\0" + /* 64759 */ "FCVTMUUWSr\0" + /* 64770 */ "FCVTNUUWSr\0" + /* 64781 */ "FCVTPUUWSr\0" + /* 64792 */ "FCVTZUUWSr\0" + /* 64803 */ "FMOVWSr\0" + /* 64811 */ "FRINT32XSr\0" + /* 64822 */ "FRINT64XSr\0" + /* 64833 */ "FRINTXSr\0" + /* 64842 */ "FCVTASUXSr\0" + /* 64853 */ "FCVTMSUXSr\0" + /* 64864 */ "FCVTNSUXSr\0" + /* 64875 */ "FCVTPSUXSr\0" + /* 64886 */ "FCVTZSUXSr\0" + /* 64897 */ "FCVTAUUXSr\0" + /* 64908 */ "FCVTMUUXSr\0" + /* 64919 */ "FCVTNUUXSr\0" + /* 64930 */ "FCVTPUUXSr\0" + /* 64941 */ "FCVTZUUXSr\0" + /* 64952 */ "FRINT32ZSr\0" + /* 64963 */ "FRINT64ZSr\0" + /* 64974 */ "FRINTZSr\0" + /* 64983 */ "REV16Wr\0" + /* 64991 */ "SBCWr\0" + /* 64997 */ "ADCWr\0" + /* 65003 */ "CSINCWr\0" + /* 65011 */ "CSNEGWr\0" + /* 65019 */ "FMOVHWr\0" + /* 65027 */ "CSELWr\0" + /* 65034 */ "CCMNWr\0" + /* 65041 */ "CCMPWr\0" + /* 65048 */ "SBCSWr\0" + /* 65055 */ "ADCSWr\0" + /* 65062 */ "CLSWr\0" + /* 65068 */ "FMOVSWr\0" + /* 65076 */ "RBITWr\0" + /* 65083 */ "REVWr\0" + /* 65089 */ "SDIVWr\0" + /* 65096 */ "UDIVWr\0" + /* 65103 */ "LSLVWr\0" + /* 65110 */ "CSINVWr\0" + /* 65118 */ "RORVWr\0" + /* 65125 */ "ASRVWr\0" + /* 65132 */ "LSRVWr\0" + /* 65139 */ "CLZWr\0" + /* 65145 */ "REV32Xr\0" + /* 65153 */ "REV16Xr\0" + /* 65161 */ "SBCXr\0" + /* 65167 */ "ADCXr\0" + /* 65173 */ "CSINCXr\0" + /* 65181 */ "FMOVDXr\0" + /* 65189 */ "CSNEGXr\0" + /* 65197 */ "FMOVHXr\0" + /* 65205 */ "CSELXr\0" + /* 65212 */ "CCMNXr\0" + /* 65219 */ "CCMPXr\0" + /* 65226 */ "SBCSXr\0" + /* 65233 */ "ADCSXr\0" + /* 65240 */ "CLSXr\0" + /* 65246 */ "RBITXr\0" + /* 65253 */ "REVXr\0" + /* 65259 */ "SDIVXr\0" + /* 65266 */ "UDIVXr\0" + /* 65273 */ "LSLVXr\0" + /* 65280 */ "CSINVXr\0" + /* 65288 */ "RORVXr\0" + /* 65295 */ "ASRVXr\0" + /* 65302 */ "LSRVXr\0" + /* 65309 */ "CLZXr\0" + /* 65315 */ "MOVaddr\0" + /* 65323 */ "CompilerBarrier\0" + /* 65339 */ "FMOVXDHighr\0" + /* 65351 */ "FMOVDXHighr\0" + /* 65363 */ "DUPv2i32gpr\0" + /* 65375 */ "DUPv4i32gpr\0" + /* 65387 */ "INSvi32gpr\0" + /* 65398 */ "DUPv2i64gpr\0" + /* 65410 */ "INSvi64gpr\0" + /* 65421 */ "DUPv4i16gpr\0" + /* 65433 */ "DUPv8i16gpr\0" + /* 65445 */ "INSvi16gpr\0" + /* 65456 */ "DUPv16i8gpr\0" + /* 65468 */ "DUPv8i8gpr\0" + /* 65479 */ "INSvi8gpr\0" + /* 65489 */ "SHA256SU0rr\0" + /* 65501 */ "SHA1SU1rr\0" + /* 65511 */ "CRC32Brr\0" + /* 65520 */ "CRC32CBrr\0" + /* 65530 */ "AESIMCrr\0" + /* 65539 */ "AESMCrr\0" + /* 65547 */ "FSUBDrr\0" + /* 65555 */ "FADDDrr\0" + /* 65563 */ "FCCMPEDrr\0" + /* 65573 */ "FCMPEDrr\0" + /* 65582 */ "FMULDrr\0" + /* 65590 */ "FNMULDrr\0" + /* 65599 */ "FMINNMDrr\0" + /* 65609 */ "FMAXNMDrr\0" + /* 65619 */ "FMINDrr\0" + /* 65627 */ "FCCMPDrr\0" + /* 65636 */ "FCMPDrr\0" + /* 65644 */ "AESDrr\0" + /* 65651 */ "FDIVDrr\0" + /* 65659 */ "FMAXDrr\0" + /* 65667 */ "AESErr\0" + /* 65674 */ "SHA1Hrr\0" + /* 65682 */ "CRC32Hrr\0" + /* 65691 */ "FSUBHrr\0" + /* 65699 */ "CRC32CHrr\0" + /* 65709 */ "FADDHrr\0" + /* 65717 */ "FCCMPEHrr\0" + /* 65727 */ "FCMPEHrr\0" + /* 65736 */ "FMULHrr\0" + /* 65744 */ "FNMULHrr\0" + /* 65753 */ "SMULHrr\0" + /* 65761 */ "UMULHrr\0" + /* 65769 */ "FMINNMHrr\0" + /* 65779 */ "FMAXNMHrr\0" + /* 65789 */ "FMINHrr\0" + /* 65797 */ "FCCMPHrr\0" + /* 65806 */ "FCMPHrr\0" + /* 65814 */ "FDIVHrr\0" + /* 65822 */ "FMAXHrr\0" + /* 65830 */ "FSUBSrr\0" + /* 65838 */ "FADDSrr\0" + /* 65846 */ "FCCMPESrr\0" + /* 65856 */ "FCMPESrr\0" + /* 65865 */ "FMULSrr\0" + /* 65873 */ "FNMULSrr\0" + /* 65882 */ "FMINNMSrr\0" + /* 65892 */ "FMAXNMSrr\0" + /* 65902 */ "FMINSrr\0" + /* 65910 */ "FCCMPSrr\0" + /* 65919 */ "FCMPSrr\0" + /* 65927 */ "FDIVSrr\0" + /* 65935 */ "FMAXSrr\0" + /* 65943 */ "CRC32Wrr\0" + /* 65952 */ "SUBWrr\0" + /* 65959 */ "CRC32CWrr\0" + /* 65969 */ "BICWrr\0" + /* 65976 */ "ADDWrr\0" + /* 65983 */ "ANDWrr\0" + /* 65990 */ "EONWrr\0" + /* 65997 */ "ORNWrr\0" + /* 66004 */ "EORWrr\0" + /* 66011 */ "ORRWrr\0" + /* 66018 */ "SUBSWrr\0" + /* 66026 */ "BICSWrr\0" + /* 66034 */ "ADDSWrr\0" + /* 66042 */ "ANDSWrr\0" + /* 66050 */ "CRC32Xrr\0" + /* 66059 */ "SUBXrr\0" + /* 66066 */ "CRC32CXrr\0" + /* 66076 */ "BICXrr\0" + /* 66083 */ "ADDXrr\0" + /* 66090 */ "ANDXrr\0" + /* 66097 */ "EONXrr\0" + /* 66104 */ "ORNXrr\0" + /* 66111 */ "EORXrr\0" + /* 66118 */ "ORRXrr\0" + /* 66125 */ "SUBSXrr\0" + /* 66133 */ "BICSXrr\0" + /* 66141 */ "ADDSXrr\0" + /* 66149 */ "ANDSXrr\0" + /* 66157 */ "SHA1SU0rrr\0" + /* 66168 */ "SHA256SU1rrr\0" + /* 66181 */ "SHA256H2rrr\0" + /* 66193 */ "SHA1Crrr\0" + /* 66202 */ "FMSUBDrrr\0" + /* 66212 */ "FNMSUBDrrr\0" + /* 66223 */ "FMADDDrrr\0" + /* 66233 */ "FNMADDDrrr\0" + /* 66244 */ "FCSELDrrr\0" + /* 66254 */ "SHA256Hrrr\0" + /* 66265 */ "FMSUBHrrr\0" + /* 66275 */ "FNMSUBHrrr\0" + /* 66286 */ "FMADDHrrr\0" + /* 66296 */ "FNMADDHrrr\0" + /* 66307 */ "FCSELHrrr\0" + /* 66317 */ "SMSUBLrrr\0" + /* 66327 */ "UMSUBLrrr\0" + /* 66337 */ "SMADDLrrr\0" + /* 66347 */ "UMADDLrrr\0" + /* 66357 */ "SHA1Mrrr\0" + /* 66366 */ "SHA1Prrr\0" + /* 66375 */ "FMSUBSrrr\0" + /* 66385 */ "FNMSUBSrrr\0" + /* 66396 */ "FMADDSrrr\0" + /* 66406 */ "FNMADDSrrr\0" + /* 66417 */ "FCSELSrrr\0" + /* 66427 */ "MSUBWrrr\0" + /* 66436 */ "MADDWrrr\0" + /* 66445 */ "MSUBXrrr\0" + /* 66454 */ "MADDXrrr\0" + /* 66463 */ "TBLv16i8Four\0" + /* 66476 */ "TBXv16i8Four\0" + /* 66489 */ "TBLv8i8Four\0" + /* 66501 */ "TBXv8i8Four\0" + /* 66513 */ "LD1Rv2s\0" + /* 66521 */ "LD2Rv2s\0" + /* 66529 */ "LD3Rv2s\0" + /* 66537 */ "LD4Rv2s\0" + /* 66545 */ "LD1Threev2s\0" + /* 66557 */ "ST1Threev2s\0" + /* 66569 */ "LD3Threev2s\0" + /* 66581 */ "ST3Threev2s\0" + /* 66593 */ "LD1Onev2s\0" + /* 66603 */ "ST1Onev2s\0" + /* 66613 */ "LD1Twov2s\0" + /* 66623 */ "ST1Twov2s\0" + /* 66633 */ "LD2Twov2s\0" + /* 66643 */ "ST2Twov2s\0" + /* 66653 */ "LD1Fourv2s\0" + /* 66664 */ "ST1Fourv2s\0" + /* 66675 */ "LD4Fourv2s\0" + /* 66686 */ "ST4Fourv2s\0" + /* 66697 */ "LD1Rv4s\0" + /* 66705 */ "LD2Rv4s\0" + /* 66713 */ "LD3Rv4s\0" + /* 66721 */ "LD4Rv4s\0" + /* 66729 */ "LD1Threev4s\0" + /* 66741 */ "ST1Threev4s\0" + /* 66753 */ "LD3Threev4s\0" + /* 66765 */ "ST3Threev4s\0" + /* 66777 */ "LD1Onev4s\0" + /* 66787 */ "ST1Onev4s\0" + /* 66797 */ "LD1Twov4s\0" + /* 66807 */ "ST1Twov4s\0" + /* 66817 */ "LD2Twov4s\0" + /* 66827 */ "ST2Twov4s\0" + /* 66837 */ "LD1Fourv4s\0" + /* 66848 */ "ST1Fourv4s\0" + /* 66859 */ "LD4Fourv4s\0" + /* 66870 */ "ST4Fourv4s\0" + /* 66881 */ "SCVTFs\0" + /* 66888 */ "UCVTFs\0" + /* 66895 */ "SQSHLs\0" + /* 66902 */ "UQSHLs\0" + /* 66909 */ "SQSHRNs\0" + /* 66917 */ "UQSHRNs\0" + /* 66925 */ "SQRSHRNs\0" + /* 66934 */ "UQRSHRNs\0" + /* 66943 */ "SQSHRUNs\0" + /* 66952 */ "SQRSHRUNs\0" + /* 66962 */ "FCVTZSs\0" + /* 66970 */ "SQSHLUs\0" + /* 66978 */ "FCVTZUs\0" + /* 66986 */ "FMOVv2f32_ns\0" + /* 66999 */ "FMOVv4f32_ns\0" + /* 67012 */ "FMOVv2f64_ns\0" + /* 67025 */ "FMOVv4f16_ns\0" + /* 67038 */ "FMOVv8f16_ns\0" + /* 67051 */ "MOVIv16b_ns\0" + /* 67063 */ "MOVIv8b_ns\0" + /* 67074 */ "MOVIv2d_ns\0" + /* 67085 */ "SUBWrs\0" + /* 67092 */ "BICWrs\0" + /* 67099 */ "ADDWrs\0" + /* 67106 */ "ANDWrs\0" + /* 67113 */ "EONWrs\0" + /* 67120 */ "ORNWrs\0" + /* 67127 */ "EORWrs\0" + /* 67134 */ "ORRWrs\0" + /* 67141 */ "SUBSWrs\0" + /* 67149 */ "BICSWrs\0" + /* 67157 */ "ADDSWrs\0" + /* 67165 */ "ANDSWrs\0" + /* 67173 */ "SUBXrs\0" + /* 67180 */ "BICXrs\0" + /* 67187 */ "ADDXrs\0" + /* 67194 */ "ANDXrs\0" + /* 67201 */ "EONXrs\0" + /* 67208 */ "ORNXrs\0" + /* 67215 */ "EORXrs\0" + /* 67222 */ "ORRXrs\0" + /* 67229 */ "SUBSXrs\0" + /* 67237 */ "BICSXrs\0" + /* 67245 */ "ADDSXrs\0" + /* 67253 */ "ANDSXrs\0" + /* 67261 */ "ST2GOffset\0" + /* 67272 */ "STZ2GOffset\0" + /* 67284 */ "STGOffset\0" + /* 67294 */ "STZGOffset\0" + /* 67305 */ "SRSRAv2i32_shift\0" + /* 67322 */ "URSRAv2i32_shift\0" + /* 67339 */ "SSRAv2i32_shift\0" + /* 67355 */ "USRAv2i32_shift\0" + /* 67371 */ "SCVTFv2i32_shift\0" + /* 67388 */ "UCVTFv2i32_shift\0" + /* 67405 */ "SLIv2i32_shift\0" + /* 67420 */ "SRIv2i32_shift\0" + /* 67435 */ "SQSHLv2i32_shift\0" + /* 67452 */ "UQSHLv2i32_shift\0" + /* 67469 */ "SSHLLv2i32_shift\0" + /* 67486 */ "USHLLv2i32_shift\0" + /* 67503 */ "SQSHRNv2i32_shift\0" + /* 67521 */ "UQSHRNv2i32_shift\0" + /* 67539 */ "SQRSHRNv2i32_shift\0" + /* 67558 */ "UQRSHRNv2i32_shift\0" + /* 67577 */ "SQSHRUNv2i32_shift\0" + /* 67596 */ "SQRSHRUNv2i32_shift\0" + /* 67616 */ "SRSHRv2i32_shift\0" + /* 67633 */ "URSHRv2i32_shift\0" + /* 67650 */ "SSHRv2i32_shift\0" + /* 67666 */ "USHRv2i32_shift\0" + /* 67682 */ "FCVTZSv2i32_shift\0" + /* 67700 */ "SQSHLUv2i32_shift\0" + /* 67718 */ "FCVTZUv2i32_shift\0" + /* 67736 */ "SRSRAv4i32_shift\0" + /* 67753 */ "URSRAv4i32_shift\0" + /* 67770 */ "SSRAv4i32_shift\0" + /* 67786 */ "USRAv4i32_shift\0" + /* 67802 */ "SCVTFv4i32_shift\0" + /* 67819 */ "UCVTFv4i32_shift\0" + /* 67836 */ "SLIv4i32_shift\0" + /* 67851 */ "SRIv4i32_shift\0" + /* 67866 */ "SQSHLv4i32_shift\0" + /* 67883 */ "UQSHLv4i32_shift\0" + /* 67900 */ "SSHLLv4i32_shift\0" + /* 67917 */ "USHLLv4i32_shift\0" + /* 67934 */ "SQSHRNv4i32_shift\0" + /* 67952 */ "UQSHRNv4i32_shift\0" + /* 67970 */ "SQRSHRNv4i32_shift\0" + /* 67989 */ "UQRSHRNv4i32_shift\0" + /* 68008 */ "SQSHRUNv4i32_shift\0" + /* 68027 */ "SQRSHRUNv4i32_shift\0" + /* 68047 */ "SRSHRv4i32_shift\0" + /* 68064 */ "URSHRv4i32_shift\0" + /* 68081 */ "SSHRv4i32_shift\0" + /* 68097 */ "USHRv4i32_shift\0" + /* 68113 */ "FCVTZSv4i32_shift\0" + /* 68131 */ "SQSHLUv4i32_shift\0" + /* 68149 */ "FCVTZUv4i32_shift\0" + /* 68167 */ "SRSRAv2i64_shift\0" + /* 68184 */ "URSRAv2i64_shift\0" + /* 68201 */ "SSRAv2i64_shift\0" + /* 68217 */ "USRAv2i64_shift\0" + /* 68233 */ "SCVTFv2i64_shift\0" + /* 68250 */ "UCVTFv2i64_shift\0" + /* 68267 */ "SLIv2i64_shift\0" + /* 68282 */ "SRIv2i64_shift\0" + /* 68297 */ "SQSHLv2i64_shift\0" + /* 68314 */ "UQSHLv2i64_shift\0" + /* 68331 */ "SRSHRv2i64_shift\0" + /* 68348 */ "URSHRv2i64_shift\0" + /* 68365 */ "SSHRv2i64_shift\0" + /* 68381 */ "USHRv2i64_shift\0" + /* 68397 */ "FCVTZSv2i64_shift\0" + /* 68415 */ "SQSHLUv2i64_shift\0" + /* 68433 */ "FCVTZUv2i64_shift\0" + /* 68451 */ "SRSRAv4i16_shift\0" + /* 68468 */ "URSRAv4i16_shift\0" + /* 68485 */ "SSRAv4i16_shift\0" + /* 68501 */ "USRAv4i16_shift\0" + /* 68517 */ "SCVTFv4i16_shift\0" + /* 68534 */ "UCVTFv4i16_shift\0" + /* 68551 */ "SLIv4i16_shift\0" + /* 68566 */ "SRIv4i16_shift\0" + /* 68581 */ "SQSHLv4i16_shift\0" + /* 68598 */ "UQSHLv4i16_shift\0" + /* 68615 */ "SSHLLv4i16_shift\0" + /* 68632 */ "USHLLv4i16_shift\0" + /* 68649 */ "SQSHRNv4i16_shift\0" + /* 68667 */ "UQSHRNv4i16_shift\0" + /* 68685 */ "SQRSHRNv4i16_shift\0" + /* 68704 */ "UQRSHRNv4i16_shift\0" + /* 68723 */ "SQSHRUNv4i16_shift\0" + /* 68742 */ "SQRSHRUNv4i16_shift\0" + /* 68762 */ "SRSHRv4i16_shift\0" + /* 68779 */ "URSHRv4i16_shift\0" + /* 68796 */ "SSHRv4i16_shift\0" + /* 68812 */ "USHRv4i16_shift\0" + /* 68828 */ "FCVTZSv4i16_shift\0" + /* 68846 */ "SQSHLUv4i16_shift\0" + /* 68864 */ "FCVTZUv4i16_shift\0" + /* 68882 */ "SRSRAv8i16_shift\0" + /* 68899 */ "URSRAv8i16_shift\0" + /* 68916 */ "SSRAv8i16_shift\0" + /* 68932 */ "USRAv8i16_shift\0" + /* 68948 */ "SCVTFv8i16_shift\0" + /* 68965 */ "UCVTFv8i16_shift\0" + /* 68982 */ "SLIv8i16_shift\0" + /* 68997 */ "SRIv8i16_shift\0" + /* 69012 */ "SQSHLv8i16_shift\0" + /* 69029 */ "UQSHLv8i16_shift\0" + /* 69046 */ "SSHLLv8i16_shift\0" + /* 69063 */ "USHLLv8i16_shift\0" + /* 69080 */ "SQSHRNv8i16_shift\0" + /* 69098 */ "UQSHRNv8i16_shift\0" + /* 69116 */ "SQRSHRNv8i16_shift\0" + /* 69135 */ "UQRSHRNv8i16_shift\0" + /* 69154 */ "SQSHRUNv8i16_shift\0" + /* 69173 */ "SQRSHRUNv8i16_shift\0" + /* 69193 */ "SRSHRv8i16_shift\0" + /* 69210 */ "URSHRv8i16_shift\0" + /* 69227 */ "SSHRv8i16_shift\0" + /* 69243 */ "USHRv8i16_shift\0" + /* 69259 */ "FCVTZSv8i16_shift\0" + /* 69277 */ "SQSHLUv8i16_shift\0" + /* 69295 */ "FCVTZUv8i16_shift\0" + /* 69313 */ "SRSRAv16i8_shift\0" + /* 69330 */ "URSRAv16i8_shift\0" + /* 69347 */ "SSRAv16i8_shift\0" + /* 69363 */ "USRAv16i8_shift\0" + /* 69379 */ "SLIv16i8_shift\0" + /* 69394 */ "SRIv16i8_shift\0" + /* 69409 */ "SQSHLv16i8_shift\0" + /* 69426 */ "UQSHLv16i8_shift\0" + /* 69443 */ "SSHLLv16i8_shift\0" + /* 69460 */ "USHLLv16i8_shift\0" + /* 69477 */ "SQSHRNv16i8_shift\0" + /* 69495 */ "UQSHRNv16i8_shift\0" + /* 69513 */ "SQRSHRNv16i8_shift\0" + /* 69532 */ "UQRSHRNv16i8_shift\0" + /* 69551 */ "SQSHRUNv16i8_shift\0" + /* 69570 */ "SQRSHRUNv16i8_shift\0" + /* 69590 */ "SRSHRv16i8_shift\0" + /* 69607 */ "URSHRv16i8_shift\0" + /* 69624 */ "SSHRv16i8_shift\0" + /* 69640 */ "USHRv16i8_shift\0" + /* 69656 */ "SQSHLUv16i8_shift\0" + /* 69674 */ "SRSRAv8i8_shift\0" + /* 69690 */ "URSRAv8i8_shift\0" + /* 69706 */ "SSRAv8i8_shift\0" + /* 69721 */ "USRAv8i8_shift\0" + /* 69736 */ "SLIv8i8_shift\0" + /* 69750 */ "SRIv8i8_shift\0" + /* 69764 */ "SQSHLv8i8_shift\0" + /* 69780 */ "UQSHLv8i8_shift\0" + /* 69796 */ "SSHLLv8i8_shift\0" + /* 69812 */ "USHLLv8i8_shift\0" + /* 69828 */ "SQSHRNv8i8_shift\0" + /* 69845 */ "UQSHRNv8i8_shift\0" + /* 69862 */ "SQRSHRNv8i8_shift\0" + /* 69880 */ "UQRSHRNv8i8_shift\0" + /* 69898 */ "SQSHRUNv8i8_shift\0" + /* 69916 */ "SQRSHRUNv8i8_shift\0" + /* 69935 */ "SRSHRv8i8_shift\0" + /* 69951 */ "URSHRv8i8_shift\0" + /* 69967 */ "SSHRv8i8_shift\0" + /* 69982 */ "USHRv8i8_shift\0" + /* 69997 */ "SQSHLUv8i8_shift\0" + /* 70014 */ "LOADgot\0" + /* 70022 */ "SEH_EpilogStart\0" + /* 70038 */ "LDRBBpost\0" + /* 70048 */ "STRBBpost\0" + /* 70058 */ "LDRBpost\0" + /* 70067 */ "STRBpost\0" + /* 70076 */ "LDPDpost\0" + /* 70085 */ "STPDpost\0" + /* 70094 */ "LDRDpost\0" + /* 70103 */ "STRDpost\0" + /* 70112 */ "LDRHHpost\0" + /* 70122 */ "STRHHpost\0" + /* 70132 */ "LDRHpost\0" + /* 70141 */ "STRHpost\0" + /* 70150 */ "STGPpost\0" + /* 70159 */ "LDPQpost\0" + /* 70168 */ "STPQpost\0" + /* 70177 */ "LDRQpost\0" + /* 70186 */ "STRQpost\0" + /* 70195 */ "LDPSpost\0" + /* 70204 */ "STPSpost\0" + /* 70213 */ "LDRSpost\0" + /* 70222 */ "STRSpost\0" + /* 70231 */ "LDRSBWpost\0" + /* 70242 */ "LDRSHWpost\0" + /* 70253 */ "LDPWpost\0" + /* 70262 */ "STPWpost\0" + /* 70271 */ "LDRWpost\0" + /* 70280 */ "STRWpost\0" + /* 70289 */ "LDPSWpost\0" + /* 70299 */ "LDRSWpost\0" + /* 70309 */ "LDRSBXpost\0" + /* 70320 */ "LDRSHXpost\0" + /* 70331 */ "LDPXpost\0" + /* 70340 */ "STPXpost\0" + /* 70349 */ "LDRXpost\0" + /* 70358 */ "STRXpost\0" + /* 70367 */ "SYSLxt\0" + /* 70374 */ "SYSxt\0" + /* 70380 */ "StoreSwiftAsyncContext\0" + /* 70403 */ "ADDVv4i32v\0" + /* 70414 */ "SADDLVv4i32v\0" + /* 70427 */ "UADDLVv4i32v\0" + /* 70440 */ "FMINNMVv4i32v\0" + /* 70454 */ "FMAXNMVv4i32v\0" + /* 70468 */ "FMINVv4i32v\0" + /* 70480 */ "SMINVv4i32v\0" + /* 70492 */ "UMINVv4i32v\0" + /* 70504 */ "FMAXVv4i32v\0" + /* 70516 */ "SMAXVv4i32v\0" + /* 70528 */ "UMAXVv4i32v\0" + /* 70540 */ "ADDVv4i16v\0" + /* 70551 */ "SADDLVv4i16v\0" + /* 70564 */ "UADDLVv4i16v\0" + /* 70577 */ "FMINNMVv4i16v\0" + /* 70591 */ "FMAXNMVv4i16v\0" + /* 70605 */ "FMINVv4i16v\0" + /* 70617 */ "SMINVv4i16v\0" + /* 70629 */ "UMINVv4i16v\0" + /* 70641 */ "FMAXVv4i16v\0" + /* 70653 */ "SMAXVv4i16v\0" + /* 70665 */ "UMAXVv4i16v\0" + /* 70677 */ "ADDVv8i16v\0" + /* 70688 */ "SADDLVv8i16v\0" + /* 70701 */ "UADDLVv8i16v\0" + /* 70714 */ "FMINNMVv8i16v\0" + /* 70728 */ "FMAXNMVv8i16v\0" + /* 70742 */ "FMINVv8i16v\0" + /* 70754 */ "SMINVv8i16v\0" + /* 70766 */ "UMINVv8i16v\0" + /* 70778 */ "FMAXVv8i16v\0" + /* 70790 */ "SMAXVv8i16v\0" + /* 70802 */ "UMAXVv8i16v\0" + /* 70814 */ "ADDVv16i8v\0" + /* 70825 */ "SADDLVv16i8v\0" + /* 70838 */ "UADDLVv16i8v\0" + /* 70851 */ "SMINVv16i8v\0" + /* 70863 */ "UMINVv16i8v\0" + /* 70875 */ "SMAXVv16i8v\0" + /* 70887 */ "UMAXVv16i8v\0" + /* 70899 */ "ADDVv8i8v\0" + /* 70909 */ "SADDLVv8i8v\0" + /* 70921 */ "UADDLVv8i8v\0" + /* 70933 */ "SMINVv8i8v\0" + /* 70944 */ "UMINVv8i8v\0" + /* 70955 */ "SMAXVv8i8v\0" + /* 70966 */ "UMAXVv8i8v\0" + /* 70977 */ "BFMLALBIdx\0" + /* 70988 */ "BFMLALTIdx\0" + /* 70999 */ "ST2GPreIndex\0" + /* 71012 */ "STZ2GPreIndex\0" + /* 71026 */ "STGPreIndex\0" + /* 71038 */ "STZGPreIndex\0" + /* 71051 */ "ST2GPostIndex\0" + /* 71065 */ "STZ2GPostIndex\0" + /* 71080 */ "STGPostIndex\0" + /* 71093 */ "STZGPostIndex\0" + /* 71107 */ "SUBWrx\0" + /* 71114 */ "ADDWrx\0" + /* 71121 */ "SUBSWrx\0" + /* 71129 */ "ADDSWrx\0" + /* 71137 */ "SUBXrx\0" + /* 71144 */ "ADDXrx\0" + /* 71151 */ "SUBSXrx\0" + /* 71159 */ "ADDSXrx\0" + /* 71167 */ "RDFFR_PPz\0" + /* 71177 */ "RDFFRS_PPz\0" + /* 71188 */ "FCMGEv1i32rz\0" + /* 71201 */ "FCMLEv1i32rz\0" + /* 71214 */ "FCMEQv1i32rz\0" + /* 71227 */ "FCMGTv1i32rz\0" + /* 71240 */ "FCMLTv1i32rz\0" + /* 71253 */ "FCMGEv2i32rz\0" + /* 71266 */ "FCMLEv2i32rz\0" + /* 71279 */ "FCMEQv2i32rz\0" + /* 71292 */ "FCMGTv2i32rz\0" + /* 71305 */ "FCMLTv2i32rz\0" + /* 71318 */ "FCMGEv4i32rz\0" + /* 71331 */ "FCMLEv4i32rz\0" + /* 71344 */ "FCMEQv4i32rz\0" + /* 71357 */ "FCMGTv4i32rz\0" + /* 71370 */ "FCMLTv4i32rz\0" + /* 71383 */ "FCMGEv1i64rz\0" + /* 71396 */ "FCMLEv1i64rz\0" + /* 71409 */ "FCMEQv1i64rz\0" + /* 71422 */ "FCMGTv1i64rz\0" + /* 71435 */ "FCMLTv1i64rz\0" + /* 71448 */ "FCMGEv2i64rz\0" + /* 71461 */ "FCMLEv2i64rz\0" + /* 71474 */ "FCMEQv2i64rz\0" + /* 71487 */ "FCMGTv2i64rz\0" + /* 71500 */ "FCMLTv2i64rz\0" + /* 71513 */ "FCMGEv1i16rz\0" + /* 71526 */ "FCMLEv1i16rz\0" + /* 71539 */ "FCMEQv1i16rz\0" + /* 71552 */ "FCMGTv1i16rz\0" + /* 71565 */ "FCMLTv1i16rz\0" + /* 71578 */ "FCMGEv4i16rz\0" + /* 71591 */ "FCMLEv4i16rz\0" + /* 71604 */ "FCMEQv4i16rz\0" + /* 71617 */ "FCMGTv4i16rz\0" + /* 71630 */ "FCMLTv4i16rz\0" + /* 71643 */ "FCMGEv8i16rz\0" + /* 71656 */ "FCMLEv8i16rz\0" + /* 71669 */ "FCMEQv8i16rz\0" + /* 71682 */ "FCMGTv8i16rz\0" + /* 71695 */ "FCMLTv8i16rz\0" + /* 71708 */ "CMGEv16i8rz\0" + /* 71720 */ "CMLEv16i8rz\0" + /* 71732 */ "CMEQv16i8rz\0" + /* 71744 */ "CMGTv16i8rz\0" + /* 71756 */ "CMLTv16i8rz\0" + /* 71768 */ "CMGEv8i8rz\0" + /* 71779 */ "CMLEv8i8rz\0" + /* 71790 */ "CMEQv8i8rz\0" + /* 71801 */ "CMGTv8i8rz\0" + /* 71812 */ "CMLTv8i8rz\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern const unsigned AArch64InstrNameIndices[] = { + 35877U, 42082U, 43186U, 42280U, 40549U, 40530U, 40558U, 40748U, 28101U, + 28116U, 28018U, 28143U, 43799U, 27916U, 52347U, 28031U, 35873U, 40539U, + 27714U, 57600U, 27794U, 52267U, 20252U, 27659U, 27702U, 42376U, 40713U, + 52189U, 20311U, 42777U, 28206U, 52178U, 27817U, 42489U, 42476U, 43229U, + 52012U, 52056U, 40645U, 40692U, 40665U, 40583U, 54873U, 54903U, 18779U, + 14286U, 40835U, 54962U, 54969U, 40862U, 40869U, 40876U, 40886U, 20230U, + 43480U, 43443U, 28016U, 35875U, 56813U, 27926U, 51950U, 43696U, 52282U, + 43713U, 43395U, 18497U, 43782U, 52200U, 43635U, 52314U, 27951U, 18471U, + 20293U, 52219U, 42141U, 43254U, 18674U, 18618U, 18648U, 18659U, 18599U, + 18629U, 27867U, 27851U, 43839U, 28157U, 28174U, 18795U, 14292U, 20236U, + 20197U, 43485U, 43449U, 56711U, 42257U, 56694U, 42240U, 18746U, 14269U, + 27694U, 20265U, 51969U, 18445U, 43869U, 54887U, 18489U, 52162U, 52150U, + 52250U, 28198U, 54866U, 28130U, 54896U, 40619U, 43349U, 43327U, 40612U, + 43334U, 43628U, 40753U, 42461U, 42454U, 51960U, 42344U, 27735U, 42328U, + 27680U, 42336U, 27727U, 42320U, 27672U, 42360U, 42352U, 28653U, 28645U, + 51868U, 51858U, 51848U, 51838U, 51888U, 51878U, 56847U, 56857U, 51898U, + 51911U, 56867U, 56877U, 51924U, 51937U, 18704U, 14248U, 40777U, 13627U, + 18592U, 54941U, 40841U, 55334U, 36049U, 42796U, 4739U, 28191U, 4700U, + 0U, 28094U, 54858U, 18461U, 36017U, 36040U, 42408U, 42417U, 43646U, + 42163U, 27960U, 42114U, 42124U, 27743U, 27758U, 42092U, 42103U, 18785U, + 36957U, 42209U, 56663U, 42233U, 56687U, 43653U, 20284U, 20274U, 43181U, + 52080U, 52126U, 52105U, 43410U, 57711U, 27998U, 57677U, 27980U, 42468U, + 42385U, 27903U, 40625U, 43760U, 42273U, 52291U, 43386U, 52211U, 52237U, + 52324U, 43203U, 27781U, 18518U, 18732U, 14255U, 40805U, 54948U, 40848U, + 13633U, 52299U, 43273U, 43289U, 57591U, 27801U, 27941U, 52026U, 42368U, + 18711U, 40784U, 18687U, 40760U, 56629U, 42175U, 18763U, 40819U, 20214U, + 43465U, 43427U, 56646U, 42192U, 56670U, 42216U, 56833U, 56840U, 14760U, + 21414U, 29811U, 45034U, 66034U, 66141U, 65976U, 66083U, 14428U, 20684U, + 29153U, 44263U, 15781U, 23152U, 31376U, 46932U, 43750U, 42303U, 42762U, + 58833U, 58846U, 66042U, 66149U, 65983U, 66090U, 15657U, 22902U, 31126U, + 46682U, 14377U, 20613U, 29082U, 44192U, 14669U, 20984U, 29453U, 44563U, + 15830U, 23274U, 31498U, 47054U, 66026U, 66133U, 65969U, 66076U, 42446U, + 43216U, 12499U, 13257U, 51992U, 52001U, 14777U, 21450U, 29847U, 45070U, + 14829U, 21597U, 29958U, 45181U, 11738U, 27830U, 18422U, 27875U, 7595U, + 508U, 5054U, 11768U, 14811U, 21484U, 29881U, 45104U, 14794U, 21467U, + 29864U, 45087U, 65323U, 57572U, 65990U, 66097U, 66004U, 66111U, 40603U, + 23134U, 31358U, 46914U, 21413U, 29810U, 45033U, 20483U, 28952U, 44062U, + 22885U, 31109U, 46665U, 20683U, 29152U, 44262U, 23151U, 31375U, 46931U, + 23306U, 31530U, 47086U, 21018U, 29487U, 44597U, 23324U, 31548U, 47104U, + 20556U, 29025U, 44135U, 22991U, 31215U, 46771U, 20910U, 29379U, 44489U, + 23220U, 31444U, 47000U, 20647U, 29116U, 44226U, 23100U, 31324U, 46880U, + 21072U, 29505U, 44651U, 23341U, 31565U, 47121U, 20536U, 29005U, 44115U, + 22972U, 31196U, 46752U, 20890U, 29359U, 44469U, 23201U, 31425U, 46981U, + 20576U, 29045U, 44155U, 23010U, 31234U, 46790U, 20930U, 29399U, 44509U, + 23239U, 31463U, 47019U, 21126U, 29559U, 44705U, 21165U, 29598U, 44744U, + 9U, 16U, 23U, 23358U, 31582U, 47138U, 20518U, 28987U, 44097U, + 22955U, 31179U, 46735U, 20872U, 29341U, 44451U, 23184U, 31408U, 46964U, + 21260U, 29693U, 44880U, 21145U, 29578U, 44724U, 21184U, 29617U, 44763U, + 21557U, 29918U, 45141U, 21204U, 29637U, 44783U, 21333U, 29730U, 44953U, + 21353U, 29750U, 44973U, 21373U, 29770U, 44993U, 21393U, 29790U, 45013U, + 21577U, 29938U, 45161U, 21614U, 29975U, 45198U, 21502U, 29899U, 45122U, + 20594U, 29063U, 44173U, 23027U, 31251U, 46807U, 23256U, 31480U, 47036U, + 20465U, 28934U, 44044U, 22868U, 31092U, 46648U, 20665U, 29134U, 44244U, + 23117U, 31341U, 46897U, 20412U, 41136U, 55498U, 55923U, 41704U, 55711U, + 56136U, 18543U, 41029U, 18811U, 55463U, 19027U, 55888U, 19609U, 21634U, + 41254U, 18867U, 55569U, 19121U, 55994U, 19703U, 41822U, 55782U, 19409U, + 56207U, 19991U, 20437U, 41199U, 55539U, 55964U, 41767U, 55752U, 56177U, + 21659U, 41317U, 18913U, 55610U, 19202U, 56035U, 19784U, 41885U, 55823U, + 19490U, 56248U, 20072U, 23770U, 41459U, 18993U, 55681U, 19327U, 56106U, + 19909U, 23745U, 41396U, 18947U, 55640U, 19246U, 56065U, 19828U, 41940U, + 55853U, 19553U, 56278U, 20135U, 20420U, 41148U, 55511U, 55936U, 41716U, + 55724U, 56149U, 18549U, 41039U, 18824U, 55474U, 19045U, 55899U, 19627U, + 21642U, 41266U, 18882U, 55582U, 19141U, 56007U, 19723U, 41834U, 55795U, + 19429U, 56220U, 20011U, 20446U, 41212U, 55553U, 55978U, 41780U, 55766U, + 56191U, 21668U, 41330U, 18929U, 55624U, 19223U, 56049U, 19805U, 41898U, + 55837U, 19511U, 56262U, 20093U, 23779U, 41472U, 19009U, 55695U, 19348U, + 56120U, 19930U, 23753U, 41408U, 18962U, 55653U, 19266U, 56078U, 19848U, + 41950U, 55864U, 19571U, 56289U, 20153U, 55324U, 42756U, 7517U, 437U, + 4983U, 11751U, 54917U, 42921U, 57684U, 27773U, 57659U, 52035U, 57693U, + 57668U, 57702U, 7579U, 492U, 5038U, 28050U, 257U, 4717U, 28058U, + 271U, 4747U, 43319U, 43341U, 264U, 4732U, 61457U, 61468U, 43816U, + 43659U, 63477U, 11722U, 4684U, 13518U, 41137U, 41594U, 40912U, 41705U, + 41030U, 41255U, 41501U, 41823U, 41200U, 41641U, 41768U, 41318U, 41886U, + 41460U, 41397U, 41941U, 13693U, 20421U, 28892U, 44002U, 18550U, 28232U, + 21643U, 45225U, 20447U, 28916U, 44026U, 21669U, 45249U, 23780U, 54987U, + 23754U, 41162U, 41605U, 40921U, 41730U, 41051U, 41280U, 41510U, 41848U, + 41227U, 41653U, 41795U, 41345U, 41913U, 41487U, 41422U, 41962U, 36135U, + 36115U, 36093U, 70014U, 14360U, 20501U, 28970U, 44080U, 14599U, 20855U, + 29324U, 44434U, 15797U, 23168U, 31392U, 46948U, 14394U, 20630U, 29099U, + 44209U, 14686U, 21001U, 29470U, 44580U, 15846U, 23290U, 31514U, 47070U, + 63607U, 65315U, 13567U, 42398U, 54923U, 52087U, 43739U, 43728U, 63587U, + 63597U, 14616U, 20873U, 29342U, 44452U, 14741U, 21261U, 29694U, 44881U, + 14812U, 21485U, 29882U, 45105U, 65997U, 66104U, 66011U, 66118U, 42803U, + 71167U, 43373U, 21036U, 44615U, 42426U, 60873U, 70022U, 63854U, 60887U, + 43360U, 57301U, 61432U, 42811U, 57270U, 57316U, 61445U, 42825U, 57286U, + 57331U, 42436U, 58402U, 14703U, 21090U, 29523U, 44669U, 14633U, 20948U, + 29417U, 44527U, 14445U, 20701U, 29170U, 44280U, 27688U, 14758U, 21431U, + 29828U, 45051U, 14739U, 21278U, 29711U, 44898U, 14521U, 20777U, 29246U, + 44356U, 15746U, 23081U, 31305U, 46861U, 15674U, 22919U, 31143U, 46699U, + 14483U, 20739U, 29208U, 44318U, 14561U, 20817U, 29286U, 44396U, 15710U, + 23045U, 31269U, 46825U, 63862U, 63448U, 36144U, 36125U, 36104U, 63870U, + 63462U, 15813U, 23257U, 31481U, 47037U, 66018U, 66125U, 65952U, 66059U, + 14411U, 20666U, 29135U, 44245U, 15765U, 23118U, 31342U, 46898U, 21224U, + 29657U, 44803U, 21297U, 44917U, 21521U, 13861U, 13891U, 56389U, 57345U, + 70380U, 63486U, 62588U, 62905U, 40734U, 36026U, 40633U, 42929U, 21054U, + 44633U, 14721U, 21108U, 29541U, 44687U, 14651U, 20966U, 29435U, 44545U, + 14464U, 20720U, 29189U, 44299U, 14541U, 20797U, 29266U, 44376U, 15692U, + 22937U, 31161U, 46717U, 14502U, 20758U, 29227U, 44337U, 44839U, 14580U, + 20836U, 29305U, 44415U, 15728U, 23063U, 31287U, 46843U, 44859U, 21242U, + 29675U, 44821U, 21315U, 44935U, 21539U, 18272U, 27126U, 35435U, 51295U, + 12560U, 5963U, 2834U, 6467U, 10075U, 3689U, 10884U, 13312U, 24682U, + 48410U, 25387U, 49186U, 65055U, 65233U, 64997U, 65167U, 28085U, 24042U, + 47769U, 16779U, 32872U, 48571U, 17114U, 33626U, 49347U, 2940U, 3795U, + 10181U, 10990U, 12724U, 13460U, 36073U, 17984U, 26745U, 35080U, 50914U, + 12467U, 2759U, 6445U, 63727U, 10000U, 3614U, 10809U, 13228U, 63128U, + 67157U, 71129U, 63203U, 67245U, 71159U, 7415U, 24055U, 47782U, 36083U, + 70814U, 70540U, 70403U, 70677U, 70899U, 63076U, 67099U, 71114U, 63151U, + 67187U, 71144U, 7396U, 15288U, 22396U, 30620U, 46184U, 17681U, 26319U, + 34642U, 50411U, 16830U, 24955U, 32999U, 48698U, 12160U, 5729U, 2378U, + 6294U, 9644U, 3233U, 10453U, 12950U, 43199U, 42719U, 48U, 316U, + 4770U, 4863U, 98U, 366U, 4820U, 4913U, 64U, 332U, 4786U, + 4879U, 81U, 349U, 4803U, 4896U, 16852U, 65644U, 16908U, 65667U, + 17185U, 65530U, 17197U, 65539U, 63136U, 67165U, 63211U, 67253U, 42664U, + 16520U, 24156U, 32321U, 47895U, 63083U, 67106U, 63158U, 67194U, 42576U, + 36332U, 17760U, 26424U, 34747U, 50516U, 57823U, 12227U, 13011U, 15516U, + 22649U, 30873U, 46437U, 18224U, 27040U, 35375U, 51209U, 65125U, 65295U, + 17787U, 34774U, 50543U, 16878U, 33048U, 48758U, 15591U, 22789U, 31013U, + 46577U, 18248U, 27064U, 35399U, 51233U, 15145U, 22326U, 30461U, 46025U, + 13583U, 13930U, 13653U, 14331U, 13601U, 7464U, 42732U, 57625U, 13942U, + 7484U, 42748U, 57652U, 13667U, 14345U, 28073U, 13691U, 56616U, 57760U, + 17039U, 25135U, 33224U, 48934U, 17127U, 25631U, 33691U, 49445U, 9128U, + 9158U, 54852U, 42296U, 4724U, 57913U, 57926U, 36301U, 57859U, 9116U, + 9146U, 13957U, 70977U, 52097U, 70988U, 13607U, 36288U, 57802U, 36319U, + 57879U, 57770U, 63091U, 63166U, 17076U, 25172U, 33261U, 48971U, 67149U, + 67237U, 42652U, 67092U, 67180U, 42565U, 17643U, 26270U, 34593U, 50362U, + 57815U, 12128U, 2346U, 9612U, 3201U, 10421U, 12921U, 12246U, 13028U, + 12608U, 13355U, 40527U, 43356U, 13554U, 57611U, 13800U, 57638U, 43183U, + 13549U, 57605U, 13795U, 57632U, 40725U, 36945U, 36953U, 42888U, 42838U, + 42858U, 42899U, 42848U, 42868U, 42910U, 42878U, 42626U, 42541U, 42639U, + 42553U, 57738U, 57749U, 57729U, 12385U, 13154U, 58398U, 15094U, 22275U, + 30410U, 45974U, 13822U, 28330U, 14010U, 28547U, 55185U, 56949U, 55084U, + 56774U, 14224U, 28773U, 14094U, 28631U, 55276U, 57040U, 55152U, 56916U, + 55055U, 56745U, 55247U, 57011U, 55341U, 57088U, 55451U, 57198U, 56361U, + 57258U, 56351U, 57248U, 62301U, 65034U, 62489U, 65212U, 62321U, 65041U, + 62509U, 65219U, 22153U, 45763U, 25546U, 49360U, 54976U, 16444U, 24068U, + 32221U, 47795U, 16470U, 24106U, 32259U, 47833U, 16590U, 24278U, 32443U, + 48017U, 16457U, 24081U, 32234U, 47808U, 16483U, 24119U, 32272U, 47846U, + 16603U, 24291U, 32456U, 48030U, 56827U, 65062U, 65240U, 18283U, 27150U, + 35459U, 51319U, 12579U, 2853U, 10094U, 3708U, 10903U, 13329U, 65139U, + 65309U, 18368U, 27373U, 35622U, 51506U, 12696U, 2912U, 10153U, 3767U, + 10962U, 13434U, 12530U, 71732U, 5939U, 71410U, 2813U, 71280U, 6455U, + 71475U, 10054U, 71605U, 3668U, 71345U, 10863U, 71670U, 13285U, 71790U, + 12236U, 71708U, 5750U, 71384U, 2445U, 71254U, 6315U, 71449U, 9711U, + 71579U, 3300U, 71319U, 10520U, 71644U, 13019U, 71768U, 12597U, 71744U, + 6030U, 71423U, 2871U, 71293U, 6486U, 71488U, 10112U, 71618U, 3726U, + 71358U, 10921U, 71683U, 13345U, 71801U, 12266U, 5818U, 2546U, 6336U, + 9787U, 3401U, 10596U, 13046U, 12569U, 5972U, 2843U, 6476U, 10084U, + 3698U, 10893U, 13320U, 30096U, 45360U, 16753U, 24554U, 32606U, 48282U, + 71720U, 71397U, 71267U, 71462U, 71592U, 71332U, 71657U, 71779U, 71756U, + 71436U, 71306U, 71501U, 71631U, 71371U, 71696U, 71812U, 15446U, 22555U, + 30779U, 46343U, 17549U, 26057U, 34396U, 50149U, 17397U, 34174U, 49942U, + 15376U, 22485U, 30709U, 46273U, 17492U, 25973U, 34297U, 50065U, 17302U, + 34079U, 49847U, 15488U, 22597U, 30821U, 46385U, 17577U, 26113U, 34452U, + 50205U, 17454U, 34231U, 49999U, 15418U, 22527U, 30751U, 46315U, 17535U, + 26015U, 34354U, 50107U, 17359U, 34136U, 49904U, 15460U, 22569U, 30793U, + 46357U, 17563U, 26071U, 34410U, 50163U, 17416U, 34193U, 49961U, 15390U, + 22499U, 30723U, 46287U, 17321U, 34098U, 49866U, 15432U, 22541U, 30765U, + 46329U, 17378U, 34155U, 49923U, 15474U, 22583U, 30807U, 46371U, 17435U, + 34212U, 49980U, 15502U, 22611U, 30835U, 46399U, 17473U, 34250U, 50018U, + 15404U, 22513U, 30737U, 46301U, 17506U, 26001U, 34325U, 50093U, 17340U, + 34117U, 49885U, 12656U, 6040U, 2881U, 6496U, 10122U, 3736U, 10931U, + 13398U, 18317U, 27184U, 35493U, 51353U, 36617U, 36675U, 36733U, 15928U, + 23442U, 31666U, 47222U, 36791U, 18306U, 27173U, 35482U, 51342U, 12617U, + 13363U, 24317U, 48056U, 15627U, 22838U, 31062U, 46626U, 16069U, 23631U, + 31855U, 47403U, 16181U, 23734U, 31958U, 47506U, 15638U, 22849U, 31073U, + 46637U, 11706U, 4643U, 7333U, 13504U, 65511U, 65520U, 65699U, 65959U, + 66066U, 65682U, 65943U, 66050U, 65027U, 65205U, 65003U, 65173U, 65110U, + 65280U, 65011U, 65189U, 56324U, 57237U, 56313U, 57226U, 278U, 4754U, + 4857U, 36571U, 36629U, 36803U, 36687U, 36851U, 15974U, 23488U, 31712U, + 47268U, 23536U, 31760U, 47316U, 36745U, 36899U, 14126U, 43773U, 14229U, + 43896U, 36339U, 15337U, 22446U, 30670U, 46234U, 16050U, 23612U, 31836U, + 47384U, 15135U, 22316U, 30451U, 43010U, 46015U, 65456U, 61102U, 65363U, + 61001U, 65398U, 61039U, 65421U, 61064U, 65375U, 61014U, 65433U, 61077U, + 65468U, 61115U, 67113U, 67201U, 4852U, 57718U, 17087U, 25270U, 33359U, + 49069U, 42686U, 16792U, 24855U, 32899U, 48598U, 16555U, 24231U, 32396U, + 47970U, 63106U, 67127U, 63181U, 67215U, 42596U, 36347U, 18202U, 27018U, + 35353U, 51187U, 57843U, 12540U, 13294U, 51987U, 13560U, 13828U, 14846U, + 21679U, 29995U, 42945U, 45259U, 16116U, 23669U, 31893U, 43020U, 47441U, + 63219U, 63228U, 36311U, 15254U, 12667U, 13408U, 7494U, 414U, 4960U, + 26281U, 34604U, 50373U, 563U, 5109U, 7831U, 1199U, 8507U, 63939U, + 64319U, 64671U, 27125U, 35434U, 51294U, 859U, 5393U, 8137U, 1495U, + 8813U, 7501U, 421U, 4967U, 25945U, 34269U, 50037U, 594U, 5140U, + 7862U, 1230U, 8538U, 7563U, 476U, 5022U, 26085U, 34424U, 50177U, + 952U, 5486U, 8230U, 1588U, 8906U, 24094U, 32247U, 47821U, 65555U, + 65709U, 25844U, 33978U, 49746U, 765U, 5299U, 63790U, 63662U, 63726U, + 8043U, 1401U, 8719U, 65838U, 24132U, 32285U, 47859U, 22637U, 30861U, + 46425U, 26330U, 34653U, 50422U, 24954U, 32998U, 48697U, 584U, 5130U, + 7852U, 1220U, 8528U, 26317U, 34640U, 50409U, 573U, 5119U, 7841U, + 1209U, 8517U, 65627U, 65563U, 65717U, 65846U, 65797U, 65910U, 7536U, + 449U, 4995U, 20370U, 28843U, 43953U, 26043U, 34382U, 50135U, 71539U, + 71214U, 71409U, 836U, 5370U, 71279U, 71474U, 8114U, 1472U, 71604U, + 71344U, 8790U, 71669U, 7509U, 429U, 4975U, 20328U, 28801U, 43911U, + 25959U, 34283U, 50051U, 71513U, 71188U, 71383U, 605U, 5151U, 71253U, + 71448U, 7873U, 1241U, 71578U, 71318U, 8549U, 71643U, 7571U, 484U, + 5030U, 20384U, 28857U, 43967U, 26099U, 34438U, 50191U, 71552U, 71227U, + 71422U, 963U, 5497U, 71292U, 71487U, 8241U, 1599U, 71617U, 71357U, + 8917U, 71682U, 25749U, 33883U, 49651U, 30095U, 45359U, 520U, 5066U, + 7788U, 60005U, 1156U, 58884U, 8464U, 60024U, 20342U, 28815U, 43925U, + 71526U, 71201U, 71396U, 71266U, 71461U, 71591U, 71331U, 71656U, 20398U, + 28871U, 43981U, 71565U, 71240U, 71435U, 71305U, 71500U, 71630U, 71370U, + 71695U, 20356U, 28829U, 43939U, 25987U, 34311U, 50079U, 62608U, 65636U, + 62599U, 65573U, 62752U, 65727U, 62916U, 65856U, 62761U, 65806U, 62925U, + 65919U, 26029U, 34368U, 50121U, 22837U, 31061U, 46625U, 66244U, 66307U, + 66417U, 63969U, 64349U, 64693U, 64110U, 64476U, 64842U, 7632U, 2045U, + 5949U, 847U, 5381U, 8125U, 1483U, 8801U, 64024U, 64404U, 64748U, + 64165U, 64531U, 64897U, 7692U, 2116U, 6051U, 985U, 5519U, 8263U, + 1621U, 8939U, 64268U, 64612U, 63895U, 64627U, 51723U, 27605U, 2674U, + 9915U, 3529U, 10724U, 63980U, 64360U, 64704U, 64121U, 64487U, 64853U, + 7644U, 2068U, 5982U, 879U, 5413U, 8157U, 1515U, 8833U, 64035U, + 64415U, 64759U, 64176U, 64542U, 64908U, 7704U, 2128U, 6063U, 997U, + 5531U, 8275U, 1633U, 8951U, 63991U, 64371U, 64715U, 64132U, 64498U, + 64864U, 7656U, 2080U, 5994U, 891U, 5425U, 8169U, 1527U, 8845U, + 51623U, 35835U, 64046U, 64426U, 64770U, 64187U, 64553U, 64919U, 7716U, + 2140U, 6075U, 1009U, 5543U, 8287U, 1645U, 8963U, 2714U, 9955U, + 3569U, 10764U, 64002U, 64382U, 64726U, 64143U, 64509U, 64875U, 7668U, + 2092U, 6006U, 915U, 5449U, 8193U, 1551U, 8869U, 64057U, 64437U, + 64781U, 64198U, 64564U, 64930U, 7728U, 2152U, 6087U, 1021U, 5555U, + 8299U, 1657U, 8975U, 63946U, 64326U, 51640U, 5927U, 753U, 1389U, + 51690U, 62638U, 62791U, 62955U, 62706U, 62859U, 63023U, 64013U, 64393U, + 64737U, 64154U, 64520U, 64886U, 27473U, 51606U, 27507U, 35769U, 51706U, + 27588U, 51804U, 58809U, 61928U, 66962U, 7680U, 2104U, 6018U, 940U, + 5474U, 67682U, 68397U, 8218U, 1576U, 68828U, 68113U, 8894U, 69259U, + 62650U, 62803U, 62967U, 62718U, 62871U, 63035U, 64068U, 64448U, 64792U, + 64209U, 64575U, 64941U, 27490U, 51673U, 27539U, 35786U, 51755U, 27637U, + 51821U, 58825U, 61944U, 66978U, 7740U, 2164U, 6099U, 1033U, 5567U, + 67718U, 68433U, 8311U, 1669U, 68864U, 68149U, 8987U, 69295U, 35722U, + 51658U, 27524U, 51740U, 27622U, 35852U, 65651U, 65814U, 27086U, 35421U, + 51255U, 65927U, 27209U, 35518U, 51378U, 1045U, 5579U, 8323U, 1681U, + 8999U, 22445U, 30669U, 46233U, 25652U, 33712U, 49480U, 43903U, 26157U, + 34480U, 50249U, 66223U, 66286U, 66396U, 25817U, 33951U, 49719U, 65659U, + 65822U, 65609U, 65779U, 25874U, 34008U, 49776U, 789U, 5323U, 63816U, + 63688U, 63752U, 8067U, 1425U, 8743U, 65892U, 24181U, 32346U, 47920U, + 70591U, 70454U, 70728U, 22724U, 30948U, 46512U, 26667U, 35002U, 50836U, + 707U, 5253U, 7997U, 1343U, 8673U, 25904U, 34038U, 49806U, 825U, + 5359U, 63842U, 63714U, 63778U, 8103U, 1461U, 8779U, 65935U, 24242U, + 32407U, 47981U, 70641U, 70504U, 70778U, 22825U, 31049U, 46613U, 27281U, + 35530U, 51414U, 1083U, 5617U, 8333U, 1719U, 9009U, 65619U, 65789U, + 65599U, 65769U, 25858U, 33992U, 49760U, 776U, 5310U, 63802U, 63674U, + 63738U, 8054U, 1412U, 8730U, 65882U, 24167U, 32332U, 47906U, 70577U, + 70440U, 70714U, 22710U, 30934U, 46498U, 26653U, 34988U, 50822U, 695U, + 5241U, 7985U, 1331U, 8661U, 25890U, 34024U, 49792U, 802U, 5336U, + 63830U, 63702U, 63766U, 8080U, 1438U, 8756U, 65902U, 24195U, 32360U, + 47934U, 70605U, 70468U, 70742U, 22738U, 30962U, 46526U, 26695U, 35030U, + 50864U, 731U, 5277U, 8021U, 1367U, 8697U, 8378U, 9054U, 7764U, + 8440U, 28369U, 28433U, 28401U, 28463U, 8410U, 9086U, 7953U, 8629U, + 25763U, 33897U, 49665U, 21779U, 30108U, 45372U, 60043U, 58903U, 59796U, + 531U, 5077U, 59082U, 59932U, 7799U, 1167U, 60159U, 59419U, 8475U, + 60496U, 8394U, 9070U, 7776U, 8452U, 28385U, 28448U, 28417U, 28478U, + 8425U, 9101U, 7964U, 8640U, 25918U, 34052U, 49820U, 22009U, 30223U, + 45619U, 60122U, 59045U, 59895U, 869U, 5403U, 59382U, 59968U, 8147U, + 1505U, 60459U, 59719U, 8823U, 60796U, 24565U, 48293U, 24331U, 48070U, + 24375U, 48114U, 65351U, 65181U, 62053U, 63962U, 65019U, 65197U, 62121U, + 64342U, 65068U, 62229U, 64686U, 64459U, 64803U, 65339U, 64220U, 64586U, + 66986U, 67012U, 67025U, 66999U, 67038U, 25790U, 33924U, 49692U, 66202U, + 66265U, 66375U, 65582U, 65736U, 65865U, 7587U, 500U, 5046U, 27332U, + 35581U, 51465U, 60140U, 59063U, 59913U, 1093U, 5627U, 59400U, 59986U, + 8343U, 1729U, 60477U, 59737U, 9019U, 60814U, 22698U, 30922U, 46486U, + 26641U, 34976U, 50810U, 21986U, 30200U, 45596U, 25111U, 33200U, 48910U, + 60104U, 59027U, 59877U, 685U, 5231U, 59364U, 59950U, 7975U, 1321U, + 60441U, 59701U, 8651U, 60778U, 63888U, 64276U, 64620U, 26449U, 34820U, + 50618U, 663U, 5209U, 7931U, 1299U, 8607U, 66233U, 66296U, 66406U, + 25830U, 33964U, 49732U, 25776U, 33910U, 49678U, 25931U, 34065U, 49833U, + 25803U, 33937U, 49705U, 66212U, 66275U, 66385U, 65590U, 65744U, 65873U, + 25663U, 33760U, 49528U, 7607U, 1852U, 5760U, 616U, 5162U, 7884U, + 1252U, 8560U, 7544U, 457U, 5003U, 25183U, 33272U, 48982U, 903U, + 5437U, 8181U, 1539U, 8857U, 27345U, 35594U, 51478U, 7752U, 2176U, + 6111U, 64079U, 64811U, 1055U, 5589U, 1691U, 64228U, 64952U, 1116U, + 5650U, 1752U, 64090U, 64822U, 1069U, 5603U, 1705U, 64239U, 64963U, + 1130U, 5664U, 1766U, 63879U, 64259U, 64603U, 26143U, 34466U, 50235U, + 541U, 5087U, 7809U, 1177U, 8485U, 63903U, 64283U, 64635U, 26536U, + 34871U, 50705U, 673U, 5219U, 7941U, 1309U, 8617U, 63912U, 64292U, + 64644U, 26681U, 35016U, 50850U, 719U, 5265U, 8009U, 1355U, 8685U, + 63921U, 64301U, 64653U, 26731U, 35066U, 50900U, 741U, 5287U, 8031U, + 1377U, 8707U, 63930U, 64310U, 64662U, 26811U, 35146U, 50980U, 813U, + 5347U, 8091U, 1449U, 8767U, 64101U, 64467U, 64833U, 27359U, 35608U, + 51492U, 1104U, 5638U, 8354U, 1740U, 9030U, 64250U, 64594U, 64974U, + 27384U, 35633U, 51517U, 1144U, 5678U, 8366U, 1780U, 9042U, 25675U, + 33772U, 49540U, 7619U, 1864U, 5772U, 628U, 5174U, 7896U, 1264U, + 8572U, 7553U, 466U, 5012U, 25196U, 33285U, 48995U, 927U, 5461U, + 8205U, 1563U, 8881U, 26435U, 34806U, 50575U, 63954U, 64334U, 64678U, + 27196U, 35505U, 51365U, 974U, 5508U, 8252U, 1610U, 8928U, 65547U, + 65691U, 22750U, 30974U, 46538U, 26851U, 35186U, 51020U, 65830U, 22625U, + 30849U, 46413U, 26194U, 34517U, 50286U, 24867U, 32911U, 48610U, 553U, + 5099U, 7821U, 1189U, 8497U, 22261U, 30396U, 45960U, 25122U, 33211U, + 48921U, 25098U, 33187U, 48897U, 38664U, 38131U, 39630U, 40088U, 39097U, + 39864U, 40322U, 38616U, 36979U, 37014U, 39596U, 37303U, 40054U, 37717U, + 38775U, 38202U, 37131U, 39708U, 37351U, 40166U, 37765U, 39208U, 39942U, + 37563U, 40400U, 37977U, 38718U, 38172U, 39668U, 40126U, 39151U, 39902U, + 40360U, 38829U, 38243U, 37173U, 39746U, 37403U, 40204U, 37817U, 39262U, + 39980U, 37615U, 40438U, 38029U, 38940U, 38515U, 37259U, 39824U, 37509U, + 40282U, 37923U, 38886U, 38474U, 37217U, 39786U, 37457U, 40244U, 37871U, + 39319U, 40020U, 37669U, 40478U, 38083U, 38681U, 38144U, 39648U, 40106U, + 39114U, 39882U, 40340U, 38631U, 36990U, 37032U, 39612U, 37326U, 40070U, + 37740U, 38792U, 38215U, 37151U, 39726U, 37376U, 40184U, 37790U, 39225U, + 39960U, 37588U, 40418U, 38002U, 38736U, 38186U, 39687U, 40145U, 39169U, + 39921U, 40379U, 38847U, 38257U, 37194U, 39765U, 37429U, 40223U, 37843U, + 39280U, 39999U, 37641U, 40457U, 38055U, 38958U, 38529U, 37280U, 39843U, + 37535U, 40301U, 37949U, 38903U, 38487U, 37237U, 39804U, 37482U, 40262U, + 37896U, 39334U, 40036U, 37692U, 40494U, 38106U, 35881U, 52173U, 26127U, + 50219U, 57831U, 52146U, 18535U, 36595U, 36653U, 36827U, 36711U, 36875U, + 15998U, 23512U, 31736U, 47292U, 23560U, 31784U, 47340U, 36769U, 36923U, + 14911U, 21744U, 30060U, 45324U, 16028U, 23590U, 31814U, 47362U, 14935U, + 21768U, 30084U, 45348U, 16039U, 23601U, 31825U, 47373U, 14894U, 21727U, + 30043U, 42993U, 45307U, 16164U, 23717U, 31941U, 43068U, 47489U, 16059U, + 23621U, 31845U, 47393U, 16106U, 23659U, 31883U, 47431U, 65445U, 61090U, + 65387U, 61027U, 65410U, 61052U, 65479U, 61127U, 28223U, 14233U, 16445U, + 24069U, 32222U, 47796U, 16471U, 24107U, 32260U, 47834U, 16458U, 24082U, + 32235U, 47809U, 16484U, 24120U, 32273U, 47847U, 13688U, 20413U, 38665U, + 28885U, 39027U, 38586U, 43995U, 39098U, 18544U, 38617U, 58091U, 52962U, + 58513U, 53450U, 58675U, 53692U, 66653U, 54514U, 61619U, 53966U, 66837U, + 54788U, 58279U, 53240U, 61803U, 54240U, 28227U, 21635U, 38776U, 38997U, + 45218U, 39209U, 58025U, 52866U, 58473U, 53390U, 58615U, 53602U, 66593U, + 54424U, 61559U, 53876U, 66777U, 54698U, 58219U, 53150U, 61743U, 54150U, + 41187U, 41629U, 40995U, 41755U, 41126U, 41305U, 41584U, 41873U, 15649U, + 41005U, 22860U, 41372U, 31084U, 41680U, 56373U, 42058U, 16020U, 41017U, + 23582U, 41384U, 31806U, 41692U, 56381U, 42070U, 41241U, 41667U, 41809U, + 41359U, 41927U, 42047U, 41447U, 42037U, 57937U, 52738U, 58417U, 53304U, + 58535U, 53482U, 66513U, 54304U, 61479U, 53756U, 66697U, 54578U, 58139U, + 53030U, 61663U, 54030U, 20438U, 38719U, 28908U, 39061U, 44018U, 39152U, + 21660U, 38830U, 45241U, 39263U, 23771U, 38941U, 57973U, 52794U, 58449U, + 53356U, 58567U, 53534U, 66545U, 54356U, 61511U, 53808U, 66729U, 54630U, + 58171U, 53082U, 61695U, 54082U, 58047U, 52898U, 58493U, 53420U, 58635U, + 53632U, 66613U, 54454U, 61579U, 53906U, 66797U, 54728U, 58239U, 53180U, + 61763U, 54180U, 54982U, 23746U, 38887U, 39320U, 14864U, 21697U, 30013U, + 42963U, 45277U, 16134U, 23687U, 31911U, 43038U, 47459U, 9176U, 52554U, + 1792U, 52362U, 5690U, 52458U, 11779U, 52650U, 13713U, 40941U, 18562U, + 41072U, 28252U, 41530U, 57946U, 52752U, 58425U, 53317U, 58543U, 53495U, + 66521U, 54317U, 61487U, 53769U, 66705U, 54591U, 58147U, 53043U, 61671U, + 54043U, 58069U, 52930U, 58655U, 53662U, 66633U, 54484U, 61599U, 53936U, + 66817U, 54758U, 58259U, 53210U, 61783U, 54210U, 54999U, 41983U, 9415U, + 52578U, 2188U, 52386U, 6195U, 52482U, 11926U, 52672U, 13731U, 40959U, + 18572U, 41090U, 28262U, 41548U, 57955U, 52766U, 58433U, 53330U, 58551U, + 53508U, 66529U, 54330U, 61495U, 53782U, 66713U, 54604U, 58155U, 53056U, + 61679U, 54056U, 57999U, 52830U, 58591U, 53568U, 66569U, 54390U, 61535U, + 53842U, 66753U, 54664U, 58195U, 53116U, 61719U, 54116U, 55009U, 42001U, + 9429U, 52602U, 3029U, 52410U, 7305U, 52506U, 11938U, 52694U, 13753U, + 40977U, 18582U, 41108U, 58115U, 52996U, 58697U, 53724U, 66675U, 54546U, + 61641U, 53998U, 66859U, 54820U, 58301U, 53272U, 61825U, 54272U, 28272U, + 41566U, 57964U, 52780U, 58441U, 53343U, 58559U, 53521U, 66537U, 54343U, + 61503U, 53795U, 66721U, 54617U, 58163U, 53069U, 61687U, 54069U, 55019U, + 42019U, 9443U, 52626U, 3043U, 52434U, 7319U, 52530U, 11950U, 52716U, + 13741U, 13763U, 28282U, 13948U, 28493U, 55123U, 56887U, 55029U, 56621U, + 13923U, 28362U, 14046U, 28583U, 55221U, 56985U, 55116U, 56806U, 14191U, + 28740U, 55418U, 57165U, 61997U, 62105U, 62254U, 62442U, 62283U, 62471U, + 62407U, 62565U, 62181U, 14151U, 28700U, 55378U, 57125U, 55352U, 57099U, + 14198U, 28747U, 55425U, 57172U, 13806U, 28314U, 13992U, 28529U, 55167U, + 56931U, 55068U, 56758U, 14164U, 28713U, 14078U, 28615U, 55260U, 57024U, + 55391U, 57138U, 13814U, 28322U, 14001U, 28538U, 55176U, 56940U, 55076U, + 56766U, 14184U, 28733U, 14086U, 28623U, 55268U, 57032U, 55411U, 57158U, + 38145U, 38557U, 36967U, 39380U, 36991U, 38216U, 38545U, 39409U, 38187U, + 38571U, 39394U, 38258U, 39423U, 38530U, 38488U, 39584U, 28090U, 40896U, + 14157U, 28706U, 55384U, 57131U, 38700U, 39043U, 38600U, 39133U, 38648U, + 38811U, 39011U, 39244U, 38756U, 39078U, 39189U, 38867U, 39300U, 38978U, + 38922U, 39351U, 62019U, 62147U, 62195U, 62328U, 62516U, 35929U, 43536U, + 38273U, 39438U, 35951U, 43558U, 38328U, 35973U, 43580U, 38364U, 39493U, + 38309U, 39474U, 38400U, 39529U, 38455U, 35995U, 43602U, 38419U, 39548U, + 62013U, 70076U, 61172U, 62141U, 70159U, 61246U, 62384U, 70289U, 61362U, + 62189U, 70195U, 61278U, 62315U, 70253U, 61330U, 62503U, 70331U, 61400U, + 58858U, 63418U, 58871U, 63433U, 70038U, 61138U, 56411U, 57367U, 63237U, + 70058U, 61156U, 56429U, 57385U, 63253U, 63496U, 70094U, 61188U, 56445U, + 57401U, 63267U, 70112U, 61204U, 56461U, 57417U, 63281U, 70132U, 61222U, + 56479U, 57435U, 63297U, 63508U, 70177U, 61262U, 56503U, 57459U, 63318U, + 70231U, 61310U, 56535U, 57491U, 63346U, 70309U, 61380U, 56580U, 57536U, + 63386U, 70242U, 61320U, 56545U, 57501U, 63355U, 70320U, 61390U, 56590U, + 57546U, 63395U, 63526U, 70299U, 61371U, 56571U, 57527U, 63378U, 63514U, + 70213U, 61294U, 56519U, 57475U, 63332U, 63520U, 70271U, 61346U, 56555U, + 57511U, 63364U, 63533U, 70349U, 61416U, 56600U, 57556U, 63404U, 36057U, + 13674U, 36153U, 13835U, 28336U, 14017U, 28554U, 55192U, 56956U, 55090U, + 56780U, 14241U, 28778U, 14100U, 28637U, 55282U, 57046U, 55456U, 57203U, + 13843U, 28344U, 14026U, 28563U, 55201U, 56965U, 55098U, 56788U, 14308U, + 28785U, 14108U, 28661U, 55290U, 57054U, 56335U, 57210U, 13771U, 28290U, + 13965U, 28502U, 55132U, 56896U, 55037U, 56727U, 14130U, 28679U, 14054U, + 28591U, 55229U, 56993U, 55308U, 57072U, 61968U, 62076U, 62236U, 62424U, + 62265U, 62453U, 62391U, 62348U, 62536U, 13852U, 28353U, 14036U, 28573U, + 55211U, 56975U, 55107U, 56797U, 14316U, 28793U, 14117U, 28670U, 55299U, + 57063U, 56343U, 57218U, 13780U, 28299U, 13975U, 28512U, 55142U, 56906U, + 55046U, 56736U, 14138U, 28687U, 14063U, 28600U, 55238U, 57002U, 55316U, + 57080U, 61952U, 61982U, 62039U, 62060U, 62090U, 62167U, 62245U, 62433U, + 62274U, 62462U, 62399U, 62215U, 62362U, 62550U, 55359U, 57106U, 14205U, + 28754U, 55432U, 57179U, 18190U, 27006U, 35341U, 51175U, 65103U, 65273U, + 17771U, 34758U, 50527U, 16863U, 33033U, 48743U, 15554U, 22687U, 30911U, + 46475U, 17938U, 26630U, 34965U, 50799U, 15125U, 22306U, 30441U, 46005U, + 18236U, 27052U, 35387U, 51221U, 65132U, 65302U, 17803U, 34790U, 50559U, + 16893U, 33063U, 48773U, 15602U, 22800U, 31024U, 46588U, 18259U, 27075U, + 35410U, 51244U, 15155U, 22336U, 30471U, 46035U, 66436U, 66454U, 17278U, + 25818U, 33952U, 49720U, 17521U, 34340U, 17254U, 25751U, 33885U, 49653U, + 21780U, 30097U, 45361U, 12075U, 2293U, 59083U, 9559U, 60160U, 3148U, + 59420U, 10368U, 60497U, 12873U, 17290U, 25919U, 34053U, 49821U, 22010U, + 30224U, 45620U, 12588U, 2862U, 59383U, 10103U, 60460U, 3717U, 59720U, + 10912U, 60797U, 13337U, 20191U, 67051U, 67074U, 2566U, 63551U, 9807U, + 3421U, 63575U, 67063U, 10616U, 62294U, 62482U, 62308U, 62496U, 18353U, + 27317U, 35566U, 51450U, 18379U, 27398U, 35647U, 51531U, 57892U, 62417U, + 62581U, 43778U, 17266U, 25791U, 33925U, 49693U, 43624U, 382U, 7425U, + 396U, 66427U, 66445U, 15308U, 22416U, 30640U, 46204U, 17949U, 26642U, + 34977U, 50811U, 21987U, 30201U, 45597U, 17029U, 25112U, 33201U, 48911U, + 12395U, 2685U, 59365U, 9926U, 60442U, 3540U, 59702U, 10735U, 60779U, + 13163U, 2556U, 63539U, 9797U, 3411U, 63563U, 10606U, 42663U, 42575U, + 57728U, 17821U, 26450U, 34821U, 50619U, 12257U, 5809U, 2482U, 6327U, + 9723U, 3337U, 10532U, 13038U, 17520U, 34339U, 42697U, 42606U, 18318U, + 27185U, 35494U, 51354U, 12647U, 13390U, 42675U, 67120U, 67208U, 42586U, + 12424U, 13189U, 42708U, 63113U, 67134U, 63188U, 67222U, 42616U, 36354U, + 18213U, 27029U, 35364U, 51198U, 57851U, 12549U, 2823U, 10064U, 3678U, + 10873U, 13302U, 16556U, 24232U, 32397U, 47971U, 13577U, 13917U, 13646U, + 14324U, 13589U, 13595U, 7454U, 42724U, 57618U, 13936U, 7474U, 42740U, + 57645U, 13660U, 14338U, 27896U, 16089U, 24761U, 32777U, 43151U, 25466U, + 33531U, 43164U, 12374U, 5916U, 6434U, 13144U, 17028U, 12394U, 13162U, + 16098U, 23651U, 31875U, 47423U, 36178U, 18839U, 19083U, 19665U, 35893U, + 43500U, 36222U, 19371U, 19953U, 36189U, 18853U, 19102U, 19684U, 35902U, + 43509U, 36233U, 19390U, 19972U, 36200U, 18899U, 19183U, 19765U, 35911U, + 43518U, 36244U, 19471U, 20053U, 63502U, 56495U, 57451U, 63311U, 43527U, + 62128U, 36211U, 18979U, 19308U, 19890U, 35920U, 36255U, 19534U, 20116U, + 14922U, 21755U, 30071U, 45335U, 42532U, 16080U, 23642U, 31866U, 47414U, + 14352U, 20457U, 28926U, 44036U, 42510U, 42521U, 16778U, 32871U, 48570U, + 17113U, 33625U, 49346U, 2939U, 3794U, 10180U, 10989U, 12723U, 13459U, + 311U, 24488U, 65076U, 65246U, 18294U, 27161U, 35470U, 51330U, 12607U, + 13354U, 71177U, 40512U, 39367U, 36169U, 51988U, 13561U, 13829U, 64983U, + 65153U, 12044U, 12845U, 65145U, 11992U, 9487U, 10296U, 12798U, 12033U, + 2262U, 9528U, 3117U, 10337U, 12835U, 26258U, 34581U, 50350U, 57903U, + 26524U, 50693U, 27269U, 65083U, 65253U, 15939U, 23453U, 31677U, 47233U, + 17245U, 25740U, 33874U, 49642U, 28045U, 65118U, 65288U, 15033U, 30337U, + 45901U, 15195U, 30537U, 46101U, 69515U, 67541U, 68687U, 67972U, 69118U, + 69864U, 16764U, 32857U, 48556U, 17099U, 33611U, 49332U, 2921U, 3776U, + 10162U, 10971U, 12705U, 13442U, 24577U, 32617U, 48305U, 25282U, 33371U, + 49081U, 11007U, 6507U, 3812U, 6870U, 4175U, 11385U, 16731U, 24532U, + 32584U, 48260U, 12055U, 2273U, 9539U, 3128U, 10348U, 12855U, 24694U, + 32710U, 48422U, 25399U, 33464U, 49198U, 11109U, 6628U, 3933U, 6991U, + 4296U, 11481U, 17654U, 26293U, 34616U, 50385U, 12137U, 2355U, 9621U, + 3210U, 10430U, 12929U, 26757U, 35092U, 50926U, 11245U, 6123U, 2957U, + 7165U, 4470U, 10198U, 25240U, 33329U, 49039U, 24720U, 32736U, 48448U, + 11281U, 6159U, 2993U, 7201U, 4506U, 10232U, 25425U, 33490U, 49224U, + 70825U, 70551U, 70414U, 70688U, 70909U, 11143U, 6662U, 3967U, 7025U, + 4330U, 11513U, 16496U, 32297U, 47871U, 24928U, 32972U, 48671U, 25605U, + 33665U, 49419U, 11351U, 6836U, 4141U, 7271U, 4576U, 11641U, 14226U, + 24670U, 48398U, 25375U, 49174U, 65048U, 65226U, 64991U, 65161U, 63090U, + 63165U, 17050U, 25146U, 33235U, 48945U, 62616U, 62769U, 62933U, 62684U, + 62837U, 63001U, 62662U, 62815U, 62979U, 62730U, 62883U, 63047U, 27441U, + 35690U, 51574U, 35737U, 27556U, 35803U, 51772U, 58745U, 61847U, 66881U, + 9236U, 1877U, 5785U, 641U, 5187U, 67371U, 68233U, 7909U, 1277U, + 68517U, 67802U, 8585U, 68948U, 27099U, 51268U, 65089U, 65259U, 27221U, + 51390U, 22165U, 45775U, 25557U, 49371U, 12742U, 13477U, 12627U, 13372U, + 42501U, 16643U, 24433U, 32496U, 48172U, 7529U, 11762U, 43312U, 66193U, + 65674U, 66357U, 66366U, 66157U, 65501U, 66181U, 66254U, 65489U, 66168U, + 28244U, 4708U, 30U, 291U, 17706U, 26370U, 34693U, 50462U, 12181U, + 2399U, 9665U, 3254U, 10474U, 12969U, 12364U, 2664U, 9905U, 3519U, + 10714U, 13135U, 58771U, 69411U, 67437U, 68299U, 68583U, 67868U, 69014U, + 69766U, 15005U, 30309U, 45873U, 15167U, 30509U, 46073U, 69479U, 67505U, + 68651U, 67936U, 69082U, 69830U, 18048U, 26864U, 35199U, 51033U, 17591U, + 26206U, 34529U, 50298U, 12084U, 2302U, 9568U, 3157U, 10377U, 12881U, + 15105U, 22286U, 30421U, 45985U, 58759U, 69379U, 67405U, 68267U, 68551U, + 67836U, 68982U, 69736U, 301U, 4760U, 284U, 13533U, 13705U, 13541U, + 13723U, 27654U, 49466U, 57581U, 48732U, 66337U, 18022U, 26825U, 35160U, + 50994U, 12508U, 2791U, 10032U, 3646U, 10841U, 13265U, 16566U, 24254U, + 32419U, 47993U, 70875U, 70653U, 70516U, 70790U, 70955U, 15356U, 22465U, + 30689U, 46253U, 18329U, 27293U, 35542U, 51426U, 12676U, 2892U, 10133U, + 3747U, 10942U, 13416U, 18457U, 17996U, 26785U, 35120U, 50954U, 12477U, + 2769U, 10010U, 3624U, 10819U, 13237U, 16531U, 24207U, 32372U, 47946U, + 70851U, 70617U, 70480U, 70754U, 70933U, 15317U, 22425U, 30649U, 46213U, + 17960U, 26707U, 35042U, 50876U, 12404U, 2694U, 9935U, 3549U, 10744U, + 13171U, 21807U, 45400U, 24618U, 32658U, 48346U, 22037U, 45647U, 25323U, + 33412U, 49122U, 11041U, 59208U, 6560U, 60285U, 3865U, 59545U, 6923U, + 60622U, 4228U, 11417U, 21895U, 45488U, 24815U, 32831U, 48530U, 22125U, + 45735U, 25520U, 33585U, 49306U, 11211U, 59326U, 6768U, 60403U, 4073U, + 59663U, 7131U, 60740U, 4436U, 11577U, 13615U, 57782U, 24346U, 48085U, + 24390U, 48129U, 4659U, 128U, 7362U, 195U, 7349U, 177U, 4672U, + 146U, 7375U, 213U, 66317U, 17832U, 26474U, 34845U, 50643U, 16979U, + 25049U, 33138U, 48848U, 65753U, 21851U, 45444U, 24774U, 32790U, 48489U, + 22081U, 45691U, 25479U, 33544U, 49265U, 11177U, 59267U, 6715U, 60344U, + 4020U, 59604U, 7078U, 60681U, 4383U, 11545U, 16629U, 24419U, 32482U, + 48158U, 16616U, 24304U, 32469U, 48043U, 18270U, 27137U, 35446U, 51306U, + 12558U, 9404U, 2057U, 5961U, 11916U, 2832U, 6465U, 10073U, 3687U, + 10882U, 13310U, 15286U, 22394U, 30618U, 46182U, 17733U, 26397U, 34720U, + 50489U, 16828U, 24965U, 33009U, 48708U, 12204U, 9213U, 1829U, 5727U, + 11812U, 2422U, 6292U, 9688U, 3277U, 10497U, 12990U, 15092U, 22273U, + 30408U, 45972U, 36569U, 36361U, 36627U, 36389U, 36801U, 36685U, 36417U, + 36849U, 18394U, 27413U, 35662U, 51546U, 15972U, 23486U, 31710U, 47266U, + 23534U, 31758U, 47314U, 36743U, 36445U, 36897U, 25210U, 33299U, 49009U, + 21791U, 45384U, 24603U, 32643U, 48331U, 22021U, 45631U, 25308U, 33397U, + 49107U, 11673U, 4610U, 58964U, 59814U, 59187U, 6541U, 60264U, 3846U, + 59524U, 6904U, 60601U, 4209U, 25254U, 33343U, 49053U, 21879U, 45472U, + 24800U, 32816U, 48515U, 22109U, 45719U, 25505U, 33570U, 49291U, 11695U, + 4632U, 59006U, 59856U, 59305U, 6749U, 60382U, 4054U, 59642U, 7112U, + 60719U, 4417U, 21939U, 30153U, 45549U, 16950U, 25020U, 33109U, 48819U, + 9283U, 60061U, 1924U, 58921U, 2505U, 59122U, 9746U, 60199U, 3360U, + 59459U, 10555U, 60536U, 21835U, 45428U, 24746U, 32762U, 48474U, 22065U, + 45675U, 25451U, 33516U, 49250U, 11684U, 4621U, 58985U, 59835U, 59246U, + 6696U, 60323U, 4001U, 59583U, 7059U, 60660U, 4364U, 36593U, 36375U, + 36651U, 36403U, 36825U, 36709U, 36431U, 36873U, 18408U, 27427U, 35676U, + 51560U, 15996U, 23510U, 31734U, 47290U, 23558U, 31782U, 47338U, 36767U, + 36459U, 36921U, 17819U, 26461U, 34832U, 50630U, 12255U, 9258U, 1899U, + 5807U, 11833U, 2480U, 6325U, 9721U, 3335U, 10530U, 13036U, 30120U, + 45516U, 16919U, 24989U, 33078U, 48788U, 21923U, 30137U, 45533U, 16935U, + 25005U, 33094U, 48804U, 60833U, 59756U, 9269U, 1910U, 2491U, 59100U, + 9732U, 60177U, 3346U, 59437U, 10541U, 60514U, 21970U, 30184U, 45580U, + 17003U, 25073U, 33162U, 48872U, 60853U, 59776U, 9310U, 1951U, 2532U, + 59165U, 9773U, 60242U, 3387U, 59502U, 10582U, 60579U, 21954U, 30168U, + 45564U, 16964U, 25034U, 33123U, 48833U, 9296U, 60082U, 1937U, 58942U, + 2518U, 59143U, 9759U, 60220U, 3373U, 59480U, 10568U, 60557U, 18132U, + 26948U, 35283U, 51117U, 17884U, 26576U, 34911U, 50745U, 12298U, 9346U, + 1987U, 5850U, 11863U, 2598U, 6368U, 9839U, 3453U, 10648U, 13075U, + 15031U, 30335U, 45899U, 15193U, 30535U, 46099U, 58353U, 61891U, 66925U, + 69513U, 67539U, 68685U, 67970U, 69116U, 69862U, 15076U, 30380U, 45944U, + 15238U, 30580U, 46144U, 58380U, 61918U, 66952U, 69570U, 67596U, 68742U, + 68027U, 69173U, 69916U, 18104U, 26920U, 35255U, 51089U, 15613U, 22811U, + 31035U, 46599U, 58390U, 58817U, 61936U, 66970U, 69656U, 67700U, 68415U, + 68846U, 68131U, 69277U, 69997U, 15528U, 22661U, 30885U, 46449U, 17858U, + 26550U, 34885U, 50719U, 58323U, 58769U, 61861U, 66895U, 12276U, 69409U, + 9324U, 1965U, 5828U, 11843U, 2576U, 67435U, 6346U, 68297U, 9817U, + 68581U, 3431U, 67866U, 10626U, 69012U, 13055U, 69764U, 15003U, 30307U, + 45871U, 15165U, 30507U, 46071U, 58337U, 61875U, 66909U, 69477U, 67503U, + 68649U, 67934U, 69080U, 69828U, 15061U, 30365U, 45929U, 15223U, 30565U, + 46129U, 58371U, 61909U, 66943U, 69551U, 67577U, 68723U, 68008U, 69154U, + 69898U, 18076U, 26892U, 35227U, 51061U, 15264U, 22372U, 30596U, 46160U, + 17617U, 26232U, 34555U, 50324U, 16804U, 24878U, 32922U, 48621U, 12106U, + 9190U, 1806U, 5704U, 11791U, 2324U, 6269U, 9590U, 3179U, 10399U, + 12901U, 17148U, 33723U, 49491U, 17208U, 33837U, 49605U, 12433U, 9370U, + 2011U, 11885U, 2725U, 9966U, 3580U, 10775U, 13197U, 17172U, 33747U, + 49515U, 17232U, 33861U, 49629U, 12455U, 9392U, 2033U, 11905U, 2747U, + 9988U, 3602U, 10797U, 13217U, 17678U, 26342U, 34665U, 50434U, 12157U, + 2375U, 9641U, 3230U, 10450U, 12947U, 15115U, 22296U, 30431U, 45995U, + 58764U, 69394U, 67420U, 68282U, 68566U, 67851U, 68997U, 69750U, 18162U, + 26978U, 35313U, 51147U, 17912U, 26604U, 34939U, 50773U, 12322U, 5874U, + 2622U, 6392U, 9863U, 3477U, 10672U, 13097U, 15565U, 22763U, 30987U, + 46551U, 58783U, 69590U, 67616U, 68331U, 68762U, 68047U, 69193U, 69935U, + 14957U, 22189U, 30235U, 45799U, 58719U, 69313U, 67305U, 68167U, 68451U, + 67736U, 68882U, 69674U, 22235U, 30281U, 45845U, 22346U, 30481U, 46045U, + 69443U, 67469U, 68615U, 67900U, 69046U, 69796U, 12344U, 5896U, 2644U, + 6414U, 9885U, 3499U, 10694U, 13117U, 58797U, 69624U, 67650U, 68365U, + 68796U, 68081U, 69227U, 69967U, 14981U, 22213U, 30259U, 45823U, 58733U, + 69347U, 67339U, 68201U, 68485U, 67770U, 68916U, 69706U, 41175U, 38159U, + 55526U, 55951U, 41743U, 55739U, 56164U, 41062U, 37003U, 37052U, 55487U, + 19065U, 55912U, 19647U, 41293U, 38230U, 37077U, 55597U, 19163U, 56022U, + 19745U, 41861U, 55810U, 19451U, 56235U, 20033U, 41435U, 38502U, 37104U, + 55668U, 19288U, 56093U, 19870U, 41973U, 55877U, 19591U, 56302U, 20173U, + 25226U, 33315U, 49025U, 24644U, 32684U, 48372U, 24841U, 32885U, 48584U, + 25349U, 33438U, 49148U, 11075U, 6594U, 3899U, 6957U, 4262U, 11449U, + 24902U, 32946U, 48645U, 25579U, 33639U, 49393U, 11317U, 6802U, 4107U, + 7237U, 4542U, 11609U, 13700U, 20430U, 41176U, 28901U, 41618U, 40932U, + 44011U, 41744U, 18557U, 41063U, 58103U, 52979U, 58524U, 53466U, 58686U, + 53708U, 66664U, 54530U, 61630U, 53982U, 66848U, 54804U, 58290U, 53256U, + 61814U, 54256U, 28239U, 21652U, 41294U, 41521U, 45234U, 41862U, 58036U, + 52882U, 58483U, 53405U, 58625U, 53617U, 66603U, 54439U, 61569U, 53891U, + 66787U, 54713U, 58229U, 53165U, 61753U, 54165U, 57986U, 52812U, 58461U, + 53373U, 58579U, 53551U, 66557U, 54373U, 61523U, 53825U, 66741U, 54647U, + 58183U, 53099U, 61707U, 54099U, 58058U, 52914U, 58503U, 53435U, 58645U, + 53647U, 66623U, 54469U, 61589U, 53921U, 66807U, 54743U, 58249U, 53195U, + 61773U, 54195U, 54994U, 23763U, 41436U, 41974U, 14879U, 21712U, 30028U, + 42978U, 45292U, 16149U, 23702U, 31926U, 43053U, 47474U, 9183U, 52566U, + 1799U, 52374U, 5697U, 52470U, 11785U, 52661U, 13718U, 40950U, 18567U, + 41081U, 67261U, 71051U, 70999U, 28257U, 41539U, 58080U, 52946U, 58665U, + 53677U, 66643U, 54499U, 61609U, 53951U, 66827U, 54773U, 58269U, 53225U, + 61793U, 54225U, 55004U, 41992U, 9422U, 52590U, 2195U, 52398U, 6202U, + 52494U, 11932U, 52683U, 13736U, 40968U, 18577U, 41099U, 28267U, 41557U, + 58012U, 52848U, 58603U, 53585U, 66581U, 54407U, 61547U, 53859U, 66765U, + 54681U, 58207U, 53133U, 61731U, 54133U, 55014U, 42010U, 9436U, 52614U, + 3036U, 52422U, 7312U, 52518U, 11944U, 52705U, 13758U, 40986U, 18587U, + 41117U, 58127U, 53013U, 58708U, 53740U, 66686U, 54562U, 61652U, 54014U, + 66870U, 54836U, 58312U, 53288U, 61836U, 54288U, 28277U, 41575U, 55024U, + 42028U, 9450U, 52638U, 3050U, 52446U, 7326U, 52542U, 11956U, 52727U, + 13747U, 54934U, 40U, 40901U, 67284U, 62135U, 71080U, 70150U, 61238U, + 71026U, 14171U, 28720U, 55398U, 57145U, 14178U, 28727U, 55405U, 57152U, + 61989U, 62097U, 62369U, 62557U, 55365U, 57112U, 14211U, 28760U, 55438U, + 57185U, 62026U, 62154U, 62202U, 62335U, 62523U, 35940U, 43547U, 38291U, + 39456U, 35962U, 43569U, 38346U, 35984U, 43591U, 38382U, 39511U, 36006U, + 43613U, 38437U, 39566U, 62033U, 70085U, 61180U, 62161U, 70168U, 61254U, + 62209U, 70204U, 61286U, 62342U, 70262U, 61338U, 62530U, 70340U, 61408U, + 70048U, 61147U, 56420U, 57376U, 63245U, 70067U, 61164U, 56437U, 57393U, + 63260U, 70103U, 61196U, 56453U, 57409U, 63274U, 70122U, 61213U, 56470U, + 57426U, 63289U, 70141U, 61230U, 56487U, 57443U, 63304U, 70186U, 61270U, + 56511U, 57467U, 63325U, 70222U, 61302U, 56527U, 57483U, 63339U, 70280U, + 61354U, 56563U, 57519U, 63371U, 70358U, 61424U, 56608U, 57564U, 63411U, + 36065U, 13681U, 36161U, 61975U, 62083U, 62355U, 62543U, 61960U, 62006U, + 62046U, 62068U, 62114U, 62174U, 62222U, 62377U, 62574U, 55372U, 57119U, + 14218U, 28767U, 55445U, 57192U, 67272U, 71065U, 71012U, 40906U, 67294U, + 71093U, 71038U, 28080U, 16765U, 32858U, 48557U, 17100U, 33612U, 49333U, + 2922U, 3777U, 10163U, 10972U, 12706U, 13443U, 42393U, 43767U, 15346U, + 22455U, 30679U, 46243U, 18050U, 26852U, 35187U, 51021U, 63120U, 67141U, + 71121U, 63195U, 67229U, 71151U, 7405U, 63069U, 67085U, 71107U, 63144U, + 67173U, 71137U, 7387U, 15266U, 22374U, 30598U, 46162U, 17593U, 26195U, + 34518U, 50287U, 16806U, 24868U, 32912U, 48611U, 12086U, 5706U, 2304U, + 6271U, 9570U, 3159U, 10379U, 12883U, 36277U, 12756U, 13490U, 24360U, + 48099U, 24404U, 48143U, 25688U, 33785U, 49553U, 25714U, 33811U, 49579U, + 17746U, 26410U, 34733U, 50502U, 12215U, 9224U, 1840U, 5738U, 11822U, + 2433U, 6303U, 9699U, 3288U, 10508U, 13000U, 18539U, 13789U, 28308U, + 13985U, 28522U, 55160U, 56924U, 55062U, 56752U, 14146U, 28695U, 14072U, + 28609U, 55254U, 57018U, 55347U, 57094U, 26170U, 34493U, 50262U, 26500U, + 50669U, 27245U, 70367U, 70374U, 16654U, 24444U, 32507U, 48183U, 17018U, + 25088U, 33177U, 48887U, 66463U, 60955U, 60901U, 63616U, 66489U, 60979U, + 60929U, 63640U, 56367U, 57264U, 17138U, 25642U, 33702U, 49456U, 66476U, + 60967U, 60915U, 63628U, 66501U, 60990U, 60942U, 63651U, 56356U, 57253U, + 40575U, 52048U, 15862U, 23376U, 31600U, 47156U, 16665U, 24455U, 32518U, + 43085U, 48194U, 11962U, 2202U, 6209U, 9457U, 3057U, 10266U, 12771U, + 15895U, 23409U, 31633U, 47189U, 16698U, 24499U, 32551U, 43118U, 48227U, + 12003U, 2232U, 6239U, 9498U, 3087U, 10307U, 12808U, 14237U, 52260U, + 52341U, 24590U, 32630U, 48318U, 25295U, 33384U, 49094U, 11024U, 6524U, + 3829U, 6887U, 4192U, 11401U, 16742U, 24543U, 32595U, 48271U, 12065U, + 2283U, 9549U, 3138U, 10358U, 12864U, 24707U, 32723U, 48435U, 25412U, + 33477U, 49211U, 11126U, 6645U, 3950U, 7008U, 4313U, 11497U, 17666U, + 26305U, 34628U, 50397U, 12147U, 2365U, 9631U, 3220U, 10440U, 12938U, + 26771U, 35106U, 50940U, 11263U, 6141U, 2975U, 7183U, 4488U, 10215U, + 24733U, 32749U, 48461U, 11299U, 6177U, 3011U, 7219U, 4524U, 10249U, + 25438U, 33503U, 49237U, 70838U, 70564U, 70427U, 70701U, 70921U, 11160U, + 6679U, 3984U, 7042U, 4347U, 11529U, 16508U, 24144U, 32309U, 47883U, + 24941U, 32985U, 48684U, 25618U, 33678U, 49432U, 11368U, 6853U, 4158U, + 7288U, 4593U, 11657U, 63098U, 63173U, 17063U, 25159U, 33248U, 48958U, + 62627U, 62780U, 62944U, 62695U, 62848U, 63012U, 62673U, 62826U, 62990U, + 62741U, 62894U, 63058U, 27457U, 35706U, 51590U, 35753U, 27572U, 35819U, + 51788U, 58752U, 61854U, 66888U, 9247U, 1888U, 5796U, 652U, 5198U, + 67388U, 68250U, 7920U, 1288U, 68534U, 67819U, 8596U, 68965U, 27976U, + 27112U, 51281U, 65096U, 65266U, 27233U, 51402U, 22177U, 45787U, 25568U, + 49382U, 12757U, 13491U, 12637U, 13381U, 17719U, 26383U, 34706U, 50475U, + 12192U, 2410U, 9676U, 3265U, 10485U, 12979U, 18062U, 26878U, 35213U, + 51047U, 17604U, 26219U, 34542U, 50311U, 12095U, 2313U, 9579U, 3168U, + 10388U, 12891U, 66347U, 18035U, 26838U, 35173U, 51007U, 12519U, 2802U, + 10043U, 3657U, 10852U, 13275U, 16578U, 24266U, 32431U, 48005U, 70887U, + 70665U, 70528U, 70802U, 70966U, 15366U, 22475U, 30699U, 46263U, 18341U, + 27305U, 35554U, 51438U, 12686U, 2902U, 10143U, 3757U, 10952U, 13425U, + 18009U, 26798U, 35133U, 50967U, 12488U, 2780U, 10021U, 3635U, 10830U, + 13247U, 16543U, 24219U, 32384U, 47958U, 70863U, 70629U, 70492U, 70766U, + 70944U, 15327U, 22435U, 30659U, 46223U, 17972U, 26719U, 35054U, 50888U, + 12414U, 2704U, 9945U, 3559U, 10754U, 13180U, 21821U, 45414U, 24631U, + 32671U, 48359U, 22051U, 45661U, 25336U, 33425U, 49135U, 11058U, 59227U, + 6577U, 60304U, 3882U, 59564U, 6940U, 60641U, 4245U, 11433U, 21909U, + 45502U, 24828U, 32844U, 48543U, 22139U, 45749U, 25533U, 33598U, 49319U, + 11228U, 59345U, 6785U, 60422U, 4090U, 59682U, 7148U, 60759U, 4453U, + 11593U, 13621U, 57792U, 24361U, 48100U, 24405U, 48144U, 11713U, 230U, + 4650U, 114U, 7340U, 163U, 13510U, 244U, 66327U, 17845U, 26487U, + 34858U, 50656U, 16991U, 25061U, 33150U, 48860U, 65761U, 21865U, 45458U, + 24787U, 32803U, 48502U, 22095U, 45705U, 25492U, 33557U, 49278U, 11194U, + 59286U, 6732U, 60363U, 4037U, 59623U, 7095U, 60700U, 4400U, 11561U, + 15297U, 22405U, 30629U, 46193U, 17747U, 26411U, 34734U, 50503U, 16840U, + 24977U, 33021U, 48720U, 12216U, 9225U, 1841U, 5739U, 11823U, 2434U, + 6304U, 9700U, 3289U, 10509U, 13001U, 36473U, 36581U, 36497U, 36639U, + 36813U, 36521U, 36697U, 36861U, 15948U, 23462U, 31686U, 47242U, 15984U, + 23498U, 31722U, 47278U, 23546U, 31770U, 47326U, 36545U, 36755U, 36909U, + 36485U, 36605U, 36509U, 36663U, 36837U, 36533U, 36721U, 36885U, 15960U, + 23474U, 31698U, 47254U, 16008U, 23522U, 31746U, 47302U, 23570U, 31794U, + 47350U, 36557U, 36779U, 36933U, 18147U, 26963U, 35298U, 51132U, 17898U, + 26590U, 34925U, 50759U, 12310U, 9358U, 1999U, 5862U, 11874U, 2610U, + 6380U, 9851U, 3465U, 10660U, 13086U, 15046U, 30350U, 45914U, 15208U, + 30550U, 46114U, 58362U, 61900U, 66934U, 69532U, 67558U, 68704U, 67989U, + 69135U, 69880U, 18118U, 26934U, 35269U, 51103U, 15541U, 22674U, 30898U, + 46462U, 17871U, 26563U, 34898U, 50732U, 58330U, 58776U, 61868U, 66902U, + 12287U, 69426U, 9335U, 1976U, 5839U, 11853U, 2587U, 67452U, 6357U, + 68314U, 9828U, 68598U, 3442U, 67883U, 10637U, 69029U, 13065U, 69780U, + 15017U, 30321U, 45885U, 15179U, 30521U, 46085U, 58345U, 61883U, 66917U, + 69495U, 67521U, 68667U, 67952U, 69098U, 69845U, 18090U, 26906U, 35241U, + 51075U, 15275U, 22383U, 30607U, 46171U, 17630U, 26245U, 34568U, 50337U, + 16816U, 24890U, 32934U, 48633U, 12117U, 9201U, 1817U, 5715U, 11801U, + 2335U, 6280U, 9601U, 3190U, 10410U, 12911U, 17160U, 33735U, 49503U, + 17220U, 33849U, 49617U, 12444U, 9381U, 2022U, 11895U, 2736U, 9977U, + 3591U, 10786U, 13207U, 50589U, 2455U, 3310U, 17692U, 26356U, 34679U, + 50448U, 12169U, 2387U, 9653U, 3242U, 10462U, 12958U, 18176U, 26992U, + 35327U, 51161U, 17925U, 26617U, 34952U, 50786U, 12333U, 5885U, 2633U, + 6403U, 9874U, 3488U, 10683U, 13107U, 15578U, 22776U, 31000U, 46564U, + 58790U, 69607U, 67633U, 68348U, 68779U, 68064U, 69210U, 69951U, 50603U, + 2467U, 3322U, 14969U, 22201U, 30247U, 45811U, 58726U, 69330U, 67322U, + 68184U, 68468U, 67753U, 68899U, 69690U, 57869U, 36266U, 12741U, 13476U, + 12626U, 13371U, 22248U, 30294U, 45858U, 22359U, 30494U, 46058U, 69460U, + 67486U, 68632U, 67917U, 69063U, 69812U, 12354U, 5906U, 2654U, 6424U, + 9895U, 3509U, 10704U, 13126U, 58803U, 69640U, 67666U, 68381U, 68812U, + 68097U, 69243U, 69982U, 13614U, 57781U, 24345U, 48084U, 24389U, 48128U, + 17732U, 26396U, 34719U, 50488U, 12203U, 9212U, 1828U, 5726U, 11811U, + 2421U, 6291U, 9687U, 3276U, 10496U, 12989U, 14992U, 22224U, 30270U, + 45834U, 58739U, 69363U, 67355U, 68217U, 68501U, 67786U, 68932U, 69721U, + 24657U, 32697U, 48385U, 25362U, 33451U, 49161U, 11092U, 6611U, 3916U, + 6974U, 4279U, 11465U, 24915U, 32959U, 48658U, 25592U, 33652U, 49406U, + 11334U, 6819U, 4124U, 7254U, 4559U, 11625U, 25701U, 33798U, 49566U, + 25727U, 33824U, 49592U, 26182U, 34505U, 50274U, 26512U, 50681U, 27257U, + 15884U, 23398U, 31622U, 47178U, 16687U, 24477U, 32540U, 43107U, 48216U, + 11982U, 2222U, 6229U, 9477U, 3077U, 10286U, 12789U, 15917U, 23431U, + 31655U, 47211U, 16720U, 24521U, 32573U, 43140U, 48249U, 12023U, 2252U, + 6259U, 9518U, 3107U, 10327U, 12826U, 51982U, 52043U, 16192U, 23790U, + 31969U, 47517U, 16304U, 23902U, 32081U, 47629U, 16276U, 23874U, 32053U, + 47601U, 16402U, 24000U, 32179U, 47727U, 16220U, 23818U, 31997U, 47545U, + 16332U, 23930U, 32109U, 47657U, 16248U, 23846U, 32025U, 47573U, 16374U, + 23972U, 32151U, 47699U, 16206U, 23804U, 31983U, 47531U, 16318U, 23916U, + 32095U, 47643U, 16234U, 23832U, 32011U, 47559U, 16346U, 23944U, 32123U, + 47671U, 16262U, 23860U, 32039U, 47587U, 16388U, 23986U, 32165U, 47713U, + 16290U, 23888U, 32067U, 47615U, 16416U, 24014U, 32193U, 47741U, 16430U, + 24028U, 32207U, 47755U, 16360U, 23958U, 32137U, 47685U, 43306U, 28066U, + 43177U, 14946U, 21998U, 30212U, 45608U, 18681U, 35867U, 35885U, 12435U, + 2727U, 9968U, 3582U, 10777U, 13199U, 42134U, 15873U, 23387U, 31611U, + 47167U, 16676U, 24466U, 32529U, 43096U, 48205U, 11972U, 2212U, 6219U, + 9467U, 3067U, 10276U, 12780U, 15906U, 23420U, 31644U, 47200U, 16709U, + 24510U, 32562U, 43129U, 48238U, 12013U, 2242U, 6249U, 9508U, 3097U, + 10317U, 12817U, 4836U, 4929U, 4945U, 7439U, +}; +#endif // GET_INSTRINFO_MC_DESC diff --git a/arch/AArch64/AArch64GenInstrInfo.inc b/arch/AArch64/AArch64GenInstrInfo.inc index 8ce807b23a..a1af8f6f92 100644 --- a/arch/AArch64/AArch64GenInstrInfo.inc +++ b/arch/AArch64/AArch64GenInstrInfo.inc @@ -2,7 +2,8 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +/*===- TableGen'erated file -------------------------------------*- C++ +-*-===*|* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| @@ -13,4523 +14,4523 @@ #undef GET_INSTRINFO_ENUM enum { - AArch64_PHI = 0, - AArch64_INLINEASM = 1, - AArch64_CFI_INSTRUCTION = 2, - AArch64_EH_LABEL = 3, - AArch64_GC_LABEL = 4, - AArch64_ANNOTATION_LABEL = 5, - AArch64_KILL = 6, - AArch64_EXTRACT_SUBREG = 7, - AArch64_INSERT_SUBREG = 8, - AArch64_IMPLICIT_DEF = 9, - AArch64_SUBREG_TO_REG = 10, - AArch64_COPY_TO_REGCLASS = 11, - AArch64_DBG_VALUE = 12, - AArch64_DBG_LABEL = 13, - AArch64_REG_SEQUENCE = 14, - AArch64_COPY = 15, - AArch64_BUNDLE = 16, - AArch64_LIFETIME_START = 17, - AArch64_LIFETIME_END = 18, - AArch64_STACKMAP = 19, - AArch64_FENTRY_CALL = 20, - AArch64_PATCHPOINT = 21, - AArch64_LOAD_STACK_GUARD = 22, - AArch64_STATEPOINT = 23, - AArch64_LOCAL_ESCAPE = 24, - AArch64_FAULTING_OP = 25, - AArch64_PATCHABLE_OP = 26, - AArch64_PATCHABLE_FUNCTION_ENTER = 27, - AArch64_PATCHABLE_RET = 28, - AArch64_PATCHABLE_FUNCTION_EXIT = 29, - AArch64_PATCHABLE_TAIL_CALL = 30, - AArch64_PATCHABLE_EVENT_CALL = 31, - AArch64_PATCHABLE_TYPED_EVENT_CALL = 32, - AArch64_ICALL_BRANCH_FUNNEL = 33, - AArch64_G_ADD = 34, - AArch64_G_SUB = 35, - AArch64_G_MUL = 36, - AArch64_G_SDIV = 37, - AArch64_G_UDIV = 38, - AArch64_G_SREM = 39, - AArch64_G_UREM = 40, - AArch64_G_AND = 41, - AArch64_G_OR = 42, - AArch64_G_XOR = 43, - AArch64_G_IMPLICIT_DEF = 44, - AArch64_G_PHI = 45, - AArch64_G_FRAME_INDEX = 46, - AArch64_G_GLOBAL_VALUE = 47, - AArch64_G_EXTRACT = 48, - AArch64_G_UNMERGE_VALUES = 49, - AArch64_G_INSERT = 50, - AArch64_G_MERGE_VALUES = 51, - AArch64_G_PTRTOINT = 52, - AArch64_G_INTTOPTR = 53, - AArch64_G_BITCAST = 54, - AArch64_G_LOAD = 55, - AArch64_G_SEXTLOAD = 56, - AArch64_G_ZEXTLOAD = 57, - AArch64_G_STORE = 58, - AArch64_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, - AArch64_G_ATOMIC_CMPXCHG = 60, - AArch64_G_ATOMICRMW_XCHG = 61, - AArch64_G_ATOMICRMW_ADD = 62, - AArch64_G_ATOMICRMW_SUB = 63, - AArch64_G_ATOMICRMW_AND = 64, - AArch64_G_ATOMICRMW_NAND = 65, - AArch64_G_ATOMICRMW_OR = 66, - AArch64_G_ATOMICRMW_XOR = 67, - AArch64_G_ATOMICRMW_MAX = 68, - AArch64_G_ATOMICRMW_MIN = 69, - AArch64_G_ATOMICRMW_UMAX = 70, - AArch64_G_ATOMICRMW_UMIN = 71, - AArch64_G_BRCOND = 72, - AArch64_G_BRINDIRECT = 73, - AArch64_G_INTRINSIC = 74, - AArch64_G_INTRINSIC_W_SIDE_EFFECTS = 75, - AArch64_G_ANYEXT = 76, - AArch64_G_TRUNC = 77, - AArch64_G_CONSTANT = 78, - AArch64_G_FCONSTANT = 79, - AArch64_G_VASTART = 80, - AArch64_G_VAARG = 81, - AArch64_G_SEXT = 82, - AArch64_G_ZEXT = 83, - AArch64_G_SHL = 84, - AArch64_G_LSHR = 85, - AArch64_G_ASHR = 86, - AArch64_G_ICMP = 87, - AArch64_G_FCMP = 88, - AArch64_G_SELECT = 89, - AArch64_G_UADDE = 90, - AArch64_G_USUBE = 91, - AArch64_G_SADDO = 92, - AArch64_G_SSUBO = 93, - AArch64_G_UMULO = 94, - AArch64_G_SMULO = 95, - AArch64_G_UMULH = 96, - AArch64_G_SMULH = 97, - AArch64_G_FADD = 98, - AArch64_G_FSUB = 99, - AArch64_G_FMUL = 100, - AArch64_G_FMA = 101, - AArch64_G_FDIV = 102, - AArch64_G_FREM = 103, - AArch64_G_FPOW = 104, - AArch64_G_FEXP = 105, - AArch64_G_FEXP2 = 106, - AArch64_G_FLOG = 107, - AArch64_G_FLOG2 = 108, - AArch64_G_FNEG = 109, - AArch64_G_FPEXT = 110, - AArch64_G_FPTRUNC = 111, - AArch64_G_FPTOSI = 112, - AArch64_G_FPTOUI = 113, - AArch64_G_SITOFP = 114, - AArch64_G_UITOFP = 115, - AArch64_G_FABS = 116, - AArch64_G_GEP = 117, - AArch64_G_PTR_MASK = 118, - AArch64_G_BR = 119, - AArch64_G_INSERT_VECTOR_ELT = 120, - AArch64_G_EXTRACT_VECTOR_ELT = 121, - AArch64_G_SHUFFLE_VECTOR = 122, - AArch64_G_BSWAP = 123, - AArch64_G_ADDRSPACE_CAST = 124, - AArch64_G_BLOCK_ADDR = 125, - AArch64_ABS_ZPmZ_B = 126, - AArch64_ABS_ZPmZ_D = 127, - AArch64_ABS_ZPmZ_H = 128, - AArch64_ABS_ZPmZ_S = 129, - AArch64_ABSv16i8 = 130, - AArch64_ABSv1i64 = 131, - AArch64_ABSv2i32 = 132, - AArch64_ABSv2i64 = 133, - AArch64_ABSv4i16 = 134, - AArch64_ABSv4i32 = 135, - AArch64_ABSv8i16 = 136, - AArch64_ABSv8i8 = 137, - AArch64_ADCSWr = 138, - AArch64_ADCSXr = 139, - AArch64_ADCWr = 140, - AArch64_ADCXr = 141, - AArch64_ADDHNv2i64_v2i32 = 142, - AArch64_ADDHNv2i64_v4i32 = 143, - AArch64_ADDHNv4i32_v4i16 = 144, - AArch64_ADDHNv4i32_v8i16 = 145, - AArch64_ADDHNv8i16_v16i8 = 146, - AArch64_ADDHNv8i16_v8i8 = 147, - AArch64_ADDPL_XXI = 148, - AArch64_ADDPv16i8 = 149, - AArch64_ADDPv2i32 = 150, - AArch64_ADDPv2i64 = 151, - AArch64_ADDPv2i64p = 152, - AArch64_ADDPv4i16 = 153, - AArch64_ADDPv4i32 = 154, - AArch64_ADDPv8i16 = 155, - AArch64_ADDPv8i8 = 156, - AArch64_ADDSWri = 157, - AArch64_ADDSWrr = 158, - AArch64_ADDSWrs = 159, - AArch64_ADDSWrx = 160, - AArch64_ADDSXri = 161, - AArch64_ADDSXrr = 162, - AArch64_ADDSXrs = 163, - AArch64_ADDSXrx = 164, - AArch64_ADDSXrx64 = 165, - AArch64_ADDVL_XXI = 166, - AArch64_ADDVv16i8v = 167, - AArch64_ADDVv4i16v = 168, - AArch64_ADDVv4i32v = 169, - AArch64_ADDVv8i16v = 170, - AArch64_ADDVv8i8v = 171, - AArch64_ADDWri = 172, - AArch64_ADDWrr = 173, - AArch64_ADDWrs = 174, - AArch64_ADDWrx = 175, - AArch64_ADDXri = 176, - AArch64_ADDXrr = 177, - AArch64_ADDXrs = 178, - AArch64_ADDXrx = 179, - AArch64_ADDXrx64 = 180, - AArch64_ADD_ZI_B = 181, - AArch64_ADD_ZI_D = 182, - AArch64_ADD_ZI_H = 183, - AArch64_ADD_ZI_S = 184, - AArch64_ADD_ZPmZ_B = 185, - AArch64_ADD_ZPmZ_D = 186, - AArch64_ADD_ZPmZ_H = 187, - AArch64_ADD_ZPmZ_S = 188, - AArch64_ADD_ZZZ_B = 189, - AArch64_ADD_ZZZ_D = 190, - AArch64_ADD_ZZZ_H = 191, - AArch64_ADD_ZZZ_S = 192, - AArch64_ADDlowTLS = 193, - AArch64_ADDv16i8 = 194, - AArch64_ADDv1i64 = 195, - AArch64_ADDv2i32 = 196, - AArch64_ADDv2i64 = 197, - AArch64_ADDv4i16 = 198, - AArch64_ADDv4i32 = 199, - AArch64_ADDv8i16 = 200, - AArch64_ADDv8i8 = 201, - AArch64_ADJCALLSTACKDOWN = 202, - AArch64_ADJCALLSTACKUP = 203, - AArch64_ADR = 204, - AArch64_ADRP = 205, - AArch64_ADR_LSL_ZZZ_D_0 = 206, - AArch64_ADR_LSL_ZZZ_D_1 = 207, - AArch64_ADR_LSL_ZZZ_D_2 = 208, - AArch64_ADR_LSL_ZZZ_D_3 = 209, - AArch64_ADR_LSL_ZZZ_S_0 = 210, - AArch64_ADR_LSL_ZZZ_S_1 = 211, - AArch64_ADR_LSL_ZZZ_S_2 = 212, - AArch64_ADR_LSL_ZZZ_S_3 = 213, - AArch64_ADR_SXTW_ZZZ_D_0 = 214, - AArch64_ADR_SXTW_ZZZ_D_1 = 215, - AArch64_ADR_SXTW_ZZZ_D_2 = 216, - AArch64_ADR_SXTW_ZZZ_D_3 = 217, - AArch64_ADR_UXTW_ZZZ_D_0 = 218, - AArch64_ADR_UXTW_ZZZ_D_1 = 219, - AArch64_ADR_UXTW_ZZZ_D_2 = 220, - AArch64_ADR_UXTW_ZZZ_D_3 = 221, - AArch64_AESDrr = 222, - AArch64_AESErr = 223, - AArch64_AESIMCrr = 224, - AArch64_AESIMCrrTied = 225, - AArch64_AESMCrr = 226, - AArch64_AESMCrrTied = 227, - AArch64_ANDSWri = 228, - AArch64_ANDSWrr = 229, - AArch64_ANDSWrs = 230, - AArch64_ANDSXri = 231, - AArch64_ANDSXrr = 232, - AArch64_ANDSXrs = 233, - AArch64_ANDS_PPzPP = 234, - AArch64_ANDV_VPZ_B = 235, - AArch64_ANDV_VPZ_D = 236, - AArch64_ANDV_VPZ_H = 237, - AArch64_ANDV_VPZ_S = 238, - AArch64_ANDWri = 239, - AArch64_ANDWrr = 240, - AArch64_ANDWrs = 241, - AArch64_ANDXri = 242, - AArch64_ANDXrr = 243, - AArch64_ANDXrs = 244, - AArch64_AND_PPzPP = 245, - AArch64_AND_ZI = 246, - AArch64_AND_ZPmZ_B = 247, - AArch64_AND_ZPmZ_D = 248, - AArch64_AND_ZPmZ_H = 249, - AArch64_AND_ZPmZ_S = 250, - AArch64_AND_ZZZ = 251, - AArch64_ANDv16i8 = 252, - AArch64_ANDv8i8 = 253, - AArch64_ASRD_ZPmI_B = 254, - AArch64_ASRD_ZPmI_D = 255, - AArch64_ASRD_ZPmI_H = 256, - AArch64_ASRD_ZPmI_S = 257, - AArch64_ASRR_ZPmZ_B = 258, - AArch64_ASRR_ZPmZ_D = 259, - AArch64_ASRR_ZPmZ_H = 260, - AArch64_ASRR_ZPmZ_S = 261, - AArch64_ASRVWr = 262, - AArch64_ASRVXr = 263, - AArch64_ASR_WIDE_ZPmZ_B = 264, - AArch64_ASR_WIDE_ZPmZ_H = 265, - AArch64_ASR_WIDE_ZPmZ_S = 266, - AArch64_ASR_WIDE_ZZZ_B = 267, - AArch64_ASR_WIDE_ZZZ_H = 268, - AArch64_ASR_WIDE_ZZZ_S = 269, - AArch64_ASR_ZPmI_B = 270, - AArch64_ASR_ZPmI_D = 271, - AArch64_ASR_ZPmI_H = 272, - AArch64_ASR_ZPmI_S = 273, - AArch64_ASR_ZPmZ_B = 274, - AArch64_ASR_ZPmZ_D = 275, - AArch64_ASR_ZPmZ_H = 276, - AArch64_ASR_ZPmZ_S = 277, - AArch64_ASR_ZZI_B = 278, - AArch64_ASR_ZZI_D = 279, - AArch64_ASR_ZZI_H = 280, - AArch64_ASR_ZZI_S = 281, - AArch64_AUTDA = 282, - AArch64_AUTDB = 283, - AArch64_AUTDZA = 284, - AArch64_AUTDZB = 285, - AArch64_AUTIA = 286, - AArch64_AUTIA1716 = 287, - AArch64_AUTIASP = 288, - AArch64_AUTIAZ = 289, - AArch64_AUTIB = 290, - AArch64_AUTIB1716 = 291, - AArch64_AUTIBSP = 292, - AArch64_AUTIBZ = 293, - AArch64_AUTIZA = 294, - AArch64_AUTIZB = 295, - AArch64_B = 296, - AArch64_BCAX = 297, - AArch64_BFMWri = 298, - AArch64_BFMXri = 299, - AArch64_BICSWrr = 300, - AArch64_BICSWrs = 301, - AArch64_BICSXrr = 302, - AArch64_BICSXrs = 303, - AArch64_BICS_PPzPP = 304, - AArch64_BICWrr = 305, - AArch64_BICWrs = 306, - AArch64_BICXrr = 307, - AArch64_BICXrs = 308, - AArch64_BIC_PPzPP = 309, - AArch64_BIC_ZPmZ_B = 310, - AArch64_BIC_ZPmZ_D = 311, - AArch64_BIC_ZPmZ_H = 312, - AArch64_BIC_ZPmZ_S = 313, - AArch64_BIC_ZZZ = 314, - AArch64_BICv16i8 = 315, - AArch64_BICv2i32 = 316, - AArch64_BICv4i16 = 317, - AArch64_BICv4i32 = 318, - AArch64_BICv8i16 = 319, - AArch64_BICv8i8 = 320, - AArch64_BIFv16i8 = 321, - AArch64_BIFv8i8 = 322, - AArch64_BITv16i8 = 323, - AArch64_BITv8i8 = 324, - AArch64_BL = 325, - AArch64_BLR = 326, - AArch64_BLRAA = 327, - AArch64_BLRAAZ = 328, - AArch64_BLRAB = 329, - AArch64_BLRABZ = 330, - AArch64_BR = 331, - AArch64_BRAA = 332, - AArch64_BRAAZ = 333, - AArch64_BRAB = 334, - AArch64_BRABZ = 335, - AArch64_BRK = 336, - AArch64_BRKAS_PPzP = 337, - AArch64_BRKA_PPmP = 338, - AArch64_BRKA_PPzP = 339, - AArch64_BRKBS_PPzP = 340, - AArch64_BRKB_PPmP = 341, - AArch64_BRKB_PPzP = 342, - AArch64_BRKNS_PPzP = 343, - AArch64_BRKN_PPzP = 344, - AArch64_BRKPAS_PPzPP = 345, - AArch64_BRKPA_PPzPP = 346, - AArch64_BRKPBS_PPzPP = 347, - AArch64_BRKPB_PPzPP = 348, - AArch64_BSLv16i8 = 349, - AArch64_BSLv8i8 = 350, - AArch64_Bcc = 351, - AArch64_CASAB = 352, - AArch64_CASAH = 353, - AArch64_CASALB = 354, - AArch64_CASALH = 355, - AArch64_CASALW = 356, - AArch64_CASALX = 357, - AArch64_CASAW = 358, - AArch64_CASAX = 359, - AArch64_CASB = 360, - AArch64_CASH = 361, - AArch64_CASLB = 362, - AArch64_CASLH = 363, - AArch64_CASLW = 364, - AArch64_CASLX = 365, - AArch64_CASPALW = 366, - AArch64_CASPALX = 367, - AArch64_CASPAW = 368, - AArch64_CASPAX = 369, - AArch64_CASPLW = 370, - AArch64_CASPLX = 371, - AArch64_CASPW = 372, - AArch64_CASPX = 373, - AArch64_CASW = 374, - AArch64_CASX = 375, - AArch64_CBNZW = 376, - AArch64_CBNZX = 377, - AArch64_CBZW = 378, - AArch64_CBZX = 379, - AArch64_CCMNWi = 380, - AArch64_CCMNWr = 381, - AArch64_CCMNXi = 382, - AArch64_CCMNXr = 383, - AArch64_CCMPWi = 384, - AArch64_CCMPWr = 385, - AArch64_CCMPXi = 386, - AArch64_CCMPXr = 387, - AArch64_CFINV = 388, - AArch64_CLASTA_RPZ_B = 389, - AArch64_CLASTA_RPZ_D = 390, - AArch64_CLASTA_RPZ_H = 391, - AArch64_CLASTA_RPZ_S = 392, - AArch64_CLASTA_VPZ_B = 393, - AArch64_CLASTA_VPZ_D = 394, - AArch64_CLASTA_VPZ_H = 395, - AArch64_CLASTA_VPZ_S = 396, - AArch64_CLASTA_ZPZ_B = 397, - AArch64_CLASTA_ZPZ_D = 398, - AArch64_CLASTA_ZPZ_H = 399, - AArch64_CLASTA_ZPZ_S = 400, - AArch64_CLASTB_RPZ_B = 401, - AArch64_CLASTB_RPZ_D = 402, - AArch64_CLASTB_RPZ_H = 403, - AArch64_CLASTB_RPZ_S = 404, - AArch64_CLASTB_VPZ_B = 405, - AArch64_CLASTB_VPZ_D = 406, - AArch64_CLASTB_VPZ_H = 407, - AArch64_CLASTB_VPZ_S = 408, - AArch64_CLASTB_ZPZ_B = 409, - AArch64_CLASTB_ZPZ_D = 410, - AArch64_CLASTB_ZPZ_H = 411, - AArch64_CLASTB_ZPZ_S = 412, - AArch64_CLREX = 413, - AArch64_CLSWr = 414, - AArch64_CLSXr = 415, - AArch64_CLS_ZPmZ_B = 416, - AArch64_CLS_ZPmZ_D = 417, - AArch64_CLS_ZPmZ_H = 418, - AArch64_CLS_ZPmZ_S = 419, - AArch64_CLSv16i8 = 420, - AArch64_CLSv2i32 = 421, - AArch64_CLSv4i16 = 422, - AArch64_CLSv4i32 = 423, - AArch64_CLSv8i16 = 424, - AArch64_CLSv8i8 = 425, - AArch64_CLZWr = 426, - AArch64_CLZXr = 427, - AArch64_CLZ_ZPmZ_B = 428, - AArch64_CLZ_ZPmZ_D = 429, - AArch64_CLZ_ZPmZ_H = 430, - AArch64_CLZ_ZPmZ_S = 431, - AArch64_CLZv16i8 = 432, - AArch64_CLZv2i32 = 433, - AArch64_CLZv4i16 = 434, - AArch64_CLZv4i32 = 435, - AArch64_CLZv8i16 = 436, - AArch64_CLZv8i8 = 437, - AArch64_CMEQv16i8 = 438, - AArch64_CMEQv16i8rz = 439, - AArch64_CMEQv1i64 = 440, - AArch64_CMEQv1i64rz = 441, - AArch64_CMEQv2i32 = 442, - AArch64_CMEQv2i32rz = 443, - AArch64_CMEQv2i64 = 444, - AArch64_CMEQv2i64rz = 445, - AArch64_CMEQv4i16 = 446, - AArch64_CMEQv4i16rz = 447, - AArch64_CMEQv4i32 = 448, - AArch64_CMEQv4i32rz = 449, - AArch64_CMEQv8i16 = 450, - AArch64_CMEQv8i16rz = 451, - AArch64_CMEQv8i8 = 452, - AArch64_CMEQv8i8rz = 453, - AArch64_CMGEv16i8 = 454, - AArch64_CMGEv16i8rz = 455, - AArch64_CMGEv1i64 = 456, - AArch64_CMGEv1i64rz = 457, - AArch64_CMGEv2i32 = 458, - AArch64_CMGEv2i32rz = 459, - AArch64_CMGEv2i64 = 460, - AArch64_CMGEv2i64rz = 461, - AArch64_CMGEv4i16 = 462, - AArch64_CMGEv4i16rz = 463, - AArch64_CMGEv4i32 = 464, - AArch64_CMGEv4i32rz = 465, - AArch64_CMGEv8i16 = 466, - AArch64_CMGEv8i16rz = 467, - AArch64_CMGEv8i8 = 468, - AArch64_CMGEv8i8rz = 469, - AArch64_CMGTv16i8 = 470, - AArch64_CMGTv16i8rz = 471, - AArch64_CMGTv1i64 = 472, - AArch64_CMGTv1i64rz = 473, - AArch64_CMGTv2i32 = 474, - AArch64_CMGTv2i32rz = 475, - AArch64_CMGTv2i64 = 476, - AArch64_CMGTv2i64rz = 477, - AArch64_CMGTv4i16 = 478, - AArch64_CMGTv4i16rz = 479, - AArch64_CMGTv4i32 = 480, - AArch64_CMGTv4i32rz = 481, - AArch64_CMGTv8i16 = 482, - AArch64_CMGTv8i16rz = 483, - AArch64_CMGTv8i8 = 484, - AArch64_CMGTv8i8rz = 485, - AArch64_CMHIv16i8 = 486, - AArch64_CMHIv1i64 = 487, - AArch64_CMHIv2i32 = 488, - AArch64_CMHIv2i64 = 489, - AArch64_CMHIv4i16 = 490, - AArch64_CMHIv4i32 = 491, - AArch64_CMHIv8i16 = 492, - AArch64_CMHIv8i8 = 493, - AArch64_CMHSv16i8 = 494, - AArch64_CMHSv1i64 = 495, - AArch64_CMHSv2i32 = 496, - AArch64_CMHSv2i64 = 497, - AArch64_CMHSv4i16 = 498, - AArch64_CMHSv4i32 = 499, - AArch64_CMHSv8i16 = 500, - AArch64_CMHSv8i8 = 501, - AArch64_CMLEv16i8rz = 502, - AArch64_CMLEv1i64rz = 503, - AArch64_CMLEv2i32rz = 504, - AArch64_CMLEv2i64rz = 505, - AArch64_CMLEv4i16rz = 506, - AArch64_CMLEv4i32rz = 507, - AArch64_CMLEv8i16rz = 508, - AArch64_CMLEv8i8rz = 509, - AArch64_CMLTv16i8rz = 510, - AArch64_CMLTv1i64rz = 511, - AArch64_CMLTv2i32rz = 512, - AArch64_CMLTv2i64rz = 513, - AArch64_CMLTv4i16rz = 514, - AArch64_CMLTv4i32rz = 515, - AArch64_CMLTv8i16rz = 516, - AArch64_CMLTv8i8rz = 517, - AArch64_CMPEQ_PPzZI_B = 518, - AArch64_CMPEQ_PPzZI_D = 519, - AArch64_CMPEQ_PPzZI_H = 520, - AArch64_CMPEQ_PPzZI_S = 521, - AArch64_CMPEQ_PPzZZ_B = 522, - AArch64_CMPEQ_PPzZZ_D = 523, - AArch64_CMPEQ_PPzZZ_H = 524, - AArch64_CMPEQ_PPzZZ_S = 525, - AArch64_CMPEQ_WIDE_PPzZZ_B = 526, - AArch64_CMPEQ_WIDE_PPzZZ_H = 527, - AArch64_CMPEQ_WIDE_PPzZZ_S = 528, - AArch64_CMPGE_PPzZI_B = 529, - AArch64_CMPGE_PPzZI_D = 530, - AArch64_CMPGE_PPzZI_H = 531, - AArch64_CMPGE_PPzZI_S = 532, - AArch64_CMPGE_PPzZZ_B = 533, - AArch64_CMPGE_PPzZZ_D = 534, - AArch64_CMPGE_PPzZZ_H = 535, - AArch64_CMPGE_PPzZZ_S = 536, - AArch64_CMPGE_WIDE_PPzZZ_B = 537, - AArch64_CMPGE_WIDE_PPzZZ_H = 538, - AArch64_CMPGE_WIDE_PPzZZ_S = 539, - AArch64_CMPGT_PPzZI_B = 540, - AArch64_CMPGT_PPzZI_D = 541, - AArch64_CMPGT_PPzZI_H = 542, - AArch64_CMPGT_PPzZI_S = 543, - AArch64_CMPGT_PPzZZ_B = 544, - AArch64_CMPGT_PPzZZ_D = 545, - AArch64_CMPGT_PPzZZ_H = 546, - AArch64_CMPGT_PPzZZ_S = 547, - AArch64_CMPGT_WIDE_PPzZZ_B = 548, - AArch64_CMPGT_WIDE_PPzZZ_H = 549, - AArch64_CMPGT_WIDE_PPzZZ_S = 550, - AArch64_CMPHI_PPzZI_B = 551, - AArch64_CMPHI_PPzZI_D = 552, - AArch64_CMPHI_PPzZI_H = 553, - AArch64_CMPHI_PPzZI_S = 554, - AArch64_CMPHI_PPzZZ_B = 555, - AArch64_CMPHI_PPzZZ_D = 556, - AArch64_CMPHI_PPzZZ_H = 557, - AArch64_CMPHI_PPzZZ_S = 558, - AArch64_CMPHI_WIDE_PPzZZ_B = 559, - AArch64_CMPHI_WIDE_PPzZZ_H = 560, - AArch64_CMPHI_WIDE_PPzZZ_S = 561, - AArch64_CMPHS_PPzZI_B = 562, - AArch64_CMPHS_PPzZI_D = 563, - AArch64_CMPHS_PPzZI_H = 564, - AArch64_CMPHS_PPzZI_S = 565, - AArch64_CMPHS_PPzZZ_B = 566, - AArch64_CMPHS_PPzZZ_D = 567, - AArch64_CMPHS_PPzZZ_H = 568, - AArch64_CMPHS_PPzZZ_S = 569, - AArch64_CMPHS_WIDE_PPzZZ_B = 570, - AArch64_CMPHS_WIDE_PPzZZ_H = 571, - AArch64_CMPHS_WIDE_PPzZZ_S = 572, - AArch64_CMPLE_PPzZI_B = 573, - AArch64_CMPLE_PPzZI_D = 574, - AArch64_CMPLE_PPzZI_H = 575, - AArch64_CMPLE_PPzZI_S = 576, - AArch64_CMPLE_WIDE_PPzZZ_B = 577, - AArch64_CMPLE_WIDE_PPzZZ_H = 578, - AArch64_CMPLE_WIDE_PPzZZ_S = 579, - AArch64_CMPLO_PPzZI_B = 580, - AArch64_CMPLO_PPzZI_D = 581, - AArch64_CMPLO_PPzZI_H = 582, - AArch64_CMPLO_PPzZI_S = 583, - AArch64_CMPLO_WIDE_PPzZZ_B = 584, - AArch64_CMPLO_WIDE_PPzZZ_H = 585, - AArch64_CMPLO_WIDE_PPzZZ_S = 586, - AArch64_CMPLS_PPzZI_B = 587, - AArch64_CMPLS_PPzZI_D = 588, - AArch64_CMPLS_PPzZI_H = 589, - AArch64_CMPLS_PPzZI_S = 590, - AArch64_CMPLS_WIDE_PPzZZ_B = 591, - AArch64_CMPLS_WIDE_PPzZZ_H = 592, - AArch64_CMPLS_WIDE_PPzZZ_S = 593, - AArch64_CMPLT_PPzZI_B = 594, - AArch64_CMPLT_PPzZI_D = 595, - AArch64_CMPLT_PPzZI_H = 596, - AArch64_CMPLT_PPzZI_S = 597, - AArch64_CMPLT_WIDE_PPzZZ_B = 598, - AArch64_CMPLT_WIDE_PPzZZ_H = 599, - AArch64_CMPLT_WIDE_PPzZZ_S = 600, - AArch64_CMPNE_PPzZI_B = 601, - AArch64_CMPNE_PPzZI_D = 602, - AArch64_CMPNE_PPzZI_H = 603, - AArch64_CMPNE_PPzZI_S = 604, - AArch64_CMPNE_PPzZZ_B = 605, - AArch64_CMPNE_PPzZZ_D = 606, - AArch64_CMPNE_PPzZZ_H = 607, - AArch64_CMPNE_PPzZZ_S = 608, - AArch64_CMPNE_WIDE_PPzZZ_B = 609, - AArch64_CMPNE_WIDE_PPzZZ_H = 610, - AArch64_CMPNE_WIDE_PPzZZ_S = 611, - AArch64_CMP_SWAP_128 = 612, - AArch64_CMP_SWAP_16 = 613, - AArch64_CMP_SWAP_32 = 614, - AArch64_CMP_SWAP_64 = 615, - AArch64_CMP_SWAP_8 = 616, - AArch64_CMTSTv16i8 = 617, - AArch64_CMTSTv1i64 = 618, - AArch64_CMTSTv2i32 = 619, - AArch64_CMTSTv2i64 = 620, - AArch64_CMTSTv4i16 = 621, - AArch64_CMTSTv4i32 = 622, - AArch64_CMTSTv8i16 = 623, - AArch64_CMTSTv8i8 = 624, - AArch64_CNOT_ZPmZ_B = 625, - AArch64_CNOT_ZPmZ_D = 626, - AArch64_CNOT_ZPmZ_H = 627, - AArch64_CNOT_ZPmZ_S = 628, - AArch64_CNTB_XPiI = 629, - AArch64_CNTD_XPiI = 630, - AArch64_CNTH_XPiI = 631, - AArch64_CNTP_XPP_B = 632, - AArch64_CNTP_XPP_D = 633, - AArch64_CNTP_XPP_H = 634, - AArch64_CNTP_XPP_S = 635, - AArch64_CNTW_XPiI = 636, - AArch64_CNT_ZPmZ_B = 637, - AArch64_CNT_ZPmZ_D = 638, - AArch64_CNT_ZPmZ_H = 639, - AArch64_CNT_ZPmZ_S = 640, - AArch64_CNTv16i8 = 641, - AArch64_CNTv8i8 = 642, - AArch64_COMPACT_ZPZ_D = 643, - AArch64_COMPACT_ZPZ_S = 644, - AArch64_CPY_ZPmI_B = 645, - AArch64_CPY_ZPmI_D = 646, - AArch64_CPY_ZPmI_H = 647, - AArch64_CPY_ZPmI_S = 648, - AArch64_CPY_ZPmR_B = 649, - AArch64_CPY_ZPmR_D = 650, - AArch64_CPY_ZPmR_H = 651, - AArch64_CPY_ZPmR_S = 652, - AArch64_CPY_ZPmV_B = 653, - AArch64_CPY_ZPmV_D = 654, - AArch64_CPY_ZPmV_H = 655, - AArch64_CPY_ZPmV_S = 656, - AArch64_CPY_ZPzI_B = 657, - AArch64_CPY_ZPzI_D = 658, - AArch64_CPY_ZPzI_H = 659, - AArch64_CPY_ZPzI_S = 660, - AArch64_CPYi16 = 661, - AArch64_CPYi32 = 662, - AArch64_CPYi64 = 663, - AArch64_CPYi8 = 664, - AArch64_CRC32Brr = 665, - AArch64_CRC32CBrr = 666, - AArch64_CRC32CHrr = 667, - AArch64_CRC32CWrr = 668, - AArch64_CRC32CXrr = 669, - AArch64_CRC32Hrr = 670, - AArch64_CRC32Wrr = 671, - AArch64_CRC32Xrr = 672, - AArch64_CSELWr = 673, - AArch64_CSELXr = 674, - AArch64_CSINCWr = 675, - AArch64_CSINCXr = 676, - AArch64_CSINVWr = 677, - AArch64_CSINVXr = 678, - AArch64_CSNEGWr = 679, - AArch64_CSNEGXr = 680, - AArch64_CTERMEQ_WW = 681, - AArch64_CTERMEQ_XX = 682, - AArch64_CTERMNE_WW = 683, - AArch64_CTERMNE_XX = 684, - AArch64_CompilerBarrier = 685, - AArch64_DCPS1 = 686, - AArch64_DCPS2 = 687, - AArch64_DCPS3 = 688, - AArch64_DECB_XPiI = 689, - AArch64_DECD_XPiI = 690, - AArch64_DECD_ZPiI = 691, - AArch64_DECH_XPiI = 692, - AArch64_DECH_ZPiI = 693, - AArch64_DECP_XP_B = 694, - AArch64_DECP_XP_D = 695, - AArch64_DECP_XP_H = 696, - AArch64_DECP_XP_S = 697, - AArch64_DECP_ZP_D = 698, - AArch64_DECP_ZP_H = 699, - AArch64_DECP_ZP_S = 700, - AArch64_DECW_XPiI = 701, - AArch64_DECW_ZPiI = 702, - AArch64_DMB = 703, - AArch64_DRPS = 704, - AArch64_DSB = 705, - AArch64_DUPM_ZI = 706, - AArch64_DUP_ZI_B = 707, - AArch64_DUP_ZI_D = 708, - AArch64_DUP_ZI_H = 709, - AArch64_DUP_ZI_S = 710, - AArch64_DUP_ZR_B = 711, - AArch64_DUP_ZR_D = 712, - AArch64_DUP_ZR_H = 713, - AArch64_DUP_ZR_S = 714, - AArch64_DUP_ZZI_B = 715, - AArch64_DUP_ZZI_D = 716, - AArch64_DUP_ZZI_H = 717, - AArch64_DUP_ZZI_Q = 718, - AArch64_DUP_ZZI_S = 719, - AArch64_DUPv16i8gpr = 720, - AArch64_DUPv16i8lane = 721, - AArch64_DUPv2i32gpr = 722, - AArch64_DUPv2i32lane = 723, - AArch64_DUPv2i64gpr = 724, - AArch64_DUPv2i64lane = 725, - AArch64_DUPv4i16gpr = 726, - AArch64_DUPv4i16lane = 727, - AArch64_DUPv4i32gpr = 728, - AArch64_DUPv4i32lane = 729, - AArch64_DUPv8i16gpr = 730, - AArch64_DUPv8i16lane = 731, - AArch64_DUPv8i8gpr = 732, - AArch64_DUPv8i8lane = 733, - AArch64_EONWrr = 734, - AArch64_EONWrs = 735, - AArch64_EONXrr = 736, - AArch64_EONXrs = 737, - AArch64_EOR3 = 738, - AArch64_EORS_PPzPP = 739, - AArch64_EORV_VPZ_B = 740, - AArch64_EORV_VPZ_D = 741, - AArch64_EORV_VPZ_H = 742, - AArch64_EORV_VPZ_S = 743, - AArch64_EORWri = 744, - AArch64_EORWrr = 745, - AArch64_EORWrs = 746, - AArch64_EORXri = 747, - AArch64_EORXrr = 748, - AArch64_EORXrs = 749, - AArch64_EOR_PPzPP = 750, - AArch64_EOR_ZI = 751, - AArch64_EOR_ZPmZ_B = 752, - AArch64_EOR_ZPmZ_D = 753, - AArch64_EOR_ZPmZ_H = 754, - AArch64_EOR_ZPmZ_S = 755, - AArch64_EOR_ZZZ = 756, - AArch64_EORv16i8 = 757, - AArch64_EORv8i8 = 758, - AArch64_ERET = 759, - AArch64_ERETAA = 760, - AArch64_ERETAB = 761, - AArch64_EXTRWrri = 762, - AArch64_EXTRXrri = 763, - AArch64_EXT_ZZI = 764, - AArch64_EXTv16i8 = 765, - AArch64_EXTv8i8 = 766, - AArch64_F128CSEL = 767, - AArch64_FABD16 = 768, - AArch64_FABD32 = 769, - AArch64_FABD64 = 770, - AArch64_FABD_ZPmZ_D = 771, - AArch64_FABD_ZPmZ_H = 772, - AArch64_FABD_ZPmZ_S = 773, - AArch64_FABDv2f32 = 774, - AArch64_FABDv2f64 = 775, - AArch64_FABDv4f16 = 776, - AArch64_FABDv4f32 = 777, - AArch64_FABDv8f16 = 778, - AArch64_FABSDr = 779, - AArch64_FABSHr = 780, - AArch64_FABSSr = 781, - AArch64_FABS_ZPmZ_D = 782, - AArch64_FABS_ZPmZ_H = 783, - AArch64_FABS_ZPmZ_S = 784, - AArch64_FABSv2f32 = 785, - AArch64_FABSv2f64 = 786, - AArch64_FABSv4f16 = 787, - AArch64_FABSv4f32 = 788, - AArch64_FABSv8f16 = 789, - AArch64_FACGE16 = 790, - AArch64_FACGE32 = 791, - AArch64_FACGE64 = 792, - AArch64_FACGE_PPzZZ_D = 793, - AArch64_FACGE_PPzZZ_H = 794, - AArch64_FACGE_PPzZZ_S = 795, - AArch64_FACGEv2f32 = 796, - AArch64_FACGEv2f64 = 797, - AArch64_FACGEv4f16 = 798, - AArch64_FACGEv4f32 = 799, - AArch64_FACGEv8f16 = 800, - AArch64_FACGT16 = 801, - AArch64_FACGT32 = 802, - AArch64_FACGT64 = 803, - AArch64_FACGT_PPzZZ_D = 804, - AArch64_FACGT_PPzZZ_H = 805, - AArch64_FACGT_PPzZZ_S = 806, - AArch64_FACGTv2f32 = 807, - AArch64_FACGTv2f64 = 808, - AArch64_FACGTv4f16 = 809, - AArch64_FACGTv4f32 = 810, - AArch64_FACGTv8f16 = 811, - AArch64_FADDA_VPZ_D = 812, - AArch64_FADDA_VPZ_H = 813, - AArch64_FADDA_VPZ_S = 814, - AArch64_FADDDrr = 815, - AArch64_FADDHrr = 816, - AArch64_FADDPv2f32 = 817, - AArch64_FADDPv2f64 = 818, - AArch64_FADDPv2i16p = 819, - AArch64_FADDPv2i32p = 820, - AArch64_FADDPv2i64p = 821, - AArch64_FADDPv4f16 = 822, - AArch64_FADDPv4f32 = 823, - AArch64_FADDPv8f16 = 824, - AArch64_FADDSrr = 825, - AArch64_FADDV_VPZ_D = 826, - AArch64_FADDV_VPZ_H = 827, - AArch64_FADDV_VPZ_S = 828, - AArch64_FADD_ZPmI_D = 829, - AArch64_FADD_ZPmI_H = 830, - AArch64_FADD_ZPmI_S = 831, - AArch64_FADD_ZPmZ_D = 832, - AArch64_FADD_ZPmZ_H = 833, - AArch64_FADD_ZPmZ_S = 834, - AArch64_FADD_ZZZ_D = 835, - AArch64_FADD_ZZZ_H = 836, - AArch64_FADD_ZZZ_S = 837, - AArch64_FADDv2f32 = 838, - AArch64_FADDv2f64 = 839, - AArch64_FADDv4f16 = 840, - AArch64_FADDv4f32 = 841, - AArch64_FADDv8f16 = 842, - AArch64_FCADD_ZPmZ_D = 843, - AArch64_FCADD_ZPmZ_H = 844, - AArch64_FCADD_ZPmZ_S = 845, - AArch64_FCADDv2f32 = 846, - AArch64_FCADDv2f64 = 847, - AArch64_FCADDv4f16 = 848, - AArch64_FCADDv4f32 = 849, - AArch64_FCADDv8f16 = 850, - AArch64_FCCMPDrr = 851, - AArch64_FCCMPEDrr = 852, - AArch64_FCCMPEHrr = 853, - AArch64_FCCMPESrr = 854, - AArch64_FCCMPHrr = 855, - AArch64_FCCMPSrr = 856, - AArch64_FCMEQ16 = 857, - AArch64_FCMEQ32 = 858, - AArch64_FCMEQ64 = 859, - AArch64_FCMEQ_PPzZ0_D = 860, - AArch64_FCMEQ_PPzZ0_H = 861, - AArch64_FCMEQ_PPzZ0_S = 862, - AArch64_FCMEQ_PPzZZ_D = 863, - AArch64_FCMEQ_PPzZZ_H = 864, - AArch64_FCMEQ_PPzZZ_S = 865, - AArch64_FCMEQv1i16rz = 866, - AArch64_FCMEQv1i32rz = 867, - AArch64_FCMEQv1i64rz = 868, - AArch64_FCMEQv2f32 = 869, - AArch64_FCMEQv2f64 = 870, - AArch64_FCMEQv2i32rz = 871, - AArch64_FCMEQv2i64rz = 872, - AArch64_FCMEQv4f16 = 873, - AArch64_FCMEQv4f32 = 874, - AArch64_FCMEQv4i16rz = 875, - AArch64_FCMEQv4i32rz = 876, - AArch64_FCMEQv8f16 = 877, - AArch64_FCMEQv8i16rz = 878, - AArch64_FCMGE16 = 879, - AArch64_FCMGE32 = 880, - AArch64_FCMGE64 = 881, - AArch64_FCMGE_PPzZ0_D = 882, - AArch64_FCMGE_PPzZ0_H = 883, - AArch64_FCMGE_PPzZ0_S = 884, - AArch64_FCMGE_PPzZZ_D = 885, - AArch64_FCMGE_PPzZZ_H = 886, - AArch64_FCMGE_PPzZZ_S = 887, - AArch64_FCMGEv1i16rz = 888, - AArch64_FCMGEv1i32rz = 889, - AArch64_FCMGEv1i64rz = 890, - AArch64_FCMGEv2f32 = 891, - AArch64_FCMGEv2f64 = 892, - AArch64_FCMGEv2i32rz = 893, - AArch64_FCMGEv2i64rz = 894, - AArch64_FCMGEv4f16 = 895, - AArch64_FCMGEv4f32 = 896, - AArch64_FCMGEv4i16rz = 897, - AArch64_FCMGEv4i32rz = 898, - AArch64_FCMGEv8f16 = 899, - AArch64_FCMGEv8i16rz = 900, - AArch64_FCMGT16 = 901, - AArch64_FCMGT32 = 902, - AArch64_FCMGT64 = 903, - AArch64_FCMGT_PPzZ0_D = 904, - AArch64_FCMGT_PPzZ0_H = 905, - AArch64_FCMGT_PPzZ0_S = 906, - AArch64_FCMGT_PPzZZ_D = 907, - AArch64_FCMGT_PPzZZ_H = 908, - AArch64_FCMGT_PPzZZ_S = 909, - AArch64_FCMGTv1i16rz = 910, - AArch64_FCMGTv1i32rz = 911, - AArch64_FCMGTv1i64rz = 912, - AArch64_FCMGTv2f32 = 913, - AArch64_FCMGTv2f64 = 914, - AArch64_FCMGTv2i32rz = 915, - AArch64_FCMGTv2i64rz = 916, - AArch64_FCMGTv4f16 = 917, - AArch64_FCMGTv4f32 = 918, - AArch64_FCMGTv4i16rz = 919, - AArch64_FCMGTv4i32rz = 920, - AArch64_FCMGTv8f16 = 921, - AArch64_FCMGTv8i16rz = 922, - AArch64_FCMLA_ZPmZZ_D = 923, - AArch64_FCMLA_ZPmZZ_H = 924, - AArch64_FCMLA_ZPmZZ_S = 925, - AArch64_FCMLA_ZZZI_H = 926, - AArch64_FCMLA_ZZZI_S = 927, - AArch64_FCMLAv2f32 = 928, - AArch64_FCMLAv2f64 = 929, - AArch64_FCMLAv4f16 = 930, - AArch64_FCMLAv4f16_indexed = 931, - AArch64_FCMLAv4f32 = 932, - AArch64_FCMLAv4f32_indexed = 933, - AArch64_FCMLAv8f16 = 934, - AArch64_FCMLAv8f16_indexed = 935, - AArch64_FCMLE_PPzZ0_D = 936, - AArch64_FCMLE_PPzZ0_H = 937, - AArch64_FCMLE_PPzZ0_S = 938, - AArch64_FCMLEv1i16rz = 939, - AArch64_FCMLEv1i32rz = 940, - AArch64_FCMLEv1i64rz = 941, - AArch64_FCMLEv2i32rz = 942, - AArch64_FCMLEv2i64rz = 943, - AArch64_FCMLEv4i16rz = 944, - AArch64_FCMLEv4i32rz = 945, - AArch64_FCMLEv8i16rz = 946, - AArch64_FCMLT_PPzZ0_D = 947, - AArch64_FCMLT_PPzZ0_H = 948, - AArch64_FCMLT_PPzZ0_S = 949, - AArch64_FCMLTv1i16rz = 950, - AArch64_FCMLTv1i32rz = 951, - AArch64_FCMLTv1i64rz = 952, - AArch64_FCMLTv2i32rz = 953, - AArch64_FCMLTv2i64rz = 954, - AArch64_FCMLTv4i16rz = 955, - AArch64_FCMLTv4i32rz = 956, - AArch64_FCMLTv8i16rz = 957, - AArch64_FCMNE_PPzZ0_D = 958, - AArch64_FCMNE_PPzZ0_H = 959, - AArch64_FCMNE_PPzZ0_S = 960, - AArch64_FCMNE_PPzZZ_D = 961, - AArch64_FCMNE_PPzZZ_H = 962, - AArch64_FCMNE_PPzZZ_S = 963, - AArch64_FCMPDri = 964, - AArch64_FCMPDrr = 965, - AArch64_FCMPEDri = 966, - AArch64_FCMPEDrr = 967, - AArch64_FCMPEHri = 968, - AArch64_FCMPEHrr = 969, - AArch64_FCMPESri = 970, - AArch64_FCMPESrr = 971, - AArch64_FCMPHri = 972, - AArch64_FCMPHrr = 973, - AArch64_FCMPSri = 974, - AArch64_FCMPSrr = 975, - AArch64_FCMUO_PPzZZ_D = 976, - AArch64_FCMUO_PPzZZ_H = 977, - AArch64_FCMUO_PPzZZ_S = 978, - AArch64_FCPY_ZPmI_D = 979, - AArch64_FCPY_ZPmI_H = 980, - AArch64_FCPY_ZPmI_S = 981, - AArch64_FCSELDrrr = 982, - AArch64_FCSELHrrr = 983, - AArch64_FCSELSrrr = 984, - AArch64_FCVTASUWDr = 985, - AArch64_FCVTASUWHr = 986, - AArch64_FCVTASUWSr = 987, - AArch64_FCVTASUXDr = 988, - AArch64_FCVTASUXHr = 989, - AArch64_FCVTASUXSr = 990, - AArch64_FCVTASv1f16 = 991, - AArch64_FCVTASv1i32 = 992, - AArch64_FCVTASv1i64 = 993, - AArch64_FCVTASv2f32 = 994, - AArch64_FCVTASv2f64 = 995, - AArch64_FCVTASv4f16 = 996, - AArch64_FCVTASv4f32 = 997, - AArch64_FCVTASv8f16 = 998, - AArch64_FCVTAUUWDr = 999, - AArch64_FCVTAUUWHr = 1000, - AArch64_FCVTAUUWSr = 1001, - AArch64_FCVTAUUXDr = 1002, - AArch64_FCVTAUUXHr = 1003, - AArch64_FCVTAUUXSr = 1004, - AArch64_FCVTAUv1f16 = 1005, - AArch64_FCVTAUv1i32 = 1006, - AArch64_FCVTAUv1i64 = 1007, - AArch64_FCVTAUv2f32 = 1008, - AArch64_FCVTAUv2f64 = 1009, - AArch64_FCVTAUv4f16 = 1010, - AArch64_FCVTAUv4f32 = 1011, - AArch64_FCVTAUv8f16 = 1012, - AArch64_FCVTDHr = 1013, - AArch64_FCVTDSr = 1014, - AArch64_FCVTHDr = 1015, - AArch64_FCVTHSr = 1016, - AArch64_FCVTLv2i32 = 1017, - AArch64_FCVTLv4i16 = 1018, - AArch64_FCVTLv4i32 = 1019, - AArch64_FCVTLv8i16 = 1020, - AArch64_FCVTMSUWDr = 1021, - AArch64_FCVTMSUWHr = 1022, - AArch64_FCVTMSUWSr = 1023, - AArch64_FCVTMSUXDr = 1024, - AArch64_FCVTMSUXHr = 1025, - AArch64_FCVTMSUXSr = 1026, - AArch64_FCVTMSv1f16 = 1027, - AArch64_FCVTMSv1i32 = 1028, - AArch64_FCVTMSv1i64 = 1029, - AArch64_FCVTMSv2f32 = 1030, - AArch64_FCVTMSv2f64 = 1031, - AArch64_FCVTMSv4f16 = 1032, - AArch64_FCVTMSv4f32 = 1033, - AArch64_FCVTMSv8f16 = 1034, - AArch64_FCVTMUUWDr = 1035, - AArch64_FCVTMUUWHr = 1036, - AArch64_FCVTMUUWSr = 1037, - AArch64_FCVTMUUXDr = 1038, - AArch64_FCVTMUUXHr = 1039, - AArch64_FCVTMUUXSr = 1040, - AArch64_FCVTMUv1f16 = 1041, - AArch64_FCVTMUv1i32 = 1042, - AArch64_FCVTMUv1i64 = 1043, - AArch64_FCVTMUv2f32 = 1044, - AArch64_FCVTMUv2f64 = 1045, - AArch64_FCVTMUv4f16 = 1046, - AArch64_FCVTMUv4f32 = 1047, - AArch64_FCVTMUv8f16 = 1048, - AArch64_FCVTNSUWDr = 1049, - AArch64_FCVTNSUWHr = 1050, - AArch64_FCVTNSUWSr = 1051, - AArch64_FCVTNSUXDr = 1052, - AArch64_FCVTNSUXHr = 1053, - AArch64_FCVTNSUXSr = 1054, - AArch64_FCVTNSv1f16 = 1055, - AArch64_FCVTNSv1i32 = 1056, - AArch64_FCVTNSv1i64 = 1057, - AArch64_FCVTNSv2f32 = 1058, - AArch64_FCVTNSv2f64 = 1059, - AArch64_FCVTNSv4f16 = 1060, - AArch64_FCVTNSv4f32 = 1061, - AArch64_FCVTNSv8f16 = 1062, - AArch64_FCVTNUUWDr = 1063, - AArch64_FCVTNUUWHr = 1064, - AArch64_FCVTNUUWSr = 1065, - AArch64_FCVTNUUXDr = 1066, - AArch64_FCVTNUUXHr = 1067, - AArch64_FCVTNUUXSr = 1068, - AArch64_FCVTNUv1f16 = 1069, - AArch64_FCVTNUv1i32 = 1070, - AArch64_FCVTNUv1i64 = 1071, - AArch64_FCVTNUv2f32 = 1072, - AArch64_FCVTNUv2f64 = 1073, - AArch64_FCVTNUv4f16 = 1074, - AArch64_FCVTNUv4f32 = 1075, - AArch64_FCVTNUv8f16 = 1076, - AArch64_FCVTNv2i32 = 1077, - AArch64_FCVTNv4i16 = 1078, - AArch64_FCVTNv4i32 = 1079, - AArch64_FCVTNv8i16 = 1080, - AArch64_FCVTPSUWDr = 1081, - AArch64_FCVTPSUWHr = 1082, - AArch64_FCVTPSUWSr = 1083, - AArch64_FCVTPSUXDr = 1084, - AArch64_FCVTPSUXHr = 1085, - AArch64_FCVTPSUXSr = 1086, - AArch64_FCVTPSv1f16 = 1087, - AArch64_FCVTPSv1i32 = 1088, - AArch64_FCVTPSv1i64 = 1089, - AArch64_FCVTPSv2f32 = 1090, - AArch64_FCVTPSv2f64 = 1091, - AArch64_FCVTPSv4f16 = 1092, - AArch64_FCVTPSv4f32 = 1093, - AArch64_FCVTPSv8f16 = 1094, - AArch64_FCVTPUUWDr = 1095, - AArch64_FCVTPUUWHr = 1096, - AArch64_FCVTPUUWSr = 1097, - AArch64_FCVTPUUXDr = 1098, - AArch64_FCVTPUUXHr = 1099, - AArch64_FCVTPUUXSr = 1100, - AArch64_FCVTPUv1f16 = 1101, - AArch64_FCVTPUv1i32 = 1102, - AArch64_FCVTPUv1i64 = 1103, - AArch64_FCVTPUv2f32 = 1104, - AArch64_FCVTPUv2f64 = 1105, - AArch64_FCVTPUv4f16 = 1106, - AArch64_FCVTPUv4f32 = 1107, - AArch64_FCVTPUv8f16 = 1108, - AArch64_FCVTSDr = 1109, - AArch64_FCVTSHr = 1110, - AArch64_FCVTXNv1i64 = 1111, - AArch64_FCVTXNv2f32 = 1112, - AArch64_FCVTXNv4f32 = 1113, - AArch64_FCVTZSSWDri = 1114, - AArch64_FCVTZSSWHri = 1115, - AArch64_FCVTZSSWSri = 1116, - AArch64_FCVTZSSXDri = 1117, - AArch64_FCVTZSSXHri = 1118, - AArch64_FCVTZSSXSri = 1119, - AArch64_FCVTZSUWDr = 1120, - AArch64_FCVTZSUWHr = 1121, - AArch64_FCVTZSUWSr = 1122, - AArch64_FCVTZSUXDr = 1123, - AArch64_FCVTZSUXHr = 1124, - AArch64_FCVTZSUXSr = 1125, - AArch64_FCVTZS_ZPmZ_DtoD = 1126, - AArch64_FCVTZS_ZPmZ_DtoS = 1127, - AArch64_FCVTZS_ZPmZ_HtoD = 1128, - AArch64_FCVTZS_ZPmZ_HtoH = 1129, - AArch64_FCVTZS_ZPmZ_HtoS = 1130, - AArch64_FCVTZS_ZPmZ_StoD = 1131, - AArch64_FCVTZS_ZPmZ_StoS = 1132, - AArch64_FCVTZSd = 1133, - AArch64_FCVTZSh = 1134, - AArch64_FCVTZSs = 1135, - AArch64_FCVTZSv1f16 = 1136, - AArch64_FCVTZSv1i32 = 1137, - AArch64_FCVTZSv1i64 = 1138, - AArch64_FCVTZSv2f32 = 1139, - AArch64_FCVTZSv2f64 = 1140, - AArch64_FCVTZSv2i32_shift = 1141, - AArch64_FCVTZSv2i64_shift = 1142, - AArch64_FCVTZSv4f16 = 1143, - AArch64_FCVTZSv4f32 = 1144, - AArch64_FCVTZSv4i16_shift = 1145, - AArch64_FCVTZSv4i32_shift = 1146, - AArch64_FCVTZSv8f16 = 1147, - AArch64_FCVTZSv8i16_shift = 1148, - AArch64_FCVTZUSWDri = 1149, - AArch64_FCVTZUSWHri = 1150, - AArch64_FCVTZUSWSri = 1151, - AArch64_FCVTZUSXDri = 1152, - AArch64_FCVTZUSXHri = 1153, - AArch64_FCVTZUSXSri = 1154, - AArch64_FCVTZUUWDr = 1155, - AArch64_FCVTZUUWHr = 1156, - AArch64_FCVTZUUWSr = 1157, - AArch64_FCVTZUUXDr = 1158, - AArch64_FCVTZUUXHr = 1159, - AArch64_FCVTZUUXSr = 1160, - AArch64_FCVTZU_ZPmZ_DtoD = 1161, - AArch64_FCVTZU_ZPmZ_DtoS = 1162, - AArch64_FCVTZU_ZPmZ_HtoD = 1163, - AArch64_FCVTZU_ZPmZ_HtoH = 1164, - AArch64_FCVTZU_ZPmZ_HtoS = 1165, - AArch64_FCVTZU_ZPmZ_StoD = 1166, - AArch64_FCVTZU_ZPmZ_StoS = 1167, - AArch64_FCVTZUd = 1168, - AArch64_FCVTZUh = 1169, - AArch64_FCVTZUs = 1170, - AArch64_FCVTZUv1f16 = 1171, - AArch64_FCVTZUv1i32 = 1172, - AArch64_FCVTZUv1i64 = 1173, - AArch64_FCVTZUv2f32 = 1174, - AArch64_FCVTZUv2f64 = 1175, - AArch64_FCVTZUv2i32_shift = 1176, - AArch64_FCVTZUv2i64_shift = 1177, - AArch64_FCVTZUv4f16 = 1178, - AArch64_FCVTZUv4f32 = 1179, - AArch64_FCVTZUv4i16_shift = 1180, - AArch64_FCVTZUv4i32_shift = 1181, - AArch64_FCVTZUv8f16 = 1182, - AArch64_FCVTZUv8i16_shift = 1183, - AArch64_FCVT_ZPmZ_DtoH = 1184, - AArch64_FCVT_ZPmZ_DtoS = 1185, - AArch64_FCVT_ZPmZ_HtoD = 1186, - AArch64_FCVT_ZPmZ_HtoS = 1187, - AArch64_FCVT_ZPmZ_StoD = 1188, - AArch64_FCVT_ZPmZ_StoH = 1189, - AArch64_FDIVDrr = 1190, - AArch64_FDIVHrr = 1191, - AArch64_FDIVR_ZPmZ_D = 1192, - AArch64_FDIVR_ZPmZ_H = 1193, - AArch64_FDIVR_ZPmZ_S = 1194, - AArch64_FDIVSrr = 1195, - AArch64_FDIV_ZPmZ_D = 1196, - AArch64_FDIV_ZPmZ_H = 1197, - AArch64_FDIV_ZPmZ_S = 1198, - AArch64_FDIVv2f32 = 1199, - AArch64_FDIVv2f64 = 1200, - AArch64_FDIVv4f16 = 1201, - AArch64_FDIVv4f32 = 1202, - AArch64_FDIVv8f16 = 1203, - AArch64_FDUP_ZI_D = 1204, - AArch64_FDUP_ZI_H = 1205, - AArch64_FDUP_ZI_S = 1206, - AArch64_FEXPA_ZZ_D = 1207, - AArch64_FEXPA_ZZ_H = 1208, - AArch64_FEXPA_ZZ_S = 1209, - AArch64_FJCVTZS = 1210, - AArch64_FMADDDrrr = 1211, - AArch64_FMADDHrrr = 1212, - AArch64_FMADDSrrr = 1213, - AArch64_FMAD_ZPmZZ_D = 1214, - AArch64_FMAD_ZPmZZ_H = 1215, - AArch64_FMAD_ZPmZZ_S = 1216, - AArch64_FMAXDrr = 1217, - AArch64_FMAXHrr = 1218, - AArch64_FMAXNMDrr = 1219, - AArch64_FMAXNMHrr = 1220, - AArch64_FMAXNMPv2f32 = 1221, - AArch64_FMAXNMPv2f64 = 1222, - AArch64_FMAXNMPv2i16p = 1223, - AArch64_FMAXNMPv2i32p = 1224, - AArch64_FMAXNMPv2i64p = 1225, - AArch64_FMAXNMPv4f16 = 1226, - AArch64_FMAXNMPv4f32 = 1227, - AArch64_FMAXNMPv8f16 = 1228, - AArch64_FMAXNMSrr = 1229, - AArch64_FMAXNMV_VPZ_D = 1230, - AArch64_FMAXNMV_VPZ_H = 1231, - AArch64_FMAXNMV_VPZ_S = 1232, - AArch64_FMAXNMVv4i16v = 1233, - AArch64_FMAXNMVv4i32v = 1234, - AArch64_FMAXNMVv8i16v = 1235, - AArch64_FMAXNM_ZPmI_D = 1236, - AArch64_FMAXNM_ZPmI_H = 1237, - AArch64_FMAXNM_ZPmI_S = 1238, - AArch64_FMAXNM_ZPmZ_D = 1239, - AArch64_FMAXNM_ZPmZ_H = 1240, - AArch64_FMAXNM_ZPmZ_S = 1241, - AArch64_FMAXNMv2f32 = 1242, - AArch64_FMAXNMv2f64 = 1243, - AArch64_FMAXNMv4f16 = 1244, - AArch64_FMAXNMv4f32 = 1245, - AArch64_FMAXNMv8f16 = 1246, - AArch64_FMAXPv2f32 = 1247, - AArch64_FMAXPv2f64 = 1248, - AArch64_FMAXPv2i16p = 1249, - AArch64_FMAXPv2i32p = 1250, - AArch64_FMAXPv2i64p = 1251, - AArch64_FMAXPv4f16 = 1252, - AArch64_FMAXPv4f32 = 1253, - AArch64_FMAXPv8f16 = 1254, - AArch64_FMAXSrr = 1255, - AArch64_FMAXV_VPZ_D = 1256, - AArch64_FMAXV_VPZ_H = 1257, - AArch64_FMAXV_VPZ_S = 1258, - AArch64_FMAXVv4i16v = 1259, - AArch64_FMAXVv4i32v = 1260, - AArch64_FMAXVv8i16v = 1261, - AArch64_FMAX_ZPmI_D = 1262, - AArch64_FMAX_ZPmI_H = 1263, - AArch64_FMAX_ZPmI_S = 1264, - AArch64_FMAX_ZPmZ_D = 1265, - AArch64_FMAX_ZPmZ_H = 1266, - AArch64_FMAX_ZPmZ_S = 1267, - AArch64_FMAXv2f32 = 1268, - AArch64_FMAXv2f64 = 1269, - AArch64_FMAXv4f16 = 1270, - AArch64_FMAXv4f32 = 1271, - AArch64_FMAXv8f16 = 1272, - AArch64_FMINDrr = 1273, - AArch64_FMINHrr = 1274, - AArch64_FMINNMDrr = 1275, - AArch64_FMINNMHrr = 1276, - AArch64_FMINNMPv2f32 = 1277, - AArch64_FMINNMPv2f64 = 1278, - AArch64_FMINNMPv2i16p = 1279, - AArch64_FMINNMPv2i32p = 1280, - AArch64_FMINNMPv2i64p = 1281, - AArch64_FMINNMPv4f16 = 1282, - AArch64_FMINNMPv4f32 = 1283, - AArch64_FMINNMPv8f16 = 1284, - AArch64_FMINNMSrr = 1285, - AArch64_FMINNMV_VPZ_D = 1286, - AArch64_FMINNMV_VPZ_H = 1287, - AArch64_FMINNMV_VPZ_S = 1288, - AArch64_FMINNMVv4i16v = 1289, - AArch64_FMINNMVv4i32v = 1290, - AArch64_FMINNMVv8i16v = 1291, - AArch64_FMINNM_ZPmI_D = 1292, - AArch64_FMINNM_ZPmI_H = 1293, - AArch64_FMINNM_ZPmI_S = 1294, - AArch64_FMINNM_ZPmZ_D = 1295, - AArch64_FMINNM_ZPmZ_H = 1296, - AArch64_FMINNM_ZPmZ_S = 1297, - AArch64_FMINNMv2f32 = 1298, - AArch64_FMINNMv2f64 = 1299, - AArch64_FMINNMv4f16 = 1300, - AArch64_FMINNMv4f32 = 1301, - AArch64_FMINNMv8f16 = 1302, - AArch64_FMINPv2f32 = 1303, - AArch64_FMINPv2f64 = 1304, - AArch64_FMINPv2i16p = 1305, - AArch64_FMINPv2i32p = 1306, - AArch64_FMINPv2i64p = 1307, - AArch64_FMINPv4f16 = 1308, - AArch64_FMINPv4f32 = 1309, - AArch64_FMINPv8f16 = 1310, - AArch64_FMINSrr = 1311, - AArch64_FMINV_VPZ_D = 1312, - AArch64_FMINV_VPZ_H = 1313, - AArch64_FMINV_VPZ_S = 1314, - AArch64_FMINVv4i16v = 1315, - AArch64_FMINVv4i32v = 1316, - AArch64_FMINVv8i16v = 1317, - AArch64_FMIN_ZPmI_D = 1318, - AArch64_FMIN_ZPmI_H = 1319, - AArch64_FMIN_ZPmI_S = 1320, - AArch64_FMIN_ZPmZ_D = 1321, - AArch64_FMIN_ZPmZ_H = 1322, - AArch64_FMIN_ZPmZ_S = 1323, - AArch64_FMINv2f32 = 1324, - AArch64_FMINv2f64 = 1325, - AArch64_FMINv4f16 = 1326, - AArch64_FMINv4f32 = 1327, - AArch64_FMINv8f16 = 1328, - AArch64_FMLA_ZPmZZ_D = 1329, - AArch64_FMLA_ZPmZZ_H = 1330, - AArch64_FMLA_ZPmZZ_S = 1331, - AArch64_FMLA_ZZZI_D = 1332, - AArch64_FMLA_ZZZI_H = 1333, - AArch64_FMLA_ZZZI_S = 1334, - AArch64_FMLAv1i16_indexed = 1335, - AArch64_FMLAv1i32_indexed = 1336, - AArch64_FMLAv1i64_indexed = 1337, - AArch64_FMLAv2f32 = 1338, - AArch64_FMLAv2f64 = 1339, - AArch64_FMLAv2i32_indexed = 1340, - AArch64_FMLAv2i64_indexed = 1341, - AArch64_FMLAv4f16 = 1342, - AArch64_FMLAv4f32 = 1343, - AArch64_FMLAv4i16_indexed = 1344, - AArch64_FMLAv4i32_indexed = 1345, - AArch64_FMLAv8f16 = 1346, - AArch64_FMLAv8i16_indexed = 1347, - AArch64_FMLS_ZPmZZ_D = 1348, - AArch64_FMLS_ZPmZZ_H = 1349, - AArch64_FMLS_ZPmZZ_S = 1350, - AArch64_FMLS_ZZZI_D = 1351, - AArch64_FMLS_ZZZI_H = 1352, - AArch64_FMLS_ZZZI_S = 1353, - AArch64_FMLSv1i16_indexed = 1354, - AArch64_FMLSv1i32_indexed = 1355, - AArch64_FMLSv1i64_indexed = 1356, - AArch64_FMLSv2f32 = 1357, - AArch64_FMLSv2f64 = 1358, - AArch64_FMLSv2i32_indexed = 1359, - AArch64_FMLSv2i64_indexed = 1360, - AArch64_FMLSv4f16 = 1361, - AArch64_FMLSv4f32 = 1362, - AArch64_FMLSv4i16_indexed = 1363, - AArch64_FMLSv4i32_indexed = 1364, - AArch64_FMLSv8f16 = 1365, - AArch64_FMLSv8i16_indexed = 1366, - AArch64_FMOVD0 = 1367, - AArch64_FMOVDXHighr = 1368, - AArch64_FMOVDXr = 1369, - AArch64_FMOVDi = 1370, - AArch64_FMOVDr = 1371, - AArch64_FMOVH0 = 1372, - AArch64_FMOVHWr = 1373, - AArch64_FMOVHXr = 1374, - AArch64_FMOVHi = 1375, - AArch64_FMOVHr = 1376, - AArch64_FMOVS0 = 1377, - AArch64_FMOVSWr = 1378, - AArch64_FMOVSi = 1379, - AArch64_FMOVSr = 1380, - AArch64_FMOVWHr = 1381, - AArch64_FMOVWSr = 1382, - AArch64_FMOVXDHighr = 1383, - AArch64_FMOVXDr = 1384, - AArch64_FMOVXHr = 1385, - AArch64_FMOVv2f32_ns = 1386, - AArch64_FMOVv2f64_ns = 1387, - AArch64_FMOVv4f16_ns = 1388, - AArch64_FMOVv4f32_ns = 1389, - AArch64_FMOVv8f16_ns = 1390, - AArch64_FMSB_ZPmZZ_D = 1391, - AArch64_FMSB_ZPmZZ_H = 1392, - AArch64_FMSB_ZPmZZ_S = 1393, - AArch64_FMSUBDrrr = 1394, - AArch64_FMSUBHrrr = 1395, - AArch64_FMSUBSrrr = 1396, - AArch64_FMULDrr = 1397, - AArch64_FMULHrr = 1398, - AArch64_FMULSrr = 1399, - AArch64_FMULX16 = 1400, - AArch64_FMULX32 = 1401, - AArch64_FMULX64 = 1402, - AArch64_FMULX_ZPmZ_D = 1403, - AArch64_FMULX_ZPmZ_H = 1404, - AArch64_FMULX_ZPmZ_S = 1405, - AArch64_FMULXv1i16_indexed = 1406, - AArch64_FMULXv1i32_indexed = 1407, - AArch64_FMULXv1i64_indexed = 1408, - AArch64_FMULXv2f32 = 1409, - AArch64_FMULXv2f64 = 1410, - AArch64_FMULXv2i32_indexed = 1411, - AArch64_FMULXv2i64_indexed = 1412, - AArch64_FMULXv4f16 = 1413, - AArch64_FMULXv4f32 = 1414, - AArch64_FMULXv4i16_indexed = 1415, - AArch64_FMULXv4i32_indexed = 1416, - AArch64_FMULXv8f16 = 1417, - AArch64_FMULXv8i16_indexed = 1418, - AArch64_FMUL_ZPmI_D = 1419, - AArch64_FMUL_ZPmI_H = 1420, - AArch64_FMUL_ZPmI_S = 1421, - AArch64_FMUL_ZPmZ_D = 1422, - AArch64_FMUL_ZPmZ_H = 1423, - AArch64_FMUL_ZPmZ_S = 1424, - AArch64_FMUL_ZZZI_D = 1425, - AArch64_FMUL_ZZZI_H = 1426, - AArch64_FMUL_ZZZI_S = 1427, - AArch64_FMUL_ZZZ_D = 1428, - AArch64_FMUL_ZZZ_H = 1429, - AArch64_FMUL_ZZZ_S = 1430, - AArch64_FMULv1i16_indexed = 1431, - AArch64_FMULv1i32_indexed = 1432, - AArch64_FMULv1i64_indexed = 1433, - AArch64_FMULv2f32 = 1434, - AArch64_FMULv2f64 = 1435, - AArch64_FMULv2i32_indexed = 1436, - AArch64_FMULv2i64_indexed = 1437, - AArch64_FMULv4f16 = 1438, - AArch64_FMULv4f32 = 1439, - AArch64_FMULv4i16_indexed = 1440, - AArch64_FMULv4i32_indexed = 1441, - AArch64_FMULv8f16 = 1442, - AArch64_FMULv8i16_indexed = 1443, - AArch64_FNEGDr = 1444, - AArch64_FNEGHr = 1445, - AArch64_FNEGSr = 1446, - AArch64_FNEG_ZPmZ_D = 1447, - AArch64_FNEG_ZPmZ_H = 1448, - AArch64_FNEG_ZPmZ_S = 1449, - AArch64_FNEGv2f32 = 1450, - AArch64_FNEGv2f64 = 1451, - AArch64_FNEGv4f16 = 1452, - AArch64_FNEGv4f32 = 1453, - AArch64_FNEGv8f16 = 1454, - AArch64_FNMADDDrrr = 1455, - AArch64_FNMADDHrrr = 1456, - AArch64_FNMADDSrrr = 1457, - AArch64_FNMAD_ZPmZZ_D = 1458, - AArch64_FNMAD_ZPmZZ_H = 1459, - AArch64_FNMAD_ZPmZZ_S = 1460, - AArch64_FNMLA_ZPmZZ_D = 1461, - AArch64_FNMLA_ZPmZZ_H = 1462, - AArch64_FNMLA_ZPmZZ_S = 1463, - AArch64_FNMLS_ZPmZZ_D = 1464, - AArch64_FNMLS_ZPmZZ_H = 1465, - AArch64_FNMLS_ZPmZZ_S = 1466, - AArch64_FNMSB_ZPmZZ_D = 1467, - AArch64_FNMSB_ZPmZZ_H = 1468, - AArch64_FNMSB_ZPmZZ_S = 1469, - AArch64_FNMSUBDrrr = 1470, - AArch64_FNMSUBHrrr = 1471, - AArch64_FNMSUBSrrr = 1472, - AArch64_FNMULDrr = 1473, - AArch64_FNMULHrr = 1474, - AArch64_FNMULSrr = 1475, - AArch64_FRECPE_ZZ_D = 1476, - AArch64_FRECPE_ZZ_H = 1477, - AArch64_FRECPE_ZZ_S = 1478, - AArch64_FRECPEv1f16 = 1479, - AArch64_FRECPEv1i32 = 1480, - AArch64_FRECPEv1i64 = 1481, - AArch64_FRECPEv2f32 = 1482, - AArch64_FRECPEv2f64 = 1483, - AArch64_FRECPEv4f16 = 1484, - AArch64_FRECPEv4f32 = 1485, - AArch64_FRECPEv8f16 = 1486, - AArch64_FRECPS16 = 1487, - AArch64_FRECPS32 = 1488, - AArch64_FRECPS64 = 1489, - AArch64_FRECPS_ZZZ_D = 1490, - AArch64_FRECPS_ZZZ_H = 1491, - AArch64_FRECPS_ZZZ_S = 1492, - AArch64_FRECPSv2f32 = 1493, - AArch64_FRECPSv2f64 = 1494, - AArch64_FRECPSv4f16 = 1495, - AArch64_FRECPSv4f32 = 1496, - AArch64_FRECPSv8f16 = 1497, - AArch64_FRECPX_ZPmZ_D = 1498, - AArch64_FRECPX_ZPmZ_H = 1499, - AArch64_FRECPX_ZPmZ_S = 1500, - AArch64_FRECPXv1f16 = 1501, - AArch64_FRECPXv1i32 = 1502, - AArch64_FRECPXv1i64 = 1503, - AArch64_FRINTADr = 1504, - AArch64_FRINTAHr = 1505, - AArch64_FRINTASr = 1506, - AArch64_FRINTA_ZPmZ_D = 1507, - AArch64_FRINTA_ZPmZ_H = 1508, - AArch64_FRINTA_ZPmZ_S = 1509, - AArch64_FRINTAv2f32 = 1510, - AArch64_FRINTAv2f64 = 1511, - AArch64_FRINTAv4f16 = 1512, - AArch64_FRINTAv4f32 = 1513, - AArch64_FRINTAv8f16 = 1514, - AArch64_FRINTIDr = 1515, - AArch64_FRINTIHr = 1516, - AArch64_FRINTISr = 1517, - AArch64_FRINTI_ZPmZ_D = 1518, - AArch64_FRINTI_ZPmZ_H = 1519, - AArch64_FRINTI_ZPmZ_S = 1520, - AArch64_FRINTIv2f32 = 1521, - AArch64_FRINTIv2f64 = 1522, - AArch64_FRINTIv4f16 = 1523, - AArch64_FRINTIv4f32 = 1524, - AArch64_FRINTIv8f16 = 1525, - AArch64_FRINTMDr = 1526, - AArch64_FRINTMHr = 1527, - AArch64_FRINTMSr = 1528, - AArch64_FRINTM_ZPmZ_D = 1529, - AArch64_FRINTM_ZPmZ_H = 1530, - AArch64_FRINTM_ZPmZ_S = 1531, - AArch64_FRINTMv2f32 = 1532, - AArch64_FRINTMv2f64 = 1533, - AArch64_FRINTMv4f16 = 1534, - AArch64_FRINTMv4f32 = 1535, - AArch64_FRINTMv8f16 = 1536, - AArch64_FRINTNDr = 1537, - AArch64_FRINTNHr = 1538, - AArch64_FRINTNSr = 1539, - AArch64_FRINTN_ZPmZ_D = 1540, - AArch64_FRINTN_ZPmZ_H = 1541, - AArch64_FRINTN_ZPmZ_S = 1542, - AArch64_FRINTNv2f32 = 1543, - AArch64_FRINTNv2f64 = 1544, - AArch64_FRINTNv4f16 = 1545, - AArch64_FRINTNv4f32 = 1546, - AArch64_FRINTNv8f16 = 1547, - AArch64_FRINTPDr = 1548, - AArch64_FRINTPHr = 1549, - AArch64_FRINTPSr = 1550, - AArch64_FRINTP_ZPmZ_D = 1551, - AArch64_FRINTP_ZPmZ_H = 1552, - AArch64_FRINTP_ZPmZ_S = 1553, - AArch64_FRINTPv2f32 = 1554, - AArch64_FRINTPv2f64 = 1555, - AArch64_FRINTPv4f16 = 1556, - AArch64_FRINTPv4f32 = 1557, - AArch64_FRINTPv8f16 = 1558, - AArch64_FRINTXDr = 1559, - AArch64_FRINTXHr = 1560, - AArch64_FRINTXSr = 1561, - AArch64_FRINTX_ZPmZ_D = 1562, - AArch64_FRINTX_ZPmZ_H = 1563, - AArch64_FRINTX_ZPmZ_S = 1564, - AArch64_FRINTXv2f32 = 1565, - AArch64_FRINTXv2f64 = 1566, - AArch64_FRINTXv4f16 = 1567, - AArch64_FRINTXv4f32 = 1568, - AArch64_FRINTXv8f16 = 1569, - AArch64_FRINTZDr = 1570, - AArch64_FRINTZHr = 1571, - AArch64_FRINTZSr = 1572, - AArch64_FRINTZ_ZPmZ_D = 1573, - AArch64_FRINTZ_ZPmZ_H = 1574, - AArch64_FRINTZ_ZPmZ_S = 1575, - AArch64_FRINTZv2f32 = 1576, - AArch64_FRINTZv2f64 = 1577, - AArch64_FRINTZv4f16 = 1578, - AArch64_FRINTZv4f32 = 1579, - AArch64_FRINTZv8f16 = 1580, - AArch64_FRSQRTE_ZZ_D = 1581, - AArch64_FRSQRTE_ZZ_H = 1582, - AArch64_FRSQRTE_ZZ_S = 1583, - AArch64_FRSQRTEv1f16 = 1584, - AArch64_FRSQRTEv1i32 = 1585, - AArch64_FRSQRTEv1i64 = 1586, - AArch64_FRSQRTEv2f32 = 1587, - AArch64_FRSQRTEv2f64 = 1588, - AArch64_FRSQRTEv4f16 = 1589, - AArch64_FRSQRTEv4f32 = 1590, - AArch64_FRSQRTEv8f16 = 1591, - AArch64_FRSQRTS16 = 1592, - AArch64_FRSQRTS32 = 1593, - AArch64_FRSQRTS64 = 1594, - AArch64_FRSQRTS_ZZZ_D = 1595, - AArch64_FRSQRTS_ZZZ_H = 1596, - AArch64_FRSQRTS_ZZZ_S = 1597, - AArch64_FRSQRTSv2f32 = 1598, - AArch64_FRSQRTSv2f64 = 1599, - AArch64_FRSQRTSv4f16 = 1600, - AArch64_FRSQRTSv4f32 = 1601, - AArch64_FRSQRTSv8f16 = 1602, - AArch64_FSCALE_ZPmZ_D = 1603, - AArch64_FSCALE_ZPmZ_H = 1604, - AArch64_FSCALE_ZPmZ_S = 1605, - AArch64_FSQRTDr = 1606, - AArch64_FSQRTHr = 1607, - AArch64_FSQRTSr = 1608, - AArch64_FSQRT_ZPmZ_D = 1609, - AArch64_FSQRT_ZPmZ_H = 1610, - AArch64_FSQRT_ZPmZ_S = 1611, - AArch64_FSQRTv2f32 = 1612, - AArch64_FSQRTv2f64 = 1613, - AArch64_FSQRTv4f16 = 1614, - AArch64_FSQRTv4f32 = 1615, - AArch64_FSQRTv8f16 = 1616, - AArch64_FSUBDrr = 1617, - AArch64_FSUBHrr = 1618, - AArch64_FSUBR_ZPmI_D = 1619, - AArch64_FSUBR_ZPmI_H = 1620, - AArch64_FSUBR_ZPmI_S = 1621, - AArch64_FSUBR_ZPmZ_D = 1622, - AArch64_FSUBR_ZPmZ_H = 1623, - AArch64_FSUBR_ZPmZ_S = 1624, - AArch64_FSUBSrr = 1625, - AArch64_FSUB_ZPmI_D = 1626, - AArch64_FSUB_ZPmI_H = 1627, - AArch64_FSUB_ZPmI_S = 1628, - AArch64_FSUB_ZPmZ_D = 1629, - AArch64_FSUB_ZPmZ_H = 1630, - AArch64_FSUB_ZPmZ_S = 1631, - AArch64_FSUB_ZZZ_D = 1632, - AArch64_FSUB_ZZZ_H = 1633, - AArch64_FSUB_ZZZ_S = 1634, - AArch64_FSUBv2f32 = 1635, - AArch64_FSUBv2f64 = 1636, - AArch64_FSUBv4f16 = 1637, - AArch64_FSUBv4f32 = 1638, - AArch64_FSUBv8f16 = 1639, - AArch64_FTMAD_ZZI_D = 1640, - AArch64_FTMAD_ZZI_H = 1641, - AArch64_FTMAD_ZZI_S = 1642, - AArch64_FTSMUL_ZZZ_D = 1643, - AArch64_FTSMUL_ZZZ_H = 1644, - AArch64_FTSMUL_ZZZ_S = 1645, - AArch64_FTSSEL_ZZZ_D = 1646, - AArch64_FTSSEL_ZZZ_H = 1647, - AArch64_FTSSEL_ZZZ_S = 1648, - AArch64_GLD1B_D_IMM_REAL = 1649, - AArch64_GLD1B_D_REAL = 1650, - AArch64_GLD1B_D_SXTW_REAL = 1651, - AArch64_GLD1B_D_UXTW_REAL = 1652, - AArch64_GLD1B_S_IMM_REAL = 1653, - AArch64_GLD1B_S_SXTW_REAL = 1654, - AArch64_GLD1B_S_UXTW_REAL = 1655, - AArch64_GLD1D_IMM_REAL = 1656, - AArch64_GLD1D_REAL = 1657, - AArch64_GLD1D_SCALED_REAL = 1658, - AArch64_GLD1D_SXTW_REAL = 1659, - AArch64_GLD1D_SXTW_SCALED_REAL = 1660, - AArch64_GLD1D_UXTW_REAL = 1661, - AArch64_GLD1D_UXTW_SCALED_REAL = 1662, - AArch64_GLD1H_D_IMM_REAL = 1663, - AArch64_GLD1H_D_REAL = 1664, - AArch64_GLD1H_D_SCALED_REAL = 1665, - AArch64_GLD1H_D_SXTW_REAL = 1666, - AArch64_GLD1H_D_SXTW_SCALED_REAL = 1667, - AArch64_GLD1H_D_UXTW_REAL = 1668, - AArch64_GLD1H_D_UXTW_SCALED_REAL = 1669, - AArch64_GLD1H_S_IMM_REAL = 1670, - AArch64_GLD1H_S_SXTW_REAL = 1671, - AArch64_GLD1H_S_SXTW_SCALED_REAL = 1672, - AArch64_GLD1H_S_UXTW_REAL = 1673, - AArch64_GLD1H_S_UXTW_SCALED_REAL = 1674, - AArch64_GLD1SB_D_IMM_REAL = 1675, - AArch64_GLD1SB_D_REAL = 1676, - AArch64_GLD1SB_D_SXTW_REAL = 1677, - AArch64_GLD1SB_D_UXTW_REAL = 1678, - AArch64_GLD1SB_S_IMM_REAL = 1679, - AArch64_GLD1SB_S_SXTW_REAL = 1680, - AArch64_GLD1SB_S_UXTW_REAL = 1681, - AArch64_GLD1SH_D_IMM_REAL = 1682, - AArch64_GLD1SH_D_REAL = 1683, - AArch64_GLD1SH_D_SCALED_REAL = 1684, - AArch64_GLD1SH_D_SXTW_REAL = 1685, - AArch64_GLD1SH_D_SXTW_SCALED_REAL = 1686, - AArch64_GLD1SH_D_UXTW_REAL = 1687, - AArch64_GLD1SH_D_UXTW_SCALED_REAL = 1688, - AArch64_GLD1SH_S_IMM_REAL = 1689, - AArch64_GLD1SH_S_SXTW_REAL = 1690, - AArch64_GLD1SH_S_SXTW_SCALED_REAL = 1691, - AArch64_GLD1SH_S_UXTW_REAL = 1692, - AArch64_GLD1SH_S_UXTW_SCALED_REAL = 1693, - AArch64_GLD1SW_D_IMM_REAL = 1694, - AArch64_GLD1SW_D_REAL = 1695, - AArch64_GLD1SW_D_SCALED_REAL = 1696, - AArch64_GLD1SW_D_SXTW_REAL = 1697, - AArch64_GLD1SW_D_SXTW_SCALED_REAL = 1698, - AArch64_GLD1SW_D_UXTW_REAL = 1699, - AArch64_GLD1SW_D_UXTW_SCALED_REAL = 1700, - AArch64_GLD1W_D_IMM_REAL = 1701, - AArch64_GLD1W_D_REAL = 1702, - AArch64_GLD1W_D_SCALED_REAL = 1703, - AArch64_GLD1W_D_SXTW_REAL = 1704, - AArch64_GLD1W_D_SXTW_SCALED_REAL = 1705, - AArch64_GLD1W_D_UXTW_REAL = 1706, - AArch64_GLD1W_D_UXTW_SCALED_REAL = 1707, - AArch64_GLD1W_IMM_REAL = 1708, - AArch64_GLD1W_SXTW_REAL = 1709, - AArch64_GLD1W_SXTW_SCALED_REAL = 1710, - AArch64_GLD1W_UXTW_REAL = 1711, - AArch64_GLD1W_UXTW_SCALED_REAL = 1712, - AArch64_GLDFF1B_D_IMM_REAL = 1713, - AArch64_GLDFF1B_D_REAL = 1714, - AArch64_GLDFF1B_D_SXTW_REAL = 1715, - AArch64_GLDFF1B_D_UXTW_REAL = 1716, - AArch64_GLDFF1B_S_IMM_REAL = 1717, - AArch64_GLDFF1B_S_SXTW_REAL = 1718, - AArch64_GLDFF1B_S_UXTW_REAL = 1719, - AArch64_GLDFF1D_IMM_REAL = 1720, - AArch64_GLDFF1D_REAL = 1721, - AArch64_GLDFF1D_SCALED_REAL = 1722, - AArch64_GLDFF1D_SXTW_REAL = 1723, - AArch64_GLDFF1D_SXTW_SCALED_REAL = 1724, - AArch64_GLDFF1D_UXTW_REAL = 1725, - AArch64_GLDFF1D_UXTW_SCALED_REAL = 1726, - AArch64_GLDFF1H_D_IMM_REAL = 1727, - AArch64_GLDFF1H_D_REAL = 1728, - AArch64_GLDFF1H_D_SCALED_REAL = 1729, - AArch64_GLDFF1H_D_SXTW_REAL = 1730, - AArch64_GLDFF1H_D_SXTW_SCALED_REAL = 1731, - AArch64_GLDFF1H_D_UXTW_REAL = 1732, - AArch64_GLDFF1H_D_UXTW_SCALED_REAL = 1733, - AArch64_GLDFF1H_S_IMM_REAL = 1734, - AArch64_GLDFF1H_S_SXTW_REAL = 1735, - AArch64_GLDFF1H_S_SXTW_SCALED_REAL = 1736, - AArch64_GLDFF1H_S_UXTW_REAL = 1737, - AArch64_GLDFF1H_S_UXTW_SCALED_REAL = 1738, - AArch64_GLDFF1SB_D_IMM_REAL = 1739, - AArch64_GLDFF1SB_D_REAL = 1740, - AArch64_GLDFF1SB_D_SXTW_REAL = 1741, - AArch64_GLDFF1SB_D_UXTW_REAL = 1742, - AArch64_GLDFF1SB_S_IMM_REAL = 1743, - AArch64_GLDFF1SB_S_SXTW_REAL = 1744, - AArch64_GLDFF1SB_S_UXTW_REAL = 1745, - AArch64_GLDFF1SH_D_IMM_REAL = 1746, - AArch64_GLDFF1SH_D_REAL = 1747, - AArch64_GLDFF1SH_D_SCALED_REAL = 1748, - AArch64_GLDFF1SH_D_SXTW_REAL = 1749, - AArch64_GLDFF1SH_D_SXTW_SCALED_REAL = 1750, - AArch64_GLDFF1SH_D_UXTW_REAL = 1751, - AArch64_GLDFF1SH_D_UXTW_SCALED_REAL = 1752, - AArch64_GLDFF1SH_S_IMM_REAL = 1753, - AArch64_GLDFF1SH_S_SXTW_REAL = 1754, - AArch64_GLDFF1SH_S_SXTW_SCALED_REAL = 1755, - AArch64_GLDFF1SH_S_UXTW_REAL = 1756, - AArch64_GLDFF1SH_S_UXTW_SCALED_REAL = 1757, - AArch64_GLDFF1SW_D_IMM_REAL = 1758, - AArch64_GLDFF1SW_D_REAL = 1759, - AArch64_GLDFF1SW_D_SCALED_REAL = 1760, - AArch64_GLDFF1SW_D_SXTW_REAL = 1761, - AArch64_GLDFF1SW_D_SXTW_SCALED_REAL = 1762, - AArch64_GLDFF1SW_D_UXTW_REAL = 1763, - AArch64_GLDFF1SW_D_UXTW_SCALED_REAL = 1764, - AArch64_GLDFF1W_D_IMM_REAL = 1765, - AArch64_GLDFF1W_D_REAL = 1766, - AArch64_GLDFF1W_D_SCALED_REAL = 1767, - AArch64_GLDFF1W_D_SXTW_REAL = 1768, - AArch64_GLDFF1W_D_SXTW_SCALED_REAL = 1769, - AArch64_GLDFF1W_D_UXTW_REAL = 1770, - AArch64_GLDFF1W_D_UXTW_SCALED_REAL = 1771, - AArch64_GLDFF1W_IMM_REAL = 1772, - AArch64_GLDFF1W_SXTW_REAL = 1773, - AArch64_GLDFF1W_SXTW_SCALED_REAL = 1774, - AArch64_GLDFF1W_UXTW_REAL = 1775, - AArch64_GLDFF1W_UXTW_SCALED_REAL = 1776, - AArch64_HINT = 1777, - AArch64_HLT = 1778, - AArch64_HVC = 1779, - AArch64_INCB_XPiI = 1780, - AArch64_INCD_XPiI = 1781, - AArch64_INCD_ZPiI = 1782, - AArch64_INCH_XPiI = 1783, - AArch64_INCH_ZPiI = 1784, - AArch64_INCP_XP_B = 1785, - AArch64_INCP_XP_D = 1786, - AArch64_INCP_XP_H = 1787, - AArch64_INCP_XP_S = 1788, - AArch64_INCP_ZP_D = 1789, - AArch64_INCP_ZP_H = 1790, - AArch64_INCP_ZP_S = 1791, - AArch64_INCW_XPiI = 1792, - AArch64_INCW_ZPiI = 1793, - AArch64_INDEX_II_B = 1794, - AArch64_INDEX_II_D = 1795, - AArch64_INDEX_II_H = 1796, - AArch64_INDEX_II_S = 1797, - AArch64_INDEX_IR_B = 1798, - AArch64_INDEX_IR_D = 1799, - AArch64_INDEX_IR_H = 1800, - AArch64_INDEX_IR_S = 1801, - AArch64_INDEX_RI_B = 1802, - AArch64_INDEX_RI_D = 1803, - AArch64_INDEX_RI_H = 1804, - AArch64_INDEX_RI_S = 1805, - AArch64_INDEX_RR_B = 1806, - AArch64_INDEX_RR_D = 1807, - AArch64_INDEX_RR_H = 1808, - AArch64_INDEX_RR_S = 1809, - AArch64_INSR_ZR_B = 1810, - AArch64_INSR_ZR_D = 1811, - AArch64_INSR_ZR_H = 1812, - AArch64_INSR_ZR_S = 1813, - AArch64_INSR_ZV_B = 1814, - AArch64_INSR_ZV_D = 1815, - AArch64_INSR_ZV_H = 1816, - AArch64_INSR_ZV_S = 1817, - AArch64_INSvi16gpr = 1818, - AArch64_INSvi16lane = 1819, - AArch64_INSvi32gpr = 1820, - AArch64_INSvi32lane = 1821, - AArch64_INSvi64gpr = 1822, - AArch64_INSvi64lane = 1823, - AArch64_INSvi8gpr = 1824, - AArch64_INSvi8lane = 1825, - AArch64_ISB = 1826, - AArch64_LASTA_RPZ_B = 1827, - AArch64_LASTA_RPZ_D = 1828, - AArch64_LASTA_RPZ_H = 1829, - AArch64_LASTA_RPZ_S = 1830, - AArch64_LASTA_VPZ_B = 1831, - AArch64_LASTA_VPZ_D = 1832, - AArch64_LASTA_VPZ_H = 1833, - AArch64_LASTA_VPZ_S = 1834, - AArch64_LASTB_RPZ_B = 1835, - AArch64_LASTB_RPZ_D = 1836, - AArch64_LASTB_RPZ_H = 1837, - AArch64_LASTB_RPZ_S = 1838, - AArch64_LASTB_VPZ_B = 1839, - AArch64_LASTB_VPZ_D = 1840, - AArch64_LASTB_VPZ_H = 1841, - AArch64_LASTB_VPZ_S = 1842, - AArch64_LD1B = 1843, - AArch64_LD1B_D = 1844, - AArch64_LD1B_D_IMM_REAL = 1845, - AArch64_LD1B_H = 1846, - AArch64_LD1B_H_IMM_REAL = 1847, - AArch64_LD1B_IMM_REAL = 1848, - AArch64_LD1B_S = 1849, - AArch64_LD1B_S_IMM_REAL = 1850, - AArch64_LD1D = 1851, - AArch64_LD1D_IMM_REAL = 1852, - AArch64_LD1Fourv16b = 1853, - AArch64_LD1Fourv16b_POST = 1854, - AArch64_LD1Fourv1d = 1855, - AArch64_LD1Fourv1d_POST = 1856, - AArch64_LD1Fourv2d = 1857, - AArch64_LD1Fourv2d_POST = 1858, - AArch64_LD1Fourv2s = 1859, - AArch64_LD1Fourv2s_POST = 1860, - AArch64_LD1Fourv4h = 1861, - AArch64_LD1Fourv4h_POST = 1862, - AArch64_LD1Fourv4s = 1863, - AArch64_LD1Fourv4s_POST = 1864, - AArch64_LD1Fourv8b = 1865, - AArch64_LD1Fourv8b_POST = 1866, - AArch64_LD1Fourv8h = 1867, - AArch64_LD1Fourv8h_POST = 1868, - AArch64_LD1H = 1869, - AArch64_LD1H_D = 1870, - AArch64_LD1H_D_IMM_REAL = 1871, - AArch64_LD1H_IMM_REAL = 1872, - AArch64_LD1H_S = 1873, - AArch64_LD1H_S_IMM_REAL = 1874, - AArch64_LD1Onev16b = 1875, - AArch64_LD1Onev16b_POST = 1876, - AArch64_LD1Onev1d = 1877, - AArch64_LD1Onev1d_POST = 1878, - AArch64_LD1Onev2d = 1879, - AArch64_LD1Onev2d_POST = 1880, - AArch64_LD1Onev2s = 1881, - AArch64_LD1Onev2s_POST = 1882, - AArch64_LD1Onev4h = 1883, - AArch64_LD1Onev4h_POST = 1884, - AArch64_LD1Onev4s = 1885, - AArch64_LD1Onev4s_POST = 1886, - AArch64_LD1Onev8b = 1887, - AArch64_LD1Onev8b_POST = 1888, - AArch64_LD1Onev8h = 1889, - AArch64_LD1Onev8h_POST = 1890, - AArch64_LD1RB_D_IMM = 1891, - AArch64_LD1RB_H_IMM = 1892, - AArch64_LD1RB_IMM = 1893, - AArch64_LD1RB_S_IMM = 1894, - AArch64_LD1RD_IMM = 1895, - AArch64_LD1RH_D_IMM = 1896, - AArch64_LD1RH_IMM = 1897, - AArch64_LD1RH_S_IMM = 1898, - AArch64_LD1RQ_B = 1899, - AArch64_LD1RQ_B_IMM = 1900, - AArch64_LD1RQ_D = 1901, - AArch64_LD1RQ_D_IMM = 1902, - AArch64_LD1RQ_H = 1903, - AArch64_LD1RQ_H_IMM = 1904, - AArch64_LD1RQ_W = 1905, - AArch64_LD1RQ_W_IMM = 1906, - AArch64_LD1RSB_D_IMM = 1907, - AArch64_LD1RSB_H_IMM = 1908, - AArch64_LD1RSB_S_IMM = 1909, - AArch64_LD1RSH_D_IMM = 1910, - AArch64_LD1RSH_S_IMM = 1911, - AArch64_LD1RSW_IMM = 1912, - AArch64_LD1RW_D_IMM = 1913, - AArch64_LD1RW_IMM = 1914, - AArch64_LD1Rv16b = 1915, - AArch64_LD1Rv16b_POST = 1916, - AArch64_LD1Rv1d = 1917, - AArch64_LD1Rv1d_POST = 1918, - AArch64_LD1Rv2d = 1919, - AArch64_LD1Rv2d_POST = 1920, - AArch64_LD1Rv2s = 1921, - AArch64_LD1Rv2s_POST = 1922, - AArch64_LD1Rv4h = 1923, - AArch64_LD1Rv4h_POST = 1924, - AArch64_LD1Rv4s = 1925, - AArch64_LD1Rv4s_POST = 1926, - AArch64_LD1Rv8b = 1927, - AArch64_LD1Rv8b_POST = 1928, - AArch64_LD1Rv8h = 1929, - AArch64_LD1Rv8h_POST = 1930, - AArch64_LD1SB_D = 1931, - AArch64_LD1SB_D_IMM_REAL = 1932, - AArch64_LD1SB_H = 1933, - AArch64_LD1SB_H_IMM_REAL = 1934, - AArch64_LD1SB_S = 1935, - AArch64_LD1SB_S_IMM_REAL = 1936, - AArch64_LD1SH_D = 1937, - AArch64_LD1SH_D_IMM_REAL = 1938, - AArch64_LD1SH_S = 1939, - AArch64_LD1SH_S_IMM_REAL = 1940, - AArch64_LD1SW_D = 1941, - AArch64_LD1SW_D_IMM_REAL = 1942, - AArch64_LD1Threev16b = 1943, - AArch64_LD1Threev16b_POST = 1944, - AArch64_LD1Threev1d = 1945, - AArch64_LD1Threev1d_POST = 1946, - AArch64_LD1Threev2d = 1947, - AArch64_LD1Threev2d_POST = 1948, - AArch64_LD1Threev2s = 1949, - AArch64_LD1Threev2s_POST = 1950, - AArch64_LD1Threev4h = 1951, - AArch64_LD1Threev4h_POST = 1952, - AArch64_LD1Threev4s = 1953, - AArch64_LD1Threev4s_POST = 1954, - AArch64_LD1Threev8b = 1955, - AArch64_LD1Threev8b_POST = 1956, - AArch64_LD1Threev8h = 1957, - AArch64_LD1Threev8h_POST = 1958, - AArch64_LD1Twov16b = 1959, - AArch64_LD1Twov16b_POST = 1960, - AArch64_LD1Twov1d = 1961, - AArch64_LD1Twov1d_POST = 1962, - AArch64_LD1Twov2d = 1963, - AArch64_LD1Twov2d_POST = 1964, - AArch64_LD1Twov2s = 1965, - AArch64_LD1Twov2s_POST = 1966, - AArch64_LD1Twov4h = 1967, - AArch64_LD1Twov4h_POST = 1968, - AArch64_LD1Twov4s = 1969, - AArch64_LD1Twov4s_POST = 1970, - AArch64_LD1Twov8b = 1971, - AArch64_LD1Twov8b_POST = 1972, - AArch64_LD1Twov8h = 1973, - AArch64_LD1Twov8h_POST = 1974, - AArch64_LD1W = 1975, - AArch64_LD1W_D = 1976, - AArch64_LD1W_D_IMM_REAL = 1977, - AArch64_LD1W_IMM_REAL = 1978, - AArch64_LD1i16 = 1979, - AArch64_LD1i16_POST = 1980, - AArch64_LD1i32 = 1981, - AArch64_LD1i32_POST = 1982, - AArch64_LD1i64 = 1983, - AArch64_LD1i64_POST = 1984, - AArch64_LD1i8 = 1985, - AArch64_LD1i8_POST = 1986, - AArch64_LD2B = 1987, - AArch64_LD2B_IMM = 1988, - AArch64_LD2D = 1989, - AArch64_LD2D_IMM = 1990, - AArch64_LD2H = 1991, - AArch64_LD2H_IMM = 1992, - AArch64_LD2Rv16b = 1993, - AArch64_LD2Rv16b_POST = 1994, - AArch64_LD2Rv1d = 1995, - AArch64_LD2Rv1d_POST = 1996, - AArch64_LD2Rv2d = 1997, - AArch64_LD2Rv2d_POST = 1998, - AArch64_LD2Rv2s = 1999, - AArch64_LD2Rv2s_POST = 2000, - AArch64_LD2Rv4h = 2001, - AArch64_LD2Rv4h_POST = 2002, - AArch64_LD2Rv4s = 2003, - AArch64_LD2Rv4s_POST = 2004, - AArch64_LD2Rv8b = 2005, - AArch64_LD2Rv8b_POST = 2006, - AArch64_LD2Rv8h = 2007, - AArch64_LD2Rv8h_POST = 2008, - AArch64_LD2Twov16b = 2009, - AArch64_LD2Twov16b_POST = 2010, - AArch64_LD2Twov2d = 2011, - AArch64_LD2Twov2d_POST = 2012, - AArch64_LD2Twov2s = 2013, - AArch64_LD2Twov2s_POST = 2014, - AArch64_LD2Twov4h = 2015, - AArch64_LD2Twov4h_POST = 2016, - AArch64_LD2Twov4s = 2017, - AArch64_LD2Twov4s_POST = 2018, - AArch64_LD2Twov8b = 2019, - AArch64_LD2Twov8b_POST = 2020, - AArch64_LD2Twov8h = 2021, - AArch64_LD2Twov8h_POST = 2022, - AArch64_LD2W = 2023, - AArch64_LD2W_IMM = 2024, - AArch64_LD2i16 = 2025, - AArch64_LD2i16_POST = 2026, - AArch64_LD2i32 = 2027, - AArch64_LD2i32_POST = 2028, - AArch64_LD2i64 = 2029, - AArch64_LD2i64_POST = 2030, - AArch64_LD2i8 = 2031, - AArch64_LD2i8_POST = 2032, - AArch64_LD3B = 2033, - AArch64_LD3B_IMM = 2034, - AArch64_LD3D = 2035, - AArch64_LD3D_IMM = 2036, - AArch64_LD3H = 2037, - AArch64_LD3H_IMM = 2038, - AArch64_LD3Rv16b = 2039, - AArch64_LD3Rv16b_POST = 2040, - AArch64_LD3Rv1d = 2041, - AArch64_LD3Rv1d_POST = 2042, - AArch64_LD3Rv2d = 2043, - AArch64_LD3Rv2d_POST = 2044, - AArch64_LD3Rv2s = 2045, - AArch64_LD3Rv2s_POST = 2046, - AArch64_LD3Rv4h = 2047, - AArch64_LD3Rv4h_POST = 2048, - AArch64_LD3Rv4s = 2049, - AArch64_LD3Rv4s_POST = 2050, - AArch64_LD3Rv8b = 2051, - AArch64_LD3Rv8b_POST = 2052, - AArch64_LD3Rv8h = 2053, - AArch64_LD3Rv8h_POST = 2054, - AArch64_LD3Threev16b = 2055, - AArch64_LD3Threev16b_POST = 2056, - AArch64_LD3Threev2d = 2057, - AArch64_LD3Threev2d_POST = 2058, - AArch64_LD3Threev2s = 2059, - AArch64_LD3Threev2s_POST = 2060, - AArch64_LD3Threev4h = 2061, - AArch64_LD3Threev4h_POST = 2062, - AArch64_LD3Threev4s = 2063, - AArch64_LD3Threev4s_POST = 2064, - AArch64_LD3Threev8b = 2065, - AArch64_LD3Threev8b_POST = 2066, - AArch64_LD3Threev8h = 2067, - AArch64_LD3Threev8h_POST = 2068, - AArch64_LD3W = 2069, - AArch64_LD3W_IMM = 2070, - AArch64_LD3i16 = 2071, - AArch64_LD3i16_POST = 2072, - AArch64_LD3i32 = 2073, - AArch64_LD3i32_POST = 2074, - AArch64_LD3i64 = 2075, - AArch64_LD3i64_POST = 2076, - AArch64_LD3i8 = 2077, - AArch64_LD3i8_POST = 2078, - AArch64_LD4B = 2079, - AArch64_LD4B_IMM = 2080, - AArch64_LD4D = 2081, - AArch64_LD4D_IMM = 2082, - AArch64_LD4Fourv16b = 2083, - AArch64_LD4Fourv16b_POST = 2084, - AArch64_LD4Fourv2d = 2085, - AArch64_LD4Fourv2d_POST = 2086, - AArch64_LD4Fourv2s = 2087, - AArch64_LD4Fourv2s_POST = 2088, - AArch64_LD4Fourv4h = 2089, - AArch64_LD4Fourv4h_POST = 2090, - AArch64_LD4Fourv4s = 2091, - AArch64_LD4Fourv4s_POST = 2092, - AArch64_LD4Fourv8b = 2093, - AArch64_LD4Fourv8b_POST = 2094, - AArch64_LD4Fourv8h = 2095, - AArch64_LD4Fourv8h_POST = 2096, - AArch64_LD4H = 2097, - AArch64_LD4H_IMM = 2098, - AArch64_LD4Rv16b = 2099, - AArch64_LD4Rv16b_POST = 2100, - AArch64_LD4Rv1d = 2101, - AArch64_LD4Rv1d_POST = 2102, - AArch64_LD4Rv2d = 2103, - AArch64_LD4Rv2d_POST = 2104, - AArch64_LD4Rv2s = 2105, - AArch64_LD4Rv2s_POST = 2106, - AArch64_LD4Rv4h = 2107, - AArch64_LD4Rv4h_POST = 2108, - AArch64_LD4Rv4s = 2109, - AArch64_LD4Rv4s_POST = 2110, - AArch64_LD4Rv8b = 2111, - AArch64_LD4Rv8b_POST = 2112, - AArch64_LD4Rv8h = 2113, - AArch64_LD4Rv8h_POST = 2114, - AArch64_LD4W = 2115, - AArch64_LD4W_IMM = 2116, - AArch64_LD4i16 = 2117, - AArch64_LD4i16_POST = 2118, - AArch64_LD4i32 = 2119, - AArch64_LD4i32_POST = 2120, - AArch64_LD4i64 = 2121, - AArch64_LD4i64_POST = 2122, - AArch64_LD4i8 = 2123, - AArch64_LD4i8_POST = 2124, - AArch64_LDADDAB = 2125, - AArch64_LDADDAH = 2126, - AArch64_LDADDALB = 2127, - AArch64_LDADDALH = 2128, - AArch64_LDADDALW = 2129, - AArch64_LDADDALX = 2130, - AArch64_LDADDAW = 2131, - AArch64_LDADDAX = 2132, - AArch64_LDADDB = 2133, - AArch64_LDADDH = 2134, - AArch64_LDADDLB = 2135, - AArch64_LDADDLH = 2136, - AArch64_LDADDLW = 2137, - AArch64_LDADDLX = 2138, - AArch64_LDADDW = 2139, - AArch64_LDADDX = 2140, - AArch64_LDAPRB = 2141, - AArch64_LDAPRH = 2142, - AArch64_LDAPRW = 2143, - AArch64_LDAPRX = 2144, - AArch64_LDAPURBi = 2145, - AArch64_LDAPURHi = 2146, - AArch64_LDAPURSBWi = 2147, - AArch64_LDAPURSBXi = 2148, - AArch64_LDAPURSHWi = 2149, - AArch64_LDAPURSHXi = 2150, - AArch64_LDAPURSWi = 2151, - AArch64_LDAPURXi = 2152, - AArch64_LDAPURi = 2153, - AArch64_LDARB = 2154, - AArch64_LDARH = 2155, - AArch64_LDARW = 2156, - AArch64_LDARX = 2157, - AArch64_LDAXPW = 2158, - AArch64_LDAXPX = 2159, - AArch64_LDAXRB = 2160, - AArch64_LDAXRH = 2161, - AArch64_LDAXRW = 2162, - AArch64_LDAXRX = 2163, - AArch64_LDCLRAB = 2164, - AArch64_LDCLRAH = 2165, - AArch64_LDCLRALB = 2166, - AArch64_LDCLRALH = 2167, - AArch64_LDCLRALW = 2168, - AArch64_LDCLRALX = 2169, - AArch64_LDCLRAW = 2170, - AArch64_LDCLRAX = 2171, - AArch64_LDCLRB = 2172, - AArch64_LDCLRH = 2173, - AArch64_LDCLRLB = 2174, - AArch64_LDCLRLH = 2175, - AArch64_LDCLRLW = 2176, - AArch64_LDCLRLX = 2177, - AArch64_LDCLRW = 2178, - AArch64_LDCLRX = 2179, - AArch64_LDEORAB = 2180, - AArch64_LDEORAH = 2181, - AArch64_LDEORALB = 2182, - AArch64_LDEORALH = 2183, - AArch64_LDEORALW = 2184, - AArch64_LDEORALX = 2185, - AArch64_LDEORAW = 2186, - AArch64_LDEORAX = 2187, - AArch64_LDEORB = 2188, - AArch64_LDEORH = 2189, - AArch64_LDEORLB = 2190, - AArch64_LDEORLH = 2191, - AArch64_LDEORLW = 2192, - AArch64_LDEORLX = 2193, - AArch64_LDEORW = 2194, - AArch64_LDEORX = 2195, - AArch64_LDFF1B_D_REAL = 2196, - AArch64_LDFF1B_H_REAL = 2197, - AArch64_LDFF1B_REAL = 2198, - AArch64_LDFF1B_S_REAL = 2199, - AArch64_LDFF1D_REAL = 2200, - AArch64_LDFF1H_D_REAL = 2201, - AArch64_LDFF1H_REAL = 2202, - AArch64_LDFF1H_S_REAL = 2203, - AArch64_LDFF1SB_D_REAL = 2204, - AArch64_LDFF1SB_H_REAL = 2205, - AArch64_LDFF1SB_S_REAL = 2206, - AArch64_LDFF1SH_D_REAL = 2207, - AArch64_LDFF1SH_S_REAL = 2208, - AArch64_LDFF1SW_D_REAL = 2209, - AArch64_LDFF1W_D_REAL = 2210, - AArch64_LDFF1W_REAL = 2211, - AArch64_LDLARB = 2212, - AArch64_LDLARH = 2213, - AArch64_LDLARW = 2214, - AArch64_LDLARX = 2215, - AArch64_LDNF1B_D_IMM_REAL = 2216, - AArch64_LDNF1B_H_IMM_REAL = 2217, - AArch64_LDNF1B_IMM_REAL = 2218, - AArch64_LDNF1B_S_IMM_REAL = 2219, - AArch64_LDNF1D_IMM_REAL = 2220, - AArch64_LDNF1H_D_IMM_REAL = 2221, - AArch64_LDNF1H_IMM_REAL = 2222, - AArch64_LDNF1H_S_IMM_REAL = 2223, - AArch64_LDNF1SB_D_IMM_REAL = 2224, - AArch64_LDNF1SB_H_IMM_REAL = 2225, - AArch64_LDNF1SB_S_IMM_REAL = 2226, - AArch64_LDNF1SH_D_IMM_REAL = 2227, - AArch64_LDNF1SH_S_IMM_REAL = 2228, - AArch64_LDNF1SW_D_IMM_REAL = 2229, - AArch64_LDNF1W_D_IMM_REAL = 2230, - AArch64_LDNF1W_IMM_REAL = 2231, - AArch64_LDNPDi = 2232, - AArch64_LDNPQi = 2233, - AArch64_LDNPSi = 2234, - AArch64_LDNPWi = 2235, - AArch64_LDNPXi = 2236, - AArch64_LDNT1B_ZRI = 2237, - AArch64_LDNT1B_ZRR = 2238, - AArch64_LDNT1D_ZRI = 2239, - AArch64_LDNT1D_ZRR = 2240, - AArch64_LDNT1H_ZRI = 2241, - AArch64_LDNT1H_ZRR = 2242, - AArch64_LDNT1W_ZRI = 2243, - AArch64_LDNT1W_ZRR = 2244, - AArch64_LDPDi = 2245, - AArch64_LDPDpost = 2246, - AArch64_LDPDpre = 2247, - AArch64_LDPQi = 2248, - AArch64_LDPQpost = 2249, - AArch64_LDPQpre = 2250, - AArch64_LDPSWi = 2251, - AArch64_LDPSWpost = 2252, - AArch64_LDPSWpre = 2253, - AArch64_LDPSi = 2254, - AArch64_LDPSpost = 2255, - AArch64_LDPSpre = 2256, - AArch64_LDPWi = 2257, - AArch64_LDPWpost = 2258, - AArch64_LDPWpre = 2259, - AArch64_LDPXi = 2260, - AArch64_LDPXpost = 2261, - AArch64_LDPXpre = 2262, - AArch64_LDRAAindexed = 2263, - AArch64_LDRAAwriteback = 2264, - AArch64_LDRABindexed = 2265, - AArch64_LDRABwriteback = 2266, - AArch64_LDRBBpost = 2267, - AArch64_LDRBBpre = 2268, - AArch64_LDRBBroW = 2269, - AArch64_LDRBBroX = 2270, - AArch64_LDRBBui = 2271, - AArch64_LDRBpost = 2272, - AArch64_LDRBpre = 2273, - AArch64_LDRBroW = 2274, - AArch64_LDRBroX = 2275, - AArch64_LDRBui = 2276, - AArch64_LDRDl = 2277, - AArch64_LDRDpost = 2278, - AArch64_LDRDpre = 2279, - AArch64_LDRDroW = 2280, - AArch64_LDRDroX = 2281, - AArch64_LDRDui = 2282, - AArch64_LDRHHpost = 2283, - AArch64_LDRHHpre = 2284, - AArch64_LDRHHroW = 2285, - AArch64_LDRHHroX = 2286, - AArch64_LDRHHui = 2287, - AArch64_LDRHpost = 2288, - AArch64_LDRHpre = 2289, - AArch64_LDRHroW = 2290, - AArch64_LDRHroX = 2291, - AArch64_LDRHui = 2292, - AArch64_LDRQl = 2293, - AArch64_LDRQpost = 2294, - AArch64_LDRQpre = 2295, - AArch64_LDRQroW = 2296, - AArch64_LDRQroX = 2297, - AArch64_LDRQui = 2298, - AArch64_LDRSBWpost = 2299, - AArch64_LDRSBWpre = 2300, - AArch64_LDRSBWroW = 2301, - AArch64_LDRSBWroX = 2302, - AArch64_LDRSBWui = 2303, - AArch64_LDRSBXpost = 2304, - AArch64_LDRSBXpre = 2305, - AArch64_LDRSBXroW = 2306, - AArch64_LDRSBXroX = 2307, - AArch64_LDRSBXui = 2308, - AArch64_LDRSHWpost = 2309, - AArch64_LDRSHWpre = 2310, - AArch64_LDRSHWroW = 2311, - AArch64_LDRSHWroX = 2312, - AArch64_LDRSHWui = 2313, - AArch64_LDRSHXpost = 2314, - AArch64_LDRSHXpre = 2315, - AArch64_LDRSHXroW = 2316, - AArch64_LDRSHXroX = 2317, - AArch64_LDRSHXui = 2318, - AArch64_LDRSWl = 2319, - AArch64_LDRSWpost = 2320, - AArch64_LDRSWpre = 2321, - AArch64_LDRSWroW = 2322, - AArch64_LDRSWroX = 2323, - AArch64_LDRSWui = 2324, - AArch64_LDRSl = 2325, - AArch64_LDRSpost = 2326, - AArch64_LDRSpre = 2327, - AArch64_LDRSroW = 2328, - AArch64_LDRSroX = 2329, - AArch64_LDRSui = 2330, - AArch64_LDRWl = 2331, - AArch64_LDRWpost = 2332, - AArch64_LDRWpre = 2333, - AArch64_LDRWroW = 2334, - AArch64_LDRWroX = 2335, - AArch64_LDRWui = 2336, - AArch64_LDRXl = 2337, - AArch64_LDRXpost = 2338, - AArch64_LDRXpre = 2339, - AArch64_LDRXroW = 2340, - AArch64_LDRXroX = 2341, - AArch64_LDRXui = 2342, - AArch64_LDR_PXI = 2343, - AArch64_LDR_ZXI = 2344, - AArch64_LDSETAB = 2345, - AArch64_LDSETAH = 2346, - AArch64_LDSETALB = 2347, - AArch64_LDSETALH = 2348, - AArch64_LDSETALW = 2349, - AArch64_LDSETALX = 2350, - AArch64_LDSETAW = 2351, - AArch64_LDSETAX = 2352, - AArch64_LDSETB = 2353, - AArch64_LDSETH = 2354, - AArch64_LDSETLB = 2355, - AArch64_LDSETLH = 2356, - AArch64_LDSETLW = 2357, - AArch64_LDSETLX = 2358, - AArch64_LDSETW = 2359, - AArch64_LDSETX = 2360, - AArch64_LDSMAXAB = 2361, - AArch64_LDSMAXAH = 2362, - AArch64_LDSMAXALB = 2363, - AArch64_LDSMAXALH = 2364, - AArch64_LDSMAXALW = 2365, - AArch64_LDSMAXALX = 2366, - AArch64_LDSMAXAW = 2367, - AArch64_LDSMAXAX = 2368, - AArch64_LDSMAXB = 2369, - AArch64_LDSMAXH = 2370, - AArch64_LDSMAXLB = 2371, - AArch64_LDSMAXLH = 2372, - AArch64_LDSMAXLW = 2373, - AArch64_LDSMAXLX = 2374, - AArch64_LDSMAXW = 2375, - AArch64_LDSMAXX = 2376, - AArch64_LDSMINAB = 2377, - AArch64_LDSMINAH = 2378, - AArch64_LDSMINALB = 2379, - AArch64_LDSMINALH = 2380, - AArch64_LDSMINALW = 2381, - AArch64_LDSMINALX = 2382, - AArch64_LDSMINAW = 2383, - AArch64_LDSMINAX = 2384, - AArch64_LDSMINB = 2385, - AArch64_LDSMINH = 2386, - AArch64_LDSMINLB = 2387, - AArch64_LDSMINLH = 2388, - AArch64_LDSMINLW = 2389, - AArch64_LDSMINLX = 2390, - AArch64_LDSMINW = 2391, - AArch64_LDSMINX = 2392, - AArch64_LDTRBi = 2393, - AArch64_LDTRHi = 2394, - AArch64_LDTRSBWi = 2395, - AArch64_LDTRSBXi = 2396, - AArch64_LDTRSHWi = 2397, - AArch64_LDTRSHXi = 2398, - AArch64_LDTRSWi = 2399, - AArch64_LDTRWi = 2400, - AArch64_LDTRXi = 2401, - AArch64_LDUMAXAB = 2402, - AArch64_LDUMAXAH = 2403, - AArch64_LDUMAXALB = 2404, - AArch64_LDUMAXALH = 2405, - AArch64_LDUMAXALW = 2406, - AArch64_LDUMAXALX = 2407, - AArch64_LDUMAXAW = 2408, - AArch64_LDUMAXAX = 2409, - AArch64_LDUMAXB = 2410, - AArch64_LDUMAXH = 2411, - AArch64_LDUMAXLB = 2412, - AArch64_LDUMAXLH = 2413, - AArch64_LDUMAXLW = 2414, - AArch64_LDUMAXLX = 2415, - AArch64_LDUMAXW = 2416, - AArch64_LDUMAXX = 2417, - AArch64_LDUMINAB = 2418, - AArch64_LDUMINAH = 2419, - AArch64_LDUMINALB = 2420, - AArch64_LDUMINALH = 2421, - AArch64_LDUMINALW = 2422, - AArch64_LDUMINALX = 2423, - AArch64_LDUMINAW = 2424, - AArch64_LDUMINAX = 2425, - AArch64_LDUMINB = 2426, - AArch64_LDUMINH = 2427, - AArch64_LDUMINLB = 2428, - AArch64_LDUMINLH = 2429, - AArch64_LDUMINLW = 2430, - AArch64_LDUMINLX = 2431, - AArch64_LDUMINW = 2432, - AArch64_LDUMINX = 2433, - AArch64_LDURBBi = 2434, - AArch64_LDURBi = 2435, - AArch64_LDURDi = 2436, - AArch64_LDURHHi = 2437, - AArch64_LDURHi = 2438, - AArch64_LDURQi = 2439, - AArch64_LDURSBWi = 2440, - AArch64_LDURSBXi = 2441, - AArch64_LDURSHWi = 2442, - AArch64_LDURSHXi = 2443, - AArch64_LDURSWi = 2444, - AArch64_LDURSi = 2445, - AArch64_LDURWi = 2446, - AArch64_LDURXi = 2447, - AArch64_LDXPW = 2448, - AArch64_LDXPX = 2449, - AArch64_LDXRB = 2450, - AArch64_LDXRH = 2451, - AArch64_LDXRW = 2452, - AArch64_LDXRX = 2453, - AArch64_LOADgot = 2454, - AArch64_LSLR_ZPmZ_B = 2455, - AArch64_LSLR_ZPmZ_D = 2456, - AArch64_LSLR_ZPmZ_H = 2457, - AArch64_LSLR_ZPmZ_S = 2458, - AArch64_LSLVWr = 2459, - AArch64_LSLVXr = 2460, - AArch64_LSL_WIDE_ZPmZ_B = 2461, - AArch64_LSL_WIDE_ZPmZ_H = 2462, - AArch64_LSL_WIDE_ZPmZ_S = 2463, - AArch64_LSL_WIDE_ZZZ_B = 2464, - AArch64_LSL_WIDE_ZZZ_H = 2465, - AArch64_LSL_WIDE_ZZZ_S = 2466, - AArch64_LSL_ZPmI_B = 2467, - AArch64_LSL_ZPmI_D = 2468, - AArch64_LSL_ZPmI_H = 2469, - AArch64_LSL_ZPmI_S = 2470, - AArch64_LSL_ZPmZ_B = 2471, - AArch64_LSL_ZPmZ_D = 2472, - AArch64_LSL_ZPmZ_H = 2473, - AArch64_LSL_ZPmZ_S = 2474, - AArch64_LSL_ZZI_B = 2475, - AArch64_LSL_ZZI_D = 2476, - AArch64_LSL_ZZI_H = 2477, - AArch64_LSL_ZZI_S = 2478, - AArch64_LSRR_ZPmZ_B = 2479, - AArch64_LSRR_ZPmZ_D = 2480, - AArch64_LSRR_ZPmZ_H = 2481, - AArch64_LSRR_ZPmZ_S = 2482, - AArch64_LSRVWr = 2483, - AArch64_LSRVXr = 2484, - AArch64_LSR_WIDE_ZPmZ_B = 2485, - AArch64_LSR_WIDE_ZPmZ_H = 2486, - AArch64_LSR_WIDE_ZPmZ_S = 2487, - AArch64_LSR_WIDE_ZZZ_B = 2488, - AArch64_LSR_WIDE_ZZZ_H = 2489, - AArch64_LSR_WIDE_ZZZ_S = 2490, - AArch64_LSR_ZPmI_B = 2491, - AArch64_LSR_ZPmI_D = 2492, - AArch64_LSR_ZPmI_H = 2493, - AArch64_LSR_ZPmI_S = 2494, - AArch64_LSR_ZPmZ_B = 2495, - AArch64_LSR_ZPmZ_D = 2496, - AArch64_LSR_ZPmZ_H = 2497, - AArch64_LSR_ZPmZ_S = 2498, - AArch64_LSR_ZZI_B = 2499, - AArch64_LSR_ZZI_D = 2500, - AArch64_LSR_ZZI_H = 2501, - AArch64_LSR_ZZI_S = 2502, - AArch64_MADDWrrr = 2503, - AArch64_MADDXrrr = 2504, - AArch64_MAD_ZPmZZ_B = 2505, - AArch64_MAD_ZPmZZ_D = 2506, - AArch64_MAD_ZPmZZ_H = 2507, - AArch64_MAD_ZPmZZ_S = 2508, - AArch64_MLA_ZPmZZ_B = 2509, - AArch64_MLA_ZPmZZ_D = 2510, - AArch64_MLA_ZPmZZ_H = 2511, - AArch64_MLA_ZPmZZ_S = 2512, - AArch64_MLAv16i8 = 2513, - AArch64_MLAv2i32 = 2514, - AArch64_MLAv2i32_indexed = 2515, - AArch64_MLAv4i16 = 2516, - AArch64_MLAv4i16_indexed = 2517, - AArch64_MLAv4i32 = 2518, - AArch64_MLAv4i32_indexed = 2519, - AArch64_MLAv8i16 = 2520, - AArch64_MLAv8i16_indexed = 2521, - AArch64_MLAv8i8 = 2522, - AArch64_MLS_ZPmZZ_B = 2523, - AArch64_MLS_ZPmZZ_D = 2524, - AArch64_MLS_ZPmZZ_H = 2525, - AArch64_MLS_ZPmZZ_S = 2526, - AArch64_MLSv16i8 = 2527, - AArch64_MLSv2i32 = 2528, - AArch64_MLSv2i32_indexed = 2529, - AArch64_MLSv4i16 = 2530, - AArch64_MLSv4i16_indexed = 2531, - AArch64_MLSv4i32 = 2532, - AArch64_MLSv4i32_indexed = 2533, - AArch64_MLSv8i16 = 2534, - AArch64_MLSv8i16_indexed = 2535, - AArch64_MLSv8i8 = 2536, - AArch64_MOVID = 2537, - AArch64_MOVIv16b_ns = 2538, - AArch64_MOVIv2d_ns = 2539, - AArch64_MOVIv2i32 = 2540, - AArch64_MOVIv2s_msl = 2541, - AArch64_MOVIv4i16 = 2542, - AArch64_MOVIv4i32 = 2543, - AArch64_MOVIv4s_msl = 2544, - AArch64_MOVIv8b_ns = 2545, - AArch64_MOVIv8i16 = 2546, - AArch64_MOVKWi = 2547, - AArch64_MOVKXi = 2548, - AArch64_MOVNWi = 2549, - AArch64_MOVNXi = 2550, - AArch64_MOVPRFX_ZPmZ_B = 2551, - AArch64_MOVPRFX_ZPmZ_D = 2552, - AArch64_MOVPRFX_ZPmZ_H = 2553, - AArch64_MOVPRFX_ZPmZ_S = 2554, - AArch64_MOVPRFX_ZPzZ_B = 2555, - AArch64_MOVPRFX_ZPzZ_D = 2556, - AArch64_MOVPRFX_ZPzZ_H = 2557, - AArch64_MOVPRFX_ZPzZ_S = 2558, - AArch64_MOVPRFX_ZZ = 2559, - AArch64_MOVZWi = 2560, - AArch64_MOVZXi = 2561, - AArch64_MOVaddr = 2562, - AArch64_MOVaddrBA = 2563, - AArch64_MOVaddrCP = 2564, - AArch64_MOVaddrEXT = 2565, - AArch64_MOVaddrJT = 2566, - AArch64_MOVaddrTLS = 2567, - AArch64_MOVbaseTLS = 2568, - AArch64_MOVi32imm = 2569, - AArch64_MOVi64imm = 2570, - AArch64_MRS = 2571, - AArch64_MSB_ZPmZZ_B = 2572, - AArch64_MSB_ZPmZZ_D = 2573, - AArch64_MSB_ZPmZZ_H = 2574, - AArch64_MSB_ZPmZZ_S = 2575, - AArch64_MSR = 2576, - AArch64_MSRpstateImm1 = 2577, - AArch64_MSRpstateImm4 = 2578, - AArch64_MSUBWrrr = 2579, - AArch64_MSUBXrrr = 2580, - AArch64_MUL_ZI_B = 2581, - AArch64_MUL_ZI_D = 2582, - AArch64_MUL_ZI_H = 2583, - AArch64_MUL_ZI_S = 2584, - AArch64_MUL_ZPmZ_B = 2585, - AArch64_MUL_ZPmZ_D = 2586, - AArch64_MUL_ZPmZ_H = 2587, - AArch64_MUL_ZPmZ_S = 2588, - AArch64_MULv16i8 = 2589, - AArch64_MULv2i32 = 2590, - AArch64_MULv2i32_indexed = 2591, - AArch64_MULv4i16 = 2592, - AArch64_MULv4i16_indexed = 2593, - AArch64_MULv4i32 = 2594, - AArch64_MULv4i32_indexed = 2595, - AArch64_MULv8i16 = 2596, - AArch64_MULv8i16_indexed = 2597, - AArch64_MULv8i8 = 2598, - AArch64_MVNIv2i32 = 2599, - AArch64_MVNIv2s_msl = 2600, - AArch64_MVNIv4i16 = 2601, - AArch64_MVNIv4i32 = 2602, - AArch64_MVNIv4s_msl = 2603, - AArch64_MVNIv8i16 = 2604, - AArch64_NANDS_PPzPP = 2605, - AArch64_NAND_PPzPP = 2606, - AArch64_NEG_ZPmZ_B = 2607, - AArch64_NEG_ZPmZ_D = 2608, - AArch64_NEG_ZPmZ_H = 2609, - AArch64_NEG_ZPmZ_S = 2610, - AArch64_NEGv16i8 = 2611, - AArch64_NEGv1i64 = 2612, - AArch64_NEGv2i32 = 2613, - AArch64_NEGv2i64 = 2614, - AArch64_NEGv4i16 = 2615, - AArch64_NEGv4i32 = 2616, - AArch64_NEGv8i16 = 2617, - AArch64_NEGv8i8 = 2618, - AArch64_NORS_PPzPP = 2619, - AArch64_NOR_PPzPP = 2620, - AArch64_NOT_ZPmZ_B = 2621, - AArch64_NOT_ZPmZ_D = 2622, - AArch64_NOT_ZPmZ_H = 2623, - AArch64_NOT_ZPmZ_S = 2624, - AArch64_NOTv16i8 = 2625, - AArch64_NOTv8i8 = 2626, - AArch64_ORNS_PPzPP = 2627, - AArch64_ORNWrr = 2628, - AArch64_ORNWrs = 2629, - AArch64_ORNXrr = 2630, - AArch64_ORNXrs = 2631, - AArch64_ORN_PPzPP = 2632, - AArch64_ORNv16i8 = 2633, - AArch64_ORNv8i8 = 2634, - AArch64_ORRS_PPzPP = 2635, - AArch64_ORRWri = 2636, - AArch64_ORRWrr = 2637, - AArch64_ORRWrs = 2638, - AArch64_ORRXri = 2639, - AArch64_ORRXrr = 2640, - AArch64_ORRXrs = 2641, - AArch64_ORR_PPzPP = 2642, - AArch64_ORR_ZI = 2643, - AArch64_ORR_ZPmZ_B = 2644, - AArch64_ORR_ZPmZ_D = 2645, - AArch64_ORR_ZPmZ_H = 2646, - AArch64_ORR_ZPmZ_S = 2647, - AArch64_ORR_ZZZ = 2648, - AArch64_ORRv16i8 = 2649, - AArch64_ORRv2i32 = 2650, - AArch64_ORRv4i16 = 2651, - AArch64_ORRv4i32 = 2652, - AArch64_ORRv8i16 = 2653, - AArch64_ORRv8i8 = 2654, - AArch64_ORV_VPZ_B = 2655, - AArch64_ORV_VPZ_D = 2656, - AArch64_ORV_VPZ_H = 2657, - AArch64_ORV_VPZ_S = 2658, - AArch64_PACDA = 2659, - AArch64_PACDB = 2660, - AArch64_PACDZA = 2661, - AArch64_PACDZB = 2662, - AArch64_PACGA = 2663, - AArch64_PACIA = 2664, - AArch64_PACIA1716 = 2665, - AArch64_PACIASP = 2666, - AArch64_PACIAZ = 2667, - AArch64_PACIB = 2668, - AArch64_PACIB1716 = 2669, - AArch64_PACIBSP = 2670, - AArch64_PACIBZ = 2671, - AArch64_PACIZA = 2672, - AArch64_PACIZB = 2673, - AArch64_PFALSE = 2674, - AArch64_PMULLv16i8 = 2675, - AArch64_PMULLv1i64 = 2676, - AArch64_PMULLv2i64 = 2677, - AArch64_PMULLv8i8 = 2678, - AArch64_PMULv16i8 = 2679, - AArch64_PMULv8i8 = 2680, - AArch64_PNEXT_B = 2681, - AArch64_PNEXT_D = 2682, - AArch64_PNEXT_H = 2683, - AArch64_PNEXT_S = 2684, - AArch64_PRFB_D_PZI = 2685, - AArch64_PRFB_D_SCALED = 2686, - AArch64_PRFB_D_SXTW_SCALED = 2687, - AArch64_PRFB_D_UXTW_SCALED = 2688, - AArch64_PRFB_PRI = 2689, - AArch64_PRFB_PRR = 2690, - AArch64_PRFB_S_PZI = 2691, - AArch64_PRFB_S_SXTW_SCALED = 2692, - AArch64_PRFB_S_UXTW_SCALED = 2693, - AArch64_PRFD_D_PZI = 2694, - AArch64_PRFD_D_SCALED = 2695, - AArch64_PRFD_D_SXTW_SCALED = 2696, - AArch64_PRFD_D_UXTW_SCALED = 2697, - AArch64_PRFD_PRI = 2698, - AArch64_PRFD_PRR = 2699, - AArch64_PRFD_S_PZI = 2700, - AArch64_PRFD_S_SXTW_SCALED = 2701, - AArch64_PRFD_S_UXTW_SCALED = 2702, - AArch64_PRFH_D_PZI = 2703, - AArch64_PRFH_D_SCALED = 2704, - AArch64_PRFH_D_SXTW_SCALED = 2705, - AArch64_PRFH_D_UXTW_SCALED = 2706, - AArch64_PRFH_PRI = 2707, - AArch64_PRFH_PRR = 2708, - AArch64_PRFH_S_PZI = 2709, - AArch64_PRFH_S_SXTW_SCALED = 2710, - AArch64_PRFH_S_UXTW_SCALED = 2711, - AArch64_PRFMl = 2712, - AArch64_PRFMroW = 2713, - AArch64_PRFMroX = 2714, - AArch64_PRFMui = 2715, - AArch64_PRFS_PRR = 2716, - AArch64_PRFUMi = 2717, - AArch64_PRFW_D_PZI = 2718, - AArch64_PRFW_D_SCALED = 2719, - AArch64_PRFW_D_SXTW_SCALED = 2720, - AArch64_PRFW_D_UXTW_SCALED = 2721, - AArch64_PRFW_PRI = 2722, - AArch64_PRFW_S_PZI = 2723, - AArch64_PRFW_S_SXTW_SCALED = 2724, - AArch64_PRFW_S_UXTW_SCALED = 2725, - AArch64_PTEST_PP = 2726, - AArch64_PTRUES_B = 2727, - AArch64_PTRUES_D = 2728, - AArch64_PTRUES_H = 2729, - AArch64_PTRUES_S = 2730, - AArch64_PTRUE_B = 2731, - AArch64_PTRUE_D = 2732, - AArch64_PTRUE_H = 2733, - AArch64_PTRUE_S = 2734, - AArch64_PUNPKHI_PP = 2735, - AArch64_PUNPKLO_PP = 2736, - AArch64_RADDHNv2i64_v2i32 = 2737, - AArch64_RADDHNv2i64_v4i32 = 2738, - AArch64_RADDHNv4i32_v4i16 = 2739, - AArch64_RADDHNv4i32_v8i16 = 2740, - AArch64_RADDHNv8i16_v16i8 = 2741, - AArch64_RADDHNv8i16_v8i8 = 2742, - AArch64_RAX1 = 2743, - AArch64_RBITWr = 2744, - AArch64_RBITXr = 2745, - AArch64_RBIT_ZPmZ_B = 2746, - AArch64_RBIT_ZPmZ_D = 2747, - AArch64_RBIT_ZPmZ_H = 2748, - AArch64_RBIT_ZPmZ_S = 2749, - AArch64_RBITv16i8 = 2750, - AArch64_RBITv8i8 = 2751, - AArch64_RDFFRS_PPz = 2752, - AArch64_RDFFR_P = 2753, - AArch64_RDFFR_PPz = 2754, - AArch64_RDVLI_XI = 2755, - AArch64_RET = 2756, - AArch64_RETAA = 2757, - AArch64_RETAB = 2758, - AArch64_RET_ReallyLR = 2759, - AArch64_REV16Wr = 2760, - AArch64_REV16Xr = 2761, - AArch64_REV16v16i8 = 2762, - AArch64_REV16v8i8 = 2763, - AArch64_REV32Xr = 2764, - AArch64_REV32v16i8 = 2765, - AArch64_REV32v4i16 = 2766, - AArch64_REV32v8i16 = 2767, - AArch64_REV32v8i8 = 2768, - AArch64_REV64v16i8 = 2769, - AArch64_REV64v2i32 = 2770, - AArch64_REV64v4i16 = 2771, - AArch64_REV64v4i32 = 2772, - AArch64_REV64v8i16 = 2773, - AArch64_REV64v8i8 = 2774, - AArch64_REVB_ZPmZ_D = 2775, - AArch64_REVB_ZPmZ_H = 2776, - AArch64_REVB_ZPmZ_S = 2777, - AArch64_REVH_ZPmZ_D = 2778, - AArch64_REVH_ZPmZ_S = 2779, - AArch64_REVW_ZPmZ_D = 2780, - AArch64_REVWr = 2781, - AArch64_REVXr = 2782, - AArch64_REV_PP_B = 2783, - AArch64_REV_PP_D = 2784, - AArch64_REV_PP_H = 2785, - AArch64_REV_PP_S = 2786, - AArch64_REV_ZZ_B = 2787, - AArch64_REV_ZZ_D = 2788, - AArch64_REV_ZZ_H = 2789, - AArch64_REV_ZZ_S = 2790, - AArch64_RMIF = 2791, - AArch64_RORVWr = 2792, - AArch64_RORVXr = 2793, - AArch64_RSHRNv16i8_shift = 2794, - AArch64_RSHRNv2i32_shift = 2795, - AArch64_RSHRNv4i16_shift = 2796, - AArch64_RSHRNv4i32_shift = 2797, - AArch64_RSHRNv8i16_shift = 2798, - AArch64_RSHRNv8i8_shift = 2799, - AArch64_RSUBHNv2i64_v2i32 = 2800, - AArch64_RSUBHNv2i64_v4i32 = 2801, - AArch64_RSUBHNv4i32_v4i16 = 2802, - AArch64_RSUBHNv4i32_v8i16 = 2803, - AArch64_RSUBHNv8i16_v16i8 = 2804, - AArch64_RSUBHNv8i16_v8i8 = 2805, - AArch64_SABALv16i8_v8i16 = 2806, - AArch64_SABALv2i32_v2i64 = 2807, - AArch64_SABALv4i16_v4i32 = 2808, - AArch64_SABALv4i32_v2i64 = 2809, - AArch64_SABALv8i16_v4i32 = 2810, - AArch64_SABALv8i8_v8i16 = 2811, - AArch64_SABAv16i8 = 2812, - AArch64_SABAv2i32 = 2813, - AArch64_SABAv4i16 = 2814, - AArch64_SABAv4i32 = 2815, - AArch64_SABAv8i16 = 2816, - AArch64_SABAv8i8 = 2817, - AArch64_SABDLv16i8_v8i16 = 2818, - AArch64_SABDLv2i32_v2i64 = 2819, - AArch64_SABDLv4i16_v4i32 = 2820, - AArch64_SABDLv4i32_v2i64 = 2821, - AArch64_SABDLv8i16_v4i32 = 2822, - AArch64_SABDLv8i8_v8i16 = 2823, - AArch64_SABD_ZPmZ_B = 2824, - AArch64_SABD_ZPmZ_D = 2825, - AArch64_SABD_ZPmZ_H = 2826, - AArch64_SABD_ZPmZ_S = 2827, - AArch64_SABDv16i8 = 2828, - AArch64_SABDv2i32 = 2829, - AArch64_SABDv4i16 = 2830, - AArch64_SABDv4i32 = 2831, - AArch64_SABDv8i16 = 2832, - AArch64_SABDv8i8 = 2833, - AArch64_SADALPv16i8_v8i16 = 2834, - AArch64_SADALPv2i32_v1i64 = 2835, - AArch64_SADALPv4i16_v2i32 = 2836, - AArch64_SADALPv4i32_v2i64 = 2837, - AArch64_SADALPv8i16_v4i32 = 2838, - AArch64_SADALPv8i8_v4i16 = 2839, - AArch64_SADDLPv16i8_v8i16 = 2840, - AArch64_SADDLPv2i32_v1i64 = 2841, - AArch64_SADDLPv4i16_v2i32 = 2842, - AArch64_SADDLPv4i32_v2i64 = 2843, - AArch64_SADDLPv8i16_v4i32 = 2844, - AArch64_SADDLPv8i8_v4i16 = 2845, - AArch64_SADDLVv16i8v = 2846, - AArch64_SADDLVv4i16v = 2847, - AArch64_SADDLVv4i32v = 2848, - AArch64_SADDLVv8i16v = 2849, - AArch64_SADDLVv8i8v = 2850, - AArch64_SADDLv16i8_v8i16 = 2851, - AArch64_SADDLv2i32_v2i64 = 2852, - AArch64_SADDLv4i16_v4i32 = 2853, - AArch64_SADDLv4i32_v2i64 = 2854, - AArch64_SADDLv8i16_v4i32 = 2855, - AArch64_SADDLv8i8_v8i16 = 2856, - AArch64_SADDV_VPZ_B = 2857, - AArch64_SADDV_VPZ_H = 2858, - AArch64_SADDV_VPZ_S = 2859, - AArch64_SADDWv16i8_v8i16 = 2860, - AArch64_SADDWv2i32_v2i64 = 2861, - AArch64_SADDWv4i16_v4i32 = 2862, - AArch64_SADDWv4i32_v2i64 = 2863, - AArch64_SADDWv8i16_v4i32 = 2864, - AArch64_SADDWv8i8_v8i16 = 2865, - AArch64_SBCSWr = 2866, - AArch64_SBCSXr = 2867, - AArch64_SBCWr = 2868, - AArch64_SBCXr = 2869, - AArch64_SBFMWri = 2870, - AArch64_SBFMXri = 2871, - AArch64_SCVTFSWDri = 2872, - AArch64_SCVTFSWHri = 2873, - AArch64_SCVTFSWSri = 2874, - AArch64_SCVTFSXDri = 2875, - AArch64_SCVTFSXHri = 2876, - AArch64_SCVTFSXSri = 2877, - AArch64_SCVTFUWDri = 2878, - AArch64_SCVTFUWHri = 2879, - AArch64_SCVTFUWSri = 2880, - AArch64_SCVTFUXDri = 2881, - AArch64_SCVTFUXHri = 2882, - AArch64_SCVTFUXSri = 2883, - AArch64_SCVTF_ZPmZ_DtoD = 2884, - AArch64_SCVTF_ZPmZ_DtoH = 2885, - AArch64_SCVTF_ZPmZ_DtoS = 2886, - AArch64_SCVTF_ZPmZ_HtoH = 2887, - AArch64_SCVTF_ZPmZ_StoD = 2888, - AArch64_SCVTF_ZPmZ_StoH = 2889, - AArch64_SCVTF_ZPmZ_StoS = 2890, - AArch64_SCVTFd = 2891, - AArch64_SCVTFh = 2892, - AArch64_SCVTFs = 2893, - AArch64_SCVTFv1i16 = 2894, - AArch64_SCVTFv1i32 = 2895, - AArch64_SCVTFv1i64 = 2896, - AArch64_SCVTFv2f32 = 2897, - AArch64_SCVTFv2f64 = 2898, - AArch64_SCVTFv2i32_shift = 2899, - AArch64_SCVTFv2i64_shift = 2900, - AArch64_SCVTFv4f16 = 2901, - AArch64_SCVTFv4f32 = 2902, - AArch64_SCVTFv4i16_shift = 2903, - AArch64_SCVTFv4i32_shift = 2904, - AArch64_SCVTFv8f16 = 2905, - AArch64_SCVTFv8i16_shift = 2906, - AArch64_SDIVR_ZPmZ_D = 2907, - AArch64_SDIVR_ZPmZ_S = 2908, - AArch64_SDIVWr = 2909, - AArch64_SDIVXr = 2910, - AArch64_SDIV_ZPmZ_D = 2911, - AArch64_SDIV_ZPmZ_S = 2912, - AArch64_SDOT_ZZZI_D = 2913, - AArch64_SDOT_ZZZI_S = 2914, - AArch64_SDOT_ZZZ_D = 2915, - AArch64_SDOT_ZZZ_S = 2916, - AArch64_SDOTlanev16i8 = 2917, - AArch64_SDOTlanev8i8 = 2918, - AArch64_SDOTv16i8 = 2919, - AArch64_SDOTv8i8 = 2920, - AArch64_SEL_PPPP = 2921, - AArch64_SEL_ZPZZ_B = 2922, - AArch64_SEL_ZPZZ_D = 2923, - AArch64_SEL_ZPZZ_H = 2924, - AArch64_SEL_ZPZZ_S = 2925, - AArch64_SETF16 = 2926, - AArch64_SETF8 = 2927, - AArch64_SETFFR = 2928, - AArch64_SHA1Crrr = 2929, - AArch64_SHA1Hrr = 2930, - AArch64_SHA1Mrrr = 2931, - AArch64_SHA1Prrr = 2932, - AArch64_SHA1SU0rrr = 2933, - AArch64_SHA1SU1rr = 2934, - AArch64_SHA256H2rrr = 2935, - AArch64_SHA256Hrrr = 2936, - AArch64_SHA256SU0rr = 2937, - AArch64_SHA256SU1rrr = 2938, - AArch64_SHA512H = 2939, - AArch64_SHA512H2 = 2940, - AArch64_SHA512SU0 = 2941, - AArch64_SHA512SU1 = 2942, - AArch64_SHADDv16i8 = 2943, - AArch64_SHADDv2i32 = 2944, - AArch64_SHADDv4i16 = 2945, - AArch64_SHADDv4i32 = 2946, - AArch64_SHADDv8i16 = 2947, - AArch64_SHADDv8i8 = 2948, - AArch64_SHLLv16i8 = 2949, - AArch64_SHLLv2i32 = 2950, - AArch64_SHLLv4i16 = 2951, - AArch64_SHLLv4i32 = 2952, - AArch64_SHLLv8i16 = 2953, - AArch64_SHLLv8i8 = 2954, - AArch64_SHLd = 2955, - AArch64_SHLv16i8_shift = 2956, - AArch64_SHLv2i32_shift = 2957, - AArch64_SHLv2i64_shift = 2958, - AArch64_SHLv4i16_shift = 2959, - AArch64_SHLv4i32_shift = 2960, - AArch64_SHLv8i16_shift = 2961, - AArch64_SHLv8i8_shift = 2962, - AArch64_SHRNv16i8_shift = 2963, - AArch64_SHRNv2i32_shift = 2964, - AArch64_SHRNv4i16_shift = 2965, - AArch64_SHRNv4i32_shift = 2966, - AArch64_SHRNv8i16_shift = 2967, - AArch64_SHRNv8i8_shift = 2968, - AArch64_SHSUBv16i8 = 2969, - AArch64_SHSUBv2i32 = 2970, - AArch64_SHSUBv4i16 = 2971, - AArch64_SHSUBv4i32 = 2972, - AArch64_SHSUBv8i16 = 2973, - AArch64_SHSUBv8i8 = 2974, - AArch64_SLId = 2975, - AArch64_SLIv16i8_shift = 2976, - AArch64_SLIv2i32_shift = 2977, - AArch64_SLIv2i64_shift = 2978, - AArch64_SLIv4i16_shift = 2979, - AArch64_SLIv4i32_shift = 2980, - AArch64_SLIv8i16_shift = 2981, - AArch64_SLIv8i8_shift = 2982, - AArch64_SM3PARTW1 = 2983, - AArch64_SM3PARTW2 = 2984, - AArch64_SM3SS1 = 2985, - AArch64_SM3TT1A = 2986, - AArch64_SM3TT1B = 2987, - AArch64_SM3TT2A = 2988, - AArch64_SM3TT2B = 2989, - AArch64_SM4E = 2990, - AArch64_SM4ENCKEY = 2991, - AArch64_SMADDLrrr = 2992, - AArch64_SMAXPv16i8 = 2993, - AArch64_SMAXPv2i32 = 2994, - AArch64_SMAXPv4i16 = 2995, - AArch64_SMAXPv4i32 = 2996, - AArch64_SMAXPv8i16 = 2997, - AArch64_SMAXPv8i8 = 2998, - AArch64_SMAXV_VPZ_B = 2999, - AArch64_SMAXV_VPZ_D = 3000, - AArch64_SMAXV_VPZ_H = 3001, - AArch64_SMAXV_VPZ_S = 3002, - AArch64_SMAXVv16i8v = 3003, - AArch64_SMAXVv4i16v = 3004, - AArch64_SMAXVv4i32v = 3005, - AArch64_SMAXVv8i16v = 3006, - AArch64_SMAXVv8i8v = 3007, - AArch64_SMAX_ZI_B = 3008, - AArch64_SMAX_ZI_D = 3009, - AArch64_SMAX_ZI_H = 3010, - AArch64_SMAX_ZI_S = 3011, - AArch64_SMAX_ZPmZ_B = 3012, - AArch64_SMAX_ZPmZ_D = 3013, - AArch64_SMAX_ZPmZ_H = 3014, - AArch64_SMAX_ZPmZ_S = 3015, - AArch64_SMAXv16i8 = 3016, - AArch64_SMAXv2i32 = 3017, - AArch64_SMAXv4i16 = 3018, - AArch64_SMAXv4i32 = 3019, - AArch64_SMAXv8i16 = 3020, - AArch64_SMAXv8i8 = 3021, - AArch64_SMC = 3022, - AArch64_SMINPv16i8 = 3023, - AArch64_SMINPv2i32 = 3024, - AArch64_SMINPv4i16 = 3025, - AArch64_SMINPv4i32 = 3026, - AArch64_SMINPv8i16 = 3027, - AArch64_SMINPv8i8 = 3028, - AArch64_SMINV_VPZ_B = 3029, - AArch64_SMINV_VPZ_D = 3030, - AArch64_SMINV_VPZ_H = 3031, - AArch64_SMINV_VPZ_S = 3032, - AArch64_SMINVv16i8v = 3033, - AArch64_SMINVv4i16v = 3034, - AArch64_SMINVv4i32v = 3035, - AArch64_SMINVv8i16v = 3036, - AArch64_SMINVv8i8v = 3037, - AArch64_SMIN_ZI_B = 3038, - AArch64_SMIN_ZI_D = 3039, - AArch64_SMIN_ZI_H = 3040, - AArch64_SMIN_ZI_S = 3041, - AArch64_SMIN_ZPmZ_B = 3042, - AArch64_SMIN_ZPmZ_D = 3043, - AArch64_SMIN_ZPmZ_H = 3044, - AArch64_SMIN_ZPmZ_S = 3045, - AArch64_SMINv16i8 = 3046, - AArch64_SMINv2i32 = 3047, - AArch64_SMINv4i16 = 3048, - AArch64_SMINv4i32 = 3049, - AArch64_SMINv8i16 = 3050, - AArch64_SMINv8i8 = 3051, - AArch64_SMLALv16i8_v8i16 = 3052, - AArch64_SMLALv2i32_indexed = 3053, - AArch64_SMLALv2i32_v2i64 = 3054, - AArch64_SMLALv4i16_indexed = 3055, - AArch64_SMLALv4i16_v4i32 = 3056, - AArch64_SMLALv4i32_indexed = 3057, - AArch64_SMLALv4i32_v2i64 = 3058, - AArch64_SMLALv8i16_indexed = 3059, - AArch64_SMLALv8i16_v4i32 = 3060, - AArch64_SMLALv8i8_v8i16 = 3061, - AArch64_SMLSLv16i8_v8i16 = 3062, - AArch64_SMLSLv2i32_indexed = 3063, - AArch64_SMLSLv2i32_v2i64 = 3064, - AArch64_SMLSLv4i16_indexed = 3065, - AArch64_SMLSLv4i16_v4i32 = 3066, - AArch64_SMLSLv4i32_indexed = 3067, - AArch64_SMLSLv4i32_v2i64 = 3068, - AArch64_SMLSLv8i16_indexed = 3069, - AArch64_SMLSLv8i16_v4i32 = 3070, - AArch64_SMLSLv8i8_v8i16 = 3071, - AArch64_SMOVvi16to32 = 3072, - AArch64_SMOVvi16to64 = 3073, - AArch64_SMOVvi32to64 = 3074, - AArch64_SMOVvi8to32 = 3075, - AArch64_SMOVvi8to64 = 3076, - AArch64_SMSUBLrrr = 3077, - AArch64_SMULH_ZPmZ_B = 3078, - AArch64_SMULH_ZPmZ_D = 3079, - AArch64_SMULH_ZPmZ_H = 3080, - AArch64_SMULH_ZPmZ_S = 3081, - AArch64_SMULHrr = 3082, - AArch64_SMULLv16i8_v8i16 = 3083, - AArch64_SMULLv2i32_indexed = 3084, - AArch64_SMULLv2i32_v2i64 = 3085, - AArch64_SMULLv4i16_indexed = 3086, - AArch64_SMULLv4i16_v4i32 = 3087, - AArch64_SMULLv4i32_indexed = 3088, - AArch64_SMULLv4i32_v2i64 = 3089, - AArch64_SMULLv8i16_indexed = 3090, - AArch64_SMULLv8i16_v4i32 = 3091, - AArch64_SMULLv8i8_v8i16 = 3092, - AArch64_SPLICE_ZPZ_B = 3093, - AArch64_SPLICE_ZPZ_D = 3094, - AArch64_SPLICE_ZPZ_H = 3095, - AArch64_SPLICE_ZPZ_S = 3096, - AArch64_SQABSv16i8 = 3097, - AArch64_SQABSv1i16 = 3098, - AArch64_SQABSv1i32 = 3099, - AArch64_SQABSv1i64 = 3100, - AArch64_SQABSv1i8 = 3101, - AArch64_SQABSv2i32 = 3102, - AArch64_SQABSv2i64 = 3103, - AArch64_SQABSv4i16 = 3104, - AArch64_SQABSv4i32 = 3105, - AArch64_SQABSv8i16 = 3106, - AArch64_SQABSv8i8 = 3107, - AArch64_SQADD_ZI_B = 3108, - AArch64_SQADD_ZI_D = 3109, - AArch64_SQADD_ZI_H = 3110, - AArch64_SQADD_ZI_S = 3111, - AArch64_SQADD_ZZZ_B = 3112, - AArch64_SQADD_ZZZ_D = 3113, - AArch64_SQADD_ZZZ_H = 3114, - AArch64_SQADD_ZZZ_S = 3115, - AArch64_SQADDv16i8 = 3116, - AArch64_SQADDv1i16 = 3117, - AArch64_SQADDv1i32 = 3118, - AArch64_SQADDv1i64 = 3119, - AArch64_SQADDv1i8 = 3120, - AArch64_SQADDv2i32 = 3121, - AArch64_SQADDv2i64 = 3122, - AArch64_SQADDv4i16 = 3123, - AArch64_SQADDv4i32 = 3124, - AArch64_SQADDv8i16 = 3125, - AArch64_SQADDv8i8 = 3126, - AArch64_SQDECB_XPiI = 3127, - AArch64_SQDECB_XPiWdI = 3128, - AArch64_SQDECD_XPiI = 3129, - AArch64_SQDECD_XPiWdI = 3130, - AArch64_SQDECD_ZPiI = 3131, - AArch64_SQDECH_XPiI = 3132, - AArch64_SQDECH_XPiWdI = 3133, - AArch64_SQDECH_ZPiI = 3134, - AArch64_SQDECP_XPWd_B = 3135, - AArch64_SQDECP_XPWd_D = 3136, - AArch64_SQDECP_XPWd_H = 3137, - AArch64_SQDECP_XPWd_S = 3138, - AArch64_SQDECP_XP_B = 3139, - AArch64_SQDECP_XP_D = 3140, - AArch64_SQDECP_XP_H = 3141, - AArch64_SQDECP_XP_S = 3142, - AArch64_SQDECP_ZP_D = 3143, - AArch64_SQDECP_ZP_H = 3144, - AArch64_SQDECP_ZP_S = 3145, - AArch64_SQDECW_XPiI = 3146, - AArch64_SQDECW_XPiWdI = 3147, - AArch64_SQDECW_ZPiI = 3148, - AArch64_SQDMLALi16 = 3149, - AArch64_SQDMLALi32 = 3150, - AArch64_SQDMLALv1i32_indexed = 3151, - AArch64_SQDMLALv1i64_indexed = 3152, - AArch64_SQDMLALv2i32_indexed = 3153, - AArch64_SQDMLALv2i32_v2i64 = 3154, - AArch64_SQDMLALv4i16_indexed = 3155, - AArch64_SQDMLALv4i16_v4i32 = 3156, - AArch64_SQDMLALv4i32_indexed = 3157, - AArch64_SQDMLALv4i32_v2i64 = 3158, - AArch64_SQDMLALv8i16_indexed = 3159, - AArch64_SQDMLALv8i16_v4i32 = 3160, - AArch64_SQDMLSLi16 = 3161, - AArch64_SQDMLSLi32 = 3162, - AArch64_SQDMLSLv1i32_indexed = 3163, - AArch64_SQDMLSLv1i64_indexed = 3164, - AArch64_SQDMLSLv2i32_indexed = 3165, - AArch64_SQDMLSLv2i32_v2i64 = 3166, - AArch64_SQDMLSLv4i16_indexed = 3167, - AArch64_SQDMLSLv4i16_v4i32 = 3168, - AArch64_SQDMLSLv4i32_indexed = 3169, - AArch64_SQDMLSLv4i32_v2i64 = 3170, - AArch64_SQDMLSLv8i16_indexed = 3171, - AArch64_SQDMLSLv8i16_v4i32 = 3172, - AArch64_SQDMULHv1i16 = 3173, - AArch64_SQDMULHv1i16_indexed = 3174, - AArch64_SQDMULHv1i32 = 3175, - AArch64_SQDMULHv1i32_indexed = 3176, - AArch64_SQDMULHv2i32 = 3177, - AArch64_SQDMULHv2i32_indexed = 3178, - AArch64_SQDMULHv4i16 = 3179, - AArch64_SQDMULHv4i16_indexed = 3180, - AArch64_SQDMULHv4i32 = 3181, - AArch64_SQDMULHv4i32_indexed = 3182, - AArch64_SQDMULHv8i16 = 3183, - AArch64_SQDMULHv8i16_indexed = 3184, - AArch64_SQDMULLi16 = 3185, - AArch64_SQDMULLi32 = 3186, - AArch64_SQDMULLv1i32_indexed = 3187, - AArch64_SQDMULLv1i64_indexed = 3188, - AArch64_SQDMULLv2i32_indexed = 3189, - AArch64_SQDMULLv2i32_v2i64 = 3190, - AArch64_SQDMULLv4i16_indexed = 3191, - AArch64_SQDMULLv4i16_v4i32 = 3192, - AArch64_SQDMULLv4i32_indexed = 3193, - AArch64_SQDMULLv4i32_v2i64 = 3194, - AArch64_SQDMULLv8i16_indexed = 3195, - AArch64_SQDMULLv8i16_v4i32 = 3196, - AArch64_SQINCB_XPiI = 3197, - AArch64_SQINCB_XPiWdI = 3198, - AArch64_SQINCD_XPiI = 3199, - AArch64_SQINCD_XPiWdI = 3200, - AArch64_SQINCD_ZPiI = 3201, - AArch64_SQINCH_XPiI = 3202, - AArch64_SQINCH_XPiWdI = 3203, - AArch64_SQINCH_ZPiI = 3204, - AArch64_SQINCP_XPWd_B = 3205, - AArch64_SQINCP_XPWd_D = 3206, - AArch64_SQINCP_XPWd_H = 3207, - AArch64_SQINCP_XPWd_S = 3208, - AArch64_SQINCP_XP_B = 3209, - AArch64_SQINCP_XP_D = 3210, - AArch64_SQINCP_XP_H = 3211, - AArch64_SQINCP_XP_S = 3212, - AArch64_SQINCP_ZP_D = 3213, - AArch64_SQINCP_ZP_H = 3214, - AArch64_SQINCP_ZP_S = 3215, - AArch64_SQINCW_XPiI = 3216, - AArch64_SQINCW_XPiWdI = 3217, - AArch64_SQINCW_ZPiI = 3218, - AArch64_SQNEGv16i8 = 3219, - AArch64_SQNEGv1i16 = 3220, - AArch64_SQNEGv1i32 = 3221, - AArch64_SQNEGv1i64 = 3222, - AArch64_SQNEGv1i8 = 3223, - AArch64_SQNEGv2i32 = 3224, - AArch64_SQNEGv2i64 = 3225, - AArch64_SQNEGv4i16 = 3226, - AArch64_SQNEGv4i32 = 3227, - AArch64_SQNEGv8i16 = 3228, - AArch64_SQNEGv8i8 = 3229, - AArch64_SQRDMLAHi16_indexed = 3230, - AArch64_SQRDMLAHi32_indexed = 3231, - AArch64_SQRDMLAHv1i16 = 3232, - AArch64_SQRDMLAHv1i32 = 3233, - AArch64_SQRDMLAHv2i32 = 3234, - AArch64_SQRDMLAHv2i32_indexed = 3235, - AArch64_SQRDMLAHv4i16 = 3236, - AArch64_SQRDMLAHv4i16_indexed = 3237, - AArch64_SQRDMLAHv4i32 = 3238, - AArch64_SQRDMLAHv4i32_indexed = 3239, - AArch64_SQRDMLAHv8i16 = 3240, - AArch64_SQRDMLAHv8i16_indexed = 3241, - AArch64_SQRDMLSHi16_indexed = 3242, - AArch64_SQRDMLSHi32_indexed = 3243, - AArch64_SQRDMLSHv1i16 = 3244, - AArch64_SQRDMLSHv1i32 = 3245, - AArch64_SQRDMLSHv2i32 = 3246, - AArch64_SQRDMLSHv2i32_indexed = 3247, - AArch64_SQRDMLSHv4i16 = 3248, - AArch64_SQRDMLSHv4i16_indexed = 3249, - AArch64_SQRDMLSHv4i32 = 3250, - AArch64_SQRDMLSHv4i32_indexed = 3251, - AArch64_SQRDMLSHv8i16 = 3252, - AArch64_SQRDMLSHv8i16_indexed = 3253, - AArch64_SQRDMULHv1i16 = 3254, - AArch64_SQRDMULHv1i16_indexed = 3255, - AArch64_SQRDMULHv1i32 = 3256, - AArch64_SQRDMULHv1i32_indexed = 3257, - AArch64_SQRDMULHv2i32 = 3258, - AArch64_SQRDMULHv2i32_indexed = 3259, - AArch64_SQRDMULHv4i16 = 3260, - AArch64_SQRDMULHv4i16_indexed = 3261, - AArch64_SQRDMULHv4i32 = 3262, - AArch64_SQRDMULHv4i32_indexed = 3263, - AArch64_SQRDMULHv8i16 = 3264, - AArch64_SQRDMULHv8i16_indexed = 3265, - AArch64_SQRSHLv16i8 = 3266, - AArch64_SQRSHLv1i16 = 3267, - AArch64_SQRSHLv1i32 = 3268, - AArch64_SQRSHLv1i64 = 3269, - AArch64_SQRSHLv1i8 = 3270, - AArch64_SQRSHLv2i32 = 3271, - AArch64_SQRSHLv2i64 = 3272, - AArch64_SQRSHLv4i16 = 3273, - AArch64_SQRSHLv4i32 = 3274, - AArch64_SQRSHLv8i16 = 3275, - AArch64_SQRSHLv8i8 = 3276, - AArch64_SQRSHRNb = 3277, - AArch64_SQRSHRNh = 3278, - AArch64_SQRSHRNs = 3279, - AArch64_SQRSHRNv16i8_shift = 3280, - AArch64_SQRSHRNv2i32_shift = 3281, - AArch64_SQRSHRNv4i16_shift = 3282, - AArch64_SQRSHRNv4i32_shift = 3283, - AArch64_SQRSHRNv8i16_shift = 3284, - AArch64_SQRSHRNv8i8_shift = 3285, - AArch64_SQRSHRUNb = 3286, - AArch64_SQRSHRUNh = 3287, - AArch64_SQRSHRUNs = 3288, - AArch64_SQRSHRUNv16i8_shift = 3289, - AArch64_SQRSHRUNv2i32_shift = 3290, - AArch64_SQRSHRUNv4i16_shift = 3291, - AArch64_SQRSHRUNv4i32_shift = 3292, - AArch64_SQRSHRUNv8i16_shift = 3293, - AArch64_SQRSHRUNv8i8_shift = 3294, - AArch64_SQSHLUb = 3295, - AArch64_SQSHLUd = 3296, - AArch64_SQSHLUh = 3297, - AArch64_SQSHLUs = 3298, - AArch64_SQSHLUv16i8_shift = 3299, - AArch64_SQSHLUv2i32_shift = 3300, - AArch64_SQSHLUv2i64_shift = 3301, - AArch64_SQSHLUv4i16_shift = 3302, - AArch64_SQSHLUv4i32_shift = 3303, - AArch64_SQSHLUv8i16_shift = 3304, - AArch64_SQSHLUv8i8_shift = 3305, - AArch64_SQSHLb = 3306, - AArch64_SQSHLd = 3307, - AArch64_SQSHLh = 3308, - AArch64_SQSHLs = 3309, - AArch64_SQSHLv16i8 = 3310, - AArch64_SQSHLv16i8_shift = 3311, - AArch64_SQSHLv1i16 = 3312, - AArch64_SQSHLv1i32 = 3313, - AArch64_SQSHLv1i64 = 3314, - AArch64_SQSHLv1i8 = 3315, - AArch64_SQSHLv2i32 = 3316, - AArch64_SQSHLv2i32_shift = 3317, - AArch64_SQSHLv2i64 = 3318, - AArch64_SQSHLv2i64_shift = 3319, - AArch64_SQSHLv4i16 = 3320, - AArch64_SQSHLv4i16_shift = 3321, - AArch64_SQSHLv4i32 = 3322, - AArch64_SQSHLv4i32_shift = 3323, - AArch64_SQSHLv8i16 = 3324, - AArch64_SQSHLv8i16_shift = 3325, - AArch64_SQSHLv8i8 = 3326, - AArch64_SQSHLv8i8_shift = 3327, - AArch64_SQSHRNb = 3328, - AArch64_SQSHRNh = 3329, - AArch64_SQSHRNs = 3330, - AArch64_SQSHRNv16i8_shift = 3331, - AArch64_SQSHRNv2i32_shift = 3332, - AArch64_SQSHRNv4i16_shift = 3333, - AArch64_SQSHRNv4i32_shift = 3334, - AArch64_SQSHRNv8i16_shift = 3335, - AArch64_SQSHRNv8i8_shift = 3336, - AArch64_SQSHRUNb = 3337, - AArch64_SQSHRUNh = 3338, - AArch64_SQSHRUNs = 3339, - AArch64_SQSHRUNv16i8_shift = 3340, - AArch64_SQSHRUNv2i32_shift = 3341, - AArch64_SQSHRUNv4i16_shift = 3342, - AArch64_SQSHRUNv4i32_shift = 3343, - AArch64_SQSHRUNv8i16_shift = 3344, - AArch64_SQSHRUNv8i8_shift = 3345, - AArch64_SQSUB_ZI_B = 3346, - AArch64_SQSUB_ZI_D = 3347, - AArch64_SQSUB_ZI_H = 3348, - AArch64_SQSUB_ZI_S = 3349, - AArch64_SQSUB_ZZZ_B = 3350, - AArch64_SQSUB_ZZZ_D = 3351, - AArch64_SQSUB_ZZZ_H = 3352, - AArch64_SQSUB_ZZZ_S = 3353, - AArch64_SQSUBv16i8 = 3354, - AArch64_SQSUBv1i16 = 3355, - AArch64_SQSUBv1i32 = 3356, - AArch64_SQSUBv1i64 = 3357, - AArch64_SQSUBv1i8 = 3358, - AArch64_SQSUBv2i32 = 3359, - AArch64_SQSUBv2i64 = 3360, - AArch64_SQSUBv4i16 = 3361, - AArch64_SQSUBv4i32 = 3362, - AArch64_SQSUBv8i16 = 3363, - AArch64_SQSUBv8i8 = 3364, - AArch64_SQXTNv16i8 = 3365, - AArch64_SQXTNv1i16 = 3366, - AArch64_SQXTNv1i32 = 3367, - AArch64_SQXTNv1i8 = 3368, - AArch64_SQXTNv2i32 = 3369, - AArch64_SQXTNv4i16 = 3370, - AArch64_SQXTNv4i32 = 3371, - AArch64_SQXTNv8i16 = 3372, - AArch64_SQXTNv8i8 = 3373, - AArch64_SQXTUNv16i8 = 3374, - AArch64_SQXTUNv1i16 = 3375, - AArch64_SQXTUNv1i32 = 3376, - AArch64_SQXTUNv1i8 = 3377, - AArch64_SQXTUNv2i32 = 3378, - AArch64_SQXTUNv4i16 = 3379, - AArch64_SQXTUNv4i32 = 3380, - AArch64_SQXTUNv8i16 = 3381, - AArch64_SQXTUNv8i8 = 3382, - AArch64_SRHADDv16i8 = 3383, - AArch64_SRHADDv2i32 = 3384, - AArch64_SRHADDv4i16 = 3385, - AArch64_SRHADDv4i32 = 3386, - AArch64_SRHADDv8i16 = 3387, - AArch64_SRHADDv8i8 = 3388, - AArch64_SRId = 3389, - AArch64_SRIv16i8_shift = 3390, - AArch64_SRIv2i32_shift = 3391, - AArch64_SRIv2i64_shift = 3392, - AArch64_SRIv4i16_shift = 3393, - AArch64_SRIv4i32_shift = 3394, - AArch64_SRIv8i16_shift = 3395, - AArch64_SRIv8i8_shift = 3396, - AArch64_SRSHLv16i8 = 3397, - AArch64_SRSHLv1i64 = 3398, - AArch64_SRSHLv2i32 = 3399, - AArch64_SRSHLv2i64 = 3400, - AArch64_SRSHLv4i16 = 3401, - AArch64_SRSHLv4i32 = 3402, - AArch64_SRSHLv8i16 = 3403, - AArch64_SRSHLv8i8 = 3404, - AArch64_SRSHRd = 3405, - AArch64_SRSHRv16i8_shift = 3406, - AArch64_SRSHRv2i32_shift = 3407, - AArch64_SRSHRv2i64_shift = 3408, - AArch64_SRSHRv4i16_shift = 3409, - AArch64_SRSHRv4i32_shift = 3410, - AArch64_SRSHRv8i16_shift = 3411, - AArch64_SRSHRv8i8_shift = 3412, - AArch64_SRSRAd = 3413, - AArch64_SRSRAv16i8_shift = 3414, - AArch64_SRSRAv2i32_shift = 3415, - AArch64_SRSRAv2i64_shift = 3416, - AArch64_SRSRAv4i16_shift = 3417, - AArch64_SRSRAv4i32_shift = 3418, - AArch64_SRSRAv8i16_shift = 3419, - AArch64_SRSRAv8i8_shift = 3420, - AArch64_SSHLLv16i8_shift = 3421, - AArch64_SSHLLv2i32_shift = 3422, - AArch64_SSHLLv4i16_shift = 3423, - AArch64_SSHLLv4i32_shift = 3424, - AArch64_SSHLLv8i16_shift = 3425, - AArch64_SSHLLv8i8_shift = 3426, - AArch64_SSHLv16i8 = 3427, - AArch64_SSHLv1i64 = 3428, - AArch64_SSHLv2i32 = 3429, - AArch64_SSHLv2i64 = 3430, - AArch64_SSHLv4i16 = 3431, - AArch64_SSHLv4i32 = 3432, - AArch64_SSHLv8i16 = 3433, - AArch64_SSHLv8i8 = 3434, - AArch64_SSHRd = 3435, - AArch64_SSHRv16i8_shift = 3436, - AArch64_SSHRv2i32_shift = 3437, - AArch64_SSHRv2i64_shift = 3438, - AArch64_SSHRv4i16_shift = 3439, - AArch64_SSHRv4i32_shift = 3440, - AArch64_SSHRv8i16_shift = 3441, - AArch64_SSHRv8i8_shift = 3442, - AArch64_SSRAd = 3443, - AArch64_SSRAv16i8_shift = 3444, - AArch64_SSRAv2i32_shift = 3445, - AArch64_SSRAv2i64_shift = 3446, - AArch64_SSRAv4i16_shift = 3447, - AArch64_SSRAv4i32_shift = 3448, - AArch64_SSRAv8i16_shift = 3449, - AArch64_SSRAv8i8_shift = 3450, - AArch64_SST1B_D = 3451, - AArch64_SST1B_D_IMM = 3452, - AArch64_SST1B_D_SXTW = 3453, - AArch64_SST1B_D_UXTW = 3454, - AArch64_SST1B_S_IMM = 3455, - AArch64_SST1B_S_SXTW = 3456, - AArch64_SST1B_S_UXTW = 3457, - AArch64_SST1D = 3458, - AArch64_SST1D_IMM = 3459, - AArch64_SST1D_SCALED = 3460, - AArch64_SST1D_SXTW = 3461, - AArch64_SST1D_SXTW_SCALED = 3462, - AArch64_SST1D_UXTW = 3463, - AArch64_SST1D_UXTW_SCALED = 3464, - AArch64_SST1H_D = 3465, - AArch64_SST1H_D_IMM = 3466, - AArch64_SST1H_D_SCALED = 3467, - AArch64_SST1H_D_SXTW = 3468, - AArch64_SST1H_D_SXTW_SCALED = 3469, - AArch64_SST1H_D_UXTW = 3470, - AArch64_SST1H_D_UXTW_SCALED = 3471, - AArch64_SST1H_S_IMM = 3472, - AArch64_SST1H_S_SXTW = 3473, - AArch64_SST1H_S_SXTW_SCALED = 3474, - AArch64_SST1H_S_UXTW = 3475, - AArch64_SST1H_S_UXTW_SCALED = 3476, - AArch64_SST1W_D = 3477, - AArch64_SST1W_D_IMM = 3478, - AArch64_SST1W_D_SCALED = 3479, - AArch64_SST1W_D_SXTW = 3480, - AArch64_SST1W_D_SXTW_SCALED = 3481, - AArch64_SST1W_D_UXTW = 3482, - AArch64_SST1W_D_UXTW_SCALED = 3483, - AArch64_SST1W_IMM = 3484, - AArch64_SST1W_SXTW = 3485, - AArch64_SST1W_SXTW_SCALED = 3486, - AArch64_SST1W_UXTW = 3487, - AArch64_SST1W_UXTW_SCALED = 3488, - AArch64_SSUBLv16i8_v8i16 = 3489, - AArch64_SSUBLv2i32_v2i64 = 3490, - AArch64_SSUBLv4i16_v4i32 = 3491, - AArch64_SSUBLv4i32_v2i64 = 3492, - AArch64_SSUBLv8i16_v4i32 = 3493, - AArch64_SSUBLv8i8_v8i16 = 3494, - AArch64_SSUBWv16i8_v8i16 = 3495, - AArch64_SSUBWv2i32_v2i64 = 3496, - AArch64_SSUBWv4i16_v4i32 = 3497, - AArch64_SSUBWv4i32_v2i64 = 3498, - AArch64_SSUBWv8i16_v4i32 = 3499, - AArch64_SSUBWv8i8_v8i16 = 3500, - AArch64_ST1B = 3501, - AArch64_ST1B_D = 3502, - AArch64_ST1B_D_IMM = 3503, - AArch64_ST1B_H = 3504, - AArch64_ST1B_H_IMM = 3505, - AArch64_ST1B_IMM = 3506, - AArch64_ST1B_S = 3507, - AArch64_ST1B_S_IMM = 3508, - AArch64_ST1D = 3509, - AArch64_ST1D_IMM = 3510, - AArch64_ST1Fourv16b = 3511, - AArch64_ST1Fourv16b_POST = 3512, - AArch64_ST1Fourv1d = 3513, - AArch64_ST1Fourv1d_POST = 3514, - AArch64_ST1Fourv2d = 3515, - AArch64_ST1Fourv2d_POST = 3516, - AArch64_ST1Fourv2s = 3517, - AArch64_ST1Fourv2s_POST = 3518, - AArch64_ST1Fourv4h = 3519, - AArch64_ST1Fourv4h_POST = 3520, - AArch64_ST1Fourv4s = 3521, - AArch64_ST1Fourv4s_POST = 3522, - AArch64_ST1Fourv8b = 3523, - AArch64_ST1Fourv8b_POST = 3524, - AArch64_ST1Fourv8h = 3525, - AArch64_ST1Fourv8h_POST = 3526, - AArch64_ST1H = 3527, - AArch64_ST1H_D = 3528, - AArch64_ST1H_D_IMM = 3529, - AArch64_ST1H_IMM = 3530, - AArch64_ST1H_S = 3531, - AArch64_ST1H_S_IMM = 3532, - AArch64_ST1Onev16b = 3533, - AArch64_ST1Onev16b_POST = 3534, - AArch64_ST1Onev1d = 3535, - AArch64_ST1Onev1d_POST = 3536, - AArch64_ST1Onev2d = 3537, - AArch64_ST1Onev2d_POST = 3538, - AArch64_ST1Onev2s = 3539, - AArch64_ST1Onev2s_POST = 3540, - AArch64_ST1Onev4h = 3541, - AArch64_ST1Onev4h_POST = 3542, - AArch64_ST1Onev4s = 3543, - AArch64_ST1Onev4s_POST = 3544, - AArch64_ST1Onev8b = 3545, - AArch64_ST1Onev8b_POST = 3546, - AArch64_ST1Onev8h = 3547, - AArch64_ST1Onev8h_POST = 3548, - AArch64_ST1Threev16b = 3549, - AArch64_ST1Threev16b_POST = 3550, - AArch64_ST1Threev1d = 3551, - AArch64_ST1Threev1d_POST = 3552, - AArch64_ST1Threev2d = 3553, - AArch64_ST1Threev2d_POST = 3554, - AArch64_ST1Threev2s = 3555, - AArch64_ST1Threev2s_POST = 3556, - AArch64_ST1Threev4h = 3557, - AArch64_ST1Threev4h_POST = 3558, - AArch64_ST1Threev4s = 3559, - AArch64_ST1Threev4s_POST = 3560, - AArch64_ST1Threev8b = 3561, - AArch64_ST1Threev8b_POST = 3562, - AArch64_ST1Threev8h = 3563, - AArch64_ST1Threev8h_POST = 3564, - AArch64_ST1Twov16b = 3565, - AArch64_ST1Twov16b_POST = 3566, - AArch64_ST1Twov1d = 3567, - AArch64_ST1Twov1d_POST = 3568, - AArch64_ST1Twov2d = 3569, - AArch64_ST1Twov2d_POST = 3570, - AArch64_ST1Twov2s = 3571, - AArch64_ST1Twov2s_POST = 3572, - AArch64_ST1Twov4h = 3573, - AArch64_ST1Twov4h_POST = 3574, - AArch64_ST1Twov4s = 3575, - AArch64_ST1Twov4s_POST = 3576, - AArch64_ST1Twov8b = 3577, - AArch64_ST1Twov8b_POST = 3578, - AArch64_ST1Twov8h = 3579, - AArch64_ST1Twov8h_POST = 3580, - AArch64_ST1W = 3581, - AArch64_ST1W_D = 3582, - AArch64_ST1W_D_IMM = 3583, - AArch64_ST1W_IMM = 3584, - AArch64_ST1i16 = 3585, - AArch64_ST1i16_POST = 3586, - AArch64_ST1i32 = 3587, - AArch64_ST1i32_POST = 3588, - AArch64_ST1i64 = 3589, - AArch64_ST1i64_POST = 3590, - AArch64_ST1i8 = 3591, - AArch64_ST1i8_POST = 3592, - AArch64_ST2B = 3593, - AArch64_ST2B_IMM = 3594, - AArch64_ST2D = 3595, - AArch64_ST2D_IMM = 3596, - AArch64_ST2H = 3597, - AArch64_ST2H_IMM = 3598, - AArch64_ST2Twov16b = 3599, - AArch64_ST2Twov16b_POST = 3600, - AArch64_ST2Twov2d = 3601, - AArch64_ST2Twov2d_POST = 3602, - AArch64_ST2Twov2s = 3603, - AArch64_ST2Twov2s_POST = 3604, - AArch64_ST2Twov4h = 3605, - AArch64_ST2Twov4h_POST = 3606, - AArch64_ST2Twov4s = 3607, - AArch64_ST2Twov4s_POST = 3608, - AArch64_ST2Twov8b = 3609, - AArch64_ST2Twov8b_POST = 3610, - AArch64_ST2Twov8h = 3611, - AArch64_ST2Twov8h_POST = 3612, - AArch64_ST2W = 3613, - AArch64_ST2W_IMM = 3614, - AArch64_ST2i16 = 3615, - AArch64_ST2i16_POST = 3616, - AArch64_ST2i32 = 3617, - AArch64_ST2i32_POST = 3618, - AArch64_ST2i64 = 3619, - AArch64_ST2i64_POST = 3620, - AArch64_ST2i8 = 3621, - AArch64_ST2i8_POST = 3622, - AArch64_ST3B = 3623, - AArch64_ST3B_IMM = 3624, - AArch64_ST3D = 3625, - AArch64_ST3D_IMM = 3626, - AArch64_ST3H = 3627, - AArch64_ST3H_IMM = 3628, - AArch64_ST3Threev16b = 3629, - AArch64_ST3Threev16b_POST = 3630, - AArch64_ST3Threev2d = 3631, - AArch64_ST3Threev2d_POST = 3632, - AArch64_ST3Threev2s = 3633, - AArch64_ST3Threev2s_POST = 3634, - AArch64_ST3Threev4h = 3635, - AArch64_ST3Threev4h_POST = 3636, - AArch64_ST3Threev4s = 3637, - AArch64_ST3Threev4s_POST = 3638, - AArch64_ST3Threev8b = 3639, - AArch64_ST3Threev8b_POST = 3640, - AArch64_ST3Threev8h = 3641, - AArch64_ST3Threev8h_POST = 3642, - AArch64_ST3W = 3643, - AArch64_ST3W_IMM = 3644, - AArch64_ST3i16 = 3645, - AArch64_ST3i16_POST = 3646, - AArch64_ST3i32 = 3647, - AArch64_ST3i32_POST = 3648, - AArch64_ST3i64 = 3649, - AArch64_ST3i64_POST = 3650, - AArch64_ST3i8 = 3651, - AArch64_ST3i8_POST = 3652, - AArch64_ST4B = 3653, - AArch64_ST4B_IMM = 3654, - AArch64_ST4D = 3655, - AArch64_ST4D_IMM = 3656, - AArch64_ST4Fourv16b = 3657, - AArch64_ST4Fourv16b_POST = 3658, - AArch64_ST4Fourv2d = 3659, - AArch64_ST4Fourv2d_POST = 3660, - AArch64_ST4Fourv2s = 3661, - AArch64_ST4Fourv2s_POST = 3662, - AArch64_ST4Fourv4h = 3663, - AArch64_ST4Fourv4h_POST = 3664, - AArch64_ST4Fourv4s = 3665, - AArch64_ST4Fourv4s_POST = 3666, - AArch64_ST4Fourv8b = 3667, - AArch64_ST4Fourv8b_POST = 3668, - AArch64_ST4Fourv8h = 3669, - AArch64_ST4Fourv8h_POST = 3670, - AArch64_ST4H = 3671, - AArch64_ST4H_IMM = 3672, - AArch64_ST4W = 3673, - AArch64_ST4W_IMM = 3674, - AArch64_ST4i16 = 3675, - AArch64_ST4i16_POST = 3676, - AArch64_ST4i32 = 3677, - AArch64_ST4i32_POST = 3678, - AArch64_ST4i64 = 3679, - AArch64_ST4i64_POST = 3680, - AArch64_ST4i8 = 3681, - AArch64_ST4i8_POST = 3682, - AArch64_STLLRB = 3683, - AArch64_STLLRH = 3684, - AArch64_STLLRW = 3685, - AArch64_STLLRX = 3686, - AArch64_STLRB = 3687, - AArch64_STLRH = 3688, - AArch64_STLRW = 3689, - AArch64_STLRX = 3690, - AArch64_STLURBi = 3691, - AArch64_STLURHi = 3692, - AArch64_STLURWi = 3693, - AArch64_STLURXi = 3694, - AArch64_STLXPW = 3695, - AArch64_STLXPX = 3696, - AArch64_STLXRB = 3697, - AArch64_STLXRH = 3698, - AArch64_STLXRW = 3699, - AArch64_STLXRX = 3700, - AArch64_STNPDi = 3701, - AArch64_STNPQi = 3702, - AArch64_STNPSi = 3703, - AArch64_STNPWi = 3704, - AArch64_STNPXi = 3705, - AArch64_STNT1B_ZRI = 3706, - AArch64_STNT1B_ZRR = 3707, - AArch64_STNT1D_ZRI = 3708, - AArch64_STNT1D_ZRR = 3709, - AArch64_STNT1H_ZRI = 3710, - AArch64_STNT1H_ZRR = 3711, - AArch64_STNT1W_ZRI = 3712, - AArch64_STNT1W_ZRR = 3713, - AArch64_STPDi = 3714, - AArch64_STPDpost = 3715, - AArch64_STPDpre = 3716, - AArch64_STPQi = 3717, - AArch64_STPQpost = 3718, - AArch64_STPQpre = 3719, - AArch64_STPSi = 3720, - AArch64_STPSpost = 3721, - AArch64_STPSpre = 3722, - AArch64_STPWi = 3723, - AArch64_STPWpost = 3724, - AArch64_STPWpre = 3725, - AArch64_STPXi = 3726, - AArch64_STPXpost = 3727, - AArch64_STPXpre = 3728, - AArch64_STRBBpost = 3729, - AArch64_STRBBpre = 3730, - AArch64_STRBBroW = 3731, - AArch64_STRBBroX = 3732, - AArch64_STRBBui = 3733, - AArch64_STRBpost = 3734, - AArch64_STRBpre = 3735, - AArch64_STRBroW = 3736, - AArch64_STRBroX = 3737, - AArch64_STRBui = 3738, - AArch64_STRDpost = 3739, - AArch64_STRDpre = 3740, - AArch64_STRDroW = 3741, - AArch64_STRDroX = 3742, - AArch64_STRDui = 3743, - AArch64_STRHHpost = 3744, - AArch64_STRHHpre = 3745, - AArch64_STRHHroW = 3746, - AArch64_STRHHroX = 3747, - AArch64_STRHHui = 3748, - AArch64_STRHpost = 3749, - AArch64_STRHpre = 3750, - AArch64_STRHroW = 3751, - AArch64_STRHroX = 3752, - AArch64_STRHui = 3753, - AArch64_STRQpost = 3754, - AArch64_STRQpre = 3755, - AArch64_STRQroW = 3756, - AArch64_STRQroX = 3757, - AArch64_STRQui = 3758, - AArch64_STRSpost = 3759, - AArch64_STRSpre = 3760, - AArch64_STRSroW = 3761, - AArch64_STRSroX = 3762, - AArch64_STRSui = 3763, - AArch64_STRWpost = 3764, - AArch64_STRWpre = 3765, - AArch64_STRWroW = 3766, - AArch64_STRWroX = 3767, - AArch64_STRWui = 3768, - AArch64_STRXpost = 3769, - AArch64_STRXpre = 3770, - AArch64_STRXroW = 3771, - AArch64_STRXroX = 3772, - AArch64_STRXui = 3773, - AArch64_STR_PXI = 3774, - AArch64_STR_ZXI = 3775, - AArch64_STTRBi = 3776, - AArch64_STTRHi = 3777, - AArch64_STTRWi = 3778, - AArch64_STTRXi = 3779, - AArch64_STURBBi = 3780, - AArch64_STURBi = 3781, - AArch64_STURDi = 3782, - AArch64_STURHHi = 3783, - AArch64_STURHi = 3784, - AArch64_STURQi = 3785, - AArch64_STURSi = 3786, - AArch64_STURWi = 3787, - AArch64_STURXi = 3788, - AArch64_STXPW = 3789, - AArch64_STXPX = 3790, - AArch64_STXRB = 3791, - AArch64_STXRH = 3792, - AArch64_STXRW = 3793, - AArch64_STXRX = 3794, - AArch64_SUBHNv2i64_v2i32 = 3795, - AArch64_SUBHNv2i64_v4i32 = 3796, - AArch64_SUBHNv4i32_v4i16 = 3797, - AArch64_SUBHNv4i32_v8i16 = 3798, - AArch64_SUBHNv8i16_v16i8 = 3799, - AArch64_SUBHNv8i16_v8i8 = 3800, - AArch64_SUBR_ZI_B = 3801, - AArch64_SUBR_ZI_D = 3802, - AArch64_SUBR_ZI_H = 3803, - AArch64_SUBR_ZI_S = 3804, - AArch64_SUBR_ZPmZ_B = 3805, - AArch64_SUBR_ZPmZ_D = 3806, - AArch64_SUBR_ZPmZ_H = 3807, - AArch64_SUBR_ZPmZ_S = 3808, - AArch64_SUBSWri = 3809, - AArch64_SUBSWrr = 3810, - AArch64_SUBSWrs = 3811, - AArch64_SUBSWrx = 3812, - AArch64_SUBSXri = 3813, - AArch64_SUBSXrr = 3814, - AArch64_SUBSXrs = 3815, - AArch64_SUBSXrx = 3816, - AArch64_SUBSXrx64 = 3817, - AArch64_SUBWri = 3818, - AArch64_SUBWrr = 3819, - AArch64_SUBWrs = 3820, - AArch64_SUBWrx = 3821, - AArch64_SUBXri = 3822, - AArch64_SUBXrr = 3823, - AArch64_SUBXrs = 3824, - AArch64_SUBXrx = 3825, - AArch64_SUBXrx64 = 3826, - AArch64_SUB_ZI_B = 3827, - AArch64_SUB_ZI_D = 3828, - AArch64_SUB_ZI_H = 3829, - AArch64_SUB_ZI_S = 3830, - AArch64_SUB_ZPmZ_B = 3831, - AArch64_SUB_ZPmZ_D = 3832, - AArch64_SUB_ZPmZ_H = 3833, - AArch64_SUB_ZPmZ_S = 3834, - AArch64_SUB_ZZZ_B = 3835, - AArch64_SUB_ZZZ_D = 3836, - AArch64_SUB_ZZZ_H = 3837, - AArch64_SUB_ZZZ_S = 3838, - AArch64_SUBv16i8 = 3839, - AArch64_SUBv1i64 = 3840, - AArch64_SUBv2i32 = 3841, - AArch64_SUBv2i64 = 3842, - AArch64_SUBv4i16 = 3843, - AArch64_SUBv4i32 = 3844, - AArch64_SUBv8i16 = 3845, - AArch64_SUBv8i8 = 3846, - AArch64_SUNPKHI_ZZ_D = 3847, - AArch64_SUNPKHI_ZZ_H = 3848, - AArch64_SUNPKHI_ZZ_S = 3849, - AArch64_SUNPKLO_ZZ_D = 3850, - AArch64_SUNPKLO_ZZ_H = 3851, - AArch64_SUNPKLO_ZZ_S = 3852, - AArch64_SUQADDv16i8 = 3853, - AArch64_SUQADDv1i16 = 3854, - AArch64_SUQADDv1i32 = 3855, - AArch64_SUQADDv1i64 = 3856, - AArch64_SUQADDv1i8 = 3857, - AArch64_SUQADDv2i32 = 3858, - AArch64_SUQADDv2i64 = 3859, - AArch64_SUQADDv4i16 = 3860, - AArch64_SUQADDv4i32 = 3861, - AArch64_SUQADDv8i16 = 3862, - AArch64_SUQADDv8i8 = 3863, - AArch64_SVC = 3864, - AArch64_SWPAB = 3865, - AArch64_SWPAH = 3866, - AArch64_SWPALB = 3867, - AArch64_SWPALH = 3868, - AArch64_SWPALW = 3869, - AArch64_SWPALX = 3870, - AArch64_SWPAW = 3871, - AArch64_SWPAX = 3872, - AArch64_SWPB = 3873, - AArch64_SWPH = 3874, - AArch64_SWPLB = 3875, - AArch64_SWPLH = 3876, - AArch64_SWPLW = 3877, - AArch64_SWPLX = 3878, - AArch64_SWPW = 3879, - AArch64_SWPX = 3880, - AArch64_SXTB_ZPmZ_D = 3881, - AArch64_SXTB_ZPmZ_H = 3882, - AArch64_SXTB_ZPmZ_S = 3883, - AArch64_SXTH_ZPmZ_D = 3884, - AArch64_SXTH_ZPmZ_S = 3885, - AArch64_SXTW_ZPmZ_D = 3886, - AArch64_SYSLxt = 3887, - AArch64_SYSxt = 3888, - AArch64_TBL_ZZZ_B = 3889, - AArch64_TBL_ZZZ_D = 3890, - AArch64_TBL_ZZZ_H = 3891, - AArch64_TBL_ZZZ_S = 3892, - AArch64_TBLv16i8Four = 3893, - AArch64_TBLv16i8One = 3894, - AArch64_TBLv16i8Three = 3895, - AArch64_TBLv16i8Two = 3896, - AArch64_TBLv8i8Four = 3897, - AArch64_TBLv8i8One = 3898, - AArch64_TBLv8i8Three = 3899, - AArch64_TBLv8i8Two = 3900, - AArch64_TBNZW = 3901, - AArch64_TBNZX = 3902, - AArch64_TBXv16i8Four = 3903, - AArch64_TBXv16i8One = 3904, - AArch64_TBXv16i8Three = 3905, - AArch64_TBXv16i8Two = 3906, - AArch64_TBXv8i8Four = 3907, - AArch64_TBXv8i8One = 3908, - AArch64_TBXv8i8Three = 3909, - AArch64_TBXv8i8Two = 3910, - AArch64_TBZW = 3911, - AArch64_TBZX = 3912, - AArch64_TCRETURNdi = 3913, - AArch64_TCRETURNri = 3914, - AArch64_TLSDESCCALL = 3915, - AArch64_TLSDESC_CALLSEQ = 3916, - AArch64_TRN1_PPP_B = 3917, - AArch64_TRN1_PPP_D = 3918, - AArch64_TRN1_PPP_H = 3919, - AArch64_TRN1_PPP_S = 3920, - AArch64_TRN1_ZZZ_B = 3921, - AArch64_TRN1_ZZZ_D = 3922, - AArch64_TRN1_ZZZ_H = 3923, - AArch64_TRN1_ZZZ_S = 3924, - AArch64_TRN1v16i8 = 3925, - AArch64_TRN1v2i32 = 3926, - AArch64_TRN1v2i64 = 3927, - AArch64_TRN1v4i16 = 3928, - AArch64_TRN1v4i32 = 3929, - AArch64_TRN1v8i16 = 3930, - AArch64_TRN1v8i8 = 3931, - AArch64_TRN2_PPP_B = 3932, - AArch64_TRN2_PPP_D = 3933, - AArch64_TRN2_PPP_H = 3934, - AArch64_TRN2_PPP_S = 3935, - AArch64_TRN2_ZZZ_B = 3936, - AArch64_TRN2_ZZZ_D = 3937, - AArch64_TRN2_ZZZ_H = 3938, - AArch64_TRN2_ZZZ_S = 3939, - AArch64_TRN2v16i8 = 3940, - AArch64_TRN2v2i32 = 3941, - AArch64_TRN2v2i64 = 3942, - AArch64_TRN2v4i16 = 3943, - AArch64_TRN2v4i32 = 3944, - AArch64_TRN2v8i16 = 3945, - AArch64_TRN2v8i8 = 3946, - AArch64_TSB = 3947, - AArch64_UABALv16i8_v8i16 = 3948, - AArch64_UABALv2i32_v2i64 = 3949, - AArch64_UABALv4i16_v4i32 = 3950, - AArch64_UABALv4i32_v2i64 = 3951, - AArch64_UABALv8i16_v4i32 = 3952, - AArch64_UABALv8i8_v8i16 = 3953, - AArch64_UABAv16i8 = 3954, - AArch64_UABAv2i32 = 3955, - AArch64_UABAv4i16 = 3956, - AArch64_UABAv4i32 = 3957, - AArch64_UABAv8i16 = 3958, - AArch64_UABAv8i8 = 3959, - AArch64_UABDLv16i8_v8i16 = 3960, - AArch64_UABDLv2i32_v2i64 = 3961, - AArch64_UABDLv4i16_v4i32 = 3962, - AArch64_UABDLv4i32_v2i64 = 3963, - AArch64_UABDLv8i16_v4i32 = 3964, - AArch64_UABDLv8i8_v8i16 = 3965, - AArch64_UABD_ZPmZ_B = 3966, - AArch64_UABD_ZPmZ_D = 3967, - AArch64_UABD_ZPmZ_H = 3968, - AArch64_UABD_ZPmZ_S = 3969, - AArch64_UABDv16i8 = 3970, - AArch64_UABDv2i32 = 3971, - AArch64_UABDv4i16 = 3972, - AArch64_UABDv4i32 = 3973, - AArch64_UABDv8i16 = 3974, - AArch64_UABDv8i8 = 3975, - AArch64_UADALPv16i8_v8i16 = 3976, - AArch64_UADALPv2i32_v1i64 = 3977, - AArch64_UADALPv4i16_v2i32 = 3978, - AArch64_UADALPv4i32_v2i64 = 3979, - AArch64_UADALPv8i16_v4i32 = 3980, - AArch64_UADALPv8i8_v4i16 = 3981, - AArch64_UADDLPv16i8_v8i16 = 3982, - AArch64_UADDLPv2i32_v1i64 = 3983, - AArch64_UADDLPv4i16_v2i32 = 3984, - AArch64_UADDLPv4i32_v2i64 = 3985, - AArch64_UADDLPv8i16_v4i32 = 3986, - AArch64_UADDLPv8i8_v4i16 = 3987, - AArch64_UADDLVv16i8v = 3988, - AArch64_UADDLVv4i16v = 3989, - AArch64_UADDLVv4i32v = 3990, - AArch64_UADDLVv8i16v = 3991, - AArch64_UADDLVv8i8v = 3992, - AArch64_UADDLv16i8_v8i16 = 3993, - AArch64_UADDLv2i32_v2i64 = 3994, - AArch64_UADDLv4i16_v4i32 = 3995, - AArch64_UADDLv4i32_v2i64 = 3996, - AArch64_UADDLv8i16_v4i32 = 3997, - AArch64_UADDLv8i8_v8i16 = 3998, - AArch64_UADDV_VPZ_B = 3999, - AArch64_UADDV_VPZ_D = 4000, - AArch64_UADDV_VPZ_H = 4001, - AArch64_UADDV_VPZ_S = 4002, - AArch64_UADDWv16i8_v8i16 = 4003, - AArch64_UADDWv2i32_v2i64 = 4004, - AArch64_UADDWv4i16_v4i32 = 4005, - AArch64_UADDWv4i32_v2i64 = 4006, - AArch64_UADDWv8i16_v4i32 = 4007, - AArch64_UADDWv8i8_v8i16 = 4008, - AArch64_UBFMWri = 4009, - AArch64_UBFMXri = 4010, - AArch64_UCVTFSWDri = 4011, - AArch64_UCVTFSWHri = 4012, - AArch64_UCVTFSWSri = 4013, - AArch64_UCVTFSXDri = 4014, - AArch64_UCVTFSXHri = 4015, - AArch64_UCVTFSXSri = 4016, - AArch64_UCVTFUWDri = 4017, - AArch64_UCVTFUWHri = 4018, - AArch64_UCVTFUWSri = 4019, - AArch64_UCVTFUXDri = 4020, - AArch64_UCVTFUXHri = 4021, - AArch64_UCVTFUXSri = 4022, - AArch64_UCVTF_ZPmZ_DtoD = 4023, - AArch64_UCVTF_ZPmZ_DtoH = 4024, - AArch64_UCVTF_ZPmZ_DtoS = 4025, - AArch64_UCVTF_ZPmZ_HtoH = 4026, - AArch64_UCVTF_ZPmZ_StoD = 4027, - AArch64_UCVTF_ZPmZ_StoH = 4028, - AArch64_UCVTF_ZPmZ_StoS = 4029, - AArch64_UCVTFd = 4030, - AArch64_UCVTFh = 4031, - AArch64_UCVTFs = 4032, - AArch64_UCVTFv1i16 = 4033, - AArch64_UCVTFv1i32 = 4034, - AArch64_UCVTFv1i64 = 4035, - AArch64_UCVTFv2f32 = 4036, - AArch64_UCVTFv2f64 = 4037, - AArch64_UCVTFv2i32_shift = 4038, - AArch64_UCVTFv2i64_shift = 4039, - AArch64_UCVTFv4f16 = 4040, - AArch64_UCVTFv4f32 = 4041, - AArch64_UCVTFv4i16_shift = 4042, - AArch64_UCVTFv4i32_shift = 4043, - AArch64_UCVTFv8f16 = 4044, - AArch64_UCVTFv8i16_shift = 4045, - AArch64_UDIVR_ZPmZ_D = 4046, - AArch64_UDIVR_ZPmZ_S = 4047, - AArch64_UDIVWr = 4048, - AArch64_UDIVXr = 4049, - AArch64_UDIV_ZPmZ_D = 4050, - AArch64_UDIV_ZPmZ_S = 4051, - AArch64_UDOT_ZZZI_D = 4052, - AArch64_UDOT_ZZZI_S = 4053, - AArch64_UDOT_ZZZ_D = 4054, - AArch64_UDOT_ZZZ_S = 4055, - AArch64_UDOTlanev16i8 = 4056, - AArch64_UDOTlanev8i8 = 4057, - AArch64_UDOTv16i8 = 4058, - AArch64_UDOTv8i8 = 4059, - AArch64_UHADDv16i8 = 4060, - AArch64_UHADDv2i32 = 4061, - AArch64_UHADDv4i16 = 4062, - AArch64_UHADDv4i32 = 4063, - AArch64_UHADDv8i16 = 4064, - AArch64_UHADDv8i8 = 4065, - AArch64_UHSUBv16i8 = 4066, - AArch64_UHSUBv2i32 = 4067, - AArch64_UHSUBv4i16 = 4068, - AArch64_UHSUBv4i32 = 4069, - AArch64_UHSUBv8i16 = 4070, - AArch64_UHSUBv8i8 = 4071, - AArch64_UMADDLrrr = 4072, - AArch64_UMAXPv16i8 = 4073, - AArch64_UMAXPv2i32 = 4074, - AArch64_UMAXPv4i16 = 4075, - AArch64_UMAXPv4i32 = 4076, - AArch64_UMAXPv8i16 = 4077, - AArch64_UMAXPv8i8 = 4078, - AArch64_UMAXV_VPZ_B = 4079, - AArch64_UMAXV_VPZ_D = 4080, - AArch64_UMAXV_VPZ_H = 4081, - AArch64_UMAXV_VPZ_S = 4082, - AArch64_UMAXVv16i8v = 4083, - AArch64_UMAXVv4i16v = 4084, - AArch64_UMAXVv4i32v = 4085, - AArch64_UMAXVv8i16v = 4086, - AArch64_UMAXVv8i8v = 4087, - AArch64_UMAX_ZI_B = 4088, - AArch64_UMAX_ZI_D = 4089, - AArch64_UMAX_ZI_H = 4090, - AArch64_UMAX_ZI_S = 4091, - AArch64_UMAX_ZPmZ_B = 4092, - AArch64_UMAX_ZPmZ_D = 4093, - AArch64_UMAX_ZPmZ_H = 4094, - AArch64_UMAX_ZPmZ_S = 4095, - AArch64_UMAXv16i8 = 4096, - AArch64_UMAXv2i32 = 4097, - AArch64_UMAXv4i16 = 4098, - AArch64_UMAXv4i32 = 4099, - AArch64_UMAXv8i16 = 4100, - AArch64_UMAXv8i8 = 4101, - AArch64_UMINPv16i8 = 4102, - AArch64_UMINPv2i32 = 4103, - AArch64_UMINPv4i16 = 4104, - AArch64_UMINPv4i32 = 4105, - AArch64_UMINPv8i16 = 4106, - AArch64_UMINPv8i8 = 4107, - AArch64_UMINV_VPZ_B = 4108, - AArch64_UMINV_VPZ_D = 4109, - AArch64_UMINV_VPZ_H = 4110, - AArch64_UMINV_VPZ_S = 4111, - AArch64_UMINVv16i8v = 4112, - AArch64_UMINVv4i16v = 4113, - AArch64_UMINVv4i32v = 4114, - AArch64_UMINVv8i16v = 4115, - AArch64_UMINVv8i8v = 4116, - AArch64_UMIN_ZI_B = 4117, - AArch64_UMIN_ZI_D = 4118, - AArch64_UMIN_ZI_H = 4119, - AArch64_UMIN_ZI_S = 4120, - AArch64_UMIN_ZPmZ_B = 4121, - AArch64_UMIN_ZPmZ_D = 4122, - AArch64_UMIN_ZPmZ_H = 4123, - AArch64_UMIN_ZPmZ_S = 4124, - AArch64_UMINv16i8 = 4125, - AArch64_UMINv2i32 = 4126, - AArch64_UMINv4i16 = 4127, - AArch64_UMINv4i32 = 4128, - AArch64_UMINv8i16 = 4129, - AArch64_UMINv8i8 = 4130, - AArch64_UMLALv16i8_v8i16 = 4131, - AArch64_UMLALv2i32_indexed = 4132, - AArch64_UMLALv2i32_v2i64 = 4133, - AArch64_UMLALv4i16_indexed = 4134, - AArch64_UMLALv4i16_v4i32 = 4135, - AArch64_UMLALv4i32_indexed = 4136, - AArch64_UMLALv4i32_v2i64 = 4137, - AArch64_UMLALv8i16_indexed = 4138, - AArch64_UMLALv8i16_v4i32 = 4139, - AArch64_UMLALv8i8_v8i16 = 4140, - AArch64_UMLSLv16i8_v8i16 = 4141, - AArch64_UMLSLv2i32_indexed = 4142, - AArch64_UMLSLv2i32_v2i64 = 4143, - AArch64_UMLSLv4i16_indexed = 4144, - AArch64_UMLSLv4i16_v4i32 = 4145, - AArch64_UMLSLv4i32_indexed = 4146, - AArch64_UMLSLv4i32_v2i64 = 4147, - AArch64_UMLSLv8i16_indexed = 4148, - AArch64_UMLSLv8i16_v4i32 = 4149, - AArch64_UMLSLv8i8_v8i16 = 4150, - AArch64_UMOVvi16 = 4151, - AArch64_UMOVvi32 = 4152, - AArch64_UMOVvi64 = 4153, - AArch64_UMOVvi8 = 4154, - AArch64_UMSUBLrrr = 4155, - AArch64_UMULH_ZPmZ_B = 4156, - AArch64_UMULH_ZPmZ_D = 4157, - AArch64_UMULH_ZPmZ_H = 4158, - AArch64_UMULH_ZPmZ_S = 4159, - AArch64_UMULHrr = 4160, - AArch64_UMULLv16i8_v8i16 = 4161, - AArch64_UMULLv2i32_indexed = 4162, - AArch64_UMULLv2i32_v2i64 = 4163, - AArch64_UMULLv4i16_indexed = 4164, - AArch64_UMULLv4i16_v4i32 = 4165, - AArch64_UMULLv4i32_indexed = 4166, - AArch64_UMULLv4i32_v2i64 = 4167, - AArch64_UMULLv8i16_indexed = 4168, - AArch64_UMULLv8i16_v4i32 = 4169, - AArch64_UMULLv8i8_v8i16 = 4170, - AArch64_UQADD_ZI_B = 4171, - AArch64_UQADD_ZI_D = 4172, - AArch64_UQADD_ZI_H = 4173, - AArch64_UQADD_ZI_S = 4174, - AArch64_UQADD_ZZZ_B = 4175, - AArch64_UQADD_ZZZ_D = 4176, - AArch64_UQADD_ZZZ_H = 4177, - AArch64_UQADD_ZZZ_S = 4178, - AArch64_UQADDv16i8 = 4179, - AArch64_UQADDv1i16 = 4180, - AArch64_UQADDv1i32 = 4181, - AArch64_UQADDv1i64 = 4182, - AArch64_UQADDv1i8 = 4183, - AArch64_UQADDv2i32 = 4184, - AArch64_UQADDv2i64 = 4185, - AArch64_UQADDv4i16 = 4186, - AArch64_UQADDv4i32 = 4187, - AArch64_UQADDv8i16 = 4188, - AArch64_UQADDv8i8 = 4189, - AArch64_UQDECB_WPiI = 4190, - AArch64_UQDECB_XPiI = 4191, - AArch64_UQDECD_WPiI = 4192, - AArch64_UQDECD_XPiI = 4193, - AArch64_UQDECD_ZPiI = 4194, - AArch64_UQDECH_WPiI = 4195, - AArch64_UQDECH_XPiI = 4196, - AArch64_UQDECH_ZPiI = 4197, - AArch64_UQDECP_WP_B = 4198, - AArch64_UQDECP_WP_D = 4199, - AArch64_UQDECP_WP_H = 4200, - AArch64_UQDECP_WP_S = 4201, - AArch64_UQDECP_XP_B = 4202, - AArch64_UQDECP_XP_D = 4203, - AArch64_UQDECP_XP_H = 4204, - AArch64_UQDECP_XP_S = 4205, - AArch64_UQDECP_ZP_D = 4206, - AArch64_UQDECP_ZP_H = 4207, - AArch64_UQDECP_ZP_S = 4208, - AArch64_UQDECW_WPiI = 4209, - AArch64_UQDECW_XPiI = 4210, - AArch64_UQDECW_ZPiI = 4211, - AArch64_UQINCB_WPiI = 4212, - AArch64_UQINCB_XPiI = 4213, - AArch64_UQINCD_WPiI = 4214, - AArch64_UQINCD_XPiI = 4215, - AArch64_UQINCD_ZPiI = 4216, - AArch64_UQINCH_WPiI = 4217, - AArch64_UQINCH_XPiI = 4218, - AArch64_UQINCH_ZPiI = 4219, - AArch64_UQINCP_WP_B = 4220, - AArch64_UQINCP_WP_D = 4221, - AArch64_UQINCP_WP_H = 4222, - AArch64_UQINCP_WP_S = 4223, - AArch64_UQINCP_XP_B = 4224, - AArch64_UQINCP_XP_D = 4225, - AArch64_UQINCP_XP_H = 4226, - AArch64_UQINCP_XP_S = 4227, - AArch64_UQINCP_ZP_D = 4228, - AArch64_UQINCP_ZP_H = 4229, - AArch64_UQINCP_ZP_S = 4230, - AArch64_UQINCW_WPiI = 4231, - AArch64_UQINCW_XPiI = 4232, - AArch64_UQINCW_ZPiI = 4233, - AArch64_UQRSHLv16i8 = 4234, - AArch64_UQRSHLv1i16 = 4235, - AArch64_UQRSHLv1i32 = 4236, - AArch64_UQRSHLv1i64 = 4237, - AArch64_UQRSHLv1i8 = 4238, - AArch64_UQRSHLv2i32 = 4239, - AArch64_UQRSHLv2i64 = 4240, - AArch64_UQRSHLv4i16 = 4241, - AArch64_UQRSHLv4i32 = 4242, - AArch64_UQRSHLv8i16 = 4243, - AArch64_UQRSHLv8i8 = 4244, - AArch64_UQRSHRNb = 4245, - AArch64_UQRSHRNh = 4246, - AArch64_UQRSHRNs = 4247, - AArch64_UQRSHRNv16i8_shift = 4248, - AArch64_UQRSHRNv2i32_shift = 4249, - AArch64_UQRSHRNv4i16_shift = 4250, - AArch64_UQRSHRNv4i32_shift = 4251, - AArch64_UQRSHRNv8i16_shift = 4252, - AArch64_UQRSHRNv8i8_shift = 4253, - AArch64_UQSHLb = 4254, - AArch64_UQSHLd = 4255, - AArch64_UQSHLh = 4256, - AArch64_UQSHLs = 4257, - AArch64_UQSHLv16i8 = 4258, - AArch64_UQSHLv16i8_shift = 4259, - AArch64_UQSHLv1i16 = 4260, - AArch64_UQSHLv1i32 = 4261, - AArch64_UQSHLv1i64 = 4262, - AArch64_UQSHLv1i8 = 4263, - AArch64_UQSHLv2i32 = 4264, - AArch64_UQSHLv2i32_shift = 4265, - AArch64_UQSHLv2i64 = 4266, - AArch64_UQSHLv2i64_shift = 4267, - AArch64_UQSHLv4i16 = 4268, - AArch64_UQSHLv4i16_shift = 4269, - AArch64_UQSHLv4i32 = 4270, - AArch64_UQSHLv4i32_shift = 4271, - AArch64_UQSHLv8i16 = 4272, - AArch64_UQSHLv8i16_shift = 4273, - AArch64_UQSHLv8i8 = 4274, - AArch64_UQSHLv8i8_shift = 4275, - AArch64_UQSHRNb = 4276, - AArch64_UQSHRNh = 4277, - AArch64_UQSHRNs = 4278, - AArch64_UQSHRNv16i8_shift = 4279, - AArch64_UQSHRNv2i32_shift = 4280, - AArch64_UQSHRNv4i16_shift = 4281, - AArch64_UQSHRNv4i32_shift = 4282, - AArch64_UQSHRNv8i16_shift = 4283, - AArch64_UQSHRNv8i8_shift = 4284, - AArch64_UQSUB_ZI_B = 4285, - AArch64_UQSUB_ZI_D = 4286, - AArch64_UQSUB_ZI_H = 4287, - AArch64_UQSUB_ZI_S = 4288, - AArch64_UQSUB_ZZZ_B = 4289, - AArch64_UQSUB_ZZZ_D = 4290, - AArch64_UQSUB_ZZZ_H = 4291, - AArch64_UQSUB_ZZZ_S = 4292, - AArch64_UQSUBv16i8 = 4293, - AArch64_UQSUBv1i16 = 4294, - AArch64_UQSUBv1i32 = 4295, - AArch64_UQSUBv1i64 = 4296, - AArch64_UQSUBv1i8 = 4297, - AArch64_UQSUBv2i32 = 4298, - AArch64_UQSUBv2i64 = 4299, - AArch64_UQSUBv4i16 = 4300, - AArch64_UQSUBv4i32 = 4301, - AArch64_UQSUBv8i16 = 4302, - AArch64_UQSUBv8i8 = 4303, - AArch64_UQXTNv16i8 = 4304, - AArch64_UQXTNv1i16 = 4305, - AArch64_UQXTNv1i32 = 4306, - AArch64_UQXTNv1i8 = 4307, - AArch64_UQXTNv2i32 = 4308, - AArch64_UQXTNv4i16 = 4309, - AArch64_UQXTNv4i32 = 4310, - AArch64_UQXTNv8i16 = 4311, - AArch64_UQXTNv8i8 = 4312, - AArch64_URECPEv2i32 = 4313, - AArch64_URECPEv4i32 = 4314, - AArch64_URHADDv16i8 = 4315, - AArch64_URHADDv2i32 = 4316, - AArch64_URHADDv4i16 = 4317, - AArch64_URHADDv4i32 = 4318, - AArch64_URHADDv8i16 = 4319, - AArch64_URHADDv8i8 = 4320, - AArch64_URSHLv16i8 = 4321, - AArch64_URSHLv1i64 = 4322, - AArch64_URSHLv2i32 = 4323, - AArch64_URSHLv2i64 = 4324, - AArch64_URSHLv4i16 = 4325, - AArch64_URSHLv4i32 = 4326, - AArch64_URSHLv8i16 = 4327, - AArch64_URSHLv8i8 = 4328, - AArch64_URSHRd = 4329, - AArch64_URSHRv16i8_shift = 4330, - AArch64_URSHRv2i32_shift = 4331, - AArch64_URSHRv2i64_shift = 4332, - AArch64_URSHRv4i16_shift = 4333, - AArch64_URSHRv4i32_shift = 4334, - AArch64_URSHRv8i16_shift = 4335, - AArch64_URSHRv8i8_shift = 4336, - AArch64_URSQRTEv2i32 = 4337, - AArch64_URSQRTEv4i32 = 4338, - AArch64_URSRAd = 4339, - AArch64_URSRAv16i8_shift = 4340, - AArch64_URSRAv2i32_shift = 4341, - AArch64_URSRAv2i64_shift = 4342, - AArch64_URSRAv4i16_shift = 4343, - AArch64_URSRAv4i32_shift = 4344, - AArch64_URSRAv8i16_shift = 4345, - AArch64_URSRAv8i8_shift = 4346, - AArch64_USHLLv16i8_shift = 4347, - AArch64_USHLLv2i32_shift = 4348, - AArch64_USHLLv4i16_shift = 4349, - AArch64_USHLLv4i32_shift = 4350, - AArch64_USHLLv8i16_shift = 4351, - AArch64_USHLLv8i8_shift = 4352, - AArch64_USHLv16i8 = 4353, - AArch64_USHLv1i64 = 4354, - AArch64_USHLv2i32 = 4355, - AArch64_USHLv2i64 = 4356, - AArch64_USHLv4i16 = 4357, - AArch64_USHLv4i32 = 4358, - AArch64_USHLv8i16 = 4359, - AArch64_USHLv8i8 = 4360, - AArch64_USHRd = 4361, - AArch64_USHRv16i8_shift = 4362, - AArch64_USHRv2i32_shift = 4363, - AArch64_USHRv2i64_shift = 4364, - AArch64_USHRv4i16_shift = 4365, - AArch64_USHRv4i32_shift = 4366, - AArch64_USHRv8i16_shift = 4367, - AArch64_USHRv8i8_shift = 4368, - AArch64_USQADDv16i8 = 4369, - AArch64_USQADDv1i16 = 4370, - AArch64_USQADDv1i32 = 4371, - AArch64_USQADDv1i64 = 4372, - AArch64_USQADDv1i8 = 4373, - AArch64_USQADDv2i32 = 4374, - AArch64_USQADDv2i64 = 4375, - AArch64_USQADDv4i16 = 4376, - AArch64_USQADDv4i32 = 4377, - AArch64_USQADDv8i16 = 4378, - AArch64_USQADDv8i8 = 4379, - AArch64_USRAd = 4380, - AArch64_USRAv16i8_shift = 4381, - AArch64_USRAv2i32_shift = 4382, - AArch64_USRAv2i64_shift = 4383, - AArch64_USRAv4i16_shift = 4384, - AArch64_USRAv4i32_shift = 4385, - AArch64_USRAv8i16_shift = 4386, - AArch64_USRAv8i8_shift = 4387, - AArch64_USUBLv16i8_v8i16 = 4388, - AArch64_USUBLv2i32_v2i64 = 4389, - AArch64_USUBLv4i16_v4i32 = 4390, - AArch64_USUBLv4i32_v2i64 = 4391, - AArch64_USUBLv8i16_v4i32 = 4392, - AArch64_USUBLv8i8_v8i16 = 4393, - AArch64_USUBWv16i8_v8i16 = 4394, - AArch64_USUBWv2i32_v2i64 = 4395, - AArch64_USUBWv4i16_v4i32 = 4396, - AArch64_USUBWv4i32_v2i64 = 4397, - AArch64_USUBWv8i16_v4i32 = 4398, - AArch64_USUBWv8i8_v8i16 = 4399, - AArch64_UUNPKHI_ZZ_D = 4400, - AArch64_UUNPKHI_ZZ_H = 4401, - AArch64_UUNPKHI_ZZ_S = 4402, - AArch64_UUNPKLO_ZZ_D = 4403, - AArch64_UUNPKLO_ZZ_H = 4404, - AArch64_UUNPKLO_ZZ_S = 4405, - AArch64_UXTB_ZPmZ_D = 4406, - AArch64_UXTB_ZPmZ_H = 4407, - AArch64_UXTB_ZPmZ_S = 4408, - AArch64_UXTH_ZPmZ_D = 4409, - AArch64_UXTH_ZPmZ_S = 4410, - AArch64_UXTW_ZPmZ_D = 4411, - AArch64_UZP1_PPP_B = 4412, - AArch64_UZP1_PPP_D = 4413, - AArch64_UZP1_PPP_H = 4414, - AArch64_UZP1_PPP_S = 4415, - AArch64_UZP1_ZZZ_B = 4416, - AArch64_UZP1_ZZZ_D = 4417, - AArch64_UZP1_ZZZ_H = 4418, - AArch64_UZP1_ZZZ_S = 4419, - AArch64_UZP1v16i8 = 4420, - AArch64_UZP1v2i32 = 4421, - AArch64_UZP1v2i64 = 4422, - AArch64_UZP1v4i16 = 4423, - AArch64_UZP1v4i32 = 4424, - AArch64_UZP1v8i16 = 4425, - AArch64_UZP1v8i8 = 4426, - AArch64_UZP2_PPP_B = 4427, - AArch64_UZP2_PPP_D = 4428, - AArch64_UZP2_PPP_H = 4429, - AArch64_UZP2_PPP_S = 4430, - AArch64_UZP2_ZZZ_B = 4431, - AArch64_UZP2_ZZZ_D = 4432, - AArch64_UZP2_ZZZ_H = 4433, - AArch64_UZP2_ZZZ_S = 4434, - AArch64_UZP2v16i8 = 4435, - AArch64_UZP2v2i32 = 4436, - AArch64_UZP2v2i64 = 4437, - AArch64_UZP2v4i16 = 4438, - AArch64_UZP2v4i32 = 4439, - AArch64_UZP2v8i16 = 4440, - AArch64_UZP2v8i8 = 4441, - AArch64_WHILELE_PWW_B = 4442, - AArch64_WHILELE_PWW_D = 4443, - AArch64_WHILELE_PWW_H = 4444, - AArch64_WHILELE_PWW_S = 4445, - AArch64_WHILELE_PXX_B = 4446, - AArch64_WHILELE_PXX_D = 4447, - AArch64_WHILELE_PXX_H = 4448, - AArch64_WHILELE_PXX_S = 4449, - AArch64_WHILELO_PWW_B = 4450, - AArch64_WHILELO_PWW_D = 4451, - AArch64_WHILELO_PWW_H = 4452, - AArch64_WHILELO_PWW_S = 4453, - AArch64_WHILELO_PXX_B = 4454, - AArch64_WHILELO_PXX_D = 4455, - AArch64_WHILELO_PXX_H = 4456, - AArch64_WHILELO_PXX_S = 4457, - AArch64_WHILELS_PWW_B = 4458, - AArch64_WHILELS_PWW_D = 4459, - AArch64_WHILELS_PWW_H = 4460, - AArch64_WHILELS_PWW_S = 4461, - AArch64_WHILELS_PXX_B = 4462, - AArch64_WHILELS_PXX_D = 4463, - AArch64_WHILELS_PXX_H = 4464, - AArch64_WHILELS_PXX_S = 4465, - AArch64_WHILELT_PWW_B = 4466, - AArch64_WHILELT_PWW_D = 4467, - AArch64_WHILELT_PWW_H = 4468, - AArch64_WHILELT_PWW_S = 4469, - AArch64_WHILELT_PXX_B = 4470, - AArch64_WHILELT_PXX_D = 4471, - AArch64_WHILELT_PXX_H = 4472, - AArch64_WHILELT_PXX_S = 4473, - AArch64_WRFFR = 4474, - AArch64_XAR = 4475, - AArch64_XPACD = 4476, - AArch64_XPACI = 4477, - AArch64_XPACLRI = 4478, - AArch64_XTNv16i8 = 4479, - AArch64_XTNv2i32 = 4480, - AArch64_XTNv4i16 = 4481, - AArch64_XTNv4i32 = 4482, - AArch64_XTNv8i16 = 4483, - AArch64_XTNv8i8 = 4484, - AArch64_ZIP1_PPP_B = 4485, - AArch64_ZIP1_PPP_D = 4486, - AArch64_ZIP1_PPP_H = 4487, - AArch64_ZIP1_PPP_S = 4488, - AArch64_ZIP1_ZZZ_B = 4489, - AArch64_ZIP1_ZZZ_D = 4490, - AArch64_ZIP1_ZZZ_H = 4491, - AArch64_ZIP1_ZZZ_S = 4492, - AArch64_ZIP1v16i8 = 4493, - AArch64_ZIP1v2i32 = 4494, - AArch64_ZIP1v2i64 = 4495, - AArch64_ZIP1v4i16 = 4496, - AArch64_ZIP1v4i32 = 4497, - AArch64_ZIP1v8i16 = 4498, - AArch64_ZIP1v8i8 = 4499, - AArch64_ZIP2_PPP_B = 4500, - AArch64_ZIP2_PPP_D = 4501, - AArch64_ZIP2_PPP_H = 4502, - AArch64_ZIP2_PPP_S = 4503, - AArch64_ZIP2_ZZZ_B = 4504, - AArch64_ZIP2_ZZZ_D = 4505, - AArch64_ZIP2_ZZZ_H = 4506, - AArch64_ZIP2_ZZZ_S = 4507, - AArch64_ZIP2v16i8 = 4508, - AArch64_ZIP2v2i32 = 4509, - AArch64_ZIP2v2i64 = 4510, - AArch64_ZIP2v4i16 = 4511, - AArch64_ZIP2v4i32 = 4512, - AArch64_ZIP2v8i16 = 4513, - AArch64_ZIP2v8i8 = 4514, - AArch64_anonymous_1349 = 4515, - AArch64_INSTRUCTION_LIST_END = 4516 + AArch64_PHI = 0, + AArch64_INLINEASM = 1, + AArch64_CFI_INSTRUCTION = 2, + AArch64_EH_LABEL = 3, + AArch64_GC_LABEL = 4, + AArch64_ANNOTATION_LABEL = 5, + AArch64_KILL = 6, + AArch64_EXTRACT_SUBREG = 7, + AArch64_INSERT_SUBREG = 8, + AArch64_IMPLICIT_DEF = 9, + AArch64_SUBREG_TO_REG = 10, + AArch64_COPY_TO_REGCLASS = 11, + AArch64_DBG_VALUE = 12, + AArch64_DBG_LABEL = 13, + AArch64_REG_SEQUENCE = 14, + AArch64_COPY = 15, + AArch64_BUNDLE = 16, + AArch64_LIFETIME_START = 17, + AArch64_LIFETIME_END = 18, + AArch64_STACKMAP = 19, + AArch64_FENTRY_CALL = 20, + AArch64_PATCHPOINT = 21, + AArch64_LOAD_STACK_GUARD = 22, + AArch64_STATEPOINT = 23, + AArch64_LOCAL_ESCAPE = 24, + AArch64_FAULTING_OP = 25, + AArch64_PATCHABLE_OP = 26, + AArch64_PATCHABLE_FUNCTION_ENTER = 27, + AArch64_PATCHABLE_RET = 28, + AArch64_PATCHABLE_FUNCTION_EXIT = 29, + AArch64_PATCHABLE_TAIL_CALL = 30, + AArch64_PATCHABLE_EVENT_CALL = 31, + AArch64_PATCHABLE_TYPED_EVENT_CALL = 32, + AArch64_ICALL_BRANCH_FUNNEL = 33, + AArch64_G_ADD = 34, + AArch64_G_SUB = 35, + AArch64_G_MUL = 36, + AArch64_G_SDIV = 37, + AArch64_G_UDIV = 38, + AArch64_G_SREM = 39, + AArch64_G_UREM = 40, + AArch64_G_AND = 41, + AArch64_G_OR = 42, + AArch64_G_XOR = 43, + AArch64_G_IMPLICIT_DEF = 44, + AArch64_G_PHI = 45, + AArch64_G_FRAME_INDEX = 46, + AArch64_G_GLOBAL_VALUE = 47, + AArch64_G_EXTRACT = 48, + AArch64_G_UNMERGE_VALUES = 49, + AArch64_G_INSERT = 50, + AArch64_G_MERGE_VALUES = 51, + AArch64_G_PTRTOINT = 52, + AArch64_G_INTTOPTR = 53, + AArch64_G_BITCAST = 54, + AArch64_G_LOAD = 55, + AArch64_G_SEXTLOAD = 56, + AArch64_G_ZEXTLOAD = 57, + AArch64_G_STORE = 58, + AArch64_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, + AArch64_G_ATOMIC_CMPXCHG = 60, + AArch64_G_ATOMICRMW_XCHG = 61, + AArch64_G_ATOMICRMW_ADD = 62, + AArch64_G_ATOMICRMW_SUB = 63, + AArch64_G_ATOMICRMW_AND = 64, + AArch64_G_ATOMICRMW_NAND = 65, + AArch64_G_ATOMICRMW_OR = 66, + AArch64_G_ATOMICRMW_XOR = 67, + AArch64_G_ATOMICRMW_MAX = 68, + AArch64_G_ATOMICRMW_MIN = 69, + AArch64_G_ATOMICRMW_UMAX = 70, + AArch64_G_ATOMICRMW_UMIN = 71, + AArch64_G_BRCOND = 72, + AArch64_G_BRINDIRECT = 73, + AArch64_G_INTRINSIC = 74, + AArch64_G_INTRINSIC_W_SIDE_EFFECTS = 75, + AArch64_G_ANYEXT = 76, + AArch64_G_TRUNC = 77, + AArch64_G_CONSTANT = 78, + AArch64_G_FCONSTANT = 79, + AArch64_G_VASTART = 80, + AArch64_G_VAARG = 81, + AArch64_G_SEXT = 82, + AArch64_G_ZEXT = 83, + AArch64_G_SHL = 84, + AArch64_G_LSHR = 85, + AArch64_G_ASHR = 86, + AArch64_G_ICMP = 87, + AArch64_G_FCMP = 88, + AArch64_G_SELECT = 89, + AArch64_G_UADDE = 90, + AArch64_G_USUBE = 91, + AArch64_G_SADDO = 92, + AArch64_G_SSUBO = 93, + AArch64_G_UMULO = 94, + AArch64_G_SMULO = 95, + AArch64_G_UMULH = 96, + AArch64_G_SMULH = 97, + AArch64_G_FADD = 98, + AArch64_G_FSUB = 99, + AArch64_G_FMUL = 100, + AArch64_G_FMA = 101, + AArch64_G_FDIV = 102, + AArch64_G_FREM = 103, + AArch64_G_FPOW = 104, + AArch64_G_FEXP = 105, + AArch64_G_FEXP2 = 106, + AArch64_G_FLOG = 107, + AArch64_G_FLOG2 = 108, + AArch64_G_FNEG = 109, + AArch64_G_FPEXT = 110, + AArch64_G_FPTRUNC = 111, + AArch64_G_FPTOSI = 112, + AArch64_G_FPTOUI = 113, + AArch64_G_SITOFP = 114, + AArch64_G_UITOFP = 115, + AArch64_G_FABS = 116, + AArch64_G_GEP = 117, + AArch64_G_PTR_MASK = 118, + AArch64_G_BR = 119, + AArch64_G_INSERT_VECTOR_ELT = 120, + AArch64_G_EXTRACT_VECTOR_ELT = 121, + AArch64_G_SHUFFLE_VECTOR = 122, + AArch64_G_BSWAP = 123, + AArch64_G_ADDRSPACE_CAST = 124, + AArch64_G_BLOCK_ADDR = 125, + AArch64_ABS_ZPmZ_B = 126, + AArch64_ABS_ZPmZ_D = 127, + AArch64_ABS_ZPmZ_H = 128, + AArch64_ABS_ZPmZ_S = 129, + AArch64_ABSv16i8 = 130, + AArch64_ABSv1i64 = 131, + AArch64_ABSv2i32 = 132, + AArch64_ABSv2i64 = 133, + AArch64_ABSv4i16 = 134, + AArch64_ABSv4i32 = 135, + AArch64_ABSv8i16 = 136, + AArch64_ABSv8i8 = 137, + AArch64_ADCSWr = 138, + AArch64_ADCSXr = 139, + AArch64_ADCWr = 140, + AArch64_ADCXr = 141, + AArch64_ADDHNv2i64_v2i32 = 142, + AArch64_ADDHNv2i64_v4i32 = 143, + AArch64_ADDHNv4i32_v4i16 = 144, + AArch64_ADDHNv4i32_v8i16 = 145, + AArch64_ADDHNv8i16_v16i8 = 146, + AArch64_ADDHNv8i16_v8i8 = 147, + AArch64_ADDPL_XXI = 148, + AArch64_ADDPv16i8 = 149, + AArch64_ADDPv2i32 = 150, + AArch64_ADDPv2i64 = 151, + AArch64_ADDPv2i64p = 152, + AArch64_ADDPv4i16 = 153, + AArch64_ADDPv4i32 = 154, + AArch64_ADDPv8i16 = 155, + AArch64_ADDPv8i8 = 156, + AArch64_ADDSWri = 157, + AArch64_ADDSWrr = 158, + AArch64_ADDSWrs = 159, + AArch64_ADDSWrx = 160, + AArch64_ADDSXri = 161, + AArch64_ADDSXrr = 162, + AArch64_ADDSXrs = 163, + AArch64_ADDSXrx = 164, + AArch64_ADDSXrx64 = 165, + AArch64_ADDVL_XXI = 166, + AArch64_ADDVv16i8v = 167, + AArch64_ADDVv4i16v = 168, + AArch64_ADDVv4i32v = 169, + AArch64_ADDVv8i16v = 170, + AArch64_ADDVv8i8v = 171, + AArch64_ADDWri = 172, + AArch64_ADDWrr = 173, + AArch64_ADDWrs = 174, + AArch64_ADDWrx = 175, + AArch64_ADDXri = 176, + AArch64_ADDXrr = 177, + AArch64_ADDXrs = 178, + AArch64_ADDXrx = 179, + AArch64_ADDXrx64 = 180, + AArch64_ADD_ZI_B = 181, + AArch64_ADD_ZI_D = 182, + AArch64_ADD_ZI_H = 183, + AArch64_ADD_ZI_S = 184, + AArch64_ADD_ZPmZ_B = 185, + AArch64_ADD_ZPmZ_D = 186, + AArch64_ADD_ZPmZ_H = 187, + AArch64_ADD_ZPmZ_S = 188, + AArch64_ADD_ZZZ_B = 189, + AArch64_ADD_ZZZ_D = 190, + AArch64_ADD_ZZZ_H = 191, + AArch64_ADD_ZZZ_S = 192, + AArch64_ADDlowTLS = 193, + AArch64_ADDv16i8 = 194, + AArch64_ADDv1i64 = 195, + AArch64_ADDv2i32 = 196, + AArch64_ADDv2i64 = 197, + AArch64_ADDv4i16 = 198, + AArch64_ADDv4i32 = 199, + AArch64_ADDv8i16 = 200, + AArch64_ADDv8i8 = 201, + AArch64_ADJCALLSTACKDOWN = 202, + AArch64_ADJCALLSTACKUP = 203, + AArch64_ADR = 204, + AArch64_ADRP = 205, + AArch64_ADR_LSL_ZZZ_D_0 = 206, + AArch64_ADR_LSL_ZZZ_D_1 = 207, + AArch64_ADR_LSL_ZZZ_D_2 = 208, + AArch64_ADR_LSL_ZZZ_D_3 = 209, + AArch64_ADR_LSL_ZZZ_S_0 = 210, + AArch64_ADR_LSL_ZZZ_S_1 = 211, + AArch64_ADR_LSL_ZZZ_S_2 = 212, + AArch64_ADR_LSL_ZZZ_S_3 = 213, + AArch64_ADR_SXTW_ZZZ_D_0 = 214, + AArch64_ADR_SXTW_ZZZ_D_1 = 215, + AArch64_ADR_SXTW_ZZZ_D_2 = 216, + AArch64_ADR_SXTW_ZZZ_D_3 = 217, + AArch64_ADR_UXTW_ZZZ_D_0 = 218, + AArch64_ADR_UXTW_ZZZ_D_1 = 219, + AArch64_ADR_UXTW_ZZZ_D_2 = 220, + AArch64_ADR_UXTW_ZZZ_D_3 = 221, + AArch64_AESDrr = 222, + AArch64_AESErr = 223, + AArch64_AESIMCrr = 224, + AArch64_AESIMCrrTied = 225, + AArch64_AESMCrr = 226, + AArch64_AESMCrrTied = 227, + AArch64_ANDSWri = 228, + AArch64_ANDSWrr = 229, + AArch64_ANDSWrs = 230, + AArch64_ANDSXri = 231, + AArch64_ANDSXrr = 232, + AArch64_ANDSXrs = 233, + AArch64_ANDS_PPzPP = 234, + AArch64_ANDV_VPZ_B = 235, + AArch64_ANDV_VPZ_D = 236, + AArch64_ANDV_VPZ_H = 237, + AArch64_ANDV_VPZ_S = 238, + AArch64_ANDWri = 239, + AArch64_ANDWrr = 240, + AArch64_ANDWrs = 241, + AArch64_ANDXri = 242, + AArch64_ANDXrr = 243, + AArch64_ANDXrs = 244, + AArch64_AND_PPzPP = 245, + AArch64_AND_ZI = 246, + AArch64_AND_ZPmZ_B = 247, + AArch64_AND_ZPmZ_D = 248, + AArch64_AND_ZPmZ_H = 249, + AArch64_AND_ZPmZ_S = 250, + AArch64_AND_ZZZ = 251, + AArch64_ANDv16i8 = 252, + AArch64_ANDv8i8 = 253, + AArch64_ASRD_ZPmI_B = 254, + AArch64_ASRD_ZPmI_D = 255, + AArch64_ASRD_ZPmI_H = 256, + AArch64_ASRD_ZPmI_S = 257, + AArch64_ASRR_ZPmZ_B = 258, + AArch64_ASRR_ZPmZ_D = 259, + AArch64_ASRR_ZPmZ_H = 260, + AArch64_ASRR_ZPmZ_S = 261, + AArch64_ASRVWr = 262, + AArch64_ASRVXr = 263, + AArch64_ASR_WIDE_ZPmZ_B = 264, + AArch64_ASR_WIDE_ZPmZ_H = 265, + AArch64_ASR_WIDE_ZPmZ_S = 266, + AArch64_ASR_WIDE_ZZZ_B = 267, + AArch64_ASR_WIDE_ZZZ_H = 268, + AArch64_ASR_WIDE_ZZZ_S = 269, + AArch64_ASR_ZPmI_B = 270, + AArch64_ASR_ZPmI_D = 271, + AArch64_ASR_ZPmI_H = 272, + AArch64_ASR_ZPmI_S = 273, + AArch64_ASR_ZPmZ_B = 274, + AArch64_ASR_ZPmZ_D = 275, + AArch64_ASR_ZPmZ_H = 276, + AArch64_ASR_ZPmZ_S = 277, + AArch64_ASR_ZZI_B = 278, + AArch64_ASR_ZZI_D = 279, + AArch64_ASR_ZZI_H = 280, + AArch64_ASR_ZZI_S = 281, + AArch64_AUTDA = 282, + AArch64_AUTDB = 283, + AArch64_AUTDZA = 284, + AArch64_AUTDZB = 285, + AArch64_AUTIA = 286, + AArch64_AUTIA1716 = 287, + AArch64_AUTIASP = 288, + AArch64_AUTIAZ = 289, + AArch64_AUTIB = 290, + AArch64_AUTIB1716 = 291, + AArch64_AUTIBSP = 292, + AArch64_AUTIBZ = 293, + AArch64_AUTIZA = 294, + AArch64_AUTIZB = 295, + AArch64_B = 296, + AArch64_BCAX = 297, + AArch64_BFMWri = 298, + AArch64_BFMXri = 299, + AArch64_BICSWrr = 300, + AArch64_BICSWrs = 301, + AArch64_BICSXrr = 302, + AArch64_BICSXrs = 303, + AArch64_BICS_PPzPP = 304, + AArch64_BICWrr = 305, + AArch64_BICWrs = 306, + AArch64_BICXrr = 307, + AArch64_BICXrs = 308, + AArch64_BIC_PPzPP = 309, + AArch64_BIC_ZPmZ_B = 310, + AArch64_BIC_ZPmZ_D = 311, + AArch64_BIC_ZPmZ_H = 312, + AArch64_BIC_ZPmZ_S = 313, + AArch64_BIC_ZZZ = 314, + AArch64_BICv16i8 = 315, + AArch64_BICv2i32 = 316, + AArch64_BICv4i16 = 317, + AArch64_BICv4i32 = 318, + AArch64_BICv8i16 = 319, + AArch64_BICv8i8 = 320, + AArch64_BIFv16i8 = 321, + AArch64_BIFv8i8 = 322, + AArch64_BITv16i8 = 323, + AArch64_BITv8i8 = 324, + AArch64_BL = 325, + AArch64_BLR = 326, + AArch64_BLRAA = 327, + AArch64_BLRAAZ = 328, + AArch64_BLRAB = 329, + AArch64_BLRABZ = 330, + AArch64_BR = 331, + AArch64_BRAA = 332, + AArch64_BRAAZ = 333, + AArch64_BRAB = 334, + AArch64_BRABZ = 335, + AArch64_BRK = 336, + AArch64_BRKAS_PPzP = 337, + AArch64_BRKA_PPmP = 338, + AArch64_BRKA_PPzP = 339, + AArch64_BRKBS_PPzP = 340, + AArch64_BRKB_PPmP = 341, + AArch64_BRKB_PPzP = 342, + AArch64_BRKNS_PPzP = 343, + AArch64_BRKN_PPzP = 344, + AArch64_BRKPAS_PPzPP = 345, + AArch64_BRKPA_PPzPP = 346, + AArch64_BRKPBS_PPzPP = 347, + AArch64_BRKPB_PPzPP = 348, + AArch64_BSLv16i8 = 349, + AArch64_BSLv8i8 = 350, + AArch64_Bcc = 351, + AArch64_CASAB = 352, + AArch64_CASAH = 353, + AArch64_CASALB = 354, + AArch64_CASALH = 355, + AArch64_CASALW = 356, + AArch64_CASALX = 357, + AArch64_CASAW = 358, + AArch64_CASAX = 359, + AArch64_CASB = 360, + AArch64_CASH = 361, + AArch64_CASLB = 362, + AArch64_CASLH = 363, + AArch64_CASLW = 364, + AArch64_CASLX = 365, + AArch64_CASPALW = 366, + AArch64_CASPALX = 367, + AArch64_CASPAW = 368, + AArch64_CASPAX = 369, + AArch64_CASPLW = 370, + AArch64_CASPLX = 371, + AArch64_CASPW = 372, + AArch64_CASPX = 373, + AArch64_CASW = 374, + AArch64_CASX = 375, + AArch64_CBNZW = 376, + AArch64_CBNZX = 377, + AArch64_CBZW = 378, + AArch64_CBZX = 379, + AArch64_CCMNWi = 380, + AArch64_CCMNWr = 381, + AArch64_CCMNXi = 382, + AArch64_CCMNXr = 383, + AArch64_CCMPWi = 384, + AArch64_CCMPWr = 385, + AArch64_CCMPXi = 386, + AArch64_CCMPXr = 387, + AArch64_CFINV = 388, + AArch64_CLASTA_RPZ_B = 389, + AArch64_CLASTA_RPZ_D = 390, + AArch64_CLASTA_RPZ_H = 391, + AArch64_CLASTA_RPZ_S = 392, + AArch64_CLASTA_VPZ_B = 393, + AArch64_CLASTA_VPZ_D = 394, + AArch64_CLASTA_VPZ_H = 395, + AArch64_CLASTA_VPZ_S = 396, + AArch64_CLASTA_ZPZ_B = 397, + AArch64_CLASTA_ZPZ_D = 398, + AArch64_CLASTA_ZPZ_H = 399, + AArch64_CLASTA_ZPZ_S = 400, + AArch64_CLASTB_RPZ_B = 401, + AArch64_CLASTB_RPZ_D = 402, + AArch64_CLASTB_RPZ_H = 403, + AArch64_CLASTB_RPZ_S = 404, + AArch64_CLASTB_VPZ_B = 405, + AArch64_CLASTB_VPZ_D = 406, + AArch64_CLASTB_VPZ_H = 407, + AArch64_CLASTB_VPZ_S = 408, + AArch64_CLASTB_ZPZ_B = 409, + AArch64_CLASTB_ZPZ_D = 410, + AArch64_CLASTB_ZPZ_H = 411, + AArch64_CLASTB_ZPZ_S = 412, + AArch64_CLREX = 413, + AArch64_CLSWr = 414, + AArch64_CLSXr = 415, + AArch64_CLS_ZPmZ_B = 416, + AArch64_CLS_ZPmZ_D = 417, + AArch64_CLS_ZPmZ_H = 418, + AArch64_CLS_ZPmZ_S = 419, + AArch64_CLSv16i8 = 420, + AArch64_CLSv2i32 = 421, + AArch64_CLSv4i16 = 422, + AArch64_CLSv4i32 = 423, + AArch64_CLSv8i16 = 424, + AArch64_CLSv8i8 = 425, + AArch64_CLZWr = 426, + AArch64_CLZXr = 427, + AArch64_CLZ_ZPmZ_B = 428, + AArch64_CLZ_ZPmZ_D = 429, + AArch64_CLZ_ZPmZ_H = 430, + AArch64_CLZ_ZPmZ_S = 431, + AArch64_CLZv16i8 = 432, + AArch64_CLZv2i32 = 433, + AArch64_CLZv4i16 = 434, + AArch64_CLZv4i32 = 435, + AArch64_CLZv8i16 = 436, + AArch64_CLZv8i8 = 437, + AArch64_CMEQv16i8 = 438, + AArch64_CMEQv16i8rz = 439, + AArch64_CMEQv1i64 = 440, + AArch64_CMEQv1i64rz = 441, + AArch64_CMEQv2i32 = 442, + AArch64_CMEQv2i32rz = 443, + AArch64_CMEQv2i64 = 444, + AArch64_CMEQv2i64rz = 445, + AArch64_CMEQv4i16 = 446, + AArch64_CMEQv4i16rz = 447, + AArch64_CMEQv4i32 = 448, + AArch64_CMEQv4i32rz = 449, + AArch64_CMEQv8i16 = 450, + AArch64_CMEQv8i16rz = 451, + AArch64_CMEQv8i8 = 452, + AArch64_CMEQv8i8rz = 453, + AArch64_CMGEv16i8 = 454, + AArch64_CMGEv16i8rz = 455, + AArch64_CMGEv1i64 = 456, + AArch64_CMGEv1i64rz = 457, + AArch64_CMGEv2i32 = 458, + AArch64_CMGEv2i32rz = 459, + AArch64_CMGEv2i64 = 460, + AArch64_CMGEv2i64rz = 461, + AArch64_CMGEv4i16 = 462, + AArch64_CMGEv4i16rz = 463, + AArch64_CMGEv4i32 = 464, + AArch64_CMGEv4i32rz = 465, + AArch64_CMGEv8i16 = 466, + AArch64_CMGEv8i16rz = 467, + AArch64_CMGEv8i8 = 468, + AArch64_CMGEv8i8rz = 469, + AArch64_CMGTv16i8 = 470, + AArch64_CMGTv16i8rz = 471, + AArch64_CMGTv1i64 = 472, + AArch64_CMGTv1i64rz = 473, + AArch64_CMGTv2i32 = 474, + AArch64_CMGTv2i32rz = 475, + AArch64_CMGTv2i64 = 476, + AArch64_CMGTv2i64rz = 477, + AArch64_CMGTv4i16 = 478, + AArch64_CMGTv4i16rz = 479, + AArch64_CMGTv4i32 = 480, + AArch64_CMGTv4i32rz = 481, + AArch64_CMGTv8i16 = 482, + AArch64_CMGTv8i16rz = 483, + AArch64_CMGTv8i8 = 484, + AArch64_CMGTv8i8rz = 485, + AArch64_CMHIv16i8 = 486, + AArch64_CMHIv1i64 = 487, + AArch64_CMHIv2i32 = 488, + AArch64_CMHIv2i64 = 489, + AArch64_CMHIv4i16 = 490, + AArch64_CMHIv4i32 = 491, + AArch64_CMHIv8i16 = 492, + AArch64_CMHIv8i8 = 493, + AArch64_CMHSv16i8 = 494, + AArch64_CMHSv1i64 = 495, + AArch64_CMHSv2i32 = 496, + AArch64_CMHSv2i64 = 497, + AArch64_CMHSv4i16 = 498, + AArch64_CMHSv4i32 = 499, + AArch64_CMHSv8i16 = 500, + AArch64_CMHSv8i8 = 501, + AArch64_CMLEv16i8rz = 502, + AArch64_CMLEv1i64rz = 503, + AArch64_CMLEv2i32rz = 504, + AArch64_CMLEv2i64rz = 505, + AArch64_CMLEv4i16rz = 506, + AArch64_CMLEv4i32rz = 507, + AArch64_CMLEv8i16rz = 508, + AArch64_CMLEv8i8rz = 509, + AArch64_CMLTv16i8rz = 510, + AArch64_CMLTv1i64rz = 511, + AArch64_CMLTv2i32rz = 512, + AArch64_CMLTv2i64rz = 513, + AArch64_CMLTv4i16rz = 514, + AArch64_CMLTv4i32rz = 515, + AArch64_CMLTv8i16rz = 516, + AArch64_CMLTv8i8rz = 517, + AArch64_CMPEQ_PPzZI_B = 518, + AArch64_CMPEQ_PPzZI_D = 519, + AArch64_CMPEQ_PPzZI_H = 520, + AArch64_CMPEQ_PPzZI_S = 521, + AArch64_CMPEQ_PPzZZ_B = 522, + AArch64_CMPEQ_PPzZZ_D = 523, + AArch64_CMPEQ_PPzZZ_H = 524, + AArch64_CMPEQ_PPzZZ_S = 525, + AArch64_CMPEQ_WIDE_PPzZZ_B = 526, + AArch64_CMPEQ_WIDE_PPzZZ_H = 527, + AArch64_CMPEQ_WIDE_PPzZZ_S = 528, + AArch64_CMPGE_PPzZI_B = 529, + AArch64_CMPGE_PPzZI_D = 530, + AArch64_CMPGE_PPzZI_H = 531, + AArch64_CMPGE_PPzZI_S = 532, + AArch64_CMPGE_PPzZZ_B = 533, + AArch64_CMPGE_PPzZZ_D = 534, + AArch64_CMPGE_PPzZZ_H = 535, + AArch64_CMPGE_PPzZZ_S = 536, + AArch64_CMPGE_WIDE_PPzZZ_B = 537, + AArch64_CMPGE_WIDE_PPzZZ_H = 538, + AArch64_CMPGE_WIDE_PPzZZ_S = 539, + AArch64_CMPGT_PPzZI_B = 540, + AArch64_CMPGT_PPzZI_D = 541, + AArch64_CMPGT_PPzZI_H = 542, + AArch64_CMPGT_PPzZI_S = 543, + AArch64_CMPGT_PPzZZ_B = 544, + AArch64_CMPGT_PPzZZ_D = 545, + AArch64_CMPGT_PPzZZ_H = 546, + AArch64_CMPGT_PPzZZ_S = 547, + AArch64_CMPGT_WIDE_PPzZZ_B = 548, + AArch64_CMPGT_WIDE_PPzZZ_H = 549, + AArch64_CMPGT_WIDE_PPzZZ_S = 550, + AArch64_CMPHI_PPzZI_B = 551, + AArch64_CMPHI_PPzZI_D = 552, + AArch64_CMPHI_PPzZI_H = 553, + AArch64_CMPHI_PPzZI_S = 554, + AArch64_CMPHI_PPzZZ_B = 555, + AArch64_CMPHI_PPzZZ_D = 556, + AArch64_CMPHI_PPzZZ_H = 557, + AArch64_CMPHI_PPzZZ_S = 558, + AArch64_CMPHI_WIDE_PPzZZ_B = 559, + AArch64_CMPHI_WIDE_PPzZZ_H = 560, + AArch64_CMPHI_WIDE_PPzZZ_S = 561, + AArch64_CMPHS_PPzZI_B = 562, + AArch64_CMPHS_PPzZI_D = 563, + AArch64_CMPHS_PPzZI_H = 564, + AArch64_CMPHS_PPzZI_S = 565, + AArch64_CMPHS_PPzZZ_B = 566, + AArch64_CMPHS_PPzZZ_D = 567, + AArch64_CMPHS_PPzZZ_H = 568, + AArch64_CMPHS_PPzZZ_S = 569, + AArch64_CMPHS_WIDE_PPzZZ_B = 570, + AArch64_CMPHS_WIDE_PPzZZ_H = 571, + AArch64_CMPHS_WIDE_PPzZZ_S = 572, + AArch64_CMPLE_PPzZI_B = 573, + AArch64_CMPLE_PPzZI_D = 574, + AArch64_CMPLE_PPzZI_H = 575, + AArch64_CMPLE_PPzZI_S = 576, + AArch64_CMPLE_WIDE_PPzZZ_B = 577, + AArch64_CMPLE_WIDE_PPzZZ_H = 578, + AArch64_CMPLE_WIDE_PPzZZ_S = 579, + AArch64_CMPLO_PPzZI_B = 580, + AArch64_CMPLO_PPzZI_D = 581, + AArch64_CMPLO_PPzZI_H = 582, + AArch64_CMPLO_PPzZI_S = 583, + AArch64_CMPLO_WIDE_PPzZZ_B = 584, + AArch64_CMPLO_WIDE_PPzZZ_H = 585, + AArch64_CMPLO_WIDE_PPzZZ_S = 586, + AArch64_CMPLS_PPzZI_B = 587, + AArch64_CMPLS_PPzZI_D = 588, + AArch64_CMPLS_PPzZI_H = 589, + AArch64_CMPLS_PPzZI_S = 590, + AArch64_CMPLS_WIDE_PPzZZ_B = 591, + AArch64_CMPLS_WIDE_PPzZZ_H = 592, + AArch64_CMPLS_WIDE_PPzZZ_S = 593, + AArch64_CMPLT_PPzZI_B = 594, + AArch64_CMPLT_PPzZI_D = 595, + AArch64_CMPLT_PPzZI_H = 596, + AArch64_CMPLT_PPzZI_S = 597, + AArch64_CMPLT_WIDE_PPzZZ_B = 598, + AArch64_CMPLT_WIDE_PPzZZ_H = 599, + AArch64_CMPLT_WIDE_PPzZZ_S = 600, + AArch64_CMPNE_PPzZI_B = 601, + AArch64_CMPNE_PPzZI_D = 602, + AArch64_CMPNE_PPzZI_H = 603, + AArch64_CMPNE_PPzZI_S = 604, + AArch64_CMPNE_PPzZZ_B = 605, + AArch64_CMPNE_PPzZZ_D = 606, + AArch64_CMPNE_PPzZZ_H = 607, + AArch64_CMPNE_PPzZZ_S = 608, + AArch64_CMPNE_WIDE_PPzZZ_B = 609, + AArch64_CMPNE_WIDE_PPzZZ_H = 610, + AArch64_CMPNE_WIDE_PPzZZ_S = 611, + AArch64_CMP_SWAP_128 = 612, + AArch64_CMP_SWAP_16 = 613, + AArch64_CMP_SWAP_32 = 614, + AArch64_CMP_SWAP_64 = 615, + AArch64_CMP_SWAP_8 = 616, + AArch64_CMTSTv16i8 = 617, + AArch64_CMTSTv1i64 = 618, + AArch64_CMTSTv2i32 = 619, + AArch64_CMTSTv2i64 = 620, + AArch64_CMTSTv4i16 = 621, + AArch64_CMTSTv4i32 = 622, + AArch64_CMTSTv8i16 = 623, + AArch64_CMTSTv8i8 = 624, + AArch64_CNOT_ZPmZ_B = 625, + AArch64_CNOT_ZPmZ_D = 626, + AArch64_CNOT_ZPmZ_H = 627, + AArch64_CNOT_ZPmZ_S = 628, + AArch64_CNTB_XPiI = 629, + AArch64_CNTD_XPiI = 630, + AArch64_CNTH_XPiI = 631, + AArch64_CNTP_XPP_B = 632, + AArch64_CNTP_XPP_D = 633, + AArch64_CNTP_XPP_H = 634, + AArch64_CNTP_XPP_S = 635, + AArch64_CNTW_XPiI = 636, + AArch64_CNT_ZPmZ_B = 637, + AArch64_CNT_ZPmZ_D = 638, + AArch64_CNT_ZPmZ_H = 639, + AArch64_CNT_ZPmZ_S = 640, + AArch64_CNTv16i8 = 641, + AArch64_CNTv8i8 = 642, + AArch64_COMPACT_ZPZ_D = 643, + AArch64_COMPACT_ZPZ_S = 644, + AArch64_CPY_ZPmI_B = 645, + AArch64_CPY_ZPmI_D = 646, + AArch64_CPY_ZPmI_H = 647, + AArch64_CPY_ZPmI_S = 648, + AArch64_CPY_ZPmR_B = 649, + AArch64_CPY_ZPmR_D = 650, + AArch64_CPY_ZPmR_H = 651, + AArch64_CPY_ZPmR_S = 652, + AArch64_CPY_ZPmV_B = 653, + AArch64_CPY_ZPmV_D = 654, + AArch64_CPY_ZPmV_H = 655, + AArch64_CPY_ZPmV_S = 656, + AArch64_CPY_ZPzI_B = 657, + AArch64_CPY_ZPzI_D = 658, + AArch64_CPY_ZPzI_H = 659, + AArch64_CPY_ZPzI_S = 660, + AArch64_CPYi16 = 661, + AArch64_CPYi32 = 662, + AArch64_CPYi64 = 663, + AArch64_CPYi8 = 664, + AArch64_CRC32Brr = 665, + AArch64_CRC32CBrr = 666, + AArch64_CRC32CHrr = 667, + AArch64_CRC32CWrr = 668, + AArch64_CRC32CXrr = 669, + AArch64_CRC32Hrr = 670, + AArch64_CRC32Wrr = 671, + AArch64_CRC32Xrr = 672, + AArch64_CSELWr = 673, + AArch64_CSELXr = 674, + AArch64_CSINCWr = 675, + AArch64_CSINCXr = 676, + AArch64_CSINVWr = 677, + AArch64_CSINVXr = 678, + AArch64_CSNEGWr = 679, + AArch64_CSNEGXr = 680, + AArch64_CTERMEQ_WW = 681, + AArch64_CTERMEQ_XX = 682, + AArch64_CTERMNE_WW = 683, + AArch64_CTERMNE_XX = 684, + AArch64_CompilerBarrier = 685, + AArch64_DCPS1 = 686, + AArch64_DCPS2 = 687, + AArch64_DCPS3 = 688, + AArch64_DECB_XPiI = 689, + AArch64_DECD_XPiI = 690, + AArch64_DECD_ZPiI = 691, + AArch64_DECH_XPiI = 692, + AArch64_DECH_ZPiI = 693, + AArch64_DECP_XP_B = 694, + AArch64_DECP_XP_D = 695, + AArch64_DECP_XP_H = 696, + AArch64_DECP_XP_S = 697, + AArch64_DECP_ZP_D = 698, + AArch64_DECP_ZP_H = 699, + AArch64_DECP_ZP_S = 700, + AArch64_DECW_XPiI = 701, + AArch64_DECW_ZPiI = 702, + AArch64_DMB = 703, + AArch64_DRPS = 704, + AArch64_DSB = 705, + AArch64_DUPM_ZI = 706, + AArch64_DUP_ZI_B = 707, + AArch64_DUP_ZI_D = 708, + AArch64_DUP_ZI_H = 709, + AArch64_DUP_ZI_S = 710, + AArch64_DUP_ZR_B = 711, + AArch64_DUP_ZR_D = 712, + AArch64_DUP_ZR_H = 713, + AArch64_DUP_ZR_S = 714, + AArch64_DUP_ZZI_B = 715, + AArch64_DUP_ZZI_D = 716, + AArch64_DUP_ZZI_H = 717, + AArch64_DUP_ZZI_Q = 718, + AArch64_DUP_ZZI_S = 719, + AArch64_DUPv16i8gpr = 720, + AArch64_DUPv16i8lane = 721, + AArch64_DUPv2i32gpr = 722, + AArch64_DUPv2i32lane = 723, + AArch64_DUPv2i64gpr = 724, + AArch64_DUPv2i64lane = 725, + AArch64_DUPv4i16gpr = 726, + AArch64_DUPv4i16lane = 727, + AArch64_DUPv4i32gpr = 728, + AArch64_DUPv4i32lane = 729, + AArch64_DUPv8i16gpr = 730, + AArch64_DUPv8i16lane = 731, + AArch64_DUPv8i8gpr = 732, + AArch64_DUPv8i8lane = 733, + AArch64_EONWrr = 734, + AArch64_EONWrs = 735, + AArch64_EONXrr = 736, + AArch64_EONXrs = 737, + AArch64_EOR3 = 738, + AArch64_EORS_PPzPP = 739, + AArch64_EORV_VPZ_B = 740, + AArch64_EORV_VPZ_D = 741, + AArch64_EORV_VPZ_H = 742, + AArch64_EORV_VPZ_S = 743, + AArch64_EORWri = 744, + AArch64_EORWrr = 745, + AArch64_EORWrs = 746, + AArch64_EORXri = 747, + AArch64_EORXrr = 748, + AArch64_EORXrs = 749, + AArch64_EOR_PPzPP = 750, + AArch64_EOR_ZI = 751, + AArch64_EOR_ZPmZ_B = 752, + AArch64_EOR_ZPmZ_D = 753, + AArch64_EOR_ZPmZ_H = 754, + AArch64_EOR_ZPmZ_S = 755, + AArch64_EOR_ZZZ = 756, + AArch64_EORv16i8 = 757, + AArch64_EORv8i8 = 758, + AArch64_ERET = 759, + AArch64_ERETAA = 760, + AArch64_ERETAB = 761, + AArch64_EXTRWrri = 762, + AArch64_EXTRXrri = 763, + AArch64_EXT_ZZI = 764, + AArch64_EXTv16i8 = 765, + AArch64_EXTv8i8 = 766, + AArch64_F128CSEL = 767, + AArch64_FABD16 = 768, + AArch64_FABD32 = 769, + AArch64_FABD64 = 770, + AArch64_FABD_ZPmZ_D = 771, + AArch64_FABD_ZPmZ_H = 772, + AArch64_FABD_ZPmZ_S = 773, + AArch64_FABDv2f32 = 774, + AArch64_FABDv2f64 = 775, + AArch64_FABDv4f16 = 776, + AArch64_FABDv4f32 = 777, + AArch64_FABDv8f16 = 778, + AArch64_FABSDr = 779, + AArch64_FABSHr = 780, + AArch64_FABSSr = 781, + AArch64_FABS_ZPmZ_D = 782, + AArch64_FABS_ZPmZ_H = 783, + AArch64_FABS_ZPmZ_S = 784, + AArch64_FABSv2f32 = 785, + AArch64_FABSv2f64 = 786, + AArch64_FABSv4f16 = 787, + AArch64_FABSv4f32 = 788, + AArch64_FABSv8f16 = 789, + AArch64_FACGE16 = 790, + AArch64_FACGE32 = 791, + AArch64_FACGE64 = 792, + AArch64_FACGE_PPzZZ_D = 793, + AArch64_FACGE_PPzZZ_H = 794, + AArch64_FACGE_PPzZZ_S = 795, + AArch64_FACGEv2f32 = 796, + AArch64_FACGEv2f64 = 797, + AArch64_FACGEv4f16 = 798, + AArch64_FACGEv4f32 = 799, + AArch64_FACGEv8f16 = 800, + AArch64_FACGT16 = 801, + AArch64_FACGT32 = 802, + AArch64_FACGT64 = 803, + AArch64_FACGT_PPzZZ_D = 804, + AArch64_FACGT_PPzZZ_H = 805, + AArch64_FACGT_PPzZZ_S = 806, + AArch64_FACGTv2f32 = 807, + AArch64_FACGTv2f64 = 808, + AArch64_FACGTv4f16 = 809, + AArch64_FACGTv4f32 = 810, + AArch64_FACGTv8f16 = 811, + AArch64_FADDA_VPZ_D = 812, + AArch64_FADDA_VPZ_H = 813, + AArch64_FADDA_VPZ_S = 814, + AArch64_FADDDrr = 815, + AArch64_FADDHrr = 816, + AArch64_FADDPv2f32 = 817, + AArch64_FADDPv2f64 = 818, + AArch64_FADDPv2i16p = 819, + AArch64_FADDPv2i32p = 820, + AArch64_FADDPv2i64p = 821, + AArch64_FADDPv4f16 = 822, + AArch64_FADDPv4f32 = 823, + AArch64_FADDPv8f16 = 824, + AArch64_FADDSrr = 825, + AArch64_FADDV_VPZ_D = 826, + AArch64_FADDV_VPZ_H = 827, + AArch64_FADDV_VPZ_S = 828, + AArch64_FADD_ZPmI_D = 829, + AArch64_FADD_ZPmI_H = 830, + AArch64_FADD_ZPmI_S = 831, + AArch64_FADD_ZPmZ_D = 832, + AArch64_FADD_ZPmZ_H = 833, + AArch64_FADD_ZPmZ_S = 834, + AArch64_FADD_ZZZ_D = 835, + AArch64_FADD_ZZZ_H = 836, + AArch64_FADD_ZZZ_S = 837, + AArch64_FADDv2f32 = 838, + AArch64_FADDv2f64 = 839, + AArch64_FADDv4f16 = 840, + AArch64_FADDv4f32 = 841, + AArch64_FADDv8f16 = 842, + AArch64_FCADD_ZPmZ_D = 843, + AArch64_FCADD_ZPmZ_H = 844, + AArch64_FCADD_ZPmZ_S = 845, + AArch64_FCADDv2f32 = 846, + AArch64_FCADDv2f64 = 847, + AArch64_FCADDv4f16 = 848, + AArch64_FCADDv4f32 = 849, + AArch64_FCADDv8f16 = 850, + AArch64_FCCMPDrr = 851, + AArch64_FCCMPEDrr = 852, + AArch64_FCCMPEHrr = 853, + AArch64_FCCMPESrr = 854, + AArch64_FCCMPHrr = 855, + AArch64_FCCMPSrr = 856, + AArch64_FCMEQ16 = 857, + AArch64_FCMEQ32 = 858, + AArch64_FCMEQ64 = 859, + AArch64_FCMEQ_PPzZ0_D = 860, + AArch64_FCMEQ_PPzZ0_H = 861, + AArch64_FCMEQ_PPzZ0_S = 862, + AArch64_FCMEQ_PPzZZ_D = 863, + AArch64_FCMEQ_PPzZZ_H = 864, + AArch64_FCMEQ_PPzZZ_S = 865, + AArch64_FCMEQv1i16rz = 866, + AArch64_FCMEQv1i32rz = 867, + AArch64_FCMEQv1i64rz = 868, + AArch64_FCMEQv2f32 = 869, + AArch64_FCMEQv2f64 = 870, + AArch64_FCMEQv2i32rz = 871, + AArch64_FCMEQv2i64rz = 872, + AArch64_FCMEQv4f16 = 873, + AArch64_FCMEQv4f32 = 874, + AArch64_FCMEQv4i16rz = 875, + AArch64_FCMEQv4i32rz = 876, + AArch64_FCMEQv8f16 = 877, + AArch64_FCMEQv8i16rz = 878, + AArch64_FCMGE16 = 879, + AArch64_FCMGE32 = 880, + AArch64_FCMGE64 = 881, + AArch64_FCMGE_PPzZ0_D = 882, + AArch64_FCMGE_PPzZ0_H = 883, + AArch64_FCMGE_PPzZ0_S = 884, + AArch64_FCMGE_PPzZZ_D = 885, + AArch64_FCMGE_PPzZZ_H = 886, + AArch64_FCMGE_PPzZZ_S = 887, + AArch64_FCMGEv1i16rz = 888, + AArch64_FCMGEv1i32rz = 889, + AArch64_FCMGEv1i64rz = 890, + AArch64_FCMGEv2f32 = 891, + AArch64_FCMGEv2f64 = 892, + AArch64_FCMGEv2i32rz = 893, + AArch64_FCMGEv2i64rz = 894, + AArch64_FCMGEv4f16 = 895, + AArch64_FCMGEv4f32 = 896, + AArch64_FCMGEv4i16rz = 897, + AArch64_FCMGEv4i32rz = 898, + AArch64_FCMGEv8f16 = 899, + AArch64_FCMGEv8i16rz = 900, + AArch64_FCMGT16 = 901, + AArch64_FCMGT32 = 902, + AArch64_FCMGT64 = 903, + AArch64_FCMGT_PPzZ0_D = 904, + AArch64_FCMGT_PPzZ0_H = 905, + AArch64_FCMGT_PPzZ0_S = 906, + AArch64_FCMGT_PPzZZ_D = 907, + AArch64_FCMGT_PPzZZ_H = 908, + AArch64_FCMGT_PPzZZ_S = 909, + AArch64_FCMGTv1i16rz = 910, + AArch64_FCMGTv1i32rz = 911, + AArch64_FCMGTv1i64rz = 912, + AArch64_FCMGTv2f32 = 913, + AArch64_FCMGTv2f64 = 914, + AArch64_FCMGTv2i32rz = 915, + AArch64_FCMGTv2i64rz = 916, + AArch64_FCMGTv4f16 = 917, + AArch64_FCMGTv4f32 = 918, + AArch64_FCMGTv4i16rz = 919, + AArch64_FCMGTv4i32rz = 920, + AArch64_FCMGTv8f16 = 921, + AArch64_FCMGTv8i16rz = 922, + AArch64_FCMLA_ZPmZZ_D = 923, + AArch64_FCMLA_ZPmZZ_H = 924, + AArch64_FCMLA_ZPmZZ_S = 925, + AArch64_FCMLA_ZZZI_H = 926, + AArch64_FCMLA_ZZZI_S = 927, + AArch64_FCMLAv2f32 = 928, + AArch64_FCMLAv2f64 = 929, + AArch64_FCMLAv4f16 = 930, + AArch64_FCMLAv4f16_indexed = 931, + AArch64_FCMLAv4f32 = 932, + AArch64_FCMLAv4f32_indexed = 933, + AArch64_FCMLAv8f16 = 934, + AArch64_FCMLAv8f16_indexed = 935, + AArch64_FCMLE_PPzZ0_D = 936, + AArch64_FCMLE_PPzZ0_H = 937, + AArch64_FCMLE_PPzZ0_S = 938, + AArch64_FCMLEv1i16rz = 939, + AArch64_FCMLEv1i32rz = 940, + AArch64_FCMLEv1i64rz = 941, + AArch64_FCMLEv2i32rz = 942, + AArch64_FCMLEv2i64rz = 943, + AArch64_FCMLEv4i16rz = 944, + AArch64_FCMLEv4i32rz = 945, + AArch64_FCMLEv8i16rz = 946, + AArch64_FCMLT_PPzZ0_D = 947, + AArch64_FCMLT_PPzZ0_H = 948, + AArch64_FCMLT_PPzZ0_S = 949, + AArch64_FCMLTv1i16rz = 950, + AArch64_FCMLTv1i32rz = 951, + AArch64_FCMLTv1i64rz = 952, + AArch64_FCMLTv2i32rz = 953, + AArch64_FCMLTv2i64rz = 954, + AArch64_FCMLTv4i16rz = 955, + AArch64_FCMLTv4i32rz = 956, + AArch64_FCMLTv8i16rz = 957, + AArch64_FCMNE_PPzZ0_D = 958, + AArch64_FCMNE_PPzZ0_H = 959, + AArch64_FCMNE_PPzZ0_S = 960, + AArch64_FCMNE_PPzZZ_D = 961, + AArch64_FCMNE_PPzZZ_H = 962, + AArch64_FCMNE_PPzZZ_S = 963, + AArch64_FCMPDri = 964, + AArch64_FCMPDrr = 965, + AArch64_FCMPEDri = 966, + AArch64_FCMPEDrr = 967, + AArch64_FCMPEHri = 968, + AArch64_FCMPEHrr = 969, + AArch64_FCMPESri = 970, + AArch64_FCMPESrr = 971, + AArch64_FCMPHri = 972, + AArch64_FCMPHrr = 973, + AArch64_FCMPSri = 974, + AArch64_FCMPSrr = 975, + AArch64_FCMUO_PPzZZ_D = 976, + AArch64_FCMUO_PPzZZ_H = 977, + AArch64_FCMUO_PPzZZ_S = 978, + AArch64_FCPY_ZPmI_D = 979, + AArch64_FCPY_ZPmI_H = 980, + AArch64_FCPY_ZPmI_S = 981, + AArch64_FCSELDrrr = 982, + AArch64_FCSELHrrr = 983, + AArch64_FCSELSrrr = 984, + AArch64_FCVTASUWDr = 985, + AArch64_FCVTASUWHr = 986, + AArch64_FCVTASUWSr = 987, + AArch64_FCVTASUXDr = 988, + AArch64_FCVTASUXHr = 989, + AArch64_FCVTASUXSr = 990, + AArch64_FCVTASv1f16 = 991, + AArch64_FCVTASv1i32 = 992, + AArch64_FCVTASv1i64 = 993, + AArch64_FCVTASv2f32 = 994, + AArch64_FCVTASv2f64 = 995, + AArch64_FCVTASv4f16 = 996, + AArch64_FCVTASv4f32 = 997, + AArch64_FCVTASv8f16 = 998, + AArch64_FCVTAUUWDr = 999, + AArch64_FCVTAUUWHr = 1000, + AArch64_FCVTAUUWSr = 1001, + AArch64_FCVTAUUXDr = 1002, + AArch64_FCVTAUUXHr = 1003, + AArch64_FCVTAUUXSr = 1004, + AArch64_FCVTAUv1f16 = 1005, + AArch64_FCVTAUv1i32 = 1006, + AArch64_FCVTAUv1i64 = 1007, + AArch64_FCVTAUv2f32 = 1008, + AArch64_FCVTAUv2f64 = 1009, + AArch64_FCVTAUv4f16 = 1010, + AArch64_FCVTAUv4f32 = 1011, + AArch64_FCVTAUv8f16 = 1012, + AArch64_FCVTDHr = 1013, + AArch64_FCVTDSr = 1014, + AArch64_FCVTHDr = 1015, + AArch64_FCVTHSr = 1016, + AArch64_FCVTLv2i32 = 1017, + AArch64_FCVTLv4i16 = 1018, + AArch64_FCVTLv4i32 = 1019, + AArch64_FCVTLv8i16 = 1020, + AArch64_FCVTMSUWDr = 1021, + AArch64_FCVTMSUWHr = 1022, + AArch64_FCVTMSUWSr = 1023, + AArch64_FCVTMSUXDr = 1024, + AArch64_FCVTMSUXHr = 1025, + AArch64_FCVTMSUXSr = 1026, + AArch64_FCVTMSv1f16 = 1027, + AArch64_FCVTMSv1i32 = 1028, + AArch64_FCVTMSv1i64 = 1029, + AArch64_FCVTMSv2f32 = 1030, + AArch64_FCVTMSv2f64 = 1031, + AArch64_FCVTMSv4f16 = 1032, + AArch64_FCVTMSv4f32 = 1033, + AArch64_FCVTMSv8f16 = 1034, + AArch64_FCVTMUUWDr = 1035, + AArch64_FCVTMUUWHr = 1036, + AArch64_FCVTMUUWSr = 1037, + AArch64_FCVTMUUXDr = 1038, + AArch64_FCVTMUUXHr = 1039, + AArch64_FCVTMUUXSr = 1040, + AArch64_FCVTMUv1f16 = 1041, + AArch64_FCVTMUv1i32 = 1042, + AArch64_FCVTMUv1i64 = 1043, + AArch64_FCVTMUv2f32 = 1044, + AArch64_FCVTMUv2f64 = 1045, + AArch64_FCVTMUv4f16 = 1046, + AArch64_FCVTMUv4f32 = 1047, + AArch64_FCVTMUv8f16 = 1048, + AArch64_FCVTNSUWDr = 1049, + AArch64_FCVTNSUWHr = 1050, + AArch64_FCVTNSUWSr = 1051, + AArch64_FCVTNSUXDr = 1052, + AArch64_FCVTNSUXHr = 1053, + AArch64_FCVTNSUXSr = 1054, + AArch64_FCVTNSv1f16 = 1055, + AArch64_FCVTNSv1i32 = 1056, + AArch64_FCVTNSv1i64 = 1057, + AArch64_FCVTNSv2f32 = 1058, + AArch64_FCVTNSv2f64 = 1059, + AArch64_FCVTNSv4f16 = 1060, + AArch64_FCVTNSv4f32 = 1061, + AArch64_FCVTNSv8f16 = 1062, + AArch64_FCVTNUUWDr = 1063, + AArch64_FCVTNUUWHr = 1064, + AArch64_FCVTNUUWSr = 1065, + AArch64_FCVTNUUXDr = 1066, + AArch64_FCVTNUUXHr = 1067, + AArch64_FCVTNUUXSr = 1068, + AArch64_FCVTNUv1f16 = 1069, + AArch64_FCVTNUv1i32 = 1070, + AArch64_FCVTNUv1i64 = 1071, + AArch64_FCVTNUv2f32 = 1072, + AArch64_FCVTNUv2f64 = 1073, + AArch64_FCVTNUv4f16 = 1074, + AArch64_FCVTNUv4f32 = 1075, + AArch64_FCVTNUv8f16 = 1076, + AArch64_FCVTNv2i32 = 1077, + AArch64_FCVTNv4i16 = 1078, + AArch64_FCVTNv4i32 = 1079, + AArch64_FCVTNv8i16 = 1080, + AArch64_FCVTPSUWDr = 1081, + AArch64_FCVTPSUWHr = 1082, + AArch64_FCVTPSUWSr = 1083, + AArch64_FCVTPSUXDr = 1084, + AArch64_FCVTPSUXHr = 1085, + AArch64_FCVTPSUXSr = 1086, + AArch64_FCVTPSv1f16 = 1087, + AArch64_FCVTPSv1i32 = 1088, + AArch64_FCVTPSv1i64 = 1089, + AArch64_FCVTPSv2f32 = 1090, + AArch64_FCVTPSv2f64 = 1091, + AArch64_FCVTPSv4f16 = 1092, + AArch64_FCVTPSv4f32 = 1093, + AArch64_FCVTPSv8f16 = 1094, + AArch64_FCVTPUUWDr = 1095, + AArch64_FCVTPUUWHr = 1096, + AArch64_FCVTPUUWSr = 1097, + AArch64_FCVTPUUXDr = 1098, + AArch64_FCVTPUUXHr = 1099, + AArch64_FCVTPUUXSr = 1100, + AArch64_FCVTPUv1f16 = 1101, + AArch64_FCVTPUv1i32 = 1102, + AArch64_FCVTPUv1i64 = 1103, + AArch64_FCVTPUv2f32 = 1104, + AArch64_FCVTPUv2f64 = 1105, + AArch64_FCVTPUv4f16 = 1106, + AArch64_FCVTPUv4f32 = 1107, + AArch64_FCVTPUv8f16 = 1108, + AArch64_FCVTSDr = 1109, + AArch64_FCVTSHr = 1110, + AArch64_FCVTXNv1i64 = 1111, + AArch64_FCVTXNv2f32 = 1112, + AArch64_FCVTXNv4f32 = 1113, + AArch64_FCVTZSSWDri = 1114, + AArch64_FCVTZSSWHri = 1115, + AArch64_FCVTZSSWSri = 1116, + AArch64_FCVTZSSXDri = 1117, + AArch64_FCVTZSSXHri = 1118, + AArch64_FCVTZSSXSri = 1119, + AArch64_FCVTZSUWDr = 1120, + AArch64_FCVTZSUWHr = 1121, + AArch64_FCVTZSUWSr = 1122, + AArch64_FCVTZSUXDr = 1123, + AArch64_FCVTZSUXHr = 1124, + AArch64_FCVTZSUXSr = 1125, + AArch64_FCVTZS_ZPmZ_DtoD = 1126, + AArch64_FCVTZS_ZPmZ_DtoS = 1127, + AArch64_FCVTZS_ZPmZ_HtoD = 1128, + AArch64_FCVTZS_ZPmZ_HtoH = 1129, + AArch64_FCVTZS_ZPmZ_HtoS = 1130, + AArch64_FCVTZS_ZPmZ_StoD = 1131, + AArch64_FCVTZS_ZPmZ_StoS = 1132, + AArch64_FCVTZSd = 1133, + AArch64_FCVTZSh = 1134, + AArch64_FCVTZSs = 1135, + AArch64_FCVTZSv1f16 = 1136, + AArch64_FCVTZSv1i32 = 1137, + AArch64_FCVTZSv1i64 = 1138, + AArch64_FCVTZSv2f32 = 1139, + AArch64_FCVTZSv2f64 = 1140, + AArch64_FCVTZSv2i32_shift = 1141, + AArch64_FCVTZSv2i64_shift = 1142, + AArch64_FCVTZSv4f16 = 1143, + AArch64_FCVTZSv4f32 = 1144, + AArch64_FCVTZSv4i16_shift = 1145, + AArch64_FCVTZSv4i32_shift = 1146, + AArch64_FCVTZSv8f16 = 1147, + AArch64_FCVTZSv8i16_shift = 1148, + AArch64_FCVTZUSWDri = 1149, + AArch64_FCVTZUSWHri = 1150, + AArch64_FCVTZUSWSri = 1151, + AArch64_FCVTZUSXDri = 1152, + AArch64_FCVTZUSXHri = 1153, + AArch64_FCVTZUSXSri = 1154, + AArch64_FCVTZUUWDr = 1155, + AArch64_FCVTZUUWHr = 1156, + AArch64_FCVTZUUWSr = 1157, + AArch64_FCVTZUUXDr = 1158, + AArch64_FCVTZUUXHr = 1159, + AArch64_FCVTZUUXSr = 1160, + AArch64_FCVTZU_ZPmZ_DtoD = 1161, + AArch64_FCVTZU_ZPmZ_DtoS = 1162, + AArch64_FCVTZU_ZPmZ_HtoD = 1163, + AArch64_FCVTZU_ZPmZ_HtoH = 1164, + AArch64_FCVTZU_ZPmZ_HtoS = 1165, + AArch64_FCVTZU_ZPmZ_StoD = 1166, + AArch64_FCVTZU_ZPmZ_StoS = 1167, + AArch64_FCVTZUd = 1168, + AArch64_FCVTZUh = 1169, + AArch64_FCVTZUs = 1170, + AArch64_FCVTZUv1f16 = 1171, + AArch64_FCVTZUv1i32 = 1172, + AArch64_FCVTZUv1i64 = 1173, + AArch64_FCVTZUv2f32 = 1174, + AArch64_FCVTZUv2f64 = 1175, + AArch64_FCVTZUv2i32_shift = 1176, + AArch64_FCVTZUv2i64_shift = 1177, + AArch64_FCVTZUv4f16 = 1178, + AArch64_FCVTZUv4f32 = 1179, + AArch64_FCVTZUv4i16_shift = 1180, + AArch64_FCVTZUv4i32_shift = 1181, + AArch64_FCVTZUv8f16 = 1182, + AArch64_FCVTZUv8i16_shift = 1183, + AArch64_FCVT_ZPmZ_DtoH = 1184, + AArch64_FCVT_ZPmZ_DtoS = 1185, + AArch64_FCVT_ZPmZ_HtoD = 1186, + AArch64_FCVT_ZPmZ_HtoS = 1187, + AArch64_FCVT_ZPmZ_StoD = 1188, + AArch64_FCVT_ZPmZ_StoH = 1189, + AArch64_FDIVDrr = 1190, + AArch64_FDIVHrr = 1191, + AArch64_FDIVR_ZPmZ_D = 1192, + AArch64_FDIVR_ZPmZ_H = 1193, + AArch64_FDIVR_ZPmZ_S = 1194, + AArch64_FDIVSrr = 1195, + AArch64_FDIV_ZPmZ_D = 1196, + AArch64_FDIV_ZPmZ_H = 1197, + AArch64_FDIV_ZPmZ_S = 1198, + AArch64_FDIVv2f32 = 1199, + AArch64_FDIVv2f64 = 1200, + AArch64_FDIVv4f16 = 1201, + AArch64_FDIVv4f32 = 1202, + AArch64_FDIVv8f16 = 1203, + AArch64_FDUP_ZI_D = 1204, + AArch64_FDUP_ZI_H = 1205, + AArch64_FDUP_ZI_S = 1206, + AArch64_FEXPA_ZZ_D = 1207, + AArch64_FEXPA_ZZ_H = 1208, + AArch64_FEXPA_ZZ_S = 1209, + AArch64_FJCVTZS = 1210, + AArch64_FMADDDrrr = 1211, + AArch64_FMADDHrrr = 1212, + AArch64_FMADDSrrr = 1213, + AArch64_FMAD_ZPmZZ_D = 1214, + AArch64_FMAD_ZPmZZ_H = 1215, + AArch64_FMAD_ZPmZZ_S = 1216, + AArch64_FMAXDrr = 1217, + AArch64_FMAXHrr = 1218, + AArch64_FMAXNMDrr = 1219, + AArch64_FMAXNMHrr = 1220, + AArch64_FMAXNMPv2f32 = 1221, + AArch64_FMAXNMPv2f64 = 1222, + AArch64_FMAXNMPv2i16p = 1223, + AArch64_FMAXNMPv2i32p = 1224, + AArch64_FMAXNMPv2i64p = 1225, + AArch64_FMAXNMPv4f16 = 1226, + AArch64_FMAXNMPv4f32 = 1227, + AArch64_FMAXNMPv8f16 = 1228, + AArch64_FMAXNMSrr = 1229, + AArch64_FMAXNMV_VPZ_D = 1230, + AArch64_FMAXNMV_VPZ_H = 1231, + AArch64_FMAXNMV_VPZ_S = 1232, + AArch64_FMAXNMVv4i16v = 1233, + AArch64_FMAXNMVv4i32v = 1234, + AArch64_FMAXNMVv8i16v = 1235, + AArch64_FMAXNM_ZPmI_D = 1236, + AArch64_FMAXNM_ZPmI_H = 1237, + AArch64_FMAXNM_ZPmI_S = 1238, + AArch64_FMAXNM_ZPmZ_D = 1239, + AArch64_FMAXNM_ZPmZ_H = 1240, + AArch64_FMAXNM_ZPmZ_S = 1241, + AArch64_FMAXNMv2f32 = 1242, + AArch64_FMAXNMv2f64 = 1243, + AArch64_FMAXNMv4f16 = 1244, + AArch64_FMAXNMv4f32 = 1245, + AArch64_FMAXNMv8f16 = 1246, + AArch64_FMAXPv2f32 = 1247, + AArch64_FMAXPv2f64 = 1248, + AArch64_FMAXPv2i16p = 1249, + AArch64_FMAXPv2i32p = 1250, + AArch64_FMAXPv2i64p = 1251, + AArch64_FMAXPv4f16 = 1252, + AArch64_FMAXPv4f32 = 1253, + AArch64_FMAXPv8f16 = 1254, + AArch64_FMAXSrr = 1255, + AArch64_FMAXV_VPZ_D = 1256, + AArch64_FMAXV_VPZ_H = 1257, + AArch64_FMAXV_VPZ_S = 1258, + AArch64_FMAXVv4i16v = 1259, + AArch64_FMAXVv4i32v = 1260, + AArch64_FMAXVv8i16v = 1261, + AArch64_FMAX_ZPmI_D = 1262, + AArch64_FMAX_ZPmI_H = 1263, + AArch64_FMAX_ZPmI_S = 1264, + AArch64_FMAX_ZPmZ_D = 1265, + AArch64_FMAX_ZPmZ_H = 1266, + AArch64_FMAX_ZPmZ_S = 1267, + AArch64_FMAXv2f32 = 1268, + AArch64_FMAXv2f64 = 1269, + AArch64_FMAXv4f16 = 1270, + AArch64_FMAXv4f32 = 1271, + AArch64_FMAXv8f16 = 1272, + AArch64_FMINDrr = 1273, + AArch64_FMINHrr = 1274, + AArch64_FMINNMDrr = 1275, + AArch64_FMINNMHrr = 1276, + AArch64_FMINNMPv2f32 = 1277, + AArch64_FMINNMPv2f64 = 1278, + AArch64_FMINNMPv2i16p = 1279, + AArch64_FMINNMPv2i32p = 1280, + AArch64_FMINNMPv2i64p = 1281, + AArch64_FMINNMPv4f16 = 1282, + AArch64_FMINNMPv4f32 = 1283, + AArch64_FMINNMPv8f16 = 1284, + AArch64_FMINNMSrr = 1285, + AArch64_FMINNMV_VPZ_D = 1286, + AArch64_FMINNMV_VPZ_H = 1287, + AArch64_FMINNMV_VPZ_S = 1288, + AArch64_FMINNMVv4i16v = 1289, + AArch64_FMINNMVv4i32v = 1290, + AArch64_FMINNMVv8i16v = 1291, + AArch64_FMINNM_ZPmI_D = 1292, + AArch64_FMINNM_ZPmI_H = 1293, + AArch64_FMINNM_ZPmI_S = 1294, + AArch64_FMINNM_ZPmZ_D = 1295, + AArch64_FMINNM_ZPmZ_H = 1296, + AArch64_FMINNM_ZPmZ_S = 1297, + AArch64_FMINNMv2f32 = 1298, + AArch64_FMINNMv2f64 = 1299, + AArch64_FMINNMv4f16 = 1300, + AArch64_FMINNMv4f32 = 1301, + AArch64_FMINNMv8f16 = 1302, + AArch64_FMINPv2f32 = 1303, + AArch64_FMINPv2f64 = 1304, + AArch64_FMINPv2i16p = 1305, + AArch64_FMINPv2i32p = 1306, + AArch64_FMINPv2i64p = 1307, + AArch64_FMINPv4f16 = 1308, + AArch64_FMINPv4f32 = 1309, + AArch64_FMINPv8f16 = 1310, + AArch64_FMINSrr = 1311, + AArch64_FMINV_VPZ_D = 1312, + AArch64_FMINV_VPZ_H = 1313, + AArch64_FMINV_VPZ_S = 1314, + AArch64_FMINVv4i16v = 1315, + AArch64_FMINVv4i32v = 1316, + AArch64_FMINVv8i16v = 1317, + AArch64_FMIN_ZPmI_D = 1318, + AArch64_FMIN_ZPmI_H = 1319, + AArch64_FMIN_ZPmI_S = 1320, + AArch64_FMIN_ZPmZ_D = 1321, + AArch64_FMIN_ZPmZ_H = 1322, + AArch64_FMIN_ZPmZ_S = 1323, + AArch64_FMINv2f32 = 1324, + AArch64_FMINv2f64 = 1325, + AArch64_FMINv4f16 = 1326, + AArch64_FMINv4f32 = 1327, + AArch64_FMINv8f16 = 1328, + AArch64_FMLA_ZPmZZ_D = 1329, + AArch64_FMLA_ZPmZZ_H = 1330, + AArch64_FMLA_ZPmZZ_S = 1331, + AArch64_FMLA_ZZZI_D = 1332, + AArch64_FMLA_ZZZI_H = 1333, + AArch64_FMLA_ZZZI_S = 1334, + AArch64_FMLAv1i16_indexed = 1335, + AArch64_FMLAv1i32_indexed = 1336, + AArch64_FMLAv1i64_indexed = 1337, + AArch64_FMLAv2f32 = 1338, + AArch64_FMLAv2f64 = 1339, + AArch64_FMLAv2i32_indexed = 1340, + AArch64_FMLAv2i64_indexed = 1341, + AArch64_FMLAv4f16 = 1342, + AArch64_FMLAv4f32 = 1343, + AArch64_FMLAv4i16_indexed = 1344, + AArch64_FMLAv4i32_indexed = 1345, + AArch64_FMLAv8f16 = 1346, + AArch64_FMLAv8i16_indexed = 1347, + AArch64_FMLS_ZPmZZ_D = 1348, + AArch64_FMLS_ZPmZZ_H = 1349, + AArch64_FMLS_ZPmZZ_S = 1350, + AArch64_FMLS_ZZZI_D = 1351, + AArch64_FMLS_ZZZI_H = 1352, + AArch64_FMLS_ZZZI_S = 1353, + AArch64_FMLSv1i16_indexed = 1354, + AArch64_FMLSv1i32_indexed = 1355, + AArch64_FMLSv1i64_indexed = 1356, + AArch64_FMLSv2f32 = 1357, + AArch64_FMLSv2f64 = 1358, + AArch64_FMLSv2i32_indexed = 1359, + AArch64_FMLSv2i64_indexed = 1360, + AArch64_FMLSv4f16 = 1361, + AArch64_FMLSv4f32 = 1362, + AArch64_FMLSv4i16_indexed = 1363, + AArch64_FMLSv4i32_indexed = 1364, + AArch64_FMLSv8f16 = 1365, + AArch64_FMLSv8i16_indexed = 1366, + AArch64_FMOVD0 = 1367, + AArch64_FMOVDXHighr = 1368, + AArch64_FMOVDXr = 1369, + AArch64_FMOVDi = 1370, + AArch64_FMOVDr = 1371, + AArch64_FMOVH0 = 1372, + AArch64_FMOVHWr = 1373, + AArch64_FMOVHXr = 1374, + AArch64_FMOVHi = 1375, + AArch64_FMOVHr = 1376, + AArch64_FMOVS0 = 1377, + AArch64_FMOVSWr = 1378, + AArch64_FMOVSi = 1379, + AArch64_FMOVSr = 1380, + AArch64_FMOVWHr = 1381, + AArch64_FMOVWSr = 1382, + AArch64_FMOVXDHighr = 1383, + AArch64_FMOVXDr = 1384, + AArch64_FMOVXHr = 1385, + AArch64_FMOVv2f32_ns = 1386, + AArch64_FMOVv2f64_ns = 1387, + AArch64_FMOVv4f16_ns = 1388, + AArch64_FMOVv4f32_ns = 1389, + AArch64_FMOVv8f16_ns = 1390, + AArch64_FMSB_ZPmZZ_D = 1391, + AArch64_FMSB_ZPmZZ_H = 1392, + AArch64_FMSB_ZPmZZ_S = 1393, + AArch64_FMSUBDrrr = 1394, + AArch64_FMSUBHrrr = 1395, + AArch64_FMSUBSrrr = 1396, + AArch64_FMULDrr = 1397, + AArch64_FMULHrr = 1398, + AArch64_FMULSrr = 1399, + AArch64_FMULX16 = 1400, + AArch64_FMULX32 = 1401, + AArch64_FMULX64 = 1402, + AArch64_FMULX_ZPmZ_D = 1403, + AArch64_FMULX_ZPmZ_H = 1404, + AArch64_FMULX_ZPmZ_S = 1405, + AArch64_FMULXv1i16_indexed = 1406, + AArch64_FMULXv1i32_indexed = 1407, + AArch64_FMULXv1i64_indexed = 1408, + AArch64_FMULXv2f32 = 1409, + AArch64_FMULXv2f64 = 1410, + AArch64_FMULXv2i32_indexed = 1411, + AArch64_FMULXv2i64_indexed = 1412, + AArch64_FMULXv4f16 = 1413, + AArch64_FMULXv4f32 = 1414, + AArch64_FMULXv4i16_indexed = 1415, + AArch64_FMULXv4i32_indexed = 1416, + AArch64_FMULXv8f16 = 1417, + AArch64_FMULXv8i16_indexed = 1418, + AArch64_FMUL_ZPmI_D = 1419, + AArch64_FMUL_ZPmI_H = 1420, + AArch64_FMUL_ZPmI_S = 1421, + AArch64_FMUL_ZPmZ_D = 1422, + AArch64_FMUL_ZPmZ_H = 1423, + AArch64_FMUL_ZPmZ_S = 1424, + AArch64_FMUL_ZZZI_D = 1425, + AArch64_FMUL_ZZZI_H = 1426, + AArch64_FMUL_ZZZI_S = 1427, + AArch64_FMUL_ZZZ_D = 1428, + AArch64_FMUL_ZZZ_H = 1429, + AArch64_FMUL_ZZZ_S = 1430, + AArch64_FMULv1i16_indexed = 1431, + AArch64_FMULv1i32_indexed = 1432, + AArch64_FMULv1i64_indexed = 1433, + AArch64_FMULv2f32 = 1434, + AArch64_FMULv2f64 = 1435, + AArch64_FMULv2i32_indexed = 1436, + AArch64_FMULv2i64_indexed = 1437, + AArch64_FMULv4f16 = 1438, + AArch64_FMULv4f32 = 1439, + AArch64_FMULv4i16_indexed = 1440, + AArch64_FMULv4i32_indexed = 1441, + AArch64_FMULv8f16 = 1442, + AArch64_FMULv8i16_indexed = 1443, + AArch64_FNEGDr = 1444, + AArch64_FNEGHr = 1445, + AArch64_FNEGSr = 1446, + AArch64_FNEG_ZPmZ_D = 1447, + AArch64_FNEG_ZPmZ_H = 1448, + AArch64_FNEG_ZPmZ_S = 1449, + AArch64_FNEGv2f32 = 1450, + AArch64_FNEGv2f64 = 1451, + AArch64_FNEGv4f16 = 1452, + AArch64_FNEGv4f32 = 1453, + AArch64_FNEGv8f16 = 1454, + AArch64_FNMADDDrrr = 1455, + AArch64_FNMADDHrrr = 1456, + AArch64_FNMADDSrrr = 1457, + AArch64_FNMAD_ZPmZZ_D = 1458, + AArch64_FNMAD_ZPmZZ_H = 1459, + AArch64_FNMAD_ZPmZZ_S = 1460, + AArch64_FNMLA_ZPmZZ_D = 1461, + AArch64_FNMLA_ZPmZZ_H = 1462, + AArch64_FNMLA_ZPmZZ_S = 1463, + AArch64_FNMLS_ZPmZZ_D = 1464, + AArch64_FNMLS_ZPmZZ_H = 1465, + AArch64_FNMLS_ZPmZZ_S = 1466, + AArch64_FNMSB_ZPmZZ_D = 1467, + AArch64_FNMSB_ZPmZZ_H = 1468, + AArch64_FNMSB_ZPmZZ_S = 1469, + AArch64_FNMSUBDrrr = 1470, + AArch64_FNMSUBHrrr = 1471, + AArch64_FNMSUBSrrr = 1472, + AArch64_FNMULDrr = 1473, + AArch64_FNMULHrr = 1474, + AArch64_FNMULSrr = 1475, + AArch64_FRECPE_ZZ_D = 1476, + AArch64_FRECPE_ZZ_H = 1477, + AArch64_FRECPE_ZZ_S = 1478, + AArch64_FRECPEv1f16 = 1479, + AArch64_FRECPEv1i32 = 1480, + AArch64_FRECPEv1i64 = 1481, + AArch64_FRECPEv2f32 = 1482, + AArch64_FRECPEv2f64 = 1483, + AArch64_FRECPEv4f16 = 1484, + AArch64_FRECPEv4f32 = 1485, + AArch64_FRECPEv8f16 = 1486, + AArch64_FRECPS16 = 1487, + AArch64_FRECPS32 = 1488, + AArch64_FRECPS64 = 1489, + AArch64_FRECPS_ZZZ_D = 1490, + AArch64_FRECPS_ZZZ_H = 1491, + AArch64_FRECPS_ZZZ_S = 1492, + AArch64_FRECPSv2f32 = 1493, + AArch64_FRECPSv2f64 = 1494, + AArch64_FRECPSv4f16 = 1495, + AArch64_FRECPSv4f32 = 1496, + AArch64_FRECPSv8f16 = 1497, + AArch64_FRECPX_ZPmZ_D = 1498, + AArch64_FRECPX_ZPmZ_H = 1499, + AArch64_FRECPX_ZPmZ_S = 1500, + AArch64_FRECPXv1f16 = 1501, + AArch64_FRECPXv1i32 = 1502, + AArch64_FRECPXv1i64 = 1503, + AArch64_FRINTADr = 1504, + AArch64_FRINTAHr = 1505, + AArch64_FRINTASr = 1506, + AArch64_FRINTA_ZPmZ_D = 1507, + AArch64_FRINTA_ZPmZ_H = 1508, + AArch64_FRINTA_ZPmZ_S = 1509, + AArch64_FRINTAv2f32 = 1510, + AArch64_FRINTAv2f64 = 1511, + AArch64_FRINTAv4f16 = 1512, + AArch64_FRINTAv4f32 = 1513, + AArch64_FRINTAv8f16 = 1514, + AArch64_FRINTIDr = 1515, + AArch64_FRINTIHr = 1516, + AArch64_FRINTISr = 1517, + AArch64_FRINTI_ZPmZ_D = 1518, + AArch64_FRINTI_ZPmZ_H = 1519, + AArch64_FRINTI_ZPmZ_S = 1520, + AArch64_FRINTIv2f32 = 1521, + AArch64_FRINTIv2f64 = 1522, + AArch64_FRINTIv4f16 = 1523, + AArch64_FRINTIv4f32 = 1524, + AArch64_FRINTIv8f16 = 1525, + AArch64_FRINTMDr = 1526, + AArch64_FRINTMHr = 1527, + AArch64_FRINTMSr = 1528, + AArch64_FRINTM_ZPmZ_D = 1529, + AArch64_FRINTM_ZPmZ_H = 1530, + AArch64_FRINTM_ZPmZ_S = 1531, + AArch64_FRINTMv2f32 = 1532, + AArch64_FRINTMv2f64 = 1533, + AArch64_FRINTMv4f16 = 1534, + AArch64_FRINTMv4f32 = 1535, + AArch64_FRINTMv8f16 = 1536, + AArch64_FRINTNDr = 1537, + AArch64_FRINTNHr = 1538, + AArch64_FRINTNSr = 1539, + AArch64_FRINTN_ZPmZ_D = 1540, + AArch64_FRINTN_ZPmZ_H = 1541, + AArch64_FRINTN_ZPmZ_S = 1542, + AArch64_FRINTNv2f32 = 1543, + AArch64_FRINTNv2f64 = 1544, + AArch64_FRINTNv4f16 = 1545, + AArch64_FRINTNv4f32 = 1546, + AArch64_FRINTNv8f16 = 1547, + AArch64_FRINTPDr = 1548, + AArch64_FRINTPHr = 1549, + AArch64_FRINTPSr = 1550, + AArch64_FRINTP_ZPmZ_D = 1551, + AArch64_FRINTP_ZPmZ_H = 1552, + AArch64_FRINTP_ZPmZ_S = 1553, + AArch64_FRINTPv2f32 = 1554, + AArch64_FRINTPv2f64 = 1555, + AArch64_FRINTPv4f16 = 1556, + AArch64_FRINTPv4f32 = 1557, + AArch64_FRINTPv8f16 = 1558, + AArch64_FRINTXDr = 1559, + AArch64_FRINTXHr = 1560, + AArch64_FRINTXSr = 1561, + AArch64_FRINTX_ZPmZ_D = 1562, + AArch64_FRINTX_ZPmZ_H = 1563, + AArch64_FRINTX_ZPmZ_S = 1564, + AArch64_FRINTXv2f32 = 1565, + AArch64_FRINTXv2f64 = 1566, + AArch64_FRINTXv4f16 = 1567, + AArch64_FRINTXv4f32 = 1568, + AArch64_FRINTXv8f16 = 1569, + AArch64_FRINTZDr = 1570, + AArch64_FRINTZHr = 1571, + AArch64_FRINTZSr = 1572, + AArch64_FRINTZ_ZPmZ_D = 1573, + AArch64_FRINTZ_ZPmZ_H = 1574, + AArch64_FRINTZ_ZPmZ_S = 1575, + AArch64_FRINTZv2f32 = 1576, + AArch64_FRINTZv2f64 = 1577, + AArch64_FRINTZv4f16 = 1578, + AArch64_FRINTZv4f32 = 1579, + AArch64_FRINTZv8f16 = 1580, + AArch64_FRSQRTE_ZZ_D = 1581, + AArch64_FRSQRTE_ZZ_H = 1582, + AArch64_FRSQRTE_ZZ_S = 1583, + AArch64_FRSQRTEv1f16 = 1584, + AArch64_FRSQRTEv1i32 = 1585, + AArch64_FRSQRTEv1i64 = 1586, + AArch64_FRSQRTEv2f32 = 1587, + AArch64_FRSQRTEv2f64 = 1588, + AArch64_FRSQRTEv4f16 = 1589, + AArch64_FRSQRTEv4f32 = 1590, + AArch64_FRSQRTEv8f16 = 1591, + AArch64_FRSQRTS16 = 1592, + AArch64_FRSQRTS32 = 1593, + AArch64_FRSQRTS64 = 1594, + AArch64_FRSQRTS_ZZZ_D = 1595, + AArch64_FRSQRTS_ZZZ_H = 1596, + AArch64_FRSQRTS_ZZZ_S = 1597, + AArch64_FRSQRTSv2f32 = 1598, + AArch64_FRSQRTSv2f64 = 1599, + AArch64_FRSQRTSv4f16 = 1600, + AArch64_FRSQRTSv4f32 = 1601, + AArch64_FRSQRTSv8f16 = 1602, + AArch64_FSCALE_ZPmZ_D = 1603, + AArch64_FSCALE_ZPmZ_H = 1604, + AArch64_FSCALE_ZPmZ_S = 1605, + AArch64_FSQRTDr = 1606, + AArch64_FSQRTHr = 1607, + AArch64_FSQRTSr = 1608, + AArch64_FSQRT_ZPmZ_D = 1609, + AArch64_FSQRT_ZPmZ_H = 1610, + AArch64_FSQRT_ZPmZ_S = 1611, + AArch64_FSQRTv2f32 = 1612, + AArch64_FSQRTv2f64 = 1613, + AArch64_FSQRTv4f16 = 1614, + AArch64_FSQRTv4f32 = 1615, + AArch64_FSQRTv8f16 = 1616, + AArch64_FSUBDrr = 1617, + AArch64_FSUBHrr = 1618, + AArch64_FSUBR_ZPmI_D = 1619, + AArch64_FSUBR_ZPmI_H = 1620, + AArch64_FSUBR_ZPmI_S = 1621, + AArch64_FSUBR_ZPmZ_D = 1622, + AArch64_FSUBR_ZPmZ_H = 1623, + AArch64_FSUBR_ZPmZ_S = 1624, + AArch64_FSUBSrr = 1625, + AArch64_FSUB_ZPmI_D = 1626, + AArch64_FSUB_ZPmI_H = 1627, + AArch64_FSUB_ZPmI_S = 1628, + AArch64_FSUB_ZPmZ_D = 1629, + AArch64_FSUB_ZPmZ_H = 1630, + AArch64_FSUB_ZPmZ_S = 1631, + AArch64_FSUB_ZZZ_D = 1632, + AArch64_FSUB_ZZZ_H = 1633, + AArch64_FSUB_ZZZ_S = 1634, + AArch64_FSUBv2f32 = 1635, + AArch64_FSUBv2f64 = 1636, + AArch64_FSUBv4f16 = 1637, + AArch64_FSUBv4f32 = 1638, + AArch64_FSUBv8f16 = 1639, + AArch64_FTMAD_ZZI_D = 1640, + AArch64_FTMAD_ZZI_H = 1641, + AArch64_FTMAD_ZZI_S = 1642, + AArch64_FTSMUL_ZZZ_D = 1643, + AArch64_FTSMUL_ZZZ_H = 1644, + AArch64_FTSMUL_ZZZ_S = 1645, + AArch64_FTSSEL_ZZZ_D = 1646, + AArch64_FTSSEL_ZZZ_H = 1647, + AArch64_FTSSEL_ZZZ_S = 1648, + AArch64_GLD1B_D_IMM_REAL = 1649, + AArch64_GLD1B_D_REAL = 1650, + AArch64_GLD1B_D_SXTW_REAL = 1651, + AArch64_GLD1B_D_UXTW_REAL = 1652, + AArch64_GLD1B_S_IMM_REAL = 1653, + AArch64_GLD1B_S_SXTW_REAL = 1654, + AArch64_GLD1B_S_UXTW_REAL = 1655, + AArch64_GLD1D_IMM_REAL = 1656, + AArch64_GLD1D_REAL = 1657, + AArch64_GLD1D_SCALED_REAL = 1658, + AArch64_GLD1D_SXTW_REAL = 1659, + AArch64_GLD1D_SXTW_SCALED_REAL = 1660, + AArch64_GLD1D_UXTW_REAL = 1661, + AArch64_GLD1D_UXTW_SCALED_REAL = 1662, + AArch64_GLD1H_D_IMM_REAL = 1663, + AArch64_GLD1H_D_REAL = 1664, + AArch64_GLD1H_D_SCALED_REAL = 1665, + AArch64_GLD1H_D_SXTW_REAL = 1666, + AArch64_GLD1H_D_SXTW_SCALED_REAL = 1667, + AArch64_GLD1H_D_UXTW_REAL = 1668, + AArch64_GLD1H_D_UXTW_SCALED_REAL = 1669, + AArch64_GLD1H_S_IMM_REAL = 1670, + AArch64_GLD1H_S_SXTW_REAL = 1671, + AArch64_GLD1H_S_SXTW_SCALED_REAL = 1672, + AArch64_GLD1H_S_UXTW_REAL = 1673, + AArch64_GLD1H_S_UXTW_SCALED_REAL = 1674, + AArch64_GLD1SB_D_IMM_REAL = 1675, + AArch64_GLD1SB_D_REAL = 1676, + AArch64_GLD1SB_D_SXTW_REAL = 1677, + AArch64_GLD1SB_D_UXTW_REAL = 1678, + AArch64_GLD1SB_S_IMM_REAL = 1679, + AArch64_GLD1SB_S_SXTW_REAL = 1680, + AArch64_GLD1SB_S_UXTW_REAL = 1681, + AArch64_GLD1SH_D_IMM_REAL = 1682, + AArch64_GLD1SH_D_REAL = 1683, + AArch64_GLD1SH_D_SCALED_REAL = 1684, + AArch64_GLD1SH_D_SXTW_REAL = 1685, + AArch64_GLD1SH_D_SXTW_SCALED_REAL = 1686, + AArch64_GLD1SH_D_UXTW_REAL = 1687, + AArch64_GLD1SH_D_UXTW_SCALED_REAL = 1688, + AArch64_GLD1SH_S_IMM_REAL = 1689, + AArch64_GLD1SH_S_SXTW_REAL = 1690, + AArch64_GLD1SH_S_SXTW_SCALED_REAL = 1691, + AArch64_GLD1SH_S_UXTW_REAL = 1692, + AArch64_GLD1SH_S_UXTW_SCALED_REAL = 1693, + AArch64_GLD1SW_D_IMM_REAL = 1694, + AArch64_GLD1SW_D_REAL = 1695, + AArch64_GLD1SW_D_SCALED_REAL = 1696, + AArch64_GLD1SW_D_SXTW_REAL = 1697, + AArch64_GLD1SW_D_SXTW_SCALED_REAL = 1698, + AArch64_GLD1SW_D_UXTW_REAL = 1699, + AArch64_GLD1SW_D_UXTW_SCALED_REAL = 1700, + AArch64_GLD1W_D_IMM_REAL = 1701, + AArch64_GLD1W_D_REAL = 1702, + AArch64_GLD1W_D_SCALED_REAL = 1703, + AArch64_GLD1W_D_SXTW_REAL = 1704, + AArch64_GLD1W_D_SXTW_SCALED_REAL = 1705, + AArch64_GLD1W_D_UXTW_REAL = 1706, + AArch64_GLD1W_D_UXTW_SCALED_REAL = 1707, + AArch64_GLD1W_IMM_REAL = 1708, + AArch64_GLD1W_SXTW_REAL = 1709, + AArch64_GLD1W_SXTW_SCALED_REAL = 1710, + AArch64_GLD1W_UXTW_REAL = 1711, + AArch64_GLD1W_UXTW_SCALED_REAL = 1712, + AArch64_GLDFF1B_D_IMM_REAL = 1713, + AArch64_GLDFF1B_D_REAL = 1714, + AArch64_GLDFF1B_D_SXTW_REAL = 1715, + AArch64_GLDFF1B_D_UXTW_REAL = 1716, + AArch64_GLDFF1B_S_IMM_REAL = 1717, + AArch64_GLDFF1B_S_SXTW_REAL = 1718, + AArch64_GLDFF1B_S_UXTW_REAL = 1719, + AArch64_GLDFF1D_IMM_REAL = 1720, + AArch64_GLDFF1D_REAL = 1721, + AArch64_GLDFF1D_SCALED_REAL = 1722, + AArch64_GLDFF1D_SXTW_REAL = 1723, + AArch64_GLDFF1D_SXTW_SCALED_REAL = 1724, + AArch64_GLDFF1D_UXTW_REAL = 1725, + AArch64_GLDFF1D_UXTW_SCALED_REAL = 1726, + AArch64_GLDFF1H_D_IMM_REAL = 1727, + AArch64_GLDFF1H_D_REAL = 1728, + AArch64_GLDFF1H_D_SCALED_REAL = 1729, + AArch64_GLDFF1H_D_SXTW_REAL = 1730, + AArch64_GLDFF1H_D_SXTW_SCALED_REAL = 1731, + AArch64_GLDFF1H_D_UXTW_REAL = 1732, + AArch64_GLDFF1H_D_UXTW_SCALED_REAL = 1733, + AArch64_GLDFF1H_S_IMM_REAL = 1734, + AArch64_GLDFF1H_S_SXTW_REAL = 1735, + AArch64_GLDFF1H_S_SXTW_SCALED_REAL = 1736, + AArch64_GLDFF1H_S_UXTW_REAL = 1737, + AArch64_GLDFF1H_S_UXTW_SCALED_REAL = 1738, + AArch64_GLDFF1SB_D_IMM_REAL = 1739, + AArch64_GLDFF1SB_D_REAL = 1740, + AArch64_GLDFF1SB_D_SXTW_REAL = 1741, + AArch64_GLDFF1SB_D_UXTW_REAL = 1742, + AArch64_GLDFF1SB_S_IMM_REAL = 1743, + AArch64_GLDFF1SB_S_SXTW_REAL = 1744, + AArch64_GLDFF1SB_S_UXTW_REAL = 1745, + AArch64_GLDFF1SH_D_IMM_REAL = 1746, + AArch64_GLDFF1SH_D_REAL = 1747, + AArch64_GLDFF1SH_D_SCALED_REAL = 1748, + AArch64_GLDFF1SH_D_SXTW_REAL = 1749, + AArch64_GLDFF1SH_D_SXTW_SCALED_REAL = 1750, + AArch64_GLDFF1SH_D_UXTW_REAL = 1751, + AArch64_GLDFF1SH_D_UXTW_SCALED_REAL = 1752, + AArch64_GLDFF1SH_S_IMM_REAL = 1753, + AArch64_GLDFF1SH_S_SXTW_REAL = 1754, + AArch64_GLDFF1SH_S_SXTW_SCALED_REAL = 1755, + AArch64_GLDFF1SH_S_UXTW_REAL = 1756, + AArch64_GLDFF1SH_S_UXTW_SCALED_REAL = 1757, + AArch64_GLDFF1SW_D_IMM_REAL = 1758, + AArch64_GLDFF1SW_D_REAL = 1759, + AArch64_GLDFF1SW_D_SCALED_REAL = 1760, + AArch64_GLDFF1SW_D_SXTW_REAL = 1761, + AArch64_GLDFF1SW_D_SXTW_SCALED_REAL = 1762, + AArch64_GLDFF1SW_D_UXTW_REAL = 1763, + AArch64_GLDFF1SW_D_UXTW_SCALED_REAL = 1764, + AArch64_GLDFF1W_D_IMM_REAL = 1765, + AArch64_GLDFF1W_D_REAL = 1766, + AArch64_GLDFF1W_D_SCALED_REAL = 1767, + AArch64_GLDFF1W_D_SXTW_REAL = 1768, + AArch64_GLDFF1W_D_SXTW_SCALED_REAL = 1769, + AArch64_GLDFF1W_D_UXTW_REAL = 1770, + AArch64_GLDFF1W_D_UXTW_SCALED_REAL = 1771, + AArch64_GLDFF1W_IMM_REAL = 1772, + AArch64_GLDFF1W_SXTW_REAL = 1773, + AArch64_GLDFF1W_SXTW_SCALED_REAL = 1774, + AArch64_GLDFF1W_UXTW_REAL = 1775, + AArch64_GLDFF1W_UXTW_SCALED_REAL = 1776, + AArch64_HINT = 1777, + AArch64_HLT = 1778, + AArch64_HVC = 1779, + AArch64_INCB_XPiI = 1780, + AArch64_INCD_XPiI = 1781, + AArch64_INCD_ZPiI = 1782, + AArch64_INCH_XPiI = 1783, + AArch64_INCH_ZPiI = 1784, + AArch64_INCP_XP_B = 1785, + AArch64_INCP_XP_D = 1786, + AArch64_INCP_XP_H = 1787, + AArch64_INCP_XP_S = 1788, + AArch64_INCP_ZP_D = 1789, + AArch64_INCP_ZP_H = 1790, + AArch64_INCP_ZP_S = 1791, + AArch64_INCW_XPiI = 1792, + AArch64_INCW_ZPiI = 1793, + AArch64_INDEX_II_B = 1794, + AArch64_INDEX_II_D = 1795, + AArch64_INDEX_II_H = 1796, + AArch64_INDEX_II_S = 1797, + AArch64_INDEX_IR_B = 1798, + AArch64_INDEX_IR_D = 1799, + AArch64_INDEX_IR_H = 1800, + AArch64_INDEX_IR_S = 1801, + AArch64_INDEX_RI_B = 1802, + AArch64_INDEX_RI_D = 1803, + AArch64_INDEX_RI_H = 1804, + AArch64_INDEX_RI_S = 1805, + AArch64_INDEX_RR_B = 1806, + AArch64_INDEX_RR_D = 1807, + AArch64_INDEX_RR_H = 1808, + AArch64_INDEX_RR_S = 1809, + AArch64_INSR_ZR_B = 1810, + AArch64_INSR_ZR_D = 1811, + AArch64_INSR_ZR_H = 1812, + AArch64_INSR_ZR_S = 1813, + AArch64_INSR_ZV_B = 1814, + AArch64_INSR_ZV_D = 1815, + AArch64_INSR_ZV_H = 1816, + AArch64_INSR_ZV_S = 1817, + AArch64_INSvi16gpr = 1818, + AArch64_INSvi16lane = 1819, + AArch64_INSvi32gpr = 1820, + AArch64_INSvi32lane = 1821, + AArch64_INSvi64gpr = 1822, + AArch64_INSvi64lane = 1823, + AArch64_INSvi8gpr = 1824, + AArch64_INSvi8lane = 1825, + AArch64_ISB = 1826, + AArch64_LASTA_RPZ_B = 1827, + AArch64_LASTA_RPZ_D = 1828, + AArch64_LASTA_RPZ_H = 1829, + AArch64_LASTA_RPZ_S = 1830, + AArch64_LASTA_VPZ_B = 1831, + AArch64_LASTA_VPZ_D = 1832, + AArch64_LASTA_VPZ_H = 1833, + AArch64_LASTA_VPZ_S = 1834, + AArch64_LASTB_RPZ_B = 1835, + AArch64_LASTB_RPZ_D = 1836, + AArch64_LASTB_RPZ_H = 1837, + AArch64_LASTB_RPZ_S = 1838, + AArch64_LASTB_VPZ_B = 1839, + AArch64_LASTB_VPZ_D = 1840, + AArch64_LASTB_VPZ_H = 1841, + AArch64_LASTB_VPZ_S = 1842, + AArch64_LD1B = 1843, + AArch64_LD1B_D = 1844, + AArch64_LD1B_D_IMM_REAL = 1845, + AArch64_LD1B_H = 1846, + AArch64_LD1B_H_IMM_REAL = 1847, + AArch64_LD1B_IMM_REAL = 1848, + AArch64_LD1B_S = 1849, + AArch64_LD1B_S_IMM_REAL = 1850, + AArch64_LD1D = 1851, + AArch64_LD1D_IMM_REAL = 1852, + AArch64_LD1Fourv16b = 1853, + AArch64_LD1Fourv16b_POST = 1854, + AArch64_LD1Fourv1d = 1855, + AArch64_LD1Fourv1d_POST = 1856, + AArch64_LD1Fourv2d = 1857, + AArch64_LD1Fourv2d_POST = 1858, + AArch64_LD1Fourv2s = 1859, + AArch64_LD1Fourv2s_POST = 1860, + AArch64_LD1Fourv4h = 1861, + AArch64_LD1Fourv4h_POST = 1862, + AArch64_LD1Fourv4s = 1863, + AArch64_LD1Fourv4s_POST = 1864, + AArch64_LD1Fourv8b = 1865, + AArch64_LD1Fourv8b_POST = 1866, + AArch64_LD1Fourv8h = 1867, + AArch64_LD1Fourv8h_POST = 1868, + AArch64_LD1H = 1869, + AArch64_LD1H_D = 1870, + AArch64_LD1H_D_IMM_REAL = 1871, + AArch64_LD1H_IMM_REAL = 1872, + AArch64_LD1H_S = 1873, + AArch64_LD1H_S_IMM_REAL = 1874, + AArch64_LD1Onev16b = 1875, + AArch64_LD1Onev16b_POST = 1876, + AArch64_LD1Onev1d = 1877, + AArch64_LD1Onev1d_POST = 1878, + AArch64_LD1Onev2d = 1879, + AArch64_LD1Onev2d_POST = 1880, + AArch64_LD1Onev2s = 1881, + AArch64_LD1Onev2s_POST = 1882, + AArch64_LD1Onev4h = 1883, + AArch64_LD1Onev4h_POST = 1884, + AArch64_LD1Onev4s = 1885, + AArch64_LD1Onev4s_POST = 1886, + AArch64_LD1Onev8b = 1887, + AArch64_LD1Onev8b_POST = 1888, + AArch64_LD1Onev8h = 1889, + AArch64_LD1Onev8h_POST = 1890, + AArch64_LD1RB_D_IMM = 1891, + AArch64_LD1RB_H_IMM = 1892, + AArch64_LD1RB_IMM = 1893, + AArch64_LD1RB_S_IMM = 1894, + AArch64_LD1RD_IMM = 1895, + AArch64_LD1RH_D_IMM = 1896, + AArch64_LD1RH_IMM = 1897, + AArch64_LD1RH_S_IMM = 1898, + AArch64_LD1RQ_B = 1899, + AArch64_LD1RQ_B_IMM = 1900, + AArch64_LD1RQ_D = 1901, + AArch64_LD1RQ_D_IMM = 1902, + AArch64_LD1RQ_H = 1903, + AArch64_LD1RQ_H_IMM = 1904, + AArch64_LD1RQ_W = 1905, + AArch64_LD1RQ_W_IMM = 1906, + AArch64_LD1RSB_D_IMM = 1907, + AArch64_LD1RSB_H_IMM = 1908, + AArch64_LD1RSB_S_IMM = 1909, + AArch64_LD1RSH_D_IMM = 1910, + AArch64_LD1RSH_S_IMM = 1911, + AArch64_LD1RSW_IMM = 1912, + AArch64_LD1RW_D_IMM = 1913, + AArch64_LD1RW_IMM = 1914, + AArch64_LD1Rv16b = 1915, + AArch64_LD1Rv16b_POST = 1916, + AArch64_LD1Rv1d = 1917, + AArch64_LD1Rv1d_POST = 1918, + AArch64_LD1Rv2d = 1919, + AArch64_LD1Rv2d_POST = 1920, + AArch64_LD1Rv2s = 1921, + AArch64_LD1Rv2s_POST = 1922, + AArch64_LD1Rv4h = 1923, + AArch64_LD1Rv4h_POST = 1924, + AArch64_LD1Rv4s = 1925, + AArch64_LD1Rv4s_POST = 1926, + AArch64_LD1Rv8b = 1927, + AArch64_LD1Rv8b_POST = 1928, + AArch64_LD1Rv8h = 1929, + AArch64_LD1Rv8h_POST = 1930, + AArch64_LD1SB_D = 1931, + AArch64_LD1SB_D_IMM_REAL = 1932, + AArch64_LD1SB_H = 1933, + AArch64_LD1SB_H_IMM_REAL = 1934, + AArch64_LD1SB_S = 1935, + AArch64_LD1SB_S_IMM_REAL = 1936, + AArch64_LD1SH_D = 1937, + AArch64_LD1SH_D_IMM_REAL = 1938, + AArch64_LD1SH_S = 1939, + AArch64_LD1SH_S_IMM_REAL = 1940, + AArch64_LD1SW_D = 1941, + AArch64_LD1SW_D_IMM_REAL = 1942, + AArch64_LD1Threev16b = 1943, + AArch64_LD1Threev16b_POST = 1944, + AArch64_LD1Threev1d = 1945, + AArch64_LD1Threev1d_POST = 1946, + AArch64_LD1Threev2d = 1947, + AArch64_LD1Threev2d_POST = 1948, + AArch64_LD1Threev2s = 1949, + AArch64_LD1Threev2s_POST = 1950, + AArch64_LD1Threev4h = 1951, + AArch64_LD1Threev4h_POST = 1952, + AArch64_LD1Threev4s = 1953, + AArch64_LD1Threev4s_POST = 1954, + AArch64_LD1Threev8b = 1955, + AArch64_LD1Threev8b_POST = 1956, + AArch64_LD1Threev8h = 1957, + AArch64_LD1Threev8h_POST = 1958, + AArch64_LD1Twov16b = 1959, + AArch64_LD1Twov16b_POST = 1960, + AArch64_LD1Twov1d = 1961, + AArch64_LD1Twov1d_POST = 1962, + AArch64_LD1Twov2d = 1963, + AArch64_LD1Twov2d_POST = 1964, + AArch64_LD1Twov2s = 1965, + AArch64_LD1Twov2s_POST = 1966, + AArch64_LD1Twov4h = 1967, + AArch64_LD1Twov4h_POST = 1968, + AArch64_LD1Twov4s = 1969, + AArch64_LD1Twov4s_POST = 1970, + AArch64_LD1Twov8b = 1971, + AArch64_LD1Twov8b_POST = 1972, + AArch64_LD1Twov8h = 1973, + AArch64_LD1Twov8h_POST = 1974, + AArch64_LD1W = 1975, + AArch64_LD1W_D = 1976, + AArch64_LD1W_D_IMM_REAL = 1977, + AArch64_LD1W_IMM_REAL = 1978, + AArch64_LD1i16 = 1979, + AArch64_LD1i16_POST = 1980, + AArch64_LD1i32 = 1981, + AArch64_LD1i32_POST = 1982, + AArch64_LD1i64 = 1983, + AArch64_LD1i64_POST = 1984, + AArch64_LD1i8 = 1985, + AArch64_LD1i8_POST = 1986, + AArch64_LD2B = 1987, + AArch64_LD2B_IMM = 1988, + AArch64_LD2D = 1989, + AArch64_LD2D_IMM = 1990, + AArch64_LD2H = 1991, + AArch64_LD2H_IMM = 1992, + AArch64_LD2Rv16b = 1993, + AArch64_LD2Rv16b_POST = 1994, + AArch64_LD2Rv1d = 1995, + AArch64_LD2Rv1d_POST = 1996, + AArch64_LD2Rv2d = 1997, + AArch64_LD2Rv2d_POST = 1998, + AArch64_LD2Rv2s = 1999, + AArch64_LD2Rv2s_POST = 2000, + AArch64_LD2Rv4h = 2001, + AArch64_LD2Rv4h_POST = 2002, + AArch64_LD2Rv4s = 2003, + AArch64_LD2Rv4s_POST = 2004, + AArch64_LD2Rv8b = 2005, + AArch64_LD2Rv8b_POST = 2006, + AArch64_LD2Rv8h = 2007, + AArch64_LD2Rv8h_POST = 2008, + AArch64_LD2Twov16b = 2009, + AArch64_LD2Twov16b_POST = 2010, + AArch64_LD2Twov2d = 2011, + AArch64_LD2Twov2d_POST = 2012, + AArch64_LD2Twov2s = 2013, + AArch64_LD2Twov2s_POST = 2014, + AArch64_LD2Twov4h = 2015, + AArch64_LD2Twov4h_POST = 2016, + AArch64_LD2Twov4s = 2017, + AArch64_LD2Twov4s_POST = 2018, + AArch64_LD2Twov8b = 2019, + AArch64_LD2Twov8b_POST = 2020, + AArch64_LD2Twov8h = 2021, + AArch64_LD2Twov8h_POST = 2022, + AArch64_LD2W = 2023, + AArch64_LD2W_IMM = 2024, + AArch64_LD2i16 = 2025, + AArch64_LD2i16_POST = 2026, + AArch64_LD2i32 = 2027, + AArch64_LD2i32_POST = 2028, + AArch64_LD2i64 = 2029, + AArch64_LD2i64_POST = 2030, + AArch64_LD2i8 = 2031, + AArch64_LD2i8_POST = 2032, + AArch64_LD3B = 2033, + AArch64_LD3B_IMM = 2034, + AArch64_LD3D = 2035, + AArch64_LD3D_IMM = 2036, + AArch64_LD3H = 2037, + AArch64_LD3H_IMM = 2038, + AArch64_LD3Rv16b = 2039, + AArch64_LD3Rv16b_POST = 2040, + AArch64_LD3Rv1d = 2041, + AArch64_LD3Rv1d_POST = 2042, + AArch64_LD3Rv2d = 2043, + AArch64_LD3Rv2d_POST = 2044, + AArch64_LD3Rv2s = 2045, + AArch64_LD3Rv2s_POST = 2046, + AArch64_LD3Rv4h = 2047, + AArch64_LD3Rv4h_POST = 2048, + AArch64_LD3Rv4s = 2049, + AArch64_LD3Rv4s_POST = 2050, + AArch64_LD3Rv8b = 2051, + AArch64_LD3Rv8b_POST = 2052, + AArch64_LD3Rv8h = 2053, + AArch64_LD3Rv8h_POST = 2054, + AArch64_LD3Threev16b = 2055, + AArch64_LD3Threev16b_POST = 2056, + AArch64_LD3Threev2d = 2057, + AArch64_LD3Threev2d_POST = 2058, + AArch64_LD3Threev2s = 2059, + AArch64_LD3Threev2s_POST = 2060, + AArch64_LD3Threev4h = 2061, + AArch64_LD3Threev4h_POST = 2062, + AArch64_LD3Threev4s = 2063, + AArch64_LD3Threev4s_POST = 2064, + AArch64_LD3Threev8b = 2065, + AArch64_LD3Threev8b_POST = 2066, + AArch64_LD3Threev8h = 2067, + AArch64_LD3Threev8h_POST = 2068, + AArch64_LD3W = 2069, + AArch64_LD3W_IMM = 2070, + AArch64_LD3i16 = 2071, + AArch64_LD3i16_POST = 2072, + AArch64_LD3i32 = 2073, + AArch64_LD3i32_POST = 2074, + AArch64_LD3i64 = 2075, + AArch64_LD3i64_POST = 2076, + AArch64_LD3i8 = 2077, + AArch64_LD3i8_POST = 2078, + AArch64_LD4B = 2079, + AArch64_LD4B_IMM = 2080, + AArch64_LD4D = 2081, + AArch64_LD4D_IMM = 2082, + AArch64_LD4Fourv16b = 2083, + AArch64_LD4Fourv16b_POST = 2084, + AArch64_LD4Fourv2d = 2085, + AArch64_LD4Fourv2d_POST = 2086, + AArch64_LD4Fourv2s = 2087, + AArch64_LD4Fourv2s_POST = 2088, + AArch64_LD4Fourv4h = 2089, + AArch64_LD4Fourv4h_POST = 2090, + AArch64_LD4Fourv4s = 2091, + AArch64_LD4Fourv4s_POST = 2092, + AArch64_LD4Fourv8b = 2093, + AArch64_LD4Fourv8b_POST = 2094, + AArch64_LD4Fourv8h = 2095, + AArch64_LD4Fourv8h_POST = 2096, + AArch64_LD4H = 2097, + AArch64_LD4H_IMM = 2098, + AArch64_LD4Rv16b = 2099, + AArch64_LD4Rv16b_POST = 2100, + AArch64_LD4Rv1d = 2101, + AArch64_LD4Rv1d_POST = 2102, + AArch64_LD4Rv2d = 2103, + AArch64_LD4Rv2d_POST = 2104, + AArch64_LD4Rv2s = 2105, + AArch64_LD4Rv2s_POST = 2106, + AArch64_LD4Rv4h = 2107, + AArch64_LD4Rv4h_POST = 2108, + AArch64_LD4Rv4s = 2109, + AArch64_LD4Rv4s_POST = 2110, + AArch64_LD4Rv8b = 2111, + AArch64_LD4Rv8b_POST = 2112, + AArch64_LD4Rv8h = 2113, + AArch64_LD4Rv8h_POST = 2114, + AArch64_LD4W = 2115, + AArch64_LD4W_IMM = 2116, + AArch64_LD4i16 = 2117, + AArch64_LD4i16_POST = 2118, + AArch64_LD4i32 = 2119, + AArch64_LD4i32_POST = 2120, + AArch64_LD4i64 = 2121, + AArch64_LD4i64_POST = 2122, + AArch64_LD4i8 = 2123, + AArch64_LD4i8_POST = 2124, + AArch64_LDADDAB = 2125, + AArch64_LDADDAH = 2126, + AArch64_LDADDALB = 2127, + AArch64_LDADDALH = 2128, + AArch64_LDADDALW = 2129, + AArch64_LDADDALX = 2130, + AArch64_LDADDAW = 2131, + AArch64_LDADDAX = 2132, + AArch64_LDADDB = 2133, + AArch64_LDADDH = 2134, + AArch64_LDADDLB = 2135, + AArch64_LDADDLH = 2136, + AArch64_LDADDLW = 2137, + AArch64_LDADDLX = 2138, + AArch64_LDADDW = 2139, + AArch64_LDADDX = 2140, + AArch64_LDAPRB = 2141, + AArch64_LDAPRH = 2142, + AArch64_LDAPRW = 2143, + AArch64_LDAPRX = 2144, + AArch64_LDAPURBi = 2145, + AArch64_LDAPURHi = 2146, + AArch64_LDAPURSBWi = 2147, + AArch64_LDAPURSBXi = 2148, + AArch64_LDAPURSHWi = 2149, + AArch64_LDAPURSHXi = 2150, + AArch64_LDAPURSWi = 2151, + AArch64_LDAPURXi = 2152, + AArch64_LDAPURi = 2153, + AArch64_LDARB = 2154, + AArch64_LDARH = 2155, + AArch64_LDARW = 2156, + AArch64_LDARX = 2157, + AArch64_LDAXPW = 2158, + AArch64_LDAXPX = 2159, + AArch64_LDAXRB = 2160, + AArch64_LDAXRH = 2161, + AArch64_LDAXRW = 2162, + AArch64_LDAXRX = 2163, + AArch64_LDCLRAB = 2164, + AArch64_LDCLRAH = 2165, + AArch64_LDCLRALB = 2166, + AArch64_LDCLRALH = 2167, + AArch64_LDCLRALW = 2168, + AArch64_LDCLRALX = 2169, + AArch64_LDCLRAW = 2170, + AArch64_LDCLRAX = 2171, + AArch64_LDCLRB = 2172, + AArch64_LDCLRH = 2173, + AArch64_LDCLRLB = 2174, + AArch64_LDCLRLH = 2175, + AArch64_LDCLRLW = 2176, + AArch64_LDCLRLX = 2177, + AArch64_LDCLRW = 2178, + AArch64_LDCLRX = 2179, + AArch64_LDEORAB = 2180, + AArch64_LDEORAH = 2181, + AArch64_LDEORALB = 2182, + AArch64_LDEORALH = 2183, + AArch64_LDEORALW = 2184, + AArch64_LDEORALX = 2185, + AArch64_LDEORAW = 2186, + AArch64_LDEORAX = 2187, + AArch64_LDEORB = 2188, + AArch64_LDEORH = 2189, + AArch64_LDEORLB = 2190, + AArch64_LDEORLH = 2191, + AArch64_LDEORLW = 2192, + AArch64_LDEORLX = 2193, + AArch64_LDEORW = 2194, + AArch64_LDEORX = 2195, + AArch64_LDFF1B_D_REAL = 2196, + AArch64_LDFF1B_H_REAL = 2197, + AArch64_LDFF1B_REAL = 2198, + AArch64_LDFF1B_S_REAL = 2199, + AArch64_LDFF1D_REAL = 2200, + AArch64_LDFF1H_D_REAL = 2201, + AArch64_LDFF1H_REAL = 2202, + AArch64_LDFF1H_S_REAL = 2203, + AArch64_LDFF1SB_D_REAL = 2204, + AArch64_LDFF1SB_H_REAL = 2205, + AArch64_LDFF1SB_S_REAL = 2206, + AArch64_LDFF1SH_D_REAL = 2207, + AArch64_LDFF1SH_S_REAL = 2208, + AArch64_LDFF1SW_D_REAL = 2209, + AArch64_LDFF1W_D_REAL = 2210, + AArch64_LDFF1W_REAL = 2211, + AArch64_LDLARB = 2212, + AArch64_LDLARH = 2213, + AArch64_LDLARW = 2214, + AArch64_LDLARX = 2215, + AArch64_LDNF1B_D_IMM_REAL = 2216, + AArch64_LDNF1B_H_IMM_REAL = 2217, + AArch64_LDNF1B_IMM_REAL = 2218, + AArch64_LDNF1B_S_IMM_REAL = 2219, + AArch64_LDNF1D_IMM_REAL = 2220, + AArch64_LDNF1H_D_IMM_REAL = 2221, + AArch64_LDNF1H_IMM_REAL = 2222, + AArch64_LDNF1H_S_IMM_REAL = 2223, + AArch64_LDNF1SB_D_IMM_REAL = 2224, + AArch64_LDNF1SB_H_IMM_REAL = 2225, + AArch64_LDNF1SB_S_IMM_REAL = 2226, + AArch64_LDNF1SH_D_IMM_REAL = 2227, + AArch64_LDNF1SH_S_IMM_REAL = 2228, + AArch64_LDNF1SW_D_IMM_REAL = 2229, + AArch64_LDNF1W_D_IMM_REAL = 2230, + AArch64_LDNF1W_IMM_REAL = 2231, + AArch64_LDNPDi = 2232, + AArch64_LDNPQi = 2233, + AArch64_LDNPSi = 2234, + AArch64_LDNPWi = 2235, + AArch64_LDNPXi = 2236, + AArch64_LDNT1B_ZRI = 2237, + AArch64_LDNT1B_ZRR = 2238, + AArch64_LDNT1D_ZRI = 2239, + AArch64_LDNT1D_ZRR = 2240, + AArch64_LDNT1H_ZRI = 2241, + AArch64_LDNT1H_ZRR = 2242, + AArch64_LDNT1W_ZRI = 2243, + AArch64_LDNT1W_ZRR = 2244, + AArch64_LDPDi = 2245, + AArch64_LDPDpost = 2246, + AArch64_LDPDpre = 2247, + AArch64_LDPQi = 2248, + AArch64_LDPQpost = 2249, + AArch64_LDPQpre = 2250, + AArch64_LDPSWi = 2251, + AArch64_LDPSWpost = 2252, + AArch64_LDPSWpre = 2253, + AArch64_LDPSi = 2254, + AArch64_LDPSpost = 2255, + AArch64_LDPSpre = 2256, + AArch64_LDPWi = 2257, + AArch64_LDPWpost = 2258, + AArch64_LDPWpre = 2259, + AArch64_LDPXi = 2260, + AArch64_LDPXpost = 2261, + AArch64_LDPXpre = 2262, + AArch64_LDRAAindexed = 2263, + AArch64_LDRAAwriteback = 2264, + AArch64_LDRABindexed = 2265, + AArch64_LDRABwriteback = 2266, + AArch64_LDRBBpost = 2267, + AArch64_LDRBBpre = 2268, + AArch64_LDRBBroW = 2269, + AArch64_LDRBBroX = 2270, + AArch64_LDRBBui = 2271, + AArch64_LDRBpost = 2272, + AArch64_LDRBpre = 2273, + AArch64_LDRBroW = 2274, + AArch64_LDRBroX = 2275, + AArch64_LDRBui = 2276, + AArch64_LDRDl = 2277, + AArch64_LDRDpost = 2278, + AArch64_LDRDpre = 2279, + AArch64_LDRDroW = 2280, + AArch64_LDRDroX = 2281, + AArch64_LDRDui = 2282, + AArch64_LDRHHpost = 2283, + AArch64_LDRHHpre = 2284, + AArch64_LDRHHroW = 2285, + AArch64_LDRHHroX = 2286, + AArch64_LDRHHui = 2287, + AArch64_LDRHpost = 2288, + AArch64_LDRHpre = 2289, + AArch64_LDRHroW = 2290, + AArch64_LDRHroX = 2291, + AArch64_LDRHui = 2292, + AArch64_LDRQl = 2293, + AArch64_LDRQpost = 2294, + AArch64_LDRQpre = 2295, + AArch64_LDRQroW = 2296, + AArch64_LDRQroX = 2297, + AArch64_LDRQui = 2298, + AArch64_LDRSBWpost = 2299, + AArch64_LDRSBWpre = 2300, + AArch64_LDRSBWroW = 2301, + AArch64_LDRSBWroX = 2302, + AArch64_LDRSBWui = 2303, + AArch64_LDRSBXpost = 2304, + AArch64_LDRSBXpre = 2305, + AArch64_LDRSBXroW = 2306, + AArch64_LDRSBXroX = 2307, + AArch64_LDRSBXui = 2308, + AArch64_LDRSHWpost = 2309, + AArch64_LDRSHWpre = 2310, + AArch64_LDRSHWroW = 2311, + AArch64_LDRSHWroX = 2312, + AArch64_LDRSHWui = 2313, + AArch64_LDRSHXpost = 2314, + AArch64_LDRSHXpre = 2315, + AArch64_LDRSHXroW = 2316, + AArch64_LDRSHXroX = 2317, + AArch64_LDRSHXui = 2318, + AArch64_LDRSWl = 2319, + AArch64_LDRSWpost = 2320, + AArch64_LDRSWpre = 2321, + AArch64_LDRSWroW = 2322, + AArch64_LDRSWroX = 2323, + AArch64_LDRSWui = 2324, + AArch64_LDRSl = 2325, + AArch64_LDRSpost = 2326, + AArch64_LDRSpre = 2327, + AArch64_LDRSroW = 2328, + AArch64_LDRSroX = 2329, + AArch64_LDRSui = 2330, + AArch64_LDRWl = 2331, + AArch64_LDRWpost = 2332, + AArch64_LDRWpre = 2333, + AArch64_LDRWroW = 2334, + AArch64_LDRWroX = 2335, + AArch64_LDRWui = 2336, + AArch64_LDRXl = 2337, + AArch64_LDRXpost = 2338, + AArch64_LDRXpre = 2339, + AArch64_LDRXroW = 2340, + AArch64_LDRXroX = 2341, + AArch64_LDRXui = 2342, + AArch64_LDR_PXI = 2343, + AArch64_LDR_ZXI = 2344, + AArch64_LDSETAB = 2345, + AArch64_LDSETAH = 2346, + AArch64_LDSETALB = 2347, + AArch64_LDSETALH = 2348, + AArch64_LDSETALW = 2349, + AArch64_LDSETALX = 2350, + AArch64_LDSETAW = 2351, + AArch64_LDSETAX = 2352, + AArch64_LDSETB = 2353, + AArch64_LDSETH = 2354, + AArch64_LDSETLB = 2355, + AArch64_LDSETLH = 2356, + AArch64_LDSETLW = 2357, + AArch64_LDSETLX = 2358, + AArch64_LDSETW = 2359, + AArch64_LDSETX = 2360, + AArch64_LDSMAXAB = 2361, + AArch64_LDSMAXAH = 2362, + AArch64_LDSMAXALB = 2363, + AArch64_LDSMAXALH = 2364, + AArch64_LDSMAXALW = 2365, + AArch64_LDSMAXALX = 2366, + AArch64_LDSMAXAW = 2367, + AArch64_LDSMAXAX = 2368, + AArch64_LDSMAXB = 2369, + AArch64_LDSMAXH = 2370, + AArch64_LDSMAXLB = 2371, + AArch64_LDSMAXLH = 2372, + AArch64_LDSMAXLW = 2373, + AArch64_LDSMAXLX = 2374, + AArch64_LDSMAXW = 2375, + AArch64_LDSMAXX = 2376, + AArch64_LDSMINAB = 2377, + AArch64_LDSMINAH = 2378, + AArch64_LDSMINALB = 2379, + AArch64_LDSMINALH = 2380, + AArch64_LDSMINALW = 2381, + AArch64_LDSMINALX = 2382, + AArch64_LDSMINAW = 2383, + AArch64_LDSMINAX = 2384, + AArch64_LDSMINB = 2385, + AArch64_LDSMINH = 2386, + AArch64_LDSMINLB = 2387, + AArch64_LDSMINLH = 2388, + AArch64_LDSMINLW = 2389, + AArch64_LDSMINLX = 2390, + AArch64_LDSMINW = 2391, + AArch64_LDSMINX = 2392, + AArch64_LDTRBi = 2393, + AArch64_LDTRHi = 2394, + AArch64_LDTRSBWi = 2395, + AArch64_LDTRSBXi = 2396, + AArch64_LDTRSHWi = 2397, + AArch64_LDTRSHXi = 2398, + AArch64_LDTRSWi = 2399, + AArch64_LDTRWi = 2400, + AArch64_LDTRXi = 2401, + AArch64_LDUMAXAB = 2402, + AArch64_LDUMAXAH = 2403, + AArch64_LDUMAXALB = 2404, + AArch64_LDUMAXALH = 2405, + AArch64_LDUMAXALW = 2406, + AArch64_LDUMAXALX = 2407, + AArch64_LDUMAXAW = 2408, + AArch64_LDUMAXAX = 2409, + AArch64_LDUMAXB = 2410, + AArch64_LDUMAXH = 2411, + AArch64_LDUMAXLB = 2412, + AArch64_LDUMAXLH = 2413, + AArch64_LDUMAXLW = 2414, + AArch64_LDUMAXLX = 2415, + AArch64_LDUMAXW = 2416, + AArch64_LDUMAXX = 2417, + AArch64_LDUMINAB = 2418, + AArch64_LDUMINAH = 2419, + AArch64_LDUMINALB = 2420, + AArch64_LDUMINALH = 2421, + AArch64_LDUMINALW = 2422, + AArch64_LDUMINALX = 2423, + AArch64_LDUMINAW = 2424, + AArch64_LDUMINAX = 2425, + AArch64_LDUMINB = 2426, + AArch64_LDUMINH = 2427, + AArch64_LDUMINLB = 2428, + AArch64_LDUMINLH = 2429, + AArch64_LDUMINLW = 2430, + AArch64_LDUMINLX = 2431, + AArch64_LDUMINW = 2432, + AArch64_LDUMINX = 2433, + AArch64_LDURBBi = 2434, + AArch64_LDURBi = 2435, + AArch64_LDURDi = 2436, + AArch64_LDURHHi = 2437, + AArch64_LDURHi = 2438, + AArch64_LDURQi = 2439, + AArch64_LDURSBWi = 2440, + AArch64_LDURSBXi = 2441, + AArch64_LDURSHWi = 2442, + AArch64_LDURSHXi = 2443, + AArch64_LDURSWi = 2444, + AArch64_LDURSi = 2445, + AArch64_LDURWi = 2446, + AArch64_LDURXi = 2447, + AArch64_LDXPW = 2448, + AArch64_LDXPX = 2449, + AArch64_LDXRB = 2450, + AArch64_LDXRH = 2451, + AArch64_LDXRW = 2452, + AArch64_LDXRX = 2453, + AArch64_LOADgot = 2454, + AArch64_LSLR_ZPmZ_B = 2455, + AArch64_LSLR_ZPmZ_D = 2456, + AArch64_LSLR_ZPmZ_H = 2457, + AArch64_LSLR_ZPmZ_S = 2458, + AArch64_LSLVWr = 2459, + AArch64_LSLVXr = 2460, + AArch64_LSL_WIDE_ZPmZ_B = 2461, + AArch64_LSL_WIDE_ZPmZ_H = 2462, + AArch64_LSL_WIDE_ZPmZ_S = 2463, + AArch64_LSL_WIDE_ZZZ_B = 2464, + AArch64_LSL_WIDE_ZZZ_H = 2465, + AArch64_LSL_WIDE_ZZZ_S = 2466, + AArch64_LSL_ZPmI_B = 2467, + AArch64_LSL_ZPmI_D = 2468, + AArch64_LSL_ZPmI_H = 2469, + AArch64_LSL_ZPmI_S = 2470, + AArch64_LSL_ZPmZ_B = 2471, + AArch64_LSL_ZPmZ_D = 2472, + AArch64_LSL_ZPmZ_H = 2473, + AArch64_LSL_ZPmZ_S = 2474, + AArch64_LSL_ZZI_B = 2475, + AArch64_LSL_ZZI_D = 2476, + AArch64_LSL_ZZI_H = 2477, + AArch64_LSL_ZZI_S = 2478, + AArch64_LSRR_ZPmZ_B = 2479, + AArch64_LSRR_ZPmZ_D = 2480, + AArch64_LSRR_ZPmZ_H = 2481, + AArch64_LSRR_ZPmZ_S = 2482, + AArch64_LSRVWr = 2483, + AArch64_LSRVXr = 2484, + AArch64_LSR_WIDE_ZPmZ_B = 2485, + AArch64_LSR_WIDE_ZPmZ_H = 2486, + AArch64_LSR_WIDE_ZPmZ_S = 2487, + AArch64_LSR_WIDE_ZZZ_B = 2488, + AArch64_LSR_WIDE_ZZZ_H = 2489, + AArch64_LSR_WIDE_ZZZ_S = 2490, + AArch64_LSR_ZPmI_B = 2491, + AArch64_LSR_ZPmI_D = 2492, + AArch64_LSR_ZPmI_H = 2493, + AArch64_LSR_ZPmI_S = 2494, + AArch64_LSR_ZPmZ_B = 2495, + AArch64_LSR_ZPmZ_D = 2496, + AArch64_LSR_ZPmZ_H = 2497, + AArch64_LSR_ZPmZ_S = 2498, + AArch64_LSR_ZZI_B = 2499, + AArch64_LSR_ZZI_D = 2500, + AArch64_LSR_ZZI_H = 2501, + AArch64_LSR_ZZI_S = 2502, + AArch64_MADDWrrr = 2503, + AArch64_MADDXrrr = 2504, + AArch64_MAD_ZPmZZ_B = 2505, + AArch64_MAD_ZPmZZ_D = 2506, + AArch64_MAD_ZPmZZ_H = 2507, + AArch64_MAD_ZPmZZ_S = 2508, + AArch64_MLA_ZPmZZ_B = 2509, + AArch64_MLA_ZPmZZ_D = 2510, + AArch64_MLA_ZPmZZ_H = 2511, + AArch64_MLA_ZPmZZ_S = 2512, + AArch64_MLAv16i8 = 2513, + AArch64_MLAv2i32 = 2514, + AArch64_MLAv2i32_indexed = 2515, + AArch64_MLAv4i16 = 2516, + AArch64_MLAv4i16_indexed = 2517, + AArch64_MLAv4i32 = 2518, + AArch64_MLAv4i32_indexed = 2519, + AArch64_MLAv8i16 = 2520, + AArch64_MLAv8i16_indexed = 2521, + AArch64_MLAv8i8 = 2522, + AArch64_MLS_ZPmZZ_B = 2523, + AArch64_MLS_ZPmZZ_D = 2524, + AArch64_MLS_ZPmZZ_H = 2525, + AArch64_MLS_ZPmZZ_S = 2526, + AArch64_MLSv16i8 = 2527, + AArch64_MLSv2i32 = 2528, + AArch64_MLSv2i32_indexed = 2529, + AArch64_MLSv4i16 = 2530, + AArch64_MLSv4i16_indexed = 2531, + AArch64_MLSv4i32 = 2532, + AArch64_MLSv4i32_indexed = 2533, + AArch64_MLSv8i16 = 2534, + AArch64_MLSv8i16_indexed = 2535, + AArch64_MLSv8i8 = 2536, + AArch64_MOVID = 2537, + AArch64_MOVIv16b_ns = 2538, + AArch64_MOVIv2d_ns = 2539, + AArch64_MOVIv2i32 = 2540, + AArch64_MOVIv2s_msl = 2541, + AArch64_MOVIv4i16 = 2542, + AArch64_MOVIv4i32 = 2543, + AArch64_MOVIv4s_msl = 2544, + AArch64_MOVIv8b_ns = 2545, + AArch64_MOVIv8i16 = 2546, + AArch64_MOVKWi = 2547, + AArch64_MOVKXi = 2548, + AArch64_MOVNWi = 2549, + AArch64_MOVNXi = 2550, + AArch64_MOVPRFX_ZPmZ_B = 2551, + AArch64_MOVPRFX_ZPmZ_D = 2552, + AArch64_MOVPRFX_ZPmZ_H = 2553, + AArch64_MOVPRFX_ZPmZ_S = 2554, + AArch64_MOVPRFX_ZPzZ_B = 2555, + AArch64_MOVPRFX_ZPzZ_D = 2556, + AArch64_MOVPRFX_ZPzZ_H = 2557, + AArch64_MOVPRFX_ZPzZ_S = 2558, + AArch64_MOVPRFX_ZZ = 2559, + AArch64_MOVZWi = 2560, + AArch64_MOVZXi = 2561, + AArch64_MOVaddr = 2562, + AArch64_MOVaddrBA = 2563, + AArch64_MOVaddrCP = 2564, + AArch64_MOVaddrEXT = 2565, + AArch64_MOVaddrJT = 2566, + AArch64_MOVaddrTLS = 2567, + AArch64_MOVbaseTLS = 2568, + AArch64_MOVi32imm = 2569, + AArch64_MOVi64imm = 2570, + AArch64_MRS = 2571, + AArch64_MSB_ZPmZZ_B = 2572, + AArch64_MSB_ZPmZZ_D = 2573, + AArch64_MSB_ZPmZZ_H = 2574, + AArch64_MSB_ZPmZZ_S = 2575, + AArch64_MSR = 2576, + AArch64_MSRpstateImm1 = 2577, + AArch64_MSRpstateImm4 = 2578, + AArch64_MSUBWrrr = 2579, + AArch64_MSUBXrrr = 2580, + AArch64_MUL_ZI_B = 2581, + AArch64_MUL_ZI_D = 2582, + AArch64_MUL_ZI_H = 2583, + AArch64_MUL_ZI_S = 2584, + AArch64_MUL_ZPmZ_B = 2585, + AArch64_MUL_ZPmZ_D = 2586, + AArch64_MUL_ZPmZ_H = 2587, + AArch64_MUL_ZPmZ_S = 2588, + AArch64_MULv16i8 = 2589, + AArch64_MULv2i32 = 2590, + AArch64_MULv2i32_indexed = 2591, + AArch64_MULv4i16 = 2592, + AArch64_MULv4i16_indexed = 2593, + AArch64_MULv4i32 = 2594, + AArch64_MULv4i32_indexed = 2595, + AArch64_MULv8i16 = 2596, + AArch64_MULv8i16_indexed = 2597, + AArch64_MULv8i8 = 2598, + AArch64_MVNIv2i32 = 2599, + AArch64_MVNIv2s_msl = 2600, + AArch64_MVNIv4i16 = 2601, + AArch64_MVNIv4i32 = 2602, + AArch64_MVNIv4s_msl = 2603, + AArch64_MVNIv8i16 = 2604, + AArch64_NANDS_PPzPP = 2605, + AArch64_NAND_PPzPP = 2606, + AArch64_NEG_ZPmZ_B = 2607, + AArch64_NEG_ZPmZ_D = 2608, + AArch64_NEG_ZPmZ_H = 2609, + AArch64_NEG_ZPmZ_S = 2610, + AArch64_NEGv16i8 = 2611, + AArch64_NEGv1i64 = 2612, + AArch64_NEGv2i32 = 2613, + AArch64_NEGv2i64 = 2614, + AArch64_NEGv4i16 = 2615, + AArch64_NEGv4i32 = 2616, + AArch64_NEGv8i16 = 2617, + AArch64_NEGv8i8 = 2618, + AArch64_NORS_PPzPP = 2619, + AArch64_NOR_PPzPP = 2620, + AArch64_NOT_ZPmZ_B = 2621, + AArch64_NOT_ZPmZ_D = 2622, + AArch64_NOT_ZPmZ_H = 2623, + AArch64_NOT_ZPmZ_S = 2624, + AArch64_NOTv16i8 = 2625, + AArch64_NOTv8i8 = 2626, + AArch64_ORNS_PPzPP = 2627, + AArch64_ORNWrr = 2628, + AArch64_ORNWrs = 2629, + AArch64_ORNXrr = 2630, + AArch64_ORNXrs = 2631, + AArch64_ORN_PPzPP = 2632, + AArch64_ORNv16i8 = 2633, + AArch64_ORNv8i8 = 2634, + AArch64_ORRS_PPzPP = 2635, + AArch64_ORRWri = 2636, + AArch64_ORRWrr = 2637, + AArch64_ORRWrs = 2638, + AArch64_ORRXri = 2639, + AArch64_ORRXrr = 2640, + AArch64_ORRXrs = 2641, + AArch64_ORR_PPzPP = 2642, + AArch64_ORR_ZI = 2643, + AArch64_ORR_ZPmZ_B = 2644, + AArch64_ORR_ZPmZ_D = 2645, + AArch64_ORR_ZPmZ_H = 2646, + AArch64_ORR_ZPmZ_S = 2647, + AArch64_ORR_ZZZ = 2648, + AArch64_ORRv16i8 = 2649, + AArch64_ORRv2i32 = 2650, + AArch64_ORRv4i16 = 2651, + AArch64_ORRv4i32 = 2652, + AArch64_ORRv8i16 = 2653, + AArch64_ORRv8i8 = 2654, + AArch64_ORV_VPZ_B = 2655, + AArch64_ORV_VPZ_D = 2656, + AArch64_ORV_VPZ_H = 2657, + AArch64_ORV_VPZ_S = 2658, + AArch64_PACDA = 2659, + AArch64_PACDB = 2660, + AArch64_PACDZA = 2661, + AArch64_PACDZB = 2662, + AArch64_PACGA = 2663, + AArch64_PACIA = 2664, + AArch64_PACIA1716 = 2665, + AArch64_PACIASP = 2666, + AArch64_PACIAZ = 2667, + AArch64_PACIB = 2668, + AArch64_PACIB1716 = 2669, + AArch64_PACIBSP = 2670, + AArch64_PACIBZ = 2671, + AArch64_PACIZA = 2672, + AArch64_PACIZB = 2673, + AArch64_PFALSE = 2674, + AArch64_PMULLv16i8 = 2675, + AArch64_PMULLv1i64 = 2676, + AArch64_PMULLv2i64 = 2677, + AArch64_PMULLv8i8 = 2678, + AArch64_PMULv16i8 = 2679, + AArch64_PMULv8i8 = 2680, + AArch64_PNEXT_B = 2681, + AArch64_PNEXT_D = 2682, + AArch64_PNEXT_H = 2683, + AArch64_PNEXT_S = 2684, + AArch64_PRFB_D_PZI = 2685, + AArch64_PRFB_D_SCALED = 2686, + AArch64_PRFB_D_SXTW_SCALED = 2687, + AArch64_PRFB_D_UXTW_SCALED = 2688, + AArch64_PRFB_PRI = 2689, + AArch64_PRFB_PRR = 2690, + AArch64_PRFB_S_PZI = 2691, + AArch64_PRFB_S_SXTW_SCALED = 2692, + AArch64_PRFB_S_UXTW_SCALED = 2693, + AArch64_PRFD_D_PZI = 2694, + AArch64_PRFD_D_SCALED = 2695, + AArch64_PRFD_D_SXTW_SCALED = 2696, + AArch64_PRFD_D_UXTW_SCALED = 2697, + AArch64_PRFD_PRI = 2698, + AArch64_PRFD_PRR = 2699, + AArch64_PRFD_S_PZI = 2700, + AArch64_PRFD_S_SXTW_SCALED = 2701, + AArch64_PRFD_S_UXTW_SCALED = 2702, + AArch64_PRFH_D_PZI = 2703, + AArch64_PRFH_D_SCALED = 2704, + AArch64_PRFH_D_SXTW_SCALED = 2705, + AArch64_PRFH_D_UXTW_SCALED = 2706, + AArch64_PRFH_PRI = 2707, + AArch64_PRFH_PRR = 2708, + AArch64_PRFH_S_PZI = 2709, + AArch64_PRFH_S_SXTW_SCALED = 2710, + AArch64_PRFH_S_UXTW_SCALED = 2711, + AArch64_PRFMl = 2712, + AArch64_PRFMroW = 2713, + AArch64_PRFMroX = 2714, + AArch64_PRFMui = 2715, + AArch64_PRFS_PRR = 2716, + AArch64_PRFUMi = 2717, + AArch64_PRFW_D_PZI = 2718, + AArch64_PRFW_D_SCALED = 2719, + AArch64_PRFW_D_SXTW_SCALED = 2720, + AArch64_PRFW_D_UXTW_SCALED = 2721, + AArch64_PRFW_PRI = 2722, + AArch64_PRFW_S_PZI = 2723, + AArch64_PRFW_S_SXTW_SCALED = 2724, + AArch64_PRFW_S_UXTW_SCALED = 2725, + AArch64_PTEST_PP = 2726, + AArch64_PTRUES_B = 2727, + AArch64_PTRUES_D = 2728, + AArch64_PTRUES_H = 2729, + AArch64_PTRUES_S = 2730, + AArch64_PTRUE_B = 2731, + AArch64_PTRUE_D = 2732, + AArch64_PTRUE_H = 2733, + AArch64_PTRUE_S = 2734, + AArch64_PUNPKHI_PP = 2735, + AArch64_PUNPKLO_PP = 2736, + AArch64_RADDHNv2i64_v2i32 = 2737, + AArch64_RADDHNv2i64_v4i32 = 2738, + AArch64_RADDHNv4i32_v4i16 = 2739, + AArch64_RADDHNv4i32_v8i16 = 2740, + AArch64_RADDHNv8i16_v16i8 = 2741, + AArch64_RADDHNv8i16_v8i8 = 2742, + AArch64_RAX1 = 2743, + AArch64_RBITWr = 2744, + AArch64_RBITXr = 2745, + AArch64_RBIT_ZPmZ_B = 2746, + AArch64_RBIT_ZPmZ_D = 2747, + AArch64_RBIT_ZPmZ_H = 2748, + AArch64_RBIT_ZPmZ_S = 2749, + AArch64_RBITv16i8 = 2750, + AArch64_RBITv8i8 = 2751, + AArch64_RDFFRS_PPz = 2752, + AArch64_RDFFR_P = 2753, + AArch64_RDFFR_PPz = 2754, + AArch64_RDVLI_XI = 2755, + AArch64_RET = 2756, + AArch64_RETAA = 2757, + AArch64_RETAB = 2758, + AArch64_RET_ReallyLR = 2759, + AArch64_REV16Wr = 2760, + AArch64_REV16Xr = 2761, + AArch64_REV16v16i8 = 2762, + AArch64_REV16v8i8 = 2763, + AArch64_REV32Xr = 2764, + AArch64_REV32v16i8 = 2765, + AArch64_REV32v4i16 = 2766, + AArch64_REV32v8i16 = 2767, + AArch64_REV32v8i8 = 2768, + AArch64_REV64v16i8 = 2769, + AArch64_REV64v2i32 = 2770, + AArch64_REV64v4i16 = 2771, + AArch64_REV64v4i32 = 2772, + AArch64_REV64v8i16 = 2773, + AArch64_REV64v8i8 = 2774, + AArch64_REVB_ZPmZ_D = 2775, + AArch64_REVB_ZPmZ_H = 2776, + AArch64_REVB_ZPmZ_S = 2777, + AArch64_REVH_ZPmZ_D = 2778, + AArch64_REVH_ZPmZ_S = 2779, + AArch64_REVW_ZPmZ_D = 2780, + AArch64_REVWr = 2781, + AArch64_REVXr = 2782, + AArch64_REV_PP_B = 2783, + AArch64_REV_PP_D = 2784, + AArch64_REV_PP_H = 2785, + AArch64_REV_PP_S = 2786, + AArch64_REV_ZZ_B = 2787, + AArch64_REV_ZZ_D = 2788, + AArch64_REV_ZZ_H = 2789, + AArch64_REV_ZZ_S = 2790, + AArch64_RMIF = 2791, + AArch64_RORVWr = 2792, + AArch64_RORVXr = 2793, + AArch64_RSHRNv16i8_shift = 2794, + AArch64_RSHRNv2i32_shift = 2795, + AArch64_RSHRNv4i16_shift = 2796, + AArch64_RSHRNv4i32_shift = 2797, + AArch64_RSHRNv8i16_shift = 2798, + AArch64_RSHRNv8i8_shift = 2799, + AArch64_RSUBHNv2i64_v2i32 = 2800, + AArch64_RSUBHNv2i64_v4i32 = 2801, + AArch64_RSUBHNv4i32_v4i16 = 2802, + AArch64_RSUBHNv4i32_v8i16 = 2803, + AArch64_RSUBHNv8i16_v16i8 = 2804, + AArch64_RSUBHNv8i16_v8i8 = 2805, + AArch64_SABALv16i8_v8i16 = 2806, + AArch64_SABALv2i32_v2i64 = 2807, + AArch64_SABALv4i16_v4i32 = 2808, + AArch64_SABALv4i32_v2i64 = 2809, + AArch64_SABALv8i16_v4i32 = 2810, + AArch64_SABALv8i8_v8i16 = 2811, + AArch64_SABAv16i8 = 2812, + AArch64_SABAv2i32 = 2813, + AArch64_SABAv4i16 = 2814, + AArch64_SABAv4i32 = 2815, + AArch64_SABAv8i16 = 2816, + AArch64_SABAv8i8 = 2817, + AArch64_SABDLv16i8_v8i16 = 2818, + AArch64_SABDLv2i32_v2i64 = 2819, + AArch64_SABDLv4i16_v4i32 = 2820, + AArch64_SABDLv4i32_v2i64 = 2821, + AArch64_SABDLv8i16_v4i32 = 2822, + AArch64_SABDLv8i8_v8i16 = 2823, + AArch64_SABD_ZPmZ_B = 2824, + AArch64_SABD_ZPmZ_D = 2825, + AArch64_SABD_ZPmZ_H = 2826, + AArch64_SABD_ZPmZ_S = 2827, + AArch64_SABDv16i8 = 2828, + AArch64_SABDv2i32 = 2829, + AArch64_SABDv4i16 = 2830, + AArch64_SABDv4i32 = 2831, + AArch64_SABDv8i16 = 2832, + AArch64_SABDv8i8 = 2833, + AArch64_SADALPv16i8_v8i16 = 2834, + AArch64_SADALPv2i32_v1i64 = 2835, + AArch64_SADALPv4i16_v2i32 = 2836, + AArch64_SADALPv4i32_v2i64 = 2837, + AArch64_SADALPv8i16_v4i32 = 2838, + AArch64_SADALPv8i8_v4i16 = 2839, + AArch64_SADDLPv16i8_v8i16 = 2840, + AArch64_SADDLPv2i32_v1i64 = 2841, + AArch64_SADDLPv4i16_v2i32 = 2842, + AArch64_SADDLPv4i32_v2i64 = 2843, + AArch64_SADDLPv8i16_v4i32 = 2844, + AArch64_SADDLPv8i8_v4i16 = 2845, + AArch64_SADDLVv16i8v = 2846, + AArch64_SADDLVv4i16v = 2847, + AArch64_SADDLVv4i32v = 2848, + AArch64_SADDLVv8i16v = 2849, + AArch64_SADDLVv8i8v = 2850, + AArch64_SADDLv16i8_v8i16 = 2851, + AArch64_SADDLv2i32_v2i64 = 2852, + AArch64_SADDLv4i16_v4i32 = 2853, + AArch64_SADDLv4i32_v2i64 = 2854, + AArch64_SADDLv8i16_v4i32 = 2855, + AArch64_SADDLv8i8_v8i16 = 2856, + AArch64_SADDV_VPZ_B = 2857, + AArch64_SADDV_VPZ_H = 2858, + AArch64_SADDV_VPZ_S = 2859, + AArch64_SADDWv16i8_v8i16 = 2860, + AArch64_SADDWv2i32_v2i64 = 2861, + AArch64_SADDWv4i16_v4i32 = 2862, + AArch64_SADDWv4i32_v2i64 = 2863, + AArch64_SADDWv8i16_v4i32 = 2864, + AArch64_SADDWv8i8_v8i16 = 2865, + AArch64_SBCSWr = 2866, + AArch64_SBCSXr = 2867, + AArch64_SBCWr = 2868, + AArch64_SBCXr = 2869, + AArch64_SBFMWri = 2870, + AArch64_SBFMXri = 2871, + AArch64_SCVTFSWDri = 2872, + AArch64_SCVTFSWHri = 2873, + AArch64_SCVTFSWSri = 2874, + AArch64_SCVTFSXDri = 2875, + AArch64_SCVTFSXHri = 2876, + AArch64_SCVTFSXSri = 2877, + AArch64_SCVTFUWDri = 2878, + AArch64_SCVTFUWHri = 2879, + AArch64_SCVTFUWSri = 2880, + AArch64_SCVTFUXDri = 2881, + AArch64_SCVTFUXHri = 2882, + AArch64_SCVTFUXSri = 2883, + AArch64_SCVTF_ZPmZ_DtoD = 2884, + AArch64_SCVTF_ZPmZ_DtoH = 2885, + AArch64_SCVTF_ZPmZ_DtoS = 2886, + AArch64_SCVTF_ZPmZ_HtoH = 2887, + AArch64_SCVTF_ZPmZ_StoD = 2888, + AArch64_SCVTF_ZPmZ_StoH = 2889, + AArch64_SCVTF_ZPmZ_StoS = 2890, + AArch64_SCVTFd = 2891, + AArch64_SCVTFh = 2892, + AArch64_SCVTFs = 2893, + AArch64_SCVTFv1i16 = 2894, + AArch64_SCVTFv1i32 = 2895, + AArch64_SCVTFv1i64 = 2896, + AArch64_SCVTFv2f32 = 2897, + AArch64_SCVTFv2f64 = 2898, + AArch64_SCVTFv2i32_shift = 2899, + AArch64_SCVTFv2i64_shift = 2900, + AArch64_SCVTFv4f16 = 2901, + AArch64_SCVTFv4f32 = 2902, + AArch64_SCVTFv4i16_shift = 2903, + AArch64_SCVTFv4i32_shift = 2904, + AArch64_SCVTFv8f16 = 2905, + AArch64_SCVTFv8i16_shift = 2906, + AArch64_SDIVR_ZPmZ_D = 2907, + AArch64_SDIVR_ZPmZ_S = 2908, + AArch64_SDIVWr = 2909, + AArch64_SDIVXr = 2910, + AArch64_SDIV_ZPmZ_D = 2911, + AArch64_SDIV_ZPmZ_S = 2912, + AArch64_SDOT_ZZZI_D = 2913, + AArch64_SDOT_ZZZI_S = 2914, + AArch64_SDOT_ZZZ_D = 2915, + AArch64_SDOT_ZZZ_S = 2916, + AArch64_SDOTlanev16i8 = 2917, + AArch64_SDOTlanev8i8 = 2918, + AArch64_SDOTv16i8 = 2919, + AArch64_SDOTv8i8 = 2920, + AArch64_SEL_PPPP = 2921, + AArch64_SEL_ZPZZ_B = 2922, + AArch64_SEL_ZPZZ_D = 2923, + AArch64_SEL_ZPZZ_H = 2924, + AArch64_SEL_ZPZZ_S = 2925, + AArch64_SETF16 = 2926, + AArch64_SETF8 = 2927, + AArch64_SETFFR = 2928, + AArch64_SHA1Crrr = 2929, + AArch64_SHA1Hrr = 2930, + AArch64_SHA1Mrrr = 2931, + AArch64_SHA1Prrr = 2932, + AArch64_SHA1SU0rrr = 2933, + AArch64_SHA1SU1rr = 2934, + AArch64_SHA256H2rrr = 2935, + AArch64_SHA256Hrrr = 2936, + AArch64_SHA256SU0rr = 2937, + AArch64_SHA256SU1rrr = 2938, + AArch64_SHA512H = 2939, + AArch64_SHA512H2 = 2940, + AArch64_SHA512SU0 = 2941, + AArch64_SHA512SU1 = 2942, + AArch64_SHADDv16i8 = 2943, + AArch64_SHADDv2i32 = 2944, + AArch64_SHADDv4i16 = 2945, + AArch64_SHADDv4i32 = 2946, + AArch64_SHADDv8i16 = 2947, + AArch64_SHADDv8i8 = 2948, + AArch64_SHLLv16i8 = 2949, + AArch64_SHLLv2i32 = 2950, + AArch64_SHLLv4i16 = 2951, + AArch64_SHLLv4i32 = 2952, + AArch64_SHLLv8i16 = 2953, + AArch64_SHLLv8i8 = 2954, + AArch64_SHLd = 2955, + AArch64_SHLv16i8_shift = 2956, + AArch64_SHLv2i32_shift = 2957, + AArch64_SHLv2i64_shift = 2958, + AArch64_SHLv4i16_shift = 2959, + AArch64_SHLv4i32_shift = 2960, + AArch64_SHLv8i16_shift = 2961, + AArch64_SHLv8i8_shift = 2962, + AArch64_SHRNv16i8_shift = 2963, + AArch64_SHRNv2i32_shift = 2964, + AArch64_SHRNv4i16_shift = 2965, + AArch64_SHRNv4i32_shift = 2966, + AArch64_SHRNv8i16_shift = 2967, + AArch64_SHRNv8i8_shift = 2968, + AArch64_SHSUBv16i8 = 2969, + AArch64_SHSUBv2i32 = 2970, + AArch64_SHSUBv4i16 = 2971, + AArch64_SHSUBv4i32 = 2972, + AArch64_SHSUBv8i16 = 2973, + AArch64_SHSUBv8i8 = 2974, + AArch64_SLId = 2975, + AArch64_SLIv16i8_shift = 2976, + AArch64_SLIv2i32_shift = 2977, + AArch64_SLIv2i64_shift = 2978, + AArch64_SLIv4i16_shift = 2979, + AArch64_SLIv4i32_shift = 2980, + AArch64_SLIv8i16_shift = 2981, + AArch64_SLIv8i8_shift = 2982, + AArch64_SM3PARTW1 = 2983, + AArch64_SM3PARTW2 = 2984, + AArch64_SM3SS1 = 2985, + AArch64_SM3TT1A = 2986, + AArch64_SM3TT1B = 2987, + AArch64_SM3TT2A = 2988, + AArch64_SM3TT2B = 2989, + AArch64_SM4E = 2990, + AArch64_SM4ENCKEY = 2991, + AArch64_SMADDLrrr = 2992, + AArch64_SMAXPv16i8 = 2993, + AArch64_SMAXPv2i32 = 2994, + AArch64_SMAXPv4i16 = 2995, + AArch64_SMAXPv4i32 = 2996, + AArch64_SMAXPv8i16 = 2997, + AArch64_SMAXPv8i8 = 2998, + AArch64_SMAXV_VPZ_B = 2999, + AArch64_SMAXV_VPZ_D = 3000, + AArch64_SMAXV_VPZ_H = 3001, + AArch64_SMAXV_VPZ_S = 3002, + AArch64_SMAXVv16i8v = 3003, + AArch64_SMAXVv4i16v = 3004, + AArch64_SMAXVv4i32v = 3005, + AArch64_SMAXVv8i16v = 3006, + AArch64_SMAXVv8i8v = 3007, + AArch64_SMAX_ZI_B = 3008, + AArch64_SMAX_ZI_D = 3009, + AArch64_SMAX_ZI_H = 3010, + AArch64_SMAX_ZI_S = 3011, + AArch64_SMAX_ZPmZ_B = 3012, + AArch64_SMAX_ZPmZ_D = 3013, + AArch64_SMAX_ZPmZ_H = 3014, + AArch64_SMAX_ZPmZ_S = 3015, + AArch64_SMAXv16i8 = 3016, + AArch64_SMAXv2i32 = 3017, + AArch64_SMAXv4i16 = 3018, + AArch64_SMAXv4i32 = 3019, + AArch64_SMAXv8i16 = 3020, + AArch64_SMAXv8i8 = 3021, + AArch64_SMC = 3022, + AArch64_SMINPv16i8 = 3023, + AArch64_SMINPv2i32 = 3024, + AArch64_SMINPv4i16 = 3025, + AArch64_SMINPv4i32 = 3026, + AArch64_SMINPv8i16 = 3027, + AArch64_SMINPv8i8 = 3028, + AArch64_SMINV_VPZ_B = 3029, + AArch64_SMINV_VPZ_D = 3030, + AArch64_SMINV_VPZ_H = 3031, + AArch64_SMINV_VPZ_S = 3032, + AArch64_SMINVv16i8v = 3033, + AArch64_SMINVv4i16v = 3034, + AArch64_SMINVv4i32v = 3035, + AArch64_SMINVv8i16v = 3036, + AArch64_SMINVv8i8v = 3037, + AArch64_SMIN_ZI_B = 3038, + AArch64_SMIN_ZI_D = 3039, + AArch64_SMIN_ZI_H = 3040, + AArch64_SMIN_ZI_S = 3041, + AArch64_SMIN_ZPmZ_B = 3042, + AArch64_SMIN_ZPmZ_D = 3043, + AArch64_SMIN_ZPmZ_H = 3044, + AArch64_SMIN_ZPmZ_S = 3045, + AArch64_SMINv16i8 = 3046, + AArch64_SMINv2i32 = 3047, + AArch64_SMINv4i16 = 3048, + AArch64_SMINv4i32 = 3049, + AArch64_SMINv8i16 = 3050, + AArch64_SMINv8i8 = 3051, + AArch64_SMLALv16i8_v8i16 = 3052, + AArch64_SMLALv2i32_indexed = 3053, + AArch64_SMLALv2i32_v2i64 = 3054, + AArch64_SMLALv4i16_indexed = 3055, + AArch64_SMLALv4i16_v4i32 = 3056, + AArch64_SMLALv4i32_indexed = 3057, + AArch64_SMLALv4i32_v2i64 = 3058, + AArch64_SMLALv8i16_indexed = 3059, + AArch64_SMLALv8i16_v4i32 = 3060, + AArch64_SMLALv8i8_v8i16 = 3061, + AArch64_SMLSLv16i8_v8i16 = 3062, + AArch64_SMLSLv2i32_indexed = 3063, + AArch64_SMLSLv2i32_v2i64 = 3064, + AArch64_SMLSLv4i16_indexed = 3065, + AArch64_SMLSLv4i16_v4i32 = 3066, + AArch64_SMLSLv4i32_indexed = 3067, + AArch64_SMLSLv4i32_v2i64 = 3068, + AArch64_SMLSLv8i16_indexed = 3069, + AArch64_SMLSLv8i16_v4i32 = 3070, + AArch64_SMLSLv8i8_v8i16 = 3071, + AArch64_SMOVvi16to32 = 3072, + AArch64_SMOVvi16to64 = 3073, + AArch64_SMOVvi32to64 = 3074, + AArch64_SMOVvi8to32 = 3075, + AArch64_SMOVvi8to64 = 3076, + AArch64_SMSUBLrrr = 3077, + AArch64_SMULH_ZPmZ_B = 3078, + AArch64_SMULH_ZPmZ_D = 3079, + AArch64_SMULH_ZPmZ_H = 3080, + AArch64_SMULH_ZPmZ_S = 3081, + AArch64_SMULHrr = 3082, + AArch64_SMULLv16i8_v8i16 = 3083, + AArch64_SMULLv2i32_indexed = 3084, + AArch64_SMULLv2i32_v2i64 = 3085, + AArch64_SMULLv4i16_indexed = 3086, + AArch64_SMULLv4i16_v4i32 = 3087, + AArch64_SMULLv4i32_indexed = 3088, + AArch64_SMULLv4i32_v2i64 = 3089, + AArch64_SMULLv8i16_indexed = 3090, + AArch64_SMULLv8i16_v4i32 = 3091, + AArch64_SMULLv8i8_v8i16 = 3092, + AArch64_SPLICE_ZPZ_B = 3093, + AArch64_SPLICE_ZPZ_D = 3094, + AArch64_SPLICE_ZPZ_H = 3095, + AArch64_SPLICE_ZPZ_S = 3096, + AArch64_SQABSv16i8 = 3097, + AArch64_SQABSv1i16 = 3098, + AArch64_SQABSv1i32 = 3099, + AArch64_SQABSv1i64 = 3100, + AArch64_SQABSv1i8 = 3101, + AArch64_SQABSv2i32 = 3102, + AArch64_SQABSv2i64 = 3103, + AArch64_SQABSv4i16 = 3104, + AArch64_SQABSv4i32 = 3105, + AArch64_SQABSv8i16 = 3106, + AArch64_SQABSv8i8 = 3107, + AArch64_SQADD_ZI_B = 3108, + AArch64_SQADD_ZI_D = 3109, + AArch64_SQADD_ZI_H = 3110, + AArch64_SQADD_ZI_S = 3111, + AArch64_SQADD_ZZZ_B = 3112, + AArch64_SQADD_ZZZ_D = 3113, + AArch64_SQADD_ZZZ_H = 3114, + AArch64_SQADD_ZZZ_S = 3115, + AArch64_SQADDv16i8 = 3116, + AArch64_SQADDv1i16 = 3117, + AArch64_SQADDv1i32 = 3118, + AArch64_SQADDv1i64 = 3119, + AArch64_SQADDv1i8 = 3120, + AArch64_SQADDv2i32 = 3121, + AArch64_SQADDv2i64 = 3122, + AArch64_SQADDv4i16 = 3123, + AArch64_SQADDv4i32 = 3124, + AArch64_SQADDv8i16 = 3125, + AArch64_SQADDv8i8 = 3126, + AArch64_SQDECB_XPiI = 3127, + AArch64_SQDECB_XPiWdI = 3128, + AArch64_SQDECD_XPiI = 3129, + AArch64_SQDECD_XPiWdI = 3130, + AArch64_SQDECD_ZPiI = 3131, + AArch64_SQDECH_XPiI = 3132, + AArch64_SQDECH_XPiWdI = 3133, + AArch64_SQDECH_ZPiI = 3134, + AArch64_SQDECP_XPWd_B = 3135, + AArch64_SQDECP_XPWd_D = 3136, + AArch64_SQDECP_XPWd_H = 3137, + AArch64_SQDECP_XPWd_S = 3138, + AArch64_SQDECP_XP_B = 3139, + AArch64_SQDECP_XP_D = 3140, + AArch64_SQDECP_XP_H = 3141, + AArch64_SQDECP_XP_S = 3142, + AArch64_SQDECP_ZP_D = 3143, + AArch64_SQDECP_ZP_H = 3144, + AArch64_SQDECP_ZP_S = 3145, + AArch64_SQDECW_XPiI = 3146, + AArch64_SQDECW_XPiWdI = 3147, + AArch64_SQDECW_ZPiI = 3148, + AArch64_SQDMLALi16 = 3149, + AArch64_SQDMLALi32 = 3150, + AArch64_SQDMLALv1i32_indexed = 3151, + AArch64_SQDMLALv1i64_indexed = 3152, + AArch64_SQDMLALv2i32_indexed = 3153, + AArch64_SQDMLALv2i32_v2i64 = 3154, + AArch64_SQDMLALv4i16_indexed = 3155, + AArch64_SQDMLALv4i16_v4i32 = 3156, + AArch64_SQDMLALv4i32_indexed = 3157, + AArch64_SQDMLALv4i32_v2i64 = 3158, + AArch64_SQDMLALv8i16_indexed = 3159, + AArch64_SQDMLALv8i16_v4i32 = 3160, + AArch64_SQDMLSLi16 = 3161, + AArch64_SQDMLSLi32 = 3162, + AArch64_SQDMLSLv1i32_indexed = 3163, + AArch64_SQDMLSLv1i64_indexed = 3164, + AArch64_SQDMLSLv2i32_indexed = 3165, + AArch64_SQDMLSLv2i32_v2i64 = 3166, + AArch64_SQDMLSLv4i16_indexed = 3167, + AArch64_SQDMLSLv4i16_v4i32 = 3168, + AArch64_SQDMLSLv4i32_indexed = 3169, + AArch64_SQDMLSLv4i32_v2i64 = 3170, + AArch64_SQDMLSLv8i16_indexed = 3171, + AArch64_SQDMLSLv8i16_v4i32 = 3172, + AArch64_SQDMULHv1i16 = 3173, + AArch64_SQDMULHv1i16_indexed = 3174, + AArch64_SQDMULHv1i32 = 3175, + AArch64_SQDMULHv1i32_indexed = 3176, + AArch64_SQDMULHv2i32 = 3177, + AArch64_SQDMULHv2i32_indexed = 3178, + AArch64_SQDMULHv4i16 = 3179, + AArch64_SQDMULHv4i16_indexed = 3180, + AArch64_SQDMULHv4i32 = 3181, + AArch64_SQDMULHv4i32_indexed = 3182, + AArch64_SQDMULHv8i16 = 3183, + AArch64_SQDMULHv8i16_indexed = 3184, + AArch64_SQDMULLi16 = 3185, + AArch64_SQDMULLi32 = 3186, + AArch64_SQDMULLv1i32_indexed = 3187, + AArch64_SQDMULLv1i64_indexed = 3188, + AArch64_SQDMULLv2i32_indexed = 3189, + AArch64_SQDMULLv2i32_v2i64 = 3190, + AArch64_SQDMULLv4i16_indexed = 3191, + AArch64_SQDMULLv4i16_v4i32 = 3192, + AArch64_SQDMULLv4i32_indexed = 3193, + AArch64_SQDMULLv4i32_v2i64 = 3194, + AArch64_SQDMULLv8i16_indexed = 3195, + AArch64_SQDMULLv8i16_v4i32 = 3196, + AArch64_SQINCB_XPiI = 3197, + AArch64_SQINCB_XPiWdI = 3198, + AArch64_SQINCD_XPiI = 3199, + AArch64_SQINCD_XPiWdI = 3200, + AArch64_SQINCD_ZPiI = 3201, + AArch64_SQINCH_XPiI = 3202, + AArch64_SQINCH_XPiWdI = 3203, + AArch64_SQINCH_ZPiI = 3204, + AArch64_SQINCP_XPWd_B = 3205, + AArch64_SQINCP_XPWd_D = 3206, + AArch64_SQINCP_XPWd_H = 3207, + AArch64_SQINCP_XPWd_S = 3208, + AArch64_SQINCP_XP_B = 3209, + AArch64_SQINCP_XP_D = 3210, + AArch64_SQINCP_XP_H = 3211, + AArch64_SQINCP_XP_S = 3212, + AArch64_SQINCP_ZP_D = 3213, + AArch64_SQINCP_ZP_H = 3214, + AArch64_SQINCP_ZP_S = 3215, + AArch64_SQINCW_XPiI = 3216, + AArch64_SQINCW_XPiWdI = 3217, + AArch64_SQINCW_ZPiI = 3218, + AArch64_SQNEGv16i8 = 3219, + AArch64_SQNEGv1i16 = 3220, + AArch64_SQNEGv1i32 = 3221, + AArch64_SQNEGv1i64 = 3222, + AArch64_SQNEGv1i8 = 3223, + AArch64_SQNEGv2i32 = 3224, + AArch64_SQNEGv2i64 = 3225, + AArch64_SQNEGv4i16 = 3226, + AArch64_SQNEGv4i32 = 3227, + AArch64_SQNEGv8i16 = 3228, + AArch64_SQNEGv8i8 = 3229, + AArch64_SQRDMLAHi16_indexed = 3230, + AArch64_SQRDMLAHi32_indexed = 3231, + AArch64_SQRDMLAHv1i16 = 3232, + AArch64_SQRDMLAHv1i32 = 3233, + AArch64_SQRDMLAHv2i32 = 3234, + AArch64_SQRDMLAHv2i32_indexed = 3235, + AArch64_SQRDMLAHv4i16 = 3236, + AArch64_SQRDMLAHv4i16_indexed = 3237, + AArch64_SQRDMLAHv4i32 = 3238, + AArch64_SQRDMLAHv4i32_indexed = 3239, + AArch64_SQRDMLAHv8i16 = 3240, + AArch64_SQRDMLAHv8i16_indexed = 3241, + AArch64_SQRDMLSHi16_indexed = 3242, + AArch64_SQRDMLSHi32_indexed = 3243, + AArch64_SQRDMLSHv1i16 = 3244, + AArch64_SQRDMLSHv1i32 = 3245, + AArch64_SQRDMLSHv2i32 = 3246, + AArch64_SQRDMLSHv2i32_indexed = 3247, + AArch64_SQRDMLSHv4i16 = 3248, + AArch64_SQRDMLSHv4i16_indexed = 3249, + AArch64_SQRDMLSHv4i32 = 3250, + AArch64_SQRDMLSHv4i32_indexed = 3251, + AArch64_SQRDMLSHv8i16 = 3252, + AArch64_SQRDMLSHv8i16_indexed = 3253, + AArch64_SQRDMULHv1i16 = 3254, + AArch64_SQRDMULHv1i16_indexed = 3255, + AArch64_SQRDMULHv1i32 = 3256, + AArch64_SQRDMULHv1i32_indexed = 3257, + AArch64_SQRDMULHv2i32 = 3258, + AArch64_SQRDMULHv2i32_indexed = 3259, + AArch64_SQRDMULHv4i16 = 3260, + AArch64_SQRDMULHv4i16_indexed = 3261, + AArch64_SQRDMULHv4i32 = 3262, + AArch64_SQRDMULHv4i32_indexed = 3263, + AArch64_SQRDMULHv8i16 = 3264, + AArch64_SQRDMULHv8i16_indexed = 3265, + AArch64_SQRSHLv16i8 = 3266, + AArch64_SQRSHLv1i16 = 3267, + AArch64_SQRSHLv1i32 = 3268, + AArch64_SQRSHLv1i64 = 3269, + AArch64_SQRSHLv1i8 = 3270, + AArch64_SQRSHLv2i32 = 3271, + AArch64_SQRSHLv2i64 = 3272, + AArch64_SQRSHLv4i16 = 3273, + AArch64_SQRSHLv4i32 = 3274, + AArch64_SQRSHLv8i16 = 3275, + AArch64_SQRSHLv8i8 = 3276, + AArch64_SQRSHRNb = 3277, + AArch64_SQRSHRNh = 3278, + AArch64_SQRSHRNs = 3279, + AArch64_SQRSHRNv16i8_shift = 3280, + AArch64_SQRSHRNv2i32_shift = 3281, + AArch64_SQRSHRNv4i16_shift = 3282, + AArch64_SQRSHRNv4i32_shift = 3283, + AArch64_SQRSHRNv8i16_shift = 3284, + AArch64_SQRSHRNv8i8_shift = 3285, + AArch64_SQRSHRUNb = 3286, + AArch64_SQRSHRUNh = 3287, + AArch64_SQRSHRUNs = 3288, + AArch64_SQRSHRUNv16i8_shift = 3289, + AArch64_SQRSHRUNv2i32_shift = 3290, + AArch64_SQRSHRUNv4i16_shift = 3291, + AArch64_SQRSHRUNv4i32_shift = 3292, + AArch64_SQRSHRUNv8i16_shift = 3293, + AArch64_SQRSHRUNv8i8_shift = 3294, + AArch64_SQSHLUb = 3295, + AArch64_SQSHLUd = 3296, + AArch64_SQSHLUh = 3297, + AArch64_SQSHLUs = 3298, + AArch64_SQSHLUv16i8_shift = 3299, + AArch64_SQSHLUv2i32_shift = 3300, + AArch64_SQSHLUv2i64_shift = 3301, + AArch64_SQSHLUv4i16_shift = 3302, + AArch64_SQSHLUv4i32_shift = 3303, + AArch64_SQSHLUv8i16_shift = 3304, + AArch64_SQSHLUv8i8_shift = 3305, + AArch64_SQSHLb = 3306, + AArch64_SQSHLd = 3307, + AArch64_SQSHLh = 3308, + AArch64_SQSHLs = 3309, + AArch64_SQSHLv16i8 = 3310, + AArch64_SQSHLv16i8_shift = 3311, + AArch64_SQSHLv1i16 = 3312, + AArch64_SQSHLv1i32 = 3313, + AArch64_SQSHLv1i64 = 3314, + AArch64_SQSHLv1i8 = 3315, + AArch64_SQSHLv2i32 = 3316, + AArch64_SQSHLv2i32_shift = 3317, + AArch64_SQSHLv2i64 = 3318, + AArch64_SQSHLv2i64_shift = 3319, + AArch64_SQSHLv4i16 = 3320, + AArch64_SQSHLv4i16_shift = 3321, + AArch64_SQSHLv4i32 = 3322, + AArch64_SQSHLv4i32_shift = 3323, + AArch64_SQSHLv8i16 = 3324, + AArch64_SQSHLv8i16_shift = 3325, + AArch64_SQSHLv8i8 = 3326, + AArch64_SQSHLv8i8_shift = 3327, + AArch64_SQSHRNb = 3328, + AArch64_SQSHRNh = 3329, + AArch64_SQSHRNs = 3330, + AArch64_SQSHRNv16i8_shift = 3331, + AArch64_SQSHRNv2i32_shift = 3332, + AArch64_SQSHRNv4i16_shift = 3333, + AArch64_SQSHRNv4i32_shift = 3334, + AArch64_SQSHRNv8i16_shift = 3335, + AArch64_SQSHRNv8i8_shift = 3336, + AArch64_SQSHRUNb = 3337, + AArch64_SQSHRUNh = 3338, + AArch64_SQSHRUNs = 3339, + AArch64_SQSHRUNv16i8_shift = 3340, + AArch64_SQSHRUNv2i32_shift = 3341, + AArch64_SQSHRUNv4i16_shift = 3342, + AArch64_SQSHRUNv4i32_shift = 3343, + AArch64_SQSHRUNv8i16_shift = 3344, + AArch64_SQSHRUNv8i8_shift = 3345, + AArch64_SQSUB_ZI_B = 3346, + AArch64_SQSUB_ZI_D = 3347, + AArch64_SQSUB_ZI_H = 3348, + AArch64_SQSUB_ZI_S = 3349, + AArch64_SQSUB_ZZZ_B = 3350, + AArch64_SQSUB_ZZZ_D = 3351, + AArch64_SQSUB_ZZZ_H = 3352, + AArch64_SQSUB_ZZZ_S = 3353, + AArch64_SQSUBv16i8 = 3354, + AArch64_SQSUBv1i16 = 3355, + AArch64_SQSUBv1i32 = 3356, + AArch64_SQSUBv1i64 = 3357, + AArch64_SQSUBv1i8 = 3358, + AArch64_SQSUBv2i32 = 3359, + AArch64_SQSUBv2i64 = 3360, + AArch64_SQSUBv4i16 = 3361, + AArch64_SQSUBv4i32 = 3362, + AArch64_SQSUBv8i16 = 3363, + AArch64_SQSUBv8i8 = 3364, + AArch64_SQXTNv16i8 = 3365, + AArch64_SQXTNv1i16 = 3366, + AArch64_SQXTNv1i32 = 3367, + AArch64_SQXTNv1i8 = 3368, + AArch64_SQXTNv2i32 = 3369, + AArch64_SQXTNv4i16 = 3370, + AArch64_SQXTNv4i32 = 3371, + AArch64_SQXTNv8i16 = 3372, + AArch64_SQXTNv8i8 = 3373, + AArch64_SQXTUNv16i8 = 3374, + AArch64_SQXTUNv1i16 = 3375, + AArch64_SQXTUNv1i32 = 3376, + AArch64_SQXTUNv1i8 = 3377, + AArch64_SQXTUNv2i32 = 3378, + AArch64_SQXTUNv4i16 = 3379, + AArch64_SQXTUNv4i32 = 3380, + AArch64_SQXTUNv8i16 = 3381, + AArch64_SQXTUNv8i8 = 3382, + AArch64_SRHADDv16i8 = 3383, + AArch64_SRHADDv2i32 = 3384, + AArch64_SRHADDv4i16 = 3385, + AArch64_SRHADDv4i32 = 3386, + AArch64_SRHADDv8i16 = 3387, + AArch64_SRHADDv8i8 = 3388, + AArch64_SRId = 3389, + AArch64_SRIv16i8_shift = 3390, + AArch64_SRIv2i32_shift = 3391, + AArch64_SRIv2i64_shift = 3392, + AArch64_SRIv4i16_shift = 3393, + AArch64_SRIv4i32_shift = 3394, + AArch64_SRIv8i16_shift = 3395, + AArch64_SRIv8i8_shift = 3396, + AArch64_SRSHLv16i8 = 3397, + AArch64_SRSHLv1i64 = 3398, + AArch64_SRSHLv2i32 = 3399, + AArch64_SRSHLv2i64 = 3400, + AArch64_SRSHLv4i16 = 3401, + AArch64_SRSHLv4i32 = 3402, + AArch64_SRSHLv8i16 = 3403, + AArch64_SRSHLv8i8 = 3404, + AArch64_SRSHRd = 3405, + AArch64_SRSHRv16i8_shift = 3406, + AArch64_SRSHRv2i32_shift = 3407, + AArch64_SRSHRv2i64_shift = 3408, + AArch64_SRSHRv4i16_shift = 3409, + AArch64_SRSHRv4i32_shift = 3410, + AArch64_SRSHRv8i16_shift = 3411, + AArch64_SRSHRv8i8_shift = 3412, + AArch64_SRSRAd = 3413, + AArch64_SRSRAv16i8_shift = 3414, + AArch64_SRSRAv2i32_shift = 3415, + AArch64_SRSRAv2i64_shift = 3416, + AArch64_SRSRAv4i16_shift = 3417, + AArch64_SRSRAv4i32_shift = 3418, + AArch64_SRSRAv8i16_shift = 3419, + AArch64_SRSRAv8i8_shift = 3420, + AArch64_SSHLLv16i8_shift = 3421, + AArch64_SSHLLv2i32_shift = 3422, + AArch64_SSHLLv4i16_shift = 3423, + AArch64_SSHLLv4i32_shift = 3424, + AArch64_SSHLLv8i16_shift = 3425, + AArch64_SSHLLv8i8_shift = 3426, + AArch64_SSHLv16i8 = 3427, + AArch64_SSHLv1i64 = 3428, + AArch64_SSHLv2i32 = 3429, + AArch64_SSHLv2i64 = 3430, + AArch64_SSHLv4i16 = 3431, + AArch64_SSHLv4i32 = 3432, + AArch64_SSHLv8i16 = 3433, + AArch64_SSHLv8i8 = 3434, + AArch64_SSHRd = 3435, + AArch64_SSHRv16i8_shift = 3436, + AArch64_SSHRv2i32_shift = 3437, + AArch64_SSHRv2i64_shift = 3438, + AArch64_SSHRv4i16_shift = 3439, + AArch64_SSHRv4i32_shift = 3440, + AArch64_SSHRv8i16_shift = 3441, + AArch64_SSHRv8i8_shift = 3442, + AArch64_SSRAd = 3443, + AArch64_SSRAv16i8_shift = 3444, + AArch64_SSRAv2i32_shift = 3445, + AArch64_SSRAv2i64_shift = 3446, + AArch64_SSRAv4i16_shift = 3447, + AArch64_SSRAv4i32_shift = 3448, + AArch64_SSRAv8i16_shift = 3449, + AArch64_SSRAv8i8_shift = 3450, + AArch64_SST1B_D = 3451, + AArch64_SST1B_D_IMM = 3452, + AArch64_SST1B_D_SXTW = 3453, + AArch64_SST1B_D_UXTW = 3454, + AArch64_SST1B_S_IMM = 3455, + AArch64_SST1B_S_SXTW = 3456, + AArch64_SST1B_S_UXTW = 3457, + AArch64_SST1D = 3458, + AArch64_SST1D_IMM = 3459, + AArch64_SST1D_SCALED = 3460, + AArch64_SST1D_SXTW = 3461, + AArch64_SST1D_SXTW_SCALED = 3462, + AArch64_SST1D_UXTW = 3463, + AArch64_SST1D_UXTW_SCALED = 3464, + AArch64_SST1H_D = 3465, + AArch64_SST1H_D_IMM = 3466, + AArch64_SST1H_D_SCALED = 3467, + AArch64_SST1H_D_SXTW = 3468, + AArch64_SST1H_D_SXTW_SCALED = 3469, + AArch64_SST1H_D_UXTW = 3470, + AArch64_SST1H_D_UXTW_SCALED = 3471, + AArch64_SST1H_S_IMM = 3472, + AArch64_SST1H_S_SXTW = 3473, + AArch64_SST1H_S_SXTW_SCALED = 3474, + AArch64_SST1H_S_UXTW = 3475, + AArch64_SST1H_S_UXTW_SCALED = 3476, + AArch64_SST1W_D = 3477, + AArch64_SST1W_D_IMM = 3478, + AArch64_SST1W_D_SCALED = 3479, + AArch64_SST1W_D_SXTW = 3480, + AArch64_SST1W_D_SXTW_SCALED = 3481, + AArch64_SST1W_D_UXTW = 3482, + AArch64_SST1W_D_UXTW_SCALED = 3483, + AArch64_SST1W_IMM = 3484, + AArch64_SST1W_SXTW = 3485, + AArch64_SST1W_SXTW_SCALED = 3486, + AArch64_SST1W_UXTW = 3487, + AArch64_SST1W_UXTW_SCALED = 3488, + AArch64_SSUBLv16i8_v8i16 = 3489, + AArch64_SSUBLv2i32_v2i64 = 3490, + AArch64_SSUBLv4i16_v4i32 = 3491, + AArch64_SSUBLv4i32_v2i64 = 3492, + AArch64_SSUBLv8i16_v4i32 = 3493, + AArch64_SSUBLv8i8_v8i16 = 3494, + AArch64_SSUBWv16i8_v8i16 = 3495, + AArch64_SSUBWv2i32_v2i64 = 3496, + AArch64_SSUBWv4i16_v4i32 = 3497, + AArch64_SSUBWv4i32_v2i64 = 3498, + AArch64_SSUBWv8i16_v4i32 = 3499, + AArch64_SSUBWv8i8_v8i16 = 3500, + AArch64_ST1B = 3501, + AArch64_ST1B_D = 3502, + AArch64_ST1B_D_IMM = 3503, + AArch64_ST1B_H = 3504, + AArch64_ST1B_H_IMM = 3505, + AArch64_ST1B_IMM = 3506, + AArch64_ST1B_S = 3507, + AArch64_ST1B_S_IMM = 3508, + AArch64_ST1D = 3509, + AArch64_ST1D_IMM = 3510, + AArch64_ST1Fourv16b = 3511, + AArch64_ST1Fourv16b_POST = 3512, + AArch64_ST1Fourv1d = 3513, + AArch64_ST1Fourv1d_POST = 3514, + AArch64_ST1Fourv2d = 3515, + AArch64_ST1Fourv2d_POST = 3516, + AArch64_ST1Fourv2s = 3517, + AArch64_ST1Fourv2s_POST = 3518, + AArch64_ST1Fourv4h = 3519, + AArch64_ST1Fourv4h_POST = 3520, + AArch64_ST1Fourv4s = 3521, + AArch64_ST1Fourv4s_POST = 3522, + AArch64_ST1Fourv8b = 3523, + AArch64_ST1Fourv8b_POST = 3524, + AArch64_ST1Fourv8h = 3525, + AArch64_ST1Fourv8h_POST = 3526, + AArch64_ST1H = 3527, + AArch64_ST1H_D = 3528, + AArch64_ST1H_D_IMM = 3529, + AArch64_ST1H_IMM = 3530, + AArch64_ST1H_S = 3531, + AArch64_ST1H_S_IMM = 3532, + AArch64_ST1Onev16b = 3533, + AArch64_ST1Onev16b_POST = 3534, + AArch64_ST1Onev1d = 3535, + AArch64_ST1Onev1d_POST = 3536, + AArch64_ST1Onev2d = 3537, + AArch64_ST1Onev2d_POST = 3538, + AArch64_ST1Onev2s = 3539, + AArch64_ST1Onev2s_POST = 3540, + AArch64_ST1Onev4h = 3541, + AArch64_ST1Onev4h_POST = 3542, + AArch64_ST1Onev4s = 3543, + AArch64_ST1Onev4s_POST = 3544, + AArch64_ST1Onev8b = 3545, + AArch64_ST1Onev8b_POST = 3546, + AArch64_ST1Onev8h = 3547, + AArch64_ST1Onev8h_POST = 3548, + AArch64_ST1Threev16b = 3549, + AArch64_ST1Threev16b_POST = 3550, + AArch64_ST1Threev1d = 3551, + AArch64_ST1Threev1d_POST = 3552, + AArch64_ST1Threev2d = 3553, + AArch64_ST1Threev2d_POST = 3554, + AArch64_ST1Threev2s = 3555, + AArch64_ST1Threev2s_POST = 3556, + AArch64_ST1Threev4h = 3557, + AArch64_ST1Threev4h_POST = 3558, + AArch64_ST1Threev4s = 3559, + AArch64_ST1Threev4s_POST = 3560, + AArch64_ST1Threev8b = 3561, + AArch64_ST1Threev8b_POST = 3562, + AArch64_ST1Threev8h = 3563, + AArch64_ST1Threev8h_POST = 3564, + AArch64_ST1Twov16b = 3565, + AArch64_ST1Twov16b_POST = 3566, + AArch64_ST1Twov1d = 3567, + AArch64_ST1Twov1d_POST = 3568, + AArch64_ST1Twov2d = 3569, + AArch64_ST1Twov2d_POST = 3570, + AArch64_ST1Twov2s = 3571, + AArch64_ST1Twov2s_POST = 3572, + AArch64_ST1Twov4h = 3573, + AArch64_ST1Twov4h_POST = 3574, + AArch64_ST1Twov4s = 3575, + AArch64_ST1Twov4s_POST = 3576, + AArch64_ST1Twov8b = 3577, + AArch64_ST1Twov8b_POST = 3578, + AArch64_ST1Twov8h = 3579, + AArch64_ST1Twov8h_POST = 3580, + AArch64_ST1W = 3581, + AArch64_ST1W_D = 3582, + AArch64_ST1W_D_IMM = 3583, + AArch64_ST1W_IMM = 3584, + AArch64_ST1i16 = 3585, + AArch64_ST1i16_POST = 3586, + AArch64_ST1i32 = 3587, + AArch64_ST1i32_POST = 3588, + AArch64_ST1i64 = 3589, + AArch64_ST1i64_POST = 3590, + AArch64_ST1i8 = 3591, + AArch64_ST1i8_POST = 3592, + AArch64_ST2B = 3593, + AArch64_ST2B_IMM = 3594, + AArch64_ST2D = 3595, + AArch64_ST2D_IMM = 3596, + AArch64_ST2H = 3597, + AArch64_ST2H_IMM = 3598, + AArch64_ST2Twov16b = 3599, + AArch64_ST2Twov16b_POST = 3600, + AArch64_ST2Twov2d = 3601, + AArch64_ST2Twov2d_POST = 3602, + AArch64_ST2Twov2s = 3603, + AArch64_ST2Twov2s_POST = 3604, + AArch64_ST2Twov4h = 3605, + AArch64_ST2Twov4h_POST = 3606, + AArch64_ST2Twov4s = 3607, + AArch64_ST2Twov4s_POST = 3608, + AArch64_ST2Twov8b = 3609, + AArch64_ST2Twov8b_POST = 3610, + AArch64_ST2Twov8h = 3611, + AArch64_ST2Twov8h_POST = 3612, + AArch64_ST2W = 3613, + AArch64_ST2W_IMM = 3614, + AArch64_ST2i16 = 3615, + AArch64_ST2i16_POST = 3616, + AArch64_ST2i32 = 3617, + AArch64_ST2i32_POST = 3618, + AArch64_ST2i64 = 3619, + AArch64_ST2i64_POST = 3620, + AArch64_ST2i8 = 3621, + AArch64_ST2i8_POST = 3622, + AArch64_ST3B = 3623, + AArch64_ST3B_IMM = 3624, + AArch64_ST3D = 3625, + AArch64_ST3D_IMM = 3626, + AArch64_ST3H = 3627, + AArch64_ST3H_IMM = 3628, + AArch64_ST3Threev16b = 3629, + AArch64_ST3Threev16b_POST = 3630, + AArch64_ST3Threev2d = 3631, + AArch64_ST3Threev2d_POST = 3632, + AArch64_ST3Threev2s = 3633, + AArch64_ST3Threev2s_POST = 3634, + AArch64_ST3Threev4h = 3635, + AArch64_ST3Threev4h_POST = 3636, + AArch64_ST3Threev4s = 3637, + AArch64_ST3Threev4s_POST = 3638, + AArch64_ST3Threev8b = 3639, + AArch64_ST3Threev8b_POST = 3640, + AArch64_ST3Threev8h = 3641, + AArch64_ST3Threev8h_POST = 3642, + AArch64_ST3W = 3643, + AArch64_ST3W_IMM = 3644, + AArch64_ST3i16 = 3645, + AArch64_ST3i16_POST = 3646, + AArch64_ST3i32 = 3647, + AArch64_ST3i32_POST = 3648, + AArch64_ST3i64 = 3649, + AArch64_ST3i64_POST = 3650, + AArch64_ST3i8 = 3651, + AArch64_ST3i8_POST = 3652, + AArch64_ST4B = 3653, + AArch64_ST4B_IMM = 3654, + AArch64_ST4D = 3655, + AArch64_ST4D_IMM = 3656, + AArch64_ST4Fourv16b = 3657, + AArch64_ST4Fourv16b_POST = 3658, + AArch64_ST4Fourv2d = 3659, + AArch64_ST4Fourv2d_POST = 3660, + AArch64_ST4Fourv2s = 3661, + AArch64_ST4Fourv2s_POST = 3662, + AArch64_ST4Fourv4h = 3663, + AArch64_ST4Fourv4h_POST = 3664, + AArch64_ST4Fourv4s = 3665, + AArch64_ST4Fourv4s_POST = 3666, + AArch64_ST4Fourv8b = 3667, + AArch64_ST4Fourv8b_POST = 3668, + AArch64_ST4Fourv8h = 3669, + AArch64_ST4Fourv8h_POST = 3670, + AArch64_ST4H = 3671, + AArch64_ST4H_IMM = 3672, + AArch64_ST4W = 3673, + AArch64_ST4W_IMM = 3674, + AArch64_ST4i16 = 3675, + AArch64_ST4i16_POST = 3676, + AArch64_ST4i32 = 3677, + AArch64_ST4i32_POST = 3678, + AArch64_ST4i64 = 3679, + AArch64_ST4i64_POST = 3680, + AArch64_ST4i8 = 3681, + AArch64_ST4i8_POST = 3682, + AArch64_STLLRB = 3683, + AArch64_STLLRH = 3684, + AArch64_STLLRW = 3685, + AArch64_STLLRX = 3686, + AArch64_STLRB = 3687, + AArch64_STLRH = 3688, + AArch64_STLRW = 3689, + AArch64_STLRX = 3690, + AArch64_STLURBi = 3691, + AArch64_STLURHi = 3692, + AArch64_STLURWi = 3693, + AArch64_STLURXi = 3694, + AArch64_STLXPW = 3695, + AArch64_STLXPX = 3696, + AArch64_STLXRB = 3697, + AArch64_STLXRH = 3698, + AArch64_STLXRW = 3699, + AArch64_STLXRX = 3700, + AArch64_STNPDi = 3701, + AArch64_STNPQi = 3702, + AArch64_STNPSi = 3703, + AArch64_STNPWi = 3704, + AArch64_STNPXi = 3705, + AArch64_STNT1B_ZRI = 3706, + AArch64_STNT1B_ZRR = 3707, + AArch64_STNT1D_ZRI = 3708, + AArch64_STNT1D_ZRR = 3709, + AArch64_STNT1H_ZRI = 3710, + AArch64_STNT1H_ZRR = 3711, + AArch64_STNT1W_ZRI = 3712, + AArch64_STNT1W_ZRR = 3713, + AArch64_STPDi = 3714, + AArch64_STPDpost = 3715, + AArch64_STPDpre = 3716, + AArch64_STPQi = 3717, + AArch64_STPQpost = 3718, + AArch64_STPQpre = 3719, + AArch64_STPSi = 3720, + AArch64_STPSpost = 3721, + AArch64_STPSpre = 3722, + AArch64_STPWi = 3723, + AArch64_STPWpost = 3724, + AArch64_STPWpre = 3725, + AArch64_STPXi = 3726, + AArch64_STPXpost = 3727, + AArch64_STPXpre = 3728, + AArch64_STRBBpost = 3729, + AArch64_STRBBpre = 3730, + AArch64_STRBBroW = 3731, + AArch64_STRBBroX = 3732, + AArch64_STRBBui = 3733, + AArch64_STRBpost = 3734, + AArch64_STRBpre = 3735, + AArch64_STRBroW = 3736, + AArch64_STRBroX = 3737, + AArch64_STRBui = 3738, + AArch64_STRDpost = 3739, + AArch64_STRDpre = 3740, + AArch64_STRDroW = 3741, + AArch64_STRDroX = 3742, + AArch64_STRDui = 3743, + AArch64_STRHHpost = 3744, + AArch64_STRHHpre = 3745, + AArch64_STRHHroW = 3746, + AArch64_STRHHroX = 3747, + AArch64_STRHHui = 3748, + AArch64_STRHpost = 3749, + AArch64_STRHpre = 3750, + AArch64_STRHroW = 3751, + AArch64_STRHroX = 3752, + AArch64_STRHui = 3753, + AArch64_STRQpost = 3754, + AArch64_STRQpre = 3755, + AArch64_STRQroW = 3756, + AArch64_STRQroX = 3757, + AArch64_STRQui = 3758, + AArch64_STRSpost = 3759, + AArch64_STRSpre = 3760, + AArch64_STRSroW = 3761, + AArch64_STRSroX = 3762, + AArch64_STRSui = 3763, + AArch64_STRWpost = 3764, + AArch64_STRWpre = 3765, + AArch64_STRWroW = 3766, + AArch64_STRWroX = 3767, + AArch64_STRWui = 3768, + AArch64_STRXpost = 3769, + AArch64_STRXpre = 3770, + AArch64_STRXroW = 3771, + AArch64_STRXroX = 3772, + AArch64_STRXui = 3773, + AArch64_STR_PXI = 3774, + AArch64_STR_ZXI = 3775, + AArch64_STTRBi = 3776, + AArch64_STTRHi = 3777, + AArch64_STTRWi = 3778, + AArch64_STTRXi = 3779, + AArch64_STURBBi = 3780, + AArch64_STURBi = 3781, + AArch64_STURDi = 3782, + AArch64_STURHHi = 3783, + AArch64_STURHi = 3784, + AArch64_STURQi = 3785, + AArch64_STURSi = 3786, + AArch64_STURWi = 3787, + AArch64_STURXi = 3788, + AArch64_STXPW = 3789, + AArch64_STXPX = 3790, + AArch64_STXRB = 3791, + AArch64_STXRH = 3792, + AArch64_STXRW = 3793, + AArch64_STXRX = 3794, + AArch64_SUBHNv2i64_v2i32 = 3795, + AArch64_SUBHNv2i64_v4i32 = 3796, + AArch64_SUBHNv4i32_v4i16 = 3797, + AArch64_SUBHNv4i32_v8i16 = 3798, + AArch64_SUBHNv8i16_v16i8 = 3799, + AArch64_SUBHNv8i16_v8i8 = 3800, + AArch64_SUBR_ZI_B = 3801, + AArch64_SUBR_ZI_D = 3802, + AArch64_SUBR_ZI_H = 3803, + AArch64_SUBR_ZI_S = 3804, + AArch64_SUBR_ZPmZ_B = 3805, + AArch64_SUBR_ZPmZ_D = 3806, + AArch64_SUBR_ZPmZ_H = 3807, + AArch64_SUBR_ZPmZ_S = 3808, + AArch64_SUBSWri = 3809, + AArch64_SUBSWrr = 3810, + AArch64_SUBSWrs = 3811, + AArch64_SUBSWrx = 3812, + AArch64_SUBSXri = 3813, + AArch64_SUBSXrr = 3814, + AArch64_SUBSXrs = 3815, + AArch64_SUBSXrx = 3816, + AArch64_SUBSXrx64 = 3817, + AArch64_SUBWri = 3818, + AArch64_SUBWrr = 3819, + AArch64_SUBWrs = 3820, + AArch64_SUBWrx = 3821, + AArch64_SUBXri = 3822, + AArch64_SUBXrr = 3823, + AArch64_SUBXrs = 3824, + AArch64_SUBXrx = 3825, + AArch64_SUBXrx64 = 3826, + AArch64_SUB_ZI_B = 3827, + AArch64_SUB_ZI_D = 3828, + AArch64_SUB_ZI_H = 3829, + AArch64_SUB_ZI_S = 3830, + AArch64_SUB_ZPmZ_B = 3831, + AArch64_SUB_ZPmZ_D = 3832, + AArch64_SUB_ZPmZ_H = 3833, + AArch64_SUB_ZPmZ_S = 3834, + AArch64_SUB_ZZZ_B = 3835, + AArch64_SUB_ZZZ_D = 3836, + AArch64_SUB_ZZZ_H = 3837, + AArch64_SUB_ZZZ_S = 3838, + AArch64_SUBv16i8 = 3839, + AArch64_SUBv1i64 = 3840, + AArch64_SUBv2i32 = 3841, + AArch64_SUBv2i64 = 3842, + AArch64_SUBv4i16 = 3843, + AArch64_SUBv4i32 = 3844, + AArch64_SUBv8i16 = 3845, + AArch64_SUBv8i8 = 3846, + AArch64_SUNPKHI_ZZ_D = 3847, + AArch64_SUNPKHI_ZZ_H = 3848, + AArch64_SUNPKHI_ZZ_S = 3849, + AArch64_SUNPKLO_ZZ_D = 3850, + AArch64_SUNPKLO_ZZ_H = 3851, + AArch64_SUNPKLO_ZZ_S = 3852, + AArch64_SUQADDv16i8 = 3853, + AArch64_SUQADDv1i16 = 3854, + AArch64_SUQADDv1i32 = 3855, + AArch64_SUQADDv1i64 = 3856, + AArch64_SUQADDv1i8 = 3857, + AArch64_SUQADDv2i32 = 3858, + AArch64_SUQADDv2i64 = 3859, + AArch64_SUQADDv4i16 = 3860, + AArch64_SUQADDv4i32 = 3861, + AArch64_SUQADDv8i16 = 3862, + AArch64_SUQADDv8i8 = 3863, + AArch64_SVC = 3864, + AArch64_SWPAB = 3865, + AArch64_SWPAH = 3866, + AArch64_SWPALB = 3867, + AArch64_SWPALH = 3868, + AArch64_SWPALW = 3869, + AArch64_SWPALX = 3870, + AArch64_SWPAW = 3871, + AArch64_SWPAX = 3872, + AArch64_SWPB = 3873, + AArch64_SWPH = 3874, + AArch64_SWPLB = 3875, + AArch64_SWPLH = 3876, + AArch64_SWPLW = 3877, + AArch64_SWPLX = 3878, + AArch64_SWPW = 3879, + AArch64_SWPX = 3880, + AArch64_SXTB_ZPmZ_D = 3881, + AArch64_SXTB_ZPmZ_H = 3882, + AArch64_SXTB_ZPmZ_S = 3883, + AArch64_SXTH_ZPmZ_D = 3884, + AArch64_SXTH_ZPmZ_S = 3885, + AArch64_SXTW_ZPmZ_D = 3886, + AArch64_SYSLxt = 3887, + AArch64_SYSxt = 3888, + AArch64_TBL_ZZZ_B = 3889, + AArch64_TBL_ZZZ_D = 3890, + AArch64_TBL_ZZZ_H = 3891, + AArch64_TBL_ZZZ_S = 3892, + AArch64_TBLv16i8Four = 3893, + AArch64_TBLv16i8One = 3894, + AArch64_TBLv16i8Three = 3895, + AArch64_TBLv16i8Two = 3896, + AArch64_TBLv8i8Four = 3897, + AArch64_TBLv8i8One = 3898, + AArch64_TBLv8i8Three = 3899, + AArch64_TBLv8i8Two = 3900, + AArch64_TBNZW = 3901, + AArch64_TBNZX = 3902, + AArch64_TBXv16i8Four = 3903, + AArch64_TBXv16i8One = 3904, + AArch64_TBXv16i8Three = 3905, + AArch64_TBXv16i8Two = 3906, + AArch64_TBXv8i8Four = 3907, + AArch64_TBXv8i8One = 3908, + AArch64_TBXv8i8Three = 3909, + AArch64_TBXv8i8Two = 3910, + AArch64_TBZW = 3911, + AArch64_TBZX = 3912, + AArch64_TCRETURNdi = 3913, + AArch64_TCRETURNri = 3914, + AArch64_TLSDESCCALL = 3915, + AArch64_TLSDESC_CALLSEQ = 3916, + AArch64_TRN1_PPP_B = 3917, + AArch64_TRN1_PPP_D = 3918, + AArch64_TRN1_PPP_H = 3919, + AArch64_TRN1_PPP_S = 3920, + AArch64_TRN1_ZZZ_B = 3921, + AArch64_TRN1_ZZZ_D = 3922, + AArch64_TRN1_ZZZ_H = 3923, + AArch64_TRN1_ZZZ_S = 3924, + AArch64_TRN1v16i8 = 3925, + AArch64_TRN1v2i32 = 3926, + AArch64_TRN1v2i64 = 3927, + AArch64_TRN1v4i16 = 3928, + AArch64_TRN1v4i32 = 3929, + AArch64_TRN1v8i16 = 3930, + AArch64_TRN1v8i8 = 3931, + AArch64_TRN2_PPP_B = 3932, + AArch64_TRN2_PPP_D = 3933, + AArch64_TRN2_PPP_H = 3934, + AArch64_TRN2_PPP_S = 3935, + AArch64_TRN2_ZZZ_B = 3936, + AArch64_TRN2_ZZZ_D = 3937, + AArch64_TRN2_ZZZ_H = 3938, + AArch64_TRN2_ZZZ_S = 3939, + AArch64_TRN2v16i8 = 3940, + AArch64_TRN2v2i32 = 3941, + AArch64_TRN2v2i64 = 3942, + AArch64_TRN2v4i16 = 3943, + AArch64_TRN2v4i32 = 3944, + AArch64_TRN2v8i16 = 3945, + AArch64_TRN2v8i8 = 3946, + AArch64_TSB = 3947, + AArch64_UABALv16i8_v8i16 = 3948, + AArch64_UABALv2i32_v2i64 = 3949, + AArch64_UABALv4i16_v4i32 = 3950, + AArch64_UABALv4i32_v2i64 = 3951, + AArch64_UABALv8i16_v4i32 = 3952, + AArch64_UABALv8i8_v8i16 = 3953, + AArch64_UABAv16i8 = 3954, + AArch64_UABAv2i32 = 3955, + AArch64_UABAv4i16 = 3956, + AArch64_UABAv4i32 = 3957, + AArch64_UABAv8i16 = 3958, + AArch64_UABAv8i8 = 3959, + AArch64_UABDLv16i8_v8i16 = 3960, + AArch64_UABDLv2i32_v2i64 = 3961, + AArch64_UABDLv4i16_v4i32 = 3962, + AArch64_UABDLv4i32_v2i64 = 3963, + AArch64_UABDLv8i16_v4i32 = 3964, + AArch64_UABDLv8i8_v8i16 = 3965, + AArch64_UABD_ZPmZ_B = 3966, + AArch64_UABD_ZPmZ_D = 3967, + AArch64_UABD_ZPmZ_H = 3968, + AArch64_UABD_ZPmZ_S = 3969, + AArch64_UABDv16i8 = 3970, + AArch64_UABDv2i32 = 3971, + AArch64_UABDv4i16 = 3972, + AArch64_UABDv4i32 = 3973, + AArch64_UABDv8i16 = 3974, + AArch64_UABDv8i8 = 3975, + AArch64_UADALPv16i8_v8i16 = 3976, + AArch64_UADALPv2i32_v1i64 = 3977, + AArch64_UADALPv4i16_v2i32 = 3978, + AArch64_UADALPv4i32_v2i64 = 3979, + AArch64_UADALPv8i16_v4i32 = 3980, + AArch64_UADALPv8i8_v4i16 = 3981, + AArch64_UADDLPv16i8_v8i16 = 3982, + AArch64_UADDLPv2i32_v1i64 = 3983, + AArch64_UADDLPv4i16_v2i32 = 3984, + AArch64_UADDLPv4i32_v2i64 = 3985, + AArch64_UADDLPv8i16_v4i32 = 3986, + AArch64_UADDLPv8i8_v4i16 = 3987, + AArch64_UADDLVv16i8v = 3988, + AArch64_UADDLVv4i16v = 3989, + AArch64_UADDLVv4i32v = 3990, + AArch64_UADDLVv8i16v = 3991, + AArch64_UADDLVv8i8v = 3992, + AArch64_UADDLv16i8_v8i16 = 3993, + AArch64_UADDLv2i32_v2i64 = 3994, + AArch64_UADDLv4i16_v4i32 = 3995, + AArch64_UADDLv4i32_v2i64 = 3996, + AArch64_UADDLv8i16_v4i32 = 3997, + AArch64_UADDLv8i8_v8i16 = 3998, + AArch64_UADDV_VPZ_B = 3999, + AArch64_UADDV_VPZ_D = 4000, + AArch64_UADDV_VPZ_H = 4001, + AArch64_UADDV_VPZ_S = 4002, + AArch64_UADDWv16i8_v8i16 = 4003, + AArch64_UADDWv2i32_v2i64 = 4004, + AArch64_UADDWv4i16_v4i32 = 4005, + AArch64_UADDWv4i32_v2i64 = 4006, + AArch64_UADDWv8i16_v4i32 = 4007, + AArch64_UADDWv8i8_v8i16 = 4008, + AArch64_UBFMWri = 4009, + AArch64_UBFMXri = 4010, + AArch64_UCVTFSWDri = 4011, + AArch64_UCVTFSWHri = 4012, + AArch64_UCVTFSWSri = 4013, + AArch64_UCVTFSXDri = 4014, + AArch64_UCVTFSXHri = 4015, + AArch64_UCVTFSXSri = 4016, + AArch64_UCVTFUWDri = 4017, + AArch64_UCVTFUWHri = 4018, + AArch64_UCVTFUWSri = 4019, + AArch64_UCVTFUXDri = 4020, + AArch64_UCVTFUXHri = 4021, + AArch64_UCVTFUXSri = 4022, + AArch64_UCVTF_ZPmZ_DtoD = 4023, + AArch64_UCVTF_ZPmZ_DtoH = 4024, + AArch64_UCVTF_ZPmZ_DtoS = 4025, + AArch64_UCVTF_ZPmZ_HtoH = 4026, + AArch64_UCVTF_ZPmZ_StoD = 4027, + AArch64_UCVTF_ZPmZ_StoH = 4028, + AArch64_UCVTF_ZPmZ_StoS = 4029, + AArch64_UCVTFd = 4030, + AArch64_UCVTFh = 4031, + AArch64_UCVTFs = 4032, + AArch64_UCVTFv1i16 = 4033, + AArch64_UCVTFv1i32 = 4034, + AArch64_UCVTFv1i64 = 4035, + AArch64_UCVTFv2f32 = 4036, + AArch64_UCVTFv2f64 = 4037, + AArch64_UCVTFv2i32_shift = 4038, + AArch64_UCVTFv2i64_shift = 4039, + AArch64_UCVTFv4f16 = 4040, + AArch64_UCVTFv4f32 = 4041, + AArch64_UCVTFv4i16_shift = 4042, + AArch64_UCVTFv4i32_shift = 4043, + AArch64_UCVTFv8f16 = 4044, + AArch64_UCVTFv8i16_shift = 4045, + AArch64_UDIVR_ZPmZ_D = 4046, + AArch64_UDIVR_ZPmZ_S = 4047, + AArch64_UDIVWr = 4048, + AArch64_UDIVXr = 4049, + AArch64_UDIV_ZPmZ_D = 4050, + AArch64_UDIV_ZPmZ_S = 4051, + AArch64_UDOT_ZZZI_D = 4052, + AArch64_UDOT_ZZZI_S = 4053, + AArch64_UDOT_ZZZ_D = 4054, + AArch64_UDOT_ZZZ_S = 4055, + AArch64_UDOTlanev16i8 = 4056, + AArch64_UDOTlanev8i8 = 4057, + AArch64_UDOTv16i8 = 4058, + AArch64_UDOTv8i8 = 4059, + AArch64_UHADDv16i8 = 4060, + AArch64_UHADDv2i32 = 4061, + AArch64_UHADDv4i16 = 4062, + AArch64_UHADDv4i32 = 4063, + AArch64_UHADDv8i16 = 4064, + AArch64_UHADDv8i8 = 4065, + AArch64_UHSUBv16i8 = 4066, + AArch64_UHSUBv2i32 = 4067, + AArch64_UHSUBv4i16 = 4068, + AArch64_UHSUBv4i32 = 4069, + AArch64_UHSUBv8i16 = 4070, + AArch64_UHSUBv8i8 = 4071, + AArch64_UMADDLrrr = 4072, + AArch64_UMAXPv16i8 = 4073, + AArch64_UMAXPv2i32 = 4074, + AArch64_UMAXPv4i16 = 4075, + AArch64_UMAXPv4i32 = 4076, + AArch64_UMAXPv8i16 = 4077, + AArch64_UMAXPv8i8 = 4078, + AArch64_UMAXV_VPZ_B = 4079, + AArch64_UMAXV_VPZ_D = 4080, + AArch64_UMAXV_VPZ_H = 4081, + AArch64_UMAXV_VPZ_S = 4082, + AArch64_UMAXVv16i8v = 4083, + AArch64_UMAXVv4i16v = 4084, + AArch64_UMAXVv4i32v = 4085, + AArch64_UMAXVv8i16v = 4086, + AArch64_UMAXVv8i8v = 4087, + AArch64_UMAX_ZI_B = 4088, + AArch64_UMAX_ZI_D = 4089, + AArch64_UMAX_ZI_H = 4090, + AArch64_UMAX_ZI_S = 4091, + AArch64_UMAX_ZPmZ_B = 4092, + AArch64_UMAX_ZPmZ_D = 4093, + AArch64_UMAX_ZPmZ_H = 4094, + AArch64_UMAX_ZPmZ_S = 4095, + AArch64_UMAXv16i8 = 4096, + AArch64_UMAXv2i32 = 4097, + AArch64_UMAXv4i16 = 4098, + AArch64_UMAXv4i32 = 4099, + AArch64_UMAXv8i16 = 4100, + AArch64_UMAXv8i8 = 4101, + AArch64_UMINPv16i8 = 4102, + AArch64_UMINPv2i32 = 4103, + AArch64_UMINPv4i16 = 4104, + AArch64_UMINPv4i32 = 4105, + AArch64_UMINPv8i16 = 4106, + AArch64_UMINPv8i8 = 4107, + AArch64_UMINV_VPZ_B = 4108, + AArch64_UMINV_VPZ_D = 4109, + AArch64_UMINV_VPZ_H = 4110, + AArch64_UMINV_VPZ_S = 4111, + AArch64_UMINVv16i8v = 4112, + AArch64_UMINVv4i16v = 4113, + AArch64_UMINVv4i32v = 4114, + AArch64_UMINVv8i16v = 4115, + AArch64_UMINVv8i8v = 4116, + AArch64_UMIN_ZI_B = 4117, + AArch64_UMIN_ZI_D = 4118, + AArch64_UMIN_ZI_H = 4119, + AArch64_UMIN_ZI_S = 4120, + AArch64_UMIN_ZPmZ_B = 4121, + AArch64_UMIN_ZPmZ_D = 4122, + AArch64_UMIN_ZPmZ_H = 4123, + AArch64_UMIN_ZPmZ_S = 4124, + AArch64_UMINv16i8 = 4125, + AArch64_UMINv2i32 = 4126, + AArch64_UMINv4i16 = 4127, + AArch64_UMINv4i32 = 4128, + AArch64_UMINv8i16 = 4129, + AArch64_UMINv8i8 = 4130, + AArch64_UMLALv16i8_v8i16 = 4131, + AArch64_UMLALv2i32_indexed = 4132, + AArch64_UMLALv2i32_v2i64 = 4133, + AArch64_UMLALv4i16_indexed = 4134, + AArch64_UMLALv4i16_v4i32 = 4135, + AArch64_UMLALv4i32_indexed = 4136, + AArch64_UMLALv4i32_v2i64 = 4137, + AArch64_UMLALv8i16_indexed = 4138, + AArch64_UMLALv8i16_v4i32 = 4139, + AArch64_UMLALv8i8_v8i16 = 4140, + AArch64_UMLSLv16i8_v8i16 = 4141, + AArch64_UMLSLv2i32_indexed = 4142, + AArch64_UMLSLv2i32_v2i64 = 4143, + AArch64_UMLSLv4i16_indexed = 4144, + AArch64_UMLSLv4i16_v4i32 = 4145, + AArch64_UMLSLv4i32_indexed = 4146, + AArch64_UMLSLv4i32_v2i64 = 4147, + AArch64_UMLSLv8i16_indexed = 4148, + AArch64_UMLSLv8i16_v4i32 = 4149, + AArch64_UMLSLv8i8_v8i16 = 4150, + AArch64_UMOVvi16 = 4151, + AArch64_UMOVvi32 = 4152, + AArch64_UMOVvi64 = 4153, + AArch64_UMOVvi8 = 4154, + AArch64_UMSUBLrrr = 4155, + AArch64_UMULH_ZPmZ_B = 4156, + AArch64_UMULH_ZPmZ_D = 4157, + AArch64_UMULH_ZPmZ_H = 4158, + AArch64_UMULH_ZPmZ_S = 4159, + AArch64_UMULHrr = 4160, + AArch64_UMULLv16i8_v8i16 = 4161, + AArch64_UMULLv2i32_indexed = 4162, + AArch64_UMULLv2i32_v2i64 = 4163, + AArch64_UMULLv4i16_indexed = 4164, + AArch64_UMULLv4i16_v4i32 = 4165, + AArch64_UMULLv4i32_indexed = 4166, + AArch64_UMULLv4i32_v2i64 = 4167, + AArch64_UMULLv8i16_indexed = 4168, + AArch64_UMULLv8i16_v4i32 = 4169, + AArch64_UMULLv8i8_v8i16 = 4170, + AArch64_UQADD_ZI_B = 4171, + AArch64_UQADD_ZI_D = 4172, + AArch64_UQADD_ZI_H = 4173, + AArch64_UQADD_ZI_S = 4174, + AArch64_UQADD_ZZZ_B = 4175, + AArch64_UQADD_ZZZ_D = 4176, + AArch64_UQADD_ZZZ_H = 4177, + AArch64_UQADD_ZZZ_S = 4178, + AArch64_UQADDv16i8 = 4179, + AArch64_UQADDv1i16 = 4180, + AArch64_UQADDv1i32 = 4181, + AArch64_UQADDv1i64 = 4182, + AArch64_UQADDv1i8 = 4183, + AArch64_UQADDv2i32 = 4184, + AArch64_UQADDv2i64 = 4185, + AArch64_UQADDv4i16 = 4186, + AArch64_UQADDv4i32 = 4187, + AArch64_UQADDv8i16 = 4188, + AArch64_UQADDv8i8 = 4189, + AArch64_UQDECB_WPiI = 4190, + AArch64_UQDECB_XPiI = 4191, + AArch64_UQDECD_WPiI = 4192, + AArch64_UQDECD_XPiI = 4193, + AArch64_UQDECD_ZPiI = 4194, + AArch64_UQDECH_WPiI = 4195, + AArch64_UQDECH_XPiI = 4196, + AArch64_UQDECH_ZPiI = 4197, + AArch64_UQDECP_WP_B = 4198, + AArch64_UQDECP_WP_D = 4199, + AArch64_UQDECP_WP_H = 4200, + AArch64_UQDECP_WP_S = 4201, + AArch64_UQDECP_XP_B = 4202, + AArch64_UQDECP_XP_D = 4203, + AArch64_UQDECP_XP_H = 4204, + AArch64_UQDECP_XP_S = 4205, + AArch64_UQDECP_ZP_D = 4206, + AArch64_UQDECP_ZP_H = 4207, + AArch64_UQDECP_ZP_S = 4208, + AArch64_UQDECW_WPiI = 4209, + AArch64_UQDECW_XPiI = 4210, + AArch64_UQDECW_ZPiI = 4211, + AArch64_UQINCB_WPiI = 4212, + AArch64_UQINCB_XPiI = 4213, + AArch64_UQINCD_WPiI = 4214, + AArch64_UQINCD_XPiI = 4215, + AArch64_UQINCD_ZPiI = 4216, + AArch64_UQINCH_WPiI = 4217, + AArch64_UQINCH_XPiI = 4218, + AArch64_UQINCH_ZPiI = 4219, + AArch64_UQINCP_WP_B = 4220, + AArch64_UQINCP_WP_D = 4221, + AArch64_UQINCP_WP_H = 4222, + AArch64_UQINCP_WP_S = 4223, + AArch64_UQINCP_XP_B = 4224, + AArch64_UQINCP_XP_D = 4225, + AArch64_UQINCP_XP_H = 4226, + AArch64_UQINCP_XP_S = 4227, + AArch64_UQINCP_ZP_D = 4228, + AArch64_UQINCP_ZP_H = 4229, + AArch64_UQINCP_ZP_S = 4230, + AArch64_UQINCW_WPiI = 4231, + AArch64_UQINCW_XPiI = 4232, + AArch64_UQINCW_ZPiI = 4233, + AArch64_UQRSHLv16i8 = 4234, + AArch64_UQRSHLv1i16 = 4235, + AArch64_UQRSHLv1i32 = 4236, + AArch64_UQRSHLv1i64 = 4237, + AArch64_UQRSHLv1i8 = 4238, + AArch64_UQRSHLv2i32 = 4239, + AArch64_UQRSHLv2i64 = 4240, + AArch64_UQRSHLv4i16 = 4241, + AArch64_UQRSHLv4i32 = 4242, + AArch64_UQRSHLv8i16 = 4243, + AArch64_UQRSHLv8i8 = 4244, + AArch64_UQRSHRNb = 4245, + AArch64_UQRSHRNh = 4246, + AArch64_UQRSHRNs = 4247, + AArch64_UQRSHRNv16i8_shift = 4248, + AArch64_UQRSHRNv2i32_shift = 4249, + AArch64_UQRSHRNv4i16_shift = 4250, + AArch64_UQRSHRNv4i32_shift = 4251, + AArch64_UQRSHRNv8i16_shift = 4252, + AArch64_UQRSHRNv8i8_shift = 4253, + AArch64_UQSHLb = 4254, + AArch64_UQSHLd = 4255, + AArch64_UQSHLh = 4256, + AArch64_UQSHLs = 4257, + AArch64_UQSHLv16i8 = 4258, + AArch64_UQSHLv16i8_shift = 4259, + AArch64_UQSHLv1i16 = 4260, + AArch64_UQSHLv1i32 = 4261, + AArch64_UQSHLv1i64 = 4262, + AArch64_UQSHLv1i8 = 4263, + AArch64_UQSHLv2i32 = 4264, + AArch64_UQSHLv2i32_shift = 4265, + AArch64_UQSHLv2i64 = 4266, + AArch64_UQSHLv2i64_shift = 4267, + AArch64_UQSHLv4i16 = 4268, + AArch64_UQSHLv4i16_shift = 4269, + AArch64_UQSHLv4i32 = 4270, + AArch64_UQSHLv4i32_shift = 4271, + AArch64_UQSHLv8i16 = 4272, + AArch64_UQSHLv8i16_shift = 4273, + AArch64_UQSHLv8i8 = 4274, + AArch64_UQSHLv8i8_shift = 4275, + AArch64_UQSHRNb = 4276, + AArch64_UQSHRNh = 4277, + AArch64_UQSHRNs = 4278, + AArch64_UQSHRNv16i8_shift = 4279, + AArch64_UQSHRNv2i32_shift = 4280, + AArch64_UQSHRNv4i16_shift = 4281, + AArch64_UQSHRNv4i32_shift = 4282, + AArch64_UQSHRNv8i16_shift = 4283, + AArch64_UQSHRNv8i8_shift = 4284, + AArch64_UQSUB_ZI_B = 4285, + AArch64_UQSUB_ZI_D = 4286, + AArch64_UQSUB_ZI_H = 4287, + AArch64_UQSUB_ZI_S = 4288, + AArch64_UQSUB_ZZZ_B = 4289, + AArch64_UQSUB_ZZZ_D = 4290, + AArch64_UQSUB_ZZZ_H = 4291, + AArch64_UQSUB_ZZZ_S = 4292, + AArch64_UQSUBv16i8 = 4293, + AArch64_UQSUBv1i16 = 4294, + AArch64_UQSUBv1i32 = 4295, + AArch64_UQSUBv1i64 = 4296, + AArch64_UQSUBv1i8 = 4297, + AArch64_UQSUBv2i32 = 4298, + AArch64_UQSUBv2i64 = 4299, + AArch64_UQSUBv4i16 = 4300, + AArch64_UQSUBv4i32 = 4301, + AArch64_UQSUBv8i16 = 4302, + AArch64_UQSUBv8i8 = 4303, + AArch64_UQXTNv16i8 = 4304, + AArch64_UQXTNv1i16 = 4305, + AArch64_UQXTNv1i32 = 4306, + AArch64_UQXTNv1i8 = 4307, + AArch64_UQXTNv2i32 = 4308, + AArch64_UQXTNv4i16 = 4309, + AArch64_UQXTNv4i32 = 4310, + AArch64_UQXTNv8i16 = 4311, + AArch64_UQXTNv8i8 = 4312, + AArch64_URECPEv2i32 = 4313, + AArch64_URECPEv4i32 = 4314, + AArch64_URHADDv16i8 = 4315, + AArch64_URHADDv2i32 = 4316, + AArch64_URHADDv4i16 = 4317, + AArch64_URHADDv4i32 = 4318, + AArch64_URHADDv8i16 = 4319, + AArch64_URHADDv8i8 = 4320, + AArch64_URSHLv16i8 = 4321, + AArch64_URSHLv1i64 = 4322, + AArch64_URSHLv2i32 = 4323, + AArch64_URSHLv2i64 = 4324, + AArch64_URSHLv4i16 = 4325, + AArch64_URSHLv4i32 = 4326, + AArch64_URSHLv8i16 = 4327, + AArch64_URSHLv8i8 = 4328, + AArch64_URSHRd = 4329, + AArch64_URSHRv16i8_shift = 4330, + AArch64_URSHRv2i32_shift = 4331, + AArch64_URSHRv2i64_shift = 4332, + AArch64_URSHRv4i16_shift = 4333, + AArch64_URSHRv4i32_shift = 4334, + AArch64_URSHRv8i16_shift = 4335, + AArch64_URSHRv8i8_shift = 4336, + AArch64_URSQRTEv2i32 = 4337, + AArch64_URSQRTEv4i32 = 4338, + AArch64_URSRAd = 4339, + AArch64_URSRAv16i8_shift = 4340, + AArch64_URSRAv2i32_shift = 4341, + AArch64_URSRAv2i64_shift = 4342, + AArch64_URSRAv4i16_shift = 4343, + AArch64_URSRAv4i32_shift = 4344, + AArch64_URSRAv8i16_shift = 4345, + AArch64_URSRAv8i8_shift = 4346, + AArch64_USHLLv16i8_shift = 4347, + AArch64_USHLLv2i32_shift = 4348, + AArch64_USHLLv4i16_shift = 4349, + AArch64_USHLLv4i32_shift = 4350, + AArch64_USHLLv8i16_shift = 4351, + AArch64_USHLLv8i8_shift = 4352, + AArch64_USHLv16i8 = 4353, + AArch64_USHLv1i64 = 4354, + AArch64_USHLv2i32 = 4355, + AArch64_USHLv2i64 = 4356, + AArch64_USHLv4i16 = 4357, + AArch64_USHLv4i32 = 4358, + AArch64_USHLv8i16 = 4359, + AArch64_USHLv8i8 = 4360, + AArch64_USHRd = 4361, + AArch64_USHRv16i8_shift = 4362, + AArch64_USHRv2i32_shift = 4363, + AArch64_USHRv2i64_shift = 4364, + AArch64_USHRv4i16_shift = 4365, + AArch64_USHRv4i32_shift = 4366, + AArch64_USHRv8i16_shift = 4367, + AArch64_USHRv8i8_shift = 4368, + AArch64_USQADDv16i8 = 4369, + AArch64_USQADDv1i16 = 4370, + AArch64_USQADDv1i32 = 4371, + AArch64_USQADDv1i64 = 4372, + AArch64_USQADDv1i8 = 4373, + AArch64_USQADDv2i32 = 4374, + AArch64_USQADDv2i64 = 4375, + AArch64_USQADDv4i16 = 4376, + AArch64_USQADDv4i32 = 4377, + AArch64_USQADDv8i16 = 4378, + AArch64_USQADDv8i8 = 4379, + AArch64_USRAd = 4380, + AArch64_USRAv16i8_shift = 4381, + AArch64_USRAv2i32_shift = 4382, + AArch64_USRAv2i64_shift = 4383, + AArch64_USRAv4i16_shift = 4384, + AArch64_USRAv4i32_shift = 4385, + AArch64_USRAv8i16_shift = 4386, + AArch64_USRAv8i8_shift = 4387, + AArch64_USUBLv16i8_v8i16 = 4388, + AArch64_USUBLv2i32_v2i64 = 4389, + AArch64_USUBLv4i16_v4i32 = 4390, + AArch64_USUBLv4i32_v2i64 = 4391, + AArch64_USUBLv8i16_v4i32 = 4392, + AArch64_USUBLv8i8_v8i16 = 4393, + AArch64_USUBWv16i8_v8i16 = 4394, + AArch64_USUBWv2i32_v2i64 = 4395, + AArch64_USUBWv4i16_v4i32 = 4396, + AArch64_USUBWv4i32_v2i64 = 4397, + AArch64_USUBWv8i16_v4i32 = 4398, + AArch64_USUBWv8i8_v8i16 = 4399, + AArch64_UUNPKHI_ZZ_D = 4400, + AArch64_UUNPKHI_ZZ_H = 4401, + AArch64_UUNPKHI_ZZ_S = 4402, + AArch64_UUNPKLO_ZZ_D = 4403, + AArch64_UUNPKLO_ZZ_H = 4404, + AArch64_UUNPKLO_ZZ_S = 4405, + AArch64_UXTB_ZPmZ_D = 4406, + AArch64_UXTB_ZPmZ_H = 4407, + AArch64_UXTB_ZPmZ_S = 4408, + AArch64_UXTH_ZPmZ_D = 4409, + AArch64_UXTH_ZPmZ_S = 4410, + AArch64_UXTW_ZPmZ_D = 4411, + AArch64_UZP1_PPP_B = 4412, + AArch64_UZP1_PPP_D = 4413, + AArch64_UZP1_PPP_H = 4414, + AArch64_UZP1_PPP_S = 4415, + AArch64_UZP1_ZZZ_B = 4416, + AArch64_UZP1_ZZZ_D = 4417, + AArch64_UZP1_ZZZ_H = 4418, + AArch64_UZP1_ZZZ_S = 4419, + AArch64_UZP1v16i8 = 4420, + AArch64_UZP1v2i32 = 4421, + AArch64_UZP1v2i64 = 4422, + AArch64_UZP1v4i16 = 4423, + AArch64_UZP1v4i32 = 4424, + AArch64_UZP1v8i16 = 4425, + AArch64_UZP1v8i8 = 4426, + AArch64_UZP2_PPP_B = 4427, + AArch64_UZP2_PPP_D = 4428, + AArch64_UZP2_PPP_H = 4429, + AArch64_UZP2_PPP_S = 4430, + AArch64_UZP2_ZZZ_B = 4431, + AArch64_UZP2_ZZZ_D = 4432, + AArch64_UZP2_ZZZ_H = 4433, + AArch64_UZP2_ZZZ_S = 4434, + AArch64_UZP2v16i8 = 4435, + AArch64_UZP2v2i32 = 4436, + AArch64_UZP2v2i64 = 4437, + AArch64_UZP2v4i16 = 4438, + AArch64_UZP2v4i32 = 4439, + AArch64_UZP2v8i16 = 4440, + AArch64_UZP2v8i8 = 4441, + AArch64_WHILELE_PWW_B = 4442, + AArch64_WHILELE_PWW_D = 4443, + AArch64_WHILELE_PWW_H = 4444, + AArch64_WHILELE_PWW_S = 4445, + AArch64_WHILELE_PXX_B = 4446, + AArch64_WHILELE_PXX_D = 4447, + AArch64_WHILELE_PXX_H = 4448, + AArch64_WHILELE_PXX_S = 4449, + AArch64_WHILELO_PWW_B = 4450, + AArch64_WHILELO_PWW_D = 4451, + AArch64_WHILELO_PWW_H = 4452, + AArch64_WHILELO_PWW_S = 4453, + AArch64_WHILELO_PXX_B = 4454, + AArch64_WHILELO_PXX_D = 4455, + AArch64_WHILELO_PXX_H = 4456, + AArch64_WHILELO_PXX_S = 4457, + AArch64_WHILELS_PWW_B = 4458, + AArch64_WHILELS_PWW_D = 4459, + AArch64_WHILELS_PWW_H = 4460, + AArch64_WHILELS_PWW_S = 4461, + AArch64_WHILELS_PXX_B = 4462, + AArch64_WHILELS_PXX_D = 4463, + AArch64_WHILELS_PXX_H = 4464, + AArch64_WHILELS_PXX_S = 4465, + AArch64_WHILELT_PWW_B = 4466, + AArch64_WHILELT_PWW_D = 4467, + AArch64_WHILELT_PWW_H = 4468, + AArch64_WHILELT_PWW_S = 4469, + AArch64_WHILELT_PXX_B = 4470, + AArch64_WHILELT_PXX_D = 4471, + AArch64_WHILELT_PXX_H = 4472, + AArch64_WHILELT_PXX_S = 4473, + AArch64_WRFFR = 4474, + AArch64_XAR = 4475, + AArch64_XPACD = 4476, + AArch64_XPACI = 4477, + AArch64_XPACLRI = 4478, + AArch64_XTNv16i8 = 4479, + AArch64_XTNv2i32 = 4480, + AArch64_XTNv4i16 = 4481, + AArch64_XTNv4i32 = 4482, + AArch64_XTNv8i16 = 4483, + AArch64_XTNv8i8 = 4484, + AArch64_ZIP1_PPP_B = 4485, + AArch64_ZIP1_PPP_D = 4486, + AArch64_ZIP1_PPP_H = 4487, + AArch64_ZIP1_PPP_S = 4488, + AArch64_ZIP1_ZZZ_B = 4489, + AArch64_ZIP1_ZZZ_D = 4490, + AArch64_ZIP1_ZZZ_H = 4491, + AArch64_ZIP1_ZZZ_S = 4492, + AArch64_ZIP1v16i8 = 4493, + AArch64_ZIP1v2i32 = 4494, + AArch64_ZIP1v2i64 = 4495, + AArch64_ZIP1v4i16 = 4496, + AArch64_ZIP1v4i32 = 4497, + AArch64_ZIP1v8i16 = 4498, + AArch64_ZIP1v8i8 = 4499, + AArch64_ZIP2_PPP_B = 4500, + AArch64_ZIP2_PPP_D = 4501, + AArch64_ZIP2_PPP_H = 4502, + AArch64_ZIP2_PPP_S = 4503, + AArch64_ZIP2_ZZZ_B = 4504, + AArch64_ZIP2_ZZZ_D = 4505, + AArch64_ZIP2_ZZZ_H = 4506, + AArch64_ZIP2_ZZZ_S = 4507, + AArch64_ZIP2v16i8 = 4508, + AArch64_ZIP2v2i32 = 4509, + AArch64_ZIP2v2i64 = 4510, + AArch64_ZIP2v4i16 = 4511, + AArch64_ZIP2v4i32 = 4512, + AArch64_ZIP2v8i16 = 4513, + AArch64_ZIP2v8i8 = 4514, + AArch64_anonymous_1349 = 4515, + AArch64_INSTRUCTION_LIST_END = 4516 }; #endif // GET_INSTRINFO_ENUM @@ -4539,4940 +4540,3924 @@ enum { #define nullptr 0 -static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<, 2013-2019 */ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +/*===- TableGen'erated file -------------------------------------*- C++ +-*-===*|* *| |* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ - enum { AArch64_FeatureAES = 0, AArch64_FeatureAggressiveFMA = 1, @@ -79,4 +79,3 @@ enum { AArch64_ProcThunderXT83 = 65, AArch64_ProcThunderXT88 = 66, }; - diff --git a/arch/AArch64/AArch64GenSystemOperands.inc b/arch/AArch64/AArch64GenSystemOperands.inc index eacb536395..9380604754 100644 --- a/arch/AArch64/AArch64GenSystemOperands.inc +++ b/arch/AArch64/AArch64GenSystemOperands.inc @@ -2,40 +2,28 @@ /* By Nguyen Anh Quynh , 2013-2019 */ static const AT ATsList[] = { - { "s1e1r", 0x3C0 }, // 0 - { "s1e2r", 0x23C0 }, // 1 - { "s1e3r", 0x33C0 }, // 2 - { "s1e1w", 0x3C1 }, // 3 - { "s1e2w", 0x23C1 }, // 4 - { "s1e3w", 0x33C1 }, // 5 - { "s1e0r", 0x3C2 }, // 6 - { "s1e0w", 0x3C3 }, // 7 - { "s12e1r", 0x23C4 }, // 8 - { "s12e1w", 0x23C5 }, // 9 - { "s12e0r", 0x23C6 }, // 10 - { "s12e0w", 0x23C7 }, // 11 - { "s1e1rp", 0x3C8 }, // 12 - { "s1e1wp", 0x3C9 }, // 13 + {"s1e1r", 0x3C0}, // 0 + {"s1e2r", 0x23C0}, // 1 + {"s1e3r", 0x33C0}, // 2 + {"s1e1w", 0x3C1}, // 3 + {"s1e2w", 0x23C1}, // 4 + {"s1e3w", 0x33C1}, // 5 + {"s1e0r", 0x3C2}, // 6 + {"s1e0w", 0x3C3}, // 7 + {"s12e1r", 0x23C4}, // 8 + {"s12e1w", 0x23C5}, // 9 + {"s12e0r", 0x23C6}, // 10 + {"s12e0w", 0x23C7}, // 11 + {"s1e1rp", 0x3C8}, // 12 + {"s1e1wp", 0x3C9}, // 13 }; -const AT *lookupATByEncoding(uint16_t Encoding) -{ +const AT *lookupATByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x3C0, 0 }, - { 0x3C1, 3 }, - { 0x3C2, 6 }, - { 0x3C3, 7 }, - { 0x3C8, 12 }, - { 0x3C9, 13 }, - { 0x23C0, 1 }, - { 0x23C1, 4 }, - { 0x23C4, 8 }, - { 0x23C5, 9 }, - { 0x23C6, 10 }, - { 0x23C7, 11 }, - { 0x33C0, 2 }, - { 0x33C1, 5 }, + {0x3C0, 0}, {0x3C1, 3}, {0x3C2, 6}, {0x3C3, 7}, {0x3C8, 12}, + {0x3C9, 13}, {0x23C0, 1}, {0x23C1, 4}, {0x23C4, 8}, {0x23C5, 9}, + {0x23C6, 10}, {0x23C7, 11}, {0x33C0, 2}, {0x33C1, 5}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -46,36 +34,25 @@ const AT *lookupATByEncoding(uint16_t Encoding) } static const DB DBsList[] = { - { "oshld", 0x1 }, // 0 - { "oshst", 0x2 }, // 1 - { "osh", 0x3 }, // 2 - { "nshld", 0x5 }, // 3 - { "nshst", 0x6 }, // 4 - { "nsh", 0x7 }, // 5 - { "ishld", 0x9 }, // 6 - { "ishst", 0xA }, // 7 - { "ish", 0xB }, // 8 - { "ld", 0xD }, // 9 - { "st", 0xE }, // 10 - { "sy", 0xF }, // 11 + {"oshld", 0x1}, // 0 + {"oshst", 0x2}, // 1 + {"osh", 0x3}, // 2 + {"nshld", 0x5}, // 3 + {"nshst", 0x6}, // 4 + {"nsh", 0x7}, // 5 + {"ishld", 0x9}, // 6 + {"ishst", 0xA}, // 7 + {"ish", 0xB}, // 8 + {"ld", 0xD}, // 9 + {"st", 0xE}, // 10 + {"sy", 0xF}, // 11 }; -const DB *lookupDBByEncoding(uint16_t Encoding) -{ +const DB *lookupDBByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x1, 0 }, - { 0x2, 1 }, - { 0x3, 2 }, - { 0x5, 3 }, - { 0x6, 4 }, - { 0x7, 5 }, - { 0x9, 6 }, - { 0xA, 7 }, - { 0xB, 8 }, - { 0xD, 9 }, - { 0xE, 10 }, - { 0xF, 11 }, + {0x1, 0}, {0x2, 1}, {0x3, 2}, {0x5, 3}, {0x6, 4}, {0x7, 5}, + {0x9, 6}, {0xA, 7}, {0xB, 8}, {0xD, 9}, {0xE, 10}, {0xF, 11}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -86,30 +63,22 @@ const DB *lookupDBByEncoding(uint16_t Encoding) } static const DC DCsList[] = { - { "zva", 0x1BA1 }, // 0 - { "ivac", 0x3B1 }, // 1 - { "isw", 0x3B2 }, // 2 - { "cvac", 0x1BD1 }, // 3 - { "csw", 0x3D2 }, // 4 - { "cvau", 0x1BD9 }, // 5 - { "civac", 0x1BF1 }, // 6 - { "cisw", 0x3F2 }, // 7 - { "cvap", 0x1BE1 }, // 8 + {"zva", 0x1BA1}, // 0 + {"ivac", 0x3B1}, // 1 + {"isw", 0x3B2}, // 2 + {"cvac", 0x1BD1}, // 3 + {"csw", 0x3D2}, // 4 + {"cvau", 0x1BD9}, // 5 + {"civac", 0x1BF1}, // 6 + {"cisw", 0x3F2}, // 7 + {"cvap", 0x1BE1}, // 8 }; -const DC *lookupDCByEncoding(uint16_t Encoding) -{ +const DC *lookupDCByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x3B1, 1 }, - { 0x3B2, 2 }, - { 0x3D2, 4 }, - { 0x3F2, 7 }, - { 0x1BA1, 0 }, - { 0x1BD1, 3 }, - { 0x1BD9, 5 }, - { 0x1BE1, 8 }, - { 0x1BF1, 6 }, + {0x3B1, 1}, {0x3B2, 2}, {0x3D2, 4}, {0x3F2, 7}, {0x1BA1, 0}, + {0x1BD1, 3}, {0x1BD9, 5}, {0x1BE1, 8}, {0x1BF1, 6}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -120,18 +89,17 @@ const DC *lookupDCByEncoding(uint16_t Encoding) } static const IC ICsList[] = { - { "ialluis", 0x388, false }, // 0 - { "iallu", 0x3a8, false }, // 1 - { "ivau", 0x1ba9, true }, // 2 + {"ialluis", 0x388, false}, // 0 + {"iallu", 0x3a8, false}, // 1 + {"ivau", 0x1ba9, true}, // 2 }; -const IC *lookupICByEncoding(uint16_t Encoding) -{ +const IC *lookupICByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x388, 0 }, - { 0x3A8, 1 }, - { 0x1BA9, 2 }, + {0x388, 0}, + {0x3A8, 1}, + {0x1BA9, 2}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -142,168 +110,105 @@ const IC *lookupICByEncoding(uint16_t Encoding) } static const TLBI TLBIsList[] = { - { "ipas2e1is", 0x2401, true }, // 0 - { "ipas2le1is", 0x2405, true }, // 1 - { "vmalle1is", 0x418, false }, // 2 - { "alle2is", 0x2418, false }, // 3 - { "alle3is", 0x3418, false }, // 4 - { "vae1is", 0x419, true }, // 5 - { "vae2is", 0x2419, true }, // 6 - { "vae3is", 0x3419, true }, // 7 - { "aside1is", 0x41A, true }, // 8 - { "vaae1is", 0x41B, true }, // 9 - { "alle1is", 0x241C, false }, // 10 - { "vale1is", 0x41D, true }, // 11 - { "vale2is", 0x241D, true }, // 12 - { "vale3is", 0x341D, true }, // 13 - { "vmalls12e1is", 0x241E, false }, // 14 - { "vaale1is", 0x41F, true }, // 15 - { "ipas2e1", 0x2421, true }, // 16 - { "ipas2le1", 0x2425, true }, // 17 - { "vmalle1", 0x438, false }, // 18 - { "alle2", 0x2438, false }, // 19 - { "alle3", 0x3438, false }, // 20 - { "vae1", 0x439, true }, // 21 - { "vae2", 0x2439, true }, // 22 - { "vae3", 0x3439, true }, // 23 - { "aside1", 0x43A, true }, // 24 - { "vaae1", 0x43B, true }, // 25 - { "alle1", 0x243C, false }, // 26 - { "vale1", 0x43D, true }, // 27 - { "vale2", 0x243D, true }, // 28 - { "vale3", 0x343D, true }, // 29 - { "vmalls12e1", 0x243E, false }, // 30 - { "vaale1", 0x43F, true }, // 31 - { "vmalle1os", 0x408, false }, // 32 - { "vae1os", 0x409, true }, // 33 - { "aside1os", 0x40A, true }, // 34 - { "vaae1os", 0x40B, true }, // 35 - { "vale1os", 0x40D, true }, // 36 - { "vaale1os", 0x40F, true }, // 37 - { "ipas2e1os", 0x2420, true }, // 38 - { "ipas2le1os", 0x2424, true }, // 39 - { "vae2os", 0x2409, true }, // 40 - { "vale2os", 0x240D, true }, // 41 - { "vmalls12e1os", 0x240E, false }, // 42 - { "vae3os", 0x3409, true }, // 43 - { "vale3os", 0x340D, true }, // 44 - { "alle2os", 0x2408, false }, // 45 - { "alle1os", 0x240C, false }, // 46 - { "alle3os", 0x3408, false }, // 47 - { "rvae1", 0x431, true }, // 48 - { "rvaae1", 0x433, true }, // 49 - { "rvale1", 0x435, true }, // 50 - { "rvaale1", 0x437, true }, // 51 - { "rvae1is", 0x411, true }, // 52 - { "rvaae1is", 0x413, true }, // 53 - { "rvale1is", 0x415, true }, // 54 - { "rvaale1is", 0x417, true }, // 55 - { "rvae1os", 0x429, true }, // 56 - { "rvaae1os", 0x42B, true }, // 57 - { "rvale1os", 0x42D, true }, // 58 - { "rvaale1os", 0x42F, true }, // 59 - { "ripas2e1is", 0x2402, true }, // 60 - { "ripas2le1is", 0x2406, true }, // 61 - { "ripas2e1", 0x2422, true }, // 62 - { "ripas2le1", 0x2426, true }, // 63 - { "ripas2e1os", 0x2423, true }, // 64 - { "ripas2le1os", 0x2427, true }, // 65 - { "rvae2", 0x2431, true }, // 66 - { "rvale2", 0x2435, true }, // 67 - { "rvae2is", 0x2411, true }, // 68 - { "rvale2is", 0x2415, true }, // 69 - { "rvae2os", 0x2429, true }, // 70 - { "rvale2os", 0x242D, true }, // 71 - { "rvae3", 0x3431, true }, // 72 - { "rvale3", 0x3435, true }, // 73 - { "rvae3is", 0x3411, true }, // 74 - { "rvale3is", 0x3415, true }, // 75 - { "rvae3os", 0x3429, true }, // 76 - { "rvale3os", 0x342D, true }, // 77 + {"ipas2e1is", 0x2401, true}, // 0 + {"ipas2le1is", 0x2405, true}, // 1 + {"vmalle1is", 0x418, false}, // 2 + {"alle2is", 0x2418, false}, // 3 + {"alle3is", 0x3418, false}, // 4 + {"vae1is", 0x419, true}, // 5 + {"vae2is", 0x2419, true}, // 6 + {"vae3is", 0x3419, true}, // 7 + {"aside1is", 0x41A, true}, // 8 + {"vaae1is", 0x41B, true}, // 9 + {"alle1is", 0x241C, false}, // 10 + {"vale1is", 0x41D, true}, // 11 + {"vale2is", 0x241D, true}, // 12 + {"vale3is", 0x341D, true}, // 13 + {"vmalls12e1is", 0x241E, false}, // 14 + {"vaale1is", 0x41F, true}, // 15 + {"ipas2e1", 0x2421, true}, // 16 + {"ipas2le1", 0x2425, true}, // 17 + {"vmalle1", 0x438, false}, // 18 + {"alle2", 0x2438, false}, // 19 + {"alle3", 0x3438, false}, // 20 + {"vae1", 0x439, true}, // 21 + {"vae2", 0x2439, true}, // 22 + {"vae3", 0x3439, true}, // 23 + {"aside1", 0x43A, true}, // 24 + {"vaae1", 0x43B, true}, // 25 + {"alle1", 0x243C, false}, // 26 + {"vale1", 0x43D, true}, // 27 + {"vale2", 0x243D, true}, // 28 + {"vale3", 0x343D, true}, // 29 + {"vmalls12e1", 0x243E, false}, // 30 + {"vaale1", 0x43F, true}, // 31 + {"vmalle1os", 0x408, false}, // 32 + {"vae1os", 0x409, true}, // 33 + {"aside1os", 0x40A, true}, // 34 + {"vaae1os", 0x40B, true}, // 35 + {"vale1os", 0x40D, true}, // 36 + {"vaale1os", 0x40F, true}, // 37 + {"ipas2e1os", 0x2420, true}, // 38 + {"ipas2le1os", 0x2424, true}, // 39 + {"vae2os", 0x2409, true}, // 40 + {"vale2os", 0x240D, true}, // 41 + {"vmalls12e1os", 0x240E, false}, // 42 + {"vae3os", 0x3409, true}, // 43 + {"vale3os", 0x340D, true}, // 44 + {"alle2os", 0x2408, false}, // 45 + {"alle1os", 0x240C, false}, // 46 + {"alle3os", 0x3408, false}, // 47 + {"rvae1", 0x431, true}, // 48 + {"rvaae1", 0x433, true}, // 49 + {"rvale1", 0x435, true}, // 50 + {"rvaale1", 0x437, true}, // 51 + {"rvae1is", 0x411, true}, // 52 + {"rvaae1is", 0x413, true}, // 53 + {"rvale1is", 0x415, true}, // 54 + {"rvaale1is", 0x417, true}, // 55 + {"rvae1os", 0x429, true}, // 56 + {"rvaae1os", 0x42B, true}, // 57 + {"rvale1os", 0x42D, true}, // 58 + {"rvaale1os", 0x42F, true}, // 59 + {"ripas2e1is", 0x2402, true}, // 60 + {"ripas2le1is", 0x2406, true}, // 61 + {"ripas2e1", 0x2422, true}, // 62 + {"ripas2le1", 0x2426, true}, // 63 + {"ripas2e1os", 0x2423, true}, // 64 + {"ripas2le1os", 0x2427, true}, // 65 + {"rvae2", 0x2431, true}, // 66 + {"rvale2", 0x2435, true}, // 67 + {"rvae2is", 0x2411, true}, // 68 + {"rvale2is", 0x2415, true}, // 69 + {"rvae2os", 0x2429, true}, // 70 + {"rvale2os", 0x242D, true}, // 71 + {"rvae3", 0x3431, true}, // 72 + {"rvale3", 0x3435, true}, // 73 + {"rvae3is", 0x3411, true}, // 74 + {"rvale3is", 0x3415, true}, // 75 + {"rvae3os", 0x3429, true}, // 76 + {"rvale3os", 0x342D, true}, // 77 }; -const TLBI *lookupTLBIByEncoding(uint16_t Encoding) -{ +const TLBI *lookupTLBIByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x408, 32 }, - { 0x409, 33 }, - { 0x40A, 34 }, - { 0x40B, 35 }, - { 0x40D, 36 }, - { 0x40F, 37 }, - { 0x411, 52 }, - { 0x413, 53 }, - { 0x415, 54 }, - { 0x417, 55 }, - { 0x418, 2 }, - { 0x419, 5 }, - { 0x41A, 8 }, - { 0x41B, 9 }, - { 0x41D, 11 }, - { 0x41F, 15 }, - { 0x429, 56 }, - { 0x42B, 57 }, - { 0x42D, 58 }, - { 0x42F, 59 }, - { 0x431, 48 }, - { 0x433, 49 }, - { 0x435, 50 }, - { 0x437, 51 }, - { 0x438, 18 }, - { 0x439, 21 }, - { 0x43A, 24 }, - { 0x43B, 25 }, - { 0x43D, 27 }, - { 0x43F, 31 }, - { 0x2401, 0 }, - { 0x2402, 60 }, - { 0x2405, 1 }, - { 0x2406, 61 }, - { 0x2408, 45 }, - { 0x2409, 40 }, - { 0x240C, 46 }, - { 0x240D, 41 }, - { 0x240E, 42 }, - { 0x2411, 68 }, - { 0x2415, 69 }, - { 0x2418, 3 }, - { 0x2419, 6 }, - { 0x241C, 10 }, - { 0x241D, 12 }, - { 0x241E, 14 }, - { 0x2420, 38 }, - { 0x2421, 16 }, - { 0x2422, 62 }, - { 0x2423, 64 }, - { 0x2424, 39 }, - { 0x2425, 17 }, - { 0x2426, 63 }, - { 0x2427, 65 }, - { 0x2429, 70 }, - { 0x242D, 71 }, - { 0x2431, 66 }, - { 0x2435, 67 }, - { 0x2438, 19 }, - { 0x2439, 22 }, - { 0x243C, 26 }, - { 0x243D, 28 }, - { 0x243E, 30 }, - { 0x3408, 47 }, - { 0x3409, 43 }, - { 0x340D, 44 }, - { 0x3411, 74 }, - { 0x3415, 75 }, - { 0x3418, 4 }, - { 0x3419, 7 }, - { 0x341D, 13 }, - { 0x3429, 76 }, - { 0x342D, 77 }, - { 0x3431, 72 }, - { 0x3435, 73 }, - { 0x3438, 20 }, - { 0x3439, 23 }, - { 0x343D, 29 }, + {0x408, 32}, {0x409, 33}, {0x40A, 34}, {0x40B, 35}, {0x40D, 36}, + {0x40F, 37}, {0x411, 52}, {0x413, 53}, {0x415, 54}, {0x417, 55}, + {0x418, 2}, {0x419, 5}, {0x41A, 8}, {0x41B, 9}, {0x41D, 11}, + {0x41F, 15}, {0x429, 56}, {0x42B, 57}, {0x42D, 58}, {0x42F, 59}, + {0x431, 48}, {0x433, 49}, {0x435, 50}, {0x437, 51}, {0x438, 18}, + {0x439, 21}, {0x43A, 24}, {0x43B, 25}, {0x43D, 27}, {0x43F, 31}, + {0x2401, 0}, {0x2402, 60}, {0x2405, 1}, {0x2406, 61}, {0x2408, 45}, + {0x2409, 40}, {0x240C, 46}, {0x240D, 41}, {0x240E, 42}, {0x2411, 68}, + {0x2415, 69}, {0x2418, 3}, {0x2419, 6}, {0x241C, 10}, {0x241D, 12}, + {0x241E, 14}, {0x2420, 38}, {0x2421, 16}, {0x2422, 62}, {0x2423, 64}, + {0x2424, 39}, {0x2425, 17}, {0x2426, 63}, {0x2427, 65}, {0x2429, 70}, + {0x242D, 71}, {0x2431, 66}, {0x2435, 67}, {0x2438, 19}, {0x2439, 22}, + {0x243C, 26}, {0x243D, 28}, {0x243E, 30}, {0x3408, 47}, {0x3409, 43}, + {0x340D, 44}, {0x3411, 74}, {0x3415, 75}, {0x3418, 4}, {0x3419, 7}, + {0x341D, 13}, {0x3429, 76}, {0x342D, 77}, {0x3431, 72}, {0x3435, 73}, + {0x3438, 20}, {0x3439, 23}, {0x343D, 29}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -314,36 +219,25 @@ const TLBI *lookupTLBIByEncoding(uint16_t Encoding) } static const SVEPRFM SVEPRFMsList[] = { - { "pldl1keep", 0x0 }, // 0 - { "pldl1strm", 0x1 }, // 1 - { "pldl2keep", 0x2 }, // 2 - { "pldl2strm", 0x3 }, // 3 - { "pldl3keep", 0x4 }, // 4 - { "pldl3strm", 0x5 }, // 5 - { "pstl1keep", 0x8 }, // 6 - { "pstl1strm", 0x9 }, // 7 - { "pstl2keep", 0xA }, // 8 - { "pstl2strm", 0xB }, // 9 - { "pstl3keep", 0xC }, // 10 - { "pstl3strm", 0xD }, // 11 + {"pldl1keep", 0x0}, // 0 + {"pldl1strm", 0x1}, // 1 + {"pldl2keep", 0x2}, // 2 + {"pldl2strm", 0x3}, // 3 + {"pldl3keep", 0x4}, // 4 + {"pldl3strm", 0x5}, // 5 + {"pstl1keep", 0x8}, // 6 + {"pstl1strm", 0x9}, // 7 + {"pstl2keep", 0xA}, // 8 + {"pstl2strm", 0xB}, // 9 + {"pstl3keep", 0xC}, // 10 + {"pstl3strm", 0xD}, // 11 }; -const SVEPRFM *lookupSVEPRFMByEncoding(uint16_t Encoding) -{ +const SVEPRFM *lookupSVEPRFMByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x0, 0 }, - { 0x1, 1 }, - { 0x2, 2 }, - { 0x3, 3 }, - { 0x4, 4 }, - { 0x5, 5 }, - { 0x8, 6 }, - { 0x9, 7 }, - { 0xA, 8 }, - { 0xB, 9 }, - { 0xC, 10 }, - { 0xD, 11 }, + {0x0, 0}, {0x1, 1}, {0x2, 2}, {0x3, 3}, {0x4, 4}, {0x5, 5}, + {0x8, 6}, {0x9, 7}, {0xA, 8}, {0xB, 9}, {0xC, 10}, {0xD, 11}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -354,48 +248,32 @@ const SVEPRFM *lookupSVEPRFMByEncoding(uint16_t Encoding) } static const PRFM PRFMsList[] = { - { "pldl1keep", 0x0 }, // 0 - { "pldl1strm", 0x1 }, // 1 - { "pldl2keep", 0x2 }, // 2 - { "pldl2strm", 0x3 }, // 3 - { "pldl3keep", 0x4 }, // 4 - { "pldl3strm", 0x5 }, // 5 - { "plil1keep", 0x8 }, // 6 - { "plil1strm", 0x9 }, // 7 - { "plil2keep", 0xa }, // 8 - { "plil2strm", 0xb }, // 9 - { "plil3keep", 0xc }, // 10 - { "plil3strm", 0xd }, // 11 - { "pstl1keep", 0x10 }, // 12 - { "pstl1strm", 0x11 }, // 13 - { "pstl2keep", 0x12 }, // 14 - { "pstl2strm", 0x13 }, // 15 - { "pstl3keep", 0x14 }, // 16 - { "pstl3strm", 0x15 }, // 17 + {"pldl1keep", 0x0}, // 0 + {"pldl1strm", 0x1}, // 1 + {"pldl2keep", 0x2}, // 2 + {"pldl2strm", 0x3}, // 3 + {"pldl3keep", 0x4}, // 4 + {"pldl3strm", 0x5}, // 5 + {"plil1keep", 0x8}, // 6 + {"plil1strm", 0x9}, // 7 + {"plil2keep", 0xa}, // 8 + {"plil2strm", 0xb}, // 9 + {"plil3keep", 0xc}, // 10 + {"plil3strm", 0xd}, // 11 + {"pstl1keep", 0x10}, // 12 + {"pstl1strm", 0x11}, // 13 + {"pstl2keep", 0x12}, // 14 + {"pstl2strm", 0x13}, // 15 + {"pstl3keep", 0x14}, // 16 + {"pstl3strm", 0x15}, // 17 }; -const PRFM *lookupPRFMByEncoding(uint16_t Encoding) -{ +const PRFM *lookupPRFMByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x0, 0 }, - { 0x1, 1 }, - { 0x2, 2 }, - { 0x3, 3 }, - { 0x4, 4 }, - { 0x5, 5 }, - { 0x8, 6 }, - { 0x9, 7 }, - { 0xA, 8 }, - { 0xB, 9 }, - { 0xC, 10 }, - { 0xD, 11 }, - { 0x10, 12 }, - { 0x11, 13 }, - { 0x12, 14 }, - { 0x13, 15 }, - { 0x14, 16 }, - { 0x15, 17 }, + {0x0, 0}, {0x1, 1}, {0x2, 2}, {0x3, 3}, {0x4, 4}, {0x5, 5}, + {0x8, 6}, {0x9, 7}, {0xA, 8}, {0xB, 9}, {0xC, 10}, {0xD, 11}, + {0x10, 12}, {0x11, 13}, {0x12, 14}, {0x13, 15}, {0x14, 16}, {0x15, 17}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -406,14 +284,13 @@ const PRFM *lookupPRFMByEncoding(uint16_t Encoding) } static const PSB PSBsList[] = { - { "csync", 0x11 }, // 0 + {"csync", 0x11}, // 0 }; -const PSB *AArch64PSBHint_lookupPSBByEncoding(uint16_t Encoding) -{ +const PSB *AArch64PSBHint_lookupPSBByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x11, 0 }, + {0x11, 0}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -424,14 +301,13 @@ const PSB *AArch64PSBHint_lookupPSBByEncoding(uint16_t Encoding) } static const ISB ISBsList[] = { - { "sy", 0xf }, // 0 + {"sy", 0xf}, // 0 }; -const ISB *lookupISBByEncoding(uint16_t Encoding) -{ +const ISB *lookupISBByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0xF, 0 }, + {0xF, 0}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -442,13 +318,12 @@ const ISB *lookupISBByEncoding(uint16_t Encoding) } static const TSB TSBsList[] = { - { "csync", 0x0 }, // 0 + {"csync", 0x0}, // 0 }; -const TSB *lookupTSBByEncoding(uint16_t Encoding) -{ +const TSB *lookupTSBByEncoding(uint16_t Encoding) { static const struct IndexType Index[] = { - { 0x0, 0 }, + {0x0, 0}, }; if (Encoding >= ARR_SIZE(TSBsList)) @@ -458,1486 +333,896 @@ const TSB *lookupTSBByEncoding(uint16_t Encoding) } static const SysReg SysRegsList[] = { - { "mdccsr_el0", 0x9808, true, false }, // 0 - { "dbgdtrrx_el0", 0x9828, true, false }, // 1 - { "mdrar_el1", 0x8080, true, false }, // 2 - { "oslsr_el1", 0x808C, true, false }, // 3 - { "dbgauthstatus_el1", 0x83F6, true, false }, // 4 - { "pmceid0_el0", 0xDCE6, true, false }, // 5 - { "pmceid1_el0", 0xDCE7, true, false }, // 6 - { "midr_el1", 0xC000, true, false }, // 7 - { "ccsidr_el1", 0xC800, true, false }, // 8 - { "ccsidr2_el1", 0xC802, true, false }, // 9 - { "clidr_el1", 0xC801, true, false }, // 10 - { "ctr_el0", 0xD801, true, false }, // 11 - { "mpidr_el1", 0xC005, true, false }, // 12 - { "revidr_el1", 0xC006, true, false }, // 13 - { "aidr_el1", 0xC807, true, false }, // 14 - { "dczid_el0", 0xD807, true, false }, // 15 - { "id_pfr0_el1", 0xC008, true, false }, // 16 - { "id_pfr1_el1", 0xC009, true, false }, // 17 - { "id_dfr0_el1", 0xC00A, true, false }, // 18 - { "id_afr0_el1", 0xC00B, true, false }, // 19 - { "id_mmfr0_el1", 0xC00C, true, false }, // 20 - { "id_mmfr1_el1", 0xC00D, true, false }, // 21 - { "id_mmfr2_el1", 0xC00E, true, false }, // 22 - { "id_mmfr3_el1", 0xC00F, true, false }, // 23 - { "id_isar0_el1", 0xC010, true, false }, // 24 - { "id_isar1_el1", 0xC011, true, false }, // 25 - { "id_isar2_el1", 0xC012, true, false }, // 26 - { "id_isar3_el1", 0xC013, true, false }, // 27 - { "id_isar4_el1", 0xC014, true, false }, // 28 - { "id_isar5_el1", 0xC015, true, false }, // 29 - { "id_isar6_el1", 0xC017, true, false }, // 30 - { "id_aa64pfr0_el1", 0xC020, true, false }, // 31 - { "id_aa64pfr1_el1", 0xC021, true, false }, // 32 - { "id_aa64dfr0_el1", 0xC028, true, false }, // 33 - { "id_aa64dfr1_el1", 0xC029, true, false }, // 34 - { "id_aa64afr0_el1", 0xC02C, true, false }, // 35 - { "id_aa64afr1_el1", 0xC02D, true, false }, // 36 - { "id_aa64isar0_el1", 0xC030, true, false }, // 37 - { "id_aa64isar1_el1", 0xC031, true, false }, // 38 - { "id_aa64mmfr0_el1", 0xC038, true, false }, // 39 - { "id_aa64mmfr1_el1", 0xC039, true, false }, // 40 - { "id_aa64mmfr2_el1", 0xC03A, true, false }, // 41 - { "mvfr0_el1", 0xC018, true, false }, // 42 - { "mvfr1_el1", 0xC019, true, false }, // 43 - { "mvfr2_el1", 0xC01A, true, false }, // 44 - { "rvbar_el1", 0xC601, true, false }, // 45 - { "rvbar_el2", 0xE601, true, false }, // 46 - { "rvbar_el3", 0xF601, true, false }, // 47 - { "isr_el1", 0xC608, true, false }, // 48 - { "cntpct_el0", 0xDF01, true, false }, // 49 - { "cntvct_el0", 0xDF02, true, false }, // 50 - { "id_mmfr4_el1", 0xC016, true, false }, // 51 - { "trcstatr", 0x8818, true, false }, // 52 - { "trcidr8", 0x8806, true, false }, // 53 - { "trcidr9", 0x880E, true, false }, // 54 - { "trcidr10", 0x8816, true, false }, // 55 - { "trcidr11", 0x881E, true, false }, // 56 - { "trcidr12", 0x8826, true, false }, // 57 - { "trcidr13", 0x882E, true, false }, // 58 - { "trcidr0", 0x8847, true, false }, // 59 - { "trcidr1", 0x884F, true, false }, // 60 - { "trcidr2", 0x8857, true, false }, // 61 - { "trcidr3", 0x885F, true, false }, // 62 - { "trcidr4", 0x8867, true, false }, // 63 - { "trcidr5", 0x886F, true, false }, // 64 - { "trcidr6", 0x8877, true, false }, // 65 - { "trcidr7", 0x887F, true, false }, // 66 - { "trcoslsr", 0x888C, true, false }, // 67 - { "trcpdsr", 0x88AC, true, false }, // 68 - { "trcdevaff0", 0x8BD6, true, false }, // 69 - { "trcdevaff1", 0x8BDE, true, false }, // 70 - { "trclsr", 0x8BEE, true, false }, // 71 - { "trcauthstatus", 0x8BF6, true, false }, // 72 - { "trcdevarch", 0x8BFE, true, false }, // 73 - { "trcdevid", 0x8B97, true, false }, // 74 - { "trcdevtype", 0x8B9F, true, false }, // 75 - { "trcpidr4", 0x8BA7, true, false }, // 76 - { "trcpidr5", 0x8BAF, true, false }, // 77 - { "trcpidr6", 0x8BB7, true, false }, // 78 - { "trcpidr7", 0x8BBF, true, false }, // 79 - { "trcpidr0", 0x8BC7, true, false }, // 80 - { "trcpidr1", 0x8BCF, true, false }, // 81 - { "trcpidr2", 0x8BD7, true, false }, // 82 - { "trcpidr3", 0x8BDF, true, false }, // 83 - { "trccidr0", 0x8BE7, true, false }, // 84 - { "trccidr1", 0x8BEF, true, false }, // 85 - { "trccidr2", 0x8BF7, true, false }, // 86 - { "trccidr3", 0x8BFF, true, false }, // 87 - { "icc_iar1_el1", 0xC660, true, false }, // 88 - { "icc_iar0_el1", 0xC640, true, false }, // 89 - { "icc_hppir1_el1", 0xC662, true, false }, // 90 - { "icc_hppir0_el1", 0xC642, true, false }, // 91 - { "icc_rpr_el1", 0xC65B, true, false }, // 92 - { "ich_vtr_el2", 0xE659, true, false }, // 93 - { "ich_eisr_el2", 0xE65B, true, false }, // 94 - { "ich_elrsr_el2", 0xE65D, true, false }, // 95 - { "id_aa64zfr0_el1", 0xC024, true, false }, // 96 - { "lorid_el1", 0xC527, true, false }, // 97 - { "erridr_el1", 0xC298, true, false }, // 98 - { "erxfr_el1", 0xC2A0, true, false }, // 99 - { "dbgdtrtx_el0", 0x9828, false, true }, // 100 - { "oslar_el1", 0x8084, false, true }, // 101 - { "pmswinc_el0", 0xDCE4, false, true }, // 102 - { "trcoslar", 0x8884, false, true }, // 103 - { "trclar", 0x8BE6, false, true }, // 104 - { "icc_eoir1_el1", 0xC661, false, true }, // 105 - { "icc_eoir0_el1", 0xC641, false, true }, // 106 - { "icc_dir_el1", 0xC659, false, true }, // 107 - { "icc_sgi1r_el1", 0xC65D, false, true }, // 108 - { "icc_asgi1r_el1", 0xC65E, false, true }, // 109 - { "icc_sgi0r_el1", 0xC65F, false, true }, // 110 - { "osdtrrx_el1", 0x8002, true, true }, // 111 - { "osdtrtx_el1", 0x801A, true, true }, // 112 - { "teecr32_el1", 0x9000, true, true }, // 113 - { "mdccint_el1", 0x8010, true, true }, // 114 - { "mdscr_el1", 0x8012, true, true }, // 115 - { "dbgdtr_el0", 0x9820, true, true }, // 116 - { "oseccr_el1", 0x8032, true, true }, // 117 - { "dbgvcr32_el2", 0xA038, true, true }, // 118 - { "dbgbvr0_el1", 0x8004, true, true }, // 119 - { "dbgbvr1_el1", 0x800C, true, true }, // 120 - { "dbgbvr2_el1", 0x8014, true, true }, // 121 - { "dbgbvr3_el1", 0x801C, true, true }, // 122 - { "dbgbvr4_el1", 0x8024, true, true }, // 123 - { "dbgbvr5_el1", 0x802C, true, true }, // 124 - { "dbgbvr6_el1", 0x8034, true, true }, // 125 - { "dbgbvr7_el1", 0x803C, true, true }, // 126 - { "dbgbvr8_el1", 0x8044, true, true }, // 127 - { "dbgbvr9_el1", 0x804C, true, true }, // 128 - { "dbgbvr10_el1", 0x8054, true, true }, // 129 - { "dbgbvr11_el1", 0x805C, true, true }, // 130 - { "dbgbvr12_el1", 0x8064, true, true }, // 131 - { "dbgbvr13_el1", 0x806C, true, true }, // 132 - { "dbgbvr14_el1", 0x8074, true, true }, // 133 - { "dbgbvr15_el1", 0x807C, true, true }, // 134 - { "dbgbcr0_el1", 0x8005, true, true }, // 135 - { "dbgbcr1_el1", 0x800D, true, true }, // 136 - { "dbgbcr2_el1", 0x8015, true, true }, // 137 - { "dbgbcr3_el1", 0x801D, true, true }, // 138 - { "dbgbcr4_el1", 0x8025, true, true }, // 139 - { "dbgbcr5_el1", 0x802D, true, true }, // 140 - { "dbgbcr6_el1", 0x8035, true, true }, // 141 - { "dbgbcr7_el1", 0x803D, true, true }, // 142 - { "dbgbcr8_el1", 0x8045, true, true }, // 143 - { "dbgbcr9_el1", 0x804D, true, true }, // 144 - { "dbgbcr10_el1", 0x8055, true, true }, // 145 - { "dbgbcr11_el1", 0x805D, true, true }, // 146 - { "dbgbcr12_el1", 0x8065, true, true }, // 147 - { "dbgbcr13_el1", 0x806D, true, true }, // 148 - { "dbgbcr14_el1", 0x8075, true, true }, // 149 - { "dbgbcr15_el1", 0x807D, true, true }, // 150 - { "dbgwvr0_el1", 0x8006, true, true }, // 151 - { "dbgwvr1_el1", 0x800E, true, true }, // 152 - { "dbgwvr2_el1", 0x8016, true, true }, // 153 - { "dbgwvr3_el1", 0x801E, true, true }, // 154 - { "dbgwvr4_el1", 0x8026, true, true }, // 155 - { "dbgwvr5_el1", 0x802E, true, true }, // 156 - { "dbgwvr6_el1", 0x8036, true, true }, // 157 - { "dbgwvr7_el1", 0x803E, true, true }, // 158 - { "dbgwvr8_el1", 0x8046, true, true }, // 159 - { "dbgwvr9_el1", 0x804E, true, true }, // 160 - { "dbgwvr10_el1", 0x8056, true, true }, // 161 - { "dbgwvr11_el1", 0x805E, true, true }, // 162 - { "dbgwvr12_el1", 0x8066, true, true }, // 163 - { "dbgwvr13_el1", 0x806E, true, true }, // 164 - { "dbgwvr14_el1", 0x8076, true, true }, // 165 - { "dbgwvr15_el1", 0x807E, true, true }, // 166 - { "dbgwcr0_el1", 0x8007, true, true }, // 167 - { "dbgwcr1_el1", 0x800F, true, true }, // 168 - { "dbgwcr2_el1", 0x8017, true, true }, // 169 - { "dbgwcr3_el1", 0x801F, true, true }, // 170 - { "dbgwcr4_el1", 0x8027, true, true }, // 171 - { "dbgwcr5_el1", 0x802F, true, true }, // 172 - { "dbgwcr6_el1", 0x8037, true, true }, // 173 - { "dbgwcr7_el1", 0x803F, true, true }, // 174 - { "dbgwcr8_el1", 0x8047, true, true }, // 175 - { "dbgwcr9_el1", 0x804F, true, true }, // 176 - { "dbgwcr10_el1", 0x8057, true, true }, // 177 - { "dbgwcr11_el1", 0x805F, true, true }, // 178 - { "dbgwcr12_el1", 0x8067, true, true }, // 179 - { "dbgwcr13_el1", 0x806F, true, true }, // 180 - { "dbgwcr14_el1", 0x8077, true, true }, // 181 - { "dbgwcr15_el1", 0x807F, true, true }, // 182 - { "teehbr32_el1", 0x9080, true, true }, // 183 - { "osdlr_el1", 0x809C, true, true }, // 184 - { "dbgprcr_el1", 0x80A4, true, true }, // 185 - { "dbgclaimset_el1", 0x83C6, true, true }, // 186 - { "dbgclaimclr_el1", 0x83CE, true, true }, // 187 - { "csselr_el1", 0xD000, true, true }, // 188 - { "vpidr_el2", 0xE000, true, true }, // 189 - { "vmpidr_el2", 0xE005, true, true }, // 190 - { "cpacr_el1", 0xC082, true, true }, // 191 - { "sctlr_el1", 0xC080, true, true }, // 192 - { "sctlr_el2", 0xE080, true, true }, // 193 - { "sctlr_el3", 0xF080, true, true }, // 194 - { "actlr_el1", 0xC081, true, true }, // 195 - { "actlr_el2", 0xE081, true, true }, // 196 - { "actlr_el3", 0xF081, true, true }, // 197 - { "hcr_el2", 0xE088, true, true }, // 198 - { "scr_el3", 0xF088, true, true }, // 199 - { "mdcr_el2", 0xE089, true, true }, // 200 - { "sder32_el3", 0xF089, true, true }, // 201 - { "cptr_el2", 0xE08A, true, true }, // 202 - { "cptr_el3", 0xF08A, true, true }, // 203 - { "hstr_el2", 0xE08B, true, true }, // 204 - { "hacr_el2", 0xE08F, true, true }, // 205 - { "mdcr_el3", 0xF099, true, true }, // 206 - { "ttbr0_el1", 0xC100, true, true }, // 207 - { "ttbr0_el2", 0xE100, true, true }, // 208 - { "ttbr0_el3", 0xF100, true, true }, // 209 - { "ttbr1_el1", 0xC101, true, true }, // 210 - { "tcr_el1", 0xC102, true, true }, // 211 - { "tcr_el2", 0xE102, true, true }, // 212 - { "tcr_el3", 0xF102, true, true }, // 213 - { "vttbr_el2", 0xE108, true, true }, // 214 - { "vtcr_el2", 0xE10A, true, true }, // 215 - { "dacr32_el2", 0xE180, true, true }, // 216 - { "spsr_el1", 0xC200, true, true }, // 217 - { "spsr_el2", 0xE200, true, true }, // 218 - { "spsr_el3", 0xF200, true, true }, // 219 - { "elr_el1", 0xC201, true, true }, // 220 - { "elr_el2", 0xE201, true, true }, // 221 - { "elr_el3", 0xF201, true, true }, // 222 - { "sp_el0", 0xC208, true, true }, // 223 - { "sp_el1", 0xE208, true, true }, // 224 - { "sp_el2", 0xF208, true, true }, // 225 - { "spsel", 0xC210, true, true }, // 226 - { "nzcv", 0xDA10, true, true }, // 227 - { "daif", 0xDA11, true, true }, // 228 - { "currentel", 0xC212, true, true }, // 229 - { "spsr_irq", 0xE218, true, true }, // 230 - { "spsr_abt", 0xE219, true, true }, // 231 - { "spsr_und", 0xE21A, true, true }, // 232 - { "spsr_fiq", 0xE21B, true, true }, // 233 - { "fpcr", 0xDA20, true, true }, // 234 - { "fpsr", 0xDA21, true, true }, // 235 - { "dspsr_el0", 0xDA28, true, true }, // 236 - { "dlr_el0", 0xDA29, true, true }, // 237 - { "ifsr32_el2", 0xE281, true, true }, // 238 - { "afsr0_el1", 0xC288, true, true }, // 239 - { "afsr0_el2", 0xE288, true, true }, // 240 - { "afsr0_el3", 0xF288, true, true }, // 241 - { "afsr1_el1", 0xC289, true, true }, // 242 - { "afsr1_el2", 0xE289, true, true }, // 243 - { "afsr1_el3", 0xF289, true, true }, // 244 - { "esr_el1", 0xC290, true, true }, // 245 - { "esr_el2", 0xE290, true, true }, // 246 - { "esr_el3", 0xF290, true, true }, // 247 - { "fpexc32_el2", 0xE298, true, true }, // 248 - { "far_el1", 0xC300, true, true }, // 249 - { "far_el2", 0xE300, true, true }, // 250 - { "far_el3", 0xF300, true, true }, // 251 - { "hpfar_el2", 0xE304, true, true }, // 252 - { "par_el1", 0xC3A0, true, true }, // 253 - { "pmcr_el0", 0xDCE0, true, true }, // 254 - { "pmcntenset_el0", 0xDCE1, true, true }, // 255 - { "pmcntenclr_el0", 0xDCE2, true, true }, // 256 - { "pmovsclr_el0", 0xDCE3, true, true }, // 257 - { "pmselr_el0", 0xDCE5, true, true }, // 258 - { "pmccntr_el0", 0xDCE8, true, true }, // 259 - { "pmxevtyper_el0", 0xDCE9, true, true }, // 260 - { "pmxevcntr_el0", 0xDCEA, true, true }, // 261 - { "pmuserenr_el0", 0xDCF0, true, true }, // 262 - { "pmintenset_el1", 0xC4F1, true, true }, // 263 - { "pmintenclr_el1", 0xC4F2, true, true }, // 264 - { "pmovsset_el0", 0xDCF3, true, true }, // 265 - { "mair_el1", 0xC510, true, true }, // 266 - { "mair_el2", 0xE510, true, true }, // 267 - { "mair_el3", 0xF510, true, true }, // 268 - { "amair_el1", 0xC518, true, true }, // 269 - { "amair_el2", 0xE518, true, true }, // 270 - { "amair_el3", 0xF518, true, true }, // 271 - { "vbar_el1", 0xC600, true, true }, // 272 - { "vbar_el2", 0xE600, true, true }, // 273 - { "vbar_el3", 0xF600, true, true }, // 274 - { "rmr_el1", 0xC602, true, true }, // 275 - { "rmr_el2", 0xE602, true, true }, // 276 - { "rmr_el3", 0xF602, true, true }, // 277 - { "contextidr_el1", 0xC681, true, true }, // 278 - { "tpidr_el0", 0xDE82, true, true }, // 279 - { "tpidr_el2", 0xE682, true, true }, // 280 - { "tpidr_el3", 0xF682, true, true }, // 281 - { "tpidrro_el0", 0xDE83, true, true }, // 282 - { "tpidr_el1", 0xC684, true, true }, // 283 - { "cntfrq_el0", 0xDF00, true, true }, // 284 - { "cntvoff_el2", 0xE703, true, true }, // 285 - { "cntkctl_el1", 0xC708, true, true }, // 286 - { "cnthctl_el2", 0xE708, true, true }, // 287 - { "cntp_tval_el0", 0xDF10, true, true }, // 288 - { "cnthp_tval_el2", 0xE710, true, true }, // 289 - { "cntps_tval_el1", 0xFF10, true, true }, // 290 - { "cntp_ctl_el0", 0xDF11, true, true }, // 291 - { "cnthp_ctl_el2", 0xE711, true, true }, // 292 - { "cntps_ctl_el1", 0xFF11, true, true }, // 293 - { "cntp_cval_el0", 0xDF12, true, true }, // 294 - { "cnthp_cval_el2", 0xE712, true, true }, // 295 - { "cntps_cval_el1", 0xFF12, true, true }, // 296 - { "cntv_tval_el0", 0xDF18, true, true }, // 297 - { "cntv_ctl_el0", 0xDF19, true, true }, // 298 - { "cntv_cval_el0", 0xDF1A, true, true }, // 299 - { "pmevcntr0_el0", 0xDF40, true, true }, // 300 - { "pmevcntr1_el0", 0xDF41, true, true }, // 301 - { "pmevcntr2_el0", 0xDF42, true, true }, // 302 - { "pmevcntr3_el0", 0xDF43, true, true }, // 303 - { "pmevcntr4_el0", 0xDF44, true, true }, // 304 - { "pmevcntr5_el0", 0xDF45, true, true }, // 305 - { "pmevcntr6_el0", 0xDF46, true, true }, // 306 - { "pmevcntr7_el0", 0xDF47, true, true }, // 307 - { "pmevcntr8_el0", 0xDF48, true, true }, // 308 - { "pmevcntr9_el0", 0xDF49, true, true }, // 309 - { "pmevcntr10_el0", 0xDF4A, true, true }, // 310 - { "pmevcntr11_el0", 0xDF4B, true, true }, // 311 - { "pmevcntr12_el0", 0xDF4C, true, true }, // 312 - { "pmevcntr13_el0", 0xDF4D, true, true }, // 313 - { "pmevcntr14_el0", 0xDF4E, true, true }, // 314 - { "pmevcntr15_el0", 0xDF4F, true, true }, // 315 - { "pmevcntr16_el0", 0xDF50, true, true }, // 316 - { "pmevcntr17_el0", 0xDF51, true, true }, // 317 - { "pmevcntr18_el0", 0xDF52, true, true }, // 318 - { "pmevcntr19_el0", 0xDF53, true, true }, // 319 - { "pmevcntr20_el0", 0xDF54, true, true }, // 320 - { "pmevcntr21_el0", 0xDF55, true, true }, // 321 - { "pmevcntr22_el0", 0xDF56, true, true }, // 322 - { "pmevcntr23_el0", 0xDF57, true, true }, // 323 - { "pmevcntr24_el0", 0xDF58, true, true }, // 324 - { "pmevcntr25_el0", 0xDF59, true, true }, // 325 - { "pmevcntr26_el0", 0xDF5A, true, true }, // 326 - { "pmevcntr27_el0", 0xDF5B, true, true }, // 327 - { "pmevcntr28_el0", 0xDF5C, true, true }, // 328 - { "pmevcntr29_el0", 0xDF5D, true, true }, // 329 - { "pmevcntr30_el0", 0xDF5E, true, true }, // 330 - { "pmccfiltr_el0", 0xDF7F, true, true }, // 331 - { "pmevtyper0_el0", 0xDF60, true, true }, // 332 - { "pmevtyper1_el0", 0xDF61, true, true }, // 333 - { "pmevtyper2_el0", 0xDF62, true, true }, // 334 - { "pmevtyper3_el0", 0xDF63, true, true }, // 335 - { "pmevtyper4_el0", 0xDF64, true, true }, // 336 - { "pmevtyper5_el0", 0xDF65, true, true }, // 337 - { "pmevtyper6_el0", 0xDF66, true, true }, // 338 - { "pmevtyper7_el0", 0xDF67, true, true }, // 339 - { "pmevtyper8_el0", 0xDF68, true, true }, // 340 - { "pmevtyper9_el0", 0xDF69, true, true }, // 341 - { "pmevtyper10_el0", 0xDF6A, true, true }, // 342 - { "pmevtyper11_el0", 0xDF6B, true, true }, // 343 - { "pmevtyper12_el0", 0xDF6C, true, true }, // 344 - { "pmevtyper13_el0", 0xDF6D, true, true }, // 345 - { "pmevtyper14_el0", 0xDF6E, true, true }, // 346 - { "pmevtyper15_el0", 0xDF6F, true, true }, // 347 - { "pmevtyper16_el0", 0xDF70, true, true }, // 348 - { "pmevtyper17_el0", 0xDF71, true, true }, // 349 - { "pmevtyper18_el0", 0xDF72, true, true }, // 350 - { "pmevtyper19_el0", 0xDF73, true, true }, // 351 - { "pmevtyper20_el0", 0xDF74, true, true }, // 352 - { "pmevtyper21_el0", 0xDF75, true, true }, // 353 - { "pmevtyper22_el0", 0xDF76, true, true }, // 354 - { "pmevtyper23_el0", 0xDF77, true, true }, // 355 - { "pmevtyper24_el0", 0xDF78, true, true }, // 356 - { "pmevtyper25_el0", 0xDF79, true, true }, // 357 - { "pmevtyper26_el0", 0xDF7A, true, true }, // 358 - { "pmevtyper27_el0", 0xDF7B, true, true }, // 359 - { "pmevtyper28_el0", 0xDF7C, true, true }, // 360 - { "pmevtyper29_el0", 0xDF7D, true, true }, // 361 - { "pmevtyper30_el0", 0xDF7E, true, true }, // 362 - { "trcprgctlr", 0x8808, true, true }, // 363 - { "trcprocselr", 0x8810, true, true }, // 364 - { "trcconfigr", 0x8820, true, true }, // 365 - { "trcauxctlr", 0x8830, true, true }, // 366 - { "trceventctl0r", 0x8840, true, true }, // 367 - { "trceventctl1r", 0x8848, true, true }, // 368 - { "trcstallctlr", 0x8858, true, true }, // 369 - { "trctsctlr", 0x8860, true, true }, // 370 - { "trcsyncpr", 0x8868, true, true }, // 371 - { "trcccctlr", 0x8870, true, true }, // 372 - { "trcbbctlr", 0x8878, true, true }, // 373 - { "trctraceidr", 0x8801, true, true }, // 374 - { "trcqctlr", 0x8809, true, true }, // 375 - { "trcvictlr", 0x8802, true, true }, // 376 - { "trcviiectlr", 0x880A, true, true }, // 377 - { "trcvissctlr", 0x8812, true, true }, // 378 - { "trcvipcssctlr", 0x881A, true, true }, // 379 - { "trcvdctlr", 0x8842, true, true }, // 380 - { "trcvdsacctlr", 0x884A, true, true }, // 381 - { "trcvdarcctlr", 0x8852, true, true }, // 382 - { "trcseqevr0", 0x8804, true, true }, // 383 - { "trcseqevr1", 0x880C, true, true }, // 384 - { "trcseqevr2", 0x8814, true, true }, // 385 - { "trcseqrstevr", 0x8834, true, true }, // 386 - { "trcseqstr", 0x883C, true, true }, // 387 - { "trcextinselr", 0x8844, true, true }, // 388 - { "trccntrldvr0", 0x8805, true, true }, // 389 - { "trccntrldvr1", 0x880D, true, true }, // 390 - { "trccntrldvr2", 0x8815, true, true }, // 391 - { "trccntrldvr3", 0x881D, true, true }, // 392 - { "trccntctlr0", 0x8825, true, true }, // 393 - { "trccntctlr1", 0x882D, true, true }, // 394 - { "trccntctlr2", 0x8835, true, true }, // 395 - { "trccntctlr3", 0x883D, true, true }, // 396 - { "trccntvr0", 0x8845, true, true }, // 397 - { "trccntvr1", 0x884D, true, true }, // 398 - { "trccntvr2", 0x8855, true, true }, // 399 - { "trccntvr3", 0x885D, true, true }, // 400 - { "trcimspec0", 0x8807, true, true }, // 401 - { "trcimspec1", 0x880F, true, true }, // 402 - { "trcimspec2", 0x8817, true, true }, // 403 - { "trcimspec3", 0x881F, true, true }, // 404 - { "trcimspec4", 0x8827, true, true }, // 405 - { "trcimspec5", 0x882F, true, true }, // 406 - { "trcimspec6", 0x8837, true, true }, // 407 - { "trcimspec7", 0x883F, true, true }, // 408 - { "trcrsctlr2", 0x8890, true, true }, // 409 - { "trcrsctlr3", 0x8898, true, true }, // 410 - { "trcrsctlr4", 0x88A0, true, true }, // 411 - { "trcrsctlr5", 0x88A8, true, true }, // 412 - { "trcrsctlr6", 0x88B0, true, true }, // 413 - { "trcrsctlr7", 0x88B8, true, true }, // 414 - { "trcrsctlr8", 0x88C0, true, true }, // 415 - { "trcrsctlr9", 0x88C8, true, true }, // 416 - { "trcrsctlr10", 0x88D0, true, true }, // 417 - { "trcrsctlr11", 0x88D8, true, true }, // 418 - { "trcrsctlr12", 0x88E0, true, true }, // 419 - { "trcrsctlr13", 0x88E8, true, true }, // 420 - { "trcrsctlr14", 0x88F0, true, true }, // 421 - { "trcrsctlr15", 0x88F8, true, true }, // 422 - { "trcrsctlr16", 0x8881, true, true }, // 423 - { "trcrsctlr17", 0x8889, true, true }, // 424 - { "trcrsctlr18", 0x8891, true, true }, // 425 - { "trcrsctlr19", 0x8899, true, true }, // 426 - { "trcrsctlr20", 0x88A1, true, true }, // 427 - { "trcrsctlr21", 0x88A9, true, true }, // 428 - { "trcrsctlr22", 0x88B1, true, true }, // 429 - { "trcrsctlr23", 0x88B9, true, true }, // 430 - { "trcrsctlr24", 0x88C1, true, true }, // 431 - { "trcrsctlr25", 0x88C9, true, true }, // 432 - { "trcrsctlr26", 0x88D1, true, true }, // 433 - { "trcrsctlr27", 0x88D9, true, true }, // 434 - { "trcrsctlr28", 0x88E1, true, true }, // 435 - { "trcrsctlr29", 0x88E9, true, true }, // 436 - { "trcrsctlr30", 0x88F1, true, true }, // 437 - { "trcrsctlr31", 0x88F9, true, true }, // 438 - { "trcssccr0", 0x8882, true, true }, // 439 - { "trcssccr1", 0x888A, true, true }, // 440 - { "trcssccr2", 0x8892, true, true }, // 441 - { "trcssccr3", 0x889A, true, true }, // 442 - { "trcssccr4", 0x88A2, true, true }, // 443 - { "trcssccr5", 0x88AA, true, true }, // 444 - { "trcssccr6", 0x88B2, true, true }, // 445 - { "trcssccr7", 0x88BA, true, true }, // 446 - { "trcsscsr0", 0x88C2, true, true }, // 447 - { "trcsscsr1", 0x88CA, true, true }, // 448 - { "trcsscsr2", 0x88D2, true, true }, // 449 - { "trcsscsr3", 0x88DA, true, true }, // 450 - { "trcsscsr4", 0x88E2, true, true }, // 451 - { "trcsscsr5", 0x88EA, true, true }, // 452 - { "trcsscsr6", 0x88F2, true, true }, // 453 - { "trcsscsr7", 0x88FA, true, true }, // 454 - { "trcsspcicr0", 0x8883, true, true }, // 455 - { "trcsspcicr1", 0x888B, true, true }, // 456 - { "trcsspcicr2", 0x8893, true, true }, // 457 - { "trcsspcicr3", 0x889B, true, true }, // 458 - { "trcsspcicr4", 0x88A3, true, true }, // 459 - { "trcsspcicr5", 0x88AB, true, true }, // 460 - { "trcsspcicr6", 0x88B3, true, true }, // 461 - { "trcsspcicr7", 0x88BB, true, true }, // 462 - { "trcpdcr", 0x88A4, true, true }, // 463 - { "trcacvr0", 0x8900, true, true }, // 464 - { "trcacvr1", 0x8910, true, true }, // 465 - { "trcacvr2", 0x8920, true, true }, // 466 - { "trcacvr3", 0x8930, true, true }, // 467 - { "trcacvr4", 0x8940, true, true }, // 468 - { "trcacvr5", 0x8950, true, true }, // 469 - { "trcacvr6", 0x8960, true, true }, // 470 - { "trcacvr7", 0x8970, true, true }, // 471 - { "trcacvr8", 0x8901, true, true }, // 472 - { "trcacvr9", 0x8911, true, true }, // 473 - { "trcacvr10", 0x8921, true, true }, // 474 - { "trcacvr11", 0x8931, true, true }, // 475 - { "trcacvr12", 0x8941, true, true }, // 476 - { "trcacvr13", 0x8951, true, true }, // 477 - { "trcacvr14", 0x8961, true, true }, // 478 - { "trcacvr15", 0x8971, true, true }, // 479 - { "trcacatr0", 0x8902, true, true }, // 480 - { "trcacatr1", 0x8912, true, true }, // 481 - { "trcacatr2", 0x8922, true, true }, // 482 - { "trcacatr3", 0x8932, true, true }, // 483 - { "trcacatr4", 0x8942, true, true }, // 484 - { "trcacatr5", 0x8952, true, true }, // 485 - { "trcacatr6", 0x8962, true, true }, // 486 - { "trcacatr7", 0x8972, true, true }, // 487 - { "trcacatr8", 0x8903, true, true }, // 488 - { "trcacatr9", 0x8913, true, true }, // 489 - { "trcacatr10", 0x8923, true, true }, // 490 - { "trcacatr11", 0x8933, true, true }, // 491 - { "trcacatr12", 0x8943, true, true }, // 492 - { "trcacatr13", 0x8953, true, true }, // 493 - { "trcacatr14", 0x8963, true, true }, // 494 - { "trcacatr15", 0x8973, true, true }, // 495 - { "trcdvcvr0", 0x8904, true, true }, // 496 - { "trcdvcvr1", 0x8924, true, true }, // 497 - { "trcdvcvr2", 0x8944, true, true }, // 498 - { "trcdvcvr3", 0x8964, true, true }, // 499 - { "trcdvcvr4", 0x8905, true, true }, // 500 - { "trcdvcvr5", 0x8925, true, true }, // 501 - { "trcdvcvr6", 0x8945, true, true }, // 502 - { "trcdvcvr7", 0x8965, true, true }, // 503 - { "trcdvcmr0", 0x8906, true, true }, // 504 - { "trcdvcmr1", 0x8926, true, true }, // 505 - { "trcdvcmr2", 0x8946, true, true }, // 506 - { "trcdvcmr3", 0x8966, true, true }, // 507 - { "trcdvcmr4", 0x8907, true, true }, // 508 - { "trcdvcmr5", 0x8927, true, true }, // 509 - { "trcdvcmr6", 0x8947, true, true }, // 510 - { "trcdvcmr7", 0x8967, true, true }, // 511 - { "trccidcvr0", 0x8980, true, true }, // 512 - { "trccidcvr1", 0x8990, true, true }, // 513 - { "trccidcvr2", 0x89A0, true, true }, // 514 - { "trccidcvr3", 0x89B0, true, true }, // 515 - { "trccidcvr4", 0x89C0, true, true }, // 516 - { "trccidcvr5", 0x89D0, true, true }, // 517 - { "trccidcvr6", 0x89E0, true, true }, // 518 - { "trccidcvr7", 0x89F0, true, true }, // 519 - { "trcvmidcvr0", 0x8981, true, true }, // 520 - { "trcvmidcvr1", 0x8991, true, true }, // 521 - { "trcvmidcvr2", 0x89A1, true, true }, // 522 - { "trcvmidcvr3", 0x89B1, true, true }, // 523 - { "trcvmidcvr4", 0x89C1, true, true }, // 524 - { "trcvmidcvr5", 0x89D1, true, true }, // 525 - { "trcvmidcvr6", 0x89E1, true, true }, // 526 - { "trcvmidcvr7", 0x89F1, true, true }, // 527 - { "trccidcctlr0", 0x8982, true, true }, // 528 - { "trccidcctlr1", 0x898A, true, true }, // 529 - { "trcvmidcctlr0", 0x8992, true, true }, // 530 - { "trcvmidcctlr1", 0x899A, true, true }, // 531 - { "trcitctrl", 0x8B84, true, true }, // 532 - { "trcclaimset", 0x8BC6, true, true }, // 533 - { "trcclaimclr", 0x8BCE, true, true }, // 534 - { "icc_bpr1_el1", 0xC663, true, true }, // 535 - { "icc_bpr0_el1", 0xC643, true, true }, // 536 - { "icc_pmr_el1", 0xC230, true, true }, // 537 - { "icc_ctlr_el1", 0xC664, true, true }, // 538 - { "icc_ctlr_el3", 0xF664, true, true }, // 539 - { "icc_sre_el1", 0xC665, true, true }, // 540 - { "icc_sre_el2", 0xE64D, true, true }, // 541 - { "icc_sre_el3", 0xF665, true, true }, // 542 - { "icc_igrpen0_el1", 0xC666, true, true }, // 543 - { "icc_igrpen1_el1", 0xC667, true, true }, // 544 - { "icc_igrpen1_el3", 0xF667, true, true }, // 545 - { "icc_seien_el1", 0xC668, true, true }, // 546 - { "icc_ap0r0_el1", 0xC644, true, true }, // 547 - { "icc_ap0r1_el1", 0xC645, true, true }, // 548 - { "icc_ap0r2_el1", 0xC646, true, true }, // 549 - { "icc_ap0r3_el1", 0xC647, true, true }, // 550 - { "icc_ap1r0_el1", 0xC648, true, true }, // 551 - { "icc_ap1r1_el1", 0xC649, true, true }, // 552 - { "icc_ap1r2_el1", 0xC64A, true, true }, // 553 - { "icc_ap1r3_el1", 0xC64B, true, true }, // 554 - { "ich_ap0r0_el2", 0xE640, true, true }, // 555 - { "ich_ap0r1_el2", 0xE641, true, true }, // 556 - { "ich_ap0r2_el2", 0xE642, true, true }, // 557 - { "ich_ap0r3_el2", 0xE643, true, true }, // 558 - { "ich_ap1r0_el2", 0xE648, true, true }, // 559 - { "ich_ap1r1_el2", 0xE649, true, true }, // 560 - { "ich_ap1r2_el2", 0xE64A, true, true }, // 561 - { "ich_ap1r3_el2", 0xE64B, true, true }, // 562 - { "ich_hcr_el2", 0xE658, true, true }, // 563 - { "ich_misr_el2", 0xE65A, true, true }, // 564 - { "ich_vmcr_el2", 0xE65F, true, true }, // 565 - { "ich_vseir_el2", 0xE64C, true, true }, // 566 - { "ich_lr0_el2", 0xE660, true, true }, // 567 - { "ich_lr1_el2", 0xE661, true, true }, // 568 - { "ich_lr2_el2", 0xE662, true, true }, // 569 - { "ich_lr3_el2", 0xE663, true, true }, // 570 - { "ich_lr4_el2", 0xE664, true, true }, // 571 - { "ich_lr5_el2", 0xE665, true, true }, // 572 - { "ich_lr6_el2", 0xE666, true, true }, // 573 - { "ich_lr7_el2", 0xE667, true, true }, // 574 - { "ich_lr8_el2", 0xE668, true, true }, // 575 - { "ich_lr9_el2", 0xE669, true, true }, // 576 - { "ich_lr10_el2", 0xE66A, true, true }, // 577 - { "ich_lr11_el2", 0xE66B, true, true }, // 578 - { "ich_lr12_el2", 0xE66C, true, true }, // 579 - { "ich_lr13_el2", 0xE66D, true, true }, // 580 - { "ich_lr14_el2", 0xE66E, true, true }, // 581 - { "ich_lr15_el2", 0xE66F, true, true }, // 582 - { "pan", 0xC213, true, true }, // 583 - { "lorsa_el1", 0xC520, true, true }, // 584 - { "lorea_el1", 0xC521, true, true }, // 585 - { "lorn_el1", 0xC522, true, true }, // 586 - { "lorc_el1", 0xC523, true, true }, // 587 - { "ttbr1_el2", 0xE101, true, true }, // 588 - { "contextidr_el2", 0xE681, true, true }, // 589 - { "cnthv_tval_el2", 0xE718, true, true }, // 590 - { "cnthv_cval_el2", 0xE71A, true, true }, // 591 - { "cnthv_ctl_el2", 0xE719, true, true }, // 592 - { "sctlr_el12", 0xE880, true, true }, // 593 - { "cpacr_el12", 0xE882, true, true }, // 594 - { "ttbr0_el12", 0xE900, true, true }, // 595 - { "ttbr1_el12", 0xE901, true, true }, // 596 - { "tcr_el12", 0xE902, true, true }, // 597 - { "afsr0_el12", 0xEA88, true, true }, // 598 - { "afsr1_el12", 0xEA89, true, true }, // 599 - { "esr_el12", 0xEA90, true, true }, // 600 - { "far_el12", 0xEB00, true, true }, // 601 - { "mair_el12", 0xED10, true, true }, // 602 - { "amair_el12", 0xED18, true, true }, // 603 - { "vbar_el12", 0xEE00, true, true }, // 604 - { "contextidr_el12", 0xEE81, true, true }, // 605 - { "cntkctl_el12", 0xEF08, true, true }, // 606 - { "cntp_tval_el02", 0xEF10, true, true }, // 607 - { "cntp_ctl_el02", 0xEF11, true, true }, // 608 - { "cntp_cval_el02", 0xEF12, true, true }, // 609 - { "cntv_tval_el02", 0xEF18, true, true }, // 610 - { "cntv_ctl_el02", 0xEF19, true, true }, // 611 - { "cntv_cval_el02", 0xEF1A, true, true }, // 612 - { "spsr_el12", 0xEA00, true, true }, // 613 - { "elr_el12", 0xEA01, true, true }, // 614 - { "uao", 0xC214, true, true }, // 615 - { "pmblimitr_el1", 0xC4D0, true, true }, // 616 - { "pmbptr_el1", 0xC4D1, true, true }, // 617 - { "pmbsr_el1", 0xC4D3, true, true }, // 618 - { "pmbidr_el1", 0xC4D7, true, true }, // 619 - { "pmscr_el2", 0xE4C8, true, true }, // 620 - { "pmscr_el12", 0xECC8, true, true }, // 621 - { "pmscr_el1", 0xC4C8, true, true }, // 622 - { "pmsicr_el1", 0xC4CA, true, true }, // 623 - { "pmsirr_el1", 0xC4CB, true, true }, // 624 - { "pmsfcr_el1", 0xC4CC, true, true }, // 625 - { "pmsevfr_el1", 0xC4CD, true, true }, // 626 - { "pmslatfr_el1", 0xC4CE, true, true }, // 627 - { "pmsidr_el1", 0xC4CF, true, true }, // 628 - { "errselr_el1", 0xC299, true, true }, // 629 - { "erxctlr_el1", 0xC2A1, true, true }, // 630 - { "erxstatus_el1", 0xC2A2, true, true }, // 631 - { "erxaddr_el1", 0xC2A3, true, true }, // 632 - { "erxmisc0_el1", 0xC2A8, true, true }, // 633 - { "erxmisc1_el1", 0xC2A9, true, true }, // 634 - { "disr_el1", 0xC609, true, true }, // 635 - { "vdisr_el2", 0xE609, true, true }, // 636 - { "vsesr_el2", 0xE293, true, true }, // 637 - { "apiakeylo_el1", 0xC108, true, true }, // 638 - { "apiakeyhi_el1", 0xC109, true, true }, // 639 - { "apibkeylo_el1", 0xC10A, true, true }, // 640 - { "apibkeyhi_el1", 0xC10B, true, true }, // 641 - { "apdakeylo_el1", 0xC110, true, true }, // 642 - { "apdakeyhi_el1", 0xC111, true, true }, // 643 - { "apdbkeylo_el1", 0xC112, true, true }, // 644 - { "apdbkeyhi_el1", 0xC113, true, true }, // 645 - { "apgakeylo_el1", 0xC118, true, true }, // 646 - { "apgakeyhi_el1", 0xC119, true, true }, // 647 - { "vstcr_el2", 0xE132, true, true }, // 648 - { "vsttbr_el2", 0xE130, true, true }, // 649 - { "cnthvs_tval_el2", 0xE720, true, true }, // 650 - { "cnthvs_cval_el2", 0xE722, true, true }, // 651 - { "cnthvs_ctl_el2", 0xE721, true, true }, // 652 - { "cnthps_tval_el2", 0xE728, true, true }, // 653 - { "cnthps_cval_el2", 0xE72A, true, true }, // 654 - { "cnthps_ctl_el2", 0xE729, true, true }, // 655 - { "sder32_el2", 0xE099, true, true }, // 656 - { "erxpfgctl_el1", 0xC2A5, true, true }, // 657 - { "erxpfgcdn_el1", 0xC2A6, true, true }, // 658 - { "erxts_el1", 0xC2AF, true, true }, // 659 - { "erxmisc2_el1", 0xC2AA, true, true }, // 660 - { "erxmisc3_el1", 0xC2AB, true, true }, // 661 - { "erxpfgf_el1", 0xC2A4, true, false }, // 662 - { "mpam0_el1", 0xC529, true, true }, // 663 - { "mpam1_el1", 0xC528, true, true }, // 664 - { "mpam2_el2", 0xE528, true, true }, // 665 - { "mpam3_el3", 0xF528, true, true }, // 666 - { "mpam1_el12", 0xED28, true, true }, // 667 - { "mpamhcr_el2", 0xE520, true, true }, // 668 - { "mpamvpmv_el2", 0xE521, true, true }, // 669 - { "mpamvpm0_el2", 0xE530, true, true }, // 670 - { "mpamvpm1_el2", 0xE531, true, true }, // 671 - { "mpamvpm2_el2", 0xE532, true, true }, // 672 - { "mpamvpm3_el2", 0xE533, true, true }, // 673 - { "mpamvpm4_el2", 0xE534, true, true }, // 674 - { "mpamvpm5_el2", 0xE535, true, true }, // 675 - { "mpamvpm6_el2", 0xE536, true, true }, // 676 - { "mpamvpm7_el2", 0xE537, true, true }, // 677 - { "mpamidr_el1", 0xC524, true, false }, // 678 - { "amcr_el0", 0xDE90, true, true }, // 679 - { "amcfgr_el0", 0xDE91, true, false }, // 680 - { "amcgcr_el0", 0xDE92, true, false }, // 681 - { "amuserenr_el0", 0xDE93, true, true }, // 682 - { "amcntenclr0_el0", 0xDE94, true, true }, // 683 - { "amcntenset0_el0", 0xDE95, true, true }, // 684 - { "amevcntr00_el0", 0xDEA0, true, true }, // 685 - { "amevcntr01_el0", 0xDEA1, true, true }, // 686 - { "amevcntr02_el0", 0xDEA2, true, true }, // 687 - { "amevcntr03_el0", 0xDEA3, true, true }, // 688 - { "amevtyper00_el0", 0xDEB0, true, false }, // 689 - { "amevtyper01_el0", 0xDEB1, true, false }, // 690 - { "amevtyper02_el0", 0xDEB2, true, false }, // 691 - { "amevtyper03_el0", 0xDEB3, true, false }, // 692 - { "amcntenclr1_el0", 0xDE98, true, true }, // 693 - { "amcntenset1_el0", 0xDE99, true, true }, // 694 - { "amevcntr10_el0", 0xDEE0, true, true }, // 695 - { "amevcntr11_el0", 0xDEE1, true, true }, // 696 - { "amevcntr12_el0", 0xDEE2, true, true }, // 697 - { "amevcntr13_el0", 0xDEE3, true, true }, // 698 - { "amevcntr14_el0", 0xDEE4, true, true }, // 699 - { "amevcntr15_el0", 0xDEE5, true, true }, // 700 - { "amevcntr16_el0", 0xDEE6, true, true }, // 701 - { "amevcntr17_el0", 0xDEE7, true, true }, // 702 - { "amevcntr18_el0", 0xDEE8, true, true }, // 703 - { "amevcntr19_el0", 0xDEE9, true, true }, // 704 - { "amevcntr110_el0", 0xDEEA, true, true }, // 705 - { "amevcntr111_el0", 0xDEEB, true, true }, // 706 - { "amevcntr112_el0", 0xDEEC, true, true }, // 707 - { "amevcntr113_el0", 0xDEED, true, true }, // 708 - { "amevcntr114_el0", 0xDEEE, true, true }, // 709 - { "amevcntr115_el0", 0xDEEF, true, true }, // 710 - { "amevtyper10_el0", 0xDEF0, true, true }, // 711 - { "amevtyper11_el0", 0xDEF1, true, true }, // 712 - { "amevtyper12_el0", 0xDEF2, true, true }, // 713 - { "amevtyper13_el0", 0xDEF3, true, true }, // 714 - { "amevtyper14_el0", 0xDEF4, true, true }, // 715 - { "amevtyper15_el0", 0xDEF5, true, true }, // 716 - { "amevtyper16_el0", 0xDEF6, true, true }, // 717 - { "amevtyper17_el0", 0xDEF7, true, true }, // 718 - { "amevtyper18_el0", 0xDEF8, true, true }, // 719 - { "amevtyper19_el0", 0xDEF9, true, true }, // 720 - { "amevtyper110_el0", 0xDEFA, true, true }, // 721 - { "amevtyper111_el0", 0xDEFB, true, true }, // 722 - { "amevtyper112_el0", 0xDEFC, true, true }, // 723 - { "amevtyper113_el0", 0xDEFD, true, true }, // 724 - { "amevtyper114_el0", 0xDEFE, true, true }, // 725 - { "amevtyper115_el0", 0xDEFF, true, true }, // 726 - { "trfcr_el1", 0xC091, true, true }, // 727 - { "trfcr_el2", 0xE091, true, true }, // 728 - { "trfcr_el12", 0xE891, true, true }, // 729 - { "dit", 0xDA15, true, true }, // 730 - { "vncr_el2", 0xE110, true, true }, // 731 - { "zcr_el1", 0xC090, true, true }, // 732 - { "zcr_el2", 0xE090, true, true }, // 733 - { "zcr_el3", 0xF090, true, true }, // 734 - { "zcr_el12", 0xE890, true, true }, // 735 - { "cpm_ioacc_ctl_el3", 0xFF90, true, true }, // 736 + {"mdccsr_el0", 0x9808, true, false}, // 0 + {"dbgdtrrx_el0", 0x9828, true, false}, // 1 + {"mdrar_el1", 0x8080, true, false}, // 2 + {"oslsr_el1", 0x808C, true, false}, // 3 + {"dbgauthstatus_el1", 0x83F6, true, false}, // 4 + {"pmceid0_el0", 0xDCE6, true, false}, // 5 + {"pmceid1_el0", 0xDCE7, true, false}, // 6 + {"midr_el1", 0xC000, true, false}, // 7 + {"ccsidr_el1", 0xC800, true, false}, // 8 + {"ccsidr2_el1", 0xC802, true, false}, // 9 + {"clidr_el1", 0xC801, true, false}, // 10 + {"ctr_el0", 0xD801, true, false}, // 11 + {"mpidr_el1", 0xC005, true, false}, // 12 + {"revidr_el1", 0xC006, true, false}, // 13 + {"aidr_el1", 0xC807, true, false}, // 14 + {"dczid_el0", 0xD807, true, false}, // 15 + {"id_pfr0_el1", 0xC008, true, false}, // 16 + {"id_pfr1_el1", 0xC009, true, false}, // 17 + {"id_dfr0_el1", 0xC00A, true, false}, // 18 + {"id_afr0_el1", 0xC00B, true, false}, // 19 + {"id_mmfr0_el1", 0xC00C, true, false}, // 20 + {"id_mmfr1_el1", 0xC00D, true, false}, // 21 + {"id_mmfr2_el1", 0xC00E, true, false}, // 22 + {"id_mmfr3_el1", 0xC00F, true, false}, // 23 + {"id_isar0_el1", 0xC010, true, false}, // 24 + {"id_isar1_el1", 0xC011, true, false}, // 25 + {"id_isar2_el1", 0xC012, true, false}, // 26 + {"id_isar3_el1", 0xC013, true, false}, // 27 + {"id_isar4_el1", 0xC014, true, false}, // 28 + {"id_isar5_el1", 0xC015, true, false}, // 29 + {"id_isar6_el1", 0xC017, true, false}, // 30 + {"id_aa64pfr0_el1", 0xC020, true, false}, // 31 + {"id_aa64pfr1_el1", 0xC021, true, false}, // 32 + {"id_aa64dfr0_el1", 0xC028, true, false}, // 33 + {"id_aa64dfr1_el1", 0xC029, true, false}, // 34 + {"id_aa64afr0_el1", 0xC02C, true, false}, // 35 + {"id_aa64afr1_el1", 0xC02D, true, false}, // 36 + {"id_aa64isar0_el1", 0xC030, true, false}, // 37 + {"id_aa64isar1_el1", 0xC031, true, false}, // 38 + {"id_aa64mmfr0_el1", 0xC038, true, false}, // 39 + {"id_aa64mmfr1_el1", 0xC039, true, false}, // 40 + {"id_aa64mmfr2_el1", 0xC03A, true, false}, // 41 + {"mvfr0_el1", 0xC018, true, false}, // 42 + {"mvfr1_el1", 0xC019, true, false}, // 43 + {"mvfr2_el1", 0xC01A, true, false}, // 44 + {"rvbar_el1", 0xC601, true, false}, // 45 + {"rvbar_el2", 0xE601, true, false}, // 46 + {"rvbar_el3", 0xF601, true, false}, // 47 + {"isr_el1", 0xC608, true, false}, // 48 + {"cntpct_el0", 0xDF01, true, false}, // 49 + {"cntvct_el0", 0xDF02, true, false}, // 50 + {"id_mmfr4_el1", 0xC016, true, false}, // 51 + {"trcstatr", 0x8818, true, false}, // 52 + {"trcidr8", 0x8806, true, false}, // 53 + {"trcidr9", 0x880E, true, false}, // 54 + {"trcidr10", 0x8816, true, false}, // 55 + {"trcidr11", 0x881E, true, false}, // 56 + {"trcidr12", 0x8826, true, false}, // 57 + {"trcidr13", 0x882E, true, false}, // 58 + {"trcidr0", 0x8847, true, false}, // 59 + {"trcidr1", 0x884F, true, false}, // 60 + {"trcidr2", 0x8857, true, false}, // 61 + {"trcidr3", 0x885F, true, false}, // 62 + {"trcidr4", 0x8867, true, false}, // 63 + {"trcidr5", 0x886F, true, false}, // 64 + {"trcidr6", 0x8877, true, false}, // 65 + {"trcidr7", 0x887F, true, false}, // 66 + {"trcoslsr", 0x888C, true, false}, // 67 + {"trcpdsr", 0x88AC, true, false}, // 68 + {"trcdevaff0", 0x8BD6, true, false}, // 69 + {"trcdevaff1", 0x8BDE, true, false}, // 70 + {"trclsr", 0x8BEE, true, false}, // 71 + {"trcauthstatus", 0x8BF6, true, false}, // 72 + {"trcdevarch", 0x8BFE, true, false}, // 73 + {"trcdevid", 0x8B97, true, false}, // 74 + {"trcdevtype", 0x8B9F, true, false}, // 75 + {"trcpidr4", 0x8BA7, true, false}, // 76 + {"trcpidr5", 0x8BAF, true, false}, // 77 + {"trcpidr6", 0x8BB7, true, false}, // 78 + {"trcpidr7", 0x8BBF, true, false}, // 79 + {"trcpidr0", 0x8BC7, true, false}, // 80 + {"trcpidr1", 0x8BCF, true, false}, // 81 + {"trcpidr2", 0x8BD7, true, false}, // 82 + {"trcpidr3", 0x8BDF, true, false}, // 83 + {"trccidr0", 0x8BE7, true, false}, // 84 + {"trccidr1", 0x8BEF, true, false}, // 85 + {"trccidr2", 0x8BF7, true, false}, // 86 + {"trccidr3", 0x8BFF, true, false}, // 87 + {"icc_iar1_el1", 0xC660, true, false}, // 88 + {"icc_iar0_el1", 0xC640, true, false}, // 89 + {"icc_hppir1_el1", 0xC662, true, false}, // 90 + {"icc_hppir0_el1", 0xC642, true, false}, // 91 + {"icc_rpr_el1", 0xC65B, true, false}, // 92 + {"ich_vtr_el2", 0xE659, true, false}, // 93 + {"ich_eisr_el2", 0xE65B, true, false}, // 94 + {"ich_elrsr_el2", 0xE65D, true, false}, // 95 + {"id_aa64zfr0_el1", 0xC024, true, false}, // 96 + {"lorid_el1", 0xC527, true, false}, // 97 + {"erridr_el1", 0xC298, true, false}, // 98 + {"erxfr_el1", 0xC2A0, true, false}, // 99 + {"dbgdtrtx_el0", 0x9828, false, true}, // 100 + {"oslar_el1", 0x8084, false, true}, // 101 + {"pmswinc_el0", 0xDCE4, false, true}, // 102 + {"trcoslar", 0x8884, false, true}, // 103 + {"trclar", 0x8BE6, false, true}, // 104 + {"icc_eoir1_el1", 0xC661, false, true}, // 105 + {"icc_eoir0_el1", 0xC641, false, true}, // 106 + {"icc_dir_el1", 0xC659, false, true}, // 107 + {"icc_sgi1r_el1", 0xC65D, false, true}, // 108 + {"icc_asgi1r_el1", 0xC65E, false, true}, // 109 + {"icc_sgi0r_el1", 0xC65F, false, true}, // 110 + {"osdtrrx_el1", 0x8002, true, true}, // 111 + {"osdtrtx_el1", 0x801A, true, true}, // 112 + {"teecr32_el1", 0x9000, true, true}, // 113 + {"mdccint_el1", 0x8010, true, true}, // 114 + {"mdscr_el1", 0x8012, true, true}, // 115 + {"dbgdtr_el0", 0x9820, true, true}, // 116 + {"oseccr_el1", 0x8032, true, true}, // 117 + {"dbgvcr32_el2", 0xA038, true, true}, // 118 + {"dbgbvr0_el1", 0x8004, true, true}, // 119 + {"dbgbvr1_el1", 0x800C, true, true}, // 120 + {"dbgbvr2_el1", 0x8014, true, true}, // 121 + {"dbgbvr3_el1", 0x801C, true, true}, // 122 + {"dbgbvr4_el1", 0x8024, true, true}, // 123 + {"dbgbvr5_el1", 0x802C, true, true}, // 124 + {"dbgbvr6_el1", 0x8034, true, true}, // 125 + {"dbgbvr7_el1", 0x803C, true, true}, // 126 + {"dbgbvr8_el1", 0x8044, true, true}, // 127 + {"dbgbvr9_el1", 0x804C, true, true}, // 128 + {"dbgbvr10_el1", 0x8054, true, true}, // 129 + {"dbgbvr11_el1", 0x805C, true, true}, // 130 + {"dbgbvr12_el1", 0x8064, true, true}, // 131 + {"dbgbvr13_el1", 0x806C, true, true}, // 132 + {"dbgbvr14_el1", 0x8074, true, true}, // 133 + {"dbgbvr15_el1", 0x807C, true, true}, // 134 + {"dbgbcr0_el1", 0x8005, true, true}, // 135 + {"dbgbcr1_el1", 0x800D, true, true}, // 136 + {"dbgbcr2_el1", 0x8015, true, true}, // 137 + {"dbgbcr3_el1", 0x801D, true, true}, // 138 + {"dbgbcr4_el1", 0x8025, true, true}, // 139 + {"dbgbcr5_el1", 0x802D, true, true}, // 140 + {"dbgbcr6_el1", 0x8035, true, true}, // 141 + {"dbgbcr7_el1", 0x803D, true, true}, // 142 + {"dbgbcr8_el1", 0x8045, true, true}, // 143 + {"dbgbcr9_el1", 0x804D, true, true}, // 144 + {"dbgbcr10_el1", 0x8055, true, true}, // 145 + {"dbgbcr11_el1", 0x805D, true, true}, // 146 + {"dbgbcr12_el1", 0x8065, true, true}, // 147 + {"dbgbcr13_el1", 0x806D, true, true}, // 148 + {"dbgbcr14_el1", 0x8075, true, true}, // 149 + {"dbgbcr15_el1", 0x807D, true, true}, // 150 + {"dbgwvr0_el1", 0x8006, true, true}, // 151 + {"dbgwvr1_el1", 0x800E, true, true}, // 152 + {"dbgwvr2_el1", 0x8016, true, true}, // 153 + {"dbgwvr3_el1", 0x801E, true, true}, // 154 + {"dbgwvr4_el1", 0x8026, true, true}, // 155 + {"dbgwvr5_el1", 0x802E, true, true}, // 156 + {"dbgwvr6_el1", 0x8036, true, true}, // 157 + {"dbgwvr7_el1", 0x803E, true, true}, // 158 + {"dbgwvr8_el1", 0x8046, true, true}, // 159 + {"dbgwvr9_el1", 0x804E, true, true}, // 160 + {"dbgwvr10_el1", 0x8056, true, true}, // 161 + {"dbgwvr11_el1", 0x805E, true, true}, // 162 + {"dbgwvr12_el1", 0x8066, true, true}, // 163 + {"dbgwvr13_el1", 0x806E, true, true}, // 164 + {"dbgwvr14_el1", 0x8076, true, true}, // 165 + {"dbgwvr15_el1", 0x807E, true, true}, // 166 + {"dbgwcr0_el1", 0x8007, true, true}, // 167 + {"dbgwcr1_el1", 0x800F, true, true}, // 168 + {"dbgwcr2_el1", 0x8017, true, true}, // 169 + {"dbgwcr3_el1", 0x801F, true, true}, // 170 + {"dbgwcr4_el1", 0x8027, true, true}, // 171 + {"dbgwcr5_el1", 0x802F, true, true}, // 172 + {"dbgwcr6_el1", 0x8037, true, true}, // 173 + {"dbgwcr7_el1", 0x803F, true, true}, // 174 + {"dbgwcr8_el1", 0x8047, true, true}, // 175 + {"dbgwcr9_el1", 0x804F, true, true}, // 176 + {"dbgwcr10_el1", 0x8057, true, true}, // 177 + {"dbgwcr11_el1", 0x805F, true, true}, // 178 + {"dbgwcr12_el1", 0x8067, true, true}, // 179 + {"dbgwcr13_el1", 0x806F, true, true}, // 180 + {"dbgwcr14_el1", 0x8077, true, true}, // 181 + {"dbgwcr15_el1", 0x807F, true, true}, // 182 + {"teehbr32_el1", 0x9080, true, true}, // 183 + {"osdlr_el1", 0x809C, true, true}, // 184 + {"dbgprcr_el1", 0x80A4, true, true}, // 185 + {"dbgclaimset_el1", 0x83C6, true, true}, // 186 + {"dbgclaimclr_el1", 0x83CE, true, true}, // 187 + {"csselr_el1", 0xD000, true, true}, // 188 + {"vpidr_el2", 0xE000, true, true}, // 189 + {"vmpidr_el2", 0xE005, true, true}, // 190 + {"cpacr_el1", 0xC082, true, true}, // 191 + {"sctlr_el1", 0xC080, true, true}, // 192 + {"sctlr_el2", 0xE080, true, true}, // 193 + {"sctlr_el3", 0xF080, true, true}, // 194 + {"actlr_el1", 0xC081, true, true}, // 195 + {"actlr_el2", 0xE081, true, true}, // 196 + {"actlr_el3", 0xF081, true, true}, // 197 + {"hcr_el2", 0xE088, true, true}, // 198 + {"scr_el3", 0xF088, true, true}, // 199 + {"mdcr_el2", 0xE089, true, true}, // 200 + {"sder32_el3", 0xF089, true, true}, // 201 + {"cptr_el2", 0xE08A, true, true}, // 202 + {"cptr_el3", 0xF08A, true, true}, // 203 + {"hstr_el2", 0xE08B, true, true}, // 204 + {"hacr_el2", 0xE08F, true, true}, // 205 + {"mdcr_el3", 0xF099, true, true}, // 206 + {"ttbr0_el1", 0xC100, true, true}, // 207 + {"ttbr0_el2", 0xE100, true, true}, // 208 + {"ttbr0_el3", 0xF100, true, true}, // 209 + {"ttbr1_el1", 0xC101, true, true}, // 210 + {"tcr_el1", 0xC102, true, true}, // 211 + {"tcr_el2", 0xE102, true, true}, // 212 + {"tcr_el3", 0xF102, true, true}, // 213 + {"vttbr_el2", 0xE108, true, true}, // 214 + {"vtcr_el2", 0xE10A, true, true}, // 215 + {"dacr32_el2", 0xE180, true, true}, // 216 + {"spsr_el1", 0xC200, true, true}, // 217 + {"spsr_el2", 0xE200, true, true}, // 218 + {"spsr_el3", 0xF200, true, true}, // 219 + {"elr_el1", 0xC201, true, true}, // 220 + {"elr_el2", 0xE201, true, true}, // 221 + {"elr_el3", 0xF201, true, true}, // 222 + {"sp_el0", 0xC208, true, true}, // 223 + {"sp_el1", 0xE208, true, true}, // 224 + {"sp_el2", 0xF208, true, true}, // 225 + {"spsel", 0xC210, true, true}, // 226 + {"nzcv", 0xDA10, true, true}, // 227 + {"daif", 0xDA11, true, true}, // 228 + {"currentel", 0xC212, true, true}, // 229 + {"spsr_irq", 0xE218, true, true}, // 230 + {"spsr_abt", 0xE219, true, true}, // 231 + {"spsr_und", 0xE21A, true, true}, // 232 + {"spsr_fiq", 0xE21B, true, true}, // 233 + {"fpcr", 0xDA20, true, true}, // 234 + {"fpsr", 0xDA21, true, true}, // 235 + {"dspsr_el0", 0xDA28, true, true}, // 236 + {"dlr_el0", 0xDA29, true, true}, // 237 + {"ifsr32_el2", 0xE281, true, true}, // 238 + {"afsr0_el1", 0xC288, true, true}, // 239 + {"afsr0_el2", 0xE288, true, true}, // 240 + {"afsr0_el3", 0xF288, true, true}, // 241 + {"afsr1_el1", 0xC289, true, true}, // 242 + {"afsr1_el2", 0xE289, true, true}, // 243 + {"afsr1_el3", 0xF289, true, true}, // 244 + {"esr_el1", 0xC290, true, true}, // 245 + {"esr_el2", 0xE290, true, true}, // 246 + {"esr_el3", 0xF290, true, true}, // 247 + {"fpexc32_el2", 0xE298, true, true}, // 248 + {"far_el1", 0xC300, true, true}, // 249 + {"far_el2", 0xE300, true, true}, // 250 + {"far_el3", 0xF300, true, true}, // 251 + {"hpfar_el2", 0xE304, true, true}, // 252 + {"par_el1", 0xC3A0, true, true}, // 253 + {"pmcr_el0", 0xDCE0, true, true}, // 254 + {"pmcntenset_el0", 0xDCE1, true, true}, // 255 + {"pmcntenclr_el0", 0xDCE2, true, true}, // 256 + {"pmovsclr_el0", 0xDCE3, true, true}, // 257 + {"pmselr_el0", 0xDCE5, true, true}, // 258 + {"pmccntr_el0", 0xDCE8, true, true}, // 259 + {"pmxevtyper_el0", 0xDCE9, true, true}, // 260 + {"pmxevcntr_el0", 0xDCEA, true, true}, // 261 + {"pmuserenr_el0", 0xDCF0, true, true}, // 262 + {"pmintenset_el1", 0xC4F1, true, true}, // 263 + {"pmintenclr_el1", 0xC4F2, true, true}, // 264 + {"pmovsset_el0", 0xDCF3, true, true}, // 265 + {"mair_el1", 0xC510, true, true}, // 266 + {"mair_el2", 0xE510, true, true}, // 267 + {"mair_el3", 0xF510, true, true}, // 268 + {"amair_el1", 0xC518, true, true}, // 269 + {"amair_el2", 0xE518, true, true}, // 270 + {"amair_el3", 0xF518, true, true}, // 271 + {"vbar_el1", 0xC600, true, true}, // 272 + {"vbar_el2", 0xE600, true, true}, // 273 + {"vbar_el3", 0xF600, true, true}, // 274 + {"rmr_el1", 0xC602, true, true}, // 275 + {"rmr_el2", 0xE602, true, true}, // 276 + {"rmr_el3", 0xF602, true, true}, // 277 + {"contextidr_el1", 0xC681, true, true}, // 278 + {"tpidr_el0", 0xDE82, true, true}, // 279 + {"tpidr_el2", 0xE682, true, true}, // 280 + {"tpidr_el3", 0xF682, true, true}, // 281 + {"tpidrro_el0", 0xDE83, true, true}, // 282 + {"tpidr_el1", 0xC684, true, true}, // 283 + {"cntfrq_el0", 0xDF00, true, true}, // 284 + {"cntvoff_el2", 0xE703, true, true}, // 285 + {"cntkctl_el1", 0xC708, true, true}, // 286 + {"cnthctl_el2", 0xE708, true, true}, // 287 + {"cntp_tval_el0", 0xDF10, true, true}, // 288 + {"cnthp_tval_el2", 0xE710, true, true}, // 289 + {"cntps_tval_el1", 0xFF10, true, true}, // 290 + {"cntp_ctl_el0", 0xDF11, true, true}, // 291 + {"cnthp_ctl_el2", 0xE711, true, true}, // 292 + {"cntps_ctl_el1", 0xFF11, true, true}, // 293 + {"cntp_cval_el0", 0xDF12, true, true}, // 294 + {"cnthp_cval_el2", 0xE712, true, true}, // 295 + {"cntps_cval_el1", 0xFF12, true, true}, // 296 + {"cntv_tval_el0", 0xDF18, true, true}, // 297 + {"cntv_ctl_el0", 0xDF19, true, true}, // 298 + {"cntv_cval_el0", 0xDF1A, true, true}, // 299 + {"pmevcntr0_el0", 0xDF40, true, true}, // 300 + {"pmevcntr1_el0", 0xDF41, true, true}, // 301 + {"pmevcntr2_el0", 0xDF42, true, true}, // 302 + {"pmevcntr3_el0", 0xDF43, true, true}, // 303 + {"pmevcntr4_el0", 0xDF44, true, true}, // 304 + {"pmevcntr5_el0", 0xDF45, true, true}, // 305 + {"pmevcntr6_el0", 0xDF46, true, true}, // 306 + {"pmevcntr7_el0", 0xDF47, true, true}, // 307 + {"pmevcntr8_el0", 0xDF48, true, true}, // 308 + {"pmevcntr9_el0", 0xDF49, true, true}, // 309 + {"pmevcntr10_el0", 0xDF4A, true, true}, // 310 + {"pmevcntr11_el0", 0xDF4B, true, true}, // 311 + {"pmevcntr12_el0", 0xDF4C, true, true}, // 312 + {"pmevcntr13_el0", 0xDF4D, true, true}, // 313 + {"pmevcntr14_el0", 0xDF4E, true, true}, // 314 + {"pmevcntr15_el0", 0xDF4F, true, true}, // 315 + {"pmevcntr16_el0", 0xDF50, true, true}, // 316 + {"pmevcntr17_el0", 0xDF51, true, true}, // 317 + {"pmevcntr18_el0", 0xDF52, true, true}, // 318 + {"pmevcntr19_el0", 0xDF53, true, true}, // 319 + {"pmevcntr20_el0", 0xDF54, true, true}, // 320 + {"pmevcntr21_el0", 0xDF55, true, true}, // 321 + {"pmevcntr22_el0", 0xDF56, true, true}, // 322 + {"pmevcntr23_el0", 0xDF57, true, true}, // 323 + {"pmevcntr24_el0", 0xDF58, true, true}, // 324 + {"pmevcntr25_el0", 0xDF59, true, true}, // 325 + {"pmevcntr26_el0", 0xDF5A, true, true}, // 326 + {"pmevcntr27_el0", 0xDF5B, true, true}, // 327 + {"pmevcntr28_el0", 0xDF5C, true, true}, // 328 + {"pmevcntr29_el0", 0xDF5D, true, true}, // 329 + {"pmevcntr30_el0", 0xDF5E, true, true}, // 330 + {"pmccfiltr_el0", 0xDF7F, true, true}, // 331 + {"pmevtyper0_el0", 0xDF60, true, true}, // 332 + {"pmevtyper1_el0", 0xDF61, true, true}, // 333 + {"pmevtyper2_el0", 0xDF62, true, true}, // 334 + {"pmevtyper3_el0", 0xDF63, true, true}, // 335 + {"pmevtyper4_el0", 0xDF64, true, true}, // 336 + {"pmevtyper5_el0", 0xDF65, true, true}, // 337 + {"pmevtyper6_el0", 0xDF66, true, true}, // 338 + {"pmevtyper7_el0", 0xDF67, true, true}, // 339 + {"pmevtyper8_el0", 0xDF68, true, true}, // 340 + {"pmevtyper9_el0", 0xDF69, true, true}, // 341 + {"pmevtyper10_el0", 0xDF6A, true, true}, // 342 + {"pmevtyper11_el0", 0xDF6B, true, true}, // 343 + {"pmevtyper12_el0", 0xDF6C, true, true}, // 344 + {"pmevtyper13_el0", 0xDF6D, true, true}, // 345 + {"pmevtyper14_el0", 0xDF6E, true, true}, // 346 + {"pmevtyper15_el0", 0xDF6F, true, true}, // 347 + {"pmevtyper16_el0", 0xDF70, true, true}, // 348 + {"pmevtyper17_el0", 0xDF71, true, true}, // 349 + {"pmevtyper18_el0", 0xDF72, true, true}, // 350 + {"pmevtyper19_el0", 0xDF73, true, true}, // 351 + {"pmevtyper20_el0", 0xDF74, true, true}, // 352 + {"pmevtyper21_el0", 0xDF75, true, true}, // 353 + {"pmevtyper22_el0", 0xDF76, true, true}, // 354 + {"pmevtyper23_el0", 0xDF77, true, true}, // 355 + {"pmevtyper24_el0", 0xDF78, true, true}, // 356 + {"pmevtyper25_el0", 0xDF79, true, true}, // 357 + {"pmevtyper26_el0", 0xDF7A, true, true}, // 358 + {"pmevtyper27_el0", 0xDF7B, true, true}, // 359 + {"pmevtyper28_el0", 0xDF7C, true, true}, // 360 + {"pmevtyper29_el0", 0xDF7D, true, true}, // 361 + {"pmevtyper30_el0", 0xDF7E, true, true}, // 362 + {"trcprgctlr", 0x8808, true, true}, // 363 + {"trcprocselr", 0x8810, true, true}, // 364 + {"trcconfigr", 0x8820, true, true}, // 365 + {"trcauxctlr", 0x8830, true, true}, // 366 + {"trceventctl0r", 0x8840, true, true}, // 367 + {"trceventctl1r", 0x8848, true, true}, // 368 + {"trcstallctlr", 0x8858, true, true}, // 369 + {"trctsctlr", 0x8860, true, true}, // 370 + {"trcsyncpr", 0x8868, true, true}, // 371 + {"trcccctlr", 0x8870, true, true}, // 372 + {"trcbbctlr", 0x8878, true, true}, // 373 + {"trctraceidr", 0x8801, true, true}, // 374 + {"trcqctlr", 0x8809, true, true}, // 375 + {"trcvictlr", 0x8802, true, true}, // 376 + {"trcviiectlr", 0x880A, true, true}, // 377 + {"trcvissctlr", 0x8812, true, true}, // 378 + {"trcvipcssctlr", 0x881A, true, true}, // 379 + {"trcvdctlr", 0x8842, true, true}, // 380 + {"trcvdsacctlr", 0x884A, true, true}, // 381 + {"trcvdarcctlr", 0x8852, true, true}, // 382 + {"trcseqevr0", 0x8804, true, true}, // 383 + {"trcseqevr1", 0x880C, true, true}, // 384 + {"trcseqevr2", 0x8814, true, true}, // 385 + {"trcseqrstevr", 0x8834, true, true}, // 386 + {"trcseqstr", 0x883C, true, true}, // 387 + {"trcextinselr", 0x8844, true, true}, // 388 + {"trccntrldvr0", 0x8805, true, true}, // 389 + {"trccntrldvr1", 0x880D, true, true}, // 390 + {"trccntrldvr2", 0x8815, true, true}, // 391 + {"trccntrldvr3", 0x881D, true, true}, // 392 + {"trccntctlr0", 0x8825, true, true}, // 393 + {"trccntctlr1", 0x882D, true, true}, // 394 + {"trccntctlr2", 0x8835, true, true}, // 395 + {"trccntctlr3", 0x883D, true, true}, // 396 + {"trccntvr0", 0x8845, true, true}, // 397 + {"trccntvr1", 0x884D, true, true}, // 398 + {"trccntvr2", 0x8855, true, true}, // 399 + {"trccntvr3", 0x885D, true, true}, // 400 + {"trcimspec0", 0x8807, true, true}, // 401 + {"trcimspec1", 0x880F, true, true}, // 402 + {"trcimspec2", 0x8817, true, true}, // 403 + {"trcimspec3", 0x881F, true, true}, // 404 + {"trcimspec4", 0x8827, true, true}, // 405 + {"trcimspec5", 0x882F, true, true}, // 406 + {"trcimspec6", 0x8837, true, true}, // 407 + {"trcimspec7", 0x883F, true, true}, // 408 + {"trcrsctlr2", 0x8890, true, true}, // 409 + {"trcrsctlr3", 0x8898, true, true}, // 410 + {"trcrsctlr4", 0x88A0, true, true}, // 411 + {"trcrsctlr5", 0x88A8, true, true}, // 412 + {"trcrsctlr6", 0x88B0, true, true}, // 413 + {"trcrsctlr7", 0x88B8, true, true}, // 414 + {"trcrsctlr8", 0x88C0, true, true}, // 415 + {"trcrsctlr9", 0x88C8, true, true}, // 416 + {"trcrsctlr10", 0x88D0, true, true}, // 417 + {"trcrsctlr11", 0x88D8, true, true}, // 418 + {"trcrsctlr12", 0x88E0, true, true}, // 419 + {"trcrsctlr13", 0x88E8, true, true}, // 420 + {"trcrsctlr14", 0x88F0, true, true}, // 421 + {"trcrsctlr15", 0x88F8, true, true}, // 422 + {"trcrsctlr16", 0x8881, true, true}, // 423 + {"trcrsctlr17", 0x8889, true, true}, // 424 + {"trcrsctlr18", 0x8891, true, true}, // 425 + {"trcrsctlr19", 0x8899, true, true}, // 426 + {"trcrsctlr20", 0x88A1, true, true}, // 427 + {"trcrsctlr21", 0x88A9, true, true}, // 428 + {"trcrsctlr22", 0x88B1, true, true}, // 429 + {"trcrsctlr23", 0x88B9, true, true}, // 430 + {"trcrsctlr24", 0x88C1, true, true}, // 431 + {"trcrsctlr25", 0x88C9, true, true}, // 432 + {"trcrsctlr26", 0x88D1, true, true}, // 433 + {"trcrsctlr27", 0x88D9, true, true}, // 434 + {"trcrsctlr28", 0x88E1, true, true}, // 435 + {"trcrsctlr29", 0x88E9, true, true}, // 436 + {"trcrsctlr30", 0x88F1, true, true}, // 437 + {"trcrsctlr31", 0x88F9, true, true}, // 438 + {"trcssccr0", 0x8882, true, true}, // 439 + {"trcssccr1", 0x888A, true, true}, // 440 + {"trcssccr2", 0x8892, true, true}, // 441 + {"trcssccr3", 0x889A, true, true}, // 442 + {"trcssccr4", 0x88A2, true, true}, // 443 + {"trcssccr5", 0x88AA, true, true}, // 444 + {"trcssccr6", 0x88B2, true, true}, // 445 + {"trcssccr7", 0x88BA, true, true}, // 446 + {"trcsscsr0", 0x88C2, true, true}, // 447 + {"trcsscsr1", 0x88CA, true, true}, // 448 + {"trcsscsr2", 0x88D2, true, true}, // 449 + {"trcsscsr3", 0x88DA, true, true}, // 450 + {"trcsscsr4", 0x88E2, true, true}, // 451 + {"trcsscsr5", 0x88EA, true, true}, // 452 + {"trcsscsr6", 0x88F2, true, true}, // 453 + {"trcsscsr7", 0x88FA, true, true}, // 454 + {"trcsspcicr0", 0x8883, true, true}, // 455 + {"trcsspcicr1", 0x888B, true, true}, // 456 + {"trcsspcicr2", 0x8893, true, true}, // 457 + {"trcsspcicr3", 0x889B, true, true}, // 458 + {"trcsspcicr4", 0x88A3, true, true}, // 459 + {"trcsspcicr5", 0x88AB, true, true}, // 460 + {"trcsspcicr6", 0x88B3, true, true}, // 461 + {"trcsspcicr7", 0x88BB, true, true}, // 462 + {"trcpdcr", 0x88A4, true, true}, // 463 + {"trcacvr0", 0x8900, true, true}, // 464 + {"trcacvr1", 0x8910, true, true}, // 465 + {"trcacvr2", 0x8920, true, true}, // 466 + {"trcacvr3", 0x8930, true, true}, // 467 + {"trcacvr4", 0x8940, true, true}, // 468 + {"trcacvr5", 0x8950, true, true}, // 469 + {"trcacvr6", 0x8960, true, true}, // 470 + {"trcacvr7", 0x8970, true, true}, // 471 + {"trcacvr8", 0x8901, true, true}, // 472 + {"trcacvr9", 0x8911, true, true}, // 473 + {"trcacvr10", 0x8921, true, true}, // 474 + {"trcacvr11", 0x8931, true, true}, // 475 + {"trcacvr12", 0x8941, true, true}, // 476 + {"trcacvr13", 0x8951, true, true}, // 477 + {"trcacvr14", 0x8961, true, true}, // 478 + {"trcacvr15", 0x8971, true, true}, // 479 + {"trcacatr0", 0x8902, true, true}, // 480 + {"trcacatr1", 0x8912, true, true}, // 481 + {"trcacatr2", 0x8922, true, true}, // 482 + {"trcacatr3", 0x8932, true, true}, // 483 + {"trcacatr4", 0x8942, true, true}, // 484 + {"trcacatr5", 0x8952, true, true}, // 485 + {"trcacatr6", 0x8962, true, true}, // 486 + {"trcacatr7", 0x8972, true, true}, // 487 + {"trcacatr8", 0x8903, true, true}, // 488 + {"trcacatr9", 0x8913, true, true}, // 489 + {"trcacatr10", 0x8923, true, true}, // 490 + {"trcacatr11", 0x8933, true, true}, // 491 + {"trcacatr12", 0x8943, true, true}, // 492 + {"trcacatr13", 0x8953, true, true}, // 493 + {"trcacatr14", 0x8963, true, true}, // 494 + {"trcacatr15", 0x8973, true, true}, // 495 + {"trcdvcvr0", 0x8904, true, true}, // 496 + {"trcdvcvr1", 0x8924, true, true}, // 497 + {"trcdvcvr2", 0x8944, true, true}, // 498 + {"trcdvcvr3", 0x8964, true, true}, // 499 + {"trcdvcvr4", 0x8905, true, true}, // 500 + {"trcdvcvr5", 0x8925, true, true}, // 501 + {"trcdvcvr6", 0x8945, true, true}, // 502 + {"trcdvcvr7", 0x8965, true, true}, // 503 + {"trcdvcmr0", 0x8906, true, true}, // 504 + {"trcdvcmr1", 0x8926, true, true}, // 505 + {"trcdvcmr2", 0x8946, true, true}, // 506 + {"trcdvcmr3", 0x8966, true, true}, // 507 + {"trcdvcmr4", 0x8907, true, true}, // 508 + {"trcdvcmr5", 0x8927, true, true}, // 509 + {"trcdvcmr6", 0x8947, true, true}, // 510 + {"trcdvcmr7", 0x8967, true, true}, // 511 + {"trccidcvr0", 0x8980, true, true}, // 512 + {"trccidcvr1", 0x8990, true, true}, // 513 + {"trccidcvr2", 0x89A0, true, true}, // 514 + {"trccidcvr3", 0x89B0, true, true}, // 515 + {"trccidcvr4", 0x89C0, true, true}, // 516 + {"trccidcvr5", 0x89D0, true, true}, // 517 + {"trccidcvr6", 0x89E0, true, true}, // 518 + {"trccidcvr7", 0x89F0, true, true}, // 519 + {"trcvmidcvr0", 0x8981, true, true}, // 520 + {"trcvmidcvr1", 0x8991, true, true}, // 521 + {"trcvmidcvr2", 0x89A1, true, true}, // 522 + {"trcvmidcvr3", 0x89B1, true, true}, // 523 + {"trcvmidcvr4", 0x89C1, true, true}, // 524 + {"trcvmidcvr5", 0x89D1, true, true}, // 525 + {"trcvmidcvr6", 0x89E1, true, true}, // 526 + {"trcvmidcvr7", 0x89F1, true, true}, // 527 + {"trccidcctlr0", 0x8982, true, true}, // 528 + {"trccidcctlr1", 0x898A, true, true}, // 529 + {"trcvmidcctlr0", 0x8992, true, true}, // 530 + {"trcvmidcctlr1", 0x899A, true, true}, // 531 + {"trcitctrl", 0x8B84, true, true}, // 532 + {"trcclaimset", 0x8BC6, true, true}, // 533 + {"trcclaimclr", 0x8BCE, true, true}, // 534 + {"icc_bpr1_el1", 0xC663, true, true}, // 535 + {"icc_bpr0_el1", 0xC643, true, true}, // 536 + {"icc_pmr_el1", 0xC230, true, true}, // 537 + {"icc_ctlr_el1", 0xC664, true, true}, // 538 + {"icc_ctlr_el3", 0xF664, true, true}, // 539 + {"icc_sre_el1", 0xC665, true, true}, // 540 + {"icc_sre_el2", 0xE64D, true, true}, // 541 + {"icc_sre_el3", 0xF665, true, true}, // 542 + {"icc_igrpen0_el1", 0xC666, true, true}, // 543 + {"icc_igrpen1_el1", 0xC667, true, true}, // 544 + {"icc_igrpen1_el3", 0xF667, true, true}, // 545 + {"icc_seien_el1", 0xC668, true, true}, // 546 + {"icc_ap0r0_el1", 0xC644, true, true}, // 547 + {"icc_ap0r1_el1", 0xC645, true, true}, // 548 + {"icc_ap0r2_el1", 0xC646, true, true}, // 549 + {"icc_ap0r3_el1", 0xC647, true, true}, // 550 + {"icc_ap1r0_el1", 0xC648, true, true}, // 551 + {"icc_ap1r1_el1", 0xC649, true, true}, // 552 + {"icc_ap1r2_el1", 0xC64A, true, true}, // 553 + {"icc_ap1r3_el1", 0xC64B, true, true}, // 554 + {"ich_ap0r0_el2", 0xE640, true, true}, // 555 + {"ich_ap0r1_el2", 0xE641, true, true}, // 556 + {"ich_ap0r2_el2", 0xE642, true, true}, // 557 + {"ich_ap0r3_el2", 0xE643, true, true}, // 558 + {"ich_ap1r0_el2", 0xE648, true, true}, // 559 + {"ich_ap1r1_el2", 0xE649, true, true}, // 560 + {"ich_ap1r2_el2", 0xE64A, true, true}, // 561 + {"ich_ap1r3_el2", 0xE64B, true, true}, // 562 + {"ich_hcr_el2", 0xE658, true, true}, // 563 + {"ich_misr_el2", 0xE65A, true, true}, // 564 + {"ich_vmcr_el2", 0xE65F, true, true}, // 565 + {"ich_vseir_el2", 0xE64C, true, true}, // 566 + {"ich_lr0_el2", 0xE660, true, true}, // 567 + {"ich_lr1_el2", 0xE661, true, true}, // 568 + {"ich_lr2_el2", 0xE662, true, true}, // 569 + {"ich_lr3_el2", 0xE663, true, true}, // 570 + {"ich_lr4_el2", 0xE664, true, true}, // 571 + {"ich_lr5_el2", 0xE665, true, true}, // 572 + {"ich_lr6_el2", 0xE666, true, true}, // 573 + {"ich_lr7_el2", 0xE667, true, true}, // 574 + {"ich_lr8_el2", 0xE668, true, true}, // 575 + {"ich_lr9_el2", 0xE669, true, true}, // 576 + {"ich_lr10_el2", 0xE66A, true, true}, // 577 + {"ich_lr11_el2", 0xE66B, true, true}, // 578 + {"ich_lr12_el2", 0xE66C, true, true}, // 579 + {"ich_lr13_el2", 0xE66D, true, true}, // 580 + {"ich_lr14_el2", 0xE66E, true, true}, // 581 + {"ich_lr15_el2", 0xE66F, true, true}, // 582 + {"pan", 0xC213, true, true}, // 583 + {"lorsa_el1", 0xC520, true, true}, // 584 + {"lorea_el1", 0xC521, true, true}, // 585 + {"lorn_el1", 0xC522, true, true}, // 586 + {"lorc_el1", 0xC523, true, true}, // 587 + {"ttbr1_el2", 0xE101, true, true}, // 588 + {"contextidr_el2", 0xE681, true, true}, // 589 + {"cnthv_tval_el2", 0xE718, true, true}, // 590 + {"cnthv_cval_el2", 0xE71A, true, true}, // 591 + {"cnthv_ctl_el2", 0xE719, true, true}, // 592 + {"sctlr_el12", 0xE880, true, true}, // 593 + {"cpacr_el12", 0xE882, true, true}, // 594 + {"ttbr0_el12", 0xE900, true, true}, // 595 + {"ttbr1_el12", 0xE901, true, true}, // 596 + {"tcr_el12", 0xE902, true, true}, // 597 + {"afsr0_el12", 0xEA88, true, true}, // 598 + {"afsr1_el12", 0xEA89, true, true}, // 599 + {"esr_el12", 0xEA90, true, true}, // 600 + {"far_el12", 0xEB00, true, true}, // 601 + {"mair_el12", 0xED10, true, true}, // 602 + {"amair_el12", 0xED18, true, true}, // 603 + {"vbar_el12", 0xEE00, true, true}, // 604 + {"contextidr_el12", 0xEE81, true, true}, // 605 + {"cntkctl_el12", 0xEF08, true, true}, // 606 + {"cntp_tval_el02", 0xEF10, true, true}, // 607 + {"cntp_ctl_el02", 0xEF11, true, true}, // 608 + {"cntp_cval_el02", 0xEF12, true, true}, // 609 + {"cntv_tval_el02", 0xEF18, true, true}, // 610 + {"cntv_ctl_el02", 0xEF19, true, true}, // 611 + {"cntv_cval_el02", 0xEF1A, true, true}, // 612 + {"spsr_el12", 0xEA00, true, true}, // 613 + {"elr_el12", 0xEA01, true, true}, // 614 + {"uao", 0xC214, true, true}, // 615 + {"pmblimitr_el1", 0xC4D0, true, true}, // 616 + {"pmbptr_el1", 0xC4D1, true, true}, // 617 + {"pmbsr_el1", 0xC4D3, true, true}, // 618 + {"pmbidr_el1", 0xC4D7, true, true}, // 619 + {"pmscr_el2", 0xE4C8, true, true}, // 620 + {"pmscr_el12", 0xECC8, true, true}, // 621 + {"pmscr_el1", 0xC4C8, true, true}, // 622 + {"pmsicr_el1", 0xC4CA, true, true}, // 623 + {"pmsirr_el1", 0xC4CB, true, true}, // 624 + {"pmsfcr_el1", 0xC4CC, true, true}, // 625 + {"pmsevfr_el1", 0xC4CD, true, true}, // 626 + {"pmslatfr_el1", 0xC4CE, true, true}, // 627 + {"pmsidr_el1", 0xC4CF, true, true}, // 628 + {"errselr_el1", 0xC299, true, true}, // 629 + {"erxctlr_el1", 0xC2A1, true, true}, // 630 + {"erxstatus_el1", 0xC2A2, true, true}, // 631 + {"erxaddr_el1", 0xC2A3, true, true}, // 632 + {"erxmisc0_el1", 0xC2A8, true, true}, // 633 + {"erxmisc1_el1", 0xC2A9, true, true}, // 634 + {"disr_el1", 0xC609, true, true}, // 635 + {"vdisr_el2", 0xE609, true, true}, // 636 + {"vsesr_el2", 0xE293, true, true}, // 637 + {"apiakeylo_el1", 0xC108, true, true}, // 638 + {"apiakeyhi_el1", 0xC109, true, true}, // 639 + {"apibkeylo_el1", 0xC10A, true, true}, // 640 + {"apibkeyhi_el1", 0xC10B, true, true}, // 641 + {"apdakeylo_el1", 0xC110, true, true}, // 642 + {"apdakeyhi_el1", 0xC111, true, true}, // 643 + {"apdbkeylo_el1", 0xC112, true, true}, // 644 + {"apdbkeyhi_el1", 0xC113, true, true}, // 645 + {"apgakeylo_el1", 0xC118, true, true}, // 646 + {"apgakeyhi_el1", 0xC119, true, true}, // 647 + {"vstcr_el2", 0xE132, true, true}, // 648 + {"vsttbr_el2", 0xE130, true, true}, // 649 + {"cnthvs_tval_el2", 0xE720, true, true}, // 650 + {"cnthvs_cval_el2", 0xE722, true, true}, // 651 + {"cnthvs_ctl_el2", 0xE721, true, true}, // 652 + {"cnthps_tval_el2", 0xE728, true, true}, // 653 + {"cnthps_cval_el2", 0xE72A, true, true}, // 654 + {"cnthps_ctl_el2", 0xE729, true, true}, // 655 + {"sder32_el2", 0xE099, true, true}, // 656 + {"erxpfgctl_el1", 0xC2A5, true, true}, // 657 + {"erxpfgcdn_el1", 0xC2A6, true, true}, // 658 + {"erxts_el1", 0xC2AF, true, true}, // 659 + {"erxmisc2_el1", 0xC2AA, true, true}, // 660 + {"erxmisc3_el1", 0xC2AB, true, true}, // 661 + {"erxpfgf_el1", 0xC2A4, true, false}, // 662 + {"mpam0_el1", 0xC529, true, true}, // 663 + {"mpam1_el1", 0xC528, true, true}, // 664 + {"mpam2_el2", 0xE528, true, true}, // 665 + {"mpam3_el3", 0xF528, true, true}, // 666 + {"mpam1_el12", 0xED28, true, true}, // 667 + {"mpamhcr_el2", 0xE520, true, true}, // 668 + {"mpamvpmv_el2", 0xE521, true, true}, // 669 + {"mpamvpm0_el2", 0xE530, true, true}, // 670 + {"mpamvpm1_el2", 0xE531, true, true}, // 671 + {"mpamvpm2_el2", 0xE532, true, true}, // 672 + {"mpamvpm3_el2", 0xE533, true, true}, // 673 + {"mpamvpm4_el2", 0xE534, true, true}, // 674 + {"mpamvpm5_el2", 0xE535, true, true}, // 675 + {"mpamvpm6_el2", 0xE536, true, true}, // 676 + {"mpamvpm7_el2", 0xE537, true, true}, // 677 + {"mpamidr_el1", 0xC524, true, false}, // 678 + {"amcr_el0", 0xDE90, true, true}, // 679 + {"amcfgr_el0", 0xDE91, true, false}, // 680 + {"amcgcr_el0", 0xDE92, true, false}, // 681 + {"amuserenr_el0", 0xDE93, true, true}, // 682 + {"amcntenclr0_el0", 0xDE94, true, true}, // 683 + {"amcntenset0_el0", 0xDE95, true, true}, // 684 + {"amevcntr00_el0", 0xDEA0, true, true}, // 685 + {"amevcntr01_el0", 0xDEA1, true, true}, // 686 + {"amevcntr02_el0", 0xDEA2, true, true}, // 687 + {"amevcntr03_el0", 0xDEA3, true, true}, // 688 + {"amevtyper00_el0", 0xDEB0, true, false}, // 689 + {"amevtyper01_el0", 0xDEB1, true, false}, // 690 + {"amevtyper02_el0", 0xDEB2, true, false}, // 691 + {"amevtyper03_el0", 0xDEB3, true, false}, // 692 + {"amcntenclr1_el0", 0xDE98, true, true}, // 693 + {"amcntenset1_el0", 0xDE99, true, true}, // 694 + {"amevcntr10_el0", 0xDEE0, true, true}, // 695 + {"amevcntr11_el0", 0xDEE1, true, true}, // 696 + {"amevcntr12_el0", 0xDEE2, true, true}, // 697 + {"amevcntr13_el0", 0xDEE3, true, true}, // 698 + {"amevcntr14_el0", 0xDEE4, true, true}, // 699 + {"amevcntr15_el0", 0xDEE5, true, true}, // 700 + {"amevcntr16_el0", 0xDEE6, true, true}, // 701 + {"amevcntr17_el0", 0xDEE7, true, true}, // 702 + {"amevcntr18_el0", 0xDEE8, true, true}, // 703 + {"amevcntr19_el0", 0xDEE9, true, true}, // 704 + {"amevcntr110_el0", 0xDEEA, true, true}, // 705 + {"amevcntr111_el0", 0xDEEB, true, true}, // 706 + {"amevcntr112_el0", 0xDEEC, true, true}, // 707 + {"amevcntr113_el0", 0xDEED, true, true}, // 708 + {"amevcntr114_el0", 0xDEEE, true, true}, // 709 + {"amevcntr115_el0", 0xDEEF, true, true}, // 710 + {"amevtyper10_el0", 0xDEF0, true, true}, // 711 + {"amevtyper11_el0", 0xDEF1, true, true}, // 712 + {"amevtyper12_el0", 0xDEF2, true, true}, // 713 + {"amevtyper13_el0", 0xDEF3, true, true}, // 714 + {"amevtyper14_el0", 0xDEF4, true, true}, // 715 + {"amevtyper15_el0", 0xDEF5, true, true}, // 716 + {"amevtyper16_el0", 0xDEF6, true, true}, // 717 + {"amevtyper17_el0", 0xDEF7, true, true}, // 718 + {"amevtyper18_el0", 0xDEF8, true, true}, // 719 + {"amevtyper19_el0", 0xDEF9, true, true}, // 720 + {"amevtyper110_el0", 0xDEFA, true, true}, // 721 + {"amevtyper111_el0", 0xDEFB, true, true}, // 722 + {"amevtyper112_el0", 0xDEFC, true, true}, // 723 + {"amevtyper113_el0", 0xDEFD, true, true}, // 724 + {"amevtyper114_el0", 0xDEFE, true, true}, // 725 + {"amevtyper115_el0", 0xDEFF, true, true}, // 726 + {"trfcr_el1", 0xC091, true, true}, // 727 + {"trfcr_el2", 0xE091, true, true}, // 728 + {"trfcr_el12", 0xE891, true, true}, // 729 + {"dit", 0xDA15, true, true}, // 730 + {"vncr_el2", 0xE110, true, true}, // 731 + {"zcr_el1", 0xC090, true, true}, // 732 + {"zcr_el2", 0xE090, true, true}, // 733 + {"zcr_el3", 0xF090, true, true}, // 734 + {"zcr_el12", 0xE890, true, true}, // 735 + {"cpm_ioacc_ctl_el3", 0xFF90, true, true}, // 736 }; -const SysReg *lookupSysRegByEncoding(uint16_t Encoding) -{ +const SysReg *lookupSysRegByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x8002, 111 }, - { 0x8004, 119 }, - { 0x8005, 135 }, - { 0x8006, 151 }, - { 0x8007, 167 }, - { 0x800C, 120 }, - { 0x800D, 136 }, - { 0x800E, 152 }, - { 0x800F, 168 }, - { 0x8010, 114 }, - { 0x8012, 115 }, - { 0x8014, 121 }, - { 0x8015, 137 }, - { 0x8016, 153 }, - { 0x8017, 169 }, - { 0x801A, 112 }, - { 0x801C, 122 }, - { 0x801D, 138 }, - { 0x801E, 154 }, - { 0x801F, 170 }, - { 0x8024, 123 }, - { 0x8025, 139 }, - { 0x8026, 155 }, - { 0x8027, 171 }, - { 0x802C, 124 }, - { 0x802D, 140 }, - { 0x802E, 156 }, - { 0x802F, 172 }, - { 0x8032, 117 }, - { 0x8034, 125 }, - { 0x8035, 141 }, - { 0x8036, 157 }, - { 0x8037, 173 }, - { 0x803C, 126 }, - { 0x803D, 142 }, - { 0x803E, 158 }, - { 0x803F, 174 }, - { 0x8044, 127 }, - { 0x8045, 143 }, - { 0x8046, 159 }, - { 0x8047, 175 }, - { 0x804C, 128 }, - { 0x804D, 144 }, - { 0x804E, 160 }, - { 0x804F, 176 }, - { 0x8054, 129 }, - { 0x8055, 145 }, - { 0x8056, 161 }, - { 0x8057, 177 }, - { 0x805C, 130 }, - { 0x805D, 146 }, - { 0x805E, 162 }, - { 0x805F, 178 }, - { 0x8064, 131 }, - { 0x8065, 147 }, - { 0x8066, 163 }, - { 0x8067, 179 }, - { 0x806C, 132 }, - { 0x806D, 148 }, - { 0x806E, 164 }, - { 0x806F, 180 }, - { 0x8074, 133 }, - { 0x8075, 149 }, - { 0x8076, 165 }, - { 0x8077, 181 }, - { 0x807C, 134 }, - { 0x807D, 150 }, - { 0x807E, 166 }, - { 0x807F, 182 }, - { 0x8080, 2 }, - { 0x8084, 101 }, - { 0x808C, 3 }, - { 0x809C, 184 }, - { 0x80A4, 185 }, - { 0x83C6, 186 }, - { 0x83CE, 187 }, - { 0x83F6, 4 }, - { 0x8801, 374 }, - { 0x8802, 376 }, - { 0x8804, 383 }, - { 0x8805, 389 }, - { 0x8806, 53 }, - { 0x8807, 401 }, - { 0x8808, 363 }, - { 0x8809, 375 }, - { 0x880A, 377 }, - { 0x880C, 384 }, - { 0x880D, 390 }, - { 0x880E, 54 }, - { 0x880F, 402 }, - { 0x8810, 364 }, - { 0x8812, 378 }, - { 0x8814, 385 }, - { 0x8815, 391 }, - { 0x8816, 55 }, - { 0x8817, 403 }, - { 0x8818, 52 }, - { 0x881A, 379 }, - { 0x881D, 392 }, - { 0x881E, 56 }, - { 0x881F, 404 }, - { 0x8820, 365 }, - { 0x8825, 393 }, - { 0x8826, 57 }, - { 0x8827, 405 }, - { 0x882D, 394 }, - { 0x882E, 58 }, - { 0x882F, 406 }, - { 0x8830, 366 }, - { 0x8834, 386 }, - { 0x8835, 395 }, - { 0x8837, 407 }, - { 0x883C, 387 }, - { 0x883D, 396 }, - { 0x883F, 408 }, - { 0x8840, 367 }, - { 0x8842, 380 }, - { 0x8844, 388 }, - { 0x8845, 397 }, - { 0x8847, 59 }, - { 0x8848, 368 }, - { 0x884A, 381 }, - { 0x884D, 398 }, - { 0x884F, 60 }, - { 0x8852, 382 }, - { 0x8855, 399 }, - { 0x8857, 61 }, - { 0x8858, 369 }, - { 0x885D, 400 }, - { 0x885F, 62 }, - { 0x8860, 370 }, - { 0x8867, 63 }, - { 0x8868, 371 }, - { 0x886F, 64 }, - { 0x8870, 372 }, - { 0x8877, 65 }, - { 0x8878, 373 }, - { 0x887F, 66 }, - { 0x8881, 423 }, - { 0x8882, 439 }, - { 0x8883, 455 }, - { 0x8884, 103 }, - { 0x8889, 424 }, - { 0x888A, 440 }, - { 0x888B, 456 }, - { 0x888C, 67 }, - { 0x8890, 409 }, - { 0x8891, 425 }, - { 0x8892, 441 }, - { 0x8893, 457 }, - { 0x8898, 410 }, - { 0x8899, 426 }, - { 0x889A, 442 }, - { 0x889B, 458 }, - { 0x88A0, 411 }, - { 0x88A1, 427 }, - { 0x88A2, 443 }, - { 0x88A3, 459 }, - { 0x88A4, 463 }, - { 0x88A8, 412 }, - { 0x88A9, 428 }, - { 0x88AA, 444 }, - { 0x88AB, 460 }, - { 0x88AC, 68 }, - { 0x88B0, 413 }, - { 0x88B1, 429 }, - { 0x88B2, 445 }, - { 0x88B3, 461 }, - { 0x88B8, 414 }, - { 0x88B9, 430 }, - { 0x88BA, 446 }, - { 0x88BB, 462 }, - { 0x88C0, 415 }, - { 0x88C1, 431 }, - { 0x88C2, 447 }, - { 0x88C8, 416 }, - { 0x88C9, 432 }, - { 0x88CA, 448 }, - { 0x88D0, 417 }, - { 0x88D1, 433 }, - { 0x88D2, 449 }, - { 0x88D8, 418 }, - { 0x88D9, 434 }, - { 0x88DA, 450 }, - { 0x88E0, 419 }, - { 0x88E1, 435 }, - { 0x88E2, 451 }, - { 0x88E8, 420 }, - { 0x88E9, 436 }, - { 0x88EA, 452 }, - { 0x88F0, 421 }, - { 0x88F1, 437 }, - { 0x88F2, 453 }, - { 0x88F8, 422 }, - { 0x88F9, 438 }, - { 0x88FA, 454 }, - { 0x8900, 464 }, - { 0x8901, 472 }, - { 0x8902, 480 }, - { 0x8903, 488 }, - { 0x8904, 496 }, - { 0x8905, 500 }, - { 0x8906, 504 }, - { 0x8907, 508 }, - { 0x8910, 465 }, - { 0x8911, 473 }, - { 0x8912, 481 }, - { 0x8913, 489 }, - { 0x8920, 466 }, - { 0x8921, 474 }, - { 0x8922, 482 }, - { 0x8923, 490 }, - { 0x8924, 497 }, - { 0x8925, 501 }, - { 0x8926, 505 }, - { 0x8927, 509 }, - { 0x8930, 467 }, - { 0x8931, 475 }, - { 0x8932, 483 }, - { 0x8933, 491 }, - { 0x8940, 468 }, - { 0x8941, 476 }, - { 0x8942, 484 }, - { 0x8943, 492 }, - { 0x8944, 498 }, - { 0x8945, 502 }, - { 0x8946, 506 }, - { 0x8947, 510 }, - { 0x8950, 469 }, - { 0x8951, 477 }, - { 0x8952, 485 }, - { 0x8953, 493 }, - { 0x8960, 470 }, - { 0x8961, 478 }, - { 0x8962, 486 }, - { 0x8963, 494 }, - { 0x8964, 499 }, - { 0x8965, 503 }, - { 0x8966, 507 }, - { 0x8967, 511 }, - { 0x8970, 471 }, - { 0x8971, 479 }, - { 0x8972, 487 }, - { 0x8973, 495 }, - { 0x8980, 512 }, - { 0x8981, 520 }, - { 0x8982, 528 }, - { 0x898A, 529 }, - { 0x8990, 513 }, - { 0x8991, 521 }, - { 0x8992, 530 }, - { 0x899A, 531 }, - { 0x89A0, 514 }, - { 0x89A1, 522 }, - { 0x89B0, 515 }, - { 0x89B1, 523 }, - { 0x89C0, 516 }, - { 0x89C1, 524 }, - { 0x89D0, 517 }, - { 0x89D1, 525 }, - { 0x89E0, 518 }, - { 0x89E1, 526 }, - { 0x89F0, 519 }, - { 0x89F1, 527 }, - { 0x8B84, 532 }, - { 0x8B97, 74 }, - { 0x8B9F, 75 }, - { 0x8BA7, 76 }, - { 0x8BAF, 77 }, - { 0x8BB7, 78 }, - { 0x8BBF, 79 }, - { 0x8BC6, 533 }, - { 0x8BC7, 80 }, - { 0x8BCE, 534 }, - { 0x8BCF, 81 }, - { 0x8BD6, 69 }, - { 0x8BD7, 82 }, - { 0x8BDE, 70 }, - { 0x8BDF, 83 }, - { 0x8BE6, 104 }, - { 0x8BE7, 84 }, - { 0x8BEE, 71 }, - { 0x8BEF, 85 }, - { 0x8BF6, 72 }, - { 0x8BF7, 86 }, - { 0x8BFE, 73 }, - { 0x8BFF, 87 }, - { 0x9000, 113 }, - { 0x9080, 183 }, - { 0x9808, 0 }, - { 0x9820, 116 }, - { 0x9828, 1 }, - { 0x9828, 100 }, - { 0xA038, 118 }, - { 0xC000, 7 }, - { 0xC005, 12 }, - { 0xC006, 13 }, - { 0xC008, 16 }, - { 0xC009, 17 }, - { 0xC00A, 18 }, - { 0xC00B, 19 }, - { 0xC00C, 20 }, - { 0xC00D, 21 }, - { 0xC00E, 22 }, - { 0xC00F, 23 }, - { 0xC010, 24 }, - { 0xC011, 25 }, - { 0xC012, 26 }, - { 0xC013, 27 }, - { 0xC014, 28 }, - { 0xC015, 29 }, - { 0xC016, 51 }, - { 0xC017, 30 }, - { 0xC018, 42 }, - { 0xC019, 43 }, - { 0xC01A, 44 }, - { 0xC020, 31 }, - { 0xC021, 32 }, - { 0xC024, 96 }, - { 0xC028, 33 }, - { 0xC029, 34 }, - { 0xC02C, 35 }, - { 0xC02D, 36 }, - { 0xC030, 37 }, - { 0xC031, 38 }, - { 0xC038, 39 }, - { 0xC039, 40 }, - { 0xC03A, 41 }, - { 0xC080, 192 }, - { 0xC081, 195 }, - { 0xC082, 191 }, - { 0xC090, 732 }, - { 0xC091, 727 }, - { 0xC100, 207 }, - { 0xC101, 210 }, - { 0xC102, 211 }, - { 0xC108, 638 }, - { 0xC109, 639 }, - { 0xC10A, 640 }, - { 0xC10B, 641 }, - { 0xC110, 642 }, - { 0xC111, 643 }, - { 0xC112, 644 }, - { 0xC113, 645 }, - { 0xC118, 646 }, - { 0xC119, 647 }, - { 0xC200, 217 }, - { 0xC201, 220 }, - { 0xC208, 223 }, - { 0xC210, 226 }, - { 0xC212, 229 }, - { 0xC213, 583 }, - { 0xC214, 615 }, - { 0xC230, 537 }, - { 0xC288, 239 }, - { 0xC289, 242 }, - { 0xC290, 245 }, - { 0xC298, 98 }, - { 0xC299, 629 }, - { 0xC2A0, 99 }, - { 0xC2A1, 630 }, - { 0xC2A2, 631 }, - { 0xC2A3, 632 }, - { 0xC2A4, 662 }, - { 0xC2A5, 657 }, - { 0xC2A6, 658 }, - { 0xC2A8, 633 }, - { 0xC2A9, 634 }, - { 0xC2AA, 660 }, - { 0xC2AB, 661 }, - { 0xC2AF, 659 }, - { 0xC300, 249 }, - { 0xC3A0, 253 }, - { 0xC4C8, 622 }, - { 0xC4CA, 623 }, - { 0xC4CB, 624 }, - { 0xC4CC, 625 }, - { 0xC4CD, 626 }, - { 0xC4CE, 627 }, - { 0xC4CF, 628 }, - { 0xC4D0, 616 }, - { 0xC4D1, 617 }, - { 0xC4D3, 618 }, - { 0xC4D7, 619 }, - { 0xC4F1, 263 }, - { 0xC4F2, 264 }, - { 0xC510, 266 }, - { 0xC518, 269 }, - { 0xC520, 584 }, - { 0xC521, 585 }, - { 0xC522, 586 }, - { 0xC523, 587 }, - { 0xC524, 678 }, - { 0xC527, 97 }, - { 0xC528, 664 }, - { 0xC529, 663 }, - { 0xC600, 272 }, - { 0xC601, 45 }, - { 0xC602, 275 }, - { 0xC608, 48 }, - { 0xC609, 635 }, - { 0xC640, 89 }, - { 0xC641, 106 }, - { 0xC642, 91 }, - { 0xC643, 536 }, - { 0xC644, 547 }, - { 0xC645, 548 }, - { 0xC646, 549 }, - { 0xC647, 550 }, - { 0xC648, 551 }, - { 0xC649, 552 }, - { 0xC64A, 553 }, - { 0xC64B, 554 }, - { 0xC659, 107 }, - { 0xC65B, 92 }, - { 0xC65D, 108 }, - { 0xC65E, 109 }, - { 0xC65F, 110 }, - { 0xC660, 88 }, - { 0xC661, 105 }, - { 0xC662, 90 }, - { 0xC663, 535 }, - { 0xC664, 538 }, - { 0xC665, 540 }, - { 0xC666, 543 }, - { 0xC667, 544 }, - { 0xC668, 546 }, - { 0xC681, 278 }, - { 0xC684, 283 }, - { 0xC708, 286 }, - { 0xC800, 8 }, - { 0xC801, 10 }, - { 0xC802, 9 }, - { 0xC807, 14 }, - { 0xD000, 188 }, - { 0xD801, 11 }, - { 0xD807, 15 }, - { 0xDA10, 227 }, - { 0xDA11, 228 }, - { 0xDA15, 730 }, - { 0xDA20, 234 }, - { 0xDA21, 235 }, - { 0xDA28, 236 }, - { 0xDA29, 237 }, - { 0xDCE0, 254 }, - { 0xDCE1, 255 }, - { 0xDCE2, 256 }, - { 0xDCE3, 257 }, - { 0xDCE4, 102 }, - { 0xDCE5, 258 }, - { 0xDCE6, 5 }, - { 0xDCE7, 6 }, - { 0xDCE8, 259 }, - { 0xDCE9, 260 }, - { 0xDCEA, 261 }, - { 0xDCF0, 262 }, - { 0xDCF3, 265 }, - { 0xDE82, 279 }, - { 0xDE83, 282 }, - { 0xDE90, 679 }, - { 0xDE91, 680 }, - { 0xDE92, 681 }, - { 0xDE93, 682 }, - { 0xDE94, 683 }, - { 0xDE95, 684 }, - { 0xDE98, 693 }, - { 0xDE99, 694 }, - { 0xDEA0, 685 }, - { 0xDEA1, 686 }, - { 0xDEA2, 687 }, - { 0xDEA3, 688 }, - { 0xDEB0, 689 }, - { 0xDEB1, 690 }, - { 0xDEB2, 691 }, - { 0xDEB3, 692 }, - { 0xDEE0, 695 }, - { 0xDEE1, 696 }, - { 0xDEE2, 697 }, - { 0xDEE3, 698 }, - { 0xDEE4, 699 }, - { 0xDEE5, 700 }, - { 0xDEE6, 701 }, - { 0xDEE7, 702 }, - { 0xDEE8, 703 }, - { 0xDEE9, 704 }, - { 0xDEEA, 705 }, - { 0xDEEB, 706 }, - { 0xDEEC, 707 }, - { 0xDEED, 708 }, - { 0xDEEE, 709 }, - { 0xDEEF, 710 }, - { 0xDEF0, 711 }, - { 0xDEF1, 712 }, - { 0xDEF2, 713 }, - { 0xDEF3, 714 }, - { 0xDEF4, 715 }, - { 0xDEF5, 716 }, - { 0xDEF6, 717 }, - { 0xDEF7, 718 }, - { 0xDEF8, 719 }, - { 0xDEF9, 720 }, - { 0xDEFA, 721 }, - { 0xDEFB, 722 }, - { 0xDEFC, 723 }, - { 0xDEFD, 724 }, - { 0xDEFE, 725 }, - { 0xDEFF, 726 }, - { 0xDF00, 284 }, - { 0xDF01, 49 }, - { 0xDF02, 50 }, - { 0xDF10, 288 }, - { 0xDF11, 291 }, - { 0xDF12, 294 }, - { 0xDF18, 297 }, - { 0xDF19, 298 }, - { 0xDF1A, 299 }, - { 0xDF40, 300 }, - { 0xDF41, 301 }, - { 0xDF42, 302 }, - { 0xDF43, 303 }, - { 0xDF44, 304 }, - { 0xDF45, 305 }, - { 0xDF46, 306 }, - { 0xDF47, 307 }, - { 0xDF48, 308 }, - { 0xDF49, 309 }, - { 0xDF4A, 310 }, - { 0xDF4B, 311 }, - { 0xDF4C, 312 }, - { 0xDF4D, 313 }, - { 0xDF4E, 314 }, - { 0xDF4F, 315 }, - { 0xDF50, 316 }, - { 0xDF51, 317 }, - { 0xDF52, 318 }, - { 0xDF53, 319 }, - { 0xDF54, 320 }, - { 0xDF55, 321 }, - { 0xDF56, 322 }, - { 0xDF57, 323 }, - { 0xDF58, 324 }, - { 0xDF59, 325 }, - { 0xDF5A, 326 }, - { 0xDF5B, 327 }, - { 0xDF5C, 328 }, - { 0xDF5D, 329 }, - { 0xDF5E, 330 }, - { 0xDF60, 332 }, - { 0xDF61, 333 }, - { 0xDF62, 334 }, - { 0xDF63, 335 }, - { 0xDF64, 336 }, - { 0xDF65, 337 }, - { 0xDF66, 338 }, - { 0xDF67, 339 }, - { 0xDF68, 340 }, - { 0xDF69, 341 }, - { 0xDF6A, 342 }, - { 0xDF6B, 343 }, - { 0xDF6C, 344 }, - { 0xDF6D, 345 }, - { 0xDF6E, 346 }, - { 0xDF6F, 347 }, - { 0xDF70, 348 }, - { 0xDF71, 349 }, - { 0xDF72, 350 }, - { 0xDF73, 351 }, - { 0xDF74, 352 }, - { 0xDF75, 353 }, - { 0xDF76, 354 }, - { 0xDF77, 355 }, - { 0xDF78, 356 }, - { 0xDF79, 357 }, - { 0xDF7A, 358 }, - { 0xDF7B, 359 }, - { 0xDF7C, 360 }, - { 0xDF7D, 361 }, - { 0xDF7E, 362 }, - { 0xDF7F, 331 }, - { 0xE000, 189 }, - { 0xE005, 190 }, - { 0xE080, 193 }, - { 0xE081, 196 }, - { 0xE088, 198 }, - { 0xE089, 200 }, - { 0xE08A, 202 }, - { 0xE08B, 204 }, - { 0xE08F, 205 }, - { 0xE090, 733 }, - { 0xE091, 728 }, - { 0xE099, 656 }, - { 0xE100, 208 }, - { 0xE101, 588 }, - { 0xE102, 212 }, - { 0xE108, 214 }, - { 0xE10A, 215 }, - { 0xE110, 731 }, - { 0xE130, 649 }, - { 0xE132, 648 }, - { 0xE180, 216 }, - { 0xE200, 218 }, - { 0xE201, 221 }, - { 0xE208, 224 }, - { 0xE218, 230 }, - { 0xE219, 231 }, - { 0xE21A, 232 }, - { 0xE21B, 233 }, - { 0xE281, 238 }, - { 0xE288, 240 }, - { 0xE289, 243 }, - { 0xE290, 246 }, - { 0xE293, 637 }, - { 0xE298, 248 }, - { 0xE300, 250 }, - { 0xE304, 252 }, - { 0xE4C8, 620 }, - { 0xE510, 267 }, - { 0xE518, 270 }, - { 0xE520, 668 }, - { 0xE521, 669 }, - { 0xE528, 665 }, - { 0xE530, 670 }, - { 0xE531, 671 }, - { 0xE532, 672 }, - { 0xE533, 673 }, - { 0xE534, 674 }, - { 0xE535, 675 }, - { 0xE536, 676 }, - { 0xE537, 677 }, - { 0xE600, 273 }, - { 0xE601, 46 }, - { 0xE602, 276 }, - { 0xE609, 636 }, - { 0xE640, 555 }, - { 0xE641, 556 }, - { 0xE642, 557 }, - { 0xE643, 558 }, - { 0xE648, 559 }, - { 0xE649, 560 }, - { 0xE64A, 561 }, - { 0xE64B, 562 }, - { 0xE64C, 566 }, - { 0xE64D, 541 }, - { 0xE658, 563 }, - { 0xE659, 93 }, - { 0xE65A, 564 }, - { 0xE65B, 94 }, - { 0xE65D, 95 }, - { 0xE65F, 565 }, - { 0xE660, 567 }, - { 0xE661, 568 }, - { 0xE662, 569 }, - { 0xE663, 570 }, - { 0xE664, 571 }, - { 0xE665, 572 }, - { 0xE666, 573 }, - { 0xE667, 574 }, - { 0xE668, 575 }, - { 0xE669, 576 }, - { 0xE66A, 577 }, - { 0xE66B, 578 }, - { 0xE66C, 579 }, - { 0xE66D, 580 }, - { 0xE66E, 581 }, - { 0xE66F, 582 }, - { 0xE681, 589 }, - { 0xE682, 280 }, - { 0xE703, 285 }, - { 0xE708, 287 }, - { 0xE710, 289 }, - { 0xE711, 292 }, - { 0xE712, 295 }, - { 0xE718, 590 }, - { 0xE719, 592 }, - { 0xE71A, 591 }, - { 0xE720, 650 }, - { 0xE721, 652 }, - { 0xE722, 651 }, - { 0xE728, 653 }, - { 0xE729, 655 }, - { 0xE72A, 654 }, - { 0xE880, 593 }, - { 0xE882, 594 }, - { 0xE890, 735 }, - { 0xE891, 729 }, - { 0xE900, 595 }, - { 0xE901, 596 }, - { 0xE902, 597 }, - { 0xEA00, 613 }, - { 0xEA01, 614 }, - { 0xEA88, 598 }, - { 0xEA89, 599 }, - { 0xEA90, 600 }, - { 0xEB00, 601 }, - { 0xECC8, 621 }, - { 0xED10, 602 }, - { 0xED18, 603 }, - { 0xED28, 667 }, - { 0xEE00, 604 }, - { 0xEE81, 605 }, - { 0xEF08, 606 }, - { 0xEF10, 607 }, - { 0xEF11, 608 }, - { 0xEF12, 609 }, - { 0xEF18, 610 }, - { 0xEF19, 611 }, - { 0xEF1A, 612 }, - { 0xF080, 194 }, - { 0xF081, 197 }, - { 0xF088, 199 }, - { 0xF089, 201 }, - { 0xF08A, 203 }, - { 0xF090, 734 }, - { 0xF099, 206 }, - { 0xF100, 209 }, - { 0xF102, 213 }, - { 0xF200, 219 }, - { 0xF201, 222 }, - { 0xF208, 225 }, - { 0xF288, 241 }, - { 0xF289, 244 }, - { 0xF290, 247 }, - { 0xF300, 251 }, - { 0xF510, 268 }, - { 0xF518, 271 }, - { 0xF528, 666 }, - { 0xF600, 274 }, - { 0xF601, 47 }, - { 0xF602, 277 }, - { 0xF664, 539 }, - { 0xF665, 542 }, - { 0xF667, 545 }, - { 0xF682, 281 }, - { 0xFF10, 290 }, - { 0xFF11, 293 }, - { 0xFF12, 296 }, - { 0xFF90, 736 }, + {0x8002, 111}, {0x8004, 119}, {0x8005, 135}, {0x8006, 151}, {0x8007, 167}, + {0x800C, 120}, {0x800D, 136}, {0x800E, 152}, {0x800F, 168}, {0x8010, 114}, + {0x8012, 115}, {0x8014, 121}, {0x8015, 137}, {0x8016, 153}, {0x8017, 169}, + {0x801A, 112}, {0x801C, 122}, {0x801D, 138}, {0x801E, 154}, {0x801F, 170}, + {0x8024, 123}, {0x8025, 139}, {0x8026, 155}, {0x8027, 171}, {0x802C, 124}, + {0x802D, 140}, {0x802E, 156}, {0x802F, 172}, {0x8032, 117}, {0x8034, 125}, + {0x8035, 141}, {0x8036, 157}, {0x8037, 173}, {0x803C, 126}, {0x803D, 142}, + {0x803E, 158}, {0x803F, 174}, {0x8044, 127}, {0x8045, 143}, {0x8046, 159}, + {0x8047, 175}, {0x804C, 128}, {0x804D, 144}, {0x804E, 160}, {0x804F, 176}, + {0x8054, 129}, {0x8055, 145}, {0x8056, 161}, {0x8057, 177}, {0x805C, 130}, + {0x805D, 146}, {0x805E, 162}, {0x805F, 178}, {0x8064, 131}, {0x8065, 147}, + {0x8066, 163}, {0x8067, 179}, {0x806C, 132}, {0x806D, 148}, {0x806E, 164}, + {0x806F, 180}, {0x8074, 133}, {0x8075, 149}, {0x8076, 165}, {0x8077, 181}, + {0x807C, 134}, {0x807D, 150}, {0x807E, 166}, {0x807F, 182}, {0x8080, 2}, + {0x8084, 101}, {0x808C, 3}, {0x809C, 184}, {0x80A4, 185}, {0x83C6, 186}, + {0x83CE, 187}, {0x83F6, 4}, {0x8801, 374}, {0x8802, 376}, {0x8804, 383}, + {0x8805, 389}, {0x8806, 53}, {0x8807, 401}, {0x8808, 363}, {0x8809, 375}, + {0x880A, 377}, {0x880C, 384}, {0x880D, 390}, {0x880E, 54}, {0x880F, 402}, + {0x8810, 364}, {0x8812, 378}, {0x8814, 385}, {0x8815, 391}, {0x8816, 55}, + {0x8817, 403}, {0x8818, 52}, {0x881A, 379}, {0x881D, 392}, {0x881E, 56}, + {0x881F, 404}, {0x8820, 365}, {0x8825, 393}, {0x8826, 57}, {0x8827, 405}, + {0x882D, 394}, {0x882E, 58}, {0x882F, 406}, {0x8830, 366}, {0x8834, 386}, + {0x8835, 395}, {0x8837, 407}, {0x883C, 387}, {0x883D, 396}, {0x883F, 408}, + {0x8840, 367}, {0x8842, 380}, {0x8844, 388}, {0x8845, 397}, {0x8847, 59}, + {0x8848, 368}, {0x884A, 381}, {0x884D, 398}, {0x884F, 60}, {0x8852, 382}, + {0x8855, 399}, {0x8857, 61}, {0x8858, 369}, {0x885D, 400}, {0x885F, 62}, + {0x8860, 370}, {0x8867, 63}, {0x8868, 371}, {0x886F, 64}, {0x8870, 372}, + {0x8877, 65}, {0x8878, 373}, {0x887F, 66}, {0x8881, 423}, {0x8882, 439}, + {0x8883, 455}, {0x8884, 103}, {0x8889, 424}, {0x888A, 440}, {0x888B, 456}, + {0x888C, 67}, {0x8890, 409}, {0x8891, 425}, {0x8892, 441}, {0x8893, 457}, + {0x8898, 410}, {0x8899, 426}, {0x889A, 442}, {0x889B, 458}, {0x88A0, 411}, + {0x88A1, 427}, {0x88A2, 443}, {0x88A3, 459}, {0x88A4, 463}, {0x88A8, 412}, + {0x88A9, 428}, {0x88AA, 444}, {0x88AB, 460}, {0x88AC, 68}, {0x88B0, 413}, + {0x88B1, 429}, {0x88B2, 445}, {0x88B3, 461}, {0x88B8, 414}, {0x88B9, 430}, + {0x88BA, 446}, {0x88BB, 462}, {0x88C0, 415}, {0x88C1, 431}, {0x88C2, 447}, + {0x88C8, 416}, {0x88C9, 432}, {0x88CA, 448}, {0x88D0, 417}, {0x88D1, 433}, + {0x88D2, 449}, {0x88D8, 418}, {0x88D9, 434}, {0x88DA, 450}, {0x88E0, 419}, + {0x88E1, 435}, {0x88E2, 451}, {0x88E8, 420}, {0x88E9, 436}, {0x88EA, 452}, + {0x88F0, 421}, {0x88F1, 437}, {0x88F2, 453}, {0x88F8, 422}, {0x88F9, 438}, + {0x88FA, 454}, {0x8900, 464}, {0x8901, 472}, {0x8902, 480}, {0x8903, 488}, + {0x8904, 496}, {0x8905, 500}, {0x8906, 504}, {0x8907, 508}, {0x8910, 465}, + {0x8911, 473}, {0x8912, 481}, {0x8913, 489}, {0x8920, 466}, {0x8921, 474}, + {0x8922, 482}, {0x8923, 490}, {0x8924, 497}, {0x8925, 501}, {0x8926, 505}, + {0x8927, 509}, {0x8930, 467}, {0x8931, 475}, {0x8932, 483}, {0x8933, 491}, + {0x8940, 468}, {0x8941, 476}, {0x8942, 484}, {0x8943, 492}, {0x8944, 498}, + {0x8945, 502}, {0x8946, 506}, {0x8947, 510}, {0x8950, 469}, {0x8951, 477}, + {0x8952, 485}, {0x8953, 493}, {0x8960, 470}, {0x8961, 478}, {0x8962, 486}, + {0x8963, 494}, {0x8964, 499}, {0x8965, 503}, {0x8966, 507}, {0x8967, 511}, + {0x8970, 471}, {0x8971, 479}, {0x8972, 487}, {0x8973, 495}, {0x8980, 512}, + {0x8981, 520}, {0x8982, 528}, {0x898A, 529}, {0x8990, 513}, {0x8991, 521}, + {0x8992, 530}, {0x899A, 531}, {0x89A0, 514}, {0x89A1, 522}, {0x89B0, 515}, + {0x89B1, 523}, {0x89C0, 516}, {0x89C1, 524}, {0x89D0, 517}, {0x89D1, 525}, + {0x89E0, 518}, {0x89E1, 526}, {0x89F0, 519}, {0x89F1, 527}, {0x8B84, 532}, + {0x8B97, 74}, {0x8B9F, 75}, {0x8BA7, 76}, {0x8BAF, 77}, {0x8BB7, 78}, + {0x8BBF, 79}, {0x8BC6, 533}, {0x8BC7, 80}, {0x8BCE, 534}, {0x8BCF, 81}, + {0x8BD6, 69}, {0x8BD7, 82}, {0x8BDE, 70}, {0x8BDF, 83}, {0x8BE6, 104}, + {0x8BE7, 84}, {0x8BEE, 71}, {0x8BEF, 85}, {0x8BF6, 72}, {0x8BF7, 86}, + {0x8BFE, 73}, {0x8BFF, 87}, {0x9000, 113}, {0x9080, 183}, {0x9808, 0}, + {0x9820, 116}, {0x9828, 1}, {0x9828, 100}, {0xA038, 118}, {0xC000, 7}, + {0xC005, 12}, {0xC006, 13}, {0xC008, 16}, {0xC009, 17}, {0xC00A, 18}, + {0xC00B, 19}, {0xC00C, 20}, {0xC00D, 21}, {0xC00E, 22}, {0xC00F, 23}, + {0xC010, 24}, {0xC011, 25}, {0xC012, 26}, {0xC013, 27}, {0xC014, 28}, + {0xC015, 29}, {0xC016, 51}, {0xC017, 30}, {0xC018, 42}, {0xC019, 43}, + {0xC01A, 44}, {0xC020, 31}, {0xC021, 32}, {0xC024, 96}, {0xC028, 33}, + {0xC029, 34}, {0xC02C, 35}, {0xC02D, 36}, {0xC030, 37}, {0xC031, 38}, + {0xC038, 39}, {0xC039, 40}, {0xC03A, 41}, {0xC080, 192}, {0xC081, 195}, + {0xC082, 191}, {0xC090, 732}, {0xC091, 727}, {0xC100, 207}, {0xC101, 210}, + {0xC102, 211}, {0xC108, 638}, {0xC109, 639}, {0xC10A, 640}, {0xC10B, 641}, + {0xC110, 642}, {0xC111, 643}, {0xC112, 644}, {0xC113, 645}, {0xC118, 646}, + {0xC119, 647}, {0xC200, 217}, {0xC201, 220}, {0xC208, 223}, {0xC210, 226}, + {0xC212, 229}, {0xC213, 583}, {0xC214, 615}, {0xC230, 537}, {0xC288, 239}, + {0xC289, 242}, {0xC290, 245}, {0xC298, 98}, {0xC299, 629}, {0xC2A0, 99}, + {0xC2A1, 630}, {0xC2A2, 631}, {0xC2A3, 632}, {0xC2A4, 662}, {0xC2A5, 657}, + {0xC2A6, 658}, {0xC2A8, 633}, {0xC2A9, 634}, {0xC2AA, 660}, {0xC2AB, 661}, + {0xC2AF, 659}, {0xC300, 249}, {0xC3A0, 253}, {0xC4C8, 622}, {0xC4CA, 623}, + {0xC4CB, 624}, {0xC4CC, 625}, {0xC4CD, 626}, {0xC4CE, 627}, {0xC4CF, 628}, + {0xC4D0, 616}, {0xC4D1, 617}, {0xC4D3, 618}, {0xC4D7, 619}, {0xC4F1, 263}, + {0xC4F2, 264}, {0xC510, 266}, {0xC518, 269}, {0xC520, 584}, {0xC521, 585}, + {0xC522, 586}, {0xC523, 587}, {0xC524, 678}, {0xC527, 97}, {0xC528, 664}, + {0xC529, 663}, {0xC600, 272}, {0xC601, 45}, {0xC602, 275}, {0xC608, 48}, + {0xC609, 635}, {0xC640, 89}, {0xC641, 106}, {0xC642, 91}, {0xC643, 536}, + {0xC644, 547}, {0xC645, 548}, {0xC646, 549}, {0xC647, 550}, {0xC648, 551}, + {0xC649, 552}, {0xC64A, 553}, {0xC64B, 554}, {0xC659, 107}, {0xC65B, 92}, + {0xC65D, 108}, {0xC65E, 109}, {0xC65F, 110}, {0xC660, 88}, {0xC661, 105}, + {0xC662, 90}, {0xC663, 535}, {0xC664, 538}, {0xC665, 540}, {0xC666, 543}, + {0xC667, 544}, {0xC668, 546}, {0xC681, 278}, {0xC684, 283}, {0xC708, 286}, + {0xC800, 8}, {0xC801, 10}, {0xC802, 9}, {0xC807, 14}, {0xD000, 188}, + {0xD801, 11}, {0xD807, 15}, {0xDA10, 227}, {0xDA11, 228}, {0xDA15, 730}, + {0xDA20, 234}, {0xDA21, 235}, {0xDA28, 236}, {0xDA29, 237}, {0xDCE0, 254}, + {0xDCE1, 255}, {0xDCE2, 256}, {0xDCE3, 257}, {0xDCE4, 102}, {0xDCE5, 258}, + {0xDCE6, 5}, {0xDCE7, 6}, {0xDCE8, 259}, {0xDCE9, 260}, {0xDCEA, 261}, + {0xDCF0, 262}, {0xDCF3, 265}, {0xDE82, 279}, {0xDE83, 282}, {0xDE90, 679}, + {0xDE91, 680}, {0xDE92, 681}, {0xDE93, 682}, {0xDE94, 683}, {0xDE95, 684}, + {0xDE98, 693}, {0xDE99, 694}, {0xDEA0, 685}, {0xDEA1, 686}, {0xDEA2, 687}, + {0xDEA3, 688}, {0xDEB0, 689}, {0xDEB1, 690}, {0xDEB2, 691}, {0xDEB3, 692}, + {0xDEE0, 695}, {0xDEE1, 696}, {0xDEE2, 697}, {0xDEE3, 698}, {0xDEE4, 699}, + {0xDEE5, 700}, {0xDEE6, 701}, {0xDEE7, 702}, {0xDEE8, 703}, {0xDEE9, 704}, + {0xDEEA, 705}, {0xDEEB, 706}, {0xDEEC, 707}, {0xDEED, 708}, {0xDEEE, 709}, + {0xDEEF, 710}, {0xDEF0, 711}, {0xDEF1, 712}, {0xDEF2, 713}, {0xDEF3, 714}, + {0xDEF4, 715}, {0xDEF5, 716}, {0xDEF6, 717}, {0xDEF7, 718}, {0xDEF8, 719}, + {0xDEF9, 720}, {0xDEFA, 721}, {0xDEFB, 722}, {0xDEFC, 723}, {0xDEFD, 724}, + {0xDEFE, 725}, {0xDEFF, 726}, {0xDF00, 284}, {0xDF01, 49}, {0xDF02, 50}, + {0xDF10, 288}, {0xDF11, 291}, {0xDF12, 294}, {0xDF18, 297}, {0xDF19, 298}, + {0xDF1A, 299}, {0xDF40, 300}, {0xDF41, 301}, {0xDF42, 302}, {0xDF43, 303}, + {0xDF44, 304}, {0xDF45, 305}, {0xDF46, 306}, {0xDF47, 307}, {0xDF48, 308}, + {0xDF49, 309}, {0xDF4A, 310}, {0xDF4B, 311}, {0xDF4C, 312}, {0xDF4D, 313}, + {0xDF4E, 314}, {0xDF4F, 315}, {0xDF50, 316}, {0xDF51, 317}, {0xDF52, 318}, + {0xDF53, 319}, {0xDF54, 320}, {0xDF55, 321}, {0xDF56, 322}, {0xDF57, 323}, + {0xDF58, 324}, {0xDF59, 325}, {0xDF5A, 326}, {0xDF5B, 327}, {0xDF5C, 328}, + {0xDF5D, 329}, {0xDF5E, 330}, {0xDF60, 332}, {0xDF61, 333}, {0xDF62, 334}, + {0xDF63, 335}, {0xDF64, 336}, {0xDF65, 337}, {0xDF66, 338}, {0xDF67, 339}, + {0xDF68, 340}, {0xDF69, 341}, {0xDF6A, 342}, {0xDF6B, 343}, {0xDF6C, 344}, + {0xDF6D, 345}, {0xDF6E, 346}, {0xDF6F, 347}, {0xDF70, 348}, {0xDF71, 349}, + {0xDF72, 350}, {0xDF73, 351}, {0xDF74, 352}, {0xDF75, 353}, {0xDF76, 354}, + {0xDF77, 355}, {0xDF78, 356}, {0xDF79, 357}, {0xDF7A, 358}, {0xDF7B, 359}, + {0xDF7C, 360}, {0xDF7D, 361}, {0xDF7E, 362}, {0xDF7F, 331}, {0xE000, 189}, + {0xE005, 190}, {0xE080, 193}, {0xE081, 196}, {0xE088, 198}, {0xE089, 200}, + {0xE08A, 202}, {0xE08B, 204}, {0xE08F, 205}, {0xE090, 733}, {0xE091, 728}, + {0xE099, 656}, {0xE100, 208}, {0xE101, 588}, {0xE102, 212}, {0xE108, 214}, + {0xE10A, 215}, {0xE110, 731}, {0xE130, 649}, {0xE132, 648}, {0xE180, 216}, + {0xE200, 218}, {0xE201, 221}, {0xE208, 224}, {0xE218, 230}, {0xE219, 231}, + {0xE21A, 232}, {0xE21B, 233}, {0xE281, 238}, {0xE288, 240}, {0xE289, 243}, + {0xE290, 246}, {0xE293, 637}, {0xE298, 248}, {0xE300, 250}, {0xE304, 252}, + {0xE4C8, 620}, {0xE510, 267}, {0xE518, 270}, {0xE520, 668}, {0xE521, 669}, + {0xE528, 665}, {0xE530, 670}, {0xE531, 671}, {0xE532, 672}, {0xE533, 673}, + {0xE534, 674}, {0xE535, 675}, {0xE536, 676}, {0xE537, 677}, {0xE600, 273}, + {0xE601, 46}, {0xE602, 276}, {0xE609, 636}, {0xE640, 555}, {0xE641, 556}, + {0xE642, 557}, {0xE643, 558}, {0xE648, 559}, {0xE649, 560}, {0xE64A, 561}, + {0xE64B, 562}, {0xE64C, 566}, {0xE64D, 541}, {0xE658, 563}, {0xE659, 93}, + {0xE65A, 564}, {0xE65B, 94}, {0xE65D, 95}, {0xE65F, 565}, {0xE660, 567}, + {0xE661, 568}, {0xE662, 569}, {0xE663, 570}, {0xE664, 571}, {0xE665, 572}, + {0xE666, 573}, {0xE667, 574}, {0xE668, 575}, {0xE669, 576}, {0xE66A, 577}, + {0xE66B, 578}, {0xE66C, 579}, {0xE66D, 580}, {0xE66E, 581}, {0xE66F, 582}, + {0xE681, 589}, {0xE682, 280}, {0xE703, 285}, {0xE708, 287}, {0xE710, 289}, + {0xE711, 292}, {0xE712, 295}, {0xE718, 590}, {0xE719, 592}, {0xE71A, 591}, + {0xE720, 650}, {0xE721, 652}, {0xE722, 651}, {0xE728, 653}, {0xE729, 655}, + {0xE72A, 654}, {0xE880, 593}, {0xE882, 594}, {0xE890, 735}, {0xE891, 729}, + {0xE900, 595}, {0xE901, 596}, {0xE902, 597}, {0xEA00, 613}, {0xEA01, 614}, + {0xEA88, 598}, {0xEA89, 599}, {0xEA90, 600}, {0xEB00, 601}, {0xECC8, 621}, + {0xED10, 602}, {0xED18, 603}, {0xED28, 667}, {0xEE00, 604}, {0xEE81, 605}, + {0xEF08, 606}, {0xEF10, 607}, {0xEF11, 608}, {0xEF12, 609}, {0xEF18, 610}, + {0xEF19, 611}, {0xEF1A, 612}, {0xF080, 194}, {0xF081, 197}, {0xF088, 199}, + {0xF089, 201}, {0xF08A, 203}, {0xF090, 734}, {0xF099, 206}, {0xF100, 209}, + {0xF102, 213}, {0xF200, 219}, {0xF201, 222}, {0xF208, 225}, {0xF288, 241}, + {0xF289, 244}, {0xF290, 247}, {0xF300, 251}, {0xF510, 268}, {0xF518, 271}, + {0xF528, 666}, {0xF600, 274}, {0xF601, 47}, {0xF602, 277}, {0xF664, 539}, + {0xF665, 542}, {0xF667, 545}, {0xF682, 281}, {0xFF10, 290}, {0xFF11, 293}, + {0xFF12, 296}, {0xFF90, 736}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -1948,24 +1233,18 @@ const SysReg *lookupSysRegByEncoding(uint16_t Encoding) } static const PState PStatesList[] = { - { "spsel", 0x5 }, // 0 - { "daifset", 0x1E }, // 1 - { "daifclr", 0x1F }, // 2 - { "pan", 0x4 }, // 3 - { "uao", 0x3 }, // 4 - { "dit", 0x1A }, // 5 + {"spsel", 0x5}, // 0 + {"daifset", 0x1E}, // 1 + {"daifclr", 0x1F}, // 2 + {"pan", 0x4}, // 3 + {"uao", 0x3}, // 4 + {"dit", 0x1A}, // 5 }; -const PState *lookupPStateByEncoding(uint16_t Encoding) -{ +const PState *lookupPStateByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x3, 4 }, - { 0x4, 3 }, - { 0x5, 0 }, - { 0x1A, 5 }, - { 0x1E, 1 }, - { 0x1F, 2 }, + {0x3, 4}, {0x4, 3}, {0x5, 0}, {0x1A, 5}, {0x1E, 1}, {0x1F, 2}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -1976,46 +1255,31 @@ const PState *lookupPStateByEncoding(uint16_t Encoding) } static const SVEPREDPAT SVEPREDPATsList[] = { - { "pow2", 0x0 }, // 0 - { "vl1", 0x1 }, // 1 - { "vl2", 0x2 }, // 2 - { "vl3", 0x3 }, // 3 - { "vl4", 0x4 }, // 4 - { "vl5", 0x5 }, // 5 - { "vl6", 0x6 }, // 6 - { "vl7", 0x7 }, // 7 - { "vl8", 0x8 }, // 8 - { "vl16", 0x9 }, // 9 - { "vl32", 0xa }, // 10 - { "vl64", 0xb }, // 11 - { "vl128", 0xc }, // 12 - { "vl256", 0xd }, // 13 - { "mul4", 0x1d }, // 14 - { "mul3", 0x1e }, // 15 - { "all", 0x1f }, // 16 + {"pow2", 0x0}, // 0 + {"vl1", 0x1}, // 1 + {"vl2", 0x2}, // 2 + {"vl3", 0x3}, // 3 + {"vl4", 0x4}, // 4 + {"vl5", 0x5}, // 5 + {"vl6", 0x6}, // 6 + {"vl7", 0x7}, // 7 + {"vl8", 0x8}, // 8 + {"vl16", 0x9}, // 9 + {"vl32", 0xa}, // 10 + {"vl64", 0xb}, // 11 + {"vl128", 0xc}, // 12 + {"vl256", 0xd}, // 13 + {"mul4", 0x1d}, // 14 + {"mul3", 0x1e}, // 15 + {"all", 0x1f}, // 16 }; -const SVEPREDPAT *lookupSVEPREDPATByEncoding(uint16_t Encoding) -{ +const SVEPREDPAT *lookupSVEPREDPATByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x0, 0 }, - { 0x1, 1 }, - { 0x2, 2 }, - { 0x3, 3 }, - { 0x4, 4 }, - { 0x5, 5 }, - { 0x6, 6 }, - { 0x7, 7 }, - { 0x8, 8 }, - { 0x9, 9 }, - { 0xA, 10 }, - { 0xB, 11 }, - { 0xC, 12 }, - { 0xD, 13 }, - { 0x1D, 14 }, - { 0x1E, 15 }, - { 0x1F, 16 }, + {0x0, 0}, {0x1, 1}, {0x2, 2}, {0x3, 3}, {0x4, 4}, {0x5, 5}, + {0x6, 6}, {0x7, 7}, {0x8, 8}, {0x9, 9}, {0xA, 10}, {0xB, 11}, + {0xC, 12}, {0xD, 13}, {0x1D, 14}, {0x1E, 15}, {0x1F, 16}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); @@ -2026,19 +1290,18 @@ const SVEPREDPAT *lookupSVEPREDPATByEncoding(uint16_t Encoding) } static const ExactFPImm ExactFPImmsList[] = { - { "zero", 0x0, "0.0" }, // 0 - { "half", 0x1, "0.5" }, // 1 - { "one", 0x2, "1.0" }, // 2 - { "two", 0x3, "2.0" }, // 3 + {"zero", 0x0, "0.0"}, // 0 + {"half", 0x1, "0.5"}, // 1 + {"one", 0x2, "1.0"}, // 2 + {"two", 0x3, "2.0"}, // 3 }; -const ExactFPImm *lookupExactFPImmByEnum(uint16_t Encoding) -{ +const ExactFPImm *lookupExactFPImmByEnum(uint16_t Encoding) { static const struct IndexType Index[] = { - { 0x0, 0 }, - { 0x1, 1 }, - { 0x2, 2 }, - { 0x3, 3 }, + {0x0, 0}, + {0x1, 1}, + {0x2, 2}, + {0x3, 3}, }; if (Encoding >= ARR_SIZE(ExactFPImmsList)) @@ -2046,4 +1309,3 @@ const ExactFPImm *lookupExactFPImmByEnum(uint16_t Encoding) else return &ExactFPImmsList[Index[Encoding].index]; } - diff --git a/arch/AArch64/AArch64GenSystemOperands_enum.inc b/arch/AArch64/AArch64GenSystemOperands_enum.inc index 400022637f..1d57665b62 100644 --- a/arch/AArch64/AArch64GenSystemOperands_enum.inc +++ b/arch/AArch64/AArch64GenSystemOperands_enum.inc @@ -16,4 +16,3 @@ enum ExactFPImmValues { AArch64ExactFPImm_one = 2, AArch64ExactFPImm_two = 3, }; - diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 31d31b5733..5f3e72dc20 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -20,2431 +20,3156 @@ #include #include -#include "AArch64InstPrinter.h" -#include "AArch64Disassembler.h" -#include "AArch64BaseInfo.h" -#include "../../utils.h" #include "../../MCInst.h" -#include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" +#include "../../SStream.h" +#include "../../utils.h" +#include "../MCInstPrinter.h" +#include "AArch64BaseInfo.h" +#include "AArch64Disassembler.h" +#include "AArch64InstPrinter.h" -#include "AArch64Mapping.h" #include "AArch64AddressingModes.h" - -#define GET_REGINFO_ENUM -#include "AArch64GenRegisterInfo.inc" +#include "AArch64Mapping.h" +// +//#define GET_REGINFO_ENUM +//#include "AArch64GenRegisterInfo.inc" #define GET_INSTRINFO_ENUM -#include "AArch64GenInstrInfo.inc" -#include "AArch64GenSubtargetInfo.inc" +#include "AArch64GenDisassemblerTables.inc" +//#include "AArch64GenSubtargetInfo.inc" static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); + static void printOperand(MCInst *MI, unsigned OpNum, SStream *O); + static bool printSysAlias(MCInst *MI, SStream *O); -static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI); + +static char *printAliasInstr(MCInst *MI, SStream *OS /*, MCRegisterInfo *MRI*/); + static void printInstruction(MCInst *MI, SStream *O); + static void printShifter(MCInst *MI, unsigned OpNum, SStream *O); -static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, SStream *OS); +static void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); -static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index) -{ -#ifndef CAPSTONE_DIET - const uint8_t *arr = AArch64_get_op_access(h, id); +static void printOperand(MCInst *MI, unsigned OpNum, SStream *O); - if (arr[index] == CS_AC_IGNORE) - return 0; +static void printImm(MCInst *MI, unsigned OpNum, SStream *O); - return arr[index]; -#else - return 0; -#endif -} +static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O); -static void op_addImm(MCInst *MI, int v) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = v; - MI->flat_insn->detail->arm64.op_count++; - } -} +static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O, + unsigned Imm); -static void set_mem_access(MCInst *MI, bool status) -{ - MI->csh->doing_mem = status; +static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O); - if (MI->csh->detail != CS_OPT_ON) - return; +static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O); - if (status) { -#ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0; - } else { - // done, create the next operand slot - MI->flat_insn->detail->arm64.op_count++; - } -} - -void AArch64_printInst(MCInst *MI, SStream *O, void *Info) +static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O); + +static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O); + +static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O); + +static void printShifter(MCInst *MI, unsigned OpNum, SStream *O); + +static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O); + +static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O); + +static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O); + +static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, + unsigned Width, char SrcRegKind, SStream *O); + +static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, + char SrcRegKind, unsigned Width); + +static void printRegWithShiftExtend(MCInst *MI, unsigned OpNum, SStream *O, + bool SignExtend, int ExtWidth, + char SrcRegKind, char Suffix); + +static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O); + +static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O); + +static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale); + +static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, + unsigned Scale); + +#if 0 +static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale) { - // Check for special encodings and print the canonical alias instead. - unsigned Opcode = MCInst_getOpcode(MI); - int LSB, Width; - char *mnem; - - // printf(">>> opcode = %u\n", MCInst_getOpcode(MI)); - - if (Opcode == AArch64_SYSxt && printSysAlias(MI, O)) - return; - - // SBFM/UBFM should print to a nicer aliased form if possible. - if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri || - Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) { - bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri); - bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri); - - MCOperand *Op0 = MCInst_getOperand(MI, 0); - MCOperand *Op1 = MCInst_getOperand(MI, 1); - MCOperand *Op2 = MCInst_getOperand(MI, 2); - MCOperand *Op3 = MCInst_getOperand(MI, 3); - - if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) { - const char *AsmMnemonic = NULL; - - switch (MCOperand_getImm(Op3)) { - default: - break; - - case 7: - if (IsSigned) - AsmMnemonic = "sxtb"; - else if (!Is64Bit) - AsmMnemonic = "uxtb"; - break; - - case 15: - if (IsSigned) - AsmMnemonic = "sxth"; - else if (!Is64Bit) - AsmMnemonic = "uxth"; - break; - - case 31: - // *xtw is only valid for signed 64-bit operations. - if (Is64Bit && IsSigned) - AsmMnemonic = "sxtw"; - break; - } - - if (AsmMnemonic) { - SStream_concat(O, "%s\t%s, %s", AsmMnemonic, - getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), - getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName)); - - if (MI->csh->detail) { -#ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1)); - MI->flat_insn->detail->arm64.op_count++; - } - - MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); - - return; - } - } - - // All immediate shifts are aliases, implemented using the Bitfield - // instruction. In all cases the immediate shift amount shift must be in - // the range 0 to (reg.size -1). - if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) { - const char *AsmMnemonic = NULL; - int shift = 0; - int immr = (int)MCOperand_getImm(Op2); - int imms = (int)MCOperand_getImm(Op3); - - if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { - AsmMnemonic = "lsl"; - shift = 31 - imms; - } else if (Opcode == AArch64_UBFMXri && imms != 0x3f && - ((imms + 1 == immr))) { - AsmMnemonic = "lsl"; - shift = 63 - imms; - } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) { - AsmMnemonic = "lsr"; - shift = immr; - } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) { - AsmMnemonic = "lsr"; - shift = immr; - } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) { - AsmMnemonic = "asr"; - shift = immr; - } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) { - AsmMnemonic = "asr"; - shift = immr; - } - - if (AsmMnemonic) { - SStream_concat(O, "%s\t%s, %s, ", AsmMnemonic, - getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), - getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); - - printInt32Bang(O, shift); - - MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); - - if (MI->csh->detail) { -#ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + MCOperand *MO = MCInst_getOperand(MI, OpNum + 1); + + SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); + + if (MCOperand_isImm(MO)) { + int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + printInt64Bang(O, val); + // } else { + // // assert(MO1.isExpr() && "Unexpected operand type!"); + // SStream_concat0(O, ", "); + // MO1.getExpr()->print(O, &MAI); + } + + SStream_concat0(O, "]"); +} #endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift; - MI->flat_insn->detail->arm64.op_count++; - } - return; - } - } +// IsSVEPrefetch = false +static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, + bool IsSVEPrefetch); - // SBFIZ/UBFIZ aliases - if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) { - SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"), - getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), - getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); +static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O); - printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2))); +static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O); - SStream_concat0(O, ", "); +// static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) +static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride); - printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1); +static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, + unsigned int size); - MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz")); +static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, + char *LayoutSuffix, MCRegisterInfo *MRI, + arm64_vas vas); - if (MI->csh->detail) { -#ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1; - MI->flat_insn->detail->arm64.op_count++; - } +static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, + unsigned NumLanes, char LaneKind); - return; - } +static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O); - // Otherwise SBFX/UBFX is the preferred form - SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"), - getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), - getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); +static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O); - printInt32Bang(O, (int)MCOperand_getImm(Op2)); - SStream_concat0(O, ", "); - printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1); +static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O); - MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx")); +static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O); - if (MI->csh->detail) { -#ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1; - MI->flat_insn->detail->arm64.op_count++; - } - - return; - } - - if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) { - MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0 - MCOperand *Op2 = MCInst_getOperand(MI, 2); - int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3)); - int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4)); - - if ((MCOperand_getReg(Op2) == AArch64_WZR || MCOperand_getReg(Op2) == AArch64_XZR) && - (ImmR == 0 || ImmS < ImmR)) { - // BFC takes precedence over its entire range, sligtly differently to BFI. - int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; - int LSB = (BitWidth - ImmR) % BitWidth; - int Width = ImmS + 1; - - SStream_concat(O, "bfc\t%s, ", - getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName)); - - printInt32Bang(O, LSB); - SStream_concat0(O, ", "); - printInt32Bang(O, Width); - MCInst_setOpcodePub(MI, AArch64_map_insn("bfc")); - - if (MI->csh->detail) { -#ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); - MI->flat_insn->detail->arm64.op_count++; +static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O); -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; - MI->flat_insn->detail->arm64.op_count++; - } +static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O); - return; - } else if (ImmS < ImmR) { - // BFI alias - int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; - LSB = (BitWidth - ImmR) % BitWidth; - Width = ImmS + 1; +static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O); - SStream_concat(O, "bfi\t%s, %s, ", - getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), - getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); +static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O); - printInt32Bang(O, LSB); - SStream_concat0(O, ", "); - printInt32Bang(O, Width); +static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, + int64_t Angle, int64_t Remainder); - MCInst_setOpcodePub(MI, AArch64_map_insn("bfi")); +static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O); - if (MI->csh->detail) { -#ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); - MI->flat_insn->detail->arm64.op_count++; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; - MI->flat_insn->detail->arm64.op_count++; +// default suffix = 0 +static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix); + +static void printImmSVE16(int16_t Val, SStream *O); + +static void printImmSVE32(int32_t Val, SStream *O); + +static void printImmSVE64(int64_t Val, SStream *O); + +static void printImm8OptLsl32(MCInst *MI, unsigned OpNum, SStream *O); + +static void printImm8OptLsl64(MCInst *MI, unsigned OpNum, SStream *O); + +static void printSVELogicalImm16(MCInst *MI, unsigned OpNum, SStream *O); + +static void printSVELogicalImm32(MCInst *MI, unsigned OpNum, SStream *O); + +static void printSVELogicalImm64(MCInst *MI, unsigned OpNum, SStream *O); + +static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width); + +static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, + unsigned ImmIs0, unsigned ImmIs1); + +static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O); + +// Starting point of new print functions + +static void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O); + +static void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O); + +static void printSImm(MCInst *MI, unsigned OpNum, SStream *O, int Size); + +static void printUnsignedImm(MCInst *MI, unsigned OpNum, SStream *O); + +static void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O); + +static void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O); + +static void printMatrixTileVector(MCInst *MI, unsigned OpNum, SStream *O, + bool IsVertical); + +static void printMatrixIndex(MCInst *MI, unsigned OpNum, SStream *O); + +static void printMatrix(MCInst *MI, unsigned OpNum, SStream *O, int EltSize); + +static void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O); + +static void printSVCROp(const MCInst *MI, unsigned OpNum, SStream *O); + +#define GET_INSTRINFO_ENUM +#define GET_REGINFO_ENUM +#define GET_ASM_WRITER +#define GET_REGINFO_EXTRA +#define PRINT_ALIAS_INSTR + +#include "AArch64GenDisassemblerTables.inc" + +#include "../../sync/logger.h" + +static cs_ac_type get_op_access(cs_struct *h, unsigned int id, + unsigned int index) { #ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + const uint8_t *arr = AArch64_get_op_access(h, id); + + if (!arr) + return 0; + + if (arr[index] == CS_AC_IGNORE) + return 0; + + return arr[index]; +#else + return 0; #endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; - MI->flat_insn->detail->arm64.op_count++; - } +} - return; - } +static void op_addImm(MCInst *MI, int v) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .imm = v; + MI->flat_insn->detail->arm64.op_count++; + } +} - LSB = ImmR; - Width = ImmS - ImmR + 1; - // Otherwise BFXIL the preferred form - SStream_concat(O, "bfxil\t%s, %s, ", - getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), - getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); +static void set_mem_access(MCInst *MI, bool status) { + MI->csh->doing_mem = status; - printInt32Bang(O, LSB); - SStream_concat0(O, ", "); - printInt32Bang(O, Width); + if (MI->csh->detail != CS_OPT_ON) + return; - MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil")); + if (status) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_MEM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .mem.base = ARM64_REG_INVALID; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .mem.index = ARM64_REG_INVALID; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .mem.disp = 0; + } else { + // done, create the next operand slot + MI->flat_insn->detail->arm64.op_count++; + } +} - if (MI->csh->detail) { +void AArch64_printInst(MCInst *MI, SStream *O, void *Info) { + MRI = Info; + // Check for special encodings and print the canonical alias instead. + unsigned Opcode = MCInst_getOpcode(MI); + int LSB, Width; + char *mnem; + + // printf(">>> opcode = %u\n", MCInst_getOpcode(MI)); + + if (Opcode == AArch64_SYSxt && printSysAlias(MI, O)) + return; + + // SBFM/UBFM should print to a nicer aliased form if possible. + if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri || + Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) { + bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri); + bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri); + + MCOperand *Op0 = MCInst_getOperand(MI, 0); + MCOperand *Op1 = MCInst_getOperand(MI, 1); + MCOperand *Op2 = MCInst_getOperand(MI, 2); + MCOperand *Op3 = MCInst_getOperand(MI, 3); + + if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && + MCOperand_isImm(Op3)) { + const char *AsmMnemonic = NULL; + + switch (MCOperand_getImm(Op3)) { + default: + break; + + case 7: + if (IsSigned) + AsmMnemonic = "sxtb"; + else if (!Is64Bit) + AsmMnemonic = "uxtb"; + break; + + case 15: + if (IsSigned) + AsmMnemonic = "sxth"; + else if (!Is64Bit) + AsmMnemonic = "uxth"; + break; + + case 31: + // *xtw is only valid for signed 64-bit operations. + if (Is64Bit && IsSigned) + AsmMnemonic = "sxtw"; + break; + } + + if (AsmMnemonic) { + SStream_concat( + O, "%s\t%s, %s", AsmMnemonic, + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), + AArch64_NoRegAltName)); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); - MI->flat_insn->detail->arm64.op_count++; + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); - MI->flat_insn->detail->arm64.op_count++; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = getWRegFromXReg(MCOperand_getReg(Op1)); + MI->flat_insn->detail->arm64.op_count++; + } + + MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); + + return; + } + } + + // All immediate shifts are aliases, implemented using the Bitfield + // instruction. In all cases the immediate shift amount shift must be in + // the range 0 to (reg.size -1). + if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) { + const char *AsmMnemonic = NULL; + int shift = 0; + int immr = (int)MCOperand_getImm(Op2); + int imms = (int)MCOperand_getImm(Op3); + + if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { + AsmMnemonic = "lsl"; + shift = 31 - imms; + } else if (Opcode == AArch64_UBFMXri && imms != 0x3f && + ((imms + 1 == immr))) { + AsmMnemonic = "lsl"; + shift = 63 - imms; + } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) { + AsmMnemonic = "lsr"; + shift = immr; + } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) { + AsmMnemonic = "lsr"; + shift = immr; + } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) { + AsmMnemonic = "asr"; + shift = immr; + } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) { + AsmMnemonic = "asr"; + shift = immr; + } + + if (AsmMnemonic) { + SStream_concat( + O, "%s\t%s, %s, ", AsmMnemonic, + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); + + printInt32Bang(O, shift); + + MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; - MI->flat_insn->detail->arm64.op_count++; + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; - MI->flat_insn->detail->arm64.op_count++; - } - - return; - } - - // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their - // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 > - // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction - // that can represent the move is the MOV alias, and the rest get printed - // normally. - if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) { - int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32; - int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); - uint64_t Value = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift; - - if (isMOVZMovAlias(Value, Shift, - Opcode == AArch64_MOVZXi ? 64 : 32)) { - SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); - - printInt64Bang(O, SignExtend64(Value, RegWidth)); - - if (MI->csh->detail) { + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op1); + MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; #endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); - MI->flat_insn->detail->arm64.op_count++; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = shift; + MI->flat_insn->detail->arm64.op_count++; + } - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth); - MI->flat_insn->detail->arm64.op_count++; - } + return; + } + } - MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); + // SBFIZ/UBFIZ aliases + if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) { + SStream_concat( + O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"), + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); - return; - } - } + printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2))); - if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) { - int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32; - int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); - uint64_t Value = ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift); + SStream_concat0(O, ", "); - if (RegWidth == 32) - Value = Value & 0xffffffff; + printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1); - if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) { - SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); + MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz")); - printInt64Bang(O, SignExtend64(Value, RegWidth)); + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op1); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = MCOperand_getImm(Op3) + 1; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + // Otherwise SBFX/UBFX is the preferred form + SStream_concat( + O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"), + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); + + printInt32Bang(O, (int)MCOperand_getImm(Op2)); + SStream_concat0(O, ", "); + printInt32Bang(O, + (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1); + + MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx")); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op1); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = MCOperand_getImm(Op2); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) { + MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0 + MCOperand *Op2 = MCInst_getOperand(MI, 2); + int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3)); + int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4)); + + if ((MCOperand_getReg(Op2) == AArch64_WZR || + MCOperand_getReg(Op2) == AArch64_XZR) && + (ImmR == 0 || ImmS < ImmR)) { + // BFC takes precedence over its entire range, sligtly differently to BFI. + int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; + int LSB = (BitWidth - ImmR) % BitWidth; + int Width = ImmS + 1; + + SStream_concat( + O, "bfc\t%s, ", + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName)); + + printInt32Bang(O, LSB); + SStream_concat0(O, ", "); + printInt32Bang(O, Width); + MCInst_setOpcodePub(MI, AArch64_map_insn("bfc")); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; - if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); - MI->flat_insn->detail->arm64.op_count++; - - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth); - MI->flat_insn->detail->arm64.op_count++; - } - - MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); - - return; - } - } - - if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) && - (MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR || - MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR) && - MCOperand_isImm(MCInst_getOperand(MI, 2))) { - int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32; - uint64_t Value = AArch64_AM_decodeLogicalImmediate( - MCOperand_getImm(MCInst_getOperand(MI, 2)), RegWidth); - if (!AArch64_AM_isAnyMOVWMovAlias(Value, RegWidth)) { - SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); - - printInt64Bang(O, SignExtend64(Value, RegWidth)); - - if (MI->csh->detail) { + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = LSB; + MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); - MI->flat_insn->detail->arm64.op_count++; - - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth); - MI->flat_insn->detail->arm64.op_count++; - } - - MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); - - return; - } - } - - // Instruction TSB is specified as a one operand instruction, but 'csync' is - // not encoded, so for printing it is treated as a special case here: - if (Opcode == AArch64_TSB) { - SStream_concat0(O, "tsb\tcsync"); - MCInst_setOpcodePub(MI, AArch64_map_insn("tsb")); - return; - } - - MI->MRI = Info; - - mnem = printAliasInstr(MI, O, (MCRegisterInfo *)Info); - if (mnem) { - MCInst_setOpcodePub(MI, AArch64_map_insn(mnem)); - cs_mem_free(mnem); - - switch(MCInst_getOpcode(MI)) { - default: break; - case AArch64_LD1i8_POST: - arm64_op_addImm(MI, 1); - break; - case AArch64_LD1i16_POST: - arm64_op_addImm(MI, 2); - break; - case AArch64_LD1i32_POST: - arm64_op_addImm(MI, 4); - break; - case AArch64_LD1Onev1d_POST: - case AArch64_LD1Onev2s_POST: - case AArch64_LD1Onev4h_POST: - case AArch64_LD1Onev8b_POST: - case AArch64_LD1i64_POST: - arm64_op_addImm(MI, 8); - break; - case AArch64_LD1Onev16b_POST: - case AArch64_LD1Onev2d_POST: - case AArch64_LD1Onev4s_POST: - case AArch64_LD1Onev8h_POST: - case AArch64_LD1Twov1d_POST: - case AArch64_LD1Twov2s_POST: - case AArch64_LD1Twov4h_POST: - case AArch64_LD1Twov8b_POST: - arm64_op_addImm(MI, 16); - break; - case AArch64_LD1Threev1d_POST: - case AArch64_LD1Threev2s_POST: - case AArch64_LD1Threev4h_POST: - case AArch64_LD1Threev8b_POST: - arm64_op_addImm(MI, 24); - break; - case AArch64_LD1Fourv1d_POST: - case AArch64_LD1Fourv2s_POST: - case AArch64_LD1Fourv4h_POST: - case AArch64_LD1Fourv8b_POST: - case AArch64_LD1Twov16b_POST: - case AArch64_LD1Twov2d_POST: - case AArch64_LD1Twov4s_POST: - case AArch64_LD1Twov8h_POST: - arm64_op_addImm(MI, 32); - break; - case AArch64_LD1Threev16b_POST: - case AArch64_LD1Threev2d_POST: - case AArch64_LD1Threev4s_POST: - case AArch64_LD1Threev8h_POST: - arm64_op_addImm(MI, 48); - break; - case AArch64_LD1Fourv16b_POST: - case AArch64_LD1Fourv2d_POST: - case AArch64_LD1Fourv4s_POST: - case AArch64_LD1Fourv8h_POST: - arm64_op_addImm(MI, 64); - break; - case AArch64_UMOVvi64: - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); - break; - case AArch64_UMOVvi32: - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); - break; - } - } else { - printInstruction(MI, O); - } -} - -static bool printSysAlias(MCInst *MI, SStream *O) -{ - // unsigned Opcode = MCInst_getOpcode(MI); - //assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!"); - - const char *Ins; - uint16_t Encoding; - bool NeedsReg; - char Name[64]; - MCOperand *Op1 = MCInst_getOperand(MI, 0); - MCOperand *Cn = MCInst_getOperand(MI, 1); - MCOperand *Cm = MCInst_getOperand(MI, 2); - MCOperand *Op2 = MCInst_getOperand(MI, 3); - - unsigned Op1Val = (unsigned)MCOperand_getImm(Op1); - unsigned CnVal = (unsigned)MCOperand_getImm(Cn); - unsigned CmVal = (unsigned)MCOperand_getImm(Cm); - unsigned Op2Val = (unsigned)MCOperand_getImm(Op2); - - Encoding = Op2Val; - Encoding |= CmVal << 3; - Encoding |= CnVal << 7; - Encoding |= Op1Val << 11; - - if (CnVal == 7) { - switch (CmVal) { - default: - return false; - - // IC aliases - case 1: case 5: { - const IC *IC = lookupICByEncoding(Encoding); - // if (!IC || !IC->haveFeatures(STI.getFeatureBits())) - if (!IC) - return false; - - NeedsReg = IC->NeedsReg; - Ins = "ic"; - strncpy(Name, IC->Name, sizeof(Name) - 1); - } - break; - - // DC aliases - case 4: case 6: case 10: case 11: case 12: case 14: { - const DC *DC = lookupDCByEncoding(Encoding); - // if (!DC || !DC->haveFeatures(STI.getFeatureBits())) - if (!DC) - return false; - - NeedsReg = true; - Ins = "dc"; - strncpy(Name, DC->Name, sizeof(Name) - 1); - } - break; - - // AT aliases - case 8: case 9: { - const AT *AT = lookupATByEncoding(Encoding); - // if (!AT || !AT->haveFeatures(STI.getFeatureBits())) - if (!AT) - return false; - - NeedsReg = true; - Ins = "at"; - strncpy(Name, AT->Name, sizeof(Name) - 1); - } - break; - } - } else if (CnVal == 8) { - // TLBI aliases - const TLBI *TLBI = lookupTLBIByEncoding(Encoding); - // if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits())) - if (!TLBI) - return false; - - NeedsReg = TLBI->NeedsReg; - Ins = "tlbi"; - strncpy(Name, TLBI->Name, sizeof(Name) - 1); - } else - return false; - - SStream_concat(O, "%s\t%s", Ins, Name); - - if (NeedsReg) { - SStream_concat(O, ", %s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 4)), AArch64_NoRegAltName)); - } - - MCInst_setOpcodePub(MI, AArch64_map_insn(Ins)); - - if (MI->csh->detail) { + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = Width; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } else if (ImmS < ImmR) { + // BFI alias + int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; + LSB = (BitWidth - ImmR) % BitWidth; + Width = ImmS + 1; + + SStream_concat( + O, "bfi\t%s, %s, ", + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); + + printInt32Bang(O, LSB); + SStream_concat0(O, ", "); + printInt32Bang(O, Width); + + MCInst_setOpcodePub(MI, AArch64_map_insn("bfi")); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op2); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = LSB; + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = Width; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + LSB = ImmR; + Width = ImmS - ImmR + 1; + // Otherwise BFXIL the preferred form + SStream_concat( + O, "bfxil\t%s, %s, ", + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), + getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); + + printInt32Bang(O, LSB); + SStream_concat0(O, ", "); + printInt32Bang(O, Width); + + MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil")); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(Op2); + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = LSB; + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = Width; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their + // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 > + // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction + // that can represent the move is the MOV alias, and the rest get printed + // normally. + if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 2))) { + int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32; + int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); + uint64_t Value = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) + << Shift; + + if (isMOVZMovAlias(Value, Shift, Opcode == AArch64_MOVZXi ? 64 : 32)) { + SStream_concat(O, "mov\t%s, ", + getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), + AArch64_NoRegAltName)); + + printInt64Bang(O, SignExtend64(Value, RegWidth)); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = SignExtend64(Value, RegWidth); + MI->flat_insn->detail->arm64.op_count++; + } + + MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); + + return; + } + } + + if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_isImm(MCInst_getOperand(MI, 2))) { + int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32; + int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); + uint64_t Value = + ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift); + + if (RegWidth == 32) + Value = Value & 0xffffffff; + + if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) { + SStream_concat(O, "mov\t%s, ", + getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), + AArch64_NoRegAltName)); + + printInt64Bang(O, SignExtend64(Value, RegWidth)); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = SignExtend64(Value, RegWidth); + MI->flat_insn->detail->arm64.op_count++; + } + + MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); + + return; + } + } + + if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) && + (MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR || + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR) && + MCOperand_isImm(MCInst_getOperand(MI, 2))) { + int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32; + uint64_t Value = AArch64_AM_decodeLogicalImmediate( + MCOperand_getImm(MCInst_getOperand(MI, 2)), RegWidth); + if (!AArch64_AM_isAnyMOVWMovAlias(Value, RegWidth)) { + SStream_concat(O, "mov\t%s, ", + getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), + AArch64_NoRegAltName)); + + printInt64Bang(O, SignExtend64(Value, RegWidth)); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = SignExtend64(Value, RegWidth); + MI->flat_insn->detail->arm64.op_count++; + } + + MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); + + return; + } + } + + // Instruction TSB is specified as a one operand instruction, but 'csync' is + // not encoded, so for printing it is treated as a special case here: + if (Opcode == AArch64_TSB) { + SStream_concat0(O, "tsb\tcsync"); + MCInst_setOpcodePub(MI, AArch64_map_insn("tsb")); + return; + } + + MI->MRI = Info; + + mnem = printAliasInstr(MI, O /*, (MCRegisterInfo *) Info*/); + if (mnem) { + MCInst_setOpcodePub(MI, AArch64_map_insn(mnem)); + cs_mem_free(mnem); + + switch (MCInst_getOpcode(MI)) { + default: + break; + case AArch64_LD1i8_POST: + arm64_op_addImm(MI, 1); + break; + case AArch64_LD1i16_POST: + arm64_op_addImm(MI, 2); + break; + case AArch64_LD1i32_POST: + arm64_op_addImm(MI, 4); + break; + case AArch64_LD1Onev1d_POST: + case AArch64_LD1Onev2s_POST: + case AArch64_LD1Onev4h_POST: + case AArch64_LD1Onev8b_POST: + case AArch64_LD1i64_POST: + arm64_op_addImm(MI, 8); + break; + case AArch64_LD1Onev16b_POST: + case AArch64_LD1Onev2d_POST: + case AArch64_LD1Onev4s_POST: + case AArch64_LD1Onev8h_POST: + case AArch64_LD1Twov1d_POST: + case AArch64_LD1Twov2s_POST: + case AArch64_LD1Twov4h_POST: + case AArch64_LD1Twov8b_POST: + arm64_op_addImm(MI, 16); + break; + case AArch64_LD1Threev1d_POST: + case AArch64_LD1Threev2s_POST: + case AArch64_LD1Threev4h_POST: + case AArch64_LD1Threev8b_POST: + arm64_op_addImm(MI, 24); + break; + case AArch64_LD1Fourv1d_POST: + case AArch64_LD1Fourv2s_POST: + case AArch64_LD1Fourv4h_POST: + case AArch64_LD1Fourv8b_POST: + case AArch64_LD1Twov16b_POST: + case AArch64_LD1Twov2d_POST: + case AArch64_LD1Twov4s_POST: + case AArch64_LD1Twov8h_POST: + arm64_op_addImm(MI, 32); + break; + case AArch64_LD1Threev16b_POST: + case AArch64_LD1Threev2d_POST: + case AArch64_LD1Threev4s_POST: + case AArch64_LD1Threev8h_POST: + arm64_op_addImm(MI, 48); + break; + case AArch64_LD1Fourv16b_POST: + case AArch64_LD1Fourv2d_POST: + case AArch64_LD1Fourv4s_POST: + case AArch64_LD1Fourv8h_POST: + arm64_op_addImm(MI, 64); + break; + case AArch64_UMOVvi64: + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); + break; + case AArch64_UMOVvi32: + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); + break; + } + } else { + printInstruction(MI, O); + } +} + +static bool printSysAlias(MCInst *MI, SStream *O) { + // unsigned Opcode = MCInst_getOpcode(MI); + // assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!"); + + const char *Ins; + uint16_t Encoding; + bool NeedsReg; + char Name[64]; + MCOperand *Op1 = MCInst_getOperand(MI, 0); + MCOperand *Cn = MCInst_getOperand(MI, 1); + MCOperand *Cm = MCInst_getOperand(MI, 2); + MCOperand *Op2 = MCInst_getOperand(MI, 3); + + unsigned Op1Val = (unsigned)MCOperand_getImm(Op1); + unsigned CnVal = (unsigned)MCOperand_getImm(Cn); + unsigned CmVal = (unsigned)MCOperand_getImm(Cm); + unsigned Op2Val = (unsigned)MCOperand_getImm(Op2); + + Encoding = Op2Val; + Encoding |= CmVal << 3; + Encoding |= CnVal << 7; + Encoding |= Op1Val << 11; + + if (CnVal == 7) { + switch (CmVal) { + default: + return false; + + // IC aliases + case 1: + case 5: { + const IC *IC = lookupICByEncoding(Encoding); + // if (!IC || !IC->haveFeatures(STI.getFeatureBits())) + if (!IC) + return false; + + NeedsReg = IC->NeedsReg; + Ins = "ic"; + strncpy(Name, IC->Name, sizeof(Name) - 1); + } break; + + // DC aliases + case 4: + case 6: + case 10: + case 11: + case 12: + case 14: { + const DC *DC = lookupDCByEncoding(Encoding); + // if (!DC || !DC->haveFeatures(STI.getFeatureBits())) + if (!DC) + return false; + + NeedsReg = true; + Ins = "dc"; + strncpy(Name, DC->Name, sizeof(Name) - 1); + } break; + + // AT aliases + case 8: + case 9: { + const AT *AT = lookupATByEncoding(Encoding); + // if (!AT || !AT->haveFeatures(STI.getFeatureBits())) + if (!AT) + return false; + + NeedsReg = true; + Ins = "at"; + strncpy(Name, AT->Name, sizeof(Name) - 1); + } break; + } + } else if (CnVal == 8) { + // TLBI aliases + const TLBI *TLBI = lookupTLBIByEncoding(Encoding); + // if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits())) + if (!TLBI) + return false; + + NeedsReg = TLBI->NeedsReg; + Ins = "tlbi"; + strncpy(Name, TLBI->Name, sizeof(Name) - 1); + } else + return false; + + SStream_concat(O, "%s\t%s", Ins, Name); + + if (NeedsReg) { + SStream_concat(O, ", %s", + getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 4)), + AArch64_NoRegAltName)); + } + + MCInst_setOpcodePub(MI, AArch64_map_insn(Ins)); + + if (MI->csh->detail) { #if 0 #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; #endif #endif - if (NeedsReg) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 4)); - MI->flat_insn->detail->arm64.op_count++; - } - } + if (NeedsReg) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, 4)); + MI->flat_insn->detail->arm64.op_count++; + } + } - return true; + return true; } -static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - - if (MCOperand_isReg(Op)) { - unsigned Reg = MCOperand_getReg(Op); - - SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg; - } - else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index == ARM64_REG_INVALID) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg; - } - } else { +static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + + if (MCOperand_isReg(Op)) { + unsigned Reg = MCOperand_getReg(Op); + + SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + if (MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .mem.base == ARM64_REG_INVALID) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .mem.base = Reg; + } else if (MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .mem.index == ARM64_REG_INVALID) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .mem.index = Reg; + } + } else { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), OpNum); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; - MI->flat_insn->detail->arm64.op_count++; - } - } - } else if (MCOperand_isImm(Op)) { - int64_t imm = MCOperand_getImm(Op); - - if (MI->Opcode == AArch64_ADR) { - imm += MI->address; - printUInt64Bang(O, imm); - } else { - if (MI->csh->doing_mem) { - if (MI->csh->imm_unsigned) { - printUInt64Bang(O, imm); - } else { - printInt64Bang(O, imm); - } - } else - printUInt64Bang(O, imm); - } - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm; - } else { + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), OpNum); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = Reg; + MI->flat_insn->detail->arm64.op_count++; + } + } + } else if (MCOperand_isImm(Op)) { + int64_t imm = MCOperand_getImm(Op); + + if (MI->Opcode == AArch64_ADR) { + imm += MI->address; + printUInt64Bang(O, imm); + } else { + if (MI->csh->imm_unsigned) { + printUInt64Bang(O, imm); + } else { + printInt64Bang(O, imm); + } + } + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .mem.disp = (int32_t)imm; + } else { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), OpNum); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; - MI->flat_insn->detail->arm64.op_count++; - } - } - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), OpNum); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = imm; + MI->flat_insn->detail->arm64.op_count++; + } + } + } } -static void printImm(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - printUInt64Bang(O, MCOperand_getImm(Op)); +static void printImm(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + printUInt64Bang(O, MCOperand_getImm(Op)); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .imm = MCOperand_getImm(Op); + MI->flat_insn->detail->arm64.op_count++; + } } -static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - printUInt64Bang(O, MCOperand_getImm(Op)); +static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + printUInt64Bang(O, MCOperand_getImm(Op)); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .imm = MCOperand_getImm(Op); + MI->flat_insn->detail->arm64.op_count++; + } } static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O, - unsigned Imm) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned Imm) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); - if (MCOperand_isReg(Op)) { - unsigned Reg = MCOperand_getReg(Op); - if (Reg == AArch64_XZR) { - printInt32Bang(O, Imm); + if (MCOperand_isReg(Op)) { + unsigned Reg = MCOperand_getReg(Op); + if (Reg == AArch64_XZR) { + printInt32Bang(O, Imm); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm; - MI->flat_insn->detail->arm64.op_count++; - } - } else { - SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); - - if (MI->csh->detail) { + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = Imm; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; - MI->flat_insn->detail->arm64.op_count++; - } - } - } - //llvm_unreachable("unknown operand kind in printPostIncOperand64"); + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = Reg; + MI->flat_insn->detail->arm64.op_count++; + } + } + } + // llvm_unreachable("unknown operand kind in printPostIncOperand64"); } -static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - //assert(Op.isReg() && "Non-register vreg operand!"); - unsigned Reg = MCOperand_getReg(Op); +static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + // assert(Op.isReg() && "Non-register vreg operand!"); + unsigned Reg = MCOperand_getReg(Op); - SStream_concat0(O, getRegisterName(Reg, AArch64_vreg)); + SStream_concat0(O, getRegisterName(Reg, AArch64_vreg)); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .reg = AArch64_map_vregister(Reg); + MI->flat_insn->detail->arm64.op_count++; + } } -static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); - SStream_concat(O, "c%u", MCOperand_getImm(Op)); +static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + // assert(Op.isImm() && "System instruction C[nm] operands must be + // immediates!"); + SStream_concat(O, "c%u", MCOperand_getImm(Op)); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_CIMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .imm = MCOperand_getImm(Op); + MI->flat_insn->detail->arm64.op_count++; + } } -static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); - if (MCOperand_isImm(MO)) { - unsigned Val = (MCOperand_getImm(MO) & 0xfff); - //assert(Val == MO.getImm() && "Add/sub immediate out of range!"); - unsigned Shift = AArch64_AM_getShiftValue((int)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1))); +static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); + if (MCOperand_isImm(MO)) { + unsigned Val = (MCOperand_getImm(MO) & 0xfff); + // assert(Val == MO.getImm() && "Add/sub immediate out of range!"); + unsigned Shift = AArch64_AM_getShiftValue( + (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1))); - printInt32Bang(O, Val); + printInt32Bang(O, Val); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; - MI->flat_insn->detail->arm64.op_count++; - } - - if (Shift != 0) - printShifter(MI, OpNum + 1, O); - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } + + if (Shift != 0) + printShifter(MI, OpNum + 1, O); + } } -static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) -{ - int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); +static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) { + int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - Val = AArch64_AM_decodeLogicalImmediate(Val, 32); - printUInt32Bang(O, (int)Val); + Val = AArch64_AM_decodeLogicalImmediate(Val, 32); + printUInt32Bang(O, (int)Val); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } } -static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) -{ - int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - Val = AArch64_AM_decodeLogicalImmediate(Val, 64); - - switch(MI->flat_insn->id) { - default: - printInt64Bang(O, Val); - break; - - case ARM64_INS_ORR: - case ARM64_INS_AND: - case ARM64_INS_EOR: - case ARM64_INS_TST: - // do not print number in negative form - if (Val >= 0 && Val <= HEX_THRESHOLD) - SStream_concat(O, "#%u", (int)Val); - else - SStream_concat(O, "#0x%"PRIx64, Val); - break; - } - - if (MI->csh->detail) { +static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) { + int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + Val = AArch64_AM_decodeLogicalImmediate(Val, 64); + + switch (MI->flat_insn->id) { + default: + printInt64Bang(O, Val); + break; + + case ARM64_INS_ORR: + case ARM64_INS_AND: + case ARM64_INS_EOR: + case ARM64_INS_TST: + // do not print number in negative form + if (Val >= 0 && Val <= HEX_THRESHOLD) + SStream_concat(O, "#%u", (int)Val); + else + SStream_concat(O, "#0x%" PRIx64, Val); + break; + } + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int64_t)Val; - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .imm = (int64_t)Val; + MI->flat_insn->detail->arm64.op_count++; + } } -static void printShifter(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - - // LSL #0 should not be printed. - if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL && - AArch64_AM_getShiftValue(Val) == 0) - return; - - SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val))); - printInt32BangDec(O, AArch64_AM_getShiftValue(Val)); - - if (MI->csh->detail) { - arm64_shifter shifter = ARM64_SFT_INVALID; - - switch(AArch64_AM_getShiftType(Val)) { - default: // never reach - case AArch64_AM_LSL: - shifter = ARM64_SFT_LSL; - break; - - case AArch64_AM_LSR: - shifter = ARM64_SFT_LSR; - break; - - case AArch64_AM_ASR: - shifter = ARM64_SFT_ASR; - break; - - case AArch64_AM_ROR: - shifter = ARM64_SFT_ROR; - break; - - case AArch64_AM_MSL: - shifter = ARM64_SFT_MSL; - break; - } - - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shifter; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = AArch64_AM_getShiftValue(Val); - } +static void printShifter(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + // LSL #0 should not be printed. + if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL && + AArch64_AM_getShiftValue(Val) == 0) + return; + + SStream_concat(O, ", %s ", + AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val))); + printInt32BangDec(O, AArch64_AM_getShiftValue(Val)); + + if (MI->csh->detail) { + arm64_shifter shifter = ARM64_SFT_INVALID; + + switch (AArch64_AM_getShiftType(Val)) { + default: // never reach + case AArch64_AM_LSL: + shifter = ARM64_SFT_LSL; + break; + + case AArch64_AM_LSR: + shifter = ARM64_SFT_LSR; + break; + + case AArch64_AM_ASR: + shifter = ARM64_SFT_ASR; + break; + + case AArch64_AM_ROR: + shifter = ARM64_SFT_ROR; + break; + + case AArch64_AM_MSL: + shifter = ARM64_SFT_MSL; + break; + } + + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count - 1] + .shift.type = shifter; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count - 1] + .shift.value = AArch64_AM_getShiftValue(Val); + } } -static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O) -{ - SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); +static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O) { + SStream_concat0( + O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), + AArch64_NoRegAltName)); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + MI->flat_insn->detail->arm64.op_count++; + } + + printShifter(MI, OpNum + 1, O); +} - printShifter(MI, OpNum + 1, O); +static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); + unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val); + + // If the destination or first source register operand is [W]SP, print + // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at + // all. + if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { + unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0)); + unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1)); + + if (((Dest == AArch64_SP || Src1 == AArch64_SP) && + ExtType == AArch64_AM_UXTX) || + ((Dest == AArch64_WSP || Src1 == AArch64_WSP) && + ExtType == AArch64_AM_UXTW)) { + if (ShiftVal != 0) { + SStream_concat0(O, ", lsl "); + printInt32Bang(O, ShiftVal); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count - 1] + .shift.type = ARM64_SFT_LSL; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count - 1] + .shift.value = ShiftVal; + } + } + + return; + } + } + + SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); + + if (MI->csh->detail) { + arm64_extender ext = ARM64_EXT_INVALID; + switch (ExtType) { + default: // never reach + + case AArch64_AM_UXTB: + ext = ARM64_EXT_UXTB; + break; + + case AArch64_AM_UXTH: + ext = ARM64_EXT_UXTH; + break; + + case AArch64_AM_UXTW: + ext = ARM64_EXT_UXTW; + break; + + case AArch64_AM_UXTX: + ext = ARM64_EXT_UXTX; + break; + + case AArch64_AM_SXTB: + ext = ARM64_EXT_SXTB; + break; + + case AArch64_AM_SXTH: + ext = ARM64_EXT_SXTH; + break; + + case AArch64_AM_SXTW: + ext = ARM64_EXT_SXTW; + break; + + case AArch64_AM_SXTX: + ext = ARM64_EXT_SXTX; + break; + } + + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count - 1] + .ext = ext; + } + + if (ShiftVal != 0) { + SStream_concat0(O, " "); + printInt32Bang(O, ShiftVal); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count - 1] + .shift.type = ARM64_SFT_LSL; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count - 1] + .shift.value = ShiftVal; + } + } } -static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); - unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val); - - // If the destination or first source register operand is [W]SP, print - // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at - // all. - if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { - unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0)); - unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1)); - - if (((Dest == AArch64_SP || Src1 == AArch64_SP) && - ExtType == AArch64_AM_UXTX) || - ((Dest == AArch64_WSP || Src1 == AArch64_WSP) && - ExtType == AArch64_AM_UXTW)) { - if (ShiftVal != 0) { - SStream_concat0(O, ", lsl "); - printInt32Bang(O, ShiftVal); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; - } - } - - return; - } - } - - SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); - - if (MI->csh->detail) { - arm64_extender ext = ARM64_EXT_INVALID; - switch(ExtType) { - default: // never reach - - case AArch64_AM_UXTB: - ext = ARM64_EXT_UXTB; - break; - - case AArch64_AM_UXTH: - ext = ARM64_EXT_UXTH; - break; - - case AArch64_AM_UXTW: - ext = ARM64_EXT_UXTW; - break; - - case AArch64_AM_UXTX: - ext = ARM64_EXT_UXTX; - break; - - case AArch64_AM_SXTB: - ext = ARM64_EXT_SXTB; - break; - - case AArch64_AM_SXTH: - ext = ARM64_EXT_SXTH; - break; - - case AArch64_AM_SXTW: - ext = ARM64_EXT_SXTW; - break; - - case AArch64_AM_SXTX: - ext = ARM64_EXT_SXTX; - break; - } - - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext; - } - - if (ShiftVal != 0) { - SStream_concat0(O, " "); - printInt32Bang(O, ShiftVal); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; - } - } -} - -static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .reg = Reg; + MI->flat_insn->detail->arm64.op_count++; + } + + printArithExtend(MI, OpNum + 1, O); +} - printArithExtend(MI, OpNum + 1, O); +static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, + unsigned Width, char SrcRegKind, SStream *O) { + // sxtw, sxtx, uxtw or lsl (== uxtx) + bool IsLSL = !SignExtend && SrcRegKind == 'x'; + if (IsLSL) { + SStream_concat0(O, "lsl"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .shift.type = ARM64_SFT_LSL; + } + } else { + SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind); + + if (MI->csh->detail) { + if (!SignExtend) { + switch (SrcRegKind) { + default: + break; + case 'b': + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .ext = ARM64_EXT_UXTB; + break; + case 'h': + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .ext = ARM64_EXT_UXTH; + break; + case 'w': + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .ext = ARM64_EXT_UXTW; + break; + } + } else { + switch (SrcRegKind) { + default: + break; + case 'b': + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .ext = ARM64_EXT_SXTB; + break; + case 'h': + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .ext = ARM64_EXT_SXTH; + break; + case 'w': + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .ext = ARM64_EXT_SXTW; + break; + case 'x': + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .ext = ARM64_EXT_SXTX; + break; + } + } + } + } + + if (DoShift || IsLSL) { + SStream_concat(O, " #%u", Log2_32(Width / 8)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .shift.type = ARM64_SFT_LSL; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .shift.value = Log2_32(Width / 8); + } + } } -static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, unsigned Width, - char SrcRegKind, SStream *O) -{ - // sxtw, sxtx, uxtw or lsl (== uxtx) - bool IsLSL = !SignExtend && SrcRegKind == 'x'; - if (IsLSL) { - SStream_concat0(O, "lsl"); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; - } - } else { - SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind); - - if (MI->csh->detail) { - if (!SignExtend) { - switch(SrcRegKind) { - default: break; - case 'b': - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB; - break; - case 'h': - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH; - break; - case 'w': - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW; - break; - } - } else { - switch(SrcRegKind) { - default: break; - case 'b': - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB; - break; - case 'h': - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH; - break; - case 'w': - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW; - break; - case 'x': - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX; - break; - } - } - } - } - - if (DoShift || IsLSL) { - SStream_concat(O, " #%u", Log2_32(Width / 8)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8); - } - } -} - -static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width) -{ - unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); +static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, + char SrcRegKind, unsigned Width) { + unsigned SignExtend = + (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned DoShift = + (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); - printMemExtendImpl(MI, SignExtend, DoShift, Width, SrcRegKind, O); + printMemExtendImpl(MI, SignExtend, DoShift, Width, SrcRegKind, O); } static void printRegWithShiftExtend(MCInst *MI, unsigned OpNum, SStream *O, - bool SignExtend, int ExtWidth, - char SrcRegKind, char Suffix) -{ - bool DoShift; + bool SignExtend, int ExtWidth, + char SrcRegKind, char Suffix) { + bool DoShift; - printOperand(MI, OpNum, O); + printOperand(MI, OpNum, O); - if (Suffix == 's' || Suffix == 'd') - SStream_concat(O, ".%c", Suffix); + if (Suffix == 's' || Suffix == 'd') + SStream_concat(O, ".%c", Suffix); - DoShift = ExtWidth != 8; - if (SignExtend || DoShift || SrcRegKind == 'w') { - SStream_concat0(O, ", "); - printMemExtendImpl(MI, SignExtend, DoShift, ExtWidth, SrcRegKind, O); - } + DoShift = ExtWidth != 8; + if (SignExtend || DoShift || SrcRegKind == 'w') { + SStream_concat0(O, ", "); + printMemExtendImpl(MI, SignExtend, DoShift, ExtWidth, SrcRegKind, O); + } } -static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O) -{ - AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - SStream_concat0(O, getCondCodeName(CC)); +static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O) { + AArch64CC_CondCode CC = + (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, getCondCodeName(CC)); - if (MI->csh->detail) - MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1); + if (MI->csh->detail) + MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1); } -static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O) -{ - AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC))); +static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O) { + AArch64CC_CondCode CC = + (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1); - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1); + } } -static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale) -{ - int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); +static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale) { + int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - printInt64Bang(O, val); + printInt64Bang(O, val); - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; - } else { + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .mem.disp = (int32_t)val; + } else { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val; - MI->flat_insn->detail->arm64.op_count++; - } - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = val; + MI->flat_insn->detail->arm64.op_count++; + } + } } -static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); +static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, + unsigned Scale) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); - if (MCOperand_isImm(MO)) { - int64_t val = Scale * MCOperand_getImm(MO); - printInt64Bang(O, val); + if (MCOperand_isImm(MO)) { + int64_t val = Scale * MCOperand_getImm(MO); + printInt64Bang(O, val); - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; - } else { + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .mem.disp = (int32_t)val; + } else { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val; - MI->flat_insn->detail->arm64.op_count++; - } - } - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = (int)val; + MI->flat_insn->detail->arm64.op_count++; + } + } + } } #if 0 static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale) { - MCOperand *MO = MCInst_getOperand(MI, OpNum + 1); + MCOperand *MO = MCInst_getOperand(MI, OpNum + 1); - SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); + SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); - if (MCOperand_isImm(MO)) { - int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - printInt64Bang(O, val); - // } else { - // // assert(MO1.isExpr() && "Unexpected operand type!"); - // SStream_concat0(O, ", "); - // MO1.getExpr()->print(O, &MAI); - } + if (MCOperand_isImm(MO)) { + int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + printInt64Bang(O, val); + // } else { + // // assert(MO1.isExpr() && "Unexpected operand type!"); + // SStream_concat0(O, ", "); + // MO1.getExpr()->print(O, &MAI); + } - SStream_concat0(O, "]"); + SStream_concat0(O, "]"); } #endif // IsSVEPrefetch = false -static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, bool IsSVEPrefetch) -{ - unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); +static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, + bool IsSVEPrefetch) { + unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - if (IsSVEPrefetch) { - const SVEPRFM *PRFM = lookupSVEPRFMByEncoding(prfop); - if (PRFM) - SStream_concat0(O, PRFM->Name); + if (IsSVEPrefetch) { + const SVEPRFM *PRFM = lookupSVEPRFMByEncoding(prfop); + if (PRFM) + SStream_concat0(O, PRFM->Name); - return; - } else { - const PRFM *PRFM = lookupPRFMByEncoding(prfop); - if (PRFM) - SStream_concat0(O, PRFM->Name); + return; + } else { + const PRFM *PRFM = lookupPRFMByEncoding(prfop); + if (PRFM) + SStream_concat0(O, PRFM->Name); - return; - } + return; + } - // FIXME: set OpcodePub? + // FIXME: set OpcodePub? - printInt32Bang(O, prfop); + printInt32Bang(O, prfop); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop; - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .imm = prfop; + MI->flat_insn->detail->arm64.op_count++; + } } -static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - unsigned int psbhintop = MCOperand_getImm(Op); +static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned int psbhintop = MCOperand_getImm(Op); - const PSB *PSB = AArch64PSBHint_lookupPSBByEncoding(psbhintop); - if (PSB) - SStream_concat0(O, PSB->Name); - else - printUInt32Bang(O, psbhintop); + const PSB *PSB = AArch64PSBHint_lookupPSBByEncoding(psbhintop); + if (PSB) + SStream_concat0(O, PSB->Name); + else + printUInt32Bang(O, psbhintop); } -static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); - float FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO)); +static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); + float FPImm = MCOperand_isFPImm(MO) + ? MCOperand_getFPImm(MO) + : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO)); - // 8 decimal places are enough to perfectly represent permitted floats. + // 8 decimal places are enough to perfectly represent permitted floats. #if defined(_KERNEL_MODE) - // Issue #681: Windows kernel does not support formatting float point - SStream_concat(O, "#"); + // Issue #681: Windows kernel does not support formatting float point + SStream_concat(O, "#"); #else - SStream_concat(O, "#%.8f", FPImm); + SStream_concat(O, "#%.8f", FPImm); #endif - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm; - MI->flat_insn->detail->arm64.op_count++; - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_FP; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .fp = FPImm; + MI->flat_insn->detail->arm64.op_count++; + } } -//static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) -static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride) -{ - while (Stride--) { - if (Reg >= AArch64_Q0 && Reg <= AArch64_Q30) // AArch64_Q0 .. AArch64_Q30 - Reg += 1; - else if (Reg == AArch64_Q31) // Vector lists can wrap around. - Reg = AArch64_Q0; - else if (Reg >= AArch64_Z0 && Reg <= AArch64_Z30) // AArch64_Z0 .. AArch64_Z30 - Reg += 1; - else if (Reg == AArch64_Z31) // Vector lists can wrap around. - Reg = AArch64_Z0; - } - - return Reg; +// static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) +static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride) { + while (Stride--) { + if (Reg >= AArch64_Q0 && Reg <= AArch64_Q30) // AArch64_Q0 .. AArch64_Q30 + Reg += 1; + else if (Reg == AArch64_Q31) // Vector lists can wrap around. + Reg = AArch64_Q0; + else if (Reg >= AArch64_Z0 && + Reg <= AArch64_Z30) // AArch64_Z0 .. AArch64_Z30 + Reg += 1; + else if (Reg == AArch64_Z31) // Vector lists can wrap around. + Reg = AArch64_Z0; + } + + return Reg; } -static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned int size) -{ - // static_assert(size == 64 || size == 32, - // "Template parameter must be either 32 or 64"); - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - unsigned Sube = (size == 32) ? AArch64_sube32 : AArch64_sube64; - unsigned Subo = (size == 32) ? AArch64_subo32 : AArch64_subo64; - unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube); - unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo); - - SStream_concat(O, "%s, %s", getRegisterName(Even, AArch64_NoRegAltName), - getRegisterName(Odd, AArch64_NoRegAltName)); - - if (MI->csh->detail) { -#ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif +static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, + unsigned int size) { + // static_assert(size == 64 || size == 32, + // "Template parameter must be either 32 or 64"); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned Sube = (size == 32) ? AArch64_sube32 : AArch64_sube64; + unsigned Subo = (size == 32) ? AArch64_subo32 : AArch64_subo64; + unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube); + unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Even); - MI->flat_insn->detail->arm64.op_count++; + SStream_concat(O, "%s, %s", getRegisterName(Even, AArch64_NoRegAltName), + getRegisterName(Odd, AArch64_NoRegAltName)); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Odd); - MI->flat_insn->detail->arm64.op_count++; - } + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .reg = AArch64_map_vregister(Even); + MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .reg = AArch64_map_vregister(Odd); + MI->flat_insn->detail->arm64.op_count++; + } } static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, - char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas) -{ -#define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg) - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - unsigned NumRegs = 1, FirstReg, i; - - SStream_concat0(O, "{"); - - // Work out how many registers there are in the list (if there is an actual - // list). - if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) || - GETREGCLASS_CONTAIN0(AArch64_ZPR2RegClassID, Reg) || - GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg)) - NumRegs = 2; - else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) || - GETREGCLASS_CONTAIN0(AArch64_ZPR3RegClassID, Reg) || - GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg)) - NumRegs = 3; - else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) || - GETREGCLASS_CONTAIN0(AArch64_ZPR4RegClassID, Reg) || - GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg)) - NumRegs = 4; - - // Now forget about the list and find out what the first register is. - if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0))) - Reg = FirstReg; - else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0))) - Reg = FirstReg; - else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_zsub0))) - Reg = FirstReg; - - // If it's a D-reg, we need to promote it to the equivalent Q-reg before - // printing (otherwise getRegisterName fails). - if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) { - const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID); - Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC); - } - - for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) { - if (GETREGCLASS_CONTAIN0(AArch64_ZPRRegClassID, Reg)) - SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName), LayoutSuffix); - else - SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix); - - if (MI->csh->detail) { + char *LayoutSuffix, MCRegisterInfo *MRI, + arm64_vas vas) { +#define GETREGCLASS_CONTAIN0(_class, _reg) \ + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg) + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned NumRegs = 1, FirstReg, i; + + SStream_concat0(O, "{"); + + // Work out how many registers there are in the list (if there is an actual + // list). + if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_ZPR2RegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg)) + NumRegs = 2; + else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_ZPR3RegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg)) + NumRegs = 3; + else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_ZPR4RegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg)) + NumRegs = 4; + + // Now forget about the list and find out what the first register is. + if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0))) + Reg = FirstReg; + else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0))) + Reg = FirstReg; + else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_zsub0))) + Reg = FirstReg; + + // If it's a D-reg, we need to promote it to the equivalent Q-reg before + // printing (otherwise getRegisterName fails). + if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) { + const MCRegisterClass *FPR128RC = + MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID); + Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC); + } + + for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) { + if (GETREGCLASS_CONTAIN0(AArch64_ZPRRegClassID, Reg)) + SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName), + LayoutSuffix); + else + SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), + LayoutSuffix); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas; - MI->flat_insn->detail->arm64.op_count++; - } - - if (i + 1 != NumRegs) - SStream_concat0(O, ", "); - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = AArch64_map_vregister(Reg); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .vas = vas; + MI->flat_insn->detail->arm64.op_count++; + } + + if (i + 1 != NumRegs) + SStream_concat0(O, ", "); + } + + SStream_concat0(O, "}"); +} - SStream_concat0(O, "}"); +static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, + unsigned NumLanes, char LaneKind) { + char Suffix[32]; + arm64_vas vas = 0; + + if (NumLanes) { + cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind); + + switch (LaneKind) { + default: + break; + case 'b': + switch (NumLanes) { + default: + break; + case 1: + vas = ARM64_VAS_1B; + break; + case 4: + vas = ARM64_VAS_4B; + break; + case 8: + vas = ARM64_VAS_8B; + break; + case 16: + vas = ARM64_VAS_16B; + break; + } + break; + case 'h': + switch (NumLanes) { + default: + break; + case 1: + vas = ARM64_VAS_1H; + break; + case 2: + vas = ARM64_VAS_2H; + break; + case 4: + vas = ARM64_VAS_4H; + break; + case 8: + vas = ARM64_VAS_8H; + break; + } + break; + case 's': + switch (NumLanes) { + default: + break; + case 1: + vas = ARM64_VAS_1S; + break; + case 2: + vas = ARM64_VAS_2S; + break; + case 4: + vas = ARM64_VAS_4S; + break; + } + break; + case 'd': + switch (NumLanes) { + default: + break; + case 1: + vas = ARM64_VAS_1D; + break; + case 2: + vas = ARM64_VAS_2D; + break; + } + break; + case 'q': + switch (NumLanes) { + default: + break; + case 1: + vas = ARM64_VAS_1Q; + break; + } + break; + } + } else { + cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind); + + switch (LaneKind) { + default: + break; + case 'b': + vas = ARM64_VAS_1B; + break; + case 'h': + vas = ARM64_VAS_1H; + break; + case 's': + vas = ARM64_VAS_1S; + break; + case 'd': + vas = ARM64_VAS_1D; + break; + case 'q': + vas = ARM64_VAS_1Q; + break; + } + } + + printVectorList(MI, OpNum, O, Suffix, MI->MRI, vas); } -static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind) -{ - char Suffix[32]; - arm64_vas vas = 0; - - if (NumLanes) { - cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind); - - switch(LaneKind) { - default: break; - case 'b': - switch(NumLanes) { - default: break; - case 1: - vas = ARM64_VAS_1B; - break; - case 4: - vas = ARM64_VAS_4B; - break; - case 8: - vas = ARM64_VAS_8B; - break; - case 16: - vas = ARM64_VAS_16B; - break; - } - break; - case 'h': - switch(NumLanes) { - default: break; - case 1: - vas = ARM64_VAS_1H; - break; - case 2: - vas = ARM64_VAS_2H; - break; - case 4: - vas = ARM64_VAS_4H; - break; - case 8: - vas = ARM64_VAS_8H; - break; - } - break; - case 's': - switch(NumLanes) { - default: break; - case 1: - vas = ARM64_VAS_1S; - break; - case 2: - vas = ARM64_VAS_2S; - break; - case 4: - vas = ARM64_VAS_4S; - break; - } - break; - case 'd': - switch(NumLanes) { - default: break; - case 1: - vas = ARM64_VAS_1D; - break; - case 2: - vas = ARM64_VAS_2D; - break; - } - break; - case 'q': - switch(NumLanes) { - default: break; - case 1: - vas = ARM64_VAS_1Q; - break; - } - break; - } - } else { - cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind); - - switch(LaneKind) { - default: break; - case 'b': - vas = ARM64_VAS_1B; - break; - case 'h': - vas = ARM64_VAS_1H; - break; - case 's': - vas = ARM64_VAS_1S; - break; - case 'd': - vas = ARM64_VAS_1D; - break; - case 'q': - vas = ARM64_VAS_1Q; - break; - } - } - - printVectorList(MI, OpNum, O, Suffix, MI->MRI, vas); -} - -static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) -{ - SStream_concat0(O, "["); - printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum))); - SStream_concat0(O, "]"); +static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) { + SStream_concat0(O, "["); + printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum))); + SStream_concat0(O, "]"); - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count - 1] + .vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + } } -static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); +static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); - // If the label has already been resolved to an immediate offset (say, when - // we're running the disassembler), just print the immediate. - if (MCOperand_isImm(Op)) { - uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address; - printUInt64Bang(O, imm); + // If the label has already been resolved to an immediate offset (say, when + // we're running the disassembler), just print the immediate. + if (MCOperand_isImm(Op)) { + uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address; + printUInt64Bang(O, imm); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; - MI->flat_insn->detail->arm64.op_count++; - } - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = imm; + MI->flat_insn->detail->arm64.op_count++; + } + } } -static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); +static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); - if (MCOperand_isImm(Op)) { - // ADRP sign extends a 21-bit offset, shifts it left by 12 - // and adds it to the value of the PC with its bottom 12 bits cleared - uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff); - printUInt64Bang(O, imm); + if (MCOperand_isImm(Op)) { + // ADRP sign extends a 21-bit offset, shifts it left by 12 + // and adds it to the value of the PC with its bottom 12 bits cleared + uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff); + printUInt64Bang(O, imm); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; - MI->flat_insn->detail->arm64.op_count++; - } - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = imm; + MI->flat_insn->detail->arm64.op_count++; + } + } } -static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - unsigned Opcode = MCInst_getOpcode(MI); - const char *Name = NULL; - - if (Opcode == AArch64_ISB) { - const ISB *ISB = lookupISBByEncoding(Val); - Name = ISB ? ISB->Name : NULL; - } else if (Opcode == AArch64_TSB) { - const TSB *TSB = lookupTSBByEncoding(Val); - Name = TSB ? TSB->Name : NULL; - } else { - const DB *DB = lookupDBByEncoding(Val); - Name = DB ? DB->Name : NULL; - } - - if (Name) { - SStream_concat0(O, Name); - - if (MI->csh->detail) { +static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned Opcode = MCInst_getOpcode(MI); + const char *Name = NULL; + + if (Opcode == AArch64_ISB) { + const ISB *ISB = lookupISBByEncoding(Val); + Name = ISB ? ISB->Name : NULL; + } else if (Opcode == AArch64_TSB) { + const TSB *TSB = lookupTSBByEncoding(Val); + Name = TSB ? TSB->Name : NULL; + } else { + const DB *DB = lookupDBByEncoding(Val); + Name = DB ? DB->Name : NULL; + } + + if (Name) { + SStream_concat0(O, Name); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val; - MI->flat_insn->detail->arm64.op_count++; - } - } else { - printUInt32Bang(O, Val); - - if (MI->csh->detail) { + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_BARRIER; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .barrier = Val; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + printUInt32Bang(O, Val); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; - MI->flat_insn->detail->arm64.op_count++; - } - } + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } + } } -static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - const SysReg *Reg = lookupSysRegByEncoding(Val); +static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + const SysReg *Reg = lookupSysRegByEncoding(Val); - // Horrible hack for the one register that has identical encodings but - // different names in MSR and MRS. Because of this, one of MRS and MSR is - // going to get the wrong entry - if (Val == ARM64_SYSREG_DBGDTRRX_EL0) { - SStream_concat0(O, "dbgdtrrx_el0"); + // Horrible hack for the one register that has identical encodings but + // different names in MSR and MRS. Because of this, one of MRS and MSR is + // going to get the wrong entry + if (Val == ARM64_SYSREG_DBGDTRRX_EL0) { + SStream_concat0(O, "dbgdtrrx_el0"); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; #endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; - MI->flat_insn->detail->arm64.op_count++; - } + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_SYS; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .sys = Val; + MI->flat_insn->detail->arm64.op_count++; + } - return; - } + return; + } - // if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) - if (Reg && Reg->Readable) { - SStream_concat0(O, Reg->Name); + // if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) + if (Reg && Reg->Readable) { + SStream_concat0(O, Reg->Name); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding; - MI->flat_insn->detail->arm64.op_count++; - } - } else { - char result[128]; - - AArch64SysReg_genericRegisterString(Val, result); - SStream_concat0(O, result); - - if (MI->csh->detail) { + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_SYS; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .sys = Reg->Encoding; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + char result[128]; + + AArch64SysReg_genericRegisterString(Val, result); + SStream_concat0(O, result); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; - MI->flat_insn->detail->arm64.op_count++; - } - } + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG_MRS; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = Val; + MI->flat_insn->detail->arm64.op_count++; + } + } } -static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - const SysReg *Reg = lookupSysRegByEncoding(Val); +static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + const SysReg *Reg = lookupSysRegByEncoding(Val); - // Horrible hack for the one register that has identical encodings but - // different names in MSR and MRS. Because of this, one of MRS and MSR is - // going to get the wrong entry - if (Val == ARM64_SYSREG_DBGDTRTX_EL0) { - SStream_concat0(O, "dbgdtrtx_el0"); + // Horrible hack for the one register that has identical encodings but + // different names in MSR and MRS. Because of this, one of MRS and MSR is + // going to get the wrong entry + if (Val == ARM64_SYSREG_DBGDTRTX_EL0) { + SStream_concat0(O, "dbgdtrtx_el0"); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; #endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; - MI->flat_insn->detail->arm64.op_count++; - } + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_SYS; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .sys = Val; + MI->flat_insn->detail->arm64.op_count++; + } - return; - } + return; + } - // if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) - if (Reg && Reg->Writeable) { - SStream_concat0(O, Reg->Name); + // if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) + if (Reg && Reg->Writeable) { + SStream_concat0(O, Reg->Name); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding; - MI->flat_insn->detail->arm64.op_count++; - } - } else { - char result[128]; - - AArch64SysReg_genericRegisterString(Val, result); - SStream_concat0(O, result); - - if (MI->csh->detail) { + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_SYS; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .sys = Reg->Encoding; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + char result[128]; + + AArch64SysReg_genericRegisterString(Val, result); + SStream_concat0(O, result); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; - MI->flat_insn->detail->arm64.op_count++; - } - } + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG_MRS; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .reg = Val; + MI->flat_insn->detail->arm64.op_count++; + } + } } -static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); +static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - const PState *PState = lookupPStateByEncoding(Val); + const PState *PState = lookupPStateByEncoding(Val); - if (PState) { - SStream_concat0(O, PState->Name); + if (PState) { + SStream_concat0(O, PState->Name); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTATE; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val; - MI->flat_insn->detail->arm64.op_count++; - } - } else { - printUInt32Bang(O, Val); - - if (MI->csh->detail) { + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_PSTATE; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .pstate = Val; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + printUInt32Bang(O, Val); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - unsigned char access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; - MI->flat_insn->detail->arm64.op_count++; - } - } + unsigned char access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count] + .imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } + } } -static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O) -{ - uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal); +static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O) { + uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal); - SStream_concat(O, "#%#016llx", Val); + SStream_concat(O, "#%#016llx", Val); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - unsigned char access; - - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; - MI->flat_insn->detail->arm64.op_count++; - } + unsigned char access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } } -static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, int64_t Angle, int64_t Remainder) -{ - unsigned int Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - printInt64Bang(O, (Val * Angle) + Remainder); - op_addImm(MI, (Val * Angle) + Remainder); +static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, + int64_t Angle, int64_t Remainder) { + unsigned int Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + printInt64Bang(O, (Val * Angle) + Remainder); + op_addImm(MI, (Val * Angle) + Remainder); } -static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); +static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - const SVEPREDPAT *Pat = lookupSVEPREDPATByEncoding(Val); - if (Pat) - SStream_concat0(O, Pat->Name); - else - printUInt32Bang(O, Val); + const SVEPREDPAT *Pat = lookupSVEPREDPATByEncoding(Val); + if (Pat) + SStream_concat0(O, Pat->Name); + else + printUInt32Bang(O, Val); } // default suffix = 0 -static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix) -{ - unsigned int Reg; +static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix) { + unsigned int Reg; #if 0 - switch (suffix) { - case 0: - case 'b': - case 'h': - case 's': - case 'd': - case 'q': - break; - default: - // llvm_unreachable("Invalid kind specifier."); - } -#endif + switch (suffix) { + case 0: + case 'b': + case 'h': + case 's': + case 'd': + case 'q': + break; + default: + // llvm_unreachable("Invalid kind specifier."); + } +#endif + + Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .reg = Reg; + MI->flat_insn->detail->arm64.op_count++; + } + + SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + + if (suffix != '\0') + SStream_concat(O, ".%c", suffix); +} - Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +static void printImmSVE16(int16_t Val, SStream *O) { printUInt32Bang(O, Val); } - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; - MI->flat_insn->detail->arm64.op_count++; - } +static void printImmSVE32(int32_t Val, SStream *O) { printUInt32Bang(O, Val); } - SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); +static void printImmSVE64(int64_t Val, SStream *O) { printUInt64Bang(O, Val); } - if (suffix != '\0') - SStream_concat(O, ".%c", suffix); -} +static void printImm8OptLsl32(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); + uint32_t Val; -static void printImmSVE16(int16_t Val, SStream *O) -{ - printUInt32Bang(O, Val); -} + // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && + // "Unexepected shift type!"); -static void printImmSVE32(int32_t Val, SStream *O) -{ - printUInt32Bang(O, Val); + // #0 lsl #8 is never pretty printed + if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { + printUInt32Bang(O, UnscaledVal); + printShifter(MI, OpNum + 1, O); + return; + } + + Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); + printImmSVE32(Val, O); } -static void printImmSVE64(int64_t Val, SStream *O) -{ - printUInt64Bang(O, Val); +static void printImm8OptLsl64(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); + uint64_t Val; + + // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && + // "Unexepected shift type!"); + + // #0 lsl #8 is never pretty printed + if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { + printUInt32Bang(O, UnscaledVal); + printShifter(MI, OpNum + 1, O); + return; + } + + Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); + printImmSVE64(Val, O); } -static void printImm8OptLsl32(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); - uint32_t Val; +static void printSVELogicalImm16(MCInst *MI, unsigned OpNum, SStream *O) { + uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); - // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && - // "Unexepected shift type!"); + // Prefer the default format for 16bit values, hex otherwise. + printImmSVE16(PrintVal, O); +} - // #0 lsl #8 is never pretty printed - if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { - printUInt32Bang(O, UnscaledVal); - printShifter(MI, OpNum + 1, O); - return; - } +static void printSVELogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) { + uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); - Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); - printImmSVE32(Val, O); + // Prefer the default format for 16bit values, hex otherwise. + if ((uint16_t)PrintVal == (uint32_t)PrintVal) + printImmSVE16(PrintVal, O); + else + printUInt64Bang(O, PrintVal); } -static void printImm8OptLsl64(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); - uint64_t Val; +static void printSVELogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) { + uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); - // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && - // "Unexepected shift type!"); + printImmSVE64(PrintVal, O); +} + +static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width) { + unsigned int Base, Reg; + + switch (Width) { + default: // llvm_unreachable("Unsupported width"); + case 8: + Base = AArch64_B0; + break; + case 16: + Base = AArch64_H0; + break; + case 32: + Base = AArch64_S0; + break; + case 64: + Base = AArch64_D0; + break; + case 128: + Base = AArch64_Q0; + break; + } + + Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + + SStream_concat0( + O, getRegisterName(Reg - AArch64_Z0 + Base, AArch64_NoRegAltName)); +} - // #0 lsl #8 is never pretty printed - if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { - printUInt32Bang(O, UnscaledVal); - printShifter(MI, OpNum + 1, O); - return; - } +static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, + unsigned ImmIs0, unsigned ImmIs1) { + const ExactFPImm *Imm0Desc = lookupExactFPImmByEnum(ImmIs0); + const ExactFPImm *Imm1Desc = lookupExactFPImmByEnum(ImmIs1); + unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); - printImmSVE64(Val, O); + SStream_concat0(O, Val ? Imm1Desc->Repr : Imm0Desc->Repr); } -static void printSVELogicalImm16(MCInst *MI, unsigned OpNum, SStream *O) -{ - uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); +static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - // Prefer the default format for 16bit values, hex otherwise. - printImmSVE16(PrintVal, O); + SStream_concat0(O, + getRegisterName(getWRegFromXReg(Reg), AArch64_NoRegAltName)); } -static void printSVELogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) -{ - uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); +static void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // Prefer the default format for 16bit values, hex otherwise. - if ((uint16_t)PrintVal == (uint32_t)PrintVal) - printImmSVE16(PrintVal, O); - else - printUInt64Bang(O, PrintVal); + // TODO lookup Gen + SStream_concat(O, "#%d", Val); } -static void printSVELogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) -{ - uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); +static void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Val = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, MCRegisterInfo_getSubReg(MI->MRI, Val, AArch64_x8sub_0)); +} - printImmSVE64(PrintVal, O); +static void printSImm(MCInst *MI, unsigned OpNum, SStream *O, int Size) { + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + if (Size == 8) + printInt32Bang(O, (signed char)Imm); + else if (Size == 16) + printInt32Bang(O, (signed short)Imm); + else + printInt64Bang(O, Imm); } -static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width) -{ - unsigned int Base, Reg; +static void printUnsignedImm(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + printInt64Bang(O, Imm); +} - switch (Width) { - default: // llvm_unreachable("Unsupported width"); - case 8: Base = AArch64_B0; break; - case 16: Base = AArch64_H0; break; - case 32: Base = AArch64_S0; break; - case 64: Base = AArch64_D0; break; - case 128: Base = AArch64_Q0; break; - } +static void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Imm = (MCOperand_getImm(MCInst_getOperand(MI, OpNum)) ^ 32) >> 1; - Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + // TODO lookup Gen + SStream_concat(O, "#%d", Imm); +} - SStream_concat0(O, getRegisterName(Reg - AArch64_Z0 + Base, AArch64_NoRegAltName)); +static void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + if (MCOperand_isReg(Op)) + SStream_concat0( + O, getRegisterName(MCOperand_getReg(Op), AArch64_NoRegAltName)); } -static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, unsigned ImmIs0, unsigned ImmIs1) -{ - const ExactFPImm *Imm0Desc = lookupExactFPImmByEnum(ImmIs0); - const ExactFPImm *Imm1Desc = lookupExactFPImmByEnum(ImmIs1); - unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); +static void printMatrixTileVector(MCInst *MI, unsigned OpNum, SStream *O, + bool IsVertical) { + const MCOperand *RegOp = MCInst_getOperand(MI, OpNum); + // assert(RegOp.isReg() && "Unexpected operand type!"); + const char *RegName = + getRegisterName(MCOperand_getReg(RegOp), AArch64_NoRegAltName); + + // Insert the horizontal/vertical flag before the suffix. + for (; *RegName != 0; RegName++) { + if (*RegName == '.') { + SStream_concat1(O, IsVertical ? 'v' : 'h'); + RegName++; + break; + } + SStream_concat1(O, *RegName); + } + SStream_concat0(O, RegName); +} - SStream_concat0(O, Val ? Imm1Desc->Repr : Imm0Desc->Repr); +static void printMatrixIndex(MCInst *MI, unsigned OpNum, SStream *O) { + SStream_concat(O, "%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum))); } -static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +static void printMatrix(MCInst *MI, unsigned OpNum, SStream *O, int EltSize) { + const MCOperand *RegOp = MCInst_getOperand(MI, OpNum); + + SStream_concat0( + O, getRegisterName(MCOperand_getReg(RegOp), AArch64_NoRegAltName)); + switch (EltSize) { + case 0: + break; + case 8: + SStream_concat0(O, ".b"); + break; + case 16: + SStream_concat0(O, ".h"); + break; + case 32: + SStream_concat0(O, ".s"); + break; + case 64: + SStream_concat0(O, ".d"); + break; + case 128: + SStream_concat0(O, ".q"); + break; + default: + llvm_unreachable("Unsupported element size"); + } +} - SStream_concat0(O, getRegisterName(getWRegFromXReg(Reg), AArch64_NoRegAltName)); +static const unsigned MatrixZADRegisterTable[] = { + AArch64_ZAD0, AArch64_ZAD1, AArch64_ZAD2, AArch64_ZAD3, + AArch64_ZAD4, AArch64_ZAD5, AArch64_ZAD6, AArch64_ZAD7}; + +static void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned MaxRegs = 8; + unsigned RegMask = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + unsigned NumRegs = 0; + for (unsigned I = 0; I < MaxRegs; ++I) + if ((RegMask & (1 << I)) != 0) + ++NumRegs; + + SStream_concat0(O, "{"); + unsigned Printed = 0; + for (unsigned I = 0; I < MaxRegs; ++I) { + unsigned Reg = RegMask & (1 << I); + if (Reg == 0) + continue; + SStream_concat0( + O, getRegisterName(MatrixZADRegisterTable[I], AArch64_NoRegAltName)); + if (Printed + 1 != NumRegs) + SStream_concat0(O, ", "); + ++Printed; + } + SStream_concat0(O, "}"); } -#define PRINT_ALIAS_INSTR -#include "AArch64GenAsmWriter.inc" -#include "AArch64GenRegisterName.inc" +struct SVCR { + char *Name; + unsigned Index; +}; + +const struct SVCR SVCRsList[] = { + {"SVCRSM", 0x1}, // 0 + {"SVCRZA", 0x2}, // 1 + {"SVCRSMZA", 0x3}, // 2 +}; + +static void printSVCROp(const MCInst *MI, unsigned OpNum, SStream *O) { + const MCOperand *MO = MCInst_getOperand(MI, OpNum); + unsigned svcrop = MCOperand_getImm(MO); + for (int i = 0; i < ARR_SIZE(SVCRsList); i++) { + if (SVCRsList[i].Index == svcrop) { + SStream_concat0(O, SVCRsList[i].Name); + return; + } + } + assert(1 && "Unexpected SVCR operand!"); +} -void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci) -{ - if (((cs_struct *)handle)->detail != CS_OPT_ON) - return; - - if (mci->csh->detail) { - unsigned opcode = MCInst_getOpcode(mci); - - switch (opcode) { - default: - break; - case AArch64_LD1Fourv16b_POST: - case AArch64_LD1Fourv1d_POST: - case AArch64_LD1Fourv2d_POST: - case AArch64_LD1Fourv2s_POST: - case AArch64_LD1Fourv4h_POST: - case AArch64_LD1Fourv4s_POST: - case AArch64_LD1Fourv8b_POST: - case AArch64_LD1Fourv8h_POST: - case AArch64_LD1Onev16b_POST: - case AArch64_LD1Onev1d_POST: - case AArch64_LD1Onev2d_POST: - case AArch64_LD1Onev2s_POST: - case AArch64_LD1Onev4h_POST: - case AArch64_LD1Onev4s_POST: - case AArch64_LD1Onev8b_POST: - case AArch64_LD1Onev8h_POST: - case AArch64_LD1Rv16b_POST: - case AArch64_LD1Rv1d_POST: - case AArch64_LD1Rv2d_POST: - case AArch64_LD1Rv2s_POST: - case AArch64_LD1Rv4h_POST: - case AArch64_LD1Rv4s_POST: - case AArch64_LD1Rv8b_POST: - case AArch64_LD1Rv8h_POST: - case AArch64_LD1Threev16b_POST: - case AArch64_LD1Threev1d_POST: - case AArch64_LD1Threev2d_POST: - case AArch64_LD1Threev2s_POST: - case AArch64_LD1Threev4h_POST: - case AArch64_LD1Threev4s_POST: - case AArch64_LD1Threev8b_POST: - case AArch64_LD1Threev8h_POST: - case AArch64_LD1Twov16b_POST: - case AArch64_LD1Twov1d_POST: - case AArch64_LD1Twov2d_POST: - case AArch64_LD1Twov2s_POST: - case AArch64_LD1Twov4h_POST: - case AArch64_LD1Twov4s_POST: - case AArch64_LD1Twov8b_POST: - case AArch64_LD1Twov8h_POST: - case AArch64_LD1i16_POST: - case AArch64_LD1i32_POST: - case AArch64_LD1i64_POST: - case AArch64_LD1i8_POST: - case AArch64_LD2Rv16b_POST: - case AArch64_LD2Rv1d_POST: - case AArch64_LD2Rv2d_POST: - case AArch64_LD2Rv2s_POST: - case AArch64_LD2Rv4h_POST: - case AArch64_LD2Rv4s_POST: - case AArch64_LD2Rv8b_POST: - case AArch64_LD2Rv8h_POST: - case AArch64_LD2Twov16b_POST: - case AArch64_LD2Twov2d_POST: - case AArch64_LD2Twov2s_POST: - case AArch64_LD2Twov4h_POST: - case AArch64_LD2Twov4s_POST: - case AArch64_LD2Twov8b_POST: - case AArch64_LD2Twov8h_POST: - case AArch64_LD2i16_POST: - case AArch64_LD2i32_POST: - case AArch64_LD2i64_POST: - case AArch64_LD2i8_POST: - case AArch64_LD3Rv16b_POST: - case AArch64_LD3Rv1d_POST: - case AArch64_LD3Rv2d_POST: - case AArch64_LD3Rv2s_POST: - case AArch64_LD3Rv4h_POST: - case AArch64_LD3Rv4s_POST: - case AArch64_LD3Rv8b_POST: - case AArch64_LD3Rv8h_POST: - case AArch64_LD3Threev16b_POST: - case AArch64_LD3Threev2d_POST: - case AArch64_LD3Threev2s_POST: - case AArch64_LD3Threev4h_POST: - case AArch64_LD3Threev4s_POST: - case AArch64_LD3Threev8b_POST: - case AArch64_LD3Threev8h_POST: - case AArch64_LD3i16_POST: - case AArch64_LD3i32_POST: - case AArch64_LD3i64_POST: - case AArch64_LD3i8_POST: - case AArch64_LD4Fourv16b_POST: - case AArch64_LD4Fourv2d_POST: - case AArch64_LD4Fourv2s_POST: - case AArch64_LD4Fourv4h_POST: - case AArch64_LD4Fourv4s_POST: - case AArch64_LD4Fourv8b_POST: - case AArch64_LD4Fourv8h_POST: - case AArch64_LD4Rv16b_POST: - case AArch64_LD4Rv1d_POST: - case AArch64_LD4Rv2d_POST: - case AArch64_LD4Rv2s_POST: - case AArch64_LD4Rv4h_POST: - case AArch64_LD4Rv4s_POST: - case AArch64_LD4Rv8b_POST: - case AArch64_LD4Rv8h_POST: - case AArch64_LD4i16_POST: - case AArch64_LD4i32_POST: - case AArch64_LD4i64_POST: - case AArch64_LD4i8_POST: - case AArch64_LDPDpost: - case AArch64_LDPDpre: - case AArch64_LDPQpost: - case AArch64_LDPQpre: - case AArch64_LDPSWpost: - case AArch64_LDPSWpre: - case AArch64_LDPSpost: - case AArch64_LDPSpre: - case AArch64_LDPWpost: - case AArch64_LDPWpre: - case AArch64_LDPXpost: - case AArch64_LDPXpre: - case AArch64_LDRBBpost: - case AArch64_LDRBBpre: - case AArch64_LDRBpost: - case AArch64_LDRBpre: - case AArch64_LDRDpost: - case AArch64_LDRDpre: - case AArch64_LDRHHpost: - case AArch64_LDRHHpre: - case AArch64_LDRHpost: - case AArch64_LDRHpre: - case AArch64_LDRQpost: - case AArch64_LDRQpre: - case AArch64_LDRSBWpost: - case AArch64_LDRSBWpre: - case AArch64_LDRSBXpost: - case AArch64_LDRSBXpre: - case AArch64_LDRSHWpost: - case AArch64_LDRSHWpre: - case AArch64_LDRSHXpost: - case AArch64_LDRSHXpre: - case AArch64_LDRSWpost: - case AArch64_LDRSWpre: - case AArch64_LDRSpost: - case AArch64_LDRSpre: - case AArch64_LDRWpost: - case AArch64_LDRWpre: - case AArch64_LDRXpost: - case AArch64_LDRXpre: - case AArch64_ST1Fourv16b_POST: - case AArch64_ST1Fourv1d_POST: - case AArch64_ST1Fourv2d_POST: - case AArch64_ST1Fourv2s_POST: - case AArch64_ST1Fourv4h_POST: - case AArch64_ST1Fourv4s_POST: - case AArch64_ST1Fourv8b_POST: - case AArch64_ST1Fourv8h_POST: - case AArch64_ST1Onev16b_POST: - case AArch64_ST1Onev1d_POST: - case AArch64_ST1Onev2d_POST: - case AArch64_ST1Onev2s_POST: - case AArch64_ST1Onev4h_POST: - case AArch64_ST1Onev4s_POST: - case AArch64_ST1Onev8b_POST: - case AArch64_ST1Onev8h_POST: - case AArch64_ST1Threev16b_POST: - case AArch64_ST1Threev1d_POST: - case AArch64_ST1Threev2d_POST: - case AArch64_ST1Threev2s_POST: - case AArch64_ST1Threev4h_POST: - case AArch64_ST1Threev4s_POST: - case AArch64_ST1Threev8b_POST: - case AArch64_ST1Threev8h_POST: - case AArch64_ST1Twov16b_POST: - case AArch64_ST1Twov1d_POST: - case AArch64_ST1Twov2d_POST: - case AArch64_ST1Twov2s_POST: - case AArch64_ST1Twov4h_POST: - case AArch64_ST1Twov4s_POST: - case AArch64_ST1Twov8b_POST: - case AArch64_ST1Twov8h_POST: - case AArch64_ST1i16_POST: - case AArch64_ST1i32_POST: - case AArch64_ST1i64_POST: - case AArch64_ST1i8_POST: - case AArch64_ST2Twov16b_POST: - case AArch64_ST2Twov2d_POST: - case AArch64_ST2Twov2s_POST: - case AArch64_ST2Twov4h_POST: - case AArch64_ST2Twov4s_POST: - case AArch64_ST2Twov8b_POST: - case AArch64_ST2Twov8h_POST: - case AArch64_ST2i16_POST: - case AArch64_ST2i32_POST: - case AArch64_ST2i64_POST: - case AArch64_ST2i8_POST: - case AArch64_ST3Threev16b_POST: - case AArch64_ST3Threev2d_POST: - case AArch64_ST3Threev2s_POST: - case AArch64_ST3Threev4h_POST: - case AArch64_ST3Threev4s_POST: - case AArch64_ST3Threev8b_POST: - case AArch64_ST3Threev8h_POST: - case AArch64_ST3i16_POST: - case AArch64_ST3i32_POST: - case AArch64_ST3i64_POST: - case AArch64_ST3i8_POST: - case AArch64_ST4Fourv16b_POST: - case AArch64_ST4Fourv2d_POST: - case AArch64_ST4Fourv2s_POST: - case AArch64_ST4Fourv4h_POST: - case AArch64_ST4Fourv4s_POST: - case AArch64_ST4Fourv8b_POST: - case AArch64_ST4Fourv8h_POST: - case AArch64_ST4i16_POST: - case AArch64_ST4i32_POST: - case AArch64_ST4i64_POST: - case AArch64_ST4i8_POST: - case AArch64_STPDpost: - case AArch64_STPDpre: - case AArch64_STPQpost: - case AArch64_STPQpre: - case AArch64_STPSpost: - case AArch64_STPSpre: - case AArch64_STPWpost: - case AArch64_STPWpre: - case AArch64_STPXpost: - case AArch64_STPXpre: - case AArch64_STRBBpost: - case AArch64_STRBBpre: - case AArch64_STRBpost: - case AArch64_STRBpre: - case AArch64_STRDpost: - case AArch64_STRDpre: - case AArch64_STRHHpost: - case AArch64_STRHHpre: - case AArch64_STRHpost: - case AArch64_STRHpre: - case AArch64_STRQpost: - case AArch64_STRQpre: - case AArch64_STRSpost: - case AArch64_STRSpre: - case AArch64_STRWpost: - case AArch64_STRWpre: - case AArch64_STRXpost: - case AArch64_STRXpre: - flat_insn->detail->arm64.writeback = true; - break; - } - } +void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, + MCInst *mci) { + if (((cs_struct *)handle)->detail != CS_OPT_ON) + return; + + if (mci->csh->detail) { + unsigned opcode = MCInst_getOpcode(mci); + + switch (opcode) { + default: + break; + case AArch64_LD1Fourv16b_POST: + case AArch64_LD1Fourv1d_POST: + case AArch64_LD1Fourv2d_POST: + case AArch64_LD1Fourv2s_POST: + case AArch64_LD1Fourv4h_POST: + case AArch64_LD1Fourv4s_POST: + case AArch64_LD1Fourv8b_POST: + case AArch64_LD1Fourv8h_POST: + case AArch64_LD1Onev16b_POST: + case AArch64_LD1Onev1d_POST: + case AArch64_LD1Onev2d_POST: + case AArch64_LD1Onev2s_POST: + case AArch64_LD1Onev4h_POST: + case AArch64_LD1Onev4s_POST: + case AArch64_LD1Onev8b_POST: + case AArch64_LD1Onev8h_POST: + case AArch64_LD1Rv16b_POST: + case AArch64_LD1Rv1d_POST: + case AArch64_LD1Rv2d_POST: + case AArch64_LD1Rv2s_POST: + case AArch64_LD1Rv4h_POST: + case AArch64_LD1Rv4s_POST: + case AArch64_LD1Rv8b_POST: + case AArch64_LD1Rv8h_POST: + case AArch64_LD1Threev16b_POST: + case AArch64_LD1Threev1d_POST: + case AArch64_LD1Threev2d_POST: + case AArch64_LD1Threev2s_POST: + case AArch64_LD1Threev4h_POST: + case AArch64_LD1Threev4s_POST: + case AArch64_LD1Threev8b_POST: + case AArch64_LD1Threev8h_POST: + case AArch64_LD1Twov16b_POST: + case AArch64_LD1Twov1d_POST: + case AArch64_LD1Twov2d_POST: + case AArch64_LD1Twov2s_POST: + case AArch64_LD1Twov4h_POST: + case AArch64_LD1Twov4s_POST: + case AArch64_LD1Twov8b_POST: + case AArch64_LD1Twov8h_POST: + case AArch64_LD1i16_POST: + case AArch64_LD1i32_POST: + case AArch64_LD1i64_POST: + case AArch64_LD1i8_POST: + case AArch64_LD2Rv16b_POST: + case AArch64_LD2Rv1d_POST: + case AArch64_LD2Rv2d_POST: + case AArch64_LD2Rv2s_POST: + case AArch64_LD2Rv4h_POST: + case AArch64_LD2Rv4s_POST: + case AArch64_LD2Rv8b_POST: + case AArch64_LD2Rv8h_POST: + case AArch64_LD2Twov16b_POST: + case AArch64_LD2Twov2d_POST: + case AArch64_LD2Twov2s_POST: + case AArch64_LD2Twov4h_POST: + case AArch64_LD2Twov4s_POST: + case AArch64_LD2Twov8b_POST: + case AArch64_LD2Twov8h_POST: + case AArch64_LD2i16_POST: + case AArch64_LD2i32_POST: + case AArch64_LD2i64_POST: + case AArch64_LD2i8_POST: + case AArch64_LD3Rv16b_POST: + case AArch64_LD3Rv1d_POST: + case AArch64_LD3Rv2d_POST: + case AArch64_LD3Rv2s_POST: + case AArch64_LD3Rv4h_POST: + case AArch64_LD3Rv4s_POST: + case AArch64_LD3Rv8b_POST: + case AArch64_LD3Rv8h_POST: + case AArch64_LD3Threev16b_POST: + case AArch64_LD3Threev2d_POST: + case AArch64_LD3Threev2s_POST: + case AArch64_LD3Threev4h_POST: + case AArch64_LD3Threev4s_POST: + case AArch64_LD3Threev8b_POST: + case AArch64_LD3Threev8h_POST: + case AArch64_LD3i16_POST: + case AArch64_LD3i32_POST: + case AArch64_LD3i64_POST: + case AArch64_LD3i8_POST: + case AArch64_LD4Fourv16b_POST: + case AArch64_LD4Fourv2d_POST: + case AArch64_LD4Fourv2s_POST: + case AArch64_LD4Fourv4h_POST: + case AArch64_LD4Fourv4s_POST: + case AArch64_LD4Fourv8b_POST: + case AArch64_LD4Fourv8h_POST: + case AArch64_LD4Rv16b_POST: + case AArch64_LD4Rv1d_POST: + case AArch64_LD4Rv2d_POST: + case AArch64_LD4Rv2s_POST: + case AArch64_LD4Rv4h_POST: + case AArch64_LD4Rv4s_POST: + case AArch64_LD4Rv8b_POST: + case AArch64_LD4Rv8h_POST: + case AArch64_LD4i16_POST: + case AArch64_LD4i32_POST: + case AArch64_LD4i64_POST: + case AArch64_LD4i8_POST: + case AArch64_LDPDpost: + case AArch64_LDPDpre: + case AArch64_LDPQpost: + case AArch64_LDPQpre: + case AArch64_LDPSWpost: + case AArch64_LDPSWpre: + case AArch64_LDPSpost: + case AArch64_LDPSpre: + case AArch64_LDPWpost: + case AArch64_LDPWpre: + case AArch64_LDPXpost: + case AArch64_LDPXpre: + case AArch64_LDRBBpost: + case AArch64_LDRBBpre: + case AArch64_LDRBpost: + case AArch64_LDRBpre: + case AArch64_LDRDpost: + case AArch64_LDRDpre: + case AArch64_LDRHHpost: + case AArch64_LDRHHpre: + case AArch64_LDRHpost: + case AArch64_LDRHpre: + case AArch64_LDRQpost: + case AArch64_LDRQpre: + case AArch64_LDRSBWpost: + case AArch64_LDRSBWpre: + case AArch64_LDRSBXpost: + case AArch64_LDRSBXpre: + case AArch64_LDRSHWpost: + case AArch64_LDRSHWpre: + case AArch64_LDRSHXpost: + case AArch64_LDRSHXpre: + case AArch64_LDRSWpost: + case AArch64_LDRSWpre: + case AArch64_LDRSpost: + case AArch64_LDRSpre: + case AArch64_LDRWpost: + case AArch64_LDRWpre: + case AArch64_LDRXpost: + case AArch64_LDRXpre: + case AArch64_ST1Fourv16b_POST: + case AArch64_ST1Fourv1d_POST: + case AArch64_ST1Fourv2d_POST: + case AArch64_ST1Fourv2s_POST: + case AArch64_ST1Fourv4h_POST: + case AArch64_ST1Fourv4s_POST: + case AArch64_ST1Fourv8b_POST: + case AArch64_ST1Fourv8h_POST: + case AArch64_ST1Onev16b_POST: + case AArch64_ST1Onev1d_POST: + case AArch64_ST1Onev2d_POST: + case AArch64_ST1Onev2s_POST: + case AArch64_ST1Onev4h_POST: + case AArch64_ST1Onev4s_POST: + case AArch64_ST1Onev8b_POST: + case AArch64_ST1Onev8h_POST: + case AArch64_ST1Threev16b_POST: + case AArch64_ST1Threev1d_POST: + case AArch64_ST1Threev2d_POST: + case AArch64_ST1Threev2s_POST: + case AArch64_ST1Threev4h_POST: + case AArch64_ST1Threev4s_POST: + case AArch64_ST1Threev8b_POST: + case AArch64_ST1Threev8h_POST: + case AArch64_ST1Twov16b_POST: + case AArch64_ST1Twov1d_POST: + case AArch64_ST1Twov2d_POST: + case AArch64_ST1Twov2s_POST: + case AArch64_ST1Twov4h_POST: + case AArch64_ST1Twov4s_POST: + case AArch64_ST1Twov8b_POST: + case AArch64_ST1Twov8h_POST: + case AArch64_ST1i16_POST: + case AArch64_ST1i32_POST: + case AArch64_ST1i64_POST: + case AArch64_ST1i8_POST: + case AArch64_ST2Twov16b_POST: + case AArch64_ST2Twov2d_POST: + case AArch64_ST2Twov2s_POST: + case AArch64_ST2Twov4h_POST: + case AArch64_ST2Twov4s_POST: + case AArch64_ST2Twov8b_POST: + case AArch64_ST2Twov8h_POST: + case AArch64_ST2i16_POST: + case AArch64_ST2i32_POST: + case AArch64_ST2i64_POST: + case AArch64_ST2i8_POST: + case AArch64_ST3Threev16b_POST: + case AArch64_ST3Threev2d_POST: + case AArch64_ST3Threev2s_POST: + case AArch64_ST3Threev4h_POST: + case AArch64_ST3Threev4s_POST: + case AArch64_ST3Threev8b_POST: + case AArch64_ST3Threev8h_POST: + case AArch64_ST3i16_POST: + case AArch64_ST3i32_POST: + case AArch64_ST3i64_POST: + case AArch64_ST3i8_POST: + case AArch64_ST4Fourv16b_POST: + case AArch64_ST4Fourv2d_POST: + case AArch64_ST4Fourv2s_POST: + case AArch64_ST4Fourv4h_POST: + case AArch64_ST4Fourv4s_POST: + case AArch64_ST4Fourv8b_POST: + case AArch64_ST4Fourv8h_POST: + case AArch64_ST4i16_POST: + case AArch64_ST4i32_POST: + case AArch64_ST4i64_POST: + case AArch64_ST4i8_POST: + case AArch64_STPDpost: + case AArch64_STPDpre: + case AArch64_STPQpost: + case AArch64_STPQpre: + case AArch64_STPSpost: + case AArch64_STPSpre: + case AArch64_STPWpost: + case AArch64_STPWpre: + case AArch64_STPXpost: + case AArch64_STPXpre: + case AArch64_STRBBpost: + case AArch64_STRBBpre: + case AArch64_STRBpost: + case AArch64_STRBpre: + case AArch64_STRDpost: + case AArch64_STRDpre: + case AArch64_STRHHpost: + case AArch64_STRHHpre: + case AArch64_STRHpost: + case AArch64_STRHpre: + case AArch64_STRQpost: + case AArch64_STRQpre: + case AArch64_STRSpost: + case AArch64_STRSpre: + case AArch64_STRWpost: + case AArch64_STRWpre: + case AArch64_STRXpost: + case AArch64_STRXpre: + flat_insn->detail->arm64.writeback = true; + break; + } + } } #endif diff --git a/arch/AArch64/AArch64InstPrinter.h b/arch/AArch64/AArch64InstPrinter.h index 97c0307c4e..31b4910b91 100644 --- a/arch/AArch64/AArch64InstPrinter.h +++ b/arch/AArch64/AArch64InstPrinter.h @@ -23,6 +23,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *); -void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci); +void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, + MCInst *mci); #endif diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index 442461dfed..6aa7022e83 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -3,7 +3,7 @@ #ifdef CAPSTONE_HAS_ARM64 -#include // debug +#include // debug #include #include "../../utils.h" @@ -11,589 +11,318 @@ #include "AArch64Mapping.h" #define GET_INSTRINFO_ENUM -#include "AArch64GenInstrInfo.inc" +#include "AArch64GenDisassemblerTables.inc" #ifndef CAPSTONE_DIET // NOTE: this reg_name_maps[] reflects the order of registers in arm64_reg -static const char * const reg_name_maps[] = { - NULL, /* ARM64_REG_INVALID */ - - "ffr", - "fp", - "lr", - "nzcv", - "sp", - "wsp", - "wzr", - "xzr", - - "b0", - "b1", - "b2", - "b3", - "b4", - "b5", - "b6", - "b7", - "b8", - "b9", - "b10", - "b11", - "b12", - "b13", - "b14", - "b15", - "b16", - "b17", - "b18", - "b19", - "b20", - "b21", - "b22", - "b23", - "b24", - "b25", - "b26", - "b27", - "b28", - "b29", - "b30", - "b31", - - "d0", - "d1", - "d2", - "d3", - "d4", - "d5", - "d6", - "d7", - "d8", - "d9", - "d10", - "d11", - "d12", - "d13", - "d14", - "d15", - "d16", - "d17", - "d18", - "d19", - "d20", - "d21", - "d22", - "d23", - "d24", - "d25", - "d26", - "d27", - "d28", - "d29", - "d30", - "d31", - - "h0", - "h1", - "h2", - "h3", - "h4", - "h5", - "h6", - "h7", - "h8", - "h9", - "h10", - "h11", - "h12", - "h13", - "h14", - "h15", - "h16", - "h17", - "h18", - "h19", - "h20", - "h21", - "h22", - "h23", - "h24", - "h25", - "h26", - "h27", - "h28", - "h29", - "h30", - "h31", - - "p0", - "p1", - "p2", - "p3", - "p4", - "p5", - "p6", - "p7", - "p8", - "p9", - "p10", - "p11", - "p12", - "p13", - "p14", - "p15", - - "q0", - "q1", - "q2", - "q3", - "q4", - "q5", - "q6", - "q7", - "q8", - "q9", - "q10", - "q11", - "q12", - "q13", - "q14", - "q15", - "q16", - "q17", - "q18", - "q19", - "q20", - "q21", - "q22", - "q23", - "q24", - "q25", - "q26", - "q27", - "q28", - "q29", - "q30", - "q31", - "s0", - "s1", - "s2", - "s3", - "s4", - "s5", - "s6", - "s7", - "s8", - "s9", - "s10", - "s11", - "s12", - "s13", - "s14", - "s15", - "s16", - "s17", - "s18", - "s19", - "s20", - "s21", - "s22", - "s23", - "s24", - "s25", - "s26", - "s27", - "s28", - "s29", - "s30", - "s31", - - "w0", - "w1", - "w2", - "w3", - "w4", - "w5", - "w6", - "w7", - "w8", - "w9", - "w10", - "w11", - "w12", - "w13", - "w14", - "w15", - "w16", - "w17", - "w18", - "w19", - "w20", - "w21", - "w22", - "w23", - "w24", - "w25", - "w26", - "w27", - "w28", - "w29", - "w30", - - "x0", - "x1", - "x2", - "x3", - "x4", - "x5", - "x6", - "x7", - "x8", - "x9", - "x10", - "x11", - "x12", - "x13", - "x14", - "x15", - "x16", - "x17", - "x18", - "x19", - "x20", - "x21", - "x22", - "x23", - "x24", - "x25", - "x26", - "x27", - "x28", - - "z0", - "z1", - "z2", - "z3", - "z4", - "z5", - "z6", - "z7", - "z8", - "z9", - "z10", - "z11", - "z12", - "z13", - "z14", - "z15", - "z16", - "z17", - "z18", - "z19", - "z20", - "z21", - "z22", - "z23", - "z24", - "z25", - "z26", - "z27", - "z28", - "z29", - "z30", - "z31", - - "v0", - "v1", - "v2", - "v3", - "v4", - "v5", - "v6", - "v7", - "v8", - "v9", - "v10", - "v11", - "v12", - "v13", - "v14", - "v15", - "v16", - "v17", - "v18", - "v19", - "v20", - "v21", - "v22", - "v23", - "v24", - "v25", - "v26", - "v27", - "v28", - "v29", - "v30", - "v31", +static const char *const reg_name_maps[] = { + NULL, /* ARM64_REG_INVALID */ + + "ffr", "fp", "lr", "nzcv", "sp", "vg", "wsp", "wzr", "xzr", "za", + + "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", "b8", "b9", + "b10", "b11", "b12", "b13", "b14", "b15", "b16", "b17", "b18", "b19", + "b20", "b21", "b22", "b23", "b24", "b25", "b26", "b27", "b28", "b29", + "b30", "b31", + + "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", + "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", + "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", + "d30", "d31", + + "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", "h8", "h9", + "h10", "h11", "h12", "h13", "h14", "h15", "h16", "h17", "h18", "h19", + "h20", "h21", "h22", "h23", "h24", "h25", "h26", "h27", "h28", "h29", + "h30", "h31", + + "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", + "p10", "p11", "p12", "p13", "p14", "p15", + + "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", + "q10", "q11", "q12", "q13", "q14", "q15", "q16", "q17", "q18", "q19", + "q20", "q21", "q22", "q23", "q24", "q25", "q26", "q27", "q28", "q29", + "q30", "q31", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", + "s18", "s19", "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", + "s28", "s29", "s30", "s31", + + "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", + "w10", "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", + "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", + "w30", + + "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", + "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", + "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", + + "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", + "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", + "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", + "z30", "z31", + + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", + "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", + "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", + "v30", "v31", }; #endif -const char *AArch64_reg_name(csh handle, unsigned int reg) -{ +const char *AArch64_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; - - return reg_name_maps[reg]; + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + return reg_name_maps[reg]; #else - return NULL; + return NULL; #endif } static const insn_map insns[] = { - // dummy item - { - 0, 0, + // dummy item + {0, + 0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif - }, + }, #include "AArch64MappingInsn.inc" }; // given internal insn id, return public instruction info -void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) -{ - int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; +void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { + int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; - if (h->detail) { + if (h->detail) { #ifndef CAPSTONE_DIET - cs_struct handle; - handle.detail = h->detail; + cs_struct handle; + handle.detail = h->detail; - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + memcpy(insn->detail->regs_read, insns[i].regs_use, + sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = + (uint8_t)count_positive(insns[i].regs_use); - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + memcpy(insn->detail->regs_write, insns[i].regs_mod, + sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = + (uint8_t)count_positive(insns[i].regs_mod); - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV); + insn->detail->arm64.update_flags = + cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV); #endif - } - } + } + } } -static const char * const insn_name_maps[] = { - NULL, // ARM64_INS_INVALID +static const char *const insn_name_maps[] = { + NULL, // ARM64_INS_INVALID #include "AArch64MappingInsnName.inc" - "sbfiz", - "ubfiz", - "sbfx", - "ubfx", - "bfi", - "bfxil", - "ic", - "dc", - "at", - "tlbi", + "sbfiz", "ubfiz", "sbfx", "ubfx", "bfi", "bfxil", "ic", "dc", "at", "tlbi", }; -const char *AArch64_insn_name(csh handle, unsigned int id) -{ +const char *AArch64_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - if (id >= ARM64_INS_ENDING) - return NULL; + if (id >= ARM64_INS_ENDING) + return NULL; - if (id < ARR_SIZE(insn_name_maps)) - return insn_name_maps[id]; + if (id < ARR_SIZE(insn_name_maps)) + return insn_name_maps[id]; - // not found - return NULL; + // not found + return NULL; #else - return NULL; + return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { - // generic groups - { ARM64_GRP_INVALID, NULL }, - { ARM64_GRP_JUMP, "jump" }, - { ARM64_GRP_CALL, "call" }, - { ARM64_GRP_RET, "return" }, - { ARM64_GRP_PRIVILEGE, "privilege" }, - { ARM64_GRP_INT, "int" }, - { ARM64_GRP_BRANCH_RELATIVE, "branch_relative" }, - { ARM64_GRP_PAC, "pointer authentication" }, - - // architecture-specific groups - { ARM64_GRP_CRYPTO, "crypto" }, - { ARM64_GRP_FPARMV8, "fparmv8" }, - { ARM64_GRP_NEON, "neon" }, - { ARM64_GRP_CRC, "crc" }, - - { ARM64_GRP_AES, "aes" }, - { ARM64_GRP_DOTPROD, "dotprod" }, - { ARM64_GRP_FULLFP16, "fullfp16" }, - { ARM64_GRP_LSE, "lse" }, - { ARM64_GRP_RCPC, "rcpc" }, - { ARM64_GRP_RDM, "rdm" }, - { ARM64_GRP_SHA2, "sha2" }, - { ARM64_GRP_SHA3, "sha3" }, - { ARM64_GRP_SM4, "sm4" }, - { ARM64_GRP_SVE, "sve" }, - { ARM64_GRP_V8_1A, "v8_1a" }, - { ARM64_GRP_V8_3A, "v8_3a" }, - { ARM64_GRP_V8_4A, "v8_4a" }, + // generic groups + {ARM64_GRP_INVALID, NULL}, + {ARM64_GRP_JUMP, "jump"}, + {ARM64_GRP_CALL, "call"}, + {ARM64_GRP_RET, "return"}, + {ARM64_GRP_PRIVILEGE, "privilege"}, + {ARM64_GRP_INT, "int"}, + {ARM64_GRP_BRANCH_RELATIVE, "branch_relative"}, + {ARM64_GRP_PAC, "pointer authentication"}, + + // architecture-specific groups + {ARM64_GRP_CRYPTO, "crypto"}, + {ARM64_GRP_FPARMV8, "fparmv8"}, + {ARM64_GRP_NEON, "neon"}, + {ARM64_GRP_CRC, "crc"}, + + {ARM64_GRP_AES, "aes"}, + {ARM64_GRP_DOTPROD, "dotprod"}, + {ARM64_GRP_FULLFP16, "fullfp16"}, + {ARM64_GRP_LSE, "lse"}, + {ARM64_GRP_RCPC, "rcpc"}, + {ARM64_GRP_RDM, "rdm"}, + {ARM64_GRP_SHA2, "sha2"}, + {ARM64_GRP_SHA3, "sha3"}, + {ARM64_GRP_SM4, "sm4"}, + {ARM64_GRP_SVE, "sve"}, + {ARM64_GRP_V8_1A, "v8_1a"}, + {ARM64_GRP_V8_3A, "v8_3a"}, + {ARM64_GRP_V8_4A, "v8_4a"}, }; #endif -const char *AArch64_group_name(csh handle, unsigned int id) -{ +const char *AArch64_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else - return NULL; + return NULL; #endif } // map instruction name to public instruction ID -arm64_insn AArch64_map_insn(const char *name) -{ - unsigned int i; +arm64_insn AArch64_map_insn(const char *name) { + unsigned int i; - for(i = 1; i < ARR_SIZE(insn_name_maps); i++) { - if (!strcmp(name, insn_name_maps[i])) - return i; - } + for (i = 1; i < ARR_SIZE(insn_name_maps); i++) { + if (!strcmp(name, insn_name_maps[i])) + return i; + } - // not found - return ARM64_INS_INVALID; + // not found + return ARM64_INS_INVALID; } // map internal raw vregister to 'public' register -arm64_reg AArch64_map_vregister(unsigned int r) -{ - static const unsigned short RegAsmOffsetvreg[] = { +arm64_reg AArch64_map_vregister(unsigned int r) { + static const unsigned short RegAsmOffsetvreg[] = { #include "AArch64GenRegisterV.inc" - }; + }; - if (r < ARR_SIZE(RegAsmOffsetvreg)) - return RegAsmOffsetvreg[r - 1]; + if (r < ARR_SIZE(RegAsmOffsetvreg)) + return RegAsmOffsetvreg[r - 1]; - // cannot find this register - return 0; + // cannot find this register + return 0; } -void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vas = sp; - } +void arm64_op_addVectorArrSpecifier(MCInst *MI, int sp) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm64 + .operands[MI->flat_insn->detail->arm64.op_count - 1] + .vas = sp; + } } -void arm64_op_addFP(MCInst *MI, float fp) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = fp; - MI->flat_insn->detail->arm64.op_count++; - } +void arm64_op_addFP(MCInst *MI, float fp) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_FP; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .fp = fp; + MI->flat_insn->detail->arm64.op_count++; + } } -void arm64_op_addImm(MCInst *MI, int64_t imm) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)imm; - MI->flat_insn->detail->arm64.op_count++; - } +void arm64_op_addImm(MCInst *MI, int64_t imm) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count] + .imm = (int)imm; + MI->flat_insn->detail->arm64.op_count++; + } } #ifndef CAPSTONE_DIET // map instruction to its characteristics typedef struct insn_op { - unsigned int eflags_update; // how this instruction update status flags - uint8_t access[5]; + unsigned int eflags_update; // how this instruction update status flags + uint8_t access[5]; } insn_op; static const insn_op insn_ops[] = { - { - /* NULL item */ - 0, { 0 } - }, + {/* NULL item */ + 0, + {0}}, #include "AArch64MappingInsnOp.inc" }; // given internal insn id, return operand access info -const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id) -{ - int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - return insn_ops[i].access; - } - - return NULL; +const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id) { + int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + return insn_ops[i].access; + } + + return NULL; } -void AArch64_reg_access(const cs_insn *insn, - cs_regs regs_read, uint8_t *regs_read_count, - cs_regs regs_write, uint8_t *regs_write_count) -{ - uint8_t i; - uint8_t read_count, write_count; - cs_arm64 *arm64 = &(insn->detail->arm64); - - read_count = insn->detail->regs_read_count; - write_count = insn->detail->regs_write_count; - - // implicit registers - memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); - memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); - - // explicit registers - for (i = 0; i < arm64->op_count; i++) { - cs_arm64_op *op = &(arm64->operands[i]); - switch((int)op->type) { - case ARM64_OP_REG: - if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { - regs_read[read_count] = (uint16_t)op->reg; - read_count++; - } - if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { - regs_write[write_count] = (uint16_t)op->reg; - write_count++; - } - break; - case ARM_OP_MEM: - // registers appeared in memory references always being read - if ((op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { - regs_read[read_count] = (uint16_t)op->mem.base; - read_count++; - } - if ((op->mem.index != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { - regs_read[read_count] = (uint16_t)op->mem.index; - read_count++; - } - if ((arm64->writeback) && (op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) { - regs_write[write_count] = (uint16_t)op->mem.base; - write_count++; - } - default: - break; - } - } - - *regs_read_count = read_count; - *regs_write_count = write_count; +void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count) { + uint8_t i; + uint8_t read_count, write_count; + cs_arm64 *arm64 = &(insn->detail->arm64); + + read_count = insn->detail->regs_read_count; + write_count = insn->detail->regs_write_count; + + // implicit registers + memcpy(regs_read, insn->detail->regs_read, + read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, + write_count * sizeof(insn->detail->regs_write[0])); + + // explicit registers + for (i = 0; i < arm64->op_count; i++) { + cs_arm64_op *op = &(arm64->operands[i]); + switch ((int)op->type) { + case ARM64_OP_REG: + if ((op->access & CS_AC_READ) && + !arr_exist(regs_read, read_count, op->reg)) { + regs_read[read_count] = (uint16_t)op->reg; + read_count++; + } + if ((op->access & CS_AC_WRITE) && + !arr_exist(regs_write, write_count, op->reg)) { + regs_write[write_count] = (uint16_t)op->reg; + write_count++; + } + break; + case ARM_OP_MEM: + // registers appeared in memory references always being read + if ((op->mem.base != ARM64_REG_INVALID) && + !arr_exist(regs_read, read_count, op->mem.base)) { + regs_read[read_count] = (uint16_t)op->mem.base; + read_count++; + } + if ((op->mem.index != ARM64_REG_INVALID) && + !arr_exist(regs_read, read_count, op->mem.index)) { + regs_read[read_count] = (uint16_t)op->mem.index; + read_count++; + } + if ((arm64->writeback) && (op->mem.base != ARM64_REG_INVALID) && + !arr_exist(regs_write, write_count, op->mem.base)) { + regs_write[write_count] = (uint16_t)op->mem.base; + write_count++; + } + default: + break; + } + } + + *regs_read_count = read_count; + *regs_write_count = write_count; } #endif diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h index a8eda4f899..f6f475af2e 100644 --- a/arch/AArch64/AArch64Mapping.h +++ b/arch/AArch64/AArch64Mapping.h @@ -6,8 +6,6 @@ #include "capstone/capstone.h" -#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) - // return name of regiser in friendly string const char *AArch64_reg_name(csh handle, unsigned int reg); @@ -26,7 +24,7 @@ arm64_reg AArch64_map_vregister(unsigned int r); void arm64_op_addReg(MCInst *MI, int reg); -void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp); +void arm64_op_addVectorArrSpecifier(MCInst *MI, int sp); void arm64_op_addFP(MCInst *MI, float fp); @@ -34,8 +32,8 @@ void arm64_op_addImm(MCInst *MI, int64_t imm); const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id); -void AArch64_reg_access(const cs_insn *insn, - cs_regs regs_read, uint8_t *regs_read_count, - cs_regs regs_write, uint8_t *regs_write_count); +void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count); #endif diff --git a/arch/AArch64/AArch64MappingInsn.inc b/arch/AArch64/AArch64MappingInsn.inc index f9e599d52b..caf2964e6a 100644 --- a/arch/AArch64/AArch64MappingInsn.inc +++ b/arch/AArch64/AArch64MappingInsn.inc @@ -1,30356 +1,47707 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* This is auto-gen data for Capstone disassembly engine + * (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ - -{ - AArch64_ABS_ZPmZ_B, ARM64_INS_ABS, +{AArch64_ABS_ZPmZ_B, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif }, -{ - AArch64_ABS_ZPmZ_D, ARM64_INS_ABS, + {AArch64_ABS_ZPmZ_D, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABS_ZPmZ_H, ARM64_INS_ABS, + {AArch64_ABS_ZPmZ_H, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABS_ZPmZ_S, ARM64_INS_ABS, + {AArch64_ABS_ZPmZ_S, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABSv16i8, ARM64_INS_ABS, + {AArch64_ABSv16i8, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABSv1i64, ARM64_INS_ABS, + {AArch64_ABSv1i64, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABSv2i32, ARM64_INS_ABS, + {AArch64_ABSv2i32, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABSv2i64, ARM64_INS_ABS, + {AArch64_ABSv2i64, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABSv4i16, ARM64_INS_ABS, + {AArch64_ABSv4i16, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABSv4i32, ARM64_INS_ABS, + {AArch64_ABSv4i32, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABSv8i16, ARM64_INS_ABS, + {AArch64_ABSv8i16, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ABSv8i8, ARM64_INS_ABS, + {AArch64_ABSv8i8, + ARM64_INS_ABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADCSWr, ARM64_INS_ADCS, + {AArch64_ADCSWr, + ARM64_INS_ADCS, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADCSXr, ARM64_INS_ADCS, + {AArch64_ADCSXr, + ARM64_INS_ADCS, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADCWr, ARM64_INS_ADC, + {AArch64_ADCWr, + ARM64_INS_ADC, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADCXr, ARM64_INS_ADC, + {AArch64_ADCXr, + ARM64_INS_ADC, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN, + {AArch64_ADDHNv2i64_v2i32, + ARM64_INS_ADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2, + {AArch64_ADDHNv2i64_v4i32, + ARM64_INS_ADDHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN, + {AArch64_ADDHNv4i32_v4i16, + ARM64_INS_ADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2, + {AArch64_ADDHNv4i32_v8i16, + ARM64_INS_ADDHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2, + {AArch64_ADDHNv8i16_v16i8, + ARM64_INS_ADDHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN, + {AArch64_ADDHNv8i16_v8i8, + ARM64_INS_ADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDPL_XXI, ARM64_INS_ADDPL, + {AArch64_ADDPL_XXI, + ARM64_INS_ADDPL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDPv16i8, ARM64_INS_ADDP, + {AArch64_ADDPv16i8, + ARM64_INS_ADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDPv2i32, ARM64_INS_ADDP, + {AArch64_ADDPv2i32, + ARM64_INS_ADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDPv2i64, ARM64_INS_ADDP, + {AArch64_ADDPv2i64, + ARM64_INS_ADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDPv2i64p, ARM64_INS_ADDP, + {AArch64_ADDPv2i64p, + ARM64_INS_ADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDPv4i16, ARM64_INS_ADDP, + {AArch64_ADDPv4i16, + ARM64_INS_ADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDPv4i32, ARM64_INS_ADDP, + {AArch64_ADDPv4i32, + ARM64_INS_ADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDPv8i16, ARM64_INS_ADDP, + {AArch64_ADDPv8i16, + ARM64_INS_ADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDPv8i8, ARM64_INS_ADDP, + {AArch64_ADDPv8i8, + ARM64_INS_ADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDSWri, ARM64_INS_ADDS, + {AArch64_ADDSWri, + ARM64_INS_ADDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDSWrs, ARM64_INS_ADDS, + {AArch64_ADDSWrs, + ARM64_INS_ADDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDSWrx, ARM64_INS_ADDS, + {AArch64_ADDSWrx, + ARM64_INS_ADDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDSXri, ARM64_INS_ADDS, + {AArch64_ADDSXri, + ARM64_INS_ADDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDSXrs, ARM64_INS_ADDS, + {AArch64_ADDSXrs, + ARM64_INS_ADDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDSXrx, ARM64_INS_ADDS, + {AArch64_ADDSXrx, + ARM64_INS_ADDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDSXrx64, ARM64_INS_ADDS, + {AArch64_ADDSXrx64, + ARM64_INS_ADDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDVL_XXI, ARM64_INS_ADDVL, + {AArch64_ADDVL_XXI, + ARM64_INS_ADDVL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDVv16i8v, ARM64_INS_ADDV, + {AArch64_ADDVv16i8v, + ARM64_INS_ADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDVv4i16v, ARM64_INS_ADDV, + {AArch64_ADDVv4i16v, + ARM64_INS_ADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDVv4i32v, ARM64_INS_ADDV, + {AArch64_ADDVv4i32v, + ARM64_INS_ADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDVv8i16v, ARM64_INS_ADDV, + {AArch64_ADDVv8i16v, + ARM64_INS_ADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDVv8i8v, ARM64_INS_ADDV, + {AArch64_ADDVv8i8v, + ARM64_INS_ADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDWri, ARM64_INS_ADD, + {AArch64_ADDWri, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDWrs, ARM64_INS_ADD, + {AArch64_ADDWrs, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDWrx, ARM64_INS_ADD, + {AArch64_ADDWrx, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDXri, ARM64_INS_ADD, + {AArch64_ADDXri, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDXrs, ARM64_INS_ADD, + {AArch64_ADDXrs, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDXrx, ARM64_INS_ADD, + {AArch64_ADDXrx, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDXrx64, ARM64_INS_ADD, + {AArch64_ADDXrx64, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZI_B, ARM64_INS_ADD, + {AArch64_ADD_ZI_B, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZI_D, ARM64_INS_ADD, + {AArch64_ADD_ZI_D, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZI_H, ARM64_INS_ADD, + {AArch64_ADD_ZI_H, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZI_S, ARM64_INS_ADD, + {AArch64_ADD_ZI_S, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZPmZ_B, ARM64_INS_ADD, + {AArch64_ADD_ZPmZ_B, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZPmZ_D, ARM64_INS_ADD, + {AArch64_ADD_ZPmZ_D, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZPmZ_H, ARM64_INS_ADD, + {AArch64_ADD_ZPmZ_H, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZPmZ_S, ARM64_INS_ADD, + {AArch64_ADD_ZPmZ_S, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZZZ_B, ARM64_INS_ADD, + {AArch64_ADD_ZZZ_B, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZZZ_D, ARM64_INS_ADD, + {AArch64_ADD_ZZZ_D, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZZZ_H, ARM64_INS_ADD, + {AArch64_ADD_ZZZ_H, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADD_ZZZ_S, ARM64_INS_ADD, + {AArch64_ADD_ZZZ_S, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDv16i8, ARM64_INS_ADD, + {AArch64_ADDv16i8, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDv1i64, ARM64_INS_ADD, + {AArch64_ADDv1i64, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDv2i32, ARM64_INS_ADD, + {AArch64_ADDv2i32, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDv2i64, ARM64_INS_ADD, + {AArch64_ADDv2i64, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDv4i16, ARM64_INS_ADD, + {AArch64_ADDv4i16, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDv4i32, ARM64_INS_ADD, + {AArch64_ADDv4i32, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDv8i16, ARM64_INS_ADD, + {AArch64_ADDv8i16, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADDv8i8, ARM64_INS_ADD, + {AArch64_ADDv8i8, + ARM64_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR, ARM64_INS_ADR, + {AArch64_ADR, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADRP, ARM64_INS_ADRP, + {AArch64_ADRP, + ARM64_INS_ADRP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_LSL_ZZZ_D_0, ARM64_INS_ADR, + {AArch64_ADR_LSL_ZZZ_D_0, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_LSL_ZZZ_D_1, ARM64_INS_ADR, + {AArch64_ADR_LSL_ZZZ_D_1, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_LSL_ZZZ_D_2, ARM64_INS_ADR, + {AArch64_ADR_LSL_ZZZ_D_2, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_LSL_ZZZ_D_3, ARM64_INS_ADR, + {AArch64_ADR_LSL_ZZZ_D_3, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_LSL_ZZZ_S_0, ARM64_INS_ADR, + {AArch64_ADR_LSL_ZZZ_S_0, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_LSL_ZZZ_S_1, ARM64_INS_ADR, + {AArch64_ADR_LSL_ZZZ_S_1, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_LSL_ZZZ_S_2, ARM64_INS_ADR, + {AArch64_ADR_LSL_ZZZ_S_2, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_LSL_ZZZ_S_3, ARM64_INS_ADR, + {AArch64_ADR_LSL_ZZZ_S_3, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_SXTW_ZZZ_D_0, ARM64_INS_ADR, + {AArch64_ADR_SXTW_ZZZ_D_0, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_SXTW_ZZZ_D_1, ARM64_INS_ADR, + {AArch64_ADR_SXTW_ZZZ_D_1, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_SXTW_ZZZ_D_2, ARM64_INS_ADR, + {AArch64_ADR_SXTW_ZZZ_D_2, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_SXTW_ZZZ_D_3, ARM64_INS_ADR, + {AArch64_ADR_SXTW_ZZZ_D_3, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_UXTW_ZZZ_D_0, ARM64_INS_ADR, + {AArch64_ADR_UXTW_ZZZ_D_0, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_UXTW_ZZZ_D_1, ARM64_INS_ADR, + {AArch64_ADR_UXTW_ZZZ_D_1, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_UXTW_ZZZ_D_2, ARM64_INS_ADR, + {AArch64_ADR_UXTW_ZZZ_D_2, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ADR_UXTW_ZZZ_D_3, ARM64_INS_ADR, + {AArch64_ADR_UXTW_ZZZ_D_3, + ARM64_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AESDrr, ARM64_INS_AESD, + {AArch64_AESDrr, + ARM64_INS_AESD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AESErr, ARM64_INS_AESE, + {AArch64_AESErr, + ARM64_INS_AESE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AESIMCrr, ARM64_INS_AESIMC, + {AArch64_AESIMCrr, + ARM64_INS_AESIMC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AESMCrr, ARM64_INS_AESMC, + {AArch64_AESMCrr, + ARM64_INS_AESMC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDSWri, ARM64_INS_ANDS, + {AArch64_ANDSWri, + ARM64_INS_ANDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDSWrs, ARM64_INS_ANDS, + {AArch64_ANDSWrs, + ARM64_INS_ANDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDSXri, ARM64_INS_ANDS, + {AArch64_ANDSXri, + ARM64_INS_ANDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDSXrs, ARM64_INS_ANDS, + {AArch64_ANDSXrs, + ARM64_INS_ANDS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDS_PPzPP, ARM64_INS_ANDS, + {AArch64_ANDS_PPzPP, + ARM64_INS_ANDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDV_VPZ_B, ARM64_INS_ANDV, + {AArch64_ANDV_VPZ_B, + ARM64_INS_ANDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDV_VPZ_D, ARM64_INS_ANDV, + {AArch64_ANDV_VPZ_D, + ARM64_INS_ANDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDV_VPZ_H, ARM64_INS_ANDV, + {AArch64_ANDV_VPZ_H, + ARM64_INS_ANDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDV_VPZ_S, ARM64_INS_ANDV, + {AArch64_ANDV_VPZ_S, + ARM64_INS_ANDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDWri, ARM64_INS_AND, + {AArch64_ANDWri, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDWrs, ARM64_INS_AND, + {AArch64_ANDWrs, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDXri, ARM64_INS_AND, + {AArch64_ANDXri, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDXrs, ARM64_INS_AND, + {AArch64_ANDXrs, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AND_PPzPP, ARM64_INS_AND, + {AArch64_AND_PPzPP, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AND_ZI, ARM64_INS_AND, + {AArch64_AND_ZI, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AND_ZPmZ_B, ARM64_INS_AND, + {AArch64_AND_ZPmZ_B, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AND_ZPmZ_D, ARM64_INS_AND, + {AArch64_AND_ZPmZ_D, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AND_ZPmZ_H, ARM64_INS_AND, + {AArch64_AND_ZPmZ_H, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AND_ZPmZ_S, ARM64_INS_AND, + {AArch64_AND_ZPmZ_S, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AND_ZZZ, ARM64_INS_AND, + {AArch64_AND_ZZZ, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDv16i8, ARM64_INS_AND, + {AArch64_ANDv16i8, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ANDv8i8, ARM64_INS_AND, + {AArch64_ANDv8i8, + ARM64_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRD_ZPmI_B, ARM64_INS_ASRD, + {AArch64_ASRD_ZPmI_B, + ARM64_INS_ASRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRD_ZPmI_D, ARM64_INS_ASRD, + {AArch64_ASRD_ZPmI_D, + ARM64_INS_ASRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRD_ZPmI_H, ARM64_INS_ASRD, + {AArch64_ASRD_ZPmI_H, + ARM64_INS_ASRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRD_ZPmI_S, ARM64_INS_ASRD, + {AArch64_ASRD_ZPmI_S, + ARM64_INS_ASRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRR_ZPmZ_B, ARM64_INS_ASRR, + {AArch64_ASRR_ZPmZ_B, + ARM64_INS_ASRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRR_ZPmZ_D, ARM64_INS_ASRR, + {AArch64_ASRR_ZPmZ_D, + ARM64_INS_ASRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRR_ZPmZ_H, ARM64_INS_ASRR, + {AArch64_ASRR_ZPmZ_H, + ARM64_INS_ASRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRR_ZPmZ_S, ARM64_INS_ASRR, + {AArch64_ASRR_ZPmZ_S, + ARM64_INS_ASRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRVWr, ARM64_INS_ASR, + {AArch64_ASRVWr, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASRVXr, ARM64_INS_ASR, + {AArch64_ASRVXr, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_WIDE_ZPmZ_B, ARM64_INS_ASR, + {AArch64_ASR_WIDE_ZPmZ_B, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_WIDE_ZPmZ_H, ARM64_INS_ASR, + {AArch64_ASR_WIDE_ZPmZ_H, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_WIDE_ZPmZ_S, ARM64_INS_ASR, + {AArch64_ASR_WIDE_ZPmZ_S, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_WIDE_ZZZ_B, ARM64_INS_ASR, + {AArch64_ASR_WIDE_ZZZ_B, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_WIDE_ZZZ_H, ARM64_INS_ASR, + {AArch64_ASR_WIDE_ZZZ_H, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_WIDE_ZZZ_S, ARM64_INS_ASR, + {AArch64_ASR_WIDE_ZZZ_S, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZPmI_B, ARM64_INS_ASR, + {AArch64_ASR_ZPmI_B, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZPmI_D, ARM64_INS_ASR, + {AArch64_ASR_ZPmI_D, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZPmI_H, ARM64_INS_ASR, + {AArch64_ASR_ZPmI_H, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZPmI_S, ARM64_INS_ASR, + {AArch64_ASR_ZPmI_S, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZPmZ_B, ARM64_INS_ASR, + {AArch64_ASR_ZPmZ_B, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZPmZ_D, ARM64_INS_ASR, + {AArch64_ASR_ZPmZ_D, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZPmZ_H, ARM64_INS_ASR, + {AArch64_ASR_ZPmZ_H, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZPmZ_S, ARM64_INS_ASR, + {AArch64_ASR_ZPmZ_S, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZZI_B, ARM64_INS_ASR, + {AArch64_ASR_ZZI_B, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZZI_D, ARM64_INS_ASR, + {AArch64_ASR_ZZI_D, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZZI_H, ARM64_INS_ASR, + {AArch64_ASR_ZZI_H, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ASR_ZZI_S, ARM64_INS_ASR, + {AArch64_ASR_ZZI_S, + ARM64_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTDA, ARM64_INS_AUTDA, + {AArch64_AUTDA, + ARM64_INS_AUTDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTDB, ARM64_INS_AUTDB, + {AArch64_AUTDB, + ARM64_INS_AUTDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTDZA, ARM64_INS_AUTDZA, + {AArch64_AUTDZA, + ARM64_INS_AUTDZA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTDZB, ARM64_INS_AUTDZB, + {AArch64_AUTDZB, + ARM64_INS_AUTDZB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIA, ARM64_INS_AUTIA, + {AArch64_AUTIA, + ARM64_INS_AUTIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIA1716, ARM64_INS_AUTIA1716, + {AArch64_AUTIA1716, + ARM64_INS_AUTIA1716, #ifndef CAPSTONE_DIET - { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_X16, ARM64_REG_X17, 0}, + {ARM64_REG_X17, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIASP, ARM64_INS_AUTIASP, + {AArch64_AUTIASP, + ARM64_INS_AUTIASP, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, ARM64_REG_SP, 0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIAZ, ARM64_INS_AUTIAZ, + {AArch64_AUTIAZ, + ARM64_INS_AUTIAZ, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, 0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIB, ARM64_INS_AUTIB, + {AArch64_AUTIB, + ARM64_INS_AUTIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIB1716, ARM64_INS_AUTIB1716, + {AArch64_AUTIB1716, + ARM64_INS_AUTIB1716, #ifndef CAPSTONE_DIET - { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_X16, ARM64_REG_X17, 0}, + {ARM64_REG_X17, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIBSP, ARM64_INS_AUTIBSP, + {AArch64_AUTIBSP, + ARM64_INS_AUTIBSP, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, ARM64_REG_SP, 0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIBZ, ARM64_INS_AUTIBZ, + {AArch64_AUTIBZ, + ARM64_INS_AUTIBZ, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, 0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIZA, ARM64_INS_AUTIZA, + {AArch64_AUTIZA, + ARM64_INS_AUTIZA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_AUTIZB, ARM64_INS_AUTIZB, + {AArch64_AUTIZB, + ARM64_INS_AUTIZB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_B, ARM64_INS_B, + {AArch64_B, ARM64_INS_B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {0}, {0}, {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, 1, + 0 #endif -}, + }, -{ - AArch64_BCAX, ARM64_INS_BCAX, + {AArch64_BCAX, + ARM64_INS_BCAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BFMWri, ARM64_INS_BFM, + {AArch64_BFMWri, + ARM64_INS_BFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BFMXri, ARM64_INS_BFM, + {AArch64_BFMXri, + ARM64_INS_BFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICSWrs, ARM64_INS_BICS, + {AArch64_BICSWrs, + ARM64_INS_BICS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICSXrs, ARM64_INS_BICS, + {AArch64_BICSXrs, + ARM64_INS_BICS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICS_PPzPP, ARM64_INS_BICS, + {AArch64_BICS_PPzPP, + ARM64_INS_BICS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICWrs, ARM64_INS_BIC, + {AArch64_BICWrs, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICXrs, ARM64_INS_BIC, + {AArch64_BICXrs, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BIC_PPzPP, ARM64_INS_BIC, + {AArch64_BIC_PPzPP, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BIC_ZPmZ_B, ARM64_INS_BIC, + {AArch64_BIC_ZPmZ_B, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BIC_ZPmZ_D, ARM64_INS_BIC, + {AArch64_BIC_ZPmZ_D, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BIC_ZPmZ_H, ARM64_INS_BIC, + {AArch64_BIC_ZPmZ_H, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BIC_ZPmZ_S, ARM64_INS_BIC, + {AArch64_BIC_ZPmZ_S, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BIC_ZZZ, ARM64_INS_BIC, + {AArch64_BIC_ZZZ, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICv16i8, ARM64_INS_BIC, + {AArch64_BICv16i8, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICv2i32, ARM64_INS_BIC, + {AArch64_BICv2i32, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICv4i16, ARM64_INS_BIC, + {AArch64_BICv4i16, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICv4i32, ARM64_INS_BIC, + {AArch64_BICv4i32, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICv8i16, ARM64_INS_BIC, + {AArch64_BICv8i16, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BICv8i8, ARM64_INS_BIC, + {AArch64_BICv8i8, + ARM64_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BIFv16i8, ARM64_INS_BIF, + {AArch64_BIFv16i8, + ARM64_INS_BIF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BIFv8i8, ARM64_INS_BIF, + {AArch64_BIFv8i8, + ARM64_INS_BIF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BITv16i8, ARM64_INS_BIT, + {AArch64_BITv16i8, + ARM64_INS_BIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BITv8i8, ARM64_INS_BIT, + {AArch64_BITv8i8, + ARM64_INS_BIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BL, ARM64_INS_BL, + {AArch64_BL, + ARM64_INS_BL, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_BLR, ARM64_INS_BLR, + {AArch64_BLR, + ARM64_INS_BLR, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 1 + {0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 1 #endif -}, + }, -{ - AArch64_BLRAA, ARM64_INS_BLRAA, + {AArch64_BLRAA, + ARM64_INS_BLRAA, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, + 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BLRAAZ, ARM64_INS_BLRAAZ, + {AArch64_BLRAAZ, + ARM64_INS_BLRAAZ, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, + 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BLRAB, ARM64_INS_BLRAB, + {AArch64_BLRAB, + ARM64_INS_BLRAB, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, + 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BLRABZ, ARM64_INS_BLRABZ, + {AArch64_BLRABZ, + ARM64_INS_BLRABZ, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, + 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BR, ARM64_INS_BR, + {AArch64_BR, ARM64_INS_BR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 1 + {0}, {0}, {ARM64_GRP_JUMP, 0}, 1, + 1 #endif -}, + }, -{ - AArch64_BRAA, ARM64_INS_BRAA, + {AArch64_BRAA, + ARM64_INS_BRAA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRAAZ, ARM64_INS_BRAAZ, + {AArch64_BRAAZ, + ARM64_INS_BRAAZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRAB, ARM64_INS_BRAB, + {AArch64_BRAB, + ARM64_INS_BRAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRABZ, ARM64_INS_BRABZ, + {AArch64_BRABZ, + ARM64_INS_BRABZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRK, ARM64_INS_BRK, + {AArch64_BRK, + ARM64_INS_BRK, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKAS_PPzP, ARM64_INS_BRKAS, + {AArch64_BRKAS_PPzP, + ARM64_INS_BRKAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKA_PPmP, ARM64_INS_BRKA, + {AArch64_BRKA_PPmP, + ARM64_INS_BRKA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKA_PPzP, ARM64_INS_BRKA, + {AArch64_BRKA_PPzP, + ARM64_INS_BRKA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKBS_PPzP, ARM64_INS_BRKBS, + {AArch64_BRKBS_PPzP, + ARM64_INS_BRKBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKB_PPmP, ARM64_INS_BRKB, + {AArch64_BRKB_PPmP, + ARM64_INS_BRKB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKB_PPzP, ARM64_INS_BRKB, + {AArch64_BRKB_PPzP, + ARM64_INS_BRKB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKNS_PPzP, ARM64_INS_BRKNS, + {AArch64_BRKNS_PPzP, + ARM64_INS_BRKNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKN_PPzP, ARM64_INS_BRKN, + {AArch64_BRKN_PPzP, + ARM64_INS_BRKN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKPAS_PPzPP, ARM64_INS_BRKPAS, + {AArch64_BRKPAS_PPzPP, + ARM64_INS_BRKPAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKPA_PPzPP, ARM64_INS_BRKPA, + {AArch64_BRKPA_PPzPP, + ARM64_INS_BRKPA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKPBS_PPzPP, ARM64_INS_BRKPBS, + {AArch64_BRKPBS_PPzPP, + ARM64_INS_BRKPBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BRKPB_PPzPP, ARM64_INS_BRKPB, + {AArch64_BRKPB_PPzPP, + ARM64_INS_BRKPB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BSLv16i8, ARM64_INS_BSL, + {AArch64_BSLv16i8, + ARM64_INS_BSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_BSLv8i8, ARM64_INS_BSL, + {AArch64_BSLv8i8, + ARM64_INS_BSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_Bcc, ARM64_INS_B, + {AArch64_Bcc, + ARM64_INS_B, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_CASAB, ARM64_INS_CASAB, + {AArch64_CASAB, + ARM64_INS_CASAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASAH, ARM64_INS_CASAH, + {AArch64_CASAH, + ARM64_INS_CASAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASALB, ARM64_INS_CASALB, + {AArch64_CASALB, + ARM64_INS_CASALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASALH, ARM64_INS_CASALH, + {AArch64_CASALH, + ARM64_INS_CASALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASALW, ARM64_INS_CASAL, + {AArch64_CASALW, + ARM64_INS_CASAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASALX, ARM64_INS_CASAL, + {AArch64_CASALX, + ARM64_INS_CASAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASAW, ARM64_INS_CASA, + {AArch64_CASAW, + ARM64_INS_CASA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASAX, ARM64_INS_CASA, + {AArch64_CASAX, + ARM64_INS_CASA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASB, ARM64_INS_CASB, + {AArch64_CASB, + ARM64_INS_CASB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASH, ARM64_INS_CASH, + {AArch64_CASH, + ARM64_INS_CASH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASLB, ARM64_INS_CASLB, + {AArch64_CASLB, + ARM64_INS_CASLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASLH, ARM64_INS_CASLH, + {AArch64_CASLH, + ARM64_INS_CASLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASLW, ARM64_INS_CASL, + {AArch64_CASLW, + ARM64_INS_CASL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASLX, ARM64_INS_CASL, + {AArch64_CASLX, + ARM64_INS_CASL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASPALW, ARM64_INS_CASPAL, + {AArch64_CASPALW, + ARM64_INS_CASPAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASPALX, ARM64_INS_CASPAL, + {AArch64_CASPALX, + ARM64_INS_CASPAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASPAW, ARM64_INS_CASPA, + {AArch64_CASPAW, + ARM64_INS_CASPA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASPAX, ARM64_INS_CASPA, + {AArch64_CASPAX, + ARM64_INS_CASPA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASPLW, ARM64_INS_CASPL, + {AArch64_CASPLW, + ARM64_INS_CASPL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASPLX, ARM64_INS_CASPL, + {AArch64_CASPLX, + ARM64_INS_CASPL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASPW, ARM64_INS_CASP, + {AArch64_CASPW, + ARM64_INS_CASP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASPX, ARM64_INS_CASP, + {AArch64_CASPX, + ARM64_INS_CASP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASW, ARM64_INS_CAS, + {AArch64_CASW, + ARM64_INS_CAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CASX, ARM64_INS_CAS, + {AArch64_CASX, + ARM64_INS_CAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CBNZW, ARM64_INS_CBNZ, + {AArch64_CBNZW, + ARM64_INS_CBNZ, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_CBNZX, ARM64_INS_CBNZ, + {AArch64_CBNZX, + ARM64_INS_CBNZ, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_CBZW, ARM64_INS_CBZ, + {AArch64_CBZW, + ARM64_INS_CBZ, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_CBZX, ARM64_INS_CBZ, + {AArch64_CBZX, + ARM64_INS_CBZ, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_CCMNWi, ARM64_INS_CCMN, + {AArch64_CCMNWi, + ARM64_INS_CCMN, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CCMNWr, ARM64_INS_CCMN, + {AArch64_CCMNWr, + ARM64_INS_CCMN, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CCMNXi, ARM64_INS_CCMN, + {AArch64_CCMNXi, + ARM64_INS_CCMN, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CCMNXr, ARM64_INS_CCMN, + {AArch64_CCMNXr, + ARM64_INS_CCMN, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CCMPWi, ARM64_INS_CCMP, + {AArch64_CCMPWi, + ARM64_INS_CCMP, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CCMPWr, ARM64_INS_CCMP, + {AArch64_CCMPWr, + ARM64_INS_CCMP, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CCMPXi, ARM64_INS_CCMP, + {AArch64_CCMPXi, + ARM64_INS_CCMP, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CCMPXr, ARM64_INS_CCMP, + {AArch64_CCMPXr, + ARM64_INS_CCMP, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CFINV, ARM64_INS_CFINV, + {AArch64_CFINV, + ARM64_INS_CFINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_RPZ_B, ARM64_INS_CLASTA, + {AArch64_CLASTA_RPZ_B, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_RPZ_D, ARM64_INS_CLASTA, + {AArch64_CLASTA_RPZ_D, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_RPZ_H, ARM64_INS_CLASTA, + {AArch64_CLASTA_RPZ_H, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_RPZ_S, ARM64_INS_CLASTA, + {AArch64_CLASTA_RPZ_S, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_VPZ_B, ARM64_INS_CLASTA, + {AArch64_CLASTA_VPZ_B, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_VPZ_D, ARM64_INS_CLASTA, + {AArch64_CLASTA_VPZ_D, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_VPZ_H, ARM64_INS_CLASTA, + {AArch64_CLASTA_VPZ_H, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_VPZ_S, ARM64_INS_CLASTA, + {AArch64_CLASTA_VPZ_S, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_ZPZ_B, ARM64_INS_CLASTA, + {AArch64_CLASTA_ZPZ_B, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_ZPZ_D, ARM64_INS_CLASTA, + {AArch64_CLASTA_ZPZ_D, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_ZPZ_H, ARM64_INS_CLASTA, + {AArch64_CLASTA_ZPZ_H, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTA_ZPZ_S, ARM64_INS_CLASTA, + {AArch64_CLASTA_ZPZ_S, + ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_RPZ_B, ARM64_INS_CLASTB, + {AArch64_CLASTB_RPZ_B, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_RPZ_D, ARM64_INS_CLASTB, + {AArch64_CLASTB_RPZ_D, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_RPZ_H, ARM64_INS_CLASTB, + {AArch64_CLASTB_RPZ_H, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_RPZ_S, ARM64_INS_CLASTB, + {AArch64_CLASTB_RPZ_S, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_VPZ_B, ARM64_INS_CLASTB, + {AArch64_CLASTB_VPZ_B, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_VPZ_D, ARM64_INS_CLASTB, + {AArch64_CLASTB_VPZ_D, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_VPZ_H, ARM64_INS_CLASTB, + {AArch64_CLASTB_VPZ_H, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_VPZ_S, ARM64_INS_CLASTB, + {AArch64_CLASTB_VPZ_S, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_ZPZ_B, ARM64_INS_CLASTB, + {AArch64_CLASTB_ZPZ_B, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_ZPZ_D, ARM64_INS_CLASTB, + {AArch64_CLASTB_ZPZ_D, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_ZPZ_H, ARM64_INS_CLASTB, + {AArch64_CLASTB_ZPZ_H, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLASTB_ZPZ_S, ARM64_INS_CLASTB, + {AArch64_CLASTB_ZPZ_S, + ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLREX, ARM64_INS_CLREX, + {AArch64_CLREX, + ARM64_INS_CLREX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLSWr, ARM64_INS_CLS, + {AArch64_CLSWr, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLSXr, ARM64_INS_CLS, + {AArch64_CLSXr, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLS_ZPmZ_B, ARM64_INS_CLS, + {AArch64_CLS_ZPmZ_B, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLS_ZPmZ_D, ARM64_INS_CLS, + {AArch64_CLS_ZPmZ_D, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLS_ZPmZ_H, ARM64_INS_CLS, + {AArch64_CLS_ZPmZ_H, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLS_ZPmZ_S, ARM64_INS_CLS, + {AArch64_CLS_ZPmZ_S, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLSv16i8, ARM64_INS_CLS, + {AArch64_CLSv16i8, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLSv2i32, ARM64_INS_CLS, + {AArch64_CLSv2i32, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLSv4i16, ARM64_INS_CLS, + {AArch64_CLSv4i16, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLSv4i32, ARM64_INS_CLS, + {AArch64_CLSv4i32, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLSv8i16, ARM64_INS_CLS, + {AArch64_CLSv8i16, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLSv8i8, ARM64_INS_CLS, + {AArch64_CLSv8i8, + ARM64_INS_CLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZWr, ARM64_INS_CLZ, + {AArch64_CLZWr, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZXr, ARM64_INS_CLZ, + {AArch64_CLZXr, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZ_ZPmZ_B, ARM64_INS_CLZ, + {AArch64_CLZ_ZPmZ_B, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZ_ZPmZ_D, ARM64_INS_CLZ, + {AArch64_CLZ_ZPmZ_D, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZ_ZPmZ_H, ARM64_INS_CLZ, + {AArch64_CLZ_ZPmZ_H, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZ_ZPmZ_S, ARM64_INS_CLZ, + {AArch64_CLZ_ZPmZ_S, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZv16i8, ARM64_INS_CLZ, + {AArch64_CLZv16i8, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZv2i32, ARM64_INS_CLZ, + {AArch64_CLZv2i32, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZv4i16, ARM64_INS_CLZ, + {AArch64_CLZv4i16, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZv4i32, ARM64_INS_CLZ, + {AArch64_CLZv4i32, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZv8i16, ARM64_INS_CLZ, + {AArch64_CLZv8i16, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CLZv8i8, ARM64_INS_CLZ, + {AArch64_CLZv8i8, + ARM64_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv16i8, ARM64_INS_CMEQ, + {AArch64_CMEQv16i8, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv16i8rz, ARM64_INS_CMEQ, + {AArch64_CMEQv16i8rz, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv1i64, ARM64_INS_CMEQ, + {AArch64_CMEQv1i64, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv1i64rz, ARM64_INS_CMEQ, + {AArch64_CMEQv1i64rz, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv2i32, ARM64_INS_CMEQ, + {AArch64_CMEQv2i32, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv2i32rz, ARM64_INS_CMEQ, + {AArch64_CMEQv2i32rz, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv2i64, ARM64_INS_CMEQ, + {AArch64_CMEQv2i64, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv2i64rz, ARM64_INS_CMEQ, + {AArch64_CMEQv2i64rz, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv4i16, ARM64_INS_CMEQ, + {AArch64_CMEQv4i16, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv4i16rz, ARM64_INS_CMEQ, + {AArch64_CMEQv4i16rz, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv4i32, ARM64_INS_CMEQ, + {AArch64_CMEQv4i32, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv4i32rz, ARM64_INS_CMEQ, + {AArch64_CMEQv4i32rz, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv8i16, ARM64_INS_CMEQ, + {AArch64_CMEQv8i16, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv8i16rz, ARM64_INS_CMEQ, + {AArch64_CMEQv8i16rz, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv8i8, ARM64_INS_CMEQ, + {AArch64_CMEQv8i8, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMEQv8i8rz, ARM64_INS_CMEQ, + {AArch64_CMEQv8i8rz, + ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv16i8, ARM64_INS_CMGE, + {AArch64_CMGEv16i8, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv16i8rz, ARM64_INS_CMGE, + {AArch64_CMGEv16i8rz, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv1i64, ARM64_INS_CMGE, + {AArch64_CMGEv1i64, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv1i64rz, ARM64_INS_CMGE, + {AArch64_CMGEv1i64rz, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv2i32, ARM64_INS_CMGE, + {AArch64_CMGEv2i32, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv2i32rz, ARM64_INS_CMGE, + {AArch64_CMGEv2i32rz, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv2i64, ARM64_INS_CMGE, + {AArch64_CMGEv2i64, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv2i64rz, ARM64_INS_CMGE, + {AArch64_CMGEv2i64rz, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv4i16, ARM64_INS_CMGE, + {AArch64_CMGEv4i16, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv4i16rz, ARM64_INS_CMGE, + {AArch64_CMGEv4i16rz, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv4i32, ARM64_INS_CMGE, + {AArch64_CMGEv4i32, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv4i32rz, ARM64_INS_CMGE, + {AArch64_CMGEv4i32rz, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv8i16, ARM64_INS_CMGE, + {AArch64_CMGEv8i16, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv8i16rz, ARM64_INS_CMGE, + {AArch64_CMGEv8i16rz, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv8i8, ARM64_INS_CMGE, + {AArch64_CMGEv8i8, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGEv8i8rz, ARM64_INS_CMGE, + {AArch64_CMGEv8i8rz, + ARM64_INS_CMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv16i8, ARM64_INS_CMGT, + {AArch64_CMGTv16i8, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv16i8rz, ARM64_INS_CMGT, + {AArch64_CMGTv16i8rz, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv1i64, ARM64_INS_CMGT, + {AArch64_CMGTv1i64, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv1i64rz, ARM64_INS_CMGT, + {AArch64_CMGTv1i64rz, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv2i32, ARM64_INS_CMGT, + {AArch64_CMGTv2i32, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv2i32rz, ARM64_INS_CMGT, + {AArch64_CMGTv2i32rz, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv2i64, ARM64_INS_CMGT, + {AArch64_CMGTv2i64, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv2i64rz, ARM64_INS_CMGT, + {AArch64_CMGTv2i64rz, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv4i16, ARM64_INS_CMGT, + {AArch64_CMGTv4i16, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv4i16rz, ARM64_INS_CMGT, + {AArch64_CMGTv4i16rz, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv4i32, ARM64_INS_CMGT, + {AArch64_CMGTv4i32, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv4i32rz, ARM64_INS_CMGT, + {AArch64_CMGTv4i32rz, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv8i16, ARM64_INS_CMGT, + {AArch64_CMGTv8i16, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv8i16rz, ARM64_INS_CMGT, + {AArch64_CMGTv8i16rz, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv8i8, ARM64_INS_CMGT, + {AArch64_CMGTv8i8, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMGTv8i8rz, ARM64_INS_CMGT, + {AArch64_CMGTv8i8rz, + ARM64_INS_CMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHIv16i8, ARM64_INS_CMHI, + {AArch64_CMHIv16i8, + ARM64_INS_CMHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHIv1i64, ARM64_INS_CMHI, + {AArch64_CMHIv1i64, + ARM64_INS_CMHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHIv2i32, ARM64_INS_CMHI, + {AArch64_CMHIv2i32, + ARM64_INS_CMHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHIv2i64, ARM64_INS_CMHI, + {AArch64_CMHIv2i64, + ARM64_INS_CMHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHIv4i16, ARM64_INS_CMHI, + {AArch64_CMHIv4i16, + ARM64_INS_CMHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHIv4i32, ARM64_INS_CMHI, + {AArch64_CMHIv4i32, + ARM64_INS_CMHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHIv8i16, ARM64_INS_CMHI, + {AArch64_CMHIv8i16, + ARM64_INS_CMHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHIv8i8, ARM64_INS_CMHI, + {AArch64_CMHIv8i8, + ARM64_INS_CMHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHSv16i8, ARM64_INS_CMHS, + {AArch64_CMHSv16i8, + ARM64_INS_CMHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHSv1i64, ARM64_INS_CMHS, + {AArch64_CMHSv1i64, + ARM64_INS_CMHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHSv2i32, ARM64_INS_CMHS, + {AArch64_CMHSv2i32, + ARM64_INS_CMHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHSv2i64, ARM64_INS_CMHS, + {AArch64_CMHSv2i64, + ARM64_INS_CMHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHSv4i16, ARM64_INS_CMHS, + {AArch64_CMHSv4i16, + ARM64_INS_CMHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHSv4i32, ARM64_INS_CMHS, + {AArch64_CMHSv4i32, + ARM64_INS_CMHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHSv8i16, ARM64_INS_CMHS, + {AArch64_CMHSv8i16, + ARM64_INS_CMHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMHSv8i8, ARM64_INS_CMHS, + {AArch64_CMHSv8i8, + ARM64_INS_CMHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLEv16i8rz, ARM64_INS_CMLE, + {AArch64_CMLEv16i8rz, + ARM64_INS_CMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLEv1i64rz, ARM64_INS_CMLE, + {AArch64_CMLEv1i64rz, + ARM64_INS_CMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLEv2i32rz, ARM64_INS_CMLE, + {AArch64_CMLEv2i32rz, + ARM64_INS_CMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLEv2i64rz, ARM64_INS_CMLE, + {AArch64_CMLEv2i64rz, + ARM64_INS_CMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLEv4i16rz, ARM64_INS_CMLE, + {AArch64_CMLEv4i16rz, + ARM64_INS_CMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLEv4i32rz, ARM64_INS_CMLE, + {AArch64_CMLEv4i32rz, + ARM64_INS_CMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLEv8i16rz, ARM64_INS_CMLE, + {AArch64_CMLEv8i16rz, + ARM64_INS_CMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLEv8i8rz, ARM64_INS_CMLE, + {AArch64_CMLEv8i8rz, + ARM64_INS_CMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLTv16i8rz, ARM64_INS_CMLT, + {AArch64_CMLTv16i8rz, + ARM64_INS_CMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLTv1i64rz, ARM64_INS_CMLT, + {AArch64_CMLTv1i64rz, + ARM64_INS_CMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLTv2i32rz, ARM64_INS_CMLT, + {AArch64_CMLTv2i32rz, + ARM64_INS_CMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLTv2i64rz, ARM64_INS_CMLT, + {AArch64_CMLTv2i64rz, + ARM64_INS_CMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLTv4i16rz, ARM64_INS_CMLT, + {AArch64_CMLTv4i16rz, + ARM64_INS_CMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLTv4i32rz, ARM64_INS_CMLT, + {AArch64_CMLTv4i32rz, + ARM64_INS_CMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLTv8i16rz, ARM64_INS_CMLT, + {AArch64_CMLTv8i16rz, + ARM64_INS_CMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMLTv8i8rz, ARM64_INS_CMLT, + {AArch64_CMLTv8i8rz, + ARM64_INS_CMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_PPzZI_B, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_PPzZI_B, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_PPzZI_D, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_PPzZI_D, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_PPzZI_H, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_PPzZI_H, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_PPzZI_S, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_PPzZI_S, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_PPzZZ_B, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_PPzZZ_B, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_PPzZZ_D, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_PPzZZ_D, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_PPzZZ_H, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_PPzZZ_H, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_PPzZZ_S, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_PPzZZ_S, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_WIDE_PPzZZ_B, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_WIDE_PPzZZ_B, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_WIDE_PPzZZ_H, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_WIDE_PPzZZ_H, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPEQ_WIDE_PPzZZ_S, ARM64_INS_CMPEQ, + {AArch64_CMPEQ_WIDE_PPzZZ_S, + ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_PPzZI_B, ARM64_INS_CMPGE, + {AArch64_CMPGE_PPzZI_B, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_PPzZI_D, ARM64_INS_CMPGE, + {AArch64_CMPGE_PPzZI_D, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_PPzZI_H, ARM64_INS_CMPGE, + {AArch64_CMPGE_PPzZI_H, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_PPzZI_S, ARM64_INS_CMPGE, + {AArch64_CMPGE_PPzZI_S, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_PPzZZ_B, ARM64_INS_CMPGE, + {AArch64_CMPGE_PPzZZ_B, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_PPzZZ_D, ARM64_INS_CMPGE, + {AArch64_CMPGE_PPzZZ_D, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_PPzZZ_H, ARM64_INS_CMPGE, + {AArch64_CMPGE_PPzZZ_H, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_PPzZZ_S, ARM64_INS_CMPGE, + {AArch64_CMPGE_PPzZZ_S, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_WIDE_PPzZZ_B, ARM64_INS_CMPGE, + {AArch64_CMPGE_WIDE_PPzZZ_B, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_WIDE_PPzZZ_H, ARM64_INS_CMPGE, + {AArch64_CMPGE_WIDE_PPzZZ_H, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGE_WIDE_PPzZZ_S, ARM64_INS_CMPGE, + {AArch64_CMPGE_WIDE_PPzZZ_S, + ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_PPzZI_B, ARM64_INS_CMPGT, + {AArch64_CMPGT_PPzZI_B, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_PPzZI_D, ARM64_INS_CMPGT, + {AArch64_CMPGT_PPzZI_D, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_PPzZI_H, ARM64_INS_CMPGT, + {AArch64_CMPGT_PPzZI_H, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_PPzZI_S, ARM64_INS_CMPGT, + {AArch64_CMPGT_PPzZI_S, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_PPzZZ_B, ARM64_INS_CMPGT, + {AArch64_CMPGT_PPzZZ_B, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_PPzZZ_D, ARM64_INS_CMPGT, + {AArch64_CMPGT_PPzZZ_D, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_PPzZZ_H, ARM64_INS_CMPGT, + {AArch64_CMPGT_PPzZZ_H, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_PPzZZ_S, ARM64_INS_CMPGT, + {AArch64_CMPGT_PPzZZ_S, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_WIDE_PPzZZ_B, ARM64_INS_CMPGT, + {AArch64_CMPGT_WIDE_PPzZZ_B, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_WIDE_PPzZZ_H, ARM64_INS_CMPGT, + {AArch64_CMPGT_WIDE_PPzZZ_H, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPGT_WIDE_PPzZZ_S, ARM64_INS_CMPGT, + {AArch64_CMPGT_WIDE_PPzZZ_S, + ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_PPzZI_B, ARM64_INS_CMPHI, + {AArch64_CMPHI_PPzZI_B, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_PPzZI_D, ARM64_INS_CMPHI, + {AArch64_CMPHI_PPzZI_D, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_PPzZI_H, ARM64_INS_CMPHI, + {AArch64_CMPHI_PPzZI_H, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_PPzZI_S, ARM64_INS_CMPHI, + {AArch64_CMPHI_PPzZI_S, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_PPzZZ_B, ARM64_INS_CMPHI, + {AArch64_CMPHI_PPzZZ_B, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_PPzZZ_D, ARM64_INS_CMPHI, + {AArch64_CMPHI_PPzZZ_D, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_PPzZZ_H, ARM64_INS_CMPHI, + {AArch64_CMPHI_PPzZZ_H, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_PPzZZ_S, ARM64_INS_CMPHI, + {AArch64_CMPHI_PPzZZ_S, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_WIDE_PPzZZ_B, ARM64_INS_CMPHI, + {AArch64_CMPHI_WIDE_PPzZZ_B, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_WIDE_PPzZZ_H, ARM64_INS_CMPHI, + {AArch64_CMPHI_WIDE_PPzZZ_H, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHI_WIDE_PPzZZ_S, ARM64_INS_CMPHI, + {AArch64_CMPHI_WIDE_PPzZZ_S, + ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_PPzZI_B, ARM64_INS_CMPHS, + {AArch64_CMPHS_PPzZI_B, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_PPzZI_D, ARM64_INS_CMPHS, + {AArch64_CMPHS_PPzZI_D, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_PPzZI_H, ARM64_INS_CMPHS, + {AArch64_CMPHS_PPzZI_H, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_PPzZI_S, ARM64_INS_CMPHS, + {AArch64_CMPHS_PPzZI_S, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_PPzZZ_B, ARM64_INS_CMPHS, + {AArch64_CMPHS_PPzZZ_B, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_PPzZZ_D, ARM64_INS_CMPHS, + {AArch64_CMPHS_PPzZZ_D, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_PPzZZ_H, ARM64_INS_CMPHS, + {AArch64_CMPHS_PPzZZ_H, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_PPzZZ_S, ARM64_INS_CMPHS, + {AArch64_CMPHS_PPzZZ_S, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_WIDE_PPzZZ_B, ARM64_INS_CMPHS, + {AArch64_CMPHS_WIDE_PPzZZ_B, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_WIDE_PPzZZ_H, ARM64_INS_CMPHS, + {AArch64_CMPHS_WIDE_PPzZZ_H, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPHS_WIDE_PPzZZ_S, ARM64_INS_CMPHS, + {AArch64_CMPHS_WIDE_PPzZZ_S, + ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLE_PPzZI_B, ARM64_INS_CMPLE, + {AArch64_CMPLE_PPzZI_B, + ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLE_PPzZI_D, ARM64_INS_CMPLE, + {AArch64_CMPLE_PPzZI_D, + ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLE_PPzZI_H, ARM64_INS_CMPLE, + {AArch64_CMPLE_PPzZI_H, + ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLE_PPzZI_S, ARM64_INS_CMPLE, + {AArch64_CMPLE_PPzZI_S, + ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLE_WIDE_PPzZZ_B, ARM64_INS_CMPLE, + {AArch64_CMPLE_WIDE_PPzZZ_B, + ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLE_WIDE_PPzZZ_H, ARM64_INS_CMPLE, + {AArch64_CMPLE_WIDE_PPzZZ_H, + ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLE_WIDE_PPzZZ_S, ARM64_INS_CMPLE, + {AArch64_CMPLE_WIDE_PPzZZ_S, + ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLO_PPzZI_B, ARM64_INS_CMPLO, + {AArch64_CMPLO_PPzZI_B, + ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLO_PPzZI_D, ARM64_INS_CMPLO, + {AArch64_CMPLO_PPzZI_D, + ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLO_PPzZI_H, ARM64_INS_CMPLO, + {AArch64_CMPLO_PPzZI_H, + ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLO_PPzZI_S, ARM64_INS_CMPLO, + {AArch64_CMPLO_PPzZI_S, + ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLO_WIDE_PPzZZ_B, ARM64_INS_CMPLO, + {AArch64_CMPLO_WIDE_PPzZZ_B, + ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLO_WIDE_PPzZZ_H, ARM64_INS_CMPLO, + {AArch64_CMPLO_WIDE_PPzZZ_H, + ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLO_WIDE_PPzZZ_S, ARM64_INS_CMPLO, + {AArch64_CMPLO_WIDE_PPzZZ_S, + ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLS_PPzZI_B, ARM64_INS_CMPLS, + {AArch64_CMPLS_PPzZI_B, + ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLS_PPzZI_D, ARM64_INS_CMPLS, + {AArch64_CMPLS_PPzZI_D, + ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLS_PPzZI_H, ARM64_INS_CMPLS, + {AArch64_CMPLS_PPzZI_H, + ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLS_PPzZI_S, ARM64_INS_CMPLS, + {AArch64_CMPLS_PPzZI_S, + ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLS_WIDE_PPzZZ_B, ARM64_INS_CMPLS, + {AArch64_CMPLS_WIDE_PPzZZ_B, + ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLS_WIDE_PPzZZ_H, ARM64_INS_CMPLS, + {AArch64_CMPLS_WIDE_PPzZZ_H, + ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLS_WIDE_PPzZZ_S, ARM64_INS_CMPLS, + {AArch64_CMPLS_WIDE_PPzZZ_S, + ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLT_PPzZI_B, ARM64_INS_CMPLT, + {AArch64_CMPLT_PPzZI_B, + ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLT_PPzZI_D, ARM64_INS_CMPLT, + {AArch64_CMPLT_PPzZI_D, + ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLT_PPzZI_H, ARM64_INS_CMPLT, + {AArch64_CMPLT_PPzZI_H, + ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLT_PPzZI_S, ARM64_INS_CMPLT, + {AArch64_CMPLT_PPzZI_S, + ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLT_WIDE_PPzZZ_B, ARM64_INS_CMPLT, + {AArch64_CMPLT_WIDE_PPzZZ_B, + ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLT_WIDE_PPzZZ_H, ARM64_INS_CMPLT, + {AArch64_CMPLT_WIDE_PPzZZ_H, + ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPLT_WIDE_PPzZZ_S, ARM64_INS_CMPLT, + {AArch64_CMPLT_WIDE_PPzZZ_S, + ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_PPzZI_B, ARM64_INS_CMPNE, + {AArch64_CMPNE_PPzZI_B, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_PPzZI_D, ARM64_INS_CMPNE, + {AArch64_CMPNE_PPzZI_D, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_PPzZI_H, ARM64_INS_CMPNE, + {AArch64_CMPNE_PPzZI_H, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_PPzZI_S, ARM64_INS_CMPNE, + {AArch64_CMPNE_PPzZI_S, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_PPzZZ_B, ARM64_INS_CMPNE, + {AArch64_CMPNE_PPzZZ_B, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_PPzZZ_D, ARM64_INS_CMPNE, + {AArch64_CMPNE_PPzZZ_D, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_PPzZZ_H, ARM64_INS_CMPNE, + {AArch64_CMPNE_PPzZZ_H, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_PPzZZ_S, ARM64_INS_CMPNE, + {AArch64_CMPNE_PPzZZ_S, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_WIDE_PPzZZ_B, ARM64_INS_CMPNE, + {AArch64_CMPNE_WIDE_PPzZZ_B, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_WIDE_PPzZZ_H, ARM64_INS_CMPNE, + {AArch64_CMPNE_WIDE_PPzZZ_H, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMPNE_WIDE_PPzZZ_S, ARM64_INS_CMPNE, + {AArch64_CMPNE_WIDE_PPzZZ_S, + ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMTSTv16i8, ARM64_INS_CMTST, + {AArch64_CMTSTv16i8, + ARM64_INS_CMTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMTSTv1i64, ARM64_INS_CMTST, + {AArch64_CMTSTv1i64, + ARM64_INS_CMTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMTSTv2i32, ARM64_INS_CMTST, + {AArch64_CMTSTv2i32, + ARM64_INS_CMTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMTSTv2i64, ARM64_INS_CMTST, + {AArch64_CMTSTv2i64, + ARM64_INS_CMTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMTSTv4i16, ARM64_INS_CMTST, + {AArch64_CMTSTv4i16, + ARM64_INS_CMTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMTSTv4i32, ARM64_INS_CMTST, + {AArch64_CMTSTv4i32, + ARM64_INS_CMTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMTSTv8i16, ARM64_INS_CMTST, + {AArch64_CMTSTv8i16, + ARM64_INS_CMTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CMTSTv8i8, ARM64_INS_CMTST, + {AArch64_CMTSTv8i8, + ARM64_INS_CMTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNOT_ZPmZ_B, ARM64_INS_CNOT, + {AArch64_CNOT_ZPmZ_B, + ARM64_INS_CNOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNOT_ZPmZ_D, ARM64_INS_CNOT, + {AArch64_CNOT_ZPmZ_D, + ARM64_INS_CNOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNOT_ZPmZ_H, ARM64_INS_CNOT, + {AArch64_CNOT_ZPmZ_H, + ARM64_INS_CNOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNOT_ZPmZ_S, ARM64_INS_CNOT, + {AArch64_CNOT_ZPmZ_S, + ARM64_INS_CNOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTB_XPiI, ARM64_INS_CNTB, + {AArch64_CNTB_XPiI, + ARM64_INS_CNTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTD_XPiI, ARM64_INS_CNTD, + {AArch64_CNTD_XPiI, + ARM64_INS_CNTD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTH_XPiI, ARM64_INS_CNTH, + {AArch64_CNTH_XPiI, + ARM64_INS_CNTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTP_XPP_B, ARM64_INS_CNTP, + {AArch64_CNTP_XPP_B, + ARM64_INS_CNTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTP_XPP_D, ARM64_INS_CNTP, + {AArch64_CNTP_XPP_D, + ARM64_INS_CNTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTP_XPP_H, ARM64_INS_CNTP, + {AArch64_CNTP_XPP_H, + ARM64_INS_CNTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTP_XPP_S, ARM64_INS_CNTP, + {AArch64_CNTP_XPP_S, + ARM64_INS_CNTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTW_XPiI, ARM64_INS_CNTW, + {AArch64_CNTW_XPiI, + ARM64_INS_CNTW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNT_ZPmZ_B, ARM64_INS_CNT, + {AArch64_CNT_ZPmZ_B, + ARM64_INS_CNT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNT_ZPmZ_D, ARM64_INS_CNT, + {AArch64_CNT_ZPmZ_D, + ARM64_INS_CNT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNT_ZPmZ_H, ARM64_INS_CNT, + {AArch64_CNT_ZPmZ_H, + ARM64_INS_CNT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNT_ZPmZ_S, ARM64_INS_CNT, + {AArch64_CNT_ZPmZ_S, + ARM64_INS_CNT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTv16i8, ARM64_INS_CNT, + {AArch64_CNTv16i8, + ARM64_INS_CNT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CNTv8i8, ARM64_INS_CNT, + {AArch64_CNTv8i8, + ARM64_INS_CNT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_COMPACT_ZPZ_D, ARM64_INS_COMPACT, + {AArch64_COMPACT_ZPZ_D, + ARM64_INS_COMPACT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_COMPACT_ZPZ_S, ARM64_INS_COMPACT, + {AArch64_COMPACT_ZPZ_S, + ARM64_INS_COMPACT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmI_B, ARM64_INS_CPY, + {AArch64_CPY_ZPmI_B, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmI_D, ARM64_INS_CPY, + {AArch64_CPY_ZPmI_D, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmI_H, ARM64_INS_CPY, + {AArch64_CPY_ZPmI_H, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmI_S, ARM64_INS_CPY, + {AArch64_CPY_ZPmI_S, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmR_B, ARM64_INS_CPY, + {AArch64_CPY_ZPmR_B, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmR_D, ARM64_INS_CPY, + {AArch64_CPY_ZPmR_D, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmR_H, ARM64_INS_CPY, + {AArch64_CPY_ZPmR_H, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmR_S, ARM64_INS_CPY, + {AArch64_CPY_ZPmR_S, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmV_B, ARM64_INS_CPY, + {AArch64_CPY_ZPmV_B, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmV_D, ARM64_INS_CPY, + {AArch64_CPY_ZPmV_D, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmV_H, ARM64_INS_CPY, + {AArch64_CPY_ZPmV_H, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPmV_S, ARM64_INS_CPY, + {AArch64_CPY_ZPmV_S, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPzI_B, ARM64_INS_CPY, + {AArch64_CPY_ZPzI_B, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPzI_D, ARM64_INS_CPY, + {AArch64_CPY_ZPzI_D, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPzI_H, ARM64_INS_CPY, + {AArch64_CPY_ZPzI_H, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPY_ZPzI_S, ARM64_INS_CPY, + {AArch64_CPY_ZPzI_S, + ARM64_INS_CPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPYi16, ARM64_INS_DUP, + {AArch64_CPYi16, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPYi32, ARM64_INS_DUP, + {AArch64_CPYi32, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPYi64, ARM64_INS_DUP, + {AArch64_CPYi64, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CPYi8, ARM64_INS_DUP, + {AArch64_CPYi8, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CRC32Brr, ARM64_INS_CRC32B, + {AArch64_CRC32Brr, + ARM64_INS_CRC32B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CRC32CBrr, ARM64_INS_CRC32CB, + {AArch64_CRC32CBrr, + ARM64_INS_CRC32CB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CRC32CHrr, ARM64_INS_CRC32CH, + {AArch64_CRC32CHrr, + ARM64_INS_CRC32CH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CRC32CWrr, ARM64_INS_CRC32CW, + {AArch64_CRC32CWrr, + ARM64_INS_CRC32CW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CRC32CXrr, ARM64_INS_CRC32CX, + {AArch64_CRC32CXrr, + ARM64_INS_CRC32CX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CRC32Hrr, ARM64_INS_CRC32H, + {AArch64_CRC32Hrr, + ARM64_INS_CRC32H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CRC32Wrr, ARM64_INS_CRC32W, + {AArch64_CRC32Wrr, + ARM64_INS_CRC32W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CRC32Xrr, ARM64_INS_CRC32X, + {AArch64_CRC32Xrr, + ARM64_INS_CRC32X, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CSELWr, ARM64_INS_CSEL, + {AArch64_CSELWr, + ARM64_INS_CSEL, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CSELXr, ARM64_INS_CSEL, + {AArch64_CSELXr, + ARM64_INS_CSEL, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CSINCWr, ARM64_INS_CSINC, + {AArch64_CSINCWr, + ARM64_INS_CSINC, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CSINCXr, ARM64_INS_CSINC, + {AArch64_CSINCXr, + ARM64_INS_CSINC, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CSINVWr, ARM64_INS_CSINV, + {AArch64_CSINVWr, + ARM64_INS_CSINV, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CSINVXr, ARM64_INS_CSINV, + {AArch64_CSINVXr, + ARM64_INS_CSINV, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CSNEGWr, ARM64_INS_CSNEG, + {AArch64_CSNEGWr, + ARM64_INS_CSNEG, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CSNEGXr, ARM64_INS_CSNEG, + {AArch64_CSNEGXr, + ARM64_INS_CSNEG, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CTERMEQ_WW, ARM64_INS_CTERMEQ, + {AArch64_CTERMEQ_WW, + ARM64_INS_CTERMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CTERMEQ_XX, ARM64_INS_CTERMEQ, + {AArch64_CTERMEQ_XX, + ARM64_INS_CTERMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CTERMNE_WW, ARM64_INS_CTERMNE, + {AArch64_CTERMNE_WW, + ARM64_INS_CTERMNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_CTERMNE_XX, ARM64_INS_CTERMNE, + {AArch64_CTERMNE_XX, + ARM64_INS_CTERMNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DCPS1, ARM64_INS_DCPS1, + {AArch64_DCPS1, + ARM64_INS_DCPS1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DCPS2, ARM64_INS_DCPS2, + {AArch64_DCPS2, + ARM64_INS_DCPS2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DCPS3, ARM64_INS_DCPS3, + {AArch64_DCPS3, + ARM64_INS_DCPS3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECB_XPiI, ARM64_INS_DECB, + {AArch64_DECB_XPiI, + ARM64_INS_DECB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECD_XPiI, ARM64_INS_DECD, + {AArch64_DECD_XPiI, + ARM64_INS_DECD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECD_ZPiI, ARM64_INS_DECD, + {AArch64_DECD_ZPiI, + ARM64_INS_DECD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECH_XPiI, ARM64_INS_DECH, + {AArch64_DECH_XPiI, + ARM64_INS_DECH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECH_ZPiI, ARM64_INS_DECH, + {AArch64_DECH_ZPiI, + ARM64_INS_DECH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECP_XP_B, ARM64_INS_DECP, + {AArch64_DECP_XP_B, + ARM64_INS_DECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECP_XP_D, ARM64_INS_DECP, + {AArch64_DECP_XP_D, + ARM64_INS_DECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECP_XP_H, ARM64_INS_DECP, + {AArch64_DECP_XP_H, + ARM64_INS_DECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECP_XP_S, ARM64_INS_DECP, + {AArch64_DECP_XP_S, + ARM64_INS_DECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECP_ZP_D, ARM64_INS_DECP, + {AArch64_DECP_ZP_D, + ARM64_INS_DECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECP_ZP_H, ARM64_INS_DECP, + {AArch64_DECP_ZP_H, + ARM64_INS_DECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECP_ZP_S, ARM64_INS_DECP, + {AArch64_DECP_ZP_S, + ARM64_INS_DECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECW_XPiI, ARM64_INS_DECW, + {AArch64_DECW_XPiI, + ARM64_INS_DECW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DECW_ZPiI, ARM64_INS_DECW, + {AArch64_DECW_ZPiI, + ARM64_INS_DECW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DMB, ARM64_INS_DMB, + {AArch64_DMB, + ARM64_INS_DMB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DRPS, ARM64_INS_DRPS, + {AArch64_DRPS, + ARM64_INS_DRPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DSB, ARM64_INS_DSB, + {AArch64_DSB, + ARM64_INS_DSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPM_ZI, ARM64_INS_DUPM, + {AArch64_DUPM_ZI, + ARM64_INS_DUPM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZI_B, ARM64_INS_DUP, + {AArch64_DUP_ZI_B, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZI_D, ARM64_INS_DUP, + {AArch64_DUP_ZI_D, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZI_H, ARM64_INS_DUP, + {AArch64_DUP_ZI_H, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZI_S, ARM64_INS_DUP, + {AArch64_DUP_ZI_S, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZR_B, ARM64_INS_DUP, + {AArch64_DUP_ZR_B, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZR_D, ARM64_INS_DUP, + {AArch64_DUP_ZR_D, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZR_H, ARM64_INS_DUP, + {AArch64_DUP_ZR_H, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZR_S, ARM64_INS_DUP, + {AArch64_DUP_ZR_S, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZZI_B, ARM64_INS_DUP, + {AArch64_DUP_ZZI_B, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZZI_D, ARM64_INS_DUP, + {AArch64_DUP_ZZI_D, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZZI_H, ARM64_INS_DUP, + {AArch64_DUP_ZZI_H, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZZI_Q, ARM64_INS_DUP, + {AArch64_DUP_ZZI_Q, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUP_ZZI_S, ARM64_INS_DUP, + {AArch64_DUP_ZZI_S, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv16i8gpr, ARM64_INS_DUP, + {AArch64_DUPv16i8gpr, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv16i8lane, ARM64_INS_DUP, + {AArch64_DUPv16i8lane, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv2i32gpr, ARM64_INS_DUP, + {AArch64_DUPv2i32gpr, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv2i32lane, ARM64_INS_DUP, + {AArch64_DUPv2i32lane, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv2i64gpr, ARM64_INS_DUP, + {AArch64_DUPv2i64gpr, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv2i64lane, ARM64_INS_DUP, + {AArch64_DUPv2i64lane, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv4i16gpr, ARM64_INS_DUP, + {AArch64_DUPv4i16gpr, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv4i16lane, ARM64_INS_DUP, + {AArch64_DUPv4i16lane, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv4i32gpr, ARM64_INS_DUP, + {AArch64_DUPv4i32gpr, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv4i32lane, ARM64_INS_DUP, + {AArch64_DUPv4i32lane, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv8i16gpr, ARM64_INS_DUP, + {AArch64_DUPv8i16gpr, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv8i16lane, ARM64_INS_DUP, + {AArch64_DUPv8i16lane, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv8i8gpr, ARM64_INS_DUP, + {AArch64_DUPv8i8gpr, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_DUPv8i8lane, ARM64_INS_DUP, + {AArch64_DUPv8i8lane, + ARM64_INS_DUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EONWrs, ARM64_INS_EON, + {AArch64_EONWrs, + ARM64_INS_EON, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EONXrs, ARM64_INS_EON, + {AArch64_EONXrs, + ARM64_INS_EON, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EOR3, ARM64_INS_EOR3, + {AArch64_EOR3, + ARM64_INS_EOR3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORS_PPzPP, ARM64_INS_EORS, + {AArch64_EORS_PPzPP, + ARM64_INS_EORS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORV_VPZ_B, ARM64_INS_EORV, + {AArch64_EORV_VPZ_B, + ARM64_INS_EORV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORV_VPZ_D, ARM64_INS_EORV, + {AArch64_EORV_VPZ_D, + ARM64_INS_EORV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORV_VPZ_H, ARM64_INS_EORV, + {AArch64_EORV_VPZ_H, + ARM64_INS_EORV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORV_VPZ_S, ARM64_INS_EORV, + {AArch64_EORV_VPZ_S, + ARM64_INS_EORV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORWri, ARM64_INS_EOR, + {AArch64_EORWri, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORWrs, ARM64_INS_EOR, + {AArch64_EORWrs, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORXri, ARM64_INS_EOR, + {AArch64_EORXri, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORXrs, ARM64_INS_EOR, + {AArch64_EORXrs, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EOR_PPzPP, ARM64_INS_EOR, + {AArch64_EOR_PPzPP, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EOR_ZI, ARM64_INS_EOR, + {AArch64_EOR_ZI, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EOR_ZPmZ_B, ARM64_INS_EOR, + {AArch64_EOR_ZPmZ_B, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EOR_ZPmZ_D, ARM64_INS_EOR, + {AArch64_EOR_ZPmZ_D, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EOR_ZPmZ_H, ARM64_INS_EOR, + {AArch64_EOR_ZPmZ_H, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EOR_ZPmZ_S, ARM64_INS_EOR, + {AArch64_EOR_ZPmZ_S, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EOR_ZZZ, ARM64_INS_EOR, + {AArch64_EOR_ZZZ, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORv16i8, ARM64_INS_EOR, + {AArch64_EORv16i8, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EORv8i8, ARM64_INS_EOR, + {AArch64_EORv8i8, + ARM64_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ERET, ARM64_INS_ERET, + {AArch64_ERET, + ARM64_INS_ERET, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ERETAA, ARM64_INS_ERETAA, + {AArch64_ERETAA, + ARM64_INS_ERETAA, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, ARM64_REG_SP, 0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ERETAB, ARM64_INS_ERETAB, + {AArch64_ERETAB, + ARM64_INS_ERETAB, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, ARM64_REG_SP, 0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EXTRWrri, ARM64_INS_EXTR, + {AArch64_EXTRWrri, + ARM64_INS_EXTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EXTRXrri, ARM64_INS_EXTR, + {AArch64_EXTRXrri, + ARM64_INS_EXTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EXT_ZZI, ARM64_INS_EXT, + {AArch64_EXT_ZZI, + ARM64_INS_EXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EXTv16i8, ARM64_INS_EXT, + {AArch64_EXTv16i8, + ARM64_INS_EXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_EXTv8i8, ARM64_INS_EXT, + {AArch64_EXTv8i8, + ARM64_INS_EXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABD16, ARM64_INS_FABD, + {AArch64_FABD16, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABD32, ARM64_INS_FABD, + {AArch64_FABD32, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABD64, ARM64_INS_FABD, + {AArch64_FABD64, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABD_ZPmZ_D, ARM64_INS_FABD, + {AArch64_FABD_ZPmZ_D, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABD_ZPmZ_H, ARM64_INS_FABD, + {AArch64_FABD_ZPmZ_H, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABD_ZPmZ_S, ARM64_INS_FABD, + {AArch64_FABD_ZPmZ_S, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABDv2f32, ARM64_INS_FABD, + {AArch64_FABDv2f32, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABDv2f64, ARM64_INS_FABD, + {AArch64_FABDv2f64, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABDv4f16, ARM64_INS_FABD, + {AArch64_FABDv4f16, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABDv4f32, ARM64_INS_FABD, + {AArch64_FABDv4f32, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABDv8f16, ARM64_INS_FABD, + {AArch64_FABDv8f16, + ARM64_INS_FABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABSDr, ARM64_INS_FABS, + {AArch64_FABSDr, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABSHr, ARM64_INS_FABS, + {AArch64_FABSHr, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABSSr, ARM64_INS_FABS, + {AArch64_FABSSr, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABS_ZPmZ_D, ARM64_INS_FABS, + {AArch64_FABS_ZPmZ_D, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABS_ZPmZ_H, ARM64_INS_FABS, + {AArch64_FABS_ZPmZ_H, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABS_ZPmZ_S, ARM64_INS_FABS, + {AArch64_FABS_ZPmZ_S, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABSv2f32, ARM64_INS_FABS, + {AArch64_FABSv2f32, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABSv2f64, ARM64_INS_FABS, + {AArch64_FABSv2f64, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABSv4f16, ARM64_INS_FABS, + {AArch64_FABSv4f16, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABSv4f32, ARM64_INS_FABS, + {AArch64_FABSv4f32, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FABSv8f16, ARM64_INS_FABS, + {AArch64_FABSv8f16, + ARM64_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGE16, ARM64_INS_FACGE, + {AArch64_FACGE16, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGE32, ARM64_INS_FACGE, + {AArch64_FACGE32, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGE64, ARM64_INS_FACGE, + {AArch64_FACGE64, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGE_PPzZZ_D, ARM64_INS_FACGE, + {AArch64_FACGE_PPzZZ_D, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGE_PPzZZ_H, ARM64_INS_FACGE, + {AArch64_FACGE_PPzZZ_H, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGE_PPzZZ_S, ARM64_INS_FACGE, + {AArch64_FACGE_PPzZZ_S, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGEv2f32, ARM64_INS_FACGE, + {AArch64_FACGEv2f32, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGEv2f64, ARM64_INS_FACGE, + {AArch64_FACGEv2f64, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGEv4f16, ARM64_INS_FACGE, + {AArch64_FACGEv4f16, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGEv4f32, ARM64_INS_FACGE, + {AArch64_FACGEv4f32, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGEv8f16, ARM64_INS_FACGE, + {AArch64_FACGEv8f16, + ARM64_INS_FACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGT16, ARM64_INS_FACGT, + {AArch64_FACGT16, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGT32, ARM64_INS_FACGT, + {AArch64_FACGT32, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGT64, ARM64_INS_FACGT, + {AArch64_FACGT64, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGT_PPzZZ_D, ARM64_INS_FACGT, + {AArch64_FACGT_PPzZZ_D, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGT_PPzZZ_H, ARM64_INS_FACGT, + {AArch64_FACGT_PPzZZ_H, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGT_PPzZZ_S, ARM64_INS_FACGT, + {AArch64_FACGT_PPzZZ_S, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGTv2f32, ARM64_INS_FACGT, + {AArch64_FACGTv2f32, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGTv2f64, ARM64_INS_FACGT, + {AArch64_FACGTv2f64, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGTv4f16, ARM64_INS_FACGT, + {AArch64_FACGTv4f16, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGTv4f32, ARM64_INS_FACGT, + {AArch64_FACGTv4f32, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FACGTv8f16, ARM64_INS_FACGT, + {AArch64_FACGTv8f16, + ARM64_INS_FACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDA_VPZ_D, ARM64_INS_FADDA, + {AArch64_FADDA_VPZ_D, + ARM64_INS_FADDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDA_VPZ_H, ARM64_INS_FADDA, + {AArch64_FADDA_VPZ_H, + ARM64_INS_FADDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDA_VPZ_S, ARM64_INS_FADDA, + {AArch64_FADDA_VPZ_S, + ARM64_INS_FADDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDDrr, ARM64_INS_FADD, + {AArch64_FADDDrr, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDHrr, ARM64_INS_FADD, + {AArch64_FADDHrr, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDPv2f32, ARM64_INS_FADDP, + {AArch64_FADDPv2f32, + ARM64_INS_FADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDPv2f64, ARM64_INS_FADDP, + {AArch64_FADDPv2f64, + ARM64_INS_FADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDPv2i16p, ARM64_INS_FADDP, + {AArch64_FADDPv2i16p, + ARM64_INS_FADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDPv2i32p, ARM64_INS_FADDP, + {AArch64_FADDPv2i32p, + ARM64_INS_FADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDPv2i64p, ARM64_INS_FADDP, + {AArch64_FADDPv2i64p, + ARM64_INS_FADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDPv4f16, ARM64_INS_FADDP, + {AArch64_FADDPv4f16, + ARM64_INS_FADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDPv4f32, ARM64_INS_FADDP, + {AArch64_FADDPv4f32, + ARM64_INS_FADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDPv8f16, ARM64_INS_FADDP, + {AArch64_FADDPv8f16, + ARM64_INS_FADDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDSrr, ARM64_INS_FADD, + {AArch64_FADDSrr, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDV_VPZ_D, ARM64_INS_FADDV, + {AArch64_FADDV_VPZ_D, + ARM64_INS_FADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDV_VPZ_H, ARM64_INS_FADDV, + {AArch64_FADDV_VPZ_H, + ARM64_INS_FADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDV_VPZ_S, ARM64_INS_FADDV, + {AArch64_FADDV_VPZ_S, + ARM64_INS_FADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADD_ZPmI_D, ARM64_INS_FADD, + {AArch64_FADD_ZPmI_D, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADD_ZPmI_H, ARM64_INS_FADD, + {AArch64_FADD_ZPmI_H, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADD_ZPmI_S, ARM64_INS_FADD, + {AArch64_FADD_ZPmI_S, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADD_ZPmZ_D, ARM64_INS_FADD, + {AArch64_FADD_ZPmZ_D, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADD_ZPmZ_H, ARM64_INS_FADD, + {AArch64_FADD_ZPmZ_H, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADD_ZPmZ_S, ARM64_INS_FADD, + {AArch64_FADD_ZPmZ_S, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADD_ZZZ_D, ARM64_INS_FADD, + {AArch64_FADD_ZZZ_D, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADD_ZZZ_H, ARM64_INS_FADD, + {AArch64_FADD_ZZZ_H, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADD_ZZZ_S, ARM64_INS_FADD, + {AArch64_FADD_ZZZ_S, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDv2f32, ARM64_INS_FADD, + {AArch64_FADDv2f32, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDv2f64, ARM64_INS_FADD, + {AArch64_FADDv2f64, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDv4f16, ARM64_INS_FADD, + {AArch64_FADDv4f16, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDv4f32, ARM64_INS_FADD, + {AArch64_FADDv4f32, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FADDv8f16, ARM64_INS_FADD, + {AArch64_FADDv8f16, + ARM64_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCADD_ZPmZ_D, ARM64_INS_FCADD, + {AArch64_FCADD_ZPmZ_D, + ARM64_INS_FCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCADD_ZPmZ_H, ARM64_INS_FCADD, + {AArch64_FCADD_ZPmZ_H, + ARM64_INS_FCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCADD_ZPmZ_S, ARM64_INS_FCADD, + {AArch64_FCADD_ZPmZ_S, + ARM64_INS_FCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCADDv2f32, ARM64_INS_FCADD, + {AArch64_FCADDv2f32, + ARM64_INS_FCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCADDv2f64, ARM64_INS_FCADD, + {AArch64_FCADDv2f64, + ARM64_INS_FCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCADDv4f16, ARM64_INS_FCADD, + {AArch64_FCADDv4f16, + ARM64_INS_FCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCADDv4f32, ARM64_INS_FCADD, + {AArch64_FCADDv4f32, + ARM64_INS_FCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCADDv8f16, ARM64_INS_FCADD, + {AArch64_FCADDv8f16, + ARM64_INS_FCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCCMPDrr, ARM64_INS_FCCMP, + {AArch64_FCCMPDrr, + ARM64_INS_FCCMP, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCCMPEDrr, ARM64_INS_FCCMPE, + {AArch64_FCCMPEDrr, + ARM64_INS_FCCMPE, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCCMPEHrr, ARM64_INS_FCCMPE, + {AArch64_FCCMPEHrr, + ARM64_INS_FCCMPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCCMPESrr, ARM64_INS_FCCMPE, + {AArch64_FCCMPESrr, + ARM64_INS_FCCMPE, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCCMPHrr, ARM64_INS_FCCMP, + {AArch64_FCCMPHrr, + ARM64_INS_FCCMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCCMPSrr, ARM64_INS_FCCMP, + {AArch64_FCCMPSrr, + ARM64_INS_FCCMP, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQ16, ARM64_INS_FCMEQ, + {AArch64_FCMEQ16, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQ32, ARM64_INS_FCMEQ, + {AArch64_FCMEQ32, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQ64, ARM64_INS_FCMEQ, + {AArch64_FCMEQ64, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQ_PPzZ0_D, ARM64_INS_FCMEQ, + {AArch64_FCMEQ_PPzZ0_D, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQ_PPzZ0_H, ARM64_INS_FCMEQ, + {AArch64_FCMEQ_PPzZ0_H, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQ_PPzZ0_S, ARM64_INS_FCMEQ, + {AArch64_FCMEQ_PPzZ0_S, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQ_PPzZZ_D, ARM64_INS_FCMEQ, + {AArch64_FCMEQ_PPzZZ_D, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQ_PPzZZ_H, ARM64_INS_FCMEQ, + {AArch64_FCMEQ_PPzZZ_H, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQ_PPzZZ_S, ARM64_INS_FCMEQ, + {AArch64_FCMEQ_PPzZZ_S, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv1i16rz, ARM64_INS_FCMEQ, + {AArch64_FCMEQv1i16rz, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ, + {AArch64_FCMEQv1i32rz, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ, + {AArch64_FCMEQv1i64rz, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv2f32, ARM64_INS_FCMEQ, + {AArch64_FCMEQv2f32, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv2f64, ARM64_INS_FCMEQ, + {AArch64_FCMEQv2f64, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ, + {AArch64_FCMEQv2i32rz, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ, + {AArch64_FCMEQv2i64rz, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv4f16, ARM64_INS_FCMEQ, + {AArch64_FCMEQv4f16, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv4f32, ARM64_INS_FCMEQ, + {AArch64_FCMEQv4f32, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv4i16rz, ARM64_INS_FCMEQ, + {AArch64_FCMEQv4i16rz, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ, + {AArch64_FCMEQv4i32rz, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv8f16, ARM64_INS_FCMEQ, + {AArch64_FCMEQv8f16, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMEQv8i16rz, ARM64_INS_FCMEQ, + {AArch64_FCMEQv8i16rz, + ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGE16, ARM64_INS_FCMGE, + {AArch64_FCMGE16, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGE32, ARM64_INS_FCMGE, + {AArch64_FCMGE32, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGE64, ARM64_INS_FCMGE, + {AArch64_FCMGE64, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGE_PPzZ0_D, ARM64_INS_FCMGE, + {AArch64_FCMGE_PPzZ0_D, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGE_PPzZ0_H, ARM64_INS_FCMGE, + {AArch64_FCMGE_PPzZ0_H, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGE_PPzZ0_S, ARM64_INS_FCMGE, + {AArch64_FCMGE_PPzZ0_S, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGE_PPzZZ_D, ARM64_INS_FCMGE, + {AArch64_FCMGE_PPzZZ_D, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGE_PPzZZ_H, ARM64_INS_FCMGE, + {AArch64_FCMGE_PPzZZ_H, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGE_PPzZZ_S, ARM64_INS_FCMGE, + {AArch64_FCMGE_PPzZZ_S, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv1i16rz, ARM64_INS_FCMGE, + {AArch64_FCMGEv1i16rz, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE, + {AArch64_FCMGEv1i32rz, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE, + {AArch64_FCMGEv1i64rz, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv2f32, ARM64_INS_FCMGE, + {AArch64_FCMGEv2f32, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv2f64, ARM64_INS_FCMGE, + {AArch64_FCMGEv2f64, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE, + {AArch64_FCMGEv2i32rz, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE, + {AArch64_FCMGEv2i64rz, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv4f16, ARM64_INS_FCMGE, + {AArch64_FCMGEv4f16, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv4f32, ARM64_INS_FCMGE, + {AArch64_FCMGEv4f32, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv4i16rz, ARM64_INS_FCMGE, + {AArch64_FCMGEv4i16rz, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE, + {AArch64_FCMGEv4i32rz, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv8f16, ARM64_INS_FCMGE, + {AArch64_FCMGEv8f16, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGEv8i16rz, ARM64_INS_FCMGE, + {AArch64_FCMGEv8i16rz, + ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGT16, ARM64_INS_FCMGT, + {AArch64_FCMGT16, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGT32, ARM64_INS_FCMGT, + {AArch64_FCMGT32, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGT64, ARM64_INS_FCMGT, + {AArch64_FCMGT64, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGT_PPzZ0_D, ARM64_INS_FCMGT, + {AArch64_FCMGT_PPzZ0_D, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGT_PPzZ0_H, ARM64_INS_FCMGT, + {AArch64_FCMGT_PPzZ0_H, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGT_PPzZ0_S, ARM64_INS_FCMGT, + {AArch64_FCMGT_PPzZ0_S, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGT_PPzZZ_D, ARM64_INS_FCMGT, + {AArch64_FCMGT_PPzZZ_D, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGT_PPzZZ_H, ARM64_INS_FCMGT, + {AArch64_FCMGT_PPzZZ_H, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGT_PPzZZ_S, ARM64_INS_FCMGT, + {AArch64_FCMGT_PPzZZ_S, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv1i16rz, ARM64_INS_FCMGT, + {AArch64_FCMGTv1i16rz, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT, + {AArch64_FCMGTv1i32rz, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT, + {AArch64_FCMGTv1i64rz, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv2f32, ARM64_INS_FCMGT, + {AArch64_FCMGTv2f32, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv2f64, ARM64_INS_FCMGT, + {AArch64_FCMGTv2f64, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT, + {AArch64_FCMGTv2i32rz, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT, + {AArch64_FCMGTv2i64rz, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv4f16, ARM64_INS_FCMGT, + {AArch64_FCMGTv4f16, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv4f32, ARM64_INS_FCMGT, + {AArch64_FCMGTv4f32, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv4i16rz, ARM64_INS_FCMGT, + {AArch64_FCMGTv4i16rz, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT, + {AArch64_FCMGTv4i32rz, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv8f16, ARM64_INS_FCMGT, + {AArch64_FCMGTv8f16, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMGTv8i16rz, ARM64_INS_FCMGT, + {AArch64_FCMGTv8i16rz, + ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLA_ZPmZZ_D, ARM64_INS_FCMLA, + {AArch64_FCMLA_ZPmZZ_D, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLA_ZPmZZ_H, ARM64_INS_FCMLA, + {AArch64_FCMLA_ZPmZZ_H, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLA_ZPmZZ_S, ARM64_INS_FCMLA, + {AArch64_FCMLA_ZPmZZ_S, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLA_ZZZI_H, ARM64_INS_FCMLA, + {AArch64_FCMLA_ZZZI_H, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLA_ZZZI_S, ARM64_INS_FCMLA, + {AArch64_FCMLA_ZZZI_S, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLAv2f32, ARM64_INS_FCMLA, + {AArch64_FCMLAv2f32, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLAv2f64, ARM64_INS_FCMLA, + {AArch64_FCMLAv2f64, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLAv4f16, ARM64_INS_FCMLA, + {AArch64_FCMLAv4f16, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLAv4f16_indexed, ARM64_INS_FCMLA, + {AArch64_FCMLAv4f16_indexed, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLAv4f32, ARM64_INS_FCMLA, + {AArch64_FCMLAv4f32, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLAv4f32_indexed, ARM64_INS_FCMLA, + {AArch64_FCMLAv4f32_indexed, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLAv8f16, ARM64_INS_FCMLA, + {AArch64_FCMLAv8f16, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLAv8f16_indexed, ARM64_INS_FCMLA, + {AArch64_FCMLAv8f16_indexed, + ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLE_PPzZ0_D, ARM64_INS_FCMLE, + {AArch64_FCMLE_PPzZ0_D, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLE_PPzZ0_H, ARM64_INS_FCMLE, + {AArch64_FCMLE_PPzZ0_H, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLE_PPzZ0_S, ARM64_INS_FCMLE, + {AArch64_FCMLE_PPzZ0_S, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLEv1i16rz, ARM64_INS_FCMLE, + {AArch64_FCMLEv1i16rz, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE, + {AArch64_FCMLEv1i32rz, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE, + {AArch64_FCMLEv1i64rz, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE, + {AArch64_FCMLEv2i32rz, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE, + {AArch64_FCMLEv2i64rz, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLEv4i16rz, ARM64_INS_FCMLE, + {AArch64_FCMLEv4i16rz, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE, + {AArch64_FCMLEv4i32rz, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLEv8i16rz, ARM64_INS_FCMLE, + {AArch64_FCMLEv8i16rz, + ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLT_PPzZ0_D, ARM64_INS_FCMLT, + {AArch64_FCMLT_PPzZ0_D, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLT_PPzZ0_H, ARM64_INS_FCMLT, + {AArch64_FCMLT_PPzZ0_H, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLT_PPzZ0_S, ARM64_INS_FCMLT, + {AArch64_FCMLT_PPzZ0_S, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLTv1i16rz, ARM64_INS_FCMLT, + {AArch64_FCMLTv1i16rz, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT, + {AArch64_FCMLTv1i32rz, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT, + {AArch64_FCMLTv1i64rz, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT, + {AArch64_FCMLTv2i32rz, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT, + {AArch64_FCMLTv2i64rz, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLTv4i16rz, ARM64_INS_FCMLT, + {AArch64_FCMLTv4i16rz, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT, + {AArch64_FCMLTv4i32rz, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMLTv8i16rz, ARM64_INS_FCMLT, + {AArch64_FCMLTv8i16rz, + ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMNE_PPzZ0_D, ARM64_INS_FCMNE, + {AArch64_FCMNE_PPzZ0_D, + ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMNE_PPzZ0_H, ARM64_INS_FCMNE, + {AArch64_FCMNE_PPzZ0_H, + ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMNE_PPzZ0_S, ARM64_INS_FCMNE, + {AArch64_FCMNE_PPzZ0_S, + ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMNE_PPzZZ_D, ARM64_INS_FCMNE, + {AArch64_FCMNE_PPzZZ_D, + ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMNE_PPzZZ_H, ARM64_INS_FCMNE, + {AArch64_FCMNE_PPzZZ_H, + ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMNE_PPzZZ_S, ARM64_INS_FCMNE, + {AArch64_FCMNE_PPzZZ_S, + ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPDri, ARM64_INS_FCMP, + {AArch64_FCMPDri, + ARM64_INS_FCMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPDrr, ARM64_INS_FCMP, + {AArch64_FCMPDrr, + ARM64_INS_FCMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPEDri, ARM64_INS_FCMPE, + {AArch64_FCMPEDri, + ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPEDrr, ARM64_INS_FCMPE, + {AArch64_FCMPEDrr, + ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPEHri, ARM64_INS_FCMPE, + {AArch64_FCMPEHri, + ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPEHrr, ARM64_INS_FCMPE, + {AArch64_FCMPEHrr, + ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPESri, ARM64_INS_FCMPE, + {AArch64_FCMPESri, + ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPESrr, ARM64_INS_FCMPE, + {AArch64_FCMPESrr, + ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPHri, ARM64_INS_FCMP, + {AArch64_FCMPHri, + ARM64_INS_FCMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPHrr, ARM64_INS_FCMP, + {AArch64_FCMPHrr, + ARM64_INS_FCMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPSri, ARM64_INS_FCMP, + {AArch64_FCMPSri, + ARM64_INS_FCMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMPSrr, ARM64_INS_FCMP, + {AArch64_FCMPSrr, + ARM64_INS_FCMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMUO_PPzZZ_D, ARM64_INS_FCMUO, + {AArch64_FCMUO_PPzZZ_D, + ARM64_INS_FCMUO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMUO_PPzZZ_H, ARM64_INS_FCMUO, + {AArch64_FCMUO_PPzZZ_H, + ARM64_INS_FCMUO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCMUO_PPzZZ_S, ARM64_INS_FCMUO, + {AArch64_FCMUO_PPzZZ_S, + ARM64_INS_FCMUO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCPY_ZPmI_D, ARM64_INS_FCPY, + {AArch64_FCPY_ZPmI_D, + ARM64_INS_FCPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCPY_ZPmI_H, ARM64_INS_FCPY, + {AArch64_FCPY_ZPmI_H, + ARM64_INS_FCPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCPY_ZPmI_S, ARM64_INS_FCPY, + {AArch64_FCPY_ZPmI_S, + ARM64_INS_FCPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCSELDrrr, ARM64_INS_FCSEL, + {AArch64_FCSELDrrr, + ARM64_INS_FCSEL, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCSELHrrr, ARM64_INS_FCSEL, + {AArch64_FCSELHrrr, + ARM64_INS_FCSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCSELSrrr, ARM64_INS_FCSEL, + {AArch64_FCSELSrrr, + ARM64_INS_FCSEL, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASUWDr, ARM64_INS_FCVTAS, + {AArch64_FCVTASUWDr, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASUWHr, ARM64_INS_FCVTAS, + {AArch64_FCVTASUWHr, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASUWSr, ARM64_INS_FCVTAS, + {AArch64_FCVTASUWSr, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASUXDr, ARM64_INS_FCVTAS, + {AArch64_FCVTASUXDr, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASUXHr, ARM64_INS_FCVTAS, + {AArch64_FCVTASUXHr, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASUXSr, ARM64_INS_FCVTAS, + {AArch64_FCVTASUXSr, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASv1f16, ARM64_INS_FCVTAS, + {AArch64_FCVTASv1f16, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASv1i32, ARM64_INS_FCVTAS, + {AArch64_FCVTASv1i32, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASv1i64, ARM64_INS_FCVTAS, + {AArch64_FCVTASv1i64, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASv2f32, ARM64_INS_FCVTAS, + {AArch64_FCVTASv2f32, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASv2f64, ARM64_INS_FCVTAS, + {AArch64_FCVTASv2f64, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASv4f16, ARM64_INS_FCVTAS, + {AArch64_FCVTASv4f16, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASv4f32, ARM64_INS_FCVTAS, + {AArch64_FCVTASv4f32, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTASv8f16, ARM64_INS_FCVTAS, + {AArch64_FCVTASv8f16, + ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU, + {AArch64_FCVTAUUWDr, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUUWHr, ARM64_INS_FCVTAU, + {AArch64_FCVTAUUWHr, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU, + {AArch64_FCVTAUUWSr, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU, + {AArch64_FCVTAUUXDr, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUUXHr, ARM64_INS_FCVTAU, + {AArch64_FCVTAUUXHr, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU, + {AArch64_FCVTAUUXSr, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUv1f16, ARM64_INS_FCVTAU, + {AArch64_FCVTAUv1f16, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU, + {AArch64_FCVTAUv1i32, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU, + {AArch64_FCVTAUv1i64, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU, + {AArch64_FCVTAUv2f32, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU, + {AArch64_FCVTAUv2f64, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUv4f16, ARM64_INS_FCVTAU, + {AArch64_FCVTAUv4f16, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU, + {AArch64_FCVTAUv4f32, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTAUv8f16, ARM64_INS_FCVTAU, + {AArch64_FCVTAUv8f16, + ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTDHr, ARM64_INS_FCVT, + {AArch64_FCVTDHr, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTDSr, ARM64_INS_FCVT, + {AArch64_FCVTDSr, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTHDr, ARM64_INS_FCVT, + {AArch64_FCVTHDr, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTHSr, ARM64_INS_FCVT, + {AArch64_FCVTHSr, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTLv2i32, ARM64_INS_FCVTL, + {AArch64_FCVTLv2i32, + ARM64_INS_FCVTL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTLv4i16, ARM64_INS_FCVTL, + {AArch64_FCVTLv4i16, + ARM64_INS_FCVTL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTLv4i32, ARM64_INS_FCVTL2, + {AArch64_FCVTLv4i32, + ARM64_INS_FCVTL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTLv8i16, ARM64_INS_FCVTL2, + {AArch64_FCVTLv8i16, + ARM64_INS_FCVTL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS, + {AArch64_FCVTMSUWDr, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSUWHr, ARM64_INS_FCVTMS, + {AArch64_FCVTMSUWHr, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS, + {AArch64_FCVTMSUWSr, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS, + {AArch64_FCVTMSUXDr, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSUXHr, ARM64_INS_FCVTMS, + {AArch64_FCVTMSUXHr, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS, + {AArch64_FCVTMSUXSr, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSv1f16, ARM64_INS_FCVTMS, + {AArch64_FCVTMSv1f16, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS, + {AArch64_FCVTMSv1i32, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS, + {AArch64_FCVTMSv1i64, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS, + {AArch64_FCVTMSv2f32, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS, + {AArch64_FCVTMSv2f64, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSv4f16, ARM64_INS_FCVTMS, + {AArch64_FCVTMSv4f16, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS, + {AArch64_FCVTMSv4f32, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMSv8f16, ARM64_INS_FCVTMS, + {AArch64_FCVTMSv8f16, + ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU, + {AArch64_FCVTMUUWDr, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUUWHr, ARM64_INS_FCVTMU, + {AArch64_FCVTMUUWHr, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU, + {AArch64_FCVTMUUWSr, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU, + {AArch64_FCVTMUUXDr, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUUXHr, ARM64_INS_FCVTMU, + {AArch64_FCVTMUUXHr, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU, + {AArch64_FCVTMUUXSr, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUv1f16, ARM64_INS_FCVTMU, + {AArch64_FCVTMUv1f16, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU, + {AArch64_FCVTMUv1i32, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU, + {AArch64_FCVTMUv1i64, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU, + {AArch64_FCVTMUv2f32, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU, + {AArch64_FCVTMUv2f64, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUv4f16, ARM64_INS_FCVTMU, + {AArch64_FCVTMUv4f16, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU, + {AArch64_FCVTMUv4f32, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTMUv8f16, ARM64_INS_FCVTMU, + {AArch64_FCVTMUv8f16, + ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS, + {AArch64_FCVTNSUWDr, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSUWHr, ARM64_INS_FCVTNS, + {AArch64_FCVTNSUWHr, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS, + {AArch64_FCVTNSUWSr, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS, + {AArch64_FCVTNSUXDr, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSUXHr, ARM64_INS_FCVTNS, + {AArch64_FCVTNSUXHr, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS, + {AArch64_FCVTNSUXSr, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSv1f16, ARM64_INS_FCVTNS, + {AArch64_FCVTNSv1f16, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS, + {AArch64_FCVTNSv1i32, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS, + {AArch64_FCVTNSv1i64, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS, + {AArch64_FCVTNSv2f32, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS, + {AArch64_FCVTNSv2f64, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSv4f16, ARM64_INS_FCVTNS, + {AArch64_FCVTNSv4f16, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS, + {AArch64_FCVTNSv4f32, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNSv8f16, ARM64_INS_FCVTNS, + {AArch64_FCVTNSv8f16, + ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU, + {AArch64_FCVTNUUWDr, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUUWHr, ARM64_INS_FCVTNU, + {AArch64_FCVTNUUWHr, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU, + {AArch64_FCVTNUUWSr, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU, + {AArch64_FCVTNUUXDr, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUUXHr, ARM64_INS_FCVTNU, + {AArch64_FCVTNUUXHr, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU, + {AArch64_FCVTNUUXSr, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUv1f16, ARM64_INS_FCVTNU, + {AArch64_FCVTNUv1f16, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU, + {AArch64_FCVTNUv1i32, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU, + {AArch64_FCVTNUv1i64, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU, + {AArch64_FCVTNUv2f32, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU, + {AArch64_FCVTNUv2f64, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUv4f16, ARM64_INS_FCVTNU, + {AArch64_FCVTNUv4f16, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU, + {AArch64_FCVTNUv4f32, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNUv8f16, ARM64_INS_FCVTNU, + {AArch64_FCVTNUv8f16, + ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNv2i32, ARM64_INS_FCVTN, + {AArch64_FCVTNv2i32, + ARM64_INS_FCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNv4i16, ARM64_INS_FCVTN, + {AArch64_FCVTNv4i16, + ARM64_INS_FCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNv4i32, ARM64_INS_FCVTN2, + {AArch64_FCVTNv4i32, + ARM64_INS_FCVTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTNv8i16, ARM64_INS_FCVTN2, + {AArch64_FCVTNv8i16, + ARM64_INS_FCVTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS, + {AArch64_FCVTPSUWDr, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSUWHr, ARM64_INS_FCVTPS, + {AArch64_FCVTPSUWHr, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS, + {AArch64_FCVTPSUWSr, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS, + {AArch64_FCVTPSUXDr, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSUXHr, ARM64_INS_FCVTPS, + {AArch64_FCVTPSUXHr, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS, + {AArch64_FCVTPSUXSr, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSv1f16, ARM64_INS_FCVTPS, + {AArch64_FCVTPSv1f16, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS, + {AArch64_FCVTPSv1i32, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS, + {AArch64_FCVTPSv1i64, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS, + {AArch64_FCVTPSv2f32, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS, + {AArch64_FCVTPSv2f64, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSv4f16, ARM64_INS_FCVTPS, + {AArch64_FCVTPSv4f16, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS, + {AArch64_FCVTPSv4f32, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPSv8f16, ARM64_INS_FCVTPS, + {AArch64_FCVTPSv8f16, + ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU, + {AArch64_FCVTPUUWDr, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUUWHr, ARM64_INS_FCVTPU, + {AArch64_FCVTPUUWHr, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU, + {AArch64_FCVTPUUWSr, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU, + {AArch64_FCVTPUUXDr, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUUXHr, ARM64_INS_FCVTPU, + {AArch64_FCVTPUUXHr, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU, + {AArch64_FCVTPUUXSr, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUv1f16, ARM64_INS_FCVTPU, + {AArch64_FCVTPUv1f16, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU, + {AArch64_FCVTPUv1i32, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU, + {AArch64_FCVTPUv1i64, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU, + {AArch64_FCVTPUv2f32, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU, + {AArch64_FCVTPUv2f64, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUv4f16, ARM64_INS_FCVTPU, + {AArch64_FCVTPUv4f16, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU, + {AArch64_FCVTPUv4f32, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTPUv8f16, ARM64_INS_FCVTPU, + {AArch64_FCVTPUv8f16, + ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTSDr, ARM64_INS_FCVT, + {AArch64_FCVTSDr, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTSHr, ARM64_INS_FCVT, + {AArch64_FCVTSHr, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN, + {AArch64_FCVTXNv1i64, + ARM64_INS_FCVTXN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN, + {AArch64_FCVTXNv2f32, + ARM64_INS_FCVTXN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2, + {AArch64_FCVTXNv4f32, + ARM64_INS_FCVTXN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS, + {AArch64_FCVTZSSWDri, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSSWHri, ARM64_INS_FCVTZS, + {AArch64_FCVTZSSWHri, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS, + {AArch64_FCVTZSSWSri, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS, + {AArch64_FCVTZSSXDri, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSSXHri, ARM64_INS_FCVTZS, + {AArch64_FCVTZSSXHri, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS, + {AArch64_FCVTZSSXSri, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS, + {AArch64_FCVTZSUWDr, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSUWHr, ARM64_INS_FCVTZS, + {AArch64_FCVTZSUWHr, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS, + {AArch64_FCVTZSUWSr, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS, + {AArch64_FCVTZSUXDr, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSUXHr, ARM64_INS_FCVTZS, + {AArch64_FCVTZSUXHr, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSUXSr, ARM64_INS_FCVTZS, + {AArch64_FCVTZSUXSr, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZS_ZPmZ_DtoD, ARM64_INS_FCVTZS, + {AArch64_FCVTZS_ZPmZ_DtoD, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZS_ZPmZ_DtoS, ARM64_INS_FCVTZS, + {AArch64_FCVTZS_ZPmZ_DtoS, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZS_ZPmZ_HtoD, ARM64_INS_FCVTZS, + {AArch64_FCVTZS_ZPmZ_HtoD, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZS_ZPmZ_HtoH, ARM64_INS_FCVTZS, + {AArch64_FCVTZS_ZPmZ_HtoH, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZS_ZPmZ_HtoS, ARM64_INS_FCVTZS, + {AArch64_FCVTZS_ZPmZ_HtoS, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZS_ZPmZ_StoD, ARM64_INS_FCVTZS, + {AArch64_FCVTZS_ZPmZ_StoD, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZS_ZPmZ_StoS, ARM64_INS_FCVTZS, + {AArch64_FCVTZS_ZPmZ_StoS, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSd, ARM64_INS_FCVTZS, + {AArch64_FCVTZSd, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSh, ARM64_INS_FCVTZS, + {AArch64_FCVTZSh, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSs, ARM64_INS_FCVTZS, + {AArch64_FCVTZSs, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv1f16, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv1f16, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv1i32, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv1i32, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv1i64, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv1i64, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv2f32, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv2f32, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv2f64, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv2f64, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv2i32_shift, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv2i32_shift, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv2i64_shift, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv2i64_shift, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv4f16, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv4f16, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv4f32, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv4f32, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv4i16_shift, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv4i16_shift, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv4i32_shift, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv4i32_shift, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv8f16, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv8f16, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZSv8i16_shift, ARM64_INS_FCVTZS, + {AArch64_FCVTZSv8i16_shift, + ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUSWDri, ARM64_INS_FCVTZU, + {AArch64_FCVTZUSWDri, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUSWHri, ARM64_INS_FCVTZU, + {AArch64_FCVTZUSWHri, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUSWSri, ARM64_INS_FCVTZU, + {AArch64_FCVTZUSWSri, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUSXDri, ARM64_INS_FCVTZU, + {AArch64_FCVTZUSXDri, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUSXHri, ARM64_INS_FCVTZU, + {AArch64_FCVTZUSXHri, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUSXSri, ARM64_INS_FCVTZU, + {AArch64_FCVTZUSXSri, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUUWDr, ARM64_INS_FCVTZU, + {AArch64_FCVTZUUWDr, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUUWHr, ARM64_INS_FCVTZU, + {AArch64_FCVTZUUWHr, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUUWSr, ARM64_INS_FCVTZU, + {AArch64_FCVTZUUWSr, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUUXDr, ARM64_INS_FCVTZU, + {AArch64_FCVTZUUXDr, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUUXHr, ARM64_INS_FCVTZU, + {AArch64_FCVTZUUXHr, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUUXSr, ARM64_INS_FCVTZU, + {AArch64_FCVTZUUXSr, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZU_ZPmZ_DtoD, ARM64_INS_FCVTZU, + {AArch64_FCVTZU_ZPmZ_DtoD, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZU_ZPmZ_DtoS, ARM64_INS_FCVTZU, + {AArch64_FCVTZU_ZPmZ_DtoS, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZU_ZPmZ_HtoD, ARM64_INS_FCVTZU, + {AArch64_FCVTZU_ZPmZ_HtoD, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZU_ZPmZ_HtoH, ARM64_INS_FCVTZU, + {AArch64_FCVTZU_ZPmZ_HtoH, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZU_ZPmZ_HtoS, ARM64_INS_FCVTZU, + {AArch64_FCVTZU_ZPmZ_HtoS, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZU_ZPmZ_StoD, ARM64_INS_FCVTZU, + {AArch64_FCVTZU_ZPmZ_StoD, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZU_ZPmZ_StoS, ARM64_INS_FCVTZU, + {AArch64_FCVTZU_ZPmZ_StoS, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUd, ARM64_INS_FCVTZU, + {AArch64_FCVTZUd, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUh, ARM64_INS_FCVTZU, + {AArch64_FCVTZUh, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUs, ARM64_INS_FCVTZU, + {AArch64_FCVTZUs, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv1f16, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv1f16, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv1i32, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv1i32, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv1i64, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv1i64, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv2f32, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv2f32, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv2f64, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv2f64, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv2i32_shift, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv2i32_shift, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv2i64_shift, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv2i64_shift, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv4f16, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv4f16, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv4f32, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv4f32, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv4i16_shift, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv4i16_shift, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv4i32_shift, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv4i32_shift, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv8f16, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv8f16, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVTZUv8i16_shift, ARM64_INS_FCVTZU, + {AArch64_FCVTZUv8i16_shift, + ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVT_ZPmZ_DtoH, ARM64_INS_FCVT, + {AArch64_FCVT_ZPmZ_DtoH, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVT_ZPmZ_DtoS, ARM64_INS_FCVT, + {AArch64_FCVT_ZPmZ_DtoS, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVT_ZPmZ_HtoD, ARM64_INS_FCVT, + {AArch64_FCVT_ZPmZ_HtoD, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVT_ZPmZ_HtoS, ARM64_INS_FCVT, + {AArch64_FCVT_ZPmZ_HtoS, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVT_ZPmZ_StoD, ARM64_INS_FCVT, + {AArch64_FCVT_ZPmZ_StoD, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FCVT_ZPmZ_StoH, ARM64_INS_FCVT, + {AArch64_FCVT_ZPmZ_StoH, + ARM64_INS_FCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVDrr, ARM64_INS_FDIV, + {AArch64_FDIVDrr, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVHrr, ARM64_INS_FDIV, + {AArch64_FDIVHrr, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVR_ZPmZ_D, ARM64_INS_FDIVR, + {AArch64_FDIVR_ZPmZ_D, + ARM64_INS_FDIVR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVR_ZPmZ_H, ARM64_INS_FDIVR, + {AArch64_FDIVR_ZPmZ_H, + ARM64_INS_FDIVR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVR_ZPmZ_S, ARM64_INS_FDIVR, + {AArch64_FDIVR_ZPmZ_S, + ARM64_INS_FDIVR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVSrr, ARM64_INS_FDIV, + {AArch64_FDIVSrr, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIV_ZPmZ_D, ARM64_INS_FDIV, + {AArch64_FDIV_ZPmZ_D, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIV_ZPmZ_H, ARM64_INS_FDIV, + {AArch64_FDIV_ZPmZ_H, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIV_ZPmZ_S, ARM64_INS_FDIV, + {AArch64_FDIV_ZPmZ_S, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVv2f32, ARM64_INS_FDIV, + {AArch64_FDIVv2f32, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVv2f64, ARM64_INS_FDIV, + {AArch64_FDIVv2f64, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVv4f16, ARM64_INS_FDIV, + {AArch64_FDIVv4f16, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVv4f32, ARM64_INS_FDIV, + {AArch64_FDIVv4f32, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDIVv8f16, ARM64_INS_FDIV, + {AArch64_FDIVv8f16, + ARM64_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDUP_ZI_D, ARM64_INS_FDUP, + {AArch64_FDUP_ZI_D, + ARM64_INS_FDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDUP_ZI_H, ARM64_INS_FDUP, + {AArch64_FDUP_ZI_H, + ARM64_INS_FDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FDUP_ZI_S, ARM64_INS_FDUP, + {AArch64_FDUP_ZI_S, + ARM64_INS_FDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FEXPA_ZZ_D, ARM64_INS_FEXPA, + {AArch64_FEXPA_ZZ_D, + ARM64_INS_FEXPA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FEXPA_ZZ_H, ARM64_INS_FEXPA, + {AArch64_FEXPA_ZZ_H, + ARM64_INS_FEXPA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FEXPA_ZZ_S, ARM64_INS_FEXPA, + {AArch64_FEXPA_ZZ_S, + ARM64_INS_FEXPA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FJCVTZS, ARM64_INS_FJCVTZS, + {AArch64_FJCVTZS, + ARM64_INS_FJCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMADDDrrr, ARM64_INS_FMADD, + {AArch64_FMADDDrrr, + ARM64_INS_FMADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMADDHrrr, ARM64_INS_FMADD, + {AArch64_FMADDHrrr, + ARM64_INS_FMADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMADDSrrr, ARM64_INS_FMADD, + {AArch64_FMADDSrrr, + ARM64_INS_FMADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAD_ZPmZZ_D, ARM64_INS_FMAD, + {AArch64_FMAD_ZPmZZ_D, + ARM64_INS_FMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAD_ZPmZZ_H, ARM64_INS_FMAD, + {AArch64_FMAD_ZPmZZ_H, + ARM64_INS_FMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAD_ZPmZZ_S, ARM64_INS_FMAD, + {AArch64_FMAD_ZPmZZ_S, + ARM64_INS_FMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXDrr, ARM64_INS_FMAX, + {AArch64_FMAXDrr, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXHrr, ARM64_INS_FMAX, + {AArch64_FMAXHrr, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMDrr, ARM64_INS_FMAXNM, + {AArch64_FMAXNMDrr, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMHrr, ARM64_INS_FMAXNM, + {AArch64_FMAXNMHrr, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMPv2f32, ARM64_INS_FMAXNMP, + {AArch64_FMAXNMPv2f32, + ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMPv2f64, ARM64_INS_FMAXNMP, + {AArch64_FMAXNMPv2f64, + ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMPv2i16p, ARM64_INS_FMAXNMP, + {AArch64_FMAXNMPv2i16p, + ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMPv2i32p, ARM64_INS_FMAXNMP, + {AArch64_FMAXNMPv2i32p, + ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMPv2i64p, ARM64_INS_FMAXNMP, + {AArch64_FMAXNMPv2i64p, + ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMPv4f16, ARM64_INS_FMAXNMP, + {AArch64_FMAXNMPv4f16, + ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMPv4f32, ARM64_INS_FMAXNMP, + {AArch64_FMAXNMPv4f32, + ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMPv8f16, ARM64_INS_FMAXNMP, + {AArch64_FMAXNMPv8f16, + ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMSrr, ARM64_INS_FMAXNM, + {AArch64_FMAXNMSrr, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMV_VPZ_D, ARM64_INS_FMAXNMV, + {AArch64_FMAXNMV_VPZ_D, + ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMV_VPZ_H, ARM64_INS_FMAXNMV, + {AArch64_FMAXNMV_VPZ_H, + ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMV_VPZ_S, ARM64_INS_FMAXNMV, + {AArch64_FMAXNMV_VPZ_S, + ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMVv4i16v, ARM64_INS_FMAXNMV, + {AArch64_FMAXNMVv4i16v, + ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMVv4i32v, ARM64_INS_FMAXNMV, + {AArch64_FMAXNMVv4i32v, + ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMVv8i16v, ARM64_INS_FMAXNMV, + {AArch64_FMAXNMVv8i16v, + ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNM_ZPmI_D, ARM64_INS_FMAXNM, + {AArch64_FMAXNM_ZPmI_D, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNM_ZPmI_H, ARM64_INS_FMAXNM, + {AArch64_FMAXNM_ZPmI_H, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNM_ZPmI_S, ARM64_INS_FMAXNM, + {AArch64_FMAXNM_ZPmI_S, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNM_ZPmZ_D, ARM64_INS_FMAXNM, + {AArch64_FMAXNM_ZPmZ_D, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNM_ZPmZ_H, ARM64_INS_FMAXNM, + {AArch64_FMAXNM_ZPmZ_H, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNM_ZPmZ_S, ARM64_INS_FMAXNM, + {AArch64_FMAXNM_ZPmZ_S, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMv2f32, ARM64_INS_FMAXNM, + {AArch64_FMAXNMv2f32, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMv2f64, ARM64_INS_FMAXNM, + {AArch64_FMAXNMv2f64, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMv4f16, ARM64_INS_FMAXNM, + {AArch64_FMAXNMv4f16, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMv4f32, ARM64_INS_FMAXNM, + {AArch64_FMAXNMv4f32, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXNMv8f16, ARM64_INS_FMAXNM, + {AArch64_FMAXNMv8f16, + ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXPv2f32, ARM64_INS_FMAXP, + {AArch64_FMAXPv2f32, + ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXPv2f64, ARM64_INS_FMAXP, + {AArch64_FMAXPv2f64, + ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXPv2i16p, ARM64_INS_FMAXP, + {AArch64_FMAXPv2i16p, + ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXPv2i32p, ARM64_INS_FMAXP, + {AArch64_FMAXPv2i32p, + ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXPv2i64p, ARM64_INS_FMAXP, + {AArch64_FMAXPv2i64p, + ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXPv4f16, ARM64_INS_FMAXP, + {AArch64_FMAXPv4f16, + ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXPv4f32, ARM64_INS_FMAXP, + {AArch64_FMAXPv4f32, + ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXPv8f16, ARM64_INS_FMAXP, + {AArch64_FMAXPv8f16, + ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXSrr, ARM64_INS_FMAX, + {AArch64_FMAXSrr, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXV_VPZ_D, ARM64_INS_FMAXV, + {AArch64_FMAXV_VPZ_D, + ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXV_VPZ_H, ARM64_INS_FMAXV, + {AArch64_FMAXV_VPZ_H, + ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXV_VPZ_S, ARM64_INS_FMAXV, + {AArch64_FMAXV_VPZ_S, + ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXVv4i16v, ARM64_INS_FMAXV, + {AArch64_FMAXVv4i16v, + ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXVv4i32v, ARM64_INS_FMAXV, + {AArch64_FMAXVv4i32v, + ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXVv8i16v, ARM64_INS_FMAXV, + {AArch64_FMAXVv8i16v, + ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAX_ZPmI_D, ARM64_INS_FMAX, + {AArch64_FMAX_ZPmI_D, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAX_ZPmI_H, ARM64_INS_FMAX, + {AArch64_FMAX_ZPmI_H, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAX_ZPmI_S, ARM64_INS_FMAX, + {AArch64_FMAX_ZPmI_S, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAX_ZPmZ_D, ARM64_INS_FMAX, + {AArch64_FMAX_ZPmZ_D, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAX_ZPmZ_H, ARM64_INS_FMAX, + {AArch64_FMAX_ZPmZ_H, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAX_ZPmZ_S, ARM64_INS_FMAX, + {AArch64_FMAX_ZPmZ_S, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXv2f32, ARM64_INS_FMAX, + {AArch64_FMAXv2f32, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXv2f64, ARM64_INS_FMAX, + {AArch64_FMAXv2f64, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXv4f16, ARM64_INS_FMAX, + {AArch64_FMAXv4f16, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXv4f32, ARM64_INS_FMAX, + {AArch64_FMAXv4f32, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMAXv8f16, ARM64_INS_FMAX, + {AArch64_FMAXv8f16, + ARM64_INS_FMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINDrr, ARM64_INS_FMIN, + {AArch64_FMINDrr, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINHrr, ARM64_INS_FMIN, + {AArch64_FMINHrr, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMDrr, ARM64_INS_FMINNM, + {AArch64_FMINNMDrr, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMHrr, ARM64_INS_FMINNM, + {AArch64_FMINNMHrr, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMPv2f32, ARM64_INS_FMINNMP, + {AArch64_FMINNMPv2f32, + ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMPv2f64, ARM64_INS_FMINNMP, + {AArch64_FMINNMPv2f64, + ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMPv2i16p, ARM64_INS_FMINNMP, + {AArch64_FMINNMPv2i16p, + ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMPv2i32p, ARM64_INS_FMINNMP, + {AArch64_FMINNMPv2i32p, + ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMPv2i64p, ARM64_INS_FMINNMP, + {AArch64_FMINNMPv2i64p, + ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMPv4f16, ARM64_INS_FMINNMP, + {AArch64_FMINNMPv4f16, + ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMPv4f32, ARM64_INS_FMINNMP, + {AArch64_FMINNMPv4f32, + ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMPv8f16, ARM64_INS_FMINNMP, + {AArch64_FMINNMPv8f16, + ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMSrr, ARM64_INS_FMINNM, + {AArch64_FMINNMSrr, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMV_VPZ_D, ARM64_INS_FMINNMV, + {AArch64_FMINNMV_VPZ_D, + ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMV_VPZ_H, ARM64_INS_FMINNMV, + {AArch64_FMINNMV_VPZ_H, + ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMV_VPZ_S, ARM64_INS_FMINNMV, + {AArch64_FMINNMV_VPZ_S, + ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMVv4i16v, ARM64_INS_FMINNMV, + {AArch64_FMINNMVv4i16v, + ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMVv4i32v, ARM64_INS_FMINNMV, + {AArch64_FMINNMVv4i32v, + ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMVv8i16v, ARM64_INS_FMINNMV, + {AArch64_FMINNMVv8i16v, + ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNM_ZPmI_D, ARM64_INS_FMINNM, + {AArch64_FMINNM_ZPmI_D, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNM_ZPmI_H, ARM64_INS_FMINNM, + {AArch64_FMINNM_ZPmI_H, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNM_ZPmI_S, ARM64_INS_FMINNM, + {AArch64_FMINNM_ZPmI_S, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNM_ZPmZ_D, ARM64_INS_FMINNM, + {AArch64_FMINNM_ZPmZ_D, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNM_ZPmZ_H, ARM64_INS_FMINNM, + {AArch64_FMINNM_ZPmZ_H, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNM_ZPmZ_S, ARM64_INS_FMINNM, + {AArch64_FMINNM_ZPmZ_S, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMv2f32, ARM64_INS_FMINNM, + {AArch64_FMINNMv2f32, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMv2f64, ARM64_INS_FMINNM, + {AArch64_FMINNMv2f64, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMv4f16, ARM64_INS_FMINNM, + {AArch64_FMINNMv4f16, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMv4f32, ARM64_INS_FMINNM, + {AArch64_FMINNMv4f32, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINNMv8f16, ARM64_INS_FMINNM, + {AArch64_FMINNMv8f16, + ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINPv2f32, ARM64_INS_FMINP, + {AArch64_FMINPv2f32, + ARM64_INS_FMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINPv2f64, ARM64_INS_FMINP, + {AArch64_FMINPv2f64, + ARM64_INS_FMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINPv2i16p, ARM64_INS_FMINP, + {AArch64_FMINPv2i16p, + ARM64_INS_FMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINPv2i32p, ARM64_INS_FMINP, + {AArch64_FMINPv2i32p, + ARM64_INS_FMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINPv2i64p, ARM64_INS_FMINP, + {AArch64_FMINPv2i64p, + ARM64_INS_FMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINPv4f16, ARM64_INS_FMINP, + {AArch64_FMINPv4f16, + ARM64_INS_FMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINPv4f32, ARM64_INS_FMINP, + {AArch64_FMINPv4f32, + ARM64_INS_FMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINPv8f16, ARM64_INS_FMINP, + {AArch64_FMINPv8f16, + ARM64_INS_FMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINSrr, ARM64_INS_FMIN, + {AArch64_FMINSrr, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINV_VPZ_D, ARM64_INS_FMINV, + {AArch64_FMINV_VPZ_D, + ARM64_INS_FMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINV_VPZ_H, ARM64_INS_FMINV, + {AArch64_FMINV_VPZ_H, + ARM64_INS_FMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINV_VPZ_S, ARM64_INS_FMINV, + {AArch64_FMINV_VPZ_S, + ARM64_INS_FMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINVv4i16v, ARM64_INS_FMINV, + {AArch64_FMINVv4i16v, + ARM64_INS_FMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINVv4i32v, ARM64_INS_FMINV, + {AArch64_FMINVv4i32v, + ARM64_INS_FMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINVv8i16v, ARM64_INS_FMINV, + {AArch64_FMINVv8i16v, + ARM64_INS_FMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMIN_ZPmI_D, ARM64_INS_FMIN, + {AArch64_FMIN_ZPmI_D, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMIN_ZPmI_H, ARM64_INS_FMIN, + {AArch64_FMIN_ZPmI_H, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMIN_ZPmI_S, ARM64_INS_FMIN, + {AArch64_FMIN_ZPmI_S, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMIN_ZPmZ_D, ARM64_INS_FMIN, + {AArch64_FMIN_ZPmZ_D, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMIN_ZPmZ_H, ARM64_INS_FMIN, + {AArch64_FMIN_ZPmZ_H, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMIN_ZPmZ_S, ARM64_INS_FMIN, + {AArch64_FMIN_ZPmZ_S, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINv2f32, ARM64_INS_FMIN, + {AArch64_FMINv2f32, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINv2f64, ARM64_INS_FMIN, + {AArch64_FMINv2f64, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINv4f16, ARM64_INS_FMIN, + {AArch64_FMINv4f16, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINv4f32, ARM64_INS_FMIN, + {AArch64_FMINv4f32, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMINv8f16, ARM64_INS_FMIN, + {AArch64_FMINv8f16, + ARM64_INS_FMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLA_ZPmZZ_D, ARM64_INS_FMLA, + {AArch64_FMLA_ZPmZZ_D, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLA_ZPmZZ_H, ARM64_INS_FMLA, + {AArch64_FMLA_ZPmZZ_H, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLA_ZPmZZ_S, ARM64_INS_FMLA, + {AArch64_FMLA_ZPmZZ_S, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLA_ZZZI_D, ARM64_INS_FMLA, + {AArch64_FMLA_ZZZI_D, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLA_ZZZI_H, ARM64_INS_FMLA, + {AArch64_FMLA_ZZZI_H, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLA_ZZZI_S, ARM64_INS_FMLA, + {AArch64_FMLA_ZZZI_S, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv1i16_indexed, ARM64_INS_FMLA, + {AArch64_FMLAv1i16_indexed, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv1i32_indexed, ARM64_INS_FMLA, + {AArch64_FMLAv1i32_indexed, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv1i64_indexed, ARM64_INS_FMLA, + {AArch64_FMLAv1i64_indexed, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv2f32, ARM64_INS_FMLA, + {AArch64_FMLAv2f32, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv2f64, ARM64_INS_FMLA, + {AArch64_FMLAv2f64, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv2i32_indexed, ARM64_INS_FMLA, + {AArch64_FMLAv2i32_indexed, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv2i64_indexed, ARM64_INS_FMLA, + {AArch64_FMLAv2i64_indexed, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv4f16, ARM64_INS_FMLA, + {AArch64_FMLAv4f16, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv4f32, ARM64_INS_FMLA, + {AArch64_FMLAv4f32, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv4i16_indexed, ARM64_INS_FMLA, + {AArch64_FMLAv4i16_indexed, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv4i32_indexed, ARM64_INS_FMLA, + {AArch64_FMLAv4i32_indexed, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv8f16, ARM64_INS_FMLA, + {AArch64_FMLAv8f16, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLAv8i16_indexed, ARM64_INS_FMLA, + {AArch64_FMLAv8i16_indexed, + ARM64_INS_FMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLS_ZPmZZ_D, ARM64_INS_FMLS, + {AArch64_FMLS_ZPmZZ_D, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLS_ZPmZZ_H, ARM64_INS_FMLS, + {AArch64_FMLS_ZPmZZ_H, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLS_ZPmZZ_S, ARM64_INS_FMLS, + {AArch64_FMLS_ZPmZZ_S, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLS_ZZZI_D, ARM64_INS_FMLS, + {AArch64_FMLS_ZZZI_D, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLS_ZZZI_H, ARM64_INS_FMLS, + {AArch64_FMLS_ZZZI_H, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLS_ZZZI_S, ARM64_INS_FMLS, + {AArch64_FMLS_ZZZI_S, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv1i16_indexed, ARM64_INS_FMLS, + {AArch64_FMLSv1i16_indexed, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv1i32_indexed, ARM64_INS_FMLS, + {AArch64_FMLSv1i32_indexed, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv1i64_indexed, ARM64_INS_FMLS, + {AArch64_FMLSv1i64_indexed, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv2f32, ARM64_INS_FMLS, + {AArch64_FMLSv2f32, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv2f64, ARM64_INS_FMLS, + {AArch64_FMLSv2f64, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv2i32_indexed, ARM64_INS_FMLS, + {AArch64_FMLSv2i32_indexed, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv2i64_indexed, ARM64_INS_FMLS, + {AArch64_FMLSv2i64_indexed, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv4f16, ARM64_INS_FMLS, + {AArch64_FMLSv4f16, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv4f32, ARM64_INS_FMLS, + {AArch64_FMLSv4f32, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv4i16_indexed, ARM64_INS_FMLS, + {AArch64_FMLSv4i16_indexed, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv4i32_indexed, ARM64_INS_FMLS, + {AArch64_FMLSv4i32_indexed, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv8f16, ARM64_INS_FMLS, + {AArch64_FMLSv8f16, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMLSv8i16_indexed, ARM64_INS_FMLS, + {AArch64_FMLSv8i16_indexed, + ARM64_INS_FMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVDXHighr, ARM64_INS_FMOV, + {AArch64_FMOVDXHighr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVDXr, ARM64_INS_FMOV, + {AArch64_FMOVDXr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVDi, ARM64_INS_FMOV, + {AArch64_FMOVDi, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVDr, ARM64_INS_FMOV, + {AArch64_FMOVDr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVHWr, ARM64_INS_FMOV, + {AArch64_FMOVHWr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVHXr, ARM64_INS_FMOV, + {AArch64_FMOVHXr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVHi, ARM64_INS_FMOV, + {AArch64_FMOVHi, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVHr, ARM64_INS_FMOV, + {AArch64_FMOVHr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVSWr, ARM64_INS_FMOV, + {AArch64_FMOVSWr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVSi, ARM64_INS_FMOV, + {AArch64_FMOVSi, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVSr, ARM64_INS_FMOV, + {AArch64_FMOVSr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVWHr, ARM64_INS_FMOV, + {AArch64_FMOVWHr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVWSr, ARM64_INS_FMOV, + {AArch64_FMOVWSr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVXDHighr, ARM64_INS_FMOV, + {AArch64_FMOVXDHighr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVXDr, ARM64_INS_FMOV, + {AArch64_FMOVXDr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVXHr, ARM64_INS_FMOV, + {AArch64_FMOVXHr, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVv2f32_ns, ARM64_INS_FMOV, + {AArch64_FMOVv2f32_ns, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVv2f64_ns, ARM64_INS_FMOV, + {AArch64_FMOVv2f64_ns, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVv4f16_ns, ARM64_INS_FMOV, + {AArch64_FMOVv4f16_ns, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVv4f32_ns, ARM64_INS_FMOV, + {AArch64_FMOVv4f32_ns, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMOVv8f16_ns, ARM64_INS_FMOV, + {AArch64_FMOVv8f16_ns, + ARM64_INS_FMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMSB_ZPmZZ_D, ARM64_INS_FMSB, + {AArch64_FMSB_ZPmZZ_D, + ARM64_INS_FMSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMSB_ZPmZZ_H, ARM64_INS_FMSB, + {AArch64_FMSB_ZPmZZ_H, + ARM64_INS_FMSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMSB_ZPmZZ_S, ARM64_INS_FMSB, + {AArch64_FMSB_ZPmZZ_S, + ARM64_INS_FMSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMSUBDrrr, ARM64_INS_FMSUB, + {AArch64_FMSUBDrrr, + ARM64_INS_FMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMSUBHrrr, ARM64_INS_FMSUB, + {AArch64_FMSUBHrrr, + ARM64_INS_FMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMSUBSrrr, ARM64_INS_FMSUB, + {AArch64_FMSUBSrrr, + ARM64_INS_FMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULDrr, ARM64_INS_FMUL, + {AArch64_FMULDrr, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULHrr, ARM64_INS_FMUL, + {AArch64_FMULHrr, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULSrr, ARM64_INS_FMUL, + {AArch64_FMULSrr, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULX16, ARM64_INS_FMULX, + {AArch64_FMULX16, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULX32, ARM64_INS_FMULX, + {AArch64_FMULX32, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULX64, ARM64_INS_FMULX, + {AArch64_FMULX64, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULX_ZPmZ_D, ARM64_INS_FMULX, + {AArch64_FMULX_ZPmZ_D, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULX_ZPmZ_H, ARM64_INS_FMULX, + {AArch64_FMULX_ZPmZ_H, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULX_ZPmZ_S, ARM64_INS_FMULX, + {AArch64_FMULX_ZPmZ_S, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv1i16_indexed, ARM64_INS_FMULX, + {AArch64_FMULXv1i16_indexed, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv1i32_indexed, ARM64_INS_FMULX, + {AArch64_FMULXv1i32_indexed, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv1i64_indexed, ARM64_INS_FMULX, + {AArch64_FMULXv1i64_indexed, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv2f32, ARM64_INS_FMULX, + {AArch64_FMULXv2f32, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv2f64, ARM64_INS_FMULX, + {AArch64_FMULXv2f64, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv2i32_indexed, ARM64_INS_FMULX, + {AArch64_FMULXv2i32_indexed, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv2i64_indexed, ARM64_INS_FMULX, + {AArch64_FMULXv2i64_indexed, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv4f16, ARM64_INS_FMULX, + {AArch64_FMULXv4f16, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv4f32, ARM64_INS_FMULX, + {AArch64_FMULXv4f32, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv4i16_indexed, ARM64_INS_FMULX, + {AArch64_FMULXv4i16_indexed, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv4i32_indexed, ARM64_INS_FMULX, + {AArch64_FMULXv4i32_indexed, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv8f16, ARM64_INS_FMULX, + {AArch64_FMULXv8f16, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULXv8i16_indexed, ARM64_INS_FMULX, + {AArch64_FMULXv8i16_indexed, + ARM64_INS_FMULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZPmI_D, ARM64_INS_FMUL, + {AArch64_FMUL_ZPmI_D, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZPmI_H, ARM64_INS_FMUL, + {AArch64_FMUL_ZPmI_H, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZPmI_S, ARM64_INS_FMUL, + {AArch64_FMUL_ZPmI_S, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZPmZ_D, ARM64_INS_FMUL, + {AArch64_FMUL_ZPmZ_D, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZPmZ_H, ARM64_INS_FMUL, + {AArch64_FMUL_ZPmZ_H, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZPmZ_S, ARM64_INS_FMUL, + {AArch64_FMUL_ZPmZ_S, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZZZI_D, ARM64_INS_FMUL, + {AArch64_FMUL_ZZZI_D, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZZZI_H, ARM64_INS_FMUL, + {AArch64_FMUL_ZZZI_H, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZZZI_S, ARM64_INS_FMUL, + {AArch64_FMUL_ZZZI_S, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZZZ_D, ARM64_INS_FMUL, + {AArch64_FMUL_ZZZ_D, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZZZ_H, ARM64_INS_FMUL, + {AArch64_FMUL_ZZZ_H, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMUL_ZZZ_S, ARM64_INS_FMUL, + {AArch64_FMUL_ZZZ_S, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv1i16_indexed, ARM64_INS_FMUL, + {AArch64_FMULv1i16_indexed, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv1i32_indexed, ARM64_INS_FMUL, + {AArch64_FMULv1i32_indexed, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv1i64_indexed, ARM64_INS_FMUL, + {AArch64_FMULv1i64_indexed, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv2f32, ARM64_INS_FMUL, + {AArch64_FMULv2f32, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv2f64, ARM64_INS_FMUL, + {AArch64_FMULv2f64, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv2i32_indexed, ARM64_INS_FMUL, + {AArch64_FMULv2i32_indexed, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv2i64_indexed, ARM64_INS_FMUL, + {AArch64_FMULv2i64_indexed, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv4f16, ARM64_INS_FMUL, + {AArch64_FMULv4f16, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv4f32, ARM64_INS_FMUL, + {AArch64_FMULv4f32, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv4i16_indexed, ARM64_INS_FMUL, + {AArch64_FMULv4i16_indexed, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv4i32_indexed, ARM64_INS_FMUL, + {AArch64_FMULv4i32_indexed, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv8f16, ARM64_INS_FMUL, + {AArch64_FMULv8f16, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FMULv8i16_indexed, ARM64_INS_FMUL, + {AArch64_FMULv8i16_indexed, + ARM64_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEGDr, ARM64_INS_FNEG, + {AArch64_FNEGDr, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEGHr, ARM64_INS_FNEG, + {AArch64_FNEGHr, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEGSr, ARM64_INS_FNEG, + {AArch64_FNEGSr, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEG_ZPmZ_D, ARM64_INS_FNEG, + {AArch64_FNEG_ZPmZ_D, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEG_ZPmZ_H, ARM64_INS_FNEG, + {AArch64_FNEG_ZPmZ_H, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEG_ZPmZ_S, ARM64_INS_FNEG, + {AArch64_FNEG_ZPmZ_S, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEGv2f32, ARM64_INS_FNEG, + {AArch64_FNEGv2f32, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEGv2f64, ARM64_INS_FNEG, + {AArch64_FNEGv2f64, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEGv4f16, ARM64_INS_FNEG, + {AArch64_FNEGv4f16, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEGv4f32, ARM64_INS_FNEG, + {AArch64_FNEGv4f32, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNEGv8f16, ARM64_INS_FNEG, + {AArch64_FNEGv8f16, + ARM64_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMADDDrrr, ARM64_INS_FNMADD, + {AArch64_FNMADDDrrr, + ARM64_INS_FNMADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMADDHrrr, ARM64_INS_FNMADD, + {AArch64_FNMADDHrrr, + ARM64_INS_FNMADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMADDSrrr, ARM64_INS_FNMADD, + {AArch64_FNMADDSrrr, + ARM64_INS_FNMADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMAD_ZPmZZ_D, ARM64_INS_FNMAD, + {AArch64_FNMAD_ZPmZZ_D, + ARM64_INS_FNMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMAD_ZPmZZ_H, ARM64_INS_FNMAD, + {AArch64_FNMAD_ZPmZZ_H, + ARM64_INS_FNMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMAD_ZPmZZ_S, ARM64_INS_FNMAD, + {AArch64_FNMAD_ZPmZZ_S, + ARM64_INS_FNMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMLA_ZPmZZ_D, ARM64_INS_FNMLA, + {AArch64_FNMLA_ZPmZZ_D, + ARM64_INS_FNMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMLA_ZPmZZ_H, ARM64_INS_FNMLA, + {AArch64_FNMLA_ZPmZZ_H, + ARM64_INS_FNMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMLA_ZPmZZ_S, ARM64_INS_FNMLA, + {AArch64_FNMLA_ZPmZZ_S, + ARM64_INS_FNMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMLS_ZPmZZ_D, ARM64_INS_FNMLS, + {AArch64_FNMLS_ZPmZZ_D, + ARM64_INS_FNMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMLS_ZPmZZ_H, ARM64_INS_FNMLS, + {AArch64_FNMLS_ZPmZZ_H, + ARM64_INS_FNMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMLS_ZPmZZ_S, ARM64_INS_FNMLS, + {AArch64_FNMLS_ZPmZZ_S, + ARM64_INS_FNMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMSB_ZPmZZ_D, ARM64_INS_FNMSB, + {AArch64_FNMSB_ZPmZZ_D, + ARM64_INS_FNMSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMSB_ZPmZZ_H, ARM64_INS_FNMSB, + {AArch64_FNMSB_ZPmZZ_H, + ARM64_INS_FNMSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMSB_ZPmZZ_S, ARM64_INS_FNMSB, + {AArch64_FNMSB_ZPmZZ_S, + ARM64_INS_FNMSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMSUBDrrr, ARM64_INS_FNMSUB, + {AArch64_FNMSUBDrrr, + ARM64_INS_FNMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMSUBHrrr, ARM64_INS_FNMSUB, + {AArch64_FNMSUBHrrr, + ARM64_INS_FNMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMSUBSrrr, ARM64_INS_FNMSUB, + {AArch64_FNMSUBSrrr, + ARM64_INS_FNMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMULDrr, ARM64_INS_FNMUL, + {AArch64_FNMULDrr, + ARM64_INS_FNMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMULHrr, ARM64_INS_FNMUL, + {AArch64_FNMULHrr, + ARM64_INS_FNMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FNMULSrr, ARM64_INS_FNMUL, + {AArch64_FNMULSrr, + ARM64_INS_FNMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPE_ZZ_D, ARM64_INS_FRECPE, + {AArch64_FRECPE_ZZ_D, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPE_ZZ_H, ARM64_INS_FRECPE, + {AArch64_FRECPE_ZZ_H, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPE_ZZ_S, ARM64_INS_FRECPE, + {AArch64_FRECPE_ZZ_S, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPEv1f16, ARM64_INS_FRECPE, + {AArch64_FRECPEv1f16, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPEv1i32, ARM64_INS_FRECPE, + {AArch64_FRECPEv1i32, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPEv1i64, ARM64_INS_FRECPE, + {AArch64_FRECPEv1i64, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPEv2f32, ARM64_INS_FRECPE, + {AArch64_FRECPEv2f32, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPEv2f64, ARM64_INS_FRECPE, + {AArch64_FRECPEv2f64, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPEv4f16, ARM64_INS_FRECPE, + {AArch64_FRECPEv4f16, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPEv4f32, ARM64_INS_FRECPE, + {AArch64_FRECPEv4f32, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPEv8f16, ARM64_INS_FRECPE, + {AArch64_FRECPEv8f16, + ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPS16, ARM64_INS_FRECPS, + {AArch64_FRECPS16, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPS32, ARM64_INS_FRECPS, + {AArch64_FRECPS32, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPS64, ARM64_INS_FRECPS, + {AArch64_FRECPS64, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPS_ZZZ_D, ARM64_INS_FRECPS, + {AArch64_FRECPS_ZZZ_D, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPS_ZZZ_H, ARM64_INS_FRECPS, + {AArch64_FRECPS_ZZZ_H, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPS_ZZZ_S, ARM64_INS_FRECPS, + {AArch64_FRECPS_ZZZ_S, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPSv2f32, ARM64_INS_FRECPS, + {AArch64_FRECPSv2f32, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPSv2f64, ARM64_INS_FRECPS, + {AArch64_FRECPSv2f64, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPSv4f16, ARM64_INS_FRECPS, + {AArch64_FRECPSv4f16, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPSv4f32, ARM64_INS_FRECPS, + {AArch64_FRECPSv4f32, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPSv8f16, ARM64_INS_FRECPS, + {AArch64_FRECPSv8f16, + ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPX_ZPmZ_D, ARM64_INS_FRECPX, + {AArch64_FRECPX_ZPmZ_D, + ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPX_ZPmZ_H, ARM64_INS_FRECPX, + {AArch64_FRECPX_ZPmZ_H, + ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPX_ZPmZ_S, ARM64_INS_FRECPX, + {AArch64_FRECPX_ZPmZ_S, + ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPXv1f16, ARM64_INS_FRECPX, + {AArch64_FRECPXv1f16, + ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPXv1i32, ARM64_INS_FRECPX, + {AArch64_FRECPXv1i32, + ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRECPXv1i64, ARM64_INS_FRECPX, + {AArch64_FRECPXv1i64, + ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTADr, ARM64_INS_FRINTA, + {AArch64_FRINTADr, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTAHr, ARM64_INS_FRINTA, + {AArch64_FRINTAHr, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTASr, ARM64_INS_FRINTA, + {AArch64_FRINTASr, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTA_ZPmZ_D, ARM64_INS_FRINTA, + {AArch64_FRINTA_ZPmZ_D, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTA_ZPmZ_H, ARM64_INS_FRINTA, + {AArch64_FRINTA_ZPmZ_H, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTA_ZPmZ_S, ARM64_INS_FRINTA, + {AArch64_FRINTA_ZPmZ_S, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTAv2f32, ARM64_INS_FRINTA, + {AArch64_FRINTAv2f32, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTAv2f64, ARM64_INS_FRINTA, + {AArch64_FRINTAv2f64, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTAv4f16, ARM64_INS_FRINTA, + {AArch64_FRINTAv4f16, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTAv4f32, ARM64_INS_FRINTA, + {AArch64_FRINTAv4f32, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTAv8f16, ARM64_INS_FRINTA, + {AArch64_FRINTAv8f16, + ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTIDr, ARM64_INS_FRINTI, + {AArch64_FRINTIDr, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTIHr, ARM64_INS_FRINTI, + {AArch64_FRINTIHr, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTISr, ARM64_INS_FRINTI, + {AArch64_FRINTISr, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTI_ZPmZ_D, ARM64_INS_FRINTI, + {AArch64_FRINTI_ZPmZ_D, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTI_ZPmZ_H, ARM64_INS_FRINTI, + {AArch64_FRINTI_ZPmZ_H, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTI_ZPmZ_S, ARM64_INS_FRINTI, + {AArch64_FRINTI_ZPmZ_S, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTIv2f32, ARM64_INS_FRINTI, + {AArch64_FRINTIv2f32, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTIv2f64, ARM64_INS_FRINTI, + {AArch64_FRINTIv2f64, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTIv4f16, ARM64_INS_FRINTI, + {AArch64_FRINTIv4f16, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTIv4f32, ARM64_INS_FRINTI, + {AArch64_FRINTIv4f32, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTIv8f16, ARM64_INS_FRINTI, + {AArch64_FRINTIv8f16, + ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTMDr, ARM64_INS_FRINTM, + {AArch64_FRINTMDr, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTMHr, ARM64_INS_FRINTM, + {AArch64_FRINTMHr, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTMSr, ARM64_INS_FRINTM, + {AArch64_FRINTMSr, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTM_ZPmZ_D, ARM64_INS_FRINTM, + {AArch64_FRINTM_ZPmZ_D, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTM_ZPmZ_H, ARM64_INS_FRINTM, + {AArch64_FRINTM_ZPmZ_H, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTM_ZPmZ_S, ARM64_INS_FRINTM, + {AArch64_FRINTM_ZPmZ_S, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTMv2f32, ARM64_INS_FRINTM, + {AArch64_FRINTMv2f32, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTMv2f64, ARM64_INS_FRINTM, + {AArch64_FRINTMv2f64, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTMv4f16, ARM64_INS_FRINTM, + {AArch64_FRINTMv4f16, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTMv4f32, ARM64_INS_FRINTM, + {AArch64_FRINTMv4f32, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTMv8f16, ARM64_INS_FRINTM, + {AArch64_FRINTMv8f16, + ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTNDr, ARM64_INS_FRINTN, + {AArch64_FRINTNDr, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTNHr, ARM64_INS_FRINTN, + {AArch64_FRINTNHr, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTNSr, ARM64_INS_FRINTN, + {AArch64_FRINTNSr, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTN_ZPmZ_D, ARM64_INS_FRINTN, + {AArch64_FRINTN_ZPmZ_D, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTN_ZPmZ_H, ARM64_INS_FRINTN, + {AArch64_FRINTN_ZPmZ_H, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTN_ZPmZ_S, ARM64_INS_FRINTN, + {AArch64_FRINTN_ZPmZ_S, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTNv2f32, ARM64_INS_FRINTN, + {AArch64_FRINTNv2f32, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTNv2f64, ARM64_INS_FRINTN, + {AArch64_FRINTNv2f64, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTNv4f16, ARM64_INS_FRINTN, + {AArch64_FRINTNv4f16, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTNv4f32, ARM64_INS_FRINTN, + {AArch64_FRINTNv4f32, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTNv8f16, ARM64_INS_FRINTN, + {AArch64_FRINTNv8f16, + ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTPDr, ARM64_INS_FRINTP, + {AArch64_FRINTPDr, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTPHr, ARM64_INS_FRINTP, + {AArch64_FRINTPHr, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTPSr, ARM64_INS_FRINTP, + {AArch64_FRINTPSr, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTP_ZPmZ_D, ARM64_INS_FRINTP, + {AArch64_FRINTP_ZPmZ_D, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTP_ZPmZ_H, ARM64_INS_FRINTP, + {AArch64_FRINTP_ZPmZ_H, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTP_ZPmZ_S, ARM64_INS_FRINTP, + {AArch64_FRINTP_ZPmZ_S, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTPv2f32, ARM64_INS_FRINTP, + {AArch64_FRINTPv2f32, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTPv2f64, ARM64_INS_FRINTP, + {AArch64_FRINTPv2f64, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTPv4f16, ARM64_INS_FRINTP, + {AArch64_FRINTPv4f16, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTPv4f32, ARM64_INS_FRINTP, + {AArch64_FRINTPv4f32, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTPv8f16, ARM64_INS_FRINTP, + {AArch64_FRINTPv8f16, + ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTXDr, ARM64_INS_FRINTX, + {AArch64_FRINTXDr, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTXHr, ARM64_INS_FRINTX, + {AArch64_FRINTXHr, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTXSr, ARM64_INS_FRINTX, + {AArch64_FRINTXSr, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTX_ZPmZ_D, ARM64_INS_FRINTX, + {AArch64_FRINTX_ZPmZ_D, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTX_ZPmZ_H, ARM64_INS_FRINTX, + {AArch64_FRINTX_ZPmZ_H, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTX_ZPmZ_S, ARM64_INS_FRINTX, + {AArch64_FRINTX_ZPmZ_S, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTXv2f32, ARM64_INS_FRINTX, + {AArch64_FRINTXv2f32, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTXv2f64, ARM64_INS_FRINTX, + {AArch64_FRINTXv2f64, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTXv4f16, ARM64_INS_FRINTX, + {AArch64_FRINTXv4f16, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTXv4f32, ARM64_INS_FRINTX, + {AArch64_FRINTXv4f32, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTXv8f16, ARM64_INS_FRINTX, + {AArch64_FRINTXv8f16, + ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZDr, ARM64_INS_FRINTZ, + {AArch64_FRINTZDr, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZHr, ARM64_INS_FRINTZ, + {AArch64_FRINTZHr, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZSr, ARM64_INS_FRINTZ, + {AArch64_FRINTZSr, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZ_ZPmZ_D, ARM64_INS_FRINTZ, + {AArch64_FRINTZ_ZPmZ_D, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZ_ZPmZ_H, ARM64_INS_FRINTZ, + {AArch64_FRINTZ_ZPmZ_H, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZ_ZPmZ_S, ARM64_INS_FRINTZ, + {AArch64_FRINTZ_ZPmZ_S, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZv2f32, ARM64_INS_FRINTZ, + {AArch64_FRINTZv2f32, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZv2f64, ARM64_INS_FRINTZ, + {AArch64_FRINTZv2f64, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZv4f16, ARM64_INS_FRINTZ, + {AArch64_FRINTZv4f16, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZv4f32, ARM64_INS_FRINTZ, + {AArch64_FRINTZv4f32, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRINTZv8f16, ARM64_INS_FRINTZ, + {AArch64_FRINTZv8f16, + ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTE_ZZ_D, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTE_ZZ_D, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTE_ZZ_H, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTE_ZZ_H, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTE_ZZ_S, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTE_ZZ_S, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTEv1f16, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTEv1f16, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTEv1i32, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTEv1i32, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTEv1i64, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTEv1i64, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTEv2f32, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTEv2f32, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTEv2f64, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTEv2f64, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTEv4f16, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTEv4f16, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTEv4f32, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTEv4f32, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTEv8f16, ARM64_INS_FRSQRTE, + {AArch64_FRSQRTEv8f16, + ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTS16, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTS16, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTS32, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTS32, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTS64, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTS64, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTS_ZZZ_D, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTS_ZZZ_D, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTS_ZZZ_H, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTS_ZZZ_H, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTS_ZZZ_S, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTS_ZZZ_S, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTSv2f32, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTSv2f32, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTSv2f64, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTSv2f64, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTSv4f16, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTSv4f16, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTSv4f32, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTSv4f32, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FRSQRTSv8f16, ARM64_INS_FRSQRTS, + {AArch64_FRSQRTSv8f16, + ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSCALE_ZPmZ_D, ARM64_INS_FSCALE, + {AArch64_FSCALE_ZPmZ_D, + ARM64_INS_FSCALE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSCALE_ZPmZ_H, ARM64_INS_FSCALE, + {AArch64_FSCALE_ZPmZ_H, + ARM64_INS_FSCALE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSCALE_ZPmZ_S, ARM64_INS_FSCALE, + {AArch64_FSCALE_ZPmZ_S, + ARM64_INS_FSCALE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRTDr, ARM64_INS_FSQRT, + {AArch64_FSQRTDr, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRTHr, ARM64_INS_FSQRT, + {AArch64_FSQRTHr, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRTSr, ARM64_INS_FSQRT, + {AArch64_FSQRTSr, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRT_ZPmZ_D, ARM64_INS_FSQRT, + {AArch64_FSQRT_ZPmZ_D, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRT_ZPmZ_H, ARM64_INS_FSQRT, + {AArch64_FSQRT_ZPmZ_H, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRT_ZPmZ_S, ARM64_INS_FSQRT, + {AArch64_FSQRT_ZPmZ_S, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRTv2f32, ARM64_INS_FSQRT, + {AArch64_FSQRTv2f32, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRTv2f64, ARM64_INS_FSQRT, + {AArch64_FSQRTv2f64, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRTv4f16, ARM64_INS_FSQRT, + {AArch64_FSQRTv4f16, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRTv4f32, ARM64_INS_FSQRT, + {AArch64_FSQRTv4f32, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSQRTv8f16, ARM64_INS_FSQRT, + {AArch64_FSQRTv8f16, + ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBDrr, ARM64_INS_FSUB, + {AArch64_FSUBDrr, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBHrr, ARM64_INS_FSUB, + {AArch64_FSUBHrr, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBR_ZPmI_D, ARM64_INS_FSUBR, + {AArch64_FSUBR_ZPmI_D, + ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBR_ZPmI_H, ARM64_INS_FSUBR, + {AArch64_FSUBR_ZPmI_H, + ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBR_ZPmI_S, ARM64_INS_FSUBR, + {AArch64_FSUBR_ZPmI_S, + ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBR_ZPmZ_D, ARM64_INS_FSUBR, + {AArch64_FSUBR_ZPmZ_D, + ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBR_ZPmZ_H, ARM64_INS_FSUBR, + {AArch64_FSUBR_ZPmZ_H, + ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBR_ZPmZ_S, ARM64_INS_FSUBR, + {AArch64_FSUBR_ZPmZ_S, + ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBSrr, ARM64_INS_FSUB, + {AArch64_FSUBSrr, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUB_ZPmI_D, ARM64_INS_FSUB, + {AArch64_FSUB_ZPmI_D, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUB_ZPmI_H, ARM64_INS_FSUB, + {AArch64_FSUB_ZPmI_H, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUB_ZPmI_S, ARM64_INS_FSUB, + {AArch64_FSUB_ZPmI_S, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUB_ZPmZ_D, ARM64_INS_FSUB, + {AArch64_FSUB_ZPmZ_D, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUB_ZPmZ_H, ARM64_INS_FSUB, + {AArch64_FSUB_ZPmZ_H, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUB_ZPmZ_S, ARM64_INS_FSUB, + {AArch64_FSUB_ZPmZ_S, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUB_ZZZ_D, ARM64_INS_FSUB, + {AArch64_FSUB_ZZZ_D, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUB_ZZZ_H, ARM64_INS_FSUB, + {AArch64_FSUB_ZZZ_H, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUB_ZZZ_S, ARM64_INS_FSUB, + {AArch64_FSUB_ZZZ_S, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBv2f32, ARM64_INS_FSUB, + {AArch64_FSUBv2f32, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBv2f64, ARM64_INS_FSUB, + {AArch64_FSUBv2f64, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBv4f16, ARM64_INS_FSUB, + {AArch64_FSUBv4f16, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBv4f32, ARM64_INS_FSUB, + {AArch64_FSUBv4f32, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FSUBv8f16, ARM64_INS_FSUB, + {AArch64_FSUBv8f16, + ARM64_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FTMAD_ZZI_D, ARM64_INS_FTMAD, + {AArch64_FTMAD_ZZI_D, + ARM64_INS_FTMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FTMAD_ZZI_H, ARM64_INS_FTMAD, + {AArch64_FTMAD_ZZI_H, + ARM64_INS_FTMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FTMAD_ZZI_S, ARM64_INS_FTMAD, + {AArch64_FTMAD_ZZI_S, + ARM64_INS_FTMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FTSMUL_ZZZ_D, ARM64_INS_FTSMUL, + {AArch64_FTSMUL_ZZZ_D, + ARM64_INS_FTSMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FTSMUL_ZZZ_H, ARM64_INS_FTSMUL, + {AArch64_FTSMUL_ZZZ_H, + ARM64_INS_FTSMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FTSMUL_ZZZ_S, ARM64_INS_FTSMUL, + {AArch64_FTSMUL_ZZZ_S, + ARM64_INS_FTSMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FTSSEL_ZZZ_D, ARM64_INS_FTSSEL, + {AArch64_FTSSEL_ZZZ_D, + ARM64_INS_FTSSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FTSSEL_ZZZ_H, ARM64_INS_FTSSEL, + {AArch64_FTSSEL_ZZZ_H, + ARM64_INS_FTSSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_FTSSEL_ZZZ_S, ARM64_INS_FTSSEL, + {AArch64_FTSSEL_ZZZ_S, + ARM64_INS_FTSSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1B_D_IMM_REAL, ARM64_INS_LD1B, + {AArch64_GLD1B_D_IMM_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1B_D_REAL, ARM64_INS_LD1B, + {AArch64_GLD1B_D_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1B_D_SXTW_REAL, ARM64_INS_LD1B, + {AArch64_GLD1B_D_SXTW_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1B_D_UXTW_REAL, ARM64_INS_LD1B, + {AArch64_GLD1B_D_UXTW_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1B_S_IMM_REAL, ARM64_INS_LD1B, + {AArch64_GLD1B_S_IMM_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1B_S_SXTW_REAL, ARM64_INS_LD1B, + {AArch64_GLD1B_S_SXTW_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1B_S_UXTW_REAL, ARM64_INS_LD1B, + {AArch64_GLD1B_S_UXTW_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1D_IMM_REAL, ARM64_INS_LD1D, + {AArch64_GLD1D_IMM_REAL, + ARM64_INS_LD1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1D_REAL, ARM64_INS_LD1D, + {AArch64_GLD1D_REAL, + ARM64_INS_LD1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1D_SCALED_REAL, ARM64_INS_LD1D, + {AArch64_GLD1D_SCALED_REAL, + ARM64_INS_LD1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1D_SXTW_REAL, ARM64_INS_LD1D, + {AArch64_GLD1D_SXTW_REAL, + ARM64_INS_LD1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1D_SXTW_SCALED_REAL, ARM64_INS_LD1D, + {AArch64_GLD1D_SXTW_SCALED_REAL, + ARM64_INS_LD1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1D_UXTW_REAL, ARM64_INS_LD1D, + {AArch64_GLD1D_UXTW_REAL, + ARM64_INS_LD1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1D_UXTW_SCALED_REAL, ARM64_INS_LD1D, + {AArch64_GLD1D_UXTW_SCALED_REAL, + ARM64_INS_LD1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_D_IMM_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_D_IMM_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_D_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_D_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_D_SCALED_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_D_SCALED_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_D_SXTW_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_D_SXTW_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_D_SXTW_SCALED_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_D_SXTW_SCALED_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_D_UXTW_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_D_UXTW_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_D_UXTW_SCALED_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_D_UXTW_SCALED_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_S_IMM_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_S_IMM_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_S_SXTW_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_S_SXTW_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_S_SXTW_SCALED_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_S_SXTW_SCALED_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_S_UXTW_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_S_UXTW_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1H_S_UXTW_SCALED_REAL, ARM64_INS_LD1H, + {AArch64_GLD1H_S_UXTW_SCALED_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SB_D_IMM_REAL, ARM64_INS_LD1SB, + {AArch64_GLD1SB_D_IMM_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SB_D_REAL, ARM64_INS_LD1SB, + {AArch64_GLD1SB_D_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SB_D_SXTW_REAL, ARM64_INS_LD1SB, + {AArch64_GLD1SB_D_SXTW_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SB_D_UXTW_REAL, ARM64_INS_LD1SB, + {AArch64_GLD1SB_D_UXTW_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SB_S_IMM_REAL, ARM64_INS_LD1SB, + {AArch64_GLD1SB_S_IMM_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SB_S_SXTW_REAL, ARM64_INS_LD1SB, + {AArch64_GLD1SB_S_SXTW_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SB_S_UXTW_REAL, ARM64_INS_LD1SB, + {AArch64_GLD1SB_S_UXTW_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_D_IMM_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_D_IMM_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_D_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_D_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_D_SCALED_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_D_SCALED_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_D_SXTW_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_D_SXTW_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_D_SXTW_SCALED_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_D_SXTW_SCALED_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_D_UXTW_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_D_UXTW_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_D_UXTW_SCALED_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_D_UXTW_SCALED_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_S_IMM_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_S_IMM_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_S_SXTW_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_S_SXTW_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_S_SXTW_SCALED_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_S_SXTW_SCALED_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_S_UXTW_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_S_UXTW_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SH_S_UXTW_SCALED_REAL, ARM64_INS_LD1SH, + {AArch64_GLD1SH_S_UXTW_SCALED_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SW_D_IMM_REAL, ARM64_INS_LD1SW, + {AArch64_GLD1SW_D_IMM_REAL, + ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SW_D_REAL, ARM64_INS_LD1SW, + {AArch64_GLD1SW_D_REAL, + ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SW_D_SCALED_REAL, ARM64_INS_LD1SW, + {AArch64_GLD1SW_D_SCALED_REAL, + ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SW_D_SXTW_REAL, ARM64_INS_LD1SW, + {AArch64_GLD1SW_D_SXTW_REAL, + ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SW_D_SXTW_SCALED_REAL, ARM64_INS_LD1SW, + {AArch64_GLD1SW_D_SXTW_SCALED_REAL, + ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SW_D_UXTW_REAL, ARM64_INS_LD1SW, + {AArch64_GLD1SW_D_UXTW_REAL, + ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1SW_D_UXTW_SCALED_REAL, ARM64_INS_LD1SW, + {AArch64_GLD1SW_D_UXTW_SCALED_REAL, + ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_D_IMM_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_D_IMM_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_D_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_D_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_D_SCALED_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_D_SCALED_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_D_SXTW_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_D_SXTW_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_D_SXTW_SCALED_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_D_SXTW_SCALED_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_D_UXTW_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_D_UXTW_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_D_UXTW_SCALED_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_D_UXTW_SCALED_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_IMM_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_IMM_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_SXTW_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_SXTW_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_SXTW_SCALED_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_SXTW_SCALED_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_UXTW_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_UXTW_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLD1W_UXTW_SCALED_REAL, ARM64_INS_LD1W, + {AArch64_GLD1W_UXTW_SCALED_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1B_D_IMM_REAL, ARM64_INS_LDFF1B, + {AArch64_GLDFF1B_D_IMM_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1B_D_REAL, ARM64_INS_LDFF1B, + {AArch64_GLDFF1B_D_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1B_D_SXTW_REAL, ARM64_INS_LDFF1B, + {AArch64_GLDFF1B_D_SXTW_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1B_D_UXTW_REAL, ARM64_INS_LDFF1B, + {AArch64_GLDFF1B_D_UXTW_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1B_S_IMM_REAL, ARM64_INS_LDFF1B, + {AArch64_GLDFF1B_S_IMM_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1B_S_SXTW_REAL, ARM64_INS_LDFF1B, + {AArch64_GLDFF1B_S_SXTW_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1B_S_UXTW_REAL, ARM64_INS_LDFF1B, + {AArch64_GLDFF1B_S_UXTW_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1D_IMM_REAL, ARM64_INS_LDFF1D, + {AArch64_GLDFF1D_IMM_REAL, + ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1D_REAL, ARM64_INS_LDFF1D, + {AArch64_GLDFF1D_REAL, + ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1D_SCALED_REAL, ARM64_INS_LDFF1D, + {AArch64_GLDFF1D_SCALED_REAL, + ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1D_SXTW_REAL, ARM64_INS_LDFF1D, + {AArch64_GLDFF1D_SXTW_REAL, + ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1D_SXTW_SCALED_REAL, ARM64_INS_LDFF1D, + {AArch64_GLDFF1D_SXTW_SCALED_REAL, + ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1D_UXTW_REAL, ARM64_INS_LDFF1D, + {AArch64_GLDFF1D_UXTW_REAL, + ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1D_UXTW_SCALED_REAL, ARM64_INS_LDFF1D, + {AArch64_GLDFF1D_UXTW_SCALED_REAL, + ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_D_IMM_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_D_IMM_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_D_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_D_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_D_SCALED_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_D_SCALED_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_D_SXTW_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_D_SXTW_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_D_SXTW_SCALED_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_D_UXTW_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_D_UXTW_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_D_UXTW_SCALED_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_S_IMM_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_S_IMM_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_S_SXTW_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_S_SXTW_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_S_SXTW_SCALED_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_S_SXTW_SCALED_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_S_UXTW_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_S_UXTW_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1H_S_UXTW_SCALED_REAL, ARM64_INS_LDFF1H, + {AArch64_GLDFF1H_S_UXTW_SCALED_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SB_D_IMM_REAL, ARM64_INS_LDFF1SB, + {AArch64_GLDFF1SB_D_IMM_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SB_D_REAL, ARM64_INS_LDFF1SB, + {AArch64_GLDFF1SB_D_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SB_D_SXTW_REAL, ARM64_INS_LDFF1SB, + {AArch64_GLDFF1SB_D_SXTW_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SB_D_UXTW_REAL, ARM64_INS_LDFF1SB, + {AArch64_GLDFF1SB_D_UXTW_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SB_S_IMM_REAL, ARM64_INS_LDFF1SB, + {AArch64_GLDFF1SB_S_IMM_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SB_S_SXTW_REAL, ARM64_INS_LDFF1SB, + {AArch64_GLDFF1SB_S_SXTW_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SB_S_UXTW_REAL, ARM64_INS_LDFF1SB, + {AArch64_GLDFF1SB_S_UXTW_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_D_IMM_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_D_IMM_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_D_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_D_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_D_SCALED_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_D_SCALED_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_D_SXTW_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_D_SXTW_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_D_SXTW_SCALED_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_D_UXTW_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_D_UXTW_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_D_UXTW_SCALED_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_S_IMM_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_S_IMM_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_S_SXTW_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_S_SXTW_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_S_SXTW_SCALED_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_S_SXTW_SCALED_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_S_UXTW_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_S_UXTW_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SH_S_UXTW_SCALED_REAL, ARM64_INS_LDFF1SH, + {AArch64_GLDFF1SH_S_UXTW_SCALED_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SW_D_IMM_REAL, ARM64_INS_LDFF1SW, + {AArch64_GLDFF1SW_D_IMM_REAL, + ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SW_D_REAL, ARM64_INS_LDFF1SW, + {AArch64_GLDFF1SW_D_REAL, + ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SW_D_SCALED_REAL, ARM64_INS_LDFF1SW, + {AArch64_GLDFF1SW_D_SCALED_REAL, + ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SW_D_SXTW_REAL, ARM64_INS_LDFF1SW, + {AArch64_GLDFF1SW_D_SXTW_REAL, + ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SW_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1SW, + {AArch64_GLDFF1SW_D_SXTW_SCALED_REAL, + ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SW_D_UXTW_REAL, ARM64_INS_LDFF1SW, + {AArch64_GLDFF1SW_D_UXTW_REAL, + ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1SW_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1SW, + {AArch64_GLDFF1SW_D_UXTW_SCALED_REAL, + ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_D_IMM_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_D_IMM_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_D_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_D_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_D_SCALED_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_D_SCALED_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_D_SXTW_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_D_SXTW_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_D_SXTW_SCALED_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_D_UXTW_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_D_UXTW_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_D_UXTW_SCALED_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_IMM_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_IMM_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_SXTW_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_SXTW_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_SXTW_SCALED_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_SXTW_SCALED_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_UXTW_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_UXTW_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_GLDFF1W_UXTW_SCALED_REAL, ARM64_INS_LDFF1W, + {AArch64_GLDFF1W_UXTW_SCALED_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_HINT, ARM64_INS_HINT, + {AArch64_HINT, + ARM64_INS_HINT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_HLT, ARM64_INS_HLT, + {AArch64_HLT, + ARM64_INS_HLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_HVC, ARM64_INS_HVC, + {AArch64_HVC, + ARM64_INS_HVC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCB_XPiI, ARM64_INS_INCB, + {AArch64_INCB_XPiI, + ARM64_INS_INCB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCD_XPiI, ARM64_INS_INCD, + {AArch64_INCD_XPiI, + ARM64_INS_INCD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCD_ZPiI, ARM64_INS_INCD, + {AArch64_INCD_ZPiI, + ARM64_INS_INCD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCH_XPiI, ARM64_INS_INCH, + {AArch64_INCH_XPiI, + ARM64_INS_INCH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCH_ZPiI, ARM64_INS_INCH, + {AArch64_INCH_ZPiI, + ARM64_INS_INCH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCP_XP_B, ARM64_INS_INCP, + {AArch64_INCP_XP_B, + ARM64_INS_INCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCP_XP_D, ARM64_INS_INCP, + {AArch64_INCP_XP_D, + ARM64_INS_INCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCP_XP_H, ARM64_INS_INCP, + {AArch64_INCP_XP_H, + ARM64_INS_INCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCP_XP_S, ARM64_INS_INCP, + {AArch64_INCP_XP_S, + ARM64_INS_INCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCP_ZP_D, ARM64_INS_INCP, + {AArch64_INCP_ZP_D, + ARM64_INS_INCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCP_ZP_H, ARM64_INS_INCP, + {AArch64_INCP_ZP_H, + ARM64_INS_INCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCP_ZP_S, ARM64_INS_INCP, + {AArch64_INCP_ZP_S, + ARM64_INS_INCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCW_XPiI, ARM64_INS_INCW, + {AArch64_INCW_XPiI, + ARM64_INS_INCW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INCW_ZPiI, ARM64_INS_INCW, + {AArch64_INCW_ZPiI, + ARM64_INS_INCW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_II_B, ARM64_INS_INDEX, + {AArch64_INDEX_II_B, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_II_D, ARM64_INS_INDEX, + {AArch64_INDEX_II_D, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_II_H, ARM64_INS_INDEX, + {AArch64_INDEX_II_H, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_II_S, ARM64_INS_INDEX, + {AArch64_INDEX_II_S, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_IR_B, ARM64_INS_INDEX, + {AArch64_INDEX_IR_B, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_IR_D, ARM64_INS_INDEX, + {AArch64_INDEX_IR_D, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_IR_H, ARM64_INS_INDEX, + {AArch64_INDEX_IR_H, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_IR_S, ARM64_INS_INDEX, + {AArch64_INDEX_IR_S, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_RI_B, ARM64_INS_INDEX, + {AArch64_INDEX_RI_B, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_RI_D, ARM64_INS_INDEX, + {AArch64_INDEX_RI_D, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_RI_H, ARM64_INS_INDEX, + {AArch64_INDEX_RI_H, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_RI_S, ARM64_INS_INDEX, + {AArch64_INDEX_RI_S, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_RR_B, ARM64_INS_INDEX, + {AArch64_INDEX_RR_B, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_RR_D, ARM64_INS_INDEX, + {AArch64_INDEX_RR_D, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_RR_H, ARM64_INS_INDEX, + {AArch64_INDEX_RR_H, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INDEX_RR_S, ARM64_INS_INDEX, + {AArch64_INDEX_RR_S, + ARM64_INS_INDEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSR_ZR_B, ARM64_INS_INSR, + {AArch64_INSR_ZR_B, + ARM64_INS_INSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSR_ZR_D, ARM64_INS_INSR, + {AArch64_INSR_ZR_D, + ARM64_INS_INSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSR_ZR_H, ARM64_INS_INSR, + {AArch64_INSR_ZR_H, + ARM64_INS_INSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSR_ZR_S, ARM64_INS_INSR, + {AArch64_INSR_ZR_S, + ARM64_INS_INSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSR_ZV_B, ARM64_INS_INSR, + {AArch64_INSR_ZV_B, + ARM64_INS_INSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSR_ZV_D, ARM64_INS_INSR, + {AArch64_INSR_ZV_D, + ARM64_INS_INSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSR_ZV_H, ARM64_INS_INSR, + {AArch64_INSR_ZV_H, + ARM64_INS_INSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSR_ZV_S, ARM64_INS_INSR, + {AArch64_INSR_ZV_S, + ARM64_INS_INSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSvi16gpr, ARM64_INS_INS, + {AArch64_INSvi16gpr, + ARM64_INS_INS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSvi16lane, ARM64_INS_INS, + {AArch64_INSvi16lane, + ARM64_INS_INS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSvi32gpr, ARM64_INS_INS, + {AArch64_INSvi32gpr, + ARM64_INS_INS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSvi32lane, ARM64_INS_INS, + {AArch64_INSvi32lane, + ARM64_INS_INS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSvi64gpr, ARM64_INS_INS, + {AArch64_INSvi64gpr, + ARM64_INS_INS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSvi64lane, ARM64_INS_INS, + {AArch64_INSvi64lane, + ARM64_INS_INS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSvi8gpr, ARM64_INS_INS, + {AArch64_INSvi8gpr, + ARM64_INS_INS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_INSvi8lane, ARM64_INS_INS, + {AArch64_INSvi8lane, + ARM64_INS_INS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ISB, ARM64_INS_ISB, + {AArch64_ISB, + ARM64_INS_ISB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTA_RPZ_B, ARM64_INS_LASTA, + {AArch64_LASTA_RPZ_B, + ARM64_INS_LASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTA_RPZ_D, ARM64_INS_LASTA, + {AArch64_LASTA_RPZ_D, + ARM64_INS_LASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTA_RPZ_H, ARM64_INS_LASTA, + {AArch64_LASTA_RPZ_H, + ARM64_INS_LASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTA_RPZ_S, ARM64_INS_LASTA, + {AArch64_LASTA_RPZ_S, + ARM64_INS_LASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTA_VPZ_B, ARM64_INS_LASTA, + {AArch64_LASTA_VPZ_B, + ARM64_INS_LASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTA_VPZ_D, ARM64_INS_LASTA, + {AArch64_LASTA_VPZ_D, + ARM64_INS_LASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTA_VPZ_H, ARM64_INS_LASTA, + {AArch64_LASTA_VPZ_H, + ARM64_INS_LASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTA_VPZ_S, ARM64_INS_LASTA, + {AArch64_LASTA_VPZ_S, + ARM64_INS_LASTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTB_RPZ_B, ARM64_INS_LASTB, + {AArch64_LASTB_RPZ_B, + ARM64_INS_LASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTB_RPZ_D, ARM64_INS_LASTB, + {AArch64_LASTB_RPZ_D, + ARM64_INS_LASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTB_RPZ_H, ARM64_INS_LASTB, + {AArch64_LASTB_RPZ_H, + ARM64_INS_LASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTB_RPZ_S, ARM64_INS_LASTB, + {AArch64_LASTB_RPZ_S, + ARM64_INS_LASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTB_VPZ_B, ARM64_INS_LASTB, + {AArch64_LASTB_VPZ_B, + ARM64_INS_LASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTB_VPZ_D, ARM64_INS_LASTB, + {AArch64_LASTB_VPZ_D, + ARM64_INS_LASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTB_VPZ_H, ARM64_INS_LASTB, + {AArch64_LASTB_VPZ_H, + ARM64_INS_LASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LASTB_VPZ_S, ARM64_INS_LASTB, + {AArch64_LASTB_VPZ_S, + ARM64_INS_LASTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1B, ARM64_INS_LD1B, + {AArch64_LD1B, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1B_D, ARM64_INS_LD1B, + {AArch64_LD1B_D, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1B_D_IMM_REAL, ARM64_INS_LD1B, + {AArch64_LD1B_D_IMM_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1B_H, ARM64_INS_LD1B, + {AArch64_LD1B_H, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1B_H_IMM_REAL, ARM64_INS_LD1B, + {AArch64_LD1B_H_IMM_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1B_IMM_REAL, ARM64_INS_LD1B, + {AArch64_LD1B_IMM_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1B_S, ARM64_INS_LD1B, + {AArch64_LD1B_S, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1B_S_IMM_REAL, ARM64_INS_LD1B, + {AArch64_LD1B_S_IMM_REAL, + ARM64_INS_LD1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1D, ARM64_INS_LD1D, + {AArch64_LD1D, + ARM64_INS_LD1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1D_IMM_REAL, ARM64_INS_LD1D, + {AArch64_LD1D_IMM_REAL, + ARM64_INS_LD1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv16b, ARM64_INS_LD1, + {AArch64_LD1Fourv16b, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv16b_POST, ARM64_INS_LD1, + {AArch64_LD1Fourv16b_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv1d, ARM64_INS_LD1, + {AArch64_LD1Fourv1d, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv1d_POST, ARM64_INS_LD1, + {AArch64_LD1Fourv1d_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv2d, ARM64_INS_LD1, + {AArch64_LD1Fourv2d, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv2d_POST, ARM64_INS_LD1, + {AArch64_LD1Fourv2d_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv2s, ARM64_INS_LD1, + {AArch64_LD1Fourv2s, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv2s_POST, ARM64_INS_LD1, + {AArch64_LD1Fourv2s_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv4h, ARM64_INS_LD1, + {AArch64_LD1Fourv4h, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv4h_POST, ARM64_INS_LD1, + {AArch64_LD1Fourv4h_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv4s, ARM64_INS_LD1, + {AArch64_LD1Fourv4s, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv4s_POST, ARM64_INS_LD1, + {AArch64_LD1Fourv4s_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv8b, ARM64_INS_LD1, + {AArch64_LD1Fourv8b, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv8b_POST, ARM64_INS_LD1, + {AArch64_LD1Fourv8b_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv8h, ARM64_INS_LD1, + {AArch64_LD1Fourv8h, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Fourv8h_POST, ARM64_INS_LD1, + {AArch64_LD1Fourv8h_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1H, ARM64_INS_LD1H, + {AArch64_LD1H, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1H_D, ARM64_INS_LD1H, + {AArch64_LD1H_D, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1H_D_IMM_REAL, ARM64_INS_LD1H, + {AArch64_LD1H_D_IMM_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1H_IMM_REAL, ARM64_INS_LD1H, + {AArch64_LD1H_IMM_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1H_S, ARM64_INS_LD1H, + {AArch64_LD1H_S, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1H_S_IMM_REAL, ARM64_INS_LD1H, + {AArch64_LD1H_S_IMM_REAL, + ARM64_INS_LD1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev16b, ARM64_INS_LD1, + {AArch64_LD1Onev16b, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev16b_POST, ARM64_INS_LD1, + {AArch64_LD1Onev16b_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev1d, ARM64_INS_LD1, + {AArch64_LD1Onev1d, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev1d_POST, ARM64_INS_LD1, + {AArch64_LD1Onev1d_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev2d, ARM64_INS_LD1, + {AArch64_LD1Onev2d, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev2d_POST, ARM64_INS_LD1, + {AArch64_LD1Onev2d_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev2s, ARM64_INS_LD1, + {AArch64_LD1Onev2s, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev2s_POST, ARM64_INS_LD1, + {AArch64_LD1Onev2s_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev4h, ARM64_INS_LD1, + {AArch64_LD1Onev4h, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev4h_POST, ARM64_INS_LD1, + {AArch64_LD1Onev4h_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev4s, ARM64_INS_LD1, + {AArch64_LD1Onev4s, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev4s_POST, ARM64_INS_LD1, + {AArch64_LD1Onev4s_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev8b, ARM64_INS_LD1, + {AArch64_LD1Onev8b, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev8b_POST, ARM64_INS_LD1, + {AArch64_LD1Onev8b_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev8h, ARM64_INS_LD1, + {AArch64_LD1Onev8h, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Onev8h_POST, ARM64_INS_LD1, + {AArch64_LD1Onev8h_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RB_D_IMM, ARM64_INS_LD1RB, + {AArch64_LD1RB_D_IMM, + ARM64_INS_LD1RB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RB_H_IMM, ARM64_INS_LD1RB, + {AArch64_LD1RB_H_IMM, + ARM64_INS_LD1RB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RB_IMM, ARM64_INS_LD1RB, + {AArch64_LD1RB_IMM, + ARM64_INS_LD1RB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RB_S_IMM, ARM64_INS_LD1RB, + {AArch64_LD1RB_S_IMM, + ARM64_INS_LD1RB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RD_IMM, ARM64_INS_LD1RD, + {AArch64_LD1RD_IMM, + ARM64_INS_LD1RD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RH_D_IMM, ARM64_INS_LD1RH, + {AArch64_LD1RH_D_IMM, + ARM64_INS_LD1RH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RH_IMM, ARM64_INS_LD1RH, + {AArch64_LD1RH_IMM, + ARM64_INS_LD1RH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RH_S_IMM, ARM64_INS_LD1RH, + {AArch64_LD1RH_S_IMM, + ARM64_INS_LD1RH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RQ_B, ARM64_INS_LD1RQB, + {AArch64_LD1RQ_B, + ARM64_INS_LD1RQB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RQ_B_IMM, ARM64_INS_LD1RQB, + {AArch64_LD1RQ_B_IMM, + ARM64_INS_LD1RQB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RQ_D, ARM64_INS_LD1RQD, + {AArch64_LD1RQ_D, + ARM64_INS_LD1RQD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RQ_D_IMM, ARM64_INS_LD1RQD, + {AArch64_LD1RQ_D_IMM, + ARM64_INS_LD1RQD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RQ_H, ARM64_INS_LD1RQH, + {AArch64_LD1RQ_H, + ARM64_INS_LD1RQH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RQ_H_IMM, ARM64_INS_LD1RQH, + {AArch64_LD1RQ_H_IMM, + ARM64_INS_LD1RQH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RQ_W, ARM64_INS_LD1RQW, + {AArch64_LD1RQ_W, + ARM64_INS_LD1RQW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RQ_W_IMM, ARM64_INS_LD1RQW, + {AArch64_LD1RQ_W_IMM, + ARM64_INS_LD1RQW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RSB_D_IMM, ARM64_INS_LD1RSB, + {AArch64_LD1RSB_D_IMM, + ARM64_INS_LD1RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RSB_H_IMM, ARM64_INS_LD1RSB, + {AArch64_LD1RSB_H_IMM, + ARM64_INS_LD1RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RSB_S_IMM, ARM64_INS_LD1RSB, + {AArch64_LD1RSB_S_IMM, + ARM64_INS_LD1RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RSH_D_IMM, ARM64_INS_LD1RSH, + {AArch64_LD1RSH_D_IMM, + ARM64_INS_LD1RSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RSH_S_IMM, ARM64_INS_LD1RSH, + {AArch64_LD1RSH_S_IMM, + ARM64_INS_LD1RSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RSW_IMM, ARM64_INS_LD1RSW, + {AArch64_LD1RSW_IMM, + ARM64_INS_LD1RSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RW_D_IMM, ARM64_INS_LD1RW, + {AArch64_LD1RW_D_IMM, + ARM64_INS_LD1RW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1RW_IMM, ARM64_INS_LD1RW, + {AArch64_LD1RW_IMM, + ARM64_INS_LD1RW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv16b, ARM64_INS_LD1R, + {AArch64_LD1Rv16b, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv16b_POST, ARM64_INS_LD1R, + {AArch64_LD1Rv16b_POST, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv1d, ARM64_INS_LD1R, + {AArch64_LD1Rv1d, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv1d_POST, ARM64_INS_LD1R, + {AArch64_LD1Rv1d_POST, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv2d, ARM64_INS_LD1R, + {AArch64_LD1Rv2d, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv2d_POST, ARM64_INS_LD1R, + {AArch64_LD1Rv2d_POST, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv2s, ARM64_INS_LD1R, + {AArch64_LD1Rv2s, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv2s_POST, ARM64_INS_LD1R, + {AArch64_LD1Rv2s_POST, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv4h, ARM64_INS_LD1R, + {AArch64_LD1Rv4h, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv4h_POST, ARM64_INS_LD1R, + {AArch64_LD1Rv4h_POST, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv4s, ARM64_INS_LD1R, + {AArch64_LD1Rv4s, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv4s_POST, ARM64_INS_LD1R, + {AArch64_LD1Rv4s_POST, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv8b, ARM64_INS_LD1R, + {AArch64_LD1Rv8b, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv8b_POST, ARM64_INS_LD1R, + {AArch64_LD1Rv8b_POST, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv8h, ARM64_INS_LD1R, + {AArch64_LD1Rv8h, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Rv8h_POST, ARM64_INS_LD1R, + {AArch64_LD1Rv8h_POST, + ARM64_INS_LD1R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SB_D, ARM64_INS_LD1SB, + {AArch64_LD1SB_D, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SB_D_IMM_REAL, ARM64_INS_LD1SB, + {AArch64_LD1SB_D_IMM_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SB_H, ARM64_INS_LD1SB, + {AArch64_LD1SB_H, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SB_H_IMM_REAL, ARM64_INS_LD1SB, + {AArch64_LD1SB_H_IMM_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SB_S, ARM64_INS_LD1SB, + {AArch64_LD1SB_S, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SB_S_IMM_REAL, ARM64_INS_LD1SB, + {AArch64_LD1SB_S_IMM_REAL, + ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SH_D, ARM64_INS_LD1SH, + {AArch64_LD1SH_D, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SH_D_IMM_REAL, ARM64_INS_LD1SH, + {AArch64_LD1SH_D_IMM_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SH_S, ARM64_INS_LD1SH, + {AArch64_LD1SH_S, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SH_S_IMM_REAL, ARM64_INS_LD1SH, + {AArch64_LD1SH_S_IMM_REAL, + ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SW_D, ARM64_INS_LD1SW, + {AArch64_LD1SW_D, + ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1SW_D_IMM_REAL, ARM64_INS_LD1SW, + {AArch64_LD1SW_D_IMM_REAL, + ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev16b, ARM64_INS_LD1, + {AArch64_LD1Threev16b, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev16b_POST, ARM64_INS_LD1, + {AArch64_LD1Threev16b_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev1d, ARM64_INS_LD1, + {AArch64_LD1Threev1d, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev1d_POST, ARM64_INS_LD1, + {AArch64_LD1Threev1d_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev2d, ARM64_INS_LD1, + {AArch64_LD1Threev2d, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev2d_POST, ARM64_INS_LD1, + {AArch64_LD1Threev2d_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev2s, ARM64_INS_LD1, + {AArch64_LD1Threev2s, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev2s_POST, ARM64_INS_LD1, + {AArch64_LD1Threev2s_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev4h, ARM64_INS_LD1, + {AArch64_LD1Threev4h, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev4h_POST, ARM64_INS_LD1, + {AArch64_LD1Threev4h_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev4s, ARM64_INS_LD1, + {AArch64_LD1Threev4s, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev4s_POST, ARM64_INS_LD1, + {AArch64_LD1Threev4s_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev8b, ARM64_INS_LD1, + {AArch64_LD1Threev8b, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev8b_POST, ARM64_INS_LD1, + {AArch64_LD1Threev8b_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev8h, ARM64_INS_LD1, + {AArch64_LD1Threev8h, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Threev8h_POST, ARM64_INS_LD1, + {AArch64_LD1Threev8h_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov16b, ARM64_INS_LD1, + {AArch64_LD1Twov16b, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov16b_POST, ARM64_INS_LD1, + {AArch64_LD1Twov16b_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov1d, ARM64_INS_LD1, + {AArch64_LD1Twov1d, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov1d_POST, ARM64_INS_LD1, + {AArch64_LD1Twov1d_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov2d, ARM64_INS_LD1, + {AArch64_LD1Twov2d, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov2d_POST, ARM64_INS_LD1, + {AArch64_LD1Twov2d_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov2s, ARM64_INS_LD1, + {AArch64_LD1Twov2s, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov2s_POST, ARM64_INS_LD1, + {AArch64_LD1Twov2s_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov4h, ARM64_INS_LD1, + {AArch64_LD1Twov4h, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov4h_POST, ARM64_INS_LD1, + {AArch64_LD1Twov4h_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov4s, ARM64_INS_LD1, + {AArch64_LD1Twov4s, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov4s_POST, ARM64_INS_LD1, + {AArch64_LD1Twov4s_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov8b, ARM64_INS_LD1, + {AArch64_LD1Twov8b, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov8b_POST, ARM64_INS_LD1, + {AArch64_LD1Twov8b_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov8h, ARM64_INS_LD1, + {AArch64_LD1Twov8h, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1Twov8h_POST, ARM64_INS_LD1, + {AArch64_LD1Twov8h_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1W, ARM64_INS_LD1W, + {AArch64_LD1W, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1W_D, ARM64_INS_LD1W, + {AArch64_LD1W_D, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1W_D_IMM_REAL, ARM64_INS_LD1W, + {AArch64_LD1W_D_IMM_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1W_IMM_REAL, ARM64_INS_LD1W, + {AArch64_LD1W_IMM_REAL, + ARM64_INS_LD1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1i16, ARM64_INS_LD1, + {AArch64_LD1i16, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1i16_POST, ARM64_INS_LD1, + {AArch64_LD1i16_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1i32, ARM64_INS_LD1, + {AArch64_LD1i32, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1i32_POST, ARM64_INS_LD1, + {AArch64_LD1i32_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1i64, ARM64_INS_LD1, + {AArch64_LD1i64, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1i64_POST, ARM64_INS_LD1, + {AArch64_LD1i64_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1i8, ARM64_INS_LD1, + {AArch64_LD1i8, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD1i8_POST, ARM64_INS_LD1, + {AArch64_LD1i8_POST, + ARM64_INS_LD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2B, ARM64_INS_LD2B, + {AArch64_LD2B, + ARM64_INS_LD2B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2B_IMM, ARM64_INS_LD2B, + {AArch64_LD2B_IMM, + ARM64_INS_LD2B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2D, ARM64_INS_LD2D, + {AArch64_LD2D, + ARM64_INS_LD2D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2D_IMM, ARM64_INS_LD2D, + {AArch64_LD2D_IMM, + ARM64_INS_LD2D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2H, ARM64_INS_LD2H, + {AArch64_LD2H, + ARM64_INS_LD2H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2H_IMM, ARM64_INS_LD2H, + {AArch64_LD2H_IMM, + ARM64_INS_LD2H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv16b, ARM64_INS_LD2R, + {AArch64_LD2Rv16b, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv16b_POST, ARM64_INS_LD2R, + {AArch64_LD2Rv16b_POST, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv1d, ARM64_INS_LD2R, + {AArch64_LD2Rv1d, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv1d_POST, ARM64_INS_LD2R, + {AArch64_LD2Rv1d_POST, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv2d, ARM64_INS_LD2R, + {AArch64_LD2Rv2d, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv2d_POST, ARM64_INS_LD2R, + {AArch64_LD2Rv2d_POST, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv2s, ARM64_INS_LD2R, + {AArch64_LD2Rv2s, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv2s_POST, ARM64_INS_LD2R, + {AArch64_LD2Rv2s_POST, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv4h, ARM64_INS_LD2R, + {AArch64_LD2Rv4h, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv4h_POST, ARM64_INS_LD2R, + {AArch64_LD2Rv4h_POST, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv4s, ARM64_INS_LD2R, + {AArch64_LD2Rv4s, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv4s_POST, ARM64_INS_LD2R, + {AArch64_LD2Rv4s_POST, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv8b, ARM64_INS_LD2R, + {AArch64_LD2Rv8b, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv8b_POST, ARM64_INS_LD2R, + {AArch64_LD2Rv8b_POST, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv8h, ARM64_INS_LD2R, + {AArch64_LD2Rv8h, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Rv8h_POST, ARM64_INS_LD2R, + {AArch64_LD2Rv8h_POST, + ARM64_INS_LD2R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov16b, ARM64_INS_LD2, + {AArch64_LD2Twov16b, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov16b_POST, ARM64_INS_LD2, + {AArch64_LD2Twov16b_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov2d, ARM64_INS_LD2, + {AArch64_LD2Twov2d, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov2d_POST, ARM64_INS_LD2, + {AArch64_LD2Twov2d_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov2s, ARM64_INS_LD2, + {AArch64_LD2Twov2s, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov2s_POST, ARM64_INS_LD2, + {AArch64_LD2Twov2s_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov4h, ARM64_INS_LD2, + {AArch64_LD2Twov4h, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov4h_POST, ARM64_INS_LD2, + {AArch64_LD2Twov4h_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov4s, ARM64_INS_LD2, + {AArch64_LD2Twov4s, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov4s_POST, ARM64_INS_LD2, + {AArch64_LD2Twov4s_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov8b, ARM64_INS_LD2, + {AArch64_LD2Twov8b, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov8b_POST, ARM64_INS_LD2, + {AArch64_LD2Twov8b_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov8h, ARM64_INS_LD2, + {AArch64_LD2Twov8h, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2Twov8h_POST, ARM64_INS_LD2, + {AArch64_LD2Twov8h_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2W, ARM64_INS_LD2W, + {AArch64_LD2W, + ARM64_INS_LD2W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2W_IMM, ARM64_INS_LD2W, + {AArch64_LD2W_IMM, + ARM64_INS_LD2W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2i16, ARM64_INS_LD2, + {AArch64_LD2i16, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2i16_POST, ARM64_INS_LD2, + {AArch64_LD2i16_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2i32, ARM64_INS_LD2, + {AArch64_LD2i32, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2i32_POST, ARM64_INS_LD2, + {AArch64_LD2i32_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2i64, ARM64_INS_LD2, + {AArch64_LD2i64, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2i64_POST, ARM64_INS_LD2, + {AArch64_LD2i64_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2i8, ARM64_INS_LD2, + {AArch64_LD2i8, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD2i8_POST, ARM64_INS_LD2, + {AArch64_LD2i8_POST, + ARM64_INS_LD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3B, ARM64_INS_LD3B, + {AArch64_LD3B, + ARM64_INS_LD3B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3B_IMM, ARM64_INS_LD3B, + {AArch64_LD3B_IMM, + ARM64_INS_LD3B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3D, ARM64_INS_LD3D, + {AArch64_LD3D, + ARM64_INS_LD3D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3D_IMM, ARM64_INS_LD3D, + {AArch64_LD3D_IMM, + ARM64_INS_LD3D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3H, ARM64_INS_LD3H, + {AArch64_LD3H, + ARM64_INS_LD3H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3H_IMM, ARM64_INS_LD3H, + {AArch64_LD3H_IMM, + ARM64_INS_LD3H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv16b, ARM64_INS_LD3R, + {AArch64_LD3Rv16b, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv16b_POST, ARM64_INS_LD3R, + {AArch64_LD3Rv16b_POST, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv1d, ARM64_INS_LD3R, + {AArch64_LD3Rv1d, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv1d_POST, ARM64_INS_LD3R, + {AArch64_LD3Rv1d_POST, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv2d, ARM64_INS_LD3R, + {AArch64_LD3Rv2d, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv2d_POST, ARM64_INS_LD3R, + {AArch64_LD3Rv2d_POST, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv2s, ARM64_INS_LD3R, + {AArch64_LD3Rv2s, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv2s_POST, ARM64_INS_LD3R, + {AArch64_LD3Rv2s_POST, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv4h, ARM64_INS_LD3R, + {AArch64_LD3Rv4h, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv4h_POST, ARM64_INS_LD3R, + {AArch64_LD3Rv4h_POST, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv4s, ARM64_INS_LD3R, + {AArch64_LD3Rv4s, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv4s_POST, ARM64_INS_LD3R, + {AArch64_LD3Rv4s_POST, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv8b, ARM64_INS_LD3R, + {AArch64_LD3Rv8b, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv8b_POST, ARM64_INS_LD3R, + {AArch64_LD3Rv8b_POST, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv8h, ARM64_INS_LD3R, + {AArch64_LD3Rv8h, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Rv8h_POST, ARM64_INS_LD3R, + {AArch64_LD3Rv8h_POST, + ARM64_INS_LD3R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev16b, ARM64_INS_LD3, + {AArch64_LD3Threev16b, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev16b_POST, ARM64_INS_LD3, + {AArch64_LD3Threev16b_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev2d, ARM64_INS_LD3, + {AArch64_LD3Threev2d, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev2d_POST, ARM64_INS_LD3, + {AArch64_LD3Threev2d_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev2s, ARM64_INS_LD3, + {AArch64_LD3Threev2s, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev2s_POST, ARM64_INS_LD3, + {AArch64_LD3Threev2s_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev4h, ARM64_INS_LD3, + {AArch64_LD3Threev4h, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev4h_POST, ARM64_INS_LD3, + {AArch64_LD3Threev4h_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev4s, ARM64_INS_LD3, + {AArch64_LD3Threev4s, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev4s_POST, ARM64_INS_LD3, + {AArch64_LD3Threev4s_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev8b, ARM64_INS_LD3, + {AArch64_LD3Threev8b, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev8b_POST, ARM64_INS_LD3, + {AArch64_LD3Threev8b_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev8h, ARM64_INS_LD3, + {AArch64_LD3Threev8h, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3Threev8h_POST, ARM64_INS_LD3, + {AArch64_LD3Threev8h_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3W, ARM64_INS_LD3W, + {AArch64_LD3W, + ARM64_INS_LD3W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3W_IMM, ARM64_INS_LD3W, + {AArch64_LD3W_IMM, + ARM64_INS_LD3W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3i16, ARM64_INS_LD3, + {AArch64_LD3i16, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3i16_POST, ARM64_INS_LD3, + {AArch64_LD3i16_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3i32, ARM64_INS_LD3, + {AArch64_LD3i32, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3i32_POST, ARM64_INS_LD3, + {AArch64_LD3i32_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3i64, ARM64_INS_LD3, + {AArch64_LD3i64, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3i64_POST, ARM64_INS_LD3, + {AArch64_LD3i64_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3i8, ARM64_INS_LD3, + {AArch64_LD3i8, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD3i8_POST, ARM64_INS_LD3, + {AArch64_LD3i8_POST, + ARM64_INS_LD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4B, ARM64_INS_LD4B, + {AArch64_LD4B, + ARM64_INS_LD4B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4B_IMM, ARM64_INS_LD4B, + {AArch64_LD4B_IMM, + ARM64_INS_LD4B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4D, ARM64_INS_LD4D, + {AArch64_LD4D, + ARM64_INS_LD4D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4D_IMM, ARM64_INS_LD4D, + {AArch64_LD4D_IMM, + ARM64_INS_LD4D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv16b, ARM64_INS_LD4, + {AArch64_LD4Fourv16b, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv16b_POST, ARM64_INS_LD4, + {AArch64_LD4Fourv16b_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv2d, ARM64_INS_LD4, + {AArch64_LD4Fourv2d, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv2d_POST, ARM64_INS_LD4, + {AArch64_LD4Fourv2d_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv2s, ARM64_INS_LD4, + {AArch64_LD4Fourv2s, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv2s_POST, ARM64_INS_LD4, + {AArch64_LD4Fourv2s_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv4h, ARM64_INS_LD4, + {AArch64_LD4Fourv4h, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv4h_POST, ARM64_INS_LD4, + {AArch64_LD4Fourv4h_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv4s, ARM64_INS_LD4, + {AArch64_LD4Fourv4s, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv4s_POST, ARM64_INS_LD4, + {AArch64_LD4Fourv4s_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv8b, ARM64_INS_LD4, + {AArch64_LD4Fourv8b, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv8b_POST, ARM64_INS_LD4, + {AArch64_LD4Fourv8b_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv8h, ARM64_INS_LD4, + {AArch64_LD4Fourv8h, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Fourv8h_POST, ARM64_INS_LD4, + {AArch64_LD4Fourv8h_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4H, ARM64_INS_LD4H, + {AArch64_LD4H, + ARM64_INS_LD4H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4H_IMM, ARM64_INS_LD4H, + {AArch64_LD4H_IMM, + ARM64_INS_LD4H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv16b, ARM64_INS_LD4R, + {AArch64_LD4Rv16b, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv16b_POST, ARM64_INS_LD4R, + {AArch64_LD4Rv16b_POST, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv1d, ARM64_INS_LD4R, + {AArch64_LD4Rv1d, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv1d_POST, ARM64_INS_LD4R, + {AArch64_LD4Rv1d_POST, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv2d, ARM64_INS_LD4R, + {AArch64_LD4Rv2d, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv2d_POST, ARM64_INS_LD4R, + {AArch64_LD4Rv2d_POST, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv2s, ARM64_INS_LD4R, + {AArch64_LD4Rv2s, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv2s_POST, ARM64_INS_LD4R, + {AArch64_LD4Rv2s_POST, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv4h, ARM64_INS_LD4R, + {AArch64_LD4Rv4h, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv4h_POST, ARM64_INS_LD4R, + {AArch64_LD4Rv4h_POST, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv4s, ARM64_INS_LD4R, + {AArch64_LD4Rv4s, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv4s_POST, ARM64_INS_LD4R, + {AArch64_LD4Rv4s_POST, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv8b, ARM64_INS_LD4R, + {AArch64_LD4Rv8b, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv8b_POST, ARM64_INS_LD4R, + {AArch64_LD4Rv8b_POST, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv8h, ARM64_INS_LD4R, + {AArch64_LD4Rv8h, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4Rv8h_POST, ARM64_INS_LD4R, + {AArch64_LD4Rv8h_POST, + ARM64_INS_LD4R, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4W, ARM64_INS_LD4W, + {AArch64_LD4W, + ARM64_INS_LD4W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4W_IMM, ARM64_INS_LD4W, + {AArch64_LD4W_IMM, + ARM64_INS_LD4W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4i16, ARM64_INS_LD4, + {AArch64_LD4i16, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4i16_POST, ARM64_INS_LD4, + {AArch64_LD4i16_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4i32, ARM64_INS_LD4, + {AArch64_LD4i32, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4i32_POST, ARM64_INS_LD4, + {AArch64_LD4i32_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4i64, ARM64_INS_LD4, + {AArch64_LD4i64, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4i64_POST, ARM64_INS_LD4, + {AArch64_LD4i64_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4i8, ARM64_INS_LD4, + {AArch64_LD4i8, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LD4i8_POST, ARM64_INS_LD4, + {AArch64_LD4i8_POST, + ARM64_INS_LD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDAB, ARM64_INS_LDADDAB, + {AArch64_LDADDAB, + ARM64_INS_LDADDAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDAH, ARM64_INS_LDADDAH, + {AArch64_LDADDAH, + ARM64_INS_LDADDAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDALB, ARM64_INS_LDADDALB, + {AArch64_LDADDALB, + ARM64_INS_LDADDALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDALH, ARM64_INS_LDADDALH, + {AArch64_LDADDALH, + ARM64_INS_LDADDALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDALW, ARM64_INS_LDADDAL, + {AArch64_LDADDALW, + ARM64_INS_LDADDAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDALX, ARM64_INS_LDADDAL, + {AArch64_LDADDALX, + ARM64_INS_LDADDAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDAW, ARM64_INS_LDADDA, + {AArch64_LDADDAW, + ARM64_INS_LDADDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDAX, ARM64_INS_LDADDA, + {AArch64_LDADDAX, + ARM64_INS_LDADDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDB, ARM64_INS_LDADDB, + {AArch64_LDADDB, + ARM64_INS_LDADDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDH, ARM64_INS_LDADDH, + {AArch64_LDADDH, + ARM64_INS_LDADDH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDLB, ARM64_INS_LDADDLB, + {AArch64_LDADDLB, + ARM64_INS_LDADDLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDLH, ARM64_INS_LDADDLH, + {AArch64_LDADDLH, + ARM64_INS_LDADDLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDLW, ARM64_INS_LDADDL, + {AArch64_LDADDLW, + ARM64_INS_LDADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDLX, ARM64_INS_LDADDL, + {AArch64_LDADDLX, + ARM64_INS_LDADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDW, ARM64_INS_LDADD, + {AArch64_LDADDW, + ARM64_INS_LDADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDADDX, ARM64_INS_LDADD, + {AArch64_LDADDX, + ARM64_INS_LDADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPRB, ARM64_INS_LDAPRB, + {AArch64_LDAPRB, + ARM64_INS_LDAPRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPRH, ARM64_INS_LDAPRH, + {AArch64_LDAPRH, + ARM64_INS_LDAPRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPRW, ARM64_INS_LDAPR, + {AArch64_LDAPRW, + ARM64_INS_LDAPR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPRX, ARM64_INS_LDAPR, + {AArch64_LDAPRX, + ARM64_INS_LDAPR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPURBi, ARM64_INS_LDAPURB, + {AArch64_LDAPURBi, + ARM64_INS_LDAPURB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPURHi, ARM64_INS_LDAPURH, + {AArch64_LDAPURHi, + ARM64_INS_LDAPURH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPURSBWi, ARM64_INS_LDAPURSB, + {AArch64_LDAPURSBWi, + ARM64_INS_LDAPURSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPURSBXi, ARM64_INS_LDAPURSB, + {AArch64_LDAPURSBXi, + ARM64_INS_LDAPURSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPURSHWi, ARM64_INS_LDAPURSH, + {AArch64_LDAPURSHWi, + ARM64_INS_LDAPURSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPURSHXi, ARM64_INS_LDAPURSH, + {AArch64_LDAPURSHXi, + ARM64_INS_LDAPURSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPURSWi, ARM64_INS_LDAPURSW, + {AArch64_LDAPURSWi, + ARM64_INS_LDAPURSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPURXi, ARM64_INS_LDAPUR, + {AArch64_LDAPURXi, + ARM64_INS_LDAPUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAPURi, ARM64_INS_LDAPUR, + {AArch64_LDAPURi, + ARM64_INS_LDAPUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDARB, ARM64_INS_LDARB, + {AArch64_LDARB, + ARM64_INS_LDARB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDARH, ARM64_INS_LDARH, + {AArch64_LDARH, + ARM64_INS_LDARH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDARW, ARM64_INS_LDAR, + {AArch64_LDARW, + ARM64_INS_LDAR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDARX, ARM64_INS_LDAR, + {AArch64_LDARX, + ARM64_INS_LDAR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAXPW, ARM64_INS_LDAXP, + {AArch64_LDAXPW, + ARM64_INS_LDAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAXPX, ARM64_INS_LDAXP, + {AArch64_LDAXPX, + ARM64_INS_LDAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAXRB, ARM64_INS_LDAXRB, + {AArch64_LDAXRB, + ARM64_INS_LDAXRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAXRH, ARM64_INS_LDAXRH, + {AArch64_LDAXRH, + ARM64_INS_LDAXRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAXRW, ARM64_INS_LDAXR, + {AArch64_LDAXRW, + ARM64_INS_LDAXR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDAXRX, ARM64_INS_LDAXR, + {AArch64_LDAXRX, + ARM64_INS_LDAXR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRAB, ARM64_INS_LDCLRAB, + {AArch64_LDCLRAB, + ARM64_INS_LDCLRAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRAH, ARM64_INS_LDCLRAH, + {AArch64_LDCLRAH, + ARM64_INS_LDCLRAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRALB, ARM64_INS_LDCLRALB, + {AArch64_LDCLRALB, + ARM64_INS_LDCLRALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRALH, ARM64_INS_LDCLRALH, + {AArch64_LDCLRALH, + ARM64_INS_LDCLRALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRALW, ARM64_INS_LDCLRAL, + {AArch64_LDCLRALW, + ARM64_INS_LDCLRAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRALX, ARM64_INS_LDCLRAL, + {AArch64_LDCLRALX, + ARM64_INS_LDCLRAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRAW, ARM64_INS_LDCLRA, + {AArch64_LDCLRAW, + ARM64_INS_LDCLRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRAX, ARM64_INS_LDCLRA, + {AArch64_LDCLRAX, + ARM64_INS_LDCLRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRB, ARM64_INS_LDCLRB, + {AArch64_LDCLRB, + ARM64_INS_LDCLRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRH, ARM64_INS_LDCLRH, + {AArch64_LDCLRH, + ARM64_INS_LDCLRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRLB, ARM64_INS_LDCLRLB, + {AArch64_LDCLRLB, + ARM64_INS_LDCLRLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRLH, ARM64_INS_LDCLRLH, + {AArch64_LDCLRLH, + ARM64_INS_LDCLRLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRLW, ARM64_INS_LDCLRL, + {AArch64_LDCLRLW, + ARM64_INS_LDCLRL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRLX, ARM64_INS_LDCLRL, + {AArch64_LDCLRLX, + ARM64_INS_LDCLRL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRW, ARM64_INS_LDCLR, + {AArch64_LDCLRW, + ARM64_INS_LDCLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDCLRX, ARM64_INS_LDCLR, + {AArch64_LDCLRX, + ARM64_INS_LDCLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORAB, ARM64_INS_LDEORAB, + {AArch64_LDEORAB, + ARM64_INS_LDEORAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORAH, ARM64_INS_LDEORAH, + {AArch64_LDEORAH, + ARM64_INS_LDEORAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORALB, ARM64_INS_LDEORALB, + {AArch64_LDEORALB, + ARM64_INS_LDEORALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORALH, ARM64_INS_LDEORALH, + {AArch64_LDEORALH, + ARM64_INS_LDEORALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORALW, ARM64_INS_LDEORAL, + {AArch64_LDEORALW, + ARM64_INS_LDEORAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORALX, ARM64_INS_LDEORAL, + {AArch64_LDEORALX, + ARM64_INS_LDEORAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORAW, ARM64_INS_LDEORA, + {AArch64_LDEORAW, + ARM64_INS_LDEORA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORAX, ARM64_INS_LDEORA, + {AArch64_LDEORAX, + ARM64_INS_LDEORA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORB, ARM64_INS_LDEORB, + {AArch64_LDEORB, + ARM64_INS_LDEORB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORH, ARM64_INS_LDEORH, + {AArch64_LDEORH, + ARM64_INS_LDEORH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORLB, ARM64_INS_LDEORLB, + {AArch64_LDEORLB, + ARM64_INS_LDEORLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORLH, ARM64_INS_LDEORLH, + {AArch64_LDEORLH, + ARM64_INS_LDEORLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORLW, ARM64_INS_LDEORL, + {AArch64_LDEORLW, + ARM64_INS_LDEORL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORLX, ARM64_INS_LDEORL, + {AArch64_LDEORLX, + ARM64_INS_LDEORL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORW, ARM64_INS_LDEOR, + {AArch64_LDEORW, + ARM64_INS_LDEOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDEORX, ARM64_INS_LDEOR, + {AArch64_LDEORX, + ARM64_INS_LDEOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1B_D_REAL, ARM64_INS_LDFF1B, + {AArch64_LDFF1B_D_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1B_H_REAL, ARM64_INS_LDFF1B, + {AArch64_LDFF1B_H_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1B_REAL, ARM64_INS_LDFF1B, + {AArch64_LDFF1B_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1B_S_REAL, ARM64_INS_LDFF1B, + {AArch64_LDFF1B_S_REAL, + ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1D_REAL, ARM64_INS_LDFF1D, + {AArch64_LDFF1D_REAL, + ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1H_D_REAL, ARM64_INS_LDFF1H, + {AArch64_LDFF1H_D_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1H_REAL, ARM64_INS_LDFF1H, + {AArch64_LDFF1H_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1H_S_REAL, ARM64_INS_LDFF1H, + {AArch64_LDFF1H_S_REAL, + ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1SB_D_REAL, ARM64_INS_LDFF1SB, + {AArch64_LDFF1SB_D_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1SB_H_REAL, ARM64_INS_LDFF1SB, + {AArch64_LDFF1SB_H_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1SB_S_REAL, ARM64_INS_LDFF1SB, + {AArch64_LDFF1SB_S_REAL, + ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1SH_D_REAL, ARM64_INS_LDFF1SH, + {AArch64_LDFF1SH_D_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1SH_S_REAL, ARM64_INS_LDFF1SH, + {AArch64_LDFF1SH_S_REAL, + ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1SW_D_REAL, ARM64_INS_LDFF1SW, + {AArch64_LDFF1SW_D_REAL, + ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1W_D_REAL, ARM64_INS_LDFF1W, + {AArch64_LDFF1W_D_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDFF1W_REAL, ARM64_INS_LDFF1W, + {AArch64_LDFF1W_REAL, + ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDLARB, ARM64_INS_LDLARB, + {AArch64_LDLARB, + ARM64_INS_LDLARB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDLARH, ARM64_INS_LDLARH, + {AArch64_LDLARH, + ARM64_INS_LDLARH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDLARW, ARM64_INS_LDLAR, + {AArch64_LDLARW, + ARM64_INS_LDLAR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDLARX, ARM64_INS_LDLAR, + {AArch64_LDLARX, + ARM64_INS_LDLAR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1B_D_IMM_REAL, ARM64_INS_LDNF1B, + {AArch64_LDNF1B_D_IMM_REAL, + ARM64_INS_LDNF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1B_H_IMM_REAL, ARM64_INS_LDNF1B, + {AArch64_LDNF1B_H_IMM_REAL, + ARM64_INS_LDNF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1B_IMM_REAL, ARM64_INS_LDNF1B, + {AArch64_LDNF1B_IMM_REAL, + ARM64_INS_LDNF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1B_S_IMM_REAL, ARM64_INS_LDNF1B, + {AArch64_LDNF1B_S_IMM_REAL, + ARM64_INS_LDNF1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1D_IMM_REAL, ARM64_INS_LDNF1D, + {AArch64_LDNF1D_IMM_REAL, + ARM64_INS_LDNF1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1H_D_IMM_REAL, ARM64_INS_LDNF1H, + {AArch64_LDNF1H_D_IMM_REAL, + ARM64_INS_LDNF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1H_IMM_REAL, ARM64_INS_LDNF1H, + {AArch64_LDNF1H_IMM_REAL, + ARM64_INS_LDNF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1H_S_IMM_REAL, ARM64_INS_LDNF1H, + {AArch64_LDNF1H_S_IMM_REAL, + ARM64_INS_LDNF1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1SB_D_IMM_REAL, ARM64_INS_LDNF1SB, + {AArch64_LDNF1SB_D_IMM_REAL, + ARM64_INS_LDNF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1SB_H_IMM_REAL, ARM64_INS_LDNF1SB, + {AArch64_LDNF1SB_H_IMM_REAL, + ARM64_INS_LDNF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1SB_S_IMM_REAL, ARM64_INS_LDNF1SB, + {AArch64_LDNF1SB_S_IMM_REAL, + ARM64_INS_LDNF1SB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1SH_D_IMM_REAL, ARM64_INS_LDNF1SH, + {AArch64_LDNF1SH_D_IMM_REAL, + ARM64_INS_LDNF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1SH_S_IMM_REAL, ARM64_INS_LDNF1SH, + {AArch64_LDNF1SH_S_IMM_REAL, + ARM64_INS_LDNF1SH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1SW_D_IMM_REAL, ARM64_INS_LDNF1SW, + {AArch64_LDNF1SW_D_IMM_REAL, + ARM64_INS_LDNF1SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1W_D_IMM_REAL, ARM64_INS_LDNF1W, + {AArch64_LDNF1W_D_IMM_REAL, + ARM64_INS_LDNF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNF1W_IMM_REAL, ARM64_INS_LDNF1W, + {AArch64_LDNF1W_IMM_REAL, + ARM64_INS_LDNF1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNPDi, ARM64_INS_LDNP, + {AArch64_LDNPDi, + ARM64_INS_LDNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNPQi, ARM64_INS_LDNP, + {AArch64_LDNPQi, + ARM64_INS_LDNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNPSi, ARM64_INS_LDNP, + {AArch64_LDNPSi, + ARM64_INS_LDNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNPWi, ARM64_INS_LDNP, + {AArch64_LDNPWi, + ARM64_INS_LDNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNPXi, ARM64_INS_LDNP, + {AArch64_LDNPXi, + ARM64_INS_LDNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNT1B_ZRI, ARM64_INS_LDNT1B, + {AArch64_LDNT1B_ZRI, + ARM64_INS_LDNT1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNT1B_ZRR, ARM64_INS_LDNT1B, + {AArch64_LDNT1B_ZRR, + ARM64_INS_LDNT1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNT1D_ZRI, ARM64_INS_LDNT1D, + {AArch64_LDNT1D_ZRI, + ARM64_INS_LDNT1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNT1D_ZRR, ARM64_INS_LDNT1D, + {AArch64_LDNT1D_ZRR, + ARM64_INS_LDNT1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNT1H_ZRI, ARM64_INS_LDNT1H, + {AArch64_LDNT1H_ZRI, + ARM64_INS_LDNT1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNT1H_ZRR, ARM64_INS_LDNT1H, + {AArch64_LDNT1H_ZRR, + ARM64_INS_LDNT1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNT1W_ZRI, ARM64_INS_LDNT1W, + {AArch64_LDNT1W_ZRI, + ARM64_INS_LDNT1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDNT1W_ZRR, ARM64_INS_LDNT1W, + {AArch64_LDNT1W_ZRR, + ARM64_INS_LDNT1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPDi, ARM64_INS_LDP, + {AArch64_LDPDi, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPDpost, ARM64_INS_LDP, + {AArch64_LDPDpost, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPDpre, ARM64_INS_LDP, + {AArch64_LDPDpre, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPQi, ARM64_INS_LDP, + {AArch64_LDPQi, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPQpost, ARM64_INS_LDP, + {AArch64_LDPQpost, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPQpre, ARM64_INS_LDP, + {AArch64_LDPQpre, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPSWi, ARM64_INS_LDPSW, + {AArch64_LDPSWi, + ARM64_INS_LDPSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPSWpost, ARM64_INS_LDPSW, + {AArch64_LDPSWpost, + ARM64_INS_LDPSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPSWpre, ARM64_INS_LDPSW, + {AArch64_LDPSWpre, + ARM64_INS_LDPSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPSi, ARM64_INS_LDP, + {AArch64_LDPSi, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPSpost, ARM64_INS_LDP, + {AArch64_LDPSpost, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPSpre, ARM64_INS_LDP, + {AArch64_LDPSpre, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPWi, ARM64_INS_LDP, + {AArch64_LDPWi, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPWpost, ARM64_INS_LDP, + {AArch64_LDPWpost, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPWpre, ARM64_INS_LDP, + {AArch64_LDPWpre, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPXi, ARM64_INS_LDP, + {AArch64_LDPXi, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPXpost, ARM64_INS_LDP, + {AArch64_LDPXpost, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDPXpre, ARM64_INS_LDP, + {AArch64_LDPXpre, + ARM64_INS_LDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRAAindexed, ARM64_INS_LDRAA, + {AArch64_LDRAAindexed, + ARM64_INS_LDRAA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRAAwriteback, ARM64_INS_LDRAA, + {AArch64_LDRAAwriteback, + ARM64_INS_LDRAA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRABindexed, ARM64_INS_LDRAB, + {AArch64_LDRABindexed, + ARM64_INS_LDRAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRABwriteback, ARM64_INS_LDRAB, + {AArch64_LDRABwriteback, + ARM64_INS_LDRAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBBpost, ARM64_INS_LDRB, + {AArch64_LDRBBpost, + ARM64_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBBpre, ARM64_INS_LDRB, + {AArch64_LDRBBpre, + ARM64_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBBroW, ARM64_INS_LDRB, + {AArch64_LDRBBroW, + ARM64_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBBroX, ARM64_INS_LDRB, + {AArch64_LDRBBroX, + ARM64_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBBui, ARM64_INS_LDRB, + {AArch64_LDRBBui, + ARM64_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBpost, ARM64_INS_LDR, + {AArch64_LDRBpost, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBpre, ARM64_INS_LDR, + {AArch64_LDRBpre, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBroW, ARM64_INS_LDR, + {AArch64_LDRBroW, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBroX, ARM64_INS_LDR, + {AArch64_LDRBroX, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRBui, ARM64_INS_LDR, + {AArch64_LDRBui, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRDl, ARM64_INS_LDR, + {AArch64_LDRDl, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRDpost, ARM64_INS_LDR, + {AArch64_LDRDpost, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRDpre, ARM64_INS_LDR, + {AArch64_LDRDpre, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRDroW, ARM64_INS_LDR, + {AArch64_LDRDroW, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRDroX, ARM64_INS_LDR, + {AArch64_LDRDroX, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRDui, ARM64_INS_LDR, + {AArch64_LDRDui, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHHpost, ARM64_INS_LDRH, + {AArch64_LDRHHpost, + ARM64_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHHpre, ARM64_INS_LDRH, + {AArch64_LDRHHpre, + ARM64_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHHroW, ARM64_INS_LDRH, + {AArch64_LDRHHroW, + ARM64_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHHroX, ARM64_INS_LDRH, + {AArch64_LDRHHroX, + ARM64_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHHui, ARM64_INS_LDRH, + {AArch64_LDRHHui, + ARM64_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHpost, ARM64_INS_LDR, + {AArch64_LDRHpost, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHpre, ARM64_INS_LDR, + {AArch64_LDRHpre, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHroW, ARM64_INS_LDR, + {AArch64_LDRHroW, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHroX, ARM64_INS_LDR, + {AArch64_LDRHroX, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRHui, ARM64_INS_LDR, + {AArch64_LDRHui, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRQl, ARM64_INS_LDR, + {AArch64_LDRQl, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRQpost, ARM64_INS_LDR, + {AArch64_LDRQpost, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRQpre, ARM64_INS_LDR, + {AArch64_LDRQpre, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRQroW, ARM64_INS_LDR, + {AArch64_LDRQroW, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRQroX, ARM64_INS_LDR, + {AArch64_LDRQroX, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRQui, ARM64_INS_LDR, + {AArch64_LDRQui, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBWpost, ARM64_INS_LDRSB, + {AArch64_LDRSBWpost, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBWpre, ARM64_INS_LDRSB, + {AArch64_LDRSBWpre, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBWroW, ARM64_INS_LDRSB, + {AArch64_LDRSBWroW, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBWroX, ARM64_INS_LDRSB, + {AArch64_LDRSBWroX, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBWui, ARM64_INS_LDRSB, + {AArch64_LDRSBWui, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBXpost, ARM64_INS_LDRSB, + {AArch64_LDRSBXpost, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBXpre, ARM64_INS_LDRSB, + {AArch64_LDRSBXpre, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBXroW, ARM64_INS_LDRSB, + {AArch64_LDRSBXroW, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBXroX, ARM64_INS_LDRSB, + {AArch64_LDRSBXroX, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSBXui, ARM64_INS_LDRSB, + {AArch64_LDRSBXui, + ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHWpost, ARM64_INS_LDRSH, + {AArch64_LDRSHWpost, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHWpre, ARM64_INS_LDRSH, + {AArch64_LDRSHWpre, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHWroW, ARM64_INS_LDRSH, + {AArch64_LDRSHWroW, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHWroX, ARM64_INS_LDRSH, + {AArch64_LDRSHWroX, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHWui, ARM64_INS_LDRSH, + {AArch64_LDRSHWui, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHXpost, ARM64_INS_LDRSH, + {AArch64_LDRSHXpost, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHXpre, ARM64_INS_LDRSH, + {AArch64_LDRSHXpre, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHXroW, ARM64_INS_LDRSH, + {AArch64_LDRSHXroW, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHXroX, ARM64_INS_LDRSH, + {AArch64_LDRSHXroX, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSHXui, ARM64_INS_LDRSH, + {AArch64_LDRSHXui, + ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSWl, ARM64_INS_LDRSW, + {AArch64_LDRSWl, + ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSWpost, ARM64_INS_LDRSW, + {AArch64_LDRSWpost, + ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSWpre, ARM64_INS_LDRSW, + {AArch64_LDRSWpre, + ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSWroW, ARM64_INS_LDRSW, + {AArch64_LDRSWroW, + ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSWroX, ARM64_INS_LDRSW, + {AArch64_LDRSWroX, + ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSWui, ARM64_INS_LDRSW, + {AArch64_LDRSWui, + ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSl, ARM64_INS_LDR, + {AArch64_LDRSl, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSpost, ARM64_INS_LDR, + {AArch64_LDRSpost, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSpre, ARM64_INS_LDR, + {AArch64_LDRSpre, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSroW, ARM64_INS_LDR, + {AArch64_LDRSroW, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSroX, ARM64_INS_LDR, + {AArch64_LDRSroX, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRSui, ARM64_INS_LDR, + {AArch64_LDRSui, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRWl, ARM64_INS_LDR, + {AArch64_LDRWl, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRWpost, ARM64_INS_LDR, + {AArch64_LDRWpost, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRWpre, ARM64_INS_LDR, + {AArch64_LDRWpre, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRWroW, ARM64_INS_LDR, + {AArch64_LDRWroW, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRWroX, ARM64_INS_LDR, + {AArch64_LDRWroX, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRWui, ARM64_INS_LDR, + {AArch64_LDRWui, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRXl, ARM64_INS_LDR, + {AArch64_LDRXl, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRXpost, ARM64_INS_LDR, + {AArch64_LDRXpost, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRXpre, ARM64_INS_LDR, + {AArch64_LDRXpre, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRXroW, ARM64_INS_LDR, + {AArch64_LDRXroW, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRXroX, ARM64_INS_LDR, + {AArch64_LDRXroX, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDRXui, ARM64_INS_LDR, + {AArch64_LDRXui, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDR_PXI, ARM64_INS_LDR, + {AArch64_LDR_PXI, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDR_ZXI, ARM64_INS_LDR, + {AArch64_LDR_ZXI, + ARM64_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETAB, ARM64_INS_LDSETAB, + {AArch64_LDSETAB, + ARM64_INS_LDSETAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETAH, ARM64_INS_LDSETAH, + {AArch64_LDSETAH, + ARM64_INS_LDSETAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETALB, ARM64_INS_LDSETALB, + {AArch64_LDSETALB, + ARM64_INS_LDSETALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETALH, ARM64_INS_LDSETALH, + {AArch64_LDSETALH, + ARM64_INS_LDSETALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETALW, ARM64_INS_LDSETAL, + {AArch64_LDSETALW, + ARM64_INS_LDSETAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETALX, ARM64_INS_LDSETAL, + {AArch64_LDSETALX, + ARM64_INS_LDSETAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETAW, ARM64_INS_LDSETA, + {AArch64_LDSETAW, + ARM64_INS_LDSETA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETAX, ARM64_INS_LDSETA, + {AArch64_LDSETAX, + ARM64_INS_LDSETA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETB, ARM64_INS_LDSETB, + {AArch64_LDSETB, + ARM64_INS_LDSETB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETH, ARM64_INS_LDSETH, + {AArch64_LDSETH, + ARM64_INS_LDSETH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETLB, ARM64_INS_LDSETLB, + {AArch64_LDSETLB, + ARM64_INS_LDSETLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETLH, ARM64_INS_LDSETLH, + {AArch64_LDSETLH, + ARM64_INS_LDSETLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETLW, ARM64_INS_LDSETL, + {AArch64_LDSETLW, + ARM64_INS_LDSETL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETLX, ARM64_INS_LDSETL, + {AArch64_LDSETLX, + ARM64_INS_LDSETL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETW, ARM64_INS_LDSET, + {AArch64_LDSETW, + ARM64_INS_LDSET, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSETX, ARM64_INS_LDSET, + {AArch64_LDSETX, + ARM64_INS_LDSET, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXAB, ARM64_INS_LDSMAXAB, + {AArch64_LDSMAXAB, + ARM64_INS_LDSMAXAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXAH, ARM64_INS_LDSMAXAH, + {AArch64_LDSMAXAH, + ARM64_INS_LDSMAXAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXALB, ARM64_INS_LDSMAXALB, + {AArch64_LDSMAXALB, + ARM64_INS_LDSMAXALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXALH, ARM64_INS_LDSMAXALH, + {AArch64_LDSMAXALH, + ARM64_INS_LDSMAXALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXALW, ARM64_INS_LDSMAXAL, + {AArch64_LDSMAXALW, + ARM64_INS_LDSMAXAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXALX, ARM64_INS_LDSMAXAL, + {AArch64_LDSMAXALX, + ARM64_INS_LDSMAXAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXAW, ARM64_INS_LDSMAXA, + {AArch64_LDSMAXAW, + ARM64_INS_LDSMAXA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXAX, ARM64_INS_LDSMAXA, + {AArch64_LDSMAXAX, + ARM64_INS_LDSMAXA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXB, ARM64_INS_LDSMAXB, + {AArch64_LDSMAXB, + ARM64_INS_LDSMAXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXH, ARM64_INS_LDSMAXH, + {AArch64_LDSMAXH, + ARM64_INS_LDSMAXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXLB, ARM64_INS_LDSMAXLB, + {AArch64_LDSMAXLB, + ARM64_INS_LDSMAXLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXLH, ARM64_INS_LDSMAXLH, + {AArch64_LDSMAXLH, + ARM64_INS_LDSMAXLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXLW, ARM64_INS_LDSMAXL, + {AArch64_LDSMAXLW, + ARM64_INS_LDSMAXL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXLX, ARM64_INS_LDSMAXL, + {AArch64_LDSMAXLX, + ARM64_INS_LDSMAXL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXW, ARM64_INS_LDSMAX, + {AArch64_LDSMAXW, + ARM64_INS_LDSMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMAXX, ARM64_INS_LDSMAX, + {AArch64_LDSMAXX, + ARM64_INS_LDSMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINAB, ARM64_INS_LDSMINAB, + {AArch64_LDSMINAB, + ARM64_INS_LDSMINAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINAH, ARM64_INS_LDSMINAH, + {AArch64_LDSMINAH, + ARM64_INS_LDSMINAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINALB, ARM64_INS_LDSMINALB, + {AArch64_LDSMINALB, + ARM64_INS_LDSMINALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINALH, ARM64_INS_LDSMINALH, + {AArch64_LDSMINALH, + ARM64_INS_LDSMINALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINALW, ARM64_INS_LDSMINAL, + {AArch64_LDSMINALW, + ARM64_INS_LDSMINAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINALX, ARM64_INS_LDSMINAL, + {AArch64_LDSMINALX, + ARM64_INS_LDSMINAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINAW, ARM64_INS_LDSMINA, + {AArch64_LDSMINAW, + ARM64_INS_LDSMINA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINAX, ARM64_INS_LDSMINA, + {AArch64_LDSMINAX, + ARM64_INS_LDSMINA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINB, ARM64_INS_LDSMINB, + {AArch64_LDSMINB, + ARM64_INS_LDSMINB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINH, ARM64_INS_LDSMINH, + {AArch64_LDSMINH, + ARM64_INS_LDSMINH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINLB, ARM64_INS_LDSMINLB, + {AArch64_LDSMINLB, + ARM64_INS_LDSMINLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINLH, ARM64_INS_LDSMINLH, + {AArch64_LDSMINLH, + ARM64_INS_LDSMINLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINLW, ARM64_INS_LDSMINL, + {AArch64_LDSMINLW, + ARM64_INS_LDSMINL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINLX, ARM64_INS_LDSMINL, + {AArch64_LDSMINLX, + ARM64_INS_LDSMINL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINW, ARM64_INS_LDSMIN, + {AArch64_LDSMINW, + ARM64_INS_LDSMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDSMINX, ARM64_INS_LDSMIN, + {AArch64_LDSMINX, + ARM64_INS_LDSMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDTRBi, ARM64_INS_LDTRB, + {AArch64_LDTRBi, + ARM64_INS_LDTRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDTRHi, ARM64_INS_LDTRH, + {AArch64_LDTRHi, + ARM64_INS_LDTRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDTRSBWi, ARM64_INS_LDTRSB, + {AArch64_LDTRSBWi, + ARM64_INS_LDTRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDTRSBXi, ARM64_INS_LDTRSB, + {AArch64_LDTRSBXi, + ARM64_INS_LDTRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDTRSHWi, ARM64_INS_LDTRSH, + {AArch64_LDTRSHWi, + ARM64_INS_LDTRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDTRSHXi, ARM64_INS_LDTRSH, + {AArch64_LDTRSHXi, + ARM64_INS_LDTRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDTRSWi, ARM64_INS_LDTRSW, + {AArch64_LDTRSWi, + ARM64_INS_LDTRSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDTRWi, ARM64_INS_LDTR, + {AArch64_LDTRWi, + ARM64_INS_LDTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDTRXi, ARM64_INS_LDTR, + {AArch64_LDTRXi, + ARM64_INS_LDTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXAB, ARM64_INS_LDUMAXAB, + {AArch64_LDUMAXAB, + ARM64_INS_LDUMAXAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXAH, ARM64_INS_LDUMAXAH, + {AArch64_LDUMAXAH, + ARM64_INS_LDUMAXAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXALB, ARM64_INS_LDUMAXALB, + {AArch64_LDUMAXALB, + ARM64_INS_LDUMAXALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXALH, ARM64_INS_LDUMAXALH, + {AArch64_LDUMAXALH, + ARM64_INS_LDUMAXALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXALW, ARM64_INS_LDUMAXAL, + {AArch64_LDUMAXALW, + ARM64_INS_LDUMAXAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXALX, ARM64_INS_LDUMAXAL, + {AArch64_LDUMAXALX, + ARM64_INS_LDUMAXAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXAW, ARM64_INS_LDUMAXA, + {AArch64_LDUMAXAW, + ARM64_INS_LDUMAXA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXAX, ARM64_INS_LDUMAXA, + {AArch64_LDUMAXAX, + ARM64_INS_LDUMAXA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXB, ARM64_INS_LDUMAXB, + {AArch64_LDUMAXB, + ARM64_INS_LDUMAXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXH, ARM64_INS_LDUMAXH, + {AArch64_LDUMAXH, + ARM64_INS_LDUMAXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXLB, ARM64_INS_LDUMAXLB, + {AArch64_LDUMAXLB, + ARM64_INS_LDUMAXLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXLH, ARM64_INS_LDUMAXLH, + {AArch64_LDUMAXLH, + ARM64_INS_LDUMAXLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXLW, ARM64_INS_LDUMAXL, + {AArch64_LDUMAXLW, + ARM64_INS_LDUMAXL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXLX, ARM64_INS_LDUMAXL, + {AArch64_LDUMAXLX, + ARM64_INS_LDUMAXL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXW, ARM64_INS_LDUMAX, + {AArch64_LDUMAXW, + ARM64_INS_LDUMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMAXX, ARM64_INS_LDUMAX, + {AArch64_LDUMAXX, + ARM64_INS_LDUMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINAB, ARM64_INS_LDUMINAB, + {AArch64_LDUMINAB, + ARM64_INS_LDUMINAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINAH, ARM64_INS_LDUMINAH, + {AArch64_LDUMINAH, + ARM64_INS_LDUMINAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINALB, ARM64_INS_LDUMINALB, + {AArch64_LDUMINALB, + ARM64_INS_LDUMINALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINALH, ARM64_INS_LDUMINALH, + {AArch64_LDUMINALH, + ARM64_INS_LDUMINALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINALW, ARM64_INS_LDUMINAL, + {AArch64_LDUMINALW, + ARM64_INS_LDUMINAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINALX, ARM64_INS_LDUMINAL, + {AArch64_LDUMINALX, + ARM64_INS_LDUMINAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINAW, ARM64_INS_LDUMINA, + {AArch64_LDUMINAW, + ARM64_INS_LDUMINA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINAX, ARM64_INS_LDUMINA, + {AArch64_LDUMINAX, + ARM64_INS_LDUMINA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINB, ARM64_INS_LDUMINB, + {AArch64_LDUMINB, + ARM64_INS_LDUMINB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINH, ARM64_INS_LDUMINH, + {AArch64_LDUMINH, + ARM64_INS_LDUMINH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINLB, ARM64_INS_LDUMINLB, + {AArch64_LDUMINLB, + ARM64_INS_LDUMINLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINLH, ARM64_INS_LDUMINLH, + {AArch64_LDUMINLH, + ARM64_INS_LDUMINLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINLW, ARM64_INS_LDUMINL, + {AArch64_LDUMINLW, + ARM64_INS_LDUMINL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINLX, ARM64_INS_LDUMINL, + {AArch64_LDUMINLX, + ARM64_INS_LDUMINL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINW, ARM64_INS_LDUMIN, + {AArch64_LDUMINW, + ARM64_INS_LDUMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDUMINX, ARM64_INS_LDUMIN, + {AArch64_LDUMINX, + ARM64_INS_LDUMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURBBi, ARM64_INS_LDURB, + {AArch64_LDURBBi, + ARM64_INS_LDURB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURBi, ARM64_INS_LDURB, + {AArch64_LDURBi, + ARM64_INS_LDURB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURDi, ARM64_INS_LDUR, + {AArch64_LDURDi, + ARM64_INS_LDUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURHHi, ARM64_INS_LDRH, + {AArch64_LDURHHi, + ARM64_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURHi, ARM64_INS_LDUR, + {AArch64_LDURHi, + ARM64_INS_LDUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURQi, ARM64_INS_LDUR, + {AArch64_LDURQi, + ARM64_INS_LDUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURSBWi, ARM64_INS_LDURSB, + {AArch64_LDURSBWi, + ARM64_INS_LDURSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURSBXi, ARM64_INS_LDURSB, + {AArch64_LDURSBXi, + ARM64_INS_LDURSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURSHWi, ARM64_INS_LDURSH, + {AArch64_LDURSHWi, + ARM64_INS_LDURSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURSHXi, ARM64_INS_LDURSH, + {AArch64_LDURSHXi, + ARM64_INS_LDURSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURSWi, ARM64_INS_LDURSW, + {AArch64_LDURSWi, + ARM64_INS_LDURSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURSi, ARM64_INS_LDUR, + {AArch64_LDURSi, + ARM64_INS_LDUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURWi, ARM64_INS_LDUR, + {AArch64_LDURWi, + ARM64_INS_LDUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDURXi, ARM64_INS_LDUR, + {AArch64_LDURXi, + ARM64_INS_LDUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDXPW, ARM64_INS_LDXP, + {AArch64_LDXPW, + ARM64_INS_LDXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDXPX, ARM64_INS_LDXP, + {AArch64_LDXPX, + ARM64_INS_LDXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDXRB, ARM64_INS_LDXRB, + {AArch64_LDXRB, + ARM64_INS_LDXRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDXRH, ARM64_INS_LDXRH, + {AArch64_LDXRH, + ARM64_INS_LDXRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDXRW, ARM64_INS_LDXR, + {AArch64_LDXRW, + ARM64_INS_LDXR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LDXRX, ARM64_INS_LDXR, + {AArch64_LDXRX, + ARM64_INS_LDXR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSLR_ZPmZ_B, ARM64_INS_LSLR, + {AArch64_LSLR_ZPmZ_B, + ARM64_INS_LSLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSLR_ZPmZ_D, ARM64_INS_LSLR, + {AArch64_LSLR_ZPmZ_D, + ARM64_INS_LSLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSLR_ZPmZ_H, ARM64_INS_LSLR, + {AArch64_LSLR_ZPmZ_H, + ARM64_INS_LSLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSLR_ZPmZ_S, ARM64_INS_LSLR, + {AArch64_LSLR_ZPmZ_S, + ARM64_INS_LSLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSLVWr, ARM64_INS_LSL, + {AArch64_LSLVWr, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSLVXr, ARM64_INS_LSL, + {AArch64_LSLVXr, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_WIDE_ZPmZ_B, ARM64_INS_LSL, + {AArch64_LSL_WIDE_ZPmZ_B, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_WIDE_ZPmZ_H, ARM64_INS_LSL, + {AArch64_LSL_WIDE_ZPmZ_H, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_WIDE_ZPmZ_S, ARM64_INS_LSL, + {AArch64_LSL_WIDE_ZPmZ_S, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_WIDE_ZZZ_B, ARM64_INS_LSL, + {AArch64_LSL_WIDE_ZZZ_B, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_WIDE_ZZZ_H, ARM64_INS_LSL, + {AArch64_LSL_WIDE_ZZZ_H, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_WIDE_ZZZ_S, ARM64_INS_LSL, + {AArch64_LSL_WIDE_ZZZ_S, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZPmI_B, ARM64_INS_LSL, + {AArch64_LSL_ZPmI_B, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZPmI_D, ARM64_INS_LSL, + {AArch64_LSL_ZPmI_D, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZPmI_H, ARM64_INS_LSL, + {AArch64_LSL_ZPmI_H, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZPmI_S, ARM64_INS_LSL, + {AArch64_LSL_ZPmI_S, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZPmZ_B, ARM64_INS_LSL, + {AArch64_LSL_ZPmZ_B, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZPmZ_D, ARM64_INS_LSL, + {AArch64_LSL_ZPmZ_D, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZPmZ_H, ARM64_INS_LSL, + {AArch64_LSL_ZPmZ_H, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZPmZ_S, ARM64_INS_LSL, + {AArch64_LSL_ZPmZ_S, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZZI_B, ARM64_INS_LSL, + {AArch64_LSL_ZZI_B, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZZI_D, ARM64_INS_LSL, + {AArch64_LSL_ZZI_D, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZZI_H, ARM64_INS_LSL, + {AArch64_LSL_ZZI_H, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSL_ZZI_S, ARM64_INS_LSL, + {AArch64_LSL_ZZI_S, + ARM64_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSRR_ZPmZ_B, ARM64_INS_LSRR, + {AArch64_LSRR_ZPmZ_B, + ARM64_INS_LSRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSRR_ZPmZ_D, ARM64_INS_LSRR, + {AArch64_LSRR_ZPmZ_D, + ARM64_INS_LSRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSRR_ZPmZ_H, ARM64_INS_LSRR, + {AArch64_LSRR_ZPmZ_H, + ARM64_INS_LSRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSRR_ZPmZ_S, ARM64_INS_LSRR, + {AArch64_LSRR_ZPmZ_S, + ARM64_INS_LSRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSRVWr, ARM64_INS_LSR, + {AArch64_LSRVWr, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSRVXr, ARM64_INS_LSR, + {AArch64_LSRVXr, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_WIDE_ZPmZ_B, ARM64_INS_LSR, + {AArch64_LSR_WIDE_ZPmZ_B, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_WIDE_ZPmZ_H, ARM64_INS_LSR, + {AArch64_LSR_WIDE_ZPmZ_H, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_WIDE_ZPmZ_S, ARM64_INS_LSR, + {AArch64_LSR_WIDE_ZPmZ_S, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_WIDE_ZZZ_B, ARM64_INS_LSR, + {AArch64_LSR_WIDE_ZZZ_B, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_WIDE_ZZZ_H, ARM64_INS_LSR, + {AArch64_LSR_WIDE_ZZZ_H, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_WIDE_ZZZ_S, ARM64_INS_LSR, + {AArch64_LSR_WIDE_ZZZ_S, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZPmI_B, ARM64_INS_LSR, + {AArch64_LSR_ZPmI_B, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZPmI_D, ARM64_INS_LSR, + {AArch64_LSR_ZPmI_D, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZPmI_H, ARM64_INS_LSR, + {AArch64_LSR_ZPmI_H, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZPmI_S, ARM64_INS_LSR, + {AArch64_LSR_ZPmI_S, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZPmZ_B, ARM64_INS_LSR, + {AArch64_LSR_ZPmZ_B, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZPmZ_D, ARM64_INS_LSR, + {AArch64_LSR_ZPmZ_D, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZPmZ_H, ARM64_INS_LSR, + {AArch64_LSR_ZPmZ_H, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZPmZ_S, ARM64_INS_LSR, + {AArch64_LSR_ZPmZ_S, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZZI_B, ARM64_INS_LSR, + {AArch64_LSR_ZZI_B, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZZI_D, ARM64_INS_LSR, + {AArch64_LSR_ZZI_D, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZZI_H, ARM64_INS_LSR, + {AArch64_LSR_ZZI_H, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_LSR_ZZI_S, ARM64_INS_LSR, + {AArch64_LSR_ZZI_S, + ARM64_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MADDWrrr, ARM64_INS_MADD, + {AArch64_MADDWrrr, + ARM64_INS_MADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MADDXrrr, ARM64_INS_MADD, + {AArch64_MADDXrrr, + ARM64_INS_MADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MAD_ZPmZZ_B, ARM64_INS_MAD, + {AArch64_MAD_ZPmZZ_B, + ARM64_INS_MAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MAD_ZPmZZ_D, ARM64_INS_MAD, + {AArch64_MAD_ZPmZZ_D, + ARM64_INS_MAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MAD_ZPmZZ_H, ARM64_INS_MAD, + {AArch64_MAD_ZPmZZ_H, + ARM64_INS_MAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MAD_ZPmZZ_S, ARM64_INS_MAD, + {AArch64_MAD_ZPmZZ_S, + ARM64_INS_MAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLA_ZPmZZ_B, ARM64_INS_MLA, + {AArch64_MLA_ZPmZZ_B, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLA_ZPmZZ_D, ARM64_INS_MLA, + {AArch64_MLA_ZPmZZ_D, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLA_ZPmZZ_H, ARM64_INS_MLA, + {AArch64_MLA_ZPmZZ_H, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLA_ZPmZZ_S, ARM64_INS_MLA, + {AArch64_MLA_ZPmZZ_S, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv16i8, ARM64_INS_MLA, + {AArch64_MLAv16i8, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv2i32, ARM64_INS_MLA, + {AArch64_MLAv2i32, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv2i32_indexed, ARM64_INS_MLA, + {AArch64_MLAv2i32_indexed, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv4i16, ARM64_INS_MLA, + {AArch64_MLAv4i16, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv4i16_indexed, ARM64_INS_MLA, + {AArch64_MLAv4i16_indexed, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv4i32, ARM64_INS_MLA, + {AArch64_MLAv4i32, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv4i32_indexed, ARM64_INS_MLA, + {AArch64_MLAv4i32_indexed, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv8i16, ARM64_INS_MLA, + {AArch64_MLAv8i16, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv8i16_indexed, ARM64_INS_MLA, + {AArch64_MLAv8i16_indexed, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLAv8i8, ARM64_INS_MLA, + {AArch64_MLAv8i8, + ARM64_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLS_ZPmZZ_B, ARM64_INS_MLS, + {AArch64_MLS_ZPmZZ_B, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLS_ZPmZZ_D, ARM64_INS_MLS, + {AArch64_MLS_ZPmZZ_D, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLS_ZPmZZ_H, ARM64_INS_MLS, + {AArch64_MLS_ZPmZZ_H, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLS_ZPmZZ_S, ARM64_INS_MLS, + {AArch64_MLS_ZPmZZ_S, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv16i8, ARM64_INS_MLS, + {AArch64_MLSv16i8, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv2i32, ARM64_INS_MLS, + {AArch64_MLSv2i32, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv2i32_indexed, ARM64_INS_MLS, + {AArch64_MLSv2i32_indexed, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv4i16, ARM64_INS_MLS, + {AArch64_MLSv4i16, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv4i16_indexed, ARM64_INS_MLS, + {AArch64_MLSv4i16_indexed, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv4i32, ARM64_INS_MLS, + {AArch64_MLSv4i32, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv4i32_indexed, ARM64_INS_MLS, + {AArch64_MLSv4i32_indexed, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv8i16, ARM64_INS_MLS, + {AArch64_MLSv8i16, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv8i16_indexed, ARM64_INS_MLS, + {AArch64_MLSv8i16_indexed, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MLSv8i8, ARM64_INS_MLS, + {AArch64_MLSv8i8, + ARM64_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVID, ARM64_INS_MOVI, + {AArch64_MOVID, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVIv16b_ns, ARM64_INS_MOVI, + {AArch64_MOVIv16b_ns, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVIv2d_ns, ARM64_INS_MOVI, + {AArch64_MOVIv2d_ns, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVIv2i32, ARM64_INS_MOVI, + {AArch64_MOVIv2i32, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVIv2s_msl, ARM64_INS_MOVI, + {AArch64_MOVIv2s_msl, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVIv4i16, ARM64_INS_MOVI, + {AArch64_MOVIv4i16, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVIv4i32, ARM64_INS_MOVI, + {AArch64_MOVIv4i32, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVIv4s_msl, ARM64_INS_MOVI, + {AArch64_MOVIv4s_msl, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVIv8b_ns, ARM64_INS_MOVI, + {AArch64_MOVIv8b_ns, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVIv8i16, ARM64_INS_MOVI, + {AArch64_MOVIv8i16, + ARM64_INS_MOVI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVKWi, ARM64_INS_MOVK, + {AArch64_MOVKWi, + ARM64_INS_MOVK, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVKXi, ARM64_INS_MOVK, + {AArch64_MOVKXi, + ARM64_INS_MOVK, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVNWi, ARM64_INS_MOV, + {AArch64_MOVNWi, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVNXi, ARM64_INS_MOV, + {AArch64_MOVNXi, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVPRFX_ZPmZ_B, ARM64_INS_MOVPRFX, + {AArch64_MOVPRFX_ZPmZ_B, + ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVPRFX_ZPmZ_D, ARM64_INS_MOVPRFX, + {AArch64_MOVPRFX_ZPmZ_D, + ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVPRFX_ZPmZ_H, ARM64_INS_MOVPRFX, + {AArch64_MOVPRFX_ZPmZ_H, + ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVPRFX_ZPmZ_S, ARM64_INS_MOVPRFX, + {AArch64_MOVPRFX_ZPmZ_S, + ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVPRFX_ZPzZ_B, ARM64_INS_MOVPRFX, + {AArch64_MOVPRFX_ZPzZ_B, + ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVPRFX_ZPzZ_D, ARM64_INS_MOVPRFX, + {AArch64_MOVPRFX_ZPzZ_D, + ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVPRFX_ZPzZ_H, ARM64_INS_MOVPRFX, + {AArch64_MOVPRFX_ZPzZ_H, + ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVPRFX_ZPzZ_S, ARM64_INS_MOVPRFX, + {AArch64_MOVPRFX_ZPzZ_S, + ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVPRFX_ZZ, ARM64_INS_MOVPRFX, + {AArch64_MOVPRFX_ZZ, + ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVZWi, ARM64_INS_MOV, + {AArch64_MOVZWi, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MOVZXi, ARM64_INS_MOV, + {AArch64_MOVZXi, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MRS, ARM64_INS_MRS, + {AArch64_MRS, + ARM64_INS_MRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PRIVILEGE, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MSB_ZPmZZ_B, ARM64_INS_MSB, + {AArch64_MSB_ZPmZZ_B, + ARM64_INS_MSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MSB_ZPmZZ_D, ARM64_INS_MSB, + {AArch64_MSB_ZPmZZ_D, + ARM64_INS_MSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MSB_ZPmZZ_H, ARM64_INS_MSB, + {AArch64_MSB_ZPmZZ_H, + ARM64_INS_MSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MSB_ZPmZZ_S, ARM64_INS_MSB, + {AArch64_MSB_ZPmZZ_S, + ARM64_INS_MSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MSR, ARM64_INS_MSR, + {AArch64_MSR, + ARM64_INS_MSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PRIVILEGE, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MSRpstateImm1, ARM64_INS_MSR, + {AArch64_MSRpstateImm1, + ARM64_INS_MSR, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_PRIVILEGE, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MSRpstateImm4, ARM64_INS_MSR, + {AArch64_MSRpstateImm4, + ARM64_INS_MSR, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {ARM64_GRP_PRIVILEGE, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MSUBWrrr, ARM64_INS_MSUB, + {AArch64_MSUBWrrr, + ARM64_INS_MSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MSUBXrrr, ARM64_INS_MSUB, + {AArch64_MSUBXrrr, + ARM64_INS_MSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MUL_ZI_B, ARM64_INS_MUL, + {AArch64_MUL_ZI_B, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MUL_ZI_D, ARM64_INS_MUL, + {AArch64_MUL_ZI_D, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MUL_ZI_H, ARM64_INS_MUL, + {AArch64_MUL_ZI_H, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MUL_ZI_S, ARM64_INS_MUL, + {AArch64_MUL_ZI_S, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MUL_ZPmZ_B, ARM64_INS_MUL, + {AArch64_MUL_ZPmZ_B, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MUL_ZPmZ_D, ARM64_INS_MUL, + {AArch64_MUL_ZPmZ_D, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MUL_ZPmZ_H, ARM64_INS_MUL, + {AArch64_MUL_ZPmZ_H, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MUL_ZPmZ_S, ARM64_INS_MUL, + {AArch64_MUL_ZPmZ_S, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv16i8, ARM64_INS_MUL, + {AArch64_MULv16i8, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv2i32, ARM64_INS_MUL, + {AArch64_MULv2i32, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv2i32_indexed, ARM64_INS_MUL, + {AArch64_MULv2i32_indexed, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv4i16, ARM64_INS_MUL, + {AArch64_MULv4i16, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv4i16_indexed, ARM64_INS_MUL, + {AArch64_MULv4i16_indexed, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv4i32, ARM64_INS_MUL, + {AArch64_MULv4i32, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv4i32_indexed, ARM64_INS_MUL, + {AArch64_MULv4i32_indexed, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv8i16, ARM64_INS_MUL, + {AArch64_MULv8i16, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv8i16_indexed, ARM64_INS_MUL, + {AArch64_MULv8i16_indexed, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MULv8i8, ARM64_INS_MUL, + {AArch64_MULv8i8, + ARM64_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MVNIv2i32, ARM64_INS_MVNI, + {AArch64_MVNIv2i32, + ARM64_INS_MVNI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MVNIv2s_msl, ARM64_INS_MVNI, + {AArch64_MVNIv2s_msl, + ARM64_INS_MVNI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MVNIv4i16, ARM64_INS_MVNI, + {AArch64_MVNIv4i16, + ARM64_INS_MVNI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MVNIv4i32, ARM64_INS_MVNI, + {AArch64_MVNIv4i32, + ARM64_INS_MVNI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MVNIv4s_msl, ARM64_INS_MVNI, + {AArch64_MVNIv4s_msl, + ARM64_INS_MVNI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_MVNIv8i16, ARM64_INS_MVNI, + {AArch64_MVNIv8i16, + ARM64_INS_MVNI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NANDS_PPzPP, ARM64_INS_NANDS, + {AArch64_NANDS_PPzPP, + ARM64_INS_NANDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NAND_PPzPP, ARM64_INS_NAND, + {AArch64_NAND_PPzPP, + ARM64_INS_NAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEG_ZPmZ_B, ARM64_INS_NEG, + {AArch64_NEG_ZPmZ_B, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEG_ZPmZ_D, ARM64_INS_NEG, + {AArch64_NEG_ZPmZ_D, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEG_ZPmZ_H, ARM64_INS_NEG, + {AArch64_NEG_ZPmZ_H, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEG_ZPmZ_S, ARM64_INS_NEG, + {AArch64_NEG_ZPmZ_S, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEGv16i8, ARM64_INS_NEG, + {AArch64_NEGv16i8, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEGv1i64, ARM64_INS_NEG, + {AArch64_NEGv1i64, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEGv2i32, ARM64_INS_NEG, + {AArch64_NEGv2i32, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEGv2i64, ARM64_INS_NEG, + {AArch64_NEGv2i64, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEGv4i16, ARM64_INS_NEG, + {AArch64_NEGv4i16, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEGv4i32, ARM64_INS_NEG, + {AArch64_NEGv4i32, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEGv8i16, ARM64_INS_NEG, + {AArch64_NEGv8i16, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NEGv8i8, ARM64_INS_NEG, + {AArch64_NEGv8i8, + ARM64_INS_NEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NORS_PPzPP, ARM64_INS_NORS, + {AArch64_NORS_PPzPP, + ARM64_INS_NORS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NOR_PPzPP, ARM64_INS_NOR, + {AArch64_NOR_PPzPP, + ARM64_INS_NOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NOT_ZPmZ_B, ARM64_INS_NOT, + {AArch64_NOT_ZPmZ_B, + ARM64_INS_NOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NOT_ZPmZ_D, ARM64_INS_NOT, + {AArch64_NOT_ZPmZ_D, + ARM64_INS_NOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NOT_ZPmZ_H, ARM64_INS_NOT, + {AArch64_NOT_ZPmZ_H, + ARM64_INS_NOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NOT_ZPmZ_S, ARM64_INS_NOT, + {AArch64_NOT_ZPmZ_S, + ARM64_INS_NOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NOTv16i8, ARM64_INS_NOT, + {AArch64_NOTv16i8, + ARM64_INS_NOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_NOTv8i8, ARM64_INS_NOT, + {AArch64_NOTv8i8, + ARM64_INS_NOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORNS_PPzPP, ARM64_INS_ORNS, + {AArch64_ORNS_PPzPP, + ARM64_INS_ORNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORNWrs, ARM64_INS_ORN, + {AArch64_ORNWrs, + ARM64_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORNXrs, ARM64_INS_ORN, + {AArch64_ORNXrs, + ARM64_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORN_PPzPP, ARM64_INS_ORN, + {AArch64_ORN_PPzPP, + ARM64_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORNv16i8, ARM64_INS_ORN, + {AArch64_ORNv16i8, + ARM64_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORNv8i8, ARM64_INS_ORN, + {AArch64_ORNv8i8, + ARM64_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRS_PPzPP, ARM64_INS_ORRS, + {AArch64_ORRS_PPzPP, + ARM64_INS_ORRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRWri, ARM64_INS_ORR, + {AArch64_ORRWri, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRWrs, ARM64_INS_ORR, + {AArch64_ORRWrs, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRXri, ARM64_INS_ORR, + {AArch64_ORRXri, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRXrs, ARM64_INS_ORR, + {AArch64_ORRXrs, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORR_PPzPP, ARM64_INS_ORR, + {AArch64_ORR_PPzPP, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORR_ZI, ARM64_INS_ORR, + {AArch64_ORR_ZI, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORR_ZPmZ_B, ARM64_INS_ORR, + {AArch64_ORR_ZPmZ_B, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORR_ZPmZ_D, ARM64_INS_ORR, + {AArch64_ORR_ZPmZ_D, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORR_ZPmZ_H, ARM64_INS_ORR, + {AArch64_ORR_ZPmZ_H, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORR_ZPmZ_S, ARM64_INS_ORR, + {AArch64_ORR_ZPmZ_S, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORR_ZZZ, ARM64_INS_ORR, + {AArch64_ORR_ZZZ, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRv16i8, ARM64_INS_ORR, + {AArch64_ORRv16i8, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRv2i32, ARM64_INS_ORR, + {AArch64_ORRv2i32, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRv4i16, ARM64_INS_ORR, + {AArch64_ORRv4i16, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRv4i32, ARM64_INS_ORR, + {AArch64_ORRv4i32, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRv8i16, ARM64_INS_ORR, + {AArch64_ORRv8i16, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORRv8i8, ARM64_INS_ORR, + {AArch64_ORRv8i8, + ARM64_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORV_VPZ_B, ARM64_INS_ORV, + {AArch64_ORV_VPZ_B, + ARM64_INS_ORV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORV_VPZ_D, ARM64_INS_ORV, + {AArch64_ORV_VPZ_D, + ARM64_INS_ORV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORV_VPZ_H, ARM64_INS_ORV, + {AArch64_ORV_VPZ_H, + ARM64_INS_ORV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ORV_VPZ_S, ARM64_INS_ORV, + {AArch64_ORV_VPZ_S, + ARM64_INS_ORV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACDA, ARM64_INS_PACDA, + {AArch64_PACDA, + ARM64_INS_PACDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACDB, ARM64_INS_PACDB, + {AArch64_PACDB, + ARM64_INS_PACDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACDZA, ARM64_INS_PACDZA, + {AArch64_PACDZA, + ARM64_INS_PACDZA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACDZB, ARM64_INS_PACDZB, + {AArch64_PACDZB, + ARM64_INS_PACDZB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACGA, ARM64_INS_PACGA, + {AArch64_PACGA, + ARM64_INS_PACGA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIA, ARM64_INS_PACIA, + {AArch64_PACIA, + ARM64_INS_PACIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIA1716, ARM64_INS_PACIA1716, + {AArch64_PACIA1716, + ARM64_INS_PACIA1716, #ifndef CAPSTONE_DIET - { ARM64_REG_X17, 0 }, { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_X17, 0}, + {ARM64_REG_X16, ARM64_REG_X17, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIASP, ARM64_INS_PACIASP, + {AArch64_PACIASP, + ARM64_INS_PACIASP, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, 0 }, { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, 0}, + {ARM64_REG_LR, ARM64_REG_SP, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIAZ, ARM64_INS_PACIAZ, + {AArch64_PACIAZ, + ARM64_INS_PACIAZ, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, 0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIB, ARM64_INS_PACIB, + {AArch64_PACIB, + ARM64_INS_PACIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIB1716, ARM64_INS_PACIB1716, + {AArch64_PACIB1716, + ARM64_INS_PACIB1716, #ifndef CAPSTONE_DIET - { ARM64_REG_X17, 0 }, { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_X17, 0}, + {ARM64_REG_X16, ARM64_REG_X17, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIBSP, ARM64_INS_PACIBSP, + {AArch64_PACIBSP, + ARM64_INS_PACIBSP, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, 0 }, { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, 0}, + {ARM64_REG_LR, ARM64_REG_SP, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIBZ, ARM64_INS_PACIBZ, + {AArch64_PACIBZ, + ARM64_INS_PACIBZ, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {ARM64_REG_LR, 0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIZA, ARM64_INS_PACIZA, + {AArch64_PACIZA, + ARM64_INS_PACIZA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PACIZB, ARM64_INS_PACIZB, + {AArch64_PACIZB, + ARM64_INS_PACIZB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PFALSE, ARM64_INS_PFALSE, + {AArch64_PFALSE, + ARM64_INS_PFALSE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PMULLv16i8, ARM64_INS_PMULL2, + {AArch64_PMULLv16i8, + ARM64_INS_PMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PMULLv1i64, ARM64_INS_PMULL, + {AArch64_PMULLv1i64, + ARM64_INS_PMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PMULLv2i64, ARM64_INS_PMULL2, + {AArch64_PMULLv2i64, + ARM64_INS_PMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PMULLv8i8, ARM64_INS_PMULL, + {AArch64_PMULLv8i8, + ARM64_INS_PMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PMULv16i8, ARM64_INS_PMUL, + {AArch64_PMULv16i8, + ARM64_INS_PMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PMULv8i8, ARM64_INS_PMUL, + {AArch64_PMULv8i8, + ARM64_INS_PMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PNEXT_B, ARM64_INS_PNEXT, + {AArch64_PNEXT_B, + ARM64_INS_PNEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PNEXT_D, ARM64_INS_PNEXT, + {AArch64_PNEXT_D, + ARM64_INS_PNEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PNEXT_H, ARM64_INS_PNEXT, + {AArch64_PNEXT_H, + ARM64_INS_PNEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PNEXT_S, ARM64_INS_PNEXT, + {AArch64_PNEXT_S, + ARM64_INS_PNEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFB_D_PZI, ARM64_INS_PRFB, + {AArch64_PRFB_D_PZI, + ARM64_INS_PRFB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFB_D_SCALED, ARM64_INS_PRFB, + {AArch64_PRFB_D_SCALED, + ARM64_INS_PRFB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFB_D_SXTW_SCALED, ARM64_INS_PRFB, + {AArch64_PRFB_D_SXTW_SCALED, + ARM64_INS_PRFB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFB_D_UXTW_SCALED, ARM64_INS_PRFB, + {AArch64_PRFB_D_UXTW_SCALED, + ARM64_INS_PRFB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFB_PRI, ARM64_INS_PRFB, + {AArch64_PRFB_PRI, + ARM64_INS_PRFB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFB_PRR, ARM64_INS_PRFB, + {AArch64_PRFB_PRR, + ARM64_INS_PRFB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFB_S_PZI, ARM64_INS_PRFB, + {AArch64_PRFB_S_PZI, + ARM64_INS_PRFB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFB_S_SXTW_SCALED, ARM64_INS_PRFB, + {AArch64_PRFB_S_SXTW_SCALED, + ARM64_INS_PRFB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFB_S_UXTW_SCALED, ARM64_INS_PRFB, + {AArch64_PRFB_S_UXTW_SCALED, + ARM64_INS_PRFB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFD_D_PZI, ARM64_INS_PRFD, + {AArch64_PRFD_D_PZI, + ARM64_INS_PRFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFD_D_SCALED, ARM64_INS_PRFD, + {AArch64_PRFD_D_SCALED, + ARM64_INS_PRFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFD_D_SXTW_SCALED, ARM64_INS_PRFD, + {AArch64_PRFD_D_SXTW_SCALED, + ARM64_INS_PRFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFD_D_UXTW_SCALED, ARM64_INS_PRFD, + {AArch64_PRFD_D_UXTW_SCALED, + ARM64_INS_PRFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFD_PRI, ARM64_INS_PRFD, + {AArch64_PRFD_PRI, + ARM64_INS_PRFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFD_PRR, ARM64_INS_PRFD, + {AArch64_PRFD_PRR, + ARM64_INS_PRFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFD_S_PZI, ARM64_INS_PRFD, + {AArch64_PRFD_S_PZI, + ARM64_INS_PRFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFD_S_SXTW_SCALED, ARM64_INS_PRFD, + {AArch64_PRFD_S_SXTW_SCALED, + ARM64_INS_PRFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFD_S_UXTW_SCALED, ARM64_INS_PRFD, + {AArch64_PRFD_S_UXTW_SCALED, + ARM64_INS_PRFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFH_D_PZI, ARM64_INS_PRFH, + {AArch64_PRFH_D_PZI, + ARM64_INS_PRFH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFH_D_SCALED, ARM64_INS_PRFH, + {AArch64_PRFH_D_SCALED, + ARM64_INS_PRFH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFH_D_SXTW_SCALED, ARM64_INS_PRFH, + {AArch64_PRFH_D_SXTW_SCALED, + ARM64_INS_PRFH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFH_D_UXTW_SCALED, ARM64_INS_PRFH, + {AArch64_PRFH_D_UXTW_SCALED, + ARM64_INS_PRFH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFH_PRI, ARM64_INS_PRFH, + {AArch64_PRFH_PRI, + ARM64_INS_PRFH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFH_PRR, ARM64_INS_PRFH, + {AArch64_PRFH_PRR, + ARM64_INS_PRFH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFH_S_PZI, ARM64_INS_PRFH, + {AArch64_PRFH_S_PZI, + ARM64_INS_PRFH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFH_S_SXTW_SCALED, ARM64_INS_PRFH, + {AArch64_PRFH_S_SXTW_SCALED, + ARM64_INS_PRFH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFH_S_UXTW_SCALED, ARM64_INS_PRFH, + {AArch64_PRFH_S_UXTW_SCALED, + ARM64_INS_PRFH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFMl, ARM64_INS_PRFM, + {AArch64_PRFMl, + ARM64_INS_PRFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFMroW, ARM64_INS_PRFM, + {AArch64_PRFMroW, + ARM64_INS_PRFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFMroX, ARM64_INS_PRFM, + {AArch64_PRFMroX, + ARM64_INS_PRFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFMui, ARM64_INS_PRFM, + {AArch64_PRFMui, + ARM64_INS_PRFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFS_PRR, ARM64_INS_PRFW, + {AArch64_PRFS_PRR, + ARM64_INS_PRFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFUMi, ARM64_INS_PRFUM, + {AArch64_PRFUMi, + ARM64_INS_PRFUM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFW_D_PZI, ARM64_INS_PRFW, + {AArch64_PRFW_D_PZI, + ARM64_INS_PRFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFW_D_SCALED, ARM64_INS_PRFW, + {AArch64_PRFW_D_SCALED, + ARM64_INS_PRFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFW_D_SXTW_SCALED, ARM64_INS_PRFW, + {AArch64_PRFW_D_SXTW_SCALED, + ARM64_INS_PRFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFW_D_UXTW_SCALED, ARM64_INS_PRFW, + {AArch64_PRFW_D_UXTW_SCALED, + ARM64_INS_PRFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFW_PRI, ARM64_INS_PRFW, + {AArch64_PRFW_PRI, + ARM64_INS_PRFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFW_S_PZI, ARM64_INS_PRFW, + {AArch64_PRFW_S_PZI, + ARM64_INS_PRFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFW_S_SXTW_SCALED, ARM64_INS_PRFW, + {AArch64_PRFW_S_SXTW_SCALED, + ARM64_INS_PRFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PRFW_S_UXTW_SCALED, ARM64_INS_PRFW, + {AArch64_PRFW_S_UXTW_SCALED, + ARM64_INS_PRFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PTEST_PP, ARM64_INS_PTEST, + {AArch64_PTEST_PP, + ARM64_INS_PTEST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PTRUES_B, ARM64_INS_PTRUES, + {AArch64_PTRUES_B, + ARM64_INS_PTRUES, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PTRUES_D, ARM64_INS_PTRUES, + {AArch64_PTRUES_D, + ARM64_INS_PTRUES, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PTRUES_H, ARM64_INS_PTRUES, + {AArch64_PTRUES_H, + ARM64_INS_PTRUES, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PTRUES_S, ARM64_INS_PTRUES, + {AArch64_PTRUES_S, + ARM64_INS_PTRUES, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PTRUE_B, ARM64_INS_PTRUE, + {AArch64_PTRUE_B, + ARM64_INS_PTRUE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PTRUE_D, ARM64_INS_PTRUE, + {AArch64_PTRUE_D, + ARM64_INS_PTRUE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PTRUE_H, ARM64_INS_PTRUE, + {AArch64_PTRUE_H, + ARM64_INS_PTRUE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PTRUE_S, ARM64_INS_PTRUE, + {AArch64_PTRUE_S, + ARM64_INS_PTRUE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PUNPKHI_PP, ARM64_INS_PUNPKHI, + {AArch64_PUNPKHI_PP, + ARM64_INS_PUNPKHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_PUNPKLO_PP, ARM64_INS_PUNPKLO, + {AArch64_PUNPKLO_PP, + ARM64_INS_PUNPKLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RADDHNv2i64_v2i32, ARM64_INS_RADDHN, + {AArch64_RADDHNv2i64_v2i32, + ARM64_INS_RADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RADDHNv2i64_v4i32, ARM64_INS_RADDHN2, + {AArch64_RADDHNv2i64_v4i32, + ARM64_INS_RADDHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RADDHNv4i32_v4i16, ARM64_INS_RADDHN, + {AArch64_RADDHNv4i32_v4i16, + ARM64_INS_RADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RADDHNv4i32_v8i16, ARM64_INS_RADDHN2, + {AArch64_RADDHNv4i32_v8i16, + ARM64_INS_RADDHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RADDHNv8i16_v16i8, ARM64_INS_RADDHN2, + {AArch64_RADDHNv8i16_v16i8, + ARM64_INS_RADDHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RADDHNv8i16_v8i8, ARM64_INS_RADDHN, + {AArch64_RADDHNv8i16_v8i8, + ARM64_INS_RADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RAX1, ARM64_INS_RAX1, + {AArch64_RAX1, + ARM64_INS_RAX1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RBITWr, ARM64_INS_RBIT, + {AArch64_RBITWr, + ARM64_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RBITXr, ARM64_INS_RBIT, + {AArch64_RBITXr, + ARM64_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RBIT_ZPmZ_B, ARM64_INS_RBIT, + {AArch64_RBIT_ZPmZ_B, + ARM64_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RBIT_ZPmZ_D, ARM64_INS_RBIT, + {AArch64_RBIT_ZPmZ_D, + ARM64_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RBIT_ZPmZ_H, ARM64_INS_RBIT, + {AArch64_RBIT_ZPmZ_H, + ARM64_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RBIT_ZPmZ_S, ARM64_INS_RBIT, + {AArch64_RBIT_ZPmZ_S, + ARM64_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RBITv16i8, ARM64_INS_RBIT, + {AArch64_RBITv16i8, + ARM64_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RBITv8i8, ARM64_INS_RBIT, + {AArch64_RBITv8i8, + ARM64_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RDFFRS_PPz, ARM64_INS_RDFFRS, + {AArch64_RDFFRS_PPz, + ARM64_INS_RDFFRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RDFFR_P, ARM64_INS_RDFFR, + {AArch64_RDFFR_P, + ARM64_INS_RDFFR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RDFFR_PPz, ARM64_INS_RDFFR, + {AArch64_RDFFR_PPz, + ARM64_INS_RDFFR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RDVLI_XI, ARM64_INS_RDVL, + {AArch64_RDVLI_XI, + ARM64_INS_RDVL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RET, ARM64_INS_RET, + {AArch64_RET, + ARM64_INS_RET, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_RET, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_RET, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RETAA, ARM64_INS_RETAA, + {AArch64_RETAA, + ARM64_INS_RETAA, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, ARM64_GRP_RET, 0 }, 0, 0 + {ARM64_REG_LR, ARM64_REG_SP, 0}, + {0}, + {ARM64_GRP_PAC, ARM64_GRP_RET, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RETAB, ARM64_INS_RETAB, + {AArch64_RETAB, + ARM64_INS_RETAB, #ifndef CAPSTONE_DIET - { ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, ARM64_GRP_RET, 0 }, 0, 0 + {ARM64_REG_LR, ARM64_REG_SP, 0}, + {0}, + {ARM64_GRP_PAC, ARM64_GRP_RET, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV16Wr, ARM64_INS_REV16, + {AArch64_REV16Wr, + ARM64_INS_REV16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV16Xr, ARM64_INS_REV16, + {AArch64_REV16Xr, + ARM64_INS_REV16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV16v16i8, ARM64_INS_REV16, + {AArch64_REV16v16i8, + ARM64_INS_REV16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV16v8i8, ARM64_INS_REV16, + {AArch64_REV16v8i8, + ARM64_INS_REV16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV32Xr, ARM64_INS_REV32, + {AArch64_REV32Xr, + ARM64_INS_REV32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV32v16i8, ARM64_INS_REV32, + {AArch64_REV32v16i8, + ARM64_INS_REV32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV32v4i16, ARM64_INS_REV32, + {AArch64_REV32v4i16, + ARM64_INS_REV32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV32v8i16, ARM64_INS_REV32, + {AArch64_REV32v8i16, + ARM64_INS_REV32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV32v8i8, ARM64_INS_REV32, + {AArch64_REV32v8i8, + ARM64_INS_REV32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV64v16i8, ARM64_INS_REV64, + {AArch64_REV64v16i8, + ARM64_INS_REV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV64v2i32, ARM64_INS_REV64, + {AArch64_REV64v2i32, + ARM64_INS_REV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV64v4i16, ARM64_INS_REV64, + {AArch64_REV64v4i16, + ARM64_INS_REV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV64v4i32, ARM64_INS_REV64, + {AArch64_REV64v4i32, + ARM64_INS_REV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV64v8i16, ARM64_INS_REV64, + {AArch64_REV64v8i16, + ARM64_INS_REV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV64v8i8, ARM64_INS_REV64, + {AArch64_REV64v8i8, + ARM64_INS_REV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REVB_ZPmZ_D, ARM64_INS_REVB, + {AArch64_REVB_ZPmZ_D, + ARM64_INS_REVB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REVB_ZPmZ_H, ARM64_INS_REVB, + {AArch64_REVB_ZPmZ_H, + ARM64_INS_REVB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REVB_ZPmZ_S, ARM64_INS_REVB, + {AArch64_REVB_ZPmZ_S, + ARM64_INS_REVB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REVH_ZPmZ_D, ARM64_INS_REVH, + {AArch64_REVH_ZPmZ_D, + ARM64_INS_REVH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REVH_ZPmZ_S, ARM64_INS_REVH, + {AArch64_REVH_ZPmZ_S, + ARM64_INS_REVH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REVW_ZPmZ_D, ARM64_INS_REVW, + {AArch64_REVW_ZPmZ_D, + ARM64_INS_REVW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REVWr, ARM64_INS_REV, + {AArch64_REVWr, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REVXr, ARM64_INS_REV, + {AArch64_REVXr, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV_PP_B, ARM64_INS_REV, + {AArch64_REV_PP_B, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV_PP_D, ARM64_INS_REV, + {AArch64_REV_PP_D, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV_PP_H, ARM64_INS_REV, + {AArch64_REV_PP_H, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV_PP_S, ARM64_INS_REV, + {AArch64_REV_PP_S, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV_ZZ_B, ARM64_INS_REV, + {AArch64_REV_ZZ_B, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV_ZZ_D, ARM64_INS_REV, + {AArch64_REV_ZZ_D, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV_ZZ_H, ARM64_INS_REV, + {AArch64_REV_ZZ_H, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_REV_ZZ_S, ARM64_INS_REV, + {AArch64_REV_ZZ_S, + ARM64_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RMIF, ARM64_INS_RMIF, + {AArch64_RMIF, + ARM64_INS_RMIF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RORVWr, ARM64_INS_ROR, + {AArch64_RORVWr, + ARM64_INS_ROR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RORVXr, ARM64_INS_ROR, + {AArch64_RORVXr, + ARM64_INS_ROR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSHRNv16i8_shift, ARM64_INS_RSHRN2, + {AArch64_RSHRNv16i8_shift, + ARM64_INS_RSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSHRNv2i32_shift, ARM64_INS_RSHRN, + {AArch64_RSHRNv2i32_shift, + ARM64_INS_RSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSHRNv4i16_shift, ARM64_INS_RSHRN, + {AArch64_RSHRNv4i16_shift, + ARM64_INS_RSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSHRNv4i32_shift, ARM64_INS_RSHRN2, + {AArch64_RSHRNv4i32_shift, + ARM64_INS_RSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSHRNv8i16_shift, ARM64_INS_RSHRN2, + {AArch64_RSHRNv8i16_shift, + ARM64_INS_RSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSHRNv8i8_shift, ARM64_INS_RSHRN, + {AArch64_RSHRNv8i8_shift, + ARM64_INS_RSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSUBHNv2i64_v2i32, ARM64_INS_RSUBHN, + {AArch64_RSUBHNv2i64_v2i32, + ARM64_INS_RSUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSUBHNv2i64_v4i32, ARM64_INS_RSUBHN2, + {AArch64_RSUBHNv2i64_v4i32, + ARM64_INS_RSUBHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSUBHNv4i32_v4i16, ARM64_INS_RSUBHN, + {AArch64_RSUBHNv4i32_v4i16, + ARM64_INS_RSUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSUBHNv4i32_v8i16, ARM64_INS_RSUBHN2, + {AArch64_RSUBHNv4i32_v8i16, + ARM64_INS_RSUBHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSUBHNv8i16_v16i8, ARM64_INS_RSUBHN2, + {AArch64_RSUBHNv8i16_v16i8, + ARM64_INS_RSUBHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_RSUBHNv8i16_v8i8, ARM64_INS_RSUBHN, + {AArch64_RSUBHNv8i16_v8i8, + ARM64_INS_RSUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABALv16i8_v8i16, ARM64_INS_SABAL2, + {AArch64_SABALv16i8_v8i16, + ARM64_INS_SABAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABALv2i32_v2i64, ARM64_INS_SABAL, + {AArch64_SABALv2i32_v2i64, + ARM64_INS_SABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABALv4i16_v4i32, ARM64_INS_SABAL, + {AArch64_SABALv4i16_v4i32, + ARM64_INS_SABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABALv4i32_v2i64, ARM64_INS_SABAL2, + {AArch64_SABALv4i32_v2i64, + ARM64_INS_SABAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABALv8i16_v4i32, ARM64_INS_SABAL2, + {AArch64_SABALv8i16_v4i32, + ARM64_INS_SABAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABALv8i8_v8i16, ARM64_INS_SABAL, + {AArch64_SABALv8i8_v8i16, + ARM64_INS_SABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABAv16i8, ARM64_INS_SABA, + {AArch64_SABAv16i8, + ARM64_INS_SABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABAv2i32, ARM64_INS_SABA, + {AArch64_SABAv2i32, + ARM64_INS_SABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABAv4i16, ARM64_INS_SABA, + {AArch64_SABAv4i16, + ARM64_INS_SABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABAv4i32, ARM64_INS_SABA, + {AArch64_SABAv4i32, + ARM64_INS_SABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABAv8i16, ARM64_INS_SABA, + {AArch64_SABAv8i16, + ARM64_INS_SABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABAv8i8, ARM64_INS_SABA, + {AArch64_SABAv8i8, + ARM64_INS_SABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDLv16i8_v8i16, ARM64_INS_SABDL2, + {AArch64_SABDLv16i8_v8i16, + ARM64_INS_SABDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDLv2i32_v2i64, ARM64_INS_SABDL, + {AArch64_SABDLv2i32_v2i64, + ARM64_INS_SABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDLv4i16_v4i32, ARM64_INS_SABDL, + {AArch64_SABDLv4i16_v4i32, + ARM64_INS_SABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDLv4i32_v2i64, ARM64_INS_SABDL2, + {AArch64_SABDLv4i32_v2i64, + ARM64_INS_SABDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDLv8i16_v4i32, ARM64_INS_SABDL2, + {AArch64_SABDLv8i16_v4i32, + ARM64_INS_SABDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDLv8i8_v8i16, ARM64_INS_SABDL, + {AArch64_SABDLv8i8_v8i16, + ARM64_INS_SABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABD_ZPmZ_B, ARM64_INS_SABD, + {AArch64_SABD_ZPmZ_B, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABD_ZPmZ_D, ARM64_INS_SABD, + {AArch64_SABD_ZPmZ_D, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABD_ZPmZ_H, ARM64_INS_SABD, + {AArch64_SABD_ZPmZ_H, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABD_ZPmZ_S, ARM64_INS_SABD, + {AArch64_SABD_ZPmZ_S, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDv16i8, ARM64_INS_SABD, + {AArch64_SABDv16i8, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDv2i32, ARM64_INS_SABD, + {AArch64_SABDv2i32, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDv4i16, ARM64_INS_SABD, + {AArch64_SABDv4i16, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDv4i32, ARM64_INS_SABD, + {AArch64_SABDv4i32, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDv8i16, ARM64_INS_SABD, + {AArch64_SABDv8i16, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SABDv8i8, ARM64_INS_SABD, + {AArch64_SABDv8i8, + ARM64_INS_SABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADALPv16i8_v8i16, ARM64_INS_SADALP, + {AArch64_SADALPv16i8_v8i16, + ARM64_INS_SADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADALPv2i32_v1i64, ARM64_INS_SADALP, + {AArch64_SADALPv2i32_v1i64, + ARM64_INS_SADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADALPv4i16_v2i32, ARM64_INS_SADALP, + {AArch64_SADALPv4i16_v2i32, + ARM64_INS_SADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADALPv4i32_v2i64, ARM64_INS_SADALP, + {AArch64_SADALPv4i32_v2i64, + ARM64_INS_SADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADALPv8i16_v4i32, ARM64_INS_SADALP, + {AArch64_SADALPv8i16_v4i32, + ARM64_INS_SADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADALPv8i8_v4i16, ARM64_INS_SADALP, + {AArch64_SADALPv8i8_v4i16, + ARM64_INS_SADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLPv16i8_v8i16, ARM64_INS_SADDLP, + {AArch64_SADDLPv16i8_v8i16, + ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLPv2i32_v1i64, ARM64_INS_SADDLP, + {AArch64_SADDLPv2i32_v1i64, + ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLPv4i16_v2i32, ARM64_INS_SADDLP, + {AArch64_SADDLPv4i16_v2i32, + ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLPv4i32_v2i64, ARM64_INS_SADDLP, + {AArch64_SADDLPv4i32_v2i64, + ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLPv8i16_v4i32, ARM64_INS_SADDLP, + {AArch64_SADDLPv8i16_v4i32, + ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLPv8i8_v4i16, ARM64_INS_SADDLP, + {AArch64_SADDLPv8i8_v4i16, + ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLVv16i8v, ARM64_INS_SADDLV, + {AArch64_SADDLVv16i8v, + ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLVv4i16v, ARM64_INS_SADDLV, + {AArch64_SADDLVv4i16v, + ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLVv4i32v, ARM64_INS_SADDLV, + {AArch64_SADDLVv4i32v, + ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLVv8i16v, ARM64_INS_SADDLV, + {AArch64_SADDLVv8i16v, + ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLVv8i8v, ARM64_INS_SADDLV, + {AArch64_SADDLVv8i8v, + ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLv16i8_v8i16, ARM64_INS_SADDL2, + {AArch64_SADDLv16i8_v8i16, + ARM64_INS_SADDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLv2i32_v2i64, ARM64_INS_SADDL, + {AArch64_SADDLv2i32_v2i64, + ARM64_INS_SADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLv4i16_v4i32, ARM64_INS_SADDL, + {AArch64_SADDLv4i16_v4i32, + ARM64_INS_SADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLv4i32_v2i64, ARM64_INS_SADDL2, + {AArch64_SADDLv4i32_v2i64, + ARM64_INS_SADDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLv8i16_v4i32, ARM64_INS_SADDL2, + {AArch64_SADDLv8i16_v4i32, + ARM64_INS_SADDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDLv8i8_v8i16, ARM64_INS_SADDL, + {AArch64_SADDLv8i8_v8i16, + ARM64_INS_SADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDV_VPZ_B, ARM64_INS_SADDV, + {AArch64_SADDV_VPZ_B, + ARM64_INS_SADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDV_VPZ_H, ARM64_INS_SADDV, + {AArch64_SADDV_VPZ_H, + ARM64_INS_SADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDV_VPZ_S, ARM64_INS_SADDV, + {AArch64_SADDV_VPZ_S, + ARM64_INS_SADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDWv16i8_v8i16, ARM64_INS_SADDW2, + {AArch64_SADDWv16i8_v8i16, + ARM64_INS_SADDW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDWv2i32_v2i64, ARM64_INS_SADDW, + {AArch64_SADDWv2i32_v2i64, + ARM64_INS_SADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDWv4i16_v4i32, ARM64_INS_SADDW, + {AArch64_SADDWv4i16_v4i32, + ARM64_INS_SADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDWv4i32_v2i64, ARM64_INS_SADDW2, + {AArch64_SADDWv4i32_v2i64, + ARM64_INS_SADDW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDWv8i16_v4i32, ARM64_INS_SADDW2, + {AArch64_SADDWv8i16_v4i32, + ARM64_INS_SADDW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SADDWv8i8_v8i16, ARM64_INS_SADDW, + {AArch64_SADDWv8i8_v8i16, + ARM64_INS_SADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SBCSWr, ARM64_INS_SBCS, + {AArch64_SBCSWr, + ARM64_INS_SBCS, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SBCSXr, ARM64_INS_SBCS, + {AArch64_SBCSXr, + ARM64_INS_SBCS, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SBCWr, ARM64_INS_SBC, + {AArch64_SBCWr, + ARM64_INS_SBC, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SBCXr, ARM64_INS_SBC, + {AArch64_SBCXr, + ARM64_INS_SBC, #ifndef CAPSTONE_DIET - { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 + {ARM64_REG_NZCV, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SBFMWri, ARM64_INS_SBFM, + {AArch64_SBFMWri, + ARM64_INS_SBFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SBFMXri, ARM64_INS_SBFM, + {AArch64_SBFMXri, + ARM64_INS_SBFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFSWDri, ARM64_INS_SCVTF, + {AArch64_SCVTFSWDri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFSWHri, ARM64_INS_SCVTF, + {AArch64_SCVTFSWHri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFSWSri, ARM64_INS_SCVTF, + {AArch64_SCVTFSWSri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFSXDri, ARM64_INS_SCVTF, + {AArch64_SCVTFSXDri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFSXHri, ARM64_INS_SCVTF, + {AArch64_SCVTFSXHri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFSXSri, ARM64_INS_SCVTF, + {AArch64_SCVTFSXSri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFUWDri, ARM64_INS_SCVTF, + {AArch64_SCVTFUWDri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFUWHri, ARM64_INS_SCVTF, + {AArch64_SCVTFUWHri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFUWSri, ARM64_INS_SCVTF, + {AArch64_SCVTFUWSri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFUXDri, ARM64_INS_SCVTF, + {AArch64_SCVTFUXDri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFUXHri, ARM64_INS_SCVTF, + {AArch64_SCVTFUXHri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFUXSri, ARM64_INS_SCVTF, + {AArch64_SCVTFUXSri, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTF_ZPmZ_DtoD, ARM64_INS_SCVTF, + {AArch64_SCVTF_ZPmZ_DtoD, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTF_ZPmZ_DtoH, ARM64_INS_SCVTF, + {AArch64_SCVTF_ZPmZ_DtoH, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTF_ZPmZ_DtoS, ARM64_INS_SCVTF, + {AArch64_SCVTF_ZPmZ_DtoS, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTF_ZPmZ_HtoH, ARM64_INS_SCVTF, + {AArch64_SCVTF_ZPmZ_HtoH, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTF_ZPmZ_StoD, ARM64_INS_SCVTF, + {AArch64_SCVTF_ZPmZ_StoD, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTF_ZPmZ_StoH, ARM64_INS_SCVTF, + {AArch64_SCVTF_ZPmZ_StoH, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTF_ZPmZ_StoS, ARM64_INS_SCVTF, + {AArch64_SCVTF_ZPmZ_StoS, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFd, ARM64_INS_SCVTF, + {AArch64_SCVTFd, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFh, ARM64_INS_SCVTF, + {AArch64_SCVTFh, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFs, ARM64_INS_SCVTF, + {AArch64_SCVTFs, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv1i16, ARM64_INS_SCVTF, + {AArch64_SCVTFv1i16, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv1i32, ARM64_INS_SCVTF, + {AArch64_SCVTFv1i32, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv1i64, ARM64_INS_SCVTF, + {AArch64_SCVTFv1i64, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv2f32, ARM64_INS_SCVTF, + {AArch64_SCVTFv2f32, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv2f64, ARM64_INS_SCVTF, + {AArch64_SCVTFv2f64, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv2i32_shift, ARM64_INS_SCVTF, + {AArch64_SCVTFv2i32_shift, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv2i64_shift, ARM64_INS_SCVTF, + {AArch64_SCVTFv2i64_shift, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv4f16, ARM64_INS_SCVTF, + {AArch64_SCVTFv4f16, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv4f32, ARM64_INS_SCVTF, + {AArch64_SCVTFv4f32, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv4i16_shift, ARM64_INS_SCVTF, + {AArch64_SCVTFv4i16_shift, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv4i32_shift, ARM64_INS_SCVTF, + {AArch64_SCVTFv4i32_shift, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv8f16, ARM64_INS_SCVTF, + {AArch64_SCVTFv8f16, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SCVTFv8i16_shift, ARM64_INS_SCVTF, + {AArch64_SCVTFv8i16_shift, + ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDIVR_ZPmZ_D, ARM64_INS_SDIVR, + {AArch64_SDIVR_ZPmZ_D, + ARM64_INS_SDIVR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDIVR_ZPmZ_S, ARM64_INS_SDIVR, + {AArch64_SDIVR_ZPmZ_S, + ARM64_INS_SDIVR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDIVWr, ARM64_INS_SDIV, + {AArch64_SDIVWr, + ARM64_INS_SDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDIVXr, ARM64_INS_SDIV, + {AArch64_SDIVXr, + ARM64_INS_SDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDIV_ZPmZ_D, ARM64_INS_SDIV, + {AArch64_SDIV_ZPmZ_D, + ARM64_INS_SDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDIV_ZPmZ_S, ARM64_INS_SDIV, + {AArch64_SDIV_ZPmZ_S, + ARM64_INS_SDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDOT_ZZZI_D, ARM64_INS_SDOT, + {AArch64_SDOT_ZZZI_D, + ARM64_INS_SDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDOT_ZZZI_S, ARM64_INS_SDOT, + {AArch64_SDOT_ZZZI_S, + ARM64_INS_SDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDOT_ZZZ_D, ARM64_INS_SDOT, + {AArch64_SDOT_ZZZ_D, + ARM64_INS_SDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDOT_ZZZ_S, ARM64_INS_SDOT, + {AArch64_SDOT_ZZZ_S, + ARM64_INS_SDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDOTlanev16i8, ARM64_INS_SDOT, + {AArch64_SDOTlanev16i8, + ARM64_INS_SDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDOTlanev8i8, ARM64_INS_SDOT, + {AArch64_SDOTlanev8i8, + ARM64_INS_SDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDOTv16i8, ARM64_INS_SDOT, + {AArch64_SDOTv16i8, + ARM64_INS_SDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SDOTv8i8, ARM64_INS_SDOT, + {AArch64_SDOTv8i8, + ARM64_INS_SDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SEL_PPPP, ARM64_INS_MOV, + {AArch64_SEL_PPPP, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SEL_ZPZZ_B, ARM64_INS_MOV, + {AArch64_SEL_ZPZZ_B, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SEL_ZPZZ_D, ARM64_INS_MOV, + {AArch64_SEL_ZPZZ_D, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SEL_ZPZZ_H, ARM64_INS_MOV, + {AArch64_SEL_ZPZZ_H, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SEL_ZPZZ_S, ARM64_INS_MOV, + {AArch64_SEL_ZPZZ_S, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SETF16, ARM64_INS_SETF16, + {AArch64_SETF16, + ARM64_INS_SETF16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SETF8, ARM64_INS_SETF8, + {AArch64_SETF8, + ARM64_INS_SETF8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SETFFR, ARM64_INS_SETFFR, + {AArch64_SETFFR, + ARM64_INS_SETFFR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA1Crrr, ARM64_INS_SHA1C, + {AArch64_SHA1Crrr, + ARM64_INS_SHA1C, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA1Hrr, ARM64_INS_SHA1H, + {AArch64_SHA1Hrr, + ARM64_INS_SHA1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA1Mrrr, ARM64_INS_SHA1M, + {AArch64_SHA1Mrrr, + ARM64_INS_SHA1M, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA1Prrr, ARM64_INS_SHA1P, + {AArch64_SHA1Prrr, + ARM64_INS_SHA1P, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA1SU0rrr, ARM64_INS_SHA1SU0, + {AArch64_SHA1SU0rrr, + ARM64_INS_SHA1SU0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA1SU1rr, ARM64_INS_SHA1SU1, + {AArch64_SHA1SU1rr, + ARM64_INS_SHA1SU1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA256H2rrr, ARM64_INS_SHA256H2, + {AArch64_SHA256H2rrr, + ARM64_INS_SHA256H2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA256Hrrr, ARM64_INS_SHA256H, + {AArch64_SHA256Hrrr, + ARM64_INS_SHA256H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA256SU0rr, ARM64_INS_SHA256SU0, + {AArch64_SHA256SU0rr, + ARM64_INS_SHA256SU0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA256SU1rrr, ARM64_INS_SHA256SU1, + {AArch64_SHA256SU1rrr, + ARM64_INS_SHA256SU1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA512H, ARM64_INS_SHA512H, + {AArch64_SHA512H, + ARM64_INS_SHA512H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA512H2, ARM64_INS_SHA512H2, + {AArch64_SHA512H2, + ARM64_INS_SHA512H2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA512SU0, ARM64_INS_SHA512SU0, + {AArch64_SHA512SU0, + ARM64_INS_SHA512SU0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHA512SU1, ARM64_INS_SHA512SU1, + {AArch64_SHA512SU1, + ARM64_INS_SHA512SU1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHADDv16i8, ARM64_INS_SHADD, + {AArch64_SHADDv16i8, + ARM64_INS_SHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHADDv2i32, ARM64_INS_SHADD, + {AArch64_SHADDv2i32, + ARM64_INS_SHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHADDv4i16, ARM64_INS_SHADD, + {AArch64_SHADDv4i16, + ARM64_INS_SHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHADDv4i32, ARM64_INS_SHADD, + {AArch64_SHADDv4i32, + ARM64_INS_SHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHADDv8i16, ARM64_INS_SHADD, + {AArch64_SHADDv8i16, + ARM64_INS_SHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHADDv8i8, ARM64_INS_SHADD, + {AArch64_SHADDv8i8, + ARM64_INS_SHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLLv16i8, ARM64_INS_SHLL2, + {AArch64_SHLLv16i8, + ARM64_INS_SHLL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLLv2i32, ARM64_INS_SHLL, + {AArch64_SHLLv2i32, + ARM64_INS_SHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLLv4i16, ARM64_INS_SHLL, + {AArch64_SHLLv4i16, + ARM64_INS_SHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLLv4i32, ARM64_INS_SHLL2, + {AArch64_SHLLv4i32, + ARM64_INS_SHLL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLLv8i16, ARM64_INS_SHLL2, + {AArch64_SHLLv8i16, + ARM64_INS_SHLL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLLv8i8, ARM64_INS_SHLL, + {AArch64_SHLLv8i8, + ARM64_INS_SHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLd, ARM64_INS_SHL, + {AArch64_SHLd, + ARM64_INS_SHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLv16i8_shift, ARM64_INS_SHL, + {AArch64_SHLv16i8_shift, + ARM64_INS_SHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLv2i32_shift, ARM64_INS_SHL, + {AArch64_SHLv2i32_shift, + ARM64_INS_SHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLv2i64_shift, ARM64_INS_SHL, + {AArch64_SHLv2i64_shift, + ARM64_INS_SHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLv4i16_shift, ARM64_INS_SHL, + {AArch64_SHLv4i16_shift, + ARM64_INS_SHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLv4i32_shift, ARM64_INS_SHL, + {AArch64_SHLv4i32_shift, + ARM64_INS_SHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLv8i16_shift, ARM64_INS_SHL, + {AArch64_SHLv8i16_shift, + ARM64_INS_SHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHLv8i8_shift, ARM64_INS_SHL, + {AArch64_SHLv8i8_shift, + ARM64_INS_SHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHRNv16i8_shift, ARM64_INS_SHRN2, + {AArch64_SHRNv16i8_shift, + ARM64_INS_SHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHRNv2i32_shift, ARM64_INS_SHRN, + {AArch64_SHRNv2i32_shift, + ARM64_INS_SHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHRNv4i16_shift, ARM64_INS_SHRN, + {AArch64_SHRNv4i16_shift, + ARM64_INS_SHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHRNv4i32_shift, ARM64_INS_SHRN2, + {AArch64_SHRNv4i32_shift, + ARM64_INS_SHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHRNv8i16_shift, ARM64_INS_SHRN2, + {AArch64_SHRNv8i16_shift, + ARM64_INS_SHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHRNv8i8_shift, ARM64_INS_SHRN, + {AArch64_SHRNv8i8_shift, + ARM64_INS_SHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHSUBv16i8, ARM64_INS_SHSUB, + {AArch64_SHSUBv16i8, + ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHSUBv2i32, ARM64_INS_SHSUB, + {AArch64_SHSUBv2i32, + ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHSUBv4i16, ARM64_INS_SHSUB, + {AArch64_SHSUBv4i16, + ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHSUBv4i32, ARM64_INS_SHSUB, + {AArch64_SHSUBv4i32, + ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHSUBv8i16, ARM64_INS_SHSUB, + {AArch64_SHSUBv8i16, + ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SHSUBv8i8, ARM64_INS_SHSUB, + {AArch64_SHSUBv8i8, + ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SLId, ARM64_INS_SLI, + {AArch64_SLId, + ARM64_INS_SLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SLIv16i8_shift, ARM64_INS_SLI, + {AArch64_SLIv16i8_shift, + ARM64_INS_SLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SLIv2i32_shift, ARM64_INS_SLI, + {AArch64_SLIv2i32_shift, + ARM64_INS_SLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SLIv2i64_shift, ARM64_INS_SLI, + {AArch64_SLIv2i64_shift, + ARM64_INS_SLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SLIv4i16_shift, ARM64_INS_SLI, + {AArch64_SLIv4i16_shift, + ARM64_INS_SLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SLIv4i32_shift, ARM64_INS_SLI, + {AArch64_SLIv4i32_shift, + ARM64_INS_SLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SLIv8i16_shift, ARM64_INS_SLI, + {AArch64_SLIv8i16_shift, + ARM64_INS_SLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SLIv8i8_shift, ARM64_INS_SLI, + {AArch64_SLIv8i8_shift, + ARM64_INS_SLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SM3PARTW1, ARM64_INS_SM3PARTW1, + {AArch64_SM3PARTW1, + ARM64_INS_SM3PARTW1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SM3PARTW2, ARM64_INS_SM3PARTW2, + {AArch64_SM3PARTW2, + ARM64_INS_SM3PARTW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SM3SS1, ARM64_INS_SM3SS1, + {AArch64_SM3SS1, + ARM64_INS_SM3SS1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SM3TT1A, ARM64_INS_SM3TT1A, + {AArch64_SM3TT1A, + ARM64_INS_SM3TT1A, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SM3TT1B, ARM64_INS_SM3TT1B, + {AArch64_SM3TT1B, + ARM64_INS_SM3TT1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SM3TT2A, ARM64_INS_SM3TT2A, + {AArch64_SM3TT2A, + ARM64_INS_SM3TT2A, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SM3TT2B, ARM64_INS_SM3TT2B, + {AArch64_SM3TT2B, + ARM64_INS_SM3TT2B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SM4E, ARM64_INS_SM4E, + {AArch64_SM4E, + ARM64_INS_SM4E, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SM4ENCKEY, ARM64_INS_SM4EKEY, + {AArch64_SM4ENCKEY, + ARM64_INS_SM4EKEY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMADDLrrr, ARM64_INS_SMADDL, + {AArch64_SMADDLrrr, + ARM64_INS_SMADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXPv16i8, ARM64_INS_SMAXP, + {AArch64_SMAXPv16i8, + ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXPv2i32, ARM64_INS_SMAXP, + {AArch64_SMAXPv2i32, + ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXPv4i16, ARM64_INS_SMAXP, + {AArch64_SMAXPv4i16, + ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXPv4i32, ARM64_INS_SMAXP, + {AArch64_SMAXPv4i32, + ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXPv8i16, ARM64_INS_SMAXP, + {AArch64_SMAXPv8i16, + ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXPv8i8, ARM64_INS_SMAXP, + {AArch64_SMAXPv8i8, + ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXV_VPZ_B, ARM64_INS_SMAXV, + {AArch64_SMAXV_VPZ_B, + ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXV_VPZ_D, ARM64_INS_SMAXV, + {AArch64_SMAXV_VPZ_D, + ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXV_VPZ_H, ARM64_INS_SMAXV, + {AArch64_SMAXV_VPZ_H, + ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXV_VPZ_S, ARM64_INS_SMAXV, + {AArch64_SMAXV_VPZ_S, + ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXVv16i8v, ARM64_INS_SMAXV, + {AArch64_SMAXVv16i8v, + ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXVv4i16v, ARM64_INS_SMAXV, + {AArch64_SMAXVv4i16v, + ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXVv4i32v, ARM64_INS_SMAXV, + {AArch64_SMAXVv4i32v, + ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXVv8i16v, ARM64_INS_SMAXV, + {AArch64_SMAXVv8i16v, + ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXVv8i8v, ARM64_INS_SMAXV, + {AArch64_SMAXVv8i8v, + ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAX_ZI_B, ARM64_INS_SMAX, + {AArch64_SMAX_ZI_B, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAX_ZI_D, ARM64_INS_SMAX, + {AArch64_SMAX_ZI_D, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAX_ZI_H, ARM64_INS_SMAX, + {AArch64_SMAX_ZI_H, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAX_ZI_S, ARM64_INS_SMAX, + {AArch64_SMAX_ZI_S, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAX_ZPmZ_B, ARM64_INS_SMAX, + {AArch64_SMAX_ZPmZ_B, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAX_ZPmZ_D, ARM64_INS_SMAX, + {AArch64_SMAX_ZPmZ_D, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAX_ZPmZ_H, ARM64_INS_SMAX, + {AArch64_SMAX_ZPmZ_H, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAX_ZPmZ_S, ARM64_INS_SMAX, + {AArch64_SMAX_ZPmZ_S, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXv16i8, ARM64_INS_SMAX, + {AArch64_SMAXv16i8, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXv2i32, ARM64_INS_SMAX, + {AArch64_SMAXv2i32, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXv4i16, ARM64_INS_SMAX, + {AArch64_SMAXv4i16, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXv4i32, ARM64_INS_SMAX, + {AArch64_SMAXv4i32, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXv8i16, ARM64_INS_SMAX, + {AArch64_SMAXv8i16, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMAXv8i8, ARM64_INS_SMAX, + {AArch64_SMAXv8i8, + ARM64_INS_SMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMC, ARM64_INS_SMC, + {AArch64_SMC, + ARM64_INS_SMC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINPv16i8, ARM64_INS_SMINP, + {AArch64_SMINPv16i8, + ARM64_INS_SMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINPv2i32, ARM64_INS_SMINP, + {AArch64_SMINPv2i32, + ARM64_INS_SMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINPv4i16, ARM64_INS_SMINP, + {AArch64_SMINPv4i16, + ARM64_INS_SMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINPv4i32, ARM64_INS_SMINP, + {AArch64_SMINPv4i32, + ARM64_INS_SMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINPv8i16, ARM64_INS_SMINP, + {AArch64_SMINPv8i16, + ARM64_INS_SMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINPv8i8, ARM64_INS_SMINP, + {AArch64_SMINPv8i8, + ARM64_INS_SMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINV_VPZ_B, ARM64_INS_SMINV, + {AArch64_SMINV_VPZ_B, + ARM64_INS_SMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINV_VPZ_D, ARM64_INS_SMINV, + {AArch64_SMINV_VPZ_D, + ARM64_INS_SMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINV_VPZ_H, ARM64_INS_SMINV, + {AArch64_SMINV_VPZ_H, + ARM64_INS_SMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINV_VPZ_S, ARM64_INS_SMINV, + {AArch64_SMINV_VPZ_S, + ARM64_INS_SMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINVv16i8v, ARM64_INS_SMINV, + {AArch64_SMINVv16i8v, + ARM64_INS_SMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINVv4i16v, ARM64_INS_SMINV, + {AArch64_SMINVv4i16v, + ARM64_INS_SMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINVv4i32v, ARM64_INS_SMINV, + {AArch64_SMINVv4i32v, + ARM64_INS_SMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINVv8i16v, ARM64_INS_SMINV, + {AArch64_SMINVv8i16v, + ARM64_INS_SMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINVv8i8v, ARM64_INS_SMINV, + {AArch64_SMINVv8i8v, + ARM64_INS_SMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMIN_ZI_B, ARM64_INS_SMIN, + {AArch64_SMIN_ZI_B, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMIN_ZI_D, ARM64_INS_SMIN, + {AArch64_SMIN_ZI_D, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMIN_ZI_H, ARM64_INS_SMIN, + {AArch64_SMIN_ZI_H, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMIN_ZI_S, ARM64_INS_SMIN, + {AArch64_SMIN_ZI_S, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMIN_ZPmZ_B, ARM64_INS_SMIN, + {AArch64_SMIN_ZPmZ_B, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMIN_ZPmZ_D, ARM64_INS_SMIN, + {AArch64_SMIN_ZPmZ_D, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMIN_ZPmZ_H, ARM64_INS_SMIN, + {AArch64_SMIN_ZPmZ_H, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMIN_ZPmZ_S, ARM64_INS_SMIN, + {AArch64_SMIN_ZPmZ_S, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINv16i8, ARM64_INS_SMIN, + {AArch64_SMINv16i8, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINv2i32, ARM64_INS_SMIN, + {AArch64_SMINv2i32, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINv4i16, ARM64_INS_SMIN, + {AArch64_SMINv4i16, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINv4i32, ARM64_INS_SMIN, + {AArch64_SMINv4i32, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINv8i16, ARM64_INS_SMIN, + {AArch64_SMINv8i16, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMINv8i8, ARM64_INS_SMIN, + {AArch64_SMINv8i8, + ARM64_INS_SMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv16i8_v8i16, ARM64_INS_SMLAL2, + {AArch64_SMLALv16i8_v8i16, + ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv2i32_indexed, ARM64_INS_SMLAL, + {AArch64_SMLALv2i32_indexed, + ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv2i32_v2i64, ARM64_INS_SMLAL, + {AArch64_SMLALv2i32_v2i64, + ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv4i16_indexed, ARM64_INS_SMLAL, + {AArch64_SMLALv4i16_indexed, + ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv4i16_v4i32, ARM64_INS_SMLAL, + {AArch64_SMLALv4i16_v4i32, + ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv4i32_indexed, ARM64_INS_SMLAL2, + {AArch64_SMLALv4i32_indexed, + ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv4i32_v2i64, ARM64_INS_SMLAL2, + {AArch64_SMLALv4i32_v2i64, + ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv8i16_indexed, ARM64_INS_SMLAL2, + {AArch64_SMLALv8i16_indexed, + ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv8i16_v4i32, ARM64_INS_SMLAL2, + {AArch64_SMLALv8i16_v4i32, + ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLALv8i8_v8i16, ARM64_INS_SMLAL, + {AArch64_SMLALv8i8_v8i16, + ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv16i8_v8i16, ARM64_INS_SMLSL2, + {AArch64_SMLSLv16i8_v8i16, + ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv2i32_indexed, ARM64_INS_SMLSL, + {AArch64_SMLSLv2i32_indexed, + ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv2i32_v2i64, ARM64_INS_SMLSL, + {AArch64_SMLSLv2i32_v2i64, + ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv4i16_indexed, ARM64_INS_SMLSL, + {AArch64_SMLSLv4i16_indexed, + ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv4i16_v4i32, ARM64_INS_SMLSL, + {AArch64_SMLSLv4i16_v4i32, + ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv4i32_indexed, ARM64_INS_SMLSL2, + {AArch64_SMLSLv4i32_indexed, + ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv4i32_v2i64, ARM64_INS_SMLSL2, + {AArch64_SMLSLv4i32_v2i64, + ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv8i16_indexed, ARM64_INS_SMLSL2, + {AArch64_SMLSLv8i16_indexed, + ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv8i16_v4i32, ARM64_INS_SMLSL2, + {AArch64_SMLSLv8i16_v4i32, + ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMLSLv8i8_v8i16, ARM64_INS_SMLSL, + {AArch64_SMLSLv8i8_v8i16, + ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMOVvi16to32, ARM64_INS_SMOV, + {AArch64_SMOVvi16to32, + ARM64_INS_SMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMOVvi16to64, ARM64_INS_SMOV, + {AArch64_SMOVvi16to64, + ARM64_INS_SMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMOVvi32to64, ARM64_INS_SMOV, + {AArch64_SMOVvi32to64, + ARM64_INS_SMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMOVvi8to32, ARM64_INS_SMOV, + {AArch64_SMOVvi8to32, + ARM64_INS_SMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMOVvi8to64, ARM64_INS_SMOV, + {AArch64_SMOVvi8to64, + ARM64_INS_SMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMSUBLrrr, ARM64_INS_SMSUBL, + {AArch64_SMSUBLrrr, + ARM64_INS_SMSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULH_ZPmZ_B, ARM64_INS_SMULH, + {AArch64_SMULH_ZPmZ_B, + ARM64_INS_SMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULH_ZPmZ_D, ARM64_INS_SMULH, + {AArch64_SMULH_ZPmZ_D, + ARM64_INS_SMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULH_ZPmZ_H, ARM64_INS_SMULH, + {AArch64_SMULH_ZPmZ_H, + ARM64_INS_SMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULH_ZPmZ_S, ARM64_INS_SMULH, + {AArch64_SMULH_ZPmZ_S, + ARM64_INS_SMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULHrr, ARM64_INS_SMULH, + {AArch64_SMULHrr, + ARM64_INS_SMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv16i8_v8i16, ARM64_INS_SMULL2, + {AArch64_SMULLv16i8_v8i16, + ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv2i32_indexed, ARM64_INS_SMULL, + {AArch64_SMULLv2i32_indexed, + ARM64_INS_SMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv2i32_v2i64, ARM64_INS_SMULL, + {AArch64_SMULLv2i32_v2i64, + ARM64_INS_SMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv4i16_indexed, ARM64_INS_SMULL, + {AArch64_SMULLv4i16_indexed, + ARM64_INS_SMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv4i16_v4i32, ARM64_INS_SMULL, + {AArch64_SMULLv4i16_v4i32, + ARM64_INS_SMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv4i32_indexed, ARM64_INS_SMULL2, + {AArch64_SMULLv4i32_indexed, + ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv4i32_v2i64, ARM64_INS_SMULL2, + {AArch64_SMULLv4i32_v2i64, + ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv8i16_indexed, ARM64_INS_SMULL2, + {AArch64_SMULLv8i16_indexed, + ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv8i16_v4i32, ARM64_INS_SMULL2, + {AArch64_SMULLv8i16_v4i32, + ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SMULLv8i8_v8i16, ARM64_INS_SMULL, + {AArch64_SMULLv8i8_v8i16, + ARM64_INS_SMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SPLICE_ZPZ_B, ARM64_INS_SPLICE, + {AArch64_SPLICE_ZPZ_B, + ARM64_INS_SPLICE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SPLICE_ZPZ_D, ARM64_INS_SPLICE, + {AArch64_SPLICE_ZPZ_D, + ARM64_INS_SPLICE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SPLICE_ZPZ_H, ARM64_INS_SPLICE, + {AArch64_SPLICE_ZPZ_H, + ARM64_INS_SPLICE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SPLICE_ZPZ_S, ARM64_INS_SPLICE, + {AArch64_SPLICE_ZPZ_S, + ARM64_INS_SPLICE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv16i8, ARM64_INS_SQABS, + {AArch64_SQABSv16i8, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv1i16, ARM64_INS_SQABS, + {AArch64_SQABSv1i16, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv1i32, ARM64_INS_SQABS, + {AArch64_SQABSv1i32, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv1i64, ARM64_INS_SQABS, + {AArch64_SQABSv1i64, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv1i8, ARM64_INS_SQABS, + {AArch64_SQABSv1i8, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv2i32, ARM64_INS_SQABS, + {AArch64_SQABSv2i32, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv2i64, ARM64_INS_SQABS, + {AArch64_SQABSv2i64, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv4i16, ARM64_INS_SQABS, + {AArch64_SQABSv4i16, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv4i32, ARM64_INS_SQABS, + {AArch64_SQABSv4i32, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv8i16, ARM64_INS_SQABS, + {AArch64_SQABSv8i16, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQABSv8i8, ARM64_INS_SQABS, + {AArch64_SQABSv8i8, + ARM64_INS_SQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADD_ZI_B, ARM64_INS_SQADD, + {AArch64_SQADD_ZI_B, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADD_ZI_D, ARM64_INS_SQADD, + {AArch64_SQADD_ZI_D, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADD_ZI_H, ARM64_INS_SQADD, + {AArch64_SQADD_ZI_H, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADD_ZI_S, ARM64_INS_SQADD, + {AArch64_SQADD_ZI_S, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADD_ZZZ_B, ARM64_INS_SQADD, + {AArch64_SQADD_ZZZ_B, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADD_ZZZ_D, ARM64_INS_SQADD, + {AArch64_SQADD_ZZZ_D, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADD_ZZZ_H, ARM64_INS_SQADD, + {AArch64_SQADD_ZZZ_H, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADD_ZZZ_S, ARM64_INS_SQADD, + {AArch64_SQADD_ZZZ_S, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv16i8, ARM64_INS_SQADD, + {AArch64_SQADDv16i8, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv1i16, ARM64_INS_SQADD, + {AArch64_SQADDv1i16, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv1i32, ARM64_INS_SQADD, + {AArch64_SQADDv1i32, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv1i64, ARM64_INS_SQADD, + {AArch64_SQADDv1i64, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv1i8, ARM64_INS_SQADD, + {AArch64_SQADDv1i8, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv2i32, ARM64_INS_SQADD, + {AArch64_SQADDv2i32, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv2i64, ARM64_INS_SQADD, + {AArch64_SQADDv2i64, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv4i16, ARM64_INS_SQADD, + {AArch64_SQADDv4i16, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv4i32, ARM64_INS_SQADD, + {AArch64_SQADDv4i32, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv8i16, ARM64_INS_SQADD, + {AArch64_SQADDv8i16, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQADDv8i8, ARM64_INS_SQADD, + {AArch64_SQADDv8i8, + ARM64_INS_SQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECB_XPiI, ARM64_INS_SQDECB, + {AArch64_SQDECB_XPiI, + ARM64_INS_SQDECB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECB_XPiWdI, ARM64_INS_SQDECB, + {AArch64_SQDECB_XPiWdI, + ARM64_INS_SQDECB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECD_XPiI, ARM64_INS_SQDECD, + {AArch64_SQDECD_XPiI, + ARM64_INS_SQDECD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECD_XPiWdI, ARM64_INS_SQDECD, + {AArch64_SQDECD_XPiWdI, + ARM64_INS_SQDECD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECD_ZPiI, ARM64_INS_SQDECD, + {AArch64_SQDECD_ZPiI, + ARM64_INS_SQDECD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECH_XPiI, ARM64_INS_SQDECH, + {AArch64_SQDECH_XPiI, + ARM64_INS_SQDECH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECH_XPiWdI, ARM64_INS_SQDECH, + {AArch64_SQDECH_XPiWdI, + ARM64_INS_SQDECH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECH_ZPiI, ARM64_INS_SQDECH, + {AArch64_SQDECH_ZPiI, + ARM64_INS_SQDECH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_XPWd_B, ARM64_INS_SQDECP, + {AArch64_SQDECP_XPWd_B, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_XPWd_D, ARM64_INS_SQDECP, + {AArch64_SQDECP_XPWd_D, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_XPWd_H, ARM64_INS_SQDECP, + {AArch64_SQDECP_XPWd_H, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_XPWd_S, ARM64_INS_SQDECP, + {AArch64_SQDECP_XPWd_S, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_XP_B, ARM64_INS_SQDECP, + {AArch64_SQDECP_XP_B, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_XP_D, ARM64_INS_SQDECP, + {AArch64_SQDECP_XP_D, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_XP_H, ARM64_INS_SQDECP, + {AArch64_SQDECP_XP_H, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_XP_S, ARM64_INS_SQDECP, + {AArch64_SQDECP_XP_S, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_ZP_D, ARM64_INS_SQDECP, + {AArch64_SQDECP_ZP_D, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_ZP_H, ARM64_INS_SQDECP, + {AArch64_SQDECP_ZP_H, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECP_ZP_S, ARM64_INS_SQDECP, + {AArch64_SQDECP_ZP_S, + ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECW_XPiI, ARM64_INS_SQDECW, + {AArch64_SQDECW_XPiI, + ARM64_INS_SQDECW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECW_XPiWdI, ARM64_INS_SQDECW, + {AArch64_SQDECW_XPiWdI, + ARM64_INS_SQDECW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDECW_ZPiI, ARM64_INS_SQDECW, + {AArch64_SQDECW_ZPiI, + ARM64_INS_SQDECW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALi16, ARM64_INS_SQDMLAL, + {AArch64_SQDMLALi16, + ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALi32, ARM64_INS_SQDMLAL, + {AArch64_SQDMLALi32, + ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv1i32_indexed, ARM64_INS_SQDMLAL, + {AArch64_SQDMLALv1i32_indexed, + ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv1i64_indexed, ARM64_INS_SQDMLAL, + {AArch64_SQDMLALv1i64_indexed, + ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv2i32_indexed, ARM64_INS_SQDMLAL, + {AArch64_SQDMLALv2i32_indexed, + ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv2i32_v2i64, ARM64_INS_SQDMLAL, + {AArch64_SQDMLALv2i32_v2i64, + ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv4i16_indexed, ARM64_INS_SQDMLAL, + {AArch64_SQDMLALv4i16_indexed, + ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv4i16_v4i32, ARM64_INS_SQDMLAL, + {AArch64_SQDMLALv4i16_v4i32, + ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv4i32_indexed, ARM64_INS_SQDMLAL2, + {AArch64_SQDMLALv4i32_indexed, + ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv4i32_v2i64, ARM64_INS_SQDMLAL2, + {AArch64_SQDMLALv4i32_v2i64, + ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv8i16_indexed, ARM64_INS_SQDMLAL2, + {AArch64_SQDMLALv8i16_indexed, + ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLALv8i16_v4i32, ARM64_INS_SQDMLAL2, + {AArch64_SQDMLALv8i16_v4i32, + ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLi16, ARM64_INS_SQDMLSL, + {AArch64_SQDMLSLi16, + ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLi32, ARM64_INS_SQDMLSL, + {AArch64_SQDMLSLi32, + ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv1i32_indexed, ARM64_INS_SQDMLSL, + {AArch64_SQDMLSLv1i32_indexed, + ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv1i64_indexed, ARM64_INS_SQDMLSL, + {AArch64_SQDMLSLv1i64_indexed, + ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv2i32_indexed, ARM64_INS_SQDMLSL, + {AArch64_SQDMLSLv2i32_indexed, + ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv2i32_v2i64, ARM64_INS_SQDMLSL, + {AArch64_SQDMLSLv2i32_v2i64, + ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv4i16_indexed, ARM64_INS_SQDMLSL, + {AArch64_SQDMLSLv4i16_indexed, + ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv4i16_v4i32, ARM64_INS_SQDMLSL, + {AArch64_SQDMLSLv4i16_v4i32, + ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv4i32_indexed, ARM64_INS_SQDMLSL2, + {AArch64_SQDMLSLv4i32_indexed, + ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv4i32_v2i64, ARM64_INS_SQDMLSL2, + {AArch64_SQDMLSLv4i32_v2i64, + ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv8i16_indexed, ARM64_INS_SQDMLSL2, + {AArch64_SQDMLSLv8i16_indexed, + ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMLSLv8i16_v4i32, ARM64_INS_SQDMLSL2, + {AArch64_SQDMLSLv8i16_v4i32, + ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv1i16, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv1i16, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv1i16_indexed, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv1i16_indexed, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv1i32, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv1i32, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv1i32_indexed, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv1i32_indexed, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv2i32, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv2i32, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv2i32_indexed, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv2i32_indexed, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv4i16, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv4i16, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv4i16_indexed, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv4i16_indexed, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv4i32, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv4i32, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv4i32_indexed, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv4i32_indexed, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv8i16, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv8i16, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULHv8i16_indexed, ARM64_INS_SQDMULH, + {AArch64_SQDMULHv8i16_indexed, + ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLi16, ARM64_INS_SQDMULL, + {AArch64_SQDMULLi16, + ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLi32, ARM64_INS_SQDMULL, + {AArch64_SQDMULLi32, + ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL, + {AArch64_SQDMULLv1i32_indexed, + ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL, + {AArch64_SQDMULLv1i64_indexed, + ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL, + {AArch64_SQDMULLv2i32_indexed, + ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL, + {AArch64_SQDMULLv2i32_v2i64, + ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL, + {AArch64_SQDMULLv4i16_indexed, + ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL, + {AArch64_SQDMULLv4i16_v4i32, + ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv4i32_indexed, ARM64_INS_SQDMULL2, + {AArch64_SQDMULLv4i32_indexed, + ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv4i32_v2i64, ARM64_INS_SQDMULL2, + {AArch64_SQDMULLv4i32_v2i64, + ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv8i16_indexed, ARM64_INS_SQDMULL2, + {AArch64_SQDMULLv8i16_indexed, + ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQDMULLv8i16_v4i32, ARM64_INS_SQDMULL2, + {AArch64_SQDMULLv8i16_v4i32, + ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCB_XPiI, ARM64_INS_SQINCB, + {AArch64_SQINCB_XPiI, + ARM64_INS_SQINCB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCB_XPiWdI, ARM64_INS_SQINCB, + {AArch64_SQINCB_XPiWdI, + ARM64_INS_SQINCB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCD_XPiI, ARM64_INS_SQINCD, + {AArch64_SQINCD_XPiI, + ARM64_INS_SQINCD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCD_XPiWdI, ARM64_INS_SQINCD, + {AArch64_SQINCD_XPiWdI, + ARM64_INS_SQINCD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCD_ZPiI, ARM64_INS_SQINCD, + {AArch64_SQINCD_ZPiI, + ARM64_INS_SQINCD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCH_XPiI, ARM64_INS_SQINCH, + {AArch64_SQINCH_XPiI, + ARM64_INS_SQINCH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCH_XPiWdI, ARM64_INS_SQINCH, + {AArch64_SQINCH_XPiWdI, + ARM64_INS_SQINCH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCH_ZPiI, ARM64_INS_SQINCH, + {AArch64_SQINCH_ZPiI, + ARM64_INS_SQINCH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_XPWd_B, ARM64_INS_SQINCP, + {AArch64_SQINCP_XPWd_B, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_XPWd_D, ARM64_INS_SQINCP, + {AArch64_SQINCP_XPWd_D, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_XPWd_H, ARM64_INS_SQINCP, + {AArch64_SQINCP_XPWd_H, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_XPWd_S, ARM64_INS_SQINCP, + {AArch64_SQINCP_XPWd_S, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_XP_B, ARM64_INS_SQINCP, + {AArch64_SQINCP_XP_B, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_XP_D, ARM64_INS_SQINCP, + {AArch64_SQINCP_XP_D, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_XP_H, ARM64_INS_SQINCP, + {AArch64_SQINCP_XP_H, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_XP_S, ARM64_INS_SQINCP, + {AArch64_SQINCP_XP_S, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_ZP_D, ARM64_INS_SQINCP, + {AArch64_SQINCP_ZP_D, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_ZP_H, ARM64_INS_SQINCP, + {AArch64_SQINCP_ZP_H, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCP_ZP_S, ARM64_INS_SQINCP, + {AArch64_SQINCP_ZP_S, + ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCW_XPiI, ARM64_INS_SQINCW, + {AArch64_SQINCW_XPiI, + ARM64_INS_SQINCW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCW_XPiWdI, ARM64_INS_SQINCW, + {AArch64_SQINCW_XPiWdI, + ARM64_INS_SQINCW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQINCW_ZPiI, ARM64_INS_SQINCW, + {AArch64_SQINCW_ZPiI, + ARM64_INS_SQINCW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv16i8, ARM64_INS_SQNEG, + {AArch64_SQNEGv16i8, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv1i16, ARM64_INS_SQNEG, + {AArch64_SQNEGv1i16, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv1i32, ARM64_INS_SQNEG, + {AArch64_SQNEGv1i32, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv1i64, ARM64_INS_SQNEG, + {AArch64_SQNEGv1i64, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv1i8, ARM64_INS_SQNEG, + {AArch64_SQNEGv1i8, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv2i32, ARM64_INS_SQNEG, + {AArch64_SQNEGv2i32, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv2i64, ARM64_INS_SQNEG, + {AArch64_SQNEGv2i64, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv4i16, ARM64_INS_SQNEG, + {AArch64_SQNEGv4i16, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv4i32, ARM64_INS_SQNEG, + {AArch64_SQNEGv4i32, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv8i16, ARM64_INS_SQNEG, + {AArch64_SQNEGv8i16, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQNEGv8i8, ARM64_INS_SQNEG, + {AArch64_SQNEGv8i8, + ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHi16_indexed, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHi16_indexed, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHi32_indexed, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHi32_indexed, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv1i16, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv1i16, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv1i32, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv1i32, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv2i32, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv2i32, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv2i32_indexed, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv2i32_indexed, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv4i16, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv4i16, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv4i16_indexed, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv4i16_indexed, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv4i32, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv4i32, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv4i32_indexed, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv4i32_indexed, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv8i16, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv8i16, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLAHv8i16_indexed, ARM64_INS_SQRDMLAH, + {AArch64_SQRDMLAHv8i16_indexed, + ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHi16_indexed, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHi16_indexed, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHi32_indexed, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHi32_indexed, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv1i16, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv1i16, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv1i32, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv1i32, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv2i32, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv2i32, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv2i32_indexed, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv2i32_indexed, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv4i16, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv4i16, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv4i16_indexed, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv4i16_indexed, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv4i32, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv4i32, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv4i32_indexed, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv4i32_indexed, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv8i16, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv8i16, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMLSHv8i16_indexed, ARM64_INS_SQRDMLSH, + {AArch64_SQRDMLSHv8i16_indexed, + ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv1i16, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv1i16, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv1i16_indexed, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv1i16_indexed, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv1i32, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv1i32, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv1i32_indexed, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv1i32_indexed, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv2i32, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv2i32, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv2i32_indexed, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv2i32_indexed, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv4i16, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv4i16, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv4i16_indexed, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv4i16_indexed, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv4i32, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv4i32, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv4i32_indexed, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv4i32_indexed, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv8i16, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv8i16, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRDMULHv8i16_indexed, ARM64_INS_SQRDMULH, + {AArch64_SQRDMULHv8i16_indexed, + ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv16i8, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv16i8, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv1i16, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv1i16, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv1i32, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv1i32, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv1i64, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv1i64, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv1i8, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv1i8, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv2i32, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv2i32, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv2i64, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv2i64, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv4i16, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv4i16, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv4i32, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv4i32, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv8i16, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv8i16, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHLv8i8, ARM64_INS_SQRSHL, + {AArch64_SQRSHLv8i8, + ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRNb, ARM64_INS_SQRSHRN, + {AArch64_SQRSHRNb, + ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRNh, ARM64_INS_SQRSHRN, + {AArch64_SQRSHRNh, + ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRNs, ARM64_INS_SQRSHRN, + {AArch64_SQRSHRNs, + ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRNv16i8_shift, ARM64_INS_SQRSHRN2, + {AArch64_SQRSHRNv16i8_shift, + ARM64_INS_SQRSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRNv2i32_shift, ARM64_INS_SQRSHRN, + {AArch64_SQRSHRNv2i32_shift, + ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRNv4i16_shift, ARM64_INS_SQRSHRN, + {AArch64_SQRSHRNv4i16_shift, + ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRNv4i32_shift, ARM64_INS_SQRSHRN2, + {AArch64_SQRSHRNv4i32_shift, + ARM64_INS_SQRSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRNv8i16_shift, ARM64_INS_SQRSHRN2, + {AArch64_SQRSHRNv8i16_shift, + ARM64_INS_SQRSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRNv8i8_shift, ARM64_INS_SQRSHRN, + {AArch64_SQRSHRNv8i8_shift, + ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRUNb, ARM64_INS_SQRSHRUN, + {AArch64_SQRSHRUNb, + ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRUNh, ARM64_INS_SQRSHRUN, + {AArch64_SQRSHRUNh, + ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRUNs, ARM64_INS_SQRSHRUN, + {AArch64_SQRSHRUNs, + ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRUNv16i8_shift, ARM64_INS_SQRSHRUN2, + {AArch64_SQRSHRUNv16i8_shift, + ARM64_INS_SQRSHRUN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRUNv2i32_shift, ARM64_INS_SQRSHRUN, + {AArch64_SQRSHRUNv2i32_shift, + ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRUNv4i16_shift, ARM64_INS_SQRSHRUN, + {AArch64_SQRSHRUNv4i16_shift, + ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRUNv4i32_shift, ARM64_INS_SQRSHRUN2, + {AArch64_SQRSHRUNv4i32_shift, + ARM64_INS_SQRSHRUN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRUNv8i16_shift, ARM64_INS_SQRSHRUN2, + {AArch64_SQRSHRUNv8i16_shift, + ARM64_INS_SQRSHRUN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQRSHRUNv8i8_shift, ARM64_INS_SQRSHRUN, + {AArch64_SQRSHRUNv8i8_shift, + ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUb, ARM64_INS_SQSHLU, + {AArch64_SQSHLUb, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUd, ARM64_INS_SQSHLU, + {AArch64_SQSHLUd, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUh, ARM64_INS_SQSHLU, + {AArch64_SQSHLUh, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUs, ARM64_INS_SQSHLU, + {AArch64_SQSHLUs, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU, + {AArch64_SQSHLUv16i8_shift, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU, + {AArch64_SQSHLUv2i32_shift, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU, + {AArch64_SQSHLUv2i64_shift, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU, + {AArch64_SQSHLUv4i16_shift, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU, + {AArch64_SQSHLUv4i32_shift, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU, + {AArch64_SQSHLUv8i16_shift, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLUv8i8_shift, ARM64_INS_SQSHLU, + {AArch64_SQSHLUv8i8_shift, + ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLb, ARM64_INS_SQSHL, + {AArch64_SQSHLb, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLd, ARM64_INS_SQSHL, + {AArch64_SQSHLd, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLh, ARM64_INS_SQSHL, + {AArch64_SQSHLh, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLs, ARM64_INS_SQSHL, + {AArch64_SQSHLs, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv16i8, ARM64_INS_SQSHL, + {AArch64_SQSHLv16i8, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv16i8_shift, ARM64_INS_SQSHL, + {AArch64_SQSHLv16i8_shift, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv1i16, ARM64_INS_SQSHL, + {AArch64_SQSHLv1i16, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv1i32, ARM64_INS_SQSHL, + {AArch64_SQSHLv1i32, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv1i64, ARM64_INS_SQSHL, + {AArch64_SQSHLv1i64, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv1i8, ARM64_INS_SQSHL, + {AArch64_SQSHLv1i8, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv2i32, ARM64_INS_SQSHL, + {AArch64_SQSHLv2i32, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv2i32_shift, ARM64_INS_SQSHL, + {AArch64_SQSHLv2i32_shift, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv2i64, ARM64_INS_SQSHL, + {AArch64_SQSHLv2i64, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv2i64_shift, ARM64_INS_SQSHL, + {AArch64_SQSHLv2i64_shift, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv4i16, ARM64_INS_SQSHL, + {AArch64_SQSHLv4i16, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv4i16_shift, ARM64_INS_SQSHL, + {AArch64_SQSHLv4i16_shift, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv4i32, ARM64_INS_SQSHL, + {AArch64_SQSHLv4i32, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv4i32_shift, ARM64_INS_SQSHL, + {AArch64_SQSHLv4i32_shift, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv8i16, ARM64_INS_SQSHL, + {AArch64_SQSHLv8i16, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv8i16_shift, ARM64_INS_SQSHL, + {AArch64_SQSHLv8i16_shift, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv8i8, ARM64_INS_SQSHL, + {AArch64_SQSHLv8i8, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHLv8i8_shift, ARM64_INS_SQSHL, + {AArch64_SQSHLv8i8_shift, + ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRNb, ARM64_INS_SQSHRN, + {AArch64_SQSHRNb, + ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRNh, ARM64_INS_SQSHRN, + {AArch64_SQSHRNh, + ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRNs, ARM64_INS_SQSHRN, + {AArch64_SQSHRNs, + ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRNv16i8_shift, ARM64_INS_SQSHRN2, + {AArch64_SQSHRNv16i8_shift, + ARM64_INS_SQSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRNv2i32_shift, ARM64_INS_SQSHRN, + {AArch64_SQSHRNv2i32_shift, + ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRNv4i16_shift, ARM64_INS_SQSHRN, + {AArch64_SQSHRNv4i16_shift, + ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRNv4i32_shift, ARM64_INS_SQSHRN2, + {AArch64_SQSHRNv4i32_shift, + ARM64_INS_SQSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRNv8i16_shift, ARM64_INS_SQSHRN2, + {AArch64_SQSHRNv8i16_shift, + ARM64_INS_SQSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRNv8i8_shift, ARM64_INS_SQSHRN, + {AArch64_SQSHRNv8i8_shift, + ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRUNb, ARM64_INS_SQSHRUN, + {AArch64_SQSHRUNb, + ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRUNh, ARM64_INS_SQSHRUN, + {AArch64_SQSHRUNh, + ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRUNs, ARM64_INS_SQSHRUN, + {AArch64_SQSHRUNs, + ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRUNv16i8_shift, ARM64_INS_SQSHRUN2, + {AArch64_SQSHRUNv16i8_shift, + ARM64_INS_SQSHRUN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRUNv2i32_shift, ARM64_INS_SQSHRUN, + {AArch64_SQSHRUNv2i32_shift, + ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRUNv4i16_shift, ARM64_INS_SQSHRUN, + {AArch64_SQSHRUNv4i16_shift, + ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRUNv4i32_shift, ARM64_INS_SQSHRUN2, + {AArch64_SQSHRUNv4i32_shift, + ARM64_INS_SQSHRUN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRUNv8i16_shift, ARM64_INS_SQSHRUN2, + {AArch64_SQSHRUNv8i16_shift, + ARM64_INS_SQSHRUN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSHRUNv8i8_shift, ARM64_INS_SQSHRUN, + {AArch64_SQSHRUNv8i8_shift, + ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUB_ZI_B, ARM64_INS_SQSUB, + {AArch64_SQSUB_ZI_B, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUB_ZI_D, ARM64_INS_SQSUB, + {AArch64_SQSUB_ZI_D, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUB_ZI_H, ARM64_INS_SQSUB, + {AArch64_SQSUB_ZI_H, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUB_ZI_S, ARM64_INS_SQSUB, + {AArch64_SQSUB_ZI_S, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUB_ZZZ_B, ARM64_INS_SQSUB, + {AArch64_SQSUB_ZZZ_B, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUB_ZZZ_D, ARM64_INS_SQSUB, + {AArch64_SQSUB_ZZZ_D, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUB_ZZZ_H, ARM64_INS_SQSUB, + {AArch64_SQSUB_ZZZ_H, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUB_ZZZ_S, ARM64_INS_SQSUB, + {AArch64_SQSUB_ZZZ_S, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv16i8, ARM64_INS_SQSUB, + {AArch64_SQSUBv16i8, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv1i16, ARM64_INS_SQSUB, + {AArch64_SQSUBv1i16, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv1i32, ARM64_INS_SQSUB, + {AArch64_SQSUBv1i32, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv1i64, ARM64_INS_SQSUB, + {AArch64_SQSUBv1i64, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv1i8, ARM64_INS_SQSUB, + {AArch64_SQSUBv1i8, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv2i32, ARM64_INS_SQSUB, + {AArch64_SQSUBv2i32, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv2i64, ARM64_INS_SQSUB, + {AArch64_SQSUBv2i64, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv4i16, ARM64_INS_SQSUB, + {AArch64_SQSUBv4i16, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv4i32, ARM64_INS_SQSUB, + {AArch64_SQSUBv4i32, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv8i16, ARM64_INS_SQSUB, + {AArch64_SQSUBv8i16, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQSUBv8i8, ARM64_INS_SQSUB, + {AArch64_SQSUBv8i8, + ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTNv16i8, ARM64_INS_SQXTN2, + {AArch64_SQXTNv16i8, + ARM64_INS_SQXTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTNv1i16, ARM64_INS_SQXTN, + {AArch64_SQXTNv1i16, + ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTNv1i32, ARM64_INS_SQXTN, + {AArch64_SQXTNv1i32, + ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTNv1i8, ARM64_INS_SQXTN, + {AArch64_SQXTNv1i8, + ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTNv2i32, ARM64_INS_SQXTN, + {AArch64_SQXTNv2i32, + ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTNv4i16, ARM64_INS_SQXTN, + {AArch64_SQXTNv4i16, + ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTNv4i32, ARM64_INS_SQXTN2, + {AArch64_SQXTNv4i32, + ARM64_INS_SQXTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTNv8i16, ARM64_INS_SQXTN2, + {AArch64_SQXTNv8i16, + ARM64_INS_SQXTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTNv8i8, ARM64_INS_SQXTN, + {AArch64_SQXTNv8i8, + ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTUNv16i8, ARM64_INS_SQXTUN2, + {AArch64_SQXTUNv16i8, + ARM64_INS_SQXTUN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTUNv1i16, ARM64_INS_SQXTUN, + {AArch64_SQXTUNv1i16, + ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTUNv1i32, ARM64_INS_SQXTUN, + {AArch64_SQXTUNv1i32, + ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTUNv1i8, ARM64_INS_SQXTUN, + {AArch64_SQXTUNv1i8, + ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTUNv2i32, ARM64_INS_SQXTUN, + {AArch64_SQXTUNv2i32, + ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTUNv4i16, ARM64_INS_SQXTUN, + {AArch64_SQXTUNv4i16, + ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTUNv4i32, ARM64_INS_SQXTUN2, + {AArch64_SQXTUNv4i32, + ARM64_INS_SQXTUN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTUNv8i16, ARM64_INS_SQXTUN2, + {AArch64_SQXTUNv8i16, + ARM64_INS_SQXTUN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SQXTUNv8i8, ARM64_INS_SQXTUN, + {AArch64_SQXTUNv8i8, + ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRHADDv16i8, ARM64_INS_SRHADD, + {AArch64_SRHADDv16i8, + ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRHADDv2i32, ARM64_INS_SRHADD, + {AArch64_SRHADDv2i32, + ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRHADDv4i16, ARM64_INS_SRHADD, + {AArch64_SRHADDv4i16, + ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRHADDv4i32, ARM64_INS_SRHADD, + {AArch64_SRHADDv4i32, + ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRHADDv8i16, ARM64_INS_SRHADD, + {AArch64_SRHADDv8i16, + ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRHADDv8i8, ARM64_INS_SRHADD, + {AArch64_SRHADDv8i8, + ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRId, ARM64_INS_SRI, + {AArch64_SRId, + ARM64_INS_SRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRIv16i8_shift, ARM64_INS_SRI, + {AArch64_SRIv16i8_shift, + ARM64_INS_SRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRIv2i32_shift, ARM64_INS_SRI, + {AArch64_SRIv2i32_shift, + ARM64_INS_SRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRIv2i64_shift, ARM64_INS_SRI, + {AArch64_SRIv2i64_shift, + ARM64_INS_SRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRIv4i16_shift, ARM64_INS_SRI, + {AArch64_SRIv4i16_shift, + ARM64_INS_SRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRIv4i32_shift, ARM64_INS_SRI, + {AArch64_SRIv4i32_shift, + ARM64_INS_SRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRIv8i16_shift, ARM64_INS_SRI, + {AArch64_SRIv8i16_shift, + ARM64_INS_SRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRIv8i8_shift, ARM64_INS_SRI, + {AArch64_SRIv8i8_shift, + ARM64_INS_SRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHLv16i8, ARM64_INS_SRSHL, + {AArch64_SRSHLv16i8, + ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHLv1i64, ARM64_INS_SRSHL, + {AArch64_SRSHLv1i64, + ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHLv2i32, ARM64_INS_SRSHL, + {AArch64_SRSHLv2i32, + ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHLv2i64, ARM64_INS_SRSHL, + {AArch64_SRSHLv2i64, + ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHLv4i16, ARM64_INS_SRSHL, + {AArch64_SRSHLv4i16, + ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHLv4i32, ARM64_INS_SRSHL, + {AArch64_SRSHLv4i32, + ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHLv8i16, ARM64_INS_SRSHL, + {AArch64_SRSHLv8i16, + ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHLv8i8, ARM64_INS_SRSHL, + {AArch64_SRSHLv8i8, + ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHRd, ARM64_INS_SRSHR, + {AArch64_SRSHRd, + ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHRv16i8_shift, ARM64_INS_SRSHR, + {AArch64_SRSHRv16i8_shift, + ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHRv2i32_shift, ARM64_INS_SRSHR, + {AArch64_SRSHRv2i32_shift, + ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHRv2i64_shift, ARM64_INS_SRSHR, + {AArch64_SRSHRv2i64_shift, + ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHRv4i16_shift, ARM64_INS_SRSHR, + {AArch64_SRSHRv4i16_shift, + ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHRv4i32_shift, ARM64_INS_SRSHR, + {AArch64_SRSHRv4i32_shift, + ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHRv8i16_shift, ARM64_INS_SRSHR, + {AArch64_SRSHRv8i16_shift, + ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSHRv8i8_shift, ARM64_INS_SRSHR, + {AArch64_SRSHRv8i8_shift, + ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSRAd, ARM64_INS_SRSRA, + {AArch64_SRSRAd, + ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSRAv16i8_shift, ARM64_INS_SRSRA, + {AArch64_SRSRAv16i8_shift, + ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSRAv2i32_shift, ARM64_INS_SRSRA, + {AArch64_SRSRAv2i32_shift, + ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSRAv2i64_shift, ARM64_INS_SRSRA, + {AArch64_SRSRAv2i64_shift, + ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSRAv4i16_shift, ARM64_INS_SRSRA, + {AArch64_SRSRAv4i16_shift, + ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSRAv4i32_shift, ARM64_INS_SRSRA, + {AArch64_SRSRAv4i32_shift, + ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSRAv8i16_shift, ARM64_INS_SRSRA, + {AArch64_SRSRAv8i16_shift, + ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SRSRAv8i8_shift, ARM64_INS_SRSRA, + {AArch64_SRSRAv8i8_shift, + ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLLv16i8_shift, ARM64_INS_SSHLL2, + {AArch64_SSHLLv16i8_shift, + ARM64_INS_SSHLL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLLv2i32_shift, ARM64_INS_SSHLL, + {AArch64_SSHLLv2i32_shift, + ARM64_INS_SSHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLLv4i16_shift, ARM64_INS_SSHLL, + {AArch64_SSHLLv4i16_shift, + ARM64_INS_SSHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLLv4i32_shift, ARM64_INS_SSHLL2, + {AArch64_SSHLLv4i32_shift, + ARM64_INS_SSHLL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLLv8i16_shift, ARM64_INS_SSHLL2, + {AArch64_SSHLLv8i16_shift, + ARM64_INS_SSHLL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLLv8i8_shift, ARM64_INS_SSHLL, + {AArch64_SSHLLv8i8_shift, + ARM64_INS_SSHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLv16i8, ARM64_INS_SSHL, + {AArch64_SSHLv16i8, + ARM64_INS_SSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLv1i64, ARM64_INS_SSHL, + {AArch64_SSHLv1i64, + ARM64_INS_SSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLv2i32, ARM64_INS_SSHL, + {AArch64_SSHLv2i32, + ARM64_INS_SSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLv2i64, ARM64_INS_SSHL, + {AArch64_SSHLv2i64, + ARM64_INS_SSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLv4i16, ARM64_INS_SSHL, + {AArch64_SSHLv4i16, + ARM64_INS_SSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLv4i32, ARM64_INS_SSHL, + {AArch64_SSHLv4i32, + ARM64_INS_SSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLv8i16, ARM64_INS_SSHL, + {AArch64_SSHLv8i16, + ARM64_INS_SSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHLv8i8, ARM64_INS_SSHL, + {AArch64_SSHLv8i8, + ARM64_INS_SSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHRd, ARM64_INS_SSHR, + {AArch64_SSHRd, + ARM64_INS_SSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHRv16i8_shift, ARM64_INS_SSHR, + {AArch64_SSHRv16i8_shift, + ARM64_INS_SSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHRv2i32_shift, ARM64_INS_SSHR, + {AArch64_SSHRv2i32_shift, + ARM64_INS_SSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHRv2i64_shift, ARM64_INS_SSHR, + {AArch64_SSHRv2i64_shift, + ARM64_INS_SSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHRv4i16_shift, ARM64_INS_SSHR, + {AArch64_SSHRv4i16_shift, + ARM64_INS_SSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHRv4i32_shift, ARM64_INS_SSHR, + {AArch64_SSHRv4i32_shift, + ARM64_INS_SSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHRv8i16_shift, ARM64_INS_SSHR, + {AArch64_SSHRv8i16_shift, + ARM64_INS_SSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSHRv8i8_shift, ARM64_INS_SSHR, + {AArch64_SSHRv8i8_shift, + ARM64_INS_SSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSRAd, ARM64_INS_SSRA, + {AArch64_SSRAd, + ARM64_INS_SSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSRAv16i8_shift, ARM64_INS_SSRA, + {AArch64_SSRAv16i8_shift, + ARM64_INS_SSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSRAv2i32_shift, ARM64_INS_SSRA, + {AArch64_SSRAv2i32_shift, + ARM64_INS_SSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSRAv2i64_shift, ARM64_INS_SSRA, + {AArch64_SSRAv2i64_shift, + ARM64_INS_SSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSRAv4i16_shift, ARM64_INS_SSRA, + {AArch64_SSRAv4i16_shift, + ARM64_INS_SSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSRAv4i32_shift, ARM64_INS_SSRA, + {AArch64_SSRAv4i32_shift, + ARM64_INS_SSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSRAv8i16_shift, ARM64_INS_SSRA, + {AArch64_SSRAv8i16_shift, + ARM64_INS_SSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSRAv8i8_shift, ARM64_INS_SSRA, + {AArch64_SSRAv8i8_shift, + ARM64_INS_SSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1B_D, ARM64_INS_ST1B, + {AArch64_SST1B_D_REAL, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1B_D_IMM, ARM64_INS_ST1B, + {AArch64_SST1B_D_IMM, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1B_D_SXTW, ARM64_INS_ST1B, + {AArch64_SST1B_D_SXTW, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1B_D_UXTW, ARM64_INS_ST1B, + {AArch64_SST1B_D_UXTW, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1B_S_IMM, ARM64_INS_ST1B, + {AArch64_SST1B_S_IMM, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1B_S_SXTW, ARM64_INS_ST1B, + {AArch64_SST1B_S_SXTW, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1B_S_UXTW, ARM64_INS_ST1B, + {AArch64_SST1B_S_UXTW, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1D, ARM64_INS_ST1D, + {AArch64_SST1D_REAL, + ARM64_INS_ST1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1D_IMM, ARM64_INS_ST1D, + {AArch64_SST1D_IMM, + ARM64_INS_ST1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1D_SCALED, ARM64_INS_ST1D, + {AArch64_SST1D_SCALED_SCALED_REAL, + ARM64_INS_ST1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1D_SXTW, ARM64_INS_ST1D, + {AArch64_SST1D_SXTW, + ARM64_INS_ST1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1D_SXTW_SCALED, ARM64_INS_ST1D, + {AArch64_SST1D_SXTW_SCALED, + ARM64_INS_ST1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1D_UXTW, ARM64_INS_ST1D, + {AArch64_SST1D_UXTW, + ARM64_INS_ST1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1D_UXTW_SCALED, ARM64_INS_ST1D, + {AArch64_SST1D_UXTW_SCALED, + ARM64_INS_ST1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_D, ARM64_INS_ST1H, + {AArch64_SST1H_D_REAL, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_D_IMM, ARM64_INS_ST1H, + {AArch64_SST1H_D_IMM, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_D_SCALED, ARM64_INS_ST1H, + {AArch64_SST1H_D_SCALED_SCALED_REAL, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_D_SXTW, ARM64_INS_ST1H, + {AArch64_SST1H_D_SXTW, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_D_SXTW_SCALED, ARM64_INS_ST1H, + {AArch64_SST1H_D_SXTW_SCALED, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_D_UXTW, ARM64_INS_ST1H, + {AArch64_SST1H_D_UXTW, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_D_UXTW_SCALED, ARM64_INS_ST1H, + {AArch64_SST1H_D_UXTW_SCALED, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_S_IMM, ARM64_INS_ST1H, + {AArch64_SST1H_S_IMM, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_S_SXTW, ARM64_INS_ST1H, + {AArch64_SST1H_S_SXTW, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_S_SXTW_SCALED, ARM64_INS_ST1H, + {AArch64_SST1H_S_SXTW_SCALED, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_S_UXTW, ARM64_INS_ST1H, + {AArch64_SST1H_S_UXTW, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1H_S_UXTW_SCALED, ARM64_INS_ST1H, + {AArch64_SST1H_S_UXTW_SCALED, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_D, ARM64_INS_ST1W, + {AArch64_SST1W_D_REAL, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_D_IMM, ARM64_INS_ST1W, + {AArch64_SST1W_D_IMM, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_D_SCALED, ARM64_INS_ST1W, + {AArch64_SST1W_D_SCALED_SCALED_REAL, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_D_SXTW, ARM64_INS_ST1W, + {AArch64_SST1W_D_SXTW, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_D_SXTW_SCALED, ARM64_INS_ST1W, + {AArch64_SST1W_D_SXTW_SCALED, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_D_UXTW, ARM64_INS_ST1W, + {AArch64_SST1W_D_UXTW, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_D_UXTW_SCALED, ARM64_INS_ST1W, + {AArch64_SST1W_D_UXTW_SCALED, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_IMM, ARM64_INS_ST1W, + {AArch64_SST1W_IMM, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_SXTW, ARM64_INS_ST1W, + {AArch64_SST1W_SXTW, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_SXTW_SCALED, ARM64_INS_ST1W, + {AArch64_SST1W_SXTW_SCALED, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_UXTW, ARM64_INS_ST1W, + {AArch64_SST1W_UXTW, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SST1W_UXTW_SCALED, ARM64_INS_ST1W, + {AArch64_SST1W_UXTW_SCALED, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBLv16i8_v8i16, ARM64_INS_SSUBL2, + {AArch64_SSUBLv16i8_v8i16, + ARM64_INS_SSUBL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBLv2i32_v2i64, ARM64_INS_SSUBL, + {AArch64_SSUBLv2i32_v2i64, + ARM64_INS_SSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBLv4i16_v4i32, ARM64_INS_SSUBL, + {AArch64_SSUBLv4i16_v4i32, + ARM64_INS_SSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBLv4i32_v2i64, ARM64_INS_SSUBL2, + {AArch64_SSUBLv4i32_v2i64, + ARM64_INS_SSUBL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBLv8i16_v4i32, ARM64_INS_SSUBL2, + {AArch64_SSUBLv8i16_v4i32, + ARM64_INS_SSUBL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBLv8i8_v8i16, ARM64_INS_SSUBL, + {AArch64_SSUBLv8i8_v8i16, + ARM64_INS_SSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2, + {AArch64_SSUBWv16i8_v8i16, + ARM64_INS_SSUBW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBWv2i32_v2i64, ARM64_INS_SSUBW, + {AArch64_SSUBWv2i32_v2i64, + ARM64_INS_SSUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBWv4i16_v4i32, ARM64_INS_SSUBW, + {AArch64_SSUBWv4i16_v4i32, + ARM64_INS_SSUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2, + {AArch64_SSUBWv4i32_v2i64, + ARM64_INS_SSUBW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2, + {AArch64_SSUBWv8i16_v4i32, + ARM64_INS_SSUBW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SSUBWv8i8_v8i16, ARM64_INS_SSUBW, + {AArch64_SSUBWv8i8_v8i16, + ARM64_INS_SSUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1B, ARM64_INS_ST1B, + {AArch64_ST1B, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1B_D, ARM64_INS_ST1B, + {AArch64_ST1B_D, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1B_D_IMM, ARM64_INS_ST1B, + {AArch64_ST1B_D_IMM, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1B_H, ARM64_INS_ST1B, + {AArch64_ST1B_H, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1B_H_IMM, ARM64_INS_ST1B, + {AArch64_ST1B_H_IMM, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1B_IMM, ARM64_INS_ST1B, + {AArch64_ST1B_IMM, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1B_S, ARM64_INS_ST1B, + {AArch64_ST1B_S, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1B_S_IMM, ARM64_INS_ST1B, + {AArch64_ST1B_S_IMM, + ARM64_INS_ST1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1D, ARM64_INS_ST1D, + {AArch64_ST1D, + ARM64_INS_ST1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1D_IMM, ARM64_INS_ST1D, + {AArch64_ST1D_IMM, + ARM64_INS_ST1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv16b, ARM64_INS_ST1, + {AArch64_ST1Fourv16b, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv16b_POST, ARM64_INS_ST1, + {AArch64_ST1Fourv16b_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv1d, ARM64_INS_ST1, + {AArch64_ST1Fourv1d, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv1d_POST, ARM64_INS_ST1, + {AArch64_ST1Fourv1d_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv2d, ARM64_INS_ST1, + {AArch64_ST1Fourv2d, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv2d_POST, ARM64_INS_ST1, + {AArch64_ST1Fourv2d_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv2s, ARM64_INS_ST1, + {AArch64_ST1Fourv2s, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv2s_POST, ARM64_INS_ST1, + {AArch64_ST1Fourv2s_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv4h, ARM64_INS_ST1, + {AArch64_ST1Fourv4h, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv4h_POST, ARM64_INS_ST1, + {AArch64_ST1Fourv4h_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv4s, ARM64_INS_ST1, + {AArch64_ST1Fourv4s, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv4s_POST, ARM64_INS_ST1, + {AArch64_ST1Fourv4s_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv8b, ARM64_INS_ST1, + {AArch64_ST1Fourv8b, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv8b_POST, ARM64_INS_ST1, + {AArch64_ST1Fourv8b_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv8h, ARM64_INS_ST1, + {AArch64_ST1Fourv8h, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Fourv8h_POST, ARM64_INS_ST1, + {AArch64_ST1Fourv8h_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1H, ARM64_INS_ST1H, + {AArch64_ST1H, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1H_D, ARM64_INS_ST1H, + {AArch64_ST1H_D, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1H_D_IMM, ARM64_INS_ST1H, + {AArch64_ST1H_D_IMM, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1H_IMM, ARM64_INS_ST1H, + {AArch64_ST1H_IMM, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1H_S, ARM64_INS_ST1H, + {AArch64_ST1H_S, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1H_S_IMM, ARM64_INS_ST1H, + {AArch64_ST1H_S_IMM, + ARM64_INS_ST1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev16b, ARM64_INS_ST1, + {AArch64_ST1Onev16b, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev16b_POST, ARM64_INS_ST1, + {AArch64_ST1Onev16b_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev1d, ARM64_INS_ST1, + {AArch64_ST1Onev1d, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev1d_POST, ARM64_INS_ST1, + {AArch64_ST1Onev1d_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev2d, ARM64_INS_ST1, + {AArch64_ST1Onev2d, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev2d_POST, ARM64_INS_ST1, + {AArch64_ST1Onev2d_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev2s, ARM64_INS_ST1, + {AArch64_ST1Onev2s, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev2s_POST, ARM64_INS_ST1, + {AArch64_ST1Onev2s_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev4h, ARM64_INS_ST1, + {AArch64_ST1Onev4h, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev4h_POST, ARM64_INS_ST1, + {AArch64_ST1Onev4h_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev4s, ARM64_INS_ST1, + {AArch64_ST1Onev4s, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev4s_POST, ARM64_INS_ST1, + {AArch64_ST1Onev4s_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev8b, ARM64_INS_ST1, + {AArch64_ST1Onev8b, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev8b_POST, ARM64_INS_ST1, + {AArch64_ST1Onev8b_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev8h, ARM64_INS_ST1, + {AArch64_ST1Onev8h, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Onev8h_POST, ARM64_INS_ST1, + {AArch64_ST1Onev8h_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev16b, ARM64_INS_ST1, + {AArch64_ST1Threev16b, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev16b_POST, ARM64_INS_ST1, + {AArch64_ST1Threev16b_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev1d, ARM64_INS_ST1, + {AArch64_ST1Threev1d, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev1d_POST, ARM64_INS_ST1, + {AArch64_ST1Threev1d_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev2d, ARM64_INS_ST1, + {AArch64_ST1Threev2d, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev2d_POST, ARM64_INS_ST1, + {AArch64_ST1Threev2d_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev2s, ARM64_INS_ST1, + {AArch64_ST1Threev2s, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev2s_POST, ARM64_INS_ST1, + {AArch64_ST1Threev2s_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev4h, ARM64_INS_ST1, + {AArch64_ST1Threev4h, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev4h_POST, ARM64_INS_ST1, + {AArch64_ST1Threev4h_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev4s, ARM64_INS_ST1, + {AArch64_ST1Threev4s, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev4s_POST, ARM64_INS_ST1, + {AArch64_ST1Threev4s_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev8b, ARM64_INS_ST1, + {AArch64_ST1Threev8b, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev8b_POST, ARM64_INS_ST1, + {AArch64_ST1Threev8b_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev8h, ARM64_INS_ST1, + {AArch64_ST1Threev8h, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Threev8h_POST, ARM64_INS_ST1, + {AArch64_ST1Threev8h_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov16b, ARM64_INS_ST1, + {AArch64_ST1Twov16b, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov16b_POST, ARM64_INS_ST1, + {AArch64_ST1Twov16b_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov1d, ARM64_INS_ST1, + {AArch64_ST1Twov1d, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov1d_POST, ARM64_INS_ST1, + {AArch64_ST1Twov1d_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov2d, ARM64_INS_ST1, + {AArch64_ST1Twov2d, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov2d_POST, ARM64_INS_ST1, + {AArch64_ST1Twov2d_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov2s, ARM64_INS_ST1, + {AArch64_ST1Twov2s, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov2s_POST, ARM64_INS_ST1, + {AArch64_ST1Twov2s_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov4h, ARM64_INS_ST1, + {AArch64_ST1Twov4h, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov4h_POST, ARM64_INS_ST1, + {AArch64_ST1Twov4h_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov4s, ARM64_INS_ST1, + {AArch64_ST1Twov4s, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov4s_POST, ARM64_INS_ST1, + {AArch64_ST1Twov4s_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov8b, ARM64_INS_ST1, + {AArch64_ST1Twov8b, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov8b_POST, ARM64_INS_ST1, + {AArch64_ST1Twov8b_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov8h, ARM64_INS_ST1, + {AArch64_ST1Twov8h, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1Twov8h_POST, ARM64_INS_ST1, + {AArch64_ST1Twov8h_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1W, ARM64_INS_ST1W, + {AArch64_ST1W, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1W_D, ARM64_INS_ST1W, + {AArch64_ST1W_D, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1W_D_IMM, ARM64_INS_ST1W, + {AArch64_ST1W_D_IMM, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1W_IMM, ARM64_INS_ST1W, + {AArch64_ST1W_IMM, + ARM64_INS_ST1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1i16, ARM64_INS_ST1, + {AArch64_ST1i16, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1i16_POST, ARM64_INS_ST1, + {AArch64_ST1i16_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1i32, ARM64_INS_ST1, + {AArch64_ST1i32, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1i32_POST, ARM64_INS_ST1, + {AArch64_ST1i32_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1i64, ARM64_INS_ST1, + {AArch64_ST1i64, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1i64_POST, ARM64_INS_ST1, + {AArch64_ST1i64_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1i8, ARM64_INS_ST1, + {AArch64_ST1i8, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST1i8_POST, ARM64_INS_ST1, + {AArch64_ST1i8_POST, + ARM64_INS_ST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2B, ARM64_INS_ST2B, + {AArch64_ST2B, + ARM64_INS_ST2B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2B_IMM, ARM64_INS_ST2B, + {AArch64_ST2B_IMM, + ARM64_INS_ST2B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2D, ARM64_INS_ST2D, + {AArch64_ST2D, + ARM64_INS_ST2D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2D_IMM, ARM64_INS_ST2D, + {AArch64_ST2D_IMM, + ARM64_INS_ST2D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2H, ARM64_INS_ST2H, + {AArch64_ST2H, + ARM64_INS_ST2H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2H_IMM, ARM64_INS_ST2H, + {AArch64_ST2H_IMM, + ARM64_INS_ST2H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov16b, ARM64_INS_ST2, + {AArch64_ST2Twov16b, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov16b_POST, ARM64_INS_ST2, + {AArch64_ST2Twov16b_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov2d, ARM64_INS_ST2, + {AArch64_ST2Twov2d, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov2d_POST, ARM64_INS_ST2, + {AArch64_ST2Twov2d_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov2s, ARM64_INS_ST2, + {AArch64_ST2Twov2s, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov2s_POST, ARM64_INS_ST2, + {AArch64_ST2Twov2s_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov4h, ARM64_INS_ST2, + {AArch64_ST2Twov4h, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov4h_POST, ARM64_INS_ST2, + {AArch64_ST2Twov4h_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov4s, ARM64_INS_ST2, + {AArch64_ST2Twov4s, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov4s_POST, ARM64_INS_ST2, + {AArch64_ST2Twov4s_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov8b, ARM64_INS_ST2, + {AArch64_ST2Twov8b, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov8b_POST, ARM64_INS_ST2, + {AArch64_ST2Twov8b_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov8h, ARM64_INS_ST2, + {AArch64_ST2Twov8h, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2Twov8h_POST, ARM64_INS_ST2, + {AArch64_ST2Twov8h_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2W, ARM64_INS_ST2W, + {AArch64_ST2W, + ARM64_INS_ST2W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2W_IMM, ARM64_INS_ST2W, + {AArch64_ST2W_IMM, + ARM64_INS_ST2W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2i16, ARM64_INS_ST2, + {AArch64_ST2i16, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2i16_POST, ARM64_INS_ST2, + {AArch64_ST2i16_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2i32, ARM64_INS_ST2, + {AArch64_ST2i32, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2i32_POST, ARM64_INS_ST2, + {AArch64_ST2i32_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2i64, ARM64_INS_ST2, + {AArch64_ST2i64, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2i64_POST, ARM64_INS_ST2, + {AArch64_ST2i64_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2i8, ARM64_INS_ST2, + {AArch64_ST2i8, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST2i8_POST, ARM64_INS_ST2, + {AArch64_ST2i8_POST, + ARM64_INS_ST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3B, ARM64_INS_ST3B, + {AArch64_ST3B, + ARM64_INS_ST3B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3B_IMM, ARM64_INS_ST3B, + {AArch64_ST3B_IMM, + ARM64_INS_ST3B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3D, ARM64_INS_ST3D, + {AArch64_ST3D, + ARM64_INS_ST3D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3D_IMM, ARM64_INS_ST3D, + {AArch64_ST3D_IMM, + ARM64_INS_ST3D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3H, ARM64_INS_ST3H, + {AArch64_ST3H, + ARM64_INS_ST3H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3H_IMM, ARM64_INS_ST3H, + {AArch64_ST3H_IMM, + ARM64_INS_ST3H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev16b, ARM64_INS_ST3, + {AArch64_ST3Threev16b, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev16b_POST, ARM64_INS_ST3, + {AArch64_ST3Threev16b_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev2d, ARM64_INS_ST3, + {AArch64_ST3Threev2d, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev2d_POST, ARM64_INS_ST3, + {AArch64_ST3Threev2d_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev2s, ARM64_INS_ST3, + {AArch64_ST3Threev2s, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev2s_POST, ARM64_INS_ST3, + {AArch64_ST3Threev2s_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev4h, ARM64_INS_ST3, + {AArch64_ST3Threev4h, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev4h_POST, ARM64_INS_ST3, + {AArch64_ST3Threev4h_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev4s, ARM64_INS_ST3, + {AArch64_ST3Threev4s, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev4s_POST, ARM64_INS_ST3, + {AArch64_ST3Threev4s_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev8b, ARM64_INS_ST3, + {AArch64_ST3Threev8b, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev8b_POST, ARM64_INS_ST3, + {AArch64_ST3Threev8b_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev8h, ARM64_INS_ST3, + {AArch64_ST3Threev8h, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3Threev8h_POST, ARM64_INS_ST3, + {AArch64_ST3Threev8h_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3W, ARM64_INS_ST3W, + {AArch64_ST3W, + ARM64_INS_ST3W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3W_IMM, ARM64_INS_ST3W, + {AArch64_ST3W_IMM, + ARM64_INS_ST3W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3i16, ARM64_INS_ST3, + {AArch64_ST3i16, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3i16_POST, ARM64_INS_ST3, + {AArch64_ST3i16_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3i32, ARM64_INS_ST3, + {AArch64_ST3i32, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3i32_POST, ARM64_INS_ST3, + {AArch64_ST3i32_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3i64, ARM64_INS_ST3, + {AArch64_ST3i64, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3i64_POST, ARM64_INS_ST3, + {AArch64_ST3i64_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3i8, ARM64_INS_ST3, + {AArch64_ST3i8, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST3i8_POST, ARM64_INS_ST3, + {AArch64_ST3i8_POST, + ARM64_INS_ST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4B, ARM64_INS_ST4B, + {AArch64_ST4B, + ARM64_INS_ST4B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4B_IMM, ARM64_INS_ST4B, + {AArch64_ST4B_IMM, + ARM64_INS_ST4B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4D, ARM64_INS_ST4D, + {AArch64_ST4D, + ARM64_INS_ST4D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4D_IMM, ARM64_INS_ST4D, + {AArch64_ST4D_IMM, + ARM64_INS_ST4D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv16b, ARM64_INS_ST4, + {AArch64_ST4Fourv16b, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv16b_POST, ARM64_INS_ST4, + {AArch64_ST4Fourv16b_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv2d, ARM64_INS_ST4, + {AArch64_ST4Fourv2d, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv2d_POST, ARM64_INS_ST4, + {AArch64_ST4Fourv2d_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv2s, ARM64_INS_ST4, + {AArch64_ST4Fourv2s, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv2s_POST, ARM64_INS_ST4, + {AArch64_ST4Fourv2s_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv4h, ARM64_INS_ST4, + {AArch64_ST4Fourv4h, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv4h_POST, ARM64_INS_ST4, + {AArch64_ST4Fourv4h_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv4s, ARM64_INS_ST4, + {AArch64_ST4Fourv4s, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv4s_POST, ARM64_INS_ST4, + {AArch64_ST4Fourv4s_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv8b, ARM64_INS_ST4, + {AArch64_ST4Fourv8b, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv8b_POST, ARM64_INS_ST4, + {AArch64_ST4Fourv8b_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv8h, ARM64_INS_ST4, + {AArch64_ST4Fourv8h, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4Fourv8h_POST, ARM64_INS_ST4, + {AArch64_ST4Fourv8h_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4H, ARM64_INS_ST4H, + {AArch64_ST4H, + ARM64_INS_ST4H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4H_IMM, ARM64_INS_ST4H, + {AArch64_ST4H_IMM, + ARM64_INS_ST4H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4W, ARM64_INS_ST4W, + {AArch64_ST4W, + ARM64_INS_ST4W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4W_IMM, ARM64_INS_ST4W, + {AArch64_ST4W_IMM, + ARM64_INS_ST4W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4i16, ARM64_INS_ST4, + {AArch64_ST4i16, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4i16_POST, ARM64_INS_ST4, + {AArch64_ST4i16_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4i32, ARM64_INS_ST4, + {AArch64_ST4i32, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4i32_POST, ARM64_INS_ST4, + {AArch64_ST4i32_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4i64, ARM64_INS_ST4, + {AArch64_ST4i64, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4i64_POST, ARM64_INS_ST4, + {AArch64_ST4i64_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4i8, ARM64_INS_ST4, + {AArch64_ST4i8, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ST4i8_POST, ARM64_INS_ST4, + {AArch64_ST4i8_POST, + ARM64_INS_ST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLLRB, ARM64_INS_STLLRB, + {AArch64_STLLRB, + ARM64_INS_STLLRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLLRH, ARM64_INS_STLLRH, + {AArch64_STLLRH, + ARM64_INS_STLLRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLLRW, ARM64_INS_STLLR, + {AArch64_STLLRW, + ARM64_INS_STLLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLLRX, ARM64_INS_STLLR, + {AArch64_STLLRX, + ARM64_INS_STLLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLRB, ARM64_INS_STLRB, + {AArch64_STLRB, + ARM64_INS_STLRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLRH, ARM64_INS_STLRH, + {AArch64_STLRH, + ARM64_INS_STLRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLRW, ARM64_INS_STLR, + {AArch64_STLRW, + ARM64_INS_STLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLRX, ARM64_INS_STLR, + {AArch64_STLRX, + ARM64_INS_STLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLURBi, ARM64_INS_STLURB, + {AArch64_STLURBi, + ARM64_INS_STLURB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLURHi, ARM64_INS_STLURH, + {AArch64_STLURHi, + ARM64_INS_STLURH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLURWi, ARM64_INS_STLUR, + {AArch64_STLURWi, + ARM64_INS_STLUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLURXi, ARM64_INS_STLUR, + {AArch64_STLURXi, + ARM64_INS_STLUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLXPW, ARM64_INS_STLXP, + {AArch64_STLXPW, + ARM64_INS_STLXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLXPX, ARM64_INS_STLXP, + {AArch64_STLXPX, + ARM64_INS_STLXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLXRB, ARM64_INS_STLXRB, + {AArch64_STLXRB, + ARM64_INS_STLXRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLXRH, ARM64_INS_STLXRH, + {AArch64_STLXRH, + ARM64_INS_STLXRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLXRW, ARM64_INS_STLXR, + {AArch64_STLXRW, + ARM64_INS_STLXR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STLXRX, ARM64_INS_STLXR, + {AArch64_STLXRX, + ARM64_INS_STLXR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNPDi, ARM64_INS_STNP, + {AArch64_STNPDi, + ARM64_INS_STNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNPQi, ARM64_INS_STNP, + {AArch64_STNPQi, + ARM64_INS_STNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNPSi, ARM64_INS_STNP, + {AArch64_STNPSi, + ARM64_INS_STNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNPWi, ARM64_INS_STNP, + {AArch64_STNPWi, + ARM64_INS_STNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNPXi, ARM64_INS_STNP, + {AArch64_STNPXi, + ARM64_INS_STNP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNT1B_ZRI, ARM64_INS_STNT1B, + {AArch64_STNT1B_ZRI, + ARM64_INS_STNT1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNT1B_ZRR, ARM64_INS_STNT1B, + {AArch64_STNT1B_ZRR, + ARM64_INS_STNT1B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNT1D_ZRI, ARM64_INS_STNT1D, + {AArch64_STNT1D_ZRI, + ARM64_INS_STNT1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNT1D_ZRR, ARM64_INS_STNT1D, + {AArch64_STNT1D_ZRR, + ARM64_INS_STNT1D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNT1H_ZRI, ARM64_INS_STNT1H, + {AArch64_STNT1H_ZRI, + ARM64_INS_STNT1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNT1H_ZRR, ARM64_INS_STNT1H, + {AArch64_STNT1H_ZRR, + ARM64_INS_STNT1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNT1W_ZRI, ARM64_INS_STNT1W, + {AArch64_STNT1W_ZRI, + ARM64_INS_STNT1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STNT1W_ZRR, ARM64_INS_STNT1W, + {AArch64_STNT1W_ZRR, + ARM64_INS_STNT1W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPDi, ARM64_INS_STP, + {AArch64_STPDi, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPDpost, ARM64_INS_STP, + {AArch64_STPDpost, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPDpre, ARM64_INS_STP, + {AArch64_STPDpre, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPQi, ARM64_INS_STP, + {AArch64_STPQi, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPQpost, ARM64_INS_STP, + {AArch64_STPQpost, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPQpre, ARM64_INS_STP, + {AArch64_STPQpre, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPSi, ARM64_INS_STP, + {AArch64_STPSi, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPSpost, ARM64_INS_STP, + {AArch64_STPSpost, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPSpre, ARM64_INS_STP, + {AArch64_STPSpre, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPWi, ARM64_INS_STP, + {AArch64_STPWi, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPWpost, ARM64_INS_STP, + {AArch64_STPWpost, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPWpre, ARM64_INS_STP, + {AArch64_STPWpre, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPXi, ARM64_INS_STP, + {AArch64_STPXi, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPXpost, ARM64_INS_STP, + {AArch64_STPXpost, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STPXpre, ARM64_INS_STP, + {AArch64_STPXpre, + ARM64_INS_STP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBBpost, ARM64_INS_STRB, + {AArch64_STRBBpost, + ARM64_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBBpre, ARM64_INS_STRB, + {AArch64_STRBBpre, + ARM64_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBBroW, ARM64_INS_STRB, + {AArch64_STRBBroW, + ARM64_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBBroX, ARM64_INS_STRB, + {AArch64_STRBBroX, + ARM64_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBBui, ARM64_INS_STRB, + {AArch64_STRBBui, + ARM64_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBpost, ARM64_INS_STR, + {AArch64_STRBpost, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBpre, ARM64_INS_STR, + {AArch64_STRBpre, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBroW, ARM64_INS_STR, + {AArch64_STRBroW, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBroX, ARM64_INS_STR, + {AArch64_STRBroX, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRBui, ARM64_INS_STR, + {AArch64_STRBui, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRDpost, ARM64_INS_STR, + {AArch64_STRDpost, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRDpre, ARM64_INS_STR, + {AArch64_STRDpre, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRDroW, ARM64_INS_STR, + {AArch64_STRDroW, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRDroX, ARM64_INS_STR, + {AArch64_STRDroX, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRDui, ARM64_INS_STR, + {AArch64_STRDui, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHHpost, ARM64_INS_STRH, + {AArch64_STRHHpost, + ARM64_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHHpre, ARM64_INS_STRH, + {AArch64_STRHHpre, + ARM64_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHHroW, ARM64_INS_STRH, + {AArch64_STRHHroW, + ARM64_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHHroX, ARM64_INS_STRH, + {AArch64_STRHHroX, + ARM64_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHHui, ARM64_INS_STRH, + {AArch64_STRHHui, + ARM64_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHpost, ARM64_INS_STR, + {AArch64_STRHpost, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHpre, ARM64_INS_STR, + {AArch64_STRHpre, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHroW, ARM64_INS_STR, + {AArch64_STRHroW, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHroX, ARM64_INS_STR, + {AArch64_STRHroX, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRHui, ARM64_INS_STR, + {AArch64_STRHui, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRQpost, ARM64_INS_STR, + {AArch64_STRQpost, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRQpre, ARM64_INS_STR, + {AArch64_STRQpre, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRQroW, ARM64_INS_STR, + {AArch64_STRQroW, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRQroX, ARM64_INS_STR, + {AArch64_STRQroX, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRQui, ARM64_INS_STR, + {AArch64_STRQui, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRSpost, ARM64_INS_STR, + {AArch64_STRSpost, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRSpre, ARM64_INS_STR, + {AArch64_STRSpre, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRSroW, ARM64_INS_STR, + {AArch64_STRSroW, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRSroX, ARM64_INS_STR, + {AArch64_STRSroX, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRSui, ARM64_INS_STR, + {AArch64_STRSui, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRWpost, ARM64_INS_STR, + {AArch64_STRWpost, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRWpre, ARM64_INS_STR, + {AArch64_STRWpre, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRWroW, ARM64_INS_STR, + {AArch64_STRWroW, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRWroX, ARM64_INS_STR, + {AArch64_STRWroX, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRWui, ARM64_INS_STR, + {AArch64_STRWui, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRXpost, ARM64_INS_STR, + {AArch64_STRXpost, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRXpre, ARM64_INS_STR, + {AArch64_STRXpre, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRXroW, ARM64_INS_STR, + {AArch64_STRXroW, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRXroX, ARM64_INS_STR, + {AArch64_STRXroX, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STRXui, ARM64_INS_STR, + {AArch64_STRXui, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STR_PXI, ARM64_INS_STR, + {AArch64_STR_PXI, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STR_ZXI, ARM64_INS_STR, + {AArch64_STR_ZXI, + ARM64_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STTRBi, ARM64_INS_STTRB, + {AArch64_STTRBi, + ARM64_INS_STTRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STTRHi, ARM64_INS_STTRH, + {AArch64_STTRHi, + ARM64_INS_STTRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STTRWi, ARM64_INS_STTR, + {AArch64_STTRWi, + ARM64_INS_STTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STTRXi, ARM64_INS_STTR, + {AArch64_STTRXi, + ARM64_INS_STTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STURBBi, ARM64_INS_STURB, + {AArch64_STURBBi, + ARM64_INS_STURB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STURBi, ARM64_INS_STUR, + {AArch64_STURBi, + ARM64_INS_STUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STURDi, ARM64_INS_STUR, + {AArch64_STURDi, + ARM64_INS_STUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STURHHi, ARM64_INS_STURH, + {AArch64_STURHHi, + ARM64_INS_STURH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STURHi, ARM64_INS_STUR, + {AArch64_STURHi, + ARM64_INS_STUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STURQi, ARM64_INS_STUR, + {AArch64_STURQi, + ARM64_INS_STUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STURSi, ARM64_INS_STUR, + {AArch64_STURSi, + ARM64_INS_STUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STURWi, ARM64_INS_STUR, + {AArch64_STURWi, + ARM64_INS_STUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STURXi, ARM64_INS_STUR, + {AArch64_STURXi, + ARM64_INS_STUR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STXPW, ARM64_INS_STXP, + {AArch64_STXPW, + ARM64_INS_STXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STXPX, ARM64_INS_STXP, + {AArch64_STXPX, + ARM64_INS_STXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STXRB, ARM64_INS_STXRB, + {AArch64_STXRB, + ARM64_INS_STXRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STXRH, ARM64_INS_STXRH, + {AArch64_STXRH, + ARM64_INS_STXRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STXRW, ARM64_INS_STXR, + {AArch64_STXRW, + ARM64_INS_STXR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_STXRX, ARM64_INS_STXR, + {AArch64_STXRX, + ARM64_INS_STXR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN, + {AArch64_SUBHNv2i64_v2i32, + ARM64_INS_SUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBHNv2i64_v4i32, ARM64_INS_SUBHN2, + {AArch64_SUBHNv2i64_v4i32, + ARM64_INS_SUBHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN, + {AArch64_SUBHNv4i32_v4i16, + ARM64_INS_SUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBHNv4i32_v8i16, ARM64_INS_SUBHN2, + {AArch64_SUBHNv4i32_v8i16, + ARM64_INS_SUBHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBHNv8i16_v16i8, ARM64_INS_SUBHN2, + {AArch64_SUBHNv8i16_v16i8, + ARM64_INS_SUBHN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN, + {AArch64_SUBHNv8i16_v8i8, + ARM64_INS_SUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBR_ZI_B, ARM64_INS_SUBR, + {AArch64_SUBR_ZI_B, + ARM64_INS_SUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBR_ZI_D, ARM64_INS_SUBR, + {AArch64_SUBR_ZI_D, + ARM64_INS_SUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBR_ZI_H, ARM64_INS_SUBR, + {AArch64_SUBR_ZI_H, + ARM64_INS_SUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBR_ZI_S, ARM64_INS_SUBR, + {AArch64_SUBR_ZI_S, + ARM64_INS_SUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBR_ZPmZ_B, ARM64_INS_SUBR, + {AArch64_SUBR_ZPmZ_B, + ARM64_INS_SUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBR_ZPmZ_D, ARM64_INS_SUBR, + {AArch64_SUBR_ZPmZ_D, + ARM64_INS_SUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBR_ZPmZ_H, ARM64_INS_SUBR, + {AArch64_SUBR_ZPmZ_H, + ARM64_INS_SUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBR_ZPmZ_S, ARM64_INS_SUBR, + {AArch64_SUBR_ZPmZ_S, + ARM64_INS_SUBR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBSWri, ARM64_INS_SUBS, + {AArch64_SUBSWri, + ARM64_INS_SUBS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBSWrs, ARM64_INS_SUBS, + {AArch64_SUBSWrs, + ARM64_INS_SUBS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBSWrx, ARM64_INS_SUBS, + {AArch64_SUBSWrx, + ARM64_INS_SUBS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBSXri, ARM64_INS_SUBS, + {AArch64_SUBSXri, + ARM64_INS_SUBS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBSXrs, ARM64_INS_SUBS, + {AArch64_SUBSXrs, + ARM64_INS_SUBS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBSXrx, ARM64_INS_SUBS, + {AArch64_SUBSXrx, + ARM64_INS_SUBS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBSXrx64, ARM64_INS_SUBS, + {AArch64_SUBSXrx64, + ARM64_INS_SUBS, #ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 + {0}, + {ARM64_REG_NZCV, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBWri, ARM64_INS_SUB, + {AArch64_SUBWri, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBWrs, ARM64_INS_SUB, + {AArch64_SUBWrs, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBWrx, ARM64_INS_SUB, + {AArch64_SUBWrx, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBXri, ARM64_INS_SUB, + {AArch64_SUBXri, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBXrs, ARM64_INS_SUB, + {AArch64_SUBXrs, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBXrx, ARM64_INS_SUB, + {AArch64_SUBXrx, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBXrx64, ARM64_INS_SUB, + {AArch64_SUBXrx64, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZI_B, ARM64_INS_SUB, + {AArch64_SUB_ZI_B, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZI_D, ARM64_INS_SUB, + {AArch64_SUB_ZI_D, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZI_H, ARM64_INS_SUB, + {AArch64_SUB_ZI_H, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZI_S, ARM64_INS_SUB, + {AArch64_SUB_ZI_S, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZPmZ_B, ARM64_INS_SUB, + {AArch64_SUB_ZPmZ_B, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZPmZ_D, ARM64_INS_SUB, + {AArch64_SUB_ZPmZ_D, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZPmZ_H, ARM64_INS_SUB, + {AArch64_SUB_ZPmZ_H, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZPmZ_S, ARM64_INS_SUB, + {AArch64_SUB_ZPmZ_S, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZZZ_B, ARM64_INS_SUB, + {AArch64_SUB_ZZZ_B, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZZZ_D, ARM64_INS_SUB, + {AArch64_SUB_ZZZ_D, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZZZ_H, ARM64_INS_SUB, + {AArch64_SUB_ZZZ_H, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUB_ZZZ_S, ARM64_INS_SUB, + {AArch64_SUB_ZZZ_S, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBv16i8, ARM64_INS_SUB, + {AArch64_SUBv16i8, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBv1i64, ARM64_INS_SUB, + {AArch64_SUBv1i64, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBv2i32, ARM64_INS_SUB, + {AArch64_SUBv2i32, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBv2i64, ARM64_INS_SUB, + {AArch64_SUBv2i64, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBv4i16, ARM64_INS_SUB, + {AArch64_SUBv4i16, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBv4i32, ARM64_INS_SUB, + {AArch64_SUBv4i32, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBv8i16, ARM64_INS_SUB, + {AArch64_SUBv8i16, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUBv8i8, ARM64_INS_SUB, + {AArch64_SUBv8i8, + ARM64_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUNPKHI_ZZ_D, ARM64_INS_SUNPKHI, + {AArch64_SUNPKHI_ZZ_D, + ARM64_INS_SUNPKHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUNPKHI_ZZ_H, ARM64_INS_SUNPKHI, + {AArch64_SUNPKHI_ZZ_H, + ARM64_INS_SUNPKHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUNPKHI_ZZ_S, ARM64_INS_SUNPKHI, + {AArch64_SUNPKHI_ZZ_S, + ARM64_INS_SUNPKHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUNPKLO_ZZ_D, ARM64_INS_SUNPKLO, + {AArch64_SUNPKLO_ZZ_D, + ARM64_INS_SUNPKLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUNPKLO_ZZ_H, ARM64_INS_SUNPKLO, + {AArch64_SUNPKLO_ZZ_H, + ARM64_INS_SUNPKLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUNPKLO_ZZ_S, ARM64_INS_SUNPKLO, + {AArch64_SUNPKLO_ZZ_S, + ARM64_INS_SUNPKLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv16i8, ARM64_INS_SUQADD, + {AArch64_SUQADDv16i8, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv1i16, ARM64_INS_SUQADD, + {AArch64_SUQADDv1i16, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv1i32, ARM64_INS_SUQADD, + {AArch64_SUQADDv1i32, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv1i64, ARM64_INS_SUQADD, + {AArch64_SUQADDv1i64, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv1i8, ARM64_INS_SUQADD, + {AArch64_SUQADDv1i8, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv2i32, ARM64_INS_SUQADD, + {AArch64_SUQADDv2i32, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv2i64, ARM64_INS_SUQADD, + {AArch64_SUQADDv2i64, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv4i16, ARM64_INS_SUQADD, + {AArch64_SUQADDv4i16, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv4i32, ARM64_INS_SUQADD, + {AArch64_SUQADDv4i32, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv8i16, ARM64_INS_SUQADD, + {AArch64_SUQADDv8i16, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SUQADDv8i8, ARM64_INS_SUQADD, + {AArch64_SUQADDv8i8, + ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SVC, ARM64_INS_SVC, + {AArch64_SVC, + ARM64_INS_SVC, #ifndef CAPSTONE_DIET - { 0, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_INT, 0 }, 0, 0 + {0, 0}, + {ARM64_REG_LR, 0}, + {ARM64_GRP_INT, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPAB, ARM64_INS_SWPAB, + {AArch64_SWPAB, + ARM64_INS_SWPAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPAH, ARM64_INS_SWPAH, + {AArch64_SWPAH, + ARM64_INS_SWPAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPALB, ARM64_INS_SWPALB, + {AArch64_SWPALB, + ARM64_INS_SWPALB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPALH, ARM64_INS_SWPALH, + {AArch64_SWPALH, + ARM64_INS_SWPALH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPALW, ARM64_INS_SWPAL, + {AArch64_SWPALW, + ARM64_INS_SWPAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPALX, ARM64_INS_SWPAL, + {AArch64_SWPALX, + ARM64_INS_SWPAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPAW, ARM64_INS_SWPA, + {AArch64_SWPAW, + ARM64_INS_SWPA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPAX, ARM64_INS_SWPA, + {AArch64_SWPAX, + ARM64_INS_SWPA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPB, ARM64_INS_SWPB, + {AArch64_SWPB, + ARM64_INS_SWPB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPH, ARM64_INS_SWPH, + {AArch64_SWPH, + ARM64_INS_SWPH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPLB, ARM64_INS_SWPLB, + {AArch64_SWPLB, + ARM64_INS_SWPLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPLH, ARM64_INS_SWPLH, + {AArch64_SWPLH, + ARM64_INS_SWPLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPLW, ARM64_INS_SWPL, + {AArch64_SWPLW, + ARM64_INS_SWPL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPLX, ARM64_INS_SWPL, + {AArch64_SWPLX, + ARM64_INS_SWPL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPW, ARM64_INS_SWP, + {AArch64_SWPW, + ARM64_INS_SWP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SWPX, ARM64_INS_SWP, + {AArch64_SWPX, + ARM64_INS_SWP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SXTB_ZPmZ_D, ARM64_INS_SXTB, + {AArch64_SXTB_ZPmZ_D, + ARM64_INS_SXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SXTB_ZPmZ_H, ARM64_INS_SXTB, + {AArch64_SXTB_ZPmZ_H, + ARM64_INS_SXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SXTB_ZPmZ_S, ARM64_INS_SXTB, + {AArch64_SXTB_ZPmZ_S, + ARM64_INS_SXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SXTH_ZPmZ_D, ARM64_INS_SXTH, + {AArch64_SXTH_ZPmZ_D, + ARM64_INS_SXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SXTH_ZPmZ_S, ARM64_INS_SXTH, + {AArch64_SXTH_ZPmZ_S, + ARM64_INS_SXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SXTW_ZPmZ_D, ARM64_INS_SXTW, + {AArch64_SXTW_ZPmZ_D, + ARM64_INS_SXTW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SYSLxt, ARM64_INS_SYSL, + {AArch64_SYSLxt, + ARM64_INS_SYSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_SYSxt, ARM64_INS_SYS, + {AArch64_SYSxt, + ARM64_INS_SYS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBL_ZZZ_B, ARM64_INS_TBL, + {AArch64_TBL_ZZZ_B, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBL_ZZZ_D, ARM64_INS_TBL, + {AArch64_TBL_ZZZ_D, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBL_ZZZ_H, ARM64_INS_TBL, + {AArch64_TBL_ZZZ_H, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBL_ZZZ_S, ARM64_INS_TBL, + {AArch64_TBL_ZZZ_S, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBLv16i8Four, ARM64_INS_TBL, + {AArch64_TBLv16i8Four, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBLv16i8One, ARM64_INS_TBL, + {AArch64_TBLv16i8One, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBLv16i8Three, ARM64_INS_TBL, + {AArch64_TBLv16i8Three, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBLv16i8Two, ARM64_INS_TBL, + {AArch64_TBLv16i8Two, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBLv8i8Four, ARM64_INS_TBL, + {AArch64_TBLv8i8Four, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBLv8i8One, ARM64_INS_TBL, + {AArch64_TBLv8i8One, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBLv8i8Three, ARM64_INS_TBL, + {AArch64_TBLv8i8Three, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBLv8i8Two, ARM64_INS_TBL, + {AArch64_TBLv8i8Two, + ARM64_INS_TBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBNZW, ARM64_INS_TBNZ, + {AArch64_TBNZW, + ARM64_INS_TBNZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_TBNZX, ARM64_INS_TBNZ, + {AArch64_TBNZX, + ARM64_INS_TBNZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_TBXv16i8Four, ARM64_INS_TBX, + {AArch64_TBXv16i8Four, + ARM64_INS_TBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBXv16i8One, ARM64_INS_TBX, + {AArch64_TBXv16i8One, + ARM64_INS_TBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBXv16i8Three, ARM64_INS_TBX, + {AArch64_TBXv16i8Three, + ARM64_INS_TBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBXv16i8Two, ARM64_INS_TBX, + {AArch64_TBXv16i8Two, + ARM64_INS_TBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBXv8i8Four, ARM64_INS_TBX, + {AArch64_TBXv8i8Four, + ARM64_INS_TBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBXv8i8One, ARM64_INS_TBX, + {AArch64_TBXv8i8One, + ARM64_INS_TBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBXv8i8Three, ARM64_INS_TBX, + {AArch64_TBXv8i8Three, + ARM64_INS_TBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBXv8i8Two, ARM64_INS_TBX, + {AArch64_TBXv8i8Two, + ARM64_INS_TBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TBZW, ARM64_INS_TBZ, + {AArch64_TBZW, + ARM64_INS_TBZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_TBZX, ARM64_INS_TBZ, + {AArch64_TBZX, + ARM64_INS_TBZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 + {0}, + {0}, + {ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0}, + 1, + 0 #endif -}, + }, -{ - AArch64_TRN1_PPP_B, ARM64_INS_TRN1, + {AArch64_TRN1_PPP_B, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1_PPP_D, ARM64_INS_TRN1, + {AArch64_TRN1_PPP_D, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1_PPP_H, ARM64_INS_TRN1, + {AArch64_TRN1_PPP_H, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1_PPP_S, ARM64_INS_TRN1, + {AArch64_TRN1_PPP_S, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1_ZZZ_B, ARM64_INS_TRN1, + {AArch64_TRN1_ZZZ_B, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1_ZZZ_D, ARM64_INS_TRN1, + {AArch64_TRN1_ZZZ_D, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1_ZZZ_H, ARM64_INS_TRN1, + {AArch64_TRN1_ZZZ_H, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1_ZZZ_S, ARM64_INS_TRN1, + {AArch64_TRN1_ZZZ_S, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1v16i8, ARM64_INS_TRN1, + {AArch64_TRN1v16i8, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1v2i32, ARM64_INS_TRN1, + {AArch64_TRN1v2i32, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1v2i64, ARM64_INS_TRN1, + {AArch64_TRN1v2i64, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1v4i16, ARM64_INS_TRN1, + {AArch64_TRN1v4i16, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1v4i32, ARM64_INS_TRN1, + {AArch64_TRN1v4i32, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1v8i16, ARM64_INS_TRN1, + {AArch64_TRN1v8i16, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN1v8i8, ARM64_INS_TRN1, + {AArch64_TRN1v8i8, + ARM64_INS_TRN1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2_PPP_B, ARM64_INS_TRN2, + {AArch64_TRN2_PPP_B, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2_PPP_D, ARM64_INS_TRN2, + {AArch64_TRN2_PPP_D, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2_PPP_H, ARM64_INS_TRN2, + {AArch64_TRN2_PPP_H, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2_PPP_S, ARM64_INS_TRN2, + {AArch64_TRN2_PPP_S, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2_ZZZ_B, ARM64_INS_TRN2, + {AArch64_TRN2_ZZZ_B, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2_ZZZ_D, ARM64_INS_TRN2, + {AArch64_TRN2_ZZZ_D, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2_ZZZ_H, ARM64_INS_TRN2, + {AArch64_TRN2_ZZZ_H, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2_ZZZ_S, ARM64_INS_TRN2, + {AArch64_TRN2_ZZZ_S, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2v16i8, ARM64_INS_TRN2, + {AArch64_TRN2v16i8, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2v2i32, ARM64_INS_TRN2, + {AArch64_TRN2v2i32, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2v2i64, ARM64_INS_TRN2, + {AArch64_TRN2v2i64, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2v4i16, ARM64_INS_TRN2, + {AArch64_TRN2v4i16, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2v4i32, ARM64_INS_TRN2, + {AArch64_TRN2v4i32, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2v8i16, ARM64_INS_TRN2, + {AArch64_TRN2v8i16, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TRN2v8i8, ARM64_INS_TRN2, + {AArch64_TRN2v8i8, + ARM64_INS_TRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_TSB, ARM64_INS_TSB, + {AArch64_TSB, + ARM64_INS_TSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABALv16i8_v8i16, ARM64_INS_UABAL2, + {AArch64_UABALv16i8_v8i16, + ARM64_INS_UABAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABALv2i32_v2i64, ARM64_INS_UABAL, + {AArch64_UABALv2i32_v2i64, + ARM64_INS_UABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABALv4i16_v4i32, ARM64_INS_UABAL, + {AArch64_UABALv4i16_v4i32, + ARM64_INS_UABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABALv4i32_v2i64, ARM64_INS_UABAL2, + {AArch64_UABALv4i32_v2i64, + ARM64_INS_UABAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABALv8i16_v4i32, ARM64_INS_UABAL2, + {AArch64_UABALv8i16_v4i32, + ARM64_INS_UABAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABALv8i8_v8i16, ARM64_INS_UABAL, + {AArch64_UABALv8i8_v8i16, + ARM64_INS_UABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABAv16i8, ARM64_INS_UABA, + {AArch64_UABAv16i8, + ARM64_INS_UABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABAv2i32, ARM64_INS_UABA, + {AArch64_UABAv2i32, + ARM64_INS_UABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABAv4i16, ARM64_INS_UABA, + {AArch64_UABAv4i16, + ARM64_INS_UABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABAv4i32, ARM64_INS_UABA, + {AArch64_UABAv4i32, + ARM64_INS_UABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABAv8i16, ARM64_INS_UABA, + {AArch64_UABAv8i16, + ARM64_INS_UABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABAv8i8, ARM64_INS_UABA, + {AArch64_UABAv8i8, + ARM64_INS_UABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDLv16i8_v8i16, ARM64_INS_UABDL2, + {AArch64_UABDLv16i8_v8i16, + ARM64_INS_UABDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDLv2i32_v2i64, ARM64_INS_UABDL, + {AArch64_UABDLv2i32_v2i64, + ARM64_INS_UABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDLv4i16_v4i32, ARM64_INS_UABDL, + {AArch64_UABDLv4i16_v4i32, + ARM64_INS_UABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDLv4i32_v2i64, ARM64_INS_UABDL2, + {AArch64_UABDLv4i32_v2i64, + ARM64_INS_UABDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDLv8i16_v4i32, ARM64_INS_UABDL2, + {AArch64_UABDLv8i16_v4i32, + ARM64_INS_UABDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDLv8i8_v8i16, ARM64_INS_UABDL, + {AArch64_UABDLv8i8_v8i16, + ARM64_INS_UABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABD_ZPmZ_B, ARM64_INS_UABD, + {AArch64_UABD_ZPmZ_B, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABD_ZPmZ_D, ARM64_INS_UABD, + {AArch64_UABD_ZPmZ_D, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABD_ZPmZ_H, ARM64_INS_UABD, + {AArch64_UABD_ZPmZ_H, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABD_ZPmZ_S, ARM64_INS_UABD, + {AArch64_UABD_ZPmZ_S, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDv16i8, ARM64_INS_UABD, + {AArch64_UABDv16i8, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDv2i32, ARM64_INS_UABD, + {AArch64_UABDv2i32, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDv4i16, ARM64_INS_UABD, + {AArch64_UABDv4i16, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDv4i32, ARM64_INS_UABD, + {AArch64_UABDv4i32, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDv8i16, ARM64_INS_UABD, + {AArch64_UABDv8i16, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UABDv8i8, ARM64_INS_UABD, + {AArch64_UABDv8i8, + ARM64_INS_UABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADALPv16i8_v8i16, ARM64_INS_UADALP, + {AArch64_UADALPv16i8_v8i16, + ARM64_INS_UADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADALPv2i32_v1i64, ARM64_INS_UADALP, + {AArch64_UADALPv2i32_v1i64, + ARM64_INS_UADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADALPv4i16_v2i32, ARM64_INS_UADALP, + {AArch64_UADALPv4i16_v2i32, + ARM64_INS_UADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADALPv4i32_v2i64, ARM64_INS_UADALP, + {AArch64_UADALPv4i32_v2i64, + ARM64_INS_UADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADALPv8i16_v4i32, ARM64_INS_UADALP, + {AArch64_UADALPv8i16_v4i32, + ARM64_INS_UADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADALPv8i8_v4i16, ARM64_INS_UADALP, + {AArch64_UADALPv8i8_v4i16, + ARM64_INS_UADALP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLPv16i8_v8i16, ARM64_INS_UADDLP, + {AArch64_UADDLPv16i8_v8i16, + ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLPv2i32_v1i64, ARM64_INS_UADDLP, + {AArch64_UADDLPv2i32_v1i64, + ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLPv4i16_v2i32, ARM64_INS_UADDLP, + {AArch64_UADDLPv4i16_v2i32, + ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLPv4i32_v2i64, ARM64_INS_UADDLP, + {AArch64_UADDLPv4i32_v2i64, + ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLPv8i16_v4i32, ARM64_INS_UADDLP, + {AArch64_UADDLPv8i16_v4i32, + ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLPv8i8_v4i16, ARM64_INS_UADDLP, + {AArch64_UADDLPv8i8_v4i16, + ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLVv16i8v, ARM64_INS_UADDLV, + {AArch64_UADDLVv16i8v, + ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLVv4i16v, ARM64_INS_UADDLV, + {AArch64_UADDLVv4i16v, + ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLVv4i32v, ARM64_INS_UADDLV, + {AArch64_UADDLVv4i32v, + ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLVv8i16v, ARM64_INS_UADDLV, + {AArch64_UADDLVv8i16v, + ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLVv8i8v, ARM64_INS_UADDLV, + {AArch64_UADDLVv8i8v, + ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLv16i8_v8i16, ARM64_INS_UADDL2, + {AArch64_UADDLv16i8_v8i16, + ARM64_INS_UADDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLv2i32_v2i64, ARM64_INS_UADDL, + {AArch64_UADDLv2i32_v2i64, + ARM64_INS_UADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLv4i16_v4i32, ARM64_INS_UADDL, + {AArch64_UADDLv4i16_v4i32, + ARM64_INS_UADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLv4i32_v2i64, ARM64_INS_UADDL2, + {AArch64_UADDLv4i32_v2i64, + ARM64_INS_UADDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLv8i16_v4i32, ARM64_INS_UADDL2, + {AArch64_UADDLv8i16_v4i32, + ARM64_INS_UADDL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDLv8i8_v8i16, ARM64_INS_UADDL, + {AArch64_UADDLv8i8_v8i16, + ARM64_INS_UADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDV_VPZ_B, ARM64_INS_UADDV, + {AArch64_UADDV_VPZ_B, + ARM64_INS_UADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDV_VPZ_D, ARM64_INS_UADDV, + {AArch64_UADDV_VPZ_D, + ARM64_INS_UADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDV_VPZ_H, ARM64_INS_UADDV, + {AArch64_UADDV_VPZ_H, + ARM64_INS_UADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDV_VPZ_S, ARM64_INS_UADDV, + {AArch64_UADDV_VPZ_S, + ARM64_INS_UADDV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDWv16i8_v8i16, ARM64_INS_UADDW2, + {AArch64_UADDWv16i8_v8i16, + ARM64_INS_UADDW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDWv2i32_v2i64, ARM64_INS_UADDW, + {AArch64_UADDWv2i32_v2i64, + ARM64_INS_UADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDWv4i16_v4i32, ARM64_INS_UADDW, + {AArch64_UADDWv4i16_v4i32, + ARM64_INS_UADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDWv4i32_v2i64, ARM64_INS_UADDW2, + {AArch64_UADDWv4i32_v2i64, + ARM64_INS_UADDW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDWv8i16_v4i32, ARM64_INS_UADDW2, + {AArch64_UADDWv8i16_v4i32, + ARM64_INS_UADDW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UADDWv8i8_v8i16, ARM64_INS_UADDW, + {AArch64_UADDWv8i8_v8i16, + ARM64_INS_UADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UBFMWri, ARM64_INS_UBFM, + {AArch64_UBFMWri, + ARM64_INS_UBFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UBFMXri, ARM64_INS_UBFM, + {AArch64_UBFMXri, + ARM64_INS_UBFM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFSWDri, ARM64_INS_UCVTF, + {AArch64_UCVTFSWDri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFSWHri, ARM64_INS_UCVTF, + {AArch64_UCVTFSWHri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFSWSri, ARM64_INS_UCVTF, + {AArch64_UCVTFSWSri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFSXDri, ARM64_INS_UCVTF, + {AArch64_UCVTFSXDri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFSXHri, ARM64_INS_UCVTF, + {AArch64_UCVTFSXHri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFSXSri, ARM64_INS_UCVTF, + {AArch64_UCVTFSXSri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFUWDri, ARM64_INS_UCVTF, + {AArch64_UCVTFUWDri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFUWHri, ARM64_INS_UCVTF, + {AArch64_UCVTFUWHri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFUWSri, ARM64_INS_UCVTF, + {AArch64_UCVTFUWSri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFUXDri, ARM64_INS_UCVTF, + {AArch64_UCVTFUXDri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFUXHri, ARM64_INS_UCVTF, + {AArch64_UCVTFUXHri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFUXSri, ARM64_INS_UCVTF, + {AArch64_UCVTFUXSri, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTF_ZPmZ_DtoD, ARM64_INS_UCVTF, + {AArch64_UCVTF_ZPmZ_DtoD, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTF_ZPmZ_DtoH, ARM64_INS_UCVTF, + {AArch64_UCVTF_ZPmZ_DtoH, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTF_ZPmZ_DtoS, ARM64_INS_UCVTF, + {AArch64_UCVTF_ZPmZ_DtoS, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTF_ZPmZ_HtoH, ARM64_INS_UCVTF, + {AArch64_UCVTF_ZPmZ_HtoH, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTF_ZPmZ_StoD, ARM64_INS_UCVTF, + {AArch64_UCVTF_ZPmZ_StoD, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTF_ZPmZ_StoH, ARM64_INS_UCVTF, + {AArch64_UCVTF_ZPmZ_StoH, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTF_ZPmZ_StoS, ARM64_INS_UCVTF, + {AArch64_UCVTF_ZPmZ_StoS, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFd, ARM64_INS_UCVTF, + {AArch64_UCVTFd, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFh, ARM64_INS_UCVTF, + {AArch64_UCVTFh, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFs, ARM64_INS_UCVTF, + {AArch64_UCVTFs, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv1i16, ARM64_INS_UCVTF, + {AArch64_UCVTFv1i16, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv1i32, ARM64_INS_UCVTF, + {AArch64_UCVTFv1i32, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv1i64, ARM64_INS_UCVTF, + {AArch64_UCVTFv1i64, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv2f32, ARM64_INS_UCVTF, + {AArch64_UCVTFv2f32, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv2f64, ARM64_INS_UCVTF, + {AArch64_UCVTFv2f64, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv2i32_shift, ARM64_INS_UCVTF, + {AArch64_UCVTFv2i32_shift, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv2i64_shift, ARM64_INS_UCVTF, + {AArch64_UCVTFv2i64_shift, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv4f16, ARM64_INS_UCVTF, + {AArch64_UCVTFv4f16, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv4f32, ARM64_INS_UCVTF, + {AArch64_UCVTFv4f32, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv4i16_shift, ARM64_INS_UCVTF, + {AArch64_UCVTFv4i16_shift, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv4i32_shift, ARM64_INS_UCVTF, + {AArch64_UCVTFv4i32_shift, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv8f16, ARM64_INS_UCVTF, + {AArch64_UCVTFv8f16, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UCVTFv8i16_shift, ARM64_INS_UCVTF, + {AArch64_UCVTFv8i16_shift, + ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDIVR_ZPmZ_D, ARM64_INS_UDIVR, + {AArch64_UDIVR_ZPmZ_D, + ARM64_INS_UDIVR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDIVR_ZPmZ_S, ARM64_INS_UDIVR, + {AArch64_UDIVR_ZPmZ_S, + ARM64_INS_UDIVR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDIVWr, ARM64_INS_UDIV, + {AArch64_UDIVWr, + ARM64_INS_UDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDIVXr, ARM64_INS_UDIV, + {AArch64_UDIVXr, + ARM64_INS_UDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDIV_ZPmZ_D, ARM64_INS_UDIV, + {AArch64_UDIV_ZPmZ_D, + ARM64_INS_UDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDIV_ZPmZ_S, ARM64_INS_UDIV, + {AArch64_UDIV_ZPmZ_S, + ARM64_INS_UDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDOT_ZZZI_D, ARM64_INS_UDOT, + {AArch64_UDOT_ZZZI_D, + ARM64_INS_UDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDOT_ZZZI_S, ARM64_INS_UDOT, + {AArch64_UDOT_ZZZI_S, + ARM64_INS_UDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDOT_ZZZ_D, ARM64_INS_UDOT, + {AArch64_UDOT_ZZZ_D, + ARM64_INS_UDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDOT_ZZZ_S, ARM64_INS_UDOT, + {AArch64_UDOT_ZZZ_S, + ARM64_INS_UDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDOTlanev16i8, ARM64_INS_UDOT, + {AArch64_UDOTlanev16i8, + ARM64_INS_UDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDOTlanev8i8, ARM64_INS_UDOT, + {AArch64_UDOTlanev8i8, + ARM64_INS_UDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDOTv16i8, ARM64_INS_UDOT, + {AArch64_UDOTv16i8, + ARM64_INS_UDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UDOTv8i8, ARM64_INS_UDOT, + {AArch64_UDOTv8i8, + ARM64_INS_UDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHADDv16i8, ARM64_INS_UHADD, + {AArch64_UHADDv16i8, + ARM64_INS_UHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHADDv2i32, ARM64_INS_UHADD, + {AArch64_UHADDv2i32, + ARM64_INS_UHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHADDv4i16, ARM64_INS_UHADD, + {AArch64_UHADDv4i16, + ARM64_INS_UHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHADDv4i32, ARM64_INS_UHADD, + {AArch64_UHADDv4i32, + ARM64_INS_UHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHADDv8i16, ARM64_INS_UHADD, + {AArch64_UHADDv8i16, + ARM64_INS_UHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHADDv8i8, ARM64_INS_UHADD, + {AArch64_UHADDv8i8, + ARM64_INS_UHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHSUBv16i8, ARM64_INS_UHSUB, + {AArch64_UHSUBv16i8, + ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHSUBv2i32, ARM64_INS_UHSUB, + {AArch64_UHSUBv2i32, + ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHSUBv4i16, ARM64_INS_UHSUB, + {AArch64_UHSUBv4i16, + ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHSUBv4i32, ARM64_INS_UHSUB, + {AArch64_UHSUBv4i32, + ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHSUBv8i16, ARM64_INS_UHSUB, + {AArch64_UHSUBv8i16, + ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UHSUBv8i8, ARM64_INS_UHSUB, + {AArch64_UHSUBv8i8, + ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMADDLrrr, ARM64_INS_UMADDL, + {AArch64_UMADDLrrr, + ARM64_INS_UMADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXPv16i8, ARM64_INS_UMAXP, + {AArch64_UMAXPv16i8, + ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXPv2i32, ARM64_INS_UMAXP, + {AArch64_UMAXPv2i32, + ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXPv4i16, ARM64_INS_UMAXP, + {AArch64_UMAXPv4i16, + ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXPv4i32, ARM64_INS_UMAXP, + {AArch64_UMAXPv4i32, + ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXPv8i16, ARM64_INS_UMAXP, + {AArch64_UMAXPv8i16, + ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXPv8i8, ARM64_INS_UMAXP, + {AArch64_UMAXPv8i8, + ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXV_VPZ_B, ARM64_INS_UMAXV, + {AArch64_UMAXV_VPZ_B, + ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXV_VPZ_D, ARM64_INS_UMAXV, + {AArch64_UMAXV_VPZ_D, + ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXV_VPZ_H, ARM64_INS_UMAXV, + {AArch64_UMAXV_VPZ_H, + ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXV_VPZ_S, ARM64_INS_UMAXV, + {AArch64_UMAXV_VPZ_S, + ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXVv16i8v, ARM64_INS_UMAXV, + {AArch64_UMAXVv16i8v, + ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXVv4i16v, ARM64_INS_UMAXV, + {AArch64_UMAXVv4i16v, + ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXVv4i32v, ARM64_INS_UMAXV, + {AArch64_UMAXVv4i32v, + ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXVv8i16v, ARM64_INS_UMAXV, + {AArch64_UMAXVv8i16v, + ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXVv8i8v, ARM64_INS_UMAXV, + {AArch64_UMAXVv8i8v, + ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAX_ZI_B, ARM64_INS_UMAX, + {AArch64_UMAX_ZI_B, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAX_ZI_D, ARM64_INS_UMAX, + {AArch64_UMAX_ZI_D, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAX_ZI_H, ARM64_INS_UMAX, + {AArch64_UMAX_ZI_H, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAX_ZI_S, ARM64_INS_UMAX, + {AArch64_UMAX_ZI_S, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAX_ZPmZ_B, ARM64_INS_UMAX, + {AArch64_UMAX_ZPmZ_B, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAX_ZPmZ_D, ARM64_INS_UMAX, + {AArch64_UMAX_ZPmZ_D, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAX_ZPmZ_H, ARM64_INS_UMAX, + {AArch64_UMAX_ZPmZ_H, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAX_ZPmZ_S, ARM64_INS_UMAX, + {AArch64_UMAX_ZPmZ_S, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXv16i8, ARM64_INS_UMAX, + {AArch64_UMAXv16i8, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXv2i32, ARM64_INS_UMAX, + {AArch64_UMAXv2i32, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXv4i16, ARM64_INS_UMAX, + {AArch64_UMAXv4i16, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXv4i32, ARM64_INS_UMAX, + {AArch64_UMAXv4i32, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXv8i16, ARM64_INS_UMAX, + {AArch64_UMAXv8i16, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMAXv8i8, ARM64_INS_UMAX, + {AArch64_UMAXv8i8, + ARM64_INS_UMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINPv16i8, ARM64_INS_UMINP, + {AArch64_UMINPv16i8, + ARM64_INS_UMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINPv2i32, ARM64_INS_UMINP, + {AArch64_UMINPv2i32, + ARM64_INS_UMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINPv4i16, ARM64_INS_UMINP, + {AArch64_UMINPv4i16, + ARM64_INS_UMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINPv4i32, ARM64_INS_UMINP, + {AArch64_UMINPv4i32, + ARM64_INS_UMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINPv8i16, ARM64_INS_UMINP, + {AArch64_UMINPv8i16, + ARM64_INS_UMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINPv8i8, ARM64_INS_UMINP, + {AArch64_UMINPv8i8, + ARM64_INS_UMINP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINV_VPZ_B, ARM64_INS_UMINV, + {AArch64_UMINV_VPZ_B, + ARM64_INS_UMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINV_VPZ_D, ARM64_INS_UMINV, + {AArch64_UMINV_VPZ_D, + ARM64_INS_UMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINV_VPZ_H, ARM64_INS_UMINV, + {AArch64_UMINV_VPZ_H, + ARM64_INS_UMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINV_VPZ_S, ARM64_INS_UMINV, + {AArch64_UMINV_VPZ_S, + ARM64_INS_UMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINVv16i8v, ARM64_INS_UMINV, + {AArch64_UMINVv16i8v, + ARM64_INS_UMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINVv4i16v, ARM64_INS_UMINV, + {AArch64_UMINVv4i16v, + ARM64_INS_UMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINVv4i32v, ARM64_INS_UMINV, + {AArch64_UMINVv4i32v, + ARM64_INS_UMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINVv8i16v, ARM64_INS_UMINV, + {AArch64_UMINVv8i16v, + ARM64_INS_UMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINVv8i8v, ARM64_INS_UMINV, + {AArch64_UMINVv8i8v, + ARM64_INS_UMINV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMIN_ZI_B, ARM64_INS_UMIN, + {AArch64_UMIN_ZI_B, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMIN_ZI_D, ARM64_INS_UMIN, + {AArch64_UMIN_ZI_D, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMIN_ZI_H, ARM64_INS_UMIN, + {AArch64_UMIN_ZI_H, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMIN_ZI_S, ARM64_INS_UMIN, + {AArch64_UMIN_ZI_S, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMIN_ZPmZ_B, ARM64_INS_UMIN, + {AArch64_UMIN_ZPmZ_B, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMIN_ZPmZ_D, ARM64_INS_UMIN, + {AArch64_UMIN_ZPmZ_D, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMIN_ZPmZ_H, ARM64_INS_UMIN, + {AArch64_UMIN_ZPmZ_H, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMIN_ZPmZ_S, ARM64_INS_UMIN, + {AArch64_UMIN_ZPmZ_S, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINv16i8, ARM64_INS_UMIN, + {AArch64_UMINv16i8, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINv2i32, ARM64_INS_UMIN, + {AArch64_UMINv2i32, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINv4i16, ARM64_INS_UMIN, + {AArch64_UMINv4i16, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINv4i32, ARM64_INS_UMIN, + {AArch64_UMINv4i32, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINv8i16, ARM64_INS_UMIN, + {AArch64_UMINv8i16, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMINv8i8, ARM64_INS_UMIN, + {AArch64_UMINv8i8, + ARM64_INS_UMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv16i8_v8i16, ARM64_INS_UMLAL2, + {AArch64_UMLALv16i8_v8i16, + ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv2i32_indexed, ARM64_INS_UMLAL, + {AArch64_UMLALv2i32_indexed, + ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv2i32_v2i64, ARM64_INS_UMLAL, + {AArch64_UMLALv2i32_v2i64, + ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv4i16_indexed, ARM64_INS_UMLAL, + {AArch64_UMLALv4i16_indexed, + ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv4i16_v4i32, ARM64_INS_UMLAL, + {AArch64_UMLALv4i16_v4i32, + ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv4i32_indexed, ARM64_INS_UMLAL2, + {AArch64_UMLALv4i32_indexed, + ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv4i32_v2i64, ARM64_INS_UMLAL2, + {AArch64_UMLALv4i32_v2i64, + ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv8i16_indexed, ARM64_INS_UMLAL2, + {AArch64_UMLALv8i16_indexed, + ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv8i16_v4i32, ARM64_INS_UMLAL2, + {AArch64_UMLALv8i16_v4i32, + ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLALv8i8_v8i16, ARM64_INS_UMLAL, + {AArch64_UMLALv8i8_v8i16, + ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv16i8_v8i16, ARM64_INS_UMLSL2, + {AArch64_UMLSLv16i8_v8i16, + ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv2i32_indexed, ARM64_INS_UMLSL, + {AArch64_UMLSLv2i32_indexed, + ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv2i32_v2i64, ARM64_INS_UMLSL, + {AArch64_UMLSLv2i32_v2i64, + ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv4i16_indexed, ARM64_INS_UMLSL, + {AArch64_UMLSLv4i16_indexed, + ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv4i16_v4i32, ARM64_INS_UMLSL, + {AArch64_UMLSLv4i16_v4i32, + ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv4i32_indexed, ARM64_INS_UMLSL2, + {AArch64_UMLSLv4i32_indexed, + ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv4i32_v2i64, ARM64_INS_UMLSL2, + {AArch64_UMLSLv4i32_v2i64, + ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv8i16_indexed, ARM64_INS_UMLSL2, + {AArch64_UMLSLv8i16_indexed, + ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv8i16_v4i32, ARM64_INS_UMLSL2, + {AArch64_UMLSLv8i16_v4i32, + ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMLSLv8i8_v8i16, ARM64_INS_UMLSL, + {AArch64_UMLSLv8i8_v8i16, + ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMOVvi16, ARM64_INS_UMOV, + {AArch64_UMOVvi16, + ARM64_INS_UMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMOVvi32, ARM64_INS_MOV, + {AArch64_UMOVvi32, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMOVvi64, ARM64_INS_MOV, + {AArch64_UMOVvi64, + ARM64_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMOVvi8, ARM64_INS_UMOV, + {AArch64_UMOVvi8, + ARM64_INS_UMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMSUBLrrr, ARM64_INS_UMSUBL, + {AArch64_UMSUBLrrr, + ARM64_INS_UMSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULH_ZPmZ_B, ARM64_INS_UMULH, + {AArch64_UMULH_ZPmZ_B, + ARM64_INS_UMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULH_ZPmZ_D, ARM64_INS_UMULH, + {AArch64_UMULH_ZPmZ_D, + ARM64_INS_UMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULH_ZPmZ_H, ARM64_INS_UMULH, + {AArch64_UMULH_ZPmZ_H, + ARM64_INS_UMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULH_ZPmZ_S, ARM64_INS_UMULH, + {AArch64_UMULH_ZPmZ_S, + ARM64_INS_UMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULHrr, ARM64_INS_UMULH, + {AArch64_UMULHrr, + ARM64_INS_UMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv16i8_v8i16, ARM64_INS_UMULL2, + {AArch64_UMULLv16i8_v8i16, + ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv2i32_indexed, ARM64_INS_UMULL, + {AArch64_UMULLv2i32_indexed, + ARM64_INS_UMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv2i32_v2i64, ARM64_INS_UMULL, + {AArch64_UMULLv2i32_v2i64, + ARM64_INS_UMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv4i16_indexed, ARM64_INS_UMULL, + {AArch64_UMULLv4i16_indexed, + ARM64_INS_UMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv4i16_v4i32, ARM64_INS_UMULL, + {AArch64_UMULLv4i16_v4i32, + ARM64_INS_UMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv4i32_indexed, ARM64_INS_UMULL2, + {AArch64_UMULLv4i32_indexed, + ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv4i32_v2i64, ARM64_INS_UMULL2, + {AArch64_UMULLv4i32_v2i64, + ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv8i16_indexed, ARM64_INS_UMULL2, + {AArch64_UMULLv8i16_indexed, + ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv8i16_v4i32, ARM64_INS_UMULL2, + {AArch64_UMULLv8i16_v4i32, + ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UMULLv8i8_v8i16, ARM64_INS_UMULL, + {AArch64_UMULLv8i8_v8i16, + ARM64_INS_UMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADD_ZI_B, ARM64_INS_UQADD, + {AArch64_UQADD_ZI_B, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADD_ZI_D, ARM64_INS_UQADD, + {AArch64_UQADD_ZI_D, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADD_ZI_H, ARM64_INS_UQADD, + {AArch64_UQADD_ZI_H, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADD_ZI_S, ARM64_INS_UQADD, + {AArch64_UQADD_ZI_S, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADD_ZZZ_B, ARM64_INS_UQADD, + {AArch64_UQADD_ZZZ_B, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADD_ZZZ_D, ARM64_INS_UQADD, + {AArch64_UQADD_ZZZ_D, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADD_ZZZ_H, ARM64_INS_UQADD, + {AArch64_UQADD_ZZZ_H, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADD_ZZZ_S, ARM64_INS_UQADD, + {AArch64_UQADD_ZZZ_S, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv16i8, ARM64_INS_UQADD, + {AArch64_UQADDv16i8, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv1i16, ARM64_INS_UQADD, + {AArch64_UQADDv1i16, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv1i32, ARM64_INS_UQADD, + {AArch64_UQADDv1i32, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv1i64, ARM64_INS_UQADD, + {AArch64_UQADDv1i64, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv1i8, ARM64_INS_UQADD, + {AArch64_UQADDv1i8, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv2i32, ARM64_INS_UQADD, + {AArch64_UQADDv2i32, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv2i64, ARM64_INS_UQADD, + {AArch64_UQADDv2i64, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv4i16, ARM64_INS_UQADD, + {AArch64_UQADDv4i16, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv4i32, ARM64_INS_UQADD, + {AArch64_UQADDv4i32, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv8i16, ARM64_INS_UQADD, + {AArch64_UQADDv8i16, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQADDv8i8, ARM64_INS_UQADD, + {AArch64_UQADDv8i8, + ARM64_INS_UQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECB_WPiI, ARM64_INS_UQDECB, + {AArch64_UQDECB_WPiI, + ARM64_INS_UQDECB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECB_XPiI, ARM64_INS_UQDECB, + {AArch64_UQDECB_XPiI, + ARM64_INS_UQDECB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECD_WPiI, ARM64_INS_UQDECD, + {AArch64_UQDECD_WPiI, + ARM64_INS_UQDECD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECD_XPiI, ARM64_INS_UQDECD, + {AArch64_UQDECD_XPiI, + ARM64_INS_UQDECD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECD_ZPiI, ARM64_INS_UQDECD, + {AArch64_UQDECD_ZPiI, + ARM64_INS_UQDECD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECH_WPiI, ARM64_INS_UQDECH, + {AArch64_UQDECH_WPiI, + ARM64_INS_UQDECH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECH_XPiI, ARM64_INS_UQDECH, + {AArch64_UQDECH_XPiI, + ARM64_INS_UQDECH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECH_ZPiI, ARM64_INS_UQDECH, + {AArch64_UQDECH_ZPiI, + ARM64_INS_UQDECH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_WP_B, ARM64_INS_UQDECP, + {AArch64_UQDECP_WP_B, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_WP_D, ARM64_INS_UQDECP, + {AArch64_UQDECP_WP_D, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_WP_H, ARM64_INS_UQDECP, + {AArch64_UQDECP_WP_H, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_WP_S, ARM64_INS_UQDECP, + {AArch64_UQDECP_WP_S, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_XP_B, ARM64_INS_UQDECP, + {AArch64_UQDECP_XP_B, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_XP_D, ARM64_INS_UQDECP, + {AArch64_UQDECP_XP_D, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_XP_H, ARM64_INS_UQDECP, + {AArch64_UQDECP_XP_H, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_XP_S, ARM64_INS_UQDECP, + {AArch64_UQDECP_XP_S, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_ZP_D, ARM64_INS_UQDECP, + {AArch64_UQDECP_ZP_D, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_ZP_H, ARM64_INS_UQDECP, + {AArch64_UQDECP_ZP_H, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECP_ZP_S, ARM64_INS_UQDECP, + {AArch64_UQDECP_ZP_S, + ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECW_WPiI, ARM64_INS_UQDECW, + {AArch64_UQDECW_WPiI, + ARM64_INS_UQDECW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECW_XPiI, ARM64_INS_UQDECW, + {AArch64_UQDECW_XPiI, + ARM64_INS_UQDECW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQDECW_ZPiI, ARM64_INS_UQDECW, + {AArch64_UQDECW_ZPiI, + ARM64_INS_UQDECW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCB_WPiI, ARM64_INS_UQINCB, + {AArch64_UQINCB_WPiI, + ARM64_INS_UQINCB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCB_XPiI, ARM64_INS_UQINCB, + {AArch64_UQINCB_XPiI, + ARM64_INS_UQINCB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCD_WPiI, ARM64_INS_UQINCD, + {AArch64_UQINCD_WPiI, + ARM64_INS_UQINCD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCD_XPiI, ARM64_INS_UQINCD, + {AArch64_UQINCD_XPiI, + ARM64_INS_UQINCD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCD_ZPiI, ARM64_INS_UQINCD, + {AArch64_UQINCD_ZPiI, + ARM64_INS_UQINCD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCH_WPiI, ARM64_INS_UQINCH, + {AArch64_UQINCH_WPiI, + ARM64_INS_UQINCH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCH_XPiI, ARM64_INS_UQINCH, + {AArch64_UQINCH_XPiI, + ARM64_INS_UQINCH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCH_ZPiI, ARM64_INS_UQINCH, + {AArch64_UQINCH_ZPiI, + ARM64_INS_UQINCH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_WP_B, ARM64_INS_UQINCP, + {AArch64_UQINCP_WP_B, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_WP_D, ARM64_INS_UQINCP, + {AArch64_UQINCP_WP_D, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_WP_H, ARM64_INS_UQINCP, + {AArch64_UQINCP_WP_H, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_WP_S, ARM64_INS_UQINCP, + {AArch64_UQINCP_WP_S, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_XP_B, ARM64_INS_UQINCP, + {AArch64_UQINCP_XP_B, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_XP_D, ARM64_INS_UQINCP, + {AArch64_UQINCP_XP_D, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_XP_H, ARM64_INS_UQINCP, + {AArch64_UQINCP_XP_H, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_XP_S, ARM64_INS_UQINCP, + {AArch64_UQINCP_XP_S, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_ZP_D, ARM64_INS_UQINCP, + {AArch64_UQINCP_ZP_D, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_ZP_H, ARM64_INS_UQINCP, + {AArch64_UQINCP_ZP_H, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCP_ZP_S, ARM64_INS_UQINCP, + {AArch64_UQINCP_ZP_S, + ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCW_WPiI, ARM64_INS_UQINCW, + {AArch64_UQINCW_WPiI, + ARM64_INS_UQINCW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCW_XPiI, ARM64_INS_UQINCW, + {AArch64_UQINCW_XPiI, + ARM64_INS_UQINCW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQINCW_ZPiI, ARM64_INS_UQINCW, + {AArch64_UQINCW_ZPiI, + ARM64_INS_UQINCW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv16i8, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv16i8, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv1i16, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv1i16, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv1i32, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv1i32, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv1i64, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv1i64, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv1i8, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv1i8, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv2i32, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv2i32, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv2i64, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv2i64, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv4i16, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv4i16, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv4i32, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv4i32, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv8i16, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv8i16, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHLv8i8, ARM64_INS_UQRSHL, + {AArch64_UQRSHLv8i8, + ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHRNb, ARM64_INS_UQRSHRN, + {AArch64_UQRSHRNb, + ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHRNh, ARM64_INS_UQRSHRN, + {AArch64_UQRSHRNh, + ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHRNs, ARM64_INS_UQRSHRN, + {AArch64_UQRSHRNs, + ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHRNv16i8_shift, ARM64_INS_UQRSHRN2, + {AArch64_UQRSHRNv16i8_shift, + ARM64_INS_UQRSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHRNv2i32_shift, ARM64_INS_UQRSHRN, + {AArch64_UQRSHRNv2i32_shift, + ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHRNv4i16_shift, ARM64_INS_UQRSHRN, + {AArch64_UQRSHRNv4i16_shift, + ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHRNv4i32_shift, ARM64_INS_UQRSHRN2, + {AArch64_UQRSHRNv4i32_shift, + ARM64_INS_UQRSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHRNv8i16_shift, ARM64_INS_UQRSHRN2, + {AArch64_UQRSHRNv8i16_shift, + ARM64_INS_UQRSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQRSHRNv8i8_shift, ARM64_INS_UQRSHRN, + {AArch64_UQRSHRNv8i8_shift, + ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLb, ARM64_INS_UQSHL, + {AArch64_UQSHLb, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLd, ARM64_INS_UQSHL, + {AArch64_UQSHLd, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLh, ARM64_INS_UQSHL, + {AArch64_UQSHLh, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLs, ARM64_INS_UQSHL, + {AArch64_UQSHLs, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv16i8, ARM64_INS_UQSHL, + {AArch64_UQSHLv16i8, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv16i8_shift, ARM64_INS_UQSHL, + {AArch64_UQSHLv16i8_shift, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv1i16, ARM64_INS_UQSHL, + {AArch64_UQSHLv1i16, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv1i32, ARM64_INS_UQSHL, + {AArch64_UQSHLv1i32, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv1i64, ARM64_INS_UQSHL, + {AArch64_UQSHLv1i64, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv1i8, ARM64_INS_UQSHL, + {AArch64_UQSHLv1i8, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv2i32, ARM64_INS_UQSHL, + {AArch64_UQSHLv2i32, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv2i32_shift, ARM64_INS_UQSHL, + {AArch64_UQSHLv2i32_shift, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv2i64, ARM64_INS_UQSHL, + {AArch64_UQSHLv2i64, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv2i64_shift, ARM64_INS_UQSHL, + {AArch64_UQSHLv2i64_shift, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv4i16, ARM64_INS_UQSHL, + {AArch64_UQSHLv4i16, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv4i16_shift, ARM64_INS_UQSHL, + {AArch64_UQSHLv4i16_shift, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv4i32, ARM64_INS_UQSHL, + {AArch64_UQSHLv4i32, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv4i32_shift, ARM64_INS_UQSHL, + {AArch64_UQSHLv4i32_shift, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv8i16, ARM64_INS_UQSHL, + {AArch64_UQSHLv8i16, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv8i16_shift, ARM64_INS_UQSHL, + {AArch64_UQSHLv8i16_shift, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv8i8, ARM64_INS_UQSHL, + {AArch64_UQSHLv8i8, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHLv8i8_shift, ARM64_INS_UQSHL, + {AArch64_UQSHLv8i8_shift, + ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHRNb, ARM64_INS_UQSHRN, + {AArch64_UQSHRNb, + ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHRNh, ARM64_INS_UQSHRN, + {AArch64_UQSHRNh, + ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHRNs, ARM64_INS_UQSHRN, + {AArch64_UQSHRNs, + ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHRNv16i8_shift, ARM64_INS_UQSHRN2, + {AArch64_UQSHRNv16i8_shift, + ARM64_INS_UQSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN, + {AArch64_UQSHRNv2i32_shift, + ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN, + {AArch64_UQSHRNv4i16_shift, + ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHRNv4i32_shift, ARM64_INS_UQSHRN2, + {AArch64_UQSHRNv4i32_shift, + ARM64_INS_UQSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHRNv8i16_shift, ARM64_INS_UQSHRN2, + {AArch64_UQSHRNv8i16_shift, + ARM64_INS_UQSHRN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN, + {AArch64_UQSHRNv8i8_shift, + ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUB_ZI_B, ARM64_INS_UQSUB, + {AArch64_UQSUB_ZI_B, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUB_ZI_D, ARM64_INS_UQSUB, + {AArch64_UQSUB_ZI_D, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUB_ZI_H, ARM64_INS_UQSUB, + {AArch64_UQSUB_ZI_H, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUB_ZI_S, ARM64_INS_UQSUB, + {AArch64_UQSUB_ZI_S, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUB_ZZZ_B, ARM64_INS_UQSUB, + {AArch64_UQSUB_ZZZ_B, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUB_ZZZ_D, ARM64_INS_UQSUB, + {AArch64_UQSUB_ZZZ_D, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUB_ZZZ_H, ARM64_INS_UQSUB, + {AArch64_UQSUB_ZZZ_H, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUB_ZZZ_S, ARM64_INS_UQSUB, + {AArch64_UQSUB_ZZZ_S, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv16i8, ARM64_INS_UQSUB, + {AArch64_UQSUBv16i8, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv1i16, ARM64_INS_UQSUB, + {AArch64_UQSUBv1i16, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv1i32, ARM64_INS_UQSUB, + {AArch64_UQSUBv1i32, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv1i64, ARM64_INS_UQSUB, + {AArch64_UQSUBv1i64, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv1i8, ARM64_INS_UQSUB, + {AArch64_UQSUBv1i8, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv2i32, ARM64_INS_UQSUB, + {AArch64_UQSUBv2i32, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv2i64, ARM64_INS_UQSUB, + {AArch64_UQSUBv2i64, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv4i16, ARM64_INS_UQSUB, + {AArch64_UQSUBv4i16, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv4i32, ARM64_INS_UQSUB, + {AArch64_UQSUBv4i32, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv8i16, ARM64_INS_UQSUB, + {AArch64_UQSUBv8i16, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQSUBv8i8, ARM64_INS_UQSUB, + {AArch64_UQSUBv8i8, + ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQXTNv16i8, ARM64_INS_UQXTN2, + {AArch64_UQXTNv16i8, + ARM64_INS_UQXTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQXTNv1i16, ARM64_INS_UQXTN, + {AArch64_UQXTNv1i16, + ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQXTNv1i32, ARM64_INS_UQXTN, + {AArch64_UQXTNv1i32, + ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQXTNv1i8, ARM64_INS_UQXTN, + {AArch64_UQXTNv1i8, + ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQXTNv2i32, ARM64_INS_UQXTN, + {AArch64_UQXTNv2i32, + ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQXTNv4i16, ARM64_INS_UQXTN, + {AArch64_UQXTNv4i16, + ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQXTNv4i32, ARM64_INS_UQXTN2, + {AArch64_UQXTNv4i32, + ARM64_INS_UQXTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQXTNv8i16, ARM64_INS_UQXTN2, + {AArch64_UQXTNv8i16, + ARM64_INS_UQXTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UQXTNv8i8, ARM64_INS_UQXTN, + {AArch64_UQXTNv8i8, + ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URECPEv2i32, ARM64_INS_URECPE, + {AArch64_URECPEv2i32, + ARM64_INS_URECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URECPEv4i32, ARM64_INS_URECPE, + {AArch64_URECPEv4i32, + ARM64_INS_URECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URHADDv16i8, ARM64_INS_URHADD, + {AArch64_URHADDv16i8, + ARM64_INS_URHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URHADDv2i32, ARM64_INS_URHADD, + {AArch64_URHADDv2i32, + ARM64_INS_URHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URHADDv4i16, ARM64_INS_URHADD, + {AArch64_URHADDv4i16, + ARM64_INS_URHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URHADDv4i32, ARM64_INS_URHADD, + {AArch64_URHADDv4i32, + ARM64_INS_URHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URHADDv8i16, ARM64_INS_URHADD, + {AArch64_URHADDv8i16, + ARM64_INS_URHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URHADDv8i8, ARM64_INS_URHADD, + {AArch64_URHADDv8i8, + ARM64_INS_URHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHLv16i8, ARM64_INS_URSHL, + {AArch64_URSHLv16i8, + ARM64_INS_URSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHLv1i64, ARM64_INS_URSHL, + {AArch64_URSHLv1i64, + ARM64_INS_URSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHLv2i32, ARM64_INS_URSHL, + {AArch64_URSHLv2i32, + ARM64_INS_URSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHLv2i64, ARM64_INS_URSHL, + {AArch64_URSHLv2i64, + ARM64_INS_URSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHLv4i16, ARM64_INS_URSHL, + {AArch64_URSHLv4i16, + ARM64_INS_URSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHLv4i32, ARM64_INS_URSHL, + {AArch64_URSHLv4i32, + ARM64_INS_URSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHLv8i16, ARM64_INS_URSHL, + {AArch64_URSHLv8i16, + ARM64_INS_URSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHLv8i8, ARM64_INS_URSHL, + {AArch64_URSHLv8i8, + ARM64_INS_URSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHRd, ARM64_INS_URSHR, + {AArch64_URSHRd, + ARM64_INS_URSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHRv16i8_shift, ARM64_INS_URSHR, + {AArch64_URSHRv16i8_shift, + ARM64_INS_URSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHRv2i32_shift, ARM64_INS_URSHR, + {AArch64_URSHRv2i32_shift, + ARM64_INS_URSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHRv2i64_shift, ARM64_INS_URSHR, + {AArch64_URSHRv2i64_shift, + ARM64_INS_URSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHRv4i16_shift, ARM64_INS_URSHR, + {AArch64_URSHRv4i16_shift, + ARM64_INS_URSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHRv4i32_shift, ARM64_INS_URSHR, + {AArch64_URSHRv4i32_shift, + ARM64_INS_URSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHRv8i16_shift, ARM64_INS_URSHR, + {AArch64_URSHRv8i16_shift, + ARM64_INS_URSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSHRv8i8_shift, ARM64_INS_URSHR, + {AArch64_URSHRv8i8_shift, + ARM64_INS_URSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSQRTEv2i32, ARM64_INS_URSQRTE, + {AArch64_URSQRTEv2i32, + ARM64_INS_URSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSQRTEv4i32, ARM64_INS_URSQRTE, + {AArch64_URSQRTEv4i32, + ARM64_INS_URSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSRAd, ARM64_INS_URSRA, + {AArch64_URSRAd, + ARM64_INS_URSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSRAv16i8_shift, ARM64_INS_URSRA, + {AArch64_URSRAv16i8_shift, + ARM64_INS_URSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSRAv2i32_shift, ARM64_INS_URSRA, + {AArch64_URSRAv2i32_shift, + ARM64_INS_URSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSRAv2i64_shift, ARM64_INS_URSRA, + {AArch64_URSRAv2i64_shift, + ARM64_INS_URSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSRAv4i16_shift, ARM64_INS_URSRA, + {AArch64_URSRAv4i16_shift, + ARM64_INS_URSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSRAv4i32_shift, ARM64_INS_URSRA, + {AArch64_URSRAv4i32_shift, + ARM64_INS_URSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSRAv8i16_shift, ARM64_INS_URSRA, + {AArch64_URSRAv8i16_shift, + ARM64_INS_URSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_URSRAv8i8_shift, ARM64_INS_URSRA, + {AArch64_URSRAv8i8_shift, + ARM64_INS_URSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLLv16i8_shift, ARM64_INS_USHLL2, + {AArch64_USHLLv16i8_shift, + ARM64_INS_USHLL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLLv2i32_shift, ARM64_INS_USHLL, + {AArch64_USHLLv2i32_shift, + ARM64_INS_USHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLLv4i16_shift, ARM64_INS_USHLL, + {AArch64_USHLLv4i16_shift, + ARM64_INS_USHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLLv4i32_shift, ARM64_INS_USHLL2, + {AArch64_USHLLv4i32_shift, + ARM64_INS_USHLL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLLv8i16_shift, ARM64_INS_USHLL2, + {AArch64_USHLLv8i16_shift, + ARM64_INS_USHLL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLLv8i8_shift, ARM64_INS_USHLL, + {AArch64_USHLLv8i8_shift, + ARM64_INS_USHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLv16i8, ARM64_INS_USHL, + {AArch64_USHLv16i8, + ARM64_INS_USHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLv1i64, ARM64_INS_USHL, + {AArch64_USHLv1i64, + ARM64_INS_USHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLv2i32, ARM64_INS_USHL, + {AArch64_USHLv2i32, + ARM64_INS_USHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLv2i64, ARM64_INS_USHL, + {AArch64_USHLv2i64, + ARM64_INS_USHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLv4i16, ARM64_INS_USHL, + {AArch64_USHLv4i16, + ARM64_INS_USHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLv4i32, ARM64_INS_USHL, + {AArch64_USHLv4i32, + ARM64_INS_USHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLv8i16, ARM64_INS_USHL, + {AArch64_USHLv8i16, + ARM64_INS_USHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHLv8i8, ARM64_INS_USHL, + {AArch64_USHLv8i8, + ARM64_INS_USHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHRd, ARM64_INS_USHR, + {AArch64_USHRd, + ARM64_INS_USHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHRv16i8_shift, ARM64_INS_USHR, + {AArch64_USHRv16i8_shift, + ARM64_INS_USHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHRv2i32_shift, ARM64_INS_USHR, + {AArch64_USHRv2i32_shift, + ARM64_INS_USHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHRv2i64_shift, ARM64_INS_USHR, + {AArch64_USHRv2i64_shift, + ARM64_INS_USHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHRv4i16_shift, ARM64_INS_USHR, + {AArch64_USHRv4i16_shift, + ARM64_INS_USHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHRv4i32_shift, ARM64_INS_USHR, + {AArch64_USHRv4i32_shift, + ARM64_INS_USHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHRv8i16_shift, ARM64_INS_USHR, + {AArch64_USHRv8i16_shift, + ARM64_INS_USHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USHRv8i8_shift, ARM64_INS_USHR, + {AArch64_USHRv8i8_shift, + ARM64_INS_USHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv16i8, ARM64_INS_USQADD, + {AArch64_USQADDv16i8, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv1i16, ARM64_INS_USQADD, + {AArch64_USQADDv1i16, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv1i32, ARM64_INS_USQADD, + {AArch64_USQADDv1i32, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv1i64, ARM64_INS_USQADD, + {AArch64_USQADDv1i64, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv1i8, ARM64_INS_USQADD, + {AArch64_USQADDv1i8, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv2i32, ARM64_INS_USQADD, + {AArch64_USQADDv2i32, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv2i64, ARM64_INS_USQADD, + {AArch64_USQADDv2i64, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv4i16, ARM64_INS_USQADD, + {AArch64_USQADDv4i16, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv4i32, ARM64_INS_USQADD, + {AArch64_USQADDv4i32, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv8i16, ARM64_INS_USQADD, + {AArch64_USQADDv8i16, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USQADDv8i8, ARM64_INS_USQADD, + {AArch64_USQADDv8i8, + ARM64_INS_USQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USRAd, ARM64_INS_USRA, + {AArch64_USRAd, + ARM64_INS_USRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USRAv16i8_shift, ARM64_INS_USRA, + {AArch64_USRAv16i8_shift, + ARM64_INS_USRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USRAv2i32_shift, ARM64_INS_USRA, + {AArch64_USRAv2i32_shift, + ARM64_INS_USRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USRAv2i64_shift, ARM64_INS_USRA, + {AArch64_USRAv2i64_shift, + ARM64_INS_USRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USRAv4i16_shift, ARM64_INS_USRA, + {AArch64_USRAv4i16_shift, + ARM64_INS_USRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USRAv4i32_shift, ARM64_INS_USRA, + {AArch64_USRAv4i32_shift, + ARM64_INS_USRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USRAv8i16_shift, ARM64_INS_USRA, + {AArch64_USRAv8i16_shift, + ARM64_INS_USRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USRAv8i8_shift, ARM64_INS_USRA, + {AArch64_USRAv8i8_shift, + ARM64_INS_USRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBLv16i8_v8i16, ARM64_INS_USUBL2, + {AArch64_USUBLv16i8_v8i16, + ARM64_INS_USUBL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBLv2i32_v2i64, ARM64_INS_USUBL, + {AArch64_USUBLv2i32_v2i64, + ARM64_INS_USUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBLv4i16_v4i32, ARM64_INS_USUBL, + {AArch64_USUBLv4i16_v4i32, + ARM64_INS_USUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBLv4i32_v2i64, ARM64_INS_USUBL2, + {AArch64_USUBLv4i32_v2i64, + ARM64_INS_USUBL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBLv8i16_v4i32, ARM64_INS_USUBL2, + {AArch64_USUBLv8i16_v4i32, + ARM64_INS_USUBL2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBLv8i8_v8i16, ARM64_INS_USUBL, + {AArch64_USUBLv8i8_v8i16, + ARM64_INS_USUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBWv16i8_v8i16, ARM64_INS_USUBW2, + {AArch64_USUBWv16i8_v8i16, + ARM64_INS_USUBW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBWv2i32_v2i64, ARM64_INS_USUBW, + {AArch64_USUBWv2i32_v2i64, + ARM64_INS_USUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBWv4i16_v4i32, ARM64_INS_USUBW, + {AArch64_USUBWv4i16_v4i32, + ARM64_INS_USUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBWv4i32_v2i64, ARM64_INS_USUBW2, + {AArch64_USUBWv4i32_v2i64, + ARM64_INS_USUBW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBWv8i16_v4i32, ARM64_INS_USUBW2, + {AArch64_USUBWv8i16_v4i32, + ARM64_INS_USUBW2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_USUBWv8i8_v8i16, ARM64_INS_USUBW, + {AArch64_USUBWv8i8_v8i16, + ARM64_INS_USUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UUNPKHI_ZZ_D, ARM64_INS_UUNPKHI, + {AArch64_UUNPKHI_ZZ_D, + ARM64_INS_UUNPKHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UUNPKHI_ZZ_H, ARM64_INS_UUNPKHI, + {AArch64_UUNPKHI_ZZ_H, + ARM64_INS_UUNPKHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UUNPKHI_ZZ_S, ARM64_INS_UUNPKHI, + {AArch64_UUNPKHI_ZZ_S, + ARM64_INS_UUNPKHI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UUNPKLO_ZZ_D, ARM64_INS_UUNPKLO, + {AArch64_UUNPKLO_ZZ_D, + ARM64_INS_UUNPKLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UUNPKLO_ZZ_H, ARM64_INS_UUNPKLO, + {AArch64_UUNPKLO_ZZ_H, + ARM64_INS_UUNPKLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UUNPKLO_ZZ_S, ARM64_INS_UUNPKLO, + {AArch64_UUNPKLO_ZZ_S, + ARM64_INS_UUNPKLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UXTB_ZPmZ_D, ARM64_INS_UXTB, + {AArch64_UXTB_ZPmZ_D, + ARM64_INS_UXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UXTB_ZPmZ_H, ARM64_INS_UXTB, + {AArch64_UXTB_ZPmZ_H, + ARM64_INS_UXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UXTB_ZPmZ_S, ARM64_INS_UXTB, + {AArch64_UXTB_ZPmZ_S, + ARM64_INS_UXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UXTH_ZPmZ_D, ARM64_INS_UXTH, + {AArch64_UXTH_ZPmZ_D, + ARM64_INS_UXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UXTH_ZPmZ_S, ARM64_INS_UXTH, + {AArch64_UXTH_ZPmZ_S, + ARM64_INS_UXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UXTW_ZPmZ_D, ARM64_INS_UXTW, + {AArch64_UXTW_ZPmZ_D, + ARM64_INS_UXTW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1_PPP_B, ARM64_INS_UZP1, + {AArch64_UZP1_PPP_B, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1_PPP_D, ARM64_INS_UZP1, + {AArch64_UZP1_PPP_D, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1_PPP_H, ARM64_INS_UZP1, + {AArch64_UZP1_PPP_H, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1_PPP_S, ARM64_INS_UZP1, + {AArch64_UZP1_PPP_S, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1_ZZZ_B, ARM64_INS_UZP1, + {AArch64_UZP1_ZZZ_B, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1_ZZZ_D, ARM64_INS_UZP1, + {AArch64_UZP1_ZZZ_D, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1_ZZZ_H, ARM64_INS_UZP1, + {AArch64_UZP1_ZZZ_H, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1_ZZZ_S, ARM64_INS_UZP1, + {AArch64_UZP1_ZZZ_S, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1v16i8, ARM64_INS_UZP1, + {AArch64_UZP1v16i8, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1v2i32, ARM64_INS_UZP1, + {AArch64_UZP1v2i32, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1v2i64, ARM64_INS_UZP1, + {AArch64_UZP1v2i64, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1v4i16, ARM64_INS_UZP1, + {AArch64_UZP1v4i16, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1v4i32, ARM64_INS_UZP1, + {AArch64_UZP1v4i32, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1v8i16, ARM64_INS_UZP1, + {AArch64_UZP1v8i16, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP1v8i8, ARM64_INS_UZP1, + {AArch64_UZP1v8i8, + ARM64_INS_UZP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2_PPP_B, ARM64_INS_UZP2, + {AArch64_UZP2_PPP_B, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2_PPP_D, ARM64_INS_UZP2, + {AArch64_UZP2_PPP_D, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2_PPP_H, ARM64_INS_UZP2, + {AArch64_UZP2_PPP_H, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2_PPP_S, ARM64_INS_UZP2, + {AArch64_UZP2_PPP_S, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2_ZZZ_B, ARM64_INS_UZP2, + {AArch64_UZP2_ZZZ_B, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2_ZZZ_D, ARM64_INS_UZP2, + {AArch64_UZP2_ZZZ_D, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2_ZZZ_H, ARM64_INS_UZP2, + {AArch64_UZP2_ZZZ_H, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2_ZZZ_S, ARM64_INS_UZP2, + {AArch64_UZP2_ZZZ_S, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2v16i8, ARM64_INS_UZP2, + {AArch64_UZP2v16i8, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2v2i32, ARM64_INS_UZP2, + {AArch64_UZP2v2i32, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2v2i64, ARM64_INS_UZP2, + {AArch64_UZP2v2i64, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2v4i16, ARM64_INS_UZP2, + {AArch64_UZP2v4i16, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2v4i32, ARM64_INS_UZP2, + {AArch64_UZP2v4i32, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2v8i16, ARM64_INS_UZP2, + {AArch64_UZP2v8i16, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_UZP2v8i8, ARM64_INS_UZP2, + {AArch64_UZP2v8i8, + ARM64_INS_UZP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELE_PWW_B, ARM64_INS_WHILELE, + {AArch64_WHILELE_PWW_B, + ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELE_PWW_D, ARM64_INS_WHILELE, + {AArch64_WHILELE_PWW_D, + ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELE_PWW_H, ARM64_INS_WHILELE, + {AArch64_WHILELE_PWW_H, + ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELE_PWW_S, ARM64_INS_WHILELE, + {AArch64_WHILELE_PWW_S, + ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELE_PXX_B, ARM64_INS_WHILELE, + {AArch64_WHILELE_PXX_B, + ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELE_PXX_D, ARM64_INS_WHILELE, + {AArch64_WHILELE_PXX_D, + ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELE_PXX_H, ARM64_INS_WHILELE, + {AArch64_WHILELE_PXX_H, + ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELE_PXX_S, ARM64_INS_WHILELE, + {AArch64_WHILELE_PXX_S, + ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELO_PWW_B, ARM64_INS_WHILELO, + {AArch64_WHILELO_PWW_B, + ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELO_PWW_D, ARM64_INS_WHILELO, + {AArch64_WHILELO_PWW_D, + ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELO_PWW_H, ARM64_INS_WHILELO, + {AArch64_WHILELO_PWW_H, + ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELO_PWW_S, ARM64_INS_WHILELO, + {AArch64_WHILELO_PWW_S, + ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELO_PXX_B, ARM64_INS_WHILELO, + {AArch64_WHILELO_PXX_B, + ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELO_PXX_D, ARM64_INS_WHILELO, + {AArch64_WHILELO_PXX_D, + ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELO_PXX_H, ARM64_INS_WHILELO, + {AArch64_WHILELO_PXX_H, + ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELO_PXX_S, ARM64_INS_WHILELO, + {AArch64_WHILELO_PXX_S, + ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELS_PWW_B, ARM64_INS_WHILELS, + {AArch64_WHILELS_PWW_B, + ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELS_PWW_D, ARM64_INS_WHILELS, + {AArch64_WHILELS_PWW_D, + ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELS_PWW_H, ARM64_INS_WHILELS, + {AArch64_WHILELS_PWW_H, + ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELS_PWW_S, ARM64_INS_WHILELS, + {AArch64_WHILELS_PWW_S, + ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELS_PXX_B, ARM64_INS_WHILELS, + {AArch64_WHILELS_PXX_B, + ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELS_PXX_D, ARM64_INS_WHILELS, + {AArch64_WHILELS_PXX_D, + ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELS_PXX_H, ARM64_INS_WHILELS, + {AArch64_WHILELS_PXX_H, + ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELS_PXX_S, ARM64_INS_WHILELS, + {AArch64_WHILELS_PXX_S, + ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELT_PWW_B, ARM64_INS_WHILELT, + {AArch64_WHILELT_PWW_B, + ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELT_PWW_D, ARM64_INS_WHILELT, + {AArch64_WHILELT_PWW_D, + ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELT_PWW_H, ARM64_INS_WHILELT, + {AArch64_WHILELT_PWW_H, + ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELT_PWW_S, ARM64_INS_WHILELT, + {AArch64_WHILELT_PWW_S, + ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELT_PXX_B, ARM64_INS_WHILELT, + {AArch64_WHILELT_PXX_B, + ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELT_PXX_D, ARM64_INS_WHILELT, + {AArch64_WHILELT_PXX_D, + ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELT_PXX_H, ARM64_INS_WHILELT, + {AArch64_WHILELT_PXX_H, + ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WHILELT_PXX_S, ARM64_INS_WHILELT, + {AArch64_WHILELT_PXX_S, + ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_WRFFR, ARM64_INS_WRFFR, + {AArch64_WRFFR, + ARM64_INS_WRFFR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XAR, ARM64_INS_XAR, + {AArch64_XAR, + ARM64_INS_XAR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XPACD, ARM64_INS_XPACD, + {AArch64_XPACD, + ARM64_INS_XPACD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XPACI, ARM64_INS_XPACI, + {AArch64_XPACI, + ARM64_INS_XPACI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XPACLRI, ARM64_INS_XPACLRI, + {AArch64_XPACLRI, + ARM64_INS_XPACLRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_PAC, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XTNv16i8, ARM64_INS_XTN2, + {AArch64_XTNv16i8, + ARM64_INS_XTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XTNv2i32, ARM64_INS_XTN, + {AArch64_XTNv2i32, + ARM64_INS_XTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XTNv4i16, ARM64_INS_XTN, + {AArch64_XTNv4i16, + ARM64_INS_XTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XTNv4i32, ARM64_INS_XTN2, + {AArch64_XTNv4i32, + ARM64_INS_XTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XTNv8i16, ARM64_INS_XTN2, + {AArch64_XTNv8i16, + ARM64_INS_XTN2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_XTNv8i8, ARM64_INS_XTN, + {AArch64_XTNv8i8, + ARM64_INS_XTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1_PPP_B, ARM64_INS_ZIP1, + {AArch64_ZIP1_PPP_B, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1_PPP_D, ARM64_INS_ZIP1, + {AArch64_ZIP1_PPP_D, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1_PPP_H, ARM64_INS_ZIP1, + {AArch64_ZIP1_PPP_H, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1_PPP_S, ARM64_INS_ZIP1, + {AArch64_ZIP1_PPP_S, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1_ZZZ_B, ARM64_INS_ZIP1, + {AArch64_ZIP1_ZZZ_B, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1_ZZZ_D, ARM64_INS_ZIP1, + {AArch64_ZIP1_ZZZ_D, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1_ZZZ_H, ARM64_INS_ZIP1, + {AArch64_ZIP1_ZZZ_H, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1_ZZZ_S, ARM64_INS_ZIP1, + {AArch64_ZIP1_ZZZ_S, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1v16i8, ARM64_INS_ZIP1, + {AArch64_ZIP1v16i8, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1v2i32, ARM64_INS_ZIP1, + {AArch64_ZIP1v2i32, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1v2i64, ARM64_INS_ZIP1, + {AArch64_ZIP1v2i64, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1v4i16, ARM64_INS_ZIP1, + {AArch64_ZIP1v4i16, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1v4i32, ARM64_INS_ZIP1, + {AArch64_ZIP1v4i32, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1v8i16, ARM64_INS_ZIP1, + {AArch64_ZIP1v8i16, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP1v8i8, ARM64_INS_ZIP1, + {AArch64_ZIP1v8i8, + ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2_PPP_B, ARM64_INS_ZIP2, + {AArch64_ZIP2_PPP_B, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2_PPP_D, ARM64_INS_ZIP2, + {AArch64_ZIP2_PPP_D, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2_PPP_H, ARM64_INS_ZIP2, + {AArch64_ZIP2_PPP_H, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2_PPP_S, ARM64_INS_ZIP2, + {AArch64_ZIP2_PPP_S, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2_ZZZ_B, ARM64_INS_ZIP2, + {AArch64_ZIP2_ZZZ_B, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2_ZZZ_D, ARM64_INS_ZIP2, + {AArch64_ZIP2_ZZZ_D, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2_ZZZ_H, ARM64_INS_ZIP2, + {AArch64_ZIP2_ZZZ_H, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2_ZZZ_S, ARM64_INS_ZIP2, + {AArch64_ZIP2_ZZZ_S, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2v16i8, ARM64_INS_ZIP2, + {AArch64_ZIP2v16i8, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2v2i32, ARM64_INS_ZIP2, + {AArch64_ZIP2v2i32, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2v2i64, ARM64_INS_ZIP2, + {AArch64_ZIP2v2i64, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2v4i16, ARM64_INS_ZIP2, + {AArch64_ZIP2v4i16, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2v4i32, ARM64_INS_ZIP2, + {AArch64_ZIP2v4i32, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2v8i16, ARM64_INS_ZIP2, + {AArch64_ZIP2v8i16, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_ZIP2v8i8, ARM64_INS_ZIP2, + {AArch64_ZIP2v8i8, + ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM64_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - AArch64_anonymous_1349, ARM64_INS_PFIRST, + {AArch64_PFIRST_B, + ARM64_INS_PFIRST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, + + {AArch64_anonymous_5365, + ARM64_INS_INVALID, + #ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 + #endif + }, diff --git a/arch/AArch64/AArch64MappingInsnName.inc b/arch/AArch64/AArch64MappingInsnName.inc index e57765b368..d15b1c3215 100644 --- a/arch/AArch64/AArch64MappingInsnName.inc +++ b/arch/AArch64/AArch64MappingInsnName.inc @@ -1,943 +1,944 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* This is auto-gen data for Capstone disassembly engine + * (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ - "abs", // ARM64_INS_ABS, - "adc", // ARM64_INS_ADC, - "adcs", // ARM64_INS_ADCS, - "add", // ARM64_INS_ADD, - "addhn", // ARM64_INS_ADDHN, - "addhn2", // ARM64_INS_ADDHN2, - "addp", // ARM64_INS_ADDP, - "addpl", // ARM64_INS_ADDPL, - "adds", // ARM64_INS_ADDS, - "addv", // ARM64_INS_ADDV, - "addvl", // ARM64_INS_ADDVL, - "adr", // ARM64_INS_ADR, - "adrp", // ARM64_INS_ADRP, - "aesd", // ARM64_INS_AESD, - "aese", // ARM64_INS_AESE, - "aesimc", // ARM64_INS_AESIMC, - "aesmc", // ARM64_INS_AESMC, - "and", // ARM64_INS_AND, - "ands", // ARM64_INS_ANDS, - "andv", // ARM64_INS_ANDV, - "asr", // ARM64_INS_ASR, - "asrd", // ARM64_INS_ASRD, - "asrr", // ARM64_INS_ASRR, - "asrv", // ARM64_INS_ASRV, - "autda", // ARM64_INS_AUTDA, - "autdb", // ARM64_INS_AUTDB, - "autdza", // ARM64_INS_AUTDZA, - "autdzb", // ARM64_INS_AUTDZB, - "autia", // ARM64_INS_AUTIA, - "autia1716", // ARM64_INS_AUTIA1716, - "autiasp", // ARM64_INS_AUTIASP, - "autiaz", // ARM64_INS_AUTIAZ, - "autib", // ARM64_INS_AUTIB, - "autib1716", // ARM64_INS_AUTIB1716, - "autibsp", // ARM64_INS_AUTIBSP, - "autibz", // ARM64_INS_AUTIBZ, - "autiza", // ARM64_INS_AUTIZA, - "autizb", // ARM64_INS_AUTIZB, - "b", // ARM64_INS_B, - "bcax", // ARM64_INS_BCAX, - "bfm", // ARM64_INS_BFM, - "bic", // ARM64_INS_BIC, - "bics", // ARM64_INS_BICS, - "bif", // ARM64_INS_BIF, - "bit", // ARM64_INS_BIT, - "bl", // ARM64_INS_BL, - "blr", // ARM64_INS_BLR, - "blraa", // ARM64_INS_BLRAA, - "blraaz", // ARM64_INS_BLRAAZ, - "blrab", // ARM64_INS_BLRAB, - "blrabz", // ARM64_INS_BLRABZ, - "br", // ARM64_INS_BR, - "braa", // ARM64_INS_BRAA, - "braaz", // ARM64_INS_BRAAZ, - "brab", // ARM64_INS_BRAB, - "brabz", // ARM64_INS_BRABZ, - "brk", // ARM64_INS_BRK, - "brka", // ARM64_INS_BRKA, - "brkas", // ARM64_INS_BRKAS, - "brkb", // ARM64_INS_BRKB, - "brkbs", // ARM64_INS_BRKBS, - "brkn", // ARM64_INS_BRKN, - "brkns", // ARM64_INS_BRKNS, - "brkpa", // ARM64_INS_BRKPA, - "brkpas", // ARM64_INS_BRKPAS, - "brkpb", // ARM64_INS_BRKPB, - "brkpbs", // ARM64_INS_BRKPBS, - "bsl", // ARM64_INS_BSL, - "cas", // ARM64_INS_CAS, - "casa", // ARM64_INS_CASA, - "casab", // ARM64_INS_CASAB, - "casah", // ARM64_INS_CASAH, - "casal", // ARM64_INS_CASAL, - "casalb", // ARM64_INS_CASALB, - "casalh", // ARM64_INS_CASALH, - "casb", // ARM64_INS_CASB, - "cash", // ARM64_INS_CASH, - "casl", // ARM64_INS_CASL, - "caslb", // ARM64_INS_CASLB, - "caslh", // ARM64_INS_CASLH, - "casp", // ARM64_INS_CASP, - "caspa", // ARM64_INS_CASPA, - "caspal", // ARM64_INS_CASPAL, - "caspl", // ARM64_INS_CASPL, - "cbnz", // ARM64_INS_CBNZ, - "cbz", // ARM64_INS_CBZ, - "ccmn", // ARM64_INS_CCMN, - "ccmp", // ARM64_INS_CCMP, - "cfinv", // ARM64_INS_CFINV, - "cinc", // ARM64_INS_CINC, - "cinv", // ARM64_INS_CINV, - "clasta", // ARM64_INS_CLASTA, - "clastb", // ARM64_INS_CLASTB, - "clrex", // ARM64_INS_CLREX, - "cls", // ARM64_INS_CLS, - "clz", // ARM64_INS_CLZ, - "cmeq", // ARM64_INS_CMEQ, - "cmge", // ARM64_INS_CMGE, - "cmgt", // ARM64_INS_CMGT, - "cmhi", // ARM64_INS_CMHI, - "cmhs", // ARM64_INS_CMHS, - "cmle", // ARM64_INS_CMLE, - "cmlo", // ARM64_INS_CMLO, - "cmls", // ARM64_INS_CMLS, - "cmlt", // ARM64_INS_CMLT, - "cmn", // ARM64_INS_CMN, - "cmp", // ARM64_INS_CMP, - "cmpeq", // ARM64_INS_CMPEQ, - "cmpge", // ARM64_INS_CMPGE, - "cmpgt", // ARM64_INS_CMPGT, - "cmphi", // ARM64_INS_CMPHI, - "cmphs", // ARM64_INS_CMPHS, - "cmple", // ARM64_INS_CMPLE, - "cmplo", // ARM64_INS_CMPLO, - "cmpls", // ARM64_INS_CMPLS, - "cmplt", // ARM64_INS_CMPLT, - "cmpne", // ARM64_INS_CMPNE, - "cmtst", // ARM64_INS_CMTST, - "cneg", // ARM64_INS_CNEG, - "cnot", // ARM64_INS_CNOT, - "cnt", // ARM64_INS_CNT, - "cntb", // ARM64_INS_CNTB, - "cntd", // ARM64_INS_CNTD, - "cnth", // ARM64_INS_CNTH, - "cntp", // ARM64_INS_CNTP, - "cntw", // ARM64_INS_CNTW, - "compact", // ARM64_INS_COMPACT, - "cpy", // ARM64_INS_CPY, - "crc32b", // ARM64_INS_CRC32B, - "crc32cb", // ARM64_INS_CRC32CB, - "crc32ch", // ARM64_INS_CRC32CH, - "crc32cw", // ARM64_INS_CRC32CW, - "crc32cx", // ARM64_INS_CRC32CX, - "crc32h", // ARM64_INS_CRC32H, - "crc32w", // ARM64_INS_CRC32W, - "crc32x", // ARM64_INS_CRC32X, - "csdb", // ARM64_INS_CSDB, - "csel", // ARM64_INS_CSEL, - "cset", // ARM64_INS_CSET, - "csetm", // ARM64_INS_CSETM, - "csinc", // ARM64_INS_CSINC, - "csinv", // ARM64_INS_CSINV, - "csneg", // ARM64_INS_CSNEG, - "ctermeq", // ARM64_INS_CTERMEQ, - "ctermne", // ARM64_INS_CTERMNE, - "dcps1", // ARM64_INS_DCPS1, - "dcps2", // ARM64_INS_DCPS2, - "dcps3", // ARM64_INS_DCPS3, - "decb", // ARM64_INS_DECB, - "decd", // ARM64_INS_DECD, - "dech", // ARM64_INS_DECH, - "decp", // ARM64_INS_DECP, - "decw", // ARM64_INS_DECW, - "dmb", // ARM64_INS_DMB, - "drps", // ARM64_INS_DRPS, - "dsb", // ARM64_INS_DSB, - "dup", // ARM64_INS_DUP, - "dupm", // ARM64_INS_DUPM, - "eon", // ARM64_INS_EON, - "eor", // ARM64_INS_EOR, - "eor3", // ARM64_INS_EOR3, - "eors", // ARM64_INS_EORS, - "eorv", // ARM64_INS_EORV, - "eret", // ARM64_INS_ERET, - "eretaa", // ARM64_INS_ERETAA, - "eretab", // ARM64_INS_ERETAB, - "esb", // ARM64_INS_ESB, - "ext", // ARM64_INS_EXT, - "extr", // ARM64_INS_EXTR, - "fabd", // ARM64_INS_FABD, - "fabs", // ARM64_INS_FABS, - "facge", // ARM64_INS_FACGE, - "facgt", // ARM64_INS_FACGT, - "facle", // ARM64_INS_FACLE, - "faclt", // ARM64_INS_FACLT, - "fadd", // ARM64_INS_FADD, - "fadda", // ARM64_INS_FADDA, - "faddp", // ARM64_INS_FADDP, - "faddv", // ARM64_INS_FADDV, - "fcadd", // ARM64_INS_FCADD, - "fccmp", // ARM64_INS_FCCMP, - "fccmpe", // ARM64_INS_FCCMPE, - "fcmeq", // ARM64_INS_FCMEQ, - "fcmge", // ARM64_INS_FCMGE, - "fcmgt", // ARM64_INS_FCMGT, - "fcmla", // ARM64_INS_FCMLA, - "fcmle", // ARM64_INS_FCMLE, - "fcmlt", // ARM64_INS_FCMLT, - "fcmne", // ARM64_INS_FCMNE, - "fcmp", // ARM64_INS_FCMP, - "fcmpe", // ARM64_INS_FCMPE, - "fcmuo", // ARM64_INS_FCMUO, - "fcpy", // ARM64_INS_FCPY, - "fcsel", // ARM64_INS_FCSEL, - "fcvt", // ARM64_INS_FCVT, - "fcvtas", // ARM64_INS_FCVTAS, - "fcvtau", // ARM64_INS_FCVTAU, - "fcvtl", // ARM64_INS_FCVTL, - "fcvtl2", // ARM64_INS_FCVTL2, - "fcvtms", // ARM64_INS_FCVTMS, - "fcvtmu", // ARM64_INS_FCVTMU, - "fcvtn", // ARM64_INS_FCVTN, - "fcvtn2", // ARM64_INS_FCVTN2, - "fcvtns", // ARM64_INS_FCVTNS, - "fcvtnu", // ARM64_INS_FCVTNU, - "fcvtps", // ARM64_INS_FCVTPS, - "fcvtpu", // ARM64_INS_FCVTPU, - "fcvtxn", // ARM64_INS_FCVTXN, - "fcvtxn2", // ARM64_INS_FCVTXN2, - "fcvtzs", // ARM64_INS_FCVTZS, - "fcvtzu", // ARM64_INS_FCVTZU, - "fdiv", // ARM64_INS_FDIV, - "fdivr", // ARM64_INS_FDIVR, - "fdup", // ARM64_INS_FDUP, - "fexpa", // ARM64_INS_FEXPA, - "fjcvtzs", // ARM64_INS_FJCVTZS, - "fmad", // ARM64_INS_FMAD, - "fmadd", // ARM64_INS_FMADD, - "fmax", // ARM64_INS_FMAX, - "fmaxnm", // ARM64_INS_FMAXNM, - "fmaxnmp", // ARM64_INS_FMAXNMP, - "fmaxnmv", // ARM64_INS_FMAXNMV, - "fmaxp", // ARM64_INS_FMAXP, - "fmaxv", // ARM64_INS_FMAXV, - "fmin", // ARM64_INS_FMIN, - "fminnm", // ARM64_INS_FMINNM, - "fminnmp", // ARM64_INS_FMINNMP, - "fminnmv", // ARM64_INS_FMINNMV, - "fminp", // ARM64_INS_FMINP, - "fminv", // ARM64_INS_FMINV, - "fmla", // ARM64_INS_FMLA, - "fmls", // ARM64_INS_FMLS, - "fmov", // ARM64_INS_FMOV, - "fmsb", // ARM64_INS_FMSB, - "fmsub", // ARM64_INS_FMSUB, - "fmul", // ARM64_INS_FMUL, - "fmulx", // ARM64_INS_FMULX, - "fneg", // ARM64_INS_FNEG, - "fnmad", // ARM64_INS_FNMAD, - "fnmadd", // ARM64_INS_FNMADD, - "fnmla", // ARM64_INS_FNMLA, - "fnmls", // ARM64_INS_FNMLS, - "fnmsb", // ARM64_INS_FNMSB, - "fnmsub", // ARM64_INS_FNMSUB, - "fnmul", // ARM64_INS_FNMUL, - "frecpe", // ARM64_INS_FRECPE, - "frecps", // ARM64_INS_FRECPS, - "frecpx", // ARM64_INS_FRECPX, - "frinta", // ARM64_INS_FRINTA, - "frinti", // ARM64_INS_FRINTI, - "frintm", // ARM64_INS_FRINTM, - "frintn", // ARM64_INS_FRINTN, - "frintp", // ARM64_INS_FRINTP, - "frintx", // ARM64_INS_FRINTX, - "frintz", // ARM64_INS_FRINTZ, - "frsqrte", // ARM64_INS_FRSQRTE, - "frsqrts", // ARM64_INS_FRSQRTS, - "fscale", // ARM64_INS_FSCALE, - "fsqrt", // ARM64_INS_FSQRT, - "fsub", // ARM64_INS_FSUB, - "fsubr", // ARM64_INS_FSUBR, - "ftmad", // ARM64_INS_FTMAD, - "ftsmul", // ARM64_INS_FTSMUL, - "ftssel", // ARM64_INS_FTSSEL, - "hint", // ARM64_INS_HINT, - "hlt", // ARM64_INS_HLT, - "hvc", // ARM64_INS_HVC, - "incb", // ARM64_INS_INCB, - "incd", // ARM64_INS_INCD, - "inch", // ARM64_INS_INCH, - "incp", // ARM64_INS_INCP, - "incw", // ARM64_INS_INCW, - "index", // ARM64_INS_INDEX, - "ins", // ARM64_INS_INS, - "insr", // ARM64_INS_INSR, - "isb", // ARM64_INS_ISB, - "lasta", // ARM64_INS_LASTA, - "lastb", // ARM64_INS_LASTB, - "ld1", // ARM64_INS_LD1, - "ld1b", // ARM64_INS_LD1B, - "ld1d", // ARM64_INS_LD1D, - "ld1h", // ARM64_INS_LD1H, - "ld1r", // ARM64_INS_LD1R, - "ld1rb", // ARM64_INS_LD1RB, - "ld1rd", // ARM64_INS_LD1RD, - "ld1rh", // ARM64_INS_LD1RH, - "ld1rqb", // ARM64_INS_LD1RQB, - "ld1rqd", // ARM64_INS_LD1RQD, - "ld1rqh", // ARM64_INS_LD1RQH, - "ld1rqw", // ARM64_INS_LD1RQW, - "ld1rsb", // ARM64_INS_LD1RSB, - "ld1rsh", // ARM64_INS_LD1RSH, - "ld1rsw", // ARM64_INS_LD1RSW, - "ld1rw", // ARM64_INS_LD1RW, - "ld1sb", // ARM64_INS_LD1SB, - "ld1sh", // ARM64_INS_LD1SH, - "ld1sw", // ARM64_INS_LD1SW, - "ld1w", // ARM64_INS_LD1W, - "ld2", // ARM64_INS_LD2, - "ld2b", // ARM64_INS_LD2B, - "ld2d", // ARM64_INS_LD2D, - "ld2h", // ARM64_INS_LD2H, - "ld2r", // ARM64_INS_LD2R, - "ld2w", // ARM64_INS_LD2W, - "ld3", // ARM64_INS_LD3, - "ld3b", // ARM64_INS_LD3B, - "ld3d", // ARM64_INS_LD3D, - "ld3h", // ARM64_INS_LD3H, - "ld3r", // ARM64_INS_LD3R, - "ld3w", // ARM64_INS_LD3W, - "ld4", // ARM64_INS_LD4, - "ld4b", // ARM64_INS_LD4B, - "ld4d", // ARM64_INS_LD4D, - "ld4h", // ARM64_INS_LD4H, - "ld4r", // ARM64_INS_LD4R, - "ld4w", // ARM64_INS_LD4W, - "ldadd", // ARM64_INS_LDADD, - "ldadda", // ARM64_INS_LDADDA, - "ldaddab", // ARM64_INS_LDADDAB, - "ldaddah", // ARM64_INS_LDADDAH, - "ldaddal", // ARM64_INS_LDADDAL, - "ldaddalb", // ARM64_INS_LDADDALB, - "ldaddalh", // ARM64_INS_LDADDALH, - "ldaddb", // ARM64_INS_LDADDB, - "ldaddh", // ARM64_INS_LDADDH, - "ldaddl", // ARM64_INS_LDADDL, - "ldaddlb", // ARM64_INS_LDADDLB, - "ldaddlh", // ARM64_INS_LDADDLH, - "ldapr", // ARM64_INS_LDAPR, - "ldaprb", // ARM64_INS_LDAPRB, - "ldaprh", // ARM64_INS_LDAPRH, - "ldapur", // ARM64_INS_LDAPUR, - "ldapurb", // ARM64_INS_LDAPURB, - "ldapurh", // ARM64_INS_LDAPURH, - "ldapursb", // ARM64_INS_LDAPURSB, - "ldapursh", // ARM64_INS_LDAPURSH, - "ldapursw", // ARM64_INS_LDAPURSW, - "ldar", // ARM64_INS_LDAR, - "ldarb", // ARM64_INS_LDARB, - "ldarh", // ARM64_INS_LDARH, - "ldaxp", // ARM64_INS_LDAXP, - "ldaxr", // ARM64_INS_LDAXR, - "ldaxrb", // ARM64_INS_LDAXRB, - "ldaxrh", // ARM64_INS_LDAXRH, - "ldclr", // ARM64_INS_LDCLR, - "ldclra", // ARM64_INS_LDCLRA, - "ldclrab", // ARM64_INS_LDCLRAB, - "ldclrah", // ARM64_INS_LDCLRAH, - "ldclral", // ARM64_INS_LDCLRAL, - "ldclralb", // ARM64_INS_LDCLRALB, - "ldclralh", // ARM64_INS_LDCLRALH, - "ldclrb", // ARM64_INS_LDCLRB, - "ldclrh", // ARM64_INS_LDCLRH, - "ldclrl", // ARM64_INS_LDCLRL, - "ldclrlb", // ARM64_INS_LDCLRLB, - "ldclrlh", // ARM64_INS_LDCLRLH, - "ldeor", // ARM64_INS_LDEOR, - "ldeora", // ARM64_INS_LDEORA, - "ldeorab", // ARM64_INS_LDEORAB, - "ldeorah", // ARM64_INS_LDEORAH, - "ldeoral", // ARM64_INS_LDEORAL, - "ldeoralb", // ARM64_INS_LDEORALB, - "ldeoralh", // ARM64_INS_LDEORALH, - "ldeorb", // ARM64_INS_LDEORB, - "ldeorh", // ARM64_INS_LDEORH, - "ldeorl", // ARM64_INS_LDEORL, - "ldeorlb", // ARM64_INS_LDEORLB, - "ldeorlh", // ARM64_INS_LDEORLH, - "ldff1b", // ARM64_INS_LDFF1B, - "ldff1d", // ARM64_INS_LDFF1D, - "ldff1h", // ARM64_INS_LDFF1H, - "ldff1sb", // ARM64_INS_LDFF1SB, - "ldff1sh", // ARM64_INS_LDFF1SH, - "ldff1sw", // ARM64_INS_LDFF1SW, - "ldff1w", // ARM64_INS_LDFF1W, - "ldlar", // ARM64_INS_LDLAR, - "ldlarb", // ARM64_INS_LDLARB, - "ldlarh", // ARM64_INS_LDLARH, - "ldnf1b", // ARM64_INS_LDNF1B, - "ldnf1d", // ARM64_INS_LDNF1D, - "ldnf1h", // ARM64_INS_LDNF1H, - "ldnf1sb", // ARM64_INS_LDNF1SB, - "ldnf1sh", // ARM64_INS_LDNF1SH, - "ldnf1sw", // ARM64_INS_LDNF1SW, - "ldnf1w", // ARM64_INS_LDNF1W, - "ldnp", // ARM64_INS_LDNP, - "ldnt1b", // ARM64_INS_LDNT1B, - "ldnt1d", // ARM64_INS_LDNT1D, - "ldnt1h", // ARM64_INS_LDNT1H, - "ldnt1w", // ARM64_INS_LDNT1W, - "ldp", // ARM64_INS_LDP, - "ldpsw", // ARM64_INS_LDPSW, - "ldr", // ARM64_INS_LDR, - "ldraa", // ARM64_INS_LDRAA, - "ldrab", // ARM64_INS_LDRAB, - "ldrb", // ARM64_INS_LDRB, - "ldrh", // ARM64_INS_LDRH, - "ldrsb", // ARM64_INS_LDRSB, - "ldrsh", // ARM64_INS_LDRSH, - "ldrsw", // ARM64_INS_LDRSW, - "ldset", // ARM64_INS_LDSET, - "ldseta", // ARM64_INS_LDSETA, - "ldsetab", // ARM64_INS_LDSETAB, - "ldsetah", // ARM64_INS_LDSETAH, - "ldsetal", // ARM64_INS_LDSETAL, - "ldsetalb", // ARM64_INS_LDSETALB, - "ldsetalh", // ARM64_INS_LDSETALH, - "ldsetb", // ARM64_INS_LDSETB, - "ldseth", // ARM64_INS_LDSETH, - "ldsetl", // ARM64_INS_LDSETL, - "ldsetlb", // ARM64_INS_LDSETLB, - "ldsetlh", // ARM64_INS_LDSETLH, - "ldsmax", // ARM64_INS_LDSMAX, - "ldsmaxa", // ARM64_INS_LDSMAXA, - "ldsmaxab", // ARM64_INS_LDSMAXAB, - "ldsmaxah", // ARM64_INS_LDSMAXAH, - "ldsmaxal", // ARM64_INS_LDSMAXAL, - "ldsmaxalb", // ARM64_INS_LDSMAXALB, - "ldsmaxalh", // ARM64_INS_LDSMAXALH, - "ldsmaxb", // ARM64_INS_LDSMAXB, - "ldsmaxh", // ARM64_INS_LDSMAXH, - "ldsmaxl", // ARM64_INS_LDSMAXL, - "ldsmaxlb", // ARM64_INS_LDSMAXLB, - "ldsmaxlh", // ARM64_INS_LDSMAXLH, - "ldsmin", // ARM64_INS_LDSMIN, - "ldsmina", // ARM64_INS_LDSMINA, - "ldsminab", // ARM64_INS_LDSMINAB, - "ldsminah", // ARM64_INS_LDSMINAH, - "ldsminal", // ARM64_INS_LDSMINAL, - "ldsminalb", // ARM64_INS_LDSMINALB, - "ldsminalh", // ARM64_INS_LDSMINALH, - "ldsminb", // ARM64_INS_LDSMINB, - "ldsminh", // ARM64_INS_LDSMINH, - "ldsminl", // ARM64_INS_LDSMINL, - "ldsminlb", // ARM64_INS_LDSMINLB, - "ldsminlh", // ARM64_INS_LDSMINLH, - "ldtr", // ARM64_INS_LDTR, - "ldtrb", // ARM64_INS_LDTRB, - "ldtrh", // ARM64_INS_LDTRH, - "ldtrsb", // ARM64_INS_LDTRSB, - "ldtrsh", // ARM64_INS_LDTRSH, - "ldtrsw", // ARM64_INS_LDTRSW, - "ldumax", // ARM64_INS_LDUMAX, - "ldumaxa", // ARM64_INS_LDUMAXA, - "ldumaxab", // ARM64_INS_LDUMAXAB, - "ldumaxah", // ARM64_INS_LDUMAXAH, - "ldumaxal", // ARM64_INS_LDUMAXAL, - "ldumaxalb", // ARM64_INS_LDUMAXALB, - "ldumaxalh", // ARM64_INS_LDUMAXALH, - "ldumaxb", // ARM64_INS_LDUMAXB, - "ldumaxh", // ARM64_INS_LDUMAXH, - "ldumaxl", // ARM64_INS_LDUMAXL, - "ldumaxlb", // ARM64_INS_LDUMAXLB, - "ldumaxlh", // ARM64_INS_LDUMAXLH, - "ldumin", // ARM64_INS_LDUMIN, - "ldumina", // ARM64_INS_LDUMINA, - "lduminab", // ARM64_INS_LDUMINAB, - "lduminah", // ARM64_INS_LDUMINAH, - "lduminal", // ARM64_INS_LDUMINAL, - "lduminalb", // ARM64_INS_LDUMINALB, - "lduminalh", // ARM64_INS_LDUMINALH, - "lduminb", // ARM64_INS_LDUMINB, - "lduminh", // ARM64_INS_LDUMINH, - "lduminl", // ARM64_INS_LDUMINL, - "lduminlb", // ARM64_INS_LDUMINLB, - "lduminlh", // ARM64_INS_LDUMINLH, - "ldur", // ARM64_INS_LDUR, - "ldurb", // ARM64_INS_LDURB, - "ldurh", // ARM64_INS_LDURH, - "ldursb", // ARM64_INS_LDURSB, - "ldursh", // ARM64_INS_LDURSH, - "ldursw", // ARM64_INS_LDURSW, - "ldxp", // ARM64_INS_LDXP, - "ldxr", // ARM64_INS_LDXR, - "ldxrb", // ARM64_INS_LDXRB, - "ldxrh", // ARM64_INS_LDXRH, - "lsl", // ARM64_INS_LSL, - "lslr", // ARM64_INS_LSLR, - "lslv", // ARM64_INS_LSLV, - "lsr", // ARM64_INS_LSR, - "lsrr", // ARM64_INS_LSRR, - "lsrv", // ARM64_INS_LSRV, - "mad", // ARM64_INS_MAD, - "madd", // ARM64_INS_MADD, - "mla", // ARM64_INS_MLA, - "mls", // ARM64_INS_MLS, - "mneg", // ARM64_INS_MNEG, - "mov", // ARM64_INS_MOV, - "movi", // ARM64_INS_MOVI, - "movk", // ARM64_INS_MOVK, - "movn", // ARM64_INS_MOVN, - "movprfx", // ARM64_INS_MOVPRFX, - "movs", // ARM64_INS_MOVS, - "movz", // ARM64_INS_MOVZ, - "mrs", // ARM64_INS_MRS, - "msb", // ARM64_INS_MSB, - "msr", // ARM64_INS_MSR, - "msub", // ARM64_INS_MSUB, - "mul", // ARM64_INS_MUL, - "mvn", // ARM64_INS_MVN, - "mvni", // ARM64_INS_MVNI, - "nand", // ARM64_INS_NAND, - "nands", // ARM64_INS_NANDS, - "neg", // ARM64_INS_NEG, - "negs", // ARM64_INS_NEGS, - "ngc", // ARM64_INS_NGC, - "ngcs", // ARM64_INS_NGCS, - "nop", // ARM64_INS_NOP, - "nor", // ARM64_INS_NOR, - "nors", // ARM64_INS_NORS, - "not", // ARM64_INS_NOT, - "nots", // ARM64_INS_NOTS, - "orn", // ARM64_INS_ORN, - "orns", // ARM64_INS_ORNS, - "orr", // ARM64_INS_ORR, - "orrs", // ARM64_INS_ORRS, - "orv", // ARM64_INS_ORV, - "pacda", // ARM64_INS_PACDA, - "pacdb", // ARM64_INS_PACDB, - "pacdza", // ARM64_INS_PACDZA, - "pacdzb", // ARM64_INS_PACDZB, - "pacga", // ARM64_INS_PACGA, - "pacia", // ARM64_INS_PACIA, - "pacia1716", // ARM64_INS_PACIA1716, - "paciasp", // ARM64_INS_PACIASP, - "paciaz", // ARM64_INS_PACIAZ, - "pacib", // ARM64_INS_PACIB, - "pacib1716", // ARM64_INS_PACIB1716, - "pacibsp", // ARM64_INS_PACIBSP, - "pacibz", // ARM64_INS_PACIBZ, - "paciza", // ARM64_INS_PACIZA, - "pacizb", // ARM64_INS_PACIZB, - "pfalse", // ARM64_INS_PFALSE, - "pfirst", // ARM64_INS_PFIRST, - "pmul", // ARM64_INS_PMUL, - "pmull", // ARM64_INS_PMULL, - "pmull2", // ARM64_INS_PMULL2, - "pnext", // ARM64_INS_PNEXT, - "prfb", // ARM64_INS_PRFB, - "prfd", // ARM64_INS_PRFD, - "prfh", // ARM64_INS_PRFH, - "prfm", // ARM64_INS_PRFM, - "prfum", // ARM64_INS_PRFUM, - "prfw", // ARM64_INS_PRFW, - "psb", // ARM64_INS_PSB, - "ptest", // ARM64_INS_PTEST, - "ptrue", // ARM64_INS_PTRUE, - "ptrues", // ARM64_INS_PTRUES, - "punpkhi", // ARM64_INS_PUNPKHI, - "punpklo", // ARM64_INS_PUNPKLO, - "raddhn", // ARM64_INS_RADDHN, - "raddhn2", // ARM64_INS_RADDHN2, - "rax1", // ARM64_INS_RAX1, - "rbit", // ARM64_INS_RBIT, - "rdffr", // ARM64_INS_RDFFR, - "rdffrs", // ARM64_INS_RDFFRS, - "rdvl", // ARM64_INS_RDVL, - "ret", // ARM64_INS_RET, - "retaa", // ARM64_INS_RETAA, - "retab", // ARM64_INS_RETAB, - "rev", // ARM64_INS_REV, - "rev16", // ARM64_INS_REV16, - "rev32", // ARM64_INS_REV32, - "rev64", // ARM64_INS_REV64, - "revb", // ARM64_INS_REVB, - "revh", // ARM64_INS_REVH, - "revw", // ARM64_INS_REVW, - "rmif", // ARM64_INS_RMIF, - "ror", // ARM64_INS_ROR, - "rorv", // ARM64_INS_RORV, - "rshrn", // ARM64_INS_RSHRN, - "rshrn2", // ARM64_INS_RSHRN2, - "rsubhn", // ARM64_INS_RSUBHN, - "rsubhn2", // ARM64_INS_RSUBHN2, - "saba", // ARM64_INS_SABA, - "sabal", // ARM64_INS_SABAL, - "sabal2", // ARM64_INS_SABAL2, - "sabd", // ARM64_INS_SABD, - "sabdl", // ARM64_INS_SABDL, - "sabdl2", // ARM64_INS_SABDL2, - "sadalp", // ARM64_INS_SADALP, - "saddl", // ARM64_INS_SADDL, - "saddl2", // ARM64_INS_SADDL2, - "saddlp", // ARM64_INS_SADDLP, - "saddlv", // ARM64_INS_SADDLV, - "saddv", // ARM64_INS_SADDV, - "saddw", // ARM64_INS_SADDW, - "saddw2", // ARM64_INS_SADDW2, - "sbc", // ARM64_INS_SBC, - "sbcs", // ARM64_INS_SBCS, - "sbfm", // ARM64_INS_SBFM, - "scvtf", // ARM64_INS_SCVTF, - "sdiv", // ARM64_INS_SDIV, - "sdivr", // ARM64_INS_SDIVR, - "sdot", // ARM64_INS_SDOT, - "sel", // ARM64_INS_SEL, - "setf16", // ARM64_INS_SETF16, - "setf8", // ARM64_INS_SETF8, - "setffr", // ARM64_INS_SETFFR, - "sev", // ARM64_INS_SEV, - "sevl", // ARM64_INS_SEVL, - "sha1c", // ARM64_INS_SHA1C, - "sha1h", // ARM64_INS_SHA1H, - "sha1m", // ARM64_INS_SHA1M, - "sha1p", // ARM64_INS_SHA1P, - "sha1su0", // ARM64_INS_SHA1SU0, - "sha1su1", // ARM64_INS_SHA1SU1, - "sha256h", // ARM64_INS_SHA256H, - "sha256h2", // ARM64_INS_SHA256H2, - "sha256su0", // ARM64_INS_SHA256SU0, - "sha256su1", // ARM64_INS_SHA256SU1, - "sha512h", // ARM64_INS_SHA512H, - "sha512h2", // ARM64_INS_SHA512H2, - "sha512su0", // ARM64_INS_SHA512SU0, - "sha512su1", // ARM64_INS_SHA512SU1, - "shadd", // ARM64_INS_SHADD, - "shl", // ARM64_INS_SHL, - "shll", // ARM64_INS_SHLL, - "shll2", // ARM64_INS_SHLL2, - "shrn", // ARM64_INS_SHRN, - "shrn2", // ARM64_INS_SHRN2, - "shsub", // ARM64_INS_SHSUB, - "sli", // ARM64_INS_SLI, - "sm3partw1", // ARM64_INS_SM3PARTW1, - "sm3partw2", // ARM64_INS_SM3PARTW2, - "sm3ss1", // ARM64_INS_SM3SS1, - "sm3tt1a", // ARM64_INS_SM3TT1A, - "sm3tt1b", // ARM64_INS_SM3TT1B, - "sm3tt2a", // ARM64_INS_SM3TT2A, - "sm3tt2b", // ARM64_INS_SM3TT2B, - "sm4e", // ARM64_INS_SM4E, - "sm4ekey", // ARM64_INS_SM4EKEY, - "smaddl", // ARM64_INS_SMADDL, - "smax", // ARM64_INS_SMAX, - "smaxp", // ARM64_INS_SMAXP, - "smaxv", // ARM64_INS_SMAXV, - "smc", // ARM64_INS_SMC, - "smin", // ARM64_INS_SMIN, - "sminp", // ARM64_INS_SMINP, - "sminv", // ARM64_INS_SMINV, - "smlal", // ARM64_INS_SMLAL, - "smlal2", // ARM64_INS_SMLAL2, - "smlsl", // ARM64_INS_SMLSL, - "smlsl2", // ARM64_INS_SMLSL2, - "smnegl", // ARM64_INS_SMNEGL, - "smov", // ARM64_INS_SMOV, - "smsubl", // ARM64_INS_SMSUBL, - "smulh", // ARM64_INS_SMULH, - "smull", // ARM64_INS_SMULL, - "smull2", // ARM64_INS_SMULL2, - "splice", // ARM64_INS_SPLICE, - "sqabs", // ARM64_INS_SQABS, - "sqadd", // ARM64_INS_SQADD, - "sqdecb", // ARM64_INS_SQDECB, - "sqdecd", // ARM64_INS_SQDECD, - "sqdech", // ARM64_INS_SQDECH, - "sqdecp", // ARM64_INS_SQDECP, - "sqdecw", // ARM64_INS_SQDECW, - "sqdmlal", // ARM64_INS_SQDMLAL, - "sqdmlal2", // ARM64_INS_SQDMLAL2, - "sqdmlsl", // ARM64_INS_SQDMLSL, - "sqdmlsl2", // ARM64_INS_SQDMLSL2, - "sqdmulh", // ARM64_INS_SQDMULH, - "sqdmull", // ARM64_INS_SQDMULL, - "sqdmull2", // ARM64_INS_SQDMULL2, - "sqincb", // ARM64_INS_SQINCB, - "sqincd", // ARM64_INS_SQINCD, - "sqinch", // ARM64_INS_SQINCH, - "sqincp", // ARM64_INS_SQINCP, - "sqincw", // ARM64_INS_SQINCW, - "sqneg", // ARM64_INS_SQNEG, - "sqrdmlah", // ARM64_INS_SQRDMLAH, - "sqrdmlsh", // ARM64_INS_SQRDMLSH, - "sqrdmulh", // ARM64_INS_SQRDMULH, - "sqrshl", // ARM64_INS_SQRSHL, - "sqrshrn", // ARM64_INS_SQRSHRN, - "sqrshrn2", // ARM64_INS_SQRSHRN2, - "sqrshrun", // ARM64_INS_SQRSHRUN, - "sqrshrun2", // ARM64_INS_SQRSHRUN2, - "sqshl", // ARM64_INS_SQSHL, - "sqshlu", // ARM64_INS_SQSHLU, - "sqshrn", // ARM64_INS_SQSHRN, - "sqshrn2", // ARM64_INS_SQSHRN2, - "sqshrun", // ARM64_INS_SQSHRUN, - "sqshrun2", // ARM64_INS_SQSHRUN2, - "sqsub", // ARM64_INS_SQSUB, - "sqxtn", // ARM64_INS_SQXTN, - "sqxtn2", // ARM64_INS_SQXTN2, - "sqxtun", // ARM64_INS_SQXTUN, - "sqxtun2", // ARM64_INS_SQXTUN2, - "srhadd", // ARM64_INS_SRHADD, - "sri", // ARM64_INS_SRI, - "srshl", // ARM64_INS_SRSHL, - "srshr", // ARM64_INS_SRSHR, - "srsra", // ARM64_INS_SRSRA, - "sshl", // ARM64_INS_SSHL, - "sshll", // ARM64_INS_SSHLL, - "sshll2", // ARM64_INS_SSHLL2, - "sshr", // ARM64_INS_SSHR, - "ssra", // ARM64_INS_SSRA, - "ssubl", // ARM64_INS_SSUBL, - "ssubl2", // ARM64_INS_SSUBL2, - "ssubw", // ARM64_INS_SSUBW, - "ssubw2", // ARM64_INS_SSUBW2, - "st1", // ARM64_INS_ST1, - "st1b", // ARM64_INS_ST1B, - "st1d", // ARM64_INS_ST1D, - "st1h", // ARM64_INS_ST1H, - "st1w", // ARM64_INS_ST1W, - "st2", // ARM64_INS_ST2, - "st2b", // ARM64_INS_ST2B, - "st2d", // ARM64_INS_ST2D, - "st2h", // ARM64_INS_ST2H, - "st2w", // ARM64_INS_ST2W, - "st3", // ARM64_INS_ST3, - "st3b", // ARM64_INS_ST3B, - "st3d", // ARM64_INS_ST3D, - "st3h", // ARM64_INS_ST3H, - "st3w", // ARM64_INS_ST3W, - "st4", // ARM64_INS_ST4, - "st4b", // ARM64_INS_ST4B, - "st4d", // ARM64_INS_ST4D, - "st4h", // ARM64_INS_ST4H, - "st4w", // ARM64_INS_ST4W, - "stadd", // ARM64_INS_STADD, - "staddb", // ARM64_INS_STADDB, - "staddh", // ARM64_INS_STADDH, - "staddl", // ARM64_INS_STADDL, - "staddlb", // ARM64_INS_STADDLB, - "staddlh", // ARM64_INS_STADDLH, - "stclr", // ARM64_INS_STCLR, - "stclrb", // ARM64_INS_STCLRB, - "stclrh", // ARM64_INS_STCLRH, - "stclrl", // ARM64_INS_STCLRL, - "stclrlb", // ARM64_INS_STCLRLB, - "stclrlh", // ARM64_INS_STCLRLH, - "steor", // ARM64_INS_STEOR, - "steorb", // ARM64_INS_STEORB, - "steorh", // ARM64_INS_STEORH, - "steorl", // ARM64_INS_STEORL, - "steorlb", // ARM64_INS_STEORLB, - "steorlh", // ARM64_INS_STEORLH, - "stllr", // ARM64_INS_STLLR, - "stllrb", // ARM64_INS_STLLRB, - "stllrh", // ARM64_INS_STLLRH, - "stlr", // ARM64_INS_STLR, - "stlrb", // ARM64_INS_STLRB, - "stlrh", // ARM64_INS_STLRH, - "stlur", // ARM64_INS_STLUR, - "stlurb", // ARM64_INS_STLURB, - "stlurh", // ARM64_INS_STLURH, - "stlxp", // ARM64_INS_STLXP, - "stlxr", // ARM64_INS_STLXR, - "stlxrb", // ARM64_INS_STLXRB, - "stlxrh", // ARM64_INS_STLXRH, - "stnp", // ARM64_INS_STNP, - "stnt1b", // ARM64_INS_STNT1B, - "stnt1d", // ARM64_INS_STNT1D, - "stnt1h", // ARM64_INS_STNT1H, - "stnt1w", // ARM64_INS_STNT1W, - "stp", // ARM64_INS_STP, - "str", // ARM64_INS_STR, - "strb", // ARM64_INS_STRB, - "strh", // ARM64_INS_STRH, - "stset", // ARM64_INS_STSET, - "stsetb", // ARM64_INS_STSETB, - "stseth", // ARM64_INS_STSETH, - "stsetl", // ARM64_INS_STSETL, - "stsetlb", // ARM64_INS_STSETLB, - "stsetlh", // ARM64_INS_STSETLH, - "stsmax", // ARM64_INS_STSMAX, - "stsmaxb", // ARM64_INS_STSMAXB, - "stsmaxh", // ARM64_INS_STSMAXH, - "stsmaxl", // ARM64_INS_STSMAXL, - "stsmaxlb", // ARM64_INS_STSMAXLB, - "stsmaxlh", // ARM64_INS_STSMAXLH, - "stsmin", // ARM64_INS_STSMIN, - "stsminb", // ARM64_INS_STSMINB, - "stsminh", // ARM64_INS_STSMINH, - "stsminl", // ARM64_INS_STSMINL, - "stsminlb", // ARM64_INS_STSMINLB, - "stsminlh", // ARM64_INS_STSMINLH, - "sttr", // ARM64_INS_STTR, - "sttrb", // ARM64_INS_STTRB, - "sttrh", // ARM64_INS_STTRH, - "stumax", // ARM64_INS_STUMAX, - "stumaxb", // ARM64_INS_STUMAXB, - "stumaxh", // ARM64_INS_STUMAXH, - "stumaxl", // ARM64_INS_STUMAXL, - "stumaxlb", // ARM64_INS_STUMAXLB, - "stumaxlh", // ARM64_INS_STUMAXLH, - "stumin", // ARM64_INS_STUMIN, - "stuminb", // ARM64_INS_STUMINB, - "stuminh", // ARM64_INS_STUMINH, - "stuminl", // ARM64_INS_STUMINL, - "stuminlb", // ARM64_INS_STUMINLB, - "stuminlh", // ARM64_INS_STUMINLH, - "stur", // ARM64_INS_STUR, - "sturb", // ARM64_INS_STURB, - "sturh", // ARM64_INS_STURH, - "stxp", // ARM64_INS_STXP, - "stxr", // ARM64_INS_STXR, - "stxrb", // ARM64_INS_STXRB, - "stxrh", // ARM64_INS_STXRH, - "sub", // ARM64_INS_SUB, - "subhn", // ARM64_INS_SUBHN, - "subhn2", // ARM64_INS_SUBHN2, - "subr", // ARM64_INS_SUBR, - "subs", // ARM64_INS_SUBS, - "sunpkhi", // ARM64_INS_SUNPKHI, - "sunpklo", // ARM64_INS_SUNPKLO, - "suqadd", // ARM64_INS_SUQADD, - "svc", // ARM64_INS_SVC, - "swp", // ARM64_INS_SWP, - "swpa", // ARM64_INS_SWPA, - "swpab", // ARM64_INS_SWPAB, - "swpah", // ARM64_INS_SWPAH, - "swpal", // ARM64_INS_SWPAL, - "swpalb", // ARM64_INS_SWPALB, - "swpalh", // ARM64_INS_SWPALH, - "swpb", // ARM64_INS_SWPB, - "swph", // ARM64_INS_SWPH, - "swpl", // ARM64_INS_SWPL, - "swplb", // ARM64_INS_SWPLB, - "swplh", // ARM64_INS_SWPLH, - "sxtb", // ARM64_INS_SXTB, - "sxth", // ARM64_INS_SXTH, - "sxtl", // ARM64_INS_SXTL, - "sxtl2", // ARM64_INS_SXTL2, - "sxtw", // ARM64_INS_SXTW, - "sys", // ARM64_INS_SYS, - "sysl", // ARM64_INS_SYSL, - "tbl", // ARM64_INS_TBL, - "tbnz", // ARM64_INS_TBNZ, - "tbx", // ARM64_INS_TBX, - "tbz", // ARM64_INS_TBZ, - "trn1", // ARM64_INS_TRN1, - "trn2", // ARM64_INS_TRN2, - "tsb", // ARM64_INS_TSB, - "tst", // ARM64_INS_TST, - "uaba", // ARM64_INS_UABA, - "uabal", // ARM64_INS_UABAL, - "uabal2", // ARM64_INS_UABAL2, - "uabd", // ARM64_INS_UABD, - "uabdl", // ARM64_INS_UABDL, - "uabdl2", // ARM64_INS_UABDL2, - "uadalp", // ARM64_INS_UADALP, - "uaddl", // ARM64_INS_UADDL, - "uaddl2", // ARM64_INS_UADDL2, - "uaddlp", // ARM64_INS_UADDLP, - "uaddlv", // ARM64_INS_UADDLV, - "uaddv", // ARM64_INS_UADDV, - "uaddw", // ARM64_INS_UADDW, - "uaddw2", // ARM64_INS_UADDW2, - "ubfm", // ARM64_INS_UBFM, - "ucvtf", // ARM64_INS_UCVTF, - "udiv", // ARM64_INS_UDIV, - "udivr", // ARM64_INS_UDIVR, - "udot", // ARM64_INS_UDOT, - "uhadd", // ARM64_INS_UHADD, - "uhsub", // ARM64_INS_UHSUB, - "umaddl", // ARM64_INS_UMADDL, - "umax", // ARM64_INS_UMAX, - "umaxp", // ARM64_INS_UMAXP, - "umaxv", // ARM64_INS_UMAXV, - "umin", // ARM64_INS_UMIN, - "uminp", // ARM64_INS_UMINP, - "uminv", // ARM64_INS_UMINV, - "umlal", // ARM64_INS_UMLAL, - "umlal2", // ARM64_INS_UMLAL2, - "umlsl", // ARM64_INS_UMLSL, - "umlsl2", // ARM64_INS_UMLSL2, - "umnegl", // ARM64_INS_UMNEGL, - "umov", // ARM64_INS_UMOV, - "umsubl", // ARM64_INS_UMSUBL, - "umulh", // ARM64_INS_UMULH, - "umull", // ARM64_INS_UMULL, - "umull2", // ARM64_INS_UMULL2, - "uqadd", // ARM64_INS_UQADD, - "uqdecb", // ARM64_INS_UQDECB, - "uqdecd", // ARM64_INS_UQDECD, - "uqdech", // ARM64_INS_UQDECH, - "uqdecp", // ARM64_INS_UQDECP, - "uqdecw", // ARM64_INS_UQDECW, - "uqincb", // ARM64_INS_UQINCB, - "uqincd", // ARM64_INS_UQINCD, - "uqinch", // ARM64_INS_UQINCH, - "uqincp", // ARM64_INS_UQINCP, - "uqincw", // ARM64_INS_UQINCW, - "uqrshl", // ARM64_INS_UQRSHL, - "uqrshrn", // ARM64_INS_UQRSHRN, - "uqrshrn2", // ARM64_INS_UQRSHRN2, - "uqshl", // ARM64_INS_UQSHL, - "uqshrn", // ARM64_INS_UQSHRN, - "uqshrn2", // ARM64_INS_UQSHRN2, - "uqsub", // ARM64_INS_UQSUB, - "uqxtn", // ARM64_INS_UQXTN, - "uqxtn2", // ARM64_INS_UQXTN2, - "urecpe", // ARM64_INS_URECPE, - "urhadd", // ARM64_INS_URHADD, - "urshl", // ARM64_INS_URSHL, - "urshr", // ARM64_INS_URSHR, - "ursqrte", // ARM64_INS_URSQRTE, - "ursra", // ARM64_INS_URSRA, - "ushl", // ARM64_INS_USHL, - "ushll", // ARM64_INS_USHLL, - "ushll2", // ARM64_INS_USHLL2, - "ushr", // ARM64_INS_USHR, - "usqadd", // ARM64_INS_USQADD, - "usra", // ARM64_INS_USRA, - "usubl", // ARM64_INS_USUBL, - "usubl2", // ARM64_INS_USUBL2, - "usubw", // ARM64_INS_USUBW, - "usubw2", // ARM64_INS_USUBW2, - "uunpkhi", // ARM64_INS_UUNPKHI, - "uunpklo", // ARM64_INS_UUNPKLO, - "uxtb", // ARM64_INS_UXTB, - "uxth", // ARM64_INS_UXTH, - "uxtl", // ARM64_INS_UXTL, - "uxtl2", // ARM64_INS_UXTL2, - "uxtw", // ARM64_INS_UXTW, - "uzp1", // ARM64_INS_UZP1, - "uzp2", // ARM64_INS_UZP2, - "wfe", // ARM64_INS_WFE, - "wfi", // ARM64_INS_WFI, - "whilele", // ARM64_INS_WHILELE, - "whilelo", // ARM64_INS_WHILELO, - "whilels", // ARM64_INS_WHILELS, - "whilelt", // ARM64_INS_WHILELT, - "wrffr", // ARM64_INS_WRFFR, - "xar", // ARM64_INS_XAR, - "xpacd", // ARM64_INS_XPACD, - "xpaci", // ARM64_INS_XPACI, - "xpaclri", // ARM64_INS_XPACLRI, - "xtn", // ARM64_INS_XTN, - "xtn2", // ARM64_INS_XTN2, - "yield", // ARM64_INS_YIELD, - "zip1", // ARM64_INS_ZIP1, - "zip2", // ARM64_INS_ZIP2, +"abs", // ARM64_INS_ABS, + "adc", // ARM64_INS_ADC, + "adcs", // ARM64_INS_ADCS, + "add", // ARM64_INS_ADD, + "addhn", // ARM64_INS_ADDHN, + "addhn2", // ARM64_INS_ADDHN2, + "addp", // ARM64_INS_ADDP, + "addpl", // ARM64_INS_ADDPL, + "adds", // ARM64_INS_ADDS, + "addv", // ARM64_INS_ADDV, + "addvl", // ARM64_INS_ADDVL, + "adr", // ARM64_INS_ADR, + "adrp", // ARM64_INS_ADRP, + "aesd", // ARM64_INS_AESD, + "aese", // ARM64_INS_AESE, + "aesimc", // ARM64_INS_AESIMC, + "aesmc", // ARM64_INS_AESMC, + "and", // ARM64_INS_AND, + "ands", // ARM64_INS_ANDS, + "andv", // ARM64_INS_ANDV, + "asr", // ARM64_INS_ASR, + "asrd", // ARM64_INS_ASRD, + "asrr", // ARM64_INS_ASRR, + "asrv", // ARM64_INS_ASRV, + "autda", // ARM64_INS_AUTDA, + "autdb", // ARM64_INS_AUTDB, + "autdza", // ARM64_INS_AUTDZA, + "autdzb", // ARM64_INS_AUTDZB, + "autia", // ARM64_INS_AUTIA, + "autia1716", // ARM64_INS_AUTIA1716, + "autiasp", // ARM64_INS_AUTIASP, + "autiaz", // ARM64_INS_AUTIAZ, + "autib", // ARM64_INS_AUTIB, + "autib1716", // ARM64_INS_AUTIB1716, + "autibsp", // ARM64_INS_AUTIBSP, + "autibz", // ARM64_INS_AUTIBZ, + "autiza", // ARM64_INS_AUTIZA, + "autizb", // ARM64_INS_AUTIZB, + "b", // ARM64_INS_B, + "bcax", // ARM64_INS_BCAX, + "bfm", // ARM64_INS_BFM, + "bic", // ARM64_INS_BIC, + "bics", // ARM64_INS_BICS, + "bif", // ARM64_INS_BIF, + "bit", // ARM64_INS_BIT, + "bl", // ARM64_INS_BL, + "blr", // ARM64_INS_BLR, + "blraa", // ARM64_INS_BLRAA, + "blraaz", // ARM64_INS_BLRAAZ, + "blrab", // ARM64_INS_BLRAB, + "blrabz", // ARM64_INS_BLRABZ, + "br", // ARM64_INS_BR, + "braa", // ARM64_INS_BRAA, + "braaz", // ARM64_INS_BRAAZ, + "brab", // ARM64_INS_BRAB, + "brabz", // ARM64_INS_BRABZ, + "brk", // ARM64_INS_BRK, + "brka", // ARM64_INS_BRKA, + "brkas", // ARM64_INS_BRKAS, + "brkb", // ARM64_INS_BRKB, + "brkbs", // ARM64_INS_BRKBS, + "brkn", // ARM64_INS_BRKN, + "brkns", // ARM64_INS_BRKNS, + "brkpa", // ARM64_INS_BRKPA, + "brkpas", // ARM64_INS_BRKPAS, + "brkpb", // ARM64_INS_BRKPB, + "brkpbs", // ARM64_INS_BRKPBS, + "bsl", // ARM64_INS_BSL, + "cas", // ARM64_INS_CAS, + "casa", // ARM64_INS_CASA, + "casab", // ARM64_INS_CASAB, + "casah", // ARM64_INS_CASAH, + "casal", // ARM64_INS_CASAL, + "casalb", // ARM64_INS_CASALB, + "casalh", // ARM64_INS_CASALH, + "casb", // ARM64_INS_CASB, + "cash", // ARM64_INS_CASH, + "casl", // ARM64_INS_CASL, + "caslb", // ARM64_INS_CASLB, + "caslh", // ARM64_INS_CASLH, + "casp", // ARM64_INS_CASP, + "caspa", // ARM64_INS_CASPA, + "caspal", // ARM64_INS_CASPAL, + "caspl", // ARM64_INS_CASPL, + "cbnz", // ARM64_INS_CBNZ, + "cbz", // ARM64_INS_CBZ, + "ccmn", // ARM64_INS_CCMN, + "ccmp", // ARM64_INS_CCMP, + "cfinv", // ARM64_INS_CFINV, + "cinc", // ARM64_INS_CINC, + "cinv", // ARM64_INS_CINV, + "clasta", // ARM64_INS_CLASTA, + "clastb", // ARM64_INS_CLASTB, + "clrex", // ARM64_INS_CLREX, + "cls", // ARM64_INS_CLS, + "clz", // ARM64_INS_CLZ, + "cmeq", // ARM64_INS_CMEQ, + "cmge", // ARM64_INS_CMGE, + "cmgt", // ARM64_INS_CMGT, + "cmhi", // ARM64_INS_CMHI, + "cmhs", // ARM64_INS_CMHS, + "cmle", // ARM64_INS_CMLE, + "cmlo", // ARM64_INS_CMLO, + "cmls", // ARM64_INS_CMLS, + "cmlt", // ARM64_INS_CMLT, + "cmn", // ARM64_INS_CMN, + "cmp", // ARM64_INS_CMP, + "cmpeq", // ARM64_INS_CMPEQ, + "cmpge", // ARM64_INS_CMPGE, + "cmpgt", // ARM64_INS_CMPGT, + "cmphi", // ARM64_INS_CMPHI, + "cmphs", // ARM64_INS_CMPHS, + "cmple", // ARM64_INS_CMPLE, + "cmplo", // ARM64_INS_CMPLO, + "cmpls", // ARM64_INS_CMPLS, + "cmplt", // ARM64_INS_CMPLT, + "cmpne", // ARM64_INS_CMPNE, + "cmtst", // ARM64_INS_CMTST, + "cneg", // ARM64_INS_CNEG, + "cnot", // ARM64_INS_CNOT, + "cnt", // ARM64_INS_CNT, + "cntb", // ARM64_INS_CNTB, + "cntd", // ARM64_INS_CNTD, + "cnth", // ARM64_INS_CNTH, + "cntp", // ARM64_INS_CNTP, + "cntw", // ARM64_INS_CNTW, + "compact", // ARM64_INS_COMPACT, + "cpy", // ARM64_INS_CPY, + "crc32b", // ARM64_INS_CRC32B, + "crc32cb", // ARM64_INS_CRC32CB, + "crc32ch", // ARM64_INS_CRC32CH, + "crc32cw", // ARM64_INS_CRC32CW, + "crc32cx", // ARM64_INS_CRC32CX, + "crc32h", // ARM64_INS_CRC32H, + "crc32w", // ARM64_INS_CRC32W, + "crc32x", // ARM64_INS_CRC32X, + "csdb", // ARM64_INS_CSDB, + "csel", // ARM64_INS_CSEL, + "cset", // ARM64_INS_CSET, + "csetm", // ARM64_INS_CSETM, + "csinc", // ARM64_INS_CSINC, + "csinv", // ARM64_INS_CSINV, + "csneg", // ARM64_INS_CSNEG, + "ctermeq", // ARM64_INS_CTERMEQ, + "ctermne", // ARM64_INS_CTERMNE, + "dcps1", // ARM64_INS_DCPS1, + "dcps2", // ARM64_INS_DCPS2, + "dcps3", // ARM64_INS_DCPS3, + "decb", // ARM64_INS_DECB, + "decd", // ARM64_INS_DECD, + "dech", // ARM64_INS_DECH, + "decp", // ARM64_INS_DECP, + "decw", // ARM64_INS_DECW, + "dmb", // ARM64_INS_DMB, + "drps", // ARM64_INS_DRPS, + "dsb", // ARM64_INS_DSB, + "dup", // ARM64_INS_DUP, + "dupm", // ARM64_INS_DUPM, + "eon", // ARM64_INS_EON, + "eor", // ARM64_INS_EOR, + "eor3", // ARM64_INS_EOR3, + "eors", // ARM64_INS_EORS, + "eorv", // ARM64_INS_EORV, + "eret", // ARM64_INS_ERET, + "eretaa", // ARM64_INS_ERETAA, + "eretab", // ARM64_INS_ERETAB, + "esb", // ARM64_INS_ESB, + "ext", // ARM64_INS_EXT, + "extr", // ARM64_INS_EXTR, + "fabd", // ARM64_INS_FABD, + "fabs", // ARM64_INS_FABS, + "facge", // ARM64_INS_FACGE, + "facgt", // ARM64_INS_FACGT, + "facle", // ARM64_INS_FACLE, + "faclt", // ARM64_INS_FACLT, + "fadd", // ARM64_INS_FADD, + "fadda", // ARM64_INS_FADDA, + "faddp", // ARM64_INS_FADDP, + "faddv", // ARM64_INS_FADDV, + "fcadd", // ARM64_INS_FCADD, + "fccmp", // ARM64_INS_FCCMP, + "fccmpe", // ARM64_INS_FCCMPE, + "fcmeq", // ARM64_INS_FCMEQ, + "fcmge", // ARM64_INS_FCMGE, + "fcmgt", // ARM64_INS_FCMGT, + "fcmla", // ARM64_INS_FCMLA, + "fcmle", // ARM64_INS_FCMLE, + "fcmlt", // ARM64_INS_FCMLT, + "fcmne", // ARM64_INS_FCMNE, + "fcmp", // ARM64_INS_FCMP, + "fcmpe", // ARM64_INS_FCMPE, + "fcmuo", // ARM64_INS_FCMUO, + "fcpy", // ARM64_INS_FCPY, + "fcsel", // ARM64_INS_FCSEL, + "fcvt", // ARM64_INS_FCVT, + "fcvtas", // ARM64_INS_FCVTAS, + "fcvtau", // ARM64_INS_FCVTAU, + "fcvtl", // ARM64_INS_FCVTL, + "fcvtl2", // ARM64_INS_FCVTL2, + "fcvtms", // ARM64_INS_FCVTMS, + "fcvtmu", // ARM64_INS_FCVTMU, + "fcvtn", // ARM64_INS_FCVTN, + "fcvtn2", // ARM64_INS_FCVTN2, + "fcvtns", // ARM64_INS_FCVTNS, + "fcvtnu", // ARM64_INS_FCVTNU, + "fcvtps", // ARM64_INS_FCVTPS, + "fcvtpu", // ARM64_INS_FCVTPU, + "fcvtxn", // ARM64_INS_FCVTXN, + "fcvtxn2", // ARM64_INS_FCVTXN2, + "fcvtzs", // ARM64_INS_FCVTZS, + "fcvtzu", // ARM64_INS_FCVTZU, + "fdiv", // ARM64_INS_FDIV, + "fdivr", // ARM64_INS_FDIVR, + "fdup", // ARM64_INS_FDUP, + "fexpa", // ARM64_INS_FEXPA, + "fjcvtzs", // ARM64_INS_FJCVTZS, + "fmad", // ARM64_INS_FMAD, + "fmadd", // ARM64_INS_FMADD, + "fmax", // ARM64_INS_FMAX, + "fmaxnm", // ARM64_INS_FMAXNM, + "fmaxnmp", // ARM64_INS_FMAXNMP, + "fmaxnmv", // ARM64_INS_FMAXNMV, + "fmaxp", // ARM64_INS_FMAXP, + "fmaxv", // ARM64_INS_FMAXV, + "fmin", // ARM64_INS_FMIN, + "fminnm", // ARM64_INS_FMINNM, + "fminnmp", // ARM64_INS_FMINNMP, + "fminnmv", // ARM64_INS_FMINNMV, + "fminp", // ARM64_INS_FMINP, + "fminv", // ARM64_INS_FMINV, + "fmla", // ARM64_INS_FMLA, + "fmls", // ARM64_INS_FMLS, + "fmov", // ARM64_INS_FMOV, + "fmsb", // ARM64_INS_FMSB, + "fmsub", // ARM64_INS_FMSUB, + "fmul", // ARM64_INS_FMUL, + "fmulx", // ARM64_INS_FMULX, + "fneg", // ARM64_INS_FNEG, + "fnmad", // ARM64_INS_FNMAD, + "fnmadd", // ARM64_INS_FNMADD, + "fnmla", // ARM64_INS_FNMLA, + "fnmls", // ARM64_INS_FNMLS, + "fnmsb", // ARM64_INS_FNMSB, + "fnmsub", // ARM64_INS_FNMSUB, + "fnmul", // ARM64_INS_FNMUL, + "frecpe", // ARM64_INS_FRECPE, + "frecps", // ARM64_INS_FRECPS, + "frecpx", // ARM64_INS_FRECPX, + "frinta", // ARM64_INS_FRINTA, + "frinti", // ARM64_INS_FRINTI, + "frintm", // ARM64_INS_FRINTM, + "frintn", // ARM64_INS_FRINTN, + "frintp", // ARM64_INS_FRINTP, + "frintx", // ARM64_INS_FRINTX, + "frintz", // ARM64_INS_FRINTZ, + "frsqrte", // ARM64_INS_FRSQRTE, + "frsqrts", // ARM64_INS_FRSQRTS, + "fscale", // ARM64_INS_FSCALE, + "fsqrt", // ARM64_INS_FSQRT, + "fsub", // ARM64_INS_FSUB, + "fsubr", // ARM64_INS_FSUBR, + "ftmad", // ARM64_INS_FTMAD, + "ftsmul", // ARM64_INS_FTSMUL, + "ftssel", // ARM64_INS_FTSSEL, + "hint", // ARM64_INS_HINT, + "hlt", // ARM64_INS_HLT, + "hvc", // ARM64_INS_HVC, + "incb", // ARM64_INS_INCB, + "incd", // ARM64_INS_INCD, + "inch", // ARM64_INS_INCH, + "incp", // ARM64_INS_INCP, + "incw", // ARM64_INS_INCW, + "index", // ARM64_INS_INDEX, + "ins", // ARM64_INS_INS, + "insr", // ARM64_INS_INSR, + "isb", // ARM64_INS_ISB, + "lasta", // ARM64_INS_LASTA, + "lastb", // ARM64_INS_LASTB, + "ld1", // ARM64_INS_LD1, + "ld1b", // ARM64_INS_LD1B, + "ld1d", // ARM64_INS_LD1D, + "ld1h", // ARM64_INS_LD1H, + "ld1r", // ARM64_INS_LD1R, + "ld1rb", // ARM64_INS_LD1RB, + "ld1rd", // ARM64_INS_LD1RD, + "ld1rh", // ARM64_INS_LD1RH, + "ld1rqb", // ARM64_INS_LD1RQB, + "ld1rqd", // ARM64_INS_LD1RQD, + "ld1rqh", // ARM64_INS_LD1RQH, + "ld1rqw", // ARM64_INS_LD1RQW, + "ld1rsb", // ARM64_INS_LD1RSB, + "ld1rsh", // ARM64_INS_LD1RSH, + "ld1rsw", // ARM64_INS_LD1RSW, + "ld1rw", // ARM64_INS_LD1RW, + "ld1sb", // ARM64_INS_LD1SB, + "ld1sh", // ARM64_INS_LD1SH, + "ld1sw", // ARM64_INS_LD1SW, + "ld1w", // ARM64_INS_LD1W, + "ld2", // ARM64_INS_LD2, + "ld2b", // ARM64_INS_LD2B, + "ld2d", // ARM64_INS_LD2D, + "ld2h", // ARM64_INS_LD2H, + "ld2r", // ARM64_INS_LD2R, + "ld2w", // ARM64_INS_LD2W, + "ld3", // ARM64_INS_LD3, + "ld3b", // ARM64_INS_LD3B, + "ld3d", // ARM64_INS_LD3D, + "ld3h", // ARM64_INS_LD3H, + "ld3r", // ARM64_INS_LD3R, + "ld3w", // ARM64_INS_LD3W, + "ld4", // ARM64_INS_LD4, + "ld4b", // ARM64_INS_LD4B, + "ld4d", // ARM64_INS_LD4D, + "ld4h", // ARM64_INS_LD4H, + "ld4r", // ARM64_INS_LD4R, + "ld4w", // ARM64_INS_LD4W, + "ldadd", // ARM64_INS_LDADD, + "ldadda", // ARM64_INS_LDADDA, + "ldaddab", // ARM64_INS_LDADDAB, + "ldaddah", // ARM64_INS_LDADDAH, + "ldaddal", // ARM64_INS_LDADDAL, + "ldaddalb", // ARM64_INS_LDADDALB, + "ldaddalh", // ARM64_INS_LDADDALH, + "ldaddb", // ARM64_INS_LDADDB, + "ldaddh", // ARM64_INS_LDADDH, + "ldaddl", // ARM64_INS_LDADDL, + "ldaddlb", // ARM64_INS_LDADDLB, + "ldaddlh", // ARM64_INS_LDADDLH, + "ldapr", // ARM64_INS_LDAPR, + "ldaprb", // ARM64_INS_LDAPRB, + "ldaprh", // ARM64_INS_LDAPRH, + "ldapur", // ARM64_INS_LDAPUR, + "ldapurb", // ARM64_INS_LDAPURB, + "ldapurh", // ARM64_INS_LDAPURH, + "ldapursb", // ARM64_INS_LDAPURSB, + "ldapursh", // ARM64_INS_LDAPURSH, + "ldapursw", // ARM64_INS_LDAPURSW, + "ldar", // ARM64_INS_LDAR, + "ldarb", // ARM64_INS_LDARB, + "ldarh", // ARM64_INS_LDARH, + "ldaxp", // ARM64_INS_LDAXP, + "ldaxr", // ARM64_INS_LDAXR, + "ldaxrb", // ARM64_INS_LDAXRB, + "ldaxrh", // ARM64_INS_LDAXRH, + "ldclr", // ARM64_INS_LDCLR, + "ldclra", // ARM64_INS_LDCLRA, + "ldclrab", // ARM64_INS_LDCLRAB, + "ldclrah", // ARM64_INS_LDCLRAH, + "ldclral", // ARM64_INS_LDCLRAL, + "ldclralb", // ARM64_INS_LDCLRALB, + "ldclralh", // ARM64_INS_LDCLRALH, + "ldclrb", // ARM64_INS_LDCLRB, + "ldclrh", // ARM64_INS_LDCLRH, + "ldclrl", // ARM64_INS_LDCLRL, + "ldclrlb", // ARM64_INS_LDCLRLB, + "ldclrlh", // ARM64_INS_LDCLRLH, + "ldeor", // ARM64_INS_LDEOR, + "ldeora", // ARM64_INS_LDEORA, + "ldeorab", // ARM64_INS_LDEORAB, + "ldeorah", // ARM64_INS_LDEORAH, + "ldeoral", // ARM64_INS_LDEORAL, + "ldeoralb", // ARM64_INS_LDEORALB, + "ldeoralh", // ARM64_INS_LDEORALH, + "ldeorb", // ARM64_INS_LDEORB, + "ldeorh", // ARM64_INS_LDEORH, + "ldeorl", // ARM64_INS_LDEORL, + "ldeorlb", // ARM64_INS_LDEORLB, + "ldeorlh", // ARM64_INS_LDEORLH, + "ldff1b", // ARM64_INS_LDFF1B, + "ldff1d", // ARM64_INS_LDFF1D, + "ldff1h", // ARM64_INS_LDFF1H, + "ldff1sb", // ARM64_INS_LDFF1SB, + "ldff1sh", // ARM64_INS_LDFF1SH, + "ldff1sw", // ARM64_INS_LDFF1SW, + "ldff1w", // ARM64_INS_LDFF1W, + "ldlar", // ARM64_INS_LDLAR, + "ldlarb", // ARM64_INS_LDLARB, + "ldlarh", // ARM64_INS_LDLARH, + "ldnf1b", // ARM64_INS_LDNF1B, + "ldnf1d", // ARM64_INS_LDNF1D, + "ldnf1h", // ARM64_INS_LDNF1H, + "ldnf1sb", // ARM64_INS_LDNF1SB, + "ldnf1sh", // ARM64_INS_LDNF1SH, + "ldnf1sw", // ARM64_INS_LDNF1SW, + "ldnf1w", // ARM64_INS_LDNF1W, + "ldnp", // ARM64_INS_LDNP, + "ldnt1b", // ARM64_INS_LDNT1B, + "ldnt1d", // ARM64_INS_LDNT1D, + "ldnt1h", // ARM64_INS_LDNT1H, + "ldnt1w", // ARM64_INS_LDNT1W, + "ldp", // ARM64_INS_LDP, + "ldpsw", // ARM64_INS_LDPSW, + "ldr", // ARM64_INS_LDR, + "ldraa", // ARM64_INS_LDRAA, + "ldrab", // ARM64_INS_LDRAB, + "ldrb", // ARM64_INS_LDRB, + "ldrh", // ARM64_INS_LDRH, + "ldrsb", // ARM64_INS_LDRSB, + "ldrsh", // ARM64_INS_LDRSH, + "ldrsw", // ARM64_INS_LDRSW, + "ldset", // ARM64_INS_LDSET, + "ldseta", // ARM64_INS_LDSETA, + "ldsetab", // ARM64_INS_LDSETAB, + "ldsetah", // ARM64_INS_LDSETAH, + "ldsetal", // ARM64_INS_LDSETAL, + "ldsetalb", // ARM64_INS_LDSETALB, + "ldsetalh", // ARM64_INS_LDSETALH, + "ldsetb", // ARM64_INS_LDSETB, + "ldseth", // ARM64_INS_LDSETH, + "ldsetl", // ARM64_INS_LDSETL, + "ldsetlb", // ARM64_INS_LDSETLB, + "ldsetlh", // ARM64_INS_LDSETLH, + "ldsmax", // ARM64_INS_LDSMAX, + "ldsmaxa", // ARM64_INS_LDSMAXA, + "ldsmaxab", // ARM64_INS_LDSMAXAB, + "ldsmaxah", // ARM64_INS_LDSMAXAH, + "ldsmaxal", // ARM64_INS_LDSMAXAL, + "ldsmaxalb", // ARM64_INS_LDSMAXALB, + "ldsmaxalh", // ARM64_INS_LDSMAXALH, + "ldsmaxb", // ARM64_INS_LDSMAXB, + "ldsmaxh", // ARM64_INS_LDSMAXH, + "ldsmaxl", // ARM64_INS_LDSMAXL, + "ldsmaxlb", // ARM64_INS_LDSMAXLB, + "ldsmaxlh", // ARM64_INS_LDSMAXLH, + "ldsmin", // ARM64_INS_LDSMIN, + "ldsmina", // ARM64_INS_LDSMINA, + "ldsminab", // ARM64_INS_LDSMINAB, + "ldsminah", // ARM64_INS_LDSMINAH, + "ldsminal", // ARM64_INS_LDSMINAL, + "ldsminalb", // ARM64_INS_LDSMINALB, + "ldsminalh", // ARM64_INS_LDSMINALH, + "ldsminb", // ARM64_INS_LDSMINB, + "ldsminh", // ARM64_INS_LDSMINH, + "ldsminl", // ARM64_INS_LDSMINL, + "ldsminlb", // ARM64_INS_LDSMINLB, + "ldsminlh", // ARM64_INS_LDSMINLH, + "ldtr", // ARM64_INS_LDTR, + "ldtrb", // ARM64_INS_LDTRB, + "ldtrh", // ARM64_INS_LDTRH, + "ldtrsb", // ARM64_INS_LDTRSB, + "ldtrsh", // ARM64_INS_LDTRSH, + "ldtrsw", // ARM64_INS_LDTRSW, + "ldumax", // ARM64_INS_LDUMAX, + "ldumaxa", // ARM64_INS_LDUMAXA, + "ldumaxab", // ARM64_INS_LDUMAXAB, + "ldumaxah", // ARM64_INS_LDUMAXAH, + "ldumaxal", // ARM64_INS_LDUMAXAL, + "ldumaxalb", // ARM64_INS_LDUMAXALB, + "ldumaxalh", // ARM64_INS_LDUMAXALH, + "ldumaxb", // ARM64_INS_LDUMAXB, + "ldumaxh", // ARM64_INS_LDUMAXH, + "ldumaxl", // ARM64_INS_LDUMAXL, + "ldumaxlb", // ARM64_INS_LDUMAXLB, + "ldumaxlh", // ARM64_INS_LDUMAXLH, + "ldumin", // ARM64_INS_LDUMIN, + "ldumina", // ARM64_INS_LDUMINA, + "lduminab", // ARM64_INS_LDUMINAB, + "lduminah", // ARM64_INS_LDUMINAH, + "lduminal", // ARM64_INS_LDUMINAL, + "lduminalb", // ARM64_INS_LDUMINALB, + "lduminalh", // ARM64_INS_LDUMINALH, + "lduminb", // ARM64_INS_LDUMINB, + "lduminh", // ARM64_INS_LDUMINH, + "lduminl", // ARM64_INS_LDUMINL, + "lduminlb", // ARM64_INS_LDUMINLB, + "lduminlh", // ARM64_INS_LDUMINLH, + "ldur", // ARM64_INS_LDUR, + "ldurb", // ARM64_INS_LDURB, + "ldurh", // ARM64_INS_LDURH, + "ldursb", // ARM64_INS_LDURSB, + "ldursh", // ARM64_INS_LDURSH, + "ldursw", // ARM64_INS_LDURSW, + "ldxp", // ARM64_INS_LDXP, + "ldxr", // ARM64_INS_LDXR, + "ldxrb", // ARM64_INS_LDXRB, + "ldxrh", // ARM64_INS_LDXRH, + "lsl", // ARM64_INS_LSL, + "lslr", // ARM64_INS_LSLR, + "lslv", // ARM64_INS_LSLV, + "lsr", // ARM64_INS_LSR, + "lsrr", // ARM64_INS_LSRR, + "lsrv", // ARM64_INS_LSRV, + "mad", // ARM64_INS_MAD, + "madd", // ARM64_INS_MADD, + "mla", // ARM64_INS_MLA, + "mls", // ARM64_INS_MLS, + "mneg", // ARM64_INS_MNEG, + "mov", // ARM64_INS_MOV, + "movi", // ARM64_INS_MOVI, + "movk", // ARM64_INS_MOVK, + "movn", // ARM64_INS_MOVN, + "movprfx", // ARM64_INS_MOVPRFX, + "movs", // ARM64_INS_MOVS, + "movz", // ARM64_INS_MOVZ, + "mrs", // ARM64_INS_MRS, + "msb", // ARM64_INS_MSB, + "msr", // ARM64_INS_MSR, + "msub", // ARM64_INS_MSUB, + "mul", // ARM64_INS_MUL, + "mvn", // ARM64_INS_MVN, + "mvni", // ARM64_INS_MVNI, + "nand", // ARM64_INS_NAND, + "nands", // ARM64_INS_NANDS, + "neg", // ARM64_INS_NEG, + "negs", // ARM64_INS_NEGS, + "ngc", // ARM64_INS_NGC, + "ngcs", // ARM64_INS_NGCS, + "nop", // ARM64_INS_NOP, + "nor", // ARM64_INS_NOR, + "nors", // ARM64_INS_NORS, + "not", // ARM64_INS_NOT, + "nots", // ARM64_INS_NOTS, + "orn", // ARM64_INS_ORN, + "orns", // ARM64_INS_ORNS, + "orr", // ARM64_INS_ORR, + "orrs", // ARM64_INS_ORRS, + "orv", // ARM64_INS_ORV, + "pacda", // ARM64_INS_PACDA, + "pacdb", // ARM64_INS_PACDB, + "pacdza", // ARM64_INS_PACDZA, + "pacdzb", // ARM64_INS_PACDZB, + "pacga", // ARM64_INS_PACGA, + "pacia", // ARM64_INS_PACIA, + "pacia1716", // ARM64_INS_PACIA1716, + "paciasp", // ARM64_INS_PACIASP, + "paciaz", // ARM64_INS_PACIAZ, + "pacib", // ARM64_INS_PACIB, + "pacib1716", // ARM64_INS_PACIB1716, + "pacibsp", // ARM64_INS_PACIBSP, + "pacibz", // ARM64_INS_PACIBZ, + "paciza", // ARM64_INS_PACIZA, + "pacizb", // ARM64_INS_PACIZB, + "pfalse", // ARM64_INS_PFALSE, + "pfirst", // ARM64_INS_PFIRST, + "pmul", // ARM64_INS_PMUL, + "pmull", // ARM64_INS_PMULL, + "pmull2", // ARM64_INS_PMULL2, + "pnext", // ARM64_INS_PNEXT, + "prfb", // ARM64_INS_PRFB, + "prfd", // ARM64_INS_PRFD, + "prfh", // ARM64_INS_PRFH, + "prfm", // ARM64_INS_PRFM, + "prfum", // ARM64_INS_PRFUM, + "prfw", // ARM64_INS_PRFW, + "psb", // ARM64_INS_PSB, + "ptest", // ARM64_INS_PTEST, + "ptrue", // ARM64_INS_PTRUE, + "ptrues", // ARM64_INS_PTRUES, + "punpkhi", // ARM64_INS_PUNPKHI, + "punpklo", // ARM64_INS_PUNPKLO, + "raddhn", // ARM64_INS_RADDHN, + "raddhn2", // ARM64_INS_RADDHN2, + "rax1", // ARM64_INS_RAX1, + "rbit", // ARM64_INS_RBIT, + "rdffr", // ARM64_INS_RDFFR, + "rdffrs", // ARM64_INS_RDFFRS, + "rdvl", // ARM64_INS_RDVL, + "ret", // ARM64_INS_RET, + "retaa", // ARM64_INS_RETAA, + "retab", // ARM64_INS_RETAB, + "rev", // ARM64_INS_REV, + "rev16", // ARM64_INS_REV16, + "rev32", // ARM64_INS_REV32, + "rev64", // ARM64_INS_REV64, + "revb", // ARM64_INS_REVB, + "revh", // ARM64_INS_REVH, + "revw", // ARM64_INS_REVW, + "rmif", // ARM64_INS_RMIF, + "ror", // ARM64_INS_ROR, + "rorv", // ARM64_INS_RORV, + "rshrn", // ARM64_INS_RSHRN, + "rshrn2", // ARM64_INS_RSHRN2, + "rsubhn", // ARM64_INS_RSUBHN, + "rsubhn2", // ARM64_INS_RSUBHN2, + "saba", // ARM64_INS_SABA, + "sabal", // ARM64_INS_SABAL, + "sabal2", // ARM64_INS_SABAL2, + "sabd", // ARM64_INS_SABD, + "sabdl", // ARM64_INS_SABDL, + "sabdl2", // ARM64_INS_SABDL2, + "sadalp", // ARM64_INS_SADALP, + "saddl", // ARM64_INS_SADDL, + "saddl2", // ARM64_INS_SADDL2, + "saddlp", // ARM64_INS_SADDLP, + "saddlv", // ARM64_INS_SADDLV, + "saddv", // ARM64_INS_SADDV, + "saddw", // ARM64_INS_SADDW, + "saddw2", // ARM64_INS_SADDW2, + "sbc", // ARM64_INS_SBC, + "sbcs", // ARM64_INS_SBCS, + "sbfm", // ARM64_INS_SBFM, + "scvtf", // ARM64_INS_SCVTF, + "sdiv", // ARM64_INS_SDIV, + "sdivr", // ARM64_INS_SDIVR, + "sdot", // ARM64_INS_SDOT, + "sel", // ARM64_INS_SEL, + "setf16", // ARM64_INS_SETF16, + "setf8", // ARM64_INS_SETF8, + "setffr", // ARM64_INS_SETFFR, + "sev", // ARM64_INS_SEV, + "sevl", // ARM64_INS_SEVL, + "sha1c", // ARM64_INS_SHA1C, + "sha1h", // ARM64_INS_SHA1H, + "sha1m", // ARM64_INS_SHA1M, + "sha1p", // ARM64_INS_SHA1P, + "sha1su0", // ARM64_INS_SHA1SU0, + "sha1su1", // ARM64_INS_SHA1SU1, + "sha256h", // ARM64_INS_SHA256H, + "sha256h2", // ARM64_INS_SHA256H2, + "sha256su0", // ARM64_INS_SHA256SU0, + "sha256su1", // ARM64_INS_SHA256SU1, + "sha512h", // ARM64_INS_SHA512H, + "sha512h2", // ARM64_INS_SHA512H2, + "sha512su0", // ARM64_INS_SHA512SU0, + "sha512su1", // ARM64_INS_SHA512SU1, + "shadd", // ARM64_INS_SHADD, + "shl", // ARM64_INS_SHL, + "shll", // ARM64_INS_SHLL, + "shll2", // ARM64_INS_SHLL2, + "shrn", // ARM64_INS_SHRN, + "shrn2", // ARM64_INS_SHRN2, + "shsub", // ARM64_INS_SHSUB, + "sli", // ARM64_INS_SLI, + "sm3partw1", // ARM64_INS_SM3PARTW1, + "sm3partw2", // ARM64_INS_SM3PARTW2, + "sm3ss1", // ARM64_INS_SM3SS1, + "sm3tt1a", // ARM64_INS_SM3TT1A, + "sm3tt1b", // ARM64_INS_SM3TT1B, + "sm3tt2a", // ARM64_INS_SM3TT2A, + "sm3tt2b", // ARM64_INS_SM3TT2B, + "sm4e", // ARM64_INS_SM4E, + "sm4ekey", // ARM64_INS_SM4EKEY, + "smaddl", // ARM64_INS_SMADDL, + "smax", // ARM64_INS_SMAX, + "smaxp", // ARM64_INS_SMAXP, + "smaxv", // ARM64_INS_SMAXV, + "smc", // ARM64_INS_SMC, + "smin", // ARM64_INS_SMIN, + "sminp", // ARM64_INS_SMINP, + "sminv", // ARM64_INS_SMINV, + "smlal", // ARM64_INS_SMLAL, + "smlal2", // ARM64_INS_SMLAL2, + "smlsl", // ARM64_INS_SMLSL, + "smlsl2", // ARM64_INS_SMLSL2, + "smnegl", // ARM64_INS_SMNEGL, + "smov", // ARM64_INS_SMOV, + "smsubl", // ARM64_INS_SMSUBL, + "smulh", // ARM64_INS_SMULH, + "smull", // ARM64_INS_SMULL, + "smull2", // ARM64_INS_SMULL2, + "splice", // ARM64_INS_SPLICE, + "sqabs", // ARM64_INS_SQABS, + "sqadd", // ARM64_INS_SQADD, + "sqdecb", // ARM64_INS_SQDECB, + "sqdecd", // ARM64_INS_SQDECD, + "sqdech", // ARM64_INS_SQDECH, + "sqdecp", // ARM64_INS_SQDECP, + "sqdecw", // ARM64_INS_SQDECW, + "sqdmlal", // ARM64_INS_SQDMLAL, + "sqdmlal2", // ARM64_INS_SQDMLAL2, + "sqdmlsl", // ARM64_INS_SQDMLSL, + "sqdmlsl2", // ARM64_INS_SQDMLSL2, + "sqdmulh", // ARM64_INS_SQDMULH, + "sqdmull", // ARM64_INS_SQDMULL, + "sqdmull2", // ARM64_INS_SQDMULL2, + "sqincb", // ARM64_INS_SQINCB, + "sqincd", // ARM64_INS_SQINCD, + "sqinch", // ARM64_INS_SQINCH, + "sqincp", // ARM64_INS_SQINCP, + "sqincw", // ARM64_INS_SQINCW, + "sqneg", // ARM64_INS_SQNEG, + "sqrdmlah", // ARM64_INS_SQRDMLAH, + "sqrdmlsh", // ARM64_INS_SQRDMLSH, + "sqrdmulh", // ARM64_INS_SQRDMULH, + "sqrshl", // ARM64_INS_SQRSHL, + "sqrshrn", // ARM64_INS_SQRSHRN, + "sqrshrn2", // ARM64_INS_SQRSHRN2, + "sqrshrun", // ARM64_INS_SQRSHRUN, + "sqrshrun2", // ARM64_INS_SQRSHRUN2, + "sqshl", // ARM64_INS_SQSHL, + "sqshlu", // ARM64_INS_SQSHLU, + "sqshrn", // ARM64_INS_SQSHRN, + "sqshrn2", // ARM64_INS_SQSHRN2, + "sqshrun", // ARM64_INS_SQSHRUN, + "sqshrun2", // ARM64_INS_SQSHRUN2, + "sqsub", // ARM64_INS_SQSUB, + "sqxtn", // ARM64_INS_SQXTN, + "sqxtn2", // ARM64_INS_SQXTN2, + "sqxtun", // ARM64_INS_SQXTUN, + "sqxtun2", // ARM64_INS_SQXTUN2, + "srhadd", // ARM64_INS_SRHADD, + "sri", // ARM64_INS_SRI, + "srshl", // ARM64_INS_SRSHL, + "srshr", // ARM64_INS_SRSHR, + "srsra", // ARM64_INS_SRSRA, + "sshl", // ARM64_INS_SSHL, + "sshll", // ARM64_INS_SSHLL, + "sshll2", // ARM64_INS_SSHLL2, + "sshr", // ARM64_INS_SSHR, + "ssra", // ARM64_INS_SSRA, + "ssubl", // ARM64_INS_SSUBL, + "ssubl2", // ARM64_INS_SSUBL2, + "ssubw", // ARM64_INS_SSUBW, + "ssubw2", // ARM64_INS_SSUBW2, + "st1", // ARM64_INS_ST1, + "st1b", // ARM64_INS_ST1B, + "st1d", // ARM64_INS_ST1D, + "st1h", // ARM64_INS_ST1H, + "st1w", // ARM64_INS_ST1W, + "st2", // ARM64_INS_ST2, + "st2b", // ARM64_INS_ST2B, + "st2d", // ARM64_INS_ST2D, + "st2h", // ARM64_INS_ST2H, + "st2w", // ARM64_INS_ST2W, + "st3", // ARM64_INS_ST3, + "st3b", // ARM64_INS_ST3B, + "st3d", // ARM64_INS_ST3D, + "st3h", // ARM64_INS_ST3H, + "st3w", // ARM64_INS_ST3W, + "st4", // ARM64_INS_ST4, + "st4b", // ARM64_INS_ST4B, + "st4d", // ARM64_INS_ST4D, + "st4h", // ARM64_INS_ST4H, + "st4w", // ARM64_INS_ST4W, + "stadd", // ARM64_INS_STADD, + "staddb", // ARM64_INS_STADDB, + "staddh", // ARM64_INS_STADDH, + "staddl", // ARM64_INS_STADDL, + "staddlb", // ARM64_INS_STADDLB, + "staddlh", // ARM64_INS_STADDLH, + "stclr", // ARM64_INS_STCLR, + "stclrb", // ARM64_INS_STCLRB, + "stclrh", // ARM64_INS_STCLRH, + "stclrl", // ARM64_INS_STCLRL, + "stclrlb", // ARM64_INS_STCLRLB, + "stclrlh", // ARM64_INS_STCLRLH, + "steor", // ARM64_INS_STEOR, + "steorb", // ARM64_INS_STEORB, + "steorh", // ARM64_INS_STEORH, + "steorl", // ARM64_INS_STEORL, + "steorlb", // ARM64_INS_STEORLB, + "steorlh", // ARM64_INS_STEORLH, + "stllr", // ARM64_INS_STLLR, + "stllrb", // ARM64_INS_STLLRB, + "stllrh", // ARM64_INS_STLLRH, + "stlr", // ARM64_INS_STLR, + "stlrb", // ARM64_INS_STLRB, + "stlrh", // ARM64_INS_STLRH, + "stlur", // ARM64_INS_STLUR, + "stlurb", // ARM64_INS_STLURB, + "stlurh", // ARM64_INS_STLURH, + "stlxp", // ARM64_INS_STLXP, + "stlxr", // ARM64_INS_STLXR, + "stlxrb", // ARM64_INS_STLXRB, + "stlxrh", // ARM64_INS_STLXRH, + "stnp", // ARM64_INS_STNP, + "stnt1b", // ARM64_INS_STNT1B, + "stnt1d", // ARM64_INS_STNT1D, + "stnt1h", // ARM64_INS_STNT1H, + "stnt1w", // ARM64_INS_STNT1W, + "stp", // ARM64_INS_STP, + "str", // ARM64_INS_STR, + "strb", // ARM64_INS_STRB, + "strh", // ARM64_INS_STRH, + "stset", // ARM64_INS_STSET, + "stsetb", // ARM64_INS_STSETB, + "stseth", // ARM64_INS_STSETH, + "stsetl", // ARM64_INS_STSETL, + "stsetlb", // ARM64_INS_STSETLB, + "stsetlh", // ARM64_INS_STSETLH, + "stsmax", // ARM64_INS_STSMAX, + "stsmaxb", // ARM64_INS_STSMAXB, + "stsmaxh", // ARM64_INS_STSMAXH, + "stsmaxl", // ARM64_INS_STSMAXL, + "stsmaxlb", // ARM64_INS_STSMAXLB, + "stsmaxlh", // ARM64_INS_STSMAXLH, + "stsmin", // ARM64_INS_STSMIN, + "stsminb", // ARM64_INS_STSMINB, + "stsminh", // ARM64_INS_STSMINH, + "stsminl", // ARM64_INS_STSMINL, + "stsminlb", // ARM64_INS_STSMINLB, + "stsminlh", // ARM64_INS_STSMINLH, + "sttr", // ARM64_INS_STTR, + "sttrb", // ARM64_INS_STTRB, + "sttrh", // ARM64_INS_STTRH, + "stumax", // ARM64_INS_STUMAX, + "stumaxb", // ARM64_INS_STUMAXB, + "stumaxh", // ARM64_INS_STUMAXH, + "stumaxl", // ARM64_INS_STUMAXL, + "stumaxlb", // ARM64_INS_STUMAXLB, + "stumaxlh", // ARM64_INS_STUMAXLH, + "stumin", // ARM64_INS_STUMIN, + "stuminb", // ARM64_INS_STUMINB, + "stuminh", // ARM64_INS_STUMINH, + "stuminl", // ARM64_INS_STUMINL, + "stuminlb", // ARM64_INS_STUMINLB, + "stuminlh", // ARM64_INS_STUMINLH, + "stur", // ARM64_INS_STUR, + "sturb", // ARM64_INS_STURB, + "sturh", // ARM64_INS_STURH, + "stxp", // ARM64_INS_STXP, + "stxr", // ARM64_INS_STXR, + "stxrb", // ARM64_INS_STXRB, + "stxrh", // ARM64_INS_STXRH, + "sub", // ARM64_INS_SUB, + "subhn", // ARM64_INS_SUBHN, + "subhn2", // ARM64_INS_SUBHN2, + "subr", // ARM64_INS_SUBR, + "subs", // ARM64_INS_SUBS, + "sunpkhi", // ARM64_INS_SUNPKHI, + "sunpklo", // ARM64_INS_SUNPKLO, + "suqadd", // ARM64_INS_SUQADD, + "svc", // ARM64_INS_SVC, + "swp", // ARM64_INS_SWP, + "swpa", // ARM64_INS_SWPA, + "swpab", // ARM64_INS_SWPAB, + "swpah", // ARM64_INS_SWPAH, + "swpal", // ARM64_INS_SWPAL, + "swpalb", // ARM64_INS_SWPALB, + "swpalh", // ARM64_INS_SWPALH, + "swpb", // ARM64_INS_SWPB, + "swph", // ARM64_INS_SWPH, + "swpl", // ARM64_INS_SWPL, + "swplb", // ARM64_INS_SWPLB, + "swplh", // ARM64_INS_SWPLH, + "sxtb", // ARM64_INS_SXTB, + "sxth", // ARM64_INS_SXTH, + "sxtl", // ARM64_INS_SXTL, + "sxtl2", // ARM64_INS_SXTL2, + "sxtw", // ARM64_INS_SXTW, + "sys", // ARM64_INS_SYS, + "sysl", // ARM64_INS_SYSL, + "tbl", // ARM64_INS_TBL, + "tbnz", // ARM64_INS_TBNZ, + "tbx", // ARM64_INS_TBX, + "tbz", // ARM64_INS_TBZ, + "trn1", // ARM64_INS_TRN1, + "trn2", // ARM64_INS_TRN2, + "tsb", // ARM64_INS_TSB, + "tst", // ARM64_INS_TST, + "uaba", // ARM64_INS_UABA, + "uabal", // ARM64_INS_UABAL, + "uabal2", // ARM64_INS_UABAL2, + "uabd", // ARM64_INS_UABD, + "uabdl", // ARM64_INS_UABDL, + "uabdl2", // ARM64_INS_UABDL2, + "uadalp", // ARM64_INS_UADALP, + "uaddl", // ARM64_INS_UADDL, + "uaddl2", // ARM64_INS_UADDL2, + "uaddlp", // ARM64_INS_UADDLP, + "uaddlv", // ARM64_INS_UADDLV, + "uaddv", // ARM64_INS_UADDV, + "uaddw", // ARM64_INS_UADDW, + "uaddw2", // ARM64_INS_UADDW2, + "ubfm", // ARM64_INS_UBFM, + "ucvtf", // ARM64_INS_UCVTF, + "udiv", // ARM64_INS_UDIV, + "udivr", // ARM64_INS_UDIVR, + "udot", // ARM64_INS_UDOT, + "uhadd", // ARM64_INS_UHADD, + "uhsub", // ARM64_INS_UHSUB, + "umaddl", // ARM64_INS_UMADDL, + "umax", // ARM64_INS_UMAX, + "umaxp", // ARM64_INS_UMAXP, + "umaxv", // ARM64_INS_UMAXV, + "umin", // ARM64_INS_UMIN, + "uminp", // ARM64_INS_UMINP, + "uminv", // ARM64_INS_UMINV, + "umlal", // ARM64_INS_UMLAL, + "umlal2", // ARM64_INS_UMLAL2, + "umlsl", // ARM64_INS_UMLSL, + "umlsl2", // ARM64_INS_UMLSL2, + "umnegl", // ARM64_INS_UMNEGL, + "umov", // ARM64_INS_UMOV, + "umsubl", // ARM64_INS_UMSUBL, + "umulh", // ARM64_INS_UMULH, + "umull", // ARM64_INS_UMULL, + "umull2", // ARM64_INS_UMULL2, + "uqadd", // ARM64_INS_UQADD, + "uqdecb", // ARM64_INS_UQDECB, + "uqdecd", // ARM64_INS_UQDECD, + "uqdech", // ARM64_INS_UQDECH, + "uqdecp", // ARM64_INS_UQDECP, + "uqdecw", // ARM64_INS_UQDECW, + "uqincb", // ARM64_INS_UQINCB, + "uqincd", // ARM64_INS_UQINCD, + "uqinch", // ARM64_INS_UQINCH, + "uqincp", // ARM64_INS_UQINCP, + "uqincw", // ARM64_INS_UQINCW, + "uqrshl", // ARM64_INS_UQRSHL, + "uqrshrn", // ARM64_INS_UQRSHRN, + "uqrshrn2", // ARM64_INS_UQRSHRN2, + "uqshl", // ARM64_INS_UQSHL, + "uqshrn", // ARM64_INS_UQSHRN, + "uqshrn2", // ARM64_INS_UQSHRN2, + "uqsub", // ARM64_INS_UQSUB, + "uqxtn", // ARM64_INS_UQXTN, + "uqxtn2", // ARM64_INS_UQXTN2, + "urecpe", // ARM64_INS_URECPE, + "urhadd", // ARM64_INS_URHADD, + "urshl", // ARM64_INS_URSHL, + "urshr", // ARM64_INS_URSHR, + "ursqrte", // ARM64_INS_URSQRTE, + "ursra", // ARM64_INS_URSRA, + "ushl", // ARM64_INS_USHL, + "ushll", // ARM64_INS_USHLL, + "ushll2", // ARM64_INS_USHLL2, + "ushr", // ARM64_INS_USHR, + "usqadd", // ARM64_INS_USQADD, + "usra", // ARM64_INS_USRA, + "usubl", // ARM64_INS_USUBL, + "usubl2", // ARM64_INS_USUBL2, + "usubw", // ARM64_INS_USUBW, + "usubw2", // ARM64_INS_USUBW2, + "uunpkhi", // ARM64_INS_UUNPKHI, + "uunpklo", // ARM64_INS_UUNPKLO, + "uxtb", // ARM64_INS_UXTB, + "uxth", // ARM64_INS_UXTH, + "uxtl", // ARM64_INS_UXTL, + "uxtl2", // ARM64_INS_UXTL2, + "uxtw", // ARM64_INS_UXTW, + "uzp1", // ARM64_INS_UZP1, + "uzp2", // ARM64_INS_UZP2, + "wfe", // ARM64_INS_WFE, + "wfi", // ARM64_INS_WFI, + "whilele", // ARM64_INS_WHILELE, + "whilelo", // ARM64_INS_WHILELO, + "whilels", // ARM64_INS_WHILELS, + "whilelt", // ARM64_INS_WHILELT, + "wrffr", // ARM64_INS_WRFFR, + "xar", // ARM64_INS_XAR, + "xpacd", // ARM64_INS_XPACD, + "xpaci", // ARM64_INS_XPACI, + "xpaclri", // ARM64_INS_XPACLRI, + "xtn", // ARM64_INS_XTN, + "xtn2", // ARM64_INS_XTN2, + "yield", // ARM64_INS_YIELD, + "zip1", // ARM64_INS_ZIP1, + "zip2", // ARM64_INS_ZIP2, diff --git a/arch/AArch64/AArch64MappingInsnOp.inc b/arch/AArch64/AArch64MappingInsnOp.inc index 49449a406f..993626c359 100644 --- a/arch/AArch64/AArch64MappingInsnOp.inc +++ b/arch/AArch64/AArch64MappingInsnOp.inc @@ -1,21684 +1,17360 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* This is auto-gen data for Capstone disassembly engine + * (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ +{/* AArch64_ABS_ZPmZ_B, AArch64_INS_ABS: abs */ + 0, + {0}}, -{ /* AArch64_ABS_ZPmZ_B, AArch64_INS_ABS: abs */ - 0, - { 0 } -}, - -{ /* AArch64_ABS_ZPmZ_D, AArch64_INS_ABS: abs */ - 0, - { 0 } -}, - -{ /* AArch64_ABS_ZPmZ_H, AArch64_INS_ABS: abs */ - 0, - { 0 } -}, - -{ /* AArch64_ABS_ZPmZ_S, AArch64_INS_ABS: abs */ - 0, - { 0 } -}, - -{ /* AArch64_ABSv16i8, AArch64_INS_ABS: abs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ABSv1i64, AArch64_INS_ABS: abs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ABSv2i32, AArch64_INS_ABS: abs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ABSv2i64, AArch64_INS_ABS: abs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ABSv4i16, AArch64_INS_ABS: abs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ABSv4i32, AArch64_INS_ABS: abs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ABSv8i16, AArch64_INS_ABS: abs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ABSv8i8, AArch64_INS_ABS: abs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADCSWr, AArch64_INS_ADCS: adcs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADCSXr, AArch64_INS_ADCS: adcs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADCWr, AArch64_INS_ADC: adc */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADCXr, AArch64_INS_ADC: adc */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDHNv2i64_v2i32, AArch64_INS_ADDHN: addhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDHNv2i64_v4i32, AArch64_INS_ADDHN2: addhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDHNv4i32_v4i16, AArch64_INS_ADDHN: addhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDHNv4i32_v8i16, AArch64_INS_ADDHN2: addhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDHNv8i16_v16i8, AArch64_INS_ADDHN2: addhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDHNv8i16_v8i8, AArch64_INS_ADDHN: addhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDPL_XXI, AArch64_INS_ADDPL: addpl */ - 0, - { 0 } -}, - -{ /* AArch64_ADDPv16i8, AArch64_INS_ADDP: addp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDPv2i32, AArch64_INS_ADDP: addp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDPv2i64, AArch64_INS_ADDP: addp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDPv2i64p, AArch64_INS_ADDP: addp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDPv4i16, AArch64_INS_ADDP: addp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDPv4i32, AArch64_INS_ADDP: addp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDPv8i16, AArch64_INS_ADDP: addp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDPv8i8, AArch64_INS_ADDP: addp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDSWri, AArch64_INS_ADDS: adds */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ,0 } -}, - -{ /* AArch64_ADDSWrs, AArch64_INS_ADDS: adds */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDSWrx, AArch64_INS_ADDS: adds */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDSXri, AArch64_INS_ADDS: adds */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDSXrs, AArch64_INS_ADDS: adds */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDSXrx, AArch64_INS_ADDS: adds */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDSXrx64, AArch64_INS_ADDS: adds */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDVL_XXI, AArch64_INS_ADDVL: addvl */ - 0, - { 0 } -}, - -{ /* AArch64_ADDVv16i8v, AArch64_INS_ADDV: addv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDVv4i16v, AArch64_INS_ADDV: addv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDVv4i32v, AArch64_INS_ADDV: addv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDVv8i16v, AArch64_INS_ADDV: addv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDVv8i8v, AArch64_INS_ADDV: addv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDWri, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDWrs, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDWrx, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDXri, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDXrs, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDXrx, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDXrx64, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADD_ZI_B, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZI_D, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZI_H, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZI_S, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZPmZ_B, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZPmZ_D, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZPmZ_H, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZPmZ_S, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZZZ_B, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZZZ_D, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZZZ_H, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADD_ZZZ_S, AArch64_INS_ADD: add */ - 0, - { 0 } -}, - -{ /* AArch64_ADDv16i8, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDv1i64, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDv2i32, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDv2i64, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDv4i16, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDv4i32, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDv8i16, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADDv8i8, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADR, AArch64_INS_ADR: adr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADRP, AArch64_INS_ADRP: adrp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ADR_LSL_ZZZ_D_0, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_LSL_ZZZ_D_1, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_LSL_ZZZ_D_2, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_LSL_ZZZ_D_3, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_LSL_ZZZ_S_0, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_LSL_ZZZ_S_1, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_LSL_ZZZ_S_2, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_LSL_ZZZ_S_3, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_SXTW_ZZZ_D_0, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_SXTW_ZZZ_D_1, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_SXTW_ZZZ_D_2, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_SXTW_ZZZ_D_3, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_UXTW_ZZZ_D_0, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_UXTW_ZZZ_D_1, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_UXTW_ZZZ_D_2, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_ADR_UXTW_ZZZ_D_3, AArch64_INS_ADR: adr */ - 0, - { 0 } -}, - -{ /* AArch64_AESDrr, AArch64_INS_AESD: aesd */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_AESErr, AArch64_INS_AESE: aese */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_AESIMCrr, AArch64_INS_AESIMC: aesimc */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_AESMCrr, AArch64_INS_AESMC: aesmc */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ANDSWri, AArch64_INS_ANDS: ands */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ANDSWrs, AArch64_INS_ANDS: ands */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ANDSXri, AArch64_INS_ANDS: ands */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ANDSXrs, AArch64_INS_ANDS: ands */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ANDS_PPzPP, AArch64_INS_ANDS: ands */ - 0, - { 0 } -}, - -{ /* AArch64_ANDV_VPZ_B, AArch64_INS_ANDV: andv */ - 0, - { 0 } -}, - -{ /* AArch64_ANDV_VPZ_D, AArch64_INS_ANDV: andv */ - 0, - { 0 } -}, - -{ /* AArch64_ANDV_VPZ_H, AArch64_INS_ANDV: andv */ - 0, - { 0 } -}, - -{ /* AArch64_ANDV_VPZ_S, AArch64_INS_ANDV: andv */ - 0, - { 0 } -}, - -{ /* AArch64_ANDWri, AArch64_INS_AND: and */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ANDWrs, AArch64_INS_AND: and */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ANDXri, AArch64_INS_AND: and */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ANDXrs, AArch64_INS_AND: and */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_AND_PPzPP, AArch64_INS_AND: and */ - 0, - { 0 } -}, - -{ /* AArch64_AND_ZI, AArch64_INS_AND: and */ - 0, - { 0 } -}, - -{ /* AArch64_AND_ZPmZ_B, AArch64_INS_AND: and */ - 0, - { 0 } -}, - -{ /* AArch64_AND_ZPmZ_D, AArch64_INS_AND: and */ - 0, - { 0 } -}, - -{ /* AArch64_AND_ZPmZ_H, AArch64_INS_AND: and */ - 0, - { 0 } -}, - -{ /* AArch64_AND_ZPmZ_S, AArch64_INS_AND: and */ - 0, - { 0 } -}, - -{ /* AArch64_AND_ZZZ, AArch64_INS_AND: and */ - 0, - { 0 } -}, - -{ /* AArch64_ANDv16i8, AArch64_INS_AND: and */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ANDv8i8, AArch64_INS_AND: and */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ASRD_ZPmI_B, AArch64_INS_ASRD: asrd */ - 0, - { 0 } -}, - -{ /* AArch64_ASRD_ZPmI_D, AArch64_INS_ASRD: asrd */ - 0, - { 0 } -}, - -{ /* AArch64_ASRD_ZPmI_H, AArch64_INS_ASRD: asrd */ - 0, - { 0 } -}, - -{ /* AArch64_ASRD_ZPmI_S, AArch64_INS_ASRD: asrd */ - 0, - { 0 } -}, - -{ /* AArch64_ASRR_ZPmZ_B, AArch64_INS_ASRR: asrr */ - 0, - { 0 } -}, - -{ /* AArch64_ASRR_ZPmZ_D, AArch64_INS_ASRR: asrr */ - 0, - { 0 } -}, - -{ /* AArch64_ASRR_ZPmZ_H, AArch64_INS_ASRR: asrr */ - 0, - { 0 } -}, - -{ /* AArch64_ASRR_ZPmZ_S, AArch64_INS_ASRR: asrr */ - 0, - { 0 } -}, - -{ /* AArch64_ASRVWr, AArch64_INS_ASR: asr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ASRVXr, AArch64_INS_ASR: asr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ASR_WIDE_ZPmZ_B, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_WIDE_ZPmZ_H, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_WIDE_ZPmZ_S, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_WIDE_ZZZ_B, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_WIDE_ZZZ_H, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_WIDE_ZZZ_S, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZPmI_B, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZPmI_D, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZPmI_H, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZPmI_S, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZPmZ_B, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZPmZ_D, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZPmZ_H, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZPmZ_S, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZZI_B, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZZI_D, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZZI_H, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_ASR_ZZI_S, AArch64_INS_ASR: asr */ - 0, - { 0 } -}, - -{ /* AArch64_AUTDA, AArch64_INS_AUTDA: autda */ - 0, - { 0 } -}, - -{ /* AArch64_AUTDB, AArch64_INS_AUTDB: autdb */ - 0, - { 0 } -}, - -{ /* AArch64_AUTDZA, AArch64_INS_AUTDZA: autdza */ - 0, - { 0 } -}, - -{ /* AArch64_AUTDZB, AArch64_INS_AUTDZB: autdzb */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIA, AArch64_INS_AUTIA: autia */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIA1716, AArch64_INS_AUTIA1716: autia1716 */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIASP, AArch64_INS_AUTIASP: autiasp */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIAZ, AArch64_INS_AUTIAZ: autiaz */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIB, AArch64_INS_AUTIB: autib */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIB1716, AArch64_INS_AUTIB1716: autib1716 */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIBSP, AArch64_INS_AUTIBSP: autibsp */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIBZ, AArch64_INS_AUTIBZ: autibz */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIZA, AArch64_INS_AUTIZA: autiza */ - 0, - { 0 } -}, - -{ /* AArch64_AUTIZB, AArch64_INS_AUTIZB: autizb */ - 0, - { 0 } -}, - -{ /* AArch64_B, AArch64_INS_B: b */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_BCAX, AArch64_INS_BCAX: bcax */ - 0, - { 0 } -}, - -{ /* AArch64_BFMWri, AArch64_INS_BFM: bfm */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_BFMXri, AArch64_INS_BFM: bfm */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_BICSWrs, AArch64_INS_BICS: bics */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BICSXrs, AArch64_INS_BICS: bics */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BICS_PPzPP, AArch64_INS_BICS: bics */ - 0, - { 0 } -}, - -{ /* AArch64_BICWrs, AArch64_INS_BIC: bic */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BICXrs, AArch64_INS_BIC: bic */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BIC_PPzPP, AArch64_INS_BIC: bic */ - 0, - { 0 } -}, - -{ /* AArch64_BIC_ZPmZ_B, AArch64_INS_BIC: bic */ - 0, - { 0 } -}, - -{ /* AArch64_BIC_ZPmZ_D, AArch64_INS_BIC: bic */ - 0, - { 0 } -}, - -{ /* AArch64_BIC_ZPmZ_H, AArch64_INS_BIC: bic */ - 0, - { 0 } -}, - -{ /* AArch64_BIC_ZPmZ_S, AArch64_INS_BIC: bic */ - 0, - { 0 } -}, - -{ /* AArch64_BIC_ZZZ, AArch64_INS_BIC: bic */ - 0, - { 0 } -}, - -{ /* AArch64_BICv16i8, AArch64_INS_BIC: bic */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BICv2i32, AArch64_INS_BIC: bic */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_BICv4i16, AArch64_INS_BIC: bic */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_BICv4i32, AArch64_INS_BIC: bic */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_BICv8i16, AArch64_INS_BIC: bic */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_BICv8i8, AArch64_INS_BIC: bic */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_BIFv16i8, AArch64_INS_BIF: bif */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BIFv8i8, AArch64_INS_BIF: bif */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BITv16i8, AArch64_INS_BIT: bit */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BITv8i8, AArch64_INS_BIT: bit */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BL, AArch64_INS_BL: bl */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_BLR, AArch64_INS_BLR: blr */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_BLRAA, AArch64_INS_BLRAA: blraa */ - 0, - { 0 } -}, - -{ /* AArch64_BLRAAZ, AArch64_INS_BLRAAZ: blraaz */ - 0, - { 0 } -}, - -{ /* AArch64_BLRAB, AArch64_INS_BLRAB: blrab */ - 0, - { 0 } -}, - -{ /* AArch64_BLRABZ, AArch64_INS_BLRABZ: blrabz */ - 0, - { 0 } -}, - -{ /* AArch64_BR, AArch64_INS_BR: br */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_BRAA, AArch64_INS_BRAA: braa */ - 0, - { 0 } -}, - -{ /* AArch64_BRAAZ, AArch64_INS_BRAAZ: braaz */ - 0, - { 0 } -}, - -{ /* AArch64_BRAB, AArch64_INS_BRAB: brab */ - 0, - { 0 } -}, - -{ /* AArch64_BRABZ, AArch64_INS_BRABZ: brabz */ - 0, - { 0 } -}, - -{ /* AArch64_BRK, AArch64_INS_BRK: brk */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_BRKAS_PPzP, AArch64_INS_BRKAS: brkas */ - 0, - { 0 } -}, - -{ /* AArch64_BRKA_PPmP, AArch64_INS_BRKA: brka */ - 0, - { 0 } -}, - -{ /* AArch64_BRKA_PPzP, AArch64_INS_BRKA: brka */ - 0, - { 0 } -}, - -{ /* AArch64_BRKBS_PPzP, AArch64_INS_BRKBS: brkbs */ - 0, - { 0 } -}, - -{ /* AArch64_BRKB_PPmP, AArch64_INS_BRKB: brkb */ - 0, - { 0 } -}, - -{ /* AArch64_BRKB_PPzP, AArch64_INS_BRKB: brkb */ - 0, - { 0 } -}, - -{ /* AArch64_BRKNS_PPzP, AArch64_INS_BRKNS: brkns */ - 0, - { 0 } -}, - -{ /* AArch64_BRKN_PPzP, AArch64_INS_BRKN: brkn */ - 0, - { 0 } -}, - -{ /* AArch64_BRKPAS_PPzPP, AArch64_INS_BRKPAS: brkpas */ - 0, - { 0 } -}, - -{ /* AArch64_BRKPA_PPzPP, AArch64_INS_BRKPA: brkpa */ - 0, - { 0 } -}, - -{ /* AArch64_BRKPBS_PPzPP, AArch64_INS_BRKPBS: brkpbs */ - 0, - { 0 } -}, - -{ /* AArch64_BRKPB_PPzPP, AArch64_INS_BRKPB: brkpb */ - 0, - { 0 } -}, - -{ /* AArch64_BSLv16i8, AArch64_INS_BSL: bsl */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_BSLv8i8, AArch64_INS_BSL: bsl */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_Bcc, AArch64_INS_B: b */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_CASAB, AArch64_INS_CASAB: casab */ - 0, - { 0 } -}, - -{ /* AArch64_CASAH, AArch64_INS_CASAH: casah */ - 0, - { 0 } -}, - -{ /* AArch64_CASALB, AArch64_INS_CASALB: casalb */ - 0, - { 0 } -}, - -{ /* AArch64_CASALH, AArch64_INS_CASALH: casalh */ - 0, - { 0 } -}, - -{ /* AArch64_CASALW, AArch64_INS_CASAL: casal */ - 0, - { 0 } -}, - -{ /* AArch64_CASALX, AArch64_INS_CASAL: casal */ - 0, - { 0 } -}, - -{ /* AArch64_CASAW, AArch64_INS_CASA: casa */ - 0, - { 0 } -}, - -{ /* AArch64_CASAX, AArch64_INS_CASA: casa */ - 0, - { 0 } -}, - -{ /* AArch64_CASB, AArch64_INS_CASB: casb */ - 0, - { 0 } -}, - -{ /* AArch64_CASH, AArch64_INS_CASH: cash */ - 0, - { 0 } -}, - -{ /* AArch64_CASLB, AArch64_INS_CASLB: caslb */ - 0, - { 0 } -}, - -{ /* AArch64_CASLH, AArch64_INS_CASLH: caslh */ - 0, - { 0 } -}, - -{ /* AArch64_CASLW, AArch64_INS_CASL: casl */ - 0, - { 0 } -}, - -{ /* AArch64_CASLX, AArch64_INS_CASL: casl */ - 0, - { 0 } -}, - -{ /* AArch64_CASPALW, AArch64_INS_CASPAL: caspal */ - 0, - { 0 } -}, - -{ /* AArch64_CASPALX, AArch64_INS_CASPAL: caspal */ - 0, - { 0 } -}, - -{ /* AArch64_CASPAW, AArch64_INS_CASPA: caspa */ - 0, - { 0 } -}, - -{ /* AArch64_CASPAX, AArch64_INS_CASPA: caspa */ - 0, - { 0 } -}, - -{ /* AArch64_CASPLW, AArch64_INS_CASPL: caspl */ - 0, - { 0 } -}, - -{ /* AArch64_CASPLX, AArch64_INS_CASPL: caspl */ - 0, - { 0 } -}, - -{ /* AArch64_CASPW, AArch64_INS_CASP: casp */ - 0, - { 0 } -}, - -{ /* AArch64_CASPX, AArch64_INS_CASP: casp */ - 0, - { 0 } -}, - -{ /* AArch64_CASW, AArch64_INS_CAS: cas */ - 0, - { 0 } -}, - -{ /* AArch64_CASX, AArch64_INS_CAS: cas */ - 0, - { 0 } -}, - -{ /* AArch64_CBNZW, AArch64_INS_CBNZ: cbnz */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CBNZX, AArch64_INS_CBNZ: cbnz */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CBZW, AArch64_INS_CBZ: cbz */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CBZX, AArch64_INS_CBZ: cbz */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CCMNWi, AArch64_INS_CCMN: ccmn */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CCMNWr, AArch64_INS_CCMN: ccmn */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CCMNXi, AArch64_INS_CCMN: ccmn */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CCMNXr, AArch64_INS_CCMN: ccmn */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CCMPWi, AArch64_INS_CCMP: ccmp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CCMPWr, AArch64_INS_CCMP: ccmp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CCMPXi, AArch64_INS_CCMP: ccmp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CCMPXr, AArch64_INS_CCMP: ccmp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CFINV, AArch64_INS_CFINV: cfinv */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_RPZ_B, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_RPZ_D, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_RPZ_H, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_RPZ_S, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_VPZ_B, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_VPZ_D, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_VPZ_H, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_VPZ_S, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_ZPZ_B, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_ZPZ_D, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_ZPZ_H, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTA_ZPZ_S, AArch64_INS_CLASTA: clasta */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_RPZ_B, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_RPZ_D, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_RPZ_H, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_RPZ_S, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_VPZ_B, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_VPZ_D, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_VPZ_H, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_VPZ_S, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_ZPZ_B, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_ZPZ_D, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_ZPZ_H, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLASTB_ZPZ_S, AArch64_INS_CLASTB: clastb */ - 0, - { 0 } -}, - -{ /* AArch64_CLREX, AArch64_INS_CLREX: clrex */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_CLSWr, AArch64_INS_CLS: cls */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLSXr, AArch64_INS_CLS: cls */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLS_ZPmZ_B, AArch64_INS_CLS: cls */ - 0, - { 0 } -}, - -{ /* AArch64_CLS_ZPmZ_D, AArch64_INS_CLS: cls */ - 0, - { 0 } -}, - -{ /* AArch64_CLS_ZPmZ_H, AArch64_INS_CLS: cls */ - 0, - { 0 } -}, - -{ /* AArch64_CLS_ZPmZ_S, AArch64_INS_CLS: cls */ - 0, - { 0 } -}, - -{ /* AArch64_CLSv16i8, AArch64_INS_CLS: cls */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLSv2i32, AArch64_INS_CLS: cls */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLSv4i16, AArch64_INS_CLS: cls */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLSv4i32, AArch64_INS_CLS: cls */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLSv8i16, AArch64_INS_CLS: cls */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLSv8i8, AArch64_INS_CLS: cls */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLZWr, AArch64_INS_CLZ: clz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLZXr, AArch64_INS_CLZ: clz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLZ_ZPmZ_B, AArch64_INS_CLZ: clz */ - 0, - { 0 } -}, - -{ /* AArch64_CLZ_ZPmZ_D, AArch64_INS_CLZ: clz */ - 0, - { 0 } -}, - -{ /* AArch64_CLZ_ZPmZ_H, AArch64_INS_CLZ: clz */ - 0, - { 0 } -}, - -{ /* AArch64_CLZ_ZPmZ_S, AArch64_INS_CLZ: clz */ - 0, - { 0 } -}, - -{ /* AArch64_CLZv16i8, AArch64_INS_CLZ: clz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLZv2i32, AArch64_INS_CLZ: clz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLZv4i16, AArch64_INS_CLZ: clz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLZv4i32, AArch64_INS_CLZ: clz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLZv8i16, AArch64_INS_CLZ: clz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CLZv8i8, AArch64_INS_CLZ: clz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv16i8, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv16i8rz, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv1i64, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv1i64rz, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv2i32, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv2i32rz, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv2i64, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv2i64rz, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv4i16, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv4i16rz, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv4i32, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv4i32rz, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv8i16, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv8i16rz, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv8i8, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMEQv8i8rz, AArch64_INS_CMEQ: cmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv16i8, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv16i8rz, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv1i64, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv1i64rz, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv2i32, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv2i32rz, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv2i64, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv2i64rz, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv4i16, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv4i16rz, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv4i32, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv4i32rz, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv8i16, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv8i16rz, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv8i8, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGEv8i8rz, AArch64_INS_CMGE: cmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv16i8, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv16i8rz, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv1i64, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv1i64rz, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv2i32, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv2i32rz, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv2i64, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv2i64rz, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv4i16, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv4i16rz, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv4i32, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv4i32rz, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv8i16, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv8i16rz, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv8i8, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMGTv8i8rz, AArch64_INS_CMGT: cmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHIv16i8, AArch64_INS_CMHI: cmhi */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHIv1i64, AArch64_INS_CMHI: cmhi */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHIv2i32, AArch64_INS_CMHI: cmhi */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHIv2i64, AArch64_INS_CMHI: cmhi */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHIv4i16, AArch64_INS_CMHI: cmhi */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHIv4i32, AArch64_INS_CMHI: cmhi */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHIv8i16, AArch64_INS_CMHI: cmhi */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHIv8i8, AArch64_INS_CMHI: cmhi */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHSv16i8, AArch64_INS_CMHS: cmhs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHSv1i64, AArch64_INS_CMHS: cmhs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHSv2i32, AArch64_INS_CMHS: cmhs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHSv2i64, AArch64_INS_CMHS: cmhs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHSv4i16, AArch64_INS_CMHS: cmhs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHSv4i32, AArch64_INS_CMHS: cmhs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHSv8i16, AArch64_INS_CMHS: cmhs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMHSv8i8, AArch64_INS_CMHS: cmhs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLEv16i8rz, AArch64_INS_CMLE: cmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLEv1i64rz, AArch64_INS_CMLE: cmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLEv2i32rz, AArch64_INS_CMLE: cmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLEv2i64rz, AArch64_INS_CMLE: cmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLEv4i16rz, AArch64_INS_CMLE: cmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLEv4i32rz, AArch64_INS_CMLE: cmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLEv8i16rz, AArch64_INS_CMLE: cmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLEv8i8rz, AArch64_INS_CMLE: cmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLTv16i8rz, AArch64_INS_CMLT: cmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLTv1i64rz, AArch64_INS_CMLT: cmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLTv2i32rz, AArch64_INS_CMLT: cmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLTv2i64rz, AArch64_INS_CMLT: cmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLTv4i16rz, AArch64_INS_CMLT: cmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLTv4i32rz, AArch64_INS_CMLT: cmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLTv8i16rz, AArch64_INS_CMLT: cmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMLTv8i8rz, AArch64_INS_CMLT: cmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMPEQ_PPzZI_B, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_PPzZI_D, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_PPzZI_H, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_PPzZI_S, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_PPzZZ_B, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_PPzZZ_D, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_PPzZZ_H, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_PPzZZ_S, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_WIDE_PPzZZ_B, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_WIDE_PPzZZ_H, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPEQ_WIDE_PPzZZ_S, AArch64_INS_CMPEQ: cmpeq */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_PPzZI_B, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_PPzZI_D, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_PPzZI_H, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_PPzZI_S, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_PPzZZ_B, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_PPzZZ_D, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_PPzZZ_H, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_PPzZZ_S, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_WIDE_PPzZZ_B, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_WIDE_PPzZZ_H, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGE_WIDE_PPzZZ_S, AArch64_INS_CMPGE: cmpge */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_PPzZI_B, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_PPzZI_D, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_PPzZI_H, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_PPzZI_S, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_PPzZZ_B, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_PPzZZ_D, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_PPzZZ_H, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_PPzZZ_S, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_WIDE_PPzZZ_B, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_WIDE_PPzZZ_H, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPGT_WIDE_PPzZZ_S, AArch64_INS_CMPGT: cmpgt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_PPzZI_B, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_PPzZI_D, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_PPzZI_H, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_PPzZI_S, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_PPzZZ_B, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_PPzZZ_D, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_PPzZZ_H, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_PPzZZ_S, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_WIDE_PPzZZ_B, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_WIDE_PPzZZ_H, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHI_WIDE_PPzZZ_S, AArch64_INS_CMPHI: cmphi */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_PPzZI_B, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_PPzZI_D, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_PPzZI_H, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_PPzZI_S, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_PPzZZ_B, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_PPzZZ_D, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_PPzZZ_H, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_PPzZZ_S, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_WIDE_PPzZZ_B, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_WIDE_PPzZZ_H, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPHS_WIDE_PPzZZ_S, AArch64_INS_CMPHS: cmphs */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLE_PPzZI_B, AArch64_INS_CMPLE: cmple */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLE_PPzZI_D, AArch64_INS_CMPLE: cmple */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLE_PPzZI_H, AArch64_INS_CMPLE: cmple */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLE_PPzZI_S, AArch64_INS_CMPLE: cmple */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLE_WIDE_PPzZZ_B, AArch64_INS_CMPLE: cmple */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLE_WIDE_PPzZZ_H, AArch64_INS_CMPLE: cmple */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLE_WIDE_PPzZZ_S, AArch64_INS_CMPLE: cmple */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLO_PPzZI_B, AArch64_INS_CMPLO: cmplo */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLO_PPzZI_D, AArch64_INS_CMPLO: cmplo */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLO_PPzZI_H, AArch64_INS_CMPLO: cmplo */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLO_PPzZI_S, AArch64_INS_CMPLO: cmplo */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLO_WIDE_PPzZZ_B, AArch64_INS_CMPLO: cmplo */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLO_WIDE_PPzZZ_H, AArch64_INS_CMPLO: cmplo */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLO_WIDE_PPzZZ_S, AArch64_INS_CMPLO: cmplo */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLS_PPzZI_B, AArch64_INS_CMPLS: cmpls */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLS_PPzZI_D, AArch64_INS_CMPLS: cmpls */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLS_PPzZI_H, AArch64_INS_CMPLS: cmpls */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLS_PPzZI_S, AArch64_INS_CMPLS: cmpls */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLS_WIDE_PPzZZ_B, AArch64_INS_CMPLS: cmpls */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLS_WIDE_PPzZZ_H, AArch64_INS_CMPLS: cmpls */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLS_WIDE_PPzZZ_S, AArch64_INS_CMPLS: cmpls */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLT_PPzZI_B, AArch64_INS_CMPLT: cmplt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLT_PPzZI_D, AArch64_INS_CMPLT: cmplt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLT_PPzZI_H, AArch64_INS_CMPLT: cmplt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLT_PPzZI_S, AArch64_INS_CMPLT: cmplt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLT_WIDE_PPzZZ_B, AArch64_INS_CMPLT: cmplt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLT_WIDE_PPzZZ_H, AArch64_INS_CMPLT: cmplt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPLT_WIDE_PPzZZ_S, AArch64_INS_CMPLT: cmplt */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_PPzZI_B, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_PPzZI_D, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_PPzZI_H, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_PPzZI_S, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_PPzZZ_B, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_PPzZZ_D, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_PPzZZ_H, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_PPzZZ_S, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_WIDE_PPzZZ_B, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_WIDE_PPzZZ_H, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMPNE_WIDE_PPzZZ_S, AArch64_INS_CMPNE: cmpne */ - 0, - { 0 } -}, - -{ /* AArch64_CMTSTv16i8, AArch64_INS_CMTST: cmtst */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMTSTv1i64, AArch64_INS_CMTST: cmtst */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMTSTv2i32, AArch64_INS_CMTST: cmtst */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMTSTv2i64, AArch64_INS_CMTST: cmtst */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMTSTv4i16, AArch64_INS_CMTST: cmtst */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMTSTv4i32, AArch64_INS_CMTST: cmtst */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMTSTv8i16, AArch64_INS_CMTST: cmtst */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CMTSTv8i8, AArch64_INS_CMTST: cmtst */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CNOT_ZPmZ_B, AArch64_INS_CNOT: cnot */ - 0, - { 0 } -}, - -{ /* AArch64_CNOT_ZPmZ_D, AArch64_INS_CNOT: cnot */ - 0, - { 0 } -}, - -{ /* AArch64_CNOT_ZPmZ_H, AArch64_INS_CNOT: cnot */ - 0, - { 0 } -}, - -{ /* AArch64_CNOT_ZPmZ_S, AArch64_INS_CNOT: cnot */ - 0, - { 0 } -}, - -{ /* AArch64_CNTB_XPiI, AArch64_INS_CNTB: cntb */ - 0, - { 0 } -}, - -{ /* AArch64_CNTD_XPiI, AArch64_INS_CNTD: cntd */ - 0, - { 0 } -}, - -{ /* AArch64_CNTH_XPiI, AArch64_INS_CNTH: cnth */ - 0, - { 0 } -}, - -{ /* AArch64_CNTP_XPP_B, AArch64_INS_CNTP: cntp */ - 0, - { 0 } -}, - -{ /* AArch64_CNTP_XPP_D, AArch64_INS_CNTP: cntp */ - 0, - { 0 } -}, - -{ /* AArch64_CNTP_XPP_H, AArch64_INS_CNTP: cntp */ - 0, - { 0 } -}, - -{ /* AArch64_CNTP_XPP_S, AArch64_INS_CNTP: cntp */ - 0, - { 0 } -}, - -{ /* AArch64_CNTW_XPiI, AArch64_INS_CNTW: cntw */ - 0, - { 0 } -}, - -{ /* AArch64_CNT_ZPmZ_B, AArch64_INS_CNT: cnt */ - 0, - { 0 } -}, - -{ /* AArch64_CNT_ZPmZ_D, AArch64_INS_CNT: cnt */ - 0, - { 0 } -}, - -{ /* AArch64_CNT_ZPmZ_H, AArch64_INS_CNT: cnt */ - 0, - { 0 } -}, - -{ /* AArch64_CNT_ZPmZ_S, AArch64_INS_CNT: cnt */ - 0, - { 0 } -}, - -{ /* AArch64_CNTv16i8, AArch64_INS_CNT: cnt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_CNTv8i8, AArch64_INS_CNT: cnt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_COMPACT_ZPZ_D, AArch64_INS_COMPACT: compact */ - 0, - { 0 } -}, - -{ /* AArch64_COMPACT_ZPZ_S, AArch64_INS_COMPACT: compact */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmI_B, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmI_D, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmI_H, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmI_S, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmR_B, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmR_D, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmR_H, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmR_S, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmV_B, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmV_D, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmV_H, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPmV_S, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPzI_B, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPzI_D, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPzI_H, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPY_ZPzI_S, AArch64_INS_CPY: cpy */ - 0, - { 0 } -}, - -{ /* AArch64_CPYi16, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CPYi32, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CPYi64, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CPYi8, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CRC32Brr, AArch64_INS_CRC32B: crc32b */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CRC32CBrr, AArch64_INS_CRC32CB: crc32cb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CRC32CHrr, AArch64_INS_CRC32CH: crc32ch */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CRC32CWrr, AArch64_INS_CRC32CW: crc32cw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CRC32CXrr, AArch64_INS_CRC32CX: crc32cx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CRC32Hrr, AArch64_INS_CRC32H: crc32h */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CRC32Wrr, AArch64_INS_CRC32W: crc32w */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CRC32Xrr, AArch64_INS_CRC32X: crc32x */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_CSELWr, AArch64_INS_CSEL: csel */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CSELXr, AArch64_INS_CSEL: csel */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CSINCWr, AArch64_INS_CINC: cinc */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CSINCXr, AArch64_INS_CINC: cinc */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CSINVWr, AArch64_INS_CINV: cinv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CSINVXr, AArch64_INS_CINV: cinv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CSNEGWr, AArch64_INS_CNEG: cneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CSNEGXr, AArch64_INS_CNEG: cneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_CTERMEQ_WW, AArch64_INS_CTERMEQ: ctermeq */ - 0, - { 0 } -}, - -{ /* AArch64_CTERMEQ_XX, AArch64_INS_CTERMEQ: ctermeq */ - 0, - { 0 } -}, - -{ /* AArch64_CTERMNE_WW, AArch64_INS_CTERMNE: ctermne */ - 0, - { 0 } -}, - -{ /* AArch64_CTERMNE_XX, AArch64_INS_CTERMNE: ctermne */ - 0, - { 0 } -}, - -{ /* AArch64_DCPS1, AArch64_INS_DCPS1: dcps1 */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_DCPS2, AArch64_INS_DCPS2: dcps2 */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_DCPS3, AArch64_INS_DCPS3: dcps3 */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_DECB_XPiI, AArch64_INS_DECB: decb */ - 0, - { 0 } -}, - -{ /* AArch64_DECD_XPiI, AArch64_INS_DECD: decd */ - 0, - { 0 } -}, - -{ /* AArch64_DECD_ZPiI, AArch64_INS_DECD: decd */ - 0, - { 0 } -}, - -{ /* AArch64_DECH_XPiI, AArch64_INS_DECH: dech */ - 0, - { 0 } -}, - -{ /* AArch64_DECH_ZPiI, AArch64_INS_DECH: dech */ - 0, - { 0 } -}, - -{ /* AArch64_DECP_XP_B, AArch64_INS_DECP: decp */ - 0, - { 0 } -}, - -{ /* AArch64_DECP_XP_D, AArch64_INS_DECP: decp */ - 0, - { 0 } -}, - -{ /* AArch64_DECP_XP_H, AArch64_INS_DECP: decp */ - 0, - { 0 } -}, - -{ /* AArch64_DECP_XP_S, AArch64_INS_DECP: decp */ - 0, - { 0 } -}, - -{ /* AArch64_DECP_ZP_D, AArch64_INS_DECP: decp */ - 0, - { 0 } -}, - -{ /* AArch64_DECP_ZP_H, AArch64_INS_DECP: decp */ - 0, - { 0 } -}, - -{ /* AArch64_DECP_ZP_S, AArch64_INS_DECP: decp */ - 0, - { 0 } -}, - -{ /* AArch64_DECW_XPiI, AArch64_INS_DECW: decw */ - 0, - { 0 } -}, - -{ /* AArch64_DECW_ZPiI, AArch64_INS_DECW: decw */ - 0, - { 0 } -}, - -{ /* AArch64_DMB, AArch64_INS_DMB: dmb */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_DRPS, AArch64_INS_DRPS: drps */ - 0, - { 0 } -}, - -{ /* AArch64_DSB, AArch64_INS_DSB: dsb */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPM_ZI, AArch64_INS_DUPM: dupm */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZI_B, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZI_D, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZI_H, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZI_S, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZR_B, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZR_D, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZR_H, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZR_S, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZZI_B, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZZI_D, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZZI_H, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZZI_Q, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUP_ZZI_S, AArch64_INS_DUP: dup */ - 0, - { 0 } -}, - -{ /* AArch64_DUPv16i8gpr, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv16i8lane, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv2i32gpr, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv2i32lane, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv2i64gpr, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv2i64lane, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv4i16gpr, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv4i16lane, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv4i32gpr, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv4i32lane, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv8i16gpr, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv8i16lane, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv8i8gpr, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_DUPv8i8lane, AArch64_INS_DUP: dup */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_EONWrs, AArch64_INS_EON: eon */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_EONXrs, AArch64_INS_EON: eon */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_EOR3, AArch64_INS_EOR3: eor3 */ - 0, - { 0 } -}, - -{ /* AArch64_EORS_PPzPP, AArch64_INS_EORS: eors */ - 0, - { 0 } -}, - -{ /* AArch64_EORV_VPZ_B, AArch64_INS_EORV: eorv */ - 0, - { 0 } -}, - -{ /* AArch64_EORV_VPZ_D, AArch64_INS_EORV: eorv */ - 0, - { 0 } -}, - -{ /* AArch64_EORV_VPZ_H, AArch64_INS_EORV: eorv */ - 0, - { 0 } -}, - -{ /* AArch64_EORV_VPZ_S, AArch64_INS_EORV: eorv */ - 0, - { 0 } -}, - -{ /* AArch64_EORWri, AArch64_INS_EON: eon */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_EORWrs, AArch64_INS_EOR: eor */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_EORXri, AArch64_INS_EON: eon */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_EORXrs, AArch64_INS_EOR: eor */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_EOR_PPzPP, AArch64_INS_EOR: eor */ - 0, - { 0 } -}, - -{ /* AArch64_EOR_ZI, AArch64_INS_EON: eon */ - 0, - { 0 } -}, - -{ /* AArch64_EOR_ZPmZ_B, AArch64_INS_EOR: eor */ - 0, - { 0 } -}, - -{ /* AArch64_EOR_ZPmZ_D, AArch64_INS_EOR: eor */ - 0, - { 0 } -}, - -{ /* AArch64_EOR_ZPmZ_H, AArch64_INS_EOR: eor */ - 0, - { 0 } -}, - -{ /* AArch64_EOR_ZPmZ_S, AArch64_INS_EOR: eor */ - 0, - { 0 } -}, - -{ /* AArch64_EOR_ZZZ, AArch64_INS_EOR: eor */ - 0, - { 0 } -}, - -{ /* AArch64_EORv16i8, AArch64_INS_EOR: eor */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_EORv8i8, AArch64_INS_EOR: eor */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ERET, AArch64_INS_ERET: eret */ - 0, - { 0 } -}, - -{ /* AArch64_ERETAA, AArch64_INS_ERETAA: eretaa */ - 0, - { 0 } -}, - -{ /* AArch64_ERETAB, AArch64_INS_ERETAB: eretab */ - 0, - { 0 } -}, - -{ /* AArch64_EXTRWrri, AArch64_INS_EXTR: extr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_EXTRXrri, AArch64_INS_EXTR: extr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_EXT_ZZI, AArch64_INS_EXT: ext */ - 0, - { 0 } -}, - -{ /* AArch64_EXTv16i8, AArch64_INS_EXT: ext */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_EXTv8i8, AArch64_INS_EXT: ext */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FABD16, AArch64_INS_FABD: fabd */ - 0, - { 0 } -}, - -{ /* AArch64_FABD32, AArch64_INS_FABD: fabd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABD64, AArch64_INS_FABD: fabd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABD_ZPmZ_D, AArch64_INS_FABD: fabd */ - 0, - { 0 } -}, - -{ /* AArch64_FABD_ZPmZ_H, AArch64_INS_FABD: fabd */ - 0, - { 0 } -}, - -{ /* AArch64_FABD_ZPmZ_S, AArch64_INS_FABD: fabd */ - 0, - { 0 } -}, - -{ /* AArch64_FABDv2f32, AArch64_INS_FABD: fabd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABDv2f64, AArch64_INS_FABD: fabd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABDv4f16, AArch64_INS_FABD: fabd */ - 0, - { 0 } -}, - -{ /* AArch64_FABDv4f32, AArch64_INS_FABD: fabd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABDv8f16, AArch64_INS_FABD: fabd */ - 0, - { 0 } -}, - -{ /* AArch64_FABSDr, AArch64_INS_FABS: fabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABSHr, AArch64_INS_FABS: fabs */ - 0, - { 0 } -}, - -{ /* AArch64_FABSSr, AArch64_INS_FABS: fabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABS_ZPmZ_D, AArch64_INS_FABS: fabs */ - 0, - { 0 } -}, - -{ /* AArch64_FABS_ZPmZ_H, AArch64_INS_FABS: fabs */ - 0, - { 0 } -}, - -{ /* AArch64_FABS_ZPmZ_S, AArch64_INS_FABS: fabs */ - 0, - { 0 } -}, - -{ /* AArch64_FABSv2f32, AArch64_INS_FABS: fabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABSv2f64, AArch64_INS_FABS: fabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABSv4f16, AArch64_INS_FABS: fabs */ - 0, - { 0 } -}, - -{ /* AArch64_FABSv4f32, AArch64_INS_FABS: fabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FABSv8f16, AArch64_INS_FABS: fabs */ - 0, - { 0 } -}, - -{ /* AArch64_FACGE16, AArch64_INS_FACGE: facge */ - 0, - { 0 } -}, - -{ /* AArch64_FACGE32, AArch64_INS_FACGE: facge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGE64, AArch64_INS_FACGE: facge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGE_PPzZZ_D, AArch64_INS_FACGE: facge */ - 0, - { 0 } -}, - -{ /* AArch64_FACGE_PPzZZ_H, AArch64_INS_FACGE: facge */ - 0, - { 0 } -}, - -{ /* AArch64_FACGE_PPzZZ_S, AArch64_INS_FACGE: facge */ - 0, - { 0 } -}, - -{ /* AArch64_FACGEv2f32, AArch64_INS_FACGE: facge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGEv2f64, AArch64_INS_FACGE: facge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGEv4f16, AArch64_INS_FACGE: facge */ - 0, - { 0 } -}, - -{ /* AArch64_FACGEv4f32, AArch64_INS_FACGE: facge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGEv8f16, AArch64_INS_FACGE: facge */ - 0, - { 0 } -}, - -{ /* AArch64_FACGT16, AArch64_INS_FACGT: facgt */ - 0, - { 0 } -}, - -{ /* AArch64_FACGT32, AArch64_INS_FACGT: facgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGT64, AArch64_INS_FACGT: facgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGT_PPzZZ_D, AArch64_INS_FACGT: facgt */ - 0, - { 0 } -}, - -{ /* AArch64_FACGT_PPzZZ_H, AArch64_INS_FACGT: facgt */ - 0, - { 0 } -}, - -{ /* AArch64_FACGT_PPzZZ_S, AArch64_INS_FACGT: facgt */ - 0, - { 0 } -}, - -{ /* AArch64_FACGTv2f32, AArch64_INS_FACGT: facgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGTv2f64, AArch64_INS_FACGT: facgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGTv4f16, AArch64_INS_FACGT: facgt */ - 0, - { 0 } -}, - -{ /* AArch64_FACGTv4f32, AArch64_INS_FACGT: facgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FACGTv8f16, AArch64_INS_FACGT: facgt */ - 0, - { 0 } -}, - -{ /* AArch64_FADDA_VPZ_D, AArch64_INS_FADDA: fadda */ - 0, - { 0 } -}, - -{ /* AArch64_FADDA_VPZ_H, AArch64_INS_FADDA: fadda */ - 0, - { 0 } -}, - -{ /* AArch64_FADDA_VPZ_S, AArch64_INS_FADDA: fadda */ - 0, - { 0 } -}, - -{ /* AArch64_FADDDrr, AArch64_INS_FADD: fadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDHrr, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADDPv2f32, AArch64_INS_FADDP: faddp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDPv2f64, AArch64_INS_FADDP: faddp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDPv2i16p, AArch64_INS_FADDP: faddp */ - 0, - { 0 } -}, - -{ /* AArch64_FADDPv2i32p, AArch64_INS_FADDP: faddp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDPv2i64p, AArch64_INS_FADDP: faddp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDPv4f16, AArch64_INS_FADDP: faddp */ - 0, - { 0 } -}, - -{ /* AArch64_FADDPv4f32, AArch64_INS_FADDP: faddp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDPv8f16, AArch64_INS_FADDP: faddp */ - 0, - { 0 } -}, - -{ /* AArch64_FADDSrr, AArch64_INS_FADD: fadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDV_VPZ_D, AArch64_INS_FADDV: faddv */ - 0, - { 0 } -}, - -{ /* AArch64_FADDV_VPZ_H, AArch64_INS_FADDV: faddv */ - 0, - { 0 } -}, - -{ /* AArch64_FADDV_VPZ_S, AArch64_INS_FADDV: faddv */ - 0, - { 0 } -}, - -{ /* AArch64_FADD_ZPmI_D, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADD_ZPmI_H, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADD_ZPmI_S, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADD_ZPmZ_D, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADD_ZPmZ_H, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADD_ZPmZ_S, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADD_ZZZ_D, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADD_ZZZ_H, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADD_ZZZ_S, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADDv2f32, AArch64_INS_FADD: fadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDv2f64, AArch64_INS_FADD: fadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDv4f16, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FADDv4f32, AArch64_INS_FADD: fadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FADDv8f16, AArch64_INS_FADD: fadd */ - 0, - { 0 } -}, - -{ /* AArch64_FCADD_ZPmZ_D, AArch64_INS_FCADD: fcadd */ - 0, - { 0 } -}, - -{ /* AArch64_FCADD_ZPmZ_H, AArch64_INS_FCADD: fcadd */ - 0, - { 0 } -}, - -{ /* AArch64_FCADD_ZPmZ_S, AArch64_INS_FCADD: fcadd */ - 0, - { 0 } -}, - -{ /* AArch64_FCADDv2f32, AArch64_INS_FCADD: fcadd */ - 0, - { 0 } -}, - -{ /* AArch64_FCADDv2f64, AArch64_INS_FCADD: fcadd */ - 0, - { 0 } -}, - -{ /* AArch64_FCADDv4f16, AArch64_INS_FCADD: fcadd */ - 0, - { 0 } -}, - -{ /* AArch64_FCADDv4f32, AArch64_INS_FCADD: fcadd */ - 0, - { 0 } -}, - -{ /* AArch64_FCADDv8f16, AArch64_INS_FCADD: fcadd */ - 0, - { 0 } -}, - -{ /* AArch64_FCCMPDrr, AArch64_INS_FCCMP: fccmp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } -}, - -{ /* AArch64_FCCMPEDrr, AArch64_INS_FCCMPE: fccmpe */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } -}, - -{ /* AArch64_FCCMPEHrr, AArch64_INS_FCCMPE: fccmpe */ - 0, - { 0 } -}, - -{ /* AArch64_FCCMPESrr, AArch64_INS_FCCMPE: fccmpe */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } -}, - -{ /* AArch64_FCCMPHrr, AArch64_INS_FCCMP: fccmp */ - 0, - { 0 } -}, - -{ /* AArch64_FCCMPSrr, AArch64_INS_FCCMP: fccmp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } -}, - -{ /* AArch64_FCMEQ16, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQ32, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQ64, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQ_PPzZ0_D, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQ_PPzZ0_H, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQ_PPzZ0_S, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQ_PPzZZ_D, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQ_PPzZZ_H, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQ_PPzZZ_S, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQv1i16rz, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQv1i32rz, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQv1i64rz, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQv2f32, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQv2f64, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQv2i32rz, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQv2i64rz, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQv4f16, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQv4f32, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQv4i16rz, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQv4i32rz, AArch64_INS_FCMEQ: fcmeq */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMEQv8f16, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMEQv8i16rz, AArch64_INS_FCMEQ: fcmeq */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGE16, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGE32, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGE64, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGE_PPzZ0_D, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGE_PPzZ0_H, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGE_PPzZ0_S, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGE_PPzZZ_D, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGE_PPzZZ_H, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGE_PPzZZ_S, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGEv1i16rz, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGEv1i32rz, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGEv1i64rz, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGEv2f32, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGEv2f64, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGEv2i32rz, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGEv2i64rz, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGEv4f16, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGEv4f32, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGEv4i16rz, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGEv4i32rz, AArch64_INS_FCMGE: fcmge */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGEv8f16, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGEv8i16rz, AArch64_INS_FCMGE: fcmge */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGT16, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGT32, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGT64, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGT_PPzZ0_D, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGT_PPzZ0_H, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGT_PPzZ0_S, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGT_PPzZZ_D, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGT_PPzZZ_H, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGT_PPzZZ_S, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGTv1i16rz, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGTv1i32rz, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGTv1i64rz, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGTv2f32, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGTv2f64, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGTv2i32rz, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGTv2i64rz, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGTv4f16, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGTv4f32, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGTv4i16rz, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGTv4i32rz, AArch64_INS_FCMGT: fcmgt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMGTv8f16, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMGTv8i16rz, AArch64_INS_FCMGT: fcmgt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLA_ZPmZZ_D, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLA_ZPmZZ_H, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLA_ZPmZZ_S, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLA_ZZZI_H, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLA_ZZZI_S, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLAv2f32, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLAv2f64, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLAv4f16, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLAv4f16_indexed, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLAv4f32, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLAv4f32_indexed, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLAv8f16, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLAv8f16_indexed, AArch64_INS_FCMLA: fcmla */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLE_PPzZ0_D, AArch64_INS_FCMLE: fcmle */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLE_PPzZ0_H, AArch64_INS_FCMLE: fcmle */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLE_PPzZ0_S, AArch64_INS_FCMLE: fcmle */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLEv1i16rz, AArch64_INS_FCMLE: fcmle */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLEv1i32rz, AArch64_INS_FCMLE: fcmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLEv1i64rz, AArch64_INS_FCMLE: fcmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLEv2i32rz, AArch64_INS_FCMLE: fcmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLEv2i64rz, AArch64_INS_FCMLE: fcmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLEv4i16rz, AArch64_INS_FCMLE: fcmle */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLEv4i32rz, AArch64_INS_FCMLE: fcmle */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLEv8i16rz, AArch64_INS_FCMLE: fcmle */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLT_PPzZ0_D, AArch64_INS_FCMLT: fcmlt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLT_PPzZ0_H, AArch64_INS_FCMLT: fcmlt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLT_PPzZ0_S, AArch64_INS_FCMLT: fcmlt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLTv1i16rz, AArch64_INS_FCMLT: fcmlt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLTv1i32rz, AArch64_INS_FCMLT: fcmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLTv1i64rz, AArch64_INS_FCMLT: fcmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLTv2i32rz, AArch64_INS_FCMLT: fcmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLTv2i64rz, AArch64_INS_FCMLT: fcmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLTv4i16rz, AArch64_INS_FCMLT: fcmlt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMLTv4i32rz, AArch64_INS_FCMLT: fcmlt */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMLTv8i16rz, AArch64_INS_FCMLT: fcmlt */ - 0, - { 0 } -}, - -{ /* AArch64_FCMNE_PPzZ0_D, AArch64_INS_FCMNE: fcmne */ - 0, - { 0 } -}, - -{ /* AArch64_FCMNE_PPzZ0_H, AArch64_INS_FCMNE: fcmne */ - 0, - { 0 } -}, - -{ /* AArch64_FCMNE_PPzZ0_S, AArch64_INS_FCMNE: fcmne */ - 0, - { 0 } -}, - -{ /* AArch64_FCMNE_PPzZZ_D, AArch64_INS_FCMNE: fcmne */ - 0, - { 0 } -}, - -{ /* AArch64_FCMNE_PPzZZ_H, AArch64_INS_FCMNE: fcmne */ - 0, - { 0 } -}, - -{ /* AArch64_FCMNE_PPzZZ_S, AArch64_INS_FCMNE: fcmne */ - 0, - { 0 } -}, - -{ /* AArch64_FCMPDri, AArch64_INS_FCMP: fcmp */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMPDrr, AArch64_INS_FCMP: fcmp */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMPEDri, AArch64_INS_FCMPE: fcmpe */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMPEDrr, AArch64_INS_FCMPE: fcmpe */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMPEHri, AArch64_INS_FCMPE: fcmpe */ - 0, - { 0 } -}, - -{ /* AArch64_FCMPEHrr, AArch64_INS_FCMPE: fcmpe */ - 0, - { 0 } -}, - -{ /* AArch64_FCMPESri, AArch64_INS_FCMPE: fcmpe */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMPESrr, AArch64_INS_FCMPE: fcmpe */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMPHri, AArch64_INS_FCMP: fcmp */ - 0, - { 0 } -}, - -{ /* AArch64_FCMPHrr, AArch64_INS_FCMP: fcmp */ - 0, - { 0 } -}, - -{ /* AArch64_FCMPSri, AArch64_INS_FCMP: fcmp */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMPSrr, AArch64_INS_FCMP: fcmp */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCMUO_PPzZZ_D, AArch64_INS_FCMUO: fcmuo */ - 0, - { 0 } -}, - -{ /* AArch64_FCMUO_PPzZZ_H, AArch64_INS_FCMUO: fcmuo */ - 0, - { 0 } -}, - -{ /* AArch64_FCMUO_PPzZZ_S, AArch64_INS_FCMUO: fcmuo */ - 0, - { 0 } -}, - -{ /* AArch64_FCPY_ZPmI_D, AArch64_INS_FCPY: fcpy */ - 0, - { 0 } -}, - -{ /* AArch64_FCPY_ZPmI_H, AArch64_INS_FCPY: fcpy */ - 0, - { 0 } -}, - -{ /* AArch64_FCPY_ZPmI_S, AArch64_INS_FCPY: fcpy */ - 0, - { 0 } -}, - -{ /* AArch64_FCSELDrrr, AArch64_INS_FCSEL: fcsel */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FCSELHrrr, AArch64_INS_FCSEL: fcsel */ - 0, - { 0 } -}, - -{ /* AArch64_FCSELSrrr, AArch64_INS_FCSEL: fcsel */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FCVTASUWDr, AArch64_INS_FCVTAS: fcvtas */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTASUWHr, AArch64_INS_FCVTAS: fcvtas */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTASUWSr, AArch64_INS_FCVTAS: fcvtas */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTASUXDr, AArch64_INS_FCVTAS: fcvtas */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTASUXHr, AArch64_INS_FCVTAS: fcvtas */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTASUXSr, AArch64_INS_FCVTAS: fcvtas */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTASv1f16, AArch64_INS_FCVTAS: fcvtas */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTASv1i32, AArch64_INS_FCVTAS: fcvtas */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTASv1i64, AArch64_INS_FCVTAS: fcvtas */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTASv2f32, AArch64_INS_FCVTAS: fcvtas */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTASv2f64, AArch64_INS_FCVTAS: fcvtas */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTASv4f16, AArch64_INS_FCVTAS: fcvtas */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTASv4f32, AArch64_INS_FCVTAS: fcvtas */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTASv8f16, AArch64_INS_FCVTAS: fcvtas */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTAUUWDr, AArch64_INS_FCVTAU: fcvtau */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTAUUWHr, AArch64_INS_FCVTAU: fcvtau */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTAUUWSr, AArch64_INS_FCVTAU: fcvtau */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTAUUXDr, AArch64_INS_FCVTAU: fcvtau */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTAUUXHr, AArch64_INS_FCVTAU: fcvtau */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTAUUXSr, AArch64_INS_FCVTAU: fcvtau */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTAUv1f16, AArch64_INS_FCVTAU: fcvtau */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTAUv1i32, AArch64_INS_FCVTAU: fcvtau */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTAUv1i64, AArch64_INS_FCVTAU: fcvtau */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTAUv2f32, AArch64_INS_FCVTAU: fcvtau */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTAUv2f64, AArch64_INS_FCVTAU: fcvtau */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTAUv4f16, AArch64_INS_FCVTAU: fcvtau */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTAUv4f32, AArch64_INS_FCVTAU: fcvtau */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTAUv8f16, AArch64_INS_FCVTAU: fcvtau */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTDHr, AArch64_INS_FCVT: fcvt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTDSr, AArch64_INS_FCVT: fcvt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTHDr, AArch64_INS_FCVT: fcvt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTHSr, AArch64_INS_FCVT: fcvt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTLv2i32, AArch64_INS_FCVTL: fcvtl */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTLv4i16, AArch64_INS_FCVTL: fcvtl */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTLv4i32, AArch64_INS_FCVTL2: fcvtl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTLv8i16, AArch64_INS_FCVTL2: fcvtl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSUWDr, AArch64_INS_FCVTMS: fcvtms */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSUWHr, AArch64_INS_FCVTMS: fcvtms */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTMSUWSr, AArch64_INS_FCVTMS: fcvtms */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSUXDr, AArch64_INS_FCVTMS: fcvtms */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSUXHr, AArch64_INS_FCVTMS: fcvtms */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTMSUXSr, AArch64_INS_FCVTMS: fcvtms */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSv1f16, AArch64_INS_FCVTMS: fcvtms */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTMSv1i32, AArch64_INS_FCVTMS: fcvtms */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSv1i64, AArch64_INS_FCVTMS: fcvtms */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSv2f32, AArch64_INS_FCVTMS: fcvtms */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSv2f64, AArch64_INS_FCVTMS: fcvtms */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSv4f16, AArch64_INS_FCVTMS: fcvtms */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTMSv4f32, AArch64_INS_FCVTMS: fcvtms */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMSv8f16, AArch64_INS_FCVTMS: fcvtms */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTMUUWDr, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMUUWHr, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTMUUWSr, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMUUXDr, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMUUXHr, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTMUUXSr, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMUv1f16, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTMUv1i32, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMUv1i64, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMUv2f32, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMUv2f64, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMUv4f16, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTMUv4f32, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTMUv8f16, AArch64_INS_FCVTMU: fcvtmu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNSUWDr, AArch64_INS_FCVTNS: fcvtns */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNSUWHr, AArch64_INS_FCVTNS: fcvtns */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNSUWSr, AArch64_INS_FCVTNS: fcvtns */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNSUXDr, AArch64_INS_FCVTNS: fcvtns */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNSUXHr, AArch64_INS_FCVTNS: fcvtns */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNSUXSr, AArch64_INS_FCVTNS: fcvtns */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNSv1f16, AArch64_INS_FCVTNS: fcvtns */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNSv1i32, AArch64_INS_FCVTNS: fcvtns */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNSv1i64, AArch64_INS_FCVTNS: fcvtns */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNSv2f32, AArch64_INS_FCVTNS: fcvtns */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNSv2f64, AArch64_INS_FCVTNS: fcvtns */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNSv4f16, AArch64_INS_FCVTNS: fcvtns */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNSv4f32, AArch64_INS_FCVTNS: fcvtns */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNSv8f16, AArch64_INS_FCVTNS: fcvtns */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNUUWDr, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNUUWHr, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNUUWSr, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNUUXDr, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNUUXHr, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNUUXSr, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNUv1f16, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNUv1i32, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNUv1i64, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNUv2f32, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNUv2f64, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNUv4f16, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNUv4f32, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNUv8f16, AArch64_INS_FCVTNU: fcvtnu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTNv2i32, AArch64_INS_FCVTN: fcvtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNv4i16, AArch64_INS_FCVTN: fcvtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNv4i32, AArch64_INS_FCVTN2: fcvtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTNv8i16, AArch64_INS_FCVTN2: fcvtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSUWDr, AArch64_INS_FCVTPS: fcvtps */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSUWHr, AArch64_INS_FCVTPS: fcvtps */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTPSUWSr, AArch64_INS_FCVTPS: fcvtps */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSUXDr, AArch64_INS_FCVTPS: fcvtps */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSUXHr, AArch64_INS_FCVTPS: fcvtps */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTPSUXSr, AArch64_INS_FCVTPS: fcvtps */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSv1f16, AArch64_INS_FCVTPS: fcvtps */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTPSv1i32, AArch64_INS_FCVTPS: fcvtps */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSv1i64, AArch64_INS_FCVTPS: fcvtps */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSv2f32, AArch64_INS_FCVTPS: fcvtps */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSv2f64, AArch64_INS_FCVTPS: fcvtps */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSv4f16, AArch64_INS_FCVTPS: fcvtps */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTPSv4f32, AArch64_INS_FCVTPS: fcvtps */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPSv8f16, AArch64_INS_FCVTPS: fcvtps */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTPUUWDr, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPUUWHr, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTPUUWSr, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPUUXDr, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPUUXHr, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTPUUXSr, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPUv1f16, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTPUv1i32, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPUv1i64, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPUv2f32, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPUv2f64, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPUv4f16, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTPUv4f32, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTPUv8f16, AArch64_INS_FCVTPU: fcvtpu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTSDr, AArch64_INS_FCVT: fcvt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTSHr, AArch64_INS_FCVT: fcvt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTXNv1i64, AArch64_INS_FCVTXN: fcvtxn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTXNv2f32, AArch64_INS_FCVTXN: fcvtxn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTXNv4f32, AArch64_INS_FCVTXN2: fcvtxn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSSWDri, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSSWHri, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSSWSri, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSSXDri, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSSXHri, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSSXSri, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSUWDr, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSUWHr, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSUWSr, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSUXDr, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSUXHr, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSUXSr, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZS_ZPmZ_DtoD, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZS_ZPmZ_DtoS, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZS_ZPmZ_HtoD, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZS_ZPmZ_HtoH, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZS_ZPmZ_HtoS, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZS_ZPmZ_StoD, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZS_ZPmZ_StoS, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSd, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSh, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSs, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSv1f16, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSv1i32, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSv1i64, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSv2f32, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSv2f64, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSv2i32_shift, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSv2i64_shift, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSv4f16, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSv4f32, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSv4i16_shift, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSv4i32_shift, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZSv8f16, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZSv8i16_shift, AArch64_INS_FCVTZS: fcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUSWDri, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUSWHri, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUSWSri, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUSXDri, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUSXHri, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUSXSri, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUUWDr, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUUWHr, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUUWSr, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUUXDr, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUUXHr, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUUXSr, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZU_ZPmZ_DtoD, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZU_ZPmZ_DtoS, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZU_ZPmZ_HtoD, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZU_ZPmZ_HtoH, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZU_ZPmZ_HtoS, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZU_ZPmZ_StoD, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZU_ZPmZ_StoS, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUd, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUh, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUs, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUv1f16, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUv1i32, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUv1i64, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUv2f32, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUv2f64, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUv2i32_shift, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUv2i64_shift, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUv4f16, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUv4f32, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUv4i16_shift, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUv4i32_shift, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FCVTZUv8f16, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVTZUv8i16_shift, AArch64_INS_FCVTZU: fcvtzu */ - 0, - { 0 } -}, - -{ /* AArch64_FCVT_ZPmZ_DtoH, AArch64_INS_FCVT: fcvt */ - 0, - { 0 } -}, - -{ /* AArch64_FCVT_ZPmZ_DtoS, AArch64_INS_FCVT: fcvt */ - 0, - { 0 } -}, - -{ /* AArch64_FCVT_ZPmZ_HtoD, AArch64_INS_FCVT: fcvt */ - 0, - { 0 } -}, - -{ /* AArch64_FCVT_ZPmZ_HtoS, AArch64_INS_FCVT: fcvt */ - 0, - { 0 } -}, - -{ /* AArch64_FCVT_ZPmZ_StoD, AArch64_INS_FCVT: fcvt */ - 0, - { 0 } -}, - -{ /* AArch64_FCVT_ZPmZ_StoH, AArch64_INS_FCVT: fcvt */ - 0, - { 0 } -}, - -{ /* AArch64_FDIVDrr, AArch64_INS_FDIV: fdiv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FDIVHrr, AArch64_INS_FDIV: fdiv */ - 0, - { 0 } -}, - -{ /* AArch64_FDIVR_ZPmZ_D, AArch64_INS_FDIVR: fdivr */ - 0, - { 0 } -}, - -{ /* AArch64_FDIVR_ZPmZ_H, AArch64_INS_FDIVR: fdivr */ - 0, - { 0 } -}, - -{ /* AArch64_FDIVR_ZPmZ_S, AArch64_INS_FDIVR: fdivr */ - 0, - { 0 } -}, - -{ /* AArch64_FDIVSrr, AArch64_INS_FDIV: fdiv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FDIV_ZPmZ_D, AArch64_INS_FDIV: fdiv */ - 0, - { 0 } -}, - -{ /* AArch64_FDIV_ZPmZ_H, AArch64_INS_FDIV: fdiv */ - 0, - { 0 } -}, - -{ /* AArch64_FDIV_ZPmZ_S, AArch64_INS_FDIV: fdiv */ - 0, - { 0 } -}, - -{ /* AArch64_FDIVv2f32, AArch64_INS_FDIV: fdiv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FDIVv2f64, AArch64_INS_FDIV: fdiv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FDIVv4f16, AArch64_INS_FDIV: fdiv */ - 0, - { 0 } -}, - -{ /* AArch64_FDIVv4f32, AArch64_INS_FDIV: fdiv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FDIVv8f16, AArch64_INS_FDIV: fdiv */ - 0, - { 0 } -}, - -{ /* AArch64_FDUP_ZI_D, AArch64_INS_FDUP: fdup */ - 0, - { 0 } -}, - -{ /* AArch64_FDUP_ZI_H, AArch64_INS_FDUP: fdup */ - 0, - { 0 } -}, - -{ /* AArch64_FDUP_ZI_S, AArch64_INS_FDUP: fdup */ - 0, - { 0 } -}, - -{ /* AArch64_FEXPA_ZZ_D, AArch64_INS_FEXPA: fexpa */ - 0, - { 0 } -}, - -{ /* AArch64_FEXPA_ZZ_H, AArch64_INS_FEXPA: fexpa */ - 0, - { 0 } -}, - -{ /* AArch64_FEXPA_ZZ_S, AArch64_INS_FEXPA: fexpa */ - 0, - { 0 } -}, - -{ /* AArch64_FJCVTZS, AArch64_INS_FJCVTZS: fjcvtzs */ - 0, - { 0 } -}, - -{ /* AArch64_FMADDDrrr, AArch64_INS_FMADD: fmadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMADDHrrr, AArch64_INS_FMADD: fmadd */ - 0, - { 0 } -}, - -{ /* AArch64_FMADDSrrr, AArch64_INS_FMADD: fmadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMAD_ZPmZZ_D, AArch64_INS_FMAD: fmad */ - 0, - { 0 } -}, - -{ /* AArch64_FMAD_ZPmZZ_H, AArch64_INS_FMAD: fmad */ - 0, - { 0 } -}, - -{ /* AArch64_FMAD_ZPmZZ_S, AArch64_INS_FMAD: fmad */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXDrr, AArch64_INS_FMAX: fmax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXHrr, AArch64_INS_FMAX: fmax */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMDrr, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMHrr, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMPv2f32, AArch64_INS_FMAXNMP: fmaxnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMPv2f64, AArch64_INS_FMAXNMP: fmaxnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMPv2i16p, AArch64_INS_FMAXNMP: fmaxnmp */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMPv2i32p, AArch64_INS_FMAXNMP: fmaxnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMPv2i64p, AArch64_INS_FMAXNMP: fmaxnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMPv4f16, AArch64_INS_FMAXNMP: fmaxnmp */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMPv4f32, AArch64_INS_FMAXNMP: fmaxnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMPv8f16, AArch64_INS_FMAXNMP: fmaxnmp */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMSrr, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMV_VPZ_D, AArch64_INS_FMAXNMV: fmaxnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMV_VPZ_H, AArch64_INS_FMAXNMV: fmaxnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMV_VPZ_S, AArch64_INS_FMAXNMV: fmaxnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMVv4i16v, AArch64_INS_FMAXNMV: fmaxnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMVv4i32v, AArch64_INS_FMAXNMV: fmaxnmv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMVv8i16v, AArch64_INS_FMAXNMV: fmaxnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNM_ZPmI_D, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNM_ZPmI_H, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNM_ZPmI_S, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNM_ZPmZ_D, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNM_ZPmZ_H, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNM_ZPmZ_S, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMv2f32, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMv2f64, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMv4f16, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXNMv4f32, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXNMv8f16, AArch64_INS_FMAXNM: fmaxnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXPv2f32, AArch64_INS_FMAXP: fmaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXPv2f64, AArch64_INS_FMAXP: fmaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXPv2i16p, AArch64_INS_FMAXP: fmaxp */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXPv2i32p, AArch64_INS_FMAXP: fmaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXPv2i64p, AArch64_INS_FMAXP: fmaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXPv4f16, AArch64_INS_FMAXP: fmaxp */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXPv4f32, AArch64_INS_FMAXP: fmaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXPv8f16, AArch64_INS_FMAXP: fmaxp */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXSrr, AArch64_INS_FMAX: fmax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXV_VPZ_D, AArch64_INS_FMAXV: fmaxv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXV_VPZ_H, AArch64_INS_FMAXV: fmaxv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXV_VPZ_S, AArch64_INS_FMAXV: fmaxv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXVv4i16v, AArch64_INS_FMAXV: fmaxv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXVv4i32v, AArch64_INS_FMAXV: fmaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXVv8i16v, AArch64_INS_FMAXV: fmaxv */ - 0, - { 0 } -}, - -{ /* AArch64_FMAX_ZPmI_D, AArch64_INS_FMAX: fmax */ - 0, - { 0 } -}, - -{ /* AArch64_FMAX_ZPmI_H, AArch64_INS_FMAX: fmax */ - 0, - { 0 } -}, - -{ /* AArch64_FMAX_ZPmI_S, AArch64_INS_FMAX: fmax */ - 0, - { 0 } -}, - -{ /* AArch64_FMAX_ZPmZ_D, AArch64_INS_FMAX: fmax */ - 0, - { 0 } -}, - -{ /* AArch64_FMAX_ZPmZ_H, AArch64_INS_FMAX: fmax */ - 0, - { 0 } -}, - -{ /* AArch64_FMAX_ZPmZ_S, AArch64_INS_FMAX: fmax */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXv2f32, AArch64_INS_FMAX: fmax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXv2f64, AArch64_INS_FMAX: fmax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXv4f16, AArch64_INS_FMAX: fmax */ - 0, - { 0 } -}, - -{ /* AArch64_FMAXv4f32, AArch64_INS_FMAX: fmax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMAXv8f16, AArch64_INS_FMAX: fmax */ - 0, - { 0 } -}, - -{ /* AArch64_FMINDrr, AArch64_INS_FMIN: fmin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINHrr, AArch64_INS_FMIN: fmin */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMDrr, AArch64_INS_FMINNM: fminnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMHrr, AArch64_INS_FMINNM: fminnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMPv2f32, AArch64_INS_FMINNMP: fminnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMPv2f64, AArch64_INS_FMINNMP: fminnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMPv2i16p, AArch64_INS_FMINNMP: fminnmp */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMPv2i32p, AArch64_INS_FMINNMP: fminnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMPv2i64p, AArch64_INS_FMINNMP: fminnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMPv4f16, AArch64_INS_FMINNMP: fminnmp */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMPv4f32, AArch64_INS_FMINNMP: fminnmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMPv8f16, AArch64_INS_FMINNMP: fminnmp */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMSrr, AArch64_INS_FMINNM: fminnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMV_VPZ_D, AArch64_INS_FMINNMV: fminnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMV_VPZ_H, AArch64_INS_FMINNMV: fminnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMV_VPZ_S, AArch64_INS_FMINNMV: fminnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMVv4i16v, AArch64_INS_FMINNMV: fminnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMVv4i32v, AArch64_INS_FMINNMV: fminnmv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMVv8i16v, AArch64_INS_FMINNMV: fminnmv */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNM_ZPmI_D, AArch64_INS_FMINNM: fminnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNM_ZPmI_H, AArch64_INS_FMINNM: fminnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNM_ZPmI_S, AArch64_INS_FMINNM: fminnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNM_ZPmZ_D, AArch64_INS_FMINNM: fminnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNM_ZPmZ_H, AArch64_INS_FMINNM: fminnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNM_ZPmZ_S, AArch64_INS_FMINNM: fminnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMv2f32, AArch64_INS_FMINNM: fminnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMv2f64, AArch64_INS_FMINNM: fminnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMv4f16, AArch64_INS_FMINNM: fminnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMINNMv4f32, AArch64_INS_FMINNM: fminnm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINNMv8f16, AArch64_INS_FMINNM: fminnm */ - 0, - { 0 } -}, - -{ /* AArch64_FMINPv2f32, AArch64_INS_FMINP: fminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINPv2f64, AArch64_INS_FMINP: fminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINPv2i16p, AArch64_INS_FMINP: fminp */ - 0, - { 0 } -}, - -{ /* AArch64_FMINPv2i32p, AArch64_INS_FMINP: fminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINPv2i64p, AArch64_INS_FMINP: fminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINPv4f16, AArch64_INS_FMINP: fminp */ - 0, - { 0 } -}, - -{ /* AArch64_FMINPv4f32, AArch64_INS_FMINP: fminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINPv8f16, AArch64_INS_FMINP: fminp */ - 0, - { 0 } -}, - -{ /* AArch64_FMINSrr, AArch64_INS_FMIN: fmin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINV_VPZ_D, AArch64_INS_FMINV: fminv */ - 0, - { 0 } -}, - -{ /* AArch64_FMINV_VPZ_H, AArch64_INS_FMINV: fminv */ - 0, - { 0 } -}, - -{ /* AArch64_FMINV_VPZ_S, AArch64_INS_FMINV: fminv */ - 0, - { 0 } -}, - -{ /* AArch64_FMINVv4i16v, AArch64_INS_FMINV: fminv */ - 0, - { 0 } -}, - -{ /* AArch64_FMINVv4i32v, AArch64_INS_FMINV: fminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINVv8i16v, AArch64_INS_FMINV: fminv */ - 0, - { 0 } -}, - -{ /* AArch64_FMIN_ZPmI_D, AArch64_INS_FMIN: fmin */ - 0, - { 0 } -}, - -{ /* AArch64_FMIN_ZPmI_H, AArch64_INS_FMIN: fmin */ - 0, - { 0 } -}, - -{ /* AArch64_FMIN_ZPmI_S, AArch64_INS_FMIN: fmin */ - 0, - { 0 } -}, - -{ /* AArch64_FMIN_ZPmZ_D, AArch64_INS_FMIN: fmin */ - 0, - { 0 } -}, - -{ /* AArch64_FMIN_ZPmZ_H, AArch64_INS_FMIN: fmin */ - 0, - { 0 } -}, - -{ /* AArch64_FMIN_ZPmZ_S, AArch64_INS_FMIN: fmin */ - 0, - { 0 } -}, - -{ /* AArch64_FMINv2f32, AArch64_INS_FMIN: fmin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINv2f64, AArch64_INS_FMIN: fmin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINv4f16, AArch64_INS_FMIN: fmin */ - 0, - { 0 } -}, - -{ /* AArch64_FMINv4f32, AArch64_INS_FMIN: fmin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMINv8f16, AArch64_INS_FMIN: fmin */ - 0, - { 0 } -}, - -{ /* AArch64_FMLA_ZPmZZ_D, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLA_ZPmZZ_H, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLA_ZPmZZ_S, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLA_ZZZI_D, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLA_ZZZI_H, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLA_ZZZI_S, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLAv1i16_indexed, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLAv1i32_indexed, AArch64_INS_FMLA: fmla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLAv1i64_indexed, AArch64_INS_FMLA: fmla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLAv2f32, AArch64_INS_FMLA: fmla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMLAv2f64, AArch64_INS_FMLA: fmla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMLAv2i32_indexed, AArch64_INS_FMLA: fmla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLAv2i64_indexed, AArch64_INS_FMLA: fmla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLAv4f16, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLAv4f32, AArch64_INS_FMLA: fmla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMLAv4i16_indexed, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLAv4i32_indexed, AArch64_INS_FMLA: fmla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLAv8f16, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLAv8i16_indexed, AArch64_INS_FMLA: fmla */ - 0, - { 0 } -}, - -{ /* AArch64_FMLS_ZPmZZ_D, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLS_ZPmZZ_H, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLS_ZPmZZ_S, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLS_ZZZI_D, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLS_ZZZI_H, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLS_ZZZI_S, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLSv1i16_indexed, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLSv1i32_indexed, AArch64_INS_FMLS: fmls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLSv1i64_indexed, AArch64_INS_FMLS: fmls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLSv2f32, AArch64_INS_FMLS: fmls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMLSv2f64, AArch64_INS_FMLS: fmls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMLSv2i32_indexed, AArch64_INS_FMLS: fmls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLSv2i64_indexed, AArch64_INS_FMLS: fmls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLSv4f16, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLSv4f32, AArch64_INS_FMLS: fmls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMLSv4i16_indexed, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLSv4i32_indexed, AArch64_INS_FMLS: fmls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMLSv8f16, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMLSv8i16_indexed, AArch64_INS_FMLS: fmls */ - 0, - { 0 } -}, - -{ /* AArch64_FMOVDXHighr, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVDXr, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVDi, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVDr, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVHWr, AArch64_INS_FMOV: fmov */ - 0, - { 0 } -}, - -{ /* AArch64_FMOVHXr, AArch64_INS_FMOV: fmov */ - 0, - { 0 } -}, - -{ /* AArch64_FMOVHi, AArch64_INS_FMOV: fmov */ - 0, - { 0 } -}, - -{ /* AArch64_FMOVHr, AArch64_INS_FMOV: fmov */ - 0, - { 0 } -}, - -{ /* AArch64_FMOVSWr, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVSi, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVSr, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVWHr, AArch64_INS_FMOV: fmov */ - 0, - { 0 } -}, - -{ /* AArch64_FMOVWSr, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVXDHighr, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVXDr, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMOVXHr, AArch64_INS_FMOV: fmov */ - 0, - { 0 } -}, - -{ /* AArch64_FMOVv2f32_ns, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } -}, - -{ /* AArch64_FMOVv2f64_ns, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } -}, - -{ /* AArch64_FMOVv4f16_ns, AArch64_INS_FMOV: fmov */ - 0, - { 0 } -}, - -{ /* AArch64_FMOVv4f32_ns, AArch64_INS_FMOV: fmov */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } -}, - -{ /* AArch64_FMOVv8f16_ns, AArch64_INS_FMOV: fmov */ - 0, - { 0 } -}, - -{ /* AArch64_FMSB_ZPmZZ_D, AArch64_INS_FMSB: fmsb */ - 0, - { 0 } -}, - -{ /* AArch64_FMSB_ZPmZZ_H, AArch64_INS_FMSB: fmsb */ - 0, - { 0 } -}, - -{ /* AArch64_FMSB_ZPmZZ_S, AArch64_INS_FMSB: fmsb */ - 0, - { 0 } -}, - -{ /* AArch64_FMSUBDrrr, AArch64_INS_FMSUB: fmsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMSUBHrrr, AArch64_INS_FMSUB: fmsub */ - 0, - { 0 } -}, - -{ /* AArch64_FMSUBSrrr, AArch64_INS_FMSUB: fmsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULDrr, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULHrr, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMULSrr, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULX16, AArch64_INS_FMULX: fmulx */ - 0, - { 0 } -}, - -{ /* AArch64_FMULX32, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULX64, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULX_ZPmZ_D, AArch64_INS_FMULX: fmulx */ - 0, - { 0 } -}, - -{ /* AArch64_FMULX_ZPmZ_H, AArch64_INS_FMULX: fmulx */ - 0, - { 0 } -}, - -{ /* AArch64_FMULX_ZPmZ_S, AArch64_INS_FMULX: fmulx */ - 0, - { 0 } -}, - -{ /* AArch64_FMULXv1i16_indexed, AArch64_INS_FMULX: fmulx */ - 0, - { 0 } -}, - -{ /* AArch64_FMULXv1i32_indexed, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULXv1i64_indexed, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULXv2f32, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULXv2f64, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULXv2i32_indexed, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULXv2i64_indexed, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULXv4f16, AArch64_INS_FMULX: fmulx */ - 0, - { 0 } -}, - -{ /* AArch64_FMULXv4f32, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULXv4i16_indexed, AArch64_INS_FMULX: fmulx */ - 0, - { 0 } -}, - -{ /* AArch64_FMULXv4i32_indexed, AArch64_INS_FMULX: fmulx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULXv8f16, AArch64_INS_FMULX: fmulx */ - 0, - { 0 } -}, - -{ /* AArch64_FMULXv8i16_indexed, AArch64_INS_FMULX: fmulx */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZPmI_D, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZPmI_H, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZPmI_S, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZPmZ_D, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZPmZ_H, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZPmZ_S, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZZZI_D, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZZZI_H, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZZZI_S, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZZZ_D, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZZZ_H, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMUL_ZZZ_S, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMULv1i16_indexed, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMULv1i32_indexed, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULv1i64_indexed, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULv2f32, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULv2f64, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULv2i32_indexed, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULv2i64_indexed, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULv4f16, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMULv4f32, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FMULv4i16_indexed, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMULv4i32_indexed, AArch64_INS_FMUL: fmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FMULv8f16, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FMULv8i16_indexed, AArch64_INS_FMUL: fmul */ - 0, - { 0 } -}, - -{ /* AArch64_FNEGDr, AArch64_INS_FNEG: fneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FNEGHr, AArch64_INS_FNEG: fneg */ - 0, - { 0 } -}, - -{ /* AArch64_FNEGSr, AArch64_INS_FNEG: fneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FNEG_ZPmZ_D, AArch64_INS_FNEG: fneg */ - 0, - { 0 } -}, - -{ /* AArch64_FNEG_ZPmZ_H, AArch64_INS_FNEG: fneg */ - 0, - { 0 } -}, - -{ /* AArch64_FNEG_ZPmZ_S, AArch64_INS_FNEG: fneg */ - 0, - { 0 } -}, - -{ /* AArch64_FNEGv2f32, AArch64_INS_FNEG: fneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FNEGv2f64, AArch64_INS_FNEG: fneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FNEGv4f16, AArch64_INS_FNEG: fneg */ - 0, - { 0 } -}, - -{ /* AArch64_FNEGv4f32, AArch64_INS_FNEG: fneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FNEGv8f16, AArch64_INS_FNEG: fneg */ - 0, - { 0 } -}, - -{ /* AArch64_FNMADDDrrr, AArch64_INS_FNMADD: fnmadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FNMADDHrrr, AArch64_INS_FNMADD: fnmadd */ - 0, - { 0 } -}, - -{ /* AArch64_FNMADDSrrr, AArch64_INS_FNMADD: fnmadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FNMAD_ZPmZZ_D, AArch64_INS_FNMAD: fnmad */ - 0, - { 0 } -}, - -{ /* AArch64_FNMAD_ZPmZZ_H, AArch64_INS_FNMAD: fnmad */ - 0, - { 0 } -}, - -{ /* AArch64_FNMAD_ZPmZZ_S, AArch64_INS_FNMAD: fnmad */ - 0, - { 0 } -}, - -{ /* AArch64_FNMLA_ZPmZZ_D, AArch64_INS_FNMLA: fnmla */ - 0, - { 0 } -}, - -{ /* AArch64_FNMLA_ZPmZZ_H, AArch64_INS_FNMLA: fnmla */ - 0, - { 0 } -}, - -{ /* AArch64_FNMLA_ZPmZZ_S, AArch64_INS_FNMLA: fnmla */ - 0, - { 0 } -}, - -{ /* AArch64_FNMLS_ZPmZZ_D, AArch64_INS_FNMLS: fnmls */ - 0, - { 0 } -}, - -{ /* AArch64_FNMLS_ZPmZZ_H, AArch64_INS_FNMLS: fnmls */ - 0, - { 0 } -}, - -{ /* AArch64_FNMLS_ZPmZZ_S, AArch64_INS_FNMLS: fnmls */ - 0, - { 0 } -}, - -{ /* AArch64_FNMSB_ZPmZZ_D, AArch64_INS_FNMSB: fnmsb */ - 0, - { 0 } -}, - -{ /* AArch64_FNMSB_ZPmZZ_H, AArch64_INS_FNMSB: fnmsb */ - 0, - { 0 } -}, - -{ /* AArch64_FNMSB_ZPmZZ_S, AArch64_INS_FNMSB: fnmsb */ - 0, - { 0 } -}, - -{ /* AArch64_FNMSUBDrrr, AArch64_INS_FNMSUB: fnmsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FNMSUBHrrr, AArch64_INS_FNMSUB: fnmsub */ - 0, - { 0 } -}, - -{ /* AArch64_FNMSUBSrrr, AArch64_INS_FNMSUB: fnmsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_FNMULDrr, AArch64_INS_FNMUL: fnmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FNMULHrr, AArch64_INS_FNMUL: fnmul */ - 0, - { 0 } -}, - -{ /* AArch64_FNMULSrr, AArch64_INS_FNMUL: fnmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPE_ZZ_D, AArch64_INS_FRECPE: frecpe */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPE_ZZ_H, AArch64_INS_FRECPE: frecpe */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPE_ZZ_S, AArch64_INS_FRECPE: frecpe */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPEv1f16, AArch64_INS_FRECPE: frecpe */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPEv1i32, AArch64_INS_FRECPE: frecpe */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPEv1i64, AArch64_INS_FRECPE: frecpe */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPEv2f32, AArch64_INS_FRECPE: frecpe */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPEv2f64, AArch64_INS_FRECPE: frecpe */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPEv4f16, AArch64_INS_FRECPE: frecpe */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPEv4f32, AArch64_INS_FRECPE: frecpe */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPEv8f16, AArch64_INS_FRECPE: frecpe */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPS16, AArch64_INS_FRECPS: frecps */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPS32, AArch64_INS_FRECPS: frecps */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPS64, AArch64_INS_FRECPS: frecps */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPS_ZZZ_D, AArch64_INS_FRECPS: frecps */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPS_ZZZ_H, AArch64_INS_FRECPS: frecps */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPS_ZZZ_S, AArch64_INS_FRECPS: frecps */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPSv2f32, AArch64_INS_FRECPS: frecps */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPSv2f64, AArch64_INS_FRECPS: frecps */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPSv4f16, AArch64_INS_FRECPS: frecps */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPSv4f32, AArch64_INS_FRECPS: frecps */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPSv8f16, AArch64_INS_FRECPS: frecps */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPX_ZPmZ_D, AArch64_INS_FRECPX: frecpx */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPX_ZPmZ_H, AArch64_INS_FRECPX: frecpx */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPX_ZPmZ_S, AArch64_INS_FRECPX: frecpx */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPXv1f16, AArch64_INS_FRECPX: frecpx */ - 0, - { 0 } -}, - -{ /* AArch64_FRECPXv1i32, AArch64_INS_FRECPX: frecpx */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRECPXv1i64, AArch64_INS_FRECPX: frecpx */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTADr, AArch64_INS_FRINTA: frinta */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTAHr, AArch64_INS_FRINTA: frinta */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTASr, AArch64_INS_FRINTA: frinta */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTA_ZPmZ_D, AArch64_INS_FRINTA: frinta */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTA_ZPmZ_H, AArch64_INS_FRINTA: frinta */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTA_ZPmZ_S, AArch64_INS_FRINTA: frinta */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTAv2f32, AArch64_INS_FRINTA: frinta */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTAv2f64, AArch64_INS_FRINTA: frinta */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTAv4f16, AArch64_INS_FRINTA: frinta */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTAv4f32, AArch64_INS_FRINTA: frinta */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTAv8f16, AArch64_INS_FRINTA: frinta */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTIDr, AArch64_INS_FRINTI: frinti */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTIHr, AArch64_INS_FRINTI: frinti */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTISr, AArch64_INS_FRINTI: frinti */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTI_ZPmZ_D, AArch64_INS_FRINTI: frinti */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTI_ZPmZ_H, AArch64_INS_FRINTI: frinti */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTI_ZPmZ_S, AArch64_INS_FRINTI: frinti */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTIv2f32, AArch64_INS_FRINTI: frinti */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTIv2f64, AArch64_INS_FRINTI: frinti */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTIv4f16, AArch64_INS_FRINTI: frinti */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTIv4f32, AArch64_INS_FRINTI: frinti */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTIv8f16, AArch64_INS_FRINTI: frinti */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTMDr, AArch64_INS_FRINTM: frintm */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTMHr, AArch64_INS_FRINTM: frintm */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTMSr, AArch64_INS_FRINTM: frintm */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTM_ZPmZ_D, AArch64_INS_FRINTM: frintm */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTM_ZPmZ_H, AArch64_INS_FRINTM: frintm */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTM_ZPmZ_S, AArch64_INS_FRINTM: frintm */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTMv2f32, AArch64_INS_FRINTM: frintm */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTMv2f64, AArch64_INS_FRINTM: frintm */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTMv4f16, AArch64_INS_FRINTM: frintm */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTMv4f32, AArch64_INS_FRINTM: frintm */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTMv8f16, AArch64_INS_FRINTM: frintm */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTNDr, AArch64_INS_FRINTN: frintn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTNHr, AArch64_INS_FRINTN: frintn */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTNSr, AArch64_INS_FRINTN: frintn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTN_ZPmZ_D, AArch64_INS_FRINTN: frintn */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTN_ZPmZ_H, AArch64_INS_FRINTN: frintn */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTN_ZPmZ_S, AArch64_INS_FRINTN: frintn */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTNv2f32, AArch64_INS_FRINTN: frintn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTNv2f64, AArch64_INS_FRINTN: frintn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTNv4f16, AArch64_INS_FRINTN: frintn */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTNv4f32, AArch64_INS_FRINTN: frintn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTNv8f16, AArch64_INS_FRINTN: frintn */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTPDr, AArch64_INS_FRINTP: frintp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTPHr, AArch64_INS_FRINTP: frintp */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTPSr, AArch64_INS_FRINTP: frintp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTP_ZPmZ_D, AArch64_INS_FRINTP: frintp */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTP_ZPmZ_H, AArch64_INS_FRINTP: frintp */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTP_ZPmZ_S, AArch64_INS_FRINTP: frintp */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTPv2f32, AArch64_INS_FRINTP: frintp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTPv2f64, AArch64_INS_FRINTP: frintp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTPv4f16, AArch64_INS_FRINTP: frintp */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTPv4f32, AArch64_INS_FRINTP: frintp */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTPv8f16, AArch64_INS_FRINTP: frintp */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTXDr, AArch64_INS_FRINTX: frintx */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTXHr, AArch64_INS_FRINTX: frintx */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTXSr, AArch64_INS_FRINTX: frintx */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTX_ZPmZ_D, AArch64_INS_FRINTX: frintx */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTX_ZPmZ_H, AArch64_INS_FRINTX: frintx */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTX_ZPmZ_S, AArch64_INS_FRINTX: frintx */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTXv2f32, AArch64_INS_FRINTX: frintx */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTXv2f64, AArch64_INS_FRINTX: frintx */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTXv4f16, AArch64_INS_FRINTX: frintx */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTXv4f32, AArch64_INS_FRINTX: frintx */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTXv8f16, AArch64_INS_FRINTX: frintx */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTZDr, AArch64_INS_FRINTZ: frintz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTZHr, AArch64_INS_FRINTZ: frintz */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTZSr, AArch64_INS_FRINTZ: frintz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTZ_ZPmZ_D, AArch64_INS_FRINTZ: frintz */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTZ_ZPmZ_H, AArch64_INS_FRINTZ: frintz */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTZ_ZPmZ_S, AArch64_INS_FRINTZ: frintz */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTZv2f32, AArch64_INS_FRINTZ: frintz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTZv2f64, AArch64_INS_FRINTZ: frintz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTZv4f16, AArch64_INS_FRINTZ: frintz */ - 0, - { 0 } -}, - -{ /* AArch64_FRINTZv4f32, AArch64_INS_FRINTZ: frintz */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRINTZv8f16, AArch64_INS_FRINTZ: frintz */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTE_ZZ_D, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTE_ZZ_H, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTE_ZZ_S, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTEv1f16, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTEv1i32, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTEv1i64, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTEv2f32, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTEv2f64, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTEv4f16, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTEv4f32, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTEv8f16, AArch64_INS_FRSQRTE: frsqrte */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTS16, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTS32, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTS64, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTS_ZZZ_D, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTS_ZZZ_H, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTS_ZZZ_S, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTSv2f32, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTSv2f64, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTSv4f16, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { 0 } -}, - -{ /* AArch64_FRSQRTSv4f32, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FRSQRTSv8f16, AArch64_INS_FRSQRTS: frsqrts */ - 0, - { 0 } -}, - -{ /* AArch64_FSCALE_ZPmZ_D, AArch64_INS_FSCALE: fscale */ - 0, - { 0 } -}, - -{ /* AArch64_FSCALE_ZPmZ_H, AArch64_INS_FSCALE: fscale */ - 0, - { 0 } -}, - -{ /* AArch64_FSCALE_ZPmZ_S, AArch64_INS_FSCALE: fscale */ - 0, - { 0 } -}, - -{ /* AArch64_FSQRTDr, AArch64_INS_FSQRT: fsqrt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSQRTHr, AArch64_INS_FSQRT: fsqrt */ - 0, - { 0 } -}, - -{ /* AArch64_FSQRTSr, AArch64_INS_FSQRT: fsqrt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSQRT_ZPmZ_D, AArch64_INS_FSQRT: fsqrt */ - 0, - { 0 } -}, - -{ /* AArch64_FSQRT_ZPmZ_H, AArch64_INS_FSQRT: fsqrt */ - 0, - { 0 } -}, - -{ /* AArch64_FSQRT_ZPmZ_S, AArch64_INS_FSQRT: fsqrt */ - 0, - { 0 } -}, - -{ /* AArch64_FSQRTv2f32, AArch64_INS_FSQRT: fsqrt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSQRTv2f64, AArch64_INS_FSQRT: fsqrt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSQRTv4f16, AArch64_INS_FSQRT: fsqrt */ - 0, - { 0 } -}, - -{ /* AArch64_FSQRTv4f32, AArch64_INS_FSQRT: fsqrt */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSQRTv8f16, AArch64_INS_FSQRT: fsqrt */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBDrr, AArch64_INS_FSUB: fsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSUBHrr, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBR_ZPmI_D, AArch64_INS_FSUBR: fsubr */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBR_ZPmI_H, AArch64_INS_FSUBR: fsubr */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBR_ZPmI_S, AArch64_INS_FSUBR: fsubr */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBR_ZPmZ_D, AArch64_INS_FSUBR: fsubr */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBR_ZPmZ_H, AArch64_INS_FSUBR: fsubr */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBR_ZPmZ_S, AArch64_INS_FSUBR: fsubr */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBSrr, AArch64_INS_FSUB: fsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSUB_ZPmI_D, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUB_ZPmI_H, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUB_ZPmI_S, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUB_ZPmZ_D, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUB_ZPmZ_H, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUB_ZPmZ_S, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUB_ZZZ_D, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUB_ZZZ_H, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUB_ZZZ_S, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBv2f32, AArch64_INS_FSUB: fsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSUBv2f64, AArch64_INS_FSUB: fsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSUBv4f16, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FSUBv4f32, AArch64_INS_FSUB: fsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_FSUBv8f16, AArch64_INS_FSUB: fsub */ - 0, - { 0 } -}, - -{ /* AArch64_FTMAD_ZZI_D, AArch64_INS_FTMAD: ftmad */ - 0, - { 0 } -}, - -{ /* AArch64_FTMAD_ZZI_H, AArch64_INS_FTMAD: ftmad */ - 0, - { 0 } -}, - -{ /* AArch64_FTMAD_ZZI_S, AArch64_INS_FTMAD: ftmad */ - 0, - { 0 } -}, - -{ /* AArch64_FTSMUL_ZZZ_D, AArch64_INS_FTSMUL: ftsmul */ - 0, - { 0 } -}, - -{ /* AArch64_FTSMUL_ZZZ_H, AArch64_INS_FTSMUL: ftsmul */ - 0, - { 0 } -}, - -{ /* AArch64_FTSMUL_ZZZ_S, AArch64_INS_FTSMUL: ftsmul */ - 0, - { 0 } -}, - -{ /* AArch64_FTSSEL_ZZZ_D, AArch64_INS_FTSSEL: ftssel */ - 0, - { 0 } -}, - -{ /* AArch64_FTSSEL_ZZZ_H, AArch64_INS_FTSSEL: ftssel */ - 0, - { 0 } -}, - -{ /* AArch64_FTSSEL_ZZZ_S, AArch64_INS_FTSSEL: ftssel */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1B_D_IMM_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1B_D_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1B_D_SXTW_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1B_D_UXTW_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1B_S_IMM_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1B_S_SXTW_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1B_S_UXTW_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1D_IMM_REAL, AArch64_INS_LD1D: ld1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1D_REAL, AArch64_INS_LD1D: ld1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1D_SCALED_REAL, AArch64_INS_LD1D: ld1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1D_SXTW_REAL, AArch64_INS_LD1D: ld1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1D_SXTW_SCALED_REAL, AArch64_INS_LD1D: ld1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1D_UXTW_REAL, AArch64_INS_LD1D: ld1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1D_UXTW_SCALED_REAL, AArch64_INS_LD1D: ld1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_D_IMM_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_D_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_D_SCALED_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_D_SXTW_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_D_SXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_D_UXTW_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_D_UXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_S_IMM_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_S_SXTW_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_S_SXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_S_UXTW_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1H_S_UXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SB_D_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SB_D_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SB_D_SXTW_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SB_D_UXTW_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SB_S_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SB_S_SXTW_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SB_S_UXTW_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_D_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_D_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_D_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_D_SXTW_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_D_SXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_D_UXTW_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_D_UXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_S_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_S_SXTW_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_S_SXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_S_UXTW_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SH_S_UXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SW_D_IMM_REAL, AArch64_INS_LD1SW: ld1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SW_D_REAL, AArch64_INS_LD1SW: ld1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SW_D_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SW_D_SXTW_REAL, AArch64_INS_LD1SW: ld1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SW_D_SXTW_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SW_D_UXTW_REAL, AArch64_INS_LD1SW: ld1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1SW_D_UXTW_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_D_IMM_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_D_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_D_SCALED_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_D_SXTW_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_D_SXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_D_UXTW_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_D_UXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_IMM_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_SXTW_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_SXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_UXTW_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLD1W_UXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1B_D_IMM_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1B_D_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1B_D_SXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1B_D_UXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1B_S_IMM_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1B_S_SXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1B_S_UXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1D_IMM_REAL, AArch64_INS_LDFF1D: ldff1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1D_REAL, AArch64_INS_LDFF1D: ldff1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1D_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1D_SXTW_REAL, AArch64_INS_LDFF1D: ldff1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1D_SXTW_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1D_UXTW_REAL, AArch64_INS_LDFF1D: ldff1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1D_UXTW_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_D_IMM_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_D_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_D_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_D_SXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_D_UXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_S_IMM_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_S_SXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_S_SXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_S_UXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1H_S_UXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SB_D_IMM_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SB_D_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SB_D_SXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SB_D_UXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SB_S_IMM_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SB_S_SXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SB_S_UXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_D_IMM_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_D_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_D_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_D_SXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_D_UXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_S_IMM_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_S_SXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_S_SXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_S_UXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SH_S_UXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SW_D_IMM_REAL, AArch64_INS_LDFF1SW: ldff1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SW_D_REAL, AArch64_INS_LDFF1SW: ldff1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SW_D_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SW_D_SXTW_REAL, AArch64_INS_LDFF1SW: ldff1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SW_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SW_D_UXTW_REAL, AArch64_INS_LDFF1SW: ldff1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1SW_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_D_IMM_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_D_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_D_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_D_SXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_D_UXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_IMM_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_SXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_SXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_UXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_GLDFF1W_UXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_HINT, AArch64_INS_CSDB: csdb */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_HLT, AArch64_INS_HLT: hlt */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_HVC, AArch64_INS_HVC: hvc */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_INCB_XPiI, AArch64_INS_INCB: incb */ - 0, - { 0 } -}, - -{ /* AArch64_INCD_XPiI, AArch64_INS_INCD: incd */ - 0, - { 0 } -}, - -{ /* AArch64_INCD_ZPiI, AArch64_INS_INCD: incd */ - 0, - { 0 } -}, - -{ /* AArch64_INCH_XPiI, AArch64_INS_INCH: inch */ - 0, - { 0 } -}, - -{ /* AArch64_INCH_ZPiI, AArch64_INS_INCH: inch */ - 0, - { 0 } -}, - -{ /* AArch64_INCP_XP_B, AArch64_INS_INCP: incp */ - 0, - { 0 } -}, - -{ /* AArch64_INCP_XP_D, AArch64_INS_INCP: incp */ - 0, - { 0 } -}, - -{ /* AArch64_INCP_XP_H, AArch64_INS_INCP: incp */ - 0, - { 0 } -}, - -{ /* AArch64_INCP_XP_S, AArch64_INS_INCP: incp */ - 0, - { 0 } -}, - -{ /* AArch64_INCP_ZP_D, AArch64_INS_INCP: incp */ - 0, - { 0 } -}, - -{ /* AArch64_INCP_ZP_H, AArch64_INS_INCP: incp */ - 0, - { 0 } -}, - -{ /* AArch64_INCP_ZP_S, AArch64_INS_INCP: incp */ - 0, - { 0 } -}, - -{ /* AArch64_INCW_XPiI, AArch64_INS_INCW: incw */ - 0, - { 0 } -}, - -{ /* AArch64_INCW_ZPiI, AArch64_INS_INCW: incw */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_II_B, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_II_D, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_II_H, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_II_S, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_IR_B, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_IR_D, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_IR_H, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_IR_S, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_RI_B, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_RI_D, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_RI_H, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_RI_S, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_RR_B, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_RR_D, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_RR_H, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INDEX_RR_S, AArch64_INS_INDEX: index */ - 0, - { 0 } -}, - -{ /* AArch64_INSR_ZR_B, AArch64_INS_INSR: insr */ - 0, - { 0 } -}, - -{ /* AArch64_INSR_ZR_D, AArch64_INS_INSR: insr */ - 0, - { 0 } -}, - -{ /* AArch64_INSR_ZR_H, AArch64_INS_INSR: insr */ - 0, - { 0 } -}, - -{ /* AArch64_INSR_ZR_S, AArch64_INS_INSR: insr */ - 0, - { 0 } -}, - -{ /* AArch64_INSR_ZV_B, AArch64_INS_INSR: insr */ - 0, - { 0 } -}, - -{ /* AArch64_INSR_ZV_D, AArch64_INS_INSR: insr */ - 0, - { 0 } -}, - -{ /* AArch64_INSR_ZV_H, AArch64_INS_INSR: insr */ - 0, - { 0 } -}, - -{ /* AArch64_INSR_ZV_S, AArch64_INS_INSR: insr */ - 0, - { 0 } -}, - -{ /* AArch64_INSvi16gpr, AArch64_INS_INS: ins */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_INSvi16lane, AArch64_INS_INS: ins */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_INSvi32gpr, AArch64_INS_INS: ins */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_INSvi32lane, AArch64_INS_INS: ins */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_INSvi64gpr, AArch64_INS_INS: ins */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_INSvi64lane, AArch64_INS_INS: ins */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_INSvi8gpr, AArch64_INS_INS: ins */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_INSvi8lane, AArch64_INS_INS: ins */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_ISB, AArch64_INS_ISB: isb */ - 0, - { 0 } -}, - -{ /* AArch64_LASTA_RPZ_B, AArch64_INS_LASTA: lasta */ - 0, - { 0 } -}, - -{ /* AArch64_LASTA_RPZ_D, AArch64_INS_LASTA: lasta */ - 0, - { 0 } -}, - -{ /* AArch64_LASTA_RPZ_H, AArch64_INS_LASTA: lasta */ - 0, - { 0 } -}, - -{ /* AArch64_LASTA_RPZ_S, AArch64_INS_LASTA: lasta */ - 0, - { 0 } -}, - -{ /* AArch64_LASTA_VPZ_B, AArch64_INS_LASTA: lasta */ - 0, - { 0 } -}, - -{ /* AArch64_LASTA_VPZ_D, AArch64_INS_LASTA: lasta */ - 0, - { 0 } -}, - -{ /* AArch64_LASTA_VPZ_H, AArch64_INS_LASTA: lasta */ - 0, - { 0 } -}, - -{ /* AArch64_LASTA_VPZ_S, AArch64_INS_LASTA: lasta */ - 0, - { 0 } -}, - -{ /* AArch64_LASTB_RPZ_B, AArch64_INS_LASTB: lastb */ - 0, - { 0 } -}, - -{ /* AArch64_LASTB_RPZ_D, AArch64_INS_LASTB: lastb */ - 0, - { 0 } -}, - -{ /* AArch64_LASTB_RPZ_H, AArch64_INS_LASTB: lastb */ - 0, - { 0 } -}, - -{ /* AArch64_LASTB_RPZ_S, AArch64_INS_LASTB: lastb */ - 0, - { 0 } -}, - -{ /* AArch64_LASTB_VPZ_B, AArch64_INS_LASTB: lastb */ - 0, - { 0 } -}, - -{ /* AArch64_LASTB_VPZ_D, AArch64_INS_LASTB: lastb */ - 0, - { 0 } -}, - -{ /* AArch64_LASTB_VPZ_H, AArch64_INS_LASTB: lastb */ - 0, - { 0 } -}, - -{ /* AArch64_LASTB_VPZ_S, AArch64_INS_LASTB: lastb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1B, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_LD1B_D, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_LD1B_D_IMM_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_LD1B_H, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_LD1B_H_IMM_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_LD1B_IMM_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_LD1B_S, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_LD1B_S_IMM_REAL, AArch64_INS_LD1B: ld1b */ - 0, - { 0 } -}, - -{ /* AArch64_LD1D, AArch64_INS_LD1D: ld1d */ - 0, - { 0 } -}, - -{ /* AArch64_LD1D_IMM_REAL, AArch64_INS_LD1D: ld1d */ - 0, - { 0 } -}, - -{ /* AArch64_LD1Fourv16b, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv16b_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv1d, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv1d_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv2d, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv2d_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv2s, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv2s_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv4h, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv4h_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv4s, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv4s_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv8b, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv8b_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv8h, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Fourv8h_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1H, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_LD1H_D, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_LD1H_D_IMM_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_LD1H_IMM_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_LD1H_S, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_LD1H_S_IMM_REAL, AArch64_INS_LD1H: ld1h */ - 0, - { 0 } -}, - -{ /* AArch64_LD1Onev16b, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev16b_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev1d, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev1d_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev2d, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev2d_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LD1Onev2s, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev2s_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev4h, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev4h_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev4s, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev4s_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev8b, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev8b_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev8h, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Onev8h_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1RB_D_IMM, AArch64_INS_LD1RB: ld1rb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RB_H_IMM, AArch64_INS_LD1RB: ld1rb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RB_IMM, AArch64_INS_LD1RB: ld1rb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RB_S_IMM, AArch64_INS_LD1RB: ld1rb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RD_IMM, AArch64_INS_LD1RD: ld1rd */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RH_D_IMM, AArch64_INS_LD1RH: ld1rh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RH_IMM, AArch64_INS_LD1RH: ld1rh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RH_S_IMM, AArch64_INS_LD1RH: ld1rh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RQ_B, AArch64_INS_LD1RQB: ld1rqb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RQ_B_IMM, AArch64_INS_LD1RQB: ld1rqb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RQ_D, AArch64_INS_LD1RQD: ld1rqd */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RQ_D_IMM, AArch64_INS_LD1RQD: ld1rqd */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RQ_H, AArch64_INS_LD1RQH: ld1rqh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RQ_H_IMM, AArch64_INS_LD1RQH: ld1rqh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RQ_W, AArch64_INS_LD1RQW: ld1rqw */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RQ_W_IMM, AArch64_INS_LD1RQW: ld1rqw */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RSB_D_IMM, AArch64_INS_LD1RSB: ld1rsb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RSB_H_IMM, AArch64_INS_LD1RSB: ld1rsb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RSB_S_IMM, AArch64_INS_LD1RSB: ld1rsb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RSH_D_IMM, AArch64_INS_LD1RSH: ld1rsh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RSH_S_IMM, AArch64_INS_LD1RSH: ld1rsh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RSW_IMM, AArch64_INS_LD1RSW: ld1rsw */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RW_D_IMM, AArch64_INS_LD1RW: ld1rw */ - 0, - { 0 } -}, - -{ /* AArch64_LD1RW_IMM, AArch64_INS_LD1RW: ld1rw */ - 0, - { 0 } -}, - -{ /* AArch64_LD1Rv16b, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv16b_POST, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv1d, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv1d_POST, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv2d, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv2d_POST, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv2s, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv2s_POST, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv4h, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv4h_POST, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv4s, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv4s_POST, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv8b, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv8b_POST, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv8h, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Rv8h_POST, AArch64_INS_LD1R: ld1r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1SB_D, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SB_D_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SB_H, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SB_H_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SB_S, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SB_S_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SH_D, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SH_D_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SH_S, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SH_S_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SW_D, AArch64_INS_LD1SW: ld1sw */ - 0, - { 0 } -}, - -{ /* AArch64_LD1SW_D_IMM_REAL, AArch64_INS_LD1SW: ld1sw */ - 0, - { 0 } -}, - -{ /* AArch64_LD1Threev16b, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev16b_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev1d, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev1d_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev2d, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev2d_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev2s, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev2s_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev4h, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev4h_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev4s, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev4s_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev8b, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev8b_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev8h, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Threev8h_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov16b, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov16b_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov1d, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov1d_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov2d, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov2d_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov2s, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov2s_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov4h, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov4h_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov4s, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov4s_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov8b, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov8b_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov8h, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1Twov8h_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1W, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_LD1W_D, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_LD1W_D_IMM_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_LD1W_IMM_REAL, AArch64_INS_LD1W: ld1w */ - 0, - { 0 } -}, - -{ /* AArch64_LD1i16, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1i16_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1i32, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1i32_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1i64, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1i64_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1i8, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD1i8_POST, AArch64_INS_LD1: ld1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2B, AArch64_INS_LD2B: ld2b */ - 0, - { 0 } -}, - -{ /* AArch64_LD2B_IMM, AArch64_INS_LD2B: ld2b */ - 0, - { 0 } -}, - -{ /* AArch64_LD2D, AArch64_INS_LD2D: ld2d */ - 0, - { 0 } -}, - -{ /* AArch64_LD2D_IMM, AArch64_INS_LD2D: ld2d */ - 0, - { 0 } -}, - -{ /* AArch64_LD2H, AArch64_INS_LD2H: ld2h */ - 0, - { 0 } -}, - -{ /* AArch64_LD2H_IMM, AArch64_INS_LD2H: ld2h */ - 0, - { 0 } -}, - -{ /* AArch64_LD2Rv16b, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv16b_POST, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv1d, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv1d_POST, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv2d, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv2d_POST, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv2s, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv2s_POST, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv4h, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv4h_POST, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv4s, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv4s_POST, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv8b, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv8b_POST, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv8h, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Rv8h_POST, AArch64_INS_LD2R: ld2r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD2Twov16b, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov16b_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov2d, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov2d_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov2s, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov2s_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov4h, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov4h_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov4s, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov4s_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov8b, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov8b_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov8h, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2Twov8h_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2W, AArch64_INS_LD2W: ld2w */ - 0, - { 0 } -}, - -{ /* AArch64_LD2W_IMM, AArch64_INS_LD2W: ld2w */ - 0, - { 0 } -}, - -{ /* AArch64_LD2i16, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2i16_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2i32, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2i32_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2i64, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2i64_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD2i8, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} -}, - -{ /* AArch64_LD2i8_POST, AArch64_INS_LD2: ld2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LD3B, AArch64_INS_LD3B: ld3b */ - 0, - { 0 } -}, - -{ /* AArch64_LD3B_IMM, AArch64_INS_LD3B: ld3b */ - 0, - { 0 } -}, - -{ /* AArch64_LD3D, AArch64_INS_LD3D: ld3d */ - 0, - { 0 } -}, - -{ /* AArch64_LD3D_IMM, AArch64_INS_LD3D: ld3d */ - 0, - { 0 } -}, - -{ /* AArch64_LD3H, AArch64_INS_LD3H: ld3h */ - 0, - { 0 } -}, - -{ /* AArch64_LD3H_IMM, AArch64_INS_LD3H: ld3h */ - 0, - { 0 } -}, - -{ /* AArch64_LD3Rv16b, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv16b_POST, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv1d, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv1d_POST, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv2d, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv2d_POST, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv2s, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv2s_POST, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv4h, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv4h_POST, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv4s, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv4s_POST, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv8b, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv8b_POST, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv8h, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Rv8h_POST, AArch64_INS_LD3R: ld3r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev16b, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev16b_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev2d, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev2d_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev2s, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev2s_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev4h, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev4h_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev4s, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev4s_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev8b, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev8b_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev8h, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3Threev8h_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3W, AArch64_INS_LD3W: ld3w */ - 0, - { 0 } -}, - -{ /* AArch64_LD3W_IMM, AArch64_INS_LD3W: ld3w */ - 0, - { 0 } -}, - -{ /* AArch64_LD3i16, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3i16_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LD3i32, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3i32_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LD3i64, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3i64_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LD3i8, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD3i8_POST, AArch64_INS_LD3: ld3 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LD4B, AArch64_INS_LD4B: ld4b */ - 0, - { 0 } -}, - -{ /* AArch64_LD4B_IMM, AArch64_INS_LD4B: ld4b */ - 0, - { 0 } -}, - -{ /* AArch64_LD4D, AArch64_INS_LD4D: ld4d */ - 0, - { 0 } -}, - -{ /* AArch64_LD4D_IMM, AArch64_INS_LD4D: ld4d */ - 0, - { 0 } -}, - -{ /* AArch64_LD4Fourv16b, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv16b_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv2d, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv2d_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv2s, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv2s_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv4h, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv4h_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv4s, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv4s_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv8b, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv8b_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv8h, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Fourv8h_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4H, AArch64_INS_LD4H: ld4h */ - 0, - { 0 } -}, - -{ /* AArch64_LD4H_IMM, AArch64_INS_LD4H: ld4h */ - 0, - { 0 } -}, - -{ /* AArch64_LD4Rv16b, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv16b_POST, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv1d, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv1d_POST, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv2d, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv2d_POST, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv2s, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv2s_POST, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv4h, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv4h_POST, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv4s, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv4s_POST, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv8b, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv8b_POST, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv8h, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4Rv8h_POST, AArch64_INS_LD4R: ld4r */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4W, AArch64_INS_LD4W: ld4w */ - 0, - { 0 } -}, - -{ /* AArch64_LD4W_IMM, AArch64_INS_LD4W: ld4w */ - 0, - { 0 } -}, - -{ /* AArch64_LD4i16, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4i16_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LD4i32, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4i32_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LD4i64, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4i64_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LD4i8, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_LD4i8_POST, AArch64_INS_LD4: ld4 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDADDAB, AArch64_INS_LDADDAB: ldaddab */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDAH, AArch64_INS_LDADDAH: ldaddah */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDALB, AArch64_INS_LDADDALB: ldaddalb */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDALH, AArch64_INS_LDADDALH: ldaddalh */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDALW, AArch64_INS_LDADDAL: ldaddal */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDALX, AArch64_INS_LDADDAL: ldaddal */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDAW, AArch64_INS_LDADDA: ldadda */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDAX, AArch64_INS_LDADDA: ldadda */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDB, AArch64_INS_LDADDB: ldaddb */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDH, AArch64_INS_LDADDH: ldaddh */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDLB, AArch64_INS_LDADDLB: ldaddlb */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDLH, AArch64_INS_LDADDLH: ldaddlh */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDLW, AArch64_INS_LDADDL: ldaddl */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDLX, AArch64_INS_LDADDL: ldaddl */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDW, AArch64_INS_LDADD: ldadd */ - 0, - { 0 } -}, - -{ /* AArch64_LDADDX, AArch64_INS_LDADD: ldadd */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPRB, AArch64_INS_LDAPRB: ldaprb */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPRH, AArch64_INS_LDAPRH: ldaprh */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPRW, AArch64_INS_LDAPR: ldapr */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPRX, AArch64_INS_LDAPR: ldapr */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPURBi, AArch64_INS_LDAPURB: ldapurb */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPURHi, AArch64_INS_LDAPURH: ldapurh */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPURSBWi, AArch64_INS_LDAPURSB: ldapursb */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPURSBXi, AArch64_INS_LDAPURSB: ldapursb */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPURSHWi, AArch64_INS_LDAPURSH: ldapursh */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPURSHXi, AArch64_INS_LDAPURSH: ldapursh */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPURSWi, AArch64_INS_LDAPURSW: ldapursw */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPURXi, AArch64_INS_LDAPUR: ldapur */ - 0, - { 0 } -}, - -{ /* AArch64_LDAPURi, AArch64_INS_LDAPUR: ldapur */ - 0, - { 0 } -}, - -{ /* AArch64_LDARB, AArch64_INS_LDARB: ldarb */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDARH, AArch64_INS_LDARH: ldarh */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDARW, AArch64_INS_LDAR: ldar */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDARX, AArch64_INS_LDAR: ldar */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDAXPW, AArch64_INS_LDAXP: ldaxp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDAXPX, AArch64_INS_LDAXP: ldaxp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDAXRB, AArch64_INS_LDAXRB: ldaxrb */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDAXRH, AArch64_INS_LDAXRH: ldaxrh */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDAXRW, AArch64_INS_LDAXR: ldaxr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDAXRX, AArch64_INS_LDAXR: ldaxr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDCLRAB, AArch64_INS_LDCLRAB: ldclrab */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRAH, AArch64_INS_LDCLRAH: ldclrah */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRALB, AArch64_INS_LDCLRALB: ldclralb */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRALH, AArch64_INS_LDCLRALH: ldclralh */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRALW, AArch64_INS_LDCLRAL: ldclral */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRALX, AArch64_INS_LDCLRAL: ldclral */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRAW, AArch64_INS_LDCLRA: ldclra */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRAX, AArch64_INS_LDCLRA: ldclra */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRB, AArch64_INS_LDCLRB: ldclrb */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRH, AArch64_INS_LDCLRH: ldclrh */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRLB, AArch64_INS_LDCLRLB: ldclrlb */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRLH, AArch64_INS_LDCLRLH: ldclrlh */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRLW, AArch64_INS_LDCLRL: ldclrl */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRLX, AArch64_INS_LDCLRL: ldclrl */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRW, AArch64_INS_LDCLR: ldclr */ - 0, - { 0 } -}, - -{ /* AArch64_LDCLRX, AArch64_INS_LDCLR: ldclr */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORAB, AArch64_INS_LDEORAB: ldeorab */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORAH, AArch64_INS_LDEORAH: ldeorah */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORALB, AArch64_INS_LDEORALB: ldeoralb */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORALH, AArch64_INS_LDEORALH: ldeoralh */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORALW, AArch64_INS_LDEORAL: ldeoral */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORALX, AArch64_INS_LDEORAL: ldeoral */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORAW, AArch64_INS_LDEORA: ldeora */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORAX, AArch64_INS_LDEORA: ldeora */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORB, AArch64_INS_LDEORB: ldeorb */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORH, AArch64_INS_LDEORH: ldeorh */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORLB, AArch64_INS_LDEORLB: ldeorlb */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORLH, AArch64_INS_LDEORLH: ldeorlh */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORLW, AArch64_INS_LDEORL: ldeorl */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORLX, AArch64_INS_LDEORL: ldeorl */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORW, AArch64_INS_LDEOR: ldeor */ - 0, - { 0 } -}, - -{ /* AArch64_LDEORX, AArch64_INS_LDEOR: ldeor */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1B_D_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1B_H_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1B_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1B_S_REAL, AArch64_INS_LDFF1B: ldff1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1D_REAL, AArch64_INS_LDFF1D: ldff1d */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1H_D_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1H_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1H_S_REAL, AArch64_INS_LDFF1H: ldff1h */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1SB_D_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1SB_H_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1SB_S_REAL, AArch64_INS_LDFF1SB: ldff1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1SH_D_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1SH_S_REAL, AArch64_INS_LDFF1SH: ldff1sh */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1SW_D_REAL, AArch64_INS_LDFF1SW: ldff1sw */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1W_D_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_LDFF1W_REAL, AArch64_INS_LDFF1W: ldff1w */ - 0, - { 0 } -}, - -{ /* AArch64_LDLARB, AArch64_INS_LDLARB: ldlarb */ - 0, - { 0 } -}, - -{ /* AArch64_LDLARH, AArch64_INS_LDLARH: ldlarh */ - 0, - { 0 } -}, - -{ /* AArch64_LDLARW, AArch64_INS_LDLAR: ldlar */ - 0, - { 0 } -}, - -{ /* AArch64_LDLARX, AArch64_INS_LDLAR: ldlar */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1B_D_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1B_H_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1B_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1B_S_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1D_IMM_REAL, AArch64_INS_LDNF1D: ldnf1d */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1H_D_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1H_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1H_S_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1SB_D_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1SB_H_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1SB_S_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1SH_D_IMM_REAL, AArch64_INS_LDNF1SH: ldnf1sh */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1SH_S_IMM_REAL, AArch64_INS_LDNF1SH: ldnf1sh */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1SW_D_IMM_REAL, AArch64_INS_LDNF1SW: ldnf1sw */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1W_D_IMM_REAL, AArch64_INS_LDNF1W: ldnf1w */ - 0, - { 0 } -}, - -{ /* AArch64_LDNF1W_IMM_REAL, AArch64_INS_LDNF1W: ldnf1w */ - 0, - { 0 } -}, - -{ /* AArch64_LDNPDi, AArch64_INS_LDNP: ldnp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDNPQi, AArch64_INS_LDNP: ldnp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDNPSi, AArch64_INS_LDNP: ldnp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDNPWi, AArch64_INS_LDNP: ldnp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDNPXi, AArch64_INS_LDNP: ldnp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDNT1B_ZRI, AArch64_INS_LDNT1B: ldnt1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDNT1B_ZRR, AArch64_INS_LDNT1B: ldnt1b */ - 0, - { 0 } -}, - -{ /* AArch64_LDNT1D_ZRI, AArch64_INS_LDNT1D: ldnt1d */ - 0, - { 0 } -}, - -{ /* AArch64_LDNT1D_ZRR, AArch64_INS_LDNT1D: ldnt1d */ - 0, - { 0 } -}, - -{ /* AArch64_LDNT1H_ZRI, AArch64_INS_LDNT1H: ldnt1h */ - 0, - { 0 } -}, - -{ /* AArch64_LDNT1H_ZRR, AArch64_INS_LDNT1H: ldnt1h */ - 0, - { 0 } -}, - -{ /* AArch64_LDNT1W_ZRI, AArch64_INS_LDNT1W: ldnt1w */ - 0, - { 0 } -}, - -{ /* AArch64_LDNT1W_ZRR, AArch64_INS_LDNT1W: ldnt1w */ - 0, - { 0 } -}, - -{ /* AArch64_LDPDi, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPDpost, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPDpre, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPQi, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPQpost, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPQpre, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPSWi, AArch64_INS_LDPSW: ldpsw */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPSWpost, AArch64_INS_LDPSW: ldpsw */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPSWpre, AArch64_INS_LDPSW: ldpsw */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPSi, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPSpost, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPSpre, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPWi, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPWpost, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPWpre, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPXi, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPXpost, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDPXpre, AArch64_INS_LDP: ldp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRAAindexed, AArch64_INS_LDRAA: ldraa */ - 0, - { 0 } -}, - -{ /* AArch64_LDRAAwriteback, AArch64_INS_LDRAA: ldraa */ - 0, - { 0 } -}, - -{ /* AArch64_LDRABindexed, AArch64_INS_LDRAB: ldrab */ - 0, - { 0 } -}, - -{ /* AArch64_LDRABwriteback, AArch64_INS_LDRAB: ldrab */ - 0, - { 0 } -}, - -{ /* AArch64_LDRBBpost, AArch64_INS_LDRB: ldrb */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRBBpre, AArch64_INS_LDRB: ldrb */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRBBroW, AArch64_INS_LDRB: ldrb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRBBroX, AArch64_INS_LDRB: ldrb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRBBui, AArch64_INS_LDRB: ldrb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRBpost, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRBpre, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRBroW, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRBroX, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRBui, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRDl, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRDpost, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRDpre, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRDroW, AArch64_INS_LDR: ldr */ - 00, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRDroX, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRDui, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRHHpost, AArch64_INS_LDRH: ldrh */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRHHpre, AArch64_INS_LDRH: ldrh */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRHHroW, AArch64_INS_LDRH: ldrh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRHHroX, AArch64_INS_LDRH: ldrh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRHHui, AArch64_INS_LDRH: ldrh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRHpost, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRHpre, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRHroW, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRHroX, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRHui, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRQl, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRQpost, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRQpre, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRQroW, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRQroX, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRQui, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSBWpost, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSBWpre, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSBWroW, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSBWroX, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSBWui, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSBXpost, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSBXpre, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSBXroW, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSBXroX, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSBXui, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSHWpost, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSHWpre, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSHWroW, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSHWroX, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSHWui, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSHXpost, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSHXpre, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSHXroW, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSHXroX, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSHXui, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSWl, AArch64_INS_LDRSW: ldrsw */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSWpost, AArch64_INS_LDRSW: ldrsw */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSWpre, AArch64_INS_LDRSW: ldrsw */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSWroW, AArch64_INS_LDRSW: ldrsw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSWroX, AArch64_INS_LDRSW: ldrsw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSWui, AArch64_INS_LDRSW: ldrsw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSl, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSpost, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSpre, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRSroW, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSroX, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRSui, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRWl, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRWpost, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRWpre, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRWroW, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRWroX, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRWui, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRXl, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRXpost, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRXpre, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDRXroW, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRXroX, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_LDRXui, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDR_PXI, AArch64_INS_LDR: ldr */ - 0, - { 0 } -}, - -{ /* AArch64_LDR_ZXI, AArch64_INS_LDR: ldr */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETAB, AArch64_INS_LDSETAB: ldsetab */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETAH, AArch64_INS_LDSETAH: ldsetah */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETALB, AArch64_INS_LDSETALB: ldsetalb */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETALH, AArch64_INS_LDSETALH: ldsetalh */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETALW, AArch64_INS_LDSETAL: ldsetal */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETALX, AArch64_INS_LDSETAL: ldsetal */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETAW, AArch64_INS_LDSETA: ldseta */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETAX, AArch64_INS_LDSETA: ldseta */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETB, AArch64_INS_LDSETB: ldsetb */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETH, AArch64_INS_LDSETH: ldseth */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETLB, AArch64_INS_LDSETLB: ldsetlb */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETLH, AArch64_INS_LDSETLH: ldsetlh */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETLW, AArch64_INS_LDSETL: ldsetl */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETLX, AArch64_INS_LDSETL: ldsetl */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETW, AArch64_INS_LDSET: ldset */ - 0, - { 0 } -}, - -{ /* AArch64_LDSETX, AArch64_INS_LDSET: ldset */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXAB, AArch64_INS_LDSMAXAB: ldsmaxab */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXAH, AArch64_INS_LDSMAXAH: ldsmaxah */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXALB, AArch64_INS_LDSMAXALB: ldsmaxalb */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXALH, AArch64_INS_LDSMAXALH: ldsmaxalh */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXALW, AArch64_INS_LDSMAXAL: ldsmaxal */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXALX, AArch64_INS_LDSMAXAL: ldsmaxal */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXAW, AArch64_INS_LDSMAXA: ldsmaxa */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXAX, AArch64_INS_LDSMAXA: ldsmaxa */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXB, AArch64_INS_LDSMAXB: ldsmaxb */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXH, AArch64_INS_LDSMAXH: ldsmaxh */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXLB, AArch64_INS_LDSMAXLB: ldsmaxlb */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXLH, AArch64_INS_LDSMAXLH: ldsmaxlh */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXLW, AArch64_INS_LDSMAXL: ldsmaxl */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXLX, AArch64_INS_LDSMAXL: ldsmaxl */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXW, AArch64_INS_LDSMAX: ldsmax */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMAXX, AArch64_INS_LDSMAX: ldsmax */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINAB, AArch64_INS_LDSMINAB: ldsminab */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINAH, AArch64_INS_LDSMINAH: ldsminah */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINALB, AArch64_INS_LDSMINALB: ldsminalb */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINALH, AArch64_INS_LDSMINALH: ldsminalh */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINALW, AArch64_INS_LDSMINAL: ldsminal */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINALX, AArch64_INS_LDSMINAL: ldsminal */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINAW, AArch64_INS_LDSMINA: ldsmina */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINAX, AArch64_INS_LDSMINA: ldsmina */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINB, AArch64_INS_LDSMINB: ldsminb */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINH, AArch64_INS_LDSMINH: ldsminh */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINLB, AArch64_INS_LDSMINLB: ldsminlb */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINLH, AArch64_INS_LDSMINLH: ldsminlh */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINLW, AArch64_INS_LDSMINL: ldsminl */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINLX, AArch64_INS_LDSMINL: ldsminl */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINW, AArch64_INS_LDSMIN: ldsmin */ - 0, - { 0 } -}, - -{ /* AArch64_LDSMINX, AArch64_INS_LDSMIN: ldsmin */ - 0, - { 0 } -}, - -{ /* AArch64_LDTRBi, AArch64_INS_LDTRB: ldtrb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDTRHi, AArch64_INS_LDTRH: ldtrh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDTRSBWi, AArch64_INS_LDTRSB: ldtrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDTRSBXi, AArch64_INS_LDTRSB: ldtrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDTRSHWi, AArch64_INS_LDTRSH: ldtrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDTRSHXi, AArch64_INS_LDTRSH: ldtrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDTRSWi, AArch64_INS_LDTRSW: ldtrsw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDTRWi, AArch64_INS_LDTR: ldtr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDTRXi, AArch64_INS_LDTR: ldtr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDUMAXAB, AArch64_INS_LDUMAXAB: ldumaxab */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXAH, AArch64_INS_LDUMAXAH: ldumaxah */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXALB, AArch64_INS_LDUMAXALB: ldumaxalb */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXALH, AArch64_INS_LDUMAXALH: ldumaxalh */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXALW, AArch64_INS_LDUMAXAL: ldumaxal */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXALX, AArch64_INS_LDUMAXAL: ldumaxal */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXAW, AArch64_INS_LDUMAXA: ldumaxa */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXAX, AArch64_INS_LDUMAXA: ldumaxa */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXB, AArch64_INS_LDUMAXB: ldumaxb */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXH, AArch64_INS_LDUMAXH: ldumaxh */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXLB, AArch64_INS_LDUMAXLB: ldumaxlb */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXLH, AArch64_INS_LDUMAXLH: ldumaxlh */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXLW, AArch64_INS_LDUMAXL: ldumaxl */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXLX, AArch64_INS_LDUMAXL: ldumaxl */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXW, AArch64_INS_LDUMAX: ldumax */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMAXX, AArch64_INS_LDUMAX: ldumax */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINAB, AArch64_INS_LDUMINAB: lduminab */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINAH, AArch64_INS_LDUMINAH: lduminah */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINALB, AArch64_INS_LDUMINALB: lduminalb */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINALH, AArch64_INS_LDUMINALH: lduminalh */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINALW, AArch64_INS_LDUMINAL: lduminal */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINALX, AArch64_INS_LDUMINAL: lduminal */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINAW, AArch64_INS_LDUMINA: ldumina */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINAX, AArch64_INS_LDUMINA: ldumina */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINB, AArch64_INS_LDUMINB: lduminb */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINH, AArch64_INS_LDUMINH: lduminh */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINLB, AArch64_INS_LDUMINLB: lduminlb */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINLH, AArch64_INS_LDUMINLH: lduminlh */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINLW, AArch64_INS_LDUMINL: lduminl */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINLX, AArch64_INS_LDUMINL: lduminl */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINW, AArch64_INS_LDUMIN: ldumin */ - 0, - { 0 } -}, - -{ /* AArch64_LDUMINX, AArch64_INS_LDUMIN: ldumin */ - 0, - { 0 } -}, - -{ /* AArch64_LDURBBi, AArch64_INS_LDRB: ldrb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURBi, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURDi, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURHHi, AArch64_INS_LDRH: ldrh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURHi, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURQi, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURSBWi, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURSBXi, AArch64_INS_LDRSB: ldrsb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURSHWi, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURSHXi, AArch64_INS_LDRSH: ldrsh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURSWi, AArch64_INS_LDRSW: ldrsw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURSi, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURWi, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDURXi, AArch64_INS_LDR: ldr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_LDXPW, AArch64_INS_LDXP: ldxp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDXPX, AArch64_INS_LDXP: ldxp */ - 0, - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDXRB, AArch64_INS_LDXRB: ldxrb */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDXRH, AArch64_INS_LDXRH: ldxrh */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDXRW, AArch64_INS_LDXR: ldxr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LDXRX, AArch64_INS_LDXR: ldxr */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_LSLR_ZPmZ_B, AArch64_INS_LSLR: lslr */ - 0, - { 0 } -}, - -{ /* AArch64_LSLR_ZPmZ_D, AArch64_INS_LSLR: lslr */ - 0, - { 0 } -}, - -{ /* AArch64_LSLR_ZPmZ_H, AArch64_INS_LSLR: lslr */ - 0, - { 0 } -}, - -{ /* AArch64_LSLR_ZPmZ_S, AArch64_INS_LSLR: lslr */ - 0, - { 0 } -}, - -{ /* AArch64_LSLVWr, AArch64_INS_LSL: lsl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LSLVXr, AArch64_INS_LSL: lsl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LSL_WIDE_ZPmZ_B, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_WIDE_ZPmZ_H, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_WIDE_ZPmZ_S, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_WIDE_ZZZ_B, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_WIDE_ZZZ_H, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_WIDE_ZZZ_S, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZPmI_B, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZPmI_D, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZPmI_H, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZPmI_S, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZPmZ_B, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZPmZ_D, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZPmZ_H, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZPmZ_S, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZZI_B, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZZI_D, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZZI_H, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSL_ZZI_S, AArch64_INS_LSL: lsl */ - 0, - { 0 } -}, - -{ /* AArch64_LSRR_ZPmZ_B, AArch64_INS_LSRR: lsrr */ - 0, - { 0 } -}, - -{ /* AArch64_LSRR_ZPmZ_D, AArch64_INS_LSRR: lsrr */ - 0, - { 0 } -}, - -{ /* AArch64_LSRR_ZPmZ_H, AArch64_INS_LSRR: lsrr */ - 0, - { 0 } -}, - -{ /* AArch64_LSRR_ZPmZ_S, AArch64_INS_LSRR: lsrr */ - 0, - { 0 } -}, - -{ /* AArch64_LSRVWr, AArch64_INS_LSR: lsr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LSRVXr, AArch64_INS_LSR: lsr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_LSR_WIDE_ZPmZ_B, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_WIDE_ZPmZ_H, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_WIDE_ZPmZ_S, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_WIDE_ZZZ_B, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_WIDE_ZZZ_H, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_WIDE_ZZZ_S, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZPmI_B, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZPmI_D, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZPmI_H, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZPmI_S, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZPmZ_B, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZPmZ_D, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZPmZ_H, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZPmZ_S, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZZI_B, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZZI_D, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZZI_H, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_LSR_ZZI_S, AArch64_INS_LSR: lsr */ - 0, - { 0 } -}, - -{ /* AArch64_MADDWrrr, AArch64_INS_MADD: madd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MADDXrrr, AArch64_INS_MADD: madd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MAD_ZPmZZ_B, AArch64_INS_MAD: mad */ - 0, - { 0 } -}, - -{ /* AArch64_MAD_ZPmZZ_D, AArch64_INS_MAD: mad */ - 0, - { 0 } -}, - -{ /* AArch64_MAD_ZPmZZ_H, AArch64_INS_MAD: mad */ - 0, - { 0 } -}, - -{ /* AArch64_MAD_ZPmZZ_S, AArch64_INS_MAD: mad */ - 0, - { 0 } -}, - -{ /* AArch64_MLA_ZPmZZ_B, AArch64_INS_MLA: mla */ - 0, - { 0 } -}, - -{ /* AArch64_MLA_ZPmZZ_D, AArch64_INS_MLA: mla */ - 0, - { 0 } -}, - -{ /* AArch64_MLA_ZPmZZ_H, AArch64_INS_MLA: mla */ - 0, - { 0 } -}, - -{ /* AArch64_MLA_ZPmZZ_S, AArch64_INS_MLA: mla */ - 0, - { 0 } -}, - -{ /* AArch64_MLAv16i8, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLAv2i32, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLAv2i32_indexed, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MLAv4i16, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLAv4i16_indexed, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MLAv4i32, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLAv4i32_indexed, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MLAv8i16, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLAv8i16_indexed, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MLAv8i8, AArch64_INS_MLA: mla */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLS_ZPmZZ_B, AArch64_INS_MLS: mls */ - 0, - { 0 } -}, - -{ /* AArch64_MLS_ZPmZZ_D, AArch64_INS_MLS: mls */ - 0, - { 0 } -}, - -{ /* AArch64_MLS_ZPmZZ_H, AArch64_INS_MLS: mls */ - 0, - { 0 } -}, - -{ /* AArch64_MLS_ZPmZZ_S, AArch64_INS_MLS: mls */ - 0, - { 0 } -}, - -{ /* AArch64_MLSv16i8, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLSv2i32, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLSv2i32_indexed, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MLSv4i16, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLSv4i16_indexed, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MLSv4i32, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLSv4i32_indexed, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MLSv8i16, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MLSv8i16_indexed, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MLSv8i8, AArch64_INS_MLS: mls */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVID, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVIv16b_ns, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVIv2d_ns, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVIv2i32, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVIv2s_msl, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVIv4i16, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVIv4i32, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVIv4s_msl, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVIv8b_ns, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVIv8i16, AArch64_INS_MOVI: movi */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVKWi, AArch64_INS_MOVK: movk */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVKXi, AArch64_INS_MOVK: movk */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVNWi, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVNXi, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVPRFX_ZPmZ_B, AArch64_INS_MOVPRFX: movprfx */ - 0, - { 0 } -}, - -{ /* AArch64_MOVPRFX_ZPmZ_D, AArch64_INS_MOVPRFX: movprfx */ - 0, - { 0 } -}, - -{ /* AArch64_MOVPRFX_ZPmZ_H, AArch64_INS_MOVPRFX: movprfx */ - 0, - { 0 } -}, - -{ /* AArch64_MOVPRFX_ZPmZ_S, AArch64_INS_MOVPRFX: movprfx */ - 0, - { 0 } -}, - -{ /* AArch64_MOVPRFX_ZPzZ_B, AArch64_INS_MOVPRFX: movprfx */ - 0, - { 0 } -}, - -{ /* AArch64_MOVPRFX_ZPzZ_D, AArch64_INS_MOVPRFX: movprfx */ - 0, - { 0 } -}, - -{ /* AArch64_MOVPRFX_ZPzZ_H, AArch64_INS_MOVPRFX: movprfx */ - 0, - { 0 } -}, - -{ /* AArch64_MOVPRFX_ZPzZ_S, AArch64_INS_MOVPRFX: movprfx */ - 0, - { 0 } -}, - -{ /* AArch64_MOVPRFX_ZZ, AArch64_INS_MOVPRFX: movprfx */ - 0, - { 0 } -}, - -{ /* AArch64_MOVZWi, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MOVZXi, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MRS, AArch64_INS_MRS: mrs */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_MSB_ZPmZZ_B, AArch64_INS_MSB: msb */ - 0, - { 0 } -}, - -{ /* AArch64_MSB_ZPmZZ_D, AArch64_INS_MSB: msb */ - 0, - { 0 } -}, - -{ /* AArch64_MSB_ZPmZZ_H, AArch64_INS_MSB: msb */ - 0, - { 0 } -}, - -{ /* AArch64_MSB_ZPmZZ_S, AArch64_INS_MSB: msb */ - 0, - { 0 } -}, - -{ /* AArch64_MSR, AArch64_INS_MSR: msr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_MSRpstateImm1, AArch64_INS_MSR: msr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MSRpstateImm4, AArch64_INS_MSR: msr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MSUBWrrr, AArch64_INS_MNEG: mneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MSUBXrrr, AArch64_INS_MNEG: mneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MUL_ZI_B, AArch64_INS_MUL: mul */ - 0, - { 0 } -}, - -{ /* AArch64_MUL_ZI_D, AArch64_INS_MUL: mul */ - 0, - { 0 } -}, - -{ /* AArch64_MUL_ZI_H, AArch64_INS_MUL: mul */ - 0, - { 0 } -}, - -{ /* AArch64_MUL_ZI_S, AArch64_INS_MUL: mul */ - 0, - { 0 } -}, - -{ /* AArch64_MUL_ZPmZ_B, AArch64_INS_MUL: mul */ - 0, - { 0 } -}, - -{ /* AArch64_MUL_ZPmZ_D, AArch64_INS_MUL: mul */ - 0, - { 0 } -}, - -{ /* AArch64_MUL_ZPmZ_H, AArch64_INS_MUL: mul */ - 0, - { 0 } -}, - -{ /* AArch64_MUL_ZPmZ_S, AArch64_INS_MUL: mul */ - 0, - { 0 } -}, - -{ /* AArch64_MULv16i8, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MULv2i32, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MULv2i32_indexed, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MULv4i16, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MULv4i16_indexed, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_MULv4i32, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MULv4i32_indexed, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MULv8i16, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MULv8i16_indexed, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MULv8i8, AArch64_INS_MUL: mul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MVNIv2i32, AArch64_INS_MVNI: mvni */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MVNIv2s_msl, AArch64_INS_MVNI: mvni */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MVNIv4i16, AArch64_INS_MVNI: mvni */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MVNIv4i32, AArch64_INS_MVNI: mvni */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MVNIv4s_msl, AArch64_INS_MVNI: mvni */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_MVNIv8i16, AArch64_INS_MVNI: mvni */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_NANDS_PPzPP, AArch64_INS_NANDS: nands */ - 0, - { 0 } -}, - -{ /* AArch64_NAND_PPzPP, AArch64_INS_NAND: nand */ - 0, - { 0 } -}, - -{ /* AArch64_NEG_ZPmZ_B, AArch64_INS_NEG: neg */ - 0, - { 0 } -}, - -{ /* AArch64_NEG_ZPmZ_D, AArch64_INS_NEG: neg */ - 0, - { 0 } -}, - -{ /* AArch64_NEG_ZPmZ_H, AArch64_INS_NEG: neg */ - 0, - { 0 } -}, - -{ /* AArch64_NEG_ZPmZ_S, AArch64_INS_NEG: neg */ - 0, - { 0 } -}, - -{ /* AArch64_NEGv16i8, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_NEGv1i64, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_NEGv2i32, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_NEGv2i64, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_NEGv4i16, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_NEGv4i32, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_NEGv8i16, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_NEGv8i8, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_NORS_PPzPP, AArch64_INS_NORS: nors */ - 0, - { 0 } -}, - -{ /* AArch64_NOR_PPzPP, AArch64_INS_NOR: nor */ - 0, - { 0 } -}, - -{ /* AArch64_NOT_ZPmZ_B, AArch64_INS_NOT: not */ - 0, - { 0 } -}, - -{ /* AArch64_NOT_ZPmZ_D, AArch64_INS_NOT: not */ - 0, - { 0 } -}, - -{ /* AArch64_NOT_ZPmZ_H, AArch64_INS_NOT: not */ - 0, - { 0 } -}, - -{ /* AArch64_NOT_ZPmZ_S, AArch64_INS_NOT: not */ - 0, - { 0 } -}, - -{ /* AArch64_NOTv16i8, AArch64_INS_MVN: mvn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_NOTv8i8, AArch64_INS_MVN: mvn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORNS_PPzPP, AArch64_INS_ORNS: orns */ - 0, - { 0 } -}, - -{ /* AArch64_ORNWrs, AArch64_INS_MVN: mvn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORNXrs, AArch64_INS_MVN: mvn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORN_PPzPP, AArch64_INS_ORN: orn */ - 0, - { 0 } -}, - -{ /* AArch64_ORNv16i8, AArch64_INS_ORN: orn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORNv8i8, AArch64_INS_ORN: orn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORRS_PPzPP, AArch64_INS_MOVS: movs */ - 0, - { 0 } -}, - -{ /* AArch64_ORRWri, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORRWrs, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORRXri, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORRXrs, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORR_PPzPP, AArch64_INS_MOV: mov */ - 0, - { 0 } -}, - -{ /* AArch64_ORR_ZI, AArch64_INS_ORN: orn */ - 0, - { 0 } -}, - -{ /* AArch64_ORR_ZPmZ_B, AArch64_INS_ORR: orr */ - 0, - { 0 } -}, - -{ /* AArch64_ORR_ZPmZ_D, AArch64_INS_ORR: orr */ - 0, - { 0 } -}, - -{ /* AArch64_ORR_ZPmZ_H, AArch64_INS_ORR: orr */ - 0, - { 0 } -}, - -{ /* AArch64_ORR_ZPmZ_S, AArch64_INS_ORR: orr */ - 0, - { 0 } -}, - -{ /* AArch64_ORR_ZZZ, AArch64_INS_MOV: mov */ - 0, - { 0 } -}, - -{ /* AArch64_ORRv16i8, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORRv2i32, AArch64_INS_ORR: orr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORRv4i16, AArch64_INS_ORR: orr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORRv4i32, AArch64_INS_ORR: orr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORRv8i16, AArch64_INS_ORR: orr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORRv8i8, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ORV_VPZ_B, AArch64_INS_ORV: orv */ - 0, - { 0 } -}, - -{ /* AArch64_ORV_VPZ_D, AArch64_INS_ORV: orv */ - 0, - { 0 } -}, - -{ /* AArch64_ORV_VPZ_H, AArch64_INS_ORV: orv */ - 0, - { 0 } -}, - -{ /* AArch64_ORV_VPZ_S, AArch64_INS_ORV: orv */ - 0, - { 0 } -}, - -{ /* AArch64_PACDA, AArch64_INS_PACDA: pacda */ - 0, - { 0 } -}, - -{ /* AArch64_PACDB, AArch64_INS_PACDB: pacdb */ - 0, - { 0 } -}, - -{ /* AArch64_PACDZA, AArch64_INS_PACDZA: pacdza */ - 0, - { 0 } -}, - -{ /* AArch64_PACDZB, AArch64_INS_PACDZB: pacdzb */ - 0, - { 0 } -}, - -{ /* AArch64_PACGA, AArch64_INS_PACGA: pacga */ - 0, - { 0 } -}, - -{ /* AArch64_PACIA, AArch64_INS_PACIA: pacia */ - 0, - { 0 } -}, - -{ /* AArch64_PACIA1716, AArch64_INS_PACIA1716: pacia1716 */ - 0, - { 0 } -}, - -{ /* AArch64_PACIASP, AArch64_INS_PACIASP: paciasp */ - 0, - { 0 } -}, - -{ /* AArch64_PACIAZ, AArch64_INS_PACIAZ: paciaz */ - 0, - { 0 } -}, - -{ /* AArch64_PACIB, AArch64_INS_PACIB: pacib */ - 0, - { 0 } -}, - -{ /* AArch64_PACIB1716, AArch64_INS_PACIB1716: pacib1716 */ - 0, - { 0 } -}, - -{ /* AArch64_PACIBSP, AArch64_INS_PACIBSP: pacibsp */ - 0, - { 0 } -}, - -{ /* AArch64_PACIBZ, AArch64_INS_PACIBZ: pacibz */ - 0, - { 0 } -}, - -{ /* AArch64_PACIZA, AArch64_INS_PACIZA: paciza */ - 0, - { 0 } -}, - -{ /* AArch64_PACIZB, AArch64_INS_PACIZB: pacizb */ - 0, - { 0 } -}, - -{ /* AArch64_PFALSE, AArch64_INS_PFALSE: pfalse */ - 0, - { 0 } -}, - -{ /* AArch64_PMULLv16i8, AArch64_INS_PMULL2: pmull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_PMULLv1i64, AArch64_INS_PMULL: pmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_PMULLv2i64, AArch64_INS_PMULL2: pmull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_PMULLv8i8, AArch64_INS_PMULL: pmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_PMULv16i8, AArch64_INS_PMUL: pmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_PMULv8i8, AArch64_INS_PMUL: pmul */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_PNEXT_B, AArch64_INS_PNEXT: pnext */ - 0, - { 0 } -}, - -{ /* AArch64_PNEXT_D, AArch64_INS_PNEXT: pnext */ - 0, - { 0 } -}, - -{ /* AArch64_PNEXT_H, AArch64_INS_PNEXT: pnext */ - 0, - { 0 } -}, - -{ /* AArch64_PNEXT_S, AArch64_INS_PNEXT: pnext */ - 0, - { 0 } -}, - -{ /* AArch64_PRFB_D_PZI, AArch64_INS_PRFB: prfb */ - 0, - { 0 } -}, - -{ /* AArch64_PRFB_D_SCALED, AArch64_INS_PRFB: prfb */ - 0, - { 0 } -}, - -{ /* AArch64_PRFB_D_SXTW_SCALED, AArch64_INS_PRFB: prfb */ - 0, - { 0 } -}, - -{ /* AArch64_PRFB_D_UXTW_SCALED, AArch64_INS_PRFB: prfb */ - 0, - { 0 } -}, - -{ /* AArch64_PRFB_PRI, AArch64_INS_PRFB: prfb */ - 0, - { 0 } -}, - -{ /* AArch64_PRFB_PRR, AArch64_INS_PRFB: prfb */ - 0, - { 0 } -}, - -{ /* AArch64_PRFB_S_PZI, AArch64_INS_PRFB: prfb */ - 0, - { 0 } -}, - -{ /* AArch64_PRFB_S_SXTW_SCALED, AArch64_INS_PRFB: prfb */ - 0, - { 0 } -}, - -{ /* AArch64_PRFB_S_UXTW_SCALED, AArch64_INS_PRFB: prfb */ - 0, - { 0 } -}, - -{ /* AArch64_PRFD_D_PZI, AArch64_INS_PRFD: prfd */ - 0, - { 0 } -}, - -{ /* AArch64_PRFD_D_SCALED, AArch64_INS_PRFD: prfd */ - 0, - { 0 } -}, - -{ /* AArch64_PRFD_D_SXTW_SCALED, AArch64_INS_PRFD: prfd */ - 0, - { 0 } -}, - -{ /* AArch64_PRFD_D_UXTW_SCALED, AArch64_INS_PRFD: prfd */ - 0, - { 0 } -}, - -{ /* AArch64_PRFD_PRI, AArch64_INS_PRFD: prfd */ - 0, - { 0 } -}, - -{ /* AArch64_PRFD_PRR, AArch64_INS_PRFD: prfd */ - 0, - { 0 } -}, - -{ /* AArch64_PRFD_S_PZI, AArch64_INS_PRFD: prfd */ - 0, - { 0 } -}, - -{ /* AArch64_PRFD_S_SXTW_SCALED, AArch64_INS_PRFD: prfd */ - 0, - { 0 } -}, - -{ /* AArch64_PRFD_S_UXTW_SCALED, AArch64_INS_PRFD: prfd */ - 0, - { 0 } -}, - -{ /* AArch64_PRFH_D_PZI, AArch64_INS_PRFH: prfh */ - 0, - { 0 } -}, - -{ /* AArch64_PRFH_D_SCALED, AArch64_INS_PRFH: prfh */ - 0, - { 0 } -}, - -{ /* AArch64_PRFH_D_SXTW_SCALED, AArch64_INS_PRFH: prfh */ - 0, - { 0 } -}, - -{ /* AArch64_PRFH_D_UXTW_SCALED, AArch64_INS_PRFH: prfh */ - 0, - { 0 } -}, - -{ /* AArch64_PRFH_PRI, AArch64_INS_PRFH: prfh */ - 0, - { 0 } -}, - -{ /* AArch64_PRFH_PRR, AArch64_INS_PRFH: prfh */ - 0, - { 0 } -}, - -{ /* AArch64_PRFH_S_PZI, AArch64_INS_PRFH: prfh */ - 0, - { 0 } -}, - -{ /* AArch64_PRFH_S_SXTW_SCALED, AArch64_INS_PRFH: prfh */ - 0, - { 0 } -}, - -{ /* AArch64_PRFH_S_UXTW_SCALED, AArch64_INS_PRFH: prfh */ - 0, - { 0 } -}, - -{ /* AArch64_PRFMl, AArch64_INS_PRFM: prfm */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_PRFMroW, AArch64_INS_PRFM: prfm */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_PRFMroX, AArch64_INS_PRFM: prfm */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_PRFMui, AArch64_INS_PRFM: prfm */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_PRFS_PRR, AArch64_INS_PRFW: prfw */ - 0, - { 0 } -}, - -{ /* AArch64_PRFUMi, AArch64_INS_PRFUM: prfum */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_PRFW_D_PZI, AArch64_INS_PRFW: prfw */ - 0, - { 0 } -}, - -{ /* AArch64_PRFW_D_SCALED, AArch64_INS_PRFW: prfw */ - 0, - { 0 } -}, - -{ /* AArch64_PRFW_D_SXTW_SCALED, AArch64_INS_PRFW: prfw */ - 0, - { 0 } -}, - -{ /* AArch64_PRFW_D_UXTW_SCALED, AArch64_INS_PRFW: prfw */ - 0, - { 0 } -}, - -{ /* AArch64_PRFW_PRI, AArch64_INS_PRFW: prfw */ - 0, - { 0 } -}, - -{ /* AArch64_PRFW_S_PZI, AArch64_INS_PRFW: prfw */ - 0, - { 0 } -}, - -{ /* AArch64_PRFW_S_SXTW_SCALED, AArch64_INS_PRFW: prfw */ - 0, - { 0 } -}, - -{ /* AArch64_PRFW_S_UXTW_SCALED, AArch64_INS_PRFW: prfw */ - 0, - { 0 } -}, - -{ /* AArch64_PTEST_PP, AArch64_INS_PTEST: ptest */ - 0, - { 0 } -}, - -{ /* AArch64_PTRUES_B, AArch64_INS_PTRUES: ptrues */ - 0, - { 0 } -}, - -{ /* AArch64_PTRUES_D, AArch64_INS_PTRUES: ptrues */ - 0, - { 0 } -}, - -{ /* AArch64_PTRUES_H, AArch64_INS_PTRUES: ptrues */ - 0, - { 0 } -}, - -{ /* AArch64_PTRUES_S, AArch64_INS_PTRUES: ptrues */ - 0, - { 0 } -}, - -{ /* AArch64_PTRUE_B, AArch64_INS_PTRUE: ptrue */ - 0, - { 0 } -}, - -{ /* AArch64_PTRUE_D, AArch64_INS_PTRUE: ptrue */ - 0, - { 0 } -}, - -{ /* AArch64_PTRUE_H, AArch64_INS_PTRUE: ptrue */ - 0, - { 0 } -}, - -{ /* AArch64_PTRUE_S, AArch64_INS_PTRUE: ptrue */ - 0, - { 0 } -}, - -{ /* AArch64_PUNPKHI_PP, AArch64_INS_PUNPKHI: punpkhi */ - 0, - { 0 } -}, - -{ /* AArch64_PUNPKLO_PP, AArch64_INS_PUNPKLO: punpklo */ - 0, - { 0 } -}, - -{ /* AArch64_RADDHNv2i64_v2i32, AArch64_INS_RADDHN: raddhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RADDHNv2i64_v4i32, AArch64_INS_RADDHN2: raddhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RADDHNv4i32_v4i16, AArch64_INS_RADDHN: raddhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RADDHNv4i32_v8i16, AArch64_INS_RADDHN2: raddhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RADDHNv8i16_v16i8, AArch64_INS_RADDHN2: raddhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RADDHNv8i16_v8i8, AArch64_INS_RADDHN: raddhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RAX1, AArch64_INS_RAX1: rax1 */ - 0, - { 0 } -}, - -{ /* AArch64_RBITWr, AArch64_INS_RBIT: rbit */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_RBITXr, AArch64_INS_RBIT: rbit */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_RBIT_ZPmZ_B, AArch64_INS_RBIT: rbit */ - 0, - { 0 } -}, - -{ /* AArch64_RBIT_ZPmZ_D, AArch64_INS_RBIT: rbit */ - 0, - { 0 } -}, - -{ /* AArch64_RBIT_ZPmZ_H, AArch64_INS_RBIT: rbit */ - 0, - { 0 } -}, - -{ /* AArch64_RBIT_ZPmZ_S, AArch64_INS_RBIT: rbit */ - 0, - { 0 } -}, - -{ /* AArch64_RBITv16i8, AArch64_INS_RBIT: rbit */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_RBITv8i8, AArch64_INS_RBIT: rbit */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_RDFFRS_PPz, AArch64_INS_RDFFRS: rdffrs */ - 0, - { 0 } -}, - -{ /* AArch64_RDFFR_P, AArch64_INS_RDFFR: rdffr */ - 0, - { 0 } -}, - -{ /* AArch64_RDFFR_PPz, AArch64_INS_RDFFR: rdffr */ - 0, - { 0 } -}, - -{ /* AArch64_RDVLI_XI, AArch64_INS_RDVL: rdvl */ - 0, - { 0 } -}, - -{ /* AArch64_RET, AArch64_INS_RET: ret */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_RETAA, AArch64_INS_RETAA: retaa */ - 0, - { 0 } -}, - -{ /* AArch64_RETAB, AArch64_INS_RETAB: retab */ - 0, - { 0 } -}, - -{ /* AArch64_REV16Wr, AArch64_INS_REV16: rev16 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV16Xr, AArch64_INS_REV16: rev16 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV16v16i8, AArch64_INS_REV16: rev16 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV16v8i8, AArch64_INS_REV16: rev16 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV32Xr, AArch64_INS_REV32: rev32 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV32v16i8, AArch64_INS_REV32: rev32 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV32v4i16, AArch64_INS_REV32: rev32 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV32v8i16, AArch64_INS_REV32: rev32 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV32v8i8, AArch64_INS_REV32: rev32 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV64v16i8, AArch64_INS_REV64: rev64 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV64v2i32, AArch64_INS_REV64: rev64 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV64v4i16, AArch64_INS_REV64: rev64 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV64v4i32, AArch64_INS_REV64: rev64 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV64v8i16, AArch64_INS_REV64: rev64 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV64v8i8, AArch64_INS_REV64: rev64 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REVB_ZPmZ_D, AArch64_INS_REVB: revb */ - 0, - { 0 } -}, - -{ /* AArch64_REVB_ZPmZ_H, AArch64_INS_REVB: revb */ - 0, - { 0 } -}, - -{ /* AArch64_REVB_ZPmZ_S, AArch64_INS_REVB: revb */ - 0, - { 0 } -}, - -{ /* AArch64_REVH_ZPmZ_D, AArch64_INS_REVH: revh */ - 0, - { 0 } -}, - -{ /* AArch64_REVH_ZPmZ_S, AArch64_INS_REVH: revh */ - 0, - { 0 } -}, - -{ /* AArch64_REVW_ZPmZ_D, AArch64_INS_REVW: revw */ - 0, - { 0 } -}, - -{ /* AArch64_REVWr, AArch64_INS_REV: rev */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REVXr, AArch64_INS_REV: rev */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_REV_PP_B, AArch64_INS_REV: rev */ - 0, - { 0 } -}, - -{ /* AArch64_REV_PP_D, AArch64_INS_REV: rev */ - 0, - { 0 } -}, - -{ /* AArch64_REV_PP_H, AArch64_INS_REV: rev */ - 0, - { 0 } -}, - -{ /* AArch64_REV_PP_S, AArch64_INS_REV: rev */ - 0, - { 0 } -}, - -{ /* AArch64_REV_ZZ_B, AArch64_INS_REV: rev */ - 0, - { 0 } -}, - -{ /* AArch64_REV_ZZ_D, AArch64_INS_REV: rev */ - 0, - { 0 } -}, - -{ /* AArch64_REV_ZZ_H, AArch64_INS_REV: rev */ - 0, - { 0 } -}, - -{ /* AArch64_REV_ZZ_S, AArch64_INS_REV: rev */ - 0, - { 0 } -}, - -{ /* AArch64_RMIF, AArch64_INS_RMIF: rmif */ - 0, - { 0 } -}, - -{ /* AArch64_RORVWr, AArch64_INS_ROR: ror */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RORVXr, AArch64_INS_ROR: ror */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSHRNv16i8_shift, AArch64_INS_RSHRN2: rshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSHRNv2i32_shift, AArch64_INS_RSHRN: rshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSHRNv4i16_shift, AArch64_INS_RSHRN: rshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSHRNv4i32_shift, AArch64_INS_RSHRN2: rshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSHRNv8i16_shift, AArch64_INS_RSHRN2: rshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSHRNv8i8_shift, AArch64_INS_RSHRN: rshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSUBHNv2i64_v2i32, AArch64_INS_RSUBHN: rsubhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSUBHNv2i64_v4i32, AArch64_INS_RSUBHN2: rsubhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSUBHNv4i32_v4i16, AArch64_INS_RSUBHN: rsubhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSUBHNv4i32_v8i16, AArch64_INS_RSUBHN2: rsubhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSUBHNv8i16_v16i8, AArch64_INS_RSUBHN2: rsubhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_RSUBHNv8i16_v8i8, AArch64_INS_RSUBHN: rsubhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABALv16i8_v8i16, AArch64_INS_SABAL2: sabal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABALv2i32_v2i64, AArch64_INS_SABAL: sabal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABALv4i16_v4i32, AArch64_INS_SABAL: sabal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABALv4i32_v2i64, AArch64_INS_SABAL2: sabal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABALv8i16_v4i32, AArch64_INS_SABAL2: sabal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABALv8i8_v8i16, AArch64_INS_SABAL: sabal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABAv16i8, AArch64_INS_SABA: saba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABAv2i32, AArch64_INS_SABA: saba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABAv4i16, AArch64_INS_SABA: saba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABAv4i32, AArch64_INS_SABA: saba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABAv8i16, AArch64_INS_SABA: saba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABAv8i8, AArch64_INS_SABA: saba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDLv16i8_v8i16, AArch64_INS_SABDL2: sabdl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDLv2i32_v2i64, AArch64_INS_SABDL: sabdl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDLv4i16_v4i32, AArch64_INS_SABDL: sabdl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDLv4i32_v2i64, AArch64_INS_SABDL2: sabdl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDLv8i16_v4i32, AArch64_INS_SABDL2: sabdl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDLv8i8_v8i16, AArch64_INS_SABDL: sabdl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABD_ZPmZ_B, AArch64_INS_SABD: sabd */ - 0, - { 0 } -}, - -{ /* AArch64_SABD_ZPmZ_D, AArch64_INS_SABD: sabd */ - 0, - { 0 } -}, - -{ /* AArch64_SABD_ZPmZ_H, AArch64_INS_SABD: sabd */ - 0, - { 0 } -}, - -{ /* AArch64_SABD_ZPmZ_S, AArch64_INS_SABD: sabd */ - 0, - { 0 } -}, - -{ /* AArch64_SABDv16i8, AArch64_INS_SABD: sabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDv2i32, AArch64_INS_SABD: sabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDv4i16, AArch64_INS_SABD: sabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDv4i32, AArch64_INS_SABD: sabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDv8i16, AArch64_INS_SABD: sabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SABDv8i8, AArch64_INS_SABD: sabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADALPv16i8_v8i16, AArch64_INS_SADALP: sadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADALPv2i32_v1i64, AArch64_INS_SADALP: sadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADALPv4i16_v2i32, AArch64_INS_SADALP: sadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADALPv4i32_v2i64, AArch64_INS_SADALP: sadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADALPv8i16_v4i32, AArch64_INS_SADALP: sadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADALPv8i8_v4i16, AArch64_INS_SADALP: sadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLPv16i8_v8i16, AArch64_INS_SADDLP: saddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLPv2i32_v1i64, AArch64_INS_SADDLP: saddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLPv4i16_v2i32, AArch64_INS_SADDLP: saddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLPv4i32_v2i64, AArch64_INS_SADDLP: saddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLPv8i16_v4i32, AArch64_INS_SADDLP: saddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLPv8i8_v4i16, AArch64_INS_SADDLP: saddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLVv16i8v, AArch64_INS_SADDLV: saddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLVv4i16v, AArch64_INS_SADDLV: saddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLVv4i32v, AArch64_INS_SADDLV: saddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLVv8i16v, AArch64_INS_SADDLV: saddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLVv8i8v, AArch64_INS_SADDLV: saddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLv16i8_v8i16, AArch64_INS_SADDL2: saddl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLv2i32_v2i64, AArch64_INS_SADDL: saddl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLv4i16_v4i32, AArch64_INS_SADDL: saddl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLv4i32_v2i64, AArch64_INS_SADDL2: saddl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLv8i16_v4i32, AArch64_INS_SADDL2: saddl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDLv8i8_v8i16, AArch64_INS_SADDL: saddl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDV_VPZ_B, AArch64_INS_SADDV: saddv */ - 0, - { 0 } -}, - -{ /* AArch64_SADDV_VPZ_H, AArch64_INS_SADDV: saddv */ - 0, - { 0 } -}, - -{ /* AArch64_SADDV_VPZ_S, AArch64_INS_SADDV: saddv */ - 0, - { 0 } -}, - -{ /* AArch64_SADDWv16i8_v8i16, AArch64_INS_SADDW2: saddw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDWv2i32_v2i64, AArch64_INS_SADDW: saddw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDWv4i16_v4i32, AArch64_INS_SADDW: saddw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDWv4i32_v2i64, AArch64_INS_SADDW2: saddw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDWv8i16_v4i32, AArch64_INS_SADDW2: saddw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SADDWv8i8_v8i16, AArch64_INS_SADDW: saddw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SBCSWr, AArch64_INS_NGCS: ngcs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SBCSXr, AArch64_INS_NGCS: ngcs */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SBCWr, AArch64_INS_NGC: ngc */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SBCXr, AArch64_INS_NGC: ngc */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SBFMWri, AArch64_INS_ASR: asr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SBFMXri, AArch64_INS_ASR: asr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SCVTFSWDri, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFSWHri, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFSWSri, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFSXDri, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFSXHri, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFSXSri, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFUWDri, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFUWHri, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFUWSri, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFUXDri, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFUXHri, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFUXSri, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTF_ZPmZ_DtoD, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTF_ZPmZ_DtoH, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTF_ZPmZ_DtoS, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTF_ZPmZ_HtoH, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTF_ZPmZ_StoD, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTF_ZPmZ_StoH, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTF_ZPmZ_StoS, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFd, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFh, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFs, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFv1i16, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFv1i32, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFv1i64, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFv2f32, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFv2f64, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFv2i32_shift, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFv2i64_shift, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFv4f16, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFv4f32, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFv4i16_shift, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFv4i32_shift, AArch64_INS_SCVTF: scvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SCVTFv8f16, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SCVTFv8i16_shift, AArch64_INS_SCVTF: scvtf */ - 0, - { 0 } -}, - -{ /* AArch64_SDIVR_ZPmZ_D, AArch64_INS_SDIVR: sdivr */ - 0, - { 0 } -}, - -{ /* AArch64_SDIVR_ZPmZ_S, AArch64_INS_SDIVR: sdivr */ - 0, - { 0 } -}, - -{ /* AArch64_SDIVWr, AArch64_INS_SDIV: sdiv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SDIVXr, AArch64_INS_SDIV: sdiv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SDIV_ZPmZ_D, AArch64_INS_SDIV: sdiv */ - 0, - { 0 } -}, - -{ /* AArch64_SDIV_ZPmZ_S, AArch64_INS_SDIV: sdiv */ - 0, - { 0 } -}, - -{ /* AArch64_SDOT_ZZZI_D, AArch64_INS_SDOT: sdot */ - 0, - { 0 } -}, - -{ /* AArch64_SDOT_ZZZI_S, AArch64_INS_SDOT: sdot */ - 0, - { 0 } -}, - -{ /* AArch64_SDOT_ZZZ_D, AArch64_INS_SDOT: sdot */ - 0, - { 0 } -}, - -{ /* AArch64_SDOT_ZZZ_S, AArch64_INS_SDOT: sdot */ - 0, - { 0 } -}, - -{ /* AArch64_SDOTlanev16i8, AArch64_INS_SDOT: sdot */ - 0, - { 0 } -}, - -{ /* AArch64_SDOTlanev8i8, AArch64_INS_SDOT: sdot */ - 0, - { 0 } -}, - -{ /* AArch64_SDOTv16i8, AArch64_INS_SDOT: sdot */ - 0, - { 0 } -}, - -{ /* AArch64_SDOTv8i8, AArch64_INS_SDOT: sdot */ - 0, - { 0 } -}, - -{ /* AArch64_SEL_PPPP, AArch64_INS_MOV: mov */ - 0, - { 0 } -}, - -{ /* AArch64_SEL_ZPZZ_B, AArch64_INS_MOV: mov */ - 0, - { 0 } -}, - -{ /* AArch64_SEL_ZPZZ_D, AArch64_INS_MOV: mov */ - 0, - { 0 } -}, - -{ /* AArch64_SEL_ZPZZ_H, AArch64_INS_MOV: mov */ - 0, - { 0 } -}, - -{ /* AArch64_SEL_ZPZZ_S, AArch64_INS_MOV: mov */ - 0, - { 0 } -}, - -{ /* AArch64_SETF16, AArch64_INS_SETF16: setf16 */ - 0, - { 0 } -}, - -{ /* AArch64_SETF8, AArch64_INS_SETF8: setf8 */ - 0, - { 0 } -}, - -{ /* AArch64_SETFFR, AArch64_INS_SETFFR: setffr */ - 0, - { 0 } -}, - -{ /* AArch64_SHA1Crrr, AArch64_INS_SHA1C: sha1c */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA1Hrr, AArch64_INS_SHA1H: sha1h */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA1Mrrr, AArch64_INS_SHA1M: sha1m */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA1Prrr, AArch64_INS_SHA1P: sha1p */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA1SU0rrr, AArch64_INS_SHA1SU0: sha1su0 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA1SU1rr, AArch64_INS_SHA1SU1: sha1su1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA256H2rrr, AArch64_INS_SHA256H2: sha256h2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA256Hrrr, AArch64_INS_SHA256H: sha256h */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA256SU0rr, AArch64_INS_SHA256SU0: sha256su0 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA256SU1rrr, AArch64_INS_SHA256SU1: sha256su1 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SHA512H, AArch64_INS_SHA512H: sha512h */ - 0, - { 0 } -}, - -{ /* AArch64_SHA512H2, AArch64_INS_SHA512H2: sha512h2 */ - 0, - { 0 } -}, - -{ /* AArch64_SHA512SU0, AArch64_INS_SHA512SU0: sha512su0 */ - 0, - { 0 } -}, - -{ /* AArch64_SHA512SU1, AArch64_INS_SHA512SU1: sha512su1 */ - 0, - { 0 } -}, - -{ /* AArch64_SHADDv16i8, AArch64_INS_SHADD: shadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHADDv2i32, AArch64_INS_SHADD: shadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHADDv4i16, AArch64_INS_SHADD: shadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHADDv4i32, AArch64_INS_SHADD: shadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHADDv8i16, AArch64_INS_SHADD: shadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHADDv8i8, AArch64_INS_SHADD: shadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLLv16i8, AArch64_INS_SHLL2: shll2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLLv2i32, AArch64_INS_SHLL: shll */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLLv4i16, AArch64_INS_SHLL: shll */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLLv4i32, AArch64_INS_SHLL2: shll2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLLv8i16, AArch64_INS_SHLL2: shll2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLLv8i8, AArch64_INS_SHLL: shll */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLd, AArch64_INS_SHL: shl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLv16i8_shift, AArch64_INS_SHL: shl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLv2i32_shift, AArch64_INS_SHL: shl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLv2i64_shift, AArch64_INS_SHL: shl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLv4i16_shift, AArch64_INS_SHL: shl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLv4i32_shift, AArch64_INS_SHL: shl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLv8i16_shift, AArch64_INS_SHL: shl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHLv8i8_shift, AArch64_INS_SHL: shl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHRNv16i8_shift, AArch64_INS_SHRN2: shrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHRNv2i32_shift, AArch64_INS_SHRN: shrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHRNv4i16_shift, AArch64_INS_SHRN: shrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHRNv4i32_shift, AArch64_INS_SHRN2: shrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHRNv8i16_shift, AArch64_INS_SHRN2: shrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHRNv8i8_shift, AArch64_INS_SHRN: shrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHSUBv16i8, AArch64_INS_SHSUB: shsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHSUBv2i32, AArch64_INS_SHSUB: shsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHSUBv4i16, AArch64_INS_SHSUB: shsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHSUBv4i32, AArch64_INS_SHSUB: shsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHSUBv8i16, AArch64_INS_SHSUB: shsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SHSUBv8i8, AArch64_INS_SHSUB: shsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SLId, AArch64_INS_SLI: sli */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SLIv16i8_shift, AArch64_INS_SLI: sli */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SLIv2i32_shift, AArch64_INS_SLI: sli */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SLIv2i64_shift, AArch64_INS_SLI: sli */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SLIv4i16_shift, AArch64_INS_SLI: sli */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SLIv4i32_shift, AArch64_INS_SLI: sli */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SLIv8i16_shift, AArch64_INS_SLI: sli */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SLIv8i8_shift, AArch64_INS_SLI: sli */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} -}, - -{ /* AArch64_SM3PARTW1, AArch64_INS_SM3PARTW1: sm3partw1 */ - 0, - { 0 } -}, - -{ /* AArch64_SM3PARTW2, AArch64_INS_SM3PARTW2: sm3partw2 */ - 0, - { 0 } -}, - -{ /* AArch64_SM3SS1, AArch64_INS_SM3SS1: sm3ss1 */ - 0, - { 0 } -}, - -{ /* AArch64_SM3TT1A, AArch64_INS_SM3TT1A: sm3tt1a */ - 0, - { 0 } -}, - -{ /* AArch64_SM3TT1B, AArch64_INS_SM3TT1B: sm3tt1b */ - 0, - { 0 } -}, - -{ /* AArch64_SM3TT2A, AArch64_INS_SM3TT2A: sm3tt2a */ - 0, - { 0 } -}, - -{ /* AArch64_SM3TT2B, AArch64_INS_SM3TT2B: sm3tt2b */ - 0, - { 0 } -}, - -{ /* AArch64_SM4E, AArch64_INS_SM4E: sm4e */ - 0, - { 0 } -}, - -{ /* AArch64_SM4ENCKEY, AArch64_INS_SM4EKEY: sm4ekey */ - 0, - { 0 } -}, - -{ /* AArch64_SMADDLrrr, AArch64_INS_SMADDL: smaddl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXPv16i8, AArch64_INS_SMAXP: smaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXPv2i32, AArch64_INS_SMAXP: smaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXPv4i16, AArch64_INS_SMAXP: smaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXPv4i32, AArch64_INS_SMAXP: smaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXPv8i16, AArch64_INS_SMAXP: smaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXPv8i8, AArch64_INS_SMAXP: smaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXV_VPZ_B, AArch64_INS_SMAXV: smaxv */ - 0, - { 0 } -}, - -{ /* AArch64_SMAXV_VPZ_D, AArch64_INS_SMAXV: smaxv */ - 0, - { 0 } -}, - -{ /* AArch64_SMAXV_VPZ_H, AArch64_INS_SMAXV: smaxv */ - 0, - { 0 } -}, - -{ /* AArch64_SMAXV_VPZ_S, AArch64_INS_SMAXV: smaxv */ - 0, - { 0 } -}, - -{ /* AArch64_SMAXVv16i8v, AArch64_INS_SMAXV: smaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXVv4i16v, AArch64_INS_SMAXV: smaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXVv4i32v, AArch64_INS_SMAXV: smaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXVv8i16v, AArch64_INS_SMAXV: smaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXVv8i8v, AArch64_INS_SMAXV: smaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAX_ZI_B, AArch64_INS_SMAX: smax */ - 0, - { 0 } -}, - -{ /* AArch64_SMAX_ZI_D, AArch64_INS_SMAX: smax */ - 0, - { 0 } -}, - -{ /* AArch64_SMAX_ZI_H, AArch64_INS_SMAX: smax */ - 0, - { 0 } -}, - -{ /* AArch64_SMAX_ZI_S, AArch64_INS_SMAX: smax */ - 0, - { 0 } -}, - -{ /* AArch64_SMAX_ZPmZ_B, AArch64_INS_SMAX: smax */ - 0, - { 0 } -}, - -{ /* AArch64_SMAX_ZPmZ_D, AArch64_INS_SMAX: smax */ - 0, - { 0 } -}, - -{ /* AArch64_SMAX_ZPmZ_H, AArch64_INS_SMAX: smax */ - 0, - { 0 } -}, - -{ /* AArch64_SMAX_ZPmZ_S, AArch64_INS_SMAX: smax */ - 0, - { 0 } -}, - -{ /* AArch64_SMAXv16i8, AArch64_INS_SMAX: smax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXv2i32, AArch64_INS_SMAX: smax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXv4i16, AArch64_INS_SMAX: smax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXv4i32, AArch64_INS_SMAX: smax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXv8i16, AArch64_INS_SMAX: smax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMAXv8i8, AArch64_INS_SMAX: smax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMC, AArch64_INS_SMC: smc */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINPv16i8, AArch64_INS_SMINP: sminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINPv2i32, AArch64_INS_SMINP: sminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINPv4i16, AArch64_INS_SMINP: sminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINPv4i32, AArch64_INS_SMINP: sminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINPv8i16, AArch64_INS_SMINP: sminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINPv8i8, AArch64_INS_SMINP: sminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINV_VPZ_B, AArch64_INS_SMINV: sminv */ - 0, - { 0 } -}, - -{ /* AArch64_SMINV_VPZ_D, AArch64_INS_SMINV: sminv */ - 0, - { 0 } -}, - -{ /* AArch64_SMINV_VPZ_H, AArch64_INS_SMINV: sminv */ - 0, - { 0 } -}, - -{ /* AArch64_SMINV_VPZ_S, AArch64_INS_SMINV: sminv */ - 0, - { 0 } -}, - -{ /* AArch64_SMINVv16i8v, AArch64_INS_SMINV: sminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINVv4i16v, AArch64_INS_SMINV: sminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINVv4i32v, AArch64_INS_SMINV: sminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINVv8i16v, AArch64_INS_SMINV: sminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINVv8i8v, AArch64_INS_SMINV: sminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMIN_ZI_B, AArch64_INS_SMIN: smin */ - 0, - { 0 } -}, - -{ /* AArch64_SMIN_ZI_D, AArch64_INS_SMIN: smin */ - 0, - { 0 } -}, - -{ /* AArch64_SMIN_ZI_H, AArch64_INS_SMIN: smin */ - 0, - { 0 } -}, - -{ /* AArch64_SMIN_ZI_S, AArch64_INS_SMIN: smin */ - 0, - { 0 } -}, - -{ /* AArch64_SMIN_ZPmZ_B, AArch64_INS_SMIN: smin */ - 0, - { 0 } -}, - -{ /* AArch64_SMIN_ZPmZ_D, AArch64_INS_SMIN: smin */ - 0, - { 0 } -}, - -{ /* AArch64_SMIN_ZPmZ_H, AArch64_INS_SMIN: smin */ - 0, - { 0 } -}, - -{ /* AArch64_SMIN_ZPmZ_S, AArch64_INS_SMIN: smin */ - 0, - { 0 } -}, - -{ /* AArch64_SMINv16i8, AArch64_INS_SMIN: smin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINv2i32, AArch64_INS_SMIN: smin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINv4i16, AArch64_INS_SMIN: smin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINv4i32, AArch64_INS_SMIN: smin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINv8i16, AArch64_INS_SMIN: smin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMINv8i8, AArch64_INS_SMIN: smin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLALv16i8_v8i16, AArch64_INS_SMLAL2: smlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLALv2i32_indexed, AArch64_INS_SMLAL: smlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SMLALv2i32_v2i64, AArch64_INS_SMLAL: smlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLALv4i16_indexed, AArch64_INS_SMLAL: smlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SMLALv4i16_v4i32, AArch64_INS_SMLAL: smlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLALv4i32_indexed, AArch64_INS_SMLAL2: smlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SMLALv4i32_v2i64, AArch64_INS_SMLAL2: smlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLALv8i16_indexed, AArch64_INS_SMLAL2: smlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SMLALv8i16_v4i32, AArch64_INS_SMLAL2: smlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLALv8i8_v8i16, AArch64_INS_SMLAL: smlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLSLv16i8_v8i16, AArch64_INS_SMLSL2: smlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLSLv2i32_indexed, AArch64_INS_SMLSL: smlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SMLSLv2i32_v2i64, AArch64_INS_SMLSL: smlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLSLv4i16_indexed, AArch64_INS_SMLSL: smlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SMLSLv4i16_v4i32, AArch64_INS_SMLSL: smlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLSLv4i32_indexed, AArch64_INS_SMLSL2: smlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SMLSLv4i32_v2i64, AArch64_INS_SMLSL2: smlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLSLv8i16_indexed, AArch64_INS_SMLSL2: smlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SMLSLv8i16_v4i32, AArch64_INS_SMLSL2: smlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMLSLv8i8_v8i16, AArch64_INS_SMLSL: smlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMOVvi16to32, AArch64_INS_SMOV: smov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMOVvi16to64, AArch64_INS_SMOV: smov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMOVvi32to64, AArch64_INS_SMOV: smov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMOVvi8to32, AArch64_INS_SMOV: smov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMOVvi8to64, AArch64_INS_SMOV: smov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMSUBLrrr, AArch64_INS_SMNEGL: smnegl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULH_ZPmZ_B, AArch64_INS_SMULH: smulh */ - 0, - { 0 } -}, - -{ /* AArch64_SMULH_ZPmZ_D, AArch64_INS_SMULH: smulh */ - 0, - { 0 } -}, - -{ /* AArch64_SMULH_ZPmZ_H, AArch64_INS_SMULH: smulh */ - 0, - { 0 } -}, - -{ /* AArch64_SMULH_ZPmZ_S, AArch64_INS_SMULH: smulh */ - 0, - { 0 } -}, - -{ /* AArch64_SMULHrr, AArch64_INS_SMULH: smulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv16i8_v8i16, AArch64_INS_SMULL2: smull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv2i32_indexed, AArch64_INS_SMULL: smull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv2i32_v2i64, AArch64_INS_SMULL: smull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv4i16_indexed, AArch64_INS_SMULL: smull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv4i16_v4i32, AArch64_INS_SMULL: smull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv4i32_indexed, AArch64_INS_SMULL2: smull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv4i32_v2i64, AArch64_INS_SMULL2: smull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv8i16_indexed, AArch64_INS_SMULL2: smull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv8i16_v4i32, AArch64_INS_SMULL2: smull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SMULLv8i8_v8i16, AArch64_INS_SMULL: smull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SPLICE_ZPZ_B, AArch64_INS_SPLICE: splice */ - 0, - { 0 } -}, - -{ /* AArch64_SPLICE_ZPZ_D, AArch64_INS_SPLICE: splice */ - 0, - { 0 } -}, - -{ /* AArch64_SPLICE_ZPZ_H, AArch64_INS_SPLICE: splice */ - 0, - { 0 } -}, - -{ /* AArch64_SPLICE_ZPZ_S, AArch64_INS_SPLICE: splice */ - 0, - { 0 } -}, - -{ /* AArch64_SQABSv16i8, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv1i16, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv1i32, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv1i64, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv1i8, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv2i32, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv2i64, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv4i16, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv4i32, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv8i16, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQABSv8i8, AArch64_INS_SQABS: sqabs */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADD_ZI_B, AArch64_INS_SQADD: sqadd */ - 0, - { 0 } -}, - -{ /* AArch64_SQADD_ZI_D, AArch64_INS_SQADD: sqadd */ - 0, - { 0 } -}, - -{ /* AArch64_SQADD_ZI_H, AArch64_INS_SQADD: sqadd */ - 0, - { 0 } -}, - -{ /* AArch64_SQADD_ZI_S, AArch64_INS_SQADD: sqadd */ - 0, - { 0 } -}, - -{ /* AArch64_SQADD_ZZZ_B, AArch64_INS_SQADD: sqadd */ - 0, - { 0 } -}, - -{ /* AArch64_SQADD_ZZZ_D, AArch64_INS_SQADD: sqadd */ - 0, - { 0 } -}, - -{ /* AArch64_SQADD_ZZZ_H, AArch64_INS_SQADD: sqadd */ - 0, - { 0 } -}, - -{ /* AArch64_SQADD_ZZZ_S, AArch64_INS_SQADD: sqadd */ - 0, - { 0 } -}, - -{ /* AArch64_SQADDv16i8, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv1i16, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv1i32, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv1i64, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv1i8, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv2i32, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv2i64, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv4i16, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv4i32, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv8i16, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQADDv8i8, AArch64_INS_SQADD: sqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDECB_XPiI, AArch64_INS_SQDECB: sqdecb */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECB_XPiWdI, AArch64_INS_SQDECB: sqdecb */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECD_XPiI, AArch64_INS_SQDECD: sqdecd */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECD_XPiWdI, AArch64_INS_SQDECD: sqdecd */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECD_ZPiI, AArch64_INS_SQDECD: sqdecd */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECH_XPiI, AArch64_INS_SQDECH: sqdech */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECH_XPiWdI, AArch64_INS_SQDECH: sqdech */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECH_ZPiI, AArch64_INS_SQDECH: sqdech */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_XPWd_B, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_XPWd_D, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_XPWd_H, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_XPWd_S, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_XP_B, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_XP_D, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_XP_H, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_XP_S, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_ZP_D, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_ZP_H, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECP_ZP_S, AArch64_INS_SQDECP: sqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECW_XPiI, AArch64_INS_SQDECW: sqdecw */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECW_XPiWdI, AArch64_INS_SQDECW: sqdecw */ - 0, - { 0 } -}, - -{ /* AArch64_SQDECW_ZPiI, AArch64_INS_SQDECW: sqdecw */ - 0, - { 0 } -}, - -{ /* AArch64_SQDMLALi16, AArch64_INS_SQDMLAL: sqdmlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLALi32, AArch64_INS_SQDMLAL: sqdmlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLALv1i32_indexed, AArch64_INS_SQDMLAL: sqdmlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLALv1i64_indexed, AArch64_INS_SQDMLAL: sqdmlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLALv2i32_indexed, AArch64_INS_SQDMLAL: sqdmlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLALv2i32_v2i64, AArch64_INS_SQDMLAL: sqdmlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLALv4i16_indexed, AArch64_INS_SQDMLAL: sqdmlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLALv4i16_v4i32, AArch64_INS_SQDMLAL: sqdmlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLALv4i32_indexed, AArch64_INS_SQDMLAL2: sqdmlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLALv4i32_v2i64, AArch64_INS_SQDMLAL2: sqdmlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLALv8i16_indexed, AArch64_INS_SQDMLAL2: sqdmlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLALv8i16_v4i32, AArch64_INS_SQDMLAL2: sqdmlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLSLi16, AArch64_INS_SQDMLSL: sqdmlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLSLi32, AArch64_INS_SQDMLSL: sqdmlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLSLv1i32_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLSLv1i64_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLSLv2i32_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLSLv2i32_v2i64, AArch64_INS_SQDMLSL: sqdmlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLSLv4i16_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLSLv4i16_v4i32, AArch64_INS_SQDMLSL: sqdmlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLSLv4i32_indexed, AArch64_INS_SQDMLSL2: sqdmlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLSLv4i32_v2i64, AArch64_INS_SQDMLSL2: sqdmlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMLSLv8i16_indexed, AArch64_INS_SQDMLSL2: sqdmlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQDMLSLv8i16_v4i32, AArch64_INS_SQDMLSL2: sqdmlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv1i16, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv1i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv1i32, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv1i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv2i32, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv2i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv4i16, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv4i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv4i32, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv4i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv8i16, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULHv8i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLi16, AArch64_INS_SQDMULL: sqdmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLi32, AArch64_INS_SQDMULL: sqdmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv1i32_indexed, AArch64_INS_SQDMULL: sqdmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv1i64_indexed, AArch64_INS_SQDMULL: sqdmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv2i32_indexed, AArch64_INS_SQDMULL: sqdmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv2i32_v2i64, AArch64_INS_SQDMULL: sqdmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv4i16_indexed, AArch64_INS_SQDMULL: sqdmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv4i16_v4i32, AArch64_INS_SQDMULL: sqdmull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv4i32_indexed, AArch64_INS_SQDMULL2: sqdmull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv4i32_v2i64, AArch64_INS_SQDMULL2: sqdmull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv8i16_indexed, AArch64_INS_SQDMULL2: sqdmull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQDMULLv8i16_v4i32, AArch64_INS_SQDMULL2: sqdmull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQINCB_XPiI, AArch64_INS_SQINCB: sqincb */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCB_XPiWdI, AArch64_INS_SQINCB: sqincb */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCD_XPiI, AArch64_INS_SQINCD: sqincd */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCD_XPiWdI, AArch64_INS_SQINCD: sqincd */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCD_ZPiI, AArch64_INS_SQINCD: sqincd */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCH_XPiI, AArch64_INS_SQINCH: sqinch */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCH_XPiWdI, AArch64_INS_SQINCH: sqinch */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCH_ZPiI, AArch64_INS_SQINCH: sqinch */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_XPWd_B, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_XPWd_D, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_XPWd_H, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_XPWd_S, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_XP_B, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_XP_D, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_XP_H, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_XP_S, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_ZP_D, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_ZP_H, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCP_ZP_S, AArch64_INS_SQINCP: sqincp */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCW_XPiI, AArch64_INS_SQINCW: sqincw */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCW_XPiWdI, AArch64_INS_SQINCW: sqincw */ - 0, - { 0 } -}, - -{ /* AArch64_SQINCW_ZPiI, AArch64_INS_SQINCW: sqincw */ - 0, - { 0 } -}, - -{ /* AArch64_SQNEGv16i8, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv1i16, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv1i32, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv1i64, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv1i8, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv2i32, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv2i64, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv4i16, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv4i32, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv8i16, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQNEGv8i8, AArch64_INS_SQNEG: sqneg */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRDMLAHi16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHi32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv1i16, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv1i32, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv2i32, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv2i32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv4i16, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv4i16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv4i32, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv4i32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv8i16, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLAHv8i16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHi16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHi32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv1i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv1i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv2i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv2i32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv4i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv4i16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv4i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv4i32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv8i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMLSHv8i16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ - 0, - { 0 } -}, - -{ /* AArch64_SQRDMULHv1i16, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRDMULHv1i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQRDMULHv1i32, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRDMULHv1i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQRDMULHv2i32, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRDMULHv2i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQRDMULHv4i16, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRDMULHv4i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQRDMULHv4i32, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRDMULHv4i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQRDMULHv8i16, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRDMULHv8i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SQRSHLv16i8, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv1i16, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv1i32, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv1i64, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv1i8, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv2i32, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv2i64, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv4i16, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv4i32, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv8i16, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHLv8i8, AArch64_INS_SQRSHL: sqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRNb, AArch64_INS_SQRSHRN: sqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRNh, AArch64_INS_SQRSHRN: sqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRNs, AArch64_INS_SQRSHRN: sqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRNv16i8_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRNv2i32_shift, AArch64_INS_SQRSHRN: sqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRNv4i16_shift, AArch64_INS_SQRSHRN: sqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRNv4i32_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRNv8i16_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRNv8i8_shift, AArch64_INS_SQRSHRN: sqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRUNb, AArch64_INS_SQRSHRUN: sqrshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRUNh, AArch64_INS_SQRSHRUN: sqrshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRUNs, AArch64_INS_SQRSHRUN: sqrshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRUNv16i8_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRUNv2i32_shift, AArch64_INS_SQRSHRUN: sqrshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRUNv4i16_shift, AArch64_INS_SQRSHRUN: sqrshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRUNv4i32_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRUNv8i16_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQRSHRUNv8i8_shift, AArch64_INS_SQRSHRUN: sqrshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUb, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUd, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUh, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUs, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUv16i8_shift, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUv2i32_shift, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUv2i64_shift, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUv4i16_shift, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUv4i32_shift, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUv8i16_shift, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLUv8i8_shift, AArch64_INS_SQSHLU: sqshlu */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLb, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLd, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLh, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLs, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv16i8, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv16i8_shift, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv1i16, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv1i32, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv1i64, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv1i8, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv2i32, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv2i32_shift, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv2i64, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv2i64_shift, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv4i16, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv4i16_shift, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv4i32, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv4i32_shift, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv8i16, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv8i16_shift, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv8i8, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHLv8i8_shift, AArch64_INS_SQSHL: sqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRNb, AArch64_INS_SQSHRN: sqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRNh, AArch64_INS_SQSHRN: sqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRNs, AArch64_INS_SQSHRN: sqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRNv16i8_shift, AArch64_INS_SQSHRN2: sqshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRNv2i32_shift, AArch64_INS_SQSHRN: sqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRNv4i16_shift, AArch64_INS_SQSHRN: sqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRNv4i32_shift, AArch64_INS_SQSHRN2: sqshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRNv8i16_shift, AArch64_INS_SQSHRN2: sqshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRNv8i8_shift, AArch64_INS_SQSHRN: sqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRUNb, AArch64_INS_SQSHRUN: sqshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRUNh, AArch64_INS_SQSHRUN: sqshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRUNs, AArch64_INS_SQSHRUN: sqshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRUNv16i8_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRUNv2i32_shift, AArch64_INS_SQSHRUN: sqshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRUNv4i16_shift, AArch64_INS_SQSHRUN: sqshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRUNv4i32_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRUNv8i16_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSHRUNv8i8_shift, AArch64_INS_SQSHRUN: sqshrun */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUB_ZI_B, AArch64_INS_SQSUB: sqsub */ - 0, - { 0 } -}, - -{ /* AArch64_SQSUB_ZI_D, AArch64_INS_SQSUB: sqsub */ - 0, - { 0 } -}, - -{ /* AArch64_SQSUB_ZI_H, AArch64_INS_SQSUB: sqsub */ - 0, - { 0 } -}, - -{ /* AArch64_SQSUB_ZI_S, AArch64_INS_SQSUB: sqsub */ - 0, - { 0 } -}, - -{ /* AArch64_SQSUB_ZZZ_B, AArch64_INS_SQSUB: sqsub */ - 0, - { 0 } -}, - -{ /* AArch64_SQSUB_ZZZ_D, AArch64_INS_SQSUB: sqsub */ - 0, - { 0 } -}, - -{ /* AArch64_SQSUB_ZZZ_H, AArch64_INS_SQSUB: sqsub */ - 0, - { 0 } -}, - -{ /* AArch64_SQSUB_ZZZ_S, AArch64_INS_SQSUB: sqsub */ - 0, - { 0 } -}, - -{ /* AArch64_SQSUBv16i8, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv1i16, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv1i32, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv1i64, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv1i8, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv2i32, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv2i64, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv4i16, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv4i32, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv8i16, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQSUBv8i8, AArch64_INS_SQSUB: sqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTNv16i8, AArch64_INS_SQXTN2: sqxtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTNv1i16, AArch64_INS_SQXTN: sqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTNv1i32, AArch64_INS_SQXTN: sqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTNv1i8, AArch64_INS_SQXTN: sqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTNv2i32, AArch64_INS_SQXTN: sqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTNv4i16, AArch64_INS_SQXTN: sqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTNv4i32, AArch64_INS_SQXTN2: sqxtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTNv8i16, AArch64_INS_SQXTN2: sqxtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTNv8i8, AArch64_INS_SQXTN: sqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTUNv16i8, AArch64_INS_SQXTUN2: sqxtun2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTUNv1i16, AArch64_INS_SQXTUN: sqxtun */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTUNv1i32, AArch64_INS_SQXTUN: sqxtun */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTUNv1i8, AArch64_INS_SQXTUN: sqxtun */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTUNv2i32, AArch64_INS_SQXTUN: sqxtun */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTUNv4i16, AArch64_INS_SQXTUN: sqxtun */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTUNv4i32, AArch64_INS_SQXTUN2: sqxtun2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTUNv8i16, AArch64_INS_SQXTUN2: sqxtun2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SQXTUNv8i8, AArch64_INS_SQXTUN: sqxtun */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRHADDv16i8, AArch64_INS_SRHADD: srhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRHADDv2i32, AArch64_INS_SRHADD: srhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRHADDv4i16, AArch64_INS_SRHADD: srhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRHADDv4i32, AArch64_INS_SRHADD: srhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRHADDv8i16, AArch64_INS_SRHADD: srhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRHADDv8i8, AArch64_INS_SRHADD: srhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRId, AArch64_INS_SRI: sri */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRIv16i8_shift, AArch64_INS_SRI: sri */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRIv2i32_shift, AArch64_INS_SRI: sri */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRIv2i64_shift, AArch64_INS_SRI: sri */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRIv4i16_shift, AArch64_INS_SRI: sri */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRIv4i32_shift, AArch64_INS_SRI: sri */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRIv8i16_shift, AArch64_INS_SRI: sri */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRIv8i8_shift, AArch64_INS_SRI: sri */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHLv16i8, AArch64_INS_SRSHL: srshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHLv1i64, AArch64_INS_SRSHL: srshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHLv2i32, AArch64_INS_SRSHL: srshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHLv2i64, AArch64_INS_SRSHL: srshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHLv4i16, AArch64_INS_SRSHL: srshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHLv4i32, AArch64_INS_SRSHL: srshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHLv8i16, AArch64_INS_SRSHL: srshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHLv8i8, AArch64_INS_SRSHL: srshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHRd, AArch64_INS_SRSHR: srshr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHRv16i8_shift, AArch64_INS_SRSHR: srshr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHRv2i32_shift, AArch64_INS_SRSHR: srshr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHRv2i64_shift, AArch64_INS_SRSHR: srshr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHRv4i16_shift, AArch64_INS_SRSHR: srshr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHRv4i32_shift, AArch64_INS_SRSHR: srshr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHRv8i16_shift, AArch64_INS_SRSHR: srshr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSHRv8i8_shift, AArch64_INS_SRSHR: srshr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSRAd, AArch64_INS_SRSRA: srsra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSRAv16i8_shift, AArch64_INS_SRSRA: srsra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSRAv2i32_shift, AArch64_INS_SRSRA: srsra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSRAv2i64_shift, AArch64_INS_SRSRA: srsra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSRAv4i16_shift, AArch64_INS_SRSRA: srsra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSRAv4i32_shift, AArch64_INS_SRSRA: srsra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSRAv8i16_shift, AArch64_INS_SRSRA: srsra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SRSRAv8i8_shift, AArch64_INS_SRSRA: srsra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLLv16i8_shift, AArch64_INS_SSHLL2: sshll2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLLv2i32_shift, AArch64_INS_SSHLL: sshll */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLLv4i16_shift, AArch64_INS_SSHLL: sshll */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLLv4i32_shift, AArch64_INS_SSHLL2: sshll2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLLv8i16_shift, AArch64_INS_SSHLL2: sshll2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLLv8i8_shift, AArch64_INS_SSHLL: sshll */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLv16i8, AArch64_INS_SSHL: sshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLv1i64, AArch64_INS_SSHL: sshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLv2i32, AArch64_INS_SSHL: sshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLv2i64, AArch64_INS_SSHL: sshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLv4i16, AArch64_INS_SSHL: sshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLv4i32, AArch64_INS_SSHL: sshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLv8i16, AArch64_INS_SSHL: sshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHLv8i8, AArch64_INS_SSHL: sshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHRd, AArch64_INS_SSHR: sshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHRv16i8_shift, AArch64_INS_SSHR: sshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHRv2i32_shift, AArch64_INS_SSHR: sshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHRv2i64_shift, AArch64_INS_SSHR: sshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHRv4i16_shift, AArch64_INS_SSHR: sshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHRv4i32_shift, AArch64_INS_SSHR: sshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHRv8i16_shift, AArch64_INS_SSHR: sshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSHRv8i8_shift, AArch64_INS_SSHR: sshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSRAd, AArch64_INS_SSRA: ssra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSRAv16i8_shift, AArch64_INS_SSRA: ssra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSRAv2i32_shift, AArch64_INS_SSRA: ssra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSRAv2i64_shift, AArch64_INS_SSRA: ssra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSRAv4i16_shift, AArch64_INS_SSRA: ssra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSRAv4i32_shift, AArch64_INS_SSRA: ssra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSRAv8i16_shift, AArch64_INS_SSRA: ssra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSRAv8i8_shift, AArch64_INS_SSRA: ssra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SST1B_D, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_SST1B_D_IMM, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_SST1B_D_SXTW, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_SST1B_D_UXTW, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_SST1B_S_IMM, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_SST1B_S_SXTW, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_SST1B_S_UXTW, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_SST1D, AArch64_INS_ST1D: st1d */ - 0, - { 0 } -}, - -{ /* AArch64_SST1D_IMM, AArch64_INS_ST1D: st1d */ - 0, - { 0 } -}, - -{ /* AArch64_SST1D_SCALED, AArch64_INS_ST1D: st1d */ - 0, - { 0 } -}, - -{ /* AArch64_SST1D_SXTW, AArch64_INS_ST1D: st1d */ - 0, - { 0 } -}, - -{ /* AArch64_SST1D_SXTW_SCALED, AArch64_INS_ST1D: st1d */ - 0, - { 0 } -}, - -{ /* AArch64_SST1D_UXTW, AArch64_INS_ST1D: st1d */ - 0, - { 0 } -}, - -{ /* AArch64_SST1D_UXTW_SCALED, AArch64_INS_ST1D: st1d */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_D, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_D_IMM, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_D_SCALED, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_D_SXTW, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_D_SXTW_SCALED, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_D_UXTW, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_D_UXTW_SCALED, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_S_IMM, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_S_SXTW, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_S_SXTW_SCALED, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_S_UXTW, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1H_S_UXTW_SCALED, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_D, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_D_IMM, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_D_SCALED, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_D_SXTW, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_D_SXTW_SCALED, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_D_UXTW, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_D_UXTW_SCALED, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_IMM, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_SXTW, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_SXTW_SCALED, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_UXTW, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SST1W_UXTW_SCALED, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_SSUBLv16i8_v8i16, AArch64_INS_SSUBL2: ssubl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBLv2i32_v2i64, AArch64_INS_SSUBL: ssubl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBLv4i16_v4i32, AArch64_INS_SSUBL: ssubl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBLv4i32_v2i64, AArch64_INS_SSUBL2: ssubl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBLv8i16_v4i32, AArch64_INS_SSUBL2: ssubl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBLv8i8_v8i16, AArch64_INS_SSUBL: ssubl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBWv16i8_v8i16, AArch64_INS_SSUBW2: ssubw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBWv2i32_v2i64, AArch64_INS_SSUBW: ssubw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBWv4i16_v4i32, AArch64_INS_SSUBW: ssubw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBWv4i32_v2i64, AArch64_INS_SSUBW2: ssubw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBWv8i16_v4i32, AArch64_INS_SSUBW2: ssubw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SSUBWv8i8_v8i16, AArch64_INS_SSUBW: ssubw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1B, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_ST1B_D, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_ST1B_D_IMM, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_ST1B_H, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_ST1B_H_IMM, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_ST1B_IMM, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_ST1B_S, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_ST1B_S_IMM, AArch64_INS_ST1B: st1b */ - 0, - { 0 } -}, - -{ /* AArch64_ST1D, AArch64_INS_ST1D: st1d */ - 0, - { 0 } -}, - -{ /* AArch64_ST1D_IMM, AArch64_INS_ST1D: st1d */ - 0, - { 0 } -}, - -{ /* AArch64_ST1Fourv16b, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv16b_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv1d, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv1d_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv2d, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv2d_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv2s, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv2s_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv4h, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv4h_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv4s, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv4s_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv8b, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv8b_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv8h, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Fourv8h_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1H, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_ST1H_D, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_ST1H_D_IMM, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_ST1H_IMM, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_ST1H_S, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_ST1H_S_IMM, AArch64_INS_ST1H: st1h */ - 0, - { 0 } -}, - -{ /* AArch64_ST1Onev16b, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev16b_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev1d, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev1d_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev2d, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev2d_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev2s, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev2s_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev4h, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev4h_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev4s, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev4s_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev8b, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev8b_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev8h, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Onev8h_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev16b, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev16b_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev1d, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev1d_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev2d, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev2d_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev2s, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev2s_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev4h, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev4h_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev4s, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev4s_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev8b, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev8b_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev8h, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Threev8h_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov16b, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov16b_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov1d, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov1d_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov2d, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov2d_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov2s, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov2s_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov4h, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov4h_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov4s, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov4s_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov8b, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov8b_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov8h, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1Twov8h_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1W, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_ST1W_D, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_ST1W_D_IMM, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_ST1W_IMM, AArch64_INS_ST1W: st1w */ - 0, - { 0 } -}, - -{ /* AArch64_ST1i16, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1i16_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1i32, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1i32_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1i64, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1i64_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1i8, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST1i8_POST, AArch64_INS_ST1: st1 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2B, AArch64_INS_ST2B: st2b */ - 0, - { 0 } -}, - -{ /* AArch64_ST2B_IMM, AArch64_INS_ST2B: st2b */ - 0, - { 0 } -}, - -{ /* AArch64_ST2D, AArch64_INS_ST2D: st2d */ - 0, - { 0 } -}, - -{ /* AArch64_ST2D_IMM, AArch64_INS_ST2D: st2d */ - 0, - { 0 } -}, - -{ /* AArch64_ST2H, AArch64_INS_ST2H: st2h */ - 0, - { 0 } -}, - -{ /* AArch64_ST2H_IMM, AArch64_INS_ST2H: st2h */ - 0, - { 0 } -}, - -{ /* AArch64_ST2Twov16b, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov16b_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov2d, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov2d_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov2s, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov2s_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov4h, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov4h_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov4s, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov4s_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov8b, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov8b_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov8h, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2Twov8h_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2W, AArch64_INS_ST2W: st2w */ - 0, - { 0 } -}, - -{ /* AArch64_ST2W_IMM, AArch64_INS_ST2W: st2w */ - 0, - { 0 } -}, - -{ /* AArch64_ST2i16, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2i16_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2i32, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2i32_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2i64, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2i64_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2i8, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST2i8_POST, AArch64_INS_ST2: st2 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3B, AArch64_INS_ST3B: st3b */ - 0, - { 0 } -}, - -{ /* AArch64_ST3B_IMM, AArch64_INS_ST3B: st3b */ - 0, - { 0 } -}, - -{ /* AArch64_ST3D, AArch64_INS_ST3D: st3d */ - 0, - { 0 } -}, - -{ /* AArch64_ST3D_IMM, AArch64_INS_ST3D: st3d */ - 0, - { 0 } -}, - -{ /* AArch64_ST3H, AArch64_INS_ST3H: st3h */ - 0, - { 0 } -}, - -{ /* AArch64_ST3H_IMM, AArch64_INS_ST3H: st3h */ - 0, - { 0 } -}, - -{ /* AArch64_ST3Threev16b, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev16b_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev2d, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev2d_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev2s, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev2s_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev4h, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev4h_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev4s, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev4s_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev8b, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev8b_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev8h, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3Threev8h_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3W, AArch64_INS_ST3W: st3w */ - 0, - { 0 } -}, - -{ /* AArch64_ST3W_IMM, AArch64_INS_ST3W: st3w */ - 0, - { 0 } -}, - -{ /* AArch64_ST3i16, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3i16_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3i32, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3i32_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3i64, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3i64_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3i8, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST3i8_POST, AArch64_INS_ST3: st3 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4B, AArch64_INS_ST4B: st4b */ - 0, - { 0 } -}, - -{ /* AArch64_ST4B_IMM, AArch64_INS_ST4B: st4b */ - 0, - { 0 } -}, - -{ /* AArch64_ST4D, AArch64_INS_ST4D: st4d */ - 0, - { 0 } -}, - -{ /* AArch64_ST4D_IMM, AArch64_INS_ST4D: st4d */ - 0, - { 0 } -}, - -{ /* AArch64_ST4Fourv16b, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv16b_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv2d, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv2d_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv2s, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv2s_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv4h, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv4h_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv4s, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv4s_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv8b, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv8b_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv8h, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4Fourv8h_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4H, AArch64_INS_ST4H: st4h */ - 0, - { 0 } -}, - -{ /* AArch64_ST4H_IMM, AArch64_INS_ST4H: st4h */ - 0, - { 0 } -}, - -{ /* AArch64_ST4W, AArch64_INS_ST4W: st4w */ - 0, - { 0 } -}, - -{ /* AArch64_ST4W_IMM, AArch64_INS_ST4W: st4w */ - 0, - { 0 } -}, - -{ /* AArch64_ST4i16, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4i16_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4i32, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4i32_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4i64, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4i64_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4i8, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } -}, - -{ /* AArch64_ST4i8_POST, AArch64_INS_ST4: st4 */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLLRB, AArch64_INS_STLLRB: stllrb */ - 0, - { 0 } -}, - -{ /* AArch64_STLLRH, AArch64_INS_STLLRH: stllrh */ - 0, - { 0 } -}, - -{ /* AArch64_STLLRW, AArch64_INS_STLLR: stllr */ - 0, - { 0 } -}, - -{ /* AArch64_STLLRX, AArch64_INS_STLLR: stllr */ - 0, - { 0 } -}, - -{ /* AArch64_STLRB, AArch64_INS_STLRB: stlrb */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLRH, AArch64_INS_STLRH: stlrh */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLRW, AArch64_INS_STLR: stlr */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLRX, AArch64_INS_STLR: stlr */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLURBi, AArch64_INS_STLURB: stlurb */ - 0, - { 0 } -}, - -{ /* AArch64_STLURHi, AArch64_INS_STLURH: stlurh */ - 0, - { 0 } -}, - -{ /* AArch64_STLURWi, AArch64_INS_STLUR: stlur */ - 0, - { 0 } -}, - -{ /* AArch64_STLURXi, AArch64_INS_STLUR: stlur */ - 0, - { 0 } -}, - -{ /* AArch64_STLXPW, AArch64_INS_STLXP: stlxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLXPX, AArch64_INS_STLXP: stlxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLXRB, AArch64_INS_STLXRB: stlxrb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLXRH, AArch64_INS_STLXRH: stlxrh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLXRW, AArch64_INS_STLXR: stlxr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STLXRX, AArch64_INS_STLXR: stlxr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STNPDi, AArch64_INS_STNP: stnp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STNPQi, AArch64_INS_STNP: stnp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STNPSi, AArch64_INS_STNP: stnp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STNPWi, AArch64_INS_STNP: stnp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STNPXi, AArch64_INS_STNP: stnp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STNT1B_ZRI, AArch64_INS_STNT1B: stnt1b */ - 0, - { 0 } -}, - -{ /* AArch64_STNT1B_ZRR, AArch64_INS_STNT1B: stnt1b */ - 0, - { 0 } -}, - -{ /* AArch64_STNT1D_ZRI, AArch64_INS_STNT1D: stnt1d */ - 0, - { 0 } -}, - -{ /* AArch64_STNT1D_ZRR, AArch64_INS_STNT1D: stnt1d */ - 0, - { 0 } -}, - -{ /* AArch64_STNT1H_ZRI, AArch64_INS_STNT1H: stnt1h */ - 0, - { 0 } -}, - -{ /* AArch64_STNT1H_ZRR, AArch64_INS_STNT1H: stnt1h */ - 0, - { 0 } -}, - -{ /* AArch64_STNT1W_ZRI, AArch64_INS_STNT1W: stnt1w */ - 0, - { 0 } -}, - -{ /* AArch64_STNT1W_ZRR, AArch64_INS_STNT1W: stnt1w */ - 0, - { 0 } -}, - -{ /* AArch64_STPDi, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPDpost, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPDpre, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPQi, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPQpost, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPQpre, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPSi, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPSpost, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPSpre, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPWi, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPWpost, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPWpre, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPXi, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPXpost, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STPXpre, AArch64_INS_STP: stp */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRBBpost, AArch64_INS_STRB: strb */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRBBpre, AArch64_INS_STRB: strb */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRBBroW, AArch64_INS_STRB: strb */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRBBroX, AArch64_INS_STRB: strb */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRBBui, AArch64_INS_STRB: strb */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRBpost, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRBpre, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRBroW, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRBroX, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRBui, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRDpost, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRDpre, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRDroW, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRDroX, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRDui, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRHHpost, AArch64_INS_STRH: strh */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRHHpre, AArch64_INS_STRH: strh */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRHHroW, AArch64_INS_STRH: strh */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRHHroX, AArch64_INS_STRH: strh */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRHHui, AArch64_INS_STRH: strh */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRHpost, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRHpre, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRHroW, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRHroX, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRHui, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRQpost, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRQpre, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRQroW, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRQroX, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRQui, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRSpost, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRSpre, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRSroW, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRSroX, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRSui, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRWpost, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRWpre, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRWroW, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRWroX, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRWui, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRXpost, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRXpre, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STRXroW, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRXroX, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STRXui, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STR_PXI, AArch64_INS_STR: str */ - 0, - { 0 } -}, - -{ /* AArch64_STR_ZXI, AArch64_INS_STR: str */ - 0, - { 0 } -}, - -{ /* AArch64_STTRBi, AArch64_INS_STTRB: sttrb */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STTRHi, AArch64_INS_STTRH: sttrh */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STTRWi, AArch64_INS_STTR: sttr */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STTRXi, AArch64_INS_STTR: sttr */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STURBBi, AArch64_INS_STRB: strb */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STURBi, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STURDi, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STURHHi, AArch64_INS_STRH: strh */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STURHi, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STURQi, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STURSi, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STURWi, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STURXi, AArch64_INS_STR: str */ - 0, - { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STXPW, AArch64_INS_STXP: stxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STXPX, AArch64_INS_STXP: stxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_STXRB, AArch64_INS_STXRB: stxrb */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STXRH, AArch64_INS_STXRH: stxrh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STXRW, AArch64_INS_STXR: stxr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_STXRX, AArch64_INS_STXR: stxr */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBHNv2i64_v2i32, AArch64_INS_SUBHN: subhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBHNv2i64_v4i32, AArch64_INS_SUBHN2: subhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBHNv4i32_v4i16, AArch64_INS_SUBHN: subhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBHNv4i32_v8i16, AArch64_INS_SUBHN2: subhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBHNv8i16_v16i8, AArch64_INS_SUBHN2: subhn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBHNv8i16_v8i8, AArch64_INS_SUBHN: subhn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBR_ZI_B, AArch64_INS_SUBR: subr */ - 0, - { 0 } -}, - -{ /* AArch64_SUBR_ZI_D, AArch64_INS_SUBR: subr */ - 0, - { 0 } -}, - -{ /* AArch64_SUBR_ZI_H, AArch64_INS_SUBR: subr */ - 0, - { 0 } -}, - -{ /* AArch64_SUBR_ZI_S, AArch64_INS_SUBR: subr */ - 0, - { 0 } -}, - -{ /* AArch64_SUBR_ZPmZ_B, AArch64_INS_SUBR: subr */ - 0, - { 0 } -}, - -{ /* AArch64_SUBR_ZPmZ_D, AArch64_INS_SUBR: subr */ - 0, - { 0 } -}, - -{ /* AArch64_SUBR_ZPmZ_H, AArch64_INS_SUBR: subr */ - 0, - { 0 } -}, - -{ /* AArch64_SUBR_ZPmZ_S, AArch64_INS_SUBR: subr */ - 0, - { 0 } -}, - -{ /* AArch64_SUBSWri, AArch64_INS_ADDS: adds */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBSWrs, AArch64_INS_CMP: cmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBSWrx, AArch64_INS_CMP: cmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBSXri, AArch64_INS_ADDS: adds */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBSXrs, AArch64_INS_CMP: cmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBSXrx, AArch64_INS_CMP: cmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBSXrx64, AArch64_INS_CMP: cmp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SUBWri, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBWrs, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBWrx, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBXri, AArch64_INS_ADD: add */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBXrs, AArch64_INS_NEG: neg */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBXrx, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBXrx64, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SUB_ZI_B, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZI_D, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZI_H, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZI_S, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZPmZ_B, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZPmZ_D, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZPmZ_H, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZPmZ_S, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZZZ_B, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZZZ_D, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZZZ_H, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUB_ZZZ_S, AArch64_INS_SUB: sub */ - 0, - { 0 } -}, - -{ /* AArch64_SUBv16i8, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBv1i64, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBv2i32, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBv2i64, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBv4i16, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBv4i32, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBv8i16, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUBv8i8, AArch64_INS_SUB: sub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUNPKHI_ZZ_D, AArch64_INS_SUNPKHI: sunpkhi */ - 0, - { 0 } -}, - -{ /* AArch64_SUNPKHI_ZZ_H, AArch64_INS_SUNPKHI: sunpkhi */ - 0, - { 0 } -}, - -{ /* AArch64_SUNPKHI_ZZ_S, AArch64_INS_SUNPKHI: sunpkhi */ - 0, - { 0 } -}, - -{ /* AArch64_SUNPKLO_ZZ_D, AArch64_INS_SUNPKLO: sunpklo */ - 0, - { 0 } -}, - -{ /* AArch64_SUNPKLO_ZZ_H, AArch64_INS_SUNPKLO: sunpklo */ - 0, - { 0 } -}, - -{ /* AArch64_SUNPKLO_ZZ_S, AArch64_INS_SUNPKLO: sunpklo */ - 0, - { 0 } -}, - -{ /* AArch64_SUQADDv16i8, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv1i16, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv1i32, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv1i64, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv1i8, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv2i32, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv2i64, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv4i16, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv4i32, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv8i16, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SUQADDv8i8, AArch64_INS_SUQADD: suqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_SVC, AArch64_INS_SVC: svc */ - 0, - { CS_AC_READ, 0 } -}, - -{ /* AArch64_SWPAB, AArch64_INS_SWPAB: swpab */ - 0, - { 0 } -}, - -{ /* AArch64_SWPAH, AArch64_INS_SWPAH: swpah */ - 0, - { 0 } -}, - -{ /* AArch64_SWPALB, AArch64_INS_SWPALB: swpalb */ - 0, - { 0 } -}, - -{ /* AArch64_SWPALH, AArch64_INS_SWPALH: swpalh */ - 0, - { 0 } -}, - -{ /* AArch64_SWPALW, AArch64_INS_SWPAL: swpal */ - 0, - { 0 } -}, - -{ /* AArch64_SWPALX, AArch64_INS_SWPAL: swpal */ - 0, - { 0 } -}, - -{ /* AArch64_SWPAW, AArch64_INS_SWPA: swpa */ - 0, - { 0 } -}, - -{ /* AArch64_SWPAX, AArch64_INS_SWPA: swpa */ - 0, - { 0 } -}, - -{ /* AArch64_SWPB, AArch64_INS_SWPB: swpb */ - 0, - { 0 } -}, - -{ /* AArch64_SWPH, AArch64_INS_SWPH: swph */ - 0, - { 0 } -}, - -{ /* AArch64_SWPLB, AArch64_INS_SWPLB: swplb */ - 0, - { 0 } -}, - -{ /* AArch64_SWPLH, AArch64_INS_SWPLH: swplh */ - 0, - { 0 } -}, - -{ /* AArch64_SWPLW, AArch64_INS_SWPL: swpl */ - 0, - { 0 } -}, - -{ /* AArch64_SWPLX, AArch64_INS_SWPL: swpl */ - 0, - { 0 } -}, - -{ /* AArch64_SWPW, AArch64_INS_SWP: swp */ - 0, - { 0 } -}, - -{ /* AArch64_SWPX, AArch64_INS_SWP: swp */ - 0, - { 0 } -}, - -{ /* AArch64_SXTB_ZPmZ_D, AArch64_INS_SXTB: sxtb */ - 0, - { 0 } -}, - -{ /* AArch64_SXTB_ZPmZ_H, AArch64_INS_SXTB: sxtb */ - 0, - { 0 } -}, - -{ /* AArch64_SXTB_ZPmZ_S, AArch64_INS_SXTB: sxtb */ - 0, - { 0 } -}, - -{ /* AArch64_SXTH_ZPmZ_D, AArch64_INS_SXTH: sxth */ - 0, - { 0 } -}, - -{ /* AArch64_SXTH_ZPmZ_S, AArch64_INS_SXTH: sxth */ - 0, - { 0 } -}, - -{ /* AArch64_SXTW_ZPmZ_D, AArch64_INS_SXTW: sxtw */ - 0, - { 0 } -}, - -{ /* AArch64_SYSLxt, AArch64_INS_SYSL: sysl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, - -{ /* AArch64_SYSxt, AArch64_INS_SYS: sys */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ } -}, - -{ /* AArch64_TBL_ZZZ_B, AArch64_INS_TBL: tbl */ - 0, - { 0 } -}, - -{ /* AArch64_TBL_ZZZ_D, AArch64_INS_TBL: tbl */ - 0, - { 0 } -}, - -{ /* AArch64_TBL_ZZZ_H, AArch64_INS_TBL: tbl */ - 0, - { 0 } -}, - -{ /* AArch64_TBL_ZZZ_S, AArch64_INS_TBL: tbl */ - 0, - { 0 } -}, - -{ /* AArch64_TBLv16i8Four, AArch64_INS_TBL: tbl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBLv16i8One, AArch64_INS_TBL: tbl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBLv16i8Three, AArch64_INS_TBL: tbl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBLv16i8Two, AArch64_INS_TBL: tbl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBLv8i8Four, AArch64_INS_TBL: tbl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBLv8i8One, AArch64_INS_TBL: tbl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBLv8i8Three, AArch64_INS_TBL: tbl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBLv8i8Two, AArch64_INS_TBL: tbl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBNZW, AArch64_INS_TBNZ: tbnz */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBNZX, AArch64_INS_TBNZ: tbnz */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBXv16i8Four, AArch64_INS_TBX: tbx */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBXv16i8One, AArch64_INS_TBX: tbx */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBXv16i8Three, AArch64_INS_TBX: tbx */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBXv16i8Two, AArch64_INS_TBX: tbx */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBXv8i8Four, AArch64_INS_TBX: tbx */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBXv8i8One, AArch64_INS_TBX: tbx */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBXv8i8Three, AArch64_INS_TBX: tbx */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBXv8i8Two, AArch64_INS_TBX: tbx */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBZW, AArch64_INS_TBZ: tbz */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TBZX, AArch64_INS_TBZ: tbz */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN1_PPP_B, AArch64_INS_TRN1: trn1 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN1_PPP_D, AArch64_INS_TRN1: trn1 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN1_PPP_H, AArch64_INS_TRN1: trn1 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN1_PPP_S, AArch64_INS_TRN1: trn1 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN1_ZZZ_B, AArch64_INS_TRN1: trn1 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN1_ZZZ_D, AArch64_INS_TRN1: trn1 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN1_ZZZ_H, AArch64_INS_TRN1: trn1 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN1_ZZZ_S, AArch64_INS_TRN1: trn1 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN1v16i8, AArch64_INS_TRN1: trn1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN1v2i32, AArch64_INS_TRN1: trn1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN1v2i64, AArch64_INS_TRN1: trn1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN1v4i16, AArch64_INS_TRN1: trn1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN1v4i32, AArch64_INS_TRN1: trn1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN1v8i16, AArch64_INS_TRN1: trn1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN1v8i8, AArch64_INS_TRN1: trn1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN2_PPP_B, AArch64_INS_TRN2: trn2 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN2_PPP_D, AArch64_INS_TRN2: trn2 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN2_PPP_H, AArch64_INS_TRN2: trn2 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN2_PPP_S, AArch64_INS_TRN2: trn2 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN2_ZZZ_B, AArch64_INS_TRN2: trn2 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN2_ZZZ_D, AArch64_INS_TRN2: trn2 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN2_ZZZ_H, AArch64_INS_TRN2: trn2 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN2_ZZZ_S, AArch64_INS_TRN2: trn2 */ - 0, - { 0 } -}, - -{ /* AArch64_TRN2v16i8, AArch64_INS_TRN2: trn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN2v2i32, AArch64_INS_TRN2: trn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN2v2i64, AArch64_INS_TRN2: trn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN2v4i16, AArch64_INS_TRN2: trn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN2v4i32, AArch64_INS_TRN2: trn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN2v8i16, AArch64_INS_TRN2: trn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TRN2v8i8, AArch64_INS_TRN2: trn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_TSB, AArch64_INS_TSB: tsb */ - 0, - { 0 } -}, - -{ /* AArch64_UABALv16i8_v8i16, AArch64_INS_UABAL2: uabal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABALv2i32_v2i64, AArch64_INS_UABAL: uabal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABALv4i16_v4i32, AArch64_INS_UABAL: uabal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABALv4i32_v2i64, AArch64_INS_UABAL2: uabal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABALv8i16_v4i32, AArch64_INS_UABAL2: uabal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABALv8i8_v8i16, AArch64_INS_UABAL: uabal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABAv16i8, AArch64_INS_UABA: uaba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABAv2i32, AArch64_INS_UABA: uaba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABAv4i16, AArch64_INS_UABA: uaba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABAv4i32, AArch64_INS_UABA: uaba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABAv8i16, AArch64_INS_UABA: uaba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABAv8i8, AArch64_INS_UABA: uaba */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDLv16i8_v8i16, AArch64_INS_UABDL2: uabdl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDLv2i32_v2i64, AArch64_INS_UABDL: uabdl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDLv4i16_v4i32, AArch64_INS_UABDL: uabdl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDLv4i32_v2i64, AArch64_INS_UABDL2: uabdl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDLv8i16_v4i32, AArch64_INS_UABDL2: uabdl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDLv8i8_v8i16, AArch64_INS_UABDL: uabdl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABD_ZPmZ_B, AArch64_INS_UABD: uabd */ - 0, - { 0 } -}, - -{ /* AArch64_UABD_ZPmZ_D, AArch64_INS_UABD: uabd */ - 0, - { 0 } -}, - -{ /* AArch64_UABD_ZPmZ_H, AArch64_INS_UABD: uabd */ - 0, - { 0 } -}, - -{ /* AArch64_UABD_ZPmZ_S, AArch64_INS_UABD: uabd */ - 0, - { 0 } -}, - -{ /* AArch64_UABDv16i8, AArch64_INS_UABD: uabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDv2i32, AArch64_INS_UABD: uabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDv4i16, AArch64_INS_UABD: uabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDv4i32, AArch64_INS_UABD: uabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDv8i16, AArch64_INS_UABD: uabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UABDv8i8, AArch64_INS_UABD: uabd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADALPv16i8_v8i16, AArch64_INS_UADALP: uadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADALPv2i32_v1i64, AArch64_INS_UADALP: uadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADALPv4i16_v2i32, AArch64_INS_UADALP: uadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADALPv4i32_v2i64, AArch64_INS_UADALP: uadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADALPv8i16_v4i32, AArch64_INS_UADALP: uadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADALPv8i8_v4i16, AArch64_INS_UADALP: uadalp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLPv16i8_v8i16, AArch64_INS_UADDLP: uaddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLPv2i32_v1i64, AArch64_INS_UADDLP: uaddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLPv4i16_v2i32, AArch64_INS_UADDLP: uaddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLPv4i32_v2i64, AArch64_INS_UADDLP: uaddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLPv8i16_v4i32, AArch64_INS_UADDLP: uaddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLPv8i8_v4i16, AArch64_INS_UADDLP: uaddlp */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLVv16i8v, AArch64_INS_UADDLV: uaddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLVv4i16v, AArch64_INS_UADDLV: uaddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLVv4i32v, AArch64_INS_UADDLV: uaddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLVv8i16v, AArch64_INS_UADDLV: uaddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLVv8i8v, AArch64_INS_UADDLV: uaddlv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLv16i8_v8i16, AArch64_INS_UADDL2: uaddl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLv2i32_v2i64, AArch64_INS_UADDL: uaddl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLv4i16_v4i32, AArch64_INS_UADDL: uaddl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLv4i32_v2i64, AArch64_INS_UADDL2: uaddl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLv8i16_v4i32, AArch64_INS_UADDL2: uaddl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDLv8i8_v8i16, AArch64_INS_UADDL: uaddl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDV_VPZ_B, AArch64_INS_UADDV: uaddv */ - 0, - { 0 } -}, - -{ /* AArch64_UADDV_VPZ_D, AArch64_INS_UADDV: uaddv */ - 0, - { 0 } -}, - -{ /* AArch64_UADDV_VPZ_H, AArch64_INS_UADDV: uaddv */ - 0, - { 0 } -}, - -{ /* AArch64_UADDV_VPZ_S, AArch64_INS_UADDV: uaddv */ - 0, - { 0 } -}, - -{ /* AArch64_UADDWv16i8_v8i16, AArch64_INS_UADDW2: uaddw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDWv2i32_v2i64, AArch64_INS_UADDW: uaddw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDWv4i16_v4i32, AArch64_INS_UADDW: uaddw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDWv4i32_v2i64, AArch64_INS_UADDW2: uaddw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDWv8i16_v4i32, AArch64_INS_UADDW2: uaddw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UADDWv8i8_v8i16, AArch64_INS_UADDW: uaddw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UBFMWri, AArch64_INS_LSR: lsr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UBFMXri, AArch64_INS_LSR: lsr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFSWDri, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFSWHri, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFSWSri, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFSXDri, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFSXHri, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFSXSri, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFUWDri, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFUWHri, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFUWSri, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFUXDri, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFUXHri, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFUXSri, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTF_ZPmZ_DtoD, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTF_ZPmZ_DtoH, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTF_ZPmZ_DtoS, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTF_ZPmZ_HtoH, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTF_ZPmZ_StoD, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTF_ZPmZ_StoH, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTF_ZPmZ_StoS, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFd, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFh, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFs, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFv1i16, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFv1i32, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFv1i64, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFv2f32, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFv2f64, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFv2i32_shift, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFv2i64_shift, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFv4f16, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFv4f32, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFv4i16_shift, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFv4i32_shift, AArch64_INS_UCVTF: ucvtf */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UCVTFv8f16, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UCVTFv8i16_shift, AArch64_INS_UCVTF: ucvtf */ - 0, - { 0 } -}, - -{ /* AArch64_UDIVR_ZPmZ_D, AArch64_INS_UDIVR: udivr */ - 0, - { 0 } -}, - -{ /* AArch64_UDIVR_ZPmZ_S, AArch64_INS_UDIVR: udivr */ - 0, - { 0 } -}, - -{ /* AArch64_UDIVWr, AArch64_INS_UDIV: udiv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UDIVXr, AArch64_INS_UDIV: udiv */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UDIV_ZPmZ_D, AArch64_INS_UDIV: udiv */ - 0, - { 0 } -}, - -{ /* AArch64_UDIV_ZPmZ_S, AArch64_INS_UDIV: udiv */ - 0, - { 0 } -}, - -{ /* AArch64_UDOT_ZZZI_D, AArch64_INS_UDOT: udot */ - 0, - { 0 } -}, - -{ /* AArch64_UDOT_ZZZI_S, AArch64_INS_UDOT: udot */ - 0, - { 0 } -}, - -{ /* AArch64_UDOT_ZZZ_D, AArch64_INS_UDOT: udot */ - 0, - { 0 } -}, - -{ /* AArch64_UDOT_ZZZ_S, AArch64_INS_UDOT: udot */ - 0, - { 0 } -}, - -{ /* AArch64_UDOTlanev16i8, AArch64_INS_UDOT: udot */ - 0, - { 0 } -}, - -{ /* AArch64_UDOTlanev8i8, AArch64_INS_UDOT: udot */ - 0, - { 0 } -}, - -{ /* AArch64_UDOTv16i8, AArch64_INS_UDOT: udot */ - 0, - { 0 } -}, - -{ /* AArch64_UDOTv8i8, AArch64_INS_UDOT: udot */ - 0, - { 0 } -}, - -{ /* AArch64_UHADDv16i8, AArch64_INS_UHADD: uhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHADDv2i32, AArch64_INS_UHADD: uhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHADDv4i16, AArch64_INS_UHADD: uhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHADDv4i32, AArch64_INS_UHADD: uhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHADDv8i16, AArch64_INS_UHADD: uhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHADDv8i8, AArch64_INS_UHADD: uhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHSUBv16i8, AArch64_INS_UHSUB: uhsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHSUBv2i32, AArch64_INS_UHSUB: uhsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHSUBv4i16, AArch64_INS_UHSUB: uhsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHSUBv4i32, AArch64_INS_UHSUB: uhsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHSUBv8i16, AArch64_INS_UHSUB: uhsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UHSUBv8i8, AArch64_INS_UHSUB: uhsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMADDLrrr, AArch64_INS_UMADDL: umaddl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXPv16i8, AArch64_INS_UMAXP: umaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXPv2i32, AArch64_INS_UMAXP: umaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXPv4i16, AArch64_INS_UMAXP: umaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXPv4i32, AArch64_INS_UMAXP: umaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXPv8i16, AArch64_INS_UMAXP: umaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXPv8i8, AArch64_INS_UMAXP: umaxp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXV_VPZ_B, AArch64_INS_UMAXV: umaxv */ - 0, - { 0 } -}, - -{ /* AArch64_UMAXV_VPZ_D, AArch64_INS_UMAXV: umaxv */ - 0, - { 0 } -}, - -{ /* AArch64_UMAXV_VPZ_H, AArch64_INS_UMAXV: umaxv */ - 0, - { 0 } -}, - -{ /* AArch64_UMAXV_VPZ_S, AArch64_INS_UMAXV: umaxv */ - 0, - { 0 } -}, - -{ /* AArch64_UMAXVv16i8v, AArch64_INS_UMAXV: umaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXVv4i16v, AArch64_INS_UMAXV: umaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXVv4i32v, AArch64_INS_UMAXV: umaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXVv8i16v, AArch64_INS_UMAXV: umaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXVv8i8v, AArch64_INS_UMAXV: umaxv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAX_ZI_B, AArch64_INS_UMAX: umax */ - 0, - { 0 } -}, - -{ /* AArch64_UMAX_ZI_D, AArch64_INS_UMAX: umax */ - 0, - { 0 } -}, - -{ /* AArch64_UMAX_ZI_H, AArch64_INS_UMAX: umax */ - 0, - { 0 } -}, - -{ /* AArch64_UMAX_ZI_S, AArch64_INS_UMAX: umax */ - 0, - { 0 } -}, - -{ /* AArch64_UMAX_ZPmZ_B, AArch64_INS_UMAX: umax */ - 0, - { 0 } -}, - -{ /* AArch64_UMAX_ZPmZ_D, AArch64_INS_UMAX: umax */ - 0, - { 0 } -}, - -{ /* AArch64_UMAX_ZPmZ_H, AArch64_INS_UMAX: umax */ - 0, - { 0 } -}, - -{ /* AArch64_UMAX_ZPmZ_S, AArch64_INS_UMAX: umax */ - 0, - { 0 } -}, - -{ /* AArch64_UMAXv16i8, AArch64_INS_UMAX: umax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXv2i32, AArch64_INS_UMAX: umax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXv4i16, AArch64_INS_UMAX: umax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXv4i32, AArch64_INS_UMAX: umax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXv8i16, AArch64_INS_UMAX: umax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMAXv8i8, AArch64_INS_UMAX: umax */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINPv16i8, AArch64_INS_UMINP: uminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINPv2i32, AArch64_INS_UMINP: uminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINPv4i16, AArch64_INS_UMINP: uminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINPv4i32, AArch64_INS_UMINP: uminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINPv8i16, AArch64_INS_UMINP: uminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINPv8i8, AArch64_INS_UMINP: uminp */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINV_VPZ_B, AArch64_INS_UMINV: uminv */ - 0, - { 0 } -}, - -{ /* AArch64_UMINV_VPZ_D, AArch64_INS_UMINV: uminv */ - 0, - { 0 } -}, - -{ /* AArch64_UMINV_VPZ_H, AArch64_INS_UMINV: uminv */ - 0, - { 0 } -}, - -{ /* AArch64_UMINV_VPZ_S, AArch64_INS_UMINV: uminv */ - 0, - { 0 } -}, - -{ /* AArch64_UMINVv16i8v, AArch64_INS_UMINV: uminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINVv4i16v, AArch64_INS_UMINV: uminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINVv4i32v, AArch64_INS_UMINV: uminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINVv8i16v, AArch64_INS_UMINV: uminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINVv8i8v, AArch64_INS_UMINV: uminv */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMIN_ZI_B, AArch64_INS_UMIN: umin */ - 0, - { 0 } -}, - -{ /* AArch64_UMIN_ZI_D, AArch64_INS_UMIN: umin */ - 0, - { 0 } -}, - -{ /* AArch64_UMIN_ZI_H, AArch64_INS_UMIN: umin */ - 0, - { 0 } -}, - -{ /* AArch64_UMIN_ZI_S, AArch64_INS_UMIN: umin */ - 0, - { 0 } -}, - -{ /* AArch64_UMIN_ZPmZ_B, AArch64_INS_UMIN: umin */ - 0, - { 0 } -}, - -{ /* AArch64_UMIN_ZPmZ_D, AArch64_INS_UMIN: umin */ - 0, - { 0 } -}, - -{ /* AArch64_UMIN_ZPmZ_H, AArch64_INS_UMIN: umin */ - 0, - { 0 } -}, - -{ /* AArch64_UMIN_ZPmZ_S, AArch64_INS_UMIN: umin */ - 0, - { 0 } -}, - -{ /* AArch64_UMINv16i8, AArch64_INS_UMIN: umin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINv2i32, AArch64_INS_UMIN: umin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINv4i16, AArch64_INS_UMIN: umin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINv4i32, AArch64_INS_UMIN: umin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINv8i16, AArch64_INS_UMIN: umin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMINv8i8, AArch64_INS_UMIN: umin */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv16i8_v8i16, AArch64_INS_UMLAL2: umlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv2i32_indexed, AArch64_INS_UMLAL: umlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv2i32_v2i64, AArch64_INS_UMLAL: umlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv4i16_indexed, AArch64_INS_UMLAL: umlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv4i16_v4i32, AArch64_INS_UMLAL: umlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv4i32_indexed, AArch64_INS_UMLAL2: umlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv4i32_v2i64, AArch64_INS_UMLAL2: umlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv8i16_indexed, AArch64_INS_UMLAL2: umlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv8i16_v4i32, AArch64_INS_UMLAL2: umlal2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLALv8i8_v8i16, AArch64_INS_UMLAL: umlal */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv16i8_v8i16, AArch64_INS_UMLSL2: umlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv2i32_indexed, AArch64_INS_UMLSL: umlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv2i32_v2i64, AArch64_INS_UMLSL: umlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv4i16_indexed, AArch64_INS_UMLSL: umlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv4i16_v4i32, AArch64_INS_UMLSL: umlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv4i32_indexed, AArch64_INS_UMLSL2: umlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv4i32_v2i64, AArch64_INS_UMLSL2: umlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv8i16_indexed, AArch64_INS_UMLSL2: umlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv8i16_v4i32, AArch64_INS_UMLSL2: umlsl2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMLSLv8i8_v8i16, AArch64_INS_UMLSL: umlsl */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMOVvi16, AArch64_INS_UMOV: umov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMOVvi32, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMOVvi64, AArch64_INS_MOV: mov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMOVvi8, AArch64_INS_UMOV: umov */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMSUBLrrr, AArch64_INS_UMNEGL: umnegl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULH_ZPmZ_B, AArch64_INS_UMULH: umulh */ - 0, - { 0 } -}, - -{ /* AArch64_UMULH_ZPmZ_D, AArch64_INS_UMULH: umulh */ - 0, - { 0 } -}, - -{ /* AArch64_UMULH_ZPmZ_H, AArch64_INS_UMULH: umulh */ - 0, - { 0 } -}, - -{ /* AArch64_UMULH_ZPmZ_S, AArch64_INS_UMULH: umulh */ - 0, - { 0 } -}, - -{ /* AArch64_UMULHrr, AArch64_INS_UMULH: umulh */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv16i8_v8i16, AArch64_INS_UMULL2: umull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv2i32_indexed, AArch64_INS_UMULL: umull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv2i32_v2i64, AArch64_INS_UMULL: umull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv4i16_indexed, AArch64_INS_UMULL: umull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv4i16_v4i32, AArch64_INS_UMULL: umull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv4i32_indexed, AArch64_INS_UMULL2: umull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv4i32_v2i64, AArch64_INS_UMULL2: umull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv8i16_indexed, AArch64_INS_UMULL2: umull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv8i16_v4i32, AArch64_INS_UMULL2: umull2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UMULLv8i8_v8i16, AArch64_INS_UMULL: umull */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADD_ZI_B, AArch64_INS_UQADD: uqadd */ - 0, - { 0 } -}, - -{ /* AArch64_UQADD_ZI_D, AArch64_INS_UQADD: uqadd */ - 0, - { 0 } -}, - -{ /* AArch64_UQADD_ZI_H, AArch64_INS_UQADD: uqadd */ - 0, - { 0 } -}, - -{ /* AArch64_UQADD_ZI_S, AArch64_INS_UQADD: uqadd */ - 0, - { 0 } -}, - -{ /* AArch64_UQADD_ZZZ_B, AArch64_INS_UQADD: uqadd */ - 0, - { 0 } -}, - -{ /* AArch64_UQADD_ZZZ_D, AArch64_INS_UQADD: uqadd */ - 0, - { 0 } -}, - -{ /* AArch64_UQADD_ZZZ_H, AArch64_INS_UQADD: uqadd */ - 0, - { 0 } -}, - -{ /* AArch64_UQADD_ZZZ_S, AArch64_INS_UQADD: uqadd */ - 0, - { 0 } -}, - -{ /* AArch64_UQADDv16i8, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv1i16, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv1i32, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv1i64, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv1i8, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv2i32, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv2i64, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv4i16, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv4i32, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv8i16, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQADDv8i8, AArch64_INS_UQADD: uqadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQDECB_WPiI, AArch64_INS_UQDECB: uqdecb */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECB_XPiI, AArch64_INS_UQDECB: uqdecb */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECD_WPiI, AArch64_INS_UQDECD: uqdecd */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECD_XPiI, AArch64_INS_UQDECD: uqdecd */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECD_ZPiI, AArch64_INS_UQDECD: uqdecd */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECH_WPiI, AArch64_INS_UQDECH: uqdech */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECH_XPiI, AArch64_INS_UQDECH: uqdech */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECH_ZPiI, AArch64_INS_UQDECH: uqdech */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_WP_B, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_WP_D, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_WP_H, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_WP_S, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_XP_B, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_XP_D, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_XP_H, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_XP_S, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_ZP_D, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_ZP_H, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECP_ZP_S, AArch64_INS_UQDECP: uqdecp */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECW_WPiI, AArch64_INS_UQDECW: uqdecw */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECW_XPiI, AArch64_INS_UQDECW: uqdecw */ - 0, - { 0 } -}, - -{ /* AArch64_UQDECW_ZPiI, AArch64_INS_UQDECW: uqdecw */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCB_WPiI, AArch64_INS_UQINCB: uqincb */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCB_XPiI, AArch64_INS_UQINCB: uqincb */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCD_WPiI, AArch64_INS_UQINCD: uqincd */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCD_XPiI, AArch64_INS_UQINCD: uqincd */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCD_ZPiI, AArch64_INS_UQINCD: uqincd */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCH_WPiI, AArch64_INS_UQINCH: uqinch */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCH_XPiI, AArch64_INS_UQINCH: uqinch */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCH_ZPiI, AArch64_INS_UQINCH: uqinch */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_WP_B, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_WP_D, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_WP_H, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_WP_S, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_XP_B, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_XP_D, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_XP_H, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_XP_S, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_ZP_D, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_ZP_H, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCP_ZP_S, AArch64_INS_UQINCP: uqincp */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCW_WPiI, AArch64_INS_UQINCW: uqincw */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCW_XPiI, AArch64_INS_UQINCW: uqincw */ - 0, - { 0 } -}, - -{ /* AArch64_UQINCW_ZPiI, AArch64_INS_UQINCW: uqincw */ - 0, - { 0 } -}, - -{ /* AArch64_UQRSHLv16i8, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv1i16, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv1i32, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv1i64, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv1i8, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv2i32, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv2i64, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv4i16, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv4i32, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv8i16, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHLv8i8, AArch64_INS_UQRSHL: uqrshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHRNb, AArch64_INS_UQRSHRN: uqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHRNh, AArch64_INS_UQRSHRN: uqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHRNs, AArch64_INS_UQRSHRN: uqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHRNv16i8_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHRNv2i32_shift, AArch64_INS_UQRSHRN: uqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHRNv4i16_shift, AArch64_INS_UQRSHRN: uqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHRNv4i32_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHRNv8i16_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQRSHRNv8i8_shift, AArch64_INS_UQRSHRN: uqrshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLb, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLd, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLh, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLs, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv16i8, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv16i8_shift, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv1i16, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv1i32, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv1i64, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv1i8, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv2i32, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv2i32_shift, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv2i64, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv2i64_shift, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv4i16, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv4i16_shift, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv4i32, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv4i32_shift, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv8i16, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv8i16_shift, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv8i8, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHLv8i8_shift, AArch64_INS_UQSHL: uqshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHRNb, AArch64_INS_UQSHRN: uqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHRNh, AArch64_INS_UQSHRN: uqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHRNs, AArch64_INS_UQSHRN: uqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHRNv16i8_shift, AArch64_INS_UQSHRN2: uqshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHRNv2i32_shift, AArch64_INS_UQSHRN: uqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHRNv4i16_shift, AArch64_INS_UQSHRN: uqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHRNv4i32_shift, AArch64_INS_UQSHRN2: uqshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHRNv8i16_shift, AArch64_INS_UQSHRN2: uqshrn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSHRNv8i8_shift, AArch64_INS_UQSHRN: uqshrn */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUB_ZI_B, AArch64_INS_UQSUB: uqsub */ - 0, - { 0 } -}, - -{ /* AArch64_UQSUB_ZI_D, AArch64_INS_UQSUB: uqsub */ - 0, - { 0 } -}, - -{ /* AArch64_UQSUB_ZI_H, AArch64_INS_UQSUB: uqsub */ - 0, - { 0 } -}, - -{ /* AArch64_UQSUB_ZI_S, AArch64_INS_UQSUB: uqsub */ - 0, - { 0 } -}, - -{ /* AArch64_UQSUB_ZZZ_B, AArch64_INS_UQSUB: uqsub */ - 0, - { 0 } -}, - -{ /* AArch64_UQSUB_ZZZ_D, AArch64_INS_UQSUB: uqsub */ - 0, - { 0 } -}, - -{ /* AArch64_UQSUB_ZZZ_H, AArch64_INS_UQSUB: uqsub */ - 0, - { 0 } -}, - -{ /* AArch64_UQSUB_ZZZ_S, AArch64_INS_UQSUB: uqsub */ - 0, - { 0 } -}, - -{ /* AArch64_UQSUBv16i8, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv1i16, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv1i32, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv1i64, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv1i8, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv2i32, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv2i64, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv4i16, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv4i32, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv8i16, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQSUBv8i8, AArch64_INS_UQSUB: uqsub */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQXTNv16i8, AArch64_INS_UQXTN2: uqxtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQXTNv1i16, AArch64_INS_UQXTN: uqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQXTNv1i32, AArch64_INS_UQXTN: uqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQXTNv1i8, AArch64_INS_UQXTN: uqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQXTNv2i32, AArch64_INS_UQXTN: uqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQXTNv4i16, AArch64_INS_UQXTN: uqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQXTNv4i32, AArch64_INS_UQXTN2: uqxtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQXTNv8i16, AArch64_INS_UQXTN2: uqxtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_UQXTNv8i8, AArch64_INS_UQXTN: uqxtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_URECPEv2i32, AArch64_INS_URECPE: urecpe */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_URECPEv4i32, AArch64_INS_URECPE: urecpe */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_URHADDv16i8, AArch64_INS_URHADD: urhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URHADDv2i32, AArch64_INS_URHADD: urhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URHADDv4i16, AArch64_INS_URHADD: urhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URHADDv4i32, AArch64_INS_URHADD: urhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URHADDv8i16, AArch64_INS_URHADD: urhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URHADDv8i8, AArch64_INS_URHADD: urhadd */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHLv16i8, AArch64_INS_URSHL: urshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHLv1i64, AArch64_INS_URSHL: urshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHLv2i32, AArch64_INS_URSHL: urshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHLv2i64, AArch64_INS_URSHL: urshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHLv4i16, AArch64_INS_URSHL: urshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHLv4i32, AArch64_INS_URSHL: urshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHLv8i16, AArch64_INS_URSHL: urshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHLv8i8, AArch64_INS_URSHL: urshl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHRd, AArch64_INS_URSHR: urshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHRv16i8_shift, AArch64_INS_URSHR: urshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHRv2i32_shift, AArch64_INS_URSHR: urshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHRv2i64_shift, AArch64_INS_URSHR: urshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHRv4i16_shift, AArch64_INS_URSHR: urshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHRv4i32_shift, AArch64_INS_URSHR: urshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHRv8i16_shift, AArch64_INS_URSHR: urshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSHRv8i8_shift, AArch64_INS_URSHR: urshr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSQRTEv2i32, AArch64_INS_URSQRTE: ursqrte */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSQRTEv4i32, AArch64_INS_URSQRTE: ursqrte */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSRAd, AArch64_INS_URSRA: ursra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSRAv16i8_shift, AArch64_INS_URSRA: ursra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSRAv2i32_shift, AArch64_INS_URSRA: ursra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSRAv2i64_shift, AArch64_INS_URSRA: ursra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSRAv4i16_shift, AArch64_INS_URSRA: ursra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSRAv4i32_shift, AArch64_INS_URSRA: ursra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSRAv8i16_shift, AArch64_INS_URSRA: ursra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_URSRAv8i8_shift, AArch64_INS_URSRA: ursra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLLv16i8_shift, AArch64_INS_USHLL2: ushll2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLLv2i32_shift, AArch64_INS_USHLL: ushll */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLLv4i16_shift, AArch64_INS_USHLL: ushll */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLLv4i32_shift, AArch64_INS_USHLL2: ushll2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLLv8i16_shift, AArch64_INS_USHLL2: ushll2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLLv8i8_shift, AArch64_INS_USHLL: ushll */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLv16i8, AArch64_INS_USHL: ushl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLv1i64, AArch64_INS_USHL: ushl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLv2i32, AArch64_INS_USHL: ushl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLv2i64, AArch64_INS_USHL: ushl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLv4i16, AArch64_INS_USHL: ushl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLv4i32, AArch64_INS_USHL: ushl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLv8i16, AArch64_INS_USHL: ushl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHLv8i8, AArch64_INS_USHL: ushl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHRd, AArch64_INS_USHR: ushr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHRv16i8_shift, AArch64_INS_USHR: ushr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHRv2i32_shift, AArch64_INS_USHR: ushr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHRv2i64_shift, AArch64_INS_USHR: ushr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHRv4i16_shift, AArch64_INS_USHR: ushr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHRv4i32_shift, AArch64_INS_USHR: ushr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHRv8i16_shift, AArch64_INS_USHR: ushr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USHRv8i8_shift, AArch64_INS_USHR: ushr */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv16i8, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv1i16, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv1i32, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv1i64, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv1i8, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv2i32, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv2i64, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv4i16, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv4i32, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv8i16, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USQADDv8i8, AArch64_INS_USQADD: usqadd */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USRAd, AArch64_INS_USRA: usra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USRAv16i8_shift, AArch64_INS_USRA: usra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USRAv2i32_shift, AArch64_INS_USRA: usra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USRAv2i64_shift, AArch64_INS_USRA: usra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USRAv4i16_shift, AArch64_INS_USRA: usra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USRAv4i32_shift, AArch64_INS_USRA: usra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USRAv8i16_shift, AArch64_INS_USRA: usra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USRAv8i8_shift, AArch64_INS_USRA: usra */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBLv16i8_v8i16, AArch64_INS_USUBL2: usubl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBLv2i32_v2i64, AArch64_INS_USUBL: usubl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBLv4i16_v4i32, AArch64_INS_USUBL: usubl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBLv4i32_v2i64, AArch64_INS_USUBL2: usubl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBLv8i16_v4i32, AArch64_INS_USUBL2: usubl2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBLv8i8_v8i16, AArch64_INS_USUBL: usubl */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBWv16i8_v8i16, AArch64_INS_USUBW2: usubw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBWv2i32_v2i64, AArch64_INS_USUBW: usubw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBWv4i16_v4i32, AArch64_INS_USUBW: usubw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBWv4i32_v2i64, AArch64_INS_USUBW2: usubw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBWv8i16_v4i32, AArch64_INS_USUBW2: usubw2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_USUBWv8i8_v8i16, AArch64_INS_USUBW: usubw */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UUNPKHI_ZZ_D, AArch64_INS_UUNPKHI: uunpkhi */ - 0, - { 0 } -}, - -{ /* AArch64_UUNPKHI_ZZ_H, AArch64_INS_UUNPKHI: uunpkhi */ - 0, - { 0 } -}, - -{ /* AArch64_UUNPKHI_ZZ_S, AArch64_INS_UUNPKHI: uunpkhi */ - 0, - { 0 } -}, - -{ /* AArch64_UUNPKLO_ZZ_D, AArch64_INS_UUNPKLO: uunpklo */ - 0, - { 0 } -}, - -{ /* AArch64_UUNPKLO_ZZ_H, AArch64_INS_UUNPKLO: uunpklo */ - 0, - { 0 } -}, - -{ /* AArch64_UUNPKLO_ZZ_S, AArch64_INS_UUNPKLO: uunpklo */ - 0, - { 0 } -}, - -{ /* AArch64_UXTB_ZPmZ_D, AArch64_INS_UXTB: uxtb */ - 0, - { 0 } -}, - -{ /* AArch64_UXTB_ZPmZ_H, AArch64_INS_UXTB: uxtb */ - 0, - { 0 } -}, - -{ /* AArch64_UXTB_ZPmZ_S, AArch64_INS_UXTB: uxtb */ - 0, - { 0 } -}, - -{ /* AArch64_UXTH_ZPmZ_D, AArch64_INS_UXTH: uxth */ - 0, - { 0 } -}, - -{ /* AArch64_UXTH_ZPmZ_S, AArch64_INS_UXTH: uxth */ - 0, - { 0 } -}, - -{ /* AArch64_UXTW_ZPmZ_D, AArch64_INS_UXTW: uxtw */ - 0, - { 0 } -}, - -{ /* AArch64_UZP1_PPP_B, AArch64_INS_UZP1: uzp1 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP1_PPP_D, AArch64_INS_UZP1: uzp1 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP1_PPP_H, AArch64_INS_UZP1: uzp1 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP1_PPP_S, AArch64_INS_UZP1: uzp1 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP1_ZZZ_B, AArch64_INS_UZP1: uzp1 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP1_ZZZ_D, AArch64_INS_UZP1: uzp1 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP1_ZZZ_H, AArch64_INS_UZP1: uzp1 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP1_ZZZ_S, AArch64_INS_UZP1: uzp1 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP1v16i8, AArch64_INS_UZP1: uzp1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP1v2i32, AArch64_INS_UZP1: uzp1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP1v2i64, AArch64_INS_UZP1: uzp1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP1v4i16, AArch64_INS_UZP1: uzp1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP1v4i32, AArch64_INS_UZP1: uzp1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP1v8i16, AArch64_INS_UZP1: uzp1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP1v8i8, AArch64_INS_UZP1: uzp1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP2_PPP_B, AArch64_INS_UZP2: uzp2 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP2_PPP_D, AArch64_INS_UZP2: uzp2 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP2_PPP_H, AArch64_INS_UZP2: uzp2 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP2_PPP_S, AArch64_INS_UZP2: uzp2 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP2_ZZZ_B, AArch64_INS_UZP2: uzp2 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP2_ZZZ_D, AArch64_INS_UZP2: uzp2 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP2_ZZZ_H, AArch64_INS_UZP2: uzp2 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP2_ZZZ_S, AArch64_INS_UZP2: uzp2 */ - 0, - { 0 } -}, - -{ /* AArch64_UZP2v16i8, AArch64_INS_UZP2: uzp2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP2v2i32, AArch64_INS_UZP2: uzp2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP2v2i64, AArch64_INS_UZP2: uzp2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP2v4i16, AArch64_INS_UZP2: uzp2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP2v4i32, AArch64_INS_UZP2: uzp2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP2v8i16, AArch64_INS_UZP2: uzp2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_UZP2v8i8, AArch64_INS_UZP2: uzp2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_WHILELE_PWW_B, AArch64_INS_WHILELE: whilele */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELE_PWW_D, AArch64_INS_WHILELE: whilele */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELE_PWW_H, AArch64_INS_WHILELE: whilele */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELE_PWW_S, AArch64_INS_WHILELE: whilele */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELE_PXX_B, AArch64_INS_WHILELE: whilele */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELE_PXX_D, AArch64_INS_WHILELE: whilele */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELE_PXX_H, AArch64_INS_WHILELE: whilele */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELE_PXX_S, AArch64_INS_WHILELE: whilele */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELO_PWW_B, AArch64_INS_WHILELO: whilelo */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELO_PWW_D, AArch64_INS_WHILELO: whilelo */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELO_PWW_H, AArch64_INS_WHILELO: whilelo */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELO_PWW_S, AArch64_INS_WHILELO: whilelo */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELO_PXX_B, AArch64_INS_WHILELO: whilelo */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELO_PXX_D, AArch64_INS_WHILELO: whilelo */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELO_PXX_H, AArch64_INS_WHILELO: whilelo */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELO_PXX_S, AArch64_INS_WHILELO: whilelo */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELS_PWW_B, AArch64_INS_WHILELS: whilels */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELS_PWW_D, AArch64_INS_WHILELS: whilels */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELS_PWW_H, AArch64_INS_WHILELS: whilels */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELS_PWW_S, AArch64_INS_WHILELS: whilels */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELS_PXX_B, AArch64_INS_WHILELS: whilels */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELS_PXX_D, AArch64_INS_WHILELS: whilels */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELS_PXX_H, AArch64_INS_WHILELS: whilels */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELS_PXX_S, AArch64_INS_WHILELS: whilels */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELT_PWW_B, AArch64_INS_WHILELT: whilelt */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELT_PWW_D, AArch64_INS_WHILELT: whilelt */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELT_PWW_H, AArch64_INS_WHILELT: whilelt */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELT_PWW_S, AArch64_INS_WHILELT: whilelt */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELT_PXX_B, AArch64_INS_WHILELT: whilelt */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELT_PXX_D, AArch64_INS_WHILELT: whilelt */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELT_PXX_H, AArch64_INS_WHILELT: whilelt */ - 0, - { 0 } -}, - -{ /* AArch64_WHILELT_PXX_S, AArch64_INS_WHILELT: whilelt */ - 0, - { 0 } -}, - -{ /* AArch64_WRFFR, AArch64_INS_WRFFR: wrffr */ - 0, - { 0 } -}, - -{ /* AArch64_XAR, AArch64_INS_XAR: xar */ - 0, - { 0 } -}, - -{ /* AArch64_XPACD, AArch64_INS_XPACD: xpacd */ - 0, - { 0 } -}, - -{ /* AArch64_XPACI, AArch64_INS_XPACI: xpaci */ - 0, - { 0 } -}, - -{ /* AArch64_XPACLRI, AArch64_INS_XPACLRI: xpaclri */ - 0, - { 0 } -}, - -{ /* AArch64_XTNv16i8, AArch64_INS_XTN2: xtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_XTNv2i32, AArch64_INS_XTN: xtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_XTNv4i16, AArch64_INS_XTN: xtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_XTNv4i32, AArch64_INS_XTN2: xtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_XTNv8i16, AArch64_INS_XTN2: xtn2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_XTNv8i8, AArch64_INS_XTN: xtn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP1_PPP_B, AArch64_INS_ZIP1: zip1 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP1_PPP_D, AArch64_INS_ZIP1: zip1 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP1_PPP_H, AArch64_INS_ZIP1: zip1 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP1_PPP_S, AArch64_INS_ZIP1: zip1 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP1_ZZZ_B, AArch64_INS_ZIP1: zip1 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP1_ZZZ_D, AArch64_INS_ZIP1: zip1 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP1_ZZZ_H, AArch64_INS_ZIP1: zip1 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP1_ZZZ_S, AArch64_INS_ZIP1: zip1 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP1v16i8, AArch64_INS_ZIP1: zip1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP1v2i32, AArch64_INS_ZIP1: zip1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP1v2i64, AArch64_INS_ZIP1: zip1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP1v4i16, AArch64_INS_ZIP1: zip1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP1v4i32, AArch64_INS_ZIP1: zip1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP1v8i16, AArch64_INS_ZIP1: zip1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP1v8i8, AArch64_INS_ZIP1: zip1 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP2_PPP_B, AArch64_INS_ZIP2: zip2 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP2_PPP_D, AArch64_INS_ZIP2: zip2 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP2_PPP_H, AArch64_INS_ZIP2: zip2 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP2_PPP_S, AArch64_INS_ZIP2: zip2 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP2_ZZZ_B, AArch64_INS_ZIP2: zip2 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP2_ZZZ_D, AArch64_INS_ZIP2: zip2 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP2_ZZZ_H, AArch64_INS_ZIP2: zip2 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP2_ZZZ_S, AArch64_INS_ZIP2: zip2 */ - 0, - { 0 } -}, - -{ /* AArch64_ZIP2v16i8, AArch64_INS_ZIP2: zip2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP2v2i32, AArch64_INS_ZIP2: zip2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP2v2i64, AArch64_INS_ZIP2: zip2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP2v4i16, AArch64_INS_ZIP2: zip2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP2v4i32, AArch64_INS_ZIP2: zip2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP2v8i16, AArch64_INS_ZIP2: zip2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_ZIP2v8i8, AArch64_INS_ZIP2: zip2 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, - -{ /* AArch64_anonymous_1349, AArch64_INS_PFIRST: pfirst */ - 0, - { 0 } -}, + {/* AArch64_ABS_ZPmZ_D, AArch64_INS_ABS: abs */ + 0, + {0}}, + + {/* AArch64_ABS_ZPmZ_H, AArch64_INS_ABS: abs */ + 0, + {0}}, + + {/* AArch64_ABS_ZPmZ_S, AArch64_INS_ABS: abs */ + 0, + {0}}, + + {/* AArch64_ABSv16i8, AArch64_INS_ABS: abs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ABSv1i64, AArch64_INS_ABS: abs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ABSv2i32, AArch64_INS_ABS: abs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ABSv2i64, AArch64_INS_ABS: abs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ABSv4i16, AArch64_INS_ABS: abs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ABSv4i32, AArch64_INS_ABS: abs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ABSv8i16, AArch64_INS_ABS: abs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ABSv8i8, AArch64_INS_ABS: abs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ADCSWr, AArch64_INS_ADCS: adcs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADCSXr, AArch64_INS_ADCS: adcs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADCWr, AArch64_INS_ADC: adc */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADCXr, AArch64_INS_ADC: adc */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDHNv2i64_v2i32, AArch64_INS_ADDHN: addhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDHNv2i64_v4i32, AArch64_INS_ADDHN2: addhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDHNv4i32_v4i16, AArch64_INS_ADDHN: addhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDHNv4i32_v8i16, AArch64_INS_ADDHN2: addhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDHNv8i16_v16i8, AArch64_INS_ADDHN2: addhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDHNv8i16_v8i8, AArch64_INS_ADDHN: addhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDPL_XXI, AArch64_INS_ADDPL: addpl */ + 0, + {0}}, + + {/* AArch64_ADDPv16i8, AArch64_INS_ADDP: addp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDPv2i32, AArch64_INS_ADDP: addp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDPv2i64, AArch64_INS_ADDP: addp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDPv2i64p, AArch64_INS_ADDP: addp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ADDPv4i16, AArch64_INS_ADDP: addp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDPv4i32, AArch64_INS_ADDP: addp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDPv8i16, AArch64_INS_ADDP: addp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDPv8i8, AArch64_INS_ADDP: addp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDSWri, AArch64_INS_ADDS: adds */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDSWrs, AArch64_INS_ADDS: adds */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDSWrx, AArch64_INS_ADDS: adds */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDSXri, AArch64_INS_ADDS: adds */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDSXrs, AArch64_INS_ADDS: adds */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDSXrx, AArch64_INS_ADDS: adds */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDSXrx64, AArch64_INS_ADDS: adds */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDVL_XXI, AArch64_INS_ADDVL: addvl */ + 0, + {0}}, + + {/* AArch64_ADDVv16i8v, AArch64_INS_ADDV: addv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ADDVv4i16v, AArch64_INS_ADDV: addv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ADDVv4i32v, AArch64_INS_ADDV: addv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ADDVv8i16v, AArch64_INS_ADDV: addv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ADDVv8i8v, AArch64_INS_ADDV: addv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ADDWri, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDWrs, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDWrx, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDXri, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDXrs, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDXrx, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDXrx64, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADD_ZI_B, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZI_D, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZI_H, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZI_S, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZPmZ_B, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZPmZ_D, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZPmZ_H, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZPmZ_S, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZZZ_B, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZZZ_D, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZZZ_H, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADD_ZZZ_S, AArch64_INS_ADD: add */ + 0, + {0}}, + + {/* AArch64_ADDv16i8, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDv1i64, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDv2i32, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDv2i64, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDv4i16, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDv4i32, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDv8i16, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADDv8i8, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ADR, AArch64_INS_ADR: adr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ADRP, AArch64_INS_ADRP: adrp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ADR_LSL_ZZZ_D_0, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_LSL_ZZZ_D_1, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_LSL_ZZZ_D_2, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_LSL_ZZZ_D_3, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_LSL_ZZZ_S_0, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_LSL_ZZZ_S_1, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_LSL_ZZZ_S_2, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_LSL_ZZZ_S_3, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_SXTW_ZZZ_D_0, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_SXTW_ZZZ_D_1, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_SXTW_ZZZ_D_2, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_SXTW_ZZZ_D_3, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_UXTW_ZZZ_D_0, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_UXTW_ZZZ_D_1, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_UXTW_ZZZ_D_2, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_ADR_UXTW_ZZZ_D_3, AArch64_INS_ADR: adr */ + 0, + {0}}, + + {/* AArch64_AESDrr, AArch64_INS_AESD: aesd */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_AESErr, AArch64_INS_AESE: aese */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_AESIMCrr, AArch64_INS_AESIMC: aesimc */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_AESMCrr, AArch64_INS_AESMC: aesmc */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ANDSWri, AArch64_INS_ANDS: ands */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ANDSWrs, AArch64_INS_ANDS: ands */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ANDSXri, AArch64_INS_ANDS: ands */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ANDSXrs, AArch64_INS_ANDS: ands */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ANDS_PPzPP, AArch64_INS_ANDS: ands */ + 0, + {0}}, + + {/* AArch64_ANDV_VPZ_B, AArch64_INS_ANDV: andv */ + 0, + {0}}, + + {/* AArch64_ANDV_VPZ_D, AArch64_INS_ANDV: andv */ + 0, + {0}}, + + {/* AArch64_ANDV_VPZ_H, AArch64_INS_ANDV: andv */ + 0, + {0}}, + + {/* AArch64_ANDV_VPZ_S, AArch64_INS_ANDV: andv */ + 0, + {0}}, + + {/* AArch64_ANDWri, AArch64_INS_AND: and */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ANDWrs, AArch64_INS_AND: and */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ANDXri, AArch64_INS_AND: and */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ANDXrs, AArch64_INS_AND: and */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_AND_PPzPP, AArch64_INS_AND: and */ + 0, + {0}}, + + {/* AArch64_AND_ZI, AArch64_INS_AND: and */ + 0, + {0}}, + + {/* AArch64_AND_ZPmZ_B, AArch64_INS_AND: and */ + 0, + {0}}, + + {/* AArch64_AND_ZPmZ_D, AArch64_INS_AND: and */ + 0, + {0}}, + + {/* AArch64_AND_ZPmZ_H, AArch64_INS_AND: and */ + 0, + {0}}, + + {/* AArch64_AND_ZPmZ_S, AArch64_INS_AND: and */ + 0, + {0}}, + + {/* AArch64_AND_ZZZ, AArch64_INS_AND: and */ + 0, + {0}}, + + {/* AArch64_ANDv16i8, AArch64_INS_AND: and */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ANDv8i8, AArch64_INS_AND: and */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ASRD_ZPmI_B, AArch64_INS_ASRD: asrd */ + 0, + {0}}, + + {/* AArch64_ASRD_ZPmI_D, AArch64_INS_ASRD: asrd */ + 0, + {0}}, + + {/* AArch64_ASRD_ZPmI_H, AArch64_INS_ASRD: asrd */ + 0, + {0}}, + + {/* AArch64_ASRD_ZPmI_S, AArch64_INS_ASRD: asrd */ + 0, + {0}}, + + {/* AArch64_ASRR_ZPmZ_B, AArch64_INS_ASRR: asrr */ + 0, + {0}}, + + {/* AArch64_ASRR_ZPmZ_D, AArch64_INS_ASRR: asrr */ + 0, + {0}}, + + {/* AArch64_ASRR_ZPmZ_H, AArch64_INS_ASRR: asrr */ + 0, + {0}}, + + {/* AArch64_ASRR_ZPmZ_S, AArch64_INS_ASRR: asrr */ + 0, + {0}}, + + {/* AArch64_ASRVWr, AArch64_INS_ASR: asr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ASRVXr, AArch64_INS_ASR: asr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ASR_WIDE_ZPmZ_B, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_WIDE_ZPmZ_H, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_WIDE_ZPmZ_S, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_WIDE_ZZZ_B, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_WIDE_ZZZ_H, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_WIDE_ZZZ_S, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZPmI_B, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZPmI_D, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZPmI_H, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZPmI_S, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZPmZ_B, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZPmZ_D, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZPmZ_H, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZPmZ_S, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZZI_B, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZZI_D, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZZI_H, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_ASR_ZZI_S, AArch64_INS_ASR: asr */ + 0, + {0}}, + + {/* AArch64_AUTDA, AArch64_INS_AUTDA: autda */ + 0, + {0}}, + + {/* AArch64_AUTDB, AArch64_INS_AUTDB: autdb */ + 0, + {0}}, + + {/* AArch64_AUTDZA, AArch64_INS_AUTDZA: autdza */ + 0, + {0}}, + + {/* AArch64_AUTDZB, AArch64_INS_AUTDZB: autdzb */ + 0, + {0}}, + + {/* AArch64_AUTIA, AArch64_INS_AUTIA: autia */ + 0, + {0}}, + + {/* AArch64_AUTIA1716, AArch64_INS_AUTIA1716: autia1716 */ + 0, + {0}}, + + {/* AArch64_AUTIASP, AArch64_INS_AUTIASP: autiasp */ + 0, + {0}}, + + {/* AArch64_AUTIAZ, AArch64_INS_AUTIAZ: autiaz */ + 0, + {0}}, + + {/* AArch64_AUTIB, AArch64_INS_AUTIB: autib */ + 0, + {0}}, + + {/* AArch64_AUTIB1716, AArch64_INS_AUTIB1716: autib1716 */ + 0, + {0}}, + + {/* AArch64_AUTIBSP, AArch64_INS_AUTIBSP: autibsp */ + 0, + {0}}, + + {/* AArch64_AUTIBZ, AArch64_INS_AUTIBZ: autibz */ + 0, + {0}}, + + {/* AArch64_AUTIZA, AArch64_INS_AUTIZA: autiza */ + 0, + {0}}, + + {/* AArch64_AUTIZB, AArch64_INS_AUTIZB: autizb */ + 0, + {0}}, + + {/* AArch64_B, AArch64_INS_B: b */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_BCAX, AArch64_INS_BCAX: bcax */ + 0, + {0}}, + + {/* AArch64_BFMWri, AArch64_INS_BFM: bfm */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_BFMXri, AArch64_INS_BFM: bfm */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_BICSWrs, AArch64_INS_BICS: bics */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BICSXrs, AArch64_INS_BICS: bics */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BICS_PPzPP, AArch64_INS_BICS: bics */ + 0, + {0}}, + + {/* AArch64_BICWrs, AArch64_INS_BIC: bic */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BICXrs, AArch64_INS_BIC: bic */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BIC_PPzPP, AArch64_INS_BIC: bic */ + 0, + {0}}, + + {/* AArch64_BIC_ZPmZ_B, AArch64_INS_BIC: bic */ + 0, + {0}}, + + {/* AArch64_BIC_ZPmZ_D, AArch64_INS_BIC: bic */ + 0, + {0}}, + + {/* AArch64_BIC_ZPmZ_H, AArch64_INS_BIC: bic */ + 0, + {0}}, + + {/* AArch64_BIC_ZPmZ_S, AArch64_INS_BIC: bic */ + 0, + {0}}, + + {/* AArch64_BIC_ZZZ, AArch64_INS_BIC: bic */ + 0, + {0}}, + + {/* AArch64_BICv16i8, AArch64_INS_BIC: bic */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BICv2i32, AArch64_INS_BIC: bic */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_BICv4i16, AArch64_INS_BIC: bic */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_BICv4i32, AArch64_INS_BIC: bic */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_BICv8i16, AArch64_INS_BIC: bic */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_BICv8i8, AArch64_INS_BIC: bic */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_BIFv16i8, AArch64_INS_BIF: bif */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BIFv8i8, AArch64_INS_BIF: bif */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BITv16i8, AArch64_INS_BIT: bit */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BITv8i8, AArch64_INS_BIT: bit */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BL, AArch64_INS_BL: bl */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_BLR, AArch64_INS_BLR: blr */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_BLRAA, AArch64_INS_BLRAA: blraa */ + 0, + {0}}, + + {/* AArch64_BLRAAZ, AArch64_INS_BLRAAZ: blraaz */ + 0, + {0}}, + + {/* AArch64_BLRAB, AArch64_INS_BLRAB: blrab */ + 0, + {0}}, + + {/* AArch64_BLRABZ, AArch64_INS_BLRABZ: blrabz */ + 0, + {0}}, + + {/* AArch64_BR, AArch64_INS_BR: br */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_BRAA, AArch64_INS_BRAA: braa */ + 0, + {0}}, + + {/* AArch64_BRAAZ, AArch64_INS_BRAAZ: braaz */ + 0, + {0}}, + + {/* AArch64_BRAB, AArch64_INS_BRAB: brab */ + 0, + {0}}, + + {/* AArch64_BRABZ, AArch64_INS_BRABZ: brabz */ + 0, + {0}}, + + {/* AArch64_BRK, AArch64_INS_BRK: brk */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_BRKAS_PPzP, AArch64_INS_BRKAS: brkas */ + 0, + {0}}, + + {/* AArch64_BRKA_PPmP, AArch64_INS_BRKA: brka */ + 0, + {0}}, + + {/* AArch64_BRKA_PPzP, AArch64_INS_BRKA: brka */ + 0, + {0}}, + + {/* AArch64_BRKBS_PPzP, AArch64_INS_BRKBS: brkbs */ + 0, + {0}}, + + {/* AArch64_BRKB_PPmP, AArch64_INS_BRKB: brkb */ + 0, + {0}}, + + {/* AArch64_BRKB_PPzP, AArch64_INS_BRKB: brkb */ + 0, + {0}}, + + {/* AArch64_BRKNS_PPzP, AArch64_INS_BRKNS: brkns */ + 0, + {0}}, + + {/* AArch64_BRKN_PPzP, AArch64_INS_BRKN: brkn */ + 0, + {0}}, + + {/* AArch64_BRKPAS_PPzPP, AArch64_INS_BRKPAS: brkpas */ + 0, + {0}}, + + {/* AArch64_BRKPA_PPzPP, AArch64_INS_BRKPA: brkpa */ + 0, + {0}}, + + {/* AArch64_BRKPBS_PPzPP, AArch64_INS_BRKPBS: brkpbs */ + 0, + {0}}, + + {/* AArch64_BRKPB_PPzPP, AArch64_INS_BRKPB: brkpb */ + 0, + {0}}, + + {/* AArch64_BSLv16i8, AArch64_INS_BSL: bsl */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_BSLv8i8, AArch64_INS_BSL: bsl */ + 0, + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_Bcc, AArch64_INS_B: b */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_CASAB, AArch64_INS_CASAB: casab */ + 0, + {0}}, + + {/* AArch64_CASAH, AArch64_INS_CASAH: casah */ + 0, + {0}}, + + {/* AArch64_CASALB, AArch64_INS_CASALB: casalb */ + 0, + {0}}, + + {/* AArch64_CASALH, AArch64_INS_CASALH: casalh */ + 0, + {0}}, + + {/* AArch64_CASALW, AArch64_INS_CASAL: casal */ + 0, + {0}}, + + {/* AArch64_CASALX, AArch64_INS_CASAL: casal */ + 0, + {0}}, + + {/* AArch64_CASAW, AArch64_INS_CASA: casa */ + 0, + {0}}, + + {/* AArch64_CASAX, AArch64_INS_CASA: casa */ + 0, + {0}}, + + {/* AArch64_CASB, AArch64_INS_CASB: casb */ + 0, + {0}}, + + {/* AArch64_CASH, AArch64_INS_CASH: cash */ + 0, + {0}}, + + {/* AArch64_CASLB, AArch64_INS_CASLB: caslb */ + 0, + {0}}, + + {/* AArch64_CASLH, AArch64_INS_CASLH: caslh */ + 0, + {0}}, + + {/* AArch64_CASLW, AArch64_INS_CASL: casl */ + 0, + {0}}, + + {/* AArch64_CASLX, AArch64_INS_CASL: casl */ + 0, + {0}}, + + {/* AArch64_CASPALW, AArch64_INS_CASPAL: caspal */ + 0, + {0}}, + + {/* AArch64_CASPALX, AArch64_INS_CASPAL: caspal */ + 0, + {0}}, + + {/* AArch64_CASPAW, AArch64_INS_CASPA: caspa */ + 0, + {0}}, + + {/* AArch64_CASPAX, AArch64_INS_CASPA: caspa */ + 0, + {0}}, + + {/* AArch64_CASPLW, AArch64_INS_CASPL: caspl */ + 0, + {0}}, + + {/* AArch64_CASPLX, AArch64_INS_CASPL: caspl */ + 0, + {0}}, + + {/* AArch64_CASPW, AArch64_INS_CASP: casp */ + 0, + {0}}, + + {/* AArch64_CASPX, AArch64_INS_CASP: casp */ + 0, + {0}}, + + {/* AArch64_CASW, AArch64_INS_CAS: cas */ + 0, + {0}}, + + {/* AArch64_CASX, AArch64_INS_CAS: cas */ + 0, + {0}}, + + {/* AArch64_CBNZW, AArch64_INS_CBNZ: cbnz */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CBNZX, AArch64_INS_CBNZ: cbnz */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CBZW, AArch64_INS_CBZ: cbz */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CBZX, AArch64_INS_CBZ: cbz */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CCMNWi, AArch64_INS_CCMN: ccmn */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CCMNWr, AArch64_INS_CCMN: ccmn */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CCMNXi, AArch64_INS_CCMN: ccmn */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CCMNXr, AArch64_INS_CCMN: ccmn */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CCMPWi, AArch64_INS_CCMP: ccmp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CCMPWr, AArch64_INS_CCMP: ccmp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CCMPXi, AArch64_INS_CCMP: ccmp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CCMPXr, AArch64_INS_CCMP: ccmp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CFINV, AArch64_INS_CFINV: cfinv */ + 0, + {0}}, + + {/* AArch64_CLASTA_RPZ_B, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_RPZ_D, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_RPZ_H, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_RPZ_S, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_VPZ_B, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_VPZ_D, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_VPZ_H, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_VPZ_S, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_ZPZ_B, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_ZPZ_D, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_ZPZ_H, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTA_ZPZ_S, AArch64_INS_CLASTA: clasta */ + 0, + {0}}, + + {/* AArch64_CLASTB_RPZ_B, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_RPZ_D, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_RPZ_H, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_RPZ_S, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_VPZ_B, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_VPZ_D, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_VPZ_H, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_VPZ_S, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_ZPZ_B, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_ZPZ_D, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_ZPZ_H, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLASTB_ZPZ_S, AArch64_INS_CLASTB: clastb */ + 0, + {0}}, + + {/* AArch64_CLREX, AArch64_INS_CLREX: clrex */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_CLSWr, AArch64_INS_CLS: cls */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLSXr, AArch64_INS_CLS: cls */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLS_ZPmZ_B, AArch64_INS_CLS: cls */ + 0, + {0}}, + + {/* AArch64_CLS_ZPmZ_D, AArch64_INS_CLS: cls */ + 0, + {0}}, + + {/* AArch64_CLS_ZPmZ_H, AArch64_INS_CLS: cls */ + 0, + {0}}, + + {/* AArch64_CLS_ZPmZ_S, AArch64_INS_CLS: cls */ + 0, + {0}}, + + {/* AArch64_CLSv16i8, AArch64_INS_CLS: cls */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLSv2i32, AArch64_INS_CLS: cls */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLSv4i16, AArch64_INS_CLS: cls */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLSv4i32, AArch64_INS_CLS: cls */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLSv8i16, AArch64_INS_CLS: cls */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLSv8i8, AArch64_INS_CLS: cls */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLZWr, AArch64_INS_CLZ: clz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLZXr, AArch64_INS_CLZ: clz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLZ_ZPmZ_B, AArch64_INS_CLZ: clz */ + 0, + {0}}, + + {/* AArch64_CLZ_ZPmZ_D, AArch64_INS_CLZ: clz */ + 0, + {0}}, + + {/* AArch64_CLZ_ZPmZ_H, AArch64_INS_CLZ: clz */ + 0, + {0}}, + + {/* AArch64_CLZ_ZPmZ_S, AArch64_INS_CLZ: clz */ + 0, + {0}}, + + {/* AArch64_CLZv16i8, AArch64_INS_CLZ: clz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLZv2i32, AArch64_INS_CLZ: clz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLZv4i16, AArch64_INS_CLZ: clz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLZv4i32, AArch64_INS_CLZ: clz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLZv8i16, AArch64_INS_CLZ: clz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CLZv8i8, AArch64_INS_CLZ: clz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv16i8, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv16i8rz, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv1i64, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv1i64rz, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv2i32, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv2i32rz, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv2i64, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv2i64rz, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv4i16, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv4i16rz, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv4i32, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv4i32rz, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv8i16, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv8i16rz, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv8i8, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMEQv8i8rz, AArch64_INS_CMEQ: cmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv16i8, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv16i8rz, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv1i64, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv1i64rz, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv2i32, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv2i32rz, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv2i64, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv2i64rz, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv4i16, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv4i16rz, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv4i32, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv4i32rz, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv8i16, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv8i16rz, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv8i8, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGEv8i8rz, AArch64_INS_CMGE: cmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv16i8, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv16i8rz, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv1i64, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv1i64rz, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv2i32, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv2i32rz, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv2i64, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv2i64rz, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv4i16, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv4i16rz, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv4i32, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv4i32rz, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv8i16, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv8i16rz, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv8i8, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMGTv8i8rz, AArch64_INS_CMGT: cmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHIv16i8, AArch64_INS_CMHI: cmhi */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHIv1i64, AArch64_INS_CMHI: cmhi */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHIv2i32, AArch64_INS_CMHI: cmhi */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHIv2i64, AArch64_INS_CMHI: cmhi */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHIv4i16, AArch64_INS_CMHI: cmhi */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHIv4i32, AArch64_INS_CMHI: cmhi */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHIv8i16, AArch64_INS_CMHI: cmhi */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHIv8i8, AArch64_INS_CMHI: cmhi */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHSv16i8, AArch64_INS_CMHS: cmhs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHSv1i64, AArch64_INS_CMHS: cmhs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHSv2i32, AArch64_INS_CMHS: cmhs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHSv2i64, AArch64_INS_CMHS: cmhs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHSv4i16, AArch64_INS_CMHS: cmhs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHSv4i32, AArch64_INS_CMHS: cmhs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHSv8i16, AArch64_INS_CMHS: cmhs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMHSv8i8, AArch64_INS_CMHS: cmhs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLEv16i8rz, AArch64_INS_CMLE: cmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLEv1i64rz, AArch64_INS_CMLE: cmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLEv2i32rz, AArch64_INS_CMLE: cmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLEv2i64rz, AArch64_INS_CMLE: cmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLEv4i16rz, AArch64_INS_CMLE: cmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLEv4i32rz, AArch64_INS_CMLE: cmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLEv8i16rz, AArch64_INS_CMLE: cmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLEv8i8rz, AArch64_INS_CMLE: cmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLTv16i8rz, AArch64_INS_CMLT: cmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLTv1i64rz, AArch64_INS_CMLT: cmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLTv2i32rz, AArch64_INS_CMLT: cmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLTv2i64rz, AArch64_INS_CMLT: cmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLTv4i16rz, AArch64_INS_CMLT: cmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLTv4i32rz, AArch64_INS_CMLT: cmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLTv8i16rz, AArch64_INS_CMLT: cmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMLTv8i8rz, AArch64_INS_CMLT: cmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMPEQ_PPzZI_B, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_PPzZI_D, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_PPzZI_H, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_PPzZI_S, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_PPzZZ_B, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_PPzZZ_D, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_PPzZZ_H, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_PPzZZ_S, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_WIDE_PPzZZ_B, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_WIDE_PPzZZ_H, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPEQ_WIDE_PPzZZ_S, AArch64_INS_CMPEQ: cmpeq */ + 0, + {0}}, + + {/* AArch64_CMPGE_PPzZI_B, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_PPzZI_D, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_PPzZI_H, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_PPzZI_S, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_PPzZZ_B, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_PPzZZ_D, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_PPzZZ_H, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_PPzZZ_S, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_WIDE_PPzZZ_B, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_WIDE_PPzZZ_H, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGE_WIDE_PPzZZ_S, AArch64_INS_CMPGE: cmpge */ + 0, + {0}}, + + {/* AArch64_CMPGT_PPzZI_B, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_PPzZI_D, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_PPzZI_H, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_PPzZI_S, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_PPzZZ_B, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_PPzZZ_D, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_PPzZZ_H, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_PPzZZ_S, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_WIDE_PPzZZ_B, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_WIDE_PPzZZ_H, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPGT_WIDE_PPzZZ_S, AArch64_INS_CMPGT: cmpgt */ + 0, + {0}}, + + {/* AArch64_CMPHI_PPzZI_B, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_PPzZI_D, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_PPzZI_H, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_PPzZI_S, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_PPzZZ_B, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_PPzZZ_D, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_PPzZZ_H, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_PPzZZ_S, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_WIDE_PPzZZ_B, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_WIDE_PPzZZ_H, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHI_WIDE_PPzZZ_S, AArch64_INS_CMPHI: cmphi */ + 0, + {0}}, + + {/* AArch64_CMPHS_PPzZI_B, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_PPzZI_D, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_PPzZI_H, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_PPzZI_S, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_PPzZZ_B, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_PPzZZ_D, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_PPzZZ_H, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_PPzZZ_S, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_WIDE_PPzZZ_B, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_WIDE_PPzZZ_H, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPHS_WIDE_PPzZZ_S, AArch64_INS_CMPHS: cmphs */ + 0, + {0}}, + + {/* AArch64_CMPLE_PPzZI_B, AArch64_INS_CMPLE: cmple */ + 0, + {0}}, + + {/* AArch64_CMPLE_PPzZI_D, AArch64_INS_CMPLE: cmple */ + 0, + {0}}, + + {/* AArch64_CMPLE_PPzZI_H, AArch64_INS_CMPLE: cmple */ + 0, + {0}}, + + {/* AArch64_CMPLE_PPzZI_S, AArch64_INS_CMPLE: cmple */ + 0, + {0}}, + + {/* AArch64_CMPLE_WIDE_PPzZZ_B, AArch64_INS_CMPLE: cmple */ + 0, + {0}}, + + {/* AArch64_CMPLE_WIDE_PPzZZ_H, AArch64_INS_CMPLE: cmple */ + 0, + {0}}, + + {/* AArch64_CMPLE_WIDE_PPzZZ_S, AArch64_INS_CMPLE: cmple */ + 0, + {0}}, + + {/* AArch64_CMPLO_PPzZI_B, AArch64_INS_CMPLO: cmplo */ + 0, + {0}}, + + {/* AArch64_CMPLO_PPzZI_D, AArch64_INS_CMPLO: cmplo */ + 0, + {0}}, + + {/* AArch64_CMPLO_PPzZI_H, AArch64_INS_CMPLO: cmplo */ + 0, + {0}}, + + {/* AArch64_CMPLO_PPzZI_S, AArch64_INS_CMPLO: cmplo */ + 0, + {0}}, + + {/* AArch64_CMPLO_WIDE_PPzZZ_B, AArch64_INS_CMPLO: cmplo */ + 0, + {0}}, + + {/* AArch64_CMPLO_WIDE_PPzZZ_H, AArch64_INS_CMPLO: cmplo */ + 0, + {0}}, + + {/* AArch64_CMPLO_WIDE_PPzZZ_S, AArch64_INS_CMPLO: cmplo */ + 0, + {0}}, + + {/* AArch64_CMPLS_PPzZI_B, AArch64_INS_CMPLS: cmpls */ + 0, + {0}}, + + {/* AArch64_CMPLS_PPzZI_D, AArch64_INS_CMPLS: cmpls */ + 0, + {0}}, + + {/* AArch64_CMPLS_PPzZI_H, AArch64_INS_CMPLS: cmpls */ + 0, + {0}}, + + {/* AArch64_CMPLS_PPzZI_S, AArch64_INS_CMPLS: cmpls */ + 0, + {0}}, + + {/* AArch64_CMPLS_WIDE_PPzZZ_B, AArch64_INS_CMPLS: cmpls */ + 0, + {0}}, + + {/* AArch64_CMPLS_WIDE_PPzZZ_H, AArch64_INS_CMPLS: cmpls */ + 0, + {0}}, + + {/* AArch64_CMPLS_WIDE_PPzZZ_S, AArch64_INS_CMPLS: cmpls */ + 0, + {0}}, + + {/* AArch64_CMPLT_PPzZI_B, AArch64_INS_CMPLT: cmplt */ + 0, + {0}}, + + {/* AArch64_CMPLT_PPzZI_D, AArch64_INS_CMPLT: cmplt */ + 0, + {0}}, + + {/* AArch64_CMPLT_PPzZI_H, AArch64_INS_CMPLT: cmplt */ + 0, + {0}}, + + {/* AArch64_CMPLT_PPzZI_S, AArch64_INS_CMPLT: cmplt */ + 0, + {0}}, + + {/* AArch64_CMPLT_WIDE_PPzZZ_B, AArch64_INS_CMPLT: cmplt */ + 0, + {0}}, + + {/* AArch64_CMPLT_WIDE_PPzZZ_H, AArch64_INS_CMPLT: cmplt */ + 0, + {0}}, + + {/* AArch64_CMPLT_WIDE_PPzZZ_S, AArch64_INS_CMPLT: cmplt */ + 0, + {0}}, + + {/* AArch64_CMPNE_PPzZI_B, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_PPzZI_D, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_PPzZI_H, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_PPzZI_S, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_PPzZZ_B, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_PPzZZ_D, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_PPzZZ_H, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_PPzZZ_S, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_WIDE_PPzZZ_B, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_WIDE_PPzZZ_H, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMPNE_WIDE_PPzZZ_S, AArch64_INS_CMPNE: cmpne */ + 0, + {0}}, + + {/* AArch64_CMTSTv16i8, AArch64_INS_CMTST: cmtst */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMTSTv1i64, AArch64_INS_CMTST: cmtst */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMTSTv2i32, AArch64_INS_CMTST: cmtst */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMTSTv2i64, AArch64_INS_CMTST: cmtst */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMTSTv4i16, AArch64_INS_CMTST: cmtst */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMTSTv4i32, AArch64_INS_CMTST: cmtst */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMTSTv8i16, AArch64_INS_CMTST: cmtst */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CMTSTv8i8, AArch64_INS_CMTST: cmtst */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CNOT_ZPmZ_B, AArch64_INS_CNOT: cnot */ + 0, + {0}}, + + {/* AArch64_CNOT_ZPmZ_D, AArch64_INS_CNOT: cnot */ + 0, + {0}}, + + {/* AArch64_CNOT_ZPmZ_H, AArch64_INS_CNOT: cnot */ + 0, + {0}}, + + {/* AArch64_CNOT_ZPmZ_S, AArch64_INS_CNOT: cnot */ + 0, + {0}}, + + {/* AArch64_CNTB_XPiI, AArch64_INS_CNTB: cntb */ + 0, + {0}}, + + {/* AArch64_CNTD_XPiI, AArch64_INS_CNTD: cntd */ + 0, + {0}}, + + {/* AArch64_CNTH_XPiI, AArch64_INS_CNTH: cnth */ + 0, + {0}}, + + {/* AArch64_CNTP_XPP_B, AArch64_INS_CNTP: cntp */ + 0, + {0}}, + + {/* AArch64_CNTP_XPP_D, AArch64_INS_CNTP: cntp */ + 0, + {0}}, + + {/* AArch64_CNTP_XPP_H, AArch64_INS_CNTP: cntp */ + 0, + {0}}, + + {/* AArch64_CNTP_XPP_S, AArch64_INS_CNTP: cntp */ + 0, + {0}}, + + {/* AArch64_CNTW_XPiI, AArch64_INS_CNTW: cntw */ + 0, + {0}}, + + {/* AArch64_CNT_ZPmZ_B, AArch64_INS_CNT: cnt */ + 0, + {0}}, + + {/* AArch64_CNT_ZPmZ_D, AArch64_INS_CNT: cnt */ + 0, + {0}}, + + {/* AArch64_CNT_ZPmZ_H, AArch64_INS_CNT: cnt */ + 0, + {0}}, + + {/* AArch64_CNT_ZPmZ_S, AArch64_INS_CNT: cnt */ + 0, + {0}}, + + {/* AArch64_CNTv16i8, AArch64_INS_CNT: cnt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_CNTv8i8, AArch64_INS_CNT: cnt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_COMPACT_ZPZ_D, AArch64_INS_COMPACT: compact */ + 0, + {0}}, + + {/* AArch64_COMPACT_ZPZ_S, AArch64_INS_COMPACT: compact */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmI_B, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmI_D, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmI_H, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmI_S, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmR_B, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmR_D, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmR_H, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmR_S, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmV_B, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmV_D, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmV_H, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPmV_S, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPzI_B, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPzI_D, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPzI_H, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPY_ZPzI_S, AArch64_INS_CPY: cpy */ + 0, + {0}}, + + {/* AArch64_CPYi16, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CPYi32, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CPYi64, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CPYi8, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CRC32Brr, AArch64_INS_CRC32B: crc32b */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CRC32CBrr, AArch64_INS_CRC32CB: crc32cb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CRC32CHrr, AArch64_INS_CRC32CH: crc32ch */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CRC32CWrr, AArch64_INS_CRC32CW: crc32cw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CRC32CXrr, AArch64_INS_CRC32CX: crc32cx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CRC32Hrr, AArch64_INS_CRC32H: crc32h */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CRC32Wrr, AArch64_INS_CRC32W: crc32w */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CRC32Xrr, AArch64_INS_CRC32X: crc32x */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_CSELWr, AArch64_INS_CSEL: csel */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CSELXr, AArch64_INS_CSEL: csel */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CSINCWr, AArch64_INS_CINC: cinc */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CSINCXr, AArch64_INS_CINC: cinc */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CSINVWr, AArch64_INS_CINV: cinv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CSINVXr, AArch64_INS_CINV: cinv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CSNEGWr, AArch64_INS_CNEG: cneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CSNEGXr, AArch64_INS_CNEG: cneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_CTERMEQ_WW, AArch64_INS_CTERMEQ: ctermeq */ + 0, + {0}}, + + {/* AArch64_CTERMEQ_XX, AArch64_INS_CTERMEQ: ctermeq */ + 0, + {0}}, + + {/* AArch64_CTERMNE_WW, AArch64_INS_CTERMNE: ctermne */ + 0, + {0}}, + + {/* AArch64_CTERMNE_XX, AArch64_INS_CTERMNE: ctermne */ + 0, + {0}}, + + {/* AArch64_DCPS1, AArch64_INS_DCPS1: dcps1 */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_DCPS2, AArch64_INS_DCPS2: dcps2 */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_DCPS3, AArch64_INS_DCPS3: dcps3 */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_DECB_XPiI, AArch64_INS_DECB: decb */ + 0, + {0}}, + + {/* AArch64_DECD_XPiI, AArch64_INS_DECD: decd */ + 0, + {0}}, + + {/* AArch64_DECD_ZPiI, AArch64_INS_DECD: decd */ + 0, + {0}}, + + {/* AArch64_DECH_XPiI, AArch64_INS_DECH: dech */ + 0, + {0}}, + + {/* AArch64_DECH_ZPiI, AArch64_INS_DECH: dech */ + 0, + {0}}, + + {/* AArch64_DECP_XP_B, AArch64_INS_DECP: decp */ + 0, + {0}}, + + {/* AArch64_DECP_XP_D, AArch64_INS_DECP: decp */ + 0, + {0}}, + + {/* AArch64_DECP_XP_H, AArch64_INS_DECP: decp */ + 0, + {0}}, + + {/* AArch64_DECP_XP_S, AArch64_INS_DECP: decp */ + 0, + {0}}, + + {/* AArch64_DECP_ZP_D, AArch64_INS_DECP: decp */ + 0, + {0}}, + + {/* AArch64_DECP_ZP_H, AArch64_INS_DECP: decp */ + 0, + {0}}, + + {/* AArch64_DECP_ZP_S, AArch64_INS_DECP: decp */ + 0, + {0}}, + + {/* AArch64_DECW_XPiI, AArch64_INS_DECW: decw */ + 0, + {0}}, + + {/* AArch64_DECW_ZPiI, AArch64_INS_DECW: decw */ + 0, + {0}}, + + {/* AArch64_DMB, AArch64_INS_DMB: dmb */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_DRPS, AArch64_INS_DRPS: drps */ + 0, + {0}}, + + {/* AArch64_DSB, AArch64_INS_DSB: dsb */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_DUPM_ZI, AArch64_INS_DUPM: dupm */ + 0, + {0}}, + + {/* AArch64_DUP_ZI_B, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZI_D, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZI_H, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZI_S, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZR_B, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZR_D, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZR_H, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZR_S, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZZI_B, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZZI_D, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZZI_H, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZZI_Q, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUP_ZZI_S, AArch64_INS_DUP: dup */ + 0, + {0}}, + + {/* AArch64_DUPv16i8gpr, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_DUPv16i8lane, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_DUPv2i32gpr, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_DUPv2i32lane, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_DUPv2i64gpr, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_DUPv2i64lane, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_DUPv4i16gpr, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_DUPv4i16lane, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_DUPv4i32gpr, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_DUPv4i32lane, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_DUPv8i16gpr, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_DUPv8i16lane, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_DUPv8i8gpr, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_DUPv8i8lane, AArch64_INS_DUP: dup */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_EONWrs, AArch64_INS_EON: eon */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_EONXrs, AArch64_INS_EON: eon */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_EOR3, AArch64_INS_EOR3: eor3 */ + 0, + {0}}, + + {/* AArch64_EORS_PPzPP, AArch64_INS_EORS: eors */ + 0, + {0}}, + + {/* AArch64_EORV_VPZ_B, AArch64_INS_EORV: eorv */ + 0, + {0}}, + + {/* AArch64_EORV_VPZ_D, AArch64_INS_EORV: eorv */ + 0, + {0}}, + + {/* AArch64_EORV_VPZ_H, AArch64_INS_EORV: eorv */ + 0, + {0}}, + + {/* AArch64_EORV_VPZ_S, AArch64_INS_EORV: eorv */ + 0, + {0}}, + + {/* AArch64_EORWri, AArch64_INS_EON: eon */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_EORWrs, AArch64_INS_EOR: eor */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_EORXri, AArch64_INS_EON: eon */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_EORXrs, AArch64_INS_EOR: eor */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_EOR_PPzPP, AArch64_INS_EOR: eor */ + 0, + {0}}, + + {/* AArch64_EOR_ZI, AArch64_INS_EON: eon */ + 0, + {0}}, + + {/* AArch64_EOR_ZPmZ_B, AArch64_INS_EOR: eor */ + 0, + {0}}, + + {/* AArch64_EOR_ZPmZ_D, AArch64_INS_EOR: eor */ + 0, + {0}}, + + {/* AArch64_EOR_ZPmZ_H, AArch64_INS_EOR: eor */ + 0, + {0}}, + + {/* AArch64_EOR_ZPmZ_S, AArch64_INS_EOR: eor */ + 0, + {0}}, + + {/* AArch64_EOR_ZZZ, AArch64_INS_EOR: eor */ + 0, + {0}}, + + {/* AArch64_EORv16i8, AArch64_INS_EOR: eor */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_EORv8i8, AArch64_INS_EOR: eor */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ERET, AArch64_INS_ERET: eret */ + 0, + {0}}, + + {/* AArch64_ERETAA, AArch64_INS_ERETAA: eretaa */ + 0, + {0}}, + + {/* AArch64_ERETAB, AArch64_INS_ERETAB: eretab */ + 0, + {0}}, + + {/* AArch64_EXTRWrri, AArch64_INS_EXTR: extr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_EXTRXrri, AArch64_INS_EXTR: extr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_EXT_ZZI, AArch64_INS_EXT: ext */ + 0, + {0}}, + + {/* AArch64_EXTv16i8, AArch64_INS_EXT: ext */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_EXTv8i8, AArch64_INS_EXT: ext */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FABD16, AArch64_INS_FABD: fabd */ + 0, + {0}}, + + {/* AArch64_FABD32, AArch64_INS_FABD: fabd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FABD64, AArch64_INS_FABD: fabd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FABD_ZPmZ_D, AArch64_INS_FABD: fabd */ + 0, + {0}}, + + {/* AArch64_FABD_ZPmZ_H, AArch64_INS_FABD: fabd */ + 0, + {0}}, + + {/* AArch64_FABD_ZPmZ_S, AArch64_INS_FABD: fabd */ + 0, + {0}}, + + {/* AArch64_FABDv2f32, AArch64_INS_FABD: fabd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FABDv2f64, AArch64_INS_FABD: fabd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FABDv4f16, AArch64_INS_FABD: fabd */ + 0, + {0}}, + + {/* AArch64_FABDv4f32, AArch64_INS_FABD: fabd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FABDv8f16, AArch64_INS_FABD: fabd */ + 0, + {0}}, + + {/* AArch64_FABSDr, AArch64_INS_FABS: fabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FABSHr, AArch64_INS_FABS: fabs */ + 0, + {0}}, + + {/* AArch64_FABSSr, AArch64_INS_FABS: fabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FABS_ZPmZ_D, AArch64_INS_FABS: fabs */ + 0, + {0}}, + + {/* AArch64_FABS_ZPmZ_H, AArch64_INS_FABS: fabs */ + 0, + {0}}, + + {/* AArch64_FABS_ZPmZ_S, AArch64_INS_FABS: fabs */ + 0, + {0}}, + + {/* AArch64_FABSv2f32, AArch64_INS_FABS: fabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FABSv2f64, AArch64_INS_FABS: fabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FABSv4f16, AArch64_INS_FABS: fabs */ + 0, + {0}}, + + {/* AArch64_FABSv4f32, AArch64_INS_FABS: fabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FABSv8f16, AArch64_INS_FABS: fabs */ + 0, + {0}}, + + {/* AArch64_FACGE16, AArch64_INS_FACGE: facge */ + 0, + {0}}, + + {/* AArch64_FACGE32, AArch64_INS_FACGE: facge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGE64, AArch64_INS_FACGE: facge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGE_PPzZZ_D, AArch64_INS_FACGE: facge */ + 0, + {0}}, + + {/* AArch64_FACGE_PPzZZ_H, AArch64_INS_FACGE: facge */ + 0, + {0}}, + + {/* AArch64_FACGE_PPzZZ_S, AArch64_INS_FACGE: facge */ + 0, + {0}}, + + {/* AArch64_FACGEv2f32, AArch64_INS_FACGE: facge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGEv2f64, AArch64_INS_FACGE: facge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGEv4f16, AArch64_INS_FACGE: facge */ + 0, + {0}}, + + {/* AArch64_FACGEv4f32, AArch64_INS_FACGE: facge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGEv8f16, AArch64_INS_FACGE: facge */ + 0, + {0}}, + + {/* AArch64_FACGT16, AArch64_INS_FACGT: facgt */ + 0, + {0}}, + + {/* AArch64_FACGT32, AArch64_INS_FACGT: facgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGT64, AArch64_INS_FACGT: facgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGT_PPzZZ_D, AArch64_INS_FACGT: facgt */ + 0, + {0}}, + + {/* AArch64_FACGT_PPzZZ_H, AArch64_INS_FACGT: facgt */ + 0, + {0}}, + + {/* AArch64_FACGT_PPzZZ_S, AArch64_INS_FACGT: facgt */ + 0, + {0}}, + + {/* AArch64_FACGTv2f32, AArch64_INS_FACGT: facgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGTv2f64, AArch64_INS_FACGT: facgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGTv4f16, AArch64_INS_FACGT: facgt */ + 0, + {0}}, + + {/* AArch64_FACGTv4f32, AArch64_INS_FACGT: facgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FACGTv8f16, AArch64_INS_FACGT: facgt */ + 0, + {0}}, + + {/* AArch64_FADDA_VPZ_D, AArch64_INS_FADDA: fadda */ + 0, + {0}}, + + {/* AArch64_FADDA_VPZ_H, AArch64_INS_FADDA: fadda */ + 0, + {0}}, + + {/* AArch64_FADDA_VPZ_S, AArch64_INS_FADDA: fadda */ + 0, + {0}}, + + {/* AArch64_FADDDrr, AArch64_INS_FADD: fadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FADDHrr, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADDPv2f32, AArch64_INS_FADDP: faddp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FADDPv2f64, AArch64_INS_FADDP: faddp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FADDPv2i16p, AArch64_INS_FADDP: faddp */ + 0, + {0}}, + + {/* AArch64_FADDPv2i32p, AArch64_INS_FADDP: faddp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FADDPv2i64p, AArch64_INS_FADDP: faddp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FADDPv4f16, AArch64_INS_FADDP: faddp */ + 0, + {0}}, + + {/* AArch64_FADDPv4f32, AArch64_INS_FADDP: faddp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FADDPv8f16, AArch64_INS_FADDP: faddp */ + 0, + {0}}, + + {/* AArch64_FADDSrr, AArch64_INS_FADD: fadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FADDV_VPZ_D, AArch64_INS_FADDV: faddv */ + 0, + {0}}, + + {/* AArch64_FADDV_VPZ_H, AArch64_INS_FADDV: faddv */ + 0, + {0}}, + + {/* AArch64_FADDV_VPZ_S, AArch64_INS_FADDV: faddv */ + 0, + {0}}, + + {/* AArch64_FADD_ZPmI_D, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADD_ZPmI_H, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADD_ZPmI_S, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADD_ZPmZ_D, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADD_ZPmZ_H, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADD_ZPmZ_S, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADD_ZZZ_D, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADD_ZZZ_H, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADD_ZZZ_S, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADDv2f32, AArch64_INS_FADD: fadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FADDv2f64, AArch64_INS_FADD: fadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FADDv4f16, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FADDv4f32, AArch64_INS_FADD: fadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FADDv8f16, AArch64_INS_FADD: fadd */ + 0, + {0}}, + + {/* AArch64_FCADD_ZPmZ_D, AArch64_INS_FCADD: fcadd */ + 0, + {0}}, + + {/* AArch64_FCADD_ZPmZ_H, AArch64_INS_FCADD: fcadd */ + 0, + {0}}, + + {/* AArch64_FCADD_ZPmZ_S, AArch64_INS_FCADD: fcadd */ + 0, + {0}}, + + {/* AArch64_FCADDv2f32, AArch64_INS_FCADD: fcadd */ + 0, + {0}}, + + {/* AArch64_FCADDv2f64, AArch64_INS_FCADD: fcadd */ + 0, + {0}}, + + {/* AArch64_FCADDv4f16, AArch64_INS_FCADD: fcadd */ + 0, + {0}}, + + {/* AArch64_FCADDv4f32, AArch64_INS_FCADD: fcadd */ + 0, + {0}}, + + {/* AArch64_FCADDv8f16, AArch64_INS_FCADD: fcadd */ + 0, + {0}}, + + {/* AArch64_FCCMPDrr, AArch64_INS_FCCMP: fccmp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ}}, + + {/* AArch64_FCCMPEDrr, AArch64_INS_FCCMPE: fccmpe */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ}}, + + {/* AArch64_FCCMPEHrr, AArch64_INS_FCCMPE: fccmpe */ + 0, + {0}}, + + {/* AArch64_FCCMPESrr, AArch64_INS_FCCMPE: fccmpe */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ}}, + + {/* AArch64_FCCMPHrr, AArch64_INS_FCCMP: fccmp */ + 0, + {0}}, + + {/* AArch64_FCCMPSrr, AArch64_INS_FCCMP: fccmp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ}}, + + {/* AArch64_FCMEQ16, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQ32, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQ64, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQ_PPzZ0_D, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQ_PPzZ0_H, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQ_PPzZ0_S, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQ_PPzZZ_D, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQ_PPzZZ_H, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQ_PPzZZ_S, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQv1i16rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQv1i32rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQv1i64rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQv2f32, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQv2f64, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQv2i32rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQv2i64rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQv4f16, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQv4f32, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQv4i16rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQv4i32rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMEQv8f16, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMEQv8i16rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + {0}}, + + {/* AArch64_FCMGE16, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGE32, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGE64, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGE_PPzZ0_D, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGE_PPzZ0_H, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGE_PPzZ0_S, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGE_PPzZZ_D, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGE_PPzZZ_H, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGE_PPzZZ_S, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGEv1i16rz, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGEv1i32rz, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGEv1i64rz, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGEv2f32, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGEv2f64, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGEv2i32rz, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGEv2i64rz, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGEv4f16, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGEv4f32, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGEv4i16rz, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGEv4i32rz, AArch64_INS_FCMGE: fcmge */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGEv8f16, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGEv8i16rz, AArch64_INS_FCMGE: fcmge */ + 0, + {0}}, + + {/* AArch64_FCMGT16, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGT32, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGT64, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGT_PPzZ0_D, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGT_PPzZ0_H, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGT_PPzZ0_S, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGT_PPzZZ_D, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGT_PPzZZ_H, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGT_PPzZZ_S, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGTv1i16rz, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGTv1i32rz, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGTv1i64rz, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGTv2f32, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGTv2f64, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGTv2i32rz, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGTv2i64rz, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGTv4f16, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGTv4f32, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGTv4i16rz, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGTv4i32rz, AArch64_INS_FCMGT: fcmgt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMGTv8f16, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMGTv8i16rz, AArch64_INS_FCMGT: fcmgt */ + 0, + {0}}, + + {/* AArch64_FCMLA_ZPmZZ_D, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLA_ZPmZZ_H, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLA_ZPmZZ_S, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLA_ZZZI_H, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLA_ZZZI_S, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLAv2f32, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLAv2f64, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLAv4f16, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLAv4f16_indexed, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLAv4f32, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLAv4f32_indexed, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLAv8f16, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLAv8f16_indexed, AArch64_INS_FCMLA: fcmla */ + 0, + {0}}, + + {/* AArch64_FCMLE_PPzZ0_D, AArch64_INS_FCMLE: fcmle */ + 0, + {0}}, + + {/* AArch64_FCMLE_PPzZ0_H, AArch64_INS_FCMLE: fcmle */ + 0, + {0}}, + + {/* AArch64_FCMLE_PPzZ0_S, AArch64_INS_FCMLE: fcmle */ + 0, + {0}}, + + {/* AArch64_FCMLEv1i16rz, AArch64_INS_FCMLE: fcmle */ + 0, + {0}}, + + {/* AArch64_FCMLEv1i32rz, AArch64_INS_FCMLE: fcmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLEv1i64rz, AArch64_INS_FCMLE: fcmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLEv2i32rz, AArch64_INS_FCMLE: fcmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLEv2i64rz, AArch64_INS_FCMLE: fcmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLEv4i16rz, AArch64_INS_FCMLE: fcmle */ + 0, + {0}}, + + {/* AArch64_FCMLEv4i32rz, AArch64_INS_FCMLE: fcmle */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLEv8i16rz, AArch64_INS_FCMLE: fcmle */ + 0, + {0}}, + + {/* AArch64_FCMLT_PPzZ0_D, AArch64_INS_FCMLT: fcmlt */ + 0, + {0}}, + + {/* AArch64_FCMLT_PPzZ0_H, AArch64_INS_FCMLT: fcmlt */ + 0, + {0}}, + + {/* AArch64_FCMLT_PPzZ0_S, AArch64_INS_FCMLT: fcmlt */ + 0, + {0}}, + + {/* AArch64_FCMLTv1i16rz, AArch64_INS_FCMLT: fcmlt */ + 0, + {0}}, + + {/* AArch64_FCMLTv1i32rz, AArch64_INS_FCMLT: fcmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLTv1i64rz, AArch64_INS_FCMLT: fcmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLTv2i32rz, AArch64_INS_FCMLT: fcmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLTv2i64rz, AArch64_INS_FCMLT: fcmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLTv4i16rz, AArch64_INS_FCMLT: fcmlt */ + 0, + {0}}, + + {/* AArch64_FCMLTv4i32rz, AArch64_INS_FCMLT: fcmlt */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMLTv8i16rz, AArch64_INS_FCMLT: fcmlt */ + 0, + {0}}, + + {/* AArch64_FCMNE_PPzZ0_D, AArch64_INS_FCMNE: fcmne */ + 0, + {0}}, + + {/* AArch64_FCMNE_PPzZ0_H, AArch64_INS_FCMNE: fcmne */ + 0, + {0}}, + + {/* AArch64_FCMNE_PPzZ0_S, AArch64_INS_FCMNE: fcmne */ + 0, + {0}}, + + {/* AArch64_FCMNE_PPzZZ_D, AArch64_INS_FCMNE: fcmne */ + 0, + {0}}, + + {/* AArch64_FCMNE_PPzZZ_H, AArch64_INS_FCMNE: fcmne */ + 0, + {0}}, + + {/* AArch64_FCMNE_PPzZZ_S, AArch64_INS_FCMNE: fcmne */ + 0, + {0}}, + + {/* AArch64_FCMPDri, AArch64_INS_FCMP: fcmp */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMPDrr, AArch64_INS_FCMP: fcmp */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMPEDri, AArch64_INS_FCMPE: fcmpe */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMPEDrr, AArch64_INS_FCMPE: fcmpe */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMPEHri, AArch64_INS_FCMPE: fcmpe */ + 0, + {0}}, + + {/* AArch64_FCMPEHrr, AArch64_INS_FCMPE: fcmpe */ + 0, + {0}}, + + {/* AArch64_FCMPESri, AArch64_INS_FCMPE: fcmpe */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMPESrr, AArch64_INS_FCMPE: fcmpe */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMPHri, AArch64_INS_FCMP: fcmp */ + 0, + {0}}, + + {/* AArch64_FCMPHrr, AArch64_INS_FCMP: fcmp */ + 0, + {0}}, + + {/* AArch64_FCMPSri, AArch64_INS_FCMP: fcmp */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMPSrr, AArch64_INS_FCMP: fcmp */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCMUO_PPzZZ_D, AArch64_INS_FCMUO: fcmuo */ + 0, + {0}}, + + {/* AArch64_FCMUO_PPzZZ_H, AArch64_INS_FCMUO: fcmuo */ + 0, + {0}}, + + {/* AArch64_FCMUO_PPzZZ_S, AArch64_INS_FCMUO: fcmuo */ + 0, + {0}}, + + {/* AArch64_FCPY_ZPmI_D, AArch64_INS_FCPY: fcpy */ + 0, + {0}}, + + {/* AArch64_FCPY_ZPmI_H, AArch64_INS_FCPY: fcpy */ + 0, + {0}}, + + {/* AArch64_FCPY_ZPmI_S, AArch64_INS_FCPY: fcpy */ + 0, + {0}}, + + {/* AArch64_FCSELDrrr, AArch64_INS_FCSEL: fcsel */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FCSELHrrr, AArch64_INS_FCSEL: fcsel */ + 0, + {0}}, + + {/* AArch64_FCSELSrrr, AArch64_INS_FCSEL: fcsel */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FCVTASUWDr, AArch64_INS_FCVTAS: fcvtas */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTASUWHr, AArch64_INS_FCVTAS: fcvtas */ + 0, + {0}}, + + {/* AArch64_FCVTASUWSr, AArch64_INS_FCVTAS: fcvtas */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTASUXDr, AArch64_INS_FCVTAS: fcvtas */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTASUXHr, AArch64_INS_FCVTAS: fcvtas */ + 0, + {0}}, + + {/* AArch64_FCVTASUXSr, AArch64_INS_FCVTAS: fcvtas */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTASv1f16, AArch64_INS_FCVTAS: fcvtas */ + 0, + {0}}, + + {/* AArch64_FCVTASv1i32, AArch64_INS_FCVTAS: fcvtas */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTASv1i64, AArch64_INS_FCVTAS: fcvtas */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTASv2f32, AArch64_INS_FCVTAS: fcvtas */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTASv2f64, AArch64_INS_FCVTAS: fcvtas */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTASv4f16, AArch64_INS_FCVTAS: fcvtas */ + 0, + {0}}, + + {/* AArch64_FCVTASv4f32, AArch64_INS_FCVTAS: fcvtas */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTASv8f16, AArch64_INS_FCVTAS: fcvtas */ + 0, + {0}}, + + {/* AArch64_FCVTAUUWDr, AArch64_INS_FCVTAU: fcvtau */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTAUUWHr, AArch64_INS_FCVTAU: fcvtau */ + 0, + {0}}, + + {/* AArch64_FCVTAUUWSr, AArch64_INS_FCVTAU: fcvtau */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTAUUXDr, AArch64_INS_FCVTAU: fcvtau */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTAUUXHr, AArch64_INS_FCVTAU: fcvtau */ + 0, + {0}}, + + {/* AArch64_FCVTAUUXSr, AArch64_INS_FCVTAU: fcvtau */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTAUv1f16, AArch64_INS_FCVTAU: fcvtau */ + 0, + {0}}, + + {/* AArch64_FCVTAUv1i32, AArch64_INS_FCVTAU: fcvtau */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTAUv1i64, AArch64_INS_FCVTAU: fcvtau */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTAUv2f32, AArch64_INS_FCVTAU: fcvtau */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTAUv2f64, AArch64_INS_FCVTAU: fcvtau */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTAUv4f16, AArch64_INS_FCVTAU: fcvtau */ + 0, + {0}}, + + {/* AArch64_FCVTAUv4f32, AArch64_INS_FCVTAU: fcvtau */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTAUv8f16, AArch64_INS_FCVTAU: fcvtau */ + 0, + {0}}, + + {/* AArch64_FCVTDHr, AArch64_INS_FCVT: fcvt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTDSr, AArch64_INS_FCVT: fcvt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTHDr, AArch64_INS_FCVT: fcvt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTHSr, AArch64_INS_FCVT: fcvt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTLv2i32, AArch64_INS_FCVTL: fcvtl */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTLv4i16, AArch64_INS_FCVTL: fcvtl */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTLv4i32, AArch64_INS_FCVTL2: fcvtl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTLv8i16, AArch64_INS_FCVTL2: fcvtl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSUWDr, AArch64_INS_FCVTMS: fcvtms */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSUWHr, AArch64_INS_FCVTMS: fcvtms */ + 0, + {0}}, + + {/* AArch64_FCVTMSUWSr, AArch64_INS_FCVTMS: fcvtms */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSUXDr, AArch64_INS_FCVTMS: fcvtms */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSUXHr, AArch64_INS_FCVTMS: fcvtms */ + 0, + {0}}, + + {/* AArch64_FCVTMSUXSr, AArch64_INS_FCVTMS: fcvtms */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSv1f16, AArch64_INS_FCVTMS: fcvtms */ + 0, + {0}}, + + {/* AArch64_FCVTMSv1i32, AArch64_INS_FCVTMS: fcvtms */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSv1i64, AArch64_INS_FCVTMS: fcvtms */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSv2f32, AArch64_INS_FCVTMS: fcvtms */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSv2f64, AArch64_INS_FCVTMS: fcvtms */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSv4f16, AArch64_INS_FCVTMS: fcvtms */ + 0, + {0}}, + + {/* AArch64_FCVTMSv4f32, AArch64_INS_FCVTMS: fcvtms */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMSv8f16, AArch64_INS_FCVTMS: fcvtms */ + 0, + {0}}, + + {/* AArch64_FCVTMUUWDr, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMUUWHr, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {0}}, + + {/* AArch64_FCVTMUUWSr, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMUUXDr, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMUUXHr, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {0}}, + + {/* AArch64_FCVTMUUXSr, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMUv1f16, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {0}}, + + {/* AArch64_FCVTMUv1i32, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMUv1i64, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMUv2f32, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMUv2f64, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMUv4f16, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {0}}, + + {/* AArch64_FCVTMUv4f32, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTMUv8f16, AArch64_INS_FCVTMU: fcvtmu */ + 0, + {0}}, + + {/* AArch64_FCVTNSUWDr, AArch64_INS_FCVTNS: fcvtns */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNSUWHr, AArch64_INS_FCVTNS: fcvtns */ + 0, + {0}}, + + {/* AArch64_FCVTNSUWSr, AArch64_INS_FCVTNS: fcvtns */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNSUXDr, AArch64_INS_FCVTNS: fcvtns */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNSUXHr, AArch64_INS_FCVTNS: fcvtns */ + 0, + {0}}, + + {/* AArch64_FCVTNSUXSr, AArch64_INS_FCVTNS: fcvtns */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNSv1f16, AArch64_INS_FCVTNS: fcvtns */ + 0, + {0}}, + + {/* AArch64_FCVTNSv1i32, AArch64_INS_FCVTNS: fcvtns */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNSv1i64, AArch64_INS_FCVTNS: fcvtns */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNSv2f32, AArch64_INS_FCVTNS: fcvtns */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNSv2f64, AArch64_INS_FCVTNS: fcvtns */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNSv4f16, AArch64_INS_FCVTNS: fcvtns */ + 0, + {0}}, + + {/* AArch64_FCVTNSv4f32, AArch64_INS_FCVTNS: fcvtns */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNSv8f16, AArch64_INS_FCVTNS: fcvtns */ + 0, + {0}}, + + {/* AArch64_FCVTNUUWDr, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNUUWHr, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {0}}, + + {/* AArch64_FCVTNUUWSr, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNUUXDr, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNUUXHr, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {0}}, + + {/* AArch64_FCVTNUUXSr, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNUv1f16, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {0}}, + + {/* AArch64_FCVTNUv1i32, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNUv1i64, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNUv2f32, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNUv2f64, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNUv4f16, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {0}}, + + {/* AArch64_FCVTNUv4f32, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNUv8f16, AArch64_INS_FCVTNU: fcvtnu */ + 0, + {0}}, + + {/* AArch64_FCVTNv2i32, AArch64_INS_FCVTN: fcvtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNv4i16, AArch64_INS_FCVTN: fcvtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNv4i32, AArch64_INS_FCVTN2: fcvtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTNv8i16, AArch64_INS_FCVTN2: fcvtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSUWDr, AArch64_INS_FCVTPS: fcvtps */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSUWHr, AArch64_INS_FCVTPS: fcvtps */ + 0, + {0}}, + + {/* AArch64_FCVTPSUWSr, AArch64_INS_FCVTPS: fcvtps */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSUXDr, AArch64_INS_FCVTPS: fcvtps */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSUXHr, AArch64_INS_FCVTPS: fcvtps */ + 0, + {0}}, + + {/* AArch64_FCVTPSUXSr, AArch64_INS_FCVTPS: fcvtps */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSv1f16, AArch64_INS_FCVTPS: fcvtps */ + 0, + {0}}, + + {/* AArch64_FCVTPSv1i32, AArch64_INS_FCVTPS: fcvtps */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSv1i64, AArch64_INS_FCVTPS: fcvtps */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSv2f32, AArch64_INS_FCVTPS: fcvtps */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSv2f64, AArch64_INS_FCVTPS: fcvtps */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSv4f16, AArch64_INS_FCVTPS: fcvtps */ + 0, + {0}}, + + {/* AArch64_FCVTPSv4f32, AArch64_INS_FCVTPS: fcvtps */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPSv8f16, AArch64_INS_FCVTPS: fcvtps */ + 0, + {0}}, + + {/* AArch64_FCVTPUUWDr, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPUUWHr, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {0}}, + + {/* AArch64_FCVTPUUWSr, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPUUXDr, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPUUXHr, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {0}}, + + {/* AArch64_FCVTPUUXSr, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPUv1f16, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {0}}, + + {/* AArch64_FCVTPUv1i32, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPUv1i64, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPUv2f32, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPUv2f64, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPUv4f16, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {0}}, + + {/* AArch64_FCVTPUv4f32, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTPUv8f16, AArch64_INS_FCVTPU: fcvtpu */ + 0, + {0}}, + + {/* AArch64_FCVTSDr, AArch64_INS_FCVT: fcvt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTSHr, AArch64_INS_FCVT: fcvt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTXNv1i64, AArch64_INS_FCVTXN: fcvtxn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTXNv2f32, AArch64_INS_FCVTXN: fcvtxn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTXNv4f32, AArch64_INS_FCVTXN2: fcvtxn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSSWDri, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSSWHri, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSSWSri, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSSXDri, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSSXHri, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSSXSri, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSUWDr, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSUWHr, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSUWSr, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSUXDr, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSUXHr, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSUXSr, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZS_ZPmZ_DtoD, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZS_ZPmZ_DtoS, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZS_ZPmZ_HtoD, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZS_ZPmZ_HtoH, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZS_ZPmZ_HtoS, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZS_ZPmZ_StoD, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZS_ZPmZ_StoS, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSd, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSh, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSs, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSv1f16, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSv1i32, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSv1i64, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSv2f32, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSv2f64, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSv2i32_shift, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSv2i64_shift, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSv4f16, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSv4f32, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSv4i16_shift, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSv4i32_shift, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZSv8f16, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZSv8i16_shift, AArch64_INS_FCVTZS: fcvtzs */ + 0, + {0}}, + + {/* AArch64_FCVTZUSWDri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUSWHri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUSWSri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUSXDri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUSXHri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUSXSri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUUWDr, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUUWHr, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUUWSr, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUUXDr, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUUXHr, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUUXSr, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZU_ZPmZ_DtoD, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZU_ZPmZ_DtoS, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZU_ZPmZ_HtoD, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZU_ZPmZ_HtoH, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZU_ZPmZ_HtoS, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZU_ZPmZ_StoD, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZU_ZPmZ_StoS, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUd, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUh, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUs, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUv1f16, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUv1i32, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUv1i64, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUv2f32, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUv2f64, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUv2i32_shift, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUv2i64_shift, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUv4f16, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUv4f32, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUv4i16_shift, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUv4i32_shift, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FCVTZUv8f16, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVTZUv8i16_shift, AArch64_INS_FCVTZU: fcvtzu */ + 0, + {0}}, + + {/* AArch64_FCVT_ZPmZ_DtoH, AArch64_INS_FCVT: fcvt */ + 0, + {0}}, + + {/* AArch64_FCVT_ZPmZ_DtoS, AArch64_INS_FCVT: fcvt */ + 0, + {0}}, + + {/* AArch64_FCVT_ZPmZ_HtoD, AArch64_INS_FCVT: fcvt */ + 0, + {0}}, + + {/* AArch64_FCVT_ZPmZ_HtoS, AArch64_INS_FCVT: fcvt */ + 0, + {0}}, + + {/* AArch64_FCVT_ZPmZ_StoD, AArch64_INS_FCVT: fcvt */ + 0, + {0}}, + + {/* AArch64_FCVT_ZPmZ_StoH, AArch64_INS_FCVT: fcvt */ + 0, + {0}}, + + {/* AArch64_FDIVDrr, AArch64_INS_FDIV: fdiv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FDIVHrr, AArch64_INS_FDIV: fdiv */ + 0, + {0}}, + + {/* AArch64_FDIVR_ZPmZ_D, AArch64_INS_FDIVR: fdivr */ + 0, + {0}}, + + {/* AArch64_FDIVR_ZPmZ_H, AArch64_INS_FDIVR: fdivr */ + 0, + {0}}, + + {/* AArch64_FDIVR_ZPmZ_S, AArch64_INS_FDIVR: fdivr */ + 0, + {0}}, + + {/* AArch64_FDIVSrr, AArch64_INS_FDIV: fdiv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FDIV_ZPmZ_D, AArch64_INS_FDIV: fdiv */ + 0, + {0}}, + + {/* AArch64_FDIV_ZPmZ_H, AArch64_INS_FDIV: fdiv */ + 0, + {0}}, + + {/* AArch64_FDIV_ZPmZ_S, AArch64_INS_FDIV: fdiv */ + 0, + {0}}, + + {/* AArch64_FDIVv2f32, AArch64_INS_FDIV: fdiv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FDIVv2f64, AArch64_INS_FDIV: fdiv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FDIVv4f16, AArch64_INS_FDIV: fdiv */ + 0, + {0}}, + + {/* AArch64_FDIVv4f32, AArch64_INS_FDIV: fdiv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FDIVv8f16, AArch64_INS_FDIV: fdiv */ + 0, + {0}}, + + {/* AArch64_FDUP_ZI_D, AArch64_INS_FDUP: fdup */ + 0, + {0}}, + + {/* AArch64_FDUP_ZI_H, AArch64_INS_FDUP: fdup */ + 0, + {0}}, + + {/* AArch64_FDUP_ZI_S, AArch64_INS_FDUP: fdup */ + 0, + {0}}, + + {/* AArch64_FEXPA_ZZ_D, AArch64_INS_FEXPA: fexpa */ + 0, + {0}}, + + {/* AArch64_FEXPA_ZZ_H, AArch64_INS_FEXPA: fexpa */ + 0, + {0}}, + + {/* AArch64_FEXPA_ZZ_S, AArch64_INS_FEXPA: fexpa */ + 0, + {0}}, + + {/* AArch64_FJCVTZS, AArch64_INS_FJCVTZS: fjcvtzs */ + 0, + {0}}, + + {/* AArch64_FMADDDrrr, AArch64_INS_FMADD: fmadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMADDHrrr, AArch64_INS_FMADD: fmadd */ + 0, + {0}}, + + {/* AArch64_FMADDSrrr, AArch64_INS_FMADD: fmadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMAD_ZPmZZ_D, AArch64_INS_FMAD: fmad */ + 0, + {0}}, + + {/* AArch64_FMAD_ZPmZZ_H, AArch64_INS_FMAD: fmad */ + 0, + {0}}, + + {/* AArch64_FMAD_ZPmZZ_S, AArch64_INS_FMAD: fmad */ + 0, + {0}}, + + {/* AArch64_FMAXDrr, AArch64_INS_FMAX: fmax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXHrr, AArch64_INS_FMAX: fmax */ + 0, + {0}}, + + {/* AArch64_FMAXNMDrr, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMHrr, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {0}}, + + {/* AArch64_FMAXNMPv2f32, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMPv2f64, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMPv2i16p, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + {0}}, + + {/* AArch64_FMAXNMPv2i32p, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMPv2i64p, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMPv4f16, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + {0}}, + + {/* AArch64_FMAXNMPv4f32, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMPv8f16, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + {0}}, + + {/* AArch64_FMAXNMSrr, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMV_VPZ_D, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + {0}}, + + {/* AArch64_FMAXNMV_VPZ_H, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + {0}}, + + {/* AArch64_FMAXNMV_VPZ_S, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + {0}}, + + {/* AArch64_FMAXNMVv4i16v, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + {0}}, + + {/* AArch64_FMAXNMVv4i32v, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMVv8i16v, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + {0}}, + + {/* AArch64_FMAXNM_ZPmI_D, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {0}}, + + {/* AArch64_FMAXNM_ZPmI_H, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {0}}, + + {/* AArch64_FMAXNM_ZPmI_S, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {0}}, + + {/* AArch64_FMAXNM_ZPmZ_D, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {0}}, + + {/* AArch64_FMAXNM_ZPmZ_H, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {0}}, + + {/* AArch64_FMAXNM_ZPmZ_S, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {0}}, + + {/* AArch64_FMAXNMv2f32, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMv2f64, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMv4f16, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {0}}, + + {/* AArch64_FMAXNMv4f32, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXNMv8f16, AArch64_INS_FMAXNM: fmaxnm */ + 0, + {0}}, + + {/* AArch64_FMAXPv2f32, AArch64_INS_FMAXP: fmaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXPv2f64, AArch64_INS_FMAXP: fmaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXPv2i16p, AArch64_INS_FMAXP: fmaxp */ + 0, + {0}}, + + {/* AArch64_FMAXPv2i32p, AArch64_INS_FMAXP: fmaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMAXPv2i64p, AArch64_INS_FMAXP: fmaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMAXPv4f16, AArch64_INS_FMAXP: fmaxp */ + 0, + {0}}, + + {/* AArch64_FMAXPv4f32, AArch64_INS_FMAXP: fmaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXPv8f16, AArch64_INS_FMAXP: fmaxp */ + 0, + {0}}, + + {/* AArch64_FMAXSrr, AArch64_INS_FMAX: fmax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXV_VPZ_D, AArch64_INS_FMAXV: fmaxv */ + 0, + {0}}, + + {/* AArch64_FMAXV_VPZ_H, AArch64_INS_FMAXV: fmaxv */ + 0, + {0}}, + + {/* AArch64_FMAXV_VPZ_S, AArch64_INS_FMAXV: fmaxv */ + 0, + {0}}, + + {/* AArch64_FMAXVv4i16v, AArch64_INS_FMAXV: fmaxv */ + 0, + {0}}, + + {/* AArch64_FMAXVv4i32v, AArch64_INS_FMAXV: fmaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMAXVv8i16v, AArch64_INS_FMAXV: fmaxv */ + 0, + {0}}, + + {/* AArch64_FMAX_ZPmI_D, AArch64_INS_FMAX: fmax */ + 0, + {0}}, + + {/* AArch64_FMAX_ZPmI_H, AArch64_INS_FMAX: fmax */ + 0, + {0}}, + + {/* AArch64_FMAX_ZPmI_S, AArch64_INS_FMAX: fmax */ + 0, + {0}}, + + {/* AArch64_FMAX_ZPmZ_D, AArch64_INS_FMAX: fmax */ + 0, + {0}}, + + {/* AArch64_FMAX_ZPmZ_H, AArch64_INS_FMAX: fmax */ + 0, + {0}}, + + {/* AArch64_FMAX_ZPmZ_S, AArch64_INS_FMAX: fmax */ + 0, + {0}}, + + {/* AArch64_FMAXv2f32, AArch64_INS_FMAX: fmax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXv2f64, AArch64_INS_FMAX: fmax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXv4f16, AArch64_INS_FMAX: fmax */ + 0, + {0}}, + + {/* AArch64_FMAXv4f32, AArch64_INS_FMAX: fmax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMAXv8f16, AArch64_INS_FMAX: fmax */ + 0, + {0}}, + + {/* AArch64_FMINDrr, AArch64_INS_FMIN: fmin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINHrr, AArch64_INS_FMIN: fmin */ + 0, + {0}}, + + {/* AArch64_FMINNMDrr, AArch64_INS_FMINNM: fminnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMHrr, AArch64_INS_FMINNM: fminnm */ + 0, + {0}}, + + {/* AArch64_FMINNMPv2f32, AArch64_INS_FMINNMP: fminnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMPv2f64, AArch64_INS_FMINNMP: fminnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMPv2i16p, AArch64_INS_FMINNMP: fminnmp */ + 0, + {0}}, + + {/* AArch64_FMINNMPv2i32p, AArch64_INS_FMINNMP: fminnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMPv2i64p, AArch64_INS_FMINNMP: fminnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMPv4f16, AArch64_INS_FMINNMP: fminnmp */ + 0, + {0}}, + + {/* AArch64_FMINNMPv4f32, AArch64_INS_FMINNMP: fminnmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMPv8f16, AArch64_INS_FMINNMP: fminnmp */ + 0, + {0}}, + + {/* AArch64_FMINNMSrr, AArch64_INS_FMINNM: fminnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMV_VPZ_D, AArch64_INS_FMINNMV: fminnmv */ + 0, + {0}}, + + {/* AArch64_FMINNMV_VPZ_H, AArch64_INS_FMINNMV: fminnmv */ + 0, + {0}}, + + {/* AArch64_FMINNMV_VPZ_S, AArch64_INS_FMINNMV: fminnmv */ + 0, + {0}}, + + {/* AArch64_FMINNMVv4i16v, AArch64_INS_FMINNMV: fminnmv */ + 0, + {0}}, + + {/* AArch64_FMINNMVv4i32v, AArch64_INS_FMINNMV: fminnmv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMVv8i16v, AArch64_INS_FMINNMV: fminnmv */ + 0, + {0}}, + + {/* AArch64_FMINNM_ZPmI_D, AArch64_INS_FMINNM: fminnm */ + 0, + {0}}, + + {/* AArch64_FMINNM_ZPmI_H, AArch64_INS_FMINNM: fminnm */ + 0, + {0}}, + + {/* AArch64_FMINNM_ZPmI_S, AArch64_INS_FMINNM: fminnm */ + 0, + {0}}, + + {/* AArch64_FMINNM_ZPmZ_D, AArch64_INS_FMINNM: fminnm */ + 0, + {0}}, + + {/* AArch64_FMINNM_ZPmZ_H, AArch64_INS_FMINNM: fminnm */ + 0, + {0}}, + + {/* AArch64_FMINNM_ZPmZ_S, AArch64_INS_FMINNM: fminnm */ + 0, + {0}}, + + {/* AArch64_FMINNMv2f32, AArch64_INS_FMINNM: fminnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMv2f64, AArch64_INS_FMINNM: fminnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMv4f16, AArch64_INS_FMINNM: fminnm */ + 0, + {0}}, + + {/* AArch64_FMINNMv4f32, AArch64_INS_FMINNM: fminnm */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINNMv8f16, AArch64_INS_FMINNM: fminnm */ + 0, + {0}}, + + {/* AArch64_FMINPv2f32, AArch64_INS_FMINP: fminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINPv2f64, AArch64_INS_FMINP: fminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINPv2i16p, AArch64_INS_FMINP: fminp */ + 0, + {0}}, + + {/* AArch64_FMINPv2i32p, AArch64_INS_FMINP: fminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMINPv2i64p, AArch64_INS_FMINP: fminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMINPv4f16, AArch64_INS_FMINP: fminp */ + 0, + {0}}, + + {/* AArch64_FMINPv4f32, AArch64_INS_FMINP: fminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINPv8f16, AArch64_INS_FMINP: fminp */ + 0, + {0}}, + + {/* AArch64_FMINSrr, AArch64_INS_FMIN: fmin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINV_VPZ_D, AArch64_INS_FMINV: fminv */ + 0, + {0}}, + + {/* AArch64_FMINV_VPZ_H, AArch64_INS_FMINV: fminv */ + 0, + {0}}, + + {/* AArch64_FMINV_VPZ_S, AArch64_INS_FMINV: fminv */ + 0, + {0}}, + + {/* AArch64_FMINVv4i16v, AArch64_INS_FMINV: fminv */ + 0, + {0}}, + + {/* AArch64_FMINVv4i32v, AArch64_INS_FMINV: fminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMINVv8i16v, AArch64_INS_FMINV: fminv */ + 0, + {0}}, + + {/* AArch64_FMIN_ZPmI_D, AArch64_INS_FMIN: fmin */ + 0, + {0}}, + + {/* AArch64_FMIN_ZPmI_H, AArch64_INS_FMIN: fmin */ + 0, + {0}}, + + {/* AArch64_FMIN_ZPmI_S, AArch64_INS_FMIN: fmin */ + 0, + {0}}, + + {/* AArch64_FMIN_ZPmZ_D, AArch64_INS_FMIN: fmin */ + 0, + {0}}, + + {/* AArch64_FMIN_ZPmZ_H, AArch64_INS_FMIN: fmin */ + 0, + {0}}, + + {/* AArch64_FMIN_ZPmZ_S, AArch64_INS_FMIN: fmin */ + 0, + {0}}, + + {/* AArch64_FMINv2f32, AArch64_INS_FMIN: fmin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINv2f64, AArch64_INS_FMIN: fmin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINv4f16, AArch64_INS_FMIN: fmin */ + 0, + {0}}, + + {/* AArch64_FMINv4f32, AArch64_INS_FMIN: fmin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMINv8f16, AArch64_INS_FMIN: fmin */ + 0, + {0}}, + + {/* AArch64_FMLA_ZPmZZ_D, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLA_ZPmZZ_H, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLA_ZPmZZ_S, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLA_ZZZI_D, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLA_ZZZI_H, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLA_ZZZI_S, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLAv1i16_indexed, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLAv1i32_indexed, AArch64_INS_FMLA: fmla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLAv1i64_indexed, AArch64_INS_FMLA: fmla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLAv2f32, AArch64_INS_FMLA: fmla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMLAv2f64, AArch64_INS_FMLA: fmla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMLAv2i32_indexed, AArch64_INS_FMLA: fmla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLAv2i64_indexed, AArch64_INS_FMLA: fmla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLAv4f16, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLAv4f32, AArch64_INS_FMLA: fmla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMLAv4i16_indexed, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLAv4i32_indexed, AArch64_INS_FMLA: fmla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLAv8f16, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLAv8i16_indexed, AArch64_INS_FMLA: fmla */ + 0, + {0}}, + + {/* AArch64_FMLS_ZPmZZ_D, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLS_ZPmZZ_H, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLS_ZPmZZ_S, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLS_ZZZI_D, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLS_ZZZI_H, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLS_ZZZI_S, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLSv1i16_indexed, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLSv1i32_indexed, AArch64_INS_FMLS: fmls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLSv1i64_indexed, AArch64_INS_FMLS: fmls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLSv2f32, AArch64_INS_FMLS: fmls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMLSv2f64, AArch64_INS_FMLS: fmls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMLSv2i32_indexed, AArch64_INS_FMLS: fmls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLSv2i64_indexed, AArch64_INS_FMLS: fmls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLSv4f16, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLSv4f32, AArch64_INS_FMLS: fmls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMLSv4i16_indexed, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLSv4i32_indexed, AArch64_INS_FMLS: fmls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMLSv8f16, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMLSv8i16_indexed, AArch64_INS_FMLS: fmls */ + 0, + {0}}, + + {/* AArch64_FMOVDXHighr, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMOVDXr, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMOVDi, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMOVDr, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMOVHWr, AArch64_INS_FMOV: fmov */ + 0, + {0}}, + + {/* AArch64_FMOVHXr, AArch64_INS_FMOV: fmov */ + 0, + {0}}, + + {/* AArch64_FMOVHi, AArch64_INS_FMOV: fmov */ + 0, + {0}}, + + {/* AArch64_FMOVHr, AArch64_INS_FMOV: fmov */ + 0, + {0}}, + + {/* AArch64_FMOVSWr, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMOVSi, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMOVSr, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMOVWHr, AArch64_INS_FMOV: fmov */ + 0, + {0}}, + + {/* AArch64_FMOVWSr, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMOVXDHighr, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMOVXDr, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FMOVXHr, AArch64_INS_FMOV: fmov */ + 0, + {0}}, + + {/* AArch64_FMOVv2f32_ns, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMOVv2f64_ns, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMOVv4f16_ns, AArch64_INS_FMOV: fmov */ + 0, + {0}}, + + {/* AArch64_FMOVv4f32_ns, AArch64_INS_FMOV: fmov */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMOVv8f16_ns, AArch64_INS_FMOV: fmov */ + 0, + {0}}, + + {/* AArch64_FMSB_ZPmZZ_D, AArch64_INS_FMSB: fmsb */ + 0, + {0}}, + + {/* AArch64_FMSB_ZPmZZ_H, AArch64_INS_FMSB: fmsb */ + 0, + {0}}, + + {/* AArch64_FMSB_ZPmZZ_S, AArch64_INS_FMSB: fmsb */ + 0, + {0}}, + + {/* AArch64_FMSUBDrrr, AArch64_INS_FMSUB: fmsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMSUBHrrr, AArch64_INS_FMSUB: fmsub */ + 0, + {0}}, + + {/* AArch64_FMSUBSrrr, AArch64_INS_FMSUB: fmsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULDrr, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULHrr, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMULSrr, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULX16, AArch64_INS_FMULX: fmulx */ + 0, + {0}}, + + {/* AArch64_FMULX32, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULX64, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULX_ZPmZ_D, AArch64_INS_FMULX: fmulx */ + 0, + {0}}, + + {/* AArch64_FMULX_ZPmZ_H, AArch64_INS_FMULX: fmulx */ + 0, + {0}}, + + {/* AArch64_FMULX_ZPmZ_S, AArch64_INS_FMULX: fmulx */ + 0, + {0}}, + + {/* AArch64_FMULXv1i16_indexed, AArch64_INS_FMULX: fmulx */ + 0, + {0}}, + + {/* AArch64_FMULXv1i32_indexed, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULXv1i64_indexed, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULXv2f32, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULXv2f64, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULXv2i32_indexed, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULXv2i64_indexed, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULXv4f16, AArch64_INS_FMULX: fmulx */ + 0, + {0}}, + + {/* AArch64_FMULXv4f32, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULXv4i16_indexed, AArch64_INS_FMULX: fmulx */ + 0, + {0}}, + + {/* AArch64_FMULXv4i32_indexed, AArch64_INS_FMULX: fmulx */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULXv8f16, AArch64_INS_FMULX: fmulx */ + 0, + {0}}, + + {/* AArch64_FMULXv8i16_indexed, AArch64_INS_FMULX: fmulx */ + 0, + {0}}, + + {/* AArch64_FMUL_ZPmI_D, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZPmI_H, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZPmI_S, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZPmZ_D, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZPmZ_H, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZPmZ_S, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZZZI_D, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZZZI_H, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZZZI_S, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZZZ_D, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZZZ_H, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMUL_ZZZ_S, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMULv1i16_indexed, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMULv1i32_indexed, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULv1i64_indexed, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULv2f32, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULv2f64, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULv2i32_indexed, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULv2i64_indexed, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULv4f16, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMULv4f32, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FMULv4i16_indexed, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMULv4i32_indexed, AArch64_INS_FMUL: fmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FMULv8f16, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FMULv8i16_indexed, AArch64_INS_FMUL: fmul */ + 0, + {0}}, + + {/* AArch64_FNEGDr, AArch64_INS_FNEG: fneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FNEGHr, AArch64_INS_FNEG: fneg */ + 0, + {0}}, + + {/* AArch64_FNEGSr, AArch64_INS_FNEG: fneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FNEG_ZPmZ_D, AArch64_INS_FNEG: fneg */ + 0, + {0}}, + + {/* AArch64_FNEG_ZPmZ_H, AArch64_INS_FNEG: fneg */ + 0, + {0}}, + + {/* AArch64_FNEG_ZPmZ_S, AArch64_INS_FNEG: fneg */ + 0, + {0}}, + + {/* AArch64_FNEGv2f32, AArch64_INS_FNEG: fneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FNEGv2f64, AArch64_INS_FNEG: fneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FNEGv4f16, AArch64_INS_FNEG: fneg */ + 0, + {0}}, + + {/* AArch64_FNEGv4f32, AArch64_INS_FNEG: fneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FNEGv8f16, AArch64_INS_FNEG: fneg */ + 0, + {0}}, + + {/* AArch64_FNMADDDrrr, AArch64_INS_FNMADD: fnmadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FNMADDHrrr, AArch64_INS_FNMADD: fnmadd */ + 0, + {0}}, + + {/* AArch64_FNMADDSrrr, AArch64_INS_FNMADD: fnmadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FNMAD_ZPmZZ_D, AArch64_INS_FNMAD: fnmad */ + 0, + {0}}, + + {/* AArch64_FNMAD_ZPmZZ_H, AArch64_INS_FNMAD: fnmad */ + 0, + {0}}, + + {/* AArch64_FNMAD_ZPmZZ_S, AArch64_INS_FNMAD: fnmad */ + 0, + {0}}, + + {/* AArch64_FNMLA_ZPmZZ_D, AArch64_INS_FNMLA: fnmla */ + 0, + {0}}, + + {/* AArch64_FNMLA_ZPmZZ_H, AArch64_INS_FNMLA: fnmla */ + 0, + {0}}, + + {/* AArch64_FNMLA_ZPmZZ_S, AArch64_INS_FNMLA: fnmla */ + 0, + {0}}, + + {/* AArch64_FNMLS_ZPmZZ_D, AArch64_INS_FNMLS: fnmls */ + 0, + {0}}, + + {/* AArch64_FNMLS_ZPmZZ_H, AArch64_INS_FNMLS: fnmls */ + 0, + {0}}, + + {/* AArch64_FNMLS_ZPmZZ_S, AArch64_INS_FNMLS: fnmls */ + 0, + {0}}, + + {/* AArch64_FNMSB_ZPmZZ_D, AArch64_INS_FNMSB: fnmsb */ + 0, + {0}}, + + {/* AArch64_FNMSB_ZPmZZ_H, AArch64_INS_FNMSB: fnmsb */ + 0, + {0}}, + + {/* AArch64_FNMSB_ZPmZZ_S, AArch64_INS_FNMSB: fnmsb */ + 0, + {0}}, + + {/* AArch64_FNMSUBDrrr, AArch64_INS_FNMSUB: fnmsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FNMSUBHrrr, AArch64_INS_FNMSUB: fnmsub */ + 0, + {0}}, + + {/* AArch64_FNMSUBSrrr, AArch64_INS_FNMSUB: fnmsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_FNMULDrr, AArch64_INS_FNMUL: fnmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FNMULHrr, AArch64_INS_FNMUL: fnmul */ + 0, + {0}}, + + {/* AArch64_FNMULSrr, AArch64_INS_FNMUL: fnmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRECPE_ZZ_D, AArch64_INS_FRECPE: frecpe */ + 0, + {0}}, + + {/* AArch64_FRECPE_ZZ_H, AArch64_INS_FRECPE: frecpe */ + 0, + {0}}, + + {/* AArch64_FRECPE_ZZ_S, AArch64_INS_FRECPE: frecpe */ + 0, + {0}}, + + {/* AArch64_FRECPEv1f16, AArch64_INS_FRECPE: frecpe */ + 0, + {0}}, + + {/* AArch64_FRECPEv1i32, AArch64_INS_FRECPE: frecpe */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRECPEv1i64, AArch64_INS_FRECPE: frecpe */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRECPEv2f32, AArch64_INS_FRECPE: frecpe */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRECPEv2f64, AArch64_INS_FRECPE: frecpe */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRECPEv4f16, AArch64_INS_FRECPE: frecpe */ + 0, + {0}}, + + {/* AArch64_FRECPEv4f32, AArch64_INS_FRECPE: frecpe */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRECPEv8f16, AArch64_INS_FRECPE: frecpe */ + 0, + {0}}, + + {/* AArch64_FRECPS16, AArch64_INS_FRECPS: frecps */ + 0, + {0}}, + + {/* AArch64_FRECPS32, AArch64_INS_FRECPS: frecps */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRECPS64, AArch64_INS_FRECPS: frecps */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRECPS_ZZZ_D, AArch64_INS_FRECPS: frecps */ + 0, + {0}}, + + {/* AArch64_FRECPS_ZZZ_H, AArch64_INS_FRECPS: frecps */ + 0, + {0}}, + + {/* AArch64_FRECPS_ZZZ_S, AArch64_INS_FRECPS: frecps */ + 0, + {0}}, + + {/* AArch64_FRECPSv2f32, AArch64_INS_FRECPS: frecps */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRECPSv2f64, AArch64_INS_FRECPS: frecps */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRECPSv4f16, AArch64_INS_FRECPS: frecps */ + 0, + {0}}, + + {/* AArch64_FRECPSv4f32, AArch64_INS_FRECPS: frecps */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRECPSv8f16, AArch64_INS_FRECPS: frecps */ + 0, + {0}}, + + {/* AArch64_FRECPX_ZPmZ_D, AArch64_INS_FRECPX: frecpx */ + 0, + {0}}, + + {/* AArch64_FRECPX_ZPmZ_H, AArch64_INS_FRECPX: frecpx */ + 0, + {0}}, + + {/* AArch64_FRECPX_ZPmZ_S, AArch64_INS_FRECPX: frecpx */ + 0, + {0}}, + + {/* AArch64_FRECPXv1f16, AArch64_INS_FRECPX: frecpx */ + 0, + {0}}, + + {/* AArch64_FRECPXv1i32, AArch64_INS_FRECPX: frecpx */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRECPXv1i64, AArch64_INS_FRECPX: frecpx */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTADr, AArch64_INS_FRINTA: frinta */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTAHr, AArch64_INS_FRINTA: frinta */ + 0, + {0}}, + + {/* AArch64_FRINTASr, AArch64_INS_FRINTA: frinta */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTA_ZPmZ_D, AArch64_INS_FRINTA: frinta */ + 0, + {0}}, + + {/* AArch64_FRINTA_ZPmZ_H, AArch64_INS_FRINTA: frinta */ + 0, + {0}}, + + {/* AArch64_FRINTA_ZPmZ_S, AArch64_INS_FRINTA: frinta */ + 0, + {0}}, + + {/* AArch64_FRINTAv2f32, AArch64_INS_FRINTA: frinta */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTAv2f64, AArch64_INS_FRINTA: frinta */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTAv4f16, AArch64_INS_FRINTA: frinta */ + 0, + {0}}, + + {/* AArch64_FRINTAv4f32, AArch64_INS_FRINTA: frinta */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTAv8f16, AArch64_INS_FRINTA: frinta */ + 0, + {0}}, + + {/* AArch64_FRINTIDr, AArch64_INS_FRINTI: frinti */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTIHr, AArch64_INS_FRINTI: frinti */ + 0, + {0}}, + + {/* AArch64_FRINTISr, AArch64_INS_FRINTI: frinti */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTI_ZPmZ_D, AArch64_INS_FRINTI: frinti */ + 0, + {0}}, + + {/* AArch64_FRINTI_ZPmZ_H, AArch64_INS_FRINTI: frinti */ + 0, + {0}}, + + {/* AArch64_FRINTI_ZPmZ_S, AArch64_INS_FRINTI: frinti */ + 0, + {0}}, + + {/* AArch64_FRINTIv2f32, AArch64_INS_FRINTI: frinti */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTIv2f64, AArch64_INS_FRINTI: frinti */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTIv4f16, AArch64_INS_FRINTI: frinti */ + 0, + {0}}, + + {/* AArch64_FRINTIv4f32, AArch64_INS_FRINTI: frinti */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTIv8f16, AArch64_INS_FRINTI: frinti */ + 0, + {0}}, + + {/* AArch64_FRINTMDr, AArch64_INS_FRINTM: frintm */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTMHr, AArch64_INS_FRINTM: frintm */ + 0, + {0}}, + + {/* AArch64_FRINTMSr, AArch64_INS_FRINTM: frintm */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTM_ZPmZ_D, AArch64_INS_FRINTM: frintm */ + 0, + {0}}, + + {/* AArch64_FRINTM_ZPmZ_H, AArch64_INS_FRINTM: frintm */ + 0, + {0}}, + + {/* AArch64_FRINTM_ZPmZ_S, AArch64_INS_FRINTM: frintm */ + 0, + {0}}, + + {/* AArch64_FRINTMv2f32, AArch64_INS_FRINTM: frintm */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTMv2f64, AArch64_INS_FRINTM: frintm */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTMv4f16, AArch64_INS_FRINTM: frintm */ + 0, + {0}}, + + {/* AArch64_FRINTMv4f32, AArch64_INS_FRINTM: frintm */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTMv8f16, AArch64_INS_FRINTM: frintm */ + 0, + {0}}, + + {/* AArch64_FRINTNDr, AArch64_INS_FRINTN: frintn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTNHr, AArch64_INS_FRINTN: frintn */ + 0, + {0}}, + + {/* AArch64_FRINTNSr, AArch64_INS_FRINTN: frintn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTN_ZPmZ_D, AArch64_INS_FRINTN: frintn */ + 0, + {0}}, + + {/* AArch64_FRINTN_ZPmZ_H, AArch64_INS_FRINTN: frintn */ + 0, + {0}}, + + {/* AArch64_FRINTN_ZPmZ_S, AArch64_INS_FRINTN: frintn */ + 0, + {0}}, + + {/* AArch64_FRINTNv2f32, AArch64_INS_FRINTN: frintn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTNv2f64, AArch64_INS_FRINTN: frintn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTNv4f16, AArch64_INS_FRINTN: frintn */ + 0, + {0}}, + + {/* AArch64_FRINTNv4f32, AArch64_INS_FRINTN: frintn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTNv8f16, AArch64_INS_FRINTN: frintn */ + 0, + {0}}, + + {/* AArch64_FRINTPDr, AArch64_INS_FRINTP: frintp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTPHr, AArch64_INS_FRINTP: frintp */ + 0, + {0}}, + + {/* AArch64_FRINTPSr, AArch64_INS_FRINTP: frintp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTP_ZPmZ_D, AArch64_INS_FRINTP: frintp */ + 0, + {0}}, + + {/* AArch64_FRINTP_ZPmZ_H, AArch64_INS_FRINTP: frintp */ + 0, + {0}}, + + {/* AArch64_FRINTP_ZPmZ_S, AArch64_INS_FRINTP: frintp */ + 0, + {0}}, + + {/* AArch64_FRINTPv2f32, AArch64_INS_FRINTP: frintp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTPv2f64, AArch64_INS_FRINTP: frintp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTPv4f16, AArch64_INS_FRINTP: frintp */ + 0, + {0}}, + + {/* AArch64_FRINTPv4f32, AArch64_INS_FRINTP: frintp */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTPv8f16, AArch64_INS_FRINTP: frintp */ + 0, + {0}}, + + {/* AArch64_FRINTXDr, AArch64_INS_FRINTX: frintx */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTXHr, AArch64_INS_FRINTX: frintx */ + 0, + {0}}, + + {/* AArch64_FRINTXSr, AArch64_INS_FRINTX: frintx */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTX_ZPmZ_D, AArch64_INS_FRINTX: frintx */ + 0, + {0}}, + + {/* AArch64_FRINTX_ZPmZ_H, AArch64_INS_FRINTX: frintx */ + 0, + {0}}, + + {/* AArch64_FRINTX_ZPmZ_S, AArch64_INS_FRINTX: frintx */ + 0, + {0}}, + + {/* AArch64_FRINTXv2f32, AArch64_INS_FRINTX: frintx */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTXv2f64, AArch64_INS_FRINTX: frintx */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTXv4f16, AArch64_INS_FRINTX: frintx */ + 0, + {0}}, + + {/* AArch64_FRINTXv4f32, AArch64_INS_FRINTX: frintx */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTXv8f16, AArch64_INS_FRINTX: frintx */ + 0, + {0}}, + + {/* AArch64_FRINTZDr, AArch64_INS_FRINTZ: frintz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTZHr, AArch64_INS_FRINTZ: frintz */ + 0, + {0}}, + + {/* AArch64_FRINTZSr, AArch64_INS_FRINTZ: frintz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTZ_ZPmZ_D, AArch64_INS_FRINTZ: frintz */ + 0, + {0}}, + + {/* AArch64_FRINTZ_ZPmZ_H, AArch64_INS_FRINTZ: frintz */ + 0, + {0}}, + + {/* AArch64_FRINTZ_ZPmZ_S, AArch64_INS_FRINTZ: frintz */ + 0, + {0}}, + + {/* AArch64_FRINTZv2f32, AArch64_INS_FRINTZ: frintz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTZv2f64, AArch64_INS_FRINTZ: frintz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTZv4f16, AArch64_INS_FRINTZ: frintz */ + 0, + {0}}, + + {/* AArch64_FRINTZv4f32, AArch64_INS_FRINTZ: frintz */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRINTZv8f16, AArch64_INS_FRINTZ: frintz */ + 0, + {0}}, + + {/* AArch64_FRSQRTE_ZZ_D, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {0}}, + + {/* AArch64_FRSQRTE_ZZ_H, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {0}}, + + {/* AArch64_FRSQRTE_ZZ_S, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {0}}, + + {/* AArch64_FRSQRTEv1f16, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {0}}, + + {/* AArch64_FRSQRTEv1i32, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTEv1i64, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTEv2f32, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTEv2f64, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTEv4f16, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {0}}, + + {/* AArch64_FRSQRTEv4f32, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTEv8f16, AArch64_INS_FRSQRTE: frsqrte */ + 0, + {0}}, + + {/* AArch64_FRSQRTS16, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {0}}, + + {/* AArch64_FRSQRTS32, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTS64, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTS_ZZZ_D, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {0}}, + + {/* AArch64_FRSQRTS_ZZZ_H, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {0}}, + + {/* AArch64_FRSQRTS_ZZZ_S, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {0}}, + + {/* AArch64_FRSQRTSv2f32, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTSv2f64, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTSv4f16, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {0}}, + + {/* AArch64_FRSQRTSv4f32, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FRSQRTSv8f16, AArch64_INS_FRSQRTS: frsqrts */ + 0, + {0}}, + + {/* AArch64_FSCALE_ZPmZ_D, AArch64_INS_FSCALE: fscale */ + 0, + {0}}, + + {/* AArch64_FSCALE_ZPmZ_H, AArch64_INS_FSCALE: fscale */ + 0, + {0}}, + + {/* AArch64_FSCALE_ZPmZ_S, AArch64_INS_FSCALE: fscale */ + 0, + {0}}, + + {/* AArch64_FSQRTDr, AArch64_INS_FSQRT: fsqrt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FSQRTHr, AArch64_INS_FSQRT: fsqrt */ + 0, + {0}}, + + {/* AArch64_FSQRTSr, AArch64_INS_FSQRT: fsqrt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FSQRT_ZPmZ_D, AArch64_INS_FSQRT: fsqrt */ + 0, + {0}}, + + {/* AArch64_FSQRT_ZPmZ_H, AArch64_INS_FSQRT: fsqrt */ + 0, + {0}}, + + {/* AArch64_FSQRT_ZPmZ_S, AArch64_INS_FSQRT: fsqrt */ + 0, + {0}}, + + {/* AArch64_FSQRTv2f32, AArch64_INS_FSQRT: fsqrt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FSQRTv2f64, AArch64_INS_FSQRT: fsqrt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FSQRTv4f16, AArch64_INS_FSQRT: fsqrt */ + 0, + {0}}, + + {/* AArch64_FSQRTv4f32, AArch64_INS_FSQRT: fsqrt */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_FSQRTv8f16, AArch64_INS_FSQRT: fsqrt */ + 0, + {0}}, + + {/* AArch64_FSUBDrr, AArch64_INS_FSUB: fsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FSUBHrr, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUBR_ZPmI_D, AArch64_INS_FSUBR: fsubr */ + 0, + {0}}, + + {/* AArch64_FSUBR_ZPmI_H, AArch64_INS_FSUBR: fsubr */ + 0, + {0}}, + + {/* AArch64_FSUBR_ZPmI_S, AArch64_INS_FSUBR: fsubr */ + 0, + {0}}, + + {/* AArch64_FSUBR_ZPmZ_D, AArch64_INS_FSUBR: fsubr */ + 0, + {0}}, + + {/* AArch64_FSUBR_ZPmZ_H, AArch64_INS_FSUBR: fsubr */ + 0, + {0}}, + + {/* AArch64_FSUBR_ZPmZ_S, AArch64_INS_FSUBR: fsubr */ + 0, + {0}}, + + {/* AArch64_FSUBSrr, AArch64_INS_FSUB: fsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FSUB_ZPmI_D, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUB_ZPmI_H, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUB_ZPmI_S, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUB_ZPmZ_D, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUB_ZPmZ_H, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUB_ZPmZ_S, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUB_ZZZ_D, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUB_ZZZ_H, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUB_ZZZ_S, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUBv2f32, AArch64_INS_FSUB: fsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FSUBv2f64, AArch64_INS_FSUB: fsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FSUBv4f16, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FSUBv4f32, AArch64_INS_FSUB: fsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_FSUBv8f16, AArch64_INS_FSUB: fsub */ + 0, + {0}}, + + {/* AArch64_FTMAD_ZZI_D, AArch64_INS_FTMAD: ftmad */ + 0, + {0}}, + + {/* AArch64_FTMAD_ZZI_H, AArch64_INS_FTMAD: ftmad */ + 0, + {0}}, + + {/* AArch64_FTMAD_ZZI_S, AArch64_INS_FTMAD: ftmad */ + 0, + {0}}, + + {/* AArch64_FTSMUL_ZZZ_D, AArch64_INS_FTSMUL: ftsmul */ + 0, + {0}}, + + {/* AArch64_FTSMUL_ZZZ_H, AArch64_INS_FTSMUL: ftsmul */ + 0, + {0}}, + + {/* AArch64_FTSMUL_ZZZ_S, AArch64_INS_FTSMUL: ftsmul */ + 0, + {0}}, + + {/* AArch64_FTSSEL_ZZZ_D, AArch64_INS_FTSSEL: ftssel */ + 0, + {0}}, + + {/* AArch64_FTSSEL_ZZZ_H, AArch64_INS_FTSSEL: ftssel */ + 0, + {0}}, + + {/* AArch64_FTSSEL_ZZZ_S, AArch64_INS_FTSSEL: ftssel */ + 0, + {0}}, + + {/* AArch64_GLD1B_D_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_GLD1B_D_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_GLD1B_D_SXTW_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_GLD1B_D_UXTW_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_GLD1B_S_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_GLD1B_S_SXTW_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_GLD1B_S_UXTW_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_GLD1D_IMM_REAL, AArch64_INS_LD1D: ld1d */ + 0, + {0}}, + + {/* AArch64_GLD1D_REAL, AArch64_INS_LD1D: ld1d */ + 0, + {0}}, + + {/* AArch64_GLD1D_SCALED_REAL, AArch64_INS_LD1D: ld1d */ + 0, + {0}}, + + {/* AArch64_GLD1D_SXTW_REAL, AArch64_INS_LD1D: ld1d */ + 0, + {0}}, + + {/* AArch64_GLD1D_SXTW_SCALED_REAL, AArch64_INS_LD1D: ld1d */ + 0, + {0}}, + + {/* AArch64_GLD1D_UXTW_REAL, AArch64_INS_LD1D: ld1d */ + 0, + {0}}, + + {/* AArch64_GLD1D_UXTW_SCALED_REAL, AArch64_INS_LD1D: ld1d */ + 0, + {0}}, + + {/* AArch64_GLD1H_D_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_D_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_D_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_D_SXTW_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_D_SXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_D_UXTW_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_D_UXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_S_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_S_SXTW_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_S_SXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_S_UXTW_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1H_S_UXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_GLD1SB_D_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_GLD1SB_D_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_GLD1SB_D_SXTW_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_GLD1SB_D_UXTW_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_GLD1SB_S_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_GLD1SB_S_SXTW_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_GLD1SB_S_UXTW_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_GLD1SH_D_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_D_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_D_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_D_SXTW_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_D_SXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_D_UXTW_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_D_UXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_S_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_S_SXTW_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_S_SXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_S_UXTW_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SH_S_UXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_GLD1SW_D_IMM_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + {0}}, + + {/* AArch64_GLD1SW_D_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + {0}}, + + {/* AArch64_GLD1SW_D_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + {0}}, + + {/* AArch64_GLD1SW_D_SXTW_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + {0}}, + + {/* AArch64_GLD1SW_D_SXTW_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + {0}}, + + {/* AArch64_GLD1SW_D_UXTW_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + {0}}, + + {/* AArch64_GLD1SW_D_UXTW_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + {0}}, + + {/* AArch64_GLD1W_D_IMM_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_D_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_D_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_D_SXTW_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_D_SXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_D_UXTW_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_D_UXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_IMM_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_SXTW_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_SXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_UXTW_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLD1W_UXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1B_D_IMM_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_GLDFF1B_D_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_GLDFF1B_D_SXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_GLDFF1B_D_UXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_GLDFF1B_S_IMM_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_GLDFF1B_S_SXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_GLDFF1B_S_UXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_GLDFF1D_IMM_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + {0}}, + + {/* AArch64_GLDFF1D_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + {0}}, + + {/* AArch64_GLDFF1D_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + {0}}, + + {/* AArch64_GLDFF1D_SXTW_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + {0}}, + + {/* AArch64_GLDFF1D_SXTW_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + {0}}, + + {/* AArch64_GLDFF1D_UXTW_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + {0}}, + + {/* AArch64_GLDFF1D_UXTW_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_D_IMM_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_D_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_D_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_D_SXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_D_UXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_S_IMM_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_S_SXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_S_SXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_S_UXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1H_S_UXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_GLDFF1SB_D_IMM_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_GLDFF1SB_D_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_GLDFF1SB_D_SXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_GLDFF1SB_D_UXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_GLDFF1SB_S_IMM_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_GLDFF1SB_S_SXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_GLDFF1SB_S_UXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_D_IMM_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_D_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_D_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_D_SXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_D_UXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_S_IMM_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_S_SXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_S_SXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_S_UXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SH_S_UXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_GLDFF1SW_D_IMM_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + {0}}, + + {/* AArch64_GLDFF1SW_D_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + {0}}, + + {/* AArch64_GLDFF1SW_D_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + {0}}, + + {/* AArch64_GLDFF1SW_D_SXTW_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + {0}}, + + {/* AArch64_GLDFF1SW_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + {0}}, + + {/* AArch64_GLDFF1SW_D_UXTW_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + {0}}, + + {/* AArch64_GLDFF1SW_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_D_IMM_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_D_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_D_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_D_SXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_D_UXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_IMM_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_SXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_SXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_UXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_GLDFF1W_UXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_HINT, AArch64_INS_CSDB: csdb */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_HLT, AArch64_INS_HLT: hlt */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_HVC, AArch64_INS_HVC: hvc */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_INCB_XPiI, AArch64_INS_INCB: incb */ + 0, + {0}}, + + {/* AArch64_INCD_XPiI, AArch64_INS_INCD: incd */ + 0, + {0}}, + + {/* AArch64_INCD_ZPiI, AArch64_INS_INCD: incd */ + 0, + {0}}, + + {/* AArch64_INCH_XPiI, AArch64_INS_INCH: inch */ + 0, + {0}}, + + {/* AArch64_INCH_ZPiI, AArch64_INS_INCH: inch */ + 0, + {0}}, + + {/* AArch64_INCP_XP_B, AArch64_INS_INCP: incp */ + 0, + {0}}, + + {/* AArch64_INCP_XP_D, AArch64_INS_INCP: incp */ + 0, + {0}}, + + {/* AArch64_INCP_XP_H, AArch64_INS_INCP: incp */ + 0, + {0}}, + + {/* AArch64_INCP_XP_S, AArch64_INS_INCP: incp */ + 0, + {0}}, + + {/* AArch64_INCP_ZP_D, AArch64_INS_INCP: incp */ + 0, + {0}}, + + {/* AArch64_INCP_ZP_H, AArch64_INS_INCP: incp */ + 0, + {0}}, + + {/* AArch64_INCP_ZP_S, AArch64_INS_INCP: incp */ + 0, + {0}}, + + {/* AArch64_INCW_XPiI, AArch64_INS_INCW: incw */ + 0, + {0}}, + + {/* AArch64_INCW_ZPiI, AArch64_INS_INCW: incw */ + 0, + {0}}, + + {/* AArch64_INDEX_II_B, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_II_D, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_II_H, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_II_S, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_IR_B, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_IR_D, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_IR_H, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_IR_S, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_RI_B, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_RI_D, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_RI_H, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_RI_S, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_RR_B, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_RR_D, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_RR_H, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INDEX_RR_S, AArch64_INS_INDEX: index */ + 0, + {0}}, + + {/* AArch64_INSR_ZR_B, AArch64_INS_INSR: insr */ + 0, + {0}}, + + {/* AArch64_INSR_ZR_D, AArch64_INS_INSR: insr */ + 0, + {0}}, + + {/* AArch64_INSR_ZR_H, AArch64_INS_INSR: insr */ + 0, + {0}}, + + {/* AArch64_INSR_ZR_S, AArch64_INS_INSR: insr */ + 0, + {0}}, + + {/* AArch64_INSR_ZV_B, AArch64_INS_INSR: insr */ + 0, + {0}}, + + {/* AArch64_INSR_ZV_D, AArch64_INS_INSR: insr */ + 0, + {0}}, + + {/* AArch64_INSR_ZV_H, AArch64_INS_INSR: insr */ + 0, + {0}}, + + {/* AArch64_INSR_ZV_S, AArch64_INS_INSR: insr */ + 0, + {0}}, + + {/* AArch64_INSvi16gpr, AArch64_INS_INS: ins */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_INSvi16lane, AArch64_INS_INS: ins */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_INSvi32gpr, AArch64_INS_INS: ins */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_INSvi32lane, AArch64_INS_INS: ins */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_INSvi64gpr, AArch64_INS_INS: ins */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_INSvi64lane, AArch64_INS_INS: ins */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_INSvi8gpr, AArch64_INS_INS: ins */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_INSvi8lane, AArch64_INS_INS: ins */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_ISB, AArch64_INS_ISB: isb */ + 0, + {0}}, + + {/* AArch64_LASTA_RPZ_B, AArch64_INS_LASTA: lasta */ + 0, + {0}}, + + {/* AArch64_LASTA_RPZ_D, AArch64_INS_LASTA: lasta */ + 0, + {0}}, + + {/* AArch64_LASTA_RPZ_H, AArch64_INS_LASTA: lasta */ + 0, + {0}}, + + {/* AArch64_LASTA_RPZ_S, AArch64_INS_LASTA: lasta */ + 0, + {0}}, + + {/* AArch64_LASTA_VPZ_B, AArch64_INS_LASTA: lasta */ + 0, + {0}}, + + {/* AArch64_LASTA_VPZ_D, AArch64_INS_LASTA: lasta */ + 0, + {0}}, + + {/* AArch64_LASTA_VPZ_H, AArch64_INS_LASTA: lasta */ + 0, + {0}}, + + {/* AArch64_LASTA_VPZ_S, AArch64_INS_LASTA: lasta */ + 0, + {0}}, + + {/* AArch64_LASTB_RPZ_B, AArch64_INS_LASTB: lastb */ + 0, + {0}}, + + {/* AArch64_LASTB_RPZ_D, AArch64_INS_LASTB: lastb */ + 0, + {0}}, + + {/* AArch64_LASTB_RPZ_H, AArch64_INS_LASTB: lastb */ + 0, + {0}}, + + {/* AArch64_LASTB_RPZ_S, AArch64_INS_LASTB: lastb */ + 0, + {0}}, + + {/* AArch64_LASTB_VPZ_B, AArch64_INS_LASTB: lastb */ + 0, + {0}}, + + {/* AArch64_LASTB_VPZ_D, AArch64_INS_LASTB: lastb */ + 0, + {0}}, + + {/* AArch64_LASTB_VPZ_H, AArch64_INS_LASTB: lastb */ + 0, + {0}}, + + {/* AArch64_LASTB_VPZ_S, AArch64_INS_LASTB: lastb */ + 0, + {0}}, + + {/* AArch64_LD1B, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_LD1B_D, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_LD1B_D_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_LD1B_H, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_LD1B_H_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_LD1B_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_LD1B_S, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_LD1B_S_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + {0}}, + + {/* AArch64_LD1D, AArch64_INS_LD1D: ld1d */ + 0, + {0}}, + + {/* AArch64_LD1D_IMM_REAL, AArch64_INS_LD1D: ld1d */ + 0, + {0}}, + + {/* AArch64_LD1Fourv16b, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv16b_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv1d, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv1d_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv2d, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv2d_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv2s, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv2s_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv4h, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv4h_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv4s, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv4s_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv8b, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv8b_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv8h, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Fourv8h_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1H, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_LD1H_D, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_LD1H_D_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_LD1H_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_LD1H_S, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_LD1H_S_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + {0}}, + + {/* AArch64_LD1Onev16b, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev16b_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev1d, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev1d_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev2d, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev2d_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LD1Onev2s, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev2s_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev4h, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev4h_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev4s, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev4s_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev8b, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev8b_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev8h, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Onev8h_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1RB_D_IMM, AArch64_INS_LD1RB: ld1rb */ + 0, + {0}}, + + {/* AArch64_LD1RB_H_IMM, AArch64_INS_LD1RB: ld1rb */ + 0, + {0}}, + + {/* AArch64_LD1RB_IMM, AArch64_INS_LD1RB: ld1rb */ + 0, + {0}}, + + {/* AArch64_LD1RB_S_IMM, AArch64_INS_LD1RB: ld1rb */ + 0, + {0}}, + + {/* AArch64_LD1RD_IMM, AArch64_INS_LD1RD: ld1rd */ + 0, + {0}}, + + {/* AArch64_LD1RH_D_IMM, AArch64_INS_LD1RH: ld1rh */ + 0, + {0}}, + + {/* AArch64_LD1RH_IMM, AArch64_INS_LD1RH: ld1rh */ + 0, + {0}}, + + {/* AArch64_LD1RH_S_IMM, AArch64_INS_LD1RH: ld1rh */ + 0, + {0}}, + + {/* AArch64_LD1RQ_B, AArch64_INS_LD1RQB: ld1rqb */ + 0, + {0}}, + + {/* AArch64_LD1RQ_B_IMM, AArch64_INS_LD1RQB: ld1rqb */ + 0, + {0}}, + + {/* AArch64_LD1RQ_D, AArch64_INS_LD1RQD: ld1rqd */ + 0, + {0}}, + + {/* AArch64_LD1RQ_D_IMM, AArch64_INS_LD1RQD: ld1rqd */ + 0, + {0}}, + + {/* AArch64_LD1RQ_H, AArch64_INS_LD1RQH: ld1rqh */ + 0, + {0}}, + + {/* AArch64_LD1RQ_H_IMM, AArch64_INS_LD1RQH: ld1rqh */ + 0, + {0}}, + + {/* AArch64_LD1RQ_W, AArch64_INS_LD1RQW: ld1rqw */ + 0, + {0}}, + + {/* AArch64_LD1RQ_W_IMM, AArch64_INS_LD1RQW: ld1rqw */ + 0, + {0}}, + + {/* AArch64_LD1RSB_D_IMM, AArch64_INS_LD1RSB: ld1rsb */ + 0, + {0}}, + + {/* AArch64_LD1RSB_H_IMM, AArch64_INS_LD1RSB: ld1rsb */ + 0, + {0}}, + + {/* AArch64_LD1RSB_S_IMM, AArch64_INS_LD1RSB: ld1rsb */ + 0, + {0}}, + + {/* AArch64_LD1RSH_D_IMM, AArch64_INS_LD1RSH: ld1rsh */ + 0, + {0}}, + + {/* AArch64_LD1RSH_S_IMM, AArch64_INS_LD1RSH: ld1rsh */ + 0, + {0}}, + + {/* AArch64_LD1RSW_IMM, AArch64_INS_LD1RSW: ld1rsw */ + 0, + {0}}, + + {/* AArch64_LD1RW_D_IMM, AArch64_INS_LD1RW: ld1rw */ + 0, + {0}}, + + {/* AArch64_LD1RW_IMM, AArch64_INS_LD1RW: ld1rw */ + 0, + {0}}, + + {/* AArch64_LD1Rv16b, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv16b_POST, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv1d, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv1d_POST, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv2d, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv2d_POST, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv2s, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv2s_POST, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv4h, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv4h_POST, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv4s, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv4s_POST, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv8b, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv8b_POST, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv8h, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Rv8h_POST, AArch64_INS_LD1R: ld1r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1SB_D, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_LD1SB_D_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_LD1SB_H, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_LD1SB_H_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_LD1SB_S, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_LD1SB_S_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + {0}}, + + {/* AArch64_LD1SH_D, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_LD1SH_D_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_LD1SH_S, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_LD1SH_S_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + {0}}, + + {/* AArch64_LD1SW_D, AArch64_INS_LD1SW: ld1sw */ + 0, + {0}}, + + {/* AArch64_LD1SW_D_IMM_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + {0}}, + + {/* AArch64_LD1Threev16b, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev16b_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev1d, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev1d_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev2d, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev2d_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev2s, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev2s_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev4h, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev4h_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev4s, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev4s_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev8b, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev8b_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev8h, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Threev8h_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov16b, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov16b_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov1d, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov1d_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov2d, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov2d_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov2s, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov2s_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov4h, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov4h_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov4s, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov4s_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov8b, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov8b_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov8h, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1Twov8h_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1W, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_LD1W_D, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_LD1W_D_IMM_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_LD1W_IMM_REAL, AArch64_INS_LD1W: ld1w */ + 0, + {0}}, + + {/* AArch64_LD1i16, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1i16_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1i32, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1i32_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1i64, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1i64_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD1i8, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD1i8_POST, AArch64_INS_LD1: ld1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2B, AArch64_INS_LD2B: ld2b */ + 0, + {0}}, + + {/* AArch64_LD2B_IMM, AArch64_INS_LD2B: ld2b */ + 0, + {0}}, + + {/* AArch64_LD2D, AArch64_INS_LD2D: ld2d */ + 0, + {0}}, + + {/* AArch64_LD2D_IMM, AArch64_INS_LD2D: ld2d */ + 0, + {0}}, + + {/* AArch64_LD2H, AArch64_INS_LD2H: ld2h */ + 0, + {0}}, + + {/* AArch64_LD2H_IMM, AArch64_INS_LD2H: ld2h */ + 0, + {0}}, + + {/* AArch64_LD2Rv16b, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv16b_POST, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv1d, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv1d_POST, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv2d, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv2d_POST, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv2s, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv2s_POST, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv4h, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv4h_POST, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv4s, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv4s_POST, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv8b, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv8b_POST, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv8h, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Rv8h_POST, AArch64_INS_LD2R: ld2r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov16b, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov16b_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov2d, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov2d_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov2s, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov2s_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov4h, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov4h_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov4s, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov4s_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov8b, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov8b_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov8h, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2Twov8h_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2W, AArch64_INS_LD2W: ld2w */ + 0, + {0}}, + + {/* AArch64_LD2W_IMM, AArch64_INS_LD2W: ld2w */ + 0, + {0}}, + + {/* AArch64_LD2i16, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2i16_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2i32, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2i32_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2i64, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2i64_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD2i8, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD2i8_POST, AArch64_INS_LD2: ld2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3B, AArch64_INS_LD3B: ld3b */ + 0, + {0}}, + + {/* AArch64_LD3B_IMM, AArch64_INS_LD3B: ld3b */ + 0, + {0}}, + + {/* AArch64_LD3D, AArch64_INS_LD3D: ld3d */ + 0, + {0}}, + + {/* AArch64_LD3D_IMM, AArch64_INS_LD3D: ld3d */ + 0, + {0}}, + + {/* AArch64_LD3H, AArch64_INS_LD3H: ld3h */ + 0, + {0}}, + + {/* AArch64_LD3H_IMM, AArch64_INS_LD3H: ld3h */ + 0, + {0}}, + + {/* AArch64_LD3Rv16b, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv16b_POST, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv1d, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv1d_POST, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv2d, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv2d_POST, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv2s, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv2s_POST, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv4h, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv4h_POST, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv4s, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv4s_POST, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv8b, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv8b_POST, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv8h, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Rv8h_POST, AArch64_INS_LD3R: ld3r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev16b, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev16b_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev2d, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev2d_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev2s, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev2s_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev4h, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev4h_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev4s, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev4s_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev8b, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev8b_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev8h, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3Threev8h_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD3W, AArch64_INS_LD3W: ld3w */ + 0, + {0}}, + + {/* AArch64_LD3W_IMM, AArch64_INS_LD3W: ld3w */ + 0, + {0}}, + + {/* AArch64_LD3i16, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3i16_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_LD3i32, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3i32_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_LD3i64, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3i64_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_LD3i8, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD3i8_POST, AArch64_INS_LD3: ld3 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_LD4B, AArch64_INS_LD4B: ld4b */ + 0, + {0}}, + + {/* AArch64_LD4B_IMM, AArch64_INS_LD4B: ld4b */ + 0, + {0}}, + + {/* AArch64_LD4D, AArch64_INS_LD4D: ld4d */ + 0, + {0}}, + + {/* AArch64_LD4D_IMM, AArch64_INS_LD4D: ld4d */ + 0, + {0}}, + + {/* AArch64_LD4Fourv16b, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv16b_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv2d, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv2d_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv2s, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv2s_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv4h, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv4h_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv4s, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv4s_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv8b, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv8b_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv8h, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Fourv8h_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4H, AArch64_INS_LD4H: ld4h */ + 0, + {0}}, + + {/* AArch64_LD4H_IMM, AArch64_INS_LD4H: ld4h */ + 0, + {0}}, + + {/* AArch64_LD4Rv16b, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv16b_POST, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv1d, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv1d_POST, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv2d, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv2d_POST, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv2s, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv2s_POST, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv4h, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv4h_POST, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv4s, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv4s_POST, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv8b, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv8b_POST, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv8h, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4Rv8h_POST, AArch64_INS_LD4R: ld4r */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LD4W, AArch64_INS_LD4W: ld4w */ + 0, + {0}}, + + {/* AArch64_LD4W_IMM, AArch64_INS_LD4W: ld4w */ + 0, + {0}}, + + {/* AArch64_LD4i16, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4i16_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_LD4i32, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4i32_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_LD4i64, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4i64_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_LD4i8, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_LD4i8_POST, AArch64_INS_LD4: ld4 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_LDADDAB, AArch64_INS_LDADDAB: ldaddab */ + 0, + {0}}, + + {/* AArch64_LDADDAH, AArch64_INS_LDADDAH: ldaddah */ + 0, + {0}}, + + {/* AArch64_LDADDALB, AArch64_INS_LDADDALB: ldaddalb */ + 0, + {0}}, + + {/* AArch64_LDADDALH, AArch64_INS_LDADDALH: ldaddalh */ + 0, + {0}}, + + {/* AArch64_LDADDALW, AArch64_INS_LDADDAL: ldaddal */ + 0, + {0}}, + + {/* AArch64_LDADDALX, AArch64_INS_LDADDAL: ldaddal */ + 0, + {0}}, + + {/* AArch64_LDADDAW, AArch64_INS_LDADDA: ldadda */ + 0, + {0}}, + + {/* AArch64_LDADDAX, AArch64_INS_LDADDA: ldadda */ + 0, + {0}}, + + {/* AArch64_LDADDB, AArch64_INS_LDADDB: ldaddb */ + 0, + {0}}, + + {/* AArch64_LDADDH, AArch64_INS_LDADDH: ldaddh */ + 0, + {0}}, + + {/* AArch64_LDADDLB, AArch64_INS_LDADDLB: ldaddlb */ + 0, + {0}}, + + {/* AArch64_LDADDLH, AArch64_INS_LDADDLH: ldaddlh */ + 0, + {0}}, + + {/* AArch64_LDADDLW, AArch64_INS_LDADDL: ldaddl */ + 0, + {0}}, + + {/* AArch64_LDADDLX, AArch64_INS_LDADDL: ldaddl */ + 0, + {0}}, + + {/* AArch64_LDADDW, AArch64_INS_LDADD: ldadd */ + 0, + {0}}, + + {/* AArch64_LDADDX, AArch64_INS_LDADD: ldadd */ + 0, + {0}}, + + {/* AArch64_LDAPRB, AArch64_INS_LDAPRB: ldaprb */ + 0, + {0}}, + + {/* AArch64_LDAPRH, AArch64_INS_LDAPRH: ldaprh */ + 0, + {0}}, + + {/* AArch64_LDAPRW, AArch64_INS_LDAPR: ldapr */ + 0, + {0}}, + + {/* AArch64_LDAPRX, AArch64_INS_LDAPR: ldapr */ + 0, + {0}}, + + {/* AArch64_LDAPURBi, AArch64_INS_LDAPURB: ldapurb */ + 0, + {0}}, + + {/* AArch64_LDAPURHi, AArch64_INS_LDAPURH: ldapurh */ + 0, + {0}}, + + {/* AArch64_LDAPURSBWi, AArch64_INS_LDAPURSB: ldapursb */ + 0, + {0}}, + + {/* AArch64_LDAPURSBXi, AArch64_INS_LDAPURSB: ldapursb */ + 0, + {0}}, + + {/* AArch64_LDAPURSHWi, AArch64_INS_LDAPURSH: ldapursh */ + 0, + {0}}, + + {/* AArch64_LDAPURSHXi, AArch64_INS_LDAPURSH: ldapursh */ + 0, + {0}}, + + {/* AArch64_LDAPURSWi, AArch64_INS_LDAPURSW: ldapursw */ + 0, + {0}}, + + {/* AArch64_LDAPURXi, AArch64_INS_LDAPUR: ldapur */ + 0, + {0}}, + + {/* AArch64_LDAPURi, AArch64_INS_LDAPUR: ldapur */ + 0, + {0}}, + + {/* AArch64_LDARB, AArch64_INS_LDARB: ldarb */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDARH, AArch64_INS_LDARH: ldarh */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDARW, AArch64_INS_LDAR: ldar */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDARX, AArch64_INS_LDAR: ldar */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDAXPW, AArch64_INS_LDAXP: ldaxp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDAXPX, AArch64_INS_LDAXP: ldaxp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDAXRB, AArch64_INS_LDAXRB: ldaxrb */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDAXRH, AArch64_INS_LDAXRH: ldaxrh */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDAXRW, AArch64_INS_LDAXR: ldaxr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDAXRX, AArch64_INS_LDAXR: ldaxr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDCLRAB, AArch64_INS_LDCLRAB: ldclrab */ + 0, + {0}}, + + {/* AArch64_LDCLRAH, AArch64_INS_LDCLRAH: ldclrah */ + 0, + {0}}, + + {/* AArch64_LDCLRALB, AArch64_INS_LDCLRALB: ldclralb */ + 0, + {0}}, + + {/* AArch64_LDCLRALH, AArch64_INS_LDCLRALH: ldclralh */ + 0, + {0}}, + + {/* AArch64_LDCLRALW, AArch64_INS_LDCLRAL: ldclral */ + 0, + {0}}, + + {/* AArch64_LDCLRALX, AArch64_INS_LDCLRAL: ldclral */ + 0, + {0}}, + + {/* AArch64_LDCLRAW, AArch64_INS_LDCLRA: ldclra */ + 0, + {0}}, + + {/* AArch64_LDCLRAX, AArch64_INS_LDCLRA: ldclra */ + 0, + {0}}, + + {/* AArch64_LDCLRB, AArch64_INS_LDCLRB: ldclrb */ + 0, + {0}}, + + {/* AArch64_LDCLRH, AArch64_INS_LDCLRH: ldclrh */ + 0, + {0}}, + + {/* AArch64_LDCLRLB, AArch64_INS_LDCLRLB: ldclrlb */ + 0, + {0}}, + + {/* AArch64_LDCLRLH, AArch64_INS_LDCLRLH: ldclrlh */ + 0, + {0}}, + + {/* AArch64_LDCLRLW, AArch64_INS_LDCLRL: ldclrl */ + 0, + {0}}, + + {/* AArch64_LDCLRLX, AArch64_INS_LDCLRL: ldclrl */ + 0, + {0}}, + + {/* AArch64_LDCLRW, AArch64_INS_LDCLR: ldclr */ + 0, + {0}}, + + {/* AArch64_LDCLRX, AArch64_INS_LDCLR: ldclr */ + 0, + {0}}, + + {/* AArch64_LDEORAB, AArch64_INS_LDEORAB: ldeorab */ + 0, + {0}}, + + {/* AArch64_LDEORAH, AArch64_INS_LDEORAH: ldeorah */ + 0, + {0}}, + + {/* AArch64_LDEORALB, AArch64_INS_LDEORALB: ldeoralb */ + 0, + {0}}, + + {/* AArch64_LDEORALH, AArch64_INS_LDEORALH: ldeoralh */ + 0, + {0}}, + + {/* AArch64_LDEORALW, AArch64_INS_LDEORAL: ldeoral */ + 0, + {0}}, + + {/* AArch64_LDEORALX, AArch64_INS_LDEORAL: ldeoral */ + 0, + {0}}, + + {/* AArch64_LDEORAW, AArch64_INS_LDEORA: ldeora */ + 0, + {0}}, + + {/* AArch64_LDEORAX, AArch64_INS_LDEORA: ldeora */ + 0, + {0}}, + + {/* AArch64_LDEORB, AArch64_INS_LDEORB: ldeorb */ + 0, + {0}}, + + {/* AArch64_LDEORH, AArch64_INS_LDEORH: ldeorh */ + 0, + {0}}, + + {/* AArch64_LDEORLB, AArch64_INS_LDEORLB: ldeorlb */ + 0, + {0}}, + + {/* AArch64_LDEORLH, AArch64_INS_LDEORLH: ldeorlh */ + 0, + {0}}, + + {/* AArch64_LDEORLW, AArch64_INS_LDEORL: ldeorl */ + 0, + {0}}, + + {/* AArch64_LDEORLX, AArch64_INS_LDEORL: ldeorl */ + 0, + {0}}, + + {/* AArch64_LDEORW, AArch64_INS_LDEOR: ldeor */ + 0, + {0}}, + + {/* AArch64_LDEORX, AArch64_INS_LDEOR: ldeor */ + 0, + {0}}, + + {/* AArch64_LDFF1B_D_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_LDFF1B_H_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_LDFF1B_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_LDFF1B_S_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + {0}}, + + {/* AArch64_LDFF1D_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + {0}}, + + {/* AArch64_LDFF1H_D_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_LDFF1H_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_LDFF1H_S_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + {0}}, + + {/* AArch64_LDFF1SB_D_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_LDFF1SB_H_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_LDFF1SB_S_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + {0}}, + + {/* AArch64_LDFF1SH_D_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_LDFF1SH_S_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + {0}}, + + {/* AArch64_LDFF1SW_D_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + {0}}, + + {/* AArch64_LDFF1W_D_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_LDFF1W_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + {0}}, + + {/* AArch64_LDLARB, AArch64_INS_LDLARB: ldlarb */ + 0, + {0}}, + + {/* AArch64_LDLARH, AArch64_INS_LDLARH: ldlarh */ + 0, + {0}}, + + {/* AArch64_LDLARW, AArch64_INS_LDLAR: ldlar */ + 0, + {0}}, + + {/* AArch64_LDLARX, AArch64_INS_LDLAR: ldlar */ + 0, + {0}}, + + {/* AArch64_LDNF1B_D_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ + 0, + {0}}, + + {/* AArch64_LDNF1B_H_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ + 0, + {0}}, + + {/* AArch64_LDNF1B_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ + 0, + {0}}, + + {/* AArch64_LDNF1B_S_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ + 0, + {0}}, + + {/* AArch64_LDNF1D_IMM_REAL, AArch64_INS_LDNF1D: ldnf1d */ + 0, + {0}}, + + {/* AArch64_LDNF1H_D_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ + 0, + {0}}, + + {/* AArch64_LDNF1H_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ + 0, + {0}}, + + {/* AArch64_LDNF1H_S_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ + 0, + {0}}, + + {/* AArch64_LDNF1SB_D_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ + 0, + {0}}, + + {/* AArch64_LDNF1SB_H_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ + 0, + {0}}, + + {/* AArch64_LDNF1SB_S_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ + 0, + {0}}, + + {/* AArch64_LDNF1SH_D_IMM_REAL, AArch64_INS_LDNF1SH: ldnf1sh */ + 0, + {0}}, + + {/* AArch64_LDNF1SH_S_IMM_REAL, AArch64_INS_LDNF1SH: ldnf1sh */ + 0, + {0}}, + + {/* AArch64_LDNF1SW_D_IMM_REAL, AArch64_INS_LDNF1SW: ldnf1sw */ + 0, + {0}}, + + {/* AArch64_LDNF1W_D_IMM_REAL, AArch64_INS_LDNF1W: ldnf1w */ + 0, + {0}}, + + {/* AArch64_LDNF1W_IMM_REAL, AArch64_INS_LDNF1W: ldnf1w */ + 0, + {0}}, + + {/* AArch64_LDNPDi, AArch64_INS_LDNP: ldnp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDNPQi, AArch64_INS_LDNP: ldnp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDNPSi, AArch64_INS_LDNP: ldnp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDNPWi, AArch64_INS_LDNP: ldnp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDNPXi, AArch64_INS_LDNP: ldnp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDNT1B_ZRI, AArch64_INS_LDNT1B: ldnt1b */ + 0, + {0}}, + + {/* AArch64_LDNT1B_ZRR, AArch64_INS_LDNT1B: ldnt1b */ + 0, + {0}}, + + {/* AArch64_LDNT1D_ZRI, AArch64_INS_LDNT1D: ldnt1d */ + 0, + {0}}, + + {/* AArch64_LDNT1D_ZRR, AArch64_INS_LDNT1D: ldnt1d */ + 0, + {0}}, + + {/* AArch64_LDNT1H_ZRI, AArch64_INS_LDNT1H: ldnt1h */ + 0, + {0}}, + + {/* AArch64_LDNT1H_ZRR, AArch64_INS_LDNT1H: ldnt1h */ + 0, + {0}}, + + {/* AArch64_LDNT1W_ZRI, AArch64_INS_LDNT1W: ldnt1w */ + 0, + {0}}, + + {/* AArch64_LDNT1W_ZRR, AArch64_INS_LDNT1W: ldnt1w */ + 0, + {0}}, + + {/* AArch64_LDPDi, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPDpost, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPDpre, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPQi, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPQpost, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPQpre, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPSWi, AArch64_INS_LDPSW: ldpsw */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPSWpost, AArch64_INS_LDPSW: ldpsw */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPSWpre, AArch64_INS_LDPSW: ldpsw */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPSi, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPSpost, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPSpre, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPWi, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPWpost, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPWpre, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPXi, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPXpost, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDPXpre, AArch64_INS_LDP: ldp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRAAindexed, AArch64_INS_LDRAA: ldraa */ + 0, + {0}}, + + {/* AArch64_LDRAAwriteback, AArch64_INS_LDRAA: ldraa */ + 0, + {0}}, + + {/* AArch64_LDRABindexed, AArch64_INS_LDRAB: ldrab */ + 0, + {0}}, + + {/* AArch64_LDRABwriteback, AArch64_INS_LDRAB: ldrab */ + 0, + {0}}, + + {/* AArch64_LDRBBpost, AArch64_INS_LDRB: ldrb */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRBBpre, AArch64_INS_LDRB: ldrb */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRBBroW, AArch64_INS_LDRB: ldrb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRBBroX, AArch64_INS_LDRB: ldrb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRBBui, AArch64_INS_LDRB: ldrb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRBpost, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRBpre, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRBroW, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRBroX, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRBui, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRDl, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDRDpost, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRDpre, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRDroW, AArch64_INS_LDR: ldr */ + 00, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRDroX, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRDui, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRHHpost, AArch64_INS_LDRH: ldrh */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRHHpre, AArch64_INS_LDRH: ldrh */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRHHroW, AArch64_INS_LDRH: ldrh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRHHroX, AArch64_INS_LDRH: ldrh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRHHui, AArch64_INS_LDRH: ldrh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRHpost, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRHpre, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRHroW, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRHroX, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRHui, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRQl, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDRQpost, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRQpre, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRQroW, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRQroX, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRQui, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSBWpost, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSBWpre, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSBWroW, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSBWroX, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSBWui, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSBXpost, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSBXpre, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSBXroW, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSBXroX, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSBXui, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSHWpost, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSHWpre, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSHWroW, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSHWroX, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSHWui, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSHXpost, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSHXpre, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSHXroW, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSHXroX, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSHXui, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSWl, AArch64_INS_LDRSW: ldrsw */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDRSWpost, AArch64_INS_LDRSW: ldrsw */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSWpre, AArch64_INS_LDRSW: ldrsw */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSWroW, AArch64_INS_LDRSW: ldrsw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSWroX, AArch64_INS_LDRSW: ldrsw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSWui, AArch64_INS_LDRSW: ldrsw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSl, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDRSpost, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSpre, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRSroW, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSroX, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRSui, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRWl, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDRWpost, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRWpre, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRWroW, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRWroX, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRWui, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRXl, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDRXpost, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRXpre, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDRXroW, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRXroX, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_LDRXui, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDR_PXI, AArch64_INS_LDR: ldr */ + 0, + {0}}, + + {/* AArch64_LDR_ZXI, AArch64_INS_LDR: ldr */ + 0, + {0}}, + + {/* AArch64_LDSETAB, AArch64_INS_LDSETAB: ldsetab */ + 0, + {0}}, + + {/* AArch64_LDSETAH, AArch64_INS_LDSETAH: ldsetah */ + 0, + {0}}, + + {/* AArch64_LDSETALB, AArch64_INS_LDSETALB: ldsetalb */ + 0, + {0}}, + + {/* AArch64_LDSETALH, AArch64_INS_LDSETALH: ldsetalh */ + 0, + {0}}, + + {/* AArch64_LDSETALW, AArch64_INS_LDSETAL: ldsetal */ + 0, + {0}}, + + {/* AArch64_LDSETALX, AArch64_INS_LDSETAL: ldsetal */ + 0, + {0}}, + + {/* AArch64_LDSETAW, AArch64_INS_LDSETA: ldseta */ + 0, + {0}}, + + {/* AArch64_LDSETAX, AArch64_INS_LDSETA: ldseta */ + 0, + {0}}, + + {/* AArch64_LDSETB, AArch64_INS_LDSETB: ldsetb */ + 0, + {0}}, + + {/* AArch64_LDSETH, AArch64_INS_LDSETH: ldseth */ + 0, + {0}}, + + {/* AArch64_LDSETLB, AArch64_INS_LDSETLB: ldsetlb */ + 0, + {0}}, + + {/* AArch64_LDSETLH, AArch64_INS_LDSETLH: ldsetlh */ + 0, + {0}}, + + {/* AArch64_LDSETLW, AArch64_INS_LDSETL: ldsetl */ + 0, + {0}}, + + {/* AArch64_LDSETLX, AArch64_INS_LDSETL: ldsetl */ + 0, + {0}}, + + {/* AArch64_LDSETW, AArch64_INS_LDSET: ldset */ + 0, + {0}}, + + {/* AArch64_LDSETX, AArch64_INS_LDSET: ldset */ + 0, + {0}}, + + {/* AArch64_LDSMAXAB, AArch64_INS_LDSMAXAB: ldsmaxab */ + 0, + {0}}, + + {/* AArch64_LDSMAXAH, AArch64_INS_LDSMAXAH: ldsmaxah */ + 0, + {0}}, + + {/* AArch64_LDSMAXALB, AArch64_INS_LDSMAXALB: ldsmaxalb */ + 0, + {0}}, + + {/* AArch64_LDSMAXALH, AArch64_INS_LDSMAXALH: ldsmaxalh */ + 0, + {0}}, + + {/* AArch64_LDSMAXALW, AArch64_INS_LDSMAXAL: ldsmaxal */ + 0, + {0}}, + + {/* AArch64_LDSMAXALX, AArch64_INS_LDSMAXAL: ldsmaxal */ + 0, + {0}}, + + {/* AArch64_LDSMAXAW, AArch64_INS_LDSMAXA: ldsmaxa */ + 0, + {0}}, + + {/* AArch64_LDSMAXAX, AArch64_INS_LDSMAXA: ldsmaxa */ + 0, + {0}}, + + {/* AArch64_LDSMAXB, AArch64_INS_LDSMAXB: ldsmaxb */ + 0, + {0}}, + + {/* AArch64_LDSMAXH, AArch64_INS_LDSMAXH: ldsmaxh */ + 0, + {0}}, + + {/* AArch64_LDSMAXLB, AArch64_INS_LDSMAXLB: ldsmaxlb */ + 0, + {0}}, + + {/* AArch64_LDSMAXLH, AArch64_INS_LDSMAXLH: ldsmaxlh */ + 0, + {0}}, + + {/* AArch64_LDSMAXLW, AArch64_INS_LDSMAXL: ldsmaxl */ + 0, + {0}}, + + {/* AArch64_LDSMAXLX, AArch64_INS_LDSMAXL: ldsmaxl */ + 0, + {0}}, + + {/* AArch64_LDSMAXW, AArch64_INS_LDSMAX: ldsmax */ + 0, + {0}}, + + {/* AArch64_LDSMAXX, AArch64_INS_LDSMAX: ldsmax */ + 0, + {0}}, + + {/* AArch64_LDSMINAB, AArch64_INS_LDSMINAB: ldsminab */ + 0, + {0}}, + + {/* AArch64_LDSMINAH, AArch64_INS_LDSMINAH: ldsminah */ + 0, + {0}}, + + {/* AArch64_LDSMINALB, AArch64_INS_LDSMINALB: ldsminalb */ + 0, + {0}}, + + {/* AArch64_LDSMINALH, AArch64_INS_LDSMINALH: ldsminalh */ + 0, + {0}}, + + {/* AArch64_LDSMINALW, AArch64_INS_LDSMINAL: ldsminal */ + 0, + {0}}, + + {/* AArch64_LDSMINALX, AArch64_INS_LDSMINAL: ldsminal */ + 0, + {0}}, + + {/* AArch64_LDSMINAW, AArch64_INS_LDSMINA: ldsmina */ + 0, + {0}}, + + {/* AArch64_LDSMINAX, AArch64_INS_LDSMINA: ldsmina */ + 0, + {0}}, + + {/* AArch64_LDSMINB, AArch64_INS_LDSMINB: ldsminb */ + 0, + {0}}, + + {/* AArch64_LDSMINH, AArch64_INS_LDSMINH: ldsminh */ + 0, + {0}}, + + {/* AArch64_LDSMINLB, AArch64_INS_LDSMINLB: ldsminlb */ + 0, + {0}}, + + {/* AArch64_LDSMINLH, AArch64_INS_LDSMINLH: ldsminlh */ + 0, + {0}}, + + {/* AArch64_LDSMINLW, AArch64_INS_LDSMINL: ldsminl */ + 0, + {0}}, + + {/* AArch64_LDSMINLX, AArch64_INS_LDSMINL: ldsminl */ + 0, + {0}}, + + {/* AArch64_LDSMINW, AArch64_INS_LDSMIN: ldsmin */ + 0, + {0}}, + + {/* AArch64_LDSMINX, AArch64_INS_LDSMIN: ldsmin */ + 0, + {0}}, + + {/* AArch64_LDTRBi, AArch64_INS_LDTRB: ldtrb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDTRHi, AArch64_INS_LDTRH: ldtrh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDTRSBWi, AArch64_INS_LDTRSB: ldtrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDTRSBXi, AArch64_INS_LDTRSB: ldtrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDTRSHWi, AArch64_INS_LDTRSH: ldtrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDTRSHXi, AArch64_INS_LDTRSH: ldtrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDTRSWi, AArch64_INS_LDTRSW: ldtrsw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDTRWi, AArch64_INS_LDTR: ldtr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDTRXi, AArch64_INS_LDTR: ldtr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDUMAXAB, AArch64_INS_LDUMAXAB: ldumaxab */ + 0, + {0}}, + + {/* AArch64_LDUMAXAH, AArch64_INS_LDUMAXAH: ldumaxah */ + 0, + {0}}, + + {/* AArch64_LDUMAXALB, AArch64_INS_LDUMAXALB: ldumaxalb */ + 0, + {0}}, + + {/* AArch64_LDUMAXALH, AArch64_INS_LDUMAXALH: ldumaxalh */ + 0, + {0}}, + + {/* AArch64_LDUMAXALW, AArch64_INS_LDUMAXAL: ldumaxal */ + 0, + {0}}, + + {/* AArch64_LDUMAXALX, AArch64_INS_LDUMAXAL: ldumaxal */ + 0, + {0}}, + + {/* AArch64_LDUMAXAW, AArch64_INS_LDUMAXA: ldumaxa */ + 0, + {0}}, + + {/* AArch64_LDUMAXAX, AArch64_INS_LDUMAXA: ldumaxa */ + 0, + {0}}, + + {/* AArch64_LDUMAXB, AArch64_INS_LDUMAXB: ldumaxb */ + 0, + {0}}, + + {/* AArch64_LDUMAXH, AArch64_INS_LDUMAXH: ldumaxh */ + 0, + {0}}, + + {/* AArch64_LDUMAXLB, AArch64_INS_LDUMAXLB: ldumaxlb */ + 0, + {0}}, + + {/* AArch64_LDUMAXLH, AArch64_INS_LDUMAXLH: ldumaxlh */ + 0, + {0}}, + + {/* AArch64_LDUMAXLW, AArch64_INS_LDUMAXL: ldumaxl */ + 0, + {0}}, + + {/* AArch64_LDUMAXLX, AArch64_INS_LDUMAXL: ldumaxl */ + 0, + {0}}, + + {/* AArch64_LDUMAXW, AArch64_INS_LDUMAX: ldumax */ + 0, + {0}}, + + {/* AArch64_LDUMAXX, AArch64_INS_LDUMAX: ldumax */ + 0, + {0}}, + + {/* AArch64_LDUMINAB, AArch64_INS_LDUMINAB: lduminab */ + 0, + {0}}, + + {/* AArch64_LDUMINAH, AArch64_INS_LDUMINAH: lduminah */ + 0, + {0}}, + + {/* AArch64_LDUMINALB, AArch64_INS_LDUMINALB: lduminalb */ + 0, + {0}}, + + {/* AArch64_LDUMINALH, AArch64_INS_LDUMINALH: lduminalh */ + 0, + {0}}, + + {/* AArch64_LDUMINALW, AArch64_INS_LDUMINAL: lduminal */ + 0, + {0}}, + + {/* AArch64_LDUMINALX, AArch64_INS_LDUMINAL: lduminal */ + 0, + {0}}, + + {/* AArch64_LDUMINAW, AArch64_INS_LDUMINA: ldumina */ + 0, + {0}}, + + {/* AArch64_LDUMINAX, AArch64_INS_LDUMINA: ldumina */ + 0, + {0}}, + + {/* AArch64_LDUMINB, AArch64_INS_LDUMINB: lduminb */ + 0, + {0}}, + + {/* AArch64_LDUMINH, AArch64_INS_LDUMINH: lduminh */ + 0, + {0}}, + + {/* AArch64_LDUMINLB, AArch64_INS_LDUMINLB: lduminlb */ + 0, + {0}}, + + {/* AArch64_LDUMINLH, AArch64_INS_LDUMINLH: lduminlh */ + 0, + {0}}, + + {/* AArch64_LDUMINLW, AArch64_INS_LDUMINL: lduminl */ + 0, + {0}}, + + {/* AArch64_LDUMINLX, AArch64_INS_LDUMINL: lduminl */ + 0, + {0}}, + + {/* AArch64_LDUMINW, AArch64_INS_LDUMIN: ldumin */ + 0, + {0}}, + + {/* AArch64_LDUMINX, AArch64_INS_LDUMIN: ldumin */ + 0, + {0}}, + + {/* AArch64_LDURBBi, AArch64_INS_LDRB: ldrb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURBi, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURDi, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURHHi, AArch64_INS_LDRH: ldrh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURHi, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURQi, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURSBWi, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURSBXi, AArch64_INS_LDRSB: ldrsb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURSHWi, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURSHXi, AArch64_INS_LDRSH: ldrsh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURSWi, AArch64_INS_LDRSW: ldrsw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURSi, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURWi, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDURXi, AArch64_INS_LDR: ldr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LDXPW, AArch64_INS_LDXP: ldxp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDXPX, AArch64_INS_LDXP: ldxp */ + 0, + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDXRB, AArch64_INS_LDXRB: ldxrb */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDXRH, AArch64_INS_LDXRH: ldxrh */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDXRW, AArch64_INS_LDXR: ldxr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LDXRX, AArch64_INS_LDXR: ldxr */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_LSLR_ZPmZ_B, AArch64_INS_LSLR: lslr */ + 0, + {0}}, + + {/* AArch64_LSLR_ZPmZ_D, AArch64_INS_LSLR: lslr */ + 0, + {0}}, + + {/* AArch64_LSLR_ZPmZ_H, AArch64_INS_LSLR: lslr */ + 0, + {0}}, + + {/* AArch64_LSLR_ZPmZ_S, AArch64_INS_LSLR: lslr */ + 0, + {0}}, + + {/* AArch64_LSLVWr, AArch64_INS_LSL: lsl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LSLVXr, AArch64_INS_LSL: lsl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LSL_WIDE_ZPmZ_B, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_WIDE_ZPmZ_H, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_WIDE_ZPmZ_S, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_WIDE_ZZZ_B, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_WIDE_ZZZ_H, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_WIDE_ZZZ_S, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZPmI_B, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZPmI_D, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZPmI_H, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZPmI_S, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZPmZ_B, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZPmZ_D, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZPmZ_H, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZPmZ_S, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZZI_B, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZZI_D, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZZI_H, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSL_ZZI_S, AArch64_INS_LSL: lsl */ + 0, + {0}}, + + {/* AArch64_LSRR_ZPmZ_B, AArch64_INS_LSRR: lsrr */ + 0, + {0}}, + + {/* AArch64_LSRR_ZPmZ_D, AArch64_INS_LSRR: lsrr */ + 0, + {0}}, + + {/* AArch64_LSRR_ZPmZ_H, AArch64_INS_LSRR: lsrr */ + 0, + {0}}, + + {/* AArch64_LSRR_ZPmZ_S, AArch64_INS_LSRR: lsrr */ + 0, + {0}}, + + {/* AArch64_LSRVWr, AArch64_INS_LSR: lsr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LSRVXr, AArch64_INS_LSR: lsr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_LSR_WIDE_ZPmZ_B, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_WIDE_ZPmZ_H, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_WIDE_ZPmZ_S, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_WIDE_ZZZ_B, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_WIDE_ZZZ_H, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_WIDE_ZZZ_S, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZPmI_B, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZPmI_D, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZPmI_H, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZPmI_S, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZPmZ_B, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZPmZ_D, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZPmZ_H, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZPmZ_S, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZZI_B, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZZI_D, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZZI_H, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_LSR_ZZI_S, AArch64_INS_LSR: lsr */ + 0, + {0}}, + + {/* AArch64_MADDWrrr, AArch64_INS_MADD: madd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MADDXrrr, AArch64_INS_MADD: madd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MAD_ZPmZZ_B, AArch64_INS_MAD: mad */ + 0, + {0}}, + + {/* AArch64_MAD_ZPmZZ_D, AArch64_INS_MAD: mad */ + 0, + {0}}, + + {/* AArch64_MAD_ZPmZZ_H, AArch64_INS_MAD: mad */ + 0, + {0}}, + + {/* AArch64_MAD_ZPmZZ_S, AArch64_INS_MAD: mad */ + 0, + {0}}, + + {/* AArch64_MLA_ZPmZZ_B, AArch64_INS_MLA: mla */ + 0, + {0}}, + + {/* AArch64_MLA_ZPmZZ_D, AArch64_INS_MLA: mla */ + 0, + {0}}, + + {/* AArch64_MLA_ZPmZZ_H, AArch64_INS_MLA: mla */ + 0, + {0}}, + + {/* AArch64_MLA_ZPmZZ_S, AArch64_INS_MLA: mla */ + 0, + {0}}, + + {/* AArch64_MLAv16i8, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLAv2i32, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLAv2i32_indexed, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MLAv4i16, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLAv4i16_indexed, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MLAv4i32, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLAv4i32_indexed, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MLAv8i16, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLAv8i16_indexed, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MLAv8i8, AArch64_INS_MLA: mla */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLS_ZPmZZ_B, AArch64_INS_MLS: mls */ + 0, + {0}}, + + {/* AArch64_MLS_ZPmZZ_D, AArch64_INS_MLS: mls */ + 0, + {0}}, + + {/* AArch64_MLS_ZPmZZ_H, AArch64_INS_MLS: mls */ + 0, + {0}}, + + {/* AArch64_MLS_ZPmZZ_S, AArch64_INS_MLS: mls */ + 0, + {0}}, + + {/* AArch64_MLSv16i8, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLSv2i32, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLSv2i32_indexed, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MLSv4i16, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLSv4i16_indexed, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MLSv4i32, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLSv4i32_indexed, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MLSv8i16, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MLSv8i16_indexed, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MLSv8i8, AArch64_INS_MLS: mls */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVID, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVIv16b_ns, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVIv2d_ns, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVIv2i32, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVIv2s_msl, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVIv4i16, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVIv4i32, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVIv4s_msl, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVIv8b_ns, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVIv8i16, AArch64_INS_MOVI: movi */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVKWi, AArch64_INS_MOVK: movk */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVKXi, AArch64_INS_MOVK: movk */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVNWi, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVNXi, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVPRFX_ZPmZ_B, AArch64_INS_MOVPRFX: movprfx */ + 0, + {0}}, + + {/* AArch64_MOVPRFX_ZPmZ_D, AArch64_INS_MOVPRFX: movprfx */ + 0, + {0}}, + + {/* AArch64_MOVPRFX_ZPmZ_H, AArch64_INS_MOVPRFX: movprfx */ + 0, + {0}}, + + {/* AArch64_MOVPRFX_ZPmZ_S, AArch64_INS_MOVPRFX: movprfx */ + 0, + {0}}, + + {/* AArch64_MOVPRFX_ZPzZ_B, AArch64_INS_MOVPRFX: movprfx */ + 0, + {0}}, + + {/* AArch64_MOVPRFX_ZPzZ_D, AArch64_INS_MOVPRFX: movprfx */ + 0, + {0}}, + + {/* AArch64_MOVPRFX_ZPzZ_H, AArch64_INS_MOVPRFX: movprfx */ + 0, + {0}}, + + {/* AArch64_MOVPRFX_ZPzZ_S, AArch64_INS_MOVPRFX: movprfx */ + 0, + {0}}, + + {/* AArch64_MOVPRFX_ZZ, AArch64_INS_MOVPRFX: movprfx */ + 0, + {0}}, + + {/* AArch64_MOVZWi, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MOVZXi, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MRS, AArch64_INS_MRS: mrs */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_MSB_ZPmZZ_B, AArch64_INS_MSB: msb */ + 0, + {0}}, + + {/* AArch64_MSB_ZPmZZ_D, AArch64_INS_MSB: msb */ + 0, + {0}}, + + {/* AArch64_MSB_ZPmZZ_H, AArch64_INS_MSB: msb */ + 0, + {0}}, + + {/* AArch64_MSB_ZPmZZ_S, AArch64_INS_MSB: msb */ + 0, + {0}}, + + {/* AArch64_MSR, AArch64_INS_MSR: msr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_MSRpstateImm1, AArch64_INS_MSR: msr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MSRpstateImm4, AArch64_INS_MSR: msr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MSUBWrrr, AArch64_INS_MNEG: mneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MSUBXrrr, AArch64_INS_MNEG: mneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MUL_ZI_B, AArch64_INS_MUL: mul */ + 0, + {0}}, + + {/* AArch64_MUL_ZI_D, AArch64_INS_MUL: mul */ + 0, + {0}}, + + {/* AArch64_MUL_ZI_H, AArch64_INS_MUL: mul */ + 0, + {0}}, + + {/* AArch64_MUL_ZI_S, AArch64_INS_MUL: mul */ + 0, + {0}}, + + {/* AArch64_MUL_ZPmZ_B, AArch64_INS_MUL: mul */ + 0, + {0}}, + + {/* AArch64_MUL_ZPmZ_D, AArch64_INS_MUL: mul */ + 0, + {0}}, + + {/* AArch64_MUL_ZPmZ_H, AArch64_INS_MUL: mul */ + 0, + {0}}, + + {/* AArch64_MUL_ZPmZ_S, AArch64_INS_MUL: mul */ + 0, + {0}}, + + {/* AArch64_MULv16i8, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MULv2i32, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MULv2i32_indexed, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MULv4i16, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MULv4i16_indexed, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_MULv4i32, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MULv4i32_indexed, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MULv8i16, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MULv8i16_indexed, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MULv8i8, AArch64_INS_MUL: mul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MVNIv2i32, AArch64_INS_MVNI: mvni */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MVNIv2s_msl, AArch64_INS_MVNI: mvni */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MVNIv4i16, AArch64_INS_MVNI: mvni */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MVNIv4i32, AArch64_INS_MVNI: mvni */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MVNIv4s_msl, AArch64_INS_MVNI: mvni */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_MVNIv8i16, AArch64_INS_MVNI: mvni */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_NANDS_PPzPP, AArch64_INS_NANDS: nands */ + 0, + {0}}, + + {/* AArch64_NAND_PPzPP, AArch64_INS_NAND: nand */ + 0, + {0}}, + + {/* AArch64_NEG_ZPmZ_B, AArch64_INS_NEG: neg */ + 0, + {0}}, + + {/* AArch64_NEG_ZPmZ_D, AArch64_INS_NEG: neg */ + 0, + {0}}, + + {/* AArch64_NEG_ZPmZ_H, AArch64_INS_NEG: neg */ + 0, + {0}}, + + {/* AArch64_NEG_ZPmZ_S, AArch64_INS_NEG: neg */ + 0, + {0}}, + + {/* AArch64_NEGv16i8, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_NEGv1i64, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_NEGv2i32, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_NEGv2i64, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_NEGv4i16, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_NEGv4i32, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_NEGv8i16, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_NEGv8i8, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_NORS_PPzPP, AArch64_INS_NORS: nors */ + 0, + {0}}, + + {/* AArch64_NOR_PPzPP, AArch64_INS_NOR: nor */ + 0, + {0}}, + + {/* AArch64_NOT_ZPmZ_B, AArch64_INS_NOT: not */ + 0, + {0}}, + + {/* AArch64_NOT_ZPmZ_D, AArch64_INS_NOT: not */ + 0, + {0}}, + + {/* AArch64_NOT_ZPmZ_H, AArch64_INS_NOT: not */ + 0, + {0}}, + + {/* AArch64_NOT_ZPmZ_S, AArch64_INS_NOT: not */ + 0, + {0}}, + + {/* AArch64_NOTv16i8, AArch64_INS_MVN: mvn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_NOTv8i8, AArch64_INS_MVN: mvn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ORNS_PPzPP, AArch64_INS_ORNS: orns */ + 0, + {0}}, + + {/* AArch64_ORNWrs, AArch64_INS_MVN: mvn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORNXrs, AArch64_INS_MVN: mvn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORN_PPzPP, AArch64_INS_ORN: orn */ + 0, + {0}}, + + {/* AArch64_ORNv16i8, AArch64_INS_ORN: orn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORNv8i8, AArch64_INS_ORN: orn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORRS_PPzPP, AArch64_INS_MOVS: movs */ + 0, + {0}}, + + {/* AArch64_ORRWri, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORRWrs, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORRXri, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORRXrs, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORR_PPzPP, AArch64_INS_MOV: mov */ + 0, + {0}}, + + {/* AArch64_ORR_ZI, AArch64_INS_ORN: orn */ + 0, + {0}}, + + {/* AArch64_ORR_ZPmZ_B, AArch64_INS_ORR: orr */ + 0, + {0}}, + + {/* AArch64_ORR_ZPmZ_D, AArch64_INS_ORR: orr */ + 0, + {0}}, + + {/* AArch64_ORR_ZPmZ_H, AArch64_INS_ORR: orr */ + 0, + {0}}, + + {/* AArch64_ORR_ZPmZ_S, AArch64_INS_ORR: orr */ + 0, + {0}}, + + {/* AArch64_ORR_ZZZ, AArch64_INS_MOV: mov */ + 0, + {0}}, + + {/* AArch64_ORRv16i8, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORRv2i32, AArch64_INS_ORR: orr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORRv4i16, AArch64_INS_ORR: orr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORRv4i32, AArch64_INS_ORR: orr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORRv8i16, AArch64_INS_ORR: orr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORRv8i8, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ORV_VPZ_B, AArch64_INS_ORV: orv */ + 0, + {0}}, + + {/* AArch64_ORV_VPZ_D, AArch64_INS_ORV: orv */ + 0, + {0}}, + + {/* AArch64_ORV_VPZ_H, AArch64_INS_ORV: orv */ + 0, + {0}}, + + {/* AArch64_ORV_VPZ_S, AArch64_INS_ORV: orv */ + 0, + {0}}, + + {/* AArch64_PACDA, AArch64_INS_PACDA: pacda */ + 0, + {0}}, + + {/* AArch64_PACDB, AArch64_INS_PACDB: pacdb */ + 0, + {0}}, + + {/* AArch64_PACDZA, AArch64_INS_PACDZA: pacdza */ + 0, + {0}}, + + {/* AArch64_PACDZB, AArch64_INS_PACDZB: pacdzb */ + 0, + {0}}, + + {/* AArch64_PACGA, AArch64_INS_PACGA: pacga */ + 0, + {0}}, + + {/* AArch64_PACIA, AArch64_INS_PACIA: pacia */ + 0, + {0}}, + + {/* AArch64_PACIA1716, AArch64_INS_PACIA1716: pacia1716 */ + 0, + {0}}, + + {/* AArch64_PACIASP, AArch64_INS_PACIASP: paciasp */ + 0, + {0}}, + + {/* AArch64_PACIAZ, AArch64_INS_PACIAZ: paciaz */ + 0, + {0}}, + + {/* AArch64_PACIB, AArch64_INS_PACIB: pacib */ + 0, + {0}}, + + {/* AArch64_PACIB1716, AArch64_INS_PACIB1716: pacib1716 */ + 0, + {0}}, + + {/* AArch64_PACIBSP, AArch64_INS_PACIBSP: pacibsp */ + 0, + {0}}, + + {/* AArch64_PACIBZ, AArch64_INS_PACIBZ: pacibz */ + 0, + {0}}, + + {/* AArch64_PACIZA, AArch64_INS_PACIZA: paciza */ + 0, + {0}}, + + {/* AArch64_PACIZB, AArch64_INS_PACIZB: pacizb */ + 0, + {0}}, + + {/* AArch64_PFALSE, AArch64_INS_PFALSE: pfalse */ + 0, + {0}}, + + {/* AArch64_PMULLv16i8, AArch64_INS_PMULL2: pmull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_PMULLv1i64, AArch64_INS_PMULL: pmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_PMULLv2i64, AArch64_INS_PMULL2: pmull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_PMULLv8i8, AArch64_INS_PMULL: pmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_PMULv16i8, AArch64_INS_PMUL: pmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_PMULv8i8, AArch64_INS_PMUL: pmul */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_PNEXT_B, AArch64_INS_PNEXT: pnext */ + 0, + {0}}, + + {/* AArch64_PNEXT_D, AArch64_INS_PNEXT: pnext */ + 0, + {0}}, + + {/* AArch64_PNEXT_H, AArch64_INS_PNEXT: pnext */ + 0, + {0}}, + + {/* AArch64_PNEXT_S, AArch64_INS_PNEXT: pnext */ + 0, + {0}}, + + {/* AArch64_PRFB_D_PZI, AArch64_INS_PRFB: prfb */ + 0, + {0}}, + + {/* AArch64_PRFB_D_SCALED, AArch64_INS_PRFB: prfb */ + 0, + {0}}, + + {/* AArch64_PRFB_D_SXTW_SCALED, AArch64_INS_PRFB: prfb */ + 0, + {0}}, + + {/* AArch64_PRFB_D_UXTW_SCALED, AArch64_INS_PRFB: prfb */ + 0, + {0}}, + + {/* AArch64_PRFB_PRI, AArch64_INS_PRFB: prfb */ + 0, + {0}}, + + {/* AArch64_PRFB_PRR, AArch64_INS_PRFB: prfb */ + 0, + {0}}, + + {/* AArch64_PRFB_S_PZI, AArch64_INS_PRFB: prfb */ + 0, + {0}}, + + {/* AArch64_PRFB_S_SXTW_SCALED, AArch64_INS_PRFB: prfb */ + 0, + {0}}, + + {/* AArch64_PRFB_S_UXTW_SCALED, AArch64_INS_PRFB: prfb */ + 0, + {0}}, + + {/* AArch64_PRFD_D_PZI, AArch64_INS_PRFD: prfd */ + 0, + {0}}, + + {/* AArch64_PRFD_D_SCALED, AArch64_INS_PRFD: prfd */ + 0, + {0}}, + + {/* AArch64_PRFD_D_SXTW_SCALED, AArch64_INS_PRFD: prfd */ + 0, + {0}}, + + {/* AArch64_PRFD_D_UXTW_SCALED, AArch64_INS_PRFD: prfd */ + 0, + {0}}, + + {/* AArch64_PRFD_PRI, AArch64_INS_PRFD: prfd */ + 0, + {0}}, + + {/* AArch64_PRFD_PRR, AArch64_INS_PRFD: prfd */ + 0, + {0}}, + + {/* AArch64_PRFD_S_PZI, AArch64_INS_PRFD: prfd */ + 0, + {0}}, + + {/* AArch64_PRFD_S_SXTW_SCALED, AArch64_INS_PRFD: prfd */ + 0, + {0}}, + + {/* AArch64_PRFD_S_UXTW_SCALED, AArch64_INS_PRFD: prfd */ + 0, + {0}}, + + {/* AArch64_PRFH_D_PZI, AArch64_INS_PRFH: prfh */ + 0, + {0}}, + + {/* AArch64_PRFH_D_SCALED, AArch64_INS_PRFH: prfh */ + 0, + {0}}, + + {/* AArch64_PRFH_D_SXTW_SCALED, AArch64_INS_PRFH: prfh */ + 0, + {0}}, + + {/* AArch64_PRFH_D_UXTW_SCALED, AArch64_INS_PRFH: prfh */ + 0, + {0}}, + + {/* AArch64_PRFH_PRI, AArch64_INS_PRFH: prfh */ + 0, + {0}}, + + {/* AArch64_PRFH_PRR, AArch64_INS_PRFH: prfh */ + 0, + {0}}, + + {/* AArch64_PRFH_S_PZI, AArch64_INS_PRFH: prfh */ + 0, + {0}}, + + {/* AArch64_PRFH_S_SXTW_SCALED, AArch64_INS_PRFH: prfh */ + 0, + {0}}, + + {/* AArch64_PRFH_S_UXTW_SCALED, AArch64_INS_PRFH: prfh */ + 0, + {0}}, + + {/* AArch64_PRFMl, AArch64_INS_PRFM: prfm */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_PRFMroW, AArch64_INS_PRFM: prfm */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_PRFMroX, AArch64_INS_PRFM: prfm */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_PRFMui, AArch64_INS_PRFM: prfm */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_PRFS_PRR, AArch64_INS_PRFW: prfw */ + 0, + {0}}, + + {/* AArch64_PRFUMi, AArch64_INS_PRFUM: prfum */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_PRFW_D_PZI, AArch64_INS_PRFW: prfw */ + 0, + {0}}, + + {/* AArch64_PRFW_D_SCALED, AArch64_INS_PRFW: prfw */ + 0, + {0}}, + + {/* AArch64_PRFW_D_SXTW_SCALED, AArch64_INS_PRFW: prfw */ + 0, + {0}}, + + {/* AArch64_PRFW_D_UXTW_SCALED, AArch64_INS_PRFW: prfw */ + 0, + {0}}, + + {/* AArch64_PRFW_PRI, AArch64_INS_PRFW: prfw */ + 0, + {0}}, + + {/* AArch64_PRFW_S_PZI, AArch64_INS_PRFW: prfw */ + 0, + {0}}, + + {/* AArch64_PRFW_S_SXTW_SCALED, AArch64_INS_PRFW: prfw */ + 0, + {0}}, + + {/* AArch64_PRFW_S_UXTW_SCALED, AArch64_INS_PRFW: prfw */ + 0, + {0}}, + + {/* AArch64_PTEST_PP, AArch64_INS_PTEST: ptest */ + 0, + {0}}, + + {/* AArch64_PTRUES_B, AArch64_INS_PTRUES: ptrues */ + 0, + {0}}, + + {/* AArch64_PTRUES_D, AArch64_INS_PTRUES: ptrues */ + 0, + {0}}, + + {/* AArch64_PTRUES_H, AArch64_INS_PTRUES: ptrues */ + 0, + {0}}, + + {/* AArch64_PTRUES_S, AArch64_INS_PTRUES: ptrues */ + 0, + {0}}, + + {/* AArch64_PTRUE_B, AArch64_INS_PTRUE: ptrue */ + 0, + {0}}, + + {/* AArch64_PTRUE_D, AArch64_INS_PTRUE: ptrue */ + 0, + {0}}, + + {/* AArch64_PTRUE_H, AArch64_INS_PTRUE: ptrue */ + 0, + {0}}, + + {/* AArch64_PTRUE_S, AArch64_INS_PTRUE: ptrue */ + 0, + {0}}, + + {/* AArch64_PUNPKHI_PP, AArch64_INS_PUNPKHI: punpkhi */ + 0, + {0}}, + + {/* AArch64_PUNPKLO_PP, AArch64_INS_PUNPKLO: punpklo */ + 0, + {0}}, + + {/* AArch64_RADDHNv2i64_v2i32, AArch64_INS_RADDHN: raddhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RADDHNv2i64_v4i32, AArch64_INS_RADDHN2: raddhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RADDHNv4i32_v4i16, AArch64_INS_RADDHN: raddhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RADDHNv4i32_v8i16, AArch64_INS_RADDHN2: raddhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RADDHNv8i16_v16i8, AArch64_INS_RADDHN2: raddhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RADDHNv8i16_v8i8, AArch64_INS_RADDHN: raddhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RAX1, AArch64_INS_RAX1: rax1 */ + 0, + {0}}, + + {/* AArch64_RBITWr, AArch64_INS_RBIT: rbit */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_RBITXr, AArch64_INS_RBIT: rbit */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_RBIT_ZPmZ_B, AArch64_INS_RBIT: rbit */ + 0, + {0}}, + + {/* AArch64_RBIT_ZPmZ_D, AArch64_INS_RBIT: rbit */ + 0, + {0}}, + + {/* AArch64_RBIT_ZPmZ_H, AArch64_INS_RBIT: rbit */ + 0, + {0}}, + + {/* AArch64_RBIT_ZPmZ_S, AArch64_INS_RBIT: rbit */ + 0, + {0}}, + + {/* AArch64_RBITv16i8, AArch64_INS_RBIT: rbit */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_RBITv8i8, AArch64_INS_RBIT: rbit */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_RDFFRS_PPz, AArch64_INS_RDFFRS: rdffrs */ + 0, + {0}}, + + {/* AArch64_RDFFR_P, AArch64_INS_RDFFR: rdffr */ + 0, + {0}}, + + {/* AArch64_RDFFR_PPz, AArch64_INS_RDFFR: rdffr */ + 0, + {0}}, + + {/* AArch64_RDVLI_XI, AArch64_INS_RDVL: rdvl */ + 0, + {0}}, + + {/* AArch64_RET, AArch64_INS_RET: ret */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_RETAA, AArch64_INS_RETAA: retaa */ + 0, + {0}}, + + {/* AArch64_RETAB, AArch64_INS_RETAB: retab */ + 0, + {0}}, + + {/* AArch64_REV16Wr, AArch64_INS_REV16: rev16 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV16Xr, AArch64_INS_REV16: rev16 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV16v16i8, AArch64_INS_REV16: rev16 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV16v8i8, AArch64_INS_REV16: rev16 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV32Xr, AArch64_INS_REV32: rev32 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV32v16i8, AArch64_INS_REV32: rev32 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV32v4i16, AArch64_INS_REV32: rev32 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV32v8i16, AArch64_INS_REV32: rev32 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV32v8i8, AArch64_INS_REV32: rev32 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV64v16i8, AArch64_INS_REV64: rev64 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV64v2i32, AArch64_INS_REV64: rev64 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV64v4i16, AArch64_INS_REV64: rev64 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV64v4i32, AArch64_INS_REV64: rev64 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV64v8i16, AArch64_INS_REV64: rev64 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV64v8i8, AArch64_INS_REV64: rev64 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REVB_ZPmZ_D, AArch64_INS_REVB: revb */ + 0, + {0}}, + + {/* AArch64_REVB_ZPmZ_H, AArch64_INS_REVB: revb */ + 0, + {0}}, + + {/* AArch64_REVB_ZPmZ_S, AArch64_INS_REVB: revb */ + 0, + {0}}, + + {/* AArch64_REVH_ZPmZ_D, AArch64_INS_REVH: revh */ + 0, + {0}}, + + {/* AArch64_REVH_ZPmZ_S, AArch64_INS_REVH: revh */ + 0, + {0}}, + + {/* AArch64_REVW_ZPmZ_D, AArch64_INS_REVW: revw */ + 0, + {0}}, + + {/* AArch64_REVWr, AArch64_INS_REV: rev */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REVXr, AArch64_INS_REV: rev */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_REV_PP_B, AArch64_INS_REV: rev */ + 0, + {0}}, + + {/* AArch64_REV_PP_D, AArch64_INS_REV: rev */ + 0, + {0}}, + + {/* AArch64_REV_PP_H, AArch64_INS_REV: rev */ + 0, + {0}}, + + {/* AArch64_REV_PP_S, AArch64_INS_REV: rev */ + 0, + {0}}, + + {/* AArch64_REV_ZZ_B, AArch64_INS_REV: rev */ + 0, + {0}}, + + {/* AArch64_REV_ZZ_D, AArch64_INS_REV: rev */ + 0, + {0}}, + + {/* AArch64_REV_ZZ_H, AArch64_INS_REV: rev */ + 0, + {0}}, + + {/* AArch64_REV_ZZ_S, AArch64_INS_REV: rev */ + 0, + {0}}, + + {/* AArch64_RMIF, AArch64_INS_RMIF: rmif */ + 0, + {0}}, + + {/* AArch64_RORVWr, AArch64_INS_ROR: ror */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RORVXr, AArch64_INS_ROR: ror */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSHRNv16i8_shift, AArch64_INS_RSHRN2: rshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSHRNv2i32_shift, AArch64_INS_RSHRN: rshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSHRNv4i16_shift, AArch64_INS_RSHRN: rshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSHRNv4i32_shift, AArch64_INS_RSHRN2: rshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSHRNv8i16_shift, AArch64_INS_RSHRN2: rshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSHRNv8i8_shift, AArch64_INS_RSHRN: rshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSUBHNv2i64_v2i32, AArch64_INS_RSUBHN: rsubhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSUBHNv2i64_v4i32, AArch64_INS_RSUBHN2: rsubhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSUBHNv4i32_v4i16, AArch64_INS_RSUBHN: rsubhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSUBHNv4i32_v8i16, AArch64_INS_RSUBHN2: rsubhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSUBHNv8i16_v16i8, AArch64_INS_RSUBHN2: rsubhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_RSUBHNv8i16_v8i8, AArch64_INS_RSUBHN: rsubhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABALv16i8_v8i16, AArch64_INS_SABAL2: sabal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABALv2i32_v2i64, AArch64_INS_SABAL: sabal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABALv4i16_v4i32, AArch64_INS_SABAL: sabal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABALv4i32_v2i64, AArch64_INS_SABAL2: sabal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABALv8i16_v4i32, AArch64_INS_SABAL2: sabal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABALv8i8_v8i16, AArch64_INS_SABAL: sabal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABAv16i8, AArch64_INS_SABA: saba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABAv2i32, AArch64_INS_SABA: saba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABAv4i16, AArch64_INS_SABA: saba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABAv4i32, AArch64_INS_SABA: saba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABAv8i16, AArch64_INS_SABA: saba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABAv8i8, AArch64_INS_SABA: saba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDLv16i8_v8i16, AArch64_INS_SABDL2: sabdl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDLv2i32_v2i64, AArch64_INS_SABDL: sabdl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDLv4i16_v4i32, AArch64_INS_SABDL: sabdl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDLv4i32_v2i64, AArch64_INS_SABDL2: sabdl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDLv8i16_v4i32, AArch64_INS_SABDL2: sabdl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDLv8i8_v8i16, AArch64_INS_SABDL: sabdl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABD_ZPmZ_B, AArch64_INS_SABD: sabd */ + 0, + {0}}, + + {/* AArch64_SABD_ZPmZ_D, AArch64_INS_SABD: sabd */ + 0, + {0}}, + + {/* AArch64_SABD_ZPmZ_H, AArch64_INS_SABD: sabd */ + 0, + {0}}, + + {/* AArch64_SABD_ZPmZ_S, AArch64_INS_SABD: sabd */ + 0, + {0}}, + + {/* AArch64_SABDv16i8, AArch64_INS_SABD: sabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDv2i32, AArch64_INS_SABD: sabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDv4i16, AArch64_INS_SABD: sabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDv4i32, AArch64_INS_SABD: sabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDv8i16, AArch64_INS_SABD: sabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SABDv8i8, AArch64_INS_SABD: sabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADALPv16i8_v8i16, AArch64_INS_SADALP: sadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADALPv2i32_v1i64, AArch64_INS_SADALP: sadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADALPv4i16_v2i32, AArch64_INS_SADALP: sadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADALPv4i32_v2i64, AArch64_INS_SADALP: sadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADALPv8i16_v4i32, AArch64_INS_SADALP: sadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADALPv8i8_v4i16, AArch64_INS_SADALP: sadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLPv16i8_v8i16, AArch64_INS_SADDLP: saddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLPv2i32_v1i64, AArch64_INS_SADDLP: saddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLPv4i16_v2i32, AArch64_INS_SADDLP: saddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLPv4i32_v2i64, AArch64_INS_SADDLP: saddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLPv8i16_v4i32, AArch64_INS_SADDLP: saddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLPv8i8_v4i16, AArch64_INS_SADDLP: saddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLVv16i8v, AArch64_INS_SADDLV: saddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SADDLVv4i16v, AArch64_INS_SADDLV: saddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SADDLVv4i32v, AArch64_INS_SADDLV: saddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SADDLVv8i16v, AArch64_INS_SADDLV: saddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SADDLVv8i8v, AArch64_INS_SADDLV: saddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SADDLv16i8_v8i16, AArch64_INS_SADDL2: saddl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLv2i32_v2i64, AArch64_INS_SADDL: saddl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLv4i16_v4i32, AArch64_INS_SADDL: saddl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLv4i32_v2i64, AArch64_INS_SADDL2: saddl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLv8i16_v4i32, AArch64_INS_SADDL2: saddl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDLv8i8_v8i16, AArch64_INS_SADDL: saddl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDV_VPZ_B, AArch64_INS_SADDV: saddv */ + 0, + {0}}, + + {/* AArch64_SADDV_VPZ_H, AArch64_INS_SADDV: saddv */ + 0, + {0}}, + + {/* AArch64_SADDV_VPZ_S, AArch64_INS_SADDV: saddv */ + 0, + {0}}, + + {/* AArch64_SADDWv16i8_v8i16, AArch64_INS_SADDW2: saddw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDWv2i32_v2i64, AArch64_INS_SADDW: saddw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDWv4i16_v4i32, AArch64_INS_SADDW: saddw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDWv4i32_v2i64, AArch64_INS_SADDW2: saddw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDWv8i16_v4i32, AArch64_INS_SADDW2: saddw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SADDWv8i8_v8i16, AArch64_INS_SADDW: saddw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SBCSWr, AArch64_INS_NGCS: ngcs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SBCSXr, AArch64_INS_NGCS: ngcs */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SBCWr, AArch64_INS_NGC: ngc */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SBCXr, AArch64_INS_NGC: ngc */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SBFMWri, AArch64_INS_ASR: asr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SBFMXri, AArch64_INS_ASR: asr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SCVTFSWDri, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFSWHri, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFSWSri, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFSXDri, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFSXHri, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFSXSri, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFUWDri, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFUWHri, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFUWSri, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFUXDri, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFUXHri, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFUXSri, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SCVTF_ZPmZ_DtoD, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTF_ZPmZ_DtoH, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTF_ZPmZ_DtoS, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTF_ZPmZ_HtoH, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTF_ZPmZ_StoD, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTF_ZPmZ_StoH, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTF_ZPmZ_StoS, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFd, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFh, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFs, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFv1i16, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFv1i32, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFv1i64, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFv2f32, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFv2f64, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFv2i32_shift, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFv2i64_shift, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFv4f16, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFv4f32, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFv4i16_shift, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFv4i32_shift, AArch64_INS_SCVTF: scvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SCVTFv8f16, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SCVTFv8i16_shift, AArch64_INS_SCVTF: scvtf */ + 0, + {0}}, + + {/* AArch64_SDIVR_ZPmZ_D, AArch64_INS_SDIVR: sdivr */ + 0, + {0}}, + + {/* AArch64_SDIVR_ZPmZ_S, AArch64_INS_SDIVR: sdivr */ + 0, + {0}}, + + {/* AArch64_SDIVWr, AArch64_INS_SDIV: sdiv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SDIVXr, AArch64_INS_SDIV: sdiv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SDIV_ZPmZ_D, AArch64_INS_SDIV: sdiv */ + 0, + {0}}, + + {/* AArch64_SDIV_ZPmZ_S, AArch64_INS_SDIV: sdiv */ + 0, + {0}}, + + {/* AArch64_SDOT_ZZZI_D, AArch64_INS_SDOT: sdot */ + 0, + {0}}, + + {/* AArch64_SDOT_ZZZI_S, AArch64_INS_SDOT: sdot */ + 0, + {0}}, + + {/* AArch64_SDOT_ZZZ_D, AArch64_INS_SDOT: sdot */ + 0, + {0}}, + + {/* AArch64_SDOT_ZZZ_S, AArch64_INS_SDOT: sdot */ + 0, + {0}}, + + {/* AArch64_SDOTlanev16i8, AArch64_INS_SDOT: sdot */ + 0, + {0}}, + + {/* AArch64_SDOTlanev8i8, AArch64_INS_SDOT: sdot */ + 0, + {0}}, + + {/* AArch64_SDOTv16i8, AArch64_INS_SDOT: sdot */ + 0, + {0}}, + + {/* AArch64_SDOTv8i8, AArch64_INS_SDOT: sdot */ + 0, + {0}}, + + {/* AArch64_SEL_PPPP, AArch64_INS_MOV: mov */ + 0, + {0}}, + + {/* AArch64_SEL_ZPZZ_B, AArch64_INS_MOV: mov */ + 0, + {0}}, + + {/* AArch64_SEL_ZPZZ_D, AArch64_INS_MOV: mov */ + 0, + {0}}, + + {/* AArch64_SEL_ZPZZ_H, AArch64_INS_MOV: mov */ + 0, + {0}}, + + {/* AArch64_SEL_ZPZZ_S, AArch64_INS_MOV: mov */ + 0, + {0}}, + + {/* AArch64_SETF16, AArch64_INS_SETF16: setf16 */ + 0, + {0}}, + + {/* AArch64_SETF8, AArch64_INS_SETF8: setf8 */ + 0, + {0}}, + + {/* AArch64_SETFFR, AArch64_INS_SETFFR: setffr */ + 0, + {0}}, + + {/* AArch64_SHA1Crrr, AArch64_INS_SHA1C: sha1c */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHA1Hrr, AArch64_INS_SHA1H: sha1h */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SHA1Mrrr, AArch64_INS_SHA1M: sha1m */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHA1Prrr, AArch64_INS_SHA1P: sha1p */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHA1SU0rrr, AArch64_INS_SHA1SU0: sha1su0 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHA1SU1rr, AArch64_INS_SHA1SU1: sha1su1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHA256H2rrr, AArch64_INS_SHA256H2: sha256h2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHA256Hrrr, AArch64_INS_SHA256H: sha256h */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHA256SU0rr, AArch64_INS_SHA256SU0: sha256su0 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHA256SU1rrr, AArch64_INS_SHA256SU1: sha256su1 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHA512H, AArch64_INS_SHA512H: sha512h */ + 0, + {0}}, + + {/* AArch64_SHA512H2, AArch64_INS_SHA512H2: sha512h2 */ + 0, + {0}}, + + {/* AArch64_SHA512SU0, AArch64_INS_SHA512SU0: sha512su0 */ + 0, + {0}}, + + {/* AArch64_SHA512SU1, AArch64_INS_SHA512SU1: sha512su1 */ + 0, + {0}}, + + {/* AArch64_SHADDv16i8, AArch64_INS_SHADD: shadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHADDv2i32, AArch64_INS_SHADD: shadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHADDv4i16, AArch64_INS_SHADD: shadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHADDv4i32, AArch64_INS_SHADD: shadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHADDv8i16, AArch64_INS_SHADD: shadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHADDv8i8, AArch64_INS_SHADD: shadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLLv16i8, AArch64_INS_SHLL2: shll2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLLv2i32, AArch64_INS_SHLL: shll */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLLv4i16, AArch64_INS_SHLL: shll */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLLv4i32, AArch64_INS_SHLL2: shll2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLLv8i16, AArch64_INS_SHLL2: shll2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLLv8i8, AArch64_INS_SHLL: shll */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLd, AArch64_INS_SHL: shl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLv16i8_shift, AArch64_INS_SHL: shl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLv2i32_shift, AArch64_INS_SHL: shl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLv2i64_shift, AArch64_INS_SHL: shl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLv4i16_shift, AArch64_INS_SHL: shl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLv4i32_shift, AArch64_INS_SHL: shl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLv8i16_shift, AArch64_INS_SHL: shl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHLv8i8_shift, AArch64_INS_SHL: shl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHRNv16i8_shift, AArch64_INS_SHRN2: shrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHRNv2i32_shift, AArch64_INS_SHRN: shrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHRNv4i16_shift, AArch64_INS_SHRN: shrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHRNv4i32_shift, AArch64_INS_SHRN2: shrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHRNv8i16_shift, AArch64_INS_SHRN2: shrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHRNv8i8_shift, AArch64_INS_SHRN: shrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHSUBv16i8, AArch64_INS_SHSUB: shsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHSUBv2i32, AArch64_INS_SHSUB: shsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHSUBv4i16, AArch64_INS_SHSUB: shsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHSUBv4i32, AArch64_INS_SHSUB: shsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHSUBv8i16, AArch64_INS_SHSUB: shsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SHSUBv8i8, AArch64_INS_SHSUB: shsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SLId, AArch64_INS_SLI: sli */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SLIv16i8_shift, AArch64_INS_SLI: sli */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SLIv2i32_shift, AArch64_INS_SLI: sli */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SLIv2i64_shift, AArch64_INS_SLI: sli */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SLIv4i16_shift, AArch64_INS_SLI: sli */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SLIv4i32_shift, AArch64_INS_SLI: sli */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SLIv8i16_shift, AArch64_INS_SLI: sli */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SLIv8i8_shift, AArch64_INS_SLI: sli */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SM3PARTW1, AArch64_INS_SM3PARTW1: sm3partw1 */ + 0, + {0}}, + + {/* AArch64_SM3PARTW2, AArch64_INS_SM3PARTW2: sm3partw2 */ + 0, + {0}}, + + {/* AArch64_SM3SS1, AArch64_INS_SM3SS1: sm3ss1 */ + 0, + {0}}, + + {/* AArch64_SM3TT1A, AArch64_INS_SM3TT1A: sm3tt1a */ + 0, + {0}}, + + {/* AArch64_SM3TT1B, AArch64_INS_SM3TT1B: sm3tt1b */ + 0, + {0}}, + + {/* AArch64_SM3TT2A, AArch64_INS_SM3TT2A: sm3tt2a */ + 0, + {0}}, + + {/* AArch64_SM3TT2B, AArch64_INS_SM3TT2B: sm3tt2b */ + 0, + {0}}, + + {/* AArch64_SM4E, AArch64_INS_SM4E: sm4e */ + 0, + {0}}, + + {/* AArch64_SM4ENCKEY, AArch64_INS_SM4EKEY: sm4ekey */ + 0, + {0}}, + + {/* AArch64_SMADDLrrr, AArch64_INS_SMADDL: smaddl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXPv16i8, AArch64_INS_SMAXP: smaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXPv2i32, AArch64_INS_SMAXP: smaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXPv4i16, AArch64_INS_SMAXP: smaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXPv4i32, AArch64_INS_SMAXP: smaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXPv8i16, AArch64_INS_SMAXP: smaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXPv8i8, AArch64_INS_SMAXP: smaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXV_VPZ_B, AArch64_INS_SMAXV: smaxv */ + 0, + {0}}, + + {/* AArch64_SMAXV_VPZ_D, AArch64_INS_SMAXV: smaxv */ + 0, + {0}}, + + {/* AArch64_SMAXV_VPZ_H, AArch64_INS_SMAXV: smaxv */ + 0, + {0}}, + + {/* AArch64_SMAXV_VPZ_S, AArch64_INS_SMAXV: smaxv */ + 0, + {0}}, + + {/* AArch64_SMAXVv16i8v, AArch64_INS_SMAXV: smaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMAXVv4i16v, AArch64_INS_SMAXV: smaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMAXVv4i32v, AArch64_INS_SMAXV: smaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMAXVv8i16v, AArch64_INS_SMAXV: smaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMAXVv8i8v, AArch64_INS_SMAXV: smaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMAX_ZI_B, AArch64_INS_SMAX: smax */ + 0, + {0}}, + + {/* AArch64_SMAX_ZI_D, AArch64_INS_SMAX: smax */ + 0, + {0}}, + + {/* AArch64_SMAX_ZI_H, AArch64_INS_SMAX: smax */ + 0, + {0}}, + + {/* AArch64_SMAX_ZI_S, AArch64_INS_SMAX: smax */ + 0, + {0}}, + + {/* AArch64_SMAX_ZPmZ_B, AArch64_INS_SMAX: smax */ + 0, + {0}}, + + {/* AArch64_SMAX_ZPmZ_D, AArch64_INS_SMAX: smax */ + 0, + {0}}, + + {/* AArch64_SMAX_ZPmZ_H, AArch64_INS_SMAX: smax */ + 0, + {0}}, + + {/* AArch64_SMAX_ZPmZ_S, AArch64_INS_SMAX: smax */ + 0, + {0}}, + + {/* AArch64_SMAXv16i8, AArch64_INS_SMAX: smax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXv2i32, AArch64_INS_SMAX: smax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXv4i16, AArch64_INS_SMAX: smax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXv4i32, AArch64_INS_SMAX: smax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXv8i16, AArch64_INS_SMAX: smax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMAXv8i8, AArch64_INS_SMAX: smax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMC, AArch64_INS_SMC: smc */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_SMINPv16i8, AArch64_INS_SMINP: sminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINPv2i32, AArch64_INS_SMINP: sminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINPv4i16, AArch64_INS_SMINP: sminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINPv4i32, AArch64_INS_SMINP: sminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINPv8i16, AArch64_INS_SMINP: sminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINPv8i8, AArch64_INS_SMINP: sminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINV_VPZ_B, AArch64_INS_SMINV: sminv */ + 0, + {0}}, + + {/* AArch64_SMINV_VPZ_D, AArch64_INS_SMINV: sminv */ + 0, + {0}}, + + {/* AArch64_SMINV_VPZ_H, AArch64_INS_SMINV: sminv */ + 0, + {0}}, + + {/* AArch64_SMINV_VPZ_S, AArch64_INS_SMINV: sminv */ + 0, + {0}}, + + {/* AArch64_SMINVv16i8v, AArch64_INS_SMINV: sminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMINVv4i16v, AArch64_INS_SMINV: sminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMINVv4i32v, AArch64_INS_SMINV: sminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMINVv8i16v, AArch64_INS_SMINV: sminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMINVv8i8v, AArch64_INS_SMINV: sminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SMIN_ZI_B, AArch64_INS_SMIN: smin */ + 0, + {0}}, + + {/* AArch64_SMIN_ZI_D, AArch64_INS_SMIN: smin */ + 0, + {0}}, + + {/* AArch64_SMIN_ZI_H, AArch64_INS_SMIN: smin */ + 0, + {0}}, + + {/* AArch64_SMIN_ZI_S, AArch64_INS_SMIN: smin */ + 0, + {0}}, + + {/* AArch64_SMIN_ZPmZ_B, AArch64_INS_SMIN: smin */ + 0, + {0}}, + + {/* AArch64_SMIN_ZPmZ_D, AArch64_INS_SMIN: smin */ + 0, + {0}}, + + {/* AArch64_SMIN_ZPmZ_H, AArch64_INS_SMIN: smin */ + 0, + {0}}, + + {/* AArch64_SMIN_ZPmZ_S, AArch64_INS_SMIN: smin */ + 0, + {0}}, + + {/* AArch64_SMINv16i8, AArch64_INS_SMIN: smin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINv2i32, AArch64_INS_SMIN: smin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINv4i16, AArch64_INS_SMIN: smin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINv4i32, AArch64_INS_SMIN: smin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINv8i16, AArch64_INS_SMIN: smin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMINv8i8, AArch64_INS_SMIN: smin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLALv16i8_v8i16, AArch64_INS_SMLAL2: smlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLALv2i32_indexed, AArch64_INS_SMLAL: smlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SMLALv2i32_v2i64, AArch64_INS_SMLAL: smlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLALv4i16_indexed, AArch64_INS_SMLAL: smlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SMLALv4i16_v4i32, AArch64_INS_SMLAL: smlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLALv4i32_indexed, AArch64_INS_SMLAL2: smlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SMLALv4i32_v2i64, AArch64_INS_SMLAL2: smlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLALv8i16_indexed, AArch64_INS_SMLAL2: smlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SMLALv8i16_v4i32, AArch64_INS_SMLAL2: smlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLALv8i8_v8i16, AArch64_INS_SMLAL: smlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLSLv16i8_v8i16, AArch64_INS_SMLSL2: smlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLSLv2i32_indexed, AArch64_INS_SMLSL: smlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SMLSLv2i32_v2i64, AArch64_INS_SMLSL: smlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLSLv4i16_indexed, AArch64_INS_SMLSL: smlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SMLSLv4i16_v4i32, AArch64_INS_SMLSL: smlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLSLv4i32_indexed, AArch64_INS_SMLSL2: smlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SMLSLv4i32_v2i64, AArch64_INS_SMLSL2: smlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLSLv8i16_indexed, AArch64_INS_SMLSL2: smlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SMLSLv8i16_v4i32, AArch64_INS_SMLSL2: smlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMLSLv8i8_v8i16, AArch64_INS_SMLSL: smlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMOVvi16to32, AArch64_INS_SMOV: smov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMOVvi16to64, AArch64_INS_SMOV: smov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMOVvi32to64, AArch64_INS_SMOV: smov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMOVvi8to32, AArch64_INS_SMOV: smov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMOVvi8to64, AArch64_INS_SMOV: smov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMSUBLrrr, AArch64_INS_SMNEGL: smnegl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULH_ZPmZ_B, AArch64_INS_SMULH: smulh */ + 0, + {0}}, + + {/* AArch64_SMULH_ZPmZ_D, AArch64_INS_SMULH: smulh */ + 0, + {0}}, + + {/* AArch64_SMULH_ZPmZ_H, AArch64_INS_SMULH: smulh */ + 0, + {0}}, + + {/* AArch64_SMULH_ZPmZ_S, AArch64_INS_SMULH: smulh */ + 0, + {0}}, + + {/* AArch64_SMULHrr, AArch64_INS_SMULH: smulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv16i8_v8i16, AArch64_INS_SMULL2: smull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv2i32_indexed, AArch64_INS_SMULL: smull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv2i32_v2i64, AArch64_INS_SMULL: smull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv4i16_indexed, AArch64_INS_SMULL: smull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv4i16_v4i32, AArch64_INS_SMULL: smull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv4i32_indexed, AArch64_INS_SMULL2: smull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv4i32_v2i64, AArch64_INS_SMULL2: smull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv8i16_indexed, AArch64_INS_SMULL2: smull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv8i16_v4i32, AArch64_INS_SMULL2: smull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SMULLv8i8_v8i16, AArch64_INS_SMULL: smull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SPLICE_ZPZ_B, AArch64_INS_SPLICE: splice */ + 0, + {0}}, + + {/* AArch64_SPLICE_ZPZ_D, AArch64_INS_SPLICE: splice */ + 0, + {0}}, + + {/* AArch64_SPLICE_ZPZ_H, AArch64_INS_SPLICE: splice */ + 0, + {0}}, + + {/* AArch64_SPLICE_ZPZ_S, AArch64_INS_SPLICE: splice */ + 0, + {0}}, + + {/* AArch64_SQABSv16i8, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv1i16, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv1i32, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv1i64, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv1i8, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv2i32, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv2i64, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv4i16, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv4i32, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv8i16, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQABSv8i8, AArch64_INS_SQABS: sqabs */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQADD_ZI_B, AArch64_INS_SQADD: sqadd */ + 0, + {0}}, + + {/* AArch64_SQADD_ZI_D, AArch64_INS_SQADD: sqadd */ + 0, + {0}}, + + {/* AArch64_SQADD_ZI_H, AArch64_INS_SQADD: sqadd */ + 0, + {0}}, + + {/* AArch64_SQADD_ZI_S, AArch64_INS_SQADD: sqadd */ + 0, + {0}}, + + {/* AArch64_SQADD_ZZZ_B, AArch64_INS_SQADD: sqadd */ + 0, + {0}}, + + {/* AArch64_SQADD_ZZZ_D, AArch64_INS_SQADD: sqadd */ + 0, + {0}}, + + {/* AArch64_SQADD_ZZZ_H, AArch64_INS_SQADD: sqadd */ + 0, + {0}}, + + {/* AArch64_SQADD_ZZZ_S, AArch64_INS_SQADD: sqadd */ + 0, + {0}}, + + {/* AArch64_SQADDv16i8, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv1i16, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv1i32, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv1i64, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv1i8, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv2i32, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv2i64, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv4i16, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv4i32, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv8i16, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQADDv8i8, AArch64_INS_SQADD: sqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDECB_XPiI, AArch64_INS_SQDECB: sqdecb */ + 0, + {0}}, + + {/* AArch64_SQDECB_XPiWdI, AArch64_INS_SQDECB: sqdecb */ + 0, + {0}}, + + {/* AArch64_SQDECD_XPiI, AArch64_INS_SQDECD: sqdecd */ + 0, + {0}}, + + {/* AArch64_SQDECD_XPiWdI, AArch64_INS_SQDECD: sqdecd */ + 0, + {0}}, + + {/* AArch64_SQDECD_ZPiI, AArch64_INS_SQDECD: sqdecd */ + 0, + {0}}, + + {/* AArch64_SQDECH_XPiI, AArch64_INS_SQDECH: sqdech */ + 0, + {0}}, + + {/* AArch64_SQDECH_XPiWdI, AArch64_INS_SQDECH: sqdech */ + 0, + {0}}, + + {/* AArch64_SQDECH_ZPiI, AArch64_INS_SQDECH: sqdech */ + 0, + {0}}, + + {/* AArch64_SQDECP_XPWd_B, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_XPWd_D, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_XPWd_H, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_XPWd_S, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_XP_B, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_XP_D, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_XP_H, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_XP_S, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_ZP_D, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_ZP_H, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECP_ZP_S, AArch64_INS_SQDECP: sqdecp */ + 0, + {0}}, + + {/* AArch64_SQDECW_XPiI, AArch64_INS_SQDECW: sqdecw */ + 0, + {0}}, + + {/* AArch64_SQDECW_XPiWdI, AArch64_INS_SQDECW: sqdecw */ + 0, + {0}}, + + {/* AArch64_SQDECW_ZPiI, AArch64_INS_SQDECW: sqdecw */ + 0, + {0}}, + + {/* AArch64_SQDMLALi16, AArch64_INS_SQDMLAL: sqdmlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLALi32, AArch64_INS_SQDMLAL: sqdmlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLALv1i32_indexed, AArch64_INS_SQDMLAL: sqdmlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLALv1i64_indexed, AArch64_INS_SQDMLAL: sqdmlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLALv2i32_indexed, AArch64_INS_SQDMLAL: sqdmlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLALv2i32_v2i64, AArch64_INS_SQDMLAL: sqdmlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLALv4i16_indexed, AArch64_INS_SQDMLAL: sqdmlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLALv4i16_v4i32, AArch64_INS_SQDMLAL: sqdmlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLALv4i32_indexed, AArch64_INS_SQDMLAL2: sqdmlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLALv4i32_v2i64, AArch64_INS_SQDMLAL2: sqdmlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLALv8i16_indexed, AArch64_INS_SQDMLAL2: sqdmlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLALv8i16_v4i32, AArch64_INS_SQDMLAL2: sqdmlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLSLi16, AArch64_INS_SQDMLSL: sqdmlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLSLi32, AArch64_INS_SQDMLSL: sqdmlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLSLv1i32_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLSLv1i64_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLSLv2i32_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLSLv2i32_v2i64, AArch64_INS_SQDMLSL: sqdmlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLSLv4i16_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLSLv4i16_v4i32, AArch64_INS_SQDMLSL: sqdmlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLSLv4i32_indexed, AArch64_INS_SQDMLSL2: sqdmlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLSLv4i32_v2i64, AArch64_INS_SQDMLSL2: sqdmlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMLSLv8i16_indexed, AArch64_INS_SQDMLSL2: sqdmlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQDMLSLv8i16_v4i32, AArch64_INS_SQDMLSL2: sqdmlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv1i16, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv1i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv1i32, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv1i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv2i32, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv2i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv4i16, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv4i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv4i32, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv4i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv8i16, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULHv8i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLi16, AArch64_INS_SQDMULL: sqdmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLi32, AArch64_INS_SQDMULL: sqdmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv1i32_indexed, AArch64_INS_SQDMULL: sqdmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv1i64_indexed, AArch64_INS_SQDMULL: sqdmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv2i32_indexed, AArch64_INS_SQDMULL: sqdmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv2i32_v2i64, AArch64_INS_SQDMULL: sqdmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv4i16_indexed, AArch64_INS_SQDMULL: sqdmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv4i16_v4i32, AArch64_INS_SQDMULL: sqdmull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv4i32_indexed, AArch64_INS_SQDMULL2: sqdmull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv4i32_v2i64, AArch64_INS_SQDMULL2: sqdmull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv8i16_indexed, AArch64_INS_SQDMULL2: sqdmull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQDMULLv8i16_v4i32, AArch64_INS_SQDMULL2: sqdmull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQINCB_XPiI, AArch64_INS_SQINCB: sqincb */ + 0, + {0}}, + + {/* AArch64_SQINCB_XPiWdI, AArch64_INS_SQINCB: sqincb */ + 0, + {0}}, + + {/* AArch64_SQINCD_XPiI, AArch64_INS_SQINCD: sqincd */ + 0, + {0}}, + + {/* AArch64_SQINCD_XPiWdI, AArch64_INS_SQINCD: sqincd */ + 0, + {0}}, + + {/* AArch64_SQINCD_ZPiI, AArch64_INS_SQINCD: sqincd */ + 0, + {0}}, + + {/* AArch64_SQINCH_XPiI, AArch64_INS_SQINCH: sqinch */ + 0, + {0}}, + + {/* AArch64_SQINCH_XPiWdI, AArch64_INS_SQINCH: sqinch */ + 0, + {0}}, + + {/* AArch64_SQINCH_ZPiI, AArch64_INS_SQINCH: sqinch */ + 0, + {0}}, + + {/* AArch64_SQINCP_XPWd_B, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_XPWd_D, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_XPWd_H, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_XPWd_S, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_XP_B, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_XP_D, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_XP_H, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_XP_S, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_ZP_D, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_ZP_H, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCP_ZP_S, AArch64_INS_SQINCP: sqincp */ + 0, + {0}}, + + {/* AArch64_SQINCW_XPiI, AArch64_INS_SQINCW: sqincw */ + 0, + {0}}, + + {/* AArch64_SQINCW_XPiWdI, AArch64_INS_SQINCW: sqincw */ + 0, + {0}}, + + {/* AArch64_SQINCW_ZPiI, AArch64_INS_SQINCW: sqincw */ + 0, + {0}}, + + {/* AArch64_SQNEGv16i8, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv1i16, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv1i32, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv1i64, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv1i8, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv2i32, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv2i64, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv4i16, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv4i32, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv8i16, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQNEGv8i8, AArch64_INS_SQNEG: sqneg */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQRDMLAHi16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHi32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv1i16, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv1i32, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv2i32, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv2i32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv4i16, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv4i16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv4i32, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv4i32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv8i16, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLAHv8i16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHi16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHi32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv1i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv1i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv2i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv2i32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv4i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv4i16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv4i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv4i32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv8i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMLSHv8i16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + {0}}, + + {/* AArch64_SQRDMULHv1i16, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRDMULHv1i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQRDMULHv1i32, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRDMULHv1i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQRDMULHv2i32, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRDMULHv2i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQRDMULHv4i16, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRDMULHv4i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQRDMULHv4i32, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRDMULHv4i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQRDMULHv8i16, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRDMULHv8i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SQRSHLv16i8, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv1i16, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv1i32, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv1i64, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv1i8, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv2i32, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv2i64, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv4i16, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv4i32, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv8i16, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHLv8i8, AArch64_INS_SQRSHL: sqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRNb, AArch64_INS_SQRSHRN: sqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRNh, AArch64_INS_SQRSHRN: sqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRNs, AArch64_INS_SQRSHRN: sqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRNv16i8_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRNv2i32_shift, AArch64_INS_SQRSHRN: sqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRNv4i16_shift, AArch64_INS_SQRSHRN: sqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRNv4i32_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRNv8i16_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRNv8i8_shift, AArch64_INS_SQRSHRN: sqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRUNb, AArch64_INS_SQRSHRUN: sqrshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRUNh, AArch64_INS_SQRSHRUN: sqrshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRUNs, AArch64_INS_SQRSHRUN: sqrshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRUNv16i8_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRUNv2i32_shift, AArch64_INS_SQRSHRUN: sqrshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRUNv4i16_shift, AArch64_INS_SQRSHRUN: sqrshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRUNv4i32_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRUNv8i16_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQRSHRUNv8i8_shift, AArch64_INS_SQRSHRUN: sqrshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUb, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUd, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUh, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUs, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUv16i8_shift, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUv2i32_shift, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUv2i64_shift, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUv4i16_shift, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUv4i32_shift, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUv8i16_shift, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLUv8i8_shift, AArch64_INS_SQSHLU: sqshlu */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLb, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLd, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLh, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLs, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv16i8, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv16i8_shift, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv1i16, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv1i32, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv1i64, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv1i8, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv2i32, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv2i32_shift, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv2i64, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv2i64_shift, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv4i16, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv4i16_shift, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv4i32, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv4i32_shift, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv8i16, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv8i16_shift, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv8i8, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHLv8i8_shift, AArch64_INS_SQSHL: sqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRNb, AArch64_INS_SQSHRN: sqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRNh, AArch64_INS_SQSHRN: sqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRNs, AArch64_INS_SQSHRN: sqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRNv16i8_shift, AArch64_INS_SQSHRN2: sqshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRNv2i32_shift, AArch64_INS_SQSHRN: sqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRNv4i16_shift, AArch64_INS_SQSHRN: sqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRNv4i32_shift, AArch64_INS_SQSHRN2: sqshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRNv8i16_shift, AArch64_INS_SQSHRN2: sqshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRNv8i8_shift, AArch64_INS_SQSHRN: sqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRUNb, AArch64_INS_SQSHRUN: sqshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRUNh, AArch64_INS_SQSHRUN: sqshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRUNs, AArch64_INS_SQSHRUN: sqshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRUNv16i8_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRUNv2i32_shift, AArch64_INS_SQSHRUN: sqshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRUNv4i16_shift, AArch64_INS_SQSHRUN: sqshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRUNv4i32_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRUNv8i16_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSHRUNv8i8_shift, AArch64_INS_SQSHRUN: sqshrun */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUB_ZI_B, AArch64_INS_SQSUB: sqsub */ + 0, + {0}}, + + {/* AArch64_SQSUB_ZI_D, AArch64_INS_SQSUB: sqsub */ + 0, + {0}}, + + {/* AArch64_SQSUB_ZI_H, AArch64_INS_SQSUB: sqsub */ + 0, + {0}}, + + {/* AArch64_SQSUB_ZI_S, AArch64_INS_SQSUB: sqsub */ + 0, + {0}}, + + {/* AArch64_SQSUB_ZZZ_B, AArch64_INS_SQSUB: sqsub */ + 0, + {0}}, + + {/* AArch64_SQSUB_ZZZ_D, AArch64_INS_SQSUB: sqsub */ + 0, + {0}}, + + {/* AArch64_SQSUB_ZZZ_H, AArch64_INS_SQSUB: sqsub */ + 0, + {0}}, + + {/* AArch64_SQSUB_ZZZ_S, AArch64_INS_SQSUB: sqsub */ + 0, + {0}}, + + {/* AArch64_SQSUBv16i8, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv1i16, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv1i32, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv1i64, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv1i8, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv2i32, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv2i64, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv4i16, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv4i32, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv8i16, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQSUBv8i8, AArch64_INS_SQSUB: sqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SQXTNv16i8, AArch64_INS_SQXTN2: sqxtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTNv1i16, AArch64_INS_SQXTN: sqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTNv1i32, AArch64_INS_SQXTN: sqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTNv1i8, AArch64_INS_SQXTN: sqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTNv2i32, AArch64_INS_SQXTN: sqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTNv4i16, AArch64_INS_SQXTN: sqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTNv4i32, AArch64_INS_SQXTN2: sqxtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTNv8i16, AArch64_INS_SQXTN2: sqxtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTNv8i8, AArch64_INS_SQXTN: sqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTUNv16i8, AArch64_INS_SQXTUN2: sqxtun2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTUNv1i16, AArch64_INS_SQXTUN: sqxtun */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTUNv1i32, AArch64_INS_SQXTUN: sqxtun */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTUNv1i8, AArch64_INS_SQXTUN: sqxtun */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTUNv2i32, AArch64_INS_SQXTUN: sqxtun */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTUNv4i16, AArch64_INS_SQXTUN: sqxtun */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTUNv4i32, AArch64_INS_SQXTUN2: sqxtun2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTUNv8i16, AArch64_INS_SQXTUN2: sqxtun2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SQXTUNv8i8, AArch64_INS_SQXTUN: sqxtun */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_SRHADDv16i8, AArch64_INS_SRHADD: srhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRHADDv2i32, AArch64_INS_SRHADD: srhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRHADDv4i16, AArch64_INS_SRHADD: srhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRHADDv4i32, AArch64_INS_SRHADD: srhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRHADDv8i16, AArch64_INS_SRHADD: srhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRHADDv8i8, AArch64_INS_SRHADD: srhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRId, AArch64_INS_SRI: sri */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRIv16i8_shift, AArch64_INS_SRI: sri */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRIv2i32_shift, AArch64_INS_SRI: sri */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRIv2i64_shift, AArch64_INS_SRI: sri */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRIv4i16_shift, AArch64_INS_SRI: sri */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRIv4i32_shift, AArch64_INS_SRI: sri */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRIv8i16_shift, AArch64_INS_SRI: sri */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRIv8i8_shift, AArch64_INS_SRI: sri */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHLv16i8, AArch64_INS_SRSHL: srshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHLv1i64, AArch64_INS_SRSHL: srshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHLv2i32, AArch64_INS_SRSHL: srshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHLv2i64, AArch64_INS_SRSHL: srshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHLv4i16, AArch64_INS_SRSHL: srshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHLv4i32, AArch64_INS_SRSHL: srshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHLv8i16, AArch64_INS_SRSHL: srshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHLv8i8, AArch64_INS_SRSHL: srshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHRd, AArch64_INS_SRSHR: srshr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHRv16i8_shift, AArch64_INS_SRSHR: srshr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHRv2i32_shift, AArch64_INS_SRSHR: srshr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHRv2i64_shift, AArch64_INS_SRSHR: srshr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHRv4i16_shift, AArch64_INS_SRSHR: srshr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHRv4i32_shift, AArch64_INS_SRSHR: srshr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHRv8i16_shift, AArch64_INS_SRSHR: srshr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSHRv8i8_shift, AArch64_INS_SRSHR: srshr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSRAd, AArch64_INS_SRSRA: srsra */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSRAv16i8_shift, AArch64_INS_SRSRA: srsra */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSRAv2i32_shift, AArch64_INS_SRSRA: srsra */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSRAv2i64_shift, AArch64_INS_SRSRA: srsra */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSRAv4i16_shift, AArch64_INS_SRSRA: srsra */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSRAv4i32_shift, AArch64_INS_SRSRA: srsra */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSRAv8i16_shift, AArch64_INS_SRSRA: srsra */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SRSRAv8i8_shift, AArch64_INS_SRSRA: srsra */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLLv16i8_shift, AArch64_INS_SSHLL2: sshll2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLLv2i32_shift, AArch64_INS_SSHLL: sshll */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLLv4i16_shift, AArch64_INS_SSHLL: sshll */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLLv4i32_shift, AArch64_INS_SSHLL2: sshll2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLLv8i16_shift, AArch64_INS_SSHLL2: sshll2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLLv8i8_shift, AArch64_INS_SSHLL: sshll */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLv16i8, AArch64_INS_SSHL: sshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLv1i64, AArch64_INS_SSHL: sshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLv2i32, AArch64_INS_SSHL: sshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLv2i64, AArch64_INS_SSHL: sshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLv4i16, AArch64_INS_SSHL: sshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLv4i32, AArch64_INS_SSHL: sshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLv8i16, AArch64_INS_SSHL: sshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHLv8i8, AArch64_INS_SSHL: sshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHRd, AArch64_INS_SSHR: sshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHRv16i8_shift, AArch64_INS_SSHR: sshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHRv2i32_shift, AArch64_INS_SSHR: sshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHRv2i64_shift, AArch64_INS_SSHR: sshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHRv4i16_shift, AArch64_INS_SSHR: sshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHRv4i32_shift, AArch64_INS_SSHR: sshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHRv8i16_shift, AArch64_INS_SSHR: sshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSHRv8i8_shift, AArch64_INS_SSHR: sshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSRAd, AArch64_INS_SSRA: ssra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSRAv16i8_shift, AArch64_INS_SSRA: ssra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSRAv2i32_shift, AArch64_INS_SSRA: ssra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSRAv2i64_shift, AArch64_INS_SSRA: ssra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSRAv4i16_shift, AArch64_INS_SSRA: ssra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSRAv4i32_shift, AArch64_INS_SSRA: ssra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSRAv8i16_shift, AArch64_INS_SSRA: ssra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSRAv8i8_shift, AArch64_INS_SSRA: ssra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SST1B_D, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_SST1B_D_IMM, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_SST1B_D_SXTW, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_SST1B_D_UXTW, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_SST1B_S_IMM, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_SST1B_S_SXTW, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_SST1B_S_UXTW, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_SST1D, AArch64_INS_ST1D: st1d */ + 0, + {0}}, + + {/* AArch64_SST1D_IMM, AArch64_INS_ST1D: st1d */ + 0, + {0}}, + + {/* AArch64_SST1D_SCALED, AArch64_INS_ST1D: st1d */ + 0, + {0}}, + + {/* AArch64_SST1D_SXTW, AArch64_INS_ST1D: st1d */ + 0, + {0}}, + + {/* AArch64_SST1D_SXTW_SCALED, AArch64_INS_ST1D: st1d */ + 0, + {0}}, + + {/* AArch64_SST1D_UXTW, AArch64_INS_ST1D: st1d */ + 0, + {0}}, + + {/* AArch64_SST1D_UXTW_SCALED, AArch64_INS_ST1D: st1d */ + 0, + {0}}, + + {/* AArch64_SST1H_D, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_D_IMM, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_D_SCALED, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_D_SXTW, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_D_SXTW_SCALED, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_D_UXTW, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_D_UXTW_SCALED, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_S_IMM, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_S_SXTW, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_S_SXTW_SCALED, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_S_UXTW, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1H_S_UXTW_SCALED, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_SST1W_D, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_D_IMM, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_D_SCALED, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_D_SXTW, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_D_SXTW_SCALED, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_D_UXTW, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_D_UXTW_SCALED, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_IMM, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_SXTW, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_SXTW_SCALED, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_UXTW, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SST1W_UXTW_SCALED, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_SSUBLv16i8_v8i16, AArch64_INS_SSUBL2: ssubl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBLv2i32_v2i64, AArch64_INS_SSUBL: ssubl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBLv4i16_v4i32, AArch64_INS_SSUBL: ssubl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBLv4i32_v2i64, AArch64_INS_SSUBL2: ssubl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBLv8i16_v4i32, AArch64_INS_SSUBL2: ssubl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBLv8i8_v8i16, AArch64_INS_SSUBL: ssubl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBWv16i8_v8i16, AArch64_INS_SSUBW2: ssubw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBWv2i32_v2i64, AArch64_INS_SSUBW: ssubw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBWv4i16_v4i32, AArch64_INS_SSUBW: ssubw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBWv4i32_v2i64, AArch64_INS_SSUBW2: ssubw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBWv8i16_v4i32, AArch64_INS_SSUBW2: ssubw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SSUBWv8i8_v8i16, AArch64_INS_SSUBW: ssubw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1B, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_ST1B_D, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_ST1B_D_IMM, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_ST1B_H, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_ST1B_H_IMM, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_ST1B_IMM, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_ST1B_S, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_ST1B_S_IMM, AArch64_INS_ST1B: st1b */ + 0, + {0}}, + + {/* AArch64_ST1D, AArch64_INS_ST1D: st1d */ + 0, + {0}}, + + {/* AArch64_ST1D_IMM, AArch64_INS_ST1D: st1d */ + 0, + {0}}, + + {/* AArch64_ST1Fourv16b, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv16b_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv1d, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv1d_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv2d, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv2d_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv2s, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv2s_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv4h, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv4h_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv4s, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv4s_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv8b, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv8b_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv8h, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Fourv8h_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1H, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_ST1H_D, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_ST1H_D_IMM, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_ST1H_IMM, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_ST1H_S, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_ST1H_S_IMM, AArch64_INS_ST1H: st1h */ + 0, + {0}}, + + {/* AArch64_ST1Onev16b, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev16b_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev1d, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev1d_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev2d, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev2d_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev2s, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev2s_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev4h, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev4h_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev4s, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev4s_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev8b, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev8b_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev8h, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Onev8h_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev16b, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev16b_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev1d, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev1d_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev2d, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev2d_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev2s, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev2s_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev4h, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev4h_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev4s, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev4s_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev8b, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev8b_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev8h, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Threev8h_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov16b, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov16b_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov1d, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov1d_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov2d, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov2d_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov2s, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov2s_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov4h, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov4h_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov4s, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov4s_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov8b, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov8b_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov8h, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1Twov8h_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1W, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_ST1W_D, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_ST1W_D_IMM, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_ST1W_IMM, AArch64_INS_ST1W: st1w */ + 0, + {0}}, + + {/* AArch64_ST1i16, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1i16_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1i32, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1i32_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1i64, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1i64_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST1i8, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST1i8_POST, AArch64_INS_ST1: st1 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2B, AArch64_INS_ST2B: st2b */ + 0, + {0}}, + + {/* AArch64_ST2B_IMM, AArch64_INS_ST2B: st2b */ + 0, + {0}}, + + {/* AArch64_ST2D, AArch64_INS_ST2D: st2d */ + 0, + {0}}, + + {/* AArch64_ST2D_IMM, AArch64_INS_ST2D: st2d */ + 0, + {0}}, + + {/* AArch64_ST2H, AArch64_INS_ST2H: st2h */ + 0, + {0}}, + + {/* AArch64_ST2H_IMM, AArch64_INS_ST2H: st2h */ + 0, + {0}}, + + {/* AArch64_ST2Twov16b, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov16b_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov2d, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov2d_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov2s, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov2s_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov4h, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov4h_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov4s, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov4s_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov8b, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov8b_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov8h, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2Twov8h_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2W, AArch64_INS_ST2W: st2w */ + 0, + {0}}, + + {/* AArch64_ST2W_IMM, AArch64_INS_ST2W: st2w */ + 0, + {0}}, + + {/* AArch64_ST2i16, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2i16_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2i32, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2i32_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2i64, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2i64_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST2i8, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST2i8_POST, AArch64_INS_ST2: st2 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3B, AArch64_INS_ST3B: st3b */ + 0, + {0}}, + + {/* AArch64_ST3B_IMM, AArch64_INS_ST3B: st3b */ + 0, + {0}}, + + {/* AArch64_ST3D, AArch64_INS_ST3D: st3d */ + 0, + {0}}, + + {/* AArch64_ST3D_IMM, AArch64_INS_ST3D: st3d */ + 0, + {0}}, + + {/* AArch64_ST3H, AArch64_INS_ST3H: st3h */ + 0, + {0}}, + + {/* AArch64_ST3H_IMM, AArch64_INS_ST3H: st3h */ + 0, + {0}}, + + {/* AArch64_ST3Threev16b, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev16b_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev2d, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev2d_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev2s, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev2s_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev4h, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev4h_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev4s, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev4s_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev8b, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev8b_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev8h, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3Threev8h_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3W, AArch64_INS_ST3W: st3w */ + 0, + {0}}, + + {/* AArch64_ST3W_IMM, AArch64_INS_ST3W: st3w */ + 0, + {0}}, + + {/* AArch64_ST3i16, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3i16_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3i32, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3i32_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3i64, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3i64_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST3i8, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST3i8_POST, AArch64_INS_ST3: st3 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4B, AArch64_INS_ST4B: st4b */ + 0, + {0}}, + + {/* AArch64_ST4B_IMM, AArch64_INS_ST4B: st4b */ + 0, + {0}}, + + {/* AArch64_ST4D, AArch64_INS_ST4D: st4d */ + 0, + {0}}, + + {/* AArch64_ST4D_IMM, AArch64_INS_ST4D: st4d */ + 0, + {0}}, + + {/* AArch64_ST4Fourv16b, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv16b_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv2d, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv2d_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv2s, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv2s_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv4h, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv4h_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv4s, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv4s_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv8b, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv8b_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv8h, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4Fourv8h_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4H, AArch64_INS_ST4H: st4h */ + 0, + {0}}, + + {/* AArch64_ST4H_IMM, AArch64_INS_ST4H: st4h */ + 0, + {0}}, + + {/* AArch64_ST4W, AArch64_INS_ST4W: st4w */ + 0, + {0}}, + + {/* AArch64_ST4W_IMM, AArch64_INS_ST4W: st4w */ + 0, + {0}}, + + {/* AArch64_ST4i16, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4i16_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4i32, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4i32_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4i64, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4i64_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ST4i8, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0}}, + + {/* AArch64_ST4i8_POST, AArch64_INS_ST4: st4 */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLLRB, AArch64_INS_STLLRB: stllrb */ + 0, + {0}}, + + {/* AArch64_STLLRH, AArch64_INS_STLLRH: stllrh */ + 0, + {0}}, + + {/* AArch64_STLLRW, AArch64_INS_STLLR: stllr */ + 0, + {0}}, + + {/* AArch64_STLLRX, AArch64_INS_STLLR: stllr */ + 0, + {0}}, + + {/* AArch64_STLRB, AArch64_INS_STLRB: stlrb */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLRH, AArch64_INS_STLRH: stlrh */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLRW, AArch64_INS_STLR: stlr */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLRX, AArch64_INS_STLR: stlr */ + 0, + {CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLURBi, AArch64_INS_STLURB: stlurb */ + 0, + {0}}, + + {/* AArch64_STLURHi, AArch64_INS_STLURH: stlurh */ + 0, + {0}}, + + {/* AArch64_STLURWi, AArch64_INS_STLUR: stlur */ + 0, + {0}}, + + {/* AArch64_STLURXi, AArch64_INS_STLUR: stlur */ + 0, + {0}}, + + {/* AArch64_STLXPW, AArch64_INS_STLXP: stlxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLXPX, AArch64_INS_STLXP: stlxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLXRB, AArch64_INS_STLXRB: stlxrb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLXRH, AArch64_INS_STLXRH: stlxrh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLXRW, AArch64_INS_STLXR: stlxr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STLXRX, AArch64_INS_STLXR: stlxr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STNPDi, AArch64_INS_STNP: stnp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STNPQi, AArch64_INS_STNP: stnp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STNPSi, AArch64_INS_STNP: stnp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STNPWi, AArch64_INS_STNP: stnp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STNPXi, AArch64_INS_STNP: stnp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STNT1B_ZRI, AArch64_INS_STNT1B: stnt1b */ + 0, + {0}}, + + {/* AArch64_STNT1B_ZRR, AArch64_INS_STNT1B: stnt1b */ + 0, + {0}}, + + {/* AArch64_STNT1D_ZRI, AArch64_INS_STNT1D: stnt1d */ + 0, + {0}}, + + {/* AArch64_STNT1D_ZRR, AArch64_INS_STNT1D: stnt1d */ + 0, + {0}}, + + {/* AArch64_STNT1H_ZRI, AArch64_INS_STNT1H: stnt1h */ + 0, + {0}}, + + {/* AArch64_STNT1H_ZRR, AArch64_INS_STNT1H: stnt1h */ + 0, + {0}}, + + {/* AArch64_STNT1W_ZRI, AArch64_INS_STNT1W: stnt1w */ + 0, + {0}}, + + {/* AArch64_STNT1W_ZRR, AArch64_INS_STNT1W: stnt1w */ + 0, + {0}}, + + {/* AArch64_STPDi, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPDpost, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPDpre, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPQi, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPQpost, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPQpre, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPSi, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPSpost, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPSpre, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPWi, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPWpost, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPWpre, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPXi, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPXpost, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STPXpre, AArch64_INS_STP: stp */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRBBpost, AArch64_INS_STRB: strb */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRBBpre, AArch64_INS_STRB: strb */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRBBroW, AArch64_INS_STRB: strb */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRBBroX, AArch64_INS_STRB: strb */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRBBui, AArch64_INS_STRB: strb */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRBpost, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRBpre, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRBroW, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRBroX, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRBui, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRDpost, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRDpre, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRDroW, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRDroX, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRDui, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRHHpost, AArch64_INS_STRH: strh */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRHHpre, AArch64_INS_STRH: strh */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRHHroW, AArch64_INS_STRH: strh */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRHHroX, AArch64_INS_STRH: strh */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRHHui, AArch64_INS_STRH: strh */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRHpost, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRHpre, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRHroW, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRHroX, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRHui, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRQpost, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRQpre, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRQroW, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRQroX, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRQui, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRSpost, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRSpre, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRSroW, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRSroX, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRSui, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRWpost, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRWpre, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRWroW, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRWroX, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRWui, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRXpost, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRXpre, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STRXroW, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRXroX, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STRXui, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STR_PXI, AArch64_INS_STR: str */ + 0, + {0}}, + + {/* AArch64_STR_ZXI, AArch64_INS_STR: str */ + 0, + {0}}, + + {/* AArch64_STTRBi, AArch64_INS_STTRB: sttrb */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STTRHi, AArch64_INS_STTRH: sttrh */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STTRWi, AArch64_INS_STTR: sttr */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STTRXi, AArch64_INS_STTR: sttr */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STURBBi, AArch64_INS_STRB: strb */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STURBi, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STURDi, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STURHHi, AArch64_INS_STRH: strh */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STURHi, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STURQi, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STURSi, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STURWi, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STURXi, AArch64_INS_STR: str */ + 0, + {CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STXPW, AArch64_INS_STXP: stxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STXPX, AArch64_INS_STXP: stxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_STXRB, AArch64_INS_STXRB: stxrb */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STXRH, AArch64_INS_STXRH: stxrh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STXRW, AArch64_INS_STXR: stxr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_STXRX, AArch64_INS_STXR: stxr */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBHNv2i64_v2i32, AArch64_INS_SUBHN: subhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBHNv2i64_v4i32, AArch64_INS_SUBHN2: subhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBHNv4i32_v4i16, AArch64_INS_SUBHN: subhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBHNv4i32_v8i16, AArch64_INS_SUBHN2: subhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBHNv8i16_v16i8, AArch64_INS_SUBHN2: subhn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBHNv8i16_v8i8, AArch64_INS_SUBHN: subhn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBR_ZI_B, AArch64_INS_SUBR: subr */ + 0, + {0}}, + + {/* AArch64_SUBR_ZI_D, AArch64_INS_SUBR: subr */ + 0, + {0}}, + + {/* AArch64_SUBR_ZI_H, AArch64_INS_SUBR: subr */ + 0, + {0}}, + + {/* AArch64_SUBR_ZI_S, AArch64_INS_SUBR: subr */ + 0, + {0}}, + + {/* AArch64_SUBR_ZPmZ_B, AArch64_INS_SUBR: subr */ + 0, + {0}}, + + {/* AArch64_SUBR_ZPmZ_D, AArch64_INS_SUBR: subr */ + 0, + {0}}, + + {/* AArch64_SUBR_ZPmZ_H, AArch64_INS_SUBR: subr */ + 0, + {0}}, + + {/* AArch64_SUBR_ZPmZ_S, AArch64_INS_SUBR: subr */ + 0, + {0}}, + + {/* AArch64_SUBSWri, AArch64_INS_ADDS: adds */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBSWrs, AArch64_INS_CMP: cmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBSWrx, AArch64_INS_CMP: cmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBSXri, AArch64_INS_ADDS: adds */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBSXrs, AArch64_INS_CMP: cmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBSXrx, AArch64_INS_CMP: cmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBSXrx64, AArch64_INS_CMP: cmp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SUBWri, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBWrs, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBWrx, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBXri, AArch64_INS_ADD: add */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBXrs, AArch64_INS_NEG: neg */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBXrx, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBXrx64, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ}}, + + {/* AArch64_SUB_ZI_B, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZI_D, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZI_H, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZI_S, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZPmZ_B, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZPmZ_D, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZPmZ_H, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZPmZ_S, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZZZ_B, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZZZ_D, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZZZ_H, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUB_ZZZ_S, AArch64_INS_SUB: sub */ + 0, + {0}}, + + {/* AArch64_SUBv16i8, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBv1i64, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBv2i32, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBv2i64, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBv4i16, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBv4i32, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBv8i16, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUBv8i8, AArch64_INS_SUB: sub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUNPKHI_ZZ_D, AArch64_INS_SUNPKHI: sunpkhi */ + 0, + {0}}, + + {/* AArch64_SUNPKHI_ZZ_H, AArch64_INS_SUNPKHI: sunpkhi */ + 0, + {0}}, + + {/* AArch64_SUNPKHI_ZZ_S, AArch64_INS_SUNPKHI: sunpkhi */ + 0, + {0}}, + + {/* AArch64_SUNPKLO_ZZ_D, AArch64_INS_SUNPKLO: sunpklo */ + 0, + {0}}, + + {/* AArch64_SUNPKLO_ZZ_H, AArch64_INS_SUNPKLO: sunpklo */ + 0, + {0}}, + + {/* AArch64_SUNPKLO_ZZ_S, AArch64_INS_SUNPKLO: sunpklo */ + 0, + {0}}, + + {/* AArch64_SUQADDv16i8, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv1i16, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv1i32, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv1i64, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv1i8, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv2i32, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv2i64, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv4i16, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv4i32, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv8i16, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SUQADDv8i8, AArch64_INS_SUQADD: suqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_SVC, AArch64_INS_SVC: svc */ + 0, + {CS_AC_READ, 0}}, + + {/* AArch64_SWPAB, AArch64_INS_SWPAB: swpab */ + 0, + {0}}, + + {/* AArch64_SWPAH, AArch64_INS_SWPAH: swpah */ + 0, + {0}}, + + {/* AArch64_SWPALB, AArch64_INS_SWPALB: swpalb */ + 0, + {0}}, + + {/* AArch64_SWPALH, AArch64_INS_SWPALH: swpalh */ + 0, + {0}}, + + {/* AArch64_SWPALW, AArch64_INS_SWPAL: swpal */ + 0, + {0}}, + + {/* AArch64_SWPALX, AArch64_INS_SWPAL: swpal */ + 0, + {0}}, + + {/* AArch64_SWPAW, AArch64_INS_SWPA: swpa */ + 0, + {0}}, + + {/* AArch64_SWPAX, AArch64_INS_SWPA: swpa */ + 0, + {0}}, + + {/* AArch64_SWPB, AArch64_INS_SWPB: swpb */ + 0, + {0}}, + + {/* AArch64_SWPH, AArch64_INS_SWPH: swph */ + 0, + {0}}, + + {/* AArch64_SWPLB, AArch64_INS_SWPLB: swplb */ + 0, + {0}}, + + {/* AArch64_SWPLH, AArch64_INS_SWPLH: swplh */ + 0, + {0}}, + + {/* AArch64_SWPLW, AArch64_INS_SWPL: swpl */ + 0, + {0}}, + + {/* AArch64_SWPLX, AArch64_INS_SWPL: swpl */ + 0, + {0}}, + + {/* AArch64_SWPW, AArch64_INS_SWP: swp */ + 0, + {0}}, + + {/* AArch64_SWPX, AArch64_INS_SWP: swp */ + 0, + {0}}, + + {/* AArch64_SXTB_ZPmZ_D, AArch64_INS_SXTB: sxtb */ + 0, + {0}}, + + {/* AArch64_SXTB_ZPmZ_H, AArch64_INS_SXTB: sxtb */ + 0, + {0}}, + + {/* AArch64_SXTB_ZPmZ_S, AArch64_INS_SXTB: sxtb */ + 0, + {0}}, + + {/* AArch64_SXTH_ZPmZ_D, AArch64_INS_SXTH: sxth */ + 0, + {0}}, + + {/* AArch64_SXTH_ZPmZ_S, AArch64_INS_SXTH: sxth */ + 0, + {0}}, + + {/* AArch64_SXTW_ZPmZ_D, AArch64_INS_SXTW: sxtw */ + 0, + {0}}, + + {/* AArch64_SYSLxt, AArch64_INS_SYSL: sysl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_READ}}, + + {/* AArch64_SYSxt, AArch64_INS_SYS: sys */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_WRITE | CS_AC_READ}}, + + {/* AArch64_TBL_ZZZ_B, AArch64_INS_TBL: tbl */ + 0, + {0}}, + + {/* AArch64_TBL_ZZZ_D, AArch64_INS_TBL: tbl */ + 0, + {0}}, + + {/* AArch64_TBL_ZZZ_H, AArch64_INS_TBL: tbl */ + 0, + {0}}, + + {/* AArch64_TBL_ZZZ_S, AArch64_INS_TBL: tbl */ + 0, + {0}}, + + {/* AArch64_TBLv16i8Four, AArch64_INS_TBL: tbl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBLv16i8One, AArch64_INS_TBL: tbl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBLv16i8Three, AArch64_INS_TBL: tbl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBLv16i8Two, AArch64_INS_TBL: tbl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBLv8i8Four, AArch64_INS_TBL: tbl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBLv8i8One, AArch64_INS_TBL: tbl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBLv8i8Three, AArch64_INS_TBL: tbl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBLv8i8Two, AArch64_INS_TBL: tbl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBNZW, AArch64_INS_TBNZ: tbnz */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBNZX, AArch64_INS_TBNZ: tbnz */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBXv16i8Four, AArch64_INS_TBX: tbx */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBXv16i8One, AArch64_INS_TBX: tbx */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBXv16i8Three, AArch64_INS_TBX: tbx */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBXv16i8Two, AArch64_INS_TBX: tbx */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBXv8i8Four, AArch64_INS_TBX: tbx */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBXv8i8One, AArch64_INS_TBX: tbx */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBXv8i8Three, AArch64_INS_TBX: tbx */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBXv8i8Two, AArch64_INS_TBX: tbx */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBZW, AArch64_INS_TBZ: tbz */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TBZX, AArch64_INS_TBZ: tbz */ + 0, + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN1_PPP_B, AArch64_INS_TRN1: trn1 */ + 0, + {0}}, + + {/* AArch64_TRN1_PPP_D, AArch64_INS_TRN1: trn1 */ + 0, + {0}}, + + {/* AArch64_TRN1_PPP_H, AArch64_INS_TRN1: trn1 */ + 0, + {0}}, + + {/* AArch64_TRN1_PPP_S, AArch64_INS_TRN1: trn1 */ + 0, + {0}}, + + {/* AArch64_TRN1_ZZZ_B, AArch64_INS_TRN1: trn1 */ + 0, + {0}}, + + {/* AArch64_TRN1_ZZZ_D, AArch64_INS_TRN1: trn1 */ + 0, + {0}}, + + {/* AArch64_TRN1_ZZZ_H, AArch64_INS_TRN1: trn1 */ + 0, + {0}}, + + {/* AArch64_TRN1_ZZZ_S, AArch64_INS_TRN1: trn1 */ + 0, + {0}}, + + {/* AArch64_TRN1v16i8, AArch64_INS_TRN1: trn1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN1v2i32, AArch64_INS_TRN1: trn1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN1v2i64, AArch64_INS_TRN1: trn1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN1v4i16, AArch64_INS_TRN1: trn1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN1v4i32, AArch64_INS_TRN1: trn1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN1v8i16, AArch64_INS_TRN1: trn1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN1v8i8, AArch64_INS_TRN1: trn1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN2_PPP_B, AArch64_INS_TRN2: trn2 */ + 0, + {0}}, + + {/* AArch64_TRN2_PPP_D, AArch64_INS_TRN2: trn2 */ + 0, + {0}}, + + {/* AArch64_TRN2_PPP_H, AArch64_INS_TRN2: trn2 */ + 0, + {0}}, + + {/* AArch64_TRN2_PPP_S, AArch64_INS_TRN2: trn2 */ + 0, + {0}}, + + {/* AArch64_TRN2_ZZZ_B, AArch64_INS_TRN2: trn2 */ + 0, + {0}}, + + {/* AArch64_TRN2_ZZZ_D, AArch64_INS_TRN2: trn2 */ + 0, + {0}}, + + {/* AArch64_TRN2_ZZZ_H, AArch64_INS_TRN2: trn2 */ + 0, + {0}}, + + {/* AArch64_TRN2_ZZZ_S, AArch64_INS_TRN2: trn2 */ + 0, + {0}}, + + {/* AArch64_TRN2v16i8, AArch64_INS_TRN2: trn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN2v2i32, AArch64_INS_TRN2: trn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN2v2i64, AArch64_INS_TRN2: trn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN2v4i16, AArch64_INS_TRN2: trn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN2v4i32, AArch64_INS_TRN2: trn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN2v8i16, AArch64_INS_TRN2: trn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TRN2v8i8, AArch64_INS_TRN2: trn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_TSB, AArch64_INS_TSB: tsb */ + 0, + {0}}, + + {/* AArch64_UABALv16i8_v8i16, AArch64_INS_UABAL2: uabal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABALv2i32_v2i64, AArch64_INS_UABAL: uabal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABALv4i16_v4i32, AArch64_INS_UABAL: uabal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABALv4i32_v2i64, AArch64_INS_UABAL2: uabal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABALv8i16_v4i32, AArch64_INS_UABAL2: uabal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABALv8i8_v8i16, AArch64_INS_UABAL: uabal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABAv16i8, AArch64_INS_UABA: uaba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABAv2i32, AArch64_INS_UABA: uaba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABAv4i16, AArch64_INS_UABA: uaba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABAv4i32, AArch64_INS_UABA: uaba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABAv8i16, AArch64_INS_UABA: uaba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABAv8i8, AArch64_INS_UABA: uaba */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDLv16i8_v8i16, AArch64_INS_UABDL2: uabdl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDLv2i32_v2i64, AArch64_INS_UABDL: uabdl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDLv4i16_v4i32, AArch64_INS_UABDL: uabdl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDLv4i32_v2i64, AArch64_INS_UABDL2: uabdl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDLv8i16_v4i32, AArch64_INS_UABDL2: uabdl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDLv8i8_v8i16, AArch64_INS_UABDL: uabdl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABD_ZPmZ_B, AArch64_INS_UABD: uabd */ + 0, + {0}}, + + {/* AArch64_UABD_ZPmZ_D, AArch64_INS_UABD: uabd */ + 0, + {0}}, + + {/* AArch64_UABD_ZPmZ_H, AArch64_INS_UABD: uabd */ + 0, + {0}}, + + {/* AArch64_UABD_ZPmZ_S, AArch64_INS_UABD: uabd */ + 0, + {0}}, + + {/* AArch64_UABDv16i8, AArch64_INS_UABD: uabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDv2i32, AArch64_INS_UABD: uabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDv4i16, AArch64_INS_UABD: uabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDv4i32, AArch64_INS_UABD: uabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDv8i16, AArch64_INS_UABD: uabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UABDv8i8, AArch64_INS_UABD: uabd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADALPv16i8_v8i16, AArch64_INS_UADALP: uadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADALPv2i32_v1i64, AArch64_INS_UADALP: uadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADALPv4i16_v2i32, AArch64_INS_UADALP: uadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADALPv4i32_v2i64, AArch64_INS_UADALP: uadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADALPv8i16_v4i32, AArch64_INS_UADALP: uadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADALPv8i8_v4i16, AArch64_INS_UADALP: uadalp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLPv16i8_v8i16, AArch64_INS_UADDLP: uaddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLPv2i32_v1i64, AArch64_INS_UADDLP: uaddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLPv4i16_v2i32, AArch64_INS_UADDLP: uaddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLPv4i32_v2i64, AArch64_INS_UADDLP: uaddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLPv8i16_v4i32, AArch64_INS_UADDLP: uaddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLPv8i8_v4i16, AArch64_INS_UADDLP: uaddlp */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLVv16i8v, AArch64_INS_UADDLV: uaddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UADDLVv4i16v, AArch64_INS_UADDLV: uaddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UADDLVv4i32v, AArch64_INS_UADDLV: uaddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UADDLVv8i16v, AArch64_INS_UADDLV: uaddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UADDLVv8i8v, AArch64_INS_UADDLV: uaddlv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UADDLv16i8_v8i16, AArch64_INS_UADDL2: uaddl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLv2i32_v2i64, AArch64_INS_UADDL: uaddl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLv4i16_v4i32, AArch64_INS_UADDL: uaddl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLv4i32_v2i64, AArch64_INS_UADDL2: uaddl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLv8i16_v4i32, AArch64_INS_UADDL2: uaddl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDLv8i8_v8i16, AArch64_INS_UADDL: uaddl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDV_VPZ_B, AArch64_INS_UADDV: uaddv */ + 0, + {0}}, + + {/* AArch64_UADDV_VPZ_D, AArch64_INS_UADDV: uaddv */ + 0, + {0}}, + + {/* AArch64_UADDV_VPZ_H, AArch64_INS_UADDV: uaddv */ + 0, + {0}}, + + {/* AArch64_UADDV_VPZ_S, AArch64_INS_UADDV: uaddv */ + 0, + {0}}, + + {/* AArch64_UADDWv16i8_v8i16, AArch64_INS_UADDW2: uaddw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDWv2i32_v2i64, AArch64_INS_UADDW: uaddw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDWv4i16_v4i32, AArch64_INS_UADDW: uaddw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDWv4i32_v2i64, AArch64_INS_UADDW2: uaddw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDWv8i16_v4i32, AArch64_INS_UADDW2: uaddw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UADDWv8i8_v8i16, AArch64_INS_UADDW: uaddw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UBFMWri, AArch64_INS_LSR: lsr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UBFMXri, AArch64_INS_LSR: lsr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFSWDri, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFSWHri, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFSWSri, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFSXDri, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFSXHri, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFSXSri, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFUWDri, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFUWHri, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFUWSri, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFUXDri, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFUXHri, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFUXSri, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UCVTF_ZPmZ_DtoD, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTF_ZPmZ_DtoH, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTF_ZPmZ_DtoS, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTF_ZPmZ_HtoH, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTF_ZPmZ_StoD, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTF_ZPmZ_StoH, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTF_ZPmZ_StoS, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFd, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFh, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFs, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFv1i16, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFv1i32, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFv1i64, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFv2f32, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFv2f64, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFv2i32_shift, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFv2i64_shift, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFv4f16, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFv4f32, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFv4i16_shift, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFv4i32_shift, AArch64_INS_UCVTF: ucvtf */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UCVTFv8f16, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UCVTFv8i16_shift, AArch64_INS_UCVTF: ucvtf */ + 0, + {0}}, + + {/* AArch64_UDIVR_ZPmZ_D, AArch64_INS_UDIVR: udivr */ + 0, + {0}}, + + {/* AArch64_UDIVR_ZPmZ_S, AArch64_INS_UDIVR: udivr */ + 0, + {0}}, + + {/* AArch64_UDIVWr, AArch64_INS_UDIV: udiv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UDIVXr, AArch64_INS_UDIV: udiv */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UDIV_ZPmZ_D, AArch64_INS_UDIV: udiv */ + 0, + {0}}, + + {/* AArch64_UDIV_ZPmZ_S, AArch64_INS_UDIV: udiv */ + 0, + {0}}, + + {/* AArch64_UDOT_ZZZI_D, AArch64_INS_UDOT: udot */ + 0, + {0}}, + + {/* AArch64_UDOT_ZZZI_S, AArch64_INS_UDOT: udot */ + 0, + {0}}, + + {/* AArch64_UDOT_ZZZ_D, AArch64_INS_UDOT: udot */ + 0, + {0}}, + + {/* AArch64_UDOT_ZZZ_S, AArch64_INS_UDOT: udot */ + 0, + {0}}, + + {/* AArch64_UDOTlanev16i8, AArch64_INS_UDOT: udot */ + 0, + {0}}, + + {/* AArch64_UDOTlanev8i8, AArch64_INS_UDOT: udot */ + 0, + {0}}, + + {/* AArch64_UDOTv16i8, AArch64_INS_UDOT: udot */ + 0, + {0}}, + + {/* AArch64_UDOTv8i8, AArch64_INS_UDOT: udot */ + 0, + {0}}, + + {/* AArch64_UHADDv16i8, AArch64_INS_UHADD: uhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHADDv2i32, AArch64_INS_UHADD: uhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHADDv4i16, AArch64_INS_UHADD: uhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHADDv4i32, AArch64_INS_UHADD: uhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHADDv8i16, AArch64_INS_UHADD: uhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHADDv8i8, AArch64_INS_UHADD: uhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHSUBv16i8, AArch64_INS_UHSUB: uhsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHSUBv2i32, AArch64_INS_UHSUB: uhsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHSUBv4i16, AArch64_INS_UHSUB: uhsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHSUBv4i32, AArch64_INS_UHSUB: uhsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHSUBv8i16, AArch64_INS_UHSUB: uhsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UHSUBv8i8, AArch64_INS_UHSUB: uhsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMADDLrrr, AArch64_INS_UMADDL: umaddl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXPv16i8, AArch64_INS_UMAXP: umaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXPv2i32, AArch64_INS_UMAXP: umaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXPv4i16, AArch64_INS_UMAXP: umaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXPv4i32, AArch64_INS_UMAXP: umaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXPv8i16, AArch64_INS_UMAXP: umaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXPv8i8, AArch64_INS_UMAXP: umaxp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXV_VPZ_B, AArch64_INS_UMAXV: umaxv */ + 0, + {0}}, + + {/* AArch64_UMAXV_VPZ_D, AArch64_INS_UMAXV: umaxv */ + 0, + {0}}, + + {/* AArch64_UMAXV_VPZ_H, AArch64_INS_UMAXV: umaxv */ + 0, + {0}}, + + {/* AArch64_UMAXV_VPZ_S, AArch64_INS_UMAXV: umaxv */ + 0, + {0}}, + + {/* AArch64_UMAXVv16i8v, AArch64_INS_UMAXV: umaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMAXVv4i16v, AArch64_INS_UMAXV: umaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMAXVv4i32v, AArch64_INS_UMAXV: umaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMAXVv8i16v, AArch64_INS_UMAXV: umaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMAXVv8i8v, AArch64_INS_UMAXV: umaxv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMAX_ZI_B, AArch64_INS_UMAX: umax */ + 0, + {0}}, + + {/* AArch64_UMAX_ZI_D, AArch64_INS_UMAX: umax */ + 0, + {0}}, + + {/* AArch64_UMAX_ZI_H, AArch64_INS_UMAX: umax */ + 0, + {0}}, + + {/* AArch64_UMAX_ZI_S, AArch64_INS_UMAX: umax */ + 0, + {0}}, + + {/* AArch64_UMAX_ZPmZ_B, AArch64_INS_UMAX: umax */ + 0, + {0}}, + + {/* AArch64_UMAX_ZPmZ_D, AArch64_INS_UMAX: umax */ + 0, + {0}}, + + {/* AArch64_UMAX_ZPmZ_H, AArch64_INS_UMAX: umax */ + 0, + {0}}, + + {/* AArch64_UMAX_ZPmZ_S, AArch64_INS_UMAX: umax */ + 0, + {0}}, + + {/* AArch64_UMAXv16i8, AArch64_INS_UMAX: umax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXv2i32, AArch64_INS_UMAX: umax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXv4i16, AArch64_INS_UMAX: umax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXv4i32, AArch64_INS_UMAX: umax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXv8i16, AArch64_INS_UMAX: umax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMAXv8i8, AArch64_INS_UMAX: umax */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINPv16i8, AArch64_INS_UMINP: uminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINPv2i32, AArch64_INS_UMINP: uminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINPv4i16, AArch64_INS_UMINP: uminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINPv4i32, AArch64_INS_UMINP: uminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINPv8i16, AArch64_INS_UMINP: uminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINPv8i8, AArch64_INS_UMINP: uminp */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINV_VPZ_B, AArch64_INS_UMINV: uminv */ + 0, + {0}}, + + {/* AArch64_UMINV_VPZ_D, AArch64_INS_UMINV: uminv */ + 0, + {0}}, + + {/* AArch64_UMINV_VPZ_H, AArch64_INS_UMINV: uminv */ + 0, + {0}}, + + {/* AArch64_UMINV_VPZ_S, AArch64_INS_UMINV: uminv */ + 0, + {0}}, + + {/* AArch64_UMINVv16i8v, AArch64_INS_UMINV: uminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMINVv4i16v, AArch64_INS_UMINV: uminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMINVv4i32v, AArch64_INS_UMINV: uminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMINVv8i16v, AArch64_INS_UMINV: uminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMINVv8i8v, AArch64_INS_UMINV: uminv */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UMIN_ZI_B, AArch64_INS_UMIN: umin */ + 0, + {0}}, + + {/* AArch64_UMIN_ZI_D, AArch64_INS_UMIN: umin */ + 0, + {0}}, + + {/* AArch64_UMIN_ZI_H, AArch64_INS_UMIN: umin */ + 0, + {0}}, + + {/* AArch64_UMIN_ZI_S, AArch64_INS_UMIN: umin */ + 0, + {0}}, + + {/* AArch64_UMIN_ZPmZ_B, AArch64_INS_UMIN: umin */ + 0, + {0}}, + + {/* AArch64_UMIN_ZPmZ_D, AArch64_INS_UMIN: umin */ + 0, + {0}}, + + {/* AArch64_UMIN_ZPmZ_H, AArch64_INS_UMIN: umin */ + 0, + {0}}, + + {/* AArch64_UMIN_ZPmZ_S, AArch64_INS_UMIN: umin */ + 0, + {0}}, + + {/* AArch64_UMINv16i8, AArch64_INS_UMIN: umin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINv2i32, AArch64_INS_UMIN: umin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINv4i16, AArch64_INS_UMIN: umin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINv4i32, AArch64_INS_UMIN: umin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINv8i16, AArch64_INS_UMIN: umin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMINv8i8, AArch64_INS_UMIN: umin */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv16i8_v8i16, AArch64_INS_UMLAL2: umlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv2i32_indexed, AArch64_INS_UMLAL: umlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv2i32_v2i64, AArch64_INS_UMLAL: umlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv4i16_indexed, AArch64_INS_UMLAL: umlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv4i16_v4i32, AArch64_INS_UMLAL: umlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv4i32_indexed, AArch64_INS_UMLAL2: umlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv4i32_v2i64, AArch64_INS_UMLAL2: umlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv8i16_indexed, AArch64_INS_UMLAL2: umlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv8i16_v4i32, AArch64_INS_UMLAL2: umlal2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLALv8i8_v8i16, AArch64_INS_UMLAL: umlal */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv16i8_v8i16, AArch64_INS_UMLSL2: umlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv2i32_indexed, AArch64_INS_UMLSL: umlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv2i32_v2i64, AArch64_INS_UMLSL: umlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv4i16_indexed, AArch64_INS_UMLSL: umlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv4i16_v4i32, AArch64_INS_UMLSL: umlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv4i32_indexed, AArch64_INS_UMLSL2: umlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv4i32_v2i64, AArch64_INS_UMLSL2: umlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv8i16_indexed, AArch64_INS_UMLSL2: umlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv8i16_v4i32, AArch64_INS_UMLSL2: umlsl2 */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMLSLv8i8_v8i16, AArch64_INS_UMLSL: umlsl */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMOVvi16, AArch64_INS_UMOV: umov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMOVvi32, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMOVvi64, AArch64_INS_MOV: mov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMOVvi8, AArch64_INS_UMOV: umov */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMSUBLrrr, AArch64_INS_UMNEGL: umnegl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULH_ZPmZ_B, AArch64_INS_UMULH: umulh */ + 0, + {0}}, + + {/* AArch64_UMULH_ZPmZ_D, AArch64_INS_UMULH: umulh */ + 0, + {0}}, + + {/* AArch64_UMULH_ZPmZ_H, AArch64_INS_UMULH: umulh */ + 0, + {0}}, + + {/* AArch64_UMULH_ZPmZ_S, AArch64_INS_UMULH: umulh */ + 0, + {0}}, + + {/* AArch64_UMULHrr, AArch64_INS_UMULH: umulh */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv16i8_v8i16, AArch64_INS_UMULL2: umull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv2i32_indexed, AArch64_INS_UMULL: umull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv2i32_v2i64, AArch64_INS_UMULL: umull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv4i16_indexed, AArch64_INS_UMULL: umull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv4i16_v4i32, AArch64_INS_UMULL: umull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv4i32_indexed, AArch64_INS_UMULL2: umull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv4i32_v2i64, AArch64_INS_UMULL2: umull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv8i16_indexed, AArch64_INS_UMULL2: umull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv8i16_v4i32, AArch64_INS_UMULL2: umull2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UMULLv8i8_v8i16, AArch64_INS_UMULL: umull */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADD_ZI_B, AArch64_INS_UQADD: uqadd */ + 0, + {0}}, + + {/* AArch64_UQADD_ZI_D, AArch64_INS_UQADD: uqadd */ + 0, + {0}}, + + {/* AArch64_UQADD_ZI_H, AArch64_INS_UQADD: uqadd */ + 0, + {0}}, + + {/* AArch64_UQADD_ZI_S, AArch64_INS_UQADD: uqadd */ + 0, + {0}}, + + {/* AArch64_UQADD_ZZZ_B, AArch64_INS_UQADD: uqadd */ + 0, + {0}}, + + {/* AArch64_UQADD_ZZZ_D, AArch64_INS_UQADD: uqadd */ + 0, + {0}}, + + {/* AArch64_UQADD_ZZZ_H, AArch64_INS_UQADD: uqadd */ + 0, + {0}}, + + {/* AArch64_UQADD_ZZZ_S, AArch64_INS_UQADD: uqadd */ + 0, + {0}}, + + {/* AArch64_UQADDv16i8, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv1i16, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv1i32, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv1i64, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv1i8, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv2i32, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv2i64, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv4i16, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv4i32, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv8i16, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQADDv8i8, AArch64_INS_UQADD: uqadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQDECB_WPiI, AArch64_INS_UQDECB: uqdecb */ + 0, + {0}}, + + {/* AArch64_UQDECB_XPiI, AArch64_INS_UQDECB: uqdecb */ + 0, + {0}}, + + {/* AArch64_UQDECD_WPiI, AArch64_INS_UQDECD: uqdecd */ + 0, + {0}}, + + {/* AArch64_UQDECD_XPiI, AArch64_INS_UQDECD: uqdecd */ + 0, + {0}}, + + {/* AArch64_UQDECD_ZPiI, AArch64_INS_UQDECD: uqdecd */ + 0, + {0}}, + + {/* AArch64_UQDECH_WPiI, AArch64_INS_UQDECH: uqdech */ + 0, + {0}}, + + {/* AArch64_UQDECH_XPiI, AArch64_INS_UQDECH: uqdech */ + 0, + {0}}, + + {/* AArch64_UQDECH_ZPiI, AArch64_INS_UQDECH: uqdech */ + 0, + {0}}, + + {/* AArch64_UQDECP_WP_B, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_WP_D, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_WP_H, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_WP_S, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_XP_B, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_XP_D, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_XP_H, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_XP_S, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_ZP_D, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_ZP_H, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECP_ZP_S, AArch64_INS_UQDECP: uqdecp */ + 0, + {0}}, + + {/* AArch64_UQDECW_WPiI, AArch64_INS_UQDECW: uqdecw */ + 0, + {0}}, + + {/* AArch64_UQDECW_XPiI, AArch64_INS_UQDECW: uqdecw */ + 0, + {0}}, + + {/* AArch64_UQDECW_ZPiI, AArch64_INS_UQDECW: uqdecw */ + 0, + {0}}, + + {/* AArch64_UQINCB_WPiI, AArch64_INS_UQINCB: uqincb */ + 0, + {0}}, + + {/* AArch64_UQINCB_XPiI, AArch64_INS_UQINCB: uqincb */ + 0, + {0}}, + + {/* AArch64_UQINCD_WPiI, AArch64_INS_UQINCD: uqincd */ + 0, + {0}}, + + {/* AArch64_UQINCD_XPiI, AArch64_INS_UQINCD: uqincd */ + 0, + {0}}, + + {/* AArch64_UQINCD_ZPiI, AArch64_INS_UQINCD: uqincd */ + 0, + {0}}, + + {/* AArch64_UQINCH_WPiI, AArch64_INS_UQINCH: uqinch */ + 0, + {0}}, + + {/* AArch64_UQINCH_XPiI, AArch64_INS_UQINCH: uqinch */ + 0, + {0}}, + + {/* AArch64_UQINCH_ZPiI, AArch64_INS_UQINCH: uqinch */ + 0, + {0}}, + + {/* AArch64_UQINCP_WP_B, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_WP_D, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_WP_H, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_WP_S, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_XP_B, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_XP_D, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_XP_H, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_XP_S, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_ZP_D, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_ZP_H, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCP_ZP_S, AArch64_INS_UQINCP: uqincp */ + 0, + {0}}, + + {/* AArch64_UQINCW_WPiI, AArch64_INS_UQINCW: uqincw */ + 0, + {0}}, + + {/* AArch64_UQINCW_XPiI, AArch64_INS_UQINCW: uqincw */ + 0, + {0}}, + + {/* AArch64_UQINCW_ZPiI, AArch64_INS_UQINCW: uqincw */ + 0, + {0}}, + + {/* AArch64_UQRSHLv16i8, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv1i16, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv1i32, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv1i64, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv1i8, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv2i32, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv2i64, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv4i16, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv4i32, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv8i16, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHLv8i8, AArch64_INS_UQRSHL: uqrshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHRNb, AArch64_INS_UQRSHRN: uqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHRNh, AArch64_INS_UQRSHRN: uqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHRNs, AArch64_INS_UQRSHRN: uqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHRNv16i8_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHRNv2i32_shift, AArch64_INS_UQRSHRN: uqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHRNv4i16_shift, AArch64_INS_UQRSHRN: uqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHRNv4i32_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHRNv8i16_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQRSHRNv8i8_shift, AArch64_INS_UQRSHRN: uqrshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLb, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLd, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLh, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLs, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv16i8, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv16i8_shift, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv1i16, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv1i32, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv1i64, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv1i8, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv2i32, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv2i32_shift, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv2i64, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv2i64_shift, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv4i16, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv4i16_shift, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv4i32, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv4i32_shift, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv8i16, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv8i16_shift, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv8i8, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHLv8i8_shift, AArch64_INS_UQSHL: uqshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHRNb, AArch64_INS_UQSHRN: uqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHRNh, AArch64_INS_UQSHRN: uqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHRNs, AArch64_INS_UQSHRN: uqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHRNv16i8_shift, AArch64_INS_UQSHRN2: uqshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHRNv2i32_shift, AArch64_INS_UQSHRN: uqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHRNv4i16_shift, AArch64_INS_UQSHRN: uqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHRNv4i32_shift, AArch64_INS_UQSHRN2: uqshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHRNv8i16_shift, AArch64_INS_UQSHRN2: uqshrn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSHRNv8i8_shift, AArch64_INS_UQSHRN: uqshrn */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUB_ZI_B, AArch64_INS_UQSUB: uqsub */ + 0, + {0}}, + + {/* AArch64_UQSUB_ZI_D, AArch64_INS_UQSUB: uqsub */ + 0, + {0}}, + + {/* AArch64_UQSUB_ZI_H, AArch64_INS_UQSUB: uqsub */ + 0, + {0}}, + + {/* AArch64_UQSUB_ZI_S, AArch64_INS_UQSUB: uqsub */ + 0, + {0}}, + + {/* AArch64_UQSUB_ZZZ_B, AArch64_INS_UQSUB: uqsub */ + 0, + {0}}, + + {/* AArch64_UQSUB_ZZZ_D, AArch64_INS_UQSUB: uqsub */ + 0, + {0}}, + + {/* AArch64_UQSUB_ZZZ_H, AArch64_INS_UQSUB: uqsub */ + 0, + {0}}, + + {/* AArch64_UQSUB_ZZZ_S, AArch64_INS_UQSUB: uqsub */ + 0, + {0}}, + + {/* AArch64_UQSUBv16i8, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv1i16, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv1i32, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv1i64, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv1i8, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv2i32, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv2i64, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv4i16, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv4i32, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv8i16, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQSUBv8i8, AArch64_INS_UQSUB: uqsub */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UQXTNv16i8, AArch64_INS_UQXTN2: uqxtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UQXTNv1i16, AArch64_INS_UQXTN: uqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UQXTNv1i32, AArch64_INS_UQXTN: uqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UQXTNv1i8, AArch64_INS_UQXTN: uqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UQXTNv2i32, AArch64_INS_UQXTN: uqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UQXTNv4i16, AArch64_INS_UQXTN: uqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UQXTNv4i32, AArch64_INS_UQXTN2: uqxtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UQXTNv8i16, AArch64_INS_UQXTN2: uqxtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_UQXTNv8i8, AArch64_INS_UQXTN: uqxtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_URECPEv2i32, AArch64_INS_URECPE: urecpe */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_URECPEv4i32, AArch64_INS_URECPE: urecpe */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_URHADDv16i8, AArch64_INS_URHADD: urhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URHADDv2i32, AArch64_INS_URHADD: urhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URHADDv4i16, AArch64_INS_URHADD: urhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URHADDv4i32, AArch64_INS_URHADD: urhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URHADDv8i16, AArch64_INS_URHADD: urhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URHADDv8i8, AArch64_INS_URHADD: urhadd */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHLv16i8, AArch64_INS_URSHL: urshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHLv1i64, AArch64_INS_URSHL: urshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHLv2i32, AArch64_INS_URSHL: urshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHLv2i64, AArch64_INS_URSHL: urshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHLv4i16, AArch64_INS_URSHL: urshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHLv4i32, AArch64_INS_URSHL: urshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHLv8i16, AArch64_INS_URSHL: urshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHLv8i8, AArch64_INS_URSHL: urshl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHRd, AArch64_INS_URSHR: urshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHRv16i8_shift, AArch64_INS_URSHR: urshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHRv2i32_shift, AArch64_INS_URSHR: urshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHRv2i64_shift, AArch64_INS_URSHR: urshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHRv4i16_shift, AArch64_INS_URSHR: urshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHRv4i32_shift, AArch64_INS_URSHR: urshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHRv8i16_shift, AArch64_INS_URSHR: urshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSHRv8i8_shift, AArch64_INS_URSHR: urshr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSQRTEv2i32, AArch64_INS_URSQRTE: ursqrte */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_URSQRTEv4i32, AArch64_INS_URSQRTE: ursqrte */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_URSRAd, AArch64_INS_URSRA: ursra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSRAv16i8_shift, AArch64_INS_URSRA: ursra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSRAv2i32_shift, AArch64_INS_URSRA: ursra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSRAv2i64_shift, AArch64_INS_URSRA: ursra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSRAv4i16_shift, AArch64_INS_URSRA: ursra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSRAv4i32_shift, AArch64_INS_URSRA: ursra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSRAv8i16_shift, AArch64_INS_URSRA: ursra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_URSRAv8i8_shift, AArch64_INS_URSRA: ursra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLLv16i8_shift, AArch64_INS_USHLL2: ushll2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLLv2i32_shift, AArch64_INS_USHLL: ushll */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLLv4i16_shift, AArch64_INS_USHLL: ushll */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLLv4i32_shift, AArch64_INS_USHLL2: ushll2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLLv8i16_shift, AArch64_INS_USHLL2: ushll2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLLv8i8_shift, AArch64_INS_USHLL: ushll */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLv16i8, AArch64_INS_USHL: ushl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLv1i64, AArch64_INS_USHL: ushl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLv2i32, AArch64_INS_USHL: ushl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLv2i64, AArch64_INS_USHL: ushl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLv4i16, AArch64_INS_USHL: ushl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLv4i32, AArch64_INS_USHL: ushl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLv8i16, AArch64_INS_USHL: ushl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHLv8i8, AArch64_INS_USHL: ushl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHRd, AArch64_INS_USHR: ushr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHRv16i8_shift, AArch64_INS_USHR: ushr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHRv2i32_shift, AArch64_INS_USHR: ushr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHRv2i64_shift, AArch64_INS_USHR: ushr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHRv4i16_shift, AArch64_INS_USHR: ushr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHRv4i32_shift, AArch64_INS_USHR: ushr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHRv8i16_shift, AArch64_INS_USHR: ushr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USHRv8i8_shift, AArch64_INS_USHR: ushr */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv16i8, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv1i16, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv1i32, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv1i64, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv1i8, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv2i32, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv2i64, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv4i16, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv4i32, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv8i16, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USQADDv8i8, AArch64_INS_USQADD: usqadd */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USRAd, AArch64_INS_USRA: usra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USRAv16i8_shift, AArch64_INS_USRA: usra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USRAv2i32_shift, AArch64_INS_USRA: usra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USRAv2i64_shift, AArch64_INS_USRA: usra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USRAv4i16_shift, AArch64_INS_USRA: usra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USRAv4i32_shift, AArch64_INS_USRA: usra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USRAv8i16_shift, AArch64_INS_USRA: usra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USRAv8i8_shift, AArch64_INS_USRA: usra */ + 0, + {CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBLv16i8_v8i16, AArch64_INS_USUBL2: usubl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBLv2i32_v2i64, AArch64_INS_USUBL: usubl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBLv4i16_v4i32, AArch64_INS_USUBL: usubl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBLv4i32_v2i64, AArch64_INS_USUBL2: usubl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBLv8i16_v4i32, AArch64_INS_USUBL2: usubl2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBLv8i8_v8i16, AArch64_INS_USUBL: usubl */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBWv16i8_v8i16, AArch64_INS_USUBW2: usubw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBWv2i32_v2i64, AArch64_INS_USUBW: usubw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBWv4i16_v4i32, AArch64_INS_USUBW: usubw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBWv4i32_v2i64, AArch64_INS_USUBW2: usubw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBWv8i16_v4i32, AArch64_INS_USUBW2: usubw2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_USUBWv8i8_v8i16, AArch64_INS_USUBW: usubw */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UUNPKHI_ZZ_D, AArch64_INS_UUNPKHI: uunpkhi */ + 0, + {0}}, + + {/* AArch64_UUNPKHI_ZZ_H, AArch64_INS_UUNPKHI: uunpkhi */ + 0, + {0}}, + + {/* AArch64_UUNPKHI_ZZ_S, AArch64_INS_UUNPKHI: uunpkhi */ + 0, + {0}}, + + {/* AArch64_UUNPKLO_ZZ_D, AArch64_INS_UUNPKLO: uunpklo */ + 0, + {0}}, + + {/* AArch64_UUNPKLO_ZZ_H, AArch64_INS_UUNPKLO: uunpklo */ + 0, + {0}}, + + {/* AArch64_UUNPKLO_ZZ_S, AArch64_INS_UUNPKLO: uunpklo */ + 0, + {0}}, + + {/* AArch64_UXTB_ZPmZ_D, AArch64_INS_UXTB: uxtb */ + 0, + {0}}, + + {/* AArch64_UXTB_ZPmZ_H, AArch64_INS_UXTB: uxtb */ + 0, + {0}}, + + {/* AArch64_UXTB_ZPmZ_S, AArch64_INS_UXTB: uxtb */ + 0, + {0}}, + + {/* AArch64_UXTH_ZPmZ_D, AArch64_INS_UXTH: uxth */ + 0, + {0}}, + + {/* AArch64_UXTH_ZPmZ_S, AArch64_INS_UXTH: uxth */ + 0, + {0}}, + + {/* AArch64_UXTW_ZPmZ_D, AArch64_INS_UXTW: uxtw */ + 0, + {0}}, + + {/* AArch64_UZP1_PPP_B, AArch64_INS_UZP1: uzp1 */ + 0, + {0}}, + + {/* AArch64_UZP1_PPP_D, AArch64_INS_UZP1: uzp1 */ + 0, + {0}}, + + {/* AArch64_UZP1_PPP_H, AArch64_INS_UZP1: uzp1 */ + 0, + {0}}, + + {/* AArch64_UZP1_PPP_S, AArch64_INS_UZP1: uzp1 */ + 0, + {0}}, + + {/* AArch64_UZP1_ZZZ_B, AArch64_INS_UZP1: uzp1 */ + 0, + {0}}, + + {/* AArch64_UZP1_ZZZ_D, AArch64_INS_UZP1: uzp1 */ + 0, + {0}}, + + {/* AArch64_UZP1_ZZZ_H, AArch64_INS_UZP1: uzp1 */ + 0, + {0}}, + + {/* AArch64_UZP1_ZZZ_S, AArch64_INS_UZP1: uzp1 */ + 0, + {0}}, + + {/* AArch64_UZP1v16i8, AArch64_INS_UZP1: uzp1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP1v2i32, AArch64_INS_UZP1: uzp1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP1v2i64, AArch64_INS_UZP1: uzp1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP1v4i16, AArch64_INS_UZP1: uzp1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP1v4i32, AArch64_INS_UZP1: uzp1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP1v8i16, AArch64_INS_UZP1: uzp1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP1v8i8, AArch64_INS_UZP1: uzp1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP2_PPP_B, AArch64_INS_UZP2: uzp2 */ + 0, + {0}}, + + {/* AArch64_UZP2_PPP_D, AArch64_INS_UZP2: uzp2 */ + 0, + {0}}, + + {/* AArch64_UZP2_PPP_H, AArch64_INS_UZP2: uzp2 */ + 0, + {0}}, + + {/* AArch64_UZP2_PPP_S, AArch64_INS_UZP2: uzp2 */ + 0, + {0}}, + + {/* AArch64_UZP2_ZZZ_B, AArch64_INS_UZP2: uzp2 */ + 0, + {0}}, + + {/* AArch64_UZP2_ZZZ_D, AArch64_INS_UZP2: uzp2 */ + 0, + {0}}, + + {/* AArch64_UZP2_ZZZ_H, AArch64_INS_UZP2: uzp2 */ + 0, + {0}}, + + {/* AArch64_UZP2_ZZZ_S, AArch64_INS_UZP2: uzp2 */ + 0, + {0}}, + + {/* AArch64_UZP2v16i8, AArch64_INS_UZP2: uzp2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP2v2i32, AArch64_INS_UZP2: uzp2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP2v2i64, AArch64_INS_UZP2: uzp2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP2v4i16, AArch64_INS_UZP2: uzp2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP2v4i32, AArch64_INS_UZP2: uzp2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP2v8i16, AArch64_INS_UZP2: uzp2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_UZP2v8i8, AArch64_INS_UZP2: uzp2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_WHILELE_PWW_B, AArch64_INS_WHILELE: whilele */ + 0, + {0}}, + + {/* AArch64_WHILELE_PWW_D, AArch64_INS_WHILELE: whilele */ + 0, + {0}}, + + {/* AArch64_WHILELE_PWW_H, AArch64_INS_WHILELE: whilele */ + 0, + {0}}, + + {/* AArch64_WHILELE_PWW_S, AArch64_INS_WHILELE: whilele */ + 0, + {0}}, + + {/* AArch64_WHILELE_PXX_B, AArch64_INS_WHILELE: whilele */ + 0, + {0}}, + + {/* AArch64_WHILELE_PXX_D, AArch64_INS_WHILELE: whilele */ + 0, + {0}}, + + {/* AArch64_WHILELE_PXX_H, AArch64_INS_WHILELE: whilele */ + 0, + {0}}, + + {/* AArch64_WHILELE_PXX_S, AArch64_INS_WHILELE: whilele */ + 0, + {0}}, + + {/* AArch64_WHILELO_PWW_B, AArch64_INS_WHILELO: whilelo */ + 0, + {0}}, + + {/* AArch64_WHILELO_PWW_D, AArch64_INS_WHILELO: whilelo */ + 0, + {0}}, + + {/* AArch64_WHILELO_PWW_H, AArch64_INS_WHILELO: whilelo */ + 0, + {0}}, + + {/* AArch64_WHILELO_PWW_S, AArch64_INS_WHILELO: whilelo */ + 0, + {0}}, + + {/* AArch64_WHILELO_PXX_B, AArch64_INS_WHILELO: whilelo */ + 0, + {0}}, + + {/* AArch64_WHILELO_PXX_D, AArch64_INS_WHILELO: whilelo */ + 0, + {0}}, + + {/* AArch64_WHILELO_PXX_H, AArch64_INS_WHILELO: whilelo */ + 0, + {0}}, + + {/* AArch64_WHILELO_PXX_S, AArch64_INS_WHILELO: whilelo */ + 0, + {0}}, + + {/* AArch64_WHILELS_PWW_B, AArch64_INS_WHILELS: whilels */ + 0, + {0}}, + + {/* AArch64_WHILELS_PWW_D, AArch64_INS_WHILELS: whilels */ + 0, + {0}}, + + {/* AArch64_WHILELS_PWW_H, AArch64_INS_WHILELS: whilels */ + 0, + {0}}, + + {/* AArch64_WHILELS_PWW_S, AArch64_INS_WHILELS: whilels */ + 0, + {0}}, + + {/* AArch64_WHILELS_PXX_B, AArch64_INS_WHILELS: whilels */ + 0, + {0}}, + + {/* AArch64_WHILELS_PXX_D, AArch64_INS_WHILELS: whilels */ + 0, + {0}}, + + {/* AArch64_WHILELS_PXX_H, AArch64_INS_WHILELS: whilels */ + 0, + {0}}, + + {/* AArch64_WHILELS_PXX_S, AArch64_INS_WHILELS: whilels */ + 0, + {0}}, + + {/* AArch64_WHILELT_PWW_B, AArch64_INS_WHILELT: whilelt */ + 0, + {0}}, + + {/* AArch64_WHILELT_PWW_D, AArch64_INS_WHILELT: whilelt */ + 0, + {0}}, + + {/* AArch64_WHILELT_PWW_H, AArch64_INS_WHILELT: whilelt */ + 0, + {0}}, + + {/* AArch64_WHILELT_PWW_S, AArch64_INS_WHILELT: whilelt */ + 0, + {0}}, + + {/* AArch64_WHILELT_PXX_B, AArch64_INS_WHILELT: whilelt */ + 0, + {0}}, + + {/* AArch64_WHILELT_PXX_D, AArch64_INS_WHILELT: whilelt */ + 0, + {0}}, + + {/* AArch64_WHILELT_PXX_H, AArch64_INS_WHILELT: whilelt */ + 0, + {0}}, + + {/* AArch64_WHILELT_PXX_S, AArch64_INS_WHILELT: whilelt */ + 0, + {0}}, + + {/* AArch64_WRFFR, AArch64_INS_WRFFR: wrffr */ + 0, + {0}}, + + {/* AArch64_XAR, AArch64_INS_XAR: xar */ + 0, + {0}}, + + {/* AArch64_XPACD, AArch64_INS_XPACD: xpacd */ + 0, + {0}}, + + {/* AArch64_XPACI, AArch64_INS_XPACI: xpaci */ + 0, + {0}}, + + {/* AArch64_XPACLRI, AArch64_INS_XPACLRI: xpaclri */ + 0, + {0}}, + + {/* AArch64_XTNv16i8, AArch64_INS_XTN2: xtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_XTNv2i32, AArch64_INS_XTN: xtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_XTNv4i16, AArch64_INS_XTN: xtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_XTNv4i32, AArch64_INS_XTN2: xtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_XTNv8i16, AArch64_INS_XTN2: xtn2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_XTNv8i8, AArch64_INS_XTN: xtn */ + 0, + {CS_AC_WRITE, CS_AC_READ, 0}}, + + {/* AArch64_ZIP1_PPP_B, AArch64_INS_ZIP1: zip1 */ + 0, + {0}}, + + {/* AArch64_ZIP1_PPP_D, AArch64_INS_ZIP1: zip1 */ + 0, + {0}}, + + {/* AArch64_ZIP1_PPP_H, AArch64_INS_ZIP1: zip1 */ + 0, + {0}}, + + {/* AArch64_ZIP1_PPP_S, AArch64_INS_ZIP1: zip1 */ + 0, + {0}}, + + {/* AArch64_ZIP1_ZZZ_B, AArch64_INS_ZIP1: zip1 */ + 0, + {0}}, + + {/* AArch64_ZIP1_ZZZ_D, AArch64_INS_ZIP1: zip1 */ + 0, + {0}}, + + {/* AArch64_ZIP1_ZZZ_H, AArch64_INS_ZIP1: zip1 */ + 0, + {0}}, + + {/* AArch64_ZIP1_ZZZ_S, AArch64_INS_ZIP1: zip1 */ + 0, + {0}}, + + {/* AArch64_ZIP1v16i8, AArch64_INS_ZIP1: zip1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP1v2i32, AArch64_INS_ZIP1: zip1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP1v2i64, AArch64_INS_ZIP1: zip1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP1v4i16, AArch64_INS_ZIP1: zip1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP1v4i32, AArch64_INS_ZIP1: zip1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP1v8i16, AArch64_INS_ZIP1: zip1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP1v8i8, AArch64_INS_ZIP1: zip1 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP2_PPP_B, AArch64_INS_ZIP2: zip2 */ + 0, + {0}}, + + {/* AArch64_ZIP2_PPP_D, AArch64_INS_ZIP2: zip2 */ + 0, + {0}}, + + {/* AArch64_ZIP2_PPP_H, AArch64_INS_ZIP2: zip2 */ + 0, + {0}}, + + {/* AArch64_ZIP2_PPP_S, AArch64_INS_ZIP2: zip2 */ + 0, + {0}}, + + {/* AArch64_ZIP2_ZZZ_B, AArch64_INS_ZIP2: zip2 */ + 0, + {0}}, + + {/* AArch64_ZIP2_ZZZ_D, AArch64_INS_ZIP2: zip2 */ + 0, + {0}}, + + {/* AArch64_ZIP2_ZZZ_H, AArch64_INS_ZIP2: zip2 */ + 0, + {0}}, + + {/* AArch64_ZIP2_ZZZ_S, AArch64_INS_ZIP2: zip2 */ + 0, + {0}}, + + {/* AArch64_ZIP2v16i8, AArch64_INS_ZIP2: zip2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP2v2i32, AArch64_INS_ZIP2: zip2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP2v2i64, AArch64_INS_ZIP2: zip2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP2v4i16, AArch64_INS_ZIP2: zip2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP2v4i32, AArch64_INS_ZIP2: zip2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP2v8i16, AArch64_INS_ZIP2: zip2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_ZIP2v8i8, AArch64_INS_ZIP2: zip2 */ + 0, + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, + + {/* AArch64_anonymous_1349, AArch64_INS_PFIRST: pfirst */ + 0, + {0}}, diff --git a/arch/AArch64/AArch64Module.c b/arch/AArch64/AArch64Module.c index 7fc5ddf40f..d5301006e5 100644 --- a/arch/AArch64/AArch64Module.c +++ b/arch/AArch64/AArch64Module.c @@ -3,42 +3,40 @@ #ifdef CAPSTONE_HAS_ARM64 -#include "../../utils.h" +#include "AArch64Module.h" #include "../../MCRegisterInfo.h" +#include "../../utils.h" #include "AArch64Disassembler.h" #include "AArch64InstPrinter.h" #include "AArch64Mapping.h" -#include "AArch64Module.h" -cs_err AArch64_global_init(cs_struct *ud) -{ - MCRegisterInfo *mri; - mri = cs_mem_malloc(sizeof(*mri)); - - AArch64_init(mri); - ud->printer = AArch64_printInst; - ud->printer_info = mri; - ud->getinsn_info = mri; - ud->disasm = AArch64_getInstruction; - ud->reg_name = AArch64_reg_name; - ud->insn_id = AArch64_get_insn_id; - ud->insn_name = AArch64_insn_name; - ud->group_name = AArch64_group_name; - ud->post_printer = AArch64_post_printer; +cs_err AArch64_global_init(cs_struct *ud) { + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + AArch64_init(mri); + ud->printer = AArch64_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = AArch64_getInstruction; + ud->reg_name = AArch64_reg_name; + ud->insn_id = AArch64_get_insn_id; + ud->insn_name = AArch64_insn_name; + ud->group_name = AArch64_group_name; + ud->post_printer = AArch64_post_printer; #ifndef CAPSTONE_DIET - ud->reg_access = AArch64_reg_access; + ud->reg_access = AArch64_reg_access; #endif - return CS_ERR_OK; + return CS_ERR_OK; } -cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value) -{ - if (type == CS_OPT_MODE) { - handle->mode = (cs_mode)value; - } +cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value) { + if (type == CS_OPT_MODE) { + handle->mode = (cs_mode)value; + } - return CS_ERR_OK; + return CS_ERR_OK; } #endif diff --git a/arch/AArch64/CapstoneAArch64Module.h b/arch/AArch64/CapstoneAArch64Module.h new file mode 100644 index 0000000000..145fd58b4e --- /dev/null +++ b/arch/AArch64/CapstoneAArch64Module.h @@ -0,0 +1,1956 @@ +// +// Created by Phosphorus15 on 2021/7/3. +// + +#ifndef CAPSTONE_CAPSTONEAARCH64MODULE_H +#define CAPSTONE_CAPSTONEAARCH64MODULE_H + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +#define Success MCDisassembler_Success +#define Fail MCDisassembler_Fail +static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeAuthLoadInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeAddSubImmShift(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, void *Decoder); + +static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, void *Decoder); + +static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Addr, + void *Decoder); + +static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address, + void *Decoder, int); + +static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr, + void *Decoder, int); + +static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm, + uint64_t Addr, void *Decoder); + +static DecodeStatus DecodeMatrixTile(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder, + unsigned NumBitsForTile); + +static DecodeStatus +DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, const void *Decoder); + +static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst *Inst, + unsigned RegMask, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeSVCROp(MCInst *Inst, unsigned Imm, uint64_t Address, + const void *Decoder); + +#define GET_REGINFO_ENUM +#define GET_INSTRINFO_ENUM +#define MIPS_GET_DISASSEMBLER +#define GET_REGINFO_MC_DESC +#include "AArch64GenDisassemblerTables.inc" + +FieldFromInstruction(fieldFromInstruction_2, uint16_t) + DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, + uint16_t) DecodeInstruction(decodeInstruction_2, + fieldFromInstruction_2, + decodeToMCInst_2, uint16_t) + + FieldFromInstruction(fieldFromInstruction_4, uint32_t) + DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) + DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, + decodeToMCInst_4, uint32_t) + + static const + unsigned FPR128DecoderTable[] = { + AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, + AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, + AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, + AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, + AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, + AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, + AArch64_Q30, AArch64_Q31}; + +static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = FPR128DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 15) + return Fail; + return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); +} + +static const unsigned FPR64DecoderTable[] = { + AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, + AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, + AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, + AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, + AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, + AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, + AArch64_D30, AArch64_D31}; + +static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = FPR64DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned FPR32DecoderTable[] = { + AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, + AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, + AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, + AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, + AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, + AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, + AArch64_S30, AArch64_S31}; + +static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = FPR32DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned FPR16DecoderTable[] = { + AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, + AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, + AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, + AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, + AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, + AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, + AArch64_H30, AArch64_H31}; + +static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = FPR16DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned FPR8DecoderTable[] = { + AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, + AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, + AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, + AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, + AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, + AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, + AArch64_B30, AArch64_B31}; + +static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = FPR8DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned GPR64DecoderTable[] = { + AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, + AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, + AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, + AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, + AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, + AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, + AArch64_LR, AArch64_XZR}; + +static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 30) + return Fail; + + unsigned Register = GPR64DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = GPR64DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned GPR64x8DecoderTable[] = { + AArch64_X0_X1_X2_X3_X4_X5_X6_X7, + AArch64_X2_X3_X4_X5_X6_X7_X8_X9, + AArch64_X4_X5_X6_X7_X8_X9_X10_X11, + AArch64_X6_X7_X8_X9_X10_X11_X12_X13, + AArch64_X8_X9_X10_X11_X12_X13_X14_X15, + AArch64_X10_X11_X12_X13_X14_X15_X16_X17, + AArch64_X12_X13_X14_X15_X16_X17_X18_X19, + AArch64_X14_X15_X16_X17_X18_X19_X20_X21, + AArch64_X16_X17_X18_X19_X20_X21_X22_X23, + AArch64_X18_X19_X20_X21_X22_X23_X24_X25, + AArch64_X20_X21_X22_X23_X24_X25_X26_X27, + AArch64_X22_X23_X24_X25_X26_X27_X28_FP, +}; + +static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 22) + return Fail; + if (RegNo & 1) + return Fail; + + unsigned Register = GPR64x8DecoderTable[RegNo >> 1]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = GPR64DecoderTable[RegNo]; + if (Register == AArch64_XZR) + Register = AArch64_SP; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned GPR32DecoderTable[] = { + AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, + AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, + AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, + AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, + AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, + AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, + AArch64_W30, AArch64_WZR}; + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = GPR32DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = GPR32DecoderTable[RegNo]; + if (Register == AArch64_WZR) + Register = AArch64_WSP; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned ZPRDecoderTable[] = { + AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, + AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, + AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, + AArch64_Z15, AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19, + AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, AArch64_Z24, + AArch64_Z25, AArch64_Z26, AArch64_Z27, AArch64_Z28, AArch64_Z29, + AArch64_Z30, AArch64_Z31}; + +static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = ZPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 15) + return Fail; + return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 7) + return Fail; + return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const unsigned ZZDecoderTable[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, + AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, + AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, + AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, + AArch64_Z16_Z17, AArch64_Z17_Z18, AArch64_Z18_Z19, AArch64_Z19_Z20, + AArch64_Z20_Z21, AArch64_Z21_Z22, AArch64_Z22_Z23, AArch64_Z23_Z24, + AArch64_Z24_Z25, AArch64_Z25_Z26, AArch64_Z26_Z27, AArch64_Z27_Z28, + AArch64_Z28_Z29, AArch64_Z29_Z30, AArch64_Z30_Z31, AArch64_Z31_Z0}; + +static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = ZZDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned ZZZDecoderTable[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, + AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, + AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, + AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, + AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, + AArch64_Z15_Z16_Z17, AArch64_Z16_Z17_Z18, AArch64_Z17_Z18_Z19, + AArch64_Z18_Z19_Z20, AArch64_Z19_Z20_Z21, AArch64_Z20_Z21_Z22, + AArch64_Z21_Z22_Z23, AArch64_Z22_Z23_Z24, AArch64_Z23_Z24_Z25, + AArch64_Z24_Z25_Z26, AArch64_Z25_Z26_Z27, AArch64_Z26_Z27_Z28, + AArch64_Z27_Z28_Z29, AArch64_Z28_Z29_Z30, AArch64_Z29_Z30_Z31, + AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1}; + +static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = ZZZDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned ZZZZDecoderTable[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, + AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, + AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, + AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, + AArch64_Z15_Z16_Z17_Z18, AArch64_Z16_Z17_Z18_Z19, AArch64_Z17_Z18_Z19_Z20, + AArch64_Z18_Z19_Z20_Z21, AArch64_Z19_Z20_Z21_Z22, AArch64_Z20_Z21_Z22_Z23, + AArch64_Z21_Z22_Z23_Z24, AArch64_Z22_Z23_Z24_Z25, AArch64_Z23_Z24_Z25_Z26, + AArch64_Z24_Z25_Z26_Z27, AArch64_Z25_Z26_Z27_Z28, AArch64_Z26_Z27_Z28_Z29, + AArch64_Z27_Z28_Z29_Z30, AArch64_Z28_Z29_Z30_Z31, AArch64_Z29_Z30_Z31_Z0, + AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2}; + +static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = ZZZZDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned PPRDecoderTable[] = { + AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5, + AArch64_P6, AArch64_P7, AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11, + AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15}; + +static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 15) + return Fail; + + unsigned Register = PPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 7) + return Fail; + + // Just reuse the PPR decode table + return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); +} + +static const unsigned VectorDecoderTable[] = { + AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, + AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, + AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, + AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, + AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, + AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, + AArch64_Q30, AArch64_Q31}; + +static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + + unsigned Register = VectorDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned QQDecoderTable[] = { + AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, + AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, + AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, + AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, + AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, + AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, + AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, + AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0}; + +static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = QQDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned QQQDecoderTable[] = { + AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, + AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, + AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, + AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, + AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, + AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, + AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, + AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, + AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, + AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, + AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1}; + +static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = QQQDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned QQQQDecoderTable[] = { + AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, + AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, + AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, + AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, + AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, + AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, + AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, + AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, + AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, + AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, + AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2}; + +static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = QQQQDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned DDDecoderTable[] = { + AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, + AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, + AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, + AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, + AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, + AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, + AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, + AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0}; + +static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = DDDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned DDDDecoderTable[] = { + AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, + AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, + AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, + AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, + AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, + AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, + AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, + AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, + AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, + AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, + AArch64_D30_D31_D0, AArch64_D31_D0_D1}; + +static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = DDDDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static const unsigned DDDDDecoderTable[] = { + AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, + AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, + AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, + AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, + AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, + AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, + AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, + AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, + AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, + AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, + AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2}; + +static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, + void *Decoder) { + if (RegNo > 31) + return Fail; + unsigned Register = DDDDDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return Success; +} + +static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + // scale{5} is asserted as 1 in tblgen. + Imm |= 0x20; + MCOperand_CreateImm0(Inst, 64 - Imm); + return Success; +} + +static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + MCOperand_CreateImm0(Inst, 64 - Imm); + return Success; +} + +static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, + uint64_t Addr, void *Decoder) { + int64_t ImmVal = Imm; + + // Sign-extend 19-bit immediate. + if (ImmVal & (1 << (19 - 1))) + ImmVal |= ~((1LL << 19) - 1); + + MCOperand_CreateImm0(Inst, ImmVal); + + return Success; +} + +static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, (Imm >> 1) & 1); + MCOperand_CreateImm0(Inst, Imm & 1); + return Success; +} + +static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder) { + MCOperand_CreateImm0(Inst, Imm); + + // Every system register in the encoding space is valid with the syntax + // S____, so decoding system registers always succeeds. + return Success; +} + +static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder) { + MCOperand_CreateImm0(Inst, Imm); + + return Success; +} + +static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + // This decoder exists to add the dummy Lane operand to the MCInst, which must + // be 1 in assembly but has no other real manifestation. + unsigned Rd = fieldFromInstruction_4(Insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(Insn, 5, 5); + unsigned IsToVec = fieldFromInstruction_4(Insn, 16, 1); + + if (IsToVec) { + DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); + DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); + } else { + DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); + DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); + } + + // Add the lane + MCOperand_CreateImm0(Inst, 1); + + return Success; +} + +static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm, + unsigned Add) { + MCOperand_CreateImm0(Inst, Add - Imm); + return Success; +} + +static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm, + unsigned Add) { + MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1)); + return Success; +} + +static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftRImm(Inst, Imm, 64); +} + +static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); +} + +static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftRImm(Inst, Imm, 32); +} + +static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); +} + +static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftRImm(Inst, Imm, 16); +} + +static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); +} + +static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftRImm(Inst, Imm, 8); +} + +static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftLImm(Inst, Imm, 64); +} + +static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftLImm(Inst, Imm, 32); +} + +static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftLImm(Inst, Imm, 16); +} + +static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, + uint64_t Addr, + void *Decoder) { + return DecodeVecShiftLImm(Inst, Imm, 8); +} + +static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Rm = fieldFromInstruction_4(insn, 16, 5); + unsigned shiftHi = fieldFromInstruction_4(insn, 22, 2); + unsigned shiftLo = fieldFromInstruction_4(insn, 10, 6); + unsigned shift = (shiftHi << 6) | shiftLo; + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_ADDWrs: + case AArch64_ADDSWrs: + case AArch64_SUBWrs: + case AArch64_SUBSWrs: + // if shift == '11' then ReservedValue() + if (shiftHi == 0x3) + return Fail; + 0x0; + case AArch64_ANDWrs: + case AArch64_ANDSWrs: + case AArch64_BICWrs: + case AArch64_BICSWrs: + case AArch64_ORRWrs: + case AArch64_ORNWrs: + case AArch64_EORWrs: + case AArch64_EONWrs: { + // if sf == '0' and imm6<5> == '1' then ReservedValue() + if (shiftLo >> 5 == 1) + return Fail; + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + } + case AArch64_ADDXrs: + case AArch64_ADDSXrs: + case AArch64_SUBXrs: + case AArch64_SUBSXrs: + // if shift == '11' then ReservedValue() + if (shiftHi == 0x3) + return Fail; + 0x0; + case AArch64_ANDXrs: + case AArch64_ANDSXrs: + case AArch64_BICXrs: + case AArch64_BICSXrs: + case AArch64_ORRXrs: + case AArch64_ORNXrs: + case AArch64_EORXrs: + case AArch64_EONXrs: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; + } + + MCOperand_CreateImm0(Inst, shift); + return Success; +} + +static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned imm = fieldFromInstruction_4(insn, 5, 16); + unsigned shift = fieldFromInstruction_4(insn, 21, 2); + shift <<= 4; + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_MOVZWi: + case AArch64_MOVNWi: + case AArch64_MOVKWi: + if (shift & (1U << 5)) + return Fail; + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + break; + case AArch64_MOVZXi: + case AArch64_MOVNXi: + case AArch64_MOVKXi: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + break; + } + + if (MCInst_getOpcode(Inst) == AArch64_MOVKWi || + MCInst_getOpcode(Inst) == AArch64_MOVKXi) + MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0)); + + MCOperand_CreateImm0(Inst, imm); + MCOperand_CreateImm0(Inst, shift); + return Success; +} + +static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rt = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned offset = fieldFromInstruction_4(insn, 10, 12); + + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + + case AArch64_PRFMui: + // Rt is an immediate in prefetch. + MCOperand_CreateImm0(Inst, Rt); + break; + + case AArch64_STRBBui: + case AArch64_LDRBBui: + case AArch64_LDRSBWui: + case AArch64_STRHHui: + case AArch64_LDRHHui: + case AArch64_LDRSHWui: + case AArch64_STRWui: + case AArch64_LDRWui: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + + case AArch64_LDRSBXui: + case AArch64_LDRSHXui: + case AArch64_LDRSWui: + case AArch64_STRXui: + case AArch64_LDRXui: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + + case AArch64_LDRQui: + case AArch64_STRQui: + DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); + break; + + case AArch64_LDRDui: + case AArch64_STRDui: + DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + + case AArch64_LDRSui: + case AArch64_STRSui: + DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + + case AArch64_LDRHui: + case AArch64_STRHui: + DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); + break; + + case AArch64_LDRBui: + case AArch64_STRBui: + DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); + break; + } + + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + + // if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) + MCOperand_CreateImm0(Inst, offset); + + return Success; +} + +static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rt = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + int64_t offset = fieldFromInstruction_4(insn, 12, 9); + + // offset is a 9-bit signed immediate, so sign extend it to + // fill the unsigned. + if (offset & (1 << (9 - 1))) + offset |= ~((1LL << 9) - 1); + + // First operand is always the writeback to the address register, if needed. + switch (MCInst_getOpcode(Inst)) { + default: + break; + case AArch64_LDRSBWpre: + case AArch64_LDRSHWpre: + case AArch64_STRBBpre: + case AArch64_LDRBBpre: + case AArch64_STRHHpre: + case AArch64_LDRHHpre: + case AArch64_STRWpre: + case AArch64_LDRWpre: + case AArch64_LDRSBWpost: + case AArch64_LDRSHWpost: + case AArch64_STRBBpost: + case AArch64_LDRBBpost: + case AArch64_STRHHpost: + case AArch64_LDRHHpost: + case AArch64_STRWpost: + case AArch64_LDRWpost: + case AArch64_LDRSBXpre: + case AArch64_LDRSHXpre: + case AArch64_STRXpre: + case AArch64_LDRSWpre: + case AArch64_LDRXpre: + case AArch64_LDRSBXpost: + case AArch64_LDRSHXpost: + case AArch64_STRXpost: + case AArch64_LDRSWpost: + case AArch64_LDRXpost: + case AArch64_LDRQpre: + case AArch64_STRQpre: + case AArch64_LDRQpost: + case AArch64_STRQpost: + case AArch64_LDRDpre: + case AArch64_STRDpre: + case AArch64_LDRDpost: + case AArch64_STRDpost: + case AArch64_LDRSpre: + case AArch64_STRSpre: + case AArch64_LDRSpost: + case AArch64_STRSpost: + case AArch64_LDRHpre: + case AArch64_STRHpre: + case AArch64_LDRHpost: + case AArch64_STRHpost: + case AArch64_LDRBpre: + case AArch64_STRBpre: + case AArch64_LDRBpost: + case AArch64_STRBpost: + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + break; + } + + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_PRFUMi: + // Rt is an immediate in prefetch. + MCOperand_CreateImm0(Inst, Rt); + break; + case AArch64_STURBBi: + case AArch64_LDURBBi: + case AArch64_LDURSBWi: + case AArch64_STURHHi: + case AArch64_LDURHHi: + case AArch64_LDURSHWi: + case AArch64_STURWi: + case AArch64_LDURWi: + case AArch64_LDTRSBWi: + case AArch64_LDTRSHWi: + case AArch64_STTRWi: + case AArch64_LDTRWi: + case AArch64_STTRHi: + case AArch64_LDTRHi: + case AArch64_LDTRBi: + case AArch64_STTRBi: + case AArch64_LDRSBWpre: + case AArch64_LDRSHWpre: + case AArch64_STRBBpre: + case AArch64_LDRBBpre: + case AArch64_STRHHpre: + case AArch64_LDRHHpre: + case AArch64_STRWpre: + case AArch64_LDRWpre: + case AArch64_LDRSBWpost: + case AArch64_LDRSHWpost: + case AArch64_STRBBpost: + case AArch64_LDRBBpost: + case AArch64_STRHHpost: + case AArch64_LDRHHpost: + case AArch64_STRWpost: + case AArch64_LDRWpost: + case AArch64_STLURBi: + case AArch64_STLURHi: + case AArch64_STLURWi: + case AArch64_LDAPURBi: + case AArch64_LDAPURSBWi: + case AArch64_LDAPURHi: + case AArch64_LDAPURSHWi: + case AArch64_LDAPURi: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURSBXi: + case AArch64_LDURSHXi: + case AArch64_LDURSWi: + case AArch64_STURXi: + case AArch64_LDURXi: + case AArch64_LDTRSBXi: + case AArch64_LDTRSHXi: + case AArch64_LDTRSWi: + case AArch64_STTRXi: + case AArch64_LDTRXi: + case AArch64_LDRSBXpre: + case AArch64_LDRSHXpre: + case AArch64_STRXpre: + case AArch64_LDRSWpre: + case AArch64_LDRXpre: + case AArch64_LDRSBXpost: + case AArch64_LDRSHXpost: + case AArch64_STRXpost: + case AArch64_LDRSWpost: + case AArch64_LDRXpost: + case AArch64_LDAPURSWi: + case AArch64_LDAPURSHXi: + case AArch64_LDAPURSBXi: + case AArch64_STLURXi: + case AArch64_LDAPURXi: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURQi: + case AArch64_STURQi: + case AArch64_LDRQpre: + case AArch64_STRQpre: + case AArch64_LDRQpost: + case AArch64_STRQpost: + DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURDi: + case AArch64_STURDi: + case AArch64_LDRDpre: + case AArch64_STRDpre: + case AArch64_LDRDpost: + case AArch64_STRDpost: + DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURSi: + case AArch64_STURSi: + case AArch64_LDRSpre: + case AArch64_STRSpre: + case AArch64_LDRSpost: + case AArch64_STRSpost: + DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURHi: + case AArch64_STURHi: + case AArch64_LDRHpre: + case AArch64_STRHpre: + case AArch64_LDRHpost: + case AArch64_STRHpost: + DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_LDURBi: + case AArch64_STURBi: + case AArch64_LDRBpre: + case AArch64_STRBpre: + case AArch64_LDRBpost: + case AArch64_STRBpost: + DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); + break; + } + + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + MCOperand_CreateImm0(Inst, offset); + + bool IsLoad = fieldFromInstruction_4(insn, 22, 1); + bool IsIndexed = fieldFromInstruction_4(insn, 10, 2) != 0; + bool IsFP = fieldFromInstruction_4(insn, 26, 1); + + // Cannot write back to a transfer register (but xzr != sp). + if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) + return SoftFail; + + return Success; +} + +static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rt = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5); + unsigned Rs = fieldFromInstruction_4(insn, 16, 5); + + unsigned Opcode = MCInst_getOpcode(Inst); + switch (Opcode) { + default: + return Fail; + case AArch64_STLXRW: + case AArch64_STLXRB: + case AArch64_STLXRH: + case AArch64_STXRW: + case AArch64_STXRB: + case AArch64_STXRH: + DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + 0x0; + case AArch64_LDARW: + case AArch64_LDARB: + case AArch64_LDARH: + case AArch64_LDAXRW: + case AArch64_LDAXRB: + case AArch64_LDAXRH: + case AArch64_LDXRW: + case AArch64_LDXRB: + case AArch64_LDXRH: + case AArch64_STLRW: + case AArch64_STLRB: + case AArch64_STLRH: + case AArch64_STLLRW: + case AArch64_STLLRB: + case AArch64_STLLRH: + case AArch64_LDLARW: + case AArch64_LDLARB: + case AArch64_LDLARH: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_STLXRX: + case AArch64_STXRX: + DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + 0x0; + case AArch64_LDARX: + case AArch64_LDAXRX: + case AArch64_LDXRX: + case AArch64_STLRX: + case AArch64_LDLARX: + case AArch64_STLLRX: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + break; + case AArch64_STLXPW: + case AArch64_STXPW: + DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + 0x0; + case AArch64_LDAXPW: + case AArch64_LDXPW: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_STLXPX: + case AArch64_STXPX: + DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); + 0x0; + case AArch64_LDAXPX: + case AArch64_LDXPX: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); + break; + } + + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + + // You shouldn't load to the same register twice in an instruction... + if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW || + Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) && + Rt == Rt2) + return SoftFail; + + return Success; +} + +static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rt = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5); + int64_t offset = fieldFromInstruction_4(insn, 15, 7); + bool IsLoad = fieldFromInstruction_4(insn, 22, 1); + + // offset is a 7-bit signed immediate, so sign extend it to + // fill the unsigned. + if (offset & (1 << (7 - 1))) + offset |= ~((1LL << 7) - 1); + + unsigned Opcode = MCInst_getOpcode(Inst); + bool NeedsDisjointWritebackTransfer = false; + + // First operand is always writeback of base register. + switch (Opcode) { + default: + break; + case AArch64_LDPXpost: + case AArch64_STPXpost: + case AArch64_LDPSWpost: + case AArch64_LDPXpre: + case AArch64_STPXpre: + case AArch64_LDPSWpre: + case AArch64_LDPWpost: + case AArch64_STPWpost: + case AArch64_LDPWpre: + case AArch64_STPWpre: + case AArch64_LDPQpost: + case AArch64_STPQpost: + case AArch64_LDPQpre: + case AArch64_STPQpre: + case AArch64_LDPDpost: + case AArch64_STPDpost: + case AArch64_LDPDpre: + case AArch64_STPDpre: + case AArch64_LDPSpost: + case AArch64_STPSpost: + case AArch64_LDPSpre: + case AArch64_STPSpre: + case AArch64_STGPpre: + case AArch64_STGPpost: + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + break; + } + + switch (Opcode) { + default: + return Fail; + case AArch64_LDPXpost: + case AArch64_STPXpost: + case AArch64_LDPSWpost: + case AArch64_LDPXpre: + case AArch64_STPXpre: + case AArch64_LDPSWpre: + case AArch64_STGPpre: + case AArch64_STGPpost: + NeedsDisjointWritebackTransfer = true; + 0x0; + case AArch64_LDNPXi: + case AArch64_STNPXi: + case AArch64_LDPXi: + case AArch64_STPXi: + case AArch64_LDPSWi: + case AArch64_STGPi: + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_LDPWpost: + case AArch64_STPWpost: + case AArch64_LDPWpre: + case AArch64_STPWpre: + NeedsDisjointWritebackTransfer = true; + 0x0; + case AArch64_LDNPWi: + case AArch64_STNPWi: + case AArch64_LDPWi: + case AArch64_STPWi: + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_LDNPQi: + case AArch64_STNPQi: + case AArch64_LDPQpost: + case AArch64_STPQpost: + case AArch64_LDPQi: + case AArch64_STPQi: + case AArch64_LDPQpre: + case AArch64_STPQpre: + DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); + DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_LDNPDi: + case AArch64_STNPDi: + case AArch64_LDPDpost: + case AArch64_STPDpost: + case AArch64_LDPDi: + case AArch64_STPDi: + case AArch64_LDPDpre: + case AArch64_STPDpre: + DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); + DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); + break; + case AArch64_LDNPSi: + case AArch64_STNPSi: + case AArch64_LDPSpost: + case AArch64_STPSpost: + case AArch64_LDPSi: + case AArch64_STPSi: + case AArch64_LDPSpre: + case AArch64_STPSpre: + DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); + DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); + break; + } + + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + MCOperand_CreateImm0(Inst, offset); + + // You shouldn't load to the same register twice in an instruction... + if (IsLoad && Rt == Rt2) + return SoftFail; + + // ... or do any operation that writes-back to a transfer register. But note + // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. + if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) + return SoftFail; + + return Success; +} + +static DecodeStatus DecodeAuthLoadInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rt = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + uint64_t offset = fieldFromInstruction_4(insn, 22, 1) << 9 | + fieldFromInstruction_4(insn, 12, 9); + unsigned writeback = fieldFromInstruction_4(insn, 11, 1); + + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_LDRAAwriteback: + case AArch64_LDRABwriteback: + DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, + Decoder); + break; + case AArch64_LDRAAindexed: + case AArch64_LDRABindexed: + break; + } + + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeSImm(Inst, offset, Addr, Decoder, 10); + + if (writeback && Rt == Rn && Rn != 31) { + return SoftFail; + } + + return Success; +} + +static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Rm = fieldFromInstruction_4(insn, 16, 5); + unsigned extend = fieldFromInstruction_4(insn, 10, 6); + + unsigned shift = extend & 0x7; + if (shift > 4) + return Fail; + + switch (MCInst_getOpcode(Inst)) { + default: + return Fail; + case AArch64_ADDWrx: + case AArch64_SUBWrx: + DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_ADDSWrx: + case AArch64_SUBSWrx: + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_ADDXrx: + case AArch64_SUBXrx: + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_ADDSXrx: + case AArch64_SUBSXrx: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_ADDXrx64: + case AArch64_SUBXrx64: + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; + case AArch64_SUBSXrx64: + case AArch64_ADDSXrx64: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; + } + + MCOperand_CreateImm0(Inst, extend); + return Success; +} + +static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Datasize = fieldFromInstruction_4(insn, 31, 1); + unsigned imm; + + if (Datasize) { + if (MCInst_getOpcode(Inst) == AArch64_ANDSXri) + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); + imm = fieldFromInstruction_4(insn, 10, 13); + if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) + return Fail; + } else { + if (MCInst_getOpcode(Inst) == AArch64_ANDSWri) + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); + imm = fieldFromInstruction_4(insn, 10, 12); + if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32)) + return Fail; + } + MCOperand_CreateImm0(Inst, imm); + return Success; +} + +static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned cmode = fieldFromInstruction_4(insn, 12, 4); + unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5; + imm |= fieldFromInstruction_4(insn, 5, 5); + + if (MCInst_getOpcode(Inst) == AArch64_MOVID) + DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); + + MCOperand_CreateImm0(Inst, imm); + + switch (MCInst_getOpcode(Inst)) { + default: + break; + case AArch64_MOVIv4i16: + case AArch64_MOVIv8i16: + case AArch64_MVNIv4i16: + case AArch64_MVNIv8i16: + case AArch64_MOVIv2i32: + case AArch64_MOVIv4i32: + case AArch64_MVNIv2i32: + case AArch64_MVNIv4i32: + MCOperand_CreateImm0(Inst, (cmode & 6) << 2); + break; + case AArch64_MOVIv2s_msl: + case AArch64_MOVIv4s_msl: + case AArch64_MVNIv2s_msl: + case AArch64_MVNIv4s_msl: + MCOperand_CreateImm0(Inst, (cmode & 1) ? 0x110 : 0x108); + break; + } + + return Success; +} + +static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned cmode = fieldFromInstruction_4(insn, 12, 4); + unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5; + imm |= fieldFromInstruction_4(insn, 5, 5); + + // Tied operands added twice. + DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); + DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); + + MCOperand_CreateImm0(Inst, imm); + MCOperand_CreateImm0(Inst, (cmode & 6) << 2); + + return Success; +} + +static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + int64_t imm = fieldFromInstruction_4(insn, 5, 19) << 2; + imm |= fieldFromInstruction_4(insn, 29, 2); + + // Sign-extend the 21-bit immediate. + if (imm & (1 << (21 - 1))) + imm |= ~((1LL << 21) - 1); + + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + // if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) + MCOperand_CreateImm0(Inst, imm); + + return Success; +} + +static DecodeStatus DecodeAddSubImmShift(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Imm = fieldFromInstruction_4(insn, 10, 14); + unsigned S = fieldFromInstruction_4(insn, 29, 1); + unsigned Datasize = fieldFromInstruction_4(insn, 31, 1); + + unsigned ShifterVal = (Imm >> 12) & 3; + unsigned ImmVal = Imm & 0xFFF; + + if (ShifterVal != 0 && ShifterVal != 1) + return Fail; + + if (Datasize) { + if (Rd == 31 && !S) + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + } else { + if (Rd == 31 && !S) + DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + } + + // if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) + MCOperand_CreateImm0(Inst, ImmVal); + MCOperand_CreateImm0(Inst, 12 * ShifterVal); + return Success; +} + +static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + int64_t imm = fieldFromInstruction_4(insn, 0, 26); + + // Sign-extend the 26-bit immediate. + if (imm & (1 << (26 - 1))) + imm |= ~((1LL << 26) - 1); + + // if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) + MCOperand_CreateImm0(Inst, imm); + + return Success; +} + +static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + uint32_t op1 = fieldFromInstruction_4(insn, 16, 3); + uint32_t op2 = fieldFromInstruction_4(insn, 5, 3); + uint32_t crm = fieldFromInstruction_4(insn, 8, 4); + uint32_t pstate_field = (op1 << 3) | op2; + + if ((pstate_field == AArch64PState_PAN || + pstate_field == AArch64PState_UAO) && + crm > 1) + return Fail; + + MCOperand_CreateImm0(Inst, pstate_field); + MCOperand_CreateImm0(Inst, crm); + + if (lookupPStateByEncoding(pstate_field)) + return Success; + + return Fail; +} + +static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + uint64_t Rt = fieldFromInstruction_4(insn, 0, 5); + uint64_t bit = fieldFromInstruction_4(insn, 31, 1) << 5; + bit |= fieldFromInstruction_4(insn, 19, 5); + int64_t dst = fieldFromInstruction_4(insn, 5, 14); + // const AArch64Disassembler *Dis = + // static_cast(Decoder, const AArch64Disassembler *); + + // Sign-extend 14-bit immediate. + if (dst & (1 << (14 - 1))) + dst |= ~((1LL << 14) - 1); + + if (fieldFromInstruction_4(insn, 31, 1) == 0) + DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); + else + DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); + MCOperand_CreateImm0(Inst, bit); + // if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) + MCOperand_CreateImm0(Inst, dst); + + return Success; +} + +static DecodeStatus +DecodeGPRSeqPairsClassRegisterClass(MCInst *Inst, unsigned RegClassID, + unsigned RegNo, uint64_t Addr, + void *Decoder) { + // Register number must be even (see CASP instruction) + if (RegNo & 0x1) + return Fail; + + unsigned Reg = AArch64MCRegisterClasses[RegClassID].RegsBegin[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + return Success; +} + +static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Addr, + void *Decoder) { + return DecodeGPRSeqPairsClassRegisterClass( + Inst, AArch64_WSeqPairsClassRegClassID, RegNo, Addr, Decoder); +} + +static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Addr, + void *Decoder) { + return DecodeGPRSeqPairsClassRegisterClass( + Inst, AArch64_XSeqPairsClassRegClassID, RegNo, Addr, Decoder); +} + +static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn, + uint64_t Addr, + void *Decoder) { + unsigned Zdn = fieldFromInstruction_4(insn, 0, 5); + unsigned imm = fieldFromInstruction_4(insn, 5, 13); + if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) + return Fail; + + // The same (tied) operand is added twice to the instruction. + DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); + if (MCInst_getOpcode(Inst) != AArch64_DUPM_ZI) + DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); + MCOperand_CreateImm0(Inst, imm); + return Success; +} + +static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address, + void *Decoder, int Bits) { + if (Imm & ~((1LL << Bits) - 1)) + return Fail; + + // Imm is a signed immediate, so sign extend it. + if (Imm & (1 << (Bits - 1))) + Imm |= ~((1LL << Bits) - 1); + + MCOperand_CreateImm0(Inst, Imm); + return Success; +} + +static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr, + void *Decoder, + int ElementWidth) { + unsigned Val = (uint8_t)Imm; + unsigned Shift = (Imm & 0x100) ? 8 : 0; + if (ElementWidth == 8 && Shift) + return Fail; + MCOperand_CreateImm0(Inst, Val); + MCOperand_CreateImm0(Inst, Shift); + return Success; +} + +static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm, + uint64_t Addr, void *Decoder) { + MCOperand_CreateImm0(Inst, Imm + 1); + return Success; +} + +static const unsigned MatrixZATileDecoderTable[5][16] = { + {AArch64_ZAB0}, + {AArch64_ZAH0, AArch64_ZAH1}, + {AArch64_ZAS0, AArch64_ZAS1, AArch64_ZAS2, AArch64_ZAS3}, + {AArch64_ZAD0, AArch64_ZAD1, AArch64_ZAD2, AArch64_ZAD3, AArch64_ZAD4, + AArch64_ZAD5, AArch64_ZAD6, AArch64_ZAD7}, + {AArch64_ZAQ0, AArch64_ZAQ1, AArch64_ZAQ2, AArch64_ZAQ3, AArch64_ZAQ4, + AArch64_ZAQ5, AArch64_ZAQ6, AArch64_ZAQ7, AArch64_ZAQ8, AArch64_ZAQ9, + AArch64_ZAQ10, AArch64_ZAQ11, AArch64_ZAQ12, AArch64_ZAQ13, AArch64_ZAQ14, + AArch64_ZAQ15}}; + +static DecodeStatus DecodeMatrixTile(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder, + unsigned NumBitsForTile) { + unsigned LastReg = (1 << NumBitsForTile) - 1; + if (RegNo > LastReg) + return Fail; + MCOperand_CreateReg0(Inst, MatrixZATileDecoderTable[NumBitsForTile][RegNo]); + return Success; +} + +static const unsigned MatrixIndexGPR32_12_15DecoderTable[] = { + AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15}; + +static DecodeStatus +DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, const void *Decoder) { + if (RegNo > 3) + return Fail; + MCOperand_CreateReg0(Inst, MatrixIndexGPR32_12_15DecoderTable[RegNo]); + return Success; +} + +static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst *Inst, + unsigned RegMask, + uint64_t Address, + const void *Decoder) { + if (RegMask > 0xFF) + return Fail; + MCOperand_CreateImm0(Inst, RegMask); + return Success; +} + +static DecodeStatus DecodeSVCROp(MCInst *Inst, unsigned Imm, uint64_t Address, + const void *Decoder) { + // if (Imm = lookupSVCRByEncoding(Imm)) { + MCOperand_CreateImm0(Inst, Imm); + return Success; + // } + // return Fail; +} + +#endif // CAPSTONE_CAPSTONEAARCH64MODULE_H diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h index c4a2f98ab3..b3ef267648 100644 --- a/arch/ARM/ARMAddressingModes.h +++ b/arch/ARM/ARMAddressingModes.h @@ -17,85 +17,95 @@ #ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H #define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H -#include "capstone/platform.h" #include "../../MathExtras.h" +#include "capstone/platform.h" /// ARM_AM - ARM Addressing Mode Stuff typedef enum ARM_AM_ShiftOpc { - ARM_AM_no_shift = 0, - ARM_AM_asr, - ARM_AM_lsl, - ARM_AM_lsr, - ARM_AM_ror, - ARM_AM_rrx + ARM_AM_no_shift = 0, + ARM_AM_asr, + ARM_AM_lsl, + ARM_AM_lsr, + ARM_AM_ror, + ARM_AM_rrx, + ARM_AM_uxtw } ARM_AM_ShiftOpc; -typedef enum ARM_AM_AddrOpc { - ARM_AM_sub = 0, - ARM_AM_add -} ARM_AM_AddrOpc; - -static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op) -{ - return Op == ARM_AM_sub ? "-" : ""; -} - -static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op) -{ - switch (Op) { - default: return ""; //llvm_unreachable("Unknown shift opc!"); - case ARM_AM_asr: return "asr"; - case ARM_AM_lsl: return "lsl"; - case ARM_AM_lsr: return "lsr"; - case ARM_AM_ror: return "ror"; - case ARM_AM_rrx: return "rrx"; - } -} - -static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op) -{ - switch (Op) { - default: return (unsigned int)-1; //llvm_unreachable("Unknown shift opc!"); - case ARM_AM_asr: return 2; - case ARM_AM_lsl: return 0; - case ARM_AM_lsr: return 1; - case ARM_AM_ror: return 3; - } +typedef enum ARM_AM_AddrOpc { ARM_AM_sub = 0, ARM_AM_add } ARM_AM_AddrOpc; + +static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op) { + return Op == ARM_AM_sub ? "-" : ""; +} + +static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op) { + switch (Op) { + default: + return ""; // llvm_unreachable("Unknown shift opc!"); + case ARM_AM_asr: + return "asr"; + case ARM_AM_lsl: + return "lsl"; + case ARM_AM_lsr: + return "lsr"; + case ARM_AM_ror: + return "ror"; + case ARM_AM_rrx: + return "rrx"; + case ARM_AM_uxtw: + return "uxtw"; + } +} + +static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op) { + switch (Op) { + default: + return (unsigned int)-1; // llvm_unreachable("Unknown shift opc!"); + case ARM_AM_asr: + return 2; + case ARM_AM_lsl: + return 0; + case ARM_AM_lsr: + return 1; + case ARM_AM_ror: + return 3; + } } typedef enum ARM_AM_AMSubMode { - ARM_AM_bad_am_submode = 0, - ARM_AM_ia, - ARM_AM_ib, - ARM_AM_da, - ARM_AM_db + ARM_AM_bad_am_submode = 0, + ARM_AM_ia, + ARM_AM_ib, + ARM_AM_da, + ARM_AM_db } ARM_AM_AMSubMode; -static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode) -{ - switch (Mode) { - default: return ""; - case ARM_AM_ia: return "ia"; - case ARM_AM_ib: return "ib"; - case ARM_AM_da: return "da"; - case ARM_AM_db: return "db"; - } +static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode) { + switch (Mode) { + default: + return ""; + case ARM_AM_ia: + return "ia"; + case ARM_AM_ib: + return "ib"; + case ARM_AM_da: + return "da"; + case ARM_AM_db: + return "db"; + } } /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. /// -static inline unsigned rotr32(unsigned Val, unsigned Amt) -{ - //assert(Amt < 32 && "Invalid rotate amount"); - return (Val >> Amt) | (Val << ((32-Amt)&31)); +static inline unsigned rotr32(unsigned Val, unsigned Amt) { + // assert(Amt < 32 && "Invalid rotate amount"); + return (Val >> Amt) | (Val << ((32 - Amt) & 31)); } /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. /// -static inline unsigned rotl32(unsigned Val, unsigned Amt) -{ - //assert(Amt < 32 && "Invalid rotate amount"); - return (Val << Amt) | (Val >> ((32-Amt)&31)); +static inline unsigned rotl32(unsigned Val, unsigned Amt) { + // assert(Amt < 32 && "Invalid rotate amount"); + return (Val << Amt) | (Val >> ((32 - Amt) & 31)); } //===--------------------------------------------------------------------===// @@ -112,175 +122,157 @@ static inline unsigned rotl32(unsigned Val, unsigned Amt) // reg, the second is the shift amount (or reg0 if not present or imm). The // third operand encodes the shift opcode and the imm if a reg isn't present. // -static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) -{ - return ShOp | (Imm << 3); +static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) { + return ShOp | (Imm << 3); } -static inline unsigned getSORegOffset(unsigned Op) -{ - return Op >> 3; -} +static inline unsigned getSORegOffset(unsigned Op) { return Op >> 3; } -static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op) -{ - return (ARM_AM_ShiftOpc)(Op & 7); +static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op) { + return (ARM_AM_ShiftOpc)(Op & 7); } /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return /// the 8-bit imm value. -static inline unsigned getSOImmValImm(unsigned Imm) -{ - return Imm & 0xFF; -} +static inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return /// the rotate amount. -static inline unsigned getSOImmValRot(unsigned Imm) -{ - return (Imm >> 8) * 2; -} +static inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, /// computing the rotate amount to use. If this immediate value cannot be /// handled with a single shifter-op, determine a good rotate amount that will /// take a maximal chunk of bits out of the immediate. -static inline unsigned getSOImmValRotate(unsigned Imm) -{ - unsigned TZ, RotAmt; - // 8-bit (or less) immediates are trivially shifter_operands with a rotate - // of zero. - if ((Imm & ~255U) == 0) return 0; - - // Use CTZ to compute the rotate amount. - TZ = CountTrailingZeros_32(Imm); - - // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, - // not 9. - RotAmt = TZ & ~1; - - // If we can handle this spread, return it. - if ((rotr32(Imm, RotAmt) & ~255U) == 0) - return (32-RotAmt)&31; // HW rotates right, not left. - - // For values like 0xF000000F, we should ignore the low 6 bits, then - // retry the hunt. - if (Imm & 63U) { - unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); - unsigned RotAmt2 = TZ2 & ~1; - if ((rotr32(Imm, RotAmt2) & ~255U) == 0) - return (32-RotAmt2)&31; // HW rotates right, not left. - } - - // Otherwise, we have no way to cover this span of bits with a single - // shifter_op immediate. Return a chunk of bits that will be useful to - // handle. - return (32-RotAmt)&31; // HW rotates right, not left. +static inline unsigned getSOImmValRotate(unsigned Imm) { + unsigned TZ, RotAmt; + // 8-bit (or less) immediates are trivially shifter_operands with a rotate + // of zero. + if ((Imm & ~255U) == 0) + return 0; + + // Use CTZ to compute the rotate amount. + TZ = CountTrailingZeros_32(Imm); + + // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, + // not 9. + RotAmt = TZ & ~1; + + // If we can handle this spread, return it. + if ((rotr32(Imm, RotAmt) & ~255U) == 0) + return (32 - RotAmt) & 31; // HW rotates right, not left. + + // For values like 0xF000000F, we should ignore the low 6 bits, then + // retry the hunt. + if (Imm & 63U) { + unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); + unsigned RotAmt2 = TZ2 & ~1; + if ((rotr32(Imm, RotAmt2) & ~255U) == 0) + return (32 - RotAmt2) & 31; // HW rotates right, not left. + } + + // Otherwise, we have no way to cover this span of bits with a single + // shifter_op immediate. Return a chunk of bits that will be useful to + // handle. + return (32 - RotAmt) & 31; // HW rotates right, not left. } /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit /// into an shifter_operand immediate operand, return the 12-bit encoding for /// it. If not, return -1. -static inline int getSOImmVal(unsigned Arg) -{ - unsigned RotAmt; - // 8-bit (or less) immediates are trivially shifter_operands with a rotate - // of zero. - if ((Arg & ~255U) == 0) return Arg; +static inline int getSOImmVal(unsigned Arg) { + unsigned RotAmt; + // 8-bit (or less) immediates are trivially shifter_operands with a rotate + // of zero. + if ((Arg & ~255U) == 0) + return Arg; - RotAmt = getSOImmValRotate(Arg); + RotAmt = getSOImmValRotate(Arg); - // If this cannot be handled with a single shifter_op, bail out. - if (rotr32(~255U, RotAmt) & Arg) - return -1; + // If this cannot be handled with a single shifter_op, bail out. + if (rotr32(~255U, RotAmt) & Arg) + return -1; - // Encode this correctly. - return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); + // Encode this correctly. + return rotl32(Arg, RotAmt) | ((RotAmt >> 1) << 8); } /// isSOImmTwoPartVal - Return true if the specified value can be obtained by /// or'ing together two SOImmVal's. -static inline bool isSOImmTwoPartVal(unsigned V) -{ - // If this can be handled with a single shifter_op, bail out. - V = rotr32(~255U, getSOImmValRotate(V)) & V; - if (V == 0) - return false; +static inline bool isSOImmTwoPartVal(unsigned V) { + // If this can be handled with a single shifter_op, bail out. + V = rotr32(~255U, getSOImmValRotate(V)) & V; + if (V == 0) + return false; - // If this can be handled with two shifter_op's, accept. - V = rotr32(~255U, getSOImmValRotate(V)) & V; - return V == 0; + // If this can be handled with two shifter_op's, accept. + V = rotr32(~255U, getSOImmValRotate(V)) & V; + return V == 0; } /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, /// return the first chunk of it. -static inline unsigned getSOImmTwoPartFirst(unsigned V) -{ - return rotr32(255U, getSOImmValRotate(V)) & V; +static inline unsigned getSOImmTwoPartFirst(unsigned V) { + return rotr32(255U, getSOImmValRotate(V)) & V; } /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, /// return the second chunk of it. -static inline unsigned getSOImmTwoPartSecond(unsigned V) -{ - // Mask out the first hunk. - V = rotr32(~255U, getSOImmValRotate(V)) & V; +static inline unsigned getSOImmTwoPartSecond(unsigned V) { + // Mask out the first hunk. + V = rotr32(~255U, getSOImmValRotate(V)) & V; - // Take what's left. - //assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); - return V; + // Take what's left. + // assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); + return V; } /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed /// by a left shift. Returns the shift amount to use. -static inline unsigned getThumbImmValShift(unsigned Imm) -{ - // 8-bit (or less) immediates are trivially immediate operand with a shift - // of zero. - if ((Imm & ~255U) == 0) return 0; +static inline unsigned getThumbImmValShift(unsigned Imm) { + // 8-bit (or less) immediates are trivially immediate operand with a shift + // of zero. + if ((Imm & ~255U) == 0) + return 0; - // Use CTZ to compute the shift amount. - return CountTrailingZeros_32(Imm); + // Use CTZ to compute the shift amount. + return CountTrailingZeros_32(Imm); } /// isThumbImmShiftedVal - Return true if the specified value can be obtained /// by left shifting a 8-bit immediate. -static inline bool isThumbImmShiftedVal(unsigned V) -{ - // If this can be handled with - V = (~255U << getThumbImmValShift(V)) & V; - return V == 0; +static inline bool isThumbImmShiftedVal(unsigned V) { + // If this can be handled with + V = (~255U << getThumbImmValShift(V)) & V; + return V == 0; } /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed /// by a left shift. Returns the shift amount to use. -static inline unsigned getThumbImm16ValShift(unsigned Imm) -{ - // 16-bit (or less) immediates are trivially immediate operand with a shift - // of zero. - if ((Imm & ~65535U) == 0) return 0; +static inline unsigned getThumbImm16ValShift(unsigned Imm) { + // 16-bit (or less) immediates are trivially immediate operand with a shift + // of zero. + if ((Imm & ~65535U) == 0) + return 0; - // Use CTZ to compute the shift amount. - return CountTrailingZeros_32(Imm); + // Use CTZ to compute the shift amount. + return CountTrailingZeros_32(Imm); } /// isThumbImm16ShiftedVal - Return true if the specified value can be /// obtained by left shifting a 16-bit immediate. -static inline bool isThumbImm16ShiftedVal(unsigned V) -{ - // If this can be handled with - V = (~65535U << getThumbImm16ValShift(V)) & V; - return V == 0; +static inline bool isThumbImm16ShiftedVal(unsigned V) { + // If this can be handled with + V = (~65535U << getThumbImm16ValShift(V)) & V; + return V == 0; } /// getThumbImmNonShiftedVal - If V is a value that satisfies /// isThumbImmShiftedVal, return the non-shiftd value. -static inline unsigned getThumbImmNonShiftedVal(unsigned V) -{ - return V >> getThumbImmValShift(V); +static inline unsigned getThumbImmNonShiftedVal(unsigned V) { + return V >> getThumbImmValShift(V); } - /// getT2SOImmValSplat - Return the 12-bit encoded representation /// if the specified value can be obtained by splatting the low 8 bits /// into every other byte or every byte of a 32-bit value. i.e., @@ -290,137 +282,132 @@ static inline unsigned getThumbImmNonShiftedVal(unsigned V) /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 /// Return -1 if none of the above apply. /// See ARM Reference Manual A6.3.2. -static inline int getT2SOImmValSplatVal(unsigned V) -{ - unsigned u, Vs, Imm; - // control = 0 - if ((V & 0xffffff00) == 0) - return V; +static inline int getT2SOImmValSplatVal(unsigned V) { + unsigned u, Vs, Imm; + // control = 0 + if ((V & 0xffffff00) == 0) + return V; - // If the value is zeroes in the first byte, just shift those off - Vs = ((V & 0xff) == 0) ? V >> 8 : V; - // Any passing value only has 8 bits of payload, splatted across the word - Imm = Vs & 0xff; - // Likewise, any passing values have the payload splatted into the 3rd byte - u = Imm | (Imm << 16); + // If the value is zeroes in the first byte, just shift those off + Vs = ((V & 0xff) == 0) ? V >> 8 : V; + // Any passing value only has 8 bits of payload, splatted across the word + Imm = Vs & 0xff; + // Likewise, any passing values have the payload splatted into the 3rd byte + u = Imm | (Imm << 16); - // control = 1 or 2 - if (Vs == u) - return (((Vs == V) ? 1 : 2) << 8) | Imm; + // control = 1 or 2 + if (Vs == u) + return (((Vs == V) ? 1 : 2) << 8) | Imm; - // control = 3 - if (Vs == (u | (u << 8))) - return (3 << 8) | Imm; + // control = 3 + if (Vs == (u | (u << 8))) + return (3 << 8) | Imm; - return -1; + return -1; } /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the /// specified value is a rotated 8-bit value. Return -1 if no rotation /// encoding is possible. /// See ARM Reference Manual A6.3.2. -static inline int getT2SOImmValRotateVal(unsigned V) -{ - unsigned RotAmt = CountLeadingZeros_32(V); - if (RotAmt >= 24) - return -1; +static inline int getT2SOImmValRotateVal(unsigned V) { + unsigned RotAmt = CountLeadingZeros_32(V); + if (RotAmt >= 24) + return -1; - // If 'Arg' can be handled with a single shifter_op return the value. - if ((rotr32(0xff000000U, RotAmt) & V) == V) - return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); + // If 'Arg' can be handled with a single shifter_op return the value. + if ((rotr32(0xff000000U, RotAmt) & V) == V) + return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); - return -1; + return -1; } /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit /// encoding for it. If not, return -1. /// See ARM Reference Manual A6.3.2. -static inline int getT2SOImmVal(unsigned Arg) -{ - int Rot; - // If 'Arg' is an 8-bit splat, then get the encoded value. - int Splat = getT2SOImmValSplatVal(Arg); - if (Splat != -1) - return Splat; - - // If 'Arg' can be handled with a single shifter_op return the value. - Rot = getT2SOImmValRotateVal(Arg); - if (Rot != -1) - return Rot; - - return -1; -} - -static inline unsigned getT2SOImmValRotate(unsigned V) -{ - unsigned RotAmt; - - if ((V & ~255U) == 0) - return 0; - - // Use CTZ to compute the rotate amount. - RotAmt = CountTrailingZeros_32(V); - return (32 - RotAmt) & 31; -} - -static inline bool isT2SOImmTwoPartVal (unsigned Imm) -{ - unsigned V = Imm; - // Passing values can be any combination of splat values and shifter - // values. If this can be handled with a single shifter or splat, bail - // out. Those should be handled directly, not with a two-part val. - if (getT2SOImmValSplatVal(V) != -1) - return false; - V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; - if (V == 0) - return false; - - // If this can be handled as an immediate, accept. - if (getT2SOImmVal(V) != -1) return true; - - // Likewise, try masking out a splat value first. - V = Imm; - if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) - V &= ~0xff00ff00U; - else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) - V &= ~0x00ff00ffU; - // If what's left can be handled as an immediate, accept. - if (getT2SOImmVal(V) != -1) return true; - - // Otherwise, do not accept. - return false; -} - -static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) -{ - //assert (isT2SOImmTwoPartVal(Imm) && - // "Immedate cannot be encoded as two part immediate!"); - // Try a shifter operand as one part - unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm; - // If the rest is encodable as an immediate, then return it. - if (getT2SOImmVal(V) != -1) return V; - - // Try masking out a splat value first. - if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) - return Imm & 0xff00ff00U; - - // The other splat is all that's left as an option. - //assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); - return Imm & 0x00ff00ffU; -} - -static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) -{ - // Mask out the first hunk - Imm ^= getT2SOImmTwoPartFirst(Imm); - // Return what's left - //assert (getT2SOImmVal(Imm) != -1 && - // "Unable to encode second part of T2 two part SO immediate"); - return Imm; +static inline int getT2SOImmVal(unsigned Arg) { + int Rot; + // If 'Arg' is an 8-bit splat, then get the encoded value. + int Splat = getT2SOImmValSplatVal(Arg); + if (Splat != -1) + return Splat; + + // If 'Arg' can be handled with a single shifter_op return the value. + Rot = getT2SOImmValRotateVal(Arg); + if (Rot != -1) + return Rot; + + return -1; +} + +static inline unsigned getT2SOImmValRotate(unsigned V) { + unsigned RotAmt; + + if ((V & ~255U) == 0) + return 0; + + // Use CTZ to compute the rotate amount. + RotAmt = CountTrailingZeros_32(V); + return (32 - RotAmt) & 31; +} + +static inline bool isT2SOImmTwoPartVal(unsigned Imm) { + unsigned V = Imm; + // Passing values can be any combination of splat values and shifter + // values. If this can be handled with a single shifter or splat, bail + // out. Those should be handled directly, not with a two-part val. + if (getT2SOImmValSplatVal(V) != -1) + return false; + V = rotr32(~255U, getT2SOImmValRotate(V)) & V; + if (V == 0) + return false; + + // If this can be handled as an immediate, accept. + if (getT2SOImmVal(V) != -1) + return true; + + // Likewise, try masking out a splat value first. + V = Imm; + if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) + V &= ~0xff00ff00U; + else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) + V &= ~0x00ff00ffU; + // If what's left can be handled as an immediate, accept. + if (getT2SOImmVal(V) != -1) + return true; + + // Otherwise, do not accept. + return false; +} + +static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) { + // assert (isT2SOImmTwoPartVal(Imm) && + // "Immedate cannot be encoded as two part immediate!"); + // Try a shifter operand as one part + unsigned V = rotr32(~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm; + // If the rest is encodable as an immediate, then return it. + if (getT2SOImmVal(V) != -1) + return V; + + // Try masking out a splat value first. + if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) + return Imm & 0xff00ff00U; + + // The other splat is all that's left as an option. + // assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); + return Imm & 0x00ff00ffU; +} + +static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) { + // Mask out the first hunk + Imm ^= getT2SOImmTwoPartFirst(Imm); + // Return what's left + // assert (getT2SOImmVal(Imm) != -1 && + // "Unable to encode second part of T2 two part SO immediate"); + return Imm; } - //===--------------------------------------------------------------------===// // Addressing Mode #2 //===--------------------------------------------------------------------===// @@ -439,33 +426,26 @@ static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) // and code rewriting), this operand will have the form: FI#, reg0, // with no shift amount for the frame offset. // -static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO, - unsigned IdxMode) -{ - //assert(Imm12 < (1 << 12) && "Imm too large!"); - bool isSub = Opc == ARM_AM_sub; - return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; +static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, + ARM_AM_ShiftOpc SO, unsigned IdxMode) { + // assert(Imm12 < (1 << 12) && "Imm too large!"); + bool isSub = Opc == ARM_AM_sub; + return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16); } -static inline unsigned getAM2Offset(unsigned AM2Opc) -{ - return AM2Opc & ((1 << 12)-1); +static inline unsigned getAM2Offset(unsigned AM2Opc) { + return AM2Opc & ((1 << 12) - 1); } -static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc) -{ - return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add; +static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc) { + return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add; } -static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) -{ - return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7); +static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { + return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7); } -static inline unsigned getAM2IdxMode(unsigned AM2Opc) -{ - return (AM2Opc >> 16); -} +static inline unsigned getAM2IdxMode(unsigned AM2Opc) { return (AM2Opc >> 16); } //===--------------------------------------------------------------------===// // Addressing Mode #3 @@ -483,26 +463,20 @@ static inline unsigned getAM2IdxMode(unsigned AM2Opc) /// getAM3Opc - This function encodes the addrmode3 opc field. static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset, - unsigned IdxMode) -{ - bool isSub = Opc == ARM_AM_sub; - return ((int)isSub << 8) | Offset | (IdxMode << 9); + unsigned IdxMode) { + bool isSub = Opc == ARM_AM_sub; + return ((int)isSub << 8) | Offset | (IdxMode << 9); } -static inline unsigned char getAM3Offset(unsigned AM3Opc) -{ - return AM3Opc & 0xFF; +static inline unsigned char getAM3Offset(unsigned AM3Opc) { + return AM3Opc & 0xFF; } -static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc) -{ - return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; +static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc) { + return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; } -static inline unsigned getAM3IdxMode(unsigned AM3Opc) -{ - return (AM3Opc >> 9); -} +static inline unsigned getAM3IdxMode(unsigned AM3Opc) { return (AM3Opc >> 9); } //===--------------------------------------------------------------------===// // Addressing Mode #4 @@ -519,14 +493,12 @@ static inline unsigned getAM3IdxMode(unsigned AM3Opc) // DB - Decrement before // For VFP instructions, only the IA and DB modes are valid. -static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode) -{ - return (ARM_AM_AMSubMode)(Mode & 0x7); +static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode) { + return (ARM_AM_AMSubMode)(Mode & 0x7); } -static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode) -{ - return (int)SubMode; +static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode) { + return (int)SubMode; } //===--------------------------------------------------------------------===// @@ -541,18 +513,18 @@ static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode) // operation in bit 8 and the immediate in bits 0-7. /// getAM5Opc - This function encodes the addrmode5 opc field. -static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset) -{ - bool isSub = Opc == ARM_AM_sub; - return ((int)isSub << 8) | Offset; +static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, + unsigned char Offset) { + bool isSub = Opc == ARM_AM_sub; + return ((int)isSub << 8) | Offset; } -static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc) -{ - return AM5Opc & 0xFF; + +static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc) { + return AM5Opc & 0xFF; } -static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc) -{ - return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; + +static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc) { + return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; } //===--------------------------------------------------------------------===// @@ -567,20 +539,17 @@ static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc) // operation (add or subtract) in bit 8 and the immediate in bits 0-7. /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field. -static inline unsigned getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset) -{ - bool isSub = Opc == ARM_AM_sub; - return ((int)isSub << 8) | Offset; +static inline unsigned getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset) { + bool isSub = Opc == ARM_AM_sub; + return ((int)isSub << 8) | Offset; } -static inline unsigned char getAM5FP16Offset(unsigned AM5Opc) -{ - return AM5Opc & 0xFF; +static inline unsigned char getAM5FP16Offset(unsigned AM5Opc) { + return AM5Opc & 0xFF; } -static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc) -{ - return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; +static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc) { + return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; } //===--------------------------------------------------------------------===// @@ -608,59 +577,58 @@ static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc) // the "Cmode" field of the instruction. The interfaces below treat the // Op and Cmode values as a single 5-bit value. -static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) -{ - return (OpCmode << 8) | Val; +static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { + return (OpCmode << 8) | Val; } -static inline unsigned getNEONModImmOpCmode(unsigned ModImm) -{ - return (ModImm >> 8) & 0x1f; + +static inline unsigned getNEONModImmOpCmode(unsigned ModImm) { + return (ModImm >> 8) & 0x1f; } -static inline unsigned getNEONModImmVal(unsigned ModImm) -{ - return ModImm & 0xff; + +static inline unsigned getNEONModImmVal(unsigned ModImm) { + return ModImm & 0xff; } /// decodeNEONModImm - Decode a NEON modified immediate value into the /// element value and the element size in bits. (If the element size is /// smaller than the vector, it is splatted into all the elements.) -static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits) -{ - unsigned OpCmode = getNEONModImmOpCmode(ModImm); - unsigned Imm8 = getNEONModImmVal(ModImm); - uint64_t Val = 0; - unsigned ByteNum; - - if (OpCmode == 0xe) { - // 8-bit vector elements - Val = Imm8; - *EltBits = 8; - } else if ((OpCmode & 0xc) == 0x8) { - // 16-bit vector elements - ByteNum = (OpCmode & 0x6) >> 1; - Val = (uint64_t)Imm8 << (8 * ByteNum); - *EltBits = 16; - } else if ((OpCmode & 0x8) == 0) { - // 32-bit vector elements, zero with one byte set - ByteNum = (OpCmode & 0x6) >> 1; - Val = (uint64_t)Imm8 << (8 * ByteNum); - *EltBits = 32; - } else if ((OpCmode & 0xe) == 0xc) { - // 32-bit vector elements, one byte with low bits set - ByteNum = 1 + (OpCmode & 0x1); - Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); - *EltBits = 32; - } else if (OpCmode == 0x1e) { - // 64-bit vector elements - for (ByteNum = 0; ByteNum < 8; ++ByteNum) { - if ((ModImm >> ByteNum) & 1) - Val |= (uint64_t)0xff << (8 * ByteNum); - } - *EltBits = 64; - } else { - //llvm_unreachable("Unsupported NEON immediate"); - } - return Val; +static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, + unsigned *EltBits) { + unsigned OpCmode = getNEONModImmOpCmode(ModImm); + unsigned Imm8 = getNEONModImmVal(ModImm); + uint64_t Val = 0; + unsigned ByteNum; + + if (OpCmode == 0xe) { + // 8-bit vector elements + Val = Imm8; + *EltBits = 8; + } else if ((OpCmode & 0xc) == 0x8) { + // 16-bit vector elements + ByteNum = (OpCmode & 0x6) >> 1; + Val = (uint64_t)Imm8 << (8 * ByteNum); + *EltBits = 16; + } else if ((OpCmode & 0x8) == 0) { + // 32-bit vector elements, zero with one byte set + ByteNum = (OpCmode & 0x6) >> 1; + Val = (uint64_t)Imm8 << (8 * ByteNum); + *EltBits = 32; + } else if ((OpCmode & 0xe) == 0xc) { + // 32-bit vector elements, one byte with low bits set + ByteNum = 1 + (OpCmode & 0x1); + Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); + *EltBits = 32; + } else if (OpCmode == 0x1e) { + // 64-bit vector elements + for (ByteNum = 0; ByteNum < 8; ++ByteNum) { + if ((ModImm >> ByteNum) & 1) + Val |= (uint64_t)0xff << (8 * ByteNum); + } + *EltBits = 64; + } else { + // llvm_unreachable("Unsupported NEON immediate"); + } + return Val; } ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode); @@ -668,31 +636,75 @@ ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode); //===--------------------------------------------------------------------===// // Floating-point Immediates // -static inline float getFPImmFloat(unsigned Imm) -{ - // We expect an 8-bit binary encoding of a floating-point number here. - union { - uint32_t I; - float F; - } FPUnion; - - uint8_t Sign = (Imm >> 7) & 0x1; - uint8_t Exp = (Imm >> 4) & 0x7; - uint8_t Mantissa = Imm & 0xf; - - // 8-bit FP iEEEE Float Encoding - // abcd efgh aBbbbbbc defgh000 00000000 00000000 - // - // where B = NOT(b); - - FPUnion.I = 0; - FPUnion.I |= ((uint32_t) Sign) << 31; - FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; - FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; - FPUnion.I |= (Exp & 0x3) << 23; - FPUnion.I |= Mantissa << 19; - return FPUnion.F; +static inline float getFPImmFloat(unsigned Imm) { + // We expect an 8-bit binary encoding of a floating-point number here. + union { + uint32_t I; + float F; + } FPUnion; + + uint8_t Sign = (Imm >> 7) & 0x1; + uint8_t Exp = (Imm >> 4) & 0x7; + uint8_t Mantissa = Imm & 0xf; + + // 8-bit FP iEEEE Float Encoding + // abcd efgh aBbbbbbc defgh000 00000000 00000000 + // + // where B = NOT(b); + + FPUnion.I = 0; + FPUnion.I |= ((uint32_t)Sign) << 31; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; + FPUnion.I |= (Exp & 0x3) << 23; + FPUnion.I |= Mantissa << 19; + return FPUnion.F; } -#endif +static unsigned ARM_AM_getVMOVModImmOpCmode(unsigned ModImm) { + return (ModImm >> 8) & 0x1f; +} +static unsigned ARM_AM_getVMOVModImmVal(unsigned ModImm) { + return ModImm & 0xff; +} + +/// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the +/// element value and the element size in bits. (If the element size is +/// smaller than the vector, it is splatted into all the elements.) +static uint64_t ARM_AM_decodeVMOVModImm(unsigned ModImm, unsigned *EltBits) { + unsigned OpCmode = ARM_AM_getVMOVModImmOpCmode(ModImm); + unsigned Imm8 = ARM_AM_getVMOVModImmVal(ModImm); + uint64_t Val = 0; + + if (OpCmode == 0xe) { + // 8-bit vector elements + Val = Imm8; + *EltBits = 8; + } else if ((OpCmode & 0xc) == 0x8) { + // 16-bit vector elements + unsigned ByteNum = (OpCmode & 0x6) >> 1; + Val = Imm8 << (8 * ByteNum); + *EltBits = 16; + } else if ((OpCmode & 0x8) == 0) { + // 32-bit vector elements, zero with one byte set + unsigned ByteNum = (OpCmode & 0x6) >> 1; + Val = Imm8 << (8 * ByteNum); + *EltBits = 32; + } else if ((OpCmode & 0xe) == 0xc) { + // 32-bit vector elements, one byte with low bits set + unsigned ByteNum = 1 + (OpCmode & 0x1); + Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); + *EltBits = 32; + } else if (OpCmode == 0x1e) { + // 64-bit vector elements + for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { + if ((ModImm >> ByteNum) & 1) + Val |= (uint64_t)0xff << (8 * ByteNum); + } + *EltBits = 64; + } + return Val; +} + +#endif diff --git a/arch/ARM/ARMBaseInfo.h b/arch/ARM/ARMBaseInfo.h index b7279569f6..94bc6fb6d7 100644 --- a/arch/ARM/ARMBaseInfo.h +++ b/arch/ARM/ARMBaseInfo.h @@ -26,169 +26,256 @@ // register name to register number. // #define GET_REGINFO_ENUM -#include "ARMGenRegisterInfo.inc" + +#include "ARMGenDisassemblerTables.inc" + +typedef enum VPTCodes { ARMVCC_None = 0, ARMVCC_Then, ARMVCC_Else } VPTCodes; + +inline static const char *ARMVPTPredToString(VPTCodes CC) { + switch (CC) { + case ARMVCC_None: + return "none"; + case ARMVCC_Then: + return "t"; + case ARMVCC_Else: + return "e"; + } +} + +// namespace ARMVCC // Enums corresponding to ARM condition codes // The CondCodes constants map directly to the 4-bit encoding of the // condition field for predicated instructions. -typedef enum ARMCC_CondCodes { // Meaning (integer) Meaning (floating-point) - ARMCC_EQ, // Equal Equal - ARMCC_NE, // Not equal Not equal, or unordered - ARMCC_HS, // Carry set >, ==, or unordered - ARMCC_LO, // Carry clear Less than - ARMCC_MI, // Minus, negative Less than - ARMCC_PL, // Plus, positive or zero >, ==, or unordered - ARMCC_VS, // Overflow Unordered - ARMCC_VC, // No overflow Not unordered - ARMCC_HI, // Unsigned higher Greater than, or unordered - ARMCC_LS, // Unsigned lower or same Less than or equal - ARMCC_GE, // Greater than or equal Greater than or equal - ARMCC_LT, // Less than Less than, or unordered - ARMCC_GT, // Greater than Greater than - ARMCC_LE, // Less than or equal <, ==, or unordered - ARMCC_AL // Always (unconditional) Always (unconditional) +typedef enum ARMCC_CondCodes { // Meaning (integer) Meaning + // (floating-point) + ARMCC_EQ, // Equal Equal + ARMCC_NE, // Not equal Not equal, or unordered + ARMCC_HS, // Carry set >, ==, or unordered + ARMCC_LO, // Carry clear Less than + ARMCC_MI, // Minus, negative Less than + ARMCC_PL, // Plus, positive or zero >, ==, or unordered + ARMCC_VS, // Overflow Unordered + ARMCC_VC, // No overflow Not unordered + ARMCC_HI, // Unsigned higher Greater than, or unordered + ARMCC_LS, // Unsigned lower or same Less than or equal + ARMCC_GE, // Greater than or equal Greater than or equal + ARMCC_LT, // Less than Less than, or unordered + ARMCC_GT, // Greater than Greater than + ARMCC_LE, // Less than or equal <, ==, or unordered + ARMCC_AL // Always (unconditional) Always (unconditional) } ARMCC_CondCodes; -inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC) -{ - switch (CC) { - case ARMCC_EQ: return ARMCC_NE; - case ARMCC_NE: return ARMCC_EQ; - case ARMCC_HS: return ARMCC_LO; - case ARMCC_LO: return ARMCC_HS; - case ARMCC_MI: return ARMCC_PL; - case ARMCC_PL: return ARMCC_MI; - case ARMCC_VS: return ARMCC_VC; - case ARMCC_VC: return ARMCC_VS; - case ARMCC_HI: return ARMCC_LS; - case ARMCC_LS: return ARMCC_HI; - case ARMCC_GE: return ARMCC_LT; - case ARMCC_LT: return ARMCC_GE; - case ARMCC_GT: return ARMCC_LE; - case ARMCC_LE: return ARMCC_GT; - default: return ARMCC_AL; - } +inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC) { + switch (CC) { + case ARMCC_EQ: + return ARMCC_NE; + case ARMCC_NE: + return ARMCC_EQ; + case ARMCC_HS: + return ARMCC_LO; + case ARMCC_LO: + return ARMCC_HS; + case ARMCC_MI: + return ARMCC_PL; + case ARMCC_PL: + return ARMCC_MI; + case ARMCC_VS: + return ARMCC_VC; + case ARMCC_VC: + return ARMCC_VS; + case ARMCC_HI: + return ARMCC_LS; + case ARMCC_LS: + return ARMCC_HI; + case ARMCC_GE: + return ARMCC_LT; + case ARMCC_LT: + return ARMCC_GE; + case ARMCC_GT: + return ARMCC_LE; + case ARMCC_LE: + return ARMCC_GT; + default: + return ARMCC_AL; + } } -inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC) -{ - switch (CC) { - case ARMCC_EQ: return "eq"; - case ARMCC_NE: return "ne"; - case ARMCC_HS: return "hs"; - case ARMCC_LO: return "lo"; - case ARMCC_MI: return "mi"; - case ARMCC_PL: return "pl"; - case ARMCC_VS: return "vs"; - case ARMCC_VC: return "vc"; - case ARMCC_HI: return "hi"; - case ARMCC_LS: return "ls"; - case ARMCC_GE: return "ge"; - case ARMCC_LT: return "lt"; - case ARMCC_GT: return "gt"; - case ARMCC_LE: return "le"; - case ARMCC_AL: return "al"; - default: return ""; - } +inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC) { + switch (CC) { + case ARMCC_EQ: + return "eq"; + case ARMCC_NE: + return "ne"; + case ARMCC_HS: + return "hs"; + case ARMCC_LO: + return "lo"; + case ARMCC_MI: + return "mi"; + case ARMCC_PL: + return "pl"; + case ARMCC_VS: + return "vs"; + case ARMCC_VC: + return "vc"; + case ARMCC_HI: + return "hi"; + case ARMCC_LS: + return "ls"; + case ARMCC_GE: + return "ge"; + case ARMCC_LT: + return "lt"; + case ARMCC_GT: + return "gt"; + case ARMCC_LE: + return "le"; + case ARMCC_AL: + return "al"; + default: + return ""; + } } -inline static const char *ARM_PROC_IFlagsToString(unsigned val) -{ - switch (val) { - case ARM_CPSFLAG_F: return "f"; - case ARM_CPSFLAG_I: return "i"; - case ARM_CPSFLAG_A: return "a"; - default: return ""; - } +inline static const char *ARM_PROC_IFlagsToString(unsigned val) { + switch (val) { + case ARM_CPSFLAG_F: + return "f"; + case ARM_CPSFLAG_I: + return "i"; + case ARM_CPSFLAG_A: + return "a"; + default: + return ""; + } } -inline static const char *ARM_PROC_IModToString(unsigned val) -{ - switch (val) { - case ARM_CPSMODE_IE: return "ie"; - case ARM_CPSMODE_ID: return "id"; - default: return ""; - } +inline static const char *ARM_PROC_IModToString(unsigned val) { + switch (val) { + case ARM_CPSMODE_IE: + return "ie"; + case ARM_CPSMODE_ID: + return "id"; + default: + return ""; + } } -inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8) -{ - // TODO: add details - switch (val + 1) { - default: return "BUGBUG"; - case ARM_MB_SY: return "sy"; - case ARM_MB_ST: return "st"; - case ARM_MB_LD: return HasV8 ? "ld" : "#0xd"; - case ARM_MB_RESERVED_12: return "#0xc"; - case ARM_MB_ISH: return "ish"; - case ARM_MB_ISHST: return "ishst"; - case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#9"; - case ARM_MB_RESERVED_8: return "#8"; - case ARM_MB_NSH: return "nsh"; - case ARM_MB_NSHST: return "nshst"; - case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#5"; - case ARM_MB_RESERVED_4: return "#4"; - case ARM_MB_OSH: return "osh"; - case ARM_MB_OSHST: return "oshst"; - case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#1"; - case ARM_MB_RESERVED_0: return "#0"; - } +inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8) { + // TODO: add details + switch (val + 1) { + default: + return "BUGBUG"; + case ARM_MB_SY: + return "sy"; + case ARM_MB_ST: + return "st"; + case ARM_MB_LD: + return HasV8 ? "ld" : "#0xd"; + case ARM_MB_RESERVED_12: + return "#0xc"; + case ARM_MB_ISH: + return "ish"; + case ARM_MB_ISHST: + return "ishst"; + case ARM_MB_ISHLD: + return HasV8 ? "ishld" : "#9"; + case ARM_MB_RESERVED_8: + return "#8"; + case ARM_MB_NSH: + return "nsh"; + case ARM_MB_NSHST: + return "nshst"; + case ARM_MB_NSHLD: + return HasV8 ? "nshld" : "#5"; + case ARM_MB_RESERVED_4: + return "#4"; + case ARM_MB_OSH: + return "osh"; + case ARM_MB_OSHST: + return "oshst"; + case ARM_MB_OSHLD: + return HasV8 ? "oshld" : "#1"; + case ARM_MB_RESERVED_0: + return "#0"; + } } enum ARM_ISB_InstSyncBOpt { - ARM_ISB_RESERVED_0 = 0, - ARM_ISB_RESERVED_1 = 1, - ARM_ISB_RESERVED_2 = 2, - ARM_ISB_RESERVED_3 = 3, - ARM_ISB_RESERVED_4 = 4, - ARM_ISB_RESERVED_5 = 5, - ARM_ISB_RESERVED_6 = 6, - ARM_ISB_RESERVED_7 = 7, - ARM_ISB_RESERVED_8 = 8, - ARM_ISB_RESERVED_9 = 9, - ARM_ISB_RESERVED_10 = 10, - ARM_ISB_RESERVED_11 = 11, - ARM_ISB_RESERVED_12 = 12, - ARM_ISB_RESERVED_13 = 13, - ARM_ISB_RESERVED_14 = 14, - ARM_ISB_SY = 15 + ARM_ISB_RESERVED_0 = 0, + ARM_ISB_RESERVED_1 = 1, + ARM_ISB_RESERVED_2 = 2, + ARM_ISB_RESERVED_3 = 3, + ARM_ISB_RESERVED_4 = 4, + ARM_ISB_RESERVED_5 = 5, + ARM_ISB_RESERVED_6 = 6, + ARM_ISB_RESERVED_7 = 7, + ARM_ISB_RESERVED_8 = 8, + ARM_ISB_RESERVED_9 = 9, + ARM_ISB_RESERVED_10 = 10, + ARM_ISB_RESERVED_11 = 11, + ARM_ISB_RESERVED_12 = 12, + ARM_ISB_RESERVED_13 = 13, + ARM_ISB_RESERVED_14 = 14, + ARM_ISB_SY = 15 }; -inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val) -{ - switch (val) { - default: // never reach - case ARM_ISB_RESERVED_0: return "#0x0"; - case ARM_ISB_RESERVED_1: return "#0x1"; - case ARM_ISB_RESERVED_2: return "#0x2"; - case ARM_ISB_RESERVED_3: return "#0x3"; - case ARM_ISB_RESERVED_4: return "#0x4"; - case ARM_ISB_RESERVED_5: return "#0x5"; - case ARM_ISB_RESERVED_6: return "#0x6"; - case ARM_ISB_RESERVED_7: return "#0x7"; - case ARM_ISB_RESERVED_8: return "#0x8"; - case ARM_ISB_RESERVED_9: return "#0x9"; - case ARM_ISB_RESERVED_10: return "#0xa"; - case ARM_ISB_RESERVED_11: return "#0xb"; - case ARM_ISB_RESERVED_12: return "#0xc"; - case ARM_ISB_RESERVED_13: return "#0xd"; - case ARM_ISB_RESERVED_14: return "#0xe"; - case ARM_ISB_SY: return "sy"; - } +inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val) { + switch (val) { + default: // never reach + case ARM_ISB_RESERVED_0: + return "#0x0"; + case ARM_ISB_RESERVED_1: + return "#0x1"; + case ARM_ISB_RESERVED_2: + return "#0x2"; + case ARM_ISB_RESERVED_3: + return "#0x3"; + case ARM_ISB_RESERVED_4: + return "#0x4"; + case ARM_ISB_RESERVED_5: + return "#0x5"; + case ARM_ISB_RESERVED_6: + return "#0x6"; + case ARM_ISB_RESERVED_7: + return "#0x7"; + case ARM_ISB_RESERVED_8: + return "#0x8"; + case ARM_ISB_RESERVED_9: + return "#0x9"; + case ARM_ISB_RESERVED_10: + return "#0xa"; + case ARM_ISB_RESERVED_11: + return "#0xb"; + case ARM_ISB_RESERVED_12: + return "#0xc"; + case ARM_ISB_RESERVED_13: + return "#0xd"; + case ARM_ISB_RESERVED_14: + return "#0xe"; + case ARM_ISB_SY: + return "sy"; + } } /// isARMLowRegister - Returns true if the register is a low register (r0-r7). /// -static inline bool isARMLowRegister(unsigned Reg) -{ - //using namespace ARM; - switch (Reg) { - case ARM_R0: case ARM_R1: case ARM_R2: case ARM_R3: - case ARM_R4: case ARM_R5: case ARM_R6: case ARM_R7: - return true; - default: - return false; - } +static inline bool isARMLowRegister(unsigned Reg) { + // using namespace ARM; + switch (Reg) { + case ARM_R0: + case ARM_R1: + case ARM_R2: + case ARM_R3: + case ARM_R4: + case ARM_R5: + case ARM_R6: + case ARM_R7: + return true; + default: + return false; + } } /// ARMII - This namespace holds all of the target specific flags that @@ -196,291 +283,306 @@ static inline bool isARMLowRegister(unsigned Reg) /// /// ARM Index Modes enum ARMII_IndexMode { - ARMII_IndexModeNone = 0, - ARMII_IndexModePre = 1, - ARMII_IndexModePost = 2, - ARMII_IndexModeUpd = 3 + ARMII_IndexModeNone = 0, + ARMII_IndexModePre = 1, + ARMII_IndexModePost = 2, + ARMII_IndexModeUpd = 3 }; /// ARM Addressing Modes typedef enum ARMII_AddrMode { - ARMII_AddrModeNone = 0, - ARMII_AddrMode1 = 1, - ARMII_AddrMode2 = 2, - ARMII_AddrMode3 = 3, - ARMII_AddrMode4 = 4, - ARMII_AddrMode5 = 5, - ARMII_AddrMode6 = 6, - ARMII_AddrModeT1_1 = 7, - ARMII_AddrModeT1_2 = 8, - ARMII_AddrModeT1_4 = 9, - ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data - ARMII_AddrModeT2_i12 = 11, - ARMII_AddrModeT2_i8 = 12, - ARMII_AddrModeT2_so = 13, - ARMII_AddrModeT2_pc = 14, // +/- i12 for pc relative data - ARMII_AddrModeT2_i8s4 = 15, // i8 * 4 - ARMII_AddrMode_i12 = 16 + ARMII_AddrModeNone = 0, + ARMII_AddrMode1 = 1, + ARMII_AddrMode2 = 2, + ARMII_AddrMode3 = 3, + ARMII_AddrMode4 = 4, + ARMII_AddrMode5 = 5, + ARMII_AddrMode6 = 6, + ARMII_AddrModeT1_1 = 7, + ARMII_AddrModeT1_2 = 8, + ARMII_AddrModeT1_4 = 9, + ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data + ARMII_AddrModeT2_i12 = 11, + ARMII_AddrModeT2_i8 = 12, + ARMII_AddrModeT2_so = 13, + ARMII_AddrModeT2_pc = 14, // +/- i12 for pc relative data + ARMII_AddrModeT2_i8s4 = 15, // i8 * 4 + ARMII_AddrMode_i12 = 16 } ARMII_AddrMode; -inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode) -{ - switch (addrmode) { - case ARMII_AddrModeNone: return "AddrModeNone"; - case ARMII_AddrMode1: return "AddrMode1"; - case ARMII_AddrMode2: return "AddrMode2"; - case ARMII_AddrMode3: return "AddrMode3"; - case ARMII_AddrMode4: return "AddrMode4"; - case ARMII_AddrMode5: return "AddrMode5"; - case ARMII_AddrMode6: return "AddrMode6"; - case ARMII_AddrModeT1_1: return "AddrModeT1_1"; - case ARMII_AddrModeT1_2: return "AddrModeT1_2"; - case ARMII_AddrModeT1_4: return "AddrModeT1_4"; - case ARMII_AddrModeT1_s: return "AddrModeT1_s"; - case ARMII_AddrModeT2_i12: return "AddrModeT2_i12"; - case ARMII_AddrModeT2_i8: return "AddrModeT2_i8"; - case ARMII_AddrModeT2_so: return "AddrModeT2_so"; - case ARMII_AddrModeT2_pc: return "AddrModeT2_pc"; - case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4"; - case ARMII_AddrMode_i12: return "AddrMode_i12"; - } +inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode) { + switch (addrmode) { + case ARMII_AddrModeNone: + return "AddrModeNone"; + case ARMII_AddrMode1: + return "AddrMode1"; + case ARMII_AddrMode2: + return "AddrMode2"; + case ARMII_AddrMode3: + return "AddrMode3"; + case ARMII_AddrMode4: + return "AddrMode4"; + case ARMII_AddrMode5: + return "AddrMode5"; + case ARMII_AddrMode6: + return "AddrMode6"; + case ARMII_AddrModeT1_1: + return "AddrModeT1_1"; + case ARMII_AddrModeT1_2: + return "AddrModeT1_2"; + case ARMII_AddrModeT1_4: + return "AddrModeT1_4"; + case ARMII_AddrModeT1_s: + return "AddrModeT1_s"; + case ARMII_AddrModeT2_i12: + return "AddrModeT2_i12"; + case ARMII_AddrModeT2_i8: + return "AddrModeT2_i8"; + case ARMII_AddrModeT2_so: + return "AddrModeT2_so"; + case ARMII_AddrModeT2_pc: + return "AddrModeT2_pc"; + case ARMII_AddrModeT2_i8s4: + return "AddrModeT2_i8s4"; + case ARMII_AddrMode_i12: + return "AddrMode_i12"; + } } /// Target Operand Flag enum. enum ARMII_TOF { - //===------------------------------------------------------------------===// - // ARM Specific MachineOperand flags. - - ARMII_MO_NO_FLAG, - - /// MO_LO16 - On a symbol operand, this represents a relocation containing - /// lower 16 bit of the address. Used only via movw instruction. - ARMII_MO_LO16, - - /// MO_HI16 - On a symbol operand, this represents a relocation containing - /// higher 16 bit of the address. Used only via movt instruction. - ARMII_MO_HI16, - - /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a - /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, - /// i.e. "FOO$non_lazy_ptr". - /// Used only via movw instruction. - ARMII_MO_LO16_NONLAZY, - - /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a - /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, - /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction. - ARMII_MO_HI16_NONLAZY, - - /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a - /// relocation containing lower 16 bit of the PC relative address of the - /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". - /// Used only via movw instruction. - ARMII_MO_LO16_NONLAZY_PIC, - - /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a - /// relocation containing lower 16 bit of the PC relative address of the - /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". - /// Used only via movt instruction. - ARMII_MO_HI16_NONLAZY_PIC, - - /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a - /// call operand. - ARMII_MO_PLT + //===------------------------------------------------------------------===// + // ARM Specific MachineOperand flags. + + ARMII_MO_NO_FLAG, + + /// MO_LO16 - On a symbol operand, this represents a relocation containing + /// lower 16 bit of the address. Used only via movw instruction. + ARMII_MO_LO16, + + /// MO_HI16 - On a symbol operand, this represents a relocation containing + /// higher 16 bit of the address. Used only via movt instruction. + ARMII_MO_HI16, + + /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a + /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, + /// i.e. "FOO$non_lazy_ptr". + /// Used only via movw instruction. + ARMII_MO_LO16_NONLAZY, + + /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a + /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, + /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction. + ARMII_MO_HI16_NONLAZY, + + /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a + /// relocation containing lower 16 bit of the PC relative address of the + /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". + /// Used only via movw instruction. + ARMII_MO_LO16_NONLAZY_PIC, + + /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a + /// relocation containing lower 16 bit of the PC relative address of the + /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". + /// Used only via movt instruction. + ARMII_MO_HI16_NONLAZY_PIC, + + /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a + /// call operand. + ARMII_MO_PLT }; enum { - //===------------------------------------------------------------------===// - // Instruction Flags. - - //===------------------------------------------------------------------===// - // This four-bit field describes the addressing mode used. - ARMII_AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h - - // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load - // and store ops only. Generic "updating" flag is used for ld/st multiple. - // The index mode enums are declared in ARMBaseInfo.h - ARMII_IndexModeShift = 5, - ARMII_IndexModeMask = 3 << ARMII_IndexModeShift, - - //===------------------------------------------------------------------===// - // Instruction encoding formats. - // - ARMII_FormShift = 7, - ARMII_FormMask = 0x3f << ARMII_FormShift, - - // Pseudo instructions - ARMII_Pseudo = 0 << ARMII_FormShift, - - // Multiply instructions - ARMII_MulFrm = 1 << ARMII_FormShift, - - // Branch instructions - ARMII_BrFrm = 2 << ARMII_FormShift, - ARMII_BrMiscFrm = 3 << ARMII_FormShift, - - // Data Processing instructions - ARMII_DPFrm = 4 << ARMII_FormShift, - ARMII_DPSoRegFrm = 5 << ARMII_FormShift, - - // Load and Store - ARMII_LdFrm = 6 << ARMII_FormShift, - ARMII_StFrm = 7 << ARMII_FormShift, - ARMII_LdMiscFrm = 8 << ARMII_FormShift, - ARMII_StMiscFrm = 9 << ARMII_FormShift, - ARMII_LdStMulFrm = 10 << ARMII_FormShift, - - ARMII_LdStExFrm = 11 << ARMII_FormShift, - - // Miscellaneous arithmetic instructions - ARMII_ArithMiscFrm = 12 << ARMII_FormShift, - ARMII_SatFrm = 13 << ARMII_FormShift, - - // Extend instructions - ARMII_ExtFrm = 14 << ARMII_FormShift, - - // VFP formats - ARMII_VFPUnaryFrm = 15 << ARMII_FormShift, - ARMII_VFPBinaryFrm = 16 << ARMII_FormShift, - ARMII_VFPConv1Frm = 17 << ARMII_FormShift, - ARMII_VFPConv2Frm = 18 << ARMII_FormShift, - ARMII_VFPConv3Frm = 19 << ARMII_FormShift, - ARMII_VFPConv4Frm = 20 << ARMII_FormShift, - ARMII_VFPConv5Frm = 21 << ARMII_FormShift, - ARMII_VFPLdStFrm = 22 << ARMII_FormShift, - ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift, - ARMII_VFPMiscFrm = 24 << ARMII_FormShift, - - // Thumb format - ARMII_ThumbFrm = 25 << ARMII_FormShift, - - // Miscelleaneous format - ARMII_MiscFrm = 26 << ARMII_FormShift, - - // NEON formats - ARMII_NGetLnFrm = 27 << ARMII_FormShift, - ARMII_NSetLnFrm = 28 << ARMII_FormShift, - ARMII_NDupFrm = 29 << ARMII_FormShift, - ARMII_NLdStFrm = 30 << ARMII_FormShift, - ARMII_N1RegModImmFrm= 31 << ARMII_FormShift, - ARMII_N2RegFrm = 32 << ARMII_FormShift, - ARMII_NVCVTFrm = 33 << ARMII_FormShift, - ARMII_NVDupLnFrm = 34 << ARMII_FormShift, - ARMII_N2RegVShLFrm = 35 << ARMII_FormShift, - ARMII_N2RegVShRFrm = 36 << ARMII_FormShift, - ARMII_N3RegFrm = 37 << ARMII_FormShift, - ARMII_N3RegVShFrm = 38 << ARMII_FormShift, - ARMII_NVExtFrm = 39 << ARMII_FormShift, - ARMII_NVMulSLFrm = 40 << ARMII_FormShift, - ARMII_NVTBLFrm = 41 << ARMII_FormShift, - - //===------------------------------------------------------------------===// - // Misc flags. - - // UnaryDP - Indicates this is a unary data processing instruction, i.e. - // it doesn't have a Rn operand. - ARMII_UnaryDP = 1 << 13, - - // Xform16Bit - Indicates this Thumb2 instruction may be transformed into - // a 16-bit Thumb instruction if certain conditions are met. - ARMII_Xform16Bit = 1 << 14, - - // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb - // instruction. Used by the parser to determine whether to require the 'S' - // suffix on the mnemonic (when not in an IT block) or preclude it (when - // in an IT block). - ARMII_ThumbArithFlagSetting = 1 << 18, - - //===------------------------------------------------------------------===// - // Code domain. - ARMII_DomainShift = 15, - ARMII_DomainMask = 7 << ARMII_DomainShift, - ARMII_DomainGeneral = 0 << ARMII_DomainShift, - ARMII_DomainVFP = 1 << ARMII_DomainShift, - ARMII_DomainNEON = 2 << ARMII_DomainShift, - ARMII_DomainNEONA8 = 4 << ARMII_DomainShift, - - //===------------------------------------------------------------------===// - // Field shifts - such shifts are used to set field while generating - // machine instructions. - // - // FIXME: This list will need adjusting/fixing as the MC code emitter - // takes shape and the ARMCodeEmitter.cpp bits go away. - ARMII_ShiftTypeShift = 4, - - ARMII_M_BitShift = 5, - ARMII_ShiftImmShift = 5, - ARMII_ShiftShift = 7, - ARMII_N_BitShift = 7, - ARMII_ImmHiShift = 8, - ARMII_SoRotImmShift = 8, - ARMII_RegRsShift = 8, - ARMII_ExtRotImmShift = 10, - ARMII_RegRdLoShift = 12, - ARMII_RegRdShift = 12, - ARMII_RegRdHiShift = 16, - ARMII_RegRnShift = 16, - ARMII_S_BitShift = 20, - ARMII_W_BitShift = 21, - ARMII_AM3_I_BitShift = 22, - ARMII_D_BitShift = 22, - ARMII_U_BitShift = 23, - ARMII_P_BitShift = 24, - ARMII_I_BitShift = 25, - ARMII_CondShift = 28 + //===------------------------------------------------------------------===// + // Instruction Flags. + + //===------------------------------------------------------------------===// + // This four-bit field describes the addressing mode used. + ARMII_AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h + + // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load + // and store ops only. Generic "updating" flag is used for ld/st multiple. + // The index mode enums are declared in ARMBaseInfo.h + ARMII_IndexModeShift = 5, + ARMII_IndexModeMask = 3 << ARMII_IndexModeShift, + + //===------------------------------------------------------------------===// + // Instruction encoding formats. + // + ARMII_FormShift = 7, + ARMII_FormMask = 0x3f << ARMII_FormShift, + + // Pseudo instructions + ARMII_Pseudo = 0 << ARMII_FormShift, + + // Multiply instructions + ARMII_MulFrm = 1 << ARMII_FormShift, + + // Branch instructions + ARMII_BrFrm = 2 << ARMII_FormShift, + ARMII_BrMiscFrm = 3 << ARMII_FormShift, + + // Data Processing instructions + ARMII_DPFrm = 4 << ARMII_FormShift, + ARMII_DPSoRegFrm = 5 << ARMII_FormShift, + + // Load and Store + ARMII_LdFrm = 6 << ARMII_FormShift, + ARMII_StFrm = 7 << ARMII_FormShift, + ARMII_LdMiscFrm = 8 << ARMII_FormShift, + ARMII_StMiscFrm = 9 << ARMII_FormShift, + ARMII_LdStMulFrm = 10 << ARMII_FormShift, + + ARMII_LdStExFrm = 11 << ARMII_FormShift, + + // Miscellaneous arithmetic instructions + ARMII_ArithMiscFrm = 12 << ARMII_FormShift, + ARMII_SatFrm = 13 << ARMII_FormShift, + + // Extend instructions + ARMII_ExtFrm = 14 << ARMII_FormShift, + + // VFP formats + ARMII_VFPUnaryFrm = 15 << ARMII_FormShift, + ARMII_VFPBinaryFrm = 16 << ARMII_FormShift, + ARMII_VFPConv1Frm = 17 << ARMII_FormShift, + ARMII_VFPConv2Frm = 18 << ARMII_FormShift, + ARMII_VFPConv3Frm = 19 << ARMII_FormShift, + ARMII_VFPConv4Frm = 20 << ARMII_FormShift, + ARMII_VFPConv5Frm = 21 << ARMII_FormShift, + ARMII_VFPLdStFrm = 22 << ARMII_FormShift, + ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift, + ARMII_VFPMiscFrm = 24 << ARMII_FormShift, + + // Thumb format + ARMII_ThumbFrm = 25 << ARMII_FormShift, + + // Miscelleaneous format + ARMII_MiscFrm = 26 << ARMII_FormShift, + + // NEON formats + ARMII_NGetLnFrm = 27 << ARMII_FormShift, + ARMII_NSetLnFrm = 28 << ARMII_FormShift, + ARMII_NDupFrm = 29 << ARMII_FormShift, + ARMII_NLdStFrm = 30 << ARMII_FormShift, + ARMII_N1RegModImmFrm = 31 << ARMII_FormShift, + ARMII_N2RegFrm = 32 << ARMII_FormShift, + ARMII_NVCVTFrm = 33 << ARMII_FormShift, + ARMII_NVDupLnFrm = 34 << ARMII_FormShift, + ARMII_N2RegVShLFrm = 35 << ARMII_FormShift, + ARMII_N2RegVShRFrm = 36 << ARMII_FormShift, + ARMII_N3RegFrm = 37 << ARMII_FormShift, + ARMII_N3RegVShFrm = 38 << ARMII_FormShift, + ARMII_NVExtFrm = 39 << ARMII_FormShift, + ARMII_NVMulSLFrm = 40 << ARMII_FormShift, + ARMII_NVTBLFrm = 41 << ARMII_FormShift, + + //===------------------------------------------------------------------===// + // Misc flags. + + // UnaryDP - Indicates this is a unary data processing instruction, i.e. + // it doesn't have a Rn operand. + ARMII_UnaryDP = 1 << 13, + + // Xform16Bit - Indicates this Thumb2 instruction may be transformed into + // a 16-bit Thumb instruction if certain conditions are met. + ARMII_Xform16Bit = 1 << 14, + + // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb + // instruction. Used by the parser to determine whether to require the 'S' + // suffix on the mnemonic (when not in an IT block) or preclude it (when + // in an IT block). + ARMII_ThumbArithFlagSetting = 1 << 18, + + //===------------------------------------------------------------------===// + // Code domain. + ARMII_DomainShift = 15, + ARMII_DomainMask = 7 << ARMII_DomainShift, + ARMII_DomainGeneral = 0 << ARMII_DomainShift, + ARMII_DomainVFP = 1 << ARMII_DomainShift, + ARMII_DomainNEON = 2 << ARMII_DomainShift, + ARMII_DomainNEONA8 = 4 << ARMII_DomainShift, + + //===------------------------------------------------------------------===// + // Field shifts - such shifts are used to set field while generating + // machine instructions. + // + // FIXME: This list will need adjusting/fixing as the MC code emitter + // takes shape and the ARMCodeEmitter.cpp bits go away. + ARMII_ShiftTypeShift = 4, + + ARMII_M_BitShift = 5, + ARMII_ShiftImmShift = 5, + ARMII_ShiftShift = 7, + ARMII_N_BitShift = 7, + ARMII_ImmHiShift = 8, + ARMII_SoRotImmShift = 8, + ARMII_RegRsShift = 8, + ARMII_ExtRotImmShift = 10, + ARMII_RegRdLoShift = 12, + ARMII_RegRdShift = 12, + ARMII_RegRdHiShift = 16, + ARMII_RegRnShift = 16, + ARMII_S_BitShift = 20, + ARMII_W_BitShift = 21, + ARMII_AM3_I_BitShift = 22, + ARMII_D_BitShift = 22, + ARMII_U_BitShift = 23, + ARMII_P_BitShift = 24, + ARMII_I_BitShift = 25, + ARMII_CondShift = 28 }; typedef struct MClassSysReg { - const char *Name; - arm_sysreg sysreg; - uint16_t M1Encoding12; - uint16_t M2M3Encoding8; - uint16_t Encoding; - int FeaturesRequired[2]; // 2 is enough for MClassSysRegsList + const char *Name; + arm_sysreg sysreg; + uint16_t M1Encoding12; + uint16_t M2M3Encoding8; + uint16_t Encoding; + int FeaturesRequired[2]; // 2 is enough for MClassSysRegsList } MClassSysReg; -enum TraceSyncBOpt { - CSYNC = 0 -}; +enum TraceSyncBOpt { CSYNC = 0 }; const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding); + const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12); // returns APSR with _ qualifier. // Note: ARMv7-M deprecates using MSR APSR without a _ qualifier -static inline const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) -{ - return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF)); +static inline const MClassSysReg * +lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) { + return lookupMClassSysRegByM2M3Encoding8((1 << 9) | (SYSm & 0xFF)); } -static inline const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) -{ - return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF)); +static inline const MClassSysReg * +lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) { + return lookupMClassSysRegByM2M3Encoding8((1 << 8) | (SYSm & 0xFF)); } // returns true if TestFeatures are all present in FeaturesRequired -static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, int TestFeatures) -{ - return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures); +static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, + int TestFeatures) { + return (TheReg->FeaturesRequired[0] == TestFeatures || + TheReg->FeaturesRequired[1] == TestFeatures); } // lookup system register using 12-bit SYSm value. // Note: the search is uniqued using M1 mask -static inline const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) -{ +static inline const MClassSysReg * +lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) { return lookupMClassSysRegByM1Encoding12(SYSm); } -static inline const char *ARM_TSB_TraceSyncBOptToString(unsigned val) -{ - switch (val) { - default: - // llvm_unreachable("Unknown trace synchronization barrier operation"); - return NULL; +static inline const char *ARM_TSB_TraceSyncBOptToString(unsigned val) { + switch (val) { + default: + // llvm_unreachable("Unknown trace synchronization barrier operation"); + return NULL; - case CSYNC: - return "csync"; - } + case CSYNC: + return "csync"; + } } #endif diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c index b2e5723af7..97ae275791 100644 --- a/arch/ARM/ARMDisassembler.c +++ b/arch/ARM/ARMDisassembler.c @@ -12,710 +12,458 @@ #ifdef CAPSTONE_HAS_ARM +#include #include -#include #include -#include +#include -#include "ARMAddressingModes.h" -#include "ARMBaseInfo.h" +#include "../../LEB128.h" +#include "../../MCDisassembler.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCRegisterInfo.h" -#include "../../LEB128.h" -#include "../../MCDisassembler.h" #include "../../cs_priv.h" #include "../../utils.h" +#include "ARMAddressingModes.h" +#include "ARMBaseInfo.h" #include "ARMDisassembler.h" #include "ARMMapping.h" #define GET_SUBTARGETINFO_ENUM -#include "ARMGenSubtargetInfo.inc" - +#define GET_REGINFO_ENUM #define GET_INSTRINFO_MC_DESC -#include "ARMGenInstrInfo.inc" - #define GET_INSTRINFO_ENUM -#include "ARMGenInstrInfo.inc" +#include "ARMGenDisassemblerTables.inc" -static bool ITStatus_push_back(ARM_ITStatus *it, char v) -{ - if (it->size >= sizeof(it->ITStates)) { - // TODO: consider warning user. - it->size = 0; - } - it->ITStates[it->size] = v; - it->size++; +static bool ITStatus_push_back(ARM_ITStatus *it, char v) { + if (it->size >= sizeof(it->ITStates)) { + // TODO: consider warning user. + it->size = 0; + } + it->ITStates[it->size] = v; + it->size++; - return true; + return true; } // Returns true if the current instruction is in an IT block -static bool ITStatus_instrInITBlock(ARM_ITStatus *it) -{ - //return !ITStates.empty(); - return (it->size > 0); +static bool ITStatus_instrInITBlock(ARM_ITStatus *it) { + // return !ITStates.empty(); + return (it->size > 0); } // Returns true if current instruction is the last instruction in an IT block -static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it) -{ - return (it->size == 1); +static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it) { + return (it->size == 1); } // Handles the condition code status of instructions in IT blocks // Returns the condition code for instruction in IT block -static unsigned ITStatus_getITCC(ARM_ITStatus *it) -{ - unsigned CC = ARMCC_AL; +static unsigned ITStatus_getITCC(ARM_ITStatus *it) { + unsigned CC = ARMCC_AL; - if (ITStatus_instrInITBlock(it)) - //CC = ITStates.back(); - CC = it->ITStates[it->size-1]; + if (ITStatus_instrInITBlock(it)) + // CC = ITStates.back(); + CC = it->ITStates[it->size - 1]; - return CC; + return CC; } // Advances the IT block state to the next T or E -static void ITStatus_advanceITState(ARM_ITStatus *it) -{ - //ITStates.pop_back(); - it->size--; +static void ITStatus_advanceITState(ARM_ITStatus *it) { + // ITStates.pop_back(); + it->size--; } // Called when decoding an IT instruction. Sets the IT state for the following -// instructions that for the IT block. Firstcond and Mask correspond to the +// instructions that for the IT block. Firstcond and Mask correspond to the // fields in the IT instruction encoding. -static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask) -{ - // (3 - the number of trailing zeros) is the number of then / else. - unsigned CondBit0 = Firstcond & 1; - unsigned NumTZ = CountTrailingZeros_32(Mask); - unsigned char CCBits = (unsigned char)Firstcond & 0xf; - unsigned Pos; +static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask) { + // (3 - the number of trailing zeros) is the number of then / else. + unsigned CondBit0 = Firstcond & 1; + unsigned NumTZ = CountTrailingZeros_32(Mask); + unsigned char CCBits = (unsigned char)Firstcond & 0xf; + unsigned Pos; - //assert(NumTZ <= 3 && "Invalid IT mask!"); - // push condition codes onto the stack the correct order for the pops - for (Pos = NumTZ + 1; Pos <= 3; ++Pos) { - bool T = ((Mask >> Pos) & 1) == (int)CondBit0; + // assert(NumTZ <= 3 && "Invalid IT mask!"); + // push condition codes onto the stack the correct order for the pops + for (Pos = NumTZ + 1; Pos <= 3; ++Pos) { + bool T = ((Mask >> Pos) & 1) == (int)CondBit0; - if (T) - ITStatus_push_back(it, CCBits); - else - ITStatus_push_back(it, CCBits ^ 1); - } + if (T) + ITStatus_push_back(it, CCBits); + else + ITStatus_push_back(it, CCBits ^ 1); + } - ITStatus_push_back(it, CCBits); + ITStatus_push_back(it, CCBits); } /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. -static bool Check(DecodeStatus *Out, DecodeStatus In) -{ - switch (In) { - case MCDisassembler_Success: - // Out stays the same. - return true; - case MCDisassembler_SoftFail: - *Out = In; - return true; - case MCDisassembler_Fail: - *Out = In; - return false; - default: // never reached - return false; - } -} - -// Forward declare these because the autogenerated code will reference them. -// Definitions are further down. -static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, - unsigned Insn, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst, - unsigned Insn, uint64_t Adddress, const void *Decoder); -static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, - uint64_t Address, const void* Decoder); -static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, - uint64_t Address, const void* Decoder); -static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, - uint64_t Address, const void* Decoder); -static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, - uint64_t Address, const void* Decoder); -static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); +static bool Check(DecodeStatus *Out, DecodeStatus In) { + switch (In) { + case MCDisassembler_Success: + // Out stays the same. + return true; + case MCDisassembler_SoftFail: + *Out = In; + return true; + case MCDisassembler_Fail: + *Out = In; + return false; + default: // never reached + return false; + } +} +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require); +#include "CapstoneARMModule.h" // Hacky: enable all features for disassembler -bool ARM_getFeatureBits(unsigned int mode, unsigned int feature) -{ - if ((mode & CS_MODE_V8) == 0) { - // not V8 mode - if (feature == ARM_HasV8Ops || feature == ARM_HasV8_1aOps || - feature == ARM_HasV8_4aOps || feature == ARM_HasV8_3aOps) - // HasV8MBaselineOps - return false; - } else { - if (feature == ARM_FeatureVFPOnlySP) - return false; - } - - if ((mode & CS_MODE_MCLASS) == 0) { - if (feature == ARM_FeatureMClass) - return false; - } - - if ((mode & CS_MODE_THUMB) == 0) { - // not Thumb - if (feature == ARM_FeatureThumb2 || feature == ARM_ModeThumb) - return false; - // FIXME: what mode enables D16? - if (feature == ARM_FeatureD16) - return false; - } else { - // Thumb - if (feature == ARM_FeatureD16) - return false; - } - - if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0) - return false; - - // we support everything - return true; +bool ARM_getFeatureBits(unsigned int mode, unsigned int feature) { + if ((mode & CS_MODE_V8) == 0) { + // not V8 mode + if (feature == ARM_HasV8Ops || feature == ARM_HasV8_1aOps || + feature == ARM_HasV8_4aOps || feature == ARM_HasV8_3aOps) + // HasV8MBaselineOps + return false; + } + + if ((mode & CS_MODE_MCLASS) == 0) { + if (feature == ARM_FeatureMClass) + return false; + } + + if ((mode & CS_MODE_THUMB) == 0) { + // not Thumb + if (feature == ARM_FeatureThumb2 || feature == ARM_ModeThumb) + return false; + // FIXME: what mode enables D16? + if (feature == ARM_FeatureVFP3_D16) + return false; + } else { + // Thumb + if (feature == ARM_FeatureVFP3_D16) + return false; + } + + if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0) + return false; + + // we support everything + return true; +} + +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require) { + // extended from original arm module + return ARM_getFeatureBits(Bits, Feature) == Require; } -#include "ARMGenDisassemblerTables.inc" - static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - if (Val == 0xF) return MCDisassembler_Fail; + uint64_t Address, + const void *Decoder) { + if (Val == 0xF) + return MCDisassembler_Fail; - // AL predicate is not allowed on Thumb1 branches. - if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) - return MCDisassembler_Fail; + // AL predicate is not allowed on Thumb1 branches. + if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) + return MCDisassembler_Fail; - MCOperand_CreateImm0(Inst, Val); + MCOperand_CreateImm0(Inst, Val); - if (Val == ARMCC_AL) { - MCOperand_CreateReg0(Inst, 0); - } else - MCOperand_CreateReg0(Inst, ARM_CPSR); + if (Val == ARMCC_AL) { + MCOperand_CreateReg0(Inst, 0); + } else + MCOperand_CreateReg0(Inst, ARM_CPSR); - return MCDisassembler_Success; + return MCDisassembler_Success; } #define GET_REGINFO_MC_DESC -#include "ARMGenRegisterInfo.inc" -void ARM_init(MCRegisterInfo *MRI) -{ - /* - InitMCRegisterInfo(ARMRegDesc, 289, - RA, PC, - ARMMCRegisterClasses, 103, - ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings, - ARMSubRegIdxLists, 57, - ARMSubRegIdxRanges, ARMRegEncodingTable); - */ - - MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289, - 0, 0, - ARMMCRegisterClasses, 103, - 0, 0, ARMRegDiffLists, 0, - ARMSubRegIdxLists, 57, - 0); +#include "ARMGenDisassemblerTables.inc" +void ARM_init(MCRegisterInfo *MRI) { + /* + InitMCRegisterInfo(ARMRegDesc, 289, + RA, PC, + ARMMCRegisterClasses, 103, + ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings, + ARMSubRegIdxLists, 57, + ARMSubRegIdxRanges, ARMRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo( + MRI, ARMRegDesc, ARR_SIZE(ARMRegDesc), 0, 0, ARMMCRegisterClasses, + ARR_SIZE(ARMMCRegisterClasses), 0, 0, ARMRegDiffLists, 0, + ARMSubRegIdxLists, ARR_SIZE(ARMSubRegIdxLists), 0); } // Post-decoding checks -static DecodeStatus checkDecodedInstruction(MCInst *MI, - uint32_t Insn, - DecodeStatus Result) -{ - switch (MCInst_getOpcode(MI)) { - case ARM_HVC: { - // HVC is undefined if condition = 0xf otherwise upredictable - // if condition != 0xe - uint32_t Cond = (Insn >> 28) & 0xF; - - if (Cond == 0xF) - return MCDisassembler_Fail; - - if (Cond != 0xE) - return MCDisassembler_SoftFail; - - return Result; - } - default: - return Result; - } -} - -static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, - uint16_t *Size, uint64_t Address) -{ - uint32_t insn; - DecodeStatus result; - - *Size = 0; - - if (code_len < 4) - // not enough data - return MCDisassembler_Fail; - - if (MI->flat_insn->detail) { - unsigned int i; - - memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm) + sizeof(cs_arm)); - - for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { - MI->flat_insn->detail->arm.operands[i].vector_index = -1; - MI->flat_insn->detail->arm.operands[i].neon_lane = -1; - } - } - - if (MODE_IS_BIG_ENDIAN(ud->mode)) - insn = (code[3] << 0) | (code[2] << 8) | - (code[1] << 16) | ((uint32_t) code[0] << 24); - else - insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | - (code[1] << 8) | (code[0] << 0); - - // Calling the auto-generated decoder function. - result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - result = checkDecodedInstruction(MI, insn, result); - if (result != MCDisassembler_Fail) - *Size = 4; - - return result; - } - - // VFP and NEON instructions, similarly, are shared between ARM - // and Thumb modes. - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - // Add a fake predicate operand, because we share these instruction - // definitions with Thumb2 where these instructions are predicable. - if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) - return MCDisassembler_Fail; - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - // Add a fake predicate operand, because we share these instruction - // definitions with Thumb2 where these instructions are predicable. - if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) - return MCDisassembler_Fail; - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - // Add a fake predicate operand, because we share these instruction - // definitions with Thumb2 where these instructions are predicable. - if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) - return MCDisassembler_Fail; - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - return result; - } - - result = decodeInstruction_4(DecoderTableCoProc32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - result = checkDecodedInstruction(MI, insn, result); - if (result != MCDisassembler_Fail) - *Size = 4; - - return result; - } - - MCInst_clear(MI); - *Size = 0; - return MCDisassembler_Fail; +static DecodeStatus checkDecodedInstruction(MCInst *MI, uint32_t Insn, + DecodeStatus Result) { + switch (MCInst_getOpcode(MI)) { + case ARM_HVC: { + // HVC is undefined if condition = 0xf otherwise upredictable + // if condition != 0xe + uint32_t Cond = (Insn >> 28) & 0xF; + + if (Cond == 0xF) + return MCDisassembler_Fail; + + if (Cond != 0xE) + return MCDisassembler_SoftFail; + + return Result; + } + default: + return Result; + } +} + +static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, + const uint8_t *code, size_t code_len, + uint16_t *Size, uint64_t Address) { + uint32_t insn; + DecodeStatus result; + + *Size = 0; + + if (code_len < 4) + // not enough data + return MCDisassembler_Fail; + + if (MI->flat_insn->detail) { + unsigned int i; + + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm) + sizeof(cs_arm)); + + for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { + MI->flat_insn->detail->arm.operands[i].vector_index = -1; + MI->flat_insn->detail->arm.operands[i].neon_lane = -1; + } + } + + if (MODE_IS_BIG_ENDIAN(ud->mode)) + insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | + ((uint32_t)code[0] << 24); + else + insn = ((uint32_t)code[3] << 24) | (code[2] << 16) | (code[1] << 8) | + (code[0] << 0); + + // Calling the auto-generated decoder function. + result = + decodeInstruction_4(DecoderTableARM32, MI, insn, Address, 0, ud->mode); + if (result != MCDisassembler_Fail) { + result = checkDecodedInstruction(MI, insn, result); + if (result != MCDisassembler_Fail) + *Size = 4; + + return result; + } + + // VFP and NEON instructions, similarly, are shared between ARM + // and Thumb modes. + MCInst_clear(MI); + result = + decodeInstruction_4(DecoderTableVFP32, MI, insn, Address, 0, ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + result = + decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address, 0, ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + // Add a fake predicate operand, because we share these instruction + // definitions with Thumb2 where these instructions are predicable. + if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) + return MCDisassembler_Fail; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address, + 0, ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + // Add a fake predicate operand, because we share these instruction + // definitions with Thumb2 where these instructions are predicable. + if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) + return MCDisassembler_Fail; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + // Add a fake predicate operand, because we share these instruction + // definitions with Thumb2 where these instructions are predicable. + if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) + return MCDisassembler_Fail; + return result; + } + + MCInst_clear(MI); + result = + decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address, 0, ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + result = + decodeInstruction_4(DecoderTableCoProc32, MI, insn, Address, 0, ud->mode); + if (result != MCDisassembler_Fail) { + result = checkDecodedInstruction(MI, insn, result); + if (result != MCDisassembler_Fail) + *Size = 4; + + return result; + } + + MCInst_clear(MI); + *Size = 0; + return MCDisassembler_Fail; } // Thumb1 instructions don't have explicit S bits. Rather, they // implicitly set CPSR. Since it's not represented in the encoding, the // auto-generated decoder won't inject the CPSR operand. We need to fix // that as a post-pass. -static void AddThumb1SBit(MCInst *MI, bool InITBlock) -{ - const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; - unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; - unsigned i; +static void AddThumb1SBit(MCInst *MI, bool InITBlock) { + const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; + unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; + unsigned i; - for (i = 0; i < NumOps; ++i) { - if (i == MCInst_getNumOperands(MI)) break; + for (i = 0; i < NumOps; ++i) { + if (i == MCInst_getNumOperands(MI)) + break; - if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) { - if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i - 1])) continue; - MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); - return; - } - } + if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && + OpInfo[i].RegClass == ARM_CCRRegClassID) { + if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i - 1])) + continue; + MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); + return; + } + } - //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR)); - MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); + // MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR)); + MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); } // Most Thumb instructions don't have explicit predicates in the // encoding, but rather get their predicates from IT context. We need // to fix up the predicate operands using this context information as a // post-pass. -static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) -{ - DecodeStatus S = MCDisassembler_Success; - const MCOperandInfo *OpInfo; - unsigned short NumOps; - unsigned int i; - unsigned CC; - - // A few instructions actually have predicates encoded in them. Don't - // try to overwrite it if we're seeing one of those. - switch (MCInst_getOpcode(MI)) { - case ARM_tBcc: - case ARM_t2Bcc: - case ARM_tCBZ: - case ARM_tCBNZ: - case ARM_tCPS: - case ARM_t2CPS3p: - case ARM_t2CPS2p: - case ARM_t2CPS1p: - case ARM_tMOVSr: - case ARM_tSETEND: - // Some instructions (mostly conditional branches) are not - // allowed in IT blocks. - if (ITStatus_instrInITBlock(&(ud->ITBlock))) - S = MCDisassembler_SoftFail; - else - return MCDisassembler_Success; - break; - - case ARM_t2HINT: - if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0x10) - S = MCDisassembler_SoftFail; - break; - - case ARM_tB: - case ARM_t2B: - case ARM_t2TBB: - case ARM_t2TBH: - // Some instructions (mostly unconditional branches) can - // only appears at the end of, or outside of, an IT. - // if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) - if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock))) - S = MCDisassembler_SoftFail; - break; - default: - break; - } - - // If we're in an IT block, base the predicate on that. Otherwise, - // assume a predicate of AL. - CC = ITStatus_getITCC(&(ud->ITBlock)); - if (CC == 0xF) - CC = ARMCC_AL; - - if (ITStatus_instrInITBlock(&(ud->ITBlock))) - ITStatus_advanceITState(&(ud->ITBlock)); - - OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; - NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; - - for (i = 0; i < NumOps; ++i) { - if (i == MCInst_getNumOperands(MI)) break; - - if (MCOperandInfo_isPredicate(&OpInfo[i])) { - MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); - - if (CC == ARMCC_AL) - MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); - else - MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); - - return S; - } - } - - MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); - - if (CC == ARMCC_AL) - MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, 0)); - else - MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, ARM_CPSR)); - - return S; +static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) { + DecodeStatus S = MCDisassembler_Success; + const MCOperandInfo *OpInfo; + unsigned short NumOps; + unsigned int i; + unsigned CC; + + // A few instructions actually have predicates encoded in them. Don't + // try to overwrite it if we're seeing one of those. + switch (MCInst_getOpcode(MI)) { + case ARM_tBcc: + case ARM_t2Bcc: + case ARM_tCBZ: + case ARM_tCBNZ: + case ARM_tCPS: + case ARM_t2CPS3p: + case ARM_t2CPS2p: + case ARM_t2CPS1p: + case ARM_tMOVSr: + case ARM_tSETEND: + // Some instructions (mostly conditional branches) are not + // allowed in IT blocks. + if (ITStatus_instrInITBlock(&(ud->ITBlock))) + S = MCDisassembler_SoftFail; + else + return MCDisassembler_Success; + break; + + case ARM_t2HINT: + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0x10) + S = MCDisassembler_SoftFail; + break; + + case ARM_tB: + case ARM_t2B: + case ARM_t2TBB: + case ARM_t2TBH: + // Some instructions (mostly unconditional branches) can + // only appears at the end of, or outside of, an IT. + // if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) + if (ITStatus_instrInITBlock(&(ud->ITBlock)) && + !ITStatus_instrLastInITBlock(&(ud->ITBlock))) + S = MCDisassembler_SoftFail; + break; + default: + break; + } + + // If we're in an IT block, base the predicate on that. Otherwise, + // assume a predicate of AL. + CC = ITStatus_getITCC(&(ud->ITBlock)); + if (CC == 0xF) + CC = ARMCC_AL; + + if (ITStatus_instrInITBlock(&(ud->ITBlock))) + ITStatus_advanceITState(&(ud->ITBlock)); + + OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; + NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; + + for (i = 0; i < NumOps; ++i) { + if (i == MCInst_getNumOperands(MI)) + break; + + if (MCOperandInfo_isPredicate(&OpInfo[i])) { + MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); + + if (CC == ARMCC_AL) + MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, 0)); + else + MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, ARM_CPSR)); + + return S; + } + } + + MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); + + if (CC == ARMCC_AL) + MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, 0)); + else + MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, ARM_CPSR)); + + return S; } // Thumb VFP instructions are a special case. Because we share their @@ -723,5042 +471,277 @@ static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) // mode, the auto-generated decoder will give them an (incorrect) // predicate operand. We need to rewrite these operands based on the IT // context as a post-pass. -static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI) -{ - unsigned CC; - unsigned short NumOps; - const MCOperandInfo *OpInfo; - unsigned i; - - CC = ITStatus_getITCC(&(ud->ITBlock)); - if (ITStatus_instrInITBlock(&(ud->ITBlock))) - ITStatus_advanceITState(&(ud->ITBlock)); - - OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; - NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; - - for (i = 0; i < NumOps; ++i) { - if (MCOperandInfo_isPredicate(&OpInfo[i])) { - MCOperand_setImm(MCInst_getOperand(MI, i), CC); - - if (CC == ARMCC_AL) - MCOperand_setReg(MCInst_getOperand(MI, i + 1), 0); - else - MCOperand_setReg(MCInst_getOperand(MI, i + 1), ARM_CPSR); - - return; - } - } -} - -static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, - uint16_t *Size, uint64_t Address) -{ - uint16_t insn16; - DecodeStatus result; - bool InITBlock; - unsigned Firstcond, Mask; - uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn; - size_t i; - - // We want to read exactly 2 bytes of data. - if (code_len < 2) - // not enough data - return MCDisassembler_Fail; - - if (MI->flat_insn->detail) { - memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm)); - for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { - MI->flat_insn->detail->arm.operands[i].vector_index = -1; - MI->flat_insn->detail->arm.operands[i].neon_lane = -1; - } - } - - if (MODE_IS_BIG_ENDIAN(ud->mode)) - insn16 = (code[0] << 8) | code[1]; - else - insn16 = (code[1] << 8) | code[0]; - - result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address); - if (result != MCDisassembler_Fail) { - *Size = 2; - Check(&result, AddThumbPredicate(ud, MI)); - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address); - if (result) { - *Size = 2; - InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); - Check(&result, AddThumbPredicate(ud, MI)); - AddThumb1SBit(MI, InITBlock); - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address); - if (result != MCDisassembler_Fail) { - *Size = 2; - - // Nested IT blocks are UNPREDICTABLE. Must be checked before we add - // the Thumb predicate. - if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock))) - return MCDisassembler_SoftFail; - - Check(&result, AddThumbPredicate(ud, MI)); - - // If we find an IT instruction, we need to parse its condition - // code and mask operands so that we can apply them correctly - // to the subsequent instructions. - if (MCInst_getOpcode(MI) == ARM_t2IT) { - Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0)); - Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1)); - ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask); - - // An IT instruction that would give a 'NV' predicate is unpredictable. - // if (Firstcond == ARMCC_AL && !isPowerOf2_32(Mask)) - // CS << "unpredictable IT predicate sequence"; - } - - return result; - } - - // We want to read exactly 4 bytes of data. - if (code_len < 4) - // not enough data - return MCDisassembler_Fail; - - if (MODE_IS_BIG_ENDIAN(ud->mode)) - insn32 = (code[3] << 0) | (code[2] << 8) | - (code[1] << 16) | ((uint32_t) code[0] << 24); - else - insn32 = (code[3] << 8) | (code[2] << 0) | - ((uint32_t) code[1] << 24) | (code[0] << 16); - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); - Check(&result, AddThumbPredicate(ud, MI)); - AddThumb1SBit(MI, InITBlock); - - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - Check(&result, AddThumbPredicate(ud, MI)); - return result; - } - - if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - UpdateThumbVFPPredicate(ud, MI); - return result; - } - } - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - return result; - } - - if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - Check(&result, AddThumbPredicate(ud, MI)); - return result; - } - } - - if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) { - MCInst_clear(MI); - NEONLdStInsn = insn32; - NEONLdStInsn &= 0xF0FFFFFF; - NEONLdStInsn |= 0x04000000; - result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - Check(&result, AddThumbPredicate(ud, MI)); - return result; - } - } - - if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) { - MCInst_clear(MI); - NEONDataInsn = insn32; - NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 - NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 - NEONDataInsn |= 0x12000000; // Set bits 28 and 25 - result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - Check(&result, AddThumbPredicate(ud, MI)); - return result; - } - } - - MCInst_clear(MI); - NEONCryptoInsn = insn32; - NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 - NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 - NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 - result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - return result; - } - - MCInst_clear(MI); - NEONv8Insn = insn32; - NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 - result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - return result; - } - - MCInst_clear(MI); - result = decodeInstruction_4(DecoderTableThumb2CoProc32, MI, insn32, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - Check(&result, AddThumbPredicate(ud, MI)); - return result; - } - - MCInst_clear(MI); - *Size = 0; - - return MCDisassembler_Fail; -} - -bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, - uint16_t *size, uint64_t address, void *info) -{ - DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); - - // TODO: fix table gen to eliminate these special cases - if (instr->Opcode == ARM_t__brkdiv0) - return false; - - //return status == MCDisassembler_Success; - return status != MCDisassembler_Fail; -} - -bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, - uint16_t *size, uint64_t address, void *info) -{ - DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); - - //return status == MCDisassembler_Success; - return status != MCDisassembler_Fail; -} - -static const uint16_t GPRDecoderTable[] = { - ARM_R0, ARM_R1, ARM_R2, ARM_R3, - ARM_R4, ARM_R5, ARM_R6, ARM_R7, - ARM_R8, ARM_R9, ARM_R10, ARM_R11, - ARM_R12, ARM_SP, ARM_LR, ARM_PC -}; - -static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 15) - return MCDisassembler_Fail; - - Register = GPRDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - if (RegNo == 15) - S = MCDisassembler_SoftFail; - - Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); - - return S; -} - -static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - if (RegNo == 15) { - MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); - - return MCDisassembler_Success; - } - - Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); - return S; -} - -static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - if (RegNo > 7) - return MCDisassembler_Fail; - - return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); -} - -static const uint16_t GPRPairDecoderTable[] = { - ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, - ARM_R8_R9, ARM_R10_R11, ARM_R12_SP -}; - -static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned RegisterPair; - DecodeStatus S = MCDisassembler_Success; - - if (RegNo > 13) - return MCDisassembler_Fail; - - if ((RegNo & 1) || RegNo == 0xe) - S = MCDisassembler_SoftFail; - - RegisterPair = GPRPairDecoderTable[RegNo / 2]; - MCOperand_CreateReg0(Inst, RegisterPair); - - return S; -} - -static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register = 0; - - switch (RegNo) { - case 0: - Register = ARM_R0; - break; - case 1: - Register = ARM_R1; - break; - case 2: - Register = ARM_R2; - break; - case 3: - Register = ARM_R3; - break; - case 9: - Register = ARM_R9; - break; - case 12: - Register = ARM_R12; - break; - default: - return MCDisassembler_Fail; - } - - MCOperand_CreateReg0(Inst, Register); - - return MCDisassembler_Success; -} - -static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - if ((RegNo == 13 && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) || RegNo == 15) - S = MCDisassembler_SoftFail; - - Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); - - return S; -} - -static const uint16_t SPRDecoderTable[] = { - ARM_S0, ARM_S1, ARM_S2, ARM_S3, - ARM_S4, ARM_S5, ARM_S6, ARM_S7, - ARM_S8, ARM_S9, ARM_S10, ARM_S11, - ARM_S12, ARM_S13, ARM_S14, ARM_S15, - ARM_S16, ARM_S17, ARM_S18, ARM_S19, - ARM_S20, ARM_S21, ARM_S22, ARM_S23, - ARM_S24, ARM_S25, ARM_S26, ARM_S27, - ARM_S28, ARM_S29, ARM_S30, ARM_S31 -}; - -static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Register = SPRDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); -} - -static const uint16_t DPRDecoderTable[] = { - ARM_D0, ARM_D1, ARM_D2, ARM_D3, - ARM_D4, ARM_D5, ARM_D6, ARM_D7, - ARM_D8, ARM_D9, ARM_D10, ARM_D11, - ARM_D12, ARM_D13, ARM_D14, ARM_D15, - ARM_D16, ARM_D17, ARM_D18, ARM_D19, - ARM_D20, ARM_D21, ARM_D22, ARM_D23, - ARM_D24, ARM_D25, ARM_D26, ARM_D27, - ARM_D28, ARM_D29, ARM_D30, ARM_D31 -}; - -static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31 || (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureD16) && RegNo > 15)) - return MCDisassembler_Fail; - - Register = DPRDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - if (RegNo > 7) - return MCDisassembler_Fail; - - return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - if (RegNo > 15) - return MCDisassembler_Fail; - - return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); -} - -static const uint16_t QPRDecoderTable[] = { - ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, - ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, - ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, - ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15 -}; - -static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 31 || (RegNo & 1) != 0) - return MCDisassembler_Fail; - - RegNo >>= 1; - - Register = QPRDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return MCDisassembler_Success; -} - -static const uint16_t DPairDecoderTable[] = { - ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, - ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, - ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, - ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, - ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, - ARM_Q15 -}; - -static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 30) - return MCDisassembler_Fail; - - Register = DPairDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return MCDisassembler_Success; -} - -static const uint16_t DPairSpacedDecoderTable[] = { - ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, - ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, - ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, - ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, - ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, - ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, - ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, - ARM_D28_D30, ARM_D29_D31 -}; - -static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const void *Decoder) -{ - unsigned Register; - - if (RegNo > 29) - return MCDisassembler_Fail; - - Register = DPairSpacedDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Register); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - if (Val) - MCOperand_CreateReg0(Inst, ARM_CPSR); - else - MCOperand_CreateReg0(Inst, 0); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - ARM_AM_ShiftOpc Shift; - unsigned Op; - unsigned Rm = fieldFromInstruction_4(Val, 0, 4); - unsigned type = fieldFromInstruction_4(Val, 5, 2); - unsigned imm = fieldFromInstruction_4(Val, 7, 5); - - // Register-immediate - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - Shift = ARM_AM_lsl; - switch (type) { - case 0: - Shift = ARM_AM_lsl; - break; - case 1: - Shift = ARM_AM_lsr; - break; - case 2: - Shift = ARM_AM_asr; - break; - case 3: - Shift = ARM_AM_ror; - break; - } - - if (Shift == ARM_AM_ror && imm == 0) - Shift = ARM_AM_rrx; - - Op = Shift | (imm << 3); - MCOperand_CreateImm0(Inst, Op); - - return S; -} - -static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - ARM_AM_ShiftOpc Shift; - - unsigned Rm = fieldFromInstruction_4(Val, 0, 4); - unsigned type = fieldFromInstruction_4(Val, 5, 2); - unsigned Rs = fieldFromInstruction_4(Val, 8, 4); - - // Register-register - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) - return MCDisassembler_Fail; - - Shift = ARM_AM_lsl; - switch (type) { - case 0: - Shift = ARM_AM_lsl; - break; - case 1: - Shift = ARM_AM_lsr; - break; - case 2: - Shift = ARM_AM_asr; - break; - case 3: - Shift = ARM_AM_ror; - break; - } - - MCOperand_CreateImm0(Inst, Shift); - - return S; -} - -static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - unsigned i; - DecodeStatus S = MCDisassembler_Success; - unsigned opcode; - bool NeedDisjointWriteback = false; - unsigned WritebackReg = 0; - - opcode = MCInst_getOpcode(Inst); - switch (opcode) { - default: - break; - - case ARM_LDMIA_UPD: - case ARM_LDMDB_UPD: - case ARM_LDMIB_UPD: - case ARM_LDMDA_UPD: - case ARM_t2LDMIA_UPD: - case ARM_t2LDMDB_UPD: - case ARM_t2STMIA_UPD: - case ARM_t2STMDB_UPD: - NeedDisjointWriteback = true; - WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0)); - break; - } - - // Empty register lists are not allowed. - if (Val == 0) return MCDisassembler_Fail; - - for (i = 0; i < 16; ++i) { - if (Val & (1 << i)) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) - return MCDisassembler_Fail; - - // Writeback not allowed if Rn is in the target list. - if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size - 1]))) - Check(&S, MCDisassembler_SoftFail); - } - } - - return S; -} - -static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned i; - unsigned Vd = fieldFromInstruction_4(Val, 8, 5); - unsigned regs = fieldFromInstruction_4(Val, 0, 8); - - // In case of unpredictable encoding, tweak the operands. - if (regs == 0 || (Vd + regs) > 32) { - regs = Vd + regs > 32 ? 32 - Vd : regs; - regs = (1u > regs? 1u : regs); - S = MCDisassembler_SoftFail; - } - - if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) - return MCDisassembler_Fail; - - for (i = 0; i < (regs - 1); ++i) { - if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) - return MCDisassembler_Fail; - } - - return S; -} - -static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned i; - unsigned Vd = fieldFromInstruction_4(Val, 8, 5); - unsigned regs = fieldFromInstruction_4(Val, 1, 7); - - // In case of unpredictable encoding, tweak the operands. - if (regs == 0 || regs > 16 || (Vd + regs) > 32) { - regs = Vd + regs > 32 ? 32 - Vd : regs; - regs = (1u > regs? 1u : regs); - regs = (16u > regs? regs : 16u); - S = MCDisassembler_SoftFail; - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) - return MCDisassembler_Fail; - - for (i = 0; i < (regs - 1); ++i) { - if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) - return MCDisassembler_Fail; - } - - return S; -} - -static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - // This operand encodes a mask of contiguous zeros between a specified MSB - // and LSB. To decode it, we create the mask of all bits MSB-and-lower, - // the mask of all bits LSB-and-lower, and then xor them to create - // the mask of that's all ones on [msb, lsb]. Finally we not it to - // create the final mask. - unsigned msb = fieldFromInstruction_4(Val, 5, 5); - unsigned lsb = fieldFromInstruction_4(Val, 0, 5); - uint32_t lsb_mask, msb_mask; - - DecodeStatus S = MCDisassembler_Success; - if (lsb > msb) { - Check(&S, MCDisassembler_SoftFail); - // The check above will cause the warning for the "potentially undefined - // instruction encoding" but we can't build a bad MCOperand value here - // with a lsb > msb or else printing the MCInst will cause a crash. - lsb = msb; - } - - msb_mask = 0xFFFFFFFF; - if (msb != 31) msb_mask = (1U << (msb + 1)) - 1; - lsb_mask = (1U << lsb) - 1; - - MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask)); - return S; -} - -static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); - unsigned coproc = fieldFromInstruction_4(Insn, 8, 4); - unsigned imm = fieldFromInstruction_4(Insn, 0, 8); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned U = fieldFromInstruction_4(Insn, 23, 1); - - switch (MCInst_getOpcode(Inst)) { - case ARM_LDC_OFFSET: - case ARM_LDC_PRE: - case ARM_LDC_POST: - case ARM_LDC_OPTION: - case ARM_LDCL_OFFSET: - case ARM_LDCL_PRE: - case ARM_LDCL_POST: - case ARM_LDCL_OPTION: - case ARM_STC_OFFSET: - case ARM_STC_PRE: - case ARM_STC_POST: - case ARM_STC_OPTION: - case ARM_STCL_OFFSET: - case ARM_STCL_PRE: - case ARM_STCL_POST: - case ARM_STCL_OPTION: - case ARM_t2LDC_OFFSET: - case ARM_t2LDC_PRE: - case ARM_t2LDC_POST: - case ARM_t2LDC_OPTION: - case ARM_t2LDCL_OFFSET: - case ARM_t2LDCL_PRE: - case ARM_t2LDCL_POST: - case ARM_t2LDCL_OPTION: - case ARM_t2STC_OFFSET: - case ARM_t2STC_PRE: - case ARM_t2STC_POST: - case ARM_t2STC_OPTION: - case ARM_t2STCL_OFFSET: - case ARM_t2STCL_PRE: - case ARM_t2STCL_POST: - case ARM_t2STCL_OPTION: - if (coproc == 0xA || coproc == 0xB) - return MCDisassembler_Fail; - break; - default: - break; - } - - if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (coproc != 14)) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, coproc); - MCOperand_CreateImm0(Inst, CRd); - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDC2_OFFSET: - case ARM_t2LDC2L_OFFSET: - case ARM_t2LDC2_PRE: - case ARM_t2LDC2L_PRE: - case ARM_t2STC2_OFFSET: - case ARM_t2STC2L_OFFSET: - case ARM_t2STC2_PRE: - case ARM_t2STC2L_PRE: - case ARM_LDC2_OFFSET: - case ARM_LDC2L_OFFSET: - case ARM_LDC2_PRE: - case ARM_LDC2L_PRE: - case ARM_STC2_OFFSET: - case ARM_STC2L_OFFSET: - case ARM_STC2_PRE: - case ARM_STC2L_PRE: - case ARM_t2LDC_OFFSET: - case ARM_t2LDCL_OFFSET: - case ARM_t2LDC_PRE: - case ARM_t2LDCL_PRE: - case ARM_t2STC_OFFSET: - case ARM_t2STCL_OFFSET: - case ARM_t2STC_PRE: - case ARM_t2STCL_PRE: - case ARM_LDC_OFFSET: - case ARM_LDCL_OFFSET: - case ARM_LDC_PRE: - case ARM_LDCL_PRE: - case ARM_STC_OFFSET: - case ARM_STCL_OFFSET: - case ARM_STC_PRE: - case ARM_STCL_PRE: - imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm); - MCOperand_CreateImm0(Inst, imm); - break; - case ARM_t2LDC2_POST: - case ARM_t2LDC2L_POST: - case ARM_t2STC2_POST: - case ARM_t2STC2L_POST: - case ARM_LDC2_POST: - case ARM_LDC2L_POST: - case ARM_STC2_POST: - case ARM_STC2L_POST: - case ARM_t2LDC_POST: - case ARM_t2LDCL_POST: - case ARM_t2STC_POST: - case ARM_t2STCL_POST: - case ARM_LDC_POST: - case ARM_LDCL_POST: - case ARM_STC_POST: - case ARM_STCL_POST: - imm |= U << 8; - // fall through. - default: - // The 'option' variant doesn't encode 'U' in the immediate since - // the immediate is unsigned [0,255]. - MCOperand_CreateImm0(Inst, imm); - break; - } - - switch (MCInst_getOpcode(Inst)) { - case ARM_LDC_OFFSET: - case ARM_LDC_PRE: - case ARM_LDC_POST: - case ARM_LDC_OPTION: - case ARM_LDCL_OFFSET: - case ARM_LDCL_PRE: - case ARM_LDCL_POST: - case ARM_LDCL_OPTION: - case ARM_STC_OFFSET: - case ARM_STC_PRE: - case ARM_STC_POST: - case ARM_STC_OPTION: - case ARM_STCL_OFFSET: - case ARM_STCL_PRE: - case ARM_STCL_POST: - case ARM_STCL_OPTION: - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - return S; -} - -static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - ARM_AM_AddrOpc Op; - ARM_AM_ShiftOpc Opc; - bool writeback; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned imm = fieldFromInstruction_4(Insn, 0, 12); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - unsigned reg = fieldFromInstruction_4(Insn, 25, 1); - unsigned P = fieldFromInstruction_4(Insn, 24, 1); - unsigned W = fieldFromInstruction_4(Insn, 21, 1); - unsigned idx_mode = 0, amt, tmp; - - // On stores, the writeback operand precedes Rt. - switch (MCInst_getOpcode(Inst)) { - case ARM_STR_POST_IMM: - case ARM_STR_POST_REG: - case ARM_STRB_POST_IMM: - case ARM_STRB_POST_REG: - case ARM_STRT_POST_REG: - case ARM_STRT_POST_IMM: - case ARM_STRBT_POST_REG: - case ARM_STRBT_POST_IMM: - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - // On loads, the writeback operand comes after Rt. - switch (MCInst_getOpcode(Inst)) { - case ARM_LDR_POST_IMM: - case ARM_LDR_POST_REG: - case ARM_LDRB_POST_IMM: - case ARM_LDRB_POST_REG: - case ARM_LDRBT_POST_REG: - case ARM_LDRBT_POST_IMM: - case ARM_LDRT_POST_REG: - case ARM_LDRT_POST_IMM: - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - Op = ARM_AM_add; - if (!fieldFromInstruction_4(Insn, 23, 1)) - Op = ARM_AM_sub; - - writeback = (P == 0) || (W == 1); - if (P && writeback) - idx_mode = ARMII_IndexModePre; - else if (!P && writeback) - idx_mode = ARMII_IndexModePost; - - if (writeback && (Rn == 15 || Rn == Rt)) - S = MCDisassembler_SoftFail; // UNPREDICTABLE - - if (reg) { - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - Opc = ARM_AM_lsl; - switch(fieldFromInstruction_4(Insn, 5, 2)) { - case 0: - Opc = ARM_AM_lsl; - break; - case 1: - Opc = ARM_AM_lsr; - break; - case 2: - Opc = ARM_AM_asr; - break; - case 3: - Opc = ARM_AM_ror; - break; - default: - return MCDisassembler_Fail; - } - - amt = fieldFromInstruction_4(Insn, 7, 5); - if (Opc == ARM_AM_ror && amt == 0) - Opc = ARM_AM_rrx; - - imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); - - MCOperand_CreateImm0(Inst, imm); - } else { - MCOperand_CreateReg0(Inst, 0); - tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); - MCOperand_CreateImm0(Inst, tmp); - } - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - ARM_AM_ShiftOpc ShOp; - unsigned shift; - unsigned Rn = fieldFromInstruction_4(Val, 13, 4); - unsigned Rm = fieldFromInstruction_4(Val, 0, 4); - unsigned type = fieldFromInstruction_4(Val, 5, 2); - unsigned imm = fieldFromInstruction_4(Val, 7, 5); - unsigned U = fieldFromInstruction_4(Val, 12, 1); - - ShOp = ARM_AM_lsl; - switch (type) { - case 0: - ShOp = ARM_AM_lsl; - break; - case 1: - ShOp = ARM_AM_lsr; - break; - case 2: - ShOp = ARM_AM_asr; - break; - case 3: - ShOp = ARM_AM_ror; - break; - } - - if (ShOp == ARM_AM_ror && imm == 0) - ShOp = ARM_AM_rrx; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - if (U) - shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); - else - shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); - - MCOperand_CreateImm0(Inst, shift); - - return S; -} - -static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned type = fieldFromInstruction_4(Insn, 22, 1); - unsigned imm = fieldFromInstruction_4(Insn, 8, 4); - unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8; - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - unsigned W = fieldFromInstruction_4(Insn, 21, 1); - unsigned P = fieldFromInstruction_4(Insn, 24, 1); - unsigned Rt2 = Rt + 1; - - bool writeback = (W == 1) | (P == 0); - - // For {LD,ST}RD, Rt must be even, else undefined. - switch (MCInst_getOpcode(Inst)) { - case ARM_STRD: - case ARM_STRD_PRE: - case ARM_STRD_POST: - case ARM_LDRD: - case ARM_LDRD_PRE: - case ARM_LDRD_POST: - if (Rt & 0x1) - S = MCDisassembler_SoftFail; - break; - default: - break; - } - - switch (MCInst_getOpcode(Inst)) { - case ARM_STRD: - case ARM_STRD_PRE: - case ARM_STRD_POST: - if (P == 0 && W == 1) - S = MCDisassembler_SoftFail; - - if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) - S = MCDisassembler_SoftFail; - - if (type && Rm == 15) - S = MCDisassembler_SoftFail; - - if (Rt2 == 15) - S = MCDisassembler_SoftFail; - - if (!type && fieldFromInstruction_4(Insn, 8, 4)) - S = MCDisassembler_SoftFail; - - break; - - case ARM_STRH: - case ARM_STRH_PRE: - case ARM_STRH_POST: - if (Rt == 15) - S = MCDisassembler_SoftFail; - - if (writeback && (Rn == 15 || Rn == Rt)) - S = MCDisassembler_SoftFail; - - if (!type && Rm == 15) - S = MCDisassembler_SoftFail; - - break; - - case ARM_LDRD: - case ARM_LDRD_PRE: - case ARM_LDRD_POST: - if (type && Rn == 15) { - if (Rt2 == 15) - S = MCDisassembler_SoftFail; - break; - } - - if (P == 0 && W == 1) - S = MCDisassembler_SoftFail; - - if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) - S = MCDisassembler_SoftFail; - - if (!type && writeback && Rn == 15) - S = MCDisassembler_SoftFail; - - if (writeback && (Rn == Rt || Rn == Rt2)) - S = MCDisassembler_SoftFail; - - break; - - case ARM_LDRH: - case ARM_LDRH_PRE: - case ARM_LDRH_POST: - if (type && Rn == 15) { - if (Rt == 15) - S = MCDisassembler_SoftFail; - break; - } - - if (Rt == 15) - S = MCDisassembler_SoftFail; - - if (!type && Rm == 15) - S = MCDisassembler_SoftFail; - - if (!type && writeback && (Rn == 15 || Rn == Rt)) - S = MCDisassembler_SoftFail; - break; - - case ARM_LDRSH: - case ARM_LDRSH_PRE: - case ARM_LDRSH_POST: - case ARM_LDRSB: - case ARM_LDRSB_PRE: - case ARM_LDRSB_POST: - if (type && Rn == 15){ - if (Rt == 15) - S = MCDisassembler_SoftFail; - break; - } - - if (type && (Rt == 15 || (writeback && Rn == Rt))) - S = MCDisassembler_SoftFail; - - if (!type && (Rt == 15 || Rm == 15)) - S = MCDisassembler_SoftFail; - - if (!type && writeback && (Rn == 15 || Rn == Rt)) - S = MCDisassembler_SoftFail; - - break; - - default: - break; - } - - if (writeback) { // Writeback - Inst->writeback = true; - - if (P) - U |= ARMII_IndexModePre << 9; - else - U |= ARMII_IndexModePost << 9; - - // On stores, the writeback operand precedes Rt. - switch (MCInst_getOpcode(Inst)) { - case ARM_STRD: - case ARM_STRD_PRE: - case ARM_STRD_POST: - case ARM_STRH: - case ARM_STRH_PRE: - case ARM_STRH_POST: - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - switch (MCInst_getOpcode(Inst)) { - case ARM_STRD: - case ARM_STRD_PRE: - case ARM_STRD_POST: - case ARM_LDRD: - case ARM_LDRD_PRE: - case ARM_LDRD_POST: - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt + 1, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - if (writeback) { - // On loads, the writeback operand comes after Rt. - switch (MCInst_getOpcode(Inst)) { - case ARM_LDRD: - case ARM_LDRD_PRE: - case ARM_LDRD_POST: - case ARM_LDRH: - case ARM_LDRH_PRE: - case ARM_LDRH_POST: - case ARM_LDRSH: - case ARM_LDRSH_PRE: - case ARM_LDRSH_POST: - case ARM_LDRSB: - case ARM_LDRSB_PRE: - case ARM_LDRSB_POST: - case ARM_LDRHTr: - case ARM_LDRSBTr: - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (type) { - MCOperand_CreateReg0(Inst, 0); - MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm); - } else { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, U); - } - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned mode = fieldFromInstruction_4(Insn, 23, 2); - - switch (mode) { - case 0: - mode = ARM_AM_da; - break; - case 1: - mode = ARM_AM_ia; - break; - case 2: - mode = ARM_AM_db; - break; - case 3: - mode = ARM_AM_ib; - break; - } - - MCOperand_CreateImm0(Inst, mode); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - - if (pred == 0xF) - return DecodeCPSInstruction(Inst, Insn, Address, Decoder); - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, - unsigned Insn, uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); - - if (pred == 0xF) { - // Ambiguous with RFE and SRS - switch (MCInst_getOpcode(Inst)) { - case ARM_LDMDA: - MCInst_setOpcode(Inst, ARM_RFEDA); - break; - case ARM_LDMDA_UPD: - MCInst_setOpcode(Inst, ARM_RFEDA_UPD); - break; - case ARM_LDMDB: - MCInst_setOpcode(Inst, ARM_RFEDB); - break; - case ARM_LDMDB_UPD: - MCInst_setOpcode(Inst, ARM_RFEDB_UPD); - break; - case ARM_LDMIA: - MCInst_setOpcode(Inst, ARM_RFEIA); - break; - case ARM_LDMIA_UPD: - MCInst_setOpcode(Inst, ARM_RFEIA_UPD); - break; - case ARM_LDMIB: - MCInst_setOpcode(Inst, ARM_RFEIB); - break; - case ARM_LDMIB_UPD: - MCInst_setOpcode(Inst, ARM_RFEIB_UPD); - break; - case ARM_STMDA: - MCInst_setOpcode(Inst, ARM_SRSDA); - break; - case ARM_STMDA_UPD: - MCInst_setOpcode(Inst, ARM_SRSDA_UPD); - break; - case ARM_STMDB: - MCInst_setOpcode(Inst, ARM_SRSDB); - break; - case ARM_STMDB_UPD: - MCInst_setOpcode(Inst, ARM_SRSDB_UPD); - break; - case ARM_STMIA: - MCInst_setOpcode(Inst, ARM_SRSIA); - break; - case ARM_STMIA_UPD: - MCInst_setOpcode(Inst, ARM_SRSIA_UPD); - break; - case ARM_STMIB: - MCInst_setOpcode(Inst, ARM_SRSIB); - break; - case ARM_STMIB_UPD: - MCInst_setOpcode(Inst, ARM_SRSIB_UPD); - break; - default: - return MCDisassembler_Fail; - } - - // For stores (which become SRS's, the only operand is the mode. - if (fieldFromInstruction_4(Insn, 20, 1) == 0) { - // Check SRS encoding constraints - if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 && - fieldFromInstruction_4(Insn, 20, 1) == 0)) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4)); - return S; - } - - return DecodeRFEInstruction(Inst, Insn, Address, Decoder); - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; // Tied - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -// Check for UNPREDICTABLE predicated ESB instruction -static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - unsigned imm8 = fieldFromInstruction_4(Insn, 0, 8); - DecodeStatus result = MCDisassembler_Success; - - MCOperand_CreateImm0(Inst, imm8); - - if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, - // so all predicates should be allowed. - if (imm8 == 0x10 && pred != 0xe && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureRAS)) - result = MCDisassembler_SoftFail; - - return result; -} - -static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - unsigned imod = fieldFromInstruction_4(Insn, 18, 2); - unsigned M = fieldFromInstruction_4(Insn, 17, 1); - unsigned iflags = fieldFromInstruction_4(Insn, 6, 3); - unsigned mode = fieldFromInstruction_4(Insn, 0, 5); - - DecodeStatus S = MCDisassembler_Success; - - // This decoder is called from multiple location that do not check - // the full encoding is valid before they do. - if (fieldFromInstruction_4(Insn, 5, 1) != 0 || - fieldFromInstruction_4(Insn, 16, 1) != 0 || - fieldFromInstruction_4(Insn, 20, 8) != 0x10) - return MCDisassembler_Fail; - - // imod == '01' --> UNPREDICTABLE - // NOTE: Even though this is technically UNPREDICTABLE, we choose to - // return failure here. The '01' imod value is unprintable, so there's - // nothing useful we could do even if we returned UNPREDICTABLE. - - if (imod == 1) return MCDisassembler_Fail; - - if (imod && M) { - MCInst_setOpcode(Inst, ARM_CPS3p); - MCOperand_CreateImm0(Inst, imod); - MCOperand_CreateImm0(Inst, iflags); - MCOperand_CreateImm0(Inst, mode); - } else if (imod && !M) { - MCInst_setOpcode(Inst, ARM_CPS2p); - MCOperand_CreateImm0(Inst, imod); - MCOperand_CreateImm0(Inst, iflags); - if (mode) S = MCDisassembler_SoftFail; - } else if (!imod && M) { - MCInst_setOpcode(Inst, ARM_CPS1p); - MCOperand_CreateImm0(Inst, mode); - if (iflags) S = MCDisassembler_SoftFail; - } else { - // imod == '00' && M == '0' --> UNPREDICTABLE - MCInst_setOpcode(Inst, ARM_CPS1p); - MCOperand_CreateImm0(Inst, mode); - S = MCDisassembler_SoftFail; - } - - return S; -} - -static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - unsigned imod = fieldFromInstruction_4(Insn, 9, 2); - unsigned M = fieldFromInstruction_4(Insn, 8, 1); - unsigned iflags = fieldFromInstruction_4(Insn, 5, 3); - unsigned mode = fieldFromInstruction_4(Insn, 0, 5); - - DecodeStatus S = MCDisassembler_Success; - - // imod == '01' --> UNPREDICTABLE - // NOTE: Even though this is technically UNPREDICTABLE, we choose to - // return failure here. The '01' imod value is unprintable, so there's - // nothing useful we could do even if we returned UNPREDICTABLE. - - if (imod == 1) return MCDisassembler_Fail; - - if (imod && M) { - MCInst_setOpcode(Inst, ARM_t2CPS3p); - MCOperand_CreateImm0(Inst, imod); - MCOperand_CreateImm0(Inst, iflags); - MCOperand_CreateImm0(Inst, mode); - } else if (imod && !M) { - MCInst_setOpcode(Inst, ARM_t2CPS2p); - MCOperand_CreateImm0(Inst, imod); - MCOperand_CreateImm0(Inst, iflags); - if (mode) S = MCDisassembler_SoftFail; - } else if (!imod && M) { - MCInst_setOpcode(Inst, ARM_t2CPS1p); - MCOperand_CreateImm0(Inst, mode); - if (iflags) S = MCDisassembler_SoftFail; - } else { - // imod == '00' && M == '0' --> this is a HINT instruction - int imm = fieldFromInstruction_4(Insn, 0, 8); - // HINT are defined only for immediate in [0..4] - if (imm > 4) return MCDisassembler_Fail; - - MCInst_setOpcode(Inst, ARM_t2HINT); - MCOperand_CreateImm0(Inst, imm); - } - - return S; -} - -static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); - unsigned imm = 0; - - imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0); - imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8); - imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); - imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11); - - if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16) - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, imm); - - return S; -} - -static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - unsigned imm = 0; - - imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0); - imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); - - if (MCInst_getOpcode(Inst) == ARM_MOVTi16) - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, imm); - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); - unsigned Ra = fieldFromInstruction_4(Insn, 12, 4); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - - if (pred == 0xF) - return DecodeCPSInstruction(Inst, Insn, Address, Decoder); - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Pred = fieldFromInstruction_4(Insn, 28, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - - if (Pred == 0xF) - return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Imm = fieldFromInstruction_4(Insn, 9, 1); - - if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps) || !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) - return MCDisassembler_Fail; - - // Decoder can be called from DecodeTST, which does not check the full - // encoding is valid. - if (fieldFromInstruction_4(Insn, 20, 12) != 0xf11 || - fieldFromInstruction_4(Insn, 4, 4) != 0) - return MCDisassembler_Fail; - - if (fieldFromInstruction_4(Insn, 10, 10) != 0 || - fieldFromInstruction_4(Insn, 0, 4) != 0) - S = MCDisassembler_SoftFail; - - MCInst_setOpcode(Inst, ARM_SETPAN); - MCOperand_CreateImm0(Inst, Imm); - - return S; -} - -static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned add = fieldFromInstruction_4(Val, 12, 1); - unsigned imm = fieldFromInstruction_4(Val, 0, 12); - unsigned Rn = fieldFromInstruction_4(Val, 13, 4); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!add) imm *= (unsigned int)-1; - if (imm == 0 && !add) imm = (unsigned int)INT32_MIN; - - MCOperand_CreateImm0(Inst, imm); - //if (Rn == 15) - // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); - - return S; -} - -static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Val, 9, 4); - // U == 1 to add imm, 0 to subtract it. - unsigned U = fieldFromInstruction_4(Val, 8, 1); - unsigned imm = fieldFromInstruction_4(Val, 0, 8); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (U) - MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm)); - else - MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm)); - - return S; -} - -static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Val, 9, 4); - // U == 1 to add imm, 0 to subtract it. - unsigned U = fieldFromInstruction_4(Val, 8, 1); - unsigned imm = fieldFromInstruction_4(Val, 0, 8); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (U) - MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_add, imm)); - else - MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_sub, imm)); - - return S; -} - -static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); -} - -static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus Status = MCDisassembler_Success; - - // Note the J1 and J2 values are from the encoded instruction. So here - // change them to I1 and I2 values via as documented: - // I1 = NOT(J1 EOR S); - // I2 = NOT(J2 EOR S); - // and build the imm32 with one trailing zero as documented: - // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); - unsigned S = fieldFromInstruction_4(Insn, 26, 1); - unsigned J1 = fieldFromInstruction_4(Insn, 13, 1); - unsigned J2 = fieldFromInstruction_4(Insn, 11, 1); - unsigned I1 = !(J1 ^ S); - unsigned I2 = !(J2 ^ S); - unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); - unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); - unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; - int imm32 = SignExtend32(tmp << 1, 25); - - MCOperand_CreateImm0(Inst, imm32); - - return Status; -} - -static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2; - - if (pred == 0xF) { - MCInst_setOpcode(Inst, ARM_BLXi); - imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; - MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); - return S; - } - - MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - - -static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rm = fieldFromInstruction_4(Val, 0, 4); - unsigned align = fieldFromInstruction_4(Val, 4, 2); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - if (!align) - MCOperand_CreateImm0(Inst, 0); - else - MCOperand_CreateImm0(Inst, 4 << align); - - return S; -} - -static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned wb, Rn, Rm; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - wb = fieldFromInstruction_4(Insn, 16, 4); - Rn = fieldFromInstruction_4(Insn, 16, 4); - Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; - Rm = fieldFromInstruction_4(Insn, 0, 4); - - // First output register - switch (MCInst_getOpcode(Inst)) { - case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8: - case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register: - case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register: - case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register: - case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register: - case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8: - case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register: - case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register: - case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register: - if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - - case ARM_VLD2b16: - case ARM_VLD2b32: - case ARM_VLD2b8: - case ARM_VLD2b16wb_fixed: - case ARM_VLD2b16wb_register: - case ARM_VLD2b32wb_fixed: - case ARM_VLD2b32wb_register: - case ARM_VLD2b8wb_fixed: - case ARM_VLD2b8wb_register: - if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - - default: - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - } - - // Second output register - switch (MCInst_getOpcode(Inst)) { - case ARM_VLD3d8: - case ARM_VLD3d16: - case ARM_VLD3d32: - case ARM_VLD3d8_UPD: - case ARM_VLD3d16_UPD: - case ARM_VLD3d32_UPD: - case ARM_VLD4d8: - case ARM_VLD4d16: - case ARM_VLD4d32: - case ARM_VLD4d8_UPD: - case ARM_VLD4d16_UPD: - case ARM_VLD4d32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - - case ARM_VLD3q8: - case ARM_VLD3q16: - case ARM_VLD3q32: - case ARM_VLD3q8_UPD: - case ARM_VLD3q16_UPD: - case ARM_VLD3q32_UPD: - case ARM_VLD4q8: - case ARM_VLD4q16: - case ARM_VLD4q32: - case ARM_VLD4q8_UPD: - case ARM_VLD4q16_UPD: - case ARM_VLD4q32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) - return MCDisassembler_Fail; - - default: - break; - } - - // Third output register - switch(MCInst_getOpcode(Inst)) { - case ARM_VLD3d8: - case ARM_VLD3d16: - case ARM_VLD3d32: - case ARM_VLD3d8_UPD: - case ARM_VLD3d16_UPD: - case ARM_VLD3d32_UPD: - case ARM_VLD4d8: - case ARM_VLD4d16: - case ARM_VLD4d32: - case ARM_VLD4d8_UPD: - case ARM_VLD4d16_UPD: - case ARM_VLD4d32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - case ARM_VLD3q8: - case ARM_VLD3q16: - case ARM_VLD3q32: - case ARM_VLD3q8_UPD: - case ARM_VLD3q16_UPD: - case ARM_VLD3q32_UPD: - case ARM_VLD4q8: - case ARM_VLD4q16: - case ARM_VLD4q32: - case ARM_VLD4q8_UPD: - case ARM_VLD4q16_UPD: - case ARM_VLD4q32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - // Fourth output register - switch (MCInst_getOpcode(Inst)) { - case ARM_VLD4d8: - case ARM_VLD4d16: - case ARM_VLD4d32: - case ARM_VLD4d8_UPD: - case ARM_VLD4d16_UPD: - case ARM_VLD4d32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - case ARM_VLD4q8: - case ARM_VLD4q16: - case ARM_VLD4q32: - case ARM_VLD4q8_UPD: - case ARM_VLD4q16_UPD: - case ARM_VLD4q32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - // Writeback operand - switch (MCInst_getOpcode(Inst)) { - case ARM_VLD1d8wb_fixed: - case ARM_VLD1d16wb_fixed: - case ARM_VLD1d32wb_fixed: - case ARM_VLD1d64wb_fixed: - case ARM_VLD1d8wb_register: - case ARM_VLD1d16wb_register: - case ARM_VLD1d32wb_register: - case ARM_VLD1d64wb_register: - case ARM_VLD1q8wb_fixed: - case ARM_VLD1q16wb_fixed: - case ARM_VLD1q32wb_fixed: - case ARM_VLD1q64wb_fixed: - case ARM_VLD1q8wb_register: - case ARM_VLD1q16wb_register: - case ARM_VLD1q32wb_register: - case ARM_VLD1q64wb_register: - case ARM_VLD1d8Twb_fixed: - case ARM_VLD1d8Twb_register: - case ARM_VLD1d16Twb_fixed: - case ARM_VLD1d16Twb_register: - case ARM_VLD1d32Twb_fixed: - case ARM_VLD1d32Twb_register: - case ARM_VLD1d64Twb_fixed: - case ARM_VLD1d64Twb_register: - case ARM_VLD1d8Qwb_fixed: - case ARM_VLD1d8Qwb_register: - case ARM_VLD1d16Qwb_fixed: - case ARM_VLD1d16Qwb_register: - case ARM_VLD1d32Qwb_fixed: - case ARM_VLD1d32Qwb_register: - case ARM_VLD1d64Qwb_fixed: - case ARM_VLD1d64Qwb_register: - case ARM_VLD2d8wb_fixed: - case ARM_VLD2d16wb_fixed: - case ARM_VLD2d32wb_fixed: - case ARM_VLD2q8wb_fixed: - case ARM_VLD2q16wb_fixed: - case ARM_VLD2q32wb_fixed: - case ARM_VLD2d8wb_register: - case ARM_VLD2d16wb_register: - case ARM_VLD2d32wb_register: - case ARM_VLD2q8wb_register: - case ARM_VLD2q16wb_register: - case ARM_VLD2q32wb_register: - case ARM_VLD2b8wb_fixed: - case ARM_VLD2b16wb_fixed: - case ARM_VLD2b32wb_fixed: - case ARM_VLD2b8wb_register: - case ARM_VLD2b16wb_register: - case ARM_VLD2b32wb_register: - MCOperand_CreateImm0(Inst, 0); - break; - - case ARM_VLD3d8_UPD: - case ARM_VLD3d16_UPD: - case ARM_VLD3d32_UPD: - case ARM_VLD3q8_UPD: - case ARM_VLD3q16_UPD: - case ARM_VLD3q32_UPD: - case ARM_VLD4d8_UPD: - case ARM_VLD4d16_UPD: - case ARM_VLD4d32_UPD: - case ARM_VLD4q8_UPD: - case ARM_VLD4q16_UPD: - case ARM_VLD4q32_UPD: - if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) - return MCDisassembler_Fail; - break; - - default: - break; - } - - // AddrMode6 Base (register+alignment) - if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - // AddrMode6 Offset (register) - switch (MCInst_getOpcode(Inst)) { - default: - // The below have been updated to have explicit am6offset split - // between fixed and register offset. For those instructions not - // yet updated, we need to add an additional reg0 operand for the - // fixed variant. - // - // The fixed offset encodes as Rm == 0xd, so we check for that. - if (Rm == 0xd) { - MCOperand_CreateReg0(Inst, 0); - break; - } - // Fall through to handle the register offset variant. - - case ARM_VLD1d8wb_fixed: - case ARM_VLD1d16wb_fixed: - case ARM_VLD1d32wb_fixed: - case ARM_VLD1d64wb_fixed: - case ARM_VLD1d8Twb_fixed: - case ARM_VLD1d16Twb_fixed: - case ARM_VLD1d32Twb_fixed: - case ARM_VLD1d64Twb_fixed: - case ARM_VLD1d8Qwb_fixed: - case ARM_VLD1d16Qwb_fixed: - case ARM_VLD1d32Qwb_fixed: - case ARM_VLD1d64Qwb_fixed: - case ARM_VLD1d8wb_register: - case ARM_VLD1d16wb_register: - case ARM_VLD1d32wb_register: - case ARM_VLD1d64wb_register: - case ARM_VLD1q8wb_fixed: - case ARM_VLD1q16wb_fixed: - case ARM_VLD1q32wb_fixed: - case ARM_VLD1q64wb_fixed: - case ARM_VLD1q8wb_register: - case ARM_VLD1q16wb_register: - case ARM_VLD1q32wb_register: - case ARM_VLD1q64wb_register: - // The fixed offset post-increment encodes Rm == 0xd. The no-writeback - // variant encodes Rm == 0xf. Anything else is a register offset post- - // increment and we need to add the register operand to the instruction. - if (Rm != 0xD && Rm != 0xF && - !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - break; - - case ARM_VLD2d8wb_fixed: - case ARM_VLD2d16wb_fixed: - case ARM_VLD2d32wb_fixed: - case ARM_VLD2b8wb_fixed: - case ARM_VLD2b16wb_fixed: - case ARM_VLD2b32wb_fixed: - case ARM_VLD2q8wb_fixed: - case ARM_VLD2q16wb_fixed: - case ARM_VLD2q32wb_fixed: - break; - } - - return S; -} - -static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - unsigned load; - unsigned type = fieldFromInstruction_4(Insn, 8, 4); - unsigned align = fieldFromInstruction_4(Insn, 4, 2); - if (type == 6 && (align & 2)) return MCDisassembler_Fail; - if (type == 7 && (align & 2)) return MCDisassembler_Fail; - if (type == 10 && align == 3) return MCDisassembler_Fail; - - load = fieldFromInstruction_4(Insn, 21, 1); - - return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) - : DecodeVSTInstruction(Inst, Insn, Address, Decoder); -} - -static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - unsigned type, align, load; - unsigned size = fieldFromInstruction_4(Insn, 6, 2); - if (size == 3) return MCDisassembler_Fail; - - type = fieldFromInstruction_4(Insn, 8, 4); - align = fieldFromInstruction_4(Insn, 4, 2); - if (type == 8 && align == 3) return MCDisassembler_Fail; - if (type == 9 && align == 3) return MCDisassembler_Fail; - - load = fieldFromInstruction_4(Insn, 21, 1); - - return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) - : DecodeVSTInstruction(Inst, Insn, Address, Decoder); -} - -static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - unsigned align, load; - unsigned size = fieldFromInstruction_4(Insn, 6, 2); - if (size == 3) return MCDisassembler_Fail; - - align = fieldFromInstruction_4(Insn, 4, 2); - if (align & 2) return MCDisassembler_Fail; - - load = fieldFromInstruction_4(Insn, 21, 1); - - return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) - : DecodeVSTInstruction(Inst, Insn, Address, Decoder); -} - -static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - unsigned load; - unsigned size = fieldFromInstruction_4(Insn, 6, 2); - if (size == 3) return MCDisassembler_Fail; - - load = fieldFromInstruction_4(Insn, 21, 1); - - return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) - : DecodeVSTInstruction(Inst, Insn, Address, Decoder); -} - -static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned wb, Rn, Rm; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - wb = fieldFromInstruction_4(Insn, 16, 4); - Rn = fieldFromInstruction_4(Insn, 16, 4); - Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; - Rm = fieldFromInstruction_4(Insn, 0, 4); - - // Writeback Operand - switch (MCInst_getOpcode(Inst)) { - case ARM_VST1d8wb_fixed: - case ARM_VST1d16wb_fixed: - case ARM_VST1d32wb_fixed: - case ARM_VST1d64wb_fixed: - case ARM_VST1d8wb_register: - case ARM_VST1d16wb_register: - case ARM_VST1d32wb_register: - case ARM_VST1d64wb_register: - case ARM_VST1q8wb_fixed: - case ARM_VST1q16wb_fixed: - case ARM_VST1q32wb_fixed: - case ARM_VST1q64wb_fixed: - case ARM_VST1q8wb_register: - case ARM_VST1q16wb_register: - case ARM_VST1q32wb_register: - case ARM_VST1q64wb_register: - case ARM_VST1d8Twb_fixed: - case ARM_VST1d16Twb_fixed: - case ARM_VST1d32Twb_fixed: - case ARM_VST1d64Twb_fixed: - case ARM_VST1d8Twb_register: - case ARM_VST1d16Twb_register: - case ARM_VST1d32Twb_register: - case ARM_VST1d64Twb_register: - case ARM_VST1d8Qwb_fixed: - case ARM_VST1d16Qwb_fixed: - case ARM_VST1d32Qwb_fixed: - case ARM_VST1d64Qwb_fixed: - case ARM_VST1d8Qwb_register: - case ARM_VST1d16Qwb_register: - case ARM_VST1d32Qwb_register: - case ARM_VST1d64Qwb_register: - case ARM_VST2d8wb_fixed: - case ARM_VST2d16wb_fixed: - case ARM_VST2d32wb_fixed: - case ARM_VST2d8wb_register: - case ARM_VST2d16wb_register: - case ARM_VST2d32wb_register: - case ARM_VST2q8wb_fixed: - case ARM_VST2q16wb_fixed: - case ARM_VST2q32wb_fixed: - case ARM_VST2q8wb_register: - case ARM_VST2q16wb_register: - case ARM_VST2q32wb_register: - case ARM_VST2b8wb_fixed: - case ARM_VST2b16wb_fixed: - case ARM_VST2b32wb_fixed: - case ARM_VST2b8wb_register: - case ARM_VST2b16wb_register: - case ARM_VST2b32wb_register: - if (Rm == 0xF) - return MCDisassembler_Fail; - MCOperand_CreateImm0(Inst, 0); - break; - case ARM_VST3d8_UPD: - case ARM_VST3d16_UPD: - case ARM_VST3d32_UPD: - case ARM_VST3q8_UPD: - case ARM_VST3q16_UPD: - case ARM_VST3q32_UPD: - case ARM_VST4d8_UPD: - case ARM_VST4d16_UPD: - case ARM_VST4d32_UPD: - case ARM_VST4q8_UPD: - case ARM_VST4q16_UPD: - case ARM_VST4q32_UPD: - if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - // AddrMode6 Base (register+alignment) - if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - // AddrMode6 Offset (register) - switch (MCInst_getOpcode(Inst)) { - default: - if (Rm == 0xD) - MCOperand_CreateReg0(Inst, 0); - else if (Rm != 0xF) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } - break; - - case ARM_VST1d8wb_fixed: - case ARM_VST1d16wb_fixed: - case ARM_VST1d32wb_fixed: - case ARM_VST1d64wb_fixed: - case ARM_VST1q8wb_fixed: - case ARM_VST1q16wb_fixed: - case ARM_VST1q32wb_fixed: - case ARM_VST1q64wb_fixed: - case ARM_VST1d8Twb_fixed: - case ARM_VST1d16Twb_fixed: - case ARM_VST1d32Twb_fixed: - case ARM_VST1d64Twb_fixed: - case ARM_VST1d8Qwb_fixed: - case ARM_VST1d16Qwb_fixed: - case ARM_VST1d32Qwb_fixed: - case ARM_VST1d64Qwb_fixed: - case ARM_VST2d8wb_fixed: - case ARM_VST2d16wb_fixed: - case ARM_VST2d32wb_fixed: - case ARM_VST2q8wb_fixed: - case ARM_VST2q16wb_fixed: - case ARM_VST2q32wb_fixed: - case ARM_VST2b8wb_fixed: - case ARM_VST2b16wb_fixed: - case ARM_VST2b32wb_fixed: - break; - } - - - // First input register - switch (MCInst_getOpcode(Inst)) { - case ARM_VST1q16: - case ARM_VST1q32: - case ARM_VST1q64: - case ARM_VST1q8: - case ARM_VST1q16wb_fixed: - case ARM_VST1q16wb_register: - case ARM_VST1q32wb_fixed: - case ARM_VST1q32wb_register: - case ARM_VST1q64wb_fixed: - case ARM_VST1q64wb_register: - case ARM_VST1q8wb_fixed: - case ARM_VST1q8wb_register: - case ARM_VST2d16: - case ARM_VST2d32: - case ARM_VST2d8: - case ARM_VST2d16wb_fixed: - case ARM_VST2d16wb_register: - case ARM_VST2d32wb_fixed: - case ARM_VST2d32wb_register: - case ARM_VST2d8wb_fixed: - case ARM_VST2d8wb_register: - if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - - case ARM_VST2b16: - case ARM_VST2b32: - case ARM_VST2b8: - case ARM_VST2b16wb_fixed: - case ARM_VST2b16wb_register: - case ARM_VST2b32wb_fixed: - case ARM_VST2b32wb_register: - case ARM_VST2b8wb_fixed: - case ARM_VST2b8wb_register: - if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - - default: - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - } - - // Second input register - switch (MCInst_getOpcode(Inst)) { - case ARM_VST3d8: - case ARM_VST3d16: - case ARM_VST3d32: - case ARM_VST3d8_UPD: - case ARM_VST3d16_UPD: - case ARM_VST3d32_UPD: - case ARM_VST4d8: - case ARM_VST4d16: - case ARM_VST4d32: - case ARM_VST4d8_UPD: - case ARM_VST4d16_UPD: - case ARM_VST4d32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - - case ARM_VST3q8: - case ARM_VST3q16: - case ARM_VST3q32: - case ARM_VST3q8_UPD: - case ARM_VST3q16_UPD: - case ARM_VST3q32_UPD: - case ARM_VST4q8: - case ARM_VST4q16: - case ARM_VST4q32: - case ARM_VST4q8_UPD: - case ARM_VST4q16_UPD: - case ARM_VST4q32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - // Third input register - switch (MCInst_getOpcode(Inst)) { - case ARM_VST3d8: - case ARM_VST3d16: - case ARM_VST3d32: - case ARM_VST3d8_UPD: - case ARM_VST3d16_UPD: - case ARM_VST3d32_UPD: - case ARM_VST4d8: - case ARM_VST4d16: - case ARM_VST4d32: - case ARM_VST4d8_UPD: - case ARM_VST4d16_UPD: - case ARM_VST4d32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - - case ARM_VST3q8: - case ARM_VST3q16: - case ARM_VST3q32: - case ARM_VST3q8_UPD: - case ARM_VST3q16_UPD: - case ARM_VST3q32_UPD: - case ARM_VST4q8: - case ARM_VST4q16: - case ARM_VST4q32: - case ARM_VST4q8_UPD: - case ARM_VST4q16_UPD: - case ARM_VST4q32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - // Fourth input register - switch (MCInst_getOpcode(Inst)) { - case ARM_VST4d8: - case ARM_VST4d16: - case ARM_VST4d32: - case ARM_VST4d8_UPD: - case ARM_VST4d16_UPD: - case ARM_VST4d32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - - case ARM_VST4q8: - case ARM_VST4q16: - case ARM_VST4q32: - case ARM_VST4q8_UPD: - case ARM_VST4q16_UPD: - case ARM_VST4q32_UPD: - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - return S; -} - -static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn, Rm, align, size; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - Rn = fieldFromInstruction_4(Insn, 16, 4); - Rm = fieldFromInstruction_4(Insn, 0, 4); - align = fieldFromInstruction_4(Insn, 4, 1); - size = fieldFromInstruction_4(Insn, 6, 2); - - if (size == 0 && align == 1) - return MCDisassembler_Fail; - - align *= (1 << size); - - switch (MCInst_getOpcode(Inst)) { - case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8: - case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register: - case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register: - case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register: - if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - - default: - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - } - - if (Rm != 0xF) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - // The fixed offset post-increment encodes Rm == 0xd. The no-writeback - // variant encodes Rm == 0xf. Anything else is a register offset post- - // increment and we need to add the register operand to the instruction. - if (Rm != 0xD && Rm != 0xF && - !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn, Rm, align, size; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - Rn = fieldFromInstruction_4(Insn, 16, 4); - Rm = fieldFromInstruction_4(Insn, 0, 4); - align = fieldFromInstruction_4(Insn, 4, 1); - size = 1 << fieldFromInstruction_4(Insn, 6, 2); - align *= 2 * size; - - switch (MCInst_getOpcode(Inst)) { - case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8: - case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register: - case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register: - case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register: - if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - - case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2: - case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register: - case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register: - case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register: - if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - - default: - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - } - - if (Rm != 0xF) - MCOperand_CreateImm0(Inst, 0); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm != 0xD && Rm != 0xF) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } - - return S; -} - -static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn, Rm, inc; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - Rn = fieldFromInstruction_4(Insn, 16, 4); - Rm = fieldFromInstruction_4(Insn, 0, 4); - inc = fieldFromInstruction_4(Insn, 5, 1) + 1; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder))) - return MCDisassembler_Fail; - - if (Rm != 0xF) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, 0); - - if (Rm == 0xD) - MCOperand_CreateReg0(Inst, 0); - else if (Rm != 0xF) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } - - return S; -} - -static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn, Rm, size, inc, align; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - Rn = fieldFromInstruction_4(Insn, 16, 4); - Rm = fieldFromInstruction_4(Insn, 0, 4); - size = fieldFromInstruction_4(Insn, 6, 2); - inc = fieldFromInstruction_4(Insn, 5, 1) + 1; - align = fieldFromInstruction_4(Insn, 4, 1); - - if (size == 0x3) { - if (align == 0) - return MCDisassembler_Fail; - align = 16; - } else { - if (size == 2) { - align *= 8; - } else { - size = 1 << size; - align *= 4 * size; - } - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3*inc) % 32, Address, Decoder))) - return MCDisassembler_Fail; - - if (Rm != 0xF) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm == 0xD) - MCOperand_CreateReg0(Inst, 0); - else if (Rm != 0xF) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } - - return S; -} - -static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned imm, Q; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - imm = fieldFromInstruction_4(Insn, 0, 4); - imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; - imm |= fieldFromInstruction_4(Insn, 24, 1) << 7; - imm |= fieldFromInstruction_4(Insn, 8, 4) << 8; - imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; - Q = fieldFromInstruction_4(Insn, 6, 1); - - if (Q) { - if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - } else { - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - } - - MCOperand_CreateImm0(Inst, imm); - - switch (MCInst_getOpcode(Inst)) { - case ARM_VORRiv4i16: - case ARM_VORRiv2i32: - case ARM_VBICiv4i16: - case ARM_VBICiv2i32: - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - case ARM_VORRiv8i16: - case ARM_VORRiv4i32: - case ARM_VBICiv8i16: - case ARM_VBICiv4i32: - if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - break; - } - - return S; -} - -static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rm, size; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - Rm = fieldFromInstruction_4(Insn, 0, 4); - Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; - size = fieldFromInstruction_4(Insn, 18, 2); - - if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, 8 << size); - - return S; -} - -static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, 8 - Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, 16 - Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, 32 - Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, 64 - Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn, Rm, op; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - Rn = fieldFromInstruction_4(Insn, 16, 4); - Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; - Rm = fieldFromInstruction_4(Insn, 0, 4); - Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; - op = fieldFromInstruction_4(Insn, 6, 1); - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (op) { - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; // Writeback - } - - switch (MCInst_getOpcode(Inst)) { - case ARM_VTBL2: - case ARM_VTBX2: - if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - break; - default: - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned dst = fieldFromInstruction_2(Insn, 8, 3); - unsigned imm = fieldFromInstruction_2(Insn, 0, 8); - - if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) - return MCDisassembler_Fail; - - switch(MCInst_getOpcode(Inst)) { - default: - return MCDisassembler_Fail; - case ARM_tADR: - break; // tADR does not explicitly represent the PC as an operand. - case ARM_tADDrSPi: - MCOperand_CreateReg0(Inst, ARM_SP); - break; - } - - MCOperand_CreateImm0(Inst, imm); - - return S; -} - -static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Val, 21)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, Val << 1); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Val, 0, 3); - unsigned Rm = fieldFromInstruction_4(Val, 3, 3); - - if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Val, 0, 3); - unsigned imm = fieldFromInstruction_4(Val, 3, 5); - - if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, imm); - - return S; -} - -static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - unsigned imm = Val << 2; - - MCOperand_CreateImm0(Inst, imm); - //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateReg0(Inst, ARM_SP); - MCOperand_CreateImm0(Inst, Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Val, 6, 4); - unsigned Rm = fieldFromInstruction_4(Val, 2, 4); - unsigned imm = fieldFromInstruction_4(Val, 0, 2); - - // Thumb stores cannot use PC as dest register. - switch (MCInst_getOpcode(Inst)) { - case ARM_t2STRHs: - case ARM_t2STRBs: - case ARM_t2STRs: - if (Rn == 15) - return MCDisassembler_Fail; - default: - break; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, imm); - - return S; -} - -static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned addrmode; - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); - bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); - - if (Rn == 15) { - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDRBs: - MCInst_setOpcode(Inst, ARM_t2LDRBpci); - break; - case ARM_t2LDRHs: - MCInst_setOpcode(Inst, ARM_t2LDRHpci); - break; - case ARM_t2LDRSHs: - MCInst_setOpcode(Inst, ARM_t2LDRSHpci); - break; - case ARM_t2LDRSBs: - MCInst_setOpcode(Inst, ARM_t2LDRSBpci); - break; - case ARM_t2LDRs: - MCInst_setOpcode(Inst, ARM_t2LDRpci); - break; - case ARM_t2PLDs: - MCInst_setOpcode(Inst, ARM_t2PLDpci); - break; - case ARM_t2PLIs: - MCInst_setOpcode(Inst, ARM_t2PLIpci); - break; - default: - return MCDisassembler_Fail; - } - - return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); - } - - if (Rt == 15) { - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDRSHs: - return MCDisassembler_Fail; - case ARM_t2LDRHs: - MCInst_setOpcode(Inst, ARM_t2PLDWs); - break; - case ARM_t2LDRSBs: - MCInst_setOpcode(Inst, ARM_t2PLIs); - default: - break; - } - } - - switch (MCInst_getOpcode(Inst)) { - case ARM_t2PLDs: - break; - case ARM_t2PLIs: - if (!hasV7Ops) - return MCDisassembler_Fail; - break; - case ARM_t2PLDWs: - if (!hasV7Ops || !hasMP) - return MCDisassembler_Fail; - break; - default: - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - } - - addrmode = fieldFromInstruction_4(Insn, 4, 2); - addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2; - addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6; - - if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, - uint64_t Address, const void* Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned U = fieldFromInstruction_4(Insn, 9, 1); - unsigned imm = fieldFromInstruction_4(Insn, 0, 8); - unsigned add = fieldFromInstruction_4(Insn, 9, 1); - bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); - bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); - - imm |= (U << 8); - imm |= (Rn << 9); - - if (Rn == 15) { - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDRi8: - MCInst_setOpcode(Inst, ARM_t2LDRpci); - break; - case ARM_t2LDRBi8: - MCInst_setOpcode(Inst, ARM_t2LDRBpci); - break; - case ARM_t2LDRSBi8: - MCInst_setOpcode(Inst, ARM_t2LDRSBpci); - break; - case ARM_t2LDRHi8: - MCInst_setOpcode(Inst, ARM_t2LDRHpci); - break; - case ARM_t2LDRSHi8: - MCInst_setOpcode(Inst, ARM_t2LDRSHpci); - break; - case ARM_t2PLDi8: - MCInst_setOpcode(Inst, ARM_t2PLDpci); - break; - case ARM_t2PLIi8: - MCInst_setOpcode(Inst, ARM_t2PLIpci); - break; - default: - return MCDisassembler_Fail; - } - - return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); - } - - if (Rt == 15) { - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDRSHi8: - return MCDisassembler_Fail; - case ARM_t2LDRHi8: - if (!add) - MCInst_setOpcode(Inst, ARM_t2PLDWi8); - break; - case ARM_t2LDRSBi8: - MCInst_setOpcode(Inst, ARM_t2PLIi8); - break; - default: - break; - } - } - - switch (MCInst_getOpcode(Inst)) { - case ARM_t2PLDi8: - break; - case ARM_t2PLIi8: - if (!hasV7Ops) - return MCDisassembler_Fail; - break; - case ARM_t2PLDWi8: - if (!hasV7Ops || !hasMP) - return MCDisassembler_Fail; - break; - default: - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, - uint64_t Address, const void* Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned imm = fieldFromInstruction_4(Insn, 0, 12); - bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); - bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); - - imm |= (Rn << 13); - - if (Rn == 15) { - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDRi12: - MCInst_setOpcode(Inst, ARM_t2LDRpci); - break; - case ARM_t2LDRHi12: - MCInst_setOpcode(Inst, ARM_t2LDRHpci); - break; - case ARM_t2LDRSHi12: - MCInst_setOpcode(Inst, ARM_t2LDRSHpci); - break; - case ARM_t2LDRBi12: - MCInst_setOpcode(Inst, ARM_t2LDRBpci); - break; - case ARM_t2LDRSBi12: - MCInst_setOpcode(Inst, ARM_t2LDRSBpci); - break; - case ARM_t2PLDi12: - MCInst_setOpcode(Inst, ARM_t2PLDpci); - break; - case ARM_t2PLIi12: - MCInst_setOpcode(Inst, ARM_t2PLIpci); - break; - default: - return MCDisassembler_Fail; - } - return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); - } - - if (Rt == 15) { - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDRSHi12: - return MCDisassembler_Fail; - case ARM_t2LDRHi12: - MCInst_setOpcode(Inst, ARM_t2PLDWi12); - break; - case ARM_t2LDRSBi12: - MCInst_setOpcode(Inst, ARM_t2PLIi12); - break; - default: - break; - } - } - - switch (MCInst_getOpcode(Inst)) { - case ARM_t2PLDi12: - break; - case ARM_t2PLIi12: - if (!hasV7Ops) - return MCDisassembler_Fail; - break; - case ARM_t2PLDWi12: - if (!hasV7Ops || !hasMP) - return MCDisassembler_Fail; - break; - default: - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, - uint64_t Address, const void* Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned imm = fieldFromInstruction_4(Insn, 0, 8); - imm |= (Rn << 9); - - if (Rn == 15) { - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDRT: - MCInst_setOpcode(Inst, ARM_t2LDRpci); - break; - case ARM_t2LDRBT: - MCInst_setOpcode(Inst, ARM_t2LDRBpci); - break; - case ARM_t2LDRHT: - MCInst_setOpcode(Inst, ARM_t2LDRHpci); - break; - case ARM_t2LDRSBT: - MCInst_setOpcode(Inst, ARM_t2LDRSBpci); - break; - case ARM_t2LDRSHT: - MCInst_setOpcode(Inst, ARM_t2LDRSHpci); - break; - default: - return MCDisassembler_Fail; - } - - return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); - } - - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, - uint64_t Address, const void* Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned U = fieldFromInstruction_4(Insn, 23, 1); - int imm = fieldFromInstruction_4(Insn, 0, 12); - bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); - - if (Rt == 15) { - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDRBpci: - case ARM_t2LDRHpci: - MCInst_setOpcode(Inst, ARM_t2PLDpci); - break; - case ARM_t2LDRSBpci: - MCInst_setOpcode(Inst, ARM_t2PLIpci); - break; - case ARM_t2LDRSHpci: - return MCDisassembler_Fail; - default: - break; - } - } - - switch(MCInst_getOpcode(Inst)) { - case ARM_t2PLDpci: - break; - case ARM_t2PLIpci: - if (!hasV7Ops) - return MCDisassembler_Fail; - break; - default: - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!U) { - // Special case for #-0. - if (imm == 0) - imm = INT32_MIN; - else - imm = -imm; - } - - MCOperand_CreateImm0(Inst, imm); - - return S; -} - -static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - if (Val == 0) - MCOperand_CreateImm0(Inst, INT32_MIN); - else { - int imm = Val & 0xFF; - - if (!(Val & 0x100)) imm *= -1; - - MCOperand_CreateImm0(Inst, imm * 4); - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Val, 9, 4); - unsigned imm = fieldFromInstruction_4(Val, 0, 9); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Val, 8, 4); - unsigned imm = fieldFromInstruction_4(Val, 0, 8); - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, imm); - - return S; -} - -static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - int imm = Val & 0xFF; - - if (Val == 0) - imm = INT32_MIN; - else if (!(Val & 0x100)) - imm *= -1; - - MCOperand_CreateImm0(Inst, imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - unsigned Rn = fieldFromInstruction_4(Val, 9, 4); - unsigned imm = fieldFromInstruction_4(Val, 0, 9); - - // Thumb stores cannot use PC as dest register. - switch (MCInst_getOpcode(Inst)) { - case ARM_t2STRT: - case ARM_t2STRBT: - case ARM_t2STRHT: - case ARM_t2STRi8: - case ARM_t2STRHi8: - case ARM_t2STRBi8: - if (Rn == 15) - return MCDisassembler_Fail; - break; - default: - break; - } - - // Some instructions always use an additive offset. - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDRT: - case ARM_t2LDRBT: - case ARM_t2LDRHT: - case ARM_t2LDRSBT: - case ARM_t2LDRSHT: - case ARM_t2STRT: - case ARM_t2STRBT: - case ARM_t2STRHT: - imm |= 0x100; - break; - default: - break; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned load; - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned addr = fieldFromInstruction_4(Insn, 0, 8); - addr |= fieldFromInstruction_4(Insn, 9, 1) << 8; - addr |= Rn << 9; - load = fieldFromInstruction_4(Insn, 20, 1); - - if (Rn == 15) { - switch (MCInst_getOpcode(Inst)) { - case ARM_t2LDR_PRE: - case ARM_t2LDR_POST: - MCInst_setOpcode(Inst, ARM_t2LDRpci); - break; - case ARM_t2LDRB_PRE: - case ARM_t2LDRB_POST: - MCInst_setOpcode(Inst, ARM_t2LDRBpci); - break; - case ARM_t2LDRH_PRE: - case ARM_t2LDRH_POST: - MCInst_setOpcode(Inst, ARM_t2LDRHpci); - break; - case ARM_t2LDRSB_PRE: - case ARM_t2LDRSB_POST: - if (Rt == 15) - MCInst_setOpcode(Inst, ARM_t2PLIpci); - else - MCInst_setOpcode(Inst, ARM_t2LDRSBpci); - break; - case ARM_t2LDRSH_PRE: - case ARM_t2LDRSH_POST: - MCInst_setOpcode(Inst, ARM_t2LDRSHpci); - break; - default: - return MCDisassembler_Fail; - } - - return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); - } - - if (!load) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (load) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Val, 13, 4); - unsigned imm = fieldFromInstruction_4(Val, 0, 12); - - // Thumb stores cannot use PC as dest register. - switch (MCInst_getOpcode(Inst)) { - case ARM_t2STRi12: - case ARM_t2STRBi12: - case ARM_t2STRHi12: - if (Rn == 15) - return MCDisassembler_Fail; - default: - break; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, imm); - - return S; -} - -static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, - uint64_t Address, const void *Decoder) -{ - unsigned imm = fieldFromInstruction_2(Insn, 0, 7); - - MCOperand_CreateReg0(Inst, ARM_SP); - MCOperand_CreateReg0(Inst, ARM_SP); - MCOperand_CreateImm0(Inst, imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - if (MCInst_getOpcode(Inst) == ARM_tADDrSP) { - unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); - Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, ARM_SP); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) - return MCDisassembler_Fail; - } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { - unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); - - MCOperand_CreateReg0(Inst, ARM_SP); - MCOperand_CreateReg0(Inst, ARM_SP); - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } - - return S; -} - -static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, - uint64_t Address, const void *Decoder) -{ - unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2; - unsigned flags = fieldFromInstruction_2(Insn, 0, 3); - - MCOperand_CreateImm0(Inst, imod); - MCOperand_CreateImm0(Inst, flags); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned add = fieldFromInstruction_4(Insn, 4, 1); - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, add); - - return S; -} - -static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - // Val is passed in as S:J1:J2:imm10H:imm10L:'0' - // Note only one trailing zero not two. Also the J1 and J2 values are from - // the encoded instruction. So here change to I1 and I2 values via: - // I1 = NOT(J1 EOR S); - // I2 = NOT(J2 EOR S); - // and build the imm32 with two trailing zeros as documented: - // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); - unsigned S = (Val >> 23) & 1; - unsigned J1 = (Val >> 22) & 1; - unsigned J2 = (Val >> 21) & 1; - unsigned I1 = !(J1 ^ S); - unsigned I2 = !(J2 ^ S); - unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); - int imm32 = SignExtend32(tmp << 1, 25); - - MCOperand_CreateImm0(Inst, imm32); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - if (Val == 0xA || Val == 0xB) - return MCDisassembler_Fail; - - if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && !(Val == 14 || Val == 15)) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - - if (Rn == ARM_SP) S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned brtarget; - unsigned pred = fieldFromInstruction_4(Insn, 22, 4); - - if (pred == 0xE || pred == 0xF) { - unsigned imm; - unsigned opc = fieldFromInstruction_4(Insn, 4, 28); - switch (opc) { - default: - return MCDisassembler_Fail; - case 0xf3bf8f4: - MCInst_setOpcode(Inst, ARM_t2DSB); - break; - case 0xf3bf8f5: - MCInst_setOpcode(Inst, ARM_t2DMB); - break; - case 0xf3bf8f6: - MCInst_setOpcode(Inst, ARM_t2ISB); - break; - } - - imm = fieldFromInstruction_4(Insn, 0, 4); - return DecodeMemBarrierOption(Inst, imm, Address, Decoder); - } - - brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1; - brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19; - brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18; - brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12; - brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20; - - if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -// Decode a shifted immediate operand. These basically consist -// of an 8-bit value, and a 4-bit directive that specifies either -// a splat operation or a rotation. -static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - unsigned ctrl = fieldFromInstruction_4(Val, 10, 2); - - if (ctrl == 0) { - unsigned byte = fieldFromInstruction_4(Val, 8, 2); - unsigned imm = fieldFromInstruction_4(Val, 0, 8); - - switch (byte) { - case 0: - MCOperand_CreateImm0(Inst, imm); - break; - case 1: - MCOperand_CreateImm0(Inst, (imm << 16) | imm); - break; - case 2: - MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8)); - break; - case 3: - MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm); - break; - } - } else { - unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; - unsigned rot = fieldFromInstruction_4(Val, 7, 5); - unsigned imm = (unrot >> rot) | (unrot << ((32 - rot) & 31)); - - MCOperand_CreateImm0(Inst, imm); - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - // Val is passed in as S:J1:J2:imm10:imm11 - // Note no trailing zero after imm11. Also the J1 and J2 values are from - // the encoded instruction. So here change to I1 and I2 values via: - // I1 = NOT(J1 EOR S); - // I2 = NOT(J2 EOR S); - // and build the imm32 with one trailing zero as documented: - // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); - unsigned S = (Val >> 23) & 1; - unsigned J1 = (Val >> 22) & 1; - unsigned J2 = (Val >> 21) & 1; - unsigned I1 = !(J1 ^ S); - unsigned I2 = !(J2 ^ S); - unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); - int imm32 = SignExtend32(tmp << 1, 25); - - MCOperand_CreateImm0(Inst, imm32); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - if (Val & ~0xf) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - if (Val & ~0xf) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - - if (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass)) { - unsigned ValLow = Val & 0xff; - - // Validate the SYSm value first. - switch (ValLow) { - case 0: // apsr - case 1: // iapsr - case 2: // eapsr - case 3: // xpsr - case 5: // ipsr - case 6: // epsr - case 7: // iepsr - case 8: // msp - case 9: // psp - case 16: // primask - case 20: // control - break; - case 17: // basepri - case 18: // basepri_max - case 19: // faultmask - if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)) - // Values basepri, basepri_max and faultmask are only valid for v7m. - return MCDisassembler_Fail; - break; - case 0x8a: // msplim_ns - case 0x8b: // psplim_ns - case 0x91: // basepri_ns - case 0x93: // faultmask_ns - if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8MMainlineOps)) - return MCDisassembler_Fail; - // LLVM_FALLTHROUGH; - case 10: // msplim - case 11: // psplim - case 0x88: // msp_ns - case 0x89: // psp_ns - case 0x90: // primask_ns - case 0x94: // control_ns - case 0x98: // sp_ns - if (!ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt)) - return MCDisassembler_Fail; - break; - default: - return MCDisassembler_SoftFail; - } - - if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) { - unsigned Mask = fieldFromInstruction_4(Val, 10, 2); - if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)) { - // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are - // unpredictable. - if (Mask != 2) - S = MCDisassembler_SoftFail; - } else { - // The ARMv7-M architecture stores an additional 2-bit mask value in - // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and - // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if - // the NZCVQ bits should be moved by the instruction. Bit mask{0} - // indicates the move for the GE{3:0} bits, the mask{0} bit can be set - // only if the processor includes the DSP extension. - if (Mask == 0 || (Mask != 2 && ValLow > 3) || - (!ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP) && (Mask & 1))) - S = MCDisassembler_SoftFail; - } - } - } else { - // A/R class - if (Val == 0) - return MCDisassembler_Fail; - } - - MCOperand_CreateImm0(Inst, Val); - return S; -} - -static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - unsigned R = fieldFromInstruction_4(Val, 5, 1); - unsigned SysM = fieldFromInstruction_4(Val, 0, 5); - - // The table of encodings for these banked registers comes from B9.2.3 of the - // ARM ARM. There are patterns, but nothing regular enough to make this logic - // neater. So by fiat, these values are UNPREDICTABLE: - if (!lookupBankedRegByEncoding((R << 5) | SysM)) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - - if (Rn == 0xF) - S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt + 1) - S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned pred; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned imm = fieldFromInstruction_4(Insn, 0, 12); - imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; - imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; - pred = fieldFromInstruction_4(Insn, 28, 4); - - if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned pred, Rm; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned imm = fieldFromInstruction_4(Insn, 0, 12); - imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; - imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; - pred = fieldFromInstruction_4(Insn, 28, 4); - Rm = fieldFromInstruction_4(Insn, 0, 4); - - if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; - if (Rm == 0xF) S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned pred; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned imm = fieldFromInstruction_4(Insn, 0, 12); - imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; - imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; - pred = fieldFromInstruction_4(Insn, 28, 4); - - if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned pred; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned imm = fieldFromInstruction_4(Insn, 0, 12); - imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; - imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; - pred = fieldFromInstruction_4(Insn, 28, 4); - - if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned size, align = 0, index = 0; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - size = fieldFromInstruction_4(Insn, 10, 2); - - switch (size) { - default: - return MCDisassembler_Fail; - case 0: - if (fieldFromInstruction_4(Insn, 4, 1)) - return MCDisassembler_Fail; // UNDEFINED - index = fieldFromInstruction_4(Insn, 5, 3); - break; - case 1: - if (fieldFromInstruction_4(Insn, 5, 1)) - return MCDisassembler_Fail; // UNDEFINED - index = fieldFromInstruction_4(Insn, 6, 2); - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 2; - break; - case 2: - if (fieldFromInstruction_4(Insn, 6, 1)) - return MCDisassembler_Fail; // UNDEFINED - - index = fieldFromInstruction_4(Insn, 7, 1); - - switch (fieldFromInstruction_4(Insn, 4, 2)) { - case 0 : - align = 0; break; - case 3: - align = 4; break; - default: - return MCDisassembler_Fail; - } - break; - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (Rm != 0xF) { // Writeback - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm != 0xF) { - if (Rm != 0xD) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } else - MCOperand_CreateReg0(Inst, 0); - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, index); - - return S; -} - -static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned size, align = 0, index = 0; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - size = fieldFromInstruction_4(Insn, 10, 2); - - switch (size) { - default: - return MCDisassembler_Fail; - case 0: - if (fieldFromInstruction_4(Insn, 4, 1)) - return MCDisassembler_Fail; // UNDEFINED - - index = fieldFromInstruction_4(Insn, 5, 3); - break; - case 1: - if (fieldFromInstruction_4(Insn, 5, 1)) - return MCDisassembler_Fail; // UNDEFINED - - index = fieldFromInstruction_4(Insn, 6, 2); - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 2; - break; - case 2: - if (fieldFromInstruction_4(Insn, 6, 1)) - return MCDisassembler_Fail; // UNDEFINED - - index = fieldFromInstruction_4(Insn, 7, 1); - - switch (fieldFromInstruction_4(Insn, 4, 2)) { - case 0: - align = 0; break; - case 3: - align = 4; break; - default: - return MCDisassembler_Fail; - } - break; - } - - if (Rm != 0xF) { // Writeback - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm != 0xF) { - if (Rm != 0xD) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } else - MCOperand_CreateReg0(Inst, 0); - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, index); - - return S; -} - -static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned size, align = 0, index = 0, inc = 1; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - size = fieldFromInstruction_4(Insn, 10, 2); - - switch (size) { - default: - return MCDisassembler_Fail; - case 0: - index = fieldFromInstruction_4(Insn, 5, 3); - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 2; - break; - case 1: - index = fieldFromInstruction_4(Insn, 6, 2); - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 4; - if (fieldFromInstruction_4(Insn, 5, 1)) - inc = 2; - break; - case 2: - if (fieldFromInstruction_4(Insn, 5, 1)) - return MCDisassembler_Fail; // UNDEFINED - - index = fieldFromInstruction_4(Insn, 7, 1); - if (fieldFromInstruction_4(Insn, 4, 1) != 0) - align = 8; - if (fieldFromInstruction_4(Insn, 6, 1)) - inc = 2; - break; - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (Rm != 0xF) { // Writeback - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm != 0xF) { - if (Rm != 0xD) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } else - MCOperand_CreateReg0(Inst, 0); - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, index); - - return S; -} - -static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned size, align = 0, index = 0, inc = 1; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - size = fieldFromInstruction_4(Insn, 10, 2); - - switch (size) { - default: - return MCDisassembler_Fail; - case 0: - index = fieldFromInstruction_4(Insn, 5, 3); - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 2; - break; - case 1: - index = fieldFromInstruction_4(Insn, 6, 2); - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 4; - if (fieldFromInstruction_4(Insn, 5, 1)) - inc = 2; - break; - case 2: - if (fieldFromInstruction_4(Insn, 5, 1)) - return MCDisassembler_Fail; // UNDEFINED - - index = fieldFromInstruction_4(Insn, 7, 1); - if (fieldFromInstruction_4(Insn, 4, 1) != 0) - align = 8; - if (fieldFromInstruction_4(Insn, 6, 1)) - inc = 2; - break; - } - - if (Rm != 0xF) { // Writeback - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm != 0xF) { - if (Rm != 0xD) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } else - MCOperand_CreateReg0(Inst, 0); - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, index); - - return S; -} - -static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned size, align = 0, index = 0, inc = 1; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - size = fieldFromInstruction_4(Insn, 10, 2); - - switch (size) { - default: - return MCDisassembler_Fail; - case 0: - if (fieldFromInstruction_4(Insn, 4, 1)) - return MCDisassembler_Fail; // UNDEFINED - index = fieldFromInstruction_4(Insn, 5, 3); - break; - case 1: - if (fieldFromInstruction_4(Insn, 4, 1)) - return MCDisassembler_Fail; // UNDEFINED - index = fieldFromInstruction_4(Insn, 6, 2); - if (fieldFromInstruction_4(Insn, 5, 1)) - inc = 2; - break; - case 2: - if (fieldFromInstruction_4(Insn, 4, 2)) - return MCDisassembler_Fail; // UNDEFINED - index = fieldFromInstruction_4(Insn, 7, 1); - if (fieldFromInstruction_4(Insn, 6, 1)) - inc = 2; - break; - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) - return MCDisassembler_Fail; - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (Rm != 0xF) { // Writeback - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm != 0xF) { - if (Rm != 0xD) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } else - MCOperand_CreateReg0(Inst, 0); - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, index); - - return S; -} - -static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned size, align = 0, index = 0, inc = 1; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - size = fieldFromInstruction_4(Insn, 10, 2); - - switch (size) { - default: - return MCDisassembler_Fail; - case 0: - if (fieldFromInstruction_4(Insn, 4, 1)) - return MCDisassembler_Fail; // UNDEFINED - index = fieldFromInstruction_4(Insn, 5, 3); - break; - case 1: - if (fieldFromInstruction_4(Insn, 4, 1)) - return MCDisassembler_Fail; // UNDEFINED - index = fieldFromInstruction_4(Insn, 6, 2); - if (fieldFromInstruction_4(Insn, 5, 1)) - inc = 2; - break; - case 2: - if (fieldFromInstruction_4(Insn, 4, 2)) - return MCDisassembler_Fail; // UNDEFINED - index = fieldFromInstruction_4(Insn, 7, 1); - if (fieldFromInstruction_4(Insn, 6, 1)) - inc = 2; - break; - } - - if (Rm != 0xF) { // Writeback - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm != 0xF) { - if (Rm != 0xD) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } else - MCOperand_CreateReg0(Inst, 0); - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, index); - - return S; -} - -static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned size, align = 0, index = 0, inc = 1; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - size = fieldFromInstruction_4(Insn, 10, 2); - - switch (size) { - default: - return MCDisassembler_Fail; - case 0: - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 4; - index = fieldFromInstruction_4(Insn, 5, 3); - break; - case 1: - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 8; - index = fieldFromInstruction_4(Insn, 6, 2); - if (fieldFromInstruction_4(Insn, 5, 1)) - inc = 2; - break; - case 2: - switch (fieldFromInstruction_4(Insn, 4, 2)) { - case 0: - align = 0; break; - case 3: - return MCDisassembler_Fail; - default: - align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; - } - - index = fieldFromInstruction_4(Insn, 7, 1); - if (fieldFromInstruction_4(Insn, 6, 1)) - inc = 2; - break; - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (Rm != 0xF) { // Writeback - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm != 0xF) { - if (Rm != 0xD) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } else - MCOperand_CreateReg0(Inst, 0); - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, index); - - return S; -} - -static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned size, align = 0, index = 0, inc = 1; - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); - Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; - size = fieldFromInstruction_4(Insn, 10, 2); - - switch (size) { - default: - return MCDisassembler_Fail; - case 0: - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 4; - index = fieldFromInstruction_4(Insn, 5, 3); - break; - case 1: - if (fieldFromInstruction_4(Insn, 4, 1)) - align = 8; - index = fieldFromInstruction_4(Insn, 6, 2); - if (fieldFromInstruction_4(Insn, 5, 1)) - inc = 2; - break; - case 2: - switch (fieldFromInstruction_4(Insn, 4, 2)) { - case 0: - align = 0; break; - case 3: - return MCDisassembler_Fail; - default: - align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; - } - - index = fieldFromInstruction_4(Insn, 7, 1); - if (fieldFromInstruction_4(Insn, 6, 1)) - inc = 2; - break; - } - - if (Rm != 0xF) { // Writeback - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, align); - - if (Rm != 0xF) { - if (Rm != 0xD) { - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - } else - MCOperand_CreateReg0(Inst, 0); - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, index); - - return S; -} - -static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; - - if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) - S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); - unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; - - if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) - S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned pred = fieldFromInstruction_4(Insn, 4, 4); - unsigned mask = fieldFromInstruction_4(Insn, 0, 4); - - if (pred == 0xF) { - pred = 0xE; - S = MCDisassembler_SoftFail; - } - - if (mask == 0x0) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, pred); - MCOperand_CreateImm0(Inst, mask); - - return S; -} - -static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned addr = fieldFromInstruction_4(Insn, 0, 8); - unsigned W = fieldFromInstruction_4(Insn, 21, 1); - unsigned U = fieldFromInstruction_4(Insn, 23, 1); - unsigned P = fieldFromInstruction_4(Insn, 24, 1); - bool writeback = (W == 1) | (P == 0); - - addr |= (U << 8) | (Rn << 9); - - if (writeback && (Rn == Rt || Rn == Rt2)) - Check(&S, MCDisassembler_SoftFail); - - if (Rt == Rt2) - Check(&S, MCDisassembler_SoftFail); - - // Rt - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - // Rt2 - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) - return MCDisassembler_Fail; - - // Writeback operand - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - // addr - if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned addr = fieldFromInstruction_4(Insn, 0, 8); - unsigned W = fieldFromInstruction_4(Insn, 21, 1); - unsigned U = fieldFromInstruction_4(Insn, 23, 1); - unsigned P = fieldFromInstruction_4(Insn, 24, 1); - bool writeback = (W == 1) | (P == 0); - - addr |= (U << 8) | (Rn << 9); - - if (writeback && (Rn == Rt || Rn == Rt2)) - Check(&S, MCDisassembler_SoftFail); - - // Writeback operand - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - // Rt - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - // Rt2 - if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) - return MCDisassembler_Fail; - - // addr - if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, - uint64_t Address, const void *Decoder) -{ - unsigned Val; - unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); - unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); - - if (sign1 != sign2) return MCDisassembler_Fail; - - Val = fieldFromInstruction_4(Insn, 0, 8); - Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; - Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; - Val |= sign1 << 12; - - MCOperand_CreateImm0(Inst, SignExtend32(Val, 13)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, - uint64_t Address, const void *Decoder) -{ - // Shift of "asr #32" is not allowed in Thumb2 mode. - if (Val == 0x20) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, Val); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S; - unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); - unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); - unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); - unsigned pred = fieldFromInstruction_4(Insn, 28, 4); - - if (pred == 0xF) - return DecodeCPSInstruction(Inst, Insn, Address, Decoder); - - S = MCDisassembler_Success; - - if (Rt == Rn || Rn == Rt2) - S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); - unsigned Vm, imm, cmode, op; - unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); - - Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); - Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); - Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); - imm = fieldFromInstruction_4(Insn, 16, 6); - cmode = fieldFromInstruction_4(Insn, 8, 4); - op = fieldFromInstruction_4(Insn, 5, 1); - - // If the top 3 bits of imm are clear, this is a VMOV (immediate) - if (!(imm & 0x38)) { - if (cmode == 0xF) { - if (op == 1) return MCDisassembler_Fail; - MCInst_setOpcode(Inst, ARM_VMOVv2f32); - } - - if (hasFullFP16) { - if (cmode == 0xE) { - if (op == 1) { - MCInst_setOpcode(Inst, ARM_VMOVv1i64); - } else { - MCInst_setOpcode(Inst, ARM_VMOVv8i8); - } - } - - if (cmode == 0xD) { - if (op == 1) { - MCInst_setOpcode(Inst, ARM_VMVNv2i32); - } else { - MCInst_setOpcode(Inst, ARM_VMOVv2i32); - } - } - - if (cmode == 0xC) { - if (op == 1) { - MCInst_setOpcode(Inst, ARM_VMVNv2i32); - } else { - MCInst_setOpcode(Inst, ARM_VMOVv2i32); - } - } - } - - return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); - } - - if (!(imm & 0x20)) return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, 64 - imm); - - return S; -} - -static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); - unsigned Vm, imm, cmode, op; - unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); - - Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); - Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); - Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); - imm = fieldFromInstruction_4(Insn, 16, 6); - cmode = fieldFromInstruction_4(Insn, 8, 4); - op = fieldFromInstruction_4(Insn, 5, 1); - - // VMOVv4f32 is ambiguous with these decodings. - if (!(imm & 0x38) && cmode == 0xF) { - if (op == 1) return MCDisassembler_Fail; - MCInst_setOpcode(Inst, ARM_VMOVv4f32); - return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); - } - - // If the top 3 bits of imm are clear, this is a VMOV (immediate) - if (!(imm & 0x38)) { - if (cmode == 0xF) { - if (op == 1) return MCDisassembler_Fail; - MCInst_setOpcode(Inst, ARM_VMOVv4f32); - } - - if (hasFullFP16) { - if (cmode == 0xE) { - if (op == 1) { - MCInst_setOpcode(Inst, ARM_VMOVv2i64); - } else { - MCInst_setOpcode(Inst, ARM_VMOVv16i8); - } - } - - if (cmode == 0xD) { - if (op == 1) { - MCInst_setOpcode(Inst, ARM_VMVNv4i32); - } else { - MCInst_setOpcode(Inst, ARM_VMOVv4i32); - } - } - - if (cmode == 0xC) { - if (op == 1) { - MCInst_setOpcode(Inst, ARM_VMVNv4i32); - } else { - MCInst_setOpcode(Inst, ARM_VMOVv4i32); - } - } - } - - return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); - } - - if (!(imm & 0x20)) return MCDisassembler_Fail; - - if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, 64 - imm); - - return S; -} - -static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); - unsigned Vn = (fieldFromInstruction_4(Insn, 16, 4) << 0); - unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); - unsigned q = (fieldFromInstruction_4(Insn, 6, 1) << 0); - unsigned rotate = (fieldFromInstruction_4(Insn, 20, 2) << 0); - - Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); - Vn |= (fieldFromInstruction_4(Insn, 7, 1) << 4); - Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); - - if (q) { - if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeQPRRegisterClass(Inst, Vn, Address, Decoder))) - return MCDisassembler_Fail; - } else { - if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Vn, Address, Decoder))) - return MCDisassembler_Fail; - } - - if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) - return MCDisassembler_Fail; - - // The lane index does not have any bits in the encoding, because it can only - // be 0. - MCOperand_CreateImm0(Inst, 0); - MCOperand_CreateImm0(Inst, rotate); - - return S; -} - -static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus S = MCDisassembler_Success; - unsigned Cond; - unsigned Rn = fieldFromInstruction_4(Val, 16, 4); - unsigned Rt = fieldFromInstruction_4(Val, 12, 4); - unsigned Rm = fieldFromInstruction_4(Val, 0, 4); - - Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4); - Cond = fieldFromInstruction_4(Val, 28, 4); - - if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt) - S = MCDisassembler_SoftFail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) - return MCDisassembler_Fail; - - return S; -} - -static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus result = MCDisassembler_Success; - unsigned CRm = fieldFromInstruction_4(Val, 0, 4); - unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); - unsigned cop = fieldFromInstruction_4(Val, 8, 4); - unsigned Rt = fieldFromInstruction_4(Val, 12, 4); - unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); - - if ((cop & ~0x1) == 0xa) - return MCDisassembler_Fail; - - if (Rt == Rt2) - result = MCDisassembler_SoftFail; - - // We have to check if the instruction is MRRC2 - // or MCRR2 when constructing the operands for - // Inst. Reason is because MRRC2 stores to two - // registers so it's tablegen desc has has two - // outputs whereas MCRR doesn't store to any - // registers so all of it's operands are listed - // as inputs, therefore the operand order for - // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] - // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] - - if (MCInst_getOpcode(Inst) == ARM_MRRC2) { - if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) - return MCDisassembler_Fail; - } - - MCOperand_CreateImm0(Inst, cop); - MCOperand_CreateImm0(Inst, opc1); - - if (MCInst_getOpcode(Inst) == ARM_MCRR2) { - if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler_Fail; - - if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) - return MCDisassembler_Fail; - } - - MCOperand_CreateImm0(Inst, CRm); - - return result; -} - -static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - DecodeStatus result = MCDisassembler_Success; - bool HasV8Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops); - unsigned Rt = fieldFromInstruction_4(Val, 12, 4); - - if ((Inst->csh->mode & CS_MODE_THUMB) && !HasV8Ops) { - if (Rt == 13 || Rt == 15) - result = MCDisassembler_SoftFail; - - Check(&result, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); - } else - Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); - - if (Inst->csh->mode & CS_MODE_THUMB) { - MCOperand_CreateImm0(Inst, ARMCC_AL); - MCOperand_CreateReg0(Inst, 0); - } else { - unsigned pred = fieldFromInstruction_4(Val, 28, 4); - if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder))) - return MCDisassembler_Fail; - } - - return result; +static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI) { + unsigned CC; + unsigned short NumOps; + const MCOperandInfo *OpInfo; + unsigned i; + + CC = ITStatus_getITCC(&(ud->ITBlock)); + if (ITStatus_instrInITBlock(&(ud->ITBlock))) + ITStatus_advanceITState(&(ud->ITBlock)); + + OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; + NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; + + for (i = 0; i < NumOps; ++i) { + if (MCOperandInfo_isPredicate(&OpInfo[i])) { + MCOperand_setImm(MCInst_getOperand(MI, i), CC); + + if (CC == ARMCC_AL) + MCOperand_setReg(MCInst_getOperand(MI, i + 1), 0); + else + MCOperand_setReg(MCInst_getOperand(MI, i + 1), ARM_CPSR); + + return; + } + } +} + +static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, + const uint8_t *code, size_t code_len, + uint16_t *Size, uint64_t Address) { + uint16_t insn16; + DecodeStatus result; + bool InITBlock; + unsigned Firstcond, Mask; + uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn; + size_t i; + + // We want to read exactly 2 bytes of data. + if (code_len < 2) + // not enough data + return MCDisassembler_Fail; + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm) + sizeof(cs_arm)); + for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { + MI->flat_insn->detail->arm.operands[i].vector_index = -1; + MI->flat_insn->detail->arm.operands[i].neon_lane = -1; + } + } + + if (MODE_IS_BIG_ENDIAN(ud->mode)) + insn16 = (code[0] << 8) | code[1]; + else + insn16 = (code[1] << 8) | code[0]; + + debugln("table 16"); + result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 2; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + + debugln("table s16"); + MCInst_clear(MI); + result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address, 0, + ud->mode); + if (result) { + *Size = 2; + InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); + Check(&result, AddThumbPredicate(ud, MI)); + AddThumb1SBit(MI, InITBlock); + return result; + } + + MCInst_clear(MI); + debugln("table 216"); + result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 2; + + // Nested IT blocks are UNPREDICTABLE. Must be checked before we add + // the Thumb predicate. + if (MCInst_getOpcode(MI) == ARM_t2IT && + ITStatus_instrInITBlock(&(ud->ITBlock))) + return MCDisassembler_SoftFail; + + Check(&result, AddThumbPredicate(ud, MI)); + + // If we find an IT instruction, we need to parse its condition + // code and mask operands so that we can apply them correctly + // to the subsequent instructions. + if (MCInst_getOpcode(MI) == ARM_t2IT) { + Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0)); + Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1)); + ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask); + + // An IT instruction that would give a 'NV' predicate is unpredictable. + // if (Firstcond == ARMCC_AL && !isPowerOf2_32(Mask)) + // CS << "unpredictable IT predicate sequence"; + } + + return result; + } + + // We want to read exactly 4 bytes of data. + if (code_len < 4) + // not enough data + return MCDisassembler_Fail; + + if (MODE_IS_BIG_ENDIAN(ud->mode)) + insn32 = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | + ((uint32_t)code[0] << 24); + else + insn32 = (code[3] << 8) | (code[2] << 0) | ((uint32_t)code[1] << 24) | + (code[0] << 16); + + MCInst_clear(MI); + debugln("table 32"); + result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); + Check(&result, AddThumbPredicate(ud, MI)); + AddThumb1SBit(MI, InITBlock); + + return result; + } + + MCInst_clear(MI); + debugln("table 232"); + result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + + if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + UpdateThumbVFPPredicate(ud, MI); + return result; + } + } + + MCInst_clear(MI); + debugln("table vfpv"); + result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + } + + if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) { + MCInst_clear(MI); + NEONLdStInsn = insn32; + NEONLdStInsn &= 0xF0FFFFFF; + NEONLdStInsn |= 0x04000000; + result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, + Address, 0, ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + } + + if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) { + MCInst_clear(MI); + NEONDataInsn = insn32; + NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 + NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 + NEONDataInsn |= 0x12000000; // Set bits 28 and 25 + result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, + Address, 0, ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + } + + MCInst_clear(MI); + NEONCryptoInsn = insn32; + NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 + NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 + NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 + result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn, + Address, 0, ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + NEONv8Insn = insn32; + NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 + result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableThumb2CoProc32, MI, insn32, Address, + 0, ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + + debugln("table cde32"); + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableThumb2CDE32, MI, insn32, Address, 0, + ud->mode); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + + MCInst_clear(MI); + *Size = 0; + + return MCDisassembler_Fail; +} + +bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info) { + DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, + code_len, size, address); + + // TODO: fix table gen to eliminate these special cases + if (instr->Opcode == ARM_t__brkdiv0) + return false; + + // return status == MCDisassembler_Success; + return status != MCDisassembler_Fail; +} + +bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info) { + DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, + code_len, size, address); + + // return status == MCDisassembler_Success; + return status != MCDisassembler_Fail; } #endif diff --git a/arch/ARM/ARMDisassembler.h b/arch/ARM/ARMDisassembler.h index 35e75c9c9b..33eeeed3bc 100644 --- a/arch/ARM/ARMDisassembler.h +++ b/arch/ARM/ARMDisassembler.h @@ -4,14 +4,18 @@ #ifndef CS_ARMDISASSEMBLER_H #define CS_ARMDISASSEMBLER_H -#include "capstone/capstone.h" #include "../../MCRegisterInfo.h" +#include "capstone/capstone.h" void ARM_init(MCRegisterInfo *MRI); -bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); +bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info); -bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); +bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info); bool ARM_getFeatureBits(unsigned int mode, unsigned int feature); diff --git a/arch/ARM/ARMGenAsmWriter.inc b/arch/ARM/ARMGenAsmWriter.inc index 78ea52ff44..838ed3ce9d 100644 --- a/arch/ARM/ARMGenAsmWriter.inc +++ b/arch/ARM/ARMGenAsmWriter.inc @@ -11,6955 +11,10252 @@ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O) -{ +static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0, - /* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0, - /* 26 */ 's', 'h', 'a', '1', 's', 'u', '1', '.', '3', '2', 9, 0, - /* 38 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', '.', '3', '2', 9, 0, - /* 52 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', '.', '3', '2', 9, 0, - /* 65 */ 's', 'h', 'a', '1', 'c', '.', '3', '2', 9, 0, - /* 75 */ 's', 'h', 'a', '1', 'h', '.', '3', '2', 9, 0, - /* 85 */ 's', 'h', 'a', '2', '5', '6', 'h', '.', '3', '2', 9, 0, - /* 97 */ 's', 'h', 'a', '1', 'm', '.', '3', '2', 9, 0, - /* 107 */ 's', 'h', 'a', '1', 'p', '.', '3', '2', 9, 0, - /* 117 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, - /* 132 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, - /* 147 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, - /* 162 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, - /* 177 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, - /* 192 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, - /* 207 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, - /* 222 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, - /* 237 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '3', '2', 9, 0, - /* 248 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '3', '2', 9, 0, - /* 260 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '3', '2', 9, 0, - /* 271 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '3', '2', 9, 0, - /* 283 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '3', '2', 9, 0, - /* 295 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '3', '2', 9, 0, - /* 307 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '3', '2', 9, 0, - /* 319 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '3', '2', 9, 0, - /* 331 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '3', '2', 9, 0, - /* 343 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '3', '2', 9, 0, - /* 355 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '3', '2', 9, 0, - /* 367 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '3', '2', 9, 0, - /* 379 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '3', '2', 9, 0, - /* 391 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '3', '2', 9, 0, - /* 403 */ 'l', 'd', 'c', '2', 9, 0, - /* 409 */ 'm', 'r', 'c', '2', 9, 0, - /* 415 */ 'm', 'r', 'r', 'c', '2', 9, 0, - /* 422 */ 's', 't', 'c', '2', 9, 0, - /* 428 */ 'c', 'd', 'p', '2', 9, 0, - /* 434 */ 'm', 'c', 'r', '2', 9, 0, - /* 440 */ 'm', 'c', 'r', 'r', '2', 9, 0, - /* 447 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, - /* 462 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, - /* 477 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, - /* 492 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, - /* 507 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, - /* 522 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, - /* 537 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, - /* 552 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, - /* 567 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '6', '4', 9, 0, - /* 579 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '6', '4', 9, 0, - /* 591 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '6', '4', 9, 0, - /* 603 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '6', '4', 9, 0, - /* 615 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '6', '4', 9, 0, - /* 627 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '6', '4', 9, 0, - /* 639 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '6', '4', 9, 0, - /* 651 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '6', '4', 9, 0, - /* 663 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '6', '4', 9, 0, - /* 675 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '6', '4', 9, 0, - /* 687 */ 'v', 'm', 'u', 'l', 'l', '.', 'p', '6', '4', 9, 0, - /* 698 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, - /* 713 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, - /* 728 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, - /* 743 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, - /* 758 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, - /* 773 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, - /* 788 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, - /* 803 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, - /* 818 */ 'v', 'c', 'v', 't', 'a', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, - /* 833 */ 'v', 'c', 'v', 't', 'm', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, - /* 848 */ 'v', 'c', 'v', 't', 'n', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, - /* 863 */ 'v', 'c', 'v', 't', 'p', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, - /* 878 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, - /* 893 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, - /* 908 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, - /* 923 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, - /* 938 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '1', '6', 9, 0, - /* 949 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '1', '6', 9, 0, - /* 961 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '1', '6', 9, 0, - /* 972 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '1', '6', 9, 0, - /* 984 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '1', '6', 9, 0, - /* 996 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '1', '6', 9, 0, - /* 1008 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '1', '6', 9, 0, - /* 1020 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '1', '6', 9, 0, - /* 1032 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '1', '6', 9, 0, - /* 1044 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '1', '6', 9, 0, - /* 1056 */ 'v', 'i', 'n', 's', '.', 'f', '1', '6', 9, 0, - /* 1066 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '1', '6', 9, 0, - /* 1078 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '1', '6', 9, 0, - /* 1090 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '1', '6', 9, 0, - /* 1102 */ 'v', 'm', 'o', 'v', 'x', '.', 'f', '1', '6', 9, 0, - /* 1113 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '1', '6', 9, 0, - /* 1125 */ 'a', 'e', 's', 'i', 'm', 'c', '.', '8', 9, 0, - /* 1135 */ 'a', 'e', 's', 'm', 'c', '.', '8', 9, 0, - /* 1144 */ 'a', 'e', 's', 'd', '.', '8', 9, 0, - /* 1152 */ 'a', 'e', 's', 'e', '.', '8', 9, 0, - /* 1160 */ 'v', 's', 'd', 'o', 't', '.', 's', '8', 9, 0, - /* 1170 */ 'v', 'u', 'd', 'o', 't', '.', 'u', '8', 9, 0, - /* 1180 */ 'r', 'f', 'e', 'd', 'a', 9, 0, - /* 1187 */ 'r', 'f', 'e', 'i', 'a', 9, 0, - /* 1194 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, - /* 1202 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, - /* 1211 */ 'r', 'f', 'e', 'd', 'b', 9, 0, - /* 1218 */ 'r', 'f', 'e', 'i', 'b', 9, 0, - /* 1225 */ 'd', 'm', 'b', 9, 0, - /* 1230 */ 'd', 's', 'b', 9, 0, - /* 1235 */ 'i', 's', 'b', 9, 0, - /* 1240 */ 't', 's', 'b', 9, 0, - /* 1245 */ 'h', 'v', 'c', 9, 0, - /* 1250 */ 'p', 'l', 'd', 9, 0, - /* 1255 */ 's', 'e', 't', 'e', 'n', 'd', 9, 0, - /* 1263 */ 'u', 'd', 'f', 9, 0, - /* 1268 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, - /* 1276 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, - /* 1285 */ 'p', 'l', 'i', 9, 0, - /* 1290 */ 'l', 'd', 'c', '2', 'l', 9, 0, - /* 1297 */ 's', 't', 'c', '2', 'l', 9, 0, - /* 1304 */ 'b', 'l', 9, 0, - /* 1308 */ 's', 'e', 't', 'p', 'a', 'n', 9, 0, - /* 1316 */ 'c', 'p', 's', 9, 0, - /* 1321 */ 'm', 'o', 'v', 's', 9, 0, - /* 1327 */ 'h', 'l', 't', 9, 0, - /* 1332 */ 'b', 'k', 'p', 't', 9, 0, - /* 1338 */ 'h', 'v', 'c', '.', 'w', 9, 0, - /* 1345 */ 'u', 'd', 'f', '.', 'w', 9, 0, - /* 1352 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, - /* 1360 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, - /* 1369 */ 'p', 'l', 'd', 'w', 9, 0, - /* 1375 */ 'b', 'x', 9, 0, - /* 1379 */ 'b', 'l', 'x', 9, 0, - /* 1384 */ 'c', 'b', 'z', 9, 0, - /* 1389 */ 'c', 'b', 'n', 'z', 9, 0, - /* 1395 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', '!', ',', 32, 0, - /* 1407 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', '!', ',', 32, 0, - /* 1419 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', '!', ',', 32, 0, - /* 1431 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', '!', ',', 32, 0, - /* 1443 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', ',', 32, 0, - /* 1454 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', ',', 32, 0, - /* 1465 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', ',', 32, 0, - /* 1476 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', ',', 32, 0, - /* 1487 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, - /* 1518 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 1542 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 1567 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, - /* 1590 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, - /* 1613 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, - /* 1635 */ '_', '_', 'b', 'r', 'k', 'd', 'i', 'v', '0', 0, - /* 1645 */ 'v', 'l', 'd', '1', 0, - /* 1650 */ 'd', 'c', 'p', 's', '1', 0, - /* 1656 */ 'v', 's', 't', '1', 0, - /* 1661 */ 'v', 'r', 'e', 'v', '3', '2', 0, - /* 1668 */ 'l', 'd', 'c', '2', 0, - /* 1673 */ 'm', 'r', 'c', '2', 0, - /* 1678 */ 'm', 'r', 'r', 'c', '2', 0, - /* 1684 */ 's', 't', 'c', '2', 0, - /* 1689 */ 'v', 'l', 'd', '2', 0, - /* 1694 */ 'c', 'd', 'p', '2', 0, - /* 1699 */ 'm', 'c', 'r', '2', 0, - /* 1704 */ 'm', 'c', 'r', 'r', '2', 0, - /* 1710 */ 'd', 'c', 'p', 's', '2', 0, - /* 1716 */ 'v', 's', 't', '2', 0, - /* 1721 */ 'v', 'l', 'd', '3', 0, - /* 1726 */ 'd', 'c', 'p', 's', '3', 0, - /* 1732 */ 'v', 's', 't', '3', 0, - /* 1737 */ 'v', 'r', 'e', 'v', '6', '4', 0, - /* 1744 */ 'v', 'l', 'd', '4', 0, - /* 1749 */ 'v', 's', 't', '4', 0, - /* 1754 */ 's', 'x', 't', 'a', 'b', '1', '6', 0, - /* 1762 */ 'u', 'x', 't', 'a', 'b', '1', '6', 0, - /* 1770 */ 's', 'x', 't', 'b', '1', '6', 0, - /* 1777 */ 'u', 'x', 't', 'b', '1', '6', 0, - /* 1784 */ 's', 'h', 's', 'u', 'b', '1', '6', 0, - /* 1792 */ 'u', 'h', 's', 'u', 'b', '1', '6', 0, - /* 1800 */ 'u', 'q', 's', 'u', 'b', '1', '6', 0, - /* 1808 */ 's', 's', 'u', 'b', '1', '6', 0, - /* 1815 */ 'u', 's', 'u', 'b', '1', '6', 0, - /* 1822 */ 's', 'h', 'a', 'd', 'd', '1', '6', 0, - /* 1830 */ 'u', 'h', 'a', 'd', 'd', '1', '6', 0, - /* 1838 */ 'u', 'q', 'a', 'd', 'd', '1', '6', 0, - /* 1846 */ 's', 'a', 'd', 'd', '1', '6', 0, - /* 1853 */ 'u', 'a', 'd', 'd', '1', '6', 0, - /* 1860 */ 's', 's', 'a', 't', '1', '6', 0, - /* 1867 */ 'u', 's', 'a', 't', '1', '6', 0, - /* 1874 */ 'v', 'r', 'e', 'v', '1', '6', 0, - /* 1881 */ 'u', 's', 'a', 'd', 'a', '8', 0, - /* 1888 */ 's', 'h', 's', 'u', 'b', '8', 0, - /* 1895 */ 'u', 'h', 's', 'u', 'b', '8', 0, - /* 1902 */ 'u', 'q', 's', 'u', 'b', '8', 0, - /* 1909 */ 's', 's', 'u', 'b', '8', 0, - /* 1915 */ 'u', 's', 'u', 'b', '8', 0, - /* 1921 */ 'u', 's', 'a', 'd', '8', 0, - /* 1927 */ 's', 'h', 'a', 'd', 'd', '8', 0, - /* 1934 */ 'u', 'h', 'a', 'd', 'd', '8', 0, - /* 1941 */ 'u', 'q', 'a', 'd', 'd', '8', 0, - /* 1948 */ 's', 'a', 'd', 'd', '8', 0, - /* 1954 */ 'u', 'a', 'd', 'd', '8', 0, - /* 1960 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 1973 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 1980 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 1990 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, - /* 2000 */ '@', 32, 'C', 'O', 'M', 'P', 'I', 'L', 'E', 'R', 32, 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0, - /* 2019 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 2034 */ 'v', 'a', 'b', 'a', 0, - /* 2039 */ 'l', 'd', 'a', 0, - /* 2043 */ 'l', 'd', 'm', 'd', 'a', 0, - /* 2049 */ 's', 't', 'm', 'd', 'a', 0, - /* 2055 */ 'r', 'f', 'e', 'i', 'a', 0, - /* 2061 */ 'v', 'l', 'd', 'm', 'i', 'a', 0, - /* 2068 */ 'v', 's', 't', 'm', 'i', 'a', 0, - /* 2075 */ 's', 'r', 's', 'i', 'a', 0, - /* 2081 */ 's', 'm', 'm', 'l', 'a', 0, - /* 2087 */ 'v', 'n', 'm', 'l', 'a', 0, - /* 2093 */ 'v', 'm', 'l', 'a', 0, - /* 2098 */ 'v', 'f', 'm', 'a', 0, - /* 2103 */ 'v', 'f', 'n', 'm', 'a', 0, - /* 2109 */ 'v', 'r', 's', 'r', 'a', 0, - /* 2115 */ 'v', 's', 'r', 'a', 0, - /* 2120 */ 't', 't', 'a', 0, - /* 2124 */ 'l', 'd', 'a', 'b', 0, - /* 2129 */ 's', 'x', 't', 'a', 'b', 0, - /* 2135 */ 'u', 'x', 't', 'a', 'b', 0, - /* 2141 */ 's', 'm', 'l', 'a', 'b', 'b', 0, - /* 2148 */ 's', 'm', 'l', 'a', 'l', 'b', 'b', 0, - /* 2156 */ 's', 'm', 'u', 'l', 'b', 'b', 0, - /* 2163 */ 't', 'b', 'b', 0, - /* 2167 */ 'r', 'f', 'e', 'd', 'b', 0, - /* 2173 */ 'v', 'l', 'd', 'm', 'd', 'b', 0, - /* 2180 */ 'v', 's', 't', 'm', 'd', 'b', 0, - /* 2187 */ 's', 'r', 's', 'd', 'b', 0, - /* 2193 */ 'l', 'd', 'm', 'i', 'b', 0, - /* 2199 */ 's', 't', 'm', 'i', 'b', 0, - /* 2205 */ 's', 't', 'l', 'b', 0, - /* 2210 */ 'd', 'm', 'b', 0, - /* 2214 */ 's', 'w', 'p', 'b', 0, - /* 2219 */ 'l', 'd', 'r', 'b', 0, - /* 2224 */ 's', 't', 'r', 'b', 0, - /* 2229 */ 'd', 's', 'b', 0, - /* 2233 */ 'i', 's', 'b', 0, - /* 2237 */ 'l', 'd', 'r', 's', 'b', 0, - /* 2243 */ 't', 's', 'b', 0, - /* 2247 */ 's', 'm', 'l', 'a', 't', 'b', 0, - /* 2254 */ 'p', 'k', 'h', 't', 'b', 0, - /* 2260 */ 's', 'm', 'l', 'a', 'l', 't', 'b', 0, - /* 2268 */ 's', 'm', 'u', 'l', 't', 'b', 0, - /* 2275 */ 'v', 'c', 'v', 't', 'b', 0, - /* 2281 */ 's', 'x', 't', 'b', 0, - /* 2286 */ 'u', 'x', 't', 'b', 0, - /* 2291 */ 'q', 'd', 's', 'u', 'b', 0, - /* 2297 */ 'v', 'h', 's', 'u', 'b', 0, - /* 2303 */ 'v', 'q', 's', 'u', 'b', 0, - /* 2309 */ 'v', 's', 'u', 'b', 0, - /* 2314 */ 's', 'm', 'l', 'a', 'w', 'b', 0, - /* 2321 */ 's', 'm', 'u', 'l', 'w', 'b', 0, - /* 2328 */ 'l', 'd', 'a', 'e', 'x', 'b', 0, - /* 2335 */ 's', 't', 'l', 'e', 'x', 'b', 0, - /* 2342 */ 'l', 'd', 'r', 'e', 'x', 'b', 0, - /* 2349 */ 's', 't', 'r', 'e', 'x', 'b', 0, - /* 2356 */ 's', 'b', 'c', 0, - /* 2360 */ 'a', 'd', 'c', 0, - /* 2364 */ 'l', 'd', 'c', 0, - /* 2368 */ 'b', 'f', 'c', 0, - /* 2372 */ 'v', 'b', 'i', 'c', 0, - /* 2377 */ 's', 'm', 'c', 0, - /* 2381 */ 'm', 'r', 'c', 0, - /* 2385 */ 'm', 'r', 'r', 'c', 0, - /* 2390 */ 'r', 's', 'c', 0, - /* 2394 */ 's', 't', 'c', 0, - /* 2398 */ 's', 'v', 'c', 0, - /* 2402 */ 's', 'm', 'l', 'a', 'd', 0, - /* 2408 */ 's', 'm', 'u', 'a', 'd', 0, - /* 2414 */ 'v', 'a', 'b', 'd', 0, - /* 2419 */ 'q', 'd', 'a', 'd', 'd', 0, - /* 2425 */ 'v', 'r', 'h', 'a', 'd', 'd', 0, - /* 2432 */ 'v', 'h', 'a', 'd', 'd', 0, - /* 2438 */ 'v', 'p', 'a', 'd', 'd', 0, - /* 2444 */ 'v', 'q', 'a', 'd', 'd', 0, - /* 2450 */ 'v', 'a', 'd', 'd', 0, - /* 2455 */ 's', 'm', 'l', 'a', 'l', 'd', 0, - /* 2462 */ 'p', 'l', 'd', 0, - /* 2466 */ 's', 'm', 'l', 's', 'l', 'd', 0, - /* 2473 */ 'v', 'a', 'n', 'd', 0, - /* 2478 */ 'l', 'd', 'r', 'd', 0, - /* 2483 */ 's', 't', 'r', 'd', 0, - /* 2488 */ 's', 'm', 'l', 's', 'd', 0, - /* 2494 */ 's', 'm', 'u', 's', 'd', 0, - /* 2500 */ 'l', 'd', 'a', 'e', 'x', 'd', 0, - /* 2507 */ 's', 't', 'l', 'e', 'x', 'd', 0, - /* 2514 */ 'l', 'd', 'r', 'e', 'x', 'd', 0, - /* 2521 */ 's', 't', 'r', 'e', 'x', 'd', 0, - /* 2528 */ 'v', 'a', 'c', 'g', 'e', 0, - /* 2534 */ 'v', 'c', 'g', 'e', 0, - /* 2539 */ 'v', 'c', 'l', 'e', 0, - /* 2544 */ 'v', 'r', 'e', 'c', 'p', 'e', 0, - /* 2551 */ 'v', 'c', 'm', 'p', 'e', 0, - /* 2557 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 0, - /* 2565 */ 'v', 'b', 'i', 'f', 0, - /* 2570 */ 'd', 'b', 'g', 0, - /* 2574 */ 'v', 'q', 'n', 'e', 'g', 0, - /* 2580 */ 'v', 'n', 'e', 'g', 0, - /* 2585 */ 's', 'g', 0, - /* 2588 */ 'l', 'd', 'a', 'h', 0, - /* 2593 */ 'v', 'q', 'r', 'd', 'm', 'l', 'a', 'h', 0, - /* 2602 */ 's', 'x', 't', 'a', 'h', 0, - /* 2608 */ 'u', 'x', 't', 'a', 'h', 0, - /* 2614 */ 't', 'b', 'h', 0, - /* 2618 */ 's', 't', 'l', 'h', 0, - /* 2623 */ 'v', 'q', 'd', 'm', 'u', 'l', 'h', 0, - /* 2631 */ 'v', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 0, - /* 2640 */ 'l', 'd', 'r', 'h', 0, - /* 2645 */ 's', 't', 'r', 'h', 0, - /* 2650 */ 'v', 'q', 'r', 'd', 'm', 'l', 's', 'h', 0, - /* 2659 */ 'l', 'd', 'r', 's', 'h', 0, - /* 2665 */ 'p', 'u', 's', 'h', 0, - /* 2670 */ 'r', 'e', 'v', 's', 'h', 0, - /* 2676 */ 's', 'x', 't', 'h', 0, - /* 2681 */ 'u', 'x', 't', 'h', 0, - /* 2686 */ 'l', 'd', 'a', 'e', 'x', 'h', 0, - /* 2693 */ 's', 't', 'l', 'e', 'x', 'h', 0, - /* 2700 */ 'l', 'd', 'r', 'e', 'x', 'h', 0, - /* 2707 */ 's', 't', 'r', 'e', 'x', 'h', 0, - /* 2714 */ 'b', 'f', 'i', 0, - /* 2718 */ 'p', 'l', 'i', 0, - /* 2722 */ 'v', 's', 'l', 'i', 0, - /* 2727 */ 'v', 's', 'r', 'i', 0, - /* 2732 */ 'b', 'x', 'j', 0, - /* 2736 */ 'l', 'd', 'c', '2', 'l', 0, - /* 2742 */ 's', 't', 'c', '2', 'l', 0, - /* 2748 */ 'u', 'm', 'a', 'a', 'l', 0, - /* 2754 */ 'v', 'a', 'b', 'a', 'l', 0, - /* 2760 */ 'v', 'p', 'a', 'd', 'a', 'l', 0, - /* 2767 */ 'v', 'q', 'd', 'm', 'l', 'a', 'l', 0, - /* 2775 */ 's', 'm', 'l', 'a', 'l', 0, - /* 2781 */ 'u', 'm', 'l', 'a', 'l', 0, - /* 2787 */ 'v', 'm', 'l', 'a', 'l', 0, - /* 2793 */ 'v', 't', 'b', 'l', 0, - /* 2798 */ 'v', 's', 'u', 'b', 'l', 0, - /* 2804 */ 'l', 'd', 'c', 'l', 0, - /* 2809 */ 's', 't', 'c', 'l', 0, - /* 2814 */ 'v', 'a', 'b', 'd', 'l', 0, - /* 2820 */ 'v', 'p', 'a', 'd', 'd', 'l', 0, - /* 2827 */ 'v', 'a', 'd', 'd', 'l', 0, - /* 2833 */ 's', 'e', 'l', 0, - /* 2837 */ 'v', 'q', 's', 'h', 'l', 0, - /* 2843 */ 'v', 'q', 'r', 's', 'h', 'l', 0, - /* 2850 */ 'v', 'r', 's', 'h', 'l', 0, - /* 2856 */ 'v', 's', 'h', 'l', 0, - /* 2861 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, - /* 2875 */ 'v', 's', 'h', 'l', 'l', 0, - /* 2881 */ 'v', 'q', 'd', 'm', 'u', 'l', 'l', 0, - /* 2889 */ 's', 'm', 'u', 'l', 'l', 0, - /* 2895 */ 'u', 'm', 'u', 'l', 'l', 0, - /* 2901 */ 'v', 'm', 'u', 'l', 'l', 0, - /* 2907 */ 'v', 'b', 's', 'l', 0, - /* 2912 */ 'v', 'q', 'd', 'm', 'l', 's', 'l', 0, - /* 2920 */ 'v', 'm', 'l', 's', 'l', 0, - /* 2926 */ 's', 't', 'l', 0, - /* 2930 */ 's', 'm', 'm', 'u', 'l', 0, - /* 2936 */ 'v', 'n', 'm', 'u', 'l', 0, - /* 2942 */ 'v', 'm', 'u', 'l', 0, - /* 2947 */ 'v', 'm', 'o', 'v', 'l', 0, - /* 2953 */ 'v', 'l', 'l', 'd', 'm', 0, - /* 2959 */ 'v', 'l', 's', 't', 'm', 0, - /* 2965 */ 'v', 'r', 's', 'u', 'b', 'h', 'n', 0, - /* 2973 */ 'v', 's', 'u', 'b', 'h', 'n', 0, - /* 2980 */ 'v', 'r', 'a', 'd', 'd', 'h', 'n', 0, - /* 2988 */ 'v', 'a', 'd', 'd', 'h', 'n', 0, - /* 2995 */ 'v', 'p', 'm', 'i', 'n', 0, - /* 3001 */ 'v', 'm', 'i', 'n', 0, - /* 3006 */ 'c', 'm', 'n', 0, - /* 3010 */ 'v', 'q', 's', 'h', 'r', 'n', 0, - /* 3017 */ 'v', 'q', 'r', 's', 'h', 'r', 'n', 0, - /* 3025 */ 'v', 'r', 's', 'h', 'r', 'n', 0, - /* 3032 */ 'v', 's', 'h', 'r', 'n', 0, - /* 3038 */ 'v', 'o', 'r', 'n', 0, - /* 3043 */ 'v', 't', 'r', 'n', 0, - /* 3048 */ 'v', 'q', 's', 'h', 'r', 'u', 'n', 0, - /* 3056 */ 'v', 'q', 'r', 's', 'h', 'r', 'u', 'n', 0, - /* 3065 */ 'v', 'q', 'm', 'o', 'v', 'u', 'n', 0, - /* 3073 */ 'v', 'm', 'v', 'n', 0, - /* 3078 */ 'v', 'q', 'm', 'o', 'v', 'n', 0, - /* 3085 */ 'v', 'm', 'o', 'v', 'n', 0, - /* 3091 */ 't', 'r', 'a', 'p', 0, - /* 3096 */ 'c', 'd', 'p', 0, - /* 3100 */ 'v', 'z', 'i', 'p', 0, - /* 3105 */ 'v', 'c', 'm', 'p', 0, - /* 3110 */ 'p', 'o', 'p', 0, - /* 3114 */ 'v', 'd', 'u', 'p', 0, - /* 3119 */ 'v', 's', 'w', 'p', 0, - /* 3124 */ 'v', 'u', 'z', 'p', 0, - /* 3129 */ 'v', 'c', 'e', 'q', 0, - /* 3134 */ 't', 'e', 'q', 0, - /* 3138 */ 's', 'm', 'm', 'l', 'a', 'r', 0, - /* 3145 */ 'm', 'c', 'r', 0, - /* 3149 */ 'a', 'd', 'r', 0, - /* 3153 */ 'v', 'l', 'd', 'r', 0, - /* 3158 */ 'v', 'r', 's', 'h', 'r', 0, - /* 3164 */ 'v', 's', 'h', 'r', 0, - /* 3169 */ 's', 'm', 'm', 'u', 'l', 'r', 0, - /* 3176 */ 'v', 'e', 'o', 'r', 0, - /* 3181 */ 'r', 'o', 'r', 0, - /* 3185 */ 'm', 'c', 'r', 'r', 0, - /* 3190 */ 'v', 'o', 'r', 'r', 0, - /* 3195 */ 'a', 's', 'r', 0, - /* 3199 */ 's', 'm', 'm', 'l', 's', 'r', 0, - /* 3206 */ 'v', 'm', 's', 'r', 0, - /* 3211 */ 'v', 'r', 'i', 'n', 't', 'r', 0, - /* 3218 */ 'v', 's', 't', 'r', 0, - /* 3223 */ 'v', 'c', 'v', 't', 'r', 0, - /* 3229 */ 'v', 'q', 'a', 'b', 's', 0, - /* 3235 */ 'v', 'a', 'b', 's', 0, - /* 3240 */ 's', 'u', 'b', 's', 0, - /* 3245 */ 'v', 'c', 'l', 's', 0, - /* 3250 */ 's', 'm', 'm', 'l', 's', 0, - /* 3256 */ 'v', 'n', 'm', 'l', 's', 0, - /* 3262 */ 'v', 'm', 'l', 's', 0, - /* 3267 */ 'v', 'f', 'm', 's', 0, - /* 3272 */ 'v', 'f', 'n', 'm', 's', 0, - /* 3278 */ 'b', 'x', 'n', 's', 0, - /* 3283 */ 'b', 'l', 'x', 'n', 's', 0, - /* 3289 */ 'v', 'r', 'e', 'c', 'p', 's', 0, - /* 3296 */ 'v', 'm', 'r', 's', 0, - /* 3301 */ 'a', 's', 'r', 's', 0, - /* 3306 */ 'l', 's', 'r', 's', 0, - /* 3311 */ 'v', 'r', 's', 'q', 'r', 't', 's', 0, - /* 3319 */ 'm', 'o', 'v', 's', 0, - /* 3324 */ 's', 's', 'a', 't', 0, - /* 3329 */ 'u', 's', 'a', 't', 0, - /* 3334 */ 't', 't', 'a', 't', 0, - /* 3339 */ 's', 'm', 'l', 'a', 'b', 't', 0, - /* 3346 */ 'p', 'k', 'h', 'b', 't', 0, - /* 3352 */ 's', 'm', 'l', 'a', 'l', 'b', 't', 0, - /* 3360 */ 's', 'm', 'u', 'l', 'b', 't', 0, - /* 3367 */ 'l', 'd', 'r', 'b', 't', 0, - /* 3373 */ 's', 't', 'r', 'b', 't', 0, - /* 3379 */ 'l', 'd', 'r', 's', 'b', 't', 0, - /* 3386 */ 'e', 'r', 'e', 't', 0, - /* 3391 */ 'v', 'a', 'c', 'g', 't', 0, - /* 3397 */ 'v', 'c', 'g', 't', 0, - /* 3402 */ 'l', 'd', 'r', 'h', 't', 0, - /* 3408 */ 's', 't', 'r', 'h', 't', 0, - /* 3414 */ 'l', 'd', 'r', 's', 'h', 't', 0, - /* 3421 */ 'r', 'b', 'i', 't', 0, - /* 3426 */ 'v', 'b', 'i', 't', 0, - /* 3431 */ 'v', 'c', 'l', 't', 0, - /* 3436 */ 'v', 'c', 'n', 't', 0, - /* 3441 */ 'h', 'i', 'n', 't', 0, - /* 3446 */ 'l', 'd', 'r', 't', 0, - /* 3451 */ 'v', 's', 'q', 'r', 't', 0, - /* 3457 */ 's', 't', 'r', 't', 0, - /* 3462 */ 'v', 't', 's', 't', 0, - /* 3467 */ 's', 'm', 'l', 'a', 't', 't', 0, - /* 3474 */ 's', 'm', 'l', 'a', 'l', 't', 't', 0, - /* 3482 */ 's', 'm', 'u', 'l', 't', 't', 0, - /* 3489 */ 't', 't', 't', 0, - /* 3493 */ 'v', 'c', 'v', 't', 't', 0, - /* 3499 */ 'v', 'j', 'c', 'v', 't', 0, - /* 3505 */ 'v', 'c', 'v', 't', 0, - /* 3510 */ 'm', 'o', 'v', 't', 0, - /* 3515 */ 's', 'm', 'l', 'a', 'w', 't', 0, - /* 3522 */ 's', 'm', 'u', 'l', 'w', 't', 0, - /* 3529 */ 'v', 'e', 'x', 't', 0, - /* 3534 */ 'v', 'q', 's', 'h', 'l', 'u', 0, - /* 3541 */ 'r', 'e', 'v', 0, - /* 3545 */ 's', 'd', 'i', 'v', 0, - /* 3550 */ 'u', 'd', 'i', 'v', 0, - /* 3555 */ 'v', 'd', 'i', 'v', 0, - /* 3560 */ 'v', 'm', 'o', 'v', 0, - /* 3565 */ 'v', 's', 'u', 'b', 'w', 0, - /* 3571 */ 'v', 'a', 'd', 'd', 'w', 0, - /* 3577 */ 'p', 'l', 'd', 'w', 0, - /* 3582 */ 'm', 'o', 'v', 'w', 0, - /* 3587 */ 'f', 'l', 'd', 'm', 'i', 'a', 'x', 0, - /* 3595 */ 'f', 's', 't', 'm', 'i', 'a', 'x', 0, - /* 3603 */ 'v', 'p', 'm', 'a', 'x', 0, - /* 3609 */ 'v', 'm', 'a', 'x', 0, - /* 3614 */ 's', 'h', 's', 'a', 'x', 0, - /* 3620 */ 'u', 'h', 's', 'a', 'x', 0, - /* 3626 */ 'u', 'q', 's', 'a', 'x', 0, - /* 3632 */ 's', 's', 'a', 'x', 0, - /* 3637 */ 'u', 's', 'a', 'x', 0, - /* 3642 */ 'f', 'l', 'd', 'm', 'd', 'b', 'x', 0, - /* 3650 */ 'f', 's', 't', 'm', 'd', 'b', 'x', 0, - /* 3658 */ 'v', 't', 'b', 'x', 0, - /* 3663 */ 's', 'm', 'l', 'a', 'd', 'x', 0, - /* 3670 */ 's', 'm', 'u', 'a', 'd', 'x', 0, - /* 3677 */ 's', 'm', 'l', 'a', 'l', 'd', 'x', 0, - /* 3685 */ 's', 'm', 'l', 's', 'l', 'd', 'x', 0, - /* 3693 */ 's', 'm', 'l', 's', 'd', 'x', 0, - /* 3700 */ 's', 'm', 'u', 's', 'd', 'x', 0, - /* 3707 */ 'l', 'd', 'a', 'e', 'x', 0, - /* 3713 */ 's', 't', 'l', 'e', 'x', 0, - /* 3719 */ 'l', 'd', 'r', 'e', 'x', 0, - /* 3725 */ 'c', 'l', 'r', 'e', 'x', 0, - /* 3731 */ 's', 't', 'r', 'e', 'x', 0, - /* 3737 */ 's', 'b', 'f', 'x', 0, - /* 3742 */ 'u', 'b', 'f', 'x', 0, - /* 3747 */ 'b', 'l', 'x', 0, - /* 3751 */ 'r', 'r', 'x', 0, - /* 3755 */ 's', 'h', 'a', 's', 'x', 0, - /* 3761 */ 'u', 'h', 'a', 's', 'x', 0, - /* 3767 */ 'u', 'q', 'a', 's', 'x', 0, - /* 3773 */ 's', 'a', 's', 'x', 0, - /* 3778 */ 'u', 'a', 's', 'x', 0, - /* 3783 */ 'v', 'r', 'i', 'n', 't', 'x', 0, - /* 3790 */ 'v', 'c', 'l', 'z', 0, - /* 3795 */ 'v', 'r', 'i', 'n', 't', 'z', 0, + /* 0 */ 's', + 'h', + 'a', + '1', + 's', + 'u', + '0', + '.', + '3', + '2', + 9, + 0, + /* 12 */ 's', + 'h', + 'a', + '2', + '5', + '6', + 's', + 'u', + '0', + '.', + '3', + '2', + 9, + 0, + /* 26 */ 's', + 'h', + 'a', + '1', + 's', + 'u', + '1', + '.', + '3', + '2', + 9, + 0, + /* 38 */ 's', + 'h', + 'a', + '2', + '5', + '6', + 's', + 'u', + '1', + '.', + '3', + '2', + 9, + 0, + /* 52 */ 's', + 'h', + 'a', + '2', + '5', + '6', + 'h', + '2', + '.', + '3', + '2', + 9, + 0, + /* 65 */ 's', + 'h', + 'a', + '1', + 'c', + '.', + '3', + '2', + 9, + 0, + /* 75 */ 's', + 'h', + 'a', + '1', + 'h', + '.', + '3', + '2', + 9, + 0, + /* 85 */ 's', + 'h', + 'a', + '2', + '5', + '6', + 'h', + '.', + '3', + '2', + 9, + 0, + /* 97 */ 's', + 'h', + 'a', + '1', + 'm', + '.', + '3', + '2', + 9, + 0, + /* 107 */ 's', + 'h', + 'a', + '1', + 'p', + '.', + '3', + '2', + 9, + 0, + /* 117 */ 'v', + 'c', + 'v', + 't', + 'a', + '.', + 's', + '3', + '2', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 132 */ 'v', + 'c', + 'v', + 't', + 'm', + '.', + 's', + '3', + '2', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 147 */ 'v', + 'c', + 'v', + 't', + 'n', + '.', + 's', + '3', + '2', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 162 */ 'v', + 'c', + 'v', + 't', + 'p', + '.', + 's', + '3', + '2', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 177 */ 'v', + 'c', + 'v', + 't', + 'a', + '.', + 'u', + '3', + '2', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 192 */ 'v', + 'c', + 'v', + 't', + 'm', + '.', + 'u', + '3', + '2', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 207 */ 'v', + 'c', + 'v', + 't', + 'n', + '.', + 'u', + '3', + '2', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 222 */ 'v', + 'c', + 'v', + 't', + 'p', + '.', + 'u', + '3', + '2', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 237 */ 'v', + 'c', + 'm', + 'l', + 'a', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 248 */ 'v', + 'r', + 'i', + 'n', + 't', + 'a', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 260 */ 'v', + 'c', + 'a', + 'd', + 'd', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 271 */ 'v', + 's', + 'e', + 'l', + 'g', + 'e', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 283 */ 'v', + 'm', + 'i', + 'n', + 'n', + 'm', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 295 */ 'v', + 'm', + 'a', + 'x', + 'n', + 'm', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 307 */ 'v', + 'r', + 'i', + 'n', + 't', + 'm', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 319 */ 'v', + 'r', + 'i', + 'n', + 't', + 'n', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 331 */ 'v', + 'r', + 'i', + 'n', + 't', + 'p', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 343 */ 'v', + 's', + 'e', + 'l', + 'e', + 'q', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 355 */ 'v', + 's', + 'e', + 'l', + 'v', + 's', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 367 */ 'v', + 's', + 'e', + 'l', + 'g', + 't', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 379 */ 'v', + 'r', + 'i', + 'n', + 't', + 'x', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 391 */ 'v', + 'r', + 'i', + 'n', + 't', + 'z', + '.', + 'f', + '3', + '2', + 9, + 0, + /* 403 */ 'l', + 'd', + 'c', + '2', + 9, + 0, + /* 409 */ 'm', + 'r', + 'c', + '2', + 9, + 0, + /* 415 */ 'm', + 'r', + 'r', + 'c', + '2', + 9, + 0, + /* 422 */ 's', + 't', + 'c', + '2', + 9, + 0, + /* 428 */ 'c', + 'd', + 'p', + '2', + 9, + 0, + /* 434 */ 'm', + 'c', + 'r', + '2', + 9, + 0, + /* 440 */ 'm', + 'c', + 'r', + 'r', + '2', + 9, + 0, + /* 447 */ 'v', + 'c', + 'v', + 't', + 'a', + '.', + 's', + '3', + '2', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 462 */ 'v', + 'c', + 'v', + 't', + 'm', + '.', + 's', + '3', + '2', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 477 */ 'v', + 'c', + 'v', + 't', + 'n', + '.', + 's', + '3', + '2', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 492 */ 'v', + 'c', + 'v', + 't', + 'p', + '.', + 's', + '3', + '2', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 507 */ 'v', + 'c', + 'v', + 't', + 'a', + '.', + 'u', + '3', + '2', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 522 */ 'v', + 'c', + 'v', + 't', + 'm', + '.', + 'u', + '3', + '2', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 537 */ 'v', + 'c', + 'v', + 't', + 'n', + '.', + 'u', + '3', + '2', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 552 */ 'v', + 'c', + 'v', + 't', + 'p', + '.', + 'u', + '3', + '2', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 567 */ 'v', + 'r', + 'i', + 'n', + 't', + 'a', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 579 */ 'v', + 's', + 'e', + 'l', + 'g', + 'e', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 591 */ 'v', + 'm', + 'i', + 'n', + 'n', + 'm', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 603 */ 'v', + 'm', + 'a', + 'x', + 'n', + 'm', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 615 */ 'v', + 'r', + 'i', + 'n', + 't', + 'm', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 627 */ 'v', + 'r', + 'i', + 'n', + 't', + 'n', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 639 */ 'v', + 'r', + 'i', + 'n', + 't', + 'p', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 651 */ 'v', + 's', + 'e', + 'l', + 'e', + 'q', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 663 */ 'v', + 's', + 'e', + 'l', + 'v', + 's', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 675 */ 'v', + 's', + 'e', + 'l', + 'g', + 't', + '.', + 'f', + '6', + '4', + 9, + 0, + /* 687 */ 'v', + 'm', + 'u', + 'l', + 'l', + '.', + 'p', + '6', + '4', + 9, + 0, + /* 698 */ 'v', + 'c', + 'v', + 't', + 'a', + '.', + 's', + '3', + '2', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 713 */ 'v', + 'c', + 'v', + 't', + 'm', + '.', + 's', + '3', + '2', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 728 */ 'v', + 'c', + 'v', + 't', + 'n', + '.', + 's', + '3', + '2', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 743 */ 'v', + 'c', + 'v', + 't', + 'p', + '.', + 's', + '3', + '2', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 758 */ 'v', + 'c', + 'v', + 't', + 'a', + '.', + 'u', + '3', + '2', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 773 */ 'v', + 'c', + 'v', + 't', + 'm', + '.', + 'u', + '3', + '2', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 788 */ 'v', + 'c', + 'v', + 't', + 'n', + '.', + 'u', + '3', + '2', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 803 */ 'v', + 'c', + 'v', + 't', + 'p', + '.', + 'u', + '3', + '2', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 818 */ 'v', + 'c', + 'v', + 't', + 'a', + '.', + 's', + '1', + '6', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 833 */ 'v', + 'c', + 'v', + 't', + 'm', + '.', + 's', + '1', + '6', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 848 */ 'v', + 'c', + 'v', + 't', + 'n', + '.', + 's', + '1', + '6', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 863 */ 'v', + 'c', + 'v', + 't', + 'p', + '.', + 's', + '1', + '6', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 878 */ 'v', + 'c', + 'v', + 't', + 'a', + '.', + 'u', + '1', + '6', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 893 */ 'v', + 'c', + 'v', + 't', + 'm', + '.', + 'u', + '1', + '6', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 908 */ 'v', + 'c', + 'v', + 't', + 'n', + '.', + 'u', + '1', + '6', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 923 */ 'v', + 'c', + 'v', + 't', + 'p', + '.', + 'u', + '1', + '6', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 938 */ 'v', + 'c', + 'm', + 'l', + 'a', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 949 */ 'v', + 'r', + 'i', + 'n', + 't', + 'a', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 961 */ 'v', + 'c', + 'a', + 'd', + 'd', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 972 */ 'v', + 's', + 'e', + 'l', + 'g', + 'e', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 984 */ 'v', + 'm', + 'i', + 'n', + 'n', + 'm', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 996 */ 'v', + 'm', + 'a', + 'x', + 'n', + 'm', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1008 */ 'v', + 'r', + 'i', + 'n', + 't', + 'm', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1020 */ 'v', + 'r', + 'i', + 'n', + 't', + 'n', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1032 */ 'v', + 'r', + 'i', + 'n', + 't', + 'p', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1044 */ 'v', + 's', + 'e', + 'l', + 'e', + 'q', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1056 */ 'v', + 'i', + 'n', + 's', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1066 */ 'v', + 's', + 'e', + 'l', + 'v', + 's', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1078 */ 'v', + 's', + 'e', + 'l', + 'g', + 't', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1090 */ 'v', + 'r', + 'i', + 'n', + 't', + 'x', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1102 */ 'v', + 'm', + 'o', + 'v', + 'x', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1113 */ 'v', + 'r', + 'i', + 'n', + 't', + 'z', + '.', + 'f', + '1', + '6', + 9, + 0, + /* 1125 */ 'a', + 'e', + 's', + 'i', + 'm', + 'c', + '.', + '8', + 9, + 0, + /* 1135 */ 'a', + 'e', + 's', + 'm', + 'c', + '.', + '8', + 9, + 0, + /* 1144 */ 'a', + 'e', + 's', + 'd', + '.', + '8', + 9, + 0, + /* 1152 */ 'a', + 'e', + 's', + 'e', + '.', + '8', + 9, + 0, + /* 1160 */ 'v', + 's', + 'd', + 'o', + 't', + '.', + 's', + '8', + 9, + 0, + /* 1170 */ 'v', + 'u', + 'd', + 'o', + 't', + '.', + 'u', + '8', + 9, + 0, + /* 1180 */ 'r', + 'f', + 'e', + 'd', + 'a', + 9, + 0, + /* 1187 */ 'r', + 'f', + 'e', + 'i', + 'a', + 9, + 0, + /* 1194 */ 'c', + 'r', + 'c', + '3', + '2', + 'b', + 9, + 0, + /* 1202 */ 'c', + 'r', + 'c', + '3', + '2', + 'c', + 'b', + 9, + 0, + /* 1211 */ 'r', + 'f', + 'e', + 'd', + 'b', + 9, + 0, + /* 1218 */ 'r', + 'f', + 'e', + 'i', + 'b', + 9, + 0, + /* 1225 */ 'd', + 'm', + 'b', + 9, + 0, + /* 1230 */ 'd', + 's', + 'b', + 9, + 0, + /* 1235 */ 'i', + 's', + 'b', + 9, + 0, + /* 1240 */ 't', + 's', + 'b', + 9, + 0, + /* 1245 */ 'h', + 'v', + 'c', + 9, + 0, + /* 1250 */ 'p', + 'l', + 'd', + 9, + 0, + /* 1255 */ 's', + 'e', + 't', + 'e', + 'n', + 'd', + 9, + 0, + /* 1263 */ 'u', + 'd', + 'f', + 9, + 0, + /* 1268 */ 'c', + 'r', + 'c', + '3', + '2', + 'h', + 9, + 0, + /* 1276 */ 'c', + 'r', + 'c', + '3', + '2', + 'c', + 'h', + 9, + 0, + /* 1285 */ 'p', + 'l', + 'i', + 9, + 0, + /* 1290 */ 'l', + 'd', + 'c', + '2', + 'l', + 9, + 0, + /* 1297 */ 's', + 't', + 'c', + '2', + 'l', + 9, + 0, + /* 1304 */ 'b', + 'l', + 9, + 0, + /* 1308 */ 's', + 'e', + 't', + 'p', + 'a', + 'n', + 9, + 0, + /* 1316 */ 'c', + 'p', + 's', + 9, + 0, + /* 1321 */ 'm', + 'o', + 'v', + 's', + 9, + 0, + /* 1327 */ 'h', + 'l', + 't', + 9, + 0, + /* 1332 */ 'b', + 'k', + 'p', + 't', + 9, + 0, + /* 1338 */ 'h', + 'v', + 'c', + '.', + 'w', + 9, + 0, + /* 1345 */ 'u', + 'd', + 'f', + '.', + 'w', + 9, + 0, + /* 1352 */ 'c', + 'r', + 'c', + '3', + '2', + 'w', + 9, + 0, + /* 1360 */ 'c', + 'r', + 'c', + '3', + '2', + 'c', + 'w', + 9, + 0, + /* 1369 */ 'p', + 'l', + 'd', + 'w', + 9, + 0, + /* 1375 */ 'b', + 'x', + 9, + 0, + /* 1379 */ 'b', + 'l', + 'x', + 9, + 0, + /* 1384 */ 'c', + 'b', + 'z', + 9, + 0, + /* 1389 */ 'c', + 'b', + 'n', + 'z', + 9, + 0, + /* 1395 */ 's', + 'r', + 's', + 'd', + 'a', + 9, + 's', + 'p', + '!', + ',', + 32, + 0, + /* 1407 */ 's', + 'r', + 's', + 'i', + 'a', + 9, + 's', + 'p', + '!', + ',', + 32, + 0, + /* 1419 */ 's', + 'r', + 's', + 'd', + 'b', + 9, + 's', + 'p', + '!', + ',', + 32, + 0, + /* 1431 */ 's', + 'r', + 's', + 'i', + 'b', + 9, + 's', + 'p', + '!', + ',', + 32, + 0, + /* 1443 */ 's', + 'r', + 's', + 'd', + 'a', + 9, + 's', + 'p', + ',', + 32, + 0, + /* 1454 */ 's', + 'r', + 's', + 'i', + 'a', + 9, + 's', + 'p', + ',', + 32, + 0, + /* 1465 */ 's', + 'r', + 's', + 'd', + 'b', + 9, + 's', + 'p', + ',', + 32, + 0, + /* 1476 */ 's', + 'r', + 's', + 'i', + 'b', + 9, + 's', + 'p', + ',', + 32, + 0, + /* 1487 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'P', + 'a', + 't', + 'c', + 'h', + 'a', + 'b', + 'l', + 'e', + 32, + 'R', + 'E', + 'T', + '.', + 0, + /* 1518 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'y', + 'p', + 'e', + 'd', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 1542 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'C', + 'u', + 's', + 't', + 'o', + 'm', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 1567 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'n', + 't', + 'e', + 'r', + '.', + 0, + /* 1590 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'a', + 'i', + 'l', + 32, + 'C', + 'a', + 'l', + 'l', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 1613 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 1635 */ '_', + '_', + 'b', + 'r', + 'k', + 'd', + 'i', + 'v', + '0', + 0, + /* 1645 */ 'v', + 'l', + 'd', + '1', + 0, + /* 1650 */ 'd', + 'c', + 'p', + 's', + '1', + 0, + /* 1656 */ 'v', + 's', + 't', + '1', + 0, + /* 1661 */ 'v', + 'r', + 'e', + 'v', + '3', + '2', + 0, + /* 1668 */ 'l', + 'd', + 'c', + '2', + 0, + /* 1673 */ 'm', + 'r', + 'c', + '2', + 0, + /* 1678 */ 'm', + 'r', + 'r', + 'c', + '2', + 0, + /* 1684 */ 's', + 't', + 'c', + '2', + 0, + /* 1689 */ 'v', + 'l', + 'd', + '2', + 0, + /* 1694 */ 'c', + 'd', + 'p', + '2', + 0, + /* 1699 */ 'm', + 'c', + 'r', + '2', + 0, + /* 1704 */ 'm', + 'c', + 'r', + 'r', + '2', + 0, + /* 1710 */ 'd', + 'c', + 'p', + 's', + '2', + 0, + /* 1716 */ 'v', + 's', + 't', + '2', + 0, + /* 1721 */ 'v', + 'l', + 'd', + '3', + 0, + /* 1726 */ 'd', + 'c', + 'p', + 's', + '3', + 0, + /* 1732 */ 'v', + 's', + 't', + '3', + 0, + /* 1737 */ 'v', + 'r', + 'e', + 'v', + '6', + '4', + 0, + /* 1744 */ 'v', + 'l', + 'd', + '4', + 0, + /* 1749 */ 'v', + 's', + 't', + '4', + 0, + /* 1754 */ 's', + 'x', + 't', + 'a', + 'b', + '1', + '6', + 0, + /* 1762 */ 'u', + 'x', + 't', + 'a', + 'b', + '1', + '6', + 0, + /* 1770 */ 's', + 'x', + 't', + 'b', + '1', + '6', + 0, + /* 1777 */ 'u', + 'x', + 't', + 'b', + '1', + '6', + 0, + /* 1784 */ 's', + 'h', + 's', + 'u', + 'b', + '1', + '6', + 0, + /* 1792 */ 'u', + 'h', + 's', + 'u', + 'b', + '1', + '6', + 0, + /* 1800 */ 'u', + 'q', + 's', + 'u', + 'b', + '1', + '6', + 0, + /* 1808 */ 's', + 's', + 'u', + 'b', + '1', + '6', + 0, + /* 1815 */ 'u', + 's', + 'u', + 'b', + '1', + '6', + 0, + /* 1822 */ 's', + 'h', + 'a', + 'd', + 'd', + '1', + '6', + 0, + /* 1830 */ 'u', + 'h', + 'a', + 'd', + 'd', + '1', + '6', + 0, + /* 1838 */ 'u', + 'q', + 'a', + 'd', + 'd', + '1', + '6', + 0, + /* 1846 */ 's', + 'a', + 'd', + 'd', + '1', + '6', + 0, + /* 1853 */ 'u', + 'a', + 'd', + 'd', + '1', + '6', + 0, + /* 1860 */ 's', + 's', + 'a', + 't', + '1', + '6', + 0, + /* 1867 */ 'u', + 's', + 'a', + 't', + '1', + '6', + 0, + /* 1874 */ 'v', + 'r', + 'e', + 'v', + '1', + '6', + 0, + /* 1881 */ 'u', + 's', + 'a', + 'd', + 'a', + '8', + 0, + /* 1888 */ 's', + 'h', + 's', + 'u', + 'b', + '8', + 0, + /* 1895 */ 'u', + 'h', + 's', + 'u', + 'b', + '8', + 0, + /* 1902 */ 'u', + 'q', + 's', + 'u', + 'b', + '8', + 0, + /* 1909 */ 's', + 's', + 'u', + 'b', + '8', + 0, + /* 1915 */ 'u', + 's', + 'u', + 'b', + '8', + 0, + /* 1921 */ 'u', + 's', + 'a', + 'd', + '8', + 0, + /* 1927 */ 's', + 'h', + 'a', + 'd', + 'd', + '8', + 0, + /* 1934 */ 'u', + 'h', + 'a', + 'd', + 'd', + '8', + 0, + /* 1941 */ 'u', + 'q', + 'a', + 'd', + 'd', + '8', + 0, + /* 1948 */ 's', + 'a', + 'd', + 'd', + '8', + 0, + /* 1954 */ 'u', + 'a', + 'd', + 'd', + '8', + 0, + /* 1960 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'E', + 'N', + 'D', + 0, + /* 1973 */ 'B', + 'U', + 'N', + 'D', + 'L', + 'E', + 0, + /* 1980 */ 'D', + 'B', + 'G', + '_', + 'V', + 'A', + 'L', + 'U', + 'E', + 0, + /* 1990 */ 'D', + 'B', + 'G', + '_', + 'L', + 'A', + 'B', + 'E', + 'L', + 0, + /* 2000 */ '@', + 32, + 'C', + 'O', + 'M', + 'P', + 'I', + 'L', + 'E', + 'R', + 32, + 'B', + 'A', + 'R', + 'R', + 'I', + 'E', + 'R', + 0, + /* 2019 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'S', + 'T', + 'A', + 'R', + 'T', + 0, + /* 2034 */ 'v', + 'a', + 'b', + 'a', + 0, + /* 2039 */ 'l', + 'd', + 'a', + 0, + /* 2043 */ 'l', + 'd', + 'm', + 'd', + 'a', + 0, + /* 2049 */ 's', + 't', + 'm', + 'd', + 'a', + 0, + /* 2055 */ 'r', + 'f', + 'e', + 'i', + 'a', + 0, + /* 2061 */ 'v', + 'l', + 'd', + 'm', + 'i', + 'a', + 0, + /* 2068 */ 'v', + 's', + 't', + 'm', + 'i', + 'a', + 0, + /* 2075 */ 's', + 'r', + 's', + 'i', + 'a', + 0, + /* 2081 */ 's', + 'm', + 'm', + 'l', + 'a', + 0, + /* 2087 */ 'v', + 'n', + 'm', + 'l', + 'a', + 0, + /* 2093 */ 'v', + 'm', + 'l', + 'a', + 0, + /* 2098 */ 'v', + 'f', + 'm', + 'a', + 0, + /* 2103 */ 'v', + 'f', + 'n', + 'm', + 'a', + 0, + /* 2109 */ 'v', + 'r', + 's', + 'r', + 'a', + 0, + /* 2115 */ 'v', + 's', + 'r', + 'a', + 0, + /* 2120 */ 't', + 't', + 'a', + 0, + /* 2124 */ 'l', + 'd', + 'a', + 'b', + 0, + /* 2129 */ 's', + 'x', + 't', + 'a', + 'b', + 0, + /* 2135 */ 'u', + 'x', + 't', + 'a', + 'b', + 0, + /* 2141 */ 's', + 'm', + 'l', + 'a', + 'b', + 'b', + 0, + /* 2148 */ 's', + 'm', + 'l', + 'a', + 'l', + 'b', + 'b', + 0, + /* 2156 */ 's', + 'm', + 'u', + 'l', + 'b', + 'b', + 0, + /* 2163 */ 't', + 'b', + 'b', + 0, + /* 2167 */ 'r', + 'f', + 'e', + 'd', + 'b', + 0, + /* 2173 */ 'v', + 'l', + 'd', + 'm', + 'd', + 'b', + 0, + /* 2180 */ 'v', + 's', + 't', + 'm', + 'd', + 'b', + 0, + /* 2187 */ 's', + 'r', + 's', + 'd', + 'b', + 0, + /* 2193 */ 'l', + 'd', + 'm', + 'i', + 'b', + 0, + /* 2199 */ 's', + 't', + 'm', + 'i', + 'b', + 0, + /* 2205 */ 's', + 't', + 'l', + 'b', + 0, + /* 2210 */ 'd', + 'm', + 'b', + 0, + /* 2214 */ 's', + 'w', + 'p', + 'b', + 0, + /* 2219 */ 'l', + 'd', + 'r', + 'b', + 0, + /* 2224 */ 's', + 't', + 'r', + 'b', + 0, + /* 2229 */ 'd', + 's', + 'b', + 0, + /* 2233 */ 'i', + 's', + 'b', + 0, + /* 2237 */ 'l', + 'd', + 'r', + 's', + 'b', + 0, + /* 2243 */ 't', + 's', + 'b', + 0, + /* 2247 */ 's', + 'm', + 'l', + 'a', + 't', + 'b', + 0, + /* 2254 */ 'p', + 'k', + 'h', + 't', + 'b', + 0, + /* 2260 */ 's', + 'm', + 'l', + 'a', + 'l', + 't', + 'b', + 0, + /* 2268 */ 's', + 'm', + 'u', + 'l', + 't', + 'b', + 0, + /* 2275 */ 'v', + 'c', + 'v', + 't', + 'b', + 0, + /* 2281 */ 's', + 'x', + 't', + 'b', + 0, + /* 2286 */ 'u', + 'x', + 't', + 'b', + 0, + /* 2291 */ 'q', + 'd', + 's', + 'u', + 'b', + 0, + /* 2297 */ 'v', + 'h', + 's', + 'u', + 'b', + 0, + /* 2303 */ 'v', + 'q', + 's', + 'u', + 'b', + 0, + /* 2309 */ 'v', + 's', + 'u', + 'b', + 0, + /* 2314 */ 's', + 'm', + 'l', + 'a', + 'w', + 'b', + 0, + /* 2321 */ 's', + 'm', + 'u', + 'l', + 'w', + 'b', + 0, + /* 2328 */ 'l', + 'd', + 'a', + 'e', + 'x', + 'b', + 0, + /* 2335 */ 's', + 't', + 'l', + 'e', + 'x', + 'b', + 0, + /* 2342 */ 'l', + 'd', + 'r', + 'e', + 'x', + 'b', + 0, + /* 2349 */ 's', + 't', + 'r', + 'e', + 'x', + 'b', + 0, + /* 2356 */ 's', + 'b', + 'c', + 0, + /* 2360 */ 'a', + 'd', + 'c', + 0, + /* 2364 */ 'l', + 'd', + 'c', + 0, + /* 2368 */ 'b', + 'f', + 'c', + 0, + /* 2372 */ 'v', + 'b', + 'i', + 'c', + 0, + /* 2377 */ 's', + 'm', + 'c', + 0, + /* 2381 */ 'm', + 'r', + 'c', + 0, + /* 2385 */ 'm', + 'r', + 'r', + 'c', + 0, + /* 2390 */ 'r', + 's', + 'c', + 0, + /* 2394 */ 's', + 't', + 'c', + 0, + /* 2398 */ 's', + 'v', + 'c', + 0, + /* 2402 */ 's', + 'm', + 'l', + 'a', + 'd', + 0, + /* 2408 */ 's', + 'm', + 'u', + 'a', + 'd', + 0, + /* 2414 */ 'v', + 'a', + 'b', + 'd', + 0, + /* 2419 */ 'q', + 'd', + 'a', + 'd', + 'd', + 0, + /* 2425 */ 'v', + 'r', + 'h', + 'a', + 'd', + 'd', + 0, + /* 2432 */ 'v', + 'h', + 'a', + 'd', + 'd', + 0, + /* 2438 */ 'v', + 'p', + 'a', + 'd', + 'd', + 0, + /* 2444 */ 'v', + 'q', + 'a', + 'd', + 'd', + 0, + /* 2450 */ 'v', + 'a', + 'd', + 'd', + 0, + /* 2455 */ 's', + 'm', + 'l', + 'a', + 'l', + 'd', + 0, + /* 2462 */ 'p', + 'l', + 'd', + 0, + /* 2466 */ 's', + 'm', + 'l', + 's', + 'l', + 'd', + 0, + /* 2473 */ 'v', + 'a', + 'n', + 'd', + 0, + /* 2478 */ 'l', + 'd', + 'r', + 'd', + 0, + /* 2483 */ 's', + 't', + 'r', + 'd', + 0, + /* 2488 */ 's', + 'm', + 'l', + 's', + 'd', + 0, + /* 2494 */ 's', + 'm', + 'u', + 's', + 'd', + 0, + /* 2500 */ 'l', + 'd', + 'a', + 'e', + 'x', + 'd', + 0, + /* 2507 */ 's', + 't', + 'l', + 'e', + 'x', + 'd', + 0, + /* 2514 */ 'l', + 'd', + 'r', + 'e', + 'x', + 'd', + 0, + /* 2521 */ 's', + 't', + 'r', + 'e', + 'x', + 'd', + 0, + /* 2528 */ 'v', + 'a', + 'c', + 'g', + 'e', + 0, + /* 2534 */ 'v', + 'c', + 'g', + 'e', + 0, + /* 2539 */ 'v', + 'c', + 'l', + 'e', + 0, + /* 2544 */ 'v', + 'r', + 'e', + 'c', + 'p', + 'e', + 0, + /* 2551 */ 'v', + 'c', + 'm', + 'p', + 'e', + 0, + /* 2557 */ 'v', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 0, + /* 2565 */ 'v', + 'b', + 'i', + 'f', + 0, + /* 2570 */ 'd', + 'b', + 'g', + 0, + /* 2574 */ 'v', + 'q', + 'n', + 'e', + 'g', + 0, + /* 2580 */ 'v', + 'n', + 'e', + 'g', + 0, + /* 2585 */ 's', + 'g', + 0, + /* 2588 */ 'l', + 'd', + 'a', + 'h', + 0, + /* 2593 */ 'v', + 'q', + 'r', + 'd', + 'm', + 'l', + 'a', + 'h', + 0, + /* 2602 */ 's', + 'x', + 't', + 'a', + 'h', + 0, + /* 2608 */ 'u', + 'x', + 't', + 'a', + 'h', + 0, + /* 2614 */ 't', + 'b', + 'h', + 0, + /* 2618 */ 's', + 't', + 'l', + 'h', + 0, + /* 2623 */ 'v', + 'q', + 'd', + 'm', + 'u', + 'l', + 'h', + 0, + /* 2631 */ 'v', + 'q', + 'r', + 'd', + 'm', + 'u', + 'l', + 'h', + 0, + /* 2640 */ 'l', + 'd', + 'r', + 'h', + 0, + /* 2645 */ 's', + 't', + 'r', + 'h', + 0, + /* 2650 */ 'v', + 'q', + 'r', + 'd', + 'm', + 'l', + 's', + 'h', + 0, + /* 2659 */ 'l', + 'd', + 'r', + 's', + 'h', + 0, + /* 2665 */ 'p', + 'u', + 's', + 'h', + 0, + /* 2670 */ 'r', + 'e', + 'v', + 's', + 'h', + 0, + /* 2676 */ 's', + 'x', + 't', + 'h', + 0, + /* 2681 */ 'u', + 'x', + 't', + 'h', + 0, + /* 2686 */ 'l', + 'd', + 'a', + 'e', + 'x', + 'h', + 0, + /* 2693 */ 's', + 't', + 'l', + 'e', + 'x', + 'h', + 0, + /* 2700 */ 'l', + 'd', + 'r', + 'e', + 'x', + 'h', + 0, + /* 2707 */ 's', + 't', + 'r', + 'e', + 'x', + 'h', + 0, + /* 2714 */ 'b', + 'f', + 'i', + 0, + /* 2718 */ 'p', + 'l', + 'i', + 0, + /* 2722 */ 'v', + 's', + 'l', + 'i', + 0, + /* 2727 */ 'v', + 's', + 'r', + 'i', + 0, + /* 2732 */ 'b', + 'x', + 'j', + 0, + /* 2736 */ 'l', + 'd', + 'c', + '2', + 'l', + 0, + /* 2742 */ 's', + 't', + 'c', + '2', + 'l', + 0, + /* 2748 */ 'u', + 'm', + 'a', + 'a', + 'l', + 0, + /* 2754 */ 'v', + 'a', + 'b', + 'a', + 'l', + 0, + /* 2760 */ 'v', + 'p', + 'a', + 'd', + 'a', + 'l', + 0, + /* 2767 */ 'v', + 'q', + 'd', + 'm', + 'l', + 'a', + 'l', + 0, + /* 2775 */ 's', + 'm', + 'l', + 'a', + 'l', + 0, + /* 2781 */ 'u', + 'm', + 'l', + 'a', + 'l', + 0, + /* 2787 */ 'v', + 'm', + 'l', + 'a', + 'l', + 0, + /* 2793 */ 'v', + 't', + 'b', + 'l', + 0, + /* 2798 */ 'v', + 's', + 'u', + 'b', + 'l', + 0, + /* 2804 */ 'l', + 'd', + 'c', + 'l', + 0, + /* 2809 */ 's', + 't', + 'c', + 'l', + 0, + /* 2814 */ 'v', + 'a', + 'b', + 'd', + 'l', + 0, + /* 2820 */ 'v', + 'p', + 'a', + 'd', + 'd', + 'l', + 0, + /* 2827 */ 'v', + 'a', + 'd', + 'd', + 'l', + 0, + /* 2833 */ 's', + 'e', + 'l', + 0, + /* 2837 */ 'v', + 'q', + 's', + 'h', + 'l', + 0, + /* 2843 */ 'v', + 'q', + 'r', + 's', + 'h', + 'l', + 0, + /* 2850 */ 'v', + 'r', + 's', + 'h', + 'l', + 0, + /* 2856 */ 'v', + 's', + 'h', + 'l', + 0, + /* 2861 */ '#', + 32, + 'F', + 'E', + 'n', + 't', + 'r', + 'y', + 32, + 'c', + 'a', + 'l', + 'l', + 0, + /* 2875 */ 'v', + 's', + 'h', + 'l', + 'l', + 0, + /* 2881 */ 'v', + 'q', + 'd', + 'm', + 'u', + 'l', + 'l', + 0, + /* 2889 */ 's', + 'm', + 'u', + 'l', + 'l', + 0, + /* 2895 */ 'u', + 'm', + 'u', + 'l', + 'l', + 0, + /* 2901 */ 'v', + 'm', + 'u', + 'l', + 'l', + 0, + /* 2907 */ 'v', + 'b', + 's', + 'l', + 0, + /* 2912 */ 'v', + 'q', + 'd', + 'm', + 'l', + 's', + 'l', + 0, + /* 2920 */ 'v', + 'm', + 'l', + 's', + 'l', + 0, + /* 2926 */ 's', + 't', + 'l', + 0, + /* 2930 */ 's', + 'm', + 'm', + 'u', + 'l', + 0, + /* 2936 */ 'v', + 'n', + 'm', + 'u', + 'l', + 0, + /* 2942 */ 'v', + 'm', + 'u', + 'l', + 0, + /* 2947 */ 'v', + 'm', + 'o', + 'v', + 'l', + 0, + /* 2953 */ 'v', + 'l', + 'l', + 'd', + 'm', + 0, + /* 2959 */ 'v', + 'l', + 's', + 't', + 'm', + 0, + /* 2965 */ 'v', + 'r', + 's', + 'u', + 'b', + 'h', + 'n', + 0, + /* 2973 */ 'v', + 's', + 'u', + 'b', + 'h', + 'n', + 0, + /* 2980 */ 'v', + 'r', + 'a', + 'd', + 'd', + 'h', + 'n', + 0, + /* 2988 */ 'v', + 'a', + 'd', + 'd', + 'h', + 'n', + 0, + /* 2995 */ 'v', + 'p', + 'm', + 'i', + 'n', + 0, + /* 3001 */ 'v', + 'm', + 'i', + 'n', + 0, + /* 3006 */ 'c', + 'm', + 'n', + 0, + /* 3010 */ 'v', + 'q', + 's', + 'h', + 'r', + 'n', + 0, + /* 3017 */ 'v', + 'q', + 'r', + 's', + 'h', + 'r', + 'n', + 0, + /* 3025 */ 'v', + 'r', + 's', + 'h', + 'r', + 'n', + 0, + /* 3032 */ 'v', + 's', + 'h', + 'r', + 'n', + 0, + /* 3038 */ 'v', + 'o', + 'r', + 'n', + 0, + /* 3043 */ 'v', + 't', + 'r', + 'n', + 0, + /* 3048 */ 'v', + 'q', + 's', + 'h', + 'r', + 'u', + 'n', + 0, + /* 3056 */ 'v', + 'q', + 'r', + 's', + 'h', + 'r', + 'u', + 'n', + 0, + /* 3065 */ 'v', + 'q', + 'm', + 'o', + 'v', + 'u', + 'n', + 0, + /* 3073 */ 'v', + 'm', + 'v', + 'n', + 0, + /* 3078 */ 'v', + 'q', + 'm', + 'o', + 'v', + 'n', + 0, + /* 3085 */ 'v', + 'm', + 'o', + 'v', + 'n', + 0, + /* 3091 */ 't', + 'r', + 'a', + 'p', + 0, + /* 3096 */ 'c', + 'd', + 'p', + 0, + /* 3100 */ 'v', + 'z', + 'i', + 'p', + 0, + /* 3105 */ 'v', + 'c', + 'm', + 'p', + 0, + /* 3110 */ 'p', + 'o', + 'p', + 0, + /* 3114 */ 'v', + 'd', + 'u', + 'p', + 0, + /* 3119 */ 'v', + 's', + 'w', + 'p', + 0, + /* 3124 */ 'v', + 'u', + 'z', + 'p', + 0, + /* 3129 */ 'v', + 'c', + 'e', + 'q', + 0, + /* 3134 */ 't', + 'e', + 'q', + 0, + /* 3138 */ 's', + 'm', + 'm', + 'l', + 'a', + 'r', + 0, + /* 3145 */ 'm', + 'c', + 'r', + 0, + /* 3149 */ 'a', + 'd', + 'r', + 0, + /* 3153 */ 'v', + 'l', + 'd', + 'r', + 0, + /* 3158 */ 'v', + 'r', + 's', + 'h', + 'r', + 0, + /* 3164 */ 'v', + 's', + 'h', + 'r', + 0, + /* 3169 */ 's', + 'm', + 'm', + 'u', + 'l', + 'r', + 0, + /* 3176 */ 'v', + 'e', + 'o', + 'r', + 0, + /* 3181 */ 'r', + 'o', + 'r', + 0, + /* 3185 */ 'm', + 'c', + 'r', + 'r', + 0, + /* 3190 */ 'v', + 'o', + 'r', + 'r', + 0, + /* 3195 */ 'a', + 's', + 'r', + 0, + /* 3199 */ 's', + 'm', + 'm', + 'l', + 's', + 'r', + 0, + /* 3206 */ 'v', + 'm', + 's', + 'r', + 0, + /* 3211 */ 'v', + 'r', + 'i', + 'n', + 't', + 'r', + 0, + /* 3218 */ 'v', + 's', + 't', + 'r', + 0, + /* 3223 */ 'v', + 'c', + 'v', + 't', + 'r', + 0, + /* 3229 */ 'v', + 'q', + 'a', + 'b', + 's', + 0, + /* 3235 */ 'v', + 'a', + 'b', + 's', + 0, + /* 3240 */ 's', + 'u', + 'b', + 's', + 0, + /* 3245 */ 'v', + 'c', + 'l', + 's', + 0, + /* 3250 */ 's', + 'm', + 'm', + 'l', + 's', + 0, + /* 3256 */ 'v', + 'n', + 'm', + 'l', + 's', + 0, + /* 3262 */ 'v', + 'm', + 'l', + 's', + 0, + /* 3267 */ 'v', + 'f', + 'm', + 's', + 0, + /* 3272 */ 'v', + 'f', + 'n', + 'm', + 's', + 0, + /* 3278 */ 'b', + 'x', + 'n', + 's', + 0, + /* 3283 */ 'b', + 'l', + 'x', + 'n', + 's', + 0, + /* 3289 */ 'v', + 'r', + 'e', + 'c', + 'p', + 's', + 0, + /* 3296 */ 'v', + 'm', + 'r', + 's', + 0, + /* 3301 */ 'a', + 's', + 'r', + 's', + 0, + /* 3306 */ 'l', + 's', + 'r', + 's', + 0, + /* 3311 */ 'v', + 'r', + 's', + 'q', + 'r', + 't', + 's', + 0, + /* 3319 */ 'm', + 'o', + 'v', + 's', + 0, + /* 3324 */ 's', + 's', + 'a', + 't', + 0, + /* 3329 */ 'u', + 's', + 'a', + 't', + 0, + /* 3334 */ 't', + 't', + 'a', + 't', + 0, + /* 3339 */ 's', + 'm', + 'l', + 'a', + 'b', + 't', + 0, + /* 3346 */ 'p', + 'k', + 'h', + 'b', + 't', + 0, + /* 3352 */ 's', + 'm', + 'l', + 'a', + 'l', + 'b', + 't', + 0, + /* 3360 */ 's', + 'm', + 'u', + 'l', + 'b', + 't', + 0, + /* 3367 */ 'l', + 'd', + 'r', + 'b', + 't', + 0, + /* 3373 */ 's', + 't', + 'r', + 'b', + 't', + 0, + /* 3379 */ 'l', + 'd', + 'r', + 's', + 'b', + 't', + 0, + /* 3386 */ 'e', + 'r', + 'e', + 't', + 0, + /* 3391 */ 'v', + 'a', + 'c', + 'g', + 't', + 0, + /* 3397 */ 'v', + 'c', + 'g', + 't', + 0, + /* 3402 */ 'l', + 'd', + 'r', + 'h', + 't', + 0, + /* 3408 */ 's', + 't', + 'r', + 'h', + 't', + 0, + /* 3414 */ 'l', + 'd', + 'r', + 's', + 'h', + 't', + 0, + /* 3421 */ 'r', + 'b', + 'i', + 't', + 0, + /* 3426 */ 'v', + 'b', + 'i', + 't', + 0, + /* 3431 */ 'v', + 'c', + 'l', + 't', + 0, + /* 3436 */ 'v', + 'c', + 'n', + 't', + 0, + /* 3441 */ 'h', + 'i', + 'n', + 't', + 0, + /* 3446 */ 'l', + 'd', + 'r', + 't', + 0, + /* 3451 */ 'v', + 's', + 'q', + 'r', + 't', + 0, + /* 3457 */ 's', + 't', + 'r', + 't', + 0, + /* 3462 */ 'v', + 't', + 's', + 't', + 0, + /* 3467 */ 's', + 'm', + 'l', + 'a', + 't', + 't', + 0, + /* 3474 */ 's', + 'm', + 'l', + 'a', + 'l', + 't', + 't', + 0, + /* 3482 */ 's', + 'm', + 'u', + 'l', + 't', + 't', + 0, + /* 3489 */ 't', + 't', + 't', + 0, + /* 3493 */ 'v', + 'c', + 'v', + 't', + 't', + 0, + /* 3499 */ 'v', + 'j', + 'c', + 'v', + 't', + 0, + /* 3505 */ 'v', + 'c', + 'v', + 't', + 0, + /* 3510 */ 'm', + 'o', + 'v', + 't', + 0, + /* 3515 */ 's', + 'm', + 'l', + 'a', + 'w', + 't', + 0, + /* 3522 */ 's', + 'm', + 'u', + 'l', + 'w', + 't', + 0, + /* 3529 */ 'v', + 'e', + 'x', + 't', + 0, + /* 3534 */ 'v', + 'q', + 's', + 'h', + 'l', + 'u', + 0, + /* 3541 */ 'r', + 'e', + 'v', + 0, + /* 3545 */ 's', + 'd', + 'i', + 'v', + 0, + /* 3550 */ 'u', + 'd', + 'i', + 'v', + 0, + /* 3555 */ 'v', + 'd', + 'i', + 'v', + 0, + /* 3560 */ 'v', + 'm', + 'o', + 'v', + 0, + /* 3565 */ 'v', + 's', + 'u', + 'b', + 'w', + 0, + /* 3571 */ 'v', + 'a', + 'd', + 'd', + 'w', + 0, + /* 3577 */ 'p', + 'l', + 'd', + 'w', + 0, + /* 3582 */ 'm', + 'o', + 'v', + 'w', + 0, + /* 3587 */ 'f', + 'l', + 'd', + 'm', + 'i', + 'a', + 'x', + 0, + /* 3595 */ 'f', + 's', + 't', + 'm', + 'i', + 'a', + 'x', + 0, + /* 3603 */ 'v', + 'p', + 'm', + 'a', + 'x', + 0, + /* 3609 */ 'v', + 'm', + 'a', + 'x', + 0, + /* 3614 */ 's', + 'h', + 's', + 'a', + 'x', + 0, + /* 3620 */ 'u', + 'h', + 's', + 'a', + 'x', + 0, + /* 3626 */ 'u', + 'q', + 's', + 'a', + 'x', + 0, + /* 3632 */ 's', + 's', + 'a', + 'x', + 0, + /* 3637 */ 'u', + 's', + 'a', + 'x', + 0, + /* 3642 */ 'f', + 'l', + 'd', + 'm', + 'd', + 'b', + 'x', + 0, + /* 3650 */ 'f', + 's', + 't', + 'm', + 'd', + 'b', + 'x', + 0, + /* 3658 */ 'v', + 't', + 'b', + 'x', + 0, + /* 3663 */ 's', + 'm', + 'l', + 'a', + 'd', + 'x', + 0, + /* 3670 */ 's', + 'm', + 'u', + 'a', + 'd', + 'x', + 0, + /* 3677 */ 's', + 'm', + 'l', + 'a', + 'l', + 'd', + 'x', + 0, + /* 3685 */ 's', + 'm', + 'l', + 's', + 'l', + 'd', + 'x', + 0, + /* 3693 */ 's', + 'm', + 'l', + 's', + 'd', + 'x', + 0, + /* 3700 */ 's', + 'm', + 'u', + 's', + 'd', + 'x', + 0, + /* 3707 */ 'l', + 'd', + 'a', + 'e', + 'x', + 0, + /* 3713 */ 's', + 't', + 'l', + 'e', + 'x', + 0, + /* 3719 */ 'l', + 'd', + 'r', + 'e', + 'x', + 0, + /* 3725 */ 'c', + 'l', + 'r', + 'e', + 'x', + 0, + /* 3731 */ 's', + 't', + 'r', + 'e', + 'x', + 0, + /* 3737 */ 's', + 'b', + 'f', + 'x', + 0, + /* 3742 */ 'u', + 'b', + 'f', + 'x', + 0, + /* 3747 */ 'b', + 'l', + 'x', + 0, + /* 3751 */ 'r', + 'r', + 'x', + 0, + /* 3755 */ 's', + 'h', + 'a', + 's', + 'x', + 0, + /* 3761 */ 'u', + 'h', + 'a', + 's', + 'x', + 0, + /* 3767 */ 'u', + 'q', + 'a', + 's', + 'x', + 0, + /* 3773 */ 's', + 'a', + 's', + 'x', + 0, + /* 3778 */ 'u', + 'a', + 's', + 'x', + 0, + /* 3783 */ 'v', + 'r', + 'i', + 'n', + 't', + 'x', + 0, + /* 3790 */ 'v', + 'c', + 'l', + 'z', + 0, + /* 3795 */ 'v', + 'r', + 'i', + 'n', + 't', + 'z', + 0, }; #endif static const uint32_t OpInfo0[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 1981U, // DBG_VALUE - 1991U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 1974U, // BUNDLE - 2020U, // LIFETIME_START - 1961U, // LIFETIME_END - 0U, // STACKMAP - 2862U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 1568U, // PATCHABLE_FUNCTION_ENTER - 1488U, // PATCHABLE_RET - 1614U, // PATCHABLE_FUNCTION_EXIT - 1591U, // PATCHABLE_TAIL_CALL - 1543U, // PATCHABLE_EVENT_CALL - 1519U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDE - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SSUBO - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_BSWAP - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 0U, // ABS - 0U, // ADDSri - 0U, // ADDSrr - 0U, // ADDSrsi - 0U, // ADDSrsr - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 7292U, // ASRi - 7292U, // ASRr - 0U, // B - 0U, // BCCZi64 - 0U, // BCCi64 - 0U, // BMOVPCB_CALL - 0U, // BMOVPCRX_CALL - 0U, // BR_JTadd - 0U, // BR_JTm_i12 - 0U, // BR_JTm_rs - 0U, // BR_JTr - 0U, // BX_CALL - 0U, // CMP_SWAP_16 - 0U, // CMP_SWAP_32 - 0U, // CMP_SWAP_64 - 0U, // CMP_SWAP_8 - 0U, // CONSTPOOL_ENTRY - 0U, // COPY_STRUCT_BYVAL_I32 - 2001U, // CompilerBarrier - 16788832U, // ITasm - 0U, // Int_eh_sjlj_dispatchsetup - 0U, // Int_eh_sjlj_longjmp - 0U, // Int_eh_sjlj_setjmp - 0U, // Int_eh_sjlj_setjmp_nofp - 0U, // Int_eh_sjlj_setup_dispatch - 0U, // JUMPTABLE_ADDRS - 0U, // JUMPTABLE_INSTS - 0U, // JUMPTABLE_TBB - 0U, // JUMPTABLE_TBH - 0U, // LDMIA_RET - 15656U, // LDRBT_POST - 15443U, // LDRConstPool - 0U, // LDRLIT_ga_abs - 0U, // LDRLIT_ga_pcrel - 0U, // LDRLIT_ga_pcrel_ldr - 15735U, // LDRT_POST - 0U, // LEApcrel - 0U, // LEApcrelJT - 7013U, // LSLi - 7013U, // LSLr - 7299U, // LSRi - 7299U, // LSRr - 0U, // MEMCPY - 0U, // MLAv5 - 0U, // MOVCCi - 0U, // MOVCCi16 - 0U, // MOVCCi32imm - 0U, // MOVCCr - 0U, // MOVCCsi - 0U, // MOVCCsr - 0U, // MOVPCRX - 0U, // MOVTi16_ga_pcrel - 0U, // MOV_ga_pcrel - 0U, // MOV_ga_pcrel_ldr - 0U, // MOVi16_ga_pcrel - 0U, // MOVi32imm - 0U, // MOVsra_flag - 0U, // MOVsrl_flag - 0U, // MULv5 - 0U, // MVNCCi - 0U, // PICADD - 0U, // PICLDR - 0U, // PICLDRB - 0U, // PICLDRH - 0U, // PICLDRSB - 0U, // PICLDRSH - 0U, // PICSTR - 0U, // PICSTRB - 0U, // PICSTRH - 7278U, // RORi - 7278U, // RORr - 0U, // RRX - 20136U, // RRXi - 0U, // RSBSri - 0U, // RSBSrsi - 0U, // RSBSrsr - 0U, // SMLALv5 - 0U, // SMULLv5 - 0U, // SPACE - 15662U, // STRBT_POST - 0U, // STRBi_preidx - 0U, // STRBr_preidx - 0U, // STRH_preidx - 15746U, // STRT_POST - 0U, // STRi_preidx - 0U, // STRr_preidx - 0U, // SUBS_PC_LR - 0U, // SUBSri - 0U, // SUBSrr - 0U, // SUBSrsi - 0U, // SUBSrsr - 0U, // TAILJMPd - 0U, // TAILJMPr - 0U, // TAILJMPr4 - 0U, // TCRETURNdi - 0U, // TCRETURNri - 0U, // TPsoft - 0U, // UMLALv5 - 0U, // UMULLv5 - 153198U, // VLD1LNdAsm_16 - 284270U, // VLD1LNdAsm_32 - 415342U, // VLD1LNdAsm_8 - 153198U, // VLD1LNdWB_fixed_Asm_16 - 284270U, // VLD1LNdWB_fixed_Asm_32 - 415342U, // VLD1LNdWB_fixed_Asm_8 - 157294U, // VLD1LNdWB_register_Asm_16 - 288366U, // VLD1LNdWB_register_Asm_32 - 419438U, // VLD1LNdWB_register_Asm_8 - 153242U, // VLD2LNdAsm_16 - 284314U, // VLD2LNdAsm_32 - 415386U, // VLD2LNdAsm_8 - 153242U, // VLD2LNdWB_fixed_Asm_16 - 284314U, // VLD2LNdWB_fixed_Asm_32 - 415386U, // VLD2LNdWB_fixed_Asm_8 - 157338U, // VLD2LNdWB_register_Asm_16 - 288410U, // VLD2LNdWB_register_Asm_32 - 419482U, // VLD2LNdWB_register_Asm_8 - 153242U, // VLD2LNqAsm_16 - 284314U, // VLD2LNqAsm_32 - 153242U, // VLD2LNqWB_fixed_Asm_16 - 284314U, // VLD2LNqWB_fixed_Asm_32 - 157338U, // VLD2LNqWB_register_Asm_16 - 288410U, // VLD2LNqWB_register_Asm_32 - 1107457722U, // VLD3DUPdAsm_16 - 1107588794U, // VLD3DUPdAsm_32 - 1107719866U, // VLD3DUPdAsm_8 - 2181199546U, // VLD3DUPdWB_fixed_Asm_16 - 2181330618U, // VLD3DUPdWB_fixed_Asm_32 - 2181461690U, // VLD3DUPdWB_fixed_Asm_8 - 33707706U, // VLD3DUPdWB_register_Asm_16 - 33838778U, // VLD3DUPdWB_register_Asm_32 - 33969850U, // VLD3DUPdWB_register_Asm_8 - 1124234938U, // VLD3DUPqAsm_16 - 1124366010U, // VLD3DUPqAsm_32 - 1124497082U, // VLD3DUPqAsm_8 - 2197976762U, // VLD3DUPqWB_fixed_Asm_16 - 2198107834U, // VLD3DUPqWB_fixed_Asm_32 - 2198238906U, // VLD3DUPqWB_fixed_Asm_8 - 50484922U, // VLD3DUPqWB_register_Asm_16 - 50615994U, // VLD3DUPqWB_register_Asm_32 - 50747066U, // VLD3DUPqWB_register_Asm_8 - 153274U, // VLD3LNdAsm_16 - 284346U, // VLD3LNdAsm_32 - 415418U, // VLD3LNdAsm_8 - 153274U, // VLD3LNdWB_fixed_Asm_16 - 284346U, // VLD3LNdWB_fixed_Asm_32 - 415418U, // VLD3LNdWB_fixed_Asm_8 - 157370U, // VLD3LNdWB_register_Asm_16 - 288442U, // VLD3LNdWB_register_Asm_32 - 419514U, // VLD3LNdWB_register_Asm_8 - 153274U, // VLD3LNqAsm_16 - 284346U, // VLD3LNqAsm_32 - 153274U, // VLD3LNqWB_fixed_Asm_16 - 284346U, // VLD3LNqWB_fixed_Asm_32 - 157370U, // VLD3LNqWB_register_Asm_16 - 288442U, // VLD3LNqWB_register_Asm_32 - 3288495802U, // VLD3dAsm_16 - 3288626874U, // VLD3dAsm_32 - 3288757946U, // VLD3dAsm_8 - 3288495802U, // VLD3dWB_fixed_Asm_16 - 3288626874U, // VLD3dWB_fixed_Asm_32 - 3288757946U, // VLD3dWB_fixed_Asm_8 - 3288487610U, // VLD3dWB_register_Asm_16 - 3288618682U, // VLD3dWB_register_Asm_32 - 3288749754U, // VLD3dWB_register_Asm_8 - 1157789370U, // VLD3qAsm_16 - 1157920442U, // VLD3qAsm_32 - 1158051514U, // VLD3qAsm_8 - 2231531194U, // VLD3qWB_fixed_Asm_16 - 2231662266U, // VLD3qWB_fixed_Asm_32 - 2231793338U, // VLD3qWB_fixed_Asm_8 - 84039354U, // VLD3qWB_register_Asm_16 - 84170426U, // VLD3qWB_register_Asm_32 - 84301498U, // VLD3qWB_register_Asm_8 - 1174566609U, // VLD4DUPdAsm_16 - 1174697681U, // VLD4DUPdAsm_32 - 1174828753U, // VLD4DUPdAsm_8 - 2248308433U, // VLD4DUPdWB_fixed_Asm_16 - 2248439505U, // VLD4DUPdWB_fixed_Asm_32 - 2248570577U, // VLD4DUPdWB_fixed_Asm_8 - 100816593U, // VLD4DUPdWB_register_Asm_16 - 100947665U, // VLD4DUPdWB_register_Asm_32 - 101078737U, // VLD4DUPdWB_register_Asm_8 - 1191343825U, // VLD4DUPqAsm_16 - 1191474897U, // VLD4DUPqAsm_32 - 1191605969U, // VLD4DUPqAsm_8 - 2265085649U, // VLD4DUPqWB_fixed_Asm_16 - 2265216721U, // VLD4DUPqWB_fixed_Asm_32 - 2265347793U, // VLD4DUPqWB_fixed_Asm_8 - 117593809U, // VLD4DUPqWB_register_Asm_16 - 117724881U, // VLD4DUPqWB_register_Asm_32 - 117855953U, // VLD4DUPqWB_register_Asm_8 - 153297U, // VLD4LNdAsm_16 - 284369U, // VLD4LNdAsm_32 - 415441U, // VLD4LNdAsm_8 - 153297U, // VLD4LNdWB_fixed_Asm_16 - 284369U, // VLD4LNdWB_fixed_Asm_32 - 415441U, // VLD4LNdWB_fixed_Asm_8 - 157393U, // VLD4LNdWB_register_Asm_16 - 288465U, // VLD4LNdWB_register_Asm_32 - 419537U, // VLD4LNdWB_register_Asm_8 - 153297U, // VLD4LNqAsm_16 - 284369U, // VLD4LNqAsm_32 - 153297U, // VLD4LNqWB_fixed_Asm_16 - 284369U, // VLD4LNqWB_fixed_Asm_32 - 157393U, // VLD4LNqWB_register_Asm_16 - 288465U, // VLD4LNqWB_register_Asm_32 - 3355604689U, // VLD4dAsm_16 - 3355735761U, // VLD4dAsm_32 - 3355866833U, // VLD4dAsm_8 - 3355604689U, // VLD4dWB_fixed_Asm_16 - 3355735761U, // VLD4dWB_fixed_Asm_32 - 3355866833U, // VLD4dWB_fixed_Asm_8 - 3355596497U, // VLD4dWB_register_Asm_16 - 3355727569U, // VLD4dWB_register_Asm_32 - 3355858641U, // VLD4dWB_register_Asm_8 - 1224898257U, // VLD4qAsm_16 - 1225029329U, // VLD4qAsm_32 - 1225160401U, // VLD4qAsm_8 - 2298640081U, // VLD4qWB_fixed_Asm_16 - 2298771153U, // VLD4qWB_fixed_Asm_32 - 2298902225U, // VLD4qWB_fixed_Asm_8 - 151148241U, // VLD4qWB_register_Asm_16 - 151279313U, // VLD4qWB_register_Asm_32 - 151410385U, // VLD4qWB_register_Asm_8 - 0U, // VMOVD0 - 0U, // VMOVDcc - 0U, // VMOVQ0 - 0U, // VMOVScc - 153209U, // VST1LNdAsm_16 - 284281U, // VST1LNdAsm_32 - 415353U, // VST1LNdAsm_8 - 153209U, // VST1LNdWB_fixed_Asm_16 - 284281U, // VST1LNdWB_fixed_Asm_32 - 415353U, // VST1LNdWB_fixed_Asm_8 - 157305U, // VST1LNdWB_register_Asm_16 - 288377U, // VST1LNdWB_register_Asm_32 - 419449U, // VST1LNdWB_register_Asm_8 - 153269U, // VST2LNdAsm_16 - 284341U, // VST2LNdAsm_32 - 415413U, // VST2LNdAsm_8 - 153269U, // VST2LNdWB_fixed_Asm_16 - 284341U, // VST2LNdWB_fixed_Asm_32 - 415413U, // VST2LNdWB_fixed_Asm_8 - 157365U, // VST2LNdWB_register_Asm_16 - 288437U, // VST2LNdWB_register_Asm_32 - 419509U, // VST2LNdWB_register_Asm_8 - 153269U, // VST2LNqAsm_16 - 284341U, // VST2LNqAsm_32 - 153269U, // VST2LNqWB_fixed_Asm_16 - 284341U, // VST2LNqWB_fixed_Asm_32 - 157365U, // VST2LNqWB_register_Asm_16 - 288437U, // VST2LNqWB_register_Asm_32 - 153285U, // VST3LNdAsm_16 - 284357U, // VST3LNdAsm_32 - 415429U, // VST3LNdAsm_8 - 153285U, // VST3LNdWB_fixed_Asm_16 - 284357U, // VST3LNdWB_fixed_Asm_32 - 415429U, // VST3LNdWB_fixed_Asm_8 - 157381U, // VST3LNdWB_register_Asm_16 - 288453U, // VST3LNdWB_register_Asm_32 - 419525U, // VST3LNdWB_register_Asm_8 - 153285U, // VST3LNqAsm_16 - 284357U, // VST3LNqAsm_32 - 153285U, // VST3LNqWB_fixed_Asm_16 - 284357U, // VST3LNqWB_fixed_Asm_32 - 157381U, // VST3LNqWB_register_Asm_16 - 288453U, // VST3LNqWB_register_Asm_32 - 3288495813U, // VST3dAsm_16 - 3288626885U, // VST3dAsm_32 - 3288757957U, // VST3dAsm_8 - 3288495813U, // VST3dWB_fixed_Asm_16 - 3288626885U, // VST3dWB_fixed_Asm_32 - 3288757957U, // VST3dWB_fixed_Asm_8 - 3288487621U, // VST3dWB_register_Asm_16 - 3288618693U, // VST3dWB_register_Asm_32 - 3288749765U, // VST3dWB_register_Asm_8 - 1157789381U, // VST3qAsm_16 - 1157920453U, // VST3qAsm_32 - 1158051525U, // VST3qAsm_8 - 2231531205U, // VST3qWB_fixed_Asm_16 - 2231662277U, // VST3qWB_fixed_Asm_32 - 2231793349U, // VST3qWB_fixed_Asm_8 - 84039365U, // VST3qWB_register_Asm_16 - 84170437U, // VST3qWB_register_Asm_32 - 84301509U, // VST3qWB_register_Asm_8 - 153302U, // VST4LNdAsm_16 - 284374U, // VST4LNdAsm_32 - 415446U, // VST4LNdAsm_8 - 153302U, // VST4LNdWB_fixed_Asm_16 - 284374U, // VST4LNdWB_fixed_Asm_32 - 415446U, // VST4LNdWB_fixed_Asm_8 - 157398U, // VST4LNdWB_register_Asm_16 - 288470U, // VST4LNdWB_register_Asm_32 - 419542U, // VST4LNdWB_register_Asm_8 - 153302U, // VST4LNqAsm_16 - 284374U, // VST4LNqAsm_32 - 153302U, // VST4LNqWB_fixed_Asm_16 - 284374U, // VST4LNqWB_fixed_Asm_32 - 157398U, // VST4LNqWB_register_Asm_16 - 288470U, // VST4LNqWB_register_Asm_32 - 3355604694U, // VST4dAsm_16 - 3355735766U, // VST4dAsm_32 - 3355866838U, // VST4dAsm_8 - 3355604694U, // VST4dWB_fixed_Asm_16 - 3355735766U, // VST4dWB_fixed_Asm_32 - 3355866838U, // VST4dWB_fixed_Asm_8 - 3355596502U, // VST4dWB_register_Asm_16 - 3355727574U, // VST4dWB_register_Asm_32 - 3355858646U, // VST4dWB_register_Asm_8 - 1224898262U, // VST4qAsm_16 - 1225029334U, // VST4qAsm_32 - 1225160406U, // VST4qAsm_8 - 2298640086U, // VST4qWB_fixed_Asm_16 - 2298771158U, // VST4qWB_fixed_Asm_32 - 2298902230U, // VST4qWB_fixed_Asm_8 - 151148246U, // VST4qWB_register_Asm_16 - 151279318U, // VST4qWB_register_Asm_32 - 151410390U, // VST4qWB_register_Asm_8 - 0U, // WIN__CHKSTK - 0U, // WIN__DBZCHK - 0U, // t2ABS - 0U, // t2ADDSri - 0U, // t2ADDSrr - 0U, // t2ADDSrs - 0U, // t2BR_JT - 0U, // t2LDMIA_RET - 14508U, // t2LDRBpcrel - 15443U, // t2LDRConstPool - 14929U, // t2LDRHpcrel - 14526U, // t2LDRSBpcrel - 14948U, // t2LDRSHpcrel - 0U, // t2LDRpci_pic - 15443U, // t2LDRpcrel - 0U, // t2LEApcrel - 0U, // t2LEApcrelJT - 0U, // t2MOVCCasr - 0U, // t2MOVCCi - 0U, // t2MOVCCi16 - 0U, // t2MOVCCi32imm - 0U, // t2MOVCClsl - 0U, // t2MOVCClsr - 0U, // t2MOVCCr - 0U, // t2MOVCCror - 31992U, // t2MOVSsi - 23800U, // t2MOVSsr - 0U, // t2MOVTi16_ga_pcrel - 0U, // t2MOV_ga_pcrel - 0U, // t2MOVi16_ga_pcrel - 0U, // t2MOVi32imm - 32234U, // t2MOVsi - 24042U, // t2MOVsr - 0U, // t2MVNCCi - 0U, // t2RSBSri - 0U, // t2RSBSrs - 0U, // t2STRB_preidx - 0U, // t2STRH_preidx - 0U, // t2STR_preidx - 0U, // t2SUBSri - 0U, // t2SUBSrr - 0U, // t2SUBSrs - 0U, // t2TBB_JT - 0U, // t2TBH_JT - 0U, // tADCS - 0U, // tADDSi3 - 0U, // tADDSi8 - 0U, // tADDSrr - 0U, // tADDframe - 0U, // tADJCALLSTACKDOWN - 0U, // tADJCALLSTACKUP - 0U, // tBRIND - 0U, // tBR_JTr - 0U, // tBX_CALL - 0U, // tBX_RET - 0U, // tBX_RET_vararg - 0U, // tBfar - 0U, // tLDMIA_UPD - 15443U, // tLDRConstPool - 0U, // tLDRLIT_ga_abs - 0U, // tLDRLIT_ga_pcrel - 0U, // tLDR_postidx - 0U, // tLDRpci_pic - 0U, // tLEApcrel - 0U, // tLEApcrelJT - 0U, // tMOVCCr_pseudo - 0U, // tPOP_RET - 0U, // tSBCS - 0U, // tSUBSi3 - 0U, // tSUBSi8 - 0U, // tSUBSrr - 0U, // tTAILJMPd - 0U, // tTAILJMPdND - 0U, // tTAILJMPr - 0U, // tTBB_JT - 0U, // tTBH_JT - 0U, // tTPsoft - 530745U, // ADCri - 530745U, // ADCrr - 559417U, // ADCrsi - 39225U, // ADCrsr - 530806U, // ADDri - 530806U, // ADDrr - 559478U, // ADDrsi - 39286U, // ADDrsr - 539726U, // ADR - 1242211449U, // AESD - 1242211457U, // AESE - 1258988646U, // AESIMC - 1258988656U, // AESMC - 530859U, // ANDri - 530859U, // ANDrr - 559531U, // ANDrsi - 39339U, // ANDrsr - 555329U, // BFC - 547483U, // BFI - 530758U, // BICri - 530758U, // BICrr - 559430U, // BICrsi - 39238U, // BICrsr - 828725U, // BKPT - 828697U, // BL - 828772U, // BLX - 1074314916U, // BLX_pred - 828772U, // BLXi - 1074313964U, // BL_pred - 828768U, // BX - 1074313901U, // BXJ - 970304U, // BX_RET - 1074314816U, // BX_pred - 1074313296U, // Bcc - 201907225U, // CDP - 219210157U, // CDP2 - 3726U, // CLREX - 540368U, // CLZ - 539583U, // CMNri - 539583U, // CMNzrr - 555967U, // CMNzrsi - 547775U, // CMNzrsr - 539683U, // CMPri - 539683U, // CMPrr - 556067U, // CMPrsi - 547875U, // CMPrsr - 828709U, // CPS1p - 1309211869U, // CPS2p - 235470045U, // CPS3p - 185246891U, // CRC32B - 185246899U, // CRC32CB - 185246973U, // CRC32CH - 185247057U, // CRC32CW - 185246965U, // CRC32H - 185247049U, // CRC32W - 1074313739U, // DBG - 66762U, // DMB - 66767U, // DSB - 531562U, // EORri - 531562U, // EORrr - 560234U, // EORrsi - 40042U, // EORrsr - 838971U, // ERET - 1326595561U, // FCONSTD - 1326726633U, // FCONSTH - 1326857705U, // FCONSTS - 2332573243U, // FLDMXDB_UPD - 572932U, // FLDMXIA - 2332573188U, // FLDMXIA_UPD - 1625313U, // FMSTAT - 2332573251U, // FSTMXDB_UPD - 572940U, // FSTMXIA - 2332573196U, // FSTMXIA_UPD - 1074314610U, // HINT - 828720U, // HLT - 828638U, // HVC - 70868U, // ISB - 538616U, // LDA - 538701U, // LDAB - 540284U, // LDAEX - 538905U, // LDAEXB - 268974533U, // LDAEXD - 539263U, // LDAEXH - 539165U, // LDAH - 286975243U, // LDC2L_OFFSET - 3524977931U, // LDC2L_OPTION - 303752459U, // LDC2L_POST - 320529675U, // LDC2L_PRE - 286974356U, // LDC2_OFFSET - 3524977044U, // LDC2_OPTION - 303751572U, // LDC2_POST - 320528788U, // LDC2_PRE - 1275615989U, // LDCL_OFFSET - 1275615989U, // LDCL_OPTION - 1275615989U, // LDCL_POST - 1275615989U, // LDCL_PRE - 1275615549U, // LDC_OFFSET - 1275615549U, // LDC_OPTION - 1275615549U, // LDC_POST - 1275615549U, // LDC_PRE - 571388U, // LDMDA - 2332571644U, // LDMDA_UPD - 571519U, // LDMDB - 2332571775U, // LDMDB_UPD - 572300U, // LDMIA - 2332572556U, // LDMIA_UPD - 571538U, // LDMIB - 2332571794U, // LDMIB_UPD - 552232U, // LDRBT_POST_IMM - 552232U, // LDRBT_POST_REG - 551084U, // LDRB_POST_IMM - 551084U, // LDRB_POST_REG - 546988U, // LDRB_PRE_IMM - 551084U, // LDRB_PRE_REG - 555180U, // LDRBi12 - 546988U, // LDRBrs - 551343U, // LDRD - 580015U, // LDRD_POST - 580015U, // LDRD_PRE - 540296U, // LDREX - 538919U, // LDREXB - 268974547U, // LDREXD - 539277U, // LDREXH - 547409U, // LDRH - 548171U, // LDRHTi - 552267U, // LDRHTr - 551505U, // LDRH_POST - 551505U, // LDRH_PRE - 547006U, // LDRSB - 548148U, // LDRSBTi - 552244U, // LDRSBTr - 551102U, // LDRSB_POST - 551102U, // LDRSB_PRE - 547428U, // LDRSH - 548183U, // LDRSHTi - 552279U, // LDRSHTr - 551524U, // LDRSH_POST - 551524U, // LDRSH_PRE - 552311U, // LDRT_POST_IMM - 552311U, // LDRT_POST_REG - 552019U, // LDR_POST_IMM - 552019U, // LDR_POST_REG - 547923U, // LDR_PRE_IMM - 552019U, // LDR_PRE_REG - 556115U, // LDRcp - 556115U, // LDRi12 - 547923U, // LDRrs - 201907274U, // MCR - 168878515U, // MCR2 - 201878642U, // MCRR - 168878521U, // MCRR2 - 559140U, // MLA - 548021U, // MLS - 1887722U, // MOVPCLR - 556471U, // MOVTi16 - 544234U, // MOVi - 540159U, // MOVi16 - 544234U, // MOVr - 544234U, // MOVr_TC - 531946U, // MOVsi - 560618U, // MOVsr - 336124238U, // MRC - 74138U, // MRC2 - 352872786U, // MRRC - 78240U, // MRRC2 - 2148056290U, // MRS - 539874U, // MRSbanked - 3221798114U, // MRSsys - 369638536U, // MSR - 386415752U, // MSRbanked - 369638536U, // MSRi - 531317U, // MUL - 543747U, // MVNi - 543747U, // MVNr - 531459U, // MVNsi - 560131U, // MVNsr - 531576U, // ORRri - 531576U, // ORRrr - 560248U, // ORRrsi - 40056U, // ORRrsr - 548115U, // PKHBT - 547023U, // PKHTB - 83290U, // PLDWi12 - 87386U, // PLDWrs - 83171U, // PLDi12 - 87267U, // PLDrs - 83206U, // PLIi12 - 87302U, // PLIrs - 555406U, // QADD - 554800U, // QADD16 - 554903U, // QADD8 - 556729U, // QASX - 555380U, // QDADD - 555252U, // QDSUB - 556588U, // QSAX - 555265U, // QSUB - 554762U, // QSUB16 - 554864U, // QSUB8 - 539998U, // RBIT - 540118U, // REV - 538452U, // REV16 - 539247U, // REVSH - 828573U, // RFEDA - 2008221U, // RFEDA_UPD - 828604U, // RFEDB - 2008252U, // RFEDB_UPD - 828580U, // RFEIA - 2008228U, // RFEIA_UPD - 828611U, // RFEIB - 2008259U, // RFEIB_UPD - 530624U, // RSBri - 530624U, // RSBrr - 559296U, // RSBrsi - 39104U, // RSBrsr - 530775U, // RSCri - 530775U, // RSCrr - 559447U, // RSCrsi - 39255U, // RSCrsr - 554807U, // SADD16 - 554909U, // SADD8 - 556734U, // SASX - 530741U, // SBCri - 530741U, // SBCrr - 559413U, // SBCrsi - 39221U, // SBCrsr - 548506U, // SBFX - 556506U, // SDIV - 555794U, // SEL - 91368U, // SETEND - 828701U, // SETPAN - 168468546U, // SHA1C - 1258987596U, // SHA1H - 168468578U, // SHA1M - 168468588U, // SHA1P - 168468481U, // SHA1SU0 - 1242210331U, // SHA1SU1 - 168468566U, // SHA256H - 168468533U, // SHA256H2 - 1242210317U, // SHA256SU0 - 168468519U, // SHA256SU1 - 554783U, // SHADD16 - 554888U, // SHADD8 - 556716U, // SHASX - 556575U, // SHSAX - 554745U, // SHSUB16 - 554849U, // SHSUB8 - 1074313546U, // SMC - 546910U, // SMLABB - 548108U, // SMLABT - 547171U, // SMLAD - 548432U, // SMLADX - 96984U, // SMLAL - 579685U, // SMLALBB - 580889U, // SMLALBT - 579992U, // SMLALD - 581214U, // SMLALDX - 579797U, // SMLALTB - 581011U, // SMLALTT - 547016U, // SMLATB - 548236U, // SMLATT - 547083U, // SMLAWB - 548284U, // SMLAWT - 547257U, // SMLSD - 548462U, // SMLSDX - 580003U, // SMLSLD - 581222U, // SMLSLDX - 546850U, // SMMLA - 547907U, // SMMLAR - 548019U, // SMMLS - 547968U, // SMMLSR - 555891U, // SMMUL - 556130U, // SMMULR - 555369U, // SMUAD - 556631U, // SMUADX - 555117U, // SMULBB - 556321U, // SMULBT - 559946U, // SMULL - 555229U, // SMULTB - 556443U, // SMULTT - 555282U, // SMULWB - 556483U, // SMULWT - 555455U, // SMUSD - 556661U, // SMUSDX - 828836U, // SRSDA - 828788U, // SRSDA_UPD - 828858U, // SRSDB - 828812U, // SRSDB_UPD - 828847U, // SRSIA - 828800U, // SRSIA_UPD - 828869U, // SRSIB - 828824U, // SRSIB_UPD - 548093U, // SSAT - 554821U, // SSAT16 - 556593U, // SSAX - 554769U, // SSUB16 - 554870U, // SSUB8 - 286975250U, // STC2L_OFFSET - 3524977938U, // STC2L_OPTION - 303752466U, // STC2L_POST - 320529682U, // STC2L_PRE - 286974375U, // STC2_OFFSET - 3524977063U, // STC2_OPTION - 303751591U, // STC2_POST - 320528807U, // STC2_PRE - 1275615994U, // STCL_OFFSET - 1275615994U, // STCL_OPTION - 1275615994U, // STCL_POST - 1275615994U, // STCL_PRE - 1275615579U, // STC_OFFSET - 1275615579U, // STC_OPTION - 1275615579U, // STC_POST - 1275615579U, // STC_PRE - 539503U, // STL - 538782U, // STLB - 556674U, // STLEX - 555296U, // STLEXB - 555468U, // STLEXD - 555654U, // STLEXH - 539195U, // STLH - 571394U, // STMDA - 2332571650U, // STMDA_UPD - 571526U, // STMDB - 2332571782U, // STMDB_UPD - 572306U, // STMIA - 2332572562U, // STMIA_UPD - 571544U, // STMIB - 2332571800U, // STMIB_UPD - 185101614U, // STRBT_POST_IMM - 185101614U, // STRBT_POST_REG - 185100465U, // STRB_POST_IMM - 185100465U, // STRB_POST_REG - 185096369U, // STRB_PRE_IMM - 185100465U, // STRB_PRE_REG - 555185U, // STRBi12 - 546993U, // STRBrs - 551348U, // STRD - 185129396U, // STRD_POST - 185129396U, // STRD_PRE - 556692U, // STREX - 555310U, // STREXB - 555482U, // STREXD - 555668U, // STREXH - 547414U, // STRH - 185097553U, // STRHTi - 185101649U, // STRHTr - 185100886U, // STRH_POST - 185100886U, // STRH_PRE - 185101698U, // STRT_POST_IMM - 185101698U, // STRT_POST_REG - 185101460U, // STR_POST_IMM - 185101460U, // STR_POST_REG - 185097364U, // STR_PRE_IMM - 185101460U, // STR_PRE_REG - 556180U, // STRi12 - 547988U, // STRrs - 530678U, // SUBri - 530678U, // SUBrr - 559350U, // SUBrsi - 39158U, // SUBrsr - 1074313567U, // SVC - 556081U, // SWP - 555175U, // SWPB - 546898U, // SXTAB - 546523U, // SXTAB16 - 547371U, // SXTAH - 555242U, // SXTB - 554731U, // SXTB16 - 555637U, // SXTH - 539711U, // TEQri - 539711U, // TEQrr - 556095U, // TEQrsi - 547903U, // TEQrsr - 3092U, // TRAP - 3092U, // TRAPNaCl - 99545U, // TSB - 540040U, // TSTri - 540040U, // TSTrr - 556424U, // TSTrsi - 548232U, // TSTrsr - 554814U, // UADD16 - 554915U, // UADD8 - 556739U, // UASX - 548511U, // UBFX - 828656U, // UDF - 556511U, // UDIV - 554791U, // UHADD16 - 554895U, // UHADD8 - 556722U, // UHASX - 556581U, // UHSAX - 554753U, // UHSUB16 - 554856U, // UHSUB8 - 580285U, // UMAAL - 96990U, // UMLAL - 559952U, // UMULL - 554799U, // UQADD16 - 554902U, // UQADD8 - 556728U, // UQASX - 556587U, // UQSAX - 554761U, // UQSUB16 - 554863U, // UQSUB8 - 554882U, // USAD8 - 546650U, // USADA8 - 548098U, // USAT - 554828U, // USAT16 - 556598U, // USAX - 554776U, // USUB16 - 554876U, // USUB8 - 546904U, // UXTAB - 546531U, // UXTAB16 - 547377U, // UXTAH - 555247U, // UXTB - 554738U, // UXTB16 - 555642U, // UXTH - 169892547U, // VABALsv2i64 - 170023619U, // VABALsv4i32 - 170154691U, // VABALsv8i16 - 170285763U, // VABALuv2i64 - 170416835U, // VABALuv4i32 - 170547907U, // VABALuv8i16 - 170153971U, // VABAsv16i8 - 169891827U, // VABAsv2i32 - 170022899U, // VABAsv4i16 - 169891827U, // VABAsv4i32 - 170022899U, // VABAsv8i16 - 170153971U, // VABAsv8i8 - 170547187U, // VABAuv16i8 - 170285043U, // VABAuv2i32 - 170416115U, // VABAuv4i16 - 170285043U, // VABAuv4i32 - 170416115U, // VABAuv8i16 - 170547187U, // VABAuv8i8 - 186678015U, // VABDLsv2i64 - 186809087U, // VABDLsv4i32 - 186940159U, // VABDLsv8i16 - 187071231U, // VABDLuv2i64 - 187202303U, // VABDLuv4i32 - 187333375U, // VABDLuv8i16 - 253131119U, // VABDfd - 253131119U, // VABDfq - 253000047U, // VABDhd - 253000047U, // VABDhq - 186939759U, // VABDsv16i8 - 186677615U, // VABDsv2i32 - 186808687U, // VABDsv4i16 - 186677615U, // VABDsv4i32 - 186808687U, // VABDsv8i16 - 186939759U, // VABDsv8i8 - 187332975U, // VABDuv16i8 - 187070831U, // VABDuv2i32 - 187201903U, // VABDuv4i16 - 187070831U, // VABDuv4i32 - 187201903U, // VABDuv8i16 - 187332975U, // VABDuv8i8 - 252853412U, // VABSD - 252984484U, // VABSH - 253115556U, // VABSS - 253115556U, // VABSfd - 253115556U, // VABSfq - 252984484U, // VABShd - 252984484U, // VABShq - 1260666020U, // VABSv16i8 - 1260403876U, // VABSv2i32 - 1260534948U, // VABSv4i16 - 1260403876U, // VABSv4i32 - 1260534948U, // VABSv8i16 - 1260666020U, // VABSv8i8 - 253131233U, // VACGEfd - 253131233U, // VACGEfq - 253000161U, // VACGEhd - 253000161U, // VACGEhq - 253132096U, // VACGTfd - 253132096U, // VACGTfq - 253001024U, // VACGThd - 253001024U, // VACGThq - 252869011U, // VADDD - 253000083U, // VADDH - 187464621U, // VADDHNv2i32 - 187595693U, // VADDHNv4i16 - 187726765U, // VADDHNv8i8 - 186678028U, // VADDLsv2i64 - 186809100U, // VADDLsv4i32 - 186940172U, // VADDLsv8i16 - 187071244U, // VADDLuv2i64 - 187202316U, // VADDLuv4i32 - 187333388U, // VADDLuv8i16 - 253131155U, // VADDS - 186678772U, // VADDWsv2i64 - 186809844U, // VADDWsv4i32 - 186940916U, // VADDWsv8i16 - 187071988U, // VADDWuv2i64 - 187203060U, // VADDWuv4i32 - 187334132U, // VADDWuv8i16 - 253131155U, // VADDfd - 253131155U, // VADDfq - 253000083U, // VADDhd - 253000083U, // VADDhq - 187857299U, // VADDv16i8 - 187464083U, // VADDv1i64 - 187595155U, // VADDv2i32 - 187464083U, // VADDv2i64 - 187726227U, // VADDv4i16 - 187595155U, // VADDv4i32 - 187726227U, // VADDv8i16 - 187857299U, // VADDv8i8 - 555434U, // VANDd - 555434U, // VANDq - 555333U, // VBICd - 405698885U, // VBICiv2i32 - 405829957U, // VBICiv4i16 - 405698885U, // VBICiv4i32 - 405829957U, // VBICiv8i16 - 555333U, // VBICq - 547334U, // VBIFd - 547334U, // VBIFq - 548195U, // VBITd - 548195U, // VBITq - 547676U, // VBSLd - 547676U, // VBSLq - 185245957U, // VCADDv2f32 - 185246658U, // VCADDv4f16 - 185245957U, // VCADDv4f32 - 185246658U, // VCADDv8f16 - 253131834U, // VCEQfd - 253131834U, // VCEQfq - 253000762U, // VCEQhd - 253000762U, // VCEQhq - 187857978U, // VCEQv16i8 - 187595834U, // VCEQv2i32 - 187726906U, // VCEQv4i16 - 187595834U, // VCEQv4i32 - 187726906U, // VCEQv8i16 - 187857978U, // VCEQv8i8 - 1261583418U, // VCEQzv16i8 - 253115450U, // VCEQzv2f32 - 1261321274U, // VCEQzv2i32 - 252984378U, // VCEQzv4f16 - 253115450U, // VCEQzv4f32 - 1261452346U, // VCEQzv4i16 - 1261321274U, // VCEQzv4i32 - 252984378U, // VCEQzv8f16 - 1261452346U, // VCEQzv8i16 - 1261583418U, // VCEQzv8i8 - 253131239U, // VCGEfd - 253131239U, // VCGEfq - 253000167U, // VCGEhd - 253000167U, // VCGEhq - 186939879U, // VCGEsv16i8 - 186677735U, // VCGEsv2i32 - 186808807U, // VCGEsv4i16 - 186677735U, // VCGEsv4i32 - 186808807U, // VCGEsv8i16 - 186939879U, // VCGEsv8i8 - 187333095U, // VCGEuv16i8 - 187070951U, // VCGEuv2i32 - 187202023U, // VCGEuv4i16 - 187070951U, // VCGEuv4i32 - 187202023U, // VCGEuv8i16 - 187333095U, // VCGEuv8i8 - 1260665319U, // VCGEzv16i8 - 253114855U, // VCGEzv2f32 - 1260403175U, // VCGEzv2i32 - 252983783U, // VCGEzv4f16 - 253114855U, // VCGEzv4f32 - 1260534247U, // VCGEzv4i16 - 1260403175U, // VCGEzv4i32 - 252983783U, // VCGEzv8f16 - 1260534247U, // VCGEzv8i16 - 1260665319U, // VCGEzv8i8 - 253132102U, // VCGTfd - 253132102U, // VCGTfq - 253001030U, // VCGThd - 253001030U, // VCGThq - 186940742U, // VCGTsv16i8 - 186678598U, // VCGTsv2i32 - 186809670U, // VCGTsv4i16 - 186678598U, // VCGTsv4i32 - 186809670U, // VCGTsv8i16 - 186940742U, // VCGTsv8i8 - 187333958U, // VCGTuv16i8 - 187071814U, // VCGTuv2i32 - 187202886U, // VCGTuv4i16 - 187071814U, // VCGTuv4i32 - 187202886U, // VCGTuv8i16 - 187333958U, // VCGTuv8i8 - 1260666182U, // VCGTzv16i8 - 253115718U, // VCGTzv2f32 - 1260404038U, // VCGTzv2i32 - 252984646U, // VCGTzv4f16 - 253115718U, // VCGTzv4f32 - 1260535110U, // VCGTzv4i16 - 1260404038U, // VCGTzv4i32 - 252984646U, // VCGTzv8f16 - 1260535110U, // VCGTzv8i16 - 1260666182U, // VCGTzv8i8 - 1260665324U, // VCLEzv16i8 - 253114860U, // VCLEzv2f32 - 1260403180U, // VCLEzv2i32 - 252983788U, // VCLEzv4f16 - 253114860U, // VCLEzv4f32 - 1260534252U, // VCLEzv4i16 - 1260403180U, // VCLEzv4i32 - 252983788U, // VCLEzv8f16 - 1260534252U, // VCLEzv8i16 - 1260665324U, // VCLEzv8i8 - 1260666030U, // VCLSv16i8 - 1260403886U, // VCLSv2i32 - 1260534958U, // VCLSv4i16 - 1260403886U, // VCLSv4i32 - 1260534958U, // VCLSv8i16 - 1260666030U, // VCLSv8i8 - 1260666216U, // VCLTzv16i8 - 253115752U, // VCLTzv2f32 - 1260404072U, // VCLTzv2i32 - 252984680U, // VCLTzv4f16 - 253115752U, // VCLTzv4f32 - 1260535144U, // VCLTzv4i16 - 1260404072U, // VCLTzv4i32 - 252984680U, // VCLTzv8f16 - 1260535144U, // VCLTzv8i16 - 1260666216U, // VCLTzv8i8 - 1261584079U, // VCLZv16i8 - 1261321935U, // VCLZv2i32 - 1261453007U, // VCLZv4i16 - 1261321935U, // VCLZv4i32 - 1261453007U, // VCLZv8i16 - 1261584079U, // VCLZv8i8 - 168468718U, // VCMLAv2f32 - 168468718U, // VCMLAv2f32_indexed - 168469419U, // VCMLAv4f16 - 168469419U, // VCMLAv4f16_indexed - 168468718U, // VCMLAv4f32 - 168468718U, // VCMLAv4f32_indexed - 168469419U, // VCMLAv8f16 - 168469419U, // VCMLAv8f16_indexed - 252853282U, // VCMPD - 252852728U, // VCMPED - 252983800U, // VCMPEH - 253114872U, // VCMPES - 420657656U, // VCMPEZD - 420788728U, // VCMPEZH - 420919800U, // VCMPEZS - 252984354U, // VCMPH - 253115426U, // VCMPS - 420658210U, // VCMPZD - 420789282U, // VCMPZH - 420920354U, // VCMPZS - 408941U, // VCNTd - 408941U, // VCNTq - 1258987638U, // VCVTANSDf - 1258988339U, // VCVTANSDh - 1258987638U, // VCVTANSQf - 1258988339U, // VCVTANSQh - 1258987698U, // VCVTANUDf - 1258988399U, // VCVTANUDh - 1258987698U, // VCVTANUQf - 1258988399U, // VCVTANUQh - 1258987968U, // VCVTASD - 1258988219U, // VCVTASH - 1258987638U, // VCVTASS - 1258988028U, // VCVTAUD - 1258988279U, // VCVTAUH - 1258987698U, // VCVTAUS - 3422436U, // VCVTBDH - 3553508U, // VCVTBHD - 3684580U, // VCVTBHS - 3815652U, // VCVTBSH - 3947954U, // VCVTDS - 1258987653U, // VCVTMNSDf - 1258988354U, // VCVTMNSDh - 1258987653U, // VCVTMNSQf - 1258988354U, // VCVTMNSQh - 1258987713U, // VCVTMNUDf - 1258988414U, // VCVTMNUDh - 1258987713U, // VCVTMNUQf - 1258988414U, // VCVTMNUQh - 1258987983U, // VCVTMSD - 1258988234U, // VCVTMSH - 1258987653U, // VCVTMSS - 1258988043U, // VCVTMUD - 1258988294U, // VCVTMUH - 1258987713U, // VCVTMUS - 1258987668U, // VCVTNNSDf - 1258988369U, // VCVTNNSDh - 1258987668U, // VCVTNNSQf - 1258988369U, // VCVTNNSQh - 1258987728U, // VCVTNNUDf - 1258988429U, // VCVTNNUDh - 1258987728U, // VCVTNNUQf - 1258988429U, // VCVTNNUQh - 1258987998U, // VCVTNSD - 1258988249U, // VCVTNSH - 1258987668U, // VCVTNSS - 1258988058U, // VCVTNUD - 1258988309U, // VCVTNUH - 1258987728U, // VCVTNUS - 1258987683U, // VCVTPNSDf - 1258988384U, // VCVTPNSDh - 1258987683U, // VCVTPNSQf - 1258988384U, // VCVTPNSQh - 1258987743U, // VCVTPNUDf - 1258988444U, // VCVTPNUDh - 1258987743U, // VCVTPNUQf - 1258988444U, // VCVTPNUQh - 1258988013U, // VCVTPSD - 1258988264U, // VCVTPSH - 1258987683U, // VCVTPSS - 1258988073U, // VCVTPUD - 1258988324U, // VCVTPUH - 1258987743U, // VCVTPUS - 4079026U, // VCVTSD - 3423654U, // VCVTTDH - 3554726U, // VCVTTHD - 3685798U, // VCVTTHS - 3816870U, // VCVTTSH - 3816882U, // VCVTf2h - 440417714U, // VCVTf2sd - 440417714U, // VCVTf2sq - 440548786U, // VCVTf2ud - 440548786U, // VCVTf2uq - 2403368370U, // VCVTf2xsd - 2403368370U, // VCVTf2xsq - 2403499442U, // VCVTf2xud - 2403499442U, // VCVTf2xuq - 3685810U, // VCVTh2f - 440679858U, // VCVTh2sd - 440679858U, // VCVTh2sq - 440810930U, // VCVTh2ud - 440810930U, // VCVTh2uq - 2403630514U, // VCVTh2xsd - 2403630514U, // VCVTh2xsq - 2403761586U, // VCVTh2xud - 2403761586U, // VCVTh2xuq - 440942002U, // VCVTs2fd - 440942002U, // VCVTs2fq - 441073074U, // VCVTs2hd - 441073074U, // VCVTs2hq - 441204146U, // VCVTu2fd - 441204146U, // VCVTu2fq - 441335218U, // VCVTu2hd - 441335218U, // VCVTu2hq - 2403892658U, // VCVTxs2fd - 2403892658U, // VCVTxs2fq - 2404023730U, // VCVTxs2hd - 2404023730U, // VCVTxs2hq - 2404154802U, // VCVTxu2fd - 2404154802U, // VCVTxu2fq - 2404285874U, // VCVTxu2hd - 2404285874U, // VCVTxu2hq - 252870116U, // VDIVD - 253001188U, // VDIVH - 253132260U, // VDIVS - 146475U, // VDUP16d - 146475U, // VDUP16q - 277547U, // VDUP32d - 277547U, // VDUP32q - 408619U, // VDUP8d - 408619U, // VDUP8q - 162859U, // VDUPLN16d - 162859U, // VDUPLN16q - 293931U, // VDUPLN32d - 293931U, // VDUPLN32q - 425003U, // VDUPLN8d - 425003U, // VDUPLN8q - 556137U, // VEORd - 556137U, // VEORq - 155082U, // VEXTd16 - 286154U, // VEXTd32 - 417226U, // VEXTd8 - 155082U, // VEXTq16 - 286154U, // VEXTq32 - 5266890U, // VEXTq64 - 417226U, // VEXTq8 - 2400344115U, // VFMAD - 2400475187U, // VFMAH - 2400606259U, // VFMAS - 2400606259U, // VFMAfd - 2400606259U, // VFMAfq - 2400475187U, // VFMAhd - 2400475187U, // VFMAhq - 2400345284U, // VFMSD - 2400476356U, // VFMSH - 2400607428U, // VFMSS - 2400607428U, // VFMSfd - 2400607428U, // VFMSfq - 2400476356U, // VFMShd - 2400476356U, // VFMShq - 2400344120U, // VFNMAD - 2400475192U, // VFNMAH - 2400606264U, // VFNMAS - 2400345289U, // VFNMSD - 2400476361U, // VFNMSH - 2400607433U, // VFNMSS - 294377U, // VGETLNi32 - 3408035305U, // VGETLNs16 - 3408166377U, // VGETLNs8 - 3408428521U, // VGETLNu16 - 3408559593U, // VGETLNu8 - 186939777U, // VHADDsv16i8 - 186677633U, // VHADDsv2i32 - 186808705U, // VHADDsv4i16 - 186677633U, // VHADDsv4i32 - 186808705U, // VHADDsv8i16 - 186939777U, // VHADDsv8i8 - 187332993U, // VHADDuv16i8 - 187070849U, // VHADDuv2i32 - 187201921U, // VHADDuv4i16 - 187070849U, // VHADDuv4i32 - 187201921U, // VHADDuv8i16 - 187332993U, // VHADDuv8i8 - 186939642U, // VHSUBsv16i8 - 186677498U, // VHSUBsv2i32 - 186808570U, // VHSUBsv4i16 - 186677498U, // VHSUBsv4i32 - 186808570U, // VHSUBsv8i16 - 186939642U, // VHSUBsv8i8 - 187332858U, // VHSUBuv16i8 - 187070714U, // VHSUBuv2i32 - 187201786U, // VHSUBuv4i16 - 187070714U, // VHSUBuv4i32 - 187201786U, // VHSUBuv8i16 - 187332858U, // VHSUBuv8i8 - 1258988577U, // VINSH - 441597356U, // VJCVT - 3674371694U, // VLD1DUPd16 - 453138030U, // VLD1DUPd16wb_fixed - 453142126U, // VLD1DUPd16wb_register - 3674502766U, // VLD1DUPd32 - 453269102U, // VLD1DUPd32wb_fixed - 453273198U, // VLD1DUPd32wb_register - 3674633838U, // VLD1DUPd8 - 453400174U, // VLD1DUPd8wb_fixed - 453404270U, // VLD1DUPd8wb_register - 3691148910U, // VLD1DUPq16 - 469915246U, // VLD1DUPq16wb_fixed - 469919342U, // VLD1DUPq16wb_register - 3691279982U, // VLD1DUPq32 - 470046318U, // VLD1DUPq32wb_fixed - 470050414U, // VLD1DUPq32wb_register - 3691411054U, // VLD1DUPq8 - 470177390U, // VLD1DUPq8wb_fixed - 470181486U, // VLD1DUPq8wb_register - 1079273070U, // VLD1LNd16 - 1079350894U, // VLD1LNd16_UPD - 1079404142U, // VLD1LNd32 - 1079481966U, // VLD1LNd32_UPD - 1079535214U, // VLD1LNd8 - 1079613038U, // VLD1LNd8_UPD - 0U, // VLD1LNq16Pseudo - 0U, // VLD1LNq16Pseudo_UPD - 0U, // VLD1LNq32Pseudo - 0U, // VLD1LNq32Pseudo_UPD - 0U, // VLD1LNq8Pseudo - 0U, // VLD1LNq8Pseudo_UPD - 3707926126U, // VLD1d16 - 3355604590U, // VLD1d16Q - 0U, // VLD1d16QPseudo - 134370926U, // VLD1d16Qwb_fixed - 134375022U, // VLD1d16Qwb_register - 3288495726U, // VLD1d16T - 0U, // VLD1d16TPseudo - 67262062U, // VLD1d16Twb_fixed - 67266158U, // VLD1d16Twb_register - 486692462U, // VLD1d16wb_fixed - 486696558U, // VLD1d16wb_register - 3708057198U, // VLD1d32 - 3355735662U, // VLD1d32Q - 0U, // VLD1d32QPseudo - 134501998U, // VLD1d32Qwb_fixed - 134506094U, // VLD1d32Qwb_register - 3288626798U, // VLD1d32T - 0U, // VLD1d32TPseudo - 67393134U, // VLD1d32Twb_fixed - 67397230U, // VLD1d32Twb_register - 486823534U, // VLD1d32wb_fixed - 486827630U, // VLD1d32wb_register - 3713037934U, // VLD1d64 - 3360716398U, // VLD1d64Q - 0U, // VLD1d64QPseudo - 0U, // VLD1d64QPseudoWB_fixed - 0U, // VLD1d64QPseudoWB_register - 139482734U, // VLD1d64Qwb_fixed - 139486830U, // VLD1d64Qwb_register - 3293607534U, // VLD1d64T - 0U, // VLD1d64TPseudo - 0U, // VLD1d64TPseudoWB_fixed - 0U, // VLD1d64TPseudoWB_register - 72373870U, // VLD1d64Twb_fixed - 72377966U, // VLD1d64Twb_register - 491804270U, // VLD1d64wb_fixed - 491808366U, // VLD1d64wb_register - 3708188270U, // VLD1d8 - 3355866734U, // VLD1d8Q - 0U, // VLD1d8QPseudo - 134633070U, // VLD1d8Qwb_fixed - 134637166U, // VLD1d8Qwb_register - 3288757870U, // VLD1d8T - 0U, // VLD1d8TPseudo - 67524206U, // VLD1d8Twb_fixed - 67528302U, // VLD1d8Twb_register - 486954606U, // VLD1d8wb_fixed - 486958702U, // VLD1d8wb_register - 3724703342U, // VLD1q16 - 0U, // VLD1q16HighQPseudo - 0U, // VLD1q16HighTPseudo - 0U, // VLD1q16LowQPseudo_UPD - 0U, // VLD1q16LowTPseudo_UPD - 503469678U, // VLD1q16wb_fixed - 503473774U, // VLD1q16wb_register - 3724834414U, // VLD1q32 - 0U, // VLD1q32HighQPseudo - 0U, // VLD1q32HighTPseudo - 0U, // VLD1q32LowQPseudo_UPD - 0U, // VLD1q32LowTPseudo_UPD - 503600750U, // VLD1q32wb_fixed - 503604846U, // VLD1q32wb_register - 3729815150U, // VLD1q64 - 0U, // VLD1q64HighQPseudo - 0U, // VLD1q64HighTPseudo - 0U, // VLD1q64LowQPseudo_UPD - 0U, // VLD1q64LowTPseudo_UPD - 508581486U, // VLD1q64wb_fixed - 508585582U, // VLD1q64wb_register - 3724965486U, // VLD1q8 - 0U, // VLD1q8HighQPseudo - 0U, // VLD1q8HighTPseudo - 0U, // VLD1q8LowQPseudo_UPD - 0U, // VLD1q8LowTPseudo_UPD - 503731822U, // VLD1q8wb_fixed - 503735918U, // VLD1q8wb_register - 3691148954U, // VLD2DUPd16 - 469915290U, // VLD2DUPd16wb_fixed - 469919386U, // VLD2DUPd16wb_register - 3741480602U, // VLD2DUPd16x2 - 520246938U, // VLD2DUPd16x2wb_fixed - 520251034U, // VLD2DUPd16x2wb_register - 3691280026U, // VLD2DUPd32 - 470046362U, // VLD2DUPd32wb_fixed - 470050458U, // VLD2DUPd32wb_register - 3741611674U, // VLD2DUPd32x2 - 520378010U, // VLD2DUPd32x2wb_fixed - 520382106U, // VLD2DUPd32x2wb_register - 3691411098U, // VLD2DUPd8 - 470177434U, // VLD2DUPd8wb_fixed - 470181530U, // VLD2DUPd8wb_register - 3741742746U, // VLD2DUPd8x2 - 520509082U, // VLD2DUPd8x2wb_fixed - 520513178U, // VLD2DUPd8x2wb_register - 0U, // VLD2DUPq16EvenPseudo - 0U, // VLD2DUPq16OddPseudo - 0U, // VLD2DUPq32EvenPseudo - 0U, // VLD2DUPq32OddPseudo - 0U, // VLD2DUPq8EvenPseudo - 0U, // VLD2DUPq8OddPseudo - 1079350938U, // VLD2LNd16 - 0U, // VLD2LNd16Pseudo - 0U, // VLD2LNd16Pseudo_UPD - 1079355034U, // VLD2LNd16_UPD - 1079482010U, // VLD2LNd32 - 0U, // VLD2LNd32Pseudo - 0U, // VLD2LNd32Pseudo_UPD - 1079486106U, // VLD2LNd32_UPD - 1079613082U, // VLD2LNd8 - 0U, // VLD2LNd8Pseudo - 0U, // VLD2LNd8Pseudo_UPD - 1079617178U, // VLD2LNd8_UPD - 1079350938U, // VLD2LNq16 - 0U, // VLD2LNq16Pseudo - 0U, // VLD2LNq16Pseudo_UPD - 1079355034U, // VLD2LNq16_UPD - 1079482010U, // VLD2LNq32 - 0U, // VLD2LNq32Pseudo - 0U, // VLD2LNq32Pseudo_UPD - 1079486106U, // VLD2LNq32_UPD - 3758257818U, // VLD2b16 - 537024154U, // VLD2b16wb_fixed - 537028250U, // VLD2b16wb_register - 3758388890U, // VLD2b32 - 537155226U, // VLD2b32wb_fixed - 537159322U, // VLD2b32wb_register - 3758519962U, // VLD2b8 - 537286298U, // VLD2b8wb_fixed - 537290394U, // VLD2b8wb_register - 3724703386U, // VLD2d16 - 503469722U, // VLD2d16wb_fixed - 503473818U, // VLD2d16wb_register - 3724834458U, // VLD2d32 - 503600794U, // VLD2d32wb_fixed - 503604890U, // VLD2d32wb_register - 3724965530U, // VLD2d8 - 503731866U, // VLD2d8wb_fixed - 503735962U, // VLD2d8wb_register - 3355604634U, // VLD2q16 - 0U, // VLD2q16Pseudo - 0U, // VLD2q16PseudoWB_fixed - 0U, // VLD2q16PseudoWB_register - 134370970U, // VLD2q16wb_fixed - 134375066U, // VLD2q16wb_register - 3355735706U, // VLD2q32 - 0U, // VLD2q32Pseudo - 0U, // VLD2q32PseudoWB_fixed - 0U, // VLD2q32PseudoWB_register - 134502042U, // VLD2q32wb_fixed - 134506138U, // VLD2q32wb_register - 3355866778U, // VLD2q8 - 0U, // VLD2q8Pseudo - 0U, // VLD2q8PseudoWB_fixed - 0U, // VLD2q8PseudoWB_register - 134633114U, // VLD2q8wb_fixed - 134637210U, // VLD2q8wb_register - 2153014970U, // VLD3DUPd16 - 0U, // VLD3DUPd16Pseudo - 0U, // VLD3DUPd16Pseudo_UPD - 2153092794U, // VLD3DUPd16_UPD - 2153146042U, // VLD3DUPd32 - 0U, // VLD3DUPd32Pseudo - 0U, // VLD3DUPd32Pseudo_UPD - 2153223866U, // VLD3DUPd32_UPD - 2153277114U, // VLD3DUPd8 - 0U, // VLD3DUPd8Pseudo - 0U, // VLD3DUPd8Pseudo_UPD - 2153354938U, // VLD3DUPd8_UPD - 2153014970U, // VLD3DUPq16 - 0U, // VLD3DUPq16EvenPseudo - 0U, // VLD3DUPq16OddPseudo - 2153092794U, // VLD3DUPq16_UPD - 2153146042U, // VLD3DUPq32 - 0U, // VLD3DUPq32EvenPseudo - 0U, // VLD3DUPq32OddPseudo - 2153223866U, // VLD3DUPq32_UPD - 2153277114U, // VLD3DUPq8 - 0U, // VLD3DUPq8EvenPseudo - 0U, // VLD3DUPq8OddPseudo - 2153354938U, // VLD3DUPq8_UPD - 1079355066U, // VLD3LNd16 - 0U, // VLD3LNd16Pseudo - 0U, // VLD3LNd16Pseudo_UPD - 1079359162U, // VLD3LNd16_UPD - 1079486138U, // VLD3LNd32 - 0U, // VLD3LNd32Pseudo - 0U, // VLD3LNd32Pseudo_UPD - 1079490234U, // VLD3LNd32_UPD - 1079617210U, // VLD3LNd8 - 0U, // VLD3LNd8Pseudo - 0U, // VLD3LNd8Pseudo_UPD - 1079621306U, // VLD3LNd8_UPD - 1079355066U, // VLD3LNq16 - 0U, // VLD3LNq16Pseudo - 0U, // VLD3LNq16Pseudo_UPD - 1079359162U, // VLD3LNq16_UPD - 1079486138U, // VLD3LNq32 - 0U, // VLD3LNq32Pseudo - 0U, // VLD3LNq32Pseudo_UPD - 1079490234U, // VLD3LNq32_UPD - 5531322U, // VLD3d16 - 0U, // VLD3d16Pseudo - 0U, // VLD3d16Pseudo_UPD - 5609146U, // VLD3d16_UPD - 5662394U, // VLD3d32 - 0U, // VLD3d32Pseudo - 0U, // VLD3d32Pseudo_UPD - 5740218U, // VLD3d32_UPD - 5793466U, // VLD3d8 - 0U, // VLD3d8Pseudo - 0U, // VLD3d8Pseudo_UPD - 5871290U, // VLD3d8_UPD - 5531322U, // VLD3q16 - 0U, // VLD3q16Pseudo_UPD - 5609146U, // VLD3q16_UPD - 0U, // VLD3q16oddPseudo - 0U, // VLD3q16oddPseudo_UPD - 5662394U, // VLD3q32 - 0U, // VLD3q32Pseudo_UPD - 5740218U, // VLD3q32_UPD - 0U, // VLD3q32oddPseudo - 0U, // VLD3q32oddPseudo_UPD - 5793466U, // VLD3q8 - 0U, // VLD3q8Pseudo_UPD - 5871290U, // VLD3q8_UPD - 0U, // VLD3q8oddPseudo - 0U, // VLD3q8oddPseudo_UPD - 2153043665U, // VLD4DUPd16 - 0U, // VLD4DUPd16Pseudo - 0U, // VLD4DUPd16Pseudo_UPD - 2153105105U, // VLD4DUPd16_UPD - 2153174737U, // VLD4DUPd32 - 0U, // VLD4DUPd32Pseudo - 0U, // VLD4DUPd32Pseudo_UPD - 2153236177U, // VLD4DUPd32_UPD - 2153305809U, // VLD4DUPd8 - 0U, // VLD4DUPd8Pseudo - 0U, // VLD4DUPd8Pseudo_UPD - 2153367249U, // VLD4DUPd8_UPD - 2153043665U, // VLD4DUPq16 - 0U, // VLD4DUPq16EvenPseudo - 0U, // VLD4DUPq16OddPseudo - 2153105105U, // VLD4DUPq16_UPD - 2153174737U, // VLD4DUPq32 - 0U, // VLD4DUPq32EvenPseudo - 0U, // VLD4DUPq32OddPseudo - 2153236177U, // VLD4DUPq32_UPD - 2153305809U, // VLD4DUPq8 - 0U, // VLD4DUPq8EvenPseudo - 0U, // VLD4DUPq8OddPseudo - 2153367249U, // VLD4DUPq8_UPD - 1079359185U, // VLD4LNd16 - 0U, // VLD4LNd16Pseudo - 0U, // VLD4LNd16Pseudo_UPD - 1079367377U, // VLD4LNd16_UPD - 1079490257U, // VLD4LNd32 - 0U, // VLD4LNd32Pseudo - 0U, // VLD4LNd32Pseudo_UPD - 1079498449U, // VLD4LNd32_UPD - 1079621329U, // VLD4LNd8 - 0U, // VLD4LNd8Pseudo - 0U, // VLD4LNd8Pseudo_UPD - 1079629521U, // VLD4LNd8_UPD - 1079359185U, // VLD4LNq16 - 0U, // VLD4LNq16Pseudo - 0U, // VLD4LNq16Pseudo_UPD - 1079367377U, // VLD4LNq16_UPD - 1079490257U, // VLD4LNq32 - 0U, // VLD4LNq32Pseudo - 0U, // VLD4LNq32Pseudo_UPD - 1079498449U, // VLD4LNq32_UPD - 5560017U, // VLD4d16 - 0U, // VLD4d16Pseudo - 0U, // VLD4d16Pseudo_UPD - 5621457U, // VLD4d16_UPD - 5691089U, // VLD4d32 - 0U, // VLD4d32Pseudo - 0U, // VLD4d32Pseudo_UPD - 5752529U, // VLD4d32_UPD - 5822161U, // VLD4d8 - 0U, // VLD4d8Pseudo - 0U, // VLD4d8Pseudo_UPD - 5883601U, // VLD4d8_UPD - 5560017U, // VLD4q16 - 0U, // VLD4q16Pseudo_UPD - 5621457U, // VLD4q16_UPD - 0U, // VLD4q16oddPseudo - 0U, // VLD4q16oddPseudo_UPD - 5691089U, // VLD4q32 - 0U, // VLD4q32Pseudo_UPD - 5752529U, // VLD4q32_UPD - 0U, // VLD4q32oddPseudo - 0U, // VLD4q32oddPseudo_UPD - 5822161U, // VLD4q8 - 0U, // VLD4q8Pseudo_UPD - 5883601U, // VLD4q8_UPD - 0U, // VLD4q8oddPseudo - 0U, // VLD4q8oddPseudo_UPD - 2332571774U, // VLDMDDB_UPD - 571406U, // VLDMDIA - 2332571662U, // VLDMDIA_UPD - 0U, // VLDMQIA - 2332571774U, // VLDMSDB_UPD - 571406U, // VLDMSIA - 2332571662U, // VLDMSIA_UPD - 556114U, // VLDRD - 162898U, // VLDRH - 556114U, // VLDRS - 1074314122U, // VLLDM - 1074314128U, // VLSTM - 185246300U, // VMAXNMD - 185246693U, // VMAXNMH - 185245992U, // VMAXNMNDf - 185246693U, // VMAXNMNDh - 185245992U, // VMAXNMNQf - 185246693U, // VMAXNMNQh - 185245992U, // VMAXNMS - 253132314U, // VMAXfd - 253132314U, // VMAXfq - 253001242U, // VMAXhd - 253001242U, // VMAXhq - 186940954U, // VMAXsv16i8 - 186678810U, // VMAXsv2i32 - 186809882U, // VMAXsv4i16 - 186678810U, // VMAXsv4i32 - 186809882U, // VMAXsv8i16 - 186940954U, // VMAXsv8i8 - 187334170U, // VMAXuv16i8 - 187072026U, // VMAXuv2i32 - 187203098U, // VMAXuv4i16 - 187072026U, // VMAXuv4i32 - 187203098U, // VMAXuv8i16 - 187334170U, // VMAXuv8i8 - 185246288U, // VMINNMD - 185246681U, // VMINNMH - 185245980U, // VMINNMNDf - 185246681U, // VMINNMNDh - 185245980U, // VMINNMNQf - 185246681U, // VMINNMNQh - 185245980U, // VMINNMS - 253131706U, // VMINfd - 253131706U, // VMINfq - 253000634U, // VMINhd - 253000634U, // VMINhq - 186940346U, // VMINsv16i8 - 186678202U, // VMINsv2i32 - 186809274U, // VMINsv4i16 - 186678202U, // VMINsv4i32 - 186809274U, // VMINsv8i16 - 186940346U, // VMINsv8i8 - 187333562U, // VMINuv16i8 - 187071418U, // VMINuv2i32 - 187202490U, // VMINuv4i16 - 187071418U, // VMINuv4i32 - 187202490U, // VMINuv8i16 - 187333562U, // VMINuv8i8 - 2400344110U, // VMLAD - 2400475182U, // VMLAH - 169896676U, // VMLALslsv2i32 - 170027748U, // VMLALslsv4i16 - 170289892U, // VMLALsluv2i32 - 170420964U, // VMLALsluv4i16 - 169892580U, // VMLALsv2i64 - 170023652U, // VMLALsv4i32 - 170154724U, // VMLALsv8i16 - 170285796U, // VMLALuv2i64 - 170416868U, // VMLALuv4i32 - 170547940U, // VMLALuv8i16 - 2400606254U, // VMLAS - 2400606254U, // VMLAfd - 2400606254U, // VMLAfq - 2400475182U, // VMLAhd - 2400475182U, // VMLAhq - 2400610350U, // VMLAslfd - 2400610350U, // VMLAslfq - 2400479278U, // VMLAslhd - 2400479278U, // VMLAslhq - 170813486U, // VMLAslv2i32 - 170944558U, // VMLAslv4i16 - 170813486U, // VMLAslv4i32 - 170944558U, // VMLAslv8i16 - 171071534U, // VMLAv16i8 - 170809390U, // VMLAv2i32 - 170940462U, // VMLAv4i16 - 170809390U, // VMLAv4i32 - 170940462U, // VMLAv8i16 - 171071534U, // VMLAv8i8 - 2400345279U, // VMLSD - 2400476351U, // VMLSH - 169896809U, // VMLSLslsv2i32 - 170027881U, // VMLSLslsv4i16 - 170290025U, // VMLSLsluv2i32 - 170421097U, // VMLSLsluv4i16 - 169892713U, // VMLSLsv2i64 - 170023785U, // VMLSLsv4i32 - 170154857U, // VMLSLsv8i16 - 170285929U, // VMLSLuv2i64 - 170417001U, // VMLSLuv4i32 - 170548073U, // VMLSLuv8i16 - 2400607423U, // VMLSS - 2400607423U, // VMLSfd - 2400607423U, // VMLSfq - 2400476351U, // VMLShd - 2400476351U, // VMLShq - 2400611519U, // VMLSslfd - 2400611519U, // VMLSslfq - 2400480447U, // VMLSslhd - 2400480447U, // VMLSslhq - 170814655U, // VMLSslv2i32 - 170945727U, // VMLSslv4i16 - 170814655U, // VMLSslv4i32 - 170945727U, // VMLSslv8i16 - 171072703U, // VMLSv16i8 - 170810559U, // VMLSv2i32 - 170941631U, // VMLSv4i16 - 170810559U, // VMLSv4i32 - 170941631U, // VMLSv8i16 - 171072703U, // VMLSv8i8 - 252853737U, // VMOVD - 556521U, // VMOVDRR - 1258988623U, // VMOVH - 252984809U, // VMOVHR - 1260403588U, // VMOVLsv2i64 - 1260534660U, // VMOVLsv4i32 - 1260665732U, // VMOVLsv8i16 - 1260796804U, // VMOVLuv2i64 - 1260927876U, // VMOVLuv4i32 - 1261058948U, // VMOVLuv8i16 - 1261190158U, // VMOVNv2i32 - 1261321230U, // VMOVNv4i16 - 1261452302U, // VMOVNv8i8 - 252984809U, // VMOVRH - 556521U, // VMOVRRD - 548329U, // VMOVRRS - 540137U, // VMOVRS - 253115881U, // VMOVS - 540137U, // VMOVSR - 548329U, // VMOVSRR - 405945833U, // VMOVv16i8 - 405552617U, // VMOVv1i64 - 1326857705U, // VMOVv2f32 - 405683689U, // VMOVv2i32 - 405552617U, // VMOVv2i64 - 1326857705U, // VMOVv4f32 - 405814761U, // VMOVv4i16 - 405683689U, // VMOVv4i32 - 405814761U, // VMOVv8i16 - 405945833U, // VMOVv8i8 - 3221798113U, // VMRS - 572641U, // VMRS_FPEXC - 1074314465U, // VMRS_FPINST - 2148056289U, // VMRS_FPINST2 - 3221798113U, // VMRS_FPSID - 572641U, // VMRS_MVFR0 - 1074314465U, // VMRS_MVFR1 - 2148056289U, // VMRS_MVFR2 - 5946503U, // VMSR - 6077575U, // VMSR_FPEXC - 6208647U, // VMSR_FPINST - 6339719U, // VMSR_FPINST2 - 6470791U, // VMSR_FPSID - 252869503U, // VMULD - 253000575U, // VMULH - 185246384U, // VMULLp64 - 6585174U, // VMULLp8 - 186669910U, // VMULLslsv2i32 - 186800982U, // VMULLslsv4i16 - 187063126U, // VMULLsluv2i32 - 187194198U, // VMULLsluv4i16 - 186678102U, // VMULLsv2i64 - 186809174U, // VMULLsv4i32 - 186940246U, // VMULLsv8i16 - 187071318U, // VMULLuv2i64 - 187202390U, // VMULLuv4i32 - 187333462U, // VMULLuv8i16 - 253131647U, // VMULS - 253131647U, // VMULfd - 253131647U, // VMULfq - 253000575U, // VMULhd - 253000575U, // VMULhq - 6585215U, // VMULpd - 6585215U, // VMULpq - 253123455U, // VMULslfd - 253123455U, // VMULslfq - 252992383U, // VMULslhd - 252992383U, // VMULslhq - 187587455U, // VMULslv2i32 - 187718527U, // VMULslv4i16 - 187587455U, // VMULslv4i32 - 187718527U, // VMULslv8i16 - 187857791U, // VMULv16i8 - 187595647U, // VMULv2i32 - 187726719U, // VMULv4i16 - 187595647U, // VMULv4i32 - 187726719U, // VMULv8i16 - 187857791U, // VMULv8i8 - 539650U, // VMVNd - 539650U, // VMVNq - 405683202U, // VMVNv2i32 - 405814274U, // VMVNv4i16 - 405683202U, // VMVNv4i32 - 405814274U, // VMVNv8i16 - 252852757U, // VNEGD - 252983829U, // VNEGH - 253114901U, // VNEGS - 253114901U, // VNEGf32q - 253114901U, // VNEGfd - 252983829U, // VNEGhd - 252983829U, // VNEGhq - 1260534293U, // VNEGs16d - 1260534293U, // VNEGs16q - 1260403221U, // VNEGs32d - 1260403221U, // VNEGs32q - 1260665365U, // VNEGs8d - 1260665365U, // VNEGs8q - 2400344104U, // VNMLAD - 2400475176U, // VNMLAH - 2400606248U, // VNMLAS - 2400345273U, // VNMLSD - 2400476345U, // VNMLSH - 2400607417U, // VNMLSS - 252869497U, // VNMULD - 253000569U, // VNMULH - 253131641U, // VNMULS - 555999U, // VORNd - 555999U, // VORNq - 556151U, // VORRd - 405699703U, // VORRiv2i32 - 405830775U, // VORRiv4i16 - 405699703U, // VORRiv4i32 - 405830775U, // VORRiv8i16 - 556151U, // VORRq - 1243904713U, // VPADALsv16i8 - 1243642569U, // VPADALsv2i32 - 1243773641U, // VPADALsv4i16 - 1243642569U, // VPADALsv4i32 - 1243773641U, // VPADALsv8i16 - 1243904713U, // VPADALsv8i8 - 1244297929U, // VPADALuv16i8 - 1244035785U, // VPADALuv2i32 - 1244166857U, // VPADALuv4i16 - 1244035785U, // VPADALuv4i32 - 1244166857U, // VPADALuv8i16 - 1244297929U, // VPADALuv8i8 - 1260665605U, // VPADDLsv16i8 - 1260403461U, // VPADDLsv2i32 - 1260534533U, // VPADDLsv4i16 - 1260403461U, // VPADDLsv4i32 - 1260534533U, // VPADDLsv8i16 - 1260665605U, // VPADDLsv8i8 - 1261058821U, // VPADDLuv16i8 - 1260796677U, // VPADDLuv2i32 - 1260927749U, // VPADDLuv4i16 - 1260796677U, // VPADDLuv4i32 - 1260927749U, // VPADDLuv8i16 - 1261058821U, // VPADDLuv8i8 - 253131143U, // VPADDf - 253000071U, // VPADDh - 187726215U, // VPADDi16 - 187595143U, // VPADDi32 - 187857287U, // VPADDi8 - 253132308U, // VPMAXf - 253001236U, // VPMAXh - 186809876U, // VPMAXs16 - 186678804U, // VPMAXs32 - 186940948U, // VPMAXs8 - 187203092U, // VPMAXu16 - 187072020U, // VPMAXu32 - 187334164U, // VPMAXu8 - 253131700U, // VPMINf - 253000628U, // VPMINh - 186809268U, // VPMINs16 - 186678196U, // VPMINs32 - 186940340U, // VPMINs8 - 187202484U, // VPMINu16 - 187071412U, // VPMINu32 - 187333556U, // VPMINu8 - 1260666014U, // VQABSv16i8 - 1260403870U, // VQABSv2i32 - 1260534942U, // VQABSv4i16 - 1260403870U, // VQABSv4i32 - 1260534942U, // VQABSv8i16 - 1260666014U, // VQABSv8i8 - 186939789U, // VQADDsv16i8 - 191265165U, // VQADDsv1i64 - 186677645U, // VQADDsv2i32 - 191265165U, // VQADDsv2i64 - 186808717U, // VQADDsv4i16 - 186677645U, // VQADDsv4i32 - 186808717U, // VQADDsv8i16 - 186939789U, // VQADDsv8i8 - 187333005U, // VQADDuv16i8 - 191396237U, // VQADDuv1i64 - 187070861U, // VQADDuv2i32 - 191396237U, // VQADDuv2i64 - 187201933U, // VQADDuv4i16 - 187070861U, // VQADDuv4i32 - 187201933U, // VQADDuv8i16 - 187333005U, // VQADDuv8i8 - 169896656U, // VQDMLALslv2i32 - 170027728U, // VQDMLALslv4i16 - 169892560U, // VQDMLALv2i64 - 170023632U, // VQDMLALv4i32 - 169896801U, // VQDMLSLslv2i32 - 170027873U, // VQDMLSLslv4i16 - 169892705U, // VQDMLSLv2i64 - 170023777U, // VQDMLSLv4i32 - 186669632U, // VQDMULHslv2i32 - 186800704U, // VQDMULHslv4i16 - 186669632U, // VQDMULHslv4i32 - 186800704U, // VQDMULHslv8i16 - 186677824U, // VQDMULHv2i32 - 186808896U, // VQDMULHv4i16 - 186677824U, // VQDMULHv4i32 - 186808896U, // VQDMULHv8i16 - 186669890U, // VQDMULLslv2i32 - 186800962U, // VQDMULLslv4i16 - 186678082U, // VQDMULLv2i64 - 186809154U, // VQDMULLv4i32 - 1264991226U, // VQMOVNsuv2i32 - 1260403706U, // VQMOVNsuv4i16 - 1260534778U, // VQMOVNsuv8i8 - 1264991239U, // VQMOVNsv2i32 - 1260403719U, // VQMOVNsv4i16 - 1260534791U, // VQMOVNsv8i8 - 1265122311U, // VQMOVNuv2i32 - 1260796935U, // VQMOVNuv4i16 - 1260928007U, // VQMOVNuv8i8 - 1260665359U, // VQNEGv16i8 - 1260403215U, // VQNEGv2i32 - 1260534287U, // VQNEGv4i16 - 1260403215U, // VQNEGv4i32 - 1260534287U, // VQNEGv8i16 - 1260665359U, // VQNEGv8i8 - 169896482U, // VQRDMLAHslv2i32 - 170027554U, // VQRDMLAHslv4i16 - 169896482U, // VQRDMLAHslv4i32 - 170027554U, // VQRDMLAHslv8i16 - 169892386U, // VQRDMLAHv2i32 - 170023458U, // VQRDMLAHv4i16 - 169892386U, // VQRDMLAHv4i32 - 170023458U, // VQRDMLAHv8i16 - 169896539U, // VQRDMLSHslv2i32 - 170027611U, // VQRDMLSHslv4i16 - 169896539U, // VQRDMLSHslv4i32 - 170027611U, // VQRDMLSHslv8i16 - 169892443U, // VQRDMLSHv2i32 - 170023515U, // VQRDMLSHv4i16 - 169892443U, // VQRDMLSHv4i32 - 170023515U, // VQRDMLSHv8i16 - 186669640U, // VQRDMULHslv2i32 - 186800712U, // VQRDMULHslv4i16 - 186669640U, // VQRDMULHslv4i32 - 186800712U, // VQRDMULHslv8i16 - 186677832U, // VQRDMULHv2i32 - 186808904U, // VQRDMULHv4i16 - 186677832U, // VQRDMULHv4i32 - 186808904U, // VQRDMULHv8i16 - 186940188U, // VQRSHLsv16i8 - 191265564U, // VQRSHLsv1i64 - 186678044U, // VQRSHLsv2i32 - 191265564U, // VQRSHLsv2i64 - 186809116U, // VQRSHLsv4i16 - 186678044U, // VQRSHLsv4i32 - 186809116U, // VQRSHLsv8i16 - 186940188U, // VQRSHLsv8i8 - 187333404U, // VQRSHLuv16i8 - 191396636U, // VQRSHLuv1i64 - 187071260U, // VQRSHLuv2i32 - 191396636U, // VQRSHLuv2i64 - 187202332U, // VQRSHLuv4i16 - 187071260U, // VQRSHLuv4i32 - 187202332U, // VQRSHLuv8i16 - 187333404U, // VQRSHLuv8i8 - 191265738U, // VQRSHRNsv2i32 - 186678218U, // VQRSHRNsv4i16 - 186809290U, // VQRSHRNsv8i8 - 191396810U, // VQRSHRNuv2i32 - 187071434U, // VQRSHRNuv4i16 - 187202506U, // VQRSHRNuv8i8 - 191265777U, // VQRSHRUNv2i32 - 186678257U, // VQRSHRUNv4i16 - 186809329U, // VQRSHRUNv8i8 - 186940182U, // VQSHLsiv16i8 - 191265558U, // VQSHLsiv1i64 - 186678038U, // VQSHLsiv2i32 - 191265558U, // VQSHLsiv2i64 - 186809110U, // VQSHLsiv4i16 - 186678038U, // VQSHLsiv4i32 - 186809110U, // VQSHLsiv8i16 - 186940182U, // VQSHLsiv8i8 - 186940879U, // VQSHLsuv16i8 - 191266255U, // VQSHLsuv1i64 - 186678735U, // VQSHLsuv2i32 - 191266255U, // VQSHLsuv2i64 - 186809807U, // VQSHLsuv4i16 - 186678735U, // VQSHLsuv4i32 - 186809807U, // VQSHLsuv8i16 - 186940879U, // VQSHLsuv8i8 - 186940182U, // VQSHLsv16i8 - 191265558U, // VQSHLsv1i64 - 186678038U, // VQSHLsv2i32 - 191265558U, // VQSHLsv2i64 - 186809110U, // VQSHLsv4i16 - 186678038U, // VQSHLsv4i32 - 186809110U, // VQSHLsv8i16 - 186940182U, // VQSHLsv8i8 - 187333398U, // VQSHLuiv16i8 - 191396630U, // VQSHLuiv1i64 - 187071254U, // VQSHLuiv2i32 - 191396630U, // VQSHLuiv2i64 - 187202326U, // VQSHLuiv4i16 - 187071254U, // VQSHLuiv4i32 - 187202326U, // VQSHLuiv8i16 - 187333398U, // VQSHLuiv8i8 - 187333398U, // VQSHLuv16i8 - 191396630U, // VQSHLuv1i64 - 187071254U, // VQSHLuv2i32 - 191396630U, // VQSHLuv2i64 - 187202326U, // VQSHLuv4i16 - 187071254U, // VQSHLuv4i32 - 187202326U, // VQSHLuv8i16 - 187333398U, // VQSHLuv8i8 - 191265731U, // VQSHRNsv2i32 - 186678211U, // VQSHRNsv4i16 - 186809283U, // VQSHRNsv8i8 - 191396803U, // VQSHRNuv2i32 - 187071427U, // VQSHRNuv4i16 - 187202499U, // VQSHRNuv8i8 - 191265769U, // VQSHRUNv2i32 - 186678249U, // VQSHRUNv4i16 - 186809321U, // VQSHRUNv8i8 - 186939648U, // VQSUBsv16i8 - 191265024U, // VQSUBsv1i64 - 186677504U, // VQSUBsv2i32 - 191265024U, // VQSUBsv2i64 - 186808576U, // VQSUBsv4i16 - 186677504U, // VQSUBsv4i32 - 186808576U, // VQSUBsv8i16 - 186939648U, // VQSUBsv8i8 - 187332864U, // VQSUBuv16i8 - 191396096U, // VQSUBuv1i64 - 187070720U, // VQSUBuv2i32 - 191396096U, // VQSUBuv2i64 - 187201792U, // VQSUBuv4i16 - 187070720U, // VQSUBuv4i32 - 187201792U, // VQSUBuv8i16 - 187332864U, // VQSUBuv8i8 - 187464613U, // VRADDHNv2i32 - 187595685U, // VRADDHNv4i16 - 187726757U, // VRADDHNv8i8 - 1260796401U, // VRECPEd - 253114865U, // VRECPEfd - 253114865U, // VRECPEfq - 252983793U, // VRECPEhd - 252983793U, // VRECPEhq - 1260796401U, // VRECPEq - 253131994U, // VRECPSfd - 253131994U, // VRECPSfq - 253000922U, // VRECPShd - 253000922U, // VRECPShq - 407379U, // VREV16d8 - 407379U, // VREV16q8 - 145022U, // VREV32d16 - 407166U, // VREV32d8 - 145022U, // VREV32q16 - 407166U, // VREV32q8 - 145098U, // VREV64d16 - 276170U, // VREV64d32 - 407242U, // VREV64d8 - 145098U, // VREV64q16 - 276170U, // VREV64q32 - 407242U, // VREV64q8 - 186939770U, // VRHADDsv16i8 - 186677626U, // VRHADDsv2i32 - 186808698U, // VRHADDsv4i16 - 186677626U, // VRHADDsv4i32 - 186808698U, // VRHADDsv8i16 - 186939770U, // VRHADDsv8i8 - 187332986U, // VRHADDuv16i8 - 187070842U, // VRHADDuv2i32 - 187201914U, // VRHADDuv4i16 - 187070842U, // VRHADDuv4i32 - 187201914U, // VRHADDuv8i16 - 187332986U, // VRHADDuv8i8 - 1258988088U, // VRINTAD - 1258988470U, // VRINTAH - 1258987769U, // VRINTANDf - 1258988470U, // VRINTANDh - 1258987769U, // VRINTANQf - 1258988470U, // VRINTANQh - 1258987769U, // VRINTAS - 1258988136U, // VRINTMD - 1258988529U, // VRINTMH - 1258987828U, // VRINTMNDf - 1258988529U, // VRINTMNDh - 1258987828U, // VRINTMNQf - 1258988529U, // VRINTMNQh - 1258987828U, // VRINTMS - 1258988148U, // VRINTND - 1258988541U, // VRINTNH - 1258987840U, // VRINTNNDf - 1258988541U, // VRINTNNDh - 1258987840U, // VRINTNNQf - 1258988541U, // VRINTNNQh - 1258987840U, // VRINTNS - 1258988160U, // VRINTPD - 1258988553U, // VRINTPH - 1258987852U, // VRINTPNDf - 1258988553U, // VRINTPNDh - 1258987852U, // VRINTPNQf - 1258988553U, // VRINTPNQh - 1258987852U, // VRINTPS - 252853388U, // VRINTRD - 252984460U, // VRINTRH - 253115532U, // VRINTRS - 252853960U, // VRINTXD - 252985032U, // VRINTXH - 1258987900U, // VRINTXNDf - 1258988611U, // VRINTXNDh - 1258987900U, // VRINTXNQf - 1258988611U, // VRINTXNQh - 253116104U, // VRINTXS - 252853972U, // VRINTZD - 252985044U, // VRINTZH - 1258987912U, // VRINTZNDf - 1258988634U, // VRINTZNDh - 1258987912U, // VRINTZNQf - 1258988634U, // VRINTZNQh - 253116116U, // VRINTZS - 186940195U, // VRSHLsv16i8 - 191265571U, // VRSHLsv1i64 - 186678051U, // VRSHLsv2i32 - 191265571U, // VRSHLsv2i64 - 186809123U, // VRSHLsv4i16 - 186678051U, // VRSHLsv4i32 - 186809123U, // VRSHLsv8i16 - 186940195U, // VRSHLsv8i8 - 187333411U, // VRSHLuv16i8 - 191396643U, // VRSHLuv1i64 - 187071267U, // VRSHLuv2i32 - 191396643U, // VRSHLuv2i64 - 187202339U, // VRSHLuv4i16 - 187071267U, // VRSHLuv4i32 - 187202339U, // VRSHLuv8i16 - 187333411U, // VRSHLuv8i8 - 187464658U, // VRSHRNv2i32 - 187595730U, // VRSHRNv4i16 - 187726802U, // VRSHRNv8i8 - 186940503U, // VRSHRsv16i8 - 191265879U, // VRSHRsv1i64 - 186678359U, // VRSHRsv2i32 - 191265879U, // VRSHRsv2i64 - 186809431U, // VRSHRsv4i16 - 186678359U, // VRSHRsv4i32 - 186809431U, // VRSHRsv8i16 - 186940503U, // VRSHRsv8i8 - 187333719U, // VRSHRuv16i8 - 191396951U, // VRSHRuv1i64 - 187071575U, // VRSHRuv2i32 - 191396951U, // VRSHRuv2i64 - 187202647U, // VRSHRuv4i16 - 187071575U, // VRSHRuv4i32 - 187202647U, // VRSHRuv8i16 - 187333719U, // VRSHRuv8i8 - 1260796414U, // VRSQRTEd - 253114878U, // VRSQRTEfd - 253114878U, // VRSQRTEfq - 252983806U, // VRSQRTEhd - 252983806U, // VRSQRTEhq - 1260796414U, // VRSQRTEq - 253132016U, // VRSQRTSfd - 253132016U, // VRSQRTSfq - 253000944U, // VRSQRTShd - 253000944U, // VRSQRTShq - 170154046U, // VRSRAsv16i8 - 174479422U, // VRSRAsv1i64 - 169891902U, // VRSRAsv2i32 - 174479422U, // VRSRAsv2i64 - 170022974U, // VRSRAsv4i16 - 169891902U, // VRSRAsv4i32 - 170022974U, // VRSRAsv8i16 - 170154046U, // VRSRAsv8i8 - 170547262U, // VRSRAuv16i8 - 174610494U, // VRSRAuv1i64 - 170285118U, // VRSRAuv2i32 - 174610494U, // VRSRAuv2i64 - 170416190U, // VRSRAuv4i16 - 170285118U, // VRSRAuv4i32 - 170416190U, // VRSRAuv8i16 - 170547262U, // VRSRAuv8i8 - 187464598U, // VRSUBHNv2i32 - 187595670U, // VRSUBHNv4i16 - 187726742U, // VRSUBHNv8i8 - 910473U, // VSDOTD - 7070857U, // VSDOTDI - 910473U, // VSDOTQ - 7070857U, // VSDOTQI - 185246348U, // VSELEQD - 185246741U, // VSELEQH - 185246040U, // VSELEQS - 185246276U, // VSELGED - 185246669U, // VSELGEH - 185245968U, // VSELGES - 185246372U, // VSELGTD - 185246775U, // VSELGTH - 185246064U, // VSELGTS - 185246360U, // VSELVSD - 185246763U, // VSELVSH - 185246052U, // VSELVSS - 3221380585U, // VSETLNi16 - 3221511657U, // VSETLNi32 - 3221642729U, // VSETLNi8 - 187726652U, // VSHLLi16 - 187595580U, // VSHLLi32 - 187857724U, // VSHLLi8 - 186678076U, // VSHLLsv2i64 - 186809148U, // VSHLLsv4i32 - 186940220U, // VSHLLsv8i16 - 187071292U, // VSHLLuv2i64 - 187202364U, // VSHLLuv4i32 - 187333436U, // VSHLLuv8i16 - 187857705U, // VSHLiv16i8 - 187464489U, // VSHLiv1i64 - 187595561U, // VSHLiv2i32 - 187464489U, // VSHLiv2i64 - 187726633U, // VSHLiv4i16 - 187595561U, // VSHLiv4i32 - 187726633U, // VSHLiv8i16 - 187857705U, // VSHLiv8i8 - 186940201U, // VSHLsv16i8 - 191265577U, // VSHLsv1i64 - 186678057U, // VSHLsv2i32 - 191265577U, // VSHLsv2i64 - 186809129U, // VSHLsv4i16 - 186678057U, // VSHLsv4i32 - 186809129U, // VSHLsv8i16 - 186940201U, // VSHLsv8i8 - 187333417U, // VSHLuv16i8 - 191396649U, // VSHLuv1i64 - 187071273U, // VSHLuv2i32 - 191396649U, // VSHLuv2i64 - 187202345U, // VSHLuv4i16 - 187071273U, // VSHLuv4i32 - 187202345U, // VSHLuv8i16 - 187333417U, // VSHLuv8i8 - 187464665U, // VSHRNv2i32 - 187595737U, // VSHRNv4i16 - 187726809U, // VSHRNv8i8 - 186940509U, // VSHRsv16i8 - 191265885U, // VSHRsv1i64 - 186678365U, // VSHRsv2i32 - 191265885U, // VSHRsv2i64 - 186809437U, // VSHRsv4i16 - 186678365U, // VSHRsv4i32 - 186809437U, // VSHRsv8i16 - 186940509U, // VSHRsv8i8 - 187333725U, // VSHRuv16i8 - 191396957U, // VSHRuv1i64 - 187071581U, // VSHRuv2i32 - 191396957U, // VSHRuv2i64 - 187202653U, // VSHRuv4i16 - 187071581U, // VSHRuv4i32 - 187202653U, // VSHRuv8i16 - 187333725U, // VSHRuv8i8 - 7110066U, // VSHTOD - 256540082U, // VSHTOH - 7241138U, // VSHTOS - 443563442U, // VSITOD - 443694514U, // VSITOH - 440942002U, // VSITOS - 416419U, // VSLIv16i8 - 5266083U, // VSLIv1i64 - 285347U, // VSLIv2i32 - 5266083U, // VSLIv2i64 - 154275U, // VSLIv4i16 - 285347U, // VSLIv4i32 - 154275U, // VSLIv8i16 - 416419U, // VSLIv8i8 - 1332772274U, // VSLTOD - 1332903346U, // VSLTOH - 1330150834U, // VSLTOS - 252853628U, // VSQRTD - 252984700U, // VSQRTH - 253115772U, // VSQRTS - 170154052U, // VSRAsv16i8 - 174479428U, // VSRAsv1i64 - 169891908U, // VSRAsv2i32 - 174479428U, // VSRAsv2i64 - 170022980U, // VSRAsv4i16 - 169891908U, // VSRAsv4i32 - 170022980U, // VSRAsv8i16 - 170154052U, // VSRAsv8i8 - 170547268U, // VSRAuv16i8 - 174610500U, // VSRAuv1i64 - 170285124U, // VSRAuv2i32 - 174610500U, // VSRAuv2i64 - 170416196U, // VSRAuv4i16 - 170285124U, // VSRAuv4i32 - 170416196U, // VSRAuv8i16 - 170547268U, // VSRAuv8i8 - 416424U, // VSRIv16i8 - 5266088U, // VSRIv1i64 - 285352U, // VSRIv2i32 - 5266088U, // VSRIv2i64 - 154280U, // VSRIv4i16 - 285352U, // VSRIv4i32 - 154280U, // VSRIv8i16 - 416424U, // VSRIv8i8 - 1247041145U, // VST1LNd16 - 1632949881U, // VST1LNd16_UPD - 1247172217U, // VST1LNd32 - 1633080953U, // VST1LNd32_UPD - 1247303289U, // VST1LNd8 - 1633212025U, // VST1LNd8_UPD - 0U, // VST1LNq16Pseudo - 0U, // VST1LNq16Pseudo_UPD - 0U, // VST1LNq32Pseudo - 0U, // VST1LNq32Pseudo_UPD - 0U, // VST1LNq8Pseudo - 0U, // VST1LNq8Pseudo_UPD - 570586745U, // VST1d16 - 587363961U, // VST1d16Q - 0U, // VST1d16QPseudo - 604132985U, // VST1d16Qwb_fixed - 620914297U, // VST1d16Qwb_register - 637695609U, // VST1d16T - 0U, // VST1d16TPseudo - 654464633U, // VST1d16Twb_fixed - 671245945U, // VST1d16Twb_register - 688019065U, // VST1d16wb_fixed - 704800377U, // VST1d16wb_register - 570717817U, // VST1d32 - 587495033U, // VST1d32Q - 0U, // VST1d32QPseudo - 604264057U, // VST1d32Qwb_fixed - 621045369U, // VST1d32Qwb_register - 637826681U, // VST1d32T - 0U, // VST1d32TPseudo - 654595705U, // VST1d32Twb_fixed - 671377017U, // VST1d32Twb_register - 688150137U, // VST1d32wb_fixed - 704931449U, // VST1d32wb_register - 575698553U, // VST1d64 - 592475769U, // VST1d64Q - 0U, // VST1d64QPseudo - 0U, // VST1d64QPseudoWB_fixed - 0U, // VST1d64QPseudoWB_register - 609244793U, // VST1d64Qwb_fixed - 626026105U, // VST1d64Qwb_register - 642807417U, // VST1d64T - 0U, // VST1d64TPseudo - 0U, // VST1d64TPseudoWB_fixed - 0U, // VST1d64TPseudoWB_register - 659576441U, // VST1d64Twb_fixed - 676357753U, // VST1d64Twb_register - 693130873U, // VST1d64wb_fixed - 709912185U, // VST1d64wb_register - 570848889U, // VST1d8 - 587626105U, // VST1d8Q - 0U, // VST1d8QPseudo - 604395129U, // VST1d8Qwb_fixed - 621176441U, // VST1d8Qwb_register - 637957753U, // VST1d8T - 0U, // VST1d8TPseudo - 654726777U, // VST1d8Twb_fixed - 671508089U, // VST1d8Twb_register - 688281209U, // VST1d8wb_fixed - 705062521U, // VST1d8wb_register - 721581689U, // VST1q16 - 0U, // VST1q16HighQPseudo - 0U, // VST1q16HighTPseudo - 0U, // VST1q16LowQPseudo_UPD - 0U, // VST1q16LowTPseudo_UPD - 738350713U, // VST1q16wb_fixed - 755132025U, // VST1q16wb_register - 721712761U, // VST1q32 - 0U, // VST1q32HighQPseudo - 0U, // VST1q32HighTPseudo - 0U, // VST1q32LowQPseudo_UPD - 0U, // VST1q32LowTPseudo_UPD - 738481785U, // VST1q32wb_fixed - 755263097U, // VST1q32wb_register - 726693497U, // VST1q64 - 0U, // VST1q64HighQPseudo - 0U, // VST1q64HighTPseudo - 0U, // VST1q64LowQPseudo_UPD - 0U, // VST1q64LowTPseudo_UPD - 743462521U, // VST1q64wb_fixed - 760243833U, // VST1q64wb_register - 721843833U, // VST1q8 - 0U, // VST1q8HighQPseudo - 0U, // VST1q8HighTPseudo - 0U, // VST1q8LowQPseudo_UPD - 0U, // VST1q8LowTPseudo_UPD - 738612857U, // VST1q8wb_fixed - 755394169U, // VST1q8wb_register - 1247045301U, // VST2LNd16 - 0U, // VST2LNd16Pseudo - 0U, // VST2LNd16Pseudo_UPD - 1632999093U, // VST2LNd16_UPD - 1247176373U, // VST2LNd32 - 0U, // VST2LNd32Pseudo - 0U, // VST2LNd32Pseudo_UPD - 1633130165U, // VST2LNd32_UPD - 1247307445U, // VST2LNd8 - 0U, // VST2LNd8Pseudo - 0U, // VST2LNd8Pseudo_UPD - 1633261237U, // VST2LNd8_UPD - 1247045301U, // VST2LNq16 - 0U, // VST2LNq16Pseudo - 0U, // VST2LNq16Pseudo_UPD - 1632999093U, // VST2LNq16_UPD - 1247176373U, // VST2LNq32 - 0U, // VST2LNq32Pseudo - 0U, // VST2LNq32Pseudo_UPD - 1633130165U, // VST2LNq32_UPD - 771913397U, // VST2b16 - 788682421U, // VST2b16wb_fixed - 805463733U, // VST2b16wb_register - 772044469U, // VST2b32 - 788813493U, // VST2b32wb_fixed - 805594805U, // VST2b32wb_register - 772175541U, // VST2b8 - 788944565U, // VST2b8wb_fixed - 805725877U, // VST2b8wb_register - 721581749U, // VST2d16 - 738350773U, // VST2d16wb_fixed - 755132085U, // VST2d16wb_register - 721712821U, // VST2d32 - 738481845U, // VST2d32wb_fixed - 755263157U, // VST2d32wb_register - 721843893U, // VST2d8 - 738612917U, // VST2d8wb_fixed - 755394229U, // VST2d8wb_register - 587364021U, // VST2q16 - 0U, // VST2q16Pseudo - 0U, // VST2q16PseudoWB_fixed - 0U, // VST2q16PseudoWB_register - 604133045U, // VST2q16wb_fixed - 620914357U, // VST2q16wb_register - 587495093U, // VST2q32 - 0U, // VST2q32Pseudo - 0U, // VST2q32PseudoWB_fixed - 0U, // VST2q32PseudoWB_register - 604264117U, // VST2q32wb_fixed - 621045429U, // VST2q32wb_register - 587626165U, // VST2q8 - 0U, // VST2q8Pseudo - 0U, // VST2q8PseudoWB_fixed - 0U, // VST2q8PseudoWB_register - 604395189U, // VST2q8wb_fixed - 621176501U, // VST2q8wb_register - 1247073989U, // VST3LNd16 - 0U, // VST3LNd16Pseudo - 0U, // VST3LNd16Pseudo_UPD - 1633011397U, // VST3LNd16_UPD - 1247205061U, // VST3LNd32 - 0U, // VST3LNd32Pseudo - 0U, // VST3LNd32Pseudo_UPD - 1633142469U, // VST3LNd32_UPD - 1247336133U, // VST3LNd8 - 0U, // VST3LNd8Pseudo - 0U, // VST3LNd8Pseudo_UPD - 1633273541U, // VST3LNd8_UPD - 1247073989U, // VST3LNq16 - 0U, // VST3LNq16Pseudo - 0U, // VST3LNq16Pseudo_UPD - 1633011397U, // VST3LNq16_UPD - 1247205061U, // VST3LNq32 - 0U, // VST3LNq32Pseudo - 0U, // VST3LNq32Pseudo_UPD - 1633142469U, // VST3LNq32_UPD - 173303493U, // VST3d16 - 0U, // VST3d16Pseudo - 0U, // VST3d16Pseudo_UPD - 559257285U, // VST3d16_UPD - 173434565U, // VST3d32 - 0U, // VST3d32Pseudo - 0U, // VST3d32Pseudo_UPD - 559388357U, // VST3d32_UPD - 173565637U, // VST3d8 - 0U, // VST3d8Pseudo - 0U, // VST3d8Pseudo_UPD - 559519429U, // VST3d8_UPD - 173303493U, // VST3q16 - 0U, // VST3q16Pseudo_UPD - 559257285U, // VST3q16_UPD - 0U, // VST3q16oddPseudo - 0U, // VST3q16oddPseudo_UPD - 173434565U, // VST3q32 - 0U, // VST3q32Pseudo_UPD - 559388357U, // VST3q32_UPD - 0U, // VST3q32oddPseudo - 0U, // VST3q32oddPseudo_UPD - 173565637U, // VST3q8 - 0U, // VST3q8Pseudo_UPD - 559519429U, // VST3q8_UPD - 0U, // VST3q8oddPseudo - 0U, // VST3q8oddPseudo_UPD - 1247123158U, // VST4LNd16 - 0U, // VST4LNd16Pseudo - 0U, // VST4LNd16Pseudo_UPD - 1633003222U, // VST4LNd16_UPD - 1247254230U, // VST4LNd32 - 0U, // VST4LNd32Pseudo - 0U, // VST4LNd32Pseudo_UPD - 1633134294U, // VST4LNd32_UPD - 1247385302U, // VST4LNd8 - 0U, // VST4LNd8Pseudo - 0U, // VST4LNd8Pseudo_UPD - 1633265366U, // VST4LNd8_UPD - 1247123158U, // VST4LNq16 - 0U, // VST4LNq16Pseudo - 0U, // VST4LNq16Pseudo_UPD - 1633003222U, // VST4LNq16_UPD - 1247254230U, // VST4LNq32 - 0U, // VST4LNq32Pseudo - 0U, // VST4LNq32Pseudo_UPD - 1633134294U, // VST4LNq32_UPD - 173332182U, // VST4d16 - 0U, // VST4d16Pseudo - 0U, // VST4d16Pseudo_UPD - 559269590U, // VST4d16_UPD - 173463254U, // VST4d32 - 0U, // VST4d32Pseudo - 0U, // VST4d32Pseudo_UPD - 559400662U, // VST4d32_UPD - 173594326U, // VST4d8 - 0U, // VST4d8Pseudo - 0U, // VST4d8Pseudo_UPD - 559531734U, // VST4d8_UPD - 173332182U, // VST4q16 - 0U, // VST4q16Pseudo_UPD - 559269590U, // VST4q16_UPD - 0U, // VST4q16oddPseudo - 0U, // VST4q16oddPseudo_UPD - 173463254U, // VST4q32 - 0U, // VST4q32Pseudo_UPD - 559400662U, // VST4q32_UPD - 0U, // VST4q32oddPseudo - 0U, // VST4q32oddPseudo_UPD - 173594326U, // VST4q8 - 0U, // VST4q8Pseudo_UPD - 559531734U, // VST4q8_UPD - 0U, // VST4q8oddPseudo - 0U, // VST4q8oddPseudo_UPD - 2332571781U, // VSTMDDB_UPD - 571413U, // VSTMDIA - 2332571669U, // VSTMDIA_UPD - 0U, // VSTMQIA - 2332571781U, // VSTMSDB_UPD - 571413U, // VSTMSIA - 2332571669U, // VSTMSIA_UPD - 556179U, // VSTRD - 162963U, // VSTRH - 556179U, // VSTRS - 252868870U, // VSUBD - 252999942U, // VSUBH - 187464606U, // VSUBHNv2i32 - 187595678U, // VSUBHNv4i16 - 187726750U, // VSUBHNv8i8 - 186677999U, // VSUBLsv2i64 - 186809071U, // VSUBLsv4i32 - 186940143U, // VSUBLsv8i16 - 187071215U, // VSUBLuv2i64 - 187202287U, // VSUBLuv4i32 - 187333359U, // VSUBLuv8i16 - 253131014U, // VSUBS - 186678766U, // VSUBWsv2i64 - 186809838U, // VSUBWsv4i32 - 186940910U, // VSUBWsv8i16 - 187071982U, // VSUBWuv2i64 - 187203054U, // VSUBWuv4i32 - 187334126U, // VSUBWuv8i16 - 253131014U, // VSUBfd - 253131014U, // VSUBfq - 252999942U, // VSUBhd - 252999942U, // VSUBhq - 187857158U, // VSUBv16i8 - 187463942U, // VSUBv1i64 - 187595014U, // VSUBv2i32 - 187463942U, // VSUBv2i64 - 187726086U, // VSUBv4i16 - 187595014U, // VSUBv4i32 - 187726086U, // VSUBv8i16 - 187857158U, // VSUBv8i8 - 547888U, // VSWPd - 547888U, // VSWPq - 424682U, // VTBL1 - 424682U, // VTBL2 - 424682U, // VTBL3 - 0U, // VTBL3Pseudo - 424682U, // VTBL4 - 0U, // VTBL4Pseudo - 417355U, // VTBX1 - 417355U, // VTBX2 - 417355U, // VTBX3 - 0U, // VTBX3Pseudo - 417355U, // VTBX4 - 0U, // VTBX4Pseudo - 7634354U, // VTOSHD - 256146866U, // VTOSHH - 7765426U, // VTOSHS - 441597080U, // VTOSIRD - 444087448U, // VTOSIRH - 440417432U, // VTOSIRS - 441597362U, // VTOSIZD - 444087730U, // VTOSIZH - 440417714U, // VTOSIZS - 1330806194U, // VTOSLD - 1333296562U, // VTOSLH - 1329626546U, // VTOSLS - 8027570U, // VTOUHD - 256277938U, // VTOUHH - 8158642U, // VTOUHS - 444480664U, // VTOUIRD - 444611736U, // VTOUIRH - 440548504U, // VTOUIRS - 444480946U, // VTOUIZD - 444612018U, // VTOUIZH - 440548786U, // VTOUIZS - 1333689778U, // VTOULD - 1333820850U, // VTOULH - 1329757618U, // VTOULS - 154596U, // VTRNd16 - 285668U, // VTRNd32 - 416740U, // VTRNd8 - 154596U, // VTRNq16 - 285668U, // VTRNq32 - 416740U, // VTRNq8 - 425351U, // VTSTv16i8 - 294279U, // VTSTv2i32 - 163207U, // VTSTv4i16 - 294279U, // VTSTv4i32 - 163207U, // VTSTv8i16 - 425351U, // VTSTv8i8 - 910483U, // VUDOTD - 7070867U, // VUDOTDI - 910483U, // VUDOTQ - 7070867U, // VUDOTQI - 8551858U, // VUHTOD - 256802226U, // VUHTOH - 8682930U, // VUHTOS - 445005234U, // VUITOD - 445136306U, // VUITOH - 441204146U, // VUITOS - 1334214066U, // VULTOD - 1334345138U, // VULTOH - 1330412978U, // VULTOS - 154677U, // VUZPd16 - 416821U, // VUZPd8 - 154677U, // VUZPq16 - 285749U, // VUZPq32 - 416821U, // VUZPq8 - 154653U, // VZIPd16 - 416797U, // VZIPd8 - 154653U, // VZIPq16 - 285725U, // VZIPq32 - 416797U, // VZIPq8 - 571388U, // sysLDMDA - 2332571644U, // sysLDMDA_UPD - 571519U, // sysLDMDB - 2332571775U, // sysLDMDB_UPD - 572300U, // sysLDMIA - 2332572556U, // sysLDMIA_UPD - 571538U, // sysLDMIB - 2332571794U, // sysLDMIB_UPD - 571394U, // sysSTMDA - 2332571650U, // sysSTMDA_UPD - 571526U, // sysSTMDB - 2332571782U, // sysSTMDB_UPD - 572306U, // sysSTMIA - 2332572562U, // sysSTMIA_UPD - 571544U, // sysSTMIB - 2332571800U, // sysSTMIB_UPD - 530745U, // t2ADCri - 9050425U, // t2ADCrr - 9079097U, // t2ADCrs - 9050486U, // t2ADDri - 556533U, // t2ADDri12 - 9050486U, // t2ADDrr - 9079158U, // t2ADDrs - 9059406U, // t2ADR - 530859U, // t2ANDri - 9050539U, // t2ANDrr - 9079211U, // t2ANDrs - 9051260U, // t2ASRri - 9051260U, // t2ASRrr - 1082832976U, // t2B - 555329U, // t2BFC - 547483U, // t2BFI - 530758U, // t2BICri - 9050438U, // t2BICrr - 9079110U, // t2BICrs - 1074313901U, // t2BXJ - 1082832976U, // t2Bcc - 201907225U, // t2CDP - 201905823U, // t2CDP2 - 839310U, // t2CLREX - 540368U, // t2CLZ - 9059263U, // t2CMNri - 9059263U, // t2CMNzrr - 9075647U, // t2CMNzrs - 9059363U, // t2CMPri - 9059363U, // t2CMPrr - 9075747U, // t2CMPrs - 828709U, // t2CPS1p - 1317731549U, // t2CPS2p - 235470045U, // t2CPS3p - 185246891U, // t2CRC32B - 185246899U, // t2CRC32CB - 185246973U, // t2CRC32CH - 185247057U, // t2CRC32CW - 185246965U, // t2CRC32H - 185247049U, // t2CRC32W - 1074313739U, // t2DBG - 837235U, // t2DCPS1 - 837295U, // t2DCPS2 - 837311U, // t2DCPS3 - 822655139U, // t2DMB - 822655158U, // t2DSB - 531562U, // t2EORri - 9051242U, // t2EORrr - 9079914U, // t2EORrs - 1082834290U, // t2HINT - 828731U, // t2HVC - 839432378U, // t2ISB - 17313120U, // t2IT - 0U, // t2Int_eh_sjlj_setjmp - 0U, // t2Int_eh_sjlj_setjmp_nofp - 538616U, // t2LDA - 538701U, // t2LDAB - 540284U, // t2LDAEX - 538905U, // t2LDAEXB - 555461U, // t2LDAEXD - 539263U, // t2LDAEXH - 539165U, // t2LDAH - 1275615921U, // t2LDC2L_OFFSET - 1275615921U, // t2LDC2L_OPTION - 1275615921U, // t2LDC2L_POST - 1275615921U, // t2LDC2L_PRE - 1275614853U, // t2LDC2_OFFSET - 1275614853U, // t2LDC2_OPTION - 1275614853U, // t2LDC2_POST - 1275614853U, // t2LDC2_PRE - 1275615989U, // t2LDCL_OFFSET - 1275615989U, // t2LDCL_OPTION - 1275615989U, // t2LDCL_POST - 1275615989U, // t2LDCL_PRE - 1275615549U, // t2LDC_OFFSET - 1275615549U, // t2LDC_OPTION - 1275615549U, // t2LDC_POST - 1275615549U, // t2LDC_PRE - 571519U, // t2LDMDB - 2332571775U, // t2LDMDB_UPD - 9091980U, // t2LDMIA - 2341092236U, // t2LDMIA_UPD - 556328U, // t2LDRBT - 546988U, // t2LDRB_POST - 546988U, // t2LDRB_PRE - 9074860U, // t2LDRBi12 - 555180U, // t2LDRBi8 - 9058476U, // t2LDRBpci - 9066668U, // t2LDRBs - 551343U, // t2LDRD_POST - 551343U, // t2LDRD_PRE - 547247U, // t2LDRDi8 - 556680U, // t2LDREX - 538919U, // t2LDREXB - 555475U, // t2LDREXD - 539277U, // t2LDREXH - 556363U, // t2LDRHT - 547409U, // t2LDRH_POST - 547409U, // t2LDRH_PRE - 9075281U, // t2LDRHi12 - 555601U, // t2LDRHi8 - 9058897U, // t2LDRHpci - 9067089U, // t2LDRHs - 556340U, // t2LDRSBT - 547006U, // t2LDRSB_POST - 547006U, // t2LDRSB_PRE - 9074878U, // t2LDRSBi12 - 555198U, // t2LDRSBi8 - 9058494U, // t2LDRSBpci - 9066686U, // t2LDRSBs - 556375U, // t2LDRSHT - 547428U, // t2LDRSH_POST - 547428U, // t2LDRSH_PRE - 9075300U, // t2LDRSHi12 - 555620U, // t2LDRSHi8 - 9058916U, // t2LDRSHpci - 9067108U, // t2LDRSHs - 556407U, // t2LDRT - 547923U, // t2LDR_POST - 547923U, // t2LDR_PRE - 9075795U, // t2LDRi12 - 556115U, // t2LDRi8 - 9059411U, // t2LDRpci - 9067603U, // t2LDRs - 9050981U, // t2LSLri - 9050981U, // t2LSLrr - 9051267U, // t2LSRri - 9051267U, // t2LSRrr - 201907274U, // t2MCR - 201905828U, // t2MCR2 - 201878642U, // t2MCRR - 201877161U, // t2MCRR2 - 546852U, // t2MLA - 548021U, // t2MLS - 556471U, // t2MOVTi16 - 9063914U, // t2MOVi - 540159U, // t2MOVi16 - 9063914U, // t2MOVr - 9059558U, // t2MOVsra_flag - 9059563U, // t2MOVsrl_flag - 336124238U, // t2MRC - 336123530U, // t2MRC2 - 352872786U, // t2MRRC - 352872079U, // t2MRRC2 - 2148056290U, // t2MRS_AR - 539874U, // t2MRS_M - 539874U, // t2MRSbanked - 3221798114U, // t2MRSsys_AR - 369638536U, // t2MSR_AR - 369638536U, // t2MSR_M - 386415752U, // t2MSRbanked - 555893U, // t2MUL - 543747U, // t2MVNi - 9063427U, // t2MVNr - 9051139U, // t2MVNs - 531424U, // t2ORNri - 531424U, // t2ORNrr - 560096U, // t2ORNrs - 531576U, // t2ORRri - 9051256U, // t2ORRrr - 9079928U, // t2ORRrs - 548115U, // t2PKHBT - 547023U, // t2PKHTB - 856178170U, // t2PLDWi12 - 872955386U, // t2PLDWi8 - 889748986U, // t2PLDWs - 856177055U, // t2PLDi12 - 872954271U, // t2PLDi8 - 906541471U, // t2PLDpci - 889747871U, // t2PLDs - 856177311U, // t2PLIi12 - 872954527U, // t2PLIi8 - 906541727U, // t2PLIpci - 889748127U, // t2PLIs - 555406U, // t2QADD - 554800U, // t2QADD16 - 554903U, // t2QADD8 - 556729U, // t2QASX - 555380U, // t2QDADD - 555252U, // t2QDSUB - 556588U, // t2QSAX - 555265U, // t2QSUB - 554762U, // t2QSUB16 - 554864U, // t2QSUB8 - 539998U, // t2RBIT - 9059798U, // t2REV - 9058132U, // t2REV16 - 9058927U, // t2REVSH - 1074313336U, // t2RFEDB - 2148055160U, // t2RFEDBW - 1074313224U, // t2RFEIA - 2148055048U, // t2RFEIAW - 9051246U, // t2RORri - 9051246U, // t2RORrr - 544424U, // t2RRX - 9050304U, // t2RSBri - 530624U, // t2RSBrr - 559296U, // t2RSBrs - 554807U, // t2SADD16 - 554909U, // t2SADD8 - 556734U, // t2SASX - 530741U, // t2SBCri - 9050421U, // t2SBCrr - 9079093U, // t2SBCrs - 548506U, // t2SBFX - 556506U, // t2SDIV - 555794U, // t2SEL - 828701U, // t2SETPAN - 838170U, // t2SG - 554783U, // t2SHADD16 - 554888U, // t2SHADD8 - 556716U, // t2SHASX - 556575U, // t2SHSAX - 554745U, // t2SHSUB16 - 554849U, // t2SHSUB8 - 1074313546U, // t2SMC - 546910U, // t2SMLABB - 548108U, // t2SMLABT - 547171U, // t2SMLAD - 548432U, // t2SMLADX - 580312U, // t2SMLAL - 579685U, // t2SMLALBB - 580889U, // t2SMLALBT - 579992U, // t2SMLALD - 581214U, // t2SMLALDX - 579797U, // t2SMLALTB - 581011U, // t2SMLALTT - 547016U, // t2SMLATB - 548236U, // t2SMLATT - 547083U, // t2SMLAWB - 548284U, // t2SMLAWT - 547257U, // t2SMLSD - 548462U, // t2SMLSDX - 580003U, // t2SMLSLD - 581222U, // t2SMLSLDX - 546850U, // t2SMMLA - 547907U, // t2SMMLAR - 548019U, // t2SMMLS - 547968U, // t2SMMLSR - 555891U, // t2SMMUL - 556130U, // t2SMMULR - 555369U, // t2SMUAD - 556631U, // t2SMUADX - 555117U, // t2SMULBB - 556321U, // t2SMULBT - 547658U, // t2SMULL - 555229U, // t2SMULTB - 556443U, // t2SMULTT - 555282U, // t2SMULWB - 556483U, // t2SMULWT - 555455U, // t2SMUSD - 556661U, // t2SMUSDX - 9222284U, // t2SRSDB - 9353356U, // t2SRSDB_UPD - 9222172U, // t2SRSIA - 9353244U, // t2SRSIA_UPD - 548093U, // t2SSAT - 554821U, // t2SSAT16 - 556593U, // t2SSAX - 554769U, // t2SSUB16 - 554870U, // t2SSUB8 - 1275615927U, // t2STC2L_OFFSET - 1275615927U, // t2STC2L_OPTION - 1275615927U, // t2STC2L_POST - 1275615927U, // t2STC2L_PRE - 1275614869U, // t2STC2_OFFSET - 1275614869U, // t2STC2_OPTION - 1275614869U, // t2STC2_POST - 1275614869U, // t2STC2_PRE - 1275615994U, // t2STCL_OFFSET - 1275615994U, // t2STCL_OPTION - 1275615994U, // t2STCL_POST - 1275615994U, // t2STCL_PRE - 1275615579U, // t2STC_OFFSET - 1275615579U, // t2STC_OPTION - 1275615579U, // t2STC_POST - 1275615579U, // t2STC_PRE - 539503U, // t2STL - 538782U, // t2STLB - 556674U, // t2STLEX - 555296U, // t2STLEXB - 547276U, // t2STLEXD - 555654U, // t2STLEXH - 539195U, // t2STLH - 571526U, // t2STMDB - 2332571782U, // t2STMDB_UPD - 9091986U, // t2STMIA - 2341092242U, // t2STMIA_UPD - 556334U, // t2STRBT - 185096369U, // t2STRB_POST - 185096369U, // t2STRB_PRE - 9074865U, // t2STRBi12 - 555185U, // t2STRBi8 - 9066673U, // t2STRBs - 185100724U, // t2STRD_POST - 185100724U, // t2STRD_PRE - 547252U, // t2STRDi8 - 548500U, // t2STREX - 555310U, // t2STREXB - 547290U, // t2STREXD - 555668U, // t2STREXH - 556369U, // t2STRHT - 185096790U, // t2STRH_POST - 185096790U, // t2STRH_PRE - 9075286U, // t2STRHi12 - 555606U, // t2STRHi8 - 9067094U, // t2STRHs - 556418U, // t2STRT - 185097364U, // t2STR_POST - 185097364U, // t2STR_PRE - 9075860U, // t2STRi12 - 556180U, // t2STRi8 - 9067668U, // t2STRs - 9485481U, // t2SUBS_PC_LR - 9050358U, // t2SUBri - 556527U, // t2SUBri12 - 9050358U, // t2SUBrr - 9079030U, // t2SUBrs - 546898U, // t2SXTAB - 546523U, // t2SXTAB16 - 547371U, // t2SXTAH - 9074922U, // t2SXTB - 554731U, // t2SXTB16 - 9075317U, // t2SXTH - 923285620U, // t2TBB - 940063287U, // t2TBH - 9059391U, // t2TEQri - 9059391U, // t2TEQrr - 9075775U, // t2TEQrs - 956872900U, // t2TSB - 9059720U, // t2TSTri - 9059720U, // t2TSTrr - 9076104U, // t2TSTrs - 540048U, // t2TT - 538697U, // t2TTA - 539911U, // t2TTAT - 540066U, // t2TTT - 554814U, // t2UADD16 - 554915U, // t2UADD8 - 556739U, // t2UASX - 548511U, // t2UBFX - 828738U, // t2UDF - 556511U, // t2UDIV - 554791U, // t2UHADD16 - 554895U, // t2UHADD8 - 556722U, // t2UHASX - 556581U, // t2UHSAX - 554753U, // t2UHSUB16 - 554856U, // t2UHSUB8 - 580285U, // t2UMAAL - 580318U, // t2UMLAL - 547664U, // t2UMULL - 554799U, // t2UQADD16 - 554902U, // t2UQADD8 - 556728U, // t2UQASX - 556587U, // t2UQSAX - 554761U, // t2UQSUB16 - 554863U, // t2UQSUB8 - 554882U, // t2USAD8 - 546650U, // t2USADA8 - 548098U, // t2USAT - 554828U, // t2USAT16 - 556598U, // t2USAX - 554776U, // t2USUB16 - 554876U, // t2USUB8 - 546904U, // t2UXTAB - 546531U, // t2UXTAB16 - 547377U, // t2UXTAH - 9074927U, // t2UXTB - 554738U, // t2UXTB16 - 9075322U, // t2UXTH - 982776121U, // tADC - 555382U, // tADDhirr - 177469814U, // tADDi3 - 982776182U, // tADDi8 - 555382U, // tADDrSP - 555382U, // tADDrSPi - 177469814U, // tADDrr - 555382U, // tADDspi - 555382U, // tADDspr - 539726U, // tADR - 982776235U, // tAND - 177470588U, // tASRri - 982776956U, // tASRrr - 1074313296U, // tB - 982776134U, // tBIC - 828725U, // tBKPT - 1242090220U, // tBL - 1242090708U, // tBLXNSr - 1242091172U, // tBLXi - 1242091172U, // tBLXr - 1074314816U, // tBX - 1074314447U, // tBXNS - 1074313296U, // tBcc - 1258988910U, // tCBNZ - 1258988905U, // tCBZ - 539583U, // tCMNz - 539683U, // tCMPhir - 539683U, // tCMPi8 - 539683U, // tCMPr - 1308687581U, // tCPS - 982776938U, // tEOR - 1074314610U, // tHINT - 828720U, // tHLT - 0U, // tInt_WIN_eh_sjlj_longjmp - 0U, // tInt_eh_sjlj_longjmp - 0U, // tInt_eh_sjlj_setjmp - 572300U, // tLDMIA - 555180U, // tLDRBi - 555180U, // tLDRBr - 555601U, // tLDRHi - 555601U, // tLDRHr - 555198U, // tLDRSB - 555620U, // tLDRSH - 556115U, // tLDRi - 539731U, // tLDRpci - 556115U, // tLDRr - 556115U, // tLDRspi - 177470309U, // tLSLri - 982776677U, // tLSLrr - 177470595U, // tLSRri - 982776963U, // tLSRrr - 1258988842U, // tMOVSr - 446037482U, // tMOVi8 - 540138U, // tMOVr - 177470325U, // tMUL - 446036995U, // tMVN - 982776952U, // tORR - 0U, // tPICADD - 990432295U, // tPOP - 990431850U, // tPUSH - 540118U, // tREV - 538452U, // tREV16 - 539247U, // tREVSH - 982776942U, // tROR - 429258944U, // tRSB - 982776117U, // tSBC - 91368U, // tSETEND - 2332572562U, // tSTMIA_UPD - 555185U, // tSTRBi - 555185U, // tSTRBr - 555606U, // tSTRHi - 555606U, // tSTRHr - 556180U, // tSTRi - 556180U, // tSTRr - 556180U, // tSTRspi - 177469686U, // tSUBi3 - 982776054U, // tSUBi8 - 177469686U, // tSUBrr - 555254U, // tSUBspi - 1074313567U, // tSVC - 538858U, // tSXTB - 539253U, // tSXTH - 3092U, // tTRAP - 540040U, // tTST - 828656U, // tUDF - 538863U, // tUXTB - 539258U, // tUXTH - 1636U, // t__brkdiv0 + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 1981U, // DBG_VALUE + 1991U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 1974U, // BUNDLE + 2020U, // LIFETIME_START + 1961U, // LIFETIME_END + 0U, // STACKMAP + 2862U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 1568U, // PATCHABLE_FUNCTION_ENTER + 1488U, // PATCHABLE_RET + 1614U, // PATCHABLE_FUNCTION_EXIT + 1591U, // PATCHABLE_TAIL_CALL + 1543U, // PATCHABLE_EVENT_CALL + 1519U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // ABS + 0U, // ADDSri + 0U, // ADDSrr + 0U, // ADDSrsi + 0U, // ADDSrsr + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 7292U, // ASRi + 7292U, // ASRr + 0U, // B + 0U, // BCCZi64 + 0U, // BCCi64 + 0U, // BMOVPCB_CALL + 0U, // BMOVPCRX_CALL + 0U, // BR_JTadd + 0U, // BR_JTm_i12 + 0U, // BR_JTm_rs + 0U, // BR_JTr + 0U, // BX_CALL + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_STRUCT_BYVAL_I32 + 2001U, // CompilerBarrier + 16788832U, // ITasm + 0U, // Int_eh_sjlj_dispatchsetup + 0U, // Int_eh_sjlj_longjmp + 0U, // Int_eh_sjlj_setjmp + 0U, // Int_eh_sjlj_setjmp_nofp + 0U, // Int_eh_sjlj_setup_dispatch + 0U, // JUMPTABLE_ADDRS + 0U, // JUMPTABLE_INSTS + 0U, // JUMPTABLE_TBB + 0U, // JUMPTABLE_TBH + 0U, // LDMIA_RET + 15656U, // LDRBT_POST + 15443U, // LDRConstPool + 0U, // LDRLIT_ga_abs + 0U, // LDRLIT_ga_pcrel + 0U, // LDRLIT_ga_pcrel_ldr + 15735U, // LDRT_POST + 0U, // LEApcrel + 0U, // LEApcrelJT + 7013U, // LSLi + 7013U, // LSLr + 7299U, // LSRi + 7299U, // LSRr + 0U, // MEMCPY + 0U, // MLAv5 + 0U, // MOVCCi + 0U, // MOVCCi16 + 0U, // MOVCCi32imm + 0U, // MOVCCr + 0U, // MOVCCsi + 0U, // MOVCCsr + 0U, // MOVPCRX + 0U, // MOVTi16_ga_pcrel + 0U, // MOV_ga_pcrel + 0U, // MOV_ga_pcrel_ldr + 0U, // MOVi16_ga_pcrel + 0U, // MOVi32imm + 0U, // MOVsra_flag + 0U, // MOVsrl_flag + 0U, // MULv5 + 0U, // MVNCCi + 0U, // PICADD + 0U, // PICLDR + 0U, // PICLDRB + 0U, // PICLDRH + 0U, // PICLDRSB + 0U, // PICLDRSH + 0U, // PICSTR + 0U, // PICSTRB + 0U, // PICSTRH + 7278U, // RORi + 7278U, // RORr + 0U, // RRX + 20136U, // RRXi + 0U, // RSBSri + 0U, // RSBSrsi + 0U, // RSBSrsr + 0U, // SMLALv5 + 0U, // SMULLv5 + 0U, // SPACE + 15662U, // STRBT_POST + 0U, // STRBi_preidx + 0U, // STRBr_preidx + 0U, // STRH_preidx + 15746U, // STRT_POST + 0U, // STRi_preidx + 0U, // STRr_preidx + 0U, // SUBS_PC_LR + 0U, // SUBSri + 0U, // SUBSrr + 0U, // SUBSrsi + 0U, // SUBSrsr + 0U, // TAILJMPd + 0U, // TAILJMPr + 0U, // TAILJMPr4 + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TPsoft + 0U, // UMLALv5 + 0U, // UMULLv5 + 153198U, // VLD1LNdAsm_16 + 284270U, // VLD1LNdAsm_32 + 415342U, // VLD1LNdAsm_8 + 153198U, // VLD1LNdWB_fixed_Asm_16 + 284270U, // VLD1LNdWB_fixed_Asm_32 + 415342U, // VLD1LNdWB_fixed_Asm_8 + 157294U, // VLD1LNdWB_register_Asm_16 + 288366U, // VLD1LNdWB_register_Asm_32 + 419438U, // VLD1LNdWB_register_Asm_8 + 153242U, // VLD2LNdAsm_16 + 284314U, // VLD2LNdAsm_32 + 415386U, // VLD2LNdAsm_8 + 153242U, // VLD2LNdWB_fixed_Asm_16 + 284314U, // VLD2LNdWB_fixed_Asm_32 + 415386U, // VLD2LNdWB_fixed_Asm_8 + 157338U, // VLD2LNdWB_register_Asm_16 + 288410U, // VLD2LNdWB_register_Asm_32 + 419482U, // VLD2LNdWB_register_Asm_8 + 153242U, // VLD2LNqAsm_16 + 284314U, // VLD2LNqAsm_32 + 153242U, // VLD2LNqWB_fixed_Asm_16 + 284314U, // VLD2LNqWB_fixed_Asm_32 + 157338U, // VLD2LNqWB_register_Asm_16 + 288410U, // VLD2LNqWB_register_Asm_32 + 1107457722U, // VLD3DUPdAsm_16 + 1107588794U, // VLD3DUPdAsm_32 + 1107719866U, // VLD3DUPdAsm_8 + 2181199546U, // VLD3DUPdWB_fixed_Asm_16 + 2181330618U, // VLD3DUPdWB_fixed_Asm_32 + 2181461690U, // VLD3DUPdWB_fixed_Asm_8 + 33707706U, // VLD3DUPdWB_register_Asm_16 + 33838778U, // VLD3DUPdWB_register_Asm_32 + 33969850U, // VLD3DUPdWB_register_Asm_8 + 1124234938U, // VLD3DUPqAsm_16 + 1124366010U, // VLD3DUPqAsm_32 + 1124497082U, // VLD3DUPqAsm_8 + 2197976762U, // VLD3DUPqWB_fixed_Asm_16 + 2198107834U, // VLD3DUPqWB_fixed_Asm_32 + 2198238906U, // VLD3DUPqWB_fixed_Asm_8 + 50484922U, // VLD3DUPqWB_register_Asm_16 + 50615994U, // VLD3DUPqWB_register_Asm_32 + 50747066U, // VLD3DUPqWB_register_Asm_8 + 153274U, // VLD3LNdAsm_16 + 284346U, // VLD3LNdAsm_32 + 415418U, // VLD3LNdAsm_8 + 153274U, // VLD3LNdWB_fixed_Asm_16 + 284346U, // VLD3LNdWB_fixed_Asm_32 + 415418U, // VLD3LNdWB_fixed_Asm_8 + 157370U, // VLD3LNdWB_register_Asm_16 + 288442U, // VLD3LNdWB_register_Asm_32 + 419514U, // VLD3LNdWB_register_Asm_8 + 153274U, // VLD3LNqAsm_16 + 284346U, // VLD3LNqAsm_32 + 153274U, // VLD3LNqWB_fixed_Asm_16 + 284346U, // VLD3LNqWB_fixed_Asm_32 + 157370U, // VLD3LNqWB_register_Asm_16 + 288442U, // VLD3LNqWB_register_Asm_32 + 3288495802U, // VLD3dAsm_16 + 3288626874U, // VLD3dAsm_32 + 3288757946U, // VLD3dAsm_8 + 3288495802U, // VLD3dWB_fixed_Asm_16 + 3288626874U, // VLD3dWB_fixed_Asm_32 + 3288757946U, // VLD3dWB_fixed_Asm_8 + 3288487610U, // VLD3dWB_register_Asm_16 + 3288618682U, // VLD3dWB_register_Asm_32 + 3288749754U, // VLD3dWB_register_Asm_8 + 1157789370U, // VLD3qAsm_16 + 1157920442U, // VLD3qAsm_32 + 1158051514U, // VLD3qAsm_8 + 2231531194U, // VLD3qWB_fixed_Asm_16 + 2231662266U, // VLD3qWB_fixed_Asm_32 + 2231793338U, // VLD3qWB_fixed_Asm_8 + 84039354U, // VLD3qWB_register_Asm_16 + 84170426U, // VLD3qWB_register_Asm_32 + 84301498U, // VLD3qWB_register_Asm_8 + 1174566609U, // VLD4DUPdAsm_16 + 1174697681U, // VLD4DUPdAsm_32 + 1174828753U, // VLD4DUPdAsm_8 + 2248308433U, // VLD4DUPdWB_fixed_Asm_16 + 2248439505U, // VLD4DUPdWB_fixed_Asm_32 + 2248570577U, // VLD4DUPdWB_fixed_Asm_8 + 100816593U, // VLD4DUPdWB_register_Asm_16 + 100947665U, // VLD4DUPdWB_register_Asm_32 + 101078737U, // VLD4DUPdWB_register_Asm_8 + 1191343825U, // VLD4DUPqAsm_16 + 1191474897U, // VLD4DUPqAsm_32 + 1191605969U, // VLD4DUPqAsm_8 + 2265085649U, // VLD4DUPqWB_fixed_Asm_16 + 2265216721U, // VLD4DUPqWB_fixed_Asm_32 + 2265347793U, // VLD4DUPqWB_fixed_Asm_8 + 117593809U, // VLD4DUPqWB_register_Asm_16 + 117724881U, // VLD4DUPqWB_register_Asm_32 + 117855953U, // VLD4DUPqWB_register_Asm_8 + 153297U, // VLD4LNdAsm_16 + 284369U, // VLD4LNdAsm_32 + 415441U, // VLD4LNdAsm_8 + 153297U, // VLD4LNdWB_fixed_Asm_16 + 284369U, // VLD4LNdWB_fixed_Asm_32 + 415441U, // VLD4LNdWB_fixed_Asm_8 + 157393U, // VLD4LNdWB_register_Asm_16 + 288465U, // VLD4LNdWB_register_Asm_32 + 419537U, // VLD4LNdWB_register_Asm_8 + 153297U, // VLD4LNqAsm_16 + 284369U, // VLD4LNqAsm_32 + 153297U, // VLD4LNqWB_fixed_Asm_16 + 284369U, // VLD4LNqWB_fixed_Asm_32 + 157393U, // VLD4LNqWB_register_Asm_16 + 288465U, // VLD4LNqWB_register_Asm_32 + 3355604689U, // VLD4dAsm_16 + 3355735761U, // VLD4dAsm_32 + 3355866833U, // VLD4dAsm_8 + 3355604689U, // VLD4dWB_fixed_Asm_16 + 3355735761U, // VLD4dWB_fixed_Asm_32 + 3355866833U, // VLD4dWB_fixed_Asm_8 + 3355596497U, // VLD4dWB_register_Asm_16 + 3355727569U, // VLD4dWB_register_Asm_32 + 3355858641U, // VLD4dWB_register_Asm_8 + 1224898257U, // VLD4qAsm_16 + 1225029329U, // VLD4qAsm_32 + 1225160401U, // VLD4qAsm_8 + 2298640081U, // VLD4qWB_fixed_Asm_16 + 2298771153U, // VLD4qWB_fixed_Asm_32 + 2298902225U, // VLD4qWB_fixed_Asm_8 + 151148241U, // VLD4qWB_register_Asm_16 + 151279313U, // VLD4qWB_register_Asm_32 + 151410385U, // VLD4qWB_register_Asm_8 + 0U, // VMOVD0 + 0U, // VMOVDcc + 0U, // VMOVQ0 + 0U, // VMOVScc + 153209U, // VST1LNdAsm_16 + 284281U, // VST1LNdAsm_32 + 415353U, // VST1LNdAsm_8 + 153209U, // VST1LNdWB_fixed_Asm_16 + 284281U, // VST1LNdWB_fixed_Asm_32 + 415353U, // VST1LNdWB_fixed_Asm_8 + 157305U, // VST1LNdWB_register_Asm_16 + 288377U, // VST1LNdWB_register_Asm_32 + 419449U, // VST1LNdWB_register_Asm_8 + 153269U, // VST2LNdAsm_16 + 284341U, // VST2LNdAsm_32 + 415413U, // VST2LNdAsm_8 + 153269U, // VST2LNdWB_fixed_Asm_16 + 284341U, // VST2LNdWB_fixed_Asm_32 + 415413U, // VST2LNdWB_fixed_Asm_8 + 157365U, // VST2LNdWB_register_Asm_16 + 288437U, // VST2LNdWB_register_Asm_32 + 419509U, // VST2LNdWB_register_Asm_8 + 153269U, // VST2LNqAsm_16 + 284341U, // VST2LNqAsm_32 + 153269U, // VST2LNqWB_fixed_Asm_16 + 284341U, // VST2LNqWB_fixed_Asm_32 + 157365U, // VST2LNqWB_register_Asm_16 + 288437U, // VST2LNqWB_register_Asm_32 + 153285U, // VST3LNdAsm_16 + 284357U, // VST3LNdAsm_32 + 415429U, // VST3LNdAsm_8 + 153285U, // VST3LNdWB_fixed_Asm_16 + 284357U, // VST3LNdWB_fixed_Asm_32 + 415429U, // VST3LNdWB_fixed_Asm_8 + 157381U, // VST3LNdWB_register_Asm_16 + 288453U, // VST3LNdWB_register_Asm_32 + 419525U, // VST3LNdWB_register_Asm_8 + 153285U, // VST3LNqAsm_16 + 284357U, // VST3LNqAsm_32 + 153285U, // VST3LNqWB_fixed_Asm_16 + 284357U, // VST3LNqWB_fixed_Asm_32 + 157381U, // VST3LNqWB_register_Asm_16 + 288453U, // VST3LNqWB_register_Asm_32 + 3288495813U, // VST3dAsm_16 + 3288626885U, // VST3dAsm_32 + 3288757957U, // VST3dAsm_8 + 3288495813U, // VST3dWB_fixed_Asm_16 + 3288626885U, // VST3dWB_fixed_Asm_32 + 3288757957U, // VST3dWB_fixed_Asm_8 + 3288487621U, // VST3dWB_register_Asm_16 + 3288618693U, // VST3dWB_register_Asm_32 + 3288749765U, // VST3dWB_register_Asm_8 + 1157789381U, // VST3qAsm_16 + 1157920453U, // VST3qAsm_32 + 1158051525U, // VST3qAsm_8 + 2231531205U, // VST3qWB_fixed_Asm_16 + 2231662277U, // VST3qWB_fixed_Asm_32 + 2231793349U, // VST3qWB_fixed_Asm_8 + 84039365U, // VST3qWB_register_Asm_16 + 84170437U, // VST3qWB_register_Asm_32 + 84301509U, // VST3qWB_register_Asm_8 + 153302U, // VST4LNdAsm_16 + 284374U, // VST4LNdAsm_32 + 415446U, // VST4LNdAsm_8 + 153302U, // VST4LNdWB_fixed_Asm_16 + 284374U, // VST4LNdWB_fixed_Asm_32 + 415446U, // VST4LNdWB_fixed_Asm_8 + 157398U, // VST4LNdWB_register_Asm_16 + 288470U, // VST4LNdWB_register_Asm_32 + 419542U, // VST4LNdWB_register_Asm_8 + 153302U, // VST4LNqAsm_16 + 284374U, // VST4LNqAsm_32 + 153302U, // VST4LNqWB_fixed_Asm_16 + 284374U, // VST4LNqWB_fixed_Asm_32 + 157398U, // VST4LNqWB_register_Asm_16 + 288470U, // VST4LNqWB_register_Asm_32 + 3355604694U, // VST4dAsm_16 + 3355735766U, // VST4dAsm_32 + 3355866838U, // VST4dAsm_8 + 3355604694U, // VST4dWB_fixed_Asm_16 + 3355735766U, // VST4dWB_fixed_Asm_32 + 3355866838U, // VST4dWB_fixed_Asm_8 + 3355596502U, // VST4dWB_register_Asm_16 + 3355727574U, // VST4dWB_register_Asm_32 + 3355858646U, // VST4dWB_register_Asm_8 + 1224898262U, // VST4qAsm_16 + 1225029334U, // VST4qAsm_32 + 1225160406U, // VST4qAsm_8 + 2298640086U, // VST4qWB_fixed_Asm_16 + 2298771158U, // VST4qWB_fixed_Asm_32 + 2298902230U, // VST4qWB_fixed_Asm_8 + 151148246U, // VST4qWB_register_Asm_16 + 151279318U, // VST4qWB_register_Asm_32 + 151410390U, // VST4qWB_register_Asm_8 + 0U, // WIN__CHKSTK + 0U, // WIN__DBZCHK + 0U, // t2ABS + 0U, // t2ADDSri + 0U, // t2ADDSrr + 0U, // t2ADDSrs + 0U, // t2BR_JT + 0U, // t2LDMIA_RET + 14508U, // t2LDRBpcrel + 15443U, // t2LDRConstPool + 14929U, // t2LDRHpcrel + 14526U, // t2LDRSBpcrel + 14948U, // t2LDRSHpcrel + 0U, // t2LDRpci_pic + 15443U, // t2LDRpcrel + 0U, // t2LEApcrel + 0U, // t2LEApcrelJT + 0U, // t2MOVCCasr + 0U, // t2MOVCCi + 0U, // t2MOVCCi16 + 0U, // t2MOVCCi32imm + 0U, // t2MOVCClsl + 0U, // t2MOVCClsr + 0U, // t2MOVCCr + 0U, // t2MOVCCror + 31992U, // t2MOVSsi + 23800U, // t2MOVSsr + 0U, // t2MOVTi16_ga_pcrel + 0U, // t2MOV_ga_pcrel + 0U, // t2MOVi16_ga_pcrel + 0U, // t2MOVi32imm + 32234U, // t2MOVsi + 24042U, // t2MOVsr + 0U, // t2MVNCCi + 0U, // t2RSBSri + 0U, // t2RSBSrs + 0U, // t2STRB_preidx + 0U, // t2STRH_preidx + 0U, // t2STR_preidx + 0U, // t2SUBSri + 0U, // t2SUBSrr + 0U, // t2SUBSrs + 0U, // t2TBB_JT + 0U, // t2TBH_JT + 0U, // tADCS + 0U, // tADDSi3 + 0U, // tADDSi8 + 0U, // tADDSrr + 0U, // tADDframe + 0U, // tADJCALLSTACKDOWN + 0U, // tADJCALLSTACKUP + 0U, // tBRIND + 0U, // tBR_JTr + 0U, // tBX_CALL + 0U, // tBX_RET + 0U, // tBX_RET_vararg + 0U, // tBfar + 0U, // tLDMIA_UPD + 15443U, // tLDRConstPool + 0U, // tLDRLIT_ga_abs + 0U, // tLDRLIT_ga_pcrel + 0U, // tLDR_postidx + 0U, // tLDRpci_pic + 0U, // tLEApcrel + 0U, // tLEApcrelJT + 0U, // tMOVCCr_pseudo + 0U, // tPOP_RET + 0U, // tSBCS + 0U, // tSUBSi3 + 0U, // tSUBSi8 + 0U, // tSUBSrr + 0U, // tTAILJMPd + 0U, // tTAILJMPdND + 0U, // tTAILJMPr + 0U, // tTBB_JT + 0U, // tTBH_JT + 0U, // tTPsoft + 530745U, // ADCri + 530745U, // ADCrr + 559417U, // ADCrsi + 39225U, // ADCrsr + 530806U, // ADDri + 530806U, // ADDrr + 559478U, // ADDrsi + 39286U, // ADDrsr + 539726U, // ADR + 1242211449U, // AESD + 1242211457U, // AESE + 1258988646U, // AESIMC + 1258988656U, // AESMC + 530859U, // ANDri + 530859U, // ANDrr + 559531U, // ANDrsi + 39339U, // ANDrsr + 555329U, // BFC + 547483U, // BFI + 530758U, // BICri + 530758U, // BICrr + 559430U, // BICrsi + 39238U, // BICrsr + 828725U, // BKPT + 828697U, // BL + 828772U, // BLX + 1074314916U, // BLX_pred + 828772U, // BLXi + 1074313964U, // BL_pred + 828768U, // BX + 1074313901U, // BXJ + 970304U, // BX_RET + 1074314816U, // BX_pred + 1074313296U, // Bcc + 201907225U, // CDP + 219210157U, // CDP2 + 3726U, // CLREX + 540368U, // CLZ + 539583U, // CMNri + 539583U, // CMNzrr + 555967U, // CMNzrsi + 547775U, // CMNzrsr + 539683U, // CMPri + 539683U, // CMPrr + 556067U, // CMPrsi + 547875U, // CMPrsr + 828709U, // CPS1p + 1309211869U, // CPS2p + 235470045U, // CPS3p + 185246891U, // CRC32B + 185246899U, // CRC32CB + 185246973U, // CRC32CH + 185247057U, // CRC32CW + 185246965U, // CRC32H + 185247049U, // CRC32W + 1074313739U, // DBG + 66762U, // DMB + 66767U, // DSB + 531562U, // EORri + 531562U, // EORrr + 560234U, // EORrsi + 40042U, // EORrsr + 838971U, // ERET + 1326595561U, // FCONSTD + 1326726633U, // FCONSTH + 1326857705U, // FCONSTS + 2332573243U, // FLDMXDB_UPD + 572932U, // FLDMXIA + 2332573188U, // FLDMXIA_UPD + 1625313U, // FMSTAT + 2332573251U, // FSTMXDB_UPD + 572940U, // FSTMXIA + 2332573196U, // FSTMXIA_UPD + 1074314610U, // HINT + 828720U, // HLT + 828638U, // HVC + 70868U, // ISB + 538616U, // LDA + 538701U, // LDAB + 540284U, // LDAEX + 538905U, // LDAEXB + 268974533U, // LDAEXD + 539263U, // LDAEXH + 539165U, // LDAH + 286975243U, // LDC2L_OFFSET + 3524977931U, // LDC2L_OPTION + 303752459U, // LDC2L_POST + 320529675U, // LDC2L_PRE + 286974356U, // LDC2_OFFSET + 3524977044U, // LDC2_OPTION + 303751572U, // LDC2_POST + 320528788U, // LDC2_PRE + 1275615989U, // LDCL_OFFSET + 1275615989U, // LDCL_OPTION + 1275615989U, // LDCL_POST + 1275615989U, // LDCL_PRE + 1275615549U, // LDC_OFFSET + 1275615549U, // LDC_OPTION + 1275615549U, // LDC_POST + 1275615549U, // LDC_PRE + 571388U, // LDMDA + 2332571644U, // LDMDA_UPD + 571519U, // LDMDB + 2332571775U, // LDMDB_UPD + 572300U, // LDMIA + 2332572556U, // LDMIA_UPD + 571538U, // LDMIB + 2332571794U, // LDMIB_UPD + 552232U, // LDRBT_POST_IMM + 552232U, // LDRBT_POST_REG + 551084U, // LDRB_POST_IMM + 551084U, // LDRB_POST_REG + 546988U, // LDRB_PRE_IMM + 551084U, // LDRB_PRE_REG + 555180U, // LDRBi12 + 546988U, // LDRBrs + 551343U, // LDRD + 580015U, // LDRD_POST + 580015U, // LDRD_PRE + 540296U, // LDREX + 538919U, // LDREXB + 268974547U, // LDREXD + 539277U, // LDREXH + 547409U, // LDRH + 548171U, // LDRHTi + 552267U, // LDRHTr + 551505U, // LDRH_POST + 551505U, // LDRH_PRE + 547006U, // LDRSB + 548148U, // LDRSBTi + 552244U, // LDRSBTr + 551102U, // LDRSB_POST + 551102U, // LDRSB_PRE + 547428U, // LDRSH + 548183U, // LDRSHTi + 552279U, // LDRSHTr + 551524U, // LDRSH_POST + 551524U, // LDRSH_PRE + 552311U, // LDRT_POST_IMM + 552311U, // LDRT_POST_REG + 552019U, // LDR_POST_IMM + 552019U, // LDR_POST_REG + 547923U, // LDR_PRE_IMM + 552019U, // LDR_PRE_REG + 556115U, // LDRcp + 556115U, // LDRi12 + 547923U, // LDRrs + 201907274U, // MCR + 168878515U, // MCR2 + 201878642U, // MCRR + 168878521U, // MCRR2 + 559140U, // MLA + 548021U, // MLS + 1887722U, // MOVPCLR + 556471U, // MOVTi16 + 544234U, // MOVi + 540159U, // MOVi16 + 544234U, // MOVr + 544234U, // MOVr_TC + 531946U, // MOVsi + 560618U, // MOVsr + 336124238U, // MRC + 74138U, // MRC2 + 352872786U, // MRRC + 78240U, // MRRC2 + 2148056290U, // MRS + 539874U, // MRSbanked + 3221798114U, // MRSsys + 369638536U, // MSR + 386415752U, // MSRbanked + 369638536U, // MSRi + 531317U, // MUL + 543747U, // MVNi + 543747U, // MVNr + 531459U, // MVNsi + 560131U, // MVNsr + 531576U, // ORRri + 531576U, // ORRrr + 560248U, // ORRrsi + 40056U, // ORRrsr + 548115U, // PKHBT + 547023U, // PKHTB + 83290U, // PLDWi12 + 87386U, // PLDWrs + 83171U, // PLDi12 + 87267U, // PLDrs + 83206U, // PLIi12 + 87302U, // PLIrs + 555406U, // QADD + 554800U, // QADD16 + 554903U, // QADD8 + 556729U, // QASX + 555380U, // QDADD + 555252U, // QDSUB + 556588U, // QSAX + 555265U, // QSUB + 554762U, // QSUB16 + 554864U, // QSUB8 + 539998U, // RBIT + 540118U, // REV + 538452U, // REV16 + 539247U, // REVSH + 828573U, // RFEDA + 2008221U, // RFEDA_UPD + 828604U, // RFEDB + 2008252U, // RFEDB_UPD + 828580U, // RFEIA + 2008228U, // RFEIA_UPD + 828611U, // RFEIB + 2008259U, // RFEIB_UPD + 530624U, // RSBri + 530624U, // RSBrr + 559296U, // RSBrsi + 39104U, // RSBrsr + 530775U, // RSCri + 530775U, // RSCrr + 559447U, // RSCrsi + 39255U, // RSCrsr + 554807U, // SADD16 + 554909U, // SADD8 + 556734U, // SASX + 530741U, // SBCri + 530741U, // SBCrr + 559413U, // SBCrsi + 39221U, // SBCrsr + 548506U, // SBFX + 556506U, // SDIV + 555794U, // SEL + 91368U, // SETEND + 828701U, // SETPAN + 168468546U, // SHA1C + 1258987596U, // SHA1H + 168468578U, // SHA1M + 168468588U, // SHA1P + 168468481U, // SHA1SU0 + 1242210331U, // SHA1SU1 + 168468566U, // SHA256H + 168468533U, // SHA256H2 + 1242210317U, // SHA256SU0 + 168468519U, // SHA256SU1 + 554783U, // SHADD16 + 554888U, // SHADD8 + 556716U, // SHASX + 556575U, // SHSAX + 554745U, // SHSUB16 + 554849U, // SHSUB8 + 1074313546U, // SMC + 546910U, // SMLABB + 548108U, // SMLABT + 547171U, // SMLAD + 548432U, // SMLADX + 96984U, // SMLAL + 579685U, // SMLALBB + 580889U, // SMLALBT + 579992U, // SMLALD + 581214U, // SMLALDX + 579797U, // SMLALTB + 581011U, // SMLALTT + 547016U, // SMLATB + 548236U, // SMLATT + 547083U, // SMLAWB + 548284U, // SMLAWT + 547257U, // SMLSD + 548462U, // SMLSDX + 580003U, // SMLSLD + 581222U, // SMLSLDX + 546850U, // SMMLA + 547907U, // SMMLAR + 548019U, // SMMLS + 547968U, // SMMLSR + 555891U, // SMMUL + 556130U, // SMMULR + 555369U, // SMUAD + 556631U, // SMUADX + 555117U, // SMULBB + 556321U, // SMULBT + 559946U, // SMULL + 555229U, // SMULTB + 556443U, // SMULTT + 555282U, // SMULWB + 556483U, // SMULWT + 555455U, // SMUSD + 556661U, // SMUSDX + 828836U, // SRSDA + 828788U, // SRSDA_UPD + 828858U, // SRSDB + 828812U, // SRSDB_UPD + 828847U, // SRSIA + 828800U, // SRSIA_UPD + 828869U, // SRSIB + 828824U, // SRSIB_UPD + 548093U, // SSAT + 554821U, // SSAT16 + 556593U, // SSAX + 554769U, // SSUB16 + 554870U, // SSUB8 + 286975250U, // STC2L_OFFSET + 3524977938U, // STC2L_OPTION + 303752466U, // STC2L_POST + 320529682U, // STC2L_PRE + 286974375U, // STC2_OFFSET + 3524977063U, // STC2_OPTION + 303751591U, // STC2_POST + 320528807U, // STC2_PRE + 1275615994U, // STCL_OFFSET + 1275615994U, // STCL_OPTION + 1275615994U, // STCL_POST + 1275615994U, // STCL_PRE + 1275615579U, // STC_OFFSET + 1275615579U, // STC_OPTION + 1275615579U, // STC_POST + 1275615579U, // STC_PRE + 539503U, // STL + 538782U, // STLB + 556674U, // STLEX + 555296U, // STLEXB + 555468U, // STLEXD + 555654U, // STLEXH + 539195U, // STLH + 571394U, // STMDA + 2332571650U, // STMDA_UPD + 571526U, // STMDB + 2332571782U, // STMDB_UPD + 572306U, // STMIA + 2332572562U, // STMIA_UPD + 571544U, // STMIB + 2332571800U, // STMIB_UPD + 185101614U, // STRBT_POST_IMM + 185101614U, // STRBT_POST_REG + 185100465U, // STRB_POST_IMM + 185100465U, // STRB_POST_REG + 185096369U, // STRB_PRE_IMM + 185100465U, // STRB_PRE_REG + 555185U, // STRBi12 + 546993U, // STRBrs + 551348U, // STRD + 185129396U, // STRD_POST + 185129396U, // STRD_PRE + 556692U, // STREX + 555310U, // STREXB + 555482U, // STREXD + 555668U, // STREXH + 547414U, // STRH + 185097553U, // STRHTi + 185101649U, // STRHTr + 185100886U, // STRH_POST + 185100886U, // STRH_PRE + 185101698U, // STRT_POST_IMM + 185101698U, // STRT_POST_REG + 185101460U, // STR_POST_IMM + 185101460U, // STR_POST_REG + 185097364U, // STR_PRE_IMM + 185101460U, // STR_PRE_REG + 556180U, // STRi12 + 547988U, // STRrs + 530678U, // SUBri + 530678U, // SUBrr + 559350U, // SUBrsi + 39158U, // SUBrsr + 1074313567U, // SVC + 556081U, // SWP + 555175U, // SWPB + 546898U, // SXTAB + 546523U, // SXTAB16 + 547371U, // SXTAH + 555242U, // SXTB + 554731U, // SXTB16 + 555637U, // SXTH + 539711U, // TEQri + 539711U, // TEQrr + 556095U, // TEQrsi + 547903U, // TEQrsr + 3092U, // TRAP + 3092U, // TRAPNaCl + 99545U, // TSB + 540040U, // TSTri + 540040U, // TSTrr + 556424U, // TSTrsi + 548232U, // TSTrsr + 554814U, // UADD16 + 554915U, // UADD8 + 556739U, // UASX + 548511U, // UBFX + 828656U, // UDF + 556511U, // UDIV + 554791U, // UHADD16 + 554895U, // UHADD8 + 556722U, // UHASX + 556581U, // UHSAX + 554753U, // UHSUB16 + 554856U, // UHSUB8 + 580285U, // UMAAL + 96990U, // UMLAL + 559952U, // UMULL + 554799U, // UQADD16 + 554902U, // UQADD8 + 556728U, // UQASX + 556587U, // UQSAX + 554761U, // UQSUB16 + 554863U, // UQSUB8 + 554882U, // USAD8 + 546650U, // USADA8 + 548098U, // USAT + 554828U, // USAT16 + 556598U, // USAX + 554776U, // USUB16 + 554876U, // USUB8 + 546904U, // UXTAB + 546531U, // UXTAB16 + 547377U, // UXTAH + 555247U, // UXTB + 554738U, // UXTB16 + 555642U, // UXTH + 169892547U, // VABALsv2i64 + 170023619U, // VABALsv4i32 + 170154691U, // VABALsv8i16 + 170285763U, // VABALuv2i64 + 170416835U, // VABALuv4i32 + 170547907U, // VABALuv8i16 + 170153971U, // VABAsv16i8 + 169891827U, // VABAsv2i32 + 170022899U, // VABAsv4i16 + 169891827U, // VABAsv4i32 + 170022899U, // VABAsv8i16 + 170153971U, // VABAsv8i8 + 170547187U, // VABAuv16i8 + 170285043U, // VABAuv2i32 + 170416115U, // VABAuv4i16 + 170285043U, // VABAuv4i32 + 170416115U, // VABAuv8i16 + 170547187U, // VABAuv8i8 + 186678015U, // VABDLsv2i64 + 186809087U, // VABDLsv4i32 + 186940159U, // VABDLsv8i16 + 187071231U, // VABDLuv2i64 + 187202303U, // VABDLuv4i32 + 187333375U, // VABDLuv8i16 + 253131119U, // VABDfd + 253131119U, // VABDfq + 253000047U, // VABDhd + 253000047U, // VABDhq + 186939759U, // VABDsv16i8 + 186677615U, // VABDsv2i32 + 186808687U, // VABDsv4i16 + 186677615U, // VABDsv4i32 + 186808687U, // VABDsv8i16 + 186939759U, // VABDsv8i8 + 187332975U, // VABDuv16i8 + 187070831U, // VABDuv2i32 + 187201903U, // VABDuv4i16 + 187070831U, // VABDuv4i32 + 187201903U, // VABDuv8i16 + 187332975U, // VABDuv8i8 + 252853412U, // VABSD + 252984484U, // VABSH + 253115556U, // VABSS + 253115556U, // VABSfd + 253115556U, // VABSfq + 252984484U, // VABShd + 252984484U, // VABShq + 1260666020U, // VABSv16i8 + 1260403876U, // VABSv2i32 + 1260534948U, // VABSv4i16 + 1260403876U, // VABSv4i32 + 1260534948U, // VABSv8i16 + 1260666020U, // VABSv8i8 + 253131233U, // VACGEfd + 253131233U, // VACGEfq + 253000161U, // VACGEhd + 253000161U, // VACGEhq + 253132096U, // VACGTfd + 253132096U, // VACGTfq + 253001024U, // VACGThd + 253001024U, // VACGThq + 252869011U, // VADDD + 253000083U, // VADDH + 187464621U, // VADDHNv2i32 + 187595693U, // VADDHNv4i16 + 187726765U, // VADDHNv8i8 + 186678028U, // VADDLsv2i64 + 186809100U, // VADDLsv4i32 + 186940172U, // VADDLsv8i16 + 187071244U, // VADDLuv2i64 + 187202316U, // VADDLuv4i32 + 187333388U, // VADDLuv8i16 + 253131155U, // VADDS + 186678772U, // VADDWsv2i64 + 186809844U, // VADDWsv4i32 + 186940916U, // VADDWsv8i16 + 187071988U, // VADDWuv2i64 + 187203060U, // VADDWuv4i32 + 187334132U, // VADDWuv8i16 + 253131155U, // VADDfd + 253131155U, // VADDfq + 253000083U, // VADDhd + 253000083U, // VADDhq + 187857299U, // VADDv16i8 + 187464083U, // VADDv1i64 + 187595155U, // VADDv2i32 + 187464083U, // VADDv2i64 + 187726227U, // VADDv4i16 + 187595155U, // VADDv4i32 + 187726227U, // VADDv8i16 + 187857299U, // VADDv8i8 + 555434U, // VANDd + 555434U, // VANDq + 555333U, // VBICd + 405698885U, // VBICiv2i32 + 405829957U, // VBICiv4i16 + 405698885U, // VBICiv4i32 + 405829957U, // VBICiv8i16 + 555333U, // VBICq + 547334U, // VBIFd + 547334U, // VBIFq + 548195U, // VBITd + 548195U, // VBITq + 547676U, // VBSLd + 547676U, // VBSLq + 185245957U, // VCADDv2f32 + 185246658U, // VCADDv4f16 + 185245957U, // VCADDv4f32 + 185246658U, // VCADDv8f16 + 253131834U, // VCEQfd + 253131834U, // VCEQfq + 253000762U, // VCEQhd + 253000762U, // VCEQhq + 187857978U, // VCEQv16i8 + 187595834U, // VCEQv2i32 + 187726906U, // VCEQv4i16 + 187595834U, // VCEQv4i32 + 187726906U, // VCEQv8i16 + 187857978U, // VCEQv8i8 + 1261583418U, // VCEQzv16i8 + 253115450U, // VCEQzv2f32 + 1261321274U, // VCEQzv2i32 + 252984378U, // VCEQzv4f16 + 253115450U, // VCEQzv4f32 + 1261452346U, // VCEQzv4i16 + 1261321274U, // VCEQzv4i32 + 252984378U, // VCEQzv8f16 + 1261452346U, // VCEQzv8i16 + 1261583418U, // VCEQzv8i8 + 253131239U, // VCGEfd + 253131239U, // VCGEfq + 253000167U, // VCGEhd + 253000167U, // VCGEhq + 186939879U, // VCGEsv16i8 + 186677735U, // VCGEsv2i32 + 186808807U, // VCGEsv4i16 + 186677735U, // VCGEsv4i32 + 186808807U, // VCGEsv8i16 + 186939879U, // VCGEsv8i8 + 187333095U, // VCGEuv16i8 + 187070951U, // VCGEuv2i32 + 187202023U, // VCGEuv4i16 + 187070951U, // VCGEuv4i32 + 187202023U, // VCGEuv8i16 + 187333095U, // VCGEuv8i8 + 1260665319U, // VCGEzv16i8 + 253114855U, // VCGEzv2f32 + 1260403175U, // VCGEzv2i32 + 252983783U, // VCGEzv4f16 + 253114855U, // VCGEzv4f32 + 1260534247U, // VCGEzv4i16 + 1260403175U, // VCGEzv4i32 + 252983783U, // VCGEzv8f16 + 1260534247U, // VCGEzv8i16 + 1260665319U, // VCGEzv8i8 + 253132102U, // VCGTfd + 253132102U, // VCGTfq + 253001030U, // VCGThd + 253001030U, // VCGThq + 186940742U, // VCGTsv16i8 + 186678598U, // VCGTsv2i32 + 186809670U, // VCGTsv4i16 + 186678598U, // VCGTsv4i32 + 186809670U, // VCGTsv8i16 + 186940742U, // VCGTsv8i8 + 187333958U, // VCGTuv16i8 + 187071814U, // VCGTuv2i32 + 187202886U, // VCGTuv4i16 + 187071814U, // VCGTuv4i32 + 187202886U, // VCGTuv8i16 + 187333958U, // VCGTuv8i8 + 1260666182U, // VCGTzv16i8 + 253115718U, // VCGTzv2f32 + 1260404038U, // VCGTzv2i32 + 252984646U, // VCGTzv4f16 + 253115718U, // VCGTzv4f32 + 1260535110U, // VCGTzv4i16 + 1260404038U, // VCGTzv4i32 + 252984646U, // VCGTzv8f16 + 1260535110U, // VCGTzv8i16 + 1260666182U, // VCGTzv8i8 + 1260665324U, // VCLEzv16i8 + 253114860U, // VCLEzv2f32 + 1260403180U, // VCLEzv2i32 + 252983788U, // VCLEzv4f16 + 253114860U, // VCLEzv4f32 + 1260534252U, // VCLEzv4i16 + 1260403180U, // VCLEzv4i32 + 252983788U, // VCLEzv8f16 + 1260534252U, // VCLEzv8i16 + 1260665324U, // VCLEzv8i8 + 1260666030U, // VCLSv16i8 + 1260403886U, // VCLSv2i32 + 1260534958U, // VCLSv4i16 + 1260403886U, // VCLSv4i32 + 1260534958U, // VCLSv8i16 + 1260666030U, // VCLSv8i8 + 1260666216U, // VCLTzv16i8 + 253115752U, // VCLTzv2f32 + 1260404072U, // VCLTzv2i32 + 252984680U, // VCLTzv4f16 + 253115752U, // VCLTzv4f32 + 1260535144U, // VCLTzv4i16 + 1260404072U, // VCLTzv4i32 + 252984680U, // VCLTzv8f16 + 1260535144U, // VCLTzv8i16 + 1260666216U, // VCLTzv8i8 + 1261584079U, // VCLZv16i8 + 1261321935U, // VCLZv2i32 + 1261453007U, // VCLZv4i16 + 1261321935U, // VCLZv4i32 + 1261453007U, // VCLZv8i16 + 1261584079U, // VCLZv8i8 + 168468718U, // VCMLAv2f32 + 168468718U, // VCMLAv2f32_indexed + 168469419U, // VCMLAv4f16 + 168469419U, // VCMLAv4f16_indexed + 168468718U, // VCMLAv4f32 + 168468718U, // VCMLAv4f32_indexed + 168469419U, // VCMLAv8f16 + 168469419U, // VCMLAv8f16_indexed + 252853282U, // VCMPD + 252852728U, // VCMPED + 252983800U, // VCMPEH + 253114872U, // VCMPES + 420657656U, // VCMPEZD + 420788728U, // VCMPEZH + 420919800U, // VCMPEZS + 252984354U, // VCMPH + 253115426U, // VCMPS + 420658210U, // VCMPZD + 420789282U, // VCMPZH + 420920354U, // VCMPZS + 408941U, // VCNTd + 408941U, // VCNTq + 1258987638U, // VCVTANSDf + 1258988339U, // VCVTANSDh + 1258987638U, // VCVTANSQf + 1258988339U, // VCVTANSQh + 1258987698U, // VCVTANUDf + 1258988399U, // VCVTANUDh + 1258987698U, // VCVTANUQf + 1258988399U, // VCVTANUQh + 1258987968U, // VCVTASD + 1258988219U, // VCVTASH + 1258987638U, // VCVTASS + 1258988028U, // VCVTAUD + 1258988279U, // VCVTAUH + 1258987698U, // VCVTAUS + 3422436U, // VCVTBDH + 3553508U, // VCVTBHD + 3684580U, // VCVTBHS + 3815652U, // VCVTBSH + 3947954U, // VCVTDS + 1258987653U, // VCVTMNSDf + 1258988354U, // VCVTMNSDh + 1258987653U, // VCVTMNSQf + 1258988354U, // VCVTMNSQh + 1258987713U, // VCVTMNUDf + 1258988414U, // VCVTMNUDh + 1258987713U, // VCVTMNUQf + 1258988414U, // VCVTMNUQh + 1258987983U, // VCVTMSD + 1258988234U, // VCVTMSH + 1258987653U, // VCVTMSS + 1258988043U, // VCVTMUD + 1258988294U, // VCVTMUH + 1258987713U, // VCVTMUS + 1258987668U, // VCVTNNSDf + 1258988369U, // VCVTNNSDh + 1258987668U, // VCVTNNSQf + 1258988369U, // VCVTNNSQh + 1258987728U, // VCVTNNUDf + 1258988429U, // VCVTNNUDh + 1258987728U, // VCVTNNUQf + 1258988429U, // VCVTNNUQh + 1258987998U, // VCVTNSD + 1258988249U, // VCVTNSH + 1258987668U, // VCVTNSS + 1258988058U, // VCVTNUD + 1258988309U, // VCVTNUH + 1258987728U, // VCVTNUS + 1258987683U, // VCVTPNSDf + 1258988384U, // VCVTPNSDh + 1258987683U, // VCVTPNSQf + 1258988384U, // VCVTPNSQh + 1258987743U, // VCVTPNUDf + 1258988444U, // VCVTPNUDh + 1258987743U, // VCVTPNUQf + 1258988444U, // VCVTPNUQh + 1258988013U, // VCVTPSD + 1258988264U, // VCVTPSH + 1258987683U, // VCVTPSS + 1258988073U, // VCVTPUD + 1258988324U, // VCVTPUH + 1258987743U, // VCVTPUS + 4079026U, // VCVTSD + 3423654U, // VCVTTDH + 3554726U, // VCVTTHD + 3685798U, // VCVTTHS + 3816870U, // VCVTTSH + 3816882U, // VCVTf2h + 440417714U, // VCVTf2sd + 440417714U, // VCVTf2sq + 440548786U, // VCVTf2ud + 440548786U, // VCVTf2uq + 2403368370U, // VCVTf2xsd + 2403368370U, // VCVTf2xsq + 2403499442U, // VCVTf2xud + 2403499442U, // VCVTf2xuq + 3685810U, // VCVTh2f + 440679858U, // VCVTh2sd + 440679858U, // VCVTh2sq + 440810930U, // VCVTh2ud + 440810930U, // VCVTh2uq + 2403630514U, // VCVTh2xsd + 2403630514U, // VCVTh2xsq + 2403761586U, // VCVTh2xud + 2403761586U, // VCVTh2xuq + 440942002U, // VCVTs2fd + 440942002U, // VCVTs2fq + 441073074U, // VCVTs2hd + 441073074U, // VCVTs2hq + 441204146U, // VCVTu2fd + 441204146U, // VCVTu2fq + 441335218U, // VCVTu2hd + 441335218U, // VCVTu2hq + 2403892658U, // VCVTxs2fd + 2403892658U, // VCVTxs2fq + 2404023730U, // VCVTxs2hd + 2404023730U, // VCVTxs2hq + 2404154802U, // VCVTxu2fd + 2404154802U, // VCVTxu2fq + 2404285874U, // VCVTxu2hd + 2404285874U, // VCVTxu2hq + 252870116U, // VDIVD + 253001188U, // VDIVH + 253132260U, // VDIVS + 146475U, // VDUP16d + 146475U, // VDUP16q + 277547U, // VDUP32d + 277547U, // VDUP32q + 408619U, // VDUP8d + 408619U, // VDUP8q + 162859U, // VDUPLN16d + 162859U, // VDUPLN16q + 293931U, // VDUPLN32d + 293931U, // VDUPLN32q + 425003U, // VDUPLN8d + 425003U, // VDUPLN8q + 556137U, // VEORd + 556137U, // VEORq + 155082U, // VEXTd16 + 286154U, // VEXTd32 + 417226U, // VEXTd8 + 155082U, // VEXTq16 + 286154U, // VEXTq32 + 5266890U, // VEXTq64 + 417226U, // VEXTq8 + 2400344115U, // VFMAD + 2400475187U, // VFMAH + 2400606259U, // VFMAS + 2400606259U, // VFMAfd + 2400606259U, // VFMAfq + 2400475187U, // VFMAhd + 2400475187U, // VFMAhq + 2400345284U, // VFMSD + 2400476356U, // VFMSH + 2400607428U, // VFMSS + 2400607428U, // VFMSfd + 2400607428U, // VFMSfq + 2400476356U, // VFMShd + 2400476356U, // VFMShq + 2400344120U, // VFNMAD + 2400475192U, // VFNMAH + 2400606264U, // VFNMAS + 2400345289U, // VFNMSD + 2400476361U, // VFNMSH + 2400607433U, // VFNMSS + 294377U, // VGETLNi32 + 3408035305U, // VGETLNs16 + 3408166377U, // VGETLNs8 + 3408428521U, // VGETLNu16 + 3408559593U, // VGETLNu8 + 186939777U, // VHADDsv16i8 + 186677633U, // VHADDsv2i32 + 186808705U, // VHADDsv4i16 + 186677633U, // VHADDsv4i32 + 186808705U, // VHADDsv8i16 + 186939777U, // VHADDsv8i8 + 187332993U, // VHADDuv16i8 + 187070849U, // VHADDuv2i32 + 187201921U, // VHADDuv4i16 + 187070849U, // VHADDuv4i32 + 187201921U, // VHADDuv8i16 + 187332993U, // VHADDuv8i8 + 186939642U, // VHSUBsv16i8 + 186677498U, // VHSUBsv2i32 + 186808570U, // VHSUBsv4i16 + 186677498U, // VHSUBsv4i32 + 186808570U, // VHSUBsv8i16 + 186939642U, // VHSUBsv8i8 + 187332858U, // VHSUBuv16i8 + 187070714U, // VHSUBuv2i32 + 187201786U, // VHSUBuv4i16 + 187070714U, // VHSUBuv4i32 + 187201786U, // VHSUBuv8i16 + 187332858U, // VHSUBuv8i8 + 1258988577U, // VINSH + 441597356U, // VJCVT + 3674371694U, // VLD1DUPd16 + 453138030U, // VLD1DUPd16wb_fixed + 453142126U, // VLD1DUPd16wb_register + 3674502766U, // VLD1DUPd32 + 453269102U, // VLD1DUPd32wb_fixed + 453273198U, // VLD1DUPd32wb_register + 3674633838U, // VLD1DUPd8 + 453400174U, // VLD1DUPd8wb_fixed + 453404270U, // VLD1DUPd8wb_register + 3691148910U, // VLD1DUPq16 + 469915246U, // VLD1DUPq16wb_fixed + 469919342U, // VLD1DUPq16wb_register + 3691279982U, // VLD1DUPq32 + 470046318U, // VLD1DUPq32wb_fixed + 470050414U, // VLD1DUPq32wb_register + 3691411054U, // VLD1DUPq8 + 470177390U, // VLD1DUPq8wb_fixed + 470181486U, // VLD1DUPq8wb_register + 1079273070U, // VLD1LNd16 + 1079350894U, // VLD1LNd16_UPD + 1079404142U, // VLD1LNd32 + 1079481966U, // VLD1LNd32_UPD + 1079535214U, // VLD1LNd8 + 1079613038U, // VLD1LNd8_UPD + 0U, // VLD1LNq16Pseudo + 0U, // VLD1LNq16Pseudo_UPD + 0U, // VLD1LNq32Pseudo + 0U, // VLD1LNq32Pseudo_UPD + 0U, // VLD1LNq8Pseudo + 0U, // VLD1LNq8Pseudo_UPD + 3707926126U, // VLD1d16 + 3355604590U, // VLD1d16Q + 0U, // VLD1d16QPseudo + 134370926U, // VLD1d16Qwb_fixed + 134375022U, // VLD1d16Qwb_register + 3288495726U, // VLD1d16T + 0U, // VLD1d16TPseudo + 67262062U, // VLD1d16Twb_fixed + 67266158U, // VLD1d16Twb_register + 486692462U, // VLD1d16wb_fixed + 486696558U, // VLD1d16wb_register + 3708057198U, // VLD1d32 + 3355735662U, // VLD1d32Q + 0U, // VLD1d32QPseudo + 134501998U, // VLD1d32Qwb_fixed + 134506094U, // VLD1d32Qwb_register + 3288626798U, // VLD1d32T + 0U, // VLD1d32TPseudo + 67393134U, // VLD1d32Twb_fixed + 67397230U, // VLD1d32Twb_register + 486823534U, // VLD1d32wb_fixed + 486827630U, // VLD1d32wb_register + 3713037934U, // VLD1d64 + 3360716398U, // VLD1d64Q + 0U, // VLD1d64QPseudo + 0U, // VLD1d64QPseudoWB_fixed + 0U, // VLD1d64QPseudoWB_register + 139482734U, // VLD1d64Qwb_fixed + 139486830U, // VLD1d64Qwb_register + 3293607534U, // VLD1d64T + 0U, // VLD1d64TPseudo + 0U, // VLD1d64TPseudoWB_fixed + 0U, // VLD1d64TPseudoWB_register + 72373870U, // VLD1d64Twb_fixed + 72377966U, // VLD1d64Twb_register + 491804270U, // VLD1d64wb_fixed + 491808366U, // VLD1d64wb_register + 3708188270U, // VLD1d8 + 3355866734U, // VLD1d8Q + 0U, // VLD1d8QPseudo + 134633070U, // VLD1d8Qwb_fixed + 134637166U, // VLD1d8Qwb_register + 3288757870U, // VLD1d8T + 0U, // VLD1d8TPseudo + 67524206U, // VLD1d8Twb_fixed + 67528302U, // VLD1d8Twb_register + 486954606U, // VLD1d8wb_fixed + 486958702U, // VLD1d8wb_register + 3724703342U, // VLD1q16 + 0U, // VLD1q16HighQPseudo + 0U, // VLD1q16HighTPseudo + 0U, // VLD1q16LowQPseudo_UPD + 0U, // VLD1q16LowTPseudo_UPD + 503469678U, // VLD1q16wb_fixed + 503473774U, // VLD1q16wb_register + 3724834414U, // VLD1q32 + 0U, // VLD1q32HighQPseudo + 0U, // VLD1q32HighTPseudo + 0U, // VLD1q32LowQPseudo_UPD + 0U, // VLD1q32LowTPseudo_UPD + 503600750U, // VLD1q32wb_fixed + 503604846U, // VLD1q32wb_register + 3729815150U, // VLD1q64 + 0U, // VLD1q64HighQPseudo + 0U, // VLD1q64HighTPseudo + 0U, // VLD1q64LowQPseudo_UPD + 0U, // VLD1q64LowTPseudo_UPD + 508581486U, // VLD1q64wb_fixed + 508585582U, // VLD1q64wb_register + 3724965486U, // VLD1q8 + 0U, // VLD1q8HighQPseudo + 0U, // VLD1q8HighTPseudo + 0U, // VLD1q8LowQPseudo_UPD + 0U, // VLD1q8LowTPseudo_UPD + 503731822U, // VLD1q8wb_fixed + 503735918U, // VLD1q8wb_register + 3691148954U, // VLD2DUPd16 + 469915290U, // VLD2DUPd16wb_fixed + 469919386U, // VLD2DUPd16wb_register + 3741480602U, // VLD2DUPd16x2 + 520246938U, // VLD2DUPd16x2wb_fixed + 520251034U, // VLD2DUPd16x2wb_register + 3691280026U, // VLD2DUPd32 + 470046362U, // VLD2DUPd32wb_fixed + 470050458U, // VLD2DUPd32wb_register + 3741611674U, // VLD2DUPd32x2 + 520378010U, // VLD2DUPd32x2wb_fixed + 520382106U, // VLD2DUPd32x2wb_register + 3691411098U, // VLD2DUPd8 + 470177434U, // VLD2DUPd8wb_fixed + 470181530U, // VLD2DUPd8wb_register + 3741742746U, // VLD2DUPd8x2 + 520509082U, // VLD2DUPd8x2wb_fixed + 520513178U, // VLD2DUPd8x2wb_register + 0U, // VLD2DUPq16EvenPseudo + 0U, // VLD2DUPq16OddPseudo + 0U, // VLD2DUPq32EvenPseudo + 0U, // VLD2DUPq32OddPseudo + 0U, // VLD2DUPq8EvenPseudo + 0U, // VLD2DUPq8OddPseudo + 1079350938U, // VLD2LNd16 + 0U, // VLD2LNd16Pseudo + 0U, // VLD2LNd16Pseudo_UPD + 1079355034U, // VLD2LNd16_UPD + 1079482010U, // VLD2LNd32 + 0U, // VLD2LNd32Pseudo + 0U, // VLD2LNd32Pseudo_UPD + 1079486106U, // VLD2LNd32_UPD + 1079613082U, // VLD2LNd8 + 0U, // VLD2LNd8Pseudo + 0U, // VLD2LNd8Pseudo_UPD + 1079617178U, // VLD2LNd8_UPD + 1079350938U, // VLD2LNq16 + 0U, // VLD2LNq16Pseudo + 0U, // VLD2LNq16Pseudo_UPD + 1079355034U, // VLD2LNq16_UPD + 1079482010U, // VLD2LNq32 + 0U, // VLD2LNq32Pseudo + 0U, // VLD2LNq32Pseudo_UPD + 1079486106U, // VLD2LNq32_UPD + 3758257818U, // VLD2b16 + 537024154U, // VLD2b16wb_fixed + 537028250U, // VLD2b16wb_register + 3758388890U, // VLD2b32 + 537155226U, // VLD2b32wb_fixed + 537159322U, // VLD2b32wb_register + 3758519962U, // VLD2b8 + 537286298U, // VLD2b8wb_fixed + 537290394U, // VLD2b8wb_register + 3724703386U, // VLD2d16 + 503469722U, // VLD2d16wb_fixed + 503473818U, // VLD2d16wb_register + 3724834458U, // VLD2d32 + 503600794U, // VLD2d32wb_fixed + 503604890U, // VLD2d32wb_register + 3724965530U, // VLD2d8 + 503731866U, // VLD2d8wb_fixed + 503735962U, // VLD2d8wb_register + 3355604634U, // VLD2q16 + 0U, // VLD2q16Pseudo + 0U, // VLD2q16PseudoWB_fixed + 0U, // VLD2q16PseudoWB_register + 134370970U, // VLD2q16wb_fixed + 134375066U, // VLD2q16wb_register + 3355735706U, // VLD2q32 + 0U, // VLD2q32Pseudo + 0U, // VLD2q32PseudoWB_fixed + 0U, // VLD2q32PseudoWB_register + 134502042U, // VLD2q32wb_fixed + 134506138U, // VLD2q32wb_register + 3355866778U, // VLD2q8 + 0U, // VLD2q8Pseudo + 0U, // VLD2q8PseudoWB_fixed + 0U, // VLD2q8PseudoWB_register + 134633114U, // VLD2q8wb_fixed + 134637210U, // VLD2q8wb_register + 2153014970U, // VLD3DUPd16 + 0U, // VLD3DUPd16Pseudo + 0U, // VLD3DUPd16Pseudo_UPD + 2153092794U, // VLD3DUPd16_UPD + 2153146042U, // VLD3DUPd32 + 0U, // VLD3DUPd32Pseudo + 0U, // VLD3DUPd32Pseudo_UPD + 2153223866U, // VLD3DUPd32_UPD + 2153277114U, // VLD3DUPd8 + 0U, // VLD3DUPd8Pseudo + 0U, // VLD3DUPd8Pseudo_UPD + 2153354938U, // VLD3DUPd8_UPD + 2153014970U, // VLD3DUPq16 + 0U, // VLD3DUPq16EvenPseudo + 0U, // VLD3DUPq16OddPseudo + 2153092794U, // VLD3DUPq16_UPD + 2153146042U, // VLD3DUPq32 + 0U, // VLD3DUPq32EvenPseudo + 0U, // VLD3DUPq32OddPseudo + 2153223866U, // VLD3DUPq32_UPD + 2153277114U, // VLD3DUPq8 + 0U, // VLD3DUPq8EvenPseudo + 0U, // VLD3DUPq8OddPseudo + 2153354938U, // VLD3DUPq8_UPD + 1079355066U, // VLD3LNd16 + 0U, // VLD3LNd16Pseudo + 0U, // VLD3LNd16Pseudo_UPD + 1079359162U, // VLD3LNd16_UPD + 1079486138U, // VLD3LNd32 + 0U, // VLD3LNd32Pseudo + 0U, // VLD3LNd32Pseudo_UPD + 1079490234U, // VLD3LNd32_UPD + 1079617210U, // VLD3LNd8 + 0U, // VLD3LNd8Pseudo + 0U, // VLD3LNd8Pseudo_UPD + 1079621306U, // VLD3LNd8_UPD + 1079355066U, // VLD3LNq16 + 0U, // VLD3LNq16Pseudo + 0U, // VLD3LNq16Pseudo_UPD + 1079359162U, // VLD3LNq16_UPD + 1079486138U, // VLD3LNq32 + 0U, // VLD3LNq32Pseudo + 0U, // VLD3LNq32Pseudo_UPD + 1079490234U, // VLD3LNq32_UPD + 5531322U, // VLD3d16 + 0U, // VLD3d16Pseudo + 0U, // VLD3d16Pseudo_UPD + 5609146U, // VLD3d16_UPD + 5662394U, // VLD3d32 + 0U, // VLD3d32Pseudo + 0U, // VLD3d32Pseudo_UPD + 5740218U, // VLD3d32_UPD + 5793466U, // VLD3d8 + 0U, // VLD3d8Pseudo + 0U, // VLD3d8Pseudo_UPD + 5871290U, // VLD3d8_UPD + 5531322U, // VLD3q16 + 0U, // VLD3q16Pseudo_UPD + 5609146U, // VLD3q16_UPD + 0U, // VLD3q16oddPseudo + 0U, // VLD3q16oddPseudo_UPD + 5662394U, // VLD3q32 + 0U, // VLD3q32Pseudo_UPD + 5740218U, // VLD3q32_UPD + 0U, // VLD3q32oddPseudo + 0U, // VLD3q32oddPseudo_UPD + 5793466U, // VLD3q8 + 0U, // VLD3q8Pseudo_UPD + 5871290U, // VLD3q8_UPD + 0U, // VLD3q8oddPseudo + 0U, // VLD3q8oddPseudo_UPD + 2153043665U, // VLD4DUPd16 + 0U, // VLD4DUPd16Pseudo + 0U, // VLD4DUPd16Pseudo_UPD + 2153105105U, // VLD4DUPd16_UPD + 2153174737U, // VLD4DUPd32 + 0U, // VLD4DUPd32Pseudo + 0U, // VLD4DUPd32Pseudo_UPD + 2153236177U, // VLD4DUPd32_UPD + 2153305809U, // VLD4DUPd8 + 0U, // VLD4DUPd8Pseudo + 0U, // VLD4DUPd8Pseudo_UPD + 2153367249U, // VLD4DUPd8_UPD + 2153043665U, // VLD4DUPq16 + 0U, // VLD4DUPq16EvenPseudo + 0U, // VLD4DUPq16OddPseudo + 2153105105U, // VLD4DUPq16_UPD + 2153174737U, // VLD4DUPq32 + 0U, // VLD4DUPq32EvenPseudo + 0U, // VLD4DUPq32OddPseudo + 2153236177U, // VLD4DUPq32_UPD + 2153305809U, // VLD4DUPq8 + 0U, // VLD4DUPq8EvenPseudo + 0U, // VLD4DUPq8OddPseudo + 2153367249U, // VLD4DUPq8_UPD + 1079359185U, // VLD4LNd16 + 0U, // VLD4LNd16Pseudo + 0U, // VLD4LNd16Pseudo_UPD + 1079367377U, // VLD4LNd16_UPD + 1079490257U, // VLD4LNd32 + 0U, // VLD4LNd32Pseudo + 0U, // VLD4LNd32Pseudo_UPD + 1079498449U, // VLD4LNd32_UPD + 1079621329U, // VLD4LNd8 + 0U, // VLD4LNd8Pseudo + 0U, // VLD4LNd8Pseudo_UPD + 1079629521U, // VLD4LNd8_UPD + 1079359185U, // VLD4LNq16 + 0U, // VLD4LNq16Pseudo + 0U, // VLD4LNq16Pseudo_UPD + 1079367377U, // VLD4LNq16_UPD + 1079490257U, // VLD4LNq32 + 0U, // VLD4LNq32Pseudo + 0U, // VLD4LNq32Pseudo_UPD + 1079498449U, // VLD4LNq32_UPD + 5560017U, // VLD4d16 + 0U, // VLD4d16Pseudo + 0U, // VLD4d16Pseudo_UPD + 5621457U, // VLD4d16_UPD + 5691089U, // VLD4d32 + 0U, // VLD4d32Pseudo + 0U, // VLD4d32Pseudo_UPD + 5752529U, // VLD4d32_UPD + 5822161U, // VLD4d8 + 0U, // VLD4d8Pseudo + 0U, // VLD4d8Pseudo_UPD + 5883601U, // VLD4d8_UPD + 5560017U, // VLD4q16 + 0U, // VLD4q16Pseudo_UPD + 5621457U, // VLD4q16_UPD + 0U, // VLD4q16oddPseudo + 0U, // VLD4q16oddPseudo_UPD + 5691089U, // VLD4q32 + 0U, // VLD4q32Pseudo_UPD + 5752529U, // VLD4q32_UPD + 0U, // VLD4q32oddPseudo + 0U, // VLD4q32oddPseudo_UPD + 5822161U, // VLD4q8 + 0U, // VLD4q8Pseudo_UPD + 5883601U, // VLD4q8_UPD + 0U, // VLD4q8oddPseudo + 0U, // VLD4q8oddPseudo_UPD + 2332571774U, // VLDMDDB_UPD + 571406U, // VLDMDIA + 2332571662U, // VLDMDIA_UPD + 0U, // VLDMQIA + 2332571774U, // VLDMSDB_UPD + 571406U, // VLDMSIA + 2332571662U, // VLDMSIA_UPD + 556114U, // VLDRD + 162898U, // VLDRH + 556114U, // VLDRS + 1074314122U, // VLLDM + 1074314128U, // VLSTM + 185246300U, // VMAXNMD + 185246693U, // VMAXNMH + 185245992U, // VMAXNMNDf + 185246693U, // VMAXNMNDh + 185245992U, // VMAXNMNQf + 185246693U, // VMAXNMNQh + 185245992U, // VMAXNMS + 253132314U, // VMAXfd + 253132314U, // VMAXfq + 253001242U, // VMAXhd + 253001242U, // VMAXhq + 186940954U, // VMAXsv16i8 + 186678810U, // VMAXsv2i32 + 186809882U, // VMAXsv4i16 + 186678810U, // VMAXsv4i32 + 186809882U, // VMAXsv8i16 + 186940954U, // VMAXsv8i8 + 187334170U, // VMAXuv16i8 + 187072026U, // VMAXuv2i32 + 187203098U, // VMAXuv4i16 + 187072026U, // VMAXuv4i32 + 187203098U, // VMAXuv8i16 + 187334170U, // VMAXuv8i8 + 185246288U, // VMINNMD + 185246681U, // VMINNMH + 185245980U, // VMINNMNDf + 185246681U, // VMINNMNDh + 185245980U, // VMINNMNQf + 185246681U, // VMINNMNQh + 185245980U, // VMINNMS + 253131706U, // VMINfd + 253131706U, // VMINfq + 253000634U, // VMINhd + 253000634U, // VMINhq + 186940346U, // VMINsv16i8 + 186678202U, // VMINsv2i32 + 186809274U, // VMINsv4i16 + 186678202U, // VMINsv4i32 + 186809274U, // VMINsv8i16 + 186940346U, // VMINsv8i8 + 187333562U, // VMINuv16i8 + 187071418U, // VMINuv2i32 + 187202490U, // VMINuv4i16 + 187071418U, // VMINuv4i32 + 187202490U, // VMINuv8i16 + 187333562U, // VMINuv8i8 + 2400344110U, // VMLAD + 2400475182U, // VMLAH + 169896676U, // VMLALslsv2i32 + 170027748U, // VMLALslsv4i16 + 170289892U, // VMLALsluv2i32 + 170420964U, // VMLALsluv4i16 + 169892580U, // VMLALsv2i64 + 170023652U, // VMLALsv4i32 + 170154724U, // VMLALsv8i16 + 170285796U, // VMLALuv2i64 + 170416868U, // VMLALuv4i32 + 170547940U, // VMLALuv8i16 + 2400606254U, // VMLAS + 2400606254U, // VMLAfd + 2400606254U, // VMLAfq + 2400475182U, // VMLAhd + 2400475182U, // VMLAhq + 2400610350U, // VMLAslfd + 2400610350U, // VMLAslfq + 2400479278U, // VMLAslhd + 2400479278U, // VMLAslhq + 170813486U, // VMLAslv2i32 + 170944558U, // VMLAslv4i16 + 170813486U, // VMLAslv4i32 + 170944558U, // VMLAslv8i16 + 171071534U, // VMLAv16i8 + 170809390U, // VMLAv2i32 + 170940462U, // VMLAv4i16 + 170809390U, // VMLAv4i32 + 170940462U, // VMLAv8i16 + 171071534U, // VMLAv8i8 + 2400345279U, // VMLSD + 2400476351U, // VMLSH + 169896809U, // VMLSLslsv2i32 + 170027881U, // VMLSLslsv4i16 + 170290025U, // VMLSLsluv2i32 + 170421097U, // VMLSLsluv4i16 + 169892713U, // VMLSLsv2i64 + 170023785U, // VMLSLsv4i32 + 170154857U, // VMLSLsv8i16 + 170285929U, // VMLSLuv2i64 + 170417001U, // VMLSLuv4i32 + 170548073U, // VMLSLuv8i16 + 2400607423U, // VMLSS + 2400607423U, // VMLSfd + 2400607423U, // VMLSfq + 2400476351U, // VMLShd + 2400476351U, // VMLShq + 2400611519U, // VMLSslfd + 2400611519U, // VMLSslfq + 2400480447U, // VMLSslhd + 2400480447U, // VMLSslhq + 170814655U, // VMLSslv2i32 + 170945727U, // VMLSslv4i16 + 170814655U, // VMLSslv4i32 + 170945727U, // VMLSslv8i16 + 171072703U, // VMLSv16i8 + 170810559U, // VMLSv2i32 + 170941631U, // VMLSv4i16 + 170810559U, // VMLSv4i32 + 170941631U, // VMLSv8i16 + 171072703U, // VMLSv8i8 + 252853737U, // VMOVD + 556521U, // VMOVDRR + 1258988623U, // VMOVH + 252984809U, // VMOVHR + 1260403588U, // VMOVLsv2i64 + 1260534660U, // VMOVLsv4i32 + 1260665732U, // VMOVLsv8i16 + 1260796804U, // VMOVLuv2i64 + 1260927876U, // VMOVLuv4i32 + 1261058948U, // VMOVLuv8i16 + 1261190158U, // VMOVNv2i32 + 1261321230U, // VMOVNv4i16 + 1261452302U, // VMOVNv8i8 + 252984809U, // VMOVRH + 556521U, // VMOVRRD + 548329U, // VMOVRRS + 540137U, // VMOVRS + 253115881U, // VMOVS + 540137U, // VMOVSR + 548329U, // VMOVSRR + 405945833U, // VMOVv16i8 + 405552617U, // VMOVv1i64 + 1326857705U, // VMOVv2f32 + 405683689U, // VMOVv2i32 + 405552617U, // VMOVv2i64 + 1326857705U, // VMOVv4f32 + 405814761U, // VMOVv4i16 + 405683689U, // VMOVv4i32 + 405814761U, // VMOVv8i16 + 405945833U, // VMOVv8i8 + 3221798113U, // VMRS + 572641U, // VMRS_FPEXC + 1074314465U, // VMRS_FPINST + 2148056289U, // VMRS_FPINST2 + 3221798113U, // VMRS_FPSID + 572641U, // VMRS_MVFR0 + 1074314465U, // VMRS_MVFR1 + 2148056289U, // VMRS_MVFR2 + 5946503U, // VMSR + 6077575U, // VMSR_FPEXC + 6208647U, // VMSR_FPINST + 6339719U, // VMSR_FPINST2 + 6470791U, // VMSR_FPSID + 252869503U, // VMULD + 253000575U, // VMULH + 185246384U, // VMULLp64 + 6585174U, // VMULLp8 + 186669910U, // VMULLslsv2i32 + 186800982U, // VMULLslsv4i16 + 187063126U, // VMULLsluv2i32 + 187194198U, // VMULLsluv4i16 + 186678102U, // VMULLsv2i64 + 186809174U, // VMULLsv4i32 + 186940246U, // VMULLsv8i16 + 187071318U, // VMULLuv2i64 + 187202390U, // VMULLuv4i32 + 187333462U, // VMULLuv8i16 + 253131647U, // VMULS + 253131647U, // VMULfd + 253131647U, // VMULfq + 253000575U, // VMULhd + 253000575U, // VMULhq + 6585215U, // VMULpd + 6585215U, // VMULpq + 253123455U, // VMULslfd + 253123455U, // VMULslfq + 252992383U, // VMULslhd + 252992383U, // VMULslhq + 187587455U, // VMULslv2i32 + 187718527U, // VMULslv4i16 + 187587455U, // VMULslv4i32 + 187718527U, // VMULslv8i16 + 187857791U, // VMULv16i8 + 187595647U, // VMULv2i32 + 187726719U, // VMULv4i16 + 187595647U, // VMULv4i32 + 187726719U, // VMULv8i16 + 187857791U, // VMULv8i8 + 539650U, // VMVNd + 539650U, // VMVNq + 405683202U, // VMVNv2i32 + 405814274U, // VMVNv4i16 + 405683202U, // VMVNv4i32 + 405814274U, // VMVNv8i16 + 252852757U, // VNEGD + 252983829U, // VNEGH + 253114901U, // VNEGS + 253114901U, // VNEGf32q + 253114901U, // VNEGfd + 252983829U, // VNEGhd + 252983829U, // VNEGhq + 1260534293U, // VNEGs16d + 1260534293U, // VNEGs16q + 1260403221U, // VNEGs32d + 1260403221U, // VNEGs32q + 1260665365U, // VNEGs8d + 1260665365U, // VNEGs8q + 2400344104U, // VNMLAD + 2400475176U, // VNMLAH + 2400606248U, // VNMLAS + 2400345273U, // VNMLSD + 2400476345U, // VNMLSH + 2400607417U, // VNMLSS + 252869497U, // VNMULD + 253000569U, // VNMULH + 253131641U, // VNMULS + 555999U, // VORNd + 555999U, // VORNq + 556151U, // VORRd + 405699703U, // VORRiv2i32 + 405830775U, // VORRiv4i16 + 405699703U, // VORRiv4i32 + 405830775U, // VORRiv8i16 + 556151U, // VORRq + 1243904713U, // VPADALsv16i8 + 1243642569U, // VPADALsv2i32 + 1243773641U, // VPADALsv4i16 + 1243642569U, // VPADALsv4i32 + 1243773641U, // VPADALsv8i16 + 1243904713U, // VPADALsv8i8 + 1244297929U, // VPADALuv16i8 + 1244035785U, // VPADALuv2i32 + 1244166857U, // VPADALuv4i16 + 1244035785U, // VPADALuv4i32 + 1244166857U, // VPADALuv8i16 + 1244297929U, // VPADALuv8i8 + 1260665605U, // VPADDLsv16i8 + 1260403461U, // VPADDLsv2i32 + 1260534533U, // VPADDLsv4i16 + 1260403461U, // VPADDLsv4i32 + 1260534533U, // VPADDLsv8i16 + 1260665605U, // VPADDLsv8i8 + 1261058821U, // VPADDLuv16i8 + 1260796677U, // VPADDLuv2i32 + 1260927749U, // VPADDLuv4i16 + 1260796677U, // VPADDLuv4i32 + 1260927749U, // VPADDLuv8i16 + 1261058821U, // VPADDLuv8i8 + 253131143U, // VPADDf + 253000071U, // VPADDh + 187726215U, // VPADDi16 + 187595143U, // VPADDi32 + 187857287U, // VPADDi8 + 253132308U, // VPMAXf + 253001236U, // VPMAXh + 186809876U, // VPMAXs16 + 186678804U, // VPMAXs32 + 186940948U, // VPMAXs8 + 187203092U, // VPMAXu16 + 187072020U, // VPMAXu32 + 187334164U, // VPMAXu8 + 253131700U, // VPMINf + 253000628U, // VPMINh + 186809268U, // VPMINs16 + 186678196U, // VPMINs32 + 186940340U, // VPMINs8 + 187202484U, // VPMINu16 + 187071412U, // VPMINu32 + 187333556U, // VPMINu8 + 1260666014U, // VQABSv16i8 + 1260403870U, // VQABSv2i32 + 1260534942U, // VQABSv4i16 + 1260403870U, // VQABSv4i32 + 1260534942U, // VQABSv8i16 + 1260666014U, // VQABSv8i8 + 186939789U, // VQADDsv16i8 + 191265165U, // VQADDsv1i64 + 186677645U, // VQADDsv2i32 + 191265165U, // VQADDsv2i64 + 186808717U, // VQADDsv4i16 + 186677645U, // VQADDsv4i32 + 186808717U, // VQADDsv8i16 + 186939789U, // VQADDsv8i8 + 187333005U, // VQADDuv16i8 + 191396237U, // VQADDuv1i64 + 187070861U, // VQADDuv2i32 + 191396237U, // VQADDuv2i64 + 187201933U, // VQADDuv4i16 + 187070861U, // VQADDuv4i32 + 187201933U, // VQADDuv8i16 + 187333005U, // VQADDuv8i8 + 169896656U, // VQDMLALslv2i32 + 170027728U, // VQDMLALslv4i16 + 169892560U, // VQDMLALv2i64 + 170023632U, // VQDMLALv4i32 + 169896801U, // VQDMLSLslv2i32 + 170027873U, // VQDMLSLslv4i16 + 169892705U, // VQDMLSLv2i64 + 170023777U, // VQDMLSLv4i32 + 186669632U, // VQDMULHslv2i32 + 186800704U, // VQDMULHslv4i16 + 186669632U, // VQDMULHslv4i32 + 186800704U, // VQDMULHslv8i16 + 186677824U, // VQDMULHv2i32 + 186808896U, // VQDMULHv4i16 + 186677824U, // VQDMULHv4i32 + 186808896U, // VQDMULHv8i16 + 186669890U, // VQDMULLslv2i32 + 186800962U, // VQDMULLslv4i16 + 186678082U, // VQDMULLv2i64 + 186809154U, // VQDMULLv4i32 + 1264991226U, // VQMOVNsuv2i32 + 1260403706U, // VQMOVNsuv4i16 + 1260534778U, // VQMOVNsuv8i8 + 1264991239U, // VQMOVNsv2i32 + 1260403719U, // VQMOVNsv4i16 + 1260534791U, // VQMOVNsv8i8 + 1265122311U, // VQMOVNuv2i32 + 1260796935U, // VQMOVNuv4i16 + 1260928007U, // VQMOVNuv8i8 + 1260665359U, // VQNEGv16i8 + 1260403215U, // VQNEGv2i32 + 1260534287U, // VQNEGv4i16 + 1260403215U, // VQNEGv4i32 + 1260534287U, // VQNEGv8i16 + 1260665359U, // VQNEGv8i8 + 169896482U, // VQRDMLAHslv2i32 + 170027554U, // VQRDMLAHslv4i16 + 169896482U, // VQRDMLAHslv4i32 + 170027554U, // VQRDMLAHslv8i16 + 169892386U, // VQRDMLAHv2i32 + 170023458U, // VQRDMLAHv4i16 + 169892386U, // VQRDMLAHv4i32 + 170023458U, // VQRDMLAHv8i16 + 169896539U, // VQRDMLSHslv2i32 + 170027611U, // VQRDMLSHslv4i16 + 169896539U, // VQRDMLSHslv4i32 + 170027611U, // VQRDMLSHslv8i16 + 169892443U, // VQRDMLSHv2i32 + 170023515U, // VQRDMLSHv4i16 + 169892443U, // VQRDMLSHv4i32 + 170023515U, // VQRDMLSHv8i16 + 186669640U, // VQRDMULHslv2i32 + 186800712U, // VQRDMULHslv4i16 + 186669640U, // VQRDMULHslv4i32 + 186800712U, // VQRDMULHslv8i16 + 186677832U, // VQRDMULHv2i32 + 186808904U, // VQRDMULHv4i16 + 186677832U, // VQRDMULHv4i32 + 186808904U, // VQRDMULHv8i16 + 186940188U, // VQRSHLsv16i8 + 191265564U, // VQRSHLsv1i64 + 186678044U, // VQRSHLsv2i32 + 191265564U, // VQRSHLsv2i64 + 186809116U, // VQRSHLsv4i16 + 186678044U, // VQRSHLsv4i32 + 186809116U, // VQRSHLsv8i16 + 186940188U, // VQRSHLsv8i8 + 187333404U, // VQRSHLuv16i8 + 191396636U, // VQRSHLuv1i64 + 187071260U, // VQRSHLuv2i32 + 191396636U, // VQRSHLuv2i64 + 187202332U, // VQRSHLuv4i16 + 187071260U, // VQRSHLuv4i32 + 187202332U, // VQRSHLuv8i16 + 187333404U, // VQRSHLuv8i8 + 191265738U, // VQRSHRNsv2i32 + 186678218U, // VQRSHRNsv4i16 + 186809290U, // VQRSHRNsv8i8 + 191396810U, // VQRSHRNuv2i32 + 187071434U, // VQRSHRNuv4i16 + 187202506U, // VQRSHRNuv8i8 + 191265777U, // VQRSHRUNv2i32 + 186678257U, // VQRSHRUNv4i16 + 186809329U, // VQRSHRUNv8i8 + 186940182U, // VQSHLsiv16i8 + 191265558U, // VQSHLsiv1i64 + 186678038U, // VQSHLsiv2i32 + 191265558U, // VQSHLsiv2i64 + 186809110U, // VQSHLsiv4i16 + 186678038U, // VQSHLsiv4i32 + 186809110U, // VQSHLsiv8i16 + 186940182U, // VQSHLsiv8i8 + 186940879U, // VQSHLsuv16i8 + 191266255U, // VQSHLsuv1i64 + 186678735U, // VQSHLsuv2i32 + 191266255U, // VQSHLsuv2i64 + 186809807U, // VQSHLsuv4i16 + 186678735U, // VQSHLsuv4i32 + 186809807U, // VQSHLsuv8i16 + 186940879U, // VQSHLsuv8i8 + 186940182U, // VQSHLsv16i8 + 191265558U, // VQSHLsv1i64 + 186678038U, // VQSHLsv2i32 + 191265558U, // VQSHLsv2i64 + 186809110U, // VQSHLsv4i16 + 186678038U, // VQSHLsv4i32 + 186809110U, // VQSHLsv8i16 + 186940182U, // VQSHLsv8i8 + 187333398U, // VQSHLuiv16i8 + 191396630U, // VQSHLuiv1i64 + 187071254U, // VQSHLuiv2i32 + 191396630U, // VQSHLuiv2i64 + 187202326U, // VQSHLuiv4i16 + 187071254U, // VQSHLuiv4i32 + 187202326U, // VQSHLuiv8i16 + 187333398U, // VQSHLuiv8i8 + 187333398U, // VQSHLuv16i8 + 191396630U, // VQSHLuv1i64 + 187071254U, // VQSHLuv2i32 + 191396630U, // VQSHLuv2i64 + 187202326U, // VQSHLuv4i16 + 187071254U, // VQSHLuv4i32 + 187202326U, // VQSHLuv8i16 + 187333398U, // VQSHLuv8i8 + 191265731U, // VQSHRNsv2i32 + 186678211U, // VQSHRNsv4i16 + 186809283U, // VQSHRNsv8i8 + 191396803U, // VQSHRNuv2i32 + 187071427U, // VQSHRNuv4i16 + 187202499U, // VQSHRNuv8i8 + 191265769U, // VQSHRUNv2i32 + 186678249U, // VQSHRUNv4i16 + 186809321U, // VQSHRUNv8i8 + 186939648U, // VQSUBsv16i8 + 191265024U, // VQSUBsv1i64 + 186677504U, // VQSUBsv2i32 + 191265024U, // VQSUBsv2i64 + 186808576U, // VQSUBsv4i16 + 186677504U, // VQSUBsv4i32 + 186808576U, // VQSUBsv8i16 + 186939648U, // VQSUBsv8i8 + 187332864U, // VQSUBuv16i8 + 191396096U, // VQSUBuv1i64 + 187070720U, // VQSUBuv2i32 + 191396096U, // VQSUBuv2i64 + 187201792U, // VQSUBuv4i16 + 187070720U, // VQSUBuv4i32 + 187201792U, // VQSUBuv8i16 + 187332864U, // VQSUBuv8i8 + 187464613U, // VRADDHNv2i32 + 187595685U, // VRADDHNv4i16 + 187726757U, // VRADDHNv8i8 + 1260796401U, // VRECPEd + 253114865U, // VRECPEfd + 253114865U, // VRECPEfq + 252983793U, // VRECPEhd + 252983793U, // VRECPEhq + 1260796401U, // VRECPEq + 253131994U, // VRECPSfd + 253131994U, // VRECPSfq + 253000922U, // VRECPShd + 253000922U, // VRECPShq + 407379U, // VREV16d8 + 407379U, // VREV16q8 + 145022U, // VREV32d16 + 407166U, // VREV32d8 + 145022U, // VREV32q16 + 407166U, // VREV32q8 + 145098U, // VREV64d16 + 276170U, // VREV64d32 + 407242U, // VREV64d8 + 145098U, // VREV64q16 + 276170U, // VREV64q32 + 407242U, // VREV64q8 + 186939770U, // VRHADDsv16i8 + 186677626U, // VRHADDsv2i32 + 186808698U, // VRHADDsv4i16 + 186677626U, // VRHADDsv4i32 + 186808698U, // VRHADDsv8i16 + 186939770U, // VRHADDsv8i8 + 187332986U, // VRHADDuv16i8 + 187070842U, // VRHADDuv2i32 + 187201914U, // VRHADDuv4i16 + 187070842U, // VRHADDuv4i32 + 187201914U, // VRHADDuv8i16 + 187332986U, // VRHADDuv8i8 + 1258988088U, // VRINTAD + 1258988470U, // VRINTAH + 1258987769U, // VRINTANDf + 1258988470U, // VRINTANDh + 1258987769U, // VRINTANQf + 1258988470U, // VRINTANQh + 1258987769U, // VRINTAS + 1258988136U, // VRINTMD + 1258988529U, // VRINTMH + 1258987828U, // VRINTMNDf + 1258988529U, // VRINTMNDh + 1258987828U, // VRINTMNQf + 1258988529U, // VRINTMNQh + 1258987828U, // VRINTMS + 1258988148U, // VRINTND + 1258988541U, // VRINTNH + 1258987840U, // VRINTNNDf + 1258988541U, // VRINTNNDh + 1258987840U, // VRINTNNQf + 1258988541U, // VRINTNNQh + 1258987840U, // VRINTNS + 1258988160U, // VRINTPD + 1258988553U, // VRINTPH + 1258987852U, // VRINTPNDf + 1258988553U, // VRINTPNDh + 1258987852U, // VRINTPNQf + 1258988553U, // VRINTPNQh + 1258987852U, // VRINTPS + 252853388U, // VRINTRD + 252984460U, // VRINTRH + 253115532U, // VRINTRS + 252853960U, // VRINTXD + 252985032U, // VRINTXH + 1258987900U, // VRINTXNDf + 1258988611U, // VRINTXNDh + 1258987900U, // VRINTXNQf + 1258988611U, // VRINTXNQh + 253116104U, // VRINTXS + 252853972U, // VRINTZD + 252985044U, // VRINTZH + 1258987912U, // VRINTZNDf + 1258988634U, // VRINTZNDh + 1258987912U, // VRINTZNQf + 1258988634U, // VRINTZNQh + 253116116U, // VRINTZS + 186940195U, // VRSHLsv16i8 + 191265571U, // VRSHLsv1i64 + 186678051U, // VRSHLsv2i32 + 191265571U, // VRSHLsv2i64 + 186809123U, // VRSHLsv4i16 + 186678051U, // VRSHLsv4i32 + 186809123U, // VRSHLsv8i16 + 186940195U, // VRSHLsv8i8 + 187333411U, // VRSHLuv16i8 + 191396643U, // VRSHLuv1i64 + 187071267U, // VRSHLuv2i32 + 191396643U, // VRSHLuv2i64 + 187202339U, // VRSHLuv4i16 + 187071267U, // VRSHLuv4i32 + 187202339U, // VRSHLuv8i16 + 187333411U, // VRSHLuv8i8 + 187464658U, // VRSHRNv2i32 + 187595730U, // VRSHRNv4i16 + 187726802U, // VRSHRNv8i8 + 186940503U, // VRSHRsv16i8 + 191265879U, // VRSHRsv1i64 + 186678359U, // VRSHRsv2i32 + 191265879U, // VRSHRsv2i64 + 186809431U, // VRSHRsv4i16 + 186678359U, // VRSHRsv4i32 + 186809431U, // VRSHRsv8i16 + 186940503U, // VRSHRsv8i8 + 187333719U, // VRSHRuv16i8 + 191396951U, // VRSHRuv1i64 + 187071575U, // VRSHRuv2i32 + 191396951U, // VRSHRuv2i64 + 187202647U, // VRSHRuv4i16 + 187071575U, // VRSHRuv4i32 + 187202647U, // VRSHRuv8i16 + 187333719U, // VRSHRuv8i8 + 1260796414U, // VRSQRTEd + 253114878U, // VRSQRTEfd + 253114878U, // VRSQRTEfq + 252983806U, // VRSQRTEhd + 252983806U, // VRSQRTEhq + 1260796414U, // VRSQRTEq + 253132016U, // VRSQRTSfd + 253132016U, // VRSQRTSfq + 253000944U, // VRSQRTShd + 253000944U, // VRSQRTShq + 170154046U, // VRSRAsv16i8 + 174479422U, // VRSRAsv1i64 + 169891902U, // VRSRAsv2i32 + 174479422U, // VRSRAsv2i64 + 170022974U, // VRSRAsv4i16 + 169891902U, // VRSRAsv4i32 + 170022974U, // VRSRAsv8i16 + 170154046U, // VRSRAsv8i8 + 170547262U, // VRSRAuv16i8 + 174610494U, // VRSRAuv1i64 + 170285118U, // VRSRAuv2i32 + 174610494U, // VRSRAuv2i64 + 170416190U, // VRSRAuv4i16 + 170285118U, // VRSRAuv4i32 + 170416190U, // VRSRAuv8i16 + 170547262U, // VRSRAuv8i8 + 187464598U, // VRSUBHNv2i32 + 187595670U, // VRSUBHNv4i16 + 187726742U, // VRSUBHNv8i8 + 910473U, // VSDOTD + 7070857U, // VSDOTDI + 910473U, // VSDOTQ + 7070857U, // VSDOTQI + 185246348U, // VSELEQD + 185246741U, // VSELEQH + 185246040U, // VSELEQS + 185246276U, // VSELGED + 185246669U, // VSELGEH + 185245968U, // VSELGES + 185246372U, // VSELGTD + 185246775U, // VSELGTH + 185246064U, // VSELGTS + 185246360U, // VSELVSD + 185246763U, // VSELVSH + 185246052U, // VSELVSS + 3221380585U, // VSETLNi16 + 3221511657U, // VSETLNi32 + 3221642729U, // VSETLNi8 + 187726652U, // VSHLLi16 + 187595580U, // VSHLLi32 + 187857724U, // VSHLLi8 + 186678076U, // VSHLLsv2i64 + 186809148U, // VSHLLsv4i32 + 186940220U, // VSHLLsv8i16 + 187071292U, // VSHLLuv2i64 + 187202364U, // VSHLLuv4i32 + 187333436U, // VSHLLuv8i16 + 187857705U, // VSHLiv16i8 + 187464489U, // VSHLiv1i64 + 187595561U, // VSHLiv2i32 + 187464489U, // VSHLiv2i64 + 187726633U, // VSHLiv4i16 + 187595561U, // VSHLiv4i32 + 187726633U, // VSHLiv8i16 + 187857705U, // VSHLiv8i8 + 186940201U, // VSHLsv16i8 + 191265577U, // VSHLsv1i64 + 186678057U, // VSHLsv2i32 + 191265577U, // VSHLsv2i64 + 186809129U, // VSHLsv4i16 + 186678057U, // VSHLsv4i32 + 186809129U, // VSHLsv8i16 + 186940201U, // VSHLsv8i8 + 187333417U, // VSHLuv16i8 + 191396649U, // VSHLuv1i64 + 187071273U, // VSHLuv2i32 + 191396649U, // VSHLuv2i64 + 187202345U, // VSHLuv4i16 + 187071273U, // VSHLuv4i32 + 187202345U, // VSHLuv8i16 + 187333417U, // VSHLuv8i8 + 187464665U, // VSHRNv2i32 + 187595737U, // VSHRNv4i16 + 187726809U, // VSHRNv8i8 + 186940509U, // VSHRsv16i8 + 191265885U, // VSHRsv1i64 + 186678365U, // VSHRsv2i32 + 191265885U, // VSHRsv2i64 + 186809437U, // VSHRsv4i16 + 186678365U, // VSHRsv4i32 + 186809437U, // VSHRsv8i16 + 186940509U, // VSHRsv8i8 + 187333725U, // VSHRuv16i8 + 191396957U, // VSHRuv1i64 + 187071581U, // VSHRuv2i32 + 191396957U, // VSHRuv2i64 + 187202653U, // VSHRuv4i16 + 187071581U, // VSHRuv4i32 + 187202653U, // VSHRuv8i16 + 187333725U, // VSHRuv8i8 + 7110066U, // VSHTOD + 256540082U, // VSHTOH + 7241138U, // VSHTOS + 443563442U, // VSITOD + 443694514U, // VSITOH + 440942002U, // VSITOS + 416419U, // VSLIv16i8 + 5266083U, // VSLIv1i64 + 285347U, // VSLIv2i32 + 5266083U, // VSLIv2i64 + 154275U, // VSLIv4i16 + 285347U, // VSLIv4i32 + 154275U, // VSLIv8i16 + 416419U, // VSLIv8i8 + 1332772274U, // VSLTOD + 1332903346U, // VSLTOH + 1330150834U, // VSLTOS + 252853628U, // VSQRTD + 252984700U, // VSQRTH + 253115772U, // VSQRTS + 170154052U, // VSRAsv16i8 + 174479428U, // VSRAsv1i64 + 169891908U, // VSRAsv2i32 + 174479428U, // VSRAsv2i64 + 170022980U, // VSRAsv4i16 + 169891908U, // VSRAsv4i32 + 170022980U, // VSRAsv8i16 + 170154052U, // VSRAsv8i8 + 170547268U, // VSRAuv16i8 + 174610500U, // VSRAuv1i64 + 170285124U, // VSRAuv2i32 + 174610500U, // VSRAuv2i64 + 170416196U, // VSRAuv4i16 + 170285124U, // VSRAuv4i32 + 170416196U, // VSRAuv8i16 + 170547268U, // VSRAuv8i8 + 416424U, // VSRIv16i8 + 5266088U, // VSRIv1i64 + 285352U, // VSRIv2i32 + 5266088U, // VSRIv2i64 + 154280U, // VSRIv4i16 + 285352U, // VSRIv4i32 + 154280U, // VSRIv8i16 + 416424U, // VSRIv8i8 + 1247041145U, // VST1LNd16 + 1632949881U, // VST1LNd16_UPD + 1247172217U, // VST1LNd32 + 1633080953U, // VST1LNd32_UPD + 1247303289U, // VST1LNd8 + 1633212025U, // VST1LNd8_UPD + 0U, // VST1LNq16Pseudo + 0U, // VST1LNq16Pseudo_UPD + 0U, // VST1LNq32Pseudo + 0U, // VST1LNq32Pseudo_UPD + 0U, // VST1LNq8Pseudo + 0U, // VST1LNq8Pseudo_UPD + 570586745U, // VST1d16 + 587363961U, // VST1d16Q + 0U, // VST1d16QPseudo + 604132985U, // VST1d16Qwb_fixed + 620914297U, // VST1d16Qwb_register + 637695609U, // VST1d16T + 0U, // VST1d16TPseudo + 654464633U, // VST1d16Twb_fixed + 671245945U, // VST1d16Twb_register + 688019065U, // VST1d16wb_fixed + 704800377U, // VST1d16wb_register + 570717817U, // VST1d32 + 587495033U, // VST1d32Q + 0U, // VST1d32QPseudo + 604264057U, // VST1d32Qwb_fixed + 621045369U, // VST1d32Qwb_register + 637826681U, // VST1d32T + 0U, // VST1d32TPseudo + 654595705U, // VST1d32Twb_fixed + 671377017U, // VST1d32Twb_register + 688150137U, // VST1d32wb_fixed + 704931449U, // VST1d32wb_register + 575698553U, // VST1d64 + 592475769U, // VST1d64Q + 0U, // VST1d64QPseudo + 0U, // VST1d64QPseudoWB_fixed + 0U, // VST1d64QPseudoWB_register + 609244793U, // VST1d64Qwb_fixed + 626026105U, // VST1d64Qwb_register + 642807417U, // VST1d64T + 0U, // VST1d64TPseudo + 0U, // VST1d64TPseudoWB_fixed + 0U, // VST1d64TPseudoWB_register + 659576441U, // VST1d64Twb_fixed + 676357753U, // VST1d64Twb_register + 693130873U, // VST1d64wb_fixed + 709912185U, // VST1d64wb_register + 570848889U, // VST1d8 + 587626105U, // VST1d8Q + 0U, // VST1d8QPseudo + 604395129U, // VST1d8Qwb_fixed + 621176441U, // VST1d8Qwb_register + 637957753U, // VST1d8T + 0U, // VST1d8TPseudo + 654726777U, // VST1d8Twb_fixed + 671508089U, // VST1d8Twb_register + 688281209U, // VST1d8wb_fixed + 705062521U, // VST1d8wb_register + 721581689U, // VST1q16 + 0U, // VST1q16HighQPseudo + 0U, // VST1q16HighTPseudo + 0U, // VST1q16LowQPseudo_UPD + 0U, // VST1q16LowTPseudo_UPD + 738350713U, // VST1q16wb_fixed + 755132025U, // VST1q16wb_register + 721712761U, // VST1q32 + 0U, // VST1q32HighQPseudo + 0U, // VST1q32HighTPseudo + 0U, // VST1q32LowQPseudo_UPD + 0U, // VST1q32LowTPseudo_UPD + 738481785U, // VST1q32wb_fixed + 755263097U, // VST1q32wb_register + 726693497U, // VST1q64 + 0U, // VST1q64HighQPseudo + 0U, // VST1q64HighTPseudo + 0U, // VST1q64LowQPseudo_UPD + 0U, // VST1q64LowTPseudo_UPD + 743462521U, // VST1q64wb_fixed + 760243833U, // VST1q64wb_register + 721843833U, // VST1q8 + 0U, // VST1q8HighQPseudo + 0U, // VST1q8HighTPseudo + 0U, // VST1q8LowQPseudo_UPD + 0U, // VST1q8LowTPseudo_UPD + 738612857U, // VST1q8wb_fixed + 755394169U, // VST1q8wb_register + 1247045301U, // VST2LNd16 + 0U, // VST2LNd16Pseudo + 0U, // VST2LNd16Pseudo_UPD + 1632999093U, // VST2LNd16_UPD + 1247176373U, // VST2LNd32 + 0U, // VST2LNd32Pseudo + 0U, // VST2LNd32Pseudo_UPD + 1633130165U, // VST2LNd32_UPD + 1247307445U, // VST2LNd8 + 0U, // VST2LNd8Pseudo + 0U, // VST2LNd8Pseudo_UPD + 1633261237U, // VST2LNd8_UPD + 1247045301U, // VST2LNq16 + 0U, // VST2LNq16Pseudo + 0U, // VST2LNq16Pseudo_UPD + 1632999093U, // VST2LNq16_UPD + 1247176373U, // VST2LNq32 + 0U, // VST2LNq32Pseudo + 0U, // VST2LNq32Pseudo_UPD + 1633130165U, // VST2LNq32_UPD + 771913397U, // VST2b16 + 788682421U, // VST2b16wb_fixed + 805463733U, // VST2b16wb_register + 772044469U, // VST2b32 + 788813493U, // VST2b32wb_fixed + 805594805U, // VST2b32wb_register + 772175541U, // VST2b8 + 788944565U, // VST2b8wb_fixed + 805725877U, // VST2b8wb_register + 721581749U, // VST2d16 + 738350773U, // VST2d16wb_fixed + 755132085U, // VST2d16wb_register + 721712821U, // VST2d32 + 738481845U, // VST2d32wb_fixed + 755263157U, // VST2d32wb_register + 721843893U, // VST2d8 + 738612917U, // VST2d8wb_fixed + 755394229U, // VST2d8wb_register + 587364021U, // VST2q16 + 0U, // VST2q16Pseudo + 0U, // VST2q16PseudoWB_fixed + 0U, // VST2q16PseudoWB_register + 604133045U, // VST2q16wb_fixed + 620914357U, // VST2q16wb_register + 587495093U, // VST2q32 + 0U, // VST2q32Pseudo + 0U, // VST2q32PseudoWB_fixed + 0U, // VST2q32PseudoWB_register + 604264117U, // VST2q32wb_fixed + 621045429U, // VST2q32wb_register + 587626165U, // VST2q8 + 0U, // VST2q8Pseudo + 0U, // VST2q8PseudoWB_fixed + 0U, // VST2q8PseudoWB_register + 604395189U, // VST2q8wb_fixed + 621176501U, // VST2q8wb_register + 1247073989U, // VST3LNd16 + 0U, // VST3LNd16Pseudo + 0U, // VST3LNd16Pseudo_UPD + 1633011397U, // VST3LNd16_UPD + 1247205061U, // VST3LNd32 + 0U, // VST3LNd32Pseudo + 0U, // VST3LNd32Pseudo_UPD + 1633142469U, // VST3LNd32_UPD + 1247336133U, // VST3LNd8 + 0U, // VST3LNd8Pseudo + 0U, // VST3LNd8Pseudo_UPD + 1633273541U, // VST3LNd8_UPD + 1247073989U, // VST3LNq16 + 0U, // VST3LNq16Pseudo + 0U, // VST3LNq16Pseudo_UPD + 1633011397U, // VST3LNq16_UPD + 1247205061U, // VST3LNq32 + 0U, // VST3LNq32Pseudo + 0U, // VST3LNq32Pseudo_UPD + 1633142469U, // VST3LNq32_UPD + 173303493U, // VST3d16 + 0U, // VST3d16Pseudo + 0U, // VST3d16Pseudo_UPD + 559257285U, // VST3d16_UPD + 173434565U, // VST3d32 + 0U, // VST3d32Pseudo + 0U, // VST3d32Pseudo_UPD + 559388357U, // VST3d32_UPD + 173565637U, // VST3d8 + 0U, // VST3d8Pseudo + 0U, // VST3d8Pseudo_UPD + 559519429U, // VST3d8_UPD + 173303493U, // VST3q16 + 0U, // VST3q16Pseudo_UPD + 559257285U, // VST3q16_UPD + 0U, // VST3q16oddPseudo + 0U, // VST3q16oddPseudo_UPD + 173434565U, // VST3q32 + 0U, // VST3q32Pseudo_UPD + 559388357U, // VST3q32_UPD + 0U, // VST3q32oddPseudo + 0U, // VST3q32oddPseudo_UPD + 173565637U, // VST3q8 + 0U, // VST3q8Pseudo_UPD + 559519429U, // VST3q8_UPD + 0U, // VST3q8oddPseudo + 0U, // VST3q8oddPseudo_UPD + 1247123158U, // VST4LNd16 + 0U, // VST4LNd16Pseudo + 0U, // VST4LNd16Pseudo_UPD + 1633003222U, // VST4LNd16_UPD + 1247254230U, // VST4LNd32 + 0U, // VST4LNd32Pseudo + 0U, // VST4LNd32Pseudo_UPD + 1633134294U, // VST4LNd32_UPD + 1247385302U, // VST4LNd8 + 0U, // VST4LNd8Pseudo + 0U, // VST4LNd8Pseudo_UPD + 1633265366U, // VST4LNd8_UPD + 1247123158U, // VST4LNq16 + 0U, // VST4LNq16Pseudo + 0U, // VST4LNq16Pseudo_UPD + 1633003222U, // VST4LNq16_UPD + 1247254230U, // VST4LNq32 + 0U, // VST4LNq32Pseudo + 0U, // VST4LNq32Pseudo_UPD + 1633134294U, // VST4LNq32_UPD + 173332182U, // VST4d16 + 0U, // VST4d16Pseudo + 0U, // VST4d16Pseudo_UPD + 559269590U, // VST4d16_UPD + 173463254U, // VST4d32 + 0U, // VST4d32Pseudo + 0U, // VST4d32Pseudo_UPD + 559400662U, // VST4d32_UPD + 173594326U, // VST4d8 + 0U, // VST4d8Pseudo + 0U, // VST4d8Pseudo_UPD + 559531734U, // VST4d8_UPD + 173332182U, // VST4q16 + 0U, // VST4q16Pseudo_UPD + 559269590U, // VST4q16_UPD + 0U, // VST4q16oddPseudo + 0U, // VST4q16oddPseudo_UPD + 173463254U, // VST4q32 + 0U, // VST4q32Pseudo_UPD + 559400662U, // VST4q32_UPD + 0U, // VST4q32oddPseudo + 0U, // VST4q32oddPseudo_UPD + 173594326U, // VST4q8 + 0U, // VST4q8Pseudo_UPD + 559531734U, // VST4q8_UPD + 0U, // VST4q8oddPseudo + 0U, // VST4q8oddPseudo_UPD + 2332571781U, // VSTMDDB_UPD + 571413U, // VSTMDIA + 2332571669U, // VSTMDIA_UPD + 0U, // VSTMQIA + 2332571781U, // VSTMSDB_UPD + 571413U, // VSTMSIA + 2332571669U, // VSTMSIA_UPD + 556179U, // VSTRD + 162963U, // VSTRH + 556179U, // VSTRS + 252868870U, // VSUBD + 252999942U, // VSUBH + 187464606U, // VSUBHNv2i32 + 187595678U, // VSUBHNv4i16 + 187726750U, // VSUBHNv8i8 + 186677999U, // VSUBLsv2i64 + 186809071U, // VSUBLsv4i32 + 186940143U, // VSUBLsv8i16 + 187071215U, // VSUBLuv2i64 + 187202287U, // VSUBLuv4i32 + 187333359U, // VSUBLuv8i16 + 253131014U, // VSUBS + 186678766U, // VSUBWsv2i64 + 186809838U, // VSUBWsv4i32 + 186940910U, // VSUBWsv8i16 + 187071982U, // VSUBWuv2i64 + 187203054U, // VSUBWuv4i32 + 187334126U, // VSUBWuv8i16 + 253131014U, // VSUBfd + 253131014U, // VSUBfq + 252999942U, // VSUBhd + 252999942U, // VSUBhq + 187857158U, // VSUBv16i8 + 187463942U, // VSUBv1i64 + 187595014U, // VSUBv2i32 + 187463942U, // VSUBv2i64 + 187726086U, // VSUBv4i16 + 187595014U, // VSUBv4i32 + 187726086U, // VSUBv8i16 + 187857158U, // VSUBv8i8 + 547888U, // VSWPd + 547888U, // VSWPq + 424682U, // VTBL1 + 424682U, // VTBL2 + 424682U, // VTBL3 + 0U, // VTBL3Pseudo + 424682U, // VTBL4 + 0U, // VTBL4Pseudo + 417355U, // VTBX1 + 417355U, // VTBX2 + 417355U, // VTBX3 + 0U, // VTBX3Pseudo + 417355U, // VTBX4 + 0U, // VTBX4Pseudo + 7634354U, // VTOSHD + 256146866U, // VTOSHH + 7765426U, // VTOSHS + 441597080U, // VTOSIRD + 444087448U, // VTOSIRH + 440417432U, // VTOSIRS + 441597362U, // VTOSIZD + 444087730U, // VTOSIZH + 440417714U, // VTOSIZS + 1330806194U, // VTOSLD + 1333296562U, // VTOSLH + 1329626546U, // VTOSLS + 8027570U, // VTOUHD + 256277938U, // VTOUHH + 8158642U, // VTOUHS + 444480664U, // VTOUIRD + 444611736U, // VTOUIRH + 440548504U, // VTOUIRS + 444480946U, // VTOUIZD + 444612018U, // VTOUIZH + 440548786U, // VTOUIZS + 1333689778U, // VTOULD + 1333820850U, // VTOULH + 1329757618U, // VTOULS + 154596U, // VTRNd16 + 285668U, // VTRNd32 + 416740U, // VTRNd8 + 154596U, // VTRNq16 + 285668U, // VTRNq32 + 416740U, // VTRNq8 + 425351U, // VTSTv16i8 + 294279U, // VTSTv2i32 + 163207U, // VTSTv4i16 + 294279U, // VTSTv4i32 + 163207U, // VTSTv8i16 + 425351U, // VTSTv8i8 + 910483U, // VUDOTD + 7070867U, // VUDOTDI + 910483U, // VUDOTQ + 7070867U, // VUDOTQI + 8551858U, // VUHTOD + 256802226U, // VUHTOH + 8682930U, // VUHTOS + 445005234U, // VUITOD + 445136306U, // VUITOH + 441204146U, // VUITOS + 1334214066U, // VULTOD + 1334345138U, // VULTOH + 1330412978U, // VULTOS + 154677U, // VUZPd16 + 416821U, // VUZPd8 + 154677U, // VUZPq16 + 285749U, // VUZPq32 + 416821U, // VUZPq8 + 154653U, // VZIPd16 + 416797U, // VZIPd8 + 154653U, // VZIPq16 + 285725U, // VZIPq32 + 416797U, // VZIPq8 + 571388U, // sysLDMDA + 2332571644U, // sysLDMDA_UPD + 571519U, // sysLDMDB + 2332571775U, // sysLDMDB_UPD + 572300U, // sysLDMIA + 2332572556U, // sysLDMIA_UPD + 571538U, // sysLDMIB + 2332571794U, // sysLDMIB_UPD + 571394U, // sysSTMDA + 2332571650U, // sysSTMDA_UPD + 571526U, // sysSTMDB + 2332571782U, // sysSTMDB_UPD + 572306U, // sysSTMIA + 2332572562U, // sysSTMIA_UPD + 571544U, // sysSTMIB + 2332571800U, // sysSTMIB_UPD + 530745U, // t2ADCri + 9050425U, // t2ADCrr + 9079097U, // t2ADCrs + 9050486U, // t2ADDri + 556533U, // t2ADDri12 + 9050486U, // t2ADDrr + 9079158U, // t2ADDrs + 9059406U, // t2ADR + 530859U, // t2ANDri + 9050539U, // t2ANDrr + 9079211U, // t2ANDrs + 9051260U, // t2ASRri + 9051260U, // t2ASRrr + 1082832976U, // t2B + 555329U, // t2BFC + 547483U, // t2BFI + 530758U, // t2BICri + 9050438U, // t2BICrr + 9079110U, // t2BICrs + 1074313901U, // t2BXJ + 1082832976U, // t2Bcc + 201907225U, // t2CDP + 201905823U, // t2CDP2 + 839310U, // t2CLREX + 540368U, // t2CLZ + 9059263U, // t2CMNri + 9059263U, // t2CMNzrr + 9075647U, // t2CMNzrs + 9059363U, // t2CMPri + 9059363U, // t2CMPrr + 9075747U, // t2CMPrs + 828709U, // t2CPS1p + 1317731549U, // t2CPS2p + 235470045U, // t2CPS3p + 185246891U, // t2CRC32B + 185246899U, // t2CRC32CB + 185246973U, // t2CRC32CH + 185247057U, // t2CRC32CW + 185246965U, // t2CRC32H + 185247049U, // t2CRC32W + 1074313739U, // t2DBG + 837235U, // t2DCPS1 + 837295U, // t2DCPS2 + 837311U, // t2DCPS3 + 822655139U, // t2DMB + 822655158U, // t2DSB + 531562U, // t2EORri + 9051242U, // t2EORrr + 9079914U, // t2EORrs + 1082834290U, // t2HINT + 828731U, // t2HVC + 839432378U, // t2ISB + 17313120U, // t2IT + 0U, // t2Int_eh_sjlj_setjmp + 0U, // t2Int_eh_sjlj_setjmp_nofp + 538616U, // t2LDA + 538701U, // t2LDAB + 540284U, // t2LDAEX + 538905U, // t2LDAEXB + 555461U, // t2LDAEXD + 539263U, // t2LDAEXH + 539165U, // t2LDAH + 1275615921U, // t2LDC2L_OFFSET + 1275615921U, // t2LDC2L_OPTION + 1275615921U, // t2LDC2L_POST + 1275615921U, // t2LDC2L_PRE + 1275614853U, // t2LDC2_OFFSET + 1275614853U, // t2LDC2_OPTION + 1275614853U, // t2LDC2_POST + 1275614853U, // t2LDC2_PRE + 1275615989U, // t2LDCL_OFFSET + 1275615989U, // t2LDCL_OPTION + 1275615989U, // t2LDCL_POST + 1275615989U, // t2LDCL_PRE + 1275615549U, // t2LDC_OFFSET + 1275615549U, // t2LDC_OPTION + 1275615549U, // t2LDC_POST + 1275615549U, // t2LDC_PRE + 571519U, // t2LDMDB + 2332571775U, // t2LDMDB_UPD + 9091980U, // t2LDMIA + 2341092236U, // t2LDMIA_UPD + 556328U, // t2LDRBT + 546988U, // t2LDRB_POST + 546988U, // t2LDRB_PRE + 9074860U, // t2LDRBi12 + 555180U, // t2LDRBi8 + 9058476U, // t2LDRBpci + 9066668U, // t2LDRBs + 551343U, // t2LDRD_POST + 551343U, // t2LDRD_PRE + 547247U, // t2LDRDi8 + 556680U, // t2LDREX + 538919U, // t2LDREXB + 555475U, // t2LDREXD + 539277U, // t2LDREXH + 556363U, // t2LDRHT + 547409U, // t2LDRH_POST + 547409U, // t2LDRH_PRE + 9075281U, // t2LDRHi12 + 555601U, // t2LDRHi8 + 9058897U, // t2LDRHpci + 9067089U, // t2LDRHs + 556340U, // t2LDRSBT + 547006U, // t2LDRSB_POST + 547006U, // t2LDRSB_PRE + 9074878U, // t2LDRSBi12 + 555198U, // t2LDRSBi8 + 9058494U, // t2LDRSBpci + 9066686U, // t2LDRSBs + 556375U, // t2LDRSHT + 547428U, // t2LDRSH_POST + 547428U, // t2LDRSH_PRE + 9075300U, // t2LDRSHi12 + 555620U, // t2LDRSHi8 + 9058916U, // t2LDRSHpci + 9067108U, // t2LDRSHs + 556407U, // t2LDRT + 547923U, // t2LDR_POST + 547923U, // t2LDR_PRE + 9075795U, // t2LDRi12 + 556115U, // t2LDRi8 + 9059411U, // t2LDRpci + 9067603U, // t2LDRs + 9050981U, // t2LSLri + 9050981U, // t2LSLrr + 9051267U, // t2LSRri + 9051267U, // t2LSRrr + 201907274U, // t2MCR + 201905828U, // t2MCR2 + 201878642U, // t2MCRR + 201877161U, // t2MCRR2 + 546852U, // t2MLA + 548021U, // t2MLS + 556471U, // t2MOVTi16 + 9063914U, // t2MOVi + 540159U, // t2MOVi16 + 9063914U, // t2MOVr + 9059558U, // t2MOVsra_flag + 9059563U, // t2MOVsrl_flag + 336124238U, // t2MRC + 336123530U, // t2MRC2 + 352872786U, // t2MRRC + 352872079U, // t2MRRC2 + 2148056290U, // t2MRS_AR + 539874U, // t2MRS_M + 539874U, // t2MRSbanked + 3221798114U, // t2MRSsys_AR + 369638536U, // t2MSR_AR + 369638536U, // t2MSR_M + 386415752U, // t2MSRbanked + 555893U, // t2MUL + 543747U, // t2MVNi + 9063427U, // t2MVNr + 9051139U, // t2MVNs + 531424U, // t2ORNri + 531424U, // t2ORNrr + 560096U, // t2ORNrs + 531576U, // t2ORRri + 9051256U, // t2ORRrr + 9079928U, // t2ORRrs + 548115U, // t2PKHBT + 547023U, // t2PKHTB + 856178170U, // t2PLDWi12 + 872955386U, // t2PLDWi8 + 889748986U, // t2PLDWs + 856177055U, // t2PLDi12 + 872954271U, // t2PLDi8 + 906541471U, // t2PLDpci + 889747871U, // t2PLDs + 856177311U, // t2PLIi12 + 872954527U, // t2PLIi8 + 906541727U, // t2PLIpci + 889748127U, // t2PLIs + 555406U, // t2QADD + 554800U, // t2QADD16 + 554903U, // t2QADD8 + 556729U, // t2QASX + 555380U, // t2QDADD + 555252U, // t2QDSUB + 556588U, // t2QSAX + 555265U, // t2QSUB + 554762U, // t2QSUB16 + 554864U, // t2QSUB8 + 539998U, // t2RBIT + 9059798U, // t2REV + 9058132U, // t2REV16 + 9058927U, // t2REVSH + 1074313336U, // t2RFEDB + 2148055160U, // t2RFEDBW + 1074313224U, // t2RFEIA + 2148055048U, // t2RFEIAW + 9051246U, // t2RORri + 9051246U, // t2RORrr + 544424U, // t2RRX + 9050304U, // t2RSBri + 530624U, // t2RSBrr + 559296U, // t2RSBrs + 554807U, // t2SADD16 + 554909U, // t2SADD8 + 556734U, // t2SASX + 530741U, // t2SBCri + 9050421U, // t2SBCrr + 9079093U, // t2SBCrs + 548506U, // t2SBFX + 556506U, // t2SDIV + 555794U, // t2SEL + 828701U, // t2SETPAN + 838170U, // t2SG + 554783U, // t2SHADD16 + 554888U, // t2SHADD8 + 556716U, // t2SHASX + 556575U, // t2SHSAX + 554745U, // t2SHSUB16 + 554849U, // t2SHSUB8 + 1074313546U, // t2SMC + 546910U, // t2SMLABB + 548108U, // t2SMLABT + 547171U, // t2SMLAD + 548432U, // t2SMLADX + 580312U, // t2SMLAL + 579685U, // t2SMLALBB + 580889U, // t2SMLALBT + 579992U, // t2SMLALD + 581214U, // t2SMLALDX + 579797U, // t2SMLALTB + 581011U, // t2SMLALTT + 547016U, // t2SMLATB + 548236U, // t2SMLATT + 547083U, // t2SMLAWB + 548284U, // t2SMLAWT + 547257U, // t2SMLSD + 548462U, // t2SMLSDX + 580003U, // t2SMLSLD + 581222U, // t2SMLSLDX + 546850U, // t2SMMLA + 547907U, // t2SMMLAR + 548019U, // t2SMMLS + 547968U, // t2SMMLSR + 555891U, // t2SMMUL + 556130U, // t2SMMULR + 555369U, // t2SMUAD + 556631U, // t2SMUADX + 555117U, // t2SMULBB + 556321U, // t2SMULBT + 547658U, // t2SMULL + 555229U, // t2SMULTB + 556443U, // t2SMULTT + 555282U, // t2SMULWB + 556483U, // t2SMULWT + 555455U, // t2SMUSD + 556661U, // t2SMUSDX + 9222284U, // t2SRSDB + 9353356U, // t2SRSDB_UPD + 9222172U, // t2SRSIA + 9353244U, // t2SRSIA_UPD + 548093U, // t2SSAT + 554821U, // t2SSAT16 + 556593U, // t2SSAX + 554769U, // t2SSUB16 + 554870U, // t2SSUB8 + 1275615927U, // t2STC2L_OFFSET + 1275615927U, // t2STC2L_OPTION + 1275615927U, // t2STC2L_POST + 1275615927U, // t2STC2L_PRE + 1275614869U, // t2STC2_OFFSET + 1275614869U, // t2STC2_OPTION + 1275614869U, // t2STC2_POST + 1275614869U, // t2STC2_PRE + 1275615994U, // t2STCL_OFFSET + 1275615994U, // t2STCL_OPTION + 1275615994U, // t2STCL_POST + 1275615994U, // t2STCL_PRE + 1275615579U, // t2STC_OFFSET + 1275615579U, // t2STC_OPTION + 1275615579U, // t2STC_POST + 1275615579U, // t2STC_PRE + 539503U, // t2STL + 538782U, // t2STLB + 556674U, // t2STLEX + 555296U, // t2STLEXB + 547276U, // t2STLEXD + 555654U, // t2STLEXH + 539195U, // t2STLH + 571526U, // t2STMDB + 2332571782U, // t2STMDB_UPD + 9091986U, // t2STMIA + 2341092242U, // t2STMIA_UPD + 556334U, // t2STRBT + 185096369U, // t2STRB_POST + 185096369U, // t2STRB_PRE + 9074865U, // t2STRBi12 + 555185U, // t2STRBi8 + 9066673U, // t2STRBs + 185100724U, // t2STRD_POST + 185100724U, // t2STRD_PRE + 547252U, // t2STRDi8 + 548500U, // t2STREX + 555310U, // t2STREXB + 547290U, // t2STREXD + 555668U, // t2STREXH + 556369U, // t2STRHT + 185096790U, // t2STRH_POST + 185096790U, // t2STRH_PRE + 9075286U, // t2STRHi12 + 555606U, // t2STRHi8 + 9067094U, // t2STRHs + 556418U, // t2STRT + 185097364U, // t2STR_POST + 185097364U, // t2STR_PRE + 9075860U, // t2STRi12 + 556180U, // t2STRi8 + 9067668U, // t2STRs + 9485481U, // t2SUBS_PC_LR + 9050358U, // t2SUBri + 556527U, // t2SUBri12 + 9050358U, // t2SUBrr + 9079030U, // t2SUBrs + 546898U, // t2SXTAB + 546523U, // t2SXTAB16 + 547371U, // t2SXTAH + 9074922U, // t2SXTB + 554731U, // t2SXTB16 + 9075317U, // t2SXTH + 923285620U, // t2TBB + 940063287U, // t2TBH + 9059391U, // t2TEQri + 9059391U, // t2TEQrr + 9075775U, // t2TEQrs + 956872900U, // t2TSB + 9059720U, // t2TSTri + 9059720U, // t2TSTrr + 9076104U, // t2TSTrs + 540048U, // t2TT + 538697U, // t2TTA + 539911U, // t2TTAT + 540066U, // t2TTT + 554814U, // t2UADD16 + 554915U, // t2UADD8 + 556739U, // t2UASX + 548511U, // t2UBFX + 828738U, // t2UDF + 556511U, // t2UDIV + 554791U, // t2UHADD16 + 554895U, // t2UHADD8 + 556722U, // t2UHASX + 556581U, // t2UHSAX + 554753U, // t2UHSUB16 + 554856U, // t2UHSUB8 + 580285U, // t2UMAAL + 580318U, // t2UMLAL + 547664U, // t2UMULL + 554799U, // t2UQADD16 + 554902U, // t2UQADD8 + 556728U, // t2UQASX + 556587U, // t2UQSAX + 554761U, // t2UQSUB16 + 554863U, // t2UQSUB8 + 554882U, // t2USAD8 + 546650U, // t2USADA8 + 548098U, // t2USAT + 554828U, // t2USAT16 + 556598U, // t2USAX + 554776U, // t2USUB16 + 554876U, // t2USUB8 + 546904U, // t2UXTAB + 546531U, // t2UXTAB16 + 547377U, // t2UXTAH + 9074927U, // t2UXTB + 554738U, // t2UXTB16 + 9075322U, // t2UXTH + 982776121U, // tADC + 555382U, // tADDhirr + 177469814U, // tADDi3 + 982776182U, // tADDi8 + 555382U, // tADDrSP + 555382U, // tADDrSPi + 177469814U, // tADDrr + 555382U, // tADDspi + 555382U, // tADDspr + 539726U, // tADR + 982776235U, // tAND + 177470588U, // tASRri + 982776956U, // tASRrr + 1074313296U, // tB + 982776134U, // tBIC + 828725U, // tBKPT + 1242090220U, // tBL + 1242090708U, // tBLXNSr + 1242091172U, // tBLXi + 1242091172U, // tBLXr + 1074314816U, // tBX + 1074314447U, // tBXNS + 1074313296U, // tBcc + 1258988910U, // tCBNZ + 1258988905U, // tCBZ + 539583U, // tCMNz + 539683U, // tCMPhir + 539683U, // tCMPi8 + 539683U, // tCMPr + 1308687581U, // tCPS + 982776938U, // tEOR + 1074314610U, // tHINT + 828720U, // tHLT + 0U, // tInt_WIN_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_setjmp + 572300U, // tLDMIA + 555180U, // tLDRBi + 555180U, // tLDRBr + 555601U, // tLDRHi + 555601U, // tLDRHr + 555198U, // tLDRSB + 555620U, // tLDRSH + 556115U, // tLDRi + 539731U, // tLDRpci + 556115U, // tLDRr + 556115U, // tLDRspi + 177470309U, // tLSLri + 982776677U, // tLSLrr + 177470595U, // tLSRri + 982776963U, // tLSRrr + 1258988842U, // tMOVSr + 446037482U, // tMOVi8 + 540138U, // tMOVr + 177470325U, // tMUL + 446036995U, // tMVN + 982776952U, // tORR + 0U, // tPICADD + 990432295U, // tPOP + 990431850U, // tPUSH + 540118U, // tREV + 538452U, // tREV16 + 539247U, // tREVSH + 982776942U, // tROR + 429258944U, // tRSB + 982776117U, // tSBC + 91368U, // tSETEND + 2332572562U, // tSTMIA_UPD + 555185U, // tSTRBi + 555185U, // tSTRBr + 555606U, // tSTRHi + 555606U, // tSTRHr + 556180U, // tSTRi + 556180U, // tSTRr + 556180U, // tSTRspi + 177469686U, // tSUBi3 + 982776054U, // tSUBi8 + 177469686U, // tSUBrr + 555254U, // tSUBspi + 1074313567U, // tSVC + 538858U, // tSXTB + 539253U, // tSXTH + 3092U, // tTRAP + 540040U, // tTST + 828656U, // tUDF + 538863U, // tUXTB + 539258U, // tUXTH + 1636U, // t__brkdiv0 }; static const uint32_t OpInfo1[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 0U, // DBG_VALUE - 0U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 0U, // BUNDLE - 0U, // LIFETIME_START - 0U, // LIFETIME_END - 0U, // STACKMAP - 0U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 0U, // PATCHABLE_FUNCTION_ENTER - 0U, // PATCHABLE_RET - 0U, // PATCHABLE_FUNCTION_EXIT - 0U, // PATCHABLE_TAIL_CALL - 0U, // PATCHABLE_EVENT_CALL - 0U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDE - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SSUBO - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_BSWAP - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 0U, // ABS - 0U, // ADDSri - 0U, // ADDSrr - 0U, // ADDSrsi - 0U, // ADDSrsr - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 0U, // ASRi - 0U, // ASRr - 0U, // B - 0U, // BCCZi64 - 0U, // BCCi64 - 0U, // BMOVPCB_CALL - 0U, // BMOVPCRX_CALL - 0U, // BR_JTadd - 0U, // BR_JTm_i12 - 0U, // BR_JTm_rs - 0U, // BR_JTr - 0U, // BX_CALL - 0U, // CMP_SWAP_16 - 0U, // CMP_SWAP_32 - 0U, // CMP_SWAP_64 - 0U, // CMP_SWAP_8 - 0U, // CONSTPOOL_ENTRY - 0U, // COPY_STRUCT_BYVAL_I32 - 0U, // CompilerBarrier - 0U, // ITasm - 0U, // Int_eh_sjlj_dispatchsetup - 0U, // Int_eh_sjlj_longjmp - 0U, // Int_eh_sjlj_setjmp - 0U, // Int_eh_sjlj_setjmp_nofp - 0U, // Int_eh_sjlj_setup_dispatch - 0U, // JUMPTABLE_ADDRS - 0U, // JUMPTABLE_INSTS - 0U, // JUMPTABLE_TBB - 0U, // JUMPTABLE_TBH - 0U, // LDMIA_RET - 8U, // LDRBT_POST - 1024U, // LDRConstPool - 0U, // LDRLIT_ga_abs - 0U, // LDRLIT_ga_pcrel - 0U, // LDRLIT_ga_pcrel_ldr - 8U, // LDRT_POST - 0U, // LEApcrel - 0U, // LEApcrelJT - 0U, // LSLi - 0U, // LSLr - 0U, // LSRi - 0U, // LSRr - 0U, // MEMCPY - 0U, // MLAv5 - 0U, // MOVCCi - 0U, // MOVCCi16 - 0U, // MOVCCi32imm - 0U, // MOVCCr - 0U, // MOVCCsi - 0U, // MOVCCsr - 0U, // MOVPCRX - 0U, // MOVTi16_ga_pcrel - 0U, // MOV_ga_pcrel - 0U, // MOV_ga_pcrel_ldr - 0U, // MOVi16_ga_pcrel - 0U, // MOVi32imm - 0U, // MOVsra_flag - 0U, // MOVsrl_flag - 0U, // MULv5 - 0U, // MVNCCi - 0U, // PICADD - 0U, // PICLDR - 0U, // PICLDRB - 0U, // PICLDRH - 0U, // PICLDRSB - 0U, // PICLDRSH - 0U, // PICSTR - 0U, // PICSTRB - 0U, // PICSTRH - 0U, // RORi - 0U, // RORr - 0U, // RRX - 1024U, // RRXi - 0U, // RSBSri - 0U, // RSBSrsi - 0U, // RSBSrsr - 0U, // SMLALv5 - 0U, // SMULLv5 - 0U, // SPACE - 8U, // STRBT_POST - 0U, // STRBi_preidx - 0U, // STRBr_preidx - 0U, // STRH_preidx - 8U, // STRT_POST - 0U, // STRi_preidx - 0U, // STRr_preidx - 0U, // SUBS_PC_LR - 0U, // SUBSri - 0U, // SUBSrr - 0U, // SUBSrsi - 0U, // SUBSrsr - 0U, // TAILJMPd - 0U, // TAILJMPr - 0U, // TAILJMPr4 - 0U, // TCRETURNdi - 0U, // TCRETURNri - 0U, // TPsoft - 0U, // UMLALv5 - 0U, // UMULLv5 - 1040U, // VLD1LNdAsm_16 - 1040U, // VLD1LNdAsm_32 - 1040U, // VLD1LNdAsm_8 - 2064U, // VLD1LNdWB_fixed_Asm_16 - 2064U, // VLD1LNdWB_fixed_Asm_32 - 2064U, // VLD1LNdWB_fixed_Asm_8 - 32784U, // VLD1LNdWB_register_Asm_16 - 32784U, // VLD1LNdWB_register_Asm_32 - 32784U, // VLD1LNdWB_register_Asm_8 - 1040U, // VLD2LNdAsm_16 - 1040U, // VLD2LNdAsm_32 - 1040U, // VLD2LNdAsm_8 - 2064U, // VLD2LNdWB_fixed_Asm_16 - 2064U, // VLD2LNdWB_fixed_Asm_32 - 2064U, // VLD2LNdWB_fixed_Asm_8 - 32784U, // VLD2LNdWB_register_Asm_16 - 32784U, // VLD2LNdWB_register_Asm_32 - 32784U, // VLD2LNdWB_register_Asm_8 - 1040U, // VLD2LNqAsm_16 - 1040U, // VLD2LNqAsm_32 - 2064U, // VLD2LNqWB_fixed_Asm_16 - 2064U, // VLD2LNqWB_fixed_Asm_32 - 32784U, // VLD2LNqWB_register_Asm_16 - 32784U, // VLD2LNqWB_register_Asm_32 - 0U, // VLD3DUPdAsm_16 - 0U, // VLD3DUPdAsm_32 - 0U, // VLD3DUPdAsm_8 - 0U, // VLD3DUPdWB_fixed_Asm_16 - 0U, // VLD3DUPdWB_fixed_Asm_32 - 0U, // VLD3DUPdWB_fixed_Asm_8 - 1048U, // VLD3DUPdWB_register_Asm_16 - 1048U, // VLD3DUPdWB_register_Asm_32 - 1048U, // VLD3DUPdWB_register_Asm_8 - 0U, // VLD3DUPqAsm_16 - 0U, // VLD3DUPqAsm_32 - 0U, // VLD3DUPqAsm_8 - 0U, // VLD3DUPqWB_fixed_Asm_16 - 0U, // VLD3DUPqWB_fixed_Asm_32 - 0U, // VLD3DUPqWB_fixed_Asm_8 - 1048U, // VLD3DUPqWB_register_Asm_16 - 1048U, // VLD3DUPqWB_register_Asm_32 - 1048U, // VLD3DUPqWB_register_Asm_8 - 1040U, // VLD3LNdAsm_16 - 1040U, // VLD3LNdAsm_32 - 1040U, // VLD3LNdAsm_8 - 2064U, // VLD3LNdWB_fixed_Asm_16 - 2064U, // VLD3LNdWB_fixed_Asm_32 - 2064U, // VLD3LNdWB_fixed_Asm_8 - 32784U, // VLD3LNdWB_register_Asm_16 - 32784U, // VLD3LNdWB_register_Asm_32 - 32784U, // VLD3LNdWB_register_Asm_8 - 1040U, // VLD3LNqAsm_16 - 1040U, // VLD3LNqAsm_32 - 2064U, // VLD3LNqWB_fixed_Asm_16 - 2064U, // VLD3LNqWB_fixed_Asm_32 - 32784U, // VLD3LNqWB_register_Asm_16 - 32784U, // VLD3LNqWB_register_Asm_32 - 32U, // VLD3dAsm_16 - 32U, // VLD3dAsm_32 - 32U, // VLD3dAsm_8 - 40U, // VLD3dWB_fixed_Asm_16 - 40U, // VLD3dWB_fixed_Asm_32 - 40U, // VLD3dWB_fixed_Asm_8 - 68656U, // VLD3dWB_register_Asm_16 - 68656U, // VLD3dWB_register_Asm_32 - 68656U, // VLD3dWB_register_Asm_8 - 0U, // VLD3qAsm_16 - 0U, // VLD3qAsm_32 - 0U, // VLD3qAsm_8 - 0U, // VLD3qWB_fixed_Asm_16 - 0U, // VLD3qWB_fixed_Asm_32 - 0U, // VLD3qWB_fixed_Asm_8 - 1048U, // VLD3qWB_register_Asm_16 - 1048U, // VLD3qWB_register_Asm_32 - 1048U, // VLD3qWB_register_Asm_8 - 0U, // VLD4DUPdAsm_16 - 0U, // VLD4DUPdAsm_32 - 0U, // VLD4DUPdAsm_8 - 0U, // VLD4DUPdWB_fixed_Asm_16 - 0U, // VLD4DUPdWB_fixed_Asm_32 - 0U, // VLD4DUPdWB_fixed_Asm_8 - 1048U, // VLD4DUPdWB_register_Asm_16 - 1048U, // VLD4DUPdWB_register_Asm_32 - 1048U, // VLD4DUPdWB_register_Asm_8 - 0U, // VLD4DUPqAsm_16 - 0U, // VLD4DUPqAsm_32 - 0U, // VLD4DUPqAsm_8 - 0U, // VLD4DUPqWB_fixed_Asm_16 - 0U, // VLD4DUPqWB_fixed_Asm_32 - 0U, // VLD4DUPqWB_fixed_Asm_8 - 1048U, // VLD4DUPqWB_register_Asm_16 - 1048U, // VLD4DUPqWB_register_Asm_32 - 1048U, // VLD4DUPqWB_register_Asm_8 - 1040U, // VLD4LNdAsm_16 - 1040U, // VLD4LNdAsm_32 - 1040U, // VLD4LNdAsm_8 - 2064U, // VLD4LNdWB_fixed_Asm_16 - 2064U, // VLD4LNdWB_fixed_Asm_32 - 2064U, // VLD4LNdWB_fixed_Asm_8 - 32784U, // VLD4LNdWB_register_Asm_16 - 32784U, // VLD4LNdWB_register_Asm_32 - 32784U, // VLD4LNdWB_register_Asm_8 - 1040U, // VLD4LNqAsm_16 - 1040U, // VLD4LNqAsm_32 - 2064U, // VLD4LNqWB_fixed_Asm_16 - 2064U, // VLD4LNqWB_fixed_Asm_32 - 32784U, // VLD4LNqWB_register_Asm_16 - 32784U, // VLD4LNqWB_register_Asm_32 - 32U, // VLD4dAsm_16 - 32U, // VLD4dAsm_32 - 32U, // VLD4dAsm_8 - 40U, // VLD4dWB_fixed_Asm_16 - 40U, // VLD4dWB_fixed_Asm_32 - 40U, // VLD4dWB_fixed_Asm_8 - 68656U, // VLD4dWB_register_Asm_16 - 68656U, // VLD4dWB_register_Asm_32 - 68656U, // VLD4dWB_register_Asm_8 - 0U, // VLD4qAsm_16 - 0U, // VLD4qAsm_32 - 0U, // VLD4qAsm_8 - 0U, // VLD4qWB_fixed_Asm_16 - 0U, // VLD4qWB_fixed_Asm_32 - 0U, // VLD4qWB_fixed_Asm_8 - 1048U, // VLD4qWB_register_Asm_16 - 1048U, // VLD4qWB_register_Asm_32 - 1048U, // VLD4qWB_register_Asm_8 - 0U, // VMOVD0 - 0U, // VMOVDcc - 0U, // VMOVQ0 - 0U, // VMOVScc - 1040U, // VST1LNdAsm_16 - 1040U, // VST1LNdAsm_32 - 1040U, // VST1LNdAsm_8 - 2064U, // VST1LNdWB_fixed_Asm_16 - 2064U, // VST1LNdWB_fixed_Asm_32 - 2064U, // VST1LNdWB_fixed_Asm_8 - 32784U, // VST1LNdWB_register_Asm_16 - 32784U, // VST1LNdWB_register_Asm_32 - 32784U, // VST1LNdWB_register_Asm_8 - 1040U, // VST2LNdAsm_16 - 1040U, // VST2LNdAsm_32 - 1040U, // VST2LNdAsm_8 - 2064U, // VST2LNdWB_fixed_Asm_16 - 2064U, // VST2LNdWB_fixed_Asm_32 - 2064U, // VST2LNdWB_fixed_Asm_8 - 32784U, // VST2LNdWB_register_Asm_16 - 32784U, // VST2LNdWB_register_Asm_32 - 32784U, // VST2LNdWB_register_Asm_8 - 1040U, // VST2LNqAsm_16 - 1040U, // VST2LNqAsm_32 - 2064U, // VST2LNqWB_fixed_Asm_16 - 2064U, // VST2LNqWB_fixed_Asm_32 - 32784U, // VST2LNqWB_register_Asm_16 - 32784U, // VST2LNqWB_register_Asm_32 - 1040U, // VST3LNdAsm_16 - 1040U, // VST3LNdAsm_32 - 1040U, // VST3LNdAsm_8 - 2064U, // VST3LNdWB_fixed_Asm_16 - 2064U, // VST3LNdWB_fixed_Asm_32 - 2064U, // VST3LNdWB_fixed_Asm_8 - 32784U, // VST3LNdWB_register_Asm_16 - 32784U, // VST3LNdWB_register_Asm_32 - 32784U, // VST3LNdWB_register_Asm_8 - 1040U, // VST3LNqAsm_16 - 1040U, // VST3LNqAsm_32 - 2064U, // VST3LNqWB_fixed_Asm_16 - 2064U, // VST3LNqWB_fixed_Asm_32 - 32784U, // VST3LNqWB_register_Asm_16 - 32784U, // VST3LNqWB_register_Asm_32 - 32U, // VST3dAsm_16 - 32U, // VST3dAsm_32 - 32U, // VST3dAsm_8 - 40U, // VST3dWB_fixed_Asm_16 - 40U, // VST3dWB_fixed_Asm_32 - 40U, // VST3dWB_fixed_Asm_8 - 68656U, // VST3dWB_register_Asm_16 - 68656U, // VST3dWB_register_Asm_32 - 68656U, // VST3dWB_register_Asm_8 - 0U, // VST3qAsm_16 - 0U, // VST3qAsm_32 - 0U, // VST3qAsm_8 - 0U, // VST3qWB_fixed_Asm_16 - 0U, // VST3qWB_fixed_Asm_32 - 0U, // VST3qWB_fixed_Asm_8 - 1048U, // VST3qWB_register_Asm_16 - 1048U, // VST3qWB_register_Asm_32 - 1048U, // VST3qWB_register_Asm_8 - 1040U, // VST4LNdAsm_16 - 1040U, // VST4LNdAsm_32 - 1040U, // VST4LNdAsm_8 - 2064U, // VST4LNdWB_fixed_Asm_16 - 2064U, // VST4LNdWB_fixed_Asm_32 - 2064U, // VST4LNdWB_fixed_Asm_8 - 32784U, // VST4LNdWB_register_Asm_16 - 32784U, // VST4LNdWB_register_Asm_32 - 32784U, // VST4LNdWB_register_Asm_8 - 1040U, // VST4LNqAsm_16 - 1040U, // VST4LNqAsm_32 - 2064U, // VST4LNqWB_fixed_Asm_16 - 2064U, // VST4LNqWB_fixed_Asm_32 - 32784U, // VST4LNqWB_register_Asm_16 - 32784U, // VST4LNqWB_register_Asm_32 - 32U, // VST4dAsm_16 - 32U, // VST4dAsm_32 - 32U, // VST4dAsm_8 - 40U, // VST4dWB_fixed_Asm_16 - 40U, // VST4dWB_fixed_Asm_32 - 40U, // VST4dWB_fixed_Asm_8 - 68656U, // VST4dWB_register_Asm_16 - 68656U, // VST4dWB_register_Asm_32 - 68656U, // VST4dWB_register_Asm_8 - 0U, // VST4qAsm_16 - 0U, // VST4qAsm_32 - 0U, // VST4qAsm_8 - 0U, // VST4qWB_fixed_Asm_16 - 0U, // VST4qWB_fixed_Asm_32 - 0U, // VST4qWB_fixed_Asm_8 - 1048U, // VST4qWB_register_Asm_16 - 1048U, // VST4qWB_register_Asm_32 - 1048U, // VST4qWB_register_Asm_8 - 0U, // WIN__CHKSTK - 0U, // WIN__DBZCHK - 0U, // t2ABS - 0U, // t2ADDSri - 0U, // t2ADDSrr - 0U, // t2ADDSrs - 0U, // t2BR_JT - 0U, // t2LDMIA_RET - 1024U, // t2LDRBpcrel - 1024U, // t2LDRConstPool - 1024U, // t2LDRHpcrel - 1024U, // t2LDRSBpcrel - 1024U, // t2LDRSHpcrel - 0U, // t2LDRpci_pic - 1024U, // t2LDRpcrel - 0U, // t2LEApcrel - 0U, // t2LEApcrelJT - 0U, // t2MOVCCasr - 0U, // t2MOVCCi - 0U, // t2MOVCCi16 - 0U, // t2MOVCCi32imm - 0U, // t2MOVCClsl - 0U, // t2MOVCClsr - 0U, // t2MOVCCr - 0U, // t2MOVCCror - 56U, // t2MOVSsi - 64U, // t2MOVSsr - 0U, // t2MOVTi16_ga_pcrel - 0U, // t2MOV_ga_pcrel - 0U, // t2MOVi16_ga_pcrel - 0U, // t2MOVi32imm - 56U, // t2MOVsi - 64U, // t2MOVsr - 0U, // t2MVNCCi - 0U, // t2RSBSri - 0U, // t2RSBSrs - 0U, // t2STRB_preidx - 0U, // t2STRH_preidx - 0U, // t2STR_preidx - 0U, // t2SUBSri - 0U, // t2SUBSrr - 0U, // t2SUBSrs - 0U, // t2TBB_JT - 0U, // t2TBH_JT - 0U, // tADCS - 0U, // tADDSi3 - 0U, // tADDSi8 - 0U, // tADDSrr - 0U, // tADDframe - 0U, // tADJCALLSTACKDOWN - 0U, // tADJCALLSTACKUP - 0U, // tBRIND - 0U, // tBR_JTr - 0U, // tBX_CALL - 0U, // tBX_RET - 0U, // tBX_RET_vararg - 0U, // tBfar - 0U, // tLDMIA_UPD - 1024U, // tLDRConstPool - 0U, // tLDRLIT_ga_abs - 0U, // tLDRLIT_ga_pcrel - 0U, // tLDR_postidx - 0U, // tLDRpci_pic - 0U, // tLEApcrel - 0U, // tLEApcrelJT - 0U, // tMOVCCr_pseudo - 0U, // tPOP_RET - 0U, // tSBCS - 0U, // tSUBSi3 - 0U, // tSUBSi8 - 0U, // tSUBSrr - 0U, // tTAILJMPd - 0U, // tTAILJMPdND - 0U, // tTAILJMPr - 0U, // tTBB_JT - 0U, // tTBH_JT - 0U, // tTPsoft - 98304U, // ADCri - 0U, // ADCrr - 131072U, // ADCrsi - 0U, // ADCrsr - 98304U, // ADDri - 0U, // ADDrr - 131072U, // ADDrsi - 0U, // ADDrsr - 72U, // ADR - 0U, // AESD - 0U, // AESE - 0U, // AESIMC - 0U, // AESMC - 98304U, // ANDri - 0U, // ANDrr - 131072U, // ANDrsi - 0U, // ANDrsr - 80U, // BFC - 163928U, // BFI - 98304U, // BICri - 0U, // BICrr - 131072U, // BICrsi - 0U, // BICrsr - 0U, // BKPT - 0U, // BL - 0U, // BLX - 0U, // BLX_pred - 0U, // BLXi - 0U, // BL_pred - 0U, // BX - 0U, // BXJ - 0U, // BX_RET - 0U, // BX_pred - 0U, // Bcc - 4145U, // CDP - 0U, // CDP2 - 0U, // CLREX - 1024U, // CLZ - 96U, // CMNri - 1024U, // CMNzrr - 104U, // CMNzrsi - 64U, // CMNzrsr - 96U, // CMPri - 1024U, // CMPrr - 104U, // CMPrsi - 64U, // CMPrsr - 0U, // CPS1p - 0U, // CPS2p - 1112U, // CPS3p - 1112U, // CRC32B - 1112U, // CRC32CB - 1112U, // CRC32CH - 1112U, // CRC32CW - 1112U, // CRC32H - 1112U, // CRC32W - 0U, // DBG - 0U, // DMB - 0U, // DSB - 98304U, // EORri - 0U, // EORrr - 131072U, // EORrsi - 0U, // EORrsr - 0U, // ERET - 1U, // FCONSTD - 1U, // FCONSTH - 1U, // FCONSTS - 33U, // FLDMXDB_UPD - 1136U, // FLDMXIA - 33U, // FLDMXIA_UPD - 0U, // FMSTAT - 33U, // FSTMXDB_UPD - 1136U, // FSTMXIA - 33U, // FSTMXIA_UPD - 0U, // HINT - 0U, // HLT - 0U, // HVC - 0U, // ISB - 8U, // LDA - 8U, // LDAB - 8U, // LDAEX - 8U, // LDAEXB - 0U, // LDAEXD - 8U, // LDAEXH - 8U, // LDAH - 0U, // LDC2L_OFFSET - 1U, // LDC2L_OPTION - 2U, // LDC2L_POST - 0U, // LDC2L_PRE - 0U, // LDC2_OFFSET - 1U, // LDC2_OPTION - 2U, // LDC2_POST - 0U, // LDC2_PRE - 122U, // LDCL_OFFSET - 196738U, // LDCL_OPTION - 229506U, // LDCL_POST - 138U, // LDCL_PRE - 122U, // LDC_OFFSET - 196738U, // LDC_OPTION - 229506U, // LDC_POST - 138U, // LDC_PRE - 1136U, // LDMDA - 33U, // LDMDA_UPD - 1136U, // LDMDB - 33U, // LDMDB_UPD - 1136U, // LDMIA - 33U, // LDMIA_UPD - 1136U, // LDMIB - 33U, // LDMIB_UPD - 262272U, // LDRBT_POST_IMM - 262272U, // LDRBT_POST_REG - 262272U, // LDRB_POST_IMM - 262272U, // LDRB_POST_REG - 144U, // LDRB_PRE_IMM - 152U, // LDRB_PRE_REG - 160U, // LDRBi12 - 168U, // LDRBrs - 294912U, // LDRD - 2424832U, // LDRD_POST - 360448U, // LDRD_PRE - 8U, // LDREX - 8U, // LDREXB - 0U, // LDREXD - 8U, // LDREXH - 176U, // LDRH - 393344U, // LDRHTi - 426112U, // LDRHTr - 458880U, // LDRH_POST - 184U, // LDRH_PRE - 176U, // LDRSB - 393344U, // LDRSBTi - 426112U, // LDRSBTr - 458880U, // LDRSB_POST - 184U, // LDRSB_PRE - 176U, // LDRSH - 393344U, // LDRSHTi - 426112U, // LDRSHTr - 458880U, // LDRSH_POST - 184U, // LDRSH_PRE - 262272U, // LDRT_POST_IMM - 262272U, // LDRT_POST_REG - 262272U, // LDR_POST_IMM - 262272U, // LDR_POST_REG - 144U, // LDR_PRE_IMM - 152U, // LDR_PRE_REG - 160U, // LDRcp - 160U, // LDRi12 - 168U, // LDRrs - 4690993U, // MCR - 192U, // MCR2 - 6788145U, // MCRR - 524312U, // MCRR2 - 35651584U, // MLA - 35651584U, // MLS - 0U, // MOVPCLR - 1112U, // MOVTi16 - 96U, // MOVi - 1024U, // MOVi16 - 1024U, // MOVr - 1024U, // MOVr_TC - 104U, // MOVsi - 64U, // MOVsr - 0U, // MRC - 0U, // MRC2 - 0U, // MRRC - 0U, // MRRC2 - 2U, // MRS - 200U, // MRSbanked - 2U, // MRSsys - 33U, // MSR - 0U, // MSRbanked - 3U, // MSRi - 0U, // MUL - 96U, // MVNi - 1024U, // MVNr - 104U, // MVNsi - 64U, // MVNsr - 98304U, // ORRri - 0U, // ORRrr - 131072U, // ORRrsi - 0U, // ORRrsr - 8388608U, // PKHBT - 10485760U, // PKHTB - 0U, // PLDWi12 - 0U, // PLDWrs - 0U, // PLDi12 - 0U, // PLDrs - 0U, // PLIi12 - 0U, // PLIrs - 0U, // QADD - 0U, // QADD16 - 0U, // QADD8 - 0U, // QASX - 0U, // QDADD - 0U, // QDSUB - 0U, // QSAX - 0U, // QSUB - 0U, // QSUB16 - 0U, // QSUB8 - 1024U, // RBIT - 1024U, // REV - 1024U, // REV16 - 1024U, // REVSH - 0U, // RFEDA - 0U, // RFEDA_UPD - 0U, // RFEDB - 0U, // RFEDB_UPD - 0U, // RFEIA - 0U, // RFEIA_UPD - 0U, // RFEIB - 0U, // RFEIB_UPD - 98304U, // RSBri - 0U, // RSBrr - 131072U, // RSBrsi - 0U, // RSBrsr - 98304U, // RSCri - 0U, // RSCrr - 131072U, // RSCrsi - 0U, // RSCrsr - 0U, // SADD16 - 0U, // SADD8 - 0U, // SASX - 98304U, // SBCri - 0U, // SBCrr - 131072U, // SBCrsi - 0U, // SBCrsr - 69206016U, // SBFX - 0U, // SDIV - 0U, // SEL - 0U, // SETEND - 0U, // SETPAN - 1048U, // SHA1C - 0U, // SHA1H - 1048U, // SHA1M - 1048U, // SHA1P - 1048U, // SHA1SU0 - 0U, // SHA1SU1 - 1048U, // SHA256H - 1048U, // SHA256H2 - 0U, // SHA256SU0 - 1048U, // SHA256SU1 - 0U, // SHADD16 - 0U, // SHADD8 - 0U, // SHASX - 0U, // SHSAX - 0U, // SHSUB16 - 0U, // SHSUB8 - 0U, // SMC - 35651584U, // SMLABB - 35651584U, // SMLABT - 35651584U, // SMLAD - 35651584U, // SMLADX - 0U, // SMLAL - 35651584U, // SMLALBB - 35651584U, // SMLALBT - 35651584U, // SMLALD - 35651584U, // SMLALDX - 35651584U, // SMLALTB - 35651584U, // SMLALTT - 35651584U, // SMLATB - 35651584U, // SMLATT - 35651584U, // SMLAWB - 35651584U, // SMLAWT - 35651584U, // SMLSD - 35651584U, // SMLSDX - 35651584U, // SMLSLD - 35651584U, // SMLSLDX - 35651584U, // SMMLA - 35651584U, // SMMLAR - 35651584U, // SMMLS - 35651584U, // SMMLSR - 0U, // SMMUL - 0U, // SMMULR - 0U, // SMUAD - 0U, // SMUADX - 0U, // SMULBB - 0U, // SMULBT - 35651584U, // SMULL - 0U, // SMULTB - 0U, // SMULTT - 0U, // SMULWB - 0U, // SMULWT - 0U, // SMUSD - 0U, // SMUSDX - 0U, // SRSDA - 0U, // SRSDA_UPD - 0U, // SRSDB - 0U, // SRSDB_UPD - 0U, // SRSIA - 0U, // SRSIA_UPD - 0U, // SRSIB - 0U, // SRSIB_UPD - 6352U, // SSAT - 1232U, // SSAT16 - 0U, // SSAX - 0U, // SSUB16 - 0U, // SSUB8 - 0U, // STC2L_OFFSET - 1U, // STC2L_OPTION - 2U, // STC2L_POST - 0U, // STC2L_PRE - 0U, // STC2_OFFSET - 1U, // STC2_OPTION - 2U, // STC2_POST - 0U, // STC2_PRE - 122U, // STCL_OFFSET - 196738U, // STCL_OPTION - 229506U, // STCL_POST - 138U, // STCL_PRE - 122U, // STC_OFFSET - 196738U, // STC_OPTION - 229506U, // STC_POST - 138U, // STC_PRE - 8U, // STL - 8U, // STLB - 557056U, // STLEX - 557056U, // STLEXB - 216U, // STLEXD - 557056U, // STLEXH - 8U, // STLH - 1136U, // STMDA - 33U, // STMDA_UPD - 1136U, // STMDB - 33U, // STMDB_UPD - 1136U, // STMIA - 33U, // STMIA_UPD - 1136U, // STMIB - 33U, // STMIB_UPD - 262272U, // STRBT_POST_IMM - 262272U, // STRBT_POST_REG - 262272U, // STRB_POST_IMM - 262272U, // STRB_POST_REG - 144U, // STRB_PRE_IMM - 152U, // STRB_PRE_REG - 160U, // STRBi12 - 168U, // STRBrs - 294912U, // STRD - 2424920U, // STRD_POST - 360536U, // STRD_PRE - 557056U, // STREX - 557056U, // STREXB - 216U, // STREXD - 557056U, // STREXH - 176U, // STRH - 393344U, // STRHTi - 426112U, // STRHTr - 458880U, // STRH_POST - 184U, // STRH_PRE - 262272U, // STRT_POST_IMM - 262272U, // STRT_POST_REG - 262272U, // STR_POST_IMM - 262272U, // STR_POST_REG - 144U, // STR_PRE_IMM - 152U, // STR_PRE_REG - 160U, // STRi12 - 168U, // STRrs - 98304U, // SUBri - 0U, // SUBrr - 131072U, // SUBrsi - 0U, // SUBrsr - 0U, // SVC - 557056U, // SWP - 557056U, // SWPB - 12582912U, // SXTAB - 12582912U, // SXTAB16 - 12582912U, // SXTAH - 7168U, // SXTB - 7168U, // SXTB16 - 7168U, // SXTH - 96U, // TEQri - 1024U, // TEQrr - 104U, // TEQrsi - 64U, // TEQrsr - 0U, // TRAP - 0U, // TRAPNaCl - 0U, // TSB - 96U, // TSTri - 1024U, // TSTrr - 104U, // TSTrsi - 64U, // TSTrsr - 0U, // UADD16 - 0U, // UADD8 - 0U, // UASX - 69206016U, // UBFX - 0U, // UDF - 0U, // UDIV - 0U, // UHADD16 - 0U, // UHADD8 - 0U, // UHASX - 0U, // UHSAX - 0U, // UHSUB16 - 0U, // UHSUB8 - 35651584U, // UMAAL - 0U, // UMLAL - 35651584U, // UMULL - 0U, // UQADD16 - 0U, // UQADD8 - 0U, // UQASX - 0U, // UQSAX - 0U, // UQSUB16 - 0U, // UQSUB8 - 0U, // USAD8 - 35651584U, // USADA8 - 14680064U, // USAT - 0U, // USAT16 - 0U, // USAX - 0U, // USUB16 - 0U, // USUB8 - 12582912U, // UXTAB - 12582912U, // UXTAB16 - 12582912U, // UXTAH - 7168U, // UXTB - 7168U, // UXTB16 - 7168U, // UXTH - 1048U, // VABALsv2i64 - 1048U, // VABALsv4i32 - 1048U, // VABALsv8i16 - 1048U, // VABALuv2i64 - 1048U, // VABALuv4i32 - 1048U, // VABALuv8i16 - 1048U, // VABAsv16i8 - 1048U, // VABAsv2i32 - 1048U, // VABAsv4i16 - 1048U, // VABAsv4i32 - 1048U, // VABAsv8i16 - 1048U, // VABAsv8i8 - 1048U, // VABAuv16i8 - 1048U, // VABAuv2i32 - 1048U, // VABAuv4i16 - 1048U, // VABAuv4i32 - 1048U, // VABAuv8i16 - 1048U, // VABAuv8i8 - 1112U, // VABDLsv2i64 - 1112U, // VABDLsv4i32 - 1112U, // VABDLsv8i16 - 1112U, // VABDLuv2i64 - 1112U, // VABDLuv4i32 - 1112U, // VABDLuv8i16 - 70705U, // VABDfd - 70705U, // VABDfq - 70705U, // VABDhd - 70705U, // VABDhq - 1112U, // VABDsv16i8 - 1112U, // VABDsv2i32 - 1112U, // VABDsv4i16 - 1112U, // VABDsv4i32 - 1112U, // VABDsv8i16 - 1112U, // VABDsv8i8 - 1112U, // VABDuv16i8 - 1112U, // VABDuv2i32 - 1112U, // VABDuv4i16 - 1112U, // VABDuv4i32 - 1112U, // VABDuv8i16 - 1112U, // VABDuv8i8 - 33U, // VABSD - 33U, // VABSH - 33U, // VABSS - 33U, // VABSfd - 33U, // VABSfq - 33U, // VABShd - 33U, // VABShq - 0U, // VABSv16i8 - 0U, // VABSv2i32 - 0U, // VABSv4i16 - 0U, // VABSv4i32 - 0U, // VABSv8i16 - 0U, // VABSv8i8 - 70705U, // VACGEfd - 70705U, // VACGEfq - 70705U, // VACGEhd - 70705U, // VACGEhq - 70705U, // VACGTfd - 70705U, // VACGTfq - 70705U, // VACGThd - 70705U, // VACGThq - 70705U, // VADDD - 70705U, // VADDH - 1112U, // VADDHNv2i32 - 1112U, // VADDHNv4i16 - 1112U, // VADDHNv8i8 - 1112U, // VADDLsv2i64 - 1112U, // VADDLsv4i32 - 1112U, // VADDLsv8i16 - 1112U, // VADDLuv2i64 - 1112U, // VADDLuv4i32 - 1112U, // VADDLuv8i16 - 70705U, // VADDS - 1112U, // VADDWsv2i64 - 1112U, // VADDWsv4i32 - 1112U, // VADDWsv8i16 - 1112U, // VADDWuv2i64 - 1112U, // VADDWuv4i32 - 1112U, // VADDWuv8i16 - 70705U, // VADDfd - 70705U, // VADDfq - 70705U, // VADDhd - 70705U, // VADDhq - 1112U, // VADDv16i8 - 1112U, // VADDv1i64 - 1112U, // VADDv2i32 - 1112U, // VADDv2i64 - 1112U, // VADDv4i16 - 1112U, // VADDv4i32 - 1112U, // VADDv8i16 - 1112U, // VADDv8i8 - 0U, // VANDd - 0U, // VANDq - 0U, // VBICd - 0U, // VBICiv2i32 - 0U, // VBICiv4i16 - 0U, // VBICiv4i32 - 0U, // VBICiv8i16 - 0U, // VBICq - 589912U, // VBIFd - 589912U, // VBIFq - 589912U, // VBITd - 589912U, // VBITq - 589912U, // VBSLd - 589912U, // VBSLq - 622680U, // VCADDv2f32 - 622680U, // VCADDv4f16 - 622680U, // VCADDv4f32 - 622680U, // VCADDv8f16 - 70705U, // VCEQfd - 70705U, // VCEQfq - 70705U, // VCEQhd - 70705U, // VCEQhq - 1112U, // VCEQv16i8 - 1112U, // VCEQv2i32 - 1112U, // VCEQv4i16 - 1112U, // VCEQv4i32 - 1112U, // VCEQv8i16 - 1112U, // VCEQv8i8 - 3U, // VCEQzv16i8 - 225U, // VCEQzv2f32 - 3U, // VCEQzv2i32 - 225U, // VCEQzv4f16 - 225U, // VCEQzv4f32 - 3U, // VCEQzv4i16 - 3U, // VCEQzv4i32 - 225U, // VCEQzv8f16 - 3U, // VCEQzv8i16 - 3U, // VCEQzv8i8 - 70705U, // VCGEfd - 70705U, // VCGEfq - 70705U, // VCGEhd - 70705U, // VCGEhq - 1112U, // VCGEsv16i8 - 1112U, // VCGEsv2i32 - 1112U, // VCGEsv4i16 - 1112U, // VCGEsv4i32 - 1112U, // VCGEsv8i16 - 1112U, // VCGEsv8i8 - 1112U, // VCGEuv16i8 - 1112U, // VCGEuv2i32 - 1112U, // VCGEuv4i16 - 1112U, // VCGEuv4i32 - 1112U, // VCGEuv8i16 - 1112U, // VCGEuv8i8 - 3U, // VCGEzv16i8 - 225U, // VCGEzv2f32 - 3U, // VCGEzv2i32 - 225U, // VCGEzv4f16 - 225U, // VCGEzv4f32 - 3U, // VCGEzv4i16 - 3U, // VCGEzv4i32 - 225U, // VCGEzv8f16 - 3U, // VCGEzv8i16 - 3U, // VCGEzv8i8 - 70705U, // VCGTfd - 70705U, // VCGTfq - 70705U, // VCGThd - 70705U, // VCGThq - 1112U, // VCGTsv16i8 - 1112U, // VCGTsv2i32 - 1112U, // VCGTsv4i16 - 1112U, // VCGTsv4i32 - 1112U, // VCGTsv8i16 - 1112U, // VCGTsv8i8 - 1112U, // VCGTuv16i8 - 1112U, // VCGTuv2i32 - 1112U, // VCGTuv4i16 - 1112U, // VCGTuv4i32 - 1112U, // VCGTuv8i16 - 1112U, // VCGTuv8i8 - 3U, // VCGTzv16i8 - 225U, // VCGTzv2f32 - 3U, // VCGTzv2i32 - 225U, // VCGTzv4f16 - 225U, // VCGTzv4f32 - 3U, // VCGTzv4i16 - 3U, // VCGTzv4i32 - 225U, // VCGTzv8f16 - 3U, // VCGTzv8i16 - 3U, // VCGTzv8i8 - 3U, // VCLEzv16i8 - 225U, // VCLEzv2f32 - 3U, // VCLEzv2i32 - 225U, // VCLEzv4f16 - 225U, // VCLEzv4f32 - 3U, // VCLEzv4i16 - 3U, // VCLEzv4i32 - 225U, // VCLEzv8f16 - 3U, // VCLEzv8i16 - 3U, // VCLEzv8i8 - 0U, // VCLSv16i8 - 0U, // VCLSv2i32 - 0U, // VCLSv4i16 - 0U, // VCLSv4i32 - 0U, // VCLSv8i16 - 0U, // VCLSv8i8 - 3U, // VCLTzv16i8 - 225U, // VCLTzv2f32 - 3U, // VCLTzv2i32 - 225U, // VCLTzv4f16 - 225U, // VCLTzv4f32 - 3U, // VCLTzv4i16 - 3U, // VCLTzv4i32 - 225U, // VCLTzv8f16 - 3U, // VCLTzv8i16 - 3U, // VCLTzv8i8 - 0U, // VCLZv16i8 - 0U, // VCLZv2i32 - 0U, // VCLZv4i16 - 0U, // VCLZv4i32 - 0U, // VCLZv8i16 - 0U, // VCLZv8i8 - 655384U, // VCMLAv2f32 - 17276952U, // VCMLAv2f32_indexed - 655384U, // VCMLAv4f16 - 17276952U, // VCMLAv4f16_indexed - 655384U, // VCMLAv4f32 - 17276952U, // VCMLAv4f32_indexed - 655384U, // VCMLAv8f16 - 17276952U, // VCMLAv8f16_indexed - 33U, // VCMPD - 33U, // VCMPED - 33U, // VCMPEH - 33U, // VCMPES - 0U, // VCMPEZD - 0U, // VCMPEZH - 0U, // VCMPEZS - 33U, // VCMPH - 33U, // VCMPS - 0U, // VCMPZD - 0U, // VCMPZH - 0U, // VCMPZS - 1024U, // VCNTd - 1024U, // VCNTq - 0U, // VCVTANSDf - 0U, // VCVTANSDh - 0U, // VCVTANSQf - 0U, // VCVTANSQh - 0U, // VCVTANUDf - 0U, // VCVTANUDh - 0U, // VCVTANUQf - 0U, // VCVTANUQh - 0U, // VCVTASD - 0U, // VCVTASH - 0U, // VCVTASS - 0U, // VCVTAUD - 0U, // VCVTAUH - 0U, // VCVTAUS - 0U, // VCVTBDH - 0U, // VCVTBHD - 0U, // VCVTBHS - 0U, // VCVTBSH - 0U, // VCVTDS - 0U, // VCVTMNSDf - 0U, // VCVTMNSDh - 0U, // VCVTMNSQf - 0U, // VCVTMNSQh - 0U, // VCVTMNUDf - 0U, // VCVTMNUDh - 0U, // VCVTMNUQf - 0U, // VCVTMNUQh - 0U, // VCVTMSD - 0U, // VCVTMSH - 0U, // VCVTMSS - 0U, // VCVTMUD - 0U, // VCVTMUH - 0U, // VCVTMUS - 0U, // VCVTNNSDf - 0U, // VCVTNNSDh - 0U, // VCVTNNSQf - 0U, // VCVTNNSQh - 0U, // VCVTNNUDf - 0U, // VCVTNNUDh - 0U, // VCVTNNUQf - 0U, // VCVTNNUQh - 0U, // VCVTNSD - 0U, // VCVTNSH - 0U, // VCVTNSS - 0U, // VCVTNUD - 0U, // VCVTNUH - 0U, // VCVTNUS - 0U, // VCVTPNSDf - 0U, // VCVTPNSDh - 0U, // VCVTPNSQf - 0U, // VCVTPNSQh - 0U, // VCVTPNUDf - 0U, // VCVTPNUDh - 0U, // VCVTPNUQf - 0U, // VCVTPNUQh - 0U, // VCVTPSD - 0U, // VCVTPSH - 0U, // VCVTPSS - 0U, // VCVTPUD - 0U, // VCVTPUH - 0U, // VCVTPUS - 0U, // VCVTSD - 0U, // VCVTTDH - 0U, // VCVTTHD - 0U, // VCVTTHS - 0U, // VCVTTSH - 0U, // VCVTf2h - 0U, // VCVTf2sd - 0U, // VCVTf2sq - 0U, // VCVTf2ud - 0U, // VCVTf2uq - 35U, // VCVTf2xsd - 35U, // VCVTf2xsq - 35U, // VCVTf2xud - 35U, // VCVTf2xuq - 0U, // VCVTh2f - 0U, // VCVTh2sd - 0U, // VCVTh2sq - 0U, // VCVTh2ud - 0U, // VCVTh2uq - 35U, // VCVTh2xsd - 35U, // VCVTh2xsq - 35U, // VCVTh2xud - 35U, // VCVTh2xuq - 0U, // VCVTs2fd - 0U, // VCVTs2fq - 0U, // VCVTs2hd - 0U, // VCVTs2hq - 0U, // VCVTu2fd - 0U, // VCVTu2fq - 0U, // VCVTu2hd - 0U, // VCVTu2hq - 35U, // VCVTxs2fd - 35U, // VCVTxs2fq - 35U, // VCVTxs2hd - 35U, // VCVTxs2hq - 35U, // VCVTxu2fd - 35U, // VCVTxu2fq - 35U, // VCVTxu2hd - 35U, // VCVTxu2hq - 70705U, // VDIVD - 70705U, // VDIVH - 70705U, // VDIVS - 1024U, // VDUP16d - 1024U, // VDUP16q - 1024U, // VDUP32d - 1024U, // VDUP32q - 1024U, // VDUP8d - 1024U, // VDUP8q - 9216U, // VDUPLN16d - 9216U, // VDUPLN16q - 9216U, // VDUPLN32d - 9216U, // VDUPLN32q - 9216U, // VDUPLN8d - 9216U, // VDUPLN8q - 0U, // VEORd - 0U, // VEORq - 35651584U, // VEXTd16 - 35651584U, // VEXTd32 - 35651584U, // VEXTd8 - 35651584U, // VEXTq16 - 35651584U, // VEXTq32 - 35651584U, // VEXTq64 - 35651584U, // VEXTq8 - 68659U, // VFMAD - 68659U, // VFMAH - 68659U, // VFMAS - 68659U, // VFMAfd - 68659U, // VFMAfq - 68659U, // VFMAhd - 68659U, // VFMAhq - 68659U, // VFMSD - 68659U, // VFMSH - 68659U, // VFMSS - 68659U, // VFMSfd - 68659U, // VFMSfq - 68659U, // VFMShd - 68659U, // VFMShq - 68659U, // VFNMAD - 68659U, // VFNMAH - 68659U, // VFNMAS - 68659U, // VFNMSD - 68659U, // VFNMSH - 68659U, // VFNMSS - 9216U, // VGETLNi32 - 3U, // VGETLNs16 - 3U, // VGETLNs8 - 3U, // VGETLNu16 - 3U, // VGETLNu8 - 1112U, // VHADDsv16i8 - 1112U, // VHADDsv2i32 - 1112U, // VHADDsv4i16 - 1112U, // VHADDsv4i32 - 1112U, // VHADDsv8i16 - 1112U, // VHADDsv8i8 - 1112U, // VHADDuv16i8 - 1112U, // VHADDuv2i32 - 1112U, // VHADDuv4i16 - 1112U, // VHADDuv4i32 - 1112U, // VHADDuv8i16 - 1112U, // VHADDuv8i8 - 1112U, // VHSUBsv16i8 - 1112U, // VHSUBsv2i32 - 1112U, // VHSUBsv4i16 - 1112U, // VHSUBsv4i32 - 1112U, // VHSUBsv8i16 - 1112U, // VHSUBsv8i8 - 1112U, // VHSUBuv16i8 - 1112U, // VHSUBuv2i32 - 1112U, // VHSUBuv4i16 - 1112U, // VHSUBuv4i32 - 1112U, // VHSUBuv8i16 - 1112U, // VHSUBuv8i8 - 0U, // VINSH - 0U, // VJCVT - 32U, // VLD1DUPd16 - 44U, // VLD1DUPd16wb_fixed - 10292U, // VLD1DUPd16wb_register - 32U, // VLD1DUPd32 - 44U, // VLD1DUPd32wb_fixed - 10292U, // VLD1DUPd32wb_register - 32U, // VLD1DUPd8 - 44U, // VLD1DUPd8wb_fixed - 10292U, // VLD1DUPd8wb_register - 32U, // VLD1DUPq16 - 44U, // VLD1DUPq16wb_fixed - 10292U, // VLD1DUPq16wb_register - 32U, // VLD1DUPq32 - 44U, // VLD1DUPq32wb_fixed - 10292U, // VLD1DUPq32wb_register - 32U, // VLD1DUPq8 - 44U, // VLD1DUPq8wb_fixed - 10292U, // VLD1DUPq8wb_register - 699628U, // VLD1LNd16 - 732404U, // VLD1LNd16_UPD - 699628U, // VLD1LNd32 - 732404U, // VLD1LNd32_UPD - 699628U, // VLD1LNd8 - 732404U, // VLD1LNd8_UPD - 0U, // VLD1LNq16Pseudo - 0U, // VLD1LNq16Pseudo_UPD - 0U, // VLD1LNq32Pseudo - 0U, // VLD1LNq32Pseudo_UPD - 0U, // VLD1LNq8Pseudo - 0U, // VLD1LNq8Pseudo_UPD - 32U, // VLD1d16 - 32U, // VLD1d16Q - 0U, // VLD1d16QPseudo - 44U, // VLD1d16Qwb_fixed - 10292U, // VLD1d16Qwb_register - 32U, // VLD1d16T - 0U, // VLD1d16TPseudo - 44U, // VLD1d16Twb_fixed - 10292U, // VLD1d16Twb_register - 44U, // VLD1d16wb_fixed - 10292U, // VLD1d16wb_register - 32U, // VLD1d32 - 32U, // VLD1d32Q - 0U, // VLD1d32QPseudo - 44U, // VLD1d32Qwb_fixed - 10292U, // VLD1d32Qwb_register - 32U, // VLD1d32T - 0U, // VLD1d32TPseudo - 44U, // VLD1d32Twb_fixed - 10292U, // VLD1d32Twb_register - 44U, // VLD1d32wb_fixed - 10292U, // VLD1d32wb_register - 32U, // VLD1d64 - 32U, // VLD1d64Q - 0U, // VLD1d64QPseudo - 0U, // VLD1d64QPseudoWB_fixed - 0U, // VLD1d64QPseudoWB_register - 44U, // VLD1d64Qwb_fixed - 10292U, // VLD1d64Qwb_register - 32U, // VLD1d64T - 0U, // VLD1d64TPseudo - 0U, // VLD1d64TPseudoWB_fixed - 0U, // VLD1d64TPseudoWB_register - 44U, // VLD1d64Twb_fixed - 10292U, // VLD1d64Twb_register - 44U, // VLD1d64wb_fixed - 10292U, // VLD1d64wb_register - 32U, // VLD1d8 - 32U, // VLD1d8Q - 0U, // VLD1d8QPseudo - 44U, // VLD1d8Qwb_fixed - 10292U, // VLD1d8Qwb_register - 32U, // VLD1d8T - 0U, // VLD1d8TPseudo - 44U, // VLD1d8Twb_fixed - 10292U, // VLD1d8Twb_register - 44U, // VLD1d8wb_fixed - 10292U, // VLD1d8wb_register - 32U, // VLD1q16 - 0U, // VLD1q16HighQPseudo - 0U, // VLD1q16HighTPseudo - 0U, // VLD1q16LowQPseudo_UPD - 0U, // VLD1q16LowTPseudo_UPD - 44U, // VLD1q16wb_fixed - 10292U, // VLD1q16wb_register - 32U, // VLD1q32 - 0U, // VLD1q32HighQPseudo - 0U, // VLD1q32HighTPseudo - 0U, // VLD1q32LowQPseudo_UPD - 0U, // VLD1q32LowTPseudo_UPD - 44U, // VLD1q32wb_fixed - 10292U, // VLD1q32wb_register - 32U, // VLD1q64 - 0U, // VLD1q64HighQPseudo - 0U, // VLD1q64HighTPseudo - 0U, // VLD1q64LowQPseudo_UPD - 0U, // VLD1q64LowTPseudo_UPD - 44U, // VLD1q64wb_fixed - 10292U, // VLD1q64wb_register - 32U, // VLD1q8 - 0U, // VLD1q8HighQPseudo - 0U, // VLD1q8HighTPseudo - 0U, // VLD1q8LowQPseudo_UPD - 0U, // VLD1q8LowTPseudo_UPD - 44U, // VLD1q8wb_fixed - 10292U, // VLD1q8wb_register - 32U, // VLD2DUPd16 - 44U, // VLD2DUPd16wb_fixed - 10292U, // VLD2DUPd16wb_register - 32U, // VLD2DUPd16x2 - 44U, // VLD2DUPd16x2wb_fixed - 10292U, // VLD2DUPd16x2wb_register - 32U, // VLD2DUPd32 - 44U, // VLD2DUPd32wb_fixed - 10292U, // VLD2DUPd32wb_register - 32U, // VLD2DUPd32x2 - 44U, // VLD2DUPd32x2wb_fixed - 10292U, // VLD2DUPd32x2wb_register - 32U, // VLD2DUPd8 - 44U, // VLD2DUPd8wb_fixed - 10292U, // VLD2DUPd8wb_register - 32U, // VLD2DUPd8x2 - 44U, // VLD2DUPd8x2wb_fixed - 10292U, // VLD2DUPd8x2wb_register - 0U, // VLD2DUPq16EvenPseudo - 0U, // VLD2DUPq16OddPseudo - 0U, // VLD2DUPq32EvenPseudo - 0U, // VLD2DUPq32OddPseudo - 0U, // VLD2DUPq8EvenPseudo - 0U, // VLD2DUPq8OddPseudo - 766196U, // VLD2LNd16 - 0U, // VLD2LNd16Pseudo - 0U, // VLD2LNd16Pseudo_UPD - 799996U, // VLD2LNd16_UPD - 766196U, // VLD2LNd32 - 0U, // VLD2LNd32Pseudo - 0U, // VLD2LNd32Pseudo_UPD - 799996U, // VLD2LNd32_UPD - 766196U, // VLD2LNd8 - 0U, // VLD2LNd8Pseudo - 0U, // VLD2LNd8Pseudo_UPD - 799996U, // VLD2LNd8_UPD - 766196U, // VLD2LNq16 - 0U, // VLD2LNq16Pseudo - 0U, // VLD2LNq16Pseudo_UPD - 799996U, // VLD2LNq16_UPD - 766196U, // VLD2LNq32 - 0U, // VLD2LNq32Pseudo - 0U, // VLD2LNq32Pseudo_UPD - 799996U, // VLD2LNq32_UPD - 32U, // VLD2b16 - 44U, // VLD2b16wb_fixed - 10292U, // VLD2b16wb_register - 32U, // VLD2b32 - 44U, // VLD2b32wb_fixed - 10292U, // VLD2b32wb_register - 32U, // VLD2b8 - 44U, // VLD2b8wb_fixed - 10292U, // VLD2b8wb_register - 32U, // VLD2d16 - 44U, // VLD2d16wb_fixed - 10292U, // VLD2d16wb_register - 32U, // VLD2d32 - 44U, // VLD2d32wb_fixed - 10292U, // VLD2d32wb_register - 32U, // VLD2d8 - 44U, // VLD2d8wb_fixed - 10292U, // VLD2d8wb_register - 32U, // VLD2q16 - 0U, // VLD2q16Pseudo - 0U, // VLD2q16PseudoWB_fixed - 0U, // VLD2q16PseudoWB_register - 44U, // VLD2q16wb_fixed - 10292U, // VLD2q16wb_register - 32U, // VLD2q32 - 0U, // VLD2q32Pseudo - 0U, // VLD2q32PseudoWB_fixed - 0U, // VLD2q32PseudoWB_register - 44U, // VLD2q32wb_fixed - 10292U, // VLD2q32wb_register - 32U, // VLD2q8 - 0U, // VLD2q8Pseudo - 0U, // VLD2q8PseudoWB_fixed - 0U, // VLD2q8PseudoWB_register - 44U, // VLD2q8wb_fixed - 10292U, // VLD2q8wb_register - 14596U, // VLD3DUPd16 - 0U, // VLD3DUPd16Pseudo - 0U, // VLD3DUPd16Pseudo_UPD - 834820U, // VLD3DUPd16_UPD - 14596U, // VLD3DUPd32 - 0U, // VLD3DUPd32Pseudo - 0U, // VLD3DUPd32Pseudo_UPD - 834820U, // VLD3DUPd32_UPD - 14596U, // VLD3DUPd8 - 0U, // VLD3DUPd8Pseudo - 0U, // VLD3DUPd8Pseudo_UPD - 834820U, // VLD3DUPd8_UPD - 14596U, // VLD3DUPq16 - 0U, // VLD3DUPq16EvenPseudo - 0U, // VLD3DUPq16OddPseudo - 834820U, // VLD3DUPq16_UPD - 14596U, // VLD3DUPq32 - 0U, // VLD3DUPq32EvenPseudo - 0U, // VLD3DUPq32OddPseudo - 834820U, // VLD3DUPq32_UPD - 14596U, // VLD3DUPq8 - 0U, // VLD3DUPq8EvenPseudo - 0U, // VLD3DUPq8OddPseudo - 834820U, // VLD3DUPq8_UPD - 865532U, // VLD3LNd16 - 0U, // VLD3LNd16Pseudo - 0U, // VLD3LNd16Pseudo_UPD - 896268U, // VLD3LNd16_UPD - 865532U, // VLD3LNd32 - 0U, // VLD3LNd32Pseudo - 0U, // VLD3LNd32Pseudo_UPD - 896268U, // VLD3LNd32_UPD - 865532U, // VLD3LNd8 - 0U, // VLD3LNd8Pseudo - 0U, // VLD3LNd8Pseudo_UPD - 896268U, // VLD3LNd8_UPD - 865532U, // VLD3LNq16 - 0U, // VLD3LNq16Pseudo - 0U, // VLD3LNq16Pseudo_UPD - 896268U, // VLD3LNq16_UPD - 865532U, // VLD3LNq32 - 0U, // VLD3LNq32Pseudo - 0U, // VLD3LNq32Pseudo_UPD - 896268U, // VLD3LNq32_UPD - 119537664U, // VLD3d16 - 0U, // VLD3d16Pseudo - 0U, // VLD3d16Pseudo_UPD - 153092096U, // VLD3d16_UPD - 119537664U, // VLD3d32 - 0U, // VLD3d32Pseudo - 0U, // VLD3d32Pseudo_UPD - 153092096U, // VLD3d32_UPD - 119537664U, // VLD3d8 - 0U, // VLD3d8Pseudo - 0U, // VLD3d8Pseudo_UPD - 153092096U, // VLD3d8_UPD - 119537664U, // VLD3q16 - 0U, // VLD3q16Pseudo_UPD - 153092096U, // VLD3q16_UPD - 0U, // VLD3q16oddPseudo - 0U, // VLD3q16oddPseudo_UPD - 119537664U, // VLD3q32 - 0U, // VLD3q32Pseudo_UPD - 153092096U, // VLD3q32_UPD - 0U, // VLD3q32oddPseudo - 0U, // VLD3q32oddPseudo_UPD - 119537664U, // VLD3q8 - 0U, // VLD3q8Pseudo_UPD - 153092096U, // VLD3q8_UPD - 0U, // VLD3q8oddPseudo - 0U, // VLD3q8oddPseudo_UPD - 81172U, // VLD4DUPd16 - 0U, // VLD4DUPd16Pseudo - 0U, // VLD4DUPd16Pseudo_UPD - 16660U, // VLD4DUPd16_UPD - 81172U, // VLD4DUPd32 - 0U, // VLD4DUPd32Pseudo - 0U, // VLD4DUPd32Pseudo_UPD - 16660U, // VLD4DUPd32_UPD - 81172U, // VLD4DUPd8 - 0U, // VLD4DUPd8Pseudo - 0U, // VLD4DUPd8Pseudo_UPD - 16660U, // VLD4DUPd8_UPD - 81172U, // VLD4DUPq16 - 0U, // VLD4DUPq16EvenPseudo - 0U, // VLD4DUPq16OddPseudo - 16660U, // VLD4DUPq16_UPD - 81172U, // VLD4DUPq32 - 0U, // VLD4DUPq32EvenPseudo - 0U, // VLD4DUPq32OddPseudo - 16660U, // VLD4DUPq32_UPD - 81172U, // VLD4DUPq8 - 0U, // VLD4DUPq8EvenPseudo - 0U, // VLD4DUPq8OddPseudo - 16660U, // VLD4DUPq8_UPD - 189346060U, // VLD4LNd16 - 0U, // VLD4LNd16Pseudo - 0U, // VLD4LNd16Pseudo_UPD - 284U, // VLD4LNd16_UPD - 189346060U, // VLD4LNd32 - 0U, // VLD4LNd32Pseudo - 0U, // VLD4LNd32Pseudo_UPD - 284U, // VLD4LNd32_UPD - 189346060U, // VLD4LNd8 - 0U, // VLD4LNd8Pseudo - 0U, // VLD4LNd8Pseudo_UPD - 284U, // VLD4LNd8_UPD - 189346060U, // VLD4LNq16 - 0U, // VLD4LNq16Pseudo - 0U, // VLD4LNq16Pseudo_UPD - 284U, // VLD4LNq16_UPD - 189346060U, // VLD4LNq32 - 0U, // VLD4LNq32Pseudo - 0U, // VLD4LNq32Pseudo_UPD - 284U, // VLD4LNq32_UPD - 572522496U, // VLD4d16 - 0U, // VLD4d16Pseudo - 0U, // VLD4d16Pseudo_UPD - 1646264320U, // VLD4d16_UPD - 572522496U, // VLD4d32 - 0U, // VLD4d32Pseudo - 0U, // VLD4d32Pseudo_UPD - 1646264320U, // VLD4d32_UPD - 572522496U, // VLD4d8 - 0U, // VLD4d8Pseudo - 0U, // VLD4d8Pseudo_UPD - 1646264320U, // VLD4d8_UPD - 572522496U, // VLD4q16 - 0U, // VLD4q16Pseudo_UPD - 1646264320U, // VLD4q16_UPD - 0U, // VLD4q16oddPseudo - 0U, // VLD4q16oddPseudo_UPD - 572522496U, // VLD4q32 - 0U, // VLD4q32Pseudo_UPD - 1646264320U, // VLD4q32_UPD - 0U, // VLD4q32oddPseudo - 0U, // VLD4q32oddPseudo_UPD - 572522496U, // VLD4q8 - 0U, // VLD4q8Pseudo_UPD - 1646264320U, // VLD4q8_UPD - 0U, // VLD4q8oddPseudo - 0U, // VLD4q8oddPseudo_UPD - 33U, // VLDMDDB_UPD - 1136U, // VLDMDIA - 33U, // VLDMDIA_UPD - 0U, // VLDMQIA - 33U, // VLDMSDB_UPD - 1136U, // VLDMSIA - 33U, // VLDMSIA_UPD - 288U, // VLDRD - 296U, // VLDRH - 288U, // VLDRS - 0U, // VLLDM - 0U, // VLSTM - 1112U, // VMAXNMD - 1112U, // VMAXNMH - 1112U, // VMAXNMNDf - 1112U, // VMAXNMNDh - 1112U, // VMAXNMNQf - 1112U, // VMAXNMNQh - 1112U, // VMAXNMS - 70705U, // VMAXfd - 70705U, // VMAXfq - 70705U, // VMAXhd - 70705U, // VMAXhq - 1112U, // VMAXsv16i8 - 1112U, // VMAXsv2i32 - 1112U, // VMAXsv4i16 - 1112U, // VMAXsv4i32 - 1112U, // VMAXsv8i16 - 1112U, // VMAXsv8i8 - 1112U, // VMAXuv16i8 - 1112U, // VMAXuv2i32 - 1112U, // VMAXuv4i16 - 1112U, // VMAXuv4i32 - 1112U, // VMAXuv8i16 - 1112U, // VMAXuv8i8 - 1112U, // VMINNMD - 1112U, // VMINNMH - 1112U, // VMINNMNDf - 1112U, // VMINNMNDh - 1112U, // VMINNMNQf - 1112U, // VMINNMNQh - 1112U, // VMINNMS - 70705U, // VMINfd - 70705U, // VMINfq - 70705U, // VMINhd - 70705U, // VMINhq - 1112U, // VMINsv16i8 - 1112U, // VMINsv2i32 - 1112U, // VMINsv4i16 - 1112U, // VMINsv4i32 - 1112U, // VMINsv8i16 - 1112U, // VMINsv8i8 - 1112U, // VMINuv16i8 - 1112U, // VMINuv2i32 - 1112U, // VMINuv4i16 - 1112U, // VMINuv4i32 - 1112U, // VMINuv8i16 - 1112U, // VMINuv8i8 - 68659U, // VMLAD - 68659U, // VMLAH - 73752U, // VMLALslsv2i32 - 73752U, // VMLALslsv4i16 - 73752U, // VMLALsluv2i32 - 73752U, // VMLALsluv4i16 - 1048U, // VMLALsv2i64 - 1048U, // VMLALsv4i32 - 1048U, // VMLALsv8i16 - 1048U, // VMLALuv2i64 - 1048U, // VMLALuv4i32 - 1048U, // VMLALuv8i16 - 68659U, // VMLAS - 68659U, // VMLAfd - 68659U, // VMLAfq - 68659U, // VMLAhd - 68659U, // VMLAhq - 920627U, // VMLAslfd - 920627U, // VMLAslfq - 920627U, // VMLAslhd - 920627U, // VMLAslhq - 73752U, // VMLAslv2i32 - 73752U, // VMLAslv4i16 - 73752U, // VMLAslv4i32 - 73752U, // VMLAslv8i16 - 1048U, // VMLAv16i8 - 1048U, // VMLAv2i32 - 1048U, // VMLAv4i16 - 1048U, // VMLAv4i32 - 1048U, // VMLAv8i16 - 1048U, // VMLAv8i8 - 68659U, // VMLSD - 68659U, // VMLSH - 73752U, // VMLSLslsv2i32 - 73752U, // VMLSLslsv4i16 - 73752U, // VMLSLsluv2i32 - 73752U, // VMLSLsluv4i16 - 1048U, // VMLSLsv2i64 - 1048U, // VMLSLsv4i32 - 1048U, // VMLSLsv8i16 - 1048U, // VMLSLuv2i64 - 1048U, // VMLSLuv4i32 - 1048U, // VMLSLuv8i16 - 68659U, // VMLSS - 68659U, // VMLSfd - 68659U, // VMLSfq - 68659U, // VMLShd - 68659U, // VMLShq - 920627U, // VMLSslfd - 920627U, // VMLSslfq - 920627U, // VMLSslhd - 920627U, // VMLSslhq - 73752U, // VMLSslv2i32 - 73752U, // VMLSslv4i16 - 73752U, // VMLSslv4i32 - 73752U, // VMLSslv8i16 - 1048U, // VMLSv16i8 - 1048U, // VMLSv2i32 - 1048U, // VMLSv4i16 - 1048U, // VMLSv4i32 - 1048U, // VMLSv8i16 - 1048U, // VMLSv8i8 - 33U, // VMOVD - 0U, // VMOVDRR - 0U, // VMOVH - 33U, // VMOVHR - 0U, // VMOVLsv2i64 - 0U, // VMOVLsv4i32 - 0U, // VMOVLsv8i16 - 0U, // VMOVLuv2i64 - 0U, // VMOVLuv4i32 - 0U, // VMOVLuv8i16 - 0U, // VMOVNv2i32 - 0U, // VMOVNv4i16 - 0U, // VMOVNv8i8 - 33U, // VMOVRH - 0U, // VMOVRRD - 35651584U, // VMOVRRS - 1024U, // VMOVRS - 33U, // VMOVS - 1024U, // VMOVSR - 35651584U, // VMOVSRR - 0U, // VMOVv16i8 - 0U, // VMOVv1i64 - 1U, // VMOVv2f32 - 0U, // VMOVv2i32 - 0U, // VMOVv2i64 - 1U, // VMOVv4f32 - 0U, // VMOVv4i16 - 0U, // VMOVv4i32 - 0U, // VMOVv8i16 - 0U, // VMOVv8i8 - 4U, // VMRS - 5U, // VMRS_FPEXC - 5U, // VMRS_FPINST - 5U, // VMRS_FPINST2 - 5U, // VMRS_FPSID - 6U, // VMRS_MVFR0 - 6U, // VMRS_MVFR1 - 6U, // VMRS_MVFR2 - 0U, // VMSR - 0U, // VMSR_FPEXC - 0U, // VMSR_FPINST - 0U, // VMSR_FPINST2 - 0U, // VMSR_FPSID - 70705U, // VMULD - 70705U, // VMULH - 1112U, // VMULLp64 - 0U, // VMULLp8 - 17496U, // VMULLslsv2i32 - 17496U, // VMULLslsv4i16 - 17496U, // VMULLsluv2i32 - 17496U, // VMULLsluv4i16 - 1112U, // VMULLsv2i64 - 1112U, // VMULLsv4i32 - 1112U, // VMULLsv8i16 - 1112U, // VMULLuv2i64 - 1112U, // VMULLuv4i32 - 1112U, // VMULLuv8i16 - 70705U, // VMULS - 70705U, // VMULfd - 70705U, // VMULfq - 70705U, // VMULhd - 70705U, // VMULhq - 0U, // VMULpd - 0U, // VMULpq - 955441U, // VMULslfd - 955441U, // VMULslfq - 955441U, // VMULslhd - 955441U, // VMULslhq - 17496U, // VMULslv2i32 - 17496U, // VMULslv4i16 - 17496U, // VMULslv4i32 - 17496U, // VMULslv8i16 - 1112U, // VMULv16i8 - 1112U, // VMULv2i32 - 1112U, // VMULv4i16 - 1112U, // VMULv4i32 - 1112U, // VMULv8i16 - 1112U, // VMULv8i8 - 1024U, // VMVNd - 1024U, // VMVNq - 0U, // VMVNv2i32 - 0U, // VMVNv4i16 - 0U, // VMVNv4i32 - 0U, // VMVNv8i16 - 33U, // VNEGD - 33U, // VNEGH - 33U, // VNEGS - 33U, // VNEGf32q - 33U, // VNEGfd - 33U, // VNEGhd - 33U, // VNEGhq - 0U, // VNEGs16d - 0U, // VNEGs16q - 0U, // VNEGs32d - 0U, // VNEGs32q - 0U, // VNEGs8d - 0U, // VNEGs8q - 68659U, // VNMLAD - 68659U, // VNMLAH - 68659U, // VNMLAS - 68659U, // VNMLSD - 68659U, // VNMLSH - 68659U, // VNMLSS - 70705U, // VNMULD - 70705U, // VNMULH - 70705U, // VNMULS - 0U, // VORNd - 0U, // VORNq - 0U, // VORRd - 0U, // VORRiv2i32 - 0U, // VORRiv4i16 - 0U, // VORRiv4i32 - 0U, // VORRiv8i16 - 0U, // VORRq - 0U, // VPADALsv16i8 - 0U, // VPADALsv2i32 - 0U, // VPADALsv4i16 - 0U, // VPADALsv4i32 - 0U, // VPADALsv8i16 - 0U, // VPADALsv8i8 - 0U, // VPADALuv16i8 - 0U, // VPADALuv2i32 - 0U, // VPADALuv4i16 - 0U, // VPADALuv4i32 - 0U, // VPADALuv8i16 - 0U, // VPADALuv8i8 - 0U, // VPADDLsv16i8 - 0U, // VPADDLsv2i32 - 0U, // VPADDLsv4i16 - 0U, // VPADDLsv4i32 - 0U, // VPADDLsv8i16 - 0U, // VPADDLsv8i8 - 0U, // VPADDLuv16i8 - 0U, // VPADDLuv2i32 - 0U, // VPADDLuv4i16 - 0U, // VPADDLuv4i32 - 0U, // VPADDLuv8i16 - 0U, // VPADDLuv8i8 - 70705U, // VPADDf - 70705U, // VPADDh - 1112U, // VPADDi16 - 1112U, // VPADDi32 - 1112U, // VPADDi8 - 70705U, // VPMAXf - 70705U, // VPMAXh - 1112U, // VPMAXs16 - 1112U, // VPMAXs32 - 1112U, // VPMAXs8 - 1112U, // VPMAXu16 - 1112U, // VPMAXu32 - 1112U, // VPMAXu8 - 70705U, // VPMINf - 70705U, // VPMINh - 1112U, // VPMINs16 - 1112U, // VPMINs32 - 1112U, // VPMINs8 - 1112U, // VPMINu16 - 1112U, // VPMINu32 - 1112U, // VPMINu8 - 0U, // VQABSv16i8 - 0U, // VQABSv2i32 - 0U, // VQABSv4i16 - 0U, // VQABSv4i32 - 0U, // VQABSv8i16 - 0U, // VQABSv8i8 - 1112U, // VQADDsv16i8 - 1112U, // VQADDsv1i64 - 1112U, // VQADDsv2i32 - 1112U, // VQADDsv2i64 - 1112U, // VQADDsv4i16 - 1112U, // VQADDsv4i32 - 1112U, // VQADDsv8i16 - 1112U, // VQADDsv8i8 - 1112U, // VQADDuv16i8 - 1112U, // VQADDuv1i64 - 1112U, // VQADDuv2i32 - 1112U, // VQADDuv2i64 - 1112U, // VQADDuv4i16 - 1112U, // VQADDuv4i32 - 1112U, // VQADDuv8i16 - 1112U, // VQADDuv8i8 - 73752U, // VQDMLALslv2i32 - 73752U, // VQDMLALslv4i16 - 1048U, // VQDMLALv2i64 - 1048U, // VQDMLALv4i32 - 73752U, // VQDMLSLslv2i32 - 73752U, // VQDMLSLslv4i16 - 1048U, // VQDMLSLv2i64 - 1048U, // VQDMLSLv4i32 - 17496U, // VQDMULHslv2i32 - 17496U, // VQDMULHslv4i16 - 17496U, // VQDMULHslv4i32 - 17496U, // VQDMULHslv8i16 - 1112U, // VQDMULHv2i32 - 1112U, // VQDMULHv4i16 - 1112U, // VQDMULHv4i32 - 1112U, // VQDMULHv8i16 - 17496U, // VQDMULLslv2i32 - 17496U, // VQDMULLslv4i16 - 1112U, // VQDMULLv2i64 - 1112U, // VQDMULLv4i32 - 0U, // VQMOVNsuv2i32 - 0U, // VQMOVNsuv4i16 - 0U, // VQMOVNsuv8i8 - 0U, // VQMOVNsv2i32 - 0U, // VQMOVNsv4i16 - 0U, // VQMOVNsv8i8 - 0U, // VQMOVNuv2i32 - 0U, // VQMOVNuv4i16 - 0U, // VQMOVNuv8i8 - 0U, // VQNEGv16i8 - 0U, // VQNEGv2i32 - 0U, // VQNEGv4i16 - 0U, // VQNEGv4i32 - 0U, // VQNEGv8i16 - 0U, // VQNEGv8i8 - 73752U, // VQRDMLAHslv2i32 - 73752U, // VQRDMLAHslv4i16 - 73752U, // VQRDMLAHslv4i32 - 73752U, // VQRDMLAHslv8i16 - 1048U, // VQRDMLAHv2i32 - 1048U, // VQRDMLAHv4i16 - 1048U, // VQRDMLAHv4i32 - 1048U, // VQRDMLAHv8i16 - 73752U, // VQRDMLSHslv2i32 - 73752U, // VQRDMLSHslv4i16 - 73752U, // VQRDMLSHslv4i32 - 73752U, // VQRDMLSHslv8i16 - 1048U, // VQRDMLSHv2i32 - 1048U, // VQRDMLSHv4i16 - 1048U, // VQRDMLSHv4i32 - 1048U, // VQRDMLSHv8i16 - 17496U, // VQRDMULHslv2i32 - 17496U, // VQRDMULHslv4i16 - 17496U, // VQRDMULHslv4i32 - 17496U, // VQRDMULHslv8i16 - 1112U, // VQRDMULHv2i32 - 1112U, // VQRDMULHv4i16 - 1112U, // VQRDMULHv4i32 - 1112U, // VQRDMULHv8i16 - 1112U, // VQRSHLsv16i8 - 1112U, // VQRSHLsv1i64 - 1112U, // VQRSHLsv2i32 - 1112U, // VQRSHLsv2i64 - 1112U, // VQRSHLsv4i16 - 1112U, // VQRSHLsv4i32 - 1112U, // VQRSHLsv8i16 - 1112U, // VQRSHLsv8i8 - 1112U, // VQRSHLuv16i8 - 1112U, // VQRSHLuv1i64 - 1112U, // VQRSHLuv2i32 - 1112U, // VQRSHLuv2i64 - 1112U, // VQRSHLuv4i16 - 1112U, // VQRSHLuv4i32 - 1112U, // VQRSHLuv8i16 - 1112U, // VQRSHLuv8i8 - 1112U, // VQRSHRNsv2i32 - 1112U, // VQRSHRNsv4i16 - 1112U, // VQRSHRNsv8i8 - 1112U, // VQRSHRNuv2i32 - 1112U, // VQRSHRNuv4i16 - 1112U, // VQRSHRNuv8i8 - 1112U, // VQRSHRUNv2i32 - 1112U, // VQRSHRUNv4i16 - 1112U, // VQRSHRUNv8i8 - 1112U, // VQSHLsiv16i8 - 1112U, // VQSHLsiv1i64 - 1112U, // VQSHLsiv2i32 - 1112U, // VQSHLsiv2i64 - 1112U, // VQSHLsiv4i16 - 1112U, // VQSHLsiv4i32 - 1112U, // VQSHLsiv8i16 - 1112U, // VQSHLsiv8i8 - 1112U, // VQSHLsuv16i8 - 1112U, // VQSHLsuv1i64 - 1112U, // VQSHLsuv2i32 - 1112U, // VQSHLsuv2i64 - 1112U, // VQSHLsuv4i16 - 1112U, // VQSHLsuv4i32 - 1112U, // VQSHLsuv8i16 - 1112U, // VQSHLsuv8i8 - 1112U, // VQSHLsv16i8 - 1112U, // VQSHLsv1i64 - 1112U, // VQSHLsv2i32 - 1112U, // VQSHLsv2i64 - 1112U, // VQSHLsv4i16 - 1112U, // VQSHLsv4i32 - 1112U, // VQSHLsv8i16 - 1112U, // VQSHLsv8i8 - 1112U, // VQSHLuiv16i8 - 1112U, // VQSHLuiv1i64 - 1112U, // VQSHLuiv2i32 - 1112U, // VQSHLuiv2i64 - 1112U, // VQSHLuiv4i16 - 1112U, // VQSHLuiv4i32 - 1112U, // VQSHLuiv8i16 - 1112U, // VQSHLuiv8i8 - 1112U, // VQSHLuv16i8 - 1112U, // VQSHLuv1i64 - 1112U, // VQSHLuv2i32 - 1112U, // VQSHLuv2i64 - 1112U, // VQSHLuv4i16 - 1112U, // VQSHLuv4i32 - 1112U, // VQSHLuv8i16 - 1112U, // VQSHLuv8i8 - 1112U, // VQSHRNsv2i32 - 1112U, // VQSHRNsv4i16 - 1112U, // VQSHRNsv8i8 - 1112U, // VQSHRNuv2i32 - 1112U, // VQSHRNuv4i16 - 1112U, // VQSHRNuv8i8 - 1112U, // VQSHRUNv2i32 - 1112U, // VQSHRUNv4i16 - 1112U, // VQSHRUNv8i8 - 1112U, // VQSUBsv16i8 - 1112U, // VQSUBsv1i64 - 1112U, // VQSUBsv2i32 - 1112U, // VQSUBsv2i64 - 1112U, // VQSUBsv4i16 - 1112U, // VQSUBsv4i32 - 1112U, // VQSUBsv8i16 - 1112U, // VQSUBsv8i8 - 1112U, // VQSUBuv16i8 - 1112U, // VQSUBuv1i64 - 1112U, // VQSUBuv2i32 - 1112U, // VQSUBuv2i64 - 1112U, // VQSUBuv4i16 - 1112U, // VQSUBuv4i32 - 1112U, // VQSUBuv8i16 - 1112U, // VQSUBuv8i8 - 1112U, // VRADDHNv2i32 - 1112U, // VRADDHNv4i16 - 1112U, // VRADDHNv8i8 - 0U, // VRECPEd - 33U, // VRECPEfd - 33U, // VRECPEfq - 33U, // VRECPEhd - 33U, // VRECPEhq - 0U, // VRECPEq - 70705U, // VRECPSfd - 70705U, // VRECPSfq - 70705U, // VRECPShd - 70705U, // VRECPShq - 1024U, // VREV16d8 - 1024U, // VREV16q8 - 1024U, // VREV32d16 - 1024U, // VREV32d8 - 1024U, // VREV32q16 - 1024U, // VREV32q8 - 1024U, // VREV64d16 - 1024U, // VREV64d32 - 1024U, // VREV64d8 - 1024U, // VREV64q16 - 1024U, // VREV64q32 - 1024U, // VREV64q8 - 1112U, // VRHADDsv16i8 - 1112U, // VRHADDsv2i32 - 1112U, // VRHADDsv4i16 - 1112U, // VRHADDsv4i32 - 1112U, // VRHADDsv8i16 - 1112U, // VRHADDsv8i8 - 1112U, // VRHADDuv16i8 - 1112U, // VRHADDuv2i32 - 1112U, // VRHADDuv4i16 - 1112U, // VRHADDuv4i32 - 1112U, // VRHADDuv8i16 - 1112U, // VRHADDuv8i8 - 0U, // VRINTAD - 0U, // VRINTAH - 0U, // VRINTANDf - 0U, // VRINTANDh - 0U, // VRINTANQf - 0U, // VRINTANQh - 0U, // VRINTAS - 0U, // VRINTMD - 0U, // VRINTMH - 0U, // VRINTMNDf - 0U, // VRINTMNDh - 0U, // VRINTMNQf - 0U, // VRINTMNQh - 0U, // VRINTMS - 0U, // VRINTND - 0U, // VRINTNH - 0U, // VRINTNNDf - 0U, // VRINTNNDh - 0U, // VRINTNNQf - 0U, // VRINTNNQh - 0U, // VRINTNS - 0U, // VRINTPD - 0U, // VRINTPH - 0U, // VRINTPNDf - 0U, // VRINTPNDh - 0U, // VRINTPNQf - 0U, // VRINTPNQh - 0U, // VRINTPS - 33U, // VRINTRD - 33U, // VRINTRH - 33U, // VRINTRS - 33U, // VRINTXD - 33U, // VRINTXH - 0U, // VRINTXNDf - 0U, // VRINTXNDh - 0U, // VRINTXNQf - 0U, // VRINTXNQh - 33U, // VRINTXS - 33U, // VRINTZD - 33U, // VRINTZH - 0U, // VRINTZNDf - 0U, // VRINTZNDh - 0U, // VRINTZNQf - 0U, // VRINTZNQh - 33U, // VRINTZS - 1112U, // VRSHLsv16i8 - 1112U, // VRSHLsv1i64 - 1112U, // VRSHLsv2i32 - 1112U, // VRSHLsv2i64 - 1112U, // VRSHLsv4i16 - 1112U, // VRSHLsv4i32 - 1112U, // VRSHLsv8i16 - 1112U, // VRSHLsv8i8 - 1112U, // VRSHLuv16i8 - 1112U, // VRSHLuv1i64 - 1112U, // VRSHLuv2i32 - 1112U, // VRSHLuv2i64 - 1112U, // VRSHLuv4i16 - 1112U, // VRSHLuv4i32 - 1112U, // VRSHLuv8i16 - 1112U, // VRSHLuv8i8 - 1112U, // VRSHRNv2i32 - 1112U, // VRSHRNv4i16 - 1112U, // VRSHRNv8i8 - 1112U, // VRSHRsv16i8 - 1112U, // VRSHRsv1i64 - 1112U, // VRSHRsv2i32 - 1112U, // VRSHRsv2i64 - 1112U, // VRSHRsv4i16 - 1112U, // VRSHRsv4i32 - 1112U, // VRSHRsv8i16 - 1112U, // VRSHRsv8i8 - 1112U, // VRSHRuv16i8 - 1112U, // VRSHRuv1i64 - 1112U, // VRSHRuv2i32 - 1112U, // VRSHRuv2i64 - 1112U, // VRSHRuv4i16 - 1112U, // VRSHRuv4i32 - 1112U, // VRSHRuv8i16 - 1112U, // VRSHRuv8i8 - 0U, // VRSQRTEd - 33U, // VRSQRTEfd - 33U, // VRSQRTEfq - 33U, // VRSQRTEhd - 33U, // VRSQRTEhq - 0U, // VRSQRTEq - 70705U, // VRSQRTSfd - 70705U, // VRSQRTSfq - 70705U, // VRSQRTShd - 70705U, // VRSQRTShq - 1048U, // VRSRAsv16i8 - 1048U, // VRSRAsv1i64 - 1048U, // VRSRAsv2i32 - 1048U, // VRSRAsv2i64 - 1048U, // VRSRAsv4i16 - 1048U, // VRSRAsv4i32 - 1048U, // VRSRAsv8i16 - 1048U, // VRSRAsv8i8 - 1048U, // VRSRAuv16i8 - 1048U, // VRSRAuv1i64 - 1048U, // VRSRAuv2i32 - 1048U, // VRSRAuv2i64 - 1048U, // VRSRAuv4i16 - 1048U, // VRSRAuv4i32 - 1048U, // VRSRAuv8i16 - 1048U, // VRSRAuv8i8 - 1112U, // VRSUBHNv2i32 - 1112U, // VRSUBHNv4i16 - 1112U, // VRSUBHNv8i8 - 0U, // VSDOTD - 0U, // VSDOTDI - 0U, // VSDOTQ - 0U, // VSDOTQI - 1112U, // VSELEQD - 1112U, // VSELEQH - 1112U, // VSELEQS - 1112U, // VSELGED - 1112U, // VSELGEH - 1112U, // VSELGES - 1112U, // VSELGTD - 1112U, // VSELGTH - 1112U, // VSELGTS - 1112U, // VSELVSD - 1112U, // VSELVSH - 1112U, // VSELVSS - 6U, // VSETLNi16 - 6U, // VSETLNi32 - 6U, // VSETLNi8 - 1112U, // VSHLLi16 - 1112U, // VSHLLi32 - 1112U, // VSHLLi8 - 1112U, // VSHLLsv2i64 - 1112U, // VSHLLsv4i32 - 1112U, // VSHLLsv8i16 - 1112U, // VSHLLuv2i64 - 1112U, // VSHLLuv4i32 - 1112U, // VSHLLuv8i16 - 1112U, // VSHLiv16i8 - 1112U, // VSHLiv1i64 - 1112U, // VSHLiv2i32 - 1112U, // VSHLiv2i64 - 1112U, // VSHLiv4i16 - 1112U, // VSHLiv4i32 - 1112U, // VSHLiv8i16 - 1112U, // VSHLiv8i8 - 1112U, // VSHLsv16i8 - 1112U, // VSHLsv1i64 - 1112U, // VSHLsv2i32 - 1112U, // VSHLsv2i64 - 1112U, // VSHLsv4i16 - 1112U, // VSHLsv4i32 - 1112U, // VSHLsv8i16 - 1112U, // VSHLsv8i8 - 1112U, // VSHLuv16i8 - 1112U, // VSHLuv1i64 - 1112U, // VSHLuv2i32 - 1112U, // VSHLuv2i64 - 1112U, // VSHLuv4i16 - 1112U, // VSHLuv4i32 - 1112U, // VSHLuv8i16 - 1112U, // VSHLuv8i8 - 1112U, // VSHRNv2i32 - 1112U, // VSHRNv4i16 - 1112U, // VSHRNv8i8 - 1112U, // VSHRsv16i8 - 1112U, // VSHRsv1i64 - 1112U, // VSHRsv2i32 - 1112U, // VSHRsv2i64 - 1112U, // VSHRsv4i16 - 1112U, // VSHRsv4i32 - 1112U, // VSHRsv8i16 - 1112U, // VSHRsv8i8 - 1112U, // VSHRuv16i8 - 1112U, // VSHRuv1i64 - 1112U, // VSHRuv2i32 - 1112U, // VSHRuv2i64 - 1112U, // VSHRuv4i16 - 1112U, // VSHRuv4i32 - 1112U, // VSHRuv8i16 - 1112U, // VSHRuv8i8 - 0U, // VSHTOD - 7U, // VSHTOH - 0U, // VSHTOS - 0U, // VSITOD - 0U, // VSITOH - 0U, // VSITOS - 589912U, // VSLIv16i8 - 589912U, // VSLIv1i64 - 589912U, // VSLIv2i32 - 589912U, // VSLIv2i64 - 589912U, // VSLIv4i16 - 589912U, // VSLIv4i32 - 589912U, // VSLIv8i16 - 589912U, // VSLIv8i8 - 7U, // VSLTOD - 7U, // VSLTOH - 7U, // VSLTOS - 33U, // VSQRTD - 33U, // VSQRTH - 33U, // VSQRTS - 1048U, // VSRAsv16i8 - 1048U, // VSRAsv1i64 - 1048U, // VSRAsv2i32 - 1048U, // VSRAsv2i64 - 1048U, // VSRAsv4i16 - 1048U, // VSRAsv4i32 - 1048U, // VSRAsv8i16 - 1048U, // VSRAsv8i8 - 1048U, // VSRAuv16i8 - 1048U, // VSRAuv1i64 - 1048U, // VSRAuv2i32 - 1048U, // VSRAuv2i64 - 1048U, // VSRAuv4i16 - 1048U, // VSRAuv4i32 - 1048U, // VSRAuv8i16 - 1048U, // VSRAuv8i8 - 589912U, // VSRIv16i8 - 589912U, // VSRIv1i64 - 589912U, // VSRIv2i32 - 589912U, // VSRIv2i64 - 589912U, // VSRIv4i16 - 589912U, // VSRIv4i32 - 589912U, // VSRIv8i16 - 589912U, // VSRIv8i8 - 308U, // VST1LNd16 - 23768380U, // VST1LNd16_UPD - 308U, // VST1LNd32 - 23768380U, // VST1LNd32_UPD - 308U, // VST1LNd8 - 23768380U, // VST1LNd8_UPD - 0U, // VST1LNq16Pseudo - 0U, // VST1LNq16Pseudo_UPD - 0U, // VST1LNq32Pseudo - 0U, // VST1LNq32Pseudo_UPD - 0U, // VST1LNq8Pseudo - 0U, // VST1LNq8Pseudo_UPD - 0U, // VST1d16 - 0U, // VST1d16Q - 0U, // VST1d16QPseudo - 0U, // VST1d16Qwb_fixed - 0U, // VST1d16Qwb_register - 0U, // VST1d16T - 0U, // VST1d16TPseudo - 0U, // VST1d16Twb_fixed - 0U, // VST1d16Twb_register - 0U, // VST1d16wb_fixed - 0U, // VST1d16wb_register - 0U, // VST1d32 - 0U, // VST1d32Q - 0U, // VST1d32QPseudo - 0U, // VST1d32Qwb_fixed - 0U, // VST1d32Qwb_register - 0U, // VST1d32T - 0U, // VST1d32TPseudo - 0U, // VST1d32Twb_fixed - 0U, // VST1d32Twb_register - 0U, // VST1d32wb_fixed - 0U, // VST1d32wb_register - 0U, // VST1d64 - 0U, // VST1d64Q - 0U, // VST1d64QPseudo - 0U, // VST1d64QPseudoWB_fixed - 0U, // VST1d64QPseudoWB_register - 0U, // VST1d64Qwb_fixed - 0U, // VST1d64Qwb_register - 0U, // VST1d64T - 0U, // VST1d64TPseudo - 0U, // VST1d64TPseudoWB_fixed - 0U, // VST1d64TPseudoWB_register - 0U, // VST1d64Twb_fixed - 0U, // VST1d64Twb_register - 0U, // VST1d64wb_fixed - 0U, // VST1d64wb_register - 0U, // VST1d8 - 0U, // VST1d8Q - 0U, // VST1d8QPseudo - 0U, // VST1d8Qwb_fixed - 0U, // VST1d8Qwb_register - 0U, // VST1d8T - 0U, // VST1d8TPseudo - 0U, // VST1d8Twb_fixed - 0U, // VST1d8Twb_register - 0U, // VST1d8wb_fixed - 0U, // VST1d8wb_register - 0U, // VST1q16 - 0U, // VST1q16HighQPseudo - 0U, // VST1q16HighTPseudo - 0U, // VST1q16LowQPseudo_UPD - 0U, // VST1q16LowTPseudo_UPD - 0U, // VST1q16wb_fixed - 0U, // VST1q16wb_register - 0U, // VST1q32 - 0U, // VST1q32HighQPseudo - 0U, // VST1q32HighTPseudo - 0U, // VST1q32LowQPseudo_UPD - 0U, // VST1q32LowTPseudo_UPD - 0U, // VST1q32wb_fixed - 0U, // VST1q32wb_register - 0U, // VST1q64 - 0U, // VST1q64HighQPseudo - 0U, // VST1q64HighTPseudo - 0U, // VST1q64LowQPseudo_UPD - 0U, // VST1q64LowTPseudo_UPD - 0U, // VST1q64wb_fixed - 0U, // VST1q64wb_register - 0U, // VST1q8 - 0U, // VST1q8HighQPseudo - 0U, // VST1q8HighTPseudo - 0U, // VST1q8LowQPseudo_UPD - 0U, // VST1q8LowTPseudo_UPD - 0U, // VST1q8wb_fixed - 0U, // VST1q8wb_register - 222900460U, // VST2LNd16 - 0U, // VST2LNd16Pseudo - 0U, // VST2LNd16Pseudo_UPD - 995572U, // VST2LNd16_UPD - 222900460U, // VST2LNd32 - 0U, // VST2LNd32Pseudo - 0U, // VST2LNd32Pseudo_UPD - 995572U, // VST2LNd32_UPD - 222900460U, // VST2LNd8 - 0U, // VST2LNd8Pseudo - 0U, // VST2LNd8Pseudo_UPD - 995572U, // VST2LNd8_UPD - 222900460U, // VST2LNq16 - 0U, // VST2LNq16Pseudo - 0U, // VST2LNq16Pseudo_UPD - 995572U, // VST2LNq16_UPD - 222900460U, // VST2LNq32 - 0U, // VST2LNq32Pseudo - 0U, // VST2LNq32Pseudo_UPD - 995572U, // VST2LNq32_UPD - 0U, // VST2b16 - 0U, // VST2b16wb_fixed - 0U, // VST2b16wb_register - 0U, // VST2b32 - 0U, // VST2b32wb_fixed - 0U, // VST2b32wb_register - 0U, // VST2b8 - 0U, // VST2b8wb_fixed - 0U, // VST2b8wb_register - 0U, // VST2d16 - 0U, // VST2d16wb_fixed - 0U, // VST2d16wb_register - 0U, // VST2d32 - 0U, // VST2d32wb_fixed - 0U, // VST2d32wb_register - 0U, // VST2d8 - 0U, // VST2d8wb_fixed - 0U, // VST2d8wb_register - 0U, // VST2q16 - 0U, // VST2q16Pseudo - 0U, // VST2q16PseudoWB_fixed - 0U, // VST2q16PseudoWB_register - 0U, // VST2q16wb_fixed - 0U, // VST2q16wb_register - 0U, // VST2q32 - 0U, // VST2q32Pseudo - 0U, // VST2q32PseudoWB_fixed - 0U, // VST2q32PseudoWB_register - 0U, // VST2q32wb_fixed - 0U, // VST2q32wb_register - 0U, // VST2q8 - 0U, // VST2q8Pseudo - 0U, // VST2q8PseudoWB_fixed - 0U, // VST2q8PseudoWB_register - 0U, // VST2q8wb_fixed - 0U, // VST2q8wb_register - 256454972U, // VST3LNd16 - 0U, // VST3LNd16Pseudo - 0U, // VST3LNd16Pseudo_UPD - 324U, // VST3LNd16_UPD - 256454972U, // VST3LNd32 - 0U, // VST3LNd32Pseudo - 0U, // VST3LNd32Pseudo_UPD - 324U, // VST3LNd32_UPD - 256454972U, // VST3LNd8 - 0U, // VST3LNd8Pseudo - 0U, // VST3LNd8Pseudo_UPD - 324U, // VST3LNd8_UPD - 256454972U, // VST3LNq16 - 0U, // VST3LNq16Pseudo - 0U, // VST3LNq16Pseudo_UPD - 324U, // VST3LNq16_UPD - 256454972U, // VST3LNq32 - 0U, // VST3LNq32Pseudo - 0U, // VST3LNq32Pseudo_UPD - 324U, // VST3LNq32_UPD - 287342616U, // VST3d16 - 0U, // VST3d16Pseudo - 0U, // VST3d16Pseudo_UPD - 18760U, // VST3d16_UPD - 287342616U, // VST3d32 - 0U, // VST3d32Pseudo - 0U, // VST3d32Pseudo_UPD - 18760U, // VST3d32_UPD - 287342616U, // VST3d8 - 0U, // VST3d8Pseudo - 0U, // VST3d8Pseudo_UPD - 18760U, // VST3d8_UPD - 287342616U, // VST3q16 - 0U, // VST3q16Pseudo_UPD - 18760U, // VST3q16_UPD - 0U, // VST3q16oddPseudo - 0U, // VST3q16oddPseudo_UPD - 287342616U, // VST3q32 - 0U, // VST3q32Pseudo_UPD - 18760U, // VST3q32_UPD - 0U, // VST3q32oddPseudo - 0U, // VST3q32oddPseudo_UPD - 287342616U, // VST3q8 - 0U, // VST3q8Pseudo_UPD - 18760U, // VST3q8_UPD - 0U, // VST3q8oddPseudo - 0U, // VST3q8oddPseudo_UPD - 323563764U, // VST4LNd16 - 0U, // VST4LNd16Pseudo - 0U, // VST4LNd16Pseudo_UPD - 19708U, // VST4LNd16_UPD - 323563764U, // VST4LNd32 - 0U, // VST4LNd32Pseudo - 0U, // VST4LNd32Pseudo_UPD - 19708U, // VST4LNd32_UPD - 323563764U, // VST4LNd8 - 0U, // VST4LNd8Pseudo - 0U, // VST4LNd8Pseudo_UPD - 19708U, // VST4LNd8_UPD - 323563764U, // VST4LNq16 - 0U, // VST4LNq16Pseudo - 0U, // VST4LNq16Pseudo_UPD - 19708U, // VST4LNq16_UPD - 323563764U, // VST4LNq32 - 0U, // VST4LNq32Pseudo - 0U, // VST4LNq32Pseudo_UPD - 19708U, // VST4LNq32_UPD - 337674264U, // VST4d16 - 0U, // VST4d16Pseudo - 0U, // VST4d16Pseudo_UPD - 1016136U, // VST4d16_UPD - 337674264U, // VST4d32 - 0U, // VST4d32Pseudo - 0U, // VST4d32Pseudo_UPD - 1016136U, // VST4d32_UPD - 337674264U, // VST4d8 - 0U, // VST4d8Pseudo - 0U, // VST4d8Pseudo_UPD - 1016136U, // VST4d8_UPD - 337674264U, // VST4q16 - 0U, // VST4q16Pseudo_UPD - 1016136U, // VST4q16_UPD - 0U, // VST4q16oddPseudo - 0U, // VST4q16oddPseudo_UPD - 337674264U, // VST4q32 - 0U, // VST4q32Pseudo_UPD - 1016136U, // VST4q32_UPD - 0U, // VST4q32oddPseudo - 0U, // VST4q32oddPseudo_UPD - 337674264U, // VST4q8 - 0U, // VST4q8Pseudo_UPD - 1016136U, // VST4q8_UPD - 0U, // VST4q8oddPseudo - 0U, // VST4q8oddPseudo_UPD - 33U, // VSTMDDB_UPD - 1136U, // VSTMDIA - 33U, // VSTMDIA_UPD - 0U, // VSTMQIA - 33U, // VSTMSDB_UPD - 1136U, // VSTMSIA - 33U, // VSTMSIA_UPD - 288U, // VSTRD - 296U, // VSTRH - 288U, // VSTRS - 70705U, // VSUBD - 70705U, // VSUBH - 1112U, // VSUBHNv2i32 - 1112U, // VSUBHNv4i16 - 1112U, // VSUBHNv8i8 - 1112U, // VSUBLsv2i64 - 1112U, // VSUBLsv4i32 - 1112U, // VSUBLsv8i16 - 1112U, // VSUBLuv2i64 - 1112U, // VSUBLuv4i32 - 1112U, // VSUBLuv8i16 - 70705U, // VSUBS - 1112U, // VSUBWsv2i64 - 1112U, // VSUBWsv4i32 - 1112U, // VSUBWsv8i16 - 1112U, // VSUBWuv2i64 - 1112U, // VSUBWuv4i32 - 1112U, // VSUBWuv8i16 - 70705U, // VSUBfd - 70705U, // VSUBfq - 70705U, // VSUBhd - 70705U, // VSUBhq - 1112U, // VSUBv16i8 - 1112U, // VSUBv1i64 - 1112U, // VSUBv2i32 - 1112U, // VSUBv2i64 - 1112U, // VSUBv4i16 - 1112U, // VSUBv4i32 - 1112U, // VSUBv8i16 - 1112U, // VSUBv8i8 - 1024U, // VSWPd - 1024U, // VSWPq - 336U, // VTBL1 - 344U, // VTBL2 - 352U, // VTBL3 - 0U, // VTBL3Pseudo - 360U, // VTBL4 - 0U, // VTBL4Pseudo - 368U, // VTBX1 - 376U, // VTBX2 - 384U, // VTBX3 - 0U, // VTBX3Pseudo - 392U, // VTBX4 - 0U, // VTBX4Pseudo - 0U, // VTOSHD - 7U, // VTOSHH - 0U, // VTOSHS - 0U, // VTOSIRD - 0U, // VTOSIRH - 0U, // VTOSIRS - 0U, // VTOSIZD - 0U, // VTOSIZH - 0U, // VTOSIZS - 7U, // VTOSLD - 7U, // VTOSLH - 7U, // VTOSLS - 0U, // VTOUHD - 7U, // VTOUHH - 0U, // VTOUHS - 0U, // VTOUIRD - 0U, // VTOUIRH - 0U, // VTOUIRS - 0U, // VTOUIZD - 0U, // VTOUIZH - 0U, // VTOUIZS - 7U, // VTOULD - 7U, // VTOULH - 7U, // VTOULS - 1024U, // VTRNd16 - 1024U, // VTRNd32 - 1024U, // VTRNd8 - 1024U, // VTRNq16 - 1024U, // VTRNq32 - 1024U, // VTRNq8 - 0U, // VTSTv16i8 - 0U, // VTSTv2i32 - 0U, // VTSTv4i16 - 0U, // VTSTv4i32 - 0U, // VTSTv8i16 - 0U, // VTSTv8i8 - 0U, // VUDOTD - 0U, // VUDOTDI - 0U, // VUDOTQ - 0U, // VUDOTQI - 0U, // VUHTOD - 7U, // VUHTOH - 0U, // VUHTOS - 0U, // VUITOD - 0U, // VUITOH - 0U, // VUITOS - 7U, // VULTOD - 7U, // VULTOH - 7U, // VULTOS - 1024U, // VUZPd16 - 1024U, // VUZPd8 - 1024U, // VUZPq16 - 1024U, // VUZPq32 - 1024U, // VUZPq8 - 1024U, // VZIPd16 - 1024U, // VZIPd8 - 1024U, // VZIPq16 - 1024U, // VZIPq32 - 1024U, // VZIPq8 - 20592U, // sysLDMDA - 401U, // sysLDMDA_UPD - 20592U, // sysLDMDB - 401U, // sysLDMDB_UPD - 20592U, // sysLDMIA - 401U, // sysLDMIA_UPD - 20592U, // sysLDMIB - 401U, // sysLDMIB_UPD - 20592U, // sysSTMDA - 401U, // sysSTMDA_UPD - 20592U, // sysSTMDB - 401U, // sysSTMDB_UPD - 20592U, // sysSTMIA - 401U, // sysSTMIA_UPD - 20592U, // sysSTMIB - 401U, // sysSTMIB_UPD - 0U, // t2ADCri - 0U, // t2ADCrr - 1048576U, // t2ADCrs - 0U, // t2ADDri - 0U, // t2ADDri12 - 0U, // t2ADDrr - 1048576U, // t2ADDrs - 72U, // t2ADR - 0U, // t2ANDri - 0U, // t2ANDrr - 1048576U, // t2ANDrs - 1081344U, // t2ASRri - 0U, // t2ASRrr - 0U, // t2B - 80U, // t2BFC - 163928U, // t2BFI - 0U, // t2BICri - 0U, // t2BICrr - 1048576U, // t2BICrs - 0U, // t2BXJ - 0U, // t2Bcc - 4145U, // t2CDP - 4145U, // t2CDP2 - 0U, // t2CLREX - 1024U, // t2CLZ - 1024U, // t2CMNri - 1024U, // t2CMNzrr - 56U, // t2CMNzrs - 1024U, // t2CMPri - 1024U, // t2CMPrr - 56U, // t2CMPrs - 0U, // t2CPS1p - 0U, // t2CPS2p - 1112U, // t2CPS3p - 1112U, // t2CRC32B - 1112U, // t2CRC32CB - 1112U, // t2CRC32CH - 1112U, // t2CRC32CW - 1112U, // t2CRC32H - 1112U, // t2CRC32W - 0U, // t2DBG - 0U, // t2DCPS1 - 0U, // t2DCPS2 - 0U, // t2DCPS3 - 0U, // t2DMB - 0U, // t2DSB - 0U, // t2EORri - 0U, // t2EORrr - 1048576U, // t2EORrs - 0U, // t2HINT - 0U, // t2HVC - 0U, // t2ISB - 0U, // t2IT - 0U, // t2Int_eh_sjlj_setjmp - 0U, // t2Int_eh_sjlj_setjmp_nofp - 8U, // t2LDA - 8U, // t2LDAB - 8U, // t2LDAEX - 8U, // t2LDAEXB - 557056U, // t2LDAEXD - 8U, // t2LDAEXH - 8U, // t2LDAH - 122U, // t2LDC2L_OFFSET - 196738U, // t2LDC2L_OPTION - 229506U, // t2LDC2L_POST - 138U, // t2LDC2L_PRE - 122U, // t2LDC2_OFFSET - 196738U, // t2LDC2_OPTION - 229506U, // t2LDC2_POST - 138U, // t2LDC2_PRE - 122U, // t2LDCL_OFFSET - 196738U, // t2LDCL_OPTION - 229506U, // t2LDCL_POST - 138U, // t2LDCL_PRE - 122U, // t2LDC_OFFSET - 196738U, // t2LDC_OPTION - 229506U, // t2LDC_POST - 138U, // t2LDC_PRE - 1136U, // t2LDMDB - 33U, // t2LDMDB_UPD - 1136U, // t2LDMIA - 33U, // t2LDMIA_UPD - 408U, // t2LDRBT - 21632U, // t2LDRB_POST - 416U, // t2LDRB_PRE - 160U, // t2LDRBi12 - 408U, // t2LDRBi8 - 424U, // t2LDRBpci - 432U, // t2LDRBs - 25493504U, // t2LDRD_POST - 1114112U, // t2LDRD_PRE - 1146880U, // t2LDRDi8 - 440U, // t2LDREX - 8U, // t2LDREXB - 557056U, // t2LDREXD - 8U, // t2LDREXH - 408U, // t2LDRHT - 21632U, // t2LDRH_POST - 416U, // t2LDRH_PRE - 160U, // t2LDRHi12 - 408U, // t2LDRHi8 - 424U, // t2LDRHpci - 432U, // t2LDRHs - 408U, // t2LDRSBT - 21632U, // t2LDRSB_POST - 416U, // t2LDRSB_PRE - 160U, // t2LDRSBi12 - 408U, // t2LDRSBi8 - 424U, // t2LDRSBpci - 432U, // t2LDRSBs - 408U, // t2LDRSHT - 21632U, // t2LDRSH_POST - 416U, // t2LDRSH_PRE - 160U, // t2LDRSHi12 - 408U, // t2LDRSHi8 - 424U, // t2LDRSHpci - 432U, // t2LDRSHs - 408U, // t2LDRT - 21632U, // t2LDR_POST - 416U, // t2LDR_PRE - 160U, // t2LDRi12 - 408U, // t2LDRi8 - 424U, // t2LDRpci - 432U, // t2LDRs - 0U, // t2LSLri - 0U, // t2LSLrr - 1081344U, // t2LSRri - 0U, // t2LSRrr - 4690993U, // t2MCR - 4690993U, // t2MCR2 - 6788145U, // t2MCRR - 6788145U, // t2MCRR2 - 35651584U, // t2MLA - 35651584U, // t2MLS - 1112U, // t2MOVTi16 - 1024U, // t2MOVi - 1024U, // t2MOVi16 - 1024U, // t2MOVr - 22528U, // t2MOVsra_flag - 22528U, // t2MOVsrl_flag - 0U, // t2MRC - 0U, // t2MRC2 - 0U, // t2MRRC - 0U, // t2MRRC2 - 2U, // t2MRS_AR - 448U, // t2MRS_M - 200U, // t2MRSbanked - 2U, // t2MRSsys_AR - 33U, // t2MSR_AR - 33U, // t2MSR_M - 0U, // t2MSRbanked - 0U, // t2MUL - 1024U, // t2MVNi - 1024U, // t2MVNr - 56U, // t2MVNs - 0U, // t2ORNri - 0U, // t2ORNrr - 1048576U, // t2ORNrs - 0U, // t2ORRri - 0U, // t2ORRrr - 1048576U, // t2ORRrs - 8388608U, // t2PKHBT - 10485760U, // t2PKHTB - 0U, // t2PLDWi12 - 0U, // t2PLDWi8 - 0U, // t2PLDWs - 0U, // t2PLDi12 - 0U, // t2PLDi8 - 0U, // t2PLDpci - 0U, // t2PLDs - 0U, // t2PLIi12 - 0U, // t2PLIi8 - 0U, // t2PLIpci - 0U, // t2PLIs - 0U, // t2QADD - 0U, // t2QADD16 - 0U, // t2QADD8 - 0U, // t2QASX - 0U, // t2QDADD - 0U, // t2QDSUB - 0U, // t2QSAX - 0U, // t2QSUB - 0U, // t2QSUB16 - 0U, // t2QSUB8 - 1024U, // t2RBIT - 1024U, // t2REV - 1024U, // t2REV16 - 1024U, // t2REVSH - 0U, // t2RFEDB - 0U, // t2RFEDBW - 0U, // t2RFEIA - 0U, // t2RFEIAW - 0U, // t2RORri - 0U, // t2RORrr - 1024U, // t2RRX - 0U, // t2RSBri - 0U, // t2RSBrr - 1048576U, // t2RSBrs - 0U, // t2SADD16 - 0U, // t2SADD8 - 0U, // t2SASX - 0U, // t2SBCri - 0U, // t2SBCrr - 1048576U, // t2SBCrs - 69206016U, // t2SBFX - 0U, // t2SDIV - 0U, // t2SEL - 0U, // t2SETPAN - 0U, // t2SG - 0U, // t2SHADD16 - 0U, // t2SHADD8 - 0U, // t2SHASX - 0U, // t2SHSAX - 0U, // t2SHSUB16 - 0U, // t2SHSUB8 - 0U, // t2SMC - 35651584U, // t2SMLABB - 35651584U, // t2SMLABT - 35651584U, // t2SMLAD - 35651584U, // t2SMLADX - 35651584U, // t2SMLAL - 35651584U, // t2SMLALBB - 35651584U, // t2SMLALBT - 35651584U, // t2SMLALD - 35651584U, // t2SMLALDX - 35651584U, // t2SMLALTB - 35651584U, // t2SMLALTT - 35651584U, // t2SMLATB - 35651584U, // t2SMLATT - 35651584U, // t2SMLAWB - 35651584U, // t2SMLAWT - 35651584U, // t2SMLSD - 35651584U, // t2SMLSDX - 35651584U, // t2SMLSLD - 35651584U, // t2SMLSLDX - 35651584U, // t2SMMLA - 35651584U, // t2SMMLAR - 35651584U, // t2SMMLS - 35651584U, // t2SMMLSR - 0U, // t2SMMUL - 0U, // t2SMMULR - 0U, // t2SMUAD - 0U, // t2SMUADX - 0U, // t2SMULBB - 0U, // t2SMULBT - 35651584U, // t2SMULL - 0U, // t2SMULTB - 0U, // t2SMULTT - 0U, // t2SMULWB - 0U, // t2SMULWT - 0U, // t2SMUSD - 0U, // t2SMUSDX - 0U, // t2SRSDB - 0U, // t2SRSDB_UPD - 0U, // t2SRSIA - 0U, // t2SRSIA_UPD - 6352U, // t2SSAT - 1232U, // t2SSAT16 - 0U, // t2SSAX - 0U, // t2SSUB16 - 0U, // t2SSUB8 - 122U, // t2STC2L_OFFSET - 196738U, // t2STC2L_OPTION - 229506U, // t2STC2L_POST - 138U, // t2STC2L_PRE - 122U, // t2STC2_OFFSET - 196738U, // t2STC2_OPTION - 229506U, // t2STC2_POST - 138U, // t2STC2_PRE - 122U, // t2STCL_OFFSET - 196738U, // t2STCL_OPTION - 229506U, // t2STCL_POST - 138U, // t2STCL_PRE - 122U, // t2STC_OFFSET - 196738U, // t2STC_OPTION - 229506U, // t2STC_POST - 138U, // t2STC_PRE - 8U, // t2STL - 8U, // t2STLB - 557056U, // t2STLEX - 557056U, // t2STLEXB - 371195904U, // t2STLEXD - 557056U, // t2STLEXH - 8U, // t2STLH - 1136U, // t2STMDB - 33U, // t2STMDB_UPD - 1136U, // t2STMIA - 33U, // t2STMIA_UPD - 408U, // t2STRBT - 21632U, // t2STRB_POST - 416U, // t2STRB_PRE - 160U, // t2STRBi12 - 408U, // t2STRBi8 - 432U, // t2STRBs - 25493592U, // t2STRD_POST - 1114200U, // t2STRD_PRE - 1146880U, // t2STRDi8 - 1179648U, // t2STREX - 557056U, // t2STREXB - 371195904U, // t2STREXD - 557056U, // t2STREXH - 408U, // t2STRHT - 21632U, // t2STRH_POST - 416U, // t2STRH_PRE - 160U, // t2STRHi12 - 408U, // t2STRHi8 - 432U, // t2STRHs - 408U, // t2STRT - 21632U, // t2STR_POST - 416U, // t2STR_PRE - 160U, // t2STRi12 - 408U, // t2STRi8 - 432U, // t2STRs - 0U, // t2SUBS_PC_LR - 0U, // t2SUBri - 0U, // t2SUBri12 - 0U, // t2SUBrr - 1048576U, // t2SUBrs - 12582912U, // t2SXTAB - 12582912U, // t2SXTAB16 - 12582912U, // t2SXTAH - 7168U, // t2SXTB - 7168U, // t2SXTB16 - 7168U, // t2SXTH - 0U, // t2TBB - 0U, // t2TBH - 1024U, // t2TEQri - 1024U, // t2TEQrr - 56U, // t2TEQrs - 0U, // t2TSB - 1024U, // t2TSTri - 1024U, // t2TSTrr - 56U, // t2TSTrs - 1024U, // t2TT - 1024U, // t2TTA - 1024U, // t2TTAT - 1024U, // t2TTT - 0U, // t2UADD16 - 0U, // t2UADD8 - 0U, // t2UASX - 69206016U, // t2UBFX - 0U, // t2UDF - 0U, // t2UDIV - 0U, // t2UHADD16 - 0U, // t2UHADD8 - 0U, // t2UHASX - 0U, // t2UHSAX - 0U, // t2UHSUB16 - 0U, // t2UHSUB8 - 35651584U, // t2UMAAL - 35651584U, // t2UMLAL - 35651584U, // t2UMULL - 0U, // t2UQADD16 - 0U, // t2UQADD8 - 0U, // t2UQASX - 0U, // t2UQSAX - 0U, // t2UQSUB16 - 0U, // t2UQSUB8 - 0U, // t2USAD8 - 35651584U, // t2USADA8 - 14680064U, // t2USAT - 0U, // t2USAT16 - 0U, // t2USAX - 0U, // t2USUB16 - 0U, // t2USUB8 - 12582912U, // t2UXTAB - 12582912U, // t2UXTAB16 - 12582912U, // t2UXTAH - 7168U, // t2UXTB - 7168U, // t2UXTB16 - 7168U, // t2UXTH - 0U, // tADC - 1112U, // tADDhirr - 1048U, // tADDi3 - 0U, // tADDi8 - 0U, // tADDrSP - 1212416U, // tADDrSPi - 1048U, // tADDrr - 456U, // tADDspi - 1112U, // tADDspr - 464U, // tADR - 0U, // tAND - 472U, // tASRri - 0U, // tASRrr - 0U, // tB - 0U, // tBIC - 0U, // tBKPT - 0U, // tBL - 0U, // tBLXNSr - 0U, // tBLXi - 0U, // tBLXr - 0U, // tBX - 0U, // tBXNS - 0U, // tBcc - 0U, // tCBNZ - 0U, // tCBZ - 1024U, // tCMNz - 1024U, // tCMPhir - 1024U, // tCMPi8 - 1024U, // tCMPr - 0U, // tCPS - 0U, // tEOR - 0U, // tHINT - 0U, // tHLT - 0U, // tInt_WIN_eh_sjlj_longjmp - 0U, // tInt_eh_sjlj_longjmp - 0U, // tInt_eh_sjlj_setjmp - 1136U, // tLDMIA - 480U, // tLDRBi - 488U, // tLDRBr - 496U, // tLDRHi - 488U, // tLDRHr - 488U, // tLDRSB - 488U, // tLDRSH - 504U, // tLDRi - 424U, // tLDRpci - 488U, // tLDRr - 512U, // tLDRspi - 1048U, // tLSLri - 0U, // tLSLrr - 472U, // tLSRri - 0U, // tLSRrr - 0U, // tMOVSr - 0U, // tMOVi8 - 1024U, // tMOVr - 1048U, // tMUL - 0U, // tMVN - 0U, // tORR - 0U, // tPICADD - 0U, // tPOP - 0U, // tPUSH - 1024U, // tREV - 1024U, // tREV16 - 1024U, // tREVSH - 0U, // tROR - 0U, // tRSB - 0U, // tSBC - 0U, // tSETEND - 33U, // tSTMIA_UPD - 480U, // tSTRBi - 488U, // tSTRBr - 496U, // tSTRHi - 488U, // tSTRHr - 504U, // tSTRi - 488U, // tSTRr - 512U, // tSTRspi - 1048U, // tSUBi3 - 0U, // tSUBi8 - 1048U, // tSUBrr - 456U, // tSUBspi - 0U, // tSVC - 1024U, // tSXTB - 1024U, // tSXTH - 0U, // tTRAP - 1024U, // tTST - 0U, // tUDF - 1024U, // tUXTB - 1024U, // tUXTH - 0U, // t__brkdiv0 + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // ABS + 0U, // ADDSri + 0U, // ADDSrr + 0U, // ADDSrsi + 0U, // ADDSrsr + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ASRi + 0U, // ASRr + 0U, // B + 0U, // BCCZi64 + 0U, // BCCi64 + 0U, // BMOVPCB_CALL + 0U, // BMOVPCRX_CALL + 0U, // BR_JTadd + 0U, // BR_JTm_i12 + 0U, // BR_JTm_rs + 0U, // BR_JTr + 0U, // BX_CALL + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_STRUCT_BYVAL_I32 + 0U, // CompilerBarrier + 0U, // ITasm + 0U, // Int_eh_sjlj_dispatchsetup + 0U, // Int_eh_sjlj_longjmp + 0U, // Int_eh_sjlj_setjmp + 0U, // Int_eh_sjlj_setjmp_nofp + 0U, // Int_eh_sjlj_setup_dispatch + 0U, // JUMPTABLE_ADDRS + 0U, // JUMPTABLE_INSTS + 0U, // JUMPTABLE_TBB + 0U, // JUMPTABLE_TBH + 0U, // LDMIA_RET + 8U, // LDRBT_POST + 1024U, // LDRConstPool + 0U, // LDRLIT_ga_abs + 0U, // LDRLIT_ga_pcrel + 0U, // LDRLIT_ga_pcrel_ldr + 8U, // LDRT_POST + 0U, // LEApcrel + 0U, // LEApcrelJT + 0U, // LSLi + 0U, // LSLr + 0U, // LSRi + 0U, // LSRr + 0U, // MEMCPY + 0U, // MLAv5 + 0U, // MOVCCi + 0U, // MOVCCi16 + 0U, // MOVCCi32imm + 0U, // MOVCCr + 0U, // MOVCCsi + 0U, // MOVCCsr + 0U, // MOVPCRX + 0U, // MOVTi16_ga_pcrel + 0U, // MOV_ga_pcrel + 0U, // MOV_ga_pcrel_ldr + 0U, // MOVi16_ga_pcrel + 0U, // MOVi32imm + 0U, // MOVsra_flag + 0U, // MOVsrl_flag + 0U, // MULv5 + 0U, // MVNCCi + 0U, // PICADD + 0U, // PICLDR + 0U, // PICLDRB + 0U, // PICLDRH + 0U, // PICLDRSB + 0U, // PICLDRSH + 0U, // PICSTR + 0U, // PICSTRB + 0U, // PICSTRH + 0U, // RORi + 0U, // RORr + 0U, // RRX + 1024U, // RRXi + 0U, // RSBSri + 0U, // RSBSrsi + 0U, // RSBSrsr + 0U, // SMLALv5 + 0U, // SMULLv5 + 0U, // SPACE + 8U, // STRBT_POST + 0U, // STRBi_preidx + 0U, // STRBr_preidx + 0U, // STRH_preidx + 8U, // STRT_POST + 0U, // STRi_preidx + 0U, // STRr_preidx + 0U, // SUBS_PC_LR + 0U, // SUBSri + 0U, // SUBSrr + 0U, // SUBSrsi + 0U, // SUBSrsr + 0U, // TAILJMPd + 0U, // TAILJMPr + 0U, // TAILJMPr4 + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TPsoft + 0U, // UMLALv5 + 0U, // UMULLv5 + 1040U, // VLD1LNdAsm_16 + 1040U, // VLD1LNdAsm_32 + 1040U, // VLD1LNdAsm_8 + 2064U, // VLD1LNdWB_fixed_Asm_16 + 2064U, // VLD1LNdWB_fixed_Asm_32 + 2064U, // VLD1LNdWB_fixed_Asm_8 + 32784U, // VLD1LNdWB_register_Asm_16 + 32784U, // VLD1LNdWB_register_Asm_32 + 32784U, // VLD1LNdWB_register_Asm_8 + 1040U, // VLD2LNdAsm_16 + 1040U, // VLD2LNdAsm_32 + 1040U, // VLD2LNdAsm_8 + 2064U, // VLD2LNdWB_fixed_Asm_16 + 2064U, // VLD2LNdWB_fixed_Asm_32 + 2064U, // VLD2LNdWB_fixed_Asm_8 + 32784U, // VLD2LNdWB_register_Asm_16 + 32784U, // VLD2LNdWB_register_Asm_32 + 32784U, // VLD2LNdWB_register_Asm_8 + 1040U, // VLD2LNqAsm_16 + 1040U, // VLD2LNqAsm_32 + 2064U, // VLD2LNqWB_fixed_Asm_16 + 2064U, // VLD2LNqWB_fixed_Asm_32 + 32784U, // VLD2LNqWB_register_Asm_16 + 32784U, // VLD2LNqWB_register_Asm_32 + 0U, // VLD3DUPdAsm_16 + 0U, // VLD3DUPdAsm_32 + 0U, // VLD3DUPdAsm_8 + 0U, // VLD3DUPdWB_fixed_Asm_16 + 0U, // VLD3DUPdWB_fixed_Asm_32 + 0U, // VLD3DUPdWB_fixed_Asm_8 + 1048U, // VLD3DUPdWB_register_Asm_16 + 1048U, // VLD3DUPdWB_register_Asm_32 + 1048U, // VLD3DUPdWB_register_Asm_8 + 0U, // VLD3DUPqAsm_16 + 0U, // VLD3DUPqAsm_32 + 0U, // VLD3DUPqAsm_8 + 0U, // VLD3DUPqWB_fixed_Asm_16 + 0U, // VLD3DUPqWB_fixed_Asm_32 + 0U, // VLD3DUPqWB_fixed_Asm_8 + 1048U, // VLD3DUPqWB_register_Asm_16 + 1048U, // VLD3DUPqWB_register_Asm_32 + 1048U, // VLD3DUPqWB_register_Asm_8 + 1040U, // VLD3LNdAsm_16 + 1040U, // VLD3LNdAsm_32 + 1040U, // VLD3LNdAsm_8 + 2064U, // VLD3LNdWB_fixed_Asm_16 + 2064U, // VLD3LNdWB_fixed_Asm_32 + 2064U, // VLD3LNdWB_fixed_Asm_8 + 32784U, // VLD3LNdWB_register_Asm_16 + 32784U, // VLD3LNdWB_register_Asm_32 + 32784U, // VLD3LNdWB_register_Asm_8 + 1040U, // VLD3LNqAsm_16 + 1040U, // VLD3LNqAsm_32 + 2064U, // VLD3LNqWB_fixed_Asm_16 + 2064U, // VLD3LNqWB_fixed_Asm_32 + 32784U, // VLD3LNqWB_register_Asm_16 + 32784U, // VLD3LNqWB_register_Asm_32 + 32U, // VLD3dAsm_16 + 32U, // VLD3dAsm_32 + 32U, // VLD3dAsm_8 + 40U, // VLD3dWB_fixed_Asm_16 + 40U, // VLD3dWB_fixed_Asm_32 + 40U, // VLD3dWB_fixed_Asm_8 + 68656U, // VLD3dWB_register_Asm_16 + 68656U, // VLD3dWB_register_Asm_32 + 68656U, // VLD3dWB_register_Asm_8 + 0U, // VLD3qAsm_16 + 0U, // VLD3qAsm_32 + 0U, // VLD3qAsm_8 + 0U, // VLD3qWB_fixed_Asm_16 + 0U, // VLD3qWB_fixed_Asm_32 + 0U, // VLD3qWB_fixed_Asm_8 + 1048U, // VLD3qWB_register_Asm_16 + 1048U, // VLD3qWB_register_Asm_32 + 1048U, // VLD3qWB_register_Asm_8 + 0U, // VLD4DUPdAsm_16 + 0U, // VLD4DUPdAsm_32 + 0U, // VLD4DUPdAsm_8 + 0U, // VLD4DUPdWB_fixed_Asm_16 + 0U, // VLD4DUPdWB_fixed_Asm_32 + 0U, // VLD4DUPdWB_fixed_Asm_8 + 1048U, // VLD4DUPdWB_register_Asm_16 + 1048U, // VLD4DUPdWB_register_Asm_32 + 1048U, // VLD4DUPdWB_register_Asm_8 + 0U, // VLD4DUPqAsm_16 + 0U, // VLD4DUPqAsm_32 + 0U, // VLD4DUPqAsm_8 + 0U, // VLD4DUPqWB_fixed_Asm_16 + 0U, // VLD4DUPqWB_fixed_Asm_32 + 0U, // VLD4DUPqWB_fixed_Asm_8 + 1048U, // VLD4DUPqWB_register_Asm_16 + 1048U, // VLD4DUPqWB_register_Asm_32 + 1048U, // VLD4DUPqWB_register_Asm_8 + 1040U, // VLD4LNdAsm_16 + 1040U, // VLD4LNdAsm_32 + 1040U, // VLD4LNdAsm_8 + 2064U, // VLD4LNdWB_fixed_Asm_16 + 2064U, // VLD4LNdWB_fixed_Asm_32 + 2064U, // VLD4LNdWB_fixed_Asm_8 + 32784U, // VLD4LNdWB_register_Asm_16 + 32784U, // VLD4LNdWB_register_Asm_32 + 32784U, // VLD4LNdWB_register_Asm_8 + 1040U, // VLD4LNqAsm_16 + 1040U, // VLD4LNqAsm_32 + 2064U, // VLD4LNqWB_fixed_Asm_16 + 2064U, // VLD4LNqWB_fixed_Asm_32 + 32784U, // VLD4LNqWB_register_Asm_16 + 32784U, // VLD4LNqWB_register_Asm_32 + 32U, // VLD4dAsm_16 + 32U, // VLD4dAsm_32 + 32U, // VLD4dAsm_8 + 40U, // VLD4dWB_fixed_Asm_16 + 40U, // VLD4dWB_fixed_Asm_32 + 40U, // VLD4dWB_fixed_Asm_8 + 68656U, // VLD4dWB_register_Asm_16 + 68656U, // VLD4dWB_register_Asm_32 + 68656U, // VLD4dWB_register_Asm_8 + 0U, // VLD4qAsm_16 + 0U, // VLD4qAsm_32 + 0U, // VLD4qAsm_8 + 0U, // VLD4qWB_fixed_Asm_16 + 0U, // VLD4qWB_fixed_Asm_32 + 0U, // VLD4qWB_fixed_Asm_8 + 1048U, // VLD4qWB_register_Asm_16 + 1048U, // VLD4qWB_register_Asm_32 + 1048U, // VLD4qWB_register_Asm_8 + 0U, // VMOVD0 + 0U, // VMOVDcc + 0U, // VMOVQ0 + 0U, // VMOVScc + 1040U, // VST1LNdAsm_16 + 1040U, // VST1LNdAsm_32 + 1040U, // VST1LNdAsm_8 + 2064U, // VST1LNdWB_fixed_Asm_16 + 2064U, // VST1LNdWB_fixed_Asm_32 + 2064U, // VST1LNdWB_fixed_Asm_8 + 32784U, // VST1LNdWB_register_Asm_16 + 32784U, // VST1LNdWB_register_Asm_32 + 32784U, // VST1LNdWB_register_Asm_8 + 1040U, // VST2LNdAsm_16 + 1040U, // VST2LNdAsm_32 + 1040U, // VST2LNdAsm_8 + 2064U, // VST2LNdWB_fixed_Asm_16 + 2064U, // VST2LNdWB_fixed_Asm_32 + 2064U, // VST2LNdWB_fixed_Asm_8 + 32784U, // VST2LNdWB_register_Asm_16 + 32784U, // VST2LNdWB_register_Asm_32 + 32784U, // VST2LNdWB_register_Asm_8 + 1040U, // VST2LNqAsm_16 + 1040U, // VST2LNqAsm_32 + 2064U, // VST2LNqWB_fixed_Asm_16 + 2064U, // VST2LNqWB_fixed_Asm_32 + 32784U, // VST2LNqWB_register_Asm_16 + 32784U, // VST2LNqWB_register_Asm_32 + 1040U, // VST3LNdAsm_16 + 1040U, // VST3LNdAsm_32 + 1040U, // VST3LNdAsm_8 + 2064U, // VST3LNdWB_fixed_Asm_16 + 2064U, // VST3LNdWB_fixed_Asm_32 + 2064U, // VST3LNdWB_fixed_Asm_8 + 32784U, // VST3LNdWB_register_Asm_16 + 32784U, // VST3LNdWB_register_Asm_32 + 32784U, // VST3LNdWB_register_Asm_8 + 1040U, // VST3LNqAsm_16 + 1040U, // VST3LNqAsm_32 + 2064U, // VST3LNqWB_fixed_Asm_16 + 2064U, // VST3LNqWB_fixed_Asm_32 + 32784U, // VST3LNqWB_register_Asm_16 + 32784U, // VST3LNqWB_register_Asm_32 + 32U, // VST3dAsm_16 + 32U, // VST3dAsm_32 + 32U, // VST3dAsm_8 + 40U, // VST3dWB_fixed_Asm_16 + 40U, // VST3dWB_fixed_Asm_32 + 40U, // VST3dWB_fixed_Asm_8 + 68656U, // VST3dWB_register_Asm_16 + 68656U, // VST3dWB_register_Asm_32 + 68656U, // VST3dWB_register_Asm_8 + 0U, // VST3qAsm_16 + 0U, // VST3qAsm_32 + 0U, // VST3qAsm_8 + 0U, // VST3qWB_fixed_Asm_16 + 0U, // VST3qWB_fixed_Asm_32 + 0U, // VST3qWB_fixed_Asm_8 + 1048U, // VST3qWB_register_Asm_16 + 1048U, // VST3qWB_register_Asm_32 + 1048U, // VST3qWB_register_Asm_8 + 1040U, // VST4LNdAsm_16 + 1040U, // VST4LNdAsm_32 + 1040U, // VST4LNdAsm_8 + 2064U, // VST4LNdWB_fixed_Asm_16 + 2064U, // VST4LNdWB_fixed_Asm_32 + 2064U, // VST4LNdWB_fixed_Asm_8 + 32784U, // VST4LNdWB_register_Asm_16 + 32784U, // VST4LNdWB_register_Asm_32 + 32784U, // VST4LNdWB_register_Asm_8 + 1040U, // VST4LNqAsm_16 + 1040U, // VST4LNqAsm_32 + 2064U, // VST4LNqWB_fixed_Asm_16 + 2064U, // VST4LNqWB_fixed_Asm_32 + 32784U, // VST4LNqWB_register_Asm_16 + 32784U, // VST4LNqWB_register_Asm_32 + 32U, // VST4dAsm_16 + 32U, // VST4dAsm_32 + 32U, // VST4dAsm_8 + 40U, // VST4dWB_fixed_Asm_16 + 40U, // VST4dWB_fixed_Asm_32 + 40U, // VST4dWB_fixed_Asm_8 + 68656U, // VST4dWB_register_Asm_16 + 68656U, // VST4dWB_register_Asm_32 + 68656U, // VST4dWB_register_Asm_8 + 0U, // VST4qAsm_16 + 0U, // VST4qAsm_32 + 0U, // VST4qAsm_8 + 0U, // VST4qWB_fixed_Asm_16 + 0U, // VST4qWB_fixed_Asm_32 + 0U, // VST4qWB_fixed_Asm_8 + 1048U, // VST4qWB_register_Asm_16 + 1048U, // VST4qWB_register_Asm_32 + 1048U, // VST4qWB_register_Asm_8 + 0U, // WIN__CHKSTK + 0U, // WIN__DBZCHK + 0U, // t2ABS + 0U, // t2ADDSri + 0U, // t2ADDSrr + 0U, // t2ADDSrs + 0U, // t2BR_JT + 0U, // t2LDMIA_RET + 1024U, // t2LDRBpcrel + 1024U, // t2LDRConstPool + 1024U, // t2LDRHpcrel + 1024U, // t2LDRSBpcrel + 1024U, // t2LDRSHpcrel + 0U, // t2LDRpci_pic + 1024U, // t2LDRpcrel + 0U, // t2LEApcrel + 0U, // t2LEApcrelJT + 0U, // t2MOVCCasr + 0U, // t2MOVCCi + 0U, // t2MOVCCi16 + 0U, // t2MOVCCi32imm + 0U, // t2MOVCClsl + 0U, // t2MOVCClsr + 0U, // t2MOVCCr + 0U, // t2MOVCCror + 56U, // t2MOVSsi + 64U, // t2MOVSsr + 0U, // t2MOVTi16_ga_pcrel + 0U, // t2MOV_ga_pcrel + 0U, // t2MOVi16_ga_pcrel + 0U, // t2MOVi32imm + 56U, // t2MOVsi + 64U, // t2MOVsr + 0U, // t2MVNCCi + 0U, // t2RSBSri + 0U, // t2RSBSrs + 0U, // t2STRB_preidx + 0U, // t2STRH_preidx + 0U, // t2STR_preidx + 0U, // t2SUBSri + 0U, // t2SUBSrr + 0U, // t2SUBSrs + 0U, // t2TBB_JT + 0U, // t2TBH_JT + 0U, // tADCS + 0U, // tADDSi3 + 0U, // tADDSi8 + 0U, // tADDSrr + 0U, // tADDframe + 0U, // tADJCALLSTACKDOWN + 0U, // tADJCALLSTACKUP + 0U, // tBRIND + 0U, // tBR_JTr + 0U, // tBX_CALL + 0U, // tBX_RET + 0U, // tBX_RET_vararg + 0U, // tBfar + 0U, // tLDMIA_UPD + 1024U, // tLDRConstPool + 0U, // tLDRLIT_ga_abs + 0U, // tLDRLIT_ga_pcrel + 0U, // tLDR_postidx + 0U, // tLDRpci_pic + 0U, // tLEApcrel + 0U, // tLEApcrelJT + 0U, // tMOVCCr_pseudo + 0U, // tPOP_RET + 0U, // tSBCS + 0U, // tSUBSi3 + 0U, // tSUBSi8 + 0U, // tSUBSrr + 0U, // tTAILJMPd + 0U, // tTAILJMPdND + 0U, // tTAILJMPr + 0U, // tTBB_JT + 0U, // tTBH_JT + 0U, // tTPsoft + 98304U, // ADCri + 0U, // ADCrr + 131072U, // ADCrsi + 0U, // ADCrsr + 98304U, // ADDri + 0U, // ADDrr + 131072U, // ADDrsi + 0U, // ADDrsr + 72U, // ADR + 0U, // AESD + 0U, // AESE + 0U, // AESIMC + 0U, // AESMC + 98304U, // ANDri + 0U, // ANDrr + 131072U, // ANDrsi + 0U, // ANDrsr + 80U, // BFC + 163928U, // BFI + 98304U, // BICri + 0U, // BICrr + 131072U, // BICrsi + 0U, // BICrsr + 0U, // BKPT + 0U, // BL + 0U, // BLX + 0U, // BLX_pred + 0U, // BLXi + 0U, // BL_pred + 0U, // BX + 0U, // BXJ + 0U, // BX_RET + 0U, // BX_pred + 0U, // Bcc + 4145U, // CDP + 0U, // CDP2 + 0U, // CLREX + 1024U, // CLZ + 96U, // CMNri + 1024U, // CMNzrr + 104U, // CMNzrsi + 64U, // CMNzrsr + 96U, // CMPri + 1024U, // CMPrr + 104U, // CMPrsi + 64U, // CMPrsr + 0U, // CPS1p + 0U, // CPS2p + 1112U, // CPS3p + 1112U, // CRC32B + 1112U, // CRC32CB + 1112U, // CRC32CH + 1112U, // CRC32CW + 1112U, // CRC32H + 1112U, // CRC32W + 0U, // DBG + 0U, // DMB + 0U, // DSB + 98304U, // EORri + 0U, // EORrr + 131072U, // EORrsi + 0U, // EORrsr + 0U, // ERET + 1U, // FCONSTD + 1U, // FCONSTH + 1U, // FCONSTS + 33U, // FLDMXDB_UPD + 1136U, // FLDMXIA + 33U, // FLDMXIA_UPD + 0U, // FMSTAT + 33U, // FSTMXDB_UPD + 1136U, // FSTMXIA + 33U, // FSTMXIA_UPD + 0U, // HINT + 0U, // HLT + 0U, // HVC + 0U, // ISB + 8U, // LDA + 8U, // LDAB + 8U, // LDAEX + 8U, // LDAEXB + 0U, // LDAEXD + 8U, // LDAEXH + 8U, // LDAH + 0U, // LDC2L_OFFSET + 1U, // LDC2L_OPTION + 2U, // LDC2L_POST + 0U, // LDC2L_PRE + 0U, // LDC2_OFFSET + 1U, // LDC2_OPTION + 2U, // LDC2_POST + 0U, // LDC2_PRE + 122U, // LDCL_OFFSET + 196738U, // LDCL_OPTION + 229506U, // LDCL_POST + 138U, // LDCL_PRE + 122U, // LDC_OFFSET + 196738U, // LDC_OPTION + 229506U, // LDC_POST + 138U, // LDC_PRE + 1136U, // LDMDA + 33U, // LDMDA_UPD + 1136U, // LDMDB + 33U, // LDMDB_UPD + 1136U, // LDMIA + 33U, // LDMIA_UPD + 1136U, // LDMIB + 33U, // LDMIB_UPD + 262272U, // LDRBT_POST_IMM + 262272U, // LDRBT_POST_REG + 262272U, // LDRB_POST_IMM + 262272U, // LDRB_POST_REG + 144U, // LDRB_PRE_IMM + 152U, // LDRB_PRE_REG + 160U, // LDRBi12 + 168U, // LDRBrs + 294912U, // LDRD + 2424832U, // LDRD_POST + 360448U, // LDRD_PRE + 8U, // LDREX + 8U, // LDREXB + 0U, // LDREXD + 8U, // LDREXH + 176U, // LDRH + 393344U, // LDRHTi + 426112U, // LDRHTr + 458880U, // LDRH_POST + 184U, // LDRH_PRE + 176U, // LDRSB + 393344U, // LDRSBTi + 426112U, // LDRSBTr + 458880U, // LDRSB_POST + 184U, // LDRSB_PRE + 176U, // LDRSH + 393344U, // LDRSHTi + 426112U, // LDRSHTr + 458880U, // LDRSH_POST + 184U, // LDRSH_PRE + 262272U, // LDRT_POST_IMM + 262272U, // LDRT_POST_REG + 262272U, // LDR_POST_IMM + 262272U, // LDR_POST_REG + 144U, // LDR_PRE_IMM + 152U, // LDR_PRE_REG + 160U, // LDRcp + 160U, // LDRi12 + 168U, // LDRrs + 4690993U, // MCR + 192U, // MCR2 + 6788145U, // MCRR + 524312U, // MCRR2 + 35651584U, // MLA + 35651584U, // MLS + 0U, // MOVPCLR + 1112U, // MOVTi16 + 96U, // MOVi + 1024U, // MOVi16 + 1024U, // MOVr + 1024U, // MOVr_TC + 104U, // MOVsi + 64U, // MOVsr + 0U, // MRC + 0U, // MRC2 + 0U, // MRRC + 0U, // MRRC2 + 2U, // MRS + 200U, // MRSbanked + 2U, // MRSsys + 33U, // MSR + 0U, // MSRbanked + 3U, // MSRi + 0U, // MUL + 96U, // MVNi + 1024U, // MVNr + 104U, // MVNsi + 64U, // MVNsr + 98304U, // ORRri + 0U, // ORRrr + 131072U, // ORRrsi + 0U, // ORRrsr + 8388608U, // PKHBT + 10485760U, // PKHTB + 0U, // PLDWi12 + 0U, // PLDWrs + 0U, // PLDi12 + 0U, // PLDrs + 0U, // PLIi12 + 0U, // PLIrs + 0U, // QADD + 0U, // QADD16 + 0U, // QADD8 + 0U, // QASX + 0U, // QDADD + 0U, // QDSUB + 0U, // QSAX + 0U, // QSUB + 0U, // QSUB16 + 0U, // QSUB8 + 1024U, // RBIT + 1024U, // REV + 1024U, // REV16 + 1024U, // REVSH + 0U, // RFEDA + 0U, // RFEDA_UPD + 0U, // RFEDB + 0U, // RFEDB_UPD + 0U, // RFEIA + 0U, // RFEIA_UPD + 0U, // RFEIB + 0U, // RFEIB_UPD + 98304U, // RSBri + 0U, // RSBrr + 131072U, // RSBrsi + 0U, // RSBrsr + 98304U, // RSCri + 0U, // RSCrr + 131072U, // RSCrsi + 0U, // RSCrsr + 0U, // SADD16 + 0U, // SADD8 + 0U, // SASX + 98304U, // SBCri + 0U, // SBCrr + 131072U, // SBCrsi + 0U, // SBCrsr + 69206016U, // SBFX + 0U, // SDIV + 0U, // SEL + 0U, // SETEND + 0U, // SETPAN + 1048U, // SHA1C + 0U, // SHA1H + 1048U, // SHA1M + 1048U, // SHA1P + 1048U, // SHA1SU0 + 0U, // SHA1SU1 + 1048U, // SHA256H + 1048U, // SHA256H2 + 0U, // SHA256SU0 + 1048U, // SHA256SU1 + 0U, // SHADD16 + 0U, // SHADD8 + 0U, // SHASX + 0U, // SHSAX + 0U, // SHSUB16 + 0U, // SHSUB8 + 0U, // SMC + 35651584U, // SMLABB + 35651584U, // SMLABT + 35651584U, // SMLAD + 35651584U, // SMLADX + 0U, // SMLAL + 35651584U, // SMLALBB + 35651584U, // SMLALBT + 35651584U, // SMLALD + 35651584U, // SMLALDX + 35651584U, // SMLALTB + 35651584U, // SMLALTT + 35651584U, // SMLATB + 35651584U, // SMLATT + 35651584U, // SMLAWB + 35651584U, // SMLAWT + 35651584U, // SMLSD + 35651584U, // SMLSDX + 35651584U, // SMLSLD + 35651584U, // SMLSLDX + 35651584U, // SMMLA + 35651584U, // SMMLAR + 35651584U, // SMMLS + 35651584U, // SMMLSR + 0U, // SMMUL + 0U, // SMMULR + 0U, // SMUAD + 0U, // SMUADX + 0U, // SMULBB + 0U, // SMULBT + 35651584U, // SMULL + 0U, // SMULTB + 0U, // SMULTT + 0U, // SMULWB + 0U, // SMULWT + 0U, // SMUSD + 0U, // SMUSDX + 0U, // SRSDA + 0U, // SRSDA_UPD + 0U, // SRSDB + 0U, // SRSDB_UPD + 0U, // SRSIA + 0U, // SRSIA_UPD + 0U, // SRSIB + 0U, // SRSIB_UPD + 6352U, // SSAT + 1232U, // SSAT16 + 0U, // SSAX + 0U, // SSUB16 + 0U, // SSUB8 + 0U, // STC2L_OFFSET + 1U, // STC2L_OPTION + 2U, // STC2L_POST + 0U, // STC2L_PRE + 0U, // STC2_OFFSET + 1U, // STC2_OPTION + 2U, // STC2_POST + 0U, // STC2_PRE + 122U, // STCL_OFFSET + 196738U, // STCL_OPTION + 229506U, // STCL_POST + 138U, // STCL_PRE + 122U, // STC_OFFSET + 196738U, // STC_OPTION + 229506U, // STC_POST + 138U, // STC_PRE + 8U, // STL + 8U, // STLB + 557056U, // STLEX + 557056U, // STLEXB + 216U, // STLEXD + 557056U, // STLEXH + 8U, // STLH + 1136U, // STMDA + 33U, // STMDA_UPD + 1136U, // STMDB + 33U, // STMDB_UPD + 1136U, // STMIA + 33U, // STMIA_UPD + 1136U, // STMIB + 33U, // STMIB_UPD + 262272U, // STRBT_POST_IMM + 262272U, // STRBT_POST_REG + 262272U, // STRB_POST_IMM + 262272U, // STRB_POST_REG + 144U, // STRB_PRE_IMM + 152U, // STRB_PRE_REG + 160U, // STRBi12 + 168U, // STRBrs + 294912U, // STRD + 2424920U, // STRD_POST + 360536U, // STRD_PRE + 557056U, // STREX + 557056U, // STREXB + 216U, // STREXD + 557056U, // STREXH + 176U, // STRH + 393344U, // STRHTi + 426112U, // STRHTr + 458880U, // STRH_POST + 184U, // STRH_PRE + 262272U, // STRT_POST_IMM + 262272U, // STRT_POST_REG + 262272U, // STR_POST_IMM + 262272U, // STR_POST_REG + 144U, // STR_PRE_IMM + 152U, // STR_PRE_REG + 160U, // STRi12 + 168U, // STRrs + 98304U, // SUBri + 0U, // SUBrr + 131072U, // SUBrsi + 0U, // SUBrsr + 0U, // SVC + 557056U, // SWP + 557056U, // SWPB + 12582912U, // SXTAB + 12582912U, // SXTAB16 + 12582912U, // SXTAH + 7168U, // SXTB + 7168U, // SXTB16 + 7168U, // SXTH + 96U, // TEQri + 1024U, // TEQrr + 104U, // TEQrsi + 64U, // TEQrsr + 0U, // TRAP + 0U, // TRAPNaCl + 0U, // TSB + 96U, // TSTri + 1024U, // TSTrr + 104U, // TSTrsi + 64U, // TSTrsr + 0U, // UADD16 + 0U, // UADD8 + 0U, // UASX + 69206016U, // UBFX + 0U, // UDF + 0U, // UDIV + 0U, // UHADD16 + 0U, // UHADD8 + 0U, // UHASX + 0U, // UHSAX + 0U, // UHSUB16 + 0U, // UHSUB8 + 35651584U, // UMAAL + 0U, // UMLAL + 35651584U, // UMULL + 0U, // UQADD16 + 0U, // UQADD8 + 0U, // UQASX + 0U, // UQSAX + 0U, // UQSUB16 + 0U, // UQSUB8 + 0U, // USAD8 + 35651584U, // USADA8 + 14680064U, // USAT + 0U, // USAT16 + 0U, // USAX + 0U, // USUB16 + 0U, // USUB8 + 12582912U, // UXTAB + 12582912U, // UXTAB16 + 12582912U, // UXTAH + 7168U, // UXTB + 7168U, // UXTB16 + 7168U, // UXTH + 1048U, // VABALsv2i64 + 1048U, // VABALsv4i32 + 1048U, // VABALsv8i16 + 1048U, // VABALuv2i64 + 1048U, // VABALuv4i32 + 1048U, // VABALuv8i16 + 1048U, // VABAsv16i8 + 1048U, // VABAsv2i32 + 1048U, // VABAsv4i16 + 1048U, // VABAsv4i32 + 1048U, // VABAsv8i16 + 1048U, // VABAsv8i8 + 1048U, // VABAuv16i8 + 1048U, // VABAuv2i32 + 1048U, // VABAuv4i16 + 1048U, // VABAuv4i32 + 1048U, // VABAuv8i16 + 1048U, // VABAuv8i8 + 1112U, // VABDLsv2i64 + 1112U, // VABDLsv4i32 + 1112U, // VABDLsv8i16 + 1112U, // VABDLuv2i64 + 1112U, // VABDLuv4i32 + 1112U, // VABDLuv8i16 + 70705U, // VABDfd + 70705U, // VABDfq + 70705U, // VABDhd + 70705U, // VABDhq + 1112U, // VABDsv16i8 + 1112U, // VABDsv2i32 + 1112U, // VABDsv4i16 + 1112U, // VABDsv4i32 + 1112U, // VABDsv8i16 + 1112U, // VABDsv8i8 + 1112U, // VABDuv16i8 + 1112U, // VABDuv2i32 + 1112U, // VABDuv4i16 + 1112U, // VABDuv4i32 + 1112U, // VABDuv8i16 + 1112U, // VABDuv8i8 + 33U, // VABSD + 33U, // VABSH + 33U, // VABSS + 33U, // VABSfd + 33U, // VABSfq + 33U, // VABShd + 33U, // VABShq + 0U, // VABSv16i8 + 0U, // VABSv2i32 + 0U, // VABSv4i16 + 0U, // VABSv4i32 + 0U, // VABSv8i16 + 0U, // VABSv8i8 + 70705U, // VACGEfd + 70705U, // VACGEfq + 70705U, // VACGEhd + 70705U, // VACGEhq + 70705U, // VACGTfd + 70705U, // VACGTfq + 70705U, // VACGThd + 70705U, // VACGThq + 70705U, // VADDD + 70705U, // VADDH + 1112U, // VADDHNv2i32 + 1112U, // VADDHNv4i16 + 1112U, // VADDHNv8i8 + 1112U, // VADDLsv2i64 + 1112U, // VADDLsv4i32 + 1112U, // VADDLsv8i16 + 1112U, // VADDLuv2i64 + 1112U, // VADDLuv4i32 + 1112U, // VADDLuv8i16 + 70705U, // VADDS + 1112U, // VADDWsv2i64 + 1112U, // VADDWsv4i32 + 1112U, // VADDWsv8i16 + 1112U, // VADDWuv2i64 + 1112U, // VADDWuv4i32 + 1112U, // VADDWuv8i16 + 70705U, // VADDfd + 70705U, // VADDfq + 70705U, // VADDhd + 70705U, // VADDhq + 1112U, // VADDv16i8 + 1112U, // VADDv1i64 + 1112U, // VADDv2i32 + 1112U, // VADDv2i64 + 1112U, // VADDv4i16 + 1112U, // VADDv4i32 + 1112U, // VADDv8i16 + 1112U, // VADDv8i8 + 0U, // VANDd + 0U, // VANDq + 0U, // VBICd + 0U, // VBICiv2i32 + 0U, // VBICiv4i16 + 0U, // VBICiv4i32 + 0U, // VBICiv8i16 + 0U, // VBICq + 589912U, // VBIFd + 589912U, // VBIFq + 589912U, // VBITd + 589912U, // VBITq + 589912U, // VBSLd + 589912U, // VBSLq + 622680U, // VCADDv2f32 + 622680U, // VCADDv4f16 + 622680U, // VCADDv4f32 + 622680U, // VCADDv8f16 + 70705U, // VCEQfd + 70705U, // VCEQfq + 70705U, // VCEQhd + 70705U, // VCEQhq + 1112U, // VCEQv16i8 + 1112U, // VCEQv2i32 + 1112U, // VCEQv4i16 + 1112U, // VCEQv4i32 + 1112U, // VCEQv8i16 + 1112U, // VCEQv8i8 + 3U, // VCEQzv16i8 + 225U, // VCEQzv2f32 + 3U, // VCEQzv2i32 + 225U, // VCEQzv4f16 + 225U, // VCEQzv4f32 + 3U, // VCEQzv4i16 + 3U, // VCEQzv4i32 + 225U, // VCEQzv8f16 + 3U, // VCEQzv8i16 + 3U, // VCEQzv8i8 + 70705U, // VCGEfd + 70705U, // VCGEfq + 70705U, // VCGEhd + 70705U, // VCGEhq + 1112U, // VCGEsv16i8 + 1112U, // VCGEsv2i32 + 1112U, // VCGEsv4i16 + 1112U, // VCGEsv4i32 + 1112U, // VCGEsv8i16 + 1112U, // VCGEsv8i8 + 1112U, // VCGEuv16i8 + 1112U, // VCGEuv2i32 + 1112U, // VCGEuv4i16 + 1112U, // VCGEuv4i32 + 1112U, // VCGEuv8i16 + 1112U, // VCGEuv8i8 + 3U, // VCGEzv16i8 + 225U, // VCGEzv2f32 + 3U, // VCGEzv2i32 + 225U, // VCGEzv4f16 + 225U, // VCGEzv4f32 + 3U, // VCGEzv4i16 + 3U, // VCGEzv4i32 + 225U, // VCGEzv8f16 + 3U, // VCGEzv8i16 + 3U, // VCGEzv8i8 + 70705U, // VCGTfd + 70705U, // VCGTfq + 70705U, // VCGThd + 70705U, // VCGThq + 1112U, // VCGTsv16i8 + 1112U, // VCGTsv2i32 + 1112U, // VCGTsv4i16 + 1112U, // VCGTsv4i32 + 1112U, // VCGTsv8i16 + 1112U, // VCGTsv8i8 + 1112U, // VCGTuv16i8 + 1112U, // VCGTuv2i32 + 1112U, // VCGTuv4i16 + 1112U, // VCGTuv4i32 + 1112U, // VCGTuv8i16 + 1112U, // VCGTuv8i8 + 3U, // VCGTzv16i8 + 225U, // VCGTzv2f32 + 3U, // VCGTzv2i32 + 225U, // VCGTzv4f16 + 225U, // VCGTzv4f32 + 3U, // VCGTzv4i16 + 3U, // VCGTzv4i32 + 225U, // VCGTzv8f16 + 3U, // VCGTzv8i16 + 3U, // VCGTzv8i8 + 3U, // VCLEzv16i8 + 225U, // VCLEzv2f32 + 3U, // VCLEzv2i32 + 225U, // VCLEzv4f16 + 225U, // VCLEzv4f32 + 3U, // VCLEzv4i16 + 3U, // VCLEzv4i32 + 225U, // VCLEzv8f16 + 3U, // VCLEzv8i16 + 3U, // VCLEzv8i8 + 0U, // VCLSv16i8 + 0U, // VCLSv2i32 + 0U, // VCLSv4i16 + 0U, // VCLSv4i32 + 0U, // VCLSv8i16 + 0U, // VCLSv8i8 + 3U, // VCLTzv16i8 + 225U, // VCLTzv2f32 + 3U, // VCLTzv2i32 + 225U, // VCLTzv4f16 + 225U, // VCLTzv4f32 + 3U, // VCLTzv4i16 + 3U, // VCLTzv4i32 + 225U, // VCLTzv8f16 + 3U, // VCLTzv8i16 + 3U, // VCLTzv8i8 + 0U, // VCLZv16i8 + 0U, // VCLZv2i32 + 0U, // VCLZv4i16 + 0U, // VCLZv4i32 + 0U, // VCLZv8i16 + 0U, // VCLZv8i8 + 655384U, // VCMLAv2f32 + 17276952U, // VCMLAv2f32_indexed + 655384U, // VCMLAv4f16 + 17276952U, // VCMLAv4f16_indexed + 655384U, // VCMLAv4f32 + 17276952U, // VCMLAv4f32_indexed + 655384U, // VCMLAv8f16 + 17276952U, // VCMLAv8f16_indexed + 33U, // VCMPD + 33U, // VCMPED + 33U, // VCMPEH + 33U, // VCMPES + 0U, // VCMPEZD + 0U, // VCMPEZH + 0U, // VCMPEZS + 33U, // VCMPH + 33U, // VCMPS + 0U, // VCMPZD + 0U, // VCMPZH + 0U, // VCMPZS + 1024U, // VCNTd + 1024U, // VCNTq + 0U, // VCVTANSDf + 0U, // VCVTANSDh + 0U, // VCVTANSQf + 0U, // VCVTANSQh + 0U, // VCVTANUDf + 0U, // VCVTANUDh + 0U, // VCVTANUQf + 0U, // VCVTANUQh + 0U, // VCVTASD + 0U, // VCVTASH + 0U, // VCVTASS + 0U, // VCVTAUD + 0U, // VCVTAUH + 0U, // VCVTAUS + 0U, // VCVTBDH + 0U, // VCVTBHD + 0U, // VCVTBHS + 0U, // VCVTBSH + 0U, // VCVTDS + 0U, // VCVTMNSDf + 0U, // VCVTMNSDh + 0U, // VCVTMNSQf + 0U, // VCVTMNSQh + 0U, // VCVTMNUDf + 0U, // VCVTMNUDh + 0U, // VCVTMNUQf + 0U, // VCVTMNUQh + 0U, // VCVTMSD + 0U, // VCVTMSH + 0U, // VCVTMSS + 0U, // VCVTMUD + 0U, // VCVTMUH + 0U, // VCVTMUS + 0U, // VCVTNNSDf + 0U, // VCVTNNSDh + 0U, // VCVTNNSQf + 0U, // VCVTNNSQh + 0U, // VCVTNNUDf + 0U, // VCVTNNUDh + 0U, // VCVTNNUQf + 0U, // VCVTNNUQh + 0U, // VCVTNSD + 0U, // VCVTNSH + 0U, // VCVTNSS + 0U, // VCVTNUD + 0U, // VCVTNUH + 0U, // VCVTNUS + 0U, // VCVTPNSDf + 0U, // VCVTPNSDh + 0U, // VCVTPNSQf + 0U, // VCVTPNSQh + 0U, // VCVTPNUDf + 0U, // VCVTPNUDh + 0U, // VCVTPNUQf + 0U, // VCVTPNUQh + 0U, // VCVTPSD + 0U, // VCVTPSH + 0U, // VCVTPSS + 0U, // VCVTPUD + 0U, // VCVTPUH + 0U, // VCVTPUS + 0U, // VCVTSD + 0U, // VCVTTDH + 0U, // VCVTTHD + 0U, // VCVTTHS + 0U, // VCVTTSH + 0U, // VCVTf2h + 0U, // VCVTf2sd + 0U, // VCVTf2sq + 0U, // VCVTf2ud + 0U, // VCVTf2uq + 35U, // VCVTf2xsd + 35U, // VCVTf2xsq + 35U, // VCVTf2xud + 35U, // VCVTf2xuq + 0U, // VCVTh2f + 0U, // VCVTh2sd + 0U, // VCVTh2sq + 0U, // VCVTh2ud + 0U, // VCVTh2uq + 35U, // VCVTh2xsd + 35U, // VCVTh2xsq + 35U, // VCVTh2xud + 35U, // VCVTh2xuq + 0U, // VCVTs2fd + 0U, // VCVTs2fq + 0U, // VCVTs2hd + 0U, // VCVTs2hq + 0U, // VCVTu2fd + 0U, // VCVTu2fq + 0U, // VCVTu2hd + 0U, // VCVTu2hq + 35U, // VCVTxs2fd + 35U, // VCVTxs2fq + 35U, // VCVTxs2hd + 35U, // VCVTxs2hq + 35U, // VCVTxu2fd + 35U, // VCVTxu2fq + 35U, // VCVTxu2hd + 35U, // VCVTxu2hq + 70705U, // VDIVD + 70705U, // VDIVH + 70705U, // VDIVS + 1024U, // VDUP16d + 1024U, // VDUP16q + 1024U, // VDUP32d + 1024U, // VDUP32q + 1024U, // VDUP8d + 1024U, // VDUP8q + 9216U, // VDUPLN16d + 9216U, // VDUPLN16q + 9216U, // VDUPLN32d + 9216U, // VDUPLN32q + 9216U, // VDUPLN8d + 9216U, // VDUPLN8q + 0U, // VEORd + 0U, // VEORq + 35651584U, // VEXTd16 + 35651584U, // VEXTd32 + 35651584U, // VEXTd8 + 35651584U, // VEXTq16 + 35651584U, // VEXTq32 + 35651584U, // VEXTq64 + 35651584U, // VEXTq8 + 68659U, // VFMAD + 68659U, // VFMAH + 68659U, // VFMAS + 68659U, // VFMAfd + 68659U, // VFMAfq + 68659U, // VFMAhd + 68659U, // VFMAhq + 68659U, // VFMSD + 68659U, // VFMSH + 68659U, // VFMSS + 68659U, // VFMSfd + 68659U, // VFMSfq + 68659U, // VFMShd + 68659U, // VFMShq + 68659U, // VFNMAD + 68659U, // VFNMAH + 68659U, // VFNMAS + 68659U, // VFNMSD + 68659U, // VFNMSH + 68659U, // VFNMSS + 9216U, // VGETLNi32 + 3U, // VGETLNs16 + 3U, // VGETLNs8 + 3U, // VGETLNu16 + 3U, // VGETLNu8 + 1112U, // VHADDsv16i8 + 1112U, // VHADDsv2i32 + 1112U, // VHADDsv4i16 + 1112U, // VHADDsv4i32 + 1112U, // VHADDsv8i16 + 1112U, // VHADDsv8i8 + 1112U, // VHADDuv16i8 + 1112U, // VHADDuv2i32 + 1112U, // VHADDuv4i16 + 1112U, // VHADDuv4i32 + 1112U, // VHADDuv8i16 + 1112U, // VHADDuv8i8 + 1112U, // VHSUBsv16i8 + 1112U, // VHSUBsv2i32 + 1112U, // VHSUBsv4i16 + 1112U, // VHSUBsv4i32 + 1112U, // VHSUBsv8i16 + 1112U, // VHSUBsv8i8 + 1112U, // VHSUBuv16i8 + 1112U, // VHSUBuv2i32 + 1112U, // VHSUBuv4i16 + 1112U, // VHSUBuv4i32 + 1112U, // VHSUBuv8i16 + 1112U, // VHSUBuv8i8 + 0U, // VINSH + 0U, // VJCVT + 32U, // VLD1DUPd16 + 44U, // VLD1DUPd16wb_fixed + 10292U, // VLD1DUPd16wb_register + 32U, // VLD1DUPd32 + 44U, // VLD1DUPd32wb_fixed + 10292U, // VLD1DUPd32wb_register + 32U, // VLD1DUPd8 + 44U, // VLD1DUPd8wb_fixed + 10292U, // VLD1DUPd8wb_register + 32U, // VLD1DUPq16 + 44U, // VLD1DUPq16wb_fixed + 10292U, // VLD1DUPq16wb_register + 32U, // VLD1DUPq32 + 44U, // VLD1DUPq32wb_fixed + 10292U, // VLD1DUPq32wb_register + 32U, // VLD1DUPq8 + 44U, // VLD1DUPq8wb_fixed + 10292U, // VLD1DUPq8wb_register + 699628U, // VLD1LNd16 + 732404U, // VLD1LNd16_UPD + 699628U, // VLD1LNd32 + 732404U, // VLD1LNd32_UPD + 699628U, // VLD1LNd8 + 732404U, // VLD1LNd8_UPD + 0U, // VLD1LNq16Pseudo + 0U, // VLD1LNq16Pseudo_UPD + 0U, // VLD1LNq32Pseudo + 0U, // VLD1LNq32Pseudo_UPD + 0U, // VLD1LNq8Pseudo + 0U, // VLD1LNq8Pseudo_UPD + 32U, // VLD1d16 + 32U, // VLD1d16Q + 0U, // VLD1d16QPseudo + 44U, // VLD1d16Qwb_fixed + 10292U, // VLD1d16Qwb_register + 32U, // VLD1d16T + 0U, // VLD1d16TPseudo + 44U, // VLD1d16Twb_fixed + 10292U, // VLD1d16Twb_register + 44U, // VLD1d16wb_fixed + 10292U, // VLD1d16wb_register + 32U, // VLD1d32 + 32U, // VLD1d32Q + 0U, // VLD1d32QPseudo + 44U, // VLD1d32Qwb_fixed + 10292U, // VLD1d32Qwb_register + 32U, // VLD1d32T + 0U, // VLD1d32TPseudo + 44U, // VLD1d32Twb_fixed + 10292U, // VLD1d32Twb_register + 44U, // VLD1d32wb_fixed + 10292U, // VLD1d32wb_register + 32U, // VLD1d64 + 32U, // VLD1d64Q + 0U, // VLD1d64QPseudo + 0U, // VLD1d64QPseudoWB_fixed + 0U, // VLD1d64QPseudoWB_register + 44U, // VLD1d64Qwb_fixed + 10292U, // VLD1d64Qwb_register + 32U, // VLD1d64T + 0U, // VLD1d64TPseudo + 0U, // VLD1d64TPseudoWB_fixed + 0U, // VLD1d64TPseudoWB_register + 44U, // VLD1d64Twb_fixed + 10292U, // VLD1d64Twb_register + 44U, // VLD1d64wb_fixed + 10292U, // VLD1d64wb_register + 32U, // VLD1d8 + 32U, // VLD1d8Q + 0U, // VLD1d8QPseudo + 44U, // VLD1d8Qwb_fixed + 10292U, // VLD1d8Qwb_register + 32U, // VLD1d8T + 0U, // VLD1d8TPseudo + 44U, // VLD1d8Twb_fixed + 10292U, // VLD1d8Twb_register + 44U, // VLD1d8wb_fixed + 10292U, // VLD1d8wb_register + 32U, // VLD1q16 + 0U, // VLD1q16HighQPseudo + 0U, // VLD1q16HighTPseudo + 0U, // VLD1q16LowQPseudo_UPD + 0U, // VLD1q16LowTPseudo_UPD + 44U, // VLD1q16wb_fixed + 10292U, // VLD1q16wb_register + 32U, // VLD1q32 + 0U, // VLD1q32HighQPseudo + 0U, // VLD1q32HighTPseudo + 0U, // VLD1q32LowQPseudo_UPD + 0U, // VLD1q32LowTPseudo_UPD + 44U, // VLD1q32wb_fixed + 10292U, // VLD1q32wb_register + 32U, // VLD1q64 + 0U, // VLD1q64HighQPseudo + 0U, // VLD1q64HighTPseudo + 0U, // VLD1q64LowQPseudo_UPD + 0U, // VLD1q64LowTPseudo_UPD + 44U, // VLD1q64wb_fixed + 10292U, // VLD1q64wb_register + 32U, // VLD1q8 + 0U, // VLD1q8HighQPseudo + 0U, // VLD1q8HighTPseudo + 0U, // VLD1q8LowQPseudo_UPD + 0U, // VLD1q8LowTPseudo_UPD + 44U, // VLD1q8wb_fixed + 10292U, // VLD1q8wb_register + 32U, // VLD2DUPd16 + 44U, // VLD2DUPd16wb_fixed + 10292U, // VLD2DUPd16wb_register + 32U, // VLD2DUPd16x2 + 44U, // VLD2DUPd16x2wb_fixed + 10292U, // VLD2DUPd16x2wb_register + 32U, // VLD2DUPd32 + 44U, // VLD2DUPd32wb_fixed + 10292U, // VLD2DUPd32wb_register + 32U, // VLD2DUPd32x2 + 44U, // VLD2DUPd32x2wb_fixed + 10292U, // VLD2DUPd32x2wb_register + 32U, // VLD2DUPd8 + 44U, // VLD2DUPd8wb_fixed + 10292U, // VLD2DUPd8wb_register + 32U, // VLD2DUPd8x2 + 44U, // VLD2DUPd8x2wb_fixed + 10292U, // VLD2DUPd8x2wb_register + 0U, // VLD2DUPq16EvenPseudo + 0U, // VLD2DUPq16OddPseudo + 0U, // VLD2DUPq32EvenPseudo + 0U, // VLD2DUPq32OddPseudo + 0U, // VLD2DUPq8EvenPseudo + 0U, // VLD2DUPq8OddPseudo + 766196U, // VLD2LNd16 + 0U, // VLD2LNd16Pseudo + 0U, // VLD2LNd16Pseudo_UPD + 799996U, // VLD2LNd16_UPD + 766196U, // VLD2LNd32 + 0U, // VLD2LNd32Pseudo + 0U, // VLD2LNd32Pseudo_UPD + 799996U, // VLD2LNd32_UPD + 766196U, // VLD2LNd8 + 0U, // VLD2LNd8Pseudo + 0U, // VLD2LNd8Pseudo_UPD + 799996U, // VLD2LNd8_UPD + 766196U, // VLD2LNq16 + 0U, // VLD2LNq16Pseudo + 0U, // VLD2LNq16Pseudo_UPD + 799996U, // VLD2LNq16_UPD + 766196U, // VLD2LNq32 + 0U, // VLD2LNq32Pseudo + 0U, // VLD2LNq32Pseudo_UPD + 799996U, // VLD2LNq32_UPD + 32U, // VLD2b16 + 44U, // VLD2b16wb_fixed + 10292U, // VLD2b16wb_register + 32U, // VLD2b32 + 44U, // VLD2b32wb_fixed + 10292U, // VLD2b32wb_register + 32U, // VLD2b8 + 44U, // VLD2b8wb_fixed + 10292U, // VLD2b8wb_register + 32U, // VLD2d16 + 44U, // VLD2d16wb_fixed + 10292U, // VLD2d16wb_register + 32U, // VLD2d32 + 44U, // VLD2d32wb_fixed + 10292U, // VLD2d32wb_register + 32U, // VLD2d8 + 44U, // VLD2d8wb_fixed + 10292U, // VLD2d8wb_register + 32U, // VLD2q16 + 0U, // VLD2q16Pseudo + 0U, // VLD2q16PseudoWB_fixed + 0U, // VLD2q16PseudoWB_register + 44U, // VLD2q16wb_fixed + 10292U, // VLD2q16wb_register + 32U, // VLD2q32 + 0U, // VLD2q32Pseudo + 0U, // VLD2q32PseudoWB_fixed + 0U, // VLD2q32PseudoWB_register + 44U, // VLD2q32wb_fixed + 10292U, // VLD2q32wb_register + 32U, // VLD2q8 + 0U, // VLD2q8Pseudo + 0U, // VLD2q8PseudoWB_fixed + 0U, // VLD2q8PseudoWB_register + 44U, // VLD2q8wb_fixed + 10292U, // VLD2q8wb_register + 14596U, // VLD3DUPd16 + 0U, // VLD3DUPd16Pseudo + 0U, // VLD3DUPd16Pseudo_UPD + 834820U, // VLD3DUPd16_UPD + 14596U, // VLD3DUPd32 + 0U, // VLD3DUPd32Pseudo + 0U, // VLD3DUPd32Pseudo_UPD + 834820U, // VLD3DUPd32_UPD + 14596U, // VLD3DUPd8 + 0U, // VLD3DUPd8Pseudo + 0U, // VLD3DUPd8Pseudo_UPD + 834820U, // VLD3DUPd8_UPD + 14596U, // VLD3DUPq16 + 0U, // VLD3DUPq16EvenPseudo + 0U, // VLD3DUPq16OddPseudo + 834820U, // VLD3DUPq16_UPD + 14596U, // VLD3DUPq32 + 0U, // VLD3DUPq32EvenPseudo + 0U, // VLD3DUPq32OddPseudo + 834820U, // VLD3DUPq32_UPD + 14596U, // VLD3DUPq8 + 0U, // VLD3DUPq8EvenPseudo + 0U, // VLD3DUPq8OddPseudo + 834820U, // VLD3DUPq8_UPD + 865532U, // VLD3LNd16 + 0U, // VLD3LNd16Pseudo + 0U, // VLD3LNd16Pseudo_UPD + 896268U, // VLD3LNd16_UPD + 865532U, // VLD3LNd32 + 0U, // VLD3LNd32Pseudo + 0U, // VLD3LNd32Pseudo_UPD + 896268U, // VLD3LNd32_UPD + 865532U, // VLD3LNd8 + 0U, // VLD3LNd8Pseudo + 0U, // VLD3LNd8Pseudo_UPD + 896268U, // VLD3LNd8_UPD + 865532U, // VLD3LNq16 + 0U, // VLD3LNq16Pseudo + 0U, // VLD3LNq16Pseudo_UPD + 896268U, // VLD3LNq16_UPD + 865532U, // VLD3LNq32 + 0U, // VLD3LNq32Pseudo + 0U, // VLD3LNq32Pseudo_UPD + 896268U, // VLD3LNq32_UPD + 119537664U, // VLD3d16 + 0U, // VLD3d16Pseudo + 0U, // VLD3d16Pseudo_UPD + 153092096U, // VLD3d16_UPD + 119537664U, // VLD3d32 + 0U, // VLD3d32Pseudo + 0U, // VLD3d32Pseudo_UPD + 153092096U, // VLD3d32_UPD + 119537664U, // VLD3d8 + 0U, // VLD3d8Pseudo + 0U, // VLD3d8Pseudo_UPD + 153092096U, // VLD3d8_UPD + 119537664U, // VLD3q16 + 0U, // VLD3q16Pseudo_UPD + 153092096U, // VLD3q16_UPD + 0U, // VLD3q16oddPseudo + 0U, // VLD3q16oddPseudo_UPD + 119537664U, // VLD3q32 + 0U, // VLD3q32Pseudo_UPD + 153092096U, // VLD3q32_UPD + 0U, // VLD3q32oddPseudo + 0U, // VLD3q32oddPseudo_UPD + 119537664U, // VLD3q8 + 0U, // VLD3q8Pseudo_UPD + 153092096U, // VLD3q8_UPD + 0U, // VLD3q8oddPseudo + 0U, // VLD3q8oddPseudo_UPD + 81172U, // VLD4DUPd16 + 0U, // VLD4DUPd16Pseudo + 0U, // VLD4DUPd16Pseudo_UPD + 16660U, // VLD4DUPd16_UPD + 81172U, // VLD4DUPd32 + 0U, // VLD4DUPd32Pseudo + 0U, // VLD4DUPd32Pseudo_UPD + 16660U, // VLD4DUPd32_UPD + 81172U, // VLD4DUPd8 + 0U, // VLD4DUPd8Pseudo + 0U, // VLD4DUPd8Pseudo_UPD + 16660U, // VLD4DUPd8_UPD + 81172U, // VLD4DUPq16 + 0U, // VLD4DUPq16EvenPseudo + 0U, // VLD4DUPq16OddPseudo + 16660U, // VLD4DUPq16_UPD + 81172U, // VLD4DUPq32 + 0U, // VLD4DUPq32EvenPseudo + 0U, // VLD4DUPq32OddPseudo + 16660U, // VLD4DUPq32_UPD + 81172U, // VLD4DUPq8 + 0U, // VLD4DUPq8EvenPseudo + 0U, // VLD4DUPq8OddPseudo + 16660U, // VLD4DUPq8_UPD + 189346060U, // VLD4LNd16 + 0U, // VLD4LNd16Pseudo + 0U, // VLD4LNd16Pseudo_UPD + 284U, // VLD4LNd16_UPD + 189346060U, // VLD4LNd32 + 0U, // VLD4LNd32Pseudo + 0U, // VLD4LNd32Pseudo_UPD + 284U, // VLD4LNd32_UPD + 189346060U, // VLD4LNd8 + 0U, // VLD4LNd8Pseudo + 0U, // VLD4LNd8Pseudo_UPD + 284U, // VLD4LNd8_UPD + 189346060U, // VLD4LNq16 + 0U, // VLD4LNq16Pseudo + 0U, // VLD4LNq16Pseudo_UPD + 284U, // VLD4LNq16_UPD + 189346060U, // VLD4LNq32 + 0U, // VLD4LNq32Pseudo + 0U, // VLD4LNq32Pseudo_UPD + 284U, // VLD4LNq32_UPD + 572522496U, // VLD4d16 + 0U, // VLD4d16Pseudo + 0U, // VLD4d16Pseudo_UPD + 1646264320U, // VLD4d16_UPD + 572522496U, // VLD4d32 + 0U, // VLD4d32Pseudo + 0U, // VLD4d32Pseudo_UPD + 1646264320U, // VLD4d32_UPD + 572522496U, // VLD4d8 + 0U, // VLD4d8Pseudo + 0U, // VLD4d8Pseudo_UPD + 1646264320U, // VLD4d8_UPD + 572522496U, // VLD4q16 + 0U, // VLD4q16Pseudo_UPD + 1646264320U, // VLD4q16_UPD + 0U, // VLD4q16oddPseudo + 0U, // VLD4q16oddPseudo_UPD + 572522496U, // VLD4q32 + 0U, // VLD4q32Pseudo_UPD + 1646264320U, // VLD4q32_UPD + 0U, // VLD4q32oddPseudo + 0U, // VLD4q32oddPseudo_UPD + 572522496U, // VLD4q8 + 0U, // VLD4q8Pseudo_UPD + 1646264320U, // VLD4q8_UPD + 0U, // VLD4q8oddPseudo + 0U, // VLD4q8oddPseudo_UPD + 33U, // VLDMDDB_UPD + 1136U, // VLDMDIA + 33U, // VLDMDIA_UPD + 0U, // VLDMQIA + 33U, // VLDMSDB_UPD + 1136U, // VLDMSIA + 33U, // VLDMSIA_UPD + 288U, // VLDRD + 296U, // VLDRH + 288U, // VLDRS + 0U, // VLLDM + 0U, // VLSTM + 1112U, // VMAXNMD + 1112U, // VMAXNMH + 1112U, // VMAXNMNDf + 1112U, // VMAXNMNDh + 1112U, // VMAXNMNQf + 1112U, // VMAXNMNQh + 1112U, // VMAXNMS + 70705U, // VMAXfd + 70705U, // VMAXfq + 70705U, // VMAXhd + 70705U, // VMAXhq + 1112U, // VMAXsv16i8 + 1112U, // VMAXsv2i32 + 1112U, // VMAXsv4i16 + 1112U, // VMAXsv4i32 + 1112U, // VMAXsv8i16 + 1112U, // VMAXsv8i8 + 1112U, // VMAXuv16i8 + 1112U, // VMAXuv2i32 + 1112U, // VMAXuv4i16 + 1112U, // VMAXuv4i32 + 1112U, // VMAXuv8i16 + 1112U, // VMAXuv8i8 + 1112U, // VMINNMD + 1112U, // VMINNMH + 1112U, // VMINNMNDf + 1112U, // VMINNMNDh + 1112U, // VMINNMNQf + 1112U, // VMINNMNQh + 1112U, // VMINNMS + 70705U, // VMINfd + 70705U, // VMINfq + 70705U, // VMINhd + 70705U, // VMINhq + 1112U, // VMINsv16i8 + 1112U, // VMINsv2i32 + 1112U, // VMINsv4i16 + 1112U, // VMINsv4i32 + 1112U, // VMINsv8i16 + 1112U, // VMINsv8i8 + 1112U, // VMINuv16i8 + 1112U, // VMINuv2i32 + 1112U, // VMINuv4i16 + 1112U, // VMINuv4i32 + 1112U, // VMINuv8i16 + 1112U, // VMINuv8i8 + 68659U, // VMLAD + 68659U, // VMLAH + 73752U, // VMLALslsv2i32 + 73752U, // VMLALslsv4i16 + 73752U, // VMLALsluv2i32 + 73752U, // VMLALsluv4i16 + 1048U, // VMLALsv2i64 + 1048U, // VMLALsv4i32 + 1048U, // VMLALsv8i16 + 1048U, // VMLALuv2i64 + 1048U, // VMLALuv4i32 + 1048U, // VMLALuv8i16 + 68659U, // VMLAS + 68659U, // VMLAfd + 68659U, // VMLAfq + 68659U, // VMLAhd + 68659U, // VMLAhq + 920627U, // VMLAslfd + 920627U, // VMLAslfq + 920627U, // VMLAslhd + 920627U, // VMLAslhq + 73752U, // VMLAslv2i32 + 73752U, // VMLAslv4i16 + 73752U, // VMLAslv4i32 + 73752U, // VMLAslv8i16 + 1048U, // VMLAv16i8 + 1048U, // VMLAv2i32 + 1048U, // VMLAv4i16 + 1048U, // VMLAv4i32 + 1048U, // VMLAv8i16 + 1048U, // VMLAv8i8 + 68659U, // VMLSD + 68659U, // VMLSH + 73752U, // VMLSLslsv2i32 + 73752U, // VMLSLslsv4i16 + 73752U, // VMLSLsluv2i32 + 73752U, // VMLSLsluv4i16 + 1048U, // VMLSLsv2i64 + 1048U, // VMLSLsv4i32 + 1048U, // VMLSLsv8i16 + 1048U, // VMLSLuv2i64 + 1048U, // VMLSLuv4i32 + 1048U, // VMLSLuv8i16 + 68659U, // VMLSS + 68659U, // VMLSfd + 68659U, // VMLSfq + 68659U, // VMLShd + 68659U, // VMLShq + 920627U, // VMLSslfd + 920627U, // VMLSslfq + 920627U, // VMLSslhd + 920627U, // VMLSslhq + 73752U, // VMLSslv2i32 + 73752U, // VMLSslv4i16 + 73752U, // VMLSslv4i32 + 73752U, // VMLSslv8i16 + 1048U, // VMLSv16i8 + 1048U, // VMLSv2i32 + 1048U, // VMLSv4i16 + 1048U, // VMLSv4i32 + 1048U, // VMLSv8i16 + 1048U, // VMLSv8i8 + 33U, // VMOVD + 0U, // VMOVDRR + 0U, // VMOVH + 33U, // VMOVHR + 0U, // VMOVLsv2i64 + 0U, // VMOVLsv4i32 + 0U, // VMOVLsv8i16 + 0U, // VMOVLuv2i64 + 0U, // VMOVLuv4i32 + 0U, // VMOVLuv8i16 + 0U, // VMOVNv2i32 + 0U, // VMOVNv4i16 + 0U, // VMOVNv8i8 + 33U, // VMOVRH + 0U, // VMOVRRD + 35651584U, // VMOVRRS + 1024U, // VMOVRS + 33U, // VMOVS + 1024U, // VMOVSR + 35651584U, // VMOVSRR + 0U, // VMOVv16i8 + 0U, // VMOVv1i64 + 1U, // VMOVv2f32 + 0U, // VMOVv2i32 + 0U, // VMOVv2i64 + 1U, // VMOVv4f32 + 0U, // VMOVv4i16 + 0U, // VMOVv4i32 + 0U, // VMOVv8i16 + 0U, // VMOVv8i8 + 4U, // VMRS + 5U, // VMRS_FPEXC + 5U, // VMRS_FPINST + 5U, // VMRS_FPINST2 + 5U, // VMRS_FPSID + 6U, // VMRS_MVFR0 + 6U, // VMRS_MVFR1 + 6U, // VMRS_MVFR2 + 0U, // VMSR + 0U, // VMSR_FPEXC + 0U, // VMSR_FPINST + 0U, // VMSR_FPINST2 + 0U, // VMSR_FPSID + 70705U, // VMULD + 70705U, // VMULH + 1112U, // VMULLp64 + 0U, // VMULLp8 + 17496U, // VMULLslsv2i32 + 17496U, // VMULLslsv4i16 + 17496U, // VMULLsluv2i32 + 17496U, // VMULLsluv4i16 + 1112U, // VMULLsv2i64 + 1112U, // VMULLsv4i32 + 1112U, // VMULLsv8i16 + 1112U, // VMULLuv2i64 + 1112U, // VMULLuv4i32 + 1112U, // VMULLuv8i16 + 70705U, // VMULS + 70705U, // VMULfd + 70705U, // VMULfq + 70705U, // VMULhd + 70705U, // VMULhq + 0U, // VMULpd + 0U, // VMULpq + 955441U, // VMULslfd + 955441U, // VMULslfq + 955441U, // VMULslhd + 955441U, // VMULslhq + 17496U, // VMULslv2i32 + 17496U, // VMULslv4i16 + 17496U, // VMULslv4i32 + 17496U, // VMULslv8i16 + 1112U, // VMULv16i8 + 1112U, // VMULv2i32 + 1112U, // VMULv4i16 + 1112U, // VMULv4i32 + 1112U, // VMULv8i16 + 1112U, // VMULv8i8 + 1024U, // VMVNd + 1024U, // VMVNq + 0U, // VMVNv2i32 + 0U, // VMVNv4i16 + 0U, // VMVNv4i32 + 0U, // VMVNv8i16 + 33U, // VNEGD + 33U, // VNEGH + 33U, // VNEGS + 33U, // VNEGf32q + 33U, // VNEGfd + 33U, // VNEGhd + 33U, // VNEGhq + 0U, // VNEGs16d + 0U, // VNEGs16q + 0U, // VNEGs32d + 0U, // VNEGs32q + 0U, // VNEGs8d + 0U, // VNEGs8q + 68659U, // VNMLAD + 68659U, // VNMLAH + 68659U, // VNMLAS + 68659U, // VNMLSD + 68659U, // VNMLSH + 68659U, // VNMLSS + 70705U, // VNMULD + 70705U, // VNMULH + 70705U, // VNMULS + 0U, // VORNd + 0U, // VORNq + 0U, // VORRd + 0U, // VORRiv2i32 + 0U, // VORRiv4i16 + 0U, // VORRiv4i32 + 0U, // VORRiv8i16 + 0U, // VORRq + 0U, // VPADALsv16i8 + 0U, // VPADALsv2i32 + 0U, // VPADALsv4i16 + 0U, // VPADALsv4i32 + 0U, // VPADALsv8i16 + 0U, // VPADALsv8i8 + 0U, // VPADALuv16i8 + 0U, // VPADALuv2i32 + 0U, // VPADALuv4i16 + 0U, // VPADALuv4i32 + 0U, // VPADALuv8i16 + 0U, // VPADALuv8i8 + 0U, // VPADDLsv16i8 + 0U, // VPADDLsv2i32 + 0U, // VPADDLsv4i16 + 0U, // VPADDLsv4i32 + 0U, // VPADDLsv8i16 + 0U, // VPADDLsv8i8 + 0U, // VPADDLuv16i8 + 0U, // VPADDLuv2i32 + 0U, // VPADDLuv4i16 + 0U, // VPADDLuv4i32 + 0U, // VPADDLuv8i16 + 0U, // VPADDLuv8i8 + 70705U, // VPADDf + 70705U, // VPADDh + 1112U, // VPADDi16 + 1112U, // VPADDi32 + 1112U, // VPADDi8 + 70705U, // VPMAXf + 70705U, // VPMAXh + 1112U, // VPMAXs16 + 1112U, // VPMAXs32 + 1112U, // VPMAXs8 + 1112U, // VPMAXu16 + 1112U, // VPMAXu32 + 1112U, // VPMAXu8 + 70705U, // VPMINf + 70705U, // VPMINh + 1112U, // VPMINs16 + 1112U, // VPMINs32 + 1112U, // VPMINs8 + 1112U, // VPMINu16 + 1112U, // VPMINu32 + 1112U, // VPMINu8 + 0U, // VQABSv16i8 + 0U, // VQABSv2i32 + 0U, // VQABSv4i16 + 0U, // VQABSv4i32 + 0U, // VQABSv8i16 + 0U, // VQABSv8i8 + 1112U, // VQADDsv16i8 + 1112U, // VQADDsv1i64 + 1112U, // VQADDsv2i32 + 1112U, // VQADDsv2i64 + 1112U, // VQADDsv4i16 + 1112U, // VQADDsv4i32 + 1112U, // VQADDsv8i16 + 1112U, // VQADDsv8i8 + 1112U, // VQADDuv16i8 + 1112U, // VQADDuv1i64 + 1112U, // VQADDuv2i32 + 1112U, // VQADDuv2i64 + 1112U, // VQADDuv4i16 + 1112U, // VQADDuv4i32 + 1112U, // VQADDuv8i16 + 1112U, // VQADDuv8i8 + 73752U, // VQDMLALslv2i32 + 73752U, // VQDMLALslv4i16 + 1048U, // VQDMLALv2i64 + 1048U, // VQDMLALv4i32 + 73752U, // VQDMLSLslv2i32 + 73752U, // VQDMLSLslv4i16 + 1048U, // VQDMLSLv2i64 + 1048U, // VQDMLSLv4i32 + 17496U, // VQDMULHslv2i32 + 17496U, // VQDMULHslv4i16 + 17496U, // VQDMULHslv4i32 + 17496U, // VQDMULHslv8i16 + 1112U, // VQDMULHv2i32 + 1112U, // VQDMULHv4i16 + 1112U, // VQDMULHv4i32 + 1112U, // VQDMULHv8i16 + 17496U, // VQDMULLslv2i32 + 17496U, // VQDMULLslv4i16 + 1112U, // VQDMULLv2i64 + 1112U, // VQDMULLv4i32 + 0U, // VQMOVNsuv2i32 + 0U, // VQMOVNsuv4i16 + 0U, // VQMOVNsuv8i8 + 0U, // VQMOVNsv2i32 + 0U, // VQMOVNsv4i16 + 0U, // VQMOVNsv8i8 + 0U, // VQMOVNuv2i32 + 0U, // VQMOVNuv4i16 + 0U, // VQMOVNuv8i8 + 0U, // VQNEGv16i8 + 0U, // VQNEGv2i32 + 0U, // VQNEGv4i16 + 0U, // VQNEGv4i32 + 0U, // VQNEGv8i16 + 0U, // VQNEGv8i8 + 73752U, // VQRDMLAHslv2i32 + 73752U, // VQRDMLAHslv4i16 + 73752U, // VQRDMLAHslv4i32 + 73752U, // VQRDMLAHslv8i16 + 1048U, // VQRDMLAHv2i32 + 1048U, // VQRDMLAHv4i16 + 1048U, // VQRDMLAHv4i32 + 1048U, // VQRDMLAHv8i16 + 73752U, // VQRDMLSHslv2i32 + 73752U, // VQRDMLSHslv4i16 + 73752U, // VQRDMLSHslv4i32 + 73752U, // VQRDMLSHslv8i16 + 1048U, // VQRDMLSHv2i32 + 1048U, // VQRDMLSHv4i16 + 1048U, // VQRDMLSHv4i32 + 1048U, // VQRDMLSHv8i16 + 17496U, // VQRDMULHslv2i32 + 17496U, // VQRDMULHslv4i16 + 17496U, // VQRDMULHslv4i32 + 17496U, // VQRDMULHslv8i16 + 1112U, // VQRDMULHv2i32 + 1112U, // VQRDMULHv4i16 + 1112U, // VQRDMULHv4i32 + 1112U, // VQRDMULHv8i16 + 1112U, // VQRSHLsv16i8 + 1112U, // VQRSHLsv1i64 + 1112U, // VQRSHLsv2i32 + 1112U, // VQRSHLsv2i64 + 1112U, // VQRSHLsv4i16 + 1112U, // VQRSHLsv4i32 + 1112U, // VQRSHLsv8i16 + 1112U, // VQRSHLsv8i8 + 1112U, // VQRSHLuv16i8 + 1112U, // VQRSHLuv1i64 + 1112U, // VQRSHLuv2i32 + 1112U, // VQRSHLuv2i64 + 1112U, // VQRSHLuv4i16 + 1112U, // VQRSHLuv4i32 + 1112U, // VQRSHLuv8i16 + 1112U, // VQRSHLuv8i8 + 1112U, // VQRSHRNsv2i32 + 1112U, // VQRSHRNsv4i16 + 1112U, // VQRSHRNsv8i8 + 1112U, // VQRSHRNuv2i32 + 1112U, // VQRSHRNuv4i16 + 1112U, // VQRSHRNuv8i8 + 1112U, // VQRSHRUNv2i32 + 1112U, // VQRSHRUNv4i16 + 1112U, // VQRSHRUNv8i8 + 1112U, // VQSHLsiv16i8 + 1112U, // VQSHLsiv1i64 + 1112U, // VQSHLsiv2i32 + 1112U, // VQSHLsiv2i64 + 1112U, // VQSHLsiv4i16 + 1112U, // VQSHLsiv4i32 + 1112U, // VQSHLsiv8i16 + 1112U, // VQSHLsiv8i8 + 1112U, // VQSHLsuv16i8 + 1112U, // VQSHLsuv1i64 + 1112U, // VQSHLsuv2i32 + 1112U, // VQSHLsuv2i64 + 1112U, // VQSHLsuv4i16 + 1112U, // VQSHLsuv4i32 + 1112U, // VQSHLsuv8i16 + 1112U, // VQSHLsuv8i8 + 1112U, // VQSHLsv16i8 + 1112U, // VQSHLsv1i64 + 1112U, // VQSHLsv2i32 + 1112U, // VQSHLsv2i64 + 1112U, // VQSHLsv4i16 + 1112U, // VQSHLsv4i32 + 1112U, // VQSHLsv8i16 + 1112U, // VQSHLsv8i8 + 1112U, // VQSHLuiv16i8 + 1112U, // VQSHLuiv1i64 + 1112U, // VQSHLuiv2i32 + 1112U, // VQSHLuiv2i64 + 1112U, // VQSHLuiv4i16 + 1112U, // VQSHLuiv4i32 + 1112U, // VQSHLuiv8i16 + 1112U, // VQSHLuiv8i8 + 1112U, // VQSHLuv16i8 + 1112U, // VQSHLuv1i64 + 1112U, // VQSHLuv2i32 + 1112U, // VQSHLuv2i64 + 1112U, // VQSHLuv4i16 + 1112U, // VQSHLuv4i32 + 1112U, // VQSHLuv8i16 + 1112U, // VQSHLuv8i8 + 1112U, // VQSHRNsv2i32 + 1112U, // VQSHRNsv4i16 + 1112U, // VQSHRNsv8i8 + 1112U, // VQSHRNuv2i32 + 1112U, // VQSHRNuv4i16 + 1112U, // VQSHRNuv8i8 + 1112U, // VQSHRUNv2i32 + 1112U, // VQSHRUNv4i16 + 1112U, // VQSHRUNv8i8 + 1112U, // VQSUBsv16i8 + 1112U, // VQSUBsv1i64 + 1112U, // VQSUBsv2i32 + 1112U, // VQSUBsv2i64 + 1112U, // VQSUBsv4i16 + 1112U, // VQSUBsv4i32 + 1112U, // VQSUBsv8i16 + 1112U, // VQSUBsv8i8 + 1112U, // VQSUBuv16i8 + 1112U, // VQSUBuv1i64 + 1112U, // VQSUBuv2i32 + 1112U, // VQSUBuv2i64 + 1112U, // VQSUBuv4i16 + 1112U, // VQSUBuv4i32 + 1112U, // VQSUBuv8i16 + 1112U, // VQSUBuv8i8 + 1112U, // VRADDHNv2i32 + 1112U, // VRADDHNv4i16 + 1112U, // VRADDHNv8i8 + 0U, // VRECPEd + 33U, // VRECPEfd + 33U, // VRECPEfq + 33U, // VRECPEhd + 33U, // VRECPEhq + 0U, // VRECPEq + 70705U, // VRECPSfd + 70705U, // VRECPSfq + 70705U, // VRECPShd + 70705U, // VRECPShq + 1024U, // VREV16d8 + 1024U, // VREV16q8 + 1024U, // VREV32d16 + 1024U, // VREV32d8 + 1024U, // VREV32q16 + 1024U, // VREV32q8 + 1024U, // VREV64d16 + 1024U, // VREV64d32 + 1024U, // VREV64d8 + 1024U, // VREV64q16 + 1024U, // VREV64q32 + 1024U, // VREV64q8 + 1112U, // VRHADDsv16i8 + 1112U, // VRHADDsv2i32 + 1112U, // VRHADDsv4i16 + 1112U, // VRHADDsv4i32 + 1112U, // VRHADDsv8i16 + 1112U, // VRHADDsv8i8 + 1112U, // VRHADDuv16i8 + 1112U, // VRHADDuv2i32 + 1112U, // VRHADDuv4i16 + 1112U, // VRHADDuv4i32 + 1112U, // VRHADDuv8i16 + 1112U, // VRHADDuv8i8 + 0U, // VRINTAD + 0U, // VRINTAH + 0U, // VRINTANDf + 0U, // VRINTANDh + 0U, // VRINTANQf + 0U, // VRINTANQh + 0U, // VRINTAS + 0U, // VRINTMD + 0U, // VRINTMH + 0U, // VRINTMNDf + 0U, // VRINTMNDh + 0U, // VRINTMNQf + 0U, // VRINTMNQh + 0U, // VRINTMS + 0U, // VRINTND + 0U, // VRINTNH + 0U, // VRINTNNDf + 0U, // VRINTNNDh + 0U, // VRINTNNQf + 0U, // VRINTNNQh + 0U, // VRINTNS + 0U, // VRINTPD + 0U, // VRINTPH + 0U, // VRINTPNDf + 0U, // VRINTPNDh + 0U, // VRINTPNQf + 0U, // VRINTPNQh + 0U, // VRINTPS + 33U, // VRINTRD + 33U, // VRINTRH + 33U, // VRINTRS + 33U, // VRINTXD + 33U, // VRINTXH + 0U, // VRINTXNDf + 0U, // VRINTXNDh + 0U, // VRINTXNQf + 0U, // VRINTXNQh + 33U, // VRINTXS + 33U, // VRINTZD + 33U, // VRINTZH + 0U, // VRINTZNDf + 0U, // VRINTZNDh + 0U, // VRINTZNQf + 0U, // VRINTZNQh + 33U, // VRINTZS + 1112U, // VRSHLsv16i8 + 1112U, // VRSHLsv1i64 + 1112U, // VRSHLsv2i32 + 1112U, // VRSHLsv2i64 + 1112U, // VRSHLsv4i16 + 1112U, // VRSHLsv4i32 + 1112U, // VRSHLsv8i16 + 1112U, // VRSHLsv8i8 + 1112U, // VRSHLuv16i8 + 1112U, // VRSHLuv1i64 + 1112U, // VRSHLuv2i32 + 1112U, // VRSHLuv2i64 + 1112U, // VRSHLuv4i16 + 1112U, // VRSHLuv4i32 + 1112U, // VRSHLuv8i16 + 1112U, // VRSHLuv8i8 + 1112U, // VRSHRNv2i32 + 1112U, // VRSHRNv4i16 + 1112U, // VRSHRNv8i8 + 1112U, // VRSHRsv16i8 + 1112U, // VRSHRsv1i64 + 1112U, // VRSHRsv2i32 + 1112U, // VRSHRsv2i64 + 1112U, // VRSHRsv4i16 + 1112U, // VRSHRsv4i32 + 1112U, // VRSHRsv8i16 + 1112U, // VRSHRsv8i8 + 1112U, // VRSHRuv16i8 + 1112U, // VRSHRuv1i64 + 1112U, // VRSHRuv2i32 + 1112U, // VRSHRuv2i64 + 1112U, // VRSHRuv4i16 + 1112U, // VRSHRuv4i32 + 1112U, // VRSHRuv8i16 + 1112U, // VRSHRuv8i8 + 0U, // VRSQRTEd + 33U, // VRSQRTEfd + 33U, // VRSQRTEfq + 33U, // VRSQRTEhd + 33U, // VRSQRTEhq + 0U, // VRSQRTEq + 70705U, // VRSQRTSfd + 70705U, // VRSQRTSfq + 70705U, // VRSQRTShd + 70705U, // VRSQRTShq + 1048U, // VRSRAsv16i8 + 1048U, // VRSRAsv1i64 + 1048U, // VRSRAsv2i32 + 1048U, // VRSRAsv2i64 + 1048U, // VRSRAsv4i16 + 1048U, // VRSRAsv4i32 + 1048U, // VRSRAsv8i16 + 1048U, // VRSRAsv8i8 + 1048U, // VRSRAuv16i8 + 1048U, // VRSRAuv1i64 + 1048U, // VRSRAuv2i32 + 1048U, // VRSRAuv2i64 + 1048U, // VRSRAuv4i16 + 1048U, // VRSRAuv4i32 + 1048U, // VRSRAuv8i16 + 1048U, // VRSRAuv8i8 + 1112U, // VRSUBHNv2i32 + 1112U, // VRSUBHNv4i16 + 1112U, // VRSUBHNv8i8 + 0U, // VSDOTD + 0U, // VSDOTDI + 0U, // VSDOTQ + 0U, // VSDOTQI + 1112U, // VSELEQD + 1112U, // VSELEQH + 1112U, // VSELEQS + 1112U, // VSELGED + 1112U, // VSELGEH + 1112U, // VSELGES + 1112U, // VSELGTD + 1112U, // VSELGTH + 1112U, // VSELGTS + 1112U, // VSELVSD + 1112U, // VSELVSH + 1112U, // VSELVSS + 6U, // VSETLNi16 + 6U, // VSETLNi32 + 6U, // VSETLNi8 + 1112U, // VSHLLi16 + 1112U, // VSHLLi32 + 1112U, // VSHLLi8 + 1112U, // VSHLLsv2i64 + 1112U, // VSHLLsv4i32 + 1112U, // VSHLLsv8i16 + 1112U, // VSHLLuv2i64 + 1112U, // VSHLLuv4i32 + 1112U, // VSHLLuv8i16 + 1112U, // VSHLiv16i8 + 1112U, // VSHLiv1i64 + 1112U, // VSHLiv2i32 + 1112U, // VSHLiv2i64 + 1112U, // VSHLiv4i16 + 1112U, // VSHLiv4i32 + 1112U, // VSHLiv8i16 + 1112U, // VSHLiv8i8 + 1112U, // VSHLsv16i8 + 1112U, // VSHLsv1i64 + 1112U, // VSHLsv2i32 + 1112U, // VSHLsv2i64 + 1112U, // VSHLsv4i16 + 1112U, // VSHLsv4i32 + 1112U, // VSHLsv8i16 + 1112U, // VSHLsv8i8 + 1112U, // VSHLuv16i8 + 1112U, // VSHLuv1i64 + 1112U, // VSHLuv2i32 + 1112U, // VSHLuv2i64 + 1112U, // VSHLuv4i16 + 1112U, // VSHLuv4i32 + 1112U, // VSHLuv8i16 + 1112U, // VSHLuv8i8 + 1112U, // VSHRNv2i32 + 1112U, // VSHRNv4i16 + 1112U, // VSHRNv8i8 + 1112U, // VSHRsv16i8 + 1112U, // VSHRsv1i64 + 1112U, // VSHRsv2i32 + 1112U, // VSHRsv2i64 + 1112U, // VSHRsv4i16 + 1112U, // VSHRsv4i32 + 1112U, // VSHRsv8i16 + 1112U, // VSHRsv8i8 + 1112U, // VSHRuv16i8 + 1112U, // VSHRuv1i64 + 1112U, // VSHRuv2i32 + 1112U, // VSHRuv2i64 + 1112U, // VSHRuv4i16 + 1112U, // VSHRuv4i32 + 1112U, // VSHRuv8i16 + 1112U, // VSHRuv8i8 + 0U, // VSHTOD + 7U, // VSHTOH + 0U, // VSHTOS + 0U, // VSITOD + 0U, // VSITOH + 0U, // VSITOS + 589912U, // VSLIv16i8 + 589912U, // VSLIv1i64 + 589912U, // VSLIv2i32 + 589912U, // VSLIv2i64 + 589912U, // VSLIv4i16 + 589912U, // VSLIv4i32 + 589912U, // VSLIv8i16 + 589912U, // VSLIv8i8 + 7U, // VSLTOD + 7U, // VSLTOH + 7U, // VSLTOS + 33U, // VSQRTD + 33U, // VSQRTH + 33U, // VSQRTS + 1048U, // VSRAsv16i8 + 1048U, // VSRAsv1i64 + 1048U, // VSRAsv2i32 + 1048U, // VSRAsv2i64 + 1048U, // VSRAsv4i16 + 1048U, // VSRAsv4i32 + 1048U, // VSRAsv8i16 + 1048U, // VSRAsv8i8 + 1048U, // VSRAuv16i8 + 1048U, // VSRAuv1i64 + 1048U, // VSRAuv2i32 + 1048U, // VSRAuv2i64 + 1048U, // VSRAuv4i16 + 1048U, // VSRAuv4i32 + 1048U, // VSRAuv8i16 + 1048U, // VSRAuv8i8 + 589912U, // VSRIv16i8 + 589912U, // VSRIv1i64 + 589912U, // VSRIv2i32 + 589912U, // VSRIv2i64 + 589912U, // VSRIv4i16 + 589912U, // VSRIv4i32 + 589912U, // VSRIv8i16 + 589912U, // VSRIv8i8 + 308U, // VST1LNd16 + 23768380U, // VST1LNd16_UPD + 308U, // VST1LNd32 + 23768380U, // VST1LNd32_UPD + 308U, // VST1LNd8 + 23768380U, // VST1LNd8_UPD + 0U, // VST1LNq16Pseudo + 0U, // VST1LNq16Pseudo_UPD + 0U, // VST1LNq32Pseudo + 0U, // VST1LNq32Pseudo_UPD + 0U, // VST1LNq8Pseudo + 0U, // VST1LNq8Pseudo_UPD + 0U, // VST1d16 + 0U, // VST1d16Q + 0U, // VST1d16QPseudo + 0U, // VST1d16Qwb_fixed + 0U, // VST1d16Qwb_register + 0U, // VST1d16T + 0U, // VST1d16TPseudo + 0U, // VST1d16Twb_fixed + 0U, // VST1d16Twb_register + 0U, // VST1d16wb_fixed + 0U, // VST1d16wb_register + 0U, // VST1d32 + 0U, // VST1d32Q + 0U, // VST1d32QPseudo + 0U, // VST1d32Qwb_fixed + 0U, // VST1d32Qwb_register + 0U, // VST1d32T + 0U, // VST1d32TPseudo + 0U, // VST1d32Twb_fixed + 0U, // VST1d32Twb_register + 0U, // VST1d32wb_fixed + 0U, // VST1d32wb_register + 0U, // VST1d64 + 0U, // VST1d64Q + 0U, // VST1d64QPseudo + 0U, // VST1d64QPseudoWB_fixed + 0U, // VST1d64QPseudoWB_register + 0U, // VST1d64Qwb_fixed + 0U, // VST1d64Qwb_register + 0U, // VST1d64T + 0U, // VST1d64TPseudo + 0U, // VST1d64TPseudoWB_fixed + 0U, // VST1d64TPseudoWB_register + 0U, // VST1d64Twb_fixed + 0U, // VST1d64Twb_register + 0U, // VST1d64wb_fixed + 0U, // VST1d64wb_register + 0U, // VST1d8 + 0U, // VST1d8Q + 0U, // VST1d8QPseudo + 0U, // VST1d8Qwb_fixed + 0U, // VST1d8Qwb_register + 0U, // VST1d8T + 0U, // VST1d8TPseudo + 0U, // VST1d8Twb_fixed + 0U, // VST1d8Twb_register + 0U, // VST1d8wb_fixed + 0U, // VST1d8wb_register + 0U, // VST1q16 + 0U, // VST1q16HighQPseudo + 0U, // VST1q16HighTPseudo + 0U, // VST1q16LowQPseudo_UPD + 0U, // VST1q16LowTPseudo_UPD + 0U, // VST1q16wb_fixed + 0U, // VST1q16wb_register + 0U, // VST1q32 + 0U, // VST1q32HighQPseudo + 0U, // VST1q32HighTPseudo + 0U, // VST1q32LowQPseudo_UPD + 0U, // VST1q32LowTPseudo_UPD + 0U, // VST1q32wb_fixed + 0U, // VST1q32wb_register + 0U, // VST1q64 + 0U, // VST1q64HighQPseudo + 0U, // VST1q64HighTPseudo + 0U, // VST1q64LowQPseudo_UPD + 0U, // VST1q64LowTPseudo_UPD + 0U, // VST1q64wb_fixed + 0U, // VST1q64wb_register + 0U, // VST1q8 + 0U, // VST1q8HighQPseudo + 0U, // VST1q8HighTPseudo + 0U, // VST1q8LowQPseudo_UPD + 0U, // VST1q8LowTPseudo_UPD + 0U, // VST1q8wb_fixed + 0U, // VST1q8wb_register + 222900460U, // VST2LNd16 + 0U, // VST2LNd16Pseudo + 0U, // VST2LNd16Pseudo_UPD + 995572U, // VST2LNd16_UPD + 222900460U, // VST2LNd32 + 0U, // VST2LNd32Pseudo + 0U, // VST2LNd32Pseudo_UPD + 995572U, // VST2LNd32_UPD + 222900460U, // VST2LNd8 + 0U, // VST2LNd8Pseudo + 0U, // VST2LNd8Pseudo_UPD + 995572U, // VST2LNd8_UPD + 222900460U, // VST2LNq16 + 0U, // VST2LNq16Pseudo + 0U, // VST2LNq16Pseudo_UPD + 995572U, // VST2LNq16_UPD + 222900460U, // VST2LNq32 + 0U, // VST2LNq32Pseudo + 0U, // VST2LNq32Pseudo_UPD + 995572U, // VST2LNq32_UPD + 0U, // VST2b16 + 0U, // VST2b16wb_fixed + 0U, // VST2b16wb_register + 0U, // VST2b32 + 0U, // VST2b32wb_fixed + 0U, // VST2b32wb_register + 0U, // VST2b8 + 0U, // VST2b8wb_fixed + 0U, // VST2b8wb_register + 0U, // VST2d16 + 0U, // VST2d16wb_fixed + 0U, // VST2d16wb_register + 0U, // VST2d32 + 0U, // VST2d32wb_fixed + 0U, // VST2d32wb_register + 0U, // VST2d8 + 0U, // VST2d8wb_fixed + 0U, // VST2d8wb_register + 0U, // VST2q16 + 0U, // VST2q16Pseudo + 0U, // VST2q16PseudoWB_fixed + 0U, // VST2q16PseudoWB_register + 0U, // VST2q16wb_fixed + 0U, // VST2q16wb_register + 0U, // VST2q32 + 0U, // VST2q32Pseudo + 0U, // VST2q32PseudoWB_fixed + 0U, // VST2q32PseudoWB_register + 0U, // VST2q32wb_fixed + 0U, // VST2q32wb_register + 0U, // VST2q8 + 0U, // VST2q8Pseudo + 0U, // VST2q8PseudoWB_fixed + 0U, // VST2q8PseudoWB_register + 0U, // VST2q8wb_fixed + 0U, // VST2q8wb_register + 256454972U, // VST3LNd16 + 0U, // VST3LNd16Pseudo + 0U, // VST3LNd16Pseudo_UPD + 324U, // VST3LNd16_UPD + 256454972U, // VST3LNd32 + 0U, // VST3LNd32Pseudo + 0U, // VST3LNd32Pseudo_UPD + 324U, // VST3LNd32_UPD + 256454972U, // VST3LNd8 + 0U, // VST3LNd8Pseudo + 0U, // VST3LNd8Pseudo_UPD + 324U, // VST3LNd8_UPD + 256454972U, // VST3LNq16 + 0U, // VST3LNq16Pseudo + 0U, // VST3LNq16Pseudo_UPD + 324U, // VST3LNq16_UPD + 256454972U, // VST3LNq32 + 0U, // VST3LNq32Pseudo + 0U, // VST3LNq32Pseudo_UPD + 324U, // VST3LNq32_UPD + 287342616U, // VST3d16 + 0U, // VST3d16Pseudo + 0U, // VST3d16Pseudo_UPD + 18760U, // VST3d16_UPD + 287342616U, // VST3d32 + 0U, // VST3d32Pseudo + 0U, // VST3d32Pseudo_UPD + 18760U, // VST3d32_UPD + 287342616U, // VST3d8 + 0U, // VST3d8Pseudo + 0U, // VST3d8Pseudo_UPD + 18760U, // VST3d8_UPD + 287342616U, // VST3q16 + 0U, // VST3q16Pseudo_UPD + 18760U, // VST3q16_UPD + 0U, // VST3q16oddPseudo + 0U, // VST3q16oddPseudo_UPD + 287342616U, // VST3q32 + 0U, // VST3q32Pseudo_UPD + 18760U, // VST3q32_UPD + 0U, // VST3q32oddPseudo + 0U, // VST3q32oddPseudo_UPD + 287342616U, // VST3q8 + 0U, // VST3q8Pseudo_UPD + 18760U, // VST3q8_UPD + 0U, // VST3q8oddPseudo + 0U, // VST3q8oddPseudo_UPD + 323563764U, // VST4LNd16 + 0U, // VST4LNd16Pseudo + 0U, // VST4LNd16Pseudo_UPD + 19708U, // VST4LNd16_UPD + 323563764U, // VST4LNd32 + 0U, // VST4LNd32Pseudo + 0U, // VST4LNd32Pseudo_UPD + 19708U, // VST4LNd32_UPD + 323563764U, // VST4LNd8 + 0U, // VST4LNd8Pseudo + 0U, // VST4LNd8Pseudo_UPD + 19708U, // VST4LNd8_UPD + 323563764U, // VST4LNq16 + 0U, // VST4LNq16Pseudo + 0U, // VST4LNq16Pseudo_UPD + 19708U, // VST4LNq16_UPD + 323563764U, // VST4LNq32 + 0U, // VST4LNq32Pseudo + 0U, // VST4LNq32Pseudo_UPD + 19708U, // VST4LNq32_UPD + 337674264U, // VST4d16 + 0U, // VST4d16Pseudo + 0U, // VST4d16Pseudo_UPD + 1016136U, // VST4d16_UPD + 337674264U, // VST4d32 + 0U, // VST4d32Pseudo + 0U, // VST4d32Pseudo_UPD + 1016136U, // VST4d32_UPD + 337674264U, // VST4d8 + 0U, // VST4d8Pseudo + 0U, // VST4d8Pseudo_UPD + 1016136U, // VST4d8_UPD + 337674264U, // VST4q16 + 0U, // VST4q16Pseudo_UPD + 1016136U, // VST4q16_UPD + 0U, // VST4q16oddPseudo + 0U, // VST4q16oddPseudo_UPD + 337674264U, // VST4q32 + 0U, // VST4q32Pseudo_UPD + 1016136U, // VST4q32_UPD + 0U, // VST4q32oddPseudo + 0U, // VST4q32oddPseudo_UPD + 337674264U, // VST4q8 + 0U, // VST4q8Pseudo_UPD + 1016136U, // VST4q8_UPD + 0U, // VST4q8oddPseudo + 0U, // VST4q8oddPseudo_UPD + 33U, // VSTMDDB_UPD + 1136U, // VSTMDIA + 33U, // VSTMDIA_UPD + 0U, // VSTMQIA + 33U, // VSTMSDB_UPD + 1136U, // VSTMSIA + 33U, // VSTMSIA_UPD + 288U, // VSTRD + 296U, // VSTRH + 288U, // VSTRS + 70705U, // VSUBD + 70705U, // VSUBH + 1112U, // VSUBHNv2i32 + 1112U, // VSUBHNv4i16 + 1112U, // VSUBHNv8i8 + 1112U, // VSUBLsv2i64 + 1112U, // VSUBLsv4i32 + 1112U, // VSUBLsv8i16 + 1112U, // VSUBLuv2i64 + 1112U, // VSUBLuv4i32 + 1112U, // VSUBLuv8i16 + 70705U, // VSUBS + 1112U, // VSUBWsv2i64 + 1112U, // VSUBWsv4i32 + 1112U, // VSUBWsv8i16 + 1112U, // VSUBWuv2i64 + 1112U, // VSUBWuv4i32 + 1112U, // VSUBWuv8i16 + 70705U, // VSUBfd + 70705U, // VSUBfq + 70705U, // VSUBhd + 70705U, // VSUBhq + 1112U, // VSUBv16i8 + 1112U, // VSUBv1i64 + 1112U, // VSUBv2i32 + 1112U, // VSUBv2i64 + 1112U, // VSUBv4i16 + 1112U, // VSUBv4i32 + 1112U, // VSUBv8i16 + 1112U, // VSUBv8i8 + 1024U, // VSWPd + 1024U, // VSWPq + 336U, // VTBL1 + 344U, // VTBL2 + 352U, // VTBL3 + 0U, // VTBL3Pseudo + 360U, // VTBL4 + 0U, // VTBL4Pseudo + 368U, // VTBX1 + 376U, // VTBX2 + 384U, // VTBX3 + 0U, // VTBX3Pseudo + 392U, // VTBX4 + 0U, // VTBX4Pseudo + 0U, // VTOSHD + 7U, // VTOSHH + 0U, // VTOSHS + 0U, // VTOSIRD + 0U, // VTOSIRH + 0U, // VTOSIRS + 0U, // VTOSIZD + 0U, // VTOSIZH + 0U, // VTOSIZS + 7U, // VTOSLD + 7U, // VTOSLH + 7U, // VTOSLS + 0U, // VTOUHD + 7U, // VTOUHH + 0U, // VTOUHS + 0U, // VTOUIRD + 0U, // VTOUIRH + 0U, // VTOUIRS + 0U, // VTOUIZD + 0U, // VTOUIZH + 0U, // VTOUIZS + 7U, // VTOULD + 7U, // VTOULH + 7U, // VTOULS + 1024U, // VTRNd16 + 1024U, // VTRNd32 + 1024U, // VTRNd8 + 1024U, // VTRNq16 + 1024U, // VTRNq32 + 1024U, // VTRNq8 + 0U, // VTSTv16i8 + 0U, // VTSTv2i32 + 0U, // VTSTv4i16 + 0U, // VTSTv4i32 + 0U, // VTSTv8i16 + 0U, // VTSTv8i8 + 0U, // VUDOTD + 0U, // VUDOTDI + 0U, // VUDOTQ + 0U, // VUDOTQI + 0U, // VUHTOD + 7U, // VUHTOH + 0U, // VUHTOS + 0U, // VUITOD + 0U, // VUITOH + 0U, // VUITOS + 7U, // VULTOD + 7U, // VULTOH + 7U, // VULTOS + 1024U, // VUZPd16 + 1024U, // VUZPd8 + 1024U, // VUZPq16 + 1024U, // VUZPq32 + 1024U, // VUZPq8 + 1024U, // VZIPd16 + 1024U, // VZIPd8 + 1024U, // VZIPq16 + 1024U, // VZIPq32 + 1024U, // VZIPq8 + 20592U, // sysLDMDA + 401U, // sysLDMDA_UPD + 20592U, // sysLDMDB + 401U, // sysLDMDB_UPD + 20592U, // sysLDMIA + 401U, // sysLDMIA_UPD + 20592U, // sysLDMIB + 401U, // sysLDMIB_UPD + 20592U, // sysSTMDA + 401U, // sysSTMDA_UPD + 20592U, // sysSTMDB + 401U, // sysSTMDB_UPD + 20592U, // sysSTMIA + 401U, // sysSTMIA_UPD + 20592U, // sysSTMIB + 401U, // sysSTMIB_UPD + 0U, // t2ADCri + 0U, // t2ADCrr + 1048576U, // t2ADCrs + 0U, // t2ADDri + 0U, // t2ADDri12 + 0U, // t2ADDrr + 1048576U, // t2ADDrs + 72U, // t2ADR + 0U, // t2ANDri + 0U, // t2ANDrr + 1048576U, // t2ANDrs + 1081344U, // t2ASRri + 0U, // t2ASRrr + 0U, // t2B + 80U, // t2BFC + 163928U, // t2BFI + 0U, // t2BICri + 0U, // t2BICrr + 1048576U, // t2BICrs + 0U, // t2BXJ + 0U, // t2Bcc + 4145U, // t2CDP + 4145U, // t2CDP2 + 0U, // t2CLREX + 1024U, // t2CLZ + 1024U, // t2CMNri + 1024U, // t2CMNzrr + 56U, // t2CMNzrs + 1024U, // t2CMPri + 1024U, // t2CMPrr + 56U, // t2CMPrs + 0U, // t2CPS1p + 0U, // t2CPS2p + 1112U, // t2CPS3p + 1112U, // t2CRC32B + 1112U, // t2CRC32CB + 1112U, // t2CRC32CH + 1112U, // t2CRC32CW + 1112U, // t2CRC32H + 1112U, // t2CRC32W + 0U, // t2DBG + 0U, // t2DCPS1 + 0U, // t2DCPS2 + 0U, // t2DCPS3 + 0U, // t2DMB + 0U, // t2DSB + 0U, // t2EORri + 0U, // t2EORrr + 1048576U, // t2EORrs + 0U, // t2HINT + 0U, // t2HVC + 0U, // t2ISB + 0U, // t2IT + 0U, // t2Int_eh_sjlj_setjmp + 0U, // t2Int_eh_sjlj_setjmp_nofp + 8U, // t2LDA + 8U, // t2LDAB + 8U, // t2LDAEX + 8U, // t2LDAEXB + 557056U, // t2LDAEXD + 8U, // t2LDAEXH + 8U, // t2LDAH + 122U, // t2LDC2L_OFFSET + 196738U, // t2LDC2L_OPTION + 229506U, // t2LDC2L_POST + 138U, // t2LDC2L_PRE + 122U, // t2LDC2_OFFSET + 196738U, // t2LDC2_OPTION + 229506U, // t2LDC2_POST + 138U, // t2LDC2_PRE + 122U, // t2LDCL_OFFSET + 196738U, // t2LDCL_OPTION + 229506U, // t2LDCL_POST + 138U, // t2LDCL_PRE + 122U, // t2LDC_OFFSET + 196738U, // t2LDC_OPTION + 229506U, // t2LDC_POST + 138U, // t2LDC_PRE + 1136U, // t2LDMDB + 33U, // t2LDMDB_UPD + 1136U, // t2LDMIA + 33U, // t2LDMIA_UPD + 408U, // t2LDRBT + 21632U, // t2LDRB_POST + 416U, // t2LDRB_PRE + 160U, // t2LDRBi12 + 408U, // t2LDRBi8 + 424U, // t2LDRBpci + 432U, // t2LDRBs + 25493504U, // t2LDRD_POST + 1114112U, // t2LDRD_PRE + 1146880U, // t2LDRDi8 + 440U, // t2LDREX + 8U, // t2LDREXB + 557056U, // t2LDREXD + 8U, // t2LDREXH + 408U, // t2LDRHT + 21632U, // t2LDRH_POST + 416U, // t2LDRH_PRE + 160U, // t2LDRHi12 + 408U, // t2LDRHi8 + 424U, // t2LDRHpci + 432U, // t2LDRHs + 408U, // t2LDRSBT + 21632U, // t2LDRSB_POST + 416U, // t2LDRSB_PRE + 160U, // t2LDRSBi12 + 408U, // t2LDRSBi8 + 424U, // t2LDRSBpci + 432U, // t2LDRSBs + 408U, // t2LDRSHT + 21632U, // t2LDRSH_POST + 416U, // t2LDRSH_PRE + 160U, // t2LDRSHi12 + 408U, // t2LDRSHi8 + 424U, // t2LDRSHpci + 432U, // t2LDRSHs + 408U, // t2LDRT + 21632U, // t2LDR_POST + 416U, // t2LDR_PRE + 160U, // t2LDRi12 + 408U, // t2LDRi8 + 424U, // t2LDRpci + 432U, // t2LDRs + 0U, // t2LSLri + 0U, // t2LSLrr + 1081344U, // t2LSRri + 0U, // t2LSRrr + 4690993U, // t2MCR + 4690993U, // t2MCR2 + 6788145U, // t2MCRR + 6788145U, // t2MCRR2 + 35651584U, // t2MLA + 35651584U, // t2MLS + 1112U, // t2MOVTi16 + 1024U, // t2MOVi + 1024U, // t2MOVi16 + 1024U, // t2MOVr + 22528U, // t2MOVsra_flag + 22528U, // t2MOVsrl_flag + 0U, // t2MRC + 0U, // t2MRC2 + 0U, // t2MRRC + 0U, // t2MRRC2 + 2U, // t2MRS_AR + 448U, // t2MRS_M + 200U, // t2MRSbanked + 2U, // t2MRSsys_AR + 33U, // t2MSR_AR + 33U, // t2MSR_M + 0U, // t2MSRbanked + 0U, // t2MUL + 1024U, // t2MVNi + 1024U, // t2MVNr + 56U, // t2MVNs + 0U, // t2ORNri + 0U, // t2ORNrr + 1048576U, // t2ORNrs + 0U, // t2ORRri + 0U, // t2ORRrr + 1048576U, // t2ORRrs + 8388608U, // t2PKHBT + 10485760U, // t2PKHTB + 0U, // t2PLDWi12 + 0U, // t2PLDWi8 + 0U, // t2PLDWs + 0U, // t2PLDi12 + 0U, // t2PLDi8 + 0U, // t2PLDpci + 0U, // t2PLDs + 0U, // t2PLIi12 + 0U, // t2PLIi8 + 0U, // t2PLIpci + 0U, // t2PLIs + 0U, // t2QADD + 0U, // t2QADD16 + 0U, // t2QADD8 + 0U, // t2QASX + 0U, // t2QDADD + 0U, // t2QDSUB + 0U, // t2QSAX + 0U, // t2QSUB + 0U, // t2QSUB16 + 0U, // t2QSUB8 + 1024U, // t2RBIT + 1024U, // t2REV + 1024U, // t2REV16 + 1024U, // t2REVSH + 0U, // t2RFEDB + 0U, // t2RFEDBW + 0U, // t2RFEIA + 0U, // t2RFEIAW + 0U, // t2RORri + 0U, // t2RORrr + 1024U, // t2RRX + 0U, // t2RSBri + 0U, // t2RSBrr + 1048576U, // t2RSBrs + 0U, // t2SADD16 + 0U, // t2SADD8 + 0U, // t2SASX + 0U, // t2SBCri + 0U, // t2SBCrr + 1048576U, // t2SBCrs + 69206016U, // t2SBFX + 0U, // t2SDIV + 0U, // t2SEL + 0U, // t2SETPAN + 0U, // t2SG + 0U, // t2SHADD16 + 0U, // t2SHADD8 + 0U, // t2SHASX + 0U, // t2SHSAX + 0U, // t2SHSUB16 + 0U, // t2SHSUB8 + 0U, // t2SMC + 35651584U, // t2SMLABB + 35651584U, // t2SMLABT + 35651584U, // t2SMLAD + 35651584U, // t2SMLADX + 35651584U, // t2SMLAL + 35651584U, // t2SMLALBB + 35651584U, // t2SMLALBT + 35651584U, // t2SMLALD + 35651584U, // t2SMLALDX + 35651584U, // t2SMLALTB + 35651584U, // t2SMLALTT + 35651584U, // t2SMLATB + 35651584U, // t2SMLATT + 35651584U, // t2SMLAWB + 35651584U, // t2SMLAWT + 35651584U, // t2SMLSD + 35651584U, // t2SMLSDX + 35651584U, // t2SMLSLD + 35651584U, // t2SMLSLDX + 35651584U, // t2SMMLA + 35651584U, // t2SMMLAR + 35651584U, // t2SMMLS + 35651584U, // t2SMMLSR + 0U, // t2SMMUL + 0U, // t2SMMULR + 0U, // t2SMUAD + 0U, // t2SMUADX + 0U, // t2SMULBB + 0U, // t2SMULBT + 35651584U, // t2SMULL + 0U, // t2SMULTB + 0U, // t2SMULTT + 0U, // t2SMULWB + 0U, // t2SMULWT + 0U, // t2SMUSD + 0U, // t2SMUSDX + 0U, // t2SRSDB + 0U, // t2SRSDB_UPD + 0U, // t2SRSIA + 0U, // t2SRSIA_UPD + 6352U, // t2SSAT + 1232U, // t2SSAT16 + 0U, // t2SSAX + 0U, // t2SSUB16 + 0U, // t2SSUB8 + 122U, // t2STC2L_OFFSET + 196738U, // t2STC2L_OPTION + 229506U, // t2STC2L_POST + 138U, // t2STC2L_PRE + 122U, // t2STC2_OFFSET + 196738U, // t2STC2_OPTION + 229506U, // t2STC2_POST + 138U, // t2STC2_PRE + 122U, // t2STCL_OFFSET + 196738U, // t2STCL_OPTION + 229506U, // t2STCL_POST + 138U, // t2STCL_PRE + 122U, // t2STC_OFFSET + 196738U, // t2STC_OPTION + 229506U, // t2STC_POST + 138U, // t2STC_PRE + 8U, // t2STL + 8U, // t2STLB + 557056U, // t2STLEX + 557056U, // t2STLEXB + 371195904U, // t2STLEXD + 557056U, // t2STLEXH + 8U, // t2STLH + 1136U, // t2STMDB + 33U, // t2STMDB_UPD + 1136U, // t2STMIA + 33U, // t2STMIA_UPD + 408U, // t2STRBT + 21632U, // t2STRB_POST + 416U, // t2STRB_PRE + 160U, // t2STRBi12 + 408U, // t2STRBi8 + 432U, // t2STRBs + 25493592U, // t2STRD_POST + 1114200U, // t2STRD_PRE + 1146880U, // t2STRDi8 + 1179648U, // t2STREX + 557056U, // t2STREXB + 371195904U, // t2STREXD + 557056U, // t2STREXH + 408U, // t2STRHT + 21632U, // t2STRH_POST + 416U, // t2STRH_PRE + 160U, // t2STRHi12 + 408U, // t2STRHi8 + 432U, // t2STRHs + 408U, // t2STRT + 21632U, // t2STR_POST + 416U, // t2STR_PRE + 160U, // t2STRi12 + 408U, // t2STRi8 + 432U, // t2STRs + 0U, // t2SUBS_PC_LR + 0U, // t2SUBri + 0U, // t2SUBri12 + 0U, // t2SUBrr + 1048576U, // t2SUBrs + 12582912U, // t2SXTAB + 12582912U, // t2SXTAB16 + 12582912U, // t2SXTAH + 7168U, // t2SXTB + 7168U, // t2SXTB16 + 7168U, // t2SXTH + 0U, // t2TBB + 0U, // t2TBH + 1024U, // t2TEQri + 1024U, // t2TEQrr + 56U, // t2TEQrs + 0U, // t2TSB + 1024U, // t2TSTri + 1024U, // t2TSTrr + 56U, // t2TSTrs + 1024U, // t2TT + 1024U, // t2TTA + 1024U, // t2TTAT + 1024U, // t2TTT + 0U, // t2UADD16 + 0U, // t2UADD8 + 0U, // t2UASX + 69206016U, // t2UBFX + 0U, // t2UDF + 0U, // t2UDIV + 0U, // t2UHADD16 + 0U, // t2UHADD8 + 0U, // t2UHASX + 0U, // t2UHSAX + 0U, // t2UHSUB16 + 0U, // t2UHSUB8 + 35651584U, // t2UMAAL + 35651584U, // t2UMLAL + 35651584U, // t2UMULL + 0U, // t2UQADD16 + 0U, // t2UQADD8 + 0U, // t2UQASX + 0U, // t2UQSAX + 0U, // t2UQSUB16 + 0U, // t2UQSUB8 + 0U, // t2USAD8 + 35651584U, // t2USADA8 + 14680064U, // t2USAT + 0U, // t2USAT16 + 0U, // t2USAX + 0U, // t2USUB16 + 0U, // t2USUB8 + 12582912U, // t2UXTAB + 12582912U, // t2UXTAB16 + 12582912U, // t2UXTAH + 7168U, // t2UXTB + 7168U, // t2UXTB16 + 7168U, // t2UXTH + 0U, // tADC + 1112U, // tADDhirr + 1048U, // tADDi3 + 0U, // tADDi8 + 0U, // tADDrSP + 1212416U, // tADDrSPi + 1048U, // tADDrr + 456U, // tADDspi + 1112U, // tADDspr + 464U, // tADR + 0U, // tAND + 472U, // tASRri + 0U, // tASRrr + 0U, // tB + 0U, // tBIC + 0U, // tBKPT + 0U, // tBL + 0U, // tBLXNSr + 0U, // tBLXi + 0U, // tBLXr + 0U, // tBX + 0U, // tBXNS + 0U, // tBcc + 0U, // tCBNZ + 0U, // tCBZ + 1024U, // tCMNz + 1024U, // tCMPhir + 1024U, // tCMPi8 + 1024U, // tCMPr + 0U, // tCPS + 0U, // tEOR + 0U, // tHINT + 0U, // tHLT + 0U, // tInt_WIN_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_setjmp + 1136U, // tLDMIA + 480U, // tLDRBi + 488U, // tLDRBr + 496U, // tLDRHi + 488U, // tLDRHr + 488U, // tLDRSB + 488U, // tLDRSH + 504U, // tLDRi + 424U, // tLDRpci + 488U, // tLDRr + 512U, // tLDRspi + 1048U, // tLSLri + 0U, // tLSLrr + 472U, // tLSRri + 0U, // tLSRrr + 0U, // tMOVSr + 0U, // tMOVi8 + 1024U, // tMOVr + 1048U, // tMUL + 0U, // tMVN + 0U, // tORR + 0U, // tPICADD + 0U, // tPOP + 0U, // tPUSH + 1024U, // tREV + 1024U, // tREV16 + 1024U, // tREVSH + 0U, // tROR + 0U, // tRSB + 0U, // tSBC + 0U, // tSETEND + 33U, // tSTMIA_UPD + 480U, // tSTRBi + 488U, // tSTRBr + 496U, // tSTRHi + 488U, // tSTRHr + 504U, // tSTRi + 488U, // tSTRr + 512U, // tSTRspi + 1048U, // tSUBi3 + 0U, // tSUBi8 + 1048U, // tSUBrr + 456U, // tSUBspi + 0U, // tSVC + 1024U, // tSXTB + 1024U, // tSXTH + 0U, // tTRAP + 1024U, // tTST + 0U, // tUDF + 1024U, // tUXTB + 1024U, // tUXTH + 0U, // t__brkdiv0 }; unsigned int opcode = MCInst_getOpcode(MI); @@ -6970,10 +10267,9 @@ static void printInstruction(MCInst *MI, SStream *O) Bits |= (uint64_t)OpInfo0[opcode] << 0; Bits |= (uint64_t)OpInfo1[opcode] << 32; #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 4095)-1); + SStream_concat0(O, AsmStrs + (Bits & 4095) - 1); #endif - // Fragment 0 encoded into 5 bits for 32 unique commands. // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 12) & 31)); switch ((Bits >> 12) & 31) { @@ -7160,7 +10456,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 1 encoded into 7 bits for 75 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 17) & 127)); switch ((Bits >> 17) & 127) { @@ -7711,7 +11006,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 2 encoded into 6 bits for 60 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 63)); switch ((Bits >> 24) & 63) { @@ -8092,7 +11386,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 3 encoded into 5 bits for 30 unique commands. // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 30) & 31)); switch ((Bits >> 30) & 31) { @@ -8258,7 +11551,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 4 encoded into 7 bits for 65 unique commands. // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 35) & 127)); switch ((Bits >> 35) & 127) { @@ -8663,7 +11955,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 5 encoded into 5 bits for 23 unique commands. // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 42) & 31)); switch ((Bits >> 42) & 31) { @@ -8811,7 +12102,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 6 encoded into 6 bits for 38 unique commands. // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 47) & 63)); switch ((Bits >> 47) & 63) { @@ -9032,7 +12322,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 7 encoded into 4 bits for 13 unique commands. // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 53) & 15)); switch ((Bits >> 53) & 15) { @@ -9107,7 +12396,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 8 encoded into 4 bits for 12 unique commands. // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 57) & 15)); switch ((Bits >> 57) & 15) { @@ -9206,7 +12494,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 9 encoded into 1 bits for 2 unique commands. // printf("Fragment 9: %"PRIu64"\n", ((Bits >> 61) & 1)); if ((Bits >> 61) & 1) { @@ -9217,7 +12504,6 @@ static void printInstruction(MCInst *MI, SStream *O) return; } - // Fragment 10 encoded into 1 bits for 2 unique commands. // printf("Fragment 10: %"PRIu64"\n", ((Bits >> 62) & 1)); if ((Bits >> 62) & 1) { @@ -9230,21 +12516,18 @@ static void printInstruction(MCInst *MI, SStream *O) printAddrMode6Operand(MI, 4, O); return; } - } - - #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR -static bool printAliasInstr(MCInst *MI, SStream *OS) -{ +static bool printAliasInstr(MCInst *MI, SStream *OS) { unsigned int I = 0, OpIdx, PrintMethodIdx; char *tmpString; const char *AsmString; switch (MCInst_getOpcode(MI)) { - default: return false; + default: + return false; case ARM_DSB: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && @@ -9487,11 +12770,10 @@ static bool printAliasInstr(MCInst *MI, SStream *OS) return false; } - tmpString = cs_strdup(AsmString); - while (AsmString[I] != ' ' && AsmString[I] != '\t' && - AsmString[I] != '$' && AsmString[I] != '\0') + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') ++I; tmpString[I] = 0; @@ -9513,7 +12795,7 @@ static bool printAliasInstr(MCInst *MI, SStream *OS) PrintMethodIdx = AsmString[I++] - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else - printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); + printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); } else { if (AsmString[I] == '[') { set_mem_access(MI, true); @@ -9527,12 +12809,9 @@ static bool printAliasInstr(MCInst *MI, SStream *OS) return true; } - -static void printCustomAliasOperand( - MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - SStream *OS) -{ + +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { switch (PrintMethodIdx) { default: break; diff --git a/arch/ARM/ARMGenDisassemblerTables.inc b/arch/ARM/ARMGenDisassemblerTables.inc index 385a7d555c..8e3306f09e 100644 --- a/arch/ARM/ARMGenDisassemblerTables.inc +++ b/arch/ARM/ARMGenDisassemblerTables.inc @@ -1,15185 +1,133628 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2019 */ +/* By Phosphorus15 , Year 2021 */ +/* This generator is under https://github.com/rizinorg/llvm-capstone */ /* Automatically generated file, do not edit! */ -#include "../../MCInst.h" #include "../../LEB128.h" +#include "../../MCInst.h" +#define ARM_ARMv2 0ULL +#define ARM_ARMv2a 1ULL +#define ARM_ARMv3 2ULL +#define ARM_ARMv3m 3ULL +#define ARM_ARMv4 4ULL +#define ARM_ARMv4t 5ULL +#define ARM_ARMv5t 6ULL +#define ARM_ARMv5te 7ULL +#define ARM_ARMv5tej 8ULL +#define ARM_ARMv6 9ULL +#define ARM_ARMv6j 10ULL +#define ARM_ARMv6k 11ULL +#define ARM_ARMv6kz 12ULL +#define ARM_ARMv6m 13ULL +#define ARM_ARMv6sm 14ULL +#define ARM_ARMv6t2 15ULL +#define ARM_ARMv7a 16ULL +#define ARM_ARMv7em 17ULL +#define ARM_ARMv7k 18ULL +#define ARM_ARMv7m 19ULL +#define ARM_ARMv7r 20ULL +#define ARM_ARMv7s 21ULL +#define ARM_ARMv7ve 22ULL +#define ARM_ARMv8a 23ULL +#define ARM_ARMv8mBaseline 24ULL +#define ARM_ARMv8mMainline 25ULL +#define ARM_ARMv8r 26ULL +#define ARM_ARMv9a 27ULL +#define ARM_ARMv81a 28ULL +#define ARM_ARMv81mMainline 29ULL +#define ARM_ARMv82a 30ULL +#define ARM_ARMv83a 31ULL +#define ARM_ARMv84a 32ULL +#define ARM_ARMv85a 33ULL +#define ARM_ARMv86a 34ULL +#define ARM_ARMv87a 35ULL +#define ARM_ARMv91a 36ULL +#define ARM_ARMv92a 37ULL +#define ARM_Feature8MSecExt 38ULL +#define ARM_FeatureAClass 39ULL +#define ARM_FeatureAES 40ULL +#define ARM_FeatureAcquireRelease 41ULL +#define ARM_FeatureAvoidMOVsShOp 42ULL +#define ARM_FeatureAvoidPartialCPSR 43ULL +#define ARM_FeatureBF16 44ULL +#define ARM_FeatureCRC 45ULL +#define ARM_FeatureCheapPredicableCPSR 46ULL +#define ARM_FeatureCheckVLDnAlign 47ULL +#define ARM_FeatureCoprocCDE0 48ULL +#define ARM_FeatureCoprocCDE1 49ULL +#define ARM_FeatureCoprocCDE2 50ULL +#define ARM_FeatureCoprocCDE3 51ULL +#define ARM_FeatureCoprocCDE4 52ULL +#define ARM_FeatureCoprocCDE5 53ULL +#define ARM_FeatureCoprocCDE6 54ULL +#define ARM_FeatureCoprocCDE7 55ULL +#define ARM_FeatureCrypto 56ULL +#define ARM_FeatureD32 57ULL +#define ARM_FeatureDB 58ULL +#define ARM_FeatureDFB 59ULL +#define ARM_FeatureDSP 60ULL +#define ARM_FeatureDontWidenVMOVS 61ULL +#define ARM_FeatureDotProd 62ULL +#define ARM_FeatureExecuteOnly 63ULL +#define ARM_FeatureExpandMLx 64ULL +#define ARM_FeatureFP16 65ULL +#define ARM_FeatureFP16FML 66ULL +#define ARM_FeatureFP64 67ULL +#define ARM_FeatureFPAO 68ULL +#define ARM_FeatureFPARMv8 69ULL +#define ARM_FeatureFPARMv8_D16 70ULL +#define ARM_FeatureFPARMv8_D16_SP 71ULL +#define ARM_FeatureFPARMv8_SP 72ULL +#define ARM_FeatureFPRegs 73ULL +#define ARM_FeatureFPRegs16 74ULL +#define ARM_FeatureFPRegs64 75ULL +#define ARM_FeatureFixCMSE_CVE_2021_35465 76ULL +#define ARM_FeatureFullFP16 77ULL +#define ARM_FeatureFuseAES 78ULL +#define ARM_FeatureFuseLiterals 79ULL +#define ARM_FeatureHWDivARM 80ULL +#define ARM_FeatureHWDivThumb 81ULL +#define ARM_FeatureHardenSlsBlr 82ULL +#define ARM_FeatureHardenSlsNoComdat 83ULL +#define ARM_FeatureHardenSlsRetBr 84ULL +#define ARM_FeatureHasNoBranchPredictor 85ULL +#define ARM_FeatureHasRetAddrStack 86ULL +#define ARM_FeatureHasSlowFPVFMx 87ULL +#define ARM_FeatureHasSlowFPVMLx 88ULL +#define ARM_FeatureHasVMLxHazards 89ULL +#define ARM_FeatureLOB 90ULL +#define ARM_FeatureLongCalls 91ULL +#define ARM_FeatureMClass 92ULL +#define ARM_FeatureMP 93ULL +#define ARM_FeatureMVEVectorCostFactor1 94ULL +#define ARM_FeatureMVEVectorCostFactor2 95ULL +#define ARM_FeatureMVEVectorCostFactor4 96ULL +#define ARM_FeatureMatMulInt8 97ULL +#define ARM_FeatureMuxedUnits 98ULL +#define ARM_FeatureNEON 99ULL +#define ARM_FeatureNEONForFP 100ULL +#define ARM_FeatureNEONForFPMovs 101ULL +#define ARM_FeatureNaClTrap 102ULL +#define ARM_FeatureNoARM 103ULL +#define ARM_FeatureNoMovt 104ULL +#define ARM_FeatureNoNegativeImmediates 105ULL +#define ARM_FeatureNoPostRASched 106ULL +#define ARM_FeatureNonpipelinedVFP 107ULL +#define ARM_FeaturePerfMon 108ULL +#define ARM_FeaturePref32BitThumb 109ULL +#define ARM_FeaturePrefISHSTBarrier 110ULL +#define ARM_FeaturePrefLoopAlign32 111ULL +#define ARM_FeaturePreferVMOVSR 112ULL +#define ARM_FeatureProfUnpredicate 113ULL +#define ARM_FeatureRAS 114ULL +#define ARM_FeatureRClass 115ULL +#define ARM_FeatureReadTp 116ULL +#define ARM_FeatureReserveR9 117ULL +#define ARM_FeatureSB 118ULL +#define ARM_FeatureSHA2 119ULL +#define ARM_FeatureSlowFPBrcc 120ULL +#define ARM_FeatureSlowLoadDSubreg 121ULL +#define ARM_FeatureSlowOddRegister 122ULL +#define ARM_FeatureSlowVDUP32 123ULL +#define ARM_FeatureSlowVGETLNi32 124ULL +#define ARM_FeatureSplatVFPToNeon 125ULL +#define ARM_FeatureStrictAlign 126ULL +#define ARM_FeatureThumb2 127ULL +#define ARM_FeatureTrustZone 128ULL +#define ARM_FeatureUseMISched 129ULL +#define ARM_FeatureUseWideStrideVFP 130ULL +#define ARM_FeatureV7Clrex 131ULL +#define ARM_FeatureVFP2 132ULL +#define ARM_FeatureVFP2_SP 133ULL +#define ARM_FeatureVFP3 134ULL +#define ARM_FeatureVFP3_D16 135ULL +#define ARM_FeatureVFP3_D16_SP 136ULL +#define ARM_FeatureVFP3_SP 137ULL +#define ARM_FeatureVFP4 138ULL +#define ARM_FeatureVFP4_D16 139ULL +#define ARM_FeatureVFP4_D16_SP 140ULL +#define ARM_FeatureVFP4_SP 141ULL +#define ARM_FeatureVMLxForwarding 142ULL +#define ARM_FeatureVirtualization 143ULL +#define ARM_FeatureZCZeroing 144ULL +#define ARM_HasCDEOps 145ULL +#define ARM_HasMVEFloatOps 146ULL +#define ARM_HasMVEIntegerOps 147ULL +#define ARM_HasV4TOps 148ULL +#define ARM_HasV5TEOps 149ULL +#define ARM_HasV5TOps 150ULL +#define ARM_HasV6KOps 151ULL +#define ARM_HasV6MOps 152ULL +#define ARM_HasV6Ops 153ULL +#define ARM_HasV6T2Ops 154ULL +#define ARM_HasV7Ops 155ULL +#define ARM_HasV8MBaselineOps 156ULL +#define ARM_HasV8MMainlineOps 157ULL +#define ARM_HasV8Ops 158ULL +#define ARM_HasV8_1MMainlineOps 159ULL +#define ARM_HasV8_1aOps 160ULL +#define ARM_HasV8_2aOps 161ULL +#define ARM_HasV8_3aOps 162ULL +#define ARM_HasV8_4aOps 163ULL +#define ARM_HasV8_5aOps 164ULL +#define ARM_HasV8_6aOps 165ULL +#define ARM_HasV8_7aOps 166ULL +#define ARM_HasV9_0aOps 167ULL +#define ARM_HasV9_1aOps 168ULL +#define ARM_HasV9_2aOps 169ULL +#define ARM_IWMMXT 170ULL +#define ARM_IWMMXT2 171ULL +#define ARM_ModeSoftFloat 172ULL +#define ARM_ModeThumb 173ULL +#define ARM_ProcA5 174ULL +#define ARM_ProcA7 175ULL +#define ARM_ProcA8 176ULL +#define ARM_ProcA9 177ULL +#define ARM_ProcA12 178ULL +#define ARM_ProcA15 179ULL +#define ARM_ProcA17 180ULL +#define ARM_ProcA32 181ULL +#define ARM_ProcA35 182ULL +#define ARM_ProcA53 183ULL +#define ARM_ProcA55 184ULL +#define ARM_ProcA57 185ULL +#define ARM_ProcA72 186ULL +#define ARM_ProcA73 187ULL +#define ARM_ProcA75 188ULL +#define ARM_ProcA76 189ULL +#define ARM_ProcA77 190ULL +#define ARM_ProcA78 191ULL +#define ARM_ProcA78C 192ULL +#define ARM_ProcA710 193ULL +#define ARM_ProcExynos 194ULL +#define ARM_ProcKrait 195ULL +#define ARM_ProcKryo 196ULL +#define ARM_ProcM3 197ULL +#define ARM_ProcM7 198ULL +#define ARM_ProcR4 199ULL +#define ARM_ProcR5 200ULL +#define ARM_ProcR7 201ULL +#define ARM_ProcR52 202ULL +#define ARM_ProcSwift 203ULL +#define ARM_ProcV1 204ULL +#define ARM_ProcX1 205ULL +#define ARM_XScale 206ULL +#ifdef MIPS_GET_DISASSEMBLER +#undef MIPS_GET_DISASSEMBLER // Helper function for extracting fields from encoded instructions. - -//#if defined(_MSC_VER) && !defined(__clang__) -//__declspec(noinline) -//#endif - -#define FieldFromInstruction(fname, InsnType) \ -static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ -{ \ - InsnType fieldMask; \ - if (numBits == sizeof(InsnType) * 8) \ - fieldMask = (InsnType)(-1LL); \ - else \ - fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ - return (insn & fieldMask) >> startBit; \ -} +#define FieldFromInstruction(fname, InsnType) \ + static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ + } static const uint8_t DecoderTableARM32[] = { -/* 0 */ MCD_OPC_ExtractField, 25, 3, // Inst{27-25} ... -/* 3 */ MCD_OPC_FilterValue, 0, 47, 14, 0, // Skip to: 3639 -/* 8 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 11 */ MCD_OPC_FilterValue, 0, 110, 7, 0, // Skip to: 1918 -/* 16 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 19 */ MCD_OPC_FilterValue, 0, 139, 1, 0, // Skip to: 419 -/* 24 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 27 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 155 -/* 32 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 35 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 65 -/* 40 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 56 -/* 45 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 56 -/* 52 */ MCD_OPC_Decode, 159, 4, 0, // Opcode: ANDrr -/* 56 */ MCD_OPC_CheckPredicate, 0, 92, 32, 0, // Skip to: 8345 -/* 61 */ MCD_OPC_Decode, 160, 4, 1, // Opcode: ANDrsi -/* 65 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 95 -/* 70 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 86 -/* 75 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 86 -/* 82 */ MCD_OPC_Decode, 245, 6, 0, // Opcode: SUBrr -/* 86 */ MCD_OPC_CheckPredicate, 0, 62, 32, 0, // Skip to: 8345 -/* 91 */ MCD_OPC_Decode, 246, 6, 1, // Opcode: SUBrsi -/* 95 */ MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 125 -/* 100 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 116 -/* 105 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 116 -/* 112 */ MCD_OPC_Decode, 150, 4, 0, // Opcode: ADDrr -/* 116 */ MCD_OPC_CheckPredicate, 0, 32, 32, 0, // Skip to: 8345 -/* 121 */ MCD_OPC_Decode, 151, 4, 1, // Opcode: ADDrsi -/* 125 */ MCD_OPC_FilterValue, 3, 23, 32, 0, // Skip to: 8345 -/* 130 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 146 -/* 135 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 146 -/* 142 */ MCD_OPC_Decode, 239, 5, 0, // Opcode: SBCrr -/* 146 */ MCD_OPC_CheckPredicate, 0, 2, 32, 0, // Skip to: 8345 -/* 151 */ MCD_OPC_Decode, 240, 5, 1, // Opcode: SBCrsi -/* 155 */ MCD_OPC_FilterValue, 1, 249, 31, 0, // Skip to: 8345 -/* 160 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 163 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 227 -/* 168 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 171 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 185 -/* 176 */ MCD_OPC_CheckPredicate, 0, 228, 31, 0, // Skip to: 8345 -/* 181 */ MCD_OPC_Decode, 161, 4, 2, // Opcode: ANDrsr -/* 185 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 199 -/* 190 */ MCD_OPC_CheckPredicate, 0, 214, 31, 0, // Skip to: 8345 -/* 195 */ MCD_OPC_Decode, 247, 6, 2, // Opcode: SUBrsr -/* 199 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 213 -/* 204 */ MCD_OPC_CheckPredicate, 0, 200, 31, 0, // Skip to: 8345 -/* 209 */ MCD_OPC_Decode, 152, 4, 2, // Opcode: ADDrsr -/* 213 */ MCD_OPC_FilterValue, 3, 191, 31, 0, // Skip to: 8345 -/* 218 */ MCD_OPC_CheckPredicate, 0, 186, 31, 0, // Skip to: 8345 -/* 223 */ MCD_OPC_Decode, 241, 5, 3, // Opcode: SBCrsr -/* 227 */ MCD_OPC_FilterValue, 1, 177, 31, 0, // Skip to: 8345 -/* 232 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 235 */ MCD_OPC_FilterValue, 0, 71, 0, 0, // Skip to: 311 -/* 240 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 243 */ MCD_OPC_FilterValue, 0, 14, 0, 0, // Skip to: 262 -/* 248 */ MCD_OPC_CheckPredicate, 1, 156, 31, 0, // Skip to: 8345 -/* 253 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 258 */ MCD_OPC_Decode, 188, 5, 4, // Opcode: MUL -/* 262 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 283 -/* 267 */ MCD_OPC_CheckPredicate, 1, 137, 31, 0, // Skip to: 8345 -/* 272 */ MCD_OPC_CheckField, 20, 1, 0, 130, 31, 0, // Skip to: 8345 -/* 279 */ MCD_OPC_Decode, 152, 7, 5, // Opcode: UMAAL -/* 283 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 297 -/* 288 */ MCD_OPC_CheckPredicate, 1, 116, 31, 0, // Skip to: 8345 -/* 293 */ MCD_OPC_Decode, 154, 7, 6, // Opcode: UMULL -/* 297 */ MCD_OPC_FilterValue, 3, 107, 31, 0, // Skip to: 8345 -/* 302 */ MCD_OPC_CheckPredicate, 1, 102, 31, 0, // Skip to: 8345 -/* 307 */ MCD_OPC_Decode, 165, 6, 6, // Opcode: SMULL -/* 311 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 347 -/* 316 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 319 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 333 -/* 324 */ MCD_OPC_CheckPredicate, 0, 80, 31, 0, // Skip to: 8345 -/* 329 */ MCD_OPC_Decode, 234, 6, 7, // Opcode: STRH_POST -/* 333 */ MCD_OPC_FilterValue, 1, 71, 31, 0, // Skip to: 8345 -/* 338 */ MCD_OPC_CheckPredicate, 0, 66, 31, 0, // Skip to: 8345 -/* 343 */ MCD_OPC_Decode, 143, 5, 7, // Opcode: LDRH_POST -/* 347 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 383 -/* 352 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 355 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 369 -/* 360 */ MCD_OPC_CheckPredicate, 0, 44, 31, 0, // Skip to: 8345 -/* 365 */ MCD_OPC_Decode, 134, 5, 7, // Opcode: LDRD_POST -/* 369 */ MCD_OPC_FilterValue, 1, 35, 31, 0, // Skip to: 8345 -/* 374 */ MCD_OPC_CheckPredicate, 0, 30, 31, 0, // Skip to: 8345 -/* 379 */ MCD_OPC_Decode, 148, 5, 7, // Opcode: LDRSB_POST -/* 383 */ MCD_OPC_FilterValue, 3, 21, 31, 0, // Skip to: 8345 -/* 388 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 391 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 405 -/* 396 */ MCD_OPC_CheckPredicate, 0, 8, 31, 0, // Skip to: 8345 -/* 401 */ MCD_OPC_Decode, 225, 6, 7, // Opcode: STRD_POST -/* 405 */ MCD_OPC_FilterValue, 1, 255, 30, 0, // Skip to: 8345 -/* 410 */ MCD_OPC_CheckPredicate, 0, 250, 30, 0, // Skip to: 8345 -/* 415 */ MCD_OPC_Decode, 153, 5, 7, // Opcode: LDRSH_POST -/* 419 */ MCD_OPC_FilterValue, 1, 241, 30, 0, // Skip to: 8345 -/* 424 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 427 */ MCD_OPC_FilterValue, 0, 6, 2, 0, // Skip to: 950 -/* 432 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 435 */ MCD_OPC_FilterValue, 0, 152, 1, 0, // Skip to: 848 -/* 440 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 443 */ MCD_OPC_FilterValue, 0, 66, 1, 0, // Skip to: 770 -/* 448 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... -/* 451 */ MCD_OPC_FilterValue, 14, 67, 0, 0, // Skip to: 523 -/* 456 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 459 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 491 -/* 464 */ MCD_OPC_CheckPredicate, 2, 171, 0, 0, // Skip to: 640 -/* 469 */ MCD_OPC_CheckField, 6, 2, 1, 164, 0, 0, // Skip to: 640 -/* 476 */ MCD_OPC_CheckField, 4, 1, 0, 157, 0, 0, // Skip to: 640 -/* 483 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, -/* 487 */ MCD_OPC_Decode, 194, 4, 8, // Opcode: CRC32B -/* 491 */ MCD_OPC_FilterValue, 1, 144, 0, 0, // Skip to: 640 -/* 496 */ MCD_OPC_CheckPredicate, 2, 139, 0, 0, // Skip to: 640 -/* 501 */ MCD_OPC_CheckField, 6, 2, 1, 132, 0, 0, // Skip to: 640 -/* 508 */ MCD_OPC_CheckField, 4, 1, 0, 125, 0, 0, // Skip to: 640 -/* 515 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, -/* 519 */ MCD_OPC_Decode, 195, 4, 8, // Opcode: CRC32CB -/* 523 */ MCD_OPC_FilterValue, 15, 112, 0, 0, // Skip to: 640 -/* 528 */ MCD_OPC_ExtractField, 10, 8, // Inst{17-10} ... -/* 531 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 559 -/* 536 */ MCD_OPC_CheckPredicate, 0, 99, 0, 0, // Skip to: 640 -/* 541 */ MCD_OPC_CheckField, 9, 1, 0, 92, 0, 0, // Skip to: 640 -/* 548 */ MCD_OPC_CheckField, 0, 5, 0, 85, 0, 0, // Skip to: 640 -/* 555 */ MCD_OPC_Decode, 192, 4, 9, // Opcode: CPS2p -/* 559 */ MCD_OPC_FilterValue, 64, 30, 0, 0, // Skip to: 594 -/* 564 */ MCD_OPC_CheckPredicate, 0, 71, 0, 0, // Skip to: 640 -/* 569 */ MCD_OPC_CheckField, 18, 2, 0, 64, 0, 0, // Skip to: 640 -/* 576 */ MCD_OPC_CheckField, 6, 3, 0, 57, 0, 0, // Skip to: 640 -/* 583 */ MCD_OPC_CheckField, 0, 5, 0, 50, 0, 0, // Skip to: 640 -/* 590 */ MCD_OPC_Decode, 245, 5, 10, // Opcode: SETEND -/* 594 */ MCD_OPC_FilterValue, 128, 1, 40, 0, 0, // Skip to: 640 -/* 600 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 603 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 640 -/* 608 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 631 -/* 613 */ MCD_OPC_CheckField, 18, 2, 0, 11, 0, 0, // Skip to: 631 -/* 620 */ MCD_OPC_CheckField, 6, 3, 0, 4, 0, 0, // Skip to: 631 -/* 627 */ MCD_OPC_Decode, 191, 4, 9, // Opcode: CPS1p -/* 631 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 640 -/* 636 */ MCD_OPC_Decode, 193, 4, 9, // Opcode: CPS3p -/* 640 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 643 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 684 -/* 648 */ MCD_OPC_CheckPredicate, 0, 88, 4, 0, // Skip to: 1765 -/* 653 */ MCD_OPC_CheckField, 16, 1, 1, 81, 4, 0, // Skip to: 1765 -/* 660 */ MCD_OPC_CheckField, 9, 1, 0, 74, 4, 0, // Skip to: 1765 -/* 667 */ MCD_OPC_CheckField, 4, 1, 0, 67, 4, 0, // Skip to: 1765 -/* 674 */ MCD_OPC_SoftFail, 143, 26 /* 0xd0f */, 128, 128, 56 /* 0xe0000 */, -/* 680 */ MCD_OPC_Decode, 182, 5, 11, // Opcode: MRS -/* 684 */ MCD_OPC_FilterValue, 1, 20, 0, 0, // Skip to: 709 -/* 689 */ MCD_OPC_CheckPredicate, 0, 47, 4, 0, // Skip to: 1765 -/* 694 */ MCD_OPC_CheckField, 4, 1, 1, 40, 4, 0, // Skip to: 1765 -/* 701 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, -/* 705 */ MCD_OPC_Decode, 205, 5, 12, // Opcode: QADD -/* 709 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 749 -/* 714 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 717 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 731 -/* 722 */ MCD_OPC_CheckPredicate, 3, 14, 4, 0, // Skip to: 1765 -/* 727 */ MCD_OPC_Decode, 136, 6, 13, // Opcode: SMLABB -/* 731 */ MCD_OPC_FilterValue, 1, 5, 4, 0, // Skip to: 1765 -/* 736 */ MCD_OPC_CheckPredicate, 4, 0, 4, 0, // Skip to: 1765 -/* 741 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, -/* 745 */ MCD_OPC_Decode, 249, 6, 14, // Opcode: SWP -/* 749 */ MCD_OPC_FilterValue, 3, 243, 3, 0, // Skip to: 1765 -/* 754 */ MCD_OPC_CheckPredicate, 3, 238, 3, 0, // Skip to: 1765 -/* 759 */ MCD_OPC_CheckField, 4, 1, 0, 231, 3, 0, // Skip to: 1765 -/* 766 */ MCD_OPC_Decode, 137, 6, 13, // Opcode: SMLABT -/* 770 */ MCD_OPC_FilterValue, 1, 222, 3, 0, // Skip to: 1765 -/* 775 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 778 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 806 -/* 783 */ MCD_OPC_CheckPredicate, 5, 209, 3, 0, // Skip to: 1765 -/* 788 */ MCD_OPC_CheckField, 28, 4, 14, 202, 3, 0, // Skip to: 1765 -/* 795 */ MCD_OPC_CheckField, 4, 1, 1, 195, 3, 0, // Skip to: 1765 -/* 802 */ MCD_OPC_Decode, 219, 4, 15, // Opcode: HLT -/* 806 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 827 -/* 811 */ MCD_OPC_CheckPredicate, 3, 181, 3, 0, // Skip to: 1765 -/* 816 */ MCD_OPC_CheckField, 4, 1, 0, 174, 3, 0, // Skip to: 1765 -/* 823 */ MCD_OPC_Decode, 147, 6, 13, // Opcode: SMLATB -/* 827 */ MCD_OPC_FilterValue, 3, 165, 3, 0, // Skip to: 1765 -/* 832 */ MCD_OPC_CheckPredicate, 3, 160, 3, 0, // Skip to: 1765 -/* 837 */ MCD_OPC_CheckField, 4, 1, 0, 153, 3, 0, // Skip to: 1765 -/* 844 */ MCD_OPC_Decode, 148, 6, 13, // Opcode: SMLATT -/* 848 */ MCD_OPC_FilterValue, 1, 144, 3, 0, // Skip to: 1765 -/* 853 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 856 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 924 -/* 861 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 882 -/* 866 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 882 -/* 873 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 878 */ MCD_OPC_Decode, 137, 7, 16, // Opcode: TSTrr -/* 882 */ MCD_OPC_CheckPredicate, 6, 23, 0, 0, // Skip to: 910 -/* 887 */ MCD_OPC_CheckField, 28, 4, 15, 16, 0, 0, // Skip to: 910 -/* 894 */ MCD_OPC_CheckField, 5, 3, 0, 9, 0, 0, // Skip to: 910 -/* 901 */ MCD_OPC_SoftFail, 143, 250, 63 /* 0xffd0f */, 0, -/* 906 */ MCD_OPC_Decode, 246, 5, 10, // Opcode: SETPAN -/* 910 */ MCD_OPC_CheckPredicate, 0, 82, 3, 0, // Skip to: 1765 -/* 915 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 920 */ MCD_OPC_Decode, 138, 7, 17, // Opcode: TSTrsi -/* 924 */ MCD_OPC_FilterValue, 1, 68, 3, 0, // Skip to: 1765 -/* 929 */ MCD_OPC_CheckPredicate, 0, 63, 3, 0, // Skip to: 1765 -/* 934 */ MCD_OPC_CheckField, 7, 1, 0, 56, 3, 0, // Skip to: 1765 -/* 941 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 946 */ MCD_OPC_Decode, 139, 7, 18, // Opcode: TSTrsr -/* 950 */ MCD_OPC_FilterValue, 1, 62, 1, 0, // Skip to: 1273 -/* 955 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 958 */ MCD_OPC_FilterValue, 0, 192, 0, 0, // Skip to: 1155 -/* 963 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 966 */ MCD_OPC_FilterValue, 0, 144, 0, 0, // Skip to: 1115 -/* 971 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... -/* 974 */ MCD_OPC_FilterValue, 0, 22, 0, 0, // Skip to: 1001 -/* 979 */ MCD_OPC_CheckPredicate, 0, 13, 3, 0, // Skip to: 1765 -/* 984 */ MCD_OPC_CheckField, 9, 1, 0, 6, 3, 0, // Skip to: 1765 -/* 991 */ MCD_OPC_SoftFail, 143, 26 /* 0xd0f */, 128, 128, 60 /* 0xf0000 */, -/* 997 */ MCD_OPC_Decode, 184, 5, 11, // Opcode: MRSsys -/* 1001 */ MCD_OPC_FilterValue, 2, 53, 0, 0, // Skip to: 1059 -/* 1006 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 1009 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 1034 -/* 1014 */ MCD_OPC_CheckPredicate, 2, 234, 2, 0, // Skip to: 1765 -/* 1019 */ MCD_OPC_CheckField, 28, 4, 14, 227, 2, 0, // Skip to: 1765 -/* 1026 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, -/* 1030 */ MCD_OPC_Decode, 199, 4, 8, // Opcode: CRC32W -/* 1034 */ MCD_OPC_FilterValue, 1, 214, 2, 0, // Skip to: 1765 -/* 1039 */ MCD_OPC_CheckPredicate, 2, 209, 2, 0, // Skip to: 1765 -/* 1044 */ MCD_OPC_CheckField, 28, 4, 14, 202, 2, 0, // Skip to: 1765 -/* 1051 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, -/* 1055 */ MCD_OPC_Decode, 197, 4, 8, // Opcode: CRC32CW -/* 1059 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1073 -/* 1064 */ MCD_OPC_CheckPredicate, 3, 184, 2, 0, // Skip to: 1765 -/* 1069 */ MCD_OPC_Decode, 141, 6, 19, // Opcode: SMLALBB -/* 1073 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1087 -/* 1078 */ MCD_OPC_CheckPredicate, 3, 170, 2, 0, // Skip to: 1765 -/* 1083 */ MCD_OPC_Decode, 145, 6, 19, // Opcode: SMLALTB -/* 1087 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1101 -/* 1092 */ MCD_OPC_CheckPredicate, 3, 156, 2, 0, // Skip to: 1765 -/* 1097 */ MCD_OPC_Decode, 142, 6, 19, // Opcode: SMLALBT -/* 1101 */ MCD_OPC_FilterValue, 7, 147, 2, 0, // Skip to: 1765 -/* 1106 */ MCD_OPC_CheckPredicate, 3, 142, 2, 0, // Skip to: 1765 -/* 1111 */ MCD_OPC_Decode, 146, 6, 19, // Opcode: SMLALTT -/* 1115 */ MCD_OPC_FilterValue, 1, 133, 2, 0, // Skip to: 1765 -/* 1120 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 1141 -/* 1125 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 1141 -/* 1132 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 1137 */ MCD_OPC_Decode, 188, 4, 20, // Opcode: CMPrr -/* 1141 */ MCD_OPC_CheckPredicate, 0, 107, 2, 0, // Skip to: 1765 -/* 1146 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 1151 */ MCD_OPC_Decode, 189, 4, 17, // Opcode: CMPrsi -/* 1155 */ MCD_OPC_FilterValue, 1, 93, 2, 0, // Skip to: 1765 -/* 1160 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 1163 */ MCD_OPC_FilterValue, 0, 73, 0, 0, // Skip to: 1241 -/* 1168 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1171 */ MCD_OPC_FilterValue, 0, 46, 0, 0, // Skip to: 1222 -/* 1176 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 1179 */ MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 1197 -/* 1184 */ MCD_OPC_CheckPredicate, 0, 64, 2, 0, // Skip to: 1765 -/* 1189 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, -/* 1193 */ MCD_OPC_Decode, 209, 5, 21, // Opcode: QDADD -/* 1197 */ MCD_OPC_FilterValue, 3, 51, 2, 0, // Skip to: 1765 -/* 1202 */ MCD_OPC_CheckPredicate, 7, 46, 2, 0, // Skip to: 1765 -/* 1207 */ MCD_OPC_SoftFail, 128, 128, 128, 128, 1 /* 0x10000000 */, 128, 128, 128, 128, 14 /* 0xffffffffe0000000 */, -/* 1218 */ MCD_OPC_Decode, 220, 4, 15, // Opcode: HVC -/* 1222 */ MCD_OPC_FilterValue, 1, 26, 2, 0, // Skip to: 1765 -/* 1227 */ MCD_OPC_CheckPredicate, 0, 21, 2, 0, // Skip to: 1765 -/* 1232 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 1237 */ MCD_OPC_Decode, 190, 4, 18, // Opcode: CMPrsr -/* 1241 */ MCD_OPC_FilterValue, 1, 7, 2, 0, // Skip to: 1765 -/* 1246 */ MCD_OPC_CheckPredicate, 4, 2, 2, 0, // Skip to: 1765 -/* 1251 */ MCD_OPC_CheckField, 20, 1, 0, 251, 1, 0, // Skip to: 1765 -/* 1258 */ MCD_OPC_CheckField, 5, 2, 0, 244, 1, 0, // Skip to: 1765 -/* 1265 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, -/* 1269 */ MCD_OPC_Decode, 250, 6, 14, // Opcode: SWPB -/* 1273 */ MCD_OPC_FilterValue, 2, 241, 0, 0, // Skip to: 1519 -/* 1278 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1281 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1311 -/* 1286 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1302 -/* 1291 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1302 -/* 1298 */ MCD_OPC_Decode, 194, 5, 0, // Opcode: ORRrr -/* 1302 */ MCD_OPC_CheckPredicate, 0, 202, 1, 0, // Skip to: 1765 -/* 1307 */ MCD_OPC_Decode, 195, 5, 1, // Opcode: ORRrsi -/* 1311 */ MCD_OPC_FilterValue, 1, 193, 1, 0, // Skip to: 1765 -/* 1316 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 1319 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1333 -/* 1324 */ MCD_OPC_CheckPredicate, 0, 180, 1, 0, // Skip to: 1765 -/* 1329 */ MCD_OPC_Decode, 196, 5, 2, // Opcode: ORRrsr -/* 1333 */ MCD_OPC_FilterValue, 1, 171, 1, 0, // Skip to: 1765 -/* 1338 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1341 */ MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 1405 -/* 1346 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1349 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1377 -/* 1354 */ MCD_OPC_CheckPredicate, 8, 150, 1, 0, // Skip to: 1765 -/* 1359 */ MCD_OPC_CheckField, 12, 4, 15, 143, 1, 0, // Skip to: 1765 -/* 1366 */ MCD_OPC_CheckField, 5, 2, 0, 136, 1, 0, // Skip to: 1765 -/* 1373 */ MCD_OPC_Decode, 201, 6, 22, // Opcode: STL -/* 1377 */ MCD_OPC_FilterValue, 1, 127, 1, 0, // Skip to: 1765 -/* 1382 */ MCD_OPC_CheckPredicate, 8, 122, 1, 0, // Skip to: 1765 -/* 1387 */ MCD_OPC_CheckField, 5, 2, 0, 115, 1, 0, // Skip to: 1765 -/* 1394 */ MCD_OPC_CheckField, 0, 4, 15, 108, 1, 0, // Skip to: 1765 -/* 1401 */ MCD_OPC_Decode, 222, 4, 23, // Opcode: LDA -/* 1405 */ MCD_OPC_FilterValue, 14, 52, 0, 0, // Skip to: 1462 -/* 1410 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1413 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1434 -/* 1418 */ MCD_OPC_CheckPredicate, 9, 86, 1, 0, // Skip to: 1765 -/* 1423 */ MCD_OPC_CheckField, 5, 2, 0, 79, 1, 0, // Skip to: 1765 -/* 1430 */ MCD_OPC_Decode, 203, 6, 24, // Opcode: STLEX -/* 1434 */ MCD_OPC_FilterValue, 1, 70, 1, 0, // Skip to: 1765 -/* 1439 */ MCD_OPC_CheckPredicate, 9, 65, 1, 0, // Skip to: 1765 -/* 1444 */ MCD_OPC_CheckField, 5, 2, 0, 58, 1, 0, // Skip to: 1765 -/* 1451 */ MCD_OPC_CheckField, 0, 4, 15, 51, 1, 0, // Skip to: 1765 -/* 1458 */ MCD_OPC_Decode, 224, 4, 23, // Opcode: LDAEX -/* 1462 */ MCD_OPC_FilterValue, 15, 42, 1, 0, // Skip to: 1765 -/* 1467 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1470 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1491 -/* 1475 */ MCD_OPC_CheckPredicate, 0, 29, 1, 0, // Skip to: 1765 -/* 1480 */ MCD_OPC_CheckField, 5, 2, 0, 22, 1, 0, // Skip to: 1765 -/* 1487 */ MCD_OPC_Decode, 227, 6, 24, // Opcode: STREX -/* 1491 */ MCD_OPC_FilterValue, 1, 13, 1, 0, // Skip to: 1765 -/* 1496 */ MCD_OPC_CheckPredicate, 0, 8, 1, 0, // Skip to: 1765 -/* 1501 */ MCD_OPC_CheckField, 5, 2, 0, 1, 1, 0, // Skip to: 1765 -/* 1508 */ MCD_OPC_CheckField, 0, 4, 15, 250, 0, 0, // Skip to: 1765 -/* 1515 */ MCD_OPC_Decode, 136, 5, 23, // Opcode: LDREX -/* 1519 */ MCD_OPC_FilterValue, 3, 241, 0, 0, // Skip to: 1765 -/* 1524 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1527 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1557 -/* 1532 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1548 -/* 1537 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1548 -/* 1544 */ MCD_OPC_Decode, 165, 4, 0, // Opcode: BICrr -/* 1548 */ MCD_OPC_CheckPredicate, 0, 212, 0, 0, // Skip to: 1765 -/* 1553 */ MCD_OPC_Decode, 166, 4, 1, // Opcode: BICrsi -/* 1557 */ MCD_OPC_FilterValue, 1, 203, 0, 0, // Skip to: 1765 -/* 1562 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 1565 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1579 -/* 1570 */ MCD_OPC_CheckPredicate, 0, 190, 0, 0, // Skip to: 1765 -/* 1575 */ MCD_OPC_Decode, 167, 4, 2, // Opcode: BICrsr -/* 1579 */ MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1765 -/* 1584 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1587 */ MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 1651 -/* 1592 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1595 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1623 -/* 1600 */ MCD_OPC_CheckPredicate, 8, 160, 0, 0, // Skip to: 1765 -/* 1605 */ MCD_OPC_CheckField, 12, 4, 15, 153, 0, 0, // Skip to: 1765 -/* 1612 */ MCD_OPC_CheckField, 5, 2, 0, 146, 0, 0, // Skip to: 1765 -/* 1619 */ MCD_OPC_Decode, 202, 6, 22, // Opcode: STLB -/* 1623 */ MCD_OPC_FilterValue, 1, 137, 0, 0, // Skip to: 1765 -/* 1628 */ MCD_OPC_CheckPredicate, 8, 132, 0, 0, // Skip to: 1765 -/* 1633 */ MCD_OPC_CheckField, 5, 2, 0, 125, 0, 0, // Skip to: 1765 -/* 1640 */ MCD_OPC_CheckField, 0, 4, 15, 118, 0, 0, // Skip to: 1765 -/* 1647 */ MCD_OPC_Decode, 223, 4, 23, // Opcode: LDAB -/* 1651 */ MCD_OPC_FilterValue, 14, 52, 0, 0, // Skip to: 1708 -/* 1656 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1659 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1680 -/* 1664 */ MCD_OPC_CheckPredicate, 9, 96, 0, 0, // Skip to: 1765 -/* 1669 */ MCD_OPC_CheckField, 5, 2, 0, 89, 0, 0, // Skip to: 1765 -/* 1676 */ MCD_OPC_Decode, 204, 6, 24, // Opcode: STLEXB -/* 1680 */ MCD_OPC_FilterValue, 1, 80, 0, 0, // Skip to: 1765 -/* 1685 */ MCD_OPC_CheckPredicate, 9, 75, 0, 0, // Skip to: 1765 -/* 1690 */ MCD_OPC_CheckField, 5, 2, 0, 68, 0, 0, // Skip to: 1765 -/* 1697 */ MCD_OPC_CheckField, 0, 4, 15, 61, 0, 0, // Skip to: 1765 -/* 1704 */ MCD_OPC_Decode, 225, 4, 23, // Opcode: LDAEXB -/* 1708 */ MCD_OPC_FilterValue, 15, 52, 0, 0, // Skip to: 1765 -/* 1713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1716 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1737 -/* 1721 */ MCD_OPC_CheckPredicate, 0, 39, 0, 0, // Skip to: 1765 -/* 1726 */ MCD_OPC_CheckField, 5, 2, 0, 32, 0, 0, // Skip to: 1765 -/* 1733 */ MCD_OPC_Decode, 228, 6, 24, // Opcode: STREXB -/* 1737 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 1765 -/* 1742 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 1765 -/* 1747 */ MCD_OPC_CheckField, 5, 2, 0, 11, 0, 0, // Skip to: 1765 -/* 1754 */ MCD_OPC_CheckField, 0, 4, 15, 4, 0, 0, // Skip to: 1765 -/* 1761 */ MCD_OPC_Decode, 137, 5, 23, // Opcode: LDREXB -/* 1765 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 1768 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 1810 -/* 1773 */ MCD_OPC_CheckPredicate, 7, 167, 25, 0, // Skip to: 8345 -/* 1778 */ MCD_OPC_CheckField, 23, 1, 0, 160, 25, 0, // Skip to: 8345 -/* 1785 */ MCD_OPC_CheckField, 20, 1, 0, 153, 25, 0, // Skip to: 8345 -/* 1792 */ MCD_OPC_CheckField, 9, 3, 1, 146, 25, 0, // Skip to: 8345 -/* 1799 */ MCD_OPC_CheckField, 0, 4, 0, 139, 25, 0, // Skip to: 8345 -/* 1806 */ MCD_OPC_Decode, 183, 5, 25, // Opcode: MRSbanked -/* 1810 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 1846 -/* 1815 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1818 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1832 -/* 1823 */ MCD_OPC_CheckPredicate, 0, 117, 25, 0, // Skip to: 8345 -/* 1828 */ MCD_OPC_Decode, 231, 6, 7, // Opcode: STRH -/* 1832 */ MCD_OPC_FilterValue, 1, 108, 25, 0, // Skip to: 8345 -/* 1837 */ MCD_OPC_CheckPredicate, 0, 103, 25, 0, // Skip to: 8345 -/* 1842 */ MCD_OPC_Decode, 140, 5, 7, // Opcode: LDRH -/* 1846 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1882 -/* 1851 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1854 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1868 -/* 1859 */ MCD_OPC_CheckPredicate, 3, 81, 25, 0, // Skip to: 8345 -/* 1864 */ MCD_OPC_Decode, 133, 5, 7, // Opcode: LDRD -/* 1868 */ MCD_OPC_FilterValue, 1, 72, 25, 0, // Skip to: 8345 -/* 1873 */ MCD_OPC_CheckPredicate, 0, 67, 25, 0, // Skip to: 8345 -/* 1878 */ MCD_OPC_Decode, 145, 5, 7, // Opcode: LDRSB -/* 1882 */ MCD_OPC_FilterValue, 15, 58, 25, 0, // Skip to: 8345 -/* 1887 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1890 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1904 -/* 1895 */ MCD_OPC_CheckPredicate, 3, 45, 25, 0, // Skip to: 8345 -/* 1900 */ MCD_OPC_Decode, 224, 6, 7, // Opcode: STRD -/* 1904 */ MCD_OPC_FilterValue, 1, 36, 25, 0, // Skip to: 8345 -/* 1909 */ MCD_OPC_CheckPredicate, 0, 31, 25, 0, // Skip to: 8345 -/* 1914 */ MCD_OPC_Decode, 150, 5, 7, // Opcode: LDRSH -/* 1918 */ MCD_OPC_FilterValue, 1, 22, 25, 0, // Skip to: 8345 -/* 1923 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1926 */ MCD_OPC_FilterValue, 0, 180, 2, 0, // Skip to: 2623 -/* 1931 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 1934 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 2002 -/* 1939 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 1942 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1972 -/* 1947 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1963 -/* 1952 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1963 -/* 1959 */ MCD_OPC_Decode, 204, 4, 0, // Opcode: EORrr -/* 1963 */ MCD_OPC_CheckPredicate, 0, 233, 24, 0, // Skip to: 8345 -/* 1968 */ MCD_OPC_Decode, 205, 4, 1, // Opcode: EORrsi -/* 1972 */ MCD_OPC_FilterValue, 1, 224, 24, 0, // Skip to: 8345 -/* 1977 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1993 -/* 1982 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1993 -/* 1989 */ MCD_OPC_Decode, 228, 5, 0, // Opcode: RSBrr -/* 1993 */ MCD_OPC_CheckPredicate, 0, 203, 24, 0, // Skip to: 8345 -/* 1998 */ MCD_OPC_Decode, 229, 5, 1, // Opcode: RSBrsi -/* 2002 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 2070 -/* 2007 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2010 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2040 -/* 2015 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2031 -/* 2020 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 2031 -/* 2027 */ MCD_OPC_Decode, 146, 4, 0, // Opcode: ADCrr -/* 2031 */ MCD_OPC_CheckPredicate, 0, 165, 24, 0, // Skip to: 8345 -/* 2036 */ MCD_OPC_Decode, 147, 4, 1, // Opcode: ADCrsi -/* 2040 */ MCD_OPC_FilterValue, 1, 156, 24, 0, // Skip to: 8345 -/* 2045 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2061 -/* 2050 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 2061 -/* 2057 */ MCD_OPC_Decode, 232, 5, 0, // Opcode: RSCrr -/* 2061 */ MCD_OPC_CheckPredicate, 0, 135, 24, 0, // Skip to: 8345 -/* 2066 */ MCD_OPC_Decode, 233, 5, 1, // Opcode: RSCrsi -/* 2070 */ MCD_OPC_FilterValue, 2, 166, 1, 0, // Skip to: 2497 -/* 2075 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 2078 */ MCD_OPC_FilterValue, 0, 70, 1, 0, // Skip to: 2409 -/* 2083 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... -/* 2086 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 2129 -/* 2091 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... -/* 2094 */ MCD_OPC_FilterValue, 120, 16, 0, 0, // Skip to: 2115 -/* 2099 */ MCD_OPC_CheckPredicate, 0, 97, 24, 0, // Skip to: 8345 -/* 2104 */ MCD_OPC_CheckField, 8, 1, 0, 90, 24, 0, // Skip to: 8345 -/* 2111 */ MCD_OPC_Decode, 185, 5, 26, // Opcode: MSR -/* 2115 */ MCD_OPC_FilterValue, 121, 81, 24, 0, // Skip to: 8345 -/* 2120 */ MCD_OPC_CheckPredicate, 7, 76, 24, 0, // Skip to: 8345 -/* 2125 */ MCD_OPC_Decode, 186, 5, 27, // Opcode: MSRbanked -/* 2129 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2158 -/* 2134 */ MCD_OPC_CheckPredicate, 0, 62, 24, 0, // Skip to: 8345 -/* 2139 */ MCD_OPC_CheckField, 22, 1, 0, 55, 24, 0, // Skip to: 8345 -/* 2146 */ MCD_OPC_CheckField, 8, 12, 255, 31, 47, 24, 0, // Skip to: 8345 -/* 2154 */ MCD_OPC_Decode, 175, 4, 28, // Opcode: BXJ -/* 2158 */ MCD_OPC_FilterValue, 2, 67, 0, 0, // Skip to: 2230 -/* 2163 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 2166 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2198 -/* 2171 */ MCD_OPC_CheckPredicate, 2, 25, 24, 0, // Skip to: 8345 -/* 2176 */ MCD_OPC_CheckField, 28, 4, 14, 18, 24, 0, // Skip to: 8345 -/* 2183 */ MCD_OPC_CheckField, 22, 1, 0, 11, 24, 0, // Skip to: 8345 -/* 2190 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, -/* 2194 */ MCD_OPC_Decode, 198, 4, 8, // Opcode: CRC32H -/* 2198 */ MCD_OPC_FilterValue, 1, 254, 23, 0, // Skip to: 8345 -/* 2203 */ MCD_OPC_CheckPredicate, 2, 249, 23, 0, // Skip to: 8345 -/* 2208 */ MCD_OPC_CheckField, 28, 4, 14, 242, 23, 0, // Skip to: 8345 -/* 2215 */ MCD_OPC_CheckField, 22, 1, 0, 235, 23, 0, // Skip to: 8345 -/* 2222 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, -/* 2226 */ MCD_OPC_Decode, 196, 4, 8, // Opcode: CRC32CH -/* 2230 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 2265 -/* 2235 */ MCD_OPC_CheckPredicate, 7, 217, 23, 0, // Skip to: 8345 -/* 2240 */ MCD_OPC_CheckField, 22, 1, 1, 210, 23, 0, // Skip to: 8345 -/* 2247 */ MCD_OPC_CheckField, 8, 12, 0, 203, 23, 0, // Skip to: 8345 -/* 2254 */ MCD_OPC_CheckField, 0, 4, 14, 196, 23, 0, // Skip to: 8345 -/* 2261 */ MCD_OPC_Decode, 207, 4, 29, // Opcode: ERET -/* 2265 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 2301 -/* 2270 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2273 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2287 -/* 2278 */ MCD_OPC_CheckPredicate, 3, 174, 23, 0, // Skip to: 8345 -/* 2283 */ MCD_OPC_Decode, 149, 6, 13, // Opcode: SMLAWB -/* 2287 */ MCD_OPC_FilterValue, 1, 165, 23, 0, // Skip to: 8345 -/* 2292 */ MCD_OPC_CheckPredicate, 3, 160, 23, 0, // Skip to: 8345 -/* 2297 */ MCD_OPC_Decode, 163, 6, 30, // Opcode: SMULBB -/* 2301 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 2337 -/* 2306 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2309 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2323 -/* 2314 */ MCD_OPC_CheckPredicate, 3, 138, 23, 0, // Skip to: 8345 -/* 2319 */ MCD_OPC_Decode, 168, 6, 30, // Opcode: SMULWB -/* 2323 */ MCD_OPC_FilterValue, 1, 129, 23, 0, // Skip to: 8345 -/* 2328 */ MCD_OPC_CheckPredicate, 3, 124, 23, 0, // Skip to: 8345 -/* 2333 */ MCD_OPC_Decode, 166, 6, 30, // Opcode: SMULTB -/* 2337 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 2373 -/* 2342 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2345 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2359 -/* 2350 */ MCD_OPC_CheckPredicate, 3, 102, 23, 0, // Skip to: 8345 -/* 2355 */ MCD_OPC_Decode, 150, 6, 13, // Opcode: SMLAWT -/* 2359 */ MCD_OPC_FilterValue, 1, 93, 23, 0, // Skip to: 8345 -/* 2364 */ MCD_OPC_CheckPredicate, 3, 88, 23, 0, // Skip to: 8345 -/* 2369 */ MCD_OPC_Decode, 164, 6, 30, // Opcode: SMULBT -/* 2373 */ MCD_OPC_FilterValue, 7, 79, 23, 0, // Skip to: 8345 -/* 2378 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2381 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2395 -/* 2386 */ MCD_OPC_CheckPredicate, 3, 66, 23, 0, // Skip to: 8345 -/* 2391 */ MCD_OPC_Decode, 169, 6, 30, // Opcode: SMULWT -/* 2395 */ MCD_OPC_FilterValue, 1, 57, 23, 0, // Skip to: 8345 -/* 2400 */ MCD_OPC_CheckPredicate, 3, 52, 23, 0, // Skip to: 8345 -/* 2405 */ MCD_OPC_Decode, 167, 6, 30, // Opcode: SMULTT -/* 2409 */ MCD_OPC_FilterValue, 1, 43, 23, 0, // Skip to: 8345 -/* 2414 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2417 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2457 -/* 2422 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2443 -/* 2427 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2443 -/* 2434 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 2439 */ MCD_OPC_Decode, 130, 7, 20, // Opcode: TEQrr -/* 2443 */ MCD_OPC_CheckPredicate, 0, 9, 23, 0, // Skip to: 8345 -/* 2448 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 2453 */ MCD_OPC_Decode, 131, 7, 17, // Opcode: TEQrsi -/* 2457 */ MCD_OPC_FilterValue, 1, 251, 22, 0, // Skip to: 8345 -/* 2462 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2483 -/* 2467 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2483 -/* 2474 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 2479 */ MCD_OPC_Decode, 184, 4, 20, // Opcode: CMNzrr -/* 2483 */ MCD_OPC_CheckPredicate, 0, 225, 22, 0, // Skip to: 8345 -/* 2488 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 2493 */ MCD_OPC_Decode, 185, 4, 17, // Opcode: CMNzrsi -/* 2497 */ MCD_OPC_FilterValue, 3, 211, 22, 0, // Skip to: 8345 -/* 2502 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2505 */ MCD_OPC_FilterValue, 0, 73, 0, 0, // Skip to: 2583 -/* 2510 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 2534 -/* 2515 */ MCD_OPC_CheckField, 5, 16, 128, 15, 11, 0, 0, // Skip to: 2534 -/* 2523 */ MCD_OPC_CheckField, 0, 4, 14, 4, 0, 0, // Skip to: 2534 -/* 2530 */ MCD_OPC_Decode, 170, 5, 29, // Opcode: MOVPCLR -/* 2534 */ MCD_OPC_ExtractField, 5, 7, // Inst{11-5} ... -/* 2537 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2567 -/* 2542 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2558 -/* 2547 */ MCD_OPC_CheckField, 16, 4, 0, 4, 0, 0, // Skip to: 2558 -/* 2554 */ MCD_OPC_Decode, 174, 5, 31, // Opcode: MOVr -/* 2558 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 2567 -/* 2563 */ MCD_OPC_Decode, 175, 5, 32, // Opcode: MOVr_TC -/* 2567 */ MCD_OPC_CheckPredicate, 0, 141, 22, 0, // Skip to: 8345 -/* 2572 */ MCD_OPC_CheckField, 16, 4, 0, 134, 22, 0, // Skip to: 8345 -/* 2579 */ MCD_OPC_Decode, 176, 5, 33, // Opcode: MOVsi -/* 2583 */ MCD_OPC_FilterValue, 1, 125, 22, 0, // Skip to: 8345 -/* 2588 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2609 -/* 2593 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2609 -/* 2600 */ MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0, -/* 2605 */ MCD_OPC_Decode, 190, 5, 31, // Opcode: MVNr -/* 2609 */ MCD_OPC_CheckPredicate, 0, 99, 22, 0, // Skip to: 8345 -/* 2614 */ MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0, -/* 2619 */ MCD_OPC_Decode, 191, 5, 33, // Opcode: MVNsi -/* 2623 */ MCD_OPC_FilterValue, 1, 85, 22, 0, // Skip to: 8345 -/* 2628 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 2631 */ MCD_OPC_FilterValue, 0, 113, 1, 0, // Skip to: 3005 -/* 2636 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... -/* 2639 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2653 -/* 2644 */ MCD_OPC_CheckPredicate, 0, 64, 22, 0, // Skip to: 8345 -/* 2649 */ MCD_OPC_Decode, 206, 4, 2, // Opcode: EORrsr -/* 2653 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2667 -/* 2658 */ MCD_OPC_CheckPredicate, 0, 50, 22, 0, // Skip to: 8345 -/* 2663 */ MCD_OPC_Decode, 230, 5, 2, // Opcode: RSBrsr -/* 2667 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2681 -/* 2672 */ MCD_OPC_CheckPredicate, 0, 36, 22, 0, // Skip to: 8345 -/* 2677 */ MCD_OPC_Decode, 148, 4, 3, // Opcode: ADCrsr -/* 2681 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2695 -/* 2686 */ MCD_OPC_CheckPredicate, 0, 22, 22, 0, // Skip to: 8345 -/* 2691 */ MCD_OPC_Decode, 234, 5, 2, // Opcode: RSCrsr -/* 2695 */ MCD_OPC_FilterValue, 4, 163, 0, 0, // Skip to: 2863 -/* 2700 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 2703 */ MCD_OPC_FilterValue, 0, 136, 0, 0, // Skip to: 2844 -/* 2708 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 2711 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 2766 -/* 2716 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... -/* 2719 */ MCD_OPC_FilterValue, 255, 31, 244, 21, 0, // Skip to: 8345 -/* 2725 */ MCD_OPC_CheckPredicate, 10, 11, 0, 0, // Skip to: 2741 -/* 2730 */ MCD_OPC_CheckField, 0, 4, 14, 4, 0, 0, // Skip to: 2741 -/* 2737 */ MCD_OPC_Decode, 176, 4, 29, // Opcode: BX_RET -/* 2741 */ MCD_OPC_CheckPredicate, 10, 11, 0, 0, // Skip to: 2757 -/* 2746 */ MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 2757 -/* 2753 */ MCD_OPC_Decode, 174, 4, 34, // Opcode: BX -/* 2757 */ MCD_OPC_CheckPredicate, 10, 207, 21, 0, // Skip to: 8345 -/* 2762 */ MCD_OPC_Decode, 177, 4, 28, // Opcode: BX_pred -/* 2766 */ MCD_OPC_FilterValue, 1, 34, 0, 0, // Skip to: 2805 -/* 2771 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... -/* 2774 */ MCD_OPC_FilterValue, 255, 31, 189, 21, 0, // Skip to: 8345 -/* 2780 */ MCD_OPC_CheckPredicate, 11, 11, 0, 0, // Skip to: 2796 -/* 2785 */ MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 2796 -/* 2792 */ MCD_OPC_Decode, 170, 4, 34, // Opcode: BLX -/* 2796 */ MCD_OPC_CheckPredicate, 11, 168, 21, 0, // Skip to: 8345 -/* 2801 */ MCD_OPC_Decode, 171, 4, 28, // Opcode: BLX_pred -/* 2805 */ MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 2823 -/* 2810 */ MCD_OPC_CheckPredicate, 0, 154, 21, 0, // Skip to: 8345 -/* 2815 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, -/* 2819 */ MCD_OPC_Decode, 212, 5, 21, // Opcode: QSUB -/* 2823 */ MCD_OPC_FilterValue, 3, 141, 21, 0, // Skip to: 8345 -/* 2828 */ MCD_OPC_CheckPredicate, 0, 136, 21, 0, // Skip to: 8345 -/* 2833 */ MCD_OPC_CheckField, 28, 4, 14, 129, 21, 0, // Skip to: 8345 -/* 2840 */ MCD_OPC_Decode, 168, 4, 15, // Opcode: BKPT -/* 2844 */ MCD_OPC_FilterValue, 1, 120, 21, 0, // Skip to: 8345 -/* 2849 */ MCD_OPC_CheckPredicate, 0, 115, 21, 0, // Skip to: 8345 -/* 2854 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 2859 */ MCD_OPC_Decode, 132, 7, 18, // Opcode: TEQrsr -/* 2863 */ MCD_OPC_FilterValue, 5, 97, 0, 0, // Skip to: 2965 -/* 2868 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 2871 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 2946 -/* 2876 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 2879 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 2907 -/* 2884 */ MCD_OPC_CheckPredicate, 11, 80, 21, 0, // Skip to: 8345 -/* 2889 */ MCD_OPC_CheckField, 16, 4, 15, 73, 21, 0, // Skip to: 8345 -/* 2896 */ MCD_OPC_CheckField, 8, 4, 15, 66, 21, 0, // Skip to: 8345 -/* 2903 */ MCD_OPC_Decode, 182, 4, 35, // Opcode: CLZ -/* 2907 */ MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 2925 -/* 2912 */ MCD_OPC_CheckPredicate, 0, 52, 21, 0, // Skip to: 8345 -/* 2917 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, -/* 2921 */ MCD_OPC_Decode, 210, 5, 21, // Opcode: QDSUB -/* 2925 */ MCD_OPC_FilterValue, 3, 39, 21, 0, // Skip to: 8345 -/* 2930 */ MCD_OPC_CheckPredicate, 12, 34, 21, 0, // Skip to: 8345 -/* 2935 */ MCD_OPC_CheckField, 8, 12, 0, 27, 21, 0, // Skip to: 8345 -/* 2942 */ MCD_OPC_Decode, 135, 6, 36, // Opcode: SMC -/* 2946 */ MCD_OPC_FilterValue, 1, 18, 21, 0, // Skip to: 8345 -/* 2951 */ MCD_OPC_CheckPredicate, 0, 13, 21, 0, // Skip to: 8345 -/* 2956 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 2961 */ MCD_OPC_Decode, 186, 4, 18, // Opcode: CMNzrsr -/* 2965 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2986 -/* 2970 */ MCD_OPC_CheckPredicate, 0, 250, 20, 0, // Skip to: 8345 -/* 2975 */ MCD_OPC_CheckField, 16, 4, 0, 243, 20, 0, // Skip to: 8345 -/* 2982 */ MCD_OPC_Decode, 177, 5, 37, // Opcode: MOVsr -/* 2986 */ MCD_OPC_FilterValue, 7, 234, 20, 0, // Skip to: 8345 -/* 2991 */ MCD_OPC_CheckPredicate, 0, 229, 20, 0, // Skip to: 8345 -/* 2996 */ MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0, -/* 3001 */ MCD_OPC_Decode, 192, 5, 37, // Opcode: MVNsr -/* 3005 */ MCD_OPC_FilterValue, 1, 215, 20, 0, // Skip to: 8345 -/* 3010 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 3013 */ MCD_OPC_FilterValue, 0, 48, 1, 0, // Skip to: 3322 -/* 3018 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... -/* 3021 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3035 -/* 3026 */ MCD_OPC_CheckPredicate, 1, 194, 20, 0, // Skip to: 8345 -/* 3031 */ MCD_OPC_Decode, 168, 5, 38, // Opcode: MLA -/* 3035 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3056 -/* 3040 */ MCD_OPC_CheckPredicate, 13, 180, 20, 0, // Skip to: 8345 -/* 3045 */ MCD_OPC_CheckField, 20, 1, 0, 173, 20, 0, // Skip to: 8345 -/* 3052 */ MCD_OPC_Decode, 169, 5, 39, // Opcode: MLS -/* 3056 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3070 -/* 3061 */ MCD_OPC_CheckPredicate, 1, 159, 20, 0, // Skip to: 8345 -/* 3066 */ MCD_OPC_Decode, 153, 7, 40, // Opcode: UMLAL -/* 3070 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3084 -/* 3075 */ MCD_OPC_CheckPredicate, 1, 145, 20, 0, // Skip to: 8345 -/* 3080 */ MCD_OPC_Decode, 140, 6, 40, // Opcode: SMLAL -/* 3084 */ MCD_OPC_FilterValue, 6, 89, 0, 0, // Skip to: 3178 -/* 3089 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 3092 */ MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 3135 -/* 3097 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3100 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3114 -/* 3105 */ MCD_OPC_CheckPredicate, 9, 115, 20, 0, // Skip to: 8345 -/* 3110 */ MCD_OPC_Decode, 205, 6, 41, // Opcode: STLEXD -/* 3114 */ MCD_OPC_FilterValue, 1, 106, 20, 0, // Skip to: 8345 -/* 3119 */ MCD_OPC_CheckPredicate, 9, 101, 20, 0, // Skip to: 8345 -/* 3124 */ MCD_OPC_CheckField, 0, 4, 15, 94, 20, 0, // Skip to: 8345 -/* 3131 */ MCD_OPC_Decode, 226, 4, 42, // Opcode: LDAEXD -/* 3135 */ MCD_OPC_FilterValue, 15, 85, 20, 0, // Skip to: 8345 -/* 3140 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3143 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3157 -/* 3148 */ MCD_OPC_CheckPredicate, 0, 72, 20, 0, // Skip to: 8345 -/* 3153 */ MCD_OPC_Decode, 229, 6, 41, // Opcode: STREXD -/* 3157 */ MCD_OPC_FilterValue, 1, 63, 20, 0, // Skip to: 8345 -/* 3162 */ MCD_OPC_CheckPredicate, 0, 58, 20, 0, // Skip to: 8345 -/* 3167 */ MCD_OPC_CheckField, 0, 4, 15, 51, 20, 0, // Skip to: 8345 -/* 3174 */ MCD_OPC_Decode, 138, 5, 42, // Opcode: LDREXD -/* 3178 */ MCD_OPC_FilterValue, 7, 42, 20, 0, // Skip to: 8345 -/* 3183 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 3186 */ MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 3236 -/* 3191 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3194 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3215 -/* 3199 */ MCD_OPC_CheckPredicate, 8, 21, 20, 0, // Skip to: 8345 -/* 3204 */ MCD_OPC_CheckField, 12, 4, 15, 14, 20, 0, // Skip to: 8345 -/* 3211 */ MCD_OPC_Decode, 207, 6, 22, // Opcode: STLH -/* 3215 */ MCD_OPC_FilterValue, 1, 5, 20, 0, // Skip to: 8345 -/* 3220 */ MCD_OPC_CheckPredicate, 8, 0, 20, 0, // Skip to: 8345 -/* 3225 */ MCD_OPC_CheckField, 0, 4, 15, 249, 19, 0, // Skip to: 8345 -/* 3232 */ MCD_OPC_Decode, 228, 4, 23, // Opcode: LDAH -/* 3236 */ MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 3279 -/* 3241 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3244 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3258 -/* 3249 */ MCD_OPC_CheckPredicate, 9, 227, 19, 0, // Skip to: 8345 -/* 3254 */ MCD_OPC_Decode, 206, 6, 24, // Opcode: STLEXH -/* 3258 */ MCD_OPC_FilterValue, 1, 218, 19, 0, // Skip to: 8345 -/* 3263 */ MCD_OPC_CheckPredicate, 9, 213, 19, 0, // Skip to: 8345 -/* 3268 */ MCD_OPC_CheckField, 0, 4, 15, 206, 19, 0, // Skip to: 8345 -/* 3275 */ MCD_OPC_Decode, 227, 4, 23, // Opcode: LDAEXH -/* 3279 */ MCD_OPC_FilterValue, 15, 197, 19, 0, // Skip to: 8345 -/* 3284 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3287 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3301 -/* 3292 */ MCD_OPC_CheckPredicate, 0, 184, 19, 0, // Skip to: 8345 -/* 3297 */ MCD_OPC_Decode, 230, 6, 24, // Opcode: STREXH -/* 3301 */ MCD_OPC_FilterValue, 1, 175, 19, 0, // Skip to: 8345 -/* 3306 */ MCD_OPC_CheckPredicate, 0, 170, 19, 0, // Skip to: 8345 -/* 3311 */ MCD_OPC_CheckField, 0, 4, 15, 163, 19, 0, // Skip to: 8345 -/* 3318 */ MCD_OPC_Decode, 139, 5, 23, // Opcode: LDREXH -/* 3322 */ MCD_OPC_FilterValue, 1, 130, 0, 0, // Skip to: 3457 -/* 3327 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3330 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 3395 -/* 3335 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 3338 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 3381 -/* 3343 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3346 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3367 -/* 3351 */ MCD_OPC_CheckPredicate, 0, 125, 19, 0, // Skip to: 8345 -/* 3356 */ MCD_OPC_CheckField, 8, 4, 0, 118, 19, 0, // Skip to: 8345 -/* 3363 */ MCD_OPC_Decode, 233, 6, 43, // Opcode: STRHTr -/* 3367 */ MCD_OPC_FilterValue, 1, 109, 19, 0, // Skip to: 8345 -/* 3372 */ MCD_OPC_CheckPredicate, 0, 104, 19, 0, // Skip to: 8345 -/* 3377 */ MCD_OPC_Decode, 232, 6, 44, // Opcode: STRHTi -/* 3381 */ MCD_OPC_FilterValue, 1, 95, 19, 0, // Skip to: 8345 -/* 3386 */ MCD_OPC_CheckPredicate, 0, 90, 19, 0, // Skip to: 8345 -/* 3391 */ MCD_OPC_Decode, 235, 6, 7, // Opcode: STRH_PRE -/* 3395 */ MCD_OPC_FilterValue, 1, 81, 19, 0, // Skip to: 8345 -/* 3400 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 3403 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3443 -/* 3408 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3411 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3429 -/* 3416 */ MCD_OPC_CheckPredicate, 0, 60, 19, 0, // Skip to: 8345 -/* 3421 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, -/* 3425 */ MCD_OPC_Decode, 142, 5, 45, // Opcode: LDRHTr -/* 3429 */ MCD_OPC_FilterValue, 1, 47, 19, 0, // Skip to: 8345 -/* 3434 */ MCD_OPC_CheckPredicate, 0, 42, 19, 0, // Skip to: 8345 -/* 3439 */ MCD_OPC_Decode, 141, 5, 46, // Opcode: LDRHTi -/* 3443 */ MCD_OPC_FilterValue, 1, 33, 19, 0, // Skip to: 8345 -/* 3448 */ MCD_OPC_CheckPredicate, 0, 28, 19, 0, // Skip to: 8345 -/* 3453 */ MCD_OPC_Decode, 144, 5, 7, // Opcode: LDRH_PRE -/* 3457 */ MCD_OPC_FilterValue, 2, 86, 0, 0, // Skip to: 3548 -/* 3462 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3465 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3486 -/* 3470 */ MCD_OPC_CheckPredicate, 0, 6, 19, 0, // Skip to: 8345 -/* 3475 */ MCD_OPC_CheckField, 24, 1, 1, 255, 18, 0, // Skip to: 8345 -/* 3482 */ MCD_OPC_Decode, 135, 5, 7, // Opcode: LDRD_PRE -/* 3486 */ MCD_OPC_FilterValue, 1, 246, 18, 0, // Skip to: 8345 -/* 3491 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 3494 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3534 -/* 3499 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3502 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3520 -/* 3507 */ MCD_OPC_CheckPredicate, 0, 225, 18, 0, // Skip to: 8345 -/* 3512 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, -/* 3516 */ MCD_OPC_Decode, 147, 5, 45, // Opcode: LDRSBTr -/* 3520 */ MCD_OPC_FilterValue, 1, 212, 18, 0, // Skip to: 8345 -/* 3525 */ MCD_OPC_CheckPredicate, 0, 207, 18, 0, // Skip to: 8345 -/* 3530 */ MCD_OPC_Decode, 146, 5, 46, // Opcode: LDRSBTi -/* 3534 */ MCD_OPC_FilterValue, 1, 198, 18, 0, // Skip to: 8345 -/* 3539 */ MCD_OPC_CheckPredicate, 0, 193, 18, 0, // Skip to: 8345 -/* 3544 */ MCD_OPC_Decode, 149, 5, 7, // Opcode: LDRSB_PRE -/* 3548 */ MCD_OPC_FilterValue, 3, 184, 18, 0, // Skip to: 8345 -/* 3553 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3556 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3577 -/* 3561 */ MCD_OPC_CheckPredicate, 0, 171, 18, 0, // Skip to: 8345 -/* 3566 */ MCD_OPC_CheckField, 24, 1, 1, 164, 18, 0, // Skip to: 8345 -/* 3573 */ MCD_OPC_Decode, 226, 6, 7, // Opcode: STRD_PRE -/* 3577 */ MCD_OPC_FilterValue, 1, 155, 18, 0, // Skip to: 8345 -/* 3582 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 3585 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3625 -/* 3590 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3593 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3611 -/* 3598 */ MCD_OPC_CheckPredicate, 0, 134, 18, 0, // Skip to: 8345 -/* 3603 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, -/* 3607 */ MCD_OPC_Decode, 152, 5, 45, // Opcode: LDRSHTr -/* 3611 */ MCD_OPC_FilterValue, 1, 121, 18, 0, // Skip to: 8345 -/* 3616 */ MCD_OPC_CheckPredicate, 0, 116, 18, 0, // Skip to: 8345 -/* 3621 */ MCD_OPC_Decode, 151, 5, 46, // Opcode: LDRSHTi -/* 3625 */ MCD_OPC_FilterValue, 1, 107, 18, 0, // Skip to: 8345 -/* 3630 */ MCD_OPC_CheckPredicate, 0, 102, 18, 0, // Skip to: 8345 -/* 3635 */ MCD_OPC_Decode, 154, 5, 7, // Opcode: LDRSH_PRE -/* 3639 */ MCD_OPC_FilterValue, 1, 0, 2, 0, // Skip to: 4156 -/* 3644 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 3647 */ MCD_OPC_FilterValue, 0, 201, 0, 0, // Skip to: 3853 -/* 3652 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 3655 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 3735 -/* 3660 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 3663 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3677 -/* 3668 */ MCD_OPC_CheckPredicate, 0, 46, 0, 0, // Skip to: 3719 -/* 3673 */ MCD_OPC_Decode, 158, 4, 47, // Opcode: ANDri -/* 3677 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3691 -/* 3682 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 3719 -/* 3687 */ MCD_OPC_Decode, 244, 6, 47, // Opcode: SUBri -/* 3691 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3705 -/* 3696 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 3719 -/* 3701 */ MCD_OPC_Decode, 149, 4, 47, // Opcode: ADDri -/* 3705 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3719 -/* 3710 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 3719 -/* 3715 */ MCD_OPC_Decode, 238, 5, 47, // Opcode: SBCri -/* 3719 */ MCD_OPC_CheckPredicate, 0, 13, 18, 0, // Skip to: 8345 -/* 3724 */ MCD_OPC_CheckField, 16, 5, 15, 6, 18, 0, // Skip to: 8345 -/* 3731 */ MCD_OPC_Decode, 153, 4, 48, // Opcode: ADR -/* 3735 */ MCD_OPC_FilterValue, 1, 253, 17, 0, // Skip to: 8345 -/* 3740 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 3743 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 3784 -/* 3748 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3751 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3765 -/* 3756 */ MCD_OPC_CheckPredicate, 13, 232, 17, 0, // Skip to: 8345 -/* 3761 */ MCD_OPC_Decode, 173, 5, 49, // Opcode: MOVi16 -/* 3765 */ MCD_OPC_FilterValue, 1, 223, 17, 0, // Skip to: 8345 -/* 3770 */ MCD_OPC_CheckPredicate, 0, 218, 17, 0, // Skip to: 8345 -/* 3775 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 3780 */ MCD_OPC_Decode, 136, 7, 50, // Opcode: TSTri -/* 3784 */ MCD_OPC_FilterValue, 1, 36, 0, 0, // Skip to: 3825 -/* 3789 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3792 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3806 -/* 3797 */ MCD_OPC_CheckPredicate, 13, 191, 17, 0, // Skip to: 8345 -/* 3802 */ MCD_OPC_Decode, 171, 5, 49, // Opcode: MOVTi16 -/* 3806 */ MCD_OPC_FilterValue, 1, 182, 17, 0, // Skip to: 8345 -/* 3811 */ MCD_OPC_CheckPredicate, 0, 177, 17, 0, // Skip to: 8345 -/* 3816 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 3821 */ MCD_OPC_Decode, 187, 4, 50, // Opcode: CMPri -/* 3825 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3839 -/* 3830 */ MCD_OPC_CheckPredicate, 0, 158, 17, 0, // Skip to: 8345 -/* 3835 */ MCD_OPC_Decode, 193, 5, 47, // Opcode: ORRri -/* 3839 */ MCD_OPC_FilterValue, 3, 149, 17, 0, // Skip to: 8345 -/* 3844 */ MCD_OPC_CheckPredicate, 0, 144, 17, 0, // Skip to: 8345 -/* 3849 */ MCD_OPC_Decode, 164, 4, 47, // Opcode: BICri -/* 3853 */ MCD_OPC_FilterValue, 1, 135, 17, 0, // Skip to: 8345 -/* 3858 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 3861 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3897 -/* 3866 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3869 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3883 -/* 3874 */ MCD_OPC_CheckPredicate, 0, 114, 17, 0, // Skip to: 8345 -/* 3879 */ MCD_OPC_Decode, 203, 4, 47, // Opcode: EORri -/* 3883 */ MCD_OPC_FilterValue, 1, 105, 17, 0, // Skip to: 8345 -/* 3888 */ MCD_OPC_CheckPredicate, 0, 100, 17, 0, // Skip to: 8345 -/* 3893 */ MCD_OPC_Decode, 227, 5, 47, // Opcode: RSBri -/* 3897 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 3933 -/* 3902 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 3905 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3919 -/* 3910 */ MCD_OPC_CheckPredicate, 0, 78, 17, 0, // Skip to: 8345 -/* 3915 */ MCD_OPC_Decode, 145, 4, 47, // Opcode: ADCri -/* 3919 */ MCD_OPC_FilterValue, 1, 69, 17, 0, // Skip to: 8345 -/* 3924 */ MCD_OPC_CheckPredicate, 0, 64, 17, 0, // Skip to: 8345 -/* 3929 */ MCD_OPC_Decode, 231, 5, 47, // Opcode: RSCri -/* 3933 */ MCD_OPC_FilterValue, 2, 168, 0, 0, // Skip to: 4106 -/* 3938 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3941 */ MCD_OPC_FilterValue, 0, 114, 0, 0, // Skip to: 4060 -/* 3946 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3949 */ MCD_OPC_FilterValue, 15, 39, 17, 0, // Skip to: 8345 -/* 3954 */ MCD_OPC_CheckPredicate, 14, 32, 0, 0, // Skip to: 3991 -/* 3959 */ MCD_OPC_CheckField, 28, 4, 14, 25, 0, 0, // Skip to: 3991 -/* 3966 */ MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 3991 -/* 3973 */ MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 3991 -/* 3980 */ MCD_OPC_CheckField, 0, 12, 18, 4, 0, 0, // Skip to: 3991 -/* 3987 */ MCD_OPC_Decode, 135, 7, 51, // Opcode: TSB -/* 3991 */ MCD_OPC_CheckPredicate, 15, 25, 0, 0, // Skip to: 4021 -/* 3996 */ MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 4021 -/* 4003 */ MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 4021 -/* 4010 */ MCD_OPC_CheckField, 4, 8, 15, 4, 0, 0, // Skip to: 4021 -/* 4017 */ MCD_OPC_Decode, 200, 4, 36, // Opcode: DBG -/* 4021 */ MCD_OPC_CheckPredicate, 1, 25, 0, 0, // Skip to: 4051 -/* 4026 */ MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 4051 -/* 4033 */ MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 4051 -/* 4040 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4051 -/* 4047 */ MCD_OPC_Decode, 218, 4, 52, // Opcode: HINT -/* 4051 */ MCD_OPC_CheckPredicate, 0, 193, 16, 0, // Skip to: 8345 -/* 4056 */ MCD_OPC_Decode, 187, 5, 53, // Opcode: MSRi -/* 4060 */ MCD_OPC_FilterValue, 1, 184, 16, 0, // Skip to: 8345 -/* 4065 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4068 */ MCD_OPC_FilterValue, 0, 14, 0, 0, // Skip to: 4087 -/* 4073 */ MCD_OPC_CheckPredicate, 0, 171, 16, 0, // Skip to: 8345 -/* 4078 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 4083 */ MCD_OPC_Decode, 129, 7, 50, // Opcode: TEQri -/* 4087 */ MCD_OPC_FilterValue, 1, 157, 16, 0, // Skip to: 8345 -/* 4092 */ MCD_OPC_CheckPredicate, 0, 152, 16, 0, // Skip to: 8345 -/* 4097 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, -/* 4102 */ MCD_OPC_Decode, 183, 4, 50, // Opcode: CMNri -/* 4106 */ MCD_OPC_FilterValue, 3, 138, 16, 0, // Skip to: 8345 -/* 4111 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 4114 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4135 -/* 4119 */ MCD_OPC_CheckPredicate, 0, 125, 16, 0, // Skip to: 8345 -/* 4124 */ MCD_OPC_CheckField, 16, 4, 0, 118, 16, 0, // Skip to: 8345 -/* 4131 */ MCD_OPC_Decode, 172, 5, 54, // Opcode: MOVi -/* 4135 */ MCD_OPC_FilterValue, 1, 109, 16, 0, // Skip to: 8345 -/* 4140 */ MCD_OPC_CheckPredicate, 0, 104, 16, 0, // Skip to: 8345 -/* 4145 */ MCD_OPC_CheckField, 16, 4, 0, 97, 16, 0, // Skip to: 8345 -/* 4152 */ MCD_OPC_Decode, 189, 5, 54, // Opcode: MVNi -/* 4156 */ MCD_OPC_FilterValue, 2, 229, 1, 0, // Skip to: 4646 -/* 4161 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... -/* 4164 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4200 -/* 4169 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4172 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4186 -/* 4177 */ MCD_OPC_CheckPredicate, 0, 67, 16, 0, // Skip to: 8345 -/* 4182 */ MCD_OPC_Decode, 238, 6, 55, // Opcode: STR_POST_IMM -/* 4186 */ MCD_OPC_FilterValue, 1, 58, 16, 0, // Skip to: 8345 -/* 4191 */ MCD_OPC_CheckPredicate, 0, 53, 16, 0, // Skip to: 8345 -/* 4196 */ MCD_OPC_Decode, 242, 6, 56, // Opcode: STRi12 -/* 4200 */ MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 4259 -/* 4205 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4208 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4222 -/* 4213 */ MCD_OPC_CheckPredicate, 0, 31, 16, 0, // Skip to: 8345 -/* 4218 */ MCD_OPC_Decode, 157, 5, 55, // Opcode: LDR_POST_IMM -/* 4222 */ MCD_OPC_FilterValue, 1, 22, 16, 0, // Skip to: 8345 -/* 4227 */ MCD_OPC_CheckPredicate, 16, 18, 0, 0, // Skip to: 4250 -/* 4232 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4250 -/* 4239 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4250 -/* 4246 */ MCD_OPC_Decode, 199, 5, 57, // Opcode: PLDWi12 -/* 4250 */ MCD_OPC_CheckPredicate, 0, 250, 15, 0, // Skip to: 8345 -/* 4255 */ MCD_OPC_Decode, 162, 5, 56, // Opcode: LDRi12 -/* 4259 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 4295 -/* 4264 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4281 -/* 4272 */ MCD_OPC_CheckPredicate, 0, 228, 15, 0, // Skip to: 8345 -/* 4277 */ MCD_OPC_Decode, 236, 6, 55, // Opcode: STRT_POST_IMM -/* 4281 */ MCD_OPC_FilterValue, 1, 219, 15, 0, // Skip to: 8345 -/* 4286 */ MCD_OPC_CheckPredicate, 0, 214, 15, 0, // Skip to: 8345 -/* 4291 */ MCD_OPC_Decode, 240, 6, 58, // Opcode: STR_PRE_IMM -/* 4295 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 4331 -/* 4300 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4303 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4317 -/* 4308 */ MCD_OPC_CheckPredicate, 0, 192, 15, 0, // Skip to: 8345 -/* 4313 */ MCD_OPC_Decode, 155, 5, 55, // Opcode: LDRT_POST_IMM -/* 4317 */ MCD_OPC_FilterValue, 1, 183, 15, 0, // Skip to: 8345 -/* 4322 */ MCD_OPC_CheckPredicate, 0, 178, 15, 0, // Skip to: 8345 -/* 4327 */ MCD_OPC_Decode, 159, 5, 59, // Opcode: LDR_PRE_IMM -/* 4331 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 4367 -/* 4336 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4339 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4353 -/* 4344 */ MCD_OPC_CheckPredicate, 0, 156, 15, 0, // Skip to: 8345 -/* 4349 */ MCD_OPC_Decode, 218, 6, 55, // Opcode: STRB_POST_IMM -/* 4353 */ MCD_OPC_FilterValue, 1, 147, 15, 0, // Skip to: 8345 -/* 4358 */ MCD_OPC_CheckPredicate, 0, 142, 15, 0, // Skip to: 8345 -/* 4363 */ MCD_OPC_Decode, 222, 6, 60, // Opcode: STRBi12 -/* 4367 */ MCD_OPC_FilterValue, 5, 77, 0, 0, // Skip to: 4449 -/* 4372 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4375 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 4412 -/* 4380 */ MCD_OPC_CheckPredicate, 15, 18, 0, 0, // Skip to: 4403 -/* 4385 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4403 -/* 4392 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4403 -/* 4399 */ MCD_OPC_Decode, 203, 5, 57, // Opcode: PLIi12 -/* 4403 */ MCD_OPC_CheckPredicate, 0, 97, 15, 0, // Skip to: 8345 -/* 4408 */ MCD_OPC_Decode, 255, 4, 55, // Opcode: LDRB_POST_IMM -/* 4412 */ MCD_OPC_FilterValue, 1, 88, 15, 0, // Skip to: 8345 -/* 4417 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 4440 -/* 4422 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4440 -/* 4429 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4440 -/* 4436 */ MCD_OPC_Decode, 201, 5, 57, // Opcode: PLDi12 -/* 4440 */ MCD_OPC_CheckPredicate, 0, 60, 15, 0, // Skip to: 8345 -/* 4445 */ MCD_OPC_Decode, 131, 5, 60, // Opcode: LDRBi12 -/* 4449 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 4485 -/* 4454 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4457 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4471 -/* 4462 */ MCD_OPC_CheckPredicate, 0, 38, 15, 0, // Skip to: 8345 -/* 4467 */ MCD_OPC_Decode, 216, 6, 55, // Opcode: STRBT_POST_IMM -/* 4471 */ MCD_OPC_FilterValue, 1, 29, 15, 0, // Skip to: 8345 -/* 4476 */ MCD_OPC_CheckPredicate, 0, 24, 15, 0, // Skip to: 8345 -/* 4481 */ MCD_OPC_Decode, 220, 6, 58, // Opcode: STRB_PRE_IMM -/* 4485 */ MCD_OPC_FilterValue, 7, 15, 15, 0, // Skip to: 8345 -/* 4490 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4493 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4507 -/* 4498 */ MCD_OPC_CheckPredicate, 0, 2, 15, 0, // Skip to: 8345 -/* 4503 */ MCD_OPC_Decode, 253, 4, 55, // Opcode: LDRBT_POST_IMM -/* 4507 */ MCD_OPC_FilterValue, 1, 249, 14, 0, // Skip to: 8345 -/* 4512 */ MCD_OPC_CheckPredicate, 17, 27, 0, 0, // Skip to: 4544 -/* 4517 */ MCD_OPC_CheckField, 28, 4, 15, 20, 0, 0, // Skip to: 4544 -/* 4524 */ MCD_OPC_CheckField, 23, 1, 0, 13, 0, 0, // Skip to: 4544 -/* 4531 */ MCD_OPC_CheckField, 0, 20, 159, 224, 63, 4, 0, 0, // Skip to: 4544 -/* 4540 */ MCD_OPC_Decode, 181, 4, 51, // Opcode: CLREX -/* 4544 */ MCD_OPC_ExtractField, 4, 16, // Inst{19-4} ... -/* 4547 */ MCD_OPC_FilterValue, 132, 254, 3, 23, 0, 0, // Skip to: 4577 -/* 4554 */ MCD_OPC_CheckPredicate, 18, 78, 0, 0, // Skip to: 4637 -/* 4559 */ MCD_OPC_CheckField, 28, 4, 15, 71, 0, 0, // Skip to: 4637 -/* 4566 */ MCD_OPC_CheckField, 23, 1, 0, 64, 0, 0, // Skip to: 4637 -/* 4573 */ MCD_OPC_Decode, 202, 4, 61, // Opcode: DSB -/* 4577 */ MCD_OPC_FilterValue, 133, 254, 3, 23, 0, 0, // Skip to: 4607 -/* 4584 */ MCD_OPC_CheckPredicate, 18, 48, 0, 0, // Skip to: 4637 -/* 4589 */ MCD_OPC_CheckField, 28, 4, 15, 41, 0, 0, // Skip to: 4637 -/* 4596 */ MCD_OPC_CheckField, 23, 1, 0, 34, 0, 0, // Skip to: 4637 -/* 4603 */ MCD_OPC_Decode, 201, 4, 61, // Opcode: DMB -/* 4607 */ MCD_OPC_FilterValue, 134, 254, 3, 23, 0, 0, // Skip to: 4637 -/* 4614 */ MCD_OPC_CheckPredicate, 18, 18, 0, 0, // Skip to: 4637 -/* 4619 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4637 -/* 4626 */ MCD_OPC_CheckField, 23, 1, 0, 4, 0, 0, // Skip to: 4637 -/* 4633 */ MCD_OPC_Decode, 221, 4, 62, // Opcode: ISB -/* 4637 */ MCD_OPC_CheckPredicate, 0, 119, 14, 0, // Skip to: 8345 -/* 4642 */ MCD_OPC_Decode, 129, 5, 59, // Opcode: LDRB_PRE_IMM -/* 4646 */ MCD_OPC_FilterValue, 3, 129, 10, 0, // Skip to: 7340 -/* 4651 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 4654 */ MCD_OPC_FilterValue, 0, 200, 2, 0, // Skip to: 5371 -/* 4659 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 4662 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 4765 -/* 4667 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4670 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4706 -/* 4675 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4678 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4692 -/* 4683 */ MCD_OPC_CheckPredicate, 0, 73, 14, 0, // Skip to: 8345 -/* 4688 */ MCD_OPC_Decode, 239, 6, 55, // Opcode: STR_POST_REG -/* 4692 */ MCD_OPC_FilterValue, 1, 64, 14, 0, // Skip to: 8345 -/* 4697 */ MCD_OPC_CheckPredicate, 0, 59, 14, 0, // Skip to: 8345 -/* 4702 */ MCD_OPC_Decode, 243, 6, 63, // Opcode: STRrs -/* 4706 */ MCD_OPC_FilterValue, 1, 50, 14, 0, // Skip to: 8345 -/* 4711 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 4714 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4728 -/* 4719 */ MCD_OPC_CheckPredicate, 0, 37, 14, 0, // Skip to: 8345 -/* 4724 */ MCD_OPC_Decode, 158, 5, 55, // Opcode: LDR_POST_REG -/* 4728 */ MCD_OPC_FilterValue, 1, 28, 14, 0, // Skip to: 8345 -/* 4733 */ MCD_OPC_CheckPredicate, 16, 18, 0, 0, // Skip to: 4756 -/* 4738 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4756 -/* 4745 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4756 -/* 4752 */ MCD_OPC_Decode, 200, 5, 64, // Opcode: PLDWrs -/* 4756 */ MCD_OPC_CheckPredicate, 0, 0, 14, 0, // Skip to: 8345 -/* 4761 */ MCD_OPC_Decode, 163, 5, 63, // Opcode: LDRrs -/* 4765 */ MCD_OPC_FilterValue, 1, 247, 13, 0, // Skip to: 8345 -/* 4770 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 4773 */ MCD_OPC_FilterValue, 0, 202, 0, 0, // Skip to: 4980 -/* 4778 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 4781 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 4839 -/* 4786 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4789 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 4814 -/* 4794 */ MCD_OPC_CheckPredicate, 0, 218, 13, 0, // Skip to: 8345 -/* 4799 */ MCD_OPC_CheckField, 20, 1, 1, 211, 13, 0, // Skip to: 8345 -/* 4806 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 4810 */ MCD_OPC_Decode, 235, 5, 65, // Opcode: SADD16 -/* 4814 */ MCD_OPC_FilterValue, 1, 198, 13, 0, // Skip to: 8345 -/* 4819 */ MCD_OPC_CheckPredicate, 0, 193, 13, 0, // Skip to: 8345 -/* 4824 */ MCD_OPC_CheckField, 20, 1, 1, 186, 13, 0, // Skip to: 8345 -/* 4831 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 4835 */ MCD_OPC_Decode, 236, 5, 65, // Opcode: SADD8 -/* 4839 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4860 -/* 4844 */ MCD_OPC_CheckPredicate, 1, 168, 13, 0, // Skip to: 8345 -/* 4849 */ MCD_OPC_CheckField, 20, 1, 0, 161, 13, 0, // Skip to: 8345 -/* 4856 */ MCD_OPC_Decode, 197, 5, 66, // Opcode: PKHBT -/* 4860 */ MCD_OPC_FilterValue, 2, 69, 0, 0, // Skip to: 4934 -/* 4865 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4868 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 4906 -/* 4873 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4876 */ MCD_OPC_FilterValue, 0, 136, 13, 0, // Skip to: 8345 -/* 4881 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 4897 -/* 4886 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4897 -/* 4893 */ MCD_OPC_Decode, 161, 6, 67, // Opcode: SMUAD -/* 4897 */ MCD_OPC_CheckPredicate, 1, 115, 13, 0, // Skip to: 8345 -/* 4902 */ MCD_OPC_Decode, 138, 6, 68, // Opcode: SMLAD -/* 4906 */ MCD_OPC_FilterValue, 1, 106, 13, 0, // Skip to: 8345 -/* 4911 */ MCD_OPC_CheckPredicate, 19, 101, 13, 0, // Skip to: 8345 -/* 4916 */ MCD_OPC_CheckField, 12, 4, 15, 94, 13, 0, // Skip to: 8345 -/* 4923 */ MCD_OPC_CheckField, 7, 1, 0, 87, 13, 0, // Skip to: 8345 -/* 4930 */ MCD_OPC_Decode, 243, 5, 30, // Opcode: SDIV -/* 4934 */ MCD_OPC_FilterValue, 3, 78, 13, 0, // Skip to: 8345 -/* 4939 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4942 */ MCD_OPC_FilterValue, 0, 70, 13, 0, // Skip to: 8345 -/* 4947 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4950 */ MCD_OPC_FilterValue, 0, 62, 13, 0, // Skip to: 8345 -/* 4955 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 4971 -/* 4960 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4971 -/* 4967 */ MCD_OPC_Decode, 161, 7, 30, // Opcode: USAD8 -/* 4971 */ MCD_OPC_CheckPredicate, 1, 41, 13, 0, // Skip to: 8345 -/* 4976 */ MCD_OPC_Decode, 162, 7, 39, // Opcode: USADA8 -/* 4980 */ MCD_OPC_FilterValue, 1, 113, 0, 0, // Skip to: 5098 -/* 4985 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 4988 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5020 -/* 4993 */ MCD_OPC_CheckPredicate, 0, 19, 13, 0, // Skip to: 8345 -/* 4998 */ MCD_OPC_CheckField, 20, 1, 1, 12, 13, 0, // Skip to: 8345 -/* 5005 */ MCD_OPC_CheckField, 7, 1, 0, 5, 13, 0, // Skip to: 8345 -/* 5012 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5016 */ MCD_OPC_Decode, 237, 5, 65, // Opcode: SASX -/* 5020 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5052 -/* 5025 */ MCD_OPC_CheckPredicate, 1, 243, 12, 0, // Skip to: 8345 -/* 5030 */ MCD_OPC_CheckField, 20, 1, 0, 236, 12, 0, // Skip to: 8345 -/* 5037 */ MCD_OPC_CheckField, 7, 1, 1, 229, 12, 0, // Skip to: 8345 -/* 5044 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5048 */ MCD_OPC_Decode, 244, 5, 69, // Opcode: SEL -/* 5052 */ MCD_OPC_FilterValue, 2, 216, 12, 0, // Skip to: 8345 -/* 5057 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 5060 */ MCD_OPC_FilterValue, 0, 208, 12, 0, // Skip to: 8345 -/* 5065 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5068 */ MCD_OPC_FilterValue, 0, 200, 12, 0, // Skip to: 8345 -/* 5073 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5089 -/* 5078 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5089 -/* 5085 */ MCD_OPC_Decode, 162, 6, 67, // Opcode: SMUADX -/* 5089 */ MCD_OPC_CheckPredicate, 1, 179, 12, 0, // Skip to: 8345 -/* 5094 */ MCD_OPC_Decode, 139, 6, 68, // Opcode: SMLADX -/* 5098 */ MCD_OPC_FilterValue, 2, 102, 0, 0, // Skip to: 5205 -/* 5103 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 5106 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5138 -/* 5111 */ MCD_OPC_CheckPredicate, 0, 157, 12, 0, // Skip to: 8345 -/* 5116 */ MCD_OPC_CheckField, 20, 1, 1, 150, 12, 0, // Skip to: 8345 -/* 5123 */ MCD_OPC_CheckField, 7, 1, 0, 143, 12, 0, // Skip to: 8345 -/* 5130 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5134 */ MCD_OPC_Decode, 182, 6, 65, // Opcode: SSAX -/* 5138 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 5159 -/* 5143 */ MCD_OPC_CheckPredicate, 1, 125, 12, 0, // Skip to: 8345 -/* 5148 */ MCD_OPC_CheckField, 20, 1, 0, 118, 12, 0, // Skip to: 8345 -/* 5155 */ MCD_OPC_Decode, 198, 5, 66, // Opcode: PKHTB -/* 5159 */ MCD_OPC_FilterValue, 2, 109, 12, 0, // Skip to: 8345 -/* 5164 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 5167 */ MCD_OPC_FilterValue, 0, 101, 12, 0, // Skip to: 8345 -/* 5172 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5175 */ MCD_OPC_FilterValue, 0, 93, 12, 0, // Skip to: 8345 -/* 5180 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5196 -/* 5185 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5196 -/* 5192 */ MCD_OPC_Decode, 170, 6, 67, // Opcode: SMUSD -/* 5196 */ MCD_OPC_CheckPredicate, 1, 72, 12, 0, // Skip to: 8345 -/* 5201 */ MCD_OPC_Decode, 151, 6, 68, // Opcode: SMLSD -/* 5205 */ MCD_OPC_FilterValue, 3, 63, 12, 0, // Skip to: 8345 -/* 5210 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 5213 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 5271 -/* 5218 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 5221 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 5246 -/* 5226 */ MCD_OPC_CheckPredicate, 0, 42, 12, 0, // Skip to: 8345 -/* 5231 */ MCD_OPC_CheckField, 20, 1, 1, 35, 12, 0, // Skip to: 8345 -/* 5238 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5242 */ MCD_OPC_Decode, 183, 6, 65, // Opcode: SSUB16 -/* 5246 */ MCD_OPC_FilterValue, 1, 22, 12, 0, // Skip to: 8345 -/* 5251 */ MCD_OPC_CheckPredicate, 0, 17, 12, 0, // Skip to: 8345 -/* 5256 */ MCD_OPC_CheckField, 20, 1, 1, 10, 12, 0, // Skip to: 8345 -/* 5263 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5267 */ MCD_OPC_Decode, 184, 6, 65, // Opcode: SSUB8 -/* 5271 */ MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 5325 -/* 5276 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 5279 */ MCD_OPC_FilterValue, 0, 245, 11, 0, // Skip to: 8345 -/* 5284 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5287 */ MCD_OPC_FilterValue, 0, 237, 11, 0, // Skip to: 8345 -/* 5292 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5312 -/* 5297 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5312 -/* 5304 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 5308 */ MCD_OPC_Decode, 255, 6, 70, // Opcode: SXTB16 -/* 5312 */ MCD_OPC_CheckPredicate, 1, 212, 11, 0, // Skip to: 8345 -/* 5317 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 5321 */ MCD_OPC_Decode, 252, 6, 71, // Opcode: SXTAB16 -/* 5325 */ MCD_OPC_FilterValue, 2, 199, 11, 0, // Skip to: 8345 -/* 5330 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 5333 */ MCD_OPC_FilterValue, 0, 191, 11, 0, // Skip to: 8345 -/* 5338 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5341 */ MCD_OPC_FilterValue, 0, 183, 11, 0, // Skip to: 8345 -/* 5346 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5362 -/* 5351 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5362 -/* 5358 */ MCD_OPC_Decode, 171, 6, 67, // Opcode: SMUSDX -/* 5362 */ MCD_OPC_CheckPredicate, 1, 162, 11, 0, // Skip to: 8345 -/* 5367 */ MCD_OPC_Decode, 152, 6, 68, // Opcode: SMLSDX -/* 5371 */ MCD_OPC_FilterValue, 1, 106, 2, 0, // Skip to: 5994 -/* 5376 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 5379 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 5459 -/* 5384 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5387 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5423 -/* 5392 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 5395 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5409 -/* 5400 */ MCD_OPC_CheckPredicate, 0, 124, 11, 0, // Skip to: 8345 -/* 5405 */ MCD_OPC_Decode, 237, 6, 55, // Opcode: STRT_POST_REG -/* 5409 */ MCD_OPC_FilterValue, 1, 115, 11, 0, // Skip to: 8345 -/* 5414 */ MCD_OPC_CheckPredicate, 0, 110, 11, 0, // Skip to: 8345 -/* 5419 */ MCD_OPC_Decode, 241, 6, 72, // Opcode: STR_PRE_REG -/* 5423 */ MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 8345 -/* 5428 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 5431 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5445 -/* 5436 */ MCD_OPC_CheckPredicate, 0, 88, 11, 0, // Skip to: 8345 -/* 5441 */ MCD_OPC_Decode, 156, 5, 55, // Opcode: LDRT_POST_REG -/* 5445 */ MCD_OPC_FilterValue, 1, 79, 11, 0, // Skip to: 8345 -/* 5450 */ MCD_OPC_CheckPredicate, 0, 74, 11, 0, // Skip to: 8345 -/* 5455 */ MCD_OPC_Decode, 160, 5, 73, // Opcode: LDR_PRE_REG -/* 5459 */ MCD_OPC_FilterValue, 1, 65, 11, 0, // Skip to: 8345 -/* 5464 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 5467 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 5739 -/* 5472 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... -/* 5475 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 5519 -/* 5480 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5483 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5501 -/* 5488 */ MCD_OPC_CheckPredicate, 0, 36, 11, 0, // Skip to: 8345 -/* 5493 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5497 */ MCD_OPC_Decode, 206, 5, 65, // Opcode: QADD16 -/* 5501 */ MCD_OPC_FilterValue, 1, 23, 11, 0, // Skip to: 8345 -/* 5506 */ MCD_OPC_CheckPredicate, 0, 18, 11, 0, // Skip to: 8345 -/* 5511 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5515 */ MCD_OPC_Decode, 129, 6, 65, // Opcode: SHADD16 -/* 5519 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 5563 -/* 5524 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5527 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5545 -/* 5532 */ MCD_OPC_CheckPredicate, 0, 248, 10, 0, // Skip to: 8345 -/* 5537 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5541 */ MCD_OPC_Decode, 208, 5, 65, // Opcode: QASX -/* 5545 */ MCD_OPC_FilterValue, 1, 235, 10, 0, // Skip to: 8345 -/* 5550 */ MCD_OPC_CheckPredicate, 0, 230, 10, 0, // Skip to: 8345 -/* 5555 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5559 */ MCD_OPC_Decode, 131, 6, 65, // Opcode: SHASX -/* 5563 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 5607 -/* 5568 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5571 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5589 -/* 5576 */ MCD_OPC_CheckPredicate, 0, 204, 10, 0, // Skip to: 8345 -/* 5581 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5585 */ MCD_OPC_Decode, 211, 5, 65, // Opcode: QSAX -/* 5589 */ MCD_OPC_FilterValue, 1, 191, 10, 0, // Skip to: 8345 -/* 5594 */ MCD_OPC_CheckPredicate, 0, 186, 10, 0, // Skip to: 8345 -/* 5599 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5603 */ MCD_OPC_Decode, 132, 6, 65, // Opcode: SHSAX -/* 5607 */ MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 5651 -/* 5612 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5615 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5633 -/* 5620 */ MCD_OPC_CheckPredicate, 0, 160, 10, 0, // Skip to: 8345 -/* 5625 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5629 */ MCD_OPC_Decode, 213, 5, 65, // Opcode: QSUB16 -/* 5633 */ MCD_OPC_FilterValue, 1, 147, 10, 0, // Skip to: 8345 -/* 5638 */ MCD_OPC_CheckPredicate, 0, 142, 10, 0, // Skip to: 8345 -/* 5643 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5647 */ MCD_OPC_Decode, 133, 6, 65, // Opcode: SHSUB16 -/* 5651 */ MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 5695 -/* 5656 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5659 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5677 -/* 5664 */ MCD_OPC_CheckPredicate, 0, 116, 10, 0, // Skip to: 8345 -/* 5669 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5673 */ MCD_OPC_Decode, 207, 5, 65, // Opcode: QADD8 -/* 5677 */ MCD_OPC_FilterValue, 1, 103, 10, 0, // Skip to: 8345 -/* 5682 */ MCD_OPC_CheckPredicate, 0, 98, 10, 0, // Skip to: 8345 -/* 5687 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5691 */ MCD_OPC_Decode, 130, 6, 65, // Opcode: SHADD8 -/* 5695 */ MCD_OPC_FilterValue, 7, 85, 10, 0, // Skip to: 8345 -/* 5700 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5703 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5721 -/* 5708 */ MCD_OPC_CheckPredicate, 0, 72, 10, 0, // Skip to: 8345 -/* 5713 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5717 */ MCD_OPC_Decode, 214, 5, 65, // Opcode: QSUB8 -/* 5721 */ MCD_OPC_FilterValue, 1, 59, 10, 0, // Skip to: 8345 -/* 5726 */ MCD_OPC_CheckPredicate, 0, 54, 10, 0, // Skip to: 8345 -/* 5731 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 5735 */ MCD_OPC_Decode, 134, 6, 65, // Opcode: SHSUB8 -/* 5739 */ MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 5938 -/* 5744 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 5747 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5761 -/* 5752 */ MCD_OPC_CheckPredicate, 1, 28, 10, 0, // Skip to: 8345 -/* 5757 */ MCD_OPC_Decode, 180, 6, 74, // Opcode: SSAT -/* 5761 */ MCD_OPC_FilterValue, 1, 19, 10, 0, // Skip to: 8345 -/* 5766 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 5769 */ MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 5826 -/* 5774 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5777 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 5798 -/* 5782 */ MCD_OPC_CheckPredicate, 1, 254, 9, 0, // Skip to: 8345 -/* 5787 */ MCD_OPC_CheckField, 8, 4, 15, 247, 9, 0, // Skip to: 8345 -/* 5794 */ MCD_OPC_Decode, 181, 6, 75, // Opcode: SSAT16 -/* 5798 */ MCD_OPC_FilterValue, 1, 238, 9, 0, // Skip to: 8345 -/* 5803 */ MCD_OPC_CheckPredicate, 1, 233, 9, 0, // Skip to: 8345 -/* 5808 */ MCD_OPC_CheckField, 16, 4, 15, 226, 9, 0, // Skip to: 8345 -/* 5815 */ MCD_OPC_CheckField, 8, 4, 15, 219, 9, 0, // Skip to: 8345 -/* 5822 */ MCD_OPC_Decode, 216, 5, 35, // Opcode: REV -/* 5826 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 5910 -/* 5831 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5834 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 5872 -/* 5839 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5859 -/* 5844 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5859 -/* 5851 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 5855 */ MCD_OPC_Decode, 254, 6, 70, // Opcode: SXTB -/* 5859 */ MCD_OPC_CheckPredicate, 1, 177, 9, 0, // Skip to: 8345 -/* 5864 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 5868 */ MCD_OPC_Decode, 251, 6, 71, // Opcode: SXTAB -/* 5872 */ MCD_OPC_FilterValue, 1, 164, 9, 0, // Skip to: 8345 -/* 5877 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5897 -/* 5882 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5897 -/* 5889 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 5893 */ MCD_OPC_Decode, 128, 7, 70, // Opcode: SXTH -/* 5897 */ MCD_OPC_CheckPredicate, 1, 139, 9, 0, // Skip to: 8345 -/* 5902 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 5906 */ MCD_OPC_Decode, 253, 6, 71, // Opcode: SXTAH -/* 5910 */ MCD_OPC_FilterValue, 2, 126, 9, 0, // Skip to: 8345 -/* 5915 */ MCD_OPC_CheckPredicate, 1, 121, 9, 0, // Skip to: 8345 -/* 5920 */ MCD_OPC_CheckField, 16, 5, 31, 114, 9, 0, // Skip to: 8345 -/* 5927 */ MCD_OPC_CheckField, 8, 4, 15, 107, 9, 0, // Skip to: 8345 -/* 5934 */ MCD_OPC_Decode, 217, 5, 35, // Opcode: REV16 -/* 5938 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 5973 -/* 5943 */ MCD_OPC_CheckPredicate, 19, 93, 9, 0, // Skip to: 8345 -/* 5948 */ MCD_OPC_CheckField, 20, 1, 1, 86, 9, 0, // Skip to: 8345 -/* 5955 */ MCD_OPC_CheckField, 12, 4, 15, 79, 9, 0, // Skip to: 8345 -/* 5962 */ MCD_OPC_CheckField, 5, 3, 0, 72, 9, 0, // Skip to: 8345 -/* 5969 */ MCD_OPC_Decode, 145, 7, 30, // Opcode: UDIV -/* 5973 */ MCD_OPC_FilterValue, 3, 63, 9, 0, // Skip to: 8345 -/* 5978 */ MCD_OPC_CheckPredicate, 13, 58, 9, 0, // Skip to: 8345 -/* 5983 */ MCD_OPC_CheckField, 5, 2, 2, 51, 9, 0, // Skip to: 8345 -/* 5990 */ MCD_OPC_Decode, 242, 5, 76, // Opcode: SBFX -/* 5994 */ MCD_OPC_FilterValue, 2, 155, 2, 0, // Skip to: 6666 -/* 5999 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 6002 */ MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 6128 -/* 6007 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6010 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6046 -/* 6015 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 6018 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6032 -/* 6023 */ MCD_OPC_CheckPredicate, 0, 13, 9, 0, // Skip to: 8345 -/* 6028 */ MCD_OPC_Decode, 219, 6, 55, // Opcode: STRB_POST_REG -/* 6032 */ MCD_OPC_FilterValue, 1, 4, 9, 0, // Skip to: 8345 -/* 6037 */ MCD_OPC_CheckPredicate, 0, 255, 8, 0, // Skip to: 8345 -/* 6042 */ MCD_OPC_Decode, 223, 6, 77, // Opcode: STRBrs -/* 6046 */ MCD_OPC_FilterValue, 1, 246, 8, 0, // Skip to: 8345 -/* 6051 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 6054 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 6091 -/* 6059 */ MCD_OPC_CheckPredicate, 15, 18, 0, 0, // Skip to: 6082 -/* 6064 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6082 -/* 6071 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6082 -/* 6078 */ MCD_OPC_Decode, 204, 5, 64, // Opcode: PLIrs -/* 6082 */ MCD_OPC_CheckPredicate, 0, 210, 8, 0, // Skip to: 8345 -/* 6087 */ MCD_OPC_Decode, 128, 5, 55, // Opcode: LDRB_POST_REG -/* 6091 */ MCD_OPC_FilterValue, 1, 201, 8, 0, // Skip to: 8345 -/* 6096 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 6119 -/* 6101 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6119 -/* 6108 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6119 -/* 6115 */ MCD_OPC_Decode, 202, 5, 64, // Opcode: PLDrs -/* 6119 */ MCD_OPC_CheckPredicate, 0, 173, 8, 0, // Skip to: 8345 -/* 6124 */ MCD_OPC_Decode, 132, 5, 77, // Opcode: LDRBrs -/* 6128 */ MCD_OPC_FilterValue, 1, 164, 8, 0, // Skip to: 8345 -/* 6133 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 6136 */ MCD_OPC_FilterValue, 0, 158, 0, 0, // Skip to: 6299 -/* 6141 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 6144 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6202 -/* 6149 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6152 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6177 -/* 6157 */ MCD_OPC_CheckPredicate, 0, 135, 8, 0, // Skip to: 8345 -/* 6162 */ MCD_OPC_CheckField, 20, 1, 1, 128, 8, 0, // Skip to: 8345 -/* 6169 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6173 */ MCD_OPC_Decode, 140, 7, 65, // Opcode: UADD16 -/* 6177 */ MCD_OPC_FilterValue, 1, 115, 8, 0, // Skip to: 8345 -/* 6182 */ MCD_OPC_CheckPredicate, 0, 110, 8, 0, // Skip to: 8345 -/* 6187 */ MCD_OPC_CheckField, 20, 1, 1, 103, 8, 0, // Skip to: 8345 -/* 6194 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6198 */ MCD_OPC_Decode, 141, 7, 65, // Opcode: UADD8 -/* 6202 */ MCD_OPC_FilterValue, 2, 62, 0, 0, // Skip to: 6269 -/* 6207 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6210 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6231 -/* 6215 */ MCD_OPC_CheckPredicate, 1, 77, 8, 0, // Skip to: 8345 -/* 6220 */ MCD_OPC_CheckField, 7, 1, 0, 70, 8, 0, // Skip to: 8345 -/* 6227 */ MCD_OPC_Decode, 143, 6, 19, // Opcode: SMLALD -/* 6231 */ MCD_OPC_FilterValue, 1, 61, 8, 0, // Skip to: 8345 -/* 6236 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6239 */ MCD_OPC_FilterValue, 0, 53, 8, 0, // Skip to: 8345 -/* 6244 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6260 -/* 6249 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6260 -/* 6256 */ MCD_OPC_Decode, 159, 6, 30, // Opcode: SMMUL -/* 6260 */ MCD_OPC_CheckPredicate, 1, 32, 8, 0, // Skip to: 8345 -/* 6265 */ MCD_OPC_Decode, 155, 6, 39, // Opcode: SMMLA -/* 6269 */ MCD_OPC_FilterValue, 3, 23, 8, 0, // Skip to: 8345 -/* 6274 */ MCD_OPC_CheckPredicate, 13, 11, 0, 0, // Skip to: 6290 -/* 6279 */ MCD_OPC_CheckField, 0, 4, 15, 4, 0, 0, // Skip to: 6290 -/* 6286 */ MCD_OPC_Decode, 162, 4, 78, // Opcode: BFC -/* 6290 */ MCD_OPC_CheckPredicate, 13, 2, 8, 0, // Skip to: 8345 -/* 6295 */ MCD_OPC_Decode, 163, 4, 79, // Opcode: BFI -/* 6299 */ MCD_OPC_FilterValue, 1, 102, 0, 0, // Skip to: 6406 -/* 6304 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6307 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6335 -/* 6312 */ MCD_OPC_CheckPredicate, 1, 236, 7, 0, // Skip to: 8345 -/* 6317 */ MCD_OPC_CheckField, 23, 2, 2, 229, 7, 0, // Skip to: 8345 -/* 6324 */ MCD_OPC_CheckField, 7, 1, 0, 222, 7, 0, // Skip to: 8345 -/* 6331 */ MCD_OPC_Decode, 144, 6, 19, // Opcode: SMLALDX -/* 6335 */ MCD_OPC_FilterValue, 1, 213, 7, 0, // Skip to: 8345 -/* 6340 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 6343 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6368 -/* 6348 */ MCD_OPC_CheckPredicate, 0, 200, 7, 0, // Skip to: 8345 -/* 6353 */ MCD_OPC_CheckField, 7, 1, 0, 193, 7, 0, // Skip to: 8345 -/* 6360 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6364 */ MCD_OPC_Decode, 142, 7, 65, // Opcode: UASX -/* 6368 */ MCD_OPC_FilterValue, 2, 180, 7, 0, // Skip to: 8345 -/* 6373 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6376 */ MCD_OPC_FilterValue, 0, 172, 7, 0, // Skip to: 8345 -/* 6381 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6397 -/* 6386 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6397 -/* 6393 */ MCD_OPC_Decode, 160, 6, 30, // Opcode: SMMULR -/* 6397 */ MCD_OPC_CheckPredicate, 1, 151, 7, 0, // Skip to: 8345 -/* 6402 */ MCD_OPC_Decode, 156, 6, 39, // Opcode: SMMLAR -/* 6406 */ MCD_OPC_FilterValue, 2, 85, 0, 0, // Skip to: 6496 -/* 6411 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6414 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6468 -/* 6419 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6422 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6443 -/* 6427 */ MCD_OPC_CheckPredicate, 1, 121, 7, 0, // Skip to: 8345 -/* 6432 */ MCD_OPC_CheckField, 23, 2, 2, 114, 7, 0, // Skip to: 8345 -/* 6439 */ MCD_OPC_Decode, 153, 6, 19, // Opcode: SMLSLD -/* 6443 */ MCD_OPC_FilterValue, 1, 105, 7, 0, // Skip to: 8345 -/* 6448 */ MCD_OPC_CheckPredicate, 0, 100, 7, 0, // Skip to: 8345 -/* 6453 */ MCD_OPC_CheckField, 23, 2, 0, 93, 7, 0, // Skip to: 8345 -/* 6460 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6464 */ MCD_OPC_Decode, 165, 7, 65, // Opcode: USAX -/* 6468 */ MCD_OPC_FilterValue, 1, 80, 7, 0, // Skip to: 8345 -/* 6473 */ MCD_OPC_CheckPredicate, 1, 75, 7, 0, // Skip to: 8345 -/* 6478 */ MCD_OPC_CheckField, 23, 2, 2, 68, 7, 0, // Skip to: 8345 -/* 6485 */ MCD_OPC_CheckField, 20, 1, 1, 61, 7, 0, // Skip to: 8345 -/* 6492 */ MCD_OPC_Decode, 157, 6, 39, // Opcode: SMMLS -/* 6496 */ MCD_OPC_FilterValue, 3, 52, 7, 0, // Skip to: 8345 -/* 6501 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 6504 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6562 -/* 6509 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6512 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6537 -/* 6517 */ MCD_OPC_CheckPredicate, 0, 31, 7, 0, // Skip to: 8345 -/* 6522 */ MCD_OPC_CheckField, 20, 1, 1, 24, 7, 0, // Skip to: 8345 -/* 6529 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6533 */ MCD_OPC_Decode, 166, 7, 65, // Opcode: USUB16 -/* 6537 */ MCD_OPC_FilterValue, 1, 11, 7, 0, // Skip to: 8345 -/* 6542 */ MCD_OPC_CheckPredicate, 0, 6, 7, 0, // Skip to: 8345 -/* 6547 */ MCD_OPC_CheckField, 20, 1, 1, 255, 6, 0, // Skip to: 8345 -/* 6554 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6558 */ MCD_OPC_Decode, 167, 7, 65, // Opcode: USUB8 -/* 6562 */ MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 6616 -/* 6567 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6570 */ MCD_OPC_FilterValue, 0, 234, 6, 0, // Skip to: 8345 -/* 6575 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6578 */ MCD_OPC_FilterValue, 0, 226, 6, 0, // Skip to: 8345 -/* 6583 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 6603 -/* 6588 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 6603 -/* 6595 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 6599 */ MCD_OPC_Decode, 172, 7, 70, // Opcode: UXTB16 -/* 6603 */ MCD_OPC_CheckPredicate, 1, 201, 6, 0, // Skip to: 8345 -/* 6608 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 6612 */ MCD_OPC_Decode, 169, 7, 71, // Opcode: UXTAB16 -/* 6616 */ MCD_OPC_FilterValue, 2, 188, 6, 0, // Skip to: 8345 -/* 6621 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6624 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6645 -/* 6629 */ MCD_OPC_CheckPredicate, 1, 175, 6, 0, // Skip to: 8345 -/* 6634 */ MCD_OPC_CheckField, 20, 1, 0, 168, 6, 0, // Skip to: 8345 -/* 6641 */ MCD_OPC_Decode, 154, 6, 19, // Opcode: SMLSLDX -/* 6645 */ MCD_OPC_FilterValue, 1, 159, 6, 0, // Skip to: 8345 -/* 6650 */ MCD_OPC_CheckPredicate, 1, 154, 6, 0, // Skip to: 8345 -/* 6655 */ MCD_OPC_CheckField, 20, 1, 1, 147, 6, 0, // Skip to: 8345 -/* 6662 */ MCD_OPC_Decode, 158, 6, 39, // Opcode: SMMLSR -/* 6666 */ MCD_OPC_FilterValue, 3, 138, 6, 0, // Skip to: 8345 -/* 6671 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 6674 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 6754 -/* 6679 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6682 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6718 -/* 6687 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 6690 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6704 -/* 6695 */ MCD_OPC_CheckPredicate, 0, 109, 6, 0, // Skip to: 8345 -/* 6700 */ MCD_OPC_Decode, 217, 6, 55, // Opcode: STRBT_POST_REG -/* 6704 */ MCD_OPC_FilterValue, 1, 100, 6, 0, // Skip to: 8345 -/* 6709 */ MCD_OPC_CheckPredicate, 0, 95, 6, 0, // Skip to: 8345 -/* 6714 */ MCD_OPC_Decode, 221, 6, 72, // Opcode: STRB_PRE_REG -/* 6718 */ MCD_OPC_FilterValue, 1, 86, 6, 0, // Skip to: 8345 -/* 6723 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 6726 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6740 -/* 6731 */ MCD_OPC_CheckPredicate, 0, 73, 6, 0, // Skip to: 8345 -/* 6736 */ MCD_OPC_Decode, 254, 4, 55, // Opcode: LDRBT_POST_REG -/* 6740 */ MCD_OPC_FilterValue, 1, 64, 6, 0, // Skip to: 8345 -/* 6745 */ MCD_OPC_CheckPredicate, 0, 59, 6, 0, // Skip to: 8345 -/* 6750 */ MCD_OPC_Decode, 130, 5, 73, // Opcode: LDRB_PRE_REG -/* 6754 */ MCD_OPC_FilterValue, 1, 50, 6, 0, // Skip to: 8345 -/* 6759 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 6762 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 7034 -/* 6767 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... -/* 6770 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 6814 -/* 6775 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6778 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6796 -/* 6783 */ MCD_OPC_CheckPredicate, 0, 21, 6, 0, // Skip to: 8345 -/* 6788 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6792 */ MCD_OPC_Decode, 155, 7, 65, // Opcode: UQADD16 -/* 6796 */ MCD_OPC_FilterValue, 1, 8, 6, 0, // Skip to: 8345 -/* 6801 */ MCD_OPC_CheckPredicate, 0, 3, 6, 0, // Skip to: 8345 -/* 6806 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6810 */ MCD_OPC_Decode, 146, 7, 65, // Opcode: UHADD16 -/* 6814 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 6858 -/* 6819 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6822 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6840 -/* 6827 */ MCD_OPC_CheckPredicate, 0, 233, 5, 0, // Skip to: 8345 -/* 6832 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6836 */ MCD_OPC_Decode, 157, 7, 65, // Opcode: UQASX -/* 6840 */ MCD_OPC_FilterValue, 1, 220, 5, 0, // Skip to: 8345 -/* 6845 */ MCD_OPC_CheckPredicate, 0, 215, 5, 0, // Skip to: 8345 -/* 6850 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6854 */ MCD_OPC_Decode, 148, 7, 65, // Opcode: UHASX -/* 6858 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 6902 -/* 6863 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6866 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6884 -/* 6871 */ MCD_OPC_CheckPredicate, 0, 189, 5, 0, // Skip to: 8345 -/* 6876 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6880 */ MCD_OPC_Decode, 158, 7, 65, // Opcode: UQSAX -/* 6884 */ MCD_OPC_FilterValue, 1, 176, 5, 0, // Skip to: 8345 -/* 6889 */ MCD_OPC_CheckPredicate, 0, 171, 5, 0, // Skip to: 8345 -/* 6894 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6898 */ MCD_OPC_Decode, 149, 7, 65, // Opcode: UHSAX -/* 6902 */ MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 6946 -/* 6907 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6910 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6928 -/* 6915 */ MCD_OPC_CheckPredicate, 0, 145, 5, 0, // Skip to: 8345 -/* 6920 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6924 */ MCD_OPC_Decode, 159, 7, 65, // Opcode: UQSUB16 -/* 6928 */ MCD_OPC_FilterValue, 1, 132, 5, 0, // Skip to: 8345 -/* 6933 */ MCD_OPC_CheckPredicate, 0, 127, 5, 0, // Skip to: 8345 -/* 6938 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6942 */ MCD_OPC_Decode, 150, 7, 65, // Opcode: UHSUB16 -/* 6946 */ MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 6990 -/* 6951 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6954 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6972 -/* 6959 */ MCD_OPC_CheckPredicate, 0, 101, 5, 0, // Skip to: 8345 -/* 6964 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6968 */ MCD_OPC_Decode, 156, 7, 65, // Opcode: UQADD8 -/* 6972 */ MCD_OPC_FilterValue, 1, 88, 5, 0, // Skip to: 8345 -/* 6977 */ MCD_OPC_CheckPredicate, 0, 83, 5, 0, // Skip to: 8345 -/* 6982 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 6986 */ MCD_OPC_Decode, 147, 7, 65, // Opcode: UHADD8 -/* 6990 */ MCD_OPC_FilterValue, 7, 70, 5, 0, // Skip to: 8345 -/* 6995 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6998 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 7016 -/* 7003 */ MCD_OPC_CheckPredicate, 0, 57, 5, 0, // Skip to: 8345 -/* 7008 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 7012 */ MCD_OPC_Decode, 160, 7, 65, // Opcode: UQSUB8 -/* 7016 */ MCD_OPC_FilterValue, 1, 44, 5, 0, // Skip to: 8345 -/* 7021 */ MCD_OPC_CheckPredicate, 0, 39, 5, 0, // Skip to: 8345 -/* 7026 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, -/* 7030 */ MCD_OPC_Decode, 151, 7, 65, // Opcode: UHSUB8 -/* 7034 */ MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 7233 -/* 7039 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 7042 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7056 -/* 7047 */ MCD_OPC_CheckPredicate, 1, 13, 5, 0, // Skip to: 8345 -/* 7052 */ MCD_OPC_Decode, 163, 7, 74, // Opcode: USAT -/* 7056 */ MCD_OPC_FilterValue, 1, 4, 5, 0, // Skip to: 8345 -/* 7061 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7064 */ MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 7121 -/* 7069 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7072 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7093 -/* 7077 */ MCD_OPC_CheckPredicate, 1, 239, 4, 0, // Skip to: 8345 -/* 7082 */ MCD_OPC_CheckField, 8, 4, 15, 232, 4, 0, // Skip to: 8345 -/* 7089 */ MCD_OPC_Decode, 164, 7, 75, // Opcode: USAT16 -/* 7093 */ MCD_OPC_FilterValue, 1, 223, 4, 0, // Skip to: 8345 -/* 7098 */ MCD_OPC_CheckPredicate, 13, 218, 4, 0, // Skip to: 8345 -/* 7103 */ MCD_OPC_CheckField, 16, 4, 15, 211, 4, 0, // Skip to: 8345 -/* 7110 */ MCD_OPC_CheckField, 8, 4, 15, 204, 4, 0, // Skip to: 8345 -/* 7117 */ MCD_OPC_Decode, 215, 5, 35, // Opcode: RBIT -/* 7121 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 7205 -/* 7126 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7129 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7167 -/* 7134 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7154 -/* 7139 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7154 -/* 7146 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 7150 */ MCD_OPC_Decode, 171, 7, 70, // Opcode: UXTB -/* 7154 */ MCD_OPC_CheckPredicate, 1, 162, 4, 0, // Skip to: 8345 -/* 7159 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 7163 */ MCD_OPC_Decode, 168, 7, 71, // Opcode: UXTAB -/* 7167 */ MCD_OPC_FilterValue, 1, 149, 4, 0, // Skip to: 8345 -/* 7172 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7192 -/* 7177 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7192 -/* 7184 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 7188 */ MCD_OPC_Decode, 173, 7, 70, // Opcode: UXTH -/* 7192 */ MCD_OPC_CheckPredicate, 1, 124, 4, 0, // Skip to: 8345 -/* 7197 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, -/* 7201 */ MCD_OPC_Decode, 170, 7, 71, // Opcode: UXTAH -/* 7205 */ MCD_OPC_FilterValue, 2, 111, 4, 0, // Skip to: 8345 -/* 7210 */ MCD_OPC_CheckPredicate, 1, 106, 4, 0, // Skip to: 8345 -/* 7215 */ MCD_OPC_CheckField, 16, 5, 31, 99, 4, 0, // Skip to: 8345 -/* 7222 */ MCD_OPC_CheckField, 8, 4, 15, 92, 4, 0, // Skip to: 8345 -/* 7229 */ MCD_OPC_Decode, 218, 5, 35, // Opcode: REVSH -/* 7233 */ MCD_OPC_FilterValue, 3, 83, 4, 0, // Skip to: 8345 -/* 7238 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 7241 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7255 -/* 7246 */ MCD_OPC_CheckPredicate, 13, 70, 4, 0, // Skip to: 8345 -/* 7251 */ MCD_OPC_Decode, 143, 7, 76, // Opcode: UBFX -/* 7255 */ MCD_OPC_FilterValue, 3, 61, 4, 0, // Skip to: 8345 -/* 7260 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 7263 */ MCD_OPC_FilterValue, 1, 53, 4, 0, // Skip to: 8345 -/* 7268 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7271 */ MCD_OPC_FilterValue, 1, 45, 4, 0, // Skip to: 8345 -/* 7276 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... -/* 7279 */ MCD_OPC_FilterValue, 14, 37, 4, 0, // Skip to: 8345 -/* 7284 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 7287 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7309 -/* 7292 */ MCD_OPC_CheckPredicate, 20, 34, 0, 0, // Skip to: 7331 -/* 7297 */ MCD_OPC_CheckField, 8, 12, 222, 29, 26, 0, 0, // Skip to: 7331 -/* 7305 */ MCD_OPC_Decode, 134, 7, 51, // Opcode: TRAPNaCl -/* 7309 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7331 -/* 7314 */ MCD_OPC_CheckPredicate, 0, 12, 0, 0, // Skip to: 7331 -/* 7319 */ MCD_OPC_CheckField, 8, 12, 222, 31, 4, 0, 0, // Skip to: 7331 -/* 7327 */ MCD_OPC_Decode, 133, 7, 51, // Opcode: TRAP -/* 7331 */ MCD_OPC_CheckPredicate, 0, 241, 3, 0, // Skip to: 8345 -/* 7336 */ MCD_OPC_Decode, 144, 7, 15, // Opcode: UDF -/* 7340 */ MCD_OPC_FilterValue, 4, 75, 3, 0, // Skip to: 8188 -/* 7345 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 7348 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7362 -/* 7353 */ MCD_OPC_CheckPredicate, 0, 219, 3, 0, // Skip to: 8345 -/* 7358 */ MCD_OPC_Decode, 208, 6, 80, // Opcode: STMDA -/* 7362 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 7400 -/* 7367 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7391 -/* 7372 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7391 -/* 7379 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7391 -/* 7387 */ MCD_OPC_Decode, 219, 5, 81, // Opcode: RFEDA -/* 7391 */ MCD_OPC_CheckPredicate, 0, 181, 3, 0, // Skip to: 8345 -/* 7396 */ MCD_OPC_Decode, 245, 4, 80, // Opcode: LDMDA -/* 7400 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7414 -/* 7405 */ MCD_OPC_CheckPredicate, 0, 167, 3, 0, // Skip to: 8345 -/* 7410 */ MCD_OPC_Decode, 209, 6, 82, // Opcode: STMDA_UPD -/* 7414 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 7452 -/* 7419 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7443 -/* 7424 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7443 -/* 7431 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7443 -/* 7439 */ MCD_OPC_Decode, 220, 5, 81, // Opcode: RFEDA_UPD -/* 7443 */ MCD_OPC_CheckPredicate, 0, 129, 3, 0, // Skip to: 8345 -/* 7448 */ MCD_OPC_Decode, 246, 4, 82, // Opcode: LDMDA_UPD -/* 7452 */ MCD_OPC_FilterValue, 4, 34, 0, 0, // Skip to: 7491 -/* 7457 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7482 -/* 7462 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7482 -/* 7469 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7482 -/* 7478 */ MCD_OPC_Decode, 172, 6, 83, // Opcode: SRSDA -/* 7482 */ MCD_OPC_CheckPredicate, 0, 90, 3, 0, // Skip to: 8345 -/* 7487 */ MCD_OPC_Decode, 190, 21, 80, // Opcode: sysSTMDA -/* 7491 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 7505 -/* 7496 */ MCD_OPC_CheckPredicate, 0, 76, 3, 0, // Skip to: 8345 -/* 7501 */ MCD_OPC_Decode, 182, 21, 80, // Opcode: sysLDMDA -/* 7505 */ MCD_OPC_FilterValue, 6, 34, 0, 0, // Skip to: 7544 -/* 7510 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7535 -/* 7515 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7535 -/* 7522 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7535 -/* 7531 */ MCD_OPC_Decode, 173, 6, 83, // Opcode: SRSDA_UPD -/* 7535 */ MCD_OPC_CheckPredicate, 0, 37, 3, 0, // Skip to: 8345 -/* 7540 */ MCD_OPC_Decode, 191, 21, 82, // Opcode: sysSTMDA_UPD -/* 7544 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 7558 -/* 7549 */ MCD_OPC_CheckPredicate, 0, 23, 3, 0, // Skip to: 8345 -/* 7554 */ MCD_OPC_Decode, 183, 21, 82, // Opcode: sysLDMDA_UPD -/* 7558 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7572 -/* 7563 */ MCD_OPC_CheckPredicate, 0, 9, 3, 0, // Skip to: 8345 -/* 7568 */ MCD_OPC_Decode, 212, 6, 80, // Opcode: STMIA -/* 7572 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 7610 -/* 7577 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7601 -/* 7582 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7601 -/* 7589 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7601 -/* 7597 */ MCD_OPC_Decode, 223, 5, 81, // Opcode: RFEIA -/* 7601 */ MCD_OPC_CheckPredicate, 0, 227, 2, 0, // Skip to: 8345 -/* 7606 */ MCD_OPC_Decode, 249, 4, 80, // Opcode: LDMIA -/* 7610 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7624 -/* 7615 */ MCD_OPC_CheckPredicate, 0, 213, 2, 0, // Skip to: 8345 -/* 7620 */ MCD_OPC_Decode, 213, 6, 82, // Opcode: STMIA_UPD -/* 7624 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 7662 -/* 7629 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7653 -/* 7634 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7653 -/* 7641 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7653 -/* 7649 */ MCD_OPC_Decode, 224, 5, 81, // Opcode: RFEIA_UPD -/* 7653 */ MCD_OPC_CheckPredicate, 0, 175, 2, 0, // Skip to: 8345 -/* 7658 */ MCD_OPC_Decode, 250, 4, 82, // Opcode: LDMIA_UPD -/* 7662 */ MCD_OPC_FilterValue, 12, 34, 0, 0, // Skip to: 7701 -/* 7667 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7692 -/* 7672 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7692 -/* 7679 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7692 -/* 7688 */ MCD_OPC_Decode, 176, 6, 83, // Opcode: SRSIA -/* 7692 */ MCD_OPC_CheckPredicate, 0, 136, 2, 0, // Skip to: 8345 -/* 7697 */ MCD_OPC_Decode, 194, 21, 80, // Opcode: sysSTMIA -/* 7701 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 7715 -/* 7706 */ MCD_OPC_CheckPredicate, 0, 122, 2, 0, // Skip to: 8345 -/* 7711 */ MCD_OPC_Decode, 186, 21, 80, // Opcode: sysLDMIA -/* 7715 */ MCD_OPC_FilterValue, 14, 34, 0, 0, // Skip to: 7754 -/* 7720 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7745 -/* 7725 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7745 -/* 7732 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7745 -/* 7741 */ MCD_OPC_Decode, 177, 6, 83, // Opcode: SRSIA_UPD -/* 7745 */ MCD_OPC_CheckPredicate, 0, 83, 2, 0, // Skip to: 8345 -/* 7750 */ MCD_OPC_Decode, 195, 21, 82, // Opcode: sysSTMIA_UPD -/* 7754 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 7768 -/* 7759 */ MCD_OPC_CheckPredicate, 0, 69, 2, 0, // Skip to: 8345 -/* 7764 */ MCD_OPC_Decode, 187, 21, 82, // Opcode: sysLDMIA_UPD -/* 7768 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 7782 -/* 7773 */ MCD_OPC_CheckPredicate, 0, 55, 2, 0, // Skip to: 8345 -/* 7778 */ MCD_OPC_Decode, 210, 6, 80, // Opcode: STMDB -/* 7782 */ MCD_OPC_FilterValue, 17, 33, 0, 0, // Skip to: 7820 -/* 7787 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7811 -/* 7792 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7811 -/* 7799 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7811 -/* 7807 */ MCD_OPC_Decode, 221, 5, 81, // Opcode: RFEDB -/* 7811 */ MCD_OPC_CheckPredicate, 0, 17, 2, 0, // Skip to: 8345 -/* 7816 */ MCD_OPC_Decode, 247, 4, 80, // Opcode: LDMDB -/* 7820 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 7834 -/* 7825 */ MCD_OPC_CheckPredicate, 0, 3, 2, 0, // Skip to: 8345 -/* 7830 */ MCD_OPC_Decode, 211, 6, 82, // Opcode: STMDB_UPD -/* 7834 */ MCD_OPC_FilterValue, 19, 33, 0, 0, // Skip to: 7872 -/* 7839 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7863 -/* 7844 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7863 -/* 7851 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7863 -/* 7859 */ MCD_OPC_Decode, 222, 5, 81, // Opcode: RFEDB_UPD -/* 7863 */ MCD_OPC_CheckPredicate, 0, 221, 1, 0, // Skip to: 8345 -/* 7868 */ MCD_OPC_Decode, 248, 4, 82, // Opcode: LDMDB_UPD -/* 7872 */ MCD_OPC_FilterValue, 20, 34, 0, 0, // Skip to: 7911 -/* 7877 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7902 -/* 7882 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7902 -/* 7889 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7902 -/* 7898 */ MCD_OPC_Decode, 174, 6, 83, // Opcode: SRSDB -/* 7902 */ MCD_OPC_CheckPredicate, 0, 182, 1, 0, // Skip to: 8345 -/* 7907 */ MCD_OPC_Decode, 192, 21, 80, // Opcode: sysSTMDB -/* 7911 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 7925 -/* 7916 */ MCD_OPC_CheckPredicate, 0, 168, 1, 0, // Skip to: 8345 -/* 7921 */ MCD_OPC_Decode, 184, 21, 80, // Opcode: sysLDMDB -/* 7925 */ MCD_OPC_FilterValue, 22, 34, 0, 0, // Skip to: 7964 -/* 7930 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7955 -/* 7935 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7955 -/* 7942 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7955 -/* 7951 */ MCD_OPC_Decode, 175, 6, 83, // Opcode: SRSDB_UPD -/* 7955 */ MCD_OPC_CheckPredicate, 0, 129, 1, 0, // Skip to: 8345 -/* 7960 */ MCD_OPC_Decode, 193, 21, 82, // Opcode: sysSTMDB_UPD -/* 7964 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 7978 -/* 7969 */ MCD_OPC_CheckPredicate, 0, 115, 1, 0, // Skip to: 8345 -/* 7974 */ MCD_OPC_Decode, 185, 21, 82, // Opcode: sysLDMDB_UPD -/* 7978 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 7992 -/* 7983 */ MCD_OPC_CheckPredicate, 0, 101, 1, 0, // Skip to: 8345 -/* 7988 */ MCD_OPC_Decode, 214, 6, 80, // Opcode: STMIB -/* 7992 */ MCD_OPC_FilterValue, 25, 33, 0, 0, // Skip to: 8030 -/* 7997 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8021 -/* 8002 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8021 -/* 8009 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8021 -/* 8017 */ MCD_OPC_Decode, 225, 5, 81, // Opcode: RFEIB -/* 8021 */ MCD_OPC_CheckPredicate, 0, 63, 1, 0, // Skip to: 8345 -/* 8026 */ MCD_OPC_Decode, 251, 4, 80, // Opcode: LDMIB -/* 8030 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 8044 -/* 8035 */ MCD_OPC_CheckPredicate, 0, 49, 1, 0, // Skip to: 8345 -/* 8040 */ MCD_OPC_Decode, 215, 6, 82, // Opcode: STMIB_UPD -/* 8044 */ MCD_OPC_FilterValue, 27, 33, 0, 0, // Skip to: 8082 -/* 8049 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8073 -/* 8054 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8073 -/* 8061 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8073 -/* 8069 */ MCD_OPC_Decode, 226, 5, 81, // Opcode: RFEIB_UPD -/* 8073 */ MCD_OPC_CheckPredicate, 0, 11, 1, 0, // Skip to: 8345 -/* 8078 */ MCD_OPC_Decode, 252, 4, 82, // Opcode: LDMIB_UPD -/* 8082 */ MCD_OPC_FilterValue, 28, 34, 0, 0, // Skip to: 8121 -/* 8087 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8112 -/* 8092 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8112 -/* 8099 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8112 -/* 8108 */ MCD_OPC_Decode, 178, 6, 83, // Opcode: SRSIB -/* 8112 */ MCD_OPC_CheckPredicate, 0, 228, 0, 0, // Skip to: 8345 -/* 8117 */ MCD_OPC_Decode, 196, 21, 80, // Opcode: sysSTMIB -/* 8121 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 8135 -/* 8126 */ MCD_OPC_CheckPredicate, 0, 214, 0, 0, // Skip to: 8345 -/* 8131 */ MCD_OPC_Decode, 188, 21, 80, // Opcode: sysLDMIB -/* 8135 */ MCD_OPC_FilterValue, 30, 34, 0, 0, // Skip to: 8174 -/* 8140 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8165 -/* 8145 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8165 -/* 8152 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8165 -/* 8161 */ MCD_OPC_Decode, 179, 6, 83, // Opcode: SRSIB_UPD -/* 8165 */ MCD_OPC_CheckPredicate, 0, 175, 0, 0, // Skip to: 8345 -/* 8170 */ MCD_OPC_Decode, 197, 21, 82, // Opcode: sysSTMIB_UPD -/* 8174 */ MCD_OPC_FilterValue, 31, 166, 0, 0, // Skip to: 8345 -/* 8179 */ MCD_OPC_CheckPredicate, 0, 161, 0, 0, // Skip to: 8345 -/* 8184 */ MCD_OPC_Decode, 189, 21, 82, // Opcode: sysLDMIB_UPD -/* 8188 */ MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 8256 -/* 8193 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 8196 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8210 -/* 8201 */ MCD_OPC_CheckPredicate, 0, 34, 0, 0, // Skip to: 8240 -/* 8206 */ MCD_OPC_Decode, 178, 4, 84, // Opcode: Bcc -/* 8210 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 8240 -/* 8215 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8231 -/* 8220 */ MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 8231 -/* 8227 */ MCD_OPC_Decode, 169, 4, 84, // Opcode: BL -/* 8231 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 8240 -/* 8236 */ MCD_OPC_Decode, 173, 4, 84, // Opcode: BL_pred -/* 8240 */ MCD_OPC_CheckPredicate, 11, 100, 0, 0, // Skip to: 8345 -/* 8245 */ MCD_OPC_CheckField, 28, 4, 15, 93, 0, 0, // Skip to: 8345 -/* 8252 */ MCD_OPC_Decode, 172, 4, 85, // Opcode: BLXi -/* 8256 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 8324 -/* 8261 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 8264 */ MCD_OPC_FilterValue, 4, 25, 0, 0, // Skip to: 8294 -/* 8269 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8285 -/* 8274 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8285 -/* 8281 */ MCD_OPC_Decode, 167, 5, 86, // Opcode: MCRR2 -/* 8285 */ MCD_OPC_CheckPredicate, 0, 55, 0, 0, // Skip to: 8345 -/* 8290 */ MCD_OPC_Decode, 166, 5, 87, // Opcode: MCRR -/* 8294 */ MCD_OPC_FilterValue, 5, 46, 0, 0, // Skip to: 8345 -/* 8299 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8315 -/* 8304 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8315 -/* 8311 */ MCD_OPC_Decode, 181, 5, 86, // Opcode: MRRC2 -/* 8315 */ MCD_OPC_CheckPredicate, 0, 25, 0, 0, // Skip to: 8345 -/* 8320 */ MCD_OPC_Decode, 180, 5, 88, // Opcode: MRRC -/* 8324 */ MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 8345 -/* 8329 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8345 -/* 8334 */ MCD_OPC_CheckField, 24, 1, 1, 4, 0, 0, // Skip to: 8345 -/* 8341 */ MCD_OPC_Decode, 248, 6, 89, // Opcode: SVC -/* 8345 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 25, + 3, // Inst{27-25} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 47, + 14, + 0, // Skip to: 3639 + /* 8 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 110, + 7, + 0, // Skip to: 1918 + /* 16 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 139, + 1, + 0, // Skip to: 419 + /* 24 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 27 */ MCD_OPC_FilterValue, + 0, + 123, + 0, + 0, // Skip to: 155 + /* 32 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 35 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 65 + /* 40 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 56 + /* 45 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 56 + /* 52 */ MCD_OPC_Decode, + 189, + 5, + 0, // Opcode: ANDrr + /* 56 */ MCD_OPC_CheckPredicate, + 0, + 128, + 32, + 0, // Skip to: 8381 + /* 61 */ MCD_OPC_Decode, + 190, + 5, + 1, // Opcode: ANDrsi + /* 65 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 95 + /* 70 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 86 + /* 75 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 86 + /* 82 */ MCD_OPC_Decode, + 144, + 15, + 0, // Opcode: SUBrr + /* 86 */ MCD_OPC_CheckPredicate, + 0, + 98, + 32, + 0, // Skip to: 8381 + /* 91 */ MCD_OPC_Decode, + 145, + 15, + 1, // Opcode: SUBrsi + /* 95 */ MCD_OPC_FilterValue, + 2, + 25, + 0, + 0, // Skip to: 125 + /* 100 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 116 + /* 105 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 116 + /* 112 */ MCD_OPC_Decode, + 180, + 5, + 0, // Opcode: ADDrr + /* 116 */ MCD_OPC_CheckPredicate, + 0, + 68, + 32, + 0, // Skip to: 8381 + /* 121 */ MCD_OPC_Decode, + 181, + 5, + 1, // Opcode: ADDrsi + /* 125 */ MCD_OPC_FilterValue, + 3, + 59, + 32, + 0, // Skip to: 8381 + /* 130 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 146 + /* 135 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 146 + /* 142 */ MCD_OPC_Decode, + 138, + 14, + 0, // Opcode: SBCrr + /* 146 */ MCD_OPC_CheckPredicate, + 0, + 38, + 32, + 0, // Skip to: 8381 + /* 151 */ MCD_OPC_Decode, + 139, + 14, + 1, // Opcode: SBCrsi + /* 155 */ MCD_OPC_FilterValue, + 1, + 29, + 32, + 0, // Skip to: 8381 + /* 160 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 163 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 227 + /* 168 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 171 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 185 + /* 176 */ MCD_OPC_CheckPredicate, + 0, + 8, + 32, + 0, // Skip to: 8381 + /* 181 */ MCD_OPC_Decode, + 191, + 5, + 2, // Opcode: ANDrsr + /* 185 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 199 + /* 190 */ MCD_OPC_CheckPredicate, + 0, + 250, + 31, + 0, // Skip to: 8381 + /* 195 */ MCD_OPC_Decode, + 146, + 15, + 2, // Opcode: SUBrsr + /* 199 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 213 + /* 204 */ MCD_OPC_CheckPredicate, + 0, + 236, + 31, + 0, // Skip to: 8381 + /* 209 */ MCD_OPC_Decode, + 182, + 5, + 2, // Opcode: ADDrsr + /* 213 */ MCD_OPC_FilterValue, + 3, + 227, + 31, + 0, // Skip to: 8381 + /* 218 */ MCD_OPC_CheckPredicate, + 0, + 222, + 31, + 0, // Skip to: 8381 + /* 223 */ MCD_OPC_Decode, + 140, + 14, + 3, // Opcode: SBCrsr + /* 227 */ MCD_OPC_FilterValue, + 1, + 213, + 31, + 0, // Skip to: 8381 + /* 232 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 235 */ MCD_OPC_FilterValue, + 0, + 71, + 0, + 0, // Skip to: 311 + /* 240 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 243 */ MCD_OPC_FilterValue, + 0, + 14, + 0, + 0, // Skip to: 262 + /* 248 */ MCD_OPC_CheckPredicate, + 1, + 192, + 31, + 0, // Skip to: 8381 + /* 253 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 258 */ MCD_OPC_Decode, + 255, + 6, + 4, // Opcode: MUL + /* 262 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 283 + /* 267 */ MCD_OPC_CheckPredicate, + 1, + 173, + 31, + 0, // Skip to: 8381 + /* 272 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 166, + 31, + 0, // Skip to: 8381 + /* 279 */ MCD_OPC_Decode, + 179, + 15, + 5, // Opcode: UMAAL + /* 283 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 297 + /* 288 */ MCD_OPC_CheckPredicate, + 1, + 152, + 31, + 0, // Skip to: 8381 + /* 293 */ MCD_OPC_Decode, + 181, + 15, + 6, // Opcode: UMULL + /* 297 */ MCD_OPC_FilterValue, + 3, + 143, + 31, + 0, // Skip to: 8381 + /* 302 */ MCD_OPC_CheckPredicate, + 1, + 138, + 31, + 0, // Skip to: 8381 + /* 307 */ MCD_OPC_Decode, + 192, + 14, + 6, // Opcode: SMULL + /* 311 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 347 + /* 316 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 319 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 333 + /* 324 */ MCD_OPC_CheckPredicate, + 0, + 116, + 31, + 0, // Skip to: 8381 + /* 329 */ MCD_OPC_Decode, + 133, + 15, + 7, // Opcode: STRH_POST + /* 333 */ MCD_OPC_FilterValue, + 1, + 107, + 31, + 0, // Skip to: 8381 + /* 338 */ MCD_OPC_CheckPredicate, + 0, + 102, + 31, + 0, // Skip to: 8381 + /* 343 */ MCD_OPC_Decode, + 210, + 6, + 7, // Opcode: LDRH_POST + /* 347 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 383 + /* 352 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 355 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 369 + /* 360 */ MCD_OPC_CheckPredicate, + 0, + 80, + 31, + 0, // Skip to: 8381 + /* 365 */ MCD_OPC_Decode, + 201, + 6, + 7, // Opcode: LDRD_POST + /* 369 */ MCD_OPC_FilterValue, + 1, + 71, + 31, + 0, // Skip to: 8381 + /* 374 */ MCD_OPC_CheckPredicate, + 0, + 66, + 31, + 0, // Skip to: 8381 + /* 379 */ MCD_OPC_Decode, + 215, + 6, + 7, // Opcode: LDRSB_POST + /* 383 */ MCD_OPC_FilterValue, + 3, + 57, + 31, + 0, // Skip to: 8381 + /* 388 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 391 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 405 + /* 396 */ MCD_OPC_CheckPredicate, + 0, + 44, + 31, + 0, // Skip to: 8381 + /* 401 */ MCD_OPC_Decode, + 252, + 14, + 7, // Opcode: STRD_POST + /* 405 */ MCD_OPC_FilterValue, + 1, + 35, + 31, + 0, // Skip to: 8381 + /* 410 */ MCD_OPC_CheckPredicate, + 0, + 30, + 31, + 0, // Skip to: 8381 + /* 415 */ MCD_OPC_Decode, + 220, + 6, + 7, // Opcode: LDRSH_POST + /* 419 */ MCD_OPC_FilterValue, + 1, + 21, + 31, + 0, // Skip to: 8381 + /* 424 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 427 */ MCD_OPC_FilterValue, + 0, + 6, + 2, + 0, // Skip to: 950 + /* 432 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 435 */ MCD_OPC_FilterValue, + 0, + 152, + 1, + 0, // Skip to: 848 + /* 440 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 443 */ MCD_OPC_FilterValue, + 0, + 66, + 1, + 0, // Skip to: 770 + /* 448 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 451 */ MCD_OPC_FilterValue, + 14, + 67, + 0, + 0, // Skip to: 523 + /* 456 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 459 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 491 + /* 464 */ MCD_OPC_CheckPredicate, + 2, + 171, + 0, + 0, // Skip to: 640 + /* 469 */ MCD_OPC_CheckField, + 6, + 2, + 1, + 164, + 0, + 0, // Skip to: 640 + /* 476 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 0, + 0, // Skip to: 640 + /* 483 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 487 */ MCD_OPC_Decode, + 133, + 6, + 8, // Opcode: CRC32B + /* 491 */ MCD_OPC_FilterValue, + 1, + 144, + 0, + 0, // Skip to: 640 + /* 496 */ MCD_OPC_CheckPredicate, + 2, + 139, + 0, + 0, // Skip to: 640 + /* 501 */ MCD_OPC_CheckField, + 6, + 2, + 1, + 132, + 0, + 0, // Skip to: 640 + /* 508 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 125, + 0, + 0, // Skip to: 640 + /* 515 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 519 */ MCD_OPC_Decode, + 134, + 6, + 8, // Opcode: CRC32CB + /* 523 */ MCD_OPC_FilterValue, + 15, + 112, + 0, + 0, // Skip to: 640 + /* 528 */ MCD_OPC_ExtractField, + 10, + 8, // Inst{17-10} ... + /* 531 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 559 + /* 536 */ MCD_OPC_CheckPredicate, + 0, + 99, + 0, + 0, // Skip to: 640 + /* 541 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 92, + 0, + 0, // Skip to: 640 + /* 548 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 85, + 0, + 0, // Skip to: 640 + /* 555 */ MCD_OPC_Decode, + 131, + 6, + 9, // Opcode: CPS2p + /* 559 */ MCD_OPC_FilterValue, + 64, + 30, + 0, + 0, // Skip to: 594 + /* 564 */ MCD_OPC_CheckPredicate, + 0, + 71, + 0, + 0, // Skip to: 640 + /* 569 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 64, + 0, + 0, // Skip to: 640 + /* 576 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 57, + 0, + 0, // Skip to: 640 + /* 583 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 50, + 0, + 0, // Skip to: 640 + /* 590 */ MCD_OPC_Decode, + 144, + 14, + 10, // Opcode: SETEND + /* 594 */ MCD_OPC_FilterValue, + 128, + 1, + 40, + 0, + 0, // Skip to: 640 + /* 600 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 603 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 640 + /* 608 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 631 + /* 613 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 11, + 0, + 0, // Skip to: 631 + /* 620 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 4, + 0, + 0, // Skip to: 631 + /* 627 */ MCD_OPC_Decode, + 130, + 6, + 9, // Opcode: CPS1p + /* 631 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 640 + /* 636 */ MCD_OPC_Decode, + 132, + 6, + 9, // Opcode: CPS3p + /* 640 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 643 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 684 + /* 648 */ MCD_OPC_CheckPredicate, + 0, + 88, + 4, + 0, // Skip to: 1765 + /* 653 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 81, + 4, + 0, // Skip to: 1765 + /* 660 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 74, + 4, + 0, // Skip to: 1765 + /* 667 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 67, + 4, + 0, // Skip to: 1765 + /* 674 */ MCD_OPC_SoftFail, + 143, + 26 /* 0xd0f */, + 128, + 128, + 56 /* 0xe0000 */, + /* 680 */ MCD_OPC_Decode, + 249, + 6, + 11, // Opcode: MRS + /* 684 */ MCD_OPC_FilterValue, + 1, + 20, + 0, + 0, // Skip to: 709 + /* 689 */ MCD_OPC_CheckPredicate, + 0, + 47, + 4, + 0, // Skip to: 1765 + /* 694 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 40, + 4, + 0, // Skip to: 1765 + /* 701 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 705 */ MCD_OPC_Decode, + 231, + 13, + 12, // Opcode: QADD + /* 709 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 749 + /* 714 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 717 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 731 + /* 722 */ MCD_OPC_CheckPredicate, + 3, + 14, + 4, + 0, // Skip to: 1765 + /* 727 */ MCD_OPC_Decode, + 163, + 14, + 13, // Opcode: SMLABB + /* 731 */ MCD_OPC_FilterValue, + 1, + 5, + 4, + 0, // Skip to: 1765 + /* 736 */ MCD_OPC_CheckPredicate, + 4, + 0, + 4, + 0, // Skip to: 1765 + /* 741 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 745 */ MCD_OPC_Decode, + 148, + 15, + 14, // Opcode: SWP + /* 749 */ MCD_OPC_FilterValue, + 3, + 243, + 3, + 0, // Skip to: 1765 + /* 754 */ MCD_OPC_CheckPredicate, + 3, + 238, + 3, + 0, // Skip to: 1765 + /* 759 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 231, + 3, + 0, // Skip to: 1765 + /* 766 */ MCD_OPC_Decode, + 164, + 14, + 13, // Opcode: SMLABT + /* 770 */ MCD_OPC_FilterValue, + 1, + 222, + 3, + 0, // Skip to: 1765 + /* 775 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 778 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 806 + /* 783 */ MCD_OPC_CheckPredicate, + 5, + 209, + 3, + 0, // Skip to: 1765 + /* 788 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 202, + 3, + 0, // Skip to: 1765 + /* 795 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 195, + 3, + 0, // Skip to: 1765 + /* 802 */ MCD_OPC_Decode, + 158, + 6, + 15, // Opcode: HLT + /* 806 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 827 + /* 811 */ MCD_OPC_CheckPredicate, + 3, + 181, + 3, + 0, // Skip to: 1765 + /* 816 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 174, + 3, + 0, // Skip to: 1765 + /* 823 */ MCD_OPC_Decode, + 174, + 14, + 13, // Opcode: SMLATB + /* 827 */ MCD_OPC_FilterValue, + 3, + 165, + 3, + 0, // Skip to: 1765 + /* 832 */ MCD_OPC_CheckPredicate, + 3, + 160, + 3, + 0, // Skip to: 1765 + /* 837 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 153, + 3, + 0, // Skip to: 1765 + /* 844 */ MCD_OPC_Decode, + 175, + 14, + 13, // Opcode: SMLATT + /* 848 */ MCD_OPC_FilterValue, + 1, + 144, + 3, + 0, // Skip to: 1765 + /* 853 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 856 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 924 + /* 861 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 882 + /* 866 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 882 + /* 873 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 878 */ MCD_OPC_Decode, + 164, + 15, + 16, // Opcode: TSTrr + /* 882 */ MCD_OPC_CheckPredicate, + 6, + 23, + 0, + 0, // Skip to: 910 + /* 887 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 16, + 0, + 0, // Skip to: 910 + /* 894 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 9, + 0, + 0, // Skip to: 910 + /* 901 */ MCD_OPC_SoftFail, + 143, + 250, + 63 /* 0xffd0f */, + 0, + /* 906 */ MCD_OPC_Decode, + 145, + 14, + 10, // Opcode: SETPAN + /* 910 */ MCD_OPC_CheckPredicate, + 0, + 82, + 3, + 0, // Skip to: 1765 + /* 915 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 920 */ MCD_OPC_Decode, + 165, + 15, + 17, // Opcode: TSTrsi + /* 924 */ MCD_OPC_FilterValue, + 1, + 68, + 3, + 0, // Skip to: 1765 + /* 929 */ MCD_OPC_CheckPredicate, + 0, + 63, + 3, + 0, // Skip to: 1765 + /* 934 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 56, + 3, + 0, // Skip to: 1765 + /* 941 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 946 */ MCD_OPC_Decode, + 166, + 15, + 18, // Opcode: TSTrsr + /* 950 */ MCD_OPC_FilterValue, + 1, + 62, + 1, + 0, // Skip to: 1273 + /* 955 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 958 */ MCD_OPC_FilterValue, + 0, + 192, + 0, + 0, // Skip to: 1155 + /* 963 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 966 */ MCD_OPC_FilterValue, + 0, + 144, + 0, + 0, // Skip to: 1115 + /* 971 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 974 */ MCD_OPC_FilterValue, + 0, + 22, + 0, + 0, // Skip to: 1001 + /* 979 */ MCD_OPC_CheckPredicate, + 0, + 13, + 3, + 0, // Skip to: 1765 + /* 984 */ MCD_OPC_CheckField, + 9, + 1, + 0, + 6, + 3, + 0, // Skip to: 1765 + /* 991 */ MCD_OPC_SoftFail, + 143, + 26 /* 0xd0f */, + 128, + 128, + 60 /* 0xf0000 */, + /* 997 */ MCD_OPC_Decode, + 251, + 6, + 11, // Opcode: MRSsys + /* 1001 */ MCD_OPC_FilterValue, + 2, + 53, + 0, + 0, // Skip to: 1059 + /* 1006 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 1009 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 1034 + /* 1014 */ MCD_OPC_CheckPredicate, + 2, + 234, + 2, + 0, // Skip to: 1765 + /* 1019 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 227, + 2, + 0, // Skip to: 1765 + /* 1026 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 1030 */ MCD_OPC_Decode, + 138, + 6, + 8, // Opcode: CRC32W + /* 1034 */ MCD_OPC_FilterValue, + 1, + 214, + 2, + 0, // Skip to: 1765 + /* 1039 */ MCD_OPC_CheckPredicate, + 2, + 209, + 2, + 0, // Skip to: 1765 + /* 1044 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 202, + 2, + 0, // Skip to: 1765 + /* 1051 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 1055 */ MCD_OPC_Decode, + 136, + 6, + 8, // Opcode: CRC32CW + /* 1059 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1073 + /* 1064 */ MCD_OPC_CheckPredicate, + 3, + 184, + 2, + 0, // Skip to: 1765 + /* 1069 */ MCD_OPC_Decode, + 168, + 14, + 19, // Opcode: SMLALBB + /* 1073 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 1087 + /* 1078 */ MCD_OPC_CheckPredicate, + 3, + 170, + 2, + 0, // Skip to: 1765 + /* 1083 */ MCD_OPC_Decode, + 172, + 14, + 19, // Opcode: SMLALTB + /* 1087 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1101 + /* 1092 */ MCD_OPC_CheckPredicate, + 3, + 156, + 2, + 0, // Skip to: 1765 + /* 1097 */ MCD_OPC_Decode, + 169, + 14, + 19, // Opcode: SMLALBT + /* 1101 */ MCD_OPC_FilterValue, + 7, + 147, + 2, + 0, // Skip to: 1765 + /* 1106 */ MCD_OPC_CheckPredicate, + 3, + 142, + 2, + 0, // Skip to: 1765 + /* 1111 */ MCD_OPC_Decode, + 173, + 14, + 19, // Opcode: SMLALTT + /* 1115 */ MCD_OPC_FilterValue, + 1, + 133, + 2, + 0, // Skip to: 1765 + /* 1120 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 1141 + /* 1125 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 1141 + /* 1132 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 1137 */ MCD_OPC_Decode, + 255, + 5, + 20, // Opcode: CMPrr + /* 1141 */ MCD_OPC_CheckPredicate, + 0, + 107, + 2, + 0, // Skip to: 1765 + /* 1146 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 1151 */ MCD_OPC_Decode, + 128, + 6, + 17, // Opcode: CMPrsi + /* 1155 */ MCD_OPC_FilterValue, + 1, + 93, + 2, + 0, // Skip to: 1765 + /* 1160 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1163 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 1241 + /* 1168 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1171 */ MCD_OPC_FilterValue, + 0, + 46, + 0, + 0, // Skip to: 1222 + /* 1176 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 1179 */ MCD_OPC_FilterValue, + 2, + 13, + 0, + 0, // Skip to: 1197 + /* 1184 */ MCD_OPC_CheckPredicate, + 0, + 64, + 2, + 0, // Skip to: 1765 + /* 1189 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 1193 */ MCD_OPC_Decode, + 235, + 13, + 21, // Opcode: QDADD + /* 1197 */ MCD_OPC_FilterValue, + 3, + 51, + 2, + 0, // Skip to: 1765 + /* 1202 */ MCD_OPC_CheckPredicate, + 7, + 46, + 2, + 0, // Skip to: 1765 + /* 1207 */ MCD_OPC_SoftFail, + 128, + 128, + 128, + 128, + 1 /* 0x10000000 */, + 128, + 128, + 128, + 128, + 14 /* 0xffffffffe0000000 */, + /* 1218 */ MCD_OPC_Decode, + 159, + 6, + 15, // Opcode: HVC + /* 1222 */ MCD_OPC_FilterValue, + 1, + 26, + 2, + 0, // Skip to: 1765 + /* 1227 */ MCD_OPC_CheckPredicate, + 0, + 21, + 2, + 0, // Skip to: 1765 + /* 1232 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 1237 */ MCD_OPC_Decode, + 129, + 6, + 18, // Opcode: CMPrsr + /* 1241 */ MCD_OPC_FilterValue, + 1, + 7, + 2, + 0, // Skip to: 1765 + /* 1246 */ MCD_OPC_CheckPredicate, + 4, + 2, + 2, + 0, // Skip to: 1765 + /* 1251 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 251, + 1, + 0, // Skip to: 1765 + /* 1258 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 244, + 1, + 0, // Skip to: 1765 + /* 1265 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 1269 */ MCD_OPC_Decode, + 149, + 15, + 14, // Opcode: SWPB + /* 1273 */ MCD_OPC_FilterValue, + 2, + 241, + 0, + 0, // Skip to: 1519 + /* 1278 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1281 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1311 + /* 1286 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 1302 + /* 1291 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 1302 + /* 1298 */ MCD_OPC_Decode, + 220, + 13, + 0, // Opcode: ORRrr + /* 1302 */ MCD_OPC_CheckPredicate, + 0, + 202, + 1, + 0, // Skip to: 1765 + /* 1307 */ MCD_OPC_Decode, + 221, + 13, + 1, // Opcode: ORRrsi + /* 1311 */ MCD_OPC_FilterValue, + 1, + 193, + 1, + 0, // Skip to: 1765 + /* 1316 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1319 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1333 + /* 1324 */ MCD_OPC_CheckPredicate, + 0, + 180, + 1, + 0, // Skip to: 1765 + /* 1329 */ MCD_OPC_Decode, + 222, + 13, + 2, // Opcode: ORRrsr + /* 1333 */ MCD_OPC_FilterValue, + 1, + 171, + 1, + 0, // Skip to: 1765 + /* 1338 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 1341 */ MCD_OPC_FilterValue, + 12, + 59, + 0, + 0, // Skip to: 1405 + /* 1346 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1349 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 1377 + /* 1354 */ MCD_OPC_CheckPredicate, + 8, + 150, + 1, + 0, // Skip to: 1765 + /* 1359 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 143, + 1, + 0, // Skip to: 1765 + /* 1366 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 136, + 1, + 0, // Skip to: 1765 + /* 1373 */ MCD_OPC_Decode, + 228, + 14, + 22, // Opcode: STL + /* 1377 */ MCD_OPC_FilterValue, + 1, + 127, + 1, + 0, // Skip to: 1765 + /* 1382 */ MCD_OPC_CheckPredicate, + 8, + 122, + 1, + 0, // Skip to: 1765 + /* 1387 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 115, + 1, + 0, // Skip to: 1765 + /* 1394 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 108, + 1, + 0, // Skip to: 1765 + /* 1401 */ MCD_OPC_Decode, + 161, + 6, + 23, // Opcode: LDA + /* 1405 */ MCD_OPC_FilterValue, + 14, + 52, + 0, + 0, // Skip to: 1462 + /* 1410 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1413 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1434 + /* 1418 */ MCD_OPC_CheckPredicate, + 9, + 86, + 1, + 0, // Skip to: 1765 + /* 1423 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 79, + 1, + 0, // Skip to: 1765 + /* 1430 */ MCD_OPC_Decode, + 230, + 14, + 24, // Opcode: STLEX + /* 1434 */ MCD_OPC_FilterValue, + 1, + 70, + 1, + 0, // Skip to: 1765 + /* 1439 */ MCD_OPC_CheckPredicate, + 9, + 65, + 1, + 0, // Skip to: 1765 + /* 1444 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 58, + 1, + 0, // Skip to: 1765 + /* 1451 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 51, + 1, + 0, // Skip to: 1765 + /* 1458 */ MCD_OPC_Decode, + 163, + 6, + 23, // Opcode: LDAEX + /* 1462 */ MCD_OPC_FilterValue, + 15, + 42, + 1, + 0, // Skip to: 1765 + /* 1467 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1470 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1491 + /* 1475 */ MCD_OPC_CheckPredicate, + 0, + 29, + 1, + 0, // Skip to: 1765 + /* 1480 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 22, + 1, + 0, // Skip to: 1765 + /* 1487 */ MCD_OPC_Decode, + 254, + 14, + 24, // Opcode: STREX + /* 1491 */ MCD_OPC_FilterValue, + 1, + 13, + 1, + 0, // Skip to: 1765 + /* 1496 */ MCD_OPC_CheckPredicate, + 0, + 8, + 1, + 0, // Skip to: 1765 + /* 1501 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 1, + 1, + 0, // Skip to: 1765 + /* 1508 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 250, + 0, + 0, // Skip to: 1765 + /* 1515 */ MCD_OPC_Decode, + 203, + 6, + 23, // Opcode: LDREX + /* 1519 */ MCD_OPC_FilterValue, + 3, + 241, + 0, + 0, // Skip to: 1765 + /* 1524 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1527 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1557 + /* 1532 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 1548 + /* 1537 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 1548 + /* 1544 */ MCD_OPC_Decode, + 202, + 5, + 0, // Opcode: BICrr + /* 1548 */ MCD_OPC_CheckPredicate, + 0, + 212, + 0, + 0, // Skip to: 1765 + /* 1553 */ MCD_OPC_Decode, + 203, + 5, + 1, // Opcode: BICrsi + /* 1557 */ MCD_OPC_FilterValue, + 1, + 203, + 0, + 0, // Skip to: 1765 + /* 1562 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1565 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1579 + /* 1570 */ MCD_OPC_CheckPredicate, + 0, + 190, + 0, + 0, // Skip to: 1765 + /* 1575 */ MCD_OPC_Decode, + 204, + 5, + 2, // Opcode: BICrsr + /* 1579 */ MCD_OPC_FilterValue, + 1, + 181, + 0, + 0, // Skip to: 1765 + /* 1584 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 1587 */ MCD_OPC_FilterValue, + 12, + 59, + 0, + 0, // Skip to: 1651 + /* 1592 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1595 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 1623 + /* 1600 */ MCD_OPC_CheckPredicate, + 8, + 160, + 0, + 0, // Skip to: 1765 + /* 1605 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 153, + 0, + 0, // Skip to: 1765 + /* 1612 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 146, + 0, + 0, // Skip to: 1765 + /* 1619 */ MCD_OPC_Decode, + 229, + 14, + 22, // Opcode: STLB + /* 1623 */ MCD_OPC_FilterValue, + 1, + 137, + 0, + 0, // Skip to: 1765 + /* 1628 */ MCD_OPC_CheckPredicate, + 8, + 132, + 0, + 0, // Skip to: 1765 + /* 1633 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 125, + 0, + 0, // Skip to: 1765 + /* 1640 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 118, + 0, + 0, // Skip to: 1765 + /* 1647 */ MCD_OPC_Decode, + 162, + 6, + 23, // Opcode: LDAB + /* 1651 */ MCD_OPC_FilterValue, + 14, + 52, + 0, + 0, // Skip to: 1708 + /* 1656 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1659 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1680 + /* 1664 */ MCD_OPC_CheckPredicate, + 9, + 96, + 0, + 0, // Skip to: 1765 + /* 1669 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 89, + 0, + 0, // Skip to: 1765 + /* 1676 */ MCD_OPC_Decode, + 231, + 14, + 24, // Opcode: STLEXB + /* 1680 */ MCD_OPC_FilterValue, + 1, + 80, + 0, + 0, // Skip to: 1765 + /* 1685 */ MCD_OPC_CheckPredicate, + 9, + 75, + 0, + 0, // Skip to: 1765 + /* 1690 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 68, + 0, + 0, // Skip to: 1765 + /* 1697 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 61, + 0, + 0, // Skip to: 1765 + /* 1704 */ MCD_OPC_Decode, + 164, + 6, + 23, // Opcode: LDAEXB + /* 1708 */ MCD_OPC_FilterValue, + 15, + 52, + 0, + 0, // Skip to: 1765 + /* 1713 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1716 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1737 + /* 1721 */ MCD_OPC_CheckPredicate, + 0, + 39, + 0, + 0, // Skip to: 1765 + /* 1726 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 32, + 0, + 0, // Skip to: 1765 + /* 1733 */ MCD_OPC_Decode, + 255, + 14, + 24, // Opcode: STREXB + /* 1737 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 1765 + /* 1742 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 1765 + /* 1747 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 11, + 0, + 0, // Skip to: 1765 + /* 1754 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 4, + 0, + 0, // Skip to: 1765 + /* 1761 */ MCD_OPC_Decode, + 204, + 6, + 23, // Opcode: LDREXB + /* 1765 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 1768 */ MCD_OPC_FilterValue, + 0, + 37, + 0, + 0, // Skip to: 1810 + /* 1773 */ MCD_OPC_CheckPredicate, + 7, + 203, + 25, + 0, // Skip to: 8381 + /* 1778 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 196, + 25, + 0, // Skip to: 8381 + /* 1785 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 189, + 25, + 0, // Skip to: 8381 + /* 1792 */ MCD_OPC_CheckField, + 9, + 3, + 1, + 182, + 25, + 0, // Skip to: 8381 + /* 1799 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 175, + 25, + 0, // Skip to: 8381 + /* 1806 */ MCD_OPC_Decode, + 250, + 6, + 25, // Opcode: MRSbanked + /* 1810 */ MCD_OPC_FilterValue, + 11, + 31, + 0, + 0, // Skip to: 1846 + /* 1815 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1818 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1832 + /* 1823 */ MCD_OPC_CheckPredicate, + 0, + 153, + 25, + 0, // Skip to: 8381 + /* 1828 */ MCD_OPC_Decode, + 130, + 15, + 7, // Opcode: STRH + /* 1832 */ MCD_OPC_FilterValue, + 1, + 144, + 25, + 0, // Skip to: 8381 + /* 1837 */ MCD_OPC_CheckPredicate, + 0, + 139, + 25, + 0, // Skip to: 8381 + /* 1842 */ MCD_OPC_Decode, + 207, + 6, + 7, // Opcode: LDRH + /* 1846 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 1882 + /* 1851 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1854 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1868 + /* 1859 */ MCD_OPC_CheckPredicate, + 3, + 117, + 25, + 0, // Skip to: 8381 + /* 1864 */ MCD_OPC_Decode, + 200, + 6, + 7, // Opcode: LDRD + /* 1868 */ MCD_OPC_FilterValue, + 1, + 108, + 25, + 0, // Skip to: 8381 + /* 1873 */ MCD_OPC_CheckPredicate, + 0, + 103, + 25, + 0, // Skip to: 8381 + /* 1878 */ MCD_OPC_Decode, + 212, + 6, + 7, // Opcode: LDRSB + /* 1882 */ MCD_OPC_FilterValue, + 15, + 94, + 25, + 0, // Skip to: 8381 + /* 1887 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1890 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1904 + /* 1895 */ MCD_OPC_CheckPredicate, + 3, + 81, + 25, + 0, // Skip to: 8381 + /* 1900 */ MCD_OPC_Decode, + 251, + 14, + 7, // Opcode: STRD + /* 1904 */ MCD_OPC_FilterValue, + 1, + 72, + 25, + 0, // Skip to: 8381 + /* 1909 */ MCD_OPC_CheckPredicate, + 0, + 67, + 25, + 0, // Skip to: 8381 + /* 1914 */ MCD_OPC_Decode, + 217, + 6, + 7, // Opcode: LDRSH + /* 1918 */ MCD_OPC_FilterValue, + 1, + 58, + 25, + 0, // Skip to: 8381 + /* 1923 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1926 */ MCD_OPC_FilterValue, + 0, + 180, + 2, + 0, // Skip to: 2623 + /* 1931 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 1934 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 2002 + /* 1939 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 1942 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1972 + /* 1947 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 1963 + /* 1952 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 1963 + /* 1959 */ MCD_OPC_Decode, + 143, + 6, + 0, // Opcode: EORrr + /* 1963 */ MCD_OPC_CheckPredicate, + 0, + 13, + 25, + 0, // Skip to: 8381 + /* 1968 */ MCD_OPC_Decode, + 144, + 6, + 1, // Opcode: EORrsi + /* 1972 */ MCD_OPC_FilterValue, + 1, + 4, + 25, + 0, // Skip to: 8381 + /* 1977 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 1993 + /* 1982 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 1993 + /* 1989 */ MCD_OPC_Decode, + 254, + 13, + 0, // Opcode: RSBrr + /* 1993 */ MCD_OPC_CheckPredicate, + 0, + 239, + 24, + 0, // Skip to: 8381 + /* 1998 */ MCD_OPC_Decode, + 255, + 13, + 1, // Opcode: RSBrsi + /* 2002 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 2070 + /* 2007 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2010 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2040 + /* 2015 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 2031 + /* 2020 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 2031 + /* 2027 */ MCD_OPC_Decode, + 176, + 5, + 0, // Opcode: ADCrr + /* 2031 */ MCD_OPC_CheckPredicate, + 0, + 201, + 24, + 0, // Skip to: 8381 + /* 2036 */ MCD_OPC_Decode, + 177, + 5, + 1, // Opcode: ADCrsi + /* 2040 */ MCD_OPC_FilterValue, + 1, + 192, + 24, + 0, // Skip to: 8381 + /* 2045 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 2061 + /* 2050 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 4, + 0, + 0, // Skip to: 2061 + /* 2057 */ MCD_OPC_Decode, + 130, + 14, + 0, // Opcode: RSCrr + /* 2061 */ MCD_OPC_CheckPredicate, + 0, + 171, + 24, + 0, // Skip to: 8381 + /* 2066 */ MCD_OPC_Decode, + 131, + 14, + 1, // Opcode: RSCrsi + /* 2070 */ MCD_OPC_FilterValue, + 2, + 166, + 1, + 0, // Skip to: 2497 + /* 2075 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2078 */ MCD_OPC_FilterValue, + 0, + 70, + 1, + 0, // Skip to: 2409 + /* 2083 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 2086 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 2129 + /* 2091 */ MCD_OPC_ExtractField, + 9, + 7, // Inst{15-9} ... + /* 2094 */ MCD_OPC_FilterValue, + 120, + 16, + 0, + 0, // Skip to: 2115 + /* 2099 */ MCD_OPC_CheckPredicate, + 0, + 133, + 24, + 0, // Skip to: 8381 + /* 2104 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 126, + 24, + 0, // Skip to: 8381 + /* 2111 */ MCD_OPC_Decode, + 252, + 6, + 26, // Opcode: MSR + /* 2115 */ MCD_OPC_FilterValue, + 121, + 117, + 24, + 0, // Skip to: 8381 + /* 2120 */ MCD_OPC_CheckPredicate, + 7, + 112, + 24, + 0, // Skip to: 8381 + /* 2125 */ MCD_OPC_Decode, + 253, + 6, + 27, // Opcode: MSRbanked + /* 2129 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 2158 + /* 2134 */ MCD_OPC_CheckPredicate, + 0, + 98, + 24, + 0, // Skip to: 8381 + /* 2139 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 91, + 24, + 0, // Skip to: 8381 + /* 2146 */ MCD_OPC_CheckField, + 8, + 12, + 255, + 31, + 83, + 24, + 0, // Skip to: 8381 + /* 2154 */ MCD_OPC_Decode, + 212, + 5, + 28, // Opcode: BXJ + /* 2158 */ MCD_OPC_FilterValue, + 2, + 67, + 0, + 0, // Skip to: 2230 + /* 2163 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 2166 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 2198 + /* 2171 */ MCD_OPC_CheckPredicate, + 2, + 61, + 24, + 0, // Skip to: 8381 + /* 2176 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 54, + 24, + 0, // Skip to: 8381 + /* 2183 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 47, + 24, + 0, // Skip to: 8381 + /* 2190 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 2194 */ MCD_OPC_Decode, + 137, + 6, + 8, // Opcode: CRC32H + /* 2198 */ MCD_OPC_FilterValue, + 1, + 34, + 24, + 0, // Skip to: 8381 + /* 2203 */ MCD_OPC_CheckPredicate, + 2, + 29, + 24, + 0, // Skip to: 8381 + /* 2208 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 22, + 24, + 0, // Skip to: 8381 + /* 2215 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 15, + 24, + 0, // Skip to: 8381 + /* 2222 */ MCD_OPC_SoftFail, + 128, + 26 /* 0xd00 */, + 0, + /* 2226 */ MCD_OPC_Decode, + 135, + 6, + 8, // Opcode: CRC32CH + /* 2230 */ MCD_OPC_FilterValue, + 3, + 30, + 0, + 0, // Skip to: 2265 + /* 2235 */ MCD_OPC_CheckPredicate, + 7, + 253, + 23, + 0, // Skip to: 8381 + /* 2240 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 246, + 23, + 0, // Skip to: 8381 + /* 2247 */ MCD_OPC_CheckField, + 8, + 12, + 0, + 239, + 23, + 0, // Skip to: 8381 + /* 2254 */ MCD_OPC_CheckField, + 0, + 4, + 14, + 232, + 23, + 0, // Skip to: 8381 + /* 2261 */ MCD_OPC_Decode, + 146, + 6, + 29, // Opcode: ERET + /* 2265 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 2301 + /* 2270 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2273 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2287 + /* 2278 */ MCD_OPC_CheckPredicate, + 3, + 210, + 23, + 0, // Skip to: 8381 + /* 2283 */ MCD_OPC_Decode, + 176, + 14, + 13, // Opcode: SMLAWB + /* 2287 */ MCD_OPC_FilterValue, + 1, + 201, + 23, + 0, // Skip to: 8381 + /* 2292 */ MCD_OPC_CheckPredicate, + 3, + 196, + 23, + 0, // Skip to: 8381 + /* 2297 */ MCD_OPC_Decode, + 190, + 14, + 30, // Opcode: SMULBB + /* 2301 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 2337 + /* 2306 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2309 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2323 + /* 2314 */ MCD_OPC_CheckPredicate, + 3, + 174, + 23, + 0, // Skip to: 8381 + /* 2319 */ MCD_OPC_Decode, + 195, + 14, + 30, // Opcode: SMULWB + /* 2323 */ MCD_OPC_FilterValue, + 1, + 165, + 23, + 0, // Skip to: 8381 + /* 2328 */ MCD_OPC_CheckPredicate, + 3, + 160, + 23, + 0, // Skip to: 8381 + /* 2333 */ MCD_OPC_Decode, + 193, + 14, + 30, // Opcode: SMULTB + /* 2337 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 2373 + /* 2342 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2345 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2359 + /* 2350 */ MCD_OPC_CheckPredicate, + 3, + 138, + 23, + 0, // Skip to: 8381 + /* 2355 */ MCD_OPC_Decode, + 177, + 14, + 13, // Opcode: SMLAWT + /* 2359 */ MCD_OPC_FilterValue, + 1, + 129, + 23, + 0, // Skip to: 8381 + /* 2364 */ MCD_OPC_CheckPredicate, + 3, + 124, + 23, + 0, // Skip to: 8381 + /* 2369 */ MCD_OPC_Decode, + 191, + 14, + 30, // Opcode: SMULBT + /* 2373 */ MCD_OPC_FilterValue, + 7, + 115, + 23, + 0, // Skip to: 8381 + /* 2378 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2381 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2395 + /* 2386 */ MCD_OPC_CheckPredicate, + 3, + 102, + 23, + 0, // Skip to: 8381 + /* 2391 */ MCD_OPC_Decode, + 196, + 14, + 30, // Opcode: SMULWT + /* 2395 */ MCD_OPC_FilterValue, + 1, + 93, + 23, + 0, // Skip to: 8381 + /* 2400 */ MCD_OPC_CheckPredicate, + 3, + 88, + 23, + 0, // Skip to: 8381 + /* 2405 */ MCD_OPC_Decode, + 194, + 14, + 30, // Opcode: SMULTT + /* 2409 */ MCD_OPC_FilterValue, + 1, + 79, + 23, + 0, // Skip to: 8381 + /* 2414 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2417 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 2457 + /* 2422 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 2443 + /* 2427 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 2443 + /* 2434 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2439 */ MCD_OPC_Decode, + 157, + 15, + 20, // Opcode: TEQrr + /* 2443 */ MCD_OPC_CheckPredicate, + 0, + 45, + 23, + 0, // Skip to: 8381 + /* 2448 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2453 */ MCD_OPC_Decode, + 158, + 15, + 17, // Opcode: TEQrsi + /* 2457 */ MCD_OPC_FilterValue, + 1, + 31, + 23, + 0, // Skip to: 8381 + /* 2462 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 2483 + /* 2467 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 2483 + /* 2474 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2479 */ MCD_OPC_Decode, + 251, + 5, + 20, // Opcode: CMNzrr + /* 2483 */ MCD_OPC_CheckPredicate, + 0, + 5, + 23, + 0, // Skip to: 8381 + /* 2488 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2493 */ MCD_OPC_Decode, + 252, + 5, + 17, // Opcode: CMNzrsi + /* 2497 */ MCD_OPC_FilterValue, + 3, + 247, + 22, + 0, // Skip to: 8381 + /* 2502 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2505 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 2583 + /* 2510 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 2534 + /* 2515 */ MCD_OPC_CheckField, + 5, + 16, + 128, + 15, + 11, + 0, + 0, // Skip to: 2534 + /* 2523 */ MCD_OPC_CheckField, + 0, + 4, + 14, + 4, + 0, + 0, // Skip to: 2534 + /* 2530 */ MCD_OPC_Decode, + 237, + 6, + 29, // Opcode: MOVPCLR + /* 2534 */ MCD_OPC_ExtractField, + 5, + 7, // Inst{11-5} ... + /* 2537 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2567 + /* 2542 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 2558 + /* 2547 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 4, + 0, + 0, // Skip to: 2558 + /* 2554 */ MCD_OPC_Decode, + 241, + 6, + 31, // Opcode: MOVr + /* 2558 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 2567 + /* 2563 */ MCD_OPC_Decode, + 242, + 6, + 32, // Opcode: MOVr_TC + /* 2567 */ MCD_OPC_CheckPredicate, + 0, + 177, + 22, + 0, // Skip to: 8381 + /* 2572 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 170, + 22, + 0, // Skip to: 8381 + /* 2579 */ MCD_OPC_Decode, + 243, + 6, + 33, // Opcode: MOVsi + /* 2583 */ MCD_OPC_FilterValue, + 1, + 161, + 22, + 0, // Skip to: 8381 + /* 2588 */ MCD_OPC_CheckPredicate, + 0, + 16, + 0, + 0, // Skip to: 2609 + /* 2593 */ MCD_OPC_CheckField, + 5, + 7, + 0, + 9, + 0, + 0, // Skip to: 2609 + /* 2600 */ MCD_OPC_SoftFail, + 128, + 128, + 60 /* 0xf0000 */, + 0, + /* 2605 */ MCD_OPC_Decode, + 208, + 13, + 31, // Opcode: MVNr + /* 2609 */ MCD_OPC_CheckPredicate, + 0, + 135, + 22, + 0, // Skip to: 8381 + /* 2614 */ MCD_OPC_SoftFail, + 128, + 128, + 60 /* 0xf0000 */, + 0, + /* 2619 */ MCD_OPC_Decode, + 209, + 13, + 33, // Opcode: MVNsi + /* 2623 */ MCD_OPC_FilterValue, + 1, + 121, + 22, + 0, // Skip to: 8381 + /* 2628 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2631 */ MCD_OPC_FilterValue, + 0, + 113, + 1, + 0, // Skip to: 3005 + /* 2636 */ MCD_OPC_ExtractField, + 22, + 3, // Inst{24-22} ... + /* 2639 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2653 + /* 2644 */ MCD_OPC_CheckPredicate, + 0, + 100, + 22, + 0, // Skip to: 8381 + /* 2649 */ MCD_OPC_Decode, + 145, + 6, + 2, // Opcode: EORrsr + /* 2653 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2667 + /* 2658 */ MCD_OPC_CheckPredicate, + 0, + 86, + 22, + 0, // Skip to: 8381 + /* 2663 */ MCD_OPC_Decode, + 128, + 14, + 2, // Opcode: RSBrsr + /* 2667 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2681 + /* 2672 */ MCD_OPC_CheckPredicate, + 0, + 72, + 22, + 0, // Skip to: 8381 + /* 2677 */ MCD_OPC_Decode, + 178, + 5, + 3, // Opcode: ADCrsr + /* 2681 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 2695 + /* 2686 */ MCD_OPC_CheckPredicate, + 0, + 58, + 22, + 0, // Skip to: 8381 + /* 2691 */ MCD_OPC_Decode, + 132, + 14, + 2, // Opcode: RSCrsr + /* 2695 */ MCD_OPC_FilterValue, + 4, + 163, + 0, + 0, // Skip to: 2863 + /* 2700 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2703 */ MCD_OPC_FilterValue, + 0, + 136, + 0, + 0, // Skip to: 2844 + /* 2708 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 2711 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 2766 + /* 2716 */ MCD_OPC_ExtractField, + 8, + 12, // Inst{19-8} ... + /* 2719 */ MCD_OPC_FilterValue, + 255, + 31, + 24, + 22, + 0, // Skip to: 8381 + /* 2725 */ MCD_OPC_CheckPredicate, + 10, + 11, + 0, + 0, // Skip to: 2741 + /* 2730 */ MCD_OPC_CheckField, + 0, + 4, + 14, + 4, + 0, + 0, // Skip to: 2741 + /* 2737 */ MCD_OPC_Decode, + 213, + 5, + 29, // Opcode: BX_RET + /* 2741 */ MCD_OPC_CheckPredicate, + 10, + 11, + 0, + 0, // Skip to: 2757 + /* 2746 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 4, + 0, + 0, // Skip to: 2757 + /* 2753 */ MCD_OPC_Decode, + 211, + 5, + 34, // Opcode: BX + /* 2757 */ MCD_OPC_CheckPredicate, + 10, + 243, + 21, + 0, // Skip to: 8381 + /* 2762 */ MCD_OPC_Decode, + 214, + 5, + 28, // Opcode: BX_pred + /* 2766 */ MCD_OPC_FilterValue, + 1, + 34, + 0, + 0, // Skip to: 2805 + /* 2771 */ MCD_OPC_ExtractField, + 8, + 12, // Inst{19-8} ... + /* 2774 */ MCD_OPC_FilterValue, + 255, + 31, + 225, + 21, + 0, // Skip to: 8381 + /* 2780 */ MCD_OPC_CheckPredicate, + 11, + 11, + 0, + 0, // Skip to: 2796 + /* 2785 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 4, + 0, + 0, // Skip to: 2796 + /* 2792 */ MCD_OPC_Decode, + 207, + 5, + 34, // Opcode: BLX + /* 2796 */ MCD_OPC_CheckPredicate, + 11, + 204, + 21, + 0, // Skip to: 8381 + /* 2801 */ MCD_OPC_Decode, + 208, + 5, + 28, // Opcode: BLX_pred + /* 2805 */ MCD_OPC_FilterValue, + 2, + 13, + 0, + 0, // Skip to: 2823 + /* 2810 */ MCD_OPC_CheckPredicate, + 0, + 190, + 21, + 0, // Skip to: 8381 + /* 2815 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 2819 */ MCD_OPC_Decode, + 238, + 13, + 21, // Opcode: QSUB + /* 2823 */ MCD_OPC_FilterValue, + 3, + 177, + 21, + 0, // Skip to: 8381 + /* 2828 */ MCD_OPC_CheckPredicate, + 0, + 172, + 21, + 0, // Skip to: 8381 + /* 2833 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 165, + 21, + 0, // Skip to: 8381 + /* 2840 */ MCD_OPC_Decode, + 205, + 5, + 15, // Opcode: BKPT + /* 2844 */ MCD_OPC_FilterValue, + 1, + 156, + 21, + 0, // Skip to: 8381 + /* 2849 */ MCD_OPC_CheckPredicate, + 0, + 151, + 21, + 0, // Skip to: 8381 + /* 2854 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2859 */ MCD_OPC_Decode, + 159, + 15, + 18, // Opcode: TEQrsr + /* 2863 */ MCD_OPC_FilterValue, + 5, + 97, + 0, + 0, // Skip to: 2965 + /* 2868 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2871 */ MCD_OPC_FilterValue, + 0, + 70, + 0, + 0, // Skip to: 2946 + /* 2876 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 2879 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 2907 + /* 2884 */ MCD_OPC_CheckPredicate, + 11, + 116, + 21, + 0, // Skip to: 8381 + /* 2889 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 109, + 21, + 0, // Skip to: 8381 + /* 2896 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 102, + 21, + 0, // Skip to: 8381 + /* 2903 */ MCD_OPC_Decode, + 249, + 5, + 35, // Opcode: CLZ + /* 2907 */ MCD_OPC_FilterValue, + 2, + 13, + 0, + 0, // Skip to: 2925 + /* 2912 */ MCD_OPC_CheckPredicate, + 0, + 88, + 21, + 0, // Skip to: 8381 + /* 2917 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 2921 */ MCD_OPC_Decode, + 236, + 13, + 21, // Opcode: QDSUB + /* 2925 */ MCD_OPC_FilterValue, + 3, + 75, + 21, + 0, // Skip to: 8381 + /* 2930 */ MCD_OPC_CheckPredicate, + 12, + 70, + 21, + 0, // Skip to: 8381 + /* 2935 */ MCD_OPC_CheckField, + 8, + 12, + 0, + 63, + 21, + 0, // Skip to: 8381 + /* 2942 */ MCD_OPC_Decode, + 162, + 14, + 36, // Opcode: SMC + /* 2946 */ MCD_OPC_FilterValue, + 1, + 54, + 21, + 0, // Skip to: 8381 + /* 2951 */ MCD_OPC_CheckPredicate, + 0, + 49, + 21, + 0, // Skip to: 8381 + /* 2956 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 2961 */ MCD_OPC_Decode, + 253, + 5, + 18, // Opcode: CMNzrsr + /* 2965 */ MCD_OPC_FilterValue, + 6, + 16, + 0, + 0, // Skip to: 2986 + /* 2970 */ MCD_OPC_CheckPredicate, + 0, + 30, + 21, + 0, // Skip to: 8381 + /* 2975 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 23, + 21, + 0, // Skip to: 8381 + /* 2982 */ MCD_OPC_Decode, + 244, + 6, + 37, // Opcode: MOVsr + /* 2986 */ MCD_OPC_FilterValue, + 7, + 14, + 21, + 0, // Skip to: 8381 + /* 2991 */ MCD_OPC_CheckPredicate, + 0, + 9, + 21, + 0, // Skip to: 8381 + /* 2996 */ MCD_OPC_SoftFail, + 128, + 128, + 60 /* 0xf0000 */, + 0, + /* 3001 */ MCD_OPC_Decode, + 210, + 13, + 37, // Opcode: MVNsr + /* 3005 */ MCD_OPC_FilterValue, + 1, + 251, + 20, + 0, // Skip to: 8381 + /* 3010 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 3013 */ MCD_OPC_FilterValue, + 0, + 48, + 1, + 0, // Skip to: 3322 + /* 3018 */ MCD_OPC_ExtractField, + 22, + 3, // Inst{24-22} ... + /* 3021 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3035 + /* 3026 */ MCD_OPC_CheckPredicate, + 1, + 230, + 20, + 0, // Skip to: 8381 + /* 3031 */ MCD_OPC_Decode, + 235, + 6, + 38, // Opcode: MLA + /* 3035 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 3056 + /* 3040 */ MCD_OPC_CheckPredicate, + 13, + 216, + 20, + 0, // Skip to: 8381 + /* 3045 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 209, + 20, + 0, // Skip to: 8381 + /* 3052 */ MCD_OPC_Decode, + 236, + 6, + 39, // Opcode: MLS + /* 3056 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3070 + /* 3061 */ MCD_OPC_CheckPredicate, + 1, + 195, + 20, + 0, // Skip to: 8381 + /* 3066 */ MCD_OPC_Decode, + 180, + 15, + 40, // Opcode: UMLAL + /* 3070 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3084 + /* 3075 */ MCD_OPC_CheckPredicate, + 1, + 181, + 20, + 0, // Skip to: 8381 + /* 3080 */ MCD_OPC_Decode, + 167, + 14, + 40, // Opcode: SMLAL + /* 3084 */ MCD_OPC_FilterValue, + 6, + 89, + 0, + 0, // Skip to: 3178 + /* 3089 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3092 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 3135 + /* 3097 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3100 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3114 + /* 3105 */ MCD_OPC_CheckPredicate, + 9, + 151, + 20, + 0, // Skip to: 8381 + /* 3110 */ MCD_OPC_Decode, + 232, + 14, + 41, // Opcode: STLEXD + /* 3114 */ MCD_OPC_FilterValue, + 1, + 142, + 20, + 0, // Skip to: 8381 + /* 3119 */ MCD_OPC_CheckPredicate, + 9, + 137, + 20, + 0, // Skip to: 8381 + /* 3124 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 130, + 20, + 0, // Skip to: 8381 + /* 3131 */ MCD_OPC_Decode, + 165, + 6, + 42, // Opcode: LDAEXD + /* 3135 */ MCD_OPC_FilterValue, + 15, + 121, + 20, + 0, // Skip to: 8381 + /* 3140 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3143 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3157 + /* 3148 */ MCD_OPC_CheckPredicate, + 0, + 108, + 20, + 0, // Skip to: 8381 + /* 3153 */ MCD_OPC_Decode, + 128, + 15, + 41, // Opcode: STREXD + /* 3157 */ MCD_OPC_FilterValue, + 1, + 99, + 20, + 0, // Skip to: 8381 + /* 3162 */ MCD_OPC_CheckPredicate, + 0, + 94, + 20, + 0, // Skip to: 8381 + /* 3167 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 87, + 20, + 0, // Skip to: 8381 + /* 3174 */ MCD_OPC_Decode, + 205, + 6, + 42, // Opcode: LDREXD + /* 3178 */ MCD_OPC_FilterValue, + 7, + 78, + 20, + 0, // Skip to: 8381 + /* 3183 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3186 */ MCD_OPC_FilterValue, + 12, + 45, + 0, + 0, // Skip to: 3236 + /* 3191 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3194 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3215 + /* 3199 */ MCD_OPC_CheckPredicate, + 8, + 57, + 20, + 0, // Skip to: 8381 + /* 3204 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 50, + 20, + 0, // Skip to: 8381 + /* 3211 */ MCD_OPC_Decode, + 234, + 14, + 22, // Opcode: STLH + /* 3215 */ MCD_OPC_FilterValue, + 1, + 41, + 20, + 0, // Skip to: 8381 + /* 3220 */ MCD_OPC_CheckPredicate, + 8, + 36, + 20, + 0, // Skip to: 8381 + /* 3225 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 29, + 20, + 0, // Skip to: 8381 + /* 3232 */ MCD_OPC_Decode, + 167, + 6, + 23, // Opcode: LDAH + /* 3236 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 3279 + /* 3241 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3244 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3258 + /* 3249 */ MCD_OPC_CheckPredicate, + 9, + 7, + 20, + 0, // Skip to: 8381 + /* 3254 */ MCD_OPC_Decode, + 233, + 14, + 24, // Opcode: STLEXH + /* 3258 */ MCD_OPC_FilterValue, + 1, + 254, + 19, + 0, // Skip to: 8381 + /* 3263 */ MCD_OPC_CheckPredicate, + 9, + 249, + 19, + 0, // Skip to: 8381 + /* 3268 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 242, + 19, + 0, // Skip to: 8381 + /* 3275 */ MCD_OPC_Decode, + 166, + 6, + 23, // Opcode: LDAEXH + /* 3279 */ MCD_OPC_FilterValue, + 15, + 233, + 19, + 0, // Skip to: 8381 + /* 3284 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3287 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3301 + /* 3292 */ MCD_OPC_CheckPredicate, + 0, + 220, + 19, + 0, // Skip to: 8381 + /* 3297 */ MCD_OPC_Decode, + 129, + 15, + 24, // Opcode: STREXH + /* 3301 */ MCD_OPC_FilterValue, + 1, + 211, + 19, + 0, // Skip to: 8381 + /* 3306 */ MCD_OPC_CheckPredicate, + 0, + 206, + 19, + 0, // Skip to: 8381 + /* 3311 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 199, + 19, + 0, // Skip to: 8381 + /* 3318 */ MCD_OPC_Decode, + 206, + 6, + 23, // Opcode: LDREXH + /* 3322 */ MCD_OPC_FilterValue, + 1, + 130, + 0, + 0, // Skip to: 3457 + /* 3327 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3330 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 3395 + /* 3335 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3338 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 3381 + /* 3343 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3346 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3367 + /* 3351 */ MCD_OPC_CheckPredicate, + 0, + 161, + 19, + 0, // Skip to: 8381 + /* 3356 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 154, + 19, + 0, // Skip to: 8381 + /* 3363 */ MCD_OPC_Decode, + 132, + 15, + 43, // Opcode: STRHTr + /* 3367 */ MCD_OPC_FilterValue, + 1, + 145, + 19, + 0, // Skip to: 8381 + /* 3372 */ MCD_OPC_CheckPredicate, + 0, + 140, + 19, + 0, // Skip to: 8381 + /* 3377 */ MCD_OPC_Decode, + 131, + 15, + 44, // Opcode: STRHTi + /* 3381 */ MCD_OPC_FilterValue, + 1, + 131, + 19, + 0, // Skip to: 8381 + /* 3386 */ MCD_OPC_CheckPredicate, + 0, + 126, + 19, + 0, // Skip to: 8381 + /* 3391 */ MCD_OPC_Decode, + 134, + 15, + 7, // Opcode: STRH_PRE + /* 3395 */ MCD_OPC_FilterValue, + 1, + 117, + 19, + 0, // Skip to: 8381 + /* 3400 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3403 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 3443 + /* 3408 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3411 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 3429 + /* 3416 */ MCD_OPC_CheckPredicate, + 0, + 96, + 19, + 0, // Skip to: 8381 + /* 3421 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 3425 */ MCD_OPC_Decode, + 209, + 6, + 45, // Opcode: LDRHTr + /* 3429 */ MCD_OPC_FilterValue, + 1, + 83, + 19, + 0, // Skip to: 8381 + /* 3434 */ MCD_OPC_CheckPredicate, + 0, + 78, + 19, + 0, // Skip to: 8381 + /* 3439 */ MCD_OPC_Decode, + 208, + 6, + 46, // Opcode: LDRHTi + /* 3443 */ MCD_OPC_FilterValue, + 1, + 69, + 19, + 0, // Skip to: 8381 + /* 3448 */ MCD_OPC_CheckPredicate, + 0, + 64, + 19, + 0, // Skip to: 8381 + /* 3453 */ MCD_OPC_Decode, + 211, + 6, + 7, // Opcode: LDRH_PRE + /* 3457 */ MCD_OPC_FilterValue, + 2, + 86, + 0, + 0, // Skip to: 3548 + /* 3462 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3465 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3486 + /* 3470 */ MCD_OPC_CheckPredicate, + 0, + 42, + 19, + 0, // Skip to: 8381 + /* 3475 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 35, + 19, + 0, // Skip to: 8381 + /* 3482 */ MCD_OPC_Decode, + 202, + 6, + 7, // Opcode: LDRD_PRE + /* 3486 */ MCD_OPC_FilterValue, + 1, + 26, + 19, + 0, // Skip to: 8381 + /* 3491 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3494 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 3534 + /* 3499 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3502 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 3520 + /* 3507 */ MCD_OPC_CheckPredicate, + 0, + 5, + 19, + 0, // Skip to: 8381 + /* 3512 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 3516 */ MCD_OPC_Decode, + 214, + 6, + 45, // Opcode: LDRSBTr + /* 3520 */ MCD_OPC_FilterValue, + 1, + 248, + 18, + 0, // Skip to: 8381 + /* 3525 */ MCD_OPC_CheckPredicate, + 0, + 243, + 18, + 0, // Skip to: 8381 + /* 3530 */ MCD_OPC_Decode, + 213, + 6, + 46, // Opcode: LDRSBTi + /* 3534 */ MCD_OPC_FilterValue, + 1, + 234, + 18, + 0, // Skip to: 8381 + /* 3539 */ MCD_OPC_CheckPredicate, + 0, + 229, + 18, + 0, // Skip to: 8381 + /* 3544 */ MCD_OPC_Decode, + 216, + 6, + 7, // Opcode: LDRSB_PRE + /* 3548 */ MCD_OPC_FilterValue, + 3, + 220, + 18, + 0, // Skip to: 8381 + /* 3553 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3556 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3577 + /* 3561 */ MCD_OPC_CheckPredicate, + 0, + 207, + 18, + 0, // Skip to: 8381 + /* 3566 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 200, + 18, + 0, // Skip to: 8381 + /* 3573 */ MCD_OPC_Decode, + 253, + 14, + 7, // Opcode: STRD_PRE + /* 3577 */ MCD_OPC_FilterValue, + 1, + 191, + 18, + 0, // Skip to: 8381 + /* 3582 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3585 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 3625 + /* 3590 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3593 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 3611 + /* 3598 */ MCD_OPC_CheckPredicate, + 0, + 170, + 18, + 0, // Skip to: 8381 + /* 3603 */ MCD_OPC_SoftFail, + 128, + 30 /* 0xf00 */, + 0, + /* 3607 */ MCD_OPC_Decode, + 219, + 6, + 45, // Opcode: LDRSHTr + /* 3611 */ MCD_OPC_FilterValue, + 1, + 157, + 18, + 0, // Skip to: 8381 + /* 3616 */ MCD_OPC_CheckPredicate, + 0, + 152, + 18, + 0, // Skip to: 8381 + /* 3621 */ MCD_OPC_Decode, + 218, + 6, + 46, // Opcode: LDRSHTi + /* 3625 */ MCD_OPC_FilterValue, + 1, + 143, + 18, + 0, // Skip to: 8381 + /* 3630 */ MCD_OPC_CheckPredicate, + 0, + 138, + 18, + 0, // Skip to: 8381 + /* 3635 */ MCD_OPC_Decode, + 221, + 6, + 7, // Opcode: LDRSH_PRE + /* 3639 */ MCD_OPC_FilterValue, + 1, + 0, + 2, + 0, // Skip to: 4156 + /* 3644 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 3647 */ MCD_OPC_FilterValue, + 0, + 201, + 0, + 0, // Skip to: 3853 + /* 3652 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3655 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 3735 + /* 3660 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 3663 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3677 + /* 3668 */ MCD_OPC_CheckPredicate, + 0, + 46, + 0, + 0, // Skip to: 3719 + /* 3673 */ MCD_OPC_Decode, + 188, + 5, + 47, // Opcode: ANDri + /* 3677 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3691 + /* 3682 */ MCD_OPC_CheckPredicate, + 0, + 32, + 0, + 0, // Skip to: 3719 + /* 3687 */ MCD_OPC_Decode, + 143, + 15, + 47, // Opcode: SUBri + /* 3691 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3705 + /* 3696 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 3719 + /* 3701 */ MCD_OPC_Decode, + 179, + 5, + 47, // Opcode: ADDri + /* 3705 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3719 + /* 3710 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 3719 + /* 3715 */ MCD_OPC_Decode, + 137, + 14, + 47, // Opcode: SBCri + /* 3719 */ MCD_OPC_CheckPredicate, + 0, + 49, + 18, + 0, // Skip to: 8381 + /* 3724 */ MCD_OPC_CheckField, + 16, + 5, + 15, + 42, + 18, + 0, // Skip to: 8381 + /* 3731 */ MCD_OPC_Decode, + 183, + 5, + 48, // Opcode: ADR + /* 3735 */ MCD_OPC_FilterValue, + 1, + 33, + 18, + 0, // Skip to: 8381 + /* 3740 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 3743 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 3784 + /* 3748 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3751 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3765 + /* 3756 */ MCD_OPC_CheckPredicate, + 13, + 12, + 18, + 0, // Skip to: 8381 + /* 3761 */ MCD_OPC_Decode, + 240, + 6, + 49, // Opcode: MOVi16 + /* 3765 */ MCD_OPC_FilterValue, + 1, + 3, + 18, + 0, // Skip to: 8381 + /* 3770 */ MCD_OPC_CheckPredicate, + 0, + 254, + 17, + 0, // Skip to: 8381 + /* 3775 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 3780 */ MCD_OPC_Decode, + 163, + 15, + 50, // Opcode: TSTri + /* 3784 */ MCD_OPC_FilterValue, + 1, + 36, + 0, + 0, // Skip to: 3825 + /* 3789 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3792 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3806 + /* 3797 */ MCD_OPC_CheckPredicate, + 13, + 227, + 17, + 0, // Skip to: 8381 + /* 3802 */ MCD_OPC_Decode, + 238, + 6, + 49, // Opcode: MOVTi16 + /* 3806 */ MCD_OPC_FilterValue, + 1, + 218, + 17, + 0, // Skip to: 8381 + /* 3811 */ MCD_OPC_CheckPredicate, + 0, + 213, + 17, + 0, // Skip to: 8381 + /* 3816 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 3821 */ MCD_OPC_Decode, + 254, + 5, + 50, // Opcode: CMPri + /* 3825 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3839 + /* 3830 */ MCD_OPC_CheckPredicate, + 0, + 194, + 17, + 0, // Skip to: 8381 + /* 3835 */ MCD_OPC_Decode, + 219, + 13, + 47, // Opcode: ORRri + /* 3839 */ MCD_OPC_FilterValue, + 3, + 185, + 17, + 0, // Skip to: 8381 + /* 3844 */ MCD_OPC_CheckPredicate, + 0, + 180, + 17, + 0, // Skip to: 8381 + /* 3849 */ MCD_OPC_Decode, + 201, + 5, + 47, // Opcode: BICri + /* 3853 */ MCD_OPC_FilterValue, + 1, + 171, + 17, + 0, // Skip to: 8381 + /* 3858 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 3861 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 3897 + /* 3866 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3869 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3883 + /* 3874 */ MCD_OPC_CheckPredicate, + 0, + 150, + 17, + 0, // Skip to: 8381 + /* 3879 */ MCD_OPC_Decode, + 142, + 6, + 47, // Opcode: EORri + /* 3883 */ MCD_OPC_FilterValue, + 1, + 141, + 17, + 0, // Skip to: 8381 + /* 3888 */ MCD_OPC_CheckPredicate, + 0, + 136, + 17, + 0, // Skip to: 8381 + /* 3893 */ MCD_OPC_Decode, + 253, + 13, + 47, // Opcode: RSBri + /* 3897 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 3933 + /* 3902 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 3905 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3919 + /* 3910 */ MCD_OPC_CheckPredicate, + 0, + 114, + 17, + 0, // Skip to: 8381 + /* 3915 */ MCD_OPC_Decode, + 175, + 5, + 47, // Opcode: ADCri + /* 3919 */ MCD_OPC_FilterValue, + 1, + 105, + 17, + 0, // Skip to: 8381 + /* 3924 */ MCD_OPC_CheckPredicate, + 0, + 100, + 17, + 0, // Skip to: 8381 + /* 3929 */ MCD_OPC_Decode, + 129, + 14, + 47, // Opcode: RSCri + /* 3933 */ MCD_OPC_FilterValue, + 2, + 168, + 0, + 0, // Skip to: 4106 + /* 3938 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3941 */ MCD_OPC_FilterValue, + 0, + 114, + 0, + 0, // Skip to: 4060 + /* 3946 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3949 */ MCD_OPC_FilterValue, + 15, + 75, + 17, + 0, // Skip to: 8381 + /* 3954 */ MCD_OPC_CheckPredicate, + 14, + 32, + 0, + 0, // Skip to: 3991 + /* 3959 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 25, + 0, + 0, // Skip to: 3991 + /* 3966 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 18, + 0, + 0, // Skip to: 3991 + /* 3973 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 11, + 0, + 0, // Skip to: 3991 + /* 3980 */ MCD_OPC_CheckField, + 0, + 12, + 18, + 4, + 0, + 0, // Skip to: 3991 + /* 3987 */ MCD_OPC_Decode, + 162, + 15, + 51, // Opcode: TSB + /* 3991 */ MCD_OPC_CheckPredicate, + 15, + 25, + 0, + 0, // Skip to: 4021 + /* 3996 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 18, + 0, + 0, // Skip to: 4021 + /* 4003 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 11, + 0, + 0, // Skip to: 4021 + /* 4010 */ MCD_OPC_CheckField, + 4, + 8, + 15, + 4, + 0, + 0, // Skip to: 4021 + /* 4017 */ MCD_OPC_Decode, + 139, + 6, + 36, // Opcode: DBG + /* 4021 */ MCD_OPC_CheckPredicate, + 1, + 25, + 0, + 0, // Skip to: 4051 + /* 4026 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 18, + 0, + 0, // Skip to: 4051 + /* 4033 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 11, + 0, + 0, // Skip to: 4051 + /* 4040 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4051 + /* 4047 */ MCD_OPC_Decode, + 157, + 6, + 52, // Opcode: HINT + /* 4051 */ MCD_OPC_CheckPredicate, + 0, + 229, + 16, + 0, // Skip to: 8381 + /* 4056 */ MCD_OPC_Decode, + 254, + 6, + 53, // Opcode: MSRi + /* 4060 */ MCD_OPC_FilterValue, + 1, + 220, + 16, + 0, // Skip to: 8381 + /* 4065 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4068 */ MCD_OPC_FilterValue, + 0, + 14, + 0, + 0, // Skip to: 4087 + /* 4073 */ MCD_OPC_CheckPredicate, + 0, + 207, + 16, + 0, // Skip to: 8381 + /* 4078 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 4083 */ MCD_OPC_Decode, + 156, + 15, + 50, // Opcode: TEQri + /* 4087 */ MCD_OPC_FilterValue, + 1, + 193, + 16, + 0, // Skip to: 8381 + /* 4092 */ MCD_OPC_CheckPredicate, + 0, + 188, + 16, + 0, // Skip to: 8381 + /* 4097 */ MCD_OPC_SoftFail, + 128, + 224, + 3 /* 0xf000 */, + 0, + /* 4102 */ MCD_OPC_Decode, + 250, + 5, + 50, // Opcode: CMNri + /* 4106 */ MCD_OPC_FilterValue, + 3, + 174, + 16, + 0, // Skip to: 8381 + /* 4111 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4114 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4135 + /* 4119 */ MCD_OPC_CheckPredicate, + 0, + 161, + 16, + 0, // Skip to: 8381 + /* 4124 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 154, + 16, + 0, // Skip to: 8381 + /* 4131 */ MCD_OPC_Decode, + 239, + 6, + 54, // Opcode: MOVi + /* 4135 */ MCD_OPC_FilterValue, + 1, + 145, + 16, + 0, // Skip to: 8381 + /* 4140 */ MCD_OPC_CheckPredicate, + 0, + 140, + 16, + 0, // Skip to: 8381 + /* 4145 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 133, + 16, + 0, // Skip to: 8381 + /* 4152 */ MCD_OPC_Decode, + 207, + 13, + 54, // Opcode: MVNi + /* 4156 */ MCD_OPC_FilterValue, + 2, + 9, + 2, + 0, // Skip to: 4682 + /* 4161 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 4164 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 4200 + /* 4169 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4172 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4186 + /* 4177 */ MCD_OPC_CheckPredicate, + 0, + 103, + 16, + 0, // Skip to: 8381 + /* 4182 */ MCD_OPC_Decode, + 137, + 15, + 55, // Opcode: STR_POST_IMM + /* 4186 */ MCD_OPC_FilterValue, + 1, + 94, + 16, + 0, // Skip to: 8381 + /* 4191 */ MCD_OPC_CheckPredicate, + 0, + 89, + 16, + 0, // Skip to: 8381 + /* 4196 */ MCD_OPC_Decode, + 141, + 15, + 56, // Opcode: STRi12 + /* 4200 */ MCD_OPC_FilterValue, + 1, + 54, + 0, + 0, // Skip to: 4259 + /* 4205 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4208 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4222 + /* 4213 */ MCD_OPC_CheckPredicate, + 0, + 67, + 16, + 0, // Skip to: 8381 + /* 4218 */ MCD_OPC_Decode, + 224, + 6, + 55, // Opcode: LDR_POST_IMM + /* 4222 */ MCD_OPC_FilterValue, + 1, + 58, + 16, + 0, // Skip to: 8381 + /* 4227 */ MCD_OPC_CheckPredicate, + 16, + 18, + 0, + 0, // Skip to: 4250 + /* 4232 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4250 + /* 4239 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4250 + /* 4246 */ MCD_OPC_Decode, + 225, + 13, + 57, // Opcode: PLDWi12 + /* 4250 */ MCD_OPC_CheckPredicate, + 0, + 30, + 16, + 0, // Skip to: 8381 + /* 4255 */ MCD_OPC_Decode, + 229, + 6, + 56, // Opcode: LDRi12 + /* 4259 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 4295 + /* 4264 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4267 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4281 + /* 4272 */ MCD_OPC_CheckPredicate, + 0, + 8, + 16, + 0, // Skip to: 8381 + /* 4277 */ MCD_OPC_Decode, + 135, + 15, + 55, // Opcode: STRT_POST_IMM + /* 4281 */ MCD_OPC_FilterValue, + 1, + 255, + 15, + 0, // Skip to: 8381 + /* 4286 */ MCD_OPC_CheckPredicate, + 0, + 250, + 15, + 0, // Skip to: 8381 + /* 4291 */ MCD_OPC_Decode, + 139, + 15, + 58, // Opcode: STR_PRE_IMM + /* 4295 */ MCD_OPC_FilterValue, + 3, + 31, + 0, + 0, // Skip to: 4331 + /* 4300 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4303 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4317 + /* 4308 */ MCD_OPC_CheckPredicate, + 0, + 228, + 15, + 0, // Skip to: 8381 + /* 4313 */ MCD_OPC_Decode, + 222, + 6, + 55, // Opcode: LDRT_POST_IMM + /* 4317 */ MCD_OPC_FilterValue, + 1, + 219, + 15, + 0, // Skip to: 8381 + /* 4322 */ MCD_OPC_CheckPredicate, + 0, + 214, + 15, + 0, // Skip to: 8381 + /* 4327 */ MCD_OPC_Decode, + 226, + 6, + 59, // Opcode: LDR_PRE_IMM + /* 4331 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 4367 + /* 4336 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4339 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4353 + /* 4344 */ MCD_OPC_CheckPredicate, + 0, + 192, + 15, + 0, // Skip to: 8381 + /* 4349 */ MCD_OPC_Decode, + 245, + 14, + 55, // Opcode: STRB_POST_IMM + /* 4353 */ MCD_OPC_FilterValue, + 1, + 183, + 15, + 0, // Skip to: 8381 + /* 4358 */ MCD_OPC_CheckPredicate, + 0, + 178, + 15, + 0, // Skip to: 8381 + /* 4363 */ MCD_OPC_Decode, + 249, + 14, + 60, // Opcode: STRBi12 + /* 4367 */ MCD_OPC_FilterValue, + 5, + 77, + 0, + 0, // Skip to: 4449 + /* 4372 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4375 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 4412 + /* 4380 */ MCD_OPC_CheckPredicate, + 15, + 18, + 0, + 0, // Skip to: 4403 + /* 4385 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4403 + /* 4392 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4403 + /* 4399 */ MCD_OPC_Decode, + 229, + 13, + 57, // Opcode: PLIi12 + /* 4403 */ MCD_OPC_CheckPredicate, + 0, + 133, + 15, + 0, // Skip to: 8381 + /* 4408 */ MCD_OPC_Decode, + 194, + 6, + 55, // Opcode: LDRB_POST_IMM + /* 4412 */ MCD_OPC_FilterValue, + 1, + 124, + 15, + 0, // Skip to: 8381 + /* 4417 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 4440 + /* 4422 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4440 + /* 4429 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4440 + /* 4436 */ MCD_OPC_Decode, + 227, + 13, + 57, // Opcode: PLDi12 + /* 4440 */ MCD_OPC_CheckPredicate, + 0, + 96, + 15, + 0, // Skip to: 8381 + /* 4445 */ MCD_OPC_Decode, + 198, + 6, + 60, // Opcode: LDRBi12 + /* 4449 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 4485 + /* 4454 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4457 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4471 + /* 4462 */ MCD_OPC_CheckPredicate, + 0, + 74, + 15, + 0, // Skip to: 8381 + /* 4467 */ MCD_OPC_Decode, + 243, + 14, + 55, // Opcode: STRBT_POST_IMM + /* 4471 */ MCD_OPC_FilterValue, + 1, + 65, + 15, + 0, // Skip to: 8381 + /* 4476 */ MCD_OPC_CheckPredicate, + 0, + 60, + 15, + 0, // Skip to: 8381 + /* 4481 */ MCD_OPC_Decode, + 247, + 14, + 58, // Opcode: STRB_PRE_IMM + /* 4485 */ MCD_OPC_FilterValue, + 7, + 51, + 15, + 0, // Skip to: 8381 + /* 4490 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4493 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4507 + /* 4498 */ MCD_OPC_CheckPredicate, + 0, + 38, + 15, + 0, // Skip to: 8381 + /* 4503 */ MCD_OPC_Decode, + 192, + 6, + 55, // Opcode: LDRBT_POST_IMM + /* 4507 */ MCD_OPC_FilterValue, + 1, + 29, + 15, + 0, // Skip to: 8381 + /* 4512 */ MCD_OPC_CheckPredicate, + 17, + 27, + 0, + 0, // Skip to: 4544 + /* 4517 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 20, + 0, + 0, // Skip to: 4544 + /* 4524 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 13, + 0, + 0, // Skip to: 4544 + /* 4531 */ MCD_OPC_CheckField, + 0, + 20, + 159, + 224, + 63, + 4, + 0, + 0, // Skip to: 4544 + /* 4540 */ MCD_OPC_Decode, + 248, + 5, + 51, // Opcode: CLREX + /* 4544 */ MCD_OPC_ExtractField, + 4, + 16, // Inst{19-4} ... + /* 4547 */ MCD_OPC_FilterValue, + 132, + 254, + 3, + 23, + 0, + 0, // Skip to: 4577 + /* 4554 */ MCD_OPC_CheckPredicate, + 18, + 78, + 0, + 0, // Skip to: 4637 + /* 4559 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 71, + 0, + 0, // Skip to: 4637 + /* 4566 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 64, + 0, + 0, // Skip to: 4637 + /* 4573 */ MCD_OPC_Decode, + 141, + 6, + 61, // Opcode: DSB + /* 4577 */ MCD_OPC_FilterValue, + 133, + 254, + 3, + 23, + 0, + 0, // Skip to: 4607 + /* 4584 */ MCD_OPC_CheckPredicate, + 18, + 48, + 0, + 0, // Skip to: 4637 + /* 4589 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 41, + 0, + 0, // Skip to: 4637 + /* 4596 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 34, + 0, + 0, // Skip to: 4637 + /* 4603 */ MCD_OPC_Decode, + 140, + 6, + 61, // Opcode: DMB + /* 4607 */ MCD_OPC_FilterValue, + 134, + 254, + 3, + 23, + 0, + 0, // Skip to: 4637 + /* 4614 */ MCD_OPC_CheckPredicate, + 18, + 18, + 0, + 0, // Skip to: 4637 + /* 4619 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4637 + /* 4626 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 4, + 0, + 0, // Skip to: 4637 + /* 4633 */ MCD_OPC_Decode, + 160, + 6, + 62, // Opcode: ISB + /* 4637 */ MCD_OPC_CheckPredicate, + 19, + 31, + 0, + 0, // Skip to: 4673 + /* 4642 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 24, + 0, + 0, // Skip to: 4673 + /* 4649 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 17, + 0, + 0, // Skip to: 4673 + /* 4656 */ MCD_OPC_CheckField, + 4, + 4, + 7, + 10, + 0, + 0, // Skip to: 4673 + /* 4663 */ MCD_OPC_SoftFail, + 143, + 30 /* 0xf0f */, + 128, + 224, + 63 /* 0xff000 */, + /* 4669 */ MCD_OPC_Decode, + 136, + 14, + 51, // Opcode: SB + /* 4673 */ MCD_OPC_CheckPredicate, + 0, + 119, + 14, + 0, // Skip to: 8381 + /* 4678 */ MCD_OPC_Decode, + 196, + 6, + 59, // Opcode: LDRB_PRE_IMM + /* 4682 */ MCD_OPC_FilterValue, + 3, + 129, + 10, + 0, // Skip to: 7376 + /* 4687 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 4690 */ MCD_OPC_FilterValue, + 0, + 200, + 2, + 0, // Skip to: 5407 + /* 4695 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 4698 */ MCD_OPC_FilterValue, + 0, + 98, + 0, + 0, // Skip to: 4801 + /* 4703 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4706 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 4742 + /* 4711 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4714 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4728 + /* 4719 */ MCD_OPC_CheckPredicate, + 0, + 73, + 14, + 0, // Skip to: 8381 + /* 4724 */ MCD_OPC_Decode, + 138, + 15, + 55, // Opcode: STR_POST_REG + /* 4728 */ MCD_OPC_FilterValue, + 1, + 64, + 14, + 0, // Skip to: 8381 + /* 4733 */ MCD_OPC_CheckPredicate, + 0, + 59, + 14, + 0, // Skip to: 8381 + /* 4738 */ MCD_OPC_Decode, + 142, + 15, + 63, // Opcode: STRrs + /* 4742 */ MCD_OPC_FilterValue, + 1, + 50, + 14, + 0, // Skip to: 8381 + /* 4747 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4750 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4764 + /* 4755 */ MCD_OPC_CheckPredicate, + 0, + 37, + 14, + 0, // Skip to: 8381 + /* 4760 */ MCD_OPC_Decode, + 225, + 6, + 55, // Opcode: LDR_POST_REG + /* 4764 */ MCD_OPC_FilterValue, + 1, + 28, + 14, + 0, // Skip to: 8381 + /* 4769 */ MCD_OPC_CheckPredicate, + 16, + 18, + 0, + 0, // Skip to: 4792 + /* 4774 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 4792 + /* 4781 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4792 + /* 4788 */ MCD_OPC_Decode, + 226, + 13, + 64, // Opcode: PLDWrs + /* 4792 */ MCD_OPC_CheckPredicate, + 0, + 0, + 14, + 0, // Skip to: 8381 + /* 4797 */ MCD_OPC_Decode, + 230, + 6, + 63, // Opcode: LDRrs + /* 4801 */ MCD_OPC_FilterValue, + 1, + 247, + 13, + 0, // Skip to: 8381 + /* 4806 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 4809 */ MCD_OPC_FilterValue, + 0, + 202, + 0, + 0, // Skip to: 5016 + /* 4814 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 4817 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 4875 + /* 4822 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4825 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 4850 + /* 4830 */ MCD_OPC_CheckPredicate, + 0, + 218, + 13, + 0, // Skip to: 8381 + /* 4835 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 211, + 13, + 0, // Skip to: 8381 + /* 4842 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 4846 */ MCD_OPC_Decode, + 133, + 14, + 65, // Opcode: SADD16 + /* 4850 */ MCD_OPC_FilterValue, + 1, + 198, + 13, + 0, // Skip to: 8381 + /* 4855 */ MCD_OPC_CheckPredicate, + 0, + 193, + 13, + 0, // Skip to: 8381 + /* 4860 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 186, + 13, + 0, // Skip to: 8381 + /* 4867 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 4871 */ MCD_OPC_Decode, + 134, + 14, + 65, // Opcode: SADD8 + /* 4875 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 4896 + /* 4880 */ MCD_OPC_CheckPredicate, + 1, + 168, + 13, + 0, // Skip to: 8381 + /* 4885 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 161, + 13, + 0, // Skip to: 8381 + /* 4892 */ MCD_OPC_Decode, + 223, + 13, + 66, // Opcode: PKHBT + /* 4896 */ MCD_OPC_FilterValue, + 2, + 69, + 0, + 0, // Skip to: 4970 + /* 4901 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4904 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 4942 + /* 4909 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4912 */ MCD_OPC_FilterValue, + 0, + 136, + 13, + 0, // Skip to: 8381 + /* 4917 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 4933 + /* 4922 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 4933 + /* 4929 */ MCD_OPC_Decode, + 188, + 14, + 67, // Opcode: SMUAD + /* 4933 */ MCD_OPC_CheckPredicate, + 1, + 115, + 13, + 0, // Skip to: 8381 + /* 4938 */ MCD_OPC_Decode, + 165, + 14, + 68, // Opcode: SMLAD + /* 4942 */ MCD_OPC_FilterValue, + 1, + 106, + 13, + 0, // Skip to: 8381 + /* 4947 */ MCD_OPC_CheckPredicate, + 20, + 101, + 13, + 0, // Skip to: 8381 + /* 4952 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 94, + 13, + 0, // Skip to: 8381 + /* 4959 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 87, + 13, + 0, // Skip to: 8381 + /* 4966 */ MCD_OPC_Decode, + 142, + 14, + 30, // Opcode: SDIV + /* 4970 */ MCD_OPC_FilterValue, + 3, + 78, + 13, + 0, // Skip to: 8381 + /* 4975 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4978 */ MCD_OPC_FilterValue, + 0, + 70, + 13, + 0, // Skip to: 8381 + /* 4983 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4986 */ MCD_OPC_FilterValue, + 0, + 62, + 13, + 0, // Skip to: 8381 + /* 4991 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 5007 + /* 4996 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 5007 + /* 5003 */ MCD_OPC_Decode, + 188, + 15, + 30, // Opcode: USAD8 + /* 5007 */ MCD_OPC_CheckPredicate, + 1, + 41, + 13, + 0, // Skip to: 8381 + /* 5012 */ MCD_OPC_Decode, + 189, + 15, + 39, // Opcode: USADA8 + /* 5016 */ MCD_OPC_FilterValue, + 1, + 113, + 0, + 0, // Skip to: 5134 + /* 5021 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5024 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 5056 + /* 5029 */ MCD_OPC_CheckPredicate, + 0, + 19, + 13, + 0, // Skip to: 8381 + /* 5034 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 13, + 0, // Skip to: 8381 + /* 5041 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 5, + 13, + 0, // Skip to: 8381 + /* 5048 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5052 */ MCD_OPC_Decode, + 135, + 14, + 65, // Opcode: SASX + /* 5056 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 5088 + /* 5061 */ MCD_OPC_CheckPredicate, + 1, + 243, + 12, + 0, // Skip to: 8381 + /* 5066 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 236, + 12, + 0, // Skip to: 8381 + /* 5073 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 229, + 12, + 0, // Skip to: 8381 + /* 5080 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5084 */ MCD_OPC_Decode, + 143, + 14, + 69, // Opcode: SEL + /* 5088 */ MCD_OPC_FilterValue, + 2, + 216, + 12, + 0, // Skip to: 8381 + /* 5093 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5096 */ MCD_OPC_FilterValue, + 0, + 208, + 12, + 0, // Skip to: 8381 + /* 5101 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5104 */ MCD_OPC_FilterValue, + 0, + 200, + 12, + 0, // Skip to: 8381 + /* 5109 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 5125 + /* 5114 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 5125 + /* 5121 */ MCD_OPC_Decode, + 189, + 14, + 67, // Opcode: SMUADX + /* 5125 */ MCD_OPC_CheckPredicate, + 1, + 179, + 12, + 0, // Skip to: 8381 + /* 5130 */ MCD_OPC_Decode, + 166, + 14, + 68, // Opcode: SMLADX + /* 5134 */ MCD_OPC_FilterValue, + 2, + 102, + 0, + 0, // Skip to: 5241 + /* 5139 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5142 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 5174 + /* 5147 */ MCD_OPC_CheckPredicate, + 0, + 157, + 12, + 0, // Skip to: 8381 + /* 5152 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 150, + 12, + 0, // Skip to: 8381 + /* 5159 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 143, + 12, + 0, // Skip to: 8381 + /* 5166 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5170 */ MCD_OPC_Decode, + 209, + 14, + 65, // Opcode: SSAX + /* 5174 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 5195 + /* 5179 */ MCD_OPC_CheckPredicate, + 1, + 125, + 12, + 0, // Skip to: 8381 + /* 5184 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 118, + 12, + 0, // Skip to: 8381 + /* 5191 */ MCD_OPC_Decode, + 224, + 13, + 66, // Opcode: PKHTB + /* 5195 */ MCD_OPC_FilterValue, + 2, + 109, + 12, + 0, // Skip to: 8381 + /* 5200 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5203 */ MCD_OPC_FilterValue, + 0, + 101, + 12, + 0, // Skip to: 8381 + /* 5208 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5211 */ MCD_OPC_FilterValue, + 0, + 93, + 12, + 0, // Skip to: 8381 + /* 5216 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 5232 + /* 5221 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 5232 + /* 5228 */ MCD_OPC_Decode, + 197, + 14, + 67, // Opcode: SMUSD + /* 5232 */ MCD_OPC_CheckPredicate, + 1, + 72, + 12, + 0, // Skip to: 8381 + /* 5237 */ MCD_OPC_Decode, + 178, + 14, + 68, // Opcode: SMLSD + /* 5241 */ MCD_OPC_FilterValue, + 3, + 63, + 12, + 0, // Skip to: 8381 + /* 5246 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5249 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 5307 + /* 5254 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5257 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 5282 + /* 5262 */ MCD_OPC_CheckPredicate, + 0, + 42, + 12, + 0, // Skip to: 8381 + /* 5267 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 35, + 12, + 0, // Skip to: 8381 + /* 5274 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5278 */ MCD_OPC_Decode, + 210, + 14, + 65, // Opcode: SSUB16 + /* 5282 */ MCD_OPC_FilterValue, + 1, + 22, + 12, + 0, // Skip to: 8381 + /* 5287 */ MCD_OPC_CheckPredicate, + 0, + 17, + 12, + 0, // Skip to: 8381 + /* 5292 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 10, + 12, + 0, // Skip to: 8381 + /* 5299 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5303 */ MCD_OPC_Decode, + 211, + 14, + 65, // Opcode: SSUB8 + /* 5307 */ MCD_OPC_FilterValue, + 1, + 49, + 0, + 0, // Skip to: 5361 + /* 5312 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5315 */ MCD_OPC_FilterValue, + 0, + 245, + 11, + 0, // Skip to: 8381 + /* 5320 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5323 */ MCD_OPC_FilterValue, + 0, + 237, + 11, + 0, // Skip to: 8381 + /* 5328 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 5348 + /* 5333 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 5348 + /* 5340 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5344 */ MCD_OPC_Decode, + 154, + 15, + 70, // Opcode: SXTB16 + /* 5348 */ MCD_OPC_CheckPredicate, + 1, + 212, + 11, + 0, // Skip to: 8381 + /* 5353 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5357 */ MCD_OPC_Decode, + 151, + 15, + 71, // Opcode: SXTAB16 + /* 5361 */ MCD_OPC_FilterValue, + 2, + 199, + 11, + 0, // Skip to: 8381 + /* 5366 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 5369 */ MCD_OPC_FilterValue, + 0, + 191, + 11, + 0, // Skip to: 8381 + /* 5374 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5377 */ MCD_OPC_FilterValue, + 0, + 183, + 11, + 0, // Skip to: 8381 + /* 5382 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 5398 + /* 5387 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 5398 + /* 5394 */ MCD_OPC_Decode, + 198, + 14, + 67, // Opcode: SMUSDX + /* 5398 */ MCD_OPC_CheckPredicate, + 1, + 162, + 11, + 0, // Skip to: 8381 + /* 5403 */ MCD_OPC_Decode, + 179, + 14, + 68, // Opcode: SMLSDX + /* 5407 */ MCD_OPC_FilterValue, + 1, + 106, + 2, + 0, // Skip to: 6030 + /* 5412 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 5415 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 5495 + /* 5420 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5423 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 5459 + /* 5428 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 5431 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5445 + /* 5436 */ MCD_OPC_CheckPredicate, + 0, + 124, + 11, + 0, // Skip to: 8381 + /* 5441 */ MCD_OPC_Decode, + 136, + 15, + 55, // Opcode: STRT_POST_REG + /* 5445 */ MCD_OPC_FilterValue, + 1, + 115, + 11, + 0, // Skip to: 8381 + /* 5450 */ MCD_OPC_CheckPredicate, + 0, + 110, + 11, + 0, // Skip to: 8381 + /* 5455 */ MCD_OPC_Decode, + 140, + 15, + 72, // Opcode: STR_PRE_REG + /* 5459 */ MCD_OPC_FilterValue, + 1, + 101, + 11, + 0, // Skip to: 8381 + /* 5464 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 5467 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5481 + /* 5472 */ MCD_OPC_CheckPredicate, + 0, + 88, + 11, + 0, // Skip to: 8381 + /* 5477 */ MCD_OPC_Decode, + 223, + 6, + 55, // Opcode: LDRT_POST_REG + /* 5481 */ MCD_OPC_FilterValue, + 1, + 79, + 11, + 0, // Skip to: 8381 + /* 5486 */ MCD_OPC_CheckPredicate, + 0, + 74, + 11, + 0, // Skip to: 8381 + /* 5491 */ MCD_OPC_Decode, + 227, + 6, + 73, // Opcode: LDR_PRE_REG + /* 5495 */ MCD_OPC_FilterValue, + 1, + 65, + 11, + 0, // Skip to: 8381 + /* 5500 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5503 */ MCD_OPC_FilterValue, + 0, + 11, + 1, + 0, // Skip to: 5775 + /* 5508 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 5511 */ MCD_OPC_FilterValue, + 0, + 39, + 0, + 0, // Skip to: 5555 + /* 5516 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5519 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5537 + /* 5524 */ MCD_OPC_CheckPredicate, + 0, + 36, + 11, + 0, // Skip to: 8381 + /* 5529 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5533 */ MCD_OPC_Decode, + 232, + 13, + 65, // Opcode: QADD16 + /* 5537 */ MCD_OPC_FilterValue, + 1, + 23, + 11, + 0, // Skip to: 8381 + /* 5542 */ MCD_OPC_CheckPredicate, + 0, + 18, + 11, + 0, // Skip to: 8381 + /* 5547 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5551 */ MCD_OPC_Decode, + 156, + 14, + 65, // Opcode: SHADD16 + /* 5555 */ MCD_OPC_FilterValue, + 1, + 39, + 0, + 0, // Skip to: 5599 + /* 5560 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5563 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5581 + /* 5568 */ MCD_OPC_CheckPredicate, + 0, + 248, + 10, + 0, // Skip to: 8381 + /* 5573 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5577 */ MCD_OPC_Decode, + 234, + 13, + 65, // Opcode: QASX + /* 5581 */ MCD_OPC_FilterValue, + 1, + 235, + 10, + 0, // Skip to: 8381 + /* 5586 */ MCD_OPC_CheckPredicate, + 0, + 230, + 10, + 0, // Skip to: 8381 + /* 5591 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5595 */ MCD_OPC_Decode, + 158, + 14, + 65, // Opcode: SHASX + /* 5599 */ MCD_OPC_FilterValue, + 2, + 39, + 0, + 0, // Skip to: 5643 + /* 5604 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5607 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5625 + /* 5612 */ MCD_OPC_CheckPredicate, + 0, + 204, + 10, + 0, // Skip to: 8381 + /* 5617 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5621 */ MCD_OPC_Decode, + 237, + 13, + 65, // Opcode: QSAX + /* 5625 */ MCD_OPC_FilterValue, + 1, + 191, + 10, + 0, // Skip to: 8381 + /* 5630 */ MCD_OPC_CheckPredicate, + 0, + 186, + 10, + 0, // Skip to: 8381 + /* 5635 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5639 */ MCD_OPC_Decode, + 159, + 14, + 65, // Opcode: SHSAX + /* 5643 */ MCD_OPC_FilterValue, + 3, + 39, + 0, + 0, // Skip to: 5687 + /* 5648 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5651 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5669 + /* 5656 */ MCD_OPC_CheckPredicate, + 0, + 160, + 10, + 0, // Skip to: 8381 + /* 5661 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5665 */ MCD_OPC_Decode, + 239, + 13, + 65, // Opcode: QSUB16 + /* 5669 */ MCD_OPC_FilterValue, + 1, + 147, + 10, + 0, // Skip to: 8381 + /* 5674 */ MCD_OPC_CheckPredicate, + 0, + 142, + 10, + 0, // Skip to: 8381 + /* 5679 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5683 */ MCD_OPC_Decode, + 160, + 14, + 65, // Opcode: SHSUB16 + /* 5687 */ MCD_OPC_FilterValue, + 4, + 39, + 0, + 0, // Skip to: 5731 + /* 5692 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5695 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5713 + /* 5700 */ MCD_OPC_CheckPredicate, + 0, + 116, + 10, + 0, // Skip to: 8381 + /* 5705 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5709 */ MCD_OPC_Decode, + 233, + 13, + 65, // Opcode: QADD8 + /* 5713 */ MCD_OPC_FilterValue, + 1, + 103, + 10, + 0, // Skip to: 8381 + /* 5718 */ MCD_OPC_CheckPredicate, + 0, + 98, + 10, + 0, // Skip to: 8381 + /* 5723 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5727 */ MCD_OPC_Decode, + 157, + 14, + 65, // Opcode: SHADD8 + /* 5731 */ MCD_OPC_FilterValue, + 7, + 85, + 10, + 0, // Skip to: 8381 + /* 5736 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5739 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 5757 + /* 5744 */ MCD_OPC_CheckPredicate, + 0, + 72, + 10, + 0, // Skip to: 8381 + /* 5749 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5753 */ MCD_OPC_Decode, + 240, + 13, + 65, // Opcode: QSUB8 + /* 5757 */ MCD_OPC_FilterValue, + 1, + 59, + 10, + 0, // Skip to: 8381 + /* 5762 */ MCD_OPC_CheckPredicate, + 0, + 54, + 10, + 0, // Skip to: 8381 + /* 5767 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 5771 */ MCD_OPC_Decode, + 161, + 14, + 65, // Opcode: SHSUB8 + /* 5775 */ MCD_OPC_FilterValue, + 1, + 194, + 0, + 0, // Skip to: 5974 + /* 5780 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 5783 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5797 + /* 5788 */ MCD_OPC_CheckPredicate, + 1, + 28, + 10, + 0, // Skip to: 8381 + /* 5793 */ MCD_OPC_Decode, + 207, + 14, + 74, // Opcode: SSAT + /* 5797 */ MCD_OPC_FilterValue, + 1, + 19, + 10, + 0, // Skip to: 8381 + /* 5802 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 5805 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 5862 + /* 5810 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5813 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 5834 + /* 5818 */ MCD_OPC_CheckPredicate, + 1, + 254, + 9, + 0, // Skip to: 8381 + /* 5823 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 247, + 9, + 0, // Skip to: 8381 + /* 5830 */ MCD_OPC_Decode, + 208, + 14, + 75, // Opcode: SSAT16 + /* 5834 */ MCD_OPC_FilterValue, + 1, + 238, + 9, + 0, // Skip to: 8381 + /* 5839 */ MCD_OPC_CheckPredicate, + 1, + 233, + 9, + 0, // Skip to: 8381 + /* 5844 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 226, + 9, + 0, // Skip to: 8381 + /* 5851 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 219, + 9, + 0, // Skip to: 8381 + /* 5858 */ MCD_OPC_Decode, + 242, + 13, + 35, // Opcode: REV + /* 5862 */ MCD_OPC_FilterValue, + 1, + 79, + 0, + 0, // Skip to: 5946 + /* 5867 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5870 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 5908 + /* 5875 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 5895 + /* 5880 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 5895 + /* 5887 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5891 */ MCD_OPC_Decode, + 153, + 15, + 70, // Opcode: SXTB + /* 5895 */ MCD_OPC_CheckPredicate, + 1, + 177, + 9, + 0, // Skip to: 8381 + /* 5900 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5904 */ MCD_OPC_Decode, + 150, + 15, + 71, // Opcode: SXTAB + /* 5908 */ MCD_OPC_FilterValue, + 1, + 164, + 9, + 0, // Skip to: 8381 + /* 5913 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 5933 + /* 5918 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 5933 + /* 5925 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5929 */ MCD_OPC_Decode, + 155, + 15, + 70, // Opcode: SXTH + /* 5933 */ MCD_OPC_CheckPredicate, + 1, + 139, + 9, + 0, // Skip to: 8381 + /* 5938 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 5942 */ MCD_OPC_Decode, + 152, + 15, + 71, // Opcode: SXTAH + /* 5946 */ MCD_OPC_FilterValue, + 2, + 126, + 9, + 0, // Skip to: 8381 + /* 5951 */ MCD_OPC_CheckPredicate, + 1, + 121, + 9, + 0, // Skip to: 8381 + /* 5956 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 114, + 9, + 0, // Skip to: 8381 + /* 5963 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 107, + 9, + 0, // Skip to: 8381 + /* 5970 */ MCD_OPC_Decode, + 243, + 13, + 35, // Opcode: REV16 + /* 5974 */ MCD_OPC_FilterValue, + 2, + 30, + 0, + 0, // Skip to: 6009 + /* 5979 */ MCD_OPC_CheckPredicate, + 20, + 93, + 9, + 0, // Skip to: 8381 + /* 5984 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 86, + 9, + 0, // Skip to: 8381 + /* 5991 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 79, + 9, + 0, // Skip to: 8381 + /* 5998 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 72, + 9, + 0, // Skip to: 8381 + /* 6005 */ MCD_OPC_Decode, + 172, + 15, + 30, // Opcode: UDIV + /* 6009 */ MCD_OPC_FilterValue, + 3, + 63, + 9, + 0, // Skip to: 8381 + /* 6014 */ MCD_OPC_CheckPredicate, + 13, + 58, + 9, + 0, // Skip to: 8381 + /* 6019 */ MCD_OPC_CheckField, + 5, + 2, + 2, + 51, + 9, + 0, // Skip to: 8381 + /* 6026 */ MCD_OPC_Decode, + 141, + 14, + 76, // Opcode: SBFX + /* 6030 */ MCD_OPC_FilterValue, + 2, + 155, + 2, + 0, // Skip to: 6702 + /* 6035 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 6038 */ MCD_OPC_FilterValue, + 0, + 121, + 0, + 0, // Skip to: 6164 + /* 6043 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6046 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 6082 + /* 6051 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 6054 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6068 + /* 6059 */ MCD_OPC_CheckPredicate, + 0, + 13, + 9, + 0, // Skip to: 8381 + /* 6064 */ MCD_OPC_Decode, + 246, + 14, + 55, // Opcode: STRB_POST_REG + /* 6068 */ MCD_OPC_FilterValue, + 1, + 4, + 9, + 0, // Skip to: 8381 + /* 6073 */ MCD_OPC_CheckPredicate, + 0, + 255, + 8, + 0, // Skip to: 8381 + /* 6078 */ MCD_OPC_Decode, + 250, + 14, + 77, // Opcode: STRBrs + /* 6082 */ MCD_OPC_FilterValue, + 1, + 246, + 8, + 0, // Skip to: 8381 + /* 6087 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 6090 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 6127 + /* 6095 */ MCD_OPC_CheckPredicate, + 15, + 18, + 0, + 0, // Skip to: 6118 + /* 6100 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 6118 + /* 6107 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 6118 + /* 6114 */ MCD_OPC_Decode, + 230, + 13, + 64, // Opcode: PLIrs + /* 6118 */ MCD_OPC_CheckPredicate, + 0, + 210, + 8, + 0, // Skip to: 8381 + /* 6123 */ MCD_OPC_Decode, + 195, + 6, + 55, // Opcode: LDRB_POST_REG + /* 6127 */ MCD_OPC_FilterValue, + 1, + 201, + 8, + 0, // Skip to: 8381 + /* 6132 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 6155 + /* 6137 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 0, + 0, // Skip to: 6155 + /* 6144 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 6155 + /* 6151 */ MCD_OPC_Decode, + 228, + 13, + 64, // Opcode: PLDrs + /* 6155 */ MCD_OPC_CheckPredicate, + 0, + 173, + 8, + 0, // Skip to: 8381 + /* 6160 */ MCD_OPC_Decode, + 199, + 6, + 77, // Opcode: LDRBrs + /* 6164 */ MCD_OPC_FilterValue, + 1, + 164, + 8, + 0, // Skip to: 8381 + /* 6169 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 6172 */ MCD_OPC_FilterValue, + 0, + 158, + 0, + 0, // Skip to: 6335 + /* 6177 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 6180 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 6238 + /* 6185 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6188 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 6213 + /* 6193 */ MCD_OPC_CheckPredicate, + 0, + 135, + 8, + 0, // Skip to: 8381 + /* 6198 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 128, + 8, + 0, // Skip to: 8381 + /* 6205 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6209 */ MCD_OPC_Decode, + 167, + 15, + 65, // Opcode: UADD16 + /* 6213 */ MCD_OPC_FilterValue, + 1, + 115, + 8, + 0, // Skip to: 8381 + /* 6218 */ MCD_OPC_CheckPredicate, + 0, + 110, + 8, + 0, // Skip to: 8381 + /* 6223 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 103, + 8, + 0, // Skip to: 8381 + /* 6230 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6234 */ MCD_OPC_Decode, + 168, + 15, + 65, // Opcode: UADD8 + /* 6238 */ MCD_OPC_FilterValue, + 2, + 62, + 0, + 0, // Skip to: 6305 + /* 6243 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6246 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 6267 + /* 6251 */ MCD_OPC_CheckPredicate, + 1, + 77, + 8, + 0, // Skip to: 8381 + /* 6256 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 70, + 8, + 0, // Skip to: 8381 + /* 6263 */ MCD_OPC_Decode, + 170, + 14, + 19, // Opcode: SMLALD + /* 6267 */ MCD_OPC_FilterValue, + 1, + 61, + 8, + 0, // Skip to: 8381 + /* 6272 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6275 */ MCD_OPC_FilterValue, + 0, + 53, + 8, + 0, // Skip to: 8381 + /* 6280 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 6296 + /* 6285 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 6296 + /* 6292 */ MCD_OPC_Decode, + 186, + 14, + 30, // Opcode: SMMUL + /* 6296 */ MCD_OPC_CheckPredicate, + 1, + 32, + 8, + 0, // Skip to: 8381 + /* 6301 */ MCD_OPC_Decode, + 182, + 14, + 39, // Opcode: SMMLA + /* 6305 */ MCD_OPC_FilterValue, + 3, + 23, + 8, + 0, // Skip to: 8381 + /* 6310 */ MCD_OPC_CheckPredicate, + 13, + 11, + 0, + 0, // Skip to: 6326 + /* 6315 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 4, + 0, + 0, // Skip to: 6326 + /* 6322 */ MCD_OPC_Decode, + 199, + 5, + 78, // Opcode: BFC + /* 6326 */ MCD_OPC_CheckPredicate, + 13, + 2, + 8, + 0, // Skip to: 8381 + /* 6331 */ MCD_OPC_Decode, + 200, + 5, + 79, // Opcode: BFI + /* 6335 */ MCD_OPC_FilterValue, + 1, + 102, + 0, + 0, // Skip to: 6442 + /* 6340 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6343 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 6371 + /* 6348 */ MCD_OPC_CheckPredicate, + 1, + 236, + 7, + 0, // Skip to: 8381 + /* 6353 */ MCD_OPC_CheckField, + 23, + 2, + 2, + 229, + 7, + 0, // Skip to: 8381 + /* 6360 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 222, + 7, + 0, // Skip to: 8381 + /* 6367 */ MCD_OPC_Decode, + 171, + 14, + 19, // Opcode: SMLALDX + /* 6371 */ MCD_OPC_FilterValue, + 1, + 213, + 7, + 0, // Skip to: 8381 + /* 6376 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 6379 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 6404 + /* 6384 */ MCD_OPC_CheckPredicate, + 0, + 200, + 7, + 0, // Skip to: 8381 + /* 6389 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 193, + 7, + 0, // Skip to: 8381 + /* 6396 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6400 */ MCD_OPC_Decode, + 169, + 15, + 65, // Opcode: UASX + /* 6404 */ MCD_OPC_FilterValue, + 2, + 180, + 7, + 0, // Skip to: 8381 + /* 6409 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6412 */ MCD_OPC_FilterValue, + 0, + 172, + 7, + 0, // Skip to: 8381 + /* 6417 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 6433 + /* 6422 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 0, + 0, // Skip to: 6433 + /* 6429 */ MCD_OPC_Decode, + 187, + 14, + 30, // Opcode: SMMULR + /* 6433 */ MCD_OPC_CheckPredicate, + 1, + 151, + 7, + 0, // Skip to: 8381 + /* 6438 */ MCD_OPC_Decode, + 183, + 14, + 39, // Opcode: SMMLAR + /* 6442 */ MCD_OPC_FilterValue, + 2, + 85, + 0, + 0, // Skip to: 6532 + /* 6447 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6450 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 6504 + /* 6455 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6458 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 6479 + /* 6463 */ MCD_OPC_CheckPredicate, + 1, + 121, + 7, + 0, // Skip to: 8381 + /* 6468 */ MCD_OPC_CheckField, + 23, + 2, + 2, + 114, + 7, + 0, // Skip to: 8381 + /* 6475 */ MCD_OPC_Decode, + 180, + 14, + 19, // Opcode: SMLSLD + /* 6479 */ MCD_OPC_FilterValue, + 1, + 105, + 7, + 0, // Skip to: 8381 + /* 6484 */ MCD_OPC_CheckPredicate, + 0, + 100, + 7, + 0, // Skip to: 8381 + /* 6489 */ MCD_OPC_CheckField, + 23, + 2, + 0, + 93, + 7, + 0, // Skip to: 8381 + /* 6496 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6500 */ MCD_OPC_Decode, + 192, + 15, + 65, // Opcode: USAX + /* 6504 */ MCD_OPC_FilterValue, + 1, + 80, + 7, + 0, // Skip to: 8381 + /* 6509 */ MCD_OPC_CheckPredicate, + 1, + 75, + 7, + 0, // Skip to: 8381 + /* 6514 */ MCD_OPC_CheckField, + 23, + 2, + 2, + 68, + 7, + 0, // Skip to: 8381 + /* 6521 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 61, + 7, + 0, // Skip to: 8381 + /* 6528 */ MCD_OPC_Decode, + 184, + 14, + 39, // Opcode: SMMLS + /* 6532 */ MCD_OPC_FilterValue, + 3, + 52, + 7, + 0, // Skip to: 8381 + /* 6537 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 6540 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 6598 + /* 6545 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6548 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 6573 + /* 6553 */ MCD_OPC_CheckPredicate, + 0, + 31, + 7, + 0, // Skip to: 8381 + /* 6558 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 24, + 7, + 0, // Skip to: 8381 + /* 6565 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6569 */ MCD_OPC_Decode, + 193, + 15, + 65, // Opcode: USUB16 + /* 6573 */ MCD_OPC_FilterValue, + 1, + 11, + 7, + 0, // Skip to: 8381 + /* 6578 */ MCD_OPC_CheckPredicate, + 0, + 6, + 7, + 0, // Skip to: 8381 + /* 6583 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 255, + 6, + 0, // Skip to: 8381 + /* 6590 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6594 */ MCD_OPC_Decode, + 194, + 15, + 65, // Opcode: USUB8 + /* 6598 */ MCD_OPC_FilterValue, + 1, + 49, + 0, + 0, // Skip to: 6652 + /* 6603 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6606 */ MCD_OPC_FilterValue, + 0, + 234, + 6, + 0, // Skip to: 8381 + /* 6611 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6614 */ MCD_OPC_FilterValue, + 0, + 226, + 6, + 0, // Skip to: 8381 + /* 6619 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 6639 + /* 6624 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 6639 + /* 6631 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 6635 */ MCD_OPC_Decode, + 199, + 15, + 70, // Opcode: UXTB16 + /* 6639 */ MCD_OPC_CheckPredicate, + 1, + 201, + 6, + 0, // Skip to: 8381 + /* 6644 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 6648 */ MCD_OPC_Decode, + 196, + 15, + 71, // Opcode: UXTAB16 + /* 6652 */ MCD_OPC_FilterValue, + 2, + 188, + 6, + 0, // Skip to: 8381 + /* 6657 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6660 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 6681 + /* 6665 */ MCD_OPC_CheckPredicate, + 1, + 175, + 6, + 0, // Skip to: 8381 + /* 6670 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 168, + 6, + 0, // Skip to: 8381 + /* 6677 */ MCD_OPC_Decode, + 181, + 14, + 19, // Opcode: SMLSLDX + /* 6681 */ MCD_OPC_FilterValue, + 1, + 159, + 6, + 0, // Skip to: 8381 + /* 6686 */ MCD_OPC_CheckPredicate, + 1, + 154, + 6, + 0, // Skip to: 8381 + /* 6691 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 147, + 6, + 0, // Skip to: 8381 + /* 6698 */ MCD_OPC_Decode, + 185, + 14, + 39, // Opcode: SMMLSR + /* 6702 */ MCD_OPC_FilterValue, + 3, + 138, + 6, + 0, // Skip to: 8381 + /* 6707 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 6710 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 6790 + /* 6715 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6718 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 6754 + /* 6723 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 6726 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6740 + /* 6731 */ MCD_OPC_CheckPredicate, + 0, + 109, + 6, + 0, // Skip to: 8381 + /* 6736 */ MCD_OPC_Decode, + 244, + 14, + 55, // Opcode: STRBT_POST_REG + /* 6740 */ MCD_OPC_FilterValue, + 1, + 100, + 6, + 0, // Skip to: 8381 + /* 6745 */ MCD_OPC_CheckPredicate, + 0, + 95, + 6, + 0, // Skip to: 8381 + /* 6750 */ MCD_OPC_Decode, + 248, + 14, + 72, // Opcode: STRB_PRE_REG + /* 6754 */ MCD_OPC_FilterValue, + 1, + 86, + 6, + 0, // Skip to: 8381 + /* 6759 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 6762 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6776 + /* 6767 */ MCD_OPC_CheckPredicate, + 0, + 73, + 6, + 0, // Skip to: 8381 + /* 6772 */ MCD_OPC_Decode, + 193, + 6, + 55, // Opcode: LDRBT_POST_REG + /* 6776 */ MCD_OPC_FilterValue, + 1, + 64, + 6, + 0, // Skip to: 8381 + /* 6781 */ MCD_OPC_CheckPredicate, + 0, + 59, + 6, + 0, // Skip to: 8381 + /* 6786 */ MCD_OPC_Decode, + 197, + 6, + 73, // Opcode: LDRB_PRE_REG + /* 6790 */ MCD_OPC_FilterValue, + 1, + 50, + 6, + 0, // Skip to: 8381 + /* 6795 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 6798 */ MCD_OPC_FilterValue, + 0, + 11, + 1, + 0, // Skip to: 7070 + /* 6803 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 6806 */ MCD_OPC_FilterValue, + 0, + 39, + 0, + 0, // Skip to: 6850 + /* 6811 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6814 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 6832 + /* 6819 */ MCD_OPC_CheckPredicate, + 0, + 21, + 6, + 0, // Skip to: 8381 + /* 6824 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6828 */ MCD_OPC_Decode, + 182, + 15, + 65, // Opcode: UQADD16 + /* 6832 */ MCD_OPC_FilterValue, + 1, + 8, + 6, + 0, // Skip to: 8381 + /* 6837 */ MCD_OPC_CheckPredicate, + 0, + 3, + 6, + 0, // Skip to: 8381 + /* 6842 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6846 */ MCD_OPC_Decode, + 173, + 15, + 65, // Opcode: UHADD16 + /* 6850 */ MCD_OPC_FilterValue, + 1, + 39, + 0, + 0, // Skip to: 6894 + /* 6855 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6858 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 6876 + /* 6863 */ MCD_OPC_CheckPredicate, + 0, + 233, + 5, + 0, // Skip to: 8381 + /* 6868 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6872 */ MCD_OPC_Decode, + 184, + 15, + 65, // Opcode: UQASX + /* 6876 */ MCD_OPC_FilterValue, + 1, + 220, + 5, + 0, // Skip to: 8381 + /* 6881 */ MCD_OPC_CheckPredicate, + 0, + 215, + 5, + 0, // Skip to: 8381 + /* 6886 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6890 */ MCD_OPC_Decode, + 175, + 15, + 65, // Opcode: UHASX + /* 6894 */ MCD_OPC_FilterValue, + 2, + 39, + 0, + 0, // Skip to: 6938 + /* 6899 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6902 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 6920 + /* 6907 */ MCD_OPC_CheckPredicate, + 0, + 189, + 5, + 0, // Skip to: 8381 + /* 6912 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6916 */ MCD_OPC_Decode, + 185, + 15, + 65, // Opcode: UQSAX + /* 6920 */ MCD_OPC_FilterValue, + 1, + 176, + 5, + 0, // Skip to: 8381 + /* 6925 */ MCD_OPC_CheckPredicate, + 0, + 171, + 5, + 0, // Skip to: 8381 + /* 6930 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6934 */ MCD_OPC_Decode, + 176, + 15, + 65, // Opcode: UHSAX + /* 6938 */ MCD_OPC_FilterValue, + 3, + 39, + 0, + 0, // Skip to: 6982 + /* 6943 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6946 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 6964 + /* 6951 */ MCD_OPC_CheckPredicate, + 0, + 145, + 5, + 0, // Skip to: 8381 + /* 6956 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6960 */ MCD_OPC_Decode, + 186, + 15, + 65, // Opcode: UQSUB16 + /* 6964 */ MCD_OPC_FilterValue, + 1, + 132, + 5, + 0, // Skip to: 8381 + /* 6969 */ MCD_OPC_CheckPredicate, + 0, + 127, + 5, + 0, // Skip to: 8381 + /* 6974 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 6978 */ MCD_OPC_Decode, + 177, + 15, + 65, // Opcode: UHSUB16 + /* 6982 */ MCD_OPC_FilterValue, + 4, + 39, + 0, + 0, // Skip to: 7026 + /* 6987 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6990 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 7008 + /* 6995 */ MCD_OPC_CheckPredicate, + 0, + 101, + 5, + 0, // Skip to: 8381 + /* 7000 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 7004 */ MCD_OPC_Decode, + 183, + 15, + 65, // Opcode: UQADD8 + /* 7008 */ MCD_OPC_FilterValue, + 1, + 88, + 5, + 0, // Skip to: 8381 + /* 7013 */ MCD_OPC_CheckPredicate, + 0, + 83, + 5, + 0, // Skip to: 8381 + /* 7018 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 7022 */ MCD_OPC_Decode, + 174, + 15, + 65, // Opcode: UHADD8 + /* 7026 */ MCD_OPC_FilterValue, + 7, + 70, + 5, + 0, // Skip to: 8381 + /* 7031 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7034 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 7052 + /* 7039 */ MCD_OPC_CheckPredicate, + 0, + 57, + 5, + 0, // Skip to: 8381 + /* 7044 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 7048 */ MCD_OPC_Decode, + 187, + 15, + 65, // Opcode: UQSUB8 + /* 7052 */ MCD_OPC_FilterValue, + 1, + 44, + 5, + 0, // Skip to: 8381 + /* 7057 */ MCD_OPC_CheckPredicate, + 0, + 39, + 5, + 0, // Skip to: 8381 + /* 7062 */ MCD_OPC_SoftFail, + 0, + 128, + 30 /* 0xf00 */, + /* 7066 */ MCD_OPC_Decode, + 178, + 15, + 65, // Opcode: UHSUB8 + /* 7070 */ MCD_OPC_FilterValue, + 1, + 194, + 0, + 0, // Skip to: 7269 + /* 7075 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 7078 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7092 + /* 7083 */ MCD_OPC_CheckPredicate, + 1, + 13, + 5, + 0, // Skip to: 8381 + /* 7088 */ MCD_OPC_Decode, + 190, + 15, + 74, // Opcode: USAT + /* 7092 */ MCD_OPC_FilterValue, + 1, + 4, + 5, + 0, // Skip to: 8381 + /* 7097 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7100 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 7157 + /* 7105 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7108 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 7129 + /* 7113 */ MCD_OPC_CheckPredicate, + 1, + 239, + 4, + 0, // Skip to: 8381 + /* 7118 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 232, + 4, + 0, // Skip to: 8381 + /* 7125 */ MCD_OPC_Decode, + 191, + 15, + 75, // Opcode: USAT16 + /* 7129 */ MCD_OPC_FilterValue, + 1, + 223, + 4, + 0, // Skip to: 8381 + /* 7134 */ MCD_OPC_CheckPredicate, + 13, + 218, + 4, + 0, // Skip to: 8381 + /* 7139 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 211, + 4, + 0, // Skip to: 8381 + /* 7146 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 204, + 4, + 0, // Skip to: 8381 + /* 7153 */ MCD_OPC_Decode, + 241, + 13, + 35, // Opcode: RBIT + /* 7157 */ MCD_OPC_FilterValue, + 1, + 79, + 0, + 0, // Skip to: 7241 + /* 7162 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7165 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 7203 + /* 7170 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 7190 + /* 7175 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 7190 + /* 7182 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 7186 */ MCD_OPC_Decode, + 198, + 15, + 70, // Opcode: UXTB + /* 7190 */ MCD_OPC_CheckPredicate, + 1, + 162, + 4, + 0, // Skip to: 8381 + /* 7195 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 7199 */ MCD_OPC_Decode, + 195, + 15, + 71, // Opcode: UXTAB + /* 7203 */ MCD_OPC_FilterValue, + 1, + 149, + 4, + 0, // Skip to: 8381 + /* 7208 */ MCD_OPC_CheckPredicate, + 1, + 15, + 0, + 0, // Skip to: 7228 + /* 7213 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 8, + 0, + 0, // Skip to: 7228 + /* 7220 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 7224 */ MCD_OPC_Decode, + 200, + 15, + 70, // Opcode: UXTH + /* 7228 */ MCD_OPC_CheckPredicate, + 1, + 124, + 4, + 0, // Skip to: 8381 + /* 7233 */ MCD_OPC_SoftFail, + 128, + 6 /* 0x300 */, + 0, + /* 7237 */ MCD_OPC_Decode, + 197, + 15, + 71, // Opcode: UXTAH + /* 7241 */ MCD_OPC_FilterValue, + 2, + 111, + 4, + 0, // Skip to: 8381 + /* 7246 */ MCD_OPC_CheckPredicate, + 1, + 106, + 4, + 0, // Skip to: 8381 + /* 7251 */ MCD_OPC_CheckField, + 16, + 5, + 31, + 99, + 4, + 0, // Skip to: 8381 + /* 7258 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 92, + 4, + 0, // Skip to: 8381 + /* 7265 */ MCD_OPC_Decode, + 244, + 13, + 35, // Opcode: REVSH + /* 7269 */ MCD_OPC_FilterValue, + 3, + 83, + 4, + 0, // Skip to: 8381 + /* 7274 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 7277 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7291 + /* 7282 */ MCD_OPC_CheckPredicate, + 13, + 70, + 4, + 0, // Skip to: 8381 + /* 7287 */ MCD_OPC_Decode, + 170, + 15, + 76, // Opcode: UBFX + /* 7291 */ MCD_OPC_FilterValue, + 3, + 61, + 4, + 0, // Skip to: 8381 + /* 7296 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 7299 */ MCD_OPC_FilterValue, + 1, + 53, + 4, + 0, // Skip to: 8381 + /* 7304 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7307 */ MCD_OPC_FilterValue, + 1, + 45, + 4, + 0, // Skip to: 8381 + /* 7312 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7315 */ MCD_OPC_FilterValue, + 14, + 37, + 4, + 0, // Skip to: 8381 + /* 7320 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 7323 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7345 + /* 7328 */ MCD_OPC_CheckPredicate, + 21, + 34, + 0, + 0, // Skip to: 7367 + /* 7333 */ MCD_OPC_CheckField, + 8, + 12, + 222, + 29, + 26, + 0, + 0, // Skip to: 7367 + /* 7341 */ MCD_OPC_Decode, + 161, + 15, + 51, // Opcode: TRAPNaCl + /* 7345 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7367 + /* 7350 */ MCD_OPC_CheckPredicate, + 0, + 12, + 0, + 0, // Skip to: 7367 + /* 7355 */ MCD_OPC_CheckField, + 8, + 12, + 222, + 31, + 4, + 0, + 0, // Skip to: 7367 + /* 7363 */ MCD_OPC_Decode, + 160, + 15, + 51, // Opcode: TRAP + /* 7367 */ MCD_OPC_CheckPredicate, + 0, + 241, + 3, + 0, // Skip to: 8381 + /* 7372 */ MCD_OPC_Decode, + 171, + 15, + 15, // Opcode: UDF + /* 7376 */ MCD_OPC_FilterValue, + 4, + 75, + 3, + 0, // Skip to: 8224 + /* 7381 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 7384 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7398 + /* 7389 */ MCD_OPC_CheckPredicate, + 0, + 219, + 3, + 0, // Skip to: 8381 + /* 7394 */ MCD_OPC_Decode, + 235, + 14, + 80, // Opcode: STMDA + /* 7398 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 7436 + /* 7403 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7427 + /* 7408 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7427 + /* 7415 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7427 + /* 7423 */ MCD_OPC_Decode, + 245, + 13, + 81, // Opcode: RFEDA + /* 7427 */ MCD_OPC_CheckPredicate, + 0, + 181, + 3, + 0, // Skip to: 8381 + /* 7432 */ MCD_OPC_Decode, + 184, + 6, + 80, // Opcode: LDMDA + /* 7436 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7450 + /* 7441 */ MCD_OPC_CheckPredicate, + 0, + 167, + 3, + 0, // Skip to: 8381 + /* 7446 */ MCD_OPC_Decode, + 236, + 14, + 82, // Opcode: STMDA_UPD + /* 7450 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 7488 + /* 7455 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7479 + /* 7460 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7479 + /* 7467 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7479 + /* 7475 */ MCD_OPC_Decode, + 246, + 13, + 81, // Opcode: RFEDA_UPD + /* 7479 */ MCD_OPC_CheckPredicate, + 0, + 129, + 3, + 0, // Skip to: 8381 + /* 7484 */ MCD_OPC_Decode, + 185, + 6, + 82, // Opcode: LDMDA_UPD + /* 7488 */ MCD_OPC_FilterValue, + 4, + 34, + 0, + 0, // Skip to: 7527 + /* 7493 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7518 + /* 7498 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7518 + /* 7505 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7518 + /* 7514 */ MCD_OPC_Decode, + 199, + 14, + 83, // Opcode: SRSDA + /* 7518 */ MCD_OPC_CheckPredicate, + 0, + 90, + 3, + 0, // Skip to: 8381 + /* 7523 */ MCD_OPC_Decode, + 205, + 30, + 80, // Opcode: sysSTMDA + /* 7527 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 7541 + /* 7532 */ MCD_OPC_CheckPredicate, + 0, + 76, + 3, + 0, // Skip to: 8381 + /* 7537 */ MCD_OPC_Decode, + 197, + 30, + 80, // Opcode: sysLDMDA + /* 7541 */ MCD_OPC_FilterValue, + 6, + 34, + 0, + 0, // Skip to: 7580 + /* 7546 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7571 + /* 7551 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7571 + /* 7558 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7571 + /* 7567 */ MCD_OPC_Decode, + 200, + 14, + 83, // Opcode: SRSDA_UPD + /* 7571 */ MCD_OPC_CheckPredicate, + 0, + 37, + 3, + 0, // Skip to: 8381 + /* 7576 */ MCD_OPC_Decode, + 206, + 30, + 82, // Opcode: sysSTMDA_UPD + /* 7580 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 7594 + /* 7585 */ MCD_OPC_CheckPredicate, + 0, + 23, + 3, + 0, // Skip to: 8381 + /* 7590 */ MCD_OPC_Decode, + 198, + 30, + 82, // Opcode: sysLDMDA_UPD + /* 7594 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 7608 + /* 7599 */ MCD_OPC_CheckPredicate, + 0, + 9, + 3, + 0, // Skip to: 8381 + /* 7604 */ MCD_OPC_Decode, + 239, + 14, + 80, // Opcode: STMIA + /* 7608 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 7646 + /* 7613 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7637 + /* 7618 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7637 + /* 7625 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7637 + /* 7633 */ MCD_OPC_Decode, + 249, + 13, + 81, // Opcode: RFEIA + /* 7637 */ MCD_OPC_CheckPredicate, + 0, + 227, + 2, + 0, // Skip to: 8381 + /* 7642 */ MCD_OPC_Decode, + 188, + 6, + 80, // Opcode: LDMIA + /* 7646 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 7660 + /* 7651 */ MCD_OPC_CheckPredicate, + 0, + 213, + 2, + 0, // Skip to: 8381 + /* 7656 */ MCD_OPC_Decode, + 240, + 14, + 82, // Opcode: STMIA_UPD + /* 7660 */ MCD_OPC_FilterValue, + 11, + 33, + 0, + 0, // Skip to: 7698 + /* 7665 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7689 + /* 7670 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7689 + /* 7677 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7689 + /* 7685 */ MCD_OPC_Decode, + 250, + 13, + 81, // Opcode: RFEIA_UPD + /* 7689 */ MCD_OPC_CheckPredicate, + 0, + 175, + 2, + 0, // Skip to: 8381 + /* 7694 */ MCD_OPC_Decode, + 189, + 6, + 82, // Opcode: LDMIA_UPD + /* 7698 */ MCD_OPC_FilterValue, + 12, + 34, + 0, + 0, // Skip to: 7737 + /* 7703 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7728 + /* 7708 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7728 + /* 7715 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7728 + /* 7724 */ MCD_OPC_Decode, + 203, + 14, + 83, // Opcode: SRSIA + /* 7728 */ MCD_OPC_CheckPredicate, + 0, + 136, + 2, + 0, // Skip to: 8381 + /* 7733 */ MCD_OPC_Decode, + 209, + 30, + 80, // Opcode: sysSTMIA + /* 7737 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 7751 + /* 7742 */ MCD_OPC_CheckPredicate, + 0, + 122, + 2, + 0, // Skip to: 8381 + /* 7747 */ MCD_OPC_Decode, + 201, + 30, + 80, // Opcode: sysLDMIA + /* 7751 */ MCD_OPC_FilterValue, + 14, + 34, + 0, + 0, // Skip to: 7790 + /* 7756 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7781 + /* 7761 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7781 + /* 7768 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7781 + /* 7777 */ MCD_OPC_Decode, + 204, + 14, + 83, // Opcode: SRSIA_UPD + /* 7781 */ MCD_OPC_CheckPredicate, + 0, + 83, + 2, + 0, // Skip to: 8381 + /* 7786 */ MCD_OPC_Decode, + 210, + 30, + 82, // Opcode: sysSTMIA_UPD + /* 7790 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 7804 + /* 7795 */ MCD_OPC_CheckPredicate, + 0, + 69, + 2, + 0, // Skip to: 8381 + /* 7800 */ MCD_OPC_Decode, + 202, + 30, + 82, // Opcode: sysLDMIA_UPD + /* 7804 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 7818 + /* 7809 */ MCD_OPC_CheckPredicate, + 0, + 55, + 2, + 0, // Skip to: 8381 + /* 7814 */ MCD_OPC_Decode, + 237, + 14, + 80, // Opcode: STMDB + /* 7818 */ MCD_OPC_FilterValue, + 17, + 33, + 0, + 0, // Skip to: 7856 + /* 7823 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7847 + /* 7828 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7847 + /* 7835 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7847 + /* 7843 */ MCD_OPC_Decode, + 247, + 13, + 81, // Opcode: RFEDB + /* 7847 */ MCD_OPC_CheckPredicate, + 0, + 17, + 2, + 0, // Skip to: 8381 + /* 7852 */ MCD_OPC_Decode, + 186, + 6, + 80, // Opcode: LDMDB + /* 7856 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 7870 + /* 7861 */ MCD_OPC_CheckPredicate, + 0, + 3, + 2, + 0, // Skip to: 8381 + /* 7866 */ MCD_OPC_Decode, + 238, + 14, + 82, // Opcode: STMDB_UPD + /* 7870 */ MCD_OPC_FilterValue, + 19, + 33, + 0, + 0, // Skip to: 7908 + /* 7875 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 7899 + /* 7880 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 7899 + /* 7887 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 7899 + /* 7895 */ MCD_OPC_Decode, + 248, + 13, + 81, // Opcode: RFEDB_UPD + /* 7899 */ MCD_OPC_CheckPredicate, + 0, + 221, + 1, + 0, // Skip to: 8381 + /* 7904 */ MCD_OPC_Decode, + 187, + 6, + 82, // Opcode: LDMDB_UPD + /* 7908 */ MCD_OPC_FilterValue, + 20, + 34, + 0, + 0, // Skip to: 7947 + /* 7913 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7938 + /* 7918 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7938 + /* 7925 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7938 + /* 7934 */ MCD_OPC_Decode, + 201, + 14, + 83, // Opcode: SRSDB + /* 7938 */ MCD_OPC_CheckPredicate, + 0, + 182, + 1, + 0, // Skip to: 8381 + /* 7943 */ MCD_OPC_Decode, + 207, + 30, + 80, // Opcode: sysSTMDB + /* 7947 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 7961 + /* 7952 */ MCD_OPC_CheckPredicate, + 0, + 168, + 1, + 0, // Skip to: 8381 + /* 7957 */ MCD_OPC_Decode, + 199, + 30, + 80, // Opcode: sysLDMDB + /* 7961 */ MCD_OPC_FilterValue, + 22, + 34, + 0, + 0, // Skip to: 8000 + /* 7966 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 7991 + /* 7971 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 7991 + /* 7978 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 7991 + /* 7987 */ MCD_OPC_Decode, + 202, + 14, + 83, // Opcode: SRSDB_UPD + /* 7991 */ MCD_OPC_CheckPredicate, + 0, + 129, + 1, + 0, // Skip to: 8381 + /* 7996 */ MCD_OPC_Decode, + 208, + 30, + 82, // Opcode: sysSTMDB_UPD + /* 8000 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 8014 + /* 8005 */ MCD_OPC_CheckPredicate, + 0, + 115, + 1, + 0, // Skip to: 8381 + /* 8010 */ MCD_OPC_Decode, + 200, + 30, + 82, // Opcode: sysLDMDB_UPD + /* 8014 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 8028 + /* 8019 */ MCD_OPC_CheckPredicate, + 0, + 101, + 1, + 0, // Skip to: 8381 + /* 8024 */ MCD_OPC_Decode, + 241, + 14, + 80, // Opcode: STMIB + /* 8028 */ MCD_OPC_FilterValue, + 25, + 33, + 0, + 0, // Skip to: 8066 + /* 8033 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 8057 + /* 8038 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 8057 + /* 8045 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 8057 + /* 8053 */ MCD_OPC_Decode, + 251, + 13, + 81, // Opcode: RFEIB + /* 8057 */ MCD_OPC_CheckPredicate, + 0, + 63, + 1, + 0, // Skip to: 8381 + /* 8062 */ MCD_OPC_Decode, + 190, + 6, + 80, // Opcode: LDMIB + /* 8066 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 8080 + /* 8071 */ MCD_OPC_CheckPredicate, + 0, + 49, + 1, + 0, // Skip to: 8381 + /* 8076 */ MCD_OPC_Decode, + 242, + 14, + 82, // Opcode: STMIB_UPD + /* 8080 */ MCD_OPC_FilterValue, + 27, + 33, + 0, + 0, // Skip to: 8118 + /* 8085 */ MCD_OPC_CheckPredicate, + 0, + 19, + 0, + 0, // Skip to: 8109 + /* 8090 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 12, + 0, + 0, // Skip to: 8109 + /* 8097 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 20, + 4, + 0, + 0, // Skip to: 8109 + /* 8105 */ MCD_OPC_Decode, + 252, + 13, + 81, // Opcode: RFEIB_UPD + /* 8109 */ MCD_OPC_CheckPredicate, + 0, + 11, + 1, + 0, // Skip to: 8381 + /* 8114 */ MCD_OPC_Decode, + 191, + 6, + 82, // Opcode: LDMIB_UPD + /* 8118 */ MCD_OPC_FilterValue, + 28, + 34, + 0, + 0, // Skip to: 8157 + /* 8123 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 8148 + /* 8128 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 8148 + /* 8135 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 8148 + /* 8144 */ MCD_OPC_Decode, + 205, + 14, + 83, // Opcode: SRSIB + /* 8148 */ MCD_OPC_CheckPredicate, + 0, + 228, + 0, + 0, // Skip to: 8381 + /* 8153 */ MCD_OPC_Decode, + 211, + 30, + 80, // Opcode: sysSTMIB + /* 8157 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 8171 + /* 8162 */ MCD_OPC_CheckPredicate, + 0, + 214, + 0, + 0, // Skip to: 8381 + /* 8167 */ MCD_OPC_Decode, + 203, + 30, + 80, // Opcode: sysLDMIB + /* 8171 */ MCD_OPC_FilterValue, + 30, + 34, + 0, + 0, // Skip to: 8210 + /* 8176 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 8201 + /* 8181 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 13, + 0, + 0, // Skip to: 8201 + /* 8188 */ MCD_OPC_CheckField, + 5, + 15, + 168, + 208, + 1, + 4, + 0, + 0, // Skip to: 8201 + /* 8197 */ MCD_OPC_Decode, + 206, + 14, + 83, // Opcode: SRSIB_UPD + /* 8201 */ MCD_OPC_CheckPredicate, + 0, + 175, + 0, + 0, // Skip to: 8381 + /* 8206 */ MCD_OPC_Decode, + 212, + 30, + 82, // Opcode: sysSTMIB_UPD + /* 8210 */ MCD_OPC_FilterValue, + 31, + 166, + 0, + 0, // Skip to: 8381 + /* 8215 */ MCD_OPC_CheckPredicate, + 0, + 161, + 0, + 0, // Skip to: 8381 + /* 8220 */ MCD_OPC_Decode, + 204, + 30, + 82, // Opcode: sysLDMIB_UPD + /* 8224 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 8292 + /* 8229 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 8232 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8246 + /* 8237 */ MCD_OPC_CheckPredicate, + 0, + 34, + 0, + 0, // Skip to: 8276 + /* 8242 */ MCD_OPC_Decode, + 215, + 5, + 84, // Opcode: Bcc + /* 8246 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 8276 + /* 8251 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 8267 + /* 8256 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 4, + 0, + 0, // Skip to: 8267 + /* 8263 */ MCD_OPC_Decode, + 206, + 5, + 84, // Opcode: BL + /* 8267 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 8276 + /* 8272 */ MCD_OPC_Decode, + 210, + 5, + 84, // Opcode: BL_pred + /* 8276 */ MCD_OPC_CheckPredicate, + 11, + 100, + 0, + 0, // Skip to: 8381 + /* 8281 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 93, + 0, + 0, // Skip to: 8381 + /* 8288 */ MCD_OPC_Decode, + 209, + 5, + 85, // Opcode: BLXi + /* 8292 */ MCD_OPC_FilterValue, + 6, + 63, + 0, + 0, // Skip to: 8360 + /* 8297 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 8300 */ MCD_OPC_FilterValue, + 4, + 25, + 0, + 0, // Skip to: 8330 + /* 8305 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 8321 + /* 8310 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 8321 + /* 8317 */ MCD_OPC_Decode, + 234, + 6, + 86, // Opcode: MCRR2 + /* 8321 */ MCD_OPC_CheckPredicate, + 0, + 55, + 0, + 0, // Skip to: 8381 + /* 8326 */ MCD_OPC_Decode, + 233, + 6, + 87, // Opcode: MCRR + /* 8330 */ MCD_OPC_FilterValue, + 5, + 46, + 0, + 0, // Skip to: 8381 + /* 8335 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 8351 + /* 8340 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 8351 + /* 8347 */ MCD_OPC_Decode, + 248, + 6, + 86, // Opcode: MRRC2 + /* 8351 */ MCD_OPC_CheckPredicate, + 0, + 25, + 0, + 0, // Skip to: 8381 + /* 8356 */ MCD_OPC_Decode, + 247, + 6, + 88, // Opcode: MRRC + /* 8360 */ MCD_OPC_FilterValue, + 7, + 16, + 0, + 0, // Skip to: 8381 + /* 8365 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 8381 + /* 8370 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 4, + 0, + 0, // Skip to: 8381 + /* 8377 */ MCD_OPC_Decode, + 147, + 15, + 89, // Opcode: SVC + /* 8381 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableCoProc32[] = { -/* 0 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 3 */ MCD_OPC_FilterValue, 12, 19, 1, 0, // Skip to: 283 -/* 8 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... -/* 11 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 49 -/* 16 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 19 */ MCD_OPC_FilterValue, 1, 101, 2, 0, // Skip to: 637 -/* 24 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 40 -/* 29 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 40 -/* 36 */ MCD_OPC_Decode, 190, 6, 90, // Opcode: STC2_OPTION -/* 40 */ MCD_OPC_CheckPredicate, 0, 80, 2, 0, // Skip to: 637 -/* 45 */ MCD_OPC_Decode, 198, 6, 90, // Opcode: STC_OPTION -/* 49 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 87 -/* 54 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 57 */ MCD_OPC_FilterValue, 1, 63, 2, 0, // Skip to: 637 -/* 62 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 78 -/* 67 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 78 -/* 74 */ MCD_OPC_Decode, 234, 4, 90, // Opcode: LDC2_OPTION -/* 78 */ MCD_OPC_CheckPredicate, 0, 42, 2, 0, // Skip to: 637 -/* 83 */ MCD_OPC_Decode, 242, 4, 90, // Opcode: LDC_OPTION -/* 87 */ MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 117 -/* 92 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 108 -/* 97 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 108 -/* 104 */ MCD_OPC_Decode, 191, 6, 90, // Opcode: STC2_POST -/* 108 */ MCD_OPC_CheckPredicate, 0, 12, 2, 0, // Skip to: 637 -/* 113 */ MCD_OPC_Decode, 199, 6, 90, // Opcode: STC_POST -/* 117 */ MCD_OPC_FilterValue, 3, 25, 0, 0, // Skip to: 147 -/* 122 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 138 -/* 127 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 138 -/* 134 */ MCD_OPC_Decode, 235, 4, 90, // Opcode: LDC2_POST -/* 138 */ MCD_OPC_CheckPredicate, 0, 238, 1, 0, // Skip to: 637 -/* 143 */ MCD_OPC_Decode, 243, 4, 90, // Opcode: LDC_POST -/* 147 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 185 -/* 152 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 155 */ MCD_OPC_FilterValue, 1, 221, 1, 0, // Skip to: 637 -/* 160 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 176 -/* 165 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 176 -/* 172 */ MCD_OPC_Decode, 186, 6, 90, // Opcode: STC2L_OPTION -/* 176 */ MCD_OPC_CheckPredicate, 0, 200, 1, 0, // Skip to: 637 -/* 181 */ MCD_OPC_Decode, 194, 6, 90, // Opcode: STCL_OPTION -/* 185 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 223 -/* 190 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 193 */ MCD_OPC_FilterValue, 1, 183, 1, 0, // Skip to: 637 -/* 198 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 214 -/* 203 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 214 -/* 210 */ MCD_OPC_Decode, 230, 4, 90, // Opcode: LDC2L_OPTION -/* 214 */ MCD_OPC_CheckPredicate, 0, 162, 1, 0, // Skip to: 637 -/* 219 */ MCD_OPC_Decode, 238, 4, 90, // Opcode: LDCL_OPTION -/* 223 */ MCD_OPC_FilterValue, 6, 25, 0, 0, // Skip to: 253 -/* 228 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 244 -/* 233 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 244 -/* 240 */ MCD_OPC_Decode, 187, 6, 90, // Opcode: STC2L_POST -/* 244 */ MCD_OPC_CheckPredicate, 0, 132, 1, 0, // Skip to: 637 -/* 249 */ MCD_OPC_Decode, 195, 6, 90, // Opcode: STCL_POST -/* 253 */ MCD_OPC_FilterValue, 7, 123, 1, 0, // Skip to: 637 -/* 258 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 274 -/* 263 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 274 -/* 270 */ MCD_OPC_Decode, 231, 4, 90, // Opcode: LDC2L_POST -/* 274 */ MCD_OPC_CheckPredicate, 0, 102, 1, 0, // Skip to: 637 -/* 279 */ MCD_OPC_Decode, 239, 4, 90, // Opcode: LDCL_POST -/* 283 */ MCD_OPC_FilterValue, 13, 243, 0, 0, // Skip to: 531 -/* 288 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... -/* 291 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 321 -/* 296 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 312 -/* 301 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 312 -/* 308 */ MCD_OPC_Decode, 189, 6, 90, // Opcode: STC2_OFFSET -/* 312 */ MCD_OPC_CheckPredicate, 0, 64, 1, 0, // Skip to: 637 -/* 317 */ MCD_OPC_Decode, 197, 6, 90, // Opcode: STC_OFFSET -/* 321 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 351 -/* 326 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 342 -/* 331 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 342 -/* 338 */ MCD_OPC_Decode, 233, 4, 90, // Opcode: LDC2_OFFSET -/* 342 */ MCD_OPC_CheckPredicate, 0, 34, 1, 0, // Skip to: 637 -/* 347 */ MCD_OPC_Decode, 241, 4, 90, // Opcode: LDC_OFFSET -/* 351 */ MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 381 -/* 356 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 372 -/* 361 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 372 -/* 368 */ MCD_OPC_Decode, 192, 6, 90, // Opcode: STC2_PRE -/* 372 */ MCD_OPC_CheckPredicate, 0, 4, 1, 0, // Skip to: 637 -/* 377 */ MCD_OPC_Decode, 200, 6, 90, // Opcode: STC_PRE -/* 381 */ MCD_OPC_FilterValue, 3, 25, 0, 0, // Skip to: 411 -/* 386 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 402 -/* 391 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 402 -/* 398 */ MCD_OPC_Decode, 236, 4, 90, // Opcode: LDC2_PRE -/* 402 */ MCD_OPC_CheckPredicate, 0, 230, 0, 0, // Skip to: 637 -/* 407 */ MCD_OPC_Decode, 244, 4, 90, // Opcode: LDC_PRE -/* 411 */ MCD_OPC_FilterValue, 4, 25, 0, 0, // Skip to: 441 -/* 416 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 432 -/* 421 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 432 -/* 428 */ MCD_OPC_Decode, 185, 6, 90, // Opcode: STC2L_OFFSET -/* 432 */ MCD_OPC_CheckPredicate, 0, 200, 0, 0, // Skip to: 637 -/* 437 */ MCD_OPC_Decode, 193, 6, 90, // Opcode: STCL_OFFSET -/* 441 */ MCD_OPC_FilterValue, 5, 25, 0, 0, // Skip to: 471 -/* 446 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 462 -/* 451 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 462 -/* 458 */ MCD_OPC_Decode, 229, 4, 90, // Opcode: LDC2L_OFFSET -/* 462 */ MCD_OPC_CheckPredicate, 0, 170, 0, 0, // Skip to: 637 -/* 467 */ MCD_OPC_Decode, 237, 4, 90, // Opcode: LDCL_OFFSET -/* 471 */ MCD_OPC_FilterValue, 6, 25, 0, 0, // Skip to: 501 -/* 476 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 492 -/* 481 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 492 -/* 488 */ MCD_OPC_Decode, 188, 6, 90, // Opcode: STC2L_PRE -/* 492 */ MCD_OPC_CheckPredicate, 0, 140, 0, 0, // Skip to: 637 -/* 497 */ MCD_OPC_Decode, 196, 6, 90, // Opcode: STCL_PRE -/* 501 */ MCD_OPC_FilterValue, 7, 131, 0, 0, // Skip to: 637 -/* 506 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 522 -/* 511 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 522 -/* 518 */ MCD_OPC_Decode, 232, 4, 90, // Opcode: LDC2L_PRE -/* 522 */ MCD_OPC_CheckPredicate, 0, 110, 0, 0, // Skip to: 637 -/* 527 */ MCD_OPC_Decode, 240, 4, 90, // Opcode: LDCL_PRE -/* 531 */ MCD_OPC_FilterValue, 14, 101, 0, 0, // Skip to: 637 -/* 536 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 539 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 569 -/* 544 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 560 -/* 549 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 560 -/* 556 */ MCD_OPC_Decode, 180, 4, 91, // Opcode: CDP2 -/* 560 */ MCD_OPC_CheckPredicate, 4, 72, 0, 0, // Skip to: 637 -/* 565 */ MCD_OPC_Decode, 179, 4, 92, // Opcode: CDP -/* 569 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 637 -/* 574 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 577 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 607 -/* 582 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 598 -/* 587 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 598 -/* 594 */ MCD_OPC_Decode, 165, 5, 93, // Opcode: MCR2 -/* 598 */ MCD_OPC_CheckPredicate, 0, 34, 0, 0, // Skip to: 637 -/* 603 */ MCD_OPC_Decode, 164, 5, 94, // Opcode: MCR -/* 607 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 637 -/* 612 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 628 -/* 617 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 628 -/* 624 */ MCD_OPC_Decode, 179, 5, 95, // Opcode: MRC2 -/* 628 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 637 -/* 633 */ MCD_OPC_Decode, 178, 5, 96, // Opcode: MRC -/* 637 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 3 */ MCD_OPC_FilterValue, + 12, + 19, + 1, + 0, // Skip to: 283 + /* 8 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 49 + /* 16 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 19 */ MCD_OPC_FilterValue, + 1, + 101, + 2, + 0, // Skip to: 637 + /* 24 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 40 + /* 29 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 40 + /* 36 */ MCD_OPC_Decode, + 217, + 14, + 90, // Opcode: STC2_OPTION + /* 40 */ MCD_OPC_CheckPredicate, + 0, + 80, + 2, + 0, // Skip to: 637 + /* 45 */ MCD_OPC_Decode, + 225, + 14, + 90, // Opcode: STC_OPTION + /* 49 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 87 + /* 54 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 57 */ MCD_OPC_FilterValue, + 1, + 63, + 2, + 0, // Skip to: 637 + /* 62 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 78 + /* 67 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 78 + /* 74 */ MCD_OPC_Decode, + 173, + 6, + 90, // Opcode: LDC2_OPTION + /* 78 */ MCD_OPC_CheckPredicate, + 0, + 42, + 2, + 0, // Skip to: 637 + /* 83 */ MCD_OPC_Decode, + 181, + 6, + 90, // Opcode: LDC_OPTION + /* 87 */ MCD_OPC_FilterValue, + 2, + 25, + 0, + 0, // Skip to: 117 + /* 92 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 108 + /* 97 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 108 + /* 104 */ MCD_OPC_Decode, + 218, + 14, + 90, // Opcode: STC2_POST + /* 108 */ MCD_OPC_CheckPredicate, + 0, + 12, + 2, + 0, // Skip to: 637 + /* 113 */ MCD_OPC_Decode, + 226, + 14, + 90, // Opcode: STC_POST + /* 117 */ MCD_OPC_FilterValue, + 3, + 25, + 0, + 0, // Skip to: 147 + /* 122 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 138 + /* 127 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 138 + /* 134 */ MCD_OPC_Decode, + 174, + 6, + 90, // Opcode: LDC2_POST + /* 138 */ MCD_OPC_CheckPredicate, + 0, + 238, + 1, + 0, // Skip to: 637 + /* 143 */ MCD_OPC_Decode, + 182, + 6, + 90, // Opcode: LDC_POST + /* 147 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 185 + /* 152 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 155 */ MCD_OPC_FilterValue, + 1, + 221, + 1, + 0, // Skip to: 637 + /* 160 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 176 + /* 165 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 176 + /* 172 */ MCD_OPC_Decode, + 213, + 14, + 90, // Opcode: STC2L_OPTION + /* 176 */ MCD_OPC_CheckPredicate, + 0, + 200, + 1, + 0, // Skip to: 637 + /* 181 */ MCD_OPC_Decode, + 221, + 14, + 90, // Opcode: STCL_OPTION + /* 185 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 223 + /* 190 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 193 */ MCD_OPC_FilterValue, + 1, + 183, + 1, + 0, // Skip to: 637 + /* 198 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 214 + /* 203 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 214 + /* 210 */ MCD_OPC_Decode, + 169, + 6, + 90, // Opcode: LDC2L_OPTION + /* 214 */ MCD_OPC_CheckPredicate, + 0, + 162, + 1, + 0, // Skip to: 637 + /* 219 */ MCD_OPC_Decode, + 177, + 6, + 90, // Opcode: LDCL_OPTION + /* 223 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 253 + /* 228 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 244 + /* 233 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 244 + /* 240 */ MCD_OPC_Decode, + 214, + 14, + 90, // Opcode: STC2L_POST + /* 244 */ MCD_OPC_CheckPredicate, + 0, + 132, + 1, + 0, // Skip to: 637 + /* 249 */ MCD_OPC_Decode, + 222, + 14, + 90, // Opcode: STCL_POST + /* 253 */ MCD_OPC_FilterValue, + 7, + 123, + 1, + 0, // Skip to: 637 + /* 258 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 274 + /* 263 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 274 + /* 270 */ MCD_OPC_Decode, + 170, + 6, + 90, // Opcode: LDC2L_POST + /* 274 */ MCD_OPC_CheckPredicate, + 0, + 102, + 1, + 0, // Skip to: 637 + /* 279 */ MCD_OPC_Decode, + 178, + 6, + 90, // Opcode: LDCL_POST + /* 283 */ MCD_OPC_FilterValue, + 13, + 243, + 0, + 0, // Skip to: 531 + /* 288 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 291 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 321 + /* 296 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 312 + /* 301 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 312 + /* 308 */ MCD_OPC_Decode, + 216, + 14, + 90, // Opcode: STC2_OFFSET + /* 312 */ MCD_OPC_CheckPredicate, + 0, + 64, + 1, + 0, // Skip to: 637 + /* 317 */ MCD_OPC_Decode, + 224, + 14, + 90, // Opcode: STC_OFFSET + /* 321 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 351 + /* 326 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 342 + /* 331 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 342 + /* 338 */ MCD_OPC_Decode, + 172, + 6, + 90, // Opcode: LDC2_OFFSET + /* 342 */ MCD_OPC_CheckPredicate, + 0, + 34, + 1, + 0, // Skip to: 637 + /* 347 */ MCD_OPC_Decode, + 180, + 6, + 90, // Opcode: LDC_OFFSET + /* 351 */ MCD_OPC_FilterValue, + 2, + 25, + 0, + 0, // Skip to: 381 + /* 356 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 372 + /* 361 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 372 + /* 368 */ MCD_OPC_Decode, + 219, + 14, + 90, // Opcode: STC2_PRE + /* 372 */ MCD_OPC_CheckPredicate, + 0, + 4, + 1, + 0, // Skip to: 637 + /* 377 */ MCD_OPC_Decode, + 227, + 14, + 90, // Opcode: STC_PRE + /* 381 */ MCD_OPC_FilterValue, + 3, + 25, + 0, + 0, // Skip to: 411 + /* 386 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 402 + /* 391 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 402 + /* 398 */ MCD_OPC_Decode, + 175, + 6, + 90, // Opcode: LDC2_PRE + /* 402 */ MCD_OPC_CheckPredicate, + 0, + 230, + 0, + 0, // Skip to: 637 + /* 407 */ MCD_OPC_Decode, + 183, + 6, + 90, // Opcode: LDC_PRE + /* 411 */ MCD_OPC_FilterValue, + 4, + 25, + 0, + 0, // Skip to: 441 + /* 416 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 432 + /* 421 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 432 + /* 428 */ MCD_OPC_Decode, + 212, + 14, + 90, // Opcode: STC2L_OFFSET + /* 432 */ MCD_OPC_CheckPredicate, + 0, + 200, + 0, + 0, // Skip to: 637 + /* 437 */ MCD_OPC_Decode, + 220, + 14, + 90, // Opcode: STCL_OFFSET + /* 441 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 471 + /* 446 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 462 + /* 451 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 462 + /* 458 */ MCD_OPC_Decode, + 168, + 6, + 90, // Opcode: LDC2L_OFFSET + /* 462 */ MCD_OPC_CheckPredicate, + 0, + 170, + 0, + 0, // Skip to: 637 + /* 467 */ MCD_OPC_Decode, + 176, + 6, + 90, // Opcode: LDCL_OFFSET + /* 471 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 501 + /* 476 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 492 + /* 481 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 492 + /* 488 */ MCD_OPC_Decode, + 215, + 14, + 90, // Opcode: STC2L_PRE + /* 492 */ MCD_OPC_CheckPredicate, + 0, + 140, + 0, + 0, // Skip to: 637 + /* 497 */ MCD_OPC_Decode, + 223, + 14, + 90, // Opcode: STCL_PRE + /* 501 */ MCD_OPC_FilterValue, + 7, + 131, + 0, + 0, // Skip to: 637 + /* 506 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 522 + /* 511 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 522 + /* 518 */ MCD_OPC_Decode, + 171, + 6, + 90, // Opcode: LDC2L_PRE + /* 522 */ MCD_OPC_CheckPredicate, + 0, + 110, + 0, + 0, // Skip to: 637 + /* 527 */ MCD_OPC_Decode, + 179, + 6, + 90, // Opcode: LDCL_PRE + /* 531 */ MCD_OPC_FilterValue, + 14, + 101, + 0, + 0, // Skip to: 637 + /* 536 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 539 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 569 + /* 544 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 560 + /* 549 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 560 + /* 556 */ MCD_OPC_Decode, + 247, + 5, + 91, // Opcode: CDP2 + /* 560 */ MCD_OPC_CheckPredicate, + 4, + 72, + 0, + 0, // Skip to: 637 + /* 565 */ MCD_OPC_Decode, + 246, + 5, + 92, // Opcode: CDP + /* 569 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 637 + /* 574 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 577 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 607 + /* 582 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 598 + /* 587 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 598 + /* 594 */ MCD_OPC_Decode, + 232, + 6, + 93, // Opcode: MCR2 + /* 598 */ MCD_OPC_CheckPredicate, + 0, + 34, + 0, + 0, // Skip to: 637 + /* 603 */ MCD_OPC_Decode, + 231, + 6, + 94, // Opcode: MCR + /* 607 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 637 + /* 612 */ MCD_OPC_CheckPredicate, + 4, + 11, + 0, + 0, // Skip to: 628 + /* 617 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 4, + 0, + 0, // Skip to: 628 + /* 624 */ MCD_OPC_Decode, + 246, + 6, + 95, // Opcode: MRC2 + /* 628 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 637 + /* 633 */ MCD_OPC_Decode, + 245, + 6, + 96, // Opcode: MRC + /* 637 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMVE32[] = { + /* 0 */ MCD_OPC_ExtractField, + 25, + 3, // Inst{27-25} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 131, + 0, + 0, // Skip to: 139 + /* 8 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 43 + /* 16 */ MCD_OPC_CheckPredicate, + 22, + 67, + 99, + 0, // Skip to: 25432 + /* 21 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 60, + 99, + 0, // Skip to: 25432 + /* 28 */ MCD_OPC_CheckField, + 11, + 5, + 29, + 53, + 99, + 0, // Skip to: 25432 + /* 35 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 1, + /* 39 */ MCD_OPC_Decode, + 245, + 7, + 97, // Opcode: MVE_VCTP8 + /* 43 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 75 + /* 48 */ MCD_OPC_CheckPredicate, + 22, + 35, + 99, + 0, // Skip to: 25432 + /* 53 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 28, + 99, + 0, // Skip to: 25432 + /* 60 */ MCD_OPC_CheckField, + 11, + 5, + 29, + 21, + 99, + 0, // Skip to: 25432 + /* 67 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 1, + /* 71 */ MCD_OPC_Decode, + 242, + 7, + 97, // Opcode: MVE_VCTP16 + /* 75 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 107 + /* 80 */ MCD_OPC_CheckPredicate, + 22, + 3, + 99, + 0, // Skip to: 25432 + /* 85 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 252, + 98, + 0, // Skip to: 25432 + /* 92 */ MCD_OPC_CheckField, + 11, + 5, + 29, + 245, + 98, + 0, // Skip to: 25432 + /* 99 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 1, + /* 103 */ MCD_OPC_Decode, + 243, + 7, + 97, // Opcode: MVE_VCTP32 + /* 107 */ MCD_OPC_FilterValue, + 3, + 232, + 98, + 0, // Skip to: 25432 + /* 112 */ MCD_OPC_CheckPredicate, + 22, + 227, + 98, + 0, // Skip to: 25432 + /* 117 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 220, + 98, + 0, // Skip to: 25432 + /* 124 */ MCD_OPC_CheckField, + 11, + 5, + 29, + 213, + 98, + 0, // Skip to: 25432 + /* 131 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 1, + /* 135 */ MCD_OPC_Decode, + 244, + 7, + 97, // Opcode: MVE_VCTP64 + /* 139 */ MCD_OPC_FilterValue, + 5, + 238, + 1, + 0, // Skip to: 638 + /* 144 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 147 */ MCD_OPC_FilterValue, + 13, + 89, + 0, + 0, // Skip to: 241 + /* 152 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 155 */ MCD_OPC_FilterValue, + 5, + 184, + 98, + 0, // Skip to: 25432 + /* 160 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 163 */ MCD_OPC_FilterValue, + 14, + 176, + 98, + 0, // Skip to: 25432 + /* 168 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 171 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 192 + /* 176 */ MCD_OPC_CheckPredicate, + 23, + 39, + 0, + 0, // Skip to: 220 + /* 181 */ MCD_OPC_CheckField, + 6, + 3, + 4, + 32, + 0, + 0, // Skip to: 220 + /* 188 */ MCD_OPC_Decode, + 137, + 7, + 98, // Opcode: MVE_LSLLr + /* 192 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 220 + /* 197 */ MCD_OPC_CheckPredicate, + 23, + 18, + 0, + 0, // Skip to: 220 + /* 202 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 11, + 0, + 0, // Skip to: 220 + /* 209 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 4, + 0, + 0, // Skip to: 220 + /* 216 */ MCD_OPC_Decode, + 146, + 7, + 98, // Opcode: MVE_UQRSHLL + /* 220 */ MCD_OPC_CheckPredicate, + 23, + 119, + 98, + 0, // Skip to: 25432 + /* 225 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 112, + 98, + 0, // Skip to: 25432 + /* 232 */ MCD_OPC_SoftFail, + 192, + 1 /* 0xc0 */, + 128, + 2 /* 0x100 */, + /* 237 */ MCD_OPC_Decode, + 145, + 7, + 99, // Opcode: MVE_UQRSHL + /* 241 */ MCD_OPC_FilterValue, + 15, + 73, + 0, + 0, // Skip to: 319 + /* 246 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 249 */ MCD_OPC_FilterValue, + 1, + 90, + 98, + 0, // Skip to: 25432 + /* 254 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 257 */ MCD_OPC_FilterValue, + 0, + 82, + 98, + 0, // Skip to: 25432 + /* 262 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 265 */ MCD_OPC_FilterValue, + 5, + 74, + 98, + 0, // Skip to: 25432 + /* 270 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 273 */ MCD_OPC_FilterValue, + 14, + 66, + 98, + 0, // Skip to: 25432 + /* 278 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 294 + /* 283 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 4, + 0, + 0, // Skip to: 294 + /* 290 */ MCD_OPC_Decode, + 147, + 7, + 100, // Opcode: MVE_UQSHL + /* 294 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 310 + /* 299 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 4, + 0, + 0, // Skip to: 310 + /* 306 */ MCD_OPC_Decode, + 148, + 7, + 101, // Opcode: MVE_UQSHLL + /* 310 */ MCD_OPC_CheckPredicate, + 23, + 29, + 98, + 0, // Skip to: 25432 + /* 315 */ MCD_OPC_Decode, + 136, + 7, + 101, // Opcode: MVE_LSLLi + /* 319 */ MCD_OPC_FilterValue, + 31, + 73, + 0, + 0, // Skip to: 397 + /* 324 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 327 */ MCD_OPC_FilterValue, + 1, + 12, + 98, + 0, // Skip to: 25432 + /* 332 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 335 */ MCD_OPC_FilterValue, + 0, + 4, + 98, + 0, // Skip to: 25432 + /* 340 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 343 */ MCD_OPC_FilterValue, + 5, + 252, + 97, + 0, // Skip to: 25432 + /* 348 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 351 */ MCD_OPC_FilterValue, + 14, + 244, + 97, + 0, // Skip to: 25432 + /* 356 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 372 + /* 361 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 4, + 0, + 0, // Skip to: 372 + /* 368 */ MCD_OPC_Decode, + 149, + 7, + 100, // Opcode: MVE_URSHR + /* 372 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 388 + /* 377 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 4, + 0, + 0, // Skip to: 388 + /* 384 */ MCD_OPC_Decode, + 150, + 7, + 101, // Opcode: MVE_URSHRL + /* 388 */ MCD_OPC_CheckPredicate, + 23, + 207, + 97, + 0, // Skip to: 25432 + /* 393 */ MCD_OPC_Decode, + 138, + 7, + 101, // Opcode: MVE_LSRL + /* 397 */ MCD_OPC_FilterValue, + 45, + 89, + 0, + 0, // Skip to: 491 + /* 402 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 405 */ MCD_OPC_FilterValue, + 5, + 190, + 97, + 0, // Skip to: 25432 + /* 410 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 413 */ MCD_OPC_FilterValue, + 14, + 182, + 97, + 0, // Skip to: 25432 + /* 418 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 421 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 442 + /* 426 */ MCD_OPC_CheckPredicate, + 23, + 39, + 0, + 0, // Skip to: 470 + /* 431 */ MCD_OPC_CheckField, + 6, + 3, + 4, + 32, + 0, + 0, // Skip to: 470 + /* 438 */ MCD_OPC_Decode, + 129, + 7, + 98, // Opcode: MVE_ASRLr + /* 442 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 470 + /* 447 */ MCD_OPC_CheckPredicate, + 23, + 18, + 0, + 0, // Skip to: 470 + /* 452 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 11, + 0, + 0, // Skip to: 470 + /* 459 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 4, + 0, + 0, // Skip to: 470 + /* 466 */ MCD_OPC_Decode, + 140, + 7, + 98, // Opcode: MVE_SQRSHRL + /* 470 */ MCD_OPC_CheckPredicate, + 23, + 125, + 97, + 0, // Skip to: 25432 + /* 475 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 118, + 97, + 0, // Skip to: 25432 + /* 482 */ MCD_OPC_SoftFail, + 192, + 1 /* 0xc0 */, + 128, + 2 /* 0x100 */, + /* 487 */ MCD_OPC_Decode, + 139, + 7, + 99, // Opcode: MVE_SQRSHR + /* 491 */ MCD_OPC_FilterValue, + 47, + 73, + 0, + 0, // Skip to: 569 + /* 496 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 499 */ MCD_OPC_FilterValue, + 1, + 96, + 97, + 0, // Skip to: 25432 + /* 504 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 507 */ MCD_OPC_FilterValue, + 0, + 88, + 97, + 0, // Skip to: 25432 + /* 512 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 515 */ MCD_OPC_FilterValue, + 5, + 80, + 97, + 0, // Skip to: 25432 + /* 520 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 523 */ MCD_OPC_FilterValue, + 14, + 72, + 97, + 0, // Skip to: 25432 + /* 528 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 544 + /* 533 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 4, + 0, + 0, // Skip to: 544 + /* 540 */ MCD_OPC_Decode, + 143, + 7, + 100, // Opcode: MVE_SRSHR + /* 544 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 560 + /* 549 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 4, + 0, + 0, // Skip to: 560 + /* 556 */ MCD_OPC_Decode, + 144, + 7, + 101, // Opcode: MVE_SRSHRL + /* 560 */ MCD_OPC_CheckPredicate, + 23, + 35, + 97, + 0, // Skip to: 25432 + /* 565 */ MCD_OPC_Decode, + 128, + 7, + 101, // Opcode: MVE_ASRLi + /* 569 */ MCD_OPC_FilterValue, + 63, + 26, + 97, + 0, // Skip to: 25432 + /* 574 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 577 */ MCD_OPC_FilterValue, + 1, + 18, + 97, + 0, // Skip to: 25432 + /* 582 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 585 */ MCD_OPC_FilterValue, + 0, + 10, + 97, + 0, // Skip to: 25432 + /* 590 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 593 */ MCD_OPC_FilterValue, + 5, + 2, + 97, + 0, // Skip to: 25432 + /* 598 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 601 */ MCD_OPC_FilterValue, + 14, + 250, + 96, + 0, // Skip to: 25432 + /* 606 */ MCD_OPC_CheckPredicate, + 23, + 11, + 0, + 0, // Skip to: 622 + /* 611 */ MCD_OPC_CheckField, + 9, + 3, + 7, + 4, + 0, + 0, // Skip to: 622 + /* 618 */ MCD_OPC_Decode, + 141, + 7, + 100, // Opcode: MVE_SQSHL + /* 622 */ MCD_OPC_CheckPredicate, + 23, + 229, + 96, + 0, // Skip to: 25432 + /* 627 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 222, + 96, + 0, // Skip to: 25432 + /* 634 */ MCD_OPC_Decode, + 142, + 7, + 101, // Opcode: MVE_SQSHLL + /* 638 */ MCD_OPC_FilterValue, + 6, + 250, + 18, + 0, // Skip to: 5501 + /* 643 */ MCD_OPC_ExtractField, + 8, + 5, // Inst{12-8} ... + /* 646 */ MCD_OPC_FilterValue, + 8, + 213, + 0, + 0, // Skip to: 864 + /* 651 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 654 */ MCD_OPC_FilterValue, + 0, + 51, + 0, + 0, // Skip to: 710 + /* 659 */ MCD_OPC_CheckPredicate, + 24, + 192, + 96, + 0, // Skip to: 25432 + /* 664 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 185, + 96, + 0, // Skip to: 25432 + /* 671 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 178, + 96, + 0, // Skip to: 25432 + /* 678 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 171, + 96, + 0, // Skip to: 25432 + /* 685 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 164, + 96, + 0, // Skip to: 25432 + /* 692 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 96, + 0, // Skip to: 25432 + /* 699 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 150, + 96, + 0, // Skip to: 25432 + /* 706 */ MCD_OPC_Decode, + 205, + 7, + 102, // Opcode: MVE_VCADDf16 + /* 710 */ MCD_OPC_FilterValue, + 1, + 51, + 0, + 0, // Skip to: 766 + /* 715 */ MCD_OPC_CheckPredicate, + 24, + 136, + 96, + 0, // Skip to: 25432 + /* 720 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 129, + 96, + 0, // Skip to: 25432 + /* 727 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 122, + 96, + 0, // Skip to: 25432 + /* 734 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 115, + 96, + 0, // Skip to: 25432 + /* 741 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 108, + 96, + 0, // Skip to: 25432 + /* 748 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 101, + 96, + 0, // Skip to: 25432 + /* 755 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 94, + 96, + 0, // Skip to: 25432 + /* 762 */ MCD_OPC_Decode, + 206, + 7, + 102, // Opcode: MVE_VCADDf32 + /* 766 */ MCD_OPC_FilterValue, + 2, + 44, + 0, + 0, // Skip to: 815 + /* 771 */ MCD_OPC_CheckPredicate, + 24, + 80, + 96, + 0, // Skip to: 25432 + /* 776 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 73, + 96, + 0, // Skip to: 25432 + /* 783 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 66, + 96, + 0, // Skip to: 25432 + /* 790 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 59, + 96, + 0, // Skip to: 25432 + /* 797 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 52, + 96, + 0, // Skip to: 25432 + /* 804 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 45, + 96, + 0, // Skip to: 25432 + /* 811 */ MCD_OPC_Decode, + 216, + 7, + 103, // Opcode: MVE_VCMLAf16 + /* 815 */ MCD_OPC_FilterValue, + 3, + 36, + 96, + 0, // Skip to: 25432 + /* 820 */ MCD_OPC_CheckPredicate, + 24, + 31, + 96, + 0, // Skip to: 25432 + /* 825 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 24, + 96, + 0, // Skip to: 25432 + /* 832 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 17, + 96, + 0, // Skip to: 25432 + /* 839 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 10, + 96, + 0, // Skip to: 25432 + /* 846 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 3, + 96, + 0, // Skip to: 25432 + /* 853 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 252, + 95, + 0, // Skip to: 25432 + /* 860 */ MCD_OPC_Decode, + 217, + 7, + 103, // Opcode: MVE_VCMLAf32 + /* 864 */ MCD_OPC_FilterValue, + 14, + 135, + 2, + 0, // Skip to: 1516 + /* 869 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 872 */ MCD_OPC_FilterValue, + 0, + 188, + 0, + 0, // Skip to: 1065 + /* 877 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 880 */ MCD_OPC_FilterValue, + 0, + 37, + 0, + 0, // Skip to: 922 + /* 885 */ MCD_OPC_CheckPredicate, + 22, + 222, + 95, + 0, // Skip to: 25432 + /* 890 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 215, + 95, + 0, // Skip to: 25432 + /* 897 */ MCD_OPC_CheckField, + 23, + 2, + 1, + 208, + 95, + 0, // Skip to: 25432 + /* 904 */ MCD_OPC_CheckField, + 4, + 3, + 0, + 201, + 95, + 0, // Skip to: 25432 + /* 911 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 194, + 95, + 0, // Skip to: 25432 + /* 918 */ MCD_OPC_Decode, + 168, + 13, + 104, // Opcode: MVE_VSTRB8_rq + /* 922 */ MCD_OPC_FilterValue, + 1, + 185, + 95, + 0, // Skip to: 25432 + /* 927 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 930 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 1037 + /* 935 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 938 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 1002 + /* 943 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 946 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 974 + /* 951 */ MCD_OPC_CheckPredicate, + 22, + 156, + 95, + 0, // Skip to: 25432 + /* 956 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 149, + 95, + 0, // Skip to: 25432 + /* 963 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 142, + 95, + 0, // Skip to: 25432 + /* 970 */ MCD_OPC_Decode, + 163, + 13, + 104, // Opcode: MVE_VSTRB16_rq + /* 974 */ MCD_OPC_FilterValue, + 1, + 133, + 95, + 0, // Skip to: 25432 + /* 979 */ MCD_OPC_CheckPredicate, + 22, + 128, + 95, + 0, // Skip to: 25432 + /* 984 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 121, + 95, + 0, // Skip to: 25432 + /* 991 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 114, + 95, + 0, // Skip to: 25432 + /* 998 */ MCD_OPC_Decode, + 177, + 13, + 104, // Opcode: MVE_VSTRH16_rq_u + /* 1002 */ MCD_OPC_FilterValue, + 1, + 105, + 95, + 0, // Skip to: 25432 + /* 1007 */ MCD_OPC_CheckPredicate, + 22, + 100, + 95, + 0, // Skip to: 25432 + /* 1012 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 93, + 95, + 0, // Skip to: 25432 + /* 1019 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 86, + 95, + 0, // Skip to: 25432 + /* 1026 */ MCD_OPC_CheckField, + 4, + 3, + 1, + 79, + 95, + 0, // Skip to: 25432 + /* 1033 */ MCD_OPC_Decode, + 176, + 13, + 104, // Opcode: MVE_VSTRH16_rq + /* 1037 */ MCD_OPC_FilterValue, + 1, + 70, + 95, + 0, // Skip to: 25432 + /* 1042 */ MCD_OPC_CheckPredicate, + 22, + 65, + 95, + 0, // Skip to: 25432 + /* 1047 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 58, + 95, + 0, // Skip to: 25432 + /* 1054 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 51, + 95, + 0, // Skip to: 25432 + /* 1061 */ MCD_OPC_Decode, + 160, + 13, + 105, // Opcode: MVE_VSTRB16 + /* 1065 */ MCD_OPC_FilterValue, + 1, + 232, + 0, + 0, // Skip to: 1302 + /* 1070 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1073 */ MCD_OPC_FilterValue, + 0, + 37, + 0, + 0, // Skip to: 1115 + /* 1078 */ MCD_OPC_CheckPredicate, + 22, + 29, + 95, + 0, // Skip to: 25432 + /* 1083 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 22, + 95, + 0, // Skip to: 25432 + /* 1090 */ MCD_OPC_CheckField, + 23, + 2, + 1, + 15, + 95, + 0, // Skip to: 25432 + /* 1097 */ MCD_OPC_CheckField, + 4, + 3, + 0, + 8, + 95, + 0, // Skip to: 25432 + /* 1104 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 1, + 95, + 0, // Skip to: 25432 + /* 1111 */ MCD_OPC_Decode, + 132, + 9, + 104, // Opcode: MVE_VLDRBU8_rq + /* 1115 */ MCD_OPC_FilterValue, + 1, + 248, + 94, + 0, // Skip to: 25432 + /* 1120 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1123 */ MCD_OPC_FilterValue, + 0, + 124, + 0, + 0, // Skip to: 1252 + /* 1128 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1131 */ MCD_OPC_FilterValue, + 0, + 81, + 0, + 0, // Skip to: 1217 + /* 1136 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 1139 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 1189 + /* 1144 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1147 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 1168 + /* 1152 */ MCD_OPC_CheckPredicate, + 22, + 211, + 94, + 0, // Skip to: 25432 + /* 1157 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 204, + 94, + 0, // Skip to: 25432 + /* 1164 */ MCD_OPC_Decode, + 244, + 8, + 104, // Opcode: MVE_VLDRBS16_rq + /* 1168 */ MCD_OPC_FilterValue, + 15, + 195, + 94, + 0, // Skip to: 25432 + /* 1173 */ MCD_OPC_CheckPredicate, + 22, + 190, + 94, + 0, // Skip to: 25432 + /* 1178 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 183, + 94, + 0, // Skip to: 25432 + /* 1185 */ MCD_OPC_Decode, + 252, + 8, + 104, // Opcode: MVE_VLDRBU16_rq + /* 1189 */ MCD_OPC_FilterValue, + 1, + 174, + 94, + 0, // Skip to: 25432 + /* 1194 */ MCD_OPC_CheckPredicate, + 22, + 169, + 94, + 0, // Skip to: 25432 + /* 1199 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 162, + 94, + 0, // Skip to: 25432 + /* 1206 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 155, + 94, + 0, // Skip to: 25432 + /* 1213 */ MCD_OPC_Decode, + 146, + 9, + 104, // Opcode: MVE_VLDRHU16_rq_u + /* 1217 */ MCD_OPC_FilterValue, + 1, + 146, + 94, + 0, // Skip to: 25432 + /* 1222 */ MCD_OPC_CheckPredicate, + 22, + 141, + 94, + 0, // Skip to: 25432 + /* 1227 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 134, + 94, + 0, // Skip to: 25432 + /* 1234 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 127, + 94, + 0, // Skip to: 25432 + /* 1241 */ MCD_OPC_CheckField, + 4, + 3, + 1, + 120, + 94, + 0, // Skip to: 25432 + /* 1248 */ MCD_OPC_Decode, + 145, + 9, + 104, // Opcode: MVE_VLDRHU16_rq + /* 1252 */ MCD_OPC_FilterValue, + 1, + 111, + 94, + 0, // Skip to: 25432 + /* 1257 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1260 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 1281 + /* 1265 */ MCD_OPC_CheckPredicate, + 22, + 98, + 94, + 0, // Skip to: 25432 + /* 1270 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 91, + 94, + 0, // Skip to: 25432 + /* 1277 */ MCD_OPC_Decode, + 241, + 8, + 105, // Opcode: MVE_VLDRBS16 + /* 1281 */ MCD_OPC_FilterValue, + 15, + 82, + 94, + 0, // Skip to: 25432 + /* 1286 */ MCD_OPC_CheckPredicate, + 22, + 77, + 94, + 0, // Skip to: 25432 + /* 1291 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 70, + 94, + 0, // Skip to: 25432 + /* 1298 */ MCD_OPC_Decode, + 249, + 8, + 105, // Opcode: MVE_VLDRBU16 + /* 1302 */ MCD_OPC_FilterValue, + 2, + 73, + 0, + 0, // Skip to: 1380 + /* 1307 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1310 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 1345 + /* 1315 */ MCD_OPC_CheckPredicate, + 22, + 48, + 94, + 0, // Skip to: 25432 + /* 1320 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 41, + 94, + 0, // Skip to: 25432 + /* 1327 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 34, + 94, + 0, // Skip to: 25432 + /* 1334 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 27, + 94, + 0, // Skip to: 25432 + /* 1341 */ MCD_OPC_Decode, + 161, + 13, + 106, // Opcode: MVE_VSTRB16_post + /* 1345 */ MCD_OPC_FilterValue, + 1, + 18, + 94, + 0, // Skip to: 25432 + /* 1350 */ MCD_OPC_CheckPredicate, + 22, + 13, + 94, + 0, // Skip to: 25432 + /* 1355 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 6, + 94, + 0, // Skip to: 25432 + /* 1362 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 255, + 93, + 0, // Skip to: 25432 + /* 1369 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 248, + 93, + 0, // Skip to: 25432 + /* 1376 */ MCD_OPC_Decode, + 162, + 13, + 107, // Opcode: MVE_VSTRB16_pre + /* 1380 */ MCD_OPC_FilterValue, + 3, + 239, + 93, + 0, // Skip to: 25432 + /* 1385 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1388 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 1452 + /* 1393 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1396 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 1424 + /* 1401 */ MCD_OPC_CheckPredicate, + 22, + 218, + 93, + 0, // Skip to: 25432 + /* 1406 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 211, + 93, + 0, // Skip to: 25432 + /* 1413 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 204, + 93, + 0, // Skip to: 25432 + /* 1420 */ MCD_OPC_Decode, + 242, + 8, + 106, // Opcode: MVE_VLDRBS16_post + /* 1424 */ MCD_OPC_FilterValue, + 15, + 195, + 93, + 0, // Skip to: 25432 + /* 1429 */ MCD_OPC_CheckPredicate, + 22, + 190, + 93, + 0, // Skip to: 25432 + /* 1434 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 183, + 93, + 0, // Skip to: 25432 + /* 1441 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 176, + 93, + 0, // Skip to: 25432 + /* 1448 */ MCD_OPC_Decode, + 250, + 8, + 106, // Opcode: MVE_VLDRBU16_post + /* 1452 */ MCD_OPC_FilterValue, + 1, + 167, + 93, + 0, // Skip to: 25432 + /* 1457 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1460 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 1488 + /* 1465 */ MCD_OPC_CheckPredicate, + 22, + 154, + 93, + 0, // Skip to: 25432 + /* 1470 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 147, + 93, + 0, // Skip to: 25432 + /* 1477 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 140, + 93, + 0, // Skip to: 25432 + /* 1484 */ MCD_OPC_Decode, + 243, + 8, + 107, // Opcode: MVE_VLDRBS16_pre + /* 1488 */ MCD_OPC_FilterValue, + 15, + 131, + 93, + 0, // Skip to: 25432 + /* 1493 */ MCD_OPC_CheckPredicate, + 22, + 126, + 93, + 0, // Skip to: 25432 + /* 1498 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 119, + 93, + 0, // Skip to: 25432 + /* 1505 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 112, + 93, + 0, // Skip to: 25432 + /* 1512 */ MCD_OPC_Decode, + 251, + 8, + 107, // Opcode: MVE_VLDRBU16_pre + /* 1516 */ MCD_OPC_FilterValue, + 15, + 44, + 5, + 0, // Skip to: 2845 + /* 1521 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1524 */ MCD_OPC_FilterValue, + 0, + 119, + 1, + 0, // Skip to: 1904 + /* 1529 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1532 */ MCD_OPC_FilterValue, + 0, + 33, + 1, + 0, // Skip to: 1826 + /* 1537 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1540 */ MCD_OPC_FilterValue, + 0, + 217, + 0, + 0, // Skip to: 1762 + /* 1545 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 1548 */ MCD_OPC_FilterValue, + 0, + 131, + 0, + 0, // Skip to: 1684 + /* 1553 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1556 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1577 + /* 1561 */ MCD_OPC_CheckPredicate, + 23, + 58, + 93, + 0, // Skip to: 25432 + /* 1566 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 51, + 93, + 0, // Skip to: 25432 + /* 1573 */ MCD_OPC_Decode, + 163, + 10, + 108, // Opcode: MVE_VMOV_rr_q + /* 1577 */ MCD_OPC_FilterValue, + 1, + 42, + 93, + 0, // Skip to: 25432 + /* 1582 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1585 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 1649 + /* 1590 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1593 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 1621 + /* 1598 */ MCD_OPC_CheckPredicate, + 22, + 21, + 93, + 0, // Skip to: 25432 + /* 1603 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 14, + 93, + 0, // Skip to: 25432 + /* 1610 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 7, + 93, + 0, // Skip to: 25432 + /* 1617 */ MCD_OPC_Decode, + 167, + 13, + 104, // Opcode: MVE_VSTRB32_rq + /* 1621 */ MCD_OPC_FilterValue, + 1, + 254, + 92, + 0, // Skip to: 25432 + /* 1626 */ MCD_OPC_CheckPredicate, + 22, + 249, + 92, + 0, // Skip to: 25432 + /* 1631 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 242, + 92, + 0, // Skip to: 25432 + /* 1638 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 235, + 92, + 0, // Skip to: 25432 + /* 1645 */ MCD_OPC_Decode, + 182, + 13, + 104, // Opcode: MVE_VSTRH32_rq_u + /* 1649 */ MCD_OPC_FilterValue, + 1, + 226, + 92, + 0, // Skip to: 25432 + /* 1654 */ MCD_OPC_CheckPredicate, + 22, + 221, + 92, + 0, // Skip to: 25432 + /* 1659 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 214, + 92, + 0, // Skip to: 25432 + /* 1666 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 207, + 92, + 0, // Skip to: 25432 + /* 1673 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 200, + 92, + 0, // Skip to: 25432 + /* 1680 */ MCD_OPC_Decode, + 181, + 13, + 104, // Opcode: MVE_VSTRH32_rq + /* 1684 */ MCD_OPC_FilterValue, + 2, + 191, + 92, + 0, // Skip to: 25432 + /* 1689 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1692 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 1727 + /* 1697 */ MCD_OPC_CheckPredicate, + 22, + 178, + 92, + 0, // Skip to: 25432 + /* 1702 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 171, + 92, + 0, // Skip to: 25432 + /* 1709 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 164, + 92, + 0, // Skip to: 25432 + /* 1716 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 92, + 0, // Skip to: 25432 + /* 1723 */ MCD_OPC_Decode, + 189, + 13, + 104, // Opcode: MVE_VSTRW32_rq_u + /* 1727 */ MCD_OPC_FilterValue, + 1, + 148, + 92, + 0, // Skip to: 25432 + /* 1732 */ MCD_OPC_CheckPredicate, + 22, + 143, + 92, + 0, // Skip to: 25432 + /* 1737 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 136, + 92, + 0, // Skip to: 25432 + /* 1744 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 129, + 92, + 0, // Skip to: 25432 + /* 1751 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 122, + 92, + 0, // Skip to: 25432 + /* 1758 */ MCD_OPC_Decode, + 188, + 13, + 104, // Opcode: MVE_VSTRW32_rq + /* 1762 */ MCD_OPC_FilterValue, + 1, + 113, + 92, + 0, // Skip to: 25432 + /* 1767 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 1770 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 1798 + /* 1775 */ MCD_OPC_CheckPredicate, + 22, + 100, + 92, + 0, // Skip to: 25432 + /* 1780 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 93, + 92, + 0, // Skip to: 25432 + /* 1787 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 86, + 92, + 0, // Skip to: 25432 + /* 1794 */ MCD_OPC_Decode, + 164, + 13, + 105, // Opcode: MVE_VSTRB32 + /* 1798 */ MCD_OPC_FilterValue, + 1, + 77, + 92, + 0, // Skip to: 25432 + /* 1803 */ MCD_OPC_CheckPredicate, + 22, + 72, + 92, + 0, // Skip to: 25432 + /* 1808 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 65, + 92, + 0, // Skip to: 25432 + /* 1815 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 58, + 92, + 0, // Skip to: 25432 + /* 1822 */ MCD_OPC_Decode, + 178, + 13, + 109, // Opcode: MVE_VSTRH32 + /* 1826 */ MCD_OPC_FilterValue, + 1, + 49, + 92, + 0, // Skip to: 25432 + /* 1831 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1834 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 1869 + /* 1839 */ MCD_OPC_CheckPredicate, + 22, + 36, + 92, + 0, // Skip to: 25432 + /* 1844 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 29, + 92, + 0, // Skip to: 25432 + /* 1851 */ MCD_OPC_CheckField, + 22, + 3, + 2, + 22, + 92, + 0, // Skip to: 25432 + /* 1858 */ MCD_OPC_CheckField, + 4, + 3, + 5, + 15, + 92, + 0, // Skip to: 25432 + /* 1865 */ MCD_OPC_Decode, + 175, + 13, + 104, // Opcode: MVE_VSTRD64_rq_u + /* 1869 */ MCD_OPC_FilterValue, + 1, + 6, + 92, + 0, // Skip to: 25432 + /* 1874 */ MCD_OPC_CheckPredicate, + 22, + 1, + 92, + 0, // Skip to: 25432 + /* 1879 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 250, + 91, + 0, // Skip to: 25432 + /* 1886 */ MCD_OPC_CheckField, + 22, + 3, + 2, + 243, + 91, + 0, // Skip to: 25432 + /* 1893 */ MCD_OPC_CheckField, + 4, + 3, + 5, + 236, + 91, + 0, // Skip to: 25432 + /* 1900 */ MCD_OPC_Decode, + 174, + 13, + 104, // Opcode: MVE_VSTRD64_rq + /* 1904 */ MCD_OPC_FilterValue, + 1, + 236, + 1, + 0, // Skip to: 2401 + /* 1909 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1912 */ MCD_OPC_FilterValue, + 0, + 150, + 1, + 0, // Skip to: 2323 + /* 1917 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 1920 */ MCD_OPC_FilterValue, + 0, + 34, + 1, + 0, // Skip to: 2215 + /* 1925 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 1928 */ MCD_OPC_FilterValue, + 0, + 204, + 0, + 0, // Skip to: 2137 + /* 1933 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1936 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1957 + /* 1941 */ MCD_OPC_CheckPredicate, + 23, + 190, + 91, + 0, // Skip to: 25432 + /* 1946 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 183, + 91, + 0, // Skip to: 25432 + /* 1953 */ MCD_OPC_Decode, + 162, + 10, + 110, // Opcode: MVE_VMOV_q_rr + /* 1957 */ MCD_OPC_FilterValue, + 1, + 174, + 91, + 0, // Skip to: 25432 + /* 1962 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 1965 */ MCD_OPC_FilterValue, + 0, + 103, + 0, + 0, // Skip to: 2073 + /* 1970 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1973 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 2023 + /* 1978 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 1981 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2002 + /* 1986 */ MCD_OPC_CheckPredicate, + 22, + 145, + 91, + 0, // Skip to: 25432 + /* 1991 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 138, + 91, + 0, // Skip to: 25432 + /* 1998 */ MCD_OPC_Decode, + 248, + 8, + 104, // Opcode: MVE_VLDRBS32_rq + /* 2002 */ MCD_OPC_FilterValue, + 15, + 129, + 91, + 0, // Skip to: 25432 + /* 2007 */ MCD_OPC_CheckPredicate, + 22, + 124, + 91, + 0, // Skip to: 25432 + /* 2012 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 117, + 91, + 0, // Skip to: 25432 + /* 2019 */ MCD_OPC_Decode, + 128, + 9, + 104, // Opcode: MVE_VLDRBU32_rq + /* 2023 */ MCD_OPC_FilterValue, + 1, + 108, + 91, + 0, // Skip to: 25432 + /* 2028 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2031 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2052 + /* 2036 */ MCD_OPC_CheckPredicate, + 22, + 95, + 91, + 0, // Skip to: 25432 + /* 2041 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 88, + 91, + 0, // Skip to: 25432 + /* 2048 */ MCD_OPC_Decode, + 141, + 9, + 104, // Opcode: MVE_VLDRHS32_rq_u + /* 2052 */ MCD_OPC_FilterValue, + 15, + 79, + 91, + 0, // Skip to: 25432 + /* 2057 */ MCD_OPC_CheckPredicate, + 22, + 74, + 91, + 0, // Skip to: 25432 + /* 2062 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 67, + 91, + 0, // Skip to: 25432 + /* 2069 */ MCD_OPC_Decode, + 151, + 9, + 104, // Opcode: MVE_VLDRHU32_rq_u + /* 2073 */ MCD_OPC_FilterValue, + 1, + 58, + 91, + 0, // Skip to: 25432 + /* 2078 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2081 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2109 + /* 2086 */ MCD_OPC_CheckPredicate, + 22, + 45, + 91, + 0, // Skip to: 25432 + /* 2091 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 38, + 91, + 0, // Skip to: 25432 + /* 2098 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 31, + 91, + 0, // Skip to: 25432 + /* 2105 */ MCD_OPC_Decode, + 140, + 9, + 104, // Opcode: MVE_VLDRHS32_rq + /* 2109 */ MCD_OPC_FilterValue, + 15, + 22, + 91, + 0, // Skip to: 25432 + /* 2114 */ MCD_OPC_CheckPredicate, + 22, + 17, + 91, + 0, // Skip to: 25432 + /* 2119 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 10, + 91, + 0, // Skip to: 25432 + /* 2126 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 3, + 91, + 0, // Skip to: 25432 + /* 2133 */ MCD_OPC_Decode, + 150, + 9, + 104, // Opcode: MVE_VLDRHU32_rq + /* 2137 */ MCD_OPC_FilterValue, + 2, + 250, + 90, + 0, // Skip to: 25432 + /* 2142 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 2145 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 2180 + /* 2150 */ MCD_OPC_CheckPredicate, + 22, + 237, + 90, + 0, // Skip to: 25432 + /* 2155 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 230, + 90, + 0, // Skip to: 25432 + /* 2162 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 223, + 90, + 0, // Skip to: 25432 + /* 2169 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 216, + 90, + 0, // Skip to: 25432 + /* 2176 */ MCD_OPC_Decode, + 158, + 9, + 104, // Opcode: MVE_VLDRWU32_rq_u + /* 2180 */ MCD_OPC_FilterValue, + 1, + 207, + 90, + 0, // Skip to: 25432 + /* 2185 */ MCD_OPC_CheckPredicate, + 22, + 202, + 90, + 0, // Skip to: 25432 + /* 2190 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 195, + 90, + 0, // Skip to: 25432 + /* 2197 */ MCD_OPC_CheckField, + 22, + 2, + 2, + 188, + 90, + 0, // Skip to: 25432 + /* 2204 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 90, + 0, // Skip to: 25432 + /* 2211 */ MCD_OPC_Decode, + 157, + 9, + 104, // Opcode: MVE_VLDRWU32_rq + /* 2215 */ MCD_OPC_FilterValue, + 1, + 172, + 90, + 0, // Skip to: 25432 + /* 2220 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 2223 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 2273 + /* 2228 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2231 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2252 + /* 2236 */ MCD_OPC_CheckPredicate, + 22, + 151, + 90, + 0, // Skip to: 25432 + /* 2241 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 144, + 90, + 0, // Skip to: 25432 + /* 2248 */ MCD_OPC_Decode, + 245, + 8, + 105, // Opcode: MVE_VLDRBS32 + /* 2252 */ MCD_OPC_FilterValue, + 15, + 135, + 90, + 0, // Skip to: 25432 + /* 2257 */ MCD_OPC_CheckPredicate, + 22, + 130, + 90, + 0, // Skip to: 25432 + /* 2262 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 123, + 90, + 0, // Skip to: 25432 + /* 2269 */ MCD_OPC_Decode, + 253, + 8, + 105, // Opcode: MVE_VLDRBU32 + /* 2273 */ MCD_OPC_FilterValue, + 1, + 114, + 90, + 0, // Skip to: 25432 + /* 2278 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2281 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2302 + /* 2286 */ MCD_OPC_CheckPredicate, + 22, + 101, + 90, + 0, // Skip to: 25432 + /* 2291 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 94, + 90, + 0, // Skip to: 25432 + /* 2298 */ MCD_OPC_Decode, + 137, + 9, + 109, // Opcode: MVE_VLDRHS32 + /* 2302 */ MCD_OPC_FilterValue, + 15, + 85, + 90, + 0, // Skip to: 25432 + /* 2307 */ MCD_OPC_CheckPredicate, + 22, + 80, + 90, + 0, // Skip to: 25432 + /* 2312 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 73, + 90, + 0, // Skip to: 25432 + /* 2319 */ MCD_OPC_Decode, + 147, + 9, + 109, // Opcode: MVE_VLDRHU32 + /* 2323 */ MCD_OPC_FilterValue, + 1, + 64, + 90, + 0, // Skip to: 25432 + /* 2328 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 2331 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 2366 + /* 2336 */ MCD_OPC_CheckPredicate, + 22, + 51, + 90, + 0, // Skip to: 25432 + /* 2341 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 44, + 90, + 0, // Skip to: 25432 + /* 2348 */ MCD_OPC_CheckField, + 22, + 3, + 2, + 37, + 90, + 0, // Skip to: 25432 + /* 2355 */ MCD_OPC_CheckField, + 4, + 3, + 5, + 30, + 90, + 0, // Skip to: 25432 + /* 2362 */ MCD_OPC_Decode, + 136, + 9, + 104, // Opcode: MVE_VLDRDU64_rq_u + /* 2366 */ MCD_OPC_FilterValue, + 1, + 21, + 90, + 0, // Skip to: 25432 + /* 2371 */ MCD_OPC_CheckPredicate, + 22, + 16, + 90, + 0, // Skip to: 25432 + /* 2376 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 9, + 90, + 0, // Skip to: 25432 + /* 2383 */ MCD_OPC_CheckField, + 22, + 3, + 2, + 2, + 90, + 0, // Skip to: 25432 + /* 2390 */ MCD_OPC_CheckField, + 4, + 3, + 5, + 251, + 89, + 0, // Skip to: 25432 + /* 2397 */ MCD_OPC_Decode, + 135, + 9, + 104, // Opcode: MVE_VLDRDU64_rq + /* 2401 */ MCD_OPC_FilterValue, + 2, + 159, + 0, + 0, // Skip to: 2565 + /* 2406 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 2409 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 2487 + /* 2414 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2417 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 2452 + /* 2422 */ MCD_OPC_CheckPredicate, + 22, + 221, + 89, + 0, // Skip to: 25432 + /* 2427 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 214, + 89, + 0, // Skip to: 25432 + /* 2434 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 207, + 89, + 0, // Skip to: 25432 + /* 2441 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 200, + 89, + 0, // Skip to: 25432 + /* 2448 */ MCD_OPC_Decode, + 165, + 13, + 106, // Opcode: MVE_VSTRB32_post + /* 2452 */ MCD_OPC_FilterValue, + 1, + 191, + 89, + 0, // Skip to: 25432 + /* 2457 */ MCD_OPC_CheckPredicate, + 22, + 186, + 89, + 0, // Skip to: 25432 + /* 2462 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 179, + 89, + 0, // Skip to: 25432 + /* 2469 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 172, + 89, + 0, // Skip to: 25432 + /* 2476 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 165, + 89, + 0, // Skip to: 25432 + /* 2483 */ MCD_OPC_Decode, + 166, + 13, + 107, // Opcode: MVE_VSTRB32_pre + /* 2487 */ MCD_OPC_FilterValue, + 1, + 156, + 89, + 0, // Skip to: 25432 + /* 2492 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2495 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 2530 + /* 2500 */ MCD_OPC_CheckPredicate, + 22, + 143, + 89, + 0, // Skip to: 25432 + /* 2505 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 136, + 89, + 0, // Skip to: 25432 + /* 2512 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 129, + 89, + 0, // Skip to: 25432 + /* 2519 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 122, + 89, + 0, // Skip to: 25432 + /* 2526 */ MCD_OPC_Decode, + 179, + 13, + 111, // Opcode: MVE_VSTRH32_post + /* 2530 */ MCD_OPC_FilterValue, + 1, + 113, + 89, + 0, // Skip to: 25432 + /* 2535 */ MCD_OPC_CheckPredicate, + 22, + 108, + 89, + 0, // Skip to: 25432 + /* 2540 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 101, + 89, + 0, // Skip to: 25432 + /* 2547 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 94, + 89, + 0, // Skip to: 25432 + /* 2554 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 87, + 89, + 0, // Skip to: 25432 + /* 2561 */ MCD_OPC_Decode, + 180, + 13, + 112, // Opcode: MVE_VSTRH32_pre + /* 2565 */ MCD_OPC_FilterValue, + 3, + 78, + 89, + 0, // Skip to: 25432 + /* 2570 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 2573 */ MCD_OPC_FilterValue, + 0, + 131, + 0, + 0, // Skip to: 2709 + /* 2578 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2581 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 2645 + /* 2586 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2589 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2617 + /* 2594 */ MCD_OPC_CheckPredicate, + 22, + 49, + 89, + 0, // Skip to: 25432 + /* 2599 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 42, + 89, + 0, // Skip to: 25432 + /* 2606 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 35, + 89, + 0, // Skip to: 25432 + /* 2613 */ MCD_OPC_Decode, + 246, + 8, + 106, // Opcode: MVE_VLDRBS32_post + /* 2617 */ MCD_OPC_FilterValue, + 15, + 26, + 89, + 0, // Skip to: 25432 + /* 2622 */ MCD_OPC_CheckPredicate, + 22, + 21, + 89, + 0, // Skip to: 25432 + /* 2627 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 14, + 89, + 0, // Skip to: 25432 + /* 2634 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 7, + 89, + 0, // Skip to: 25432 + /* 2641 */ MCD_OPC_Decode, + 254, + 8, + 106, // Opcode: MVE_VLDRBU32_post + /* 2645 */ MCD_OPC_FilterValue, + 1, + 254, + 88, + 0, // Skip to: 25432 + /* 2650 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2653 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2681 + /* 2658 */ MCD_OPC_CheckPredicate, + 22, + 241, + 88, + 0, // Skip to: 25432 + /* 2663 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 234, + 88, + 0, // Skip to: 25432 + /* 2670 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 227, + 88, + 0, // Skip to: 25432 + /* 2677 */ MCD_OPC_Decode, + 247, + 8, + 107, // Opcode: MVE_VLDRBS32_pre + /* 2681 */ MCD_OPC_FilterValue, + 15, + 218, + 88, + 0, // Skip to: 25432 + /* 2686 */ MCD_OPC_CheckPredicate, + 22, + 213, + 88, + 0, // Skip to: 25432 + /* 2691 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 206, + 88, + 0, // Skip to: 25432 + /* 2698 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 199, + 88, + 0, // Skip to: 25432 + /* 2705 */ MCD_OPC_Decode, + 255, + 8, + 107, // Opcode: MVE_VLDRBU32_pre + /* 2709 */ MCD_OPC_FilterValue, + 1, + 190, + 88, + 0, // Skip to: 25432 + /* 2714 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2717 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 2781 + /* 2722 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2725 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2753 + /* 2730 */ MCD_OPC_CheckPredicate, + 22, + 169, + 88, + 0, // Skip to: 25432 + /* 2735 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 162, + 88, + 0, // Skip to: 25432 + /* 2742 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 155, + 88, + 0, // Skip to: 25432 + /* 2749 */ MCD_OPC_Decode, + 138, + 9, + 111, // Opcode: MVE_VLDRHS32_post + /* 2753 */ MCD_OPC_FilterValue, + 15, + 146, + 88, + 0, // Skip to: 25432 + /* 2758 */ MCD_OPC_CheckPredicate, + 22, + 141, + 88, + 0, // Skip to: 25432 + /* 2763 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 134, + 88, + 0, // Skip to: 25432 + /* 2770 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 127, + 88, + 0, // Skip to: 25432 + /* 2777 */ MCD_OPC_Decode, + 148, + 9, + 111, // Opcode: MVE_VLDRHU32_post + /* 2781 */ MCD_OPC_FilterValue, + 1, + 118, + 88, + 0, // Skip to: 25432 + /* 2786 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 2789 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 2817 + /* 2794 */ MCD_OPC_CheckPredicate, + 22, + 105, + 88, + 0, // Skip to: 25432 + /* 2799 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 98, + 88, + 0, // Skip to: 25432 + /* 2806 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 91, + 88, + 0, // Skip to: 25432 + /* 2813 */ MCD_OPC_Decode, + 139, + 9, + 112, // Opcode: MVE_VLDRHS32_pre + /* 2817 */ MCD_OPC_FilterValue, + 15, + 82, + 88, + 0, // Skip to: 25432 + /* 2822 */ MCD_OPC_CheckPredicate, + 22, + 77, + 88, + 0, // Skip to: 25432 + /* 2827 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 70, + 88, + 0, // Skip to: 25432 + /* 2834 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 63, + 88, + 0, // Skip to: 25432 + /* 2841 */ MCD_OPC_Decode, + 149, + 9, + 112, // Opcode: MVE_VLDRHU32_pre + /* 2845 */ MCD_OPC_FilterValue, + 30, + 155, + 6, + 0, // Skip to: 4541 + /* 2850 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 2853 */ MCD_OPC_FilterValue, + 0, + 179, + 1, + 0, // Skip to: 3293 + /* 2858 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2861 */ MCD_OPC_FilterValue, + 0, + 222, + 0, + 0, // Skip to: 3088 + /* 2866 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 2869 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 3045 + /* 2874 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 2877 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 2905 + /* 2882 */ MCD_OPC_CheckPredicate, + 22, + 17, + 88, + 0, // Skip to: 25432 + /* 2887 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 10, + 88, + 0, // Skip to: 25432 + /* 2894 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 3, + 88, + 0, // Skip to: 25432 + /* 2901 */ MCD_OPC_Decode, + 128, + 13, + 113, // Opcode: MVE_VST20_8 + /* 2905 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 2933 + /* 2910 */ MCD_OPC_CheckPredicate, + 22, + 245, + 87, + 0, // Skip to: 25432 + /* 2915 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 238, + 87, + 0, // Skip to: 25432 + /* 2922 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 231, + 87, + 0, // Skip to: 25432 + /* 2929 */ MCD_OPC_Decode, + 140, + 13, + 114, // Opcode: MVE_VST40_8 + /* 2933 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 2961 + /* 2938 */ MCD_OPC_CheckPredicate, + 22, + 217, + 87, + 0, // Skip to: 25432 + /* 2943 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 210, + 87, + 0, // Skip to: 25432 + /* 2950 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 203, + 87, + 0, // Skip to: 25432 + /* 2957 */ MCD_OPC_Decode, + 134, + 13, + 113, // Opcode: MVE_VST21_8 + /* 2961 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 2989 + /* 2966 */ MCD_OPC_CheckPredicate, + 22, + 189, + 87, + 0, // Skip to: 25432 + /* 2971 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 182, + 87, + 0, // Skip to: 25432 + /* 2978 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 175, + 87, + 0, // Skip to: 25432 + /* 2985 */ MCD_OPC_Decode, + 146, + 13, + 114, // Opcode: MVE_VST41_8 + /* 2989 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 3017 + /* 2994 */ MCD_OPC_CheckPredicate, + 22, + 161, + 87, + 0, // Skip to: 25432 + /* 2999 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 154, + 87, + 0, // Skip to: 25432 + /* 3006 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 147, + 87, + 0, // Skip to: 25432 + /* 3013 */ MCD_OPC_Decode, + 152, + 13, + 114, // Opcode: MVE_VST42_8 + /* 3017 */ MCD_OPC_FilterValue, + 97, + 138, + 87, + 0, // Skip to: 25432 + /* 3022 */ MCD_OPC_CheckPredicate, + 22, + 133, + 87, + 0, // Skip to: 25432 + /* 3027 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 126, + 87, + 0, // Skip to: 25432 + /* 3034 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 119, + 87, + 0, // Skip to: 25432 + /* 3041 */ MCD_OPC_Decode, + 158, + 13, + 114, // Opcode: MVE_VST43_8 + /* 3045 */ MCD_OPC_FilterValue, + 1, + 110, + 87, + 0, // Skip to: 25432 + /* 3050 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3053 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3067 + /* 3058 */ MCD_OPC_CheckPredicate, + 22, + 97, + 87, + 0, // Skip to: 25432 + /* 3063 */ MCD_OPC_Decode, + 169, + 13, + 115, // Opcode: MVE_VSTRBU8 + /* 3067 */ MCD_OPC_FilterValue, + 15, + 88, + 87, + 0, // Skip to: 25432 + /* 3072 */ MCD_OPC_CheckPredicate, + 22, + 83, + 87, + 0, // Skip to: 25432 + /* 3077 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 76, + 87, + 0, // Skip to: 25432 + /* 3084 */ MCD_OPC_Decode, + 186, + 13, + 116, // Opcode: MVE_VSTRW32_qi + /* 3088 */ MCD_OPC_FilterValue, + 1, + 67, + 87, + 0, // Skip to: 25432 + /* 3093 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3096 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 3272 + /* 3101 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3104 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 3132 + /* 3109 */ MCD_OPC_CheckPredicate, + 22, + 46, + 87, + 0, // Skip to: 25432 + /* 3114 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 39, + 87, + 0, // Skip to: 25432 + /* 3121 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 32, + 87, + 0, // Skip to: 25432 + /* 3128 */ MCD_OPC_Decode, + 252, + 12, + 113, // Opcode: MVE_VST20_16 + /* 3132 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 3160 + /* 3137 */ MCD_OPC_CheckPredicate, + 22, + 18, + 87, + 0, // Skip to: 25432 + /* 3142 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 11, + 87, + 0, // Skip to: 25432 + /* 3149 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 4, + 87, + 0, // Skip to: 25432 + /* 3156 */ MCD_OPC_Decode, + 136, + 13, + 114, // Opcode: MVE_VST40_16 + /* 3160 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 3188 + /* 3165 */ MCD_OPC_CheckPredicate, + 22, + 246, + 86, + 0, // Skip to: 25432 + /* 3170 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 239, + 86, + 0, // Skip to: 25432 + /* 3177 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 232, + 86, + 0, // Skip to: 25432 + /* 3184 */ MCD_OPC_Decode, + 130, + 13, + 113, // Opcode: MVE_VST21_16 + /* 3188 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 3216 + /* 3193 */ MCD_OPC_CheckPredicate, + 22, + 218, + 86, + 0, // Skip to: 25432 + /* 3198 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 211, + 86, + 0, // Skip to: 25432 + /* 3205 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 204, + 86, + 0, // Skip to: 25432 + /* 3212 */ MCD_OPC_Decode, + 142, + 13, + 114, // Opcode: MVE_VST41_16 + /* 3216 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 3244 + /* 3221 */ MCD_OPC_CheckPredicate, + 22, + 190, + 86, + 0, // Skip to: 25432 + /* 3226 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 183, + 86, + 0, // Skip to: 25432 + /* 3233 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 176, + 86, + 0, // Skip to: 25432 + /* 3240 */ MCD_OPC_Decode, + 148, + 13, + 114, // Opcode: MVE_VST42_16 + /* 3244 */ MCD_OPC_FilterValue, + 97, + 167, + 86, + 0, // Skip to: 25432 + /* 3249 */ MCD_OPC_CheckPredicate, + 22, + 162, + 86, + 0, // Skip to: 25432 + /* 3254 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 155, + 86, + 0, // Skip to: 25432 + /* 3261 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 148, + 86, + 0, // Skip to: 25432 + /* 3268 */ MCD_OPC_Decode, + 154, + 13, + 114, // Opcode: MVE_VST43_16 + /* 3272 */ MCD_OPC_FilterValue, + 1, + 139, + 86, + 0, // Skip to: 25432 + /* 3277 */ MCD_OPC_CheckPredicate, + 22, + 134, + 86, + 0, // Skip to: 25432 + /* 3282 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 127, + 86, + 0, // Skip to: 25432 + /* 3289 */ MCD_OPC_Decode, + 183, + 13, + 117, // Opcode: MVE_VSTRHU16 + /* 3293 */ MCD_OPC_FilterValue, + 1, + 179, + 1, + 0, // Skip to: 3733 + /* 3298 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3301 */ MCD_OPC_FilterValue, + 0, + 222, + 0, + 0, // Skip to: 3528 + /* 3306 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3309 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 3485 + /* 3314 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3317 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 3345 + /* 3322 */ MCD_OPC_CheckPredicate, + 22, + 89, + 86, + 0, // Skip to: 25432 + /* 3327 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 82, + 86, + 0, // Skip to: 25432 + /* 3334 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 75, + 86, + 0, // Skip to: 25432 + /* 3341 */ MCD_OPC_Decode, + 209, + 8, + 118, // Opcode: MVE_VLD20_8 + /* 3345 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 3373 + /* 3350 */ MCD_OPC_CheckPredicate, + 22, + 61, + 86, + 0, // Skip to: 25432 + /* 3355 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 54, + 86, + 0, // Skip to: 25432 + /* 3362 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 47, + 86, + 0, // Skip to: 25432 + /* 3369 */ MCD_OPC_Decode, + 221, + 8, + 119, // Opcode: MVE_VLD40_8 + /* 3373 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 3401 + /* 3378 */ MCD_OPC_CheckPredicate, + 22, + 33, + 86, + 0, // Skip to: 25432 + /* 3383 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 26, + 86, + 0, // Skip to: 25432 + /* 3390 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 19, + 86, + 0, // Skip to: 25432 + /* 3397 */ MCD_OPC_Decode, + 215, + 8, + 118, // Opcode: MVE_VLD21_8 + /* 3401 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 3429 + /* 3406 */ MCD_OPC_CheckPredicate, + 22, + 5, + 86, + 0, // Skip to: 25432 + /* 3411 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 254, + 85, + 0, // Skip to: 25432 + /* 3418 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 247, + 85, + 0, // Skip to: 25432 + /* 3425 */ MCD_OPC_Decode, + 227, + 8, + 119, // Opcode: MVE_VLD41_8 + /* 3429 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 3457 + /* 3434 */ MCD_OPC_CheckPredicate, + 22, + 233, + 85, + 0, // Skip to: 25432 + /* 3439 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 226, + 85, + 0, // Skip to: 25432 + /* 3446 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 219, + 85, + 0, // Skip to: 25432 + /* 3453 */ MCD_OPC_Decode, + 233, + 8, + 119, // Opcode: MVE_VLD42_8 + /* 3457 */ MCD_OPC_FilterValue, + 97, + 210, + 85, + 0, // Skip to: 25432 + /* 3462 */ MCD_OPC_CheckPredicate, + 22, + 205, + 85, + 0, // Skip to: 25432 + /* 3467 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 198, + 85, + 0, // Skip to: 25432 + /* 3474 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 191, + 85, + 0, // Skip to: 25432 + /* 3481 */ MCD_OPC_Decode, + 239, + 8, + 119, // Opcode: MVE_VLD43_8 + /* 3485 */ MCD_OPC_FilterValue, + 1, + 182, + 85, + 0, // Skip to: 25432 + /* 3490 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3493 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3507 + /* 3498 */ MCD_OPC_CheckPredicate, + 22, + 169, + 85, + 0, // Skip to: 25432 + /* 3503 */ MCD_OPC_Decode, + 129, + 9, + 115, // Opcode: MVE_VLDRBU8 + /* 3507 */ MCD_OPC_FilterValue, + 15, + 160, + 85, + 0, // Skip to: 25432 + /* 3512 */ MCD_OPC_CheckPredicate, + 22, + 155, + 85, + 0, // Skip to: 25432 + /* 3517 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 148, + 85, + 0, // Skip to: 25432 + /* 3524 */ MCD_OPC_Decode, + 155, + 9, + 116, // Opcode: MVE_VLDRWU32_qi + /* 3528 */ MCD_OPC_FilterValue, + 1, + 139, + 85, + 0, // Skip to: 25432 + /* 3533 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3536 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 3712 + /* 3541 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3544 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 3572 + /* 3549 */ MCD_OPC_CheckPredicate, + 22, + 118, + 85, + 0, // Skip to: 25432 + /* 3554 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 111, + 85, + 0, // Skip to: 25432 + /* 3561 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 104, + 85, + 0, // Skip to: 25432 + /* 3568 */ MCD_OPC_Decode, + 205, + 8, + 118, // Opcode: MVE_VLD20_16 + /* 3572 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 3600 + /* 3577 */ MCD_OPC_CheckPredicate, + 22, + 90, + 85, + 0, // Skip to: 25432 + /* 3582 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 83, + 85, + 0, // Skip to: 25432 + /* 3589 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 76, + 85, + 0, // Skip to: 25432 + /* 3596 */ MCD_OPC_Decode, + 217, + 8, + 119, // Opcode: MVE_VLD40_16 + /* 3600 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 3628 + /* 3605 */ MCD_OPC_CheckPredicate, + 22, + 62, + 85, + 0, // Skip to: 25432 + /* 3610 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 55, + 85, + 0, // Skip to: 25432 + /* 3617 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 48, + 85, + 0, // Skip to: 25432 + /* 3624 */ MCD_OPC_Decode, + 211, + 8, + 118, // Opcode: MVE_VLD21_16 + /* 3628 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 3656 + /* 3633 */ MCD_OPC_CheckPredicate, + 22, + 34, + 85, + 0, // Skip to: 25432 + /* 3638 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 27, + 85, + 0, // Skip to: 25432 + /* 3645 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 20, + 85, + 0, // Skip to: 25432 + /* 3652 */ MCD_OPC_Decode, + 223, + 8, + 119, // Opcode: MVE_VLD41_16 + /* 3656 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 3684 + /* 3661 */ MCD_OPC_CheckPredicate, + 22, + 6, + 85, + 0, // Skip to: 25432 + /* 3666 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 255, + 84, + 0, // Skip to: 25432 + /* 3673 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 248, + 84, + 0, // Skip to: 25432 + /* 3680 */ MCD_OPC_Decode, + 229, + 8, + 119, // Opcode: MVE_VLD42_16 + /* 3684 */ MCD_OPC_FilterValue, + 97, + 239, + 84, + 0, // Skip to: 25432 + /* 3689 */ MCD_OPC_CheckPredicate, + 22, + 234, + 84, + 0, // Skip to: 25432 + /* 3694 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 227, + 84, + 0, // Skip to: 25432 + /* 3701 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 220, + 84, + 0, // Skip to: 25432 + /* 3708 */ MCD_OPC_Decode, + 235, + 8, + 119, // Opcode: MVE_VLD43_16 + /* 3712 */ MCD_OPC_FilterValue, + 1, + 211, + 84, + 0, // Skip to: 25432 + /* 3717 */ MCD_OPC_CheckPredicate, + 22, + 206, + 84, + 0, // Skip to: 25432 + /* 3722 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 199, + 84, + 0, // Skip to: 25432 + /* 3729 */ MCD_OPC_Decode, + 142, + 9, + 117, // Opcode: MVE_VLDRHU16 + /* 3733 */ MCD_OPC_FilterValue, + 2, + 139, + 1, + 0, // Skip to: 4133 + /* 3738 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3741 */ MCD_OPC_FilterValue, + 0, + 202, + 0, + 0, // Skip to: 3948 + /* 3746 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3749 */ MCD_OPC_FilterValue, + 0, + 151, + 0, + 0, // Skip to: 3905 + /* 3754 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3757 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3771 + /* 3762 */ MCD_OPC_CheckPredicate, + 22, + 161, + 84, + 0, // Skip to: 25432 + /* 3767 */ MCD_OPC_Decode, + 170, + 13, + 120, // Opcode: MVE_VSTRBU8_post + /* 3771 */ MCD_OPC_FilterValue, + 15, + 152, + 84, + 0, // Skip to: 25432 + /* 3776 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3779 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3800 + /* 3784 */ MCD_OPC_CheckPredicate, + 22, + 139, + 84, + 0, // Skip to: 25432 + /* 3789 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 132, + 84, + 0, // Skip to: 25432 + /* 3796 */ MCD_OPC_Decode, + 129, + 13, + 121, // Opcode: MVE_VST20_8_wb + /* 3800 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 3821 + /* 3805 */ MCD_OPC_CheckPredicate, + 22, + 118, + 84, + 0, // Skip to: 25432 + /* 3810 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 111, + 84, + 0, // Skip to: 25432 + /* 3817 */ MCD_OPC_Decode, + 141, + 13, + 122, // Opcode: MVE_VST40_8_wb + /* 3821 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 3842 + /* 3826 */ MCD_OPC_CheckPredicate, + 22, + 97, + 84, + 0, // Skip to: 25432 + /* 3831 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 90, + 84, + 0, // Skip to: 25432 + /* 3838 */ MCD_OPC_Decode, + 135, + 13, + 121, // Opcode: MVE_VST21_8_wb + /* 3842 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 3863 + /* 3847 */ MCD_OPC_CheckPredicate, + 22, + 76, + 84, + 0, // Skip to: 25432 + /* 3852 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 69, + 84, + 0, // Skip to: 25432 + /* 3859 */ MCD_OPC_Decode, + 147, + 13, + 122, // Opcode: MVE_VST41_8_wb + /* 3863 */ MCD_OPC_FilterValue, + 65, + 16, + 0, + 0, // Skip to: 3884 + /* 3868 */ MCD_OPC_CheckPredicate, + 22, + 55, + 84, + 0, // Skip to: 25432 + /* 3873 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 48, + 84, + 0, // Skip to: 25432 + /* 3880 */ MCD_OPC_Decode, + 153, + 13, + 122, // Opcode: MVE_VST42_8_wb + /* 3884 */ MCD_OPC_FilterValue, + 97, + 39, + 84, + 0, // Skip to: 25432 + /* 3889 */ MCD_OPC_CheckPredicate, + 22, + 34, + 84, + 0, // Skip to: 25432 + /* 3894 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 27, + 84, + 0, // Skip to: 25432 + /* 3901 */ MCD_OPC_Decode, + 159, + 13, + 122, // Opcode: MVE_VST43_8_wb + /* 3905 */ MCD_OPC_FilterValue, + 1, + 18, + 84, + 0, // Skip to: 25432 + /* 3910 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3913 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3927 + /* 3918 */ MCD_OPC_CheckPredicate, + 22, + 5, + 84, + 0, // Skip to: 25432 + /* 3923 */ MCD_OPC_Decode, + 171, + 13, + 123, // Opcode: MVE_VSTRBU8_pre + /* 3927 */ MCD_OPC_FilterValue, + 15, + 252, + 83, + 0, // Skip to: 25432 + /* 3932 */ MCD_OPC_CheckPredicate, + 22, + 247, + 83, + 0, // Skip to: 25432 + /* 3937 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 240, + 83, + 0, // Skip to: 25432 + /* 3944 */ MCD_OPC_Decode, + 187, + 13, + 124, // Opcode: MVE_VSTRW32_qi_pre + /* 3948 */ MCD_OPC_FilterValue, + 1, + 231, + 83, + 0, // Skip to: 25432 + /* 3953 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 3956 */ MCD_OPC_FilterValue, + 0, + 151, + 0, + 0, // Skip to: 4112 + /* 3961 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3964 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 3978 + /* 3969 */ MCD_OPC_CheckPredicate, + 22, + 210, + 83, + 0, // Skip to: 25432 + /* 3974 */ MCD_OPC_Decode, + 184, + 13, + 125, // Opcode: MVE_VSTRHU16_post + /* 3978 */ MCD_OPC_FilterValue, + 15, + 201, + 83, + 0, // Skip to: 25432 + /* 3983 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3986 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4007 + /* 3991 */ MCD_OPC_CheckPredicate, + 22, + 188, + 83, + 0, // Skip to: 25432 + /* 3996 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 181, + 83, + 0, // Skip to: 25432 + /* 4003 */ MCD_OPC_Decode, + 253, + 12, + 121, // Opcode: MVE_VST20_16_wb + /* 4007 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 4028 + /* 4012 */ MCD_OPC_CheckPredicate, + 22, + 167, + 83, + 0, // Skip to: 25432 + /* 4017 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 160, + 83, + 0, // Skip to: 25432 + /* 4024 */ MCD_OPC_Decode, + 137, + 13, + 122, // Opcode: MVE_VST40_16_wb + /* 4028 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 4049 + /* 4033 */ MCD_OPC_CheckPredicate, + 22, + 146, + 83, + 0, // Skip to: 25432 + /* 4038 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 139, + 83, + 0, // Skip to: 25432 + /* 4045 */ MCD_OPC_Decode, + 131, + 13, + 121, // Opcode: MVE_VST21_16_wb + /* 4049 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 4070 + /* 4054 */ MCD_OPC_CheckPredicate, + 22, + 125, + 83, + 0, // Skip to: 25432 + /* 4059 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 118, + 83, + 0, // Skip to: 25432 + /* 4066 */ MCD_OPC_Decode, + 143, + 13, + 122, // Opcode: MVE_VST41_16_wb + /* 4070 */ MCD_OPC_FilterValue, + 65, + 16, + 0, + 0, // Skip to: 4091 + /* 4075 */ MCD_OPC_CheckPredicate, + 22, + 104, + 83, + 0, // Skip to: 25432 + /* 4080 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 97, + 83, + 0, // Skip to: 25432 + /* 4087 */ MCD_OPC_Decode, + 149, + 13, + 122, // Opcode: MVE_VST42_16_wb + /* 4091 */ MCD_OPC_FilterValue, + 97, + 88, + 83, + 0, // Skip to: 25432 + /* 4096 */ MCD_OPC_CheckPredicate, + 22, + 83, + 83, + 0, // Skip to: 25432 + /* 4101 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 76, + 83, + 0, // Skip to: 25432 + /* 4108 */ MCD_OPC_Decode, + 155, + 13, + 122, // Opcode: MVE_VST43_16_wb + /* 4112 */ MCD_OPC_FilterValue, + 1, + 67, + 83, + 0, // Skip to: 25432 + /* 4117 */ MCD_OPC_CheckPredicate, + 22, + 62, + 83, + 0, // Skip to: 25432 + /* 4122 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 55, + 83, + 0, // Skip to: 25432 + /* 4129 */ MCD_OPC_Decode, + 185, + 13, + 126, // Opcode: MVE_VSTRHU16_pre + /* 4133 */ MCD_OPC_FilterValue, + 3, + 46, + 83, + 0, // Skip to: 25432 + /* 4138 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4141 */ MCD_OPC_FilterValue, + 0, + 206, + 0, + 0, // Skip to: 4352 + /* 4146 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4149 */ MCD_OPC_FilterValue, + 0, + 155, + 0, + 0, // Skip to: 4309 + /* 4154 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4157 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4171 + /* 4162 */ MCD_OPC_CheckPredicate, + 22, + 17, + 83, + 0, // Skip to: 25432 + /* 4167 */ MCD_OPC_Decode, + 130, + 9, + 120, // Opcode: MVE_VLDRBU8_post + /* 4171 */ MCD_OPC_FilterValue, + 15, + 8, + 83, + 0, // Skip to: 25432 + /* 4176 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 4179 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4200 + /* 4184 */ MCD_OPC_CheckPredicate, + 22, + 251, + 82, + 0, // Skip to: 25432 + /* 4189 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 244, + 82, + 0, // Skip to: 25432 + /* 4196 */ MCD_OPC_Decode, + 210, + 8, + 127, // Opcode: MVE_VLD20_8_wb + /* 4200 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 4222 + /* 4205 */ MCD_OPC_CheckPredicate, + 22, + 230, + 82, + 0, // Skip to: 25432 + /* 4210 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 223, + 82, + 0, // Skip to: 25432 + /* 4217 */ MCD_OPC_Decode, + 222, + 8, + 128, + 1, // Opcode: MVE_VLD40_8_wb + /* 4222 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 4243 + /* 4227 */ MCD_OPC_CheckPredicate, + 22, + 208, + 82, + 0, // Skip to: 25432 + /* 4232 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 201, + 82, + 0, // Skip to: 25432 + /* 4239 */ MCD_OPC_Decode, + 216, + 8, + 127, // Opcode: MVE_VLD21_8_wb + /* 4243 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 4265 + /* 4248 */ MCD_OPC_CheckPredicate, + 22, + 187, + 82, + 0, // Skip to: 25432 + /* 4253 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 180, + 82, + 0, // Skip to: 25432 + /* 4260 */ MCD_OPC_Decode, + 228, + 8, + 128, + 1, // Opcode: MVE_VLD41_8_wb + /* 4265 */ MCD_OPC_FilterValue, + 65, + 17, + 0, + 0, // Skip to: 4287 + /* 4270 */ MCD_OPC_CheckPredicate, + 22, + 165, + 82, + 0, // Skip to: 25432 + /* 4275 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 158, + 82, + 0, // Skip to: 25432 + /* 4282 */ MCD_OPC_Decode, + 234, + 8, + 128, + 1, // Opcode: MVE_VLD42_8_wb + /* 4287 */ MCD_OPC_FilterValue, + 97, + 148, + 82, + 0, // Skip to: 25432 + /* 4292 */ MCD_OPC_CheckPredicate, + 22, + 143, + 82, + 0, // Skip to: 25432 + /* 4297 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 136, + 82, + 0, // Skip to: 25432 + /* 4304 */ MCD_OPC_Decode, + 240, + 8, + 128, + 1, // Opcode: MVE_VLD43_8_wb + /* 4309 */ MCD_OPC_FilterValue, + 1, + 126, + 82, + 0, // Skip to: 25432 + /* 4314 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4317 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4331 + /* 4322 */ MCD_OPC_CheckPredicate, + 22, + 113, + 82, + 0, // Skip to: 25432 + /* 4327 */ MCD_OPC_Decode, + 131, + 9, + 123, // Opcode: MVE_VLDRBU8_pre + /* 4331 */ MCD_OPC_FilterValue, + 15, + 104, + 82, + 0, // Skip to: 25432 + /* 4336 */ MCD_OPC_CheckPredicate, + 22, + 99, + 82, + 0, // Skip to: 25432 + /* 4341 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 92, + 82, + 0, // Skip to: 25432 + /* 4348 */ MCD_OPC_Decode, + 156, + 9, + 124, // Opcode: MVE_VLDRWU32_qi_pre + /* 4352 */ MCD_OPC_FilterValue, + 1, + 83, + 82, + 0, // Skip to: 25432 + /* 4357 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4360 */ MCD_OPC_FilterValue, + 0, + 155, + 0, + 0, // Skip to: 4520 + /* 4365 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4368 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4382 + /* 4373 */ MCD_OPC_CheckPredicate, + 22, + 62, + 82, + 0, // Skip to: 25432 + /* 4378 */ MCD_OPC_Decode, + 143, + 9, + 125, // Opcode: MVE_VLDRHU16_post + /* 4382 */ MCD_OPC_FilterValue, + 15, + 53, + 82, + 0, // Skip to: 25432 + /* 4387 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 4390 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4411 + /* 4395 */ MCD_OPC_CheckPredicate, + 22, + 40, + 82, + 0, // Skip to: 25432 + /* 4400 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 33, + 82, + 0, // Skip to: 25432 + /* 4407 */ MCD_OPC_Decode, + 206, + 8, + 127, // Opcode: MVE_VLD20_16_wb + /* 4411 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 4433 + /* 4416 */ MCD_OPC_CheckPredicate, + 22, + 19, + 82, + 0, // Skip to: 25432 + /* 4421 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 12, + 82, + 0, // Skip to: 25432 + /* 4428 */ MCD_OPC_Decode, + 218, + 8, + 128, + 1, // Opcode: MVE_VLD40_16_wb + /* 4433 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 4454 + /* 4438 */ MCD_OPC_CheckPredicate, + 22, + 253, + 81, + 0, // Skip to: 25432 + /* 4443 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 246, + 81, + 0, // Skip to: 25432 + /* 4450 */ MCD_OPC_Decode, + 212, + 8, + 127, // Opcode: MVE_VLD21_16_wb + /* 4454 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 4476 + /* 4459 */ MCD_OPC_CheckPredicate, + 22, + 232, + 81, + 0, // Skip to: 25432 + /* 4464 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 225, + 81, + 0, // Skip to: 25432 + /* 4471 */ MCD_OPC_Decode, + 224, + 8, + 128, + 1, // Opcode: MVE_VLD41_16_wb + /* 4476 */ MCD_OPC_FilterValue, + 65, + 17, + 0, + 0, // Skip to: 4498 + /* 4481 */ MCD_OPC_CheckPredicate, + 22, + 210, + 81, + 0, // Skip to: 25432 + /* 4486 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 203, + 81, + 0, // Skip to: 25432 + /* 4493 */ MCD_OPC_Decode, + 230, + 8, + 128, + 1, // Opcode: MVE_VLD42_16_wb + /* 4498 */ MCD_OPC_FilterValue, + 97, + 193, + 81, + 0, // Skip to: 25432 + /* 4503 */ MCD_OPC_CheckPredicate, + 22, + 188, + 81, + 0, // Skip to: 25432 + /* 4508 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 181, + 81, + 0, // Skip to: 25432 + /* 4515 */ MCD_OPC_Decode, + 236, + 8, + 128, + 1, // Opcode: MVE_VLD43_16_wb + /* 4520 */ MCD_OPC_FilterValue, + 1, + 171, + 81, + 0, // Skip to: 25432 + /* 4525 */ MCD_OPC_CheckPredicate, + 22, + 166, + 81, + 0, // Skip to: 25432 + /* 4530 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 159, + 81, + 0, // Skip to: 25432 + /* 4537 */ MCD_OPC_Decode, + 144, + 9, + 126, // Opcode: MVE_VLDRHU16_pre + /* 4541 */ MCD_OPC_FilterValue, + 31, + 150, + 81, + 0, // Skip to: 25432 + /* 4546 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 4549 */ MCD_OPC_FilterValue, + 0, + 238, + 0, + 0, // Skip to: 4792 + /* 4554 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4557 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 4733 + /* 4562 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 4565 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 4593 + /* 4570 */ MCD_OPC_CheckPredicate, + 22, + 121, + 81, + 0, // Skip to: 25432 + /* 4575 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 114, + 81, + 0, // Skip to: 25432 + /* 4582 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 107, + 81, + 0, // Skip to: 25432 + /* 4589 */ MCD_OPC_Decode, + 254, + 12, + 113, // Opcode: MVE_VST20_32 + /* 4593 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 4621 + /* 4598 */ MCD_OPC_CheckPredicate, + 22, + 93, + 81, + 0, // Skip to: 25432 + /* 4603 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 86, + 81, + 0, // Skip to: 25432 + /* 4610 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 79, + 81, + 0, // Skip to: 25432 + /* 4617 */ MCD_OPC_Decode, + 138, + 13, + 114, // Opcode: MVE_VST40_32 + /* 4621 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 4649 + /* 4626 */ MCD_OPC_CheckPredicate, + 22, + 65, + 81, + 0, // Skip to: 25432 + /* 4631 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 58, + 81, + 0, // Skip to: 25432 + /* 4638 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 51, + 81, + 0, // Skip to: 25432 + /* 4645 */ MCD_OPC_Decode, + 132, + 13, + 113, // Opcode: MVE_VST21_32 + /* 4649 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 4677 + /* 4654 */ MCD_OPC_CheckPredicate, + 22, + 37, + 81, + 0, // Skip to: 25432 + /* 4659 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 30, + 81, + 0, // Skip to: 25432 + /* 4666 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 23, + 81, + 0, // Skip to: 25432 + /* 4673 */ MCD_OPC_Decode, + 144, + 13, + 114, // Opcode: MVE_VST41_32 + /* 4677 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 4705 + /* 4682 */ MCD_OPC_CheckPredicate, + 22, + 9, + 81, + 0, // Skip to: 25432 + /* 4687 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 2, + 81, + 0, // Skip to: 25432 + /* 4694 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 251, + 80, + 0, // Skip to: 25432 + /* 4701 */ MCD_OPC_Decode, + 150, + 13, + 114, // Opcode: MVE_VST42_32 + /* 4705 */ MCD_OPC_FilterValue, + 97, + 242, + 80, + 0, // Skip to: 25432 + /* 4710 */ MCD_OPC_CheckPredicate, + 22, + 237, + 80, + 0, // Skip to: 25432 + /* 4715 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 230, + 80, + 0, // Skip to: 25432 + /* 4722 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 223, + 80, + 0, // Skip to: 25432 + /* 4729 */ MCD_OPC_Decode, + 156, + 13, + 114, // Opcode: MVE_VST43_32 + /* 4733 */ MCD_OPC_FilterValue, + 1, + 214, + 80, + 0, // Skip to: 25432 + /* 4738 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4741 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 4763 + /* 4746 */ MCD_OPC_CheckPredicate, + 22, + 201, + 80, + 0, // Skip to: 25432 + /* 4751 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 194, + 80, + 0, // Skip to: 25432 + /* 4758 */ MCD_OPC_Decode, + 190, + 13, + 129, + 1, // Opcode: MVE_VSTRWU32 + /* 4763 */ MCD_OPC_FilterValue, + 15, + 184, + 80, + 0, // Skip to: 25432 + /* 4768 */ MCD_OPC_CheckPredicate, + 22, + 179, + 80, + 0, // Skip to: 25432 + /* 4773 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 172, + 80, + 0, // Skip to: 25432 + /* 4780 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 165, + 80, + 0, // Skip to: 25432 + /* 4787 */ MCD_OPC_Decode, + 172, + 13, + 130, + 1, // Opcode: MVE_VSTRD64_qi + /* 4792 */ MCD_OPC_FilterValue, + 1, + 238, + 0, + 0, // Skip to: 5035 + /* 4797 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 4800 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 4976 + /* 4805 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 4808 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 4836 + /* 4813 */ MCD_OPC_CheckPredicate, + 22, + 134, + 80, + 0, // Skip to: 25432 + /* 4818 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 127, + 80, + 0, // Skip to: 25432 + /* 4825 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 120, + 80, + 0, // Skip to: 25432 + /* 4832 */ MCD_OPC_Decode, + 207, + 8, + 118, // Opcode: MVE_VLD20_32 + /* 4836 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 4864 + /* 4841 */ MCD_OPC_CheckPredicate, + 22, + 106, + 80, + 0, // Skip to: 25432 + /* 4846 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 99, + 80, + 0, // Skip to: 25432 + /* 4853 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 92, + 80, + 0, // Skip to: 25432 + /* 4860 */ MCD_OPC_Decode, + 219, + 8, + 119, // Opcode: MVE_VLD40_32 + /* 4864 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 4892 + /* 4869 */ MCD_OPC_CheckPredicate, + 22, + 78, + 80, + 0, // Skip to: 25432 + /* 4874 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 71, + 80, + 0, // Skip to: 25432 + /* 4881 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 64, + 80, + 0, // Skip to: 25432 + /* 4888 */ MCD_OPC_Decode, + 213, + 8, + 118, // Opcode: MVE_VLD21_32 + /* 4892 */ MCD_OPC_FilterValue, + 33, + 23, + 0, + 0, // Skip to: 4920 + /* 4897 */ MCD_OPC_CheckPredicate, + 22, + 50, + 80, + 0, // Skip to: 25432 + /* 4902 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 43, + 80, + 0, // Skip to: 25432 + /* 4909 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 36, + 80, + 0, // Skip to: 25432 + /* 4916 */ MCD_OPC_Decode, + 225, + 8, + 119, // Opcode: MVE_VLD41_32 + /* 4920 */ MCD_OPC_FilterValue, + 65, + 23, + 0, + 0, // Skip to: 4948 + /* 4925 */ MCD_OPC_CheckPredicate, + 22, + 22, + 80, + 0, // Skip to: 25432 + /* 4930 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 15, + 80, + 0, // Skip to: 25432 + /* 4937 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 8, + 80, + 0, // Skip to: 25432 + /* 4944 */ MCD_OPC_Decode, + 231, + 8, + 119, // Opcode: MVE_VLD42_32 + /* 4948 */ MCD_OPC_FilterValue, + 97, + 255, + 79, + 0, // Skip to: 25432 + /* 4953 */ MCD_OPC_CheckPredicate, + 22, + 250, + 79, + 0, // Skip to: 25432 + /* 4958 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 243, + 79, + 0, // Skip to: 25432 + /* 4965 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 236, + 79, + 0, // Skip to: 25432 + /* 4972 */ MCD_OPC_Decode, + 237, + 8, + 119, // Opcode: MVE_VLD43_32 + /* 4976 */ MCD_OPC_FilterValue, + 1, + 227, + 79, + 0, // Skip to: 25432 + /* 4981 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 4984 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5006 + /* 4989 */ MCD_OPC_CheckPredicate, + 22, + 214, + 79, + 0, // Skip to: 25432 + /* 4994 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 207, + 79, + 0, // Skip to: 25432 + /* 5001 */ MCD_OPC_Decode, + 152, + 9, + 129, + 1, // Opcode: MVE_VLDRWU32 + /* 5006 */ MCD_OPC_FilterValue, + 15, + 197, + 79, + 0, // Skip to: 25432 + /* 5011 */ MCD_OPC_CheckPredicate, + 22, + 192, + 79, + 0, // Skip to: 25432 + /* 5016 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 185, + 79, + 0, // Skip to: 25432 + /* 5023 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 178, + 79, + 0, // Skip to: 25432 + /* 5030 */ MCD_OPC_Decode, + 133, + 9, + 130, + 1, // Opcode: MVE_VLDRDU64_qi + /* 5035 */ MCD_OPC_FilterValue, + 2, + 226, + 0, + 0, // Skip to: 5266 + /* 5040 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 5043 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 5207 + /* 5048 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5051 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5073 + /* 5056 */ MCD_OPC_CheckPredicate, + 22, + 147, + 79, + 0, // Skip to: 25432 + /* 5061 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 140, + 79, + 0, // Skip to: 25432 + /* 5068 */ MCD_OPC_Decode, + 191, + 13, + 131, + 1, // Opcode: MVE_VSTRWU32_post + /* 5073 */ MCD_OPC_FilterValue, + 15, + 130, + 79, + 0, // Skip to: 25432 + /* 5078 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 5081 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 5102 + /* 5086 */ MCD_OPC_CheckPredicate, + 22, + 117, + 79, + 0, // Skip to: 25432 + /* 5091 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 110, + 79, + 0, // Skip to: 25432 + /* 5098 */ MCD_OPC_Decode, + 255, + 12, + 121, // Opcode: MVE_VST20_32_wb + /* 5102 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 5123 + /* 5107 */ MCD_OPC_CheckPredicate, + 22, + 96, + 79, + 0, // Skip to: 25432 + /* 5112 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 89, + 79, + 0, // Skip to: 25432 + /* 5119 */ MCD_OPC_Decode, + 139, + 13, + 122, // Opcode: MVE_VST40_32_wb + /* 5123 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 5144 + /* 5128 */ MCD_OPC_CheckPredicate, + 22, + 75, + 79, + 0, // Skip to: 25432 + /* 5133 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 68, + 79, + 0, // Skip to: 25432 + /* 5140 */ MCD_OPC_Decode, + 133, + 13, + 121, // Opcode: MVE_VST21_32_wb + /* 5144 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 5165 + /* 5149 */ MCD_OPC_CheckPredicate, + 22, + 54, + 79, + 0, // Skip to: 25432 + /* 5154 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 47, + 79, + 0, // Skip to: 25432 + /* 5161 */ MCD_OPC_Decode, + 145, + 13, + 122, // Opcode: MVE_VST41_32_wb + /* 5165 */ MCD_OPC_FilterValue, + 65, + 16, + 0, + 0, // Skip to: 5186 + /* 5170 */ MCD_OPC_CheckPredicate, + 22, + 33, + 79, + 0, // Skip to: 25432 + /* 5175 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 26, + 79, + 0, // Skip to: 25432 + /* 5182 */ MCD_OPC_Decode, + 151, + 13, + 122, // Opcode: MVE_VST42_32_wb + /* 5186 */ MCD_OPC_FilterValue, + 97, + 17, + 79, + 0, // Skip to: 25432 + /* 5191 */ MCD_OPC_CheckPredicate, + 22, + 12, + 79, + 0, // Skip to: 25432 + /* 5196 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 5, + 79, + 0, // Skip to: 25432 + /* 5203 */ MCD_OPC_Decode, + 157, + 13, + 122, // Opcode: MVE_VST43_32_wb + /* 5207 */ MCD_OPC_FilterValue, + 1, + 252, + 78, + 0, // Skip to: 25432 + /* 5212 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5215 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5237 + /* 5220 */ MCD_OPC_CheckPredicate, + 22, + 239, + 78, + 0, // Skip to: 25432 + /* 5225 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 232, + 78, + 0, // Skip to: 25432 + /* 5232 */ MCD_OPC_Decode, + 192, + 13, + 132, + 1, // Opcode: MVE_VSTRWU32_pre + /* 5237 */ MCD_OPC_FilterValue, + 15, + 222, + 78, + 0, // Skip to: 25432 + /* 5242 */ MCD_OPC_CheckPredicate, + 22, + 217, + 78, + 0, // Skip to: 25432 + /* 5247 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 210, + 78, + 0, // Skip to: 25432 + /* 5254 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 203, + 78, + 0, // Skip to: 25432 + /* 5261 */ MCD_OPC_Decode, + 173, + 13, + 133, + 1, // Opcode: MVE_VSTRD64_qi_pre + /* 5266 */ MCD_OPC_FilterValue, + 3, + 193, + 78, + 0, // Skip to: 25432 + /* 5271 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 5274 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 5442 + /* 5279 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5282 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5304 + /* 5287 */ MCD_OPC_CheckPredicate, + 22, + 172, + 78, + 0, // Skip to: 25432 + /* 5292 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 165, + 78, + 0, // Skip to: 25432 + /* 5299 */ MCD_OPC_Decode, + 153, + 9, + 131, + 1, // Opcode: MVE_VLDRWU32_post + /* 5304 */ MCD_OPC_FilterValue, + 15, + 155, + 78, + 0, // Skip to: 25432 + /* 5309 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 5312 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 5333 + /* 5317 */ MCD_OPC_CheckPredicate, + 22, + 142, + 78, + 0, // Skip to: 25432 + /* 5322 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 135, + 78, + 0, // Skip to: 25432 + /* 5329 */ MCD_OPC_Decode, + 208, + 8, + 127, // Opcode: MVE_VLD20_32_wb + /* 5333 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 5355 + /* 5338 */ MCD_OPC_CheckPredicate, + 22, + 121, + 78, + 0, // Skip to: 25432 + /* 5343 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 114, + 78, + 0, // Skip to: 25432 + /* 5350 */ MCD_OPC_Decode, + 220, + 8, + 128, + 1, // Opcode: MVE_VLD40_32_wb + /* 5355 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 5376 + /* 5360 */ MCD_OPC_CheckPredicate, + 22, + 99, + 78, + 0, // Skip to: 25432 + /* 5365 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 92, + 78, + 0, // Skip to: 25432 + /* 5372 */ MCD_OPC_Decode, + 214, + 8, + 127, // Opcode: MVE_VLD21_32_wb + /* 5376 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 5398 + /* 5381 */ MCD_OPC_CheckPredicate, + 22, + 78, + 78, + 0, // Skip to: 25432 + /* 5386 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 71, + 78, + 0, // Skip to: 25432 + /* 5393 */ MCD_OPC_Decode, + 226, + 8, + 128, + 1, // Opcode: MVE_VLD41_32_wb + /* 5398 */ MCD_OPC_FilterValue, + 65, + 17, + 0, + 0, // Skip to: 5420 + /* 5403 */ MCD_OPC_CheckPredicate, + 22, + 56, + 78, + 0, // Skip to: 25432 + /* 5408 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 49, + 78, + 0, // Skip to: 25432 + /* 5415 */ MCD_OPC_Decode, + 232, + 8, + 128, + 1, // Opcode: MVE_VLD42_32_wb + /* 5420 */ MCD_OPC_FilterValue, + 97, + 39, + 78, + 0, // Skip to: 25432 + /* 5425 */ MCD_OPC_CheckPredicate, + 22, + 34, + 78, + 0, // Skip to: 25432 + /* 5430 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 27, + 78, + 0, // Skip to: 25432 + /* 5437 */ MCD_OPC_Decode, + 238, + 8, + 128, + 1, // Opcode: MVE_VLD43_32_wb + /* 5442 */ MCD_OPC_FilterValue, + 1, + 17, + 78, + 0, // Skip to: 25432 + /* 5447 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5450 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5472 + /* 5455 */ MCD_OPC_CheckPredicate, + 22, + 4, + 78, + 0, // Skip to: 25432 + /* 5460 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 253, + 77, + 0, // Skip to: 25432 + /* 5467 */ MCD_OPC_Decode, + 154, + 9, + 132, + 1, // Opcode: MVE_VLDRWU32_pre + /* 5472 */ MCD_OPC_FilterValue, + 15, + 243, + 77, + 0, // Skip to: 25432 + /* 5477 */ MCD_OPC_CheckPredicate, + 22, + 238, + 77, + 0, // Skip to: 25432 + /* 5482 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 231, + 77, + 0, // Skip to: 25432 + /* 5489 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 224, + 77, + 0, // Skip to: 25432 + /* 5496 */ MCD_OPC_Decode, + 134, + 9, + 133, + 1, // Opcode: MVE_VLDRDU64_qi_pre + /* 5501 */ MCD_OPC_FilterValue, + 7, + 214, + 77, + 0, // Skip to: 25432 + /* 5506 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 5509 */ MCD_OPC_FilterValue, + 0, + 19, + 29, + 0, // Skip to: 12957 + /* 5514 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 5517 */ MCD_OPC_FilterValue, + 11, + 195, + 0, + 0, // Skip to: 5717 + /* 5522 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5525 */ MCD_OPC_FilterValue, + 0, + 91, + 0, + 0, // Skip to: 5621 + /* 5530 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5533 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 5592 + /* 5538 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 5541 */ MCD_OPC_FilterValue, + 16, + 24, + 0, + 0, // Skip to: 5570 + /* 5546 */ MCD_OPC_CheckPredicate, + 25, + 169, + 77, + 0, // Skip to: 25432 + /* 5551 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 162, + 77, + 0, // Skip to: 25432 + /* 5558 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 155, + 77, + 0, // Skip to: 25432 + /* 5565 */ MCD_OPC_Decode, + 165, + 10, + 134, + 1, // Opcode: MVE_VMOV_to_lane_32 + /* 5570 */ MCD_OPC_FilterValue, + 48, + 145, + 77, + 0, // Skip to: 25432 + /* 5575 */ MCD_OPC_CheckPredicate, + 23, + 140, + 77, + 0, // Skip to: 25432 + /* 5580 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 133, + 77, + 0, // Skip to: 25432 + /* 5587 */ MCD_OPC_Decode, + 164, + 10, + 135, + 1, // Opcode: MVE_VMOV_to_lane_16 + /* 5592 */ MCD_OPC_FilterValue, + 1, + 123, + 77, + 0, // Skip to: 25432 + /* 5597 */ MCD_OPC_CheckPredicate, + 23, + 118, + 77, + 0, // Skip to: 25432 + /* 5602 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 111, + 77, + 0, // Skip to: 25432 + /* 5609 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 104, + 77, + 0, // Skip to: 25432 + /* 5616 */ MCD_OPC_Decode, + 166, + 10, + 136, + 1, // Opcode: MVE_VMOV_to_lane_8 + /* 5621 */ MCD_OPC_FilterValue, + 1, + 94, + 77, + 0, // Skip to: 25432 + /* 5626 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 5629 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 5688 + /* 5634 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 5637 */ MCD_OPC_FilterValue, + 16, + 24, + 0, + 0, // Skip to: 5666 + /* 5642 */ MCD_OPC_CheckPredicate, + 25, + 73, + 77, + 0, // Skip to: 25432 + /* 5647 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 66, + 77, + 0, // Skip to: 25432 + /* 5654 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 59, + 77, + 0, // Skip to: 25432 + /* 5661 */ MCD_OPC_Decode, + 157, + 10, + 137, + 1, // Opcode: MVE_VMOV_from_lane_32 + /* 5666 */ MCD_OPC_FilterValue, + 48, + 49, + 77, + 0, // Skip to: 25432 + /* 5671 */ MCD_OPC_CheckPredicate, + 23, + 44, + 77, + 0, // Skip to: 25432 + /* 5676 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 37, + 77, + 0, // Skip to: 25432 + /* 5683 */ MCD_OPC_Decode, + 158, + 10, + 138, + 1, // Opcode: MVE_VMOV_from_lane_s16 + /* 5688 */ MCD_OPC_FilterValue, + 1, + 27, + 77, + 0, // Skip to: 25432 + /* 5693 */ MCD_OPC_CheckPredicate, + 23, + 22, + 77, + 0, // Skip to: 25432 + /* 5698 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 15, + 77, + 0, // Skip to: 25432 + /* 5705 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 8, + 77, + 0, // Skip to: 25432 + /* 5712 */ MCD_OPC_Decode, + 159, + 10, + 139, + 1, // Opcode: MVE_VMOV_from_lane_s8 + /* 5717 */ MCD_OPC_FilterValue, + 14, + 15, + 17, + 0, // Skip to: 10089 + /* 5722 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5725 */ MCD_OPC_FilterValue, + 0, + 3, + 3, + 0, // Skip to: 6501 + /* 5730 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5733 */ MCD_OPC_FilterValue, + 0, + 211, + 1, + 0, // Skip to: 6205 + /* 5738 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 5741 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 5973 + /* 5746 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 5749 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 5861 + /* 5754 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 5757 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 5809 + /* 5762 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5765 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5787 + /* 5770 */ MCD_OPC_CheckPredicate, + 22, + 201, + 76, + 0, // Skip to: 25432 + /* 5775 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 194, + 76, + 0, // Skip to: 25432 + /* 5782 */ MCD_OPC_Decode, + 133, + 11, + 140, + 1, // Opcode: MVE_VQDMLADHs8 + /* 5787 */ MCD_OPC_FilterValue, + 15, + 184, + 76, + 0, // Skip to: 25432 + /* 5792 */ MCD_OPC_CheckPredicate, + 22, + 179, + 76, + 0, // Skip to: 25432 + /* 5797 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 172, + 76, + 0, // Skip to: 25432 + /* 5804 */ MCD_OPC_Decode, + 145, + 11, + 140, + 1, // Opcode: MVE_VQDMLSDHs8 + /* 5809 */ MCD_OPC_FilterValue, + 1, + 162, + 76, + 0, // Skip to: 25432 + /* 5814 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5817 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5839 + /* 5822 */ MCD_OPC_CheckPredicate, + 22, + 149, + 76, + 0, // Skip to: 25432 + /* 5827 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 142, + 76, + 0, // Skip to: 25432 + /* 5834 */ MCD_OPC_Decode, + 182, + 10, + 141, + 1, // Opcode: MVE_VMULLBs8 + /* 5839 */ MCD_OPC_FilterValue, + 15, + 132, + 76, + 0, // Skip to: 25432 + /* 5844 */ MCD_OPC_CheckPredicate, + 22, + 127, + 76, + 0, // Skip to: 25432 + /* 5849 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 120, + 76, + 0, // Skip to: 25432 + /* 5856 */ MCD_OPC_Decode, + 185, + 10, + 141, + 1, // Opcode: MVE_VMULLBu8 + /* 5861 */ MCD_OPC_FilterValue, + 1, + 110, + 76, + 0, // Skip to: 25432 + /* 5866 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 5869 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 5921 + /* 5874 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5877 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5899 + /* 5882 */ MCD_OPC_CheckPredicate, + 22, + 89, + 76, + 0, // Skip to: 25432 + /* 5887 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 82, + 76, + 0, // Skip to: 25432 + /* 5894 */ MCD_OPC_Decode, + 130, + 11, + 140, + 1, // Opcode: MVE_VQDMLADHXs8 + /* 5899 */ MCD_OPC_FilterValue, + 15, + 72, + 76, + 0, // Skip to: 25432 + /* 5904 */ MCD_OPC_CheckPredicate, + 22, + 67, + 76, + 0, // Skip to: 25432 + /* 5909 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 60, + 76, + 0, // Skip to: 25432 + /* 5916 */ MCD_OPC_Decode, + 142, + 11, + 140, + 1, // Opcode: MVE_VQDMLSDHXs8 + /* 5921 */ MCD_OPC_FilterValue, + 1, + 50, + 76, + 0, // Skip to: 25432 + /* 5926 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5929 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 5951 + /* 5934 */ MCD_OPC_CheckPredicate, + 22, + 37, + 76, + 0, // Skip to: 25432 + /* 5939 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 30, + 76, + 0, // Skip to: 25432 + /* 5946 */ MCD_OPC_Decode, + 190, + 10, + 141, + 1, // Opcode: MVE_VMULLTs8 + /* 5951 */ MCD_OPC_FilterValue, + 15, + 20, + 76, + 0, // Skip to: 25432 + /* 5956 */ MCD_OPC_CheckPredicate, + 22, + 15, + 76, + 0, // Skip to: 25432 + /* 5961 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 8, + 76, + 0, // Skip to: 25432 + /* 5968 */ MCD_OPC_Decode, + 193, + 10, + 141, + 1, // Opcode: MVE_VMULLTu8 + /* 5973 */ MCD_OPC_FilterValue, + 1, + 254, + 75, + 0, // Skip to: 25432 + /* 5978 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 5981 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 6093 + /* 5986 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 5989 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6041 + /* 5994 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 5997 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6019 + /* 6002 */ MCD_OPC_CheckPredicate, + 22, + 225, + 75, + 0, // Skip to: 25432 + /* 6007 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 218, + 75, + 0, // Skip to: 25432 + /* 6014 */ MCD_OPC_Decode, + 180, + 11, + 140, + 1, // Opcode: MVE_VQRDMLADHs8 + /* 6019 */ MCD_OPC_FilterValue, + 15, + 208, + 75, + 0, // Skip to: 25432 + /* 6024 */ MCD_OPC_CheckPredicate, + 22, + 203, + 75, + 0, // Skip to: 25432 + /* 6029 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 196, + 75, + 0, // Skip to: 25432 + /* 6036 */ MCD_OPC_Decode, + 192, + 11, + 140, + 1, // Opcode: MVE_VQRDMLSDHs8 + /* 6041 */ MCD_OPC_FilterValue, + 1, + 186, + 75, + 0, // Skip to: 25432 + /* 6046 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6049 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6071 + /* 6054 */ MCD_OPC_CheckPredicate, + 22, + 173, + 75, + 0, // Skip to: 25432 + /* 6059 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 166, + 75, + 0, // Skip to: 25432 + /* 6066 */ MCD_OPC_Decode, + 174, + 10, + 141, + 1, // Opcode: MVE_VMULHs8 + /* 6071 */ MCD_OPC_FilterValue, + 15, + 156, + 75, + 0, // Skip to: 25432 + /* 6076 */ MCD_OPC_CheckPredicate, + 22, + 151, + 75, + 0, // Skip to: 25432 + /* 6081 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 144, + 75, + 0, // Skip to: 25432 + /* 6088 */ MCD_OPC_Decode, + 177, + 10, + 141, + 1, // Opcode: MVE_VMULHu8 + /* 6093 */ MCD_OPC_FilterValue, + 1, + 134, + 75, + 0, // Skip to: 25432 + /* 6098 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6101 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6153 + /* 6106 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6109 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6131 + /* 6114 */ MCD_OPC_CheckPredicate, + 22, + 113, + 75, + 0, // Skip to: 25432 + /* 6119 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 106, + 75, + 0, // Skip to: 25432 + /* 6126 */ MCD_OPC_Decode, + 177, + 11, + 140, + 1, // Opcode: MVE_VQRDMLADHXs8 + /* 6131 */ MCD_OPC_FilterValue, + 15, + 96, + 75, + 0, // Skip to: 25432 + /* 6136 */ MCD_OPC_CheckPredicate, + 22, + 91, + 75, + 0, // Skip to: 25432 + /* 6141 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 84, + 75, + 0, // Skip to: 25432 + /* 6148 */ MCD_OPC_Decode, + 189, + 11, + 140, + 1, // Opcode: MVE_VQRDMLSDHXs8 + /* 6153 */ MCD_OPC_FilterValue, + 1, + 74, + 75, + 0, // Skip to: 25432 + /* 6158 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6161 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6183 + /* 6166 */ MCD_OPC_CheckPredicate, + 22, + 61, + 75, + 0, // Skip to: 25432 + /* 6171 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 54, + 75, + 0, // Skip to: 25432 + /* 6178 */ MCD_OPC_Decode, + 176, + 12, + 141, + 1, // Opcode: MVE_VRMULHs8 + /* 6183 */ MCD_OPC_FilterValue, + 15, + 44, + 75, + 0, // Skip to: 25432 + /* 6188 */ MCD_OPC_CheckPredicate, + 22, + 39, + 75, + 0, // Skip to: 25432 + /* 6193 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 32, + 75, + 0, // Skip to: 25432 + /* 6200 */ MCD_OPC_Decode, + 179, + 12, + 141, + 1, // Opcode: MVE_VRMULHu8 + /* 6205 */ MCD_OPC_FilterValue, + 1, + 22, + 75, + 0, // Skip to: 25432 + /* 6210 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 6213 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 6357 + /* 6218 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6221 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 6289 + /* 6226 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6229 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6251 + /* 6234 */ MCD_OPC_CheckPredicate, + 22, + 249, + 74, + 0, // Skip to: 25432 + /* 6239 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 242, + 74, + 0, // Skip to: 25432 + /* 6246 */ MCD_OPC_Decode, + 183, + 11, + 142, + 1, // Opcode: MVE_VQRDMLAH_qrs8 + /* 6251 */ MCD_OPC_FilterValue, + 1, + 232, + 74, + 0, // Skip to: 25432 + /* 6256 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6259 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 6274 + /* 6264 */ MCD_OPC_CheckPredicate, + 22, + 219, + 74, + 0, // Skip to: 25432 + /* 6269 */ MCD_OPC_Decode, + 249, + 9, + 142, + 1, // Opcode: MVE_VMLA_qr_s8 + /* 6274 */ MCD_OPC_FilterValue, + 15, + 209, + 74, + 0, // Skip to: 25432 + /* 6279 */ MCD_OPC_CheckPredicate, + 22, + 204, + 74, + 0, // Skip to: 25432 + /* 6284 */ MCD_OPC_Decode, + 252, + 9, + 142, + 1, // Opcode: MVE_VMLA_qr_u8 + /* 6289 */ MCD_OPC_FilterValue, + 1, + 194, + 74, + 0, // Skip to: 25432 + /* 6294 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6297 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6319 + /* 6302 */ MCD_OPC_CheckPredicate, + 22, + 181, + 74, + 0, // Skip to: 25432 + /* 6307 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 174, + 74, + 0, // Skip to: 25432 + /* 6314 */ MCD_OPC_Decode, + 186, + 11, + 142, + 1, // Opcode: MVE_VQRDMLASH_qrs8 + /* 6319 */ MCD_OPC_FilterValue, + 1, + 164, + 74, + 0, // Skip to: 25432 + /* 6324 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6327 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 6342 + /* 6332 */ MCD_OPC_CheckPredicate, + 22, + 151, + 74, + 0, // Skip to: 25432 + /* 6337 */ MCD_OPC_Decode, + 243, + 9, + 142, + 1, // Opcode: MVE_VMLAS_qr_s8 + /* 6342 */ MCD_OPC_FilterValue, + 15, + 141, + 74, + 0, // Skip to: 25432 + /* 6347 */ MCD_OPC_CheckPredicate, + 22, + 136, + 74, + 0, // Skip to: 25432 + /* 6352 */ MCD_OPC_Decode, + 246, + 9, + 142, + 1, // Opcode: MVE_VMLAS_qr_u8 + /* 6357 */ MCD_OPC_FilterValue, + 2, + 126, + 74, + 0, // Skip to: 25432 + /* 6362 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6365 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 6433 + /* 6370 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6373 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6395 + /* 6378 */ MCD_OPC_CheckPredicate, + 22, + 105, + 74, + 0, // Skip to: 25432 + /* 6383 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 98, + 74, + 0, // Skip to: 25432 + /* 6390 */ MCD_OPC_Decode, + 136, + 11, + 142, + 1, // Opcode: MVE_VQDMLAH_qrs8 + /* 6395 */ MCD_OPC_FilterValue, + 1, + 88, + 74, + 0, // Skip to: 25432 + /* 6400 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6403 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 6418 + /* 6408 */ MCD_OPC_CheckPredicate, + 22, + 75, + 74, + 0, // Skip to: 25432 + /* 6413 */ MCD_OPC_Decode, + 148, + 11, + 143, + 1, // Opcode: MVE_VQDMULH_qr_s8 + /* 6418 */ MCD_OPC_FilterValue, + 15, + 65, + 74, + 0, // Skip to: 25432 + /* 6423 */ MCD_OPC_CheckPredicate, + 22, + 60, + 74, + 0, // Skip to: 25432 + /* 6428 */ MCD_OPC_Decode, + 195, + 11, + 143, + 1, // Opcode: MVE_VQRDMULH_qr_s8 + /* 6433 */ MCD_OPC_FilterValue, + 1, + 50, + 74, + 0, // Skip to: 25432 + /* 6438 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6441 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6463 + /* 6446 */ MCD_OPC_CheckPredicate, + 22, + 37, + 74, + 0, // Skip to: 25432 + /* 6451 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 30, + 74, + 0, // Skip to: 25432 + /* 6458 */ MCD_OPC_Decode, + 139, + 11, + 142, + 1, // Opcode: MVE_VQDMLASH_qrs8 + /* 6463 */ MCD_OPC_FilterValue, + 1, + 20, + 74, + 0, // Skip to: 25432 + /* 6468 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6471 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 6486 + /* 6476 */ MCD_OPC_CheckPredicate, + 22, + 7, + 74, + 0, // Skip to: 25432 + /* 6481 */ MCD_OPC_Decode, + 198, + 10, + 143, + 1, // Opcode: MVE_VMUL_qr_i8 + /* 6486 */ MCD_OPC_FilterValue, + 15, + 253, + 73, + 0, // Skip to: 25432 + /* 6491 */ MCD_OPC_CheckPredicate, + 22, + 248, + 73, + 0, // Skip to: 25432 + /* 6496 */ MCD_OPC_Decode, + 204, + 7, + 143, + 1, // Opcode: MVE_VBRSR8 + /* 6501 */ MCD_OPC_FilterValue, + 1, + 3, + 3, + 0, // Skip to: 7277 + /* 6506 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6509 */ MCD_OPC_FilterValue, + 0, + 211, + 1, + 0, // Skip to: 6981 + /* 6514 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 6517 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 6749 + /* 6522 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6525 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 6637 + /* 6530 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6533 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6585 + /* 6538 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6541 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6563 + /* 6546 */ MCD_OPC_CheckPredicate, + 22, + 193, + 73, + 0, // Skip to: 25432 + /* 6551 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 186, + 73, + 0, // Skip to: 25432 + /* 6558 */ MCD_OPC_Decode, + 131, + 11, + 140, + 1, // Opcode: MVE_VQDMLADHs16 + /* 6563 */ MCD_OPC_FilterValue, + 15, + 176, + 73, + 0, // Skip to: 25432 + /* 6568 */ MCD_OPC_CheckPredicate, + 22, + 171, + 73, + 0, // Skip to: 25432 + /* 6573 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 164, + 73, + 0, // Skip to: 25432 + /* 6580 */ MCD_OPC_Decode, + 143, + 11, + 140, + 1, // Opcode: MVE_VQDMLSDHs16 + /* 6585 */ MCD_OPC_FilterValue, + 1, + 154, + 73, + 0, // Skip to: 25432 + /* 6590 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6593 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6615 + /* 6598 */ MCD_OPC_CheckPredicate, + 22, + 141, + 73, + 0, // Skip to: 25432 + /* 6603 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 134, + 73, + 0, // Skip to: 25432 + /* 6610 */ MCD_OPC_Decode, + 180, + 10, + 141, + 1, // Opcode: MVE_VMULLBs16 + /* 6615 */ MCD_OPC_FilterValue, + 15, + 124, + 73, + 0, // Skip to: 25432 + /* 6620 */ MCD_OPC_CheckPredicate, + 22, + 119, + 73, + 0, // Skip to: 25432 + /* 6625 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 112, + 73, + 0, // Skip to: 25432 + /* 6632 */ MCD_OPC_Decode, + 183, + 10, + 141, + 1, // Opcode: MVE_VMULLBu16 + /* 6637 */ MCD_OPC_FilterValue, + 1, + 102, + 73, + 0, // Skip to: 25432 + /* 6642 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6645 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6697 + /* 6650 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6653 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6675 + /* 6658 */ MCD_OPC_CheckPredicate, + 22, + 81, + 73, + 0, // Skip to: 25432 + /* 6663 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 74, + 73, + 0, // Skip to: 25432 + /* 6670 */ MCD_OPC_Decode, + 128, + 11, + 140, + 1, // Opcode: MVE_VQDMLADHXs16 + /* 6675 */ MCD_OPC_FilterValue, + 15, + 64, + 73, + 0, // Skip to: 25432 + /* 6680 */ MCD_OPC_CheckPredicate, + 22, + 59, + 73, + 0, // Skip to: 25432 + /* 6685 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 52, + 73, + 0, // Skip to: 25432 + /* 6692 */ MCD_OPC_Decode, + 140, + 11, + 140, + 1, // Opcode: MVE_VQDMLSDHXs16 + /* 6697 */ MCD_OPC_FilterValue, + 1, + 42, + 73, + 0, // Skip to: 25432 + /* 6702 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6705 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6727 + /* 6710 */ MCD_OPC_CheckPredicate, + 22, + 29, + 73, + 0, // Skip to: 25432 + /* 6715 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 22, + 73, + 0, // Skip to: 25432 + /* 6722 */ MCD_OPC_Decode, + 188, + 10, + 141, + 1, // Opcode: MVE_VMULLTs16 + /* 6727 */ MCD_OPC_FilterValue, + 15, + 12, + 73, + 0, // Skip to: 25432 + /* 6732 */ MCD_OPC_CheckPredicate, + 22, + 7, + 73, + 0, // Skip to: 25432 + /* 6737 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 0, + 73, + 0, // Skip to: 25432 + /* 6744 */ MCD_OPC_Decode, + 191, + 10, + 141, + 1, // Opcode: MVE_VMULLTu16 + /* 6749 */ MCD_OPC_FilterValue, + 1, + 246, + 72, + 0, // Skip to: 25432 + /* 6754 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6757 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 6869 + /* 6762 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6765 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6817 + /* 6770 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6773 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6795 + /* 6778 */ MCD_OPC_CheckPredicate, + 22, + 217, + 72, + 0, // Skip to: 25432 + /* 6783 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 210, + 72, + 0, // Skip to: 25432 + /* 6790 */ MCD_OPC_Decode, + 178, + 11, + 140, + 1, // Opcode: MVE_VQRDMLADHs16 + /* 6795 */ MCD_OPC_FilterValue, + 15, + 200, + 72, + 0, // Skip to: 25432 + /* 6800 */ MCD_OPC_CheckPredicate, + 22, + 195, + 72, + 0, // Skip to: 25432 + /* 6805 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 188, + 72, + 0, // Skip to: 25432 + /* 6812 */ MCD_OPC_Decode, + 190, + 11, + 140, + 1, // Opcode: MVE_VQRDMLSDHs16 + /* 6817 */ MCD_OPC_FilterValue, + 1, + 178, + 72, + 0, // Skip to: 25432 + /* 6822 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6825 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6847 + /* 6830 */ MCD_OPC_CheckPredicate, + 22, + 165, + 72, + 0, // Skip to: 25432 + /* 6835 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 158, + 72, + 0, // Skip to: 25432 + /* 6842 */ MCD_OPC_Decode, + 172, + 10, + 141, + 1, // Opcode: MVE_VMULHs16 + /* 6847 */ MCD_OPC_FilterValue, + 15, + 148, + 72, + 0, // Skip to: 25432 + /* 6852 */ MCD_OPC_CheckPredicate, + 22, + 143, + 72, + 0, // Skip to: 25432 + /* 6857 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 136, + 72, + 0, // Skip to: 25432 + /* 6864 */ MCD_OPC_Decode, + 175, + 10, + 141, + 1, // Opcode: MVE_VMULHu16 + /* 6869 */ MCD_OPC_FilterValue, + 1, + 126, + 72, + 0, // Skip to: 25432 + /* 6874 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 6877 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 6929 + /* 6882 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6885 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6907 + /* 6890 */ MCD_OPC_CheckPredicate, + 22, + 105, + 72, + 0, // Skip to: 25432 + /* 6895 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 98, + 72, + 0, // Skip to: 25432 + /* 6902 */ MCD_OPC_Decode, + 175, + 11, + 140, + 1, // Opcode: MVE_VQRDMLADHXs16 + /* 6907 */ MCD_OPC_FilterValue, + 15, + 88, + 72, + 0, // Skip to: 25432 + /* 6912 */ MCD_OPC_CheckPredicate, + 22, + 83, + 72, + 0, // Skip to: 25432 + /* 6917 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 76, + 72, + 0, // Skip to: 25432 + /* 6924 */ MCD_OPC_Decode, + 187, + 11, + 140, + 1, // Opcode: MVE_VQRDMLSDHXs16 + /* 6929 */ MCD_OPC_FilterValue, + 1, + 66, + 72, + 0, // Skip to: 25432 + /* 6934 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 6937 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 6959 + /* 6942 */ MCD_OPC_CheckPredicate, + 22, + 53, + 72, + 0, // Skip to: 25432 + /* 6947 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 46, + 72, + 0, // Skip to: 25432 + /* 6954 */ MCD_OPC_Decode, + 174, + 12, + 141, + 1, // Opcode: MVE_VRMULHs16 + /* 6959 */ MCD_OPC_FilterValue, + 15, + 36, + 72, + 0, // Skip to: 25432 + /* 6964 */ MCD_OPC_CheckPredicate, + 22, + 31, + 72, + 0, // Skip to: 25432 + /* 6969 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 24, + 72, + 0, // Skip to: 25432 + /* 6976 */ MCD_OPC_Decode, + 177, + 12, + 141, + 1, // Opcode: MVE_VRMULHu16 + /* 6981 */ MCD_OPC_FilterValue, + 1, + 14, + 72, + 0, // Skip to: 25432 + /* 6986 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 6989 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 7133 + /* 6994 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 6997 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 7065 + /* 7002 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7005 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7027 + /* 7010 */ MCD_OPC_CheckPredicate, + 22, + 241, + 71, + 0, // Skip to: 25432 + /* 7015 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 234, + 71, + 0, // Skip to: 25432 + /* 7022 */ MCD_OPC_Decode, + 181, + 11, + 142, + 1, // Opcode: MVE_VQRDMLAH_qrs16 + /* 7027 */ MCD_OPC_FilterValue, + 1, + 224, + 71, + 0, // Skip to: 25432 + /* 7032 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7035 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7050 + /* 7040 */ MCD_OPC_CheckPredicate, + 22, + 211, + 71, + 0, // Skip to: 25432 + /* 7045 */ MCD_OPC_Decode, + 247, + 9, + 142, + 1, // Opcode: MVE_VMLA_qr_s16 + /* 7050 */ MCD_OPC_FilterValue, + 15, + 201, + 71, + 0, // Skip to: 25432 + /* 7055 */ MCD_OPC_CheckPredicate, + 22, + 196, + 71, + 0, // Skip to: 25432 + /* 7060 */ MCD_OPC_Decode, + 250, + 9, + 142, + 1, // Opcode: MVE_VMLA_qr_u16 + /* 7065 */ MCD_OPC_FilterValue, + 1, + 186, + 71, + 0, // Skip to: 25432 + /* 7070 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7073 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7095 + /* 7078 */ MCD_OPC_CheckPredicate, + 22, + 173, + 71, + 0, // Skip to: 25432 + /* 7083 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 166, + 71, + 0, // Skip to: 25432 + /* 7090 */ MCD_OPC_Decode, + 184, + 11, + 142, + 1, // Opcode: MVE_VQRDMLASH_qrs16 + /* 7095 */ MCD_OPC_FilterValue, + 1, + 156, + 71, + 0, // Skip to: 25432 + /* 7100 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7103 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7118 + /* 7108 */ MCD_OPC_CheckPredicate, + 22, + 143, + 71, + 0, // Skip to: 25432 + /* 7113 */ MCD_OPC_Decode, + 241, + 9, + 142, + 1, // Opcode: MVE_VMLAS_qr_s16 + /* 7118 */ MCD_OPC_FilterValue, + 15, + 133, + 71, + 0, // Skip to: 25432 + /* 7123 */ MCD_OPC_CheckPredicate, + 22, + 128, + 71, + 0, // Skip to: 25432 + /* 7128 */ MCD_OPC_Decode, + 244, + 9, + 142, + 1, // Opcode: MVE_VMLAS_qr_u16 + /* 7133 */ MCD_OPC_FilterValue, + 2, + 118, + 71, + 0, // Skip to: 25432 + /* 7138 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7141 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 7209 + /* 7146 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7149 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7171 + /* 7154 */ MCD_OPC_CheckPredicate, + 22, + 97, + 71, + 0, // Skip to: 25432 + /* 7159 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 90, + 71, + 0, // Skip to: 25432 + /* 7166 */ MCD_OPC_Decode, + 134, + 11, + 142, + 1, // Opcode: MVE_VQDMLAH_qrs16 + /* 7171 */ MCD_OPC_FilterValue, + 1, + 80, + 71, + 0, // Skip to: 25432 + /* 7176 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7179 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7194 + /* 7184 */ MCD_OPC_CheckPredicate, + 22, + 67, + 71, + 0, // Skip to: 25432 + /* 7189 */ MCD_OPC_Decode, + 146, + 11, + 143, + 1, // Opcode: MVE_VQDMULH_qr_s16 + /* 7194 */ MCD_OPC_FilterValue, + 15, + 57, + 71, + 0, // Skip to: 25432 + /* 7199 */ MCD_OPC_CheckPredicate, + 22, + 52, + 71, + 0, // Skip to: 25432 + /* 7204 */ MCD_OPC_Decode, + 193, + 11, + 143, + 1, // Opcode: MVE_VQRDMULH_qr_s16 + /* 7209 */ MCD_OPC_FilterValue, + 1, + 42, + 71, + 0, // Skip to: 25432 + /* 7214 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7217 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7239 + /* 7222 */ MCD_OPC_CheckPredicate, + 22, + 29, + 71, + 0, // Skip to: 25432 + /* 7227 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 22, + 71, + 0, // Skip to: 25432 + /* 7234 */ MCD_OPC_Decode, + 137, + 11, + 142, + 1, // Opcode: MVE_VQDMLASH_qrs16 + /* 7239 */ MCD_OPC_FilterValue, + 1, + 12, + 71, + 0, // Skip to: 25432 + /* 7244 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7247 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7262 + /* 7252 */ MCD_OPC_CheckPredicate, + 22, + 255, + 70, + 0, // Skip to: 25432 + /* 7257 */ MCD_OPC_Decode, + 196, + 10, + 143, + 1, // Opcode: MVE_VMUL_qr_i16 + /* 7262 */ MCD_OPC_FilterValue, + 15, + 245, + 70, + 0, // Skip to: 25432 + /* 7267 */ MCD_OPC_CheckPredicate, + 22, + 240, + 70, + 0, // Skip to: 25432 + /* 7272 */ MCD_OPC_Decode, + 202, + 7, + 143, + 1, // Opcode: MVE_VBRSR16 + /* 7277 */ MCD_OPC_FilterValue, + 2, + 3, + 3, + 0, // Skip to: 8053 + /* 7282 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 7285 */ MCD_OPC_FilterValue, + 0, + 211, + 1, + 0, // Skip to: 7757 + /* 7290 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 7293 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 7525 + /* 7298 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7301 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 7413 + /* 7306 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7309 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7361 + /* 7314 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7317 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7339 + /* 7322 */ MCD_OPC_CheckPredicate, + 22, + 185, + 70, + 0, // Skip to: 25432 + /* 7327 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 178, + 70, + 0, // Skip to: 25432 + /* 7334 */ MCD_OPC_Decode, + 132, + 11, + 140, + 1, // Opcode: MVE_VQDMLADHs32 + /* 7339 */ MCD_OPC_FilterValue, + 15, + 168, + 70, + 0, // Skip to: 25432 + /* 7344 */ MCD_OPC_CheckPredicate, + 22, + 163, + 70, + 0, // Skip to: 25432 + /* 7349 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 156, + 70, + 0, // Skip to: 25432 + /* 7356 */ MCD_OPC_Decode, + 144, + 11, + 140, + 1, // Opcode: MVE_VQDMLSDHs32 + /* 7361 */ MCD_OPC_FilterValue, + 1, + 146, + 70, + 0, // Skip to: 25432 + /* 7366 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7369 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7391 + /* 7374 */ MCD_OPC_CheckPredicate, + 22, + 133, + 70, + 0, // Skip to: 25432 + /* 7379 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 126, + 70, + 0, // Skip to: 25432 + /* 7386 */ MCD_OPC_Decode, + 181, + 10, + 141, + 1, // Opcode: MVE_VMULLBs32 + /* 7391 */ MCD_OPC_FilterValue, + 15, + 116, + 70, + 0, // Skip to: 25432 + /* 7396 */ MCD_OPC_CheckPredicate, + 22, + 111, + 70, + 0, // Skip to: 25432 + /* 7401 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 104, + 70, + 0, // Skip to: 25432 + /* 7408 */ MCD_OPC_Decode, + 184, + 10, + 141, + 1, // Opcode: MVE_VMULLBu32 + /* 7413 */ MCD_OPC_FilterValue, + 1, + 94, + 70, + 0, // Skip to: 25432 + /* 7418 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7421 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7473 + /* 7426 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7429 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7451 + /* 7434 */ MCD_OPC_CheckPredicate, + 22, + 73, + 70, + 0, // Skip to: 25432 + /* 7439 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 66, + 70, + 0, // Skip to: 25432 + /* 7446 */ MCD_OPC_Decode, + 129, + 11, + 140, + 1, // Opcode: MVE_VQDMLADHXs32 + /* 7451 */ MCD_OPC_FilterValue, + 15, + 56, + 70, + 0, // Skip to: 25432 + /* 7456 */ MCD_OPC_CheckPredicate, + 22, + 51, + 70, + 0, // Skip to: 25432 + /* 7461 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 44, + 70, + 0, // Skip to: 25432 + /* 7468 */ MCD_OPC_Decode, + 141, + 11, + 140, + 1, // Opcode: MVE_VQDMLSDHXs32 + /* 7473 */ MCD_OPC_FilterValue, + 1, + 34, + 70, + 0, // Skip to: 25432 + /* 7478 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7481 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7503 + /* 7486 */ MCD_OPC_CheckPredicate, + 22, + 21, + 70, + 0, // Skip to: 25432 + /* 7491 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 14, + 70, + 0, // Skip to: 25432 + /* 7498 */ MCD_OPC_Decode, + 189, + 10, + 141, + 1, // Opcode: MVE_VMULLTs32 + /* 7503 */ MCD_OPC_FilterValue, + 15, + 4, + 70, + 0, // Skip to: 25432 + /* 7508 */ MCD_OPC_CheckPredicate, + 22, + 255, + 69, + 0, // Skip to: 25432 + /* 7513 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 248, + 69, + 0, // Skip to: 25432 + /* 7520 */ MCD_OPC_Decode, + 192, + 10, + 141, + 1, // Opcode: MVE_VMULLTu32 + /* 7525 */ MCD_OPC_FilterValue, + 1, + 238, + 69, + 0, // Skip to: 25432 + /* 7530 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7533 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 7645 + /* 7538 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7541 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7593 + /* 7546 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7549 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7571 + /* 7554 */ MCD_OPC_CheckPredicate, + 22, + 209, + 69, + 0, // Skip to: 25432 + /* 7559 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 202, + 69, + 0, // Skip to: 25432 + /* 7566 */ MCD_OPC_Decode, + 179, + 11, + 140, + 1, // Opcode: MVE_VQRDMLADHs32 + /* 7571 */ MCD_OPC_FilterValue, + 15, + 192, + 69, + 0, // Skip to: 25432 + /* 7576 */ MCD_OPC_CheckPredicate, + 22, + 187, + 69, + 0, // Skip to: 25432 + /* 7581 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 180, + 69, + 0, // Skip to: 25432 + /* 7588 */ MCD_OPC_Decode, + 191, + 11, + 140, + 1, // Opcode: MVE_VQRDMLSDHs32 + /* 7593 */ MCD_OPC_FilterValue, + 1, + 170, + 69, + 0, // Skip to: 25432 + /* 7598 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7601 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7623 + /* 7606 */ MCD_OPC_CheckPredicate, + 22, + 157, + 69, + 0, // Skip to: 25432 + /* 7611 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 150, + 69, + 0, // Skip to: 25432 + /* 7618 */ MCD_OPC_Decode, + 173, + 10, + 141, + 1, // Opcode: MVE_VMULHs32 + /* 7623 */ MCD_OPC_FilterValue, + 15, + 140, + 69, + 0, // Skip to: 25432 + /* 7628 */ MCD_OPC_CheckPredicate, + 22, + 135, + 69, + 0, // Skip to: 25432 + /* 7633 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 128, + 69, + 0, // Skip to: 25432 + /* 7640 */ MCD_OPC_Decode, + 176, + 10, + 141, + 1, // Opcode: MVE_VMULHu32 + /* 7645 */ MCD_OPC_FilterValue, + 1, + 118, + 69, + 0, // Skip to: 25432 + /* 7650 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7653 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 7705 + /* 7658 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7661 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7683 + /* 7666 */ MCD_OPC_CheckPredicate, + 22, + 97, + 69, + 0, // Skip to: 25432 + /* 7671 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 90, + 69, + 0, // Skip to: 25432 + /* 7678 */ MCD_OPC_Decode, + 176, + 11, + 140, + 1, // Opcode: MVE_VQRDMLADHXs32 + /* 7683 */ MCD_OPC_FilterValue, + 15, + 80, + 69, + 0, // Skip to: 25432 + /* 7688 */ MCD_OPC_CheckPredicate, + 22, + 75, + 69, + 0, // Skip to: 25432 + /* 7693 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 68, + 69, + 0, // Skip to: 25432 + /* 7700 */ MCD_OPC_Decode, + 188, + 11, + 140, + 1, // Opcode: MVE_VQRDMLSDHXs32 + /* 7705 */ MCD_OPC_FilterValue, + 1, + 58, + 69, + 0, // Skip to: 25432 + /* 7710 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7713 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 7735 + /* 7718 */ MCD_OPC_CheckPredicate, + 22, + 45, + 69, + 0, // Skip to: 25432 + /* 7723 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 38, + 69, + 0, // Skip to: 25432 + /* 7730 */ MCD_OPC_Decode, + 175, + 12, + 141, + 1, // Opcode: MVE_VRMULHs32 + /* 7735 */ MCD_OPC_FilterValue, + 15, + 28, + 69, + 0, // Skip to: 25432 + /* 7740 */ MCD_OPC_CheckPredicate, + 22, + 23, + 69, + 0, // Skip to: 25432 + /* 7745 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 16, + 69, + 0, // Skip to: 25432 + /* 7752 */ MCD_OPC_Decode, + 178, + 12, + 141, + 1, // Opcode: MVE_VRMULHu32 + /* 7757 */ MCD_OPC_FilterValue, + 1, + 6, + 69, + 0, // Skip to: 25432 + /* 7762 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 7765 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 7909 + /* 7770 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7773 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 7841 + /* 7778 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7781 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7803 + /* 7786 */ MCD_OPC_CheckPredicate, + 22, + 233, + 68, + 0, // Skip to: 25432 + /* 7791 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 226, + 68, + 0, // Skip to: 25432 + /* 7798 */ MCD_OPC_Decode, + 182, + 11, + 142, + 1, // Opcode: MVE_VQRDMLAH_qrs32 + /* 7803 */ MCD_OPC_FilterValue, + 1, + 216, + 68, + 0, // Skip to: 25432 + /* 7808 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7811 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7826 + /* 7816 */ MCD_OPC_CheckPredicate, + 22, + 203, + 68, + 0, // Skip to: 25432 + /* 7821 */ MCD_OPC_Decode, + 248, + 9, + 142, + 1, // Opcode: MVE_VMLA_qr_s32 + /* 7826 */ MCD_OPC_FilterValue, + 15, + 193, + 68, + 0, // Skip to: 25432 + /* 7831 */ MCD_OPC_CheckPredicate, + 22, + 188, + 68, + 0, // Skip to: 25432 + /* 7836 */ MCD_OPC_Decode, + 251, + 9, + 142, + 1, // Opcode: MVE_VMLA_qr_u32 + /* 7841 */ MCD_OPC_FilterValue, + 1, + 178, + 68, + 0, // Skip to: 25432 + /* 7846 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7849 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7871 + /* 7854 */ MCD_OPC_CheckPredicate, + 22, + 165, + 68, + 0, // Skip to: 25432 + /* 7859 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 158, + 68, + 0, // Skip to: 25432 + /* 7866 */ MCD_OPC_Decode, + 185, + 11, + 142, + 1, // Opcode: MVE_VQRDMLASH_qrs32 + /* 7871 */ MCD_OPC_FilterValue, + 1, + 148, + 68, + 0, // Skip to: 25432 + /* 7876 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7879 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7894 + /* 7884 */ MCD_OPC_CheckPredicate, + 22, + 135, + 68, + 0, // Skip to: 25432 + /* 7889 */ MCD_OPC_Decode, + 242, + 9, + 142, + 1, // Opcode: MVE_VMLAS_qr_s32 + /* 7894 */ MCD_OPC_FilterValue, + 15, + 125, + 68, + 0, // Skip to: 25432 + /* 7899 */ MCD_OPC_CheckPredicate, + 22, + 120, + 68, + 0, // Skip to: 25432 + /* 7904 */ MCD_OPC_Decode, + 245, + 9, + 142, + 1, // Opcode: MVE_VMLAS_qr_u32 + /* 7909 */ MCD_OPC_FilterValue, + 2, + 110, + 68, + 0, // Skip to: 25432 + /* 7914 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 7917 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 7985 + /* 7922 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7925 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7947 + /* 7930 */ MCD_OPC_CheckPredicate, + 22, + 89, + 68, + 0, // Skip to: 25432 + /* 7935 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 82, + 68, + 0, // Skip to: 25432 + /* 7942 */ MCD_OPC_Decode, + 135, + 11, + 142, + 1, // Opcode: MVE_VQDMLAH_qrs32 + /* 7947 */ MCD_OPC_FilterValue, + 1, + 72, + 68, + 0, // Skip to: 25432 + /* 7952 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 7955 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7970 + /* 7960 */ MCD_OPC_CheckPredicate, + 22, + 59, + 68, + 0, // Skip to: 25432 + /* 7965 */ MCD_OPC_Decode, + 147, + 11, + 143, + 1, // Opcode: MVE_VQDMULH_qr_s32 + /* 7970 */ MCD_OPC_FilterValue, + 15, + 49, + 68, + 0, // Skip to: 25432 + /* 7975 */ MCD_OPC_CheckPredicate, + 22, + 44, + 68, + 0, // Skip to: 25432 + /* 7980 */ MCD_OPC_Decode, + 194, + 11, + 143, + 1, // Opcode: MVE_VQRDMULH_qr_s32 + /* 7985 */ MCD_OPC_FilterValue, + 1, + 34, + 68, + 0, // Skip to: 25432 + /* 7990 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 7993 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 8015 + /* 7998 */ MCD_OPC_CheckPredicate, + 22, + 21, + 68, + 0, // Skip to: 25432 + /* 8003 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 14, + 68, + 0, // Skip to: 25432 + /* 8010 */ MCD_OPC_Decode, + 138, + 11, + 142, + 1, // Opcode: MVE_VQDMLASH_qrs32 + /* 8015 */ MCD_OPC_FilterValue, + 1, + 4, + 68, + 0, // Skip to: 25432 + /* 8020 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8023 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 8038 + /* 8028 */ MCD_OPC_CheckPredicate, + 22, + 247, + 67, + 0, // Skip to: 25432 + /* 8033 */ MCD_OPC_Decode, + 197, + 10, + 143, + 1, // Opcode: MVE_VMUL_qr_i32 + /* 8038 */ MCD_OPC_FilterValue, + 15, + 237, + 67, + 0, // Skip to: 25432 + /* 8043 */ MCD_OPC_CheckPredicate, + 22, + 232, + 67, + 0, // Skip to: 25432 + /* 8048 */ MCD_OPC_Decode, + 203, + 7, + 143, + 1, // Opcode: MVE_VBRSR32 + /* 8053 */ MCD_OPC_FilterValue, + 3, + 222, + 67, + 0, // Skip to: 25432 + /* 8058 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 8061 */ MCD_OPC_FilterValue, + 0, + 51, + 5, + 0, // Skip to: 9397 + /* 8066 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 8069 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8121 + /* 8074 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8077 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8099 + /* 8082 */ MCD_OPC_CheckPredicate, + 24, + 193, + 67, + 0, // Skip to: 25432 + /* 8087 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 186, + 67, + 0, // Skip to: 25432 + /* 8094 */ MCD_OPC_Decode, + 240, + 7, + 144, + 1, // Opcode: MVE_VCMULf16 + /* 8099 */ MCD_OPC_FilterValue, + 15, + 176, + 67, + 0, // Skip to: 25432 + /* 8104 */ MCD_OPC_CheckPredicate, + 24, + 171, + 67, + 0, // Skip to: 25432 + /* 8109 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 164, + 67, + 0, // Skip to: 25432 + /* 8116 */ MCD_OPC_Decode, + 241, + 7, + 144, + 1, // Opcode: MVE_VCMULf32 + /* 8121 */ MCD_OPC_FilterValue, + 1, + 154, + 67, + 0, // Skip to: 25432 + /* 8126 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 8129 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 8241 + /* 8134 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8137 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8189 + /* 8142 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8145 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8167 + /* 8150 */ MCD_OPC_CheckPredicate, + 22, + 125, + 67, + 0, // Skip to: 25432 + /* 8155 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 118, + 67, + 0, // Skip to: 25432 + /* 8162 */ MCD_OPC_Decode, + 179, + 10, + 141, + 1, // Opcode: MVE_VMULLBp8 + /* 8167 */ MCD_OPC_FilterValue, + 15, + 108, + 67, + 0, // Skip to: 25432 + /* 8172 */ MCD_OPC_CheckPredicate, + 22, + 103, + 67, + 0, // Skip to: 25432 + /* 8177 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 96, + 67, + 0, // Skip to: 25432 + /* 8184 */ MCD_OPC_Decode, + 178, + 10, + 141, + 1, // Opcode: MVE_VMULLBp16 + /* 8189 */ MCD_OPC_FilterValue, + 1, + 86, + 67, + 0, // Skip to: 25432 + /* 8194 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8197 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8219 + /* 8202 */ MCD_OPC_CheckPredicate, + 22, + 73, + 67, + 0, // Skip to: 25432 + /* 8207 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 66, + 67, + 0, // Skip to: 25432 + /* 8214 */ MCD_OPC_Decode, + 187, + 10, + 141, + 1, // Opcode: MVE_VMULLTp8 + /* 8219 */ MCD_OPC_FilterValue, + 15, + 56, + 67, + 0, // Skip to: 25432 + /* 8224 */ MCD_OPC_CheckPredicate, + 22, + 51, + 67, + 0, // Skip to: 25432 + /* 8229 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 44, + 67, + 0, // Skip to: 25432 + /* 8236 */ MCD_OPC_Decode, + 186, + 10, + 141, + 1, // Opcode: MVE_VMULLTp16 + /* 8241 */ MCD_OPC_FilterValue, + 1, + 34, + 67, + 0, // Skip to: 25432 + /* 8246 */ MCD_OPC_ExtractField, + 17, + 3, // Inst{19-17} ... + /* 8249 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 8481 + /* 8254 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 8257 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 8369 + /* 8262 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8265 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8317 + /* 8270 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8273 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8295 + /* 8278 */ MCD_OPC_CheckPredicate, + 22, + 253, + 66, + 0, // Skip to: 25432 + /* 8283 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 246, + 66, + 0, // Skip to: 25432 + /* 8290 */ MCD_OPC_Decode, + 215, + 12, + 145, + 1, // Opcode: MVE_VSHLL_lws8bh + /* 8295 */ MCD_OPC_FilterValue, + 15, + 236, + 66, + 0, // Skip to: 25432 + /* 8300 */ MCD_OPC_CheckPredicate, + 22, + 231, + 66, + 0, // Skip to: 25432 + /* 8305 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 224, + 66, + 0, // Skip to: 25432 + /* 8312 */ MCD_OPC_Decode, + 219, + 12, + 145, + 1, // Opcode: MVE_VSHLL_lwu8bh + /* 8317 */ MCD_OPC_FilterValue, + 1, + 214, + 66, + 0, // Skip to: 25432 + /* 8322 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8325 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8347 + /* 8330 */ MCD_OPC_CheckPredicate, + 22, + 201, + 66, + 0, // Skip to: 25432 + /* 8335 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 194, + 66, + 0, // Skip to: 25432 + /* 8342 */ MCD_OPC_Decode, + 216, + 12, + 145, + 1, // Opcode: MVE_VSHLL_lws8th + /* 8347 */ MCD_OPC_FilterValue, + 15, + 184, + 66, + 0, // Skip to: 25432 + /* 8352 */ MCD_OPC_CheckPredicate, + 22, + 179, + 66, + 0, // Skip to: 25432 + /* 8357 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 172, + 66, + 0, // Skip to: 25432 + /* 8364 */ MCD_OPC_Decode, + 220, + 12, + 145, + 1, // Opcode: MVE_VSHLL_lwu8th + /* 8369 */ MCD_OPC_FilterValue, + 1, + 162, + 66, + 0, // Skip to: 25432 + /* 8374 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8377 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8429 + /* 8382 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8385 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8407 + /* 8390 */ MCD_OPC_CheckPredicate, + 22, + 141, + 66, + 0, // Skip to: 25432 + /* 8395 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 134, + 66, + 0, // Skip to: 25432 + /* 8402 */ MCD_OPC_Decode, + 168, + 11, + 146, + 1, // Opcode: MVE_VQMOVUNs16bh + /* 8407 */ MCD_OPC_FilterValue, + 15, + 124, + 66, + 0, // Skip to: 25432 + /* 8412 */ MCD_OPC_CheckPredicate, + 22, + 119, + 66, + 0, // Skip to: 25432 + /* 8417 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 112, + 66, + 0, // Skip to: 25432 + /* 8424 */ MCD_OPC_Decode, + 153, + 10, + 146, + 1, // Opcode: MVE_VMOVNi16bh + /* 8429 */ MCD_OPC_FilterValue, + 1, + 102, + 66, + 0, // Skip to: 25432 + /* 8434 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8437 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8459 + /* 8442 */ MCD_OPC_CheckPredicate, + 22, + 89, + 66, + 0, // Skip to: 25432 + /* 8447 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 82, + 66, + 0, // Skip to: 25432 + /* 8454 */ MCD_OPC_Decode, + 169, + 11, + 146, + 1, // Opcode: MVE_VQMOVUNs16th + /* 8459 */ MCD_OPC_FilterValue, + 15, + 72, + 66, + 0, // Skip to: 25432 + /* 8464 */ MCD_OPC_CheckPredicate, + 22, + 67, + 66, + 0, // Skip to: 25432 + /* 8469 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 60, + 66, + 0, // Skip to: 25432 + /* 8476 */ MCD_OPC_Decode, + 154, + 10, + 146, + 1, // Opcode: MVE_VMOVNi16th + /* 8481 */ MCD_OPC_FilterValue, + 1, + 181, + 0, + 0, // Skip to: 8667 + /* 8486 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 8489 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 8601 + /* 8494 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8497 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8549 + /* 8502 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8505 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8527 + /* 8510 */ MCD_OPC_CheckPredicate, + 22, + 21, + 66, + 0, // Skip to: 25432 + /* 8515 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 14, + 66, + 0, // Skip to: 25432 + /* 8522 */ MCD_OPC_Decode, + 160, + 11, + 146, + 1, // Opcode: MVE_VQMOVNs16bh + /* 8527 */ MCD_OPC_FilterValue, + 15, + 4, + 66, + 0, // Skip to: 25432 + /* 8532 */ MCD_OPC_CheckPredicate, + 22, + 255, + 65, + 0, // Skip to: 25432 + /* 8537 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 248, + 65, + 0, // Skip to: 25432 + /* 8544 */ MCD_OPC_Decode, + 164, + 11, + 146, + 1, // Opcode: MVE_VQMOVNu16bh + /* 8549 */ MCD_OPC_FilterValue, + 1, + 238, + 65, + 0, // Skip to: 25432 + /* 8554 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8557 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8579 + /* 8562 */ MCD_OPC_CheckPredicate, + 22, + 225, + 65, + 0, // Skip to: 25432 + /* 8567 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 218, + 65, + 0, // Skip to: 25432 + /* 8574 */ MCD_OPC_Decode, + 161, + 11, + 146, + 1, // Opcode: MVE_VQMOVNs16th + /* 8579 */ MCD_OPC_FilterValue, + 15, + 208, + 65, + 0, // Skip to: 25432 + /* 8584 */ MCD_OPC_CheckPredicate, + 22, + 203, + 65, + 0, // Skip to: 25432 + /* 8589 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 196, + 65, + 0, // Skip to: 25432 + /* 8596 */ MCD_OPC_Decode, + 165, + 11, + 146, + 1, // Opcode: MVE_VQMOVNu16th + /* 8601 */ MCD_OPC_FilterValue, + 1, + 186, + 65, + 0, // Skip to: 25432 + /* 8606 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8609 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 8638 + /* 8614 */ MCD_OPC_CheckPredicate, + 22, + 173, + 65, + 0, // Skip to: 25432 + /* 8619 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 166, + 65, + 0, // Skip to: 25432 + /* 8626 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 159, + 65, + 0, // Skip to: 25432 + /* 8633 */ MCD_OPC_Decode, + 164, + 9, + 146, + 1, // Opcode: MVE_VMAXAs8 + /* 8638 */ MCD_OPC_FilterValue, + 1, + 149, + 65, + 0, // Skip to: 25432 + /* 8643 */ MCD_OPC_CheckPredicate, + 22, + 144, + 65, + 0, // Skip to: 25432 + /* 8648 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 137, + 65, + 0, // Skip to: 25432 + /* 8655 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 130, + 65, + 0, // Skip to: 25432 + /* 8662 */ MCD_OPC_Decode, + 190, + 9, + 146, + 1, // Opcode: MVE_VMINAs8 + /* 8667 */ MCD_OPC_FilterValue, + 2, + 227, + 0, + 0, // Skip to: 8899 + /* 8672 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 8675 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 8787 + /* 8680 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8683 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8735 + /* 8688 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8691 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8713 + /* 8696 */ MCD_OPC_CheckPredicate, + 22, + 91, + 65, + 0, // Skip to: 25432 + /* 8701 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 84, + 65, + 0, // Skip to: 25432 + /* 8708 */ MCD_OPC_Decode, + 213, + 12, + 145, + 1, // Opcode: MVE_VSHLL_lws16bh + /* 8713 */ MCD_OPC_FilterValue, + 15, + 74, + 65, + 0, // Skip to: 25432 + /* 8718 */ MCD_OPC_CheckPredicate, + 22, + 69, + 65, + 0, // Skip to: 25432 + /* 8723 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 62, + 65, + 0, // Skip to: 25432 + /* 8730 */ MCD_OPC_Decode, + 217, + 12, + 145, + 1, // Opcode: MVE_VSHLL_lwu16bh + /* 8735 */ MCD_OPC_FilterValue, + 1, + 52, + 65, + 0, // Skip to: 25432 + /* 8740 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8743 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8765 + /* 8748 */ MCD_OPC_CheckPredicate, + 22, + 39, + 65, + 0, // Skip to: 25432 + /* 8753 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 32, + 65, + 0, // Skip to: 25432 + /* 8760 */ MCD_OPC_Decode, + 214, + 12, + 145, + 1, // Opcode: MVE_VSHLL_lws16th + /* 8765 */ MCD_OPC_FilterValue, + 15, + 22, + 65, + 0, // Skip to: 25432 + /* 8770 */ MCD_OPC_CheckPredicate, + 22, + 17, + 65, + 0, // Skip to: 25432 + /* 8775 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 10, + 65, + 0, // Skip to: 25432 + /* 8782 */ MCD_OPC_Decode, + 218, + 12, + 145, + 1, // Opcode: MVE_VSHLL_lwu16th + /* 8787 */ MCD_OPC_FilterValue, + 1, + 0, + 65, + 0, // Skip to: 25432 + /* 8792 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8795 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8847 + /* 8800 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8803 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8825 + /* 8808 */ MCD_OPC_CheckPredicate, + 22, + 235, + 64, + 0, // Skip to: 25432 + /* 8813 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 228, + 64, + 0, // Skip to: 25432 + /* 8820 */ MCD_OPC_Decode, + 170, + 11, + 146, + 1, // Opcode: MVE_VQMOVUNs32bh + /* 8825 */ MCD_OPC_FilterValue, + 15, + 218, + 64, + 0, // Skip to: 25432 + /* 8830 */ MCD_OPC_CheckPredicate, + 22, + 213, + 64, + 0, // Skip to: 25432 + /* 8835 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 206, + 64, + 0, // Skip to: 25432 + /* 8842 */ MCD_OPC_Decode, + 155, + 10, + 146, + 1, // Opcode: MVE_VMOVNi32bh + /* 8847 */ MCD_OPC_FilterValue, + 1, + 196, + 64, + 0, // Skip to: 25432 + /* 8852 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8855 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8877 + /* 8860 */ MCD_OPC_CheckPredicate, + 22, + 183, + 64, + 0, // Skip to: 25432 + /* 8865 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 176, + 64, + 0, // Skip to: 25432 + /* 8872 */ MCD_OPC_Decode, + 171, + 11, + 146, + 1, // Opcode: MVE_VQMOVUNs32th + /* 8877 */ MCD_OPC_FilterValue, + 15, + 166, + 64, + 0, // Skip to: 25432 + /* 8882 */ MCD_OPC_CheckPredicate, + 22, + 161, + 64, + 0, // Skip to: 25432 + /* 8887 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 154, + 64, + 0, // Skip to: 25432 + /* 8894 */ MCD_OPC_Decode, + 156, + 10, + 146, + 1, // Opcode: MVE_VMOVNi32th + /* 8899 */ MCD_OPC_FilterValue, + 3, + 181, + 0, + 0, // Skip to: 9085 + /* 8904 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 8907 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 9019 + /* 8912 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 8915 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 8967 + /* 8920 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8923 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8945 + /* 8928 */ MCD_OPC_CheckPredicate, + 22, + 115, + 64, + 0, // Skip to: 25432 + /* 8933 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 108, + 64, + 0, // Skip to: 25432 + /* 8940 */ MCD_OPC_Decode, + 162, + 11, + 146, + 1, // Opcode: MVE_VQMOVNs32bh + /* 8945 */ MCD_OPC_FilterValue, + 15, + 98, + 64, + 0, // Skip to: 25432 + /* 8950 */ MCD_OPC_CheckPredicate, + 22, + 93, + 64, + 0, // Skip to: 25432 + /* 8955 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 86, + 64, + 0, // Skip to: 25432 + /* 8962 */ MCD_OPC_Decode, + 166, + 11, + 146, + 1, // Opcode: MVE_VQMOVNu32bh + /* 8967 */ MCD_OPC_FilterValue, + 1, + 76, + 64, + 0, // Skip to: 25432 + /* 8972 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 8975 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 8997 + /* 8980 */ MCD_OPC_CheckPredicate, + 22, + 63, + 64, + 0, // Skip to: 25432 + /* 8985 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 56, + 64, + 0, // Skip to: 25432 + /* 8992 */ MCD_OPC_Decode, + 163, + 11, + 146, + 1, // Opcode: MVE_VQMOVNs32th + /* 8997 */ MCD_OPC_FilterValue, + 15, + 46, + 64, + 0, // Skip to: 25432 + /* 9002 */ MCD_OPC_CheckPredicate, + 22, + 41, + 64, + 0, // Skip to: 25432 + /* 9007 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 34, + 64, + 0, // Skip to: 25432 + /* 9014 */ MCD_OPC_Decode, + 167, + 11, + 146, + 1, // Opcode: MVE_VQMOVNu32th + /* 9019 */ MCD_OPC_FilterValue, + 1, + 24, + 64, + 0, // Skip to: 25432 + /* 9024 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9027 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 9056 + /* 9032 */ MCD_OPC_CheckPredicate, + 22, + 11, + 64, + 0, // Skip to: 25432 + /* 9037 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 4, + 64, + 0, // Skip to: 25432 + /* 9044 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 253, + 63, + 0, // Skip to: 25432 + /* 9051 */ MCD_OPC_Decode, + 162, + 9, + 146, + 1, // Opcode: MVE_VMAXAs16 + /* 9056 */ MCD_OPC_FilterValue, + 1, + 243, + 63, + 0, // Skip to: 25432 + /* 9061 */ MCD_OPC_CheckPredicate, + 22, + 238, + 63, + 0, // Skip to: 25432 + /* 9066 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 231, + 63, + 0, // Skip to: 25432 + /* 9073 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 224, + 63, + 0, // Skip to: 25432 + /* 9080 */ MCD_OPC_Decode, + 188, + 9, + 146, + 1, // Opcode: MVE_VMINAs16 + /* 9085 */ MCD_OPC_FilterValue, + 5, + 75, + 0, + 0, // Skip to: 9165 + /* 9090 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9093 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 9129 + /* 9098 */ MCD_OPC_CheckPredicate, + 22, + 201, + 63, + 0, // Skip to: 25432 + /* 9103 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 194, + 63, + 0, // Skip to: 25432 + /* 9110 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 187, + 63, + 0, // Skip to: 25432 + /* 9117 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 180, + 63, + 0, // Skip to: 25432 + /* 9124 */ MCD_OPC_Decode, + 163, + 9, + 146, + 1, // Opcode: MVE_VMAXAs32 + /* 9129 */ MCD_OPC_FilterValue, + 1, + 170, + 63, + 0, // Skip to: 25432 + /* 9134 */ MCD_OPC_CheckPredicate, + 22, + 165, + 63, + 0, // Skip to: 25432 + /* 9139 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 158, + 63, + 0, // Skip to: 25432 + /* 9146 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 151, + 63, + 0, // Skip to: 25432 + /* 9153 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 144, + 63, + 0, // Skip to: 25432 + /* 9160 */ MCD_OPC_Decode, + 189, + 9, + 146, + 1, // Opcode: MVE_VMINAs32 + /* 9165 */ MCD_OPC_FilterValue, + 7, + 134, + 63, + 0, // Skip to: 25432 + /* 9170 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9173 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 9285 + /* 9178 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9181 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 9233 + /* 9186 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9189 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9211 + /* 9194 */ MCD_OPC_CheckPredicate, + 24, + 105, + 63, + 0, // Skip to: 25432 + /* 9199 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 98, + 63, + 0, // Skip to: 25432 + /* 9206 */ MCD_OPC_Decode, + 246, + 7, + 146, + 1, // Opcode: MVE_VCVTf16f32bh + /* 9211 */ MCD_OPC_FilterValue, + 15, + 88, + 63, + 0, // Skip to: 25432 + /* 9216 */ MCD_OPC_CheckPredicate, + 24, + 83, + 63, + 0, // Skip to: 25432 + /* 9221 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 76, + 63, + 0, // Skip to: 25432 + /* 9228 */ MCD_OPC_Decode, + 252, + 7, + 145, + 1, // Opcode: MVE_VCVTf32f16bh + /* 9233 */ MCD_OPC_FilterValue, + 1, + 66, + 63, + 0, // Skip to: 25432 + /* 9238 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9241 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9263 + /* 9246 */ MCD_OPC_CheckPredicate, + 24, + 53, + 63, + 0, // Skip to: 25432 + /* 9251 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 46, + 63, + 0, // Skip to: 25432 + /* 9258 */ MCD_OPC_Decode, + 247, + 7, + 146, + 1, // Opcode: MVE_VCVTf16f32th + /* 9263 */ MCD_OPC_FilterValue, + 15, + 36, + 63, + 0, // Skip to: 25432 + /* 9268 */ MCD_OPC_CheckPredicate, + 24, + 31, + 63, + 0, // Skip to: 25432 + /* 9273 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 24, + 63, + 0, // Skip to: 25432 + /* 9280 */ MCD_OPC_Decode, + 253, + 7, + 145, + 1, // Opcode: MVE_VCVTf32f16th + /* 9285 */ MCD_OPC_FilterValue, + 1, + 14, + 63, + 0, // Skip to: 25432 + /* 9290 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9293 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 9345 + /* 9298 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9301 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9323 + /* 9306 */ MCD_OPC_CheckPredicate, + 24, + 249, + 62, + 0, // Skip to: 25432 + /* 9311 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 242, + 62, + 0, // Skip to: 25432 + /* 9318 */ MCD_OPC_Decode, + 168, + 9, + 146, + 1, // Opcode: MVE_VMAXNMAf32 + /* 9323 */ MCD_OPC_FilterValue, + 15, + 232, + 62, + 0, // Skip to: 25432 + /* 9328 */ MCD_OPC_CheckPredicate, + 24, + 227, + 62, + 0, // Skip to: 25432 + /* 9333 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 220, + 62, + 0, // Skip to: 25432 + /* 9340 */ MCD_OPC_Decode, + 167, + 9, + 146, + 1, // Opcode: MVE_VMAXNMAf16 + /* 9345 */ MCD_OPC_FilterValue, + 1, + 210, + 62, + 0, // Skip to: 25432 + /* 9350 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9353 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9375 + /* 9358 */ MCD_OPC_CheckPredicate, + 24, + 197, + 62, + 0, // Skip to: 25432 + /* 9363 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 190, + 62, + 0, // Skip to: 25432 + /* 9370 */ MCD_OPC_Decode, + 194, + 9, + 146, + 1, // Opcode: MVE_VMINNMAf32 + /* 9375 */ MCD_OPC_FilterValue, + 15, + 180, + 62, + 0, // Skip to: 25432 + /* 9380 */ MCD_OPC_CheckPredicate, + 24, + 175, + 62, + 0, // Skip to: 25432 + /* 9385 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 168, + 62, + 0, // Skip to: 25432 + /* 9392 */ MCD_OPC_Decode, + 193, + 9, + 146, + 1, // Opcode: MVE_VMINNMAf16 + /* 9397 */ MCD_OPC_FilterValue, + 1, + 158, + 62, + 0, // Skip to: 25432 + /* 9402 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 9405 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 9517 + /* 9410 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9413 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 9465 + /* 9418 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9421 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9443 + /* 9426 */ MCD_OPC_CheckPredicate, + 24, + 129, + 62, + 0, // Skip to: 25432 + /* 9431 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 122, + 62, + 0, // Skip to: 25432 + /* 9438 */ MCD_OPC_Decode, + 167, + 8, + 142, + 1, // Opcode: MVE_VFMA_qr_f32 + /* 9443 */ MCD_OPC_FilterValue, + 15, + 112, + 62, + 0, // Skip to: 25432 + /* 9448 */ MCD_OPC_CheckPredicate, + 24, + 107, + 62, + 0, // Skip to: 25432 + /* 9453 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 100, + 62, + 0, // Skip to: 25432 + /* 9460 */ MCD_OPC_Decode, + 166, + 8, + 142, + 1, // Opcode: MVE_VFMA_qr_f16 + /* 9465 */ MCD_OPC_FilterValue, + 1, + 90, + 62, + 0, // Skip to: 25432 + /* 9470 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9473 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9495 + /* 9478 */ MCD_OPC_CheckPredicate, + 24, + 77, + 62, + 0, // Skip to: 25432 + /* 9483 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 70, + 62, + 0, // Skip to: 25432 + /* 9490 */ MCD_OPC_Decode, + 165, + 8, + 142, + 1, // Opcode: MVE_VFMA_qr_Sf32 + /* 9495 */ MCD_OPC_FilterValue, + 15, + 60, + 62, + 0, // Skip to: 25432 + /* 9500 */ MCD_OPC_CheckPredicate, + 24, + 55, + 62, + 0, // Skip to: 25432 + /* 9505 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 48, + 62, + 0, // Skip to: 25432 + /* 9512 */ MCD_OPC_Decode, + 164, + 8, + 142, + 1, // Opcode: MVE_VFMA_qr_Sf16 + /* 9517 */ MCD_OPC_FilterValue, + 2, + 38, + 62, + 0, // Skip to: 25432 + /* 9522 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 9525 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 9577 + /* 9530 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9533 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 9555 + /* 9538 */ MCD_OPC_CheckPredicate, + 24, + 17, + 62, + 0, // Skip to: 25432 + /* 9543 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 10, + 62, + 0, // Skip to: 25432 + /* 9550 */ MCD_OPC_Decode, + 195, + 10, + 143, + 1, // Opcode: MVE_VMUL_qr_f32 + /* 9555 */ MCD_OPC_FilterValue, + 15, + 0, + 62, + 0, // Skip to: 25432 + /* 9560 */ MCD_OPC_CheckPredicate, + 24, + 251, + 61, + 0, // Skip to: 25432 + /* 9565 */ MCD_OPC_CheckField, + 16, + 1, + 1, + 244, + 61, + 0, // Skip to: 25432 + /* 9572 */ MCD_OPC_Decode, + 194, + 10, + 143, + 1, // Opcode: MVE_VMUL_qr_f16 + /* 9577 */ MCD_OPC_FilterValue, + 1, + 234, + 61, + 0, // Skip to: 25432 + /* 9582 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9585 */ MCD_OPC_FilterValue, + 1, + 79, + 0, + 0, // Skip to: 9669 + /* 9590 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9593 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9631 + /* 9598 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9601 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9616 + /* 9606 */ MCD_OPC_CheckPredicate, + 22, + 205, + 61, + 0, // Skip to: 25432 + /* 9611 */ MCD_OPC_Decode, + 232, + 12, + 147, + 1, // Opcode: MVE_VSHL_qrs8 + /* 9616 */ MCD_OPC_FilterValue, + 15, + 195, + 61, + 0, // Skip to: 25432 + /* 9621 */ MCD_OPC_CheckPredicate, + 22, + 190, + 61, + 0, // Skip to: 25432 + /* 9626 */ MCD_OPC_Decode, + 235, + 12, + 147, + 1, // Opcode: MVE_VSHL_qru8 + /* 9631 */ MCD_OPC_FilterValue, + 1, + 180, + 61, + 0, // Skip to: 25432 + /* 9636 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9639 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9654 + /* 9644 */ MCD_OPC_CheckPredicate, + 22, + 167, + 61, + 0, // Skip to: 25432 + /* 9649 */ MCD_OPC_Decode, + 234, + 11, + 147, + 1, // Opcode: MVE_VQSHL_qrs8 + /* 9654 */ MCD_OPC_FilterValue, + 15, + 157, + 61, + 0, // Skip to: 25432 + /* 9659 */ MCD_OPC_CheckPredicate, + 22, + 152, + 61, + 0, // Skip to: 25432 + /* 9664 */ MCD_OPC_Decode, + 237, + 11, + 147, + 1, // Opcode: MVE_VQSHL_qru8 + /* 9669 */ MCD_OPC_FilterValue, + 3, + 79, + 0, + 0, // Skip to: 9753 + /* 9674 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9677 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9715 + /* 9682 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9685 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9700 + /* 9690 */ MCD_OPC_CheckPredicate, + 22, + 121, + 61, + 0, // Skip to: 25432 + /* 9695 */ MCD_OPC_Decode, + 188, + 12, + 147, + 1, // Opcode: MVE_VRSHL_qrs8 + /* 9700 */ MCD_OPC_FilterValue, + 15, + 111, + 61, + 0, // Skip to: 25432 + /* 9705 */ MCD_OPC_CheckPredicate, + 22, + 106, + 61, + 0, // Skip to: 25432 + /* 9710 */ MCD_OPC_Decode, + 191, + 12, + 147, + 1, // Opcode: MVE_VRSHL_qru8 + /* 9715 */ MCD_OPC_FilterValue, + 1, + 96, + 61, + 0, // Skip to: 25432 + /* 9720 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9723 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9738 + /* 9728 */ MCD_OPC_CheckPredicate, + 22, + 83, + 61, + 0, // Skip to: 25432 + /* 9733 */ MCD_OPC_Decode, + 207, + 11, + 147, + 1, // Opcode: MVE_VQRSHL_qrs8 + /* 9738 */ MCD_OPC_FilterValue, + 15, + 73, + 61, + 0, // Skip to: 25432 + /* 9743 */ MCD_OPC_CheckPredicate, + 22, + 68, + 61, + 0, // Skip to: 25432 + /* 9748 */ MCD_OPC_Decode, + 210, + 11, + 147, + 1, // Opcode: MVE_VQRSHL_qru8 + /* 9753 */ MCD_OPC_FilterValue, + 5, + 79, + 0, + 0, // Skip to: 9837 + /* 9758 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9761 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9799 + /* 9766 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9769 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9784 + /* 9774 */ MCD_OPC_CheckPredicate, + 22, + 37, + 61, + 0, // Skip to: 25432 + /* 9779 */ MCD_OPC_Decode, + 230, + 12, + 147, + 1, // Opcode: MVE_VSHL_qrs16 + /* 9784 */ MCD_OPC_FilterValue, + 15, + 27, + 61, + 0, // Skip to: 25432 + /* 9789 */ MCD_OPC_CheckPredicate, + 22, + 22, + 61, + 0, // Skip to: 25432 + /* 9794 */ MCD_OPC_Decode, + 233, + 12, + 147, + 1, // Opcode: MVE_VSHL_qru16 + /* 9799 */ MCD_OPC_FilterValue, + 1, + 12, + 61, + 0, // Skip to: 25432 + /* 9804 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9807 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9822 + /* 9812 */ MCD_OPC_CheckPredicate, + 22, + 255, + 60, + 0, // Skip to: 25432 + /* 9817 */ MCD_OPC_Decode, + 232, + 11, + 147, + 1, // Opcode: MVE_VQSHL_qrs16 + /* 9822 */ MCD_OPC_FilterValue, + 15, + 245, + 60, + 0, // Skip to: 25432 + /* 9827 */ MCD_OPC_CheckPredicate, + 22, + 240, + 60, + 0, // Skip to: 25432 + /* 9832 */ MCD_OPC_Decode, + 235, + 11, + 147, + 1, // Opcode: MVE_VQSHL_qru16 + /* 9837 */ MCD_OPC_FilterValue, + 7, + 79, + 0, + 0, // Skip to: 9921 + /* 9842 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9845 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9883 + /* 9850 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9853 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9868 + /* 9858 */ MCD_OPC_CheckPredicate, + 22, + 209, + 60, + 0, // Skip to: 25432 + /* 9863 */ MCD_OPC_Decode, + 186, + 12, + 147, + 1, // Opcode: MVE_VRSHL_qrs16 + /* 9868 */ MCD_OPC_FilterValue, + 15, + 199, + 60, + 0, // Skip to: 25432 + /* 9873 */ MCD_OPC_CheckPredicate, + 22, + 194, + 60, + 0, // Skip to: 25432 + /* 9878 */ MCD_OPC_Decode, + 189, + 12, + 147, + 1, // Opcode: MVE_VRSHL_qru16 + /* 9883 */ MCD_OPC_FilterValue, + 1, + 184, + 60, + 0, // Skip to: 25432 + /* 9888 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9891 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9906 + /* 9896 */ MCD_OPC_CheckPredicate, + 22, + 171, + 60, + 0, // Skip to: 25432 + /* 9901 */ MCD_OPC_Decode, + 205, + 11, + 147, + 1, // Opcode: MVE_VQRSHL_qrs16 + /* 9906 */ MCD_OPC_FilterValue, + 15, + 161, + 60, + 0, // Skip to: 25432 + /* 9911 */ MCD_OPC_CheckPredicate, + 22, + 156, + 60, + 0, // Skip to: 25432 + /* 9916 */ MCD_OPC_Decode, + 208, + 11, + 147, + 1, // Opcode: MVE_VQRSHL_qru16 + /* 9921 */ MCD_OPC_FilterValue, + 9, + 79, + 0, + 0, // Skip to: 10005 + /* 9926 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 9929 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 9967 + /* 9934 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9937 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9952 + /* 9942 */ MCD_OPC_CheckPredicate, + 22, + 125, + 60, + 0, // Skip to: 25432 + /* 9947 */ MCD_OPC_Decode, + 231, + 12, + 147, + 1, // Opcode: MVE_VSHL_qrs32 + /* 9952 */ MCD_OPC_FilterValue, + 15, + 115, + 60, + 0, // Skip to: 25432 + /* 9957 */ MCD_OPC_CheckPredicate, + 22, + 110, + 60, + 0, // Skip to: 25432 + /* 9962 */ MCD_OPC_Decode, + 234, + 12, + 147, + 1, // Opcode: MVE_VSHL_qru32 + /* 9967 */ MCD_OPC_FilterValue, + 1, + 100, + 60, + 0, // Skip to: 25432 + /* 9972 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 9975 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9990 + /* 9980 */ MCD_OPC_CheckPredicate, + 22, + 87, + 60, + 0, // Skip to: 25432 + /* 9985 */ MCD_OPC_Decode, + 233, + 11, + 147, + 1, // Opcode: MVE_VQSHL_qrs32 + /* 9990 */ MCD_OPC_FilterValue, + 15, + 77, + 60, + 0, // Skip to: 25432 + /* 9995 */ MCD_OPC_CheckPredicate, + 22, + 72, + 60, + 0, // Skip to: 25432 + /* 10000 */ MCD_OPC_Decode, + 236, + 11, + 147, + 1, // Opcode: MVE_VQSHL_qru32 + /* 10005 */ MCD_OPC_FilterValue, + 11, + 62, + 60, + 0, // Skip to: 25432 + /* 10010 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 10013 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 10051 + /* 10018 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10021 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10036 + /* 10026 */ MCD_OPC_CheckPredicate, + 22, + 41, + 60, + 0, // Skip to: 25432 + /* 10031 */ MCD_OPC_Decode, + 187, + 12, + 147, + 1, // Opcode: MVE_VRSHL_qrs32 + /* 10036 */ MCD_OPC_FilterValue, + 15, + 31, + 60, + 0, // Skip to: 25432 + /* 10041 */ MCD_OPC_CheckPredicate, + 22, + 26, + 60, + 0, // Skip to: 25432 + /* 10046 */ MCD_OPC_Decode, + 190, + 12, + 147, + 1, // Opcode: MVE_VRSHL_qru32 + /* 10051 */ MCD_OPC_FilterValue, + 1, + 16, + 60, + 0, // Skip to: 25432 + /* 10056 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10059 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10074 + /* 10064 */ MCD_OPC_CheckPredicate, + 22, + 3, + 60, + 0, // Skip to: 25432 + /* 10069 */ MCD_OPC_Decode, + 206, + 11, + 147, + 1, // Opcode: MVE_VQRSHL_qrs32 + /* 10074 */ MCD_OPC_FilterValue, + 15, + 249, + 59, + 0, // Skip to: 25432 + /* 10079 */ MCD_OPC_CheckPredicate, + 22, + 244, + 59, + 0, // Skip to: 25432 + /* 10084 */ MCD_OPC_Decode, + 209, + 11, + 147, + 1, // Opcode: MVE_VQRSHL_qru32 + /* 10089 */ MCD_OPC_FilterValue, + 15, + 234, + 59, + 0, // Skip to: 25432 + /* 10094 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 10097 */ MCD_OPC_FilterValue, + 0, + 197, + 2, + 0, // Skip to: 10811 + /* 10102 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10105 */ MCD_OPC_FilterValue, + 0, + 250, + 0, + 0, // Skip to: 10360 + /* 10110 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10113 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 10179 + /* 10118 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10121 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 10150 + /* 10126 */ MCD_OPC_CheckPredicate, + 22, + 197, + 59, + 0, // Skip to: 25432 + /* 10131 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 190, + 59, + 0, // Skip to: 25432 + /* 10138 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 183, + 59, + 0, // Skip to: 25432 + /* 10145 */ MCD_OPC_Decode, + 186, + 8, + 148, + 1, // Opcode: MVE_VHCADDs8 + /* 10150 */ MCD_OPC_FilterValue, + 15, + 173, + 59, + 0, // Skip to: 25432 + /* 10155 */ MCD_OPC_CheckPredicate, + 22, + 168, + 59, + 0, // Skip to: 25432 + /* 10160 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 161, + 59, + 0, // Skip to: 25432 + /* 10167 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 154, + 59, + 0, // Skip to: 25432 + /* 10174 */ MCD_OPC_Decode, + 209, + 7, + 148, + 1, // Opcode: MVE_VCADDi8 + /* 10179 */ MCD_OPC_FilterValue, + 1, + 144, + 59, + 0, // Skip to: 25432 + /* 10184 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 10187 */ MCD_OPC_FilterValue, + 0, + 113, + 0, + 0, // Skip to: 10305 + /* 10192 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 10195 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 10250 + /* 10200 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10203 */ MCD_OPC_FilterValue, + 0, + 120, + 59, + 0, // Skip to: 25432 + /* 10208 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10211 */ MCD_OPC_FilterValue, + 15, + 112, + 59, + 0, // Skip to: 25432 + /* 10216 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10240 + /* 10221 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10240 + /* 10228 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10240 + /* 10235 */ MCD_OPC_Decode, + 226, + 7, + 149, + 1, // Opcode: MVE_VCMPi8 + /* 10240 */ MCD_OPC_CheckPredicate, + 22, + 83, + 59, + 0, // Skip to: 25432 + /* 10245 */ MCD_OPC_Decode, + 219, + 10, + 150, + 1, // Opcode: MVE_VPTv16i8 + /* 10250 */ MCD_OPC_FilterValue, + 1, + 73, + 59, + 0, // Skip to: 25432 + /* 10255 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10258 */ MCD_OPC_FilterValue, + 0, + 65, + 59, + 0, // Skip to: 25432 + /* 10263 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10266 */ MCD_OPC_FilterValue, + 15, + 57, + 59, + 0, // Skip to: 25432 + /* 10271 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10295 + /* 10276 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10295 + /* 10283 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10295 + /* 10290 */ MCD_OPC_Decode, + 238, + 7, + 151, + 1, // Opcode: MVE_VCMPu8 + /* 10295 */ MCD_OPC_CheckPredicate, + 22, + 28, + 59, + 0, // Skip to: 25432 + /* 10300 */ MCD_OPC_Decode, + 223, + 10, + 152, + 1, // Opcode: MVE_VPTv16u8 + /* 10305 */ MCD_OPC_FilterValue, + 1, + 18, + 59, + 0, // Skip to: 25432 + /* 10310 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10313 */ MCD_OPC_FilterValue, + 0, + 10, + 59, + 0, // Skip to: 25432 + /* 10318 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10321 */ MCD_OPC_FilterValue, + 15, + 2, + 59, + 0, // Skip to: 25432 + /* 10326 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10350 + /* 10331 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10350 + /* 10338 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10350 + /* 10345 */ MCD_OPC_Decode, + 232, + 7, + 153, + 1, // Opcode: MVE_VCMPs8 + /* 10350 */ MCD_OPC_CheckPredicate, + 22, + 229, + 58, + 0, // Skip to: 25432 + /* 10355 */ MCD_OPC_Decode, + 221, + 10, + 154, + 1, // Opcode: MVE_VPTv16s8 + /* 10360 */ MCD_OPC_FilterValue, + 1, + 219, + 58, + 0, // Skip to: 25432 + /* 10365 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 10368 */ MCD_OPC_FilterValue, + 0, + 236, + 0, + 0, // Skip to: 10609 + /* 10373 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 10376 */ MCD_OPC_FilterValue, + 0, + 103, + 0, + 0, // Skip to: 10484 + /* 10381 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10384 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 10422 + /* 10389 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10392 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10407 + /* 10397 */ MCD_OPC_CheckPredicate, + 22, + 182, + 58, + 0, // Skip to: 25432 + /* 10402 */ MCD_OPC_Decode, + 174, + 8, + 143, + 1, // Opcode: MVE_VHADD_qr_s8 + /* 10407 */ MCD_OPC_FilterValue, + 15, + 172, + 58, + 0, // Skip to: 25432 + /* 10412 */ MCD_OPC_CheckPredicate, + 22, + 167, + 58, + 0, // Skip to: 25432 + /* 10417 */ MCD_OPC_Decode, + 177, + 8, + 143, + 1, // Opcode: MVE_VHADD_qr_u8 + /* 10422 */ MCD_OPC_FilterValue, + 1, + 157, + 58, + 0, // Skip to: 25432 + /* 10427 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10430 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10445 + /* 10435 */ MCD_OPC_CheckPredicate, + 22, + 144, + 58, + 0, // Skip to: 25432 + /* 10440 */ MCD_OPC_Decode, + 192, + 7, + 143, + 1, // Opcode: MVE_VADD_qr_i8 + /* 10445 */ MCD_OPC_FilterValue, + 15, + 134, + 58, + 0, // Skip to: 25432 + /* 10450 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10474 + /* 10455 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10474 + /* 10462 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10474 + /* 10469 */ MCD_OPC_Decode, + 227, + 7, + 155, + 1, // Opcode: MVE_VCMPi8r + /* 10474 */ MCD_OPC_CheckPredicate, + 22, + 105, + 58, + 0, // Skip to: 25432 + /* 10479 */ MCD_OPC_Decode, + 220, + 10, + 156, + 1, // Opcode: MVE_VPTv16i8r + /* 10484 */ MCD_OPC_FilterValue, + 2, + 95, + 58, + 0, // Skip to: 25432 + /* 10489 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10492 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 10530 + /* 10497 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10500 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10515 + /* 10505 */ MCD_OPC_CheckPredicate, + 22, + 74, + 58, + 0, // Skip to: 25432 + /* 10510 */ MCD_OPC_Decode, + 246, + 10, + 143, + 1, // Opcode: MVE_VQADD_qr_s8 + /* 10515 */ MCD_OPC_FilterValue, + 15, + 64, + 58, + 0, // Skip to: 25432 + /* 10520 */ MCD_OPC_CheckPredicate, + 22, + 59, + 58, + 0, // Skip to: 25432 + /* 10525 */ MCD_OPC_Decode, + 249, + 10, + 143, + 1, // Opcode: MVE_VQADD_qr_u8 + /* 10530 */ MCD_OPC_FilterValue, + 1, + 49, + 58, + 0, // Skip to: 25432 + /* 10535 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10538 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 10570 + /* 10543 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 10560 + /* 10548 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 10560 + /* 10555 */ MCD_OPC_Decode, + 201, + 8, + 157, + 1, // Opcode: MVE_VIDUPu8 + /* 10560 */ MCD_OPC_CheckPredicate, + 22, + 19, + 58, + 0, // Skip to: 25432 + /* 10565 */ MCD_OPC_Decode, + 204, + 8, + 158, + 1, // Opcode: MVE_VIWDUPu8 + /* 10570 */ MCD_OPC_FilterValue, + 15, + 9, + 58, + 0, // Skip to: 25432 + /* 10575 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10599 + /* 10580 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10599 + /* 10587 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10599 + /* 10594 */ MCD_OPC_Decode, + 239, + 7, + 159, + 1, // Opcode: MVE_VCMPu8r + /* 10599 */ MCD_OPC_CheckPredicate, + 22, + 236, + 57, + 0, // Skip to: 25432 + /* 10604 */ MCD_OPC_Decode, + 224, + 10, + 160, + 1, // Opcode: MVE_VPTv16u8r + /* 10609 */ MCD_OPC_FilterValue, + 1, + 226, + 57, + 0, // Skip to: 25432 + /* 10614 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10617 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 10701 + /* 10622 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 10625 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 10663 + /* 10630 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10633 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10648 + /* 10638 */ MCD_OPC_CheckPredicate, + 22, + 197, + 57, + 0, // Skip to: 25432 + /* 10643 */ MCD_OPC_Decode, + 189, + 8, + 143, + 1, // Opcode: MVE_VHSUB_qr_s8 + /* 10648 */ MCD_OPC_FilterValue, + 15, + 187, + 57, + 0, // Skip to: 25432 + /* 10653 */ MCD_OPC_CheckPredicate, + 22, + 182, + 57, + 0, // Skip to: 25432 + /* 10658 */ MCD_OPC_Decode, + 192, + 8, + 143, + 1, // Opcode: MVE_VHSUB_qr_u8 + /* 10663 */ MCD_OPC_FilterValue, + 2, + 172, + 57, + 0, // Skip to: 25432 + /* 10668 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10671 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10686 + /* 10676 */ MCD_OPC_CheckPredicate, + 22, + 159, + 57, + 0, // Skip to: 25432 + /* 10681 */ MCD_OPC_Decode, + 130, + 12, + 143, + 1, // Opcode: MVE_VQSUB_qr_s8 + /* 10686 */ MCD_OPC_FilterValue, + 15, + 149, + 57, + 0, // Skip to: 25432 + /* 10691 */ MCD_OPC_CheckPredicate, + 22, + 144, + 57, + 0, // Skip to: 25432 + /* 10696 */ MCD_OPC_Decode, + 133, + 12, + 143, + 1, // Opcode: MVE_VQSUB_qr_u8 + /* 10701 */ MCD_OPC_FilterValue, + 1, + 134, + 57, + 0, // Skip to: 25432 + /* 10706 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10709 */ MCD_OPC_FilterValue, + 14, + 50, + 0, + 0, // Skip to: 10764 + /* 10714 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 10717 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10732 + /* 10722 */ MCD_OPC_CheckPredicate, + 22, + 113, + 57, + 0, // Skip to: 25432 + /* 10727 */ MCD_OPC_Decode, + 197, + 13, + 143, + 1, // Opcode: MVE_VSUB_qr_i8 + /* 10732 */ MCD_OPC_FilterValue, + 2, + 103, + 57, + 0, // Skip to: 25432 + /* 10737 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 10754 + /* 10742 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 10754 + /* 10749 */ MCD_OPC_Decode, + 156, + 8, + 157, + 1, // Opcode: MVE_VDDUPu8 + /* 10754 */ MCD_OPC_CheckPredicate, + 22, + 81, + 57, + 0, // Skip to: 25432 + /* 10759 */ MCD_OPC_Decode, + 162, + 8, + 158, + 1, // Opcode: MVE_VDWDUPu8 + /* 10764 */ MCD_OPC_FilterValue, + 15, + 71, + 57, + 0, // Skip to: 25432 + /* 10769 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10772 */ MCD_OPC_FilterValue, + 0, + 63, + 57, + 0, // Skip to: 25432 + /* 10777 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10801 + /* 10782 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10801 + /* 10789 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10801 + /* 10796 */ MCD_OPC_Decode, + 233, + 7, + 161, + 1, // Opcode: MVE_VCMPs8r + /* 10801 */ MCD_OPC_CheckPredicate, + 22, + 34, + 57, + 0, // Skip to: 25432 + /* 10806 */ MCD_OPC_Decode, + 222, + 10, + 162, + 1, // Opcode: MVE_VPTv16s8r + /* 10811 */ MCD_OPC_FilterValue, + 1, + 197, + 2, + 0, // Skip to: 11525 + /* 10816 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10819 */ MCD_OPC_FilterValue, + 0, + 250, + 0, + 0, // Skip to: 11074 + /* 10824 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10827 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 10893 + /* 10832 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10835 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 10864 + /* 10840 */ MCD_OPC_CheckPredicate, + 22, + 251, + 56, + 0, // Skip to: 25432 + /* 10845 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 56, + 0, // Skip to: 25432 + /* 10852 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 237, + 56, + 0, // Skip to: 25432 + /* 10859 */ MCD_OPC_Decode, + 184, + 8, + 148, + 1, // Opcode: MVE_VHCADDs16 + /* 10864 */ MCD_OPC_FilterValue, + 15, + 227, + 56, + 0, // Skip to: 25432 + /* 10869 */ MCD_OPC_CheckPredicate, + 22, + 222, + 56, + 0, // Skip to: 25432 + /* 10874 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 215, + 56, + 0, // Skip to: 25432 + /* 10881 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 208, + 56, + 0, // Skip to: 25432 + /* 10888 */ MCD_OPC_Decode, + 207, + 7, + 148, + 1, // Opcode: MVE_VCADDi16 + /* 10893 */ MCD_OPC_FilterValue, + 1, + 198, + 56, + 0, // Skip to: 25432 + /* 10898 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 10901 */ MCD_OPC_FilterValue, + 0, + 113, + 0, + 0, // Skip to: 11019 + /* 10906 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 10909 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 10964 + /* 10914 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10917 */ MCD_OPC_FilterValue, + 0, + 174, + 56, + 0, // Skip to: 25432 + /* 10922 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10925 */ MCD_OPC_FilterValue, + 15, + 166, + 56, + 0, // Skip to: 25432 + /* 10930 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 10954 + /* 10935 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 10954 + /* 10942 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 10954 + /* 10949 */ MCD_OPC_Decode, + 222, + 7, + 149, + 1, // Opcode: MVE_VCMPi16 + /* 10954 */ MCD_OPC_CheckPredicate, + 22, + 137, + 56, + 0, // Skip to: 25432 + /* 10959 */ MCD_OPC_Decode, + 235, + 10, + 150, + 1, // Opcode: MVE_VPTv8i16 + /* 10964 */ MCD_OPC_FilterValue, + 1, + 127, + 56, + 0, // Skip to: 25432 + /* 10969 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 10972 */ MCD_OPC_FilterValue, + 0, + 119, + 56, + 0, // Skip to: 25432 + /* 10977 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 10980 */ MCD_OPC_FilterValue, + 15, + 111, + 56, + 0, // Skip to: 25432 + /* 10985 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11009 + /* 10990 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11009 + /* 10997 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11009 + /* 11004 */ MCD_OPC_Decode, + 234, + 7, + 151, + 1, // Opcode: MVE_VCMPu16 + /* 11009 */ MCD_OPC_CheckPredicate, + 22, + 82, + 56, + 0, // Skip to: 25432 + /* 11014 */ MCD_OPC_Decode, + 239, + 10, + 152, + 1, // Opcode: MVE_VPTv8u16 + /* 11019 */ MCD_OPC_FilterValue, + 1, + 72, + 56, + 0, // Skip to: 25432 + /* 11024 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11027 */ MCD_OPC_FilterValue, + 0, + 64, + 56, + 0, // Skip to: 25432 + /* 11032 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11035 */ MCD_OPC_FilterValue, + 15, + 56, + 56, + 0, // Skip to: 25432 + /* 11040 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11064 + /* 11045 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11064 + /* 11052 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11064 + /* 11059 */ MCD_OPC_Decode, + 228, + 7, + 153, + 1, // Opcode: MVE_VCMPs16 + /* 11064 */ MCD_OPC_CheckPredicate, + 22, + 27, + 56, + 0, // Skip to: 25432 + /* 11069 */ MCD_OPC_Decode, + 237, + 10, + 154, + 1, // Opcode: MVE_VPTv8s16 + /* 11074 */ MCD_OPC_FilterValue, + 1, + 17, + 56, + 0, // Skip to: 25432 + /* 11079 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 11082 */ MCD_OPC_FilterValue, + 0, + 236, + 0, + 0, // Skip to: 11323 + /* 11087 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 11090 */ MCD_OPC_FilterValue, + 0, + 103, + 0, + 0, // Skip to: 11198 + /* 11095 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11098 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11136 + /* 11103 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11106 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11121 + /* 11111 */ MCD_OPC_CheckPredicate, + 22, + 236, + 55, + 0, // Skip to: 25432 + /* 11116 */ MCD_OPC_Decode, + 172, + 8, + 143, + 1, // Opcode: MVE_VHADD_qr_s16 + /* 11121 */ MCD_OPC_FilterValue, + 15, + 226, + 55, + 0, // Skip to: 25432 + /* 11126 */ MCD_OPC_CheckPredicate, + 22, + 221, + 55, + 0, // Skip to: 25432 + /* 11131 */ MCD_OPC_Decode, + 175, + 8, + 143, + 1, // Opcode: MVE_VHADD_qr_u16 + /* 11136 */ MCD_OPC_FilterValue, + 1, + 211, + 55, + 0, // Skip to: 25432 + /* 11141 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11144 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11159 + /* 11149 */ MCD_OPC_CheckPredicate, + 22, + 198, + 55, + 0, // Skip to: 25432 + /* 11154 */ MCD_OPC_Decode, + 190, + 7, + 143, + 1, // Opcode: MVE_VADD_qr_i16 + /* 11159 */ MCD_OPC_FilterValue, + 15, + 188, + 55, + 0, // Skip to: 25432 + /* 11164 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11188 + /* 11169 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11188 + /* 11176 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11188 + /* 11183 */ MCD_OPC_Decode, + 223, + 7, + 155, + 1, // Opcode: MVE_VCMPi16r + /* 11188 */ MCD_OPC_CheckPredicate, + 22, + 159, + 55, + 0, // Skip to: 25432 + /* 11193 */ MCD_OPC_Decode, + 236, + 10, + 156, + 1, // Opcode: MVE_VPTv8i16r + /* 11198 */ MCD_OPC_FilterValue, + 2, + 149, + 55, + 0, // Skip to: 25432 + /* 11203 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11206 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11244 + /* 11211 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11214 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11229 + /* 11219 */ MCD_OPC_CheckPredicate, + 22, + 128, + 55, + 0, // Skip to: 25432 + /* 11224 */ MCD_OPC_Decode, + 244, + 10, + 143, + 1, // Opcode: MVE_VQADD_qr_s16 + /* 11229 */ MCD_OPC_FilterValue, + 15, + 118, + 55, + 0, // Skip to: 25432 + /* 11234 */ MCD_OPC_CheckPredicate, + 22, + 113, + 55, + 0, // Skip to: 25432 + /* 11239 */ MCD_OPC_Decode, + 247, + 10, + 143, + 1, // Opcode: MVE_VQADD_qr_u16 + /* 11244 */ MCD_OPC_FilterValue, + 1, + 103, + 55, + 0, // Skip to: 25432 + /* 11249 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11252 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 11284 + /* 11257 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 11274 + /* 11262 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 11274 + /* 11269 */ MCD_OPC_Decode, + 199, + 8, + 157, + 1, // Opcode: MVE_VIDUPu16 + /* 11274 */ MCD_OPC_CheckPredicate, + 22, + 73, + 55, + 0, // Skip to: 25432 + /* 11279 */ MCD_OPC_Decode, + 202, + 8, + 158, + 1, // Opcode: MVE_VIWDUPu16 + /* 11284 */ MCD_OPC_FilterValue, + 15, + 63, + 55, + 0, // Skip to: 25432 + /* 11289 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11313 + /* 11294 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11313 + /* 11301 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11313 + /* 11308 */ MCD_OPC_Decode, + 235, + 7, + 159, + 1, // Opcode: MVE_VCMPu16r + /* 11313 */ MCD_OPC_CheckPredicate, + 22, + 34, + 55, + 0, // Skip to: 25432 + /* 11318 */ MCD_OPC_Decode, + 240, + 10, + 160, + 1, // Opcode: MVE_VPTv8u16r + /* 11323 */ MCD_OPC_FilterValue, + 1, + 24, + 55, + 0, // Skip to: 25432 + /* 11328 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11331 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 11415 + /* 11336 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 11339 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11377 + /* 11344 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11347 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11362 + /* 11352 */ MCD_OPC_CheckPredicate, + 22, + 251, + 54, + 0, // Skip to: 25432 + /* 11357 */ MCD_OPC_Decode, + 187, + 8, + 143, + 1, // Opcode: MVE_VHSUB_qr_s16 + /* 11362 */ MCD_OPC_FilterValue, + 15, + 241, + 54, + 0, // Skip to: 25432 + /* 11367 */ MCD_OPC_CheckPredicate, + 22, + 236, + 54, + 0, // Skip to: 25432 + /* 11372 */ MCD_OPC_Decode, + 190, + 8, + 143, + 1, // Opcode: MVE_VHSUB_qr_u16 + /* 11377 */ MCD_OPC_FilterValue, + 2, + 226, + 54, + 0, // Skip to: 25432 + /* 11382 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11385 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11400 + /* 11390 */ MCD_OPC_CheckPredicate, + 22, + 213, + 54, + 0, // Skip to: 25432 + /* 11395 */ MCD_OPC_Decode, + 128, + 12, + 143, + 1, // Opcode: MVE_VQSUB_qr_s16 + /* 11400 */ MCD_OPC_FilterValue, + 15, + 203, + 54, + 0, // Skip to: 25432 + /* 11405 */ MCD_OPC_CheckPredicate, + 22, + 198, + 54, + 0, // Skip to: 25432 + /* 11410 */ MCD_OPC_Decode, + 131, + 12, + 143, + 1, // Opcode: MVE_VQSUB_qr_u16 + /* 11415 */ MCD_OPC_FilterValue, + 1, + 188, + 54, + 0, // Skip to: 25432 + /* 11420 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11423 */ MCD_OPC_FilterValue, + 14, + 50, + 0, + 0, // Skip to: 11478 + /* 11428 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 11431 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11446 + /* 11436 */ MCD_OPC_CheckPredicate, + 22, + 167, + 54, + 0, // Skip to: 25432 + /* 11441 */ MCD_OPC_Decode, + 195, + 13, + 143, + 1, // Opcode: MVE_VSUB_qr_i16 + /* 11446 */ MCD_OPC_FilterValue, + 2, + 157, + 54, + 0, // Skip to: 25432 + /* 11451 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 11468 + /* 11456 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 11468 + /* 11463 */ MCD_OPC_Decode, + 154, + 8, + 157, + 1, // Opcode: MVE_VDDUPu16 + /* 11468 */ MCD_OPC_CheckPredicate, + 22, + 135, + 54, + 0, // Skip to: 25432 + /* 11473 */ MCD_OPC_Decode, + 160, + 8, + 158, + 1, // Opcode: MVE_VDWDUPu16 + /* 11478 */ MCD_OPC_FilterValue, + 15, + 125, + 54, + 0, // Skip to: 25432 + /* 11483 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11486 */ MCD_OPC_FilterValue, + 0, + 117, + 54, + 0, // Skip to: 25432 + /* 11491 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11515 + /* 11496 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11515 + /* 11503 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11515 + /* 11510 */ MCD_OPC_Decode, + 229, + 7, + 161, + 1, // Opcode: MVE_VCMPs16r + /* 11515 */ MCD_OPC_CheckPredicate, + 22, + 88, + 54, + 0, // Skip to: 25432 + /* 11520 */ MCD_OPC_Decode, + 238, + 10, + 162, + 1, // Opcode: MVE_VPTv8s16r + /* 11525 */ MCD_OPC_FilterValue, + 2, + 197, + 2, + 0, // Skip to: 12239 + /* 11530 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 11533 */ MCD_OPC_FilterValue, + 0, + 250, + 0, + 0, // Skip to: 11788 + /* 11538 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11541 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 11607 + /* 11546 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11549 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 11578 + /* 11554 */ MCD_OPC_CheckPredicate, + 22, + 49, + 54, + 0, // Skip to: 25432 + /* 11559 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 42, + 54, + 0, // Skip to: 25432 + /* 11566 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 35, + 54, + 0, // Skip to: 25432 + /* 11573 */ MCD_OPC_Decode, + 185, + 8, + 148, + 1, // Opcode: MVE_VHCADDs32 + /* 11578 */ MCD_OPC_FilterValue, + 15, + 25, + 54, + 0, // Skip to: 25432 + /* 11583 */ MCD_OPC_CheckPredicate, + 22, + 20, + 54, + 0, // Skip to: 25432 + /* 11588 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 13, + 54, + 0, // Skip to: 25432 + /* 11595 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 6, + 54, + 0, // Skip to: 25432 + /* 11602 */ MCD_OPC_Decode, + 208, + 7, + 148, + 1, // Opcode: MVE_VCADDi32 + /* 11607 */ MCD_OPC_FilterValue, + 1, + 252, + 53, + 0, // Skip to: 25432 + /* 11612 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 11615 */ MCD_OPC_FilterValue, + 0, + 113, + 0, + 0, // Skip to: 11733 + /* 11620 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 11623 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 11678 + /* 11628 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11631 */ MCD_OPC_FilterValue, + 0, + 228, + 53, + 0, // Skip to: 25432 + /* 11636 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11639 */ MCD_OPC_FilterValue, + 15, + 220, + 53, + 0, // Skip to: 25432 + /* 11644 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11668 + /* 11649 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11668 + /* 11656 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11668 + /* 11663 */ MCD_OPC_Decode, + 224, + 7, + 149, + 1, // Opcode: MVE_VCMPi32 + /* 11668 */ MCD_OPC_CheckPredicate, + 22, + 191, + 53, + 0, // Skip to: 25432 + /* 11673 */ MCD_OPC_Decode, + 227, + 10, + 150, + 1, // Opcode: MVE_VPTv4i32 + /* 11678 */ MCD_OPC_FilterValue, + 1, + 181, + 53, + 0, // Skip to: 25432 + /* 11683 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11686 */ MCD_OPC_FilterValue, + 0, + 173, + 53, + 0, // Skip to: 25432 + /* 11691 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11694 */ MCD_OPC_FilterValue, + 15, + 165, + 53, + 0, // Skip to: 25432 + /* 11699 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11723 + /* 11704 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11723 + /* 11711 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11723 + /* 11718 */ MCD_OPC_Decode, + 236, + 7, + 151, + 1, // Opcode: MVE_VCMPu32 + /* 11723 */ MCD_OPC_CheckPredicate, + 22, + 136, + 53, + 0, // Skip to: 25432 + /* 11728 */ MCD_OPC_Decode, + 231, + 10, + 152, + 1, // Opcode: MVE_VPTv4u32 + /* 11733 */ MCD_OPC_FilterValue, + 1, + 126, + 53, + 0, // Skip to: 25432 + /* 11738 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11741 */ MCD_OPC_FilterValue, + 0, + 118, + 53, + 0, // Skip to: 25432 + /* 11746 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11749 */ MCD_OPC_FilterValue, + 15, + 110, + 53, + 0, // Skip to: 25432 + /* 11754 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11778 + /* 11759 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11778 + /* 11766 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11778 + /* 11773 */ MCD_OPC_Decode, + 230, + 7, + 153, + 1, // Opcode: MVE_VCMPs32 + /* 11778 */ MCD_OPC_CheckPredicate, + 22, + 81, + 53, + 0, // Skip to: 25432 + /* 11783 */ MCD_OPC_Decode, + 229, + 10, + 154, + 1, // Opcode: MVE_VPTv4s32 + /* 11788 */ MCD_OPC_FilterValue, + 1, + 71, + 53, + 0, // Skip to: 25432 + /* 11793 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 11796 */ MCD_OPC_FilterValue, + 0, + 236, + 0, + 0, // Skip to: 12037 + /* 11801 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 11804 */ MCD_OPC_FilterValue, + 0, + 103, + 0, + 0, // Skip to: 11912 + /* 11809 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11812 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11850 + /* 11817 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11820 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11835 + /* 11825 */ MCD_OPC_CheckPredicate, + 22, + 34, + 53, + 0, // Skip to: 25432 + /* 11830 */ MCD_OPC_Decode, + 173, + 8, + 143, + 1, // Opcode: MVE_VHADD_qr_s32 + /* 11835 */ MCD_OPC_FilterValue, + 15, + 24, + 53, + 0, // Skip to: 25432 + /* 11840 */ MCD_OPC_CheckPredicate, + 22, + 19, + 53, + 0, // Skip to: 25432 + /* 11845 */ MCD_OPC_Decode, + 176, + 8, + 143, + 1, // Opcode: MVE_VHADD_qr_u32 + /* 11850 */ MCD_OPC_FilterValue, + 1, + 9, + 53, + 0, // Skip to: 25432 + /* 11855 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11858 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11873 + /* 11863 */ MCD_OPC_CheckPredicate, + 22, + 252, + 52, + 0, // Skip to: 25432 + /* 11868 */ MCD_OPC_Decode, + 191, + 7, + 143, + 1, // Opcode: MVE_VADD_qr_i32 + /* 11873 */ MCD_OPC_FilterValue, + 15, + 242, + 52, + 0, // Skip to: 25432 + /* 11878 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 11902 + /* 11883 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 11902 + /* 11890 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 11902 + /* 11897 */ MCD_OPC_Decode, + 225, + 7, + 155, + 1, // Opcode: MVE_VCMPi32r + /* 11902 */ MCD_OPC_CheckPredicate, + 22, + 213, + 52, + 0, // Skip to: 25432 + /* 11907 */ MCD_OPC_Decode, + 228, + 10, + 156, + 1, // Opcode: MVE_VPTv4i32r + /* 11912 */ MCD_OPC_FilterValue, + 2, + 203, + 52, + 0, // Skip to: 25432 + /* 11917 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 11920 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 11958 + /* 11925 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11928 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11943 + /* 11933 */ MCD_OPC_CheckPredicate, + 22, + 182, + 52, + 0, // Skip to: 25432 + /* 11938 */ MCD_OPC_Decode, + 245, + 10, + 143, + 1, // Opcode: MVE_VQADD_qr_s32 + /* 11943 */ MCD_OPC_FilterValue, + 15, + 172, + 52, + 0, // Skip to: 25432 + /* 11948 */ MCD_OPC_CheckPredicate, + 22, + 167, + 52, + 0, // Skip to: 25432 + /* 11953 */ MCD_OPC_Decode, + 248, + 10, + 143, + 1, // Opcode: MVE_VQADD_qr_u32 + /* 11958 */ MCD_OPC_FilterValue, + 1, + 157, + 52, + 0, // Skip to: 25432 + /* 11963 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 11966 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 11998 + /* 11971 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 11988 + /* 11976 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 11988 + /* 11983 */ MCD_OPC_Decode, + 200, + 8, + 157, + 1, // Opcode: MVE_VIDUPu32 + /* 11988 */ MCD_OPC_CheckPredicate, + 22, + 127, + 52, + 0, // Skip to: 25432 + /* 11993 */ MCD_OPC_Decode, + 203, + 8, + 158, + 1, // Opcode: MVE_VIWDUPu32 + /* 11998 */ MCD_OPC_FilterValue, + 15, + 117, + 52, + 0, // Skip to: 25432 + /* 12003 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 12027 + /* 12008 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12027 + /* 12015 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12027 + /* 12022 */ MCD_OPC_Decode, + 237, + 7, + 159, + 1, // Opcode: MVE_VCMPu32r + /* 12027 */ MCD_OPC_CheckPredicate, + 22, + 88, + 52, + 0, // Skip to: 25432 + /* 12032 */ MCD_OPC_Decode, + 232, + 10, + 160, + 1, // Opcode: MVE_VPTv4u32r + /* 12037 */ MCD_OPC_FilterValue, + 1, + 78, + 52, + 0, // Skip to: 25432 + /* 12042 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 12045 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 12129 + /* 12050 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 12053 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 12091 + /* 12058 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12061 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12076 + /* 12066 */ MCD_OPC_CheckPredicate, + 22, + 49, + 52, + 0, // Skip to: 25432 + /* 12071 */ MCD_OPC_Decode, + 188, + 8, + 143, + 1, // Opcode: MVE_VHSUB_qr_s32 + /* 12076 */ MCD_OPC_FilterValue, + 15, + 39, + 52, + 0, // Skip to: 25432 + /* 12081 */ MCD_OPC_CheckPredicate, + 22, + 34, + 52, + 0, // Skip to: 25432 + /* 12086 */ MCD_OPC_Decode, + 191, + 8, + 143, + 1, // Opcode: MVE_VHSUB_qr_u32 + /* 12091 */ MCD_OPC_FilterValue, + 2, + 24, + 52, + 0, // Skip to: 25432 + /* 12096 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12099 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12114 + /* 12104 */ MCD_OPC_CheckPredicate, + 22, + 11, + 52, + 0, // Skip to: 25432 + /* 12109 */ MCD_OPC_Decode, + 129, + 12, + 143, + 1, // Opcode: MVE_VQSUB_qr_s32 + /* 12114 */ MCD_OPC_FilterValue, + 15, + 1, + 52, + 0, // Skip to: 25432 + /* 12119 */ MCD_OPC_CheckPredicate, + 22, + 252, + 51, + 0, // Skip to: 25432 + /* 12124 */ MCD_OPC_Decode, + 132, + 12, + 143, + 1, // Opcode: MVE_VQSUB_qr_u32 + /* 12129 */ MCD_OPC_FilterValue, + 1, + 242, + 51, + 0, // Skip to: 25432 + /* 12134 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12137 */ MCD_OPC_FilterValue, + 14, + 50, + 0, + 0, // Skip to: 12192 + /* 12142 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 12145 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 12160 + /* 12150 */ MCD_OPC_CheckPredicate, + 22, + 221, + 51, + 0, // Skip to: 25432 + /* 12155 */ MCD_OPC_Decode, + 196, + 13, + 143, + 1, // Opcode: MVE_VSUB_qr_i32 + /* 12160 */ MCD_OPC_FilterValue, + 2, + 211, + 51, + 0, // Skip to: 25432 + /* 12165 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 12182 + /* 12170 */ MCD_OPC_CheckField, + 1, + 3, + 7, + 5, + 0, + 0, // Skip to: 12182 + /* 12177 */ MCD_OPC_Decode, + 155, + 8, + 157, + 1, // Opcode: MVE_VDDUPu32 + /* 12182 */ MCD_OPC_CheckPredicate, + 22, + 189, + 51, + 0, // Skip to: 25432 + /* 12187 */ MCD_OPC_Decode, + 161, + 8, + 158, + 1, // Opcode: MVE_VDWDUPu32 + /* 12192 */ MCD_OPC_FilterValue, + 15, + 179, + 51, + 0, // Skip to: 25432 + /* 12197 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12200 */ MCD_OPC_FilterValue, + 0, + 171, + 51, + 0, // Skip to: 25432 + /* 12205 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 12229 + /* 12210 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12229 + /* 12217 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12229 + /* 12224 */ MCD_OPC_Decode, + 231, + 7, + 161, + 1, // Opcode: MVE_VCMPs32r + /* 12229 */ MCD_OPC_CheckPredicate, + 22, + 142, + 51, + 0, // Skip to: 25432 + /* 12234 */ MCD_OPC_Decode, + 230, + 10, + 162, + 1, // Opcode: MVE_VPTv4s32r + /* 12239 */ MCD_OPC_FilterValue, + 3, + 132, + 51, + 0, // Skip to: 25432 + /* 12244 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 12247 */ MCD_OPC_FilterValue, + 0, + 105, + 1, + 0, // Skip to: 12613 + /* 12252 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 12255 */ MCD_OPC_FilterValue, + 0, + 227, + 0, + 0, // Skip to: 12487 + /* 12260 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 12263 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 12375 + /* 12268 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 12271 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 12323 + /* 12276 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12279 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 12301 + /* 12284 */ MCD_OPC_CheckPredicate, + 22, + 87, + 51, + 0, // Skip to: 25432 + /* 12289 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 80, + 51, + 0, // Skip to: 25432 + /* 12296 */ MCD_OPC_Decode, + 170, + 7, + 163, + 1, // Opcode: MVE_VADC + /* 12301 */ MCD_OPC_FilterValue, + 15, + 70, + 51, + 0, // Skip to: 25432 + /* 12306 */ MCD_OPC_CheckPredicate, + 22, + 65, + 51, + 0, // Skip to: 25432 + /* 12311 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 58, + 51, + 0, // Skip to: 25432 + /* 12318 */ MCD_OPC_Decode, + 202, + 12, + 163, + 1, // Opcode: MVE_VSBC + /* 12323 */ MCD_OPC_FilterValue, + 1, + 48, + 51, + 0, // Skip to: 25432 + /* 12328 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12331 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 12353 + /* 12336 */ MCD_OPC_CheckPredicate, + 22, + 35, + 51, + 0, // Skip to: 25432 + /* 12341 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 28, + 51, + 0, // Skip to: 25432 + /* 12348 */ MCD_OPC_Decode, + 171, + 7, + 163, + 1, // Opcode: MVE_VADCI + /* 12353 */ MCD_OPC_FilterValue, + 15, + 18, + 51, + 0, // Skip to: 25432 + /* 12358 */ MCD_OPC_CheckPredicate, + 22, + 13, + 51, + 0, // Skip to: 25432 + /* 12363 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 6, + 51, + 0, // Skip to: 25432 + /* 12370 */ MCD_OPC_Decode, + 203, + 12, + 163, + 1, // Opcode: MVE_VSBCI + /* 12375 */ MCD_OPC_FilterValue, + 1, + 252, + 50, + 0, // Skip to: 25432 + /* 12380 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 12383 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 12435 + /* 12388 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12391 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 12413 + /* 12396 */ MCD_OPC_CheckPredicate, + 22, + 231, + 50, + 0, // Skip to: 25432 + /* 12401 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 224, + 50, + 0, // Skip to: 25432 + /* 12408 */ MCD_OPC_Decode, + 156, + 11, + 141, + 1, // Opcode: MVE_VQDMULLs16bh + /* 12413 */ MCD_OPC_FilterValue, + 15, + 214, + 50, + 0, // Skip to: 25432 + /* 12418 */ MCD_OPC_CheckPredicate, + 22, + 209, + 50, + 0, // Skip to: 25432 + /* 12423 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 202, + 50, + 0, // Skip to: 25432 + /* 12430 */ MCD_OPC_Decode, + 158, + 11, + 141, + 1, // Opcode: MVE_VQDMULLs32bh + /* 12435 */ MCD_OPC_FilterValue, + 1, + 192, + 50, + 0, // Skip to: 25432 + /* 12440 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12443 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 12465 + /* 12448 */ MCD_OPC_CheckPredicate, + 22, + 179, + 50, + 0, // Skip to: 25432 + /* 12453 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 172, + 50, + 0, // Skip to: 25432 + /* 12460 */ MCD_OPC_Decode, + 157, + 11, + 141, + 1, // Opcode: MVE_VQDMULLs16th + /* 12465 */ MCD_OPC_FilterValue, + 15, + 162, + 50, + 0, // Skip to: 25432 + /* 12470 */ MCD_OPC_CheckPredicate, + 22, + 157, + 50, + 0, // Skip to: 25432 + /* 12475 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 150, + 50, + 0, // Skip to: 25432 + /* 12482 */ MCD_OPC_Decode, + 159, + 11, + 141, + 1, // Opcode: MVE_VQDMULLs32th + /* 12487 */ MCD_OPC_FilterValue, + 1, + 140, + 50, + 0, // Skip to: 25432 + /* 12492 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12495 */ MCD_OPC_FilterValue, + 14, + 42, + 0, + 0, // Skip to: 12542 + /* 12500 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12503 */ MCD_OPC_FilterValue, + 0, + 124, + 50, + 0, // Skip to: 25432 + /* 12508 */ MCD_OPC_CheckPredicate, + 24, + 19, + 0, + 0, // Skip to: 12532 + /* 12513 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12532 + /* 12520 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12532 + /* 12527 */ MCD_OPC_Decode, + 220, + 7, + 164, + 1, // Opcode: MVE_VCMPf32 + /* 12532 */ MCD_OPC_CheckPredicate, + 24, + 95, + 50, + 0, // Skip to: 25432 + /* 12537 */ MCD_OPC_Decode, + 225, + 10, + 165, + 1, // Opcode: MVE_VPTv4f32 + /* 12542 */ MCD_OPC_FilterValue, + 15, + 85, + 50, + 0, // Skip to: 25432 + /* 12547 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12550 */ MCD_OPC_FilterValue, + 0, + 77, + 50, + 0, // Skip to: 25432 + /* 12555 */ MCD_OPC_CheckPredicate, + 22, + 19, + 0, + 0, // Skip to: 12579 + /* 12560 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 12, + 0, + 0, // Skip to: 12579 + /* 12567 */ MCD_OPC_CheckField, + 0, + 1, + 1, + 5, + 0, + 0, // Skip to: 12579 + /* 12574 */ MCD_OPC_Decode, + 217, + 10, + 166, + 1, // Opcode: MVE_VPSEL + /* 12579 */ MCD_OPC_CheckPredicate, + 24, + 19, + 0, + 0, // Skip to: 12603 + /* 12584 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12603 + /* 12591 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12603 + /* 12598 */ MCD_OPC_Decode, + 218, + 7, + 164, + 1, // Opcode: MVE_VCMPf16 + /* 12603 */ MCD_OPC_CheckPredicate, + 24, + 24, + 50, + 0, // Skip to: 25432 + /* 12608 */ MCD_OPC_Decode, + 233, + 10, + 165, + 1, // Opcode: MVE_VPTv8f16 + /* 12613 */ MCD_OPC_FilterValue, + 1, + 14, + 50, + 0, // Skip to: 25432 + /* 12618 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 12621 */ MCD_OPC_FilterValue, + 0, + 171, + 0, + 0, // Skip to: 12797 + /* 12626 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 12629 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 12713 + /* 12634 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 12637 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 12675 + /* 12642 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12645 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12660 + /* 12650 */ MCD_OPC_CheckPredicate, + 24, + 233, + 49, + 0, // Skip to: 25432 + /* 12655 */ MCD_OPC_Decode, + 189, + 7, + 143, + 1, // Opcode: MVE_VADD_qr_f32 + /* 12660 */ MCD_OPC_FilterValue, + 15, + 223, + 49, + 0, // Skip to: 25432 + /* 12665 */ MCD_OPC_CheckPredicate, + 24, + 218, + 49, + 0, // Skip to: 25432 + /* 12670 */ MCD_OPC_Decode, + 188, + 7, + 143, + 1, // Opcode: MVE_VADD_qr_f16 + /* 12675 */ MCD_OPC_FilterValue, + 1, + 208, + 49, + 0, // Skip to: 25432 + /* 12680 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12683 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12698 + /* 12688 */ MCD_OPC_CheckPredicate, + 24, + 195, + 49, + 0, // Skip to: 25432 + /* 12693 */ MCD_OPC_Decode, + 194, + 13, + 143, + 1, // Opcode: MVE_VSUB_qr_f32 + /* 12698 */ MCD_OPC_FilterValue, + 15, + 185, + 49, + 0, // Skip to: 25432 + /* 12703 */ MCD_OPC_CheckPredicate, + 24, + 180, + 49, + 0, // Skip to: 25432 + /* 12708 */ MCD_OPC_Decode, + 193, + 13, + 143, + 1, // Opcode: MVE_VSUB_qr_f16 + /* 12713 */ MCD_OPC_FilterValue, + 2, + 170, + 49, + 0, // Skip to: 25432 + /* 12718 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 12721 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 12759 + /* 12726 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12729 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12744 + /* 12734 */ MCD_OPC_CheckPredicate, + 22, + 149, + 49, + 0, // Skip to: 25432 + /* 12739 */ MCD_OPC_Decode, + 152, + 11, + 143, + 1, // Opcode: MVE_VQDMULL_qr_s16bh + /* 12744 */ MCD_OPC_FilterValue, + 15, + 139, + 49, + 0, // Skip to: 25432 + /* 12749 */ MCD_OPC_CheckPredicate, + 22, + 134, + 49, + 0, // Skip to: 25432 + /* 12754 */ MCD_OPC_Decode, + 154, + 11, + 143, + 1, // Opcode: MVE_VQDMULL_qr_s32bh + /* 12759 */ MCD_OPC_FilterValue, + 1, + 124, + 49, + 0, // Skip to: 25432 + /* 12764 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12767 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12782 + /* 12772 */ MCD_OPC_CheckPredicate, + 22, + 111, + 49, + 0, // Skip to: 25432 + /* 12777 */ MCD_OPC_Decode, + 153, + 11, + 143, + 1, // Opcode: MVE_VQDMULL_qr_s16th + /* 12782 */ MCD_OPC_FilterValue, + 15, + 101, + 49, + 0, // Skip to: 25432 + /* 12787 */ MCD_OPC_CheckPredicate, + 22, + 96, + 49, + 0, // Skip to: 25432 + /* 12792 */ MCD_OPC_Decode, + 155, + 11, + 143, + 1, // Opcode: MVE_VQDMULL_qr_s32th + /* 12797 */ MCD_OPC_FilterValue, + 1, + 86, + 49, + 0, // Skip to: 25432 + /* 12802 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 12805 */ MCD_OPC_FilterValue, + 14, + 42, + 0, + 0, // Skip to: 12852 + /* 12810 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12813 */ MCD_OPC_FilterValue, + 0, + 70, + 49, + 0, // Skip to: 25432 + /* 12818 */ MCD_OPC_CheckPredicate, + 24, + 19, + 0, + 0, // Skip to: 12842 + /* 12823 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12842 + /* 12830 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12842 + /* 12837 */ MCD_OPC_Decode, + 221, + 7, + 167, + 1, // Opcode: MVE_VCMPf32r + /* 12842 */ MCD_OPC_CheckPredicate, + 24, + 41, + 49, + 0, // Skip to: 25432 + /* 12847 */ MCD_OPC_Decode, + 226, + 10, + 168, + 1, // Opcode: MVE_VPTv4f32r + /* 12852 */ MCD_OPC_FilterValue, + 15, + 31, + 49, + 0, // Skip to: 25432 + /* 12857 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 12860 */ MCD_OPC_FilterValue, + 0, + 23, + 49, + 0, // Skip to: 25432 + /* 12865 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 12868 */ MCD_OPC_FilterValue, + 13, + 50, + 0, + 0, // Skip to: 12923 + /* 12873 */ MCD_OPC_CheckPredicate, + 22, + 24, + 0, + 0, // Skip to: 12902 + /* 12878 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 17, + 0, + 0, // Skip to: 12902 + /* 12885 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 10, + 0, + 0, // Skip to: 12902 + /* 12892 */ MCD_OPC_SoftFail, + 160, + 161, + 56 /* 0xe10a0 */, + 0, + /* 12897 */ MCD_OPC_Decode, + 216, + 10, + 169, + 1, // Opcode: MVE_VPNOT + /* 12902 */ MCD_OPC_CheckPredicate, + 22, + 16, + 0, + 0, // Skip to: 12923 + /* 12907 */ MCD_OPC_CheckField, + 17, + 3, + 0, + 9, + 0, + 0, // Skip to: 12923 + /* 12914 */ MCD_OPC_SoftFail, + 160, + 33 /* 0x10a0 */, + 0, + /* 12918 */ MCD_OPC_Decode, + 218, + 10, + 170, + 1, // Opcode: MVE_VPST + /* 12923 */ MCD_OPC_CheckPredicate, + 24, + 19, + 0, + 0, // Skip to: 12947 + /* 12928 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 12, + 0, + 0, // Skip to: 12947 + /* 12935 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 5, + 0, + 0, // Skip to: 12947 + /* 12942 */ MCD_OPC_Decode, + 219, + 7, + 167, + 1, // Opcode: MVE_VCMPf16r + /* 12947 */ MCD_OPC_CheckPredicate, + 24, + 192, + 48, + 0, // Skip to: 25432 + /* 12952 */ MCD_OPC_Decode, + 234, + 10, + 168, + 1, // Opcode: MVE_VPTv8f16r + /* 12957 */ MCD_OPC_FilterValue, + 1, + 119, + 16, + 0, // Skip to: 17177 + /* 12962 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 12965 */ MCD_OPC_FilterValue, + 11, + 179, + 0, + 0, // Skip to: 13149 + /* 12970 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 12973 */ MCD_OPC_FilterValue, + 0, + 105, + 0, + 0, // Skip to: 13083 + /* 12978 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 12981 */ MCD_OPC_FilterValue, + 16, + 61, + 0, + 0, // Skip to: 13047 + /* 12986 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 12989 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 13018 + /* 12994 */ MCD_OPC_CheckPredicate, + 22, + 145, + 48, + 0, // Skip to: 25432 + /* 12999 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 138, + 48, + 0, // Skip to: 25432 + /* 13006 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 131, + 48, + 0, // Skip to: 25432 + /* 13013 */ MCD_OPC_Decode, + 158, + 8, + 171, + 1, // Opcode: MVE_VDUP32 + /* 13018 */ MCD_OPC_FilterValue, + 3, + 121, + 48, + 0, // Skip to: 25432 + /* 13023 */ MCD_OPC_CheckPredicate, + 22, + 116, + 48, + 0, // Skip to: 25432 + /* 13028 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 109, + 48, + 0, // Skip to: 25432 + /* 13035 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 102, + 48, + 0, // Skip to: 25432 + /* 13042 */ MCD_OPC_Decode, + 159, + 8, + 171, + 1, // Opcode: MVE_VDUP8 + /* 13047 */ MCD_OPC_FilterValue, + 48, + 92, + 48, + 0, // Skip to: 25432 + /* 13052 */ MCD_OPC_CheckPredicate, + 22, + 87, + 48, + 0, // Skip to: 25432 + /* 13057 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 80, + 48, + 0, // Skip to: 25432 + /* 13064 */ MCD_OPC_CheckField, + 21, + 2, + 1, + 73, + 48, + 0, // Skip to: 25432 + /* 13071 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 66, + 48, + 0, // Skip to: 25432 + /* 13078 */ MCD_OPC_Decode, + 157, + 8, + 171, + 1, // Opcode: MVE_VDUP16 + /* 13083 */ MCD_OPC_FilterValue, + 1, + 56, + 48, + 0, // Skip to: 25432 + /* 13088 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 13091 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 13120 + /* 13096 */ MCD_OPC_CheckPredicate, + 23, + 43, + 48, + 0, // Skip to: 25432 + /* 13101 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 36, + 48, + 0, // Skip to: 25432 + /* 13108 */ MCD_OPC_CheckField, + 0, + 6, + 48, + 29, + 48, + 0, // Skip to: 25432 + /* 13115 */ MCD_OPC_Decode, + 160, + 10, + 138, + 1, // Opcode: MVE_VMOV_from_lane_u16 + /* 13120 */ MCD_OPC_FilterValue, + 1, + 19, + 48, + 0, // Skip to: 25432 + /* 13125 */ MCD_OPC_CheckPredicate, + 23, + 14, + 48, + 0, // Skip to: 25432 + /* 13130 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 7, + 48, + 0, // Skip to: 25432 + /* 13137 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 0, + 48, + 0, // Skip to: 25432 + /* 13144 */ MCD_OPC_Decode, + 161, + 10, + 139, + 1, // Opcode: MVE_VMOV_from_lane_u8 + /* 13149 */ MCD_OPC_FilterValue, + 14, + 243, + 3, + 0, // Skip to: 14165 + /* 13154 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 13157 */ MCD_OPC_FilterValue, + 0, + 243, + 1, + 0, // Skip to: 13661 + /* 13162 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 13165 */ MCD_OPC_FilterValue, + 0, + 243, + 0, + 0, // Skip to: 13413 + /* 13170 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 13173 */ MCD_OPC_FilterValue, + 0, + 147, + 0, + 0, // Skip to: 13325 + /* 13178 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13181 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 13253 + /* 13186 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13189 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13221 + /* 13194 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13211 + /* 13199 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13211 + /* 13206 */ MCD_OPC_Decode, + 220, + 9, + 172, + 1, // Opcode: MVE_VMLADAVs16 + /* 13211 */ MCD_OPC_CheckPredicate, + 22, + 184, + 47, + 0, // Skip to: 25432 + /* 13216 */ MCD_OPC_Decode, + 235, + 9, + 173, + 1, // Opcode: MVE_VMLALDAVs16 + /* 13221 */ MCD_OPC_FilterValue, + 15, + 174, + 47, + 0, // Skip to: 25432 + /* 13226 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13243 + /* 13231 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13243 + /* 13238 */ MCD_OPC_Decode, + 223, + 9, + 172, + 1, // Opcode: MVE_VMLADAVu16 + /* 13243 */ MCD_OPC_CheckPredicate, + 22, + 152, + 47, + 0, // Skip to: 25432 + /* 13248 */ MCD_OPC_Decode, + 237, + 9, + 173, + 1, // Opcode: MVE_VMLALDAVu16 + /* 13253 */ MCD_OPC_FilterValue, + 1, + 142, + 47, + 0, // Skip to: 25432 + /* 13258 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13261 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13293 + /* 13266 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13283 + /* 13271 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13283 + /* 13278 */ MCD_OPC_Decode, + 221, + 9, + 172, + 1, // Opcode: MVE_VMLADAVs32 + /* 13283 */ MCD_OPC_CheckPredicate, + 22, + 112, + 47, + 0, // Skip to: 25432 + /* 13288 */ MCD_OPC_Decode, + 236, + 9, + 173, + 1, // Opcode: MVE_VMLALDAVs32 + /* 13293 */ MCD_OPC_FilterValue, + 15, + 102, + 47, + 0, // Skip to: 25432 + /* 13298 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13315 + /* 13303 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13315 + /* 13310 */ MCD_OPC_Decode, + 224, + 9, + 172, + 1, // Opcode: MVE_VMLADAVu32 + /* 13315 */ MCD_OPC_CheckPredicate, + 22, + 80, + 47, + 0, // Skip to: 25432 + /* 13320 */ MCD_OPC_Decode, + 238, + 9, + 173, + 1, // Opcode: MVE_VMLALDAVu32 + /* 13325 */ MCD_OPC_FilterValue, + 1, + 70, + 47, + 0, // Skip to: 25432 + /* 13330 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13333 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 13373 + /* 13338 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13341 */ MCD_OPC_FilterValue, + 14, + 54, + 47, + 0, // Skip to: 25432 + /* 13346 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13363 + /* 13351 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13363 + /* 13358 */ MCD_OPC_Decode, + 226, + 9, + 172, + 1, // Opcode: MVE_VMLADAVxs16 + /* 13363 */ MCD_OPC_CheckPredicate, + 22, + 32, + 47, + 0, // Skip to: 25432 + /* 13368 */ MCD_OPC_Decode, + 239, + 9, + 173, + 1, // Opcode: MVE_VMLALDAVxs16 + /* 13373 */ MCD_OPC_FilterValue, + 1, + 22, + 47, + 0, // Skip to: 25432 + /* 13378 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13381 */ MCD_OPC_FilterValue, + 14, + 14, + 47, + 0, // Skip to: 25432 + /* 13386 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13403 + /* 13391 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13403 + /* 13398 */ MCD_OPC_Decode, + 227, + 9, + 172, + 1, // Opcode: MVE_VMLADAVxs32 + /* 13403 */ MCD_OPC_CheckPredicate, + 22, + 248, + 46, + 0, // Skip to: 25432 + /* 13408 */ MCD_OPC_Decode, + 240, + 9, + 173, + 1, // Opcode: MVE_VMLALDAVxs32 + /* 13413 */ MCD_OPC_FilterValue, + 2, + 238, + 46, + 0, // Skip to: 25432 + /* 13418 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 13421 */ MCD_OPC_FilterValue, + 0, + 147, + 0, + 0, // Skip to: 13573 + /* 13426 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13429 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 13501 + /* 13434 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13437 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13469 + /* 13442 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13459 + /* 13447 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13459 + /* 13454 */ MCD_OPC_Decode, + 211, + 9, + 174, + 1, // Opcode: MVE_VMLADAVas16 + /* 13459 */ MCD_OPC_CheckPredicate, + 22, + 192, + 46, + 0, // Skip to: 25432 + /* 13464 */ MCD_OPC_Decode, + 229, + 9, + 175, + 1, // Opcode: MVE_VMLALDAVas16 + /* 13469 */ MCD_OPC_FilterValue, + 15, + 182, + 46, + 0, // Skip to: 25432 + /* 13474 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13491 + /* 13479 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13491 + /* 13486 */ MCD_OPC_Decode, + 214, + 9, + 174, + 1, // Opcode: MVE_VMLADAVau16 + /* 13491 */ MCD_OPC_CheckPredicate, + 22, + 160, + 46, + 0, // Skip to: 25432 + /* 13496 */ MCD_OPC_Decode, + 231, + 9, + 175, + 1, // Opcode: MVE_VMLALDAVau16 + /* 13501 */ MCD_OPC_FilterValue, + 1, + 150, + 46, + 0, // Skip to: 25432 + /* 13506 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13509 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13541 + /* 13514 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13531 + /* 13519 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13531 + /* 13526 */ MCD_OPC_Decode, + 212, + 9, + 174, + 1, // Opcode: MVE_VMLADAVas32 + /* 13531 */ MCD_OPC_CheckPredicate, + 22, + 120, + 46, + 0, // Skip to: 25432 + /* 13536 */ MCD_OPC_Decode, + 230, + 9, + 175, + 1, // Opcode: MVE_VMLALDAVas32 + /* 13541 */ MCD_OPC_FilterValue, + 15, + 110, + 46, + 0, // Skip to: 25432 + /* 13546 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13563 + /* 13551 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13563 + /* 13558 */ MCD_OPC_Decode, + 215, + 9, + 174, + 1, // Opcode: MVE_VMLADAVau32 + /* 13563 */ MCD_OPC_CheckPredicate, + 22, + 88, + 46, + 0, // Skip to: 25432 + /* 13568 */ MCD_OPC_Decode, + 232, + 9, + 175, + 1, // Opcode: MVE_VMLALDAVau32 + /* 13573 */ MCD_OPC_FilterValue, + 1, + 78, + 46, + 0, // Skip to: 25432 + /* 13578 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13581 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 13621 + /* 13586 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13589 */ MCD_OPC_FilterValue, + 14, + 62, + 46, + 0, // Skip to: 25432 + /* 13594 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13611 + /* 13599 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13611 + /* 13606 */ MCD_OPC_Decode, + 217, + 9, + 174, + 1, // Opcode: MVE_VMLADAVaxs16 + /* 13611 */ MCD_OPC_CheckPredicate, + 22, + 40, + 46, + 0, // Skip to: 25432 + /* 13616 */ MCD_OPC_Decode, + 233, + 9, + 175, + 1, // Opcode: MVE_VMLALDAVaxs16 + /* 13621 */ MCD_OPC_FilterValue, + 1, + 30, + 46, + 0, // Skip to: 25432 + /* 13626 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13629 */ MCD_OPC_FilterValue, + 14, + 22, + 46, + 0, // Skip to: 25432 + /* 13634 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13651 + /* 13639 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13651 + /* 13646 */ MCD_OPC_Decode, + 218, + 9, + 174, + 1, // Opcode: MVE_VMLADAVaxs32 + /* 13651 */ MCD_OPC_CheckPredicate, + 22, + 0, + 46, + 0, // Skip to: 25432 + /* 13656 */ MCD_OPC_Decode, + 234, + 9, + 175, + 1, // Opcode: MVE_VMLALDAVaxs32 + /* 13661 */ MCD_OPC_FilterValue, + 1, + 246, + 45, + 0, // Skip to: 25432 + /* 13666 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 13669 */ MCD_OPC_FilterValue, + 0, + 243, + 0, + 0, // Skip to: 13917 + /* 13674 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 13677 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 13797 + /* 13682 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13685 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 13757 + /* 13690 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13693 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13725 + /* 13698 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13715 + /* 13703 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13715 + /* 13710 */ MCD_OPC_Decode, + 131, + 10, + 172, + 1, // Opcode: MVE_VMLSDAVs16 + /* 13715 */ MCD_OPC_CheckPredicate, + 22, + 192, + 45, + 0, // Skip to: 25432 + /* 13720 */ MCD_OPC_Decode, + 141, + 10, + 173, + 1, // Opcode: MVE_VMLSLDAVs16 + /* 13725 */ MCD_OPC_FilterValue, + 15, + 182, + 45, + 0, // Skip to: 25432 + /* 13730 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13747 + /* 13735 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13747 + /* 13742 */ MCD_OPC_Decode, + 133, + 10, + 172, + 1, // Opcode: MVE_VMLSDAVs8 + /* 13747 */ MCD_OPC_CheckPredicate, + 22, + 160, + 45, + 0, // Skip to: 25432 + /* 13752 */ MCD_OPC_Decode, + 172, + 12, + 173, + 1, // Opcode: MVE_VRMLSLDAVHs32 + /* 13757 */ MCD_OPC_FilterValue, + 1, + 150, + 45, + 0, // Skip to: 25432 + /* 13762 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13765 */ MCD_OPC_FilterValue, + 14, + 142, + 45, + 0, // Skip to: 25432 + /* 13770 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13787 + /* 13775 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13787 + /* 13782 */ MCD_OPC_Decode, + 132, + 10, + 172, + 1, // Opcode: MVE_VMLSDAVs32 + /* 13787 */ MCD_OPC_CheckPredicate, + 22, + 120, + 45, + 0, // Skip to: 25432 + /* 13792 */ MCD_OPC_Decode, + 142, + 10, + 173, + 1, // Opcode: MVE_VMLSLDAVs32 + /* 13797 */ MCD_OPC_FilterValue, + 1, + 110, + 45, + 0, // Skip to: 25432 + /* 13802 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13805 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 13877 + /* 13810 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13813 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13845 + /* 13818 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13835 + /* 13823 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13835 + /* 13830 */ MCD_OPC_Decode, + 134, + 10, + 172, + 1, // Opcode: MVE_VMLSDAVxs16 + /* 13835 */ MCD_OPC_CheckPredicate, + 22, + 72, + 45, + 0, // Skip to: 25432 + /* 13840 */ MCD_OPC_Decode, + 143, + 10, + 173, + 1, // Opcode: MVE_VMLSLDAVxs16 + /* 13845 */ MCD_OPC_FilterValue, + 15, + 62, + 45, + 0, // Skip to: 25432 + /* 13850 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13867 + /* 13855 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13867 + /* 13862 */ MCD_OPC_Decode, + 136, + 10, + 172, + 1, // Opcode: MVE_VMLSDAVxs8 + /* 13867 */ MCD_OPC_CheckPredicate, + 22, + 40, + 45, + 0, // Skip to: 25432 + /* 13872 */ MCD_OPC_Decode, + 173, + 12, + 173, + 1, // Opcode: MVE_VRMLSLDAVHxs32 + /* 13877 */ MCD_OPC_FilterValue, + 1, + 30, + 45, + 0, // Skip to: 25432 + /* 13882 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13885 */ MCD_OPC_FilterValue, + 14, + 22, + 45, + 0, // Skip to: 25432 + /* 13890 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13907 + /* 13895 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13907 + /* 13902 */ MCD_OPC_Decode, + 135, + 10, + 172, + 1, // Opcode: MVE_VMLSDAVxs32 + /* 13907 */ MCD_OPC_CheckPredicate, + 22, + 0, + 45, + 0, // Skip to: 25432 + /* 13912 */ MCD_OPC_Decode, + 144, + 10, + 173, + 1, // Opcode: MVE_VMLSLDAVxs32 + /* 13917 */ MCD_OPC_FilterValue, + 2, + 246, + 44, + 0, // Skip to: 25432 + /* 13922 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 13925 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 14045 + /* 13930 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 13933 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 14005 + /* 13938 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 13941 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 13973 + /* 13946 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13963 + /* 13951 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13963 + /* 13958 */ MCD_OPC_Decode, + 253, + 9, + 174, + 1, // Opcode: MVE_VMLSDAVas16 + /* 13963 */ MCD_OPC_CheckPredicate, + 22, + 200, + 44, + 0, // Skip to: 25432 + /* 13968 */ MCD_OPC_Decode, + 137, + 10, + 175, + 1, // Opcode: MVE_VMLSLDAVas16 + /* 13973 */ MCD_OPC_FilterValue, + 15, + 190, + 44, + 0, // Skip to: 25432 + /* 13978 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 13995 + /* 13983 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 13995 + /* 13990 */ MCD_OPC_Decode, + 255, + 9, + 174, + 1, // Opcode: MVE_VMLSDAVas8 + /* 13995 */ MCD_OPC_CheckPredicate, + 22, + 168, + 44, + 0, // Skip to: 25432 + /* 14000 */ MCD_OPC_Decode, + 170, + 12, + 175, + 1, // Opcode: MVE_VRMLSLDAVHas32 + /* 14005 */ MCD_OPC_FilterValue, + 1, + 158, + 44, + 0, // Skip to: 25432 + /* 14010 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14013 */ MCD_OPC_FilterValue, + 14, + 150, + 44, + 0, // Skip to: 25432 + /* 14018 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14035 + /* 14023 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14035 + /* 14030 */ MCD_OPC_Decode, + 254, + 9, + 174, + 1, // Opcode: MVE_VMLSDAVas32 + /* 14035 */ MCD_OPC_CheckPredicate, + 22, + 128, + 44, + 0, // Skip to: 25432 + /* 14040 */ MCD_OPC_Decode, + 138, + 10, + 175, + 1, // Opcode: MVE_VMLSLDAVas32 + /* 14045 */ MCD_OPC_FilterValue, + 1, + 118, + 44, + 0, // Skip to: 25432 + /* 14050 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 14053 */ MCD_OPC_FilterValue, + 0, + 67, + 0, + 0, // Skip to: 14125 + /* 14058 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14061 */ MCD_OPC_FilterValue, + 14, + 27, + 0, + 0, // Skip to: 14093 + /* 14066 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14083 + /* 14071 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14083 + /* 14078 */ MCD_OPC_Decode, + 128, + 10, + 174, + 1, // Opcode: MVE_VMLSDAVaxs16 + /* 14083 */ MCD_OPC_CheckPredicate, + 22, + 80, + 44, + 0, // Skip to: 25432 + /* 14088 */ MCD_OPC_Decode, + 139, + 10, + 175, + 1, // Opcode: MVE_VMLSLDAVaxs16 + /* 14093 */ MCD_OPC_FilterValue, + 15, + 70, + 44, + 0, // Skip to: 25432 + /* 14098 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14115 + /* 14103 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14115 + /* 14110 */ MCD_OPC_Decode, + 130, + 10, + 174, + 1, // Opcode: MVE_VMLSDAVaxs8 + /* 14115 */ MCD_OPC_CheckPredicate, + 22, + 48, + 44, + 0, // Skip to: 25432 + /* 14120 */ MCD_OPC_Decode, + 171, + 12, + 175, + 1, // Opcode: MVE_VRMLSLDAVHaxs32 + /* 14125 */ MCD_OPC_FilterValue, + 1, + 38, + 44, + 0, // Skip to: 25432 + /* 14130 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14133 */ MCD_OPC_FilterValue, + 14, + 30, + 44, + 0, // Skip to: 25432 + /* 14138 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14155 + /* 14143 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14155 + /* 14150 */ MCD_OPC_Decode, + 129, + 10, + 174, + 1, // Opcode: MVE_VMLSDAVaxs32 + /* 14155 */ MCD_OPC_CheckPredicate, + 22, + 8, + 44, + 0, // Skip to: 25432 + /* 14160 */ MCD_OPC_Decode, + 140, + 10, + 175, + 1, // Opcode: MVE_VMLSLDAVaxs32 + /* 14165 */ MCD_OPC_FilterValue, + 15, + 254, + 43, + 0, // Skip to: 25432 + /* 14170 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 14173 */ MCD_OPC_FilterValue, + 0, + 154, + 5, + 0, // Skip to: 15612 + /* 14178 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 14181 */ MCD_OPC_FilterValue, + 0, + 196, + 4, + 0, // Skip to: 15406 + /* 14186 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 14189 */ MCD_OPC_FilterValue, + 0, + 56, + 3, + 0, // Skip to: 15018 + /* 14194 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 14197 */ MCD_OPC_FilterValue, + 0, + 40, + 2, + 0, // Skip to: 14754 + /* 14202 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 14205 */ MCD_OPC_FilterValue, + 0, + 60, + 1, + 0, // Skip to: 14526 + /* 14210 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14213 */ MCD_OPC_FilterValue, + 14, + 190, + 0, + 0, // Skip to: 14408 + /* 14218 */ MCD_OPC_ExtractField, + 17, + 6, // Inst{22-17} ... + /* 14221 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 14236 + /* 14226 */ MCD_OPC_CheckPredicate, + 22, + 110, + 0, + 0, // Skip to: 14341 + /* 14231 */ MCD_OPC_Decode, + 161, + 9, + 176, + 1, // Opcode: MVE_VMAXAVs8 + /* 14236 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 14251 + /* 14241 */ MCD_OPC_CheckPredicate, + 22, + 95, + 0, + 0, // Skip to: 14341 + /* 14246 */ MCD_OPC_Decode, + 175, + 9, + 176, + 1, // Opcode: MVE_VMAXVs8 + /* 14251 */ MCD_OPC_FilterValue, + 50, + 10, + 0, + 0, // Skip to: 14266 + /* 14256 */ MCD_OPC_CheckPredicate, + 22, + 80, + 0, + 0, // Skip to: 14341 + /* 14261 */ MCD_OPC_Decode, + 159, + 9, + 176, + 1, // Opcode: MVE_VMAXAVs16 + /* 14266 */ MCD_OPC_FilterValue, + 51, + 10, + 0, + 0, // Skip to: 14281 + /* 14271 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 14341 + /* 14276 */ MCD_OPC_Decode, + 173, + 9, + 176, + 1, // Opcode: MVE_VMAXVs16 + /* 14281 */ MCD_OPC_FilterValue, + 52, + 10, + 0, + 0, // Skip to: 14296 + /* 14286 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 14341 + /* 14291 */ MCD_OPC_Decode, + 160, + 9, + 176, + 1, // Opcode: MVE_VMAXAVs32 + /* 14296 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 14311 + /* 14301 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 14341 + /* 14306 */ MCD_OPC_Decode, + 174, + 9, + 176, + 1, // Opcode: MVE_VMAXVs32 + /* 14311 */ MCD_OPC_FilterValue, + 54, + 10, + 0, + 0, // Skip to: 14326 + /* 14316 */ MCD_OPC_CheckPredicate, + 24, + 20, + 0, + 0, // Skip to: 14341 + /* 14321 */ MCD_OPC_Decode, + 166, + 9, + 176, + 1, // Opcode: MVE_VMAXNMAVf32 + /* 14326 */ MCD_OPC_FilterValue, + 55, + 10, + 0, + 0, // Skip to: 14341 + /* 14331 */ MCD_OPC_CheckPredicate, + 24, + 5, + 0, + 0, // Skip to: 14341 + /* 14336 */ MCD_OPC_Decode, + 170, + 9, + 176, + 1, // Opcode: MVE_VMAXNMVf32 + /* 14341 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 14344 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 14376 + /* 14349 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14366 + /* 14354 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14366 + /* 14361 */ MCD_OPC_Decode, + 222, + 9, + 172, + 1, // Opcode: MVE_VMLADAVs8 + /* 14366 */ MCD_OPC_CheckPredicate, + 22, + 53, + 43, + 0, // Skip to: 25432 + /* 14371 */ MCD_OPC_Decode, + 167, + 12, + 173, + 1, // Opcode: MVE_VRMLALDAVHs32 + /* 14376 */ MCD_OPC_FilterValue, + 1, + 43, + 43, + 0, // Skip to: 25432 + /* 14381 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14398 + /* 14386 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14398 + /* 14393 */ MCD_OPC_Decode, + 228, + 9, + 172, + 1, // Opcode: MVE_VMLADAVxs8 + /* 14398 */ MCD_OPC_CheckPredicate, + 22, + 21, + 43, + 0, // Skip to: 25432 + /* 14403 */ MCD_OPC_Decode, + 169, + 12, + 173, + 1, // Opcode: MVE_VRMLALDAVHxs32 + /* 14408 */ MCD_OPC_FilterValue, + 15, + 11, + 43, + 0, // Skip to: 25432 + /* 14413 */ MCD_OPC_ExtractField, + 17, + 6, // Inst{22-17} ... + /* 14416 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 14431 + /* 14421 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 14491 + /* 14426 */ MCD_OPC_Decode, + 178, + 9, + 176, + 1, // Opcode: MVE_VMAXVu8 + /* 14431 */ MCD_OPC_FilterValue, + 51, + 10, + 0, + 0, // Skip to: 14446 + /* 14436 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 14491 + /* 14441 */ MCD_OPC_Decode, + 176, + 9, + 176, + 1, // Opcode: MVE_VMAXVu16 + /* 14446 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 14461 + /* 14451 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 14491 + /* 14456 */ MCD_OPC_Decode, + 177, + 9, + 176, + 1, // Opcode: MVE_VMAXVu32 + /* 14461 */ MCD_OPC_FilterValue, + 54, + 10, + 0, + 0, // Skip to: 14476 + /* 14466 */ MCD_OPC_CheckPredicate, + 24, + 20, + 0, + 0, // Skip to: 14491 + /* 14471 */ MCD_OPC_Decode, + 165, + 9, + 176, + 1, // Opcode: MVE_VMAXNMAVf16 + /* 14476 */ MCD_OPC_FilterValue, + 55, + 10, + 0, + 0, // Skip to: 14491 + /* 14481 */ MCD_OPC_CheckPredicate, + 24, + 5, + 0, + 0, // Skip to: 14491 + /* 14486 */ MCD_OPC_Decode, + 169, + 9, + 176, + 1, // Opcode: MVE_VMAXNMVf16 + /* 14491 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 14494 */ MCD_OPC_FilterValue, + 0, + 181, + 42, + 0, // Skip to: 25432 + /* 14499 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14516 + /* 14504 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14516 + /* 14511 */ MCD_OPC_Decode, + 225, + 9, + 172, + 1, // Opcode: MVE_VMLADAVu8 + /* 14516 */ MCD_OPC_CheckPredicate, + 22, + 159, + 42, + 0, // Skip to: 25432 + /* 14521 */ MCD_OPC_Decode, + 168, + 12, + 173, + 1, // Opcode: MVE_VRMLALDAVHu32 + /* 14526 */ MCD_OPC_FilterValue, + 1, + 149, + 42, + 0, // Skip to: 25432 + /* 14531 */ MCD_OPC_ExtractField, + 17, + 3, // Inst{19-17} ... + /* 14534 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 14600 + /* 14539 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14542 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 14571 + /* 14547 */ MCD_OPC_CheckPredicate, + 22, + 128, + 42, + 0, // Skip to: 25432 + /* 14552 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 121, + 42, + 0, // Skip to: 25432 + /* 14559 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 114, + 42, + 0, // Skip to: 25432 + /* 14566 */ MCD_OPC_Decode, + 181, + 7, + 177, + 1, // Opcode: MVE_VADDVs8no_acc + /* 14571 */ MCD_OPC_FilterValue, + 15, + 104, + 42, + 0, // Skip to: 25432 + /* 14576 */ MCD_OPC_CheckPredicate, + 22, + 99, + 42, + 0, // Skip to: 25432 + /* 14581 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 92, + 42, + 0, // Skip to: 25432 + /* 14588 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 85, + 42, + 0, // Skip to: 25432 + /* 14595 */ MCD_OPC_Decode, + 187, + 7, + 177, + 1, // Opcode: MVE_VADDVu8no_acc + /* 14600 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 14666 + /* 14605 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14608 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 14637 + /* 14613 */ MCD_OPC_CheckPredicate, + 22, + 62, + 42, + 0, // Skip to: 25432 + /* 14618 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 55, + 42, + 0, // Skip to: 25432 + /* 14625 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 48, + 42, + 0, // Skip to: 25432 + /* 14632 */ MCD_OPC_Decode, + 177, + 7, + 177, + 1, // Opcode: MVE_VADDVs16no_acc + /* 14637 */ MCD_OPC_FilterValue, + 15, + 38, + 42, + 0, // Skip to: 25432 + /* 14642 */ MCD_OPC_CheckPredicate, + 22, + 33, + 42, + 0, // Skip to: 25432 + /* 14647 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 26, + 42, + 0, // Skip to: 25432 + /* 14654 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 19, + 42, + 0, // Skip to: 25432 + /* 14661 */ MCD_OPC_Decode, + 183, + 7, + 177, + 1, // Opcode: MVE_VADDVu16no_acc + /* 14666 */ MCD_OPC_FilterValue, + 4, + 9, + 42, + 0, // Skip to: 25432 + /* 14671 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14674 */ MCD_OPC_FilterValue, + 14, + 35, + 0, + 0, // Skip to: 14714 + /* 14679 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 14682 */ MCD_OPC_FilterValue, + 0, + 249, + 41, + 0, // Skip to: 25432 + /* 14687 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14704 + /* 14692 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14704 + /* 14699 */ MCD_OPC_Decode, + 179, + 7, + 177, + 1, // Opcode: MVE_VADDVs32no_acc + /* 14704 */ MCD_OPC_CheckPredicate, + 22, + 227, + 41, + 0, // Skip to: 25432 + /* 14709 */ MCD_OPC_Decode, + 173, + 7, + 178, + 1, // Opcode: MVE_VADDLVs32no_acc + /* 14714 */ MCD_OPC_FilterValue, + 15, + 217, + 41, + 0, // Skip to: 25432 + /* 14719 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 14722 */ MCD_OPC_FilterValue, + 0, + 209, + 41, + 0, // Skip to: 25432 + /* 14727 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 14744 + /* 14732 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 14744 + /* 14739 */ MCD_OPC_Decode, + 185, + 7, + 177, + 1, // Opcode: MVE_VADDVu32no_acc + /* 14744 */ MCD_OPC_CheckPredicate, + 22, + 187, + 41, + 0, // Skip to: 25432 + /* 14749 */ MCD_OPC_Decode, + 175, + 7, + 178, + 1, // Opcode: MVE_VADDLVu32no_acc + /* 14754 */ MCD_OPC_FilterValue, + 1, + 177, + 41, + 0, // Skip to: 25432 + /* 14759 */ MCD_OPC_ExtractField, + 16, + 7, // Inst{22-16} ... + /* 14762 */ MCD_OPC_FilterValue, + 96, + 17, + 0, + 0, // Skip to: 14784 + /* 14767 */ MCD_OPC_CheckPredicate, + 22, + 164, + 41, + 0, // Skip to: 25432 + /* 14772 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 157, + 41, + 0, // Skip to: 25432 + /* 14779 */ MCD_OPC_Decode, + 187, + 9, + 176, + 1, // Opcode: MVE_VMINAVs8 + /* 14784 */ MCD_OPC_FilterValue, + 98, + 33, + 0, + 0, // Skip to: 14822 + /* 14789 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14792 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14807 + /* 14797 */ MCD_OPC_CheckPredicate, + 22, + 134, + 41, + 0, // Skip to: 25432 + /* 14802 */ MCD_OPC_Decode, + 201, + 9, + 176, + 1, // Opcode: MVE_VMINVs8 + /* 14807 */ MCD_OPC_FilterValue, + 15, + 124, + 41, + 0, // Skip to: 25432 + /* 14812 */ MCD_OPC_CheckPredicate, + 22, + 119, + 41, + 0, // Skip to: 25432 + /* 14817 */ MCD_OPC_Decode, + 204, + 9, + 176, + 1, // Opcode: MVE_VMINVu8 + /* 14822 */ MCD_OPC_FilterValue, + 100, + 17, + 0, + 0, // Skip to: 14844 + /* 14827 */ MCD_OPC_CheckPredicate, + 22, + 104, + 41, + 0, // Skip to: 25432 + /* 14832 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 97, + 41, + 0, // Skip to: 25432 + /* 14839 */ MCD_OPC_Decode, + 185, + 9, + 176, + 1, // Opcode: MVE_VMINAVs16 + /* 14844 */ MCD_OPC_FilterValue, + 102, + 33, + 0, + 0, // Skip to: 14882 + /* 14849 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14852 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14867 + /* 14857 */ MCD_OPC_CheckPredicate, + 22, + 74, + 41, + 0, // Skip to: 25432 + /* 14862 */ MCD_OPC_Decode, + 199, + 9, + 176, + 1, // Opcode: MVE_VMINVs16 + /* 14867 */ MCD_OPC_FilterValue, + 15, + 64, + 41, + 0, // Skip to: 25432 + /* 14872 */ MCD_OPC_CheckPredicate, + 22, + 59, + 41, + 0, // Skip to: 25432 + /* 14877 */ MCD_OPC_Decode, + 202, + 9, + 176, + 1, // Opcode: MVE_VMINVu16 + /* 14882 */ MCD_OPC_FilterValue, + 104, + 17, + 0, + 0, // Skip to: 14904 + /* 14887 */ MCD_OPC_CheckPredicate, + 22, + 44, + 41, + 0, // Skip to: 25432 + /* 14892 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 37, + 41, + 0, // Skip to: 25432 + /* 14899 */ MCD_OPC_Decode, + 186, + 9, + 176, + 1, // Opcode: MVE_VMINAVs32 + /* 14904 */ MCD_OPC_FilterValue, + 106, + 33, + 0, + 0, // Skip to: 14942 + /* 14909 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14912 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14927 + /* 14917 */ MCD_OPC_CheckPredicate, + 22, + 14, + 41, + 0, // Skip to: 25432 + /* 14922 */ MCD_OPC_Decode, + 200, + 9, + 176, + 1, // Opcode: MVE_VMINVs32 + /* 14927 */ MCD_OPC_FilterValue, + 15, + 4, + 41, + 0, // Skip to: 25432 + /* 14932 */ MCD_OPC_CheckPredicate, + 22, + 255, + 40, + 0, // Skip to: 25432 + /* 14937 */ MCD_OPC_Decode, + 203, + 9, + 176, + 1, // Opcode: MVE_VMINVu32 + /* 14942 */ MCD_OPC_FilterValue, + 108, + 33, + 0, + 0, // Skip to: 14980 + /* 14947 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14950 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14965 + /* 14955 */ MCD_OPC_CheckPredicate, + 24, + 232, + 40, + 0, // Skip to: 25432 + /* 14960 */ MCD_OPC_Decode, + 192, + 9, + 176, + 1, // Opcode: MVE_VMINNMAVf32 + /* 14965 */ MCD_OPC_FilterValue, + 15, + 222, + 40, + 0, // Skip to: 25432 + /* 14970 */ MCD_OPC_CheckPredicate, + 24, + 217, + 40, + 0, // Skip to: 25432 + /* 14975 */ MCD_OPC_Decode, + 191, + 9, + 176, + 1, // Opcode: MVE_VMINNMAVf16 + /* 14980 */ MCD_OPC_FilterValue, + 110, + 207, + 40, + 0, // Skip to: 25432 + /* 14985 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 14988 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 15003 + /* 14993 */ MCD_OPC_CheckPredicate, + 24, + 194, + 40, + 0, // Skip to: 25432 + /* 14998 */ MCD_OPC_Decode, + 196, + 9, + 176, + 1, // Opcode: MVE_VMINNMVf32 + /* 15003 */ MCD_OPC_FilterValue, + 15, + 184, + 40, + 0, // Skip to: 25432 + /* 15008 */ MCD_OPC_CheckPredicate, + 24, + 179, + 40, + 0, // Skip to: 25432 + /* 15013 */ MCD_OPC_Decode, + 195, + 9, + 176, + 1, // Opcode: MVE_VMINNMVf16 + /* 15018 */ MCD_OPC_FilterValue, + 2, + 169, + 40, + 0, // Skip to: 25432 + /* 15023 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 15026 */ MCD_OPC_FilterValue, + 0, + 63, + 1, + 0, // Skip to: 15350 + /* 15031 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 15034 */ MCD_OPC_FilterValue, + 0, + 83, + 0, + 0, // Skip to: 15122 + /* 15039 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15042 */ MCD_OPC_FilterValue, + 14, + 35, + 0, + 0, // Skip to: 15082 + /* 15047 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15050 */ MCD_OPC_FilterValue, + 0, + 137, + 40, + 0, // Skip to: 25432 + /* 15055 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 15072 + /* 15060 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 15072 + /* 15067 */ MCD_OPC_Decode, + 213, + 9, + 174, + 1, // Opcode: MVE_VMLADAVas8 + /* 15072 */ MCD_OPC_CheckPredicate, + 22, + 115, + 40, + 0, // Skip to: 25432 + /* 15077 */ MCD_OPC_Decode, + 164, + 12, + 175, + 1, // Opcode: MVE_VRMLALDAVHas32 + /* 15082 */ MCD_OPC_FilterValue, + 15, + 105, + 40, + 0, // Skip to: 25432 + /* 15087 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15090 */ MCD_OPC_FilterValue, + 0, + 97, + 40, + 0, // Skip to: 25432 + /* 15095 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 15112 + /* 15100 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 15112 + /* 15107 */ MCD_OPC_Decode, + 216, + 9, + 174, + 1, // Opcode: MVE_VMLADAVau8 + /* 15112 */ MCD_OPC_CheckPredicate, + 22, + 75, + 40, + 0, // Skip to: 25432 + /* 15117 */ MCD_OPC_Decode, + 165, + 12, + 175, + 1, // Opcode: MVE_VRMLALDAVHau32 + /* 15122 */ MCD_OPC_FilterValue, + 1, + 65, + 40, + 0, // Skip to: 25432 + /* 15127 */ MCD_OPC_ExtractField, + 17, + 3, // Inst{19-17} ... + /* 15130 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 15196 + /* 15135 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15138 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15167 + /* 15143 */ MCD_OPC_CheckPredicate, + 22, + 44, + 40, + 0, // Skip to: 25432 + /* 15148 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 37, + 40, + 0, // Skip to: 25432 + /* 15155 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 30, + 40, + 0, // Skip to: 25432 + /* 15162 */ MCD_OPC_Decode, + 180, + 7, + 179, + 1, // Opcode: MVE_VADDVs8acc + /* 15167 */ MCD_OPC_FilterValue, + 15, + 20, + 40, + 0, // Skip to: 25432 + /* 15172 */ MCD_OPC_CheckPredicate, + 22, + 15, + 40, + 0, // Skip to: 25432 + /* 15177 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 8, + 40, + 0, // Skip to: 25432 + /* 15184 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 1, + 40, + 0, // Skip to: 25432 + /* 15191 */ MCD_OPC_Decode, + 186, + 7, + 179, + 1, // Opcode: MVE_VADDVu8acc + /* 15196 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 15262 + /* 15201 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15204 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15233 + /* 15209 */ MCD_OPC_CheckPredicate, + 22, + 234, + 39, + 0, // Skip to: 25432 + /* 15214 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 227, + 39, + 0, // Skip to: 25432 + /* 15221 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 220, + 39, + 0, // Skip to: 25432 + /* 15228 */ MCD_OPC_Decode, + 176, + 7, + 179, + 1, // Opcode: MVE_VADDVs16acc + /* 15233 */ MCD_OPC_FilterValue, + 15, + 210, + 39, + 0, // Skip to: 25432 + /* 15238 */ MCD_OPC_CheckPredicate, + 22, + 205, + 39, + 0, // Skip to: 25432 + /* 15243 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 198, + 39, + 0, // Skip to: 25432 + /* 15250 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 191, + 39, + 0, // Skip to: 25432 + /* 15257 */ MCD_OPC_Decode, + 182, + 7, + 179, + 1, // Opcode: MVE_VADDVu16acc + /* 15262 */ MCD_OPC_FilterValue, + 4, + 181, + 39, + 0, // Skip to: 25432 + /* 15267 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15270 */ MCD_OPC_FilterValue, + 14, + 35, + 0, + 0, // Skip to: 15310 + /* 15275 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15278 */ MCD_OPC_FilterValue, + 0, + 165, + 39, + 0, // Skip to: 25432 + /* 15283 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 15300 + /* 15288 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 15300 + /* 15295 */ MCD_OPC_Decode, + 178, + 7, + 179, + 1, // Opcode: MVE_VADDVs32acc + /* 15300 */ MCD_OPC_CheckPredicate, + 22, + 143, + 39, + 0, // Skip to: 25432 + /* 15305 */ MCD_OPC_Decode, + 172, + 7, + 180, + 1, // Opcode: MVE_VADDLVs32acc + /* 15310 */ MCD_OPC_FilterValue, + 15, + 133, + 39, + 0, // Skip to: 25432 + /* 15315 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15318 */ MCD_OPC_FilterValue, + 0, + 125, + 39, + 0, // Skip to: 25432 + /* 15323 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 15340 + /* 15328 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 15340 + /* 15335 */ MCD_OPC_Decode, + 184, + 7, + 179, + 1, // Opcode: MVE_VADDVu32acc + /* 15340 */ MCD_OPC_CheckPredicate, + 22, + 103, + 39, + 0, // Skip to: 25432 + /* 15345 */ MCD_OPC_Decode, + 174, + 7, + 180, + 1, // Opcode: MVE_VADDLVu32acc + /* 15350 */ MCD_OPC_FilterValue, + 1, + 93, + 39, + 0, // Skip to: 25432 + /* 15355 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15358 */ MCD_OPC_FilterValue, + 0, + 85, + 39, + 0, // Skip to: 25432 + /* 15363 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 15366 */ MCD_OPC_FilterValue, + 0, + 77, + 39, + 0, // Skip to: 25432 + /* 15371 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15374 */ MCD_OPC_FilterValue, + 14, + 69, + 39, + 0, // Skip to: 25432 + /* 15379 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 15396 + /* 15384 */ MCD_OPC_CheckField, + 20, + 3, + 7, + 5, + 0, + 0, // Skip to: 15396 + /* 15391 */ MCD_OPC_Decode, + 219, + 9, + 174, + 1, // Opcode: MVE_VMLADAVaxs8 + /* 15396 */ MCD_OPC_CheckPredicate, + 22, + 47, + 39, + 0, // Skip to: 25432 + /* 15401 */ MCD_OPC_Decode, + 166, + 12, + 175, + 1, // Opcode: MVE_VRMLALDAVHaxs32 + /* 15406 */ MCD_OPC_FilterValue, + 1, + 37, + 39, + 0, // Skip to: 25432 + /* 15411 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 15414 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 15480 + /* 15419 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15422 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15451 + /* 15427 */ MCD_OPC_CheckPredicate, + 22, + 16, + 39, + 0, // Skip to: 25432 + /* 15432 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 9, + 39, + 0, // Skip to: 25432 + /* 15439 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 2, + 39, + 0, // Skip to: 25432 + /* 15446 */ MCD_OPC_Decode, + 153, + 7, + 181, + 1, // Opcode: MVE_VABAVs8 + /* 15451 */ MCD_OPC_FilterValue, + 15, + 248, + 38, + 0, // Skip to: 25432 + /* 15456 */ MCD_OPC_CheckPredicate, + 22, + 243, + 38, + 0, // Skip to: 25432 + /* 15461 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 236, + 38, + 0, // Skip to: 25432 + /* 15468 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 229, + 38, + 0, // Skip to: 25432 + /* 15475 */ MCD_OPC_Decode, + 156, + 7, + 181, + 1, // Opcode: MVE_VABAVu8 + /* 15480 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 15546 + /* 15485 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15488 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15517 + /* 15493 */ MCD_OPC_CheckPredicate, + 22, + 206, + 38, + 0, // Skip to: 25432 + /* 15498 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 199, + 38, + 0, // Skip to: 25432 + /* 15505 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 192, + 38, + 0, // Skip to: 25432 + /* 15512 */ MCD_OPC_Decode, + 151, + 7, + 181, + 1, // Opcode: MVE_VABAVs16 + /* 15517 */ MCD_OPC_FilterValue, + 15, + 182, + 38, + 0, // Skip to: 25432 + /* 15522 */ MCD_OPC_CheckPredicate, + 22, + 177, + 38, + 0, // Skip to: 25432 + /* 15527 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 170, + 38, + 0, // Skip to: 25432 + /* 15534 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 163, + 38, + 0, // Skip to: 25432 + /* 15541 */ MCD_OPC_Decode, + 154, + 7, + 181, + 1, // Opcode: MVE_VABAVu16 + /* 15546 */ MCD_OPC_FilterValue, + 2, + 153, + 38, + 0, // Skip to: 25432 + /* 15551 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15554 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15583 + /* 15559 */ MCD_OPC_CheckPredicate, + 22, + 140, + 38, + 0, // Skip to: 25432 + /* 15564 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 133, + 38, + 0, // Skip to: 25432 + /* 15571 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 126, + 38, + 0, // Skip to: 25432 + /* 15578 */ MCD_OPC_Decode, + 152, + 7, + 181, + 1, // Opcode: MVE_VABAVs32 + /* 15583 */ MCD_OPC_FilterValue, + 15, + 116, + 38, + 0, // Skip to: 25432 + /* 15588 */ MCD_OPC_CheckPredicate, + 22, + 111, + 38, + 0, // Skip to: 25432 + /* 15593 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 104, + 38, + 0, // Skip to: 25432 + /* 15600 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 97, + 38, + 0, // Skip to: 25432 + /* 15607 */ MCD_OPC_Decode, + 155, + 7, + 181, + 1, // Opcode: MVE_VABAVu32 + /* 15612 */ MCD_OPC_FilterValue, + 1, + 87, + 38, + 0, // Skip to: 25432 + /* 15617 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 15620 */ MCD_OPC_FilterValue, + 0, + 219, + 3, + 0, // Skip to: 16612 + /* 15625 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15628 */ MCD_OPC_FilterValue, + 0, + 27, + 1, + 0, // Skip to: 15916 + /* 15633 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 15636 */ MCD_OPC_FilterValue, + 0, + 135, + 0, + 0, // Skip to: 15776 + /* 15641 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 15644 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 15710 + /* 15649 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15652 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15681 + /* 15657 */ MCD_OPC_CheckPredicate, + 22, + 42, + 38, + 0, // Skip to: 25432 + /* 15662 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 35, + 38, + 0, // Skip to: 25432 + /* 15669 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 28, + 38, + 0, // Skip to: 25432 + /* 15676 */ MCD_OPC_Decode, + 244, + 11, + 182, + 1, // Opcode: MVE_VQSHRNbhs16 + /* 15681 */ MCD_OPC_FilterValue, + 15, + 18, + 38, + 0, // Skip to: 25432 + /* 15686 */ MCD_OPC_CheckPredicate, + 22, + 13, + 38, + 0, // Skip to: 25432 + /* 15691 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 6, + 38, + 0, // Skip to: 25432 + /* 15698 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 255, + 37, + 0, // Skip to: 25432 + /* 15705 */ MCD_OPC_Decode, + 246, + 11, + 182, + 1, // Opcode: MVE_VQSHRNbhu16 + /* 15710 */ MCD_OPC_FilterValue, + 1, + 245, + 37, + 0, // Skip to: 25432 + /* 15715 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15718 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15747 + /* 15723 */ MCD_OPC_CheckPredicate, + 22, + 232, + 37, + 0, // Skip to: 25432 + /* 15728 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 225, + 37, + 0, // Skip to: 25432 + /* 15735 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 218, + 37, + 0, // Skip to: 25432 + /* 15742 */ MCD_OPC_Decode, + 248, + 11, + 182, + 1, // Opcode: MVE_VQSHRNths16 + /* 15747 */ MCD_OPC_FilterValue, + 15, + 208, + 37, + 0, // Skip to: 25432 + /* 15752 */ MCD_OPC_CheckPredicate, + 22, + 203, + 37, + 0, // Skip to: 25432 + /* 15757 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 196, + 37, + 0, // Skip to: 25432 + /* 15764 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 189, + 37, + 0, // Skip to: 25432 + /* 15771 */ MCD_OPC_Decode, + 250, + 11, + 182, + 1, // Opcode: MVE_VQSHRNthu16 + /* 15776 */ MCD_OPC_FilterValue, + 1, + 179, + 37, + 0, // Skip to: 25432 + /* 15781 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 15784 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 15850 + /* 15789 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15792 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15821 + /* 15797 */ MCD_OPC_CheckPredicate, + 22, + 158, + 37, + 0, // Skip to: 25432 + /* 15802 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 151, + 37, + 0, // Skip to: 25432 + /* 15809 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 144, + 37, + 0, // Skip to: 25432 + /* 15816 */ MCD_OPC_Decode, + 211, + 11, + 182, + 1, // Opcode: MVE_VQRSHRNbhs16 + /* 15821 */ MCD_OPC_FilterValue, + 15, + 134, + 37, + 0, // Skip to: 25432 + /* 15826 */ MCD_OPC_CheckPredicate, + 22, + 129, + 37, + 0, // Skip to: 25432 + /* 15831 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 122, + 37, + 0, // Skip to: 25432 + /* 15838 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 115, + 37, + 0, // Skip to: 25432 + /* 15845 */ MCD_OPC_Decode, + 213, + 11, + 182, + 1, // Opcode: MVE_VQRSHRNbhu16 + /* 15850 */ MCD_OPC_FilterValue, + 1, + 105, + 37, + 0, // Skip to: 25432 + /* 15855 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15858 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 15887 + /* 15863 */ MCD_OPC_CheckPredicate, + 22, + 92, + 37, + 0, // Skip to: 25432 + /* 15868 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 85, + 37, + 0, // Skip to: 25432 + /* 15875 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 78, + 37, + 0, // Skip to: 25432 + /* 15882 */ MCD_OPC_Decode, + 215, + 11, + 182, + 1, // Opcode: MVE_VQRSHRNths16 + /* 15887 */ MCD_OPC_FilterValue, + 15, + 68, + 37, + 0, // Skip to: 25432 + /* 15892 */ MCD_OPC_CheckPredicate, + 22, + 63, + 37, + 0, // Skip to: 25432 + /* 15897 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 56, + 37, + 0, // Skip to: 25432 + /* 15904 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 49, + 37, + 0, // Skip to: 25432 + /* 15911 */ MCD_OPC_Decode, + 217, + 11, + 182, + 1, // Opcode: MVE_VQRSHRNthu16 + /* 15916 */ MCD_OPC_FilterValue, + 1, + 227, + 0, + 0, // Skip to: 16148 + /* 15921 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 15924 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 16036 + /* 15929 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 15932 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 15984 + /* 15937 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15940 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 15962 + /* 15945 */ MCD_OPC_CheckPredicate, + 22, + 10, + 37, + 0, // Skip to: 25432 + /* 15950 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 3, + 37, + 0, // Skip to: 25432 + /* 15957 */ MCD_OPC_Decode, + 245, + 11, + 183, + 1, // Opcode: MVE_VQSHRNbhs32 + /* 15962 */ MCD_OPC_FilterValue, + 15, + 249, + 36, + 0, // Skip to: 25432 + /* 15967 */ MCD_OPC_CheckPredicate, + 22, + 244, + 36, + 0, // Skip to: 25432 + /* 15972 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 237, + 36, + 0, // Skip to: 25432 + /* 15979 */ MCD_OPC_Decode, + 247, + 11, + 183, + 1, // Opcode: MVE_VQSHRNbhu32 + /* 15984 */ MCD_OPC_FilterValue, + 1, + 227, + 36, + 0, // Skip to: 25432 + /* 15989 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 15992 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16014 + /* 15997 */ MCD_OPC_CheckPredicate, + 22, + 214, + 36, + 0, // Skip to: 25432 + /* 16002 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 207, + 36, + 0, // Skip to: 25432 + /* 16009 */ MCD_OPC_Decode, + 249, + 11, + 183, + 1, // Opcode: MVE_VQSHRNths32 + /* 16014 */ MCD_OPC_FilterValue, + 15, + 197, + 36, + 0, // Skip to: 25432 + /* 16019 */ MCD_OPC_CheckPredicate, + 22, + 192, + 36, + 0, // Skip to: 25432 + /* 16024 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 185, + 36, + 0, // Skip to: 25432 + /* 16031 */ MCD_OPC_Decode, + 251, + 11, + 183, + 1, // Opcode: MVE_VQSHRNthu32 + /* 16036 */ MCD_OPC_FilterValue, + 1, + 175, + 36, + 0, // Skip to: 25432 + /* 16041 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 16044 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 16096 + /* 16049 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16052 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16074 + /* 16057 */ MCD_OPC_CheckPredicate, + 22, + 154, + 36, + 0, // Skip to: 25432 + /* 16062 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 147, + 36, + 0, // Skip to: 25432 + /* 16069 */ MCD_OPC_Decode, + 212, + 11, + 183, + 1, // Opcode: MVE_VQRSHRNbhs32 + /* 16074 */ MCD_OPC_FilterValue, + 15, + 137, + 36, + 0, // Skip to: 25432 + /* 16079 */ MCD_OPC_CheckPredicate, + 22, + 132, + 36, + 0, // Skip to: 25432 + /* 16084 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 125, + 36, + 0, // Skip to: 25432 + /* 16091 */ MCD_OPC_Decode, + 214, + 11, + 183, + 1, // Opcode: MVE_VQRSHRNbhu32 + /* 16096 */ MCD_OPC_FilterValue, + 1, + 115, + 36, + 0, // Skip to: 25432 + /* 16101 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16104 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16126 + /* 16109 */ MCD_OPC_CheckPredicate, + 22, + 102, + 36, + 0, // Skip to: 25432 + /* 16114 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 95, + 36, + 0, // Skip to: 25432 + /* 16121 */ MCD_OPC_Decode, + 216, + 11, + 183, + 1, // Opcode: MVE_VQRSHRNths32 + /* 16126 */ MCD_OPC_FilterValue, + 15, + 85, + 36, + 0, // Skip to: 25432 + /* 16131 */ MCD_OPC_CheckPredicate, + 22, + 80, + 36, + 0, // Skip to: 25432 + /* 16136 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 73, + 36, + 0, // Skip to: 25432 + /* 16143 */ MCD_OPC_Decode, + 218, + 11, + 183, + 1, // Opcode: MVE_VQRSHRNthu32 + /* 16148 */ MCD_OPC_FilterValue, + 2, + 243, + 0, + 0, // Skip to: 16396 + /* 16153 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 16156 */ MCD_OPC_FilterValue, + 0, + 115, + 0, + 0, // Skip to: 16276 + /* 16161 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16164 */ MCD_OPC_FilterValue, + 14, + 51, + 0, + 0, // Skip to: 16220 + /* 16169 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16172 */ MCD_OPC_FilterValue, + 0, + 39, + 36, + 0, // Skip to: 25432 + /* 16177 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16180 */ MCD_OPC_FilterValue, + 0, + 31, + 36, + 0, // Skip to: 25432 + /* 16185 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 16188 */ MCD_OPC_FilterValue, + 1, + 23, + 36, + 0, // Skip to: 25432 + /* 16193 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16210 + /* 16198 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 16210 + /* 16205 */ MCD_OPC_Decode, + 147, + 10, + 145, + 1, // Opcode: MVE_VMOVLs8bh + /* 16210 */ MCD_OPC_CheckPredicate, + 22, + 1, + 36, + 0, // Skip to: 25432 + /* 16215 */ MCD_OPC_Decode, + 207, + 12, + 184, + 1, // Opcode: MVE_VSHLL_imms8bh + /* 16220 */ MCD_OPC_FilterValue, + 15, + 247, + 35, + 0, // Skip to: 25432 + /* 16225 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16228 */ MCD_OPC_FilterValue, + 0, + 239, + 35, + 0, // Skip to: 25432 + /* 16233 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16236 */ MCD_OPC_FilterValue, + 0, + 231, + 35, + 0, // Skip to: 25432 + /* 16241 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 16244 */ MCD_OPC_FilterValue, + 1, + 223, + 35, + 0, // Skip to: 25432 + /* 16249 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16266 + /* 16254 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 16266 + /* 16261 */ MCD_OPC_Decode, + 151, + 10, + 145, + 1, // Opcode: MVE_VMOVLu8bh + /* 16266 */ MCD_OPC_CheckPredicate, + 22, + 201, + 35, + 0, // Skip to: 25432 + /* 16271 */ MCD_OPC_Decode, + 211, + 12, + 184, + 1, // Opcode: MVE_VSHLL_immu8bh + /* 16276 */ MCD_OPC_FilterValue, + 1, + 191, + 35, + 0, // Skip to: 25432 + /* 16281 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16284 */ MCD_OPC_FilterValue, + 14, + 51, + 0, + 0, // Skip to: 16340 + /* 16289 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16292 */ MCD_OPC_FilterValue, + 0, + 175, + 35, + 0, // Skip to: 25432 + /* 16297 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16300 */ MCD_OPC_FilterValue, + 0, + 167, + 35, + 0, // Skip to: 25432 + /* 16305 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 16308 */ MCD_OPC_FilterValue, + 1, + 159, + 35, + 0, // Skip to: 25432 + /* 16313 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16330 + /* 16318 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 16330 + /* 16325 */ MCD_OPC_Decode, + 148, + 10, + 145, + 1, // Opcode: MVE_VMOVLs8th + /* 16330 */ MCD_OPC_CheckPredicate, + 22, + 137, + 35, + 0, // Skip to: 25432 + /* 16335 */ MCD_OPC_Decode, + 208, + 12, + 184, + 1, // Opcode: MVE_VSHLL_imms8th + /* 16340 */ MCD_OPC_FilterValue, + 15, + 127, + 35, + 0, // Skip to: 25432 + /* 16345 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16348 */ MCD_OPC_FilterValue, + 0, + 119, + 35, + 0, // Skip to: 25432 + /* 16353 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16356 */ MCD_OPC_FilterValue, + 0, + 111, + 35, + 0, // Skip to: 25432 + /* 16361 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 16364 */ MCD_OPC_FilterValue, + 1, + 103, + 35, + 0, // Skip to: 25432 + /* 16369 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16386 + /* 16374 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 16386 + /* 16381 */ MCD_OPC_Decode, + 152, + 10, + 145, + 1, // Opcode: MVE_VMOVLu8th + /* 16386 */ MCD_OPC_CheckPredicate, + 22, + 81, + 35, + 0, // Skip to: 25432 + /* 16391 */ MCD_OPC_Decode, + 212, + 12, + 184, + 1, // Opcode: MVE_VSHLL_immu8th + /* 16396 */ MCD_OPC_FilterValue, + 3, + 71, + 35, + 0, // Skip to: 25432 + /* 16401 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 16404 */ MCD_OPC_FilterValue, + 0, + 99, + 0, + 0, // Skip to: 16508 + /* 16409 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16412 */ MCD_OPC_FilterValue, + 14, + 43, + 0, + 0, // Skip to: 16460 + /* 16417 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16420 */ MCD_OPC_FilterValue, + 0, + 47, + 35, + 0, // Skip to: 25432 + /* 16425 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16428 */ MCD_OPC_FilterValue, + 0, + 39, + 35, + 0, // Skip to: 25432 + /* 16433 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16450 + /* 16438 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 16450 + /* 16445 */ MCD_OPC_Decode, + 145, + 10, + 145, + 1, // Opcode: MVE_VMOVLs16bh + /* 16450 */ MCD_OPC_CheckPredicate, + 22, + 17, + 35, + 0, // Skip to: 25432 + /* 16455 */ MCD_OPC_Decode, + 205, + 12, + 185, + 1, // Opcode: MVE_VSHLL_imms16bh + /* 16460 */ MCD_OPC_FilterValue, + 15, + 7, + 35, + 0, // Skip to: 25432 + /* 16465 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16468 */ MCD_OPC_FilterValue, + 0, + 255, + 34, + 0, // Skip to: 25432 + /* 16473 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16476 */ MCD_OPC_FilterValue, + 0, + 247, + 34, + 0, // Skip to: 25432 + /* 16481 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16498 + /* 16486 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 16498 + /* 16493 */ MCD_OPC_Decode, + 149, + 10, + 145, + 1, // Opcode: MVE_VMOVLu16bh + /* 16498 */ MCD_OPC_CheckPredicate, + 22, + 225, + 34, + 0, // Skip to: 25432 + /* 16503 */ MCD_OPC_Decode, + 209, + 12, + 185, + 1, // Opcode: MVE_VSHLL_immu16bh + /* 16508 */ MCD_OPC_FilterValue, + 1, + 215, + 34, + 0, // Skip to: 25432 + /* 16513 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16516 */ MCD_OPC_FilterValue, + 14, + 43, + 0, + 0, // Skip to: 16564 + /* 16521 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16524 */ MCD_OPC_FilterValue, + 0, + 199, + 34, + 0, // Skip to: 25432 + /* 16529 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16532 */ MCD_OPC_FilterValue, + 0, + 191, + 34, + 0, // Skip to: 25432 + /* 16537 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16554 + /* 16542 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 16554 + /* 16549 */ MCD_OPC_Decode, + 146, + 10, + 145, + 1, // Opcode: MVE_VMOVLs16th + /* 16554 */ MCD_OPC_CheckPredicate, + 22, + 169, + 34, + 0, // Skip to: 25432 + /* 16559 */ MCD_OPC_Decode, + 206, + 12, + 185, + 1, // Opcode: MVE_VSHLL_imms16th + /* 16564 */ MCD_OPC_FilterValue, + 15, + 159, + 34, + 0, // Skip to: 25432 + /* 16569 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16572 */ MCD_OPC_FilterValue, + 0, + 151, + 34, + 0, // Skip to: 25432 + /* 16577 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 16580 */ MCD_OPC_FilterValue, + 0, + 143, + 34, + 0, // Skip to: 25432 + /* 16585 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 16602 + /* 16590 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 16602 + /* 16597 */ MCD_OPC_Decode, + 150, + 10, + 145, + 1, // Opcode: MVE_VMOVLu16th + /* 16602 */ MCD_OPC_CheckPredicate, + 22, + 121, + 34, + 0, // Skip to: 25432 + /* 16607 */ MCD_OPC_Decode, + 210, + 12, + 185, + 1, // Opcode: MVE_VSHLL_immu16th + /* 16612 */ MCD_OPC_FilterValue, + 1, + 111, + 34, + 0, // Skip to: 25432 + /* 16617 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 16620 */ MCD_OPC_FilterValue, + 0, + 36, + 1, + 0, // Skip to: 16917 + /* 16625 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 16628 */ MCD_OPC_FilterValue, + 0, + 255, + 0, + 0, // Skip to: 16888 + /* 16633 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16636 */ MCD_OPC_FilterValue, + 0, + 121, + 0, + 0, // Skip to: 16762 + /* 16641 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 16644 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 16710 + /* 16649 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16652 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 16681 + /* 16657 */ MCD_OPC_CheckPredicate, + 22, + 66, + 34, + 0, // Skip to: 25432 + /* 16662 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 59, + 34, + 0, // Skip to: 25432 + /* 16669 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 52, + 34, + 0, // Skip to: 25432 + /* 16676 */ MCD_OPC_Decode, + 252, + 11, + 182, + 1, // Opcode: MVE_VQSHRUNs16bh + /* 16681 */ MCD_OPC_FilterValue, + 15, + 42, + 34, + 0, // Skip to: 25432 + /* 16686 */ MCD_OPC_CheckPredicate, + 22, + 37, + 34, + 0, // Skip to: 25432 + /* 16691 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 30, + 34, + 0, // Skip to: 25432 + /* 16698 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 23, + 34, + 0, // Skip to: 25432 + /* 16705 */ MCD_OPC_Decode, + 219, + 11, + 182, + 1, // Opcode: MVE_VQRSHRUNs16bh + /* 16710 */ MCD_OPC_FilterValue, + 1, + 13, + 34, + 0, // Skip to: 25432 + /* 16715 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16718 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16740 + /* 16723 */ MCD_OPC_CheckPredicate, + 22, + 0, + 34, + 0, // Skip to: 25432 + /* 16728 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 249, + 33, + 0, // Skip to: 25432 + /* 16735 */ MCD_OPC_Decode, + 254, + 11, + 183, + 1, // Opcode: MVE_VQSHRUNs32bh + /* 16740 */ MCD_OPC_FilterValue, + 15, + 239, + 33, + 0, // Skip to: 25432 + /* 16745 */ MCD_OPC_CheckPredicate, + 22, + 234, + 33, + 0, // Skip to: 25432 + /* 16750 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 227, + 33, + 0, // Skip to: 25432 + /* 16757 */ MCD_OPC_Decode, + 221, + 11, + 183, + 1, // Opcode: MVE_VQRSHRUNs32bh + /* 16762 */ MCD_OPC_FilterValue, + 1, + 217, + 33, + 0, // Skip to: 25432 + /* 16767 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 16770 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 16836 + /* 16775 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16778 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 16807 + /* 16783 */ MCD_OPC_CheckPredicate, + 22, + 196, + 33, + 0, // Skip to: 25432 + /* 16788 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 189, + 33, + 0, // Skip to: 25432 + /* 16795 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 182, + 33, + 0, // Skip to: 25432 + /* 16802 */ MCD_OPC_Decode, + 236, + 12, + 182, + 1, // Opcode: MVE_VSHRNi16bh + /* 16807 */ MCD_OPC_FilterValue, + 15, + 172, + 33, + 0, // Skip to: 25432 + /* 16812 */ MCD_OPC_CheckPredicate, + 22, + 167, + 33, + 0, // Skip to: 25432 + /* 16817 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 160, + 33, + 0, // Skip to: 25432 + /* 16824 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 153, + 33, + 0, // Skip to: 25432 + /* 16831 */ MCD_OPC_Decode, + 192, + 12, + 182, + 1, // Opcode: MVE_VRSHRNi16bh + /* 16836 */ MCD_OPC_FilterValue, + 1, + 143, + 33, + 0, // Skip to: 25432 + /* 16841 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16844 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16866 + /* 16849 */ MCD_OPC_CheckPredicate, + 22, + 130, + 33, + 0, // Skip to: 25432 + /* 16854 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 123, + 33, + 0, // Skip to: 25432 + /* 16861 */ MCD_OPC_Decode, + 238, + 12, + 183, + 1, // Opcode: MVE_VSHRNi32bh + /* 16866 */ MCD_OPC_FilterValue, + 15, + 113, + 33, + 0, // Skip to: 25432 + /* 16871 */ MCD_OPC_CheckPredicate, + 22, + 108, + 33, + 0, // Skip to: 25432 + /* 16876 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 101, + 33, + 0, // Skip to: 25432 + /* 16883 */ MCD_OPC_Decode, + 194, + 12, + 183, + 1, // Opcode: MVE_VRSHRNi32bh + /* 16888 */ MCD_OPC_FilterValue, + 1, + 91, + 33, + 0, // Skip to: 25432 + /* 16893 */ MCD_OPC_CheckPredicate, + 22, + 86, + 33, + 0, // Skip to: 25432 + /* 16898 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 79, + 33, + 0, // Skip to: 25432 + /* 16905 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 72, + 33, + 0, // Skip to: 25432 + /* 16912 */ MCD_OPC_Decode, + 204, + 12, + 186, + 1, // Opcode: MVE_VSHLC + /* 16917 */ MCD_OPC_FilterValue, + 1, + 62, + 33, + 0, // Skip to: 25432 + /* 16922 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 16925 */ MCD_OPC_FilterValue, + 0, + 121, + 0, + 0, // Skip to: 17051 + /* 16930 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16933 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 16999 + /* 16938 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 16941 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 16970 + /* 16946 */ MCD_OPC_CheckPredicate, + 22, + 33, + 33, + 0, // Skip to: 25432 + /* 16951 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 26, + 33, + 0, // Skip to: 25432 + /* 16958 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 19, + 33, + 0, // Skip to: 25432 + /* 16965 */ MCD_OPC_Decode, + 253, + 11, + 182, + 1, // Opcode: MVE_VQSHRUNs16th + /* 16970 */ MCD_OPC_FilterValue, + 15, + 9, + 33, + 0, // Skip to: 25432 + /* 16975 */ MCD_OPC_CheckPredicate, + 22, + 4, + 33, + 0, // Skip to: 25432 + /* 16980 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 253, + 32, + 0, // Skip to: 25432 + /* 16987 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 246, + 32, + 0, // Skip to: 25432 + /* 16994 */ MCD_OPC_Decode, + 220, + 11, + 182, + 1, // Opcode: MVE_VQRSHRUNs16th + /* 16999 */ MCD_OPC_FilterValue, + 1, + 236, + 32, + 0, // Skip to: 25432 + /* 17004 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17007 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 17029 + /* 17012 */ MCD_OPC_CheckPredicate, + 22, + 223, + 32, + 0, // Skip to: 25432 + /* 17017 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 216, + 32, + 0, // Skip to: 25432 + /* 17024 */ MCD_OPC_Decode, + 255, + 11, + 183, + 1, // Opcode: MVE_VQSHRUNs32th + /* 17029 */ MCD_OPC_FilterValue, + 15, + 206, + 32, + 0, // Skip to: 25432 + /* 17034 */ MCD_OPC_CheckPredicate, + 22, + 201, + 32, + 0, // Skip to: 25432 + /* 17039 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 194, + 32, + 0, // Skip to: 25432 + /* 17046 */ MCD_OPC_Decode, + 222, + 11, + 183, + 1, // Opcode: MVE_VQRSHRUNs32th + /* 17051 */ MCD_OPC_FilterValue, + 1, + 184, + 32, + 0, // Skip to: 25432 + /* 17056 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 17059 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 17125 + /* 17064 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17067 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 17096 + /* 17072 */ MCD_OPC_CheckPredicate, + 22, + 163, + 32, + 0, // Skip to: 25432 + /* 17077 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 156, + 32, + 0, // Skip to: 25432 + /* 17084 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 149, + 32, + 0, // Skip to: 25432 + /* 17091 */ MCD_OPC_Decode, + 237, + 12, + 182, + 1, // Opcode: MVE_VSHRNi16th + /* 17096 */ MCD_OPC_FilterValue, + 15, + 139, + 32, + 0, // Skip to: 25432 + /* 17101 */ MCD_OPC_CheckPredicate, + 22, + 134, + 32, + 0, // Skip to: 25432 + /* 17106 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 127, + 32, + 0, // Skip to: 25432 + /* 17113 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 120, + 32, + 0, // Skip to: 25432 + /* 17120 */ MCD_OPC_Decode, + 193, + 12, + 182, + 1, // Opcode: MVE_VRSHRNi16th + /* 17125 */ MCD_OPC_FilterValue, + 1, + 110, + 32, + 0, // Skip to: 25432 + /* 17130 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17133 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 17155 + /* 17138 */ MCD_OPC_CheckPredicate, + 22, + 97, + 32, + 0, // Skip to: 25432 + /* 17143 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 90, + 32, + 0, // Skip to: 25432 + /* 17150 */ MCD_OPC_Decode, + 239, + 12, + 183, + 1, // Opcode: MVE_VSHRNi32th + /* 17155 */ MCD_OPC_FilterValue, + 15, + 80, + 32, + 0, // Skip to: 25432 + /* 17160 */ MCD_OPC_CheckPredicate, + 22, + 75, + 32, + 0, // Skip to: 25432 + /* 17165 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 68, + 32, + 0, // Skip to: 25432 + /* 17172 */ MCD_OPC_Decode, + 195, + 12, + 183, + 1, // Opcode: MVE_VRSHRNi32th + /* 17177 */ MCD_OPC_FilterValue, + 2, + 15, + 19, + 0, // Skip to: 22061 + /* 17182 */ MCD_OPC_ExtractField, + 8, + 5, // Inst{12-8} ... + /* 17185 */ MCD_OPC_FilterValue, + 0, + 251, + 1, + 0, // Skip to: 17697 + /* 17190 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 17193 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 17361 + /* 17198 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17201 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17281 + /* 17206 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17209 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17245 + /* 17214 */ MCD_OPC_CheckPredicate, + 22, + 21, + 32, + 0, // Skip to: 25432 + /* 17219 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 14, + 32, + 0, // Skip to: 25432 + /* 17226 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 7, + 32, + 0, // Skip to: 25432 + /* 17233 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 0, + 32, + 0, // Skip to: 25432 + /* 17240 */ MCD_OPC_Decode, + 180, + 8, + 141, + 1, // Opcode: MVE_VHADDs8 + /* 17245 */ MCD_OPC_FilterValue, + 15, + 246, + 31, + 0, // Skip to: 25432 + /* 17250 */ MCD_OPC_CheckPredicate, + 22, + 241, + 31, + 0, // Skip to: 25432 + /* 17255 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 234, + 31, + 0, // Skip to: 25432 + /* 17262 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 227, + 31, + 0, // Skip to: 25432 + /* 17269 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 220, + 31, + 0, // Skip to: 25432 + /* 17276 */ MCD_OPC_Decode, + 183, + 8, + 141, + 1, // Opcode: MVE_VHADDu8 + /* 17281 */ MCD_OPC_FilterValue, + 1, + 210, + 31, + 0, // Skip to: 25432 + /* 17286 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17289 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17325 + /* 17294 */ MCD_OPC_CheckPredicate, + 22, + 197, + 31, + 0, // Skip to: 25432 + /* 17299 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 190, + 31, + 0, // Skip to: 25432 + /* 17306 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 183, + 31, + 0, // Skip to: 25432 + /* 17313 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 176, + 31, + 0, // Skip to: 25432 + /* 17320 */ MCD_OPC_Decode, + 252, + 10, + 141, + 1, // Opcode: MVE_VQADDs8 + /* 17325 */ MCD_OPC_FilterValue, + 15, + 166, + 31, + 0, // Skip to: 25432 + /* 17330 */ MCD_OPC_CheckPredicate, + 22, + 161, + 31, + 0, // Skip to: 25432 + /* 17335 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 154, + 31, + 0, // Skip to: 25432 + /* 17342 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 147, + 31, + 0, // Skip to: 25432 + /* 17349 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 140, + 31, + 0, // Skip to: 25432 + /* 17356 */ MCD_OPC_Decode, + 255, + 10, + 141, + 1, // Opcode: MVE_VQADDu8 + /* 17361 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 17529 + /* 17366 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17369 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17449 + /* 17374 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17377 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17413 + /* 17382 */ MCD_OPC_CheckPredicate, + 22, + 109, + 31, + 0, // Skip to: 25432 + /* 17387 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 102, + 31, + 0, // Skip to: 25432 + /* 17394 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 95, + 31, + 0, // Skip to: 25432 + /* 17401 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 88, + 31, + 0, // Skip to: 25432 + /* 17408 */ MCD_OPC_Decode, + 178, + 8, + 141, + 1, // Opcode: MVE_VHADDs16 + /* 17413 */ MCD_OPC_FilterValue, + 15, + 78, + 31, + 0, // Skip to: 25432 + /* 17418 */ MCD_OPC_CheckPredicate, + 22, + 73, + 31, + 0, // Skip to: 25432 + /* 17423 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 66, + 31, + 0, // Skip to: 25432 + /* 17430 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 59, + 31, + 0, // Skip to: 25432 + /* 17437 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 52, + 31, + 0, // Skip to: 25432 + /* 17444 */ MCD_OPC_Decode, + 181, + 8, + 141, + 1, // Opcode: MVE_VHADDu16 + /* 17449 */ MCD_OPC_FilterValue, + 1, + 42, + 31, + 0, // Skip to: 25432 + /* 17454 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17457 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17493 + /* 17462 */ MCD_OPC_CheckPredicate, + 22, + 29, + 31, + 0, // Skip to: 25432 + /* 17467 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 22, + 31, + 0, // Skip to: 25432 + /* 17474 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 15, + 31, + 0, // Skip to: 25432 + /* 17481 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 8, + 31, + 0, // Skip to: 25432 + /* 17488 */ MCD_OPC_Decode, + 250, + 10, + 141, + 1, // Opcode: MVE_VQADDs16 + /* 17493 */ MCD_OPC_FilterValue, + 15, + 254, + 30, + 0, // Skip to: 25432 + /* 17498 */ MCD_OPC_CheckPredicate, + 22, + 249, + 30, + 0, // Skip to: 25432 + /* 17503 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 242, + 30, + 0, // Skip to: 25432 + /* 17510 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 235, + 30, + 0, // Skip to: 25432 + /* 17517 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 228, + 30, + 0, // Skip to: 25432 + /* 17524 */ MCD_OPC_Decode, + 253, + 10, + 141, + 1, // Opcode: MVE_VQADDu16 + /* 17529 */ MCD_OPC_FilterValue, + 2, + 218, + 30, + 0, // Skip to: 25432 + /* 17534 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17537 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17617 + /* 17542 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17545 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17581 + /* 17550 */ MCD_OPC_CheckPredicate, + 22, + 197, + 30, + 0, // Skip to: 25432 + /* 17555 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 190, + 30, + 0, // Skip to: 25432 + /* 17562 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 183, + 30, + 0, // Skip to: 25432 + /* 17569 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 176, + 30, + 0, // Skip to: 25432 + /* 17576 */ MCD_OPC_Decode, + 179, + 8, + 141, + 1, // Opcode: MVE_VHADDs32 + /* 17581 */ MCD_OPC_FilterValue, + 15, + 166, + 30, + 0, // Skip to: 25432 + /* 17586 */ MCD_OPC_CheckPredicate, + 22, + 161, + 30, + 0, // Skip to: 25432 + /* 17591 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 154, + 30, + 0, // Skip to: 25432 + /* 17598 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 147, + 30, + 0, // Skip to: 25432 + /* 17605 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 140, + 30, + 0, // Skip to: 25432 + /* 17612 */ MCD_OPC_Decode, + 182, + 8, + 141, + 1, // Opcode: MVE_VHADDu32 + /* 17617 */ MCD_OPC_FilterValue, + 1, + 130, + 30, + 0, // Skip to: 25432 + /* 17622 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17625 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17661 + /* 17630 */ MCD_OPC_CheckPredicate, + 22, + 117, + 30, + 0, // Skip to: 25432 + /* 17635 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 110, + 30, + 0, // Skip to: 25432 + /* 17642 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 103, + 30, + 0, // Skip to: 25432 + /* 17649 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 96, + 30, + 0, // Skip to: 25432 + /* 17656 */ MCD_OPC_Decode, + 251, + 10, + 141, + 1, // Opcode: MVE_VQADDs32 + /* 17661 */ MCD_OPC_FilterValue, + 15, + 86, + 30, + 0, // Skip to: 25432 + /* 17666 */ MCD_OPC_CheckPredicate, + 22, + 81, + 30, + 0, // Skip to: 25432 + /* 17671 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 74, + 30, + 0, // Skip to: 25432 + /* 17678 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 67, + 30, + 0, // Skip to: 25432 + /* 17685 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 60, + 30, + 0, // Skip to: 25432 + /* 17692 */ MCD_OPC_Decode, + 254, + 10, + 141, + 1, // Opcode: MVE_VQADDu32 + /* 17697 */ MCD_OPC_FilterValue, + 1, + 227, + 1, + 0, // Skip to: 18185 + /* 17702 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 17705 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 17873 + /* 17710 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17713 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17793 + /* 17718 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17721 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17757 + /* 17726 */ MCD_OPC_CheckPredicate, + 22, + 21, + 30, + 0, // Skip to: 25432 + /* 17731 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 14, + 30, + 0, // Skip to: 25432 + /* 17738 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 7, + 30, + 0, // Skip to: 25432 + /* 17745 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 0, + 30, + 0, // Skip to: 25432 + /* 17752 */ MCD_OPC_Decode, + 148, + 12, + 141, + 1, // Opcode: MVE_VRHADDs8 + /* 17757 */ MCD_OPC_FilterValue, + 15, + 246, + 29, + 0, // Skip to: 25432 + /* 17762 */ MCD_OPC_CheckPredicate, + 22, + 241, + 29, + 0, // Skip to: 25432 + /* 17767 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 234, + 29, + 0, // Skip to: 25432 + /* 17774 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 227, + 29, + 0, // Skip to: 25432 + /* 17781 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 220, + 29, + 0, // Skip to: 25432 + /* 17788 */ MCD_OPC_Decode, + 151, + 12, + 141, + 1, // Opcode: MVE_VRHADDu8 + /* 17793 */ MCD_OPC_FilterValue, + 1, + 210, + 29, + 0, // Skip to: 25432 + /* 17798 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17801 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17837 + /* 17806 */ MCD_OPC_CheckPredicate, + 22, + 197, + 29, + 0, // Skip to: 25432 + /* 17811 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 190, + 29, + 0, // Skip to: 25432 + /* 17818 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 183, + 29, + 0, // Skip to: 25432 + /* 17825 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 176, + 29, + 0, // Skip to: 25432 + /* 17832 */ MCD_OPC_Decode, + 198, + 7, + 141, + 1, // Opcode: MVE_VAND + /* 17837 */ MCD_OPC_FilterValue, + 15, + 166, + 29, + 0, // Skip to: 25432 + /* 17842 */ MCD_OPC_CheckPredicate, + 22, + 161, + 29, + 0, // Skip to: 25432 + /* 17847 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 154, + 29, + 0, // Skip to: 25432 + /* 17854 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 147, + 29, + 0, // Skip to: 25432 + /* 17861 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 140, + 29, + 0, // Skip to: 25432 + /* 17868 */ MCD_OPC_Decode, + 163, + 8, + 141, + 1, // Opcode: MVE_VEOR + /* 17873 */ MCD_OPC_FilterValue, + 1, + 126, + 0, + 0, // Skip to: 18004 + /* 17878 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 17881 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 17961 + /* 17886 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 17889 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 17925 + /* 17894 */ MCD_OPC_CheckPredicate, + 22, + 109, + 29, + 0, // Skip to: 25432 + /* 17899 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 102, + 29, + 0, // Skip to: 25432 + /* 17906 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 95, + 29, + 0, // Skip to: 25432 + /* 17913 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 88, + 29, + 0, // Skip to: 25432 + /* 17920 */ MCD_OPC_Decode, + 146, + 12, + 141, + 1, // Opcode: MVE_VRHADDs16 + /* 17925 */ MCD_OPC_FilterValue, + 15, + 78, + 29, + 0, // Skip to: 25432 + /* 17930 */ MCD_OPC_CheckPredicate, + 22, + 73, + 29, + 0, // Skip to: 25432 + /* 17935 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 66, + 29, + 0, // Skip to: 25432 + /* 17942 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 59, + 29, + 0, // Skip to: 25432 + /* 17949 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 52, + 29, + 0, // Skip to: 25432 + /* 17956 */ MCD_OPC_Decode, + 149, + 12, + 141, + 1, // Opcode: MVE_VRHADDu16 + /* 17961 */ MCD_OPC_FilterValue, + 1, + 42, + 29, + 0, // Skip to: 25432 + /* 17966 */ MCD_OPC_CheckPredicate, + 22, + 37, + 29, + 0, // Skip to: 25432 + /* 17971 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 30, + 29, + 0, // Skip to: 25432 + /* 17978 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 23, + 29, + 0, // Skip to: 25432 + /* 17985 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 16, + 29, + 0, // Skip to: 25432 + /* 17992 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 9, + 29, + 0, // Skip to: 25432 + /* 17999 */ MCD_OPC_Decode, + 199, + 7, + 141, + 1, // Opcode: MVE_VBIC + /* 18004 */ MCD_OPC_FilterValue, + 2, + 126, + 0, + 0, // Skip to: 18135 + /* 18009 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18012 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18092 + /* 18017 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18020 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18056 + /* 18025 */ MCD_OPC_CheckPredicate, + 22, + 234, + 28, + 0, // Skip to: 25432 + /* 18030 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 227, + 28, + 0, // Skip to: 25432 + /* 18037 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 220, + 28, + 0, // Skip to: 25432 + /* 18044 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 213, + 28, + 0, // Skip to: 25432 + /* 18051 */ MCD_OPC_Decode, + 147, + 12, + 141, + 1, // Opcode: MVE_VRHADDs32 + /* 18056 */ MCD_OPC_FilterValue, + 15, + 203, + 28, + 0, // Skip to: 25432 + /* 18061 */ MCD_OPC_CheckPredicate, + 22, + 198, + 28, + 0, // Skip to: 25432 + /* 18066 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 191, + 28, + 0, // Skip to: 25432 + /* 18073 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 184, + 28, + 0, // Skip to: 25432 + /* 18080 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 177, + 28, + 0, // Skip to: 25432 + /* 18087 */ MCD_OPC_Decode, + 150, + 12, + 141, + 1, // Opcode: MVE_VRHADDu32 + /* 18092 */ MCD_OPC_FilterValue, + 1, + 167, + 28, + 0, // Skip to: 25432 + /* 18097 */ MCD_OPC_CheckPredicate, + 22, + 162, + 28, + 0, // Skip to: 25432 + /* 18102 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 155, + 28, + 0, // Skip to: 25432 + /* 18109 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 148, + 28, + 0, // Skip to: 25432 + /* 18116 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 141, + 28, + 0, // Skip to: 25432 + /* 18123 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 134, + 28, + 0, // Skip to: 25432 + /* 18130 */ MCD_OPC_Decode, + 213, + 10, + 141, + 1, // Opcode: MVE_VORR + /* 18135 */ MCD_OPC_FilterValue, + 3, + 124, + 28, + 0, // Skip to: 25432 + /* 18140 */ MCD_OPC_CheckPredicate, + 22, + 119, + 28, + 0, // Skip to: 25432 + /* 18145 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 112, + 28, + 0, // Skip to: 25432 + /* 18152 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 105, + 28, + 0, // Skip to: 25432 + /* 18159 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 98, + 28, + 0, // Skip to: 25432 + /* 18166 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 91, + 28, + 0, // Skip to: 25432 + /* 18173 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 28, + 0, // Skip to: 25432 + /* 18180 */ MCD_OPC_Decode, + 212, + 10, + 141, + 1, // Opcode: MVE_VORN + /* 18185 */ MCD_OPC_FilterValue, + 2, + 251, + 1, + 0, // Skip to: 18697 + /* 18190 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 18193 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 18361 + /* 18198 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18201 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18281 + /* 18206 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18209 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18245 + /* 18214 */ MCD_OPC_CheckPredicate, + 22, + 45, + 28, + 0, // Skip to: 25432 + /* 18219 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 38, + 28, + 0, // Skip to: 25432 + /* 18226 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 28, + 0, // Skip to: 25432 + /* 18233 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 24, + 28, + 0, // Skip to: 25432 + /* 18240 */ MCD_OPC_Decode, + 195, + 8, + 141, + 1, // Opcode: MVE_VHSUBs8 + /* 18245 */ MCD_OPC_FilterValue, + 15, + 14, + 28, + 0, // Skip to: 25432 + /* 18250 */ MCD_OPC_CheckPredicate, + 22, + 9, + 28, + 0, // Skip to: 25432 + /* 18255 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 2, + 28, + 0, // Skip to: 25432 + /* 18262 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 251, + 27, + 0, // Skip to: 25432 + /* 18269 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 244, + 27, + 0, // Skip to: 25432 + /* 18276 */ MCD_OPC_Decode, + 198, + 8, + 141, + 1, // Opcode: MVE_VHSUBu8 + /* 18281 */ MCD_OPC_FilterValue, + 1, + 234, + 27, + 0, // Skip to: 25432 + /* 18286 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18289 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18325 + /* 18294 */ MCD_OPC_CheckPredicate, + 22, + 221, + 27, + 0, // Skip to: 25432 + /* 18299 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 27, + 0, // Skip to: 25432 + /* 18306 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 27, + 0, // Skip to: 25432 + /* 18313 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 27, + 0, // Skip to: 25432 + /* 18320 */ MCD_OPC_Decode, + 136, + 12, + 141, + 1, // Opcode: MVE_VQSUBs8 + /* 18325 */ MCD_OPC_FilterValue, + 15, + 190, + 27, + 0, // Skip to: 25432 + /* 18330 */ MCD_OPC_CheckPredicate, + 22, + 185, + 27, + 0, // Skip to: 25432 + /* 18335 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 27, + 0, // Skip to: 25432 + /* 18342 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 27, + 0, // Skip to: 25432 + /* 18349 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 27, + 0, // Skip to: 25432 + /* 18356 */ MCD_OPC_Decode, + 139, + 12, + 141, + 1, // Opcode: MVE_VQSUBu8 + /* 18361 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 18529 + /* 18366 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18369 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18449 + /* 18374 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18377 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18413 + /* 18382 */ MCD_OPC_CheckPredicate, + 22, + 133, + 27, + 0, // Skip to: 25432 + /* 18387 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 126, + 27, + 0, // Skip to: 25432 + /* 18394 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 119, + 27, + 0, // Skip to: 25432 + /* 18401 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 112, + 27, + 0, // Skip to: 25432 + /* 18408 */ MCD_OPC_Decode, + 193, + 8, + 141, + 1, // Opcode: MVE_VHSUBs16 + /* 18413 */ MCD_OPC_FilterValue, + 15, + 102, + 27, + 0, // Skip to: 25432 + /* 18418 */ MCD_OPC_CheckPredicate, + 22, + 97, + 27, + 0, // Skip to: 25432 + /* 18423 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 90, + 27, + 0, // Skip to: 25432 + /* 18430 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 83, + 27, + 0, // Skip to: 25432 + /* 18437 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 76, + 27, + 0, // Skip to: 25432 + /* 18444 */ MCD_OPC_Decode, + 196, + 8, + 141, + 1, // Opcode: MVE_VHSUBu16 + /* 18449 */ MCD_OPC_FilterValue, + 1, + 66, + 27, + 0, // Skip to: 25432 + /* 18454 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18457 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18493 + /* 18462 */ MCD_OPC_CheckPredicate, + 22, + 53, + 27, + 0, // Skip to: 25432 + /* 18467 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 27, + 0, // Skip to: 25432 + /* 18474 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 27, + 0, // Skip to: 25432 + /* 18481 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 32, + 27, + 0, // Skip to: 25432 + /* 18488 */ MCD_OPC_Decode, + 134, + 12, + 141, + 1, // Opcode: MVE_VQSUBs16 + /* 18493 */ MCD_OPC_FilterValue, + 15, + 22, + 27, + 0, // Skip to: 25432 + /* 18498 */ MCD_OPC_CheckPredicate, + 22, + 17, + 27, + 0, // Skip to: 25432 + /* 18503 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 10, + 27, + 0, // Skip to: 25432 + /* 18510 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 3, + 27, + 0, // Skip to: 25432 + /* 18517 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 252, + 26, + 0, // Skip to: 25432 + /* 18524 */ MCD_OPC_Decode, + 137, + 12, + 141, + 1, // Opcode: MVE_VQSUBu16 + /* 18529 */ MCD_OPC_FilterValue, + 2, + 242, + 26, + 0, // Skip to: 25432 + /* 18534 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18537 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18617 + /* 18542 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18545 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18581 + /* 18550 */ MCD_OPC_CheckPredicate, + 22, + 221, + 26, + 0, // Skip to: 25432 + /* 18555 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 26, + 0, // Skip to: 25432 + /* 18562 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 26, + 0, // Skip to: 25432 + /* 18569 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 26, + 0, // Skip to: 25432 + /* 18576 */ MCD_OPC_Decode, + 194, + 8, + 141, + 1, // Opcode: MVE_VHSUBs32 + /* 18581 */ MCD_OPC_FilterValue, + 15, + 190, + 26, + 0, // Skip to: 25432 + /* 18586 */ MCD_OPC_CheckPredicate, + 22, + 185, + 26, + 0, // Skip to: 25432 + /* 18591 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 26, + 0, // Skip to: 25432 + /* 18598 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 26, + 0, // Skip to: 25432 + /* 18605 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 26, + 0, // Skip to: 25432 + /* 18612 */ MCD_OPC_Decode, + 197, + 8, + 141, + 1, // Opcode: MVE_VHSUBu32 + /* 18617 */ MCD_OPC_FilterValue, + 1, + 154, + 26, + 0, // Skip to: 25432 + /* 18622 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18625 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18661 + /* 18630 */ MCD_OPC_CheckPredicate, + 22, + 141, + 26, + 0, // Skip to: 25432 + /* 18635 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 134, + 26, + 0, // Skip to: 25432 + /* 18642 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 127, + 26, + 0, // Skip to: 25432 + /* 18649 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 120, + 26, + 0, // Skip to: 25432 + /* 18656 */ MCD_OPC_Decode, + 135, + 12, + 141, + 1, // Opcode: MVE_VQSUBs32 + /* 18661 */ MCD_OPC_FilterValue, + 15, + 110, + 26, + 0, // Skip to: 25432 + /* 18666 */ MCD_OPC_CheckPredicate, + 22, + 105, + 26, + 0, // Skip to: 25432 + /* 18671 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 98, + 26, + 0, // Skip to: 25432 + /* 18678 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 91, + 26, + 0, // Skip to: 25432 + /* 18685 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 26, + 0, // Skip to: 25432 + /* 18692 */ MCD_OPC_Decode, + 138, + 12, + 141, + 1, // Opcode: MVE_VQSUBu32 + /* 18697 */ MCD_OPC_FilterValue, + 4, + 251, + 1, + 0, // Skip to: 19209 + /* 18702 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 18705 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 18873 + /* 18710 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18713 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18793 + /* 18718 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18721 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18757 + /* 18726 */ MCD_OPC_CheckPredicate, + 22, + 45, + 26, + 0, // Skip to: 25432 + /* 18731 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 38, + 26, + 0, // Skip to: 25432 + /* 18738 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 26, + 0, // Skip to: 25432 + /* 18745 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 24, + 26, + 0, // Skip to: 25432 + /* 18752 */ MCD_OPC_Decode, + 223, + 12, + 187, + 1, // Opcode: MVE_VSHL_by_vecs8 + /* 18757 */ MCD_OPC_FilterValue, + 15, + 14, + 26, + 0, // Skip to: 25432 + /* 18762 */ MCD_OPC_CheckPredicate, + 22, + 9, + 26, + 0, // Skip to: 25432 + /* 18767 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 2, + 26, + 0, // Skip to: 25432 + /* 18774 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 251, + 25, + 0, // Skip to: 25432 + /* 18781 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 244, + 25, + 0, // Skip to: 25432 + /* 18788 */ MCD_OPC_Decode, + 226, + 12, + 187, + 1, // Opcode: MVE_VSHL_by_vecu8 + /* 18793 */ MCD_OPC_FilterValue, + 1, + 234, + 25, + 0, // Skip to: 25432 + /* 18798 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18801 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18837 + /* 18806 */ MCD_OPC_CheckPredicate, + 22, + 221, + 25, + 0, // Skip to: 25432 + /* 18811 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 25, + 0, // Skip to: 25432 + /* 18818 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 25, + 0, // Skip to: 25432 + /* 18825 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 25, + 0, // Skip to: 25432 + /* 18832 */ MCD_OPC_Decode, + 228, + 11, + 187, + 1, // Opcode: MVE_VQSHL_by_vecs8 + /* 18837 */ MCD_OPC_FilterValue, + 15, + 190, + 25, + 0, // Skip to: 25432 + /* 18842 */ MCD_OPC_CheckPredicate, + 22, + 185, + 25, + 0, // Skip to: 25432 + /* 18847 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 25, + 0, // Skip to: 25432 + /* 18854 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 25, + 0, // Skip to: 25432 + /* 18861 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 25, + 0, // Skip to: 25432 + /* 18868 */ MCD_OPC_Decode, + 231, + 11, + 187, + 1, // Opcode: MVE_VQSHL_by_vecu8 + /* 18873 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 19041 + /* 18878 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 18881 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 18961 + /* 18886 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18889 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 18925 + /* 18894 */ MCD_OPC_CheckPredicate, + 22, + 133, + 25, + 0, // Skip to: 25432 + /* 18899 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 126, + 25, + 0, // Skip to: 25432 + /* 18906 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 119, + 25, + 0, // Skip to: 25432 + /* 18913 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 112, + 25, + 0, // Skip to: 25432 + /* 18920 */ MCD_OPC_Decode, + 221, + 12, + 187, + 1, // Opcode: MVE_VSHL_by_vecs16 + /* 18925 */ MCD_OPC_FilterValue, + 15, + 102, + 25, + 0, // Skip to: 25432 + /* 18930 */ MCD_OPC_CheckPredicate, + 22, + 97, + 25, + 0, // Skip to: 25432 + /* 18935 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 90, + 25, + 0, // Skip to: 25432 + /* 18942 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 83, + 25, + 0, // Skip to: 25432 + /* 18949 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 76, + 25, + 0, // Skip to: 25432 + /* 18956 */ MCD_OPC_Decode, + 224, + 12, + 187, + 1, // Opcode: MVE_VSHL_by_vecu16 + /* 18961 */ MCD_OPC_FilterValue, + 1, + 66, + 25, + 0, // Skip to: 25432 + /* 18966 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 18969 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19005 + /* 18974 */ MCD_OPC_CheckPredicate, + 22, + 53, + 25, + 0, // Skip to: 25432 + /* 18979 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 25, + 0, // Skip to: 25432 + /* 18986 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 25, + 0, // Skip to: 25432 + /* 18993 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 32, + 25, + 0, // Skip to: 25432 + /* 19000 */ MCD_OPC_Decode, + 226, + 11, + 187, + 1, // Opcode: MVE_VQSHL_by_vecs16 + /* 19005 */ MCD_OPC_FilterValue, + 15, + 22, + 25, + 0, // Skip to: 25432 + /* 19010 */ MCD_OPC_CheckPredicate, + 22, + 17, + 25, + 0, // Skip to: 25432 + /* 19015 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 10, + 25, + 0, // Skip to: 25432 + /* 19022 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 3, + 25, + 0, // Skip to: 25432 + /* 19029 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 252, + 24, + 0, // Skip to: 25432 + /* 19036 */ MCD_OPC_Decode, + 229, + 11, + 187, + 1, // Opcode: MVE_VQSHL_by_vecu16 + /* 19041 */ MCD_OPC_FilterValue, + 2, + 242, + 24, + 0, // Skip to: 25432 + /* 19046 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19049 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19129 + /* 19054 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19057 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19093 + /* 19062 */ MCD_OPC_CheckPredicate, + 22, + 221, + 24, + 0, // Skip to: 25432 + /* 19067 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 24, + 0, // Skip to: 25432 + /* 19074 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 24, + 0, // Skip to: 25432 + /* 19081 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 24, + 0, // Skip to: 25432 + /* 19088 */ MCD_OPC_Decode, + 222, + 12, + 187, + 1, // Opcode: MVE_VSHL_by_vecs32 + /* 19093 */ MCD_OPC_FilterValue, + 15, + 190, + 24, + 0, // Skip to: 25432 + /* 19098 */ MCD_OPC_CheckPredicate, + 22, + 185, + 24, + 0, // Skip to: 25432 + /* 19103 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 24, + 0, // Skip to: 25432 + /* 19110 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 24, + 0, // Skip to: 25432 + /* 19117 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 24, + 0, // Skip to: 25432 + /* 19124 */ MCD_OPC_Decode, + 225, + 12, + 187, + 1, // Opcode: MVE_VSHL_by_vecu32 + /* 19129 */ MCD_OPC_FilterValue, + 1, + 154, + 24, + 0, // Skip to: 25432 + /* 19134 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19137 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19173 + /* 19142 */ MCD_OPC_CheckPredicate, + 22, + 141, + 24, + 0, // Skip to: 25432 + /* 19147 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 134, + 24, + 0, // Skip to: 25432 + /* 19154 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 127, + 24, + 0, // Skip to: 25432 + /* 19161 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 120, + 24, + 0, // Skip to: 25432 + /* 19168 */ MCD_OPC_Decode, + 227, + 11, + 187, + 1, // Opcode: MVE_VQSHL_by_vecs32 + /* 19173 */ MCD_OPC_FilterValue, + 15, + 110, + 24, + 0, // Skip to: 25432 + /* 19178 */ MCD_OPC_CheckPredicate, + 22, + 105, + 24, + 0, // Skip to: 25432 + /* 19183 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 98, + 24, + 0, // Skip to: 25432 + /* 19190 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 91, + 24, + 0, // Skip to: 25432 + /* 19197 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 24, + 0, // Skip to: 25432 + /* 19204 */ MCD_OPC_Decode, + 230, + 11, + 187, + 1, // Opcode: MVE_VQSHL_by_vecu32 + /* 19209 */ MCD_OPC_FilterValue, + 5, + 251, + 1, + 0, // Skip to: 19721 + /* 19214 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 19217 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 19385 + /* 19222 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19225 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19305 + /* 19230 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19233 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19269 + /* 19238 */ MCD_OPC_CheckPredicate, + 22, + 45, + 24, + 0, // Skip to: 25432 + /* 19243 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 38, + 24, + 0, // Skip to: 25432 + /* 19250 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 24, + 0, // Skip to: 25432 + /* 19257 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 24, + 24, + 0, // Skip to: 25432 + /* 19264 */ MCD_OPC_Decode, + 182, + 12, + 187, + 1, // Opcode: MVE_VRSHL_by_vecs8 + /* 19269 */ MCD_OPC_FilterValue, + 15, + 14, + 24, + 0, // Skip to: 25432 + /* 19274 */ MCD_OPC_CheckPredicate, + 22, + 9, + 24, + 0, // Skip to: 25432 + /* 19279 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 2, + 24, + 0, // Skip to: 25432 + /* 19286 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 251, + 23, + 0, // Skip to: 25432 + /* 19293 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 244, + 23, + 0, // Skip to: 25432 + /* 19300 */ MCD_OPC_Decode, + 185, + 12, + 187, + 1, // Opcode: MVE_VRSHL_by_vecu8 + /* 19305 */ MCD_OPC_FilterValue, + 1, + 234, + 23, + 0, // Skip to: 25432 + /* 19310 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19313 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19349 + /* 19318 */ MCD_OPC_CheckPredicate, + 22, + 221, + 23, + 0, // Skip to: 25432 + /* 19323 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 23, + 0, // Skip to: 25432 + /* 19330 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 23, + 0, // Skip to: 25432 + /* 19337 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 23, + 0, // Skip to: 25432 + /* 19344 */ MCD_OPC_Decode, + 201, + 11, + 187, + 1, // Opcode: MVE_VQRSHL_by_vecs8 + /* 19349 */ MCD_OPC_FilterValue, + 15, + 190, + 23, + 0, // Skip to: 25432 + /* 19354 */ MCD_OPC_CheckPredicate, + 22, + 185, + 23, + 0, // Skip to: 25432 + /* 19359 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 23, + 0, // Skip to: 25432 + /* 19366 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 23, + 0, // Skip to: 25432 + /* 19373 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 23, + 0, // Skip to: 25432 + /* 19380 */ MCD_OPC_Decode, + 204, + 11, + 187, + 1, // Opcode: MVE_VQRSHL_by_vecu8 + /* 19385 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 19553 + /* 19390 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19393 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19473 + /* 19398 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19401 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19437 + /* 19406 */ MCD_OPC_CheckPredicate, + 22, + 133, + 23, + 0, // Skip to: 25432 + /* 19411 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 126, + 23, + 0, // Skip to: 25432 + /* 19418 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 119, + 23, + 0, // Skip to: 25432 + /* 19425 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 112, + 23, + 0, // Skip to: 25432 + /* 19432 */ MCD_OPC_Decode, + 180, + 12, + 187, + 1, // Opcode: MVE_VRSHL_by_vecs16 + /* 19437 */ MCD_OPC_FilterValue, + 15, + 102, + 23, + 0, // Skip to: 25432 + /* 19442 */ MCD_OPC_CheckPredicate, + 22, + 97, + 23, + 0, // Skip to: 25432 + /* 19447 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 90, + 23, + 0, // Skip to: 25432 + /* 19454 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 83, + 23, + 0, // Skip to: 25432 + /* 19461 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 76, + 23, + 0, // Skip to: 25432 + /* 19468 */ MCD_OPC_Decode, + 183, + 12, + 187, + 1, // Opcode: MVE_VRSHL_by_vecu16 + /* 19473 */ MCD_OPC_FilterValue, + 1, + 66, + 23, + 0, // Skip to: 25432 + /* 19478 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19481 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19517 + /* 19486 */ MCD_OPC_CheckPredicate, + 22, + 53, + 23, + 0, // Skip to: 25432 + /* 19491 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 23, + 0, // Skip to: 25432 + /* 19498 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 23, + 0, // Skip to: 25432 + /* 19505 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 32, + 23, + 0, // Skip to: 25432 + /* 19512 */ MCD_OPC_Decode, + 199, + 11, + 187, + 1, // Opcode: MVE_VQRSHL_by_vecs16 + /* 19517 */ MCD_OPC_FilterValue, + 15, + 22, + 23, + 0, // Skip to: 25432 + /* 19522 */ MCD_OPC_CheckPredicate, + 22, + 17, + 23, + 0, // Skip to: 25432 + /* 19527 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 10, + 23, + 0, // Skip to: 25432 + /* 19534 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 3, + 23, + 0, // Skip to: 25432 + /* 19541 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 252, + 22, + 0, // Skip to: 25432 + /* 19548 */ MCD_OPC_Decode, + 202, + 11, + 187, + 1, // Opcode: MVE_VQRSHL_by_vecu16 + /* 19553 */ MCD_OPC_FilterValue, + 2, + 242, + 22, + 0, // Skip to: 25432 + /* 19558 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19561 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19641 + /* 19566 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19569 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19605 + /* 19574 */ MCD_OPC_CheckPredicate, + 22, + 221, + 22, + 0, // Skip to: 25432 + /* 19579 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 22, + 0, // Skip to: 25432 + /* 19586 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 22, + 0, // Skip to: 25432 + /* 19593 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 22, + 0, // Skip to: 25432 + /* 19600 */ MCD_OPC_Decode, + 181, + 12, + 187, + 1, // Opcode: MVE_VRSHL_by_vecs32 + /* 19605 */ MCD_OPC_FilterValue, + 15, + 190, + 22, + 0, // Skip to: 25432 + /* 19610 */ MCD_OPC_CheckPredicate, + 22, + 185, + 22, + 0, // Skip to: 25432 + /* 19615 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 22, + 0, // Skip to: 25432 + /* 19622 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 22, + 0, // Skip to: 25432 + /* 19629 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 22, + 0, // Skip to: 25432 + /* 19636 */ MCD_OPC_Decode, + 184, + 12, + 187, + 1, // Opcode: MVE_VRSHL_by_vecu32 + /* 19641 */ MCD_OPC_FilterValue, + 1, + 154, + 22, + 0, // Skip to: 25432 + /* 19646 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19649 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19685 + /* 19654 */ MCD_OPC_CheckPredicate, + 22, + 141, + 22, + 0, // Skip to: 25432 + /* 19659 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 134, + 22, + 0, // Skip to: 25432 + /* 19666 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 127, + 22, + 0, // Skip to: 25432 + /* 19673 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 120, + 22, + 0, // Skip to: 25432 + /* 19680 */ MCD_OPC_Decode, + 200, + 11, + 187, + 1, // Opcode: MVE_VQRSHL_by_vecs32 + /* 19685 */ MCD_OPC_FilterValue, + 15, + 110, + 22, + 0, // Skip to: 25432 + /* 19690 */ MCD_OPC_CheckPredicate, + 22, + 105, + 22, + 0, // Skip to: 25432 + /* 19695 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 98, + 22, + 0, // Skip to: 25432 + /* 19702 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 91, + 22, + 0, // Skip to: 25432 + /* 19709 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 22, + 0, // Skip to: 25432 + /* 19716 */ MCD_OPC_Decode, + 203, + 11, + 187, + 1, // Opcode: MVE_VQRSHL_by_vecu32 + /* 19721 */ MCD_OPC_FilterValue, + 6, + 251, + 1, + 0, // Skip to: 20233 + /* 19726 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 19729 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 19897 + /* 19734 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19737 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19817 + /* 19742 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19745 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19781 + /* 19750 */ MCD_OPC_CheckPredicate, + 22, + 45, + 22, + 0, // Skip to: 25432 + /* 19755 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 38, + 22, + 0, // Skip to: 25432 + /* 19762 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 22, + 0, // Skip to: 25432 + /* 19769 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 24, + 22, + 0, // Skip to: 25432 + /* 19776 */ MCD_OPC_Decode, + 181, + 9, + 141, + 1, // Opcode: MVE_VMAXs8 + /* 19781 */ MCD_OPC_FilterValue, + 15, + 14, + 22, + 0, // Skip to: 25432 + /* 19786 */ MCD_OPC_CheckPredicate, + 22, + 9, + 22, + 0, // Skip to: 25432 + /* 19791 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 2, + 22, + 0, // Skip to: 25432 + /* 19798 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 251, + 21, + 0, // Skip to: 25432 + /* 19805 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 244, + 21, + 0, // Skip to: 25432 + /* 19812 */ MCD_OPC_Decode, + 184, + 9, + 141, + 1, // Opcode: MVE_VMAXu8 + /* 19817 */ MCD_OPC_FilterValue, + 1, + 234, + 21, + 0, // Skip to: 25432 + /* 19822 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19825 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19861 + /* 19830 */ MCD_OPC_CheckPredicate, + 22, + 221, + 21, + 0, // Skip to: 25432 + /* 19835 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 21, + 0, // Skip to: 25432 + /* 19842 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 21, + 0, // Skip to: 25432 + /* 19849 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 21, + 0, // Skip to: 25432 + /* 19856 */ MCD_OPC_Decode, + 207, + 9, + 141, + 1, // Opcode: MVE_VMINs8 + /* 19861 */ MCD_OPC_FilterValue, + 15, + 190, + 21, + 0, // Skip to: 25432 + /* 19866 */ MCD_OPC_CheckPredicate, + 22, + 185, + 21, + 0, // Skip to: 25432 + /* 19871 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 21, + 0, // Skip to: 25432 + /* 19878 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 21, + 0, // Skip to: 25432 + /* 19885 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 21, + 0, // Skip to: 25432 + /* 19892 */ MCD_OPC_Decode, + 210, + 9, + 141, + 1, // Opcode: MVE_VMINu8 + /* 19897 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 20065 + /* 19902 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19905 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 19985 + /* 19910 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19913 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 19949 + /* 19918 */ MCD_OPC_CheckPredicate, + 22, + 133, + 21, + 0, // Skip to: 25432 + /* 19923 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 126, + 21, + 0, // Skip to: 25432 + /* 19930 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 119, + 21, + 0, // Skip to: 25432 + /* 19937 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 112, + 21, + 0, // Skip to: 25432 + /* 19944 */ MCD_OPC_Decode, + 179, + 9, + 141, + 1, // Opcode: MVE_VMAXs16 + /* 19949 */ MCD_OPC_FilterValue, + 15, + 102, + 21, + 0, // Skip to: 25432 + /* 19954 */ MCD_OPC_CheckPredicate, + 22, + 97, + 21, + 0, // Skip to: 25432 + /* 19959 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 90, + 21, + 0, // Skip to: 25432 + /* 19966 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 83, + 21, + 0, // Skip to: 25432 + /* 19973 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 76, + 21, + 0, // Skip to: 25432 + /* 19980 */ MCD_OPC_Decode, + 182, + 9, + 141, + 1, // Opcode: MVE_VMAXu16 + /* 19985 */ MCD_OPC_FilterValue, + 1, + 66, + 21, + 0, // Skip to: 25432 + /* 19990 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 19993 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 20029 + /* 19998 */ MCD_OPC_CheckPredicate, + 22, + 53, + 21, + 0, // Skip to: 25432 + /* 20003 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 21, + 0, // Skip to: 25432 + /* 20010 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 21, + 0, // Skip to: 25432 + /* 20017 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 32, + 21, + 0, // Skip to: 25432 + /* 20024 */ MCD_OPC_Decode, + 205, + 9, + 141, + 1, // Opcode: MVE_VMINs16 + /* 20029 */ MCD_OPC_FilterValue, + 15, + 22, + 21, + 0, // Skip to: 25432 + /* 20034 */ MCD_OPC_CheckPredicate, + 22, + 17, + 21, + 0, // Skip to: 25432 + /* 20039 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 10, + 21, + 0, // Skip to: 25432 + /* 20046 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 3, + 21, + 0, // Skip to: 25432 + /* 20053 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 252, + 20, + 0, // Skip to: 25432 + /* 20060 */ MCD_OPC_Decode, + 208, + 9, + 141, + 1, // Opcode: MVE_VMINu16 + /* 20065 */ MCD_OPC_FilterValue, + 2, + 242, + 20, + 0, // Skip to: 25432 + /* 20070 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 20073 */ MCD_OPC_FilterValue, + 0, + 75, + 0, + 0, // Skip to: 20153 + /* 20078 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20081 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 20117 + /* 20086 */ MCD_OPC_CheckPredicate, + 22, + 221, + 20, + 0, // Skip to: 25432 + /* 20091 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 214, + 20, + 0, // Skip to: 25432 + /* 20098 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 207, + 20, + 0, // Skip to: 25432 + /* 20105 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 200, + 20, + 0, // Skip to: 25432 + /* 20112 */ MCD_OPC_Decode, + 180, + 9, + 141, + 1, // Opcode: MVE_VMAXs32 + /* 20117 */ MCD_OPC_FilterValue, + 15, + 190, + 20, + 0, // Skip to: 25432 + /* 20122 */ MCD_OPC_CheckPredicate, + 22, + 185, + 20, + 0, // Skip to: 25432 + /* 20127 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 178, + 20, + 0, // Skip to: 25432 + /* 20134 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 171, + 20, + 0, // Skip to: 25432 + /* 20141 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 20, + 0, // Skip to: 25432 + /* 20148 */ MCD_OPC_Decode, + 183, + 9, + 141, + 1, // Opcode: MVE_VMAXu32 + /* 20153 */ MCD_OPC_FilterValue, + 1, + 154, + 20, + 0, // Skip to: 25432 + /* 20158 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20161 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 20197 + /* 20166 */ MCD_OPC_CheckPredicate, + 22, + 141, + 20, + 0, // Skip to: 25432 + /* 20171 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 134, + 20, + 0, // Skip to: 25432 + /* 20178 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 127, + 20, + 0, // Skip to: 25432 + /* 20185 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 120, + 20, + 0, // Skip to: 25432 + /* 20192 */ MCD_OPC_Decode, + 206, + 9, + 141, + 1, // Opcode: MVE_VMINs32 + /* 20197 */ MCD_OPC_FilterValue, + 15, + 110, + 20, + 0, // Skip to: 25432 + /* 20202 */ MCD_OPC_CheckPredicate, + 22, + 105, + 20, + 0, // Skip to: 25432 + /* 20207 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 98, + 20, + 0, // Skip to: 25432 + /* 20214 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 91, + 20, + 0, // Skip to: 25432 + /* 20221 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 20, + 0, // Skip to: 25432 + /* 20228 */ MCD_OPC_Decode, + 209, + 9, + 141, + 1, // Opcode: MVE_VMINu32 + /* 20233 */ MCD_OPC_FilterValue, + 7, + 29, + 1, + 0, // Skip to: 20523 + /* 20238 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 20241 */ MCD_OPC_FilterValue, + 0, + 89, + 0, + 0, // Skip to: 20335 + /* 20246 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20249 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20292 + /* 20254 */ MCD_OPC_CheckPredicate, + 22, + 53, + 20, + 0, // Skip to: 25432 + /* 20259 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 46, + 20, + 0, // Skip to: 25432 + /* 20266 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 39, + 20, + 0, // Skip to: 25432 + /* 20273 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 32, + 20, + 0, // Skip to: 25432 + /* 20280 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 25, + 20, + 0, // Skip to: 25432 + /* 20287 */ MCD_OPC_Decode, + 161, + 7, + 141, + 1, // Opcode: MVE_VABDs8 + /* 20292 */ MCD_OPC_FilterValue, + 15, + 15, + 20, + 0, // Skip to: 25432 + /* 20297 */ MCD_OPC_CheckPredicate, + 22, + 10, + 20, + 0, // Skip to: 25432 + /* 20302 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 3, + 20, + 0, // Skip to: 25432 + /* 20309 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 252, + 19, + 0, // Skip to: 25432 + /* 20316 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 245, + 19, + 0, // Skip to: 25432 + /* 20323 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 238, + 19, + 0, // Skip to: 25432 + /* 20330 */ MCD_OPC_Decode, + 164, + 7, + 141, + 1, // Opcode: MVE_VABDu8 + /* 20335 */ MCD_OPC_FilterValue, + 1, + 89, + 0, + 0, // Skip to: 20429 + /* 20340 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20343 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20386 + /* 20348 */ MCD_OPC_CheckPredicate, + 22, + 215, + 19, + 0, // Skip to: 25432 + /* 20353 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 208, + 19, + 0, // Skip to: 25432 + /* 20360 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 201, + 19, + 0, // Skip to: 25432 + /* 20367 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 194, + 19, + 0, // Skip to: 25432 + /* 20374 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 187, + 19, + 0, // Skip to: 25432 + /* 20381 */ MCD_OPC_Decode, + 159, + 7, + 141, + 1, // Opcode: MVE_VABDs16 + /* 20386 */ MCD_OPC_FilterValue, + 15, + 177, + 19, + 0, // Skip to: 25432 + /* 20391 */ MCD_OPC_CheckPredicate, + 22, + 172, + 19, + 0, // Skip to: 25432 + /* 20396 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 165, + 19, + 0, // Skip to: 25432 + /* 20403 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 158, + 19, + 0, // Skip to: 25432 + /* 20410 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 151, + 19, + 0, // Skip to: 25432 + /* 20417 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 144, + 19, + 0, // Skip to: 25432 + /* 20424 */ MCD_OPC_Decode, + 162, + 7, + 141, + 1, // Opcode: MVE_VABDu16 + /* 20429 */ MCD_OPC_FilterValue, + 2, + 134, + 19, + 0, // Skip to: 25432 + /* 20434 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20437 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20480 + /* 20442 */ MCD_OPC_CheckPredicate, + 22, + 121, + 19, + 0, // Skip to: 25432 + /* 20447 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 114, + 19, + 0, // Skip to: 25432 + /* 20454 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 107, + 19, + 0, // Skip to: 25432 + /* 20461 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 100, + 19, + 0, // Skip to: 25432 + /* 20468 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 93, + 19, + 0, // Skip to: 25432 + /* 20475 */ MCD_OPC_Decode, + 160, + 7, + 141, + 1, // Opcode: MVE_VABDs32 + /* 20480 */ MCD_OPC_FilterValue, + 15, + 83, + 19, + 0, // Skip to: 25432 + /* 20485 */ MCD_OPC_CheckPredicate, + 22, + 78, + 19, + 0, // Skip to: 25432 + /* 20490 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 71, + 19, + 0, // Skip to: 25432 + /* 20497 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 64, + 19, + 0, // Skip to: 25432 + /* 20504 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 57, + 19, + 0, // Skip to: 25432 + /* 20511 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 50, + 19, + 0, // Skip to: 25432 + /* 20518 */ MCD_OPC_Decode, + 163, + 7, + 141, + 1, // Opcode: MVE_VABDu32 + /* 20523 */ MCD_OPC_FilterValue, + 8, + 29, + 1, + 0, // Skip to: 20813 + /* 20528 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 20531 */ MCD_OPC_FilterValue, + 0, + 89, + 0, + 0, // Skip to: 20625 + /* 20536 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20539 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20582 + /* 20544 */ MCD_OPC_CheckPredicate, + 22, + 19, + 19, + 0, // Skip to: 25432 + /* 20549 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 12, + 19, + 0, // Skip to: 25432 + /* 20556 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 5, + 19, + 0, // Skip to: 25432 + /* 20563 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 254, + 18, + 0, // Skip to: 25432 + /* 20570 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 247, + 18, + 0, // Skip to: 25432 + /* 20577 */ MCD_OPC_Decode, + 197, + 7, + 141, + 1, // Opcode: MVE_VADDi8 + /* 20582 */ MCD_OPC_FilterValue, + 15, + 237, + 18, + 0, // Skip to: 25432 + /* 20587 */ MCD_OPC_CheckPredicate, + 22, + 232, + 18, + 0, // Skip to: 25432 + /* 20592 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 225, + 18, + 0, // Skip to: 25432 + /* 20599 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 218, + 18, + 0, // Skip to: 25432 + /* 20606 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 211, + 18, + 0, // Skip to: 25432 + /* 20613 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 204, + 18, + 0, // Skip to: 25432 + /* 20620 */ MCD_OPC_Decode, + 202, + 13, + 141, + 1, // Opcode: MVE_VSUBi8 + /* 20625 */ MCD_OPC_FilterValue, + 1, + 89, + 0, + 0, // Skip to: 20719 + /* 20630 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20633 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20676 + /* 20638 */ MCD_OPC_CheckPredicate, + 22, + 181, + 18, + 0, // Skip to: 25432 + /* 20643 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 174, + 18, + 0, // Skip to: 25432 + /* 20650 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 167, + 18, + 0, // Skip to: 25432 + /* 20657 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 160, + 18, + 0, // Skip to: 25432 + /* 20664 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 153, + 18, + 0, // Skip to: 25432 + /* 20671 */ MCD_OPC_Decode, + 195, + 7, + 141, + 1, // Opcode: MVE_VADDi16 + /* 20676 */ MCD_OPC_FilterValue, + 15, + 143, + 18, + 0, // Skip to: 25432 + /* 20681 */ MCD_OPC_CheckPredicate, + 22, + 138, + 18, + 0, // Skip to: 25432 + /* 20686 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 131, + 18, + 0, // Skip to: 25432 + /* 20693 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 124, + 18, + 0, // Skip to: 25432 + /* 20700 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 117, + 18, + 0, // Skip to: 25432 + /* 20707 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 110, + 18, + 0, // Skip to: 25432 + /* 20714 */ MCD_OPC_Decode, + 200, + 13, + 141, + 1, // Opcode: MVE_VSUBi16 + /* 20719 */ MCD_OPC_FilterValue, + 2, + 100, + 18, + 0, // Skip to: 25432 + /* 20724 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20727 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 20770 + /* 20732 */ MCD_OPC_CheckPredicate, + 22, + 87, + 18, + 0, // Skip to: 25432 + /* 20737 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 80, + 18, + 0, // Skip to: 25432 + /* 20744 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 73, + 18, + 0, // Skip to: 25432 + /* 20751 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 66, + 18, + 0, // Skip to: 25432 + /* 20758 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 59, + 18, + 0, // Skip to: 25432 + /* 20765 */ MCD_OPC_Decode, + 196, + 7, + 141, + 1, // Opcode: MVE_VADDi32 + /* 20770 */ MCD_OPC_FilterValue, + 15, + 49, + 18, + 0, // Skip to: 25432 + /* 20775 */ MCD_OPC_CheckPredicate, + 22, + 44, + 18, + 0, // Skip to: 25432 + /* 20780 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 37, + 18, + 0, // Skip to: 25432 + /* 20787 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 30, + 18, + 0, // Skip to: 25432 + /* 20794 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 23, + 18, + 0, // Skip to: 25432 + /* 20801 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 16, + 18, + 0, // Skip to: 25432 + /* 20808 */ MCD_OPC_Decode, + 201, + 13, + 141, + 1, // Opcode: MVE_VSUBi32 + /* 20813 */ MCD_OPC_FilterValue, + 9, + 153, + 0, + 0, // Skip to: 20971 + /* 20818 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 20821 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 20871 + /* 20826 */ MCD_OPC_CheckPredicate, + 22, + 249, + 17, + 0, // Skip to: 25432 + /* 20831 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 242, + 17, + 0, // Skip to: 25432 + /* 20838 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 235, + 17, + 0, // Skip to: 25432 + /* 20845 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 228, + 17, + 0, // Skip to: 25432 + /* 20852 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 221, + 17, + 0, // Skip to: 25432 + /* 20859 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 214, + 17, + 0, // Skip to: 25432 + /* 20866 */ MCD_OPC_Decode, + 203, + 10, + 141, + 1, // Opcode: MVE_VMULi8 + /* 20871 */ MCD_OPC_FilterValue, + 1, + 45, + 0, + 0, // Skip to: 20921 + /* 20876 */ MCD_OPC_CheckPredicate, + 22, + 199, + 17, + 0, // Skip to: 25432 + /* 20881 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 192, + 17, + 0, // Skip to: 25432 + /* 20888 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 185, + 17, + 0, // Skip to: 25432 + /* 20895 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 178, + 17, + 0, // Skip to: 25432 + /* 20902 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 171, + 17, + 0, // Skip to: 25432 + /* 20909 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 17, + 0, // Skip to: 25432 + /* 20916 */ MCD_OPC_Decode, + 201, + 10, + 141, + 1, // Opcode: MVE_VMULi16 + /* 20921 */ MCD_OPC_FilterValue, + 2, + 154, + 17, + 0, // Skip to: 25432 + /* 20926 */ MCD_OPC_CheckPredicate, + 22, + 149, + 17, + 0, // Skip to: 25432 + /* 20931 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 142, + 17, + 0, // Skip to: 25432 + /* 20938 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 135, + 17, + 0, // Skip to: 25432 + /* 20945 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 128, + 17, + 0, // Skip to: 25432 + /* 20952 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 121, + 17, + 0, // Skip to: 25432 + /* 20959 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 114, + 17, + 0, // Skip to: 25432 + /* 20966 */ MCD_OPC_Decode, + 202, + 10, + 141, + 1, // Opcode: MVE_VMULi32 + /* 20971 */ MCD_OPC_FilterValue, + 11, + 29, + 1, + 0, // Skip to: 21261 + /* 20976 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 20979 */ MCD_OPC_FilterValue, + 0, + 89, + 0, + 0, // Skip to: 21073 + /* 20984 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 20987 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 21030 + /* 20992 */ MCD_OPC_CheckPredicate, + 22, + 83, + 17, + 0, // Skip to: 25432 + /* 20997 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 76, + 17, + 0, // Skip to: 25432 + /* 21004 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 69, + 17, + 0, // Skip to: 25432 + /* 21011 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 62, + 17, + 0, // Skip to: 25432 + /* 21018 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 55, + 17, + 0, // Skip to: 25432 + /* 21025 */ MCD_OPC_Decode, + 151, + 11, + 141, + 1, // Opcode: MVE_VQDMULHi8 + /* 21030 */ MCD_OPC_FilterValue, + 15, + 45, + 17, + 0, // Skip to: 25432 + /* 21035 */ MCD_OPC_CheckPredicate, + 22, + 40, + 17, + 0, // Skip to: 25432 + /* 21040 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 33, + 17, + 0, // Skip to: 25432 + /* 21047 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 26, + 17, + 0, // Skip to: 25432 + /* 21054 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 19, + 17, + 0, // Skip to: 25432 + /* 21061 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 12, + 17, + 0, // Skip to: 25432 + /* 21068 */ MCD_OPC_Decode, + 198, + 11, + 141, + 1, // Opcode: MVE_VQRDMULHi8 + /* 21073 */ MCD_OPC_FilterValue, + 1, + 89, + 0, + 0, // Skip to: 21167 + /* 21078 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 21081 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 21124 + /* 21086 */ MCD_OPC_CheckPredicate, + 22, + 245, + 16, + 0, // Skip to: 25432 + /* 21091 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 238, + 16, + 0, // Skip to: 25432 + /* 21098 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 231, + 16, + 0, // Skip to: 25432 + /* 21105 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 224, + 16, + 0, // Skip to: 25432 + /* 21112 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 217, + 16, + 0, // Skip to: 25432 + /* 21119 */ MCD_OPC_Decode, + 149, + 11, + 141, + 1, // Opcode: MVE_VQDMULHi16 + /* 21124 */ MCD_OPC_FilterValue, + 15, + 207, + 16, + 0, // Skip to: 25432 + /* 21129 */ MCD_OPC_CheckPredicate, + 22, + 202, + 16, + 0, // Skip to: 25432 + /* 21134 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 195, + 16, + 0, // Skip to: 25432 + /* 21141 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 188, + 16, + 0, // Skip to: 25432 + /* 21148 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 16, + 0, // Skip to: 25432 + /* 21155 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 174, + 16, + 0, // Skip to: 25432 + /* 21162 */ MCD_OPC_Decode, + 196, + 11, + 141, + 1, // Opcode: MVE_VQRDMULHi16 + /* 21167 */ MCD_OPC_FilterValue, + 2, + 164, + 16, + 0, // Skip to: 25432 + /* 21172 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 21175 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 21218 + /* 21180 */ MCD_OPC_CheckPredicate, + 22, + 151, + 16, + 0, // Skip to: 25432 + /* 21185 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 144, + 16, + 0, // Skip to: 25432 + /* 21192 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 137, + 16, + 0, // Skip to: 25432 + /* 21199 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 130, + 16, + 0, // Skip to: 25432 + /* 21206 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 123, + 16, + 0, // Skip to: 25432 + /* 21213 */ MCD_OPC_Decode, + 150, + 11, + 141, + 1, // Opcode: MVE_VQDMULHi32 + /* 21218 */ MCD_OPC_FilterValue, + 15, + 113, + 16, + 0, // Skip to: 25432 + /* 21223 */ MCD_OPC_CheckPredicate, + 22, + 108, + 16, + 0, // Skip to: 25432 + /* 21228 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 101, + 16, + 0, // Skip to: 25432 + /* 21235 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 94, + 16, + 0, // Skip to: 25432 + /* 21242 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 87, + 16, + 0, // Skip to: 25432 + /* 21249 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 80, + 16, + 0, // Skip to: 25432 + /* 21256 */ MCD_OPC_Decode, + 197, + 11, + 141, + 1, // Opcode: MVE_VQRDMULHi32 + /* 21261 */ MCD_OPC_FilterValue, + 12, + 203, + 0, + 0, // Skip to: 21469 + /* 21266 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 21269 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 21319 + /* 21274 */ MCD_OPC_CheckPredicate, + 24, + 57, + 16, + 0, // Skip to: 25432 + /* 21279 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 50, + 16, + 0, // Skip to: 25432 + /* 21286 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 43, + 16, + 0, // Skip to: 25432 + /* 21293 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 36, + 16, + 0, // Skip to: 25432 + /* 21300 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 29, + 16, + 0, // Skip to: 25432 + /* 21307 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 22, + 16, + 0, // Skip to: 25432 + /* 21314 */ MCD_OPC_Decode, + 169, + 8, + 140, + 1, // Opcode: MVE_VFMAf32 + /* 21319 */ MCD_OPC_FilterValue, + 1, + 45, + 0, + 0, // Skip to: 21369 + /* 21324 */ MCD_OPC_CheckPredicate, + 24, + 7, + 16, + 0, // Skip to: 25432 + /* 21329 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 0, + 16, + 0, // Skip to: 25432 + /* 21336 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 249, + 15, + 0, // Skip to: 25432 + /* 21343 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 242, + 15, + 0, // Skip to: 25432 + /* 21350 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 235, + 15, + 0, // Skip to: 25432 + /* 21357 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 228, + 15, + 0, // Skip to: 25432 + /* 21364 */ MCD_OPC_Decode, + 168, + 8, + 140, + 1, // Opcode: MVE_VFMAf16 + /* 21369 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 21419 + /* 21374 */ MCD_OPC_CheckPredicate, + 24, + 213, + 15, + 0, // Skip to: 25432 + /* 21379 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 206, + 15, + 0, // Skip to: 25432 + /* 21386 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 199, + 15, + 0, // Skip to: 25432 + /* 21393 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 192, + 15, + 0, // Skip to: 25432 + /* 21400 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 185, + 15, + 0, // Skip to: 25432 + /* 21407 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 178, + 15, + 0, // Skip to: 25432 + /* 21414 */ MCD_OPC_Decode, + 171, + 8, + 140, + 1, // Opcode: MVE_VFMSf32 + /* 21419 */ MCD_OPC_FilterValue, + 3, + 168, + 15, + 0, // Skip to: 25432 + /* 21424 */ MCD_OPC_CheckPredicate, + 24, + 163, + 15, + 0, // Skip to: 25432 + /* 21429 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 156, + 15, + 0, // Skip to: 25432 + /* 21436 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 149, + 15, + 0, // Skip to: 25432 + /* 21443 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 142, + 15, + 0, // Skip to: 25432 + /* 21450 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 135, + 15, + 0, // Skip to: 25432 + /* 21457 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 128, + 15, + 0, // Skip to: 25432 + /* 21464 */ MCD_OPC_Decode, + 170, + 8, + 140, + 1, // Opcode: MVE_VFMSf16 + /* 21469 */ MCD_OPC_FilterValue, + 13, + 123, + 1, + 0, // Skip to: 21853 + /* 21474 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 21477 */ MCD_OPC_FilterValue, + 0, + 89, + 0, + 0, // Skip to: 21571 + /* 21482 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 21485 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 21528 + /* 21490 */ MCD_OPC_CheckPredicate, + 24, + 97, + 15, + 0, // Skip to: 25432 + /* 21495 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 90, + 15, + 0, // Skip to: 25432 + /* 21502 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 83, + 15, + 0, // Skip to: 25432 + /* 21509 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 76, + 15, + 0, // Skip to: 25432 + /* 21516 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 69, + 15, + 0, // Skip to: 25432 + /* 21523 */ MCD_OPC_Decode, + 194, + 7, + 141, + 1, // Opcode: MVE_VADDf32 + /* 21528 */ MCD_OPC_FilterValue, + 1, + 59, + 15, + 0, // Skip to: 25432 + /* 21533 */ MCD_OPC_CheckPredicate, + 24, + 54, + 15, + 0, // Skip to: 25432 + /* 21538 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 47, + 15, + 0, // Skip to: 25432 + /* 21545 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 40, + 15, + 0, // Skip to: 25432 + /* 21552 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 33, + 15, + 0, // Skip to: 25432 + /* 21559 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 26, + 15, + 0, // Skip to: 25432 + /* 21566 */ MCD_OPC_Decode, + 200, + 10, + 141, + 1, // Opcode: MVE_VMULf32 + /* 21571 */ MCD_OPC_FilterValue, + 1, + 89, + 0, + 0, // Skip to: 21665 + /* 21576 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 21579 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 21622 + /* 21584 */ MCD_OPC_CheckPredicate, + 24, + 3, + 15, + 0, // Skip to: 25432 + /* 21589 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 252, + 14, + 0, // Skip to: 25432 + /* 21596 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 245, + 14, + 0, // Skip to: 25432 + /* 21603 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 238, + 14, + 0, // Skip to: 25432 + /* 21610 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 231, + 14, + 0, // Skip to: 25432 + /* 21617 */ MCD_OPC_Decode, + 193, + 7, + 141, + 1, // Opcode: MVE_VADDf16 + /* 21622 */ MCD_OPC_FilterValue, + 1, + 221, + 14, + 0, // Skip to: 25432 + /* 21627 */ MCD_OPC_CheckPredicate, + 24, + 216, + 14, + 0, // Skip to: 25432 + /* 21632 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 209, + 14, + 0, // Skip to: 25432 + /* 21639 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 202, + 14, + 0, // Skip to: 25432 + /* 21646 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 195, + 14, + 0, // Skip to: 25432 + /* 21653 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 188, + 14, + 0, // Skip to: 25432 + /* 21660 */ MCD_OPC_Decode, + 199, + 10, + 141, + 1, // Opcode: MVE_VMULf16 + /* 21665 */ MCD_OPC_FilterValue, + 2, + 89, + 0, + 0, // Skip to: 21759 + /* 21670 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 21673 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 21716 + /* 21678 */ MCD_OPC_CheckPredicate, + 24, + 165, + 14, + 0, // Skip to: 25432 + /* 21683 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 158, + 14, + 0, // Skip to: 25432 + /* 21690 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 151, + 14, + 0, // Skip to: 25432 + /* 21697 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 144, + 14, + 0, // Skip to: 25432 + /* 21704 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 137, + 14, + 0, // Skip to: 25432 + /* 21711 */ MCD_OPC_Decode, + 199, + 13, + 141, + 1, // Opcode: MVE_VSUBf32 + /* 21716 */ MCD_OPC_FilterValue, + 15, + 127, + 14, + 0, // Skip to: 25432 + /* 21721 */ MCD_OPC_CheckPredicate, + 24, + 122, + 14, + 0, // Skip to: 25432 + /* 21726 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 115, + 14, + 0, // Skip to: 25432 + /* 21733 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 108, + 14, + 0, // Skip to: 25432 + /* 21740 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 101, + 14, + 0, // Skip to: 25432 + /* 21747 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 94, + 14, + 0, // Skip to: 25432 + /* 21754 */ MCD_OPC_Decode, + 158, + 7, + 141, + 1, // Opcode: MVE_VABDf32 + /* 21759 */ MCD_OPC_FilterValue, + 3, + 84, + 14, + 0, // Skip to: 25432 + /* 21764 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 21767 */ MCD_OPC_FilterValue, + 14, + 38, + 0, + 0, // Skip to: 21810 + /* 21772 */ MCD_OPC_CheckPredicate, + 24, + 71, + 14, + 0, // Skip to: 25432 + /* 21777 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 64, + 14, + 0, // Skip to: 25432 + /* 21784 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 57, + 14, + 0, // Skip to: 25432 + /* 21791 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 50, + 14, + 0, // Skip to: 25432 + /* 21798 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 43, + 14, + 0, // Skip to: 25432 + /* 21805 */ MCD_OPC_Decode, + 198, + 13, + 141, + 1, // Opcode: MVE_VSUBf16 + /* 21810 */ MCD_OPC_FilterValue, + 15, + 33, + 14, + 0, // Skip to: 25432 + /* 21815 */ MCD_OPC_CheckPredicate, + 24, + 28, + 14, + 0, // Skip to: 25432 + /* 21820 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 21, + 14, + 0, // Skip to: 25432 + /* 21827 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 14, + 14, + 0, // Skip to: 25432 + /* 21834 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 7, + 14, + 0, // Skip to: 25432 + /* 21841 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 0, + 14, + 0, // Skip to: 25432 + /* 21848 */ MCD_OPC_Decode, + 157, + 7, + 141, + 1, // Opcode: MVE_VABDf16 + /* 21853 */ MCD_OPC_FilterValue, + 15, + 246, + 13, + 0, // Skip to: 25432 + /* 21858 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 21861 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 21911 + /* 21866 */ MCD_OPC_CheckPredicate, + 24, + 233, + 13, + 0, // Skip to: 25432 + /* 21871 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 226, + 13, + 0, // Skip to: 25432 + /* 21878 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 219, + 13, + 0, // Skip to: 25432 + /* 21885 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 212, + 13, + 0, // Skip to: 25432 + /* 21892 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 205, + 13, + 0, // Skip to: 25432 + /* 21899 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 198, + 13, + 0, // Skip to: 25432 + /* 21906 */ MCD_OPC_Decode, + 172, + 9, + 141, + 1, // Opcode: MVE_VMAXNMf32 + /* 21911 */ MCD_OPC_FilterValue, + 1, + 45, + 0, + 0, // Skip to: 21961 + /* 21916 */ MCD_OPC_CheckPredicate, + 24, + 183, + 13, + 0, // Skip to: 25432 + /* 21921 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 176, + 13, + 0, // Skip to: 25432 + /* 21928 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 169, + 13, + 0, // Skip to: 25432 + /* 21935 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 162, + 13, + 0, // Skip to: 25432 + /* 21942 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 155, + 13, + 0, // Skip to: 25432 + /* 21949 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 148, + 13, + 0, // Skip to: 25432 + /* 21956 */ MCD_OPC_Decode, + 171, + 9, + 141, + 1, // Opcode: MVE_VMAXNMf16 + /* 21961 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 22011 + /* 21966 */ MCD_OPC_CheckPredicate, + 24, + 133, + 13, + 0, // Skip to: 25432 + /* 21971 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 126, + 13, + 0, // Skip to: 25432 + /* 21978 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 119, + 13, + 0, // Skip to: 25432 + /* 21985 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 112, + 13, + 0, // Skip to: 25432 + /* 21992 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 105, + 13, + 0, // Skip to: 25432 + /* 21999 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 98, + 13, + 0, // Skip to: 25432 + /* 22006 */ MCD_OPC_Decode, + 198, + 9, + 141, + 1, // Opcode: MVE_VMINNMf32 + /* 22011 */ MCD_OPC_FilterValue, + 3, + 88, + 13, + 0, // Skip to: 25432 + /* 22016 */ MCD_OPC_CheckPredicate, + 24, + 83, + 13, + 0, // Skip to: 25432 + /* 22021 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 76, + 13, + 0, // Skip to: 25432 + /* 22028 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 69, + 13, + 0, // Skip to: 25432 + /* 22035 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 62, + 13, + 0, // Skip to: 25432 + /* 22042 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 55, + 13, + 0, // Skip to: 25432 + /* 22049 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 48, + 13, + 0, // Skip to: 25432 + /* 22056 */ MCD_OPC_Decode, + 197, + 9, + 141, + 1, // Opcode: MVE_VMINNMf16 + /* 22061 */ MCD_OPC_FilterValue, + 3, + 38, + 13, + 0, // Skip to: 25432 + /* 22066 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 22069 */ MCD_OPC_FilterValue, + 0, + 224, + 7, + 0, // Skip to: 24090 + /* 22074 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 22077 */ MCD_OPC_FilterValue, + 1, + 148, + 0, + 0, // Skip to: 22230 + /* 22082 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22085 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 22114 + /* 22090 */ MCD_OPC_CheckPredicate, + 22, + 9, + 13, + 0, // Skip to: 25432 + /* 22095 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 2, + 13, + 0, // Skip to: 25432 + /* 22102 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 251, + 12, + 0, // Skip to: 25432 + /* 22109 */ MCD_OPC_Decode, + 145, + 12, + 145, + 1, // Opcode: MVE_VREV64_8 + /* 22114 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 22143 + /* 22119 */ MCD_OPC_CheckPredicate, + 22, + 236, + 12, + 0, // Skip to: 25432 + /* 22124 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 229, + 12, + 0, // Skip to: 25432 + /* 22131 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 222, + 12, + 0, // Skip to: 25432 + /* 22138 */ MCD_OPC_Decode, + 143, + 12, + 145, + 1, // Opcode: MVE_VREV64_16 + /* 22143 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22172 + /* 22148 */ MCD_OPC_CheckPredicate, + 24, + 207, + 12, + 0, // Skip to: 25432 + /* 22153 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 200, + 12, + 0, // Skip to: 25432 + /* 22160 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 193, + 12, + 0, // Skip to: 25432 + /* 22167 */ MCD_OPC_Decode, + 131, + 8, + 145, + 1, // Opcode: MVE_VCVTs16f16a + /* 22172 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 22201 + /* 22177 */ MCD_OPC_CheckPredicate, + 22, + 178, + 12, + 0, // Skip to: 25432 + /* 22182 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 171, + 12, + 0, // Skip to: 25432 + /* 22189 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 12, + 0, // Skip to: 25432 + /* 22196 */ MCD_OPC_Decode, + 144, + 12, + 145, + 1, // Opcode: MVE_VREV64_32 + /* 22201 */ MCD_OPC_FilterValue, + 59, + 154, + 12, + 0, // Skip to: 25432 + /* 22206 */ MCD_OPC_CheckPredicate, + 24, + 149, + 12, + 0, // Skip to: 25432 + /* 22211 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 142, + 12, + 0, // Skip to: 25432 + /* 22218 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 135, + 12, + 0, // Skip to: 25432 + /* 22225 */ MCD_OPC_Decode, + 137, + 8, + 145, + 1, // Opcode: MVE_VCVTs32f32a + /* 22230 */ MCD_OPC_FilterValue, + 3, + 119, + 0, + 0, // Skip to: 22354 + /* 22235 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22238 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 22267 + /* 22243 */ MCD_OPC_CheckPredicate, + 22, + 112, + 12, + 0, // Skip to: 25432 + /* 22248 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 105, + 12, + 0, // Skip to: 25432 + /* 22255 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 98, + 12, + 0, // Skip to: 25432 + /* 22262 */ MCD_OPC_Decode, + 142, + 12, + 145, + 1, // Opcode: MVE_VREV32_8 + /* 22267 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 22296 + /* 22272 */ MCD_OPC_CheckPredicate, + 22, + 83, + 12, + 0, // Skip to: 25432 + /* 22277 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 76, + 12, + 0, // Skip to: 25432 + /* 22284 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 69, + 12, + 0, // Skip to: 25432 + /* 22291 */ MCD_OPC_Decode, + 141, + 12, + 145, + 1, // Opcode: MVE_VREV32_16 + /* 22296 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22325 + /* 22301 */ MCD_OPC_CheckPredicate, + 24, + 54, + 12, + 0, // Skip to: 25432 + /* 22306 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 47, + 12, + 0, // Skip to: 25432 + /* 22313 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 40, + 12, + 0, // Skip to: 25432 + /* 22320 */ MCD_OPC_Decode, + 143, + 8, + 145, + 1, // Opcode: MVE_VCVTu16f16a + /* 22325 */ MCD_OPC_FilterValue, + 59, + 30, + 12, + 0, // Skip to: 25432 + /* 22330 */ MCD_OPC_CheckPredicate, + 24, + 25, + 12, + 0, // Skip to: 25432 + /* 22335 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 18, + 12, + 0, // Skip to: 25432 + /* 22342 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 11, + 12, + 0, // Skip to: 25432 + /* 22349 */ MCD_OPC_Decode, + 149, + 8, + 145, + 1, // Opcode: MVE_VCVTu32f32a + /* 22354 */ MCD_OPC_FilterValue, + 5, + 90, + 0, + 0, // Skip to: 22449 + /* 22359 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22362 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 22391 + /* 22367 */ MCD_OPC_CheckPredicate, + 22, + 244, + 11, + 0, // Skip to: 25432 + /* 22372 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 237, + 11, + 0, // Skip to: 25432 + /* 22379 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 230, + 11, + 0, // Skip to: 25432 + /* 22386 */ MCD_OPC_Decode, + 140, + 12, + 145, + 1, // Opcode: MVE_VREV16_8 + /* 22391 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22420 + /* 22396 */ MCD_OPC_CheckPredicate, + 24, + 215, + 11, + 0, // Skip to: 25432 + /* 22401 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 208, + 11, + 0, // Skip to: 25432 + /* 22408 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 201, + 11, + 0, // Skip to: 25432 + /* 22415 */ MCD_OPC_Decode, + 133, + 8, + 145, + 1, // Opcode: MVE_VCVTs16f16n + /* 22420 */ MCD_OPC_FilterValue, + 59, + 191, + 11, + 0, // Skip to: 25432 + /* 22425 */ MCD_OPC_CheckPredicate, + 24, + 186, + 11, + 0, // Skip to: 25432 + /* 22430 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 179, + 11, + 0, // Skip to: 25432 + /* 22437 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 172, + 11, + 0, // Skip to: 25432 + /* 22444 */ MCD_OPC_Decode, + 139, + 8, + 145, + 1, // Opcode: MVE_VCVTs32f32n + /* 22449 */ MCD_OPC_FilterValue, + 7, + 61, + 0, + 0, // Skip to: 22515 + /* 22454 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22457 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22486 + /* 22462 */ MCD_OPC_CheckPredicate, + 24, + 149, + 11, + 0, // Skip to: 25432 + /* 22467 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 142, + 11, + 0, // Skip to: 25432 + /* 22474 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 135, + 11, + 0, // Skip to: 25432 + /* 22481 */ MCD_OPC_Decode, + 145, + 8, + 145, + 1, // Opcode: MVE_VCVTu16f16n + /* 22486 */ MCD_OPC_FilterValue, + 59, + 125, + 11, + 0, // Skip to: 25432 + /* 22491 */ MCD_OPC_CheckPredicate, + 24, + 120, + 11, + 0, // Skip to: 25432 + /* 22496 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 113, + 11, + 0, // Skip to: 25432 + /* 22503 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 106, + 11, + 0, // Skip to: 25432 + /* 22510 */ MCD_OPC_Decode, + 151, + 8, + 145, + 1, // Opcode: MVE_VCVTu32f32n + /* 22515 */ MCD_OPC_FilterValue, + 9, + 61, + 0, + 0, // Skip to: 22581 + /* 22520 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22523 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22552 + /* 22528 */ MCD_OPC_CheckPredicate, + 24, + 83, + 11, + 0, // Skip to: 25432 + /* 22533 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 76, + 11, + 0, // Skip to: 25432 + /* 22540 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 69, + 11, + 0, // Skip to: 25432 + /* 22547 */ MCD_OPC_Decode, + 134, + 8, + 145, + 1, // Opcode: MVE_VCVTs16f16p + /* 22552 */ MCD_OPC_FilterValue, + 59, + 59, + 11, + 0, // Skip to: 25432 + /* 22557 */ MCD_OPC_CheckPredicate, + 24, + 54, + 11, + 0, // Skip to: 25432 + /* 22562 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 47, + 11, + 0, // Skip to: 25432 + /* 22569 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 40, + 11, + 0, // Skip to: 25432 + /* 22576 */ MCD_OPC_Decode, + 140, + 8, + 145, + 1, // Opcode: MVE_VCVTs32f32p + /* 22581 */ MCD_OPC_FilterValue, + 11, + 61, + 0, + 0, // Skip to: 22647 + /* 22586 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22589 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22618 + /* 22594 */ MCD_OPC_CheckPredicate, + 24, + 17, + 11, + 0, // Skip to: 25432 + /* 22599 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 10, + 11, + 0, // Skip to: 25432 + /* 22606 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 3, + 11, + 0, // Skip to: 25432 + /* 22613 */ MCD_OPC_Decode, + 146, + 8, + 145, + 1, // Opcode: MVE_VCVTu16f16p + /* 22618 */ MCD_OPC_FilterValue, + 59, + 249, + 10, + 0, // Skip to: 25432 + /* 22623 */ MCD_OPC_CheckPredicate, + 24, + 244, + 10, + 0, // Skip to: 25432 + /* 22628 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 237, + 10, + 0, // Skip to: 25432 + /* 22635 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 230, + 10, + 0, // Skip to: 25432 + /* 22642 */ MCD_OPC_Decode, + 152, + 8, + 145, + 1, // Opcode: MVE_VCVTu32f32p + /* 22647 */ MCD_OPC_FilterValue, + 13, + 148, + 0, + 0, // Skip to: 22800 + /* 22652 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22655 */ MCD_OPC_FilterValue, + 49, + 24, + 0, + 0, // Skip to: 22684 + /* 22660 */ MCD_OPC_CheckPredicate, + 22, + 207, + 10, + 0, // Skip to: 25432 + /* 22665 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 200, + 10, + 0, // Skip to: 25432 + /* 22672 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 193, + 10, + 0, // Skip to: 25432 + /* 22679 */ MCD_OPC_Decode, + 169, + 7, + 145, + 1, // Opcode: MVE_VABSs8 + /* 22684 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 22713 + /* 22689 */ MCD_OPC_CheckPredicate, + 22, + 178, + 10, + 0, // Skip to: 25432 + /* 22694 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 171, + 10, + 0, // Skip to: 25432 + /* 22701 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 164, + 10, + 0, // Skip to: 25432 + /* 22708 */ MCD_OPC_Decode, + 167, + 7, + 145, + 1, // Opcode: MVE_VABSs16 + /* 22713 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22742 + /* 22718 */ MCD_OPC_CheckPredicate, + 24, + 149, + 10, + 0, // Skip to: 25432 + /* 22723 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 142, + 10, + 0, // Skip to: 25432 + /* 22730 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 135, + 10, + 0, // Skip to: 25432 + /* 22737 */ MCD_OPC_Decode, + 132, + 8, + 145, + 1, // Opcode: MVE_VCVTs16f16m + /* 22742 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 22771 + /* 22747 */ MCD_OPC_CheckPredicate, + 22, + 120, + 10, + 0, // Skip to: 25432 + /* 22752 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 113, + 10, + 0, // Skip to: 25432 + /* 22759 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 106, + 10, + 0, // Skip to: 25432 + /* 22766 */ MCD_OPC_Decode, + 168, + 7, + 145, + 1, // Opcode: MVE_VABSs32 + /* 22771 */ MCD_OPC_FilterValue, + 59, + 96, + 10, + 0, // Skip to: 25432 + /* 22776 */ MCD_OPC_CheckPredicate, + 24, + 91, + 10, + 0, // Skip to: 25432 + /* 22781 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 84, + 10, + 0, // Skip to: 25432 + /* 22788 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 77, + 10, + 0, // Skip to: 25432 + /* 22795 */ MCD_OPC_Decode, + 138, + 8, + 145, + 1, // Opcode: MVE_VCVTs32f32m + /* 22800 */ MCD_OPC_FilterValue, + 15, + 148, + 0, + 0, // Skip to: 22953 + /* 22805 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22808 */ MCD_OPC_FilterValue, + 49, + 24, + 0, + 0, // Skip to: 22837 + /* 22813 */ MCD_OPC_CheckPredicate, + 22, + 54, + 10, + 0, // Skip to: 25432 + /* 22818 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 47, + 10, + 0, // Skip to: 25432 + /* 22825 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 40, + 10, + 0, // Skip to: 25432 + /* 22832 */ MCD_OPC_Decode, + 211, + 10, + 145, + 1, // Opcode: MVE_VNEGs8 + /* 22837 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 22866 + /* 22842 */ MCD_OPC_CheckPredicate, + 22, + 25, + 10, + 0, // Skip to: 25432 + /* 22847 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 18, + 10, + 0, // Skip to: 25432 + /* 22854 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 11, + 10, + 0, // Skip to: 25432 + /* 22861 */ MCD_OPC_Decode, + 209, + 10, + 145, + 1, // Opcode: MVE_VNEGs16 + /* 22866 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 22895 + /* 22871 */ MCD_OPC_CheckPredicate, + 24, + 252, + 9, + 0, // Skip to: 25432 + /* 22876 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 245, + 9, + 0, // Skip to: 25432 + /* 22883 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 238, + 9, + 0, // Skip to: 25432 + /* 22890 */ MCD_OPC_Decode, + 144, + 8, + 145, + 1, // Opcode: MVE_VCVTu16f16m + /* 22895 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 22924 + /* 22900 */ MCD_OPC_CheckPredicate, + 22, + 223, + 9, + 0, // Skip to: 25432 + /* 22905 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 216, + 9, + 0, // Skip to: 25432 + /* 22912 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 209, + 9, + 0, // Skip to: 25432 + /* 22919 */ MCD_OPC_Decode, + 210, + 10, + 145, + 1, // Opcode: MVE_VNEGs32 + /* 22924 */ MCD_OPC_FilterValue, + 59, + 199, + 9, + 0, // Skip to: 25432 + /* 22929 */ MCD_OPC_CheckPredicate, + 24, + 194, + 9, + 0, // Skip to: 25432 + /* 22934 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 187, + 9, + 0, // Skip to: 25432 + /* 22941 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 180, + 9, + 0, // Skip to: 25432 + /* 22948 */ MCD_OPC_Decode, + 150, + 8, + 145, + 1, // Opcode: MVE_VCVTu32f32m + /* 22953 */ MCD_OPC_FilterValue, + 17, + 148, + 0, + 0, // Skip to: 23106 + /* 22958 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 22961 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 22990 + /* 22966 */ MCD_OPC_CheckPredicate, + 22, + 157, + 9, + 0, // Skip to: 25432 + /* 22971 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 150, + 9, + 0, // Skip to: 25432 + /* 22978 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 143, + 9, + 0, // Skip to: 25432 + /* 22985 */ MCD_OPC_Decode, + 212, + 7, + 145, + 1, // Opcode: MVE_VCLSs8 + /* 22990 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 23019 + /* 22995 */ MCD_OPC_CheckPredicate, + 22, + 128, + 9, + 0, // Skip to: 25432 + /* 23000 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 121, + 9, + 0, // Skip to: 25432 + /* 23007 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 114, + 9, + 0, // Skip to: 25432 + /* 23014 */ MCD_OPC_Decode, + 210, + 7, + 145, + 1, // Opcode: MVE_VCLSs16 + /* 23019 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23048 + /* 23024 */ MCD_OPC_CheckPredicate, + 24, + 99, + 9, + 0, // Skip to: 25432 + /* 23029 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 92, + 9, + 0, // Skip to: 25432 + /* 23036 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 85, + 9, + 0, // Skip to: 25432 + /* 23043 */ MCD_OPC_Decode, + 154, + 12, + 145, + 1, // Opcode: MVE_VRINTf16N + /* 23048 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 23077 + /* 23053 */ MCD_OPC_CheckPredicate, + 22, + 70, + 9, + 0, // Skip to: 25432 + /* 23058 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 63, + 9, + 0, // Skip to: 25432 + /* 23065 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 56, + 9, + 0, // Skip to: 25432 + /* 23072 */ MCD_OPC_Decode, + 211, + 7, + 145, + 1, // Opcode: MVE_VCLSs32 + /* 23077 */ MCD_OPC_FilterValue, + 58, + 46, + 9, + 0, // Skip to: 25432 + /* 23082 */ MCD_OPC_CheckPredicate, + 24, + 41, + 9, + 0, // Skip to: 25432 + /* 23087 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 34, + 9, + 0, // Skip to: 25432 + /* 23094 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 27, + 9, + 0, // Skip to: 25432 + /* 23101 */ MCD_OPC_Decode, + 160, + 12, + 145, + 1, // Opcode: MVE_VRINTf32N + /* 23106 */ MCD_OPC_FilterValue, + 19, + 148, + 0, + 0, // Skip to: 23259 + /* 23111 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23114 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 23143 + /* 23119 */ MCD_OPC_CheckPredicate, + 22, + 4, + 9, + 0, // Skip to: 25432 + /* 23124 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 253, + 8, + 0, // Skip to: 25432 + /* 23131 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 246, + 8, + 0, // Skip to: 25432 + /* 23138 */ MCD_OPC_Decode, + 215, + 7, + 145, + 1, // Opcode: MVE_VCLZs8 + /* 23143 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 23172 + /* 23148 */ MCD_OPC_CheckPredicate, + 22, + 231, + 8, + 0, // Skip to: 25432 + /* 23153 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 224, + 8, + 0, // Skip to: 25432 + /* 23160 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 217, + 8, + 0, // Skip to: 25432 + /* 23167 */ MCD_OPC_Decode, + 213, + 7, + 145, + 1, // Opcode: MVE_VCLZs16 + /* 23172 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23201 + /* 23177 */ MCD_OPC_CheckPredicate, + 24, + 202, + 8, + 0, // Skip to: 25432 + /* 23182 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 195, + 8, + 0, // Skip to: 25432 + /* 23189 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 188, + 8, + 0, // Skip to: 25432 + /* 23196 */ MCD_OPC_Decode, + 156, + 12, + 145, + 1, // Opcode: MVE_VRINTf16X + /* 23201 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 23230 + /* 23206 */ MCD_OPC_CheckPredicate, + 22, + 173, + 8, + 0, // Skip to: 25432 + /* 23211 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 166, + 8, + 0, // Skip to: 25432 + /* 23218 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 159, + 8, + 0, // Skip to: 25432 + /* 23225 */ MCD_OPC_Decode, + 214, + 7, + 145, + 1, // Opcode: MVE_VCLZs32 + /* 23230 */ MCD_OPC_FilterValue, + 58, + 149, + 8, + 0, // Skip to: 25432 + /* 23235 */ MCD_OPC_CheckPredicate, + 24, + 144, + 8, + 0, // Skip to: 25432 + /* 23240 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 137, + 8, + 0, // Skip to: 25432 + /* 23247 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 130, + 8, + 0, // Skip to: 25432 + /* 23254 */ MCD_OPC_Decode, + 162, + 12, + 145, + 1, // Opcode: MVE_VRINTf32X + /* 23259 */ MCD_OPC_FilterValue, + 21, + 61, + 0, + 0, // Skip to: 23325 + /* 23264 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23267 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23296 + /* 23272 */ MCD_OPC_CheckPredicate, + 24, + 107, + 8, + 0, // Skip to: 25432 + /* 23277 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 100, + 8, + 0, // Skip to: 25432 + /* 23284 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 93, + 8, + 0, // Skip to: 25432 + /* 23291 */ MCD_OPC_Decode, + 152, + 12, + 145, + 1, // Opcode: MVE_VRINTf16A + /* 23296 */ MCD_OPC_FilterValue, + 58, + 83, + 8, + 0, // Skip to: 25432 + /* 23301 */ MCD_OPC_CheckPredicate, + 24, + 78, + 8, + 0, // Skip to: 25432 + /* 23306 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 71, + 8, + 0, // Skip to: 25432 + /* 23313 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 64, + 8, + 0, // Skip to: 25432 + /* 23320 */ MCD_OPC_Decode, + 158, + 12, + 145, + 1, // Opcode: MVE_VRINTf32A + /* 23325 */ MCD_OPC_FilterValue, + 23, + 90, + 0, + 0, // Skip to: 23420 + /* 23330 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23333 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 23362 + /* 23338 */ MCD_OPC_CheckPredicate, + 22, + 41, + 8, + 0, // Skip to: 25432 + /* 23343 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 34, + 8, + 0, // Skip to: 25432 + /* 23350 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 27, + 8, + 0, // Skip to: 25432 + /* 23357 */ MCD_OPC_Decode, + 204, + 10, + 145, + 1, // Opcode: MVE_VMVN + /* 23362 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23391 + /* 23367 */ MCD_OPC_CheckPredicate, + 24, + 12, + 8, + 0, // Skip to: 25432 + /* 23372 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 5, + 8, + 0, // Skip to: 25432 + /* 23379 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 254, + 7, + 0, // Skip to: 25432 + /* 23386 */ MCD_OPC_Decode, + 157, + 12, + 145, + 1, // Opcode: MVE_VRINTf16Z + /* 23391 */ MCD_OPC_FilterValue, + 58, + 244, + 7, + 0, // Skip to: 25432 + /* 23396 */ MCD_OPC_CheckPredicate, + 24, + 239, + 7, + 0, // Skip to: 25432 + /* 23401 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 232, + 7, + 0, // Skip to: 25432 + /* 23408 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 225, + 7, + 0, // Skip to: 25432 + /* 23415 */ MCD_OPC_Decode, + 163, + 12, + 145, + 1, // Opcode: MVE_VRINTf32Z + /* 23420 */ MCD_OPC_FilterValue, + 25, + 61, + 0, + 0, // Skip to: 23486 + /* 23425 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23428 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 23457 + /* 23433 */ MCD_OPC_CheckPredicate, + 24, + 202, + 7, + 0, // Skip to: 25432 + /* 23438 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 195, + 7, + 0, // Skip to: 25432 + /* 23445 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 188, + 7, + 0, // Skip to: 25432 + /* 23452 */ MCD_OPC_Decode, + 249, + 7, + 145, + 1, // Opcode: MVE_VCVTf16s16n + /* 23457 */ MCD_OPC_FilterValue, + 59, + 178, + 7, + 0, // Skip to: 25432 + /* 23462 */ MCD_OPC_CheckPredicate, + 24, + 173, + 7, + 0, // Skip to: 25432 + /* 23467 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 166, + 7, + 0, // Skip to: 25432 + /* 23474 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 159, + 7, + 0, // Skip to: 25432 + /* 23481 */ MCD_OPC_Decode, + 255, + 7, + 145, + 1, // Opcode: MVE_VCVTf32s32n + /* 23486 */ MCD_OPC_FilterValue, + 27, + 119, + 0, + 0, // Skip to: 23610 + /* 23491 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23494 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23523 + /* 23499 */ MCD_OPC_CheckPredicate, + 24, + 136, + 7, + 0, // Skip to: 25432 + /* 23504 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 129, + 7, + 0, // Skip to: 25432 + /* 23511 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 122, + 7, + 0, // Skip to: 25432 + /* 23518 */ MCD_OPC_Decode, + 153, + 12, + 145, + 1, // Opcode: MVE_VRINTf16M + /* 23523 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 23552 + /* 23528 */ MCD_OPC_CheckPredicate, + 24, + 107, + 7, + 0, // Skip to: 25432 + /* 23533 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 100, + 7, + 0, // Skip to: 25432 + /* 23540 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 93, + 7, + 0, // Skip to: 25432 + /* 23547 */ MCD_OPC_Decode, + 251, + 7, + 145, + 1, // Opcode: MVE_VCVTf16u16n + /* 23552 */ MCD_OPC_FilterValue, + 58, + 24, + 0, + 0, // Skip to: 23581 + /* 23557 */ MCD_OPC_CheckPredicate, + 24, + 78, + 7, + 0, // Skip to: 25432 + /* 23562 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 71, + 7, + 0, // Skip to: 25432 + /* 23569 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 64, + 7, + 0, // Skip to: 25432 + /* 23576 */ MCD_OPC_Decode, + 159, + 12, + 145, + 1, // Opcode: MVE_VRINTf32M + /* 23581 */ MCD_OPC_FilterValue, + 59, + 54, + 7, + 0, // Skip to: 25432 + /* 23586 */ MCD_OPC_CheckPredicate, + 24, + 49, + 7, + 0, // Skip to: 25432 + /* 23591 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 42, + 7, + 0, // Skip to: 25432 + /* 23598 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 35, + 7, + 0, // Skip to: 25432 + /* 23605 */ MCD_OPC_Decode, + 129, + 8, + 145, + 1, // Opcode: MVE_VCVTf32u32n + /* 23610 */ MCD_OPC_FilterValue, + 29, + 206, + 0, + 0, // Skip to: 23821 + /* 23615 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23618 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 23647 + /* 23623 */ MCD_OPC_CheckPredicate, + 22, + 12, + 7, + 0, // Skip to: 25432 + /* 23628 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 5, + 7, + 0, // Skip to: 25432 + /* 23635 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 254, + 6, + 0, // Skip to: 25432 + /* 23642 */ MCD_OPC_Decode, + 243, + 10, + 145, + 1, // Opcode: MVE_VQABSs8 + /* 23647 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 23676 + /* 23652 */ MCD_OPC_CheckPredicate, + 22, + 239, + 6, + 0, // Skip to: 25432 + /* 23657 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 232, + 6, + 0, // Skip to: 25432 + /* 23664 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 225, + 6, + 0, // Skip to: 25432 + /* 23671 */ MCD_OPC_Decode, + 241, + 10, + 145, + 1, // Opcode: MVE_VQABSs16 + /* 23676 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 23705 + /* 23681 */ MCD_OPC_CheckPredicate, + 24, + 210, + 6, + 0, // Skip to: 25432 + /* 23686 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 203, + 6, + 0, // Skip to: 25432 + /* 23693 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 196, + 6, + 0, // Skip to: 25432 + /* 23700 */ MCD_OPC_Decode, + 165, + 7, + 145, + 1, // Opcode: MVE_VABSf16 + /* 23705 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 23734 + /* 23710 */ MCD_OPC_CheckPredicate, + 24, + 181, + 6, + 0, // Skip to: 25432 + /* 23715 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 174, + 6, + 0, // Skip to: 25432 + /* 23722 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 167, + 6, + 0, // Skip to: 25432 + /* 23729 */ MCD_OPC_Decode, + 135, + 8, + 145, + 1, // Opcode: MVE_VCVTs16f16z + /* 23734 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 23763 + /* 23739 */ MCD_OPC_CheckPredicate, + 22, + 152, + 6, + 0, // Skip to: 25432 + /* 23744 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 145, + 6, + 0, // Skip to: 25432 + /* 23751 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 138, + 6, + 0, // Skip to: 25432 + /* 23758 */ MCD_OPC_Decode, + 242, + 10, + 145, + 1, // Opcode: MVE_VQABSs32 + /* 23763 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 23792 + /* 23768 */ MCD_OPC_CheckPredicate, + 24, + 123, + 6, + 0, // Skip to: 25432 + /* 23773 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 116, + 6, + 0, // Skip to: 25432 + /* 23780 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 109, + 6, + 0, // Skip to: 25432 + /* 23787 */ MCD_OPC_Decode, + 166, + 7, + 145, + 1, // Opcode: MVE_VABSf32 + /* 23792 */ MCD_OPC_FilterValue, + 59, + 99, + 6, + 0, // Skip to: 25432 + /* 23797 */ MCD_OPC_CheckPredicate, + 24, + 94, + 6, + 0, // Skip to: 25432 + /* 23802 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 87, + 6, + 0, // Skip to: 25432 + /* 23809 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 80, + 6, + 0, // Skip to: 25432 + /* 23816 */ MCD_OPC_Decode, + 141, + 8, + 145, + 1, // Opcode: MVE_VCVTs32f32z + /* 23821 */ MCD_OPC_FilterValue, + 31, + 70, + 6, + 0, // Skip to: 25432 + /* 23826 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 23829 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 23858 + /* 23834 */ MCD_OPC_CheckPredicate, + 22, + 57, + 6, + 0, // Skip to: 25432 + /* 23839 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 50, + 6, + 0, // Skip to: 25432 + /* 23846 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 43, + 6, + 0, // Skip to: 25432 + /* 23853 */ MCD_OPC_Decode, + 174, + 11, + 145, + 1, // Opcode: MVE_VQNEGs8 + /* 23858 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 23887 + /* 23863 */ MCD_OPC_CheckPredicate, + 22, + 28, + 6, + 0, // Skip to: 25432 + /* 23868 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 21, + 6, + 0, // Skip to: 25432 + /* 23875 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 14, + 6, + 0, // Skip to: 25432 + /* 23882 */ MCD_OPC_Decode, + 172, + 11, + 145, + 1, // Opcode: MVE_VQNEGs16 + /* 23887 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 23916 + /* 23892 */ MCD_OPC_CheckPredicate, + 24, + 255, + 5, + 0, // Skip to: 25432 + /* 23897 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 248, + 5, + 0, // Skip to: 25432 + /* 23904 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 241, + 5, + 0, // Skip to: 25432 + /* 23911 */ MCD_OPC_Decode, + 207, + 10, + 145, + 1, // Opcode: MVE_VNEGf16 + /* 23916 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 23945 + /* 23921 */ MCD_OPC_CheckPredicate, + 24, + 226, + 5, + 0, // Skip to: 25432 + /* 23926 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 219, + 5, + 0, // Skip to: 25432 + /* 23933 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 212, + 5, + 0, // Skip to: 25432 + /* 23940 */ MCD_OPC_Decode, + 155, + 12, + 145, + 1, // Opcode: MVE_VRINTf16P + /* 23945 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 23974 + /* 23950 */ MCD_OPC_CheckPredicate, + 24, + 197, + 5, + 0, // Skip to: 25432 + /* 23955 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 190, + 5, + 0, // Skip to: 25432 + /* 23962 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 183, + 5, + 0, // Skip to: 25432 + /* 23969 */ MCD_OPC_Decode, + 147, + 8, + 145, + 1, // Opcode: MVE_VCVTu16f16z + /* 23974 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 24003 + /* 23979 */ MCD_OPC_CheckPredicate, + 22, + 168, + 5, + 0, // Skip to: 25432 + /* 23984 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 161, + 5, + 0, // Skip to: 25432 + /* 23991 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 154, + 5, + 0, // Skip to: 25432 + /* 23998 */ MCD_OPC_Decode, + 173, + 11, + 145, + 1, // Opcode: MVE_VQNEGs32 + /* 24003 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 24032 + /* 24008 */ MCD_OPC_CheckPredicate, + 24, + 139, + 5, + 0, // Skip to: 25432 + /* 24013 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 132, + 5, + 0, // Skip to: 25432 + /* 24020 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 125, + 5, + 0, // Skip to: 25432 + /* 24027 */ MCD_OPC_Decode, + 208, + 10, + 145, + 1, // Opcode: MVE_VNEGf32 + /* 24032 */ MCD_OPC_FilterValue, + 58, + 24, + 0, + 0, // Skip to: 24061 + /* 24037 */ MCD_OPC_CheckPredicate, + 24, + 110, + 5, + 0, // Skip to: 25432 + /* 24042 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 103, + 5, + 0, // Skip to: 25432 + /* 24049 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 96, + 5, + 0, // Skip to: 25432 + /* 24056 */ MCD_OPC_Decode, + 161, + 12, + 145, + 1, // Opcode: MVE_VRINTf32P + /* 24061 */ MCD_OPC_FilterValue, + 59, + 86, + 5, + 0, // Skip to: 25432 + /* 24066 */ MCD_OPC_CheckPredicate, + 24, + 81, + 5, + 0, // Skip to: 25432 + /* 24071 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 74, + 5, + 0, // Skip to: 25432 + /* 24078 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 67, + 5, + 0, // Skip to: 25432 + /* 24085 */ MCD_OPC_Decode, + 153, + 8, + 145, + 1, // Opcode: MVE_VCVTu32f32z + /* 24090 */ MCD_OPC_FilterValue, + 1, + 57, + 5, + 0, // Skip to: 25432 + /* 24095 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 24098 */ MCD_OPC_FilterValue, + 0, + 51, + 3, + 0, // Skip to: 24922 + /* 24103 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 24106 */ MCD_OPC_FilterValue, + 0, + 25, + 2, + 0, // Skip to: 24648 + /* 24111 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 24114 */ MCD_OPC_FilterValue, + 0, + 255, + 0, + 0, // Skip to: 24374 + /* 24119 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 24122 */ MCD_OPC_FilterValue, + 2, + 129, + 0, + 0, // Skip to: 24256 + /* 24127 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 24130 */ MCD_OPC_FilterValue, + 0, + 17, + 5, + 0, // Skip to: 25432 + /* 24135 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 24138 */ MCD_OPC_FilterValue, + 7, + 9, + 5, + 0, // Skip to: 25432 + /* 24143 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 24146 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 24161 + /* 24151 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 24176 + /* 24156 */ MCD_OPC_Decode, + 171, + 10, + 188, + 1, // Opcode: MVE_VMOVimmi8 + /* 24161 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 24176 + /* 24166 */ MCD_OPC_CheckPredicate, + 22, + 5, + 0, + 0, // Skip to: 24176 + /* 24171 */ MCD_OPC_Decode, + 167, + 10, + 188, + 1, // Opcode: MVE_VMOVimmf32 + /* 24176 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 24179 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 24201 + /* 24184 */ MCD_OPC_CheckPredicate, + 22, + 57, + 0, + 0, // Skip to: 24246 + /* 24189 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 24246 + /* 24196 */ MCD_OPC_Decode, + 168, + 10, + 188, + 1, // Opcode: MVE_VMOVimmi16 + /* 24201 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 24246 + /* 24206 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 24209 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 24224 + /* 24214 */ MCD_OPC_CheckPredicate, + 22, + 27, + 0, + 0, // Skip to: 24246 + /* 24219 */ MCD_OPC_Decode, + 215, + 10, + 189, + 1, // Opcode: MVE_VORRimmi32 + /* 24224 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 24246 + /* 24229 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 24246 + /* 24234 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 24246 + /* 24241 */ MCD_OPC_Decode, + 214, + 10, + 190, + 1, // Opcode: MVE_VORRimmi16 + /* 24246 */ MCD_OPC_CheckPredicate, + 22, + 157, + 4, + 0, // Skip to: 25432 + /* 24251 */ MCD_OPC_Decode, + 169, + 10, + 188, + 1, // Opcode: MVE_VMOVimmi32 + /* 24256 */ MCD_OPC_FilterValue, + 3, + 147, + 4, + 0, // Skip to: 25432 + /* 24261 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 24264 */ MCD_OPC_FilterValue, + 0, + 139, + 4, + 0, // Skip to: 25432 + /* 24269 */ MCD_OPC_ExtractField, + 29, + 3, // Inst{31-29} ... + /* 24272 */ MCD_OPC_FilterValue, + 7, + 131, + 4, + 0, // Skip to: 25432 + /* 24277 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 24294 + /* 24282 */ MCD_OPC_CheckField, + 8, + 4, + 14, + 5, + 0, + 0, // Skip to: 24294 + /* 24289 */ MCD_OPC_Decode, + 170, + 10, + 188, + 1, // Opcode: MVE_VMOVimmi64 + /* 24294 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 24297 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 24319 + /* 24302 */ MCD_OPC_CheckPredicate, + 22, + 57, + 0, + 0, // Skip to: 24364 + /* 24307 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 24364 + /* 24314 */ MCD_OPC_Decode, + 205, + 10, + 188, + 1, // Opcode: MVE_VMVNimmi16 + /* 24319 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 24364 + /* 24324 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 24327 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 24342 + /* 24332 */ MCD_OPC_CheckPredicate, + 22, + 27, + 0, + 0, // Skip to: 24364 + /* 24337 */ MCD_OPC_Decode, + 201, + 7, + 189, + 1, // Opcode: MVE_VBICimmi32 + /* 24342 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 24364 + /* 24347 */ MCD_OPC_CheckPredicate, + 22, + 12, + 0, + 0, // Skip to: 24364 + /* 24352 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 24364 + /* 24359 */ MCD_OPC_Decode, + 200, + 7, + 190, + 1, // Opcode: MVE_VBICimmi16 + /* 24364 */ MCD_OPC_CheckPredicate, + 22, + 39, + 4, + 0, // Skip to: 25432 + /* 24369 */ MCD_OPC_Decode, + 206, + 10, + 188, + 1, // Opcode: MVE_VMVNimmi32 + /* 24374 */ MCD_OPC_FilterValue, + 1, + 29, + 4, + 0, // Skip to: 25432 + /* 24379 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 24382 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 24434 + /* 24387 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24390 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24412 + /* 24395 */ MCD_OPC_CheckPredicate, + 22, + 8, + 4, + 0, // Skip to: 25432 + /* 24400 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 1, + 4, + 0, // Skip to: 25432 + /* 24407 */ MCD_OPC_Decode, + 242, + 12, + 191, + 1, // Opcode: MVE_VSHR_imms8 + /* 24412 */ MCD_OPC_FilterValue, + 15, + 247, + 3, + 0, // Skip to: 25432 + /* 24417 */ MCD_OPC_CheckPredicate, + 22, + 242, + 3, + 0, // Skip to: 25432 + /* 24422 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 235, + 3, + 0, // Skip to: 25432 + /* 24429 */ MCD_OPC_Decode, + 245, + 12, + 191, + 1, // Opcode: MVE_VSHR_immu8 + /* 24434 */ MCD_OPC_FilterValue, + 9, + 47, + 0, + 0, // Skip to: 24486 + /* 24439 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24442 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24464 + /* 24447 */ MCD_OPC_CheckPredicate, + 22, + 212, + 3, + 0, // Skip to: 25432 + /* 24452 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 205, + 3, + 0, // Skip to: 25432 + /* 24459 */ MCD_OPC_Decode, + 198, + 12, + 191, + 1, // Opcode: MVE_VRSHR_imms8 + /* 24464 */ MCD_OPC_FilterValue, + 15, + 195, + 3, + 0, // Skip to: 25432 + /* 24469 */ MCD_OPC_CheckPredicate, + 22, + 190, + 3, + 0, // Skip to: 25432 + /* 24474 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 183, + 3, + 0, // Skip to: 25432 + /* 24481 */ MCD_OPC_Decode, + 201, + 12, + 191, + 1, // Opcode: MVE_VRSHR_immu8 + /* 24486 */ MCD_OPC_FilterValue, + 17, + 24, + 0, + 0, // Skip to: 24515 + /* 24491 */ MCD_OPC_CheckPredicate, + 22, + 168, + 3, + 0, // Skip to: 25432 + /* 24496 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 161, + 3, + 0, // Skip to: 25432 + /* 24503 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 154, + 3, + 0, // Skip to: 25432 + /* 24510 */ MCD_OPC_Decode, + 251, + 12, + 182, + 1, // Opcode: MVE_VSRIimm8 + /* 24515 */ MCD_OPC_FilterValue, + 21, + 47, + 0, + 0, // Skip to: 24567 + /* 24520 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24523 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24545 + /* 24528 */ MCD_OPC_CheckPredicate, + 22, + 131, + 3, + 0, // Skip to: 25432 + /* 24533 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 124, + 3, + 0, // Skip to: 25432 + /* 24540 */ MCD_OPC_Decode, + 229, + 12, + 184, + 1, // Opcode: MVE_VSHL_immi8 + /* 24545 */ MCD_OPC_FilterValue, + 15, + 114, + 3, + 0, // Skip to: 25432 + /* 24550 */ MCD_OPC_CheckPredicate, + 22, + 109, + 3, + 0, // Skip to: 25432 + /* 24555 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 102, + 3, + 0, // Skip to: 25432 + /* 24562 */ MCD_OPC_Decode, + 248, + 12, + 192, + 1, // Opcode: MVE_VSLIimm8 + /* 24567 */ MCD_OPC_FilterValue, + 25, + 24, + 0, + 0, // Skip to: 24596 + /* 24572 */ MCD_OPC_CheckPredicate, + 22, + 87, + 3, + 0, // Skip to: 25432 + /* 24577 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 80, + 3, + 0, // Skip to: 25432 + /* 24584 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 73, + 3, + 0, // Skip to: 25432 + /* 24591 */ MCD_OPC_Decode, + 225, + 11, + 184, + 1, // Opcode: MVE_VQSHLU_imms8 + /* 24596 */ MCD_OPC_FilterValue, + 29, + 63, + 3, + 0, // Skip to: 25432 + /* 24601 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24604 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24626 + /* 24609 */ MCD_OPC_CheckPredicate, + 22, + 50, + 3, + 0, // Skip to: 25432 + /* 24614 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 43, + 3, + 0, // Skip to: 25432 + /* 24621 */ MCD_OPC_Decode, + 240, + 11, + 184, + 1, // Opcode: MVE_VQSHLimms8 + /* 24626 */ MCD_OPC_FilterValue, + 15, + 33, + 3, + 0, // Skip to: 25432 + /* 24631 */ MCD_OPC_CheckPredicate, + 22, + 28, + 3, + 0, // Skip to: 25432 + /* 24636 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 21, + 3, + 0, // Skip to: 25432 + /* 24643 */ MCD_OPC_Decode, + 243, + 11, + 184, + 1, // Opcode: MVE_VQSHLimmu8 + /* 24648 */ MCD_OPC_FilterValue, + 1, + 11, + 3, + 0, // Skip to: 25432 + /* 24653 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 24656 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 24708 + /* 24661 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24664 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24686 + /* 24669 */ MCD_OPC_CheckPredicate, + 22, + 246, + 2, + 0, // Skip to: 25432 + /* 24674 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 239, + 2, + 0, // Skip to: 25432 + /* 24681 */ MCD_OPC_Decode, + 240, + 12, + 193, + 1, // Opcode: MVE_VSHR_imms16 + /* 24686 */ MCD_OPC_FilterValue, + 15, + 229, + 2, + 0, // Skip to: 25432 + /* 24691 */ MCD_OPC_CheckPredicate, + 22, + 224, + 2, + 0, // Skip to: 25432 + /* 24696 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 217, + 2, + 0, // Skip to: 25432 + /* 24703 */ MCD_OPC_Decode, + 243, + 12, + 193, + 1, // Opcode: MVE_VSHR_immu16 + /* 24708 */ MCD_OPC_FilterValue, + 9, + 47, + 0, + 0, // Skip to: 24760 + /* 24713 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24716 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24738 + /* 24721 */ MCD_OPC_CheckPredicate, + 22, + 194, + 2, + 0, // Skip to: 25432 + /* 24726 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 187, + 2, + 0, // Skip to: 25432 + /* 24733 */ MCD_OPC_Decode, + 196, + 12, + 193, + 1, // Opcode: MVE_VRSHR_imms16 + /* 24738 */ MCD_OPC_FilterValue, + 15, + 177, + 2, + 0, // Skip to: 25432 + /* 24743 */ MCD_OPC_CheckPredicate, + 22, + 172, + 2, + 0, // Skip to: 25432 + /* 24748 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 165, + 2, + 0, // Skip to: 25432 + /* 24755 */ MCD_OPC_Decode, + 199, + 12, + 193, + 1, // Opcode: MVE_VRSHR_immu16 + /* 24760 */ MCD_OPC_FilterValue, + 17, + 24, + 0, + 0, // Skip to: 24789 + /* 24765 */ MCD_OPC_CheckPredicate, + 22, + 150, + 2, + 0, // Skip to: 25432 + /* 24770 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 143, + 2, + 0, // Skip to: 25432 + /* 24777 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 136, + 2, + 0, // Skip to: 25432 + /* 24784 */ MCD_OPC_Decode, + 249, + 12, + 183, + 1, // Opcode: MVE_VSRIimm16 + /* 24789 */ MCD_OPC_FilterValue, + 21, + 47, + 0, + 0, // Skip to: 24841 + /* 24794 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24797 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24819 + /* 24802 */ MCD_OPC_CheckPredicate, + 22, + 113, + 2, + 0, // Skip to: 25432 + /* 24807 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 106, + 2, + 0, // Skip to: 25432 + /* 24814 */ MCD_OPC_Decode, + 227, + 12, + 185, + 1, // Opcode: MVE_VSHL_immi16 + /* 24819 */ MCD_OPC_FilterValue, + 15, + 96, + 2, + 0, // Skip to: 25432 + /* 24824 */ MCD_OPC_CheckPredicate, + 22, + 91, + 2, + 0, // Skip to: 25432 + /* 24829 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 84, + 2, + 0, // Skip to: 25432 + /* 24836 */ MCD_OPC_Decode, + 246, + 12, + 194, + 1, // Opcode: MVE_VSLIimm16 + /* 24841 */ MCD_OPC_FilterValue, + 25, + 24, + 0, + 0, // Skip to: 24870 + /* 24846 */ MCD_OPC_CheckPredicate, + 22, + 69, + 2, + 0, // Skip to: 25432 + /* 24851 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 62, + 2, + 0, // Skip to: 25432 + /* 24858 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 55, + 2, + 0, // Skip to: 25432 + /* 24865 */ MCD_OPC_Decode, + 223, + 11, + 185, + 1, // Opcode: MVE_VQSHLU_imms16 + /* 24870 */ MCD_OPC_FilterValue, + 29, + 45, + 2, + 0, // Skip to: 25432 + /* 24875 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24878 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24900 + /* 24883 */ MCD_OPC_CheckPredicate, + 22, + 32, + 2, + 0, // Skip to: 25432 + /* 24888 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 25, + 2, + 0, // Skip to: 25432 + /* 24895 */ MCD_OPC_Decode, + 238, + 11, + 185, + 1, // Opcode: MVE_VQSHLimms16 + /* 24900 */ MCD_OPC_FilterValue, + 15, + 15, + 2, + 0, // Skip to: 25432 + /* 24905 */ MCD_OPC_CheckPredicate, + 22, + 10, + 2, + 0, // Skip to: 25432 + /* 24910 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 3, + 2, + 0, // Skip to: 25432 + /* 24917 */ MCD_OPC_Decode, + 241, + 11, + 185, + 1, // Opcode: MVE_VQSHLimmu16 + /* 24922 */ MCD_OPC_FilterValue, + 1, + 249, + 1, + 0, // Skip to: 25432 + /* 24927 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 24930 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 24982 + /* 24935 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24938 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 24960 + /* 24943 */ MCD_OPC_CheckPredicate, + 22, + 228, + 1, + 0, // Skip to: 25432 + /* 24948 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 221, + 1, + 0, // Skip to: 25432 + /* 24955 */ MCD_OPC_Decode, + 241, + 12, + 195, + 1, // Opcode: MVE_VSHR_imms32 + /* 24960 */ MCD_OPC_FilterValue, + 15, + 211, + 1, + 0, // Skip to: 25432 + /* 24965 */ MCD_OPC_CheckPredicate, + 22, + 206, + 1, + 0, // Skip to: 25432 + /* 24970 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 199, + 1, + 0, // Skip to: 25432 + /* 24977 */ MCD_OPC_Decode, + 244, + 12, + 195, + 1, // Opcode: MVE_VSHR_immu32 + /* 24982 */ MCD_OPC_FilterValue, + 9, + 47, + 0, + 0, // Skip to: 25034 + /* 24987 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 24990 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 25012 + /* 24995 */ MCD_OPC_CheckPredicate, + 22, + 176, + 1, + 0, // Skip to: 25432 + /* 25000 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 169, + 1, + 0, // Skip to: 25432 + /* 25007 */ MCD_OPC_Decode, + 197, + 12, + 195, + 1, // Opcode: MVE_VRSHR_imms32 + /* 25012 */ MCD_OPC_FilterValue, + 15, + 159, + 1, + 0, // Skip to: 25432 + /* 25017 */ MCD_OPC_CheckPredicate, + 22, + 154, + 1, + 0, // Skip to: 25432 + /* 25022 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 147, + 1, + 0, // Skip to: 25432 + /* 25029 */ MCD_OPC_Decode, + 200, + 12, + 195, + 1, // Opcode: MVE_VRSHR_immu32 + /* 25034 */ MCD_OPC_FilterValue, + 17, + 24, + 0, + 0, // Skip to: 25063 + /* 25039 */ MCD_OPC_CheckPredicate, + 22, + 132, + 1, + 0, // Skip to: 25432 + /* 25044 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 125, + 1, + 0, // Skip to: 25432 + /* 25051 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 118, + 1, + 0, // Skip to: 25432 + /* 25058 */ MCD_OPC_Decode, + 250, + 12, + 196, + 1, // Opcode: MVE_VSRIimm32 + /* 25063 */ MCD_OPC_FilterValue, + 21, + 47, + 0, + 0, // Skip to: 25115 + /* 25068 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25071 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 25093 + /* 25076 */ MCD_OPC_CheckPredicate, + 22, + 95, + 1, + 0, // Skip to: 25432 + /* 25081 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 88, + 1, + 0, // Skip to: 25432 + /* 25088 */ MCD_OPC_Decode, + 228, + 12, + 197, + 1, // Opcode: MVE_VSHL_immi32 + /* 25093 */ MCD_OPC_FilterValue, + 15, + 78, + 1, + 0, // Skip to: 25432 + /* 25098 */ MCD_OPC_CheckPredicate, + 22, + 73, + 1, + 0, // Skip to: 25432 + /* 25103 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 66, + 1, + 0, // Skip to: 25432 + /* 25110 */ MCD_OPC_Decode, + 247, + 12, + 198, + 1, // Opcode: MVE_VSLIimm32 + /* 25115 */ MCD_OPC_FilterValue, + 25, + 24, + 0, + 0, // Skip to: 25144 + /* 25120 */ MCD_OPC_CheckPredicate, + 22, + 51, + 1, + 0, // Skip to: 25432 + /* 25125 */ MCD_OPC_CheckField, + 28, + 4, + 15, + 44, + 1, + 0, // Skip to: 25432 + /* 25132 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 37, + 1, + 0, // Skip to: 25432 + /* 25139 */ MCD_OPC_Decode, + 224, + 11, + 197, + 1, // Opcode: MVE_VQSHLU_imms32 + /* 25144 */ MCD_OPC_FilterValue, + 29, + 47, + 0, + 0, // Skip to: 25196 + /* 25149 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25152 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 25174 + /* 25157 */ MCD_OPC_CheckPredicate, + 22, + 14, + 1, + 0, // Skip to: 25432 + /* 25162 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 7, + 1, + 0, // Skip to: 25432 + /* 25169 */ MCD_OPC_Decode, + 239, + 11, + 197, + 1, // Opcode: MVE_VQSHLimms32 + /* 25174 */ MCD_OPC_FilterValue, + 15, + 253, + 0, + 0, // Skip to: 25432 + /* 25179 */ MCD_OPC_CheckPredicate, + 22, + 248, + 0, + 0, // Skip to: 25432 + /* 25184 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 241, + 0, + 0, // Skip to: 25432 + /* 25191 */ MCD_OPC_Decode, + 242, + 11, + 197, + 1, // Opcode: MVE_VQSHLimmu32 + /* 25196 */ MCD_OPC_FilterValue, + 49, + 61, + 0, + 0, // Skip to: 25262 + /* 25201 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25204 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 25233 + /* 25209 */ MCD_OPC_CheckPredicate, + 24, + 218, + 0, + 0, // Skip to: 25432 + /* 25214 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 211, + 0, + 0, // Skip to: 25432 + /* 25221 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 204, + 0, + 0, // Skip to: 25432 + /* 25228 */ MCD_OPC_Decode, + 248, + 7, + 199, + 1, // Opcode: MVE_VCVTf16s16_fix + /* 25233 */ MCD_OPC_FilterValue, + 15, + 194, + 0, + 0, // Skip to: 25432 + /* 25238 */ MCD_OPC_CheckPredicate, + 24, + 189, + 0, + 0, // Skip to: 25432 + /* 25243 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 182, + 0, + 0, // Skip to: 25432 + /* 25250 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 175, + 0, + 0, // Skip to: 25432 + /* 25257 */ MCD_OPC_Decode, + 250, + 7, + 199, + 1, // Opcode: MVE_VCVTf16u16_fix + /* 25262 */ MCD_OPC_FilterValue, + 53, + 61, + 0, + 0, // Skip to: 25328 + /* 25267 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25270 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 25299 + /* 25275 */ MCD_OPC_CheckPredicate, + 24, + 152, + 0, + 0, // Skip to: 25432 + /* 25280 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 145, + 0, + 0, // Skip to: 25432 + /* 25287 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 138, + 0, + 0, // Skip to: 25432 + /* 25294 */ MCD_OPC_Decode, + 130, + 8, + 199, + 1, // Opcode: MVE_VCVTs16f16_fix + /* 25299 */ MCD_OPC_FilterValue, + 15, + 128, + 0, + 0, // Skip to: 25432 + /* 25304 */ MCD_OPC_CheckPredicate, + 24, + 123, + 0, + 0, // Skip to: 25432 + /* 25309 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 116, + 0, + 0, // Skip to: 25432 + /* 25316 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 109, + 0, + 0, // Skip to: 25432 + /* 25323 */ MCD_OPC_Decode, + 142, + 8, + 199, + 1, // Opcode: MVE_VCVTu16f16_fix + /* 25328 */ MCD_OPC_FilterValue, + 57, + 47, + 0, + 0, // Skip to: 25380 + /* 25333 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25336 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 25358 + /* 25341 */ MCD_OPC_CheckPredicate, + 24, + 86, + 0, + 0, // Skip to: 25432 + /* 25346 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 79, + 0, + 0, // Skip to: 25432 + /* 25353 */ MCD_OPC_Decode, + 254, + 7, + 199, + 1, // Opcode: MVE_VCVTf32s32_fix + /* 25358 */ MCD_OPC_FilterValue, + 15, + 69, + 0, + 0, // Skip to: 25432 + /* 25363 */ MCD_OPC_CheckPredicate, + 24, + 64, + 0, + 0, // Skip to: 25432 + /* 25368 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 57, + 0, + 0, // Skip to: 25432 + /* 25375 */ MCD_OPC_Decode, + 128, + 8, + 199, + 1, // Opcode: MVE_VCVTf32u32_fix + /* 25380 */ MCD_OPC_FilterValue, + 61, + 47, + 0, + 0, // Skip to: 25432 + /* 25385 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 25388 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 25410 + /* 25393 */ MCD_OPC_CheckPredicate, + 24, + 34, + 0, + 0, // Skip to: 25432 + /* 25398 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 27, + 0, + 0, // Skip to: 25432 + /* 25405 */ MCD_OPC_Decode, + 136, + 8, + 199, + 1, // Opcode: MVE_VCVTs32f32_fix + /* 25410 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 25432 + /* 25415 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 25432 + /* 25420 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 5, + 0, + 0, // Skip to: 25432 + /* 25427 */ MCD_OPC_Decode, + 148, + 8, + 199, + 1, // Opcode: MVE_VCVTu32f32_fix + /* 25432 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableNEONData32[] = { -/* 0 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 3 */ MCD_OPC_FilterValue, 0, 221, 39, 0, // Skip to: 10213 -/* 8 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11 */ MCD_OPC_FilterValue, 0, 73, 6, 0, // Skip to: 1625 -/* 16 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 19 */ MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 145 -/* 24 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 27 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 64 -/* 33 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 50 -/* 41 */ MCD_OPC_CheckPredicate, 21, 75, 72, 0, // Skip to: 18553 -/* 46 */ MCD_OPC_Decode, 179, 10, 97, // Opcode: VHADDsv8i8 -/* 50 */ MCD_OPC_FilterValue, 1, 66, 72, 0, // Skip to: 18553 -/* 55 */ MCD_OPC_CheckPredicate, 21, 61, 72, 0, // Skip to: 18553 -/* 60 */ MCD_OPC_Decode, 174, 10, 98, // Opcode: VHADDsv16i8 -/* 64 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 86 -/* 70 */ MCD_OPC_CheckPredicate, 21, 46, 72, 0, // Skip to: 18553 -/* 75 */ MCD_OPC_CheckField, 6, 1, 0, 39, 72, 0, // Skip to: 18553 -/* 82 */ MCD_OPC_Decode, 242, 7, 99, // Opcode: VADDLsv8i16 -/* 86 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 123 -/* 92 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 95 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 109 -/* 100 */ MCD_OPC_CheckPredicate, 21, 16, 72, 0, // Skip to: 18553 -/* 105 */ MCD_OPC_Decode, 185, 10, 97, // Opcode: VHADDuv8i8 -/* 109 */ MCD_OPC_FilterValue, 1, 7, 72, 0, // Skip to: 18553 -/* 114 */ MCD_OPC_CheckPredicate, 21, 2, 72, 0, // Skip to: 18553 -/* 119 */ MCD_OPC_Decode, 180, 10, 98, // Opcode: VHADDuv16i8 -/* 123 */ MCD_OPC_FilterValue, 231, 3, 248, 71, 0, // Skip to: 18553 -/* 129 */ MCD_OPC_CheckPredicate, 21, 243, 71, 0, // Skip to: 18553 -/* 134 */ MCD_OPC_CheckField, 6, 1, 0, 236, 71, 0, // Skip to: 18553 -/* 141 */ MCD_OPC_Decode, 245, 7, 99, // Opcode: VADDLuv8i16 -/* 145 */ MCD_OPC_FilterValue, 1, 121, 0, 0, // Skip to: 271 -/* 150 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 153 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 190 -/* 159 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 162 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 176 -/* 167 */ MCD_OPC_CheckPredicate, 21, 205, 71, 0, // Skip to: 18553 -/* 172 */ MCD_OPC_Decode, 240, 16, 97, // Opcode: VRHADDsv8i8 -/* 176 */ MCD_OPC_FilterValue, 1, 196, 71, 0, // Skip to: 18553 -/* 181 */ MCD_OPC_CheckPredicate, 21, 191, 71, 0, // Skip to: 18553 -/* 186 */ MCD_OPC_Decode, 235, 16, 98, // Opcode: VRHADDsv16i8 -/* 190 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 212 -/* 196 */ MCD_OPC_CheckPredicate, 21, 176, 71, 0, // Skip to: 18553 -/* 201 */ MCD_OPC_CheckField, 6, 1, 0, 169, 71, 0, // Skip to: 18553 -/* 208 */ MCD_OPC_Decode, 249, 7, 100, // Opcode: VADDWsv8i16 -/* 212 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 249 -/* 218 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 221 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 235 -/* 226 */ MCD_OPC_CheckPredicate, 21, 146, 71, 0, // Skip to: 18553 -/* 231 */ MCD_OPC_Decode, 246, 16, 97, // Opcode: VRHADDuv8i8 -/* 235 */ MCD_OPC_FilterValue, 1, 137, 71, 0, // Skip to: 18553 -/* 240 */ MCD_OPC_CheckPredicate, 21, 132, 71, 0, // Skip to: 18553 -/* 245 */ MCD_OPC_Decode, 241, 16, 98, // Opcode: VRHADDuv16i8 -/* 249 */ MCD_OPC_FilterValue, 231, 3, 122, 71, 0, // Skip to: 18553 -/* 255 */ MCD_OPC_CheckPredicate, 21, 117, 71, 0, // Skip to: 18553 -/* 260 */ MCD_OPC_CheckField, 6, 1, 0, 110, 71, 0, // Skip to: 18553 -/* 267 */ MCD_OPC_Decode, 252, 7, 100, // Opcode: VADDWuv8i16 -/* 271 */ MCD_OPC_FilterValue, 2, 121, 0, 0, // Skip to: 397 -/* 276 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 279 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 316 -/* 285 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 288 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 302 -/* 293 */ MCD_OPC_CheckPredicate, 21, 79, 71, 0, // Skip to: 18553 -/* 298 */ MCD_OPC_Decode, 191, 10, 97, // Opcode: VHSUBsv8i8 -/* 302 */ MCD_OPC_FilterValue, 1, 70, 71, 0, // Skip to: 18553 -/* 307 */ MCD_OPC_CheckPredicate, 21, 65, 71, 0, // Skip to: 18553 -/* 312 */ MCD_OPC_Decode, 186, 10, 98, // Opcode: VHSUBsv16i8 -/* 316 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 338 -/* 322 */ MCD_OPC_CheckPredicate, 21, 50, 71, 0, // Skip to: 18553 -/* 327 */ MCD_OPC_CheckField, 6, 1, 0, 43, 71, 0, // Skip to: 18553 -/* 334 */ MCD_OPC_Decode, 214, 20, 99, // Opcode: VSUBLsv8i16 -/* 338 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 375 -/* 344 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 347 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 361 -/* 352 */ MCD_OPC_CheckPredicate, 21, 20, 71, 0, // Skip to: 18553 -/* 357 */ MCD_OPC_Decode, 197, 10, 97, // Opcode: VHSUBuv8i8 -/* 361 */ MCD_OPC_FilterValue, 1, 11, 71, 0, // Skip to: 18553 -/* 366 */ MCD_OPC_CheckPredicate, 21, 6, 71, 0, // Skip to: 18553 -/* 371 */ MCD_OPC_Decode, 192, 10, 98, // Opcode: VHSUBuv16i8 -/* 375 */ MCD_OPC_FilterValue, 231, 3, 252, 70, 0, // Skip to: 18553 -/* 381 */ MCD_OPC_CheckPredicate, 21, 247, 70, 0, // Skip to: 18553 -/* 386 */ MCD_OPC_CheckField, 6, 1, 0, 240, 70, 0, // Skip to: 18553 -/* 393 */ MCD_OPC_Decode, 217, 20, 99, // Opcode: VSUBLuv8i16 -/* 397 */ MCD_OPC_FilterValue, 3, 121, 0, 0, // Skip to: 523 -/* 402 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 405 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 442 -/* 411 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 414 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 428 -/* 419 */ MCD_OPC_CheckPredicate, 21, 209, 70, 0, // Skip to: 18553 -/* 424 */ MCD_OPC_Decode, 210, 8, 97, // Opcode: VCGTsv8i8 -/* 428 */ MCD_OPC_FilterValue, 1, 200, 70, 0, // Skip to: 18553 -/* 433 */ MCD_OPC_CheckPredicate, 21, 195, 70, 0, // Skip to: 18553 -/* 438 */ MCD_OPC_Decode, 205, 8, 98, // Opcode: VCGTsv16i8 -/* 442 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 464 -/* 448 */ MCD_OPC_CheckPredicate, 21, 180, 70, 0, // Skip to: 18553 -/* 453 */ MCD_OPC_CheckField, 6, 1, 0, 173, 70, 0, // Skip to: 18553 -/* 460 */ MCD_OPC_Decode, 221, 20, 100, // Opcode: VSUBWsv8i16 -/* 464 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 501 -/* 470 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 473 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 487 -/* 478 */ MCD_OPC_CheckPredicate, 21, 150, 70, 0, // Skip to: 18553 -/* 483 */ MCD_OPC_Decode, 216, 8, 97, // Opcode: VCGTuv8i8 -/* 487 */ MCD_OPC_FilterValue, 1, 141, 70, 0, // Skip to: 18553 -/* 492 */ MCD_OPC_CheckPredicate, 21, 136, 70, 0, // Skip to: 18553 -/* 497 */ MCD_OPC_Decode, 211, 8, 98, // Opcode: VCGTuv16i8 -/* 501 */ MCD_OPC_FilterValue, 231, 3, 126, 70, 0, // Skip to: 18553 -/* 507 */ MCD_OPC_CheckPredicate, 21, 121, 70, 0, // Skip to: 18553 -/* 512 */ MCD_OPC_CheckField, 6, 1, 0, 114, 70, 0, // Skip to: 18553 -/* 519 */ MCD_OPC_Decode, 224, 20, 100, // Opcode: VSUBWuv8i16 -/* 523 */ MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 649 -/* 528 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 531 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 568 -/* 537 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 540 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 554 -/* 545 */ MCD_OPC_CheckPredicate, 21, 83, 70, 0, // Skip to: 18553 -/* 550 */ MCD_OPC_Decode, 143, 18, 101, // Opcode: VSHLsv8i8 -/* 554 */ MCD_OPC_FilterValue, 1, 74, 70, 0, // Skip to: 18553 -/* 559 */ MCD_OPC_CheckPredicate, 21, 69, 70, 0, // Skip to: 18553 -/* 564 */ MCD_OPC_Decode, 136, 18, 102, // Opcode: VSHLsv16i8 -/* 568 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 590 -/* 574 */ MCD_OPC_CheckPredicate, 21, 54, 70, 0, // Skip to: 18553 -/* 579 */ MCD_OPC_CheckField, 6, 1, 0, 47, 70, 0, // Skip to: 18553 -/* 586 */ MCD_OPC_Decode, 239, 7, 103, // Opcode: VADDHNv8i8 -/* 590 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 627 -/* 596 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 599 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 613 -/* 604 */ MCD_OPC_CheckPredicate, 21, 24, 70, 0, // Skip to: 18553 -/* 609 */ MCD_OPC_Decode, 151, 18, 101, // Opcode: VSHLuv8i8 -/* 613 */ MCD_OPC_FilterValue, 1, 15, 70, 0, // Skip to: 18553 -/* 618 */ MCD_OPC_CheckPredicate, 21, 10, 70, 0, // Skip to: 18553 -/* 623 */ MCD_OPC_Decode, 144, 18, 102, // Opcode: VSHLuv16i8 -/* 627 */ MCD_OPC_FilterValue, 231, 3, 0, 70, 0, // Skip to: 18553 -/* 633 */ MCD_OPC_CheckPredicate, 21, 251, 69, 0, // Skip to: 18553 -/* 638 */ MCD_OPC_CheckField, 6, 1, 0, 244, 69, 0, // Skip to: 18553 -/* 645 */ MCD_OPC_Decode, 212, 16, 103, // Opcode: VRADDHNv8i8 -/* 649 */ MCD_OPC_FilterValue, 5, 121, 0, 0, // Skip to: 775 -/* 654 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 657 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 694 -/* 663 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 666 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 680 -/* 671 */ MCD_OPC_CheckPredicate, 21, 213, 69, 0, // Skip to: 18553 -/* 676 */ MCD_OPC_Decode, 171, 17, 101, // Opcode: VRSHLsv8i8 -/* 680 */ MCD_OPC_FilterValue, 1, 204, 69, 0, // Skip to: 18553 -/* 685 */ MCD_OPC_CheckPredicate, 21, 199, 69, 0, // Skip to: 18553 -/* 690 */ MCD_OPC_Decode, 164, 17, 102, // Opcode: VRSHLsv16i8 -/* 694 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 716 -/* 700 */ MCD_OPC_CheckPredicate, 21, 184, 69, 0, // Skip to: 18553 -/* 705 */ MCD_OPC_CheckField, 6, 1, 0, 177, 69, 0, // Skip to: 18553 -/* 712 */ MCD_OPC_Decode, 176, 7, 104, // Opcode: VABALsv8i16 -/* 716 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 753 -/* 722 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 725 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 739 -/* 730 */ MCD_OPC_CheckPredicate, 21, 154, 69, 0, // Skip to: 18553 -/* 735 */ MCD_OPC_Decode, 179, 17, 101, // Opcode: VRSHLuv8i8 -/* 739 */ MCD_OPC_FilterValue, 1, 145, 69, 0, // Skip to: 18553 -/* 744 */ MCD_OPC_CheckPredicate, 21, 140, 69, 0, // Skip to: 18553 -/* 749 */ MCD_OPC_Decode, 172, 17, 102, // Opcode: VRSHLuv16i8 -/* 753 */ MCD_OPC_FilterValue, 231, 3, 130, 69, 0, // Skip to: 18553 -/* 759 */ MCD_OPC_CheckPredicate, 21, 125, 69, 0, // Skip to: 18553 -/* 764 */ MCD_OPC_CheckField, 6, 1, 0, 118, 69, 0, // Skip to: 18553 -/* 771 */ MCD_OPC_Decode, 179, 7, 104, // Opcode: VABALuv8i16 -/* 775 */ MCD_OPC_FilterValue, 6, 121, 0, 0, // Skip to: 901 -/* 780 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 783 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 820 -/* 789 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 792 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 806 -/* 797 */ MCD_OPC_CheckPredicate, 21, 87, 69, 0, // Skip to: 18553 -/* 802 */ MCD_OPC_Decode, 172, 13, 97, // Opcode: VMAXsv8i8 -/* 806 */ MCD_OPC_FilterValue, 1, 78, 69, 0, // Skip to: 18553 -/* 811 */ MCD_OPC_CheckPredicate, 21, 73, 69, 0, // Skip to: 18553 -/* 816 */ MCD_OPC_Decode, 167, 13, 98, // Opcode: VMAXsv16i8 -/* 820 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 842 -/* 826 */ MCD_OPC_CheckPredicate, 21, 58, 69, 0, // Skip to: 18553 -/* 831 */ MCD_OPC_CheckField, 6, 1, 0, 51, 69, 0, // Skip to: 18553 -/* 838 */ MCD_OPC_Decode, 211, 20, 103, // Opcode: VSUBHNv8i8 -/* 842 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 879 -/* 848 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 851 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 865 -/* 856 */ MCD_OPC_CheckPredicate, 21, 28, 69, 0, // Skip to: 18553 -/* 861 */ MCD_OPC_Decode, 178, 13, 97, // Opcode: VMAXuv8i8 -/* 865 */ MCD_OPC_FilterValue, 1, 19, 69, 0, // Skip to: 18553 -/* 870 */ MCD_OPC_CheckPredicate, 21, 14, 69, 0, // Skip to: 18553 -/* 875 */ MCD_OPC_Decode, 173, 13, 98, // Opcode: VMAXuv16i8 -/* 879 */ MCD_OPC_FilterValue, 231, 3, 4, 69, 0, // Skip to: 18553 -/* 885 */ MCD_OPC_CheckPredicate, 21, 255, 68, 0, // Skip to: 18553 -/* 890 */ MCD_OPC_CheckField, 6, 1, 0, 248, 68, 0, // Skip to: 18553 -/* 897 */ MCD_OPC_Decode, 227, 17, 103, // Opcode: VRSUBHNv8i8 -/* 901 */ MCD_OPC_FilterValue, 7, 121, 0, 0, // Skip to: 1027 -/* 906 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 909 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 946 -/* 915 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 918 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 932 -/* 923 */ MCD_OPC_CheckPredicate, 21, 217, 68, 0, // Skip to: 18553 -/* 928 */ MCD_OPC_Decode, 207, 7, 97, // Opcode: VABDsv8i8 -/* 932 */ MCD_OPC_FilterValue, 1, 208, 68, 0, // Skip to: 18553 -/* 937 */ MCD_OPC_CheckPredicate, 21, 203, 68, 0, // Skip to: 18553 -/* 942 */ MCD_OPC_Decode, 202, 7, 98, // Opcode: VABDsv16i8 -/* 946 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 968 -/* 952 */ MCD_OPC_CheckPredicate, 21, 188, 68, 0, // Skip to: 18553 -/* 957 */ MCD_OPC_CheckField, 6, 1, 0, 181, 68, 0, // Skip to: 18553 -/* 964 */ MCD_OPC_Decode, 194, 7, 99, // Opcode: VABDLsv8i16 -/* 968 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1005 -/* 974 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 977 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 991 -/* 982 */ MCD_OPC_CheckPredicate, 21, 158, 68, 0, // Skip to: 18553 -/* 987 */ MCD_OPC_Decode, 213, 7, 97, // Opcode: VABDuv8i8 -/* 991 */ MCD_OPC_FilterValue, 1, 149, 68, 0, // Skip to: 18553 -/* 996 */ MCD_OPC_CheckPredicate, 21, 144, 68, 0, // Skip to: 18553 -/* 1001 */ MCD_OPC_Decode, 208, 7, 98, // Opcode: VABDuv16i8 -/* 1005 */ MCD_OPC_FilterValue, 231, 3, 134, 68, 0, // Skip to: 18553 -/* 1011 */ MCD_OPC_CheckPredicate, 21, 129, 68, 0, // Skip to: 18553 -/* 1016 */ MCD_OPC_CheckField, 6, 1, 0, 122, 68, 0, // Skip to: 18553 -/* 1023 */ MCD_OPC_Decode, 197, 7, 99, // Opcode: VABDLuv8i16 -/* 1027 */ MCD_OPC_FilterValue, 8, 121, 0, 0, // Skip to: 1153 -/* 1032 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1035 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1072 -/* 1041 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1044 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1058 -/* 1049 */ MCD_OPC_CheckPredicate, 21, 91, 68, 0, // Skip to: 18553 -/* 1054 */ MCD_OPC_Decode, 136, 8, 97, // Opcode: VADDv8i8 -/* 1058 */ MCD_OPC_FilterValue, 1, 82, 68, 0, // Skip to: 18553 -/* 1063 */ MCD_OPC_CheckPredicate, 21, 77, 68, 0, // Skip to: 18553 -/* 1068 */ MCD_OPC_Decode, 129, 8, 98, // Opcode: VADDv16i8 -/* 1072 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1094 -/* 1078 */ MCD_OPC_CheckPredicate, 21, 62, 68, 0, // Skip to: 18553 -/* 1083 */ MCD_OPC_CheckField, 6, 1, 0, 55, 68, 0, // Skip to: 18553 -/* 1090 */ MCD_OPC_Decode, 210, 13, 104, // Opcode: VMLALsv8i16 -/* 1094 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1131 -/* 1100 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1103 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1117 -/* 1108 */ MCD_OPC_CheckPredicate, 21, 32, 68, 0, // Skip to: 18553 -/* 1113 */ MCD_OPC_Decode, 236, 20, 97, // Opcode: VSUBv8i8 -/* 1117 */ MCD_OPC_FilterValue, 1, 23, 68, 0, // Skip to: 18553 -/* 1122 */ MCD_OPC_CheckPredicate, 21, 18, 68, 0, // Skip to: 18553 -/* 1127 */ MCD_OPC_Decode, 229, 20, 98, // Opcode: VSUBv16i8 -/* 1131 */ MCD_OPC_FilterValue, 231, 3, 8, 68, 0, // Skip to: 18553 -/* 1137 */ MCD_OPC_CheckPredicate, 21, 3, 68, 0, // Skip to: 18553 -/* 1142 */ MCD_OPC_CheckField, 6, 1, 0, 252, 67, 0, // Skip to: 18553 -/* 1149 */ MCD_OPC_Decode, 213, 13, 104, // Opcode: VMLALuv8i16 -/* 1153 */ MCD_OPC_FilterValue, 9, 79, 0, 0, // Skip to: 1237 -/* 1158 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1161 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1199 -/* 1166 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1169 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1184 -/* 1175 */ MCD_OPC_CheckPredicate, 21, 221, 67, 0, // Skip to: 18553 -/* 1180 */ MCD_OPC_Decode, 232, 13, 105, // Opcode: VMLAv8i8 -/* 1184 */ MCD_OPC_FilterValue, 230, 3, 211, 67, 0, // Skip to: 18553 -/* 1190 */ MCD_OPC_CheckPredicate, 21, 206, 67, 0, // Skip to: 18553 -/* 1195 */ MCD_OPC_Decode, 135, 14, 105, // Opcode: VMLSv8i8 -/* 1199 */ MCD_OPC_FilterValue, 1, 197, 67, 0, // Skip to: 18553 -/* 1204 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1207 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1222 -/* 1213 */ MCD_OPC_CheckPredicate, 21, 183, 67, 0, // Skip to: 18553 -/* 1218 */ MCD_OPC_Decode, 227, 13, 106, // Opcode: VMLAv16i8 -/* 1222 */ MCD_OPC_FilterValue, 230, 3, 173, 67, 0, // Skip to: 18553 -/* 1228 */ MCD_OPC_CheckPredicate, 21, 168, 67, 0, // Skip to: 18553 -/* 1233 */ MCD_OPC_Decode, 130, 14, 106, // Opcode: VMLSv16i8 -/* 1237 */ MCD_OPC_FilterValue, 10, 91, 0, 0, // Skip to: 1333 -/* 1242 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1245 */ MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 1267 -/* 1251 */ MCD_OPC_CheckPredicate, 21, 145, 67, 0, // Skip to: 18553 -/* 1256 */ MCD_OPC_CheckField, 6, 1, 0, 138, 67, 0, // Skip to: 18553 -/* 1263 */ MCD_OPC_Decode, 155, 15, 97, // Opcode: VPMAXs8 -/* 1267 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1289 -/* 1273 */ MCD_OPC_CheckPredicate, 21, 123, 67, 0, // Skip to: 18553 -/* 1278 */ MCD_OPC_CheckField, 6, 1, 0, 116, 67, 0, // Skip to: 18553 -/* 1285 */ MCD_OPC_Decode, 241, 13, 104, // Opcode: VMLSLsv8i16 -/* 1289 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 1311 -/* 1295 */ MCD_OPC_CheckPredicate, 21, 101, 67, 0, // Skip to: 18553 -/* 1300 */ MCD_OPC_CheckField, 6, 1, 0, 94, 67, 0, // Skip to: 18553 -/* 1307 */ MCD_OPC_Decode, 158, 15, 97, // Opcode: VPMAXu8 -/* 1311 */ MCD_OPC_FilterValue, 231, 3, 84, 67, 0, // Skip to: 18553 -/* 1317 */ MCD_OPC_CheckPredicate, 21, 79, 67, 0, // Skip to: 18553 -/* 1322 */ MCD_OPC_CheckField, 6, 1, 0, 72, 67, 0, // Skip to: 18553 -/* 1329 */ MCD_OPC_Decode, 244, 13, 104, // Opcode: VMLSLuv8i16 -/* 1333 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 1385 -/* 1338 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1341 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1363 -/* 1347 */ MCD_OPC_CheckPredicate, 21, 49, 67, 0, // Skip to: 18553 -/* 1352 */ MCD_OPC_CheckField, 6, 1, 0, 42, 67, 0, // Skip to: 18553 -/* 1359 */ MCD_OPC_Decode, 189, 14, 99, // Opcode: VMULLsv8i16 -/* 1363 */ MCD_OPC_FilterValue, 231, 3, 32, 67, 0, // Skip to: 18553 -/* 1369 */ MCD_OPC_CheckPredicate, 21, 27, 67, 0, // Skip to: 18553 -/* 1374 */ MCD_OPC_CheckField, 6, 1, 0, 20, 67, 0, // Skip to: 18553 -/* 1381 */ MCD_OPC_Decode, 192, 14, 99, // Opcode: VMULLuv8i16 -/* 1385 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1453 -/* 1390 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1393 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1431 -/* 1398 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1401 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1416 -/* 1407 */ MCD_OPC_CheckPredicate, 21, 245, 66, 0, // Skip to: 18553 -/* 1412 */ MCD_OPC_Decode, 253, 7, 97, // Opcode: VADDfd -/* 1416 */ MCD_OPC_FilterValue, 230, 3, 235, 66, 0, // Skip to: 18553 -/* 1422 */ MCD_OPC_CheckPredicate, 21, 230, 66, 0, // Skip to: 18553 -/* 1427 */ MCD_OPC_Decode, 146, 15, 97, // Opcode: VPADDf -/* 1431 */ MCD_OPC_FilterValue, 1, 221, 66, 0, // Skip to: 18553 -/* 1436 */ MCD_OPC_CheckPredicate, 21, 216, 66, 0, // Skip to: 18553 -/* 1441 */ MCD_OPC_CheckField, 23, 9, 228, 3, 208, 66, 0, // Skip to: 18553 -/* 1449 */ MCD_OPC_Decode, 254, 7, 98, // Opcode: VADDfq -/* 1453 */ MCD_OPC_FilterValue, 14, 99, 0, 0, // Skip to: 1557 -/* 1458 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1461 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1498 -/* 1467 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1470 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1484 -/* 1475 */ MCD_OPC_CheckPredicate, 21, 177, 66, 0, // Skip to: 18553 -/* 1480 */ MCD_OPC_Decode, 155, 8, 97, // Opcode: VCEQfd -/* 1484 */ MCD_OPC_FilterValue, 1, 168, 66, 0, // Skip to: 18553 -/* 1489 */ MCD_OPC_CheckPredicate, 21, 163, 66, 0, // Skip to: 18553 -/* 1494 */ MCD_OPC_Decode, 156, 8, 98, // Opcode: VCEQfq -/* 1498 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1520 -/* 1504 */ MCD_OPC_CheckPredicate, 21, 148, 66, 0, // Skip to: 18553 -/* 1509 */ MCD_OPC_CheckField, 6, 1, 0, 141, 66, 0, // Skip to: 18553 -/* 1516 */ MCD_OPC_Decode, 182, 14, 99, // Opcode: VMULLp8 -/* 1520 */ MCD_OPC_FilterValue, 230, 3, 131, 66, 0, // Skip to: 18553 -/* 1526 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1529 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1543 -/* 1534 */ MCD_OPC_CheckPredicate, 21, 118, 66, 0, // Skip to: 18553 -/* 1539 */ MCD_OPC_Decode, 175, 8, 97, // Opcode: VCGEfd -/* 1543 */ MCD_OPC_FilterValue, 1, 109, 66, 0, // Skip to: 18553 -/* 1548 */ MCD_OPC_CheckPredicate, 21, 104, 66, 0, // Skip to: 18553 -/* 1553 */ MCD_OPC_Decode, 176, 8, 98, // Opcode: VCGEfq -/* 1557 */ MCD_OPC_FilterValue, 15, 95, 66, 0, // Skip to: 18553 -/* 1562 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1565 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1603 -/* 1570 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1573 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1588 -/* 1579 */ MCD_OPC_CheckPredicate, 21, 73, 66, 0, // Skip to: 18553 -/* 1584 */ MCD_OPC_Decode, 163, 13, 97, // Opcode: VMAXfd -/* 1588 */ MCD_OPC_FilterValue, 230, 3, 63, 66, 0, // Skip to: 18553 -/* 1594 */ MCD_OPC_CheckPredicate, 21, 58, 66, 0, // Skip to: 18553 -/* 1599 */ MCD_OPC_Decode, 151, 15, 97, // Opcode: VPMAXf -/* 1603 */ MCD_OPC_FilterValue, 1, 49, 66, 0, // Skip to: 18553 -/* 1608 */ MCD_OPC_CheckPredicate, 21, 44, 66, 0, // Skip to: 18553 -/* 1613 */ MCD_OPC_CheckField, 23, 9, 228, 3, 36, 66, 0, // Skip to: 18553 -/* 1621 */ MCD_OPC_Decode, 164, 13, 98, // Opcode: VMAXfq -/* 1625 */ MCD_OPC_FilterValue, 1, 162, 8, 0, // Skip to: 3840 -/* 1630 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1633 */ MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 1789 -/* 1638 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1641 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1678 -/* 1647 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1650 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1664 -/* 1655 */ MCD_OPC_CheckPredicate, 21, 253, 65, 0, // Skip to: 18553 -/* 1660 */ MCD_OPC_Decode, 176, 10, 97, // Opcode: VHADDsv4i16 -/* 1664 */ MCD_OPC_FilterValue, 1, 244, 65, 0, // Skip to: 18553 -/* 1669 */ MCD_OPC_CheckPredicate, 21, 239, 65, 0, // Skip to: 18553 -/* 1674 */ MCD_OPC_Decode, 178, 10, 98, // Opcode: VHADDsv8i16 -/* 1678 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 1715 -/* 1684 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1687 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1701 -/* 1692 */ MCD_OPC_CheckPredicate, 21, 216, 65, 0, // Skip to: 18553 -/* 1697 */ MCD_OPC_Decode, 241, 7, 99, // Opcode: VADDLsv4i32 -/* 1701 */ MCD_OPC_FilterValue, 1, 207, 65, 0, // Skip to: 18553 -/* 1706 */ MCD_OPC_CheckPredicate, 21, 202, 65, 0, // Skip to: 18553 -/* 1711 */ MCD_OPC_Decode, 224, 13, 107, // Opcode: VMLAslv4i16 -/* 1715 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1752 -/* 1721 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1724 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1738 -/* 1729 */ MCD_OPC_CheckPredicate, 21, 179, 65, 0, // Skip to: 18553 -/* 1734 */ MCD_OPC_Decode, 182, 10, 97, // Opcode: VHADDuv4i16 -/* 1738 */ MCD_OPC_FilterValue, 1, 170, 65, 0, // Skip to: 18553 -/* 1743 */ MCD_OPC_CheckPredicate, 21, 165, 65, 0, // Skip to: 18553 -/* 1748 */ MCD_OPC_Decode, 184, 10, 98, // Opcode: VHADDuv8i16 -/* 1752 */ MCD_OPC_FilterValue, 231, 3, 155, 65, 0, // Skip to: 18553 -/* 1758 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1761 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1775 -/* 1766 */ MCD_OPC_CheckPredicate, 21, 142, 65, 0, // Skip to: 18553 -/* 1771 */ MCD_OPC_Decode, 244, 7, 99, // Opcode: VADDLuv4i32 -/* 1775 */ MCD_OPC_FilterValue, 1, 133, 65, 0, // Skip to: 18553 -/* 1780 */ MCD_OPC_CheckPredicate, 21, 128, 65, 0, // Skip to: 18553 -/* 1785 */ MCD_OPC_Decode, 226, 13, 108, // Opcode: VMLAslv8i16 -/* 1789 */ MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 1945 -/* 1794 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1797 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1834 -/* 1803 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1806 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1820 -/* 1811 */ MCD_OPC_CheckPredicate, 21, 97, 65, 0, // Skip to: 18553 -/* 1816 */ MCD_OPC_Decode, 237, 16, 97, // Opcode: VRHADDsv4i16 -/* 1820 */ MCD_OPC_FilterValue, 1, 88, 65, 0, // Skip to: 18553 -/* 1825 */ MCD_OPC_CheckPredicate, 21, 83, 65, 0, // Skip to: 18553 -/* 1830 */ MCD_OPC_Decode, 239, 16, 98, // Opcode: VRHADDsv8i16 -/* 1834 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 1871 -/* 1840 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1843 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1857 -/* 1848 */ MCD_OPC_CheckPredicate, 21, 60, 65, 0, // Skip to: 18553 -/* 1853 */ MCD_OPC_Decode, 248, 7, 100, // Opcode: VADDWsv4i32 -/* 1857 */ MCD_OPC_FilterValue, 1, 51, 65, 0, // Skip to: 18553 -/* 1862 */ MCD_OPC_CheckPredicate, 22, 46, 65, 0, // Skip to: 18553 -/* 1867 */ MCD_OPC_Decode, 221, 13, 107, // Opcode: VMLAslhd -/* 1871 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1908 -/* 1877 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1880 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1894 -/* 1885 */ MCD_OPC_CheckPredicate, 21, 23, 65, 0, // Skip to: 18553 -/* 1890 */ MCD_OPC_Decode, 243, 16, 97, // Opcode: VRHADDuv4i16 -/* 1894 */ MCD_OPC_FilterValue, 1, 14, 65, 0, // Skip to: 18553 -/* 1899 */ MCD_OPC_CheckPredicate, 21, 9, 65, 0, // Skip to: 18553 -/* 1904 */ MCD_OPC_Decode, 245, 16, 98, // Opcode: VRHADDuv8i16 -/* 1908 */ MCD_OPC_FilterValue, 231, 3, 255, 64, 0, // Skip to: 18553 -/* 1914 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1917 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1931 -/* 1922 */ MCD_OPC_CheckPredicate, 21, 242, 64, 0, // Skip to: 18553 -/* 1927 */ MCD_OPC_Decode, 251, 7, 100, // Opcode: VADDWuv4i32 -/* 1931 */ MCD_OPC_FilterValue, 1, 233, 64, 0, // Skip to: 18553 -/* 1936 */ MCD_OPC_CheckPredicate, 22, 228, 64, 0, // Skip to: 18553 -/* 1941 */ MCD_OPC_Decode, 222, 13, 108, // Opcode: VMLAslhq -/* 1945 */ MCD_OPC_FilterValue, 2, 151, 0, 0, // Skip to: 2101 -/* 1950 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1953 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1990 -/* 1959 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1962 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1976 -/* 1967 */ MCD_OPC_CheckPredicate, 21, 197, 64, 0, // Skip to: 18553 -/* 1972 */ MCD_OPC_Decode, 188, 10, 97, // Opcode: VHSUBsv4i16 -/* 1976 */ MCD_OPC_FilterValue, 1, 188, 64, 0, // Skip to: 18553 -/* 1981 */ MCD_OPC_CheckPredicate, 21, 183, 64, 0, // Skip to: 18553 -/* 1986 */ MCD_OPC_Decode, 190, 10, 98, // Opcode: VHSUBsv8i16 -/* 1990 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2027 -/* 1996 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1999 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2013 -/* 2004 */ MCD_OPC_CheckPredicate, 21, 160, 64, 0, // Skip to: 18553 -/* 2009 */ MCD_OPC_Decode, 213, 20, 99, // Opcode: VSUBLsv4i32 -/* 2013 */ MCD_OPC_FilterValue, 1, 151, 64, 0, // Skip to: 18553 -/* 2018 */ MCD_OPC_CheckPredicate, 21, 146, 64, 0, // Skip to: 18553 -/* 2023 */ MCD_OPC_Decode, 205, 13, 109, // Opcode: VMLALslsv4i16 -/* 2027 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2064 -/* 2033 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2036 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2050 -/* 2041 */ MCD_OPC_CheckPredicate, 21, 123, 64, 0, // Skip to: 18553 -/* 2046 */ MCD_OPC_Decode, 194, 10, 97, // Opcode: VHSUBuv4i16 -/* 2050 */ MCD_OPC_FilterValue, 1, 114, 64, 0, // Skip to: 18553 -/* 2055 */ MCD_OPC_CheckPredicate, 21, 109, 64, 0, // Skip to: 18553 -/* 2060 */ MCD_OPC_Decode, 196, 10, 98, // Opcode: VHSUBuv8i16 -/* 2064 */ MCD_OPC_FilterValue, 231, 3, 99, 64, 0, // Skip to: 18553 -/* 2070 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2073 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2087 -/* 2078 */ MCD_OPC_CheckPredicate, 21, 86, 64, 0, // Skip to: 18553 -/* 2083 */ MCD_OPC_Decode, 216, 20, 99, // Opcode: VSUBLuv4i32 -/* 2087 */ MCD_OPC_FilterValue, 1, 77, 64, 0, // Skip to: 18553 -/* 2092 */ MCD_OPC_CheckPredicate, 21, 72, 64, 0, // Skip to: 18553 -/* 2097 */ MCD_OPC_Decode, 207, 13, 109, // Opcode: VMLALsluv4i16 -/* 2101 */ MCD_OPC_FilterValue, 3, 136, 0, 0, // Skip to: 2242 -/* 2106 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2109 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2146 -/* 2115 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2118 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2132 -/* 2123 */ MCD_OPC_CheckPredicate, 21, 41, 64, 0, // Skip to: 18553 -/* 2128 */ MCD_OPC_Decode, 207, 8, 97, // Opcode: VCGTsv4i16 -/* 2132 */ MCD_OPC_FilterValue, 1, 32, 64, 0, // Skip to: 18553 -/* 2137 */ MCD_OPC_CheckPredicate, 21, 27, 64, 0, // Skip to: 18553 -/* 2142 */ MCD_OPC_Decode, 209, 8, 98, // Opcode: VCGTsv8i16 -/* 2146 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2183 -/* 2152 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2155 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2169 -/* 2160 */ MCD_OPC_CheckPredicate, 21, 4, 64, 0, // Skip to: 18553 -/* 2165 */ MCD_OPC_Decode, 220, 20, 100, // Opcode: VSUBWsv4i32 -/* 2169 */ MCD_OPC_FilterValue, 1, 251, 63, 0, // Skip to: 18553 -/* 2174 */ MCD_OPC_CheckPredicate, 21, 246, 63, 0, // Skip to: 18553 -/* 2179 */ MCD_OPC_Decode, 190, 15, 109, // Opcode: VQDMLALslv4i16 -/* 2183 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2220 -/* 2189 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2192 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2206 -/* 2197 */ MCD_OPC_CheckPredicate, 21, 223, 63, 0, // Skip to: 18553 -/* 2202 */ MCD_OPC_Decode, 213, 8, 97, // Opcode: VCGTuv4i16 -/* 2206 */ MCD_OPC_FilterValue, 1, 214, 63, 0, // Skip to: 18553 -/* 2211 */ MCD_OPC_CheckPredicate, 21, 209, 63, 0, // Skip to: 18553 -/* 2216 */ MCD_OPC_Decode, 215, 8, 98, // Opcode: VCGTuv8i16 -/* 2220 */ MCD_OPC_FilterValue, 231, 3, 199, 63, 0, // Skip to: 18553 -/* 2226 */ MCD_OPC_CheckPredicate, 21, 194, 63, 0, // Skip to: 18553 -/* 2231 */ MCD_OPC_CheckField, 6, 1, 0, 187, 63, 0, // Skip to: 18553 -/* 2238 */ MCD_OPC_Decode, 223, 20, 100, // Opcode: VSUBWuv4i32 -/* 2242 */ MCD_OPC_FilterValue, 4, 151, 0, 0, // Skip to: 2398 -/* 2247 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2250 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2287 -/* 2256 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2259 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2273 -/* 2264 */ MCD_OPC_CheckPredicate, 21, 156, 63, 0, // Skip to: 18553 -/* 2269 */ MCD_OPC_Decode, 140, 18, 101, // Opcode: VSHLsv4i16 -/* 2273 */ MCD_OPC_FilterValue, 1, 147, 63, 0, // Skip to: 18553 -/* 2278 */ MCD_OPC_CheckPredicate, 21, 142, 63, 0, // Skip to: 18553 -/* 2283 */ MCD_OPC_Decode, 142, 18, 102, // Opcode: VSHLsv8i16 -/* 2287 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2324 -/* 2293 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2296 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2310 -/* 2301 */ MCD_OPC_CheckPredicate, 21, 119, 63, 0, // Skip to: 18553 -/* 2306 */ MCD_OPC_Decode, 238, 7, 103, // Opcode: VADDHNv4i16 -/* 2310 */ MCD_OPC_FilterValue, 1, 110, 63, 0, // Skip to: 18553 -/* 2315 */ MCD_OPC_CheckPredicate, 21, 105, 63, 0, // Skip to: 18553 -/* 2320 */ MCD_OPC_Decode, 255, 13, 107, // Opcode: VMLSslv4i16 -/* 2324 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2361 -/* 2330 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2333 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2347 -/* 2338 */ MCD_OPC_CheckPredicate, 21, 82, 63, 0, // Skip to: 18553 -/* 2343 */ MCD_OPC_Decode, 148, 18, 101, // Opcode: VSHLuv4i16 -/* 2347 */ MCD_OPC_FilterValue, 1, 73, 63, 0, // Skip to: 18553 -/* 2352 */ MCD_OPC_CheckPredicate, 21, 68, 63, 0, // Skip to: 18553 -/* 2357 */ MCD_OPC_Decode, 150, 18, 102, // Opcode: VSHLuv8i16 -/* 2361 */ MCD_OPC_FilterValue, 231, 3, 58, 63, 0, // Skip to: 18553 -/* 2367 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2370 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2384 -/* 2375 */ MCD_OPC_CheckPredicate, 21, 45, 63, 0, // Skip to: 18553 -/* 2380 */ MCD_OPC_Decode, 211, 16, 103, // Opcode: VRADDHNv4i16 -/* 2384 */ MCD_OPC_FilterValue, 1, 36, 63, 0, // Skip to: 18553 -/* 2389 */ MCD_OPC_CheckPredicate, 21, 31, 63, 0, // Skip to: 18553 -/* 2394 */ MCD_OPC_Decode, 129, 14, 108, // Opcode: VMLSslv8i16 -/* 2398 */ MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 2554 -/* 2403 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2406 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2443 -/* 2412 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2415 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2429 -/* 2420 */ MCD_OPC_CheckPredicate, 21, 0, 63, 0, // Skip to: 18553 -/* 2425 */ MCD_OPC_Decode, 168, 17, 101, // Opcode: VRSHLsv4i16 -/* 2429 */ MCD_OPC_FilterValue, 1, 247, 62, 0, // Skip to: 18553 -/* 2434 */ MCD_OPC_CheckPredicate, 21, 242, 62, 0, // Skip to: 18553 -/* 2439 */ MCD_OPC_Decode, 170, 17, 102, // Opcode: VRSHLsv8i16 -/* 2443 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2480 -/* 2449 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2452 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2466 -/* 2457 */ MCD_OPC_CheckPredicate, 21, 219, 62, 0, // Skip to: 18553 -/* 2462 */ MCD_OPC_Decode, 175, 7, 104, // Opcode: VABALsv4i32 -/* 2466 */ MCD_OPC_FilterValue, 1, 210, 62, 0, // Skip to: 18553 -/* 2471 */ MCD_OPC_CheckPredicate, 22, 205, 62, 0, // Skip to: 18553 -/* 2476 */ MCD_OPC_Decode, 252, 13, 107, // Opcode: VMLSslhd -/* 2480 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2517 -/* 2486 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2489 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2503 -/* 2494 */ MCD_OPC_CheckPredicate, 21, 182, 62, 0, // Skip to: 18553 -/* 2499 */ MCD_OPC_Decode, 176, 17, 101, // Opcode: VRSHLuv4i16 -/* 2503 */ MCD_OPC_FilterValue, 1, 173, 62, 0, // Skip to: 18553 -/* 2508 */ MCD_OPC_CheckPredicate, 21, 168, 62, 0, // Skip to: 18553 -/* 2513 */ MCD_OPC_Decode, 178, 17, 102, // Opcode: VRSHLuv8i16 -/* 2517 */ MCD_OPC_FilterValue, 231, 3, 158, 62, 0, // Skip to: 18553 -/* 2523 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2526 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2540 -/* 2531 */ MCD_OPC_CheckPredicate, 21, 145, 62, 0, // Skip to: 18553 -/* 2536 */ MCD_OPC_Decode, 178, 7, 104, // Opcode: VABALuv4i32 -/* 2540 */ MCD_OPC_FilterValue, 1, 136, 62, 0, // Skip to: 18553 -/* 2545 */ MCD_OPC_CheckPredicate, 22, 131, 62, 0, // Skip to: 18553 -/* 2550 */ MCD_OPC_Decode, 253, 13, 108, // Opcode: VMLSslhq -/* 2554 */ MCD_OPC_FilterValue, 6, 151, 0, 0, // Skip to: 2710 -/* 2559 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2562 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2599 -/* 2568 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2571 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2585 -/* 2576 */ MCD_OPC_CheckPredicate, 21, 100, 62, 0, // Skip to: 18553 -/* 2581 */ MCD_OPC_Decode, 169, 13, 97, // Opcode: VMAXsv4i16 -/* 2585 */ MCD_OPC_FilterValue, 1, 91, 62, 0, // Skip to: 18553 -/* 2590 */ MCD_OPC_CheckPredicate, 21, 86, 62, 0, // Skip to: 18553 -/* 2595 */ MCD_OPC_Decode, 171, 13, 98, // Opcode: VMAXsv8i16 -/* 2599 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2636 -/* 2605 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2608 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2622 -/* 2613 */ MCD_OPC_CheckPredicate, 21, 63, 62, 0, // Skip to: 18553 -/* 2618 */ MCD_OPC_Decode, 210, 20, 103, // Opcode: VSUBHNv4i16 -/* 2622 */ MCD_OPC_FilterValue, 1, 54, 62, 0, // Skip to: 18553 -/* 2627 */ MCD_OPC_CheckPredicate, 21, 49, 62, 0, // Skip to: 18553 -/* 2632 */ MCD_OPC_Decode, 236, 13, 109, // Opcode: VMLSLslsv4i16 -/* 2636 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2673 -/* 2642 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2645 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2659 -/* 2650 */ MCD_OPC_CheckPredicate, 21, 26, 62, 0, // Skip to: 18553 -/* 2655 */ MCD_OPC_Decode, 175, 13, 97, // Opcode: VMAXuv4i16 -/* 2659 */ MCD_OPC_FilterValue, 1, 17, 62, 0, // Skip to: 18553 -/* 2664 */ MCD_OPC_CheckPredicate, 21, 12, 62, 0, // Skip to: 18553 -/* 2669 */ MCD_OPC_Decode, 177, 13, 98, // Opcode: VMAXuv8i16 -/* 2673 */ MCD_OPC_FilterValue, 231, 3, 2, 62, 0, // Skip to: 18553 -/* 2679 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2682 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2696 -/* 2687 */ MCD_OPC_CheckPredicate, 21, 245, 61, 0, // Skip to: 18553 -/* 2692 */ MCD_OPC_Decode, 226, 17, 103, // Opcode: VRSUBHNv4i16 -/* 2696 */ MCD_OPC_FilterValue, 1, 236, 61, 0, // Skip to: 18553 -/* 2701 */ MCD_OPC_CheckPredicate, 21, 231, 61, 0, // Skip to: 18553 -/* 2706 */ MCD_OPC_Decode, 238, 13, 109, // Opcode: VMLSLsluv4i16 -/* 2710 */ MCD_OPC_FilterValue, 7, 136, 0, 0, // Skip to: 2851 -/* 2715 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2718 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2755 -/* 2724 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2727 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2741 -/* 2732 */ MCD_OPC_CheckPredicate, 21, 200, 61, 0, // Skip to: 18553 -/* 2737 */ MCD_OPC_Decode, 204, 7, 97, // Opcode: VABDsv4i16 -/* 2741 */ MCD_OPC_FilterValue, 1, 191, 61, 0, // Skip to: 18553 -/* 2746 */ MCD_OPC_CheckPredicate, 21, 186, 61, 0, // Skip to: 18553 -/* 2751 */ MCD_OPC_Decode, 206, 7, 98, // Opcode: VABDsv8i16 -/* 2755 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2792 -/* 2761 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2764 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2778 -/* 2769 */ MCD_OPC_CheckPredicate, 21, 163, 61, 0, // Skip to: 18553 -/* 2774 */ MCD_OPC_Decode, 193, 7, 99, // Opcode: VABDLsv4i32 -/* 2778 */ MCD_OPC_FilterValue, 1, 154, 61, 0, // Skip to: 18553 -/* 2783 */ MCD_OPC_CheckPredicate, 21, 149, 61, 0, // Skip to: 18553 -/* 2788 */ MCD_OPC_Decode, 194, 15, 109, // Opcode: VQDMLSLslv4i16 -/* 2792 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2829 -/* 2798 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2801 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2815 -/* 2806 */ MCD_OPC_CheckPredicate, 21, 126, 61, 0, // Skip to: 18553 -/* 2811 */ MCD_OPC_Decode, 210, 7, 97, // Opcode: VABDuv4i16 -/* 2815 */ MCD_OPC_FilterValue, 1, 117, 61, 0, // Skip to: 18553 -/* 2820 */ MCD_OPC_CheckPredicate, 21, 112, 61, 0, // Skip to: 18553 -/* 2825 */ MCD_OPC_Decode, 212, 7, 98, // Opcode: VABDuv8i16 -/* 2829 */ MCD_OPC_FilterValue, 231, 3, 102, 61, 0, // Skip to: 18553 -/* 2835 */ MCD_OPC_CheckPredicate, 21, 97, 61, 0, // Skip to: 18553 -/* 2840 */ MCD_OPC_CheckField, 6, 1, 0, 90, 61, 0, // Skip to: 18553 -/* 2847 */ MCD_OPC_Decode, 196, 7, 99, // Opcode: VABDLuv4i32 -/* 2851 */ MCD_OPC_FilterValue, 8, 151, 0, 0, // Skip to: 3007 -/* 2856 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2859 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2896 -/* 2865 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2868 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2882 -/* 2873 */ MCD_OPC_CheckPredicate, 21, 59, 61, 0, // Skip to: 18553 -/* 2878 */ MCD_OPC_Decode, 133, 8, 97, // Opcode: VADDv4i16 -/* 2882 */ MCD_OPC_FilterValue, 1, 50, 61, 0, // Skip to: 18553 -/* 2887 */ MCD_OPC_CheckPredicate, 21, 45, 61, 0, // Skip to: 18553 -/* 2892 */ MCD_OPC_Decode, 135, 8, 98, // Opcode: VADDv8i16 -/* 2896 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2933 -/* 2902 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2905 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2919 -/* 2910 */ MCD_OPC_CheckPredicate, 21, 22, 61, 0, // Skip to: 18553 -/* 2915 */ MCD_OPC_Decode, 209, 13, 104, // Opcode: VMLALsv4i32 -/* 2919 */ MCD_OPC_FilterValue, 1, 13, 61, 0, // Skip to: 18553 -/* 2924 */ MCD_OPC_CheckPredicate, 21, 8, 61, 0, // Skip to: 18553 -/* 2929 */ MCD_OPC_Decode, 205, 14, 110, // Opcode: VMULslv4i16 -/* 2933 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2970 -/* 2939 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2942 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2956 -/* 2947 */ MCD_OPC_CheckPredicate, 21, 241, 60, 0, // Skip to: 18553 -/* 2952 */ MCD_OPC_Decode, 233, 20, 97, // Opcode: VSUBv4i16 -/* 2956 */ MCD_OPC_FilterValue, 1, 232, 60, 0, // Skip to: 18553 -/* 2961 */ MCD_OPC_CheckPredicate, 21, 227, 60, 0, // Skip to: 18553 -/* 2966 */ MCD_OPC_Decode, 235, 20, 98, // Opcode: VSUBv8i16 -/* 2970 */ MCD_OPC_FilterValue, 231, 3, 217, 60, 0, // Skip to: 18553 -/* 2976 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2979 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2993 -/* 2984 */ MCD_OPC_CheckPredicate, 21, 204, 60, 0, // Skip to: 18553 -/* 2989 */ MCD_OPC_Decode, 212, 13, 104, // Opcode: VMLALuv4i32 -/* 2993 */ MCD_OPC_FilterValue, 1, 195, 60, 0, // Skip to: 18553 -/* 2998 */ MCD_OPC_CheckPredicate, 21, 190, 60, 0, // Skip to: 18553 -/* 3003 */ MCD_OPC_Decode, 207, 14, 111, // Opcode: VMULslv8i16 -/* 3007 */ MCD_OPC_FilterValue, 9, 136, 0, 0, // Skip to: 3148 -/* 3012 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3015 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3052 -/* 3021 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3024 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3038 -/* 3029 */ MCD_OPC_CheckPredicate, 21, 159, 60, 0, // Skip to: 18553 -/* 3034 */ MCD_OPC_Decode, 229, 13, 105, // Opcode: VMLAv4i16 -/* 3038 */ MCD_OPC_FilterValue, 1, 150, 60, 0, // Skip to: 18553 -/* 3043 */ MCD_OPC_CheckPredicate, 21, 145, 60, 0, // Skip to: 18553 -/* 3048 */ MCD_OPC_Decode, 231, 13, 106, // Opcode: VMLAv8i16 -/* 3052 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3089 -/* 3058 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3061 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3075 -/* 3066 */ MCD_OPC_CheckPredicate, 21, 122, 60, 0, // Skip to: 18553 -/* 3071 */ MCD_OPC_Decode, 192, 15, 104, // Opcode: VQDMLALv4i32 -/* 3075 */ MCD_OPC_FilterValue, 1, 113, 60, 0, // Skip to: 18553 -/* 3080 */ MCD_OPC_CheckPredicate, 22, 108, 60, 0, // Skip to: 18553 -/* 3085 */ MCD_OPC_Decode, 202, 14, 110, // Opcode: VMULslhd -/* 3089 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3126 -/* 3095 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3098 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3112 -/* 3103 */ MCD_OPC_CheckPredicate, 21, 85, 60, 0, // Skip to: 18553 -/* 3108 */ MCD_OPC_Decode, 132, 14, 105, // Opcode: VMLSv4i16 -/* 3112 */ MCD_OPC_FilterValue, 1, 76, 60, 0, // Skip to: 18553 -/* 3117 */ MCD_OPC_CheckPredicate, 21, 71, 60, 0, // Skip to: 18553 -/* 3122 */ MCD_OPC_Decode, 134, 14, 106, // Opcode: VMLSv8i16 -/* 3126 */ MCD_OPC_FilterValue, 231, 3, 61, 60, 0, // Skip to: 18553 -/* 3132 */ MCD_OPC_CheckPredicate, 22, 56, 60, 0, // Skip to: 18553 -/* 3137 */ MCD_OPC_CheckField, 6, 1, 1, 49, 60, 0, // Skip to: 18553 -/* 3144 */ MCD_OPC_Decode, 203, 14, 111, // Opcode: VMULslhq -/* 3148 */ MCD_OPC_FilterValue, 10, 121, 0, 0, // Skip to: 3274 -/* 3153 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3156 */ MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 3178 -/* 3162 */ MCD_OPC_CheckPredicate, 21, 26, 60, 0, // Skip to: 18553 -/* 3167 */ MCD_OPC_CheckField, 6, 1, 0, 19, 60, 0, // Skip to: 18553 -/* 3174 */ MCD_OPC_Decode, 153, 15, 97, // Opcode: VPMAXs16 -/* 3178 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3215 -/* 3184 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3187 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3201 -/* 3192 */ MCD_OPC_CheckPredicate, 21, 252, 59, 0, // Skip to: 18553 -/* 3197 */ MCD_OPC_Decode, 240, 13, 104, // Opcode: VMLSLsv4i32 -/* 3201 */ MCD_OPC_FilterValue, 1, 243, 59, 0, // Skip to: 18553 -/* 3206 */ MCD_OPC_CheckPredicate, 21, 238, 59, 0, // Skip to: 18553 -/* 3211 */ MCD_OPC_Decode, 184, 14, 112, // Opcode: VMULLslsv4i16 -/* 3215 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3237 -/* 3221 */ MCD_OPC_CheckPredicate, 21, 223, 59, 0, // Skip to: 18553 -/* 3226 */ MCD_OPC_CheckField, 6, 1, 0, 216, 59, 0, // Skip to: 18553 -/* 3233 */ MCD_OPC_Decode, 156, 15, 97, // Opcode: VPMAXu16 -/* 3237 */ MCD_OPC_FilterValue, 231, 3, 206, 59, 0, // Skip to: 18553 -/* 3243 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3246 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3260 -/* 3251 */ MCD_OPC_CheckPredicate, 21, 193, 59, 0, // Skip to: 18553 -/* 3256 */ MCD_OPC_Decode, 243, 13, 104, // Opcode: VMLSLuv4i32 -/* 3260 */ MCD_OPC_FilterValue, 1, 184, 59, 0, // Skip to: 18553 -/* 3265 */ MCD_OPC_CheckPredicate, 21, 179, 59, 0, // Skip to: 18553 -/* 3270 */ MCD_OPC_Decode, 186, 14, 112, // Opcode: VMULLsluv4i16 -/* 3274 */ MCD_OPC_FilterValue, 11, 114, 0, 0, // Skip to: 3393 -/* 3279 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3282 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3319 -/* 3288 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3291 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3305 -/* 3296 */ MCD_OPC_CheckPredicate, 21, 148, 59, 0, // Skip to: 18553 -/* 3301 */ MCD_OPC_Decode, 202, 15, 97, // Opcode: VQDMULHv4i16 -/* 3305 */ MCD_OPC_FilterValue, 1, 139, 59, 0, // Skip to: 18553 -/* 3310 */ MCD_OPC_CheckPredicate, 21, 134, 59, 0, // Skip to: 18553 -/* 3315 */ MCD_OPC_Decode, 204, 15, 98, // Opcode: VQDMULHv8i16 -/* 3319 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3356 -/* 3325 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3328 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3342 -/* 3333 */ MCD_OPC_CheckPredicate, 21, 111, 59, 0, // Skip to: 18553 -/* 3338 */ MCD_OPC_Decode, 196, 15, 104, // Opcode: VQDMLSLv4i32 -/* 3342 */ MCD_OPC_FilterValue, 1, 102, 59, 0, // Skip to: 18553 -/* 3347 */ MCD_OPC_CheckPredicate, 21, 97, 59, 0, // Skip to: 18553 -/* 3352 */ MCD_OPC_Decode, 206, 15, 112, // Opcode: VQDMULLslv4i16 -/* 3356 */ MCD_OPC_FilterValue, 230, 3, 87, 59, 0, // Skip to: 18553 -/* 3362 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3365 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3379 -/* 3370 */ MCD_OPC_CheckPredicate, 21, 74, 59, 0, // Skip to: 18553 -/* 3375 */ MCD_OPC_Decode, 245, 15, 97, // Opcode: VQRDMULHv4i16 -/* 3379 */ MCD_OPC_FilterValue, 1, 65, 59, 0, // Skip to: 18553 -/* 3384 */ MCD_OPC_CheckPredicate, 21, 60, 59, 0, // Skip to: 18553 -/* 3389 */ MCD_OPC_Decode, 247, 15, 98, // Opcode: VQRDMULHv8i16 -/* 3393 */ MCD_OPC_FilterValue, 12, 79, 0, 0, // Skip to: 3477 -/* 3398 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3401 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 3439 -/* 3406 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3409 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 3424 -/* 3415 */ MCD_OPC_CheckPredicate, 21, 29, 59, 0, // Skip to: 18553 -/* 3420 */ MCD_OPC_Decode, 188, 14, 99, // Opcode: VMULLsv4i32 -/* 3424 */ MCD_OPC_FilterValue, 231, 3, 19, 59, 0, // Skip to: 18553 -/* 3430 */ MCD_OPC_CheckPredicate, 21, 14, 59, 0, // Skip to: 18553 -/* 3435 */ MCD_OPC_Decode, 191, 14, 99, // Opcode: VMULLuv4i32 -/* 3439 */ MCD_OPC_FilterValue, 1, 5, 59, 0, // Skip to: 18553 -/* 3444 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3447 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 3462 -/* 3453 */ MCD_OPC_CheckPredicate, 21, 247, 58, 0, // Skip to: 18553 -/* 3458 */ MCD_OPC_Decode, 198, 15, 110, // Opcode: VQDMULHslv4i16 -/* 3462 */ MCD_OPC_FilterValue, 231, 3, 237, 58, 0, // Skip to: 18553 -/* 3468 */ MCD_OPC_CheckPredicate, 21, 232, 58, 0, // Skip to: 18553 -/* 3473 */ MCD_OPC_Decode, 200, 15, 111, // Opcode: VQDMULHslv8i16 -/* 3477 */ MCD_OPC_FilterValue, 13, 121, 0, 0, // Skip to: 3603 -/* 3482 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3485 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3522 -/* 3491 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3494 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3508 -/* 3499 */ MCD_OPC_CheckPredicate, 22, 201, 58, 0, // Skip to: 18553 -/* 3504 */ MCD_OPC_Decode, 255, 7, 97, // Opcode: VADDhd -/* 3508 */ MCD_OPC_FilterValue, 1, 192, 58, 0, // Skip to: 18553 -/* 3513 */ MCD_OPC_CheckPredicate, 22, 187, 58, 0, // Skip to: 18553 -/* 3518 */ MCD_OPC_Decode, 128, 8, 98, // Opcode: VADDhq -/* 3522 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3559 -/* 3528 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3531 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3545 -/* 3536 */ MCD_OPC_CheckPredicate, 21, 164, 58, 0, // Skip to: 18553 -/* 3541 */ MCD_OPC_Decode, 208, 15, 99, // Opcode: VQDMULLv4i32 -/* 3545 */ MCD_OPC_FilterValue, 1, 155, 58, 0, // Skip to: 18553 -/* 3550 */ MCD_OPC_CheckPredicate, 21, 150, 58, 0, // Skip to: 18553 -/* 3555 */ MCD_OPC_Decode, 241, 15, 110, // Opcode: VQRDMULHslv4i16 -/* 3559 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3581 -/* 3565 */ MCD_OPC_CheckPredicate, 22, 135, 58, 0, // Skip to: 18553 -/* 3570 */ MCD_OPC_CheckField, 6, 1, 0, 128, 58, 0, // Skip to: 18553 -/* 3577 */ MCD_OPC_Decode, 147, 15, 97, // Opcode: VPADDh -/* 3581 */ MCD_OPC_FilterValue, 231, 3, 118, 58, 0, // Skip to: 18553 -/* 3587 */ MCD_OPC_CheckPredicate, 21, 113, 58, 0, // Skip to: 18553 -/* 3592 */ MCD_OPC_CheckField, 6, 1, 1, 106, 58, 0, // Skip to: 18553 -/* 3599 */ MCD_OPC_Decode, 243, 15, 111, // Opcode: VQRDMULHslv8i16 -/* 3603 */ MCD_OPC_FilterValue, 14, 121, 0, 0, // Skip to: 3729 -/* 3608 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3611 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3648 -/* 3617 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3620 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3634 -/* 3625 */ MCD_OPC_CheckPredicate, 22, 75, 58, 0, // Skip to: 18553 -/* 3630 */ MCD_OPC_Decode, 157, 8, 97, // Opcode: VCEQhd -/* 3634 */ MCD_OPC_FilterValue, 1, 66, 58, 0, // Skip to: 18553 -/* 3639 */ MCD_OPC_CheckPredicate, 22, 61, 58, 0, // Skip to: 18553 -/* 3644 */ MCD_OPC_Decode, 158, 8, 98, // Opcode: VCEQhq -/* 3648 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 3670 -/* 3654 */ MCD_OPC_CheckPredicate, 23, 46, 58, 0, // Skip to: 18553 -/* 3659 */ MCD_OPC_CheckField, 6, 1, 1, 39, 58, 0, // Skip to: 18553 -/* 3666 */ MCD_OPC_Decode, 225, 15, 107, // Opcode: VQRDMLAHslv4i16 -/* 3670 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3707 -/* 3676 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3679 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3693 -/* 3684 */ MCD_OPC_CheckPredicate, 22, 16, 58, 0, // Skip to: 18553 -/* 3689 */ MCD_OPC_Decode, 177, 8, 97, // Opcode: VCGEhd -/* 3693 */ MCD_OPC_FilterValue, 1, 7, 58, 0, // Skip to: 18553 -/* 3698 */ MCD_OPC_CheckPredicate, 22, 2, 58, 0, // Skip to: 18553 -/* 3703 */ MCD_OPC_Decode, 178, 8, 98, // Opcode: VCGEhq -/* 3707 */ MCD_OPC_FilterValue, 231, 3, 248, 57, 0, // Skip to: 18553 -/* 3713 */ MCD_OPC_CheckPredicate, 23, 243, 57, 0, // Skip to: 18553 -/* 3718 */ MCD_OPC_CheckField, 6, 1, 1, 236, 57, 0, // Skip to: 18553 -/* 3725 */ MCD_OPC_Decode, 227, 15, 108, // Opcode: VQRDMLAHslv8i16 -/* 3729 */ MCD_OPC_FilterValue, 15, 227, 57, 0, // Skip to: 18553 -/* 3734 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3737 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3774 -/* 3743 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3746 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3760 -/* 3751 */ MCD_OPC_CheckPredicate, 22, 205, 57, 0, // Skip to: 18553 -/* 3756 */ MCD_OPC_Decode, 165, 13, 97, // Opcode: VMAXhd -/* 3760 */ MCD_OPC_FilterValue, 1, 196, 57, 0, // Skip to: 18553 -/* 3765 */ MCD_OPC_CheckPredicate, 22, 191, 57, 0, // Skip to: 18553 -/* 3770 */ MCD_OPC_Decode, 166, 13, 98, // Opcode: VMAXhq -/* 3774 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 3796 -/* 3780 */ MCD_OPC_CheckPredicate, 23, 176, 57, 0, // Skip to: 18553 -/* 3785 */ MCD_OPC_CheckField, 6, 1, 1, 169, 57, 0, // Skip to: 18553 -/* 3792 */ MCD_OPC_Decode, 233, 15, 107, // Opcode: VQRDMLSHslv4i16 -/* 3796 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3818 -/* 3802 */ MCD_OPC_CheckPredicate, 22, 154, 57, 0, // Skip to: 18553 -/* 3807 */ MCD_OPC_CheckField, 6, 1, 0, 147, 57, 0, // Skip to: 18553 -/* 3814 */ MCD_OPC_Decode, 152, 15, 97, // Opcode: VPMAXh -/* 3818 */ MCD_OPC_FilterValue, 231, 3, 137, 57, 0, // Skip to: 18553 -/* 3824 */ MCD_OPC_CheckPredicate, 23, 132, 57, 0, // Skip to: 18553 -/* 3829 */ MCD_OPC_CheckField, 6, 1, 1, 125, 57, 0, // Skip to: 18553 -/* 3836 */ MCD_OPC_Decode, 235, 15, 108, // Opcode: VQRDMLSHslv8i16 -/* 3840 */ MCD_OPC_FilterValue, 2, 155, 8, 0, // Skip to: 6048 -/* 3845 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 3848 */ MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 4004 -/* 3853 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3856 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3893 -/* 3862 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3865 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3879 -/* 3870 */ MCD_OPC_CheckPredicate, 21, 86, 57, 0, // Skip to: 18553 -/* 3875 */ MCD_OPC_Decode, 175, 10, 97, // Opcode: VHADDsv2i32 -/* 3879 */ MCD_OPC_FilterValue, 1, 77, 57, 0, // Skip to: 18553 -/* 3884 */ MCD_OPC_CheckPredicate, 21, 72, 57, 0, // Skip to: 18553 -/* 3889 */ MCD_OPC_Decode, 177, 10, 98, // Opcode: VHADDsv4i32 -/* 3893 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3930 -/* 3899 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3902 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3916 -/* 3907 */ MCD_OPC_CheckPredicate, 21, 49, 57, 0, // Skip to: 18553 -/* 3912 */ MCD_OPC_Decode, 240, 7, 99, // Opcode: VADDLsv2i64 -/* 3916 */ MCD_OPC_FilterValue, 1, 40, 57, 0, // Skip to: 18553 -/* 3921 */ MCD_OPC_CheckPredicate, 21, 35, 57, 0, // Skip to: 18553 -/* 3926 */ MCD_OPC_Decode, 223, 13, 113, // Opcode: VMLAslv2i32 -/* 3930 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3967 -/* 3936 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3939 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3953 -/* 3944 */ MCD_OPC_CheckPredicate, 21, 12, 57, 0, // Skip to: 18553 -/* 3949 */ MCD_OPC_Decode, 181, 10, 97, // Opcode: VHADDuv2i32 -/* 3953 */ MCD_OPC_FilterValue, 1, 3, 57, 0, // Skip to: 18553 -/* 3958 */ MCD_OPC_CheckPredicate, 21, 254, 56, 0, // Skip to: 18553 -/* 3963 */ MCD_OPC_Decode, 183, 10, 98, // Opcode: VHADDuv4i32 -/* 3967 */ MCD_OPC_FilterValue, 231, 3, 244, 56, 0, // Skip to: 18553 -/* 3973 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3976 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3990 -/* 3981 */ MCD_OPC_CheckPredicate, 21, 231, 56, 0, // Skip to: 18553 -/* 3986 */ MCD_OPC_Decode, 243, 7, 99, // Opcode: VADDLuv2i64 -/* 3990 */ MCD_OPC_FilterValue, 1, 222, 56, 0, // Skip to: 18553 -/* 3995 */ MCD_OPC_CheckPredicate, 21, 217, 56, 0, // Skip to: 18553 -/* 4000 */ MCD_OPC_Decode, 225, 13, 114, // Opcode: VMLAslv4i32 -/* 4004 */ MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 4160 -/* 4009 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4012 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4049 -/* 4018 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4021 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4035 -/* 4026 */ MCD_OPC_CheckPredicate, 21, 186, 56, 0, // Skip to: 18553 -/* 4031 */ MCD_OPC_Decode, 236, 16, 97, // Opcode: VRHADDsv2i32 -/* 4035 */ MCD_OPC_FilterValue, 1, 177, 56, 0, // Skip to: 18553 -/* 4040 */ MCD_OPC_CheckPredicate, 21, 172, 56, 0, // Skip to: 18553 -/* 4045 */ MCD_OPC_Decode, 238, 16, 98, // Opcode: VRHADDsv4i32 -/* 4049 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4086 -/* 4055 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4058 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4072 -/* 4063 */ MCD_OPC_CheckPredicate, 21, 149, 56, 0, // Skip to: 18553 -/* 4068 */ MCD_OPC_Decode, 247, 7, 100, // Opcode: VADDWsv2i64 -/* 4072 */ MCD_OPC_FilterValue, 1, 140, 56, 0, // Skip to: 18553 -/* 4077 */ MCD_OPC_CheckPredicate, 21, 135, 56, 0, // Skip to: 18553 -/* 4082 */ MCD_OPC_Decode, 219, 13, 113, // Opcode: VMLAslfd -/* 4086 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4123 -/* 4092 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4095 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4109 -/* 4100 */ MCD_OPC_CheckPredicate, 21, 112, 56, 0, // Skip to: 18553 -/* 4105 */ MCD_OPC_Decode, 242, 16, 97, // Opcode: VRHADDuv2i32 -/* 4109 */ MCD_OPC_FilterValue, 1, 103, 56, 0, // Skip to: 18553 -/* 4114 */ MCD_OPC_CheckPredicate, 21, 98, 56, 0, // Skip to: 18553 -/* 4119 */ MCD_OPC_Decode, 244, 16, 98, // Opcode: VRHADDuv4i32 -/* 4123 */ MCD_OPC_FilterValue, 231, 3, 88, 56, 0, // Skip to: 18553 -/* 4129 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4132 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4146 -/* 4137 */ MCD_OPC_CheckPredicate, 21, 75, 56, 0, // Skip to: 18553 -/* 4142 */ MCD_OPC_Decode, 250, 7, 100, // Opcode: VADDWuv2i64 -/* 4146 */ MCD_OPC_FilterValue, 1, 66, 56, 0, // Skip to: 18553 -/* 4151 */ MCD_OPC_CheckPredicate, 21, 61, 56, 0, // Skip to: 18553 -/* 4156 */ MCD_OPC_Decode, 220, 13, 114, // Opcode: VMLAslfq -/* 4160 */ MCD_OPC_FilterValue, 2, 151, 0, 0, // Skip to: 4316 -/* 4165 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4168 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4205 -/* 4174 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4177 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4191 -/* 4182 */ MCD_OPC_CheckPredicate, 21, 30, 56, 0, // Skip to: 18553 -/* 4187 */ MCD_OPC_Decode, 187, 10, 97, // Opcode: VHSUBsv2i32 -/* 4191 */ MCD_OPC_FilterValue, 1, 21, 56, 0, // Skip to: 18553 -/* 4196 */ MCD_OPC_CheckPredicate, 21, 16, 56, 0, // Skip to: 18553 -/* 4201 */ MCD_OPC_Decode, 189, 10, 98, // Opcode: VHSUBsv4i32 -/* 4205 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4242 -/* 4211 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4214 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4228 -/* 4219 */ MCD_OPC_CheckPredicate, 21, 249, 55, 0, // Skip to: 18553 -/* 4224 */ MCD_OPC_Decode, 212, 20, 99, // Opcode: VSUBLsv2i64 -/* 4228 */ MCD_OPC_FilterValue, 1, 240, 55, 0, // Skip to: 18553 -/* 4233 */ MCD_OPC_CheckPredicate, 21, 235, 55, 0, // Skip to: 18553 -/* 4238 */ MCD_OPC_Decode, 204, 13, 115, // Opcode: VMLALslsv2i32 -/* 4242 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4279 -/* 4248 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4251 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4265 -/* 4256 */ MCD_OPC_CheckPredicate, 21, 212, 55, 0, // Skip to: 18553 -/* 4261 */ MCD_OPC_Decode, 193, 10, 97, // Opcode: VHSUBuv2i32 -/* 4265 */ MCD_OPC_FilterValue, 1, 203, 55, 0, // Skip to: 18553 -/* 4270 */ MCD_OPC_CheckPredicate, 21, 198, 55, 0, // Skip to: 18553 -/* 4275 */ MCD_OPC_Decode, 195, 10, 98, // Opcode: VHSUBuv4i32 -/* 4279 */ MCD_OPC_FilterValue, 231, 3, 188, 55, 0, // Skip to: 18553 -/* 4285 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4288 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4302 -/* 4293 */ MCD_OPC_CheckPredicate, 21, 175, 55, 0, // Skip to: 18553 -/* 4298 */ MCD_OPC_Decode, 215, 20, 99, // Opcode: VSUBLuv2i64 -/* 4302 */ MCD_OPC_FilterValue, 1, 166, 55, 0, // Skip to: 18553 -/* 4307 */ MCD_OPC_CheckPredicate, 21, 161, 55, 0, // Skip to: 18553 -/* 4312 */ MCD_OPC_Decode, 206, 13, 115, // Opcode: VMLALsluv2i32 -/* 4316 */ MCD_OPC_FilterValue, 3, 136, 0, 0, // Skip to: 4457 -/* 4321 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4324 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4361 -/* 4330 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4333 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4347 -/* 4338 */ MCD_OPC_CheckPredicate, 21, 130, 55, 0, // Skip to: 18553 -/* 4343 */ MCD_OPC_Decode, 206, 8, 97, // Opcode: VCGTsv2i32 -/* 4347 */ MCD_OPC_FilterValue, 1, 121, 55, 0, // Skip to: 18553 -/* 4352 */ MCD_OPC_CheckPredicate, 21, 116, 55, 0, // Skip to: 18553 -/* 4357 */ MCD_OPC_Decode, 208, 8, 98, // Opcode: VCGTsv4i32 -/* 4361 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4398 -/* 4367 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4370 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4384 -/* 4375 */ MCD_OPC_CheckPredicate, 21, 93, 55, 0, // Skip to: 18553 -/* 4380 */ MCD_OPC_Decode, 219, 20, 100, // Opcode: VSUBWsv2i64 -/* 4384 */ MCD_OPC_FilterValue, 1, 84, 55, 0, // Skip to: 18553 -/* 4389 */ MCD_OPC_CheckPredicate, 21, 79, 55, 0, // Skip to: 18553 -/* 4394 */ MCD_OPC_Decode, 189, 15, 115, // Opcode: VQDMLALslv2i32 -/* 4398 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4435 -/* 4404 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4407 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4421 -/* 4412 */ MCD_OPC_CheckPredicate, 21, 56, 55, 0, // Skip to: 18553 -/* 4417 */ MCD_OPC_Decode, 212, 8, 97, // Opcode: VCGTuv2i32 -/* 4421 */ MCD_OPC_FilterValue, 1, 47, 55, 0, // Skip to: 18553 -/* 4426 */ MCD_OPC_CheckPredicate, 21, 42, 55, 0, // Skip to: 18553 -/* 4431 */ MCD_OPC_Decode, 214, 8, 98, // Opcode: VCGTuv4i32 -/* 4435 */ MCD_OPC_FilterValue, 231, 3, 32, 55, 0, // Skip to: 18553 -/* 4441 */ MCD_OPC_CheckPredicate, 21, 27, 55, 0, // Skip to: 18553 -/* 4446 */ MCD_OPC_CheckField, 6, 1, 0, 20, 55, 0, // Skip to: 18553 -/* 4453 */ MCD_OPC_Decode, 222, 20, 100, // Opcode: VSUBWuv2i64 -/* 4457 */ MCD_OPC_FilterValue, 4, 151, 0, 0, // Skip to: 4613 -/* 4462 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4465 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4502 -/* 4471 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4474 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4488 -/* 4479 */ MCD_OPC_CheckPredicate, 21, 245, 54, 0, // Skip to: 18553 -/* 4484 */ MCD_OPC_Decode, 138, 18, 101, // Opcode: VSHLsv2i32 -/* 4488 */ MCD_OPC_FilterValue, 1, 236, 54, 0, // Skip to: 18553 -/* 4493 */ MCD_OPC_CheckPredicate, 21, 231, 54, 0, // Skip to: 18553 -/* 4498 */ MCD_OPC_Decode, 141, 18, 102, // Opcode: VSHLsv4i32 -/* 4502 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4539 -/* 4508 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4511 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4525 -/* 4516 */ MCD_OPC_CheckPredicate, 21, 208, 54, 0, // Skip to: 18553 -/* 4521 */ MCD_OPC_Decode, 237, 7, 103, // Opcode: VADDHNv2i32 -/* 4525 */ MCD_OPC_FilterValue, 1, 199, 54, 0, // Skip to: 18553 -/* 4530 */ MCD_OPC_CheckPredicate, 21, 194, 54, 0, // Skip to: 18553 -/* 4535 */ MCD_OPC_Decode, 254, 13, 113, // Opcode: VMLSslv2i32 -/* 4539 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4576 -/* 4545 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4548 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4562 -/* 4553 */ MCD_OPC_CheckPredicate, 21, 171, 54, 0, // Skip to: 18553 -/* 4558 */ MCD_OPC_Decode, 146, 18, 101, // Opcode: VSHLuv2i32 -/* 4562 */ MCD_OPC_FilterValue, 1, 162, 54, 0, // Skip to: 18553 -/* 4567 */ MCD_OPC_CheckPredicate, 21, 157, 54, 0, // Skip to: 18553 -/* 4572 */ MCD_OPC_Decode, 149, 18, 102, // Opcode: VSHLuv4i32 -/* 4576 */ MCD_OPC_FilterValue, 231, 3, 147, 54, 0, // Skip to: 18553 -/* 4582 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4585 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4599 -/* 4590 */ MCD_OPC_CheckPredicate, 21, 134, 54, 0, // Skip to: 18553 -/* 4595 */ MCD_OPC_Decode, 210, 16, 103, // Opcode: VRADDHNv2i32 -/* 4599 */ MCD_OPC_FilterValue, 1, 125, 54, 0, // Skip to: 18553 -/* 4604 */ MCD_OPC_CheckPredicate, 21, 120, 54, 0, // Skip to: 18553 -/* 4609 */ MCD_OPC_Decode, 128, 14, 114, // Opcode: VMLSslv4i32 -/* 4613 */ MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 4769 -/* 4618 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4621 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4658 -/* 4627 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4630 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4644 -/* 4635 */ MCD_OPC_CheckPredicate, 21, 89, 54, 0, // Skip to: 18553 -/* 4640 */ MCD_OPC_Decode, 166, 17, 101, // Opcode: VRSHLsv2i32 -/* 4644 */ MCD_OPC_FilterValue, 1, 80, 54, 0, // Skip to: 18553 -/* 4649 */ MCD_OPC_CheckPredicate, 21, 75, 54, 0, // Skip to: 18553 -/* 4654 */ MCD_OPC_Decode, 169, 17, 102, // Opcode: VRSHLsv4i32 -/* 4658 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4695 -/* 4664 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4667 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4681 -/* 4672 */ MCD_OPC_CheckPredicate, 21, 52, 54, 0, // Skip to: 18553 -/* 4677 */ MCD_OPC_Decode, 174, 7, 104, // Opcode: VABALsv2i64 -/* 4681 */ MCD_OPC_FilterValue, 1, 43, 54, 0, // Skip to: 18553 -/* 4686 */ MCD_OPC_CheckPredicate, 21, 38, 54, 0, // Skip to: 18553 -/* 4691 */ MCD_OPC_Decode, 250, 13, 113, // Opcode: VMLSslfd -/* 4695 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4732 -/* 4701 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4704 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4718 -/* 4709 */ MCD_OPC_CheckPredicate, 21, 15, 54, 0, // Skip to: 18553 -/* 4714 */ MCD_OPC_Decode, 174, 17, 101, // Opcode: VRSHLuv2i32 -/* 4718 */ MCD_OPC_FilterValue, 1, 6, 54, 0, // Skip to: 18553 -/* 4723 */ MCD_OPC_CheckPredicate, 21, 1, 54, 0, // Skip to: 18553 -/* 4728 */ MCD_OPC_Decode, 177, 17, 102, // Opcode: VRSHLuv4i32 -/* 4732 */ MCD_OPC_FilterValue, 231, 3, 247, 53, 0, // Skip to: 18553 -/* 4738 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4741 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4755 -/* 4746 */ MCD_OPC_CheckPredicate, 21, 234, 53, 0, // Skip to: 18553 -/* 4751 */ MCD_OPC_Decode, 177, 7, 104, // Opcode: VABALuv2i64 -/* 4755 */ MCD_OPC_FilterValue, 1, 225, 53, 0, // Skip to: 18553 -/* 4760 */ MCD_OPC_CheckPredicate, 21, 220, 53, 0, // Skip to: 18553 -/* 4765 */ MCD_OPC_Decode, 251, 13, 114, // Opcode: VMLSslfq -/* 4769 */ MCD_OPC_FilterValue, 6, 151, 0, 0, // Skip to: 4925 -/* 4774 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4777 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4814 -/* 4783 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4786 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4800 -/* 4791 */ MCD_OPC_CheckPredicate, 21, 189, 53, 0, // Skip to: 18553 -/* 4796 */ MCD_OPC_Decode, 168, 13, 97, // Opcode: VMAXsv2i32 -/* 4800 */ MCD_OPC_FilterValue, 1, 180, 53, 0, // Skip to: 18553 -/* 4805 */ MCD_OPC_CheckPredicate, 21, 175, 53, 0, // Skip to: 18553 -/* 4810 */ MCD_OPC_Decode, 170, 13, 98, // Opcode: VMAXsv4i32 -/* 4814 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4851 -/* 4820 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4823 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4837 -/* 4828 */ MCD_OPC_CheckPredicate, 21, 152, 53, 0, // Skip to: 18553 -/* 4833 */ MCD_OPC_Decode, 209, 20, 103, // Opcode: VSUBHNv2i32 -/* 4837 */ MCD_OPC_FilterValue, 1, 143, 53, 0, // Skip to: 18553 -/* 4842 */ MCD_OPC_CheckPredicate, 21, 138, 53, 0, // Skip to: 18553 -/* 4847 */ MCD_OPC_Decode, 235, 13, 115, // Opcode: VMLSLslsv2i32 -/* 4851 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4888 -/* 4857 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4860 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4874 -/* 4865 */ MCD_OPC_CheckPredicate, 21, 115, 53, 0, // Skip to: 18553 -/* 4870 */ MCD_OPC_Decode, 174, 13, 97, // Opcode: VMAXuv2i32 -/* 4874 */ MCD_OPC_FilterValue, 1, 106, 53, 0, // Skip to: 18553 -/* 4879 */ MCD_OPC_CheckPredicate, 21, 101, 53, 0, // Skip to: 18553 -/* 4884 */ MCD_OPC_Decode, 176, 13, 98, // Opcode: VMAXuv4i32 -/* 4888 */ MCD_OPC_FilterValue, 231, 3, 91, 53, 0, // Skip to: 18553 -/* 4894 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4897 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4911 -/* 4902 */ MCD_OPC_CheckPredicate, 21, 78, 53, 0, // Skip to: 18553 -/* 4907 */ MCD_OPC_Decode, 225, 17, 103, // Opcode: VRSUBHNv2i32 -/* 4911 */ MCD_OPC_FilterValue, 1, 69, 53, 0, // Skip to: 18553 -/* 4916 */ MCD_OPC_CheckPredicate, 21, 64, 53, 0, // Skip to: 18553 -/* 4921 */ MCD_OPC_Decode, 237, 13, 115, // Opcode: VMLSLsluv2i32 -/* 4925 */ MCD_OPC_FilterValue, 7, 136, 0, 0, // Skip to: 5066 -/* 4930 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4933 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4970 -/* 4939 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4942 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4956 -/* 4947 */ MCD_OPC_CheckPredicate, 21, 33, 53, 0, // Skip to: 18553 -/* 4952 */ MCD_OPC_Decode, 203, 7, 97, // Opcode: VABDsv2i32 -/* 4956 */ MCD_OPC_FilterValue, 1, 24, 53, 0, // Skip to: 18553 -/* 4961 */ MCD_OPC_CheckPredicate, 21, 19, 53, 0, // Skip to: 18553 -/* 4966 */ MCD_OPC_Decode, 205, 7, 98, // Opcode: VABDsv4i32 -/* 4970 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5007 -/* 4976 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4979 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4993 -/* 4984 */ MCD_OPC_CheckPredicate, 21, 252, 52, 0, // Skip to: 18553 -/* 4989 */ MCD_OPC_Decode, 192, 7, 99, // Opcode: VABDLsv2i64 -/* 4993 */ MCD_OPC_FilterValue, 1, 243, 52, 0, // Skip to: 18553 -/* 4998 */ MCD_OPC_CheckPredicate, 21, 238, 52, 0, // Skip to: 18553 -/* 5003 */ MCD_OPC_Decode, 193, 15, 115, // Opcode: VQDMLSLslv2i32 -/* 5007 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5044 -/* 5013 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5016 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5030 -/* 5021 */ MCD_OPC_CheckPredicate, 21, 215, 52, 0, // Skip to: 18553 -/* 5026 */ MCD_OPC_Decode, 209, 7, 97, // Opcode: VABDuv2i32 -/* 5030 */ MCD_OPC_FilterValue, 1, 206, 52, 0, // Skip to: 18553 -/* 5035 */ MCD_OPC_CheckPredicate, 21, 201, 52, 0, // Skip to: 18553 -/* 5040 */ MCD_OPC_Decode, 211, 7, 98, // Opcode: VABDuv4i32 -/* 5044 */ MCD_OPC_FilterValue, 231, 3, 191, 52, 0, // Skip to: 18553 -/* 5050 */ MCD_OPC_CheckPredicate, 21, 186, 52, 0, // Skip to: 18553 -/* 5055 */ MCD_OPC_CheckField, 6, 1, 0, 179, 52, 0, // Skip to: 18553 -/* 5062 */ MCD_OPC_Decode, 195, 7, 99, // Opcode: VABDLuv2i64 -/* 5066 */ MCD_OPC_FilterValue, 8, 151, 0, 0, // Skip to: 5222 -/* 5071 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5074 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5111 -/* 5080 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5083 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5097 -/* 5088 */ MCD_OPC_CheckPredicate, 21, 148, 52, 0, // Skip to: 18553 -/* 5093 */ MCD_OPC_Decode, 131, 8, 97, // Opcode: VADDv2i32 -/* 5097 */ MCD_OPC_FilterValue, 1, 139, 52, 0, // Skip to: 18553 -/* 5102 */ MCD_OPC_CheckPredicate, 21, 134, 52, 0, // Skip to: 18553 -/* 5107 */ MCD_OPC_Decode, 134, 8, 98, // Opcode: VADDv4i32 -/* 5111 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5148 -/* 5117 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5120 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5134 -/* 5125 */ MCD_OPC_CheckPredicate, 21, 111, 52, 0, // Skip to: 18553 -/* 5130 */ MCD_OPC_Decode, 208, 13, 104, // Opcode: VMLALsv2i64 -/* 5134 */ MCD_OPC_FilterValue, 1, 102, 52, 0, // Skip to: 18553 -/* 5139 */ MCD_OPC_CheckPredicate, 21, 97, 52, 0, // Skip to: 18553 -/* 5144 */ MCD_OPC_Decode, 204, 14, 116, // Opcode: VMULslv2i32 -/* 5148 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5185 -/* 5154 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5157 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5171 -/* 5162 */ MCD_OPC_CheckPredicate, 21, 74, 52, 0, // Skip to: 18553 -/* 5167 */ MCD_OPC_Decode, 231, 20, 97, // Opcode: VSUBv2i32 -/* 5171 */ MCD_OPC_FilterValue, 1, 65, 52, 0, // Skip to: 18553 -/* 5176 */ MCD_OPC_CheckPredicate, 21, 60, 52, 0, // Skip to: 18553 -/* 5181 */ MCD_OPC_Decode, 234, 20, 98, // Opcode: VSUBv4i32 -/* 5185 */ MCD_OPC_FilterValue, 231, 3, 50, 52, 0, // Skip to: 18553 -/* 5191 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5194 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5208 -/* 5199 */ MCD_OPC_CheckPredicate, 21, 37, 52, 0, // Skip to: 18553 -/* 5204 */ MCD_OPC_Decode, 211, 13, 104, // Opcode: VMLALuv2i64 -/* 5208 */ MCD_OPC_FilterValue, 1, 28, 52, 0, // Skip to: 18553 -/* 5213 */ MCD_OPC_CheckPredicate, 21, 23, 52, 0, // Skip to: 18553 -/* 5218 */ MCD_OPC_Decode, 206, 14, 117, // Opcode: VMULslv4i32 -/* 5222 */ MCD_OPC_FilterValue, 9, 136, 0, 0, // Skip to: 5363 -/* 5227 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5230 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5267 -/* 5236 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5239 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5253 -/* 5244 */ MCD_OPC_CheckPredicate, 21, 248, 51, 0, // Skip to: 18553 -/* 5249 */ MCD_OPC_Decode, 228, 13, 105, // Opcode: VMLAv2i32 -/* 5253 */ MCD_OPC_FilterValue, 1, 239, 51, 0, // Skip to: 18553 -/* 5258 */ MCD_OPC_CheckPredicate, 21, 234, 51, 0, // Skip to: 18553 -/* 5263 */ MCD_OPC_Decode, 230, 13, 106, // Opcode: VMLAv4i32 -/* 5267 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5304 -/* 5273 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5276 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5290 -/* 5281 */ MCD_OPC_CheckPredicate, 21, 211, 51, 0, // Skip to: 18553 -/* 5286 */ MCD_OPC_Decode, 191, 15, 104, // Opcode: VQDMLALv2i64 -/* 5290 */ MCD_OPC_FilterValue, 1, 202, 51, 0, // Skip to: 18553 -/* 5295 */ MCD_OPC_CheckPredicate, 21, 197, 51, 0, // Skip to: 18553 -/* 5300 */ MCD_OPC_Decode, 200, 14, 116, // Opcode: VMULslfd -/* 5304 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5341 -/* 5310 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5313 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5327 -/* 5318 */ MCD_OPC_CheckPredicate, 21, 174, 51, 0, // Skip to: 18553 -/* 5323 */ MCD_OPC_Decode, 131, 14, 105, // Opcode: VMLSv2i32 -/* 5327 */ MCD_OPC_FilterValue, 1, 165, 51, 0, // Skip to: 18553 -/* 5332 */ MCD_OPC_CheckPredicate, 21, 160, 51, 0, // Skip to: 18553 -/* 5337 */ MCD_OPC_Decode, 133, 14, 106, // Opcode: VMLSv4i32 -/* 5341 */ MCD_OPC_FilterValue, 231, 3, 150, 51, 0, // Skip to: 18553 -/* 5347 */ MCD_OPC_CheckPredicate, 21, 145, 51, 0, // Skip to: 18553 -/* 5352 */ MCD_OPC_CheckField, 6, 1, 1, 138, 51, 0, // Skip to: 18553 -/* 5359 */ MCD_OPC_Decode, 201, 14, 117, // Opcode: VMULslfq -/* 5363 */ MCD_OPC_FilterValue, 10, 121, 0, 0, // Skip to: 5489 -/* 5368 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5371 */ MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 5393 -/* 5377 */ MCD_OPC_CheckPredicate, 21, 115, 51, 0, // Skip to: 18553 -/* 5382 */ MCD_OPC_CheckField, 6, 1, 0, 108, 51, 0, // Skip to: 18553 -/* 5389 */ MCD_OPC_Decode, 154, 15, 97, // Opcode: VPMAXs32 -/* 5393 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5430 -/* 5399 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5402 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5416 -/* 5407 */ MCD_OPC_CheckPredicate, 21, 85, 51, 0, // Skip to: 18553 -/* 5412 */ MCD_OPC_Decode, 239, 13, 104, // Opcode: VMLSLsv2i64 -/* 5416 */ MCD_OPC_FilterValue, 1, 76, 51, 0, // Skip to: 18553 -/* 5421 */ MCD_OPC_CheckPredicate, 21, 71, 51, 0, // Skip to: 18553 -/* 5426 */ MCD_OPC_Decode, 183, 14, 118, // Opcode: VMULLslsv2i32 -/* 5430 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 5452 -/* 5436 */ MCD_OPC_CheckPredicate, 21, 56, 51, 0, // Skip to: 18553 -/* 5441 */ MCD_OPC_CheckField, 6, 1, 0, 49, 51, 0, // Skip to: 18553 -/* 5448 */ MCD_OPC_Decode, 157, 15, 97, // Opcode: VPMAXu32 -/* 5452 */ MCD_OPC_FilterValue, 231, 3, 39, 51, 0, // Skip to: 18553 -/* 5458 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5461 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5475 -/* 5466 */ MCD_OPC_CheckPredicate, 21, 26, 51, 0, // Skip to: 18553 -/* 5471 */ MCD_OPC_Decode, 242, 13, 104, // Opcode: VMLSLuv2i64 -/* 5475 */ MCD_OPC_FilterValue, 1, 17, 51, 0, // Skip to: 18553 -/* 5480 */ MCD_OPC_CheckPredicate, 21, 12, 51, 0, // Skip to: 18553 -/* 5485 */ MCD_OPC_Decode, 185, 14, 118, // Opcode: VMULLsluv2i32 -/* 5489 */ MCD_OPC_FilterValue, 11, 114, 0, 0, // Skip to: 5608 -/* 5494 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5497 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5534 -/* 5503 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5506 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5520 -/* 5511 */ MCD_OPC_CheckPredicate, 21, 237, 50, 0, // Skip to: 18553 -/* 5516 */ MCD_OPC_Decode, 201, 15, 97, // Opcode: VQDMULHv2i32 -/* 5520 */ MCD_OPC_FilterValue, 1, 228, 50, 0, // Skip to: 18553 -/* 5525 */ MCD_OPC_CheckPredicate, 21, 223, 50, 0, // Skip to: 18553 -/* 5530 */ MCD_OPC_Decode, 203, 15, 98, // Opcode: VQDMULHv4i32 -/* 5534 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5571 -/* 5540 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5543 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5557 -/* 5548 */ MCD_OPC_CheckPredicate, 21, 200, 50, 0, // Skip to: 18553 -/* 5553 */ MCD_OPC_Decode, 195, 15, 104, // Opcode: VQDMLSLv2i64 -/* 5557 */ MCD_OPC_FilterValue, 1, 191, 50, 0, // Skip to: 18553 -/* 5562 */ MCD_OPC_CheckPredicate, 21, 186, 50, 0, // Skip to: 18553 -/* 5567 */ MCD_OPC_Decode, 205, 15, 118, // Opcode: VQDMULLslv2i32 -/* 5571 */ MCD_OPC_FilterValue, 230, 3, 176, 50, 0, // Skip to: 18553 -/* 5577 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5580 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5594 -/* 5585 */ MCD_OPC_CheckPredicate, 21, 163, 50, 0, // Skip to: 18553 -/* 5590 */ MCD_OPC_Decode, 244, 15, 97, // Opcode: VQRDMULHv2i32 -/* 5594 */ MCD_OPC_FilterValue, 1, 154, 50, 0, // Skip to: 18553 -/* 5599 */ MCD_OPC_CheckPredicate, 21, 149, 50, 0, // Skip to: 18553 -/* 5604 */ MCD_OPC_Decode, 246, 15, 98, // Opcode: VQRDMULHv4i32 -/* 5608 */ MCD_OPC_FilterValue, 12, 79, 0, 0, // Skip to: 5692 -/* 5613 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5616 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 5654 -/* 5621 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5624 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 5639 -/* 5630 */ MCD_OPC_CheckPredicate, 21, 118, 50, 0, // Skip to: 18553 -/* 5635 */ MCD_OPC_Decode, 187, 14, 99, // Opcode: VMULLsv2i64 -/* 5639 */ MCD_OPC_FilterValue, 231, 3, 108, 50, 0, // Skip to: 18553 -/* 5645 */ MCD_OPC_CheckPredicate, 21, 103, 50, 0, // Skip to: 18553 -/* 5650 */ MCD_OPC_Decode, 190, 14, 99, // Opcode: VMULLuv2i64 -/* 5654 */ MCD_OPC_FilterValue, 1, 94, 50, 0, // Skip to: 18553 -/* 5659 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5662 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 5677 -/* 5668 */ MCD_OPC_CheckPredicate, 21, 80, 50, 0, // Skip to: 18553 -/* 5673 */ MCD_OPC_Decode, 197, 15, 116, // Opcode: VQDMULHslv2i32 -/* 5677 */ MCD_OPC_FilterValue, 231, 3, 70, 50, 0, // Skip to: 18553 -/* 5683 */ MCD_OPC_CheckPredicate, 21, 65, 50, 0, // Skip to: 18553 -/* 5688 */ MCD_OPC_Decode, 199, 15, 117, // Opcode: VQDMULHslv4i32 -/* 5692 */ MCD_OPC_FilterValue, 13, 136, 0, 0, // Skip to: 5833 -/* 5697 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5700 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5737 -/* 5706 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5709 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5723 -/* 5714 */ MCD_OPC_CheckPredicate, 21, 34, 50, 0, // Skip to: 18553 -/* 5719 */ MCD_OPC_Decode, 225, 20, 97, // Opcode: VSUBfd -/* 5723 */ MCD_OPC_FilterValue, 1, 25, 50, 0, // Skip to: 18553 -/* 5728 */ MCD_OPC_CheckPredicate, 21, 20, 50, 0, // Skip to: 18553 -/* 5733 */ MCD_OPC_Decode, 226, 20, 98, // Opcode: VSUBfq -/* 5737 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5774 -/* 5743 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5746 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5760 -/* 5751 */ MCD_OPC_CheckPredicate, 21, 253, 49, 0, // Skip to: 18553 -/* 5756 */ MCD_OPC_Decode, 207, 15, 99, // Opcode: VQDMULLv2i64 -/* 5760 */ MCD_OPC_FilterValue, 1, 244, 49, 0, // Skip to: 18553 -/* 5765 */ MCD_OPC_CheckPredicate, 21, 239, 49, 0, // Skip to: 18553 -/* 5770 */ MCD_OPC_Decode, 240, 15, 116, // Opcode: VQRDMULHslv2i32 -/* 5774 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5811 -/* 5780 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5783 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5797 -/* 5788 */ MCD_OPC_CheckPredicate, 21, 216, 49, 0, // Skip to: 18553 -/* 5793 */ MCD_OPC_Decode, 198, 7, 97, // Opcode: VABDfd -/* 5797 */ MCD_OPC_FilterValue, 1, 207, 49, 0, // Skip to: 18553 -/* 5802 */ MCD_OPC_CheckPredicate, 21, 202, 49, 0, // Skip to: 18553 -/* 5807 */ MCD_OPC_Decode, 199, 7, 98, // Opcode: VABDfq -/* 5811 */ MCD_OPC_FilterValue, 231, 3, 192, 49, 0, // Skip to: 18553 -/* 5817 */ MCD_OPC_CheckPredicate, 21, 187, 49, 0, // Skip to: 18553 -/* 5822 */ MCD_OPC_CheckField, 6, 1, 1, 180, 49, 0, // Skip to: 18553 -/* 5829 */ MCD_OPC_Decode, 242, 15, 117, // Opcode: VQRDMULHslv4i32 -/* 5833 */ MCD_OPC_FilterValue, 14, 99, 0, 0, // Skip to: 5937 -/* 5838 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5841 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5878 -/* 5847 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5850 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5864 -/* 5855 */ MCD_OPC_CheckPredicate, 24, 149, 49, 0, // Skip to: 18553 -/* 5860 */ MCD_OPC_Decode, 181, 14, 99, // Opcode: VMULLp64 -/* 5864 */ MCD_OPC_FilterValue, 1, 140, 49, 0, // Skip to: 18553 -/* 5869 */ MCD_OPC_CheckPredicate, 23, 135, 49, 0, // Skip to: 18553 -/* 5874 */ MCD_OPC_Decode, 224, 15, 113, // Opcode: VQRDMLAHslv2i32 -/* 5878 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5915 -/* 5884 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5887 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5901 -/* 5892 */ MCD_OPC_CheckPredicate, 21, 112, 49, 0, // Skip to: 18553 -/* 5897 */ MCD_OPC_Decode, 201, 8, 97, // Opcode: VCGTfd -/* 5901 */ MCD_OPC_FilterValue, 1, 103, 49, 0, // Skip to: 18553 -/* 5906 */ MCD_OPC_CheckPredicate, 21, 98, 49, 0, // Skip to: 18553 -/* 5911 */ MCD_OPC_Decode, 202, 8, 98, // Opcode: VCGTfq -/* 5915 */ MCD_OPC_FilterValue, 231, 3, 88, 49, 0, // Skip to: 18553 -/* 5921 */ MCD_OPC_CheckPredicate, 23, 83, 49, 0, // Skip to: 18553 -/* 5926 */ MCD_OPC_CheckField, 6, 1, 1, 76, 49, 0, // Skip to: 18553 -/* 5933 */ MCD_OPC_Decode, 226, 15, 114, // Opcode: VQRDMLAHslv4i32 -/* 5937 */ MCD_OPC_FilterValue, 15, 67, 49, 0, // Skip to: 18553 -/* 5942 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5945 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5982 -/* 5951 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5954 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5968 -/* 5959 */ MCD_OPC_CheckPredicate, 21, 45, 49, 0, // Skip to: 18553 -/* 5964 */ MCD_OPC_Decode, 186, 13, 97, // Opcode: VMINfd -/* 5968 */ MCD_OPC_FilterValue, 1, 36, 49, 0, // Skip to: 18553 -/* 5973 */ MCD_OPC_CheckPredicate, 21, 31, 49, 0, // Skip to: 18553 -/* 5978 */ MCD_OPC_Decode, 187, 13, 98, // Opcode: VMINfq -/* 5982 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 6004 -/* 5988 */ MCD_OPC_CheckPredicate, 23, 16, 49, 0, // Skip to: 18553 -/* 5993 */ MCD_OPC_CheckField, 6, 1, 1, 9, 49, 0, // Skip to: 18553 -/* 6000 */ MCD_OPC_Decode, 232, 15, 113, // Opcode: VQRDMLSHslv2i32 -/* 6004 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 6026 -/* 6010 */ MCD_OPC_CheckPredicate, 21, 250, 48, 0, // Skip to: 18553 -/* 6015 */ MCD_OPC_CheckField, 6, 1, 0, 243, 48, 0, // Skip to: 18553 -/* 6022 */ MCD_OPC_Decode, 159, 15, 97, // Opcode: VPMINf -/* 6026 */ MCD_OPC_FilterValue, 231, 3, 233, 48, 0, // Skip to: 18553 -/* 6032 */ MCD_OPC_CheckPredicate, 23, 228, 48, 0, // Skip to: 18553 -/* 6037 */ MCD_OPC_CheckField, 6, 1, 1, 221, 48, 0, // Skip to: 18553 -/* 6044 */ MCD_OPC_Decode, 234, 15, 114, // Opcode: VQRDMLSHslv4i32 -/* 6048 */ MCD_OPC_FilterValue, 3, 212, 48, 0, // Skip to: 18553 -/* 6053 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6056 */ MCD_OPC_FilterValue, 228, 3, 183, 0, 0, // Skip to: 6245 -/* 6062 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6065 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 6101 -/* 6070 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6073 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6087 -/* 6078 */ MCD_OPC_CheckPredicate, 21, 182, 48, 0, // Skip to: 18553 -/* 6083 */ MCD_OPC_Decode, 137, 18, 101, // Opcode: VSHLsv1i64 -/* 6087 */ MCD_OPC_FilterValue, 1, 173, 48, 0, // Skip to: 18553 -/* 6092 */ MCD_OPC_CheckPredicate, 21, 168, 48, 0, // Skip to: 18553 -/* 6097 */ MCD_OPC_Decode, 139, 18, 102, // Opcode: VSHLsv2i64 -/* 6101 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 6137 -/* 6106 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6109 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6123 -/* 6114 */ MCD_OPC_CheckPredicate, 21, 146, 48, 0, // Skip to: 18553 -/* 6119 */ MCD_OPC_Decode, 165, 17, 101, // Opcode: VRSHLsv1i64 -/* 6123 */ MCD_OPC_FilterValue, 1, 137, 48, 0, // Skip to: 18553 -/* 6128 */ MCD_OPC_CheckPredicate, 21, 132, 48, 0, // Skip to: 18553 -/* 6133 */ MCD_OPC_Decode, 167, 17, 102, // Opcode: VRSHLsv2i64 -/* 6137 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6173 -/* 6142 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6145 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6159 -/* 6150 */ MCD_OPC_CheckPredicate, 21, 110, 48, 0, // Skip to: 18553 -/* 6155 */ MCD_OPC_Decode, 130, 8, 97, // Opcode: VADDv1i64 -/* 6159 */ MCD_OPC_FilterValue, 1, 101, 48, 0, // Skip to: 18553 -/* 6164 */ MCD_OPC_CheckPredicate, 21, 96, 48, 0, // Skip to: 18553 -/* 6169 */ MCD_OPC_Decode, 132, 8, 98, // Opcode: VADDv2i64 -/* 6173 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 6209 -/* 6178 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6181 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6195 -/* 6186 */ MCD_OPC_CheckPredicate, 22, 74, 48, 0, // Skip to: 18553 -/* 6191 */ MCD_OPC_Decode, 227, 20, 97, // Opcode: VSUBhd -/* 6195 */ MCD_OPC_FilterValue, 1, 65, 48, 0, // Skip to: 18553 -/* 6200 */ MCD_OPC_CheckPredicate, 22, 60, 48, 0, // Skip to: 18553 -/* 6205 */ MCD_OPC_Decode, 228, 20, 98, // Opcode: VSUBhq -/* 6209 */ MCD_OPC_FilterValue, 15, 51, 48, 0, // Skip to: 18553 -/* 6214 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6217 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6231 -/* 6222 */ MCD_OPC_CheckPredicate, 22, 38, 48, 0, // Skip to: 18553 -/* 6227 */ MCD_OPC_Decode, 188, 13, 97, // Opcode: VMINhd -/* 6231 */ MCD_OPC_FilterValue, 1, 29, 48, 0, // Skip to: 18553 -/* 6236 */ MCD_OPC_CheckPredicate, 22, 24, 48, 0, // Skip to: 18553 -/* 6241 */ MCD_OPC_Decode, 189, 13, 98, // Opcode: VMINhq -/* 6245 */ MCD_OPC_FilterValue, 229, 3, 119, 0, 0, // Skip to: 6370 -/* 6251 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6254 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6308 -/* 6259 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 6262 */ MCD_OPC_FilterValue, 0, 254, 47, 0, // Skip to: 18553 -/* 6267 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6283 -/* 6272 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, 0, // Skip to: 6283 -/* 6279 */ MCD_OPC_Decode, 143, 10, 119, // Opcode: VEXTd32 -/* 6283 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6299 -/* 6288 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, 0, // Skip to: 6299 -/* 6295 */ MCD_OPC_Decode, 142, 10, 120, // Opcode: VEXTd16 -/* 6299 */ MCD_OPC_CheckPredicate, 21, 217, 47, 0, // Skip to: 18553 -/* 6304 */ MCD_OPC_Decode, 144, 10, 121, // Opcode: VEXTd8 -/* 6308 */ MCD_OPC_FilterValue, 1, 208, 47, 0, // Skip to: 18553 -/* 6313 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6329 -/* 6318 */ MCD_OPC_CheckField, 8, 3, 0, 4, 0, 0, // Skip to: 6329 -/* 6325 */ MCD_OPC_Decode, 147, 10, 122, // Opcode: VEXTq64 -/* 6329 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6345 -/* 6334 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, 0, // Skip to: 6345 -/* 6341 */ MCD_OPC_Decode, 146, 10, 123, // Opcode: VEXTq32 -/* 6345 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6361 -/* 6350 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, 0, // Skip to: 6361 -/* 6357 */ MCD_OPC_Decode, 145, 10, 124, // Opcode: VEXTq16 -/* 6361 */ MCD_OPC_CheckPredicate, 21, 155, 47, 0, // Skip to: 18553 -/* 6366 */ MCD_OPC_Decode, 148, 10, 125, // Opcode: VEXTq8 -/* 6370 */ MCD_OPC_FilterValue, 230, 3, 204, 0, 0, // Skip to: 6580 -/* 6376 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6379 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 6415 -/* 6384 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6387 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6401 -/* 6392 */ MCD_OPC_CheckPredicate, 21, 124, 47, 0, // Skip to: 18553 -/* 6397 */ MCD_OPC_Decode, 145, 18, 101, // Opcode: VSHLuv1i64 -/* 6401 */ MCD_OPC_FilterValue, 1, 115, 47, 0, // Skip to: 18553 -/* 6406 */ MCD_OPC_CheckPredicate, 21, 110, 47, 0, // Skip to: 18553 -/* 6411 */ MCD_OPC_Decode, 147, 18, 102, // Opcode: VSHLuv2i64 -/* 6415 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 6451 -/* 6420 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6423 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6437 -/* 6428 */ MCD_OPC_CheckPredicate, 21, 88, 47, 0, // Skip to: 18553 -/* 6433 */ MCD_OPC_Decode, 173, 17, 101, // Opcode: VRSHLuv1i64 -/* 6437 */ MCD_OPC_FilterValue, 1, 79, 47, 0, // Skip to: 18553 -/* 6442 */ MCD_OPC_CheckPredicate, 21, 74, 47, 0, // Skip to: 18553 -/* 6447 */ MCD_OPC_Decode, 175, 17, 102, // Opcode: VRSHLuv2i64 -/* 6451 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6487 -/* 6456 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6459 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6473 -/* 6464 */ MCD_OPC_CheckPredicate, 21, 52, 47, 0, // Skip to: 18553 -/* 6469 */ MCD_OPC_Decode, 230, 20, 97, // Opcode: VSUBv1i64 -/* 6473 */ MCD_OPC_FilterValue, 1, 43, 47, 0, // Skip to: 18553 -/* 6478 */ MCD_OPC_CheckPredicate, 21, 38, 47, 0, // Skip to: 18553 -/* 6483 */ MCD_OPC_Decode, 232, 20, 98, // Opcode: VSUBv2i64 -/* 6487 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 6523 -/* 6492 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6495 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6509 -/* 6500 */ MCD_OPC_CheckPredicate, 22, 16, 47, 0, // Skip to: 18553 -/* 6505 */ MCD_OPC_Decode, 200, 7, 97, // Opcode: VABDhd -/* 6509 */ MCD_OPC_FilterValue, 1, 7, 47, 0, // Skip to: 18553 -/* 6514 */ MCD_OPC_CheckPredicate, 22, 2, 47, 0, // Skip to: 18553 -/* 6519 */ MCD_OPC_Decode, 201, 7, 98, // Opcode: VABDhq -/* 6523 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 6559 -/* 6528 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6531 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6545 -/* 6536 */ MCD_OPC_CheckPredicate, 22, 236, 46, 0, // Skip to: 18553 -/* 6541 */ MCD_OPC_Decode, 203, 8, 97, // Opcode: VCGThd -/* 6545 */ MCD_OPC_FilterValue, 1, 227, 46, 0, // Skip to: 18553 -/* 6550 */ MCD_OPC_CheckPredicate, 22, 222, 46, 0, // Skip to: 18553 -/* 6555 */ MCD_OPC_Decode, 204, 8, 98, // Opcode: VCGThq -/* 6559 */ MCD_OPC_FilterValue, 15, 213, 46, 0, // Skip to: 18553 -/* 6564 */ MCD_OPC_CheckPredicate, 22, 208, 46, 0, // Skip to: 18553 -/* 6569 */ MCD_OPC_CheckField, 6, 1, 0, 201, 46, 0, // Skip to: 18553 -/* 6576 */ MCD_OPC_Decode, 160, 15, 97, // Opcode: VPMINh -/* 6580 */ MCD_OPC_FilterValue, 231, 3, 191, 46, 0, // Skip to: 18553 -/* 6586 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6589 */ MCD_OPC_FilterValue, 0, 247, 1, 0, // Skip to: 7097 -/* 6594 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6597 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 6661 -/* 6602 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 6605 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6619 -/* 6610 */ MCD_OPC_CheckPredicate, 21, 162, 46, 0, // Skip to: 18553 -/* 6615 */ MCD_OPC_Decode, 231, 16, 126, // Opcode: VREV64d8 -/* 6619 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6633 -/* 6624 */ MCD_OPC_CheckPredicate, 21, 148, 46, 0, // Skip to: 18553 -/* 6629 */ MCD_OPC_Decode, 234, 16, 127, // Opcode: VREV64q8 -/* 6633 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6647 -/* 6638 */ MCD_OPC_CheckPredicate, 21, 134, 46, 0, // Skip to: 18553 -/* 6643 */ MCD_OPC_Decode, 226, 16, 126, // Opcode: VREV32d8 -/* 6647 */ MCD_OPC_FilterValue, 3, 125, 46, 0, // Skip to: 18553 -/* 6652 */ MCD_OPC_CheckPredicate, 21, 120, 46, 0, // Skip to: 18553 -/* 6657 */ MCD_OPC_Decode, 228, 16, 127, // Opcode: VREV32q8 -/* 6661 */ MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 6725 -/* 6666 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 6669 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6683 -/* 6674 */ MCD_OPC_CheckPredicate, 21, 98, 46, 0, // Skip to: 18553 -/* 6679 */ MCD_OPC_Decode, 226, 8, 126, // Opcode: VCGTzv8i8 -/* 6683 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6697 -/* 6688 */ MCD_OPC_CheckPredicate, 21, 84, 46, 0, // Skip to: 18553 -/* 6693 */ MCD_OPC_Decode, 217, 8, 127, // Opcode: VCGTzv16i8 -/* 6697 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6711 -/* 6702 */ MCD_OPC_CheckPredicate, 21, 70, 46, 0, // Skip to: 18553 -/* 6707 */ MCD_OPC_Decode, 200, 8, 126, // Opcode: VCGEzv8i8 -/* 6711 */ MCD_OPC_FilterValue, 3, 61, 46, 0, // Skip to: 18553 -/* 6716 */ MCD_OPC_CheckPredicate, 21, 56, 46, 0, // Skip to: 18553 -/* 6721 */ MCD_OPC_Decode, 191, 8, 127, // Opcode: VCGEzv16i8 -/* 6725 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 6793 -/* 6730 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 6733 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6748 -/* 6738 */ MCD_OPC_CheckPredicate, 21, 34, 46, 0, // Skip to: 18553 -/* 6743 */ MCD_OPC_Decode, 237, 20, 128, 1, // Opcode: VSWPd -/* 6748 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6763 -/* 6753 */ MCD_OPC_CheckPredicate, 21, 19, 46, 0, // Skip to: 18553 -/* 6758 */ MCD_OPC_Decode, 238, 20, 129, 1, // Opcode: VSWPq -/* 6763 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6778 -/* 6768 */ MCD_OPC_CheckPredicate, 21, 4, 46, 0, // Skip to: 18553 -/* 6773 */ MCD_OPC_Decode, 149, 21, 128, 1, // Opcode: VTRNd8 -/* 6778 */ MCD_OPC_FilterValue, 3, 250, 45, 0, // Skip to: 18553 -/* 6783 */ MCD_OPC_CheckPredicate, 21, 245, 45, 0, // Skip to: 18553 -/* 6788 */ MCD_OPC_Decode, 152, 21, 129, 1, // Opcode: VTRNq8 -/* 6793 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 6857 -/* 6798 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 6801 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6815 -/* 6806 */ MCD_OPC_CheckPredicate, 21, 222, 45, 0, // Skip to: 18553 -/* 6811 */ MCD_OPC_Decode, 229, 16, 126, // Opcode: VREV64d16 -/* 6815 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6829 -/* 6820 */ MCD_OPC_CheckPredicate, 21, 208, 45, 0, // Skip to: 18553 -/* 6825 */ MCD_OPC_Decode, 232, 16, 127, // Opcode: VREV64q16 -/* 6829 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6843 -/* 6834 */ MCD_OPC_CheckPredicate, 21, 194, 45, 0, // Skip to: 18553 -/* 6839 */ MCD_OPC_Decode, 225, 16, 126, // Opcode: VREV32d16 -/* 6843 */ MCD_OPC_FilterValue, 3, 185, 45, 0, // Skip to: 18553 -/* 6848 */ MCD_OPC_CheckPredicate, 21, 180, 45, 0, // Skip to: 18553 -/* 6853 */ MCD_OPC_Decode, 227, 16, 127, // Opcode: VREV32q16 -/* 6857 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 6921 -/* 6862 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 6865 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6879 -/* 6870 */ MCD_OPC_CheckPredicate, 21, 158, 45, 0, // Skip to: 18553 -/* 6875 */ MCD_OPC_Decode, 222, 8, 126, // Opcode: VCGTzv4i16 -/* 6879 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6893 -/* 6884 */ MCD_OPC_CheckPredicate, 21, 144, 45, 0, // Skip to: 18553 -/* 6889 */ MCD_OPC_Decode, 225, 8, 127, // Opcode: VCGTzv8i16 -/* 6893 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6907 -/* 6898 */ MCD_OPC_CheckPredicate, 21, 130, 45, 0, // Skip to: 18553 -/* 6903 */ MCD_OPC_Decode, 196, 8, 126, // Opcode: VCGEzv4i16 -/* 6907 */ MCD_OPC_FilterValue, 3, 121, 45, 0, // Skip to: 18553 -/* 6912 */ MCD_OPC_CheckPredicate, 21, 116, 45, 0, // Skip to: 18553 -/* 6917 */ MCD_OPC_Decode, 199, 8, 127, // Opcode: VCGEzv8i16 -/* 6921 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 6959 -/* 6926 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 6929 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6944 -/* 6934 */ MCD_OPC_CheckPredicate, 21, 94, 45, 0, // Skip to: 18553 -/* 6939 */ MCD_OPC_Decode, 147, 21, 128, 1, // Opcode: VTRNd16 -/* 6944 */ MCD_OPC_FilterValue, 3, 84, 45, 0, // Skip to: 18553 -/* 6949 */ MCD_OPC_CheckPredicate, 21, 79, 45, 0, // Skip to: 18553 -/* 6954 */ MCD_OPC_Decode, 150, 21, 129, 1, // Opcode: VTRNq16 -/* 6959 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6995 -/* 6964 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 6967 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6981 -/* 6972 */ MCD_OPC_CheckPredicate, 21, 56, 45, 0, // Skip to: 18553 -/* 6977 */ MCD_OPC_Decode, 230, 16, 126, // Opcode: VREV64d32 -/* 6981 */ MCD_OPC_FilterValue, 1, 47, 45, 0, // Skip to: 18553 -/* 6986 */ MCD_OPC_CheckPredicate, 21, 42, 45, 0, // Skip to: 18553 -/* 6991 */ MCD_OPC_Decode, 233, 16, 127, // Opcode: VREV64q32 -/* 6995 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 7059 -/* 7000 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7003 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7017 -/* 7008 */ MCD_OPC_CheckPredicate, 21, 20, 45, 0, // Skip to: 18553 -/* 7013 */ MCD_OPC_Decode, 219, 8, 126, // Opcode: VCGTzv2i32 -/* 7017 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7031 -/* 7022 */ MCD_OPC_CheckPredicate, 21, 6, 45, 0, // Skip to: 18553 -/* 7027 */ MCD_OPC_Decode, 223, 8, 127, // Opcode: VCGTzv4i32 -/* 7031 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7045 -/* 7036 */ MCD_OPC_CheckPredicate, 21, 248, 44, 0, // Skip to: 18553 -/* 7041 */ MCD_OPC_Decode, 193, 8, 126, // Opcode: VCGEzv2i32 -/* 7045 */ MCD_OPC_FilterValue, 3, 239, 44, 0, // Skip to: 18553 -/* 7050 */ MCD_OPC_CheckPredicate, 21, 234, 44, 0, // Skip to: 18553 -/* 7055 */ MCD_OPC_Decode, 197, 8, 127, // Opcode: VCGEzv4i32 -/* 7059 */ MCD_OPC_FilterValue, 10, 225, 44, 0, // Skip to: 18553 -/* 7064 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7067 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7082 -/* 7072 */ MCD_OPC_CheckPredicate, 21, 212, 44, 0, // Skip to: 18553 -/* 7077 */ MCD_OPC_Decode, 148, 21, 128, 1, // Opcode: VTRNd32 -/* 7082 */ MCD_OPC_FilterValue, 3, 202, 44, 0, // Skip to: 18553 -/* 7087 */ MCD_OPC_CheckPredicate, 21, 197, 44, 0, // Skip to: 18553 -/* 7092 */ MCD_OPC_Decode, 151, 21, 129, 1, // Opcode: VTRNq32 -/* 7097 */ MCD_OPC_FilterValue, 1, 149, 1, 0, // Skip to: 7507 -/* 7102 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7105 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7141 -/* 7110 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7113 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7127 -/* 7118 */ MCD_OPC_CheckPredicate, 21, 166, 44, 0, // Skip to: 18553 -/* 7123 */ MCD_OPC_Decode, 223, 16, 126, // Opcode: VREV16d8 -/* 7127 */ MCD_OPC_FilterValue, 1, 157, 44, 0, // Skip to: 18553 -/* 7132 */ MCD_OPC_CheckPredicate, 21, 152, 44, 0, // Skip to: 18553 -/* 7137 */ MCD_OPC_Decode, 224, 16, 127, // Opcode: VREV16q8 -/* 7141 */ MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 7205 -/* 7146 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7149 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7163 -/* 7154 */ MCD_OPC_CheckPredicate, 21, 130, 44, 0, // Skip to: 18553 -/* 7159 */ MCD_OPC_Decode, 174, 8, 126, // Opcode: VCEQzv8i8 -/* 7163 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7177 -/* 7168 */ MCD_OPC_CheckPredicate, 21, 116, 44, 0, // Skip to: 18553 -/* 7173 */ MCD_OPC_Decode, 165, 8, 127, // Opcode: VCEQzv16i8 -/* 7177 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7191 -/* 7182 */ MCD_OPC_CheckPredicate, 21, 102, 44, 0, // Skip to: 18553 -/* 7187 */ MCD_OPC_Decode, 236, 8, 126, // Opcode: VCLEzv8i8 -/* 7191 */ MCD_OPC_FilterValue, 3, 93, 44, 0, // Skip to: 18553 -/* 7196 */ MCD_OPC_CheckPredicate, 21, 88, 44, 0, // Skip to: 18553 -/* 7201 */ MCD_OPC_Decode, 227, 8, 127, // Opcode: VCLEzv16i8 -/* 7205 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7273 -/* 7210 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7213 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7228 -/* 7218 */ MCD_OPC_CheckPredicate, 21, 66, 44, 0, // Skip to: 18553 -/* 7223 */ MCD_OPC_Decode, 173, 21, 128, 1, // Opcode: VUZPd8 -/* 7228 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7243 -/* 7233 */ MCD_OPC_CheckPredicate, 21, 51, 44, 0, // Skip to: 18553 -/* 7238 */ MCD_OPC_Decode, 176, 21, 129, 1, // Opcode: VUZPq8 -/* 7243 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7258 -/* 7248 */ MCD_OPC_CheckPredicate, 21, 36, 44, 0, // Skip to: 18553 -/* 7253 */ MCD_OPC_Decode, 178, 21, 128, 1, // Opcode: VZIPd8 -/* 7258 */ MCD_OPC_FilterValue, 3, 26, 44, 0, // Skip to: 18553 -/* 7263 */ MCD_OPC_CheckPredicate, 21, 21, 44, 0, // Skip to: 18553 -/* 7268 */ MCD_OPC_Decode, 181, 21, 129, 1, // Opcode: VZIPq8 -/* 7273 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 7337 -/* 7278 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7281 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7295 -/* 7286 */ MCD_OPC_CheckPredicate, 21, 254, 43, 0, // Skip to: 18553 -/* 7291 */ MCD_OPC_Decode, 170, 8, 126, // Opcode: VCEQzv4i16 -/* 7295 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7309 -/* 7300 */ MCD_OPC_CheckPredicate, 21, 240, 43, 0, // Skip to: 18553 -/* 7305 */ MCD_OPC_Decode, 173, 8, 127, // Opcode: VCEQzv8i16 -/* 7309 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7323 -/* 7314 */ MCD_OPC_CheckPredicate, 21, 226, 43, 0, // Skip to: 18553 -/* 7319 */ MCD_OPC_Decode, 232, 8, 126, // Opcode: VCLEzv4i16 -/* 7323 */ MCD_OPC_FilterValue, 3, 217, 43, 0, // Skip to: 18553 -/* 7328 */ MCD_OPC_CheckPredicate, 21, 212, 43, 0, // Skip to: 18553 -/* 7333 */ MCD_OPC_Decode, 235, 8, 127, // Opcode: VCLEzv8i16 -/* 7337 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 7405 -/* 7342 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7345 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7360 -/* 7350 */ MCD_OPC_CheckPredicate, 21, 190, 43, 0, // Skip to: 18553 -/* 7355 */ MCD_OPC_Decode, 172, 21, 128, 1, // Opcode: VUZPd16 -/* 7360 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7375 -/* 7365 */ MCD_OPC_CheckPredicate, 21, 175, 43, 0, // Skip to: 18553 -/* 7370 */ MCD_OPC_Decode, 174, 21, 129, 1, // Opcode: VUZPq16 -/* 7375 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7390 -/* 7380 */ MCD_OPC_CheckPredicate, 21, 160, 43, 0, // Skip to: 18553 -/* 7385 */ MCD_OPC_Decode, 177, 21, 128, 1, // Opcode: VZIPd16 -/* 7390 */ MCD_OPC_FilterValue, 3, 150, 43, 0, // Skip to: 18553 -/* 7395 */ MCD_OPC_CheckPredicate, 21, 145, 43, 0, // Skip to: 18553 -/* 7400 */ MCD_OPC_Decode, 179, 21, 129, 1, // Opcode: VZIPq16 -/* 7405 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 7469 -/* 7410 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7413 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7427 -/* 7418 */ MCD_OPC_CheckPredicate, 21, 122, 43, 0, // Skip to: 18553 -/* 7423 */ MCD_OPC_Decode, 167, 8, 126, // Opcode: VCEQzv2i32 -/* 7427 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7441 -/* 7432 */ MCD_OPC_CheckPredicate, 21, 108, 43, 0, // Skip to: 18553 -/* 7437 */ MCD_OPC_Decode, 171, 8, 127, // Opcode: VCEQzv4i32 -/* 7441 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7455 -/* 7446 */ MCD_OPC_CheckPredicate, 21, 94, 43, 0, // Skip to: 18553 -/* 7451 */ MCD_OPC_Decode, 229, 8, 126, // Opcode: VCLEzv2i32 -/* 7455 */ MCD_OPC_FilterValue, 3, 85, 43, 0, // Skip to: 18553 -/* 7460 */ MCD_OPC_CheckPredicate, 21, 80, 43, 0, // Skip to: 18553 -/* 7465 */ MCD_OPC_Decode, 233, 8, 127, // Opcode: VCLEzv4i32 -/* 7469 */ MCD_OPC_FilterValue, 10, 71, 43, 0, // Skip to: 18553 -/* 7474 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7477 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7492 -/* 7482 */ MCD_OPC_CheckPredicate, 21, 58, 43, 0, // Skip to: 18553 -/* 7487 */ MCD_OPC_Decode, 175, 21, 129, 1, // Opcode: VUZPq32 -/* 7492 */ MCD_OPC_FilterValue, 3, 48, 43, 0, // Skip to: 18553 -/* 7497 */ MCD_OPC_CheckPredicate, 21, 43, 43, 0, // Skip to: 18553 -/* 7502 */ MCD_OPC_Decode, 180, 21, 129, 1, // Opcode: VZIPq32 -/* 7507 */ MCD_OPC_FilterValue, 2, 251, 1, 0, // Skip to: 8019 -/* 7512 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7515 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 7579 -/* 7520 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7523 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7537 -/* 7528 */ MCD_OPC_CheckPredicate, 21, 12, 43, 0, // Skip to: 18553 -/* 7533 */ MCD_OPC_Decode, 139, 15, 126, // Opcode: VPADDLsv8i8 -/* 7537 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7551 -/* 7542 */ MCD_OPC_CheckPredicate, 21, 254, 42, 0, // Skip to: 18553 -/* 7547 */ MCD_OPC_Decode, 134, 15, 127, // Opcode: VPADDLsv16i8 -/* 7551 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7565 -/* 7556 */ MCD_OPC_CheckPredicate, 21, 240, 42, 0, // Skip to: 18553 -/* 7561 */ MCD_OPC_Decode, 145, 15, 126, // Opcode: VPADDLuv8i8 -/* 7565 */ MCD_OPC_FilterValue, 3, 231, 42, 0, // Skip to: 18553 -/* 7570 */ MCD_OPC_CheckPredicate, 21, 226, 42, 0, // Skip to: 18553 -/* 7575 */ MCD_OPC_Decode, 140, 15, 127, // Opcode: VPADDLuv16i8 -/* 7579 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 7615 -/* 7584 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7587 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7601 -/* 7592 */ MCD_OPC_CheckPredicate, 21, 204, 42, 0, // Skip to: 18553 -/* 7597 */ MCD_OPC_Decode, 252, 8, 126, // Opcode: VCLTzv8i8 -/* 7601 */ MCD_OPC_FilterValue, 1, 195, 42, 0, // Skip to: 18553 -/* 7606 */ MCD_OPC_CheckPredicate, 21, 190, 42, 0, // Skip to: 18553 -/* 7611 */ MCD_OPC_Decode, 243, 8, 127, // Opcode: VCLTzv16i8 -/* 7615 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7683 -/* 7620 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7623 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7638 -/* 7628 */ MCD_OPC_CheckPredicate, 21, 168, 42, 0, // Skip to: 18553 -/* 7633 */ MCD_OPC_Decode, 148, 14, 130, 1, // Opcode: VMOVNv8i8 -/* 7638 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7653 -/* 7643 */ MCD_OPC_CheckPredicate, 21, 153, 42, 0, // Skip to: 18553 -/* 7648 */ MCD_OPC_Decode, 211, 15, 130, 1, // Opcode: VQMOVNsuv8i8 -/* 7653 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7668 -/* 7658 */ MCD_OPC_CheckPredicate, 21, 138, 42, 0, // Skip to: 18553 -/* 7663 */ MCD_OPC_Decode, 214, 15, 130, 1, // Opcode: VQMOVNsv8i8 -/* 7668 */ MCD_OPC_FilterValue, 3, 128, 42, 0, // Skip to: 18553 -/* 7673 */ MCD_OPC_CheckPredicate, 21, 123, 42, 0, // Skip to: 18553 -/* 7678 */ MCD_OPC_Decode, 217, 15, 130, 1, // Opcode: VQMOVNuv8i8 -/* 7683 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 7747 -/* 7688 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7691 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7705 -/* 7696 */ MCD_OPC_CheckPredicate, 21, 100, 42, 0, // Skip to: 18553 -/* 7701 */ MCD_OPC_Decode, 136, 15, 126, // Opcode: VPADDLsv4i16 -/* 7705 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7719 -/* 7710 */ MCD_OPC_CheckPredicate, 21, 86, 42, 0, // Skip to: 18553 -/* 7715 */ MCD_OPC_Decode, 138, 15, 127, // Opcode: VPADDLsv8i16 -/* 7719 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7733 -/* 7724 */ MCD_OPC_CheckPredicate, 21, 72, 42, 0, // Skip to: 18553 -/* 7729 */ MCD_OPC_Decode, 142, 15, 126, // Opcode: VPADDLuv4i16 -/* 7733 */ MCD_OPC_FilterValue, 3, 63, 42, 0, // Skip to: 18553 -/* 7738 */ MCD_OPC_CheckPredicate, 21, 58, 42, 0, // Skip to: 18553 -/* 7743 */ MCD_OPC_Decode, 144, 15, 127, // Opcode: VPADDLuv8i16 -/* 7747 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 7783 -/* 7752 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7755 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7769 -/* 7760 */ MCD_OPC_CheckPredicate, 21, 36, 42, 0, // Skip to: 18553 -/* 7765 */ MCD_OPC_Decode, 248, 8, 126, // Opcode: VCLTzv4i16 -/* 7769 */ MCD_OPC_FilterValue, 1, 27, 42, 0, // Skip to: 18553 -/* 7774 */ MCD_OPC_CheckPredicate, 21, 22, 42, 0, // Skip to: 18553 -/* 7779 */ MCD_OPC_Decode, 251, 8, 127, // Opcode: VCLTzv8i16 -/* 7783 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 7851 -/* 7788 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7791 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7806 -/* 7796 */ MCD_OPC_CheckPredicate, 21, 0, 42, 0, // Skip to: 18553 -/* 7801 */ MCD_OPC_Decode, 147, 14, 130, 1, // Opcode: VMOVNv4i16 -/* 7806 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7821 -/* 7811 */ MCD_OPC_CheckPredicate, 21, 241, 41, 0, // Skip to: 18553 -/* 7816 */ MCD_OPC_Decode, 210, 15, 130, 1, // Opcode: VQMOVNsuv4i16 -/* 7821 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7836 -/* 7826 */ MCD_OPC_CheckPredicate, 21, 226, 41, 0, // Skip to: 18553 -/* 7831 */ MCD_OPC_Decode, 213, 15, 130, 1, // Opcode: VQMOVNsv4i16 -/* 7836 */ MCD_OPC_FilterValue, 3, 216, 41, 0, // Skip to: 18553 -/* 7841 */ MCD_OPC_CheckPredicate, 21, 211, 41, 0, // Skip to: 18553 -/* 7846 */ MCD_OPC_Decode, 216, 15, 130, 1, // Opcode: VQMOVNuv4i16 -/* 7851 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 7915 -/* 7856 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7859 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7873 -/* 7864 */ MCD_OPC_CheckPredicate, 21, 188, 41, 0, // Skip to: 18553 -/* 7869 */ MCD_OPC_Decode, 135, 15, 126, // Opcode: VPADDLsv2i32 -/* 7873 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7887 -/* 7878 */ MCD_OPC_CheckPredicate, 21, 174, 41, 0, // Skip to: 18553 -/* 7883 */ MCD_OPC_Decode, 137, 15, 127, // Opcode: VPADDLsv4i32 -/* 7887 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7901 -/* 7892 */ MCD_OPC_CheckPredicate, 21, 160, 41, 0, // Skip to: 18553 -/* 7897 */ MCD_OPC_Decode, 141, 15, 126, // Opcode: VPADDLuv2i32 -/* 7901 */ MCD_OPC_FilterValue, 3, 151, 41, 0, // Skip to: 18553 -/* 7906 */ MCD_OPC_CheckPredicate, 21, 146, 41, 0, // Skip to: 18553 -/* 7911 */ MCD_OPC_Decode, 143, 15, 127, // Opcode: VPADDLuv4i32 -/* 7915 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 7951 -/* 7920 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7923 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7937 -/* 7928 */ MCD_OPC_CheckPredicate, 21, 124, 41, 0, // Skip to: 18553 -/* 7933 */ MCD_OPC_Decode, 245, 8, 126, // Opcode: VCLTzv2i32 -/* 7937 */ MCD_OPC_FilterValue, 1, 115, 41, 0, // Skip to: 18553 -/* 7942 */ MCD_OPC_CheckPredicate, 21, 110, 41, 0, // Skip to: 18553 -/* 7947 */ MCD_OPC_Decode, 249, 8, 127, // Opcode: VCLTzv4i32 -/* 7951 */ MCD_OPC_FilterValue, 10, 101, 41, 0, // Skip to: 18553 -/* 7956 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 7959 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7974 -/* 7964 */ MCD_OPC_CheckPredicate, 21, 88, 41, 0, // Skip to: 18553 -/* 7969 */ MCD_OPC_Decode, 146, 14, 130, 1, // Opcode: VMOVNv2i32 -/* 7974 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7989 -/* 7979 */ MCD_OPC_CheckPredicate, 21, 73, 41, 0, // Skip to: 18553 -/* 7984 */ MCD_OPC_Decode, 209, 15, 130, 1, // Opcode: VQMOVNsuv2i32 -/* 7989 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8004 -/* 7994 */ MCD_OPC_CheckPredicate, 21, 58, 41, 0, // Skip to: 18553 -/* 7999 */ MCD_OPC_Decode, 212, 15, 130, 1, // Opcode: VQMOVNsv2i32 -/* 8004 */ MCD_OPC_FilterValue, 3, 48, 41, 0, // Skip to: 18553 -/* 8009 */ MCD_OPC_CheckPredicate, 21, 43, 41, 0, // Skip to: 18553 -/* 8014 */ MCD_OPC_Decode, 215, 15, 130, 1, // Opcode: VQMOVNuv2i32 -/* 8019 */ MCD_OPC_FilterValue, 3, 5, 1, 0, // Skip to: 8285 -/* 8024 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 8027 */ MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 8091 -/* 8032 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8035 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8049 -/* 8040 */ MCD_OPC_CheckPredicate, 21, 12, 41, 0, // Skip to: 18553 -/* 8045 */ MCD_OPC_Decode, 226, 7, 126, // Opcode: VABSv8i8 -/* 8049 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8063 -/* 8054 */ MCD_OPC_CheckPredicate, 21, 254, 40, 0, // Skip to: 18553 -/* 8059 */ MCD_OPC_Decode, 221, 7, 127, // Opcode: VABSv16i8 -/* 8063 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8077 -/* 8068 */ MCD_OPC_CheckPredicate, 21, 240, 40, 0, // Skip to: 18553 -/* 8073 */ MCD_OPC_Decode, 231, 14, 126, // Opcode: VNEGs8d -/* 8077 */ MCD_OPC_FilterValue, 3, 231, 40, 0, // Skip to: 18553 -/* 8082 */ MCD_OPC_CheckPredicate, 21, 226, 40, 0, // Skip to: 18553 -/* 8087 */ MCD_OPC_Decode, 232, 14, 127, // Opcode: VNEGs8q -/* 8091 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 8113 -/* 8096 */ MCD_OPC_CheckPredicate, 21, 212, 40, 0, // Skip to: 18553 -/* 8101 */ MCD_OPC_CheckField, 6, 2, 0, 205, 40, 0, // Skip to: 18553 -/* 8108 */ MCD_OPC_Decode, 249, 17, 131, 1, // Opcode: VSHLLi8 -/* 8113 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8177 -/* 8118 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8121 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8135 -/* 8126 */ MCD_OPC_CheckPredicate, 21, 182, 40, 0, // Skip to: 18553 -/* 8131 */ MCD_OPC_Decode, 223, 7, 126, // Opcode: VABSv4i16 -/* 8135 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8149 -/* 8140 */ MCD_OPC_CheckPredicate, 21, 168, 40, 0, // Skip to: 18553 -/* 8145 */ MCD_OPC_Decode, 225, 7, 127, // Opcode: VABSv8i16 -/* 8149 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8163 -/* 8154 */ MCD_OPC_CheckPredicate, 21, 154, 40, 0, // Skip to: 18553 -/* 8159 */ MCD_OPC_Decode, 227, 14, 126, // Opcode: VNEGs16d -/* 8163 */ MCD_OPC_FilterValue, 3, 145, 40, 0, // Skip to: 18553 -/* 8168 */ MCD_OPC_CheckPredicate, 21, 140, 40, 0, // Skip to: 18553 -/* 8173 */ MCD_OPC_Decode, 228, 14, 127, // Opcode: VNEGs16q -/* 8177 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 8199 -/* 8182 */ MCD_OPC_CheckPredicate, 21, 126, 40, 0, // Skip to: 18553 -/* 8187 */ MCD_OPC_CheckField, 6, 2, 0, 119, 40, 0, // Skip to: 18553 -/* 8194 */ MCD_OPC_Decode, 247, 17, 131, 1, // Opcode: VSHLLi16 -/* 8199 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8263 -/* 8204 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8207 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8221 -/* 8212 */ MCD_OPC_CheckPredicate, 21, 96, 40, 0, // Skip to: 18553 -/* 8217 */ MCD_OPC_Decode, 222, 7, 126, // Opcode: VABSv2i32 -/* 8221 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8235 -/* 8226 */ MCD_OPC_CheckPredicate, 21, 82, 40, 0, // Skip to: 18553 -/* 8231 */ MCD_OPC_Decode, 224, 7, 127, // Opcode: VABSv4i32 -/* 8235 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8249 -/* 8240 */ MCD_OPC_CheckPredicate, 21, 68, 40, 0, // Skip to: 18553 -/* 8245 */ MCD_OPC_Decode, 229, 14, 126, // Opcode: VNEGs32d -/* 8249 */ MCD_OPC_FilterValue, 3, 59, 40, 0, // Skip to: 18553 -/* 8254 */ MCD_OPC_CheckPredicate, 21, 54, 40, 0, // Skip to: 18553 -/* 8259 */ MCD_OPC_Decode, 230, 14, 127, // Opcode: VNEGs32q -/* 8263 */ MCD_OPC_FilterValue, 10, 45, 40, 0, // Skip to: 18553 -/* 8268 */ MCD_OPC_CheckPredicate, 21, 40, 40, 0, // Skip to: 18553 -/* 8273 */ MCD_OPC_CheckField, 6, 2, 0, 33, 40, 0, // Skip to: 18553 -/* 8280 */ MCD_OPC_Decode, 248, 17, 131, 1, // Opcode: VSHLLi32 -/* 8285 */ MCD_OPC_FilterValue, 4, 131, 1, 0, // Skip to: 8677 -/* 8290 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 8293 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 8357 -/* 8298 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8301 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8315 -/* 8306 */ MCD_OPC_CheckPredicate, 21, 2, 40, 0, // Skip to: 18553 -/* 8311 */ MCD_OPC_Decode, 242, 8, 126, // Opcode: VCLSv8i8 -/* 8315 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8329 -/* 8320 */ MCD_OPC_CheckPredicate, 21, 244, 39, 0, // Skip to: 18553 -/* 8325 */ MCD_OPC_Decode, 237, 8, 127, // Opcode: VCLSv16i8 -/* 8329 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8343 -/* 8334 */ MCD_OPC_CheckPredicate, 21, 230, 39, 0, // Skip to: 18553 -/* 8339 */ MCD_OPC_Decode, 130, 9, 126, // Opcode: VCLZv8i8 -/* 8343 */ MCD_OPC_FilterValue, 3, 221, 39, 0, // Skip to: 18553 -/* 8348 */ MCD_OPC_CheckPredicate, 21, 216, 39, 0, // Skip to: 18553 -/* 8353 */ MCD_OPC_Decode, 253, 8, 127, // Opcode: VCLZv16i8 -/* 8357 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 8421 -/* 8362 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8365 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8379 -/* 8370 */ MCD_OPC_CheckPredicate, 21, 194, 39, 0, // Skip to: 18553 -/* 8375 */ MCD_OPC_Decode, 239, 8, 126, // Opcode: VCLSv4i16 -/* 8379 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8393 -/* 8384 */ MCD_OPC_CheckPredicate, 21, 180, 39, 0, // Skip to: 18553 -/* 8389 */ MCD_OPC_Decode, 241, 8, 127, // Opcode: VCLSv8i16 -/* 8393 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8407 -/* 8398 */ MCD_OPC_CheckPredicate, 21, 166, 39, 0, // Skip to: 18553 -/* 8403 */ MCD_OPC_Decode, 255, 8, 126, // Opcode: VCLZv4i16 -/* 8407 */ MCD_OPC_FilterValue, 3, 157, 39, 0, // Skip to: 18553 -/* 8412 */ MCD_OPC_CheckPredicate, 21, 152, 39, 0, // Skip to: 18553 -/* 8417 */ MCD_OPC_Decode, 129, 9, 127, // Opcode: VCLZv8i16 -/* 8421 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8485 -/* 8426 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8429 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8443 -/* 8434 */ MCD_OPC_CheckPredicate, 22, 130, 39, 0, // Skip to: 18553 -/* 8439 */ MCD_OPC_Decode, 220, 8, 126, // Opcode: VCGTzv4f16 -/* 8443 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8457 -/* 8448 */ MCD_OPC_CheckPredicate, 22, 116, 39, 0, // Skip to: 18553 -/* 8453 */ MCD_OPC_Decode, 224, 8, 127, // Opcode: VCGTzv8f16 -/* 8457 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8471 -/* 8462 */ MCD_OPC_CheckPredicate, 22, 102, 39, 0, // Skip to: 18553 -/* 8467 */ MCD_OPC_Decode, 194, 8, 126, // Opcode: VCGEzv4f16 -/* 8471 */ MCD_OPC_FilterValue, 3, 93, 39, 0, // Skip to: 18553 -/* 8476 */ MCD_OPC_CheckPredicate, 22, 88, 39, 0, // Skip to: 18553 -/* 8481 */ MCD_OPC_Decode, 198, 8, 127, // Opcode: VCGEzv8f16 -/* 8485 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 8549 -/* 8490 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8493 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8507 -/* 8498 */ MCD_OPC_CheckPredicate, 21, 66, 39, 0, // Skip to: 18553 -/* 8503 */ MCD_OPC_Decode, 238, 8, 126, // Opcode: VCLSv2i32 -/* 8507 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8521 -/* 8512 */ MCD_OPC_CheckPredicate, 21, 52, 39, 0, // Skip to: 18553 -/* 8517 */ MCD_OPC_Decode, 240, 8, 127, // Opcode: VCLSv4i32 -/* 8521 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8535 -/* 8526 */ MCD_OPC_CheckPredicate, 21, 38, 39, 0, // Skip to: 18553 -/* 8531 */ MCD_OPC_Decode, 254, 8, 126, // Opcode: VCLZv2i32 -/* 8535 */ MCD_OPC_FilterValue, 3, 29, 39, 0, // Skip to: 18553 -/* 8540 */ MCD_OPC_CheckPredicate, 21, 24, 39, 0, // Skip to: 18553 -/* 8545 */ MCD_OPC_Decode, 128, 9, 127, // Opcode: VCLZv4i32 -/* 8549 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8613 -/* 8554 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8557 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8571 -/* 8562 */ MCD_OPC_CheckPredicate, 21, 2, 39, 0, // Skip to: 18553 -/* 8567 */ MCD_OPC_Decode, 218, 8, 126, // Opcode: VCGTzv2f32 -/* 8571 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8585 -/* 8576 */ MCD_OPC_CheckPredicate, 21, 244, 38, 0, // Skip to: 18553 -/* 8581 */ MCD_OPC_Decode, 221, 8, 127, // Opcode: VCGTzv4f32 -/* 8585 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8599 -/* 8590 */ MCD_OPC_CheckPredicate, 21, 230, 38, 0, // Skip to: 18553 -/* 8595 */ MCD_OPC_Decode, 192, 8, 126, // Opcode: VCGEzv2f32 -/* 8599 */ MCD_OPC_FilterValue, 3, 221, 38, 0, // Skip to: 18553 -/* 8604 */ MCD_OPC_CheckPredicate, 21, 216, 38, 0, // Skip to: 18553 -/* 8609 */ MCD_OPC_Decode, 195, 8, 127, // Opcode: VCGEzv4f32 -/* 8613 */ MCD_OPC_FilterValue, 11, 207, 38, 0, // Skip to: 18553 -/* 8618 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8621 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8635 -/* 8626 */ MCD_OPC_CheckPredicate, 21, 194, 38, 0, // Skip to: 18553 -/* 8631 */ MCD_OPC_Decode, 213, 16, 126, // Opcode: VRECPEd -/* 8635 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8649 -/* 8640 */ MCD_OPC_CheckPredicate, 21, 180, 38, 0, // Skip to: 18553 -/* 8645 */ MCD_OPC_Decode, 218, 16, 127, // Opcode: VRECPEq -/* 8649 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8663 -/* 8654 */ MCD_OPC_CheckPredicate, 21, 166, 38, 0, // Skip to: 18553 -/* 8659 */ MCD_OPC_Decode, 199, 17, 126, // Opcode: VRSQRTEd -/* 8663 */ MCD_OPC_FilterValue, 3, 157, 38, 0, // Skip to: 18553 -/* 8668 */ MCD_OPC_CheckPredicate, 21, 152, 38, 0, // Skip to: 18553 -/* 8673 */ MCD_OPC_Decode, 204, 17, 127, // Opcode: VRSQRTEq -/* 8677 */ MCD_OPC_FilterValue, 5, 67, 1, 0, // Skip to: 9005 -/* 8682 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 8685 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 8749 -/* 8690 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8693 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8707 -/* 8698 */ MCD_OPC_CheckPredicate, 21, 122, 38, 0, // Skip to: 18553 -/* 8703 */ MCD_OPC_Decode, 151, 9, 126, // Opcode: VCNTd -/* 8707 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8721 -/* 8712 */ MCD_OPC_CheckPredicate, 21, 108, 38, 0, // Skip to: 18553 -/* 8717 */ MCD_OPC_Decode, 152, 9, 127, // Opcode: VCNTq -/* 8721 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8735 -/* 8726 */ MCD_OPC_CheckPredicate, 21, 94, 38, 0, // Skip to: 18553 -/* 8731 */ MCD_OPC_Decode, 214, 14, 126, // Opcode: VMVNd -/* 8735 */ MCD_OPC_FilterValue, 3, 85, 38, 0, // Skip to: 18553 -/* 8740 */ MCD_OPC_CheckPredicate, 21, 80, 38, 0, // Skip to: 18553 -/* 8745 */ MCD_OPC_Decode, 215, 14, 127, // Opcode: VMVNq -/* 8749 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8813 -/* 8754 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8757 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8771 -/* 8762 */ MCD_OPC_CheckPredicate, 22, 58, 38, 0, // Skip to: 18553 -/* 8767 */ MCD_OPC_Decode, 168, 8, 126, // Opcode: VCEQzv4f16 -/* 8771 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8785 -/* 8776 */ MCD_OPC_CheckPredicate, 22, 44, 38, 0, // Skip to: 18553 -/* 8781 */ MCD_OPC_Decode, 172, 8, 127, // Opcode: VCEQzv8f16 -/* 8785 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8799 -/* 8790 */ MCD_OPC_CheckPredicate, 22, 30, 38, 0, // Skip to: 18553 -/* 8795 */ MCD_OPC_Decode, 230, 8, 126, // Opcode: VCLEzv4f16 -/* 8799 */ MCD_OPC_FilterValue, 3, 21, 38, 0, // Skip to: 18553 -/* 8804 */ MCD_OPC_CheckPredicate, 22, 16, 38, 0, // Skip to: 18553 -/* 8809 */ MCD_OPC_Decode, 234, 8, 127, // Opcode: VCLEzv8f16 -/* 8813 */ MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 8877 -/* 8818 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8821 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8835 -/* 8826 */ MCD_OPC_CheckPredicate, 22, 250, 37, 0, // Skip to: 18553 -/* 8831 */ MCD_OPC_Decode, 216, 16, 126, // Opcode: VRECPEhd -/* 8835 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8849 -/* 8840 */ MCD_OPC_CheckPredicate, 22, 236, 37, 0, // Skip to: 18553 -/* 8845 */ MCD_OPC_Decode, 217, 16, 127, // Opcode: VRECPEhq -/* 8849 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8863 -/* 8854 */ MCD_OPC_CheckPredicate, 22, 222, 37, 0, // Skip to: 18553 -/* 8859 */ MCD_OPC_Decode, 202, 17, 126, // Opcode: VRSQRTEhd -/* 8863 */ MCD_OPC_FilterValue, 3, 213, 37, 0, // Skip to: 18553 -/* 8868 */ MCD_OPC_CheckPredicate, 22, 208, 37, 0, // Skip to: 18553 -/* 8873 */ MCD_OPC_Decode, 203, 17, 127, // Opcode: VRSQRTEhq -/* 8877 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8941 -/* 8882 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8885 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8899 -/* 8890 */ MCD_OPC_CheckPredicate, 21, 186, 37, 0, // Skip to: 18553 -/* 8895 */ MCD_OPC_Decode, 166, 8, 126, // Opcode: VCEQzv2f32 -/* 8899 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8913 -/* 8904 */ MCD_OPC_CheckPredicate, 21, 172, 37, 0, // Skip to: 18553 -/* 8909 */ MCD_OPC_Decode, 169, 8, 127, // Opcode: VCEQzv4f32 -/* 8913 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8927 -/* 8918 */ MCD_OPC_CheckPredicate, 21, 158, 37, 0, // Skip to: 18553 -/* 8923 */ MCD_OPC_Decode, 228, 8, 126, // Opcode: VCLEzv2f32 -/* 8927 */ MCD_OPC_FilterValue, 3, 149, 37, 0, // Skip to: 18553 -/* 8932 */ MCD_OPC_CheckPredicate, 21, 144, 37, 0, // Skip to: 18553 -/* 8937 */ MCD_OPC_Decode, 231, 8, 127, // Opcode: VCLEzv4f32 -/* 8941 */ MCD_OPC_FilterValue, 11, 135, 37, 0, // Skip to: 18553 -/* 8946 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 8949 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8963 -/* 8954 */ MCD_OPC_CheckPredicate, 21, 122, 37, 0, // Skip to: 18553 -/* 8959 */ MCD_OPC_Decode, 214, 16, 126, // Opcode: VRECPEfd -/* 8963 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8977 -/* 8968 */ MCD_OPC_CheckPredicate, 21, 108, 37, 0, // Skip to: 18553 -/* 8973 */ MCD_OPC_Decode, 215, 16, 127, // Opcode: VRECPEfq -/* 8977 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8991 -/* 8982 */ MCD_OPC_CheckPredicate, 21, 94, 37, 0, // Skip to: 18553 -/* 8987 */ MCD_OPC_Decode, 200, 17, 126, // Opcode: VRSQRTEfd -/* 8991 */ MCD_OPC_FilterValue, 3, 85, 37, 0, // Skip to: 18553 -/* 8996 */ MCD_OPC_CheckPredicate, 21, 80, 37, 0, // Skip to: 18553 -/* 9001 */ MCD_OPC_Decode, 201, 17, 127, // Opcode: VRSQRTEfq -/* 9005 */ MCD_OPC_FilterValue, 6, 173, 1, 0, // Skip to: 9439 -/* 9010 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 9013 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 9081 -/* 9018 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9021 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9036 -/* 9026 */ MCD_OPC_CheckPredicate, 21, 50, 37, 0, // Skip to: 18553 -/* 9031 */ MCD_OPC_Decode, 255, 14, 132, 1, // Opcode: VPADALsv8i8 -/* 9036 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9051 -/* 9041 */ MCD_OPC_CheckPredicate, 21, 35, 37, 0, // Skip to: 18553 -/* 9046 */ MCD_OPC_Decode, 250, 14, 133, 1, // Opcode: VPADALsv16i8 -/* 9051 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9066 -/* 9056 */ MCD_OPC_CheckPredicate, 21, 20, 37, 0, // Skip to: 18553 -/* 9061 */ MCD_OPC_Decode, 133, 15, 132, 1, // Opcode: VPADALuv8i8 -/* 9066 */ MCD_OPC_FilterValue, 3, 10, 37, 0, // Skip to: 18553 -/* 9071 */ MCD_OPC_CheckPredicate, 21, 5, 37, 0, // Skip to: 18553 -/* 9076 */ MCD_OPC_Decode, 128, 15, 133, 1, // Opcode: VPADALuv16i8 -/* 9081 */ MCD_OPC_FilterValue, 4, 63, 0, 0, // Skip to: 9149 -/* 9086 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9089 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9104 -/* 9094 */ MCD_OPC_CheckPredicate, 21, 238, 36, 0, // Skip to: 18553 -/* 9099 */ MCD_OPC_Decode, 252, 14, 132, 1, // Opcode: VPADALsv4i16 -/* 9104 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9119 -/* 9109 */ MCD_OPC_CheckPredicate, 21, 223, 36, 0, // Skip to: 18553 -/* 9114 */ MCD_OPC_Decode, 254, 14, 133, 1, // Opcode: VPADALsv8i16 -/* 9119 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9134 -/* 9124 */ MCD_OPC_CheckPredicate, 21, 208, 36, 0, // Skip to: 18553 -/* 9129 */ MCD_OPC_Decode, 130, 15, 132, 1, // Opcode: VPADALuv4i16 -/* 9134 */ MCD_OPC_FilterValue, 3, 198, 36, 0, // Skip to: 18553 -/* 9139 */ MCD_OPC_CheckPredicate, 21, 193, 36, 0, // Skip to: 18553 -/* 9144 */ MCD_OPC_Decode, 132, 15, 133, 1, // Opcode: VPADALuv8i16 -/* 9149 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 9185 -/* 9154 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9157 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9171 -/* 9162 */ MCD_OPC_CheckPredicate, 22, 170, 36, 0, // Skip to: 18553 -/* 9167 */ MCD_OPC_Decode, 246, 8, 126, // Opcode: VCLTzv4f16 -/* 9171 */ MCD_OPC_FilterValue, 1, 161, 36, 0, // Skip to: 18553 -/* 9176 */ MCD_OPC_CheckPredicate, 22, 156, 36, 0, // Skip to: 18553 -/* 9181 */ MCD_OPC_Decode, 250, 8, 127, // Opcode: VCLTzv8f16 -/* 9185 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 9207 -/* 9190 */ MCD_OPC_CheckPredicate, 25, 142, 36, 0, // Skip to: 18553 -/* 9195 */ MCD_OPC_CheckField, 6, 2, 0, 135, 36, 0, // Skip to: 18553 -/* 9202 */ MCD_OPC_Decode, 219, 9, 130, 1, // Opcode: VCVTf2h -/* 9207 */ MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 9271 -/* 9212 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9215 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9229 -/* 9220 */ MCD_OPC_CheckPredicate, 22, 112, 36, 0, // Skip to: 18553 -/* 9225 */ MCD_OPC_Decode, 239, 9, 126, // Opcode: VCVTs2hd -/* 9229 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9243 -/* 9234 */ MCD_OPC_CheckPredicate, 22, 98, 36, 0, // Skip to: 18553 -/* 9239 */ MCD_OPC_Decode, 240, 9, 127, // Opcode: VCVTs2hq -/* 9243 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9257 -/* 9248 */ MCD_OPC_CheckPredicate, 22, 84, 36, 0, // Skip to: 18553 -/* 9253 */ MCD_OPC_Decode, 243, 9, 126, // Opcode: VCVTu2hd -/* 9257 */ MCD_OPC_FilterValue, 3, 75, 36, 0, // Skip to: 18553 -/* 9262 */ MCD_OPC_CheckPredicate, 22, 70, 36, 0, // Skip to: 18553 -/* 9267 */ MCD_OPC_Decode, 244, 9, 127, // Opcode: VCVTu2hq -/* 9271 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 9339 -/* 9276 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9279 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9294 -/* 9284 */ MCD_OPC_CheckPredicate, 21, 48, 36, 0, // Skip to: 18553 -/* 9289 */ MCD_OPC_Decode, 251, 14, 132, 1, // Opcode: VPADALsv2i32 -/* 9294 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9309 -/* 9299 */ MCD_OPC_CheckPredicate, 21, 33, 36, 0, // Skip to: 18553 -/* 9304 */ MCD_OPC_Decode, 253, 14, 133, 1, // Opcode: VPADALsv4i32 -/* 9309 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9324 -/* 9314 */ MCD_OPC_CheckPredicate, 21, 18, 36, 0, // Skip to: 18553 -/* 9319 */ MCD_OPC_Decode, 129, 15, 132, 1, // Opcode: VPADALuv2i32 -/* 9324 */ MCD_OPC_FilterValue, 3, 8, 36, 0, // Skip to: 18553 -/* 9329 */ MCD_OPC_CheckPredicate, 21, 3, 36, 0, // Skip to: 18553 -/* 9334 */ MCD_OPC_Decode, 131, 15, 133, 1, // Opcode: VPADALuv4i32 -/* 9339 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 9375 -/* 9344 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9347 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9361 -/* 9352 */ MCD_OPC_CheckPredicate, 21, 236, 35, 0, // Skip to: 18553 -/* 9357 */ MCD_OPC_Decode, 244, 8, 126, // Opcode: VCLTzv2f32 -/* 9361 */ MCD_OPC_FilterValue, 1, 227, 35, 0, // Skip to: 18553 -/* 9366 */ MCD_OPC_CheckPredicate, 21, 222, 35, 0, // Skip to: 18553 -/* 9371 */ MCD_OPC_Decode, 247, 8, 127, // Opcode: VCLTzv4f32 -/* 9375 */ MCD_OPC_FilterValue, 11, 213, 35, 0, // Skip to: 18553 -/* 9380 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9383 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9397 -/* 9388 */ MCD_OPC_CheckPredicate, 21, 200, 35, 0, // Skip to: 18553 -/* 9393 */ MCD_OPC_Decode, 237, 9, 126, // Opcode: VCVTs2fd -/* 9397 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9411 -/* 9402 */ MCD_OPC_CheckPredicate, 21, 186, 35, 0, // Skip to: 18553 -/* 9407 */ MCD_OPC_Decode, 238, 9, 127, // Opcode: VCVTs2fq -/* 9411 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9425 -/* 9416 */ MCD_OPC_CheckPredicate, 21, 172, 35, 0, // Skip to: 18553 -/* 9421 */ MCD_OPC_Decode, 241, 9, 126, // Opcode: VCVTu2fd -/* 9425 */ MCD_OPC_FilterValue, 3, 163, 35, 0, // Skip to: 18553 -/* 9430 */ MCD_OPC_CheckPredicate, 21, 158, 35, 0, // Skip to: 18553 -/* 9435 */ MCD_OPC_Decode, 242, 9, 127, // Opcode: VCVTu2fq -/* 9439 */ MCD_OPC_FilterValue, 7, 217, 1, 0, // Skip to: 9917 -/* 9444 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 9447 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 9511 -/* 9452 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9455 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9469 -/* 9460 */ MCD_OPC_CheckPredicate, 21, 128, 35, 0, // Skip to: 18553 -/* 9465 */ MCD_OPC_Decode, 172, 15, 126, // Opcode: VQABSv8i8 -/* 9469 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9483 -/* 9474 */ MCD_OPC_CheckPredicate, 21, 114, 35, 0, // Skip to: 18553 -/* 9479 */ MCD_OPC_Decode, 167, 15, 127, // Opcode: VQABSv16i8 -/* 9483 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9497 -/* 9488 */ MCD_OPC_CheckPredicate, 21, 100, 35, 0, // Skip to: 18553 -/* 9493 */ MCD_OPC_Decode, 223, 15, 126, // Opcode: VQNEGv8i8 -/* 9497 */ MCD_OPC_FilterValue, 3, 91, 35, 0, // Skip to: 18553 -/* 9502 */ MCD_OPC_CheckPredicate, 21, 86, 35, 0, // Skip to: 18553 -/* 9507 */ MCD_OPC_Decode, 218, 15, 127, // Opcode: VQNEGv16i8 -/* 9511 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 9575 -/* 9516 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9519 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9533 -/* 9524 */ MCD_OPC_CheckPredicate, 21, 64, 35, 0, // Skip to: 18553 -/* 9529 */ MCD_OPC_Decode, 169, 15, 126, // Opcode: VQABSv4i16 -/* 9533 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9547 -/* 9538 */ MCD_OPC_CheckPredicate, 21, 50, 35, 0, // Skip to: 18553 -/* 9543 */ MCD_OPC_Decode, 171, 15, 127, // Opcode: VQABSv8i16 -/* 9547 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9561 -/* 9552 */ MCD_OPC_CheckPredicate, 21, 36, 35, 0, // Skip to: 18553 -/* 9557 */ MCD_OPC_Decode, 220, 15, 126, // Opcode: VQNEGv4i16 -/* 9561 */ MCD_OPC_FilterValue, 3, 27, 35, 0, // Skip to: 18553 -/* 9566 */ MCD_OPC_CheckPredicate, 21, 22, 35, 0, // Skip to: 18553 -/* 9571 */ MCD_OPC_Decode, 222, 15, 127, // Opcode: VQNEGv8i16 -/* 9575 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 9639 -/* 9580 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9583 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9597 -/* 9588 */ MCD_OPC_CheckPredicate, 22, 0, 35, 0, // Skip to: 18553 -/* 9593 */ MCD_OPC_Decode, 219, 7, 126, // Opcode: VABShd -/* 9597 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9611 -/* 9602 */ MCD_OPC_CheckPredicate, 22, 242, 34, 0, // Skip to: 18553 -/* 9607 */ MCD_OPC_Decode, 220, 7, 127, // Opcode: VABShq -/* 9611 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9625 -/* 9616 */ MCD_OPC_CheckPredicate, 22, 228, 34, 0, // Skip to: 18553 -/* 9621 */ MCD_OPC_Decode, 225, 14, 126, // Opcode: VNEGhd -/* 9625 */ MCD_OPC_FilterValue, 3, 219, 34, 0, // Skip to: 18553 -/* 9630 */ MCD_OPC_CheckPredicate, 22, 214, 34, 0, // Skip to: 18553 -/* 9635 */ MCD_OPC_Decode, 226, 14, 127, // Opcode: VNEGhq -/* 9639 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 9661 -/* 9644 */ MCD_OPC_CheckPredicate, 25, 200, 34, 0, // Skip to: 18553 -/* 9649 */ MCD_OPC_CheckField, 6, 2, 0, 193, 34, 0, // Skip to: 18553 -/* 9656 */ MCD_OPC_Decode, 228, 9, 134, 1, // Opcode: VCVTh2f -/* 9661 */ MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 9725 -/* 9666 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9669 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9683 -/* 9674 */ MCD_OPC_CheckPredicate, 22, 170, 34, 0, // Skip to: 18553 -/* 9679 */ MCD_OPC_Decode, 229, 9, 126, // Opcode: VCVTh2sd -/* 9683 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9697 -/* 9688 */ MCD_OPC_CheckPredicate, 22, 156, 34, 0, // Skip to: 18553 -/* 9693 */ MCD_OPC_Decode, 230, 9, 127, // Opcode: VCVTh2sq -/* 9697 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9711 -/* 9702 */ MCD_OPC_CheckPredicate, 22, 142, 34, 0, // Skip to: 18553 -/* 9707 */ MCD_OPC_Decode, 231, 9, 126, // Opcode: VCVTh2ud -/* 9711 */ MCD_OPC_FilterValue, 3, 133, 34, 0, // Skip to: 18553 -/* 9716 */ MCD_OPC_CheckPredicate, 22, 128, 34, 0, // Skip to: 18553 -/* 9721 */ MCD_OPC_Decode, 232, 9, 127, // Opcode: VCVTh2uq -/* 9725 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 9789 -/* 9730 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9733 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9747 -/* 9738 */ MCD_OPC_CheckPredicate, 21, 106, 34, 0, // Skip to: 18553 -/* 9743 */ MCD_OPC_Decode, 168, 15, 126, // Opcode: VQABSv2i32 -/* 9747 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9761 -/* 9752 */ MCD_OPC_CheckPredicate, 21, 92, 34, 0, // Skip to: 18553 -/* 9757 */ MCD_OPC_Decode, 170, 15, 127, // Opcode: VQABSv4i32 -/* 9761 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9775 -/* 9766 */ MCD_OPC_CheckPredicate, 21, 78, 34, 0, // Skip to: 18553 -/* 9771 */ MCD_OPC_Decode, 219, 15, 126, // Opcode: VQNEGv2i32 -/* 9775 */ MCD_OPC_FilterValue, 3, 69, 34, 0, // Skip to: 18553 -/* 9780 */ MCD_OPC_CheckPredicate, 21, 64, 34, 0, // Skip to: 18553 -/* 9785 */ MCD_OPC_Decode, 221, 15, 127, // Opcode: VQNEGv4i32 -/* 9789 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 9853 -/* 9794 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9797 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9811 -/* 9802 */ MCD_OPC_CheckPredicate, 21, 42, 34, 0, // Skip to: 18553 -/* 9807 */ MCD_OPC_Decode, 217, 7, 126, // Opcode: VABSfd -/* 9811 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9825 -/* 9816 */ MCD_OPC_CheckPredicate, 21, 28, 34, 0, // Skip to: 18553 -/* 9821 */ MCD_OPC_Decode, 218, 7, 127, // Opcode: VABSfq -/* 9825 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9839 -/* 9830 */ MCD_OPC_CheckPredicate, 21, 14, 34, 0, // Skip to: 18553 -/* 9835 */ MCD_OPC_Decode, 224, 14, 126, // Opcode: VNEGfd -/* 9839 */ MCD_OPC_FilterValue, 3, 5, 34, 0, // Skip to: 18553 -/* 9844 */ MCD_OPC_CheckPredicate, 21, 0, 34, 0, // Skip to: 18553 -/* 9849 */ MCD_OPC_Decode, 223, 14, 127, // Opcode: VNEGf32q -/* 9853 */ MCD_OPC_FilterValue, 11, 247, 33, 0, // Skip to: 18553 -/* 9858 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 9861 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9875 -/* 9866 */ MCD_OPC_CheckPredicate, 21, 234, 33, 0, // Skip to: 18553 -/* 9871 */ MCD_OPC_Decode, 220, 9, 126, // Opcode: VCVTf2sd -/* 9875 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9889 -/* 9880 */ MCD_OPC_CheckPredicate, 21, 220, 33, 0, // Skip to: 18553 -/* 9885 */ MCD_OPC_Decode, 221, 9, 127, // Opcode: VCVTf2sq -/* 9889 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9903 -/* 9894 */ MCD_OPC_CheckPredicate, 21, 206, 33, 0, // Skip to: 18553 -/* 9899 */ MCD_OPC_Decode, 222, 9, 126, // Opcode: VCVTf2ud -/* 9903 */ MCD_OPC_FilterValue, 3, 197, 33, 0, // Skip to: 18553 -/* 9908 */ MCD_OPC_CheckPredicate, 21, 192, 33, 0, // Skip to: 18553 -/* 9913 */ MCD_OPC_Decode, 223, 9, 127, // Opcode: VCVTf2uq -/* 9917 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 9955 -/* 9922 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 9925 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9940 -/* 9930 */ MCD_OPC_CheckPredicate, 21, 170, 33, 0, // Skip to: 18553 -/* 9935 */ MCD_OPC_Decode, 239, 20, 135, 1, // Opcode: VTBL1 -/* 9940 */ MCD_OPC_FilterValue, 1, 160, 33, 0, // Skip to: 18553 -/* 9945 */ MCD_OPC_CheckPredicate, 21, 155, 33, 0, // Skip to: 18553 -/* 9950 */ MCD_OPC_Decode, 245, 20, 135, 1, // Opcode: VTBX1 -/* 9955 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 9993 -/* 9960 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 9963 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9978 -/* 9968 */ MCD_OPC_CheckPredicate, 21, 132, 33, 0, // Skip to: 18553 -/* 9973 */ MCD_OPC_Decode, 240, 20, 135, 1, // Opcode: VTBL2 -/* 9978 */ MCD_OPC_FilterValue, 1, 122, 33, 0, // Skip to: 18553 -/* 9983 */ MCD_OPC_CheckPredicate, 21, 117, 33, 0, // Skip to: 18553 -/* 9988 */ MCD_OPC_Decode, 246, 20, 135, 1, // Opcode: VTBX2 -/* 9993 */ MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 10031 -/* 9998 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 10001 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10016 -/* 10006 */ MCD_OPC_CheckPredicate, 21, 94, 33, 0, // Skip to: 18553 -/* 10011 */ MCD_OPC_Decode, 241, 20, 135, 1, // Opcode: VTBL3 -/* 10016 */ MCD_OPC_FilterValue, 1, 84, 33, 0, // Skip to: 18553 -/* 10021 */ MCD_OPC_CheckPredicate, 21, 79, 33, 0, // Skip to: 18553 -/* 10026 */ MCD_OPC_Decode, 247, 20, 135, 1, // Opcode: VTBX3 -/* 10031 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 10069 -/* 10036 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 10039 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10054 -/* 10044 */ MCD_OPC_CheckPredicate, 21, 56, 33, 0, // Skip to: 18553 -/* 10049 */ MCD_OPC_Decode, 243, 20, 135, 1, // Opcode: VTBL4 -/* 10054 */ MCD_OPC_FilterValue, 1, 46, 33, 0, // Skip to: 18553 -/* 10059 */ MCD_OPC_CheckPredicate, 21, 41, 33, 0, // Skip to: 18553 -/* 10064 */ MCD_OPC_Decode, 249, 20, 135, 1, // Opcode: VTBX4 -/* 10069 */ MCD_OPC_FilterValue, 12, 31, 33, 0, // Skip to: 18553 -/* 10074 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 10077 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 10145 -/* 10082 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 10085 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10130 -/* 10090 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 10093 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10115 -/* 10098 */ MCD_OPC_CheckPredicate, 21, 2, 33, 0, // Skip to: 18553 -/* 10103 */ MCD_OPC_CheckField, 18, 1, 1, 251, 32, 0, // Skip to: 18553 -/* 10110 */ MCD_OPC_Decode, 136, 10, 136, 1, // Opcode: VDUPLN32d -/* 10115 */ MCD_OPC_FilterValue, 1, 241, 32, 0, // Skip to: 18553 -/* 10120 */ MCD_OPC_CheckPredicate, 21, 236, 32, 0, // Skip to: 18553 -/* 10125 */ MCD_OPC_Decode, 134, 10, 137, 1, // Opcode: VDUPLN16d -/* 10130 */ MCD_OPC_FilterValue, 1, 226, 32, 0, // Skip to: 18553 -/* 10135 */ MCD_OPC_CheckPredicate, 21, 221, 32, 0, // Skip to: 18553 -/* 10140 */ MCD_OPC_Decode, 138, 10, 138, 1, // Opcode: VDUPLN8d -/* 10145 */ MCD_OPC_FilterValue, 1, 211, 32, 0, // Skip to: 18553 -/* 10150 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 10153 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10198 -/* 10158 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 10161 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10183 -/* 10166 */ MCD_OPC_CheckPredicate, 21, 190, 32, 0, // Skip to: 18553 -/* 10171 */ MCD_OPC_CheckField, 18, 1, 1, 183, 32, 0, // Skip to: 18553 -/* 10178 */ MCD_OPC_Decode, 137, 10, 139, 1, // Opcode: VDUPLN32q -/* 10183 */ MCD_OPC_FilterValue, 1, 173, 32, 0, // Skip to: 18553 -/* 10188 */ MCD_OPC_CheckPredicate, 21, 168, 32, 0, // Skip to: 18553 -/* 10193 */ MCD_OPC_Decode, 135, 10, 140, 1, // Opcode: VDUPLN16q -/* 10198 */ MCD_OPC_FilterValue, 1, 158, 32, 0, // Skip to: 18553 -/* 10203 */ MCD_OPC_CheckPredicate, 21, 153, 32, 0, // Skip to: 18553 -/* 10208 */ MCD_OPC_Decode, 139, 10, 141, 1, // Opcode: VDUPLN8q -/* 10213 */ MCD_OPC_FilterValue, 1, 143, 32, 0, // Skip to: 18553 -/* 10218 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 10221 */ MCD_OPC_FilterValue, 0, 21, 17, 0, // Skip to: 14599 -/* 10226 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 10229 */ MCD_OPC_FilterValue, 0, 9, 8, 0, // Skip to: 12291 -/* 10234 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 10237 */ MCD_OPC_FilterValue, 0, 155, 0, 0, // Skip to: 10397 -/* 10242 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 10245 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10283 -/* 10250 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10253 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10268 -/* 10259 */ MCD_OPC_CheckPredicate, 21, 97, 32, 0, // Skip to: 18553 -/* 10264 */ MCD_OPC_Decode, 180, 15, 97, // Opcode: VQADDsv8i8 -/* 10268 */ MCD_OPC_FilterValue, 243, 1, 87, 32, 0, // Skip to: 18553 -/* 10274 */ MCD_OPC_CheckPredicate, 21, 82, 32, 0, // Skip to: 18553 -/* 10279 */ MCD_OPC_Decode, 188, 15, 97, // Opcode: VQADDuv8i8 -/* 10283 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10321 -/* 10288 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10291 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10306 -/* 10297 */ MCD_OPC_CheckPredicate, 21, 59, 32, 0, // Skip to: 18553 -/* 10302 */ MCD_OPC_Decode, 177, 15, 97, // Opcode: VQADDsv4i16 -/* 10306 */ MCD_OPC_FilterValue, 243, 1, 49, 32, 0, // Skip to: 18553 -/* 10312 */ MCD_OPC_CheckPredicate, 21, 44, 32, 0, // Skip to: 18553 -/* 10317 */ MCD_OPC_Decode, 185, 15, 97, // Opcode: VQADDuv4i16 -/* 10321 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10359 -/* 10326 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10329 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10344 -/* 10335 */ MCD_OPC_CheckPredicate, 21, 21, 32, 0, // Skip to: 18553 -/* 10340 */ MCD_OPC_Decode, 175, 15, 97, // Opcode: VQADDsv2i32 -/* 10344 */ MCD_OPC_FilterValue, 243, 1, 11, 32, 0, // Skip to: 18553 -/* 10350 */ MCD_OPC_CheckPredicate, 21, 6, 32, 0, // Skip to: 18553 -/* 10355 */ MCD_OPC_Decode, 183, 15, 97, // Opcode: VQADDuv2i32 -/* 10359 */ MCD_OPC_FilterValue, 3, 253, 31, 0, // Skip to: 18553 -/* 10364 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10367 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10382 -/* 10373 */ MCD_OPC_CheckPredicate, 21, 239, 31, 0, // Skip to: 18553 -/* 10378 */ MCD_OPC_Decode, 174, 15, 97, // Opcode: VQADDsv1i64 -/* 10382 */ MCD_OPC_FilterValue, 243, 1, 229, 31, 0, // Skip to: 18553 -/* 10388 */ MCD_OPC_CheckPredicate, 21, 224, 31, 0, // Skip to: 18553 -/* 10393 */ MCD_OPC_Decode, 182, 15, 97, // Opcode: VQADDuv1i64 -/* 10397 */ MCD_OPC_FilterValue, 1, 155, 0, 0, // Skip to: 10557 -/* 10402 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 10405 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10443 -/* 10410 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10413 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10428 -/* 10419 */ MCD_OPC_CheckPredicate, 21, 193, 31, 0, // Skip to: 18553 -/* 10424 */ MCD_OPC_Decode, 137, 8, 97, // Opcode: VANDd -/* 10428 */ MCD_OPC_FilterValue, 243, 1, 183, 31, 0, // Skip to: 18553 -/* 10434 */ MCD_OPC_CheckPredicate, 21, 178, 31, 0, // Skip to: 18553 -/* 10439 */ MCD_OPC_Decode, 140, 10, 97, // Opcode: VEORd -/* 10443 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10481 -/* 10448 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10451 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10466 -/* 10457 */ MCD_OPC_CheckPredicate, 21, 155, 31, 0, // Skip to: 18553 -/* 10462 */ MCD_OPC_Decode, 139, 8, 97, // Opcode: VBICd -/* 10466 */ MCD_OPC_FilterValue, 243, 1, 145, 31, 0, // Skip to: 18553 -/* 10472 */ MCD_OPC_CheckPredicate, 21, 140, 31, 0, // Skip to: 18553 -/* 10477 */ MCD_OPC_Decode, 149, 8, 105, // Opcode: VBSLd -/* 10481 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10519 -/* 10486 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10489 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10504 -/* 10495 */ MCD_OPC_CheckPredicate, 21, 117, 31, 0, // Skip to: 18553 -/* 10500 */ MCD_OPC_Decode, 244, 14, 97, // Opcode: VORRd -/* 10504 */ MCD_OPC_FilterValue, 243, 1, 107, 31, 0, // Skip to: 18553 -/* 10510 */ MCD_OPC_CheckPredicate, 21, 102, 31, 0, // Skip to: 18553 -/* 10515 */ MCD_OPC_Decode, 147, 8, 105, // Opcode: VBITd -/* 10519 */ MCD_OPC_FilterValue, 3, 93, 31, 0, // Skip to: 18553 -/* 10524 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10527 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10542 -/* 10533 */ MCD_OPC_CheckPredicate, 21, 79, 31, 0, // Skip to: 18553 -/* 10538 */ MCD_OPC_Decode, 242, 14, 97, // Opcode: VORNd -/* 10542 */ MCD_OPC_FilterValue, 243, 1, 69, 31, 0, // Skip to: 18553 -/* 10548 */ MCD_OPC_CheckPredicate, 21, 64, 31, 0, // Skip to: 18553 -/* 10553 */ MCD_OPC_Decode, 145, 8, 105, // Opcode: VBIFd -/* 10557 */ MCD_OPC_FilterValue, 2, 155, 0, 0, // Skip to: 10717 -/* 10562 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 10565 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10603 -/* 10570 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10573 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10588 -/* 10579 */ MCD_OPC_CheckPredicate, 21, 33, 31, 0, // Skip to: 18553 -/* 10584 */ MCD_OPC_Decode, 201, 16, 97, // Opcode: VQSUBsv8i8 -/* 10588 */ MCD_OPC_FilterValue, 243, 1, 23, 31, 0, // Skip to: 18553 -/* 10594 */ MCD_OPC_CheckPredicate, 21, 18, 31, 0, // Skip to: 18553 -/* 10599 */ MCD_OPC_Decode, 209, 16, 97, // Opcode: VQSUBuv8i8 -/* 10603 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10641 -/* 10608 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10611 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10626 -/* 10617 */ MCD_OPC_CheckPredicate, 21, 251, 30, 0, // Skip to: 18553 -/* 10622 */ MCD_OPC_Decode, 198, 16, 97, // Opcode: VQSUBsv4i16 -/* 10626 */ MCD_OPC_FilterValue, 243, 1, 241, 30, 0, // Skip to: 18553 -/* 10632 */ MCD_OPC_CheckPredicate, 21, 236, 30, 0, // Skip to: 18553 -/* 10637 */ MCD_OPC_Decode, 206, 16, 97, // Opcode: VQSUBuv4i16 -/* 10641 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10679 -/* 10646 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10649 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10664 -/* 10655 */ MCD_OPC_CheckPredicate, 21, 213, 30, 0, // Skip to: 18553 -/* 10660 */ MCD_OPC_Decode, 196, 16, 97, // Opcode: VQSUBsv2i32 -/* 10664 */ MCD_OPC_FilterValue, 243, 1, 203, 30, 0, // Skip to: 18553 -/* 10670 */ MCD_OPC_CheckPredicate, 21, 198, 30, 0, // Skip to: 18553 -/* 10675 */ MCD_OPC_Decode, 204, 16, 97, // Opcode: VQSUBuv2i32 -/* 10679 */ MCD_OPC_FilterValue, 3, 189, 30, 0, // Skip to: 18553 -/* 10684 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10687 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10702 -/* 10693 */ MCD_OPC_CheckPredicate, 21, 175, 30, 0, // Skip to: 18553 -/* 10698 */ MCD_OPC_Decode, 195, 16, 97, // Opcode: VQSUBsv1i64 -/* 10702 */ MCD_OPC_FilterValue, 243, 1, 165, 30, 0, // Skip to: 18553 -/* 10708 */ MCD_OPC_CheckPredicate, 21, 160, 30, 0, // Skip to: 18553 -/* 10713 */ MCD_OPC_Decode, 203, 16, 97, // Opcode: VQSUBuv1i64 -/* 10717 */ MCD_OPC_FilterValue, 3, 117, 0, 0, // Skip to: 10839 -/* 10722 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 10725 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10763 -/* 10730 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10733 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10748 -/* 10739 */ MCD_OPC_CheckPredicate, 21, 129, 30, 0, // Skip to: 18553 -/* 10744 */ MCD_OPC_Decode, 184, 8, 97, // Opcode: VCGEsv8i8 -/* 10748 */ MCD_OPC_FilterValue, 243, 1, 119, 30, 0, // Skip to: 18553 -/* 10754 */ MCD_OPC_CheckPredicate, 21, 114, 30, 0, // Skip to: 18553 -/* 10759 */ MCD_OPC_Decode, 190, 8, 97, // Opcode: VCGEuv8i8 -/* 10763 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10801 -/* 10768 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10771 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10786 -/* 10777 */ MCD_OPC_CheckPredicate, 21, 91, 30, 0, // Skip to: 18553 -/* 10782 */ MCD_OPC_Decode, 181, 8, 97, // Opcode: VCGEsv4i16 -/* 10786 */ MCD_OPC_FilterValue, 243, 1, 81, 30, 0, // Skip to: 18553 -/* 10792 */ MCD_OPC_CheckPredicate, 21, 76, 30, 0, // Skip to: 18553 -/* 10797 */ MCD_OPC_Decode, 187, 8, 97, // Opcode: VCGEuv4i16 -/* 10801 */ MCD_OPC_FilterValue, 2, 67, 30, 0, // Skip to: 18553 -/* 10806 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10809 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10824 -/* 10815 */ MCD_OPC_CheckPredicate, 21, 53, 30, 0, // Skip to: 18553 -/* 10820 */ MCD_OPC_Decode, 180, 8, 97, // Opcode: VCGEsv2i32 -/* 10824 */ MCD_OPC_FilterValue, 243, 1, 43, 30, 0, // Skip to: 18553 -/* 10830 */ MCD_OPC_CheckPredicate, 21, 38, 30, 0, // Skip to: 18553 -/* 10835 */ MCD_OPC_Decode, 186, 8, 97, // Opcode: VCGEuv2i32 -/* 10839 */ MCD_OPC_FilterValue, 4, 155, 0, 0, // Skip to: 10999 -/* 10844 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 10847 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10885 -/* 10852 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10855 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10870 -/* 10861 */ MCD_OPC_CheckPredicate, 21, 7, 30, 0, // Skip to: 18553 -/* 10866 */ MCD_OPC_Decode, 168, 16, 101, // Opcode: VQSHLsv8i8 -/* 10870 */ MCD_OPC_FilterValue, 243, 1, 253, 29, 0, // Skip to: 18553 -/* 10876 */ MCD_OPC_CheckPredicate, 21, 248, 29, 0, // Skip to: 18553 -/* 10881 */ MCD_OPC_Decode, 184, 16, 101, // Opcode: VQSHLuv8i8 -/* 10885 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10923 -/* 10890 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10893 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10908 -/* 10899 */ MCD_OPC_CheckPredicate, 21, 225, 29, 0, // Skip to: 18553 -/* 10904 */ MCD_OPC_Decode, 165, 16, 101, // Opcode: VQSHLsv4i16 -/* 10908 */ MCD_OPC_FilterValue, 243, 1, 215, 29, 0, // Skip to: 18553 -/* 10914 */ MCD_OPC_CheckPredicate, 21, 210, 29, 0, // Skip to: 18553 -/* 10919 */ MCD_OPC_Decode, 181, 16, 101, // Opcode: VQSHLuv4i16 -/* 10923 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10961 -/* 10928 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10931 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10946 -/* 10937 */ MCD_OPC_CheckPredicate, 21, 187, 29, 0, // Skip to: 18553 -/* 10942 */ MCD_OPC_Decode, 163, 16, 101, // Opcode: VQSHLsv2i32 -/* 10946 */ MCD_OPC_FilterValue, 243, 1, 177, 29, 0, // Skip to: 18553 -/* 10952 */ MCD_OPC_CheckPredicate, 21, 172, 29, 0, // Skip to: 18553 -/* 10957 */ MCD_OPC_Decode, 179, 16, 101, // Opcode: VQSHLuv2i32 -/* 10961 */ MCD_OPC_FilterValue, 3, 163, 29, 0, // Skip to: 18553 -/* 10966 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 10969 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10984 -/* 10975 */ MCD_OPC_CheckPredicate, 21, 149, 29, 0, // Skip to: 18553 -/* 10980 */ MCD_OPC_Decode, 162, 16, 101, // Opcode: VQSHLsv1i64 -/* 10984 */ MCD_OPC_FilterValue, 243, 1, 139, 29, 0, // Skip to: 18553 -/* 10990 */ MCD_OPC_CheckPredicate, 21, 134, 29, 0, // Skip to: 18553 -/* 10995 */ MCD_OPC_Decode, 178, 16, 101, // Opcode: VQSHLuv1i64 -/* 10999 */ MCD_OPC_FilterValue, 5, 155, 0, 0, // Skip to: 11159 -/* 11004 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11007 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11045 -/* 11012 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11015 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11030 -/* 11021 */ MCD_OPC_CheckPredicate, 21, 103, 29, 0, // Skip to: 18553 -/* 11026 */ MCD_OPC_Decode, 255, 15, 101, // Opcode: VQRSHLsv8i8 -/* 11030 */ MCD_OPC_FilterValue, 243, 1, 93, 29, 0, // Skip to: 18553 -/* 11036 */ MCD_OPC_CheckPredicate, 21, 88, 29, 0, // Skip to: 18553 -/* 11041 */ MCD_OPC_Decode, 135, 16, 101, // Opcode: VQRSHLuv8i8 -/* 11045 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11083 -/* 11050 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11053 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11068 -/* 11059 */ MCD_OPC_CheckPredicate, 21, 65, 29, 0, // Skip to: 18553 -/* 11064 */ MCD_OPC_Decode, 252, 15, 101, // Opcode: VQRSHLsv4i16 -/* 11068 */ MCD_OPC_FilterValue, 243, 1, 55, 29, 0, // Skip to: 18553 -/* 11074 */ MCD_OPC_CheckPredicate, 21, 50, 29, 0, // Skip to: 18553 -/* 11079 */ MCD_OPC_Decode, 132, 16, 101, // Opcode: VQRSHLuv4i16 -/* 11083 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 11121 -/* 11088 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11091 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11106 -/* 11097 */ MCD_OPC_CheckPredicate, 21, 27, 29, 0, // Skip to: 18553 -/* 11102 */ MCD_OPC_Decode, 250, 15, 101, // Opcode: VQRSHLsv2i32 -/* 11106 */ MCD_OPC_FilterValue, 243, 1, 17, 29, 0, // Skip to: 18553 -/* 11112 */ MCD_OPC_CheckPredicate, 21, 12, 29, 0, // Skip to: 18553 -/* 11117 */ MCD_OPC_Decode, 130, 16, 101, // Opcode: VQRSHLuv2i32 -/* 11121 */ MCD_OPC_FilterValue, 3, 3, 29, 0, // Skip to: 18553 -/* 11126 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11129 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11144 -/* 11135 */ MCD_OPC_CheckPredicate, 21, 245, 28, 0, // Skip to: 18553 -/* 11140 */ MCD_OPC_Decode, 249, 15, 101, // Opcode: VQRSHLsv1i64 -/* 11144 */ MCD_OPC_FilterValue, 243, 1, 235, 28, 0, // Skip to: 18553 -/* 11150 */ MCD_OPC_CheckPredicate, 21, 230, 28, 0, // Skip to: 18553 -/* 11155 */ MCD_OPC_Decode, 129, 16, 101, // Opcode: VQRSHLuv1i64 -/* 11159 */ MCD_OPC_FilterValue, 6, 117, 0, 0, // Skip to: 11281 -/* 11164 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11167 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11205 -/* 11172 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11175 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11190 -/* 11181 */ MCD_OPC_CheckPredicate, 21, 199, 28, 0, // Skip to: 18553 -/* 11186 */ MCD_OPC_Decode, 195, 13, 97, // Opcode: VMINsv8i8 -/* 11190 */ MCD_OPC_FilterValue, 243, 1, 189, 28, 0, // Skip to: 18553 -/* 11196 */ MCD_OPC_CheckPredicate, 21, 184, 28, 0, // Skip to: 18553 -/* 11201 */ MCD_OPC_Decode, 201, 13, 97, // Opcode: VMINuv8i8 -/* 11205 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11243 -/* 11210 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11213 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11228 -/* 11219 */ MCD_OPC_CheckPredicate, 21, 161, 28, 0, // Skip to: 18553 -/* 11224 */ MCD_OPC_Decode, 192, 13, 97, // Opcode: VMINsv4i16 -/* 11228 */ MCD_OPC_FilterValue, 243, 1, 151, 28, 0, // Skip to: 18553 -/* 11234 */ MCD_OPC_CheckPredicate, 21, 146, 28, 0, // Skip to: 18553 -/* 11239 */ MCD_OPC_Decode, 198, 13, 97, // Opcode: VMINuv4i16 -/* 11243 */ MCD_OPC_FilterValue, 2, 137, 28, 0, // Skip to: 18553 -/* 11248 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11251 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11266 -/* 11257 */ MCD_OPC_CheckPredicate, 21, 123, 28, 0, // Skip to: 18553 -/* 11262 */ MCD_OPC_Decode, 191, 13, 97, // Opcode: VMINsv2i32 -/* 11266 */ MCD_OPC_FilterValue, 243, 1, 113, 28, 0, // Skip to: 18553 -/* 11272 */ MCD_OPC_CheckPredicate, 21, 108, 28, 0, // Skip to: 18553 -/* 11277 */ MCD_OPC_Decode, 197, 13, 97, // Opcode: VMINuv2i32 -/* 11281 */ MCD_OPC_FilterValue, 7, 117, 0, 0, // Skip to: 11403 -/* 11286 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11289 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11327 -/* 11294 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11297 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11312 -/* 11303 */ MCD_OPC_CheckPredicate, 21, 77, 28, 0, // Skip to: 18553 -/* 11308 */ MCD_OPC_Decode, 185, 7, 105, // Opcode: VABAsv8i8 -/* 11312 */ MCD_OPC_FilterValue, 243, 1, 67, 28, 0, // Skip to: 18553 -/* 11318 */ MCD_OPC_CheckPredicate, 21, 62, 28, 0, // Skip to: 18553 -/* 11323 */ MCD_OPC_Decode, 191, 7, 105, // Opcode: VABAuv8i8 -/* 11327 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11365 -/* 11332 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11335 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11350 -/* 11341 */ MCD_OPC_CheckPredicate, 21, 39, 28, 0, // Skip to: 18553 -/* 11346 */ MCD_OPC_Decode, 182, 7, 105, // Opcode: VABAsv4i16 -/* 11350 */ MCD_OPC_FilterValue, 243, 1, 29, 28, 0, // Skip to: 18553 -/* 11356 */ MCD_OPC_CheckPredicate, 21, 24, 28, 0, // Skip to: 18553 -/* 11361 */ MCD_OPC_Decode, 188, 7, 105, // Opcode: VABAuv4i16 -/* 11365 */ MCD_OPC_FilterValue, 2, 15, 28, 0, // Skip to: 18553 -/* 11370 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11373 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11388 -/* 11379 */ MCD_OPC_CheckPredicate, 21, 1, 28, 0, // Skip to: 18553 -/* 11384 */ MCD_OPC_Decode, 181, 7, 105, // Opcode: VABAsv2i32 -/* 11388 */ MCD_OPC_FilterValue, 243, 1, 247, 27, 0, // Skip to: 18553 -/* 11394 */ MCD_OPC_CheckPredicate, 21, 242, 27, 0, // Skip to: 18553 -/* 11399 */ MCD_OPC_Decode, 187, 7, 105, // Opcode: VABAuv2i32 -/* 11403 */ MCD_OPC_FilterValue, 8, 117, 0, 0, // Skip to: 11525 -/* 11408 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11411 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11449 -/* 11416 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11419 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11434 -/* 11425 */ MCD_OPC_CheckPredicate, 21, 211, 27, 0, // Skip to: 18553 -/* 11430 */ MCD_OPC_Decode, 158, 21, 97, // Opcode: VTSTv8i8 -/* 11434 */ MCD_OPC_FilterValue, 243, 1, 201, 27, 0, // Skip to: 18553 -/* 11440 */ MCD_OPC_CheckPredicate, 21, 196, 27, 0, // Skip to: 18553 -/* 11445 */ MCD_OPC_Decode, 164, 8, 97, // Opcode: VCEQv8i8 -/* 11449 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11487 -/* 11454 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11457 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11472 -/* 11463 */ MCD_OPC_CheckPredicate, 21, 173, 27, 0, // Skip to: 18553 -/* 11468 */ MCD_OPC_Decode, 155, 21, 97, // Opcode: VTSTv4i16 -/* 11472 */ MCD_OPC_FilterValue, 243, 1, 163, 27, 0, // Skip to: 18553 -/* 11478 */ MCD_OPC_CheckPredicate, 21, 158, 27, 0, // Skip to: 18553 -/* 11483 */ MCD_OPC_Decode, 161, 8, 97, // Opcode: VCEQv4i16 -/* 11487 */ MCD_OPC_FilterValue, 2, 149, 27, 0, // Skip to: 18553 -/* 11492 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11495 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11510 -/* 11501 */ MCD_OPC_CheckPredicate, 21, 135, 27, 0, // Skip to: 18553 -/* 11506 */ MCD_OPC_Decode, 154, 21, 97, // Opcode: VTSTv2i32 -/* 11510 */ MCD_OPC_FilterValue, 243, 1, 125, 27, 0, // Skip to: 18553 -/* 11516 */ MCD_OPC_CheckPredicate, 21, 120, 27, 0, // Skip to: 18553 -/* 11521 */ MCD_OPC_Decode, 160, 8, 97, // Opcode: VCEQv2i32 -/* 11525 */ MCD_OPC_FilterValue, 9, 85, 0, 0, // Skip to: 11615 -/* 11530 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11533 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11571 -/* 11538 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11541 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11556 -/* 11547 */ MCD_OPC_CheckPredicate, 21, 89, 27, 0, // Skip to: 18553 -/* 11552 */ MCD_OPC_Decode, 213, 14, 97, // Opcode: VMULv8i8 -/* 11556 */ MCD_OPC_FilterValue, 243, 1, 79, 27, 0, // Skip to: 18553 -/* 11562 */ MCD_OPC_CheckPredicate, 21, 74, 27, 0, // Skip to: 18553 -/* 11567 */ MCD_OPC_Decode, 198, 14, 97, // Opcode: VMULpd -/* 11571 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 11593 -/* 11576 */ MCD_OPC_CheckPredicate, 21, 60, 27, 0, // Skip to: 18553 -/* 11581 */ MCD_OPC_CheckField, 24, 8, 242, 1, 52, 27, 0, // Skip to: 18553 -/* 11589 */ MCD_OPC_Decode, 210, 14, 97, // Opcode: VMULv4i16 -/* 11593 */ MCD_OPC_FilterValue, 2, 43, 27, 0, // Skip to: 18553 -/* 11598 */ MCD_OPC_CheckPredicate, 21, 38, 27, 0, // Skip to: 18553 -/* 11603 */ MCD_OPC_CheckField, 24, 8, 242, 1, 30, 27, 0, // Skip to: 18553 -/* 11611 */ MCD_OPC_Decode, 209, 14, 97, // Opcode: VMULv2i32 -/* 11615 */ MCD_OPC_FilterValue, 10, 117, 0, 0, // Skip to: 11737 -/* 11620 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11623 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11661 -/* 11628 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11631 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11646 -/* 11637 */ MCD_OPC_CheckPredicate, 21, 255, 26, 0, // Skip to: 18553 -/* 11642 */ MCD_OPC_Decode, 163, 15, 97, // Opcode: VPMINs8 -/* 11646 */ MCD_OPC_FilterValue, 243, 1, 245, 26, 0, // Skip to: 18553 -/* 11652 */ MCD_OPC_CheckPredicate, 21, 240, 26, 0, // Skip to: 18553 -/* 11657 */ MCD_OPC_Decode, 166, 15, 97, // Opcode: VPMINu8 -/* 11661 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11699 -/* 11666 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11669 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11684 -/* 11675 */ MCD_OPC_CheckPredicate, 21, 217, 26, 0, // Skip to: 18553 -/* 11680 */ MCD_OPC_Decode, 161, 15, 97, // Opcode: VPMINs16 -/* 11684 */ MCD_OPC_FilterValue, 243, 1, 207, 26, 0, // Skip to: 18553 -/* 11690 */ MCD_OPC_CheckPredicate, 21, 202, 26, 0, // Skip to: 18553 -/* 11695 */ MCD_OPC_Decode, 164, 15, 97, // Opcode: VPMINu16 -/* 11699 */ MCD_OPC_FilterValue, 2, 193, 26, 0, // Skip to: 18553 -/* 11704 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11707 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11722 -/* 11713 */ MCD_OPC_CheckPredicate, 21, 179, 26, 0, // Skip to: 18553 -/* 11718 */ MCD_OPC_Decode, 162, 15, 97, // Opcode: VPMINs32 -/* 11722 */ MCD_OPC_FilterValue, 243, 1, 169, 26, 0, // Skip to: 18553 -/* 11728 */ MCD_OPC_CheckPredicate, 21, 164, 26, 0, // Skip to: 18553 -/* 11733 */ MCD_OPC_Decode, 165, 15, 97, // Opcode: VPMINu32 -/* 11737 */ MCD_OPC_FilterValue, 11, 101, 0, 0, // Skip to: 11843 -/* 11742 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11745 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11767 -/* 11750 */ MCD_OPC_CheckPredicate, 21, 142, 26, 0, // Skip to: 18553 -/* 11755 */ MCD_OPC_CheckField, 24, 8, 242, 1, 134, 26, 0, // Skip to: 18553 -/* 11763 */ MCD_OPC_Decode, 150, 15, 97, // Opcode: VPADDi8 -/* 11767 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11805 -/* 11772 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11775 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11790 -/* 11781 */ MCD_OPC_CheckPredicate, 21, 111, 26, 0, // Skip to: 18553 -/* 11786 */ MCD_OPC_Decode, 148, 15, 97, // Opcode: VPADDi16 -/* 11790 */ MCD_OPC_FilterValue, 243, 1, 101, 26, 0, // Skip to: 18553 -/* 11796 */ MCD_OPC_CheckPredicate, 23, 96, 26, 0, // Skip to: 18553 -/* 11801 */ MCD_OPC_Decode, 229, 15, 105, // Opcode: VQRDMLAHv4i16 -/* 11805 */ MCD_OPC_FilterValue, 2, 87, 26, 0, // Skip to: 18553 -/* 11810 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11813 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11828 -/* 11819 */ MCD_OPC_CheckPredicate, 21, 73, 26, 0, // Skip to: 18553 -/* 11824 */ MCD_OPC_Decode, 149, 15, 97, // Opcode: VPADDi32 -/* 11828 */ MCD_OPC_FilterValue, 243, 1, 63, 26, 0, // Skip to: 18553 -/* 11834 */ MCD_OPC_CheckPredicate, 23, 58, 26, 0, // Skip to: 18553 -/* 11839 */ MCD_OPC_Decode, 228, 15, 105, // Opcode: VQRDMLAHv2i32 -/* 11843 */ MCD_OPC_FilterValue, 12, 123, 0, 0, // Skip to: 11971 -/* 11848 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11851 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11873 -/* 11856 */ MCD_OPC_CheckPredicate, 26, 36, 26, 0, // Skip to: 18553 -/* 11861 */ MCD_OPC_CheckField, 24, 8, 242, 1, 28, 26, 0, // Skip to: 18553 -/* 11869 */ MCD_OPC_Decode, 152, 10, 105, // Opcode: VFMAfd -/* 11873 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11911 -/* 11878 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11881 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11896 -/* 11887 */ MCD_OPC_CheckPredicate, 22, 5, 26, 0, // Skip to: 18553 -/* 11892 */ MCD_OPC_Decode, 154, 10, 105, // Opcode: VFMAhd -/* 11896 */ MCD_OPC_FilterValue, 243, 1, 251, 25, 0, // Skip to: 18553 -/* 11902 */ MCD_OPC_CheckPredicate, 23, 246, 25, 0, // Skip to: 18553 -/* 11907 */ MCD_OPC_Decode, 237, 15, 105, // Opcode: VQRDMLSHv4i16 -/* 11911 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 11949 -/* 11916 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11919 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11934 -/* 11925 */ MCD_OPC_CheckPredicate, 26, 223, 25, 0, // Skip to: 18553 -/* 11930 */ MCD_OPC_Decode, 159, 10, 105, // Opcode: VFMSfd -/* 11934 */ MCD_OPC_FilterValue, 243, 1, 213, 25, 0, // Skip to: 18553 -/* 11940 */ MCD_OPC_CheckPredicate, 23, 208, 25, 0, // Skip to: 18553 -/* 11945 */ MCD_OPC_Decode, 236, 15, 105, // Opcode: VQRDMLSHv2i32 -/* 11949 */ MCD_OPC_FilterValue, 3, 199, 25, 0, // Skip to: 18553 -/* 11954 */ MCD_OPC_CheckPredicate, 22, 194, 25, 0, // Skip to: 18553 -/* 11959 */ MCD_OPC_CheckField, 24, 8, 242, 1, 186, 25, 0, // Skip to: 18553 -/* 11967 */ MCD_OPC_Decode, 161, 10, 105, // Opcode: VFMShd -/* 11971 */ MCD_OPC_FilterValue, 13, 123, 0, 0, // Skip to: 12099 -/* 11976 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11979 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 12017 -/* 11984 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 11987 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 12002 -/* 11993 */ MCD_OPC_CheckPredicate, 21, 155, 25, 0, // Skip to: 18553 -/* 11998 */ MCD_OPC_Decode, 215, 13, 105, // Opcode: VMLAfd -/* 12002 */ MCD_OPC_FilterValue, 243, 1, 145, 25, 0, // Skip to: 18553 -/* 12008 */ MCD_OPC_CheckPredicate, 21, 140, 25, 0, // Skip to: 18553 -/* 12013 */ MCD_OPC_Decode, 194, 14, 97, // Opcode: VMULfd -/* 12017 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 12055 -/* 12022 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 12025 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 12040 -/* 12031 */ MCD_OPC_CheckPredicate, 22, 117, 25, 0, // Skip to: 18553 -/* 12036 */ MCD_OPC_Decode, 217, 13, 105, // Opcode: VMLAhd -/* 12040 */ MCD_OPC_FilterValue, 243, 1, 107, 25, 0, // Skip to: 18553 -/* 12046 */ MCD_OPC_CheckPredicate, 22, 102, 25, 0, // Skip to: 18553 -/* 12051 */ MCD_OPC_Decode, 196, 14, 97, // Opcode: VMULhd -/* 12055 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12077 -/* 12060 */ MCD_OPC_CheckPredicate, 21, 88, 25, 0, // Skip to: 18553 -/* 12065 */ MCD_OPC_CheckField, 24, 8, 242, 1, 80, 25, 0, // Skip to: 18553 -/* 12073 */ MCD_OPC_Decode, 246, 13, 105, // Opcode: VMLSfd -/* 12077 */ MCD_OPC_FilterValue, 3, 71, 25, 0, // Skip to: 18553 -/* 12082 */ MCD_OPC_CheckPredicate, 22, 66, 25, 0, // Skip to: 18553 -/* 12087 */ MCD_OPC_CheckField, 24, 8, 242, 1, 58, 25, 0, // Skip to: 18553 -/* 12095 */ MCD_OPC_Decode, 248, 13, 105, // Opcode: VMLShd -/* 12099 */ MCD_OPC_FilterValue, 14, 91, 0, 0, // Skip to: 12195 -/* 12104 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 12107 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12129 -/* 12112 */ MCD_OPC_CheckPredicate, 21, 36, 25, 0, // Skip to: 18553 -/* 12117 */ MCD_OPC_CheckField, 24, 8, 243, 1, 28, 25, 0, // Skip to: 18553 -/* 12125 */ MCD_OPC_Decode, 227, 7, 97, // Opcode: VACGEfd -/* 12129 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 12151 -/* 12134 */ MCD_OPC_CheckPredicate, 22, 14, 25, 0, // Skip to: 18553 -/* 12139 */ MCD_OPC_CheckField, 24, 8, 243, 1, 6, 25, 0, // Skip to: 18553 -/* 12147 */ MCD_OPC_Decode, 229, 7, 97, // Opcode: VACGEhd -/* 12151 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12173 -/* 12156 */ MCD_OPC_CheckPredicate, 21, 248, 24, 0, // Skip to: 18553 -/* 12161 */ MCD_OPC_CheckField, 24, 8, 243, 1, 240, 24, 0, // Skip to: 18553 -/* 12169 */ MCD_OPC_Decode, 231, 7, 97, // Opcode: VACGTfd -/* 12173 */ MCD_OPC_FilterValue, 3, 231, 24, 0, // Skip to: 18553 -/* 12178 */ MCD_OPC_CheckPredicate, 22, 226, 24, 0, // Skip to: 18553 -/* 12183 */ MCD_OPC_CheckField, 24, 8, 243, 1, 218, 24, 0, // Skip to: 18553 -/* 12191 */ MCD_OPC_Decode, 233, 7, 97, // Opcode: VACGThd -/* 12195 */ MCD_OPC_FilterValue, 15, 209, 24, 0, // Skip to: 18553 -/* 12200 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 12203 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12225 -/* 12208 */ MCD_OPC_CheckPredicate, 21, 196, 24, 0, // Skip to: 18553 -/* 12213 */ MCD_OPC_CheckField, 24, 8, 242, 1, 188, 24, 0, // Skip to: 18553 -/* 12221 */ MCD_OPC_Decode, 219, 16, 97, // Opcode: VRECPSfd -/* 12225 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 12247 -/* 12230 */ MCD_OPC_CheckPredicate, 22, 174, 24, 0, // Skip to: 18553 -/* 12235 */ MCD_OPC_CheckField, 24, 8, 242, 1, 166, 24, 0, // Skip to: 18553 -/* 12243 */ MCD_OPC_Decode, 221, 16, 97, // Opcode: VRECPShd -/* 12247 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12269 -/* 12252 */ MCD_OPC_CheckPredicate, 21, 152, 24, 0, // Skip to: 18553 -/* 12257 */ MCD_OPC_CheckField, 24, 8, 242, 1, 144, 24, 0, // Skip to: 18553 -/* 12265 */ MCD_OPC_Decode, 205, 17, 97, // Opcode: VRSQRTSfd -/* 12269 */ MCD_OPC_FilterValue, 3, 135, 24, 0, // Skip to: 18553 -/* 12274 */ MCD_OPC_CheckPredicate, 22, 130, 24, 0, // Skip to: 18553 -/* 12279 */ MCD_OPC_CheckField, 24, 8, 242, 1, 122, 24, 0, // Skip to: 18553 -/* 12287 */ MCD_OPC_Decode, 207, 17, 97, // Opcode: VRSQRTShd -/* 12291 */ MCD_OPC_FilterValue, 1, 113, 24, 0, // Skip to: 18553 -/* 12296 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 12299 */ MCD_OPC_FilterValue, 0, 209, 7, 0, // Skip to: 14305 -/* 12304 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 12307 */ MCD_OPC_FilterValue, 121, 97, 24, 0, // Skip to: 18553 -/* 12312 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 12315 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 12459 -/* 12320 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 12323 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12421 -/* 12328 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 12331 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12383 -/* 12336 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12339 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12361 -/* 12344 */ MCD_OPC_CheckPredicate, 21, 231, 6, 0, // Skip to: 14116 -/* 12349 */ MCD_OPC_CheckField, 19, 1, 1, 224, 6, 0, // Skip to: 14116 -/* 12356 */ MCD_OPC_Decode, 162, 18, 142, 1, // Opcode: VSHRsv8i8 -/* 12361 */ MCD_OPC_FilterValue, 1, 214, 6, 0, // Skip to: 14116 -/* 12366 */ MCD_OPC_CheckPredicate, 21, 209, 6, 0, // Skip to: 14116 -/* 12371 */ MCD_OPC_CheckField, 19, 1, 1, 202, 6, 0, // Skip to: 14116 -/* 12378 */ MCD_OPC_Decode, 170, 18, 142, 1, // Opcode: VSHRuv8i8 -/* 12383 */ MCD_OPC_FilterValue, 1, 192, 6, 0, // Skip to: 14116 -/* 12388 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12391 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12406 -/* 12396 */ MCD_OPC_CheckPredicate, 21, 179, 6, 0, // Skip to: 14116 -/* 12401 */ MCD_OPC_Decode, 159, 18, 143, 1, // Opcode: VSHRsv4i16 -/* 12406 */ MCD_OPC_FilterValue, 1, 169, 6, 0, // Skip to: 14116 -/* 12411 */ MCD_OPC_CheckPredicate, 21, 164, 6, 0, // Skip to: 14116 -/* 12416 */ MCD_OPC_Decode, 167, 18, 143, 1, // Opcode: VSHRuv4i16 -/* 12421 */ MCD_OPC_FilterValue, 1, 154, 6, 0, // Skip to: 14116 -/* 12426 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12429 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12444 -/* 12434 */ MCD_OPC_CheckPredicate, 21, 141, 6, 0, // Skip to: 14116 -/* 12439 */ MCD_OPC_Decode, 157, 18, 144, 1, // Opcode: VSHRsv2i32 -/* 12444 */ MCD_OPC_FilterValue, 1, 131, 6, 0, // Skip to: 14116 -/* 12449 */ MCD_OPC_CheckPredicate, 21, 126, 6, 0, // Skip to: 14116 -/* 12454 */ MCD_OPC_Decode, 165, 18, 144, 1, // Opcode: VSHRuv2i32 -/* 12459 */ MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 12603 -/* 12464 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 12467 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12565 -/* 12472 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 12475 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12527 -/* 12480 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12483 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12505 -/* 12488 */ MCD_OPC_CheckPredicate, 21, 87, 6, 0, // Skip to: 14116 -/* 12493 */ MCD_OPC_CheckField, 19, 1, 1, 80, 6, 0, // Skip to: 14116 -/* 12500 */ MCD_OPC_Decode, 198, 18, 145, 1, // Opcode: VSRAsv8i8 -/* 12505 */ MCD_OPC_FilterValue, 1, 70, 6, 0, // Skip to: 14116 -/* 12510 */ MCD_OPC_CheckPredicate, 21, 65, 6, 0, // Skip to: 14116 -/* 12515 */ MCD_OPC_CheckField, 19, 1, 1, 58, 6, 0, // Skip to: 14116 -/* 12522 */ MCD_OPC_Decode, 206, 18, 145, 1, // Opcode: VSRAuv8i8 -/* 12527 */ MCD_OPC_FilterValue, 1, 48, 6, 0, // Skip to: 14116 -/* 12532 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12535 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12550 -/* 12540 */ MCD_OPC_CheckPredicate, 21, 35, 6, 0, // Skip to: 14116 -/* 12545 */ MCD_OPC_Decode, 195, 18, 146, 1, // Opcode: VSRAsv4i16 -/* 12550 */ MCD_OPC_FilterValue, 1, 25, 6, 0, // Skip to: 14116 -/* 12555 */ MCD_OPC_CheckPredicate, 21, 20, 6, 0, // Skip to: 14116 -/* 12560 */ MCD_OPC_Decode, 203, 18, 146, 1, // Opcode: VSRAuv4i16 -/* 12565 */ MCD_OPC_FilterValue, 1, 10, 6, 0, // Skip to: 14116 -/* 12570 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12573 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12588 -/* 12578 */ MCD_OPC_CheckPredicate, 21, 253, 5, 0, // Skip to: 14116 -/* 12583 */ MCD_OPC_Decode, 193, 18, 147, 1, // Opcode: VSRAsv2i32 -/* 12588 */ MCD_OPC_FilterValue, 1, 243, 5, 0, // Skip to: 14116 -/* 12593 */ MCD_OPC_CheckPredicate, 21, 238, 5, 0, // Skip to: 14116 -/* 12598 */ MCD_OPC_Decode, 201, 18, 147, 1, // Opcode: VSRAuv2i32 -/* 12603 */ MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 12747 -/* 12608 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 12611 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12709 -/* 12616 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 12619 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12671 -/* 12624 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12627 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12649 -/* 12632 */ MCD_OPC_CheckPredicate, 21, 199, 5, 0, // Skip to: 14116 -/* 12637 */ MCD_OPC_CheckField, 19, 1, 1, 192, 5, 0, // Skip to: 14116 -/* 12644 */ MCD_OPC_Decode, 190, 17, 142, 1, // Opcode: VRSHRsv8i8 -/* 12649 */ MCD_OPC_FilterValue, 1, 182, 5, 0, // Skip to: 14116 -/* 12654 */ MCD_OPC_CheckPredicate, 21, 177, 5, 0, // Skip to: 14116 -/* 12659 */ MCD_OPC_CheckField, 19, 1, 1, 170, 5, 0, // Skip to: 14116 -/* 12666 */ MCD_OPC_Decode, 198, 17, 142, 1, // Opcode: VRSHRuv8i8 -/* 12671 */ MCD_OPC_FilterValue, 1, 160, 5, 0, // Skip to: 14116 -/* 12676 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12679 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12694 -/* 12684 */ MCD_OPC_CheckPredicate, 21, 147, 5, 0, // Skip to: 14116 -/* 12689 */ MCD_OPC_Decode, 187, 17, 143, 1, // Opcode: VRSHRsv4i16 -/* 12694 */ MCD_OPC_FilterValue, 1, 137, 5, 0, // Skip to: 14116 -/* 12699 */ MCD_OPC_CheckPredicate, 21, 132, 5, 0, // Skip to: 14116 -/* 12704 */ MCD_OPC_Decode, 195, 17, 143, 1, // Opcode: VRSHRuv4i16 -/* 12709 */ MCD_OPC_FilterValue, 1, 122, 5, 0, // Skip to: 14116 -/* 12714 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12717 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12732 -/* 12722 */ MCD_OPC_CheckPredicate, 21, 109, 5, 0, // Skip to: 14116 -/* 12727 */ MCD_OPC_Decode, 185, 17, 144, 1, // Opcode: VRSHRsv2i32 -/* 12732 */ MCD_OPC_FilterValue, 1, 99, 5, 0, // Skip to: 14116 -/* 12737 */ MCD_OPC_CheckPredicate, 21, 94, 5, 0, // Skip to: 14116 -/* 12742 */ MCD_OPC_Decode, 193, 17, 144, 1, // Opcode: VRSHRuv2i32 -/* 12747 */ MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 12891 -/* 12752 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 12755 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12853 -/* 12760 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 12763 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12815 -/* 12768 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12771 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12793 -/* 12776 */ MCD_OPC_CheckPredicate, 21, 55, 5, 0, // Skip to: 14116 -/* 12781 */ MCD_OPC_CheckField, 19, 1, 1, 48, 5, 0, // Skip to: 14116 -/* 12788 */ MCD_OPC_Decode, 216, 17, 145, 1, // Opcode: VRSRAsv8i8 -/* 12793 */ MCD_OPC_FilterValue, 1, 38, 5, 0, // Skip to: 14116 -/* 12798 */ MCD_OPC_CheckPredicate, 21, 33, 5, 0, // Skip to: 14116 -/* 12803 */ MCD_OPC_CheckField, 19, 1, 1, 26, 5, 0, // Skip to: 14116 -/* 12810 */ MCD_OPC_Decode, 224, 17, 145, 1, // Opcode: VRSRAuv8i8 -/* 12815 */ MCD_OPC_FilterValue, 1, 16, 5, 0, // Skip to: 14116 -/* 12820 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12823 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12838 -/* 12828 */ MCD_OPC_CheckPredicate, 21, 3, 5, 0, // Skip to: 14116 -/* 12833 */ MCD_OPC_Decode, 213, 17, 146, 1, // Opcode: VRSRAsv4i16 -/* 12838 */ MCD_OPC_FilterValue, 1, 249, 4, 0, // Skip to: 14116 -/* 12843 */ MCD_OPC_CheckPredicate, 21, 244, 4, 0, // Skip to: 14116 -/* 12848 */ MCD_OPC_Decode, 221, 17, 146, 1, // Opcode: VRSRAuv4i16 -/* 12853 */ MCD_OPC_FilterValue, 1, 234, 4, 0, // Skip to: 14116 -/* 12858 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 12861 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12876 -/* 12866 */ MCD_OPC_CheckPredicate, 21, 221, 4, 0, // Skip to: 14116 -/* 12871 */ MCD_OPC_Decode, 211, 17, 147, 1, // Opcode: VRSRAsv2i32 -/* 12876 */ MCD_OPC_FilterValue, 1, 211, 4, 0, // Skip to: 14116 -/* 12881 */ MCD_OPC_CheckPredicate, 21, 206, 4, 0, // Skip to: 14116 -/* 12886 */ MCD_OPC_Decode, 219, 17, 147, 1, // Opcode: VRSRAuv2i32 -/* 12891 */ MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 12980 -/* 12896 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 12899 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 12958 -/* 12904 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 12907 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 12936 -/* 12912 */ MCD_OPC_CheckPredicate, 21, 175, 4, 0, // Skip to: 14116 -/* 12917 */ MCD_OPC_CheckField, 24, 1, 1, 168, 4, 0, // Skip to: 14116 -/* 12924 */ MCD_OPC_CheckField, 19, 1, 1, 161, 4, 0, // Skip to: 14116 -/* 12931 */ MCD_OPC_Decode, 214, 18, 145, 1, // Opcode: VSRIv8i8 -/* 12936 */ MCD_OPC_FilterValue, 1, 151, 4, 0, // Skip to: 14116 -/* 12941 */ MCD_OPC_CheckPredicate, 21, 146, 4, 0, // Skip to: 14116 -/* 12946 */ MCD_OPC_CheckField, 24, 1, 1, 139, 4, 0, // Skip to: 14116 -/* 12953 */ MCD_OPC_Decode, 211, 18, 146, 1, // Opcode: VSRIv4i16 -/* 12958 */ MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 14116 -/* 12963 */ MCD_OPC_CheckPredicate, 21, 124, 4, 0, // Skip to: 14116 -/* 12968 */ MCD_OPC_CheckField, 24, 1, 1, 117, 4, 0, // Skip to: 14116 -/* 12975 */ MCD_OPC_Decode, 209, 18, 147, 1, // Opcode: VSRIv2i32 -/* 12980 */ MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 13124 -/* 12985 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 12988 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13086 -/* 12993 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 12996 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13048 -/* 13001 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13004 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13026 -/* 13009 */ MCD_OPC_CheckPredicate, 21, 78, 4, 0, // Skip to: 14116 -/* 13014 */ MCD_OPC_CheckField, 19, 1, 1, 71, 4, 0, // Skip to: 14116 -/* 13021 */ MCD_OPC_Decode, 135, 18, 148, 1, // Opcode: VSHLiv8i8 -/* 13026 */ MCD_OPC_FilterValue, 1, 61, 4, 0, // Skip to: 14116 -/* 13031 */ MCD_OPC_CheckPredicate, 21, 56, 4, 0, // Skip to: 14116 -/* 13036 */ MCD_OPC_CheckField, 19, 1, 1, 49, 4, 0, // Skip to: 14116 -/* 13043 */ MCD_OPC_Decode, 184, 18, 149, 1, // Opcode: VSLIv8i8 -/* 13048 */ MCD_OPC_FilterValue, 1, 39, 4, 0, // Skip to: 14116 -/* 13053 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13056 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13071 -/* 13061 */ MCD_OPC_CheckPredicate, 21, 26, 4, 0, // Skip to: 14116 -/* 13066 */ MCD_OPC_Decode, 132, 18, 150, 1, // Opcode: VSHLiv4i16 -/* 13071 */ MCD_OPC_FilterValue, 1, 16, 4, 0, // Skip to: 14116 -/* 13076 */ MCD_OPC_CheckPredicate, 21, 11, 4, 0, // Skip to: 14116 -/* 13081 */ MCD_OPC_Decode, 181, 18, 151, 1, // Opcode: VSLIv4i16 -/* 13086 */ MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 14116 -/* 13091 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13094 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13109 -/* 13099 */ MCD_OPC_CheckPredicate, 21, 244, 3, 0, // Skip to: 14116 -/* 13104 */ MCD_OPC_Decode, 130, 18, 152, 1, // Opcode: VSHLiv2i32 -/* 13109 */ MCD_OPC_FilterValue, 1, 234, 3, 0, // Skip to: 14116 -/* 13114 */ MCD_OPC_CheckPredicate, 21, 229, 3, 0, // Skip to: 14116 -/* 13119 */ MCD_OPC_Decode, 179, 18, 153, 1, // Opcode: VSLIv2i32 -/* 13124 */ MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 13213 -/* 13129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 13132 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 13191 -/* 13137 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 13140 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 13169 -/* 13145 */ MCD_OPC_CheckPredicate, 21, 198, 3, 0, // Skip to: 14116 -/* 13150 */ MCD_OPC_CheckField, 24, 1, 1, 191, 3, 0, // Skip to: 14116 -/* 13157 */ MCD_OPC_CheckField, 19, 1, 1, 184, 3, 0, // Skip to: 14116 -/* 13164 */ MCD_OPC_Decode, 160, 16, 148, 1, // Opcode: VQSHLsuv8i8 -/* 13169 */ MCD_OPC_FilterValue, 1, 174, 3, 0, // Skip to: 14116 -/* 13174 */ MCD_OPC_CheckPredicate, 21, 169, 3, 0, // Skip to: 14116 -/* 13179 */ MCD_OPC_CheckField, 24, 1, 1, 162, 3, 0, // Skip to: 14116 -/* 13186 */ MCD_OPC_Decode, 157, 16, 150, 1, // Opcode: VQSHLsuv4i16 -/* 13191 */ MCD_OPC_FilterValue, 1, 152, 3, 0, // Skip to: 14116 -/* 13196 */ MCD_OPC_CheckPredicate, 21, 147, 3, 0, // Skip to: 14116 -/* 13201 */ MCD_OPC_CheckField, 24, 1, 1, 140, 3, 0, // Skip to: 14116 -/* 13208 */ MCD_OPC_Decode, 155, 16, 152, 1, // Opcode: VQSHLsuv2i32 -/* 13213 */ MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 13357 -/* 13218 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 13221 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13319 -/* 13226 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 13229 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13281 -/* 13234 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13237 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13259 -/* 13242 */ MCD_OPC_CheckPredicate, 21, 101, 3, 0, // Skip to: 14116 -/* 13247 */ MCD_OPC_CheckField, 19, 1, 1, 94, 3, 0, // Skip to: 14116 -/* 13254 */ MCD_OPC_Decode, 152, 16, 148, 1, // Opcode: VQSHLsiv8i8 -/* 13259 */ MCD_OPC_FilterValue, 1, 84, 3, 0, // Skip to: 14116 -/* 13264 */ MCD_OPC_CheckPredicate, 21, 79, 3, 0, // Skip to: 14116 -/* 13269 */ MCD_OPC_CheckField, 19, 1, 1, 72, 3, 0, // Skip to: 14116 -/* 13276 */ MCD_OPC_Decode, 176, 16, 148, 1, // Opcode: VQSHLuiv8i8 -/* 13281 */ MCD_OPC_FilterValue, 1, 62, 3, 0, // Skip to: 14116 -/* 13286 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13289 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13304 -/* 13294 */ MCD_OPC_CheckPredicate, 21, 49, 3, 0, // Skip to: 14116 -/* 13299 */ MCD_OPC_Decode, 149, 16, 150, 1, // Opcode: VQSHLsiv4i16 -/* 13304 */ MCD_OPC_FilterValue, 1, 39, 3, 0, // Skip to: 14116 -/* 13309 */ MCD_OPC_CheckPredicate, 21, 34, 3, 0, // Skip to: 14116 -/* 13314 */ MCD_OPC_Decode, 173, 16, 150, 1, // Opcode: VQSHLuiv4i16 -/* 13319 */ MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 14116 -/* 13324 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13327 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13342 -/* 13332 */ MCD_OPC_CheckPredicate, 21, 11, 3, 0, // Skip to: 14116 -/* 13337 */ MCD_OPC_Decode, 147, 16, 152, 1, // Opcode: VQSHLsiv2i32 -/* 13342 */ MCD_OPC_FilterValue, 1, 1, 3, 0, // Skip to: 14116 -/* 13347 */ MCD_OPC_CheckPredicate, 21, 252, 2, 0, // Skip to: 14116 -/* 13352 */ MCD_OPC_Decode, 171, 16, 152, 1, // Opcode: VQSHLuiv2i32 -/* 13357 */ MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 13501 -/* 13362 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 13365 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13463 -/* 13370 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 13373 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13425 -/* 13378 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13381 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13403 -/* 13386 */ MCD_OPC_CheckPredicate, 21, 213, 2, 0, // Skip to: 14116 -/* 13391 */ MCD_OPC_CheckField, 19, 1, 1, 206, 2, 0, // Skip to: 14116 -/* 13398 */ MCD_OPC_Decode, 154, 18, 154, 1, // Opcode: VSHRNv8i8 -/* 13403 */ MCD_OPC_FilterValue, 1, 196, 2, 0, // Skip to: 14116 -/* 13408 */ MCD_OPC_CheckPredicate, 21, 191, 2, 0, // Skip to: 14116 -/* 13413 */ MCD_OPC_CheckField, 19, 1, 1, 184, 2, 0, // Skip to: 14116 -/* 13420 */ MCD_OPC_Decode, 193, 16, 154, 1, // Opcode: VQSHRUNv8i8 -/* 13425 */ MCD_OPC_FilterValue, 1, 174, 2, 0, // Skip to: 14116 -/* 13430 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13433 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13448 -/* 13438 */ MCD_OPC_CheckPredicate, 21, 161, 2, 0, // Skip to: 14116 -/* 13443 */ MCD_OPC_Decode, 153, 18, 155, 1, // Opcode: VSHRNv4i16 -/* 13448 */ MCD_OPC_FilterValue, 1, 151, 2, 0, // Skip to: 14116 -/* 13453 */ MCD_OPC_CheckPredicate, 21, 146, 2, 0, // Skip to: 14116 -/* 13458 */ MCD_OPC_Decode, 192, 16, 155, 1, // Opcode: VQSHRUNv4i16 -/* 13463 */ MCD_OPC_FilterValue, 1, 136, 2, 0, // Skip to: 14116 -/* 13468 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13471 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13486 -/* 13476 */ MCD_OPC_CheckPredicate, 21, 123, 2, 0, // Skip to: 14116 -/* 13481 */ MCD_OPC_Decode, 152, 18, 156, 1, // Opcode: VSHRNv2i32 -/* 13486 */ MCD_OPC_FilterValue, 1, 113, 2, 0, // Skip to: 14116 -/* 13491 */ MCD_OPC_CheckPredicate, 21, 108, 2, 0, // Skip to: 14116 -/* 13496 */ MCD_OPC_Decode, 191, 16, 156, 1, // Opcode: VQSHRUNv2i32 -/* 13501 */ MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 13645 -/* 13506 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 13509 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13607 -/* 13514 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 13517 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13569 -/* 13522 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13525 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13547 -/* 13530 */ MCD_OPC_CheckPredicate, 21, 69, 2, 0, // Skip to: 14116 -/* 13535 */ MCD_OPC_CheckField, 19, 1, 1, 62, 2, 0, // Skip to: 14116 -/* 13542 */ MCD_OPC_Decode, 187, 16, 154, 1, // Opcode: VQSHRNsv8i8 -/* 13547 */ MCD_OPC_FilterValue, 1, 52, 2, 0, // Skip to: 14116 -/* 13552 */ MCD_OPC_CheckPredicate, 21, 47, 2, 0, // Skip to: 14116 -/* 13557 */ MCD_OPC_CheckField, 19, 1, 1, 40, 2, 0, // Skip to: 14116 -/* 13564 */ MCD_OPC_Decode, 190, 16, 154, 1, // Opcode: VQSHRNuv8i8 -/* 13569 */ MCD_OPC_FilterValue, 1, 30, 2, 0, // Skip to: 14116 -/* 13574 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13577 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13592 -/* 13582 */ MCD_OPC_CheckPredicate, 21, 17, 2, 0, // Skip to: 14116 -/* 13587 */ MCD_OPC_Decode, 186, 16, 155, 1, // Opcode: VQSHRNsv4i16 -/* 13592 */ MCD_OPC_FilterValue, 1, 7, 2, 0, // Skip to: 14116 -/* 13597 */ MCD_OPC_CheckPredicate, 21, 2, 2, 0, // Skip to: 14116 -/* 13602 */ MCD_OPC_Decode, 189, 16, 155, 1, // Opcode: VQSHRNuv4i16 -/* 13607 */ MCD_OPC_FilterValue, 1, 248, 1, 0, // Skip to: 14116 -/* 13612 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13615 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13630 -/* 13620 */ MCD_OPC_CheckPredicate, 21, 235, 1, 0, // Skip to: 14116 -/* 13625 */ MCD_OPC_Decode, 185, 16, 156, 1, // Opcode: VQSHRNsv2i32 -/* 13630 */ MCD_OPC_FilterValue, 1, 225, 1, 0, // Skip to: 14116 -/* 13635 */ MCD_OPC_CheckPredicate, 21, 220, 1, 0, // Skip to: 14116 -/* 13640 */ MCD_OPC_Decode, 188, 16, 156, 1, // Opcode: VQSHRNuv2i32 -/* 13645 */ MCD_OPC_FilterValue, 10, 243, 0, 0, // Skip to: 13893 -/* 13650 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 13653 */ MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 13821 -/* 13658 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 13661 */ MCD_OPC_FilterValue, 0, 83, 0, 0, // Skip to: 13749 -/* 13666 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13669 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 13709 -/* 13674 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 13677 */ MCD_OPC_FilterValue, 1, 178, 1, 0, // Skip to: 14116 -/* 13682 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13699 -/* 13687 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 13699 -/* 13694 */ MCD_OPC_Decode, 142, 14, 134, 1, // Opcode: VMOVLsv8i16 -/* 13699 */ MCD_OPC_CheckPredicate, 21, 156, 1, 0, // Skip to: 14116 -/* 13704 */ MCD_OPC_Decode, 252, 17, 157, 1, // Opcode: VSHLLsv8i16 -/* 13709 */ MCD_OPC_FilterValue, 1, 146, 1, 0, // Skip to: 14116 -/* 13714 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 13717 */ MCD_OPC_FilterValue, 1, 138, 1, 0, // Skip to: 14116 -/* 13722 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13739 -/* 13727 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 13739 -/* 13734 */ MCD_OPC_Decode, 145, 14, 134, 1, // Opcode: VMOVLuv8i16 -/* 13739 */ MCD_OPC_CheckPredicate, 21, 116, 1, 0, // Skip to: 14116 -/* 13744 */ MCD_OPC_Decode, 255, 17, 157, 1, // Opcode: VSHLLuv8i16 -/* 13749 */ MCD_OPC_FilterValue, 1, 106, 1, 0, // Skip to: 14116 -/* 13754 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13757 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 13789 -/* 13762 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13779 -/* 13767 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 13779 -/* 13774 */ MCD_OPC_Decode, 141, 14, 134, 1, // Opcode: VMOVLsv4i32 -/* 13779 */ MCD_OPC_CheckPredicate, 21, 76, 1, 0, // Skip to: 14116 -/* 13784 */ MCD_OPC_Decode, 251, 17, 158, 1, // Opcode: VSHLLsv4i32 -/* 13789 */ MCD_OPC_FilterValue, 1, 66, 1, 0, // Skip to: 14116 -/* 13794 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13811 -/* 13799 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 13811 -/* 13806 */ MCD_OPC_Decode, 144, 14, 134, 1, // Opcode: VMOVLuv4i32 -/* 13811 */ MCD_OPC_CheckPredicate, 21, 44, 1, 0, // Skip to: 14116 -/* 13816 */ MCD_OPC_Decode, 254, 17, 158, 1, // Opcode: VSHLLuv4i32 -/* 13821 */ MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 14116 -/* 13826 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13829 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 13861 -/* 13834 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13851 -/* 13839 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 13851 -/* 13846 */ MCD_OPC_Decode, 140, 14, 134, 1, // Opcode: VMOVLsv2i64 -/* 13851 */ MCD_OPC_CheckPredicate, 21, 4, 1, 0, // Skip to: 14116 -/* 13856 */ MCD_OPC_Decode, 250, 17, 159, 1, // Opcode: VSHLLsv2i64 -/* 13861 */ MCD_OPC_FilterValue, 1, 250, 0, 0, // Skip to: 14116 -/* 13866 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13883 -/* 13871 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 13883 -/* 13878 */ MCD_OPC_Decode, 143, 14, 134, 1, // Opcode: VMOVLuv2i64 -/* 13883 */ MCD_OPC_CheckPredicate, 21, 228, 0, 0, // Skip to: 14116 -/* 13888 */ MCD_OPC_Decode, 253, 17, 159, 1, // Opcode: VSHLLuv2i64 -/* 13893 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 13931 -/* 13898 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13901 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13916 -/* 13906 */ MCD_OPC_CheckPredicate, 22, 205, 0, 0, // Skip to: 14116 -/* 13911 */ MCD_OPC_Decode, 247, 9, 160, 1, // Opcode: VCVTxs2hd -/* 13916 */ MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 14116 -/* 13921 */ MCD_OPC_CheckPredicate, 22, 190, 0, 0, // Skip to: 14116 -/* 13926 */ MCD_OPC_Decode, 251, 9, 160, 1, // Opcode: VCVTxu2hd -/* 13931 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 13969 -/* 13936 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 13939 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13954 -/* 13944 */ MCD_OPC_CheckPredicate, 22, 167, 0, 0, // Skip to: 14116 -/* 13949 */ MCD_OPC_Decode, 233, 9, 160, 1, // Opcode: VCVTh2xsd -/* 13954 */ MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 14116 -/* 13959 */ MCD_OPC_CheckPredicate, 22, 152, 0, 0, // Skip to: 14116 -/* 13964 */ MCD_OPC_Decode, 235, 9, 160, 1, // Opcode: VCVTh2xud -/* 13969 */ MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 14054 -/* 13974 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 13977 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13999 -/* 13982 */ MCD_OPC_CheckPredicate, 21, 34, 0, 0, // Skip to: 14021 -/* 13987 */ MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 14021 -/* 13994 */ MCD_OPC_Decode, 165, 14, 161, 1, // Opcode: VMOVv8i8 -/* 13999 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14021 -/* 14004 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14021 -/* 14009 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 14021 -/* 14016 */ MCD_OPC_Decode, 157, 14, 161, 1, // Opcode: VMOVv1i64 -/* 14021 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 14024 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14039 -/* 14029 */ MCD_OPC_CheckPredicate, 21, 82, 0, 0, // Skip to: 14116 -/* 14034 */ MCD_OPC_Decode, 245, 9, 160, 1, // Opcode: VCVTxs2fd -/* 14039 */ MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 14116 -/* 14044 */ MCD_OPC_CheckPredicate, 21, 67, 0, 0, // Skip to: 14116 -/* 14049 */ MCD_OPC_Decode, 249, 9, 160, 1, // Opcode: VCVTxu2fd -/* 14054 */ MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 14116 -/* 14059 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 14062 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14077 -/* 14067 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 14092 -/* 14072 */ MCD_OPC_Decode, 224, 9, 160, 1, // Opcode: VCVTf2xsd -/* 14077 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 14092 -/* 14082 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 14092 -/* 14087 */ MCD_OPC_Decode, 226, 9, 160, 1, // Opcode: VCVTf2xud -/* 14092 */ MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 14116 -/* 14097 */ MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 14116 -/* 14104 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 14116 -/* 14111 */ MCD_OPC_Decode, 158, 14, 161, 1, // Opcode: VMOVv2f32 -/* 14116 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 14119 */ MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 14212 -/* 14124 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... -/* 14127 */ MCD_OPC_FilterValue, 0, 69, 17, 0, // Skip to: 18553 -/* 14132 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 14135 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14157 -/* 14140 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 14202 -/* 14145 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14202 -/* 14152 */ MCD_OPC_Decode, 162, 14, 161, 1, // Opcode: VMOVv4i16 -/* 14157 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14202 -/* 14162 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 14165 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14180 -/* 14170 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 14202 -/* 14175 */ MCD_OPC_Decode, 245, 14, 161, 1, // Opcode: VORRiv2i32 -/* 14180 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14202 -/* 14185 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14202 -/* 14190 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14202 -/* 14197 */ MCD_OPC_Decode, 246, 14, 161, 1, // Opcode: VORRiv4i16 -/* 14202 */ MCD_OPC_CheckPredicate, 21, 250, 16, 0, // Skip to: 18553 -/* 14207 */ MCD_OPC_Decode, 159, 14, 161, 1, // Opcode: VMOVv2i32 -/* 14212 */ MCD_OPC_FilterValue, 1, 240, 16, 0, // Skip to: 18553 -/* 14217 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... -/* 14220 */ MCD_OPC_FilterValue, 0, 232, 16, 0, // Skip to: 18553 -/* 14225 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 14228 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14250 -/* 14233 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 14295 -/* 14238 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14295 -/* 14245 */ MCD_OPC_Decode, 217, 14, 161, 1, // Opcode: VMVNv4i16 -/* 14250 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14295 -/* 14255 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 14258 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14273 -/* 14263 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 14295 -/* 14268 */ MCD_OPC_Decode, 140, 8, 161, 1, // Opcode: VBICiv2i32 -/* 14273 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14295 -/* 14278 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14295 -/* 14283 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14295 -/* 14290 */ MCD_OPC_Decode, 141, 8, 161, 1, // Opcode: VBICiv4i16 -/* 14295 */ MCD_OPC_CheckPredicate, 21, 157, 16, 0, // Skip to: 18553 -/* 14300 */ MCD_OPC_Decode, 216, 14, 161, 1, // Opcode: VMVNv2i32 -/* 14305 */ MCD_OPC_FilterValue, 1, 147, 16, 0, // Skip to: 18553 -/* 14310 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 14313 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 14353 -/* 14318 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14321 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14337 -/* 14327 */ MCD_OPC_CheckPredicate, 21, 125, 16, 0, // Skip to: 18553 -/* 14332 */ MCD_OPC_Decode, 156, 18, 162, 1, // Opcode: VSHRsv1i64 -/* 14337 */ MCD_OPC_FilterValue, 243, 1, 114, 16, 0, // Skip to: 18553 -/* 14343 */ MCD_OPC_CheckPredicate, 21, 109, 16, 0, // Skip to: 18553 -/* 14348 */ MCD_OPC_Decode, 164, 18, 162, 1, // Opcode: VSHRuv1i64 -/* 14353 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 14393 -/* 14358 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14361 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14377 -/* 14367 */ MCD_OPC_CheckPredicate, 21, 85, 16, 0, // Skip to: 18553 -/* 14372 */ MCD_OPC_Decode, 192, 18, 163, 1, // Opcode: VSRAsv1i64 -/* 14377 */ MCD_OPC_FilterValue, 243, 1, 74, 16, 0, // Skip to: 18553 -/* 14383 */ MCD_OPC_CheckPredicate, 21, 69, 16, 0, // Skip to: 18553 -/* 14388 */ MCD_OPC_Decode, 200, 18, 163, 1, // Opcode: VSRAuv1i64 -/* 14393 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 14433 -/* 14398 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14401 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14417 -/* 14407 */ MCD_OPC_CheckPredicate, 21, 45, 16, 0, // Skip to: 18553 -/* 14412 */ MCD_OPC_Decode, 184, 17, 162, 1, // Opcode: VRSHRsv1i64 -/* 14417 */ MCD_OPC_FilterValue, 243, 1, 34, 16, 0, // Skip to: 18553 -/* 14423 */ MCD_OPC_CheckPredicate, 21, 29, 16, 0, // Skip to: 18553 -/* 14428 */ MCD_OPC_Decode, 192, 17, 162, 1, // Opcode: VRSHRuv1i64 -/* 14433 */ MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 14473 -/* 14438 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14441 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14457 -/* 14447 */ MCD_OPC_CheckPredicate, 21, 5, 16, 0, // Skip to: 18553 -/* 14452 */ MCD_OPC_Decode, 210, 17, 163, 1, // Opcode: VRSRAsv1i64 -/* 14457 */ MCD_OPC_FilterValue, 243, 1, 250, 15, 0, // Skip to: 18553 -/* 14463 */ MCD_OPC_CheckPredicate, 21, 245, 15, 0, // Skip to: 18553 -/* 14468 */ MCD_OPC_Decode, 218, 17, 163, 1, // Opcode: VRSRAuv1i64 -/* 14473 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 14496 -/* 14478 */ MCD_OPC_CheckPredicate, 21, 230, 15, 0, // Skip to: 18553 -/* 14483 */ MCD_OPC_CheckField, 24, 8, 243, 1, 222, 15, 0, // Skip to: 18553 -/* 14491 */ MCD_OPC_Decode, 208, 18, 163, 1, // Opcode: VSRIv1i64 -/* 14496 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 14536 -/* 14501 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14504 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14520 -/* 14510 */ MCD_OPC_CheckPredicate, 21, 198, 15, 0, // Skip to: 18553 -/* 14515 */ MCD_OPC_Decode, 129, 18, 164, 1, // Opcode: VSHLiv1i64 -/* 14520 */ MCD_OPC_FilterValue, 243, 1, 187, 15, 0, // Skip to: 18553 -/* 14526 */ MCD_OPC_CheckPredicate, 21, 182, 15, 0, // Skip to: 18553 -/* 14531 */ MCD_OPC_Decode, 178, 18, 165, 1, // Opcode: VSLIv1i64 -/* 14536 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 14559 -/* 14541 */ MCD_OPC_CheckPredicate, 21, 167, 15, 0, // Skip to: 18553 -/* 14546 */ MCD_OPC_CheckField, 24, 8, 243, 1, 159, 15, 0, // Skip to: 18553 -/* 14554 */ MCD_OPC_Decode, 154, 16, 164, 1, // Opcode: VQSHLsuv1i64 -/* 14559 */ MCD_OPC_FilterValue, 7, 149, 15, 0, // Skip to: 18553 -/* 14564 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14567 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14583 -/* 14573 */ MCD_OPC_CheckPredicate, 21, 135, 15, 0, // Skip to: 18553 -/* 14578 */ MCD_OPC_Decode, 146, 16, 164, 1, // Opcode: VQSHLsiv1i64 -/* 14583 */ MCD_OPC_FilterValue, 243, 1, 124, 15, 0, // Skip to: 18553 -/* 14589 */ MCD_OPC_CheckPredicate, 21, 119, 15, 0, // Skip to: 18553 -/* 14594 */ MCD_OPC_Decode, 170, 16, 164, 1, // Opcode: VQSHLuiv1i64 -/* 14599 */ MCD_OPC_FilterValue, 1, 109, 15, 0, // Skip to: 18553 -/* 14604 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 14607 */ MCD_OPC_FilterValue, 0, 89, 7, 0, // Skip to: 16493 -/* 14612 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 14615 */ MCD_OPC_FilterValue, 0, 155, 0, 0, // Skip to: 14775 -/* 14620 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 14623 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14661 -/* 14628 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14631 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14646 -/* 14637 */ MCD_OPC_CheckPredicate, 21, 71, 15, 0, // Skip to: 18553 -/* 14642 */ MCD_OPC_Decode, 173, 15, 98, // Opcode: VQADDsv16i8 -/* 14646 */ MCD_OPC_FilterValue, 243, 1, 61, 15, 0, // Skip to: 18553 -/* 14652 */ MCD_OPC_CheckPredicate, 21, 56, 15, 0, // Skip to: 18553 -/* 14657 */ MCD_OPC_Decode, 181, 15, 98, // Opcode: VQADDuv16i8 -/* 14661 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 14699 -/* 14666 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14669 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14684 -/* 14675 */ MCD_OPC_CheckPredicate, 21, 33, 15, 0, // Skip to: 18553 -/* 14680 */ MCD_OPC_Decode, 179, 15, 98, // Opcode: VQADDsv8i16 -/* 14684 */ MCD_OPC_FilterValue, 243, 1, 23, 15, 0, // Skip to: 18553 -/* 14690 */ MCD_OPC_CheckPredicate, 21, 18, 15, 0, // Skip to: 18553 -/* 14695 */ MCD_OPC_Decode, 187, 15, 98, // Opcode: VQADDuv8i16 -/* 14699 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 14737 -/* 14704 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14707 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14722 -/* 14713 */ MCD_OPC_CheckPredicate, 21, 251, 14, 0, // Skip to: 18553 -/* 14718 */ MCD_OPC_Decode, 178, 15, 98, // Opcode: VQADDsv4i32 -/* 14722 */ MCD_OPC_FilterValue, 243, 1, 241, 14, 0, // Skip to: 18553 -/* 14728 */ MCD_OPC_CheckPredicate, 21, 236, 14, 0, // Skip to: 18553 -/* 14733 */ MCD_OPC_Decode, 186, 15, 98, // Opcode: VQADDuv4i32 -/* 14737 */ MCD_OPC_FilterValue, 3, 227, 14, 0, // Skip to: 18553 -/* 14742 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14745 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14760 -/* 14751 */ MCD_OPC_CheckPredicate, 21, 213, 14, 0, // Skip to: 18553 -/* 14756 */ MCD_OPC_Decode, 176, 15, 98, // Opcode: VQADDsv2i64 -/* 14760 */ MCD_OPC_FilterValue, 243, 1, 203, 14, 0, // Skip to: 18553 -/* 14766 */ MCD_OPC_CheckPredicate, 21, 198, 14, 0, // Skip to: 18553 -/* 14771 */ MCD_OPC_Decode, 184, 15, 98, // Opcode: VQADDuv2i64 -/* 14775 */ MCD_OPC_FilterValue, 1, 155, 0, 0, // Skip to: 14935 -/* 14780 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 14783 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14821 -/* 14788 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14791 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14806 -/* 14797 */ MCD_OPC_CheckPredicate, 21, 167, 14, 0, // Skip to: 18553 -/* 14802 */ MCD_OPC_Decode, 138, 8, 98, // Opcode: VANDq -/* 14806 */ MCD_OPC_FilterValue, 243, 1, 157, 14, 0, // Skip to: 18553 -/* 14812 */ MCD_OPC_CheckPredicate, 21, 152, 14, 0, // Skip to: 18553 -/* 14817 */ MCD_OPC_Decode, 141, 10, 98, // Opcode: VEORq -/* 14821 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 14859 -/* 14826 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14829 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14844 -/* 14835 */ MCD_OPC_CheckPredicate, 21, 129, 14, 0, // Skip to: 18553 -/* 14840 */ MCD_OPC_Decode, 144, 8, 98, // Opcode: VBICq -/* 14844 */ MCD_OPC_FilterValue, 243, 1, 119, 14, 0, // Skip to: 18553 -/* 14850 */ MCD_OPC_CheckPredicate, 21, 114, 14, 0, // Skip to: 18553 -/* 14855 */ MCD_OPC_Decode, 150, 8, 106, // Opcode: VBSLq -/* 14859 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 14897 -/* 14864 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14867 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14882 -/* 14873 */ MCD_OPC_CheckPredicate, 21, 91, 14, 0, // Skip to: 18553 -/* 14878 */ MCD_OPC_Decode, 249, 14, 98, // Opcode: VORRq -/* 14882 */ MCD_OPC_FilterValue, 243, 1, 81, 14, 0, // Skip to: 18553 -/* 14888 */ MCD_OPC_CheckPredicate, 21, 76, 14, 0, // Skip to: 18553 -/* 14893 */ MCD_OPC_Decode, 148, 8, 106, // Opcode: VBITq -/* 14897 */ MCD_OPC_FilterValue, 3, 67, 14, 0, // Skip to: 18553 -/* 14902 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14905 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14920 -/* 14911 */ MCD_OPC_CheckPredicate, 21, 53, 14, 0, // Skip to: 18553 -/* 14916 */ MCD_OPC_Decode, 243, 14, 98, // Opcode: VORNq -/* 14920 */ MCD_OPC_FilterValue, 243, 1, 43, 14, 0, // Skip to: 18553 -/* 14926 */ MCD_OPC_CheckPredicate, 21, 38, 14, 0, // Skip to: 18553 -/* 14931 */ MCD_OPC_Decode, 146, 8, 106, // Opcode: VBIFq -/* 14935 */ MCD_OPC_FilterValue, 2, 155, 0, 0, // Skip to: 15095 -/* 14940 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 14943 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14981 -/* 14948 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14951 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14966 -/* 14957 */ MCD_OPC_CheckPredicate, 21, 7, 14, 0, // Skip to: 18553 -/* 14962 */ MCD_OPC_Decode, 194, 16, 98, // Opcode: VQSUBsv16i8 -/* 14966 */ MCD_OPC_FilterValue, 243, 1, 253, 13, 0, // Skip to: 18553 -/* 14972 */ MCD_OPC_CheckPredicate, 21, 248, 13, 0, // Skip to: 18553 -/* 14977 */ MCD_OPC_Decode, 202, 16, 98, // Opcode: VQSUBuv16i8 -/* 14981 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15019 -/* 14986 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 14989 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15004 -/* 14995 */ MCD_OPC_CheckPredicate, 21, 225, 13, 0, // Skip to: 18553 -/* 15000 */ MCD_OPC_Decode, 200, 16, 98, // Opcode: VQSUBsv8i16 -/* 15004 */ MCD_OPC_FilterValue, 243, 1, 215, 13, 0, // Skip to: 18553 -/* 15010 */ MCD_OPC_CheckPredicate, 21, 210, 13, 0, // Skip to: 18553 -/* 15015 */ MCD_OPC_Decode, 208, 16, 98, // Opcode: VQSUBuv8i16 -/* 15019 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15057 -/* 15024 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15027 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15042 -/* 15033 */ MCD_OPC_CheckPredicate, 21, 187, 13, 0, // Skip to: 18553 -/* 15038 */ MCD_OPC_Decode, 199, 16, 98, // Opcode: VQSUBsv4i32 -/* 15042 */ MCD_OPC_FilterValue, 243, 1, 177, 13, 0, // Skip to: 18553 -/* 15048 */ MCD_OPC_CheckPredicate, 21, 172, 13, 0, // Skip to: 18553 -/* 15053 */ MCD_OPC_Decode, 207, 16, 98, // Opcode: VQSUBuv4i32 -/* 15057 */ MCD_OPC_FilterValue, 3, 163, 13, 0, // Skip to: 18553 -/* 15062 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15065 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15080 -/* 15071 */ MCD_OPC_CheckPredicate, 21, 149, 13, 0, // Skip to: 18553 -/* 15076 */ MCD_OPC_Decode, 197, 16, 98, // Opcode: VQSUBsv2i64 -/* 15080 */ MCD_OPC_FilterValue, 243, 1, 139, 13, 0, // Skip to: 18553 -/* 15086 */ MCD_OPC_CheckPredicate, 21, 134, 13, 0, // Skip to: 18553 -/* 15091 */ MCD_OPC_Decode, 205, 16, 98, // Opcode: VQSUBuv2i64 -/* 15095 */ MCD_OPC_FilterValue, 3, 117, 0, 0, // Skip to: 15217 -/* 15100 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 15103 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15141 -/* 15108 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15111 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15126 -/* 15117 */ MCD_OPC_CheckPredicate, 21, 103, 13, 0, // Skip to: 18553 -/* 15122 */ MCD_OPC_Decode, 179, 8, 98, // Opcode: VCGEsv16i8 -/* 15126 */ MCD_OPC_FilterValue, 243, 1, 93, 13, 0, // Skip to: 18553 -/* 15132 */ MCD_OPC_CheckPredicate, 21, 88, 13, 0, // Skip to: 18553 -/* 15137 */ MCD_OPC_Decode, 185, 8, 98, // Opcode: VCGEuv16i8 -/* 15141 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15179 -/* 15146 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15149 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15164 -/* 15155 */ MCD_OPC_CheckPredicate, 21, 65, 13, 0, // Skip to: 18553 -/* 15160 */ MCD_OPC_Decode, 183, 8, 98, // Opcode: VCGEsv8i16 -/* 15164 */ MCD_OPC_FilterValue, 243, 1, 55, 13, 0, // Skip to: 18553 -/* 15170 */ MCD_OPC_CheckPredicate, 21, 50, 13, 0, // Skip to: 18553 -/* 15175 */ MCD_OPC_Decode, 189, 8, 98, // Opcode: VCGEuv8i16 -/* 15179 */ MCD_OPC_FilterValue, 2, 41, 13, 0, // Skip to: 18553 -/* 15184 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15187 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15202 -/* 15193 */ MCD_OPC_CheckPredicate, 21, 27, 13, 0, // Skip to: 18553 -/* 15198 */ MCD_OPC_Decode, 182, 8, 98, // Opcode: VCGEsv4i32 -/* 15202 */ MCD_OPC_FilterValue, 243, 1, 17, 13, 0, // Skip to: 18553 -/* 15208 */ MCD_OPC_CheckPredicate, 21, 12, 13, 0, // Skip to: 18553 -/* 15213 */ MCD_OPC_Decode, 188, 8, 98, // Opcode: VCGEuv4i32 -/* 15217 */ MCD_OPC_FilterValue, 4, 155, 0, 0, // Skip to: 15377 -/* 15222 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 15225 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15263 -/* 15230 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15233 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15248 -/* 15239 */ MCD_OPC_CheckPredicate, 21, 237, 12, 0, // Skip to: 18553 -/* 15244 */ MCD_OPC_Decode, 161, 16, 102, // Opcode: VQSHLsv16i8 -/* 15248 */ MCD_OPC_FilterValue, 243, 1, 227, 12, 0, // Skip to: 18553 -/* 15254 */ MCD_OPC_CheckPredicate, 21, 222, 12, 0, // Skip to: 18553 -/* 15259 */ MCD_OPC_Decode, 177, 16, 102, // Opcode: VQSHLuv16i8 -/* 15263 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15301 -/* 15268 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15271 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15286 -/* 15277 */ MCD_OPC_CheckPredicate, 21, 199, 12, 0, // Skip to: 18553 -/* 15282 */ MCD_OPC_Decode, 167, 16, 102, // Opcode: VQSHLsv8i16 -/* 15286 */ MCD_OPC_FilterValue, 243, 1, 189, 12, 0, // Skip to: 18553 -/* 15292 */ MCD_OPC_CheckPredicate, 21, 184, 12, 0, // Skip to: 18553 -/* 15297 */ MCD_OPC_Decode, 183, 16, 102, // Opcode: VQSHLuv8i16 -/* 15301 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15339 -/* 15306 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15309 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15324 -/* 15315 */ MCD_OPC_CheckPredicate, 21, 161, 12, 0, // Skip to: 18553 -/* 15320 */ MCD_OPC_Decode, 166, 16, 102, // Opcode: VQSHLsv4i32 -/* 15324 */ MCD_OPC_FilterValue, 243, 1, 151, 12, 0, // Skip to: 18553 -/* 15330 */ MCD_OPC_CheckPredicate, 21, 146, 12, 0, // Skip to: 18553 -/* 15335 */ MCD_OPC_Decode, 182, 16, 102, // Opcode: VQSHLuv4i32 -/* 15339 */ MCD_OPC_FilterValue, 3, 137, 12, 0, // Skip to: 18553 -/* 15344 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15347 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15362 -/* 15353 */ MCD_OPC_CheckPredicate, 21, 123, 12, 0, // Skip to: 18553 -/* 15358 */ MCD_OPC_Decode, 164, 16, 102, // Opcode: VQSHLsv2i64 -/* 15362 */ MCD_OPC_FilterValue, 243, 1, 113, 12, 0, // Skip to: 18553 -/* 15368 */ MCD_OPC_CheckPredicate, 21, 108, 12, 0, // Skip to: 18553 -/* 15373 */ MCD_OPC_Decode, 180, 16, 102, // Opcode: VQSHLuv2i64 -/* 15377 */ MCD_OPC_FilterValue, 5, 155, 0, 0, // Skip to: 15537 -/* 15382 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 15385 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15423 -/* 15390 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15393 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15408 -/* 15399 */ MCD_OPC_CheckPredicate, 21, 77, 12, 0, // Skip to: 18553 -/* 15404 */ MCD_OPC_Decode, 248, 15, 102, // Opcode: VQRSHLsv16i8 -/* 15408 */ MCD_OPC_FilterValue, 243, 1, 67, 12, 0, // Skip to: 18553 -/* 15414 */ MCD_OPC_CheckPredicate, 21, 62, 12, 0, // Skip to: 18553 -/* 15419 */ MCD_OPC_Decode, 128, 16, 102, // Opcode: VQRSHLuv16i8 -/* 15423 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15461 -/* 15428 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15431 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15446 -/* 15437 */ MCD_OPC_CheckPredicate, 21, 39, 12, 0, // Skip to: 18553 -/* 15442 */ MCD_OPC_Decode, 254, 15, 102, // Opcode: VQRSHLsv8i16 -/* 15446 */ MCD_OPC_FilterValue, 243, 1, 29, 12, 0, // Skip to: 18553 -/* 15452 */ MCD_OPC_CheckPredicate, 21, 24, 12, 0, // Skip to: 18553 -/* 15457 */ MCD_OPC_Decode, 134, 16, 102, // Opcode: VQRSHLuv8i16 -/* 15461 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15499 -/* 15466 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15469 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15484 -/* 15475 */ MCD_OPC_CheckPredicate, 21, 1, 12, 0, // Skip to: 18553 -/* 15480 */ MCD_OPC_Decode, 253, 15, 102, // Opcode: VQRSHLsv4i32 -/* 15484 */ MCD_OPC_FilterValue, 243, 1, 247, 11, 0, // Skip to: 18553 -/* 15490 */ MCD_OPC_CheckPredicate, 21, 242, 11, 0, // Skip to: 18553 -/* 15495 */ MCD_OPC_Decode, 133, 16, 102, // Opcode: VQRSHLuv4i32 -/* 15499 */ MCD_OPC_FilterValue, 3, 233, 11, 0, // Skip to: 18553 -/* 15504 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15507 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15522 -/* 15513 */ MCD_OPC_CheckPredicate, 21, 219, 11, 0, // Skip to: 18553 -/* 15518 */ MCD_OPC_Decode, 251, 15, 102, // Opcode: VQRSHLsv2i64 -/* 15522 */ MCD_OPC_FilterValue, 243, 1, 209, 11, 0, // Skip to: 18553 -/* 15528 */ MCD_OPC_CheckPredicate, 21, 204, 11, 0, // Skip to: 18553 -/* 15533 */ MCD_OPC_Decode, 131, 16, 102, // Opcode: VQRSHLuv2i64 -/* 15537 */ MCD_OPC_FilterValue, 6, 117, 0, 0, // Skip to: 15659 -/* 15542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 15545 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15583 -/* 15550 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15553 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15568 -/* 15559 */ MCD_OPC_CheckPredicate, 21, 173, 11, 0, // Skip to: 18553 -/* 15564 */ MCD_OPC_Decode, 190, 13, 98, // Opcode: VMINsv16i8 -/* 15568 */ MCD_OPC_FilterValue, 243, 1, 163, 11, 0, // Skip to: 18553 -/* 15574 */ MCD_OPC_CheckPredicate, 21, 158, 11, 0, // Skip to: 18553 -/* 15579 */ MCD_OPC_Decode, 196, 13, 98, // Opcode: VMINuv16i8 -/* 15583 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15621 -/* 15588 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15591 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15606 -/* 15597 */ MCD_OPC_CheckPredicate, 21, 135, 11, 0, // Skip to: 18553 -/* 15602 */ MCD_OPC_Decode, 194, 13, 98, // Opcode: VMINsv8i16 -/* 15606 */ MCD_OPC_FilterValue, 243, 1, 125, 11, 0, // Skip to: 18553 -/* 15612 */ MCD_OPC_CheckPredicate, 21, 120, 11, 0, // Skip to: 18553 -/* 15617 */ MCD_OPC_Decode, 200, 13, 98, // Opcode: VMINuv8i16 -/* 15621 */ MCD_OPC_FilterValue, 2, 111, 11, 0, // Skip to: 18553 -/* 15626 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15629 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15644 -/* 15635 */ MCD_OPC_CheckPredicate, 21, 97, 11, 0, // Skip to: 18553 -/* 15640 */ MCD_OPC_Decode, 193, 13, 98, // Opcode: VMINsv4i32 -/* 15644 */ MCD_OPC_FilterValue, 243, 1, 87, 11, 0, // Skip to: 18553 -/* 15650 */ MCD_OPC_CheckPredicate, 21, 82, 11, 0, // Skip to: 18553 -/* 15655 */ MCD_OPC_Decode, 199, 13, 98, // Opcode: VMINuv4i32 -/* 15659 */ MCD_OPC_FilterValue, 7, 117, 0, 0, // Skip to: 15781 -/* 15664 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 15667 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15705 -/* 15672 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15675 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15690 -/* 15681 */ MCD_OPC_CheckPredicate, 21, 51, 11, 0, // Skip to: 18553 -/* 15686 */ MCD_OPC_Decode, 180, 7, 106, // Opcode: VABAsv16i8 -/* 15690 */ MCD_OPC_FilterValue, 243, 1, 41, 11, 0, // Skip to: 18553 -/* 15696 */ MCD_OPC_CheckPredicate, 21, 36, 11, 0, // Skip to: 18553 -/* 15701 */ MCD_OPC_Decode, 186, 7, 106, // Opcode: VABAuv16i8 -/* 15705 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15743 -/* 15710 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15713 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15728 -/* 15719 */ MCD_OPC_CheckPredicate, 21, 13, 11, 0, // Skip to: 18553 -/* 15724 */ MCD_OPC_Decode, 184, 7, 106, // Opcode: VABAsv8i16 -/* 15728 */ MCD_OPC_FilterValue, 243, 1, 3, 11, 0, // Skip to: 18553 -/* 15734 */ MCD_OPC_CheckPredicate, 21, 254, 10, 0, // Skip to: 18553 -/* 15739 */ MCD_OPC_Decode, 190, 7, 106, // Opcode: VABAuv8i16 -/* 15743 */ MCD_OPC_FilterValue, 2, 245, 10, 0, // Skip to: 18553 -/* 15748 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15751 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15766 -/* 15757 */ MCD_OPC_CheckPredicate, 21, 231, 10, 0, // Skip to: 18553 -/* 15762 */ MCD_OPC_Decode, 183, 7, 106, // Opcode: VABAsv4i32 -/* 15766 */ MCD_OPC_FilterValue, 243, 1, 221, 10, 0, // Skip to: 18553 -/* 15772 */ MCD_OPC_CheckPredicate, 21, 216, 10, 0, // Skip to: 18553 -/* 15777 */ MCD_OPC_Decode, 189, 7, 106, // Opcode: VABAuv4i32 -/* 15781 */ MCD_OPC_FilterValue, 8, 117, 0, 0, // Skip to: 15903 -/* 15786 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 15789 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15827 -/* 15794 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15797 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15812 -/* 15803 */ MCD_OPC_CheckPredicate, 21, 185, 10, 0, // Skip to: 18553 -/* 15808 */ MCD_OPC_Decode, 153, 21, 98, // Opcode: VTSTv16i8 -/* 15812 */ MCD_OPC_FilterValue, 243, 1, 175, 10, 0, // Skip to: 18553 -/* 15818 */ MCD_OPC_CheckPredicate, 21, 170, 10, 0, // Skip to: 18553 -/* 15823 */ MCD_OPC_Decode, 159, 8, 98, // Opcode: VCEQv16i8 -/* 15827 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15865 -/* 15832 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15835 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15850 -/* 15841 */ MCD_OPC_CheckPredicate, 21, 147, 10, 0, // Skip to: 18553 -/* 15846 */ MCD_OPC_Decode, 157, 21, 98, // Opcode: VTSTv8i16 -/* 15850 */ MCD_OPC_FilterValue, 243, 1, 137, 10, 0, // Skip to: 18553 -/* 15856 */ MCD_OPC_CheckPredicate, 21, 132, 10, 0, // Skip to: 18553 -/* 15861 */ MCD_OPC_Decode, 163, 8, 98, // Opcode: VCEQv8i16 -/* 15865 */ MCD_OPC_FilterValue, 2, 123, 10, 0, // Skip to: 18553 -/* 15870 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15873 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15888 -/* 15879 */ MCD_OPC_CheckPredicate, 21, 109, 10, 0, // Skip to: 18553 -/* 15884 */ MCD_OPC_Decode, 156, 21, 98, // Opcode: VTSTv4i32 -/* 15888 */ MCD_OPC_FilterValue, 243, 1, 99, 10, 0, // Skip to: 18553 -/* 15894 */ MCD_OPC_CheckPredicate, 21, 94, 10, 0, // Skip to: 18553 -/* 15899 */ MCD_OPC_Decode, 162, 8, 98, // Opcode: VCEQv4i32 -/* 15903 */ MCD_OPC_FilterValue, 9, 85, 0, 0, // Skip to: 15993 -/* 15908 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 15911 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15949 -/* 15916 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 15919 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15934 -/* 15925 */ MCD_OPC_CheckPredicate, 21, 63, 10, 0, // Skip to: 18553 -/* 15930 */ MCD_OPC_Decode, 208, 14, 98, // Opcode: VMULv16i8 -/* 15934 */ MCD_OPC_FilterValue, 243, 1, 53, 10, 0, // Skip to: 18553 -/* 15940 */ MCD_OPC_CheckPredicate, 21, 48, 10, 0, // Skip to: 18553 -/* 15945 */ MCD_OPC_Decode, 199, 14, 98, // Opcode: VMULpq -/* 15949 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 15971 -/* 15954 */ MCD_OPC_CheckPredicate, 21, 34, 10, 0, // Skip to: 18553 -/* 15959 */ MCD_OPC_CheckField, 24, 8, 242, 1, 26, 10, 0, // Skip to: 18553 -/* 15967 */ MCD_OPC_Decode, 212, 14, 98, // Opcode: VMULv8i16 -/* 15971 */ MCD_OPC_FilterValue, 2, 17, 10, 0, // Skip to: 18553 -/* 15976 */ MCD_OPC_CheckPredicate, 21, 12, 10, 0, // Skip to: 18553 -/* 15981 */ MCD_OPC_CheckField, 24, 8, 242, 1, 4, 10, 0, // Skip to: 18553 -/* 15989 */ MCD_OPC_Decode, 211, 14, 98, // Opcode: VMULv4i32 -/* 15993 */ MCD_OPC_FilterValue, 11, 47, 0, 0, // Skip to: 16045 -/* 15998 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 16001 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16023 -/* 16006 */ MCD_OPC_CheckPredicate, 23, 238, 9, 0, // Skip to: 18553 -/* 16011 */ MCD_OPC_CheckField, 24, 8, 243, 1, 230, 9, 0, // Skip to: 18553 -/* 16019 */ MCD_OPC_Decode, 231, 15, 106, // Opcode: VQRDMLAHv8i16 -/* 16023 */ MCD_OPC_FilterValue, 2, 221, 9, 0, // Skip to: 18553 -/* 16028 */ MCD_OPC_CheckPredicate, 23, 216, 9, 0, // Skip to: 18553 -/* 16033 */ MCD_OPC_CheckField, 24, 8, 243, 1, 208, 9, 0, // Skip to: 18553 -/* 16041 */ MCD_OPC_Decode, 230, 15, 106, // Opcode: VQRDMLAHv4i32 -/* 16045 */ MCD_OPC_FilterValue, 12, 123, 0, 0, // Skip to: 16173 -/* 16050 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 16053 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16075 -/* 16058 */ MCD_OPC_CheckPredicate, 26, 186, 9, 0, // Skip to: 18553 -/* 16063 */ MCD_OPC_CheckField, 24, 8, 242, 1, 178, 9, 0, // Skip to: 18553 -/* 16071 */ MCD_OPC_Decode, 153, 10, 106, // Opcode: VFMAfq -/* 16075 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16113 -/* 16080 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 16083 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16098 -/* 16089 */ MCD_OPC_CheckPredicate, 22, 155, 9, 0, // Skip to: 18553 -/* 16094 */ MCD_OPC_Decode, 155, 10, 106, // Opcode: VFMAhq -/* 16098 */ MCD_OPC_FilterValue, 243, 1, 145, 9, 0, // Skip to: 18553 -/* 16104 */ MCD_OPC_CheckPredicate, 23, 140, 9, 0, // Skip to: 18553 -/* 16109 */ MCD_OPC_Decode, 239, 15, 106, // Opcode: VQRDMLSHv8i16 -/* 16113 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 16151 -/* 16118 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 16121 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16136 -/* 16127 */ MCD_OPC_CheckPredicate, 26, 117, 9, 0, // Skip to: 18553 -/* 16132 */ MCD_OPC_Decode, 160, 10, 106, // Opcode: VFMSfq -/* 16136 */ MCD_OPC_FilterValue, 243, 1, 107, 9, 0, // Skip to: 18553 -/* 16142 */ MCD_OPC_CheckPredicate, 23, 102, 9, 0, // Skip to: 18553 -/* 16147 */ MCD_OPC_Decode, 238, 15, 106, // Opcode: VQRDMLSHv4i32 -/* 16151 */ MCD_OPC_FilterValue, 3, 93, 9, 0, // Skip to: 18553 -/* 16156 */ MCD_OPC_CheckPredicate, 22, 88, 9, 0, // Skip to: 18553 -/* 16161 */ MCD_OPC_CheckField, 24, 8, 242, 1, 80, 9, 0, // Skip to: 18553 -/* 16169 */ MCD_OPC_Decode, 162, 10, 106, // Opcode: VFMShq -/* 16173 */ MCD_OPC_FilterValue, 13, 123, 0, 0, // Skip to: 16301 -/* 16178 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 16181 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 16219 -/* 16186 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 16189 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16204 -/* 16195 */ MCD_OPC_CheckPredicate, 21, 49, 9, 0, // Skip to: 18553 -/* 16200 */ MCD_OPC_Decode, 216, 13, 106, // Opcode: VMLAfq -/* 16204 */ MCD_OPC_FilterValue, 243, 1, 39, 9, 0, // Skip to: 18553 -/* 16210 */ MCD_OPC_CheckPredicate, 21, 34, 9, 0, // Skip to: 18553 -/* 16215 */ MCD_OPC_Decode, 195, 14, 98, // Opcode: VMULfq -/* 16219 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16257 -/* 16224 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 16227 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16242 -/* 16233 */ MCD_OPC_CheckPredicate, 22, 11, 9, 0, // Skip to: 18553 -/* 16238 */ MCD_OPC_Decode, 218, 13, 106, // Opcode: VMLAhq -/* 16242 */ MCD_OPC_FilterValue, 243, 1, 1, 9, 0, // Skip to: 18553 -/* 16248 */ MCD_OPC_CheckPredicate, 22, 252, 8, 0, // Skip to: 18553 -/* 16253 */ MCD_OPC_Decode, 197, 14, 98, // Opcode: VMULhq -/* 16257 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16279 -/* 16262 */ MCD_OPC_CheckPredicate, 21, 238, 8, 0, // Skip to: 18553 -/* 16267 */ MCD_OPC_CheckField, 24, 8, 242, 1, 230, 8, 0, // Skip to: 18553 -/* 16275 */ MCD_OPC_Decode, 247, 13, 106, // Opcode: VMLSfq -/* 16279 */ MCD_OPC_FilterValue, 3, 221, 8, 0, // Skip to: 18553 -/* 16284 */ MCD_OPC_CheckPredicate, 22, 216, 8, 0, // Skip to: 18553 -/* 16289 */ MCD_OPC_CheckField, 24, 8, 242, 1, 208, 8, 0, // Skip to: 18553 -/* 16297 */ MCD_OPC_Decode, 249, 13, 106, // Opcode: VMLShq -/* 16301 */ MCD_OPC_FilterValue, 14, 91, 0, 0, // Skip to: 16397 -/* 16306 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 16309 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16331 -/* 16314 */ MCD_OPC_CheckPredicate, 21, 186, 8, 0, // Skip to: 18553 -/* 16319 */ MCD_OPC_CheckField, 24, 8, 243, 1, 178, 8, 0, // Skip to: 18553 -/* 16327 */ MCD_OPC_Decode, 228, 7, 98, // Opcode: VACGEfq -/* 16331 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16353 -/* 16336 */ MCD_OPC_CheckPredicate, 22, 164, 8, 0, // Skip to: 18553 -/* 16341 */ MCD_OPC_CheckField, 24, 8, 243, 1, 156, 8, 0, // Skip to: 18553 -/* 16349 */ MCD_OPC_Decode, 230, 7, 98, // Opcode: VACGEhq -/* 16353 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16375 -/* 16358 */ MCD_OPC_CheckPredicate, 21, 142, 8, 0, // Skip to: 18553 -/* 16363 */ MCD_OPC_CheckField, 24, 8, 243, 1, 134, 8, 0, // Skip to: 18553 -/* 16371 */ MCD_OPC_Decode, 232, 7, 98, // Opcode: VACGTfq -/* 16375 */ MCD_OPC_FilterValue, 3, 125, 8, 0, // Skip to: 18553 -/* 16380 */ MCD_OPC_CheckPredicate, 22, 120, 8, 0, // Skip to: 18553 -/* 16385 */ MCD_OPC_CheckField, 24, 8, 243, 1, 112, 8, 0, // Skip to: 18553 -/* 16393 */ MCD_OPC_Decode, 234, 7, 98, // Opcode: VACGThq -/* 16397 */ MCD_OPC_FilterValue, 15, 103, 8, 0, // Skip to: 18553 -/* 16402 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 16405 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16427 -/* 16410 */ MCD_OPC_CheckPredicate, 21, 90, 8, 0, // Skip to: 18553 -/* 16415 */ MCD_OPC_CheckField, 24, 8, 242, 1, 82, 8, 0, // Skip to: 18553 -/* 16423 */ MCD_OPC_Decode, 220, 16, 98, // Opcode: VRECPSfq -/* 16427 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16449 -/* 16432 */ MCD_OPC_CheckPredicate, 22, 68, 8, 0, // Skip to: 18553 -/* 16437 */ MCD_OPC_CheckField, 24, 8, 242, 1, 60, 8, 0, // Skip to: 18553 -/* 16445 */ MCD_OPC_Decode, 222, 16, 98, // Opcode: VRECPShq -/* 16449 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16471 -/* 16454 */ MCD_OPC_CheckPredicate, 21, 46, 8, 0, // Skip to: 18553 -/* 16459 */ MCD_OPC_CheckField, 24, 8, 242, 1, 38, 8, 0, // Skip to: 18553 -/* 16467 */ MCD_OPC_Decode, 206, 17, 98, // Opcode: VRSQRTSfq -/* 16471 */ MCD_OPC_FilterValue, 3, 29, 8, 0, // Skip to: 18553 -/* 16476 */ MCD_OPC_CheckPredicate, 22, 24, 8, 0, // Skip to: 18553 -/* 16481 */ MCD_OPC_CheckField, 24, 8, 242, 1, 16, 8, 0, // Skip to: 18553 -/* 16489 */ MCD_OPC_Decode, 208, 17, 98, // Opcode: VRSQRTShq -/* 16493 */ MCD_OPC_FilterValue, 1, 7, 8, 0, // Skip to: 18553 -/* 16498 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 16501 */ MCD_OPC_FilterValue, 0, 217, 6, 0, // Skip to: 18259 -/* 16506 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 16509 */ MCD_OPC_FilterValue, 121, 247, 7, 0, // Skip to: 18553 -/* 16514 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16517 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 16661 -/* 16522 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 16525 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16623 -/* 16530 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 16533 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16585 -/* 16538 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16541 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16563 -/* 16546 */ MCD_OPC_CheckPredicate, 21, 239, 5, 0, // Skip to: 18070 -/* 16551 */ MCD_OPC_CheckField, 19, 1, 1, 232, 5, 0, // Skip to: 18070 -/* 16558 */ MCD_OPC_Decode, 155, 18, 166, 1, // Opcode: VSHRsv16i8 -/* 16563 */ MCD_OPC_FilterValue, 1, 222, 5, 0, // Skip to: 18070 -/* 16568 */ MCD_OPC_CheckPredicate, 21, 217, 5, 0, // Skip to: 18070 -/* 16573 */ MCD_OPC_CheckField, 19, 1, 1, 210, 5, 0, // Skip to: 18070 -/* 16580 */ MCD_OPC_Decode, 163, 18, 166, 1, // Opcode: VSHRuv16i8 -/* 16585 */ MCD_OPC_FilterValue, 1, 200, 5, 0, // Skip to: 18070 -/* 16590 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16593 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16608 -/* 16598 */ MCD_OPC_CheckPredicate, 21, 187, 5, 0, // Skip to: 18070 -/* 16603 */ MCD_OPC_Decode, 161, 18, 167, 1, // Opcode: VSHRsv8i16 -/* 16608 */ MCD_OPC_FilterValue, 1, 177, 5, 0, // Skip to: 18070 -/* 16613 */ MCD_OPC_CheckPredicate, 21, 172, 5, 0, // Skip to: 18070 -/* 16618 */ MCD_OPC_Decode, 169, 18, 167, 1, // Opcode: VSHRuv8i16 -/* 16623 */ MCD_OPC_FilterValue, 1, 162, 5, 0, // Skip to: 18070 -/* 16628 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16631 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16646 -/* 16636 */ MCD_OPC_CheckPredicate, 21, 149, 5, 0, // Skip to: 18070 -/* 16641 */ MCD_OPC_Decode, 160, 18, 168, 1, // Opcode: VSHRsv4i32 -/* 16646 */ MCD_OPC_FilterValue, 1, 139, 5, 0, // Skip to: 18070 -/* 16651 */ MCD_OPC_CheckPredicate, 21, 134, 5, 0, // Skip to: 18070 -/* 16656 */ MCD_OPC_Decode, 168, 18, 168, 1, // Opcode: VSHRuv4i32 -/* 16661 */ MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 16805 -/* 16666 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 16669 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16767 -/* 16674 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 16677 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16729 -/* 16682 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16685 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16707 -/* 16690 */ MCD_OPC_CheckPredicate, 21, 95, 5, 0, // Skip to: 18070 -/* 16695 */ MCD_OPC_CheckField, 19, 1, 1, 88, 5, 0, // Skip to: 18070 -/* 16702 */ MCD_OPC_Decode, 191, 18, 169, 1, // Opcode: VSRAsv16i8 -/* 16707 */ MCD_OPC_FilterValue, 1, 78, 5, 0, // Skip to: 18070 -/* 16712 */ MCD_OPC_CheckPredicate, 21, 73, 5, 0, // Skip to: 18070 -/* 16717 */ MCD_OPC_CheckField, 19, 1, 1, 66, 5, 0, // Skip to: 18070 -/* 16724 */ MCD_OPC_Decode, 199, 18, 169, 1, // Opcode: VSRAuv16i8 -/* 16729 */ MCD_OPC_FilterValue, 1, 56, 5, 0, // Skip to: 18070 -/* 16734 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16737 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16752 -/* 16742 */ MCD_OPC_CheckPredicate, 21, 43, 5, 0, // Skip to: 18070 -/* 16747 */ MCD_OPC_Decode, 197, 18, 170, 1, // Opcode: VSRAsv8i16 -/* 16752 */ MCD_OPC_FilterValue, 1, 33, 5, 0, // Skip to: 18070 -/* 16757 */ MCD_OPC_CheckPredicate, 21, 28, 5, 0, // Skip to: 18070 -/* 16762 */ MCD_OPC_Decode, 205, 18, 170, 1, // Opcode: VSRAuv8i16 -/* 16767 */ MCD_OPC_FilterValue, 1, 18, 5, 0, // Skip to: 18070 -/* 16772 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16775 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16790 -/* 16780 */ MCD_OPC_CheckPredicate, 21, 5, 5, 0, // Skip to: 18070 -/* 16785 */ MCD_OPC_Decode, 196, 18, 171, 1, // Opcode: VSRAsv4i32 -/* 16790 */ MCD_OPC_FilterValue, 1, 251, 4, 0, // Skip to: 18070 -/* 16795 */ MCD_OPC_CheckPredicate, 21, 246, 4, 0, // Skip to: 18070 -/* 16800 */ MCD_OPC_Decode, 204, 18, 171, 1, // Opcode: VSRAuv4i32 -/* 16805 */ MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 16949 -/* 16810 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 16813 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16911 -/* 16818 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 16821 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16873 -/* 16826 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16829 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16851 -/* 16834 */ MCD_OPC_CheckPredicate, 21, 207, 4, 0, // Skip to: 18070 -/* 16839 */ MCD_OPC_CheckField, 19, 1, 1, 200, 4, 0, // Skip to: 18070 -/* 16846 */ MCD_OPC_Decode, 183, 17, 166, 1, // Opcode: VRSHRsv16i8 -/* 16851 */ MCD_OPC_FilterValue, 1, 190, 4, 0, // Skip to: 18070 -/* 16856 */ MCD_OPC_CheckPredicate, 21, 185, 4, 0, // Skip to: 18070 -/* 16861 */ MCD_OPC_CheckField, 19, 1, 1, 178, 4, 0, // Skip to: 18070 -/* 16868 */ MCD_OPC_Decode, 191, 17, 166, 1, // Opcode: VRSHRuv16i8 -/* 16873 */ MCD_OPC_FilterValue, 1, 168, 4, 0, // Skip to: 18070 -/* 16878 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16881 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16896 -/* 16886 */ MCD_OPC_CheckPredicate, 21, 155, 4, 0, // Skip to: 18070 -/* 16891 */ MCD_OPC_Decode, 189, 17, 167, 1, // Opcode: VRSHRsv8i16 -/* 16896 */ MCD_OPC_FilterValue, 1, 145, 4, 0, // Skip to: 18070 -/* 16901 */ MCD_OPC_CheckPredicate, 21, 140, 4, 0, // Skip to: 18070 -/* 16906 */ MCD_OPC_Decode, 197, 17, 167, 1, // Opcode: VRSHRuv8i16 -/* 16911 */ MCD_OPC_FilterValue, 1, 130, 4, 0, // Skip to: 18070 -/* 16916 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16919 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16934 -/* 16924 */ MCD_OPC_CheckPredicate, 21, 117, 4, 0, // Skip to: 18070 -/* 16929 */ MCD_OPC_Decode, 188, 17, 168, 1, // Opcode: VRSHRsv4i32 -/* 16934 */ MCD_OPC_FilterValue, 1, 107, 4, 0, // Skip to: 18070 -/* 16939 */ MCD_OPC_CheckPredicate, 21, 102, 4, 0, // Skip to: 18070 -/* 16944 */ MCD_OPC_Decode, 196, 17, 168, 1, // Opcode: VRSHRuv4i32 -/* 16949 */ MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 17093 -/* 16954 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 16957 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17055 -/* 16962 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 16965 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17017 -/* 16970 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 16973 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16995 -/* 16978 */ MCD_OPC_CheckPredicate, 21, 63, 4, 0, // Skip to: 18070 -/* 16983 */ MCD_OPC_CheckField, 19, 1, 1, 56, 4, 0, // Skip to: 18070 -/* 16990 */ MCD_OPC_Decode, 209, 17, 169, 1, // Opcode: VRSRAsv16i8 -/* 16995 */ MCD_OPC_FilterValue, 1, 46, 4, 0, // Skip to: 18070 -/* 17000 */ MCD_OPC_CheckPredicate, 21, 41, 4, 0, // Skip to: 18070 -/* 17005 */ MCD_OPC_CheckField, 19, 1, 1, 34, 4, 0, // Skip to: 18070 -/* 17012 */ MCD_OPC_Decode, 217, 17, 169, 1, // Opcode: VRSRAuv16i8 -/* 17017 */ MCD_OPC_FilterValue, 1, 24, 4, 0, // Skip to: 18070 -/* 17022 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17025 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17040 -/* 17030 */ MCD_OPC_CheckPredicate, 21, 11, 4, 0, // Skip to: 18070 -/* 17035 */ MCD_OPC_Decode, 215, 17, 170, 1, // Opcode: VRSRAsv8i16 -/* 17040 */ MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 18070 -/* 17045 */ MCD_OPC_CheckPredicate, 21, 252, 3, 0, // Skip to: 18070 -/* 17050 */ MCD_OPC_Decode, 223, 17, 170, 1, // Opcode: VRSRAuv8i16 -/* 17055 */ MCD_OPC_FilterValue, 1, 242, 3, 0, // Skip to: 18070 -/* 17060 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17063 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17078 -/* 17068 */ MCD_OPC_CheckPredicate, 21, 229, 3, 0, // Skip to: 18070 -/* 17073 */ MCD_OPC_Decode, 214, 17, 171, 1, // Opcode: VRSRAsv4i32 -/* 17078 */ MCD_OPC_FilterValue, 1, 219, 3, 0, // Skip to: 18070 -/* 17083 */ MCD_OPC_CheckPredicate, 21, 214, 3, 0, // Skip to: 18070 -/* 17088 */ MCD_OPC_Decode, 222, 17, 171, 1, // Opcode: VRSRAuv4i32 -/* 17093 */ MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 17182 -/* 17098 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 17101 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 17160 -/* 17106 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 17109 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 17138 -/* 17114 */ MCD_OPC_CheckPredicate, 21, 183, 3, 0, // Skip to: 18070 -/* 17119 */ MCD_OPC_CheckField, 24, 1, 1, 176, 3, 0, // Skip to: 18070 -/* 17126 */ MCD_OPC_CheckField, 19, 1, 1, 169, 3, 0, // Skip to: 18070 -/* 17133 */ MCD_OPC_Decode, 207, 18, 169, 1, // Opcode: VSRIv16i8 -/* 17138 */ MCD_OPC_FilterValue, 1, 159, 3, 0, // Skip to: 18070 -/* 17143 */ MCD_OPC_CheckPredicate, 21, 154, 3, 0, // Skip to: 18070 -/* 17148 */ MCD_OPC_CheckField, 24, 1, 1, 147, 3, 0, // Skip to: 18070 -/* 17155 */ MCD_OPC_Decode, 213, 18, 170, 1, // Opcode: VSRIv8i16 -/* 17160 */ MCD_OPC_FilterValue, 1, 137, 3, 0, // Skip to: 18070 -/* 17165 */ MCD_OPC_CheckPredicate, 21, 132, 3, 0, // Skip to: 18070 -/* 17170 */ MCD_OPC_CheckField, 24, 1, 1, 125, 3, 0, // Skip to: 18070 -/* 17177 */ MCD_OPC_Decode, 212, 18, 171, 1, // Opcode: VSRIv4i32 -/* 17182 */ MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 17326 -/* 17187 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 17190 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17288 -/* 17195 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 17198 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17250 -/* 17203 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17206 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17228 -/* 17211 */ MCD_OPC_CheckPredicate, 21, 86, 3, 0, // Skip to: 18070 -/* 17216 */ MCD_OPC_CheckField, 19, 1, 1, 79, 3, 0, // Skip to: 18070 -/* 17223 */ MCD_OPC_Decode, 128, 18, 172, 1, // Opcode: VSHLiv16i8 -/* 17228 */ MCD_OPC_FilterValue, 1, 69, 3, 0, // Skip to: 18070 -/* 17233 */ MCD_OPC_CheckPredicate, 21, 64, 3, 0, // Skip to: 18070 -/* 17238 */ MCD_OPC_CheckField, 19, 1, 1, 57, 3, 0, // Skip to: 18070 -/* 17245 */ MCD_OPC_Decode, 177, 18, 173, 1, // Opcode: VSLIv16i8 -/* 17250 */ MCD_OPC_FilterValue, 1, 47, 3, 0, // Skip to: 18070 -/* 17255 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17258 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17273 -/* 17263 */ MCD_OPC_CheckPredicate, 21, 34, 3, 0, // Skip to: 18070 -/* 17268 */ MCD_OPC_Decode, 134, 18, 174, 1, // Opcode: VSHLiv8i16 -/* 17273 */ MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 18070 -/* 17278 */ MCD_OPC_CheckPredicate, 21, 19, 3, 0, // Skip to: 18070 -/* 17283 */ MCD_OPC_Decode, 183, 18, 175, 1, // Opcode: VSLIv8i16 -/* 17288 */ MCD_OPC_FilterValue, 1, 9, 3, 0, // Skip to: 18070 -/* 17293 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17311 -/* 17301 */ MCD_OPC_CheckPredicate, 21, 252, 2, 0, // Skip to: 18070 -/* 17306 */ MCD_OPC_Decode, 133, 18, 176, 1, // Opcode: VSHLiv4i32 -/* 17311 */ MCD_OPC_FilterValue, 1, 242, 2, 0, // Skip to: 18070 -/* 17316 */ MCD_OPC_CheckPredicate, 21, 237, 2, 0, // Skip to: 18070 -/* 17321 */ MCD_OPC_Decode, 182, 18, 177, 1, // Opcode: VSLIv4i32 -/* 17326 */ MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 17415 -/* 17331 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 17334 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 17393 -/* 17339 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 17342 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 17371 -/* 17347 */ MCD_OPC_CheckPredicate, 21, 206, 2, 0, // Skip to: 18070 -/* 17352 */ MCD_OPC_CheckField, 24, 1, 1, 199, 2, 0, // Skip to: 18070 -/* 17359 */ MCD_OPC_CheckField, 19, 1, 1, 192, 2, 0, // Skip to: 18070 -/* 17366 */ MCD_OPC_Decode, 153, 16, 172, 1, // Opcode: VQSHLsuv16i8 -/* 17371 */ MCD_OPC_FilterValue, 1, 182, 2, 0, // Skip to: 18070 -/* 17376 */ MCD_OPC_CheckPredicate, 21, 177, 2, 0, // Skip to: 18070 -/* 17381 */ MCD_OPC_CheckField, 24, 1, 1, 170, 2, 0, // Skip to: 18070 -/* 17388 */ MCD_OPC_Decode, 159, 16, 174, 1, // Opcode: VQSHLsuv8i16 -/* 17393 */ MCD_OPC_FilterValue, 1, 160, 2, 0, // Skip to: 18070 -/* 17398 */ MCD_OPC_CheckPredicate, 21, 155, 2, 0, // Skip to: 18070 -/* 17403 */ MCD_OPC_CheckField, 24, 1, 1, 148, 2, 0, // Skip to: 18070 -/* 17410 */ MCD_OPC_Decode, 158, 16, 176, 1, // Opcode: VQSHLsuv4i32 -/* 17415 */ MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 17559 -/* 17420 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 17423 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17521 -/* 17428 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 17431 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17483 -/* 17436 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17439 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17461 -/* 17444 */ MCD_OPC_CheckPredicate, 21, 109, 2, 0, // Skip to: 18070 -/* 17449 */ MCD_OPC_CheckField, 19, 1, 1, 102, 2, 0, // Skip to: 18070 -/* 17456 */ MCD_OPC_Decode, 145, 16, 172, 1, // Opcode: VQSHLsiv16i8 -/* 17461 */ MCD_OPC_FilterValue, 1, 92, 2, 0, // Skip to: 18070 -/* 17466 */ MCD_OPC_CheckPredicate, 21, 87, 2, 0, // Skip to: 18070 -/* 17471 */ MCD_OPC_CheckField, 19, 1, 1, 80, 2, 0, // Skip to: 18070 -/* 17478 */ MCD_OPC_Decode, 169, 16, 172, 1, // Opcode: VQSHLuiv16i8 -/* 17483 */ MCD_OPC_FilterValue, 1, 70, 2, 0, // Skip to: 18070 -/* 17488 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17491 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17506 -/* 17496 */ MCD_OPC_CheckPredicate, 21, 57, 2, 0, // Skip to: 18070 -/* 17501 */ MCD_OPC_Decode, 151, 16, 174, 1, // Opcode: VQSHLsiv8i16 -/* 17506 */ MCD_OPC_FilterValue, 1, 47, 2, 0, // Skip to: 18070 -/* 17511 */ MCD_OPC_CheckPredicate, 21, 42, 2, 0, // Skip to: 18070 -/* 17516 */ MCD_OPC_Decode, 175, 16, 174, 1, // Opcode: VQSHLuiv8i16 -/* 17521 */ MCD_OPC_FilterValue, 1, 32, 2, 0, // Skip to: 18070 -/* 17526 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17529 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17544 -/* 17534 */ MCD_OPC_CheckPredicate, 21, 19, 2, 0, // Skip to: 18070 -/* 17539 */ MCD_OPC_Decode, 150, 16, 176, 1, // Opcode: VQSHLsiv4i32 -/* 17544 */ MCD_OPC_FilterValue, 1, 9, 2, 0, // Skip to: 18070 -/* 17549 */ MCD_OPC_CheckPredicate, 21, 4, 2, 0, // Skip to: 18070 -/* 17554 */ MCD_OPC_Decode, 174, 16, 176, 1, // Opcode: VQSHLuiv4i32 -/* 17559 */ MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 17703 -/* 17564 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 17567 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17665 -/* 17572 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 17575 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17627 -/* 17580 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17583 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17605 -/* 17588 */ MCD_OPC_CheckPredicate, 21, 221, 1, 0, // Skip to: 18070 -/* 17593 */ MCD_OPC_CheckField, 19, 1, 1, 214, 1, 0, // Skip to: 18070 -/* 17600 */ MCD_OPC_Decode, 182, 17, 154, 1, // Opcode: VRSHRNv8i8 -/* 17605 */ MCD_OPC_FilterValue, 1, 204, 1, 0, // Skip to: 18070 -/* 17610 */ MCD_OPC_CheckPredicate, 21, 199, 1, 0, // Skip to: 18070 -/* 17615 */ MCD_OPC_CheckField, 19, 1, 1, 192, 1, 0, // Skip to: 18070 -/* 17622 */ MCD_OPC_Decode, 144, 16, 154, 1, // Opcode: VQRSHRUNv8i8 -/* 17627 */ MCD_OPC_FilterValue, 1, 182, 1, 0, // Skip to: 18070 -/* 17632 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17635 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17650 -/* 17640 */ MCD_OPC_CheckPredicate, 21, 169, 1, 0, // Skip to: 18070 -/* 17645 */ MCD_OPC_Decode, 181, 17, 155, 1, // Opcode: VRSHRNv4i16 -/* 17650 */ MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 18070 -/* 17655 */ MCD_OPC_CheckPredicate, 21, 154, 1, 0, // Skip to: 18070 -/* 17660 */ MCD_OPC_Decode, 143, 16, 155, 1, // Opcode: VQRSHRUNv4i16 -/* 17665 */ MCD_OPC_FilterValue, 1, 144, 1, 0, // Skip to: 18070 -/* 17670 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17673 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17688 -/* 17678 */ MCD_OPC_CheckPredicate, 21, 131, 1, 0, // Skip to: 18070 -/* 17683 */ MCD_OPC_Decode, 180, 17, 156, 1, // Opcode: VRSHRNv2i32 -/* 17688 */ MCD_OPC_FilterValue, 1, 121, 1, 0, // Skip to: 18070 -/* 17693 */ MCD_OPC_CheckPredicate, 21, 116, 1, 0, // Skip to: 18070 -/* 17698 */ MCD_OPC_Decode, 142, 16, 156, 1, // Opcode: VQRSHRUNv2i32 -/* 17703 */ MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 17847 -/* 17708 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 17711 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17809 -/* 17716 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 17719 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17771 -/* 17724 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17727 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17749 -/* 17732 */ MCD_OPC_CheckPredicate, 21, 77, 1, 0, // Skip to: 18070 -/* 17737 */ MCD_OPC_CheckField, 19, 1, 1, 70, 1, 0, // Skip to: 18070 -/* 17744 */ MCD_OPC_Decode, 138, 16, 154, 1, // Opcode: VQRSHRNsv8i8 -/* 17749 */ MCD_OPC_FilterValue, 1, 60, 1, 0, // Skip to: 18070 -/* 17754 */ MCD_OPC_CheckPredicate, 21, 55, 1, 0, // Skip to: 18070 -/* 17759 */ MCD_OPC_CheckField, 19, 1, 1, 48, 1, 0, // Skip to: 18070 -/* 17766 */ MCD_OPC_Decode, 141, 16, 154, 1, // Opcode: VQRSHRNuv8i8 -/* 17771 */ MCD_OPC_FilterValue, 1, 38, 1, 0, // Skip to: 18070 -/* 17776 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17779 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17794 -/* 17784 */ MCD_OPC_CheckPredicate, 21, 25, 1, 0, // Skip to: 18070 -/* 17789 */ MCD_OPC_Decode, 137, 16, 155, 1, // Opcode: VQRSHRNsv4i16 -/* 17794 */ MCD_OPC_FilterValue, 1, 15, 1, 0, // Skip to: 18070 -/* 17799 */ MCD_OPC_CheckPredicate, 21, 10, 1, 0, // Skip to: 18070 -/* 17804 */ MCD_OPC_Decode, 140, 16, 155, 1, // Opcode: VQRSHRNuv4i16 -/* 17809 */ MCD_OPC_FilterValue, 1, 0, 1, 0, // Skip to: 18070 -/* 17814 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17817 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17832 -/* 17822 */ MCD_OPC_CheckPredicate, 21, 243, 0, 0, // Skip to: 18070 -/* 17827 */ MCD_OPC_Decode, 136, 16, 156, 1, // Opcode: VQRSHRNsv2i32 -/* 17832 */ MCD_OPC_FilterValue, 1, 233, 0, 0, // Skip to: 18070 -/* 17837 */ MCD_OPC_CheckPredicate, 21, 228, 0, 0, // Skip to: 18070 -/* 17842 */ MCD_OPC_Decode, 139, 16, 156, 1, // Opcode: VQRSHRNuv2i32 -/* 17847 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 17885 -/* 17852 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17855 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17870 -/* 17860 */ MCD_OPC_CheckPredicate, 22, 205, 0, 0, // Skip to: 18070 -/* 17865 */ MCD_OPC_Decode, 248, 9, 178, 1, // Opcode: VCVTxs2hq -/* 17870 */ MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 18070 -/* 17875 */ MCD_OPC_CheckPredicate, 22, 190, 0, 0, // Skip to: 18070 -/* 17880 */ MCD_OPC_Decode, 252, 9, 178, 1, // Opcode: VCVTxu2hq -/* 17885 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 17923 -/* 17890 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17893 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17908 -/* 17898 */ MCD_OPC_CheckPredicate, 22, 167, 0, 0, // Skip to: 18070 -/* 17903 */ MCD_OPC_Decode, 234, 9, 178, 1, // Opcode: VCVTh2xsq -/* 17908 */ MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 18070 -/* 17913 */ MCD_OPC_CheckPredicate, 22, 152, 0, 0, // Skip to: 18070 -/* 17918 */ MCD_OPC_Decode, 236, 9, 178, 1, // Opcode: VCVTh2xuq -/* 17923 */ MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 18008 -/* 17928 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 17931 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17953 -/* 17936 */ MCD_OPC_CheckPredicate, 21, 34, 0, 0, // Skip to: 17975 -/* 17941 */ MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 17975 -/* 17948 */ MCD_OPC_Decode, 156, 14, 161, 1, // Opcode: VMOVv16i8 -/* 17953 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 17975 -/* 17958 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 17975 -/* 17963 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 17975 -/* 17970 */ MCD_OPC_Decode, 160, 14, 161, 1, // Opcode: VMOVv2i64 -/* 17975 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 17978 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17993 -/* 17983 */ MCD_OPC_CheckPredicate, 21, 82, 0, 0, // Skip to: 18070 -/* 17988 */ MCD_OPC_Decode, 246, 9, 178, 1, // Opcode: VCVTxs2fq -/* 17993 */ MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 18070 -/* 17998 */ MCD_OPC_CheckPredicate, 21, 67, 0, 0, // Skip to: 18070 -/* 18003 */ MCD_OPC_Decode, 250, 9, 178, 1, // Opcode: VCVTxu2fq -/* 18008 */ MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 18070 -/* 18013 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... -/* 18016 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18031 -/* 18021 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 18046 -/* 18026 */ MCD_OPC_Decode, 225, 9, 178, 1, // Opcode: VCVTf2xsq -/* 18031 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 18046 -/* 18036 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 18046 -/* 18041 */ MCD_OPC_Decode, 227, 9, 178, 1, // Opcode: VCVTf2xuq -/* 18046 */ MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 18070 -/* 18051 */ MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 18070 -/* 18058 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 18070 -/* 18065 */ MCD_OPC_Decode, 161, 14, 161, 1, // Opcode: VMOVv4f32 -/* 18070 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 18073 */ MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 18166 -/* 18078 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... -/* 18081 */ MCD_OPC_FilterValue, 0, 211, 1, 0, // Skip to: 18553 -/* 18086 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 18089 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18111 -/* 18094 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 18156 -/* 18099 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18156 -/* 18106 */ MCD_OPC_Decode, 164, 14, 161, 1, // Opcode: VMOVv8i16 -/* 18111 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18156 -/* 18116 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 18119 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18134 -/* 18124 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 18156 -/* 18129 */ MCD_OPC_Decode, 247, 14, 161, 1, // Opcode: VORRiv4i32 -/* 18134 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18156 -/* 18139 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 18156 -/* 18144 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18156 -/* 18151 */ MCD_OPC_Decode, 248, 14, 161, 1, // Opcode: VORRiv8i16 -/* 18156 */ MCD_OPC_CheckPredicate, 21, 136, 1, 0, // Skip to: 18553 -/* 18161 */ MCD_OPC_Decode, 163, 14, 161, 1, // Opcode: VMOVv4i32 -/* 18166 */ MCD_OPC_FilterValue, 1, 126, 1, 0, // Skip to: 18553 -/* 18171 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... -/* 18174 */ MCD_OPC_FilterValue, 0, 118, 1, 0, // Skip to: 18553 -/* 18179 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 18182 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18204 -/* 18187 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 18249 -/* 18192 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18249 -/* 18199 */ MCD_OPC_Decode, 219, 14, 161, 1, // Opcode: VMVNv8i16 -/* 18204 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18249 -/* 18209 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 18212 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18227 -/* 18217 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 18249 -/* 18222 */ MCD_OPC_Decode, 142, 8, 161, 1, // Opcode: VBICiv4i32 -/* 18227 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18249 -/* 18232 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 18249 -/* 18237 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18249 -/* 18244 */ MCD_OPC_Decode, 143, 8, 161, 1, // Opcode: VBICiv8i16 -/* 18249 */ MCD_OPC_CheckPredicate, 21, 43, 1, 0, // Skip to: 18553 -/* 18254 */ MCD_OPC_Decode, 218, 14, 161, 1, // Opcode: VMVNv4i32 -/* 18259 */ MCD_OPC_FilterValue, 1, 33, 1, 0, // Skip to: 18553 -/* 18264 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 18267 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 18307 -/* 18272 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 18275 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18291 -/* 18281 */ MCD_OPC_CheckPredicate, 21, 11, 1, 0, // Skip to: 18553 -/* 18286 */ MCD_OPC_Decode, 158, 18, 179, 1, // Opcode: VSHRsv2i64 -/* 18291 */ MCD_OPC_FilterValue, 243, 1, 0, 1, 0, // Skip to: 18553 -/* 18297 */ MCD_OPC_CheckPredicate, 21, 251, 0, 0, // Skip to: 18553 -/* 18302 */ MCD_OPC_Decode, 166, 18, 179, 1, // Opcode: VSHRuv2i64 -/* 18307 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 18347 -/* 18312 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 18315 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18331 -/* 18321 */ MCD_OPC_CheckPredicate, 21, 227, 0, 0, // Skip to: 18553 -/* 18326 */ MCD_OPC_Decode, 194, 18, 180, 1, // Opcode: VSRAsv2i64 -/* 18331 */ MCD_OPC_FilterValue, 243, 1, 216, 0, 0, // Skip to: 18553 -/* 18337 */ MCD_OPC_CheckPredicate, 21, 211, 0, 0, // Skip to: 18553 -/* 18342 */ MCD_OPC_Decode, 202, 18, 180, 1, // Opcode: VSRAuv2i64 -/* 18347 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 18387 -/* 18352 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 18355 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18371 -/* 18361 */ MCD_OPC_CheckPredicate, 21, 187, 0, 0, // Skip to: 18553 -/* 18366 */ MCD_OPC_Decode, 186, 17, 179, 1, // Opcode: VRSHRsv2i64 -/* 18371 */ MCD_OPC_FilterValue, 243, 1, 176, 0, 0, // Skip to: 18553 -/* 18377 */ MCD_OPC_CheckPredicate, 21, 171, 0, 0, // Skip to: 18553 -/* 18382 */ MCD_OPC_Decode, 194, 17, 179, 1, // Opcode: VRSHRuv2i64 -/* 18387 */ MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 18427 -/* 18392 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 18395 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18411 -/* 18401 */ MCD_OPC_CheckPredicate, 21, 147, 0, 0, // Skip to: 18553 -/* 18406 */ MCD_OPC_Decode, 212, 17, 180, 1, // Opcode: VRSRAsv2i64 -/* 18411 */ MCD_OPC_FilterValue, 243, 1, 136, 0, 0, // Skip to: 18553 -/* 18417 */ MCD_OPC_CheckPredicate, 21, 131, 0, 0, // Skip to: 18553 -/* 18422 */ MCD_OPC_Decode, 220, 17, 180, 1, // Opcode: VRSRAuv2i64 -/* 18427 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 18450 -/* 18432 */ MCD_OPC_CheckPredicate, 21, 116, 0, 0, // Skip to: 18553 -/* 18437 */ MCD_OPC_CheckField, 24, 8, 243, 1, 108, 0, 0, // Skip to: 18553 -/* 18445 */ MCD_OPC_Decode, 210, 18, 180, 1, // Opcode: VSRIv2i64 -/* 18450 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 18490 -/* 18455 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 18458 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18474 -/* 18464 */ MCD_OPC_CheckPredicate, 21, 84, 0, 0, // Skip to: 18553 -/* 18469 */ MCD_OPC_Decode, 131, 18, 181, 1, // Opcode: VSHLiv2i64 -/* 18474 */ MCD_OPC_FilterValue, 243, 1, 73, 0, 0, // Skip to: 18553 -/* 18480 */ MCD_OPC_CheckPredicate, 21, 68, 0, 0, // Skip to: 18553 -/* 18485 */ MCD_OPC_Decode, 180, 18, 182, 1, // Opcode: VSLIv2i64 -/* 18490 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 18513 -/* 18495 */ MCD_OPC_CheckPredicate, 21, 53, 0, 0, // Skip to: 18553 -/* 18500 */ MCD_OPC_CheckField, 24, 8, 243, 1, 45, 0, 0, // Skip to: 18553 -/* 18508 */ MCD_OPC_Decode, 156, 16, 181, 1, // Opcode: VQSHLsuv2i64 -/* 18513 */ MCD_OPC_FilterValue, 7, 35, 0, 0, // Skip to: 18553 -/* 18518 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 18521 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18537 -/* 18527 */ MCD_OPC_CheckPredicate, 21, 21, 0, 0, // Skip to: 18553 -/* 18532 */ MCD_OPC_Decode, 148, 16, 181, 1, // Opcode: VQSHLsiv2i64 -/* 18537 */ MCD_OPC_FilterValue, 243, 1, 10, 0, 0, // Skip to: 18553 -/* 18543 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 18553 -/* 18548 */ MCD_OPC_Decode, 172, 16, 181, 1, // Opcode: VQSHLuiv2i64 -/* 18553 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 198, + 41, + 0, // Skip to: 10702 + /* 8 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 148, + 6, + 0, // Skip to: 1700 + /* 16 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 127, + 0, + 0, // Skip to: 151 + /* 24 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 27 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 66 + /* 33 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 36 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 51 + /* 41 */ MCD_OPC_CheckPredicate, + 26, + 241, + 74, + 0, // Skip to: 19231 + /* 46 */ MCD_OPC_Decode, + 226, + 18, + 200, + 1, // Opcode: VHADDsv8i8 + /* 51 */ MCD_OPC_FilterValue, + 1, + 231, + 74, + 0, // Skip to: 19231 + /* 56 */ MCD_OPC_CheckPredicate, + 26, + 226, + 74, + 0, // Skip to: 19231 + /* 61 */ MCD_OPC_Decode, + 221, + 18, + 201, + 1, // Opcode: VHADDsv16i8 + /* 66 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 89 + /* 72 */ MCD_OPC_CheckPredicate, + 26, + 210, + 74, + 0, // Skip to: 19231 + /* 77 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 203, + 74, + 0, // Skip to: 19231 + /* 84 */ MCD_OPC_Decode, + 141, + 16, + 202, + 1, // Opcode: VADDLsv8i16 + /* 89 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 128 + /* 95 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 98 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 113 + /* 103 */ MCD_OPC_CheckPredicate, + 26, + 179, + 74, + 0, // Skip to: 19231 + /* 108 */ MCD_OPC_Decode, + 232, + 18, + 200, + 1, // Opcode: VHADDuv8i8 + /* 113 */ MCD_OPC_FilterValue, + 1, + 169, + 74, + 0, // Skip to: 19231 + /* 118 */ MCD_OPC_CheckPredicate, + 26, + 164, + 74, + 0, // Skip to: 19231 + /* 123 */ MCD_OPC_Decode, + 227, + 18, + 201, + 1, // Opcode: VHADDuv16i8 + /* 128 */ MCD_OPC_FilterValue, + 231, + 3, + 153, + 74, + 0, // Skip to: 19231 + /* 134 */ MCD_OPC_CheckPredicate, + 26, + 148, + 74, + 0, // Skip to: 19231 + /* 139 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 141, + 74, + 0, // Skip to: 19231 + /* 146 */ MCD_OPC_Decode, + 144, + 16, + 202, + 1, // Opcode: VADDLuv8i16 + /* 151 */ MCD_OPC_FilterValue, + 1, + 127, + 0, + 0, // Skip to: 283 + /* 156 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 159 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 198 + /* 165 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 168 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 183 + /* 173 */ MCD_OPC_CheckPredicate, + 26, + 109, + 74, + 0, // Skip to: 19231 + /* 178 */ MCD_OPC_Decode, + 206, + 25, + 200, + 1, // Opcode: VRHADDsv8i8 + /* 183 */ MCD_OPC_FilterValue, + 1, + 99, + 74, + 0, // Skip to: 19231 + /* 188 */ MCD_OPC_CheckPredicate, + 26, + 94, + 74, + 0, // Skip to: 19231 + /* 193 */ MCD_OPC_Decode, + 201, + 25, + 201, + 1, // Opcode: VRHADDsv16i8 + /* 198 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 221 + /* 204 */ MCD_OPC_CheckPredicate, + 26, + 78, + 74, + 0, // Skip to: 19231 + /* 209 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 71, + 74, + 0, // Skip to: 19231 + /* 216 */ MCD_OPC_Decode, + 148, + 16, + 203, + 1, // Opcode: VADDWsv8i16 + /* 221 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 260 + /* 227 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 230 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 245 + /* 235 */ MCD_OPC_CheckPredicate, + 26, + 47, + 74, + 0, // Skip to: 19231 + /* 240 */ MCD_OPC_Decode, + 212, + 25, + 200, + 1, // Opcode: VRHADDuv8i8 + /* 245 */ MCD_OPC_FilterValue, + 1, + 37, + 74, + 0, // Skip to: 19231 + /* 250 */ MCD_OPC_CheckPredicate, + 26, + 32, + 74, + 0, // Skip to: 19231 + /* 255 */ MCD_OPC_Decode, + 207, + 25, + 201, + 1, // Opcode: VRHADDuv16i8 + /* 260 */ MCD_OPC_FilterValue, + 231, + 3, + 21, + 74, + 0, // Skip to: 19231 + /* 266 */ MCD_OPC_CheckPredicate, + 26, + 16, + 74, + 0, // Skip to: 19231 + /* 271 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 9, + 74, + 0, // Skip to: 19231 + /* 278 */ MCD_OPC_Decode, + 151, + 16, + 203, + 1, // Opcode: VADDWuv8i16 + /* 283 */ MCD_OPC_FilterValue, + 2, + 127, + 0, + 0, // Skip to: 415 + /* 288 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 291 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 330 + /* 297 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 300 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 315 + /* 305 */ MCD_OPC_CheckPredicate, + 26, + 233, + 73, + 0, // Skip to: 19231 + /* 310 */ MCD_OPC_Decode, + 238, + 18, + 200, + 1, // Opcode: VHSUBsv8i8 + /* 315 */ MCD_OPC_FilterValue, + 1, + 223, + 73, + 0, // Skip to: 19231 + /* 320 */ MCD_OPC_CheckPredicate, + 26, + 218, + 73, + 0, // Skip to: 19231 + /* 325 */ MCD_OPC_Decode, + 233, + 18, + 201, + 1, // Opcode: VHSUBsv16i8 + /* 330 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 353 + /* 336 */ MCD_OPC_CheckPredicate, + 26, + 202, + 73, + 0, // Skip to: 19231 + /* 341 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 195, + 73, + 0, // Skip to: 19231 + /* 348 */ MCD_OPC_Decode, + 221, + 29, + 202, + 1, // Opcode: VSUBLsv8i16 + /* 353 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 392 + /* 359 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 362 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 377 + /* 367 */ MCD_OPC_CheckPredicate, + 26, + 171, + 73, + 0, // Skip to: 19231 + /* 372 */ MCD_OPC_Decode, + 244, + 18, + 200, + 1, // Opcode: VHSUBuv8i8 + /* 377 */ MCD_OPC_FilterValue, + 1, + 161, + 73, + 0, // Skip to: 19231 + /* 382 */ MCD_OPC_CheckPredicate, + 26, + 156, + 73, + 0, // Skip to: 19231 + /* 387 */ MCD_OPC_Decode, + 239, + 18, + 201, + 1, // Opcode: VHSUBuv16i8 + /* 392 */ MCD_OPC_FilterValue, + 231, + 3, + 145, + 73, + 0, // Skip to: 19231 + /* 398 */ MCD_OPC_CheckPredicate, + 26, + 140, + 73, + 0, // Skip to: 19231 + /* 403 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 133, + 73, + 0, // Skip to: 19231 + /* 410 */ MCD_OPC_Decode, + 224, + 29, + 202, + 1, // Opcode: VSUBLuv8i16 + /* 415 */ MCD_OPC_FilterValue, + 3, + 127, + 0, + 0, // Skip to: 547 + /* 420 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 423 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 462 + /* 429 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 432 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 447 + /* 437 */ MCD_OPC_CheckPredicate, + 26, + 101, + 73, + 0, // Skip to: 19231 + /* 442 */ MCD_OPC_Decode, + 243, + 16, + 200, + 1, // Opcode: VCGTsv8i8 + /* 447 */ MCD_OPC_FilterValue, + 1, + 91, + 73, + 0, // Skip to: 19231 + /* 452 */ MCD_OPC_CheckPredicate, + 26, + 86, + 73, + 0, // Skip to: 19231 + /* 457 */ MCD_OPC_Decode, + 238, + 16, + 201, + 1, // Opcode: VCGTsv16i8 + /* 462 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 485 + /* 468 */ MCD_OPC_CheckPredicate, + 26, + 70, + 73, + 0, // Skip to: 19231 + /* 473 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 63, + 73, + 0, // Skip to: 19231 + /* 480 */ MCD_OPC_Decode, + 228, + 29, + 203, + 1, // Opcode: VSUBWsv8i16 + /* 485 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 524 + /* 491 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 494 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 509 + /* 499 */ MCD_OPC_CheckPredicate, + 26, + 39, + 73, + 0, // Skip to: 19231 + /* 504 */ MCD_OPC_Decode, + 249, + 16, + 200, + 1, // Opcode: VCGTuv8i8 + /* 509 */ MCD_OPC_FilterValue, + 1, + 29, + 73, + 0, // Skip to: 19231 + /* 514 */ MCD_OPC_CheckPredicate, + 26, + 24, + 73, + 0, // Skip to: 19231 + /* 519 */ MCD_OPC_Decode, + 244, + 16, + 201, + 1, // Opcode: VCGTuv16i8 + /* 524 */ MCD_OPC_FilterValue, + 231, + 3, + 13, + 73, + 0, // Skip to: 19231 + /* 530 */ MCD_OPC_CheckPredicate, + 26, + 8, + 73, + 0, // Skip to: 19231 + /* 535 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 1, + 73, + 0, // Skip to: 19231 + /* 542 */ MCD_OPC_Decode, + 231, + 29, + 203, + 1, // Opcode: VSUBWuv8i16 + /* 547 */ MCD_OPC_FilterValue, + 4, + 127, + 0, + 0, // Skip to: 679 + /* 552 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 555 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 594 + /* 561 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 564 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 579 + /* 569 */ MCD_OPC_CheckPredicate, + 26, + 225, + 72, + 0, // Skip to: 19231 + /* 574 */ MCD_OPC_Decode, + 239, + 26, + 204, + 1, // Opcode: VSHLsv8i8 + /* 579 */ MCD_OPC_FilterValue, + 1, + 215, + 72, + 0, // Skip to: 19231 + /* 584 */ MCD_OPC_CheckPredicate, + 26, + 210, + 72, + 0, // Skip to: 19231 + /* 589 */ MCD_OPC_Decode, + 232, + 26, + 205, + 1, // Opcode: VSHLsv16i8 + /* 594 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 617 + /* 600 */ MCD_OPC_CheckPredicate, + 26, + 194, + 72, + 0, // Skip to: 19231 + /* 605 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 187, + 72, + 0, // Skip to: 19231 + /* 612 */ MCD_OPC_Decode, + 138, + 16, + 206, + 1, // Opcode: VADDHNv8i8 + /* 617 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 656 + /* 623 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 626 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 641 + /* 631 */ MCD_OPC_CheckPredicate, + 26, + 163, + 72, + 0, // Skip to: 19231 + /* 636 */ MCD_OPC_Decode, + 247, + 26, + 204, + 1, // Opcode: VSHLuv8i8 + /* 641 */ MCD_OPC_FilterValue, + 1, + 153, + 72, + 0, // Skip to: 19231 + /* 646 */ MCD_OPC_CheckPredicate, + 26, + 148, + 72, + 0, // Skip to: 19231 + /* 651 */ MCD_OPC_Decode, + 240, + 26, + 205, + 1, // Opcode: VSHLuv16i8 + /* 656 */ MCD_OPC_FilterValue, + 231, + 3, + 137, + 72, + 0, // Skip to: 19231 + /* 662 */ MCD_OPC_CheckPredicate, + 26, + 132, + 72, + 0, // Skip to: 19231 + /* 667 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 125, + 72, + 0, // Skip to: 19231 + /* 674 */ MCD_OPC_Decode, + 178, + 25, + 206, + 1, // Opcode: VRADDHNv8i8 + /* 679 */ MCD_OPC_FilterValue, + 5, + 127, + 0, + 0, // Skip to: 811 + /* 684 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 687 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 726 + /* 693 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 696 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 711 + /* 701 */ MCD_OPC_CheckPredicate, + 26, + 93, + 72, + 0, // Skip to: 19231 + /* 706 */ MCD_OPC_Decode, + 137, + 26, + 204, + 1, // Opcode: VRSHLsv8i8 + /* 711 */ MCD_OPC_FilterValue, + 1, + 83, + 72, + 0, // Skip to: 19231 + /* 716 */ MCD_OPC_CheckPredicate, + 26, + 78, + 72, + 0, // Skip to: 19231 + /* 721 */ MCD_OPC_Decode, + 130, + 26, + 205, + 1, // Opcode: VRSHLsv16i8 + /* 726 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 749 + /* 732 */ MCD_OPC_CheckPredicate, + 26, + 62, + 72, + 0, // Skip to: 19231 + /* 737 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 55, + 72, + 0, // Skip to: 19231 + /* 744 */ MCD_OPC_Decode, + 203, + 15, + 207, + 1, // Opcode: VABALsv8i16 + /* 749 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 788 + /* 755 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 758 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 773 + /* 763 */ MCD_OPC_CheckPredicate, + 26, + 31, + 72, + 0, // Skip to: 19231 + /* 768 */ MCD_OPC_Decode, + 145, + 26, + 204, + 1, // Opcode: VRSHLuv8i8 + /* 773 */ MCD_OPC_FilterValue, + 1, + 21, + 72, + 0, // Skip to: 19231 + /* 778 */ MCD_OPC_CheckPredicate, + 26, + 16, + 72, + 0, // Skip to: 19231 + /* 783 */ MCD_OPC_Decode, + 138, + 26, + 205, + 1, // Opcode: VRSHLuv16i8 + /* 788 */ MCD_OPC_FilterValue, + 231, + 3, + 5, + 72, + 0, // Skip to: 19231 + /* 794 */ MCD_OPC_CheckPredicate, + 26, + 0, + 72, + 0, // Skip to: 19231 + /* 799 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 249, + 71, + 0, // Skip to: 19231 + /* 806 */ MCD_OPC_Decode, + 206, + 15, + 207, + 1, // Opcode: VABALuv8i16 + /* 811 */ MCD_OPC_FilterValue, + 6, + 127, + 0, + 0, // Skip to: 943 + /* 816 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 819 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 858 + /* 825 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 828 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 843 + /* 833 */ MCD_OPC_CheckPredicate, + 26, + 217, + 71, + 0, // Skip to: 19231 + /* 838 */ MCD_OPC_Decode, + 134, + 22, + 200, + 1, // Opcode: VMAXsv8i8 + /* 843 */ MCD_OPC_FilterValue, + 1, + 207, + 71, + 0, // Skip to: 19231 + /* 848 */ MCD_OPC_CheckPredicate, + 26, + 202, + 71, + 0, // Skip to: 19231 + /* 853 */ MCD_OPC_Decode, + 129, + 22, + 201, + 1, // Opcode: VMAXsv16i8 + /* 858 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 881 + /* 864 */ MCD_OPC_CheckPredicate, + 26, + 186, + 71, + 0, // Skip to: 19231 + /* 869 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 179, + 71, + 0, // Skip to: 19231 + /* 876 */ MCD_OPC_Decode, + 218, + 29, + 206, + 1, // Opcode: VSUBHNv8i8 + /* 881 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 920 + /* 887 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 890 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 905 + /* 895 */ MCD_OPC_CheckPredicate, + 26, + 155, + 71, + 0, // Skip to: 19231 + /* 900 */ MCD_OPC_Decode, + 140, + 22, + 200, + 1, // Opcode: VMAXuv8i8 + /* 905 */ MCD_OPC_FilterValue, + 1, + 145, + 71, + 0, // Skip to: 19231 + /* 910 */ MCD_OPC_CheckPredicate, + 26, + 140, + 71, + 0, // Skip to: 19231 + /* 915 */ MCD_OPC_Decode, + 135, + 22, + 201, + 1, // Opcode: VMAXuv16i8 + /* 920 */ MCD_OPC_FilterValue, + 231, + 3, + 129, + 71, + 0, // Skip to: 19231 + /* 926 */ MCD_OPC_CheckPredicate, + 26, + 124, + 71, + 0, // Skip to: 19231 + /* 931 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 117, + 71, + 0, // Skip to: 19231 + /* 938 */ MCD_OPC_Decode, + 193, + 26, + 206, + 1, // Opcode: VRSUBHNv8i8 + /* 943 */ MCD_OPC_FilterValue, + 7, + 127, + 0, + 0, // Skip to: 1075 + /* 948 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 951 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 990 + /* 957 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 960 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 975 + /* 965 */ MCD_OPC_CheckPredicate, + 26, + 85, + 71, + 0, // Skip to: 19231 + /* 970 */ MCD_OPC_Decode, + 234, + 15, + 200, + 1, // Opcode: VABDsv8i8 + /* 975 */ MCD_OPC_FilterValue, + 1, + 75, + 71, + 0, // Skip to: 19231 + /* 980 */ MCD_OPC_CheckPredicate, + 26, + 70, + 71, + 0, // Skip to: 19231 + /* 985 */ MCD_OPC_Decode, + 229, + 15, + 201, + 1, // Opcode: VABDsv16i8 + /* 990 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1013 + /* 996 */ MCD_OPC_CheckPredicate, + 26, + 54, + 71, + 0, // Skip to: 19231 + /* 1001 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 47, + 71, + 0, // Skip to: 19231 + /* 1008 */ MCD_OPC_Decode, + 221, + 15, + 202, + 1, // Opcode: VABDLsv8i16 + /* 1013 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 1052 + /* 1019 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1022 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1037 + /* 1027 */ MCD_OPC_CheckPredicate, + 26, + 23, + 71, + 0, // Skip to: 19231 + /* 1032 */ MCD_OPC_Decode, + 240, + 15, + 200, + 1, // Opcode: VABDuv8i8 + /* 1037 */ MCD_OPC_FilterValue, + 1, + 13, + 71, + 0, // Skip to: 19231 + /* 1042 */ MCD_OPC_CheckPredicate, + 26, + 8, + 71, + 0, // Skip to: 19231 + /* 1047 */ MCD_OPC_Decode, + 235, + 15, + 201, + 1, // Opcode: VABDuv16i8 + /* 1052 */ MCD_OPC_FilterValue, + 231, + 3, + 253, + 70, + 0, // Skip to: 19231 + /* 1058 */ MCD_OPC_CheckPredicate, + 26, + 248, + 70, + 0, // Skip to: 19231 + /* 1063 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 241, + 70, + 0, // Skip to: 19231 + /* 1070 */ MCD_OPC_Decode, + 224, + 15, + 202, + 1, // Opcode: VABDLuv8i16 + /* 1075 */ MCD_OPC_FilterValue, + 8, + 127, + 0, + 0, // Skip to: 1207 + /* 1080 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1083 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 1122 + /* 1089 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1092 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1107 + /* 1097 */ MCD_OPC_CheckPredicate, + 26, + 209, + 70, + 0, // Skip to: 19231 + /* 1102 */ MCD_OPC_Decode, + 163, + 16, + 200, + 1, // Opcode: VADDv8i8 + /* 1107 */ MCD_OPC_FilterValue, + 1, + 199, + 70, + 0, // Skip to: 19231 + /* 1112 */ MCD_OPC_CheckPredicate, + 26, + 194, + 70, + 0, // Skip to: 19231 + /* 1117 */ MCD_OPC_Decode, + 156, + 16, + 201, + 1, // Opcode: VADDv16i8 + /* 1122 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1145 + /* 1128 */ MCD_OPC_CheckPredicate, + 26, + 178, + 70, + 0, // Skip to: 19231 + /* 1133 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 171, + 70, + 0, // Skip to: 19231 + /* 1140 */ MCD_OPC_Decode, + 165, + 22, + 207, + 1, // Opcode: VMLALsv8i16 + /* 1145 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 1184 + /* 1151 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1154 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1169 + /* 1159 */ MCD_OPC_CheckPredicate, + 26, + 147, + 70, + 0, // Skip to: 19231 + /* 1164 */ MCD_OPC_Decode, + 243, + 29, + 200, + 1, // Opcode: VSUBv8i8 + /* 1169 */ MCD_OPC_FilterValue, + 1, + 137, + 70, + 0, // Skip to: 19231 + /* 1174 */ MCD_OPC_CheckPredicate, + 26, + 132, + 70, + 0, // Skip to: 19231 + /* 1179 */ MCD_OPC_Decode, + 236, + 29, + 201, + 1, // Opcode: VSUBv16i8 + /* 1184 */ MCD_OPC_FilterValue, + 231, + 3, + 121, + 70, + 0, // Skip to: 19231 + /* 1190 */ MCD_OPC_CheckPredicate, + 26, + 116, + 70, + 0, // Skip to: 19231 + /* 1195 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 109, + 70, + 0, // Skip to: 19231 + /* 1202 */ MCD_OPC_Decode, + 168, + 22, + 207, + 1, // Opcode: VMLALuv8i16 + /* 1207 */ MCD_OPC_FilterValue, + 9, + 83, + 0, + 0, // Skip to: 1295 + /* 1212 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1215 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 1255 + /* 1220 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1223 */ MCD_OPC_FilterValue, + 228, + 3, + 10, + 0, + 0, // Skip to: 1239 + /* 1229 */ MCD_OPC_CheckPredicate, + 26, + 77, + 70, + 0, // Skip to: 19231 + /* 1234 */ MCD_OPC_Decode, + 187, + 22, + 208, + 1, // Opcode: VMLAv8i8 + /* 1239 */ MCD_OPC_FilterValue, + 230, + 3, + 66, + 70, + 0, // Skip to: 19231 + /* 1245 */ MCD_OPC_CheckPredicate, + 26, + 61, + 70, + 0, // Skip to: 19231 + /* 1250 */ MCD_OPC_Decode, + 218, + 22, + 208, + 1, // Opcode: VMLSv8i8 + /* 1255 */ MCD_OPC_FilterValue, + 1, + 51, + 70, + 0, // Skip to: 19231 + /* 1260 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1263 */ MCD_OPC_FilterValue, + 228, + 3, + 10, + 0, + 0, // Skip to: 1279 + /* 1269 */ MCD_OPC_CheckPredicate, + 26, + 37, + 70, + 0, // Skip to: 19231 + /* 1274 */ MCD_OPC_Decode, + 182, + 22, + 209, + 1, // Opcode: VMLAv16i8 + /* 1279 */ MCD_OPC_FilterValue, + 230, + 3, + 26, + 70, + 0, // Skip to: 19231 + /* 1285 */ MCD_OPC_CheckPredicate, + 26, + 21, + 70, + 0, // Skip to: 19231 + /* 1290 */ MCD_OPC_Decode, + 213, + 22, + 209, + 1, // Opcode: VMLSv16i8 + /* 1295 */ MCD_OPC_FilterValue, + 10, + 95, + 0, + 0, // Skip to: 1395 + /* 1300 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1303 */ MCD_OPC_FilterValue, + 228, + 3, + 17, + 0, + 0, // Skip to: 1326 + /* 1309 */ MCD_OPC_CheckPredicate, + 26, + 253, + 69, + 0, // Skip to: 19231 + /* 1314 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 246, + 69, + 0, // Skip to: 19231 + /* 1321 */ MCD_OPC_Decode, + 249, + 23, + 200, + 1, // Opcode: VPMAXs8 + /* 1326 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1349 + /* 1332 */ MCD_OPC_CheckPredicate, + 26, + 230, + 69, + 0, // Skip to: 19231 + /* 1337 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 223, + 69, + 0, // Skip to: 19231 + /* 1344 */ MCD_OPC_Decode, + 196, + 22, + 207, + 1, // Opcode: VMLSLsv8i16 + /* 1349 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 1372 + /* 1355 */ MCD_OPC_CheckPredicate, + 26, + 207, + 69, + 0, // Skip to: 19231 + /* 1360 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 200, + 69, + 0, // Skip to: 19231 + /* 1367 */ MCD_OPC_Decode, + 252, + 23, + 200, + 1, // Opcode: VPMAXu8 + /* 1372 */ MCD_OPC_FilterValue, + 231, + 3, + 189, + 69, + 0, // Skip to: 19231 + /* 1378 */ MCD_OPC_CheckPredicate, + 26, + 184, + 69, + 0, // Skip to: 19231 + /* 1383 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 177, + 69, + 0, // Skip to: 19231 + /* 1390 */ MCD_OPC_Decode, + 199, + 22, + 207, + 1, // Opcode: VMLSLuv8i16 + /* 1395 */ MCD_OPC_FilterValue, + 12, + 49, + 0, + 0, // Skip to: 1449 + /* 1400 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1403 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1426 + /* 1409 */ MCD_OPC_CheckPredicate, + 26, + 153, + 69, + 0, // Skip to: 19231 + /* 1414 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 146, + 69, + 0, // Skip to: 19231 + /* 1421 */ MCD_OPC_Decode, + 155, + 23, + 202, + 1, // Opcode: VMULLsv8i16 + /* 1426 */ MCD_OPC_FilterValue, + 231, + 3, + 135, + 69, + 0, // Skip to: 19231 + /* 1432 */ MCD_OPC_CheckPredicate, + 26, + 130, + 69, + 0, // Skip to: 19231 + /* 1437 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 123, + 69, + 0, // Skip to: 19231 + /* 1444 */ MCD_OPC_Decode, + 158, + 23, + 202, + 1, // Opcode: VMULLuv8i16 + /* 1449 */ MCD_OPC_FilterValue, + 13, + 66, + 0, + 0, // Skip to: 1520 + /* 1454 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1457 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 1497 + /* 1462 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1465 */ MCD_OPC_FilterValue, + 228, + 3, + 10, + 0, + 0, // Skip to: 1481 + /* 1471 */ MCD_OPC_CheckPredicate, + 26, + 91, + 69, + 0, // Skip to: 19231 + /* 1476 */ MCD_OPC_Decode, + 152, + 16, + 200, + 1, // Opcode: VADDfd + /* 1481 */ MCD_OPC_FilterValue, + 230, + 3, + 80, + 69, + 0, // Skip to: 19231 + /* 1487 */ MCD_OPC_CheckPredicate, + 26, + 75, + 69, + 0, // Skip to: 19231 + /* 1492 */ MCD_OPC_Decode, + 240, + 23, + 200, + 1, // Opcode: VPADDf + /* 1497 */ MCD_OPC_FilterValue, + 1, + 65, + 69, + 0, // Skip to: 19231 + /* 1502 */ MCD_OPC_CheckPredicate, + 26, + 60, + 69, + 0, // Skip to: 19231 + /* 1507 */ MCD_OPC_CheckField, + 23, + 9, + 228, + 3, + 52, + 69, + 0, // Skip to: 19231 + /* 1515 */ MCD_OPC_Decode, + 153, + 16, + 201, + 1, // Opcode: VADDfq + /* 1520 */ MCD_OPC_FilterValue, + 14, + 104, + 0, + 0, // Skip to: 1629 + /* 1525 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1528 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 1567 + /* 1534 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1537 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1552 + /* 1542 */ MCD_OPC_CheckPredicate, + 26, + 20, + 69, + 0, // Skip to: 19231 + /* 1547 */ MCD_OPC_Decode, + 188, + 16, + 200, + 1, // Opcode: VCEQfd + /* 1552 */ MCD_OPC_FilterValue, + 1, + 10, + 69, + 0, // Skip to: 19231 + /* 1557 */ MCD_OPC_CheckPredicate, + 26, + 5, + 69, + 0, // Skip to: 19231 + /* 1562 */ MCD_OPC_Decode, + 189, + 16, + 201, + 1, // Opcode: VCEQfq + /* 1567 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 1590 + /* 1573 */ MCD_OPC_CheckPredicate, + 26, + 245, + 68, + 0, // Skip to: 19231 + /* 1578 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 238, + 68, + 0, // Skip to: 19231 + /* 1585 */ MCD_OPC_Decode, + 148, + 23, + 202, + 1, // Opcode: VMULLp8 + /* 1590 */ MCD_OPC_FilterValue, + 230, + 3, + 227, + 68, + 0, // Skip to: 19231 + /* 1596 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1599 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1614 + /* 1604 */ MCD_OPC_CheckPredicate, + 26, + 214, + 68, + 0, // Skip to: 19231 + /* 1609 */ MCD_OPC_Decode, + 208, + 16, + 200, + 1, // Opcode: VCGEfd + /* 1614 */ MCD_OPC_FilterValue, + 1, + 204, + 68, + 0, // Skip to: 19231 + /* 1619 */ MCD_OPC_CheckPredicate, + 26, + 199, + 68, + 0, // Skip to: 19231 + /* 1624 */ MCD_OPC_Decode, + 209, + 16, + 201, + 1, // Opcode: VCGEfq + /* 1629 */ MCD_OPC_FilterValue, + 15, + 189, + 68, + 0, // Skip to: 19231 + /* 1634 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1637 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 1677 + /* 1642 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1645 */ MCD_OPC_FilterValue, + 228, + 3, + 10, + 0, + 0, // Skip to: 1661 + /* 1651 */ MCD_OPC_CheckPredicate, + 26, + 167, + 68, + 0, // Skip to: 19231 + /* 1656 */ MCD_OPC_Decode, + 253, + 21, + 200, + 1, // Opcode: VMAXfd + /* 1661 */ MCD_OPC_FilterValue, + 230, + 3, + 156, + 68, + 0, // Skip to: 19231 + /* 1667 */ MCD_OPC_CheckPredicate, + 26, + 151, + 68, + 0, // Skip to: 19231 + /* 1672 */ MCD_OPC_Decode, + 245, + 23, + 200, + 1, // Opcode: VPMAXf + /* 1677 */ MCD_OPC_FilterValue, + 1, + 141, + 68, + 0, // Skip to: 19231 + /* 1682 */ MCD_OPC_CheckPredicate, + 26, + 136, + 68, + 0, // Skip to: 19231 + /* 1687 */ MCD_OPC_CheckField, + 23, + 9, + 228, + 3, + 128, + 68, + 0, // Skip to: 19231 + /* 1695 */ MCD_OPC_Decode, + 254, + 21, + 201, + 1, // Opcode: VMAXfq + /* 1700 */ MCD_OPC_FilterValue, + 1, + 16, + 9, + 0, // Skip to: 4025 + /* 1705 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 1708 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 1872 + /* 1713 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1716 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 1755 + /* 1722 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1725 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1740 + /* 1730 */ MCD_OPC_CheckPredicate, + 26, + 88, + 68, + 0, // Skip to: 19231 + /* 1735 */ MCD_OPC_Decode, + 223, + 18, + 200, + 1, // Opcode: VHADDsv4i16 + /* 1740 */ MCD_OPC_FilterValue, + 1, + 78, + 68, + 0, // Skip to: 19231 + /* 1745 */ MCD_OPC_CheckPredicate, + 26, + 73, + 68, + 0, // Skip to: 19231 + /* 1750 */ MCD_OPC_Decode, + 225, + 18, + 201, + 1, // Opcode: VHADDsv8i16 + /* 1755 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 1794 + /* 1761 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1764 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1779 + /* 1769 */ MCD_OPC_CheckPredicate, + 26, + 49, + 68, + 0, // Skip to: 19231 + /* 1774 */ MCD_OPC_Decode, + 140, + 16, + 202, + 1, // Opcode: VADDLsv4i32 + /* 1779 */ MCD_OPC_FilterValue, + 1, + 39, + 68, + 0, // Skip to: 19231 + /* 1784 */ MCD_OPC_CheckPredicate, + 26, + 34, + 68, + 0, // Skip to: 19231 + /* 1789 */ MCD_OPC_Decode, + 179, + 22, + 210, + 1, // Opcode: VMLAslv4i16 + /* 1794 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 1833 + /* 1800 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1803 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1818 + /* 1808 */ MCD_OPC_CheckPredicate, + 26, + 10, + 68, + 0, // Skip to: 19231 + /* 1813 */ MCD_OPC_Decode, + 229, + 18, + 200, + 1, // Opcode: VHADDuv4i16 + /* 1818 */ MCD_OPC_FilterValue, + 1, + 0, + 68, + 0, // Skip to: 19231 + /* 1823 */ MCD_OPC_CheckPredicate, + 26, + 251, + 67, + 0, // Skip to: 19231 + /* 1828 */ MCD_OPC_Decode, + 231, + 18, + 201, + 1, // Opcode: VHADDuv8i16 + /* 1833 */ MCD_OPC_FilterValue, + 231, + 3, + 240, + 67, + 0, // Skip to: 19231 + /* 1839 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1842 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1857 + /* 1847 */ MCD_OPC_CheckPredicate, + 26, + 227, + 67, + 0, // Skip to: 19231 + /* 1852 */ MCD_OPC_Decode, + 143, + 16, + 202, + 1, // Opcode: VADDLuv4i32 + /* 1857 */ MCD_OPC_FilterValue, + 1, + 217, + 67, + 0, // Skip to: 19231 + /* 1862 */ MCD_OPC_CheckPredicate, + 26, + 212, + 67, + 0, // Skip to: 19231 + /* 1867 */ MCD_OPC_Decode, + 181, + 22, + 211, + 1, // Opcode: VMLAslv8i16 + /* 1872 */ MCD_OPC_FilterValue, + 1, + 159, + 0, + 0, // Skip to: 2036 + /* 1877 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1880 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 1919 + /* 1886 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1889 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1904 + /* 1894 */ MCD_OPC_CheckPredicate, + 26, + 180, + 67, + 0, // Skip to: 19231 + /* 1899 */ MCD_OPC_Decode, + 203, + 25, + 200, + 1, // Opcode: VRHADDsv4i16 + /* 1904 */ MCD_OPC_FilterValue, + 1, + 170, + 67, + 0, // Skip to: 19231 + /* 1909 */ MCD_OPC_CheckPredicate, + 26, + 165, + 67, + 0, // Skip to: 19231 + /* 1914 */ MCD_OPC_Decode, + 205, + 25, + 201, + 1, // Opcode: VRHADDsv8i16 + /* 1919 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 1958 + /* 1925 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1928 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1943 + /* 1933 */ MCD_OPC_CheckPredicate, + 26, + 141, + 67, + 0, // Skip to: 19231 + /* 1938 */ MCD_OPC_Decode, + 147, + 16, + 203, + 1, // Opcode: VADDWsv4i32 + /* 1943 */ MCD_OPC_FilterValue, + 1, + 131, + 67, + 0, // Skip to: 19231 + /* 1948 */ MCD_OPC_CheckPredicate, + 27, + 126, + 67, + 0, // Skip to: 19231 + /* 1953 */ MCD_OPC_Decode, + 176, + 22, + 210, + 1, // Opcode: VMLAslhd + /* 1958 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 1997 + /* 1964 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1967 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1982 + /* 1972 */ MCD_OPC_CheckPredicate, + 26, + 102, + 67, + 0, // Skip to: 19231 + /* 1977 */ MCD_OPC_Decode, + 209, + 25, + 200, + 1, // Opcode: VRHADDuv4i16 + /* 1982 */ MCD_OPC_FilterValue, + 1, + 92, + 67, + 0, // Skip to: 19231 + /* 1987 */ MCD_OPC_CheckPredicate, + 26, + 87, + 67, + 0, // Skip to: 19231 + /* 1992 */ MCD_OPC_Decode, + 211, + 25, + 201, + 1, // Opcode: VRHADDuv8i16 + /* 1997 */ MCD_OPC_FilterValue, + 231, + 3, + 76, + 67, + 0, // Skip to: 19231 + /* 2003 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2006 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2021 + /* 2011 */ MCD_OPC_CheckPredicate, + 26, + 63, + 67, + 0, // Skip to: 19231 + /* 2016 */ MCD_OPC_Decode, + 150, + 16, + 203, + 1, // Opcode: VADDWuv4i32 + /* 2021 */ MCD_OPC_FilterValue, + 1, + 53, + 67, + 0, // Skip to: 19231 + /* 2026 */ MCD_OPC_CheckPredicate, + 27, + 48, + 67, + 0, // Skip to: 19231 + /* 2031 */ MCD_OPC_Decode, + 177, + 22, + 211, + 1, // Opcode: VMLAslhq + /* 2036 */ MCD_OPC_FilterValue, + 2, + 159, + 0, + 0, // Skip to: 2200 + /* 2041 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2044 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2083 + /* 2050 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2053 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2068 + /* 2058 */ MCD_OPC_CheckPredicate, + 26, + 16, + 67, + 0, // Skip to: 19231 + /* 2063 */ MCD_OPC_Decode, + 235, + 18, + 200, + 1, // Opcode: VHSUBsv4i16 + /* 2068 */ MCD_OPC_FilterValue, + 1, + 6, + 67, + 0, // Skip to: 19231 + /* 2073 */ MCD_OPC_CheckPredicate, + 26, + 1, + 67, + 0, // Skip to: 19231 + /* 2078 */ MCD_OPC_Decode, + 237, + 18, + 201, + 1, // Opcode: VHSUBsv8i16 + /* 2083 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2122 + /* 2089 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2092 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2107 + /* 2097 */ MCD_OPC_CheckPredicate, + 26, + 233, + 66, + 0, // Skip to: 19231 + /* 2102 */ MCD_OPC_Decode, + 220, + 29, + 202, + 1, // Opcode: VSUBLsv4i32 + /* 2107 */ MCD_OPC_FilterValue, + 1, + 223, + 66, + 0, // Skip to: 19231 + /* 2112 */ MCD_OPC_CheckPredicate, + 26, + 218, + 66, + 0, // Skip to: 19231 + /* 2117 */ MCD_OPC_Decode, + 160, + 22, + 212, + 1, // Opcode: VMLALslsv4i16 + /* 2122 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2161 + /* 2128 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2131 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2146 + /* 2136 */ MCD_OPC_CheckPredicate, + 26, + 194, + 66, + 0, // Skip to: 19231 + /* 2141 */ MCD_OPC_Decode, + 241, + 18, + 200, + 1, // Opcode: VHSUBuv4i16 + /* 2146 */ MCD_OPC_FilterValue, + 1, + 184, + 66, + 0, // Skip to: 19231 + /* 2151 */ MCD_OPC_CheckPredicate, + 26, + 179, + 66, + 0, // Skip to: 19231 + /* 2156 */ MCD_OPC_Decode, + 243, + 18, + 201, + 1, // Opcode: VHSUBuv8i16 + /* 2161 */ MCD_OPC_FilterValue, + 231, + 3, + 168, + 66, + 0, // Skip to: 19231 + /* 2167 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2170 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2185 + /* 2175 */ MCD_OPC_CheckPredicate, + 26, + 155, + 66, + 0, // Skip to: 19231 + /* 2180 */ MCD_OPC_Decode, + 223, + 29, + 202, + 1, // Opcode: VSUBLuv4i32 + /* 2185 */ MCD_OPC_FilterValue, + 1, + 145, + 66, + 0, // Skip to: 19231 + /* 2190 */ MCD_OPC_CheckPredicate, + 26, + 140, + 66, + 0, // Skip to: 19231 + /* 2195 */ MCD_OPC_Decode, + 162, + 22, + 212, + 1, // Opcode: VMLALsluv4i16 + /* 2200 */ MCD_OPC_FilterValue, + 3, + 143, + 0, + 0, // Skip to: 2348 + /* 2205 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2208 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2247 + /* 2214 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2217 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2232 + /* 2222 */ MCD_OPC_CheckPredicate, + 26, + 108, + 66, + 0, // Skip to: 19231 + /* 2227 */ MCD_OPC_Decode, + 240, + 16, + 200, + 1, // Opcode: VCGTsv4i16 + /* 2232 */ MCD_OPC_FilterValue, + 1, + 98, + 66, + 0, // Skip to: 19231 + /* 2237 */ MCD_OPC_CheckPredicate, + 26, + 93, + 66, + 0, // Skip to: 19231 + /* 2242 */ MCD_OPC_Decode, + 242, + 16, + 201, + 1, // Opcode: VCGTsv8i16 + /* 2247 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2286 + /* 2253 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2256 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2271 + /* 2261 */ MCD_OPC_CheckPredicate, + 26, + 69, + 66, + 0, // Skip to: 19231 + /* 2266 */ MCD_OPC_Decode, + 227, + 29, + 203, + 1, // Opcode: VSUBWsv4i32 + /* 2271 */ MCD_OPC_FilterValue, + 1, + 59, + 66, + 0, // Skip to: 19231 + /* 2276 */ MCD_OPC_CheckPredicate, + 26, + 54, + 66, + 0, // Skip to: 19231 + /* 2281 */ MCD_OPC_Decode, + 156, + 24, + 212, + 1, // Opcode: VQDMLALslv4i16 + /* 2286 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2325 + /* 2292 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2295 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2310 + /* 2300 */ MCD_OPC_CheckPredicate, + 26, + 30, + 66, + 0, // Skip to: 19231 + /* 2305 */ MCD_OPC_Decode, + 246, + 16, + 200, + 1, // Opcode: VCGTuv4i16 + /* 2310 */ MCD_OPC_FilterValue, + 1, + 20, + 66, + 0, // Skip to: 19231 + /* 2315 */ MCD_OPC_CheckPredicate, + 26, + 15, + 66, + 0, // Skip to: 19231 + /* 2320 */ MCD_OPC_Decode, + 248, + 16, + 201, + 1, // Opcode: VCGTuv8i16 + /* 2325 */ MCD_OPC_FilterValue, + 231, + 3, + 4, + 66, + 0, // Skip to: 19231 + /* 2331 */ MCD_OPC_CheckPredicate, + 26, + 255, + 65, + 0, // Skip to: 19231 + /* 2336 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 248, + 65, + 0, // Skip to: 19231 + /* 2343 */ MCD_OPC_Decode, + 230, + 29, + 203, + 1, // Opcode: VSUBWuv4i32 + /* 2348 */ MCD_OPC_FilterValue, + 4, + 159, + 0, + 0, // Skip to: 2512 + /* 2353 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2356 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2395 + /* 2362 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2365 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2380 + /* 2370 */ MCD_OPC_CheckPredicate, + 26, + 216, + 65, + 0, // Skip to: 19231 + /* 2375 */ MCD_OPC_Decode, + 236, + 26, + 204, + 1, // Opcode: VSHLsv4i16 + /* 2380 */ MCD_OPC_FilterValue, + 1, + 206, + 65, + 0, // Skip to: 19231 + /* 2385 */ MCD_OPC_CheckPredicate, + 26, + 201, + 65, + 0, // Skip to: 19231 + /* 2390 */ MCD_OPC_Decode, + 238, + 26, + 205, + 1, // Opcode: VSHLsv8i16 + /* 2395 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2434 + /* 2401 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2404 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2419 + /* 2409 */ MCD_OPC_CheckPredicate, + 26, + 177, + 65, + 0, // Skip to: 19231 + /* 2414 */ MCD_OPC_Decode, + 137, + 16, + 206, + 1, // Opcode: VADDHNv4i16 + /* 2419 */ MCD_OPC_FilterValue, + 1, + 167, + 65, + 0, // Skip to: 19231 + /* 2424 */ MCD_OPC_CheckPredicate, + 26, + 162, + 65, + 0, // Skip to: 19231 + /* 2429 */ MCD_OPC_Decode, + 210, + 22, + 210, + 1, // Opcode: VMLSslv4i16 + /* 2434 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2473 + /* 2440 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2443 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2458 + /* 2448 */ MCD_OPC_CheckPredicate, + 26, + 138, + 65, + 0, // Skip to: 19231 + /* 2453 */ MCD_OPC_Decode, + 244, + 26, + 204, + 1, // Opcode: VSHLuv4i16 + /* 2458 */ MCD_OPC_FilterValue, + 1, + 128, + 65, + 0, // Skip to: 19231 + /* 2463 */ MCD_OPC_CheckPredicate, + 26, + 123, + 65, + 0, // Skip to: 19231 + /* 2468 */ MCD_OPC_Decode, + 246, + 26, + 205, + 1, // Opcode: VSHLuv8i16 + /* 2473 */ MCD_OPC_FilterValue, + 231, + 3, + 112, + 65, + 0, // Skip to: 19231 + /* 2479 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2482 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2497 + /* 2487 */ MCD_OPC_CheckPredicate, + 26, + 99, + 65, + 0, // Skip to: 19231 + /* 2492 */ MCD_OPC_Decode, + 177, + 25, + 206, + 1, // Opcode: VRADDHNv4i16 + /* 2497 */ MCD_OPC_FilterValue, + 1, + 89, + 65, + 0, // Skip to: 19231 + /* 2502 */ MCD_OPC_CheckPredicate, + 26, + 84, + 65, + 0, // Skip to: 19231 + /* 2507 */ MCD_OPC_Decode, + 212, + 22, + 211, + 1, // Opcode: VMLSslv8i16 + /* 2512 */ MCD_OPC_FilterValue, + 5, + 159, + 0, + 0, // Skip to: 2676 + /* 2517 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2520 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2559 + /* 2526 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2529 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2544 + /* 2534 */ MCD_OPC_CheckPredicate, + 26, + 52, + 65, + 0, // Skip to: 19231 + /* 2539 */ MCD_OPC_Decode, + 134, + 26, + 204, + 1, // Opcode: VRSHLsv4i16 + /* 2544 */ MCD_OPC_FilterValue, + 1, + 42, + 65, + 0, // Skip to: 19231 + /* 2549 */ MCD_OPC_CheckPredicate, + 26, + 37, + 65, + 0, // Skip to: 19231 + /* 2554 */ MCD_OPC_Decode, + 136, + 26, + 205, + 1, // Opcode: VRSHLsv8i16 + /* 2559 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2598 + /* 2565 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2568 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2583 + /* 2573 */ MCD_OPC_CheckPredicate, + 26, + 13, + 65, + 0, // Skip to: 19231 + /* 2578 */ MCD_OPC_Decode, + 202, + 15, + 207, + 1, // Opcode: VABALsv4i32 + /* 2583 */ MCD_OPC_FilterValue, + 1, + 3, + 65, + 0, // Skip to: 19231 + /* 2588 */ MCD_OPC_CheckPredicate, + 27, + 254, + 64, + 0, // Skip to: 19231 + /* 2593 */ MCD_OPC_Decode, + 207, + 22, + 210, + 1, // Opcode: VMLSslhd + /* 2598 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2637 + /* 2604 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2607 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2622 + /* 2612 */ MCD_OPC_CheckPredicate, + 26, + 230, + 64, + 0, // Skip to: 19231 + /* 2617 */ MCD_OPC_Decode, + 142, + 26, + 204, + 1, // Opcode: VRSHLuv4i16 + /* 2622 */ MCD_OPC_FilterValue, + 1, + 220, + 64, + 0, // Skip to: 19231 + /* 2627 */ MCD_OPC_CheckPredicate, + 26, + 215, + 64, + 0, // Skip to: 19231 + /* 2632 */ MCD_OPC_Decode, + 144, + 26, + 205, + 1, // Opcode: VRSHLuv8i16 + /* 2637 */ MCD_OPC_FilterValue, + 231, + 3, + 204, + 64, + 0, // Skip to: 19231 + /* 2643 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2646 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2661 + /* 2651 */ MCD_OPC_CheckPredicate, + 26, + 191, + 64, + 0, // Skip to: 19231 + /* 2656 */ MCD_OPC_Decode, + 205, + 15, + 207, + 1, // Opcode: VABALuv4i32 + /* 2661 */ MCD_OPC_FilterValue, + 1, + 181, + 64, + 0, // Skip to: 19231 + /* 2666 */ MCD_OPC_CheckPredicate, + 27, + 176, + 64, + 0, // Skip to: 19231 + /* 2671 */ MCD_OPC_Decode, + 208, + 22, + 211, + 1, // Opcode: VMLSslhq + /* 2676 */ MCD_OPC_FilterValue, + 6, + 159, + 0, + 0, // Skip to: 2840 + /* 2681 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2684 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2723 + /* 2690 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2693 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2708 + /* 2698 */ MCD_OPC_CheckPredicate, + 26, + 144, + 64, + 0, // Skip to: 19231 + /* 2703 */ MCD_OPC_Decode, + 131, + 22, + 200, + 1, // Opcode: VMAXsv4i16 + /* 2708 */ MCD_OPC_FilterValue, + 1, + 134, + 64, + 0, // Skip to: 19231 + /* 2713 */ MCD_OPC_CheckPredicate, + 26, + 129, + 64, + 0, // Skip to: 19231 + /* 2718 */ MCD_OPC_Decode, + 133, + 22, + 201, + 1, // Opcode: VMAXsv8i16 + /* 2723 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2762 + /* 2729 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2732 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2747 + /* 2737 */ MCD_OPC_CheckPredicate, + 26, + 105, + 64, + 0, // Skip to: 19231 + /* 2742 */ MCD_OPC_Decode, + 217, + 29, + 206, + 1, // Opcode: VSUBHNv4i16 + /* 2747 */ MCD_OPC_FilterValue, + 1, + 95, + 64, + 0, // Skip to: 19231 + /* 2752 */ MCD_OPC_CheckPredicate, + 26, + 90, + 64, + 0, // Skip to: 19231 + /* 2757 */ MCD_OPC_Decode, + 191, + 22, + 212, + 1, // Opcode: VMLSLslsv4i16 + /* 2762 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2801 + /* 2768 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2771 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2786 + /* 2776 */ MCD_OPC_CheckPredicate, + 26, + 66, + 64, + 0, // Skip to: 19231 + /* 2781 */ MCD_OPC_Decode, + 137, + 22, + 200, + 1, // Opcode: VMAXuv4i16 + /* 2786 */ MCD_OPC_FilterValue, + 1, + 56, + 64, + 0, // Skip to: 19231 + /* 2791 */ MCD_OPC_CheckPredicate, + 26, + 51, + 64, + 0, // Skip to: 19231 + /* 2796 */ MCD_OPC_Decode, + 139, + 22, + 201, + 1, // Opcode: VMAXuv8i16 + /* 2801 */ MCD_OPC_FilterValue, + 231, + 3, + 40, + 64, + 0, // Skip to: 19231 + /* 2807 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2810 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2825 + /* 2815 */ MCD_OPC_CheckPredicate, + 26, + 27, + 64, + 0, // Skip to: 19231 + /* 2820 */ MCD_OPC_Decode, + 192, + 26, + 206, + 1, // Opcode: VRSUBHNv4i16 + /* 2825 */ MCD_OPC_FilterValue, + 1, + 17, + 64, + 0, // Skip to: 19231 + /* 2830 */ MCD_OPC_CheckPredicate, + 26, + 12, + 64, + 0, // Skip to: 19231 + /* 2835 */ MCD_OPC_Decode, + 193, + 22, + 212, + 1, // Opcode: VMLSLsluv4i16 + /* 2840 */ MCD_OPC_FilterValue, + 7, + 143, + 0, + 0, // Skip to: 2988 + /* 2845 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2848 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 2887 + /* 2854 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2857 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2872 + /* 2862 */ MCD_OPC_CheckPredicate, + 26, + 236, + 63, + 0, // Skip to: 19231 + /* 2867 */ MCD_OPC_Decode, + 231, + 15, + 200, + 1, // Opcode: VABDsv4i16 + /* 2872 */ MCD_OPC_FilterValue, + 1, + 226, + 63, + 0, // Skip to: 19231 + /* 2877 */ MCD_OPC_CheckPredicate, + 26, + 221, + 63, + 0, // Skip to: 19231 + /* 2882 */ MCD_OPC_Decode, + 233, + 15, + 201, + 1, // Opcode: VABDsv8i16 + /* 2887 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 2926 + /* 2893 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2896 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2911 + /* 2901 */ MCD_OPC_CheckPredicate, + 26, + 197, + 63, + 0, // Skip to: 19231 + /* 2906 */ MCD_OPC_Decode, + 220, + 15, + 202, + 1, // Opcode: VABDLsv4i32 + /* 2911 */ MCD_OPC_FilterValue, + 1, + 187, + 63, + 0, // Skip to: 19231 + /* 2916 */ MCD_OPC_CheckPredicate, + 26, + 182, + 63, + 0, // Skip to: 19231 + /* 2921 */ MCD_OPC_Decode, + 160, + 24, + 212, + 1, // Opcode: VQDMLSLslv4i16 + /* 2926 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 2965 + /* 2932 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2935 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2950 + /* 2940 */ MCD_OPC_CheckPredicate, + 26, + 158, + 63, + 0, // Skip to: 19231 + /* 2945 */ MCD_OPC_Decode, + 237, + 15, + 200, + 1, // Opcode: VABDuv4i16 + /* 2950 */ MCD_OPC_FilterValue, + 1, + 148, + 63, + 0, // Skip to: 19231 + /* 2955 */ MCD_OPC_CheckPredicate, + 26, + 143, + 63, + 0, // Skip to: 19231 + /* 2960 */ MCD_OPC_Decode, + 239, + 15, + 201, + 1, // Opcode: VABDuv8i16 + /* 2965 */ MCD_OPC_FilterValue, + 231, + 3, + 132, + 63, + 0, // Skip to: 19231 + /* 2971 */ MCD_OPC_CheckPredicate, + 26, + 127, + 63, + 0, // Skip to: 19231 + /* 2976 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 120, + 63, + 0, // Skip to: 19231 + /* 2983 */ MCD_OPC_Decode, + 223, + 15, + 202, + 1, // Opcode: VABDLuv4i32 + /* 2988 */ MCD_OPC_FilterValue, + 8, + 159, + 0, + 0, // Skip to: 3152 + /* 2993 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2996 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3035 + /* 3002 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3005 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3020 + /* 3010 */ MCD_OPC_CheckPredicate, + 26, + 88, + 63, + 0, // Skip to: 19231 + /* 3015 */ MCD_OPC_Decode, + 160, + 16, + 200, + 1, // Opcode: VADDv4i16 + /* 3020 */ MCD_OPC_FilterValue, + 1, + 78, + 63, + 0, // Skip to: 19231 + /* 3025 */ MCD_OPC_CheckPredicate, + 26, + 73, + 63, + 0, // Skip to: 19231 + /* 3030 */ MCD_OPC_Decode, + 162, + 16, + 201, + 1, // Opcode: VADDv8i16 + /* 3035 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3074 + /* 3041 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3044 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3059 + /* 3049 */ MCD_OPC_CheckPredicate, + 26, + 49, + 63, + 0, // Skip to: 19231 + /* 3054 */ MCD_OPC_Decode, + 164, + 22, + 207, + 1, // Opcode: VMLALsv4i32 + /* 3059 */ MCD_OPC_FilterValue, + 1, + 39, + 63, + 0, // Skip to: 19231 + /* 3064 */ MCD_OPC_CheckPredicate, + 26, + 34, + 63, + 0, // Skip to: 19231 + /* 3069 */ MCD_OPC_Decode, + 171, + 23, + 213, + 1, // Opcode: VMULslv4i16 + /* 3074 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 3113 + /* 3080 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3083 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3098 + /* 3088 */ MCD_OPC_CheckPredicate, + 26, + 10, + 63, + 0, // Skip to: 19231 + /* 3093 */ MCD_OPC_Decode, + 240, + 29, + 200, + 1, // Opcode: VSUBv4i16 + /* 3098 */ MCD_OPC_FilterValue, + 1, + 0, + 63, + 0, // Skip to: 19231 + /* 3103 */ MCD_OPC_CheckPredicate, + 26, + 251, + 62, + 0, // Skip to: 19231 + /* 3108 */ MCD_OPC_Decode, + 242, + 29, + 201, + 1, // Opcode: VSUBv8i16 + /* 3113 */ MCD_OPC_FilterValue, + 231, + 3, + 240, + 62, + 0, // Skip to: 19231 + /* 3119 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3122 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3137 + /* 3127 */ MCD_OPC_CheckPredicate, + 26, + 227, + 62, + 0, // Skip to: 19231 + /* 3132 */ MCD_OPC_Decode, + 167, + 22, + 207, + 1, // Opcode: VMLALuv4i32 + /* 3137 */ MCD_OPC_FilterValue, + 1, + 217, + 62, + 0, // Skip to: 19231 + /* 3142 */ MCD_OPC_CheckPredicate, + 26, + 212, + 62, + 0, // Skip to: 19231 + /* 3147 */ MCD_OPC_Decode, + 173, + 23, + 214, + 1, // Opcode: VMULslv8i16 + /* 3152 */ MCD_OPC_FilterValue, + 9, + 143, + 0, + 0, // Skip to: 3300 + /* 3157 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3160 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3199 + /* 3166 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3169 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3184 + /* 3174 */ MCD_OPC_CheckPredicate, + 26, + 180, + 62, + 0, // Skip to: 19231 + /* 3179 */ MCD_OPC_Decode, + 184, + 22, + 208, + 1, // Opcode: VMLAv4i16 + /* 3184 */ MCD_OPC_FilterValue, + 1, + 170, + 62, + 0, // Skip to: 19231 + /* 3189 */ MCD_OPC_CheckPredicate, + 26, + 165, + 62, + 0, // Skip to: 19231 + /* 3194 */ MCD_OPC_Decode, + 186, + 22, + 209, + 1, // Opcode: VMLAv8i16 + /* 3199 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3238 + /* 3205 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3208 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3223 + /* 3213 */ MCD_OPC_CheckPredicate, + 26, + 141, + 62, + 0, // Skip to: 19231 + /* 3218 */ MCD_OPC_Decode, + 158, + 24, + 207, + 1, // Opcode: VQDMLALv4i32 + /* 3223 */ MCD_OPC_FilterValue, + 1, + 131, + 62, + 0, // Skip to: 19231 + /* 3228 */ MCD_OPC_CheckPredicate, + 27, + 126, + 62, + 0, // Skip to: 19231 + /* 3233 */ MCD_OPC_Decode, + 168, + 23, + 213, + 1, // Opcode: VMULslhd + /* 3238 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 3277 + /* 3244 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3247 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3262 + /* 3252 */ MCD_OPC_CheckPredicate, + 26, + 102, + 62, + 0, // Skip to: 19231 + /* 3257 */ MCD_OPC_Decode, + 215, + 22, + 208, + 1, // Opcode: VMLSv4i16 + /* 3262 */ MCD_OPC_FilterValue, + 1, + 92, + 62, + 0, // Skip to: 19231 + /* 3267 */ MCD_OPC_CheckPredicate, + 26, + 87, + 62, + 0, // Skip to: 19231 + /* 3272 */ MCD_OPC_Decode, + 217, + 22, + 209, + 1, // Opcode: VMLSv8i16 + /* 3277 */ MCD_OPC_FilterValue, + 231, + 3, + 76, + 62, + 0, // Skip to: 19231 + /* 3283 */ MCD_OPC_CheckPredicate, + 27, + 71, + 62, + 0, // Skip to: 19231 + /* 3288 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 64, + 62, + 0, // Skip to: 19231 + /* 3295 */ MCD_OPC_Decode, + 169, + 23, + 214, + 1, // Opcode: VMULslhq + /* 3300 */ MCD_OPC_FilterValue, + 10, + 127, + 0, + 0, // Skip to: 3432 + /* 3305 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3308 */ MCD_OPC_FilterValue, + 228, + 3, + 17, + 0, + 0, // Skip to: 3331 + /* 3314 */ MCD_OPC_CheckPredicate, + 26, + 40, + 62, + 0, // Skip to: 19231 + /* 3319 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 33, + 62, + 0, // Skip to: 19231 + /* 3326 */ MCD_OPC_Decode, + 247, + 23, + 200, + 1, // Opcode: VPMAXs16 + /* 3331 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3370 + /* 3337 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3340 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3355 + /* 3345 */ MCD_OPC_CheckPredicate, + 26, + 9, + 62, + 0, // Skip to: 19231 + /* 3350 */ MCD_OPC_Decode, + 195, + 22, + 207, + 1, // Opcode: VMLSLsv4i32 + /* 3355 */ MCD_OPC_FilterValue, + 1, + 255, + 61, + 0, // Skip to: 19231 + /* 3360 */ MCD_OPC_CheckPredicate, + 26, + 250, + 61, + 0, // Skip to: 19231 + /* 3365 */ MCD_OPC_Decode, + 150, + 23, + 215, + 1, // Opcode: VMULLslsv4i16 + /* 3370 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 3393 + /* 3376 */ MCD_OPC_CheckPredicate, + 26, + 234, + 61, + 0, // Skip to: 19231 + /* 3381 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 227, + 61, + 0, // Skip to: 19231 + /* 3388 */ MCD_OPC_Decode, + 250, + 23, + 200, + 1, // Opcode: VPMAXu16 + /* 3393 */ MCD_OPC_FilterValue, + 231, + 3, + 216, + 61, + 0, // Skip to: 19231 + /* 3399 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3402 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3417 + /* 3407 */ MCD_OPC_CheckPredicate, + 26, + 203, + 61, + 0, // Skip to: 19231 + /* 3412 */ MCD_OPC_Decode, + 198, + 22, + 207, + 1, // Opcode: VMLSLuv4i32 + /* 3417 */ MCD_OPC_FilterValue, + 1, + 193, + 61, + 0, // Skip to: 19231 + /* 3422 */ MCD_OPC_CheckPredicate, + 26, + 188, + 61, + 0, // Skip to: 19231 + /* 3427 */ MCD_OPC_Decode, + 152, + 23, + 215, + 1, // Opcode: VMULLsluv4i16 + /* 3432 */ MCD_OPC_FilterValue, + 11, + 120, + 0, + 0, // Skip to: 3557 + /* 3437 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3440 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3479 + /* 3446 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3449 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3464 + /* 3454 */ MCD_OPC_CheckPredicate, + 26, + 156, + 61, + 0, // Skip to: 19231 + /* 3459 */ MCD_OPC_Decode, + 168, + 24, + 200, + 1, // Opcode: VQDMULHv4i16 + /* 3464 */ MCD_OPC_FilterValue, + 1, + 146, + 61, + 0, // Skip to: 19231 + /* 3469 */ MCD_OPC_CheckPredicate, + 26, + 141, + 61, + 0, // Skip to: 19231 + /* 3474 */ MCD_OPC_Decode, + 170, + 24, + 201, + 1, // Opcode: VQDMULHv8i16 + /* 3479 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3518 + /* 3485 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3488 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3503 + /* 3493 */ MCD_OPC_CheckPredicate, + 26, + 117, + 61, + 0, // Skip to: 19231 + /* 3498 */ MCD_OPC_Decode, + 162, + 24, + 207, + 1, // Opcode: VQDMLSLv4i32 + /* 3503 */ MCD_OPC_FilterValue, + 1, + 107, + 61, + 0, // Skip to: 19231 + /* 3508 */ MCD_OPC_CheckPredicate, + 26, + 102, + 61, + 0, // Skip to: 19231 + /* 3513 */ MCD_OPC_Decode, + 172, + 24, + 215, + 1, // Opcode: VQDMULLslv4i16 + /* 3518 */ MCD_OPC_FilterValue, + 230, + 3, + 91, + 61, + 0, // Skip to: 19231 + /* 3524 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3527 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3542 + /* 3532 */ MCD_OPC_CheckPredicate, + 26, + 78, + 61, + 0, // Skip to: 19231 + /* 3537 */ MCD_OPC_Decode, + 211, + 24, + 200, + 1, // Opcode: VQRDMULHv4i16 + /* 3542 */ MCD_OPC_FilterValue, + 1, + 68, + 61, + 0, // Skip to: 19231 + /* 3547 */ MCD_OPC_CheckPredicate, + 26, + 63, + 61, + 0, // Skip to: 19231 + /* 3552 */ MCD_OPC_Decode, + 213, + 24, + 201, + 1, // Opcode: VQRDMULHv8i16 + /* 3557 */ MCD_OPC_FilterValue, + 12, + 83, + 0, + 0, // Skip to: 3645 + /* 3562 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3565 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 3605 + /* 3570 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3573 */ MCD_OPC_FilterValue, + 229, + 3, + 10, + 0, + 0, // Skip to: 3589 + /* 3579 */ MCD_OPC_CheckPredicate, + 26, + 31, + 61, + 0, // Skip to: 19231 + /* 3584 */ MCD_OPC_Decode, + 154, + 23, + 202, + 1, // Opcode: VMULLsv4i32 + /* 3589 */ MCD_OPC_FilterValue, + 231, + 3, + 20, + 61, + 0, // Skip to: 19231 + /* 3595 */ MCD_OPC_CheckPredicate, + 26, + 15, + 61, + 0, // Skip to: 19231 + /* 3600 */ MCD_OPC_Decode, + 157, + 23, + 202, + 1, // Opcode: VMULLuv4i32 + /* 3605 */ MCD_OPC_FilterValue, + 1, + 5, + 61, + 0, // Skip to: 19231 + /* 3610 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3613 */ MCD_OPC_FilterValue, + 229, + 3, + 10, + 0, + 0, // Skip to: 3629 + /* 3619 */ MCD_OPC_CheckPredicate, + 26, + 247, + 60, + 0, // Skip to: 19231 + /* 3624 */ MCD_OPC_Decode, + 164, + 24, + 213, + 1, // Opcode: VQDMULHslv4i16 + /* 3629 */ MCD_OPC_FilterValue, + 231, + 3, + 236, + 60, + 0, // Skip to: 19231 + /* 3635 */ MCD_OPC_CheckPredicate, + 26, + 231, + 60, + 0, // Skip to: 19231 + /* 3640 */ MCD_OPC_Decode, + 166, + 24, + 214, + 1, // Opcode: VQDMULHslv8i16 + /* 3645 */ MCD_OPC_FilterValue, + 13, + 127, + 0, + 0, // Skip to: 3777 + /* 3650 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3653 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3692 + /* 3659 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3662 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3677 + /* 3667 */ MCD_OPC_CheckPredicate, + 27, + 199, + 60, + 0, // Skip to: 19231 + /* 3672 */ MCD_OPC_Decode, + 154, + 16, + 200, + 1, // Opcode: VADDhd + /* 3677 */ MCD_OPC_FilterValue, + 1, + 189, + 60, + 0, // Skip to: 19231 + /* 3682 */ MCD_OPC_CheckPredicate, + 27, + 184, + 60, + 0, // Skip to: 19231 + /* 3687 */ MCD_OPC_Decode, + 155, + 16, + 201, + 1, // Opcode: VADDhq + /* 3692 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 3731 + /* 3698 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3701 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3716 + /* 3706 */ MCD_OPC_CheckPredicate, + 26, + 160, + 60, + 0, // Skip to: 19231 + /* 3711 */ MCD_OPC_Decode, + 174, + 24, + 202, + 1, // Opcode: VQDMULLv4i32 + /* 3716 */ MCD_OPC_FilterValue, + 1, + 150, + 60, + 0, // Skip to: 19231 + /* 3721 */ MCD_OPC_CheckPredicate, + 26, + 145, + 60, + 0, // Skip to: 19231 + /* 3726 */ MCD_OPC_Decode, + 207, + 24, + 213, + 1, // Opcode: VQRDMULHslv4i16 + /* 3731 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 3754 + /* 3737 */ MCD_OPC_CheckPredicate, + 27, + 129, + 60, + 0, // Skip to: 19231 + /* 3742 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 122, + 60, + 0, // Skip to: 19231 + /* 3749 */ MCD_OPC_Decode, + 241, + 23, + 200, + 1, // Opcode: VPADDh + /* 3754 */ MCD_OPC_FilterValue, + 231, + 3, + 111, + 60, + 0, // Skip to: 19231 + /* 3760 */ MCD_OPC_CheckPredicate, + 26, + 106, + 60, + 0, // Skip to: 19231 + /* 3765 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 99, + 60, + 0, // Skip to: 19231 + /* 3772 */ MCD_OPC_Decode, + 209, + 24, + 214, + 1, // Opcode: VQRDMULHslv8i16 + /* 3777 */ MCD_OPC_FilterValue, + 14, + 127, + 0, + 0, // Skip to: 3909 + /* 3782 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3785 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3824 + /* 3791 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3794 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3809 + /* 3799 */ MCD_OPC_CheckPredicate, + 27, + 67, + 60, + 0, // Skip to: 19231 + /* 3804 */ MCD_OPC_Decode, + 190, + 16, + 200, + 1, // Opcode: VCEQhd + /* 3809 */ MCD_OPC_FilterValue, + 1, + 57, + 60, + 0, // Skip to: 19231 + /* 3814 */ MCD_OPC_CheckPredicate, + 27, + 52, + 60, + 0, // Skip to: 19231 + /* 3819 */ MCD_OPC_Decode, + 191, + 16, + 201, + 1, // Opcode: VCEQhq + /* 3824 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 3847 + /* 3830 */ MCD_OPC_CheckPredicate, + 28, + 36, + 60, + 0, // Skip to: 19231 + /* 3835 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 29, + 60, + 0, // Skip to: 19231 + /* 3842 */ MCD_OPC_Decode, + 191, + 24, + 210, + 1, // Opcode: VQRDMLAHslv4i16 + /* 3847 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 3886 + /* 3853 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3856 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3871 + /* 3861 */ MCD_OPC_CheckPredicate, + 27, + 5, + 60, + 0, // Skip to: 19231 + /* 3866 */ MCD_OPC_Decode, + 210, + 16, + 200, + 1, // Opcode: VCGEhd + /* 3871 */ MCD_OPC_FilterValue, + 1, + 251, + 59, + 0, // Skip to: 19231 + /* 3876 */ MCD_OPC_CheckPredicate, + 27, + 246, + 59, + 0, // Skip to: 19231 + /* 3881 */ MCD_OPC_Decode, + 211, + 16, + 201, + 1, // Opcode: VCGEhq + /* 3886 */ MCD_OPC_FilterValue, + 231, + 3, + 235, + 59, + 0, // Skip to: 19231 + /* 3892 */ MCD_OPC_CheckPredicate, + 28, + 230, + 59, + 0, // Skip to: 19231 + /* 3897 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 223, + 59, + 0, // Skip to: 19231 + /* 3904 */ MCD_OPC_Decode, + 193, + 24, + 211, + 1, // Opcode: VQRDMLAHslv8i16 + /* 3909 */ MCD_OPC_FilterValue, + 15, + 213, + 59, + 0, // Skip to: 19231 + /* 3914 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3917 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 3956 + /* 3923 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3926 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3941 + /* 3931 */ MCD_OPC_CheckPredicate, + 27, + 191, + 59, + 0, // Skip to: 19231 + /* 3936 */ MCD_OPC_Decode, + 255, + 21, + 200, + 1, // Opcode: VMAXhd + /* 3941 */ MCD_OPC_FilterValue, + 1, + 181, + 59, + 0, // Skip to: 19231 + /* 3946 */ MCD_OPC_CheckPredicate, + 27, + 176, + 59, + 0, // Skip to: 19231 + /* 3951 */ MCD_OPC_Decode, + 128, + 22, + 201, + 1, // Opcode: VMAXhq + /* 3956 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 3979 + /* 3962 */ MCD_OPC_CheckPredicate, + 28, + 160, + 59, + 0, // Skip to: 19231 + /* 3967 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 153, + 59, + 0, // Skip to: 19231 + /* 3974 */ MCD_OPC_Decode, + 199, + 24, + 210, + 1, // Opcode: VQRDMLSHslv4i16 + /* 3979 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 4002 + /* 3985 */ MCD_OPC_CheckPredicate, + 27, + 137, + 59, + 0, // Skip to: 19231 + /* 3990 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 130, + 59, + 0, // Skip to: 19231 + /* 3997 */ MCD_OPC_Decode, + 246, + 23, + 200, + 1, // Opcode: VPMAXh + /* 4002 */ MCD_OPC_FilterValue, + 231, + 3, + 119, + 59, + 0, // Skip to: 19231 + /* 4008 */ MCD_OPC_CheckPredicate, + 28, + 114, + 59, + 0, // Skip to: 19231 + /* 4013 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 107, + 59, + 0, // Skip to: 19231 + /* 4020 */ MCD_OPC_Decode, + 201, + 24, + 211, + 1, // Opcode: VQRDMLSHslv8i16 + /* 4025 */ MCD_OPC_FilterValue, + 2, + 9, + 9, + 0, // Skip to: 6343 + /* 4030 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 4033 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 4197 + /* 4038 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4041 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4080 + /* 4047 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4050 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4065 + /* 4055 */ MCD_OPC_CheckPredicate, + 26, + 67, + 59, + 0, // Skip to: 19231 + /* 4060 */ MCD_OPC_Decode, + 222, + 18, + 200, + 1, // Opcode: VHADDsv2i32 + /* 4065 */ MCD_OPC_FilterValue, + 1, + 57, + 59, + 0, // Skip to: 19231 + /* 4070 */ MCD_OPC_CheckPredicate, + 26, + 52, + 59, + 0, // Skip to: 19231 + /* 4075 */ MCD_OPC_Decode, + 224, + 18, + 201, + 1, // Opcode: VHADDsv4i32 + /* 4080 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4119 + /* 4086 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4089 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4104 + /* 4094 */ MCD_OPC_CheckPredicate, + 26, + 28, + 59, + 0, // Skip to: 19231 + /* 4099 */ MCD_OPC_Decode, + 139, + 16, + 202, + 1, // Opcode: VADDLsv2i64 + /* 4104 */ MCD_OPC_FilterValue, + 1, + 18, + 59, + 0, // Skip to: 19231 + /* 4109 */ MCD_OPC_CheckPredicate, + 26, + 13, + 59, + 0, // Skip to: 19231 + /* 4114 */ MCD_OPC_Decode, + 178, + 22, + 216, + 1, // Opcode: VMLAslv2i32 + /* 4119 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4158 + /* 4125 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4128 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4143 + /* 4133 */ MCD_OPC_CheckPredicate, + 26, + 245, + 58, + 0, // Skip to: 19231 + /* 4138 */ MCD_OPC_Decode, + 228, + 18, + 200, + 1, // Opcode: VHADDuv2i32 + /* 4143 */ MCD_OPC_FilterValue, + 1, + 235, + 58, + 0, // Skip to: 19231 + /* 4148 */ MCD_OPC_CheckPredicate, + 26, + 230, + 58, + 0, // Skip to: 19231 + /* 4153 */ MCD_OPC_Decode, + 230, + 18, + 201, + 1, // Opcode: VHADDuv4i32 + /* 4158 */ MCD_OPC_FilterValue, + 231, + 3, + 219, + 58, + 0, // Skip to: 19231 + /* 4164 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4167 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4182 + /* 4172 */ MCD_OPC_CheckPredicate, + 26, + 206, + 58, + 0, // Skip to: 19231 + /* 4177 */ MCD_OPC_Decode, + 142, + 16, + 202, + 1, // Opcode: VADDLuv2i64 + /* 4182 */ MCD_OPC_FilterValue, + 1, + 196, + 58, + 0, // Skip to: 19231 + /* 4187 */ MCD_OPC_CheckPredicate, + 26, + 191, + 58, + 0, // Skip to: 19231 + /* 4192 */ MCD_OPC_Decode, + 180, + 22, + 217, + 1, // Opcode: VMLAslv4i32 + /* 4197 */ MCD_OPC_FilterValue, + 1, + 159, + 0, + 0, // Skip to: 4361 + /* 4202 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4205 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4244 + /* 4211 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4214 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4229 + /* 4219 */ MCD_OPC_CheckPredicate, + 26, + 159, + 58, + 0, // Skip to: 19231 + /* 4224 */ MCD_OPC_Decode, + 202, + 25, + 200, + 1, // Opcode: VRHADDsv2i32 + /* 4229 */ MCD_OPC_FilterValue, + 1, + 149, + 58, + 0, // Skip to: 19231 + /* 4234 */ MCD_OPC_CheckPredicate, + 26, + 144, + 58, + 0, // Skip to: 19231 + /* 4239 */ MCD_OPC_Decode, + 204, + 25, + 201, + 1, // Opcode: VRHADDsv4i32 + /* 4244 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4283 + /* 4250 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4253 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4268 + /* 4258 */ MCD_OPC_CheckPredicate, + 26, + 120, + 58, + 0, // Skip to: 19231 + /* 4263 */ MCD_OPC_Decode, + 146, + 16, + 203, + 1, // Opcode: VADDWsv2i64 + /* 4268 */ MCD_OPC_FilterValue, + 1, + 110, + 58, + 0, // Skip to: 19231 + /* 4273 */ MCD_OPC_CheckPredicate, + 26, + 105, + 58, + 0, // Skip to: 19231 + /* 4278 */ MCD_OPC_Decode, + 174, + 22, + 216, + 1, // Opcode: VMLAslfd + /* 4283 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4322 + /* 4289 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4292 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4307 + /* 4297 */ MCD_OPC_CheckPredicate, + 26, + 81, + 58, + 0, // Skip to: 19231 + /* 4302 */ MCD_OPC_Decode, + 208, + 25, + 200, + 1, // Opcode: VRHADDuv2i32 + /* 4307 */ MCD_OPC_FilterValue, + 1, + 71, + 58, + 0, // Skip to: 19231 + /* 4312 */ MCD_OPC_CheckPredicate, + 26, + 66, + 58, + 0, // Skip to: 19231 + /* 4317 */ MCD_OPC_Decode, + 210, + 25, + 201, + 1, // Opcode: VRHADDuv4i32 + /* 4322 */ MCD_OPC_FilterValue, + 231, + 3, + 55, + 58, + 0, // Skip to: 19231 + /* 4328 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4331 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4346 + /* 4336 */ MCD_OPC_CheckPredicate, + 26, + 42, + 58, + 0, // Skip to: 19231 + /* 4341 */ MCD_OPC_Decode, + 149, + 16, + 203, + 1, // Opcode: VADDWuv2i64 + /* 4346 */ MCD_OPC_FilterValue, + 1, + 32, + 58, + 0, // Skip to: 19231 + /* 4351 */ MCD_OPC_CheckPredicate, + 26, + 27, + 58, + 0, // Skip to: 19231 + /* 4356 */ MCD_OPC_Decode, + 175, + 22, + 217, + 1, // Opcode: VMLAslfq + /* 4361 */ MCD_OPC_FilterValue, + 2, + 159, + 0, + 0, // Skip to: 4525 + /* 4366 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4369 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4408 + /* 4375 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4378 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4393 + /* 4383 */ MCD_OPC_CheckPredicate, + 26, + 251, + 57, + 0, // Skip to: 19231 + /* 4388 */ MCD_OPC_Decode, + 234, + 18, + 200, + 1, // Opcode: VHSUBsv2i32 + /* 4393 */ MCD_OPC_FilterValue, + 1, + 241, + 57, + 0, // Skip to: 19231 + /* 4398 */ MCD_OPC_CheckPredicate, + 26, + 236, + 57, + 0, // Skip to: 19231 + /* 4403 */ MCD_OPC_Decode, + 236, + 18, + 201, + 1, // Opcode: VHSUBsv4i32 + /* 4408 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4447 + /* 4414 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4417 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4432 + /* 4422 */ MCD_OPC_CheckPredicate, + 26, + 212, + 57, + 0, // Skip to: 19231 + /* 4427 */ MCD_OPC_Decode, + 219, + 29, + 202, + 1, // Opcode: VSUBLsv2i64 + /* 4432 */ MCD_OPC_FilterValue, + 1, + 202, + 57, + 0, // Skip to: 19231 + /* 4437 */ MCD_OPC_CheckPredicate, + 26, + 197, + 57, + 0, // Skip to: 19231 + /* 4442 */ MCD_OPC_Decode, + 159, + 22, + 218, + 1, // Opcode: VMLALslsv2i32 + /* 4447 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4486 + /* 4453 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4456 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4471 + /* 4461 */ MCD_OPC_CheckPredicate, + 26, + 173, + 57, + 0, // Skip to: 19231 + /* 4466 */ MCD_OPC_Decode, + 240, + 18, + 200, + 1, // Opcode: VHSUBuv2i32 + /* 4471 */ MCD_OPC_FilterValue, + 1, + 163, + 57, + 0, // Skip to: 19231 + /* 4476 */ MCD_OPC_CheckPredicate, + 26, + 158, + 57, + 0, // Skip to: 19231 + /* 4481 */ MCD_OPC_Decode, + 242, + 18, + 201, + 1, // Opcode: VHSUBuv4i32 + /* 4486 */ MCD_OPC_FilterValue, + 231, + 3, + 147, + 57, + 0, // Skip to: 19231 + /* 4492 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4495 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4510 + /* 4500 */ MCD_OPC_CheckPredicate, + 26, + 134, + 57, + 0, // Skip to: 19231 + /* 4505 */ MCD_OPC_Decode, + 222, + 29, + 202, + 1, // Opcode: VSUBLuv2i64 + /* 4510 */ MCD_OPC_FilterValue, + 1, + 124, + 57, + 0, // Skip to: 19231 + /* 4515 */ MCD_OPC_CheckPredicate, + 26, + 119, + 57, + 0, // Skip to: 19231 + /* 4520 */ MCD_OPC_Decode, + 161, + 22, + 218, + 1, // Opcode: VMLALsluv2i32 + /* 4525 */ MCD_OPC_FilterValue, + 3, + 143, + 0, + 0, // Skip to: 4673 + /* 4530 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4533 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4572 + /* 4539 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4542 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4557 + /* 4547 */ MCD_OPC_CheckPredicate, + 26, + 87, + 57, + 0, // Skip to: 19231 + /* 4552 */ MCD_OPC_Decode, + 239, + 16, + 200, + 1, // Opcode: VCGTsv2i32 + /* 4557 */ MCD_OPC_FilterValue, + 1, + 77, + 57, + 0, // Skip to: 19231 + /* 4562 */ MCD_OPC_CheckPredicate, + 26, + 72, + 57, + 0, // Skip to: 19231 + /* 4567 */ MCD_OPC_Decode, + 241, + 16, + 201, + 1, // Opcode: VCGTsv4i32 + /* 4572 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4611 + /* 4578 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4581 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4596 + /* 4586 */ MCD_OPC_CheckPredicate, + 26, + 48, + 57, + 0, // Skip to: 19231 + /* 4591 */ MCD_OPC_Decode, + 226, + 29, + 203, + 1, // Opcode: VSUBWsv2i64 + /* 4596 */ MCD_OPC_FilterValue, + 1, + 38, + 57, + 0, // Skip to: 19231 + /* 4601 */ MCD_OPC_CheckPredicate, + 26, + 33, + 57, + 0, // Skip to: 19231 + /* 4606 */ MCD_OPC_Decode, + 155, + 24, + 218, + 1, // Opcode: VQDMLALslv2i32 + /* 4611 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4650 + /* 4617 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4620 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4635 + /* 4625 */ MCD_OPC_CheckPredicate, + 26, + 9, + 57, + 0, // Skip to: 19231 + /* 4630 */ MCD_OPC_Decode, + 245, + 16, + 200, + 1, // Opcode: VCGTuv2i32 + /* 4635 */ MCD_OPC_FilterValue, + 1, + 255, + 56, + 0, // Skip to: 19231 + /* 4640 */ MCD_OPC_CheckPredicate, + 26, + 250, + 56, + 0, // Skip to: 19231 + /* 4645 */ MCD_OPC_Decode, + 247, + 16, + 201, + 1, // Opcode: VCGTuv4i32 + /* 4650 */ MCD_OPC_FilterValue, + 231, + 3, + 239, + 56, + 0, // Skip to: 19231 + /* 4656 */ MCD_OPC_CheckPredicate, + 26, + 234, + 56, + 0, // Skip to: 19231 + /* 4661 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 227, + 56, + 0, // Skip to: 19231 + /* 4668 */ MCD_OPC_Decode, + 229, + 29, + 203, + 1, // Opcode: VSUBWuv2i64 + /* 4673 */ MCD_OPC_FilterValue, + 4, + 159, + 0, + 0, // Skip to: 4837 + /* 4678 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4681 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4720 + /* 4687 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4690 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4705 + /* 4695 */ MCD_OPC_CheckPredicate, + 26, + 195, + 56, + 0, // Skip to: 19231 + /* 4700 */ MCD_OPC_Decode, + 234, + 26, + 204, + 1, // Opcode: VSHLsv2i32 + /* 4705 */ MCD_OPC_FilterValue, + 1, + 185, + 56, + 0, // Skip to: 19231 + /* 4710 */ MCD_OPC_CheckPredicate, + 26, + 180, + 56, + 0, // Skip to: 19231 + /* 4715 */ MCD_OPC_Decode, + 237, + 26, + 205, + 1, // Opcode: VSHLsv4i32 + /* 4720 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4759 + /* 4726 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4729 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4744 + /* 4734 */ MCD_OPC_CheckPredicate, + 26, + 156, + 56, + 0, // Skip to: 19231 + /* 4739 */ MCD_OPC_Decode, + 136, + 16, + 206, + 1, // Opcode: VADDHNv2i32 + /* 4744 */ MCD_OPC_FilterValue, + 1, + 146, + 56, + 0, // Skip to: 19231 + /* 4749 */ MCD_OPC_CheckPredicate, + 26, + 141, + 56, + 0, // Skip to: 19231 + /* 4754 */ MCD_OPC_Decode, + 209, + 22, + 216, + 1, // Opcode: VMLSslv2i32 + /* 4759 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4798 + /* 4765 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4768 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4783 + /* 4773 */ MCD_OPC_CheckPredicate, + 26, + 117, + 56, + 0, // Skip to: 19231 + /* 4778 */ MCD_OPC_Decode, + 242, + 26, + 204, + 1, // Opcode: VSHLuv2i32 + /* 4783 */ MCD_OPC_FilterValue, + 1, + 107, + 56, + 0, // Skip to: 19231 + /* 4788 */ MCD_OPC_CheckPredicate, + 26, + 102, + 56, + 0, // Skip to: 19231 + /* 4793 */ MCD_OPC_Decode, + 245, + 26, + 205, + 1, // Opcode: VSHLuv4i32 + /* 4798 */ MCD_OPC_FilterValue, + 231, + 3, + 91, + 56, + 0, // Skip to: 19231 + /* 4804 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4807 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4822 + /* 4812 */ MCD_OPC_CheckPredicate, + 26, + 78, + 56, + 0, // Skip to: 19231 + /* 4817 */ MCD_OPC_Decode, + 176, + 25, + 206, + 1, // Opcode: VRADDHNv2i32 + /* 4822 */ MCD_OPC_FilterValue, + 1, + 68, + 56, + 0, // Skip to: 19231 + /* 4827 */ MCD_OPC_CheckPredicate, + 26, + 63, + 56, + 0, // Skip to: 19231 + /* 4832 */ MCD_OPC_Decode, + 211, + 22, + 217, + 1, // Opcode: VMLSslv4i32 + /* 4837 */ MCD_OPC_FilterValue, + 5, + 159, + 0, + 0, // Skip to: 5001 + /* 4842 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4845 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 4884 + /* 4851 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4854 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4869 + /* 4859 */ MCD_OPC_CheckPredicate, + 26, + 31, + 56, + 0, // Skip to: 19231 + /* 4864 */ MCD_OPC_Decode, + 132, + 26, + 204, + 1, // Opcode: VRSHLsv2i32 + /* 4869 */ MCD_OPC_FilterValue, + 1, + 21, + 56, + 0, // Skip to: 19231 + /* 4874 */ MCD_OPC_CheckPredicate, + 26, + 16, + 56, + 0, // Skip to: 19231 + /* 4879 */ MCD_OPC_Decode, + 135, + 26, + 205, + 1, // Opcode: VRSHLsv4i32 + /* 4884 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 4923 + /* 4890 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4893 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4908 + /* 4898 */ MCD_OPC_CheckPredicate, + 26, + 248, + 55, + 0, // Skip to: 19231 + /* 4903 */ MCD_OPC_Decode, + 201, + 15, + 207, + 1, // Opcode: VABALsv2i64 + /* 4908 */ MCD_OPC_FilterValue, + 1, + 238, + 55, + 0, // Skip to: 19231 + /* 4913 */ MCD_OPC_CheckPredicate, + 26, + 233, + 55, + 0, // Skip to: 19231 + /* 4918 */ MCD_OPC_Decode, + 205, + 22, + 216, + 1, // Opcode: VMLSslfd + /* 4923 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 4962 + /* 4929 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4932 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4947 + /* 4937 */ MCD_OPC_CheckPredicate, + 26, + 209, + 55, + 0, // Skip to: 19231 + /* 4942 */ MCD_OPC_Decode, + 140, + 26, + 204, + 1, // Opcode: VRSHLuv2i32 + /* 4947 */ MCD_OPC_FilterValue, + 1, + 199, + 55, + 0, // Skip to: 19231 + /* 4952 */ MCD_OPC_CheckPredicate, + 26, + 194, + 55, + 0, // Skip to: 19231 + /* 4957 */ MCD_OPC_Decode, + 143, + 26, + 205, + 1, // Opcode: VRSHLuv4i32 + /* 4962 */ MCD_OPC_FilterValue, + 231, + 3, + 183, + 55, + 0, // Skip to: 19231 + /* 4968 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4971 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4986 + /* 4976 */ MCD_OPC_CheckPredicate, + 26, + 170, + 55, + 0, // Skip to: 19231 + /* 4981 */ MCD_OPC_Decode, + 204, + 15, + 207, + 1, // Opcode: VABALuv2i64 + /* 4986 */ MCD_OPC_FilterValue, + 1, + 160, + 55, + 0, // Skip to: 19231 + /* 4991 */ MCD_OPC_CheckPredicate, + 26, + 155, + 55, + 0, // Skip to: 19231 + /* 4996 */ MCD_OPC_Decode, + 206, + 22, + 217, + 1, // Opcode: VMLSslfq + /* 5001 */ MCD_OPC_FilterValue, + 6, + 159, + 0, + 0, // Skip to: 5165 + /* 5006 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5009 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5048 + /* 5015 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5018 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5033 + /* 5023 */ MCD_OPC_CheckPredicate, + 26, + 123, + 55, + 0, // Skip to: 19231 + /* 5028 */ MCD_OPC_Decode, + 130, + 22, + 200, + 1, // Opcode: VMAXsv2i32 + /* 5033 */ MCD_OPC_FilterValue, + 1, + 113, + 55, + 0, // Skip to: 19231 + /* 5038 */ MCD_OPC_CheckPredicate, + 26, + 108, + 55, + 0, // Skip to: 19231 + /* 5043 */ MCD_OPC_Decode, + 132, + 22, + 201, + 1, // Opcode: VMAXsv4i32 + /* 5048 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5087 + /* 5054 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5057 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5072 + /* 5062 */ MCD_OPC_CheckPredicate, + 26, + 84, + 55, + 0, // Skip to: 19231 + /* 5067 */ MCD_OPC_Decode, + 216, + 29, + 206, + 1, // Opcode: VSUBHNv2i32 + /* 5072 */ MCD_OPC_FilterValue, + 1, + 74, + 55, + 0, // Skip to: 19231 + /* 5077 */ MCD_OPC_CheckPredicate, + 26, + 69, + 55, + 0, // Skip to: 19231 + /* 5082 */ MCD_OPC_Decode, + 190, + 22, + 218, + 1, // Opcode: VMLSLslsv2i32 + /* 5087 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 5126 + /* 5093 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5096 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5111 + /* 5101 */ MCD_OPC_CheckPredicate, + 26, + 45, + 55, + 0, // Skip to: 19231 + /* 5106 */ MCD_OPC_Decode, + 136, + 22, + 200, + 1, // Opcode: VMAXuv2i32 + /* 5111 */ MCD_OPC_FilterValue, + 1, + 35, + 55, + 0, // Skip to: 19231 + /* 5116 */ MCD_OPC_CheckPredicate, + 26, + 30, + 55, + 0, // Skip to: 19231 + /* 5121 */ MCD_OPC_Decode, + 138, + 22, + 201, + 1, // Opcode: VMAXuv4i32 + /* 5126 */ MCD_OPC_FilterValue, + 231, + 3, + 19, + 55, + 0, // Skip to: 19231 + /* 5132 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5135 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5150 + /* 5140 */ MCD_OPC_CheckPredicate, + 26, + 6, + 55, + 0, // Skip to: 19231 + /* 5145 */ MCD_OPC_Decode, + 191, + 26, + 206, + 1, // Opcode: VRSUBHNv2i32 + /* 5150 */ MCD_OPC_FilterValue, + 1, + 252, + 54, + 0, // Skip to: 19231 + /* 5155 */ MCD_OPC_CheckPredicate, + 26, + 247, + 54, + 0, // Skip to: 19231 + /* 5160 */ MCD_OPC_Decode, + 192, + 22, + 218, + 1, // Opcode: VMLSLsluv2i32 + /* 5165 */ MCD_OPC_FilterValue, + 7, + 143, + 0, + 0, // Skip to: 5313 + /* 5170 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5173 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5212 + /* 5179 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5182 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5197 + /* 5187 */ MCD_OPC_CheckPredicate, + 26, + 215, + 54, + 0, // Skip to: 19231 + /* 5192 */ MCD_OPC_Decode, + 230, + 15, + 200, + 1, // Opcode: VABDsv2i32 + /* 5197 */ MCD_OPC_FilterValue, + 1, + 205, + 54, + 0, // Skip to: 19231 + /* 5202 */ MCD_OPC_CheckPredicate, + 26, + 200, + 54, + 0, // Skip to: 19231 + /* 5207 */ MCD_OPC_Decode, + 232, + 15, + 201, + 1, // Opcode: VABDsv4i32 + /* 5212 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5251 + /* 5218 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5221 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5236 + /* 5226 */ MCD_OPC_CheckPredicate, + 26, + 176, + 54, + 0, // Skip to: 19231 + /* 5231 */ MCD_OPC_Decode, + 219, + 15, + 202, + 1, // Opcode: VABDLsv2i64 + /* 5236 */ MCD_OPC_FilterValue, + 1, + 166, + 54, + 0, // Skip to: 19231 + /* 5241 */ MCD_OPC_CheckPredicate, + 26, + 161, + 54, + 0, // Skip to: 19231 + /* 5246 */ MCD_OPC_Decode, + 159, + 24, + 218, + 1, // Opcode: VQDMLSLslv2i32 + /* 5251 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 5290 + /* 5257 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5260 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5275 + /* 5265 */ MCD_OPC_CheckPredicate, + 26, + 137, + 54, + 0, // Skip to: 19231 + /* 5270 */ MCD_OPC_Decode, + 236, + 15, + 200, + 1, // Opcode: VABDuv2i32 + /* 5275 */ MCD_OPC_FilterValue, + 1, + 127, + 54, + 0, // Skip to: 19231 + /* 5280 */ MCD_OPC_CheckPredicate, + 26, + 122, + 54, + 0, // Skip to: 19231 + /* 5285 */ MCD_OPC_Decode, + 238, + 15, + 201, + 1, // Opcode: VABDuv4i32 + /* 5290 */ MCD_OPC_FilterValue, + 231, + 3, + 111, + 54, + 0, // Skip to: 19231 + /* 5296 */ MCD_OPC_CheckPredicate, + 26, + 106, + 54, + 0, // Skip to: 19231 + /* 5301 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 99, + 54, + 0, // Skip to: 19231 + /* 5308 */ MCD_OPC_Decode, + 222, + 15, + 202, + 1, // Opcode: VABDLuv2i64 + /* 5313 */ MCD_OPC_FilterValue, + 8, + 159, + 0, + 0, // Skip to: 5477 + /* 5318 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5321 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5360 + /* 5327 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5330 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5345 + /* 5335 */ MCD_OPC_CheckPredicate, + 26, + 67, + 54, + 0, // Skip to: 19231 + /* 5340 */ MCD_OPC_Decode, + 158, + 16, + 200, + 1, // Opcode: VADDv2i32 + /* 5345 */ MCD_OPC_FilterValue, + 1, + 57, + 54, + 0, // Skip to: 19231 + /* 5350 */ MCD_OPC_CheckPredicate, + 26, + 52, + 54, + 0, // Skip to: 19231 + /* 5355 */ MCD_OPC_Decode, + 161, + 16, + 201, + 1, // Opcode: VADDv4i32 + /* 5360 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5399 + /* 5366 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5369 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5384 + /* 5374 */ MCD_OPC_CheckPredicate, + 26, + 28, + 54, + 0, // Skip to: 19231 + /* 5379 */ MCD_OPC_Decode, + 163, + 22, + 207, + 1, // Opcode: VMLALsv2i64 + /* 5384 */ MCD_OPC_FilterValue, + 1, + 18, + 54, + 0, // Skip to: 19231 + /* 5389 */ MCD_OPC_CheckPredicate, + 26, + 13, + 54, + 0, // Skip to: 19231 + /* 5394 */ MCD_OPC_Decode, + 170, + 23, + 219, + 1, // Opcode: VMULslv2i32 + /* 5399 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 5438 + /* 5405 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5408 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5423 + /* 5413 */ MCD_OPC_CheckPredicate, + 26, + 245, + 53, + 0, // Skip to: 19231 + /* 5418 */ MCD_OPC_Decode, + 238, + 29, + 200, + 1, // Opcode: VSUBv2i32 + /* 5423 */ MCD_OPC_FilterValue, + 1, + 235, + 53, + 0, // Skip to: 19231 + /* 5428 */ MCD_OPC_CheckPredicate, + 26, + 230, + 53, + 0, // Skip to: 19231 + /* 5433 */ MCD_OPC_Decode, + 241, + 29, + 201, + 1, // Opcode: VSUBv4i32 + /* 5438 */ MCD_OPC_FilterValue, + 231, + 3, + 219, + 53, + 0, // Skip to: 19231 + /* 5444 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5447 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5462 + /* 5452 */ MCD_OPC_CheckPredicate, + 26, + 206, + 53, + 0, // Skip to: 19231 + /* 5457 */ MCD_OPC_Decode, + 166, + 22, + 207, + 1, // Opcode: VMLALuv2i64 + /* 5462 */ MCD_OPC_FilterValue, + 1, + 196, + 53, + 0, // Skip to: 19231 + /* 5467 */ MCD_OPC_CheckPredicate, + 26, + 191, + 53, + 0, // Skip to: 19231 + /* 5472 */ MCD_OPC_Decode, + 172, + 23, + 220, + 1, // Opcode: VMULslv4i32 + /* 5477 */ MCD_OPC_FilterValue, + 9, + 143, + 0, + 0, // Skip to: 5625 + /* 5482 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5485 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5524 + /* 5491 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5494 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5509 + /* 5499 */ MCD_OPC_CheckPredicate, + 26, + 159, + 53, + 0, // Skip to: 19231 + /* 5504 */ MCD_OPC_Decode, + 183, + 22, + 208, + 1, // Opcode: VMLAv2i32 + /* 5509 */ MCD_OPC_FilterValue, + 1, + 149, + 53, + 0, // Skip to: 19231 + /* 5514 */ MCD_OPC_CheckPredicate, + 26, + 144, + 53, + 0, // Skip to: 19231 + /* 5519 */ MCD_OPC_Decode, + 185, + 22, + 209, + 1, // Opcode: VMLAv4i32 + /* 5524 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5563 + /* 5530 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5533 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5548 + /* 5538 */ MCD_OPC_CheckPredicate, + 26, + 120, + 53, + 0, // Skip to: 19231 + /* 5543 */ MCD_OPC_Decode, + 157, + 24, + 207, + 1, // Opcode: VQDMLALv2i64 + /* 5548 */ MCD_OPC_FilterValue, + 1, + 110, + 53, + 0, // Skip to: 19231 + /* 5553 */ MCD_OPC_CheckPredicate, + 26, + 105, + 53, + 0, // Skip to: 19231 + /* 5558 */ MCD_OPC_Decode, + 166, + 23, + 219, + 1, // Opcode: VMULslfd + /* 5563 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 5602 + /* 5569 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5572 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5587 + /* 5577 */ MCD_OPC_CheckPredicate, + 26, + 81, + 53, + 0, // Skip to: 19231 + /* 5582 */ MCD_OPC_Decode, + 214, + 22, + 208, + 1, // Opcode: VMLSv2i32 + /* 5587 */ MCD_OPC_FilterValue, + 1, + 71, + 53, + 0, // Skip to: 19231 + /* 5592 */ MCD_OPC_CheckPredicate, + 26, + 66, + 53, + 0, // Skip to: 19231 + /* 5597 */ MCD_OPC_Decode, + 216, + 22, + 209, + 1, // Opcode: VMLSv4i32 + /* 5602 */ MCD_OPC_FilterValue, + 231, + 3, + 55, + 53, + 0, // Skip to: 19231 + /* 5608 */ MCD_OPC_CheckPredicate, + 26, + 50, + 53, + 0, // Skip to: 19231 + /* 5613 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 43, + 53, + 0, // Skip to: 19231 + /* 5620 */ MCD_OPC_Decode, + 167, + 23, + 220, + 1, // Opcode: VMULslfq + /* 5625 */ MCD_OPC_FilterValue, + 10, + 127, + 0, + 0, // Skip to: 5757 + /* 5630 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5633 */ MCD_OPC_FilterValue, + 228, + 3, + 17, + 0, + 0, // Skip to: 5656 + /* 5639 */ MCD_OPC_CheckPredicate, + 26, + 19, + 53, + 0, // Skip to: 19231 + /* 5644 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 12, + 53, + 0, // Skip to: 19231 + /* 5651 */ MCD_OPC_Decode, + 248, + 23, + 200, + 1, // Opcode: VPMAXs32 + /* 5656 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5695 + /* 5662 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5665 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5680 + /* 5670 */ MCD_OPC_CheckPredicate, + 26, + 244, + 52, + 0, // Skip to: 19231 + /* 5675 */ MCD_OPC_Decode, + 194, + 22, + 207, + 1, // Opcode: VMLSLsv2i64 + /* 5680 */ MCD_OPC_FilterValue, + 1, + 234, + 52, + 0, // Skip to: 19231 + /* 5685 */ MCD_OPC_CheckPredicate, + 26, + 229, + 52, + 0, // Skip to: 19231 + /* 5690 */ MCD_OPC_Decode, + 149, + 23, + 221, + 1, // Opcode: VMULLslsv2i32 + /* 5695 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 5718 + /* 5701 */ MCD_OPC_CheckPredicate, + 26, + 213, + 52, + 0, // Skip to: 19231 + /* 5706 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 206, + 52, + 0, // Skip to: 19231 + /* 5713 */ MCD_OPC_Decode, + 251, + 23, + 200, + 1, // Opcode: VPMAXu32 + /* 5718 */ MCD_OPC_FilterValue, + 231, + 3, + 195, + 52, + 0, // Skip to: 19231 + /* 5724 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5727 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5742 + /* 5732 */ MCD_OPC_CheckPredicate, + 26, + 182, + 52, + 0, // Skip to: 19231 + /* 5737 */ MCD_OPC_Decode, + 197, + 22, + 207, + 1, // Opcode: VMLSLuv2i64 + /* 5742 */ MCD_OPC_FilterValue, + 1, + 172, + 52, + 0, // Skip to: 19231 + /* 5747 */ MCD_OPC_CheckPredicate, + 26, + 167, + 52, + 0, // Skip to: 19231 + /* 5752 */ MCD_OPC_Decode, + 151, + 23, + 221, + 1, // Opcode: VMULLsluv2i32 + /* 5757 */ MCD_OPC_FilterValue, + 11, + 120, + 0, + 0, // Skip to: 5882 + /* 5762 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5765 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 5804 + /* 5771 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5774 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5789 + /* 5779 */ MCD_OPC_CheckPredicate, + 26, + 135, + 52, + 0, // Skip to: 19231 + /* 5784 */ MCD_OPC_Decode, + 167, + 24, + 200, + 1, // Opcode: VQDMULHv2i32 + /* 5789 */ MCD_OPC_FilterValue, + 1, + 125, + 52, + 0, // Skip to: 19231 + /* 5794 */ MCD_OPC_CheckPredicate, + 26, + 120, + 52, + 0, // Skip to: 19231 + /* 5799 */ MCD_OPC_Decode, + 169, + 24, + 201, + 1, // Opcode: VQDMULHv4i32 + /* 5804 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 5843 + /* 5810 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5813 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5828 + /* 5818 */ MCD_OPC_CheckPredicate, + 26, + 96, + 52, + 0, // Skip to: 19231 + /* 5823 */ MCD_OPC_Decode, + 161, + 24, + 207, + 1, // Opcode: VQDMLSLv2i64 + /* 5828 */ MCD_OPC_FilterValue, + 1, + 86, + 52, + 0, // Skip to: 19231 + /* 5833 */ MCD_OPC_CheckPredicate, + 26, + 81, + 52, + 0, // Skip to: 19231 + /* 5838 */ MCD_OPC_Decode, + 171, + 24, + 221, + 1, // Opcode: VQDMULLslv2i32 + /* 5843 */ MCD_OPC_FilterValue, + 230, + 3, + 70, + 52, + 0, // Skip to: 19231 + /* 5849 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5852 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5867 + /* 5857 */ MCD_OPC_CheckPredicate, + 26, + 57, + 52, + 0, // Skip to: 19231 + /* 5862 */ MCD_OPC_Decode, + 210, + 24, + 200, + 1, // Opcode: VQRDMULHv2i32 + /* 5867 */ MCD_OPC_FilterValue, + 1, + 47, + 52, + 0, // Skip to: 19231 + /* 5872 */ MCD_OPC_CheckPredicate, + 26, + 42, + 52, + 0, // Skip to: 19231 + /* 5877 */ MCD_OPC_Decode, + 212, + 24, + 201, + 1, // Opcode: VQRDMULHv4i32 + /* 5882 */ MCD_OPC_FilterValue, + 12, + 83, + 0, + 0, // Skip to: 5970 + /* 5887 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5890 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 5930 + /* 5895 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5898 */ MCD_OPC_FilterValue, + 229, + 3, + 10, + 0, + 0, // Skip to: 5914 + /* 5904 */ MCD_OPC_CheckPredicate, + 26, + 10, + 52, + 0, // Skip to: 19231 + /* 5909 */ MCD_OPC_Decode, + 153, + 23, + 202, + 1, // Opcode: VMULLsv2i64 + /* 5914 */ MCD_OPC_FilterValue, + 231, + 3, + 255, + 51, + 0, // Skip to: 19231 + /* 5920 */ MCD_OPC_CheckPredicate, + 26, + 250, + 51, + 0, // Skip to: 19231 + /* 5925 */ MCD_OPC_Decode, + 156, + 23, + 202, + 1, // Opcode: VMULLuv2i64 + /* 5930 */ MCD_OPC_FilterValue, + 1, + 240, + 51, + 0, // Skip to: 19231 + /* 5935 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5938 */ MCD_OPC_FilterValue, + 229, + 3, + 10, + 0, + 0, // Skip to: 5954 + /* 5944 */ MCD_OPC_CheckPredicate, + 26, + 226, + 51, + 0, // Skip to: 19231 + /* 5949 */ MCD_OPC_Decode, + 163, + 24, + 219, + 1, // Opcode: VQDMULHslv2i32 + /* 5954 */ MCD_OPC_FilterValue, + 231, + 3, + 215, + 51, + 0, // Skip to: 19231 + /* 5960 */ MCD_OPC_CheckPredicate, + 26, + 210, + 51, + 0, // Skip to: 19231 + /* 5965 */ MCD_OPC_Decode, + 165, + 24, + 220, + 1, // Opcode: VQDMULHslv4i32 + /* 5970 */ MCD_OPC_FilterValue, + 13, + 143, + 0, + 0, // Skip to: 6118 + /* 5975 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5978 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 6017 + /* 5984 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5987 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6002 + /* 5992 */ MCD_OPC_CheckPredicate, + 26, + 178, + 51, + 0, // Skip to: 19231 + /* 5997 */ MCD_OPC_Decode, + 232, + 29, + 200, + 1, // Opcode: VSUBfd + /* 6002 */ MCD_OPC_FilterValue, + 1, + 168, + 51, + 0, // Skip to: 19231 + /* 6007 */ MCD_OPC_CheckPredicate, + 26, + 163, + 51, + 0, // Skip to: 19231 + /* 6012 */ MCD_OPC_Decode, + 233, + 29, + 201, + 1, // Opcode: VSUBfq + /* 6017 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 6056 + /* 6023 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6026 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6041 + /* 6031 */ MCD_OPC_CheckPredicate, + 26, + 139, + 51, + 0, // Skip to: 19231 + /* 6036 */ MCD_OPC_Decode, + 173, + 24, + 202, + 1, // Opcode: VQDMULLv2i64 + /* 6041 */ MCD_OPC_FilterValue, + 1, + 129, + 51, + 0, // Skip to: 19231 + /* 6046 */ MCD_OPC_CheckPredicate, + 26, + 124, + 51, + 0, // Skip to: 19231 + /* 6051 */ MCD_OPC_Decode, + 206, + 24, + 219, + 1, // Opcode: VQRDMULHslv2i32 + /* 6056 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 6095 + /* 6062 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6065 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6080 + /* 6070 */ MCD_OPC_CheckPredicate, + 26, + 100, + 51, + 0, // Skip to: 19231 + /* 6075 */ MCD_OPC_Decode, + 225, + 15, + 200, + 1, // Opcode: VABDfd + /* 6080 */ MCD_OPC_FilterValue, + 1, + 90, + 51, + 0, // Skip to: 19231 + /* 6085 */ MCD_OPC_CheckPredicate, + 26, + 85, + 51, + 0, // Skip to: 19231 + /* 6090 */ MCD_OPC_Decode, + 226, + 15, + 201, + 1, // Opcode: VABDfq + /* 6095 */ MCD_OPC_FilterValue, + 231, + 3, + 74, + 51, + 0, // Skip to: 19231 + /* 6101 */ MCD_OPC_CheckPredicate, + 26, + 69, + 51, + 0, // Skip to: 19231 + /* 6106 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 62, + 51, + 0, // Skip to: 19231 + /* 6113 */ MCD_OPC_Decode, + 208, + 24, + 220, + 1, // Opcode: VQRDMULHslv4i32 + /* 6118 */ MCD_OPC_FilterValue, + 14, + 104, + 0, + 0, // Skip to: 6227 + /* 6123 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6126 */ MCD_OPC_FilterValue, + 229, + 3, + 33, + 0, + 0, // Skip to: 6165 + /* 6132 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6135 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6150 + /* 6140 */ MCD_OPC_CheckPredicate, + 29, + 30, + 51, + 0, // Skip to: 19231 + /* 6145 */ MCD_OPC_Decode, + 147, + 23, + 202, + 1, // Opcode: VMULLp64 + /* 6150 */ MCD_OPC_FilterValue, + 1, + 20, + 51, + 0, // Skip to: 19231 + /* 6155 */ MCD_OPC_CheckPredicate, + 28, + 15, + 51, + 0, // Skip to: 19231 + /* 6160 */ MCD_OPC_Decode, + 190, + 24, + 216, + 1, // Opcode: VQRDMLAHslv2i32 + /* 6165 */ MCD_OPC_FilterValue, + 230, + 3, + 33, + 0, + 0, // Skip to: 6204 + /* 6171 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6174 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6189 + /* 6179 */ MCD_OPC_CheckPredicate, + 26, + 247, + 50, + 0, // Skip to: 19231 + /* 6184 */ MCD_OPC_Decode, + 234, + 16, + 200, + 1, // Opcode: VCGTfd + /* 6189 */ MCD_OPC_FilterValue, + 1, + 237, + 50, + 0, // Skip to: 19231 + /* 6194 */ MCD_OPC_CheckPredicate, + 26, + 232, + 50, + 0, // Skip to: 19231 + /* 6199 */ MCD_OPC_Decode, + 235, + 16, + 201, + 1, // Opcode: VCGTfq + /* 6204 */ MCD_OPC_FilterValue, + 231, + 3, + 221, + 50, + 0, // Skip to: 19231 + /* 6210 */ MCD_OPC_CheckPredicate, + 28, + 216, + 50, + 0, // Skip to: 19231 + /* 6215 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 209, + 50, + 0, // Skip to: 19231 + /* 6222 */ MCD_OPC_Decode, + 192, + 24, + 217, + 1, // Opcode: VQRDMLAHslv4i32 + /* 6227 */ MCD_OPC_FilterValue, + 15, + 199, + 50, + 0, // Skip to: 19231 + /* 6232 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6235 */ MCD_OPC_FilterValue, + 228, + 3, + 33, + 0, + 0, // Skip to: 6274 + /* 6241 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6244 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6259 + /* 6249 */ MCD_OPC_CheckPredicate, + 26, + 177, + 50, + 0, // Skip to: 19231 + /* 6254 */ MCD_OPC_Decode, + 141, + 22, + 200, + 1, // Opcode: VMINfd + /* 6259 */ MCD_OPC_FilterValue, + 1, + 167, + 50, + 0, // Skip to: 19231 + /* 6264 */ MCD_OPC_CheckPredicate, + 26, + 162, + 50, + 0, // Skip to: 19231 + /* 6269 */ MCD_OPC_Decode, + 142, + 22, + 201, + 1, // Opcode: VMINfq + /* 6274 */ MCD_OPC_FilterValue, + 229, + 3, + 17, + 0, + 0, // Skip to: 6297 + /* 6280 */ MCD_OPC_CheckPredicate, + 28, + 146, + 50, + 0, // Skip to: 19231 + /* 6285 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 139, + 50, + 0, // Skip to: 19231 + /* 6292 */ MCD_OPC_Decode, + 198, + 24, + 216, + 1, // Opcode: VQRDMLSHslv2i32 + /* 6297 */ MCD_OPC_FilterValue, + 230, + 3, + 17, + 0, + 0, // Skip to: 6320 + /* 6303 */ MCD_OPC_CheckPredicate, + 26, + 123, + 50, + 0, // Skip to: 19231 + /* 6308 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 116, + 50, + 0, // Skip to: 19231 + /* 6315 */ MCD_OPC_Decode, + 253, + 23, + 200, + 1, // Opcode: VPMINf + /* 6320 */ MCD_OPC_FilterValue, + 231, + 3, + 105, + 50, + 0, // Skip to: 19231 + /* 6326 */ MCD_OPC_CheckPredicate, + 28, + 100, + 50, + 0, // Skip to: 19231 + /* 6331 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 93, + 50, + 0, // Skip to: 19231 + /* 6338 */ MCD_OPC_Decode, + 200, + 24, + 217, + 1, // Opcode: VQRDMLSHslv4i32 + /* 6343 */ MCD_OPC_FilterValue, + 3, + 83, + 50, + 0, // Skip to: 19231 + /* 6348 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6351 */ MCD_OPC_FilterValue, + 228, + 3, + 193, + 0, + 0, // Skip to: 6550 + /* 6357 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 6360 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 6398 + /* 6365 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6368 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6383 + /* 6373 */ MCD_OPC_CheckPredicate, + 26, + 53, + 50, + 0, // Skip to: 19231 + /* 6378 */ MCD_OPC_Decode, + 233, + 26, + 204, + 1, // Opcode: VSHLsv1i64 + /* 6383 */ MCD_OPC_FilterValue, + 1, + 43, + 50, + 0, // Skip to: 19231 + /* 6388 */ MCD_OPC_CheckPredicate, + 26, + 38, + 50, + 0, // Skip to: 19231 + /* 6393 */ MCD_OPC_Decode, + 235, + 26, + 205, + 1, // Opcode: VSHLsv2i64 + /* 6398 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 6436 + /* 6403 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6406 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6421 + /* 6411 */ MCD_OPC_CheckPredicate, + 26, + 15, + 50, + 0, // Skip to: 19231 + /* 6416 */ MCD_OPC_Decode, + 131, + 26, + 204, + 1, // Opcode: VRSHLsv1i64 + /* 6421 */ MCD_OPC_FilterValue, + 1, + 5, + 50, + 0, // Skip to: 19231 + /* 6426 */ MCD_OPC_CheckPredicate, + 26, + 0, + 50, + 0, // Skip to: 19231 + /* 6431 */ MCD_OPC_Decode, + 133, + 26, + 205, + 1, // Opcode: VRSHLsv2i64 + /* 6436 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 6474 + /* 6441 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6444 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6459 + /* 6449 */ MCD_OPC_CheckPredicate, + 26, + 233, + 49, + 0, // Skip to: 19231 + /* 6454 */ MCD_OPC_Decode, + 157, + 16, + 200, + 1, // Opcode: VADDv1i64 + /* 6459 */ MCD_OPC_FilterValue, + 1, + 223, + 49, + 0, // Skip to: 19231 + /* 6464 */ MCD_OPC_CheckPredicate, + 26, + 218, + 49, + 0, // Skip to: 19231 + /* 6469 */ MCD_OPC_Decode, + 159, + 16, + 201, + 1, // Opcode: VADDv2i64 + /* 6474 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 6512 + /* 6479 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6482 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6497 + /* 6487 */ MCD_OPC_CheckPredicate, + 27, + 195, + 49, + 0, // Skip to: 19231 + /* 6492 */ MCD_OPC_Decode, + 234, + 29, + 200, + 1, // Opcode: VSUBhd + /* 6497 */ MCD_OPC_FilterValue, + 1, + 185, + 49, + 0, // Skip to: 19231 + /* 6502 */ MCD_OPC_CheckPredicate, + 27, + 180, + 49, + 0, // Skip to: 19231 + /* 6507 */ MCD_OPC_Decode, + 235, + 29, + 201, + 1, // Opcode: VSUBhq + /* 6512 */ MCD_OPC_FilterValue, + 15, + 170, + 49, + 0, // Skip to: 19231 + /* 6517 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6520 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6535 + /* 6525 */ MCD_OPC_CheckPredicate, + 27, + 157, + 49, + 0, // Skip to: 19231 + /* 6530 */ MCD_OPC_Decode, + 143, + 22, + 200, + 1, // Opcode: VMINhd + /* 6535 */ MCD_OPC_FilterValue, + 1, + 147, + 49, + 0, // Skip to: 19231 + /* 6540 */ MCD_OPC_CheckPredicate, + 27, + 142, + 49, + 0, // Skip to: 19231 + /* 6545 */ MCD_OPC_Decode, + 144, + 22, + 201, + 1, // Opcode: VMINhq + /* 6550 */ MCD_OPC_FilterValue, + 229, + 3, + 126, + 0, + 0, // Skip to: 6682 + /* 6556 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6559 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 6616 + /* 6564 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 6567 */ MCD_OPC_FilterValue, + 0, + 115, + 49, + 0, // Skip to: 19231 + /* 6572 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6589 + /* 6577 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 5, + 0, + 0, // Skip to: 6589 + /* 6584 */ MCD_OPC_Decode, + 176, + 18, + 222, + 1, // Opcode: VEXTd32 + /* 6589 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6606 + /* 6594 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 5, + 0, + 0, // Skip to: 6606 + /* 6601 */ MCD_OPC_Decode, + 175, + 18, + 223, + 1, // Opcode: VEXTd16 + /* 6606 */ MCD_OPC_CheckPredicate, + 26, + 76, + 49, + 0, // Skip to: 19231 + /* 6611 */ MCD_OPC_Decode, + 177, + 18, + 224, + 1, // Opcode: VEXTd8 + /* 6616 */ MCD_OPC_FilterValue, + 1, + 66, + 49, + 0, // Skip to: 19231 + /* 6621 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6638 + /* 6626 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 5, + 0, + 0, // Skip to: 6638 + /* 6633 */ MCD_OPC_Decode, + 180, + 18, + 225, + 1, // Opcode: VEXTq64 + /* 6638 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6655 + /* 6643 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 5, + 0, + 0, // Skip to: 6655 + /* 6650 */ MCD_OPC_Decode, + 179, + 18, + 226, + 1, // Opcode: VEXTq32 + /* 6655 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6672 + /* 6660 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 5, + 0, + 0, // Skip to: 6672 + /* 6667 */ MCD_OPC_Decode, + 178, + 18, + 227, + 1, // Opcode: VEXTq16 + /* 6672 */ MCD_OPC_CheckPredicate, + 26, + 10, + 49, + 0, // Skip to: 19231 + /* 6677 */ MCD_OPC_Decode, + 181, + 18, + 228, + 1, // Opcode: VEXTq8 + /* 6682 */ MCD_OPC_FilterValue, + 230, + 3, + 215, + 0, + 0, // Skip to: 6903 + /* 6688 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 6691 */ MCD_OPC_FilterValue, + 4, + 33, + 0, + 0, // Skip to: 6729 + /* 6696 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6699 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6714 + /* 6704 */ MCD_OPC_CheckPredicate, + 26, + 234, + 48, + 0, // Skip to: 19231 + /* 6709 */ MCD_OPC_Decode, + 241, + 26, + 204, + 1, // Opcode: VSHLuv1i64 + /* 6714 */ MCD_OPC_FilterValue, + 1, + 224, + 48, + 0, // Skip to: 19231 + /* 6719 */ MCD_OPC_CheckPredicate, + 26, + 219, + 48, + 0, // Skip to: 19231 + /* 6724 */ MCD_OPC_Decode, + 243, + 26, + 205, + 1, // Opcode: VSHLuv2i64 + /* 6729 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 6767 + /* 6734 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6737 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6752 + /* 6742 */ MCD_OPC_CheckPredicate, + 26, + 196, + 48, + 0, // Skip to: 19231 + /* 6747 */ MCD_OPC_Decode, + 139, + 26, + 204, + 1, // Opcode: VRSHLuv1i64 + /* 6752 */ MCD_OPC_FilterValue, + 1, + 186, + 48, + 0, // Skip to: 19231 + /* 6757 */ MCD_OPC_CheckPredicate, + 26, + 181, + 48, + 0, // Skip to: 19231 + /* 6762 */ MCD_OPC_Decode, + 141, + 26, + 205, + 1, // Opcode: VRSHLuv2i64 + /* 6767 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 6805 + /* 6772 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6775 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6790 + /* 6780 */ MCD_OPC_CheckPredicate, + 26, + 158, + 48, + 0, // Skip to: 19231 + /* 6785 */ MCD_OPC_Decode, + 237, + 29, + 200, + 1, // Opcode: VSUBv1i64 + /* 6790 */ MCD_OPC_FilterValue, + 1, + 148, + 48, + 0, // Skip to: 19231 + /* 6795 */ MCD_OPC_CheckPredicate, + 26, + 143, + 48, + 0, // Skip to: 19231 + /* 6800 */ MCD_OPC_Decode, + 239, + 29, + 201, + 1, // Opcode: VSUBv2i64 + /* 6805 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 6843 + /* 6810 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6813 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6828 + /* 6818 */ MCD_OPC_CheckPredicate, + 27, + 120, + 48, + 0, // Skip to: 19231 + /* 6823 */ MCD_OPC_Decode, + 227, + 15, + 200, + 1, // Opcode: VABDhd + /* 6828 */ MCD_OPC_FilterValue, + 1, + 110, + 48, + 0, // Skip to: 19231 + /* 6833 */ MCD_OPC_CheckPredicate, + 27, + 105, + 48, + 0, // Skip to: 19231 + /* 6838 */ MCD_OPC_Decode, + 228, + 15, + 201, + 1, // Opcode: VABDhq + /* 6843 */ MCD_OPC_FilterValue, + 14, + 33, + 0, + 0, // Skip to: 6881 + /* 6848 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6851 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6866 + /* 6856 */ MCD_OPC_CheckPredicate, + 27, + 82, + 48, + 0, // Skip to: 19231 + /* 6861 */ MCD_OPC_Decode, + 236, + 16, + 200, + 1, // Opcode: VCGThd + /* 6866 */ MCD_OPC_FilterValue, + 1, + 72, + 48, + 0, // Skip to: 19231 + /* 6871 */ MCD_OPC_CheckPredicate, + 27, + 67, + 48, + 0, // Skip to: 19231 + /* 6876 */ MCD_OPC_Decode, + 237, + 16, + 201, + 1, // Opcode: VCGThq + /* 6881 */ MCD_OPC_FilterValue, + 15, + 57, + 48, + 0, // Skip to: 19231 + /* 6886 */ MCD_OPC_CheckPredicate, + 27, + 52, + 48, + 0, // Skip to: 19231 + /* 6891 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 45, + 48, + 0, // Skip to: 19231 + /* 6898 */ MCD_OPC_Decode, + 254, + 23, + 200, + 1, // Opcode: VPMINh + /* 6903 */ MCD_OPC_FilterValue, + 231, + 3, + 34, + 48, + 0, // Skip to: 19231 + /* 6909 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 6912 */ MCD_OPC_FilterValue, + 0, + 13, + 2, + 0, // Skip to: 7442 + /* 6917 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 6920 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 6988 + /* 6925 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 6928 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6943 + /* 6933 */ MCD_OPC_CheckPredicate, + 26, + 5, + 48, + 0, // Skip to: 19231 + /* 6938 */ MCD_OPC_Decode, + 197, + 25, + 229, + 1, // Opcode: VREV64d8 + /* 6943 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6958 + /* 6948 */ MCD_OPC_CheckPredicate, + 26, + 246, + 47, + 0, // Skip to: 19231 + /* 6953 */ MCD_OPC_Decode, + 200, + 25, + 230, + 1, // Opcode: VREV64q8 + /* 6958 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6973 + /* 6963 */ MCD_OPC_CheckPredicate, + 26, + 231, + 47, + 0, // Skip to: 19231 + /* 6968 */ MCD_OPC_Decode, + 192, + 25, + 229, + 1, // Opcode: VREV32d8 + /* 6973 */ MCD_OPC_FilterValue, + 3, + 221, + 47, + 0, // Skip to: 19231 + /* 6978 */ MCD_OPC_CheckPredicate, + 26, + 216, + 47, + 0, // Skip to: 19231 + /* 6983 */ MCD_OPC_Decode, + 194, + 25, + 230, + 1, // Opcode: VREV32q8 + /* 6988 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 7056 + /* 6993 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 6996 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7011 + /* 7001 */ MCD_OPC_CheckPredicate, + 26, + 193, + 47, + 0, // Skip to: 19231 + /* 7006 */ MCD_OPC_Decode, + 131, + 17, + 229, + 1, // Opcode: VCGTzv8i8 + /* 7011 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7026 + /* 7016 */ MCD_OPC_CheckPredicate, + 26, + 178, + 47, + 0, // Skip to: 19231 + /* 7021 */ MCD_OPC_Decode, + 250, + 16, + 230, + 1, // Opcode: VCGTzv16i8 + /* 7026 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7041 + /* 7031 */ MCD_OPC_CheckPredicate, + 26, + 163, + 47, + 0, // Skip to: 19231 + /* 7036 */ MCD_OPC_Decode, + 233, + 16, + 229, + 1, // Opcode: VCGEzv8i8 + /* 7041 */ MCD_OPC_FilterValue, + 3, + 153, + 47, + 0, // Skip to: 19231 + /* 7046 */ MCD_OPC_CheckPredicate, + 26, + 148, + 47, + 0, // Skip to: 19231 + /* 7051 */ MCD_OPC_Decode, + 224, + 16, + 230, + 1, // Opcode: VCGEzv16i8 + /* 7056 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 7124 + /* 7061 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7064 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7079 + /* 7069 */ MCD_OPC_CheckPredicate, + 26, + 125, + 47, + 0, // Skip to: 19231 + /* 7074 */ MCD_OPC_Decode, + 246, + 29, + 231, + 1, // Opcode: VSWPd + /* 7079 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7094 + /* 7084 */ MCD_OPC_CheckPredicate, + 26, + 110, + 47, + 0, // Skip to: 19231 + /* 7089 */ MCD_OPC_Decode, + 247, + 29, + 232, + 1, // Opcode: VSWPq + /* 7094 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7109 + /* 7099 */ MCD_OPC_CheckPredicate, + 26, + 95, + 47, + 0, // Skip to: 19231 + /* 7104 */ MCD_OPC_Decode, + 158, + 30, + 231, + 1, // Opcode: VTRNd8 + /* 7109 */ MCD_OPC_FilterValue, + 3, + 85, + 47, + 0, // Skip to: 19231 + /* 7114 */ MCD_OPC_CheckPredicate, + 26, + 80, + 47, + 0, // Skip to: 19231 + /* 7119 */ MCD_OPC_Decode, + 161, + 30, + 232, + 1, // Opcode: VTRNq8 + /* 7124 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 7192 + /* 7129 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7132 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7147 + /* 7137 */ MCD_OPC_CheckPredicate, + 26, + 57, + 47, + 0, // Skip to: 19231 + /* 7142 */ MCD_OPC_Decode, + 195, + 25, + 229, + 1, // Opcode: VREV64d16 + /* 7147 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7162 + /* 7152 */ MCD_OPC_CheckPredicate, + 26, + 42, + 47, + 0, // Skip to: 19231 + /* 7157 */ MCD_OPC_Decode, + 198, + 25, + 230, + 1, // Opcode: VREV64q16 + /* 7162 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7177 + /* 7167 */ MCD_OPC_CheckPredicate, + 26, + 27, + 47, + 0, // Skip to: 19231 + /* 7172 */ MCD_OPC_Decode, + 191, + 25, + 229, + 1, // Opcode: VREV32d16 + /* 7177 */ MCD_OPC_FilterValue, + 3, + 17, + 47, + 0, // Skip to: 19231 + /* 7182 */ MCD_OPC_CheckPredicate, + 26, + 12, + 47, + 0, // Skip to: 19231 + /* 7187 */ MCD_OPC_Decode, + 193, + 25, + 230, + 1, // Opcode: VREV32q16 + /* 7192 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 7260 + /* 7197 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7200 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7215 + /* 7205 */ MCD_OPC_CheckPredicate, + 26, + 245, + 46, + 0, // Skip to: 19231 + /* 7210 */ MCD_OPC_Decode, + 255, + 16, + 229, + 1, // Opcode: VCGTzv4i16 + /* 7215 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7230 + /* 7220 */ MCD_OPC_CheckPredicate, + 26, + 230, + 46, + 0, // Skip to: 19231 + /* 7225 */ MCD_OPC_Decode, + 130, + 17, + 230, + 1, // Opcode: VCGTzv8i16 + /* 7230 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7245 + /* 7235 */ MCD_OPC_CheckPredicate, + 26, + 215, + 46, + 0, // Skip to: 19231 + /* 7240 */ MCD_OPC_Decode, + 229, + 16, + 229, + 1, // Opcode: VCGEzv4i16 + /* 7245 */ MCD_OPC_FilterValue, + 3, + 205, + 46, + 0, // Skip to: 19231 + /* 7250 */ MCD_OPC_CheckPredicate, + 26, + 200, + 46, + 0, // Skip to: 19231 + /* 7255 */ MCD_OPC_Decode, + 232, + 16, + 230, + 1, // Opcode: VCGEzv8i16 + /* 7260 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 7298 + /* 7265 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7268 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7283 + /* 7273 */ MCD_OPC_CheckPredicate, + 26, + 177, + 46, + 0, // Skip to: 19231 + /* 7278 */ MCD_OPC_Decode, + 156, + 30, + 231, + 1, // Opcode: VTRNd16 + /* 7283 */ MCD_OPC_FilterValue, + 3, + 167, + 46, + 0, // Skip to: 19231 + /* 7288 */ MCD_OPC_CheckPredicate, + 26, + 162, + 46, + 0, // Skip to: 19231 + /* 7293 */ MCD_OPC_Decode, + 159, + 30, + 232, + 1, // Opcode: VTRNq16 + /* 7298 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 7336 + /* 7303 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7306 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7321 + /* 7311 */ MCD_OPC_CheckPredicate, + 26, + 139, + 46, + 0, // Skip to: 19231 + /* 7316 */ MCD_OPC_Decode, + 196, + 25, + 229, + 1, // Opcode: VREV64d32 + /* 7321 */ MCD_OPC_FilterValue, + 1, + 129, + 46, + 0, // Skip to: 19231 + /* 7326 */ MCD_OPC_CheckPredicate, + 26, + 124, + 46, + 0, // Skip to: 19231 + /* 7331 */ MCD_OPC_Decode, + 199, + 25, + 230, + 1, // Opcode: VREV64q32 + /* 7336 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 7404 + /* 7341 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7344 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7359 + /* 7349 */ MCD_OPC_CheckPredicate, + 26, + 101, + 46, + 0, // Skip to: 19231 + /* 7354 */ MCD_OPC_Decode, + 252, + 16, + 229, + 1, // Opcode: VCGTzv2i32 + /* 7359 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7374 + /* 7364 */ MCD_OPC_CheckPredicate, + 26, + 86, + 46, + 0, // Skip to: 19231 + /* 7369 */ MCD_OPC_Decode, + 128, + 17, + 230, + 1, // Opcode: VCGTzv4i32 + /* 7374 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7389 + /* 7379 */ MCD_OPC_CheckPredicate, + 26, + 71, + 46, + 0, // Skip to: 19231 + /* 7384 */ MCD_OPC_Decode, + 226, + 16, + 229, + 1, // Opcode: VCGEzv2i32 + /* 7389 */ MCD_OPC_FilterValue, + 3, + 61, + 46, + 0, // Skip to: 19231 + /* 7394 */ MCD_OPC_CheckPredicate, + 26, + 56, + 46, + 0, // Skip to: 19231 + /* 7399 */ MCD_OPC_Decode, + 230, + 16, + 230, + 1, // Opcode: VCGEzv4i32 + /* 7404 */ MCD_OPC_FilterValue, + 10, + 46, + 46, + 0, // Skip to: 19231 + /* 7409 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7412 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7427 + /* 7417 */ MCD_OPC_CheckPredicate, + 26, + 33, + 46, + 0, // Skip to: 19231 + /* 7422 */ MCD_OPC_Decode, + 157, + 30, + 231, + 1, // Opcode: VTRNd32 + /* 7427 */ MCD_OPC_FilterValue, + 3, + 23, + 46, + 0, // Skip to: 19231 + /* 7432 */ MCD_OPC_CheckPredicate, + 26, + 18, + 46, + 0, // Skip to: 19231 + /* 7437 */ MCD_OPC_Decode, + 160, + 30, + 232, + 1, // Opcode: VTRNq32 + /* 7442 */ MCD_OPC_FilterValue, + 1, + 163, + 1, + 0, // Skip to: 7866 + /* 7447 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 7450 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 7488 + /* 7455 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7458 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7473 + /* 7463 */ MCD_OPC_CheckPredicate, + 26, + 243, + 45, + 0, // Skip to: 19231 + /* 7468 */ MCD_OPC_Decode, + 189, + 25, + 229, + 1, // Opcode: VREV16d8 + /* 7473 */ MCD_OPC_FilterValue, + 1, + 233, + 45, + 0, // Skip to: 19231 + /* 7478 */ MCD_OPC_CheckPredicate, + 26, + 228, + 45, + 0, // Skip to: 19231 + /* 7483 */ MCD_OPC_Decode, + 190, + 25, + 230, + 1, // Opcode: VREV16q8 + /* 7488 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 7556 + /* 7493 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7496 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7511 + /* 7501 */ MCD_OPC_CheckPredicate, + 26, + 205, + 45, + 0, // Skip to: 19231 + /* 7506 */ MCD_OPC_Decode, + 207, + 16, + 229, + 1, // Opcode: VCEQzv8i8 + /* 7511 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7526 + /* 7516 */ MCD_OPC_CheckPredicate, + 26, + 190, + 45, + 0, // Skip to: 19231 + /* 7521 */ MCD_OPC_Decode, + 198, + 16, + 230, + 1, // Opcode: VCEQzv16i8 + /* 7526 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7541 + /* 7531 */ MCD_OPC_CheckPredicate, + 26, + 175, + 45, + 0, // Skip to: 19231 + /* 7536 */ MCD_OPC_Decode, + 141, + 17, + 229, + 1, // Opcode: VCLEzv8i8 + /* 7541 */ MCD_OPC_FilterValue, + 3, + 165, + 45, + 0, // Skip to: 19231 + /* 7546 */ MCD_OPC_CheckPredicate, + 26, + 160, + 45, + 0, // Skip to: 19231 + /* 7551 */ MCD_OPC_Decode, + 132, + 17, + 230, + 1, // Opcode: VCLEzv16i8 + /* 7556 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 7624 + /* 7561 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7564 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7579 + /* 7569 */ MCD_OPC_CheckPredicate, + 26, + 137, + 45, + 0, // Skip to: 19231 + /* 7574 */ MCD_OPC_Decode, + 188, + 30, + 231, + 1, // Opcode: VUZPd8 + /* 7579 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7594 + /* 7584 */ MCD_OPC_CheckPredicate, + 26, + 122, + 45, + 0, // Skip to: 19231 + /* 7589 */ MCD_OPC_Decode, + 191, + 30, + 232, + 1, // Opcode: VUZPq8 + /* 7594 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7609 + /* 7599 */ MCD_OPC_CheckPredicate, + 26, + 107, + 45, + 0, // Skip to: 19231 + /* 7604 */ MCD_OPC_Decode, + 193, + 30, + 231, + 1, // Opcode: VZIPd8 + /* 7609 */ MCD_OPC_FilterValue, + 3, + 97, + 45, + 0, // Skip to: 19231 + /* 7614 */ MCD_OPC_CheckPredicate, + 26, + 92, + 45, + 0, // Skip to: 19231 + /* 7619 */ MCD_OPC_Decode, + 196, + 30, + 232, + 1, // Opcode: VZIPq8 + /* 7624 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 7692 + /* 7629 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7632 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7647 + /* 7637 */ MCD_OPC_CheckPredicate, + 26, + 69, + 45, + 0, // Skip to: 19231 + /* 7642 */ MCD_OPC_Decode, + 203, + 16, + 229, + 1, // Opcode: VCEQzv4i16 + /* 7647 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7662 + /* 7652 */ MCD_OPC_CheckPredicate, + 26, + 54, + 45, + 0, // Skip to: 19231 + /* 7657 */ MCD_OPC_Decode, + 206, + 16, + 230, + 1, // Opcode: VCEQzv8i16 + /* 7662 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7677 + /* 7667 */ MCD_OPC_CheckPredicate, + 26, + 39, + 45, + 0, // Skip to: 19231 + /* 7672 */ MCD_OPC_Decode, + 137, + 17, + 229, + 1, // Opcode: VCLEzv4i16 + /* 7677 */ MCD_OPC_FilterValue, + 3, + 29, + 45, + 0, // Skip to: 19231 + /* 7682 */ MCD_OPC_CheckPredicate, + 26, + 24, + 45, + 0, // Skip to: 19231 + /* 7687 */ MCD_OPC_Decode, + 140, + 17, + 230, + 1, // Opcode: VCLEzv8i16 + /* 7692 */ MCD_OPC_FilterValue, + 6, + 63, + 0, + 0, // Skip to: 7760 + /* 7697 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7700 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7715 + /* 7705 */ MCD_OPC_CheckPredicate, + 26, + 1, + 45, + 0, // Skip to: 19231 + /* 7710 */ MCD_OPC_Decode, + 187, + 30, + 231, + 1, // Opcode: VUZPd16 + /* 7715 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7730 + /* 7720 */ MCD_OPC_CheckPredicate, + 26, + 242, + 44, + 0, // Skip to: 19231 + /* 7725 */ MCD_OPC_Decode, + 189, + 30, + 232, + 1, // Opcode: VUZPq16 + /* 7730 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7745 + /* 7735 */ MCD_OPC_CheckPredicate, + 26, + 227, + 44, + 0, // Skip to: 19231 + /* 7740 */ MCD_OPC_Decode, + 192, + 30, + 231, + 1, // Opcode: VZIPd16 + /* 7745 */ MCD_OPC_FilterValue, + 3, + 217, + 44, + 0, // Skip to: 19231 + /* 7750 */ MCD_OPC_CheckPredicate, + 26, + 212, + 44, + 0, // Skip to: 19231 + /* 7755 */ MCD_OPC_Decode, + 194, + 30, + 232, + 1, // Opcode: VZIPq16 + /* 7760 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 7828 + /* 7765 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7768 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7783 + /* 7773 */ MCD_OPC_CheckPredicate, + 26, + 189, + 44, + 0, // Skip to: 19231 + /* 7778 */ MCD_OPC_Decode, + 200, + 16, + 229, + 1, // Opcode: VCEQzv2i32 + /* 7783 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7798 + /* 7788 */ MCD_OPC_CheckPredicate, + 26, + 174, + 44, + 0, // Skip to: 19231 + /* 7793 */ MCD_OPC_Decode, + 204, + 16, + 230, + 1, // Opcode: VCEQzv4i32 + /* 7798 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7813 + /* 7803 */ MCD_OPC_CheckPredicate, + 26, + 159, + 44, + 0, // Skip to: 19231 + /* 7808 */ MCD_OPC_Decode, + 134, + 17, + 229, + 1, // Opcode: VCLEzv2i32 + /* 7813 */ MCD_OPC_FilterValue, + 3, + 149, + 44, + 0, // Skip to: 19231 + /* 7818 */ MCD_OPC_CheckPredicate, + 26, + 144, + 44, + 0, // Skip to: 19231 + /* 7823 */ MCD_OPC_Decode, + 138, + 17, + 230, + 1, // Opcode: VCLEzv4i32 + /* 7828 */ MCD_OPC_FilterValue, + 10, + 134, + 44, + 0, // Skip to: 19231 + /* 7833 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7836 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7851 + /* 7841 */ MCD_OPC_CheckPredicate, + 26, + 121, + 44, + 0, // Skip to: 19231 + /* 7846 */ MCD_OPC_Decode, + 190, + 30, + 232, + 1, // Opcode: VUZPq32 + /* 7851 */ MCD_OPC_FilterValue, + 3, + 111, + 44, + 0, // Skip to: 19231 + /* 7856 */ MCD_OPC_CheckPredicate, + 26, + 106, + 44, + 0, // Skip to: 19231 + /* 7861 */ MCD_OPC_Decode, + 195, + 30, + 232, + 1, // Opcode: VZIPq32 + /* 7866 */ MCD_OPC_FilterValue, + 2, + 13, + 2, + 0, // Skip to: 8396 + /* 7871 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 7874 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 7942 + /* 7879 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7882 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7897 + /* 7887 */ MCD_OPC_CheckPredicate, + 26, + 75, + 44, + 0, // Skip to: 19231 + /* 7892 */ MCD_OPC_Decode, + 233, + 23, + 229, + 1, // Opcode: VPADDLsv8i8 + /* 7897 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7912 + /* 7902 */ MCD_OPC_CheckPredicate, + 26, + 60, + 44, + 0, // Skip to: 19231 + /* 7907 */ MCD_OPC_Decode, + 228, + 23, + 230, + 1, // Opcode: VPADDLsv16i8 + /* 7912 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7927 + /* 7917 */ MCD_OPC_CheckPredicate, + 26, + 45, + 44, + 0, // Skip to: 19231 + /* 7922 */ MCD_OPC_Decode, + 239, + 23, + 229, + 1, // Opcode: VPADDLuv8i8 + /* 7927 */ MCD_OPC_FilterValue, + 3, + 35, + 44, + 0, // Skip to: 19231 + /* 7932 */ MCD_OPC_CheckPredicate, + 26, + 30, + 44, + 0, // Skip to: 19231 + /* 7937 */ MCD_OPC_Decode, + 234, + 23, + 230, + 1, // Opcode: VPADDLuv16i8 + /* 7942 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 7980 + /* 7947 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7950 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7965 + /* 7955 */ MCD_OPC_CheckPredicate, + 26, + 7, + 44, + 0, // Skip to: 19231 + /* 7960 */ MCD_OPC_Decode, + 157, + 17, + 229, + 1, // Opcode: VCLTzv8i8 + /* 7965 */ MCD_OPC_FilterValue, + 1, + 253, + 43, + 0, // Skip to: 19231 + /* 7970 */ MCD_OPC_CheckPredicate, + 26, + 248, + 43, + 0, // Skip to: 19231 + /* 7975 */ MCD_OPC_Decode, + 148, + 17, + 230, + 1, // Opcode: VCLTzv16i8 + /* 7980 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 8048 + /* 7985 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 7988 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8003 + /* 7993 */ MCD_OPC_CheckPredicate, + 26, + 225, + 43, + 0, // Skip to: 19231 + /* 7998 */ MCD_OPC_Decode, + 232, + 22, + 233, + 1, // Opcode: VMOVNv8i8 + /* 8003 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8018 + /* 8008 */ MCD_OPC_CheckPredicate, + 26, + 210, + 43, + 0, // Skip to: 19231 + /* 8013 */ MCD_OPC_Decode, + 177, + 24, + 233, + 1, // Opcode: VQMOVNsuv8i8 + /* 8018 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8033 + /* 8023 */ MCD_OPC_CheckPredicate, + 26, + 195, + 43, + 0, // Skip to: 19231 + /* 8028 */ MCD_OPC_Decode, + 180, + 24, + 233, + 1, // Opcode: VQMOVNsv8i8 + /* 8033 */ MCD_OPC_FilterValue, + 3, + 185, + 43, + 0, // Skip to: 19231 + /* 8038 */ MCD_OPC_CheckPredicate, + 26, + 180, + 43, + 0, // Skip to: 19231 + /* 8043 */ MCD_OPC_Decode, + 183, + 24, + 233, + 1, // Opcode: VQMOVNuv8i8 + /* 8048 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 8116 + /* 8053 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8056 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8071 + /* 8061 */ MCD_OPC_CheckPredicate, + 26, + 157, + 43, + 0, // Skip to: 19231 + /* 8066 */ MCD_OPC_Decode, + 230, + 23, + 229, + 1, // Opcode: VPADDLsv4i16 + /* 8071 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8086 + /* 8076 */ MCD_OPC_CheckPredicate, + 26, + 142, + 43, + 0, // Skip to: 19231 + /* 8081 */ MCD_OPC_Decode, + 232, + 23, + 230, + 1, // Opcode: VPADDLsv8i16 + /* 8086 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8101 + /* 8091 */ MCD_OPC_CheckPredicate, + 26, + 127, + 43, + 0, // Skip to: 19231 + /* 8096 */ MCD_OPC_Decode, + 236, + 23, + 229, + 1, // Opcode: VPADDLuv4i16 + /* 8101 */ MCD_OPC_FilterValue, + 3, + 117, + 43, + 0, // Skip to: 19231 + /* 8106 */ MCD_OPC_CheckPredicate, + 26, + 112, + 43, + 0, // Skip to: 19231 + /* 8111 */ MCD_OPC_Decode, + 238, + 23, + 230, + 1, // Opcode: VPADDLuv8i16 + /* 8116 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 8154 + /* 8121 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8124 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8139 + /* 8129 */ MCD_OPC_CheckPredicate, + 26, + 89, + 43, + 0, // Skip to: 19231 + /* 8134 */ MCD_OPC_Decode, + 153, + 17, + 229, + 1, // Opcode: VCLTzv4i16 + /* 8139 */ MCD_OPC_FilterValue, + 1, + 79, + 43, + 0, // Skip to: 19231 + /* 8144 */ MCD_OPC_CheckPredicate, + 26, + 74, + 43, + 0, // Skip to: 19231 + /* 8149 */ MCD_OPC_Decode, + 156, + 17, + 230, + 1, // Opcode: VCLTzv8i16 + /* 8154 */ MCD_OPC_FilterValue, + 6, + 63, + 0, + 0, // Skip to: 8222 + /* 8159 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8162 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8177 + /* 8167 */ MCD_OPC_CheckPredicate, + 26, + 51, + 43, + 0, // Skip to: 19231 + /* 8172 */ MCD_OPC_Decode, + 231, + 22, + 233, + 1, // Opcode: VMOVNv4i16 + /* 8177 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8192 + /* 8182 */ MCD_OPC_CheckPredicate, + 26, + 36, + 43, + 0, // Skip to: 19231 + /* 8187 */ MCD_OPC_Decode, + 176, + 24, + 233, + 1, // Opcode: VQMOVNsuv4i16 + /* 8192 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8207 + /* 8197 */ MCD_OPC_CheckPredicate, + 26, + 21, + 43, + 0, // Skip to: 19231 + /* 8202 */ MCD_OPC_Decode, + 179, + 24, + 233, + 1, // Opcode: VQMOVNsv4i16 + /* 8207 */ MCD_OPC_FilterValue, + 3, + 11, + 43, + 0, // Skip to: 19231 + /* 8212 */ MCD_OPC_CheckPredicate, + 26, + 6, + 43, + 0, // Skip to: 19231 + /* 8217 */ MCD_OPC_Decode, + 182, + 24, + 233, + 1, // Opcode: VQMOVNuv4i16 + /* 8222 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 8290 + /* 8227 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8230 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8245 + /* 8235 */ MCD_OPC_CheckPredicate, + 26, + 239, + 42, + 0, // Skip to: 19231 + /* 8240 */ MCD_OPC_Decode, + 229, + 23, + 229, + 1, // Opcode: VPADDLsv2i32 + /* 8245 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8260 + /* 8250 */ MCD_OPC_CheckPredicate, + 26, + 224, + 42, + 0, // Skip to: 19231 + /* 8255 */ MCD_OPC_Decode, + 231, + 23, + 230, + 1, // Opcode: VPADDLsv4i32 + /* 8260 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8275 + /* 8265 */ MCD_OPC_CheckPredicate, + 26, + 209, + 42, + 0, // Skip to: 19231 + /* 8270 */ MCD_OPC_Decode, + 235, + 23, + 229, + 1, // Opcode: VPADDLuv2i32 + /* 8275 */ MCD_OPC_FilterValue, + 3, + 199, + 42, + 0, // Skip to: 19231 + /* 8280 */ MCD_OPC_CheckPredicate, + 26, + 194, + 42, + 0, // Skip to: 19231 + /* 8285 */ MCD_OPC_Decode, + 237, + 23, + 230, + 1, // Opcode: VPADDLuv4i32 + /* 8290 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 8328 + /* 8295 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8298 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8313 + /* 8303 */ MCD_OPC_CheckPredicate, + 26, + 171, + 42, + 0, // Skip to: 19231 + /* 8308 */ MCD_OPC_Decode, + 150, + 17, + 229, + 1, // Opcode: VCLTzv2i32 + /* 8313 */ MCD_OPC_FilterValue, + 1, + 161, + 42, + 0, // Skip to: 19231 + /* 8318 */ MCD_OPC_CheckPredicate, + 26, + 156, + 42, + 0, // Skip to: 19231 + /* 8323 */ MCD_OPC_Decode, + 154, + 17, + 230, + 1, // Opcode: VCLTzv4i32 + /* 8328 */ MCD_OPC_FilterValue, + 10, + 146, + 42, + 0, // Skip to: 19231 + /* 8333 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8336 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8351 + /* 8341 */ MCD_OPC_CheckPredicate, + 26, + 133, + 42, + 0, // Skip to: 19231 + /* 8346 */ MCD_OPC_Decode, + 230, + 22, + 233, + 1, // Opcode: VMOVNv2i32 + /* 8351 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8366 + /* 8356 */ MCD_OPC_CheckPredicate, + 26, + 118, + 42, + 0, // Skip to: 19231 + /* 8361 */ MCD_OPC_Decode, + 175, + 24, + 233, + 1, // Opcode: VQMOVNsuv2i32 + /* 8366 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8381 + /* 8371 */ MCD_OPC_CheckPredicate, + 26, + 103, + 42, + 0, // Skip to: 19231 + /* 8376 */ MCD_OPC_Decode, + 178, + 24, + 233, + 1, // Opcode: VQMOVNsv2i32 + /* 8381 */ MCD_OPC_FilterValue, + 3, + 93, + 42, + 0, // Skip to: 19231 + /* 8386 */ MCD_OPC_CheckPredicate, + 26, + 88, + 42, + 0, // Skip to: 19231 + /* 8391 */ MCD_OPC_Decode, + 181, + 24, + 233, + 1, // Opcode: VQMOVNuv2i32 + /* 8396 */ MCD_OPC_FilterValue, + 3, + 17, + 1, + 0, // Skip to: 8674 + /* 8401 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 8404 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 8472 + /* 8409 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8412 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8427 + /* 8417 */ MCD_OPC_CheckPredicate, + 26, + 57, + 42, + 0, // Skip to: 19231 + /* 8422 */ MCD_OPC_Decode, + 253, + 15, + 229, + 1, // Opcode: VABSv8i8 + /* 8427 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8442 + /* 8432 */ MCD_OPC_CheckPredicate, + 26, + 42, + 42, + 0, // Skip to: 19231 + /* 8437 */ MCD_OPC_Decode, + 248, + 15, + 230, + 1, // Opcode: VABSv16i8 + /* 8442 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8457 + /* 8447 */ MCD_OPC_CheckPredicate, + 26, + 27, + 42, + 0, // Skip to: 19231 + /* 8452 */ MCD_OPC_Decode, + 197, + 23, + 229, + 1, // Opcode: VNEGs8d + /* 8457 */ MCD_OPC_FilterValue, + 3, + 17, + 42, + 0, // Skip to: 19231 + /* 8462 */ MCD_OPC_CheckPredicate, + 26, + 12, + 42, + 0, // Skip to: 19231 + /* 8467 */ MCD_OPC_Decode, + 198, + 23, + 230, + 1, // Opcode: VNEGs8q + /* 8472 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 8494 + /* 8477 */ MCD_OPC_CheckPredicate, + 26, + 253, + 41, + 0, // Skip to: 19231 + /* 8482 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 246, + 41, + 0, // Skip to: 19231 + /* 8489 */ MCD_OPC_Decode, + 217, + 26, + 234, + 1, // Opcode: VSHLLi8 + /* 8494 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 8562 + /* 8499 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8502 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8517 + /* 8507 */ MCD_OPC_CheckPredicate, + 26, + 223, + 41, + 0, // Skip to: 19231 + /* 8512 */ MCD_OPC_Decode, + 250, + 15, + 229, + 1, // Opcode: VABSv4i16 + /* 8517 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8532 + /* 8522 */ MCD_OPC_CheckPredicate, + 26, + 208, + 41, + 0, // Skip to: 19231 + /* 8527 */ MCD_OPC_Decode, + 252, + 15, + 230, + 1, // Opcode: VABSv8i16 + /* 8532 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8547 + /* 8537 */ MCD_OPC_CheckPredicate, + 26, + 193, + 41, + 0, // Skip to: 19231 + /* 8542 */ MCD_OPC_Decode, + 193, + 23, + 229, + 1, // Opcode: VNEGs16d + /* 8547 */ MCD_OPC_FilterValue, + 3, + 183, + 41, + 0, // Skip to: 19231 + /* 8552 */ MCD_OPC_CheckPredicate, + 26, + 178, + 41, + 0, // Skip to: 19231 + /* 8557 */ MCD_OPC_Decode, + 194, + 23, + 230, + 1, // Opcode: VNEGs16q + /* 8562 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 8584 + /* 8567 */ MCD_OPC_CheckPredicate, + 26, + 163, + 41, + 0, // Skip to: 19231 + /* 8572 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 156, + 41, + 0, // Skip to: 19231 + /* 8579 */ MCD_OPC_Decode, + 215, + 26, + 234, + 1, // Opcode: VSHLLi16 + /* 8584 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 8652 + /* 8589 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8592 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8607 + /* 8597 */ MCD_OPC_CheckPredicate, + 26, + 133, + 41, + 0, // Skip to: 19231 + /* 8602 */ MCD_OPC_Decode, + 249, + 15, + 229, + 1, // Opcode: VABSv2i32 + /* 8607 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8622 + /* 8612 */ MCD_OPC_CheckPredicate, + 26, + 118, + 41, + 0, // Skip to: 19231 + /* 8617 */ MCD_OPC_Decode, + 251, + 15, + 230, + 1, // Opcode: VABSv4i32 + /* 8622 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8637 + /* 8627 */ MCD_OPC_CheckPredicate, + 26, + 103, + 41, + 0, // Skip to: 19231 + /* 8632 */ MCD_OPC_Decode, + 195, + 23, + 229, + 1, // Opcode: VNEGs32d + /* 8637 */ MCD_OPC_FilterValue, + 3, + 93, + 41, + 0, // Skip to: 19231 + /* 8642 */ MCD_OPC_CheckPredicate, + 26, + 88, + 41, + 0, // Skip to: 19231 + /* 8647 */ MCD_OPC_Decode, + 196, + 23, + 230, + 1, // Opcode: VNEGs32q + /* 8652 */ MCD_OPC_FilterValue, + 10, + 78, + 41, + 0, // Skip to: 19231 + /* 8657 */ MCD_OPC_CheckPredicate, + 26, + 73, + 41, + 0, // Skip to: 19231 + /* 8662 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 66, + 41, + 0, // Skip to: 19231 + /* 8669 */ MCD_OPC_Decode, + 216, + 26, + 234, + 1, // Opcode: VSHLLi32 + /* 8674 */ MCD_OPC_FilterValue, + 4, + 155, + 1, + 0, // Skip to: 9090 + /* 8679 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 8682 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 8750 + /* 8687 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8690 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8705 + /* 8695 */ MCD_OPC_CheckPredicate, + 26, + 35, + 41, + 0, // Skip to: 19231 + /* 8700 */ MCD_OPC_Decode, + 147, + 17, + 229, + 1, // Opcode: VCLSv8i8 + /* 8705 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8720 + /* 8710 */ MCD_OPC_CheckPredicate, + 26, + 20, + 41, + 0, // Skip to: 19231 + /* 8715 */ MCD_OPC_Decode, + 142, + 17, + 230, + 1, // Opcode: VCLSv16i8 + /* 8720 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8735 + /* 8725 */ MCD_OPC_CheckPredicate, + 26, + 5, + 41, + 0, // Skip to: 19231 + /* 8730 */ MCD_OPC_Decode, + 163, + 17, + 229, + 1, // Opcode: VCLZv8i8 + /* 8735 */ MCD_OPC_FilterValue, + 3, + 251, + 40, + 0, // Skip to: 19231 + /* 8740 */ MCD_OPC_CheckPredicate, + 26, + 246, + 40, + 0, // Skip to: 19231 + /* 8745 */ MCD_OPC_Decode, + 158, + 17, + 230, + 1, // Opcode: VCLZv16i8 + /* 8750 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 8818 + /* 8755 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8758 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8773 + /* 8763 */ MCD_OPC_CheckPredicate, + 26, + 223, + 40, + 0, // Skip to: 19231 + /* 8768 */ MCD_OPC_Decode, + 144, + 17, + 229, + 1, // Opcode: VCLSv4i16 + /* 8773 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8788 + /* 8778 */ MCD_OPC_CheckPredicate, + 26, + 208, + 40, + 0, // Skip to: 19231 + /* 8783 */ MCD_OPC_Decode, + 146, + 17, + 230, + 1, // Opcode: VCLSv8i16 + /* 8788 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8803 + /* 8793 */ MCD_OPC_CheckPredicate, + 26, + 193, + 40, + 0, // Skip to: 19231 + /* 8798 */ MCD_OPC_Decode, + 160, + 17, + 229, + 1, // Opcode: VCLZv4i16 + /* 8803 */ MCD_OPC_FilterValue, + 3, + 183, + 40, + 0, // Skip to: 19231 + /* 8808 */ MCD_OPC_CheckPredicate, + 26, + 178, + 40, + 0, // Skip to: 19231 + /* 8813 */ MCD_OPC_Decode, + 162, + 17, + 230, + 1, // Opcode: VCLZv8i16 + /* 8818 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 8886 + /* 8823 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8826 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8841 + /* 8831 */ MCD_OPC_CheckPredicate, + 27, + 155, + 40, + 0, // Skip to: 19231 + /* 8836 */ MCD_OPC_Decode, + 253, + 16, + 229, + 1, // Opcode: VCGTzv4f16 + /* 8841 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8856 + /* 8846 */ MCD_OPC_CheckPredicate, + 27, + 140, + 40, + 0, // Skip to: 19231 + /* 8851 */ MCD_OPC_Decode, + 129, + 17, + 230, + 1, // Opcode: VCGTzv8f16 + /* 8856 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8871 + /* 8861 */ MCD_OPC_CheckPredicate, + 27, + 125, + 40, + 0, // Skip to: 19231 + /* 8866 */ MCD_OPC_Decode, + 227, + 16, + 229, + 1, // Opcode: VCGEzv4f16 + /* 8871 */ MCD_OPC_FilterValue, + 3, + 115, + 40, + 0, // Skip to: 19231 + /* 8876 */ MCD_OPC_CheckPredicate, + 27, + 110, + 40, + 0, // Skip to: 19231 + /* 8881 */ MCD_OPC_Decode, + 231, + 16, + 230, + 1, // Opcode: VCGEzv8f16 + /* 8886 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 8954 + /* 8891 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8894 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8909 + /* 8899 */ MCD_OPC_CheckPredicate, + 26, + 87, + 40, + 0, // Skip to: 19231 + /* 8904 */ MCD_OPC_Decode, + 143, + 17, + 229, + 1, // Opcode: VCLSv2i32 + /* 8909 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8924 + /* 8914 */ MCD_OPC_CheckPredicate, + 26, + 72, + 40, + 0, // Skip to: 19231 + /* 8919 */ MCD_OPC_Decode, + 145, + 17, + 230, + 1, // Opcode: VCLSv4i32 + /* 8924 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8939 + /* 8929 */ MCD_OPC_CheckPredicate, + 26, + 57, + 40, + 0, // Skip to: 19231 + /* 8934 */ MCD_OPC_Decode, + 159, + 17, + 229, + 1, // Opcode: VCLZv2i32 + /* 8939 */ MCD_OPC_FilterValue, + 3, + 47, + 40, + 0, // Skip to: 19231 + /* 8944 */ MCD_OPC_CheckPredicate, + 26, + 42, + 40, + 0, // Skip to: 19231 + /* 8949 */ MCD_OPC_Decode, + 161, + 17, + 230, + 1, // Opcode: VCLZv4i32 + /* 8954 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 9022 + /* 8959 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 8962 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8977 + /* 8967 */ MCD_OPC_CheckPredicate, + 26, + 19, + 40, + 0, // Skip to: 19231 + /* 8972 */ MCD_OPC_Decode, + 251, + 16, + 229, + 1, // Opcode: VCGTzv2f32 + /* 8977 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8992 + /* 8982 */ MCD_OPC_CheckPredicate, + 26, + 4, + 40, + 0, // Skip to: 19231 + /* 8987 */ MCD_OPC_Decode, + 254, + 16, + 230, + 1, // Opcode: VCGTzv4f32 + /* 8992 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9007 + /* 8997 */ MCD_OPC_CheckPredicate, + 26, + 245, + 39, + 0, // Skip to: 19231 + /* 9002 */ MCD_OPC_Decode, + 225, + 16, + 229, + 1, // Opcode: VCGEzv2f32 + /* 9007 */ MCD_OPC_FilterValue, + 3, + 235, + 39, + 0, // Skip to: 19231 + /* 9012 */ MCD_OPC_CheckPredicate, + 26, + 230, + 39, + 0, // Skip to: 19231 + /* 9017 */ MCD_OPC_Decode, + 228, + 16, + 230, + 1, // Opcode: VCGEzv4f32 + /* 9022 */ MCD_OPC_FilterValue, + 11, + 220, + 39, + 0, // Skip to: 19231 + /* 9027 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9030 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9045 + /* 9035 */ MCD_OPC_CheckPredicate, + 26, + 207, + 39, + 0, // Skip to: 19231 + /* 9040 */ MCD_OPC_Decode, + 179, + 25, + 229, + 1, // Opcode: VRECPEd + /* 9045 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9060 + /* 9050 */ MCD_OPC_CheckPredicate, + 26, + 192, + 39, + 0, // Skip to: 19231 + /* 9055 */ MCD_OPC_Decode, + 184, + 25, + 230, + 1, // Opcode: VRECPEq + /* 9060 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9075 + /* 9065 */ MCD_OPC_CheckPredicate, + 26, + 177, + 39, + 0, // Skip to: 19231 + /* 9070 */ MCD_OPC_Decode, + 165, + 26, + 229, + 1, // Opcode: VRSQRTEd + /* 9075 */ MCD_OPC_FilterValue, + 3, + 167, + 39, + 0, // Skip to: 19231 + /* 9080 */ MCD_OPC_CheckPredicate, + 26, + 162, + 39, + 0, // Skip to: 19231 + /* 9085 */ MCD_OPC_Decode, + 170, + 26, + 230, + 1, // Opcode: VRSQRTEq + /* 9090 */ MCD_OPC_FilterValue, + 5, + 87, + 1, + 0, // Skip to: 9438 + /* 9095 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9098 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 9166 + /* 9103 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9106 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9121 + /* 9111 */ MCD_OPC_CheckPredicate, + 26, + 131, + 39, + 0, // Skip to: 19231 + /* 9116 */ MCD_OPC_Decode, + 184, + 17, + 229, + 1, // Opcode: VCNTd + /* 9121 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9136 + /* 9126 */ MCD_OPC_CheckPredicate, + 26, + 116, + 39, + 0, // Skip to: 19231 + /* 9131 */ MCD_OPC_Decode, + 185, + 17, + 230, + 1, // Opcode: VCNTq + /* 9136 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9151 + /* 9141 */ MCD_OPC_CheckPredicate, + 26, + 101, + 39, + 0, // Skip to: 19231 + /* 9146 */ MCD_OPC_Decode, + 180, + 23, + 229, + 1, // Opcode: VMVNd + /* 9151 */ MCD_OPC_FilterValue, + 3, + 91, + 39, + 0, // Skip to: 19231 + /* 9156 */ MCD_OPC_CheckPredicate, + 26, + 86, + 39, + 0, // Skip to: 19231 + /* 9161 */ MCD_OPC_Decode, + 181, + 23, + 230, + 1, // Opcode: VMVNq + /* 9166 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 9234 + /* 9171 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9174 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9189 + /* 9179 */ MCD_OPC_CheckPredicate, + 27, + 63, + 39, + 0, // Skip to: 19231 + /* 9184 */ MCD_OPC_Decode, + 201, + 16, + 229, + 1, // Opcode: VCEQzv4f16 + /* 9189 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9204 + /* 9194 */ MCD_OPC_CheckPredicate, + 27, + 48, + 39, + 0, // Skip to: 19231 + /* 9199 */ MCD_OPC_Decode, + 205, + 16, + 230, + 1, // Opcode: VCEQzv8f16 + /* 9204 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9219 + /* 9209 */ MCD_OPC_CheckPredicate, + 27, + 33, + 39, + 0, // Skip to: 19231 + /* 9214 */ MCD_OPC_Decode, + 135, + 17, + 229, + 1, // Opcode: VCLEzv4f16 + /* 9219 */ MCD_OPC_FilterValue, + 3, + 23, + 39, + 0, // Skip to: 19231 + /* 9224 */ MCD_OPC_CheckPredicate, + 27, + 18, + 39, + 0, // Skip to: 19231 + /* 9229 */ MCD_OPC_Decode, + 139, + 17, + 230, + 1, // Opcode: VCLEzv8f16 + /* 9234 */ MCD_OPC_FilterValue, + 7, + 63, + 0, + 0, // Skip to: 9302 + /* 9239 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9242 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9257 + /* 9247 */ MCD_OPC_CheckPredicate, + 27, + 251, + 38, + 0, // Skip to: 19231 + /* 9252 */ MCD_OPC_Decode, + 182, + 25, + 229, + 1, // Opcode: VRECPEhd + /* 9257 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9272 + /* 9262 */ MCD_OPC_CheckPredicate, + 27, + 236, + 38, + 0, // Skip to: 19231 + /* 9267 */ MCD_OPC_Decode, + 183, + 25, + 230, + 1, // Opcode: VRECPEhq + /* 9272 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9287 + /* 9277 */ MCD_OPC_CheckPredicate, + 27, + 221, + 38, + 0, // Skip to: 19231 + /* 9282 */ MCD_OPC_Decode, + 168, + 26, + 229, + 1, // Opcode: VRSQRTEhd + /* 9287 */ MCD_OPC_FilterValue, + 3, + 211, + 38, + 0, // Skip to: 19231 + /* 9292 */ MCD_OPC_CheckPredicate, + 27, + 206, + 38, + 0, // Skip to: 19231 + /* 9297 */ MCD_OPC_Decode, + 169, + 26, + 230, + 1, // Opcode: VRSQRTEhq + /* 9302 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 9370 + /* 9307 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9310 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9325 + /* 9315 */ MCD_OPC_CheckPredicate, + 26, + 183, + 38, + 0, // Skip to: 19231 + /* 9320 */ MCD_OPC_Decode, + 199, + 16, + 229, + 1, // Opcode: VCEQzv2f32 + /* 9325 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9340 + /* 9330 */ MCD_OPC_CheckPredicate, + 26, + 168, + 38, + 0, // Skip to: 19231 + /* 9335 */ MCD_OPC_Decode, + 202, + 16, + 230, + 1, // Opcode: VCEQzv4f32 + /* 9340 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9355 + /* 9345 */ MCD_OPC_CheckPredicate, + 26, + 153, + 38, + 0, // Skip to: 19231 + /* 9350 */ MCD_OPC_Decode, + 133, + 17, + 229, + 1, // Opcode: VCLEzv2f32 + /* 9355 */ MCD_OPC_FilterValue, + 3, + 143, + 38, + 0, // Skip to: 19231 + /* 9360 */ MCD_OPC_CheckPredicate, + 26, + 138, + 38, + 0, // Skip to: 19231 + /* 9365 */ MCD_OPC_Decode, + 136, + 17, + 230, + 1, // Opcode: VCLEzv4f32 + /* 9370 */ MCD_OPC_FilterValue, + 11, + 128, + 38, + 0, // Skip to: 19231 + /* 9375 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9378 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9393 + /* 9383 */ MCD_OPC_CheckPredicate, + 26, + 115, + 38, + 0, // Skip to: 19231 + /* 9388 */ MCD_OPC_Decode, + 180, + 25, + 229, + 1, // Opcode: VRECPEfd + /* 9393 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9408 + /* 9398 */ MCD_OPC_CheckPredicate, + 26, + 100, + 38, + 0, // Skip to: 19231 + /* 9403 */ MCD_OPC_Decode, + 181, + 25, + 230, + 1, // Opcode: VRECPEfq + /* 9408 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9423 + /* 9413 */ MCD_OPC_CheckPredicate, + 26, + 85, + 38, + 0, // Skip to: 19231 + /* 9418 */ MCD_OPC_Decode, + 166, + 26, + 229, + 1, // Opcode: VRSQRTEfd + /* 9423 */ MCD_OPC_FilterValue, + 3, + 75, + 38, + 0, // Skip to: 19231 + /* 9428 */ MCD_OPC_CheckPredicate, + 26, + 70, + 38, + 0, // Skip to: 19231 + /* 9433 */ MCD_OPC_Decode, + 167, + 26, + 230, + 1, // Opcode: VRSQRTEfq + /* 9438 */ MCD_OPC_FilterValue, + 6, + 201, + 1, + 0, // Skip to: 9900 + /* 9443 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9446 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 9514 + /* 9451 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9454 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9469 + /* 9459 */ MCD_OPC_CheckPredicate, + 26, + 39, + 38, + 0, // Skip to: 19231 + /* 9464 */ MCD_OPC_Decode, + 221, + 23, + 235, + 1, // Opcode: VPADALsv8i8 + /* 9469 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9484 + /* 9474 */ MCD_OPC_CheckPredicate, + 26, + 24, + 38, + 0, // Skip to: 19231 + /* 9479 */ MCD_OPC_Decode, + 216, + 23, + 236, + 1, // Opcode: VPADALsv16i8 + /* 9484 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9499 + /* 9489 */ MCD_OPC_CheckPredicate, + 26, + 9, + 38, + 0, // Skip to: 19231 + /* 9494 */ MCD_OPC_Decode, + 227, + 23, + 235, + 1, // Opcode: VPADALuv8i8 + /* 9499 */ MCD_OPC_FilterValue, + 3, + 255, + 37, + 0, // Skip to: 19231 + /* 9504 */ MCD_OPC_CheckPredicate, + 26, + 250, + 37, + 0, // Skip to: 19231 + /* 9509 */ MCD_OPC_Decode, + 222, + 23, + 236, + 1, // Opcode: VPADALuv16i8 + /* 9514 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 9582 + /* 9519 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9522 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9537 + /* 9527 */ MCD_OPC_CheckPredicate, + 26, + 227, + 37, + 0, // Skip to: 19231 + /* 9532 */ MCD_OPC_Decode, + 218, + 23, + 235, + 1, // Opcode: VPADALsv4i16 + /* 9537 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9552 + /* 9542 */ MCD_OPC_CheckPredicate, + 26, + 212, + 37, + 0, // Skip to: 19231 + /* 9547 */ MCD_OPC_Decode, + 220, + 23, + 236, + 1, // Opcode: VPADALsv8i16 + /* 9552 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9567 + /* 9557 */ MCD_OPC_CheckPredicate, + 26, + 197, + 37, + 0, // Skip to: 19231 + /* 9562 */ MCD_OPC_Decode, + 224, + 23, + 235, + 1, // Opcode: VPADALuv4i16 + /* 9567 */ MCD_OPC_FilterValue, + 3, + 187, + 37, + 0, // Skip to: 19231 + /* 9572 */ MCD_OPC_CheckPredicate, + 26, + 182, + 37, + 0, // Skip to: 19231 + /* 9577 */ MCD_OPC_Decode, + 226, + 23, + 236, + 1, // Opcode: VPADALuv8i16 + /* 9582 */ MCD_OPC_FilterValue, + 5, + 33, + 0, + 0, // Skip to: 9620 + /* 9587 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9590 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9605 + /* 9595 */ MCD_OPC_CheckPredicate, + 27, + 159, + 37, + 0, // Skip to: 19231 + /* 9600 */ MCD_OPC_Decode, + 151, + 17, + 229, + 1, // Opcode: VCLTzv4f16 + /* 9605 */ MCD_OPC_FilterValue, + 1, + 149, + 37, + 0, // Skip to: 19231 + /* 9610 */ MCD_OPC_CheckPredicate, + 27, + 144, + 37, + 0, // Skip to: 19231 + /* 9615 */ MCD_OPC_Decode, + 155, + 17, + 230, + 1, // Opcode: VCLTzv8f16 + /* 9620 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 9658 + /* 9625 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9628 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9643 + /* 9633 */ MCD_OPC_CheckPredicate, + 30, + 121, + 37, + 0, // Skip to: 19231 + /* 9638 */ MCD_OPC_Decode, + 252, + 17, + 233, + 1, // Opcode: VCVTf2h + /* 9643 */ MCD_OPC_FilterValue, + 1, + 111, + 37, + 0, // Skip to: 19231 + /* 9648 */ MCD_OPC_CheckPredicate, + 31, + 106, + 37, + 0, // Skip to: 19231 + /* 9653 */ MCD_OPC_Decode, + 196, + 5, + 233, + 1, // Opcode: BF16_VCVT + /* 9658 */ MCD_OPC_FilterValue, + 7, + 63, + 0, + 0, // Skip to: 9726 + /* 9663 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9666 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9681 + /* 9671 */ MCD_OPC_CheckPredicate, + 27, + 83, + 37, + 0, // Skip to: 19231 + /* 9676 */ MCD_OPC_Decode, + 144, + 18, + 229, + 1, // Opcode: VCVTs2hd + /* 9681 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9696 + /* 9686 */ MCD_OPC_CheckPredicate, + 27, + 68, + 37, + 0, // Skip to: 19231 + /* 9691 */ MCD_OPC_Decode, + 145, + 18, + 230, + 1, // Opcode: VCVTs2hq + /* 9696 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9711 + /* 9701 */ MCD_OPC_CheckPredicate, + 27, + 53, + 37, + 0, // Skip to: 19231 + /* 9706 */ MCD_OPC_Decode, + 148, + 18, + 229, + 1, // Opcode: VCVTu2hd + /* 9711 */ MCD_OPC_FilterValue, + 3, + 43, + 37, + 0, // Skip to: 19231 + /* 9716 */ MCD_OPC_CheckPredicate, + 27, + 38, + 37, + 0, // Skip to: 19231 + /* 9721 */ MCD_OPC_Decode, + 149, + 18, + 230, + 1, // Opcode: VCVTu2hq + /* 9726 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 9794 + /* 9731 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9734 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9749 + /* 9739 */ MCD_OPC_CheckPredicate, + 26, + 15, + 37, + 0, // Skip to: 19231 + /* 9744 */ MCD_OPC_Decode, + 217, + 23, + 235, + 1, // Opcode: VPADALsv2i32 + /* 9749 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9764 + /* 9754 */ MCD_OPC_CheckPredicate, + 26, + 0, + 37, + 0, // Skip to: 19231 + /* 9759 */ MCD_OPC_Decode, + 219, + 23, + 236, + 1, // Opcode: VPADALsv4i32 + /* 9764 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9779 + /* 9769 */ MCD_OPC_CheckPredicate, + 26, + 241, + 36, + 0, // Skip to: 19231 + /* 9774 */ MCD_OPC_Decode, + 223, + 23, + 235, + 1, // Opcode: VPADALuv2i32 + /* 9779 */ MCD_OPC_FilterValue, + 3, + 231, + 36, + 0, // Skip to: 19231 + /* 9784 */ MCD_OPC_CheckPredicate, + 26, + 226, + 36, + 0, // Skip to: 19231 + /* 9789 */ MCD_OPC_Decode, + 225, + 23, + 236, + 1, // Opcode: VPADALuv4i32 + /* 9794 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 9832 + /* 9799 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9802 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9817 + /* 9807 */ MCD_OPC_CheckPredicate, + 26, + 203, + 36, + 0, // Skip to: 19231 + /* 9812 */ MCD_OPC_Decode, + 149, + 17, + 229, + 1, // Opcode: VCLTzv2f32 + /* 9817 */ MCD_OPC_FilterValue, + 1, + 193, + 36, + 0, // Skip to: 19231 + /* 9822 */ MCD_OPC_CheckPredicate, + 26, + 188, + 36, + 0, // Skip to: 19231 + /* 9827 */ MCD_OPC_Decode, + 152, + 17, + 230, + 1, // Opcode: VCLTzv4f32 + /* 9832 */ MCD_OPC_FilterValue, + 11, + 178, + 36, + 0, // Skip to: 19231 + /* 9837 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9840 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9855 + /* 9845 */ MCD_OPC_CheckPredicate, + 26, + 165, + 36, + 0, // Skip to: 19231 + /* 9850 */ MCD_OPC_Decode, + 142, + 18, + 229, + 1, // Opcode: VCVTs2fd + /* 9855 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9870 + /* 9860 */ MCD_OPC_CheckPredicate, + 26, + 150, + 36, + 0, // Skip to: 19231 + /* 9865 */ MCD_OPC_Decode, + 143, + 18, + 230, + 1, // Opcode: VCVTs2fq + /* 9870 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9885 + /* 9875 */ MCD_OPC_CheckPredicate, + 26, + 135, + 36, + 0, // Skip to: 19231 + /* 9880 */ MCD_OPC_Decode, + 146, + 18, + 229, + 1, // Opcode: VCVTu2fd + /* 9885 */ MCD_OPC_FilterValue, + 3, + 125, + 36, + 0, // Skip to: 19231 + /* 9890 */ MCD_OPC_CheckPredicate, + 26, + 120, + 36, + 0, // Skip to: 19231 + /* 9895 */ MCD_OPC_Decode, + 147, + 18, + 230, + 1, // Opcode: VCVTu2fq + /* 9900 */ MCD_OPC_FilterValue, + 7, + 245, + 1, + 0, // Skip to: 10406 + /* 9905 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9908 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 9976 + /* 9913 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9916 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9931 + /* 9921 */ MCD_OPC_CheckPredicate, + 26, + 89, + 36, + 0, // Skip to: 19231 + /* 9926 */ MCD_OPC_Decode, + 138, + 24, + 229, + 1, // Opcode: VQABSv8i8 + /* 9931 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9946 + /* 9936 */ MCD_OPC_CheckPredicate, + 26, + 74, + 36, + 0, // Skip to: 19231 + /* 9941 */ MCD_OPC_Decode, + 133, + 24, + 230, + 1, // Opcode: VQABSv16i8 + /* 9946 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9961 + /* 9951 */ MCD_OPC_CheckPredicate, + 26, + 59, + 36, + 0, // Skip to: 19231 + /* 9956 */ MCD_OPC_Decode, + 189, + 24, + 229, + 1, // Opcode: VQNEGv8i8 + /* 9961 */ MCD_OPC_FilterValue, + 3, + 49, + 36, + 0, // Skip to: 19231 + /* 9966 */ MCD_OPC_CheckPredicate, + 26, + 44, + 36, + 0, // Skip to: 19231 + /* 9971 */ MCD_OPC_Decode, + 184, + 24, + 230, + 1, // Opcode: VQNEGv16i8 + /* 9976 */ MCD_OPC_FilterValue, + 4, + 63, + 0, + 0, // Skip to: 10044 + /* 9981 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 9984 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9999 + /* 9989 */ MCD_OPC_CheckPredicate, + 26, + 21, + 36, + 0, // Skip to: 19231 + /* 9994 */ MCD_OPC_Decode, + 135, + 24, + 229, + 1, // Opcode: VQABSv4i16 + /* 9999 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10014 + /* 10004 */ MCD_OPC_CheckPredicate, + 26, + 6, + 36, + 0, // Skip to: 19231 + /* 10009 */ MCD_OPC_Decode, + 137, + 24, + 230, + 1, // Opcode: VQABSv8i16 + /* 10014 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10029 + /* 10019 */ MCD_OPC_CheckPredicate, + 26, + 247, + 35, + 0, // Skip to: 19231 + /* 10024 */ MCD_OPC_Decode, + 186, + 24, + 229, + 1, // Opcode: VQNEGv4i16 + /* 10029 */ MCD_OPC_FilterValue, + 3, + 237, + 35, + 0, // Skip to: 19231 + /* 10034 */ MCD_OPC_CheckPredicate, + 26, + 232, + 35, + 0, // Skip to: 19231 + /* 10039 */ MCD_OPC_Decode, + 188, + 24, + 230, + 1, // Opcode: VQNEGv8i16 + /* 10044 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 10112 + /* 10049 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10052 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10067 + /* 10057 */ MCD_OPC_CheckPredicate, + 27, + 209, + 35, + 0, // Skip to: 19231 + /* 10062 */ MCD_OPC_Decode, + 246, + 15, + 229, + 1, // Opcode: VABShd + /* 10067 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10082 + /* 10072 */ MCD_OPC_CheckPredicate, + 27, + 194, + 35, + 0, // Skip to: 19231 + /* 10077 */ MCD_OPC_Decode, + 247, + 15, + 230, + 1, // Opcode: VABShq + /* 10082 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10097 + /* 10087 */ MCD_OPC_CheckPredicate, + 27, + 179, + 35, + 0, // Skip to: 19231 + /* 10092 */ MCD_OPC_Decode, + 191, + 23, + 229, + 1, // Opcode: VNEGhd + /* 10097 */ MCD_OPC_FilterValue, + 3, + 169, + 35, + 0, // Skip to: 19231 + /* 10102 */ MCD_OPC_CheckPredicate, + 27, + 164, + 35, + 0, // Skip to: 19231 + /* 10107 */ MCD_OPC_Decode, + 192, + 23, + 230, + 1, // Opcode: VNEGhq + /* 10112 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 10134 + /* 10117 */ MCD_OPC_CheckPredicate, + 30, + 149, + 35, + 0, // Skip to: 19231 + /* 10122 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 142, + 35, + 0, // Skip to: 19231 + /* 10129 */ MCD_OPC_Decode, + 133, + 18, + 237, + 1, // Opcode: VCVTh2f + /* 10134 */ MCD_OPC_FilterValue, + 7, + 63, + 0, + 0, // Skip to: 10202 + /* 10139 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10142 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10157 + /* 10147 */ MCD_OPC_CheckPredicate, + 27, + 119, + 35, + 0, // Skip to: 19231 + /* 10152 */ MCD_OPC_Decode, + 134, + 18, + 229, + 1, // Opcode: VCVTh2sd + /* 10157 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10172 + /* 10162 */ MCD_OPC_CheckPredicate, + 27, + 104, + 35, + 0, // Skip to: 19231 + /* 10167 */ MCD_OPC_Decode, + 135, + 18, + 230, + 1, // Opcode: VCVTh2sq + /* 10172 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10187 + /* 10177 */ MCD_OPC_CheckPredicate, + 27, + 89, + 35, + 0, // Skip to: 19231 + /* 10182 */ MCD_OPC_Decode, + 136, + 18, + 229, + 1, // Opcode: VCVTh2ud + /* 10187 */ MCD_OPC_FilterValue, + 3, + 79, + 35, + 0, // Skip to: 19231 + /* 10192 */ MCD_OPC_CheckPredicate, + 27, + 74, + 35, + 0, // Skip to: 19231 + /* 10197 */ MCD_OPC_Decode, + 137, + 18, + 230, + 1, // Opcode: VCVTh2uq + /* 10202 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 10270 + /* 10207 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10210 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10225 + /* 10215 */ MCD_OPC_CheckPredicate, + 26, + 51, + 35, + 0, // Skip to: 19231 + /* 10220 */ MCD_OPC_Decode, + 134, + 24, + 229, + 1, // Opcode: VQABSv2i32 + /* 10225 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10240 + /* 10230 */ MCD_OPC_CheckPredicate, + 26, + 36, + 35, + 0, // Skip to: 19231 + /* 10235 */ MCD_OPC_Decode, + 136, + 24, + 230, + 1, // Opcode: VQABSv4i32 + /* 10240 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10255 + /* 10245 */ MCD_OPC_CheckPredicate, + 26, + 21, + 35, + 0, // Skip to: 19231 + /* 10250 */ MCD_OPC_Decode, + 185, + 24, + 229, + 1, // Opcode: VQNEGv2i32 + /* 10255 */ MCD_OPC_FilterValue, + 3, + 11, + 35, + 0, // Skip to: 19231 + /* 10260 */ MCD_OPC_CheckPredicate, + 26, + 6, + 35, + 0, // Skip to: 19231 + /* 10265 */ MCD_OPC_Decode, + 187, + 24, + 230, + 1, // Opcode: VQNEGv4i32 + /* 10270 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 10338 + /* 10275 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10278 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10293 + /* 10283 */ MCD_OPC_CheckPredicate, + 26, + 239, + 34, + 0, // Skip to: 19231 + /* 10288 */ MCD_OPC_Decode, + 244, + 15, + 229, + 1, // Opcode: VABSfd + /* 10293 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10308 + /* 10298 */ MCD_OPC_CheckPredicate, + 26, + 224, + 34, + 0, // Skip to: 19231 + /* 10303 */ MCD_OPC_Decode, + 245, + 15, + 230, + 1, // Opcode: VABSfq + /* 10308 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10323 + /* 10313 */ MCD_OPC_CheckPredicate, + 26, + 209, + 34, + 0, // Skip to: 19231 + /* 10318 */ MCD_OPC_Decode, + 190, + 23, + 229, + 1, // Opcode: VNEGfd + /* 10323 */ MCD_OPC_FilterValue, + 3, + 199, + 34, + 0, // Skip to: 19231 + /* 10328 */ MCD_OPC_CheckPredicate, + 26, + 194, + 34, + 0, // Skip to: 19231 + /* 10333 */ MCD_OPC_Decode, + 189, + 23, + 230, + 1, // Opcode: VNEGf32q + /* 10338 */ MCD_OPC_FilterValue, + 11, + 184, + 34, + 0, // Skip to: 19231 + /* 10343 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10346 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10361 + /* 10351 */ MCD_OPC_CheckPredicate, + 26, + 171, + 34, + 0, // Skip to: 19231 + /* 10356 */ MCD_OPC_Decode, + 253, + 17, + 229, + 1, // Opcode: VCVTf2sd + /* 10361 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10376 + /* 10366 */ MCD_OPC_CheckPredicate, + 26, + 156, + 34, + 0, // Skip to: 19231 + /* 10371 */ MCD_OPC_Decode, + 254, + 17, + 230, + 1, // Opcode: VCVTf2sq + /* 10376 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10391 + /* 10381 */ MCD_OPC_CheckPredicate, + 26, + 141, + 34, + 0, // Skip to: 19231 + /* 10386 */ MCD_OPC_Decode, + 255, + 17, + 229, + 1, // Opcode: VCVTf2ud + /* 10391 */ MCD_OPC_FilterValue, + 3, + 131, + 34, + 0, // Skip to: 19231 + /* 10396 */ MCD_OPC_CheckPredicate, + 26, + 126, + 34, + 0, // Skip to: 19231 + /* 10401 */ MCD_OPC_Decode, + 128, + 18, + 230, + 1, // Opcode: VCVTf2uq + /* 10406 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 10444 + /* 10411 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10414 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10429 + /* 10419 */ MCD_OPC_CheckPredicate, + 26, + 103, + 34, + 0, // Skip to: 19231 + /* 10424 */ MCD_OPC_Decode, + 248, + 29, + 238, + 1, // Opcode: VTBL1 + /* 10429 */ MCD_OPC_FilterValue, + 1, + 93, + 34, + 0, // Skip to: 19231 + /* 10434 */ MCD_OPC_CheckPredicate, + 26, + 88, + 34, + 0, // Skip to: 19231 + /* 10439 */ MCD_OPC_Decode, + 254, + 29, + 238, + 1, // Opcode: VTBX1 + /* 10444 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 10482 + /* 10449 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10452 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10467 + /* 10457 */ MCD_OPC_CheckPredicate, + 26, + 65, + 34, + 0, // Skip to: 19231 + /* 10462 */ MCD_OPC_Decode, + 249, + 29, + 238, + 1, // Opcode: VTBL2 + /* 10467 */ MCD_OPC_FilterValue, + 1, + 55, + 34, + 0, // Skip to: 19231 + /* 10472 */ MCD_OPC_CheckPredicate, + 26, + 50, + 34, + 0, // Skip to: 19231 + /* 10477 */ MCD_OPC_Decode, + 255, + 29, + 238, + 1, // Opcode: VTBX2 + /* 10482 */ MCD_OPC_FilterValue, + 10, + 33, + 0, + 0, // Skip to: 10520 + /* 10487 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10490 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10505 + /* 10495 */ MCD_OPC_CheckPredicate, + 26, + 27, + 34, + 0, // Skip to: 19231 + /* 10500 */ MCD_OPC_Decode, + 250, + 29, + 238, + 1, // Opcode: VTBL3 + /* 10505 */ MCD_OPC_FilterValue, + 1, + 17, + 34, + 0, // Skip to: 19231 + /* 10510 */ MCD_OPC_CheckPredicate, + 26, + 12, + 34, + 0, // Skip to: 19231 + /* 10515 */ MCD_OPC_Decode, + 128, + 30, + 238, + 1, // Opcode: VTBX3 + /* 10520 */ MCD_OPC_FilterValue, + 11, + 33, + 0, + 0, // Skip to: 10558 + /* 10525 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10528 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10543 + /* 10533 */ MCD_OPC_CheckPredicate, + 26, + 245, + 33, + 0, // Skip to: 19231 + /* 10538 */ MCD_OPC_Decode, + 252, + 29, + 238, + 1, // Opcode: VTBL4 + /* 10543 */ MCD_OPC_FilterValue, + 1, + 235, + 33, + 0, // Skip to: 19231 + /* 10548 */ MCD_OPC_CheckPredicate, + 26, + 230, + 33, + 0, // Skip to: 19231 + /* 10553 */ MCD_OPC_Decode, + 130, + 30, + 238, + 1, // Opcode: VTBX4 + /* 10558 */ MCD_OPC_FilterValue, + 12, + 220, + 33, + 0, // Skip to: 19231 + /* 10563 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 10566 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 10634 + /* 10571 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10574 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 10619 + /* 10579 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 10582 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 10604 + /* 10587 */ MCD_OPC_CheckPredicate, + 26, + 191, + 33, + 0, // Skip to: 19231 + /* 10592 */ MCD_OPC_CheckField, + 18, + 1, + 1, + 184, + 33, + 0, // Skip to: 19231 + /* 10599 */ MCD_OPC_Decode, + 169, + 18, + 239, + 1, // Opcode: VDUPLN32d + /* 10604 */ MCD_OPC_FilterValue, + 1, + 174, + 33, + 0, // Skip to: 19231 + /* 10609 */ MCD_OPC_CheckPredicate, + 26, + 169, + 33, + 0, // Skip to: 19231 + /* 10614 */ MCD_OPC_Decode, + 167, + 18, + 240, + 1, // Opcode: VDUPLN16d + /* 10619 */ MCD_OPC_FilterValue, + 1, + 159, + 33, + 0, // Skip to: 19231 + /* 10624 */ MCD_OPC_CheckPredicate, + 26, + 154, + 33, + 0, // Skip to: 19231 + /* 10629 */ MCD_OPC_Decode, + 171, + 18, + 241, + 1, // Opcode: VDUPLN8d + /* 10634 */ MCD_OPC_FilterValue, + 1, + 144, + 33, + 0, // Skip to: 19231 + /* 10639 */ MCD_OPC_ExtractField, + 16, + 1, // Inst{16} ... + /* 10642 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 10687 + /* 10647 */ MCD_OPC_ExtractField, + 17, + 1, // Inst{17} ... + /* 10650 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 10672 + /* 10655 */ MCD_OPC_CheckPredicate, + 26, + 123, + 33, + 0, // Skip to: 19231 + /* 10660 */ MCD_OPC_CheckField, + 18, + 1, + 1, + 116, + 33, + 0, // Skip to: 19231 + /* 10667 */ MCD_OPC_Decode, + 170, + 18, + 242, + 1, // Opcode: VDUPLN32q + /* 10672 */ MCD_OPC_FilterValue, + 1, + 106, + 33, + 0, // Skip to: 19231 + /* 10677 */ MCD_OPC_CheckPredicate, + 26, + 101, + 33, + 0, // Skip to: 19231 + /* 10682 */ MCD_OPC_Decode, + 168, + 18, + 243, + 1, // Opcode: VDUPLN16q + /* 10687 */ MCD_OPC_FilterValue, + 1, + 91, + 33, + 0, // Skip to: 19231 + /* 10692 */ MCD_OPC_CheckPredicate, + 26, + 86, + 33, + 0, // Skip to: 19231 + /* 10697 */ MCD_OPC_Decode, + 172, + 18, + 244, + 1, // Opcode: VDUPLN8q + /* 10702 */ MCD_OPC_FilterValue, + 1, + 76, + 33, + 0, // Skip to: 19231 + /* 10707 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 10710 */ MCD_OPC_FilterValue, + 0, + 120, + 17, + 0, // Skip to: 15187 + /* 10715 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 10718 */ MCD_OPC_FilterValue, + 0, + 108, + 8, + 0, // Skip to: 12879 + /* 10723 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 10726 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 10894 + /* 10731 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 10734 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 10774 + /* 10739 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10742 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10758 + /* 10748 */ MCD_OPC_CheckPredicate, + 26, + 30, + 33, + 0, // Skip to: 19231 + /* 10753 */ MCD_OPC_Decode, + 146, + 24, + 200, + 1, // Opcode: VQADDsv8i8 + /* 10758 */ MCD_OPC_FilterValue, + 243, + 1, + 19, + 33, + 0, // Skip to: 19231 + /* 10764 */ MCD_OPC_CheckPredicate, + 26, + 14, + 33, + 0, // Skip to: 19231 + /* 10769 */ MCD_OPC_Decode, + 154, + 24, + 200, + 1, // Opcode: VQADDuv8i8 + /* 10774 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 10814 + /* 10779 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10782 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10798 + /* 10788 */ MCD_OPC_CheckPredicate, + 26, + 246, + 32, + 0, // Skip to: 19231 + /* 10793 */ MCD_OPC_Decode, + 143, + 24, + 200, + 1, // Opcode: VQADDsv4i16 + /* 10798 */ MCD_OPC_FilterValue, + 243, + 1, + 235, + 32, + 0, // Skip to: 19231 + /* 10804 */ MCD_OPC_CheckPredicate, + 26, + 230, + 32, + 0, // Skip to: 19231 + /* 10809 */ MCD_OPC_Decode, + 151, + 24, + 200, + 1, // Opcode: VQADDuv4i16 + /* 10814 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 10854 + /* 10819 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10822 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10838 + /* 10828 */ MCD_OPC_CheckPredicate, + 26, + 206, + 32, + 0, // Skip to: 19231 + /* 10833 */ MCD_OPC_Decode, + 141, + 24, + 200, + 1, // Opcode: VQADDsv2i32 + /* 10838 */ MCD_OPC_FilterValue, + 243, + 1, + 195, + 32, + 0, // Skip to: 19231 + /* 10844 */ MCD_OPC_CheckPredicate, + 26, + 190, + 32, + 0, // Skip to: 19231 + /* 10849 */ MCD_OPC_Decode, + 149, + 24, + 200, + 1, // Opcode: VQADDuv2i32 + /* 10854 */ MCD_OPC_FilterValue, + 3, + 180, + 32, + 0, // Skip to: 19231 + /* 10859 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10862 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10878 + /* 10868 */ MCD_OPC_CheckPredicate, + 26, + 166, + 32, + 0, // Skip to: 19231 + /* 10873 */ MCD_OPC_Decode, + 140, + 24, + 200, + 1, // Opcode: VQADDsv1i64 + /* 10878 */ MCD_OPC_FilterValue, + 243, + 1, + 155, + 32, + 0, // Skip to: 19231 + /* 10884 */ MCD_OPC_CheckPredicate, + 26, + 150, + 32, + 0, // Skip to: 19231 + /* 10889 */ MCD_OPC_Decode, + 148, + 24, + 200, + 1, // Opcode: VQADDuv1i64 + /* 10894 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 11062 + /* 10899 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 10902 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 10942 + /* 10907 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10910 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10926 + /* 10916 */ MCD_OPC_CheckPredicate, + 26, + 118, + 32, + 0, // Skip to: 19231 + /* 10921 */ MCD_OPC_Decode, + 164, + 16, + 200, + 1, // Opcode: VANDd + /* 10926 */ MCD_OPC_FilterValue, + 243, + 1, + 107, + 32, + 0, // Skip to: 19231 + /* 10932 */ MCD_OPC_CheckPredicate, + 26, + 102, + 32, + 0, // Skip to: 19231 + /* 10937 */ MCD_OPC_Decode, + 173, + 18, + 200, + 1, // Opcode: VEORd + /* 10942 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 10982 + /* 10947 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10950 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 10966 + /* 10956 */ MCD_OPC_CheckPredicate, + 26, + 78, + 32, + 0, // Skip to: 19231 + /* 10961 */ MCD_OPC_Decode, + 170, + 16, + 200, + 1, // Opcode: VBICd + /* 10966 */ MCD_OPC_FilterValue, + 243, + 1, + 67, + 32, + 0, // Skip to: 19231 + /* 10972 */ MCD_OPC_CheckPredicate, + 26, + 62, + 32, + 0, // Skip to: 19231 + /* 10977 */ MCD_OPC_Decode, + 180, + 16, + 208, + 1, // Opcode: VBSLd + /* 10982 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 11022 + /* 10987 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 10990 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11006 + /* 10996 */ MCD_OPC_CheckPredicate, + 26, + 38, + 32, + 0, // Skip to: 19231 + /* 11001 */ MCD_OPC_Decode, + 210, + 23, + 200, + 1, // Opcode: VORRd + /* 11006 */ MCD_OPC_FilterValue, + 243, + 1, + 27, + 32, + 0, // Skip to: 19231 + /* 11012 */ MCD_OPC_CheckPredicate, + 26, + 22, + 32, + 0, // Skip to: 19231 + /* 11017 */ MCD_OPC_Decode, + 178, + 16, + 208, + 1, // Opcode: VBITd + /* 11022 */ MCD_OPC_FilterValue, + 3, + 12, + 32, + 0, // Skip to: 19231 + /* 11027 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11030 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11046 + /* 11036 */ MCD_OPC_CheckPredicate, + 26, + 254, + 31, + 0, // Skip to: 19231 + /* 11041 */ MCD_OPC_Decode, + 208, + 23, + 200, + 1, // Opcode: VORNd + /* 11046 */ MCD_OPC_FilterValue, + 243, + 1, + 243, + 31, + 0, // Skip to: 19231 + /* 11052 */ MCD_OPC_CheckPredicate, + 26, + 238, + 31, + 0, // Skip to: 19231 + /* 11057 */ MCD_OPC_Decode, + 176, + 16, + 208, + 1, // Opcode: VBIFd + /* 11062 */ MCD_OPC_FilterValue, + 2, + 163, + 0, + 0, // Skip to: 11230 + /* 11067 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11070 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11110 + /* 11075 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11078 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11094 + /* 11084 */ MCD_OPC_CheckPredicate, + 26, + 206, + 31, + 0, // Skip to: 19231 + /* 11089 */ MCD_OPC_Decode, + 167, + 25, + 200, + 1, // Opcode: VQSUBsv8i8 + /* 11094 */ MCD_OPC_FilterValue, + 243, + 1, + 195, + 31, + 0, // Skip to: 19231 + /* 11100 */ MCD_OPC_CheckPredicate, + 26, + 190, + 31, + 0, // Skip to: 19231 + /* 11105 */ MCD_OPC_Decode, + 175, + 25, + 200, + 1, // Opcode: VQSUBuv8i8 + /* 11110 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11150 + /* 11115 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11118 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11134 + /* 11124 */ MCD_OPC_CheckPredicate, + 26, + 166, + 31, + 0, // Skip to: 19231 + /* 11129 */ MCD_OPC_Decode, + 164, + 25, + 200, + 1, // Opcode: VQSUBsv4i16 + /* 11134 */ MCD_OPC_FilterValue, + 243, + 1, + 155, + 31, + 0, // Skip to: 19231 + /* 11140 */ MCD_OPC_CheckPredicate, + 26, + 150, + 31, + 0, // Skip to: 19231 + /* 11145 */ MCD_OPC_Decode, + 172, + 25, + 200, + 1, // Opcode: VQSUBuv4i16 + /* 11150 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 11190 + /* 11155 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11158 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11174 + /* 11164 */ MCD_OPC_CheckPredicate, + 26, + 126, + 31, + 0, // Skip to: 19231 + /* 11169 */ MCD_OPC_Decode, + 162, + 25, + 200, + 1, // Opcode: VQSUBsv2i32 + /* 11174 */ MCD_OPC_FilterValue, + 243, + 1, + 115, + 31, + 0, // Skip to: 19231 + /* 11180 */ MCD_OPC_CheckPredicate, + 26, + 110, + 31, + 0, // Skip to: 19231 + /* 11185 */ MCD_OPC_Decode, + 170, + 25, + 200, + 1, // Opcode: VQSUBuv2i32 + /* 11190 */ MCD_OPC_FilterValue, + 3, + 100, + 31, + 0, // Skip to: 19231 + /* 11195 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11198 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11214 + /* 11204 */ MCD_OPC_CheckPredicate, + 26, + 86, + 31, + 0, // Skip to: 19231 + /* 11209 */ MCD_OPC_Decode, + 161, + 25, + 200, + 1, // Opcode: VQSUBsv1i64 + /* 11214 */ MCD_OPC_FilterValue, + 243, + 1, + 75, + 31, + 0, // Skip to: 19231 + /* 11220 */ MCD_OPC_CheckPredicate, + 26, + 70, + 31, + 0, // Skip to: 19231 + /* 11225 */ MCD_OPC_Decode, + 169, + 25, + 200, + 1, // Opcode: VQSUBuv1i64 + /* 11230 */ MCD_OPC_FilterValue, + 3, + 123, + 0, + 0, // Skip to: 11358 + /* 11235 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11238 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11278 + /* 11243 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11246 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11262 + /* 11252 */ MCD_OPC_CheckPredicate, + 26, + 38, + 31, + 0, // Skip to: 19231 + /* 11257 */ MCD_OPC_Decode, + 217, + 16, + 200, + 1, // Opcode: VCGEsv8i8 + /* 11262 */ MCD_OPC_FilterValue, + 243, + 1, + 27, + 31, + 0, // Skip to: 19231 + /* 11268 */ MCD_OPC_CheckPredicate, + 26, + 22, + 31, + 0, // Skip to: 19231 + /* 11273 */ MCD_OPC_Decode, + 223, + 16, + 200, + 1, // Opcode: VCGEuv8i8 + /* 11278 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11318 + /* 11283 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11286 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11302 + /* 11292 */ MCD_OPC_CheckPredicate, + 26, + 254, + 30, + 0, // Skip to: 19231 + /* 11297 */ MCD_OPC_Decode, + 214, + 16, + 200, + 1, // Opcode: VCGEsv4i16 + /* 11302 */ MCD_OPC_FilterValue, + 243, + 1, + 243, + 30, + 0, // Skip to: 19231 + /* 11308 */ MCD_OPC_CheckPredicate, + 26, + 238, + 30, + 0, // Skip to: 19231 + /* 11313 */ MCD_OPC_Decode, + 220, + 16, + 200, + 1, // Opcode: VCGEuv4i16 + /* 11318 */ MCD_OPC_FilterValue, + 2, + 228, + 30, + 0, // Skip to: 19231 + /* 11323 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11326 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11342 + /* 11332 */ MCD_OPC_CheckPredicate, + 26, + 214, + 30, + 0, // Skip to: 19231 + /* 11337 */ MCD_OPC_Decode, + 213, + 16, + 200, + 1, // Opcode: VCGEsv2i32 + /* 11342 */ MCD_OPC_FilterValue, + 243, + 1, + 203, + 30, + 0, // Skip to: 19231 + /* 11348 */ MCD_OPC_CheckPredicate, + 26, + 198, + 30, + 0, // Skip to: 19231 + /* 11353 */ MCD_OPC_Decode, + 219, + 16, + 200, + 1, // Opcode: VCGEuv2i32 + /* 11358 */ MCD_OPC_FilterValue, + 4, + 163, + 0, + 0, // Skip to: 11526 + /* 11363 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11366 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11406 + /* 11371 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11374 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11390 + /* 11380 */ MCD_OPC_CheckPredicate, + 26, + 166, + 30, + 0, // Skip to: 19231 + /* 11385 */ MCD_OPC_Decode, + 134, + 25, + 204, + 1, // Opcode: VQSHLsv8i8 + /* 11390 */ MCD_OPC_FilterValue, + 243, + 1, + 155, + 30, + 0, // Skip to: 19231 + /* 11396 */ MCD_OPC_CheckPredicate, + 26, + 150, + 30, + 0, // Skip to: 19231 + /* 11401 */ MCD_OPC_Decode, + 150, + 25, + 204, + 1, // Opcode: VQSHLuv8i8 + /* 11406 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11446 + /* 11411 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11414 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11430 + /* 11420 */ MCD_OPC_CheckPredicate, + 26, + 126, + 30, + 0, // Skip to: 19231 + /* 11425 */ MCD_OPC_Decode, + 131, + 25, + 204, + 1, // Opcode: VQSHLsv4i16 + /* 11430 */ MCD_OPC_FilterValue, + 243, + 1, + 115, + 30, + 0, // Skip to: 19231 + /* 11436 */ MCD_OPC_CheckPredicate, + 26, + 110, + 30, + 0, // Skip to: 19231 + /* 11441 */ MCD_OPC_Decode, + 147, + 25, + 204, + 1, // Opcode: VQSHLuv4i16 + /* 11446 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 11486 + /* 11451 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11454 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11470 + /* 11460 */ MCD_OPC_CheckPredicate, + 26, + 86, + 30, + 0, // Skip to: 19231 + /* 11465 */ MCD_OPC_Decode, + 129, + 25, + 204, + 1, // Opcode: VQSHLsv2i32 + /* 11470 */ MCD_OPC_FilterValue, + 243, + 1, + 75, + 30, + 0, // Skip to: 19231 + /* 11476 */ MCD_OPC_CheckPredicate, + 26, + 70, + 30, + 0, // Skip to: 19231 + /* 11481 */ MCD_OPC_Decode, + 145, + 25, + 204, + 1, // Opcode: VQSHLuv2i32 + /* 11486 */ MCD_OPC_FilterValue, + 3, + 60, + 30, + 0, // Skip to: 19231 + /* 11491 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11494 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11510 + /* 11500 */ MCD_OPC_CheckPredicate, + 26, + 46, + 30, + 0, // Skip to: 19231 + /* 11505 */ MCD_OPC_Decode, + 128, + 25, + 204, + 1, // Opcode: VQSHLsv1i64 + /* 11510 */ MCD_OPC_FilterValue, + 243, + 1, + 35, + 30, + 0, // Skip to: 19231 + /* 11516 */ MCD_OPC_CheckPredicate, + 26, + 30, + 30, + 0, // Skip to: 19231 + /* 11521 */ MCD_OPC_Decode, + 144, + 25, + 204, + 1, // Opcode: VQSHLuv1i64 + /* 11526 */ MCD_OPC_FilterValue, + 5, + 163, + 0, + 0, // Skip to: 11694 + /* 11531 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11534 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11574 + /* 11539 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11542 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11558 + /* 11548 */ MCD_OPC_CheckPredicate, + 26, + 254, + 29, + 0, // Skip to: 19231 + /* 11553 */ MCD_OPC_Decode, + 221, + 24, + 204, + 1, // Opcode: VQRSHLsv8i8 + /* 11558 */ MCD_OPC_FilterValue, + 243, + 1, + 243, + 29, + 0, // Skip to: 19231 + /* 11564 */ MCD_OPC_CheckPredicate, + 26, + 238, + 29, + 0, // Skip to: 19231 + /* 11569 */ MCD_OPC_Decode, + 229, + 24, + 204, + 1, // Opcode: VQRSHLuv8i8 + /* 11574 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11614 + /* 11579 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11582 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11598 + /* 11588 */ MCD_OPC_CheckPredicate, + 26, + 214, + 29, + 0, // Skip to: 19231 + /* 11593 */ MCD_OPC_Decode, + 218, + 24, + 204, + 1, // Opcode: VQRSHLsv4i16 + /* 11598 */ MCD_OPC_FilterValue, + 243, + 1, + 203, + 29, + 0, // Skip to: 19231 + /* 11604 */ MCD_OPC_CheckPredicate, + 26, + 198, + 29, + 0, // Skip to: 19231 + /* 11609 */ MCD_OPC_Decode, + 226, + 24, + 204, + 1, // Opcode: VQRSHLuv4i16 + /* 11614 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 11654 + /* 11619 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11622 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11638 + /* 11628 */ MCD_OPC_CheckPredicate, + 26, + 174, + 29, + 0, // Skip to: 19231 + /* 11633 */ MCD_OPC_Decode, + 216, + 24, + 204, + 1, // Opcode: VQRSHLsv2i32 + /* 11638 */ MCD_OPC_FilterValue, + 243, + 1, + 163, + 29, + 0, // Skip to: 19231 + /* 11644 */ MCD_OPC_CheckPredicate, + 26, + 158, + 29, + 0, // Skip to: 19231 + /* 11649 */ MCD_OPC_Decode, + 224, + 24, + 204, + 1, // Opcode: VQRSHLuv2i32 + /* 11654 */ MCD_OPC_FilterValue, + 3, + 148, + 29, + 0, // Skip to: 19231 + /* 11659 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11662 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11678 + /* 11668 */ MCD_OPC_CheckPredicate, + 26, + 134, + 29, + 0, // Skip to: 19231 + /* 11673 */ MCD_OPC_Decode, + 215, + 24, + 204, + 1, // Opcode: VQRSHLsv1i64 + /* 11678 */ MCD_OPC_FilterValue, + 243, + 1, + 123, + 29, + 0, // Skip to: 19231 + /* 11684 */ MCD_OPC_CheckPredicate, + 26, + 118, + 29, + 0, // Skip to: 19231 + /* 11689 */ MCD_OPC_Decode, + 223, + 24, + 204, + 1, // Opcode: VQRSHLuv1i64 + /* 11694 */ MCD_OPC_FilterValue, + 6, + 123, + 0, + 0, // Skip to: 11822 + /* 11699 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11702 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11742 + /* 11707 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11710 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11726 + /* 11716 */ MCD_OPC_CheckPredicate, + 26, + 86, + 29, + 0, // Skip to: 19231 + /* 11721 */ MCD_OPC_Decode, + 150, + 22, + 200, + 1, // Opcode: VMINsv8i8 + /* 11726 */ MCD_OPC_FilterValue, + 243, + 1, + 75, + 29, + 0, // Skip to: 19231 + /* 11732 */ MCD_OPC_CheckPredicate, + 26, + 70, + 29, + 0, // Skip to: 19231 + /* 11737 */ MCD_OPC_Decode, + 156, + 22, + 200, + 1, // Opcode: VMINuv8i8 + /* 11742 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11782 + /* 11747 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11750 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11766 + /* 11756 */ MCD_OPC_CheckPredicate, + 26, + 46, + 29, + 0, // Skip to: 19231 + /* 11761 */ MCD_OPC_Decode, + 147, + 22, + 200, + 1, // Opcode: VMINsv4i16 + /* 11766 */ MCD_OPC_FilterValue, + 243, + 1, + 35, + 29, + 0, // Skip to: 19231 + /* 11772 */ MCD_OPC_CheckPredicate, + 26, + 30, + 29, + 0, // Skip to: 19231 + /* 11777 */ MCD_OPC_Decode, + 153, + 22, + 200, + 1, // Opcode: VMINuv4i16 + /* 11782 */ MCD_OPC_FilterValue, + 2, + 20, + 29, + 0, // Skip to: 19231 + /* 11787 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11790 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11806 + /* 11796 */ MCD_OPC_CheckPredicate, + 26, + 6, + 29, + 0, // Skip to: 19231 + /* 11801 */ MCD_OPC_Decode, + 146, + 22, + 200, + 1, // Opcode: VMINsv2i32 + /* 11806 */ MCD_OPC_FilterValue, + 243, + 1, + 251, + 28, + 0, // Skip to: 19231 + /* 11812 */ MCD_OPC_CheckPredicate, + 26, + 246, + 28, + 0, // Skip to: 19231 + /* 11817 */ MCD_OPC_Decode, + 152, + 22, + 200, + 1, // Opcode: VMINuv2i32 + /* 11822 */ MCD_OPC_FilterValue, + 7, + 123, + 0, + 0, // Skip to: 11950 + /* 11827 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11830 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11870 + /* 11835 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11838 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11854 + /* 11844 */ MCD_OPC_CheckPredicate, + 26, + 214, + 28, + 0, // Skip to: 19231 + /* 11849 */ MCD_OPC_Decode, + 212, + 15, + 208, + 1, // Opcode: VABAsv8i8 + /* 11854 */ MCD_OPC_FilterValue, + 243, + 1, + 203, + 28, + 0, // Skip to: 19231 + /* 11860 */ MCD_OPC_CheckPredicate, + 26, + 198, + 28, + 0, // Skip to: 19231 + /* 11865 */ MCD_OPC_Decode, + 218, + 15, + 208, + 1, // Opcode: VABAuv8i8 + /* 11870 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 11910 + /* 11875 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11878 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11894 + /* 11884 */ MCD_OPC_CheckPredicate, + 26, + 174, + 28, + 0, // Skip to: 19231 + /* 11889 */ MCD_OPC_Decode, + 209, + 15, + 208, + 1, // Opcode: VABAsv4i16 + /* 11894 */ MCD_OPC_FilterValue, + 243, + 1, + 163, + 28, + 0, // Skip to: 19231 + /* 11900 */ MCD_OPC_CheckPredicate, + 26, + 158, + 28, + 0, // Skip to: 19231 + /* 11905 */ MCD_OPC_Decode, + 215, + 15, + 208, + 1, // Opcode: VABAuv4i16 + /* 11910 */ MCD_OPC_FilterValue, + 2, + 148, + 28, + 0, // Skip to: 19231 + /* 11915 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11918 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11934 + /* 11924 */ MCD_OPC_CheckPredicate, + 26, + 134, + 28, + 0, // Skip to: 19231 + /* 11929 */ MCD_OPC_Decode, + 208, + 15, + 208, + 1, // Opcode: VABAsv2i32 + /* 11934 */ MCD_OPC_FilterValue, + 243, + 1, + 123, + 28, + 0, // Skip to: 19231 + /* 11940 */ MCD_OPC_CheckPredicate, + 26, + 118, + 28, + 0, // Skip to: 19231 + /* 11945 */ MCD_OPC_Decode, + 214, + 15, + 208, + 1, // Opcode: VABAuv2i32 + /* 11950 */ MCD_OPC_FilterValue, + 8, + 123, + 0, + 0, // Skip to: 12078 + /* 11955 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11958 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 11998 + /* 11963 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11966 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 11982 + /* 11972 */ MCD_OPC_CheckPredicate, + 26, + 86, + 28, + 0, // Skip to: 19231 + /* 11977 */ MCD_OPC_Decode, + 167, + 30, + 200, + 1, // Opcode: VTSTv8i8 + /* 11982 */ MCD_OPC_FilterValue, + 243, + 1, + 75, + 28, + 0, // Skip to: 19231 + /* 11988 */ MCD_OPC_CheckPredicate, + 26, + 70, + 28, + 0, // Skip to: 19231 + /* 11993 */ MCD_OPC_Decode, + 197, + 16, + 200, + 1, // Opcode: VCEQv8i8 + /* 11998 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12038 + /* 12003 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12006 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12022 + /* 12012 */ MCD_OPC_CheckPredicate, + 26, + 46, + 28, + 0, // Skip to: 19231 + /* 12017 */ MCD_OPC_Decode, + 164, + 30, + 200, + 1, // Opcode: VTSTv4i16 + /* 12022 */ MCD_OPC_FilterValue, + 243, + 1, + 35, + 28, + 0, // Skip to: 19231 + /* 12028 */ MCD_OPC_CheckPredicate, + 26, + 30, + 28, + 0, // Skip to: 19231 + /* 12033 */ MCD_OPC_Decode, + 194, + 16, + 200, + 1, // Opcode: VCEQv4i16 + /* 12038 */ MCD_OPC_FilterValue, + 2, + 20, + 28, + 0, // Skip to: 19231 + /* 12043 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12046 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12062 + /* 12052 */ MCD_OPC_CheckPredicate, + 26, + 6, + 28, + 0, // Skip to: 19231 + /* 12057 */ MCD_OPC_Decode, + 163, + 30, + 200, + 1, // Opcode: VTSTv2i32 + /* 12062 */ MCD_OPC_FilterValue, + 243, + 1, + 251, + 27, + 0, // Skip to: 19231 + /* 12068 */ MCD_OPC_CheckPredicate, + 26, + 246, + 27, + 0, // Skip to: 19231 + /* 12073 */ MCD_OPC_Decode, + 193, + 16, + 200, + 1, // Opcode: VCEQv2i32 + /* 12078 */ MCD_OPC_FilterValue, + 9, + 89, + 0, + 0, // Skip to: 12172 + /* 12083 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12086 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 12126 + /* 12091 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12094 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12110 + /* 12100 */ MCD_OPC_CheckPredicate, + 26, + 214, + 27, + 0, // Skip to: 19231 + /* 12105 */ MCD_OPC_Decode, + 179, + 23, + 200, + 1, // Opcode: VMULv8i8 + /* 12110 */ MCD_OPC_FilterValue, + 243, + 1, + 203, + 27, + 0, // Skip to: 19231 + /* 12116 */ MCD_OPC_CheckPredicate, + 26, + 198, + 27, + 0, // Skip to: 19231 + /* 12121 */ MCD_OPC_Decode, + 164, + 23, + 200, + 1, // Opcode: VMULpd + /* 12126 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 12149 + /* 12131 */ MCD_OPC_CheckPredicate, + 26, + 183, + 27, + 0, // Skip to: 19231 + /* 12136 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 175, + 27, + 0, // Skip to: 19231 + /* 12144 */ MCD_OPC_Decode, + 176, + 23, + 200, + 1, // Opcode: VMULv4i16 + /* 12149 */ MCD_OPC_FilterValue, + 2, + 165, + 27, + 0, // Skip to: 19231 + /* 12154 */ MCD_OPC_CheckPredicate, + 26, + 160, + 27, + 0, // Skip to: 19231 + /* 12159 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 152, + 27, + 0, // Skip to: 19231 + /* 12167 */ MCD_OPC_Decode, + 175, + 23, + 200, + 1, // Opcode: VMULv2i32 + /* 12172 */ MCD_OPC_FilterValue, + 10, + 123, + 0, + 0, // Skip to: 12300 + /* 12177 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12180 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 12220 + /* 12185 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12188 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12204 + /* 12194 */ MCD_OPC_CheckPredicate, + 26, + 120, + 27, + 0, // Skip to: 19231 + /* 12199 */ MCD_OPC_Decode, + 129, + 24, + 200, + 1, // Opcode: VPMINs8 + /* 12204 */ MCD_OPC_FilterValue, + 243, + 1, + 109, + 27, + 0, // Skip to: 19231 + /* 12210 */ MCD_OPC_CheckPredicate, + 26, + 104, + 27, + 0, // Skip to: 19231 + /* 12215 */ MCD_OPC_Decode, + 132, + 24, + 200, + 1, // Opcode: VPMINu8 + /* 12220 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12260 + /* 12225 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12228 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12244 + /* 12234 */ MCD_OPC_CheckPredicate, + 26, + 80, + 27, + 0, // Skip to: 19231 + /* 12239 */ MCD_OPC_Decode, + 255, + 23, + 200, + 1, // Opcode: VPMINs16 + /* 12244 */ MCD_OPC_FilterValue, + 243, + 1, + 69, + 27, + 0, // Skip to: 19231 + /* 12250 */ MCD_OPC_CheckPredicate, + 26, + 64, + 27, + 0, // Skip to: 19231 + /* 12255 */ MCD_OPC_Decode, + 130, + 24, + 200, + 1, // Opcode: VPMINu16 + /* 12260 */ MCD_OPC_FilterValue, + 2, + 54, + 27, + 0, // Skip to: 19231 + /* 12265 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12268 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12284 + /* 12274 */ MCD_OPC_CheckPredicate, + 26, + 40, + 27, + 0, // Skip to: 19231 + /* 12279 */ MCD_OPC_Decode, + 128, + 24, + 200, + 1, // Opcode: VPMINs32 + /* 12284 */ MCD_OPC_FilterValue, + 243, + 1, + 29, + 27, + 0, // Skip to: 19231 + /* 12290 */ MCD_OPC_CheckPredicate, + 26, + 24, + 27, + 0, // Skip to: 19231 + /* 12295 */ MCD_OPC_Decode, + 131, + 24, + 200, + 1, // Opcode: VPMINu32 + /* 12300 */ MCD_OPC_FilterValue, + 11, + 106, + 0, + 0, // Skip to: 12411 + /* 12305 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12308 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 12331 + /* 12313 */ MCD_OPC_CheckPredicate, + 26, + 1, + 27, + 0, // Skip to: 19231 + /* 12318 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 249, + 26, + 0, // Skip to: 19231 + /* 12326 */ MCD_OPC_Decode, + 244, + 23, + 200, + 1, // Opcode: VPADDi8 + /* 12331 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12371 + /* 12336 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12339 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12355 + /* 12345 */ MCD_OPC_CheckPredicate, + 26, + 225, + 26, + 0, // Skip to: 19231 + /* 12350 */ MCD_OPC_Decode, + 242, + 23, + 200, + 1, // Opcode: VPADDi16 + /* 12355 */ MCD_OPC_FilterValue, + 243, + 1, + 214, + 26, + 0, // Skip to: 19231 + /* 12361 */ MCD_OPC_CheckPredicate, + 28, + 209, + 26, + 0, // Skip to: 19231 + /* 12366 */ MCD_OPC_Decode, + 195, + 24, + 208, + 1, // Opcode: VQRDMLAHv4i16 + /* 12371 */ MCD_OPC_FilterValue, + 2, + 199, + 26, + 0, // Skip to: 19231 + /* 12376 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12379 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12395 + /* 12385 */ MCD_OPC_CheckPredicate, + 26, + 185, + 26, + 0, // Skip to: 19231 + /* 12390 */ MCD_OPC_Decode, + 243, + 23, + 200, + 1, // Opcode: VPADDi32 + /* 12395 */ MCD_OPC_FilterValue, + 243, + 1, + 174, + 26, + 0, // Skip to: 19231 + /* 12401 */ MCD_OPC_CheckPredicate, + 28, + 169, + 26, + 0, // Skip to: 19231 + /* 12406 */ MCD_OPC_Decode, + 194, + 24, + 208, + 1, // Opcode: VQRDMLAHv2i32 + /* 12411 */ MCD_OPC_FilterValue, + 12, + 129, + 0, + 0, // Skip to: 12545 + /* 12416 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12419 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 12442 + /* 12424 */ MCD_OPC_CheckPredicate, + 32, + 146, + 26, + 0, // Skip to: 19231 + /* 12429 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 138, + 26, + 0, // Skip to: 19231 + /* 12437 */ MCD_OPC_Decode, + 189, + 18, + 208, + 1, // Opcode: VFMAfd + /* 12442 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12482 + /* 12447 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12450 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12466 + /* 12456 */ MCD_OPC_CheckPredicate, + 27, + 114, + 26, + 0, // Skip to: 19231 + /* 12461 */ MCD_OPC_Decode, + 191, + 18, + 208, + 1, // Opcode: VFMAhd + /* 12466 */ MCD_OPC_FilterValue, + 243, + 1, + 103, + 26, + 0, // Skip to: 19231 + /* 12472 */ MCD_OPC_CheckPredicate, + 28, + 98, + 26, + 0, // Skip to: 19231 + /* 12477 */ MCD_OPC_Decode, + 203, + 24, + 208, + 1, // Opcode: VQRDMLSHv4i16 + /* 12482 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 12522 + /* 12487 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12490 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12506 + /* 12496 */ MCD_OPC_CheckPredicate, + 32, + 74, + 26, + 0, // Skip to: 19231 + /* 12501 */ MCD_OPC_Decode, + 200, + 18, + 208, + 1, // Opcode: VFMSfd + /* 12506 */ MCD_OPC_FilterValue, + 243, + 1, + 63, + 26, + 0, // Skip to: 19231 + /* 12512 */ MCD_OPC_CheckPredicate, + 28, + 58, + 26, + 0, // Skip to: 19231 + /* 12517 */ MCD_OPC_Decode, + 202, + 24, + 208, + 1, // Opcode: VQRDMLSHv2i32 + /* 12522 */ MCD_OPC_FilterValue, + 3, + 48, + 26, + 0, // Skip to: 19231 + /* 12527 */ MCD_OPC_CheckPredicate, + 27, + 43, + 26, + 0, // Skip to: 19231 + /* 12532 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 35, + 26, + 0, // Skip to: 19231 + /* 12540 */ MCD_OPC_Decode, + 202, + 18, + 208, + 1, // Opcode: VFMShd + /* 12545 */ MCD_OPC_FilterValue, + 13, + 129, + 0, + 0, // Skip to: 12679 + /* 12550 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12553 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 12593 + /* 12558 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12561 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12577 + /* 12567 */ MCD_OPC_CheckPredicate, + 26, + 3, + 26, + 0, // Skip to: 19231 + /* 12572 */ MCD_OPC_Decode, + 170, + 22, + 208, + 1, // Opcode: VMLAfd + /* 12577 */ MCD_OPC_FilterValue, + 243, + 1, + 248, + 25, + 0, // Skip to: 19231 + /* 12583 */ MCD_OPC_CheckPredicate, + 26, + 243, + 25, + 0, // Skip to: 19231 + /* 12588 */ MCD_OPC_Decode, + 160, + 23, + 200, + 1, // Opcode: VMULfd + /* 12593 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 12633 + /* 12598 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12601 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 12617 + /* 12607 */ MCD_OPC_CheckPredicate, + 27, + 219, + 25, + 0, // Skip to: 19231 + /* 12612 */ MCD_OPC_Decode, + 172, + 22, + 208, + 1, // Opcode: VMLAhd + /* 12617 */ MCD_OPC_FilterValue, + 243, + 1, + 208, + 25, + 0, // Skip to: 19231 + /* 12623 */ MCD_OPC_CheckPredicate, + 27, + 203, + 25, + 0, // Skip to: 19231 + /* 12628 */ MCD_OPC_Decode, + 162, + 23, + 200, + 1, // Opcode: VMULhd + /* 12633 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 12656 + /* 12638 */ MCD_OPC_CheckPredicate, + 26, + 188, + 25, + 0, // Skip to: 19231 + /* 12643 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 180, + 25, + 0, // Skip to: 19231 + /* 12651 */ MCD_OPC_Decode, + 201, + 22, + 208, + 1, // Opcode: VMLSfd + /* 12656 */ MCD_OPC_FilterValue, + 3, + 170, + 25, + 0, // Skip to: 19231 + /* 12661 */ MCD_OPC_CheckPredicate, + 27, + 165, + 25, + 0, // Skip to: 19231 + /* 12666 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 157, + 25, + 0, // Skip to: 19231 + /* 12674 */ MCD_OPC_Decode, + 203, + 22, + 208, + 1, // Opcode: VMLShd + /* 12679 */ MCD_OPC_FilterValue, + 14, + 95, + 0, + 0, // Skip to: 12779 + /* 12684 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12687 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 12710 + /* 12692 */ MCD_OPC_CheckPredicate, + 26, + 134, + 25, + 0, // Skip to: 19231 + /* 12697 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 126, + 25, + 0, // Skip to: 19231 + /* 12705 */ MCD_OPC_Decode, + 254, + 15, + 200, + 1, // Opcode: VACGEfd + /* 12710 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 12733 + /* 12715 */ MCD_OPC_CheckPredicate, + 27, + 111, + 25, + 0, // Skip to: 19231 + /* 12720 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 103, + 25, + 0, // Skip to: 19231 + /* 12728 */ MCD_OPC_Decode, + 128, + 16, + 200, + 1, // Opcode: VACGEhd + /* 12733 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 12756 + /* 12738 */ MCD_OPC_CheckPredicate, + 26, + 88, + 25, + 0, // Skip to: 19231 + /* 12743 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 80, + 25, + 0, // Skip to: 19231 + /* 12751 */ MCD_OPC_Decode, + 130, + 16, + 200, + 1, // Opcode: VACGTfd + /* 12756 */ MCD_OPC_FilterValue, + 3, + 70, + 25, + 0, // Skip to: 19231 + /* 12761 */ MCD_OPC_CheckPredicate, + 27, + 65, + 25, + 0, // Skip to: 19231 + /* 12766 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 57, + 25, + 0, // Skip to: 19231 + /* 12774 */ MCD_OPC_Decode, + 132, + 16, + 200, + 1, // Opcode: VACGThd + /* 12779 */ MCD_OPC_FilterValue, + 15, + 47, + 25, + 0, // Skip to: 19231 + /* 12784 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 12787 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 12810 + /* 12792 */ MCD_OPC_CheckPredicate, + 26, + 34, + 25, + 0, // Skip to: 19231 + /* 12797 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 26, + 25, + 0, // Skip to: 19231 + /* 12805 */ MCD_OPC_Decode, + 185, + 25, + 200, + 1, // Opcode: VRECPSfd + /* 12810 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 12833 + /* 12815 */ MCD_OPC_CheckPredicate, + 27, + 11, + 25, + 0, // Skip to: 19231 + /* 12820 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 3, + 25, + 0, // Skip to: 19231 + /* 12828 */ MCD_OPC_Decode, + 187, + 25, + 200, + 1, // Opcode: VRECPShd + /* 12833 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 12856 + /* 12838 */ MCD_OPC_CheckPredicate, + 26, + 244, + 24, + 0, // Skip to: 19231 + /* 12843 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 236, + 24, + 0, // Skip to: 19231 + /* 12851 */ MCD_OPC_Decode, + 171, + 26, + 200, + 1, // Opcode: VRSQRTSfd + /* 12856 */ MCD_OPC_FilterValue, + 3, + 226, + 24, + 0, // Skip to: 19231 + /* 12861 */ MCD_OPC_CheckPredicate, + 27, + 221, + 24, + 0, // Skip to: 19231 + /* 12866 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 213, + 24, + 0, // Skip to: 19231 + /* 12874 */ MCD_OPC_Decode, + 173, + 26, + 200, + 1, // Opcode: VRSQRTShd + /* 12879 */ MCD_OPC_FilterValue, + 1, + 203, + 24, + 0, // Skip to: 19231 + /* 12884 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 12887 */ MCD_OPC_FilterValue, + 0, + 209, + 7, + 0, // Skip to: 14893 + /* 12892 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 12895 */ MCD_OPC_FilterValue, + 121, + 187, + 24, + 0, // Skip to: 19231 + /* 12900 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 12903 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 13047 + /* 12908 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 12911 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13009 + /* 12916 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 12919 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 12971 + /* 12924 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 12927 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 12949 + /* 12932 */ MCD_OPC_CheckPredicate, + 26, + 231, + 6, + 0, // Skip to: 14704 + /* 12937 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 224, + 6, + 0, // Skip to: 14704 + /* 12944 */ MCD_OPC_Decode, + 130, + 27, + 245, + 1, // Opcode: VSHRsv8i8 + /* 12949 */ MCD_OPC_FilterValue, + 1, + 214, + 6, + 0, // Skip to: 14704 + /* 12954 */ MCD_OPC_CheckPredicate, + 26, + 209, + 6, + 0, // Skip to: 14704 + /* 12959 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 202, + 6, + 0, // Skip to: 14704 + /* 12966 */ MCD_OPC_Decode, + 138, + 27, + 245, + 1, // Opcode: VSHRuv8i8 + /* 12971 */ MCD_OPC_FilterValue, + 1, + 192, + 6, + 0, // Skip to: 14704 + /* 12976 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 12979 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 12994 + /* 12984 */ MCD_OPC_CheckPredicate, + 26, + 179, + 6, + 0, // Skip to: 14704 + /* 12989 */ MCD_OPC_Decode, + 255, + 26, + 246, + 1, // Opcode: VSHRsv4i16 + /* 12994 */ MCD_OPC_FilterValue, + 1, + 169, + 6, + 0, // Skip to: 14704 + /* 12999 */ MCD_OPC_CheckPredicate, + 26, + 164, + 6, + 0, // Skip to: 14704 + /* 13004 */ MCD_OPC_Decode, + 135, + 27, + 246, + 1, // Opcode: VSHRuv4i16 + /* 13009 */ MCD_OPC_FilterValue, + 1, + 154, + 6, + 0, // Skip to: 14704 + /* 13014 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13017 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13032 + /* 13022 */ MCD_OPC_CheckPredicate, + 26, + 141, + 6, + 0, // Skip to: 14704 + /* 13027 */ MCD_OPC_Decode, + 253, + 26, + 247, + 1, // Opcode: VSHRsv2i32 + /* 13032 */ MCD_OPC_FilterValue, + 1, + 131, + 6, + 0, // Skip to: 14704 + /* 13037 */ MCD_OPC_CheckPredicate, + 26, + 126, + 6, + 0, // Skip to: 14704 + /* 13042 */ MCD_OPC_Decode, + 133, + 27, + 247, + 1, // Opcode: VSHRuv2i32 + /* 13047 */ MCD_OPC_FilterValue, + 1, + 139, + 0, + 0, // Skip to: 13191 + /* 13052 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13055 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13153 + /* 13060 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13063 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13115 + /* 13068 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13071 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13093 + /* 13076 */ MCD_OPC_CheckPredicate, + 26, + 87, + 6, + 0, // Skip to: 14704 + /* 13081 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 80, + 6, + 0, // Skip to: 14704 + /* 13088 */ MCD_OPC_Decode, + 167, + 27, + 248, + 1, // Opcode: VSRAsv8i8 + /* 13093 */ MCD_OPC_FilterValue, + 1, + 70, + 6, + 0, // Skip to: 14704 + /* 13098 */ MCD_OPC_CheckPredicate, + 26, + 65, + 6, + 0, // Skip to: 14704 + /* 13103 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 58, + 6, + 0, // Skip to: 14704 + /* 13110 */ MCD_OPC_Decode, + 175, + 27, + 248, + 1, // Opcode: VSRAuv8i8 + /* 13115 */ MCD_OPC_FilterValue, + 1, + 48, + 6, + 0, // Skip to: 14704 + /* 13120 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13123 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13138 + /* 13128 */ MCD_OPC_CheckPredicate, + 26, + 35, + 6, + 0, // Skip to: 14704 + /* 13133 */ MCD_OPC_Decode, + 164, + 27, + 249, + 1, // Opcode: VSRAsv4i16 + /* 13138 */ MCD_OPC_FilterValue, + 1, + 25, + 6, + 0, // Skip to: 14704 + /* 13143 */ MCD_OPC_CheckPredicate, + 26, + 20, + 6, + 0, // Skip to: 14704 + /* 13148 */ MCD_OPC_Decode, + 172, + 27, + 249, + 1, // Opcode: VSRAuv4i16 + /* 13153 */ MCD_OPC_FilterValue, + 1, + 10, + 6, + 0, // Skip to: 14704 + /* 13158 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13161 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13176 + /* 13166 */ MCD_OPC_CheckPredicate, + 26, + 253, + 5, + 0, // Skip to: 14704 + /* 13171 */ MCD_OPC_Decode, + 162, + 27, + 250, + 1, // Opcode: VSRAsv2i32 + /* 13176 */ MCD_OPC_FilterValue, + 1, + 243, + 5, + 0, // Skip to: 14704 + /* 13181 */ MCD_OPC_CheckPredicate, + 26, + 238, + 5, + 0, // Skip to: 14704 + /* 13186 */ MCD_OPC_Decode, + 170, + 27, + 250, + 1, // Opcode: VSRAuv2i32 + /* 13191 */ MCD_OPC_FilterValue, + 2, + 139, + 0, + 0, // Skip to: 13335 + /* 13196 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13199 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13297 + /* 13204 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13207 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13259 + /* 13212 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13215 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13237 + /* 13220 */ MCD_OPC_CheckPredicate, + 26, + 199, + 5, + 0, // Skip to: 14704 + /* 13225 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 192, + 5, + 0, // Skip to: 14704 + /* 13232 */ MCD_OPC_Decode, + 156, + 26, + 245, + 1, // Opcode: VRSHRsv8i8 + /* 13237 */ MCD_OPC_FilterValue, + 1, + 182, + 5, + 0, // Skip to: 14704 + /* 13242 */ MCD_OPC_CheckPredicate, + 26, + 177, + 5, + 0, // Skip to: 14704 + /* 13247 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 170, + 5, + 0, // Skip to: 14704 + /* 13254 */ MCD_OPC_Decode, + 164, + 26, + 245, + 1, // Opcode: VRSHRuv8i8 + /* 13259 */ MCD_OPC_FilterValue, + 1, + 160, + 5, + 0, // Skip to: 14704 + /* 13264 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13267 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13282 + /* 13272 */ MCD_OPC_CheckPredicate, + 26, + 147, + 5, + 0, // Skip to: 14704 + /* 13277 */ MCD_OPC_Decode, + 153, + 26, + 246, + 1, // Opcode: VRSHRsv4i16 + /* 13282 */ MCD_OPC_FilterValue, + 1, + 137, + 5, + 0, // Skip to: 14704 + /* 13287 */ MCD_OPC_CheckPredicate, + 26, + 132, + 5, + 0, // Skip to: 14704 + /* 13292 */ MCD_OPC_Decode, + 161, + 26, + 246, + 1, // Opcode: VRSHRuv4i16 + /* 13297 */ MCD_OPC_FilterValue, + 1, + 122, + 5, + 0, // Skip to: 14704 + /* 13302 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13305 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13320 + /* 13310 */ MCD_OPC_CheckPredicate, + 26, + 109, + 5, + 0, // Skip to: 14704 + /* 13315 */ MCD_OPC_Decode, + 151, + 26, + 247, + 1, // Opcode: VRSHRsv2i32 + /* 13320 */ MCD_OPC_FilterValue, + 1, + 99, + 5, + 0, // Skip to: 14704 + /* 13325 */ MCD_OPC_CheckPredicate, + 26, + 94, + 5, + 0, // Skip to: 14704 + /* 13330 */ MCD_OPC_Decode, + 159, + 26, + 247, + 1, // Opcode: VRSHRuv2i32 + /* 13335 */ MCD_OPC_FilterValue, + 3, + 139, + 0, + 0, // Skip to: 13479 + /* 13340 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13343 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13441 + /* 13348 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13351 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13403 + /* 13356 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13359 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13381 + /* 13364 */ MCD_OPC_CheckPredicate, + 26, + 55, + 5, + 0, // Skip to: 14704 + /* 13369 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 48, + 5, + 0, // Skip to: 14704 + /* 13376 */ MCD_OPC_Decode, + 182, + 26, + 248, + 1, // Opcode: VRSRAsv8i8 + /* 13381 */ MCD_OPC_FilterValue, + 1, + 38, + 5, + 0, // Skip to: 14704 + /* 13386 */ MCD_OPC_CheckPredicate, + 26, + 33, + 5, + 0, // Skip to: 14704 + /* 13391 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 26, + 5, + 0, // Skip to: 14704 + /* 13398 */ MCD_OPC_Decode, + 190, + 26, + 248, + 1, // Opcode: VRSRAuv8i8 + /* 13403 */ MCD_OPC_FilterValue, + 1, + 16, + 5, + 0, // Skip to: 14704 + /* 13408 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13411 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13426 + /* 13416 */ MCD_OPC_CheckPredicate, + 26, + 3, + 5, + 0, // Skip to: 14704 + /* 13421 */ MCD_OPC_Decode, + 179, + 26, + 249, + 1, // Opcode: VRSRAsv4i16 + /* 13426 */ MCD_OPC_FilterValue, + 1, + 249, + 4, + 0, // Skip to: 14704 + /* 13431 */ MCD_OPC_CheckPredicate, + 26, + 244, + 4, + 0, // Skip to: 14704 + /* 13436 */ MCD_OPC_Decode, + 187, + 26, + 249, + 1, // Opcode: VRSRAuv4i16 + /* 13441 */ MCD_OPC_FilterValue, + 1, + 234, + 4, + 0, // Skip to: 14704 + /* 13446 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13449 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13464 + /* 13454 */ MCD_OPC_CheckPredicate, + 26, + 221, + 4, + 0, // Skip to: 14704 + /* 13459 */ MCD_OPC_Decode, + 177, + 26, + 250, + 1, // Opcode: VRSRAsv2i32 + /* 13464 */ MCD_OPC_FilterValue, + 1, + 211, + 4, + 0, // Skip to: 14704 + /* 13469 */ MCD_OPC_CheckPredicate, + 26, + 206, + 4, + 0, // Skip to: 14704 + /* 13474 */ MCD_OPC_Decode, + 185, + 26, + 250, + 1, // Opcode: VRSRAuv2i32 + /* 13479 */ MCD_OPC_FilterValue, + 4, + 84, + 0, + 0, // Skip to: 13568 + /* 13484 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13487 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 13546 + /* 13492 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13495 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 13524 + /* 13500 */ MCD_OPC_CheckPredicate, + 26, + 175, + 4, + 0, // Skip to: 14704 + /* 13505 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 168, + 4, + 0, // Skip to: 14704 + /* 13512 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 161, + 4, + 0, // Skip to: 14704 + /* 13519 */ MCD_OPC_Decode, + 183, + 27, + 248, + 1, // Opcode: VSRIv8i8 + /* 13524 */ MCD_OPC_FilterValue, + 1, + 151, + 4, + 0, // Skip to: 14704 + /* 13529 */ MCD_OPC_CheckPredicate, + 26, + 146, + 4, + 0, // Skip to: 14704 + /* 13534 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 139, + 4, + 0, // Skip to: 14704 + /* 13541 */ MCD_OPC_Decode, + 180, + 27, + 249, + 1, // Opcode: VSRIv4i16 + /* 13546 */ MCD_OPC_FilterValue, + 1, + 129, + 4, + 0, // Skip to: 14704 + /* 13551 */ MCD_OPC_CheckPredicate, + 26, + 124, + 4, + 0, // Skip to: 14704 + /* 13556 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 117, + 4, + 0, // Skip to: 14704 + /* 13563 */ MCD_OPC_Decode, + 178, + 27, + 250, + 1, // Opcode: VSRIv2i32 + /* 13568 */ MCD_OPC_FilterValue, + 5, + 139, + 0, + 0, // Skip to: 13712 + /* 13573 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13576 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13674 + /* 13581 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13584 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13636 + /* 13589 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13592 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13614 + /* 13597 */ MCD_OPC_CheckPredicate, + 26, + 78, + 4, + 0, // Skip to: 14704 + /* 13602 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 71, + 4, + 0, // Skip to: 14704 + /* 13609 */ MCD_OPC_Decode, + 231, + 26, + 251, + 1, // Opcode: VSHLiv8i8 + /* 13614 */ MCD_OPC_FilterValue, + 1, + 61, + 4, + 0, // Skip to: 14704 + /* 13619 */ MCD_OPC_CheckPredicate, + 26, + 56, + 4, + 0, // Skip to: 14704 + /* 13624 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 49, + 4, + 0, // Skip to: 14704 + /* 13631 */ MCD_OPC_Decode, + 152, + 27, + 252, + 1, // Opcode: VSLIv8i8 + /* 13636 */ MCD_OPC_FilterValue, + 1, + 39, + 4, + 0, // Skip to: 14704 + /* 13641 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13644 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13659 + /* 13649 */ MCD_OPC_CheckPredicate, + 26, + 26, + 4, + 0, // Skip to: 14704 + /* 13654 */ MCD_OPC_Decode, + 228, + 26, + 253, + 1, // Opcode: VSHLiv4i16 + /* 13659 */ MCD_OPC_FilterValue, + 1, + 16, + 4, + 0, // Skip to: 14704 + /* 13664 */ MCD_OPC_CheckPredicate, + 26, + 11, + 4, + 0, // Skip to: 14704 + /* 13669 */ MCD_OPC_Decode, + 149, + 27, + 254, + 1, // Opcode: VSLIv4i16 + /* 13674 */ MCD_OPC_FilterValue, + 1, + 1, + 4, + 0, // Skip to: 14704 + /* 13679 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13682 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13697 + /* 13687 */ MCD_OPC_CheckPredicate, + 26, + 244, + 3, + 0, // Skip to: 14704 + /* 13692 */ MCD_OPC_Decode, + 226, + 26, + 255, + 1, // Opcode: VSHLiv2i32 + /* 13697 */ MCD_OPC_FilterValue, + 1, + 234, + 3, + 0, // Skip to: 14704 + /* 13702 */ MCD_OPC_CheckPredicate, + 26, + 229, + 3, + 0, // Skip to: 14704 + /* 13707 */ MCD_OPC_Decode, + 147, + 27, + 128, + 2, // Opcode: VSLIv2i32 + /* 13712 */ MCD_OPC_FilterValue, + 6, + 84, + 0, + 0, // Skip to: 13801 + /* 13717 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13720 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 13779 + /* 13725 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13728 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 13757 + /* 13733 */ MCD_OPC_CheckPredicate, + 26, + 198, + 3, + 0, // Skip to: 14704 + /* 13738 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 191, + 3, + 0, // Skip to: 14704 + /* 13745 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 184, + 3, + 0, // Skip to: 14704 + /* 13752 */ MCD_OPC_Decode, + 254, + 24, + 251, + 1, // Opcode: VQSHLsuv8i8 + /* 13757 */ MCD_OPC_FilterValue, + 1, + 174, + 3, + 0, // Skip to: 14704 + /* 13762 */ MCD_OPC_CheckPredicate, + 26, + 169, + 3, + 0, // Skip to: 14704 + /* 13767 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 162, + 3, + 0, // Skip to: 14704 + /* 13774 */ MCD_OPC_Decode, + 251, + 24, + 253, + 1, // Opcode: VQSHLsuv4i16 + /* 13779 */ MCD_OPC_FilterValue, + 1, + 152, + 3, + 0, // Skip to: 14704 + /* 13784 */ MCD_OPC_CheckPredicate, + 26, + 147, + 3, + 0, // Skip to: 14704 + /* 13789 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 140, + 3, + 0, // Skip to: 14704 + /* 13796 */ MCD_OPC_Decode, + 249, + 24, + 255, + 1, // Opcode: VQSHLsuv2i32 + /* 13801 */ MCD_OPC_FilterValue, + 7, + 139, + 0, + 0, // Skip to: 13945 + /* 13806 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13809 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 13907 + /* 13814 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13817 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 13869 + /* 13822 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13825 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13847 + /* 13830 */ MCD_OPC_CheckPredicate, + 26, + 101, + 3, + 0, // Skip to: 14704 + /* 13835 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 94, + 3, + 0, // Skip to: 14704 + /* 13842 */ MCD_OPC_Decode, + 246, + 24, + 251, + 1, // Opcode: VQSHLsiv8i8 + /* 13847 */ MCD_OPC_FilterValue, + 1, + 84, + 3, + 0, // Skip to: 14704 + /* 13852 */ MCD_OPC_CheckPredicate, + 26, + 79, + 3, + 0, // Skip to: 14704 + /* 13857 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 72, + 3, + 0, // Skip to: 14704 + /* 13864 */ MCD_OPC_Decode, + 142, + 25, + 251, + 1, // Opcode: VQSHLuiv8i8 + /* 13869 */ MCD_OPC_FilterValue, + 1, + 62, + 3, + 0, // Skip to: 14704 + /* 13874 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13877 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13892 + /* 13882 */ MCD_OPC_CheckPredicate, + 26, + 49, + 3, + 0, // Skip to: 14704 + /* 13887 */ MCD_OPC_Decode, + 243, + 24, + 253, + 1, // Opcode: VQSHLsiv4i16 + /* 13892 */ MCD_OPC_FilterValue, + 1, + 39, + 3, + 0, // Skip to: 14704 + /* 13897 */ MCD_OPC_CheckPredicate, + 26, + 34, + 3, + 0, // Skip to: 14704 + /* 13902 */ MCD_OPC_Decode, + 139, + 25, + 253, + 1, // Opcode: VQSHLuiv4i16 + /* 13907 */ MCD_OPC_FilterValue, + 1, + 24, + 3, + 0, // Skip to: 14704 + /* 13912 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13915 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13930 + /* 13920 */ MCD_OPC_CheckPredicate, + 26, + 11, + 3, + 0, // Skip to: 14704 + /* 13925 */ MCD_OPC_Decode, + 241, + 24, + 255, + 1, // Opcode: VQSHLsiv2i32 + /* 13930 */ MCD_OPC_FilterValue, + 1, + 1, + 3, + 0, // Skip to: 14704 + /* 13935 */ MCD_OPC_CheckPredicate, + 26, + 252, + 2, + 0, // Skip to: 14704 + /* 13940 */ MCD_OPC_Decode, + 137, + 25, + 255, + 1, // Opcode: VQSHLuiv2i32 + /* 13945 */ MCD_OPC_FilterValue, + 8, + 139, + 0, + 0, // Skip to: 14089 + /* 13950 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 13953 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 14051 + /* 13958 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 13961 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 14013 + /* 13966 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 13969 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 13991 + /* 13974 */ MCD_OPC_CheckPredicate, + 26, + 213, + 2, + 0, // Skip to: 14704 + /* 13979 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 206, + 2, + 0, // Skip to: 14704 + /* 13986 */ MCD_OPC_Decode, + 250, + 26, + 129, + 2, // Opcode: VSHRNv8i8 + /* 13991 */ MCD_OPC_FilterValue, + 1, + 196, + 2, + 0, // Skip to: 14704 + /* 13996 */ MCD_OPC_CheckPredicate, + 26, + 191, + 2, + 0, // Skip to: 14704 + /* 14001 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 184, + 2, + 0, // Skip to: 14704 + /* 14008 */ MCD_OPC_Decode, + 159, + 25, + 129, + 2, // Opcode: VQSHRUNv8i8 + /* 14013 */ MCD_OPC_FilterValue, + 1, + 174, + 2, + 0, // Skip to: 14704 + /* 14018 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14021 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14036 + /* 14026 */ MCD_OPC_CheckPredicate, + 26, + 161, + 2, + 0, // Skip to: 14704 + /* 14031 */ MCD_OPC_Decode, + 249, + 26, + 130, + 2, // Opcode: VSHRNv4i16 + /* 14036 */ MCD_OPC_FilterValue, + 1, + 151, + 2, + 0, // Skip to: 14704 + /* 14041 */ MCD_OPC_CheckPredicate, + 26, + 146, + 2, + 0, // Skip to: 14704 + /* 14046 */ MCD_OPC_Decode, + 158, + 25, + 130, + 2, // Opcode: VQSHRUNv4i16 + /* 14051 */ MCD_OPC_FilterValue, + 1, + 136, + 2, + 0, // Skip to: 14704 + /* 14056 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14059 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14074 + /* 14064 */ MCD_OPC_CheckPredicate, + 26, + 123, + 2, + 0, // Skip to: 14704 + /* 14069 */ MCD_OPC_Decode, + 248, + 26, + 131, + 2, // Opcode: VSHRNv2i32 + /* 14074 */ MCD_OPC_FilterValue, + 1, + 113, + 2, + 0, // Skip to: 14704 + /* 14079 */ MCD_OPC_CheckPredicate, + 26, + 108, + 2, + 0, // Skip to: 14704 + /* 14084 */ MCD_OPC_Decode, + 157, + 25, + 131, + 2, // Opcode: VQSHRUNv2i32 + /* 14089 */ MCD_OPC_FilterValue, + 9, + 139, + 0, + 0, // Skip to: 14233 + /* 14094 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 14097 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 14195 + /* 14102 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 14105 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 14157 + /* 14110 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14113 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 14135 + /* 14118 */ MCD_OPC_CheckPredicate, + 26, + 69, + 2, + 0, // Skip to: 14704 + /* 14123 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 62, + 2, + 0, // Skip to: 14704 + /* 14130 */ MCD_OPC_Decode, + 153, + 25, + 129, + 2, // Opcode: VQSHRNsv8i8 + /* 14135 */ MCD_OPC_FilterValue, + 1, + 52, + 2, + 0, // Skip to: 14704 + /* 14140 */ MCD_OPC_CheckPredicate, + 26, + 47, + 2, + 0, // Skip to: 14704 + /* 14145 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 40, + 2, + 0, // Skip to: 14704 + /* 14152 */ MCD_OPC_Decode, + 156, + 25, + 129, + 2, // Opcode: VQSHRNuv8i8 + /* 14157 */ MCD_OPC_FilterValue, + 1, + 30, + 2, + 0, // Skip to: 14704 + /* 14162 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14165 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14180 + /* 14170 */ MCD_OPC_CheckPredicate, + 26, + 17, + 2, + 0, // Skip to: 14704 + /* 14175 */ MCD_OPC_Decode, + 152, + 25, + 130, + 2, // Opcode: VQSHRNsv4i16 + /* 14180 */ MCD_OPC_FilterValue, + 1, + 7, + 2, + 0, // Skip to: 14704 + /* 14185 */ MCD_OPC_CheckPredicate, + 26, + 2, + 2, + 0, // Skip to: 14704 + /* 14190 */ MCD_OPC_Decode, + 155, + 25, + 130, + 2, // Opcode: VQSHRNuv4i16 + /* 14195 */ MCD_OPC_FilterValue, + 1, + 248, + 1, + 0, // Skip to: 14704 + /* 14200 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14203 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14218 + /* 14208 */ MCD_OPC_CheckPredicate, + 26, + 235, + 1, + 0, // Skip to: 14704 + /* 14213 */ MCD_OPC_Decode, + 151, + 25, + 131, + 2, // Opcode: VQSHRNsv2i32 + /* 14218 */ MCD_OPC_FilterValue, + 1, + 225, + 1, + 0, // Skip to: 14704 + /* 14223 */ MCD_OPC_CheckPredicate, + 26, + 220, + 1, + 0, // Skip to: 14704 + /* 14228 */ MCD_OPC_Decode, + 154, + 25, + 131, + 2, // Opcode: VQSHRNuv2i32 + /* 14233 */ MCD_OPC_FilterValue, + 10, + 243, + 0, + 0, // Skip to: 14481 + /* 14238 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 14241 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 14409 + /* 14246 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 14249 */ MCD_OPC_FilterValue, + 0, + 83, + 0, + 0, // Skip to: 14337 + /* 14254 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14257 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 14297 + /* 14262 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 14265 */ MCD_OPC_FilterValue, + 1, + 178, + 1, + 0, // Skip to: 14704 + /* 14270 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14287 + /* 14275 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 14287 + /* 14282 */ MCD_OPC_Decode, + 226, + 22, + 237, + 1, // Opcode: VMOVLsv8i16 + /* 14287 */ MCD_OPC_CheckPredicate, + 26, + 156, + 1, + 0, // Skip to: 14704 + /* 14292 */ MCD_OPC_Decode, + 220, + 26, + 132, + 2, // Opcode: VSHLLsv8i16 + /* 14297 */ MCD_OPC_FilterValue, + 1, + 146, + 1, + 0, // Skip to: 14704 + /* 14302 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 14305 */ MCD_OPC_FilterValue, + 1, + 138, + 1, + 0, // Skip to: 14704 + /* 14310 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14327 + /* 14315 */ MCD_OPC_CheckField, + 16, + 3, + 0, + 5, + 0, + 0, // Skip to: 14327 + /* 14322 */ MCD_OPC_Decode, + 229, + 22, + 237, + 1, // Opcode: VMOVLuv8i16 + /* 14327 */ MCD_OPC_CheckPredicate, + 26, + 116, + 1, + 0, // Skip to: 14704 + /* 14332 */ MCD_OPC_Decode, + 223, + 26, + 132, + 2, // Opcode: VSHLLuv8i16 + /* 14337 */ MCD_OPC_FilterValue, + 1, + 106, + 1, + 0, // Skip to: 14704 + /* 14342 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14345 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 14377 + /* 14350 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14367 + /* 14355 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 14367 + /* 14362 */ MCD_OPC_Decode, + 225, + 22, + 237, + 1, // Opcode: VMOVLsv4i32 + /* 14367 */ MCD_OPC_CheckPredicate, + 26, + 76, + 1, + 0, // Skip to: 14704 + /* 14372 */ MCD_OPC_Decode, + 219, + 26, + 133, + 2, // Opcode: VSHLLsv4i32 + /* 14377 */ MCD_OPC_FilterValue, + 1, + 66, + 1, + 0, // Skip to: 14704 + /* 14382 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14399 + /* 14387 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 14399 + /* 14394 */ MCD_OPC_Decode, + 228, + 22, + 237, + 1, // Opcode: VMOVLuv4i32 + /* 14399 */ MCD_OPC_CheckPredicate, + 26, + 44, + 1, + 0, // Skip to: 14704 + /* 14404 */ MCD_OPC_Decode, + 222, + 26, + 133, + 2, // Opcode: VSHLLuv4i32 + /* 14409 */ MCD_OPC_FilterValue, + 1, + 34, + 1, + 0, // Skip to: 14704 + /* 14414 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14417 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 14449 + /* 14422 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14439 + /* 14427 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 14439 + /* 14434 */ MCD_OPC_Decode, + 224, + 22, + 237, + 1, // Opcode: VMOVLsv2i64 + /* 14439 */ MCD_OPC_CheckPredicate, + 26, + 4, + 1, + 0, // Skip to: 14704 + /* 14444 */ MCD_OPC_Decode, + 218, + 26, + 134, + 2, // Opcode: VSHLLsv2i64 + /* 14449 */ MCD_OPC_FilterValue, + 1, + 250, + 0, + 0, // Skip to: 14704 + /* 14454 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14471 + /* 14459 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 14471 + /* 14466 */ MCD_OPC_Decode, + 227, + 22, + 237, + 1, // Opcode: VMOVLuv2i64 + /* 14471 */ MCD_OPC_CheckPredicate, + 26, + 228, + 0, + 0, // Skip to: 14704 + /* 14476 */ MCD_OPC_Decode, + 221, + 26, + 134, + 2, // Opcode: VSHLLuv2i64 + /* 14481 */ MCD_OPC_FilterValue, + 12, + 33, + 0, + 0, // Skip to: 14519 + /* 14486 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14489 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14504 + /* 14494 */ MCD_OPC_CheckPredicate, + 27, + 205, + 0, + 0, // Skip to: 14704 + /* 14499 */ MCD_OPC_Decode, + 152, + 18, + 135, + 2, // Opcode: VCVTxs2hd + /* 14504 */ MCD_OPC_FilterValue, + 1, + 195, + 0, + 0, // Skip to: 14704 + /* 14509 */ MCD_OPC_CheckPredicate, + 27, + 190, + 0, + 0, // Skip to: 14704 + /* 14514 */ MCD_OPC_Decode, + 156, + 18, + 135, + 2, // Opcode: VCVTxu2hd + /* 14519 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 14557 + /* 14524 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14527 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14542 + /* 14532 */ MCD_OPC_CheckPredicate, + 27, + 167, + 0, + 0, // Skip to: 14704 + /* 14537 */ MCD_OPC_Decode, + 138, + 18, + 135, + 2, // Opcode: VCVTh2xsd + /* 14542 */ MCD_OPC_FilterValue, + 1, + 157, + 0, + 0, // Skip to: 14704 + /* 14547 */ MCD_OPC_CheckPredicate, + 27, + 152, + 0, + 0, // Skip to: 14704 + /* 14552 */ MCD_OPC_Decode, + 140, + 18, + 135, + 2, // Opcode: VCVTh2xud + /* 14557 */ MCD_OPC_FilterValue, + 14, + 80, + 0, + 0, // Skip to: 14642 + /* 14562 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 14565 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 14587 + /* 14570 */ MCD_OPC_CheckPredicate, + 26, + 34, + 0, + 0, // Skip to: 14609 + /* 14575 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 27, + 0, + 0, // Skip to: 14609 + /* 14582 */ MCD_OPC_Decode, + 249, + 22, + 136, + 2, // Opcode: VMOVv8i8 + /* 14587 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 14609 + /* 14592 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14609 + /* 14597 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 5, + 0, + 0, // Skip to: 14609 + /* 14604 */ MCD_OPC_Decode, + 241, + 22, + 136, + 2, // Opcode: VMOVv1i64 + /* 14609 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14612 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14627 + /* 14617 */ MCD_OPC_CheckPredicate, + 26, + 82, + 0, + 0, // Skip to: 14704 + /* 14622 */ MCD_OPC_Decode, + 150, + 18, + 135, + 2, // Opcode: VCVTxs2fd + /* 14627 */ MCD_OPC_FilterValue, + 1, + 72, + 0, + 0, // Skip to: 14704 + /* 14632 */ MCD_OPC_CheckPredicate, + 26, + 67, + 0, + 0, // Skip to: 14704 + /* 14637 */ MCD_OPC_Decode, + 154, + 18, + 135, + 2, // Opcode: VCVTxu2fd + /* 14642 */ MCD_OPC_FilterValue, + 15, + 57, + 0, + 0, // Skip to: 14704 + /* 14647 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 14650 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14665 + /* 14655 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 14680 + /* 14660 */ MCD_OPC_Decode, + 129, + 18, + 135, + 2, // Opcode: VCVTf2xsd + /* 14665 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 14680 + /* 14670 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 14680 + /* 14675 */ MCD_OPC_Decode, + 131, + 18, + 135, + 2, // Opcode: VCVTf2xud + /* 14680 */ MCD_OPC_CheckPredicate, + 26, + 19, + 0, + 0, // Skip to: 14704 + /* 14685 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 12, + 0, + 0, // Skip to: 14704 + /* 14692 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 14704 + /* 14699 */ MCD_OPC_Decode, + 242, + 22, + 136, + 2, // Opcode: VMOVv2f32 + /* 14704 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 14707 */ MCD_OPC_FilterValue, + 0, + 88, + 0, + 0, // Skip to: 14800 + /* 14712 */ MCD_OPC_ExtractField, + 19, + 3, // Inst{21-19} ... + /* 14715 */ MCD_OPC_FilterValue, + 0, + 159, + 17, + 0, // Skip to: 19231 + /* 14720 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 14723 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 14745 + /* 14728 */ MCD_OPC_CheckPredicate, + 26, + 57, + 0, + 0, // Skip to: 14790 + /* 14733 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 14790 + /* 14740 */ MCD_OPC_Decode, + 246, + 22, + 136, + 2, // Opcode: VMOVv4i16 + /* 14745 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 14790 + /* 14750 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 14753 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14768 + /* 14758 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 14790 + /* 14763 */ MCD_OPC_Decode, + 211, + 23, + 136, + 2, // Opcode: VORRiv2i32 + /* 14768 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 14790 + /* 14773 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14790 + /* 14778 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 14790 + /* 14785 */ MCD_OPC_Decode, + 212, + 23, + 136, + 2, // Opcode: VORRiv4i16 + /* 14790 */ MCD_OPC_CheckPredicate, + 26, + 84, + 17, + 0, // Skip to: 19231 + /* 14795 */ MCD_OPC_Decode, + 243, + 22, + 136, + 2, // Opcode: VMOVv2i32 + /* 14800 */ MCD_OPC_FilterValue, + 1, + 74, + 17, + 0, // Skip to: 19231 + /* 14805 */ MCD_OPC_ExtractField, + 19, + 3, // Inst{21-19} ... + /* 14808 */ MCD_OPC_FilterValue, + 0, + 66, + 17, + 0, // Skip to: 19231 + /* 14813 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 14816 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 14838 + /* 14821 */ MCD_OPC_CheckPredicate, + 26, + 57, + 0, + 0, // Skip to: 14883 + /* 14826 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 14883 + /* 14833 */ MCD_OPC_Decode, + 183, + 23, + 136, + 2, // Opcode: VMVNv4i16 + /* 14838 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 14883 + /* 14843 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 14846 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14861 + /* 14851 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 14883 + /* 14856 */ MCD_OPC_Decode, + 171, + 16, + 136, + 2, // Opcode: VBICiv2i32 + /* 14861 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 14883 + /* 14866 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 14883 + /* 14871 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 14883 + /* 14878 */ MCD_OPC_Decode, + 172, + 16, + 136, + 2, // Opcode: VBICiv4i16 + /* 14883 */ MCD_OPC_CheckPredicate, + 26, + 247, + 16, + 0, // Skip to: 19231 + /* 14888 */ MCD_OPC_Decode, + 182, + 23, + 136, + 2, // Opcode: VMVNv2i32 + /* 14893 */ MCD_OPC_FilterValue, + 1, + 237, + 16, + 0, // Skip to: 19231 + /* 14898 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 14901 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 14941 + /* 14906 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 14909 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 14925 + /* 14915 */ MCD_OPC_CheckPredicate, + 26, + 215, + 16, + 0, // Skip to: 19231 + /* 14920 */ MCD_OPC_Decode, + 252, + 26, + 137, + 2, // Opcode: VSHRsv1i64 + /* 14925 */ MCD_OPC_FilterValue, + 243, + 1, + 204, + 16, + 0, // Skip to: 19231 + /* 14931 */ MCD_OPC_CheckPredicate, + 26, + 199, + 16, + 0, // Skip to: 19231 + /* 14936 */ MCD_OPC_Decode, + 132, + 27, + 137, + 2, // Opcode: VSHRuv1i64 + /* 14941 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 14981 + /* 14946 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 14949 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 14965 + /* 14955 */ MCD_OPC_CheckPredicate, + 26, + 175, + 16, + 0, // Skip to: 19231 + /* 14960 */ MCD_OPC_Decode, + 161, + 27, + 138, + 2, // Opcode: VSRAsv1i64 + /* 14965 */ MCD_OPC_FilterValue, + 243, + 1, + 164, + 16, + 0, // Skip to: 19231 + /* 14971 */ MCD_OPC_CheckPredicate, + 26, + 159, + 16, + 0, // Skip to: 19231 + /* 14976 */ MCD_OPC_Decode, + 169, + 27, + 138, + 2, // Opcode: VSRAuv1i64 + /* 14981 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15021 + /* 14986 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 14989 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15005 + /* 14995 */ MCD_OPC_CheckPredicate, + 26, + 135, + 16, + 0, // Skip to: 19231 + /* 15000 */ MCD_OPC_Decode, + 150, + 26, + 137, + 2, // Opcode: VRSHRsv1i64 + /* 15005 */ MCD_OPC_FilterValue, + 243, + 1, + 124, + 16, + 0, // Skip to: 19231 + /* 15011 */ MCD_OPC_CheckPredicate, + 26, + 119, + 16, + 0, // Skip to: 19231 + /* 15016 */ MCD_OPC_Decode, + 158, + 26, + 137, + 2, // Opcode: VRSHRuv1i64 + /* 15021 */ MCD_OPC_FilterValue, + 3, + 35, + 0, + 0, // Skip to: 15061 + /* 15026 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15029 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15045 + /* 15035 */ MCD_OPC_CheckPredicate, + 26, + 95, + 16, + 0, // Skip to: 19231 + /* 15040 */ MCD_OPC_Decode, + 176, + 26, + 138, + 2, // Opcode: VRSRAsv1i64 + /* 15045 */ MCD_OPC_FilterValue, + 243, + 1, + 84, + 16, + 0, // Skip to: 19231 + /* 15051 */ MCD_OPC_CheckPredicate, + 26, + 79, + 16, + 0, // Skip to: 19231 + /* 15056 */ MCD_OPC_Decode, + 184, + 26, + 138, + 2, // Opcode: VRSRAuv1i64 + /* 15061 */ MCD_OPC_FilterValue, + 4, + 18, + 0, + 0, // Skip to: 15084 + /* 15066 */ MCD_OPC_CheckPredicate, + 26, + 64, + 16, + 0, // Skip to: 19231 + /* 15071 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 56, + 16, + 0, // Skip to: 19231 + /* 15079 */ MCD_OPC_Decode, + 177, + 27, + 138, + 2, // Opcode: VSRIv1i64 + /* 15084 */ MCD_OPC_FilterValue, + 5, + 35, + 0, + 0, // Skip to: 15124 + /* 15089 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15092 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15108 + /* 15098 */ MCD_OPC_CheckPredicate, + 26, + 32, + 16, + 0, // Skip to: 19231 + /* 15103 */ MCD_OPC_Decode, + 225, + 26, + 139, + 2, // Opcode: VSHLiv1i64 + /* 15108 */ MCD_OPC_FilterValue, + 243, + 1, + 21, + 16, + 0, // Skip to: 19231 + /* 15114 */ MCD_OPC_CheckPredicate, + 26, + 16, + 16, + 0, // Skip to: 19231 + /* 15119 */ MCD_OPC_Decode, + 146, + 27, + 140, + 2, // Opcode: VSLIv1i64 + /* 15124 */ MCD_OPC_FilterValue, + 6, + 18, + 0, + 0, // Skip to: 15147 + /* 15129 */ MCD_OPC_CheckPredicate, + 26, + 1, + 16, + 0, // Skip to: 19231 + /* 15134 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 249, + 15, + 0, // Skip to: 19231 + /* 15142 */ MCD_OPC_Decode, + 248, + 24, + 139, + 2, // Opcode: VQSHLsuv1i64 + /* 15147 */ MCD_OPC_FilterValue, + 7, + 239, + 15, + 0, // Skip to: 19231 + /* 15152 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15155 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15171 + /* 15161 */ MCD_OPC_CheckPredicate, + 26, + 225, + 15, + 0, // Skip to: 19231 + /* 15166 */ MCD_OPC_Decode, + 240, + 24, + 139, + 2, // Opcode: VQSHLsiv1i64 + /* 15171 */ MCD_OPC_FilterValue, + 243, + 1, + 214, + 15, + 0, // Skip to: 19231 + /* 15177 */ MCD_OPC_CheckPredicate, + 26, + 209, + 15, + 0, // Skip to: 19231 + /* 15182 */ MCD_OPC_Decode, + 136, + 25, + 139, + 2, // Opcode: VQSHLuiv1i64 + /* 15187 */ MCD_OPC_FilterValue, + 1, + 199, + 15, + 0, // Skip to: 19231 + /* 15192 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 15195 */ MCD_OPC_FilterValue, + 0, + 179, + 7, + 0, // Skip to: 17171 + /* 15200 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 15203 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 15371 + /* 15208 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15211 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15251 + /* 15216 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15219 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15235 + /* 15225 */ MCD_OPC_CheckPredicate, + 26, + 161, + 15, + 0, // Skip to: 19231 + /* 15230 */ MCD_OPC_Decode, + 139, + 24, + 201, + 1, // Opcode: VQADDsv16i8 + /* 15235 */ MCD_OPC_FilterValue, + 243, + 1, + 150, + 15, + 0, // Skip to: 19231 + /* 15241 */ MCD_OPC_CheckPredicate, + 26, + 145, + 15, + 0, // Skip to: 19231 + /* 15246 */ MCD_OPC_Decode, + 147, + 24, + 201, + 1, // Opcode: VQADDuv16i8 + /* 15251 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15291 + /* 15256 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15259 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15275 + /* 15265 */ MCD_OPC_CheckPredicate, + 26, + 121, + 15, + 0, // Skip to: 19231 + /* 15270 */ MCD_OPC_Decode, + 145, + 24, + 201, + 1, // Opcode: VQADDsv8i16 + /* 15275 */ MCD_OPC_FilterValue, + 243, + 1, + 110, + 15, + 0, // Skip to: 19231 + /* 15281 */ MCD_OPC_CheckPredicate, + 26, + 105, + 15, + 0, // Skip to: 19231 + /* 15286 */ MCD_OPC_Decode, + 153, + 24, + 201, + 1, // Opcode: VQADDuv8i16 + /* 15291 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15331 + /* 15296 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15299 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15315 + /* 15305 */ MCD_OPC_CheckPredicate, + 26, + 81, + 15, + 0, // Skip to: 19231 + /* 15310 */ MCD_OPC_Decode, + 144, + 24, + 201, + 1, // Opcode: VQADDsv4i32 + /* 15315 */ MCD_OPC_FilterValue, + 243, + 1, + 70, + 15, + 0, // Skip to: 19231 + /* 15321 */ MCD_OPC_CheckPredicate, + 26, + 65, + 15, + 0, // Skip to: 19231 + /* 15326 */ MCD_OPC_Decode, + 152, + 24, + 201, + 1, // Opcode: VQADDuv4i32 + /* 15331 */ MCD_OPC_FilterValue, + 3, + 55, + 15, + 0, // Skip to: 19231 + /* 15336 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15339 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15355 + /* 15345 */ MCD_OPC_CheckPredicate, + 26, + 41, + 15, + 0, // Skip to: 19231 + /* 15350 */ MCD_OPC_Decode, + 142, + 24, + 201, + 1, // Opcode: VQADDsv2i64 + /* 15355 */ MCD_OPC_FilterValue, + 243, + 1, + 30, + 15, + 0, // Skip to: 19231 + /* 15361 */ MCD_OPC_CheckPredicate, + 26, + 25, + 15, + 0, // Skip to: 19231 + /* 15366 */ MCD_OPC_Decode, + 150, + 24, + 201, + 1, // Opcode: VQADDuv2i64 + /* 15371 */ MCD_OPC_FilterValue, + 1, + 163, + 0, + 0, // Skip to: 15539 + /* 15376 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15379 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15419 + /* 15384 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15387 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15403 + /* 15393 */ MCD_OPC_CheckPredicate, + 26, + 249, + 14, + 0, // Skip to: 19231 + /* 15398 */ MCD_OPC_Decode, + 165, + 16, + 201, + 1, // Opcode: VANDq + /* 15403 */ MCD_OPC_FilterValue, + 243, + 1, + 238, + 14, + 0, // Skip to: 19231 + /* 15409 */ MCD_OPC_CheckPredicate, + 26, + 233, + 14, + 0, // Skip to: 19231 + /* 15414 */ MCD_OPC_Decode, + 174, + 18, + 201, + 1, // Opcode: VEORq + /* 15419 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15459 + /* 15424 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15427 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15443 + /* 15433 */ MCD_OPC_CheckPredicate, + 26, + 209, + 14, + 0, // Skip to: 19231 + /* 15438 */ MCD_OPC_Decode, + 175, + 16, + 201, + 1, // Opcode: VBICq + /* 15443 */ MCD_OPC_FilterValue, + 243, + 1, + 198, + 14, + 0, // Skip to: 19231 + /* 15449 */ MCD_OPC_CheckPredicate, + 26, + 193, + 14, + 0, // Skip to: 19231 + /* 15454 */ MCD_OPC_Decode, + 181, + 16, + 209, + 1, // Opcode: VBSLq + /* 15459 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15499 + /* 15464 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15467 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15483 + /* 15473 */ MCD_OPC_CheckPredicate, + 26, + 169, + 14, + 0, // Skip to: 19231 + /* 15478 */ MCD_OPC_Decode, + 215, + 23, + 201, + 1, // Opcode: VORRq + /* 15483 */ MCD_OPC_FilterValue, + 243, + 1, + 158, + 14, + 0, // Skip to: 19231 + /* 15489 */ MCD_OPC_CheckPredicate, + 26, + 153, + 14, + 0, // Skip to: 19231 + /* 15494 */ MCD_OPC_Decode, + 179, + 16, + 209, + 1, // Opcode: VBITq + /* 15499 */ MCD_OPC_FilterValue, + 3, + 143, + 14, + 0, // Skip to: 19231 + /* 15504 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15507 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15523 + /* 15513 */ MCD_OPC_CheckPredicate, + 26, + 129, + 14, + 0, // Skip to: 19231 + /* 15518 */ MCD_OPC_Decode, + 209, + 23, + 201, + 1, // Opcode: VORNq + /* 15523 */ MCD_OPC_FilterValue, + 243, + 1, + 118, + 14, + 0, // Skip to: 19231 + /* 15529 */ MCD_OPC_CheckPredicate, + 26, + 113, + 14, + 0, // Skip to: 19231 + /* 15534 */ MCD_OPC_Decode, + 177, + 16, + 209, + 1, // Opcode: VBIFq + /* 15539 */ MCD_OPC_FilterValue, + 2, + 163, + 0, + 0, // Skip to: 15707 + /* 15544 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15547 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15587 + /* 15552 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15555 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15571 + /* 15561 */ MCD_OPC_CheckPredicate, + 26, + 81, + 14, + 0, // Skip to: 19231 + /* 15566 */ MCD_OPC_Decode, + 160, + 25, + 201, + 1, // Opcode: VQSUBsv16i8 + /* 15571 */ MCD_OPC_FilterValue, + 243, + 1, + 70, + 14, + 0, // Skip to: 19231 + /* 15577 */ MCD_OPC_CheckPredicate, + 26, + 65, + 14, + 0, // Skip to: 19231 + /* 15582 */ MCD_OPC_Decode, + 168, + 25, + 201, + 1, // Opcode: VQSUBuv16i8 + /* 15587 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15627 + /* 15592 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15595 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15611 + /* 15601 */ MCD_OPC_CheckPredicate, + 26, + 41, + 14, + 0, // Skip to: 19231 + /* 15606 */ MCD_OPC_Decode, + 166, + 25, + 201, + 1, // Opcode: VQSUBsv8i16 + /* 15611 */ MCD_OPC_FilterValue, + 243, + 1, + 30, + 14, + 0, // Skip to: 19231 + /* 15617 */ MCD_OPC_CheckPredicate, + 26, + 25, + 14, + 0, // Skip to: 19231 + /* 15622 */ MCD_OPC_Decode, + 174, + 25, + 201, + 1, // Opcode: VQSUBuv8i16 + /* 15627 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15667 + /* 15632 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15635 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15651 + /* 15641 */ MCD_OPC_CheckPredicate, + 26, + 1, + 14, + 0, // Skip to: 19231 + /* 15646 */ MCD_OPC_Decode, + 165, + 25, + 201, + 1, // Opcode: VQSUBsv4i32 + /* 15651 */ MCD_OPC_FilterValue, + 243, + 1, + 246, + 13, + 0, // Skip to: 19231 + /* 15657 */ MCD_OPC_CheckPredicate, + 26, + 241, + 13, + 0, // Skip to: 19231 + /* 15662 */ MCD_OPC_Decode, + 173, + 25, + 201, + 1, // Opcode: VQSUBuv4i32 + /* 15667 */ MCD_OPC_FilterValue, + 3, + 231, + 13, + 0, // Skip to: 19231 + /* 15672 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15675 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15691 + /* 15681 */ MCD_OPC_CheckPredicate, + 26, + 217, + 13, + 0, // Skip to: 19231 + /* 15686 */ MCD_OPC_Decode, + 163, + 25, + 201, + 1, // Opcode: VQSUBsv2i64 + /* 15691 */ MCD_OPC_FilterValue, + 243, + 1, + 206, + 13, + 0, // Skip to: 19231 + /* 15697 */ MCD_OPC_CheckPredicate, + 26, + 201, + 13, + 0, // Skip to: 19231 + /* 15702 */ MCD_OPC_Decode, + 171, + 25, + 201, + 1, // Opcode: VQSUBuv2i64 + /* 15707 */ MCD_OPC_FilterValue, + 3, + 123, + 0, + 0, // Skip to: 15835 + /* 15712 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15715 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15755 + /* 15720 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15723 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15739 + /* 15729 */ MCD_OPC_CheckPredicate, + 26, + 169, + 13, + 0, // Skip to: 19231 + /* 15734 */ MCD_OPC_Decode, + 212, + 16, + 201, + 1, // Opcode: VCGEsv16i8 + /* 15739 */ MCD_OPC_FilterValue, + 243, + 1, + 158, + 13, + 0, // Skip to: 19231 + /* 15745 */ MCD_OPC_CheckPredicate, + 26, + 153, + 13, + 0, // Skip to: 19231 + /* 15750 */ MCD_OPC_Decode, + 218, + 16, + 201, + 1, // Opcode: VCGEuv16i8 + /* 15755 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15795 + /* 15760 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15763 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15779 + /* 15769 */ MCD_OPC_CheckPredicate, + 26, + 129, + 13, + 0, // Skip to: 19231 + /* 15774 */ MCD_OPC_Decode, + 216, + 16, + 201, + 1, // Opcode: VCGEsv8i16 + /* 15779 */ MCD_OPC_FilterValue, + 243, + 1, + 118, + 13, + 0, // Skip to: 19231 + /* 15785 */ MCD_OPC_CheckPredicate, + 26, + 113, + 13, + 0, // Skip to: 19231 + /* 15790 */ MCD_OPC_Decode, + 222, + 16, + 201, + 1, // Opcode: VCGEuv8i16 + /* 15795 */ MCD_OPC_FilterValue, + 2, + 103, + 13, + 0, // Skip to: 19231 + /* 15800 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15803 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15819 + /* 15809 */ MCD_OPC_CheckPredicate, + 26, + 89, + 13, + 0, // Skip to: 19231 + /* 15814 */ MCD_OPC_Decode, + 215, + 16, + 201, + 1, // Opcode: VCGEsv4i32 + /* 15819 */ MCD_OPC_FilterValue, + 243, + 1, + 78, + 13, + 0, // Skip to: 19231 + /* 15825 */ MCD_OPC_CheckPredicate, + 26, + 73, + 13, + 0, // Skip to: 19231 + /* 15830 */ MCD_OPC_Decode, + 221, + 16, + 201, + 1, // Opcode: VCGEuv4i32 + /* 15835 */ MCD_OPC_FilterValue, + 4, + 163, + 0, + 0, // Skip to: 16003 + /* 15840 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 15843 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 15883 + /* 15848 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15851 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15867 + /* 15857 */ MCD_OPC_CheckPredicate, + 26, + 41, + 13, + 0, // Skip to: 19231 + /* 15862 */ MCD_OPC_Decode, + 255, + 24, + 205, + 1, // Opcode: VQSHLsv16i8 + /* 15867 */ MCD_OPC_FilterValue, + 243, + 1, + 30, + 13, + 0, // Skip to: 19231 + /* 15873 */ MCD_OPC_CheckPredicate, + 26, + 25, + 13, + 0, // Skip to: 19231 + /* 15878 */ MCD_OPC_Decode, + 143, + 25, + 205, + 1, // Opcode: VQSHLuv16i8 + /* 15883 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 15923 + /* 15888 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15891 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15907 + /* 15897 */ MCD_OPC_CheckPredicate, + 26, + 1, + 13, + 0, // Skip to: 19231 + /* 15902 */ MCD_OPC_Decode, + 133, + 25, + 205, + 1, // Opcode: VQSHLsv8i16 + /* 15907 */ MCD_OPC_FilterValue, + 243, + 1, + 246, + 12, + 0, // Skip to: 19231 + /* 15913 */ MCD_OPC_CheckPredicate, + 26, + 241, + 12, + 0, // Skip to: 19231 + /* 15918 */ MCD_OPC_Decode, + 149, + 25, + 205, + 1, // Opcode: VQSHLuv8i16 + /* 15923 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 15963 + /* 15928 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15931 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15947 + /* 15937 */ MCD_OPC_CheckPredicate, + 26, + 217, + 12, + 0, // Skip to: 19231 + /* 15942 */ MCD_OPC_Decode, + 132, + 25, + 205, + 1, // Opcode: VQSHLsv4i32 + /* 15947 */ MCD_OPC_FilterValue, + 243, + 1, + 206, + 12, + 0, // Skip to: 19231 + /* 15953 */ MCD_OPC_CheckPredicate, + 26, + 201, + 12, + 0, // Skip to: 19231 + /* 15958 */ MCD_OPC_Decode, + 148, + 25, + 205, + 1, // Opcode: VQSHLuv4i32 + /* 15963 */ MCD_OPC_FilterValue, + 3, + 191, + 12, + 0, // Skip to: 19231 + /* 15968 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 15971 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 15987 + /* 15977 */ MCD_OPC_CheckPredicate, + 26, + 177, + 12, + 0, // Skip to: 19231 + /* 15982 */ MCD_OPC_Decode, + 130, + 25, + 205, + 1, // Opcode: VQSHLsv2i64 + /* 15987 */ MCD_OPC_FilterValue, + 243, + 1, + 166, + 12, + 0, // Skip to: 19231 + /* 15993 */ MCD_OPC_CheckPredicate, + 26, + 161, + 12, + 0, // Skip to: 19231 + /* 15998 */ MCD_OPC_Decode, + 146, + 25, + 205, + 1, // Opcode: VQSHLuv2i64 + /* 16003 */ MCD_OPC_FilterValue, + 5, + 163, + 0, + 0, // Skip to: 16171 + /* 16008 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16011 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16051 + /* 16016 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16019 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16035 + /* 16025 */ MCD_OPC_CheckPredicate, + 26, + 129, + 12, + 0, // Skip to: 19231 + /* 16030 */ MCD_OPC_Decode, + 214, + 24, + 205, + 1, // Opcode: VQRSHLsv16i8 + /* 16035 */ MCD_OPC_FilterValue, + 243, + 1, + 118, + 12, + 0, // Skip to: 19231 + /* 16041 */ MCD_OPC_CheckPredicate, + 26, + 113, + 12, + 0, // Skip to: 19231 + /* 16046 */ MCD_OPC_Decode, + 222, + 24, + 205, + 1, // Opcode: VQRSHLuv16i8 + /* 16051 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16091 + /* 16056 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16059 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16075 + /* 16065 */ MCD_OPC_CheckPredicate, + 26, + 89, + 12, + 0, // Skip to: 19231 + /* 16070 */ MCD_OPC_Decode, + 220, + 24, + 205, + 1, // Opcode: VQRSHLsv8i16 + /* 16075 */ MCD_OPC_FilterValue, + 243, + 1, + 78, + 12, + 0, // Skip to: 19231 + /* 16081 */ MCD_OPC_CheckPredicate, + 26, + 73, + 12, + 0, // Skip to: 19231 + /* 16086 */ MCD_OPC_Decode, + 228, + 24, + 205, + 1, // Opcode: VQRSHLuv8i16 + /* 16091 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 16131 + /* 16096 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16099 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16115 + /* 16105 */ MCD_OPC_CheckPredicate, + 26, + 49, + 12, + 0, // Skip to: 19231 + /* 16110 */ MCD_OPC_Decode, + 219, + 24, + 205, + 1, // Opcode: VQRSHLsv4i32 + /* 16115 */ MCD_OPC_FilterValue, + 243, + 1, + 38, + 12, + 0, // Skip to: 19231 + /* 16121 */ MCD_OPC_CheckPredicate, + 26, + 33, + 12, + 0, // Skip to: 19231 + /* 16126 */ MCD_OPC_Decode, + 227, + 24, + 205, + 1, // Opcode: VQRSHLuv4i32 + /* 16131 */ MCD_OPC_FilterValue, + 3, + 23, + 12, + 0, // Skip to: 19231 + /* 16136 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16139 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16155 + /* 16145 */ MCD_OPC_CheckPredicate, + 26, + 9, + 12, + 0, // Skip to: 19231 + /* 16150 */ MCD_OPC_Decode, + 217, + 24, + 205, + 1, // Opcode: VQRSHLsv2i64 + /* 16155 */ MCD_OPC_FilterValue, + 243, + 1, + 254, + 11, + 0, // Skip to: 19231 + /* 16161 */ MCD_OPC_CheckPredicate, + 26, + 249, + 11, + 0, // Skip to: 19231 + /* 16166 */ MCD_OPC_Decode, + 225, + 24, + 205, + 1, // Opcode: VQRSHLuv2i64 + /* 16171 */ MCD_OPC_FilterValue, + 6, + 123, + 0, + 0, // Skip to: 16299 + /* 16176 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16179 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16219 + /* 16184 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16187 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16203 + /* 16193 */ MCD_OPC_CheckPredicate, + 26, + 217, + 11, + 0, // Skip to: 19231 + /* 16198 */ MCD_OPC_Decode, + 145, + 22, + 201, + 1, // Opcode: VMINsv16i8 + /* 16203 */ MCD_OPC_FilterValue, + 243, + 1, + 206, + 11, + 0, // Skip to: 19231 + /* 16209 */ MCD_OPC_CheckPredicate, + 26, + 201, + 11, + 0, // Skip to: 19231 + /* 16214 */ MCD_OPC_Decode, + 151, + 22, + 201, + 1, // Opcode: VMINuv16i8 + /* 16219 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16259 + /* 16224 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16227 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16243 + /* 16233 */ MCD_OPC_CheckPredicate, + 26, + 177, + 11, + 0, // Skip to: 19231 + /* 16238 */ MCD_OPC_Decode, + 149, + 22, + 201, + 1, // Opcode: VMINsv8i16 + /* 16243 */ MCD_OPC_FilterValue, + 243, + 1, + 166, + 11, + 0, // Skip to: 19231 + /* 16249 */ MCD_OPC_CheckPredicate, + 26, + 161, + 11, + 0, // Skip to: 19231 + /* 16254 */ MCD_OPC_Decode, + 155, + 22, + 201, + 1, // Opcode: VMINuv8i16 + /* 16259 */ MCD_OPC_FilterValue, + 2, + 151, + 11, + 0, // Skip to: 19231 + /* 16264 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16267 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16283 + /* 16273 */ MCD_OPC_CheckPredicate, + 26, + 137, + 11, + 0, // Skip to: 19231 + /* 16278 */ MCD_OPC_Decode, + 148, + 22, + 201, + 1, // Opcode: VMINsv4i32 + /* 16283 */ MCD_OPC_FilterValue, + 243, + 1, + 126, + 11, + 0, // Skip to: 19231 + /* 16289 */ MCD_OPC_CheckPredicate, + 26, + 121, + 11, + 0, // Skip to: 19231 + /* 16294 */ MCD_OPC_Decode, + 154, + 22, + 201, + 1, // Opcode: VMINuv4i32 + /* 16299 */ MCD_OPC_FilterValue, + 7, + 123, + 0, + 0, // Skip to: 16427 + /* 16304 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16307 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16347 + /* 16312 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16315 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16331 + /* 16321 */ MCD_OPC_CheckPredicate, + 26, + 89, + 11, + 0, // Skip to: 19231 + /* 16326 */ MCD_OPC_Decode, + 207, + 15, + 209, + 1, // Opcode: VABAsv16i8 + /* 16331 */ MCD_OPC_FilterValue, + 243, + 1, + 78, + 11, + 0, // Skip to: 19231 + /* 16337 */ MCD_OPC_CheckPredicate, + 26, + 73, + 11, + 0, // Skip to: 19231 + /* 16342 */ MCD_OPC_Decode, + 213, + 15, + 209, + 1, // Opcode: VABAuv16i8 + /* 16347 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16387 + /* 16352 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16355 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16371 + /* 16361 */ MCD_OPC_CheckPredicate, + 26, + 49, + 11, + 0, // Skip to: 19231 + /* 16366 */ MCD_OPC_Decode, + 211, + 15, + 209, + 1, // Opcode: VABAsv8i16 + /* 16371 */ MCD_OPC_FilterValue, + 243, + 1, + 38, + 11, + 0, // Skip to: 19231 + /* 16377 */ MCD_OPC_CheckPredicate, + 26, + 33, + 11, + 0, // Skip to: 19231 + /* 16382 */ MCD_OPC_Decode, + 217, + 15, + 209, + 1, // Opcode: VABAuv8i16 + /* 16387 */ MCD_OPC_FilterValue, + 2, + 23, + 11, + 0, // Skip to: 19231 + /* 16392 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16395 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16411 + /* 16401 */ MCD_OPC_CheckPredicate, + 26, + 9, + 11, + 0, // Skip to: 19231 + /* 16406 */ MCD_OPC_Decode, + 210, + 15, + 209, + 1, // Opcode: VABAsv4i32 + /* 16411 */ MCD_OPC_FilterValue, + 243, + 1, + 254, + 10, + 0, // Skip to: 19231 + /* 16417 */ MCD_OPC_CheckPredicate, + 26, + 249, + 10, + 0, // Skip to: 19231 + /* 16422 */ MCD_OPC_Decode, + 216, + 15, + 209, + 1, // Opcode: VABAuv4i32 + /* 16427 */ MCD_OPC_FilterValue, + 8, + 123, + 0, + 0, // Skip to: 16555 + /* 16432 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16435 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16475 + /* 16440 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16443 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16459 + /* 16449 */ MCD_OPC_CheckPredicate, + 26, + 217, + 10, + 0, // Skip to: 19231 + /* 16454 */ MCD_OPC_Decode, + 162, + 30, + 201, + 1, // Opcode: VTSTv16i8 + /* 16459 */ MCD_OPC_FilterValue, + 243, + 1, + 206, + 10, + 0, // Skip to: 19231 + /* 16465 */ MCD_OPC_CheckPredicate, + 26, + 201, + 10, + 0, // Skip to: 19231 + /* 16470 */ MCD_OPC_Decode, + 192, + 16, + 201, + 1, // Opcode: VCEQv16i8 + /* 16475 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16515 + /* 16480 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16483 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16499 + /* 16489 */ MCD_OPC_CheckPredicate, + 26, + 177, + 10, + 0, // Skip to: 19231 + /* 16494 */ MCD_OPC_Decode, + 166, + 30, + 201, + 1, // Opcode: VTSTv8i16 + /* 16499 */ MCD_OPC_FilterValue, + 243, + 1, + 166, + 10, + 0, // Skip to: 19231 + /* 16505 */ MCD_OPC_CheckPredicate, + 26, + 161, + 10, + 0, // Skip to: 19231 + /* 16510 */ MCD_OPC_Decode, + 196, + 16, + 201, + 1, // Opcode: VCEQv8i16 + /* 16515 */ MCD_OPC_FilterValue, + 2, + 151, + 10, + 0, // Skip to: 19231 + /* 16520 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16523 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16539 + /* 16529 */ MCD_OPC_CheckPredicate, + 26, + 137, + 10, + 0, // Skip to: 19231 + /* 16534 */ MCD_OPC_Decode, + 165, + 30, + 201, + 1, // Opcode: VTSTv4i32 + /* 16539 */ MCD_OPC_FilterValue, + 243, + 1, + 126, + 10, + 0, // Skip to: 19231 + /* 16545 */ MCD_OPC_CheckPredicate, + 26, + 121, + 10, + 0, // Skip to: 19231 + /* 16550 */ MCD_OPC_Decode, + 195, + 16, + 201, + 1, // Opcode: VCEQv4i32 + /* 16555 */ MCD_OPC_FilterValue, + 9, + 89, + 0, + 0, // Skip to: 16649 + /* 16560 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16563 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16603 + /* 16568 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16571 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16587 + /* 16577 */ MCD_OPC_CheckPredicate, + 26, + 89, + 10, + 0, // Skip to: 19231 + /* 16582 */ MCD_OPC_Decode, + 174, + 23, + 201, + 1, // Opcode: VMULv16i8 + /* 16587 */ MCD_OPC_FilterValue, + 243, + 1, + 78, + 10, + 0, // Skip to: 19231 + /* 16593 */ MCD_OPC_CheckPredicate, + 26, + 73, + 10, + 0, // Skip to: 19231 + /* 16598 */ MCD_OPC_Decode, + 165, + 23, + 201, + 1, // Opcode: VMULpq + /* 16603 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 16626 + /* 16608 */ MCD_OPC_CheckPredicate, + 26, + 58, + 10, + 0, // Skip to: 19231 + /* 16613 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 50, + 10, + 0, // Skip to: 19231 + /* 16621 */ MCD_OPC_Decode, + 178, + 23, + 201, + 1, // Opcode: VMULv8i16 + /* 16626 */ MCD_OPC_FilterValue, + 2, + 40, + 10, + 0, // Skip to: 19231 + /* 16631 */ MCD_OPC_CheckPredicate, + 26, + 35, + 10, + 0, // Skip to: 19231 + /* 16636 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 27, + 10, + 0, // Skip to: 19231 + /* 16644 */ MCD_OPC_Decode, + 177, + 23, + 201, + 1, // Opcode: VMULv4i32 + /* 16649 */ MCD_OPC_FilterValue, + 11, + 49, + 0, + 0, // Skip to: 16703 + /* 16654 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16657 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 16680 + /* 16662 */ MCD_OPC_CheckPredicate, + 28, + 4, + 10, + 0, // Skip to: 19231 + /* 16667 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 252, + 9, + 0, // Skip to: 19231 + /* 16675 */ MCD_OPC_Decode, + 197, + 24, + 209, + 1, // Opcode: VQRDMLAHv8i16 + /* 16680 */ MCD_OPC_FilterValue, + 2, + 242, + 9, + 0, // Skip to: 19231 + /* 16685 */ MCD_OPC_CheckPredicate, + 28, + 237, + 9, + 0, // Skip to: 19231 + /* 16690 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 229, + 9, + 0, // Skip to: 19231 + /* 16698 */ MCD_OPC_Decode, + 196, + 24, + 209, + 1, // Opcode: VQRDMLAHv4i32 + /* 16703 */ MCD_OPC_FilterValue, + 12, + 129, + 0, + 0, // Skip to: 16837 + /* 16708 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16711 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 16734 + /* 16716 */ MCD_OPC_CheckPredicate, + 32, + 206, + 9, + 0, // Skip to: 19231 + /* 16721 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 198, + 9, + 0, // Skip to: 19231 + /* 16729 */ MCD_OPC_Decode, + 190, + 18, + 209, + 1, // Opcode: VFMAfq + /* 16734 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16774 + /* 16739 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16742 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16758 + /* 16748 */ MCD_OPC_CheckPredicate, + 27, + 174, + 9, + 0, // Skip to: 19231 + /* 16753 */ MCD_OPC_Decode, + 192, + 18, + 209, + 1, // Opcode: VFMAhq + /* 16758 */ MCD_OPC_FilterValue, + 243, + 1, + 163, + 9, + 0, // Skip to: 19231 + /* 16764 */ MCD_OPC_CheckPredicate, + 28, + 158, + 9, + 0, // Skip to: 19231 + /* 16769 */ MCD_OPC_Decode, + 205, + 24, + 209, + 1, // Opcode: VQRDMLSHv8i16 + /* 16774 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 16814 + /* 16779 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16782 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16798 + /* 16788 */ MCD_OPC_CheckPredicate, + 32, + 134, + 9, + 0, // Skip to: 19231 + /* 16793 */ MCD_OPC_Decode, + 201, + 18, + 209, + 1, // Opcode: VFMSfq + /* 16798 */ MCD_OPC_FilterValue, + 243, + 1, + 123, + 9, + 0, // Skip to: 19231 + /* 16804 */ MCD_OPC_CheckPredicate, + 28, + 118, + 9, + 0, // Skip to: 19231 + /* 16809 */ MCD_OPC_Decode, + 204, + 24, + 209, + 1, // Opcode: VQRDMLSHv4i32 + /* 16814 */ MCD_OPC_FilterValue, + 3, + 108, + 9, + 0, // Skip to: 19231 + /* 16819 */ MCD_OPC_CheckPredicate, + 27, + 103, + 9, + 0, // Skip to: 19231 + /* 16824 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 95, + 9, + 0, // Skip to: 19231 + /* 16832 */ MCD_OPC_Decode, + 203, + 18, + 209, + 1, // Opcode: VFMShq + /* 16837 */ MCD_OPC_FilterValue, + 13, + 129, + 0, + 0, // Skip to: 16971 + /* 16842 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16845 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 16885 + /* 16850 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16853 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16869 + /* 16859 */ MCD_OPC_CheckPredicate, + 26, + 63, + 9, + 0, // Skip to: 19231 + /* 16864 */ MCD_OPC_Decode, + 171, + 22, + 209, + 1, // Opcode: VMLAfq + /* 16869 */ MCD_OPC_FilterValue, + 243, + 1, + 52, + 9, + 0, // Skip to: 19231 + /* 16875 */ MCD_OPC_CheckPredicate, + 26, + 47, + 9, + 0, // Skip to: 19231 + /* 16880 */ MCD_OPC_Decode, + 161, + 23, + 201, + 1, // Opcode: VMULfq + /* 16885 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 16925 + /* 16890 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 16893 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 16909 + /* 16899 */ MCD_OPC_CheckPredicate, + 27, + 23, + 9, + 0, // Skip to: 19231 + /* 16904 */ MCD_OPC_Decode, + 173, + 22, + 209, + 1, // Opcode: VMLAhq + /* 16909 */ MCD_OPC_FilterValue, + 243, + 1, + 12, + 9, + 0, // Skip to: 19231 + /* 16915 */ MCD_OPC_CheckPredicate, + 27, + 7, + 9, + 0, // Skip to: 19231 + /* 16920 */ MCD_OPC_Decode, + 163, + 23, + 201, + 1, // Opcode: VMULhq + /* 16925 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 16948 + /* 16930 */ MCD_OPC_CheckPredicate, + 26, + 248, + 8, + 0, // Skip to: 19231 + /* 16935 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 240, + 8, + 0, // Skip to: 19231 + /* 16943 */ MCD_OPC_Decode, + 202, + 22, + 209, + 1, // Opcode: VMLSfq + /* 16948 */ MCD_OPC_FilterValue, + 3, + 230, + 8, + 0, // Skip to: 19231 + /* 16953 */ MCD_OPC_CheckPredicate, + 27, + 225, + 8, + 0, // Skip to: 19231 + /* 16958 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 217, + 8, + 0, // Skip to: 19231 + /* 16966 */ MCD_OPC_Decode, + 204, + 22, + 209, + 1, // Opcode: VMLShq + /* 16971 */ MCD_OPC_FilterValue, + 14, + 95, + 0, + 0, // Skip to: 17071 + /* 16976 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 16979 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 17002 + /* 16984 */ MCD_OPC_CheckPredicate, + 26, + 194, + 8, + 0, // Skip to: 19231 + /* 16989 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 186, + 8, + 0, // Skip to: 19231 + /* 16997 */ MCD_OPC_Decode, + 255, + 15, + 201, + 1, // Opcode: VACGEfq + /* 17002 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 17025 + /* 17007 */ MCD_OPC_CheckPredicate, + 27, + 171, + 8, + 0, // Skip to: 19231 + /* 17012 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 163, + 8, + 0, // Skip to: 19231 + /* 17020 */ MCD_OPC_Decode, + 129, + 16, + 201, + 1, // Opcode: VACGEhq + /* 17025 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 17048 + /* 17030 */ MCD_OPC_CheckPredicate, + 26, + 148, + 8, + 0, // Skip to: 19231 + /* 17035 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 140, + 8, + 0, // Skip to: 19231 + /* 17043 */ MCD_OPC_Decode, + 131, + 16, + 201, + 1, // Opcode: VACGTfq + /* 17048 */ MCD_OPC_FilterValue, + 3, + 130, + 8, + 0, // Skip to: 19231 + /* 17053 */ MCD_OPC_CheckPredicate, + 27, + 125, + 8, + 0, // Skip to: 19231 + /* 17058 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 117, + 8, + 0, // Skip to: 19231 + /* 17066 */ MCD_OPC_Decode, + 133, + 16, + 201, + 1, // Opcode: VACGThq + /* 17071 */ MCD_OPC_FilterValue, + 15, + 107, + 8, + 0, // Skip to: 19231 + /* 17076 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 17079 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 17102 + /* 17084 */ MCD_OPC_CheckPredicate, + 26, + 94, + 8, + 0, // Skip to: 19231 + /* 17089 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 86, + 8, + 0, // Skip to: 19231 + /* 17097 */ MCD_OPC_Decode, + 186, + 25, + 201, + 1, // Opcode: VRECPSfq + /* 17102 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 17125 + /* 17107 */ MCD_OPC_CheckPredicate, + 27, + 71, + 8, + 0, // Skip to: 19231 + /* 17112 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 63, + 8, + 0, // Skip to: 19231 + /* 17120 */ MCD_OPC_Decode, + 188, + 25, + 201, + 1, // Opcode: VRECPShq + /* 17125 */ MCD_OPC_FilterValue, + 2, + 18, + 0, + 0, // Skip to: 17148 + /* 17130 */ MCD_OPC_CheckPredicate, + 26, + 48, + 8, + 0, // Skip to: 19231 + /* 17135 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 40, + 8, + 0, // Skip to: 19231 + /* 17143 */ MCD_OPC_Decode, + 172, + 26, + 201, + 1, // Opcode: VRSQRTSfq + /* 17148 */ MCD_OPC_FilterValue, + 3, + 30, + 8, + 0, // Skip to: 19231 + /* 17153 */ MCD_OPC_CheckPredicate, + 27, + 25, + 8, + 0, // Skip to: 19231 + /* 17158 */ MCD_OPC_CheckField, + 24, + 8, + 242, + 1, + 17, + 8, + 0, // Skip to: 19231 + /* 17166 */ MCD_OPC_Decode, + 174, + 26, + 201, + 1, // Opcode: VRSQRTShq + /* 17171 */ MCD_OPC_FilterValue, + 1, + 7, + 8, + 0, // Skip to: 19231 + /* 17176 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 17179 */ MCD_OPC_FilterValue, + 0, + 217, + 6, + 0, // Skip to: 18937 + /* 17184 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 17187 */ MCD_OPC_FilterValue, + 121, + 247, + 7, + 0, // Skip to: 19231 + /* 17192 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 17195 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 17339 + /* 17200 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17203 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17301 + /* 17208 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17211 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17263 + /* 17216 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17219 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17241 + /* 17224 */ MCD_OPC_CheckPredicate, + 26, + 239, + 5, + 0, // Skip to: 18748 + /* 17229 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 232, + 5, + 0, // Skip to: 18748 + /* 17236 */ MCD_OPC_Decode, + 251, + 26, + 141, + 2, // Opcode: VSHRsv16i8 + /* 17241 */ MCD_OPC_FilterValue, + 1, + 222, + 5, + 0, // Skip to: 18748 + /* 17246 */ MCD_OPC_CheckPredicate, + 26, + 217, + 5, + 0, // Skip to: 18748 + /* 17251 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 210, + 5, + 0, // Skip to: 18748 + /* 17258 */ MCD_OPC_Decode, + 131, + 27, + 141, + 2, // Opcode: VSHRuv16i8 + /* 17263 */ MCD_OPC_FilterValue, + 1, + 200, + 5, + 0, // Skip to: 18748 + /* 17268 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17271 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17286 + /* 17276 */ MCD_OPC_CheckPredicate, + 26, + 187, + 5, + 0, // Skip to: 18748 + /* 17281 */ MCD_OPC_Decode, + 129, + 27, + 142, + 2, // Opcode: VSHRsv8i16 + /* 17286 */ MCD_OPC_FilterValue, + 1, + 177, + 5, + 0, // Skip to: 18748 + /* 17291 */ MCD_OPC_CheckPredicate, + 26, + 172, + 5, + 0, // Skip to: 18748 + /* 17296 */ MCD_OPC_Decode, + 137, + 27, + 142, + 2, // Opcode: VSHRuv8i16 + /* 17301 */ MCD_OPC_FilterValue, + 1, + 162, + 5, + 0, // Skip to: 18748 + /* 17306 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17309 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17324 + /* 17314 */ MCD_OPC_CheckPredicate, + 26, + 149, + 5, + 0, // Skip to: 18748 + /* 17319 */ MCD_OPC_Decode, + 128, + 27, + 143, + 2, // Opcode: VSHRsv4i32 + /* 17324 */ MCD_OPC_FilterValue, + 1, + 139, + 5, + 0, // Skip to: 18748 + /* 17329 */ MCD_OPC_CheckPredicate, + 26, + 134, + 5, + 0, // Skip to: 18748 + /* 17334 */ MCD_OPC_Decode, + 136, + 27, + 143, + 2, // Opcode: VSHRuv4i32 + /* 17339 */ MCD_OPC_FilterValue, + 1, + 139, + 0, + 0, // Skip to: 17483 + /* 17344 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17347 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17445 + /* 17352 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17355 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17407 + /* 17360 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17363 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17385 + /* 17368 */ MCD_OPC_CheckPredicate, + 26, + 95, + 5, + 0, // Skip to: 18748 + /* 17373 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 88, + 5, + 0, // Skip to: 18748 + /* 17380 */ MCD_OPC_Decode, + 160, + 27, + 144, + 2, // Opcode: VSRAsv16i8 + /* 17385 */ MCD_OPC_FilterValue, + 1, + 78, + 5, + 0, // Skip to: 18748 + /* 17390 */ MCD_OPC_CheckPredicate, + 26, + 73, + 5, + 0, // Skip to: 18748 + /* 17395 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 66, + 5, + 0, // Skip to: 18748 + /* 17402 */ MCD_OPC_Decode, + 168, + 27, + 144, + 2, // Opcode: VSRAuv16i8 + /* 17407 */ MCD_OPC_FilterValue, + 1, + 56, + 5, + 0, // Skip to: 18748 + /* 17412 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17415 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17430 + /* 17420 */ MCD_OPC_CheckPredicate, + 26, + 43, + 5, + 0, // Skip to: 18748 + /* 17425 */ MCD_OPC_Decode, + 166, + 27, + 145, + 2, // Opcode: VSRAsv8i16 + /* 17430 */ MCD_OPC_FilterValue, + 1, + 33, + 5, + 0, // Skip to: 18748 + /* 17435 */ MCD_OPC_CheckPredicate, + 26, + 28, + 5, + 0, // Skip to: 18748 + /* 17440 */ MCD_OPC_Decode, + 174, + 27, + 145, + 2, // Opcode: VSRAuv8i16 + /* 17445 */ MCD_OPC_FilterValue, + 1, + 18, + 5, + 0, // Skip to: 18748 + /* 17450 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17453 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17468 + /* 17458 */ MCD_OPC_CheckPredicate, + 26, + 5, + 5, + 0, // Skip to: 18748 + /* 17463 */ MCD_OPC_Decode, + 165, + 27, + 146, + 2, // Opcode: VSRAsv4i32 + /* 17468 */ MCD_OPC_FilterValue, + 1, + 251, + 4, + 0, // Skip to: 18748 + /* 17473 */ MCD_OPC_CheckPredicate, + 26, + 246, + 4, + 0, // Skip to: 18748 + /* 17478 */ MCD_OPC_Decode, + 173, + 27, + 146, + 2, // Opcode: VSRAuv4i32 + /* 17483 */ MCD_OPC_FilterValue, + 2, + 139, + 0, + 0, // Skip to: 17627 + /* 17488 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17491 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17589 + /* 17496 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17499 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17551 + /* 17504 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17507 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17529 + /* 17512 */ MCD_OPC_CheckPredicate, + 26, + 207, + 4, + 0, // Skip to: 18748 + /* 17517 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 200, + 4, + 0, // Skip to: 18748 + /* 17524 */ MCD_OPC_Decode, + 149, + 26, + 141, + 2, // Opcode: VRSHRsv16i8 + /* 17529 */ MCD_OPC_FilterValue, + 1, + 190, + 4, + 0, // Skip to: 18748 + /* 17534 */ MCD_OPC_CheckPredicate, + 26, + 185, + 4, + 0, // Skip to: 18748 + /* 17539 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 178, + 4, + 0, // Skip to: 18748 + /* 17546 */ MCD_OPC_Decode, + 157, + 26, + 141, + 2, // Opcode: VRSHRuv16i8 + /* 17551 */ MCD_OPC_FilterValue, + 1, + 168, + 4, + 0, // Skip to: 18748 + /* 17556 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17559 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17574 + /* 17564 */ MCD_OPC_CheckPredicate, + 26, + 155, + 4, + 0, // Skip to: 18748 + /* 17569 */ MCD_OPC_Decode, + 155, + 26, + 142, + 2, // Opcode: VRSHRsv8i16 + /* 17574 */ MCD_OPC_FilterValue, + 1, + 145, + 4, + 0, // Skip to: 18748 + /* 17579 */ MCD_OPC_CheckPredicate, + 26, + 140, + 4, + 0, // Skip to: 18748 + /* 17584 */ MCD_OPC_Decode, + 163, + 26, + 142, + 2, // Opcode: VRSHRuv8i16 + /* 17589 */ MCD_OPC_FilterValue, + 1, + 130, + 4, + 0, // Skip to: 18748 + /* 17594 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17597 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17612 + /* 17602 */ MCD_OPC_CheckPredicate, + 26, + 117, + 4, + 0, // Skip to: 18748 + /* 17607 */ MCD_OPC_Decode, + 154, + 26, + 143, + 2, // Opcode: VRSHRsv4i32 + /* 17612 */ MCD_OPC_FilterValue, + 1, + 107, + 4, + 0, // Skip to: 18748 + /* 17617 */ MCD_OPC_CheckPredicate, + 26, + 102, + 4, + 0, // Skip to: 18748 + /* 17622 */ MCD_OPC_Decode, + 162, + 26, + 143, + 2, // Opcode: VRSHRuv4i32 + /* 17627 */ MCD_OPC_FilterValue, + 3, + 139, + 0, + 0, // Skip to: 17771 + /* 17632 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17635 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17733 + /* 17640 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17643 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17695 + /* 17648 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17651 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17673 + /* 17656 */ MCD_OPC_CheckPredicate, + 26, + 63, + 4, + 0, // Skip to: 18748 + /* 17661 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 56, + 4, + 0, // Skip to: 18748 + /* 17668 */ MCD_OPC_Decode, + 175, + 26, + 144, + 2, // Opcode: VRSRAsv16i8 + /* 17673 */ MCD_OPC_FilterValue, + 1, + 46, + 4, + 0, // Skip to: 18748 + /* 17678 */ MCD_OPC_CheckPredicate, + 26, + 41, + 4, + 0, // Skip to: 18748 + /* 17683 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 34, + 4, + 0, // Skip to: 18748 + /* 17690 */ MCD_OPC_Decode, + 183, + 26, + 144, + 2, // Opcode: VRSRAuv16i8 + /* 17695 */ MCD_OPC_FilterValue, + 1, + 24, + 4, + 0, // Skip to: 18748 + /* 17700 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17703 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17718 + /* 17708 */ MCD_OPC_CheckPredicate, + 26, + 11, + 4, + 0, // Skip to: 18748 + /* 17713 */ MCD_OPC_Decode, + 181, + 26, + 145, + 2, // Opcode: VRSRAsv8i16 + /* 17718 */ MCD_OPC_FilterValue, + 1, + 1, + 4, + 0, // Skip to: 18748 + /* 17723 */ MCD_OPC_CheckPredicate, + 26, + 252, + 3, + 0, // Skip to: 18748 + /* 17728 */ MCD_OPC_Decode, + 189, + 26, + 145, + 2, // Opcode: VRSRAuv8i16 + /* 17733 */ MCD_OPC_FilterValue, + 1, + 242, + 3, + 0, // Skip to: 18748 + /* 17738 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17741 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17756 + /* 17746 */ MCD_OPC_CheckPredicate, + 26, + 229, + 3, + 0, // Skip to: 18748 + /* 17751 */ MCD_OPC_Decode, + 180, + 26, + 146, + 2, // Opcode: VRSRAsv4i32 + /* 17756 */ MCD_OPC_FilterValue, + 1, + 219, + 3, + 0, // Skip to: 18748 + /* 17761 */ MCD_OPC_CheckPredicate, + 26, + 214, + 3, + 0, // Skip to: 18748 + /* 17766 */ MCD_OPC_Decode, + 188, + 26, + 146, + 2, // Opcode: VRSRAuv4i32 + /* 17771 */ MCD_OPC_FilterValue, + 4, + 84, + 0, + 0, // Skip to: 17860 + /* 17776 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17779 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 17838 + /* 17784 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17787 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 17816 + /* 17792 */ MCD_OPC_CheckPredicate, + 26, + 183, + 3, + 0, // Skip to: 18748 + /* 17797 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 176, + 3, + 0, // Skip to: 18748 + /* 17804 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 169, + 3, + 0, // Skip to: 18748 + /* 17811 */ MCD_OPC_Decode, + 176, + 27, + 144, + 2, // Opcode: VSRIv16i8 + /* 17816 */ MCD_OPC_FilterValue, + 1, + 159, + 3, + 0, // Skip to: 18748 + /* 17821 */ MCD_OPC_CheckPredicate, + 26, + 154, + 3, + 0, // Skip to: 18748 + /* 17826 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 147, + 3, + 0, // Skip to: 18748 + /* 17833 */ MCD_OPC_Decode, + 182, + 27, + 145, + 2, // Opcode: VSRIv8i16 + /* 17838 */ MCD_OPC_FilterValue, + 1, + 137, + 3, + 0, // Skip to: 18748 + /* 17843 */ MCD_OPC_CheckPredicate, + 26, + 132, + 3, + 0, // Skip to: 18748 + /* 17848 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 125, + 3, + 0, // Skip to: 18748 + /* 17855 */ MCD_OPC_Decode, + 181, + 27, + 146, + 2, // Opcode: VSRIv4i32 + /* 17860 */ MCD_OPC_FilterValue, + 5, + 139, + 0, + 0, // Skip to: 18004 + /* 17865 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 17868 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 17966 + /* 17873 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 17876 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 17928 + /* 17881 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17884 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 17906 + /* 17889 */ MCD_OPC_CheckPredicate, + 26, + 86, + 3, + 0, // Skip to: 18748 + /* 17894 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 79, + 3, + 0, // Skip to: 18748 + /* 17901 */ MCD_OPC_Decode, + 224, + 26, + 147, + 2, // Opcode: VSHLiv16i8 + /* 17906 */ MCD_OPC_FilterValue, + 1, + 69, + 3, + 0, // Skip to: 18748 + /* 17911 */ MCD_OPC_CheckPredicate, + 26, + 64, + 3, + 0, // Skip to: 18748 + /* 17916 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 57, + 3, + 0, // Skip to: 18748 + /* 17923 */ MCD_OPC_Decode, + 145, + 27, + 148, + 2, // Opcode: VSLIv16i8 + /* 17928 */ MCD_OPC_FilterValue, + 1, + 47, + 3, + 0, // Skip to: 18748 + /* 17933 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17936 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17951 + /* 17941 */ MCD_OPC_CheckPredicate, + 26, + 34, + 3, + 0, // Skip to: 18748 + /* 17946 */ MCD_OPC_Decode, + 230, + 26, + 149, + 2, // Opcode: VSHLiv8i16 + /* 17951 */ MCD_OPC_FilterValue, + 1, + 24, + 3, + 0, // Skip to: 18748 + /* 17956 */ MCD_OPC_CheckPredicate, + 26, + 19, + 3, + 0, // Skip to: 18748 + /* 17961 */ MCD_OPC_Decode, + 151, + 27, + 150, + 2, // Opcode: VSLIv8i16 + /* 17966 */ MCD_OPC_FilterValue, + 1, + 9, + 3, + 0, // Skip to: 18748 + /* 17971 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 17974 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17989 + /* 17979 */ MCD_OPC_CheckPredicate, + 26, + 252, + 2, + 0, // Skip to: 18748 + /* 17984 */ MCD_OPC_Decode, + 229, + 26, + 151, + 2, // Opcode: VSHLiv4i32 + /* 17989 */ MCD_OPC_FilterValue, + 1, + 242, + 2, + 0, // Skip to: 18748 + /* 17994 */ MCD_OPC_CheckPredicate, + 26, + 237, + 2, + 0, // Skip to: 18748 + /* 17999 */ MCD_OPC_Decode, + 150, + 27, + 152, + 2, // Opcode: VSLIv4i32 + /* 18004 */ MCD_OPC_FilterValue, + 6, + 84, + 0, + 0, // Skip to: 18093 + /* 18009 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 18012 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 18071 + /* 18017 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 18020 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 18049 + /* 18025 */ MCD_OPC_CheckPredicate, + 26, + 206, + 2, + 0, // Skip to: 18748 + /* 18030 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 199, + 2, + 0, // Skip to: 18748 + /* 18037 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 192, + 2, + 0, // Skip to: 18748 + /* 18044 */ MCD_OPC_Decode, + 247, + 24, + 147, + 2, // Opcode: VQSHLsuv16i8 + /* 18049 */ MCD_OPC_FilterValue, + 1, + 182, + 2, + 0, // Skip to: 18748 + /* 18054 */ MCD_OPC_CheckPredicate, + 26, + 177, + 2, + 0, // Skip to: 18748 + /* 18059 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 170, + 2, + 0, // Skip to: 18748 + /* 18066 */ MCD_OPC_Decode, + 253, + 24, + 149, + 2, // Opcode: VQSHLsuv8i16 + /* 18071 */ MCD_OPC_FilterValue, + 1, + 160, + 2, + 0, // Skip to: 18748 + /* 18076 */ MCD_OPC_CheckPredicate, + 26, + 155, + 2, + 0, // Skip to: 18748 + /* 18081 */ MCD_OPC_CheckField, + 24, + 1, + 1, + 148, + 2, + 0, // Skip to: 18748 + /* 18088 */ MCD_OPC_Decode, + 252, + 24, + 151, + 2, // Opcode: VQSHLsuv4i32 + /* 18093 */ MCD_OPC_FilterValue, + 7, + 139, + 0, + 0, // Skip to: 18237 + /* 18098 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 18101 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 18199 + /* 18106 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 18109 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 18161 + /* 18114 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18117 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18139 + /* 18122 */ MCD_OPC_CheckPredicate, + 26, + 109, + 2, + 0, // Skip to: 18748 + /* 18127 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 102, + 2, + 0, // Skip to: 18748 + /* 18134 */ MCD_OPC_Decode, + 239, + 24, + 147, + 2, // Opcode: VQSHLsiv16i8 + /* 18139 */ MCD_OPC_FilterValue, + 1, + 92, + 2, + 0, // Skip to: 18748 + /* 18144 */ MCD_OPC_CheckPredicate, + 26, + 87, + 2, + 0, // Skip to: 18748 + /* 18149 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 80, + 2, + 0, // Skip to: 18748 + /* 18156 */ MCD_OPC_Decode, + 135, + 25, + 147, + 2, // Opcode: VQSHLuiv16i8 + /* 18161 */ MCD_OPC_FilterValue, + 1, + 70, + 2, + 0, // Skip to: 18748 + /* 18166 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18169 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18184 + /* 18174 */ MCD_OPC_CheckPredicate, + 26, + 57, + 2, + 0, // Skip to: 18748 + /* 18179 */ MCD_OPC_Decode, + 245, + 24, + 149, + 2, // Opcode: VQSHLsiv8i16 + /* 18184 */ MCD_OPC_FilterValue, + 1, + 47, + 2, + 0, // Skip to: 18748 + /* 18189 */ MCD_OPC_CheckPredicate, + 26, + 42, + 2, + 0, // Skip to: 18748 + /* 18194 */ MCD_OPC_Decode, + 141, + 25, + 149, + 2, // Opcode: VQSHLuiv8i16 + /* 18199 */ MCD_OPC_FilterValue, + 1, + 32, + 2, + 0, // Skip to: 18748 + /* 18204 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18207 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18222 + /* 18212 */ MCD_OPC_CheckPredicate, + 26, + 19, + 2, + 0, // Skip to: 18748 + /* 18217 */ MCD_OPC_Decode, + 244, + 24, + 151, + 2, // Opcode: VQSHLsiv4i32 + /* 18222 */ MCD_OPC_FilterValue, + 1, + 9, + 2, + 0, // Skip to: 18748 + /* 18227 */ MCD_OPC_CheckPredicate, + 26, + 4, + 2, + 0, // Skip to: 18748 + /* 18232 */ MCD_OPC_Decode, + 140, + 25, + 151, + 2, // Opcode: VQSHLuiv4i32 + /* 18237 */ MCD_OPC_FilterValue, + 8, + 139, + 0, + 0, // Skip to: 18381 + /* 18242 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 18245 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 18343 + /* 18250 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 18253 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 18305 + /* 18258 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18261 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18283 + /* 18266 */ MCD_OPC_CheckPredicate, + 26, + 221, + 1, + 0, // Skip to: 18748 + /* 18271 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 214, + 1, + 0, // Skip to: 18748 + /* 18278 */ MCD_OPC_Decode, + 148, + 26, + 129, + 2, // Opcode: VRSHRNv8i8 + /* 18283 */ MCD_OPC_FilterValue, + 1, + 204, + 1, + 0, // Skip to: 18748 + /* 18288 */ MCD_OPC_CheckPredicate, + 26, + 199, + 1, + 0, // Skip to: 18748 + /* 18293 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 192, + 1, + 0, // Skip to: 18748 + /* 18300 */ MCD_OPC_Decode, + 238, + 24, + 129, + 2, // Opcode: VQRSHRUNv8i8 + /* 18305 */ MCD_OPC_FilterValue, + 1, + 182, + 1, + 0, // Skip to: 18748 + /* 18310 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18313 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18328 + /* 18318 */ MCD_OPC_CheckPredicate, + 26, + 169, + 1, + 0, // Skip to: 18748 + /* 18323 */ MCD_OPC_Decode, + 147, + 26, + 130, + 2, // Opcode: VRSHRNv4i16 + /* 18328 */ MCD_OPC_FilterValue, + 1, + 159, + 1, + 0, // Skip to: 18748 + /* 18333 */ MCD_OPC_CheckPredicate, + 26, + 154, + 1, + 0, // Skip to: 18748 + /* 18338 */ MCD_OPC_Decode, + 237, + 24, + 130, + 2, // Opcode: VQRSHRUNv4i16 + /* 18343 */ MCD_OPC_FilterValue, + 1, + 144, + 1, + 0, // Skip to: 18748 + /* 18348 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18351 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18366 + /* 18356 */ MCD_OPC_CheckPredicate, + 26, + 131, + 1, + 0, // Skip to: 18748 + /* 18361 */ MCD_OPC_Decode, + 146, + 26, + 131, + 2, // Opcode: VRSHRNv2i32 + /* 18366 */ MCD_OPC_FilterValue, + 1, + 121, + 1, + 0, // Skip to: 18748 + /* 18371 */ MCD_OPC_CheckPredicate, + 26, + 116, + 1, + 0, // Skip to: 18748 + /* 18376 */ MCD_OPC_Decode, + 236, + 24, + 131, + 2, // Opcode: VQRSHRUNv2i32 + /* 18381 */ MCD_OPC_FilterValue, + 9, + 139, + 0, + 0, // Skip to: 18525 + /* 18386 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 18389 */ MCD_OPC_FilterValue, + 0, + 93, + 0, + 0, // Skip to: 18487 + /* 18394 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 18397 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 18449 + /* 18402 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18405 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18427 + /* 18410 */ MCD_OPC_CheckPredicate, + 26, + 77, + 1, + 0, // Skip to: 18748 + /* 18415 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 70, + 1, + 0, // Skip to: 18748 + /* 18422 */ MCD_OPC_Decode, + 232, + 24, + 129, + 2, // Opcode: VQRSHRNsv8i8 + /* 18427 */ MCD_OPC_FilterValue, + 1, + 60, + 1, + 0, // Skip to: 18748 + /* 18432 */ MCD_OPC_CheckPredicate, + 26, + 55, + 1, + 0, // Skip to: 18748 + /* 18437 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 48, + 1, + 0, // Skip to: 18748 + /* 18444 */ MCD_OPC_Decode, + 235, + 24, + 129, + 2, // Opcode: VQRSHRNuv8i8 + /* 18449 */ MCD_OPC_FilterValue, + 1, + 38, + 1, + 0, // Skip to: 18748 + /* 18454 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18457 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18472 + /* 18462 */ MCD_OPC_CheckPredicate, + 26, + 25, + 1, + 0, // Skip to: 18748 + /* 18467 */ MCD_OPC_Decode, + 231, + 24, + 130, + 2, // Opcode: VQRSHRNsv4i16 + /* 18472 */ MCD_OPC_FilterValue, + 1, + 15, + 1, + 0, // Skip to: 18748 + /* 18477 */ MCD_OPC_CheckPredicate, + 26, + 10, + 1, + 0, // Skip to: 18748 + /* 18482 */ MCD_OPC_Decode, + 234, + 24, + 130, + 2, // Opcode: VQRSHRNuv4i16 + /* 18487 */ MCD_OPC_FilterValue, + 1, + 0, + 1, + 0, // Skip to: 18748 + /* 18492 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18495 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18510 + /* 18500 */ MCD_OPC_CheckPredicate, + 26, + 243, + 0, + 0, // Skip to: 18748 + /* 18505 */ MCD_OPC_Decode, + 230, + 24, + 131, + 2, // Opcode: VQRSHRNsv2i32 + /* 18510 */ MCD_OPC_FilterValue, + 1, + 233, + 0, + 0, // Skip to: 18748 + /* 18515 */ MCD_OPC_CheckPredicate, + 26, + 228, + 0, + 0, // Skip to: 18748 + /* 18520 */ MCD_OPC_Decode, + 233, + 24, + 131, + 2, // Opcode: VQRSHRNuv2i32 + /* 18525 */ MCD_OPC_FilterValue, + 12, + 33, + 0, + 0, // Skip to: 18563 + /* 18530 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18533 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18548 + /* 18538 */ MCD_OPC_CheckPredicate, + 27, + 205, + 0, + 0, // Skip to: 18748 + /* 18543 */ MCD_OPC_Decode, + 153, + 18, + 153, + 2, // Opcode: VCVTxs2hq + /* 18548 */ MCD_OPC_FilterValue, + 1, + 195, + 0, + 0, // Skip to: 18748 + /* 18553 */ MCD_OPC_CheckPredicate, + 27, + 190, + 0, + 0, // Skip to: 18748 + /* 18558 */ MCD_OPC_Decode, + 157, + 18, + 153, + 2, // Opcode: VCVTxu2hq + /* 18563 */ MCD_OPC_FilterValue, + 13, + 33, + 0, + 0, // Skip to: 18601 + /* 18568 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18571 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18586 + /* 18576 */ MCD_OPC_CheckPredicate, + 27, + 167, + 0, + 0, // Skip to: 18748 + /* 18581 */ MCD_OPC_Decode, + 139, + 18, + 153, + 2, // Opcode: VCVTh2xsq + /* 18586 */ MCD_OPC_FilterValue, + 1, + 157, + 0, + 0, // Skip to: 18748 + /* 18591 */ MCD_OPC_CheckPredicate, + 27, + 152, + 0, + 0, // Skip to: 18748 + /* 18596 */ MCD_OPC_Decode, + 141, + 18, + 153, + 2, // Opcode: VCVTh2xuq + /* 18601 */ MCD_OPC_FilterValue, + 14, + 80, + 0, + 0, // Skip to: 18686 + /* 18606 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 18609 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18631 + /* 18614 */ MCD_OPC_CheckPredicate, + 26, + 34, + 0, + 0, // Skip to: 18653 + /* 18619 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 27, + 0, + 0, // Skip to: 18653 + /* 18626 */ MCD_OPC_Decode, + 240, + 22, + 136, + 2, // Opcode: VMOVv16i8 + /* 18631 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 18653 + /* 18636 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 18653 + /* 18641 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 5, + 0, + 0, // Skip to: 18653 + /* 18648 */ MCD_OPC_Decode, + 244, + 22, + 136, + 2, // Opcode: VMOVv2i64 + /* 18653 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18656 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18671 + /* 18661 */ MCD_OPC_CheckPredicate, + 26, + 82, + 0, + 0, // Skip to: 18748 + /* 18666 */ MCD_OPC_Decode, + 151, + 18, + 153, + 2, // Opcode: VCVTxs2fq + /* 18671 */ MCD_OPC_FilterValue, + 1, + 72, + 0, + 0, // Skip to: 18748 + /* 18676 */ MCD_OPC_CheckPredicate, + 26, + 67, + 0, + 0, // Skip to: 18748 + /* 18681 */ MCD_OPC_Decode, + 155, + 18, + 153, + 2, // Opcode: VCVTxu2fq + /* 18686 */ MCD_OPC_FilterValue, + 15, + 57, + 0, + 0, // Skip to: 18748 + /* 18691 */ MCD_OPC_ExtractField, + 24, + 1, // Inst{24} ... + /* 18694 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18709 + /* 18699 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 18724 + /* 18704 */ MCD_OPC_Decode, + 130, + 18, + 153, + 2, // Opcode: VCVTf2xsq + /* 18709 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 18724 + /* 18714 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 18724 + /* 18719 */ MCD_OPC_Decode, + 132, + 18, + 153, + 2, // Opcode: VCVTf2xuq + /* 18724 */ MCD_OPC_CheckPredicate, + 26, + 19, + 0, + 0, // Skip to: 18748 + /* 18729 */ MCD_OPC_CheckField, + 19, + 3, + 0, + 12, + 0, + 0, // Skip to: 18748 + /* 18736 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 18748 + /* 18743 */ MCD_OPC_Decode, + 245, + 22, + 136, + 2, // Opcode: VMOVv4f32 + /* 18748 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 18751 */ MCD_OPC_FilterValue, + 0, + 88, + 0, + 0, // Skip to: 18844 + /* 18756 */ MCD_OPC_ExtractField, + 19, + 3, // Inst{21-19} ... + /* 18759 */ MCD_OPC_FilterValue, + 0, + 211, + 1, + 0, // Skip to: 19231 + /* 18764 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 18767 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18789 + /* 18772 */ MCD_OPC_CheckPredicate, + 26, + 57, + 0, + 0, // Skip to: 18834 + /* 18777 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 18834 + /* 18784 */ MCD_OPC_Decode, + 248, + 22, + 136, + 2, // Opcode: VMOVv8i16 + /* 18789 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 18834 + /* 18794 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 18797 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18812 + /* 18802 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 18834 + /* 18807 */ MCD_OPC_Decode, + 213, + 23, + 136, + 2, // Opcode: VORRiv4i32 + /* 18812 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 18834 + /* 18817 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 18834 + /* 18822 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 18834 + /* 18829 */ MCD_OPC_Decode, + 214, + 23, + 136, + 2, // Opcode: VORRiv8i16 + /* 18834 */ MCD_OPC_CheckPredicate, + 26, + 136, + 1, + 0, // Skip to: 19231 + /* 18839 */ MCD_OPC_Decode, + 247, + 22, + 136, + 2, // Opcode: VMOVv4i32 + /* 18844 */ MCD_OPC_FilterValue, + 1, + 126, + 1, + 0, // Skip to: 19231 + /* 18849 */ MCD_OPC_ExtractField, + 19, + 3, // Inst{21-19} ... + /* 18852 */ MCD_OPC_FilterValue, + 0, + 118, + 1, + 0, // Skip to: 19231 + /* 18857 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 18860 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 18882 + /* 18865 */ MCD_OPC_CheckPredicate, + 26, + 57, + 0, + 0, // Skip to: 18927 + /* 18870 */ MCD_OPC_CheckField, + 10, + 2, + 2, + 50, + 0, + 0, // Skip to: 18927 + /* 18877 */ MCD_OPC_Decode, + 185, + 23, + 136, + 2, // Opcode: VMVNv8i16 + /* 18882 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 18927 + /* 18887 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 18890 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18905 + /* 18895 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 18927 + /* 18900 */ MCD_OPC_Decode, + 173, + 16, + 136, + 2, // Opcode: VBICiv4i32 + /* 18905 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 18927 + /* 18910 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 18927 + /* 18915 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 5, + 0, + 0, // Skip to: 18927 + /* 18922 */ MCD_OPC_Decode, + 174, + 16, + 136, + 2, // Opcode: VBICiv8i16 + /* 18927 */ MCD_OPC_CheckPredicate, + 26, + 43, + 1, + 0, // Skip to: 19231 + /* 18932 */ MCD_OPC_Decode, + 184, + 23, + 136, + 2, // Opcode: VMVNv4i32 + /* 18937 */ MCD_OPC_FilterValue, + 1, + 33, + 1, + 0, // Skip to: 19231 + /* 18942 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 18945 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 18985 + /* 18950 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 18953 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 18969 + /* 18959 */ MCD_OPC_CheckPredicate, + 26, + 11, + 1, + 0, // Skip to: 19231 + /* 18964 */ MCD_OPC_Decode, + 254, + 26, + 154, + 2, // Opcode: VSHRsv2i64 + /* 18969 */ MCD_OPC_FilterValue, + 243, + 1, + 0, + 1, + 0, // Skip to: 19231 + /* 18975 */ MCD_OPC_CheckPredicate, + 26, + 251, + 0, + 0, // Skip to: 19231 + /* 18980 */ MCD_OPC_Decode, + 134, + 27, + 154, + 2, // Opcode: VSHRuv2i64 + /* 18985 */ MCD_OPC_FilterValue, + 1, + 35, + 0, + 0, // Skip to: 19025 + /* 18990 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 18993 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19009 + /* 18999 */ MCD_OPC_CheckPredicate, + 26, + 227, + 0, + 0, // Skip to: 19231 + /* 19004 */ MCD_OPC_Decode, + 163, + 27, + 155, + 2, // Opcode: VSRAsv2i64 + /* 19009 */ MCD_OPC_FilterValue, + 243, + 1, + 216, + 0, + 0, // Skip to: 19231 + /* 19015 */ MCD_OPC_CheckPredicate, + 26, + 211, + 0, + 0, // Skip to: 19231 + /* 19020 */ MCD_OPC_Decode, + 171, + 27, + 155, + 2, // Opcode: VSRAuv2i64 + /* 19025 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 19065 + /* 19030 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 19033 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19049 + /* 19039 */ MCD_OPC_CheckPredicate, + 26, + 187, + 0, + 0, // Skip to: 19231 + /* 19044 */ MCD_OPC_Decode, + 152, + 26, + 154, + 2, // Opcode: VRSHRsv2i64 + /* 19049 */ MCD_OPC_FilterValue, + 243, + 1, + 176, + 0, + 0, // Skip to: 19231 + /* 19055 */ MCD_OPC_CheckPredicate, + 26, + 171, + 0, + 0, // Skip to: 19231 + /* 19060 */ MCD_OPC_Decode, + 160, + 26, + 154, + 2, // Opcode: VRSHRuv2i64 + /* 19065 */ MCD_OPC_FilterValue, + 3, + 35, + 0, + 0, // Skip to: 19105 + /* 19070 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 19073 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19089 + /* 19079 */ MCD_OPC_CheckPredicate, + 26, + 147, + 0, + 0, // Skip to: 19231 + /* 19084 */ MCD_OPC_Decode, + 178, + 26, + 155, + 2, // Opcode: VRSRAsv2i64 + /* 19089 */ MCD_OPC_FilterValue, + 243, + 1, + 136, + 0, + 0, // Skip to: 19231 + /* 19095 */ MCD_OPC_CheckPredicate, + 26, + 131, + 0, + 0, // Skip to: 19231 + /* 19100 */ MCD_OPC_Decode, + 186, + 26, + 155, + 2, // Opcode: VRSRAuv2i64 + /* 19105 */ MCD_OPC_FilterValue, + 4, + 18, + 0, + 0, // Skip to: 19128 + /* 19110 */ MCD_OPC_CheckPredicate, + 26, + 116, + 0, + 0, // Skip to: 19231 + /* 19115 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 108, + 0, + 0, // Skip to: 19231 + /* 19123 */ MCD_OPC_Decode, + 179, + 27, + 155, + 2, // Opcode: VSRIv2i64 + /* 19128 */ MCD_OPC_FilterValue, + 5, + 35, + 0, + 0, // Skip to: 19168 + /* 19133 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 19136 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19152 + /* 19142 */ MCD_OPC_CheckPredicate, + 26, + 84, + 0, + 0, // Skip to: 19231 + /* 19147 */ MCD_OPC_Decode, + 227, + 26, + 156, + 2, // Opcode: VSHLiv2i64 + /* 19152 */ MCD_OPC_FilterValue, + 243, + 1, + 73, + 0, + 0, // Skip to: 19231 + /* 19158 */ MCD_OPC_CheckPredicate, + 26, + 68, + 0, + 0, // Skip to: 19231 + /* 19163 */ MCD_OPC_Decode, + 148, + 27, + 157, + 2, // Opcode: VSLIv2i64 + /* 19168 */ MCD_OPC_FilterValue, + 6, + 18, + 0, + 0, // Skip to: 19191 + /* 19173 */ MCD_OPC_CheckPredicate, + 26, + 53, + 0, + 0, // Skip to: 19231 + /* 19178 */ MCD_OPC_CheckField, + 24, + 8, + 243, + 1, + 45, + 0, + 0, // Skip to: 19231 + /* 19186 */ MCD_OPC_Decode, + 250, + 24, + 156, + 2, // Opcode: VQSHLsuv2i64 + /* 19191 */ MCD_OPC_FilterValue, + 7, + 35, + 0, + 0, // Skip to: 19231 + /* 19196 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 19199 */ MCD_OPC_FilterValue, + 242, + 1, + 10, + 0, + 0, // Skip to: 19215 + /* 19205 */ MCD_OPC_CheckPredicate, + 26, + 21, + 0, + 0, // Skip to: 19231 + /* 19210 */ MCD_OPC_Decode, + 242, + 24, + 156, + 2, // Opcode: VQSHLsiv2i64 + /* 19215 */ MCD_OPC_FilterValue, + 243, + 1, + 10, + 0, + 0, // Skip to: 19231 + /* 19221 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 19231 + /* 19226 */ MCD_OPC_Decode, + 138, + 25, + 156, + 2, // Opcode: VQSHLuiv2i64 + /* 19231 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableNEONDup32[] = { -/* 0 */ MCD_OPC_ExtractField, 22, 6, // Inst{27-22} ... -/* 3 */ MCD_OPC_FilterValue, 56, 121, 0, 0, // Skip to: 129 -/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 11 */ MCD_OPC_FilterValue, 16, 61, 0, 0, // Skip to: 77 -/* 16 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 19 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 48 -/* 24 */ MCD_OPC_CheckPredicate, 27, 183, 1, 0, // Skip to: 468 -/* 29 */ MCD_OPC_CheckField, 8, 4, 11, 176, 1, 0, // Skip to: 468 -/* 36 */ MCD_OPC_CheckField, 6, 1, 0, 169, 1, 0, // Skip to: 468 -/* 43 */ MCD_OPC_Decode, 245, 17, 183, 1, // Opcode: VSETLNi32 -/* 48 */ MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 468 -/* 53 */ MCD_OPC_CheckPredicate, 27, 154, 1, 0, // Skip to: 468 -/* 58 */ MCD_OPC_CheckField, 8, 4, 11, 147, 1, 0, // Skip to: 468 -/* 65 */ MCD_OPC_CheckField, 6, 1, 0, 140, 1, 0, // Skip to: 468 -/* 72 */ MCD_OPC_Decode, 169, 10, 184, 1, // Opcode: VGETLNi32 -/* 77 */ MCD_OPC_FilterValue, 48, 130, 1, 0, // Skip to: 468 -/* 82 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 85 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 107 -/* 90 */ MCD_OPC_CheckPredicate, 21, 117, 1, 0, // Skip to: 468 -/* 95 */ MCD_OPC_CheckField, 8, 4, 11, 110, 1, 0, // Skip to: 468 -/* 102 */ MCD_OPC_Decode, 244, 17, 185, 1, // Opcode: VSETLNi16 -/* 107 */ MCD_OPC_FilterValue, 1, 100, 1, 0, // Skip to: 468 -/* 112 */ MCD_OPC_CheckPredicate, 21, 95, 1, 0, // Skip to: 468 -/* 117 */ MCD_OPC_CheckField, 8, 4, 11, 88, 1, 0, // Skip to: 468 -/* 124 */ MCD_OPC_Decode, 170, 10, 186, 1, // Opcode: VGETLNs16 -/* 129 */ MCD_OPC_FilterValue, 57, 61, 0, 0, // Skip to: 195 -/* 134 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 137 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 166 -/* 142 */ MCD_OPC_CheckPredicate, 21, 65, 1, 0, // Skip to: 468 -/* 147 */ MCD_OPC_CheckField, 8, 4, 11, 58, 1, 0, // Skip to: 468 -/* 154 */ MCD_OPC_CheckField, 0, 5, 16, 51, 1, 0, // Skip to: 468 -/* 161 */ MCD_OPC_Decode, 246, 17, 187, 1, // Opcode: VSETLNi8 -/* 166 */ MCD_OPC_FilterValue, 1, 41, 1, 0, // Skip to: 468 -/* 171 */ MCD_OPC_CheckPredicate, 21, 36, 1, 0, // Skip to: 468 -/* 176 */ MCD_OPC_CheckField, 8, 4, 11, 29, 1, 0, // Skip to: 468 -/* 183 */ MCD_OPC_CheckField, 0, 5, 16, 22, 1, 0, // Skip to: 468 -/* 190 */ MCD_OPC_Decode, 171, 10, 188, 1, // Opcode: VGETLNs8 -/* 195 */ MCD_OPC_FilterValue, 58, 165, 0, 0, // Skip to: 365 -/* 200 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 203 */ MCD_OPC_FilterValue, 16, 61, 0, 0, // Skip to: 269 -/* 208 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 211 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 240 -/* 216 */ MCD_OPC_CheckPredicate, 21, 247, 0, 0, // Skip to: 468 -/* 221 */ MCD_OPC_CheckField, 8, 4, 11, 240, 0, 0, // Skip to: 468 -/* 228 */ MCD_OPC_CheckField, 6, 1, 0, 233, 0, 0, // Skip to: 468 -/* 235 */ MCD_OPC_Decode, 130, 10, 189, 1, // Opcode: VDUP32d -/* 240 */ MCD_OPC_FilterValue, 2, 223, 0, 0, // Skip to: 468 -/* 245 */ MCD_OPC_CheckPredicate, 21, 218, 0, 0, // Skip to: 468 -/* 250 */ MCD_OPC_CheckField, 8, 4, 11, 211, 0, 0, // Skip to: 468 -/* 257 */ MCD_OPC_CheckField, 6, 1, 0, 204, 0, 0, // Skip to: 468 -/* 264 */ MCD_OPC_Decode, 131, 10, 190, 1, // Opcode: VDUP32q -/* 269 */ MCD_OPC_FilterValue, 48, 194, 0, 0, // Skip to: 468 -/* 274 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 277 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 343 -/* 282 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 285 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 314 -/* 290 */ MCD_OPC_CheckPredicate, 21, 173, 0, 0, // Skip to: 468 -/* 295 */ MCD_OPC_CheckField, 8, 4, 11, 166, 0, 0, // Skip to: 468 -/* 302 */ MCD_OPC_CheckField, 6, 1, 0, 159, 0, 0, // Skip to: 468 -/* 309 */ MCD_OPC_Decode, 128, 10, 189, 1, // Opcode: VDUP16d -/* 314 */ MCD_OPC_FilterValue, 1, 149, 0, 0, // Skip to: 468 -/* 319 */ MCD_OPC_CheckPredicate, 21, 144, 0, 0, // Skip to: 468 -/* 324 */ MCD_OPC_CheckField, 8, 4, 11, 137, 0, 0, // Skip to: 468 -/* 331 */ MCD_OPC_CheckField, 6, 1, 0, 130, 0, 0, // Skip to: 468 -/* 338 */ MCD_OPC_Decode, 129, 10, 190, 1, // Opcode: VDUP16q -/* 343 */ MCD_OPC_FilterValue, 1, 120, 0, 0, // Skip to: 468 -/* 348 */ MCD_OPC_CheckPredicate, 21, 115, 0, 0, // Skip to: 468 -/* 353 */ MCD_OPC_CheckField, 8, 4, 11, 108, 0, 0, // Skip to: 468 -/* 360 */ MCD_OPC_Decode, 172, 10, 186, 1, // Opcode: VGETLNu16 -/* 365 */ MCD_OPC_FilterValue, 59, 98, 0, 0, // Skip to: 468 -/* 370 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 373 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 439 -/* 378 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 381 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 410 -/* 386 */ MCD_OPC_CheckPredicate, 21, 77, 0, 0, // Skip to: 468 -/* 391 */ MCD_OPC_CheckField, 8, 4, 11, 70, 0, 0, // Skip to: 468 -/* 398 */ MCD_OPC_CheckField, 0, 7, 16, 63, 0, 0, // Skip to: 468 -/* 405 */ MCD_OPC_Decode, 132, 10, 189, 1, // Opcode: VDUP8d -/* 410 */ MCD_OPC_FilterValue, 1, 53, 0, 0, // Skip to: 468 -/* 415 */ MCD_OPC_CheckPredicate, 21, 48, 0, 0, // Skip to: 468 -/* 420 */ MCD_OPC_CheckField, 8, 4, 11, 41, 0, 0, // Skip to: 468 -/* 427 */ MCD_OPC_CheckField, 0, 7, 16, 34, 0, 0, // Skip to: 468 -/* 434 */ MCD_OPC_Decode, 133, 10, 190, 1, // Opcode: VDUP8q -/* 439 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 468 -/* 444 */ MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 468 -/* 449 */ MCD_OPC_CheckField, 8, 4, 11, 12, 0, 0, // Skip to: 468 -/* 456 */ MCD_OPC_CheckField, 0, 5, 16, 5, 0, 0, // Skip to: 468 -/* 463 */ MCD_OPC_Decode, 173, 10, 188, 1, // Opcode: VGETLNu8 -/* 468 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 22, + 6, // Inst{27-22} ... + /* 3 */ MCD_OPC_FilterValue, + 56, + 121, + 0, + 0, // Skip to: 129 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 16, + 61, + 0, + 0, // Skip to: 77 + /* 16 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 48 + /* 24 */ MCD_OPC_CheckPredicate, + 33, + 183, + 1, + 0, // Skip to: 468 + /* 29 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 176, + 1, + 0, // Skip to: 468 + /* 36 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 169, + 1, + 0, // Skip to: 468 + /* 43 */ MCD_OPC_Decode, + 213, + 26, + 158, + 2, // Opcode: VSETLNi32 + /* 48 */ MCD_OPC_FilterValue, + 1, + 159, + 1, + 0, // Skip to: 468 + /* 53 */ MCD_OPC_CheckPredicate, + 34, + 154, + 1, + 0, // Skip to: 468 + /* 58 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 147, + 1, + 0, // Skip to: 468 + /* 65 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 140, + 1, + 0, // Skip to: 468 + /* 72 */ MCD_OPC_Decode, + 216, + 18, + 159, + 2, // Opcode: VGETLNi32 + /* 77 */ MCD_OPC_FilterValue, + 48, + 130, + 1, + 0, // Skip to: 468 + /* 82 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 85 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 107 + /* 90 */ MCD_OPC_CheckPredicate, + 26, + 117, + 1, + 0, // Skip to: 468 + /* 95 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 110, + 1, + 0, // Skip to: 468 + /* 102 */ MCD_OPC_Decode, + 212, + 26, + 160, + 2, // Opcode: VSETLNi16 + /* 107 */ MCD_OPC_FilterValue, + 1, + 100, + 1, + 0, // Skip to: 468 + /* 112 */ MCD_OPC_CheckPredicate, + 26, + 95, + 1, + 0, // Skip to: 468 + /* 117 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 88, + 1, + 0, // Skip to: 468 + /* 124 */ MCD_OPC_Decode, + 217, + 18, + 161, + 2, // Opcode: VGETLNs16 + /* 129 */ MCD_OPC_FilterValue, + 57, + 61, + 0, + 0, // Skip to: 195 + /* 134 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 137 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 166 + /* 142 */ MCD_OPC_CheckPredicate, + 26, + 65, + 1, + 0, // Skip to: 468 + /* 147 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 58, + 1, + 0, // Skip to: 468 + /* 154 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 51, + 1, + 0, // Skip to: 468 + /* 161 */ MCD_OPC_Decode, + 214, + 26, + 162, + 2, // Opcode: VSETLNi8 + /* 166 */ MCD_OPC_FilterValue, + 1, + 41, + 1, + 0, // Skip to: 468 + /* 171 */ MCD_OPC_CheckPredicate, + 26, + 36, + 1, + 0, // Skip to: 468 + /* 176 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 29, + 1, + 0, // Skip to: 468 + /* 183 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 22, + 1, + 0, // Skip to: 468 + /* 190 */ MCD_OPC_Decode, + 218, + 18, + 163, + 2, // Opcode: VGETLNs8 + /* 195 */ MCD_OPC_FilterValue, + 58, + 165, + 0, + 0, // Skip to: 365 + /* 200 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 203 */ MCD_OPC_FilterValue, + 16, + 61, + 0, + 0, // Skip to: 269 + /* 208 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 211 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 240 + /* 216 */ MCD_OPC_CheckPredicate, + 26, + 247, + 0, + 0, // Skip to: 468 + /* 221 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 240, + 0, + 0, // Skip to: 468 + /* 228 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 233, + 0, + 0, // Skip to: 468 + /* 235 */ MCD_OPC_Decode, + 163, + 18, + 164, + 2, // Opcode: VDUP32d + /* 240 */ MCD_OPC_FilterValue, + 2, + 223, + 0, + 0, // Skip to: 468 + /* 245 */ MCD_OPC_CheckPredicate, + 26, + 218, + 0, + 0, // Skip to: 468 + /* 250 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 211, + 0, + 0, // Skip to: 468 + /* 257 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 204, + 0, + 0, // Skip to: 468 + /* 264 */ MCD_OPC_Decode, + 164, + 18, + 165, + 2, // Opcode: VDUP32q + /* 269 */ MCD_OPC_FilterValue, + 48, + 194, + 0, + 0, // Skip to: 468 + /* 274 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 277 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 343 + /* 282 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 285 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 314 + /* 290 */ MCD_OPC_CheckPredicate, + 26, + 173, + 0, + 0, // Skip to: 468 + /* 295 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 166, + 0, + 0, // Skip to: 468 + /* 302 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 159, + 0, + 0, // Skip to: 468 + /* 309 */ MCD_OPC_Decode, + 161, + 18, + 164, + 2, // Opcode: VDUP16d + /* 314 */ MCD_OPC_FilterValue, + 1, + 149, + 0, + 0, // Skip to: 468 + /* 319 */ MCD_OPC_CheckPredicate, + 26, + 144, + 0, + 0, // Skip to: 468 + /* 324 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 137, + 0, + 0, // Skip to: 468 + /* 331 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 130, + 0, + 0, // Skip to: 468 + /* 338 */ MCD_OPC_Decode, + 162, + 18, + 165, + 2, // Opcode: VDUP16q + /* 343 */ MCD_OPC_FilterValue, + 1, + 120, + 0, + 0, // Skip to: 468 + /* 348 */ MCD_OPC_CheckPredicate, + 26, + 115, + 0, + 0, // Skip to: 468 + /* 353 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 108, + 0, + 0, // Skip to: 468 + /* 360 */ MCD_OPC_Decode, + 219, + 18, + 161, + 2, // Opcode: VGETLNu16 + /* 365 */ MCD_OPC_FilterValue, + 59, + 98, + 0, + 0, // Skip to: 468 + /* 370 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 373 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 439 + /* 378 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 381 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 410 + /* 386 */ MCD_OPC_CheckPredicate, + 26, + 77, + 0, + 0, // Skip to: 468 + /* 391 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 70, + 0, + 0, // Skip to: 468 + /* 398 */ MCD_OPC_CheckField, + 0, + 7, + 16, + 63, + 0, + 0, // Skip to: 468 + /* 405 */ MCD_OPC_Decode, + 165, + 18, + 164, + 2, // Opcode: VDUP8d + /* 410 */ MCD_OPC_FilterValue, + 1, + 53, + 0, + 0, // Skip to: 468 + /* 415 */ MCD_OPC_CheckPredicate, + 26, + 48, + 0, + 0, // Skip to: 468 + /* 420 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 41, + 0, + 0, // Skip to: 468 + /* 427 */ MCD_OPC_CheckField, + 0, + 7, + 16, + 34, + 0, + 0, // Skip to: 468 + /* 434 */ MCD_OPC_Decode, + 166, + 18, + 165, + 2, // Opcode: VDUP8q + /* 439 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 468 + /* 444 */ MCD_OPC_CheckPredicate, + 26, + 19, + 0, + 0, // Skip to: 468 + /* 449 */ MCD_OPC_CheckField, + 8, + 4, + 11, + 12, + 0, + 0, // Skip to: 468 + /* 456 */ MCD_OPC_CheckField, + 0, + 5, + 16, + 5, + 0, + 0, // Skip to: 468 + /* 463 */ MCD_OPC_Decode, + 220, + 18, + 163, + 2, // Opcode: VGETLNu8 + /* 468 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableNEONLoadStore32[] = { -/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 3 */ MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 319 -/* 8 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 11 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 165 -/* 16 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 19 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 124 -/* 25 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 28 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 60 -/* 33 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 50 -/* 38 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 50 -/* 45 */ MCD_OPC_Decode, 178, 20, 191, 1, // Opcode: VST4d8 -/* 50 */ MCD_OPC_CheckPredicate, 21, 246, 25, 0, // Skip to: 6701 -/* 55 */ MCD_OPC_Decode, 181, 20, 191, 1, // Opcode: VST4d8_UPD -/* 60 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 92 -/* 65 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 82 -/* 70 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 82 -/* 77 */ MCD_OPC_Decode, 170, 20, 191, 1, // Opcode: VST4d16 -/* 82 */ MCD_OPC_CheckPredicate, 21, 214, 25, 0, // Skip to: 6701 -/* 87 */ MCD_OPC_Decode, 173, 20, 191, 1, // Opcode: VST4d16_UPD -/* 92 */ MCD_OPC_FilterValue, 2, 204, 25, 0, // Skip to: 6701 -/* 97 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 114 -/* 102 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 114 -/* 109 */ MCD_OPC_Decode, 174, 20, 191, 1, // Opcode: VST4d32 -/* 114 */ MCD_OPC_CheckPredicate, 21, 182, 25, 0, // Skip to: 6701 -/* 119 */ MCD_OPC_Decode, 177, 20, 191, 1, // Opcode: VST4d32_UPD -/* 124 */ MCD_OPC_FilterValue, 233, 3, 171, 25, 0, // Skip to: 6701 -/* 130 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 133 */ MCD_OPC_FilterValue, 0, 163, 25, 0, // Skip to: 6701 -/* 138 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 155 -/* 143 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 155 -/* 150 */ MCD_OPC_Decode, 219, 18, 192, 1, // Opcode: VST1LNd8 -/* 155 */ MCD_OPC_CheckPredicate, 21, 141, 25, 0, // Skip to: 6701 -/* 160 */ MCD_OPC_Decode, 220, 18, 192, 1, // Opcode: VST1LNd8_UPD -/* 165 */ MCD_OPC_FilterValue, 2, 131, 25, 0, // Skip to: 6701 -/* 170 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 173 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 278 -/* 179 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 182 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 214 -/* 187 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 204 -/* 192 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 204 -/* 199 */ MCD_OPC_Decode, 253, 12, 191, 1, // Opcode: VLD4d8 -/* 204 */ MCD_OPC_CheckPredicate, 21, 92, 25, 0, // Skip to: 6701 -/* 209 */ MCD_OPC_Decode, 128, 13, 191, 1, // Opcode: VLD4d8_UPD -/* 214 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 246 -/* 219 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 236 -/* 224 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 236 -/* 231 */ MCD_OPC_Decode, 245, 12, 191, 1, // Opcode: VLD4d16 -/* 236 */ MCD_OPC_CheckPredicate, 21, 60, 25, 0, // Skip to: 6701 -/* 241 */ MCD_OPC_Decode, 248, 12, 191, 1, // Opcode: VLD4d16_UPD -/* 246 */ MCD_OPC_FilterValue, 2, 50, 25, 0, // Skip to: 6701 -/* 251 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 268 -/* 256 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 268 -/* 263 */ MCD_OPC_Decode, 249, 12, 191, 1, // Opcode: VLD4d32 -/* 268 */ MCD_OPC_CheckPredicate, 21, 28, 25, 0, // Skip to: 6701 -/* 273 */ MCD_OPC_Decode, 252, 12, 191, 1, // Opcode: VLD4d32_UPD -/* 278 */ MCD_OPC_FilterValue, 233, 3, 17, 25, 0, // Skip to: 6701 -/* 284 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 287 */ MCD_OPC_FilterValue, 0, 9, 25, 0, // Skip to: 6701 -/* 292 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 309 -/* 297 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 309 -/* 304 */ MCD_OPC_Decode, 222, 10, 193, 1, // Opcode: VLD1LNd8 -/* 309 */ MCD_OPC_CheckPredicate, 21, 243, 24, 0, // Skip to: 6701 -/* 314 */ MCD_OPC_Decode, 223, 10, 193, 1, // Opcode: VLD1LNd8_UPD -/* 319 */ MCD_OPC_FilterValue, 1, 39, 1, 0, // Skip to: 619 -/* 324 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 327 */ MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 473 -/* 332 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 335 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 440 -/* 341 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 344 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 376 -/* 349 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 366 -/* 354 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 366 -/* 361 */ MCD_OPC_Decode, 192, 20, 191, 1, // Opcode: VST4q8 -/* 366 */ MCD_OPC_CheckPredicate, 21, 186, 24, 0, // Skip to: 6701 -/* 371 */ MCD_OPC_Decode, 194, 20, 191, 1, // Opcode: VST4q8_UPD -/* 376 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 408 -/* 381 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 398 -/* 386 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 398 -/* 393 */ MCD_OPC_Decode, 182, 20, 191, 1, // Opcode: VST4q16 -/* 398 */ MCD_OPC_CheckPredicate, 21, 154, 24, 0, // Skip to: 6701 -/* 403 */ MCD_OPC_Decode, 184, 20, 191, 1, // Opcode: VST4q16_UPD -/* 408 */ MCD_OPC_FilterValue, 2, 144, 24, 0, // Skip to: 6701 -/* 413 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 430 -/* 418 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 430 -/* 425 */ MCD_OPC_Decode, 187, 20, 191, 1, // Opcode: VST4q32 -/* 430 */ MCD_OPC_CheckPredicate, 21, 122, 24, 0, // Skip to: 6701 -/* 435 */ MCD_OPC_Decode, 189, 20, 191, 1, // Opcode: VST4q32_UPD -/* 440 */ MCD_OPC_FilterValue, 233, 3, 111, 24, 0, // Skip to: 6701 -/* 446 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 463 -/* 451 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 463 -/* 458 */ MCD_OPC_Decode, 183, 19, 194, 1, // Opcode: VST2LNd8 -/* 463 */ MCD_OPC_CheckPredicate, 21, 89, 24, 0, // Skip to: 6701 -/* 468 */ MCD_OPC_Decode, 186, 19, 194, 1, // Opcode: VST2LNd8_UPD -/* 473 */ MCD_OPC_FilterValue, 2, 79, 24, 0, // Skip to: 6701 -/* 478 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 481 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 586 -/* 487 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 490 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 522 -/* 495 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 512 -/* 500 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 512 -/* 507 */ MCD_OPC_Decode, 139, 13, 191, 1, // Opcode: VLD4q8 -/* 512 */ MCD_OPC_CheckPredicate, 21, 40, 24, 0, // Skip to: 6701 -/* 517 */ MCD_OPC_Decode, 141, 13, 191, 1, // Opcode: VLD4q8_UPD -/* 522 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 554 -/* 527 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 544 -/* 532 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 544 -/* 539 */ MCD_OPC_Decode, 129, 13, 191, 1, // Opcode: VLD4q16 -/* 544 */ MCD_OPC_CheckPredicate, 21, 8, 24, 0, // Skip to: 6701 -/* 549 */ MCD_OPC_Decode, 131, 13, 191, 1, // Opcode: VLD4q16_UPD -/* 554 */ MCD_OPC_FilterValue, 2, 254, 23, 0, // Skip to: 6701 -/* 559 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 576 -/* 564 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 576 -/* 571 */ MCD_OPC_Decode, 134, 13, 191, 1, // Opcode: VLD4q32 -/* 576 */ MCD_OPC_CheckPredicate, 21, 232, 23, 0, // Skip to: 6701 -/* 581 */ MCD_OPC_Decode, 136, 13, 191, 1, // Opcode: VLD4q32_UPD -/* 586 */ MCD_OPC_FilterValue, 233, 3, 221, 23, 0, // Skip to: 6701 -/* 592 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 609 -/* 597 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 609 -/* 604 */ MCD_OPC_Decode, 210, 11, 195, 1, // Opcode: VLD2LNd8 -/* 609 */ MCD_OPC_CheckPredicate, 21, 199, 23, 0, // Skip to: 6701 -/* 614 */ MCD_OPC_Decode, 213, 11, 195, 1, // Opcode: VLD2LNd8_UPD -/* 619 */ MCD_OPC_FilterValue, 2, 247, 1, 0, // Skip to: 1127 -/* 624 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 627 */ MCD_OPC_FilterValue, 0, 245, 0, 0, // Skip to: 877 -/* 632 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 635 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 836 -/* 641 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 644 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 692 -/* 649 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 652 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 667 -/* 657 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 682 -/* 662 */ MCD_OPC_Decode, 139, 19, 196, 1, // Opcode: VST1d8Qwb_fixed -/* 667 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 682 -/* 672 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 682 -/* 677 */ MCD_OPC_Decode, 137, 19, 196, 1, // Opcode: VST1d8Q -/* 682 */ MCD_OPC_CheckPredicate, 21, 126, 23, 0, // Skip to: 6701 -/* 687 */ MCD_OPC_Decode, 140, 19, 196, 1, // Opcode: VST1d8Qwb_register -/* 692 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 740 -/* 697 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 700 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 715 -/* 705 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 730 -/* 710 */ MCD_OPC_Decode, 230, 18, 196, 1, // Opcode: VST1d16Qwb_fixed -/* 715 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 730 -/* 720 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 730 -/* 725 */ MCD_OPC_Decode, 228, 18, 196, 1, // Opcode: VST1d16Q -/* 730 */ MCD_OPC_CheckPredicate, 21, 78, 23, 0, // Skip to: 6701 -/* 735 */ MCD_OPC_Decode, 231, 18, 196, 1, // Opcode: VST1d16Qwb_register -/* 740 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 788 -/* 745 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 748 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 763 -/* 753 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 778 -/* 758 */ MCD_OPC_Decode, 241, 18, 196, 1, // Opcode: VST1d32Qwb_fixed -/* 763 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 778 -/* 768 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 778 -/* 773 */ MCD_OPC_Decode, 239, 18, 196, 1, // Opcode: VST1d32Q -/* 778 */ MCD_OPC_CheckPredicate, 21, 30, 23, 0, // Skip to: 6701 -/* 783 */ MCD_OPC_Decode, 242, 18, 196, 1, // Opcode: VST1d32Qwb_register -/* 788 */ MCD_OPC_FilterValue, 3, 20, 23, 0, // Skip to: 6701 -/* 793 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 796 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 811 -/* 801 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 826 -/* 806 */ MCD_OPC_Decode, 254, 18, 196, 1, // Opcode: VST1d64Qwb_fixed -/* 811 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 826 -/* 816 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 826 -/* 821 */ MCD_OPC_Decode, 250, 18, 196, 1, // Opcode: VST1d64Q -/* 826 */ MCD_OPC_CheckPredicate, 21, 238, 22, 0, // Skip to: 6701 -/* 831 */ MCD_OPC_Decode, 255, 18, 196, 1, // Opcode: VST1d64Qwb_register -/* 836 */ MCD_OPC_FilterValue, 233, 3, 227, 22, 0, // Skip to: 6701 -/* 842 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 845 */ MCD_OPC_FilterValue, 0, 219, 22, 0, // Skip to: 6701 -/* 850 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 867 -/* 855 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 867 -/* 862 */ MCD_OPC_Decode, 239, 19, 197, 1, // Opcode: VST3LNd8 -/* 867 */ MCD_OPC_CheckPredicate, 21, 197, 22, 0, // Skip to: 6701 -/* 872 */ MCD_OPC_Decode, 242, 19, 197, 1, // Opcode: VST3LNd8_UPD -/* 877 */ MCD_OPC_FilterValue, 2, 187, 22, 0, // Skip to: 6701 -/* 882 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 885 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 1086 -/* 891 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 894 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 942 -/* 899 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 902 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 917 -/* 907 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 932 -/* 912 */ MCD_OPC_Decode, 142, 11, 196, 1, // Opcode: VLD1d8Qwb_fixed -/* 917 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 932 -/* 922 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 932 -/* 927 */ MCD_OPC_Decode, 140, 11, 196, 1, // Opcode: VLD1d8Q -/* 932 */ MCD_OPC_CheckPredicate, 21, 132, 22, 0, // Skip to: 6701 -/* 937 */ MCD_OPC_Decode, 143, 11, 196, 1, // Opcode: VLD1d8Qwb_register -/* 942 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 990 -/* 947 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 950 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 965 -/* 955 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 980 -/* 960 */ MCD_OPC_Decode, 233, 10, 196, 1, // Opcode: VLD1d16Qwb_fixed -/* 965 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 980 -/* 970 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 980 -/* 975 */ MCD_OPC_Decode, 231, 10, 196, 1, // Opcode: VLD1d16Q -/* 980 */ MCD_OPC_CheckPredicate, 21, 84, 22, 0, // Skip to: 6701 -/* 985 */ MCD_OPC_Decode, 234, 10, 196, 1, // Opcode: VLD1d16Qwb_register -/* 990 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 1038 -/* 995 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 998 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1013 -/* 1003 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1028 -/* 1008 */ MCD_OPC_Decode, 244, 10, 196, 1, // Opcode: VLD1d32Qwb_fixed -/* 1013 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1028 -/* 1018 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1028 -/* 1023 */ MCD_OPC_Decode, 242, 10, 196, 1, // Opcode: VLD1d32Q -/* 1028 */ MCD_OPC_CheckPredicate, 21, 36, 22, 0, // Skip to: 6701 -/* 1033 */ MCD_OPC_Decode, 245, 10, 196, 1, // Opcode: VLD1d32Qwb_register -/* 1038 */ MCD_OPC_FilterValue, 3, 26, 22, 0, // Skip to: 6701 -/* 1043 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 1046 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1061 -/* 1051 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1076 -/* 1056 */ MCD_OPC_Decode, 129, 11, 196, 1, // Opcode: VLD1d64Qwb_fixed -/* 1061 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1076 -/* 1066 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1076 -/* 1071 */ MCD_OPC_Decode, 253, 10, 196, 1, // Opcode: VLD1d64Q -/* 1076 */ MCD_OPC_CheckPredicate, 21, 244, 21, 0, // Skip to: 6701 -/* 1081 */ MCD_OPC_Decode, 130, 11, 196, 1, // Opcode: VLD1d64Qwb_register -/* 1086 */ MCD_OPC_FilterValue, 233, 3, 233, 21, 0, // Skip to: 6701 -/* 1092 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1095 */ MCD_OPC_FilterValue, 0, 225, 21, 0, // Skip to: 6701 -/* 1100 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1117 -/* 1105 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1117 -/* 1112 */ MCD_OPC_Decode, 162, 12, 198, 1, // Opcode: VLD3LNd8 -/* 1117 */ MCD_OPC_CheckPredicate, 21, 203, 21, 0, // Skip to: 6701 -/* 1122 */ MCD_OPC_Decode, 165, 12, 198, 1, // Opcode: VLD3LNd8_UPD -/* 1127 */ MCD_OPC_FilterValue, 3, 135, 1, 0, // Skip to: 1523 -/* 1132 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 1135 */ MCD_OPC_FilterValue, 0, 189, 0, 0, // Skip to: 1329 -/* 1140 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1143 */ MCD_OPC_FilterValue, 232, 3, 147, 0, 0, // Skip to: 1296 -/* 1149 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 1152 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 1200 -/* 1157 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 1160 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1175 -/* 1165 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1190 -/* 1170 */ MCD_OPC_Decode, 229, 19, 199, 1, // Opcode: VST2q8wb_fixed -/* 1175 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1190 -/* 1180 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1190 -/* 1185 */ MCD_OPC_Decode, 225, 19, 199, 1, // Opcode: VST2q8 -/* 1190 */ MCD_OPC_CheckPredicate, 21, 130, 21, 0, // Skip to: 6701 -/* 1195 */ MCD_OPC_Decode, 230, 19, 199, 1, // Opcode: VST2q8wb_register -/* 1200 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 1248 -/* 1205 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 1208 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1223 -/* 1213 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1238 -/* 1218 */ MCD_OPC_Decode, 217, 19, 199, 1, // Opcode: VST2q16wb_fixed -/* 1223 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1238 -/* 1228 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1238 -/* 1233 */ MCD_OPC_Decode, 213, 19, 199, 1, // Opcode: VST2q16 -/* 1238 */ MCD_OPC_CheckPredicate, 21, 82, 21, 0, // Skip to: 6701 -/* 1243 */ MCD_OPC_Decode, 218, 19, 199, 1, // Opcode: VST2q16wb_register -/* 1248 */ MCD_OPC_FilterValue, 2, 72, 21, 0, // Skip to: 6701 -/* 1253 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 1256 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1271 -/* 1261 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1286 -/* 1266 */ MCD_OPC_Decode, 223, 19, 199, 1, // Opcode: VST2q32wb_fixed -/* 1271 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1286 -/* 1276 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1286 -/* 1281 */ MCD_OPC_Decode, 219, 19, 199, 1, // Opcode: VST2q32 -/* 1286 */ MCD_OPC_CheckPredicate, 21, 34, 21, 0, // Skip to: 6701 -/* 1291 */ MCD_OPC_Decode, 224, 19, 199, 1, // Opcode: VST2q32wb_register -/* 1296 */ MCD_OPC_FilterValue, 233, 3, 23, 21, 0, // Skip to: 6701 -/* 1302 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1319 -/* 1307 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1319 -/* 1314 */ MCD_OPC_Decode, 158, 20, 200, 1, // Opcode: VST4LNd8 -/* 1319 */ MCD_OPC_CheckPredicate, 21, 1, 21, 0, // Skip to: 6701 -/* 1324 */ MCD_OPC_Decode, 161, 20, 200, 1, // Opcode: VST4LNd8_UPD -/* 1329 */ MCD_OPC_FilterValue, 2, 247, 20, 0, // Skip to: 6701 -/* 1334 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1337 */ MCD_OPC_FilterValue, 232, 3, 147, 0, 0, // Skip to: 1490 -/* 1343 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 1346 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 1394 -/* 1351 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 1354 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1369 -/* 1359 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1384 -/* 1364 */ MCD_OPC_Decode, 128, 12, 199, 1, // Opcode: VLD2q8wb_fixed -/* 1369 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1384 -/* 1374 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1384 -/* 1379 */ MCD_OPC_Decode, 252, 11, 199, 1, // Opcode: VLD2q8 -/* 1384 */ MCD_OPC_CheckPredicate, 21, 192, 20, 0, // Skip to: 6701 -/* 1389 */ MCD_OPC_Decode, 129, 12, 199, 1, // Opcode: VLD2q8wb_register -/* 1394 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 1442 -/* 1399 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 1402 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1417 -/* 1407 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1432 -/* 1412 */ MCD_OPC_Decode, 244, 11, 199, 1, // Opcode: VLD2q16wb_fixed -/* 1417 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1432 -/* 1422 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1432 -/* 1427 */ MCD_OPC_Decode, 240, 11, 199, 1, // Opcode: VLD2q16 -/* 1432 */ MCD_OPC_CheckPredicate, 21, 144, 20, 0, // Skip to: 6701 -/* 1437 */ MCD_OPC_Decode, 245, 11, 199, 1, // Opcode: VLD2q16wb_register -/* 1442 */ MCD_OPC_FilterValue, 2, 134, 20, 0, // Skip to: 6701 -/* 1447 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 1450 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1465 -/* 1455 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1480 -/* 1460 */ MCD_OPC_Decode, 250, 11, 199, 1, // Opcode: VLD2q32wb_fixed -/* 1465 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1480 -/* 1470 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1480 -/* 1475 */ MCD_OPC_Decode, 246, 11, 199, 1, // Opcode: VLD2q32 -/* 1480 */ MCD_OPC_CheckPredicate, 21, 96, 20, 0, // Skip to: 6701 -/* 1485 */ MCD_OPC_Decode, 251, 11, 199, 1, // Opcode: VLD2q32wb_register -/* 1490 */ MCD_OPC_FilterValue, 233, 3, 85, 20, 0, // Skip to: 6701 -/* 1496 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1513 -/* 1501 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1513 -/* 1508 */ MCD_OPC_Decode, 233, 12, 201, 1, // Opcode: VLD4LNd8 -/* 1513 */ MCD_OPC_CheckPredicate, 21, 63, 20, 0, // Skip to: 6701 -/* 1518 */ MCD_OPC_Decode, 236, 12, 201, 1, // Opcode: VLD4LNd8_UPD -/* 1523 */ MCD_OPC_FilterValue, 4, 54, 1, 0, // Skip to: 1838 -/* 1528 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 1531 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 1685 -/* 1536 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1539 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1644 -/* 1545 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... -/* 1548 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1580 -/* 1553 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1570 -/* 1558 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1570 -/* 1565 */ MCD_OPC_Decode, 131, 20, 202, 1, // Opcode: VST3d8 -/* 1570 */ MCD_OPC_CheckPredicate, 21, 6, 20, 0, // Skip to: 6701 -/* 1575 */ MCD_OPC_Decode, 134, 20, 202, 1, // Opcode: VST3d8_UPD -/* 1580 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 1612 -/* 1585 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1602 -/* 1590 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1602 -/* 1597 */ MCD_OPC_Decode, 251, 19, 202, 1, // Opcode: VST3d16 -/* 1602 */ MCD_OPC_CheckPredicate, 21, 230, 19, 0, // Skip to: 6701 -/* 1607 */ MCD_OPC_Decode, 254, 19, 202, 1, // Opcode: VST3d16_UPD -/* 1612 */ MCD_OPC_FilterValue, 4, 220, 19, 0, // Skip to: 6701 -/* 1617 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1634 -/* 1622 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1634 -/* 1629 */ MCD_OPC_Decode, 255, 19, 202, 1, // Opcode: VST3d32 -/* 1634 */ MCD_OPC_CheckPredicate, 21, 198, 19, 0, // Skip to: 6701 -/* 1639 */ MCD_OPC_Decode, 130, 20, 202, 1, // Opcode: VST3d32_UPD -/* 1644 */ MCD_OPC_FilterValue, 233, 3, 187, 19, 0, // Skip to: 6701 -/* 1650 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 1653 */ MCD_OPC_FilterValue, 0, 179, 19, 0, // Skip to: 6701 -/* 1658 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1675 -/* 1663 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1675 -/* 1670 */ MCD_OPC_Decode, 215, 18, 192, 1, // Opcode: VST1LNd16 -/* 1675 */ MCD_OPC_CheckPredicate, 21, 157, 19, 0, // Skip to: 6701 -/* 1680 */ MCD_OPC_Decode, 216, 18, 192, 1, // Opcode: VST1LNd16_UPD -/* 1685 */ MCD_OPC_FilterValue, 2, 147, 19, 0, // Skip to: 6701 -/* 1690 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1693 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1798 -/* 1699 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... -/* 1702 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1734 -/* 1707 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1724 -/* 1712 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1724 -/* 1719 */ MCD_OPC_Decode, 182, 12, 202, 1, // Opcode: VLD3d8 -/* 1724 */ MCD_OPC_CheckPredicate, 21, 108, 19, 0, // Skip to: 6701 -/* 1729 */ MCD_OPC_Decode, 185, 12, 202, 1, // Opcode: VLD3d8_UPD -/* 1734 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 1766 -/* 1739 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1756 -/* 1744 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1756 -/* 1751 */ MCD_OPC_Decode, 174, 12, 202, 1, // Opcode: VLD3d16 -/* 1756 */ MCD_OPC_CheckPredicate, 21, 76, 19, 0, // Skip to: 6701 -/* 1761 */ MCD_OPC_Decode, 177, 12, 202, 1, // Opcode: VLD3d16_UPD -/* 1766 */ MCD_OPC_FilterValue, 4, 66, 19, 0, // Skip to: 6701 -/* 1771 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1788 -/* 1776 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1788 -/* 1783 */ MCD_OPC_Decode, 178, 12, 202, 1, // Opcode: VLD3d32 -/* 1788 */ MCD_OPC_CheckPredicate, 21, 44, 19, 0, // Skip to: 6701 -/* 1793 */ MCD_OPC_Decode, 181, 12, 202, 1, // Opcode: VLD3d32_UPD -/* 1798 */ MCD_OPC_FilterValue, 233, 3, 33, 19, 0, // Skip to: 6701 -/* 1804 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1821 -/* 1809 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1821 -/* 1816 */ MCD_OPC_Decode, 218, 10, 193, 1, // Opcode: VLD1LNd16 -/* 1821 */ MCD_OPC_CheckPredicate, 21, 11, 19, 0, // Skip to: 6701 -/* 1826 */ MCD_OPC_CheckField, 5, 1, 0, 4, 19, 0, // Skip to: 6701 -/* 1833 */ MCD_OPC_Decode, 219, 10, 193, 1, // Opcode: VLD1LNd16_UPD -/* 1838 */ MCD_OPC_FilterValue, 5, 137, 1, 0, // Skip to: 2236 -/* 1843 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 1846 */ MCD_OPC_FilterValue, 0, 39, 1, 0, // Skip to: 2146 -/* 1851 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 1854 */ MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 2000 -/* 1859 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1862 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1967 -/* 1868 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 1871 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1903 -/* 1876 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1893 -/* 1881 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1893 -/* 1888 */ MCD_OPC_Decode, 145, 20, 202, 1, // Opcode: VST3q8 -/* 1893 */ MCD_OPC_CheckPredicate, 21, 195, 18, 0, // Skip to: 6701 -/* 1898 */ MCD_OPC_Decode, 147, 20, 202, 1, // Opcode: VST3q8_UPD -/* 1903 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 1935 -/* 1908 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1925 -/* 1913 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1925 -/* 1920 */ MCD_OPC_Decode, 135, 20, 202, 1, // Opcode: VST3q16 -/* 1925 */ MCD_OPC_CheckPredicate, 21, 163, 18, 0, // Skip to: 6701 -/* 1930 */ MCD_OPC_Decode, 137, 20, 202, 1, // Opcode: VST3q16_UPD -/* 1935 */ MCD_OPC_FilterValue, 2, 153, 18, 0, // Skip to: 6701 -/* 1940 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1957 -/* 1945 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1957 -/* 1952 */ MCD_OPC_Decode, 140, 20, 202, 1, // Opcode: VST3q32 -/* 1957 */ MCD_OPC_CheckPredicate, 21, 131, 18, 0, // Skip to: 6701 -/* 1962 */ MCD_OPC_Decode, 142, 20, 202, 1, // Opcode: VST3q32_UPD -/* 1967 */ MCD_OPC_FilterValue, 233, 3, 120, 18, 0, // Skip to: 6701 -/* 1973 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1990 -/* 1978 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1990 -/* 1985 */ MCD_OPC_Decode, 175, 19, 194, 1, // Opcode: VST2LNd16 -/* 1990 */ MCD_OPC_CheckPredicate, 21, 98, 18, 0, // Skip to: 6701 -/* 1995 */ MCD_OPC_Decode, 178, 19, 194, 1, // Opcode: VST2LNd16_UPD -/* 2000 */ MCD_OPC_FilterValue, 2, 88, 18, 0, // Skip to: 6701 -/* 2005 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2008 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 2113 -/* 2014 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 2017 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2049 -/* 2022 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2039 -/* 2027 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2039 -/* 2034 */ MCD_OPC_Decode, 196, 12, 202, 1, // Opcode: VLD3q8 -/* 2039 */ MCD_OPC_CheckPredicate, 21, 49, 18, 0, // Skip to: 6701 -/* 2044 */ MCD_OPC_Decode, 198, 12, 202, 1, // Opcode: VLD3q8_UPD -/* 2049 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 2081 -/* 2054 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2071 -/* 2059 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2071 -/* 2066 */ MCD_OPC_Decode, 186, 12, 202, 1, // Opcode: VLD3q16 -/* 2071 */ MCD_OPC_CheckPredicate, 21, 17, 18, 0, // Skip to: 6701 -/* 2076 */ MCD_OPC_Decode, 188, 12, 202, 1, // Opcode: VLD3q16_UPD -/* 2081 */ MCD_OPC_FilterValue, 2, 7, 18, 0, // Skip to: 6701 -/* 2086 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2103 -/* 2091 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2103 -/* 2098 */ MCD_OPC_Decode, 191, 12, 202, 1, // Opcode: VLD3q32 -/* 2103 */ MCD_OPC_CheckPredicate, 21, 241, 17, 0, // Skip to: 6701 -/* 2108 */ MCD_OPC_Decode, 193, 12, 202, 1, // Opcode: VLD3q32_UPD -/* 2113 */ MCD_OPC_FilterValue, 233, 3, 230, 17, 0, // Skip to: 6701 -/* 2119 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2136 -/* 2124 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2136 -/* 2131 */ MCD_OPC_Decode, 202, 11, 195, 1, // Opcode: VLD2LNd16 -/* 2136 */ MCD_OPC_CheckPredicate, 21, 208, 17, 0, // Skip to: 6701 -/* 2141 */ MCD_OPC_Decode, 205, 11, 195, 1, // Opcode: VLD2LNd16_UPD -/* 2146 */ MCD_OPC_FilterValue, 1, 198, 17, 0, // Skip to: 6701 -/* 2151 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 2154 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 2195 -/* 2159 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2162 */ MCD_OPC_FilterValue, 233, 3, 181, 17, 0, // Skip to: 6701 -/* 2168 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2185 -/* 2173 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2185 -/* 2180 */ MCD_OPC_Decode, 187, 19, 194, 1, // Opcode: VST2LNq16 -/* 2185 */ MCD_OPC_CheckPredicate, 21, 159, 17, 0, // Skip to: 6701 -/* 2190 */ MCD_OPC_Decode, 190, 19, 194, 1, // Opcode: VST2LNq16_UPD -/* 2195 */ MCD_OPC_FilterValue, 2, 149, 17, 0, // Skip to: 6701 -/* 2200 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2203 */ MCD_OPC_FilterValue, 233, 3, 140, 17, 0, // Skip to: 6701 -/* 2209 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2226 -/* 2214 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2226 -/* 2221 */ MCD_OPC_Decode, 214, 11, 195, 1, // Opcode: VLD2LNq16 -/* 2226 */ MCD_OPC_CheckPredicate, 21, 118, 17, 0, // Skip to: 6701 -/* 2231 */ MCD_OPC_Decode, 217, 11, 195, 1, // Opcode: VLD2LNq16_UPD -/* 2236 */ MCD_OPC_FilterValue, 6, 108, 2, 0, // Skip to: 2861 -/* 2241 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 2244 */ MCD_OPC_FilterValue, 0, 49, 1, 0, // Skip to: 2554 -/* 2249 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2252 */ MCD_OPC_FilterValue, 232, 3, 223, 0, 0, // Skip to: 2481 -/* 2258 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 2261 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 2316 -/* 2266 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2269 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2284 -/* 2274 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2306 -/* 2279 */ MCD_OPC_Decode, 143, 19, 196, 1, // Opcode: VST1d8Twb_fixed -/* 2284 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2306 -/* 2289 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2306 -/* 2294 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2306 -/* 2301 */ MCD_OPC_Decode, 141, 19, 196, 1, // Opcode: VST1d8T -/* 2306 */ MCD_OPC_CheckPredicate, 21, 38, 17, 0, // Skip to: 6701 -/* 2311 */ MCD_OPC_Decode, 144, 19, 196, 1, // Opcode: VST1d8Twb_register -/* 2316 */ MCD_OPC_FilterValue, 1, 50, 0, 0, // Skip to: 2371 -/* 2321 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2324 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2339 -/* 2329 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2361 -/* 2334 */ MCD_OPC_Decode, 234, 18, 196, 1, // Opcode: VST1d16Twb_fixed -/* 2339 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2361 -/* 2344 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2361 -/* 2349 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2361 -/* 2356 */ MCD_OPC_Decode, 232, 18, 196, 1, // Opcode: VST1d16T -/* 2361 */ MCD_OPC_CheckPredicate, 21, 239, 16, 0, // Skip to: 6701 -/* 2366 */ MCD_OPC_Decode, 235, 18, 196, 1, // Opcode: VST1d16Twb_register -/* 2371 */ MCD_OPC_FilterValue, 2, 50, 0, 0, // Skip to: 2426 -/* 2376 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2379 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2394 -/* 2384 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2416 -/* 2389 */ MCD_OPC_Decode, 245, 18, 196, 1, // Opcode: VST1d32Twb_fixed -/* 2394 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2416 -/* 2399 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2416 -/* 2404 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2416 -/* 2411 */ MCD_OPC_Decode, 243, 18, 196, 1, // Opcode: VST1d32T -/* 2416 */ MCD_OPC_CheckPredicate, 21, 184, 16, 0, // Skip to: 6701 -/* 2421 */ MCD_OPC_Decode, 246, 18, 196, 1, // Opcode: VST1d32Twb_register -/* 2426 */ MCD_OPC_FilterValue, 3, 174, 16, 0, // Skip to: 6701 -/* 2431 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2434 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2449 -/* 2439 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2471 -/* 2444 */ MCD_OPC_Decode, 132, 19, 196, 1, // Opcode: VST1d64Twb_fixed -/* 2449 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2471 -/* 2454 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2471 -/* 2459 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2471 -/* 2466 */ MCD_OPC_Decode, 128, 19, 196, 1, // Opcode: VST1d64T -/* 2471 */ MCD_OPC_CheckPredicate, 21, 129, 16, 0, // Skip to: 6701 -/* 2476 */ MCD_OPC_Decode, 133, 19, 196, 1, // Opcode: VST1d64Twb_register -/* 2481 */ MCD_OPC_FilterValue, 233, 3, 118, 16, 0, // Skip to: 6701 -/* 2487 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 2490 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2522 -/* 2495 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2512 -/* 2500 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2512 -/* 2507 */ MCD_OPC_Decode, 231, 19, 197, 1, // Opcode: VST3LNd16 -/* 2512 */ MCD_OPC_CheckPredicate, 21, 88, 16, 0, // Skip to: 6701 -/* 2517 */ MCD_OPC_Decode, 234, 19, 197, 1, // Opcode: VST3LNd16_UPD -/* 2522 */ MCD_OPC_FilterValue, 2, 78, 16, 0, // Skip to: 6701 -/* 2527 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2544 -/* 2532 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2544 -/* 2539 */ MCD_OPC_Decode, 243, 19, 197, 1, // Opcode: VST3LNq16 -/* 2544 */ MCD_OPC_CheckPredicate, 21, 56, 16, 0, // Skip to: 6701 -/* 2549 */ MCD_OPC_Decode, 246, 19, 197, 1, // Opcode: VST3LNq16_UPD -/* 2554 */ MCD_OPC_FilterValue, 2, 46, 16, 0, // Skip to: 6701 -/* 2559 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 2562 */ MCD_OPC_FilterValue, 0, 245, 0, 0, // Skip to: 2812 -/* 2567 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2570 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 2771 -/* 2576 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 2579 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 2627 -/* 2584 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2587 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2602 -/* 2592 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2617 -/* 2597 */ MCD_OPC_Decode, 146, 11, 196, 1, // Opcode: VLD1d8Twb_fixed -/* 2602 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2617 -/* 2607 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2617 -/* 2612 */ MCD_OPC_Decode, 144, 11, 196, 1, // Opcode: VLD1d8T -/* 2617 */ MCD_OPC_CheckPredicate, 21, 239, 15, 0, // Skip to: 6701 -/* 2622 */ MCD_OPC_Decode, 147, 11, 196, 1, // Opcode: VLD1d8Twb_register -/* 2627 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 2675 -/* 2632 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2635 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2650 -/* 2640 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2665 -/* 2645 */ MCD_OPC_Decode, 237, 10, 196, 1, // Opcode: VLD1d16Twb_fixed -/* 2650 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2665 -/* 2655 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2665 -/* 2660 */ MCD_OPC_Decode, 235, 10, 196, 1, // Opcode: VLD1d16T -/* 2665 */ MCD_OPC_CheckPredicate, 21, 191, 15, 0, // Skip to: 6701 -/* 2670 */ MCD_OPC_Decode, 238, 10, 196, 1, // Opcode: VLD1d16Twb_register -/* 2675 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 2723 -/* 2680 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2683 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2698 -/* 2688 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2713 -/* 2693 */ MCD_OPC_Decode, 248, 10, 196, 1, // Opcode: VLD1d32Twb_fixed -/* 2698 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2713 -/* 2703 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2713 -/* 2708 */ MCD_OPC_Decode, 246, 10, 196, 1, // Opcode: VLD1d32T -/* 2713 */ MCD_OPC_CheckPredicate, 21, 143, 15, 0, // Skip to: 6701 -/* 2718 */ MCD_OPC_Decode, 249, 10, 196, 1, // Opcode: VLD1d32Twb_register -/* 2723 */ MCD_OPC_FilterValue, 3, 133, 15, 0, // Skip to: 6701 -/* 2728 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2731 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2746 -/* 2736 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2761 -/* 2741 */ MCD_OPC_Decode, 135, 11, 196, 1, // Opcode: VLD1d64Twb_fixed -/* 2746 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2761 -/* 2751 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2761 -/* 2756 */ MCD_OPC_Decode, 131, 11, 196, 1, // Opcode: VLD1d64T -/* 2761 */ MCD_OPC_CheckPredicate, 21, 95, 15, 0, // Skip to: 6701 -/* 2766 */ MCD_OPC_Decode, 136, 11, 196, 1, // Opcode: VLD1d64Twb_register -/* 2771 */ MCD_OPC_FilterValue, 233, 3, 84, 15, 0, // Skip to: 6701 -/* 2777 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 2780 */ MCD_OPC_FilterValue, 0, 76, 15, 0, // Skip to: 6701 -/* 2785 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2802 -/* 2790 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2802 -/* 2797 */ MCD_OPC_Decode, 154, 12, 198, 1, // Opcode: VLD3LNd16 -/* 2802 */ MCD_OPC_CheckPredicate, 21, 54, 15, 0, // Skip to: 6701 -/* 2807 */ MCD_OPC_Decode, 157, 12, 198, 1, // Opcode: VLD3LNd16_UPD -/* 2812 */ MCD_OPC_FilterValue, 1, 44, 15, 0, // Skip to: 6701 -/* 2817 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 2820 */ MCD_OPC_FilterValue, 0, 36, 15, 0, // Skip to: 6701 -/* 2825 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2828 */ MCD_OPC_FilterValue, 233, 3, 27, 15, 0, // Skip to: 6701 -/* 2834 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2851 -/* 2839 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2851 -/* 2846 */ MCD_OPC_Decode, 166, 12, 198, 1, // Opcode: VLD3LNq16 -/* 2851 */ MCD_OPC_CheckPredicate, 21, 5, 15, 0, // Skip to: 6701 -/* 2856 */ MCD_OPC_Decode, 169, 12, 198, 1, // Opcode: VLD3LNq16_UPD -/* 2861 */ MCD_OPC_FilterValue, 7, 73, 2, 0, // Skip to: 3451 -/* 2866 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 2869 */ MCD_OPC_FilterValue, 0, 231, 1, 0, // Skip to: 3361 -/* 2874 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 2877 */ MCD_OPC_FilterValue, 0, 237, 0, 0, // Skip to: 3119 -/* 2882 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2885 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 3086 -/* 2891 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 2894 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 2942 -/* 2899 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2902 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2917 -/* 2907 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2932 -/* 2912 */ MCD_OPC_Decode, 145, 19, 196, 1, // Opcode: VST1d8wb_fixed -/* 2917 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2932 -/* 2922 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2932 -/* 2927 */ MCD_OPC_Decode, 136, 19, 196, 1, // Opcode: VST1d8 -/* 2932 */ MCD_OPC_CheckPredicate, 21, 180, 14, 0, // Skip to: 6701 -/* 2937 */ MCD_OPC_Decode, 146, 19, 196, 1, // Opcode: VST1d8wb_register -/* 2942 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 2990 -/* 2947 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2950 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2965 -/* 2955 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2980 -/* 2960 */ MCD_OPC_Decode, 236, 18, 196, 1, // Opcode: VST1d16wb_fixed -/* 2965 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2980 -/* 2970 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2980 -/* 2975 */ MCD_OPC_Decode, 227, 18, 196, 1, // Opcode: VST1d16 -/* 2980 */ MCD_OPC_CheckPredicate, 21, 132, 14, 0, // Skip to: 6701 -/* 2985 */ MCD_OPC_Decode, 237, 18, 196, 1, // Opcode: VST1d16wb_register -/* 2990 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 3038 -/* 2995 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2998 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3013 -/* 3003 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3028 -/* 3008 */ MCD_OPC_Decode, 247, 18, 196, 1, // Opcode: VST1d32wb_fixed -/* 3013 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3028 -/* 3018 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3028 -/* 3023 */ MCD_OPC_Decode, 238, 18, 196, 1, // Opcode: VST1d32 -/* 3028 */ MCD_OPC_CheckPredicate, 21, 84, 14, 0, // Skip to: 6701 -/* 3033 */ MCD_OPC_Decode, 248, 18, 196, 1, // Opcode: VST1d32wb_register -/* 3038 */ MCD_OPC_FilterValue, 3, 74, 14, 0, // Skip to: 6701 -/* 3043 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3046 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3061 -/* 3051 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3076 -/* 3056 */ MCD_OPC_Decode, 134, 19, 196, 1, // Opcode: VST1d64wb_fixed -/* 3061 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3076 -/* 3066 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3076 -/* 3071 */ MCD_OPC_Decode, 249, 18, 196, 1, // Opcode: VST1d64 -/* 3076 */ MCD_OPC_CheckPredicate, 21, 36, 14, 0, // Skip to: 6701 -/* 3081 */ MCD_OPC_Decode, 135, 19, 196, 1, // Opcode: VST1d64wb_register -/* 3086 */ MCD_OPC_FilterValue, 233, 3, 25, 14, 0, // Skip to: 6701 -/* 3092 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3109 -/* 3097 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3109 -/* 3104 */ MCD_OPC_Decode, 150, 20, 200, 1, // Opcode: VST4LNd16 -/* 3109 */ MCD_OPC_CheckPredicate, 21, 3, 14, 0, // Skip to: 6701 -/* 3114 */ MCD_OPC_Decode, 153, 20, 200, 1, // Opcode: VST4LNd16_UPD -/* 3119 */ MCD_OPC_FilterValue, 2, 249, 13, 0, // Skip to: 6701 -/* 3124 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3127 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 3328 -/* 3133 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 3136 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3184 -/* 3141 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3144 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3159 -/* 3149 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3174 -/* 3154 */ MCD_OPC_Decode, 148, 11, 196, 1, // Opcode: VLD1d8wb_fixed -/* 3159 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3174 -/* 3164 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3174 -/* 3169 */ MCD_OPC_Decode, 139, 11, 196, 1, // Opcode: VLD1d8 -/* 3174 */ MCD_OPC_CheckPredicate, 21, 194, 13, 0, // Skip to: 6701 -/* 3179 */ MCD_OPC_Decode, 149, 11, 196, 1, // Opcode: VLD1d8wb_register -/* 3184 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 3232 -/* 3189 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3192 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3207 -/* 3197 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3222 -/* 3202 */ MCD_OPC_Decode, 239, 10, 196, 1, // Opcode: VLD1d16wb_fixed -/* 3207 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3222 -/* 3212 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3222 -/* 3217 */ MCD_OPC_Decode, 230, 10, 196, 1, // Opcode: VLD1d16 -/* 3222 */ MCD_OPC_CheckPredicate, 21, 146, 13, 0, // Skip to: 6701 -/* 3227 */ MCD_OPC_Decode, 240, 10, 196, 1, // Opcode: VLD1d16wb_register -/* 3232 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 3280 -/* 3237 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3240 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3255 -/* 3245 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3270 -/* 3250 */ MCD_OPC_Decode, 250, 10, 196, 1, // Opcode: VLD1d32wb_fixed -/* 3255 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3270 -/* 3260 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3270 -/* 3265 */ MCD_OPC_Decode, 241, 10, 196, 1, // Opcode: VLD1d32 -/* 3270 */ MCD_OPC_CheckPredicate, 21, 98, 13, 0, // Skip to: 6701 -/* 3275 */ MCD_OPC_Decode, 251, 10, 196, 1, // Opcode: VLD1d32wb_register -/* 3280 */ MCD_OPC_FilterValue, 3, 88, 13, 0, // Skip to: 6701 -/* 3285 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3288 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3303 -/* 3293 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3318 -/* 3298 */ MCD_OPC_Decode, 137, 11, 196, 1, // Opcode: VLD1d64wb_fixed -/* 3303 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3318 -/* 3308 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3318 -/* 3313 */ MCD_OPC_Decode, 252, 10, 196, 1, // Opcode: VLD1d64 -/* 3318 */ MCD_OPC_CheckPredicate, 21, 50, 13, 0, // Skip to: 6701 -/* 3323 */ MCD_OPC_Decode, 138, 11, 196, 1, // Opcode: VLD1d64wb_register -/* 3328 */ MCD_OPC_FilterValue, 233, 3, 39, 13, 0, // Skip to: 6701 -/* 3334 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3351 -/* 3339 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3351 -/* 3346 */ MCD_OPC_Decode, 225, 12, 201, 1, // Opcode: VLD4LNd16 -/* 3351 */ MCD_OPC_CheckPredicate, 21, 17, 13, 0, // Skip to: 6701 -/* 3356 */ MCD_OPC_Decode, 228, 12, 201, 1, // Opcode: VLD4LNd16_UPD -/* 3361 */ MCD_OPC_FilterValue, 1, 7, 13, 0, // Skip to: 6701 -/* 3366 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 3369 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 3410 -/* 3374 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3377 */ MCD_OPC_FilterValue, 233, 3, 246, 12, 0, // Skip to: 6701 -/* 3383 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3400 -/* 3388 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3400 -/* 3395 */ MCD_OPC_Decode, 162, 20, 200, 1, // Opcode: VST4LNq16 -/* 3400 */ MCD_OPC_CheckPredicate, 21, 224, 12, 0, // Skip to: 6701 -/* 3405 */ MCD_OPC_Decode, 165, 20, 200, 1, // Opcode: VST4LNq16_UPD -/* 3410 */ MCD_OPC_FilterValue, 2, 214, 12, 0, // Skip to: 6701 -/* 3415 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3418 */ MCD_OPC_FilterValue, 233, 3, 205, 12, 0, // Skip to: 6701 -/* 3424 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3441 -/* 3429 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3441 -/* 3436 */ MCD_OPC_Decode, 237, 12, 201, 1, // Opcode: VLD4LNq16 -/* 3441 */ MCD_OPC_CheckPredicate, 21, 183, 12, 0, // Skip to: 6701 -/* 3446 */ MCD_OPC_Decode, 240, 12, 201, 1, // Opcode: VLD4LNq16_UPD -/* 3451 */ MCD_OPC_FilterValue, 8, 185, 1, 0, // Skip to: 3897 -/* 3456 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3459 */ MCD_OPC_FilterValue, 0, 39, 1, 0, // Skip to: 3759 -/* 3464 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 3467 */ MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 3613 -/* 3472 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3475 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 3580 -/* 3481 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 3484 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3532 -/* 3489 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3492 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3507 -/* 3497 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3522 -/* 3502 */ MCD_OPC_Decode, 211, 19, 199, 1, // Opcode: VST2d8wb_fixed -/* 3507 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3522 -/* 3512 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3522 -/* 3517 */ MCD_OPC_Decode, 210, 19, 199, 1, // Opcode: VST2d8 -/* 3522 */ MCD_OPC_CheckPredicate, 21, 102, 12, 0, // Skip to: 6701 -/* 3527 */ MCD_OPC_Decode, 212, 19, 199, 1, // Opcode: VST2d8wb_register -/* 3532 */ MCD_OPC_FilterValue, 1, 92, 12, 0, // Skip to: 6701 -/* 3537 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3540 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3555 -/* 3545 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3570 -/* 3550 */ MCD_OPC_Decode, 208, 19, 199, 1, // Opcode: VST2d32wb_fixed -/* 3555 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3570 -/* 3560 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3570 -/* 3565 */ MCD_OPC_Decode, 207, 19, 199, 1, // Opcode: VST2d32 -/* 3570 */ MCD_OPC_CheckPredicate, 21, 54, 12, 0, // Skip to: 6701 -/* 3575 */ MCD_OPC_Decode, 209, 19, 199, 1, // Opcode: VST2d32wb_register -/* 3580 */ MCD_OPC_FilterValue, 233, 3, 43, 12, 0, // Skip to: 6701 -/* 3586 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3603 -/* 3591 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3603 -/* 3598 */ MCD_OPC_Decode, 217, 18, 192, 1, // Opcode: VST1LNd32 -/* 3603 */ MCD_OPC_CheckPredicate, 21, 21, 12, 0, // Skip to: 6701 -/* 3608 */ MCD_OPC_Decode, 218, 18, 192, 1, // Opcode: VST1LNd32_UPD -/* 3613 */ MCD_OPC_FilterValue, 2, 11, 12, 0, // Skip to: 6701 -/* 3618 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3621 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 3726 -/* 3627 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 3630 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3678 -/* 3635 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3638 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3653 -/* 3643 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3668 -/* 3648 */ MCD_OPC_Decode, 238, 11, 199, 1, // Opcode: VLD2d8wb_fixed -/* 3653 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3668 -/* 3658 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3668 -/* 3663 */ MCD_OPC_Decode, 237, 11, 199, 1, // Opcode: VLD2d8 -/* 3668 */ MCD_OPC_CheckPredicate, 21, 212, 11, 0, // Skip to: 6701 -/* 3673 */ MCD_OPC_Decode, 239, 11, 199, 1, // Opcode: VLD2d8wb_register -/* 3678 */ MCD_OPC_FilterValue, 1, 202, 11, 0, // Skip to: 6701 -/* 3683 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3686 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3701 -/* 3691 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3716 -/* 3696 */ MCD_OPC_Decode, 235, 11, 199, 1, // Opcode: VLD2d32wb_fixed -/* 3701 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3716 -/* 3706 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3716 -/* 3711 */ MCD_OPC_Decode, 234, 11, 199, 1, // Opcode: VLD2d32 -/* 3716 */ MCD_OPC_CheckPredicate, 21, 164, 11, 0, // Skip to: 6701 -/* 3721 */ MCD_OPC_Decode, 236, 11, 199, 1, // Opcode: VLD2d32wb_register -/* 3726 */ MCD_OPC_FilterValue, 233, 3, 153, 11, 0, // Skip to: 6701 -/* 3732 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3749 -/* 3737 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3749 -/* 3744 */ MCD_OPC_Decode, 220, 10, 193, 1, // Opcode: VLD1LNd32 -/* 3749 */ MCD_OPC_CheckPredicate, 21, 131, 11, 0, // Skip to: 6701 -/* 3754 */ MCD_OPC_Decode, 221, 10, 193, 1, // Opcode: VLD1LNd32_UPD -/* 3759 */ MCD_OPC_FilterValue, 1, 121, 11, 0, // Skip to: 6701 -/* 3764 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 3767 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 3832 -/* 3772 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 3775 */ MCD_OPC_FilterValue, 0, 105, 11, 0, // Skip to: 6701 -/* 3780 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3783 */ MCD_OPC_FilterValue, 232, 3, 96, 11, 0, // Skip to: 6701 -/* 3789 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3792 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3807 -/* 3797 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3822 -/* 3802 */ MCD_OPC_Decode, 205, 19, 199, 1, // Opcode: VST2d16wb_fixed -/* 3807 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3822 -/* 3812 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3822 -/* 3817 */ MCD_OPC_Decode, 204, 19, 199, 1, // Opcode: VST2d16 -/* 3822 */ MCD_OPC_CheckPredicate, 21, 58, 11, 0, // Skip to: 6701 -/* 3827 */ MCD_OPC_Decode, 206, 19, 199, 1, // Opcode: VST2d16wb_register -/* 3832 */ MCD_OPC_FilterValue, 2, 48, 11, 0, // Skip to: 6701 -/* 3837 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 3840 */ MCD_OPC_FilterValue, 0, 40, 11, 0, // Skip to: 6701 -/* 3845 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3848 */ MCD_OPC_FilterValue, 232, 3, 31, 11, 0, // Skip to: 6701 -/* 3854 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3857 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3872 -/* 3862 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3887 -/* 3867 */ MCD_OPC_Decode, 232, 11, 199, 1, // Opcode: VLD2d16wb_fixed -/* 3872 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3887 -/* 3877 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3887 -/* 3882 */ MCD_OPC_Decode, 231, 11, 199, 1, // Opcode: VLD2d16 -/* 3887 */ MCD_OPC_CheckPredicate, 21, 249, 10, 0, // Skip to: 6701 -/* 3892 */ MCD_OPC_Decode, 233, 11, 199, 1, // Opcode: VLD2d16wb_register -/* 3897 */ MCD_OPC_FilterValue, 9, 27, 2, 0, // Skip to: 4441 -/* 3902 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 3905 */ MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 4221 -/* 3910 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 3913 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4067 -/* 3918 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 3921 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4026 -/* 3927 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 3930 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3978 -/* 3935 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3938 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3953 -/* 3943 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3968 -/* 3948 */ MCD_OPC_Decode, 202, 19, 199, 1, // Opcode: VST2b8wb_fixed -/* 3953 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3968 -/* 3958 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3968 -/* 3963 */ MCD_OPC_Decode, 201, 19, 199, 1, // Opcode: VST2b8 -/* 3968 */ MCD_OPC_CheckPredicate, 21, 168, 10, 0, // Skip to: 6701 -/* 3973 */ MCD_OPC_Decode, 203, 19, 199, 1, // Opcode: VST2b8wb_register -/* 3978 */ MCD_OPC_FilterValue, 1, 158, 10, 0, // Skip to: 6701 -/* 3983 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 3986 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4001 -/* 3991 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4016 -/* 3996 */ MCD_OPC_Decode, 199, 19, 199, 1, // Opcode: VST2b32wb_fixed -/* 4001 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4016 -/* 4006 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4016 -/* 4011 */ MCD_OPC_Decode, 198, 19, 199, 1, // Opcode: VST2b32 -/* 4016 */ MCD_OPC_CheckPredicate, 21, 120, 10, 0, // Skip to: 6701 -/* 4021 */ MCD_OPC_Decode, 200, 19, 199, 1, // Opcode: VST2b32wb_register -/* 4026 */ MCD_OPC_FilterValue, 233, 3, 109, 10, 0, // Skip to: 6701 -/* 4032 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 4035 */ MCD_OPC_FilterValue, 0, 101, 10, 0, // Skip to: 6701 -/* 4040 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4057 -/* 4045 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4057 -/* 4052 */ MCD_OPC_Decode, 179, 19, 194, 1, // Opcode: VST2LNd32 -/* 4057 */ MCD_OPC_CheckPredicate, 21, 79, 10, 0, // Skip to: 6701 -/* 4062 */ MCD_OPC_Decode, 182, 19, 194, 1, // Opcode: VST2LNd32_UPD -/* 4067 */ MCD_OPC_FilterValue, 2, 69, 10, 0, // Skip to: 6701 -/* 4072 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4075 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4180 -/* 4081 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4084 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4132 -/* 4089 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4092 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4107 -/* 4097 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4122 -/* 4102 */ MCD_OPC_Decode, 229, 11, 199, 1, // Opcode: VLD2b8wb_fixed -/* 4107 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4122 -/* 4112 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4122 -/* 4117 */ MCD_OPC_Decode, 228, 11, 199, 1, // Opcode: VLD2b8 -/* 4122 */ MCD_OPC_CheckPredicate, 21, 14, 10, 0, // Skip to: 6701 -/* 4127 */ MCD_OPC_Decode, 230, 11, 199, 1, // Opcode: VLD2b8wb_register -/* 4132 */ MCD_OPC_FilterValue, 1, 4, 10, 0, // Skip to: 6701 -/* 4137 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4140 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4155 -/* 4145 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4170 -/* 4150 */ MCD_OPC_Decode, 226, 11, 199, 1, // Opcode: VLD2b32wb_fixed -/* 4155 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4170 -/* 4160 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4170 -/* 4165 */ MCD_OPC_Decode, 225, 11, 199, 1, // Opcode: VLD2b32 -/* 4170 */ MCD_OPC_CheckPredicate, 21, 222, 9, 0, // Skip to: 6701 -/* 4175 */ MCD_OPC_Decode, 227, 11, 199, 1, // Opcode: VLD2b32wb_register -/* 4180 */ MCD_OPC_FilterValue, 233, 3, 211, 9, 0, // Skip to: 6701 -/* 4186 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 4189 */ MCD_OPC_FilterValue, 0, 203, 9, 0, // Skip to: 6701 -/* 4194 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4211 -/* 4199 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4211 -/* 4206 */ MCD_OPC_Decode, 206, 11, 195, 1, // Opcode: VLD2LNd32 -/* 4211 */ MCD_OPC_CheckPredicate, 21, 181, 9, 0, // Skip to: 6701 -/* 4216 */ MCD_OPC_Decode, 209, 11, 195, 1, // Opcode: VLD2LNd32_UPD -/* 4221 */ MCD_OPC_FilterValue, 1, 171, 9, 0, // Skip to: 6701 -/* 4226 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 4229 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 4335 -/* 4234 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4237 */ MCD_OPC_FilterValue, 232, 3, 51, 0, 0, // Skip to: 4294 -/* 4243 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4246 */ MCD_OPC_FilterValue, 0, 146, 9, 0, // Skip to: 6701 -/* 4251 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4254 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4269 -/* 4259 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4284 -/* 4264 */ MCD_OPC_Decode, 196, 19, 199, 1, // Opcode: VST2b16wb_fixed -/* 4269 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4284 -/* 4274 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4284 -/* 4279 */ MCD_OPC_Decode, 195, 19, 199, 1, // Opcode: VST2b16 -/* 4284 */ MCD_OPC_CheckPredicate, 21, 108, 9, 0, // Skip to: 6701 -/* 4289 */ MCD_OPC_Decode, 197, 19, 199, 1, // Opcode: VST2b16wb_register -/* 4294 */ MCD_OPC_FilterValue, 233, 3, 97, 9, 0, // Skip to: 6701 -/* 4300 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 4303 */ MCD_OPC_FilterValue, 0, 89, 9, 0, // Skip to: 6701 -/* 4308 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4325 -/* 4313 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4325 -/* 4320 */ MCD_OPC_Decode, 191, 19, 194, 1, // Opcode: VST2LNq32 -/* 4325 */ MCD_OPC_CheckPredicate, 21, 67, 9, 0, // Skip to: 6701 -/* 4330 */ MCD_OPC_Decode, 194, 19, 194, 1, // Opcode: VST2LNq32_UPD -/* 4335 */ MCD_OPC_FilterValue, 2, 57, 9, 0, // Skip to: 6701 -/* 4340 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4343 */ MCD_OPC_FilterValue, 232, 3, 51, 0, 0, // Skip to: 4400 -/* 4349 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4352 */ MCD_OPC_FilterValue, 0, 40, 9, 0, // Skip to: 6701 -/* 4357 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4360 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4375 -/* 4365 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4390 -/* 4370 */ MCD_OPC_Decode, 223, 11, 199, 1, // Opcode: VLD2b16wb_fixed -/* 4375 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4390 -/* 4380 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4390 -/* 4385 */ MCD_OPC_Decode, 222, 11, 199, 1, // Opcode: VLD2b16 -/* 4390 */ MCD_OPC_CheckPredicate, 21, 2, 9, 0, // Skip to: 6701 -/* 4395 */ MCD_OPC_Decode, 224, 11, 199, 1, // Opcode: VLD2b16wb_register -/* 4400 */ MCD_OPC_FilterValue, 233, 3, 247, 8, 0, // Skip to: 6701 -/* 4406 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 4409 */ MCD_OPC_FilterValue, 0, 239, 8, 0, // Skip to: 6701 -/* 4414 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4431 -/* 4419 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4431 -/* 4426 */ MCD_OPC_Decode, 218, 11, 195, 1, // Opcode: VLD2LNq32 -/* 4431 */ MCD_OPC_CheckPredicate, 21, 217, 8, 0, // Skip to: 6701 -/* 4436 */ MCD_OPC_Decode, 221, 11, 195, 1, // Opcode: VLD2LNq32_UPD -/* 4441 */ MCD_OPC_FilterValue, 10, 123, 2, 0, // Skip to: 5081 -/* 4446 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 4449 */ MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 4765 -/* 4454 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 4457 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4611 -/* 4462 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4465 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4570 -/* 4471 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4474 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4522 -/* 4479 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4482 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4497 -/* 4487 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4512 -/* 4492 */ MCD_OPC_Decode, 173, 19, 196, 1, // Opcode: VST1q8wb_fixed -/* 4497 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4512 -/* 4502 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4512 -/* 4507 */ MCD_OPC_Decode, 168, 19, 196, 1, // Opcode: VST1q8 -/* 4512 */ MCD_OPC_CheckPredicate, 21, 136, 8, 0, // Skip to: 6701 -/* 4517 */ MCD_OPC_Decode, 174, 19, 196, 1, // Opcode: VST1q8wb_register -/* 4522 */ MCD_OPC_FilterValue, 1, 126, 8, 0, // Skip to: 6701 -/* 4527 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4530 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4545 -/* 4535 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4560 -/* 4540 */ MCD_OPC_Decode, 159, 19, 196, 1, // Opcode: VST1q32wb_fixed -/* 4545 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4560 -/* 4550 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4560 -/* 4555 */ MCD_OPC_Decode, 154, 19, 196, 1, // Opcode: VST1q32 -/* 4560 */ MCD_OPC_CheckPredicate, 21, 88, 8, 0, // Skip to: 6701 -/* 4565 */ MCD_OPC_Decode, 160, 19, 196, 1, // Opcode: VST1q32wb_register -/* 4570 */ MCD_OPC_FilterValue, 233, 3, 77, 8, 0, // Skip to: 6701 -/* 4576 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 4579 */ MCD_OPC_FilterValue, 0, 69, 8, 0, // Skip to: 6701 -/* 4584 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4601 -/* 4589 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4601 -/* 4596 */ MCD_OPC_Decode, 235, 19, 197, 1, // Opcode: VST3LNd32 -/* 4601 */ MCD_OPC_CheckPredicate, 21, 47, 8, 0, // Skip to: 6701 -/* 4606 */ MCD_OPC_Decode, 238, 19, 197, 1, // Opcode: VST3LNd32_UPD -/* 4611 */ MCD_OPC_FilterValue, 2, 37, 8, 0, // Skip to: 6701 -/* 4616 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4619 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4724 -/* 4625 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4628 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4676 -/* 4633 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4636 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4651 -/* 4641 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4666 -/* 4646 */ MCD_OPC_Decode, 176, 11, 196, 1, // Opcode: VLD1q8wb_fixed -/* 4651 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4666 -/* 4656 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4666 -/* 4661 */ MCD_OPC_Decode, 171, 11, 196, 1, // Opcode: VLD1q8 -/* 4666 */ MCD_OPC_CheckPredicate, 21, 238, 7, 0, // Skip to: 6701 -/* 4671 */ MCD_OPC_Decode, 177, 11, 196, 1, // Opcode: VLD1q8wb_register -/* 4676 */ MCD_OPC_FilterValue, 1, 228, 7, 0, // Skip to: 6701 -/* 4681 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4684 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4699 -/* 4689 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4714 -/* 4694 */ MCD_OPC_Decode, 162, 11, 196, 1, // Opcode: VLD1q32wb_fixed -/* 4699 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4714 -/* 4704 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4714 -/* 4709 */ MCD_OPC_Decode, 157, 11, 196, 1, // Opcode: VLD1q32 -/* 4714 */ MCD_OPC_CheckPredicate, 21, 190, 7, 0, // Skip to: 6701 -/* 4719 */ MCD_OPC_Decode, 163, 11, 196, 1, // Opcode: VLD1q32wb_register -/* 4724 */ MCD_OPC_FilterValue, 233, 3, 179, 7, 0, // Skip to: 6701 -/* 4730 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 4733 */ MCD_OPC_FilterValue, 0, 171, 7, 0, // Skip to: 6701 -/* 4738 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4755 -/* 4743 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4755 -/* 4750 */ MCD_OPC_Decode, 158, 12, 198, 1, // Opcode: VLD3LNd32 -/* 4755 */ MCD_OPC_CheckPredicate, 21, 149, 7, 0, // Skip to: 6701 -/* 4760 */ MCD_OPC_Decode, 161, 12, 198, 1, // Opcode: VLD3LNd32_UPD -/* 4765 */ MCD_OPC_FilterValue, 1, 139, 7, 0, // Skip to: 6701 -/* 4770 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 4773 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4927 -/* 4778 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4781 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4886 -/* 4787 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4790 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4838 -/* 4795 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4798 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4813 -/* 4803 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4828 -/* 4808 */ MCD_OPC_Decode, 152, 19, 196, 1, // Opcode: VST1q16wb_fixed -/* 4813 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4828 -/* 4818 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4828 -/* 4823 */ MCD_OPC_Decode, 147, 19, 196, 1, // Opcode: VST1q16 -/* 4828 */ MCD_OPC_CheckPredicate, 21, 76, 7, 0, // Skip to: 6701 -/* 4833 */ MCD_OPC_Decode, 153, 19, 196, 1, // Opcode: VST1q16wb_register -/* 4838 */ MCD_OPC_FilterValue, 1, 66, 7, 0, // Skip to: 6701 -/* 4843 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4846 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4861 -/* 4851 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4876 -/* 4856 */ MCD_OPC_Decode, 166, 19, 196, 1, // Opcode: VST1q64wb_fixed -/* 4861 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4876 -/* 4866 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4876 -/* 4871 */ MCD_OPC_Decode, 161, 19, 196, 1, // Opcode: VST1q64 -/* 4876 */ MCD_OPC_CheckPredicate, 21, 28, 7, 0, // Skip to: 6701 -/* 4881 */ MCD_OPC_Decode, 167, 19, 196, 1, // Opcode: VST1q64wb_register -/* 4886 */ MCD_OPC_FilterValue, 233, 3, 17, 7, 0, // Skip to: 6701 -/* 4892 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 4895 */ MCD_OPC_FilterValue, 0, 9, 7, 0, // Skip to: 6701 -/* 4900 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4917 -/* 4905 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4917 -/* 4912 */ MCD_OPC_Decode, 247, 19, 197, 1, // Opcode: VST3LNq32 -/* 4917 */ MCD_OPC_CheckPredicate, 21, 243, 6, 0, // Skip to: 6701 -/* 4922 */ MCD_OPC_Decode, 250, 19, 197, 1, // Opcode: VST3LNq32_UPD -/* 4927 */ MCD_OPC_FilterValue, 2, 233, 6, 0, // Skip to: 6701 -/* 4932 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 4935 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 5040 -/* 4941 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4944 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4992 -/* 4949 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 4952 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4967 -/* 4957 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4982 -/* 4962 */ MCD_OPC_Decode, 155, 11, 196, 1, // Opcode: VLD1q16wb_fixed -/* 4967 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4982 -/* 4972 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4982 -/* 4977 */ MCD_OPC_Decode, 150, 11, 196, 1, // Opcode: VLD1q16 -/* 4982 */ MCD_OPC_CheckPredicate, 21, 178, 6, 0, // Skip to: 6701 -/* 4987 */ MCD_OPC_Decode, 156, 11, 196, 1, // Opcode: VLD1q16wb_register -/* 4992 */ MCD_OPC_FilterValue, 1, 168, 6, 0, // Skip to: 6701 -/* 4997 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5000 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5015 -/* 5005 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5030 -/* 5010 */ MCD_OPC_Decode, 169, 11, 196, 1, // Opcode: VLD1q64wb_fixed -/* 5015 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5030 -/* 5020 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5030 -/* 5025 */ MCD_OPC_Decode, 164, 11, 196, 1, // Opcode: VLD1q64 -/* 5030 */ MCD_OPC_CheckPredicate, 21, 130, 6, 0, // Skip to: 6701 -/* 5035 */ MCD_OPC_Decode, 170, 11, 196, 1, // Opcode: VLD1q64wb_register -/* 5040 */ MCD_OPC_FilterValue, 233, 3, 119, 6, 0, // Skip to: 6701 -/* 5046 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 5049 */ MCD_OPC_FilterValue, 0, 111, 6, 0, // Skip to: 6701 -/* 5054 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5071 -/* 5059 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5071 -/* 5066 */ MCD_OPC_Decode, 170, 12, 198, 1, // Opcode: VLD3LNq32 -/* 5071 */ MCD_OPC_CheckPredicate, 21, 89, 6, 0, // Skip to: 6701 -/* 5076 */ MCD_OPC_Decode, 173, 12, 198, 1, // Opcode: VLD3LNq32_UPD -/* 5081 */ MCD_OPC_FilterValue, 11, 183, 0, 0, // Skip to: 5269 -/* 5086 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 5089 */ MCD_OPC_FilterValue, 0, 85, 0, 0, // Skip to: 5179 -/* 5094 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5097 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 5138 -/* 5102 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5105 */ MCD_OPC_FilterValue, 233, 3, 54, 6, 0, // Skip to: 6701 -/* 5111 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5128 -/* 5116 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5128 -/* 5123 */ MCD_OPC_Decode, 154, 20, 200, 1, // Opcode: VST4LNd32 -/* 5128 */ MCD_OPC_CheckPredicate, 21, 32, 6, 0, // Skip to: 6701 -/* 5133 */ MCD_OPC_Decode, 157, 20, 200, 1, // Opcode: VST4LNd32_UPD -/* 5138 */ MCD_OPC_FilterValue, 2, 22, 6, 0, // Skip to: 6701 -/* 5143 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5146 */ MCD_OPC_FilterValue, 233, 3, 13, 6, 0, // Skip to: 6701 -/* 5152 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5169 -/* 5157 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5169 -/* 5164 */ MCD_OPC_Decode, 229, 12, 201, 1, // Opcode: VLD4LNd32 -/* 5169 */ MCD_OPC_CheckPredicate, 21, 247, 5, 0, // Skip to: 6701 -/* 5174 */ MCD_OPC_Decode, 232, 12, 201, 1, // Opcode: VLD4LNd32_UPD -/* 5179 */ MCD_OPC_FilterValue, 1, 237, 5, 0, // Skip to: 6701 -/* 5184 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5187 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 5228 -/* 5192 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5195 */ MCD_OPC_FilterValue, 233, 3, 220, 5, 0, // Skip to: 6701 -/* 5201 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5218 -/* 5206 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5218 -/* 5213 */ MCD_OPC_Decode, 166, 20, 200, 1, // Opcode: VST4LNq32 -/* 5218 */ MCD_OPC_CheckPredicate, 21, 198, 5, 0, // Skip to: 6701 -/* 5223 */ MCD_OPC_Decode, 169, 20, 200, 1, // Opcode: VST4LNq32_UPD -/* 5228 */ MCD_OPC_FilterValue, 2, 188, 5, 0, // Skip to: 6701 -/* 5233 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5236 */ MCD_OPC_FilterValue, 233, 3, 179, 5, 0, // Skip to: 6701 -/* 5242 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5259 -/* 5247 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5259 -/* 5254 */ MCD_OPC_Decode, 241, 12, 201, 1, // Opcode: VLD4LNq32 -/* 5259 */ MCD_OPC_CheckPredicate, 21, 157, 5, 0, // Skip to: 6701 -/* 5264 */ MCD_OPC_Decode, 244, 12, 201, 1, // Opcode: VLD4LNq32_UPD -/* 5269 */ MCD_OPC_FilterValue, 12, 137, 1, 0, // Skip to: 5667 -/* 5274 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... -/* 5277 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 5342 -/* 5282 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5285 */ MCD_OPC_FilterValue, 2, 131, 5, 0, // Skip to: 6701 -/* 5290 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5293 */ MCD_OPC_FilterValue, 233, 3, 122, 5, 0, // Skip to: 6701 -/* 5299 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5302 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5317 -/* 5307 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5332 -/* 5312 */ MCD_OPC_Decode, 207, 10, 203, 1, // Opcode: VLD1DUPd8wb_fixed -/* 5317 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5332 -/* 5322 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5332 -/* 5327 */ MCD_OPC_Decode, 206, 10, 203, 1, // Opcode: VLD1DUPd8 -/* 5332 */ MCD_OPC_CheckPredicate, 21, 84, 5, 0, // Skip to: 6701 -/* 5337 */ MCD_OPC_Decode, 208, 10, 203, 1, // Opcode: VLD1DUPd8wb_register -/* 5342 */ MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 5407 -/* 5347 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5350 */ MCD_OPC_FilterValue, 2, 66, 5, 0, // Skip to: 6701 -/* 5355 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5358 */ MCD_OPC_FilterValue, 233, 3, 57, 5, 0, // Skip to: 6701 -/* 5364 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5367 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5382 -/* 5372 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5397 -/* 5377 */ MCD_OPC_Decode, 216, 10, 203, 1, // Opcode: VLD1DUPq8wb_fixed -/* 5382 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5397 -/* 5387 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5397 -/* 5392 */ MCD_OPC_Decode, 215, 10, 203, 1, // Opcode: VLD1DUPq8 -/* 5397 */ MCD_OPC_CheckPredicate, 21, 19, 5, 0, // Skip to: 6701 -/* 5402 */ MCD_OPC_Decode, 217, 10, 203, 1, // Opcode: VLD1DUPq8wb_register -/* 5407 */ MCD_OPC_FilterValue, 2, 60, 0, 0, // Skip to: 5472 -/* 5412 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5415 */ MCD_OPC_FilterValue, 2, 1, 5, 0, // Skip to: 6701 -/* 5420 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5423 */ MCD_OPC_FilterValue, 233, 3, 248, 4, 0, // Skip to: 6701 -/* 5429 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5432 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5447 -/* 5437 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5462 -/* 5442 */ MCD_OPC_Decode, 201, 10, 203, 1, // Opcode: VLD1DUPd16wb_fixed -/* 5447 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5462 -/* 5452 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5462 -/* 5457 */ MCD_OPC_Decode, 200, 10, 203, 1, // Opcode: VLD1DUPd16 -/* 5462 */ MCD_OPC_CheckPredicate, 21, 210, 4, 0, // Skip to: 6701 -/* 5467 */ MCD_OPC_Decode, 202, 10, 203, 1, // Opcode: VLD1DUPd16wb_register -/* 5472 */ MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 5537 -/* 5477 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5480 */ MCD_OPC_FilterValue, 2, 192, 4, 0, // Skip to: 6701 -/* 5485 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5488 */ MCD_OPC_FilterValue, 233, 3, 183, 4, 0, // Skip to: 6701 -/* 5494 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5497 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5512 -/* 5502 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5527 -/* 5507 */ MCD_OPC_Decode, 210, 10, 203, 1, // Opcode: VLD1DUPq16wb_fixed -/* 5512 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5527 -/* 5517 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5527 -/* 5522 */ MCD_OPC_Decode, 209, 10, 203, 1, // Opcode: VLD1DUPq16 -/* 5527 */ MCD_OPC_CheckPredicate, 21, 145, 4, 0, // Skip to: 6701 -/* 5532 */ MCD_OPC_Decode, 211, 10, 203, 1, // Opcode: VLD1DUPq16wb_register -/* 5537 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 5602 -/* 5542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5545 */ MCD_OPC_FilterValue, 2, 127, 4, 0, // Skip to: 6701 -/* 5550 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5553 */ MCD_OPC_FilterValue, 233, 3, 118, 4, 0, // Skip to: 6701 -/* 5559 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5562 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5577 -/* 5567 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5592 -/* 5572 */ MCD_OPC_Decode, 204, 10, 203, 1, // Opcode: VLD1DUPd32wb_fixed -/* 5577 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5592 -/* 5582 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5592 -/* 5587 */ MCD_OPC_Decode, 203, 10, 203, 1, // Opcode: VLD1DUPd32 -/* 5592 */ MCD_OPC_CheckPredicate, 21, 80, 4, 0, // Skip to: 6701 -/* 5597 */ MCD_OPC_Decode, 205, 10, 203, 1, // Opcode: VLD1DUPd32wb_register -/* 5602 */ MCD_OPC_FilterValue, 5, 70, 4, 0, // Skip to: 6701 -/* 5607 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5610 */ MCD_OPC_FilterValue, 2, 62, 4, 0, // Skip to: 6701 -/* 5615 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5618 */ MCD_OPC_FilterValue, 233, 3, 53, 4, 0, // Skip to: 6701 -/* 5624 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5627 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5642 -/* 5632 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5657 -/* 5637 */ MCD_OPC_Decode, 213, 10, 203, 1, // Opcode: VLD1DUPq32wb_fixed -/* 5642 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5657 -/* 5647 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5657 -/* 5652 */ MCD_OPC_Decode, 212, 10, 203, 1, // Opcode: VLD1DUPq32 -/* 5657 */ MCD_OPC_CheckPredicate, 21, 15, 4, 0, // Skip to: 6701 -/* 5662 */ MCD_OPC_Decode, 214, 10, 203, 1, // Opcode: VLD1DUPq32wb_register -/* 5667 */ MCD_OPC_FilterValue, 13, 137, 1, 0, // Skip to: 6065 -/* 5672 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... -/* 5675 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 5740 -/* 5680 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5683 */ MCD_OPC_FilterValue, 2, 245, 3, 0, // Skip to: 6701 -/* 5688 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5691 */ MCD_OPC_FilterValue, 233, 3, 236, 3, 0, // Skip to: 6701 -/* 5697 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5700 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5715 -/* 5705 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5730 -/* 5710 */ MCD_OPC_Decode, 191, 11, 204, 1, // Opcode: VLD2DUPd8wb_fixed -/* 5715 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5730 -/* 5720 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5730 -/* 5725 */ MCD_OPC_Decode, 190, 11, 204, 1, // Opcode: VLD2DUPd8 -/* 5730 */ MCD_OPC_CheckPredicate, 21, 198, 3, 0, // Skip to: 6701 -/* 5735 */ MCD_OPC_Decode, 192, 11, 204, 1, // Opcode: VLD2DUPd8wb_register -/* 5740 */ MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 5805 -/* 5745 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5748 */ MCD_OPC_FilterValue, 2, 180, 3, 0, // Skip to: 6701 -/* 5753 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5756 */ MCD_OPC_FilterValue, 233, 3, 171, 3, 0, // Skip to: 6701 -/* 5762 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5765 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5780 -/* 5770 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5795 -/* 5775 */ MCD_OPC_Decode, 194, 11, 204, 1, // Opcode: VLD2DUPd8x2wb_fixed -/* 5780 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5795 -/* 5785 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5795 -/* 5790 */ MCD_OPC_Decode, 193, 11, 204, 1, // Opcode: VLD2DUPd8x2 -/* 5795 */ MCD_OPC_CheckPredicate, 21, 133, 3, 0, // Skip to: 6701 -/* 5800 */ MCD_OPC_Decode, 195, 11, 204, 1, // Opcode: VLD2DUPd8x2wb_register -/* 5805 */ MCD_OPC_FilterValue, 2, 60, 0, 0, // Skip to: 5870 -/* 5810 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5813 */ MCD_OPC_FilterValue, 2, 115, 3, 0, // Skip to: 6701 -/* 5818 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5821 */ MCD_OPC_FilterValue, 233, 3, 106, 3, 0, // Skip to: 6701 -/* 5827 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5830 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5845 -/* 5835 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5860 -/* 5840 */ MCD_OPC_Decode, 179, 11, 204, 1, // Opcode: VLD2DUPd16wb_fixed -/* 5845 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5860 -/* 5850 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5860 -/* 5855 */ MCD_OPC_Decode, 178, 11, 204, 1, // Opcode: VLD2DUPd16 -/* 5860 */ MCD_OPC_CheckPredicate, 21, 68, 3, 0, // Skip to: 6701 -/* 5865 */ MCD_OPC_Decode, 180, 11, 204, 1, // Opcode: VLD2DUPd16wb_register -/* 5870 */ MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 5935 -/* 5875 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5878 */ MCD_OPC_FilterValue, 2, 50, 3, 0, // Skip to: 6701 -/* 5883 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5886 */ MCD_OPC_FilterValue, 233, 3, 41, 3, 0, // Skip to: 6701 -/* 5892 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5895 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5910 -/* 5900 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5925 -/* 5905 */ MCD_OPC_Decode, 182, 11, 204, 1, // Opcode: VLD2DUPd16x2wb_fixed -/* 5910 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5925 -/* 5915 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5925 -/* 5920 */ MCD_OPC_Decode, 181, 11, 204, 1, // Opcode: VLD2DUPd16x2 -/* 5925 */ MCD_OPC_CheckPredicate, 21, 3, 3, 0, // Skip to: 6701 -/* 5930 */ MCD_OPC_Decode, 183, 11, 204, 1, // Opcode: VLD2DUPd16x2wb_register -/* 5935 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 6000 -/* 5940 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 5943 */ MCD_OPC_FilterValue, 2, 241, 2, 0, // Skip to: 6701 -/* 5948 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 5951 */ MCD_OPC_FilterValue, 233, 3, 232, 2, 0, // Skip to: 6701 -/* 5957 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 5960 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5975 -/* 5965 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5990 -/* 5970 */ MCD_OPC_Decode, 185, 11, 204, 1, // Opcode: VLD2DUPd32wb_fixed -/* 5975 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5990 -/* 5980 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5990 -/* 5985 */ MCD_OPC_Decode, 184, 11, 204, 1, // Opcode: VLD2DUPd32 -/* 5990 */ MCD_OPC_CheckPredicate, 21, 194, 2, 0, // Skip to: 6701 -/* 5995 */ MCD_OPC_Decode, 186, 11, 204, 1, // Opcode: VLD2DUPd32wb_register -/* 6000 */ MCD_OPC_FilterValue, 5, 184, 2, 0, // Skip to: 6701 -/* 6005 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6008 */ MCD_OPC_FilterValue, 2, 176, 2, 0, // Skip to: 6701 -/* 6013 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6016 */ MCD_OPC_FilterValue, 233, 3, 167, 2, 0, // Skip to: 6701 -/* 6022 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 6025 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 6040 -/* 6030 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 6055 -/* 6035 */ MCD_OPC_Decode, 188, 11, 204, 1, // Opcode: VLD2DUPd32x2wb_fixed -/* 6040 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 6055 -/* 6045 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 6055 -/* 6050 */ MCD_OPC_Decode, 187, 11, 204, 1, // Opcode: VLD2DUPd32x2 -/* 6055 */ MCD_OPC_CheckPredicate, 21, 129, 2, 0, // Skip to: 6701 -/* 6060 */ MCD_OPC_Decode, 189, 11, 204, 1, // Opcode: VLD2DUPd32x2wb_register -/* 6065 */ MCD_OPC_FilterValue, 14, 41, 1, 0, // Skip to: 6367 -/* 6070 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 6073 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6122 -/* 6078 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6081 */ MCD_OPC_FilterValue, 2, 103, 2, 0, // Skip to: 6701 -/* 6086 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6089 */ MCD_OPC_FilterValue, 233, 3, 94, 2, 0, // Skip to: 6701 -/* 6095 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6112 -/* 6100 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6112 -/* 6107 */ MCD_OPC_Decode, 138, 12, 205, 1, // Opcode: VLD3DUPd8 -/* 6112 */ MCD_OPC_CheckPredicate, 21, 72, 2, 0, // Skip to: 6701 -/* 6117 */ MCD_OPC_Decode, 141, 12, 205, 1, // Opcode: VLD3DUPd8_UPD -/* 6122 */ MCD_OPC_FilterValue, 2, 44, 0, 0, // Skip to: 6171 -/* 6127 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6130 */ MCD_OPC_FilterValue, 2, 54, 2, 0, // Skip to: 6701 -/* 6135 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6138 */ MCD_OPC_FilterValue, 233, 3, 45, 2, 0, // Skip to: 6701 -/* 6144 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6161 -/* 6149 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6161 -/* 6156 */ MCD_OPC_Decode, 150, 12, 205, 1, // Opcode: VLD3DUPq8 -/* 6161 */ MCD_OPC_CheckPredicate, 21, 23, 2, 0, // Skip to: 6701 -/* 6166 */ MCD_OPC_Decode, 153, 12, 205, 1, // Opcode: VLD3DUPq8_UPD -/* 6171 */ MCD_OPC_FilterValue, 4, 44, 0, 0, // Skip to: 6220 -/* 6176 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6179 */ MCD_OPC_FilterValue, 2, 5, 2, 0, // Skip to: 6701 -/* 6184 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6187 */ MCD_OPC_FilterValue, 233, 3, 252, 1, 0, // Skip to: 6701 -/* 6193 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6210 -/* 6198 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6210 -/* 6205 */ MCD_OPC_Decode, 130, 12, 205, 1, // Opcode: VLD3DUPd16 -/* 6210 */ MCD_OPC_CheckPredicate, 21, 230, 1, 0, // Skip to: 6701 -/* 6215 */ MCD_OPC_Decode, 133, 12, 205, 1, // Opcode: VLD3DUPd16_UPD -/* 6220 */ MCD_OPC_FilterValue, 6, 44, 0, 0, // Skip to: 6269 -/* 6225 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6228 */ MCD_OPC_FilterValue, 2, 212, 1, 0, // Skip to: 6701 -/* 6233 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6236 */ MCD_OPC_FilterValue, 233, 3, 203, 1, 0, // Skip to: 6701 -/* 6242 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6259 -/* 6247 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6259 -/* 6254 */ MCD_OPC_Decode, 142, 12, 205, 1, // Opcode: VLD3DUPq16 -/* 6259 */ MCD_OPC_CheckPredicate, 21, 181, 1, 0, // Skip to: 6701 -/* 6264 */ MCD_OPC_Decode, 145, 12, 205, 1, // Opcode: VLD3DUPq16_UPD -/* 6269 */ MCD_OPC_FilterValue, 8, 44, 0, 0, // Skip to: 6318 -/* 6274 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6277 */ MCD_OPC_FilterValue, 2, 163, 1, 0, // Skip to: 6701 -/* 6282 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6285 */ MCD_OPC_FilterValue, 233, 3, 154, 1, 0, // Skip to: 6701 -/* 6291 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6308 -/* 6296 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6308 -/* 6303 */ MCD_OPC_Decode, 134, 12, 205, 1, // Opcode: VLD3DUPd32 -/* 6308 */ MCD_OPC_CheckPredicate, 21, 132, 1, 0, // Skip to: 6701 -/* 6313 */ MCD_OPC_Decode, 137, 12, 205, 1, // Opcode: VLD3DUPd32_UPD -/* 6318 */ MCD_OPC_FilterValue, 10, 122, 1, 0, // Skip to: 6701 -/* 6323 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6326 */ MCD_OPC_FilterValue, 2, 114, 1, 0, // Skip to: 6701 -/* 6331 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6334 */ MCD_OPC_FilterValue, 233, 3, 105, 1, 0, // Skip to: 6701 -/* 6340 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6357 -/* 6345 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6357 -/* 6352 */ MCD_OPC_Decode, 146, 12, 205, 1, // Opcode: VLD3DUPq32 -/* 6357 */ MCD_OPC_CheckPredicate, 21, 83, 1, 0, // Skip to: 6701 -/* 6362 */ MCD_OPC_Decode, 149, 12, 205, 1, // Opcode: VLD3DUPq32_UPD -/* 6367 */ MCD_OPC_FilterValue, 15, 73, 1, 0, // Skip to: 6701 -/* 6372 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 6375 */ MCD_OPC_FilterValue, 0, 158, 0, 0, // Skip to: 6538 -/* 6380 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6383 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 6489 -/* 6388 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6391 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6440 -/* 6396 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6399 */ MCD_OPC_FilterValue, 2, 41, 1, 0, // Skip to: 6701 -/* 6404 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6407 */ MCD_OPC_FilterValue, 233, 3, 32, 1, 0, // Skip to: 6701 -/* 6413 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6430 -/* 6418 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6430 -/* 6425 */ MCD_OPC_Decode, 209, 12, 206, 1, // Opcode: VLD4DUPd8 -/* 6430 */ MCD_OPC_CheckPredicate, 21, 10, 1, 0, // Skip to: 6701 -/* 6435 */ MCD_OPC_Decode, 212, 12, 206, 1, // Opcode: VLD4DUPd8_UPD -/* 6440 */ MCD_OPC_FilterValue, 1, 0, 1, 0, // Skip to: 6701 -/* 6445 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6448 */ MCD_OPC_FilterValue, 2, 248, 0, 0, // Skip to: 6701 -/* 6453 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6456 */ MCD_OPC_FilterValue, 233, 3, 239, 0, 0, // Skip to: 6701 -/* 6462 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6479 -/* 6467 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6479 -/* 6474 */ MCD_OPC_Decode, 201, 12, 206, 1, // Opcode: VLD4DUPd16 -/* 6479 */ MCD_OPC_CheckPredicate, 21, 217, 0, 0, // Skip to: 6701 -/* 6484 */ MCD_OPC_Decode, 204, 12, 206, 1, // Opcode: VLD4DUPd16_UPD -/* 6489 */ MCD_OPC_FilterValue, 1, 207, 0, 0, // Skip to: 6701 -/* 6494 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6497 */ MCD_OPC_FilterValue, 2, 199, 0, 0, // Skip to: 6701 -/* 6502 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6505 */ MCD_OPC_FilterValue, 233, 3, 190, 0, 0, // Skip to: 6701 -/* 6511 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6528 -/* 6516 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6528 -/* 6523 */ MCD_OPC_Decode, 205, 12, 206, 1, // Opcode: VLD4DUPd32 -/* 6528 */ MCD_OPC_CheckPredicate, 21, 168, 0, 0, // Skip to: 6701 -/* 6533 */ MCD_OPC_Decode, 208, 12, 206, 1, // Opcode: VLD4DUPd32_UPD -/* 6538 */ MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 6701 -/* 6543 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6546 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 6652 -/* 6551 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 6554 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6603 -/* 6559 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6562 */ MCD_OPC_FilterValue, 2, 134, 0, 0, // Skip to: 6701 -/* 6567 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6570 */ MCD_OPC_FilterValue, 233, 3, 125, 0, 0, // Skip to: 6701 -/* 6576 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6593 -/* 6581 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6593 -/* 6588 */ MCD_OPC_Decode, 221, 12, 206, 1, // Opcode: VLD4DUPq8 -/* 6593 */ MCD_OPC_CheckPredicate, 21, 103, 0, 0, // Skip to: 6701 -/* 6598 */ MCD_OPC_Decode, 224, 12, 206, 1, // Opcode: VLD4DUPq8_UPD -/* 6603 */ MCD_OPC_FilterValue, 1, 93, 0, 0, // Skip to: 6701 -/* 6608 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6611 */ MCD_OPC_FilterValue, 2, 85, 0, 0, // Skip to: 6701 -/* 6616 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6619 */ MCD_OPC_FilterValue, 233, 3, 76, 0, 0, // Skip to: 6701 -/* 6625 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6642 -/* 6630 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6642 -/* 6637 */ MCD_OPC_Decode, 213, 12, 206, 1, // Opcode: VLD4DUPq16 -/* 6642 */ MCD_OPC_CheckPredicate, 21, 54, 0, 0, // Skip to: 6701 -/* 6647 */ MCD_OPC_Decode, 216, 12, 206, 1, // Opcode: VLD4DUPq16_UPD -/* 6652 */ MCD_OPC_FilterValue, 1, 44, 0, 0, // Skip to: 6701 -/* 6657 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 6660 */ MCD_OPC_FilterValue, 2, 36, 0, 0, // Skip to: 6701 -/* 6665 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 6668 */ MCD_OPC_FilterValue, 233, 3, 27, 0, 0, // Skip to: 6701 -/* 6674 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6691 -/* 6679 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6691 -/* 6686 */ MCD_OPC_Decode, 217, 12, 206, 1, // Opcode: VLD4DUPq32 -/* 6691 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 6701 -/* 6696 */ MCD_OPC_Decode, 220, 12, 206, 1, // Opcode: VLD4DUPq32_UPD -/* 6701 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 55, + 1, + 0, // Skip to: 319 + /* 8 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 165 + /* 16 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 19 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 124 + /* 25 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 28 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 60 + /* 33 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 50 + /* 38 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 50 + /* 45 */ MCD_OPC_Decode, + 167, + 29, + 166, + 2, // Opcode: VST4d8 + /* 50 */ MCD_OPC_CheckPredicate, + 26, + 246, + 25, + 0, // Skip to: 6701 + /* 55 */ MCD_OPC_Decode, + 170, + 29, + 166, + 2, // Opcode: VST4d8_UPD + /* 60 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 92 + /* 65 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 82 + /* 70 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 82 + /* 77 */ MCD_OPC_Decode, + 159, + 29, + 166, + 2, // Opcode: VST4d16 + /* 82 */ MCD_OPC_CheckPredicate, + 26, + 214, + 25, + 0, // Skip to: 6701 + /* 87 */ MCD_OPC_Decode, + 162, + 29, + 166, + 2, // Opcode: VST4d16_UPD + /* 92 */ MCD_OPC_FilterValue, + 2, + 204, + 25, + 0, // Skip to: 6701 + /* 97 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 114 + /* 102 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 114 + /* 109 */ MCD_OPC_Decode, + 163, + 29, + 166, + 2, // Opcode: VST4d32 + /* 114 */ MCD_OPC_CheckPredicate, + 26, + 182, + 25, + 0, // Skip to: 6701 + /* 119 */ MCD_OPC_Decode, + 166, + 29, + 166, + 2, // Opcode: VST4d32_UPD + /* 124 */ MCD_OPC_FilterValue, + 233, + 3, + 171, + 25, + 0, // Skip to: 6701 + /* 130 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 133 */ MCD_OPC_FilterValue, + 0, + 163, + 25, + 0, // Skip to: 6701 + /* 138 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 155 + /* 143 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 155 + /* 150 */ MCD_OPC_Decode, + 188, + 27, + 167, + 2, // Opcode: VST1LNd8 + /* 155 */ MCD_OPC_CheckPredicate, + 26, + 141, + 25, + 0, // Skip to: 6701 + /* 160 */ MCD_OPC_Decode, + 189, + 27, + 167, + 2, // Opcode: VST1LNd8_UPD + /* 165 */ MCD_OPC_FilterValue, + 2, + 131, + 25, + 0, // Skip to: 6701 + /* 170 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 173 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 278 + /* 179 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 182 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 214 + /* 187 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 204 + /* 192 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 204 + /* 199 */ MCD_OPC_Decode, + 204, + 21, + 166, + 2, // Opcode: VLD4d8 + /* 204 */ MCD_OPC_CheckPredicate, + 26, + 92, + 25, + 0, // Skip to: 6701 + /* 209 */ MCD_OPC_Decode, + 207, + 21, + 166, + 2, // Opcode: VLD4d8_UPD + /* 214 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 246 + /* 219 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 236 + /* 224 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 236 + /* 231 */ MCD_OPC_Decode, + 196, + 21, + 166, + 2, // Opcode: VLD4d16 + /* 236 */ MCD_OPC_CheckPredicate, + 26, + 60, + 25, + 0, // Skip to: 6701 + /* 241 */ MCD_OPC_Decode, + 199, + 21, + 166, + 2, // Opcode: VLD4d16_UPD + /* 246 */ MCD_OPC_FilterValue, + 2, + 50, + 25, + 0, // Skip to: 6701 + /* 251 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 268 + /* 256 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 268 + /* 263 */ MCD_OPC_Decode, + 200, + 21, + 166, + 2, // Opcode: VLD4d32 + /* 268 */ MCD_OPC_CheckPredicate, + 26, + 28, + 25, + 0, // Skip to: 6701 + /* 273 */ MCD_OPC_Decode, + 203, + 21, + 166, + 2, // Opcode: VLD4d32_UPD + /* 278 */ MCD_OPC_FilterValue, + 233, + 3, + 17, + 25, + 0, // Skip to: 6701 + /* 284 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 287 */ MCD_OPC_FilterValue, + 0, + 9, + 25, + 0, // Skip to: 6701 + /* 292 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 309 + /* 297 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 309 + /* 304 */ MCD_OPC_Decode, + 141, + 19, + 168, + 2, // Opcode: VLD1LNd8 + /* 309 */ MCD_OPC_CheckPredicate, + 26, + 243, + 24, + 0, // Skip to: 6701 + /* 314 */ MCD_OPC_Decode, + 142, + 19, + 168, + 2, // Opcode: VLD1LNd8_UPD + /* 319 */ MCD_OPC_FilterValue, + 1, + 39, + 1, + 0, // Skip to: 619 + /* 324 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 327 */ MCD_OPC_FilterValue, + 0, + 141, + 0, + 0, // Skip to: 473 + /* 332 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 335 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 440 + /* 341 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 344 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 376 + /* 349 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 366 + /* 354 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 366 + /* 361 */ MCD_OPC_Decode, + 181, + 29, + 166, + 2, // Opcode: VST4q8 + /* 366 */ MCD_OPC_CheckPredicate, + 26, + 186, + 24, + 0, // Skip to: 6701 + /* 371 */ MCD_OPC_Decode, + 183, + 29, + 166, + 2, // Opcode: VST4q8_UPD + /* 376 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 408 + /* 381 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 398 + /* 386 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 398 + /* 393 */ MCD_OPC_Decode, + 171, + 29, + 166, + 2, // Opcode: VST4q16 + /* 398 */ MCD_OPC_CheckPredicate, + 26, + 154, + 24, + 0, // Skip to: 6701 + /* 403 */ MCD_OPC_Decode, + 173, + 29, + 166, + 2, // Opcode: VST4q16_UPD + /* 408 */ MCD_OPC_FilterValue, + 2, + 144, + 24, + 0, // Skip to: 6701 + /* 413 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 430 + /* 418 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 430 + /* 425 */ MCD_OPC_Decode, + 176, + 29, + 166, + 2, // Opcode: VST4q32 + /* 430 */ MCD_OPC_CheckPredicate, + 26, + 122, + 24, + 0, // Skip to: 6701 + /* 435 */ MCD_OPC_Decode, + 178, + 29, + 166, + 2, // Opcode: VST4q32_UPD + /* 440 */ MCD_OPC_FilterValue, + 233, + 3, + 111, + 24, + 0, // Skip to: 6701 + /* 446 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 463 + /* 451 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 463 + /* 458 */ MCD_OPC_Decode, + 172, + 28, + 169, + 2, // Opcode: VST2LNd8 + /* 463 */ MCD_OPC_CheckPredicate, + 26, + 89, + 24, + 0, // Skip to: 6701 + /* 468 */ MCD_OPC_Decode, + 175, + 28, + 169, + 2, // Opcode: VST2LNd8_UPD + /* 473 */ MCD_OPC_FilterValue, + 2, + 79, + 24, + 0, // Skip to: 6701 + /* 478 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 481 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 586 + /* 487 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 490 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 522 + /* 495 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 512 + /* 500 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 512 + /* 507 */ MCD_OPC_Decode, + 218, + 21, + 166, + 2, // Opcode: VLD4q8 + /* 512 */ MCD_OPC_CheckPredicate, + 26, + 40, + 24, + 0, // Skip to: 6701 + /* 517 */ MCD_OPC_Decode, + 220, + 21, + 166, + 2, // Opcode: VLD4q8_UPD + /* 522 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 554 + /* 527 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 544 + /* 532 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 544 + /* 539 */ MCD_OPC_Decode, + 208, + 21, + 166, + 2, // Opcode: VLD4q16 + /* 544 */ MCD_OPC_CheckPredicate, + 26, + 8, + 24, + 0, // Skip to: 6701 + /* 549 */ MCD_OPC_Decode, + 210, + 21, + 166, + 2, // Opcode: VLD4q16_UPD + /* 554 */ MCD_OPC_FilterValue, + 2, + 254, + 23, + 0, // Skip to: 6701 + /* 559 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 576 + /* 564 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 576 + /* 571 */ MCD_OPC_Decode, + 213, + 21, + 166, + 2, // Opcode: VLD4q32 + /* 576 */ MCD_OPC_CheckPredicate, + 26, + 232, + 23, + 0, // Skip to: 6701 + /* 581 */ MCD_OPC_Decode, + 215, + 21, + 166, + 2, // Opcode: VLD4q32_UPD + /* 586 */ MCD_OPC_FilterValue, + 233, + 3, + 221, + 23, + 0, // Skip to: 6701 + /* 592 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 609 + /* 597 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 609 + /* 604 */ MCD_OPC_Decode, + 155, + 20, + 170, + 2, // Opcode: VLD2LNd8 + /* 609 */ MCD_OPC_CheckPredicate, + 26, + 199, + 23, + 0, // Skip to: 6701 + /* 614 */ MCD_OPC_Decode, + 158, + 20, + 170, + 2, // Opcode: VLD2LNd8_UPD + /* 619 */ MCD_OPC_FilterValue, + 2, + 247, + 1, + 0, // Skip to: 1127 + /* 624 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 627 */ MCD_OPC_FilterValue, + 0, + 245, + 0, + 0, // Skip to: 877 + /* 632 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 635 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 836 + /* 641 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 644 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 692 + /* 649 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 652 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 667 + /* 657 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 682 + /* 662 */ MCD_OPC_Decode, + 246, + 27, + 171, + 2, // Opcode: VST1d8Qwb_fixed + /* 667 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 682 + /* 672 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 682 + /* 677 */ MCD_OPC_Decode, + 242, + 27, + 171, + 2, // Opcode: VST1d8Q + /* 682 */ MCD_OPC_CheckPredicate, + 26, + 126, + 23, + 0, // Skip to: 6701 + /* 687 */ MCD_OPC_Decode, + 247, + 27, + 171, + 2, // Opcode: VST1d8Qwb_register + /* 692 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 740 + /* 697 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 700 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 715 + /* 705 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 730 + /* 710 */ MCD_OPC_Decode, + 201, + 27, + 171, + 2, // Opcode: VST1d16Qwb_fixed + /* 715 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 730 + /* 720 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 730 + /* 725 */ MCD_OPC_Decode, + 197, + 27, + 171, + 2, // Opcode: VST1d16Q + /* 730 */ MCD_OPC_CheckPredicate, + 26, + 78, + 23, + 0, // Skip to: 6701 + /* 735 */ MCD_OPC_Decode, + 202, + 27, + 171, + 2, // Opcode: VST1d16Qwb_register + /* 740 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 788 + /* 745 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 748 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 763 + /* 753 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 778 + /* 758 */ MCD_OPC_Decode, + 216, + 27, + 171, + 2, // Opcode: VST1d32Qwb_fixed + /* 763 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 778 + /* 768 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 778 + /* 773 */ MCD_OPC_Decode, + 212, + 27, + 171, + 2, // Opcode: VST1d32Q + /* 778 */ MCD_OPC_CheckPredicate, + 26, + 30, + 23, + 0, // Skip to: 6701 + /* 783 */ MCD_OPC_Decode, + 217, + 27, + 171, + 2, // Opcode: VST1d32Qwb_register + /* 788 */ MCD_OPC_FilterValue, + 3, + 20, + 23, + 0, // Skip to: 6701 + /* 793 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 796 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 811 + /* 801 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 826 + /* 806 */ MCD_OPC_Decode, + 231, + 27, + 171, + 2, // Opcode: VST1d64Qwb_fixed + /* 811 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 826 + /* 816 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 826 + /* 821 */ MCD_OPC_Decode, + 227, + 27, + 171, + 2, // Opcode: VST1d64Q + /* 826 */ MCD_OPC_CheckPredicate, + 26, + 238, + 22, + 0, // Skip to: 6701 + /* 831 */ MCD_OPC_Decode, + 232, + 27, + 171, + 2, // Opcode: VST1d64Qwb_register + /* 836 */ MCD_OPC_FilterValue, + 233, + 3, + 227, + 22, + 0, // Skip to: 6701 + /* 842 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 845 */ MCD_OPC_FilterValue, + 0, + 219, + 22, + 0, // Skip to: 6701 + /* 850 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 867 + /* 855 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 867 + /* 862 */ MCD_OPC_Decode, + 228, + 28, + 172, + 2, // Opcode: VST3LNd8 + /* 867 */ MCD_OPC_CheckPredicate, + 26, + 197, + 22, + 0, // Skip to: 6701 + /* 872 */ MCD_OPC_Decode, + 231, + 28, + 172, + 2, // Opcode: VST3LNd8_UPD + /* 877 */ MCD_OPC_FilterValue, + 2, + 187, + 22, + 0, // Skip to: 6701 + /* 882 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 885 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 1086 + /* 891 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 894 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 942 + /* 899 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 902 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 917 + /* 907 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 932 + /* 912 */ MCD_OPC_Decode, + 199, + 19, + 171, + 2, // Opcode: VLD1d8Qwb_fixed + /* 917 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 932 + /* 922 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 932 + /* 927 */ MCD_OPC_Decode, + 195, + 19, + 171, + 2, // Opcode: VLD1d8Q + /* 932 */ MCD_OPC_CheckPredicate, + 26, + 132, + 22, + 0, // Skip to: 6701 + /* 937 */ MCD_OPC_Decode, + 200, + 19, + 171, + 2, // Opcode: VLD1d8Qwb_register + /* 942 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 990 + /* 947 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 950 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 965 + /* 955 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 980 + /* 960 */ MCD_OPC_Decode, + 154, + 19, + 171, + 2, // Opcode: VLD1d16Qwb_fixed + /* 965 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 980 + /* 970 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 980 + /* 975 */ MCD_OPC_Decode, + 150, + 19, + 171, + 2, // Opcode: VLD1d16Q + /* 980 */ MCD_OPC_CheckPredicate, + 26, + 84, + 22, + 0, // Skip to: 6701 + /* 985 */ MCD_OPC_Decode, + 155, + 19, + 171, + 2, // Opcode: VLD1d16Qwb_register + /* 990 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 1038 + /* 995 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 998 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1013 + /* 1003 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1028 + /* 1008 */ MCD_OPC_Decode, + 169, + 19, + 171, + 2, // Opcode: VLD1d32Qwb_fixed + /* 1013 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1028 + /* 1018 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1028 + /* 1023 */ MCD_OPC_Decode, + 165, + 19, + 171, + 2, // Opcode: VLD1d32Q + /* 1028 */ MCD_OPC_CheckPredicate, + 26, + 36, + 22, + 0, // Skip to: 6701 + /* 1033 */ MCD_OPC_Decode, + 170, + 19, + 171, + 2, // Opcode: VLD1d32Qwb_register + /* 1038 */ MCD_OPC_FilterValue, + 3, + 26, + 22, + 0, // Skip to: 6701 + /* 1043 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1046 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1061 + /* 1051 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1076 + /* 1056 */ MCD_OPC_Decode, + 184, + 19, + 171, + 2, // Opcode: VLD1d64Qwb_fixed + /* 1061 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1076 + /* 1066 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1076 + /* 1071 */ MCD_OPC_Decode, + 180, + 19, + 171, + 2, // Opcode: VLD1d64Q + /* 1076 */ MCD_OPC_CheckPredicate, + 26, + 244, + 21, + 0, // Skip to: 6701 + /* 1081 */ MCD_OPC_Decode, + 185, + 19, + 171, + 2, // Opcode: VLD1d64Qwb_register + /* 1086 */ MCD_OPC_FilterValue, + 233, + 3, + 233, + 21, + 0, // Skip to: 6701 + /* 1092 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1095 */ MCD_OPC_FilterValue, + 0, + 225, + 21, + 0, // Skip to: 6701 + /* 1100 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1117 + /* 1105 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1117 + /* 1112 */ MCD_OPC_Decode, + 238, + 20, + 173, + 2, // Opcode: VLD3LNd8 + /* 1117 */ MCD_OPC_CheckPredicate, + 26, + 203, + 21, + 0, // Skip to: 6701 + /* 1122 */ MCD_OPC_Decode, + 241, + 20, + 173, + 2, // Opcode: VLD3LNd8_UPD + /* 1127 */ MCD_OPC_FilterValue, + 3, + 135, + 1, + 0, // Skip to: 1523 + /* 1132 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1135 */ MCD_OPC_FilterValue, + 0, + 189, + 0, + 0, // Skip to: 1329 + /* 1140 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1143 */ MCD_OPC_FilterValue, + 232, + 3, + 147, + 0, + 0, // Skip to: 1296 + /* 1149 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1152 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 1200 + /* 1157 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1160 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1175 + /* 1165 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1190 + /* 1170 */ MCD_OPC_Decode, + 218, + 28, + 174, + 2, // Opcode: VST2q8wb_fixed + /* 1175 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1190 + /* 1180 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1190 + /* 1185 */ MCD_OPC_Decode, + 214, + 28, + 174, + 2, // Opcode: VST2q8 + /* 1190 */ MCD_OPC_CheckPredicate, + 26, + 130, + 21, + 0, // Skip to: 6701 + /* 1195 */ MCD_OPC_Decode, + 219, + 28, + 174, + 2, // Opcode: VST2q8wb_register + /* 1200 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 1248 + /* 1205 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1208 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1223 + /* 1213 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1238 + /* 1218 */ MCD_OPC_Decode, + 206, + 28, + 174, + 2, // Opcode: VST2q16wb_fixed + /* 1223 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1238 + /* 1228 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1238 + /* 1233 */ MCD_OPC_Decode, + 202, + 28, + 174, + 2, // Opcode: VST2q16 + /* 1238 */ MCD_OPC_CheckPredicate, + 26, + 82, + 21, + 0, // Skip to: 6701 + /* 1243 */ MCD_OPC_Decode, + 207, + 28, + 174, + 2, // Opcode: VST2q16wb_register + /* 1248 */ MCD_OPC_FilterValue, + 2, + 72, + 21, + 0, // Skip to: 6701 + /* 1253 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1256 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1271 + /* 1261 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1286 + /* 1266 */ MCD_OPC_Decode, + 212, + 28, + 174, + 2, // Opcode: VST2q32wb_fixed + /* 1271 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1286 + /* 1276 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1286 + /* 1281 */ MCD_OPC_Decode, + 208, + 28, + 174, + 2, // Opcode: VST2q32 + /* 1286 */ MCD_OPC_CheckPredicate, + 26, + 34, + 21, + 0, // Skip to: 6701 + /* 1291 */ MCD_OPC_Decode, + 213, + 28, + 174, + 2, // Opcode: VST2q32wb_register + /* 1296 */ MCD_OPC_FilterValue, + 233, + 3, + 23, + 21, + 0, // Skip to: 6701 + /* 1302 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1319 + /* 1307 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1319 + /* 1314 */ MCD_OPC_Decode, + 147, + 29, + 175, + 2, // Opcode: VST4LNd8 + /* 1319 */ MCD_OPC_CheckPredicate, + 26, + 1, + 21, + 0, // Skip to: 6701 + /* 1324 */ MCD_OPC_Decode, + 150, + 29, + 175, + 2, // Opcode: VST4LNd8_UPD + /* 1329 */ MCD_OPC_FilterValue, + 2, + 247, + 20, + 0, // Skip to: 6701 + /* 1334 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1337 */ MCD_OPC_FilterValue, + 232, + 3, + 147, + 0, + 0, // Skip to: 1490 + /* 1343 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1346 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 1394 + /* 1351 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1354 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1369 + /* 1359 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1384 + /* 1364 */ MCD_OPC_Decode, + 201, + 20, + 174, + 2, // Opcode: VLD2q8wb_fixed + /* 1369 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1384 + /* 1374 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1384 + /* 1379 */ MCD_OPC_Decode, + 197, + 20, + 174, + 2, // Opcode: VLD2q8 + /* 1384 */ MCD_OPC_CheckPredicate, + 26, + 192, + 20, + 0, // Skip to: 6701 + /* 1389 */ MCD_OPC_Decode, + 202, + 20, + 174, + 2, // Opcode: VLD2q8wb_register + /* 1394 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 1442 + /* 1399 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1402 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1417 + /* 1407 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1432 + /* 1412 */ MCD_OPC_Decode, + 189, + 20, + 174, + 2, // Opcode: VLD2q16wb_fixed + /* 1417 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1432 + /* 1422 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1432 + /* 1427 */ MCD_OPC_Decode, + 185, + 20, + 174, + 2, // Opcode: VLD2q16 + /* 1432 */ MCD_OPC_CheckPredicate, + 26, + 144, + 20, + 0, // Skip to: 6701 + /* 1437 */ MCD_OPC_Decode, + 190, + 20, + 174, + 2, // Opcode: VLD2q16wb_register + /* 1442 */ MCD_OPC_FilterValue, + 2, + 134, + 20, + 0, // Skip to: 6701 + /* 1447 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 1450 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1465 + /* 1455 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 1480 + /* 1460 */ MCD_OPC_Decode, + 195, + 20, + 174, + 2, // Opcode: VLD2q32wb_fixed + /* 1465 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1480 + /* 1470 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 1480 + /* 1475 */ MCD_OPC_Decode, + 191, + 20, + 174, + 2, // Opcode: VLD2q32 + /* 1480 */ MCD_OPC_CheckPredicate, + 26, + 96, + 20, + 0, // Skip to: 6701 + /* 1485 */ MCD_OPC_Decode, + 196, + 20, + 174, + 2, // Opcode: VLD2q32wb_register + /* 1490 */ MCD_OPC_FilterValue, + 233, + 3, + 85, + 20, + 0, // Skip to: 6701 + /* 1496 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1513 + /* 1501 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1513 + /* 1508 */ MCD_OPC_Decode, + 184, + 21, + 176, + 2, // Opcode: VLD4LNd8 + /* 1513 */ MCD_OPC_CheckPredicate, + 26, + 63, + 20, + 0, // Skip to: 6701 + /* 1518 */ MCD_OPC_Decode, + 187, + 21, + 176, + 2, // Opcode: VLD4LNd8_UPD + /* 1523 */ MCD_OPC_FilterValue, + 4, + 54, + 1, + 0, // Skip to: 1838 + /* 1528 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1531 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 1685 + /* 1536 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1539 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 1644 + /* 1545 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 1548 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 1580 + /* 1553 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1570 + /* 1558 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1570 + /* 1565 */ MCD_OPC_Decode, + 248, + 28, + 177, + 2, // Opcode: VST3d8 + /* 1570 */ MCD_OPC_CheckPredicate, + 26, + 6, + 20, + 0, // Skip to: 6701 + /* 1575 */ MCD_OPC_Decode, + 251, + 28, + 177, + 2, // Opcode: VST3d8_UPD + /* 1580 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 1612 + /* 1585 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1602 + /* 1590 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1602 + /* 1597 */ MCD_OPC_Decode, + 240, + 28, + 177, + 2, // Opcode: VST3d16 + /* 1602 */ MCD_OPC_CheckPredicate, + 26, + 230, + 19, + 0, // Skip to: 6701 + /* 1607 */ MCD_OPC_Decode, + 243, + 28, + 177, + 2, // Opcode: VST3d16_UPD + /* 1612 */ MCD_OPC_FilterValue, + 4, + 220, + 19, + 0, // Skip to: 6701 + /* 1617 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1634 + /* 1622 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1634 + /* 1629 */ MCD_OPC_Decode, + 244, + 28, + 177, + 2, // Opcode: VST3d32 + /* 1634 */ MCD_OPC_CheckPredicate, + 26, + 198, + 19, + 0, // Skip to: 6701 + /* 1639 */ MCD_OPC_Decode, + 247, + 28, + 177, + 2, // Opcode: VST3d32_UPD + /* 1644 */ MCD_OPC_FilterValue, + 233, + 3, + 187, + 19, + 0, // Skip to: 6701 + /* 1650 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 1653 */ MCD_OPC_FilterValue, + 0, + 179, + 19, + 0, // Skip to: 6701 + /* 1658 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1675 + /* 1663 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1675 + /* 1670 */ MCD_OPC_Decode, + 184, + 27, + 167, + 2, // Opcode: VST1LNd16 + /* 1675 */ MCD_OPC_CheckPredicate, + 26, + 157, + 19, + 0, // Skip to: 6701 + /* 1680 */ MCD_OPC_Decode, + 185, + 27, + 167, + 2, // Opcode: VST1LNd16_UPD + /* 1685 */ MCD_OPC_FilterValue, + 2, + 147, + 19, + 0, // Skip to: 6701 + /* 1690 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1693 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 1798 + /* 1699 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 1702 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 1734 + /* 1707 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1724 + /* 1712 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1724 + /* 1719 */ MCD_OPC_Decode, + 130, + 21, + 177, + 2, // Opcode: VLD3d8 + /* 1724 */ MCD_OPC_CheckPredicate, + 26, + 108, + 19, + 0, // Skip to: 6701 + /* 1729 */ MCD_OPC_Decode, + 133, + 21, + 177, + 2, // Opcode: VLD3d8_UPD + /* 1734 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 1766 + /* 1739 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1756 + /* 1744 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1756 + /* 1751 */ MCD_OPC_Decode, + 250, + 20, + 177, + 2, // Opcode: VLD3d16 + /* 1756 */ MCD_OPC_CheckPredicate, + 26, + 76, + 19, + 0, // Skip to: 6701 + /* 1761 */ MCD_OPC_Decode, + 253, + 20, + 177, + 2, // Opcode: VLD3d16_UPD + /* 1766 */ MCD_OPC_FilterValue, + 4, + 66, + 19, + 0, // Skip to: 6701 + /* 1771 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1788 + /* 1776 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1788 + /* 1783 */ MCD_OPC_Decode, + 254, + 20, + 177, + 2, // Opcode: VLD3d32 + /* 1788 */ MCD_OPC_CheckPredicate, + 26, + 44, + 19, + 0, // Skip to: 6701 + /* 1793 */ MCD_OPC_Decode, + 129, + 21, + 177, + 2, // Opcode: VLD3d32_UPD + /* 1798 */ MCD_OPC_FilterValue, + 233, + 3, + 33, + 19, + 0, // Skip to: 6701 + /* 1804 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1821 + /* 1809 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1821 + /* 1816 */ MCD_OPC_Decode, + 137, + 19, + 168, + 2, // Opcode: VLD1LNd16 + /* 1821 */ MCD_OPC_CheckPredicate, + 26, + 11, + 19, + 0, // Skip to: 6701 + /* 1826 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 4, + 19, + 0, // Skip to: 6701 + /* 1833 */ MCD_OPC_Decode, + 138, + 19, + 168, + 2, // Opcode: VLD1LNd16_UPD + /* 1838 */ MCD_OPC_FilterValue, + 5, + 137, + 1, + 0, // Skip to: 2236 + /* 1843 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 1846 */ MCD_OPC_FilterValue, + 0, + 39, + 1, + 0, // Skip to: 2146 + /* 1851 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1854 */ MCD_OPC_FilterValue, + 0, + 141, + 0, + 0, // Skip to: 2000 + /* 1859 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1862 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 1967 + /* 1868 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1871 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 1903 + /* 1876 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1893 + /* 1881 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1893 + /* 1888 */ MCD_OPC_Decode, + 134, + 29, + 177, + 2, // Opcode: VST3q8 + /* 1893 */ MCD_OPC_CheckPredicate, + 26, + 195, + 18, + 0, // Skip to: 6701 + /* 1898 */ MCD_OPC_Decode, + 136, + 29, + 177, + 2, // Opcode: VST3q8_UPD + /* 1903 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 1935 + /* 1908 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1925 + /* 1913 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1925 + /* 1920 */ MCD_OPC_Decode, + 252, + 28, + 177, + 2, // Opcode: VST3q16 + /* 1925 */ MCD_OPC_CheckPredicate, + 26, + 163, + 18, + 0, // Skip to: 6701 + /* 1930 */ MCD_OPC_Decode, + 254, + 28, + 177, + 2, // Opcode: VST3q16_UPD + /* 1935 */ MCD_OPC_FilterValue, + 2, + 153, + 18, + 0, // Skip to: 6701 + /* 1940 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1957 + /* 1945 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1957 + /* 1952 */ MCD_OPC_Decode, + 129, + 29, + 177, + 2, // Opcode: VST3q32 + /* 1957 */ MCD_OPC_CheckPredicate, + 26, + 131, + 18, + 0, // Skip to: 6701 + /* 1962 */ MCD_OPC_Decode, + 131, + 29, + 177, + 2, // Opcode: VST3q32_UPD + /* 1967 */ MCD_OPC_FilterValue, + 233, + 3, + 120, + 18, + 0, // Skip to: 6701 + /* 1973 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 1990 + /* 1978 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 1990 + /* 1985 */ MCD_OPC_Decode, + 164, + 28, + 169, + 2, // Opcode: VST2LNd16 + /* 1990 */ MCD_OPC_CheckPredicate, + 26, + 98, + 18, + 0, // Skip to: 6701 + /* 1995 */ MCD_OPC_Decode, + 167, + 28, + 169, + 2, // Opcode: VST2LNd16_UPD + /* 2000 */ MCD_OPC_FilterValue, + 2, + 88, + 18, + 0, // Skip to: 6701 + /* 2005 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2008 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 2113 + /* 2014 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2017 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 2049 + /* 2022 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2039 + /* 2027 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2039 + /* 2034 */ MCD_OPC_Decode, + 144, + 21, + 177, + 2, // Opcode: VLD3q8 + /* 2039 */ MCD_OPC_CheckPredicate, + 26, + 49, + 18, + 0, // Skip to: 6701 + /* 2044 */ MCD_OPC_Decode, + 146, + 21, + 177, + 2, // Opcode: VLD3q8_UPD + /* 2049 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 2081 + /* 2054 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2071 + /* 2059 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2071 + /* 2066 */ MCD_OPC_Decode, + 134, + 21, + 177, + 2, // Opcode: VLD3q16 + /* 2071 */ MCD_OPC_CheckPredicate, + 26, + 17, + 18, + 0, // Skip to: 6701 + /* 2076 */ MCD_OPC_Decode, + 136, + 21, + 177, + 2, // Opcode: VLD3q16_UPD + /* 2081 */ MCD_OPC_FilterValue, + 2, + 7, + 18, + 0, // Skip to: 6701 + /* 2086 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2103 + /* 2091 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2103 + /* 2098 */ MCD_OPC_Decode, + 139, + 21, + 177, + 2, // Opcode: VLD3q32 + /* 2103 */ MCD_OPC_CheckPredicate, + 26, + 241, + 17, + 0, // Skip to: 6701 + /* 2108 */ MCD_OPC_Decode, + 141, + 21, + 177, + 2, // Opcode: VLD3q32_UPD + /* 2113 */ MCD_OPC_FilterValue, + 233, + 3, + 230, + 17, + 0, // Skip to: 6701 + /* 2119 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2136 + /* 2124 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2136 + /* 2131 */ MCD_OPC_Decode, + 147, + 20, + 170, + 2, // Opcode: VLD2LNd16 + /* 2136 */ MCD_OPC_CheckPredicate, + 26, + 208, + 17, + 0, // Skip to: 6701 + /* 2141 */ MCD_OPC_Decode, + 150, + 20, + 170, + 2, // Opcode: VLD2LNd16_UPD + /* 2146 */ MCD_OPC_FilterValue, + 1, + 198, + 17, + 0, // Skip to: 6701 + /* 2151 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2154 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 2195 + /* 2159 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2162 */ MCD_OPC_FilterValue, + 233, + 3, + 181, + 17, + 0, // Skip to: 6701 + /* 2168 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2185 + /* 2173 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2185 + /* 2180 */ MCD_OPC_Decode, + 176, + 28, + 169, + 2, // Opcode: VST2LNq16 + /* 2185 */ MCD_OPC_CheckPredicate, + 26, + 159, + 17, + 0, // Skip to: 6701 + /* 2190 */ MCD_OPC_Decode, + 179, + 28, + 169, + 2, // Opcode: VST2LNq16_UPD + /* 2195 */ MCD_OPC_FilterValue, + 2, + 149, + 17, + 0, // Skip to: 6701 + /* 2200 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2203 */ MCD_OPC_FilterValue, + 233, + 3, + 140, + 17, + 0, // Skip to: 6701 + /* 2209 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2226 + /* 2214 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2226 + /* 2221 */ MCD_OPC_Decode, + 159, + 20, + 170, + 2, // Opcode: VLD2LNq16 + /* 2226 */ MCD_OPC_CheckPredicate, + 26, + 118, + 17, + 0, // Skip to: 6701 + /* 2231 */ MCD_OPC_Decode, + 162, + 20, + 170, + 2, // Opcode: VLD2LNq16_UPD + /* 2236 */ MCD_OPC_FilterValue, + 6, + 108, + 2, + 0, // Skip to: 2861 + /* 2241 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2244 */ MCD_OPC_FilterValue, + 0, + 49, + 1, + 0, // Skip to: 2554 + /* 2249 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2252 */ MCD_OPC_FilterValue, + 232, + 3, + 223, + 0, + 0, // Skip to: 2481 + /* 2258 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2261 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 2316 + /* 2266 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2269 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2284 + /* 2274 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 2306 + /* 2279 */ MCD_OPC_Decode, + 252, + 27, + 171, + 2, // Opcode: VST1d8Twb_fixed + /* 2284 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2306 + /* 2289 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2306 + /* 2294 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 2306 + /* 2301 */ MCD_OPC_Decode, + 248, + 27, + 171, + 2, // Opcode: VST1d8T + /* 2306 */ MCD_OPC_CheckPredicate, + 26, + 38, + 17, + 0, // Skip to: 6701 + /* 2311 */ MCD_OPC_Decode, + 253, + 27, + 171, + 2, // Opcode: VST1d8Twb_register + /* 2316 */ MCD_OPC_FilterValue, + 1, + 50, + 0, + 0, // Skip to: 2371 + /* 2321 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2324 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2339 + /* 2329 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 2361 + /* 2334 */ MCD_OPC_Decode, + 207, + 27, + 171, + 2, // Opcode: VST1d16Twb_fixed + /* 2339 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2361 + /* 2344 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2361 + /* 2349 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 2361 + /* 2356 */ MCD_OPC_Decode, + 203, + 27, + 171, + 2, // Opcode: VST1d16T + /* 2361 */ MCD_OPC_CheckPredicate, + 26, + 239, + 16, + 0, // Skip to: 6701 + /* 2366 */ MCD_OPC_Decode, + 208, + 27, + 171, + 2, // Opcode: VST1d16Twb_register + /* 2371 */ MCD_OPC_FilterValue, + 2, + 50, + 0, + 0, // Skip to: 2426 + /* 2376 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2379 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2394 + /* 2384 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 2416 + /* 2389 */ MCD_OPC_Decode, + 222, + 27, + 171, + 2, // Opcode: VST1d32Twb_fixed + /* 2394 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2416 + /* 2399 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2416 + /* 2404 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 2416 + /* 2411 */ MCD_OPC_Decode, + 218, + 27, + 171, + 2, // Opcode: VST1d32T + /* 2416 */ MCD_OPC_CheckPredicate, + 26, + 184, + 16, + 0, // Skip to: 6701 + /* 2421 */ MCD_OPC_Decode, + 223, + 27, + 171, + 2, // Opcode: VST1d32Twb_register + /* 2426 */ MCD_OPC_FilterValue, + 3, + 174, + 16, + 0, // Skip to: 6701 + /* 2431 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2434 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2449 + /* 2439 */ MCD_OPC_CheckPredicate, + 26, + 27, + 0, + 0, // Skip to: 2471 + /* 2444 */ MCD_OPC_Decode, + 237, + 27, + 171, + 2, // Opcode: VST1d64Twb_fixed + /* 2449 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2471 + /* 2454 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2471 + /* 2459 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 5, + 0, + 0, // Skip to: 2471 + /* 2466 */ MCD_OPC_Decode, + 233, + 27, + 171, + 2, // Opcode: VST1d64T + /* 2471 */ MCD_OPC_CheckPredicate, + 26, + 129, + 16, + 0, // Skip to: 6701 + /* 2476 */ MCD_OPC_Decode, + 238, + 27, + 171, + 2, // Opcode: VST1d64Twb_register + /* 2481 */ MCD_OPC_FilterValue, + 233, + 3, + 118, + 16, + 0, // Skip to: 6701 + /* 2487 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 2490 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 2522 + /* 2495 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2512 + /* 2500 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2512 + /* 2507 */ MCD_OPC_Decode, + 220, + 28, + 172, + 2, // Opcode: VST3LNd16 + /* 2512 */ MCD_OPC_CheckPredicate, + 26, + 88, + 16, + 0, // Skip to: 6701 + /* 2517 */ MCD_OPC_Decode, + 223, + 28, + 172, + 2, // Opcode: VST3LNd16_UPD + /* 2522 */ MCD_OPC_FilterValue, + 2, + 78, + 16, + 0, // Skip to: 6701 + /* 2527 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2544 + /* 2532 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2544 + /* 2539 */ MCD_OPC_Decode, + 232, + 28, + 172, + 2, // Opcode: VST3LNq16 + /* 2544 */ MCD_OPC_CheckPredicate, + 26, + 56, + 16, + 0, // Skip to: 6701 + /* 2549 */ MCD_OPC_Decode, + 235, + 28, + 172, + 2, // Opcode: VST3LNq16_UPD + /* 2554 */ MCD_OPC_FilterValue, + 2, + 46, + 16, + 0, // Skip to: 6701 + /* 2559 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 2562 */ MCD_OPC_FilterValue, + 0, + 245, + 0, + 0, // Skip to: 2812 + /* 2567 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2570 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 2771 + /* 2576 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2579 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 2627 + /* 2584 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2587 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2602 + /* 2592 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2617 + /* 2597 */ MCD_OPC_Decode, + 205, + 19, + 171, + 2, // Opcode: VLD1d8Twb_fixed + /* 2602 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2617 + /* 2607 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2617 + /* 2612 */ MCD_OPC_Decode, + 201, + 19, + 171, + 2, // Opcode: VLD1d8T + /* 2617 */ MCD_OPC_CheckPredicate, + 26, + 239, + 15, + 0, // Skip to: 6701 + /* 2622 */ MCD_OPC_Decode, + 206, + 19, + 171, + 2, // Opcode: VLD1d8Twb_register + /* 2627 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 2675 + /* 2632 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2635 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2650 + /* 2640 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2665 + /* 2645 */ MCD_OPC_Decode, + 160, + 19, + 171, + 2, // Opcode: VLD1d16Twb_fixed + /* 2650 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2665 + /* 2655 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2665 + /* 2660 */ MCD_OPC_Decode, + 156, + 19, + 171, + 2, // Opcode: VLD1d16T + /* 2665 */ MCD_OPC_CheckPredicate, + 26, + 191, + 15, + 0, // Skip to: 6701 + /* 2670 */ MCD_OPC_Decode, + 161, + 19, + 171, + 2, // Opcode: VLD1d16Twb_register + /* 2675 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 2723 + /* 2680 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2683 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2698 + /* 2688 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2713 + /* 2693 */ MCD_OPC_Decode, + 175, + 19, + 171, + 2, // Opcode: VLD1d32Twb_fixed + /* 2698 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2713 + /* 2703 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2713 + /* 2708 */ MCD_OPC_Decode, + 171, + 19, + 171, + 2, // Opcode: VLD1d32T + /* 2713 */ MCD_OPC_CheckPredicate, + 26, + 143, + 15, + 0, // Skip to: 6701 + /* 2718 */ MCD_OPC_Decode, + 176, + 19, + 171, + 2, // Opcode: VLD1d32Twb_register + /* 2723 */ MCD_OPC_FilterValue, + 3, + 133, + 15, + 0, // Skip to: 6701 + /* 2728 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2731 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2746 + /* 2736 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2761 + /* 2741 */ MCD_OPC_Decode, + 190, + 19, + 171, + 2, // Opcode: VLD1d64Twb_fixed + /* 2746 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2761 + /* 2751 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2761 + /* 2756 */ MCD_OPC_Decode, + 186, + 19, + 171, + 2, // Opcode: VLD1d64T + /* 2761 */ MCD_OPC_CheckPredicate, + 26, + 95, + 15, + 0, // Skip to: 6701 + /* 2766 */ MCD_OPC_Decode, + 191, + 19, + 171, + 2, // Opcode: VLD1d64Twb_register + /* 2771 */ MCD_OPC_FilterValue, + 233, + 3, + 84, + 15, + 0, // Skip to: 6701 + /* 2777 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2780 */ MCD_OPC_FilterValue, + 0, + 76, + 15, + 0, // Skip to: 6701 + /* 2785 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2802 + /* 2790 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2802 + /* 2797 */ MCD_OPC_Decode, + 230, + 20, + 173, + 2, // Opcode: VLD3LNd16 + /* 2802 */ MCD_OPC_CheckPredicate, + 26, + 54, + 15, + 0, // Skip to: 6701 + /* 2807 */ MCD_OPC_Decode, + 233, + 20, + 173, + 2, // Opcode: VLD3LNd16_UPD + /* 2812 */ MCD_OPC_FilterValue, + 1, + 44, + 15, + 0, // Skip to: 6701 + /* 2817 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2820 */ MCD_OPC_FilterValue, + 0, + 36, + 15, + 0, // Skip to: 6701 + /* 2825 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2828 */ MCD_OPC_FilterValue, + 233, + 3, + 27, + 15, + 0, // Skip to: 6701 + /* 2834 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 2851 + /* 2839 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 2851 + /* 2846 */ MCD_OPC_Decode, + 242, + 20, + 173, + 2, // Opcode: VLD3LNq16 + /* 2851 */ MCD_OPC_CheckPredicate, + 26, + 5, + 15, + 0, // Skip to: 6701 + /* 2856 */ MCD_OPC_Decode, + 245, + 20, + 173, + 2, // Opcode: VLD3LNq16_UPD + /* 2861 */ MCD_OPC_FilterValue, + 7, + 73, + 2, + 0, // Skip to: 3451 + /* 2866 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 2869 */ MCD_OPC_FilterValue, + 0, + 231, + 1, + 0, // Skip to: 3361 + /* 2874 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2877 */ MCD_OPC_FilterValue, + 0, + 237, + 0, + 0, // Skip to: 3119 + /* 2882 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2885 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 3086 + /* 2891 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2894 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 2942 + /* 2899 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2902 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2917 + /* 2907 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2932 + /* 2912 */ MCD_OPC_Decode, + 254, + 27, + 171, + 2, // Opcode: VST1d8wb_fixed + /* 2917 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2932 + /* 2922 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2932 + /* 2927 */ MCD_OPC_Decode, + 241, + 27, + 171, + 2, // Opcode: VST1d8 + /* 2932 */ MCD_OPC_CheckPredicate, + 26, + 180, + 14, + 0, // Skip to: 6701 + /* 2937 */ MCD_OPC_Decode, + 255, + 27, + 171, + 2, // Opcode: VST1d8wb_register + /* 2942 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 2990 + /* 2947 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2950 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2965 + /* 2955 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 2980 + /* 2960 */ MCD_OPC_Decode, + 209, + 27, + 171, + 2, // Opcode: VST1d16wb_fixed + /* 2965 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2980 + /* 2970 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 2980 + /* 2975 */ MCD_OPC_Decode, + 196, + 27, + 171, + 2, // Opcode: VST1d16 + /* 2980 */ MCD_OPC_CheckPredicate, + 26, + 132, + 14, + 0, // Skip to: 6701 + /* 2985 */ MCD_OPC_Decode, + 210, + 27, + 171, + 2, // Opcode: VST1d16wb_register + /* 2990 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 3038 + /* 2995 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 2998 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3013 + /* 3003 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3028 + /* 3008 */ MCD_OPC_Decode, + 224, + 27, + 171, + 2, // Opcode: VST1d32wb_fixed + /* 3013 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3028 + /* 3018 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3028 + /* 3023 */ MCD_OPC_Decode, + 211, + 27, + 171, + 2, // Opcode: VST1d32 + /* 3028 */ MCD_OPC_CheckPredicate, + 26, + 84, + 14, + 0, // Skip to: 6701 + /* 3033 */ MCD_OPC_Decode, + 225, + 27, + 171, + 2, // Opcode: VST1d32wb_register + /* 3038 */ MCD_OPC_FilterValue, + 3, + 74, + 14, + 0, // Skip to: 6701 + /* 3043 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3046 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3061 + /* 3051 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3076 + /* 3056 */ MCD_OPC_Decode, + 239, + 27, + 171, + 2, // Opcode: VST1d64wb_fixed + /* 3061 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3076 + /* 3066 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3076 + /* 3071 */ MCD_OPC_Decode, + 226, + 27, + 171, + 2, // Opcode: VST1d64 + /* 3076 */ MCD_OPC_CheckPredicate, + 26, + 36, + 14, + 0, // Skip to: 6701 + /* 3081 */ MCD_OPC_Decode, + 240, + 27, + 171, + 2, // Opcode: VST1d64wb_register + /* 3086 */ MCD_OPC_FilterValue, + 233, + 3, + 25, + 14, + 0, // Skip to: 6701 + /* 3092 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3109 + /* 3097 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3109 + /* 3104 */ MCD_OPC_Decode, + 139, + 29, + 175, + 2, // Opcode: VST4LNd16 + /* 3109 */ MCD_OPC_CheckPredicate, + 26, + 3, + 14, + 0, // Skip to: 6701 + /* 3114 */ MCD_OPC_Decode, + 142, + 29, + 175, + 2, // Opcode: VST4LNd16_UPD + /* 3119 */ MCD_OPC_FilterValue, + 2, + 249, + 13, + 0, // Skip to: 6701 + /* 3124 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3127 */ MCD_OPC_FilterValue, + 232, + 3, + 195, + 0, + 0, // Skip to: 3328 + /* 3133 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 3136 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 3184 + /* 3141 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3144 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3159 + /* 3149 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3174 + /* 3154 */ MCD_OPC_Decode, + 207, + 19, + 171, + 2, // Opcode: VLD1d8wb_fixed + /* 3159 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3174 + /* 3164 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3174 + /* 3169 */ MCD_OPC_Decode, + 194, + 19, + 171, + 2, // Opcode: VLD1d8 + /* 3174 */ MCD_OPC_CheckPredicate, + 26, + 194, + 13, + 0, // Skip to: 6701 + /* 3179 */ MCD_OPC_Decode, + 208, + 19, + 171, + 2, // Opcode: VLD1d8wb_register + /* 3184 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 3232 + /* 3189 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3192 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3207 + /* 3197 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3222 + /* 3202 */ MCD_OPC_Decode, + 162, + 19, + 171, + 2, // Opcode: VLD1d16wb_fixed + /* 3207 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3222 + /* 3212 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3222 + /* 3217 */ MCD_OPC_Decode, + 149, + 19, + 171, + 2, // Opcode: VLD1d16 + /* 3222 */ MCD_OPC_CheckPredicate, + 26, + 146, + 13, + 0, // Skip to: 6701 + /* 3227 */ MCD_OPC_Decode, + 163, + 19, + 171, + 2, // Opcode: VLD1d16wb_register + /* 3232 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 3280 + /* 3237 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3240 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3255 + /* 3245 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3270 + /* 3250 */ MCD_OPC_Decode, + 177, + 19, + 171, + 2, // Opcode: VLD1d32wb_fixed + /* 3255 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3270 + /* 3260 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3270 + /* 3265 */ MCD_OPC_Decode, + 164, + 19, + 171, + 2, // Opcode: VLD1d32 + /* 3270 */ MCD_OPC_CheckPredicate, + 26, + 98, + 13, + 0, // Skip to: 6701 + /* 3275 */ MCD_OPC_Decode, + 178, + 19, + 171, + 2, // Opcode: VLD1d32wb_register + /* 3280 */ MCD_OPC_FilterValue, + 3, + 88, + 13, + 0, // Skip to: 6701 + /* 3285 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3288 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3303 + /* 3293 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3318 + /* 3298 */ MCD_OPC_Decode, + 192, + 19, + 171, + 2, // Opcode: VLD1d64wb_fixed + /* 3303 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3318 + /* 3308 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3318 + /* 3313 */ MCD_OPC_Decode, + 179, + 19, + 171, + 2, // Opcode: VLD1d64 + /* 3318 */ MCD_OPC_CheckPredicate, + 26, + 50, + 13, + 0, // Skip to: 6701 + /* 3323 */ MCD_OPC_Decode, + 193, + 19, + 171, + 2, // Opcode: VLD1d64wb_register + /* 3328 */ MCD_OPC_FilterValue, + 233, + 3, + 39, + 13, + 0, // Skip to: 6701 + /* 3334 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3351 + /* 3339 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3351 + /* 3346 */ MCD_OPC_Decode, + 176, + 21, + 176, + 2, // Opcode: VLD4LNd16 + /* 3351 */ MCD_OPC_CheckPredicate, + 26, + 17, + 13, + 0, // Skip to: 6701 + /* 3356 */ MCD_OPC_Decode, + 179, + 21, + 176, + 2, // Opcode: VLD4LNd16_UPD + /* 3361 */ MCD_OPC_FilterValue, + 1, + 7, + 13, + 0, // Skip to: 6701 + /* 3366 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3369 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 3410 + /* 3374 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3377 */ MCD_OPC_FilterValue, + 233, + 3, + 246, + 12, + 0, // Skip to: 6701 + /* 3383 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3400 + /* 3388 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3400 + /* 3395 */ MCD_OPC_Decode, + 151, + 29, + 175, + 2, // Opcode: VST4LNq16 + /* 3400 */ MCD_OPC_CheckPredicate, + 26, + 224, + 12, + 0, // Skip to: 6701 + /* 3405 */ MCD_OPC_Decode, + 154, + 29, + 175, + 2, // Opcode: VST4LNq16_UPD + /* 3410 */ MCD_OPC_FilterValue, + 2, + 214, + 12, + 0, // Skip to: 6701 + /* 3415 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3418 */ MCD_OPC_FilterValue, + 233, + 3, + 205, + 12, + 0, // Skip to: 6701 + /* 3424 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3441 + /* 3429 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3441 + /* 3436 */ MCD_OPC_Decode, + 188, + 21, + 176, + 2, // Opcode: VLD4LNq16 + /* 3441 */ MCD_OPC_CheckPredicate, + 26, + 183, + 12, + 0, // Skip to: 6701 + /* 3446 */ MCD_OPC_Decode, + 191, + 21, + 176, + 2, // Opcode: VLD4LNq16_UPD + /* 3451 */ MCD_OPC_FilterValue, + 8, + 185, + 1, + 0, // Skip to: 3897 + /* 3456 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3459 */ MCD_OPC_FilterValue, + 0, + 39, + 1, + 0, // Skip to: 3759 + /* 3464 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3467 */ MCD_OPC_FilterValue, + 0, + 141, + 0, + 0, // Skip to: 3613 + /* 3472 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3475 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 3580 + /* 3481 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3484 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 3532 + /* 3489 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3492 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3507 + /* 3497 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3522 + /* 3502 */ MCD_OPC_Decode, + 200, + 28, + 174, + 2, // Opcode: VST2d8wb_fixed + /* 3507 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3522 + /* 3512 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3522 + /* 3517 */ MCD_OPC_Decode, + 199, + 28, + 174, + 2, // Opcode: VST2d8 + /* 3522 */ MCD_OPC_CheckPredicate, + 26, + 102, + 12, + 0, // Skip to: 6701 + /* 3527 */ MCD_OPC_Decode, + 201, + 28, + 174, + 2, // Opcode: VST2d8wb_register + /* 3532 */ MCD_OPC_FilterValue, + 1, + 92, + 12, + 0, // Skip to: 6701 + /* 3537 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3540 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3555 + /* 3545 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3570 + /* 3550 */ MCD_OPC_Decode, + 197, + 28, + 174, + 2, // Opcode: VST2d32wb_fixed + /* 3555 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3570 + /* 3560 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3570 + /* 3565 */ MCD_OPC_Decode, + 196, + 28, + 174, + 2, // Opcode: VST2d32 + /* 3570 */ MCD_OPC_CheckPredicate, + 26, + 54, + 12, + 0, // Skip to: 6701 + /* 3575 */ MCD_OPC_Decode, + 198, + 28, + 174, + 2, // Opcode: VST2d32wb_register + /* 3580 */ MCD_OPC_FilterValue, + 233, + 3, + 43, + 12, + 0, // Skip to: 6701 + /* 3586 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3603 + /* 3591 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3603 + /* 3598 */ MCD_OPC_Decode, + 186, + 27, + 167, + 2, // Opcode: VST1LNd32 + /* 3603 */ MCD_OPC_CheckPredicate, + 26, + 21, + 12, + 0, // Skip to: 6701 + /* 3608 */ MCD_OPC_Decode, + 187, + 27, + 167, + 2, // Opcode: VST1LNd32_UPD + /* 3613 */ MCD_OPC_FilterValue, + 2, + 11, + 12, + 0, // Skip to: 6701 + /* 3618 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3621 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 3726 + /* 3627 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3630 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 3678 + /* 3635 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3638 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3653 + /* 3643 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3668 + /* 3648 */ MCD_OPC_Decode, + 183, + 20, + 174, + 2, // Opcode: VLD2d8wb_fixed + /* 3653 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3668 + /* 3658 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3668 + /* 3663 */ MCD_OPC_Decode, + 182, + 20, + 174, + 2, // Opcode: VLD2d8 + /* 3668 */ MCD_OPC_CheckPredicate, + 26, + 212, + 11, + 0, // Skip to: 6701 + /* 3673 */ MCD_OPC_Decode, + 184, + 20, + 174, + 2, // Opcode: VLD2d8wb_register + /* 3678 */ MCD_OPC_FilterValue, + 1, + 202, + 11, + 0, // Skip to: 6701 + /* 3683 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3686 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3701 + /* 3691 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3716 + /* 3696 */ MCD_OPC_Decode, + 180, + 20, + 174, + 2, // Opcode: VLD2d32wb_fixed + /* 3701 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3716 + /* 3706 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3716 + /* 3711 */ MCD_OPC_Decode, + 179, + 20, + 174, + 2, // Opcode: VLD2d32 + /* 3716 */ MCD_OPC_CheckPredicate, + 26, + 164, + 11, + 0, // Skip to: 6701 + /* 3721 */ MCD_OPC_Decode, + 181, + 20, + 174, + 2, // Opcode: VLD2d32wb_register + /* 3726 */ MCD_OPC_FilterValue, + 233, + 3, + 153, + 11, + 0, // Skip to: 6701 + /* 3732 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 3749 + /* 3737 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 3749 + /* 3744 */ MCD_OPC_Decode, + 139, + 19, + 168, + 2, // Opcode: VLD1LNd32 + /* 3749 */ MCD_OPC_CheckPredicate, + 26, + 131, + 11, + 0, // Skip to: 6701 + /* 3754 */ MCD_OPC_Decode, + 140, + 19, + 168, + 2, // Opcode: VLD1LNd32_UPD + /* 3759 */ MCD_OPC_FilterValue, + 1, + 121, + 11, + 0, // Skip to: 6701 + /* 3764 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3767 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 3832 + /* 3772 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3775 */ MCD_OPC_FilterValue, + 0, + 105, + 11, + 0, // Skip to: 6701 + /* 3780 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3783 */ MCD_OPC_FilterValue, + 232, + 3, + 96, + 11, + 0, // Skip to: 6701 + /* 3789 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3792 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3807 + /* 3797 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3822 + /* 3802 */ MCD_OPC_Decode, + 194, + 28, + 174, + 2, // Opcode: VST2d16wb_fixed + /* 3807 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3822 + /* 3812 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3822 + /* 3817 */ MCD_OPC_Decode, + 193, + 28, + 174, + 2, // Opcode: VST2d16 + /* 3822 */ MCD_OPC_CheckPredicate, + 26, + 58, + 11, + 0, // Skip to: 6701 + /* 3827 */ MCD_OPC_Decode, + 195, + 28, + 174, + 2, // Opcode: VST2d16wb_register + /* 3832 */ MCD_OPC_FilterValue, + 2, + 48, + 11, + 0, // Skip to: 6701 + /* 3837 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3840 */ MCD_OPC_FilterValue, + 0, + 40, + 11, + 0, // Skip to: 6701 + /* 3845 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3848 */ MCD_OPC_FilterValue, + 232, + 3, + 31, + 11, + 0, // Skip to: 6701 + /* 3854 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3857 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3872 + /* 3862 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3887 + /* 3867 */ MCD_OPC_Decode, + 177, + 20, + 174, + 2, // Opcode: VLD2d16wb_fixed + /* 3872 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3887 + /* 3877 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3887 + /* 3882 */ MCD_OPC_Decode, + 176, + 20, + 174, + 2, // Opcode: VLD2d16 + /* 3887 */ MCD_OPC_CheckPredicate, + 26, + 249, + 10, + 0, // Skip to: 6701 + /* 3892 */ MCD_OPC_Decode, + 178, + 20, + 174, + 2, // Opcode: VLD2d16wb_register + /* 3897 */ MCD_OPC_FilterValue, + 9, + 27, + 2, + 0, // Skip to: 4441 + /* 3902 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3905 */ MCD_OPC_FilterValue, + 0, + 55, + 1, + 0, // Skip to: 4221 + /* 3910 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3913 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 4067 + /* 3918 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 3921 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4026 + /* 3927 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 3930 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 3978 + /* 3935 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3938 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3953 + /* 3943 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 3968 + /* 3948 */ MCD_OPC_Decode, + 191, + 28, + 174, + 2, // Opcode: VST2b8wb_fixed + /* 3953 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3968 + /* 3958 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 3968 + /* 3963 */ MCD_OPC_Decode, + 190, + 28, + 174, + 2, // Opcode: VST2b8 + /* 3968 */ MCD_OPC_CheckPredicate, + 26, + 168, + 10, + 0, // Skip to: 6701 + /* 3973 */ MCD_OPC_Decode, + 192, + 28, + 174, + 2, // Opcode: VST2b8wb_register + /* 3978 */ MCD_OPC_FilterValue, + 1, + 158, + 10, + 0, // Skip to: 6701 + /* 3983 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 3986 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4001 + /* 3991 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4016 + /* 3996 */ MCD_OPC_Decode, + 188, + 28, + 174, + 2, // Opcode: VST2b32wb_fixed + /* 4001 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4016 + /* 4006 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4016 + /* 4011 */ MCD_OPC_Decode, + 187, + 28, + 174, + 2, // Opcode: VST2b32 + /* 4016 */ MCD_OPC_CheckPredicate, + 26, + 120, + 10, + 0, // Skip to: 6701 + /* 4021 */ MCD_OPC_Decode, + 189, + 28, + 174, + 2, // Opcode: VST2b32wb_register + /* 4026 */ MCD_OPC_FilterValue, + 233, + 3, + 109, + 10, + 0, // Skip to: 6701 + /* 4032 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 4035 */ MCD_OPC_FilterValue, + 0, + 101, + 10, + 0, // Skip to: 6701 + /* 4040 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4057 + /* 4045 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4057 + /* 4052 */ MCD_OPC_Decode, + 168, + 28, + 169, + 2, // Opcode: VST2LNd32 + /* 4057 */ MCD_OPC_CheckPredicate, + 26, + 79, + 10, + 0, // Skip to: 6701 + /* 4062 */ MCD_OPC_Decode, + 171, + 28, + 169, + 2, // Opcode: VST2LNd32_UPD + /* 4067 */ MCD_OPC_FilterValue, + 2, + 69, + 10, + 0, // Skip to: 6701 + /* 4072 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4075 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4180 + /* 4081 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4084 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4132 + /* 4089 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4092 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4107 + /* 4097 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4122 + /* 4102 */ MCD_OPC_Decode, + 174, + 20, + 174, + 2, // Opcode: VLD2b8wb_fixed + /* 4107 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4122 + /* 4112 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4122 + /* 4117 */ MCD_OPC_Decode, + 173, + 20, + 174, + 2, // Opcode: VLD2b8 + /* 4122 */ MCD_OPC_CheckPredicate, + 26, + 14, + 10, + 0, // Skip to: 6701 + /* 4127 */ MCD_OPC_Decode, + 175, + 20, + 174, + 2, // Opcode: VLD2b8wb_register + /* 4132 */ MCD_OPC_FilterValue, + 1, + 4, + 10, + 0, // Skip to: 6701 + /* 4137 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4140 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4155 + /* 4145 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4170 + /* 4150 */ MCD_OPC_Decode, + 171, + 20, + 174, + 2, // Opcode: VLD2b32wb_fixed + /* 4155 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4170 + /* 4160 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4170 + /* 4165 */ MCD_OPC_Decode, + 170, + 20, + 174, + 2, // Opcode: VLD2b32 + /* 4170 */ MCD_OPC_CheckPredicate, + 26, + 222, + 9, + 0, // Skip to: 6701 + /* 4175 */ MCD_OPC_Decode, + 172, + 20, + 174, + 2, // Opcode: VLD2b32wb_register + /* 4180 */ MCD_OPC_FilterValue, + 233, + 3, + 211, + 9, + 0, // Skip to: 6701 + /* 4186 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 4189 */ MCD_OPC_FilterValue, + 0, + 203, + 9, + 0, // Skip to: 6701 + /* 4194 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4211 + /* 4199 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4211 + /* 4206 */ MCD_OPC_Decode, + 151, + 20, + 170, + 2, // Opcode: VLD2LNd32 + /* 4211 */ MCD_OPC_CheckPredicate, + 26, + 181, + 9, + 0, // Skip to: 6701 + /* 4216 */ MCD_OPC_Decode, + 154, + 20, + 170, + 2, // Opcode: VLD2LNd32_UPD + /* 4221 */ MCD_OPC_FilterValue, + 1, + 171, + 9, + 0, // Skip to: 6701 + /* 4226 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 4229 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 4335 + /* 4234 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4237 */ MCD_OPC_FilterValue, + 232, + 3, + 51, + 0, + 0, // Skip to: 4294 + /* 4243 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4246 */ MCD_OPC_FilterValue, + 0, + 146, + 9, + 0, // Skip to: 6701 + /* 4251 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4254 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4269 + /* 4259 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4284 + /* 4264 */ MCD_OPC_Decode, + 185, + 28, + 174, + 2, // Opcode: VST2b16wb_fixed + /* 4269 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4284 + /* 4274 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4284 + /* 4279 */ MCD_OPC_Decode, + 184, + 28, + 174, + 2, // Opcode: VST2b16 + /* 4284 */ MCD_OPC_CheckPredicate, + 26, + 108, + 9, + 0, // Skip to: 6701 + /* 4289 */ MCD_OPC_Decode, + 186, + 28, + 174, + 2, // Opcode: VST2b16wb_register + /* 4294 */ MCD_OPC_FilterValue, + 233, + 3, + 97, + 9, + 0, // Skip to: 6701 + /* 4300 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 4303 */ MCD_OPC_FilterValue, + 0, + 89, + 9, + 0, // Skip to: 6701 + /* 4308 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4325 + /* 4313 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4325 + /* 4320 */ MCD_OPC_Decode, + 180, + 28, + 169, + 2, // Opcode: VST2LNq32 + /* 4325 */ MCD_OPC_CheckPredicate, + 26, + 67, + 9, + 0, // Skip to: 6701 + /* 4330 */ MCD_OPC_Decode, + 183, + 28, + 169, + 2, // Opcode: VST2LNq32_UPD + /* 4335 */ MCD_OPC_FilterValue, + 2, + 57, + 9, + 0, // Skip to: 6701 + /* 4340 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4343 */ MCD_OPC_FilterValue, + 232, + 3, + 51, + 0, + 0, // Skip to: 4400 + /* 4349 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4352 */ MCD_OPC_FilterValue, + 0, + 40, + 9, + 0, // Skip to: 6701 + /* 4357 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4360 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4375 + /* 4365 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4390 + /* 4370 */ MCD_OPC_Decode, + 168, + 20, + 174, + 2, // Opcode: VLD2b16wb_fixed + /* 4375 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4390 + /* 4380 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4390 + /* 4385 */ MCD_OPC_Decode, + 167, + 20, + 174, + 2, // Opcode: VLD2b16 + /* 4390 */ MCD_OPC_CheckPredicate, + 26, + 2, + 9, + 0, // Skip to: 6701 + /* 4395 */ MCD_OPC_Decode, + 169, + 20, + 174, + 2, // Opcode: VLD2b16wb_register + /* 4400 */ MCD_OPC_FilterValue, + 233, + 3, + 247, + 8, + 0, // Skip to: 6701 + /* 4406 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 4409 */ MCD_OPC_FilterValue, + 0, + 239, + 8, + 0, // Skip to: 6701 + /* 4414 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4431 + /* 4419 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4431 + /* 4426 */ MCD_OPC_Decode, + 163, + 20, + 170, + 2, // Opcode: VLD2LNq32 + /* 4431 */ MCD_OPC_CheckPredicate, + 26, + 217, + 8, + 0, // Skip to: 6701 + /* 4436 */ MCD_OPC_Decode, + 166, + 20, + 170, + 2, // Opcode: VLD2LNq32_UPD + /* 4441 */ MCD_OPC_FilterValue, + 10, + 123, + 2, + 0, // Skip to: 5081 + /* 4446 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 4449 */ MCD_OPC_FilterValue, + 0, + 55, + 1, + 0, // Skip to: 4765 + /* 4454 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 4457 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 4611 + /* 4462 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4465 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4570 + /* 4471 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4474 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4522 + /* 4479 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4482 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4497 + /* 4487 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4512 + /* 4492 */ MCD_OPC_Decode, + 162, + 28, + 171, + 2, // Opcode: VST1q8wb_fixed + /* 4497 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4512 + /* 4502 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4512 + /* 4507 */ MCD_OPC_Decode, + 155, + 28, + 171, + 2, // Opcode: VST1q8 + /* 4512 */ MCD_OPC_CheckPredicate, + 26, + 136, + 8, + 0, // Skip to: 6701 + /* 4517 */ MCD_OPC_Decode, + 163, + 28, + 171, + 2, // Opcode: VST1q8wb_register + /* 4522 */ MCD_OPC_FilterValue, + 1, + 126, + 8, + 0, // Skip to: 6701 + /* 4527 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4530 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4545 + /* 4535 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4560 + /* 4540 */ MCD_OPC_Decode, + 144, + 28, + 171, + 2, // Opcode: VST1q32wb_fixed + /* 4545 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4560 + /* 4550 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4560 + /* 4555 */ MCD_OPC_Decode, + 137, + 28, + 171, + 2, // Opcode: VST1q32 + /* 4560 */ MCD_OPC_CheckPredicate, + 26, + 88, + 8, + 0, // Skip to: 6701 + /* 4565 */ MCD_OPC_Decode, + 145, + 28, + 171, + 2, // Opcode: VST1q32wb_register + /* 4570 */ MCD_OPC_FilterValue, + 233, + 3, + 77, + 8, + 0, // Skip to: 6701 + /* 4576 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 4579 */ MCD_OPC_FilterValue, + 0, + 69, + 8, + 0, // Skip to: 6701 + /* 4584 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4601 + /* 4589 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4601 + /* 4596 */ MCD_OPC_Decode, + 224, + 28, + 172, + 2, // Opcode: VST3LNd32 + /* 4601 */ MCD_OPC_CheckPredicate, + 26, + 47, + 8, + 0, // Skip to: 6701 + /* 4606 */ MCD_OPC_Decode, + 227, + 28, + 172, + 2, // Opcode: VST3LNd32_UPD + /* 4611 */ MCD_OPC_FilterValue, + 2, + 37, + 8, + 0, // Skip to: 6701 + /* 4616 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4619 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4724 + /* 4625 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4628 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4676 + /* 4633 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4636 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4651 + /* 4641 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4666 + /* 4646 */ MCD_OPC_Decode, + 243, + 19, + 171, + 2, // Opcode: VLD1q8wb_fixed + /* 4651 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4666 + /* 4656 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4666 + /* 4661 */ MCD_OPC_Decode, + 236, + 19, + 171, + 2, // Opcode: VLD1q8 + /* 4666 */ MCD_OPC_CheckPredicate, + 26, + 238, + 7, + 0, // Skip to: 6701 + /* 4671 */ MCD_OPC_Decode, + 244, + 19, + 171, + 2, // Opcode: VLD1q8wb_register + /* 4676 */ MCD_OPC_FilterValue, + 1, + 228, + 7, + 0, // Skip to: 6701 + /* 4681 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4684 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4699 + /* 4689 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4714 + /* 4694 */ MCD_OPC_Decode, + 225, + 19, + 171, + 2, // Opcode: VLD1q32wb_fixed + /* 4699 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4714 + /* 4704 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4714 + /* 4709 */ MCD_OPC_Decode, + 218, + 19, + 171, + 2, // Opcode: VLD1q32 + /* 4714 */ MCD_OPC_CheckPredicate, + 26, + 190, + 7, + 0, // Skip to: 6701 + /* 4719 */ MCD_OPC_Decode, + 226, + 19, + 171, + 2, // Opcode: VLD1q32wb_register + /* 4724 */ MCD_OPC_FilterValue, + 233, + 3, + 179, + 7, + 0, // Skip to: 6701 + /* 4730 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 4733 */ MCD_OPC_FilterValue, + 0, + 171, + 7, + 0, // Skip to: 6701 + /* 4738 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4755 + /* 4743 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4755 + /* 4750 */ MCD_OPC_Decode, + 234, + 20, + 173, + 2, // Opcode: VLD3LNd32 + /* 4755 */ MCD_OPC_CheckPredicate, + 26, + 149, + 7, + 0, // Skip to: 6701 + /* 4760 */ MCD_OPC_Decode, + 237, + 20, + 173, + 2, // Opcode: VLD3LNd32_UPD + /* 4765 */ MCD_OPC_FilterValue, + 1, + 139, + 7, + 0, // Skip to: 6701 + /* 4770 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 4773 */ MCD_OPC_FilterValue, + 0, + 149, + 0, + 0, // Skip to: 4927 + /* 4778 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4781 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 4886 + /* 4787 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4790 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4838 + /* 4795 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4798 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4813 + /* 4803 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4828 + /* 4808 */ MCD_OPC_Decode, + 135, + 28, + 171, + 2, // Opcode: VST1q16wb_fixed + /* 4813 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4828 + /* 4818 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4828 + /* 4823 */ MCD_OPC_Decode, + 128, + 28, + 171, + 2, // Opcode: VST1q16 + /* 4828 */ MCD_OPC_CheckPredicate, + 26, + 76, + 7, + 0, // Skip to: 6701 + /* 4833 */ MCD_OPC_Decode, + 136, + 28, + 171, + 2, // Opcode: VST1q16wb_register + /* 4838 */ MCD_OPC_FilterValue, + 1, + 66, + 7, + 0, // Skip to: 6701 + /* 4843 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4846 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4861 + /* 4851 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4876 + /* 4856 */ MCD_OPC_Decode, + 153, + 28, + 171, + 2, // Opcode: VST1q64wb_fixed + /* 4861 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4876 + /* 4866 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4876 + /* 4871 */ MCD_OPC_Decode, + 146, + 28, + 171, + 2, // Opcode: VST1q64 + /* 4876 */ MCD_OPC_CheckPredicate, + 26, + 28, + 7, + 0, // Skip to: 6701 + /* 4881 */ MCD_OPC_Decode, + 154, + 28, + 171, + 2, // Opcode: VST1q64wb_register + /* 4886 */ MCD_OPC_FilterValue, + 233, + 3, + 17, + 7, + 0, // Skip to: 6701 + /* 4892 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 4895 */ MCD_OPC_FilterValue, + 0, + 9, + 7, + 0, // Skip to: 6701 + /* 4900 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 4917 + /* 4905 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 4917 + /* 4912 */ MCD_OPC_Decode, + 236, + 28, + 172, + 2, // Opcode: VST3LNq32 + /* 4917 */ MCD_OPC_CheckPredicate, + 26, + 243, + 6, + 0, // Skip to: 6701 + /* 4922 */ MCD_OPC_Decode, + 239, + 28, + 172, + 2, // Opcode: VST3LNq32_UPD + /* 4927 */ MCD_OPC_FilterValue, + 2, + 233, + 6, + 0, // Skip to: 6701 + /* 4932 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 4935 */ MCD_OPC_FilterValue, + 232, + 3, + 99, + 0, + 0, // Skip to: 5040 + /* 4941 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4944 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 4992 + /* 4949 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 4952 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 4967 + /* 4957 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 4982 + /* 4962 */ MCD_OPC_Decode, + 216, + 19, + 171, + 2, // Opcode: VLD1q16wb_fixed + /* 4967 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 4982 + /* 4972 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 4982 + /* 4977 */ MCD_OPC_Decode, + 209, + 19, + 171, + 2, // Opcode: VLD1q16 + /* 4982 */ MCD_OPC_CheckPredicate, + 26, + 178, + 6, + 0, // Skip to: 6701 + /* 4987 */ MCD_OPC_Decode, + 217, + 19, + 171, + 2, // Opcode: VLD1q16wb_register + /* 4992 */ MCD_OPC_FilterValue, + 1, + 168, + 6, + 0, // Skip to: 6701 + /* 4997 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5000 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5015 + /* 5005 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5030 + /* 5010 */ MCD_OPC_Decode, + 234, + 19, + 171, + 2, // Opcode: VLD1q64wb_fixed + /* 5015 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5030 + /* 5020 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5030 + /* 5025 */ MCD_OPC_Decode, + 227, + 19, + 171, + 2, // Opcode: VLD1q64 + /* 5030 */ MCD_OPC_CheckPredicate, + 26, + 130, + 6, + 0, // Skip to: 6701 + /* 5035 */ MCD_OPC_Decode, + 235, + 19, + 171, + 2, // Opcode: VLD1q64wb_register + /* 5040 */ MCD_OPC_FilterValue, + 233, + 3, + 119, + 6, + 0, // Skip to: 6701 + /* 5046 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 5049 */ MCD_OPC_FilterValue, + 0, + 111, + 6, + 0, // Skip to: 6701 + /* 5054 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5071 + /* 5059 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5071 + /* 5066 */ MCD_OPC_Decode, + 246, + 20, + 173, + 2, // Opcode: VLD3LNq32 + /* 5071 */ MCD_OPC_CheckPredicate, + 26, + 89, + 6, + 0, // Skip to: 6701 + /* 5076 */ MCD_OPC_Decode, + 249, + 20, + 173, + 2, // Opcode: VLD3LNq32_UPD + /* 5081 */ MCD_OPC_FilterValue, + 11, + 183, + 0, + 0, // Skip to: 5269 + /* 5086 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 5089 */ MCD_OPC_FilterValue, + 0, + 85, + 0, + 0, // Skip to: 5179 + /* 5094 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5097 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 5138 + /* 5102 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5105 */ MCD_OPC_FilterValue, + 233, + 3, + 54, + 6, + 0, // Skip to: 6701 + /* 5111 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5128 + /* 5116 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5128 + /* 5123 */ MCD_OPC_Decode, + 143, + 29, + 175, + 2, // Opcode: VST4LNd32 + /* 5128 */ MCD_OPC_CheckPredicate, + 26, + 32, + 6, + 0, // Skip to: 6701 + /* 5133 */ MCD_OPC_Decode, + 146, + 29, + 175, + 2, // Opcode: VST4LNd32_UPD + /* 5138 */ MCD_OPC_FilterValue, + 2, + 22, + 6, + 0, // Skip to: 6701 + /* 5143 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5146 */ MCD_OPC_FilterValue, + 233, + 3, + 13, + 6, + 0, // Skip to: 6701 + /* 5152 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5169 + /* 5157 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5169 + /* 5164 */ MCD_OPC_Decode, + 180, + 21, + 176, + 2, // Opcode: VLD4LNd32 + /* 5169 */ MCD_OPC_CheckPredicate, + 26, + 247, + 5, + 0, // Skip to: 6701 + /* 5174 */ MCD_OPC_Decode, + 183, + 21, + 176, + 2, // Opcode: VLD4LNd32_UPD + /* 5179 */ MCD_OPC_FilterValue, + 1, + 237, + 5, + 0, // Skip to: 6701 + /* 5184 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5187 */ MCD_OPC_FilterValue, + 0, + 36, + 0, + 0, // Skip to: 5228 + /* 5192 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5195 */ MCD_OPC_FilterValue, + 233, + 3, + 220, + 5, + 0, // Skip to: 6701 + /* 5201 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5218 + /* 5206 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5218 + /* 5213 */ MCD_OPC_Decode, + 155, + 29, + 175, + 2, // Opcode: VST4LNq32 + /* 5218 */ MCD_OPC_CheckPredicate, + 26, + 198, + 5, + 0, // Skip to: 6701 + /* 5223 */ MCD_OPC_Decode, + 158, + 29, + 175, + 2, // Opcode: VST4LNq32_UPD + /* 5228 */ MCD_OPC_FilterValue, + 2, + 188, + 5, + 0, // Skip to: 6701 + /* 5233 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5236 */ MCD_OPC_FilterValue, + 233, + 3, + 179, + 5, + 0, // Skip to: 6701 + /* 5242 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 5259 + /* 5247 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 5259 + /* 5254 */ MCD_OPC_Decode, + 192, + 21, + 176, + 2, // Opcode: VLD4LNq32 + /* 5259 */ MCD_OPC_CheckPredicate, + 26, + 157, + 5, + 0, // Skip to: 6701 + /* 5264 */ MCD_OPC_Decode, + 195, + 21, + 176, + 2, // Opcode: VLD4LNq32_UPD + /* 5269 */ MCD_OPC_FilterValue, + 12, + 137, + 1, + 0, // Skip to: 5667 + /* 5274 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 5277 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 5342 + /* 5282 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5285 */ MCD_OPC_FilterValue, + 2, + 131, + 5, + 0, // Skip to: 6701 + /* 5290 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5293 */ MCD_OPC_FilterValue, + 233, + 3, + 122, + 5, + 0, // Skip to: 6701 + /* 5299 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5302 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5317 + /* 5307 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5332 + /* 5312 */ MCD_OPC_Decode, + 254, + 18, + 178, + 2, // Opcode: VLD1DUPd8wb_fixed + /* 5317 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5332 + /* 5322 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5332 + /* 5327 */ MCD_OPC_Decode, + 253, + 18, + 178, + 2, // Opcode: VLD1DUPd8 + /* 5332 */ MCD_OPC_CheckPredicate, + 26, + 84, + 5, + 0, // Skip to: 6701 + /* 5337 */ MCD_OPC_Decode, + 255, + 18, + 178, + 2, // Opcode: VLD1DUPd8wb_register + /* 5342 */ MCD_OPC_FilterValue, + 1, + 60, + 0, + 0, // Skip to: 5407 + /* 5347 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5350 */ MCD_OPC_FilterValue, + 2, + 66, + 5, + 0, // Skip to: 6701 + /* 5355 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5358 */ MCD_OPC_FilterValue, + 233, + 3, + 57, + 5, + 0, // Skip to: 6701 + /* 5364 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5367 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5382 + /* 5372 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5397 + /* 5377 */ MCD_OPC_Decode, + 135, + 19, + 178, + 2, // Opcode: VLD1DUPq8wb_fixed + /* 5382 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5397 + /* 5387 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5397 + /* 5392 */ MCD_OPC_Decode, + 134, + 19, + 178, + 2, // Opcode: VLD1DUPq8 + /* 5397 */ MCD_OPC_CheckPredicate, + 26, + 19, + 5, + 0, // Skip to: 6701 + /* 5402 */ MCD_OPC_Decode, + 136, + 19, + 178, + 2, // Opcode: VLD1DUPq8wb_register + /* 5407 */ MCD_OPC_FilterValue, + 2, + 60, + 0, + 0, // Skip to: 5472 + /* 5412 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5415 */ MCD_OPC_FilterValue, + 2, + 1, + 5, + 0, // Skip to: 6701 + /* 5420 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5423 */ MCD_OPC_FilterValue, + 233, + 3, + 248, + 4, + 0, // Skip to: 6701 + /* 5429 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5432 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5447 + /* 5437 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5462 + /* 5442 */ MCD_OPC_Decode, + 248, + 18, + 178, + 2, // Opcode: VLD1DUPd16wb_fixed + /* 5447 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5462 + /* 5452 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5462 + /* 5457 */ MCD_OPC_Decode, + 247, + 18, + 178, + 2, // Opcode: VLD1DUPd16 + /* 5462 */ MCD_OPC_CheckPredicate, + 26, + 210, + 4, + 0, // Skip to: 6701 + /* 5467 */ MCD_OPC_Decode, + 249, + 18, + 178, + 2, // Opcode: VLD1DUPd16wb_register + /* 5472 */ MCD_OPC_FilterValue, + 3, + 60, + 0, + 0, // Skip to: 5537 + /* 5477 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5480 */ MCD_OPC_FilterValue, + 2, + 192, + 4, + 0, // Skip to: 6701 + /* 5485 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5488 */ MCD_OPC_FilterValue, + 233, + 3, + 183, + 4, + 0, // Skip to: 6701 + /* 5494 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5497 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5512 + /* 5502 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5527 + /* 5507 */ MCD_OPC_Decode, + 129, + 19, + 178, + 2, // Opcode: VLD1DUPq16wb_fixed + /* 5512 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5527 + /* 5517 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5527 + /* 5522 */ MCD_OPC_Decode, + 128, + 19, + 178, + 2, // Opcode: VLD1DUPq16 + /* 5527 */ MCD_OPC_CheckPredicate, + 26, + 145, + 4, + 0, // Skip to: 6701 + /* 5532 */ MCD_OPC_Decode, + 130, + 19, + 178, + 2, // Opcode: VLD1DUPq16wb_register + /* 5537 */ MCD_OPC_FilterValue, + 4, + 60, + 0, + 0, // Skip to: 5602 + /* 5542 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5545 */ MCD_OPC_FilterValue, + 2, + 127, + 4, + 0, // Skip to: 6701 + /* 5550 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5553 */ MCD_OPC_FilterValue, + 233, + 3, + 118, + 4, + 0, // Skip to: 6701 + /* 5559 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5562 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5577 + /* 5567 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5592 + /* 5572 */ MCD_OPC_Decode, + 251, + 18, + 178, + 2, // Opcode: VLD1DUPd32wb_fixed + /* 5577 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5592 + /* 5582 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5592 + /* 5587 */ MCD_OPC_Decode, + 250, + 18, + 178, + 2, // Opcode: VLD1DUPd32 + /* 5592 */ MCD_OPC_CheckPredicate, + 26, + 80, + 4, + 0, // Skip to: 6701 + /* 5597 */ MCD_OPC_Decode, + 252, + 18, + 178, + 2, // Opcode: VLD1DUPd32wb_register + /* 5602 */ MCD_OPC_FilterValue, + 5, + 70, + 4, + 0, // Skip to: 6701 + /* 5607 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5610 */ MCD_OPC_FilterValue, + 2, + 62, + 4, + 0, // Skip to: 6701 + /* 5615 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5618 */ MCD_OPC_FilterValue, + 233, + 3, + 53, + 4, + 0, // Skip to: 6701 + /* 5624 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5627 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5642 + /* 5632 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5657 + /* 5637 */ MCD_OPC_Decode, + 132, + 19, + 178, + 2, // Opcode: VLD1DUPq32wb_fixed + /* 5642 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5657 + /* 5647 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5657 + /* 5652 */ MCD_OPC_Decode, + 131, + 19, + 178, + 2, // Opcode: VLD1DUPq32 + /* 5657 */ MCD_OPC_CheckPredicate, + 26, + 15, + 4, + 0, // Skip to: 6701 + /* 5662 */ MCD_OPC_Decode, + 133, + 19, + 178, + 2, // Opcode: VLD1DUPq32wb_register + /* 5667 */ MCD_OPC_FilterValue, + 13, + 137, + 1, + 0, // Skip to: 6065 + /* 5672 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 5675 */ MCD_OPC_FilterValue, + 0, + 60, + 0, + 0, // Skip to: 5740 + /* 5680 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5683 */ MCD_OPC_FilterValue, + 2, + 245, + 3, + 0, // Skip to: 6701 + /* 5688 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5691 */ MCD_OPC_FilterValue, + 233, + 3, + 236, + 3, + 0, // Skip to: 6701 + /* 5697 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5700 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5715 + /* 5705 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5730 + /* 5710 */ MCD_OPC_Decode, + 130, + 20, + 179, + 2, // Opcode: VLD2DUPd8wb_fixed + /* 5715 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5730 + /* 5720 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5730 + /* 5725 */ MCD_OPC_Decode, + 129, + 20, + 179, + 2, // Opcode: VLD2DUPd8 + /* 5730 */ MCD_OPC_CheckPredicate, + 26, + 198, + 3, + 0, // Skip to: 6701 + /* 5735 */ MCD_OPC_Decode, + 131, + 20, + 179, + 2, // Opcode: VLD2DUPd8wb_register + /* 5740 */ MCD_OPC_FilterValue, + 1, + 60, + 0, + 0, // Skip to: 5805 + /* 5745 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5748 */ MCD_OPC_FilterValue, + 2, + 180, + 3, + 0, // Skip to: 6701 + /* 5753 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5756 */ MCD_OPC_FilterValue, + 233, + 3, + 171, + 3, + 0, // Skip to: 6701 + /* 5762 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5765 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5780 + /* 5770 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5795 + /* 5775 */ MCD_OPC_Decode, + 133, + 20, + 179, + 2, // Opcode: VLD2DUPd8x2wb_fixed + /* 5780 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5795 + /* 5785 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5795 + /* 5790 */ MCD_OPC_Decode, + 132, + 20, + 179, + 2, // Opcode: VLD2DUPd8x2 + /* 5795 */ MCD_OPC_CheckPredicate, + 26, + 133, + 3, + 0, // Skip to: 6701 + /* 5800 */ MCD_OPC_Decode, + 134, + 20, + 179, + 2, // Opcode: VLD2DUPd8x2wb_register + /* 5805 */ MCD_OPC_FilterValue, + 2, + 60, + 0, + 0, // Skip to: 5870 + /* 5810 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5813 */ MCD_OPC_FilterValue, + 2, + 115, + 3, + 0, // Skip to: 6701 + /* 5818 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5821 */ MCD_OPC_FilterValue, + 233, + 3, + 106, + 3, + 0, // Skip to: 6701 + /* 5827 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5830 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5845 + /* 5835 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5860 + /* 5840 */ MCD_OPC_Decode, + 246, + 19, + 179, + 2, // Opcode: VLD2DUPd16wb_fixed + /* 5845 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5860 + /* 5850 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5860 + /* 5855 */ MCD_OPC_Decode, + 245, + 19, + 179, + 2, // Opcode: VLD2DUPd16 + /* 5860 */ MCD_OPC_CheckPredicate, + 26, + 68, + 3, + 0, // Skip to: 6701 + /* 5865 */ MCD_OPC_Decode, + 247, + 19, + 179, + 2, // Opcode: VLD2DUPd16wb_register + /* 5870 */ MCD_OPC_FilterValue, + 3, + 60, + 0, + 0, // Skip to: 5935 + /* 5875 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5878 */ MCD_OPC_FilterValue, + 2, + 50, + 3, + 0, // Skip to: 6701 + /* 5883 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5886 */ MCD_OPC_FilterValue, + 233, + 3, + 41, + 3, + 0, // Skip to: 6701 + /* 5892 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5895 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5910 + /* 5900 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5925 + /* 5905 */ MCD_OPC_Decode, + 249, + 19, + 179, + 2, // Opcode: VLD2DUPd16x2wb_fixed + /* 5910 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5925 + /* 5915 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5925 + /* 5920 */ MCD_OPC_Decode, + 248, + 19, + 179, + 2, // Opcode: VLD2DUPd16x2 + /* 5925 */ MCD_OPC_CheckPredicate, + 26, + 3, + 3, + 0, // Skip to: 6701 + /* 5930 */ MCD_OPC_Decode, + 250, + 19, + 179, + 2, // Opcode: VLD2DUPd16x2wb_register + /* 5935 */ MCD_OPC_FilterValue, + 4, + 60, + 0, + 0, // Skip to: 6000 + /* 5940 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 5943 */ MCD_OPC_FilterValue, + 2, + 241, + 2, + 0, // Skip to: 6701 + /* 5948 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 5951 */ MCD_OPC_FilterValue, + 233, + 3, + 232, + 2, + 0, // Skip to: 6701 + /* 5957 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 5960 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5975 + /* 5965 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 5990 + /* 5970 */ MCD_OPC_Decode, + 252, + 19, + 179, + 2, // Opcode: VLD2DUPd32wb_fixed + /* 5975 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5990 + /* 5980 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 5990 + /* 5985 */ MCD_OPC_Decode, + 251, + 19, + 179, + 2, // Opcode: VLD2DUPd32 + /* 5990 */ MCD_OPC_CheckPredicate, + 26, + 194, + 2, + 0, // Skip to: 6701 + /* 5995 */ MCD_OPC_Decode, + 253, + 19, + 179, + 2, // Opcode: VLD2DUPd32wb_register + /* 6000 */ MCD_OPC_FilterValue, + 5, + 184, + 2, + 0, // Skip to: 6701 + /* 6005 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6008 */ MCD_OPC_FilterValue, + 2, + 176, + 2, + 0, // Skip to: 6701 + /* 6013 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6016 */ MCD_OPC_FilterValue, + 233, + 3, + 167, + 2, + 0, // Skip to: 6701 + /* 6022 */ MCD_OPC_ExtractField, + 0, + 4, // Inst{3-0} ... + /* 6025 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 6040 + /* 6030 */ MCD_OPC_CheckPredicate, + 26, + 20, + 0, + 0, // Skip to: 6055 + /* 6035 */ MCD_OPC_Decode, + 255, + 19, + 179, + 2, // Opcode: VLD2DUPd32x2wb_fixed + /* 6040 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 6055 + /* 6045 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 6055 + /* 6050 */ MCD_OPC_Decode, + 254, + 19, + 179, + 2, // Opcode: VLD2DUPd32x2 + /* 6055 */ MCD_OPC_CheckPredicate, + 26, + 129, + 2, + 0, // Skip to: 6701 + /* 6060 */ MCD_OPC_Decode, + 128, + 20, + 179, + 2, // Opcode: VLD2DUPd32x2wb_register + /* 6065 */ MCD_OPC_FilterValue, + 14, + 41, + 1, + 0, // Skip to: 6367 + /* 6070 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 6073 */ MCD_OPC_FilterValue, + 0, + 44, + 0, + 0, // Skip to: 6122 + /* 6078 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6081 */ MCD_OPC_FilterValue, + 2, + 103, + 2, + 0, // Skip to: 6701 + /* 6086 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6089 */ MCD_OPC_FilterValue, + 233, + 3, + 94, + 2, + 0, // Skip to: 6701 + /* 6095 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6112 + /* 6100 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6112 + /* 6107 */ MCD_OPC_Decode, + 211, + 20, + 180, + 2, // Opcode: VLD3DUPd8 + /* 6112 */ MCD_OPC_CheckPredicate, + 26, + 72, + 2, + 0, // Skip to: 6701 + /* 6117 */ MCD_OPC_Decode, + 214, + 20, + 180, + 2, // Opcode: VLD3DUPd8_UPD + /* 6122 */ MCD_OPC_FilterValue, + 2, + 44, + 0, + 0, // Skip to: 6171 + /* 6127 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6130 */ MCD_OPC_FilterValue, + 2, + 54, + 2, + 0, // Skip to: 6701 + /* 6135 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6138 */ MCD_OPC_FilterValue, + 233, + 3, + 45, + 2, + 0, // Skip to: 6701 + /* 6144 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6161 + /* 6149 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6161 + /* 6156 */ MCD_OPC_Decode, + 225, + 20, + 180, + 2, // Opcode: VLD3DUPq8 + /* 6161 */ MCD_OPC_CheckPredicate, + 26, + 23, + 2, + 0, // Skip to: 6701 + /* 6166 */ MCD_OPC_Decode, + 229, + 20, + 180, + 2, // Opcode: VLD3DUPq8_UPD + /* 6171 */ MCD_OPC_FilterValue, + 4, + 44, + 0, + 0, // Skip to: 6220 + /* 6176 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6179 */ MCD_OPC_FilterValue, + 2, + 5, + 2, + 0, // Skip to: 6701 + /* 6184 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6187 */ MCD_OPC_FilterValue, + 233, + 3, + 252, + 1, + 0, // Skip to: 6701 + /* 6193 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6210 + /* 6198 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6210 + /* 6205 */ MCD_OPC_Decode, + 203, + 20, + 180, + 2, // Opcode: VLD3DUPd16 + /* 6210 */ MCD_OPC_CheckPredicate, + 26, + 230, + 1, + 0, // Skip to: 6701 + /* 6215 */ MCD_OPC_Decode, + 206, + 20, + 180, + 2, // Opcode: VLD3DUPd16_UPD + /* 6220 */ MCD_OPC_FilterValue, + 6, + 44, + 0, + 0, // Skip to: 6269 + /* 6225 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6228 */ MCD_OPC_FilterValue, + 2, + 212, + 1, + 0, // Skip to: 6701 + /* 6233 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6236 */ MCD_OPC_FilterValue, + 233, + 3, + 203, + 1, + 0, // Skip to: 6701 + /* 6242 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6259 + /* 6247 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6259 + /* 6254 */ MCD_OPC_Decode, + 215, + 20, + 180, + 2, // Opcode: VLD3DUPq16 + /* 6259 */ MCD_OPC_CheckPredicate, + 26, + 181, + 1, + 0, // Skip to: 6701 + /* 6264 */ MCD_OPC_Decode, + 219, + 20, + 180, + 2, // Opcode: VLD3DUPq16_UPD + /* 6269 */ MCD_OPC_FilterValue, + 8, + 44, + 0, + 0, // Skip to: 6318 + /* 6274 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6277 */ MCD_OPC_FilterValue, + 2, + 163, + 1, + 0, // Skip to: 6701 + /* 6282 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6285 */ MCD_OPC_FilterValue, + 233, + 3, + 154, + 1, + 0, // Skip to: 6701 + /* 6291 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6308 + /* 6296 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6308 + /* 6303 */ MCD_OPC_Decode, + 207, + 20, + 180, + 2, // Opcode: VLD3DUPd32 + /* 6308 */ MCD_OPC_CheckPredicate, + 26, + 132, + 1, + 0, // Skip to: 6701 + /* 6313 */ MCD_OPC_Decode, + 210, + 20, + 180, + 2, // Opcode: VLD3DUPd32_UPD + /* 6318 */ MCD_OPC_FilterValue, + 10, + 122, + 1, + 0, // Skip to: 6701 + /* 6323 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6326 */ MCD_OPC_FilterValue, + 2, + 114, + 1, + 0, // Skip to: 6701 + /* 6331 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6334 */ MCD_OPC_FilterValue, + 233, + 3, + 105, + 1, + 0, // Skip to: 6701 + /* 6340 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6357 + /* 6345 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6357 + /* 6352 */ MCD_OPC_Decode, + 220, + 20, + 180, + 2, // Opcode: VLD3DUPq32 + /* 6357 */ MCD_OPC_CheckPredicate, + 26, + 83, + 1, + 0, // Skip to: 6701 + /* 6362 */ MCD_OPC_Decode, + 224, + 20, + 180, + 2, // Opcode: VLD3DUPq32_UPD + /* 6367 */ MCD_OPC_FilterValue, + 15, + 73, + 1, + 0, // Skip to: 6701 + /* 6372 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 6375 */ MCD_OPC_FilterValue, + 0, + 158, + 0, + 0, // Skip to: 6538 + /* 6380 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6383 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 6489 + /* 6388 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6391 */ MCD_OPC_FilterValue, + 0, + 44, + 0, + 0, // Skip to: 6440 + /* 6396 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6399 */ MCD_OPC_FilterValue, + 2, + 41, + 1, + 0, // Skip to: 6701 + /* 6404 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6407 */ MCD_OPC_FilterValue, + 233, + 3, + 32, + 1, + 0, // Skip to: 6701 + /* 6413 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6430 + /* 6418 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6430 + /* 6425 */ MCD_OPC_Decode, + 157, + 21, + 181, + 2, // Opcode: VLD4DUPd8 + /* 6430 */ MCD_OPC_CheckPredicate, + 26, + 10, + 1, + 0, // Skip to: 6701 + /* 6435 */ MCD_OPC_Decode, + 160, + 21, + 181, + 2, // Opcode: VLD4DUPd8_UPD + /* 6440 */ MCD_OPC_FilterValue, + 1, + 0, + 1, + 0, // Skip to: 6701 + /* 6445 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6448 */ MCD_OPC_FilterValue, + 2, + 248, + 0, + 0, // Skip to: 6701 + /* 6453 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6456 */ MCD_OPC_FilterValue, + 233, + 3, + 239, + 0, + 0, // Skip to: 6701 + /* 6462 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6479 + /* 6467 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6479 + /* 6474 */ MCD_OPC_Decode, + 149, + 21, + 181, + 2, // Opcode: VLD4DUPd16 + /* 6479 */ MCD_OPC_CheckPredicate, + 26, + 217, + 0, + 0, // Skip to: 6701 + /* 6484 */ MCD_OPC_Decode, + 152, + 21, + 181, + 2, // Opcode: VLD4DUPd16_UPD + /* 6489 */ MCD_OPC_FilterValue, + 1, + 207, + 0, + 0, // Skip to: 6701 + /* 6494 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6497 */ MCD_OPC_FilterValue, + 2, + 199, + 0, + 0, // Skip to: 6701 + /* 6502 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6505 */ MCD_OPC_FilterValue, + 233, + 3, + 190, + 0, + 0, // Skip to: 6701 + /* 6511 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6528 + /* 6516 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6528 + /* 6523 */ MCD_OPC_Decode, + 153, + 21, + 181, + 2, // Opcode: VLD4DUPd32 + /* 6528 */ MCD_OPC_CheckPredicate, + 26, + 168, + 0, + 0, // Skip to: 6701 + /* 6533 */ MCD_OPC_Decode, + 156, + 21, + 181, + 2, // Opcode: VLD4DUPd32_UPD + /* 6538 */ MCD_OPC_FilterValue, + 1, + 158, + 0, + 0, // Skip to: 6701 + /* 6543 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6546 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 6652 + /* 6551 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 6554 */ MCD_OPC_FilterValue, + 0, + 44, + 0, + 0, // Skip to: 6603 + /* 6559 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6562 */ MCD_OPC_FilterValue, + 2, + 134, + 0, + 0, // Skip to: 6701 + /* 6567 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6570 */ MCD_OPC_FilterValue, + 233, + 3, + 125, + 0, + 0, // Skip to: 6701 + /* 6576 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6593 + /* 6581 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6593 + /* 6588 */ MCD_OPC_Decode, + 171, + 21, + 181, + 2, // Opcode: VLD4DUPq8 + /* 6593 */ MCD_OPC_CheckPredicate, + 26, + 103, + 0, + 0, // Skip to: 6701 + /* 6598 */ MCD_OPC_Decode, + 175, + 21, + 181, + 2, // Opcode: VLD4DUPq8_UPD + /* 6603 */ MCD_OPC_FilterValue, + 1, + 93, + 0, + 0, // Skip to: 6701 + /* 6608 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6611 */ MCD_OPC_FilterValue, + 2, + 85, + 0, + 0, // Skip to: 6701 + /* 6616 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6619 */ MCD_OPC_FilterValue, + 233, + 3, + 76, + 0, + 0, // Skip to: 6701 + /* 6625 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6642 + /* 6630 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6642 + /* 6637 */ MCD_OPC_Decode, + 161, + 21, + 181, + 2, // Opcode: VLD4DUPq16 + /* 6642 */ MCD_OPC_CheckPredicate, + 26, + 54, + 0, + 0, // Skip to: 6701 + /* 6647 */ MCD_OPC_Decode, + 165, + 21, + 181, + 2, // Opcode: VLD4DUPq16_UPD + /* 6652 */ MCD_OPC_FilterValue, + 1, + 44, + 0, + 0, // Skip to: 6701 + /* 6657 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 6660 */ MCD_OPC_FilterValue, + 2, + 36, + 0, + 0, // Skip to: 6701 + /* 6665 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 6668 */ MCD_OPC_FilterValue, + 233, + 3, + 27, + 0, + 0, // Skip to: 6701 + /* 6674 */ MCD_OPC_CheckPredicate, + 26, + 12, + 0, + 0, // Skip to: 6691 + /* 6679 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 5, + 0, + 0, // Skip to: 6691 + /* 6686 */ MCD_OPC_Decode, + 166, + 21, + 181, + 2, // Opcode: VLD4DUPq32 + /* 6691 */ MCD_OPC_CheckPredicate, + 26, + 5, + 0, + 0, // Skip to: 6701 + /* 6696 */ MCD_OPC_Decode, + 170, + 21, + 181, + 2, // Opcode: VLD4DUPq32_UPD + /* 6701 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableThumb16[] = { -/* 0 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25 -/* 8 */ MCD_OPC_CheckPredicate, 28, 181, 4, 0, // Skip to: 1218 -/* 13 */ MCD_OPC_CheckField, 6, 6, 0, 174, 4, 0, // Skip to: 1218 -/* 20 */ MCD_OPC_Decode, 236, 24, 207, 1, // Opcode: tMOVSr -/* 25 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 47 -/* 30 */ MCD_OPC_CheckPredicate, 28, 159, 4, 0, // Skip to: 1218 -/* 35 */ MCD_OPC_CheckField, 11, 1, 1, 152, 4, 0, // Skip to: 1218 -/* 42 */ MCD_OPC_Decode, 212, 24, 208, 1, // Opcode: tCMPi8 -/* 47 */ MCD_OPC_FilterValue, 4, 3, 1, 0, // Skip to: 311 -/* 52 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 55 */ MCD_OPC_FilterValue, 0, 236, 0, 0, // Skip to: 296 -/* 60 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 63 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 116 -/* 68 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 71 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 86 -/* 76 */ MCD_OPC_CheckPredicate, 28, 113, 4, 0, // Skip to: 1218 -/* 81 */ MCD_OPC_Decode, 140, 25, 207, 1, // Opcode: tTST -/* 86 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 101 -/* 91 */ MCD_OPC_CheckPredicate, 28, 98, 4, 0, // Skip to: 1218 -/* 96 */ MCD_OPC_Decode, 213, 24, 207, 1, // Opcode: tCMPr -/* 101 */ MCD_OPC_FilterValue, 3, 88, 4, 0, // Skip to: 1218 -/* 106 */ MCD_OPC_CheckPredicate, 28, 83, 4, 0, // Skip to: 1218 -/* 111 */ MCD_OPC_Decode, 210, 24, 207, 1, // Opcode: tCMNz -/* 116 */ MCD_OPC_FilterValue, 4, 51, 0, 0, // Skip to: 172 -/* 121 */ MCD_OPC_CheckPredicate, 28, 12, 0, 0, // Skip to: 138 -/* 126 */ MCD_OPC_CheckField, 3, 4, 13, 5, 0, 0, // Skip to: 138 -/* 133 */ MCD_OPC_Decode, 189, 24, 209, 1, // Opcode: tADDrSP -/* 138 */ MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 162 -/* 143 */ MCD_OPC_CheckField, 7, 1, 1, 12, 0, 0, // Skip to: 162 -/* 150 */ MCD_OPC_CheckField, 0, 3, 5, 5, 0, 0, // Skip to: 162 -/* 157 */ MCD_OPC_Decode, 193, 24, 209, 1, // Opcode: tADDspr -/* 162 */ MCD_OPC_CheckPredicate, 28, 27, 4, 0, // Skip to: 1218 -/* 167 */ MCD_OPC_Decode, 186, 24, 210, 1, // Opcode: tADDhirr -/* 172 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 187 -/* 177 */ MCD_OPC_CheckPredicate, 28, 12, 4, 0, // Skip to: 1218 -/* 182 */ MCD_OPC_Decode, 211, 24, 211, 1, // Opcode: tCMPhir -/* 187 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 202 -/* 192 */ MCD_OPC_CheckPredicate, 28, 253, 3, 0, // Skip to: 1218 -/* 197 */ MCD_OPC_Decode, 238, 24, 211, 1, // Opcode: tMOVr -/* 202 */ MCD_OPC_FilterValue, 7, 243, 3, 0, // Skip to: 1218 -/* 207 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 210 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 248 -/* 215 */ MCD_OPC_CheckPredicate, 29, 15, 0, 0, // Skip to: 235 -/* 220 */ MCD_OPC_CheckField, 2, 1, 1, 8, 0, 0, // Skip to: 235 -/* 227 */ MCD_OPC_SoftFail, 3, 0, -/* 230 */ MCD_OPC_Decode, 206, 24, 212, 1, // Opcode: tBXNS -/* 235 */ MCD_OPC_CheckPredicate, 28, 210, 3, 0, // Skip to: 1218 -/* 240 */ MCD_OPC_SoftFail, 7, 0, -/* 243 */ MCD_OPC_Decode, 205, 24, 212, 1, // Opcode: tBX -/* 248 */ MCD_OPC_FilterValue, 1, 197, 3, 0, // Skip to: 1218 -/* 253 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 256 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 278 -/* 261 */ MCD_OPC_CheckPredicate, 30, 184, 3, 0, // Skip to: 1218 -/* 266 */ MCD_OPC_CheckField, 0, 2, 0, 177, 3, 0, // Skip to: 1218 -/* 273 */ MCD_OPC_Decode, 204, 24, 212, 1, // Opcode: tBLXr -/* 278 */ MCD_OPC_FilterValue, 1, 167, 3, 0, // Skip to: 1218 -/* 283 */ MCD_OPC_CheckPredicate, 29, 162, 3, 0, // Skip to: 1218 -/* 288 */ MCD_OPC_SoftFail, 3, 0, -/* 291 */ MCD_OPC_Decode, 202, 24, 213, 1, // Opcode: tBLXNSr -/* 296 */ MCD_OPC_FilterValue, 1, 149, 3, 0, // Skip to: 1218 -/* 301 */ MCD_OPC_CheckPredicate, 28, 144, 3, 0, // Skip to: 1218 -/* 306 */ MCD_OPC_Decode, 229, 24, 214, 1, // Opcode: tLDRpci -/* 311 */ MCD_OPC_FilterValue, 5, 123, 0, 0, // Skip to: 439 -/* 316 */ MCD_OPC_ExtractField, 9, 3, // Inst{11-9} ... -/* 319 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 334 -/* 324 */ MCD_OPC_CheckPredicate, 28, 121, 3, 0, // Skip to: 1218 -/* 329 */ MCD_OPC_Decode, 130, 25, 215, 1, // Opcode: tSTRr -/* 334 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 349 -/* 339 */ MCD_OPC_CheckPredicate, 28, 106, 3, 0, // Skip to: 1218 -/* 344 */ MCD_OPC_Decode, 128, 25, 215, 1, // Opcode: tSTRHr -/* 349 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 364 -/* 354 */ MCD_OPC_CheckPredicate, 28, 91, 3, 0, // Skip to: 1218 -/* 359 */ MCD_OPC_Decode, 254, 24, 215, 1, // Opcode: tSTRBr -/* 364 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 379 -/* 369 */ MCD_OPC_CheckPredicate, 28, 76, 3, 0, // Skip to: 1218 -/* 374 */ MCD_OPC_Decode, 226, 24, 215, 1, // Opcode: tLDRSB -/* 379 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 394 -/* 384 */ MCD_OPC_CheckPredicate, 28, 61, 3, 0, // Skip to: 1218 -/* 389 */ MCD_OPC_Decode, 230, 24, 215, 1, // Opcode: tLDRr -/* 394 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 409 -/* 399 */ MCD_OPC_CheckPredicate, 28, 46, 3, 0, // Skip to: 1218 -/* 404 */ MCD_OPC_Decode, 225, 24, 215, 1, // Opcode: tLDRHr -/* 409 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 424 -/* 414 */ MCD_OPC_CheckPredicate, 28, 31, 3, 0, // Skip to: 1218 -/* 419 */ MCD_OPC_Decode, 223, 24, 215, 1, // Opcode: tLDRBr -/* 424 */ MCD_OPC_FilterValue, 7, 21, 3, 0, // Skip to: 1218 -/* 429 */ MCD_OPC_CheckPredicate, 28, 16, 3, 0, // Skip to: 1218 -/* 434 */ MCD_OPC_Decode, 227, 24, 215, 1, // Opcode: tLDRSH -/* 439 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 477 -/* 444 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 447 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 462 -/* 452 */ MCD_OPC_CheckPredicate, 28, 249, 2, 0, // Skip to: 1218 -/* 457 */ MCD_OPC_Decode, 129, 25, 216, 1, // Opcode: tSTRi -/* 462 */ MCD_OPC_FilterValue, 1, 239, 2, 0, // Skip to: 1218 -/* 467 */ MCD_OPC_CheckPredicate, 28, 234, 2, 0, // Skip to: 1218 -/* 472 */ MCD_OPC_Decode, 228, 24, 216, 1, // Opcode: tLDRi -/* 477 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 515 -/* 482 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 485 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 500 -/* 490 */ MCD_OPC_CheckPredicate, 28, 211, 2, 0, // Skip to: 1218 -/* 495 */ MCD_OPC_Decode, 253, 24, 216, 1, // Opcode: tSTRBi -/* 500 */ MCD_OPC_FilterValue, 1, 201, 2, 0, // Skip to: 1218 -/* 505 */ MCD_OPC_CheckPredicate, 28, 196, 2, 0, // Skip to: 1218 -/* 510 */ MCD_OPC_Decode, 222, 24, 216, 1, // Opcode: tLDRBi -/* 515 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 553 -/* 520 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 523 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 538 -/* 528 */ MCD_OPC_CheckPredicate, 28, 173, 2, 0, // Skip to: 1218 -/* 533 */ MCD_OPC_Decode, 255, 24, 216, 1, // Opcode: tSTRHi -/* 538 */ MCD_OPC_FilterValue, 1, 163, 2, 0, // Skip to: 1218 -/* 543 */ MCD_OPC_CheckPredicate, 28, 158, 2, 0, // Skip to: 1218 -/* 548 */ MCD_OPC_Decode, 224, 24, 216, 1, // Opcode: tLDRHi -/* 553 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 591 -/* 558 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 561 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 576 -/* 566 */ MCD_OPC_CheckPredicate, 28, 135, 2, 0, // Skip to: 1218 -/* 571 */ MCD_OPC_Decode, 131, 25, 217, 1, // Opcode: tSTRspi -/* 576 */ MCD_OPC_FilterValue, 1, 125, 2, 0, // Skip to: 1218 -/* 581 */ MCD_OPC_CheckPredicate, 28, 120, 2, 0, // Skip to: 1218 -/* 586 */ MCD_OPC_Decode, 231, 24, 217, 1, // Opcode: tLDRspi -/* 591 */ MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 629 -/* 596 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 599 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 614 -/* 604 */ MCD_OPC_CheckPredicate, 28, 97, 2, 0, // Skip to: 1218 -/* 609 */ MCD_OPC_Decode, 194, 24, 218, 1, // Opcode: tADR -/* 614 */ MCD_OPC_FilterValue, 1, 87, 2, 0, // Skip to: 1218 -/* 619 */ MCD_OPC_CheckPredicate, 28, 82, 2, 0, // Skip to: 1218 -/* 624 */ MCD_OPC_Decode, 190, 24, 218, 1, // Opcode: tADDrSPi -/* 629 */ MCD_OPC_FilterValue, 11, 187, 1, 0, // Skip to: 1077 -/* 634 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 637 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 790 -/* 642 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 645 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 775 -/* 650 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 653 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 714 -/* 658 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 676 -/* 666 */ MCD_OPC_CheckPredicate, 28, 35, 2, 0, // Skip to: 1218 -/* 671 */ MCD_OPC_Decode, 192, 24, 219, 1, // Opcode: tADDspi -/* 676 */ MCD_OPC_FilterValue, 1, 25, 2, 0, // Skip to: 1218 -/* 681 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 684 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 699 -/* 689 */ MCD_OPC_CheckPredicate, 31, 12, 2, 0, // Skip to: 1218 -/* 694 */ MCD_OPC_Decode, 138, 25, 207, 1, // Opcode: tSXTH -/* 699 */ MCD_OPC_FilterValue, 1, 2, 2, 0, // Skip to: 1218 -/* 704 */ MCD_OPC_CheckPredicate, 31, 253, 1, 0, // Skip to: 1218 -/* 709 */ MCD_OPC_Decode, 137, 25, 207, 1, // Opcode: tSXTB -/* 714 */ MCD_OPC_FilterValue, 1, 243, 1, 0, // Skip to: 1218 -/* 719 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 722 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 737 -/* 727 */ MCD_OPC_CheckPredicate, 28, 230, 1, 0, // Skip to: 1218 -/* 732 */ MCD_OPC_Decode, 135, 25, 219, 1, // Opcode: tSUBspi -/* 737 */ MCD_OPC_FilterValue, 1, 220, 1, 0, // Skip to: 1218 -/* 742 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 745 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 760 -/* 750 */ MCD_OPC_CheckPredicate, 31, 207, 1, 0, // Skip to: 1218 -/* 755 */ MCD_OPC_Decode, 143, 25, 207, 1, // Opcode: tUXTH -/* 760 */ MCD_OPC_FilterValue, 1, 197, 1, 0, // Skip to: 1218 -/* 765 */ MCD_OPC_CheckPredicate, 31, 192, 1, 0, // Skip to: 1218 -/* 770 */ MCD_OPC_Decode, 142, 25, 207, 1, // Opcode: tUXTB -/* 775 */ MCD_OPC_FilterValue, 1, 182, 1, 0, // Skip to: 1218 -/* 780 */ MCD_OPC_CheckPredicate, 32, 177, 1, 0, // Skip to: 1218 -/* 785 */ MCD_OPC_Decode, 209, 24, 220, 1, // Opcode: tCBZ -/* 790 */ MCD_OPC_FilterValue, 1, 95, 0, 0, // Skip to: 890 -/* 795 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 798 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 813 -/* 803 */ MCD_OPC_CheckPredicate, 28, 154, 1, 0, // Skip to: 1218 -/* 808 */ MCD_OPC_Decode, 244, 24, 221, 1, // Opcode: tPUSH -/* 813 */ MCD_OPC_FilterValue, 1, 144, 1, 0, // Skip to: 1218 -/* 818 */ MCD_OPC_ExtractField, 5, 4, // Inst{8-5} ... -/* 821 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 839 -/* 826 */ MCD_OPC_CheckPredicate, 33, 131, 1, 0, // Skip to: 1218 -/* 831 */ MCD_OPC_SoftFail, 7, 16, -/* 834 */ MCD_OPC_Decode, 149, 23, 222, 1, // Opcode: t2SETPAN -/* 839 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 868 -/* 844 */ MCD_OPC_CheckPredicate, 34, 113, 1, 0, // Skip to: 1218 -/* 849 */ MCD_OPC_CheckField, 4, 1, 1, 106, 1, 0, // Skip to: 1218 -/* 856 */ MCD_OPC_CheckField, 0, 3, 0, 99, 1, 0, // Skip to: 1218 -/* 863 */ MCD_OPC_Decode, 251, 24, 222, 1, // Opcode: tSETEND -/* 868 */ MCD_OPC_FilterValue, 3, 89, 1, 0, // Skip to: 1218 -/* 873 */ MCD_OPC_CheckPredicate, 28, 84, 1, 0, // Skip to: 1218 -/* 878 */ MCD_OPC_CheckField, 3, 1, 0, 77, 1, 0, // Skip to: 1218 -/* 885 */ MCD_OPC_Decode, 214, 24, 223, 1, // Opcode: tCPS -/* 890 */ MCD_OPC_FilterValue, 2, 114, 0, 0, // Skip to: 1009 -/* 895 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 898 */ MCD_OPC_FilterValue, 0, 91, 0, 0, // Skip to: 994 -/* 903 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 906 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 928 -/* 911 */ MCD_OPC_CheckPredicate, 31, 46, 1, 0, // Skip to: 1218 -/* 916 */ MCD_OPC_CheckField, 9, 1, 1, 39, 1, 0, // Skip to: 1218 -/* 923 */ MCD_OPC_Decode, 245, 24, 207, 1, // Opcode: tREV -/* 928 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 950 -/* 933 */ MCD_OPC_CheckPredicate, 31, 24, 1, 0, // Skip to: 1218 -/* 938 */ MCD_OPC_CheckField, 9, 1, 1, 17, 1, 0, // Skip to: 1218 -/* 945 */ MCD_OPC_Decode, 246, 24, 207, 1, // Opcode: tREV16 -/* 950 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 972 -/* 955 */ MCD_OPC_CheckPredicate, 35, 2, 1, 0, // Skip to: 1218 -/* 960 */ MCD_OPC_CheckField, 9, 1, 1, 251, 0, 0, // Skip to: 1218 -/* 967 */ MCD_OPC_Decode, 217, 24, 224, 1, // Opcode: tHLT -/* 972 */ MCD_OPC_FilterValue, 3, 241, 0, 0, // Skip to: 1218 -/* 977 */ MCD_OPC_CheckPredicate, 31, 236, 0, 0, // Skip to: 1218 -/* 982 */ MCD_OPC_CheckField, 9, 1, 1, 229, 0, 0, // Skip to: 1218 -/* 989 */ MCD_OPC_Decode, 247, 24, 207, 1, // Opcode: tREVSH -/* 994 */ MCD_OPC_FilterValue, 1, 219, 0, 0, // Skip to: 1218 -/* 999 */ MCD_OPC_CheckPredicate, 32, 214, 0, 0, // Skip to: 1218 -/* 1004 */ MCD_OPC_Decode, 208, 24, 220, 1, // Opcode: tCBNZ -/* 1009 */ MCD_OPC_FilterValue, 3, 204, 0, 0, // Skip to: 1218 -/* 1014 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 1017 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1032 -/* 1022 */ MCD_OPC_CheckPredicate, 28, 191, 0, 0, // Skip to: 1218 -/* 1027 */ MCD_OPC_Decode, 243, 24, 225, 1, // Opcode: tPOP -/* 1032 */ MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1218 -/* 1037 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 1040 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1055 -/* 1045 */ MCD_OPC_CheckPredicate, 28, 168, 0, 0, // Skip to: 1218 -/* 1050 */ MCD_OPC_Decode, 200, 24, 226, 1, // Opcode: tBKPT -/* 1055 */ MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 1218 -/* 1060 */ MCD_OPC_CheckPredicate, 36, 153, 0, 0, // Skip to: 1218 -/* 1065 */ MCD_OPC_CheckField, 0, 4, 0, 146, 0, 0, // Skip to: 1218 -/* 1072 */ MCD_OPC_Decode, 216, 24, 227, 1, // Opcode: tHINT -/* 1077 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 1115 -/* 1082 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 1085 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1100 -/* 1090 */ MCD_OPC_CheckPredicate, 28, 123, 0, 0, // Skip to: 1218 -/* 1095 */ MCD_OPC_Decode, 252, 24, 228, 1, // Opcode: tSTMIA_UPD -/* 1100 */ MCD_OPC_FilterValue, 1, 113, 0, 0, // Skip to: 1218 -/* 1105 */ MCD_OPC_CheckPredicate, 28, 108, 0, 0, // Skip to: 1218 -/* 1110 */ MCD_OPC_Decode, 221, 24, 229, 1, // Opcode: tLDMIA -/* 1115 */ MCD_OPC_FilterValue, 13, 76, 0, 0, // Skip to: 1196 -/* 1120 */ MCD_OPC_ExtractField, 0, 12, // Inst{11-0} ... -/* 1123 */ MCD_OPC_FilterValue, 249, 29, 9, 0, 0, // Skip to: 1138 -/* 1129 */ MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 1153 -/* 1134 */ MCD_OPC_Decode, 144, 25, 51, // Opcode: t__brkdiv0 -/* 1138 */ MCD_OPC_FilterValue, 254, 29, 9, 0, 0, // Skip to: 1153 -/* 1144 */ MCD_OPC_CheckPredicate, 28, 4, 0, 0, // Skip to: 1153 -/* 1149 */ MCD_OPC_Decode, 139, 25, 51, // Opcode: tTRAP -/* 1153 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1156 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1171 -/* 1161 */ MCD_OPC_CheckPredicate, 28, 20, 0, 0, // Skip to: 1186 -/* 1166 */ MCD_OPC_Decode, 141, 25, 226, 1, // Opcode: tUDF -/* 1171 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1186 -/* 1176 */ MCD_OPC_CheckPredicate, 28, 5, 0, 0, // Skip to: 1186 -/* 1181 */ MCD_OPC_Decode, 136, 25, 226, 1, // Opcode: tSVC -/* 1186 */ MCD_OPC_CheckPredicate, 28, 27, 0, 0, // Skip to: 1218 -/* 1191 */ MCD_OPC_Decode, 207, 24, 230, 1, // Opcode: tBcc -/* 1196 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 1218 -/* 1201 */ MCD_OPC_CheckPredicate, 28, 12, 0, 0, // Skip to: 1218 -/* 1206 */ MCD_OPC_CheckField, 11, 1, 0, 5, 0, 0, // Skip to: 1218 -/* 1213 */ MCD_OPC_Decode, 198, 24, 231, 1, // Opcode: tB -/* 1218 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 25 + /* 8 */ MCD_OPC_CheckPredicate, + 35, + 181, + 4, + 0, // Skip to: 1218 + /* 13 */ MCD_OPC_CheckField, + 6, + 6, + 0, + 174, + 4, + 0, // Skip to: 1218 + /* 20 */ MCD_OPC_Decode, + 142, + 34, + 182, + 2, // Opcode: tMOVSr + /* 25 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 47 + /* 30 */ MCD_OPC_CheckPredicate, + 35, + 159, + 4, + 0, // Skip to: 1218 + /* 35 */ MCD_OPC_CheckField, + 11, + 1, + 1, + 152, + 4, + 0, // Skip to: 1218 + /* 42 */ MCD_OPC_Decode, + 246, + 33, + 183, + 2, // Opcode: tCMPi8 + /* 47 */ MCD_OPC_FilterValue, + 4, + 3, + 1, + 0, // Skip to: 311 + /* 52 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 55 */ MCD_OPC_FilterValue, + 0, + 236, + 0, + 0, // Skip to: 296 + /* 60 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 63 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 116 + /* 68 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 71 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 86 + /* 76 */ MCD_OPC_CheckPredicate, + 35, + 113, + 4, + 0, // Skip to: 1218 + /* 81 */ MCD_OPC_Decode, + 174, + 34, + 182, + 2, // Opcode: tTST + /* 86 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 101 + /* 91 */ MCD_OPC_CheckPredicate, + 35, + 98, + 4, + 0, // Skip to: 1218 + /* 96 */ MCD_OPC_Decode, + 247, + 33, + 182, + 2, // Opcode: tCMPr + /* 101 */ MCD_OPC_FilterValue, + 3, + 88, + 4, + 0, // Skip to: 1218 + /* 106 */ MCD_OPC_CheckPredicate, + 35, + 83, + 4, + 0, // Skip to: 1218 + /* 111 */ MCD_OPC_Decode, + 244, + 33, + 182, + 2, // Opcode: tCMNz + /* 116 */ MCD_OPC_FilterValue, + 4, + 51, + 0, + 0, // Skip to: 172 + /* 121 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 138 + /* 126 */ MCD_OPC_CheckField, + 3, + 4, + 13, + 5, + 0, + 0, // Skip to: 138 + /* 133 */ MCD_OPC_Decode, + 223, + 33, + 184, + 2, // Opcode: tADDrSP + /* 138 */ MCD_OPC_CheckPredicate, + 35, + 19, + 0, + 0, // Skip to: 162 + /* 143 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 12, + 0, + 0, // Skip to: 162 + /* 150 */ MCD_OPC_CheckField, + 0, + 3, + 5, + 5, + 0, + 0, // Skip to: 162 + /* 157 */ MCD_OPC_Decode, + 227, + 33, + 184, + 2, // Opcode: tADDspr + /* 162 */ MCD_OPC_CheckPredicate, + 35, + 27, + 4, + 0, // Skip to: 1218 + /* 167 */ MCD_OPC_Decode, + 220, + 33, + 185, + 2, // Opcode: tADDhirr + /* 172 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 187 + /* 177 */ MCD_OPC_CheckPredicate, + 35, + 12, + 4, + 0, // Skip to: 1218 + /* 182 */ MCD_OPC_Decode, + 245, + 33, + 186, + 2, // Opcode: tCMPhir + /* 187 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 202 + /* 192 */ MCD_OPC_CheckPredicate, + 35, + 253, + 3, + 0, // Skip to: 1218 + /* 197 */ MCD_OPC_Decode, + 144, + 34, + 186, + 2, // Opcode: tMOVr + /* 202 */ MCD_OPC_FilterValue, + 7, + 243, + 3, + 0, // Skip to: 1218 + /* 207 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 210 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 248 + /* 215 */ MCD_OPC_CheckPredicate, + 36, + 15, + 0, + 0, // Skip to: 235 + /* 220 */ MCD_OPC_CheckField, + 2, + 1, + 1, + 8, + 0, + 0, // Skip to: 235 + /* 227 */ MCD_OPC_SoftFail, + 3, + 0, + /* 230 */ MCD_OPC_Decode, + 240, + 33, + 187, + 2, // Opcode: tBXNS + /* 235 */ MCD_OPC_CheckPredicate, + 35, + 210, + 3, + 0, // Skip to: 1218 + /* 240 */ MCD_OPC_SoftFail, + 7, + 0, + /* 243 */ MCD_OPC_Decode, + 239, + 33, + 187, + 2, // Opcode: tBX + /* 248 */ MCD_OPC_FilterValue, + 1, + 197, + 3, + 0, // Skip to: 1218 + /* 253 */ MCD_OPC_ExtractField, + 2, + 1, // Inst{2} ... + /* 256 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 278 + /* 261 */ MCD_OPC_CheckPredicate, + 37, + 184, + 3, + 0, // Skip to: 1218 + /* 266 */ MCD_OPC_CheckField, + 0, + 2, + 0, + 177, + 3, + 0, // Skip to: 1218 + /* 273 */ MCD_OPC_Decode, + 238, + 33, + 187, + 2, // Opcode: tBLXr + /* 278 */ MCD_OPC_FilterValue, + 1, + 167, + 3, + 0, // Skip to: 1218 + /* 283 */ MCD_OPC_CheckPredicate, + 36, + 162, + 3, + 0, // Skip to: 1218 + /* 288 */ MCD_OPC_SoftFail, + 3, + 0, + /* 291 */ MCD_OPC_Decode, + 236, + 33, + 188, + 2, // Opcode: tBLXNSr + /* 296 */ MCD_OPC_FilterValue, + 1, + 149, + 3, + 0, // Skip to: 1218 + /* 301 */ MCD_OPC_CheckPredicate, + 35, + 144, + 3, + 0, // Skip to: 1218 + /* 306 */ MCD_OPC_Decode, + 135, + 34, + 189, + 2, // Opcode: tLDRpci + /* 311 */ MCD_OPC_FilterValue, + 5, + 123, + 0, + 0, // Skip to: 439 + /* 316 */ MCD_OPC_ExtractField, + 9, + 3, // Inst{11-9} ... + /* 319 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 334 + /* 324 */ MCD_OPC_CheckPredicate, + 35, + 121, + 3, + 0, // Skip to: 1218 + /* 329 */ MCD_OPC_Decode, + 164, + 34, + 190, + 2, // Opcode: tSTRr + /* 334 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 349 + /* 339 */ MCD_OPC_CheckPredicate, + 35, + 106, + 3, + 0, // Skip to: 1218 + /* 344 */ MCD_OPC_Decode, + 162, + 34, + 190, + 2, // Opcode: tSTRHr + /* 349 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 364 + /* 354 */ MCD_OPC_CheckPredicate, + 35, + 91, + 3, + 0, // Skip to: 1218 + /* 359 */ MCD_OPC_Decode, + 160, + 34, + 190, + 2, // Opcode: tSTRBr + /* 364 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 379 + /* 369 */ MCD_OPC_CheckPredicate, + 35, + 76, + 3, + 0, // Skip to: 1218 + /* 374 */ MCD_OPC_Decode, + 132, + 34, + 190, + 2, // Opcode: tLDRSB + /* 379 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 394 + /* 384 */ MCD_OPC_CheckPredicate, + 35, + 61, + 3, + 0, // Skip to: 1218 + /* 389 */ MCD_OPC_Decode, + 136, + 34, + 190, + 2, // Opcode: tLDRr + /* 394 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 409 + /* 399 */ MCD_OPC_CheckPredicate, + 35, + 46, + 3, + 0, // Skip to: 1218 + /* 404 */ MCD_OPC_Decode, + 131, + 34, + 190, + 2, // Opcode: tLDRHr + /* 409 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 424 + /* 414 */ MCD_OPC_CheckPredicate, + 35, + 31, + 3, + 0, // Skip to: 1218 + /* 419 */ MCD_OPC_Decode, + 129, + 34, + 190, + 2, // Opcode: tLDRBr + /* 424 */ MCD_OPC_FilterValue, + 7, + 21, + 3, + 0, // Skip to: 1218 + /* 429 */ MCD_OPC_CheckPredicate, + 35, + 16, + 3, + 0, // Skip to: 1218 + /* 434 */ MCD_OPC_Decode, + 133, + 34, + 190, + 2, // Opcode: tLDRSH + /* 439 */ MCD_OPC_FilterValue, + 6, + 33, + 0, + 0, // Skip to: 477 + /* 444 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 447 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 462 + /* 452 */ MCD_OPC_CheckPredicate, + 35, + 249, + 2, + 0, // Skip to: 1218 + /* 457 */ MCD_OPC_Decode, + 163, + 34, + 191, + 2, // Opcode: tSTRi + /* 462 */ MCD_OPC_FilterValue, + 1, + 239, + 2, + 0, // Skip to: 1218 + /* 467 */ MCD_OPC_CheckPredicate, + 35, + 234, + 2, + 0, // Skip to: 1218 + /* 472 */ MCD_OPC_Decode, + 134, + 34, + 191, + 2, // Opcode: tLDRi + /* 477 */ MCD_OPC_FilterValue, + 7, + 33, + 0, + 0, // Skip to: 515 + /* 482 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 485 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 500 + /* 490 */ MCD_OPC_CheckPredicate, + 35, + 211, + 2, + 0, // Skip to: 1218 + /* 495 */ MCD_OPC_Decode, + 159, + 34, + 191, + 2, // Opcode: tSTRBi + /* 500 */ MCD_OPC_FilterValue, + 1, + 201, + 2, + 0, // Skip to: 1218 + /* 505 */ MCD_OPC_CheckPredicate, + 35, + 196, + 2, + 0, // Skip to: 1218 + /* 510 */ MCD_OPC_Decode, + 128, + 34, + 191, + 2, // Opcode: tLDRBi + /* 515 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 553 + /* 520 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 523 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 538 + /* 528 */ MCD_OPC_CheckPredicate, + 35, + 173, + 2, + 0, // Skip to: 1218 + /* 533 */ MCD_OPC_Decode, + 161, + 34, + 191, + 2, // Opcode: tSTRHi + /* 538 */ MCD_OPC_FilterValue, + 1, + 163, + 2, + 0, // Skip to: 1218 + /* 543 */ MCD_OPC_CheckPredicate, + 35, + 158, + 2, + 0, // Skip to: 1218 + /* 548 */ MCD_OPC_Decode, + 130, + 34, + 191, + 2, // Opcode: tLDRHi + /* 553 */ MCD_OPC_FilterValue, + 9, + 33, + 0, + 0, // Skip to: 591 + /* 558 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 561 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 576 + /* 566 */ MCD_OPC_CheckPredicate, + 35, + 135, + 2, + 0, // Skip to: 1218 + /* 571 */ MCD_OPC_Decode, + 165, + 34, + 192, + 2, // Opcode: tSTRspi + /* 576 */ MCD_OPC_FilterValue, + 1, + 125, + 2, + 0, // Skip to: 1218 + /* 581 */ MCD_OPC_CheckPredicate, + 35, + 120, + 2, + 0, // Skip to: 1218 + /* 586 */ MCD_OPC_Decode, + 137, + 34, + 192, + 2, // Opcode: tLDRspi + /* 591 */ MCD_OPC_FilterValue, + 10, + 33, + 0, + 0, // Skip to: 629 + /* 596 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 599 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 614 + /* 604 */ MCD_OPC_CheckPredicate, + 35, + 97, + 2, + 0, // Skip to: 1218 + /* 609 */ MCD_OPC_Decode, + 228, + 33, + 193, + 2, // Opcode: tADR + /* 614 */ MCD_OPC_FilterValue, + 1, + 87, + 2, + 0, // Skip to: 1218 + /* 619 */ MCD_OPC_CheckPredicate, + 35, + 82, + 2, + 0, // Skip to: 1218 + /* 624 */ MCD_OPC_Decode, + 224, + 33, + 193, + 2, // Opcode: tADDrSPi + /* 629 */ MCD_OPC_FilterValue, + 11, + 187, + 1, + 0, // Skip to: 1077 + /* 634 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 637 */ MCD_OPC_FilterValue, + 0, + 148, + 0, + 0, // Skip to: 790 + /* 642 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 645 */ MCD_OPC_FilterValue, + 0, + 125, + 0, + 0, // Skip to: 775 + /* 650 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 653 */ MCD_OPC_FilterValue, + 0, + 56, + 0, + 0, // Skip to: 714 + /* 658 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 661 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 676 + /* 666 */ MCD_OPC_CheckPredicate, + 35, + 35, + 2, + 0, // Skip to: 1218 + /* 671 */ MCD_OPC_Decode, + 226, + 33, + 194, + 2, // Opcode: tADDspi + /* 676 */ MCD_OPC_FilterValue, + 1, + 25, + 2, + 0, // Skip to: 1218 + /* 681 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 684 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 699 + /* 689 */ MCD_OPC_CheckPredicate, + 38, + 12, + 2, + 0, // Skip to: 1218 + /* 694 */ MCD_OPC_Decode, + 172, + 34, + 182, + 2, // Opcode: tSXTH + /* 699 */ MCD_OPC_FilterValue, + 1, + 2, + 2, + 0, // Skip to: 1218 + /* 704 */ MCD_OPC_CheckPredicate, + 38, + 253, + 1, + 0, // Skip to: 1218 + /* 709 */ MCD_OPC_Decode, + 171, + 34, + 182, + 2, // Opcode: tSXTB + /* 714 */ MCD_OPC_FilterValue, + 1, + 243, + 1, + 0, // Skip to: 1218 + /* 719 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 722 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 737 + /* 727 */ MCD_OPC_CheckPredicate, + 35, + 230, + 1, + 0, // Skip to: 1218 + /* 732 */ MCD_OPC_Decode, + 169, + 34, + 194, + 2, // Opcode: tSUBspi + /* 737 */ MCD_OPC_FilterValue, + 1, + 220, + 1, + 0, // Skip to: 1218 + /* 742 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 745 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 760 + /* 750 */ MCD_OPC_CheckPredicate, + 38, + 207, + 1, + 0, // Skip to: 1218 + /* 755 */ MCD_OPC_Decode, + 177, + 34, + 182, + 2, // Opcode: tUXTH + /* 760 */ MCD_OPC_FilterValue, + 1, + 197, + 1, + 0, // Skip to: 1218 + /* 765 */ MCD_OPC_CheckPredicate, + 38, + 192, + 1, + 0, // Skip to: 1218 + /* 770 */ MCD_OPC_Decode, + 176, + 34, + 182, + 2, // Opcode: tUXTB + /* 775 */ MCD_OPC_FilterValue, + 1, + 182, + 1, + 0, // Skip to: 1218 + /* 780 */ MCD_OPC_CheckPredicate, + 39, + 177, + 1, + 0, // Skip to: 1218 + /* 785 */ MCD_OPC_Decode, + 243, + 33, + 195, + 2, // Opcode: tCBZ + /* 790 */ MCD_OPC_FilterValue, + 1, + 95, + 0, + 0, // Skip to: 890 + /* 795 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 798 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 813 + /* 803 */ MCD_OPC_CheckPredicate, + 35, + 154, + 1, + 0, // Skip to: 1218 + /* 808 */ MCD_OPC_Decode, + 150, + 34, + 196, + 2, // Opcode: tPUSH + /* 813 */ MCD_OPC_FilterValue, + 1, + 144, + 1, + 0, // Skip to: 1218 + /* 818 */ MCD_OPC_ExtractField, + 5, + 4, // Inst{8-5} ... + /* 821 */ MCD_OPC_FilterValue, + 0, + 13, + 0, + 0, // Skip to: 839 + /* 826 */ MCD_OPC_CheckPredicate, + 40, + 131, + 1, + 0, // Skip to: 1218 + /* 831 */ MCD_OPC_SoftFail, + 7, + 16, + /* 834 */ MCD_OPC_Decode, + 180, + 32, + 197, + 2, // Opcode: t2SETPAN + /* 839 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 868 + /* 844 */ MCD_OPC_CheckPredicate, + 41, + 113, + 1, + 0, // Skip to: 1218 + /* 849 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 106, + 1, + 0, // Skip to: 1218 + /* 856 */ MCD_OPC_CheckField, + 0, + 3, + 0, + 99, + 1, + 0, // Skip to: 1218 + /* 863 */ MCD_OPC_Decode, + 157, + 34, + 197, + 2, // Opcode: tSETEND + /* 868 */ MCD_OPC_FilterValue, + 3, + 89, + 1, + 0, // Skip to: 1218 + /* 873 */ MCD_OPC_CheckPredicate, + 35, + 84, + 1, + 0, // Skip to: 1218 + /* 878 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 77, + 1, + 0, // Skip to: 1218 + /* 885 */ MCD_OPC_Decode, + 248, + 33, + 198, + 2, // Opcode: tCPS + /* 890 */ MCD_OPC_FilterValue, + 2, + 114, + 0, + 0, // Skip to: 1009 + /* 895 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 898 */ MCD_OPC_FilterValue, + 0, + 91, + 0, + 0, // Skip to: 994 + /* 903 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 906 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 928 + /* 911 */ MCD_OPC_CheckPredicate, + 38, + 46, + 1, + 0, // Skip to: 1218 + /* 916 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 39, + 1, + 0, // Skip to: 1218 + /* 923 */ MCD_OPC_Decode, + 151, + 34, + 182, + 2, // Opcode: tREV + /* 928 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 950 + /* 933 */ MCD_OPC_CheckPredicate, + 38, + 24, + 1, + 0, // Skip to: 1218 + /* 938 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 17, + 1, + 0, // Skip to: 1218 + /* 945 */ MCD_OPC_Decode, + 152, + 34, + 182, + 2, // Opcode: tREV16 + /* 950 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 972 + /* 955 */ MCD_OPC_CheckPredicate, + 42, + 2, + 1, + 0, // Skip to: 1218 + /* 960 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 251, + 0, + 0, // Skip to: 1218 + /* 967 */ MCD_OPC_Decode, + 251, + 33, + 199, + 2, // Opcode: tHLT + /* 972 */ MCD_OPC_FilterValue, + 3, + 241, + 0, + 0, // Skip to: 1218 + /* 977 */ MCD_OPC_CheckPredicate, + 38, + 236, + 0, + 0, // Skip to: 1218 + /* 982 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 229, + 0, + 0, // Skip to: 1218 + /* 989 */ MCD_OPC_Decode, + 153, + 34, + 182, + 2, // Opcode: tREVSH + /* 994 */ MCD_OPC_FilterValue, + 1, + 219, + 0, + 0, // Skip to: 1218 + /* 999 */ MCD_OPC_CheckPredicate, + 39, + 214, + 0, + 0, // Skip to: 1218 + /* 1004 */ MCD_OPC_Decode, + 242, + 33, + 195, + 2, // Opcode: tCBNZ + /* 1009 */ MCD_OPC_FilterValue, + 3, + 204, + 0, + 0, // Skip to: 1218 + /* 1014 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 1017 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1032 + /* 1022 */ MCD_OPC_CheckPredicate, + 35, + 191, + 0, + 0, // Skip to: 1218 + /* 1027 */ MCD_OPC_Decode, + 149, + 34, + 200, + 2, // Opcode: tPOP + /* 1032 */ MCD_OPC_FilterValue, + 1, + 181, + 0, + 0, // Skip to: 1218 + /* 1037 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 1040 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1055 + /* 1045 */ MCD_OPC_CheckPredicate, + 35, + 168, + 0, + 0, // Skip to: 1218 + /* 1050 */ MCD_OPC_Decode, + 234, + 33, + 201, + 2, // Opcode: tBKPT + /* 1055 */ MCD_OPC_FilterValue, + 1, + 158, + 0, + 0, // Skip to: 1218 + /* 1060 */ MCD_OPC_CheckPredicate, + 43, + 153, + 0, + 0, // Skip to: 1218 + /* 1065 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 146, + 0, + 0, // Skip to: 1218 + /* 1072 */ MCD_OPC_Decode, + 250, + 33, + 202, + 2, // Opcode: tHINT + /* 1077 */ MCD_OPC_FilterValue, + 12, + 33, + 0, + 0, // Skip to: 1115 + /* 1082 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 1085 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1100 + /* 1090 */ MCD_OPC_CheckPredicate, + 35, + 123, + 0, + 0, // Skip to: 1218 + /* 1095 */ MCD_OPC_Decode, + 158, + 34, + 203, + 2, // Opcode: tSTMIA_UPD + /* 1100 */ MCD_OPC_FilterValue, + 1, + 113, + 0, + 0, // Skip to: 1218 + /* 1105 */ MCD_OPC_CheckPredicate, + 35, + 108, + 0, + 0, // Skip to: 1218 + /* 1110 */ MCD_OPC_Decode, + 255, + 33, + 204, + 2, // Opcode: tLDMIA + /* 1115 */ MCD_OPC_FilterValue, + 13, + 76, + 0, + 0, // Skip to: 1196 + /* 1120 */ MCD_OPC_ExtractField, + 0, + 12, // Inst{11-0} ... + /* 1123 */ MCD_OPC_FilterValue, + 249, + 29, + 9, + 0, + 0, // Skip to: 1138 + /* 1129 */ MCD_OPC_CheckPredicate, + 35, + 19, + 0, + 0, // Skip to: 1153 + /* 1134 */ MCD_OPC_Decode, + 178, + 34, + 51, // Opcode: t__brkdiv0 + /* 1138 */ MCD_OPC_FilterValue, + 254, + 29, + 9, + 0, + 0, // Skip to: 1153 + /* 1144 */ MCD_OPC_CheckPredicate, + 35, + 4, + 0, + 0, // Skip to: 1153 + /* 1149 */ MCD_OPC_Decode, + 173, + 34, + 51, // Opcode: tTRAP + /* 1153 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 1156 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1171 + /* 1161 */ MCD_OPC_CheckPredicate, + 35, + 20, + 0, + 0, // Skip to: 1186 + /* 1166 */ MCD_OPC_Decode, + 175, + 34, + 201, + 2, // Opcode: tUDF + /* 1171 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1186 + /* 1176 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 1186 + /* 1181 */ MCD_OPC_Decode, + 170, + 34, + 201, + 2, // Opcode: tSVC + /* 1186 */ MCD_OPC_CheckPredicate, + 35, + 27, + 0, + 0, // Skip to: 1218 + /* 1191 */ MCD_OPC_Decode, + 241, + 33, + 205, + 2, // Opcode: tBcc + /* 1196 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 1218 + /* 1201 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 1218 + /* 1206 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 5, + 0, + 0, // Skip to: 1218 + /* 1213 */ MCD_OPC_Decode, + 232, + 33, + 206, + 2, // Opcode: tB + /* 1218 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableThumb32[] = { -/* 0 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 3 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 39 -/* 8 */ MCD_OPC_CheckPredicate, 37, 55, 0, 0, // Skip to: 68 -/* 13 */ MCD_OPC_CheckField, 27, 5, 30, 48, 0, 0, // Skip to: 68 -/* 20 */ MCD_OPC_CheckField, 14, 2, 3, 41, 0, 0, // Skip to: 68 -/* 27 */ MCD_OPC_CheckField, 0, 1, 0, 34, 0, 0, // Skip to: 68 -/* 34 */ MCD_OPC_Decode, 203, 24, 232, 1, // Opcode: tBLXi -/* 39 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 68 -/* 44 */ MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 68 -/* 49 */ MCD_OPC_CheckField, 27, 5, 30, 12, 0, 0, // Skip to: 68 -/* 56 */ MCD_OPC_CheckField, 14, 2, 3, 5, 0, 0, // Skip to: 68 -/* 63 */ MCD_OPC_Decode, 201, 24, 233, 1, // Opcode: tBL -/* 68 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 39 + /* 8 */ MCD_OPC_CheckPredicate, + 44, + 55, + 0, + 0, // Skip to: 68 + /* 13 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 48, + 0, + 0, // Skip to: 68 + /* 20 */ MCD_OPC_CheckField, + 14, + 2, + 3, + 41, + 0, + 0, // Skip to: 68 + /* 27 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 34, + 0, + 0, // Skip to: 68 + /* 34 */ MCD_OPC_Decode, + 237, + 33, + 207, + 2, // Opcode: tBLXi + /* 39 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 68 + /* 44 */ MCD_OPC_CheckPredicate, + 35, + 19, + 0, + 0, // Skip to: 68 + /* 49 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 12, + 0, + 0, // Skip to: 68 + /* 56 */ MCD_OPC_CheckField, + 14, + 2, + 3, + 5, + 0, + 0, // Skip to: 68 + /* 63 */ MCD_OPC_Decode, + 235, + 33, + 208, + 2, // Opcode: tBL + /* 68 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableThumb216[] = { -/* 0 */ MCD_OPC_CheckPredicate, 38, 13, 0, 0, // Skip to: 18 -/* 5 */ MCD_OPC_CheckField, 8, 8, 191, 1, 5, 0, 0, // Skip to: 18 -/* 13 */ MCD_OPC_Decode, 250, 21, 234, 1, // Opcode: t2IT -/* 18 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_CheckPredicate, + 45, + 13, + 0, + 0, // Skip to: 18 + /* 5 */ MCD_OPC_CheckField, + 8, + 8, + 191, + 1, + 5, + 0, + 0, // Skip to: 18 + /* 13 */ MCD_OPC_Decode, + 150, + 31, + 209, + 2, // Opcode: t2IT + /* 18 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableThumb232[] = { -/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... -/* 3 */ MCD_OPC_FilterValue, 29, 124, 8, 0, // Skip to: 2180 -/* 8 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 11 */ MCD_OPC_FilterValue, 0, 223, 1, 0, // Skip to: 495 -/* 16 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... -/* 19 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 73 -/* 24 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 27 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 50 -/* 32 */ MCD_OPC_CheckPredicate, 39, 210, 31, 0, // Skip to: 8183 -/* 37 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 201, 31, 0, // Skip to: 8183 -/* 46 */ MCD_OPC_Decode, 194, 23, 83, // Opcode: t2SRSDB -/* 50 */ MCD_OPC_FilterValue, 1, 192, 31, 0, // Skip to: 8183 -/* 55 */ MCD_OPC_CheckPredicate, 39, 187, 31, 0, // Skip to: 8183 -/* 60 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 178, 31, 0, // Skip to: 8183 -/* 69 */ MCD_OPC_Decode, 130, 23, 81, // Opcode: t2RFEDB -/* 73 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 125 -/* 78 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 81 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 110 -/* 86 */ MCD_OPC_CheckPredicate, 38, 156, 31, 0, // Skip to: 8183 -/* 91 */ MCD_OPC_CheckField, 15, 1, 0, 149, 31, 0, // Skip to: 8183 -/* 98 */ MCD_OPC_CheckField, 13, 1, 0, 142, 31, 0, // Skip to: 8183 -/* 105 */ MCD_OPC_Decode, 228, 23, 235, 1, // Opcode: t2STMIA -/* 110 */ MCD_OPC_FilterValue, 1, 132, 31, 0, // Skip to: 8183 -/* 115 */ MCD_OPC_CheckPredicate, 38, 127, 31, 0, // Skip to: 8183 -/* 120 */ MCD_OPC_Decode, 150, 22, 236, 1, // Opcode: t2LDMIA -/* 125 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 177 -/* 130 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 133 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 162 -/* 138 */ MCD_OPC_CheckPredicate, 38, 104, 31, 0, // Skip to: 8183 -/* 143 */ MCD_OPC_CheckField, 15, 1, 0, 97, 31, 0, // Skip to: 8183 -/* 150 */ MCD_OPC_CheckField, 13, 1, 0, 90, 31, 0, // Skip to: 8183 -/* 157 */ MCD_OPC_Decode, 226, 23, 235, 1, // Opcode: t2STMDB -/* 162 */ MCD_OPC_FilterValue, 1, 80, 31, 0, // Skip to: 8183 -/* 167 */ MCD_OPC_CheckPredicate, 38, 75, 31, 0, // Skip to: 8183 -/* 172 */ MCD_OPC_Decode, 148, 22, 236, 1, // Opcode: t2LDMDB -/* 177 */ MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 231 -/* 182 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 185 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 208 -/* 190 */ MCD_OPC_CheckPredicate, 39, 52, 31, 0, // Skip to: 8183 -/* 195 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 43, 31, 0, // Skip to: 8183 -/* 204 */ MCD_OPC_Decode, 196, 23, 83, // Opcode: t2SRSIA -/* 208 */ MCD_OPC_FilterValue, 1, 34, 31, 0, // Skip to: 8183 -/* 213 */ MCD_OPC_CheckPredicate, 39, 29, 31, 0, // Skip to: 8183 -/* 218 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 20, 31, 0, // Skip to: 8183 -/* 227 */ MCD_OPC_Decode, 132, 23, 81, // Opcode: t2RFEIA -/* 231 */ MCD_OPC_FilterValue, 4, 83, 0, 0, // Skip to: 319 -/* 236 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 261 -/* 241 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 261 -/* 248 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 261 -/* 256 */ MCD_OPC_Decode, 145, 24, 237, 1, // Opcode: t2TSTrr -/* 261 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 285 -/* 266 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 285 -/* 273 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 285 -/* 280 */ MCD_OPC_Decode, 146, 24, 238, 1, // Opcode: t2TSTrs -/* 285 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 309 -/* 290 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 309 -/* 297 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 309 -/* 304 */ MCD_OPC_Decode, 207, 21, 239, 1, // Opcode: t2ANDrr -/* 309 */ MCD_OPC_CheckPredicate, 38, 189, 30, 0, // Skip to: 8183 -/* 314 */ MCD_OPC_Decode, 208, 21, 240, 1, // Opcode: t2ANDrs -/* 319 */ MCD_OPC_FilterValue, 5, 83, 0, 0, // Skip to: 407 -/* 324 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 349 -/* 329 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 349 -/* 336 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 349 -/* 344 */ MCD_OPC_Decode, 141, 24, 237, 1, // Opcode: t2TEQrr -/* 349 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 373 -/* 354 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 373 -/* 361 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 373 -/* 368 */ MCD_OPC_Decode, 142, 24, 238, 1, // Opcode: t2TEQrs -/* 373 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 397 -/* 378 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 397 -/* 385 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 397 -/* 392 */ MCD_OPC_Decode, 245, 21, 239, 1, // Opcode: t2EORrr -/* 397 */ MCD_OPC_CheckPredicate, 38, 101, 30, 0, // Skip to: 8183 -/* 402 */ MCD_OPC_Decode, 246, 21, 240, 1, // Opcode: t2EORrs -/* 407 */ MCD_OPC_FilterValue, 6, 91, 30, 0, // Skip to: 8183 -/* 412 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 437 -/* 417 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 437 -/* 424 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 437 -/* 432 */ MCD_OPC_Decode, 224, 21, 237, 1, // Opcode: t2CMNzrr -/* 437 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 461 -/* 442 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 461 -/* 449 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 461 -/* 456 */ MCD_OPC_Decode, 225, 21, 238, 1, // Opcode: t2CMNzrs -/* 461 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 485 -/* 466 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 485 -/* 473 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 485 -/* 480 */ MCD_OPC_Decode, 203, 21, 241, 1, // Opcode: t2ADDrr -/* 485 */ MCD_OPC_CheckPredicate, 38, 13, 30, 0, // Skip to: 8183 -/* 490 */ MCD_OPC_Decode, 204, 21, 242, 1, // Opcode: t2ADDrs -/* 495 */ MCD_OPC_FilterValue, 1, 86, 1, 0, // Skip to: 842 -/* 500 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... -/* 503 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 557 -/* 508 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 511 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 534 -/* 516 */ MCD_OPC_CheckPredicate, 39, 238, 29, 0, // Skip to: 8183 -/* 521 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 229, 29, 0, // Skip to: 8183 -/* 530 */ MCD_OPC_Decode, 195, 23, 83, // Opcode: t2SRSDB_UPD -/* 534 */ MCD_OPC_FilterValue, 1, 220, 29, 0, // Skip to: 8183 -/* 539 */ MCD_OPC_CheckPredicate, 39, 215, 29, 0, // Skip to: 8183 -/* 544 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 206, 29, 0, // Skip to: 8183 -/* 553 */ MCD_OPC_Decode, 131, 23, 81, // Opcode: t2RFEDBW -/* 557 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 609 -/* 562 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 565 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 594 -/* 570 */ MCD_OPC_CheckPredicate, 38, 184, 29, 0, // Skip to: 8183 -/* 575 */ MCD_OPC_CheckField, 15, 1, 0, 177, 29, 0, // Skip to: 8183 -/* 582 */ MCD_OPC_CheckField, 13, 1, 0, 170, 29, 0, // Skip to: 8183 -/* 589 */ MCD_OPC_Decode, 229, 23, 243, 1, // Opcode: t2STMIA_UPD -/* 594 */ MCD_OPC_FilterValue, 1, 160, 29, 0, // Skip to: 8183 -/* 599 */ MCD_OPC_CheckPredicate, 38, 155, 29, 0, // Skip to: 8183 -/* 604 */ MCD_OPC_Decode, 151, 22, 244, 1, // Opcode: t2LDMIA_UPD -/* 609 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 661 -/* 614 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 617 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 646 -/* 622 */ MCD_OPC_CheckPredicate, 38, 132, 29, 0, // Skip to: 8183 -/* 627 */ MCD_OPC_CheckField, 15, 1, 0, 125, 29, 0, // Skip to: 8183 -/* 634 */ MCD_OPC_CheckField, 13, 1, 0, 118, 29, 0, // Skip to: 8183 -/* 641 */ MCD_OPC_Decode, 227, 23, 243, 1, // Opcode: t2STMDB_UPD -/* 646 */ MCD_OPC_FilterValue, 1, 108, 29, 0, // Skip to: 8183 -/* 651 */ MCD_OPC_CheckPredicate, 38, 103, 29, 0, // Skip to: 8183 -/* 656 */ MCD_OPC_Decode, 149, 22, 244, 1, // Opcode: t2LDMDB_UPD -/* 661 */ MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 715 -/* 666 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 669 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 692 -/* 674 */ MCD_OPC_CheckPredicate, 39, 80, 29, 0, // Skip to: 8183 -/* 679 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 71, 29, 0, // Skip to: 8183 -/* 688 */ MCD_OPC_Decode, 197, 23, 83, // Opcode: t2SRSIA_UPD -/* 692 */ MCD_OPC_FilterValue, 1, 62, 29, 0, // Skip to: 8183 -/* 697 */ MCD_OPC_CheckPredicate, 39, 57, 29, 0, // Skip to: 8183 -/* 702 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 48, 29, 0, // Skip to: 8183 -/* 711 */ MCD_OPC_Decode, 133, 23, 81, // Opcode: t2RFEIAW -/* 715 */ MCD_OPC_FilterValue, 4, 34, 0, 0, // Skip to: 754 -/* 720 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 744 -/* 725 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 744 -/* 732 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 744 -/* 739 */ MCD_OPC_Decode, 215, 21, 239, 1, // Opcode: t2BICrr -/* 744 */ MCD_OPC_CheckPredicate, 38, 10, 29, 0, // Skip to: 8183 -/* 749 */ MCD_OPC_Decode, 216, 21, 240, 1, // Opcode: t2BICrs -/* 754 */ MCD_OPC_FilterValue, 7, 0, 29, 0, // Skip to: 8183 -/* 759 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 784 -/* 764 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 784 -/* 771 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 784 -/* 779 */ MCD_OPC_Decode, 227, 21, 237, 1, // Opcode: t2CMPrr -/* 784 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 808 -/* 789 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 808 -/* 796 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 808 -/* 803 */ MCD_OPC_Decode, 228, 21, 238, 1, // Opcode: t2CMPrs -/* 808 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 832 -/* 813 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 832 -/* 820 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 832 -/* 827 */ MCD_OPC_Decode, 130, 24, 241, 1, // Opcode: t2SUBrr -/* 832 */ MCD_OPC_CheckPredicate, 38, 178, 28, 0, // Skip to: 8183 -/* 837 */ MCD_OPC_Decode, 131, 24, 242, 1, // Opcode: t2SUBrs -/* 842 */ MCD_OPC_FilterValue, 2, 70, 4, 0, // Skip to: 1941 -/* 847 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... -/* 850 */ MCD_OPC_FilterValue, 0, 212, 2, 0, // Skip to: 1579 -/* 855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 858 */ MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 1219 -/* 863 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 866 */ MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 984 -/* 871 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 874 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 899 -/* 879 */ MCD_OPC_CheckPredicate, 29, 90, 0, 0, // Skip to: 974 -/* 884 */ MCD_OPC_CheckField, 12, 4, 15, 83, 0, 0, // Skip to: 974 -/* 891 */ MCD_OPC_SoftFail, 63, 0, -/* 894 */ MCD_OPC_Decode, 147, 24, 245, 1, // Opcode: t2TT -/* 899 */ MCD_OPC_FilterValue, 1, 20, 0, 0, // Skip to: 924 -/* 904 */ MCD_OPC_CheckPredicate, 29, 65, 0, 0, // Skip to: 974 -/* 909 */ MCD_OPC_CheckField, 12, 4, 15, 58, 0, 0, // Skip to: 974 -/* 916 */ MCD_OPC_SoftFail, 63, 0, -/* 919 */ MCD_OPC_Decode, 150, 24, 245, 1, // Opcode: t2TTT -/* 924 */ MCD_OPC_FilterValue, 2, 20, 0, 0, // Skip to: 949 -/* 929 */ MCD_OPC_CheckPredicate, 29, 40, 0, 0, // Skip to: 974 -/* 934 */ MCD_OPC_CheckField, 12, 4, 15, 33, 0, 0, // Skip to: 974 -/* 941 */ MCD_OPC_SoftFail, 63, 0, -/* 944 */ MCD_OPC_Decode, 148, 24, 245, 1, // Opcode: t2TTA -/* 949 */ MCD_OPC_FilterValue, 3, 20, 0, 0, // Skip to: 974 -/* 954 */ MCD_OPC_CheckPredicate, 29, 15, 0, 0, // Skip to: 974 -/* 959 */ MCD_OPC_CheckField, 12, 4, 15, 8, 0, 0, // Skip to: 974 -/* 966 */ MCD_OPC_SoftFail, 63, 0, -/* 969 */ MCD_OPC_Decode, 149, 24, 245, 1, // Opcode: t2TTAT -/* 974 */ MCD_OPC_CheckPredicate, 32, 36, 28, 0, // Skip to: 8183 -/* 979 */ MCD_OPC_Decode, 239, 23, 246, 1, // Opcode: t2STREX -/* 984 */ MCD_OPC_FilterValue, 1, 26, 28, 0, // Skip to: 8183 -/* 989 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 992 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1014 -/* 997 */ MCD_OPC_CheckPredicate, 32, 13, 28, 0, // Skip to: 8183 -/* 1002 */ MCD_OPC_CheckField, 8, 4, 15, 6, 28, 0, // Skip to: 8183 -/* 1009 */ MCD_OPC_Decode, 240, 23, 247, 1, // Opcode: t2STREXB -/* 1014 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1036 -/* 1019 */ MCD_OPC_CheckPredicate, 32, 247, 27, 0, // Skip to: 8183 -/* 1024 */ MCD_OPC_CheckField, 8, 4, 15, 240, 27, 0, // Skip to: 8183 -/* 1031 */ MCD_OPC_Decode, 242, 23, 247, 1, // Opcode: t2STREXH -/* 1036 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1051 -/* 1041 */ MCD_OPC_CheckPredicate, 39, 225, 27, 0, // Skip to: 8183 -/* 1046 */ MCD_OPC_Decode, 241, 23, 248, 1, // Opcode: t2STREXD -/* 1051 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1080 -/* 1056 */ MCD_OPC_CheckPredicate, 40, 210, 27, 0, // Skip to: 8183 -/* 1061 */ MCD_OPC_CheckField, 8, 4, 15, 203, 27, 0, // Skip to: 8183 -/* 1068 */ MCD_OPC_CheckField, 0, 4, 15, 196, 27, 0, // Skip to: 8183 -/* 1075 */ MCD_OPC_Decode, 220, 23, 249, 1, // Opcode: t2STLB -/* 1080 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1109 -/* 1085 */ MCD_OPC_CheckPredicate, 40, 181, 27, 0, // Skip to: 8183 -/* 1090 */ MCD_OPC_CheckField, 8, 4, 15, 174, 27, 0, // Skip to: 8183 -/* 1097 */ MCD_OPC_CheckField, 0, 4, 15, 167, 27, 0, // Skip to: 8183 -/* 1104 */ MCD_OPC_Decode, 225, 23, 249, 1, // Opcode: t2STLH -/* 1109 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1138 -/* 1114 */ MCD_OPC_CheckPredicate, 40, 152, 27, 0, // Skip to: 8183 -/* 1119 */ MCD_OPC_CheckField, 8, 4, 15, 145, 27, 0, // Skip to: 8183 -/* 1126 */ MCD_OPC_CheckField, 0, 4, 15, 138, 27, 0, // Skip to: 8183 -/* 1133 */ MCD_OPC_Decode, 219, 23, 249, 1, // Opcode: t2STL -/* 1138 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1160 -/* 1143 */ MCD_OPC_CheckPredicate, 41, 123, 27, 0, // Skip to: 8183 -/* 1148 */ MCD_OPC_CheckField, 8, 4, 15, 116, 27, 0, // Skip to: 8183 -/* 1155 */ MCD_OPC_Decode, 222, 23, 247, 1, // Opcode: t2STLEXB -/* 1160 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1182 -/* 1165 */ MCD_OPC_CheckPredicate, 41, 101, 27, 0, // Skip to: 8183 -/* 1170 */ MCD_OPC_CheckField, 8, 4, 15, 94, 27, 0, // Skip to: 8183 -/* 1177 */ MCD_OPC_Decode, 224, 23, 247, 1, // Opcode: t2STLEXH -/* 1182 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 1204 -/* 1187 */ MCD_OPC_CheckPredicate, 41, 79, 27, 0, // Skip to: 8183 -/* 1192 */ MCD_OPC_CheckField, 8, 4, 15, 72, 27, 0, // Skip to: 8183 -/* 1199 */ MCD_OPC_Decode, 221, 23, 247, 1, // Opcode: t2STLEX -/* 1204 */ MCD_OPC_FilterValue, 15, 62, 27, 0, // Skip to: 8183 -/* 1209 */ MCD_OPC_CheckPredicate, 42, 57, 27, 0, // Skip to: 8183 -/* 1214 */ MCD_OPC_Decode, 223, 23, 248, 1, // Opcode: t2STLEXD -/* 1219 */ MCD_OPC_FilterValue, 1, 47, 27, 0, // Skip to: 8183 -/* 1224 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 1227 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1249 -/* 1232 */ MCD_OPC_CheckPredicate, 32, 34, 27, 0, // Skip to: 8183 -/* 1237 */ MCD_OPC_CheckField, 8, 4, 15, 27, 27, 0, // Skip to: 8183 -/* 1244 */ MCD_OPC_Decode, 162, 22, 250, 1, // Opcode: t2LDREX -/* 1249 */ MCD_OPC_FilterValue, 1, 17, 27, 0, // Skip to: 8183 -/* 1254 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 1257 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 1280 -/* 1262 */ MCD_OPC_CheckPredicate, 38, 4, 27, 0, // Skip to: 8183 -/* 1267 */ MCD_OPC_CheckField, 8, 8, 240, 1, 252, 26, 0, // Skip to: 8183 -/* 1275 */ MCD_OPC_Decode, 138, 24, 251, 1, // Opcode: t2TBB -/* 1280 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 1303 -/* 1285 */ MCD_OPC_CheckPredicate, 38, 237, 26, 0, // Skip to: 8183 -/* 1290 */ MCD_OPC_CheckField, 8, 8, 240, 1, 229, 26, 0, // Skip to: 8183 -/* 1298 */ MCD_OPC_Decode, 139, 24, 251, 1, // Opcode: t2TBH -/* 1303 */ MCD_OPC_FilterValue, 4, 24, 0, 0, // Skip to: 1332 -/* 1308 */ MCD_OPC_CheckPredicate, 32, 214, 26, 0, // Skip to: 8183 -/* 1313 */ MCD_OPC_CheckField, 8, 4, 15, 207, 26, 0, // Skip to: 8183 -/* 1320 */ MCD_OPC_CheckField, 0, 4, 15, 200, 26, 0, // Skip to: 8183 -/* 1327 */ MCD_OPC_Decode, 163, 22, 249, 1, // Opcode: t2LDREXB -/* 1332 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 1361 -/* 1337 */ MCD_OPC_CheckPredicate, 32, 185, 26, 0, // Skip to: 8183 -/* 1342 */ MCD_OPC_CheckField, 8, 4, 15, 178, 26, 0, // Skip to: 8183 -/* 1349 */ MCD_OPC_CheckField, 0, 4, 15, 171, 26, 0, // Skip to: 8183 -/* 1356 */ MCD_OPC_Decode, 165, 22, 249, 1, // Opcode: t2LDREXH -/* 1361 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1383 -/* 1366 */ MCD_OPC_CheckPredicate, 39, 156, 26, 0, // Skip to: 8183 -/* 1371 */ MCD_OPC_CheckField, 0, 4, 15, 149, 26, 0, // Skip to: 8183 -/* 1378 */ MCD_OPC_Decode, 164, 22, 252, 1, // Opcode: t2LDREXD -/* 1383 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1412 -/* 1388 */ MCD_OPC_CheckPredicate, 40, 134, 26, 0, // Skip to: 8183 -/* 1393 */ MCD_OPC_CheckField, 8, 4, 15, 127, 26, 0, // Skip to: 8183 -/* 1400 */ MCD_OPC_CheckField, 0, 4, 15, 120, 26, 0, // Skip to: 8183 -/* 1407 */ MCD_OPC_Decode, 254, 21, 249, 1, // Opcode: t2LDAB -/* 1412 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1441 -/* 1417 */ MCD_OPC_CheckPredicate, 40, 105, 26, 0, // Skip to: 8183 -/* 1422 */ MCD_OPC_CheckField, 8, 4, 15, 98, 26, 0, // Skip to: 8183 -/* 1429 */ MCD_OPC_CheckField, 0, 4, 15, 91, 26, 0, // Skip to: 8183 -/* 1436 */ MCD_OPC_Decode, 131, 22, 249, 1, // Opcode: t2LDAH -/* 1441 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1470 -/* 1446 */ MCD_OPC_CheckPredicate, 40, 76, 26, 0, // Skip to: 8183 -/* 1451 */ MCD_OPC_CheckField, 8, 4, 15, 69, 26, 0, // Skip to: 8183 -/* 1458 */ MCD_OPC_CheckField, 0, 4, 15, 62, 26, 0, // Skip to: 8183 -/* 1465 */ MCD_OPC_Decode, 253, 21, 249, 1, // Opcode: t2LDA -/* 1470 */ MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 1499 -/* 1475 */ MCD_OPC_CheckPredicate, 41, 47, 26, 0, // Skip to: 8183 -/* 1480 */ MCD_OPC_CheckField, 8, 4, 15, 40, 26, 0, // Skip to: 8183 -/* 1487 */ MCD_OPC_CheckField, 0, 4, 15, 33, 26, 0, // Skip to: 8183 -/* 1494 */ MCD_OPC_Decode, 128, 22, 249, 1, // Opcode: t2LDAEXB -/* 1499 */ MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 1528 -/* 1504 */ MCD_OPC_CheckPredicate, 41, 18, 26, 0, // Skip to: 8183 -/* 1509 */ MCD_OPC_CheckField, 8, 4, 15, 11, 26, 0, // Skip to: 8183 -/* 1516 */ MCD_OPC_CheckField, 0, 4, 15, 4, 26, 0, // Skip to: 8183 -/* 1523 */ MCD_OPC_Decode, 130, 22, 249, 1, // Opcode: t2LDAEXH -/* 1528 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 1557 -/* 1533 */ MCD_OPC_CheckPredicate, 41, 245, 25, 0, // Skip to: 8183 -/* 1538 */ MCD_OPC_CheckField, 8, 4, 15, 238, 25, 0, // Skip to: 8183 -/* 1545 */ MCD_OPC_CheckField, 0, 4, 15, 231, 25, 0, // Skip to: 8183 -/* 1552 */ MCD_OPC_Decode, 255, 21, 249, 1, // Opcode: t2LDAEX -/* 1557 */ MCD_OPC_FilterValue, 15, 221, 25, 0, // Skip to: 8183 -/* 1562 */ MCD_OPC_CheckPredicate, 42, 216, 25, 0, // Skip to: 8183 -/* 1567 */ MCD_OPC_CheckField, 0, 4, 15, 209, 25, 0, // Skip to: 8183 -/* 1574 */ MCD_OPC_Decode, 129, 22, 252, 1, // Opcode: t2LDAEXD -/* 1579 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 1617 -/* 1584 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1587 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1602 -/* 1592 */ MCD_OPC_CheckPredicate, 38, 186, 25, 0, // Skip to: 8183 -/* 1597 */ MCD_OPC_Decode, 238, 23, 253, 1, // Opcode: t2STRDi8 -/* 1602 */ MCD_OPC_FilterValue, 1, 176, 25, 0, // Skip to: 8183 -/* 1607 */ MCD_OPC_CheckPredicate, 38, 171, 25, 0, // Skip to: 8183 -/* 1612 */ MCD_OPC_Decode, 161, 22, 253, 1, // Opcode: t2LDRDi8 -/* 1617 */ MCD_OPC_FilterValue, 2, 233, 0, 0, // Skip to: 1855 -/* 1622 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 1625 */ MCD_OPC_FilterValue, 0, 173, 0, 0, // Skip to: 1803 -/* 1630 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 1633 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 1673 -/* 1638 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1641 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 1702 -/* 1646 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 1663 -/* 1651 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1663 -/* 1658 */ MCD_OPC_Decode, 207, 22, 254, 1, // Opcode: t2MOVr -/* 1663 */ MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 1702 -/* 1668 */ MCD_OPC_Decode, 229, 22, 239, 1, // Opcode: t2ORRrr -/* 1673 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 1702 -/* 1678 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1702 -/* 1683 */ MCD_OPC_CheckField, 16, 4, 15, 12, 0, 0, // Skip to: 1702 -/* 1690 */ MCD_OPC_CheckField, 12, 3, 0, 5, 0, 0, // Skip to: 1702 -/* 1697 */ MCD_OPC_Decode, 136, 23, 255, 1, // Opcode: t2RRX -/* 1702 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 1705 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1727 -/* 1710 */ MCD_OPC_CheckPredicate, 38, 78, 0, 0, // Skip to: 1793 -/* 1715 */ MCD_OPC_CheckField, 16, 4, 15, 71, 0, 0, // Skip to: 1793 -/* 1722 */ MCD_OPC_Decode, 194, 22, 128, 2, // Opcode: t2LSLri -/* 1727 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1749 -/* 1732 */ MCD_OPC_CheckPredicate, 38, 56, 0, 0, // Skip to: 1793 -/* 1737 */ MCD_OPC_CheckField, 16, 4, 15, 49, 0, 0, // Skip to: 1793 -/* 1744 */ MCD_OPC_Decode, 196, 22, 128, 2, // Opcode: t2LSRri -/* 1749 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1771 -/* 1754 */ MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 1793 -/* 1759 */ MCD_OPC_CheckField, 16, 4, 15, 27, 0, 0, // Skip to: 1793 -/* 1766 */ MCD_OPC_Decode, 209, 21, 128, 2, // Opcode: t2ASRri -/* 1771 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1793 -/* 1776 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 1793 -/* 1781 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1793 -/* 1788 */ MCD_OPC_Decode, 134, 23, 128, 2, // Opcode: t2RORri -/* 1793 */ MCD_OPC_CheckPredicate, 38, 241, 24, 0, // Skip to: 8183 -/* 1798 */ MCD_OPC_Decode, 230, 22, 240, 1, // Opcode: t2ORRrs -/* 1803 */ MCD_OPC_FilterValue, 1, 231, 24, 0, // Skip to: 8183 -/* 1808 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 1811 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1833 -/* 1816 */ MCD_OPC_CheckPredicate, 43, 218, 24, 0, // Skip to: 8183 -/* 1821 */ MCD_OPC_CheckField, 20, 1, 0, 211, 24, 0, // Skip to: 8183 -/* 1828 */ MCD_OPC_Decode, 231, 22, 129, 2, // Opcode: t2PKHBT -/* 1833 */ MCD_OPC_FilterValue, 2, 201, 24, 0, // Skip to: 8183 -/* 1838 */ MCD_OPC_CheckPredicate, 43, 196, 24, 0, // Skip to: 8183 -/* 1843 */ MCD_OPC_CheckField, 20, 1, 0, 189, 24, 0, // Skip to: 8183 -/* 1850 */ MCD_OPC_Decode, 232, 22, 129, 2, // Opcode: t2PKHTB -/* 1855 */ MCD_OPC_FilterValue, 3, 179, 24, 0, // Skip to: 8183 -/* 1860 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 1863 */ MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 1902 -/* 1868 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1892 -/* 1873 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 1892 -/* 1880 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 1892 -/* 1887 */ MCD_OPC_Decode, 199, 21, 239, 1, // Opcode: t2ADCrr -/* 1892 */ MCD_OPC_CheckPredicate, 38, 142, 24, 0, // Skip to: 8183 -/* 1897 */ MCD_OPC_Decode, 200, 21, 240, 1, // Opcode: t2ADCrs -/* 1902 */ MCD_OPC_FilterValue, 1, 132, 24, 0, // Skip to: 8183 -/* 1907 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1931 -/* 1912 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 1931 -/* 1919 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 1931 -/* 1926 */ MCD_OPC_Decode, 138, 23, 239, 1, // Opcode: t2RSBrr -/* 1931 */ MCD_OPC_CheckPredicate, 38, 103, 24, 0, // Skip to: 8183 -/* 1936 */ MCD_OPC_Decode, 139, 23, 240, 1, // Opcode: t2RSBrs -/* 1941 */ MCD_OPC_FilterValue, 3, 93, 24, 0, // Skip to: 8183 -/* 1946 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... -/* 1949 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1987 -/* 1954 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1957 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1972 -/* 1962 */ MCD_OPC_CheckPredicate, 38, 72, 24, 0, // Skip to: 8183 -/* 1967 */ MCD_OPC_Decode, 236, 23, 130, 2, // Opcode: t2STRD_POST -/* 1972 */ MCD_OPC_FilterValue, 1, 62, 24, 0, // Skip to: 8183 -/* 1977 */ MCD_OPC_CheckPredicate, 38, 57, 24, 0, // Skip to: 8183 -/* 1982 */ MCD_OPC_Decode, 159, 22, 131, 2, // Opcode: t2LDRD_POST -/* 1987 */ MCD_OPC_FilterValue, 1, 58, 0, 0, // Skip to: 2050 -/* 1992 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 1995 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2010 -/* 2000 */ MCD_OPC_CheckPredicate, 38, 34, 24, 0, // Skip to: 8183 -/* 2005 */ MCD_OPC_Decode, 237, 23, 132, 2, // Opcode: t2STRD_PRE -/* 2010 */ MCD_OPC_FilterValue, 1, 24, 24, 0, // Skip to: 8183 -/* 2015 */ MCD_OPC_CheckPredicate, 44, 20, 0, 0, // Skip to: 2040 -/* 2020 */ MCD_OPC_CheckField, 23, 1, 0, 13, 0, 0, // Skip to: 2040 -/* 2027 */ MCD_OPC_CheckField, 0, 20, 255, 210, 63, 4, 0, 0, // Skip to: 2040 -/* 2036 */ MCD_OPC_Decode, 150, 23, 51, // Opcode: t2SG -/* 2040 */ MCD_OPC_CheckPredicate, 38, 250, 23, 0, // Skip to: 8183 -/* 2045 */ MCD_OPC_Decode, 160, 22, 133, 2, // Opcode: t2LDRD_PRE -/* 2050 */ MCD_OPC_FilterValue, 2, 78, 0, 0, // Skip to: 2133 -/* 2055 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 2058 */ MCD_OPC_FilterValue, 0, 232, 23, 0, // Skip to: 8183 -/* 2063 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 2066 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2106 -/* 2071 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2074 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2106 -/* 2079 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2096 -/* 2084 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2096 -/* 2091 */ MCD_OPC_Decode, 223, 22, 255, 1, // Opcode: t2MVNr -/* 2096 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 2106 -/* 2101 */ MCD_OPC_Decode, 226, 22, 239, 1, // Opcode: t2ORNrr -/* 2106 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2123 -/* 2111 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2123 -/* 2118 */ MCD_OPC_Decode, 224, 22, 134, 2, // Opcode: t2MVNs -/* 2123 */ MCD_OPC_CheckPredicate, 38, 167, 23, 0, // Skip to: 8183 -/* 2128 */ MCD_OPC_Decode, 227, 22, 240, 1, // Opcode: t2ORNrs -/* 2133 */ MCD_OPC_FilterValue, 3, 157, 23, 0, // Skip to: 8183 -/* 2138 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 2141 */ MCD_OPC_FilterValue, 0, 149, 23, 0, // Skip to: 8183 -/* 2146 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2170 -/* 2151 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 2170 -/* 2158 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 2170 -/* 2165 */ MCD_OPC_Decode, 144, 23, 239, 1, // Opcode: t2SBCrr -/* 2170 */ MCD_OPC_CheckPredicate, 38, 120, 23, 0, // Skip to: 8183 -/* 2175 */ MCD_OPC_Decode, 145, 23, 240, 1, // Opcode: t2SBCrs -/* 2180 */ MCD_OPC_FilterValue, 30, 153, 5, 0, // Skip to: 3618 -/* 2185 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 2188 */ MCD_OPC_FilterValue, 0, 179, 2, 0, // Skip to: 2884 -/* 2193 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 2196 */ MCD_OPC_FilterValue, 0, 160, 0, 0, // Skip to: 2361 -/* 2201 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 2204 */ MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2243 -/* 2209 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2233 -/* 2214 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2233 -/* 2221 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2233 -/* 2228 */ MCD_OPC_Decode, 144, 24, 135, 2, // Opcode: t2TSTri -/* 2233 */ MCD_OPC_CheckPredicate, 38, 57, 23, 0, // Skip to: 8183 -/* 2238 */ MCD_OPC_Decode, 206, 21, 136, 2, // Opcode: t2ANDri -/* 2243 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2258 -/* 2248 */ MCD_OPC_CheckPredicate, 38, 42, 23, 0, // Skip to: 8183 -/* 2253 */ MCD_OPC_Decode, 214, 21, 136, 2, // Opcode: t2BICri -/* 2258 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 2290 -/* 2263 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2280 -/* 2268 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2280 -/* 2275 */ MCD_OPC_Decode, 205, 22, 137, 2, // Opcode: t2MOVi -/* 2280 */ MCD_OPC_CheckPredicate, 38, 10, 23, 0, // Skip to: 8183 -/* 2285 */ MCD_OPC_Decode, 228, 22, 136, 2, // Opcode: t2ORRri -/* 2290 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 2322 -/* 2295 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2312 -/* 2300 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2312 -/* 2307 */ MCD_OPC_Decode, 222, 22, 137, 2, // Opcode: t2MVNi -/* 2312 */ MCD_OPC_CheckPredicate, 38, 234, 22, 0, // Skip to: 8183 -/* 2317 */ MCD_OPC_Decode, 225, 22, 136, 2, // Opcode: t2ORNri -/* 2322 */ MCD_OPC_FilterValue, 4, 224, 22, 0, // Skip to: 8183 -/* 2327 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2351 -/* 2332 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2351 -/* 2339 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2351 -/* 2346 */ MCD_OPC_Decode, 140, 24, 135, 2, // Opcode: t2TEQri -/* 2351 */ MCD_OPC_CheckPredicate, 38, 195, 22, 0, // Skip to: 8183 -/* 2356 */ MCD_OPC_Decode, 244, 21, 136, 2, // Opcode: t2EORri -/* 2361 */ MCD_OPC_FilterValue, 1, 126, 0, 0, // Skip to: 2492 -/* 2366 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 2369 */ MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2408 -/* 2374 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2398 -/* 2379 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2398 -/* 2386 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2398 -/* 2393 */ MCD_OPC_Decode, 223, 21, 135, 2, // Opcode: t2CMNri -/* 2398 */ MCD_OPC_CheckPredicate, 38, 148, 22, 0, // Skip to: 8183 -/* 2403 */ MCD_OPC_Decode, 201, 21, 138, 2, // Opcode: t2ADDri -/* 2408 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2423 -/* 2413 */ MCD_OPC_CheckPredicate, 38, 133, 22, 0, // Skip to: 8183 -/* 2418 */ MCD_OPC_Decode, 198, 21, 136, 2, // Opcode: t2ADCri -/* 2423 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2438 -/* 2428 */ MCD_OPC_CheckPredicate, 38, 118, 22, 0, // Skip to: 8183 -/* 2433 */ MCD_OPC_Decode, 143, 23, 136, 2, // Opcode: t2SBCri -/* 2438 */ MCD_OPC_FilterValue, 5, 34, 0, 0, // Skip to: 2477 -/* 2443 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2467 -/* 2448 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2467 -/* 2455 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2467 -/* 2462 */ MCD_OPC_Decode, 226, 21, 135, 2, // Opcode: t2CMPri -/* 2467 */ MCD_OPC_CheckPredicate, 38, 79, 22, 0, // Skip to: 8183 -/* 2472 */ MCD_OPC_Decode, 128, 24, 138, 2, // Opcode: t2SUBri -/* 2477 */ MCD_OPC_FilterValue, 6, 69, 22, 0, // Skip to: 8183 -/* 2482 */ MCD_OPC_CheckPredicate, 38, 64, 22, 0, // Skip to: 8183 -/* 2487 */ MCD_OPC_Decode, 137, 23, 136, 2, // Opcode: t2RSBri -/* 2492 */ MCD_OPC_FilterValue, 2, 132, 0, 0, // Skip to: 2629 -/* 2497 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2500 */ MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 2577 -/* 2505 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 2508 */ MCD_OPC_FilterValue, 0, 38, 22, 0, // Skip to: 8183 -/* 2513 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 2516 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2538 -/* 2521 */ MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 2560 -/* 2526 */ MCD_OPC_CheckField, 23, 1, 0, 27, 0, 0, // Skip to: 2560 -/* 2533 */ MCD_OPC_Decode, 202, 21, 139, 2, // Opcode: t2ADDri12 -/* 2538 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2560 -/* 2543 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2560 -/* 2548 */ MCD_OPC_CheckField, 23, 1, 1, 5, 0, 0, // Skip to: 2560 -/* 2555 */ MCD_OPC_Decode, 129, 24, 139, 2, // Opcode: t2SUBri12 -/* 2560 */ MCD_OPC_CheckPredicate, 38, 242, 21, 0, // Skip to: 8183 -/* 2565 */ MCD_OPC_CheckField, 16, 4, 15, 235, 21, 0, // Skip to: 8183 -/* 2572 */ MCD_OPC_Decode, 205, 21, 140, 2, // Opcode: t2ADR -/* 2577 */ MCD_OPC_FilterValue, 1, 225, 21, 0, // Skip to: 8183 -/* 2582 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 2585 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2607 -/* 2590 */ MCD_OPC_CheckPredicate, 32, 212, 21, 0, // Skip to: 8183 -/* 2595 */ MCD_OPC_CheckField, 20, 2, 0, 205, 21, 0, // Skip to: 8183 -/* 2602 */ MCD_OPC_Decode, 206, 22, 141, 2, // Opcode: t2MOVi16 -/* 2607 */ MCD_OPC_FilterValue, 1, 195, 21, 0, // Skip to: 8183 -/* 2612 */ MCD_OPC_CheckPredicate, 32, 190, 21, 0, // Skip to: 8183 -/* 2617 */ MCD_OPC_CheckField, 20, 2, 0, 183, 21, 0, // Skip to: 8183 -/* 2624 */ MCD_OPC_Decode, 204, 22, 141, 2, // Opcode: t2MOVTi16 -/* 2629 */ MCD_OPC_FilterValue, 3, 173, 21, 0, // Skip to: 8183 -/* 2634 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 2637 */ MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 2714 -/* 2642 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 2645 */ MCD_OPC_FilterValue, 0, 157, 21, 0, // Skip to: 8183 -/* 2650 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 2653 */ MCD_OPC_FilterValue, 0, 149, 21, 0, // Skip to: 8183 -/* 2658 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 2661 */ MCD_OPC_FilterValue, 0, 141, 21, 0, // Skip to: 8183 -/* 2666 */ MCD_OPC_CheckPredicate, 45, 33, 0, 0, // Skip to: 2704 -/* 2671 */ MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 2704 -/* 2678 */ MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 2704 -/* 2685 */ MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 2704 -/* 2692 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 2704 -/* 2699 */ MCD_OPC_Decode, 199, 23, 142, 2, // Opcode: t2SSAT16 -/* 2704 */ MCD_OPC_CheckPredicate, 38, 98, 21, 0, // Skip to: 8183 -/* 2709 */ MCD_OPC_Decode, 198, 23, 143, 2, // Opcode: t2SSAT -/* 2714 */ MCD_OPC_FilterValue, 1, 66, 0, 0, // Skip to: 2785 -/* 2719 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 2722 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2737 -/* 2727 */ MCD_OPC_CheckPredicate, 38, 75, 21, 0, // Skip to: 8183 -/* 2732 */ MCD_OPC_Decode, 146, 23, 144, 2, // Opcode: t2SBFX -/* 2737 */ MCD_OPC_FilterValue, 2, 65, 21, 0, // Skip to: 8183 -/* 2742 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 2745 */ MCD_OPC_FilterValue, 0, 57, 21, 0, // Skip to: 8183 -/* 2750 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 2753 */ MCD_OPC_FilterValue, 0, 49, 21, 0, // Skip to: 8183 -/* 2758 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2775 -/* 2763 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2775 -/* 2770 */ MCD_OPC_Decode, 212, 21, 145, 2, // Opcode: t2BFC -/* 2775 */ MCD_OPC_CheckPredicate, 38, 27, 21, 0, // Skip to: 8183 -/* 2780 */ MCD_OPC_Decode, 213, 21, 146, 2, // Opcode: t2BFI -/* 2785 */ MCD_OPC_FilterValue, 2, 72, 0, 0, // Skip to: 2862 -/* 2790 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 2793 */ MCD_OPC_FilterValue, 0, 9, 21, 0, // Skip to: 8183 -/* 2798 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 2801 */ MCD_OPC_FilterValue, 0, 1, 21, 0, // Skip to: 8183 -/* 2806 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 2809 */ MCD_OPC_FilterValue, 0, 249, 20, 0, // Skip to: 8183 -/* 2814 */ MCD_OPC_CheckPredicate, 45, 33, 0, 0, // Skip to: 2852 -/* 2819 */ MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 2852 -/* 2826 */ MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 2852 -/* 2833 */ MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 2852 -/* 2840 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 2852 -/* 2847 */ MCD_OPC_Decode, 175, 24, 142, 2, // Opcode: t2USAT16 -/* 2852 */ MCD_OPC_CheckPredicate, 38, 206, 20, 0, // Skip to: 8183 -/* 2857 */ MCD_OPC_Decode, 174, 24, 143, 2, // Opcode: t2USAT -/* 2862 */ MCD_OPC_FilterValue, 3, 196, 20, 0, // Skip to: 8183 -/* 2867 */ MCD_OPC_CheckPredicate, 38, 191, 20, 0, // Skip to: 8183 -/* 2872 */ MCD_OPC_CheckField, 20, 2, 0, 184, 20, 0, // Skip to: 8183 -/* 2879 */ MCD_OPC_Decode, 154, 24, 144, 2, // Opcode: t2UBFX -/* 2884 */ MCD_OPC_FilterValue, 1, 174, 20, 0, // Skip to: 8183 -/* 2889 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 2892 */ MCD_OPC_FilterValue, 0, 187, 2, 0, // Skip to: 3596 -/* 2897 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 2900 */ MCD_OPC_FilterValue, 0, 158, 20, 0, // Skip to: 8183 -/* 2905 */ MCD_OPC_ExtractField, 0, 12, // Inst{11-0} ... -/* 2908 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2937 -/* 2913 */ MCD_OPC_CheckPredicate, 46, 166, 0, 0, // Skip to: 3084 -/* 2918 */ MCD_OPC_CheckField, 16, 11, 143, 15, 158, 0, 0, // Skip to: 3084 -/* 2926 */ MCD_OPC_CheckField, 13, 1, 0, 151, 0, 0, // Skip to: 3084 -/* 2933 */ MCD_OPC_Decode, 239, 21, 51, // Opcode: t2DCPS1 -/* 2937 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 2966 -/* 2942 */ MCD_OPC_CheckPredicate, 46, 137, 0, 0, // Skip to: 3084 -/* 2947 */ MCD_OPC_CheckField, 16, 11, 143, 15, 129, 0, 0, // Skip to: 3084 -/* 2955 */ MCD_OPC_CheckField, 13, 1, 0, 122, 0, 0, // Skip to: 3084 -/* 2962 */ MCD_OPC_Decode, 240, 21, 51, // Opcode: t2DCPS2 -/* 2966 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 2995 -/* 2971 */ MCD_OPC_CheckPredicate, 46, 108, 0, 0, // Skip to: 3084 -/* 2976 */ MCD_OPC_CheckField, 16, 11, 143, 15, 100, 0, 0, // Skip to: 3084 -/* 2984 */ MCD_OPC_CheckField, 13, 1, 0, 93, 0, 0, // Skip to: 3084 -/* 2991 */ MCD_OPC_Decode, 241, 21, 51, // Opcode: t2DCPS3 -/* 2995 */ MCD_OPC_FilterValue, 18, 24, 0, 0, // Skip to: 3024 -/* 3000 */ MCD_OPC_CheckPredicate, 47, 79, 0, 0, // Skip to: 3084 -/* 3005 */ MCD_OPC_CheckField, 16, 11, 175, 7, 71, 0, 0, // Skip to: 3084 -/* 3013 */ MCD_OPC_CheckField, 13, 1, 0, 64, 0, 0, // Skip to: 3084 -/* 3020 */ MCD_OPC_Decode, 143, 24, 51, // Opcode: t2TSB -/* 3024 */ MCD_OPC_FilterValue, 128, 30, 24, 0, 0, // Skip to: 3054 -/* 3030 */ MCD_OPC_CheckPredicate, 39, 49, 0, 0, // Skip to: 3084 -/* 3035 */ MCD_OPC_CheckField, 20, 7, 60, 42, 0, 0, // Skip to: 3084 -/* 3042 */ MCD_OPC_CheckField, 13, 1, 0, 35, 0, 0, // Skip to: 3084 -/* 3049 */ MCD_OPC_Decode, 217, 21, 147, 2, // Opcode: t2BXJ -/* 3054 */ MCD_OPC_FilterValue, 175, 30, 24, 0, 0, // Skip to: 3084 -/* 3060 */ MCD_OPC_CheckPredicate, 48, 19, 0, 0, // Skip to: 3084 -/* 3065 */ MCD_OPC_CheckField, 16, 11, 191, 7, 11, 0, 0, // Skip to: 3084 -/* 3073 */ MCD_OPC_CheckField, 13, 1, 0, 4, 0, 0, // Skip to: 3084 -/* 3080 */ MCD_OPC_Decode, 221, 21, 51, // Opcode: t2CLREX -/* 3084 */ MCD_OPC_ExtractField, 16, 11, // Inst{26-16} ... -/* 3087 */ MCD_OPC_FilterValue, 175, 7, 131, 0, 0, // Skip to: 3224 -/* 3093 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 3096 */ MCD_OPC_FilterValue, 0, 68, 0, 0, // Skip to: 3169 -/* 3101 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 3104 */ MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 3389 -/* 3109 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 3112 */ MCD_OPC_FilterValue, 0, 16, 1, 0, // Skip to: 3389 -/* 3117 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 3120 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 3152 -/* 3125 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3142 -/* 3130 */ MCD_OPC_CheckField, 4, 4, 15, 5, 0, 0, // Skip to: 3142 -/* 3137 */ MCD_OPC_Decode, 238, 21, 148, 2, // Opcode: t2DBG -/* 3142 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3152 -/* 3147 */ MCD_OPC_Decode, 247, 21, 226, 1, // Opcode: t2HINT -/* 3152 */ MCD_OPC_CheckPredicate, 39, 232, 0, 0, // Skip to: 3389 -/* 3157 */ MCD_OPC_CheckField, 0, 5, 0, 225, 0, 0, // Skip to: 3389 -/* 3164 */ MCD_OPC_Decode, 230, 21, 149, 2, // Opcode: t2CPS2p -/* 3169 */ MCD_OPC_FilterValue, 1, 215, 0, 0, // Skip to: 3389 -/* 3174 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 3177 */ MCD_OPC_FilterValue, 0, 207, 0, 0, // Skip to: 3389 -/* 3182 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 3185 */ MCD_OPC_FilterValue, 0, 199, 0, 0, // Skip to: 3389 -/* 3190 */ MCD_OPC_CheckPredicate, 39, 19, 0, 0, // Skip to: 3214 -/* 3195 */ MCD_OPC_CheckField, 9, 2, 0, 12, 0, 0, // Skip to: 3214 -/* 3202 */ MCD_OPC_CheckField, 5, 3, 0, 5, 0, 0, // Skip to: 3214 -/* 3209 */ MCD_OPC_Decode, 229, 21, 149, 2, // Opcode: t2CPS1p -/* 3214 */ MCD_OPC_CheckPredicate, 39, 170, 0, 0, // Skip to: 3389 -/* 3219 */ MCD_OPC_Decode, 231, 21, 149, 2, // Opcode: t2CPS3p -/* 3224 */ MCD_OPC_FilterValue, 191, 7, 69, 0, 0, // Skip to: 3299 -/* 3230 */ MCD_OPC_ExtractField, 4, 8, // Inst{11-4} ... -/* 3233 */ MCD_OPC_FilterValue, 244, 1, 16, 0, 0, // Skip to: 3255 -/* 3239 */ MCD_OPC_CheckPredicate, 49, 145, 0, 0, // Skip to: 3389 -/* 3244 */ MCD_OPC_CheckField, 13, 1, 0, 138, 0, 0, // Skip to: 3389 -/* 3251 */ MCD_OPC_Decode, 243, 21, 61, // Opcode: t2DSB -/* 3255 */ MCD_OPC_FilterValue, 245, 1, 16, 0, 0, // Skip to: 3277 -/* 3261 */ MCD_OPC_CheckPredicate, 49, 123, 0, 0, // Skip to: 3389 -/* 3266 */ MCD_OPC_CheckField, 13, 1, 0, 116, 0, 0, // Skip to: 3389 -/* 3273 */ MCD_OPC_Decode, 242, 21, 61, // Opcode: t2DMB -/* 3277 */ MCD_OPC_FilterValue, 246, 1, 106, 0, 0, // Skip to: 3389 -/* 3283 */ MCD_OPC_CheckPredicate, 49, 101, 0, 0, // Skip to: 3389 -/* 3288 */ MCD_OPC_CheckField, 13, 1, 0, 94, 0, 0, // Skip to: 3389 -/* 3295 */ MCD_OPC_Decode, 249, 21, 62, // Opcode: t2ISB -/* 3299 */ MCD_OPC_FilterValue, 222, 7, 24, 0, 0, // Skip to: 3329 -/* 3305 */ MCD_OPC_CheckPredicate, 39, 79, 0, 0, // Skip to: 3389 -/* 3310 */ MCD_OPC_CheckField, 13, 1, 0, 72, 0, 0, // Skip to: 3389 -/* 3317 */ MCD_OPC_CheckField, 8, 4, 15, 65, 0, 0, // Skip to: 3389 -/* 3324 */ MCD_OPC_Decode, 255, 23, 226, 1, // Opcode: t2SUBS_PC_LR -/* 3329 */ MCD_OPC_FilterValue, 239, 7, 24, 0, 0, // Skip to: 3359 -/* 3335 */ MCD_OPC_CheckPredicate, 39, 49, 0, 0, // Skip to: 3389 -/* 3340 */ MCD_OPC_CheckField, 13, 1, 0, 42, 0, 0, // Skip to: 3389 -/* 3347 */ MCD_OPC_CheckField, 0, 8, 0, 35, 0, 0, // Skip to: 3389 -/* 3354 */ MCD_OPC_Decode, 214, 22, 150, 2, // Opcode: t2MRS_AR -/* 3359 */ MCD_OPC_FilterValue, 255, 7, 24, 0, 0, // Skip to: 3389 -/* 3365 */ MCD_OPC_CheckPredicate, 39, 19, 0, 0, // Skip to: 3389 -/* 3370 */ MCD_OPC_CheckField, 13, 1, 0, 12, 0, 0, // Skip to: 3389 -/* 3377 */ MCD_OPC_CheckField, 0, 8, 0, 5, 0, 0, // Skip to: 3389 -/* 3384 */ MCD_OPC_Decode, 217, 22, 150, 2, // Opcode: t2MRSsys_AR -/* 3389 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 3392 */ MCD_OPC_FilterValue, 0, 122, 0, 0, // Skip to: 3519 -/* 3397 */ MCD_OPC_ExtractField, 21, 6, // Inst{26-21} ... -/* 3400 */ MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 3452 -/* 3405 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... -/* 3408 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3430 -/* 3413 */ MCD_OPC_CheckPredicate, 39, 123, 0, 0, // Skip to: 3541 -/* 3418 */ MCD_OPC_CheckField, 0, 5, 0, 116, 0, 0, // Skip to: 3541 -/* 3425 */ MCD_OPC_Decode, 218, 22, 151, 2, // Opcode: t2MSR_AR -/* 3430 */ MCD_OPC_FilterValue, 1, 106, 0, 0, // Skip to: 3541 -/* 3435 */ MCD_OPC_CheckPredicate, 50, 101, 0, 0, // Skip to: 3541 -/* 3440 */ MCD_OPC_CheckField, 0, 4, 0, 94, 0, 0, // Skip to: 3541 -/* 3447 */ MCD_OPC_Decode, 220, 22, 152, 2, // Opcode: t2MSRbanked -/* 3452 */ MCD_OPC_FilterValue, 31, 24, 0, 0, // Skip to: 3481 -/* 3457 */ MCD_OPC_CheckPredicate, 50, 79, 0, 0, // Skip to: 3541 -/* 3462 */ MCD_OPC_CheckField, 5, 3, 1, 72, 0, 0, // Skip to: 3541 -/* 3469 */ MCD_OPC_CheckField, 0, 4, 0, 65, 0, 0, // Skip to: 3541 -/* 3476 */ MCD_OPC_Decode, 216, 22, 153, 2, // Opcode: t2MRSbanked -/* 3481 */ MCD_OPC_FilterValue, 63, 55, 0, 0, // Skip to: 3541 -/* 3486 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3489 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3504 -/* 3494 */ MCD_OPC_CheckPredicate, 51, 42, 0, 0, // Skip to: 3541 -/* 3499 */ MCD_OPC_Decode, 248, 21, 154, 2, // Opcode: t2HVC -/* 3504 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 3541 -/* 3509 */ MCD_OPC_CheckPredicate, 52, 27, 0, 0, // Skip to: 3541 -/* 3514 */ MCD_OPC_Decode, 157, 23, 155, 2, // Opcode: t2SMC -/* 3519 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3541 -/* 3524 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3541 -/* 3529 */ MCD_OPC_CheckField, 20, 7, 127, 5, 0, 0, // Skip to: 3541 -/* 3536 */ MCD_OPC_Decode, 155, 24, 154, 2, // Opcode: t2UDF -/* 3541 */ MCD_OPC_ExtractField, 21, 6, // Inst{26-21} ... -/* 3544 */ MCD_OPC_FilterValue, 28, 15, 0, 0, // Skip to: 3564 -/* 3549 */ MCD_OPC_CheckPredicate, 53, 32, 0, 0, // Skip to: 3586 -/* 3554 */ MCD_OPC_SoftFail, 128, 198, 64 /* 0x102300 */, 0, -/* 3559 */ MCD_OPC_Decode, 219, 22, 156, 2, // Opcode: t2MSR_M -/* 3564 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 3586 -/* 3569 */ MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 3586 -/* 3574 */ MCD_OPC_SoftFail, 128, 192, 64 /* 0x102000 */, 128, 128, 60 /* 0xf0000 */, -/* 3581 */ MCD_OPC_Decode, 215, 22, 157, 2, // Opcode: t2MRS_M -/* 3586 */ MCD_OPC_CheckPredicate, 38, 240, 17, 0, // Skip to: 8183 -/* 3591 */ MCD_OPC_Decode, 218, 21, 158, 2, // Opcode: t2Bcc -/* 3596 */ MCD_OPC_FilterValue, 1, 230, 17, 0, // Skip to: 8183 -/* 3601 */ MCD_OPC_CheckPredicate, 32, 225, 17, 0, // Skip to: 8183 -/* 3606 */ MCD_OPC_CheckField, 14, 1, 0, 218, 17, 0, // Skip to: 8183 -/* 3613 */ MCD_OPC_Decode, 211, 21, 159, 2, // Opcode: t2B -/* 3618 */ MCD_OPC_FilterValue, 31, 208, 17, 0, // Skip to: 8183 -/* 3623 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 3626 */ MCD_OPC_FilterValue, 0, 96, 6, 0, // Skip to: 5263 -/* 3631 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... -/* 3634 */ MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 3995 -/* 3639 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 3642 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 3772 -/* 3647 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 3650 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 3757 -/* 3655 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 3658 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3680 -/* 3663 */ MCD_OPC_CheckPredicate, 38, 163, 17, 0, // Skip to: 8183 -/* 3668 */ MCD_OPC_CheckField, 6, 4, 0, 156, 17, 0, // Skip to: 8183 -/* 3675 */ MCD_OPC_Decode, 235, 23, 160, 2, // Opcode: t2STRBs -/* 3680 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3702 -/* 3685 */ MCD_OPC_CheckPredicate, 38, 141, 17, 0, // Skip to: 8183 -/* 3690 */ MCD_OPC_CheckField, 8, 1, 1, 134, 17, 0, // Skip to: 8183 -/* 3697 */ MCD_OPC_Decode, 231, 23, 161, 2, // Opcode: t2STRB_POST -/* 3702 */ MCD_OPC_FilterValue, 3, 124, 17, 0, // Skip to: 8183 -/* 3707 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 3710 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 3742 -/* 3715 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3732 -/* 3720 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 3732 -/* 3727 */ MCD_OPC_Decode, 230, 23, 162, 2, // Opcode: t2STRBT -/* 3732 */ MCD_OPC_CheckPredicate, 38, 94, 17, 0, // Skip to: 8183 -/* 3737 */ MCD_OPC_Decode, 234, 23, 163, 2, // Opcode: t2STRBi8 -/* 3742 */ MCD_OPC_FilterValue, 1, 84, 17, 0, // Skip to: 8183 -/* 3747 */ MCD_OPC_CheckPredicate, 38, 79, 17, 0, // Skip to: 8183 -/* 3752 */ MCD_OPC_Decode, 232, 23, 161, 2, // Opcode: t2STRB_PRE -/* 3757 */ MCD_OPC_FilterValue, 1, 69, 17, 0, // Skip to: 8183 -/* 3762 */ MCD_OPC_CheckPredicate, 38, 64, 17, 0, // Skip to: 8183 -/* 3767 */ MCD_OPC_Decode, 233, 23, 164, 2, // Opcode: t2STRBi12 -/* 3772 */ MCD_OPC_FilterValue, 1, 54, 17, 0, // Skip to: 8183 -/* 3777 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 3780 */ MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 3928 -/* 3785 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 3788 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3828 -/* 3793 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 3796 */ MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 3960 -/* 3801 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3818 -/* 3806 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3818 -/* 3813 */ MCD_OPC_Decode, 239, 22, 165, 2, // Opcode: t2PLDs -/* 3818 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 3960 -/* 3823 */ MCD_OPC_Decode, 158, 22, 165, 2, // Opcode: t2LDRBs -/* 3828 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3850 -/* 3833 */ MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 3960 -/* 3838 */ MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 3960 -/* 3845 */ MCD_OPC_Decode, 153, 22, 161, 2, // Opcode: t2LDRB_POST -/* 3850 */ MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 3960 -/* 3855 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 3858 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 3913 -/* 3863 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 3866 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3888 -/* 3871 */ MCD_OPC_CheckPredicate, 38, 27, 0, 0, // Skip to: 3903 -/* 3876 */ MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 3903 -/* 3883 */ MCD_OPC_Decode, 237, 22, 166, 2, // Opcode: t2PLDi8 -/* 3888 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3903 -/* 3893 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3903 -/* 3898 */ MCD_OPC_Decode, 152, 22, 167, 2, // Opcode: t2LDRBT -/* 3903 */ MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 3960 -/* 3908 */ MCD_OPC_Decode, 156, 22, 166, 2, // Opcode: t2LDRBi8 -/* 3913 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 3960 -/* 3918 */ MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 3960 -/* 3923 */ MCD_OPC_Decode, 154, 22, 161, 2, // Opcode: t2LDRB_PRE -/* 3928 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 3960 -/* 3933 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3950 -/* 3938 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3950 -/* 3945 */ MCD_OPC_Decode, 236, 22, 168, 2, // Opcode: t2PLDi12 -/* 3950 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3960 -/* 3955 */ MCD_OPC_Decode, 155, 22, 168, 2, // Opcode: t2LDRBi12 -/* 3960 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 3963 */ MCD_OPC_FilterValue, 15, 119, 16, 0, // Skip to: 8183 -/* 3968 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3985 -/* 3973 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3985 -/* 3980 */ MCD_OPC_Decode, 238, 22, 169, 2, // Opcode: t2PLDpci -/* 3985 */ MCD_OPC_CheckPredicate, 38, 97, 16, 0, // Skip to: 8183 -/* 3990 */ MCD_OPC_Decode, 157, 22, 169, 2, // Opcode: t2LDRBpci -/* 3995 */ MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 4226 -/* 4000 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4003 */ MCD_OPC_FilterValue, 1, 79, 16, 0, // Skip to: 8183 -/* 4008 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 4011 */ MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 4159 -/* 4016 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 4019 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4059 -/* 4024 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 4027 */ MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 4191 -/* 4032 */ MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4049 -/* 4037 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4049 -/* 4044 */ MCD_OPC_Decode, 243, 22, 165, 2, // Opcode: t2PLIs -/* 4049 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 4191 -/* 4054 */ MCD_OPC_Decode, 179, 22, 165, 2, // Opcode: t2LDRSBs -/* 4059 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4081 -/* 4064 */ MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 4191 -/* 4069 */ MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 4191 -/* 4076 */ MCD_OPC_Decode, 174, 22, 161, 2, // Opcode: t2LDRSB_POST -/* 4081 */ MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 4191 -/* 4086 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 4089 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 4144 -/* 4094 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 4097 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4119 -/* 4102 */ MCD_OPC_CheckPredicate, 54, 27, 0, 0, // Skip to: 4134 -/* 4107 */ MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 4134 -/* 4114 */ MCD_OPC_Decode, 241, 22, 166, 2, // Opcode: t2PLIi8 -/* 4119 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 4134 -/* 4124 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 4134 -/* 4129 */ MCD_OPC_Decode, 173, 22, 167, 2, // Opcode: t2LDRSBT -/* 4134 */ MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 4191 -/* 4139 */ MCD_OPC_Decode, 177, 22, 166, 2, // Opcode: t2LDRSBi8 -/* 4144 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 4191 -/* 4149 */ MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 4191 -/* 4154 */ MCD_OPC_Decode, 175, 22, 161, 2, // Opcode: t2LDRSB_PRE -/* 4159 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 4191 -/* 4164 */ MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4181 -/* 4169 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4181 -/* 4176 */ MCD_OPC_Decode, 240, 22, 168, 2, // Opcode: t2PLIi12 -/* 4181 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 4191 -/* 4186 */ MCD_OPC_Decode, 176, 22, 168, 2, // Opcode: t2LDRSBi12 -/* 4191 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 4194 */ MCD_OPC_FilterValue, 15, 144, 15, 0, // Skip to: 8183 -/* 4199 */ MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4216 -/* 4204 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4216 -/* 4211 */ MCD_OPC_Decode, 242, 22, 169, 2, // Opcode: t2PLIpci -/* 4216 */ MCD_OPC_CheckPredicate, 38, 122, 15, 0, // Skip to: 8183 -/* 4221 */ MCD_OPC_Decode, 178, 22, 169, 2, // Opcode: t2LDRSBpci -/* 4226 */ MCD_OPC_FilterValue, 2, 207, 2, 0, // Skip to: 4950 -/* 4231 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 4234 */ MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 4654 -/* 4239 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... -/* 4242 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 4324 -/* 4247 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 4250 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4272 -/* 4255 */ MCD_OPC_CheckPredicate, 38, 83, 15, 0, // Skip to: 8183 -/* 4260 */ MCD_OPC_CheckField, 12, 4, 15, 76, 15, 0, // Skip to: 8183 -/* 4267 */ MCD_OPC_Decode, 195, 22, 239, 1, // Opcode: t2LSLrr -/* 4272 */ MCD_OPC_FilterValue, 1, 66, 15, 0, // Skip to: 8183 -/* 4277 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4280 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4302 -/* 4285 */ MCD_OPC_CheckPredicate, 45, 53, 15, 0, // Skip to: 8183 -/* 4290 */ MCD_OPC_CheckField, 12, 4, 15, 46, 15, 0, // Skip to: 8183 -/* 4297 */ MCD_OPC_Decode, 141, 23, 170, 2, // Opcode: t2SADD8 -/* 4302 */ MCD_OPC_FilterValue, 1, 36, 15, 0, // Skip to: 8183 -/* 4307 */ MCD_OPC_CheckPredicate, 45, 31, 15, 0, // Skip to: 8183 -/* 4312 */ MCD_OPC_CheckField, 12, 4, 15, 24, 15, 0, // Skip to: 8183 -/* 4319 */ MCD_OPC_Decode, 140, 23, 170, 2, // Opcode: t2SADD16 -/* 4324 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 4390 -/* 4329 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4332 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4361 -/* 4337 */ MCD_OPC_CheckPredicate, 45, 1, 15, 0, // Skip to: 8183 -/* 4342 */ MCD_OPC_CheckField, 23, 1, 1, 250, 14, 0, // Skip to: 8183 -/* 4349 */ MCD_OPC_CheckField, 12, 4, 15, 243, 14, 0, // Skip to: 8183 -/* 4356 */ MCD_OPC_Decode, 246, 22, 170, 2, // Opcode: t2QADD8 -/* 4361 */ MCD_OPC_FilterValue, 1, 233, 14, 0, // Skip to: 8183 -/* 4366 */ MCD_OPC_CheckPredicate, 45, 228, 14, 0, // Skip to: 8183 -/* 4371 */ MCD_OPC_CheckField, 23, 1, 1, 221, 14, 0, // Skip to: 8183 -/* 4378 */ MCD_OPC_CheckField, 12, 4, 15, 214, 14, 0, // Skip to: 8183 -/* 4385 */ MCD_OPC_Decode, 245, 22, 170, 2, // Opcode: t2QADD16 -/* 4390 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 4456 -/* 4395 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4398 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4427 -/* 4403 */ MCD_OPC_CheckPredicate, 45, 191, 14, 0, // Skip to: 8183 -/* 4408 */ MCD_OPC_CheckField, 23, 1, 1, 184, 14, 0, // Skip to: 8183 -/* 4415 */ MCD_OPC_CheckField, 12, 4, 15, 177, 14, 0, // Skip to: 8183 -/* 4422 */ MCD_OPC_Decode, 152, 23, 170, 2, // Opcode: t2SHADD8 -/* 4427 */ MCD_OPC_FilterValue, 1, 167, 14, 0, // Skip to: 8183 -/* 4432 */ MCD_OPC_CheckPredicate, 45, 162, 14, 0, // Skip to: 8183 -/* 4437 */ MCD_OPC_CheckField, 23, 1, 1, 155, 14, 0, // Skip to: 8183 -/* 4444 */ MCD_OPC_CheckField, 12, 4, 15, 148, 14, 0, // Skip to: 8183 -/* 4451 */ MCD_OPC_Decode, 151, 23, 170, 2, // Opcode: t2SHADD16 -/* 4456 */ MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 4522 -/* 4461 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4464 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4493 -/* 4469 */ MCD_OPC_CheckPredicate, 45, 125, 14, 0, // Skip to: 8183 -/* 4474 */ MCD_OPC_CheckField, 23, 1, 1, 118, 14, 0, // Skip to: 8183 -/* 4481 */ MCD_OPC_CheckField, 12, 4, 15, 111, 14, 0, // Skip to: 8183 -/* 4488 */ MCD_OPC_Decode, 152, 24, 170, 2, // Opcode: t2UADD8 -/* 4493 */ MCD_OPC_FilterValue, 1, 101, 14, 0, // Skip to: 8183 -/* 4498 */ MCD_OPC_CheckPredicate, 45, 96, 14, 0, // Skip to: 8183 -/* 4503 */ MCD_OPC_CheckField, 23, 1, 1, 89, 14, 0, // Skip to: 8183 -/* 4510 */ MCD_OPC_CheckField, 12, 4, 15, 82, 14, 0, // Skip to: 8183 -/* 4517 */ MCD_OPC_Decode, 151, 24, 170, 2, // Opcode: t2UADD16 -/* 4522 */ MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 4588 -/* 4527 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4530 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4559 -/* 4535 */ MCD_OPC_CheckPredicate, 45, 59, 14, 0, // Skip to: 8183 -/* 4540 */ MCD_OPC_CheckField, 23, 1, 1, 52, 14, 0, // Skip to: 8183 -/* 4547 */ MCD_OPC_CheckField, 12, 4, 15, 45, 14, 0, // Skip to: 8183 -/* 4554 */ MCD_OPC_Decode, 167, 24, 170, 2, // Opcode: t2UQADD8 -/* 4559 */ MCD_OPC_FilterValue, 1, 35, 14, 0, // Skip to: 8183 -/* 4564 */ MCD_OPC_CheckPredicate, 45, 30, 14, 0, // Skip to: 8183 -/* 4569 */ MCD_OPC_CheckField, 23, 1, 1, 23, 14, 0, // Skip to: 8183 -/* 4576 */ MCD_OPC_CheckField, 12, 4, 15, 16, 14, 0, // Skip to: 8183 -/* 4583 */ MCD_OPC_Decode, 166, 24, 170, 2, // Opcode: t2UQADD16 -/* 4588 */ MCD_OPC_FilterValue, 6, 6, 14, 0, // Skip to: 8183 -/* 4593 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4596 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4625 -/* 4601 */ MCD_OPC_CheckPredicate, 45, 249, 13, 0, // Skip to: 8183 -/* 4606 */ MCD_OPC_CheckField, 23, 1, 1, 242, 13, 0, // Skip to: 8183 -/* 4613 */ MCD_OPC_CheckField, 12, 4, 15, 235, 13, 0, // Skip to: 8183 -/* 4620 */ MCD_OPC_Decode, 158, 24, 170, 2, // Opcode: t2UHADD8 -/* 4625 */ MCD_OPC_FilterValue, 1, 225, 13, 0, // Skip to: 8183 -/* 4630 */ MCD_OPC_CheckPredicate, 45, 220, 13, 0, // Skip to: 8183 -/* 4635 */ MCD_OPC_CheckField, 23, 1, 1, 213, 13, 0, // Skip to: 8183 -/* 4642 */ MCD_OPC_CheckField, 12, 4, 15, 206, 13, 0, // Skip to: 8183 -/* 4649 */ MCD_OPC_Decode, 157, 24, 170, 2, // Opcode: t2UHADD16 -/* 4654 */ MCD_OPC_FilterValue, 1, 196, 13, 0, // Skip to: 8183 -/* 4659 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4662 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 4806 -/* 4667 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 4670 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4710 -/* 4675 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4678 */ MCD_OPC_FilterValue, 15, 172, 13, 0, // Skip to: 8183 -/* 4683 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4700 -/* 4688 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 4700 -/* 4695 */ MCD_OPC_Decode, 137, 24, 171, 2, // Opcode: t2SXTH -/* 4700 */ MCD_OPC_CheckPredicate, 43, 150, 13, 0, // Skip to: 8183 -/* 4705 */ MCD_OPC_Decode, 134, 24, 172, 2, // Opcode: t2SXTAH -/* 4710 */ MCD_OPC_FilterValue, 1, 140, 13, 0, // Skip to: 8183 -/* 4715 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... -/* 4718 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4740 -/* 4723 */ MCD_OPC_CheckPredicate, 45, 127, 13, 0, // Skip to: 8183 -/* 4728 */ MCD_OPC_CheckField, 12, 4, 15, 120, 13, 0, // Skip to: 8183 -/* 4735 */ MCD_OPC_Decode, 244, 22, 173, 2, // Opcode: t2QADD -/* 4740 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4762 -/* 4745 */ MCD_OPC_CheckPredicate, 45, 105, 13, 0, // Skip to: 8183 -/* 4750 */ MCD_OPC_CheckField, 12, 4, 15, 98, 13, 0, // Skip to: 8183 -/* 4757 */ MCD_OPC_Decode, 248, 22, 173, 2, // Opcode: t2QDADD -/* 4762 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4784 -/* 4767 */ MCD_OPC_CheckPredicate, 45, 83, 13, 0, // Skip to: 8183 -/* 4772 */ MCD_OPC_CheckField, 12, 4, 15, 76, 13, 0, // Skip to: 8183 -/* 4779 */ MCD_OPC_Decode, 251, 22, 173, 2, // Opcode: t2QSUB -/* 4784 */ MCD_OPC_FilterValue, 3, 66, 13, 0, // Skip to: 8183 -/* 4789 */ MCD_OPC_CheckPredicate, 45, 61, 13, 0, // Skip to: 8183 -/* 4794 */ MCD_OPC_CheckField, 12, 4, 15, 54, 13, 0, // Skip to: 8183 -/* 4801 */ MCD_OPC_Decode, 249, 22, 173, 2, // Opcode: t2QDSUB -/* 4806 */ MCD_OPC_FilterValue, 1, 44, 13, 0, // Skip to: 8183 -/* 4811 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 4814 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4854 -/* 4819 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4822 */ MCD_OPC_FilterValue, 15, 28, 13, 0, // Skip to: 8183 -/* 4827 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4844 -/* 4832 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 4844 -/* 4839 */ MCD_OPC_Decode, 184, 24, 171, 2, // Opcode: t2UXTH -/* 4844 */ MCD_OPC_CheckPredicate, 43, 6, 13, 0, // Skip to: 8183 -/* 4849 */ MCD_OPC_Decode, 181, 24, 172, 2, // Opcode: t2UXTAH -/* 4854 */ MCD_OPC_FilterValue, 1, 252, 12, 0, // Skip to: 8183 -/* 4859 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... -/* 4862 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4884 -/* 4867 */ MCD_OPC_CheckPredicate, 38, 239, 12, 0, // Skip to: 8183 -/* 4872 */ MCD_OPC_CheckField, 12, 4, 15, 232, 12, 0, // Skip to: 8183 -/* 4879 */ MCD_OPC_Decode, 255, 22, 174, 2, // Opcode: t2REV -/* 4884 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4906 -/* 4889 */ MCD_OPC_CheckPredicate, 38, 217, 12, 0, // Skip to: 8183 -/* 4894 */ MCD_OPC_CheckField, 12, 4, 15, 210, 12, 0, // Skip to: 8183 -/* 4901 */ MCD_OPC_Decode, 128, 23, 174, 2, // Opcode: t2REV16 -/* 4906 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4928 -/* 4911 */ MCD_OPC_CheckPredicate, 38, 195, 12, 0, // Skip to: 8183 -/* 4916 */ MCD_OPC_CheckField, 12, 4, 15, 188, 12, 0, // Skip to: 8183 -/* 4923 */ MCD_OPC_Decode, 254, 22, 174, 2, // Opcode: t2RBIT -/* 4928 */ MCD_OPC_FilterValue, 3, 178, 12, 0, // Skip to: 8183 -/* 4933 */ MCD_OPC_CheckPredicate, 38, 173, 12, 0, // Skip to: 8183 -/* 4938 */ MCD_OPC_CheckField, 12, 4, 15, 166, 12, 0, // Skip to: 8183 -/* 4945 */ MCD_OPC_Decode, 129, 23, 174, 2, // Opcode: t2REVSH -/* 4950 */ MCD_OPC_FilterValue, 3, 156, 12, 0, // Skip to: 8183 -/* 4955 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 4958 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 5061 -/* 4963 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4966 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5021 -/* 4971 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 4974 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5006 -/* 4979 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4996 -/* 4984 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4996 -/* 4991 */ MCD_OPC_Decode, 221, 22, 170, 2, // Opcode: t2MUL -/* 4996 */ MCD_OPC_CheckPredicate, 38, 110, 12, 0, // Skip to: 8183 -/* 5001 */ MCD_OPC_Decode, 202, 22, 175, 2, // Opcode: t2MLA -/* 5006 */ MCD_OPC_FilterValue, 1, 100, 12, 0, // Skip to: 8183 -/* 5011 */ MCD_OPC_CheckPredicate, 38, 95, 12, 0, // Skip to: 8183 -/* 5016 */ MCD_OPC_Decode, 187, 23, 176, 2, // Opcode: t2SMULL -/* 5021 */ MCD_OPC_FilterValue, 1, 85, 12, 0, // Skip to: 8183 -/* 5026 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 5029 */ MCD_OPC_FilterValue, 0, 77, 12, 0, // Skip to: 8183 -/* 5034 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5051 -/* 5039 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5051 -/* 5046 */ MCD_OPC_Decode, 185, 23, 170, 2, // Opcode: t2SMULBB -/* 5051 */ MCD_OPC_CheckPredicate, 45, 55, 12, 0, // Skip to: 8183 -/* 5056 */ MCD_OPC_Decode, 158, 23, 175, 2, // Opcode: t2SMLABB -/* 5061 */ MCD_OPC_FilterValue, 1, 65, 0, 0, // Skip to: 5131 -/* 5066 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5069 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5091 -/* 5074 */ MCD_OPC_CheckPredicate, 38, 32, 12, 0, // Skip to: 8183 -/* 5079 */ MCD_OPC_CheckField, 23, 1, 0, 25, 12, 0, // Skip to: 8183 -/* 5086 */ MCD_OPC_Decode, 203, 22, 175, 2, // Opcode: t2MLS -/* 5091 */ MCD_OPC_FilterValue, 1, 15, 12, 0, // Skip to: 8183 -/* 5096 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 5099 */ MCD_OPC_FilterValue, 0, 7, 12, 0, // Skip to: 8183 -/* 5104 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5121 -/* 5109 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5121 -/* 5116 */ MCD_OPC_Decode, 186, 23, 170, 2, // Opcode: t2SMULBT -/* 5121 */ MCD_OPC_CheckPredicate, 45, 241, 11, 0, // Skip to: 8183 -/* 5126 */ MCD_OPC_Decode, 159, 23, 175, 2, // Opcode: t2SMLABT -/* 5131 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 5179 -/* 5136 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5139 */ MCD_OPC_FilterValue, 1, 223, 11, 0, // Skip to: 8183 -/* 5144 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 5147 */ MCD_OPC_FilterValue, 0, 215, 11, 0, // Skip to: 8183 -/* 5152 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5169 -/* 5157 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5169 -/* 5164 */ MCD_OPC_Decode, 188, 23, 170, 2, // Opcode: t2SMULTB -/* 5169 */ MCD_OPC_CheckPredicate, 45, 193, 11, 0, // Skip to: 8183 -/* 5174 */ MCD_OPC_Decode, 169, 23, 175, 2, // Opcode: t2SMLATB -/* 5179 */ MCD_OPC_FilterValue, 3, 43, 0, 0, // Skip to: 5227 -/* 5184 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5187 */ MCD_OPC_FilterValue, 1, 175, 11, 0, // Skip to: 8183 -/* 5192 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 5195 */ MCD_OPC_FilterValue, 0, 167, 11, 0, // Skip to: 8183 -/* 5200 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5217 -/* 5205 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5217 -/* 5212 */ MCD_OPC_Decode, 189, 23, 170, 2, // Opcode: t2SMULTT -/* 5217 */ MCD_OPC_CheckPredicate, 45, 145, 11, 0, // Skip to: 8183 -/* 5222 */ MCD_OPC_Decode, 170, 23, 175, 2, // Opcode: t2SMLATT -/* 5227 */ MCD_OPC_FilterValue, 15, 135, 11, 0, // Skip to: 8183 -/* 5232 */ MCD_OPC_CheckPredicate, 55, 130, 11, 0, // Skip to: 8183 -/* 5237 */ MCD_OPC_CheckField, 23, 1, 1, 123, 11, 0, // Skip to: 8183 -/* 5244 */ MCD_OPC_CheckField, 20, 1, 1, 116, 11, 0, // Skip to: 8183 -/* 5251 */ MCD_OPC_CheckField, 12, 4, 15, 109, 11, 0, // Skip to: 8183 -/* 5258 */ MCD_OPC_Decode, 147, 23, 170, 2, // Opcode: t2SDIV -/* 5263 */ MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 6421 -/* 5268 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... -/* 5271 */ MCD_OPC_FilterValue, 0, 82, 1, 0, // Skip to: 5614 -/* 5276 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5279 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 5409 -/* 5284 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 5287 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 5394 -/* 5292 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 5295 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5317 -/* 5300 */ MCD_OPC_CheckPredicate, 38, 62, 11, 0, // Skip to: 8183 -/* 5305 */ MCD_OPC_CheckField, 6, 4, 0, 55, 11, 0, // Skip to: 8183 -/* 5312 */ MCD_OPC_Decode, 248, 23, 160, 2, // Opcode: t2STRHs -/* 5317 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5339 -/* 5322 */ MCD_OPC_CheckPredicate, 38, 40, 11, 0, // Skip to: 8183 -/* 5327 */ MCD_OPC_CheckField, 8, 1, 1, 33, 11, 0, // Skip to: 8183 -/* 5334 */ MCD_OPC_Decode, 244, 23, 161, 2, // Opcode: t2STRH_POST -/* 5339 */ MCD_OPC_FilterValue, 3, 23, 11, 0, // Skip to: 8183 -/* 5344 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5347 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5379 -/* 5352 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 5369 -/* 5357 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 5369 -/* 5364 */ MCD_OPC_Decode, 243, 23, 162, 2, // Opcode: t2STRHT -/* 5369 */ MCD_OPC_CheckPredicate, 38, 249, 10, 0, // Skip to: 8183 -/* 5374 */ MCD_OPC_Decode, 247, 23, 163, 2, // Opcode: t2STRHi8 -/* 5379 */ MCD_OPC_FilterValue, 1, 239, 10, 0, // Skip to: 8183 -/* 5384 */ MCD_OPC_CheckPredicate, 38, 234, 10, 0, // Skip to: 8183 -/* 5389 */ MCD_OPC_Decode, 245, 23, 161, 2, // Opcode: t2STRH_PRE -/* 5394 */ MCD_OPC_FilterValue, 1, 224, 10, 0, // Skip to: 8183 -/* 5399 */ MCD_OPC_CheckPredicate, 38, 219, 10, 0, // Skip to: 8183 -/* 5404 */ MCD_OPC_Decode, 246, 23, 164, 2, // Opcode: t2STRHi12 -/* 5409 */ MCD_OPC_FilterValue, 1, 209, 10, 0, // Skip to: 8183 -/* 5414 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 5417 */ MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 5565 -/* 5422 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 5425 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 5465 -/* 5430 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 5433 */ MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 5597 -/* 5438 */ MCD_OPC_CheckPredicate, 56, 12, 0, 0, // Skip to: 5455 -/* 5443 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5455 -/* 5450 */ MCD_OPC_Decode, 235, 22, 165, 2, // Opcode: t2PLDWs -/* 5455 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 5597 -/* 5460 */ MCD_OPC_Decode, 172, 22, 165, 2, // Opcode: t2LDRHs -/* 5465 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5487 -/* 5470 */ MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 5597 -/* 5475 */ MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 5597 -/* 5482 */ MCD_OPC_Decode, 167, 22, 161, 2, // Opcode: t2LDRH_POST -/* 5487 */ MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 5597 -/* 5492 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5495 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5550 -/* 5500 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... -/* 5503 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5525 -/* 5508 */ MCD_OPC_CheckPredicate, 56, 27, 0, 0, // Skip to: 5540 -/* 5513 */ MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 5540 -/* 5520 */ MCD_OPC_Decode, 234, 22, 166, 2, // Opcode: t2PLDWi8 -/* 5525 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5540 -/* 5530 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5540 -/* 5535 */ MCD_OPC_Decode, 166, 22, 167, 2, // Opcode: t2LDRHT -/* 5540 */ MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 5597 -/* 5545 */ MCD_OPC_Decode, 170, 22, 166, 2, // Opcode: t2LDRHi8 -/* 5550 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 5597 -/* 5555 */ MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 5597 -/* 5560 */ MCD_OPC_Decode, 168, 22, 161, 2, // Opcode: t2LDRH_PRE -/* 5565 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5597 -/* 5570 */ MCD_OPC_CheckPredicate, 56, 12, 0, 0, // Skip to: 5587 -/* 5575 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5587 -/* 5582 */ MCD_OPC_Decode, 233, 22, 168, 2, // Opcode: t2PLDWi12 -/* 5587 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5597 -/* 5592 */ MCD_OPC_Decode, 169, 22, 168, 2, // Opcode: t2LDRHi12 -/* 5597 */ MCD_OPC_CheckPredicate, 38, 21, 10, 0, // Skip to: 8183 -/* 5602 */ MCD_OPC_CheckField, 16, 4, 15, 14, 10, 0, // Skip to: 8183 -/* 5609 */ MCD_OPC_Decode, 171, 22, 169, 2, // Opcode: t2LDRHpci -/* 5614 */ MCD_OPC_FilterValue, 1, 150, 0, 0, // Skip to: 5769 -/* 5619 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5622 */ MCD_OPC_FilterValue, 1, 252, 9, 0, // Skip to: 8183 -/* 5627 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 5630 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 5737 -/* 5635 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 5638 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5660 -/* 5643 */ MCD_OPC_CheckPredicate, 38, 104, 0, 0, // Skip to: 5752 -/* 5648 */ MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 5752 -/* 5655 */ MCD_OPC_Decode, 186, 22, 165, 2, // Opcode: t2LDRSHs -/* 5660 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5682 -/* 5665 */ MCD_OPC_CheckPredicate, 38, 82, 0, 0, // Skip to: 5752 -/* 5670 */ MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 5752 -/* 5677 */ MCD_OPC_Decode, 181, 22, 161, 2, // Opcode: t2LDRSH_POST -/* 5682 */ MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 5752 -/* 5687 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5690 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5722 -/* 5695 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 5712 -/* 5700 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 5712 -/* 5707 */ MCD_OPC_Decode, 180, 22, 167, 2, // Opcode: t2LDRSHT -/* 5712 */ MCD_OPC_CheckPredicate, 38, 35, 0, 0, // Skip to: 5752 -/* 5717 */ MCD_OPC_Decode, 184, 22, 166, 2, // Opcode: t2LDRSHi8 -/* 5722 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 5752 -/* 5727 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 5752 -/* 5732 */ MCD_OPC_Decode, 182, 22, 161, 2, // Opcode: t2LDRSH_PRE -/* 5737 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5752 -/* 5742 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5752 -/* 5747 */ MCD_OPC_Decode, 183, 22, 168, 2, // Opcode: t2LDRSHi12 -/* 5752 */ MCD_OPC_CheckPredicate, 38, 122, 9, 0, // Skip to: 8183 -/* 5757 */ MCD_OPC_CheckField, 16, 4, 15, 115, 9, 0, // Skip to: 8183 -/* 5764 */ MCD_OPC_Decode, 185, 22, 169, 2, // Opcode: t2LDRSHpci -/* 5769 */ MCD_OPC_FilterValue, 2, 156, 1, 0, // Skip to: 6186 -/* 5774 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 5777 */ MCD_OPC_FilterValue, 0, 242, 0, 0, // Skip to: 6024 -/* 5782 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... -/* 5785 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 5844 -/* 5790 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 5793 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5815 -/* 5798 */ MCD_OPC_CheckPredicate, 38, 76, 9, 0, // Skip to: 8183 -/* 5803 */ MCD_OPC_CheckField, 12, 4, 15, 69, 9, 0, // Skip to: 8183 -/* 5810 */ MCD_OPC_Decode, 197, 22, 239, 1, // Opcode: t2LSRrr -/* 5815 */ MCD_OPC_FilterValue, 1, 59, 9, 0, // Skip to: 8183 -/* 5820 */ MCD_OPC_CheckPredicate, 45, 54, 9, 0, // Skip to: 8183 -/* 5825 */ MCD_OPC_CheckField, 20, 1, 0, 47, 9, 0, // Skip to: 8183 -/* 5832 */ MCD_OPC_CheckField, 12, 4, 15, 40, 9, 0, // Skip to: 8183 -/* 5839 */ MCD_OPC_Decode, 142, 23, 170, 2, // Opcode: t2SASX -/* 5844 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5880 -/* 5849 */ MCD_OPC_CheckPredicate, 45, 25, 9, 0, // Skip to: 8183 -/* 5854 */ MCD_OPC_CheckField, 23, 1, 1, 18, 9, 0, // Skip to: 8183 -/* 5861 */ MCD_OPC_CheckField, 20, 1, 0, 11, 9, 0, // Skip to: 8183 -/* 5868 */ MCD_OPC_CheckField, 12, 4, 15, 4, 9, 0, // Skip to: 8183 -/* 5875 */ MCD_OPC_Decode, 247, 22, 170, 2, // Opcode: t2QASX -/* 5880 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 5916 -/* 5885 */ MCD_OPC_CheckPredicate, 45, 245, 8, 0, // Skip to: 8183 -/* 5890 */ MCD_OPC_CheckField, 23, 1, 1, 238, 8, 0, // Skip to: 8183 -/* 5897 */ MCD_OPC_CheckField, 20, 1, 0, 231, 8, 0, // Skip to: 8183 -/* 5904 */ MCD_OPC_CheckField, 12, 4, 15, 224, 8, 0, // Skip to: 8183 -/* 5911 */ MCD_OPC_Decode, 153, 23, 170, 2, // Opcode: t2SHASX -/* 5916 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 5952 -/* 5921 */ MCD_OPC_CheckPredicate, 45, 209, 8, 0, // Skip to: 8183 -/* 5926 */ MCD_OPC_CheckField, 23, 1, 1, 202, 8, 0, // Skip to: 8183 -/* 5933 */ MCD_OPC_CheckField, 20, 1, 0, 195, 8, 0, // Skip to: 8183 -/* 5940 */ MCD_OPC_CheckField, 12, 4, 15, 188, 8, 0, // Skip to: 8183 -/* 5947 */ MCD_OPC_Decode, 153, 24, 170, 2, // Opcode: t2UASX -/* 5952 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 5988 -/* 5957 */ MCD_OPC_CheckPredicate, 45, 173, 8, 0, // Skip to: 8183 -/* 5962 */ MCD_OPC_CheckField, 23, 1, 1, 166, 8, 0, // Skip to: 8183 -/* 5969 */ MCD_OPC_CheckField, 20, 1, 0, 159, 8, 0, // Skip to: 8183 -/* 5976 */ MCD_OPC_CheckField, 12, 4, 15, 152, 8, 0, // Skip to: 8183 -/* 5983 */ MCD_OPC_Decode, 168, 24, 170, 2, // Opcode: t2UQASX -/* 5988 */ MCD_OPC_FilterValue, 6, 142, 8, 0, // Skip to: 8183 -/* 5993 */ MCD_OPC_CheckPredicate, 45, 137, 8, 0, // Skip to: 8183 -/* 5998 */ MCD_OPC_CheckField, 23, 1, 1, 130, 8, 0, // Skip to: 8183 -/* 6005 */ MCD_OPC_CheckField, 20, 1, 0, 123, 8, 0, // Skip to: 8183 -/* 6012 */ MCD_OPC_CheckField, 12, 4, 15, 116, 8, 0, // Skip to: 8183 -/* 6019 */ MCD_OPC_Decode, 159, 24, 170, 2, // Opcode: t2UHASX -/* 6024 */ MCD_OPC_FilterValue, 1, 106, 8, 0, // Skip to: 8183 -/* 6029 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6032 */ MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 6109 -/* 6037 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 6040 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6080 -/* 6045 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6048 */ MCD_OPC_FilterValue, 15, 82, 8, 0, // Skip to: 8183 -/* 6053 */ MCD_OPC_CheckPredicate, 43, 12, 0, 0, // Skip to: 6070 -/* 6058 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 6070 -/* 6065 */ MCD_OPC_Decode, 136, 24, 171, 2, // Opcode: t2SXTB16 -/* 6070 */ MCD_OPC_CheckPredicate, 43, 60, 8, 0, // Skip to: 8183 -/* 6075 */ MCD_OPC_Decode, 133, 24, 172, 2, // Opcode: t2SXTAB16 -/* 6080 */ MCD_OPC_FilterValue, 1, 50, 8, 0, // Skip to: 8183 -/* 6085 */ MCD_OPC_CheckPredicate, 45, 45, 8, 0, // Skip to: 8183 -/* 6090 */ MCD_OPC_CheckField, 12, 4, 15, 38, 8, 0, // Skip to: 8183 -/* 6097 */ MCD_OPC_CheckField, 4, 3, 0, 31, 8, 0, // Skip to: 8183 -/* 6104 */ MCD_OPC_Decode, 148, 23, 177, 2, // Opcode: t2SEL -/* 6109 */ MCD_OPC_FilterValue, 1, 21, 8, 0, // Skip to: 8183 -/* 6114 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 6117 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6157 -/* 6122 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6125 */ MCD_OPC_FilterValue, 15, 5, 8, 0, // Skip to: 8183 -/* 6130 */ MCD_OPC_CheckPredicate, 43, 12, 0, 0, // Skip to: 6147 -/* 6135 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 6147 -/* 6142 */ MCD_OPC_Decode, 183, 24, 171, 2, // Opcode: t2UXTB16 -/* 6147 */ MCD_OPC_CheckPredicate, 43, 239, 7, 0, // Skip to: 8183 -/* 6152 */ MCD_OPC_Decode, 180, 24, 172, 2, // Opcode: t2UXTAB16 -/* 6157 */ MCD_OPC_FilterValue, 1, 229, 7, 0, // Skip to: 8183 -/* 6162 */ MCD_OPC_CheckPredicate, 38, 224, 7, 0, // Skip to: 8183 -/* 6167 */ MCD_OPC_CheckField, 12, 4, 15, 217, 7, 0, // Skip to: 8183 -/* 6174 */ MCD_OPC_CheckField, 4, 3, 0, 210, 7, 0, // Skip to: 8183 -/* 6181 */ MCD_OPC_Decode, 222, 21, 174, 2, // Opcode: t2CLZ -/* 6186 */ MCD_OPC_FilterValue, 3, 200, 7, 0, // Skip to: 8183 -/* 6191 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 6194 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 6297 -/* 6199 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6202 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 6257 -/* 6207 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 6210 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6242 -/* 6215 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6232 -/* 6220 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6232 -/* 6227 */ MCD_OPC_Decode, 183, 23, 170, 2, // Opcode: t2SMUAD -/* 6232 */ MCD_OPC_CheckPredicate, 45, 154, 7, 0, // Skip to: 8183 -/* 6237 */ MCD_OPC_Decode, 160, 23, 175, 2, // Opcode: t2SMLAD -/* 6242 */ MCD_OPC_FilterValue, 1, 144, 7, 0, // Skip to: 8183 -/* 6247 */ MCD_OPC_CheckPredicate, 38, 139, 7, 0, // Skip to: 8183 -/* 6252 */ MCD_OPC_Decode, 165, 24, 176, 2, // Opcode: t2UMULL -/* 6257 */ MCD_OPC_FilterValue, 1, 129, 7, 0, // Skip to: 8183 -/* 6262 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 6265 */ MCD_OPC_FilterValue, 0, 121, 7, 0, // Skip to: 8183 -/* 6270 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6287 -/* 6275 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6287 -/* 6282 */ MCD_OPC_Decode, 190, 23, 170, 2, // Opcode: t2SMULWB -/* 6287 */ MCD_OPC_CheckPredicate, 45, 99, 7, 0, // Skip to: 8183 -/* 6292 */ MCD_OPC_Decode, 171, 23, 175, 2, // Opcode: t2SMLAWB -/* 6297 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 6385 -/* 6302 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6305 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6345 -/* 6310 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 6313 */ MCD_OPC_FilterValue, 0, 73, 7, 0, // Skip to: 8183 -/* 6318 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6335 -/* 6323 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6335 -/* 6330 */ MCD_OPC_Decode, 184, 23, 170, 2, // Opcode: t2SMUADX -/* 6335 */ MCD_OPC_CheckPredicate, 45, 51, 7, 0, // Skip to: 8183 -/* 6340 */ MCD_OPC_Decode, 161, 23, 175, 2, // Opcode: t2SMLADX -/* 6345 */ MCD_OPC_FilterValue, 1, 41, 7, 0, // Skip to: 8183 -/* 6350 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 6353 */ MCD_OPC_FilterValue, 0, 33, 7, 0, // Skip to: 8183 -/* 6358 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6375 -/* 6363 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6375 -/* 6370 */ MCD_OPC_Decode, 191, 23, 170, 2, // Opcode: t2SMULWT -/* 6375 */ MCD_OPC_CheckPredicate, 45, 11, 7, 0, // Skip to: 8183 -/* 6380 */ MCD_OPC_Decode, 172, 23, 175, 2, // Opcode: t2SMLAWT -/* 6385 */ MCD_OPC_FilterValue, 15, 1, 7, 0, // Skip to: 8183 -/* 6390 */ MCD_OPC_CheckPredicate, 55, 252, 6, 0, // Skip to: 8183 -/* 6395 */ MCD_OPC_CheckField, 23, 1, 1, 245, 6, 0, // Skip to: 8183 -/* 6402 */ MCD_OPC_CheckField, 20, 1, 1, 238, 6, 0, // Skip to: 8183 -/* 6409 */ MCD_OPC_CheckField, 12, 4, 15, 231, 6, 0, // Skip to: 8183 -/* 6416 */ MCD_OPC_Decode, 156, 24, 170, 2, // Opcode: t2UDIV -/* 6421 */ MCD_OPC_FilterValue, 2, 107, 5, 0, // Skip to: 7813 -/* 6426 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... -/* 6429 */ MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 6714 -/* 6434 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6437 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 6567 -/* 6442 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 6445 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6552 -/* 6450 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 6453 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6475 -/* 6458 */ MCD_OPC_CheckPredicate, 38, 184, 6, 0, // Skip to: 8183 -/* 6463 */ MCD_OPC_CheckField, 6, 4, 0, 177, 6, 0, // Skip to: 8183 -/* 6470 */ MCD_OPC_Decode, 254, 23, 178, 2, // Opcode: t2STRs -/* 6475 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6497 -/* 6480 */ MCD_OPC_CheckPredicate, 38, 162, 6, 0, // Skip to: 8183 -/* 6485 */ MCD_OPC_CheckField, 8, 1, 1, 155, 6, 0, // Skip to: 8183 -/* 6492 */ MCD_OPC_Decode, 250, 23, 161, 2, // Opcode: t2STR_POST -/* 6497 */ MCD_OPC_FilterValue, 3, 145, 6, 0, // Skip to: 8183 -/* 6502 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6505 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6537 -/* 6510 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 6527 -/* 6515 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6527 -/* 6522 */ MCD_OPC_Decode, 249, 23, 162, 2, // Opcode: t2STRT -/* 6527 */ MCD_OPC_CheckPredicate, 38, 115, 6, 0, // Skip to: 8183 -/* 6532 */ MCD_OPC_Decode, 253, 23, 179, 2, // Opcode: t2STRi8 -/* 6537 */ MCD_OPC_FilterValue, 1, 105, 6, 0, // Skip to: 8183 -/* 6542 */ MCD_OPC_CheckPredicate, 38, 100, 6, 0, // Skip to: 8183 -/* 6547 */ MCD_OPC_Decode, 251, 23, 161, 2, // Opcode: t2STR_PRE -/* 6552 */ MCD_OPC_FilterValue, 1, 90, 6, 0, // Skip to: 8183 -/* 6557 */ MCD_OPC_CheckPredicate, 38, 85, 6, 0, // Skip to: 8183 -/* 6562 */ MCD_OPC_Decode, 252, 23, 180, 2, // Opcode: t2STRi12 -/* 6567 */ MCD_OPC_FilterValue, 1, 75, 6, 0, // Skip to: 8183 -/* 6572 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 6575 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6682 -/* 6580 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 6583 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6605 -/* 6588 */ MCD_OPC_CheckPredicate, 38, 104, 0, 0, // Skip to: 6697 -/* 6593 */ MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 6697 -/* 6600 */ MCD_OPC_Decode, 193, 22, 165, 2, // Opcode: t2LDRs -/* 6605 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6627 -/* 6610 */ MCD_OPC_CheckPredicate, 38, 82, 0, 0, // Skip to: 6697 -/* 6615 */ MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 6697 -/* 6622 */ MCD_OPC_Decode, 188, 22, 161, 2, // Opcode: t2LDR_POST -/* 6627 */ MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 6697 -/* 6632 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6635 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6667 -/* 6640 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 6657 -/* 6645 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6657 -/* 6652 */ MCD_OPC_Decode, 187, 22, 167, 2, // Opcode: t2LDRT -/* 6657 */ MCD_OPC_CheckPredicate, 38, 35, 0, 0, // Skip to: 6697 -/* 6662 */ MCD_OPC_Decode, 191, 22, 166, 2, // Opcode: t2LDRi8 -/* 6667 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 6697 -/* 6672 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 6697 -/* 6677 */ MCD_OPC_Decode, 189, 22, 161, 2, // Opcode: t2LDR_PRE -/* 6682 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6697 -/* 6687 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 6697 -/* 6692 */ MCD_OPC_Decode, 190, 22, 168, 2, // Opcode: t2LDRi12 -/* 6697 */ MCD_OPC_CheckPredicate, 38, 201, 5, 0, // Skip to: 8183 -/* 6702 */ MCD_OPC_CheckField, 16, 4, 15, 194, 5, 0, // Skip to: 8183 -/* 6709 */ MCD_OPC_Decode, 192, 22, 169, 2, // Opcode: t2LDRpci -/* 6714 */ MCD_OPC_FilterValue, 2, 163, 2, 0, // Skip to: 7394 -/* 6719 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 6722 */ MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 7142 -/* 6727 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... -/* 6730 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 6812 -/* 6735 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 6738 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6760 -/* 6743 */ MCD_OPC_CheckPredicate, 38, 155, 5, 0, // Skip to: 8183 -/* 6748 */ MCD_OPC_CheckField, 12, 4, 15, 148, 5, 0, // Skip to: 8183 -/* 6755 */ MCD_OPC_Decode, 210, 21, 239, 1, // Opcode: t2ASRrr -/* 6760 */ MCD_OPC_FilterValue, 1, 138, 5, 0, // Skip to: 8183 -/* 6765 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6768 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6790 -/* 6773 */ MCD_OPC_CheckPredicate, 45, 125, 5, 0, // Skip to: 8183 -/* 6778 */ MCD_OPC_CheckField, 12, 4, 15, 118, 5, 0, // Skip to: 8183 -/* 6785 */ MCD_OPC_Decode, 202, 23, 170, 2, // Opcode: t2SSUB8 -/* 6790 */ MCD_OPC_FilterValue, 1, 108, 5, 0, // Skip to: 8183 -/* 6795 */ MCD_OPC_CheckPredicate, 45, 103, 5, 0, // Skip to: 8183 -/* 6800 */ MCD_OPC_CheckField, 12, 4, 15, 96, 5, 0, // Skip to: 8183 -/* 6807 */ MCD_OPC_Decode, 201, 23, 170, 2, // Opcode: t2SSUB16 -/* 6812 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 6878 -/* 6817 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6820 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6849 -/* 6825 */ MCD_OPC_CheckPredicate, 45, 73, 5, 0, // Skip to: 8183 -/* 6830 */ MCD_OPC_CheckField, 23, 1, 1, 66, 5, 0, // Skip to: 8183 -/* 6837 */ MCD_OPC_CheckField, 12, 4, 15, 59, 5, 0, // Skip to: 8183 -/* 6844 */ MCD_OPC_Decode, 253, 22, 170, 2, // Opcode: t2QSUB8 -/* 6849 */ MCD_OPC_FilterValue, 1, 49, 5, 0, // Skip to: 8183 -/* 6854 */ MCD_OPC_CheckPredicate, 45, 44, 5, 0, // Skip to: 8183 -/* 6859 */ MCD_OPC_CheckField, 23, 1, 1, 37, 5, 0, // Skip to: 8183 -/* 6866 */ MCD_OPC_CheckField, 12, 4, 15, 30, 5, 0, // Skip to: 8183 -/* 6873 */ MCD_OPC_Decode, 252, 22, 170, 2, // Opcode: t2QSUB16 -/* 6878 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 6944 -/* 6883 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6886 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6915 -/* 6891 */ MCD_OPC_CheckPredicate, 45, 7, 5, 0, // Skip to: 8183 -/* 6896 */ MCD_OPC_CheckField, 23, 1, 1, 0, 5, 0, // Skip to: 8183 -/* 6903 */ MCD_OPC_CheckField, 12, 4, 15, 249, 4, 0, // Skip to: 8183 -/* 6910 */ MCD_OPC_Decode, 156, 23, 170, 2, // Opcode: t2SHSUB8 -/* 6915 */ MCD_OPC_FilterValue, 1, 239, 4, 0, // Skip to: 8183 -/* 6920 */ MCD_OPC_CheckPredicate, 45, 234, 4, 0, // Skip to: 8183 -/* 6925 */ MCD_OPC_CheckField, 23, 1, 1, 227, 4, 0, // Skip to: 8183 -/* 6932 */ MCD_OPC_CheckField, 12, 4, 15, 220, 4, 0, // Skip to: 8183 -/* 6939 */ MCD_OPC_Decode, 155, 23, 170, 2, // Opcode: t2SHSUB16 -/* 6944 */ MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 7010 -/* 6949 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6952 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6981 -/* 6957 */ MCD_OPC_CheckPredicate, 45, 197, 4, 0, // Skip to: 8183 -/* 6962 */ MCD_OPC_CheckField, 23, 1, 1, 190, 4, 0, // Skip to: 8183 -/* 6969 */ MCD_OPC_CheckField, 12, 4, 15, 183, 4, 0, // Skip to: 8183 -/* 6976 */ MCD_OPC_Decode, 178, 24, 170, 2, // Opcode: t2USUB8 -/* 6981 */ MCD_OPC_FilterValue, 1, 173, 4, 0, // Skip to: 8183 -/* 6986 */ MCD_OPC_CheckPredicate, 45, 168, 4, 0, // Skip to: 8183 -/* 6991 */ MCD_OPC_CheckField, 23, 1, 1, 161, 4, 0, // Skip to: 8183 -/* 6998 */ MCD_OPC_CheckField, 12, 4, 15, 154, 4, 0, // Skip to: 8183 -/* 7005 */ MCD_OPC_Decode, 177, 24, 170, 2, // Opcode: t2USUB16 -/* 7010 */ MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 7076 -/* 7015 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7018 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7047 -/* 7023 */ MCD_OPC_CheckPredicate, 45, 131, 4, 0, // Skip to: 8183 -/* 7028 */ MCD_OPC_CheckField, 23, 1, 1, 124, 4, 0, // Skip to: 8183 -/* 7035 */ MCD_OPC_CheckField, 12, 4, 15, 117, 4, 0, // Skip to: 8183 -/* 7042 */ MCD_OPC_Decode, 171, 24, 170, 2, // Opcode: t2UQSUB8 -/* 7047 */ MCD_OPC_FilterValue, 1, 107, 4, 0, // Skip to: 8183 -/* 7052 */ MCD_OPC_CheckPredicate, 45, 102, 4, 0, // Skip to: 8183 -/* 7057 */ MCD_OPC_CheckField, 23, 1, 1, 95, 4, 0, // Skip to: 8183 -/* 7064 */ MCD_OPC_CheckField, 12, 4, 15, 88, 4, 0, // Skip to: 8183 -/* 7071 */ MCD_OPC_Decode, 170, 24, 170, 2, // Opcode: t2UQSUB16 -/* 7076 */ MCD_OPC_FilterValue, 6, 78, 4, 0, // Skip to: 8183 -/* 7081 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7084 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7113 -/* 7089 */ MCD_OPC_CheckPredicate, 45, 65, 4, 0, // Skip to: 8183 -/* 7094 */ MCD_OPC_CheckField, 23, 1, 1, 58, 4, 0, // Skip to: 8183 -/* 7101 */ MCD_OPC_CheckField, 12, 4, 15, 51, 4, 0, // Skip to: 8183 -/* 7108 */ MCD_OPC_Decode, 162, 24, 170, 2, // Opcode: t2UHSUB8 -/* 7113 */ MCD_OPC_FilterValue, 1, 41, 4, 0, // Skip to: 8183 -/* 7118 */ MCD_OPC_CheckPredicate, 45, 36, 4, 0, // Skip to: 8183 -/* 7123 */ MCD_OPC_CheckField, 23, 1, 1, 29, 4, 0, // Skip to: 8183 -/* 7130 */ MCD_OPC_CheckField, 12, 4, 15, 22, 4, 0, // Skip to: 8183 -/* 7137 */ MCD_OPC_Decode, 161, 24, 170, 2, // Opcode: t2UHSUB16 -/* 7142 */ MCD_OPC_FilterValue, 1, 12, 4, 0, // Skip to: 8183 -/* 7147 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7150 */ MCD_OPC_FilterValue, 0, 117, 0, 0, // Skip to: 7272 -/* 7155 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 7158 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7198 -/* 7163 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7166 */ MCD_OPC_FilterValue, 15, 244, 3, 0, // Skip to: 8183 -/* 7171 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 7188 -/* 7176 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 7188 -/* 7183 */ MCD_OPC_Decode, 135, 24, 171, 2, // Opcode: t2SXTB -/* 7188 */ MCD_OPC_CheckPredicate, 43, 222, 3, 0, // Skip to: 8183 -/* 7193 */ MCD_OPC_Decode, 132, 24, 172, 2, // Opcode: t2SXTAB -/* 7198 */ MCD_OPC_FilterValue, 1, 212, 3, 0, // Skip to: 8183 -/* 7203 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... -/* 7206 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7228 -/* 7211 */ MCD_OPC_CheckPredicate, 57, 199, 3, 0, // Skip to: 8183 -/* 7216 */ MCD_OPC_CheckField, 12, 4, 15, 192, 3, 0, // Skip to: 8183 -/* 7223 */ MCD_OPC_Decode, 232, 21, 170, 2, // Opcode: t2CRC32B -/* 7228 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 7250 -/* 7233 */ MCD_OPC_CheckPredicate, 57, 177, 3, 0, // Skip to: 8183 -/* 7238 */ MCD_OPC_CheckField, 12, 4, 15, 170, 3, 0, // Skip to: 8183 -/* 7245 */ MCD_OPC_Decode, 236, 21, 170, 2, // Opcode: t2CRC32H -/* 7250 */ MCD_OPC_FilterValue, 2, 160, 3, 0, // Skip to: 8183 -/* 7255 */ MCD_OPC_CheckPredicate, 57, 155, 3, 0, // Skip to: 8183 -/* 7260 */ MCD_OPC_CheckField, 12, 4, 15, 148, 3, 0, // Skip to: 8183 -/* 7267 */ MCD_OPC_Decode, 237, 21, 170, 2, // Opcode: t2CRC32W -/* 7272 */ MCD_OPC_FilterValue, 1, 138, 3, 0, // Skip to: 8183 -/* 7277 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 7280 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7320 -/* 7285 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7288 */ MCD_OPC_FilterValue, 15, 122, 3, 0, // Skip to: 8183 -/* 7293 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 7310 -/* 7298 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 7310 -/* 7305 */ MCD_OPC_Decode, 182, 24, 171, 2, // Opcode: t2UXTB -/* 7310 */ MCD_OPC_CheckPredicate, 43, 100, 3, 0, // Skip to: 8183 -/* 7315 */ MCD_OPC_Decode, 179, 24, 172, 2, // Opcode: t2UXTAB -/* 7320 */ MCD_OPC_FilterValue, 1, 90, 3, 0, // Skip to: 8183 -/* 7325 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... -/* 7328 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7350 -/* 7333 */ MCD_OPC_CheckPredicate, 57, 77, 3, 0, // Skip to: 8183 -/* 7338 */ MCD_OPC_CheckField, 12, 4, 15, 70, 3, 0, // Skip to: 8183 -/* 7345 */ MCD_OPC_Decode, 233, 21, 170, 2, // Opcode: t2CRC32CB -/* 7350 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 7372 -/* 7355 */ MCD_OPC_CheckPredicate, 57, 55, 3, 0, // Skip to: 8183 -/* 7360 */ MCD_OPC_CheckField, 12, 4, 15, 48, 3, 0, // Skip to: 8183 -/* 7367 */ MCD_OPC_Decode, 234, 21, 170, 2, // Opcode: t2CRC32CH -/* 7372 */ MCD_OPC_FilterValue, 2, 38, 3, 0, // Skip to: 8183 -/* 7377 */ MCD_OPC_CheckPredicate, 57, 33, 3, 0, // Skip to: 8183 -/* 7382 */ MCD_OPC_CheckField, 12, 4, 15, 26, 3, 0, // Skip to: 8183 -/* 7389 */ MCD_OPC_Decode, 235, 21, 170, 2, // Opcode: t2CRC32CW -/* 7394 */ MCD_OPC_FilterValue, 3, 16, 3, 0, // Skip to: 8183 -/* 7399 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 7402 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 7505 -/* 7407 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7410 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 7465 -/* 7415 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 7418 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 7450 -/* 7423 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7440 -/* 7428 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7440 -/* 7435 */ MCD_OPC_Decode, 192, 23, 170, 2, // Opcode: t2SMUSD -/* 7440 */ MCD_OPC_CheckPredicate, 45, 226, 2, 0, // Skip to: 8183 -/* 7445 */ MCD_OPC_Decode, 173, 23, 175, 2, // Opcode: t2SMLSD -/* 7450 */ MCD_OPC_FilterValue, 1, 216, 2, 0, // Skip to: 8183 -/* 7455 */ MCD_OPC_CheckPredicate, 38, 211, 2, 0, // Skip to: 8183 -/* 7460 */ MCD_OPC_Decode, 162, 23, 181, 2, // Opcode: t2SMLAL -/* 7465 */ MCD_OPC_FilterValue, 1, 201, 2, 0, // Skip to: 8183 -/* 7470 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 7473 */ MCD_OPC_FilterValue, 0, 193, 2, 0, // Skip to: 8183 -/* 7478 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7495 -/* 7483 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7495 -/* 7490 */ MCD_OPC_Decode, 181, 23, 170, 2, // Opcode: t2SMMUL -/* 7495 */ MCD_OPC_CheckPredicate, 45, 171, 2, 0, // Skip to: 8183 -/* 7500 */ MCD_OPC_Decode, 177, 23, 175, 2, // Opcode: t2SMMLA -/* 7505 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 7593 -/* 7510 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7513 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7553 -/* 7518 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 7521 */ MCD_OPC_FilterValue, 0, 145, 2, 0, // Skip to: 8183 -/* 7526 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7543 -/* 7531 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7543 -/* 7538 */ MCD_OPC_Decode, 193, 23, 170, 2, // Opcode: t2SMUSDX -/* 7543 */ MCD_OPC_CheckPredicate, 45, 123, 2, 0, // Skip to: 8183 -/* 7548 */ MCD_OPC_Decode, 174, 23, 175, 2, // Opcode: t2SMLSDX -/* 7553 */ MCD_OPC_FilterValue, 1, 113, 2, 0, // Skip to: 8183 -/* 7558 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 7561 */ MCD_OPC_FilterValue, 0, 105, 2, 0, // Skip to: 8183 -/* 7566 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7583 -/* 7571 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7583 -/* 7578 */ MCD_OPC_Decode, 182, 23, 170, 2, // Opcode: t2SMMULR -/* 7583 */ MCD_OPC_CheckPredicate, 45, 83, 2, 0, // Skip to: 8183 -/* 7588 */ MCD_OPC_Decode, 178, 23, 175, 2, // Opcode: t2SMMLAR -/* 7593 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 7622 -/* 7598 */ MCD_OPC_CheckPredicate, 45, 68, 2, 0, // Skip to: 8183 -/* 7603 */ MCD_OPC_CheckField, 23, 1, 1, 61, 2, 0, // Skip to: 8183 -/* 7610 */ MCD_OPC_CheckField, 20, 1, 0, 54, 2, 0, // Skip to: 8183 -/* 7617 */ MCD_OPC_Decode, 163, 23, 181, 2, // Opcode: t2SMLALBB -/* 7622 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 7651 -/* 7627 */ MCD_OPC_CheckPredicate, 45, 39, 2, 0, // Skip to: 8183 -/* 7632 */ MCD_OPC_CheckField, 23, 1, 1, 32, 2, 0, // Skip to: 8183 -/* 7639 */ MCD_OPC_CheckField, 20, 1, 0, 25, 2, 0, // Skip to: 8183 -/* 7646 */ MCD_OPC_Decode, 164, 23, 181, 2, // Opcode: t2SMLALBT -/* 7651 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 7680 -/* 7656 */ MCD_OPC_CheckPredicate, 45, 10, 2, 0, // Skip to: 8183 -/* 7661 */ MCD_OPC_CheckField, 23, 1, 1, 3, 2, 0, // Skip to: 8183 -/* 7668 */ MCD_OPC_CheckField, 20, 1, 0, 252, 1, 0, // Skip to: 8183 -/* 7675 */ MCD_OPC_Decode, 167, 23, 181, 2, // Opcode: t2SMLALTB -/* 7680 */ MCD_OPC_FilterValue, 11, 24, 0, 0, // Skip to: 7709 -/* 7685 */ MCD_OPC_CheckPredicate, 45, 237, 1, 0, // Skip to: 8183 -/* 7690 */ MCD_OPC_CheckField, 23, 1, 1, 230, 1, 0, // Skip to: 8183 -/* 7697 */ MCD_OPC_CheckField, 20, 1, 0, 223, 1, 0, // Skip to: 8183 -/* 7704 */ MCD_OPC_Decode, 168, 23, 181, 2, // Opcode: t2SMLALTT -/* 7709 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 7761 -/* 7714 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7717 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7739 -/* 7722 */ MCD_OPC_CheckPredicate, 45, 200, 1, 0, // Skip to: 8183 -/* 7727 */ MCD_OPC_CheckField, 23, 1, 1, 193, 1, 0, // Skip to: 8183 -/* 7734 */ MCD_OPC_Decode, 165, 23, 181, 2, // Opcode: t2SMLALD -/* 7739 */ MCD_OPC_FilterValue, 1, 183, 1, 0, // Skip to: 8183 -/* 7744 */ MCD_OPC_CheckPredicate, 45, 178, 1, 0, // Skip to: 8183 -/* 7749 */ MCD_OPC_CheckField, 23, 1, 1, 171, 1, 0, // Skip to: 8183 -/* 7756 */ MCD_OPC_Decode, 175, 23, 181, 2, // Opcode: t2SMLSLD -/* 7761 */ MCD_OPC_FilterValue, 13, 161, 1, 0, // Skip to: 8183 -/* 7766 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7769 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7791 -/* 7774 */ MCD_OPC_CheckPredicate, 45, 148, 1, 0, // Skip to: 8183 -/* 7779 */ MCD_OPC_CheckField, 23, 1, 1, 141, 1, 0, // Skip to: 8183 -/* 7786 */ MCD_OPC_Decode, 166, 23, 181, 2, // Opcode: t2SMLALDX -/* 7791 */ MCD_OPC_FilterValue, 1, 131, 1, 0, // Skip to: 8183 -/* 7796 */ MCD_OPC_CheckPredicate, 45, 126, 1, 0, // Skip to: 8183 -/* 7801 */ MCD_OPC_CheckField, 23, 1, 1, 119, 1, 0, // Skip to: 8183 -/* 7808 */ MCD_OPC_Decode, 176, 23, 181, 2, // Opcode: t2SMLSLDX -/* 7813 */ MCD_OPC_FilterValue, 3, 109, 1, 0, // Skip to: 8183 -/* 7818 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 7821 */ MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 7957 -/* 7826 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... -/* 7829 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 7851 -/* 7834 */ MCD_OPC_CheckPredicate, 38, 88, 1, 0, // Skip to: 8183 -/* 7839 */ MCD_OPC_CheckField, 12, 4, 15, 81, 1, 0, // Skip to: 8183 -/* 7846 */ MCD_OPC_Decode, 135, 23, 239, 1, // Opcode: t2RORrr -/* 7851 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 7880 -/* 7856 */ MCD_OPC_CheckPredicate, 45, 66, 1, 0, // Skip to: 8183 -/* 7861 */ MCD_OPC_CheckField, 20, 1, 0, 59, 1, 0, // Skip to: 8183 -/* 7868 */ MCD_OPC_CheckField, 12, 4, 15, 52, 1, 0, // Skip to: 8183 -/* 7875 */ MCD_OPC_Decode, 200, 23, 170, 2, // Opcode: t2SSAX -/* 7880 */ MCD_OPC_FilterValue, 6, 50, 0, 0, // Skip to: 7935 -/* 7885 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 7888 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7903 -/* 7893 */ MCD_OPC_CheckPredicate, 45, 29, 1, 0, // Skip to: 8183 -/* 7898 */ MCD_OPC_Decode, 179, 23, 175, 2, // Opcode: t2SMMLS -/* 7903 */ MCD_OPC_FilterValue, 1, 19, 1, 0, // Skip to: 8183 -/* 7908 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7925 -/* 7913 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7925 -/* 7920 */ MCD_OPC_Decode, 172, 24, 170, 2, // Opcode: t2USAD8 -/* 7925 */ MCD_OPC_CheckPredicate, 45, 253, 0, 0, // Skip to: 8183 -/* 7930 */ MCD_OPC_Decode, 173, 24, 175, 2, // Opcode: t2USADA8 -/* 7935 */ MCD_OPC_FilterValue, 7, 243, 0, 0, // Skip to: 8183 -/* 7940 */ MCD_OPC_CheckPredicate, 38, 238, 0, 0, // Skip to: 8183 -/* 7945 */ MCD_OPC_CheckField, 20, 1, 0, 231, 0, 0, // Skip to: 8183 -/* 7952 */ MCD_OPC_Decode, 164, 24, 181, 2, // Opcode: t2UMLAL -/* 7957 */ MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 8016 -/* 7962 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... -/* 7965 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 7994 -/* 7970 */ MCD_OPC_CheckPredicate, 45, 208, 0, 0, // Skip to: 8183 -/* 7975 */ MCD_OPC_CheckField, 20, 1, 0, 201, 0, 0, // Skip to: 8183 -/* 7982 */ MCD_OPC_CheckField, 12, 4, 15, 194, 0, 0, // Skip to: 8183 -/* 7989 */ MCD_OPC_Decode, 250, 22, 170, 2, // Opcode: t2QSAX -/* 7994 */ MCD_OPC_FilterValue, 6, 184, 0, 0, // Skip to: 8183 -/* 7999 */ MCD_OPC_CheckPredicate, 45, 179, 0, 0, // Skip to: 8183 -/* 8004 */ MCD_OPC_CheckField, 20, 1, 0, 172, 0, 0, // Skip to: 8183 -/* 8011 */ MCD_OPC_Decode, 180, 23, 175, 2, // Opcode: t2SMMLSR -/* 8016 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 8052 -/* 8021 */ MCD_OPC_CheckPredicate, 45, 157, 0, 0, // Skip to: 8183 -/* 8026 */ MCD_OPC_CheckField, 23, 4, 5, 150, 0, 0, // Skip to: 8183 -/* 8033 */ MCD_OPC_CheckField, 20, 1, 0, 143, 0, 0, // Skip to: 8183 -/* 8040 */ MCD_OPC_CheckField, 12, 4, 15, 136, 0, 0, // Skip to: 8183 -/* 8047 */ MCD_OPC_Decode, 154, 23, 170, 2, // Opcode: t2SHSAX -/* 8052 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 8088 -/* 8057 */ MCD_OPC_CheckPredicate, 45, 121, 0, 0, // Skip to: 8183 -/* 8062 */ MCD_OPC_CheckField, 23, 4, 5, 114, 0, 0, // Skip to: 8183 -/* 8069 */ MCD_OPC_CheckField, 20, 1, 0, 107, 0, 0, // Skip to: 8183 -/* 8076 */ MCD_OPC_CheckField, 12, 4, 15, 100, 0, 0, // Skip to: 8183 -/* 8083 */ MCD_OPC_Decode, 176, 24, 170, 2, // Opcode: t2USAX -/* 8088 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 8124 -/* 8093 */ MCD_OPC_CheckPredicate, 45, 85, 0, 0, // Skip to: 8183 -/* 8098 */ MCD_OPC_CheckField, 23, 4, 5, 78, 0, 0, // Skip to: 8183 -/* 8105 */ MCD_OPC_CheckField, 20, 1, 0, 71, 0, 0, // Skip to: 8183 -/* 8112 */ MCD_OPC_CheckField, 12, 4, 15, 64, 0, 0, // Skip to: 8183 -/* 8119 */ MCD_OPC_Decode, 169, 24, 170, 2, // Opcode: t2UQSAX -/* 8124 */ MCD_OPC_FilterValue, 6, 54, 0, 0, // Skip to: 8183 -/* 8129 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... -/* 8132 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 8161 -/* 8137 */ MCD_OPC_CheckPredicate, 45, 41, 0, 0, // Skip to: 8183 -/* 8142 */ MCD_OPC_CheckField, 20, 1, 0, 34, 0, 0, // Skip to: 8183 -/* 8149 */ MCD_OPC_CheckField, 12, 4, 15, 27, 0, 0, // Skip to: 8183 -/* 8156 */ MCD_OPC_Decode, 160, 24, 170, 2, // Opcode: t2UHSAX -/* 8161 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 8183 -/* 8166 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 8183 -/* 8171 */ MCD_OPC_CheckField, 20, 1, 0, 5, 0, 0, // Skip to: 8183 -/* 8178 */ MCD_OPC_Decode, 163, 24, 181, 2, // Opcode: t2UMAAL -/* 8183 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 3 */ MCD_OPC_FilterValue, + 29, + 41, + 9, + 0, // Skip to: 2353 + /* 8 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 11, + 2, + 0, // Skip to: 539 + /* 16 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 73 + /* 24 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 27 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 50 + /* 32 */ MCD_OPC_CheckPredicate, + 46, + 199, + 34, + 0, // Skip to: 8940 + /* 37 */ MCD_OPC_CheckField, + 5, + 15, + 128, + 220, + 1, + 190, + 34, + 0, // Skip to: 8940 + /* 46 */ MCD_OPC_Decode, + 225, + 32, + 83, // Opcode: t2SRSDB + /* 50 */ MCD_OPC_FilterValue, + 1, + 181, + 34, + 0, // Skip to: 8940 + /* 55 */ MCD_OPC_CheckPredicate, + 46, + 176, + 34, + 0, // Skip to: 8940 + /* 60 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 128, + 3, + 167, + 34, + 0, // Skip to: 8940 + /* 69 */ MCD_OPC_Decode, + 160, + 32, + 81, // Opcode: t2RFEDB + /* 73 */ MCD_OPC_FilterValue, + 1, + 71, + 0, + 0, // Skip to: 149 + /* 78 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 81 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 110 + /* 86 */ MCD_OPC_CheckPredicate, + 45, + 145, + 34, + 0, // Skip to: 8940 + /* 91 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 138, + 34, + 0, // Skip to: 8940 + /* 98 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 131, + 34, + 0, // Skip to: 8940 + /* 105 */ MCD_OPC_Decode, + 131, + 33, + 210, + 2, // Opcode: t2STMIA + /* 110 */ MCD_OPC_FilterValue, + 1, + 121, + 34, + 0, // Skip to: 8940 + /* 115 */ MCD_OPC_CheckPredicate, + 47, + 19, + 0, + 0, // Skip to: 139 + /* 120 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 12, + 0, + 0, // Skip to: 139 + /* 127 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 5, + 0, + 0, // Skip to: 139 + /* 134 */ MCD_OPC_Decode, + 244, + 30, + 211, + 2, // Opcode: t2CLRM + /* 139 */ MCD_OPC_CheckPredicate, + 45, + 92, + 34, + 0, // Skip to: 8940 + /* 144 */ MCD_OPC_Decode, + 178, + 31, + 212, + 2, // Opcode: t2LDMIA + /* 149 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 201 + /* 154 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 157 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 186 + /* 162 */ MCD_OPC_CheckPredicate, + 45, + 69, + 34, + 0, // Skip to: 8940 + /* 167 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 62, + 34, + 0, // Skip to: 8940 + /* 174 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 55, + 34, + 0, // Skip to: 8940 + /* 181 */ MCD_OPC_Decode, + 129, + 33, + 210, + 2, // Opcode: t2STMDB + /* 186 */ MCD_OPC_FilterValue, + 1, + 45, + 34, + 0, // Skip to: 8940 + /* 191 */ MCD_OPC_CheckPredicate, + 45, + 40, + 34, + 0, // Skip to: 8940 + /* 196 */ MCD_OPC_Decode, + 176, + 31, + 212, + 2, // Opcode: t2LDMDB + /* 201 */ MCD_OPC_FilterValue, + 3, + 49, + 0, + 0, // Skip to: 255 + /* 206 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 209 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 232 + /* 214 */ MCD_OPC_CheckPredicate, + 46, + 17, + 34, + 0, // Skip to: 8940 + /* 219 */ MCD_OPC_CheckField, + 5, + 15, + 128, + 220, + 1, + 8, + 34, + 0, // Skip to: 8940 + /* 228 */ MCD_OPC_Decode, + 227, + 32, + 83, // Opcode: t2SRSIA + /* 232 */ MCD_OPC_FilterValue, + 1, + 255, + 33, + 0, // Skip to: 8940 + /* 237 */ MCD_OPC_CheckPredicate, + 46, + 250, + 33, + 0, // Skip to: 8940 + /* 242 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 128, + 3, + 241, + 33, + 0, // Skip to: 8940 + /* 251 */ MCD_OPC_Decode, + 162, + 32, + 81, // Opcode: t2RFEIA + /* 255 */ MCD_OPC_FilterValue, + 4, + 93, + 0, + 0, // Skip to: 353 + /* 260 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 285 + /* 265 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 13, + 0, + 0, // Skip to: 285 + /* 272 */ MCD_OPC_CheckField, + 4, + 11, + 240, + 1, + 5, + 0, + 0, // Skip to: 285 + /* 280 */ MCD_OPC_Decode, + 178, + 33, + 213, + 2, // Opcode: t2TSTrr + /* 285 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 309 + /* 290 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 309 + /* 297 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 309 + /* 304 */ MCD_OPC_Decode, + 179, + 33, + 214, + 2, // Opcode: t2TSTrs + /* 309 */ MCD_OPC_CheckPredicate, + 45, + 24, + 0, + 0, // Skip to: 338 + /* 314 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 17, + 0, + 0, // Skip to: 338 + /* 321 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 10, + 0, + 0, // Skip to: 338 + /* 328 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 333 */ MCD_OPC_Decode, + 224, + 30, + 215, + 2, // Opcode: t2ANDrr + /* 338 */ MCD_OPC_CheckPredicate, + 45, + 149, + 33, + 0, // Skip to: 8940 + /* 343 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 348 */ MCD_OPC_Decode, + 225, + 30, + 216, + 2, // Opcode: t2ANDrs + /* 353 */ MCD_OPC_FilterValue, + 5, + 93, + 0, + 0, // Skip to: 451 + /* 358 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 383 + /* 363 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 13, + 0, + 0, // Skip to: 383 + /* 370 */ MCD_OPC_CheckField, + 4, + 11, + 240, + 1, + 5, + 0, + 0, // Skip to: 383 + /* 378 */ MCD_OPC_Decode, + 174, + 33, + 213, + 2, // Opcode: t2TEQrr + /* 383 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 407 + /* 388 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 407 + /* 395 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 407 + /* 402 */ MCD_OPC_Decode, + 175, + 33, + 214, + 2, // Opcode: t2TEQrs + /* 407 */ MCD_OPC_CheckPredicate, + 45, + 24, + 0, + 0, // Skip to: 436 + /* 412 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 17, + 0, + 0, // Skip to: 436 + /* 419 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 10, + 0, + 0, // Skip to: 436 + /* 426 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 431 */ MCD_OPC_Decode, + 145, + 31, + 215, + 2, // Opcode: t2EORrr + /* 436 */ MCD_OPC_CheckPredicate, + 45, + 51, + 33, + 0, // Skip to: 8940 + /* 441 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 446 */ MCD_OPC_Decode, + 146, + 31, + 216, + 2, // Opcode: t2EORrs + /* 451 */ MCD_OPC_FilterValue, + 6, + 36, + 33, + 0, // Skip to: 8940 + /* 456 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 481 + /* 461 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 13, + 0, + 0, // Skip to: 481 + /* 468 */ MCD_OPC_CheckField, + 4, + 11, + 240, + 1, + 5, + 0, + 0, // Skip to: 481 + /* 476 */ MCD_OPC_Decode, + 247, + 30, + 217, + 2, // Opcode: t2CMNzrr + /* 481 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 505 + /* 486 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 505 + /* 493 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 505 + /* 500 */ MCD_OPC_Decode, + 248, + 30, + 218, + 2, // Opcode: t2CMNzrs + /* 505 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 529 + /* 510 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 529 + /* 517 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 529 + /* 524 */ MCD_OPC_Decode, + 218, + 30, + 219, + 2, // Opcode: t2ADDrr + /* 529 */ MCD_OPC_CheckPredicate, + 45, + 214, + 32, + 0, // Skip to: 8940 + /* 534 */ MCD_OPC_Decode, + 219, + 30, + 220, + 2, // Opcode: t2ADDrs + /* 539 */ MCD_OPC_FilterValue, + 1, + 96, + 1, + 0, // Skip to: 896 + /* 544 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 547 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 601 + /* 552 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 555 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 578 + /* 560 */ MCD_OPC_CheckPredicate, + 46, + 183, + 32, + 0, // Skip to: 8940 + /* 565 */ MCD_OPC_CheckField, + 5, + 15, + 128, + 220, + 1, + 174, + 32, + 0, // Skip to: 8940 + /* 574 */ MCD_OPC_Decode, + 226, + 32, + 83, // Opcode: t2SRSDB_UPD + /* 578 */ MCD_OPC_FilterValue, + 1, + 165, + 32, + 0, // Skip to: 8940 + /* 583 */ MCD_OPC_CheckPredicate, + 46, + 160, + 32, + 0, // Skip to: 8940 + /* 588 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 128, + 3, + 151, + 32, + 0, // Skip to: 8940 + /* 597 */ MCD_OPC_Decode, + 161, + 32, + 81, // Opcode: t2RFEDBW + /* 601 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 653 + /* 606 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 609 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 638 + /* 614 */ MCD_OPC_CheckPredicate, + 45, + 129, + 32, + 0, // Skip to: 8940 + /* 619 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 122, + 32, + 0, // Skip to: 8940 + /* 626 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 115, + 32, + 0, // Skip to: 8940 + /* 633 */ MCD_OPC_Decode, + 132, + 33, + 221, + 2, // Opcode: t2STMIA_UPD + /* 638 */ MCD_OPC_FilterValue, + 1, + 105, + 32, + 0, // Skip to: 8940 + /* 643 */ MCD_OPC_CheckPredicate, + 45, + 100, + 32, + 0, // Skip to: 8940 + /* 648 */ MCD_OPC_Decode, + 179, + 31, + 222, + 2, // Opcode: t2LDMIA_UPD + /* 653 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 705 + /* 658 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 661 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 690 + /* 666 */ MCD_OPC_CheckPredicate, + 45, + 77, + 32, + 0, // Skip to: 8940 + /* 671 */ MCD_OPC_CheckField, + 15, + 1, + 0, + 70, + 32, + 0, // Skip to: 8940 + /* 678 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 63, + 32, + 0, // Skip to: 8940 + /* 685 */ MCD_OPC_Decode, + 130, + 33, + 221, + 2, // Opcode: t2STMDB_UPD + /* 690 */ MCD_OPC_FilterValue, + 1, + 53, + 32, + 0, // Skip to: 8940 + /* 695 */ MCD_OPC_CheckPredicate, + 45, + 48, + 32, + 0, // Skip to: 8940 + /* 700 */ MCD_OPC_Decode, + 177, + 31, + 222, + 2, // Opcode: t2LDMDB_UPD + /* 705 */ MCD_OPC_FilterValue, + 3, + 49, + 0, + 0, // Skip to: 759 + /* 710 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 713 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 736 + /* 718 */ MCD_OPC_CheckPredicate, + 46, + 25, + 32, + 0, // Skip to: 8940 + /* 723 */ MCD_OPC_CheckField, + 5, + 15, + 128, + 220, + 1, + 16, + 32, + 0, // Skip to: 8940 + /* 732 */ MCD_OPC_Decode, + 228, + 32, + 83, // Opcode: t2SRSIA_UPD + /* 736 */ MCD_OPC_FilterValue, + 1, + 7, + 32, + 0, // Skip to: 8940 + /* 741 */ MCD_OPC_CheckPredicate, + 46, + 2, + 32, + 0, // Skip to: 8940 + /* 746 */ MCD_OPC_CheckField, + 0, + 16, + 128, + 128, + 3, + 249, + 31, + 0, // Skip to: 8940 + /* 755 */ MCD_OPC_Decode, + 163, + 32, + 81, // Opcode: t2RFEIAW + /* 759 */ MCD_OPC_FilterValue, + 4, + 44, + 0, + 0, // Skip to: 808 + /* 764 */ MCD_OPC_CheckPredicate, + 45, + 24, + 0, + 0, // Skip to: 793 + /* 769 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 17, + 0, + 0, // Skip to: 793 + /* 776 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 10, + 0, + 0, // Skip to: 793 + /* 783 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 788 */ MCD_OPC_Decode, + 237, + 30, + 215, + 2, // Opcode: t2BICrr + /* 793 */ MCD_OPC_CheckPredicate, + 45, + 206, + 31, + 0, // Skip to: 8940 + /* 798 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 803 */ MCD_OPC_Decode, + 238, + 30, + 216, + 2, // Opcode: t2BICrs + /* 808 */ MCD_OPC_FilterValue, + 7, + 191, + 31, + 0, // Skip to: 8940 + /* 813 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 838 + /* 818 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 13, + 0, + 0, // Skip to: 838 + /* 825 */ MCD_OPC_CheckField, + 4, + 11, + 240, + 1, + 5, + 0, + 0, // Skip to: 838 + /* 833 */ MCD_OPC_Decode, + 250, + 30, + 217, + 2, // Opcode: t2CMPrr + /* 838 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 862 + /* 843 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 862 + /* 850 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 862 + /* 857 */ MCD_OPC_Decode, + 251, + 30, + 218, + 2, // Opcode: t2CMPrs + /* 862 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 886 + /* 867 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 886 + /* 874 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 886 + /* 881 */ MCD_OPC_Decode, + 161, + 33, + 219, + 2, // Opcode: t2SUBrr + /* 886 */ MCD_OPC_CheckPredicate, + 45, + 113, + 31, + 0, // Skip to: 8940 + /* 891 */ MCD_OPC_Decode, + 162, + 33, + 220, + 2, // Opcode: t2SUBrs + /* 896 */ MCD_OPC_FilterValue, + 2, + 179, + 4, + 0, // Skip to: 2104 + /* 901 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 904 */ MCD_OPC_FilterValue, + 0, + 212, + 2, + 0, // Skip to: 1633 + /* 909 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 912 */ MCD_OPC_FilterValue, + 0, + 100, + 1, + 0, // Skip to: 1273 + /* 917 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 920 */ MCD_OPC_FilterValue, + 0, + 113, + 0, + 0, // Skip to: 1038 + /* 925 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 928 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 953 + /* 933 */ MCD_OPC_CheckPredicate, + 36, + 90, + 0, + 0, // Skip to: 1028 + /* 938 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 83, + 0, + 0, // Skip to: 1028 + /* 945 */ MCD_OPC_SoftFail, + 63, + 0, + /* 948 */ MCD_OPC_Decode, + 180, + 33, + 223, + 2, // Opcode: t2TT + /* 953 */ MCD_OPC_FilterValue, + 1, + 20, + 0, + 0, // Skip to: 978 + /* 958 */ MCD_OPC_CheckPredicate, + 36, + 65, + 0, + 0, // Skip to: 1028 + /* 963 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 58, + 0, + 0, // Skip to: 1028 + /* 970 */ MCD_OPC_SoftFail, + 63, + 0, + /* 973 */ MCD_OPC_Decode, + 183, + 33, + 223, + 2, // Opcode: t2TTT + /* 978 */ MCD_OPC_FilterValue, + 2, + 20, + 0, + 0, // Skip to: 1003 + /* 983 */ MCD_OPC_CheckPredicate, + 36, + 40, + 0, + 0, // Skip to: 1028 + /* 988 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 33, + 0, + 0, // Skip to: 1028 + /* 995 */ MCD_OPC_SoftFail, + 63, + 0, + /* 998 */ MCD_OPC_Decode, + 181, + 33, + 223, + 2, // Opcode: t2TTA + /* 1003 */ MCD_OPC_FilterValue, + 3, + 20, + 0, + 0, // Skip to: 1028 + /* 1008 */ MCD_OPC_CheckPredicate, + 36, + 15, + 0, + 0, // Skip to: 1028 + /* 1013 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 8, + 0, + 0, // Skip to: 1028 + /* 1020 */ MCD_OPC_SoftFail, + 63, + 0, + /* 1023 */ MCD_OPC_Decode, + 182, + 33, + 223, + 2, // Opcode: t2TTAT + /* 1028 */ MCD_OPC_CheckPredicate, + 39, + 227, + 30, + 0, // Skip to: 8940 + /* 1033 */ MCD_OPC_Decode, + 142, + 33, + 224, + 2, // Opcode: t2STREX + /* 1038 */ MCD_OPC_FilterValue, + 1, + 217, + 30, + 0, // Skip to: 8940 + /* 1043 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 1046 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 1068 + /* 1051 */ MCD_OPC_CheckPredicate, + 39, + 204, + 30, + 0, // Skip to: 8940 + /* 1056 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 197, + 30, + 0, // Skip to: 8940 + /* 1063 */ MCD_OPC_Decode, + 143, + 33, + 225, + 2, // Opcode: t2STREXB + /* 1068 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 1090 + /* 1073 */ MCD_OPC_CheckPredicate, + 39, + 182, + 30, + 0, // Skip to: 8940 + /* 1078 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 175, + 30, + 0, // Skip to: 8940 + /* 1085 */ MCD_OPC_Decode, + 145, + 33, + 225, + 2, // Opcode: t2STREXH + /* 1090 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1105 + /* 1095 */ MCD_OPC_CheckPredicate, + 46, + 160, + 30, + 0, // Skip to: 8940 + /* 1100 */ MCD_OPC_Decode, + 144, + 33, + 226, + 2, // Opcode: t2STREXD + /* 1105 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 1134 + /* 1110 */ MCD_OPC_CheckPredicate, + 48, + 145, + 30, + 0, // Skip to: 8940 + /* 1115 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 138, + 30, + 0, // Skip to: 8940 + /* 1122 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 131, + 30, + 0, // Skip to: 8940 + /* 1129 */ MCD_OPC_Decode, + 251, + 32, + 227, + 2, // Opcode: t2STLB + /* 1134 */ MCD_OPC_FilterValue, + 9, + 24, + 0, + 0, // Skip to: 1163 + /* 1139 */ MCD_OPC_CheckPredicate, + 48, + 116, + 30, + 0, // Skip to: 8940 + /* 1144 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 109, + 30, + 0, // Skip to: 8940 + /* 1151 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 102, + 30, + 0, // Skip to: 8940 + /* 1158 */ MCD_OPC_Decode, + 128, + 33, + 227, + 2, // Opcode: t2STLH + /* 1163 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 1192 + /* 1168 */ MCD_OPC_CheckPredicate, + 48, + 87, + 30, + 0, // Skip to: 8940 + /* 1173 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 80, + 30, + 0, // Skip to: 8940 + /* 1180 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 73, + 30, + 0, // Skip to: 8940 + /* 1187 */ MCD_OPC_Decode, + 250, + 32, + 227, + 2, // Opcode: t2STL + /* 1192 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 1214 + /* 1197 */ MCD_OPC_CheckPredicate, + 49, + 58, + 30, + 0, // Skip to: 8940 + /* 1202 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 51, + 30, + 0, // Skip to: 8940 + /* 1209 */ MCD_OPC_Decode, + 253, + 32, + 225, + 2, // Opcode: t2STLEXB + /* 1214 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 1236 + /* 1219 */ MCD_OPC_CheckPredicate, + 49, + 36, + 30, + 0, // Skip to: 8940 + /* 1224 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 29, + 30, + 0, // Skip to: 8940 + /* 1231 */ MCD_OPC_Decode, + 255, + 32, + 225, + 2, // Opcode: t2STLEXH + /* 1236 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 1258 + /* 1241 */ MCD_OPC_CheckPredicate, + 49, + 14, + 30, + 0, // Skip to: 8940 + /* 1246 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 7, + 30, + 0, // Skip to: 8940 + /* 1253 */ MCD_OPC_Decode, + 252, + 32, + 225, + 2, // Opcode: t2STLEX + /* 1258 */ MCD_OPC_FilterValue, + 15, + 253, + 29, + 0, // Skip to: 8940 + /* 1263 */ MCD_OPC_CheckPredicate, + 50, + 248, + 29, + 0, // Skip to: 8940 + /* 1268 */ MCD_OPC_Decode, + 254, + 32, + 226, + 2, // Opcode: t2STLEXD + /* 1273 */ MCD_OPC_FilterValue, + 1, + 238, + 29, + 0, // Skip to: 8940 + /* 1278 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1281 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1303 + /* 1286 */ MCD_OPC_CheckPredicate, + 39, + 225, + 29, + 0, // Skip to: 8940 + /* 1291 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 218, + 29, + 0, // Skip to: 8940 + /* 1298 */ MCD_OPC_Decode, + 190, + 31, + 228, + 2, // Opcode: t2LDREX + /* 1303 */ MCD_OPC_FilterValue, + 1, + 208, + 29, + 0, // Skip to: 8940 + /* 1308 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 1311 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 1334 + /* 1316 */ MCD_OPC_CheckPredicate, + 45, + 195, + 29, + 0, // Skip to: 8940 + /* 1321 */ MCD_OPC_CheckField, + 8, + 8, + 240, + 1, + 187, + 29, + 0, // Skip to: 8940 + /* 1329 */ MCD_OPC_Decode, + 171, + 33, + 229, + 2, // Opcode: t2TBB + /* 1334 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 1357 + /* 1339 */ MCD_OPC_CheckPredicate, + 45, + 172, + 29, + 0, // Skip to: 8940 + /* 1344 */ MCD_OPC_CheckField, + 8, + 8, + 240, + 1, + 164, + 29, + 0, // Skip to: 8940 + /* 1352 */ MCD_OPC_Decode, + 172, + 33, + 229, + 2, // Opcode: t2TBH + /* 1357 */ MCD_OPC_FilterValue, + 4, + 24, + 0, + 0, // Skip to: 1386 + /* 1362 */ MCD_OPC_CheckPredicate, + 39, + 149, + 29, + 0, // Skip to: 8940 + /* 1367 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 142, + 29, + 0, // Skip to: 8940 + /* 1374 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 135, + 29, + 0, // Skip to: 8940 + /* 1381 */ MCD_OPC_Decode, + 191, + 31, + 227, + 2, // Opcode: t2LDREXB + /* 1386 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 1415 + /* 1391 */ MCD_OPC_CheckPredicate, + 39, + 120, + 29, + 0, // Skip to: 8940 + /* 1396 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 113, + 29, + 0, // Skip to: 8940 + /* 1403 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 106, + 29, + 0, // Skip to: 8940 + /* 1410 */ MCD_OPC_Decode, + 193, + 31, + 227, + 2, // Opcode: t2LDREXH + /* 1415 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 1437 + /* 1420 */ MCD_OPC_CheckPredicate, + 46, + 91, + 29, + 0, // Skip to: 8940 + /* 1425 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 84, + 29, + 0, // Skip to: 8940 + /* 1432 */ MCD_OPC_Decode, + 192, + 31, + 230, + 2, // Opcode: t2LDREXD + /* 1437 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 1466 + /* 1442 */ MCD_OPC_CheckPredicate, + 48, + 69, + 29, + 0, // Skip to: 8940 + /* 1447 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 62, + 29, + 0, // Skip to: 8940 + /* 1454 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 55, + 29, + 0, // Skip to: 8940 + /* 1461 */ MCD_OPC_Decode, + 154, + 31, + 227, + 2, // Opcode: t2LDAB + /* 1466 */ MCD_OPC_FilterValue, + 9, + 24, + 0, + 0, // Skip to: 1495 + /* 1471 */ MCD_OPC_CheckPredicate, + 48, + 40, + 29, + 0, // Skip to: 8940 + /* 1476 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 33, + 29, + 0, // Skip to: 8940 + /* 1483 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 26, + 29, + 0, // Skip to: 8940 + /* 1490 */ MCD_OPC_Decode, + 159, + 31, + 227, + 2, // Opcode: t2LDAH + /* 1495 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 1524 + /* 1500 */ MCD_OPC_CheckPredicate, + 48, + 11, + 29, + 0, // Skip to: 8940 + /* 1505 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 4, + 29, + 0, // Skip to: 8940 + /* 1512 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 253, + 28, + 0, // Skip to: 8940 + /* 1519 */ MCD_OPC_Decode, + 153, + 31, + 227, + 2, // Opcode: t2LDA + /* 1524 */ MCD_OPC_FilterValue, + 12, + 24, + 0, + 0, // Skip to: 1553 + /* 1529 */ MCD_OPC_CheckPredicate, + 49, + 238, + 28, + 0, // Skip to: 8940 + /* 1534 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 231, + 28, + 0, // Skip to: 8940 + /* 1541 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 224, + 28, + 0, // Skip to: 8940 + /* 1548 */ MCD_OPC_Decode, + 156, + 31, + 227, + 2, // Opcode: t2LDAEXB + /* 1553 */ MCD_OPC_FilterValue, + 13, + 24, + 0, + 0, // Skip to: 1582 + /* 1558 */ MCD_OPC_CheckPredicate, + 49, + 209, + 28, + 0, // Skip to: 8940 + /* 1563 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 202, + 28, + 0, // Skip to: 8940 + /* 1570 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 195, + 28, + 0, // Skip to: 8940 + /* 1577 */ MCD_OPC_Decode, + 158, + 31, + 227, + 2, // Opcode: t2LDAEXH + /* 1582 */ MCD_OPC_FilterValue, + 14, + 24, + 0, + 0, // Skip to: 1611 + /* 1587 */ MCD_OPC_CheckPredicate, + 49, + 180, + 28, + 0, // Skip to: 8940 + /* 1592 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 173, + 28, + 0, // Skip to: 8940 + /* 1599 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 166, + 28, + 0, // Skip to: 8940 + /* 1606 */ MCD_OPC_Decode, + 155, + 31, + 227, + 2, // Opcode: t2LDAEX + /* 1611 */ MCD_OPC_FilterValue, + 15, + 156, + 28, + 0, // Skip to: 8940 + /* 1616 */ MCD_OPC_CheckPredicate, + 50, + 151, + 28, + 0, // Skip to: 8940 + /* 1621 */ MCD_OPC_CheckField, + 0, + 4, + 15, + 144, + 28, + 0, // Skip to: 8940 + /* 1628 */ MCD_OPC_Decode, + 157, + 31, + 230, + 2, // Opcode: t2LDAEXD + /* 1633 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 1671 + /* 1638 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 1641 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1656 + /* 1646 */ MCD_OPC_CheckPredicate, + 45, + 121, + 28, + 0, // Skip to: 8940 + /* 1651 */ MCD_OPC_Decode, + 141, + 33, + 231, + 2, // Opcode: t2STRDi8 + /* 1656 */ MCD_OPC_FilterValue, + 1, + 111, + 28, + 0, // Skip to: 8940 + /* 1661 */ MCD_OPC_CheckPredicate, + 45, + 106, + 28, + 0, // Skip to: 8940 + /* 1666 */ MCD_OPC_Decode, + 189, + 31, + 231, + 2, // Opcode: t2LDRDi8 + /* 1671 */ MCD_OPC_FilterValue, + 2, + 86, + 1, + 0, // Skip to: 2018 + /* 1676 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1679 */ MCD_OPC_FilterValue, + 0, + 26, + 1, + 0, // Skip to: 1966 + /* 1684 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 1687 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 1727 + /* 1692 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 1695 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 1761 + /* 1700 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 1717 + /* 1705 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 1717 + /* 1712 */ MCD_OPC_Decode, + 237, + 31, + 232, + 2, // Opcode: t2MOVr + /* 1717 */ MCD_OPC_CheckPredicate, + 45, + 39, + 0, + 0, // Skip to: 1761 + /* 1722 */ MCD_OPC_Decode, + 131, + 32, + 215, + 2, // Opcode: t2ORRrr + /* 1727 */ MCD_OPC_FilterValue, + 3, + 29, + 0, + 0, // Skip to: 1761 + /* 1732 */ MCD_OPC_CheckPredicate, + 45, + 24, + 0, + 0, // Skip to: 1761 + /* 1737 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 17, + 0, + 0, // Skip to: 1761 + /* 1744 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 10, + 0, + 0, // Skip to: 1761 + /* 1751 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 1756 */ MCD_OPC_Decode, + 166, + 32, + 233, + 2, // Opcode: t2RRX + /* 1761 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 1764 */ MCD_OPC_FilterValue, + 0, + 101, + 0, + 0, // Skip to: 1870 + /* 1769 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 1772 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1794 + /* 1777 */ MCD_OPC_CheckPredicate, + 45, + 78, + 0, + 0, // Skip to: 1860 + /* 1782 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 71, + 0, + 0, // Skip to: 1860 + /* 1789 */ MCD_OPC_Decode, + 224, + 31, + 234, + 2, // Opcode: t2LSLri + /* 1794 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 1816 + /* 1799 */ MCD_OPC_CheckPredicate, + 45, + 56, + 0, + 0, // Skip to: 1860 + /* 1804 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 49, + 0, + 0, // Skip to: 1860 + /* 1811 */ MCD_OPC_Decode, + 226, + 31, + 234, + 2, // Opcode: t2LSRri + /* 1816 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 1838 + /* 1821 */ MCD_OPC_CheckPredicate, + 45, + 34, + 0, + 0, // Skip to: 1860 + /* 1826 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 27, + 0, + 0, // Skip to: 1860 + /* 1833 */ MCD_OPC_Decode, + 226, + 30, + 234, + 2, // Opcode: t2ASRri + /* 1838 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 1860 + /* 1843 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 1860 + /* 1848 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 1860 + /* 1855 */ MCD_OPC_Decode, + 164, + 32, + 234, + 2, // Opcode: t2RORri + /* 1860 */ MCD_OPC_CheckPredicate, + 45, + 163, + 27, + 0, // Skip to: 8940 + /* 1865 */ MCD_OPC_Decode, + 132, + 32, + 216, + 2, // Opcode: t2ORRrs + /* 1870 */ MCD_OPC_FilterValue, + 1, + 153, + 27, + 0, // Skip to: 8940 + /* 1875 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 1878 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1900 + /* 1883 */ MCD_OPC_CheckPredicate, + 47, + 140, + 27, + 0, // Skip to: 8940 + /* 1888 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 133, + 27, + 0, // Skip to: 8940 + /* 1895 */ MCD_OPC_Decode, + 133, + 31, + 235, + 2, // Opcode: t2CSEL + /* 1900 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 1922 + /* 1905 */ MCD_OPC_CheckPredicate, + 47, + 118, + 27, + 0, // Skip to: 8940 + /* 1910 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 111, + 27, + 0, // Skip to: 8940 + /* 1917 */ MCD_OPC_Decode, + 134, + 31, + 235, + 2, // Opcode: t2CSINC + /* 1922 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 1944 + /* 1927 */ MCD_OPC_CheckPredicate, + 47, + 96, + 27, + 0, // Skip to: 8940 + /* 1932 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 89, + 27, + 0, // Skip to: 8940 + /* 1939 */ MCD_OPC_Decode, + 135, + 31, + 235, + 2, // Opcode: t2CSINV + /* 1944 */ MCD_OPC_FilterValue, + 3, + 79, + 27, + 0, // Skip to: 8940 + /* 1949 */ MCD_OPC_CheckPredicate, + 47, + 74, + 27, + 0, // Skip to: 8940 + /* 1954 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 67, + 27, + 0, // Skip to: 8940 + /* 1961 */ MCD_OPC_Decode, + 136, + 31, + 235, + 2, // Opcode: t2CSNEG + /* 1966 */ MCD_OPC_FilterValue, + 1, + 57, + 27, + 0, // Skip to: 8940 + /* 1971 */ MCD_OPC_ExtractField, + 4, + 2, // Inst{5-4} ... + /* 1974 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1996 + /* 1979 */ MCD_OPC_CheckPredicate, + 51, + 44, + 27, + 0, // Skip to: 8940 + /* 1984 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 37, + 27, + 0, // Skip to: 8940 + /* 1991 */ MCD_OPC_Decode, + 133, + 32, + 236, + 2, // Opcode: t2PKHBT + /* 1996 */ MCD_OPC_FilterValue, + 2, + 27, + 27, + 0, // Skip to: 8940 + /* 2001 */ MCD_OPC_CheckPredicate, + 51, + 22, + 27, + 0, // Skip to: 8940 + /* 2006 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 15, + 27, + 0, // Skip to: 8940 + /* 2013 */ MCD_OPC_Decode, + 134, + 32, + 236, + 2, // Opcode: t2PKHTB + /* 2018 */ MCD_OPC_FilterValue, + 3, + 5, + 27, + 0, // Skip to: 8940 + /* 2023 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 2026 */ MCD_OPC_FilterValue, + 0, + 34, + 0, + 0, // Skip to: 2065 + /* 2031 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2055 + /* 2036 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 2055 + /* 2043 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 2055 + /* 2050 */ MCD_OPC_Decode, + 214, + 30, + 215, + 2, // Opcode: t2ADCrr + /* 2055 */ MCD_OPC_CheckPredicate, + 45, + 224, + 26, + 0, // Skip to: 8940 + /* 2060 */ MCD_OPC_Decode, + 215, + 30, + 216, + 2, // Opcode: t2ADCrs + /* 2065 */ MCD_OPC_FilterValue, + 1, + 214, + 26, + 0, // Skip to: 8940 + /* 2070 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2094 + /* 2075 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 2094 + /* 2082 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 2094 + /* 2089 */ MCD_OPC_Decode, + 168, + 32, + 215, + 2, // Opcode: t2RSBrr + /* 2094 */ MCD_OPC_CheckPredicate, + 45, + 185, + 26, + 0, // Skip to: 8940 + /* 2099 */ MCD_OPC_Decode, + 169, + 32, + 216, + 2, // Opcode: t2RSBrs + /* 2104 */ MCD_OPC_FilterValue, + 3, + 175, + 26, + 0, // Skip to: 8940 + /* 2109 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 2112 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 2150 + /* 2117 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2120 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2135 + /* 2125 */ MCD_OPC_CheckPredicate, + 45, + 154, + 26, + 0, // Skip to: 8940 + /* 2130 */ MCD_OPC_Decode, + 139, + 33, + 237, + 2, // Opcode: t2STRD_POST + /* 2135 */ MCD_OPC_FilterValue, + 1, + 144, + 26, + 0, // Skip to: 8940 + /* 2140 */ MCD_OPC_CheckPredicate, + 45, + 139, + 26, + 0, // Skip to: 8940 + /* 2145 */ MCD_OPC_Decode, + 187, + 31, + 238, + 2, // Opcode: t2LDRD_POST + /* 2150 */ MCD_OPC_FilterValue, + 1, + 58, + 0, + 0, // Skip to: 2213 + /* 2155 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2158 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2173 + /* 2163 */ MCD_OPC_CheckPredicate, + 45, + 116, + 26, + 0, // Skip to: 8940 + /* 2168 */ MCD_OPC_Decode, + 140, + 33, + 239, + 2, // Opcode: t2STRD_PRE + /* 2173 */ MCD_OPC_FilterValue, + 1, + 106, + 26, + 0, // Skip to: 8940 + /* 2178 */ MCD_OPC_CheckPredicate, + 52, + 20, + 0, + 0, // Skip to: 2203 + /* 2183 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 13, + 0, + 0, // Skip to: 2203 + /* 2190 */ MCD_OPC_CheckField, + 0, + 20, + 255, + 210, + 63, + 4, + 0, + 0, // Skip to: 2203 + /* 2199 */ MCD_OPC_Decode, + 181, + 32, + 51, // Opcode: t2SG + /* 2203 */ MCD_OPC_CheckPredicate, + 45, + 76, + 26, + 0, // Skip to: 8940 + /* 2208 */ MCD_OPC_Decode, + 188, + 31, + 240, + 2, // Opcode: t2LDRD_PRE + /* 2213 */ MCD_OPC_FilterValue, + 2, + 88, + 0, + 0, // Skip to: 2306 + /* 2218 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 2221 */ MCD_OPC_FilterValue, + 0, + 58, + 26, + 0, // Skip to: 8940 + /* 2226 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 2229 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 2274 + /* 2234 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 2237 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 2274 + /* 2242 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2259 + /* 2247 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 2259 + /* 2254 */ MCD_OPC_Decode, + 253, + 31, + 233, + 2, // Opcode: t2MVNr + /* 2259 */ MCD_OPC_CheckPredicate, + 45, + 10, + 0, + 0, // Skip to: 2274 + /* 2264 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 2269 */ MCD_OPC_Decode, + 128, + 32, + 215, + 2, // Opcode: t2ORNrr + /* 2274 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2291 + /* 2279 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 2291 + /* 2286 */ MCD_OPC_Decode, + 254, + 31, + 241, + 2, // Opcode: t2MVNs + /* 2291 */ MCD_OPC_CheckPredicate, + 45, + 244, + 25, + 0, // Skip to: 8940 + /* 2296 */ MCD_OPC_SoftFail, + 128, + 128, + 2 /* 0x8000 */, + 0, + /* 2301 */ MCD_OPC_Decode, + 129, + 32, + 216, + 2, // Opcode: t2ORNrs + /* 2306 */ MCD_OPC_FilterValue, + 3, + 229, + 25, + 0, // Skip to: 8940 + /* 2311 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 2314 */ MCD_OPC_FilterValue, + 0, + 221, + 25, + 0, // Skip to: 8940 + /* 2319 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2343 + /* 2324 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 12, + 0, + 0, // Skip to: 2343 + /* 2331 */ MCD_OPC_CheckField, + 4, + 4, + 0, + 5, + 0, + 0, // Skip to: 2343 + /* 2338 */ MCD_OPC_Decode, + 175, + 32, + 215, + 2, // Opcode: t2SBCrr + /* 2343 */ MCD_OPC_CheckPredicate, + 45, + 192, + 25, + 0, // Skip to: 8940 + /* 2348 */ MCD_OPC_Decode, + 176, + 32, + 216, + 2, // Opcode: t2SBCrs + /* 2353 */ MCD_OPC_FilterValue, + 30, + 225, + 7, + 0, // Skip to: 4375 + /* 2358 */ MCD_OPC_ExtractField, + 15, + 1, // Inst{15} ... + /* 2361 */ MCD_OPC_FilterValue, + 0, + 36, + 3, + 0, // Skip to: 3170 + /* 2366 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 2369 */ MCD_OPC_FilterValue, + 0, + 160, + 0, + 0, // Skip to: 2534 + /* 2374 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 2377 */ MCD_OPC_FilterValue, + 0, + 34, + 0, + 0, // Skip to: 2416 + /* 2382 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2406 + /* 2387 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 2406 + /* 2394 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 2406 + /* 2401 */ MCD_OPC_Decode, + 177, + 33, + 242, + 2, // Opcode: t2TSTri + /* 2406 */ MCD_OPC_CheckPredicate, + 45, + 129, + 25, + 0, // Skip to: 8940 + /* 2411 */ MCD_OPC_Decode, + 223, + 30, + 243, + 2, // Opcode: t2ANDri + /* 2416 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2431 + /* 2421 */ MCD_OPC_CheckPredicate, + 45, + 114, + 25, + 0, // Skip to: 8940 + /* 2426 */ MCD_OPC_Decode, + 236, + 30, + 243, + 2, // Opcode: t2BICri + /* 2431 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 2463 + /* 2436 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2453 + /* 2441 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 2453 + /* 2448 */ MCD_OPC_Decode, + 235, + 31, + 244, + 2, // Opcode: t2MOVi + /* 2453 */ MCD_OPC_CheckPredicate, + 45, + 82, + 25, + 0, // Skip to: 8940 + /* 2458 */ MCD_OPC_Decode, + 130, + 32, + 243, + 2, // Opcode: t2ORRri + /* 2463 */ MCD_OPC_FilterValue, + 3, + 27, + 0, + 0, // Skip to: 2495 + /* 2468 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2485 + /* 2473 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 2485 + /* 2480 */ MCD_OPC_Decode, + 252, + 31, + 244, + 2, // Opcode: t2MVNi + /* 2485 */ MCD_OPC_CheckPredicate, + 45, + 50, + 25, + 0, // Skip to: 8940 + /* 2490 */ MCD_OPC_Decode, + 255, + 31, + 243, + 2, // Opcode: t2ORNri + /* 2495 */ MCD_OPC_FilterValue, + 4, + 40, + 25, + 0, // Skip to: 8940 + /* 2500 */ MCD_OPC_CheckPredicate, + 45, + 19, + 0, + 0, // Skip to: 2524 + /* 2505 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 12, + 0, + 0, // Skip to: 2524 + /* 2512 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 5, + 0, + 0, // Skip to: 2524 + /* 2519 */ MCD_OPC_Decode, + 173, + 33, + 242, + 2, // Opcode: t2TEQri + /* 2524 */ MCD_OPC_CheckPredicate, + 45, + 11, + 25, + 0, // Skip to: 8940 + /* 2529 */ MCD_OPC_Decode, + 144, + 31, + 243, + 2, // Opcode: t2EORri + /* 2534 */ MCD_OPC_FilterValue, + 1, + 172, + 0, + 0, // Skip to: 2711 + /* 2539 */ MCD_OPC_ExtractField, + 21, + 3, // Inst{23-21} ... + /* 2542 */ MCD_OPC_FilterValue, + 0, + 57, + 0, + 0, // Skip to: 2604 + /* 2547 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 2550 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 2572 + /* 2555 */ MCD_OPC_CheckPredicate, + 45, + 34, + 0, + 0, // Skip to: 2594 + /* 2560 */ MCD_OPC_CheckField, + 16, + 4, + 13, + 27, + 0, + 0, // Skip to: 2594 + /* 2567 */ MCD_OPC_Decode, + 220, + 30, + 245, + 2, // Opcode: t2ADDspImm + /* 2572 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2594 + /* 2577 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2594 + /* 2582 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 2594 + /* 2589 */ MCD_OPC_Decode, + 246, + 30, + 246, + 2, // Opcode: t2CMNri + /* 2594 */ MCD_OPC_CheckPredicate, + 45, + 197, + 24, + 0, // Skip to: 8940 + /* 2599 */ MCD_OPC_Decode, + 216, + 30, + 247, + 2, // Opcode: t2ADDri + /* 2604 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2619 + /* 2609 */ MCD_OPC_CheckPredicate, + 45, + 182, + 24, + 0, // Skip to: 8940 + /* 2614 */ MCD_OPC_Decode, + 213, + 30, + 243, + 2, // Opcode: t2ADCri + /* 2619 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 2634 + /* 2624 */ MCD_OPC_CheckPredicate, + 45, + 167, + 24, + 0, // Skip to: 8940 + /* 2629 */ MCD_OPC_Decode, + 174, + 32, + 243, + 2, // Opcode: t2SBCri + /* 2634 */ MCD_OPC_FilterValue, + 5, + 57, + 0, + 0, // Skip to: 2696 + /* 2639 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 2642 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 2664 + /* 2647 */ MCD_OPC_CheckPredicate, + 45, + 34, + 0, + 0, // Skip to: 2686 + /* 2652 */ MCD_OPC_CheckField, + 16, + 4, + 13, + 27, + 0, + 0, // Skip to: 2686 + /* 2659 */ MCD_OPC_Decode, + 163, + 33, + 245, + 2, // Opcode: t2SUBspImm + /* 2664 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2686 + /* 2669 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 2686 + /* 2674 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 2686 + /* 2681 */ MCD_OPC_Decode, + 249, + 30, + 246, + 2, // Opcode: t2CMPri + /* 2686 */ MCD_OPC_CheckPredicate, + 45, + 105, + 24, + 0, // Skip to: 8940 + /* 2691 */ MCD_OPC_Decode, + 159, + 33, + 247, + 2, // Opcode: t2SUBri + /* 2696 */ MCD_OPC_FilterValue, + 6, + 95, + 24, + 0, // Skip to: 8940 + /* 2701 */ MCD_OPC_CheckPredicate, + 45, + 90, + 24, + 0, // Skip to: 8940 + /* 2706 */ MCD_OPC_Decode, + 167, + 32, + 243, + 2, // Opcode: t2RSBri + /* 2711 */ MCD_OPC_FilterValue, + 2, + 199, + 0, + 0, // Skip to: 2915 + /* 2716 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2719 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 2863 + /* 2724 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2727 */ MCD_OPC_FilterValue, + 0, + 64, + 24, + 0, // Skip to: 8940 + /* 2732 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2735 */ MCD_OPC_FilterValue, + 13, + 61, + 0, + 0, // Skip to: 2801 + /* 2740 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 2743 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 2772 + /* 2748 */ MCD_OPC_CheckPredicate, + 45, + 63, + 0, + 0, // Skip to: 2816 + /* 2753 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 56, + 0, + 0, // Skip to: 2816 + /* 2760 */ MCD_OPC_CheckField, + 8, + 4, + 13, + 49, + 0, + 0, // Skip to: 2816 + /* 2767 */ MCD_OPC_Decode, + 221, + 30, + 245, + 2, // Opcode: t2ADDspImm12 + /* 2772 */ MCD_OPC_FilterValue, + 1, + 39, + 0, + 0, // Skip to: 2816 + /* 2777 */ MCD_OPC_CheckPredicate, + 45, + 34, + 0, + 0, // Skip to: 2816 + /* 2782 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 27, + 0, + 0, // Skip to: 2816 + /* 2789 */ MCD_OPC_CheckField, + 8, + 4, + 13, + 20, + 0, + 0, // Skip to: 2816 + /* 2796 */ MCD_OPC_Decode, + 164, + 33, + 245, + 2, // Opcode: t2SUBspImm12 + /* 2801 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2816 + /* 2806 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 2816 + /* 2811 */ MCD_OPC_Decode, + 222, + 30, + 248, + 2, // Opcode: t2ADR + /* 2816 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 2819 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2841 + /* 2824 */ MCD_OPC_CheckPredicate, + 45, + 223, + 23, + 0, // Skip to: 8940 + /* 2829 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 216, + 23, + 0, // Skip to: 8940 + /* 2836 */ MCD_OPC_Decode, + 217, + 30, + 249, + 2, // Opcode: t2ADDri12 + /* 2841 */ MCD_OPC_FilterValue, + 1, + 206, + 23, + 0, // Skip to: 8940 + /* 2846 */ MCD_OPC_CheckPredicate, + 45, + 201, + 23, + 0, // Skip to: 8940 + /* 2851 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 194, + 23, + 0, // Skip to: 8940 + /* 2858 */ MCD_OPC_Decode, + 160, + 33, + 249, + 2, // Opcode: t2SUBri12 + /* 2863 */ MCD_OPC_FilterValue, + 1, + 184, + 23, + 0, // Skip to: 8940 + /* 2868 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 2871 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2893 + /* 2876 */ MCD_OPC_CheckPredicate, + 39, + 171, + 23, + 0, // Skip to: 8940 + /* 2881 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 164, + 23, + 0, // Skip to: 8940 + /* 2888 */ MCD_OPC_Decode, + 236, + 31, + 250, + 2, // Opcode: t2MOVi16 + /* 2893 */ MCD_OPC_FilterValue, + 1, + 154, + 23, + 0, // Skip to: 8940 + /* 2898 */ MCD_OPC_CheckPredicate, + 39, + 149, + 23, + 0, // Skip to: 8940 + /* 2903 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 142, + 23, + 0, // Skip to: 8940 + /* 2910 */ MCD_OPC_Decode, + 234, + 31, + 250, + 2, // Opcode: t2MOVTi16 + /* 2915 */ MCD_OPC_FilterValue, + 3, + 132, + 23, + 0, // Skip to: 8940 + /* 2920 */ MCD_OPC_ExtractField, + 22, + 2, // Inst{23-22} ... + /* 2923 */ MCD_OPC_FilterValue, + 0, + 72, + 0, + 0, // Skip to: 3000 + /* 2928 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 2931 */ MCD_OPC_FilterValue, + 0, + 116, + 23, + 0, // Skip to: 8940 + /* 2936 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 2939 */ MCD_OPC_FilterValue, + 0, + 108, + 23, + 0, // Skip to: 8940 + /* 2944 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 2947 */ MCD_OPC_FilterValue, + 0, + 100, + 23, + 0, // Skip to: 8940 + /* 2952 */ MCD_OPC_CheckPredicate, + 53, + 33, + 0, + 0, // Skip to: 2990 + /* 2957 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 26, + 0, + 0, // Skip to: 2990 + /* 2964 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 19, + 0, + 0, // Skip to: 2990 + /* 2971 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 12, + 0, + 0, // Skip to: 2990 + /* 2978 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 5, + 0, + 0, // Skip to: 2990 + /* 2985 */ MCD_OPC_Decode, + 230, + 32, + 251, + 2, // Opcode: t2SSAT16 + /* 2990 */ MCD_OPC_CheckPredicate, + 45, + 57, + 23, + 0, // Skip to: 8940 + /* 2995 */ MCD_OPC_Decode, + 229, + 32, + 252, + 2, // Opcode: t2SSAT + /* 3000 */ MCD_OPC_FilterValue, + 1, + 66, + 0, + 0, // Skip to: 3071 + /* 3005 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3008 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3023 + /* 3013 */ MCD_OPC_CheckPredicate, + 45, + 34, + 23, + 0, // Skip to: 8940 + /* 3018 */ MCD_OPC_Decode, + 177, + 32, + 253, + 2, // Opcode: t2SBFX + /* 3023 */ MCD_OPC_FilterValue, + 2, + 24, + 23, + 0, // Skip to: 8940 + /* 3028 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 3031 */ MCD_OPC_FilterValue, + 0, + 16, + 23, + 0, // Skip to: 8940 + /* 3036 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 3039 */ MCD_OPC_FilterValue, + 0, + 8, + 23, + 0, // Skip to: 8940 + /* 3044 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 3061 + /* 3049 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 3061 + /* 3056 */ MCD_OPC_Decode, + 229, + 30, + 254, + 2, // Opcode: t2BFC + /* 3061 */ MCD_OPC_CheckPredicate, + 45, + 242, + 22, + 0, // Skip to: 8940 + /* 3066 */ MCD_OPC_Decode, + 230, + 30, + 255, + 2, // Opcode: t2BFI + /* 3071 */ MCD_OPC_FilterValue, + 2, + 72, + 0, + 0, // Skip to: 3148 + /* 3076 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 3079 */ MCD_OPC_FilterValue, + 0, + 224, + 22, + 0, // Skip to: 8940 + /* 3084 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 3087 */ MCD_OPC_FilterValue, + 0, + 216, + 22, + 0, // Skip to: 8940 + /* 3092 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 3095 */ MCD_OPC_FilterValue, + 0, + 208, + 22, + 0, // Skip to: 8940 + /* 3100 */ MCD_OPC_CheckPredicate, + 53, + 33, + 0, + 0, // Skip to: 3138 + /* 3105 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 26, + 0, + 0, // Skip to: 3138 + /* 3112 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 19, + 0, + 0, // Skip to: 3138 + /* 3119 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 12, + 0, + 0, // Skip to: 3138 + /* 3126 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 5, + 0, + 0, // Skip to: 3138 + /* 3133 */ MCD_OPC_Decode, + 208, + 33, + 251, + 2, // Opcode: t2USAT16 + /* 3138 */ MCD_OPC_CheckPredicate, + 45, + 165, + 22, + 0, // Skip to: 8940 + /* 3143 */ MCD_OPC_Decode, + 207, + 33, + 252, + 2, // Opcode: t2USAT + /* 3148 */ MCD_OPC_FilterValue, + 3, + 155, + 22, + 0, // Skip to: 8940 + /* 3153 */ MCD_OPC_CheckPredicate, + 45, + 150, + 22, + 0, // Skip to: 8940 + /* 3158 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 143, + 22, + 0, // Skip to: 8940 + /* 3165 */ MCD_OPC_Decode, + 187, + 33, + 253, + 2, // Opcode: t2UBFX + /* 3170 */ MCD_OPC_FilterValue, + 1, + 133, + 22, + 0, // Skip to: 8940 + /* 3175 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 3178 */ MCD_OPC_FilterValue, + 0, + 146, + 4, + 0, // Skip to: 4353 + /* 3183 */ MCD_OPC_ExtractField, + 14, + 1, // Inst{14} ... + /* 3186 */ MCD_OPC_FilterValue, + 0, + 203, + 2, + 0, // Skip to: 3906 + /* 3191 */ MCD_OPC_ExtractField, + 0, + 12, // Inst{11-0} ... + /* 3194 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 3223 + /* 3199 */ MCD_OPC_CheckPredicate, + 54, + 166, + 0, + 0, // Skip to: 3370 + /* 3204 */ MCD_OPC_CheckField, + 16, + 11, + 143, + 15, + 158, + 0, + 0, // Skip to: 3370 + /* 3212 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 151, + 0, + 0, // Skip to: 3370 + /* 3219 */ MCD_OPC_Decode, + 138, + 31, + 51, // Opcode: t2DCPS1 + /* 3223 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 3252 + /* 3228 */ MCD_OPC_CheckPredicate, + 54, + 137, + 0, + 0, // Skip to: 3370 + /* 3233 */ MCD_OPC_CheckField, + 16, + 11, + 143, + 15, + 129, + 0, + 0, // Skip to: 3370 + /* 3241 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 122, + 0, + 0, // Skip to: 3370 + /* 3248 */ MCD_OPC_Decode, + 139, + 31, + 51, // Opcode: t2DCPS2 + /* 3252 */ MCD_OPC_FilterValue, + 3, + 24, + 0, + 0, // Skip to: 3281 + /* 3257 */ MCD_OPC_CheckPredicate, + 54, + 108, + 0, + 0, // Skip to: 3370 + /* 3262 */ MCD_OPC_CheckField, + 16, + 11, + 143, + 15, + 100, + 0, + 0, // Skip to: 3370 + /* 3270 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 93, + 0, + 0, // Skip to: 3370 + /* 3277 */ MCD_OPC_Decode, + 140, + 31, + 51, // Opcode: t2DCPS3 + /* 3281 */ MCD_OPC_FilterValue, + 18, + 24, + 0, + 0, // Skip to: 3310 + /* 3286 */ MCD_OPC_CheckPredicate, + 55, + 79, + 0, + 0, // Skip to: 3370 + /* 3291 */ MCD_OPC_CheckField, + 16, + 11, + 175, + 7, + 71, + 0, + 0, // Skip to: 3370 + /* 3299 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 64, + 0, + 0, // Skip to: 3370 + /* 3306 */ MCD_OPC_Decode, + 176, + 33, + 51, // Opcode: t2TSB + /* 3310 */ MCD_OPC_FilterValue, + 128, + 30, + 24, + 0, + 0, // Skip to: 3340 + /* 3316 */ MCD_OPC_CheckPredicate, + 46, + 49, + 0, + 0, // Skip to: 3370 + /* 3321 */ MCD_OPC_CheckField, + 20, + 7, + 60, + 42, + 0, + 0, // Skip to: 3370 + /* 3328 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 35, + 0, + 0, // Skip to: 3370 + /* 3335 */ MCD_OPC_Decode, + 239, + 30, + 128, + 3, // Opcode: t2BXJ + /* 3340 */ MCD_OPC_FilterValue, + 175, + 30, + 24, + 0, + 0, // Skip to: 3370 + /* 3346 */ MCD_OPC_CheckPredicate, + 56, + 19, + 0, + 0, // Skip to: 3370 + /* 3351 */ MCD_OPC_CheckField, + 16, + 11, + 191, + 7, + 11, + 0, + 0, // Skip to: 3370 + /* 3359 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 4, + 0, + 0, // Skip to: 3370 + /* 3366 */ MCD_OPC_Decode, + 243, + 30, + 51, // Opcode: t2CLREX + /* 3370 */ MCD_OPC_ExtractField, + 16, + 11, // Inst{26-16} ... + /* 3373 */ MCD_OPC_FilterValue, + 175, + 7, + 131, + 0, + 0, // Skip to: 3510 + /* 3379 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 3382 */ MCD_OPC_FilterValue, + 0, + 68, + 0, + 0, // Skip to: 3455 + /* 3387 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 3390 */ MCD_OPC_FilterValue, + 0, + 24, + 1, + 0, // Skip to: 3675 + /* 3395 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3398 */ MCD_OPC_FilterValue, + 0, + 16, + 1, + 0, // Skip to: 3675 + /* 3403 */ MCD_OPC_ExtractField, + 9, + 2, // Inst{10-9} ... + /* 3406 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 3438 + /* 3411 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 3428 + /* 3416 */ MCD_OPC_CheckField, + 4, + 4, + 15, + 5, + 0, + 0, // Skip to: 3428 + /* 3423 */ MCD_OPC_Decode, + 137, + 31, + 129, + 3, // Opcode: t2DBG + /* 3428 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 3438 + /* 3433 */ MCD_OPC_Decode, + 147, + 31, + 201, + 2, // Opcode: t2HINT + /* 3438 */ MCD_OPC_CheckPredicate, + 46, + 232, + 0, + 0, // Skip to: 3675 + /* 3443 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 225, + 0, + 0, // Skip to: 3675 + /* 3450 */ MCD_OPC_Decode, + 253, + 30, + 130, + 3, // Opcode: t2CPS2p + /* 3455 */ MCD_OPC_FilterValue, + 1, + 215, + 0, + 0, // Skip to: 3675 + /* 3460 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 3463 */ MCD_OPC_FilterValue, + 0, + 207, + 0, + 0, // Skip to: 3675 + /* 3468 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3471 */ MCD_OPC_FilterValue, + 0, + 199, + 0, + 0, // Skip to: 3675 + /* 3476 */ MCD_OPC_CheckPredicate, + 46, + 19, + 0, + 0, // Skip to: 3500 + /* 3481 */ MCD_OPC_CheckField, + 9, + 2, + 0, + 12, + 0, + 0, // Skip to: 3500 + /* 3488 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 5, + 0, + 0, // Skip to: 3500 + /* 3495 */ MCD_OPC_Decode, + 252, + 30, + 130, + 3, // Opcode: t2CPS1p + /* 3500 */ MCD_OPC_CheckPredicate, + 46, + 170, + 0, + 0, // Skip to: 3675 + /* 3505 */ MCD_OPC_Decode, + 254, + 30, + 130, + 3, // Opcode: t2CPS3p + /* 3510 */ MCD_OPC_FilterValue, + 191, + 7, + 69, + 0, + 0, // Skip to: 3585 + /* 3516 */ MCD_OPC_ExtractField, + 4, + 8, // Inst{11-4} ... + /* 3519 */ MCD_OPC_FilterValue, + 244, + 1, + 16, + 0, + 0, // Skip to: 3541 + /* 3525 */ MCD_OPC_CheckPredicate, + 57, + 145, + 0, + 0, // Skip to: 3675 + /* 3530 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 138, + 0, + 0, // Skip to: 3675 + /* 3537 */ MCD_OPC_Decode, + 143, + 31, + 61, // Opcode: t2DSB + /* 3541 */ MCD_OPC_FilterValue, + 245, + 1, + 16, + 0, + 0, // Skip to: 3563 + /* 3547 */ MCD_OPC_CheckPredicate, + 57, + 123, + 0, + 0, // Skip to: 3675 + /* 3552 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 116, + 0, + 0, // Skip to: 3675 + /* 3559 */ MCD_OPC_Decode, + 142, + 31, + 61, // Opcode: t2DMB + /* 3563 */ MCD_OPC_FilterValue, + 246, + 1, + 106, + 0, + 0, // Skip to: 3675 + /* 3569 */ MCD_OPC_CheckPredicate, + 57, + 101, + 0, + 0, // Skip to: 3675 + /* 3574 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 94, + 0, + 0, // Skip to: 3675 + /* 3581 */ MCD_OPC_Decode, + 149, + 31, + 62, // Opcode: t2ISB + /* 3585 */ MCD_OPC_FilterValue, + 222, + 7, + 24, + 0, + 0, // Skip to: 3615 + /* 3591 */ MCD_OPC_CheckPredicate, + 46, + 79, + 0, + 0, // Skip to: 3675 + /* 3596 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 72, + 0, + 0, // Skip to: 3675 + /* 3603 */ MCD_OPC_CheckField, + 8, + 4, + 15, + 65, + 0, + 0, // Skip to: 3675 + /* 3610 */ MCD_OPC_Decode, + 158, + 33, + 201, + 2, // Opcode: t2SUBS_PC_LR + /* 3615 */ MCD_OPC_FilterValue, + 239, + 7, + 24, + 0, + 0, // Skip to: 3645 + /* 3621 */ MCD_OPC_CheckPredicate, + 46, + 49, + 0, + 0, // Skip to: 3675 + /* 3626 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 42, + 0, + 0, // Skip to: 3675 + /* 3633 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 35, + 0, + 0, // Skip to: 3675 + /* 3640 */ MCD_OPC_Decode, + 244, + 31, + 131, + 3, // Opcode: t2MRS_AR + /* 3645 */ MCD_OPC_FilterValue, + 255, + 7, + 24, + 0, + 0, // Skip to: 3675 + /* 3651 */ MCD_OPC_CheckPredicate, + 46, + 19, + 0, + 0, // Skip to: 3675 + /* 3656 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 12, + 0, + 0, // Skip to: 3675 + /* 3663 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 5, + 0, + 0, // Skip to: 3675 + /* 3670 */ MCD_OPC_Decode, + 247, + 31, + 131, + 3, // Opcode: t2MRSsys_AR + /* 3675 */ MCD_OPC_ExtractField, + 20, + 7, // Inst{26-20} ... + /* 3678 */ MCD_OPC_FilterValue, + 59, + 22, + 0, + 0, // Skip to: 3705 + /* 3683 */ MCD_OPC_CheckPredicate, + 58, + 77, + 0, + 0, // Skip to: 3765 + /* 3688 */ MCD_OPC_CheckField, + 4, + 4, + 7, + 70, + 0, + 0, // Skip to: 3765 + /* 3695 */ MCD_OPC_SoftFail, + 143, + 64 /* 0x200f */, + 128, + 158, + 60 /* 0xf0f00 */, + /* 3701 */ MCD_OPC_Decode, + 173, + 32, + 51, // Opcode: t2SB + /* 3705 */ MCD_OPC_FilterValue, + 126, + 17, + 0, + 0, // Skip to: 3727 + /* 3710 */ MCD_OPC_CheckPredicate, + 59, + 50, + 0, + 0, // Skip to: 3765 + /* 3715 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 43, + 0, + 0, // Skip to: 3765 + /* 3722 */ MCD_OPC_Decode, + 148, + 31, + 132, + 3, // Opcode: t2HVC + /* 3727 */ MCD_OPC_FilterValue, + 127, + 33, + 0, + 0, // Skip to: 3765 + /* 3732 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3735 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3750 + /* 3740 */ MCD_OPC_CheckPredicate, + 60, + 20, + 0, + 0, // Skip to: 3765 + /* 3745 */ MCD_OPC_Decode, + 188, + 32, + 133, + 3, // Opcode: t2SMC + /* 3750 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 3765 + /* 3755 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 3765 + /* 3760 */ MCD_OPC_Decode, + 188, + 33, + 132, + 3, // Opcode: t2UDF + /* 3765 */ MCD_OPC_ExtractField, + 21, + 6, // Inst{26-21} ... + /* 3768 */ MCD_OPC_FilterValue, + 28, + 70, + 0, + 0, // Skip to: 3843 + /* 3773 */ MCD_OPC_CheckPredicate, + 46, + 19, + 0, + 0, // Skip to: 3797 + /* 3778 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 12, + 0, + 0, // Skip to: 3797 + /* 3785 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 5, + 0, + 0, // Skip to: 3797 + /* 3792 */ MCD_OPC_Decode, + 248, + 31, + 134, + 3, // Opcode: t2MSR_AR + /* 3797 */ MCD_OPC_CheckPredicate, + 61, + 26, + 0, + 0, // Skip to: 3828 + /* 3802 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 19, + 0, + 0, // Skip to: 3828 + /* 3809 */ MCD_OPC_CheckField, + 5, + 3, + 1, + 12, + 0, + 0, // Skip to: 3828 + /* 3816 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 5, + 0, + 0, // Skip to: 3828 + /* 3823 */ MCD_OPC_Decode, + 250, + 31, + 135, + 3, // Opcode: t2MSRbanked + /* 3828 */ MCD_OPC_CheckPredicate, + 62, + 63, + 0, + 0, // Skip to: 3896 + /* 3833 */ MCD_OPC_SoftFail, + 128, + 198, + 64 /* 0x102300 */, + 0, + /* 3838 */ MCD_OPC_Decode, + 249, + 31, + 136, + 3, // Opcode: t2MSR_M + /* 3843 */ MCD_OPC_FilterValue, + 31, + 48, + 0, + 0, // Skip to: 3896 + /* 3848 */ MCD_OPC_CheckPredicate, + 61, + 26, + 0, + 0, // Skip to: 3879 + /* 3853 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 19, + 0, + 0, // Skip to: 3879 + /* 3860 */ MCD_OPC_CheckField, + 5, + 3, + 1, + 12, + 0, + 0, // Skip to: 3879 + /* 3867 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 5, + 0, + 0, // Skip to: 3879 + /* 3874 */ MCD_OPC_Decode, + 246, + 31, + 137, + 3, // Opcode: t2MRSbanked + /* 3879 */ MCD_OPC_CheckPredicate, + 62, + 12, + 0, + 0, // Skip to: 3896 + /* 3884 */ MCD_OPC_SoftFail, + 128, + 192, + 64 /* 0x102000 */, + 128, + 128, + 60 /* 0xf0000 */, + /* 3891 */ MCD_OPC_Decode, + 245, + 31, + 138, + 3, // Opcode: t2MRS_M + /* 3896 */ MCD_OPC_CheckPredicate, + 45, + 175, + 19, + 0, // Skip to: 8940 + /* 3901 */ MCD_OPC_Decode, + 240, + 30, + 139, + 3, // Opcode: t2Bcc + /* 3906 */ MCD_OPC_FilterValue, + 1, + 165, + 19, + 0, // Skip to: 8940 + /* 3911 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3914 */ MCD_OPC_FilterValue, + 0, + 144, + 0, + 0, // Skip to: 4063 + /* 3919 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3922 */ MCD_OPC_FilterValue, + 1, + 149, + 19, + 0, // Skip to: 8940 + /* 3927 */ MCD_OPC_ExtractField, + 16, + 11, // Inst{26-16} ... + /* 3930 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 3945 + /* 3935 */ MCD_OPC_CheckPredicate, + 63, + 35, + 0, + 0, // Skip to: 3975 + /* 3940 */ MCD_OPC_Decode, + 223, + 31, + 140, + 3, // Opcode: t2LEUpdate + /* 3945 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 3960 + /* 3950 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 3975 + /* 3955 */ MCD_OPC_Decode, + 135, + 7, + 140, + 3, // Opcode: MVE_LETP + /* 3960 */ MCD_OPC_FilterValue, + 47, + 10, + 0, + 0, // Skip to: 3975 + /* 3965 */ MCD_OPC_CheckPredicate, + 63, + 5, + 0, + 0, // Skip to: 3975 + /* 3970 */ MCD_OPC_Decode, + 222, + 31, + 140, + 3, // Opcode: t2LE + /* 3975 */ MCD_OPC_ExtractField, + 20, + 7, // Inst{26-20} ... + /* 3978 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3993 + /* 3983 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 4053 + /* 3988 */ MCD_OPC_Decode, + 206, + 13, + 140, + 3, // Opcode: MVE_WLSTP_8 + /* 3993 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4008 + /* 3998 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 4053 + /* 4003 */ MCD_OPC_Decode, + 203, + 13, + 140, + 3, // Opcode: MVE_WLSTP_16 + /* 4008 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 4023 + /* 4013 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 4053 + /* 4018 */ MCD_OPC_Decode, + 204, + 13, + 140, + 3, // Opcode: MVE_WLSTP_32 + /* 4023 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 4038 + /* 4028 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 4053 + /* 4033 */ MCD_OPC_Decode, + 205, + 13, + 140, + 3, // Opcode: MVE_WLSTP_64 + /* 4038 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 4053 + /* 4043 */ MCD_OPC_CheckPredicate, + 63, + 5, + 0, + 0, // Skip to: 4053 + /* 4048 */ MCD_OPC_Decode, + 218, + 33, + 140, + 3, // Opcode: t2WLS + /* 4053 */ MCD_OPC_CheckPredicate, + 63, + 18, + 19, + 0, // Skip to: 8940 + /* 4058 */ MCD_OPC_Decode, + 231, + 30, + 141, + 3, // Opcode: t2BFLi + /* 4063 */ MCD_OPC_FilterValue, + 1, + 8, + 19, + 0, // Skip to: 8940 + /* 4068 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 4071 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 4239 + /* 4076 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 4079 */ MCD_OPC_FilterValue, + 1, + 248, + 18, + 0, // Skip to: 8940 + /* 4084 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 4087 */ MCD_OPC_FilterValue, + 0, + 107, + 0, + 0, // Skip to: 4199 + /* 4092 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 4095 */ MCD_OPC_FilterValue, + 0, + 21, + 0, + 0, // Skip to: 4121 + /* 4100 */ MCD_OPC_CheckPredicate, + 22, + 94, + 0, + 0, // Skip to: 4199 + /* 4105 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 87, + 0, + 0, // Skip to: 4199 + /* 4112 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 0, + /* 4116 */ MCD_OPC_Decode, + 133, + 7, + 140, + 3, // Opcode: MVE_DLSTP_8 + /* 4121 */ MCD_OPC_FilterValue, + 1, + 21, + 0, + 0, // Skip to: 4147 + /* 4126 */ MCD_OPC_CheckPredicate, + 22, + 68, + 0, + 0, // Skip to: 4199 + /* 4131 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 61, + 0, + 0, // Skip to: 4199 + /* 4138 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 0, + /* 4142 */ MCD_OPC_Decode, + 130, + 7, + 140, + 3, // Opcode: MVE_DLSTP_16 + /* 4147 */ MCD_OPC_FilterValue, + 2, + 21, + 0, + 0, // Skip to: 4173 + /* 4152 */ MCD_OPC_CheckPredicate, + 22, + 42, + 0, + 0, // Skip to: 4199 + /* 4157 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 35, + 0, + 0, // Skip to: 4199 + /* 4164 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 0, + /* 4168 */ MCD_OPC_Decode, + 131, + 7, + 140, + 3, // Opcode: MVE_DLSTP_32 + /* 4173 */ MCD_OPC_FilterValue, + 3, + 21, + 0, + 0, // Skip to: 4199 + /* 4178 */ MCD_OPC_CheckPredicate, + 22, + 16, + 0, + 0, // Skip to: 4199 + /* 4183 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 9, + 0, + 0, // Skip to: 4199 + /* 4190 */ MCD_OPC_SoftFail, + 254, + 15 /* 0x7fe */, + 0, + /* 4194 */ MCD_OPC_Decode, + 132, + 7, + 140, + 3, // Opcode: MVE_DLSTP_64 + /* 4199 */ MCD_OPC_CheckPredicate, + 22, + 25, + 0, + 0, // Skip to: 4229 + /* 4204 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 18, + 0, + 0, // Skip to: 4229 + /* 4211 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 11, + 0, + 0, // Skip to: 4229 + /* 4218 */ MCD_OPC_SoftFail, + 254, + 159, + 192, + 1 /* 0x300ffe */, + 0, + /* 4224 */ MCD_OPC_Decode, + 134, + 7, + 140, + 3, // Opcode: MVE_LCTP + /* 4229 */ MCD_OPC_CheckPredicate, + 63, + 98, + 18, + 0, // Skip to: 8940 + /* 4234 */ MCD_OPC_Decode, + 234, + 30, + 142, + 3, // Opcode: t2BFic + /* 4239 */ MCD_OPC_FilterValue, + 1, + 88, + 18, + 0, // Skip to: 8940 + /* 4244 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 4247 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 4301 + /* 4252 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 4255 */ MCD_OPC_FilterValue, + 1, + 72, + 18, + 0, // Skip to: 8940 + /* 4260 */ MCD_OPC_CheckPredicate, + 63, + 26, + 0, + 0, // Skip to: 4291 + /* 4265 */ MCD_OPC_CheckField, + 23, + 4, + 0, + 19, + 0, + 0, // Skip to: 4291 + /* 4272 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 12, + 0, + 0, // Skip to: 4291 + /* 4279 */ MCD_OPC_CheckField, + 1, + 11, + 0, + 5, + 0, + 0, // Skip to: 4291 + /* 4286 */ MCD_OPC_Decode, + 141, + 31, + 140, + 3, // Opcode: t2DLS + /* 4291 */ MCD_OPC_CheckPredicate, + 63, + 36, + 18, + 0, // Skip to: 8940 + /* 4296 */ MCD_OPC_Decode, + 233, + 30, + 143, + 3, // Opcode: t2BFi + /* 4301 */ MCD_OPC_FilterValue, + 1, + 26, + 18, + 0, // Skip to: 8940 + /* 4306 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4309 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4331 + /* 4314 */ MCD_OPC_CheckPredicate, + 63, + 13, + 18, + 0, // Skip to: 8940 + /* 4319 */ MCD_OPC_CheckField, + 0, + 12, + 1, + 6, + 18, + 0, // Skip to: 8940 + /* 4326 */ MCD_OPC_Decode, + 235, + 30, + 144, + 3, // Opcode: t2BFr + /* 4331 */ MCD_OPC_FilterValue, + 1, + 252, + 17, + 0, // Skip to: 8940 + /* 4336 */ MCD_OPC_CheckPredicate, + 63, + 247, + 17, + 0, // Skip to: 8940 + /* 4341 */ MCD_OPC_CheckField, + 0, + 12, + 1, + 240, + 17, + 0, // Skip to: 8940 + /* 4348 */ MCD_OPC_Decode, + 232, + 30, + 144, + 3, // Opcode: t2BFLr + /* 4353 */ MCD_OPC_FilterValue, + 1, + 230, + 17, + 0, // Skip to: 8940 + /* 4358 */ MCD_OPC_CheckPredicate, + 39, + 225, + 17, + 0, // Skip to: 8940 + /* 4363 */ MCD_OPC_CheckField, + 14, + 1, + 0, + 218, + 17, + 0, // Skip to: 8940 + /* 4370 */ MCD_OPC_Decode, + 228, + 30, + 145, + 3, // Opcode: t2B + /* 4375 */ MCD_OPC_FilterValue, + 31, + 208, + 17, + 0, // Skip to: 8940 + /* 4380 */ MCD_OPC_ExtractField, + 21, + 2, // Inst{22-21} ... + /* 4383 */ MCD_OPC_FilterValue, + 0, + 96, + 6, + 0, // Skip to: 6020 + /* 4388 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 4391 */ MCD_OPC_FilterValue, + 0, + 100, + 1, + 0, // Skip to: 4752 + /* 4396 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4399 */ MCD_OPC_FilterValue, + 0, + 125, + 0, + 0, // Skip to: 4529 + /* 4404 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 4407 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 4514 + /* 4412 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 4415 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4437 + /* 4420 */ MCD_OPC_CheckPredicate, + 45, + 163, + 17, + 0, // Skip to: 8940 + /* 4425 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 156, + 17, + 0, // Skip to: 8940 + /* 4432 */ MCD_OPC_Decode, + 138, + 33, + 146, + 3, // Opcode: t2STRBs + /* 4437 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 4459 + /* 4442 */ MCD_OPC_CheckPredicate, + 45, + 141, + 17, + 0, // Skip to: 8940 + /* 4447 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 134, + 17, + 0, // Skip to: 8940 + /* 4454 */ MCD_OPC_Decode, + 134, + 33, + 147, + 3, // Opcode: t2STRB_POST + /* 4459 */ MCD_OPC_FilterValue, + 3, + 124, + 17, + 0, // Skip to: 8940 + /* 4464 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 4467 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 4499 + /* 4472 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 4489 + /* 4477 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 4489 + /* 4484 */ MCD_OPC_Decode, + 133, + 33, + 148, + 3, // Opcode: t2STRBT + /* 4489 */ MCD_OPC_CheckPredicate, + 45, + 94, + 17, + 0, // Skip to: 8940 + /* 4494 */ MCD_OPC_Decode, + 137, + 33, + 149, + 3, // Opcode: t2STRBi8 + /* 4499 */ MCD_OPC_FilterValue, + 1, + 84, + 17, + 0, // Skip to: 8940 + /* 4504 */ MCD_OPC_CheckPredicate, + 45, + 79, + 17, + 0, // Skip to: 8940 + /* 4509 */ MCD_OPC_Decode, + 135, + 33, + 147, + 3, // Opcode: t2STRB_PRE + /* 4514 */ MCD_OPC_FilterValue, + 1, + 69, + 17, + 0, // Skip to: 8940 + /* 4519 */ MCD_OPC_CheckPredicate, + 45, + 64, + 17, + 0, // Skip to: 8940 + /* 4524 */ MCD_OPC_Decode, + 136, + 33, + 150, + 3, // Opcode: t2STRBi12 + /* 4529 */ MCD_OPC_FilterValue, + 1, + 54, + 17, + 0, // Skip to: 8940 + /* 4534 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 4537 */ MCD_OPC_FilterValue, + 0, + 143, + 0, + 0, // Skip to: 4685 + /* 4542 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 4545 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 4585 + /* 4550 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 4553 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 4717 + /* 4558 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 4575 + /* 4563 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4575 + /* 4570 */ MCD_OPC_Decode, + 141, + 32, + 151, + 3, // Opcode: t2PLDs + /* 4575 */ MCD_OPC_CheckPredicate, + 45, + 137, + 0, + 0, // Skip to: 4717 + /* 4580 */ MCD_OPC_Decode, + 186, + 31, + 151, + 3, // Opcode: t2LDRBs + /* 4585 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 4607 + /* 4590 */ MCD_OPC_CheckPredicate, + 45, + 122, + 0, + 0, // Skip to: 4717 + /* 4595 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 115, + 0, + 0, // Skip to: 4717 + /* 4602 */ MCD_OPC_Decode, + 181, + 31, + 147, + 3, // Opcode: t2LDRB_POST + /* 4607 */ MCD_OPC_FilterValue, + 3, + 105, + 0, + 0, // Skip to: 4717 + /* 4612 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 4615 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 4670 + /* 4620 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 4623 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4645 + /* 4628 */ MCD_OPC_CheckPredicate, + 45, + 27, + 0, + 0, // Skip to: 4660 + /* 4633 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 20, + 0, + 0, // Skip to: 4660 + /* 4640 */ MCD_OPC_Decode, + 139, + 32, + 152, + 3, // Opcode: t2PLDi8 + /* 4645 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4660 + /* 4650 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 4660 + /* 4655 */ MCD_OPC_Decode, + 180, + 31, + 153, + 3, // Opcode: t2LDRBT + /* 4660 */ MCD_OPC_CheckPredicate, + 45, + 52, + 0, + 0, // Skip to: 4717 + /* 4665 */ MCD_OPC_Decode, + 184, + 31, + 152, + 3, // Opcode: t2LDRBi8 + /* 4670 */ MCD_OPC_FilterValue, + 1, + 42, + 0, + 0, // Skip to: 4717 + /* 4675 */ MCD_OPC_CheckPredicate, + 45, + 37, + 0, + 0, // Skip to: 4717 + /* 4680 */ MCD_OPC_Decode, + 182, + 31, + 147, + 3, // Opcode: t2LDRB_PRE + /* 4685 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 4717 + /* 4690 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 4707 + /* 4695 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4707 + /* 4702 */ MCD_OPC_Decode, + 138, + 32, + 154, + 3, // Opcode: t2PLDi12 + /* 4707 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 4717 + /* 4712 */ MCD_OPC_Decode, + 183, + 31, + 154, + 3, // Opcode: t2LDRBi12 + /* 4717 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 4720 */ MCD_OPC_FilterValue, + 15, + 119, + 16, + 0, // Skip to: 8940 + /* 4725 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 4742 + /* 4730 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4742 + /* 4737 */ MCD_OPC_Decode, + 140, + 32, + 155, + 3, // Opcode: t2PLDpci + /* 4742 */ MCD_OPC_CheckPredicate, + 45, + 97, + 16, + 0, // Skip to: 8940 + /* 4747 */ MCD_OPC_Decode, + 185, + 31, + 155, + 3, // Opcode: t2LDRBpci + /* 4752 */ MCD_OPC_FilterValue, + 1, + 226, + 0, + 0, // Skip to: 4983 + /* 4757 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 4760 */ MCD_OPC_FilterValue, + 1, + 79, + 16, + 0, // Skip to: 8940 + /* 4765 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 4768 */ MCD_OPC_FilterValue, + 0, + 143, + 0, + 0, // Skip to: 4916 + /* 4773 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 4776 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 4816 + /* 4781 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 4784 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 4948 + /* 4789 */ MCD_OPC_CheckPredicate, + 64, + 12, + 0, + 0, // Skip to: 4806 + /* 4794 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4806 + /* 4801 */ MCD_OPC_Decode, + 145, + 32, + 151, + 3, // Opcode: t2PLIs + /* 4806 */ MCD_OPC_CheckPredicate, + 45, + 137, + 0, + 0, // Skip to: 4948 + /* 4811 */ MCD_OPC_Decode, + 207, + 31, + 151, + 3, // Opcode: t2LDRSBs + /* 4816 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 4838 + /* 4821 */ MCD_OPC_CheckPredicate, + 45, + 122, + 0, + 0, // Skip to: 4948 + /* 4826 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 115, + 0, + 0, // Skip to: 4948 + /* 4833 */ MCD_OPC_Decode, + 202, + 31, + 147, + 3, // Opcode: t2LDRSB_POST + /* 4838 */ MCD_OPC_FilterValue, + 3, + 105, + 0, + 0, // Skip to: 4948 + /* 4843 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 4846 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 4901 + /* 4851 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 4854 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4876 + /* 4859 */ MCD_OPC_CheckPredicate, + 64, + 27, + 0, + 0, // Skip to: 4891 + /* 4864 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 20, + 0, + 0, // Skip to: 4891 + /* 4871 */ MCD_OPC_Decode, + 143, + 32, + 152, + 3, // Opcode: t2PLIi8 + /* 4876 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4891 + /* 4881 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 4891 + /* 4886 */ MCD_OPC_Decode, + 201, + 31, + 153, + 3, // Opcode: t2LDRSBT + /* 4891 */ MCD_OPC_CheckPredicate, + 45, + 52, + 0, + 0, // Skip to: 4948 + /* 4896 */ MCD_OPC_Decode, + 205, + 31, + 152, + 3, // Opcode: t2LDRSBi8 + /* 4901 */ MCD_OPC_FilterValue, + 1, + 42, + 0, + 0, // Skip to: 4948 + /* 4906 */ MCD_OPC_CheckPredicate, + 45, + 37, + 0, + 0, // Skip to: 4948 + /* 4911 */ MCD_OPC_Decode, + 203, + 31, + 147, + 3, // Opcode: t2LDRSB_PRE + /* 4916 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 4948 + /* 4921 */ MCD_OPC_CheckPredicate, + 64, + 12, + 0, + 0, // Skip to: 4938 + /* 4926 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4938 + /* 4933 */ MCD_OPC_Decode, + 142, + 32, + 154, + 3, // Opcode: t2PLIi12 + /* 4938 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 4948 + /* 4943 */ MCD_OPC_Decode, + 204, + 31, + 154, + 3, // Opcode: t2LDRSBi12 + /* 4948 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 4951 */ MCD_OPC_FilterValue, + 15, + 144, + 15, + 0, // Skip to: 8940 + /* 4956 */ MCD_OPC_CheckPredicate, + 64, + 12, + 0, + 0, // Skip to: 4973 + /* 4961 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 4973 + /* 4968 */ MCD_OPC_Decode, + 144, + 32, + 155, + 3, // Opcode: t2PLIpci + /* 4973 */ MCD_OPC_CheckPredicate, + 45, + 122, + 15, + 0, // Skip to: 8940 + /* 4978 */ MCD_OPC_Decode, + 206, + 31, + 155, + 3, // Opcode: t2LDRSBpci + /* 4983 */ MCD_OPC_FilterValue, + 2, + 207, + 2, + 0, // Skip to: 5707 + /* 4988 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 4991 */ MCD_OPC_FilterValue, + 0, + 159, + 1, + 0, // Skip to: 5411 + /* 4996 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 4999 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 5081 + /* 5004 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5007 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5029 + /* 5012 */ MCD_OPC_CheckPredicate, + 45, + 83, + 15, + 0, // Skip to: 8940 + /* 5017 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 76, + 15, + 0, // Skip to: 8940 + /* 5024 */ MCD_OPC_Decode, + 225, + 31, + 215, + 2, // Opcode: t2LSLrr + /* 5029 */ MCD_OPC_FilterValue, + 1, + 66, + 15, + 0, // Skip to: 8940 + /* 5034 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5037 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5059 + /* 5042 */ MCD_OPC_CheckPredicate, + 53, + 53, + 15, + 0, // Skip to: 8940 + /* 5047 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 46, + 15, + 0, // Skip to: 8940 + /* 5054 */ MCD_OPC_Decode, + 171, + 32, + 156, + 3, // Opcode: t2SADD8 + /* 5059 */ MCD_OPC_FilterValue, + 1, + 36, + 15, + 0, // Skip to: 8940 + /* 5064 */ MCD_OPC_CheckPredicate, + 53, + 31, + 15, + 0, // Skip to: 8940 + /* 5069 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 24, + 15, + 0, // Skip to: 8940 + /* 5076 */ MCD_OPC_Decode, + 170, + 32, + 156, + 3, // Opcode: t2SADD16 + /* 5081 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 5147 + /* 5086 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5089 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5118 + /* 5094 */ MCD_OPC_CheckPredicate, + 53, + 1, + 15, + 0, // Skip to: 8940 + /* 5099 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 250, + 14, + 0, // Skip to: 8940 + /* 5106 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 243, + 14, + 0, // Skip to: 8940 + /* 5113 */ MCD_OPC_Decode, + 148, + 32, + 156, + 3, // Opcode: t2QADD8 + /* 5118 */ MCD_OPC_FilterValue, + 1, + 233, + 14, + 0, // Skip to: 8940 + /* 5123 */ MCD_OPC_CheckPredicate, + 53, + 228, + 14, + 0, // Skip to: 8940 + /* 5128 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 221, + 14, + 0, // Skip to: 8940 + /* 5135 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 214, + 14, + 0, // Skip to: 8940 + /* 5142 */ MCD_OPC_Decode, + 147, + 32, + 156, + 3, // Opcode: t2QADD16 + /* 5147 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 5213 + /* 5152 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5155 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5184 + /* 5160 */ MCD_OPC_CheckPredicate, + 53, + 191, + 14, + 0, // Skip to: 8940 + /* 5165 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 184, + 14, + 0, // Skip to: 8940 + /* 5172 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 177, + 14, + 0, // Skip to: 8940 + /* 5179 */ MCD_OPC_Decode, + 183, + 32, + 156, + 3, // Opcode: t2SHADD8 + /* 5184 */ MCD_OPC_FilterValue, + 1, + 167, + 14, + 0, // Skip to: 8940 + /* 5189 */ MCD_OPC_CheckPredicate, + 53, + 162, + 14, + 0, // Skip to: 8940 + /* 5194 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 155, + 14, + 0, // Skip to: 8940 + /* 5201 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 148, + 14, + 0, // Skip to: 8940 + /* 5208 */ MCD_OPC_Decode, + 182, + 32, + 156, + 3, // Opcode: t2SHADD16 + /* 5213 */ MCD_OPC_FilterValue, + 4, + 61, + 0, + 0, // Skip to: 5279 + /* 5218 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5221 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5250 + /* 5226 */ MCD_OPC_CheckPredicate, + 53, + 125, + 14, + 0, // Skip to: 8940 + /* 5231 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 118, + 14, + 0, // Skip to: 8940 + /* 5238 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 111, + 14, + 0, // Skip to: 8940 + /* 5245 */ MCD_OPC_Decode, + 185, + 33, + 156, + 3, // Opcode: t2UADD8 + /* 5250 */ MCD_OPC_FilterValue, + 1, + 101, + 14, + 0, // Skip to: 8940 + /* 5255 */ MCD_OPC_CheckPredicate, + 53, + 96, + 14, + 0, // Skip to: 8940 + /* 5260 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 89, + 14, + 0, // Skip to: 8940 + /* 5267 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 82, + 14, + 0, // Skip to: 8940 + /* 5274 */ MCD_OPC_Decode, + 184, + 33, + 156, + 3, // Opcode: t2UADD16 + /* 5279 */ MCD_OPC_FilterValue, + 5, + 61, + 0, + 0, // Skip to: 5345 + /* 5284 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5287 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5316 + /* 5292 */ MCD_OPC_CheckPredicate, + 53, + 59, + 14, + 0, // Skip to: 8940 + /* 5297 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 52, + 14, + 0, // Skip to: 8940 + /* 5304 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 45, + 14, + 0, // Skip to: 8940 + /* 5311 */ MCD_OPC_Decode, + 200, + 33, + 156, + 3, // Opcode: t2UQADD8 + /* 5316 */ MCD_OPC_FilterValue, + 1, + 35, + 14, + 0, // Skip to: 8940 + /* 5321 */ MCD_OPC_CheckPredicate, + 53, + 30, + 14, + 0, // Skip to: 8940 + /* 5326 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 23, + 14, + 0, // Skip to: 8940 + /* 5333 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 16, + 14, + 0, // Skip to: 8940 + /* 5340 */ MCD_OPC_Decode, + 199, + 33, + 156, + 3, // Opcode: t2UQADD16 + /* 5345 */ MCD_OPC_FilterValue, + 6, + 6, + 14, + 0, // Skip to: 8940 + /* 5350 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5353 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 5382 + /* 5358 */ MCD_OPC_CheckPredicate, + 53, + 249, + 13, + 0, // Skip to: 8940 + /* 5363 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 242, + 13, + 0, // Skip to: 8940 + /* 5370 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 235, + 13, + 0, // Skip to: 8940 + /* 5377 */ MCD_OPC_Decode, + 191, + 33, + 156, + 3, // Opcode: t2UHADD8 + /* 5382 */ MCD_OPC_FilterValue, + 1, + 225, + 13, + 0, // Skip to: 8940 + /* 5387 */ MCD_OPC_CheckPredicate, + 53, + 220, + 13, + 0, // Skip to: 8940 + /* 5392 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 213, + 13, + 0, // Skip to: 8940 + /* 5399 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 206, + 13, + 0, // Skip to: 8940 + /* 5406 */ MCD_OPC_Decode, + 190, + 33, + 156, + 3, // Opcode: t2UHADD16 + /* 5411 */ MCD_OPC_FilterValue, + 1, + 196, + 13, + 0, // Skip to: 8940 + /* 5416 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5419 */ MCD_OPC_FilterValue, + 0, + 139, + 0, + 0, // Skip to: 5563 + /* 5424 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5427 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 5467 + /* 5432 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5435 */ MCD_OPC_FilterValue, + 15, + 172, + 13, + 0, // Skip to: 8940 + /* 5440 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 5457 + /* 5445 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 5457 + /* 5452 */ MCD_OPC_Decode, + 170, + 33, + 157, + 3, // Opcode: t2SXTH + /* 5457 */ MCD_OPC_CheckPredicate, + 51, + 150, + 13, + 0, // Skip to: 8940 + /* 5462 */ MCD_OPC_Decode, + 167, + 33, + 158, + 3, // Opcode: t2SXTAH + /* 5467 */ MCD_OPC_FilterValue, + 1, + 140, + 13, + 0, // Skip to: 8940 + /* 5472 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 5475 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5497 + /* 5480 */ MCD_OPC_CheckPredicate, + 53, + 127, + 13, + 0, // Skip to: 8940 + /* 5485 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 120, + 13, + 0, // Skip to: 8940 + /* 5492 */ MCD_OPC_Decode, + 146, + 32, + 159, + 3, // Opcode: t2QADD + /* 5497 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 5519 + /* 5502 */ MCD_OPC_CheckPredicate, + 53, + 105, + 13, + 0, // Skip to: 8940 + /* 5507 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 98, + 13, + 0, // Skip to: 8940 + /* 5514 */ MCD_OPC_Decode, + 150, + 32, + 159, + 3, // Opcode: t2QDADD + /* 5519 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 5541 + /* 5524 */ MCD_OPC_CheckPredicate, + 53, + 83, + 13, + 0, // Skip to: 8940 + /* 5529 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 76, + 13, + 0, // Skip to: 8940 + /* 5536 */ MCD_OPC_Decode, + 153, + 32, + 159, + 3, // Opcode: t2QSUB + /* 5541 */ MCD_OPC_FilterValue, + 3, + 66, + 13, + 0, // Skip to: 8940 + /* 5546 */ MCD_OPC_CheckPredicate, + 53, + 61, + 13, + 0, // Skip to: 8940 + /* 5551 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 54, + 13, + 0, // Skip to: 8940 + /* 5558 */ MCD_OPC_Decode, + 151, + 32, + 159, + 3, // Opcode: t2QDSUB + /* 5563 */ MCD_OPC_FilterValue, + 1, + 44, + 13, + 0, // Skip to: 8940 + /* 5568 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5571 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 5611 + /* 5576 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5579 */ MCD_OPC_FilterValue, + 15, + 28, + 13, + 0, // Skip to: 8940 + /* 5584 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 5601 + /* 5589 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 5601 + /* 5596 */ MCD_OPC_Decode, + 217, + 33, + 157, + 3, // Opcode: t2UXTH + /* 5601 */ MCD_OPC_CheckPredicate, + 51, + 6, + 13, + 0, // Skip to: 8940 + /* 5606 */ MCD_OPC_Decode, + 214, + 33, + 158, + 3, // Opcode: t2UXTAH + /* 5611 */ MCD_OPC_FilterValue, + 1, + 252, + 12, + 0, // Skip to: 8940 + /* 5616 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 5619 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5641 + /* 5624 */ MCD_OPC_CheckPredicate, + 45, + 239, + 12, + 0, // Skip to: 8940 + /* 5629 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 232, + 12, + 0, // Skip to: 8940 + /* 5636 */ MCD_OPC_Decode, + 157, + 32, + 160, + 3, // Opcode: t2REV + /* 5641 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 5663 + /* 5646 */ MCD_OPC_CheckPredicate, + 45, + 217, + 12, + 0, // Skip to: 8940 + /* 5651 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 210, + 12, + 0, // Skip to: 8940 + /* 5658 */ MCD_OPC_Decode, + 158, + 32, + 160, + 3, // Opcode: t2REV16 + /* 5663 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 5685 + /* 5668 */ MCD_OPC_CheckPredicate, + 45, + 195, + 12, + 0, // Skip to: 8940 + /* 5673 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 188, + 12, + 0, // Skip to: 8940 + /* 5680 */ MCD_OPC_Decode, + 156, + 32, + 160, + 3, // Opcode: t2RBIT + /* 5685 */ MCD_OPC_FilterValue, + 3, + 178, + 12, + 0, // Skip to: 8940 + /* 5690 */ MCD_OPC_CheckPredicate, + 45, + 173, + 12, + 0, // Skip to: 8940 + /* 5695 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 166, + 12, + 0, // Skip to: 8940 + /* 5702 */ MCD_OPC_Decode, + 159, + 32, + 160, + 3, // Opcode: t2REVSH + /* 5707 */ MCD_OPC_FilterValue, + 3, + 156, + 12, + 0, // Skip to: 8940 + /* 5712 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 5715 */ MCD_OPC_FilterValue, + 0, + 98, + 0, + 0, // Skip to: 5818 + /* 5720 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5723 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 5778 + /* 5728 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5731 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 5763 + /* 5736 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 5753 + /* 5741 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5753 + /* 5748 */ MCD_OPC_Decode, + 251, + 31, + 156, + 3, // Opcode: t2MUL + /* 5753 */ MCD_OPC_CheckPredicate, + 45, + 110, + 12, + 0, // Skip to: 8940 + /* 5758 */ MCD_OPC_Decode, + 232, + 31, + 161, + 3, // Opcode: t2MLA + /* 5763 */ MCD_OPC_FilterValue, + 1, + 100, + 12, + 0, // Skip to: 8940 + /* 5768 */ MCD_OPC_CheckPredicate, + 45, + 95, + 12, + 0, // Skip to: 8940 + /* 5773 */ MCD_OPC_Decode, + 218, + 32, + 162, + 3, // Opcode: t2SMULL + /* 5778 */ MCD_OPC_FilterValue, + 1, + 85, + 12, + 0, // Skip to: 8940 + /* 5783 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5786 */ MCD_OPC_FilterValue, + 0, + 77, + 12, + 0, // Skip to: 8940 + /* 5791 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 5808 + /* 5796 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5808 + /* 5803 */ MCD_OPC_Decode, + 216, + 32, + 156, + 3, // Opcode: t2SMULBB + /* 5808 */ MCD_OPC_CheckPredicate, + 53, + 55, + 12, + 0, // Skip to: 8940 + /* 5813 */ MCD_OPC_Decode, + 189, + 32, + 161, + 3, // Opcode: t2SMLABB + /* 5818 */ MCD_OPC_FilterValue, + 1, + 65, + 0, + 0, // Skip to: 5888 + /* 5823 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5826 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 5848 + /* 5831 */ MCD_OPC_CheckPredicate, + 45, + 32, + 12, + 0, // Skip to: 8940 + /* 5836 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 25, + 12, + 0, // Skip to: 8940 + /* 5843 */ MCD_OPC_Decode, + 233, + 31, + 161, + 3, // Opcode: t2MLS + /* 5848 */ MCD_OPC_FilterValue, + 1, + 15, + 12, + 0, // Skip to: 8940 + /* 5853 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5856 */ MCD_OPC_FilterValue, + 0, + 7, + 12, + 0, // Skip to: 8940 + /* 5861 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 5878 + /* 5866 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5878 + /* 5873 */ MCD_OPC_Decode, + 217, + 32, + 156, + 3, // Opcode: t2SMULBT + /* 5878 */ MCD_OPC_CheckPredicate, + 53, + 241, + 11, + 0, // Skip to: 8940 + /* 5883 */ MCD_OPC_Decode, + 190, + 32, + 161, + 3, // Opcode: t2SMLABT + /* 5888 */ MCD_OPC_FilterValue, + 2, + 43, + 0, + 0, // Skip to: 5936 + /* 5893 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5896 */ MCD_OPC_FilterValue, + 1, + 223, + 11, + 0, // Skip to: 8940 + /* 5901 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5904 */ MCD_OPC_FilterValue, + 0, + 215, + 11, + 0, // Skip to: 8940 + /* 5909 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 5926 + /* 5914 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5926 + /* 5921 */ MCD_OPC_Decode, + 219, + 32, + 156, + 3, // Opcode: t2SMULTB + /* 5926 */ MCD_OPC_CheckPredicate, + 53, + 193, + 11, + 0, // Skip to: 8940 + /* 5931 */ MCD_OPC_Decode, + 200, + 32, + 161, + 3, // Opcode: t2SMLATB + /* 5936 */ MCD_OPC_FilterValue, + 3, + 43, + 0, + 0, // Skip to: 5984 + /* 5941 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 5944 */ MCD_OPC_FilterValue, + 1, + 175, + 11, + 0, // Skip to: 8940 + /* 5949 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 5952 */ MCD_OPC_FilterValue, + 0, + 167, + 11, + 0, // Skip to: 8940 + /* 5957 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 5974 + /* 5962 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 5974 + /* 5969 */ MCD_OPC_Decode, + 220, + 32, + 156, + 3, // Opcode: t2SMULTT + /* 5974 */ MCD_OPC_CheckPredicate, + 53, + 145, + 11, + 0, // Skip to: 8940 + /* 5979 */ MCD_OPC_Decode, + 201, + 32, + 161, + 3, // Opcode: t2SMLATT + /* 5984 */ MCD_OPC_FilterValue, + 15, + 135, + 11, + 0, // Skip to: 8940 + /* 5989 */ MCD_OPC_CheckPredicate, + 65, + 130, + 11, + 0, // Skip to: 8940 + /* 5994 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 123, + 11, + 0, // Skip to: 8940 + /* 6001 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 116, + 11, + 0, // Skip to: 8940 + /* 6008 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 109, + 11, + 0, // Skip to: 8940 + /* 6015 */ MCD_OPC_Decode, + 178, + 32, + 156, + 3, // Opcode: t2SDIV + /* 6020 */ MCD_OPC_FilterValue, + 1, + 129, + 4, + 0, // Skip to: 7178 + /* 6025 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 6028 */ MCD_OPC_FilterValue, + 0, + 82, + 1, + 0, // Skip to: 6371 + /* 6033 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6036 */ MCD_OPC_FilterValue, + 0, + 125, + 0, + 0, // Skip to: 6166 + /* 6041 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6044 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 6151 + /* 6049 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 6052 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6074 + /* 6057 */ MCD_OPC_CheckPredicate, + 45, + 62, + 11, + 0, // Skip to: 8940 + /* 6062 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 55, + 11, + 0, // Skip to: 8940 + /* 6069 */ MCD_OPC_Decode, + 151, + 33, + 146, + 3, // Opcode: t2STRHs + /* 6074 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 6096 + /* 6079 */ MCD_OPC_CheckPredicate, + 45, + 40, + 11, + 0, // Skip to: 8940 + /* 6084 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 33, + 11, + 0, // Skip to: 8940 + /* 6091 */ MCD_OPC_Decode, + 147, + 33, + 147, + 3, // Opcode: t2STRH_POST + /* 6096 */ MCD_OPC_FilterValue, + 3, + 23, + 11, + 0, // Skip to: 8940 + /* 6101 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 6104 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 6136 + /* 6109 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 6126 + /* 6114 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 6126 + /* 6121 */ MCD_OPC_Decode, + 146, + 33, + 148, + 3, // Opcode: t2STRHT + /* 6126 */ MCD_OPC_CheckPredicate, + 45, + 249, + 10, + 0, // Skip to: 8940 + /* 6131 */ MCD_OPC_Decode, + 150, + 33, + 149, + 3, // Opcode: t2STRHi8 + /* 6136 */ MCD_OPC_FilterValue, + 1, + 239, + 10, + 0, // Skip to: 8940 + /* 6141 */ MCD_OPC_CheckPredicate, + 45, + 234, + 10, + 0, // Skip to: 8940 + /* 6146 */ MCD_OPC_Decode, + 148, + 33, + 147, + 3, // Opcode: t2STRH_PRE + /* 6151 */ MCD_OPC_FilterValue, + 1, + 224, + 10, + 0, // Skip to: 8940 + /* 6156 */ MCD_OPC_CheckPredicate, + 45, + 219, + 10, + 0, // Skip to: 8940 + /* 6161 */ MCD_OPC_Decode, + 149, + 33, + 150, + 3, // Opcode: t2STRHi12 + /* 6166 */ MCD_OPC_FilterValue, + 1, + 209, + 10, + 0, // Skip to: 8940 + /* 6171 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6174 */ MCD_OPC_FilterValue, + 0, + 143, + 0, + 0, // Skip to: 6322 + /* 6179 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 6182 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 6222 + /* 6187 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 6190 */ MCD_OPC_FilterValue, + 0, + 159, + 0, + 0, // Skip to: 6354 + /* 6195 */ MCD_OPC_CheckPredicate, + 66, + 12, + 0, + 0, // Skip to: 6212 + /* 6200 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 6212 + /* 6207 */ MCD_OPC_Decode, + 137, + 32, + 151, + 3, // Opcode: t2PLDWs + /* 6212 */ MCD_OPC_CheckPredicate, + 45, + 137, + 0, + 0, // Skip to: 6354 + /* 6217 */ MCD_OPC_Decode, + 200, + 31, + 151, + 3, // Opcode: t2LDRHs + /* 6222 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 6244 + /* 6227 */ MCD_OPC_CheckPredicate, + 45, + 122, + 0, + 0, // Skip to: 6354 + /* 6232 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 115, + 0, + 0, // Skip to: 6354 + /* 6239 */ MCD_OPC_Decode, + 195, + 31, + 147, + 3, // Opcode: t2LDRH_POST + /* 6244 */ MCD_OPC_FilterValue, + 3, + 105, + 0, + 0, // Skip to: 6354 + /* 6249 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 6252 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 6307 + /* 6257 */ MCD_OPC_ExtractField, + 9, + 1, // Inst{9} ... + /* 6260 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6282 + /* 6265 */ MCD_OPC_CheckPredicate, + 66, + 27, + 0, + 0, // Skip to: 6297 + /* 6270 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 20, + 0, + 0, // Skip to: 6297 + /* 6277 */ MCD_OPC_Decode, + 136, + 32, + 152, + 3, // Opcode: t2PLDWi8 + /* 6282 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6297 + /* 6287 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 6297 + /* 6292 */ MCD_OPC_Decode, + 194, + 31, + 153, + 3, // Opcode: t2LDRHT + /* 6297 */ MCD_OPC_CheckPredicate, + 45, + 52, + 0, + 0, // Skip to: 6354 + /* 6302 */ MCD_OPC_Decode, + 198, + 31, + 152, + 3, // Opcode: t2LDRHi8 + /* 6307 */ MCD_OPC_FilterValue, + 1, + 42, + 0, + 0, // Skip to: 6354 + /* 6312 */ MCD_OPC_CheckPredicate, + 45, + 37, + 0, + 0, // Skip to: 6354 + /* 6317 */ MCD_OPC_Decode, + 196, + 31, + 147, + 3, // Opcode: t2LDRH_PRE + /* 6322 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 6354 + /* 6327 */ MCD_OPC_CheckPredicate, + 66, + 12, + 0, + 0, // Skip to: 6344 + /* 6332 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 6344 + /* 6339 */ MCD_OPC_Decode, + 135, + 32, + 154, + 3, // Opcode: t2PLDWi12 + /* 6344 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 6354 + /* 6349 */ MCD_OPC_Decode, + 197, + 31, + 154, + 3, // Opcode: t2LDRHi12 + /* 6354 */ MCD_OPC_CheckPredicate, + 45, + 21, + 10, + 0, // Skip to: 8940 + /* 6359 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 14, + 10, + 0, // Skip to: 8940 + /* 6366 */ MCD_OPC_Decode, + 199, + 31, + 155, + 3, // Opcode: t2LDRHpci + /* 6371 */ MCD_OPC_FilterValue, + 1, + 150, + 0, + 0, // Skip to: 6526 + /* 6376 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6379 */ MCD_OPC_FilterValue, + 1, + 252, + 9, + 0, // Skip to: 8940 + /* 6384 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6387 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 6494 + /* 6392 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 6395 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6417 + /* 6400 */ MCD_OPC_CheckPredicate, + 45, + 104, + 0, + 0, // Skip to: 6509 + /* 6405 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 97, + 0, + 0, // Skip to: 6509 + /* 6412 */ MCD_OPC_Decode, + 214, + 31, + 151, + 3, // Opcode: t2LDRSHs + /* 6417 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 6439 + /* 6422 */ MCD_OPC_CheckPredicate, + 45, + 82, + 0, + 0, // Skip to: 6509 + /* 6427 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 75, + 0, + 0, // Skip to: 6509 + /* 6434 */ MCD_OPC_Decode, + 209, + 31, + 147, + 3, // Opcode: t2LDRSH_POST + /* 6439 */ MCD_OPC_FilterValue, + 3, + 65, + 0, + 0, // Skip to: 6509 + /* 6444 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 6447 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 6479 + /* 6452 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 6469 + /* 6457 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 6469 + /* 6464 */ MCD_OPC_Decode, + 208, + 31, + 153, + 3, // Opcode: t2LDRSHT + /* 6469 */ MCD_OPC_CheckPredicate, + 45, + 35, + 0, + 0, // Skip to: 6509 + /* 6474 */ MCD_OPC_Decode, + 212, + 31, + 152, + 3, // Opcode: t2LDRSHi8 + /* 6479 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 6509 + /* 6484 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 6509 + /* 6489 */ MCD_OPC_Decode, + 210, + 31, + 147, + 3, // Opcode: t2LDRSH_PRE + /* 6494 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6509 + /* 6499 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 6509 + /* 6504 */ MCD_OPC_Decode, + 211, + 31, + 154, + 3, // Opcode: t2LDRSHi12 + /* 6509 */ MCD_OPC_CheckPredicate, + 45, + 122, + 9, + 0, // Skip to: 8940 + /* 6514 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 115, + 9, + 0, // Skip to: 8940 + /* 6521 */ MCD_OPC_Decode, + 213, + 31, + 155, + 3, // Opcode: t2LDRSHpci + /* 6526 */ MCD_OPC_FilterValue, + 2, + 156, + 1, + 0, // Skip to: 6943 + /* 6531 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 6534 */ MCD_OPC_FilterValue, + 0, + 242, + 0, + 0, // Skip to: 6781 + /* 6539 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 6542 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 6601 + /* 6547 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6550 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 6572 + /* 6555 */ MCD_OPC_CheckPredicate, + 45, + 76, + 9, + 0, // Skip to: 8940 + /* 6560 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 69, + 9, + 0, // Skip to: 8940 + /* 6567 */ MCD_OPC_Decode, + 227, + 31, + 215, + 2, // Opcode: t2LSRrr + /* 6572 */ MCD_OPC_FilterValue, + 1, + 59, + 9, + 0, // Skip to: 8940 + /* 6577 */ MCD_OPC_CheckPredicate, + 53, + 54, + 9, + 0, // Skip to: 8940 + /* 6582 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 47, + 9, + 0, // Skip to: 8940 + /* 6589 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 40, + 9, + 0, // Skip to: 8940 + /* 6596 */ MCD_OPC_Decode, + 172, + 32, + 156, + 3, // Opcode: t2SASX + /* 6601 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 6637 + /* 6606 */ MCD_OPC_CheckPredicate, + 53, + 25, + 9, + 0, // Skip to: 8940 + /* 6611 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 18, + 9, + 0, // Skip to: 8940 + /* 6618 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 11, + 9, + 0, // Skip to: 8940 + /* 6625 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 4, + 9, + 0, // Skip to: 8940 + /* 6632 */ MCD_OPC_Decode, + 149, + 32, + 156, + 3, // Opcode: t2QASX + /* 6637 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 6673 + /* 6642 */ MCD_OPC_CheckPredicate, + 53, + 245, + 8, + 0, // Skip to: 8940 + /* 6647 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 238, + 8, + 0, // Skip to: 8940 + /* 6654 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 231, + 8, + 0, // Skip to: 8940 + /* 6661 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 224, + 8, + 0, // Skip to: 8940 + /* 6668 */ MCD_OPC_Decode, + 184, + 32, + 156, + 3, // Opcode: t2SHASX + /* 6673 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 6709 + /* 6678 */ MCD_OPC_CheckPredicate, + 53, + 209, + 8, + 0, // Skip to: 8940 + /* 6683 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 202, + 8, + 0, // Skip to: 8940 + /* 6690 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 195, + 8, + 0, // Skip to: 8940 + /* 6697 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 188, + 8, + 0, // Skip to: 8940 + /* 6704 */ MCD_OPC_Decode, + 186, + 33, + 156, + 3, // Opcode: t2UASX + /* 6709 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 6745 + /* 6714 */ MCD_OPC_CheckPredicate, + 53, + 173, + 8, + 0, // Skip to: 8940 + /* 6719 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 166, + 8, + 0, // Skip to: 8940 + /* 6726 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 159, + 8, + 0, // Skip to: 8940 + /* 6733 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 152, + 8, + 0, // Skip to: 8940 + /* 6740 */ MCD_OPC_Decode, + 201, + 33, + 156, + 3, // Opcode: t2UQASX + /* 6745 */ MCD_OPC_FilterValue, + 6, + 142, + 8, + 0, // Skip to: 8940 + /* 6750 */ MCD_OPC_CheckPredicate, + 53, + 137, + 8, + 0, // Skip to: 8940 + /* 6755 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 130, + 8, + 0, // Skip to: 8940 + /* 6762 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 123, + 8, + 0, // Skip to: 8940 + /* 6769 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 116, + 8, + 0, // Skip to: 8940 + /* 6776 */ MCD_OPC_Decode, + 192, + 33, + 156, + 3, // Opcode: t2UHASX + /* 6781 */ MCD_OPC_FilterValue, + 1, + 106, + 8, + 0, // Skip to: 8940 + /* 6786 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6789 */ MCD_OPC_FilterValue, + 0, + 72, + 0, + 0, // Skip to: 6866 + /* 6794 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6797 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 6837 + /* 6802 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6805 */ MCD_OPC_FilterValue, + 15, + 82, + 8, + 0, // Skip to: 8940 + /* 6810 */ MCD_OPC_CheckPredicate, + 51, + 12, + 0, + 0, // Skip to: 6827 + /* 6815 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 6827 + /* 6822 */ MCD_OPC_Decode, + 169, + 33, + 157, + 3, // Opcode: t2SXTB16 + /* 6827 */ MCD_OPC_CheckPredicate, + 51, + 60, + 8, + 0, // Skip to: 8940 + /* 6832 */ MCD_OPC_Decode, + 166, + 33, + 158, + 3, // Opcode: t2SXTAB16 + /* 6837 */ MCD_OPC_FilterValue, + 1, + 50, + 8, + 0, // Skip to: 8940 + /* 6842 */ MCD_OPC_CheckPredicate, + 53, + 45, + 8, + 0, // Skip to: 8940 + /* 6847 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 38, + 8, + 0, // Skip to: 8940 + /* 6854 */ MCD_OPC_CheckField, + 4, + 3, + 0, + 31, + 8, + 0, // Skip to: 8940 + /* 6861 */ MCD_OPC_Decode, + 179, + 32, + 163, + 3, // Opcode: t2SEL + /* 6866 */ MCD_OPC_FilterValue, + 1, + 21, + 8, + 0, // Skip to: 8940 + /* 6871 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6874 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 6914 + /* 6879 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6882 */ MCD_OPC_FilterValue, + 15, + 5, + 8, + 0, // Skip to: 8940 + /* 6887 */ MCD_OPC_CheckPredicate, + 51, + 12, + 0, + 0, // Skip to: 6904 + /* 6892 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 6904 + /* 6899 */ MCD_OPC_Decode, + 216, + 33, + 157, + 3, // Opcode: t2UXTB16 + /* 6904 */ MCD_OPC_CheckPredicate, + 51, + 239, + 7, + 0, // Skip to: 8940 + /* 6909 */ MCD_OPC_Decode, + 213, + 33, + 158, + 3, // Opcode: t2UXTAB16 + /* 6914 */ MCD_OPC_FilterValue, + 1, + 229, + 7, + 0, // Skip to: 8940 + /* 6919 */ MCD_OPC_CheckPredicate, + 45, + 224, + 7, + 0, // Skip to: 8940 + /* 6924 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 217, + 7, + 0, // Skip to: 8940 + /* 6931 */ MCD_OPC_CheckField, + 4, + 3, + 0, + 210, + 7, + 0, // Skip to: 8940 + /* 6938 */ MCD_OPC_Decode, + 245, + 30, + 160, + 3, // Opcode: t2CLZ + /* 6943 */ MCD_OPC_FilterValue, + 3, + 200, + 7, + 0, // Skip to: 8940 + /* 6948 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 6951 */ MCD_OPC_FilterValue, + 0, + 98, + 0, + 0, // Skip to: 7054 + /* 6956 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6959 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 7014 + /* 6964 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 6967 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 6999 + /* 6972 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 6989 + /* 6977 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 6989 + /* 6984 */ MCD_OPC_Decode, + 214, + 32, + 156, + 3, // Opcode: t2SMUAD + /* 6989 */ MCD_OPC_CheckPredicate, + 53, + 154, + 7, + 0, // Skip to: 8940 + /* 6994 */ MCD_OPC_Decode, + 191, + 32, + 161, + 3, // Opcode: t2SMLAD + /* 6999 */ MCD_OPC_FilterValue, + 1, + 144, + 7, + 0, // Skip to: 8940 + /* 7004 */ MCD_OPC_CheckPredicate, + 45, + 139, + 7, + 0, // Skip to: 8940 + /* 7009 */ MCD_OPC_Decode, + 198, + 33, + 162, + 3, // Opcode: t2UMULL + /* 7014 */ MCD_OPC_FilterValue, + 1, + 129, + 7, + 0, // Skip to: 8940 + /* 7019 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7022 */ MCD_OPC_FilterValue, + 0, + 121, + 7, + 0, // Skip to: 8940 + /* 7027 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 7044 + /* 7032 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 7044 + /* 7039 */ MCD_OPC_Decode, + 221, + 32, + 156, + 3, // Opcode: t2SMULWB + /* 7044 */ MCD_OPC_CheckPredicate, + 53, + 99, + 7, + 0, // Skip to: 8940 + /* 7049 */ MCD_OPC_Decode, + 202, + 32, + 161, + 3, // Opcode: t2SMLAWB + /* 7054 */ MCD_OPC_FilterValue, + 1, + 83, + 0, + 0, // Skip to: 7142 + /* 7059 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7062 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 7102 + /* 7067 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7070 */ MCD_OPC_FilterValue, + 0, + 73, + 7, + 0, // Skip to: 8940 + /* 7075 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 7092 + /* 7080 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 7092 + /* 7087 */ MCD_OPC_Decode, + 215, + 32, + 156, + 3, // Opcode: t2SMUADX + /* 7092 */ MCD_OPC_CheckPredicate, + 53, + 51, + 7, + 0, // Skip to: 8940 + /* 7097 */ MCD_OPC_Decode, + 192, + 32, + 161, + 3, // Opcode: t2SMLADX + /* 7102 */ MCD_OPC_FilterValue, + 1, + 41, + 7, + 0, // Skip to: 8940 + /* 7107 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7110 */ MCD_OPC_FilterValue, + 0, + 33, + 7, + 0, // Skip to: 8940 + /* 7115 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 7132 + /* 7120 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 7132 + /* 7127 */ MCD_OPC_Decode, + 222, + 32, + 156, + 3, // Opcode: t2SMULWT + /* 7132 */ MCD_OPC_CheckPredicate, + 53, + 11, + 7, + 0, // Skip to: 8940 + /* 7137 */ MCD_OPC_Decode, + 203, + 32, + 161, + 3, // Opcode: t2SMLAWT + /* 7142 */ MCD_OPC_FilterValue, + 15, + 1, + 7, + 0, // Skip to: 8940 + /* 7147 */ MCD_OPC_CheckPredicate, + 65, + 252, + 6, + 0, // Skip to: 8940 + /* 7152 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 245, + 6, + 0, // Skip to: 8940 + /* 7159 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 238, + 6, + 0, // Skip to: 8940 + /* 7166 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 231, + 6, + 0, // Skip to: 8940 + /* 7173 */ MCD_OPC_Decode, + 189, + 33, + 156, + 3, // Opcode: t2UDIV + /* 7178 */ MCD_OPC_FilterValue, + 2, + 107, + 5, + 0, // Skip to: 8570 + /* 7183 */ MCD_OPC_ExtractField, + 24, + 3, // Inst{26-24} ... + /* 7186 */ MCD_OPC_FilterValue, + 0, + 24, + 1, + 0, // Skip to: 7471 + /* 7191 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7194 */ MCD_OPC_FilterValue, + 0, + 125, + 0, + 0, // Skip to: 7324 + /* 7199 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7202 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 7309 + /* 7207 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 7210 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7232 + /* 7215 */ MCD_OPC_CheckPredicate, + 45, + 184, + 6, + 0, // Skip to: 8940 + /* 7220 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 177, + 6, + 0, // Skip to: 8940 + /* 7227 */ MCD_OPC_Decode, + 157, + 33, + 164, + 3, // Opcode: t2STRs + /* 7232 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 7254 + /* 7237 */ MCD_OPC_CheckPredicate, + 45, + 162, + 6, + 0, // Skip to: 8940 + /* 7242 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 155, + 6, + 0, // Skip to: 8940 + /* 7249 */ MCD_OPC_Decode, + 153, + 33, + 147, + 3, // Opcode: t2STR_POST + /* 7254 */ MCD_OPC_FilterValue, + 3, + 145, + 6, + 0, // Skip to: 8940 + /* 7259 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7262 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 7294 + /* 7267 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 7284 + /* 7272 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 7284 + /* 7279 */ MCD_OPC_Decode, + 152, + 33, + 148, + 3, // Opcode: t2STRT + /* 7284 */ MCD_OPC_CheckPredicate, + 45, + 115, + 6, + 0, // Skip to: 8940 + /* 7289 */ MCD_OPC_Decode, + 156, + 33, + 165, + 3, // Opcode: t2STRi8 + /* 7294 */ MCD_OPC_FilterValue, + 1, + 105, + 6, + 0, // Skip to: 8940 + /* 7299 */ MCD_OPC_CheckPredicate, + 45, + 100, + 6, + 0, // Skip to: 8940 + /* 7304 */ MCD_OPC_Decode, + 154, + 33, + 147, + 3, // Opcode: t2STR_PRE + /* 7309 */ MCD_OPC_FilterValue, + 1, + 90, + 6, + 0, // Skip to: 8940 + /* 7314 */ MCD_OPC_CheckPredicate, + 45, + 85, + 6, + 0, // Skip to: 8940 + /* 7319 */ MCD_OPC_Decode, + 155, + 33, + 166, + 3, // Opcode: t2STRi12 + /* 7324 */ MCD_OPC_FilterValue, + 1, + 75, + 6, + 0, // Skip to: 8940 + /* 7329 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7332 */ MCD_OPC_FilterValue, + 0, + 102, + 0, + 0, // Skip to: 7439 + /* 7337 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 7340 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7362 + /* 7345 */ MCD_OPC_CheckPredicate, + 45, + 104, + 0, + 0, // Skip to: 7454 + /* 7350 */ MCD_OPC_CheckField, + 6, + 4, + 0, + 97, + 0, + 0, // Skip to: 7454 + /* 7357 */ MCD_OPC_Decode, + 221, + 31, + 151, + 3, // Opcode: t2LDRs + /* 7362 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 7384 + /* 7367 */ MCD_OPC_CheckPredicate, + 45, + 82, + 0, + 0, // Skip to: 7454 + /* 7372 */ MCD_OPC_CheckField, + 8, + 1, + 1, + 75, + 0, + 0, // Skip to: 7454 + /* 7379 */ MCD_OPC_Decode, + 216, + 31, + 147, + 3, // Opcode: t2LDR_POST + /* 7384 */ MCD_OPC_FilterValue, + 3, + 65, + 0, + 0, // Skip to: 7454 + /* 7389 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7392 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 7424 + /* 7397 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 7414 + /* 7402 */ MCD_OPC_CheckField, + 9, + 1, + 1, + 5, + 0, + 0, // Skip to: 7414 + /* 7409 */ MCD_OPC_Decode, + 215, + 31, + 153, + 3, // Opcode: t2LDRT + /* 7414 */ MCD_OPC_CheckPredicate, + 45, + 35, + 0, + 0, // Skip to: 7454 + /* 7419 */ MCD_OPC_Decode, + 219, + 31, + 152, + 3, // Opcode: t2LDRi8 + /* 7424 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 7454 + /* 7429 */ MCD_OPC_CheckPredicate, + 45, + 20, + 0, + 0, // Skip to: 7454 + /* 7434 */ MCD_OPC_Decode, + 217, + 31, + 147, + 3, // Opcode: t2LDR_PRE + /* 7439 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7454 + /* 7444 */ MCD_OPC_CheckPredicate, + 45, + 5, + 0, + 0, // Skip to: 7454 + /* 7449 */ MCD_OPC_Decode, + 218, + 31, + 154, + 3, // Opcode: t2LDRi12 + /* 7454 */ MCD_OPC_CheckPredicate, + 45, + 201, + 5, + 0, // Skip to: 8940 + /* 7459 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 194, + 5, + 0, // Skip to: 8940 + /* 7466 */ MCD_OPC_Decode, + 220, + 31, + 155, + 3, // Opcode: t2LDRpci + /* 7471 */ MCD_OPC_FilterValue, + 2, + 163, + 2, + 0, // Skip to: 8151 + /* 7476 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 7479 */ MCD_OPC_FilterValue, + 0, + 159, + 1, + 0, // Skip to: 7899 + /* 7484 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 7487 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 7569 + /* 7492 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7495 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7517 + /* 7500 */ MCD_OPC_CheckPredicate, + 45, + 155, + 5, + 0, // Skip to: 8940 + /* 7505 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 148, + 5, + 0, // Skip to: 8940 + /* 7512 */ MCD_OPC_Decode, + 227, + 30, + 215, + 2, // Opcode: t2ASRrr + /* 7517 */ MCD_OPC_FilterValue, + 1, + 138, + 5, + 0, // Skip to: 8940 + /* 7522 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7525 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7547 + /* 7530 */ MCD_OPC_CheckPredicate, + 53, + 125, + 5, + 0, // Skip to: 8940 + /* 7535 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 118, + 5, + 0, // Skip to: 8940 + /* 7542 */ MCD_OPC_Decode, + 233, + 32, + 156, + 3, // Opcode: t2SSUB8 + /* 7547 */ MCD_OPC_FilterValue, + 1, + 108, + 5, + 0, // Skip to: 8940 + /* 7552 */ MCD_OPC_CheckPredicate, + 53, + 103, + 5, + 0, // Skip to: 8940 + /* 7557 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 96, + 5, + 0, // Skip to: 8940 + /* 7564 */ MCD_OPC_Decode, + 232, + 32, + 156, + 3, // Opcode: t2SSUB16 + /* 7569 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 7635 + /* 7574 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7577 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7606 + /* 7582 */ MCD_OPC_CheckPredicate, + 53, + 73, + 5, + 0, // Skip to: 8940 + /* 7587 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 66, + 5, + 0, // Skip to: 8940 + /* 7594 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 59, + 5, + 0, // Skip to: 8940 + /* 7601 */ MCD_OPC_Decode, + 155, + 32, + 156, + 3, // Opcode: t2QSUB8 + /* 7606 */ MCD_OPC_FilterValue, + 1, + 49, + 5, + 0, // Skip to: 8940 + /* 7611 */ MCD_OPC_CheckPredicate, + 53, + 44, + 5, + 0, // Skip to: 8940 + /* 7616 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 37, + 5, + 0, // Skip to: 8940 + /* 7623 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 30, + 5, + 0, // Skip to: 8940 + /* 7630 */ MCD_OPC_Decode, + 154, + 32, + 156, + 3, // Opcode: t2QSUB16 + /* 7635 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 7701 + /* 7640 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7643 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7672 + /* 7648 */ MCD_OPC_CheckPredicate, + 53, + 7, + 5, + 0, // Skip to: 8940 + /* 7653 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 0, + 5, + 0, // Skip to: 8940 + /* 7660 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 249, + 4, + 0, // Skip to: 8940 + /* 7667 */ MCD_OPC_Decode, + 187, + 32, + 156, + 3, // Opcode: t2SHSUB8 + /* 7672 */ MCD_OPC_FilterValue, + 1, + 239, + 4, + 0, // Skip to: 8940 + /* 7677 */ MCD_OPC_CheckPredicate, + 53, + 234, + 4, + 0, // Skip to: 8940 + /* 7682 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 227, + 4, + 0, // Skip to: 8940 + /* 7689 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 220, + 4, + 0, // Skip to: 8940 + /* 7696 */ MCD_OPC_Decode, + 186, + 32, + 156, + 3, // Opcode: t2SHSUB16 + /* 7701 */ MCD_OPC_FilterValue, + 4, + 61, + 0, + 0, // Skip to: 7767 + /* 7706 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7709 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7738 + /* 7714 */ MCD_OPC_CheckPredicate, + 53, + 197, + 4, + 0, // Skip to: 8940 + /* 7719 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 190, + 4, + 0, // Skip to: 8940 + /* 7726 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 183, + 4, + 0, // Skip to: 8940 + /* 7733 */ MCD_OPC_Decode, + 211, + 33, + 156, + 3, // Opcode: t2USUB8 + /* 7738 */ MCD_OPC_FilterValue, + 1, + 173, + 4, + 0, // Skip to: 8940 + /* 7743 */ MCD_OPC_CheckPredicate, + 53, + 168, + 4, + 0, // Skip to: 8940 + /* 7748 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 161, + 4, + 0, // Skip to: 8940 + /* 7755 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 154, + 4, + 0, // Skip to: 8940 + /* 7762 */ MCD_OPC_Decode, + 210, + 33, + 156, + 3, // Opcode: t2USUB16 + /* 7767 */ MCD_OPC_FilterValue, + 5, + 61, + 0, + 0, // Skip to: 7833 + /* 7772 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7775 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7804 + /* 7780 */ MCD_OPC_CheckPredicate, + 53, + 131, + 4, + 0, // Skip to: 8940 + /* 7785 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 124, + 4, + 0, // Skip to: 8940 + /* 7792 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 117, + 4, + 0, // Skip to: 8940 + /* 7799 */ MCD_OPC_Decode, + 204, + 33, + 156, + 3, // Opcode: t2UQSUB8 + /* 7804 */ MCD_OPC_FilterValue, + 1, + 107, + 4, + 0, // Skip to: 8940 + /* 7809 */ MCD_OPC_CheckPredicate, + 53, + 102, + 4, + 0, // Skip to: 8940 + /* 7814 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 95, + 4, + 0, // Skip to: 8940 + /* 7821 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 88, + 4, + 0, // Skip to: 8940 + /* 7828 */ MCD_OPC_Decode, + 203, + 33, + 156, + 3, // Opcode: t2UQSUB16 + /* 7833 */ MCD_OPC_FilterValue, + 6, + 78, + 4, + 0, // Skip to: 8940 + /* 7838 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7841 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 7870 + /* 7846 */ MCD_OPC_CheckPredicate, + 53, + 65, + 4, + 0, // Skip to: 8940 + /* 7851 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 58, + 4, + 0, // Skip to: 8940 + /* 7858 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 51, + 4, + 0, // Skip to: 8940 + /* 7865 */ MCD_OPC_Decode, + 195, + 33, + 156, + 3, // Opcode: t2UHSUB8 + /* 7870 */ MCD_OPC_FilterValue, + 1, + 41, + 4, + 0, // Skip to: 8940 + /* 7875 */ MCD_OPC_CheckPredicate, + 53, + 36, + 4, + 0, // Skip to: 8940 + /* 7880 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 29, + 4, + 0, // Skip to: 8940 + /* 7887 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 22, + 4, + 0, // Skip to: 8940 + /* 7894 */ MCD_OPC_Decode, + 194, + 33, + 156, + 3, // Opcode: t2UHSUB16 + /* 7899 */ MCD_OPC_FilterValue, + 1, + 12, + 4, + 0, // Skip to: 8940 + /* 7904 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7907 */ MCD_OPC_FilterValue, + 0, + 117, + 0, + 0, // Skip to: 8029 + /* 7912 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 7915 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 7955 + /* 7920 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7923 */ MCD_OPC_FilterValue, + 15, + 244, + 3, + 0, // Skip to: 8940 + /* 7928 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 7945 + /* 7933 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 7945 + /* 7940 */ MCD_OPC_Decode, + 168, + 33, + 157, + 3, // Opcode: t2SXTB + /* 7945 */ MCD_OPC_CheckPredicate, + 51, + 222, + 3, + 0, // Skip to: 8940 + /* 7950 */ MCD_OPC_Decode, + 165, + 33, + 158, + 3, // Opcode: t2SXTAB + /* 7955 */ MCD_OPC_FilterValue, + 1, + 212, + 3, + 0, // Skip to: 8940 + /* 7960 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 7963 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 7985 + /* 7968 */ MCD_OPC_CheckPredicate, + 67, + 199, + 3, + 0, // Skip to: 8940 + /* 7973 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 192, + 3, + 0, // Skip to: 8940 + /* 7980 */ MCD_OPC_Decode, + 255, + 30, + 156, + 3, // Opcode: t2CRC32B + /* 7985 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 8007 + /* 7990 */ MCD_OPC_CheckPredicate, + 67, + 177, + 3, + 0, // Skip to: 8940 + /* 7995 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 170, + 3, + 0, // Skip to: 8940 + /* 8002 */ MCD_OPC_Decode, + 131, + 31, + 156, + 3, // Opcode: t2CRC32H + /* 8007 */ MCD_OPC_FilterValue, + 2, + 160, + 3, + 0, // Skip to: 8940 + /* 8012 */ MCD_OPC_CheckPredicate, + 67, + 155, + 3, + 0, // Skip to: 8940 + /* 8017 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 148, + 3, + 0, // Skip to: 8940 + /* 8024 */ MCD_OPC_Decode, + 132, + 31, + 156, + 3, // Opcode: t2CRC32W + /* 8029 */ MCD_OPC_FilterValue, + 1, + 138, + 3, + 0, // Skip to: 8940 + /* 8034 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8037 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 8077 + /* 8042 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 8045 */ MCD_OPC_FilterValue, + 15, + 122, + 3, + 0, // Skip to: 8940 + /* 8050 */ MCD_OPC_CheckPredicate, + 45, + 12, + 0, + 0, // Skip to: 8067 + /* 8055 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 8067 + /* 8062 */ MCD_OPC_Decode, + 215, + 33, + 157, + 3, // Opcode: t2UXTB + /* 8067 */ MCD_OPC_CheckPredicate, + 51, + 100, + 3, + 0, // Skip to: 8940 + /* 8072 */ MCD_OPC_Decode, + 212, + 33, + 158, + 3, // Opcode: t2UXTAB + /* 8077 */ MCD_OPC_FilterValue, + 1, + 90, + 3, + 0, // Skip to: 8940 + /* 8082 */ MCD_OPC_ExtractField, + 4, + 3, // Inst{6-4} ... + /* 8085 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 8107 + /* 8090 */ MCD_OPC_CheckPredicate, + 67, + 77, + 3, + 0, // Skip to: 8940 + /* 8095 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 70, + 3, + 0, // Skip to: 8940 + /* 8102 */ MCD_OPC_Decode, + 128, + 31, + 156, + 3, // Opcode: t2CRC32CB + /* 8107 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 8129 + /* 8112 */ MCD_OPC_CheckPredicate, + 67, + 55, + 3, + 0, // Skip to: 8940 + /* 8117 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 48, + 3, + 0, // Skip to: 8940 + /* 8124 */ MCD_OPC_Decode, + 129, + 31, + 156, + 3, // Opcode: t2CRC32CH + /* 8129 */ MCD_OPC_FilterValue, + 2, + 38, + 3, + 0, // Skip to: 8940 + /* 8134 */ MCD_OPC_CheckPredicate, + 67, + 33, + 3, + 0, // Skip to: 8940 + /* 8139 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 26, + 3, + 0, // Skip to: 8940 + /* 8146 */ MCD_OPC_Decode, + 130, + 31, + 156, + 3, // Opcode: t2CRC32CW + /* 8151 */ MCD_OPC_FilterValue, + 3, + 16, + 3, + 0, // Skip to: 8940 + /* 8156 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 8159 */ MCD_OPC_FilterValue, + 0, + 98, + 0, + 0, // Skip to: 8262 + /* 8164 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8167 */ MCD_OPC_FilterValue, + 0, + 50, + 0, + 0, // Skip to: 8222 + /* 8172 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8175 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 8207 + /* 8180 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8197 + /* 8185 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8197 + /* 8192 */ MCD_OPC_Decode, + 223, + 32, + 156, + 3, // Opcode: t2SMUSD + /* 8197 */ MCD_OPC_CheckPredicate, + 53, + 226, + 2, + 0, // Skip to: 8940 + /* 8202 */ MCD_OPC_Decode, + 204, + 32, + 161, + 3, // Opcode: t2SMLSD + /* 8207 */ MCD_OPC_FilterValue, + 1, + 216, + 2, + 0, // Skip to: 8940 + /* 8212 */ MCD_OPC_CheckPredicate, + 45, + 211, + 2, + 0, // Skip to: 8940 + /* 8217 */ MCD_OPC_Decode, + 193, + 32, + 167, + 3, // Opcode: t2SMLAL + /* 8222 */ MCD_OPC_FilterValue, + 1, + 201, + 2, + 0, // Skip to: 8940 + /* 8227 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8230 */ MCD_OPC_FilterValue, + 0, + 193, + 2, + 0, // Skip to: 8940 + /* 8235 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8252 + /* 8240 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8252 + /* 8247 */ MCD_OPC_Decode, + 212, + 32, + 156, + 3, // Opcode: t2SMMUL + /* 8252 */ MCD_OPC_CheckPredicate, + 53, + 171, + 2, + 0, // Skip to: 8940 + /* 8257 */ MCD_OPC_Decode, + 208, + 32, + 161, + 3, // Opcode: t2SMMLA + /* 8262 */ MCD_OPC_FilterValue, + 1, + 83, + 0, + 0, // Skip to: 8350 + /* 8267 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8270 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 8310 + /* 8275 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8278 */ MCD_OPC_FilterValue, + 0, + 145, + 2, + 0, // Skip to: 8940 + /* 8283 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8300 + /* 8288 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8300 + /* 8295 */ MCD_OPC_Decode, + 224, + 32, + 156, + 3, // Opcode: t2SMUSDX + /* 8300 */ MCD_OPC_CheckPredicate, + 53, + 123, + 2, + 0, // Skip to: 8940 + /* 8305 */ MCD_OPC_Decode, + 205, + 32, + 161, + 3, // Opcode: t2SMLSDX + /* 8310 */ MCD_OPC_FilterValue, + 1, + 113, + 2, + 0, // Skip to: 8940 + /* 8315 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 8318 */ MCD_OPC_FilterValue, + 0, + 105, + 2, + 0, // Skip to: 8940 + /* 8323 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8340 + /* 8328 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8340 + /* 8335 */ MCD_OPC_Decode, + 213, + 32, + 156, + 3, // Opcode: t2SMMULR + /* 8340 */ MCD_OPC_CheckPredicate, + 53, + 83, + 2, + 0, // Skip to: 8940 + /* 8345 */ MCD_OPC_Decode, + 209, + 32, + 161, + 3, // Opcode: t2SMMLAR + /* 8350 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 8379 + /* 8355 */ MCD_OPC_CheckPredicate, + 53, + 68, + 2, + 0, // Skip to: 8940 + /* 8360 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 61, + 2, + 0, // Skip to: 8940 + /* 8367 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 54, + 2, + 0, // Skip to: 8940 + /* 8374 */ MCD_OPC_Decode, + 194, + 32, + 167, + 3, // Opcode: t2SMLALBB + /* 8379 */ MCD_OPC_FilterValue, + 9, + 24, + 0, + 0, // Skip to: 8408 + /* 8384 */ MCD_OPC_CheckPredicate, + 53, + 39, + 2, + 0, // Skip to: 8940 + /* 8389 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 32, + 2, + 0, // Skip to: 8940 + /* 8396 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 25, + 2, + 0, // Skip to: 8940 + /* 8403 */ MCD_OPC_Decode, + 195, + 32, + 167, + 3, // Opcode: t2SMLALBT + /* 8408 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 8437 + /* 8413 */ MCD_OPC_CheckPredicate, + 53, + 10, + 2, + 0, // Skip to: 8940 + /* 8418 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 3, + 2, + 0, // Skip to: 8940 + /* 8425 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 252, + 1, + 0, // Skip to: 8940 + /* 8432 */ MCD_OPC_Decode, + 198, + 32, + 167, + 3, // Opcode: t2SMLALTB + /* 8437 */ MCD_OPC_FilterValue, + 11, + 24, + 0, + 0, // Skip to: 8466 + /* 8442 */ MCD_OPC_CheckPredicate, + 53, + 237, + 1, + 0, // Skip to: 8940 + /* 8447 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 230, + 1, + 0, // Skip to: 8940 + /* 8454 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 223, + 1, + 0, // Skip to: 8940 + /* 8461 */ MCD_OPC_Decode, + 199, + 32, + 167, + 3, // Opcode: t2SMLALTT + /* 8466 */ MCD_OPC_FilterValue, + 12, + 47, + 0, + 0, // Skip to: 8518 + /* 8471 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8474 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 8496 + /* 8479 */ MCD_OPC_CheckPredicate, + 53, + 200, + 1, + 0, // Skip to: 8940 + /* 8484 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 193, + 1, + 0, // Skip to: 8940 + /* 8491 */ MCD_OPC_Decode, + 196, + 32, + 167, + 3, // Opcode: t2SMLALD + /* 8496 */ MCD_OPC_FilterValue, + 1, + 183, + 1, + 0, // Skip to: 8940 + /* 8501 */ MCD_OPC_CheckPredicate, + 53, + 178, + 1, + 0, // Skip to: 8940 + /* 8506 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 171, + 1, + 0, // Skip to: 8940 + /* 8513 */ MCD_OPC_Decode, + 206, + 32, + 167, + 3, // Opcode: t2SMLSLD + /* 8518 */ MCD_OPC_FilterValue, + 13, + 161, + 1, + 0, // Skip to: 8940 + /* 8523 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8526 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 8548 + /* 8531 */ MCD_OPC_CheckPredicate, + 53, + 148, + 1, + 0, // Skip to: 8940 + /* 8536 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 141, + 1, + 0, // Skip to: 8940 + /* 8543 */ MCD_OPC_Decode, + 197, + 32, + 167, + 3, // Opcode: t2SMLALDX + /* 8548 */ MCD_OPC_FilterValue, + 1, + 131, + 1, + 0, // Skip to: 8940 + /* 8553 */ MCD_OPC_CheckPredicate, + 53, + 126, + 1, + 0, // Skip to: 8940 + /* 8558 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 119, + 1, + 0, // Skip to: 8940 + /* 8565 */ MCD_OPC_Decode, + 207, + 32, + 167, + 3, // Opcode: t2SMLSLDX + /* 8570 */ MCD_OPC_FilterValue, + 3, + 109, + 1, + 0, // Skip to: 8940 + /* 8575 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 8578 */ MCD_OPC_FilterValue, + 0, + 131, + 0, + 0, // Skip to: 8714 + /* 8583 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 8586 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 8608 + /* 8591 */ MCD_OPC_CheckPredicate, + 45, + 88, + 1, + 0, // Skip to: 8940 + /* 8596 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 81, + 1, + 0, // Skip to: 8940 + /* 8603 */ MCD_OPC_Decode, + 165, + 32, + 215, + 2, // Opcode: t2RORrr + /* 8608 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 8637 + /* 8613 */ MCD_OPC_CheckPredicate, + 53, + 66, + 1, + 0, // Skip to: 8940 + /* 8618 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 59, + 1, + 0, // Skip to: 8940 + /* 8625 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 52, + 1, + 0, // Skip to: 8940 + /* 8632 */ MCD_OPC_Decode, + 231, + 32, + 156, + 3, // Opcode: t2SSAX + /* 8637 */ MCD_OPC_FilterValue, + 6, + 50, + 0, + 0, // Skip to: 8692 + /* 8642 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 8645 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8660 + /* 8650 */ MCD_OPC_CheckPredicate, + 53, + 29, + 1, + 0, // Skip to: 8940 + /* 8655 */ MCD_OPC_Decode, + 210, + 32, + 161, + 3, // Opcode: t2SMMLS + /* 8660 */ MCD_OPC_FilterValue, + 1, + 19, + 1, + 0, // Skip to: 8940 + /* 8665 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8682 + /* 8670 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 5, + 0, + 0, // Skip to: 8682 + /* 8677 */ MCD_OPC_Decode, + 205, + 33, + 156, + 3, // Opcode: t2USAD8 + /* 8682 */ MCD_OPC_CheckPredicate, + 53, + 253, + 0, + 0, // Skip to: 8940 + /* 8687 */ MCD_OPC_Decode, + 206, + 33, + 161, + 3, // Opcode: t2USADA8 + /* 8692 */ MCD_OPC_FilterValue, + 7, + 243, + 0, + 0, // Skip to: 8940 + /* 8697 */ MCD_OPC_CheckPredicate, + 45, + 238, + 0, + 0, // Skip to: 8940 + /* 8702 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 231, + 0, + 0, // Skip to: 8940 + /* 8709 */ MCD_OPC_Decode, + 197, + 33, + 167, + 3, // Opcode: t2UMLAL + /* 8714 */ MCD_OPC_FilterValue, + 1, + 54, + 0, + 0, // Skip to: 8773 + /* 8719 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 8722 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 8751 + /* 8727 */ MCD_OPC_CheckPredicate, + 53, + 208, + 0, + 0, // Skip to: 8940 + /* 8732 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 201, + 0, + 0, // Skip to: 8940 + /* 8739 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 194, + 0, + 0, // Skip to: 8940 + /* 8746 */ MCD_OPC_Decode, + 152, + 32, + 156, + 3, // Opcode: t2QSAX + /* 8751 */ MCD_OPC_FilterValue, + 6, + 184, + 0, + 0, // Skip to: 8940 + /* 8756 */ MCD_OPC_CheckPredicate, + 53, + 179, + 0, + 0, // Skip to: 8940 + /* 8761 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 172, + 0, + 0, // Skip to: 8940 + /* 8768 */ MCD_OPC_Decode, + 211, + 32, + 161, + 3, // Opcode: t2SMMLSR + /* 8773 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 8809 + /* 8778 */ MCD_OPC_CheckPredicate, + 53, + 157, + 0, + 0, // Skip to: 8940 + /* 8783 */ MCD_OPC_CheckField, + 23, + 4, + 5, + 150, + 0, + 0, // Skip to: 8940 + /* 8790 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 143, + 0, + 0, // Skip to: 8940 + /* 8797 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 136, + 0, + 0, // Skip to: 8940 + /* 8804 */ MCD_OPC_Decode, + 185, + 32, + 156, + 3, // Opcode: t2SHSAX + /* 8809 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 8845 + /* 8814 */ MCD_OPC_CheckPredicate, + 53, + 121, + 0, + 0, // Skip to: 8940 + /* 8819 */ MCD_OPC_CheckField, + 23, + 4, + 5, + 114, + 0, + 0, // Skip to: 8940 + /* 8826 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 107, + 0, + 0, // Skip to: 8940 + /* 8833 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 100, + 0, + 0, // Skip to: 8940 + /* 8840 */ MCD_OPC_Decode, + 209, + 33, + 156, + 3, // Opcode: t2USAX + /* 8845 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 8881 + /* 8850 */ MCD_OPC_CheckPredicate, + 53, + 85, + 0, + 0, // Skip to: 8940 + /* 8855 */ MCD_OPC_CheckField, + 23, + 4, + 5, + 78, + 0, + 0, // Skip to: 8940 + /* 8862 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 71, + 0, + 0, // Skip to: 8940 + /* 8869 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 64, + 0, + 0, // Skip to: 8940 + /* 8876 */ MCD_OPC_Decode, + 202, + 33, + 156, + 3, // Opcode: t2UQSAX + /* 8881 */ MCD_OPC_FilterValue, + 6, + 54, + 0, + 0, // Skip to: 8940 + /* 8886 */ MCD_OPC_ExtractField, + 23, + 4, // Inst{26-23} ... + /* 8889 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 8918 + /* 8894 */ MCD_OPC_CheckPredicate, + 53, + 41, + 0, + 0, // Skip to: 8940 + /* 8899 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 34, + 0, + 0, // Skip to: 8940 + /* 8906 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 27, + 0, + 0, // Skip to: 8940 + /* 8913 */ MCD_OPC_Decode, + 193, + 33, + 156, + 3, // Opcode: t2UHSAX + /* 8918 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 8940 + /* 8923 */ MCD_OPC_CheckPredicate, + 53, + 12, + 0, + 0, // Skip to: 8940 + /* 8928 */ MCD_OPC_CheckField, + 20, + 1, + 0, + 5, + 0, + 0, // Skip to: 8940 + /* 8935 */ MCD_OPC_Decode, + 196, + 33, + 167, + 3, // Opcode: t2UMAAL + /* 8940 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableThumb2CDE32[] = { + /* 0 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 3 */ MCD_OPC_FilterValue, + 118, + 24, + 1, + 0, // Skip to: 288 + /* 8 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 151, + 0, + 0, // Skip to: 167 + /* 16 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 71 + /* 24 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 27 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 49 + /* 32 */ MCD_OPC_CheckPredicate, + 68, + 112, + 3, + 0, // Skip to: 917 + /* 37 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 105, + 3, + 0, // Skip to: 917 + /* 44 */ MCD_OPC_Decode, + 232, + 5, + 168, + 3, // Opcode: CDE_VCX1_fpsp + /* 49 */ MCD_OPC_FilterValue, + 3, + 95, + 3, + 0, // Skip to: 917 + /* 54 */ MCD_OPC_CheckPredicate, + 68, + 90, + 3, + 0, // Skip to: 917 + /* 59 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 83, + 3, + 0, // Skip to: 917 + /* 66 */ MCD_OPC_Decode, + 238, + 5, + 169, + 3, // Opcode: CDE_VCX2_fpsp + /* 71 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 93 + /* 76 */ MCD_OPC_CheckPredicate, + 68, + 68, + 3, + 0, // Skip to: 917 + /* 81 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 61, + 3, + 0, // Skip to: 917 + /* 88 */ MCD_OPC_Decode, + 244, + 5, + 170, + 3, // Opcode: CDE_VCX3_fpsp + /* 93 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 145 + /* 98 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 101 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 123 + /* 106 */ MCD_OPC_CheckPredicate, + 68, + 38, + 3, + 0, // Skip to: 917 + /* 111 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 31, + 3, + 0, // Skip to: 917 + /* 118 */ MCD_OPC_Decode, + 231, + 5, + 171, + 3, // Opcode: CDE_VCX1_fpdp + /* 123 */ MCD_OPC_FilterValue, + 3, + 21, + 3, + 0, // Skip to: 917 + /* 128 */ MCD_OPC_CheckPredicate, + 68, + 16, + 3, + 0, // Skip to: 917 + /* 133 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 9, + 3, + 0, // Skip to: 917 + /* 140 */ MCD_OPC_Decode, + 237, + 5, + 172, + 3, // Opcode: CDE_VCX2_fpdp + /* 145 */ MCD_OPC_FilterValue, + 3, + 255, + 2, + 0, // Skip to: 917 + /* 150 */ MCD_OPC_CheckPredicate, + 68, + 250, + 2, + 0, // Skip to: 917 + /* 155 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 243, + 2, + 0, // Skip to: 917 + /* 162 */ MCD_OPC_Decode, + 243, + 5, + 173, + 3, // Opcode: CDE_VCX3_fpdp + /* 167 */ MCD_OPC_FilterValue, + 1, + 233, + 2, + 0, // Skip to: 917 + /* 172 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 175 */ MCD_OPC_FilterValue, + 0, + 66, + 0, + 0, // Skip to: 246 + /* 180 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 183 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 211 + /* 188 */ MCD_OPC_CheckPredicate, + 69, + 212, + 2, + 0, // Skip to: 917 + /* 193 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 205, + 2, + 0, // Skip to: 917 + /* 200 */ MCD_OPC_SoftFail, + 128, + 128, + 128, + 2 /* 0x400000 */, + 0, + /* 206 */ MCD_OPC_Decode, + 233, + 5, + 174, + 3, // Opcode: CDE_VCX1_vec + /* 211 */ MCD_OPC_FilterValue, + 3, + 189, + 2, + 0, // Skip to: 917 + /* 216 */ MCD_OPC_CheckPredicate, + 69, + 184, + 2, + 0, // Skip to: 917 + /* 221 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 177, + 2, + 0, // Skip to: 917 + /* 228 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 170, + 2, + 0, // Skip to: 917 + /* 235 */ MCD_OPC_SoftFail, + 160, + 128, + 128, + 2 /* 0x400020 */, + 0, + /* 241 */ MCD_OPC_Decode, + 239, + 5, + 175, + 3, // Opcode: CDE_VCX2_vec + /* 246 */ MCD_OPC_FilterValue, + 1, + 154, + 2, + 0, // Skip to: 917 + /* 251 */ MCD_OPC_CheckPredicate, + 69, + 149, + 2, + 0, // Skip to: 917 + /* 256 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 142, + 2, + 0, // Skip to: 917 + /* 263 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 135, + 2, + 0, // Skip to: 917 + /* 270 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 128, + 2, + 0, // Skip to: 917 + /* 277 */ MCD_OPC_SoftFail, + 160, + 129, + 128, + 2 /* 0x4000a0 */, + 0, + /* 283 */ MCD_OPC_Decode, + 245, + 5, + 176, + 3, // Opcode: CDE_VCX3_vec + /* 288 */ MCD_OPC_FilterValue, + 119, + 167, + 0, + 0, // Skip to: 460 + /* 293 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 296 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 378 + /* 301 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 304 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 356 + /* 309 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 312 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 334 + /* 317 */ MCD_OPC_CheckPredicate, + 70, + 83, + 2, + 0, // Skip to: 917 + /* 322 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 76, + 2, + 0, // Skip to: 917 + /* 329 */ MCD_OPC_Decode, + 216, + 5, + 177, + 3, // Opcode: CDE_CX1 + /* 334 */ MCD_OPC_FilterValue, + 1, + 66, + 2, + 0, // Skip to: 917 + /* 339 */ MCD_OPC_CheckPredicate, + 70, + 61, + 2, + 0, // Skip to: 917 + /* 344 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 54, + 2, + 0, // Skip to: 917 + /* 351 */ MCD_OPC_Decode, + 220, + 5, + 178, + 3, // Opcode: CDE_CX2 + /* 356 */ MCD_OPC_FilterValue, + 1, + 44, + 2, + 0, // Skip to: 917 + /* 361 */ MCD_OPC_CheckPredicate, + 70, + 39, + 2, + 0, // Skip to: 917 + /* 366 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 32, + 2, + 0, // Skip to: 917 + /* 373 */ MCD_OPC_Decode, + 224, + 5, + 179, + 3, // Opcode: CDE_CX3 + /* 378 */ MCD_OPC_FilterValue, + 1, + 22, + 2, + 0, // Skip to: 917 + /* 383 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 386 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 438 + /* 391 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 394 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 416 + /* 399 */ MCD_OPC_CheckPredicate, + 70, + 1, + 2, + 0, // Skip to: 917 + /* 404 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 250, + 1, + 0, // Skip to: 917 + /* 411 */ MCD_OPC_Decode, + 218, + 5, + 180, + 3, // Opcode: CDE_CX1D + /* 416 */ MCD_OPC_FilterValue, + 1, + 240, + 1, + 0, // Skip to: 917 + /* 421 */ MCD_OPC_CheckPredicate, + 70, + 235, + 1, + 0, // Skip to: 917 + /* 426 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 228, + 1, + 0, // Skip to: 917 + /* 433 */ MCD_OPC_Decode, + 222, + 5, + 181, + 3, // Opcode: CDE_CX2D + /* 438 */ MCD_OPC_FilterValue, + 1, + 218, + 1, + 0, // Skip to: 917 + /* 443 */ MCD_OPC_CheckPredicate, + 70, + 213, + 1, + 0, // Skip to: 917 + /* 448 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 206, + 1, + 0, // Skip to: 917 + /* 455 */ MCD_OPC_Decode, + 226, + 5, + 182, + 3, // Opcode: CDE_CX3D + /* 460 */ MCD_OPC_FilterValue, + 126, + 24, + 1, + 0, // Skip to: 745 + /* 465 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 468 */ MCD_OPC_FilterValue, + 0, + 151, + 0, + 0, // Skip to: 624 + /* 473 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 476 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 528 + /* 481 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 484 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 506 + /* 489 */ MCD_OPC_CheckPredicate, + 68, + 167, + 1, + 0, // Skip to: 917 + /* 494 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 160, + 1, + 0, // Skip to: 917 + /* 501 */ MCD_OPC_Decode, + 229, + 5, + 183, + 3, // Opcode: CDE_VCX1A_fpsp + /* 506 */ MCD_OPC_FilterValue, + 3, + 150, + 1, + 0, // Skip to: 917 + /* 511 */ MCD_OPC_CheckPredicate, + 68, + 145, + 1, + 0, // Skip to: 917 + /* 516 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 138, + 1, + 0, // Skip to: 917 + /* 523 */ MCD_OPC_Decode, + 235, + 5, + 184, + 3, // Opcode: CDE_VCX2A_fpsp + /* 528 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 550 + /* 533 */ MCD_OPC_CheckPredicate, + 68, + 123, + 1, + 0, // Skip to: 917 + /* 538 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 116, + 1, + 0, // Skip to: 917 + /* 545 */ MCD_OPC_Decode, + 241, + 5, + 185, + 3, // Opcode: CDE_VCX3A_fpsp + /* 550 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 602 + /* 555 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 558 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 580 + /* 563 */ MCD_OPC_CheckPredicate, + 68, + 93, + 1, + 0, // Skip to: 917 + /* 568 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 86, + 1, + 0, // Skip to: 917 + /* 575 */ MCD_OPC_Decode, + 228, + 5, + 186, + 3, // Opcode: CDE_VCX1A_fpdp + /* 580 */ MCD_OPC_FilterValue, + 3, + 76, + 1, + 0, // Skip to: 917 + /* 585 */ MCD_OPC_CheckPredicate, + 68, + 71, + 1, + 0, // Skip to: 917 + /* 590 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 64, + 1, + 0, // Skip to: 917 + /* 597 */ MCD_OPC_Decode, + 234, + 5, + 187, + 3, // Opcode: CDE_VCX2A_fpdp + /* 602 */ MCD_OPC_FilterValue, + 3, + 54, + 1, + 0, // Skip to: 917 + /* 607 */ MCD_OPC_CheckPredicate, + 68, + 49, + 1, + 0, // Skip to: 917 + /* 612 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 42, + 1, + 0, // Skip to: 917 + /* 619 */ MCD_OPC_Decode, + 240, + 5, + 188, + 3, // Opcode: CDE_VCX3A_fpdp + /* 624 */ MCD_OPC_FilterValue, + 1, + 32, + 1, + 0, // Skip to: 917 + /* 629 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 632 */ MCD_OPC_FilterValue, + 0, + 66, + 0, + 0, // Skip to: 703 + /* 637 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 640 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 668 + /* 645 */ MCD_OPC_CheckPredicate, + 69, + 11, + 1, + 0, // Skip to: 917 + /* 650 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 1, + 0, // Skip to: 917 + /* 657 */ MCD_OPC_SoftFail, + 128, + 128, + 128, + 2 /* 0x400000 */, + 0, + /* 663 */ MCD_OPC_Decode, + 230, + 5, + 189, + 3, // Opcode: CDE_VCX1A_vec + /* 668 */ MCD_OPC_FilterValue, + 3, + 244, + 0, + 0, // Skip to: 917 + /* 673 */ MCD_OPC_CheckPredicate, + 69, + 239, + 0, + 0, // Skip to: 917 + /* 678 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 232, + 0, + 0, // Skip to: 917 + /* 685 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 225, + 0, + 0, // Skip to: 917 + /* 692 */ MCD_OPC_SoftFail, + 160, + 128, + 128, + 2 /* 0x400020 */, + 0, + /* 698 */ MCD_OPC_Decode, + 236, + 5, + 190, + 3, // Opcode: CDE_VCX2A_vec + /* 703 */ MCD_OPC_FilterValue, + 1, + 209, + 0, + 0, // Skip to: 917 + /* 708 */ MCD_OPC_CheckPredicate, + 69, + 204, + 0, + 0, // Skip to: 917 + /* 713 */ MCD_OPC_CheckField, + 16, + 1, + 0, + 197, + 0, + 0, // Skip to: 917 + /* 720 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 190, + 0, + 0, // Skip to: 917 + /* 727 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 183, + 0, + 0, // Skip to: 917 + /* 734 */ MCD_OPC_SoftFail, + 160, + 129, + 128, + 2 /* 0x4000a0 */, + 0, + /* 740 */ MCD_OPC_Decode, + 242, + 5, + 191, + 3, // Opcode: CDE_VCX3A_vec + /* 745 */ MCD_OPC_FilterValue, + 127, + 167, + 0, + 0, // Skip to: 917 + /* 750 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 753 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 835 + /* 758 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 761 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 813 + /* 766 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 769 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 791 + /* 774 */ MCD_OPC_CheckPredicate, + 70, + 138, + 0, + 0, // Skip to: 917 + /* 779 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 131, + 0, + 0, // Skip to: 917 + /* 786 */ MCD_OPC_Decode, + 217, + 5, + 192, + 3, // Opcode: CDE_CX1A + /* 791 */ MCD_OPC_FilterValue, + 1, + 121, + 0, + 0, // Skip to: 917 + /* 796 */ MCD_OPC_CheckPredicate, + 70, + 116, + 0, + 0, // Skip to: 917 + /* 801 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 109, + 0, + 0, // Skip to: 917 + /* 808 */ MCD_OPC_Decode, + 221, + 5, + 193, + 3, // Opcode: CDE_CX2A + /* 813 */ MCD_OPC_FilterValue, + 1, + 99, + 0, + 0, // Skip to: 917 + /* 818 */ MCD_OPC_CheckPredicate, + 70, + 94, + 0, + 0, // Skip to: 917 + /* 823 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 87, + 0, + 0, // Skip to: 917 + /* 830 */ MCD_OPC_Decode, + 225, + 5, + 194, + 3, // Opcode: CDE_CX3A + /* 835 */ MCD_OPC_FilterValue, + 1, + 77, + 0, + 0, // Skip to: 917 + /* 840 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 843 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 895 + /* 848 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 851 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 873 + /* 856 */ MCD_OPC_CheckPredicate, + 70, + 56, + 0, + 0, // Skip to: 917 + /* 861 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 49, + 0, + 0, // Skip to: 917 + /* 868 */ MCD_OPC_Decode, + 219, + 5, + 195, + 3, // Opcode: CDE_CX1DA + /* 873 */ MCD_OPC_FilterValue, + 1, + 39, + 0, + 0, // Skip to: 917 + /* 878 */ MCD_OPC_CheckPredicate, + 70, + 34, + 0, + 0, // Skip to: 917 + /* 883 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 27, + 0, + 0, // Skip to: 917 + /* 890 */ MCD_OPC_Decode, + 223, + 5, + 196, + 3, // Opcode: CDE_CX2DA + /* 895 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 917 + /* 900 */ MCD_OPC_CheckPredicate, + 70, + 12, + 0, + 0, // Skip to: 917 + /* 905 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 5, + 0, + 0, // Skip to: 917 + /* 912 */ MCD_OPC_Decode, + 227, + 5, + 197, + 3, // Opcode: CDE_CX3DA + /* 917 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableThumb2CoProc32[] = { -/* 0 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 3 */ MCD_OPC_FilterValue, 236, 1, 175, 0, 0, // Skip to: 184 -/* 9 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... -/* 12 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 33 -/* 17 */ MCD_OPC_CheckPredicate, 38, 191, 2, 0, // Skip to: 725 -/* 22 */ MCD_OPC_CheckField, 23, 1, 1, 184, 2, 0, // Skip to: 725 -/* 29 */ MCD_OPC_Decode, 216, 23, 90, // Opcode: t2STC_OPTION -/* 33 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 54 -/* 38 */ MCD_OPC_CheckPredicate, 38, 170, 2, 0, // Skip to: 725 -/* 43 */ MCD_OPC_CheckField, 23, 1, 1, 163, 2, 0, // Skip to: 725 -/* 50 */ MCD_OPC_Decode, 145, 22, 90, // Opcode: t2LDC_OPTION -/* 54 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 68 -/* 59 */ MCD_OPC_CheckPredicate, 38, 149, 2, 0, // Skip to: 725 -/* 64 */ MCD_OPC_Decode, 217, 23, 90, // Opcode: t2STC_POST -/* 68 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 82 -/* 73 */ MCD_OPC_CheckPredicate, 38, 135, 2, 0, // Skip to: 725 -/* 78 */ MCD_OPC_Decode, 146, 22, 90, // Opcode: t2LDC_POST -/* 82 */ MCD_OPC_FilterValue, 4, 32, 0, 0, // Skip to: 119 -/* 87 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 90 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 105 -/* 95 */ MCD_OPC_CheckPredicate, 38, 113, 2, 0, // Skip to: 725 -/* 100 */ MCD_OPC_Decode, 200, 22, 182, 2, // Opcode: t2MCRR -/* 105 */ MCD_OPC_FilterValue, 1, 103, 2, 0, // Skip to: 725 -/* 110 */ MCD_OPC_CheckPredicate, 38, 98, 2, 0, // Skip to: 725 -/* 115 */ MCD_OPC_Decode, 212, 23, 90, // Opcode: t2STCL_OPTION -/* 119 */ MCD_OPC_FilterValue, 5, 32, 0, 0, // Skip to: 156 -/* 124 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 127 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 142 -/* 132 */ MCD_OPC_CheckPredicate, 38, 76, 2, 0, // Skip to: 725 -/* 137 */ MCD_OPC_Decode, 212, 22, 183, 2, // Opcode: t2MRRC -/* 142 */ MCD_OPC_FilterValue, 1, 66, 2, 0, // Skip to: 725 -/* 147 */ MCD_OPC_CheckPredicate, 38, 61, 2, 0, // Skip to: 725 -/* 152 */ MCD_OPC_Decode, 141, 22, 90, // Opcode: t2LDCL_OPTION -/* 156 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 170 -/* 161 */ MCD_OPC_CheckPredicate, 38, 47, 2, 0, // Skip to: 725 -/* 166 */ MCD_OPC_Decode, 213, 23, 90, // Opcode: t2STCL_POST -/* 170 */ MCD_OPC_FilterValue, 7, 38, 2, 0, // Skip to: 725 -/* 175 */ MCD_OPC_CheckPredicate, 38, 33, 2, 0, // Skip to: 725 -/* 180 */ MCD_OPC_Decode, 142, 22, 90, // Opcode: t2LDCL_POST -/* 184 */ MCD_OPC_FilterValue, 237, 1, 115, 0, 0, // Skip to: 305 -/* 190 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... -/* 193 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 207 -/* 198 */ MCD_OPC_CheckPredicate, 38, 10, 2, 0, // Skip to: 725 -/* 203 */ MCD_OPC_Decode, 215, 23, 90, // Opcode: t2STC_OFFSET -/* 207 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 221 -/* 212 */ MCD_OPC_CheckPredicate, 38, 252, 1, 0, // Skip to: 725 -/* 217 */ MCD_OPC_Decode, 144, 22, 90, // Opcode: t2LDC_OFFSET -/* 221 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 235 -/* 226 */ MCD_OPC_CheckPredicate, 38, 238, 1, 0, // Skip to: 725 -/* 231 */ MCD_OPC_Decode, 218, 23, 90, // Opcode: t2STC_PRE -/* 235 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 249 -/* 240 */ MCD_OPC_CheckPredicate, 38, 224, 1, 0, // Skip to: 725 -/* 245 */ MCD_OPC_Decode, 147, 22, 90, // Opcode: t2LDC_PRE -/* 249 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 263 -/* 254 */ MCD_OPC_CheckPredicate, 38, 210, 1, 0, // Skip to: 725 -/* 259 */ MCD_OPC_Decode, 211, 23, 90, // Opcode: t2STCL_OFFSET -/* 263 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 277 -/* 268 */ MCD_OPC_CheckPredicate, 38, 196, 1, 0, // Skip to: 725 -/* 273 */ MCD_OPC_Decode, 140, 22, 90, // Opcode: t2LDCL_OFFSET -/* 277 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 291 -/* 282 */ MCD_OPC_CheckPredicate, 38, 182, 1, 0, // Skip to: 725 -/* 287 */ MCD_OPC_Decode, 214, 23, 90, // Opcode: t2STCL_PRE -/* 291 */ MCD_OPC_FilterValue, 7, 173, 1, 0, // Skip to: 725 -/* 296 */ MCD_OPC_CheckPredicate, 38, 168, 1, 0, // Skip to: 725 -/* 301 */ MCD_OPC_Decode, 143, 22, 90, // Opcode: t2LDCL_PRE -/* 305 */ MCD_OPC_FilterValue, 238, 1, 53, 0, 0, // Skip to: 364 -/* 311 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 314 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 328 -/* 319 */ MCD_OPC_CheckPredicate, 58, 145, 1, 0, // Skip to: 725 -/* 324 */ MCD_OPC_Decode, 219, 21, 91, // Opcode: t2CDP -/* 328 */ MCD_OPC_FilterValue, 1, 136, 1, 0, // Skip to: 725 -/* 333 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 336 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 350 -/* 341 */ MCD_OPC_CheckPredicate, 38, 123, 1, 0, // Skip to: 725 -/* 346 */ MCD_OPC_Decode, 198, 22, 93, // Opcode: t2MCR -/* 350 */ MCD_OPC_FilterValue, 1, 114, 1, 0, // Skip to: 725 -/* 355 */ MCD_OPC_CheckPredicate, 38, 109, 1, 0, // Skip to: 725 -/* 360 */ MCD_OPC_Decode, 210, 22, 95, // Opcode: t2MRC -/* 364 */ MCD_OPC_FilterValue, 252, 1, 175, 0, 0, // Skip to: 545 -/* 370 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... -/* 373 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 394 -/* 378 */ MCD_OPC_CheckPredicate, 59, 86, 1, 0, // Skip to: 725 -/* 383 */ MCD_OPC_CheckField, 23, 1, 1, 79, 1, 0, // Skip to: 725 -/* 390 */ MCD_OPC_Decode, 208, 23, 90, // Opcode: t2STC2_OPTION -/* 394 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 415 -/* 399 */ MCD_OPC_CheckPredicate, 59, 65, 1, 0, // Skip to: 725 -/* 404 */ MCD_OPC_CheckField, 23, 1, 1, 58, 1, 0, // Skip to: 725 -/* 411 */ MCD_OPC_Decode, 137, 22, 90, // Opcode: t2LDC2_OPTION -/* 415 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 429 -/* 420 */ MCD_OPC_CheckPredicate, 59, 44, 1, 0, // Skip to: 725 -/* 425 */ MCD_OPC_Decode, 209, 23, 90, // Opcode: t2STC2_POST -/* 429 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 443 -/* 434 */ MCD_OPC_CheckPredicate, 59, 30, 1, 0, // Skip to: 725 -/* 439 */ MCD_OPC_Decode, 138, 22, 90, // Opcode: t2LDC2_POST -/* 443 */ MCD_OPC_FilterValue, 4, 32, 0, 0, // Skip to: 480 -/* 448 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 451 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 466 -/* 456 */ MCD_OPC_CheckPredicate, 58, 8, 1, 0, // Skip to: 725 -/* 461 */ MCD_OPC_Decode, 201, 22, 182, 2, // Opcode: t2MCRR2 -/* 466 */ MCD_OPC_FilterValue, 1, 254, 0, 0, // Skip to: 725 -/* 471 */ MCD_OPC_CheckPredicate, 59, 249, 0, 0, // Skip to: 725 -/* 476 */ MCD_OPC_Decode, 204, 23, 90, // Opcode: t2STC2L_OPTION -/* 480 */ MCD_OPC_FilterValue, 5, 32, 0, 0, // Skip to: 517 -/* 485 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 488 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 503 -/* 493 */ MCD_OPC_CheckPredicate, 58, 227, 0, 0, // Skip to: 725 -/* 498 */ MCD_OPC_Decode, 213, 22, 183, 2, // Opcode: t2MRRC2 -/* 503 */ MCD_OPC_FilterValue, 1, 217, 0, 0, // Skip to: 725 -/* 508 */ MCD_OPC_CheckPredicate, 59, 212, 0, 0, // Skip to: 725 -/* 513 */ MCD_OPC_Decode, 133, 22, 90, // Opcode: t2LDC2L_OPTION -/* 517 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 531 -/* 522 */ MCD_OPC_CheckPredicate, 59, 198, 0, 0, // Skip to: 725 -/* 527 */ MCD_OPC_Decode, 205, 23, 90, // Opcode: t2STC2L_POST -/* 531 */ MCD_OPC_FilterValue, 7, 189, 0, 0, // Skip to: 725 -/* 536 */ MCD_OPC_CheckPredicate, 59, 184, 0, 0, // Skip to: 725 -/* 541 */ MCD_OPC_Decode, 134, 22, 90, // Opcode: t2LDC2L_POST -/* 545 */ MCD_OPC_FilterValue, 253, 1, 115, 0, 0, // Skip to: 666 -/* 551 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... -/* 554 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 568 -/* 559 */ MCD_OPC_CheckPredicate, 59, 161, 0, 0, // Skip to: 725 -/* 564 */ MCD_OPC_Decode, 207, 23, 90, // Opcode: t2STC2_OFFSET -/* 568 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 582 -/* 573 */ MCD_OPC_CheckPredicate, 59, 147, 0, 0, // Skip to: 725 -/* 578 */ MCD_OPC_Decode, 136, 22, 90, // Opcode: t2LDC2_OFFSET -/* 582 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 596 -/* 587 */ MCD_OPC_CheckPredicate, 59, 133, 0, 0, // Skip to: 725 -/* 592 */ MCD_OPC_Decode, 210, 23, 90, // Opcode: t2STC2_PRE -/* 596 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 610 -/* 601 */ MCD_OPC_CheckPredicate, 59, 119, 0, 0, // Skip to: 725 -/* 606 */ MCD_OPC_Decode, 139, 22, 90, // Opcode: t2LDC2_PRE -/* 610 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 624 -/* 615 */ MCD_OPC_CheckPredicate, 59, 105, 0, 0, // Skip to: 725 -/* 620 */ MCD_OPC_Decode, 203, 23, 90, // Opcode: t2STC2L_OFFSET -/* 624 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 638 -/* 629 */ MCD_OPC_CheckPredicate, 59, 91, 0, 0, // Skip to: 725 -/* 634 */ MCD_OPC_Decode, 132, 22, 90, // Opcode: t2LDC2L_OFFSET -/* 638 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 652 -/* 643 */ MCD_OPC_CheckPredicate, 59, 77, 0, 0, // Skip to: 725 -/* 648 */ MCD_OPC_Decode, 206, 23, 90, // Opcode: t2STC2L_PRE -/* 652 */ MCD_OPC_FilterValue, 7, 68, 0, 0, // Skip to: 725 -/* 657 */ MCD_OPC_CheckPredicate, 59, 63, 0, 0, // Skip to: 725 -/* 662 */ MCD_OPC_Decode, 135, 22, 90, // Opcode: t2LDC2L_PRE -/* 666 */ MCD_OPC_FilterValue, 254, 1, 53, 0, 0, // Skip to: 725 -/* 672 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 675 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 689 -/* 680 */ MCD_OPC_CheckPredicate, 58, 40, 0, 0, // Skip to: 725 -/* 685 */ MCD_OPC_Decode, 220, 21, 91, // Opcode: t2CDP2 -/* 689 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 725 -/* 694 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 697 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 711 -/* 702 */ MCD_OPC_CheckPredicate, 58, 18, 0, 0, // Skip to: 725 -/* 707 */ MCD_OPC_Decode, 199, 22, 93, // Opcode: t2MCR2 -/* 711 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 725 -/* 716 */ MCD_OPC_CheckPredicate, 58, 4, 0, 0, // Skip to: 725 -/* 721 */ MCD_OPC_Decode, 211, 22, 95, // Opcode: t2MRC2 -/* 725 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 3 */ MCD_OPC_FilterValue, + 236, + 1, + 175, + 0, + 0, // Skip to: 184 + /* 9 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 12 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 33 + /* 17 */ MCD_OPC_CheckPredicate, + 45, + 191, + 2, + 0, // Skip to: 725 + /* 22 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 184, + 2, + 0, // Skip to: 725 + /* 29 */ MCD_OPC_Decode, + 247, + 32, + 90, // Opcode: t2STC_OPTION + /* 33 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 54 + /* 38 */ MCD_OPC_CheckPredicate, + 45, + 170, + 2, + 0, // Skip to: 725 + /* 43 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 163, + 2, + 0, // Skip to: 725 + /* 50 */ MCD_OPC_Decode, + 173, + 31, + 90, // Opcode: t2LDC_OPTION + /* 54 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 68 + /* 59 */ MCD_OPC_CheckPredicate, + 45, + 149, + 2, + 0, // Skip to: 725 + /* 64 */ MCD_OPC_Decode, + 248, + 32, + 90, // Opcode: t2STC_POST + /* 68 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 82 + /* 73 */ MCD_OPC_CheckPredicate, + 45, + 135, + 2, + 0, // Skip to: 725 + /* 78 */ MCD_OPC_Decode, + 174, + 31, + 90, // Opcode: t2LDC_POST + /* 82 */ MCD_OPC_FilterValue, + 4, + 32, + 0, + 0, // Skip to: 119 + /* 87 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 90 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 105 + /* 95 */ MCD_OPC_CheckPredicate, + 45, + 113, + 2, + 0, // Skip to: 725 + /* 100 */ MCD_OPC_Decode, + 230, + 31, + 198, + 3, // Opcode: t2MCRR + /* 105 */ MCD_OPC_FilterValue, + 1, + 103, + 2, + 0, // Skip to: 725 + /* 110 */ MCD_OPC_CheckPredicate, + 45, + 98, + 2, + 0, // Skip to: 725 + /* 115 */ MCD_OPC_Decode, + 243, + 32, + 90, // Opcode: t2STCL_OPTION + /* 119 */ MCD_OPC_FilterValue, + 5, + 32, + 0, + 0, // Skip to: 156 + /* 124 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 127 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 142 + /* 132 */ MCD_OPC_CheckPredicate, + 45, + 76, + 2, + 0, // Skip to: 725 + /* 137 */ MCD_OPC_Decode, + 242, + 31, + 199, + 3, // Opcode: t2MRRC + /* 142 */ MCD_OPC_FilterValue, + 1, + 66, + 2, + 0, // Skip to: 725 + /* 147 */ MCD_OPC_CheckPredicate, + 45, + 61, + 2, + 0, // Skip to: 725 + /* 152 */ MCD_OPC_Decode, + 169, + 31, + 90, // Opcode: t2LDCL_OPTION + /* 156 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 170 + /* 161 */ MCD_OPC_CheckPredicate, + 45, + 47, + 2, + 0, // Skip to: 725 + /* 166 */ MCD_OPC_Decode, + 244, + 32, + 90, // Opcode: t2STCL_POST + /* 170 */ MCD_OPC_FilterValue, + 7, + 38, + 2, + 0, // Skip to: 725 + /* 175 */ MCD_OPC_CheckPredicate, + 45, + 33, + 2, + 0, // Skip to: 725 + /* 180 */ MCD_OPC_Decode, + 170, + 31, + 90, // Opcode: t2LDCL_POST + /* 184 */ MCD_OPC_FilterValue, + 237, + 1, + 115, + 0, + 0, // Skip to: 305 + /* 190 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 193 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 207 + /* 198 */ MCD_OPC_CheckPredicate, + 45, + 10, + 2, + 0, // Skip to: 725 + /* 203 */ MCD_OPC_Decode, + 246, + 32, + 90, // Opcode: t2STC_OFFSET + /* 207 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 221 + /* 212 */ MCD_OPC_CheckPredicate, + 45, + 252, + 1, + 0, // Skip to: 725 + /* 217 */ MCD_OPC_Decode, + 172, + 31, + 90, // Opcode: t2LDC_OFFSET + /* 221 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 235 + /* 226 */ MCD_OPC_CheckPredicate, + 45, + 238, + 1, + 0, // Skip to: 725 + /* 231 */ MCD_OPC_Decode, + 249, + 32, + 90, // Opcode: t2STC_PRE + /* 235 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 249 + /* 240 */ MCD_OPC_CheckPredicate, + 45, + 224, + 1, + 0, // Skip to: 725 + /* 245 */ MCD_OPC_Decode, + 175, + 31, + 90, // Opcode: t2LDC_PRE + /* 249 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 263 + /* 254 */ MCD_OPC_CheckPredicate, + 45, + 210, + 1, + 0, // Skip to: 725 + /* 259 */ MCD_OPC_Decode, + 242, + 32, + 90, // Opcode: t2STCL_OFFSET + /* 263 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 277 + /* 268 */ MCD_OPC_CheckPredicate, + 45, + 196, + 1, + 0, // Skip to: 725 + /* 273 */ MCD_OPC_Decode, + 168, + 31, + 90, // Opcode: t2LDCL_OFFSET + /* 277 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 291 + /* 282 */ MCD_OPC_CheckPredicate, + 45, + 182, + 1, + 0, // Skip to: 725 + /* 287 */ MCD_OPC_Decode, + 245, + 32, + 90, // Opcode: t2STCL_PRE + /* 291 */ MCD_OPC_FilterValue, + 7, + 173, + 1, + 0, // Skip to: 725 + /* 296 */ MCD_OPC_CheckPredicate, + 45, + 168, + 1, + 0, // Skip to: 725 + /* 301 */ MCD_OPC_Decode, + 171, + 31, + 90, // Opcode: t2LDCL_PRE + /* 305 */ MCD_OPC_FilterValue, + 238, + 1, + 53, + 0, + 0, // Skip to: 364 + /* 311 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 314 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 328 + /* 319 */ MCD_OPC_CheckPredicate, + 71, + 145, + 1, + 0, // Skip to: 725 + /* 324 */ MCD_OPC_Decode, + 241, + 30, + 91, // Opcode: t2CDP + /* 328 */ MCD_OPC_FilterValue, + 1, + 136, + 1, + 0, // Skip to: 725 + /* 333 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 336 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 350 + /* 341 */ MCD_OPC_CheckPredicate, + 45, + 123, + 1, + 0, // Skip to: 725 + /* 346 */ MCD_OPC_Decode, + 228, + 31, + 93, // Opcode: t2MCR + /* 350 */ MCD_OPC_FilterValue, + 1, + 114, + 1, + 0, // Skip to: 725 + /* 355 */ MCD_OPC_CheckPredicate, + 45, + 109, + 1, + 0, // Skip to: 725 + /* 360 */ MCD_OPC_Decode, + 240, + 31, + 95, // Opcode: t2MRC + /* 364 */ MCD_OPC_FilterValue, + 252, + 1, + 175, + 0, + 0, // Skip to: 545 + /* 370 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 373 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 394 + /* 378 */ MCD_OPC_CheckPredicate, + 72, + 86, + 1, + 0, // Skip to: 725 + /* 383 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 79, + 1, + 0, // Skip to: 725 + /* 390 */ MCD_OPC_Decode, + 239, + 32, + 90, // Opcode: t2STC2_OPTION + /* 394 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 415 + /* 399 */ MCD_OPC_CheckPredicate, + 72, + 65, + 1, + 0, // Skip to: 725 + /* 404 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 58, + 1, + 0, // Skip to: 725 + /* 411 */ MCD_OPC_Decode, + 165, + 31, + 90, // Opcode: t2LDC2_OPTION + /* 415 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 429 + /* 420 */ MCD_OPC_CheckPredicate, + 72, + 44, + 1, + 0, // Skip to: 725 + /* 425 */ MCD_OPC_Decode, + 240, + 32, + 90, // Opcode: t2STC2_POST + /* 429 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 443 + /* 434 */ MCD_OPC_CheckPredicate, + 72, + 30, + 1, + 0, // Skip to: 725 + /* 439 */ MCD_OPC_Decode, + 166, + 31, + 90, // Opcode: t2LDC2_POST + /* 443 */ MCD_OPC_FilterValue, + 4, + 32, + 0, + 0, // Skip to: 480 + /* 448 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 451 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 466 + /* 456 */ MCD_OPC_CheckPredicate, + 71, + 8, + 1, + 0, // Skip to: 725 + /* 461 */ MCD_OPC_Decode, + 231, + 31, + 198, + 3, // Opcode: t2MCRR2 + /* 466 */ MCD_OPC_FilterValue, + 1, + 254, + 0, + 0, // Skip to: 725 + /* 471 */ MCD_OPC_CheckPredicate, + 72, + 249, + 0, + 0, // Skip to: 725 + /* 476 */ MCD_OPC_Decode, + 235, + 32, + 90, // Opcode: t2STC2L_OPTION + /* 480 */ MCD_OPC_FilterValue, + 5, + 32, + 0, + 0, // Skip to: 517 + /* 485 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 488 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 503 + /* 493 */ MCD_OPC_CheckPredicate, + 71, + 227, + 0, + 0, // Skip to: 725 + /* 498 */ MCD_OPC_Decode, + 243, + 31, + 199, + 3, // Opcode: t2MRRC2 + /* 503 */ MCD_OPC_FilterValue, + 1, + 217, + 0, + 0, // Skip to: 725 + /* 508 */ MCD_OPC_CheckPredicate, + 72, + 212, + 0, + 0, // Skip to: 725 + /* 513 */ MCD_OPC_Decode, + 161, + 31, + 90, // Opcode: t2LDC2L_OPTION + /* 517 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 531 + /* 522 */ MCD_OPC_CheckPredicate, + 72, + 198, + 0, + 0, // Skip to: 725 + /* 527 */ MCD_OPC_Decode, + 236, + 32, + 90, // Opcode: t2STC2L_POST + /* 531 */ MCD_OPC_FilterValue, + 7, + 189, + 0, + 0, // Skip to: 725 + /* 536 */ MCD_OPC_CheckPredicate, + 72, + 184, + 0, + 0, // Skip to: 725 + /* 541 */ MCD_OPC_Decode, + 162, + 31, + 90, // Opcode: t2LDC2L_POST + /* 545 */ MCD_OPC_FilterValue, + 253, + 1, + 115, + 0, + 0, // Skip to: 666 + /* 551 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 554 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 568 + /* 559 */ MCD_OPC_CheckPredicate, + 72, + 161, + 0, + 0, // Skip to: 725 + /* 564 */ MCD_OPC_Decode, + 238, + 32, + 90, // Opcode: t2STC2_OFFSET + /* 568 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 582 + /* 573 */ MCD_OPC_CheckPredicate, + 72, + 147, + 0, + 0, // Skip to: 725 + /* 578 */ MCD_OPC_Decode, + 164, + 31, + 90, // Opcode: t2LDC2_OFFSET + /* 582 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 596 + /* 587 */ MCD_OPC_CheckPredicate, + 72, + 133, + 0, + 0, // Skip to: 725 + /* 592 */ MCD_OPC_Decode, + 241, + 32, + 90, // Opcode: t2STC2_PRE + /* 596 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 610 + /* 601 */ MCD_OPC_CheckPredicate, + 72, + 119, + 0, + 0, // Skip to: 725 + /* 606 */ MCD_OPC_Decode, + 167, + 31, + 90, // Opcode: t2LDC2_PRE + /* 610 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 624 + /* 615 */ MCD_OPC_CheckPredicate, + 72, + 105, + 0, + 0, // Skip to: 725 + /* 620 */ MCD_OPC_Decode, + 234, + 32, + 90, // Opcode: t2STC2L_OFFSET + /* 624 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 638 + /* 629 */ MCD_OPC_CheckPredicate, + 72, + 91, + 0, + 0, // Skip to: 725 + /* 634 */ MCD_OPC_Decode, + 160, + 31, + 90, // Opcode: t2LDC2L_OFFSET + /* 638 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 652 + /* 643 */ MCD_OPC_CheckPredicate, + 72, + 77, + 0, + 0, // Skip to: 725 + /* 648 */ MCD_OPC_Decode, + 237, + 32, + 90, // Opcode: t2STC2L_PRE + /* 652 */ MCD_OPC_FilterValue, + 7, + 68, + 0, + 0, // Skip to: 725 + /* 657 */ MCD_OPC_CheckPredicate, + 72, + 63, + 0, + 0, // Skip to: 725 + /* 662 */ MCD_OPC_Decode, + 163, + 31, + 90, // Opcode: t2LDC2L_PRE + /* 666 */ MCD_OPC_FilterValue, + 254, + 1, + 53, + 0, + 0, // Skip to: 725 + /* 672 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 675 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 689 + /* 680 */ MCD_OPC_CheckPredicate, + 71, + 40, + 0, + 0, // Skip to: 725 + /* 685 */ MCD_OPC_Decode, + 242, + 30, + 91, // Opcode: t2CDP2 + /* 689 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 725 + /* 694 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 697 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 711 + /* 702 */ MCD_OPC_CheckPredicate, + 71, + 18, + 0, + 0, // Skip to: 725 + /* 707 */ MCD_OPC_Decode, + 229, + 31, + 93, // Opcode: t2MCR2 + /* 711 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 725 + /* 716 */ MCD_OPC_CheckPredicate, + 71, + 4, + 0, + 0, // Skip to: 725 + /* 721 */ MCD_OPC_Decode, + 241, + 31, + 95, // Opcode: t2MRC2 + /* 725 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableThumbSBit16[] = { -/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... -/* 3 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18 -/* 8 */ MCD_OPC_CheckPredicate, 28, 95, 1, 0, // Skip to: 364 -/* 13 */ MCD_OPC_Decode, 232, 24, 184, 2, // Opcode: tLSLri -/* 18 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 33 -/* 23 */ MCD_OPC_CheckPredicate, 28, 80, 1, 0, // Skip to: 364 -/* 28 */ MCD_OPC_Decode, 234, 24, 184, 2, // Opcode: tLSRri -/* 33 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 48 -/* 38 */ MCD_OPC_CheckPredicate, 28, 65, 1, 0, // Skip to: 364 -/* 43 */ MCD_OPC_Decode, 196, 24, 184, 2, // Opcode: tASRri -/* 48 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 116 -/* 53 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 56 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71 -/* 61 */ MCD_OPC_CheckPredicate, 28, 42, 1, 0, // Skip to: 364 -/* 66 */ MCD_OPC_Decode, 191, 24, 185, 2, // Opcode: tADDrr -/* 71 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 86 -/* 76 */ MCD_OPC_CheckPredicate, 28, 27, 1, 0, // Skip to: 364 -/* 81 */ MCD_OPC_Decode, 134, 25, 185, 2, // Opcode: tSUBrr -/* 86 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 101 -/* 91 */ MCD_OPC_CheckPredicate, 28, 12, 1, 0, // Skip to: 364 -/* 96 */ MCD_OPC_Decode, 187, 24, 186, 2, // Opcode: tADDi3 -/* 101 */ MCD_OPC_FilterValue, 3, 2, 1, 0, // Skip to: 364 -/* 106 */ MCD_OPC_CheckPredicate, 28, 253, 0, 0, // Skip to: 364 -/* 111 */ MCD_OPC_Decode, 132, 25, 186, 2, // Opcode: tSUBi3 -/* 116 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 131 -/* 121 */ MCD_OPC_CheckPredicate, 28, 238, 0, 0, // Skip to: 364 -/* 126 */ MCD_OPC_Decode, 237, 24, 208, 1, // Opcode: tMOVi8 -/* 131 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 146 -/* 136 */ MCD_OPC_CheckPredicate, 28, 223, 0, 0, // Skip to: 364 -/* 141 */ MCD_OPC_Decode, 188, 24, 187, 2, // Opcode: tADDi8 -/* 146 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 161 -/* 151 */ MCD_OPC_CheckPredicate, 28, 208, 0, 0, // Skip to: 364 -/* 156 */ MCD_OPC_Decode, 133, 25, 187, 2, // Opcode: tSUBi8 -/* 161 */ MCD_OPC_FilterValue, 8, 198, 0, 0, // Skip to: 364 -/* 166 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 169 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 184 -/* 174 */ MCD_OPC_CheckPredicate, 28, 185, 0, 0, // Skip to: 364 -/* 179 */ MCD_OPC_Decode, 195, 24, 188, 2, // Opcode: tAND -/* 184 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 199 -/* 189 */ MCD_OPC_CheckPredicate, 28, 170, 0, 0, // Skip to: 364 -/* 194 */ MCD_OPC_Decode, 215, 24, 188, 2, // Opcode: tEOR -/* 199 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 214 -/* 204 */ MCD_OPC_CheckPredicate, 28, 155, 0, 0, // Skip to: 364 -/* 209 */ MCD_OPC_Decode, 233, 24, 188, 2, // Opcode: tLSLrr -/* 214 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 229 -/* 219 */ MCD_OPC_CheckPredicate, 28, 140, 0, 0, // Skip to: 364 -/* 224 */ MCD_OPC_Decode, 235, 24, 188, 2, // Opcode: tLSRrr -/* 229 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 244 -/* 234 */ MCD_OPC_CheckPredicate, 28, 125, 0, 0, // Skip to: 364 -/* 239 */ MCD_OPC_Decode, 197, 24, 188, 2, // Opcode: tASRrr -/* 244 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 259 -/* 249 */ MCD_OPC_CheckPredicate, 28, 110, 0, 0, // Skip to: 364 -/* 254 */ MCD_OPC_Decode, 185, 24, 188, 2, // Opcode: tADC -/* 259 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 274 -/* 264 */ MCD_OPC_CheckPredicate, 28, 95, 0, 0, // Skip to: 364 -/* 269 */ MCD_OPC_Decode, 250, 24, 188, 2, // Opcode: tSBC -/* 274 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 289 -/* 279 */ MCD_OPC_CheckPredicate, 28, 80, 0, 0, // Skip to: 364 -/* 284 */ MCD_OPC_Decode, 248, 24, 188, 2, // Opcode: tROR -/* 289 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 304 -/* 294 */ MCD_OPC_CheckPredicate, 28, 65, 0, 0, // Skip to: 364 -/* 299 */ MCD_OPC_Decode, 249, 24, 207, 1, // Opcode: tRSB -/* 304 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 319 -/* 309 */ MCD_OPC_CheckPredicate, 28, 50, 0, 0, // Skip to: 364 -/* 314 */ MCD_OPC_Decode, 241, 24, 188, 2, // Opcode: tORR -/* 319 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 334 -/* 324 */ MCD_OPC_CheckPredicate, 28, 35, 0, 0, // Skip to: 364 -/* 329 */ MCD_OPC_Decode, 239, 24, 189, 2, // Opcode: tMUL -/* 334 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 349 -/* 339 */ MCD_OPC_CheckPredicate, 28, 20, 0, 0, // Skip to: 364 -/* 344 */ MCD_OPC_Decode, 199, 24, 188, 2, // Opcode: tBIC -/* 349 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 364 -/* 354 */ MCD_OPC_CheckPredicate, 28, 5, 0, 0, // Skip to: 364 -/* 359 */ MCD_OPC_Decode, 240, 24, 207, 1, // Opcode: tMVN -/* 364 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, + 35, + 95, + 1, + 0, // Skip to: 364 + /* 13 */ MCD_OPC_Decode, + 138, + 34, + 200, + 3, // Opcode: tLSLri + /* 18 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, + 35, + 80, + 1, + 0, // Skip to: 364 + /* 28 */ MCD_OPC_Decode, + 140, + 34, + 200, + 3, // Opcode: tLSRri + /* 33 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 48 + /* 38 */ MCD_OPC_CheckPredicate, + 35, + 65, + 1, + 0, // Skip to: 364 + /* 43 */ MCD_OPC_Decode, + 230, + 33, + 200, + 3, // Opcode: tASRri + /* 48 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 116 + /* 53 */ MCD_OPC_ExtractField, + 9, + 2, // Inst{10-9} ... + /* 56 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 71 + /* 61 */ MCD_OPC_CheckPredicate, + 35, + 42, + 1, + 0, // Skip to: 364 + /* 66 */ MCD_OPC_Decode, + 225, + 33, + 201, + 3, // Opcode: tADDrr + /* 71 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 86 + /* 76 */ MCD_OPC_CheckPredicate, + 35, + 27, + 1, + 0, // Skip to: 364 + /* 81 */ MCD_OPC_Decode, + 168, + 34, + 201, + 3, // Opcode: tSUBrr + /* 86 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 101 + /* 91 */ MCD_OPC_CheckPredicate, + 35, + 12, + 1, + 0, // Skip to: 364 + /* 96 */ MCD_OPC_Decode, + 221, + 33, + 202, + 3, // Opcode: tADDi3 + /* 101 */ MCD_OPC_FilterValue, + 3, + 2, + 1, + 0, // Skip to: 364 + /* 106 */ MCD_OPC_CheckPredicate, + 35, + 253, + 0, + 0, // Skip to: 364 + /* 111 */ MCD_OPC_Decode, + 166, + 34, + 202, + 3, // Opcode: tSUBi3 + /* 116 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 131 + /* 121 */ MCD_OPC_CheckPredicate, + 35, + 238, + 0, + 0, // Skip to: 364 + /* 126 */ MCD_OPC_Decode, + 143, + 34, + 183, + 2, // Opcode: tMOVi8 + /* 131 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 146 + /* 136 */ MCD_OPC_CheckPredicate, + 35, + 223, + 0, + 0, // Skip to: 364 + /* 141 */ MCD_OPC_Decode, + 222, + 33, + 203, + 3, // Opcode: tADDi8 + /* 146 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 161 + /* 151 */ MCD_OPC_CheckPredicate, + 35, + 208, + 0, + 0, // Skip to: 364 + /* 156 */ MCD_OPC_Decode, + 167, + 34, + 203, + 3, // Opcode: tSUBi8 + /* 161 */ MCD_OPC_FilterValue, + 8, + 198, + 0, + 0, // Skip to: 364 + /* 166 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 169 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 184 + /* 174 */ MCD_OPC_CheckPredicate, + 35, + 185, + 0, + 0, // Skip to: 364 + /* 179 */ MCD_OPC_Decode, + 229, + 33, + 204, + 3, // Opcode: tAND + /* 184 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 199 + /* 189 */ MCD_OPC_CheckPredicate, + 35, + 170, + 0, + 0, // Skip to: 364 + /* 194 */ MCD_OPC_Decode, + 249, + 33, + 204, + 3, // Opcode: tEOR + /* 199 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 214 + /* 204 */ MCD_OPC_CheckPredicate, + 35, + 155, + 0, + 0, // Skip to: 364 + /* 209 */ MCD_OPC_Decode, + 139, + 34, + 204, + 3, // Opcode: tLSLrr + /* 214 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 229 + /* 219 */ MCD_OPC_CheckPredicate, + 35, + 140, + 0, + 0, // Skip to: 364 + /* 224 */ MCD_OPC_Decode, + 141, + 34, + 204, + 3, // Opcode: tLSRrr + /* 229 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 244 + /* 234 */ MCD_OPC_CheckPredicate, + 35, + 125, + 0, + 0, // Skip to: 364 + /* 239 */ MCD_OPC_Decode, + 231, + 33, + 204, + 3, // Opcode: tASRrr + /* 244 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 259 + /* 249 */ MCD_OPC_CheckPredicate, + 35, + 110, + 0, + 0, // Skip to: 364 + /* 254 */ MCD_OPC_Decode, + 219, + 33, + 204, + 3, // Opcode: tADC + /* 259 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 274 + /* 264 */ MCD_OPC_CheckPredicate, + 35, + 95, + 0, + 0, // Skip to: 364 + /* 269 */ MCD_OPC_Decode, + 156, + 34, + 204, + 3, // Opcode: tSBC + /* 274 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 289 + /* 279 */ MCD_OPC_CheckPredicate, + 35, + 80, + 0, + 0, // Skip to: 364 + /* 284 */ MCD_OPC_Decode, + 154, + 34, + 204, + 3, // Opcode: tROR + /* 289 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 304 + /* 294 */ MCD_OPC_CheckPredicate, + 35, + 65, + 0, + 0, // Skip to: 364 + /* 299 */ MCD_OPC_Decode, + 155, + 34, + 182, + 2, // Opcode: tRSB + /* 304 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 319 + /* 309 */ MCD_OPC_CheckPredicate, + 35, + 50, + 0, + 0, // Skip to: 364 + /* 314 */ MCD_OPC_Decode, + 147, + 34, + 204, + 3, // Opcode: tORR + /* 319 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 334 + /* 324 */ MCD_OPC_CheckPredicate, + 35, + 35, + 0, + 0, // Skip to: 364 + /* 329 */ MCD_OPC_Decode, + 145, + 34, + 205, + 3, // Opcode: tMUL + /* 334 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 349 + /* 339 */ MCD_OPC_CheckPredicate, + 35, + 20, + 0, + 0, // Skip to: 364 + /* 344 */ MCD_OPC_Decode, + 233, + 33, + 204, + 3, // Opcode: tBIC + /* 349 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 364 + /* 354 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 364 + /* 359 */ MCD_OPC_Decode, + 146, + 34, + 182, + 2, // Opcode: tMVN + /* 364 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableVFP32[] = { -/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 3 */ MCD_OPC_FilterValue, 0, 21, 2, 0, // Skip to: 541 -/* 8 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 11 */ MCD_OPC_FilterValue, 9, 130, 0, 0, // Skip to: 146 -/* 16 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 19 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 34 -/* 24 */ MCD_OPC_CheckPredicate, 60, 247, 16, 0, // Skip to: 4372 -/* 29 */ MCD_OPC_Decode, 205, 20, 190, 2, // Opcode: VSTRH -/* 34 */ MCD_OPC_FilterValue, 14, 237, 16, 0, // Skip to: 4372 -/* 39 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 42 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 110 -/* 47 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 50 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 88 -/* 55 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 58 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73 -/* 63 */ MCD_OPC_CheckPredicate, 60, 208, 16, 0, // Skip to: 4372 -/* 68 */ MCD_OPC_Decode, 203, 13, 191, 2, // Opcode: VMLAH -/* 73 */ MCD_OPC_FilterValue, 1, 198, 16, 0, // Skip to: 4372 -/* 78 */ MCD_OPC_CheckPredicate, 60, 193, 16, 0, // Skip to: 4372 -/* 83 */ MCD_OPC_Decode, 254, 9, 192, 2, // Opcode: VDIVH -/* 88 */ MCD_OPC_FilterValue, 1, 183, 16, 0, // Skip to: 4372 -/* 93 */ MCD_OPC_CheckPredicate, 60, 178, 16, 0, // Skip to: 4372 -/* 98 */ MCD_OPC_CheckField, 23, 1, 0, 171, 16, 0, // Skip to: 4372 -/* 105 */ MCD_OPC_Decode, 234, 13, 191, 2, // Opcode: VMLSH -/* 110 */ MCD_OPC_FilterValue, 1, 161, 16, 0, // Skip to: 4372 -/* 115 */ MCD_OPC_CheckPredicate, 60, 156, 16, 0, // Skip to: 4372 -/* 120 */ MCD_OPC_CheckField, 22, 2, 0, 149, 16, 0, // Skip to: 4372 -/* 127 */ MCD_OPC_CheckField, 5, 2, 0, 142, 16, 0, // Skip to: 4372 -/* 134 */ MCD_OPC_CheckField, 0, 4, 0, 135, 16, 0, // Skip to: 4372 -/* 141 */ MCD_OPC_Decode, 139, 14, 193, 2, // Opcode: VMOVHR -/* 146 */ MCD_OPC_FilterValue, 10, 189, 0, 0, // Skip to: 340 -/* 151 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 154 */ MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 213 -/* 159 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 162 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 198 -/* 167 */ MCD_OPC_CheckPredicate, 27, 104, 16, 0, // Skip to: 4372 -/* 172 */ MCD_OPC_CheckField, 22, 1, 1, 97, 16, 0, // Skip to: 4372 -/* 179 */ MCD_OPC_CheckField, 6, 2, 0, 90, 16, 0, // Skip to: 4372 -/* 186 */ MCD_OPC_CheckField, 4, 1, 1, 83, 16, 0, // Skip to: 4372 -/* 193 */ MCD_OPC_Decode, 155, 14, 194, 2, // Opcode: VMOVSRR -/* 198 */ MCD_OPC_FilterValue, 1, 73, 16, 0, // Skip to: 4372 -/* 203 */ MCD_OPC_CheckPredicate, 27, 68, 16, 0, // Skip to: 4372 -/* 208 */ MCD_OPC_Decode, 202, 20, 195, 2, // Opcode: VSTMSIA -/* 213 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 228 -/* 218 */ MCD_OPC_CheckPredicate, 27, 53, 16, 0, // Skip to: 4372 -/* 223 */ MCD_OPC_Decode, 206, 20, 196, 2, // Opcode: VSTRS -/* 228 */ MCD_OPC_FilterValue, 14, 43, 16, 0, // Skip to: 4372 -/* 233 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 236 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 304 -/* 241 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 244 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 282 -/* 249 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 252 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 267 -/* 257 */ MCD_OPC_CheckPredicate, 27, 14, 16, 0, // Skip to: 4372 -/* 262 */ MCD_OPC_Decode, 214, 13, 197, 2, // Opcode: VMLAS -/* 267 */ MCD_OPC_FilterValue, 1, 4, 16, 0, // Skip to: 4372 -/* 272 */ MCD_OPC_CheckPredicate, 27, 255, 15, 0, // Skip to: 4372 -/* 277 */ MCD_OPC_Decode, 255, 9, 198, 2, // Opcode: VDIVS -/* 282 */ MCD_OPC_FilterValue, 1, 245, 15, 0, // Skip to: 4372 -/* 287 */ MCD_OPC_CheckPredicate, 27, 240, 15, 0, // Skip to: 4372 -/* 292 */ MCD_OPC_CheckField, 23, 1, 0, 233, 15, 0, // Skip to: 4372 -/* 299 */ MCD_OPC_Decode, 245, 13, 197, 2, // Opcode: VMLSS -/* 304 */ MCD_OPC_FilterValue, 1, 223, 15, 0, // Skip to: 4372 -/* 309 */ MCD_OPC_CheckPredicate, 27, 218, 15, 0, // Skip to: 4372 -/* 314 */ MCD_OPC_CheckField, 22, 2, 0, 211, 15, 0, // Skip to: 4372 -/* 321 */ MCD_OPC_CheckField, 5, 2, 0, 204, 15, 0, // Skip to: 4372 -/* 328 */ MCD_OPC_CheckField, 0, 4, 0, 197, 15, 0, // Skip to: 4372 -/* 335 */ MCD_OPC_Decode, 154, 14, 199, 2, // Opcode: VMOVSR -/* 340 */ MCD_OPC_FilterValue, 11, 187, 15, 0, // Skip to: 4372 -/* 345 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 348 */ MCD_OPC_FilterValue, 12, 84, 0, 0, // Skip to: 437 -/* 353 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 356 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 392 -/* 361 */ MCD_OPC_CheckPredicate, 27, 166, 15, 0, // Skip to: 4372 -/* 366 */ MCD_OPC_CheckField, 22, 1, 1, 159, 15, 0, // Skip to: 4372 -/* 373 */ MCD_OPC_CheckField, 6, 2, 0, 152, 15, 0, // Skip to: 4372 -/* 380 */ MCD_OPC_CheckField, 4, 1, 1, 145, 15, 0, // Skip to: 4372 -/* 387 */ MCD_OPC_Decode, 137, 14, 200, 2, // Opcode: VMOVDRR -/* 392 */ MCD_OPC_FilterValue, 1, 135, 15, 0, // Skip to: 4372 -/* 397 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 400 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 415 -/* 405 */ MCD_OPC_CheckPredicate, 27, 122, 15, 0, // Skip to: 4372 -/* 410 */ MCD_OPC_Decode, 198, 20, 201, 2, // Opcode: VSTMDIA -/* 415 */ MCD_OPC_FilterValue, 1, 112, 15, 0, // Skip to: 4372 -/* 420 */ MCD_OPC_CheckPredicate, 27, 107, 15, 0, // Skip to: 4372 -/* 425 */ MCD_OPC_CheckField, 22, 1, 0, 100, 15, 0, // Skip to: 4372 -/* 432 */ MCD_OPC_Decode, 216, 4, 202, 2, // Opcode: FSTMXIA -/* 437 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 452 -/* 442 */ MCD_OPC_CheckPredicate, 27, 85, 15, 0, // Skip to: 4372 -/* 447 */ MCD_OPC_Decode, 204, 20, 203, 2, // Opcode: VSTRD -/* 452 */ MCD_OPC_FilterValue, 14, 75, 15, 0, // Skip to: 4372 -/* 457 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 460 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 512 -/* 465 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 468 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 490 -/* 473 */ MCD_OPC_CheckPredicate, 61, 54, 15, 0, // Skip to: 4372 -/* 478 */ MCD_OPC_CheckField, 4, 1, 0, 47, 15, 0, // Skip to: 4372 -/* 485 */ MCD_OPC_Decode, 202, 13, 204, 2, // Opcode: VMLAD -/* 490 */ MCD_OPC_FilterValue, 1, 37, 15, 0, // Skip to: 4372 -/* 495 */ MCD_OPC_CheckPredicate, 61, 32, 15, 0, // Skip to: 4372 -/* 500 */ MCD_OPC_CheckField, 4, 1, 0, 25, 15, 0, // Skip to: 4372 -/* 507 */ MCD_OPC_Decode, 253, 9, 205, 2, // Opcode: VDIVD -/* 512 */ MCD_OPC_FilterValue, 1, 15, 15, 0, // Skip to: 4372 -/* 517 */ MCD_OPC_CheckPredicate, 61, 10, 15, 0, // Skip to: 4372 -/* 522 */ MCD_OPC_CheckField, 23, 1, 0, 3, 15, 0, // Skip to: 4372 -/* 529 */ MCD_OPC_CheckField, 4, 1, 0, 252, 14, 0, // Skip to: 4372 -/* 536 */ MCD_OPC_Decode, 233, 13, 204, 2, // Opcode: VMLSD -/* 541 */ MCD_OPC_FilterValue, 1, 76, 2, 0, // Skip to: 1134 -/* 546 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 549 */ MCD_OPC_FilterValue, 9, 146, 0, 0, // Skip to: 700 -/* 554 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 557 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 572 -/* 562 */ MCD_OPC_CheckPredicate, 60, 221, 14, 0, // Skip to: 4372 -/* 567 */ MCD_OPC_Decode, 152, 13, 190, 2, // Opcode: VLDRH -/* 572 */ MCD_OPC_FilterValue, 14, 211, 14, 0, // Skip to: 4372 -/* 577 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 580 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 664 -/* 585 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 588 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 626 -/* 593 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 596 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 611 -/* 601 */ MCD_OPC_CheckPredicate, 60, 182, 14, 0, // Skip to: 4372 -/* 606 */ MCD_OPC_Decode, 237, 14, 191, 2, // Opcode: VNMLSH -/* 611 */ MCD_OPC_FilterValue, 1, 172, 14, 0, // Skip to: 4372 -/* 616 */ MCD_OPC_CheckPredicate, 60, 167, 14, 0, // Skip to: 4372 -/* 621 */ MCD_OPC_Decode, 167, 10, 191, 2, // Opcode: VFNMSH -/* 626 */ MCD_OPC_FilterValue, 1, 157, 14, 0, // Skip to: 4372 -/* 631 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 634 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 649 -/* 639 */ MCD_OPC_CheckPredicate, 60, 144, 14, 0, // Skip to: 4372 -/* 644 */ MCD_OPC_Decode, 234, 14, 191, 2, // Opcode: VNMLAH -/* 649 */ MCD_OPC_FilterValue, 1, 134, 14, 0, // Skip to: 4372 -/* 654 */ MCD_OPC_CheckPredicate, 60, 129, 14, 0, // Skip to: 4372 -/* 659 */ MCD_OPC_Decode, 164, 10, 191, 2, // Opcode: VFNMAH -/* 664 */ MCD_OPC_FilterValue, 1, 119, 14, 0, // Skip to: 4372 -/* 669 */ MCD_OPC_CheckPredicate, 60, 114, 14, 0, // Skip to: 4372 -/* 674 */ MCD_OPC_CheckField, 22, 2, 0, 107, 14, 0, // Skip to: 4372 -/* 681 */ MCD_OPC_CheckField, 5, 2, 0, 100, 14, 0, // Skip to: 4372 -/* 688 */ MCD_OPC_CheckField, 0, 4, 0, 93, 14, 0, // Skip to: 4372 -/* 695 */ MCD_OPC_Decode, 149, 14, 206, 2, // Opcode: VMOVRH -/* 700 */ MCD_OPC_FilterValue, 10, 205, 0, 0, // Skip to: 910 -/* 705 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 708 */ MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 767 -/* 713 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 716 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 752 -/* 721 */ MCD_OPC_CheckPredicate, 27, 62, 14, 0, // Skip to: 4372 -/* 726 */ MCD_OPC_CheckField, 22, 1, 1, 55, 14, 0, // Skip to: 4372 -/* 733 */ MCD_OPC_CheckField, 6, 2, 0, 48, 14, 0, // Skip to: 4372 -/* 740 */ MCD_OPC_CheckField, 4, 1, 1, 41, 14, 0, // Skip to: 4372 -/* 747 */ MCD_OPC_Decode, 151, 14, 207, 2, // Opcode: VMOVRRS -/* 752 */ MCD_OPC_FilterValue, 1, 31, 14, 0, // Skip to: 4372 -/* 757 */ MCD_OPC_CheckPredicate, 27, 26, 14, 0, // Skip to: 4372 -/* 762 */ MCD_OPC_Decode, 149, 13, 195, 2, // Opcode: VLDMSIA -/* 767 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 782 -/* 772 */ MCD_OPC_CheckPredicate, 27, 11, 14, 0, // Skip to: 4372 -/* 777 */ MCD_OPC_Decode, 153, 13, 196, 2, // Opcode: VLDRS -/* 782 */ MCD_OPC_FilterValue, 14, 1, 14, 0, // Skip to: 4372 -/* 787 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 790 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 874 -/* 795 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 798 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 836 -/* 803 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 806 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 821 -/* 811 */ MCD_OPC_CheckPredicate, 27, 228, 13, 0, // Skip to: 4372 -/* 816 */ MCD_OPC_Decode, 238, 14, 197, 2, // Opcode: VNMLSS -/* 821 */ MCD_OPC_FilterValue, 1, 218, 13, 0, // Skip to: 4372 -/* 826 */ MCD_OPC_CheckPredicate, 62, 213, 13, 0, // Skip to: 4372 -/* 831 */ MCD_OPC_Decode, 168, 10, 197, 2, // Opcode: VFNMSS -/* 836 */ MCD_OPC_FilterValue, 1, 203, 13, 0, // Skip to: 4372 -/* 841 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 844 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 859 -/* 849 */ MCD_OPC_CheckPredicate, 27, 190, 13, 0, // Skip to: 4372 -/* 854 */ MCD_OPC_Decode, 235, 14, 197, 2, // Opcode: VNMLAS -/* 859 */ MCD_OPC_FilterValue, 1, 180, 13, 0, // Skip to: 4372 -/* 864 */ MCD_OPC_CheckPredicate, 62, 175, 13, 0, // Skip to: 4372 -/* 869 */ MCD_OPC_Decode, 165, 10, 197, 2, // Opcode: VFNMAS -/* 874 */ MCD_OPC_FilterValue, 1, 165, 13, 0, // Skip to: 4372 -/* 879 */ MCD_OPC_CheckPredicate, 27, 160, 13, 0, // Skip to: 4372 -/* 884 */ MCD_OPC_CheckField, 22, 2, 0, 153, 13, 0, // Skip to: 4372 -/* 891 */ MCD_OPC_CheckField, 5, 2, 0, 146, 13, 0, // Skip to: 4372 -/* 898 */ MCD_OPC_CheckField, 0, 4, 0, 139, 13, 0, // Skip to: 4372 -/* 905 */ MCD_OPC_Decode, 152, 14, 208, 2, // Opcode: VMOVRS -/* 910 */ MCD_OPC_FilterValue, 11, 129, 13, 0, // Skip to: 4372 -/* 915 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 918 */ MCD_OPC_FilterValue, 12, 84, 0, 0, // Skip to: 1007 -/* 923 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 926 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 962 -/* 931 */ MCD_OPC_CheckPredicate, 27, 108, 13, 0, // Skip to: 4372 -/* 936 */ MCD_OPC_CheckField, 22, 1, 1, 101, 13, 0, // Skip to: 4372 -/* 943 */ MCD_OPC_CheckField, 6, 2, 0, 94, 13, 0, // Skip to: 4372 -/* 950 */ MCD_OPC_CheckField, 4, 1, 1, 87, 13, 0, // Skip to: 4372 -/* 957 */ MCD_OPC_Decode, 150, 14, 209, 2, // Opcode: VMOVRRD -/* 962 */ MCD_OPC_FilterValue, 1, 77, 13, 0, // Skip to: 4372 -/* 967 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 970 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 985 -/* 975 */ MCD_OPC_CheckPredicate, 27, 64, 13, 0, // Skip to: 4372 -/* 980 */ MCD_OPC_Decode, 145, 13, 201, 2, // Opcode: VLDMDIA -/* 985 */ MCD_OPC_FilterValue, 1, 54, 13, 0, // Skip to: 4372 -/* 990 */ MCD_OPC_CheckPredicate, 27, 49, 13, 0, // Skip to: 4372 -/* 995 */ MCD_OPC_CheckField, 22, 1, 0, 42, 13, 0, // Skip to: 4372 -/* 1002 */ MCD_OPC_Decode, 212, 4, 202, 2, // Opcode: FLDMXIA -/* 1007 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1022 -/* 1012 */ MCD_OPC_CheckPredicate, 27, 27, 13, 0, // Skip to: 4372 -/* 1017 */ MCD_OPC_Decode, 151, 13, 203, 2, // Opcode: VLDRD -/* 1022 */ MCD_OPC_FilterValue, 14, 17, 13, 0, // Skip to: 4372 -/* 1027 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1030 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1082 -/* 1035 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 1038 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1060 -/* 1043 */ MCD_OPC_CheckPredicate, 61, 252, 12, 0, // Skip to: 4372 -/* 1048 */ MCD_OPC_CheckField, 4, 1, 0, 245, 12, 0, // Skip to: 4372 -/* 1055 */ MCD_OPC_Decode, 236, 14, 204, 2, // Opcode: VNMLSD -/* 1060 */ MCD_OPC_FilterValue, 1, 235, 12, 0, // Skip to: 4372 -/* 1065 */ MCD_OPC_CheckPredicate, 63, 230, 12, 0, // Skip to: 4372 -/* 1070 */ MCD_OPC_CheckField, 4, 1, 0, 223, 12, 0, // Skip to: 4372 -/* 1077 */ MCD_OPC_Decode, 166, 10, 204, 2, // Opcode: VFNMSD -/* 1082 */ MCD_OPC_FilterValue, 1, 213, 12, 0, // Skip to: 4372 -/* 1087 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 1090 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1112 -/* 1095 */ MCD_OPC_CheckPredicate, 61, 200, 12, 0, // Skip to: 4372 -/* 1100 */ MCD_OPC_CheckField, 4, 1, 0, 193, 12, 0, // Skip to: 4372 -/* 1107 */ MCD_OPC_Decode, 233, 14, 204, 2, // Opcode: VNMLAD -/* 1112 */ MCD_OPC_FilterValue, 1, 183, 12, 0, // Skip to: 4372 -/* 1117 */ MCD_OPC_CheckPredicate, 63, 178, 12, 0, // Skip to: 4372 -/* 1122 */ MCD_OPC_CheckField, 4, 1, 0, 171, 12, 0, // Skip to: 4372 -/* 1129 */ MCD_OPC_Decode, 163, 10, 204, 2, // Opcode: VFNMAD -/* 1134 */ MCD_OPC_FilterValue, 2, 132, 2, 0, // Skip to: 1783 -/* 1139 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... -/* 1142 */ MCD_OPC_FilterValue, 24, 25, 0, 0, // Skip to: 1172 -/* 1147 */ MCD_OPC_CheckPredicate, 64, 148, 12, 0, // Skip to: 4372 -/* 1152 */ MCD_OPC_CheckField, 22, 1, 0, 141, 12, 0, // Skip to: 4372 -/* 1159 */ MCD_OPC_CheckField, 0, 16, 128, 20, 133, 12, 0, // Skip to: 4372 -/* 1167 */ MCD_OPC_Decode, 155, 13, 210, 2, // Opcode: VLSTM -/* 1172 */ MCD_OPC_FilterValue, 25, 63, 0, 0, // Skip to: 1240 -/* 1177 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1180 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1195 -/* 1185 */ MCD_OPC_CheckPredicate, 27, 110, 12, 0, // Skip to: 4372 -/* 1190 */ MCD_OPC_Decode, 203, 20, 211, 2, // Opcode: VSTMSIA_UPD -/* 1195 */ MCD_OPC_FilterValue, 11, 100, 12, 0, // Skip to: 4372 -/* 1200 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 1203 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1218 -/* 1208 */ MCD_OPC_CheckPredicate, 27, 87, 12, 0, // Skip to: 4372 -/* 1213 */ MCD_OPC_Decode, 199, 20, 212, 2, // Opcode: VSTMDIA_UPD -/* 1218 */ MCD_OPC_FilterValue, 1, 77, 12, 0, // Skip to: 4372 -/* 1223 */ MCD_OPC_CheckPredicate, 27, 72, 12, 0, // Skip to: 4372 -/* 1228 */ MCD_OPC_CheckField, 22, 1, 0, 65, 12, 0, // Skip to: 4372 -/* 1235 */ MCD_OPC_Decode, 217, 4, 213, 2, // Opcode: FSTMXIA_UPD -/* 1240 */ MCD_OPC_FilterValue, 26, 63, 0, 0, // Skip to: 1308 -/* 1245 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1248 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1263 -/* 1253 */ MCD_OPC_CheckPredicate, 27, 42, 12, 0, // Skip to: 4372 -/* 1258 */ MCD_OPC_Decode, 201, 20, 211, 2, // Opcode: VSTMSDB_UPD -/* 1263 */ MCD_OPC_FilterValue, 11, 32, 12, 0, // Skip to: 4372 -/* 1268 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 1271 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1286 -/* 1276 */ MCD_OPC_CheckPredicate, 27, 19, 12, 0, // Skip to: 4372 -/* 1281 */ MCD_OPC_Decode, 197, 20, 212, 2, // Opcode: VSTMDDB_UPD -/* 1286 */ MCD_OPC_FilterValue, 1, 9, 12, 0, // Skip to: 4372 -/* 1291 */ MCD_OPC_CheckPredicate, 27, 4, 12, 0, // Skip to: 4372 -/* 1296 */ MCD_OPC_CheckField, 22, 1, 0, 253, 11, 0, // Skip to: 4372 -/* 1303 */ MCD_OPC_Decode, 215, 4, 213, 2, // Opcode: FSTMXDB_UPD -/* 1308 */ MCD_OPC_FilterValue, 28, 159, 0, 0, // Skip to: 1472 -/* 1313 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1316 */ MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 1368 -/* 1321 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1324 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1346 -/* 1329 */ MCD_OPC_CheckPredicate, 60, 222, 11, 0, // Skip to: 4372 -/* 1334 */ MCD_OPC_CheckField, 4, 1, 0, 215, 11, 0, // Skip to: 4372 -/* 1341 */ MCD_OPC_Decode, 180, 14, 192, 2, // Opcode: VMULH -/* 1346 */ MCD_OPC_FilterValue, 1, 205, 11, 0, // Skip to: 4372 -/* 1351 */ MCD_OPC_CheckPredicate, 60, 200, 11, 0, // Skip to: 4372 -/* 1356 */ MCD_OPC_CheckField, 4, 1, 0, 193, 11, 0, // Skip to: 4372 -/* 1363 */ MCD_OPC_Decode, 240, 14, 192, 2, // Opcode: VNMULH -/* 1368 */ MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 1420 -/* 1373 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1376 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1398 -/* 1381 */ MCD_OPC_CheckPredicate, 27, 170, 11, 0, // Skip to: 4372 -/* 1386 */ MCD_OPC_CheckField, 4, 1, 0, 163, 11, 0, // Skip to: 4372 -/* 1393 */ MCD_OPC_Decode, 193, 14, 198, 2, // Opcode: VMULS -/* 1398 */ MCD_OPC_FilterValue, 1, 153, 11, 0, // Skip to: 4372 -/* 1403 */ MCD_OPC_CheckPredicate, 27, 148, 11, 0, // Skip to: 4372 -/* 1408 */ MCD_OPC_CheckField, 4, 1, 0, 141, 11, 0, // Skip to: 4372 -/* 1415 */ MCD_OPC_Decode, 241, 14, 198, 2, // Opcode: VNMULS -/* 1420 */ MCD_OPC_FilterValue, 11, 131, 11, 0, // Skip to: 4372 -/* 1425 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1428 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1450 -/* 1433 */ MCD_OPC_CheckPredicate, 61, 118, 11, 0, // Skip to: 4372 -/* 1438 */ MCD_OPC_CheckField, 4, 1, 0, 111, 11, 0, // Skip to: 4372 -/* 1445 */ MCD_OPC_Decode, 179, 14, 205, 2, // Opcode: VMULD -/* 1450 */ MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 4372 -/* 1455 */ MCD_OPC_CheckPredicate, 61, 96, 11, 0, // Skip to: 4372 -/* 1460 */ MCD_OPC_CheckField, 4, 1, 0, 89, 11, 0, // Skip to: 4372 -/* 1467 */ MCD_OPC_Decode, 239, 14, 205, 2, // Opcode: VNMULD -/* 1472 */ MCD_OPC_FilterValue, 29, 79, 11, 0, // Skip to: 4372 -/* 1477 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1480 */ MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 1532 -/* 1485 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1488 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1510 -/* 1493 */ MCD_OPC_CheckPredicate, 60, 58, 11, 0, // Skip to: 4372 -/* 1498 */ MCD_OPC_CheckField, 4, 1, 0, 51, 11, 0, // Skip to: 4372 -/* 1505 */ MCD_OPC_Decode, 150, 10, 191, 2, // Opcode: VFMAH -/* 1510 */ MCD_OPC_FilterValue, 1, 41, 11, 0, // Skip to: 4372 -/* 1515 */ MCD_OPC_CheckPredicate, 60, 36, 11, 0, // Skip to: 4372 -/* 1520 */ MCD_OPC_CheckField, 4, 1, 0, 29, 11, 0, // Skip to: 4372 -/* 1527 */ MCD_OPC_Decode, 157, 10, 191, 2, // Opcode: VFMSH -/* 1532 */ MCD_OPC_FilterValue, 10, 194, 0, 0, // Skip to: 1731 -/* 1537 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1540 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1578 -/* 1545 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1548 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1563 -/* 1553 */ MCD_OPC_CheckPredicate, 62, 254, 10, 0, // Skip to: 4372 -/* 1558 */ MCD_OPC_Decode, 151, 10, 197, 2, // Opcode: VFMAS -/* 1563 */ MCD_OPC_FilterValue, 1, 244, 10, 0, // Skip to: 4372 -/* 1568 */ MCD_OPC_CheckPredicate, 62, 239, 10, 0, // Skip to: 4372 -/* 1573 */ MCD_OPC_Decode, 158, 10, 197, 2, // Opcode: VFMSS -/* 1578 */ MCD_OPC_FilterValue, 1, 229, 10, 0, // Skip to: 4372 -/* 1583 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 1586 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1615 -/* 1591 */ MCD_OPC_CheckPredicate, 27, 216, 10, 0, // Skip to: 4372 -/* 1596 */ MCD_OPC_CheckField, 22, 1, 1, 209, 10, 0, // Skip to: 4372 -/* 1603 */ MCD_OPC_CheckField, 7, 1, 0, 202, 10, 0, // Skip to: 4372 -/* 1610 */ MCD_OPC_Decode, 178, 14, 214, 2, // Opcode: VMSR_FPSID -/* 1615 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 1644 -/* 1620 */ MCD_OPC_CheckPredicate, 27, 187, 10, 0, // Skip to: 4372 -/* 1625 */ MCD_OPC_CheckField, 22, 1, 1, 180, 10, 0, // Skip to: 4372 -/* 1632 */ MCD_OPC_CheckField, 7, 1, 0, 173, 10, 0, // Skip to: 4372 -/* 1639 */ MCD_OPC_Decode, 174, 14, 214, 2, // Opcode: VMSR -/* 1644 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1673 -/* 1649 */ MCD_OPC_CheckPredicate, 27, 158, 10, 0, // Skip to: 4372 -/* 1654 */ MCD_OPC_CheckField, 22, 1, 1, 151, 10, 0, // Skip to: 4372 -/* 1661 */ MCD_OPC_CheckField, 7, 1, 0, 144, 10, 0, // Skip to: 4372 -/* 1668 */ MCD_OPC_Decode, 175, 14, 214, 2, // Opcode: VMSR_FPEXC -/* 1673 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1702 -/* 1678 */ MCD_OPC_CheckPredicate, 27, 129, 10, 0, // Skip to: 4372 -/* 1683 */ MCD_OPC_CheckField, 22, 1, 1, 122, 10, 0, // Skip to: 4372 -/* 1690 */ MCD_OPC_CheckField, 7, 1, 0, 115, 10, 0, // Skip to: 4372 -/* 1697 */ MCD_OPC_Decode, 176, 14, 214, 2, // Opcode: VMSR_FPINST -/* 1702 */ MCD_OPC_FilterValue, 10, 105, 10, 0, // Skip to: 4372 -/* 1707 */ MCD_OPC_CheckPredicate, 27, 100, 10, 0, // Skip to: 4372 -/* 1712 */ MCD_OPC_CheckField, 22, 1, 1, 93, 10, 0, // Skip to: 4372 -/* 1719 */ MCD_OPC_CheckField, 7, 1, 0, 86, 10, 0, // Skip to: 4372 -/* 1726 */ MCD_OPC_Decode, 177, 14, 214, 2, // Opcode: VMSR_FPINST2 -/* 1731 */ MCD_OPC_FilterValue, 11, 76, 10, 0, // Skip to: 4372 -/* 1736 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1739 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1761 -/* 1744 */ MCD_OPC_CheckPredicate, 63, 63, 10, 0, // Skip to: 4372 -/* 1749 */ MCD_OPC_CheckField, 4, 1, 0, 56, 10, 0, // Skip to: 4372 -/* 1756 */ MCD_OPC_Decode, 149, 10, 204, 2, // Opcode: VFMAD -/* 1761 */ MCD_OPC_FilterValue, 1, 46, 10, 0, // Skip to: 4372 -/* 1766 */ MCD_OPC_CheckPredicate, 63, 41, 10, 0, // Skip to: 4372 -/* 1771 */ MCD_OPC_CheckField, 4, 1, 0, 34, 10, 0, // Skip to: 4372 -/* 1778 */ MCD_OPC_Decode, 156, 10, 204, 2, // Opcode: VFMSD -/* 1783 */ MCD_OPC_FilterValue, 3, 24, 10, 0, // Skip to: 4372 -/* 1788 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... -/* 1791 */ MCD_OPC_FilterValue, 24, 25, 0, 0, // Skip to: 1821 -/* 1796 */ MCD_OPC_CheckPredicate, 64, 11, 10, 0, // Skip to: 4372 -/* 1801 */ MCD_OPC_CheckField, 22, 1, 0, 4, 10, 0, // Skip to: 4372 -/* 1808 */ MCD_OPC_CheckField, 0, 16, 128, 20, 252, 9, 0, // Skip to: 4372 -/* 1816 */ MCD_OPC_Decode, 154, 13, 210, 2, // Opcode: VLLDM -/* 1821 */ MCD_OPC_FilterValue, 25, 63, 0, 0, // Skip to: 1889 -/* 1826 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1829 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1844 -/* 1834 */ MCD_OPC_CheckPredicate, 27, 229, 9, 0, // Skip to: 4372 -/* 1839 */ MCD_OPC_Decode, 150, 13, 211, 2, // Opcode: VLDMSIA_UPD -/* 1844 */ MCD_OPC_FilterValue, 11, 219, 9, 0, // Skip to: 4372 -/* 1849 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 1852 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1867 -/* 1857 */ MCD_OPC_CheckPredicate, 27, 206, 9, 0, // Skip to: 4372 -/* 1862 */ MCD_OPC_Decode, 146, 13, 212, 2, // Opcode: VLDMDIA_UPD -/* 1867 */ MCD_OPC_FilterValue, 1, 196, 9, 0, // Skip to: 4372 -/* 1872 */ MCD_OPC_CheckPredicate, 27, 191, 9, 0, // Skip to: 4372 -/* 1877 */ MCD_OPC_CheckField, 22, 1, 0, 184, 9, 0, // Skip to: 4372 -/* 1884 */ MCD_OPC_Decode, 213, 4, 213, 2, // Opcode: FLDMXIA_UPD -/* 1889 */ MCD_OPC_FilterValue, 26, 63, 0, 0, // Skip to: 1957 -/* 1894 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1897 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1912 -/* 1902 */ MCD_OPC_CheckPredicate, 27, 161, 9, 0, // Skip to: 4372 -/* 1907 */ MCD_OPC_Decode, 148, 13, 211, 2, // Opcode: VLDMSDB_UPD -/* 1912 */ MCD_OPC_FilterValue, 11, 151, 9, 0, // Skip to: 4372 -/* 1917 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 1920 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1935 -/* 1925 */ MCD_OPC_CheckPredicate, 27, 138, 9, 0, // Skip to: 4372 -/* 1930 */ MCD_OPC_Decode, 144, 13, 212, 2, // Opcode: VLDMDDB_UPD -/* 1935 */ MCD_OPC_FilterValue, 1, 128, 9, 0, // Skip to: 4372 -/* 1940 */ MCD_OPC_CheckPredicate, 27, 123, 9, 0, // Skip to: 4372 -/* 1945 */ MCD_OPC_CheckField, 22, 1, 0, 116, 9, 0, // Skip to: 4372 -/* 1952 */ MCD_OPC_Decode, 211, 4, 213, 2, // Opcode: FLDMXDB_UPD -/* 1957 */ MCD_OPC_FilterValue, 28, 159, 0, 0, // Skip to: 2121 -/* 1962 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1965 */ MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 2017 -/* 1970 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1973 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1995 -/* 1978 */ MCD_OPC_CheckPredicate, 60, 85, 9, 0, // Skip to: 4372 -/* 1983 */ MCD_OPC_CheckField, 4, 1, 0, 78, 9, 0, // Skip to: 4372 -/* 1990 */ MCD_OPC_Decode, 236, 7, 192, 2, // Opcode: VADDH -/* 1995 */ MCD_OPC_FilterValue, 1, 68, 9, 0, // Skip to: 4372 -/* 2000 */ MCD_OPC_CheckPredicate, 60, 63, 9, 0, // Skip to: 4372 -/* 2005 */ MCD_OPC_CheckField, 4, 1, 0, 56, 9, 0, // Skip to: 4372 -/* 2012 */ MCD_OPC_Decode, 208, 20, 192, 2, // Opcode: VSUBH -/* 2017 */ MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 2069 -/* 2022 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2025 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2047 -/* 2030 */ MCD_OPC_CheckPredicate, 27, 33, 9, 0, // Skip to: 4372 -/* 2035 */ MCD_OPC_CheckField, 4, 1, 0, 26, 9, 0, // Skip to: 4372 -/* 2042 */ MCD_OPC_Decode, 246, 7, 198, 2, // Opcode: VADDS -/* 2047 */ MCD_OPC_FilterValue, 1, 16, 9, 0, // Skip to: 4372 -/* 2052 */ MCD_OPC_CheckPredicate, 27, 11, 9, 0, // Skip to: 4372 -/* 2057 */ MCD_OPC_CheckField, 4, 1, 0, 4, 9, 0, // Skip to: 4372 -/* 2064 */ MCD_OPC_Decode, 218, 20, 198, 2, // Opcode: VSUBS -/* 2069 */ MCD_OPC_FilterValue, 11, 250, 8, 0, // Skip to: 4372 -/* 2074 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2077 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2099 -/* 2082 */ MCD_OPC_CheckPredicate, 61, 237, 8, 0, // Skip to: 4372 -/* 2087 */ MCD_OPC_CheckField, 4, 1, 0, 230, 8, 0, // Skip to: 4372 -/* 2094 */ MCD_OPC_Decode, 235, 7, 205, 2, // Opcode: VADDD -/* 2099 */ MCD_OPC_FilterValue, 1, 220, 8, 0, // Skip to: 4372 -/* 2104 */ MCD_OPC_CheckPredicate, 61, 215, 8, 0, // Skip to: 4372 -/* 2109 */ MCD_OPC_CheckField, 4, 1, 0, 208, 8, 0, // Skip to: 4372 -/* 2116 */ MCD_OPC_Decode, 207, 20, 205, 2, // Opcode: VSUBD -/* 2121 */ MCD_OPC_FilterValue, 29, 198, 8, 0, // Skip to: 4372 -/* 2126 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... -/* 2129 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 2151 -/* 2134 */ MCD_OPC_CheckPredicate, 60, 185, 8, 0, // Skip to: 4372 -/* 2139 */ MCD_OPC_CheckField, 4, 2, 0, 178, 8, 0, // Skip to: 4372 -/* 2146 */ MCD_OPC_Decode, 209, 4, 215, 2, // Opcode: FCONSTH -/* 2151 */ MCD_OPC_FilterValue, 37, 11, 1, 0, // Skip to: 2423 -/* 2156 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 2159 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2181 -/* 2164 */ MCD_OPC_CheckPredicate, 60, 155, 8, 0, // Skip to: 4372 -/* 2169 */ MCD_OPC_CheckField, 4, 1, 0, 148, 8, 0, // Skip to: 4372 -/* 2176 */ MCD_OPC_Decode, 221, 14, 216, 2, // Opcode: VNEGH -/* 2181 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2203 -/* 2186 */ MCD_OPC_CheckPredicate, 60, 133, 8, 0, // Skip to: 4372 -/* 2191 */ MCD_OPC_CheckField, 4, 1, 0, 126, 8, 0, // Skip to: 4372 -/* 2198 */ MCD_OPC_Decode, 146, 9, 216, 2, // Opcode: VCMPH -/* 2203 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2225 -/* 2208 */ MCD_OPC_CheckPredicate, 60, 111, 8, 0, // Skip to: 4372 -/* 2213 */ MCD_OPC_CheckField, 0, 6, 0, 104, 8, 0, // Skip to: 4372 -/* 2220 */ MCD_OPC_Decode, 149, 9, 217, 2, // Opcode: VCMPZH -/* 2225 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2247 -/* 2230 */ MCD_OPC_CheckPredicate, 60, 89, 8, 0, // Skip to: 4372 -/* 2235 */ MCD_OPC_CheckField, 4, 1, 0, 82, 8, 0, // Skip to: 4372 -/* 2242 */ MCD_OPC_Decode, 148, 17, 218, 2, // Opcode: VRINTRH -/* 2247 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2269 -/* 2252 */ MCD_OPC_CheckPredicate, 60, 67, 8, 0, // Skip to: 4372 -/* 2257 */ MCD_OPC_CheckField, 4, 1, 0, 60, 8, 0, // Skip to: 4372 -/* 2264 */ MCD_OPC_Decode, 151, 17, 218, 2, // Opcode: VRINTXH -/* 2269 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 2291 -/* 2274 */ MCD_OPC_CheckPredicate, 60, 45, 8, 0, // Skip to: 4372 -/* 2279 */ MCD_OPC_CheckField, 4, 1, 0, 38, 8, 0, // Skip to: 4372 -/* 2286 */ MCD_OPC_Decode, 167, 21, 219, 2, // Opcode: VUITOH -/* 2291 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 2313 -/* 2296 */ MCD_OPC_CheckPredicate, 60, 23, 8, 0, // Skip to: 4372 -/* 2301 */ MCD_OPC_CheckField, 4, 1, 0, 16, 8, 0, // Skip to: 4372 -/* 2308 */ MCD_OPC_Decode, 172, 18, 220, 2, // Opcode: VSHTOH -/* 2313 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 2335 -/* 2318 */ MCD_OPC_CheckPredicate, 60, 1, 8, 0, // Skip to: 4372 -/* 2323 */ MCD_OPC_CheckField, 4, 1, 0, 250, 7, 0, // Skip to: 4372 -/* 2330 */ MCD_OPC_Decode, 164, 21, 220, 2, // Opcode: VUHTOH -/* 2335 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2357 -/* 2340 */ MCD_OPC_CheckPredicate, 60, 235, 7, 0, // Skip to: 4372 -/* 2345 */ MCD_OPC_CheckField, 4, 1, 0, 228, 7, 0, // Skip to: 4372 -/* 2352 */ MCD_OPC_Decode, 139, 21, 218, 2, // Opcode: VTOUIRH -/* 2357 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2379 -/* 2362 */ MCD_OPC_CheckPredicate, 60, 213, 7, 0, // Skip to: 4372 -/* 2367 */ MCD_OPC_CheckField, 4, 1, 0, 206, 7, 0, // Skip to: 4372 -/* 2374 */ MCD_OPC_Decode, 255, 20, 218, 2, // Opcode: VTOSIRH -/* 2379 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2401 -/* 2384 */ MCD_OPC_CheckPredicate, 60, 191, 7, 0, // Skip to: 4372 -/* 2389 */ MCD_OPC_CheckField, 4, 1, 0, 184, 7, 0, // Skip to: 4372 -/* 2396 */ MCD_OPC_Decode, 252, 20, 220, 2, // Opcode: VTOSHH -/* 2401 */ MCD_OPC_FilterValue, 15, 174, 7, 0, // Skip to: 4372 -/* 2406 */ MCD_OPC_CheckPredicate, 60, 169, 7, 0, // Skip to: 4372 -/* 2411 */ MCD_OPC_CheckField, 4, 1, 0, 162, 7, 0, // Skip to: 4372 -/* 2418 */ MCD_OPC_Decode, 136, 21, 220, 2, // Opcode: VTOUHH -/* 2423 */ MCD_OPC_FilterValue, 39, 11, 1, 0, // Skip to: 2695 -/* 2428 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 2431 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2453 -/* 2436 */ MCD_OPC_CheckPredicate, 60, 139, 7, 0, // Skip to: 4372 -/* 2441 */ MCD_OPC_CheckField, 4, 1, 0, 132, 7, 0, // Skip to: 4372 -/* 2448 */ MCD_OPC_Decode, 215, 7, 218, 2, // Opcode: VABSH -/* 2453 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2475 -/* 2458 */ MCD_OPC_CheckPredicate, 60, 117, 7, 0, // Skip to: 4372 -/* 2463 */ MCD_OPC_CheckField, 4, 1, 0, 110, 7, 0, // Skip to: 4372 -/* 2470 */ MCD_OPC_Decode, 189, 18, 218, 2, // Opcode: VSQRTH -/* 2475 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2497 -/* 2480 */ MCD_OPC_CheckPredicate, 60, 95, 7, 0, // Skip to: 4372 -/* 2485 */ MCD_OPC_CheckField, 4, 1, 0, 88, 7, 0, // Skip to: 4372 -/* 2492 */ MCD_OPC_Decode, 141, 9, 216, 2, // Opcode: VCMPEH -/* 2497 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2519 -/* 2502 */ MCD_OPC_CheckPredicate, 60, 73, 7, 0, // Skip to: 4372 -/* 2507 */ MCD_OPC_CheckField, 0, 6, 0, 66, 7, 0, // Skip to: 4372 -/* 2514 */ MCD_OPC_Decode, 144, 9, 217, 2, // Opcode: VCMPEZH -/* 2519 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2541 -/* 2524 */ MCD_OPC_CheckPredicate, 60, 51, 7, 0, // Skip to: 4372 -/* 2529 */ MCD_OPC_CheckField, 4, 1, 0, 44, 7, 0, // Skip to: 4372 -/* 2536 */ MCD_OPC_Decode, 158, 17, 218, 2, // Opcode: VRINTZH -/* 2541 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 2563 -/* 2546 */ MCD_OPC_CheckPredicate, 60, 29, 7, 0, // Skip to: 4372 -/* 2551 */ MCD_OPC_CheckField, 4, 1, 0, 22, 7, 0, // Skip to: 4372 -/* 2558 */ MCD_OPC_Decode, 175, 18, 219, 2, // Opcode: VSITOH -/* 2563 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 2585 -/* 2568 */ MCD_OPC_CheckPredicate, 60, 7, 7, 0, // Skip to: 4372 -/* 2573 */ MCD_OPC_CheckField, 4, 1, 0, 0, 7, 0, // Skip to: 4372 -/* 2580 */ MCD_OPC_Decode, 186, 18, 220, 2, // Opcode: VSLTOH -/* 2585 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 2607 -/* 2590 */ MCD_OPC_CheckPredicate, 60, 241, 6, 0, // Skip to: 4372 -/* 2595 */ MCD_OPC_CheckField, 4, 1, 0, 234, 6, 0, // Skip to: 4372 -/* 2602 */ MCD_OPC_Decode, 170, 21, 220, 2, // Opcode: VULTOH -/* 2607 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2629 -/* 2612 */ MCD_OPC_CheckPredicate, 60, 219, 6, 0, // Skip to: 4372 -/* 2617 */ MCD_OPC_CheckField, 4, 1, 0, 212, 6, 0, // Skip to: 4372 -/* 2624 */ MCD_OPC_Decode, 142, 21, 221, 2, // Opcode: VTOUIZH -/* 2629 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2651 -/* 2634 */ MCD_OPC_CheckPredicate, 60, 197, 6, 0, // Skip to: 4372 -/* 2639 */ MCD_OPC_CheckField, 4, 1, 0, 190, 6, 0, // Skip to: 4372 -/* 2646 */ MCD_OPC_Decode, 130, 21, 221, 2, // Opcode: VTOSIZH -/* 2651 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2673 -/* 2656 */ MCD_OPC_CheckPredicate, 60, 175, 6, 0, // Skip to: 4372 -/* 2661 */ MCD_OPC_CheckField, 4, 1, 0, 168, 6, 0, // Skip to: 4372 -/* 2668 */ MCD_OPC_Decode, 133, 21, 220, 2, // Opcode: VTOSLH -/* 2673 */ MCD_OPC_FilterValue, 15, 158, 6, 0, // Skip to: 4372 -/* 2678 */ MCD_OPC_CheckPredicate, 60, 153, 6, 0, // Skip to: 4372 -/* 2683 */ MCD_OPC_CheckField, 4, 1, 0, 146, 6, 0, // Skip to: 4372 -/* 2690 */ MCD_OPC_Decode, 145, 21, 220, 2, // Opcode: VTOULH -/* 2695 */ MCD_OPC_FilterValue, 40, 20, 1, 0, // Skip to: 2976 -/* 2700 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 2703 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2718 -/* 2708 */ MCD_OPC_CheckPredicate, 65, 123, 6, 0, // Skip to: 4372 -/* 2713 */ MCD_OPC_Decode, 210, 4, 222, 2, // Opcode: FCONSTS -/* 2718 */ MCD_OPC_FilterValue, 1, 113, 6, 0, // Skip to: 4372 -/* 2723 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 2726 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2755 -/* 2731 */ MCD_OPC_CheckPredicate, 27, 100, 6, 0, // Skip to: 4372 -/* 2736 */ MCD_OPC_CheckField, 22, 1, 1, 93, 6, 0, // Skip to: 4372 -/* 2743 */ MCD_OPC_CheckField, 0, 4, 0, 86, 6, 0, // Skip to: 4372 -/* 2750 */ MCD_OPC_Decode, 170, 14, 214, 2, // Opcode: VMRS_FPSID -/* 2755 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 2802 -/* 2760 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... -/* 2763 */ MCD_OPC_FilterValue, 0, 68, 6, 0, // Skip to: 4372 -/* 2768 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... -/* 2771 */ MCD_OPC_FilterValue, 1, 60, 6, 0, // Skip to: 4372 -/* 2776 */ MCD_OPC_CheckPredicate, 27, 11, 0, 0, // Skip to: 2792 -/* 2781 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 2792 -/* 2788 */ MCD_OPC_Decode, 214, 4, 29, // Opcode: FMSTAT -/* 2792 */ MCD_OPC_CheckPredicate, 27, 39, 6, 0, // Skip to: 4372 -/* 2797 */ MCD_OPC_Decode, 166, 14, 214, 2, // Opcode: VMRS -/* 2802 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 2831 -/* 2807 */ MCD_OPC_CheckPredicate, 66, 24, 6, 0, // Skip to: 4372 -/* 2812 */ MCD_OPC_CheckField, 22, 1, 1, 17, 6, 0, // Skip to: 4372 -/* 2819 */ MCD_OPC_CheckField, 0, 4, 0, 10, 6, 0, // Skip to: 4372 -/* 2826 */ MCD_OPC_Decode, 173, 14, 214, 2, // Opcode: VMRS_MVFR2 -/* 2831 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 2860 -/* 2836 */ MCD_OPC_CheckPredicate, 27, 251, 5, 0, // Skip to: 4372 -/* 2841 */ MCD_OPC_CheckField, 22, 1, 1, 244, 5, 0, // Skip to: 4372 -/* 2848 */ MCD_OPC_CheckField, 0, 4, 0, 237, 5, 0, // Skip to: 4372 -/* 2855 */ MCD_OPC_Decode, 172, 14, 214, 2, // Opcode: VMRS_MVFR1 -/* 2860 */ MCD_OPC_FilterValue, 7, 24, 0, 0, // Skip to: 2889 -/* 2865 */ MCD_OPC_CheckPredicate, 27, 222, 5, 0, // Skip to: 4372 -/* 2870 */ MCD_OPC_CheckField, 22, 1, 1, 215, 5, 0, // Skip to: 4372 -/* 2877 */ MCD_OPC_CheckField, 0, 4, 0, 208, 5, 0, // Skip to: 4372 -/* 2884 */ MCD_OPC_Decode, 171, 14, 214, 2, // Opcode: VMRS_MVFR0 -/* 2889 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 2918 -/* 2894 */ MCD_OPC_CheckPredicate, 27, 193, 5, 0, // Skip to: 4372 -/* 2899 */ MCD_OPC_CheckField, 22, 1, 1, 186, 5, 0, // Skip to: 4372 -/* 2906 */ MCD_OPC_CheckField, 0, 4, 0, 179, 5, 0, // Skip to: 4372 -/* 2913 */ MCD_OPC_Decode, 167, 14, 214, 2, // Opcode: VMRS_FPEXC -/* 2918 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 2947 -/* 2923 */ MCD_OPC_CheckPredicate, 27, 164, 5, 0, // Skip to: 4372 -/* 2928 */ MCD_OPC_CheckField, 22, 1, 1, 157, 5, 0, // Skip to: 4372 -/* 2935 */ MCD_OPC_CheckField, 0, 4, 0, 150, 5, 0, // Skip to: 4372 -/* 2942 */ MCD_OPC_Decode, 168, 14, 214, 2, // Opcode: VMRS_FPINST -/* 2947 */ MCD_OPC_FilterValue, 10, 140, 5, 0, // Skip to: 4372 -/* 2952 */ MCD_OPC_CheckPredicate, 27, 135, 5, 0, // Skip to: 4372 -/* 2957 */ MCD_OPC_CheckField, 22, 1, 1, 128, 5, 0, // Skip to: 4372 -/* 2964 */ MCD_OPC_CheckField, 0, 4, 0, 121, 5, 0, // Skip to: 4372 -/* 2971 */ MCD_OPC_Decode, 169, 14, 214, 2, // Opcode: VMRS_FPINST2 -/* 2976 */ MCD_OPC_FilterValue, 41, 77, 1, 0, // Skip to: 3314 -/* 2981 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 2984 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3006 -/* 2989 */ MCD_OPC_CheckPredicate, 27, 98, 5, 0, // Skip to: 4372 -/* 2994 */ MCD_OPC_CheckField, 4, 1, 0, 91, 5, 0, // Skip to: 4372 -/* 3001 */ MCD_OPC_Decode, 153, 14, 218, 2, // Opcode: VMOVS -/* 3006 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3028 -/* 3011 */ MCD_OPC_CheckPredicate, 27, 76, 5, 0, // Skip to: 4372 -/* 3016 */ MCD_OPC_CheckField, 4, 1, 0, 69, 5, 0, // Skip to: 4372 -/* 3023 */ MCD_OPC_Decode, 222, 14, 218, 2, // Opcode: VNEGS -/* 3028 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3050 -/* 3033 */ MCD_OPC_CheckPredicate, 67, 54, 5, 0, // Skip to: 4372 -/* 3038 */ MCD_OPC_CheckField, 4, 1, 0, 47, 5, 0, // Skip to: 4372 -/* 3045 */ MCD_OPC_Decode, 169, 9, 218, 2, // Opcode: VCVTBHS -/* 3050 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3072 -/* 3055 */ MCD_OPC_CheckPredicate, 67, 32, 5, 0, // Skip to: 4372 -/* 3060 */ MCD_OPC_CheckField, 4, 1, 0, 25, 5, 0, // Skip to: 4372 -/* 3067 */ MCD_OPC_Decode, 170, 9, 218, 2, // Opcode: VCVTBSH -/* 3072 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3094 -/* 3077 */ MCD_OPC_CheckPredicate, 27, 10, 5, 0, // Skip to: 4372 -/* 3082 */ MCD_OPC_CheckField, 4, 1, 0, 3, 5, 0, // Skip to: 4372 -/* 3089 */ MCD_OPC_Decode, 147, 9, 218, 2, // Opcode: VCMPS -/* 3094 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3116 -/* 3099 */ MCD_OPC_CheckPredicate, 27, 244, 4, 0, // Skip to: 4372 -/* 3104 */ MCD_OPC_CheckField, 0, 6, 0, 237, 4, 0, // Skip to: 4372 -/* 3111 */ MCD_OPC_Decode, 150, 9, 223, 2, // Opcode: VCMPZS -/* 3116 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3138 -/* 3121 */ MCD_OPC_CheckPredicate, 66, 222, 4, 0, // Skip to: 4372 -/* 3126 */ MCD_OPC_CheckField, 4, 1, 0, 215, 4, 0, // Skip to: 4372 -/* 3133 */ MCD_OPC_Decode, 149, 17, 218, 2, // Opcode: VRINTRS -/* 3138 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3160 -/* 3143 */ MCD_OPC_CheckPredicate, 66, 200, 4, 0, // Skip to: 4372 -/* 3148 */ MCD_OPC_CheckField, 4, 1, 0, 193, 4, 0, // Skip to: 4372 -/* 3155 */ MCD_OPC_Decode, 156, 17, 218, 2, // Opcode: VRINTXS -/* 3160 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3182 -/* 3165 */ MCD_OPC_CheckPredicate, 27, 178, 4, 0, // Skip to: 4372 -/* 3170 */ MCD_OPC_CheckField, 4, 1, 0, 171, 4, 0, // Skip to: 4372 -/* 3177 */ MCD_OPC_Decode, 168, 21, 218, 2, // Opcode: VUITOS -/* 3182 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3204 -/* 3187 */ MCD_OPC_CheckPredicate, 27, 156, 4, 0, // Skip to: 4372 -/* 3192 */ MCD_OPC_CheckField, 4, 1, 0, 149, 4, 0, // Skip to: 4372 -/* 3199 */ MCD_OPC_Decode, 173, 18, 220, 2, // Opcode: VSHTOS -/* 3204 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3226 -/* 3209 */ MCD_OPC_CheckPredicate, 27, 134, 4, 0, // Skip to: 4372 -/* 3214 */ MCD_OPC_CheckField, 4, 1, 0, 127, 4, 0, // Skip to: 4372 -/* 3221 */ MCD_OPC_Decode, 165, 21, 220, 2, // Opcode: VUHTOS -/* 3226 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3248 -/* 3231 */ MCD_OPC_CheckPredicate, 27, 112, 4, 0, // Skip to: 4372 -/* 3236 */ MCD_OPC_CheckField, 4, 1, 0, 105, 4, 0, // Skip to: 4372 -/* 3243 */ MCD_OPC_Decode, 140, 21, 218, 2, // Opcode: VTOUIRS -/* 3248 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3270 -/* 3253 */ MCD_OPC_CheckPredicate, 27, 90, 4, 0, // Skip to: 4372 -/* 3258 */ MCD_OPC_CheckField, 4, 1, 0, 83, 4, 0, // Skip to: 4372 -/* 3265 */ MCD_OPC_Decode, 128, 21, 218, 2, // Opcode: VTOSIRS -/* 3270 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3292 -/* 3275 */ MCD_OPC_CheckPredicate, 27, 68, 4, 0, // Skip to: 4372 -/* 3280 */ MCD_OPC_CheckField, 4, 1, 0, 61, 4, 0, // Skip to: 4372 -/* 3287 */ MCD_OPC_Decode, 253, 20, 220, 2, // Opcode: VTOSHS -/* 3292 */ MCD_OPC_FilterValue, 15, 51, 4, 0, // Skip to: 4372 -/* 3297 */ MCD_OPC_CheckPredicate, 27, 46, 4, 0, // Skip to: 4372 -/* 3302 */ MCD_OPC_CheckField, 4, 1, 0, 39, 4, 0, // Skip to: 4372 -/* 3309 */ MCD_OPC_Decode, 137, 21, 220, 2, // Opcode: VTOUHS -/* 3314 */ MCD_OPC_FilterValue, 43, 77, 1, 0, // Skip to: 3652 -/* 3319 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 3322 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3344 -/* 3327 */ MCD_OPC_CheckPredicate, 27, 16, 4, 0, // Skip to: 4372 -/* 3332 */ MCD_OPC_CheckField, 4, 1, 0, 9, 4, 0, // Skip to: 4372 -/* 3339 */ MCD_OPC_Decode, 216, 7, 218, 2, // Opcode: VABSS -/* 3344 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3366 -/* 3349 */ MCD_OPC_CheckPredicate, 27, 250, 3, 0, // Skip to: 4372 -/* 3354 */ MCD_OPC_CheckField, 4, 1, 0, 243, 3, 0, // Skip to: 4372 -/* 3361 */ MCD_OPC_Decode, 190, 18, 218, 2, // Opcode: VSQRTS -/* 3366 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3388 -/* 3371 */ MCD_OPC_CheckPredicate, 67, 228, 3, 0, // Skip to: 4372 -/* 3376 */ MCD_OPC_CheckField, 4, 1, 0, 221, 3, 0, // Skip to: 4372 -/* 3383 */ MCD_OPC_Decode, 217, 9, 218, 2, // Opcode: VCVTTHS -/* 3388 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3410 -/* 3393 */ MCD_OPC_CheckPredicate, 67, 206, 3, 0, // Skip to: 4372 -/* 3398 */ MCD_OPC_CheckField, 4, 1, 0, 199, 3, 0, // Skip to: 4372 -/* 3405 */ MCD_OPC_Decode, 218, 9, 218, 2, // Opcode: VCVTTSH -/* 3410 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3432 -/* 3415 */ MCD_OPC_CheckPredicate, 27, 184, 3, 0, // Skip to: 4372 -/* 3420 */ MCD_OPC_CheckField, 4, 1, 0, 177, 3, 0, // Skip to: 4372 -/* 3427 */ MCD_OPC_Decode, 142, 9, 218, 2, // Opcode: VCMPES -/* 3432 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3454 -/* 3437 */ MCD_OPC_CheckPredicate, 27, 162, 3, 0, // Skip to: 4372 -/* 3442 */ MCD_OPC_CheckField, 0, 6, 0, 155, 3, 0, // Skip to: 4372 -/* 3449 */ MCD_OPC_Decode, 145, 9, 223, 2, // Opcode: VCMPEZS -/* 3454 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3476 -/* 3459 */ MCD_OPC_CheckPredicate, 66, 140, 3, 0, // Skip to: 4372 -/* 3464 */ MCD_OPC_CheckField, 4, 1, 0, 133, 3, 0, // Skip to: 4372 -/* 3471 */ MCD_OPC_Decode, 163, 17, 218, 2, // Opcode: VRINTZS -/* 3476 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3498 -/* 3481 */ MCD_OPC_CheckPredicate, 61, 118, 3, 0, // Skip to: 4372 -/* 3486 */ MCD_OPC_CheckField, 4, 1, 0, 111, 3, 0, // Skip to: 4372 -/* 3493 */ MCD_OPC_Decode, 171, 9, 224, 2, // Opcode: VCVTDS -/* 3498 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3520 -/* 3503 */ MCD_OPC_CheckPredicate, 27, 96, 3, 0, // Skip to: 4372 -/* 3508 */ MCD_OPC_CheckField, 4, 1, 0, 89, 3, 0, // Skip to: 4372 -/* 3515 */ MCD_OPC_Decode, 176, 18, 218, 2, // Opcode: VSITOS -/* 3520 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3542 -/* 3525 */ MCD_OPC_CheckPredicate, 27, 74, 3, 0, // Skip to: 4372 -/* 3530 */ MCD_OPC_CheckField, 4, 1, 0, 67, 3, 0, // Skip to: 4372 -/* 3537 */ MCD_OPC_Decode, 187, 18, 220, 2, // Opcode: VSLTOS -/* 3542 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3564 -/* 3547 */ MCD_OPC_CheckPredicate, 27, 52, 3, 0, // Skip to: 4372 -/* 3552 */ MCD_OPC_CheckField, 4, 1, 0, 45, 3, 0, // Skip to: 4372 -/* 3559 */ MCD_OPC_Decode, 171, 21, 220, 2, // Opcode: VULTOS -/* 3564 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3586 -/* 3569 */ MCD_OPC_CheckPredicate, 27, 30, 3, 0, // Skip to: 4372 -/* 3574 */ MCD_OPC_CheckField, 4, 1, 0, 23, 3, 0, // Skip to: 4372 -/* 3581 */ MCD_OPC_Decode, 143, 21, 218, 2, // Opcode: VTOUIZS -/* 3586 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3608 -/* 3591 */ MCD_OPC_CheckPredicate, 27, 8, 3, 0, // Skip to: 4372 -/* 3596 */ MCD_OPC_CheckField, 4, 1, 0, 1, 3, 0, // Skip to: 4372 -/* 3603 */ MCD_OPC_Decode, 131, 21, 218, 2, // Opcode: VTOSIZS -/* 3608 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3630 -/* 3613 */ MCD_OPC_CheckPredicate, 27, 242, 2, 0, // Skip to: 4372 -/* 3618 */ MCD_OPC_CheckField, 4, 1, 0, 235, 2, 0, // Skip to: 4372 -/* 3625 */ MCD_OPC_Decode, 134, 21, 220, 2, // Opcode: VTOSLS -/* 3630 */ MCD_OPC_FilterValue, 15, 225, 2, 0, // Skip to: 4372 -/* 3635 */ MCD_OPC_CheckPredicate, 27, 220, 2, 0, // Skip to: 4372 -/* 3640 */ MCD_OPC_CheckField, 4, 1, 0, 213, 2, 0, // Skip to: 4372 -/* 3647 */ MCD_OPC_Decode, 146, 21, 220, 2, // Opcode: VTOULS -/* 3652 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 3674 -/* 3657 */ MCD_OPC_CheckPredicate, 68, 198, 2, 0, // Skip to: 4372 -/* 3662 */ MCD_OPC_CheckField, 4, 2, 0, 191, 2, 0, // Skip to: 4372 -/* 3669 */ MCD_OPC_Decode, 208, 4, 225, 2, // Opcode: FCONSTD -/* 3674 */ MCD_OPC_FilterValue, 45, 77, 1, 0, // Skip to: 4012 -/* 3679 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 3682 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3704 -/* 3687 */ MCD_OPC_CheckPredicate, 61, 168, 2, 0, // Skip to: 4372 -/* 3692 */ MCD_OPC_CheckField, 4, 1, 0, 161, 2, 0, // Skip to: 4372 -/* 3699 */ MCD_OPC_Decode, 136, 14, 226, 2, // Opcode: VMOVD -/* 3704 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3726 -/* 3709 */ MCD_OPC_CheckPredicate, 61, 146, 2, 0, // Skip to: 4372 -/* 3714 */ MCD_OPC_CheckField, 4, 1, 0, 139, 2, 0, // Skip to: 4372 -/* 3721 */ MCD_OPC_Decode, 220, 14, 226, 2, // Opcode: VNEGD -/* 3726 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3748 -/* 3731 */ MCD_OPC_CheckPredicate, 69, 124, 2, 0, // Skip to: 4372 -/* 3736 */ MCD_OPC_CheckField, 4, 1, 0, 117, 2, 0, // Skip to: 4372 -/* 3743 */ MCD_OPC_Decode, 168, 9, 224, 2, // Opcode: VCVTBHD -/* 3748 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3770 -/* 3753 */ MCD_OPC_CheckPredicate, 69, 102, 2, 0, // Skip to: 4372 -/* 3758 */ MCD_OPC_CheckField, 4, 1, 0, 95, 2, 0, // Skip to: 4372 -/* 3765 */ MCD_OPC_Decode, 167, 9, 227, 2, // Opcode: VCVTBDH -/* 3770 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3792 -/* 3775 */ MCD_OPC_CheckPredicate, 61, 80, 2, 0, // Skip to: 4372 -/* 3780 */ MCD_OPC_CheckField, 4, 1, 0, 73, 2, 0, // Skip to: 4372 -/* 3787 */ MCD_OPC_Decode, 139, 9, 226, 2, // Opcode: VCMPD -/* 3792 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3814 -/* 3797 */ MCD_OPC_CheckPredicate, 61, 58, 2, 0, // Skip to: 4372 -/* 3802 */ MCD_OPC_CheckField, 0, 6, 0, 51, 2, 0, // Skip to: 4372 -/* 3809 */ MCD_OPC_Decode, 148, 9, 228, 2, // Opcode: VCMPZD -/* 3814 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3836 -/* 3819 */ MCD_OPC_CheckPredicate, 69, 36, 2, 0, // Skip to: 4372 -/* 3824 */ MCD_OPC_CheckField, 4, 1, 0, 29, 2, 0, // Skip to: 4372 -/* 3831 */ MCD_OPC_Decode, 147, 17, 226, 2, // Opcode: VRINTRD -/* 3836 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3858 -/* 3841 */ MCD_OPC_CheckPredicate, 69, 14, 2, 0, // Skip to: 4372 -/* 3846 */ MCD_OPC_CheckField, 4, 1, 0, 7, 2, 0, // Skip to: 4372 -/* 3853 */ MCD_OPC_Decode, 150, 17, 226, 2, // Opcode: VRINTXD -/* 3858 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3880 -/* 3863 */ MCD_OPC_CheckPredicate, 61, 248, 1, 0, // Skip to: 4372 -/* 3868 */ MCD_OPC_CheckField, 4, 1, 0, 241, 1, 0, // Skip to: 4372 -/* 3875 */ MCD_OPC_Decode, 166, 21, 224, 2, // Opcode: VUITOD -/* 3880 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3902 -/* 3885 */ MCD_OPC_CheckPredicate, 61, 226, 1, 0, // Skip to: 4372 -/* 3890 */ MCD_OPC_CheckField, 4, 1, 0, 219, 1, 0, // Skip to: 4372 -/* 3897 */ MCD_OPC_Decode, 171, 18, 229, 2, // Opcode: VSHTOD -/* 3902 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3924 -/* 3907 */ MCD_OPC_CheckPredicate, 61, 204, 1, 0, // Skip to: 4372 -/* 3912 */ MCD_OPC_CheckField, 4, 1, 0, 197, 1, 0, // Skip to: 4372 -/* 3919 */ MCD_OPC_Decode, 163, 21, 229, 2, // Opcode: VUHTOD -/* 3924 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3946 -/* 3929 */ MCD_OPC_CheckPredicate, 61, 182, 1, 0, // Skip to: 4372 -/* 3934 */ MCD_OPC_CheckField, 4, 1, 0, 175, 1, 0, // Skip to: 4372 -/* 3941 */ MCD_OPC_Decode, 138, 21, 227, 2, // Opcode: VTOUIRD -/* 3946 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3968 -/* 3951 */ MCD_OPC_CheckPredicate, 61, 160, 1, 0, // Skip to: 4372 -/* 3956 */ MCD_OPC_CheckField, 4, 1, 0, 153, 1, 0, // Skip to: 4372 -/* 3963 */ MCD_OPC_Decode, 254, 20, 227, 2, // Opcode: VTOSIRD -/* 3968 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3990 -/* 3973 */ MCD_OPC_CheckPredicate, 61, 138, 1, 0, // Skip to: 4372 -/* 3978 */ MCD_OPC_CheckField, 4, 1, 0, 131, 1, 0, // Skip to: 4372 -/* 3985 */ MCD_OPC_Decode, 251, 20, 229, 2, // Opcode: VTOSHD -/* 3990 */ MCD_OPC_FilterValue, 15, 121, 1, 0, // Skip to: 4372 -/* 3995 */ MCD_OPC_CheckPredicate, 61, 116, 1, 0, // Skip to: 4372 -/* 4000 */ MCD_OPC_CheckField, 4, 1, 0, 109, 1, 0, // Skip to: 4372 -/* 4007 */ MCD_OPC_Decode, 135, 21, 229, 2, // Opcode: VTOUHD -/* 4012 */ MCD_OPC_FilterValue, 47, 99, 1, 0, // Skip to: 4372 -/* 4017 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 4020 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4042 -/* 4025 */ MCD_OPC_CheckPredicate, 61, 86, 1, 0, // Skip to: 4372 -/* 4030 */ MCD_OPC_CheckField, 4, 1, 0, 79, 1, 0, // Skip to: 4372 -/* 4037 */ MCD_OPC_Decode, 214, 7, 226, 2, // Opcode: VABSD -/* 4042 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4064 -/* 4047 */ MCD_OPC_CheckPredicate, 61, 64, 1, 0, // Skip to: 4372 -/* 4052 */ MCD_OPC_CheckField, 4, 1, 0, 57, 1, 0, // Skip to: 4372 -/* 4059 */ MCD_OPC_Decode, 188, 18, 226, 2, // Opcode: VSQRTD -/* 4064 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4086 -/* 4069 */ MCD_OPC_CheckPredicate, 69, 42, 1, 0, // Skip to: 4372 -/* 4074 */ MCD_OPC_CheckField, 4, 1, 0, 35, 1, 0, // Skip to: 4372 -/* 4081 */ MCD_OPC_Decode, 216, 9, 224, 2, // Opcode: VCVTTHD -/* 4086 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4108 -/* 4091 */ MCD_OPC_CheckPredicate, 69, 20, 1, 0, // Skip to: 4372 -/* 4096 */ MCD_OPC_CheckField, 4, 1, 0, 13, 1, 0, // Skip to: 4372 -/* 4103 */ MCD_OPC_Decode, 215, 9, 227, 2, // Opcode: VCVTTDH -/* 4108 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4130 -/* 4113 */ MCD_OPC_CheckPredicate, 61, 254, 0, 0, // Skip to: 4372 -/* 4118 */ MCD_OPC_CheckField, 4, 1, 0, 247, 0, 0, // Skip to: 4372 -/* 4125 */ MCD_OPC_Decode, 140, 9, 226, 2, // Opcode: VCMPED -/* 4130 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4152 -/* 4135 */ MCD_OPC_CheckPredicate, 61, 232, 0, 0, // Skip to: 4372 -/* 4140 */ MCD_OPC_CheckField, 0, 6, 0, 225, 0, 0, // Skip to: 4372 -/* 4147 */ MCD_OPC_Decode, 143, 9, 228, 2, // Opcode: VCMPEZD -/* 4152 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4174 -/* 4157 */ MCD_OPC_CheckPredicate, 69, 210, 0, 0, // Skip to: 4372 -/* 4162 */ MCD_OPC_CheckField, 4, 1, 0, 203, 0, 0, // Skip to: 4372 -/* 4169 */ MCD_OPC_Decode, 157, 17, 226, 2, // Opcode: VRINTZD -/* 4174 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4196 -/* 4179 */ MCD_OPC_CheckPredicate, 61, 188, 0, 0, // Skip to: 4372 -/* 4184 */ MCD_OPC_CheckField, 4, 1, 0, 181, 0, 0, // Skip to: 4372 -/* 4191 */ MCD_OPC_Decode, 214, 9, 227, 2, // Opcode: VCVTSD -/* 4196 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4218 -/* 4201 */ MCD_OPC_CheckPredicate, 61, 166, 0, 0, // Skip to: 4372 -/* 4206 */ MCD_OPC_CheckField, 4, 1, 0, 159, 0, 0, // Skip to: 4372 -/* 4213 */ MCD_OPC_Decode, 174, 18, 224, 2, // Opcode: VSITOD -/* 4218 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4240 -/* 4223 */ MCD_OPC_CheckPredicate, 70, 144, 0, 0, // Skip to: 4372 -/* 4228 */ MCD_OPC_CheckField, 4, 1, 0, 137, 0, 0, // Skip to: 4372 -/* 4235 */ MCD_OPC_Decode, 199, 10, 227, 2, // Opcode: VJCVT -/* 4240 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4262 -/* 4245 */ MCD_OPC_CheckPredicate, 61, 122, 0, 0, // Skip to: 4372 -/* 4250 */ MCD_OPC_CheckField, 4, 1, 0, 115, 0, 0, // Skip to: 4372 -/* 4257 */ MCD_OPC_Decode, 185, 18, 229, 2, // Opcode: VSLTOD -/* 4262 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4284 -/* 4267 */ MCD_OPC_CheckPredicate, 61, 100, 0, 0, // Skip to: 4372 -/* 4272 */ MCD_OPC_CheckField, 4, 1, 0, 93, 0, 0, // Skip to: 4372 -/* 4279 */ MCD_OPC_Decode, 169, 21, 229, 2, // Opcode: VULTOD -/* 4284 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4306 -/* 4289 */ MCD_OPC_CheckPredicate, 61, 78, 0, 0, // Skip to: 4372 -/* 4294 */ MCD_OPC_CheckField, 4, 1, 0, 71, 0, 0, // Skip to: 4372 -/* 4301 */ MCD_OPC_Decode, 141, 21, 227, 2, // Opcode: VTOUIZD -/* 4306 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4328 -/* 4311 */ MCD_OPC_CheckPredicate, 61, 56, 0, 0, // Skip to: 4372 -/* 4316 */ MCD_OPC_CheckField, 4, 1, 0, 49, 0, 0, // Skip to: 4372 -/* 4323 */ MCD_OPC_Decode, 129, 21, 227, 2, // Opcode: VTOSIZD -/* 4328 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4350 -/* 4333 */ MCD_OPC_CheckPredicate, 61, 34, 0, 0, // Skip to: 4372 -/* 4338 */ MCD_OPC_CheckField, 4, 1, 0, 27, 0, 0, // Skip to: 4372 -/* 4345 */ MCD_OPC_Decode, 132, 21, 229, 2, // Opcode: VTOSLD -/* 4350 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 4372 -/* 4355 */ MCD_OPC_CheckPredicate, 61, 12, 0, 0, // Skip to: 4372 -/* 4360 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 4372 -/* 4367 */ MCD_OPC_Decode, 144, 21, 229, 2, // Opcode: VTOULD -/* 4372 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3 */ MCD_OPC_FilterValue, + 9, + 112, + 4, + 0, // Skip to: 1144 + /* 8 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 130, + 0, + 0, // Skip to: 146 + /* 16 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 19 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 34 + /* 24 */ MCD_OPC_CheckPredicate, + 73, + 222, + 21, + 0, // Skip to: 5627 + /* 29 */ MCD_OPC_Decode, + 194, + 29, + 206, + 3, // Opcode: VSTRH + /* 34 */ MCD_OPC_FilterValue, + 14, + 212, + 21, + 0, // Skip to: 5627 + /* 39 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 42 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 110 + /* 47 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 50 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 88 + /* 55 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 58 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 73 + /* 63 */ MCD_OPC_CheckPredicate, + 74, + 183, + 21, + 0, // Skip to: 5627 + /* 68 */ MCD_OPC_Decode, + 158, + 22, + 207, + 3, // Opcode: VMLAH + /* 73 */ MCD_OPC_FilterValue, + 1, + 173, + 21, + 0, // Skip to: 5627 + /* 78 */ MCD_OPC_CheckPredicate, + 74, + 168, + 21, + 0, // Skip to: 5627 + /* 83 */ MCD_OPC_Decode, + 159, + 18, + 208, + 3, // Opcode: VDIVH + /* 88 */ MCD_OPC_FilterValue, + 1, + 158, + 21, + 0, // Skip to: 5627 + /* 93 */ MCD_OPC_CheckPredicate, + 74, + 153, + 21, + 0, // Skip to: 5627 + /* 98 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 146, + 21, + 0, // Skip to: 5627 + /* 105 */ MCD_OPC_Decode, + 189, + 22, + 207, + 3, // Opcode: VMLSH + /* 110 */ MCD_OPC_FilterValue, + 1, + 136, + 21, + 0, // Skip to: 5627 + /* 115 */ MCD_OPC_CheckPredicate, + 73, + 131, + 21, + 0, // Skip to: 5627 + /* 120 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 124, + 21, + 0, // Skip to: 5627 + /* 127 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 117, + 21, + 0, // Skip to: 5627 + /* 134 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 110, + 21, + 0, // Skip to: 5627 + /* 141 */ MCD_OPC_Decode, + 223, + 22, + 209, + 3, // Opcode: VMOVHR + /* 146 */ MCD_OPC_FilterValue, + 1, + 146, + 0, + 0, // Skip to: 297 + /* 151 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 154 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 169 + /* 159 */ MCD_OPC_CheckPredicate, + 73, + 87, + 21, + 0, // Skip to: 5627 + /* 164 */ MCD_OPC_Decode, + 231, + 21, + 206, + 3, // Opcode: VLDRH + /* 169 */ MCD_OPC_FilterValue, + 14, + 77, + 21, + 0, // Skip to: 5627 + /* 174 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 177 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 261 + /* 182 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 185 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 223 + /* 190 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 193 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 208 + /* 198 */ MCD_OPC_CheckPredicate, + 74, + 48, + 21, + 0, // Skip to: 5627 + /* 203 */ MCD_OPC_Decode, + 203, + 23, + 207, + 3, // Opcode: VNMLSH + /* 208 */ MCD_OPC_FilterValue, + 1, + 38, + 21, + 0, // Skip to: 5627 + /* 213 */ MCD_OPC_CheckPredicate, + 74, + 33, + 21, + 0, // Skip to: 5627 + /* 218 */ MCD_OPC_Decode, + 208, + 18, + 207, + 3, // Opcode: VFNMSH + /* 223 */ MCD_OPC_FilterValue, + 1, + 23, + 21, + 0, // Skip to: 5627 + /* 228 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 231 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 246 + /* 236 */ MCD_OPC_CheckPredicate, + 74, + 10, + 21, + 0, // Skip to: 5627 + /* 241 */ MCD_OPC_Decode, + 200, + 23, + 207, + 3, // Opcode: VNMLAH + /* 246 */ MCD_OPC_FilterValue, + 1, + 0, + 21, + 0, // Skip to: 5627 + /* 251 */ MCD_OPC_CheckPredicate, + 74, + 251, + 20, + 0, // Skip to: 5627 + /* 256 */ MCD_OPC_Decode, + 205, + 18, + 207, + 3, // Opcode: VFNMAH + /* 261 */ MCD_OPC_FilterValue, + 1, + 241, + 20, + 0, // Skip to: 5627 + /* 266 */ MCD_OPC_CheckPredicate, + 73, + 236, + 20, + 0, // Skip to: 5627 + /* 271 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 229, + 20, + 0, // Skip to: 5627 + /* 278 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 222, + 20, + 0, // Skip to: 5627 + /* 285 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 215, + 20, + 0, // Skip to: 5627 + /* 292 */ MCD_OPC_Decode, + 233, + 22, + 210, + 3, // Opcode: VMOVRH + /* 297 */ MCD_OPC_FilterValue, + 2, + 107, + 0, + 0, // Skip to: 409 + /* 302 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 305 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 357 + /* 310 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 313 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 335 + /* 318 */ MCD_OPC_CheckPredicate, + 74, + 184, + 20, + 0, // Skip to: 5627 + /* 323 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 177, + 20, + 0, // Skip to: 5627 + /* 330 */ MCD_OPC_Decode, + 146, + 23, + 208, + 3, // Opcode: VMULH + /* 335 */ MCD_OPC_FilterValue, + 29, + 167, + 20, + 0, // Skip to: 5627 + /* 340 */ MCD_OPC_CheckPredicate, + 74, + 162, + 20, + 0, // Skip to: 5627 + /* 345 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 155, + 20, + 0, // Skip to: 5627 + /* 352 */ MCD_OPC_Decode, + 183, + 18, + 207, + 3, // Opcode: VFMAH + /* 357 */ MCD_OPC_FilterValue, + 1, + 145, + 20, + 0, // Skip to: 5627 + /* 362 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 365 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 387 + /* 370 */ MCD_OPC_CheckPredicate, + 74, + 132, + 20, + 0, // Skip to: 5627 + /* 375 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 125, + 20, + 0, // Skip to: 5627 + /* 382 */ MCD_OPC_Decode, + 206, + 23, + 208, + 3, // Opcode: VNMULH + /* 387 */ MCD_OPC_FilterValue, + 29, + 115, + 20, + 0, // Skip to: 5627 + /* 392 */ MCD_OPC_CheckPredicate, + 74, + 110, + 20, + 0, // Skip to: 5627 + /* 397 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 103, + 20, + 0, // Skip to: 5627 + /* 404 */ MCD_OPC_Decode, + 194, + 18, + 207, + 3, // Opcode: VFMSH + /* 409 */ MCD_OPC_FilterValue, + 3, + 93, + 20, + 0, // Skip to: 5627 + /* 414 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 417 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 476 + /* 422 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 425 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 447 + /* 430 */ MCD_OPC_CheckPredicate, + 74, + 72, + 20, + 0, // Skip to: 5627 + /* 435 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 65, + 20, + 0, // Skip to: 5627 + /* 442 */ MCD_OPC_Decode, + 135, + 16, + 208, + 3, // Opcode: VADDH + /* 447 */ MCD_OPC_FilterValue, + 29, + 55, + 20, + 0, // Skip to: 5627 + /* 452 */ MCD_OPC_CheckPredicate, + 74, + 50, + 20, + 0, // Skip to: 5627 + /* 457 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 43, + 20, + 0, // Skip to: 5627 + /* 464 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 36, + 20, + 0, // Skip to: 5627 + /* 471 */ MCD_OPC_Decode, + 148, + 6, + 211, + 3, // Opcode: FCONSTH + /* 476 */ MCD_OPC_FilterValue, + 1, + 26, + 20, + 0, // Skip to: 5627 + /* 481 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 484 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 506 + /* 489 */ MCD_OPC_CheckPredicate, + 74, + 13, + 20, + 0, // Skip to: 5627 + /* 494 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 6, + 20, + 0, // Skip to: 5627 + /* 501 */ MCD_OPC_Decode, + 215, + 29, + 208, + 3, // Opcode: VSUBH + /* 506 */ MCD_OPC_FilterValue, + 29, + 252, + 19, + 0, // Skip to: 5627 + /* 511 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 514 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 543 + /* 519 */ MCD_OPC_CheckPredicate, + 74, + 239, + 19, + 0, // Skip to: 5627 + /* 524 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 232, + 19, + 0, // Skip to: 5627 + /* 531 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 225, + 19, + 0, // Skip to: 5627 + /* 538 */ MCD_OPC_Decode, + 242, + 15, + 212, + 3, // Opcode: VABSH + /* 543 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 595 + /* 548 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 551 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 573 + /* 556 */ MCD_OPC_CheckPredicate, + 74, + 202, + 19, + 0, // Skip to: 5627 + /* 561 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 195, + 19, + 0, // Skip to: 5627 + /* 568 */ MCD_OPC_Decode, + 187, + 23, + 212, + 3, // Opcode: VNEGH + /* 573 */ MCD_OPC_FilterValue, + 1, + 185, + 19, + 0, // Skip to: 5627 + /* 578 */ MCD_OPC_CheckPredicate, + 74, + 180, + 19, + 0, // Skip to: 5627 + /* 583 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 173, + 19, + 0, // Skip to: 5627 + /* 590 */ MCD_OPC_Decode, + 158, + 27, + 212, + 3, // Opcode: VSQRTH + /* 595 */ MCD_OPC_FilterValue, + 4, + 47, + 0, + 0, // Skip to: 647 + /* 600 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 603 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 625 + /* 608 */ MCD_OPC_CheckPredicate, + 74, + 150, + 19, + 0, // Skip to: 5627 + /* 613 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 143, + 19, + 0, // Skip to: 5627 + /* 620 */ MCD_OPC_Decode, + 179, + 17, + 212, + 3, // Opcode: VCMPH + /* 625 */ MCD_OPC_FilterValue, + 1, + 133, + 19, + 0, // Skip to: 5627 + /* 630 */ MCD_OPC_CheckPredicate, + 74, + 128, + 19, + 0, // Skip to: 5627 + /* 635 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 121, + 19, + 0, // Skip to: 5627 + /* 642 */ MCD_OPC_Decode, + 174, + 17, + 212, + 3, // Opcode: VCMPEH + /* 647 */ MCD_OPC_FilterValue, + 5, + 47, + 0, + 0, // Skip to: 699 + /* 652 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 655 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 677 + /* 660 */ MCD_OPC_CheckPredicate, + 74, + 98, + 19, + 0, // Skip to: 5627 + /* 665 */ MCD_OPC_CheckField, + 0, + 6, + 0, + 91, + 19, + 0, // Skip to: 5627 + /* 672 */ MCD_OPC_Decode, + 182, + 17, + 213, + 3, // Opcode: VCMPZH + /* 677 */ MCD_OPC_FilterValue, + 1, + 81, + 19, + 0, // Skip to: 5627 + /* 682 */ MCD_OPC_CheckPredicate, + 74, + 76, + 19, + 0, // Skip to: 5627 + /* 687 */ MCD_OPC_CheckField, + 0, + 6, + 0, + 69, + 19, + 0, // Skip to: 5627 + /* 694 */ MCD_OPC_Decode, + 177, + 17, + 213, + 3, // Opcode: VCMPEZH + /* 699 */ MCD_OPC_FilterValue, + 6, + 47, + 0, + 0, // Skip to: 751 + /* 704 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 707 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 729 + /* 712 */ MCD_OPC_CheckPredicate, + 74, + 46, + 19, + 0, // Skip to: 5627 + /* 717 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 39, + 19, + 0, // Skip to: 5627 + /* 724 */ MCD_OPC_Decode, + 242, + 25, + 212, + 3, // Opcode: VRINTRH + /* 729 */ MCD_OPC_FilterValue, + 1, + 29, + 19, + 0, // Skip to: 5627 + /* 734 */ MCD_OPC_CheckPredicate, + 74, + 24, + 19, + 0, // Skip to: 5627 + /* 739 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 17, + 19, + 0, // Skip to: 5627 + /* 746 */ MCD_OPC_Decode, + 252, + 25, + 212, + 3, // Opcode: VRINTZH + /* 751 */ MCD_OPC_FilterValue, + 7, + 24, + 0, + 0, // Skip to: 780 + /* 756 */ MCD_OPC_CheckPredicate, + 74, + 2, + 19, + 0, // Skip to: 5627 + /* 761 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 251, + 18, + 0, // Skip to: 5627 + /* 768 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 18, + 0, // Skip to: 5627 + /* 775 */ MCD_OPC_Decode, + 245, + 25, + 212, + 3, // Opcode: VRINTXH + /* 780 */ MCD_OPC_FilterValue, + 8, + 47, + 0, + 0, // Skip to: 832 + /* 785 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 788 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 810 + /* 793 */ MCD_OPC_CheckPredicate, + 74, + 221, + 18, + 0, // Skip to: 5627 + /* 798 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 214, + 18, + 0, // Skip to: 5627 + /* 805 */ MCD_OPC_Decode, + 176, + 30, + 214, + 3, // Opcode: VUITOH + /* 810 */ MCD_OPC_FilterValue, + 1, + 204, + 18, + 0, // Skip to: 5627 + /* 815 */ MCD_OPC_CheckPredicate, + 74, + 199, + 18, + 0, // Skip to: 5627 + /* 820 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 192, + 18, + 0, // Skip to: 5627 + /* 827 */ MCD_OPC_Decode, + 143, + 27, + 214, + 3, // Opcode: VSITOH + /* 832 */ MCD_OPC_FilterValue, + 10, + 47, + 0, + 0, // Skip to: 884 + /* 837 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 840 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 862 + /* 845 */ MCD_OPC_CheckPredicate, + 74, + 169, + 18, + 0, // Skip to: 5627 + /* 850 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 162, + 18, + 0, // Skip to: 5627 + /* 857 */ MCD_OPC_Decode, + 140, + 27, + 215, + 3, // Opcode: VSHTOH + /* 862 */ MCD_OPC_FilterValue, + 1, + 152, + 18, + 0, // Skip to: 5627 + /* 867 */ MCD_OPC_CheckPredicate, + 74, + 147, + 18, + 0, // Skip to: 5627 + /* 872 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 140, + 18, + 0, // Skip to: 5627 + /* 879 */ MCD_OPC_Decode, + 154, + 27, + 215, + 3, // Opcode: VSLTOH + /* 884 */ MCD_OPC_FilterValue, + 11, + 47, + 0, + 0, // Skip to: 936 + /* 889 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 892 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 914 + /* 897 */ MCD_OPC_CheckPredicate, + 74, + 117, + 18, + 0, // Skip to: 5627 + /* 902 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 110, + 18, + 0, // Skip to: 5627 + /* 909 */ MCD_OPC_Decode, + 173, + 30, + 215, + 3, // Opcode: VUHTOH + /* 914 */ MCD_OPC_FilterValue, + 1, + 100, + 18, + 0, // Skip to: 5627 + /* 919 */ MCD_OPC_CheckPredicate, + 74, + 95, + 18, + 0, // Skip to: 5627 + /* 924 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 88, + 18, + 0, // Skip to: 5627 + /* 931 */ MCD_OPC_Decode, + 179, + 30, + 215, + 3, // Opcode: VULTOH + /* 936 */ MCD_OPC_FilterValue, + 12, + 47, + 0, + 0, // Skip to: 988 + /* 941 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 944 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 966 + /* 949 */ MCD_OPC_CheckPredicate, + 74, + 65, + 18, + 0, // Skip to: 5627 + /* 954 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 58, + 18, + 0, // Skip to: 5627 + /* 961 */ MCD_OPC_Decode, + 148, + 30, + 216, + 3, // Opcode: VTOUIRH + /* 966 */ MCD_OPC_FilterValue, + 1, + 48, + 18, + 0, // Skip to: 5627 + /* 971 */ MCD_OPC_CheckPredicate, + 74, + 43, + 18, + 0, // Skip to: 5627 + /* 976 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 36, + 18, + 0, // Skip to: 5627 + /* 983 */ MCD_OPC_Decode, + 151, + 30, + 217, + 3, // Opcode: VTOUIZH + /* 988 */ MCD_OPC_FilterValue, + 13, + 47, + 0, + 0, // Skip to: 1040 + /* 993 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 996 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1018 + /* 1001 */ MCD_OPC_CheckPredicate, + 74, + 13, + 18, + 0, // Skip to: 5627 + /* 1006 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 6, + 18, + 0, // Skip to: 5627 + /* 1013 */ MCD_OPC_Decode, + 136, + 30, + 216, + 3, // Opcode: VTOSIRH + /* 1018 */ MCD_OPC_FilterValue, + 1, + 252, + 17, + 0, // Skip to: 5627 + /* 1023 */ MCD_OPC_CheckPredicate, + 74, + 247, + 17, + 0, // Skip to: 5627 + /* 1028 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 240, + 17, + 0, // Skip to: 5627 + /* 1035 */ MCD_OPC_Decode, + 139, + 30, + 217, + 3, // Opcode: VTOSIZH + /* 1040 */ MCD_OPC_FilterValue, + 14, + 47, + 0, + 0, // Skip to: 1092 + /* 1045 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1048 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1070 + /* 1053 */ MCD_OPC_CheckPredicate, + 74, + 217, + 17, + 0, // Skip to: 5627 + /* 1058 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 210, + 17, + 0, // Skip to: 5627 + /* 1065 */ MCD_OPC_Decode, + 133, + 30, + 215, + 3, // Opcode: VTOSHH + /* 1070 */ MCD_OPC_FilterValue, + 1, + 200, + 17, + 0, // Skip to: 5627 + /* 1075 */ MCD_OPC_CheckPredicate, + 74, + 195, + 17, + 0, // Skip to: 5627 + /* 1080 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 188, + 17, + 0, // Skip to: 5627 + /* 1087 */ MCD_OPC_Decode, + 142, + 30, + 215, + 3, // Opcode: VTOSLH + /* 1092 */ MCD_OPC_FilterValue, + 15, + 178, + 17, + 0, // Skip to: 5627 + /* 1097 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1100 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1122 + /* 1105 */ MCD_OPC_CheckPredicate, + 74, + 165, + 17, + 0, // Skip to: 5627 + /* 1110 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 158, + 17, + 0, // Skip to: 5627 + /* 1117 */ MCD_OPC_Decode, + 145, + 30, + 215, + 3, // Opcode: VTOUHH + /* 1122 */ MCD_OPC_FilterValue, + 1, + 148, + 17, + 0, // Skip to: 5627 + /* 1127 */ MCD_OPC_CheckPredicate, + 74, + 143, + 17, + 0, // Skip to: 5627 + /* 1132 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 136, + 17, + 0, // Skip to: 5627 + /* 1139 */ MCD_OPC_Decode, + 154, + 30, + 215, + 3, // Opcode: VTOULH + /* 1144 */ MCD_OPC_FilterValue, + 10, + 105, + 7, + 0, // Skip to: 3046 + /* 1149 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1152 */ MCD_OPC_FilterValue, + 0, + 189, + 0, + 0, // Skip to: 1346 + /* 1157 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 1160 */ MCD_OPC_FilterValue, + 12, + 54, + 0, + 0, // Skip to: 1219 + /* 1165 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1168 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 1204 + /* 1173 */ MCD_OPC_CheckPredicate, + 34, + 97, + 17, + 0, // Skip to: 5627 + /* 1178 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 90, + 17, + 0, // Skip to: 5627 + /* 1185 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 83, + 17, + 0, // Skip to: 5627 + /* 1192 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 76, + 17, + 0, // Skip to: 5627 + /* 1199 */ MCD_OPC_Decode, + 239, + 22, + 218, + 3, // Opcode: VMOVSRR + /* 1204 */ MCD_OPC_FilterValue, + 1, + 66, + 17, + 0, // Skip to: 5627 + /* 1209 */ MCD_OPC_CheckPredicate, + 34, + 61, + 17, + 0, // Skip to: 5627 + /* 1214 */ MCD_OPC_Decode, + 191, + 29, + 219, + 3, // Opcode: VSTMSIA + /* 1219 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1234 + /* 1224 */ MCD_OPC_CheckPredicate, + 34, + 46, + 17, + 0, // Skip to: 5627 + /* 1229 */ MCD_OPC_Decode, + 195, + 29, + 220, + 3, // Opcode: VSTRS + /* 1234 */ MCD_OPC_FilterValue, + 14, + 36, + 17, + 0, // Skip to: 5627 + /* 1239 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1242 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 1310 + /* 1247 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1250 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 1288 + /* 1255 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1258 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1273 + /* 1263 */ MCD_OPC_CheckPredicate, + 33, + 7, + 17, + 0, // Skip to: 5627 + /* 1268 */ MCD_OPC_Decode, + 169, + 22, + 221, + 3, // Opcode: VMLAS + /* 1273 */ MCD_OPC_FilterValue, + 1, + 253, + 16, + 0, // Skip to: 5627 + /* 1278 */ MCD_OPC_CheckPredicate, + 33, + 248, + 16, + 0, // Skip to: 5627 + /* 1283 */ MCD_OPC_Decode, + 160, + 18, + 222, + 3, // Opcode: VDIVS + /* 1288 */ MCD_OPC_FilterValue, + 1, + 238, + 16, + 0, // Skip to: 5627 + /* 1293 */ MCD_OPC_CheckPredicate, + 33, + 233, + 16, + 0, // Skip to: 5627 + /* 1298 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 226, + 16, + 0, // Skip to: 5627 + /* 1305 */ MCD_OPC_Decode, + 200, + 22, + 221, + 3, // Opcode: VMLSS + /* 1310 */ MCD_OPC_FilterValue, + 1, + 216, + 16, + 0, // Skip to: 5627 + /* 1315 */ MCD_OPC_CheckPredicate, + 34, + 211, + 16, + 0, // Skip to: 5627 + /* 1320 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 204, + 16, + 0, // Skip to: 5627 + /* 1327 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 197, + 16, + 0, // Skip to: 5627 + /* 1334 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 190, + 16, + 0, // Skip to: 5627 + /* 1341 */ MCD_OPC_Decode, + 238, + 22, + 223, + 3, // Opcode: VMOVSR + /* 1346 */ MCD_OPC_FilterValue, + 1, + 229, + 0, + 0, // Skip to: 1580 + /* 1351 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 1354 */ MCD_OPC_FilterValue, + 12, + 78, + 0, + 0, // Skip to: 1437 + /* 1359 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1362 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 1398 + /* 1367 */ MCD_OPC_CheckPredicate, + 34, + 159, + 16, + 0, // Skip to: 5627 + /* 1372 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 152, + 16, + 0, // Skip to: 5627 + /* 1379 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 145, + 16, + 0, // Skip to: 5627 + /* 1386 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 138, + 16, + 0, // Skip to: 5627 + /* 1393 */ MCD_OPC_Decode, + 235, + 22, + 224, + 3, // Opcode: VMOVRRS + /* 1398 */ MCD_OPC_FilterValue, + 1, + 128, + 16, + 0, // Skip to: 5627 + /* 1403 */ MCD_OPC_CheckPredicate, + 75, + 19, + 0, + 0, // Skip to: 1427 + /* 1408 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 12, + 0, + 0, // Skip to: 1427 + /* 1415 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 1427 + /* 1422 */ MCD_OPC_Decode, + 195, + 26, + 225, + 3, // Opcode: VSCCLRMS + /* 1427 */ MCD_OPC_CheckPredicate, + 34, + 99, + 16, + 0, // Skip to: 5627 + /* 1432 */ MCD_OPC_Decode, + 228, + 21, + 219, + 3, // Opcode: VLDMSIA + /* 1437 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1452 + /* 1442 */ MCD_OPC_CheckPredicate, + 34, + 84, + 16, + 0, // Skip to: 5627 + /* 1447 */ MCD_OPC_Decode, + 232, + 21, + 220, + 3, // Opcode: VLDRS + /* 1452 */ MCD_OPC_FilterValue, + 14, + 74, + 16, + 0, // Skip to: 5627 + /* 1457 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1460 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 1544 + /* 1465 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1468 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 1506 + /* 1473 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1476 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1491 + /* 1481 */ MCD_OPC_CheckPredicate, + 33, + 45, + 16, + 0, // Skip to: 5627 + /* 1486 */ MCD_OPC_Decode, + 204, + 23, + 221, + 3, // Opcode: VNMLSS + /* 1491 */ MCD_OPC_FilterValue, + 1, + 35, + 16, + 0, // Skip to: 5627 + /* 1496 */ MCD_OPC_CheckPredicate, + 76, + 30, + 16, + 0, // Skip to: 5627 + /* 1501 */ MCD_OPC_Decode, + 209, + 18, + 221, + 3, // Opcode: VFNMSS + /* 1506 */ MCD_OPC_FilterValue, + 1, + 20, + 16, + 0, // Skip to: 5627 + /* 1511 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 1514 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1529 + /* 1519 */ MCD_OPC_CheckPredicate, + 33, + 7, + 16, + 0, // Skip to: 5627 + /* 1524 */ MCD_OPC_Decode, + 201, + 23, + 221, + 3, // Opcode: VNMLAS + /* 1529 */ MCD_OPC_FilterValue, + 1, + 253, + 15, + 0, // Skip to: 5627 + /* 1534 */ MCD_OPC_CheckPredicate, + 76, + 248, + 15, + 0, // Skip to: 5627 + /* 1539 */ MCD_OPC_Decode, + 206, + 18, + 221, + 3, // Opcode: VFNMAS + /* 1544 */ MCD_OPC_FilterValue, + 1, + 238, + 15, + 0, // Skip to: 5627 + /* 1549 */ MCD_OPC_CheckPredicate, + 34, + 233, + 15, + 0, // Skip to: 5627 + /* 1554 */ MCD_OPC_CheckField, + 22, + 2, + 0, + 226, + 15, + 0, // Skip to: 5627 + /* 1561 */ MCD_OPC_CheckField, + 5, + 2, + 0, + 219, + 15, + 0, // Skip to: 5627 + /* 1568 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 212, + 15, + 0, // Skip to: 5627 + /* 1575 */ MCD_OPC_Decode, + 236, + 22, + 226, + 3, // Opcode: VMOVRS + /* 1580 */ MCD_OPC_FilterValue, + 2, + 179, + 1, + 0, // Skip to: 2020 + /* 1585 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 1588 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 1624 + /* 1593 */ MCD_OPC_CheckPredicate, + 77, + 189, + 15, + 0, // Skip to: 5627 + /* 1598 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 182, + 15, + 0, // Skip to: 5627 + /* 1605 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 175, + 15, + 0, // Skip to: 5627 + /* 1612 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 168, + 15, + 0, // Skip to: 5627 + /* 1619 */ MCD_OPC_Decode, + 252, + 21, + 227, + 3, // Opcode: VLSTM + /* 1624 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 1639 + /* 1629 */ MCD_OPC_CheckPredicate, + 34, + 153, + 15, + 0, // Skip to: 5627 + /* 1634 */ MCD_OPC_Decode, + 192, + 29, + 228, + 3, // Opcode: VSTMSIA_UPD + /* 1639 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 1654 + /* 1644 */ MCD_OPC_CheckPredicate, + 34, + 138, + 15, + 0, // Skip to: 5627 + /* 1649 */ MCD_OPC_Decode, + 190, + 29, + 228, + 3, // Opcode: VSTMSDB_UPD + /* 1654 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 1706 + /* 1659 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1662 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1684 + /* 1667 */ MCD_OPC_CheckPredicate, + 33, + 115, + 15, + 0, // Skip to: 5627 + /* 1672 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 108, + 15, + 0, // Skip to: 5627 + /* 1679 */ MCD_OPC_Decode, + 159, + 23, + 222, + 3, // Opcode: VMULS + /* 1684 */ MCD_OPC_FilterValue, + 1, + 98, + 15, + 0, // Skip to: 5627 + /* 1689 */ MCD_OPC_CheckPredicate, + 33, + 93, + 15, + 0, // Skip to: 5627 + /* 1694 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 86, + 15, + 0, // Skip to: 5627 + /* 1701 */ MCD_OPC_Decode, + 207, + 23, + 222, + 3, // Opcode: VNMULS + /* 1706 */ MCD_OPC_FilterValue, + 29, + 76, + 15, + 0, // Skip to: 5627 + /* 1711 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1714 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 1752 + /* 1719 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1722 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1737 + /* 1727 */ MCD_OPC_CheckPredicate, + 76, + 55, + 15, + 0, // Skip to: 5627 + /* 1732 */ MCD_OPC_Decode, + 188, + 18, + 221, + 3, // Opcode: VFMAS + /* 1737 */ MCD_OPC_FilterValue, + 1, + 45, + 15, + 0, // Skip to: 5627 + /* 1742 */ MCD_OPC_CheckPredicate, + 76, + 40, + 15, + 0, // Skip to: 5627 + /* 1747 */ MCD_OPC_Decode, + 199, + 18, + 221, + 3, // Opcode: VFMSS + /* 1752 */ MCD_OPC_FilterValue, + 1, + 30, + 15, + 0, // Skip to: 5627 + /* 1757 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 1760 */ MCD_OPC_FilterValue, + 0, + 21, + 0, + 0, // Skip to: 1786 + /* 1765 */ MCD_OPC_CheckPredicate, + 33, + 17, + 15, + 0, // Skip to: 5627 + /* 1770 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 10, + 15, + 0, // Skip to: 5627 + /* 1777 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1781 */ MCD_OPC_Decode, + 142, + 23, + 229, + 3, // Opcode: VMSR_FPSID + /* 1786 */ MCD_OPC_FilterValue, + 1, + 21, + 0, + 0, // Skip to: 1812 + /* 1791 */ MCD_OPC_CheckPredicate, + 34, + 247, + 14, + 0, // Skip to: 5627 + /* 1796 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 240, + 14, + 0, // Skip to: 5627 + /* 1803 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1807 */ MCD_OPC_Decode, + 135, + 23, + 229, + 3, // Opcode: VMSR + /* 1812 */ MCD_OPC_FilterValue, + 2, + 21, + 0, + 0, // Skip to: 1838 + /* 1817 */ MCD_OPC_CheckPredicate, + 78, + 221, + 14, + 0, // Skip to: 5627 + /* 1822 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 214, + 14, + 0, // Skip to: 5627 + /* 1829 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1833 */ MCD_OPC_Decode, + 141, + 23, + 229, + 3, // Opcode: VMSR_FPSCR_NZCVQC + /* 1838 */ MCD_OPC_FilterValue, + 8, + 21, + 0, + 0, // Skip to: 1864 + /* 1843 */ MCD_OPC_CheckPredicate, + 33, + 195, + 14, + 0, // Skip to: 5627 + /* 1848 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 188, + 14, + 0, // Skip to: 5627 + /* 1855 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1859 */ MCD_OPC_Decode, + 138, + 23, + 229, + 3, // Opcode: VMSR_FPEXC + /* 1864 */ MCD_OPC_FilterValue, + 9, + 21, + 0, + 0, // Skip to: 1890 + /* 1869 */ MCD_OPC_CheckPredicate, + 33, + 169, + 14, + 0, // Skip to: 5627 + /* 1874 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 162, + 14, + 0, // Skip to: 5627 + /* 1881 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1885 */ MCD_OPC_Decode, + 139, + 23, + 229, + 3, // Opcode: VMSR_FPINST + /* 1890 */ MCD_OPC_FilterValue, + 10, + 21, + 0, + 0, // Skip to: 1916 + /* 1895 */ MCD_OPC_CheckPredicate, + 33, + 143, + 14, + 0, // Skip to: 5627 + /* 1900 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 136, + 14, + 0, // Skip to: 5627 + /* 1907 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1911 */ MCD_OPC_Decode, + 140, + 23, + 229, + 3, // Opcode: VMSR_FPINST2 + /* 1916 */ MCD_OPC_FilterValue, + 12, + 21, + 0, + 0, // Skip to: 1942 + /* 1921 */ MCD_OPC_CheckPredicate, + 23, + 117, + 14, + 0, // Skip to: 5627 + /* 1926 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 110, + 14, + 0, // Skip to: 5627 + /* 1933 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1937 */ MCD_OPC_Decode, + 144, + 23, + 229, + 3, // Opcode: VMSR_VPR + /* 1942 */ MCD_OPC_FilterValue, + 13, + 21, + 0, + 0, // Skip to: 1968 + /* 1947 */ MCD_OPC_CheckPredicate, + 23, + 91, + 14, + 0, // Skip to: 5627 + /* 1952 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 84, + 14, + 0, // Skip to: 5627 + /* 1959 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1963 */ MCD_OPC_Decode, + 143, + 23, + 229, + 3, // Opcode: VMSR_P0 + /* 1968 */ MCD_OPC_FilterValue, + 14, + 21, + 0, + 0, // Skip to: 1994 + /* 1973 */ MCD_OPC_CheckPredicate, + 75, + 65, + 14, + 0, // Skip to: 5627 + /* 1978 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 58, + 14, + 0, // Skip to: 5627 + /* 1985 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 1989 */ MCD_OPC_Decode, + 136, + 23, + 229, + 3, // Opcode: VMSR_FPCXTNS + /* 1994 */ MCD_OPC_FilterValue, + 15, + 44, + 14, + 0, // Skip to: 5627 + /* 1999 */ MCD_OPC_CheckPredicate, + 75, + 39, + 14, + 0, // Skip to: 5627 + /* 2004 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 32, + 14, + 0, // Skip to: 5627 + /* 2011 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2015 */ MCD_OPC_Decode, + 137, + 23, + 229, + 3, // Opcode: VMSR_FPCXTS + /* 2020 */ MCD_OPC_FilterValue, + 3, + 18, + 14, + 0, // Skip to: 5627 + /* 2025 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 2028 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 2064 + /* 2033 */ MCD_OPC_CheckPredicate, + 77, + 5, + 14, + 0, // Skip to: 5627 + /* 2038 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 254, + 13, + 0, // Skip to: 5627 + /* 2045 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 247, + 13, + 0, // Skip to: 5627 + /* 2052 */ MCD_OPC_CheckField, + 0, + 8, + 0, + 240, + 13, + 0, // Skip to: 5627 + /* 2059 */ MCD_OPC_Decode, + 251, + 21, + 227, + 3, // Opcode: VLLDM + /* 2064 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 2079 + /* 2069 */ MCD_OPC_CheckPredicate, + 34, + 225, + 13, + 0, // Skip to: 5627 + /* 2074 */ MCD_OPC_Decode, + 229, + 21, + 228, + 3, // Opcode: VLDMSIA_UPD + /* 2079 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 2094 + /* 2084 */ MCD_OPC_CheckPredicate, + 34, + 210, + 13, + 0, // Skip to: 5627 + /* 2089 */ MCD_OPC_Decode, + 227, + 21, + 228, + 3, // Opcode: VLDMSDB_UPD + /* 2094 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 2146 + /* 2099 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2102 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2124 + /* 2107 */ MCD_OPC_CheckPredicate, + 33, + 187, + 13, + 0, // Skip to: 5627 + /* 2112 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 180, + 13, + 0, // Skip to: 5627 + /* 2119 */ MCD_OPC_Decode, + 145, + 16, + 222, + 3, // Opcode: VADDS + /* 2124 */ MCD_OPC_FilterValue, + 1, + 170, + 13, + 0, // Skip to: 5627 + /* 2129 */ MCD_OPC_CheckPredicate, + 33, + 165, + 13, + 0, // Skip to: 5627 + /* 2134 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 158, + 13, + 0, // Skip to: 5627 + /* 2141 */ MCD_OPC_Decode, + 225, + 29, + 222, + 3, // Opcode: VSUBS + /* 2146 */ MCD_OPC_FilterValue, + 29, + 148, + 13, + 0, // Skip to: 5627 + /* 2151 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2154 */ MCD_OPC_FilterValue, + 0, + 7, + 2, + 0, // Skip to: 2678 + /* 2159 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2162 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2184 + /* 2167 */ MCD_OPC_CheckPredicate, + 79, + 127, + 13, + 0, // Skip to: 5627 + /* 2172 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 120, + 13, + 0, // Skip to: 5627 + /* 2179 */ MCD_OPC_Decode, + 149, + 6, + 230, + 3, // Opcode: FCONSTS + /* 2184 */ MCD_OPC_FilterValue, + 1, + 242, + 0, + 0, // Skip to: 2431 + /* 2189 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2192 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2207 + /* 2197 */ MCD_OPC_CheckPredicate, + 34, + 97, + 13, + 0, // Skip to: 5627 + /* 2202 */ MCD_OPC_Decode, + 237, + 22, + 216, + 3, // Opcode: VMOVS + /* 2207 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2222 + /* 2212 */ MCD_OPC_CheckPredicate, + 33, + 82, + 13, + 0, // Skip to: 5627 + /* 2217 */ MCD_OPC_Decode, + 188, + 23, + 216, + 3, // Opcode: VNEGS + /* 2222 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2237 + /* 2227 */ MCD_OPC_CheckPredicate, + 80, + 67, + 13, + 0, // Skip to: 5627 + /* 2232 */ MCD_OPC_Decode, + 202, + 17, + 216, + 3, // Opcode: VCVTBHS + /* 2237 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 2252 + /* 2242 */ MCD_OPC_CheckPredicate, + 80, + 52, + 13, + 0, // Skip to: 5627 + /* 2247 */ MCD_OPC_Decode, + 203, + 17, + 216, + 3, // Opcode: VCVTBSH + /* 2252 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 2267 + /* 2257 */ MCD_OPC_CheckPredicate, + 33, + 37, + 13, + 0, // Skip to: 5627 + /* 2262 */ MCD_OPC_Decode, + 180, + 17, + 216, + 3, // Opcode: VCMPS + /* 2267 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 2296 + /* 2272 */ MCD_OPC_CheckPredicate, + 33, + 22, + 13, + 0, // Skip to: 5627 + /* 2277 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 15, + 13, + 0, // Skip to: 5627 + /* 2284 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 8, + 13, + 0, // Skip to: 5627 + /* 2291 */ MCD_OPC_Decode, + 183, + 17, + 231, + 3, // Opcode: VCMPZS + /* 2296 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 2311 + /* 2301 */ MCD_OPC_CheckPredicate, + 81, + 249, + 12, + 0, // Skip to: 5627 + /* 2306 */ MCD_OPC_Decode, + 243, + 25, + 216, + 3, // Opcode: VRINTRS + /* 2311 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 2326 + /* 2316 */ MCD_OPC_CheckPredicate, + 81, + 234, + 12, + 0, // Skip to: 5627 + /* 2321 */ MCD_OPC_Decode, + 250, + 25, + 216, + 3, // Opcode: VRINTXS + /* 2326 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 2341 + /* 2331 */ MCD_OPC_CheckPredicate, + 33, + 219, + 12, + 0, // Skip to: 5627 + /* 2336 */ MCD_OPC_Decode, + 177, + 30, + 216, + 3, // Opcode: VUITOS + /* 2341 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 2356 + /* 2346 */ MCD_OPC_CheckPredicate, + 33, + 204, + 12, + 0, // Skip to: 5627 + /* 2351 */ MCD_OPC_Decode, + 141, + 27, + 215, + 3, // Opcode: VSHTOS + /* 2356 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 2371 + /* 2361 */ MCD_OPC_CheckPredicate, + 33, + 189, + 12, + 0, // Skip to: 5627 + /* 2366 */ MCD_OPC_Decode, + 174, + 30, + 215, + 3, // Opcode: VUHTOS + /* 2371 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 2386 + /* 2376 */ MCD_OPC_CheckPredicate, + 33, + 174, + 12, + 0, // Skip to: 5627 + /* 2381 */ MCD_OPC_Decode, + 149, + 30, + 216, + 3, // Opcode: VTOUIRS + /* 2386 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2401 + /* 2391 */ MCD_OPC_CheckPredicate, + 33, + 159, + 12, + 0, // Skip to: 5627 + /* 2396 */ MCD_OPC_Decode, + 137, + 30, + 216, + 3, // Opcode: VTOSIRS + /* 2401 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 2416 + /* 2406 */ MCD_OPC_CheckPredicate, + 33, + 144, + 12, + 0, // Skip to: 5627 + /* 2411 */ MCD_OPC_Decode, + 134, + 30, + 215, + 3, // Opcode: VTOSHS + /* 2416 */ MCD_OPC_FilterValue, + 15, + 134, + 12, + 0, // Skip to: 5627 + /* 2421 */ MCD_OPC_CheckPredicate, + 33, + 129, + 12, + 0, // Skip to: 5627 + /* 2426 */ MCD_OPC_Decode, + 146, + 30, + 215, + 3, // Opcode: VTOUHS + /* 2431 */ MCD_OPC_FilterValue, + 3, + 119, + 12, + 0, // Skip to: 5627 + /* 2436 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2439 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2454 + /* 2444 */ MCD_OPC_CheckPredicate, + 33, + 106, + 12, + 0, // Skip to: 5627 + /* 2449 */ MCD_OPC_Decode, + 243, + 15, + 216, + 3, // Opcode: VABSS + /* 2454 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2469 + /* 2459 */ MCD_OPC_CheckPredicate, + 33, + 91, + 12, + 0, // Skip to: 5627 + /* 2464 */ MCD_OPC_Decode, + 159, + 27, + 216, + 3, // Opcode: VSQRTS + /* 2469 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2484 + /* 2474 */ MCD_OPC_CheckPredicate, + 80, + 76, + 12, + 0, // Skip to: 5627 + /* 2479 */ MCD_OPC_Decode, + 250, + 17, + 216, + 3, // Opcode: VCVTTHS + /* 2484 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 2499 + /* 2489 */ MCD_OPC_CheckPredicate, + 80, + 61, + 12, + 0, // Skip to: 5627 + /* 2494 */ MCD_OPC_Decode, + 251, + 17, + 216, + 3, // Opcode: VCVTTSH + /* 2499 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 2514 + /* 2504 */ MCD_OPC_CheckPredicate, + 33, + 46, + 12, + 0, // Skip to: 5627 + /* 2509 */ MCD_OPC_Decode, + 175, + 17, + 216, + 3, // Opcode: VCMPES + /* 2514 */ MCD_OPC_FilterValue, + 5, + 24, + 0, + 0, // Skip to: 2543 + /* 2519 */ MCD_OPC_CheckPredicate, + 33, + 31, + 12, + 0, // Skip to: 5627 + /* 2524 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 24, + 12, + 0, // Skip to: 5627 + /* 2531 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 17, + 12, + 0, // Skip to: 5627 + /* 2538 */ MCD_OPC_Decode, + 178, + 17, + 231, + 3, // Opcode: VCMPEZS + /* 2543 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 2558 + /* 2548 */ MCD_OPC_CheckPredicate, + 81, + 2, + 12, + 0, // Skip to: 5627 + /* 2553 */ MCD_OPC_Decode, + 129, + 26, + 216, + 3, // Opcode: VRINTZS + /* 2558 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 2573 + /* 2563 */ MCD_OPC_CheckPredicate, + 82, + 243, + 11, + 0, // Skip to: 5627 + /* 2568 */ MCD_OPC_Decode, + 204, + 17, + 232, + 3, // Opcode: VCVTDS + /* 2573 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 2588 + /* 2578 */ MCD_OPC_CheckPredicate, + 33, + 228, + 11, + 0, // Skip to: 5627 + /* 2583 */ MCD_OPC_Decode, + 144, + 27, + 216, + 3, // Opcode: VSITOS + /* 2588 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 2603 + /* 2593 */ MCD_OPC_CheckPredicate, + 33, + 213, + 11, + 0, // Skip to: 5627 + /* 2598 */ MCD_OPC_Decode, + 155, + 27, + 215, + 3, // Opcode: VSLTOS + /* 2603 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 2618 + /* 2608 */ MCD_OPC_CheckPredicate, + 33, + 198, + 11, + 0, // Skip to: 5627 + /* 2613 */ MCD_OPC_Decode, + 180, + 30, + 215, + 3, // Opcode: VULTOS + /* 2618 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 2633 + /* 2623 */ MCD_OPC_CheckPredicate, + 33, + 183, + 11, + 0, // Skip to: 5627 + /* 2628 */ MCD_OPC_Decode, + 152, + 30, + 216, + 3, // Opcode: VTOUIZS + /* 2633 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2648 + /* 2638 */ MCD_OPC_CheckPredicate, + 33, + 168, + 11, + 0, // Skip to: 5627 + /* 2643 */ MCD_OPC_Decode, + 140, + 30, + 216, + 3, // Opcode: VTOSIZS + /* 2648 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 2663 + /* 2653 */ MCD_OPC_CheckPredicate, + 33, + 153, + 11, + 0, // Skip to: 5627 + /* 2658 */ MCD_OPC_Decode, + 143, + 30, + 215, + 3, // Opcode: VTOSLS + /* 2663 */ MCD_OPC_FilterValue, + 15, + 143, + 11, + 0, // Skip to: 5627 + /* 2668 */ MCD_OPC_CheckPredicate, + 33, + 138, + 11, + 0, // Skip to: 5627 + /* 2673 */ MCD_OPC_Decode, + 155, + 30, + 215, + 3, // Opcode: VTOULS + /* 2678 */ MCD_OPC_FilterValue, + 1, + 128, + 11, + 0, // Skip to: 5627 + /* 2683 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2686 */ MCD_OPC_FilterValue, + 0, + 21, + 0, + 0, // Skip to: 2712 + /* 2691 */ MCD_OPC_CheckPredicate, + 33, + 115, + 11, + 0, // Skip to: 5627 + /* 2696 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 108, + 11, + 0, // Skip to: 5627 + /* 2703 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2707 */ MCD_OPC_Decode, + 129, + 23, + 229, + 3, // Opcode: VMRS_FPSID + /* 2712 */ MCD_OPC_FilterValue, + 1, + 43, + 0, + 0, // Skip to: 2760 + /* 2717 */ MCD_OPC_ExtractField, + 22, + 1, // Inst{22} ... + /* 2720 */ MCD_OPC_FilterValue, + 1, + 86, + 11, + 0, // Skip to: 5627 + /* 2725 */ MCD_OPC_CheckPredicate, + 34, + 16, + 0, + 0, // Skip to: 2746 + /* 2730 */ MCD_OPC_CheckField, + 12, + 4, + 15, + 9, + 0, + 0, // Skip to: 2746 + /* 2737 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2741 */ MCD_OPC_Decode, + 153, + 6, + 229, + 3, // Opcode: FMSTAT + /* 2746 */ MCD_OPC_CheckPredicate, + 34, + 60, + 11, + 0, // Skip to: 5627 + /* 2751 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2755 */ MCD_OPC_Decode, + 250, + 22, + 229, + 3, // Opcode: VMRS + /* 2760 */ MCD_OPC_FilterValue, + 2, + 21, + 0, + 0, // Skip to: 2786 + /* 2765 */ MCD_OPC_CheckPredicate, + 78, + 41, + 11, + 0, // Skip to: 5627 + /* 2770 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 34, + 11, + 0, // Skip to: 5627 + /* 2777 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2781 */ MCD_OPC_Decode, + 128, + 23, + 229, + 3, // Opcode: VMRS_FPSCR_NZCVQC + /* 2786 */ MCD_OPC_FilterValue, + 5, + 21, + 0, + 0, // Skip to: 2812 + /* 2791 */ MCD_OPC_CheckPredicate, + 81, + 15, + 11, + 0, // Skip to: 5627 + /* 2796 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 8, + 11, + 0, // Skip to: 5627 + /* 2803 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2807 */ MCD_OPC_Decode, + 132, + 23, + 229, + 3, // Opcode: VMRS_MVFR2 + /* 2812 */ MCD_OPC_FilterValue, + 6, + 21, + 0, + 0, // Skip to: 2838 + /* 2817 */ MCD_OPC_CheckPredicate, + 33, + 245, + 10, + 0, // Skip to: 5627 + /* 2822 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 238, + 10, + 0, // Skip to: 5627 + /* 2829 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2833 */ MCD_OPC_Decode, + 131, + 23, + 229, + 3, // Opcode: VMRS_MVFR1 + /* 2838 */ MCD_OPC_FilterValue, + 7, + 21, + 0, + 0, // Skip to: 2864 + /* 2843 */ MCD_OPC_CheckPredicate, + 33, + 219, + 10, + 0, // Skip to: 5627 + /* 2848 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 212, + 10, + 0, // Skip to: 5627 + /* 2855 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2859 */ MCD_OPC_Decode, + 130, + 23, + 229, + 3, // Opcode: VMRS_MVFR0 + /* 2864 */ MCD_OPC_FilterValue, + 8, + 21, + 0, + 0, // Skip to: 2890 + /* 2869 */ MCD_OPC_CheckPredicate, + 33, + 193, + 10, + 0, // Skip to: 5627 + /* 2874 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 186, + 10, + 0, // Skip to: 5627 + /* 2881 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2885 */ MCD_OPC_Decode, + 253, + 22, + 229, + 3, // Opcode: VMRS_FPEXC + /* 2890 */ MCD_OPC_FilterValue, + 9, + 21, + 0, + 0, // Skip to: 2916 + /* 2895 */ MCD_OPC_CheckPredicate, + 33, + 167, + 10, + 0, // Skip to: 5627 + /* 2900 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 160, + 10, + 0, // Skip to: 5627 + /* 2907 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2911 */ MCD_OPC_Decode, + 254, + 22, + 229, + 3, // Opcode: VMRS_FPINST + /* 2916 */ MCD_OPC_FilterValue, + 10, + 21, + 0, + 0, // Skip to: 2942 + /* 2921 */ MCD_OPC_CheckPredicate, + 33, + 141, + 10, + 0, // Skip to: 5627 + /* 2926 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 134, + 10, + 0, // Skip to: 5627 + /* 2933 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2937 */ MCD_OPC_Decode, + 255, + 22, + 229, + 3, // Opcode: VMRS_FPINST2 + /* 2942 */ MCD_OPC_FilterValue, + 12, + 21, + 0, + 0, // Skip to: 2968 + /* 2947 */ MCD_OPC_CheckPredicate, + 23, + 115, + 10, + 0, // Skip to: 5627 + /* 2952 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 108, + 10, + 0, // Skip to: 5627 + /* 2959 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2963 */ MCD_OPC_Decode, + 134, + 23, + 229, + 3, // Opcode: VMRS_VPR + /* 2968 */ MCD_OPC_FilterValue, + 13, + 21, + 0, + 0, // Skip to: 2994 + /* 2973 */ MCD_OPC_CheckPredicate, + 23, + 89, + 10, + 0, // Skip to: 5627 + /* 2978 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 82, + 10, + 0, // Skip to: 5627 + /* 2985 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 2989 */ MCD_OPC_Decode, + 133, + 23, + 229, + 3, // Opcode: VMRS_P0 + /* 2994 */ MCD_OPC_FilterValue, + 14, + 21, + 0, + 0, // Skip to: 3020 + /* 2999 */ MCD_OPC_CheckPredicate, + 75, + 63, + 10, + 0, // Skip to: 5627 + /* 3004 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 56, + 10, + 0, // Skip to: 5627 + /* 3011 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 3015 */ MCD_OPC_Decode, + 251, + 22, + 229, + 3, // Opcode: VMRS_FPCXTNS + /* 3020 */ MCD_OPC_FilterValue, + 15, + 42, + 10, + 0, // Skip to: 5627 + /* 3025 */ MCD_OPC_CheckPredicate, + 75, + 37, + 10, + 0, // Skip to: 5627 + /* 3030 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 30, + 10, + 0, // Skip to: 5627 + /* 3037 */ MCD_OPC_SoftFail, + 239, + 1 /* 0xef */, + 0, + /* 3041 */ MCD_OPC_Decode, + 252, + 22, + 229, + 3, // Opcode: VMRS_FPCXTS + /* 3046 */ MCD_OPC_FilterValue, + 11, + 252, + 5, + 0, // Skip to: 4583 + /* 3051 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3054 */ MCD_OPC_FilterValue, + 0, + 196, + 0, + 0, // Skip to: 3255 + /* 3059 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 3062 */ MCD_OPC_FilterValue, + 12, + 84, + 0, + 0, // Skip to: 3151 + /* 3067 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3070 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 3106 + /* 3075 */ MCD_OPC_CheckPredicate, + 34, + 243, + 9, + 0, // Skip to: 5627 + /* 3080 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 236, + 9, + 0, // Skip to: 5627 + /* 3087 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 229, + 9, + 0, // Skip to: 5627 + /* 3094 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 222, + 9, + 0, // Skip to: 5627 + /* 3101 */ MCD_OPC_Decode, + 221, + 22, + 233, + 3, // Opcode: VMOVDRR + /* 3106 */ MCD_OPC_FilterValue, + 1, + 212, + 9, + 0, // Skip to: 5627 + /* 3111 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3114 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3129 + /* 3119 */ MCD_OPC_CheckPredicate, + 34, + 199, + 9, + 0, // Skip to: 5627 + /* 3124 */ MCD_OPC_Decode, + 187, + 29, + 234, + 3, // Opcode: VSTMDIA + /* 3129 */ MCD_OPC_FilterValue, + 1, + 189, + 9, + 0, // Skip to: 5627 + /* 3134 */ MCD_OPC_CheckPredicate, + 34, + 184, + 9, + 0, // Skip to: 5627 + /* 3139 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 177, + 9, + 0, // Skip to: 5627 + /* 3146 */ MCD_OPC_Decode, + 155, + 6, + 235, + 3, // Opcode: FSTMXIA + /* 3151 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3166 + /* 3156 */ MCD_OPC_CheckPredicate, + 34, + 162, + 9, + 0, // Skip to: 5627 + /* 3161 */ MCD_OPC_Decode, + 193, + 29, + 236, + 3, // Opcode: VSTRD + /* 3166 */ MCD_OPC_FilterValue, + 14, + 152, + 9, + 0, // Skip to: 5627 + /* 3171 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3174 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 3226 + /* 3179 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3182 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3204 + /* 3187 */ MCD_OPC_CheckPredicate, + 82, + 131, + 9, + 0, // Skip to: 5627 + /* 3192 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 124, + 9, + 0, // Skip to: 5627 + /* 3199 */ MCD_OPC_Decode, + 157, + 22, + 237, + 3, // Opcode: VMLAD + /* 3204 */ MCD_OPC_FilterValue, + 1, + 114, + 9, + 0, // Skip to: 5627 + /* 3209 */ MCD_OPC_CheckPredicate, + 82, + 109, + 9, + 0, // Skip to: 5627 + /* 3214 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 102, + 9, + 0, // Skip to: 5627 + /* 3221 */ MCD_OPC_Decode, + 158, + 18, + 238, + 3, // Opcode: VDIVD + /* 3226 */ MCD_OPC_FilterValue, + 1, + 92, + 9, + 0, // Skip to: 5627 + /* 3231 */ MCD_OPC_CheckPredicate, + 82, + 87, + 9, + 0, // Skip to: 5627 + /* 3236 */ MCD_OPC_CheckField, + 23, + 1, + 0, + 80, + 9, + 0, // Skip to: 5627 + /* 3243 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 73, + 9, + 0, // Skip to: 5627 + /* 3250 */ MCD_OPC_Decode, + 188, + 22, + 237, + 3, // Opcode: VMLSD + /* 3255 */ MCD_OPC_FilterValue, + 1, + 243, + 0, + 0, // Skip to: 3503 + /* 3260 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 3263 */ MCD_OPC_FilterValue, + 12, + 108, + 0, + 0, // Skip to: 3376 + /* 3268 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3271 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 3307 + /* 3276 */ MCD_OPC_CheckPredicate, + 34, + 42, + 9, + 0, // Skip to: 5627 + /* 3281 */ MCD_OPC_CheckField, + 22, + 1, + 1, + 35, + 9, + 0, // Skip to: 5627 + /* 3288 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 28, + 9, + 0, // Skip to: 5627 + /* 3295 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 21, + 9, + 0, // Skip to: 5627 + /* 3302 */ MCD_OPC_Decode, + 234, + 22, + 239, + 3, // Opcode: VMOVRRD + /* 3307 */ MCD_OPC_FilterValue, + 1, + 11, + 9, + 0, // Skip to: 5627 + /* 3312 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3315 */ MCD_OPC_FilterValue, + 0, + 34, + 0, + 0, // Skip to: 3354 + /* 3320 */ MCD_OPC_CheckPredicate, + 75, + 19, + 0, + 0, // Skip to: 3344 + /* 3325 */ MCD_OPC_CheckField, + 28, + 4, + 14, + 12, + 0, + 0, // Skip to: 3344 + /* 3332 */ MCD_OPC_CheckField, + 16, + 4, + 15, + 5, + 0, + 0, // Skip to: 3344 + /* 3339 */ MCD_OPC_Decode, + 194, + 26, + 225, + 3, // Opcode: VSCCLRMD + /* 3344 */ MCD_OPC_CheckPredicate, + 34, + 230, + 8, + 0, // Skip to: 5627 + /* 3349 */ MCD_OPC_Decode, + 224, + 21, + 234, + 3, // Opcode: VLDMDIA + /* 3354 */ MCD_OPC_FilterValue, + 1, + 220, + 8, + 0, // Skip to: 5627 + /* 3359 */ MCD_OPC_CheckPredicate, + 34, + 215, + 8, + 0, // Skip to: 5627 + /* 3364 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 208, + 8, + 0, // Skip to: 5627 + /* 3371 */ MCD_OPC_Decode, + 151, + 6, + 235, + 3, // Opcode: FLDMXIA + /* 3376 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 3391 + /* 3381 */ MCD_OPC_CheckPredicate, + 34, + 193, + 8, + 0, // Skip to: 5627 + /* 3386 */ MCD_OPC_Decode, + 230, + 21, + 236, + 3, // Opcode: VLDRD + /* 3391 */ MCD_OPC_FilterValue, + 14, + 183, + 8, + 0, // Skip to: 5627 + /* 3396 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3399 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 3451 + /* 3404 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3407 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3429 + /* 3412 */ MCD_OPC_CheckPredicate, + 82, + 162, + 8, + 0, // Skip to: 5627 + /* 3417 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 155, + 8, + 0, // Skip to: 5627 + /* 3424 */ MCD_OPC_Decode, + 202, + 23, + 237, + 3, // Opcode: VNMLSD + /* 3429 */ MCD_OPC_FilterValue, + 1, + 145, + 8, + 0, // Skip to: 5627 + /* 3434 */ MCD_OPC_CheckPredicate, + 83, + 140, + 8, + 0, // Skip to: 5627 + /* 3439 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 133, + 8, + 0, // Skip to: 5627 + /* 3446 */ MCD_OPC_Decode, + 207, + 18, + 237, + 3, // Opcode: VFNMSD + /* 3451 */ MCD_OPC_FilterValue, + 1, + 123, + 8, + 0, // Skip to: 5627 + /* 3456 */ MCD_OPC_ExtractField, + 23, + 1, // Inst{23} ... + /* 3459 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3481 + /* 3464 */ MCD_OPC_CheckPredicate, + 82, + 110, + 8, + 0, // Skip to: 5627 + /* 3469 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 103, + 8, + 0, // Skip to: 5627 + /* 3476 */ MCD_OPC_Decode, + 199, + 23, + 237, + 3, // Opcode: VNMLAD + /* 3481 */ MCD_OPC_FilterValue, + 1, + 93, + 8, + 0, // Skip to: 5627 + /* 3486 */ MCD_OPC_CheckPredicate, + 83, + 88, + 8, + 0, // Skip to: 5627 + /* 3491 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 81, + 8, + 0, // Skip to: 5627 + /* 3498 */ MCD_OPC_Decode, + 204, + 18, + 237, + 3, // Opcode: VFNMAD + /* 3503 */ MCD_OPC_FilterValue, + 2, + 197, + 0, + 0, // Skip to: 3705 + /* 3508 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 3511 */ MCD_OPC_FilterValue, + 25, + 40, + 0, + 0, // Skip to: 3556 + /* 3516 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3519 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3534 + /* 3524 */ MCD_OPC_CheckPredicate, + 34, + 50, + 8, + 0, // Skip to: 5627 + /* 3529 */ MCD_OPC_Decode, + 188, + 29, + 240, + 3, // Opcode: VSTMDIA_UPD + /* 3534 */ MCD_OPC_FilterValue, + 1, + 40, + 8, + 0, // Skip to: 5627 + /* 3539 */ MCD_OPC_CheckPredicate, + 34, + 35, + 8, + 0, // Skip to: 5627 + /* 3544 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 28, + 8, + 0, // Skip to: 5627 + /* 3551 */ MCD_OPC_Decode, + 156, + 6, + 241, + 3, // Opcode: FSTMXIA_UPD + /* 3556 */ MCD_OPC_FilterValue, + 26, + 40, + 0, + 0, // Skip to: 3601 + /* 3561 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3564 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3579 + /* 3569 */ MCD_OPC_CheckPredicate, + 34, + 5, + 8, + 0, // Skip to: 5627 + /* 3574 */ MCD_OPC_Decode, + 186, + 29, + 240, + 3, // Opcode: VSTMDDB_UPD + /* 3579 */ MCD_OPC_FilterValue, + 1, + 251, + 7, + 0, // Skip to: 5627 + /* 3584 */ MCD_OPC_CheckPredicate, + 34, + 246, + 7, + 0, // Skip to: 5627 + /* 3589 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 239, + 7, + 0, // Skip to: 5627 + /* 3596 */ MCD_OPC_Decode, + 154, + 6, + 241, + 3, // Opcode: FSTMXDB_UPD + /* 3601 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 3653 + /* 3606 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3609 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3631 + /* 3614 */ MCD_OPC_CheckPredicate, + 82, + 216, + 7, + 0, // Skip to: 5627 + /* 3619 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 209, + 7, + 0, // Skip to: 5627 + /* 3626 */ MCD_OPC_Decode, + 145, + 23, + 238, + 3, // Opcode: VMULD + /* 3631 */ MCD_OPC_FilterValue, + 1, + 199, + 7, + 0, // Skip to: 5627 + /* 3636 */ MCD_OPC_CheckPredicate, + 82, + 194, + 7, + 0, // Skip to: 5627 + /* 3641 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 187, + 7, + 0, // Skip to: 5627 + /* 3648 */ MCD_OPC_Decode, + 205, + 23, + 238, + 3, // Opcode: VNMULD + /* 3653 */ MCD_OPC_FilterValue, + 29, + 177, + 7, + 0, // Skip to: 5627 + /* 3658 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3661 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3683 + /* 3666 */ MCD_OPC_CheckPredicate, + 83, + 164, + 7, + 0, // Skip to: 5627 + /* 3671 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 7, + 0, // Skip to: 5627 + /* 3678 */ MCD_OPC_Decode, + 182, + 18, + 237, + 3, // Opcode: VFMAD + /* 3683 */ MCD_OPC_FilterValue, + 1, + 147, + 7, + 0, // Skip to: 5627 + /* 3688 */ MCD_OPC_CheckPredicate, + 83, + 142, + 7, + 0, // Skip to: 5627 + /* 3693 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 135, + 7, + 0, // Skip to: 5627 + /* 3700 */ MCD_OPC_Decode, + 193, + 18, + 237, + 3, // Opcode: VFMSD + /* 3705 */ MCD_OPC_FilterValue, + 3, + 125, + 7, + 0, // Skip to: 5627 + /* 3710 */ MCD_OPC_ExtractField, + 23, + 5, // Inst{27-23} ... + /* 3713 */ MCD_OPC_FilterValue, + 25, + 40, + 0, + 0, // Skip to: 3758 + /* 3718 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3721 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3736 + /* 3726 */ MCD_OPC_CheckPredicate, + 34, + 104, + 7, + 0, // Skip to: 5627 + /* 3731 */ MCD_OPC_Decode, + 225, + 21, + 240, + 3, // Opcode: VLDMDIA_UPD + /* 3736 */ MCD_OPC_FilterValue, + 1, + 94, + 7, + 0, // Skip to: 5627 + /* 3741 */ MCD_OPC_CheckPredicate, + 34, + 89, + 7, + 0, // Skip to: 5627 + /* 3746 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 82, + 7, + 0, // Skip to: 5627 + /* 3753 */ MCD_OPC_Decode, + 152, + 6, + 241, + 3, // Opcode: FLDMXIA_UPD + /* 3758 */ MCD_OPC_FilterValue, + 26, + 40, + 0, + 0, // Skip to: 3803 + /* 3763 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 3766 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3781 + /* 3771 */ MCD_OPC_CheckPredicate, + 34, + 59, + 7, + 0, // Skip to: 5627 + /* 3776 */ MCD_OPC_Decode, + 223, + 21, + 240, + 3, // Opcode: VLDMDDB_UPD + /* 3781 */ MCD_OPC_FilterValue, + 1, + 49, + 7, + 0, // Skip to: 5627 + /* 3786 */ MCD_OPC_CheckPredicate, + 34, + 44, + 7, + 0, // Skip to: 5627 + /* 3791 */ MCD_OPC_CheckField, + 22, + 1, + 0, + 37, + 7, + 0, // Skip to: 5627 + /* 3798 */ MCD_OPC_Decode, + 150, + 6, + 241, + 3, // Opcode: FLDMXDB_UPD + /* 3803 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 3855 + /* 3808 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3811 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3833 + /* 3816 */ MCD_OPC_CheckPredicate, + 82, + 14, + 7, + 0, // Skip to: 5627 + /* 3821 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 7, + 7, + 0, // Skip to: 5627 + /* 3828 */ MCD_OPC_Decode, + 134, + 16, + 238, + 3, // Opcode: VADDD + /* 3833 */ MCD_OPC_FilterValue, + 1, + 253, + 6, + 0, // Skip to: 5627 + /* 3838 */ MCD_OPC_CheckPredicate, + 82, + 248, + 6, + 0, // Skip to: 5627 + /* 3843 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 241, + 6, + 0, // Skip to: 5627 + /* 3850 */ MCD_OPC_Decode, + 214, + 29, + 238, + 3, // Opcode: VSUBD + /* 3855 */ MCD_OPC_FilterValue, + 29, + 231, + 6, + 0, // Skip to: 5627 + /* 3860 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 3863 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3885 + /* 3868 */ MCD_OPC_CheckPredicate, + 84, + 218, + 6, + 0, // Skip to: 5627 + /* 3873 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 211, + 6, + 0, // Skip to: 5627 + /* 3880 */ MCD_OPC_Decode, + 147, + 6, + 242, + 3, // Opcode: FCONSTD + /* 3885 */ MCD_OPC_FilterValue, + 1, + 77, + 1, + 0, // Skip to: 4223 + /* 3890 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 3893 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3915 + /* 3898 */ MCD_OPC_CheckPredicate, + 85, + 188, + 6, + 0, // Skip to: 5627 + /* 3903 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 6, + 0, // Skip to: 5627 + /* 3910 */ MCD_OPC_Decode, + 220, + 22, + 243, + 3, // Opcode: VMOVD + /* 3915 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 3937 + /* 3920 */ MCD_OPC_CheckPredicate, + 82, + 166, + 6, + 0, // Skip to: 5627 + /* 3925 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 159, + 6, + 0, // Skip to: 5627 + /* 3932 */ MCD_OPC_Decode, + 186, + 23, + 243, + 3, // Opcode: VNEGD + /* 3937 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 3959 + /* 3942 */ MCD_OPC_CheckPredicate, + 86, + 144, + 6, + 0, // Skip to: 5627 + /* 3947 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 137, + 6, + 0, // Skip to: 5627 + /* 3954 */ MCD_OPC_Decode, + 201, + 17, + 232, + 3, // Opcode: VCVTBHD + /* 3959 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 3981 + /* 3964 */ MCD_OPC_CheckPredicate, + 86, + 122, + 6, + 0, // Skip to: 5627 + /* 3969 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 115, + 6, + 0, // Skip to: 5627 + /* 3976 */ MCD_OPC_Decode, + 200, + 17, + 244, + 3, // Opcode: VCVTBDH + /* 3981 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 4003 + /* 3986 */ MCD_OPC_CheckPredicate, + 82, + 100, + 6, + 0, // Skip to: 5627 + /* 3991 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 93, + 6, + 0, // Skip to: 5627 + /* 3998 */ MCD_OPC_Decode, + 172, + 17, + 243, + 3, // Opcode: VCMPD + /* 4003 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 4025 + /* 4008 */ MCD_OPC_CheckPredicate, + 82, + 78, + 6, + 0, // Skip to: 5627 + /* 4013 */ MCD_OPC_CheckField, + 0, + 6, + 0, + 71, + 6, + 0, // Skip to: 5627 + /* 4020 */ MCD_OPC_Decode, + 181, + 17, + 245, + 3, // Opcode: VCMPZD + /* 4025 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 4047 + /* 4030 */ MCD_OPC_CheckPredicate, + 86, + 56, + 6, + 0, // Skip to: 5627 + /* 4035 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 49, + 6, + 0, // Skip to: 5627 + /* 4042 */ MCD_OPC_Decode, + 241, + 25, + 243, + 3, // Opcode: VRINTRD + /* 4047 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 4069 + /* 4052 */ MCD_OPC_CheckPredicate, + 86, + 34, + 6, + 0, // Skip to: 5627 + /* 4057 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 27, + 6, + 0, // Skip to: 5627 + /* 4064 */ MCD_OPC_Decode, + 244, + 25, + 243, + 3, // Opcode: VRINTXD + /* 4069 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 4091 + /* 4074 */ MCD_OPC_CheckPredicate, + 82, + 12, + 6, + 0, // Skip to: 5627 + /* 4079 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 5, + 6, + 0, // Skip to: 5627 + /* 4086 */ MCD_OPC_Decode, + 175, + 30, + 232, + 3, // Opcode: VUITOD + /* 4091 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 4113 + /* 4096 */ MCD_OPC_CheckPredicate, + 82, + 246, + 5, + 0, // Skip to: 5627 + /* 4101 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 239, + 5, + 0, // Skip to: 5627 + /* 4108 */ MCD_OPC_Decode, + 139, + 27, + 246, + 3, // Opcode: VSHTOD + /* 4113 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 4135 + /* 4118 */ MCD_OPC_CheckPredicate, + 82, + 224, + 5, + 0, // Skip to: 5627 + /* 4123 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 217, + 5, + 0, // Skip to: 5627 + /* 4130 */ MCD_OPC_Decode, + 172, + 30, + 246, + 3, // Opcode: VUHTOD + /* 4135 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4157 + /* 4140 */ MCD_OPC_CheckPredicate, + 82, + 202, + 5, + 0, // Skip to: 5627 + /* 4145 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 195, + 5, + 0, // Skip to: 5627 + /* 4152 */ MCD_OPC_Decode, + 147, + 30, + 244, + 3, // Opcode: VTOUIRD + /* 4157 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 4179 + /* 4162 */ MCD_OPC_CheckPredicate, + 82, + 180, + 5, + 0, // Skip to: 5627 + /* 4167 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 173, + 5, + 0, // Skip to: 5627 + /* 4174 */ MCD_OPC_Decode, + 135, + 30, + 244, + 3, // Opcode: VTOSIRD + /* 4179 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 4201 + /* 4184 */ MCD_OPC_CheckPredicate, + 82, + 158, + 5, + 0, // Skip to: 5627 + /* 4189 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 151, + 5, + 0, // Skip to: 5627 + /* 4196 */ MCD_OPC_Decode, + 132, + 30, + 246, + 3, // Opcode: VTOSHD + /* 4201 */ MCD_OPC_FilterValue, + 15, + 141, + 5, + 0, // Skip to: 5627 + /* 4206 */ MCD_OPC_CheckPredicate, + 82, + 136, + 5, + 0, // Skip to: 5627 + /* 4211 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 129, + 5, + 0, // Skip to: 5627 + /* 4218 */ MCD_OPC_Decode, + 144, + 30, + 246, + 3, // Opcode: VTOUHD + /* 4223 */ MCD_OPC_FilterValue, + 3, + 119, + 5, + 0, // Skip to: 5627 + /* 4228 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 4231 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4253 + /* 4236 */ MCD_OPC_CheckPredicate, + 82, + 106, + 5, + 0, // Skip to: 5627 + /* 4241 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 99, + 5, + 0, // Skip to: 5627 + /* 4248 */ MCD_OPC_Decode, + 241, + 15, + 243, + 3, // Opcode: VABSD + /* 4253 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 4275 + /* 4258 */ MCD_OPC_CheckPredicate, + 82, + 84, + 5, + 0, // Skip to: 5627 + /* 4263 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 77, + 5, + 0, // Skip to: 5627 + /* 4270 */ MCD_OPC_Decode, + 157, + 27, + 243, + 3, // Opcode: VSQRTD + /* 4275 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 4297 + /* 4280 */ MCD_OPC_CheckPredicate, + 86, + 62, + 5, + 0, // Skip to: 5627 + /* 4285 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 55, + 5, + 0, // Skip to: 5627 + /* 4292 */ MCD_OPC_Decode, + 249, + 17, + 232, + 3, // Opcode: VCVTTHD + /* 4297 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 4319 + /* 4302 */ MCD_OPC_CheckPredicate, + 86, + 40, + 5, + 0, // Skip to: 5627 + /* 4307 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 33, + 5, + 0, // Skip to: 5627 + /* 4314 */ MCD_OPC_Decode, + 248, + 17, + 244, + 3, // Opcode: VCVTTDH + /* 4319 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 4341 + /* 4324 */ MCD_OPC_CheckPredicate, + 82, + 18, + 5, + 0, // Skip to: 5627 + /* 4329 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 11, + 5, + 0, // Skip to: 5627 + /* 4336 */ MCD_OPC_Decode, + 173, + 17, + 243, + 3, // Opcode: VCMPED + /* 4341 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 4363 + /* 4346 */ MCD_OPC_CheckPredicate, + 82, + 252, + 4, + 0, // Skip to: 5627 + /* 4351 */ MCD_OPC_CheckField, + 0, + 6, + 0, + 245, + 4, + 0, // Skip to: 5627 + /* 4358 */ MCD_OPC_Decode, + 176, + 17, + 245, + 3, // Opcode: VCMPEZD + /* 4363 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 4385 + /* 4368 */ MCD_OPC_CheckPredicate, + 86, + 230, + 4, + 0, // Skip to: 5627 + /* 4373 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 223, + 4, + 0, // Skip to: 5627 + /* 4380 */ MCD_OPC_Decode, + 251, + 25, + 243, + 3, // Opcode: VRINTZD + /* 4385 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 4407 + /* 4390 */ MCD_OPC_CheckPredicate, + 82, + 208, + 4, + 0, // Skip to: 5627 + /* 4395 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 201, + 4, + 0, // Skip to: 5627 + /* 4402 */ MCD_OPC_Decode, + 247, + 17, + 244, + 3, // Opcode: VCVTSD + /* 4407 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 4429 + /* 4412 */ MCD_OPC_CheckPredicate, + 82, + 186, + 4, + 0, // Skip to: 5627 + /* 4417 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 179, + 4, + 0, // Skip to: 5627 + /* 4424 */ MCD_OPC_Decode, + 142, + 27, + 232, + 3, // Opcode: VSITOD + /* 4429 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 4451 + /* 4434 */ MCD_OPC_CheckPredicate, + 87, + 164, + 4, + 0, // Skip to: 5627 + /* 4439 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 4, + 0, // Skip to: 5627 + /* 4446 */ MCD_OPC_Decode, + 246, + 18, + 244, + 3, // Opcode: VJCVT + /* 4451 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 4473 + /* 4456 */ MCD_OPC_CheckPredicate, + 82, + 142, + 4, + 0, // Skip to: 5627 + /* 4461 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 135, + 4, + 0, // Skip to: 5627 + /* 4468 */ MCD_OPC_Decode, + 153, + 27, + 246, + 3, // Opcode: VSLTOD + /* 4473 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 4495 + /* 4478 */ MCD_OPC_CheckPredicate, + 82, + 120, + 4, + 0, // Skip to: 5627 + /* 4483 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 113, + 4, + 0, // Skip to: 5627 + /* 4490 */ MCD_OPC_Decode, + 178, + 30, + 246, + 3, // Opcode: VULTOD + /* 4495 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4517 + /* 4500 */ MCD_OPC_CheckPredicate, + 82, + 98, + 4, + 0, // Skip to: 5627 + /* 4505 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 91, + 4, + 0, // Skip to: 5627 + /* 4512 */ MCD_OPC_Decode, + 150, + 30, + 244, + 3, // Opcode: VTOUIZD + /* 4517 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 4539 + /* 4522 */ MCD_OPC_CheckPredicate, + 82, + 76, + 4, + 0, // Skip to: 5627 + /* 4527 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 69, + 4, + 0, // Skip to: 5627 + /* 4534 */ MCD_OPC_Decode, + 138, + 30, + 244, + 3, // Opcode: VTOSIZD + /* 4539 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 4561 + /* 4544 */ MCD_OPC_CheckPredicate, + 82, + 54, + 4, + 0, // Skip to: 5627 + /* 4549 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 47, + 4, + 0, // Skip to: 5627 + /* 4556 */ MCD_OPC_Decode, + 141, + 30, + 246, + 3, // Opcode: VTOSLD + /* 4561 */ MCD_OPC_FilterValue, + 15, + 37, + 4, + 0, // Skip to: 5627 + /* 4566 */ MCD_OPC_CheckPredicate, + 82, + 32, + 4, + 0, // Skip to: 5627 + /* 4571 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 25, + 4, + 0, // Skip to: 5627 + /* 4578 */ MCD_OPC_Decode, + 153, + 30, + 246, + 3, // Opcode: VTOULD + /* 4583 */ MCD_OPC_FilterValue, + 15, + 15, + 4, + 0, // Skip to: 5627 + /* 4588 */ MCD_OPC_ExtractField, + 20, + 3, // Inst{22-20} ... + /* 4591 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 4657 + /* 4596 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4599 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 4628 + /* 4604 */ MCD_OPC_CheckPredicate, + 25, + 250, + 3, + 0, // Skip to: 5627 + /* 4609 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 243, + 3, + 0, // Skip to: 5627 + /* 4616 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 236, + 3, + 0, // Skip to: 5627 + /* 4623 */ MCD_OPC_Decode, + 205, + 29, + 247, + 3, // Opcode: VSTR_FPSCR_off + /* 4628 */ MCD_OPC_FilterValue, + 4, + 226, + 3, + 0, // Skip to: 5627 + /* 4633 */ MCD_OPC_CheckPredicate, + 25, + 221, + 3, + 0, // Skip to: 5627 + /* 4638 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 214, + 3, + 0, // Skip to: 5627 + /* 4645 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 207, + 3, + 0, // Skip to: 5627 + /* 4652 */ MCD_OPC_Decode, + 202, + 29, + 247, + 3, // Opcode: VSTR_FPSCR_NZCVQC_off + /* 4657 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 4723 + /* 4662 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4665 */ MCD_OPC_FilterValue, + 2, + 24, + 0, + 0, // Skip to: 4694 + /* 4670 */ MCD_OPC_CheckPredicate, + 25, + 184, + 3, + 0, // Skip to: 5627 + /* 4675 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 177, + 3, + 0, // Skip to: 5627 + /* 4682 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 170, + 3, + 0, // Skip to: 5627 + /* 4689 */ MCD_OPC_Decode, + 242, + 21, + 247, + 3, // Opcode: VLDR_FPSCR_off + /* 4694 */ MCD_OPC_FilterValue, + 4, + 160, + 3, + 0, // Skip to: 5627 + /* 4699 */ MCD_OPC_CheckPredicate, + 25, + 155, + 3, + 0, // Skip to: 5627 + /* 4704 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 148, + 3, + 0, // Skip to: 5627 + /* 4711 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 141, + 3, + 0, // Skip to: 5627 + /* 4718 */ MCD_OPC_Decode, + 239, + 21, + 247, + 3, // Opcode: VLDR_FPSCR_NZCVQC_off + /* 4723 */ MCD_OPC_FilterValue, + 2, + 107, + 0, + 0, // Skip to: 4835 + /* 4728 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4731 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 4783 + /* 4736 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 4739 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4761 + /* 4744 */ MCD_OPC_CheckPredicate, + 25, + 110, + 3, + 0, // Skip to: 5627 + /* 4749 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 103, + 3, + 0, // Skip to: 5627 + /* 4756 */ MCD_OPC_Decode, + 206, + 29, + 248, + 3, // Opcode: VSTR_FPSCR_post + /* 4761 */ MCD_OPC_FilterValue, + 13, + 93, + 3, + 0, // Skip to: 5627 + /* 4766 */ MCD_OPC_CheckPredicate, + 25, + 88, + 3, + 0, // Skip to: 5627 + /* 4771 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 81, + 3, + 0, // Skip to: 5627 + /* 4778 */ MCD_OPC_Decode, + 207, + 29, + 248, + 3, // Opcode: VSTR_FPSCR_pre + /* 4783 */ MCD_OPC_FilterValue, + 4, + 71, + 3, + 0, // Skip to: 5627 + /* 4788 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 4791 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4813 + /* 4796 */ MCD_OPC_CheckPredicate, + 25, + 58, + 3, + 0, // Skip to: 5627 + /* 4801 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 51, + 3, + 0, // Skip to: 5627 + /* 4808 */ MCD_OPC_Decode, + 203, + 29, + 248, + 3, // Opcode: VSTR_FPSCR_NZCVQC_post + /* 4813 */ MCD_OPC_FilterValue, + 13, + 41, + 3, + 0, // Skip to: 5627 + /* 4818 */ MCD_OPC_CheckPredicate, + 25, + 36, + 3, + 0, // Skip to: 5627 + /* 4823 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 29, + 3, + 0, // Skip to: 5627 + /* 4830 */ MCD_OPC_Decode, + 204, + 29, + 248, + 3, // Opcode: VSTR_FPSCR_NZCVQC_pre + /* 4835 */ MCD_OPC_FilterValue, + 3, + 107, + 0, + 0, // Skip to: 4947 + /* 4840 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4843 */ MCD_OPC_FilterValue, + 2, + 47, + 0, + 0, // Skip to: 4895 + /* 4848 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 4851 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4873 + /* 4856 */ MCD_OPC_CheckPredicate, + 25, + 254, + 2, + 0, // Skip to: 5627 + /* 4861 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 247, + 2, + 0, // Skip to: 5627 + /* 4868 */ MCD_OPC_Decode, + 243, + 21, + 248, + 3, // Opcode: VLDR_FPSCR_post + /* 4873 */ MCD_OPC_FilterValue, + 13, + 237, + 2, + 0, // Skip to: 5627 + /* 4878 */ MCD_OPC_CheckPredicate, + 25, + 232, + 2, + 0, // Skip to: 5627 + /* 4883 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 225, + 2, + 0, // Skip to: 5627 + /* 4890 */ MCD_OPC_Decode, + 244, + 21, + 248, + 3, // Opcode: VLDR_FPSCR_pre + /* 4895 */ MCD_OPC_FilterValue, + 4, + 215, + 2, + 0, // Skip to: 5627 + /* 4900 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 4903 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 4925 + /* 4908 */ MCD_OPC_CheckPredicate, + 25, + 202, + 2, + 0, // Skip to: 5627 + /* 4913 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 195, + 2, + 0, // Skip to: 5627 + /* 4920 */ MCD_OPC_Decode, + 240, + 21, + 248, + 3, // Opcode: VLDR_FPSCR_NZCVQC_post + /* 4925 */ MCD_OPC_FilterValue, + 13, + 185, + 2, + 0, // Skip to: 5627 + /* 4930 */ MCD_OPC_CheckPredicate, + 25, + 180, + 2, + 0, // Skip to: 5627 + /* 4935 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 173, + 2, + 0, // Skip to: 5627 + /* 4942 */ MCD_OPC_Decode, + 241, + 21, + 248, + 3, // Opcode: VLDR_FPSCR_NZCVQC_pre + /* 4947 */ MCD_OPC_FilterValue, + 4, + 119, + 0, + 0, // Skip to: 5071 + /* 4952 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4955 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 4984 + /* 4960 */ MCD_OPC_CheckPredicate, + 23, + 150, + 2, + 0, // Skip to: 5627 + /* 4965 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 143, + 2, + 0, // Skip to: 5627 + /* 4972 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 136, + 2, + 0, // Skip to: 5627 + /* 4979 */ MCD_OPC_Decode, + 211, + 29, + 247, + 3, // Opcode: VSTR_VPR_off + /* 4984 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 5013 + /* 4989 */ MCD_OPC_CheckPredicate, + 23, + 121, + 2, + 0, // Skip to: 5627 + /* 4994 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 114, + 2, + 0, // Skip to: 5627 + /* 5001 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 107, + 2, + 0, // Skip to: 5627 + /* 5008 */ MCD_OPC_Decode, + 208, + 29, + 247, + 3, // Opcode: VSTR_P0_off + /* 5013 */ MCD_OPC_FilterValue, + 12, + 24, + 0, + 0, // Skip to: 5042 + /* 5018 */ MCD_OPC_CheckPredicate, + 75, + 92, + 2, + 0, // Skip to: 5627 + /* 5023 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 85, + 2, + 0, // Skip to: 5627 + /* 5030 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 78, + 2, + 0, // Skip to: 5627 + /* 5037 */ MCD_OPC_Decode, + 196, + 29, + 247, + 3, // Opcode: VSTR_FPCXTNS_off + /* 5042 */ MCD_OPC_FilterValue, + 14, + 68, + 2, + 0, // Skip to: 5627 + /* 5047 */ MCD_OPC_CheckPredicate, + 75, + 63, + 2, + 0, // Skip to: 5627 + /* 5052 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 56, + 2, + 0, // Skip to: 5627 + /* 5059 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 49, + 2, + 0, // Skip to: 5627 + /* 5066 */ MCD_OPC_Decode, + 199, + 29, + 247, + 3, // Opcode: VSTR_FPCXTS_off + /* 5071 */ MCD_OPC_FilterValue, + 5, + 119, + 0, + 0, // Skip to: 5195 + /* 5076 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5079 */ MCD_OPC_FilterValue, + 8, + 24, + 0, + 0, // Skip to: 5108 + /* 5084 */ MCD_OPC_CheckPredicate, + 23, + 26, + 2, + 0, // Skip to: 5627 + /* 5089 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 19, + 2, + 0, // Skip to: 5627 + /* 5096 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 12, + 2, + 0, // Skip to: 5627 + /* 5103 */ MCD_OPC_Decode, + 248, + 21, + 247, + 3, // Opcode: VLDR_VPR_off + /* 5108 */ MCD_OPC_FilterValue, + 10, + 24, + 0, + 0, // Skip to: 5137 + /* 5113 */ MCD_OPC_CheckPredicate, + 23, + 253, + 1, + 0, // Skip to: 5627 + /* 5118 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 246, + 1, + 0, // Skip to: 5627 + /* 5125 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 239, + 1, + 0, // Skip to: 5627 + /* 5132 */ MCD_OPC_Decode, + 245, + 21, + 247, + 3, // Opcode: VLDR_P0_off + /* 5137 */ MCD_OPC_FilterValue, + 12, + 24, + 0, + 0, // Skip to: 5166 + /* 5142 */ MCD_OPC_CheckPredicate, + 75, + 224, + 1, + 0, // Skip to: 5627 + /* 5147 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 217, + 1, + 0, // Skip to: 5627 + /* 5154 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 210, + 1, + 0, // Skip to: 5627 + /* 5161 */ MCD_OPC_Decode, + 233, + 21, + 247, + 3, // Opcode: VLDR_FPCXTNS_off + /* 5166 */ MCD_OPC_FilterValue, + 14, + 200, + 1, + 0, // Skip to: 5627 + /* 5171 */ MCD_OPC_CheckPredicate, + 75, + 195, + 1, + 0, // Skip to: 5627 + /* 5176 */ MCD_OPC_CheckField, + 24, + 4, + 13, + 188, + 1, + 0, // Skip to: 5627 + /* 5183 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 181, + 1, + 0, // Skip to: 5627 + /* 5190 */ MCD_OPC_Decode, + 236, + 21, + 247, + 3, // Opcode: VLDR_FPCXTS_off + /* 5195 */ MCD_OPC_FilterValue, + 6, + 211, + 0, + 0, // Skip to: 5411 + /* 5200 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5203 */ MCD_OPC_FilterValue, + 8, + 47, + 0, + 0, // Skip to: 5255 + /* 5208 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5211 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5233 + /* 5216 */ MCD_OPC_CheckPredicate, + 23, + 150, + 1, + 0, // Skip to: 5627 + /* 5221 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 143, + 1, + 0, // Skip to: 5627 + /* 5228 */ MCD_OPC_Decode, + 212, + 29, + 248, + 3, // Opcode: VSTR_VPR_post + /* 5233 */ MCD_OPC_FilterValue, + 13, + 133, + 1, + 0, // Skip to: 5627 + /* 5238 */ MCD_OPC_CheckPredicate, + 23, + 128, + 1, + 0, // Skip to: 5627 + /* 5243 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 121, + 1, + 0, // Skip to: 5627 + /* 5250 */ MCD_OPC_Decode, + 213, + 29, + 248, + 3, // Opcode: VSTR_VPR_pre + /* 5255 */ MCD_OPC_FilterValue, + 10, + 47, + 0, + 0, // Skip to: 5307 + /* 5260 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5263 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5285 + /* 5268 */ MCD_OPC_CheckPredicate, + 23, + 98, + 1, + 0, // Skip to: 5627 + /* 5273 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 91, + 1, + 0, // Skip to: 5627 + /* 5280 */ MCD_OPC_Decode, + 209, + 29, + 248, + 3, // Opcode: VSTR_P0_post + /* 5285 */ MCD_OPC_FilterValue, + 13, + 81, + 1, + 0, // Skip to: 5627 + /* 5290 */ MCD_OPC_CheckPredicate, + 23, + 76, + 1, + 0, // Skip to: 5627 + /* 5295 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 69, + 1, + 0, // Skip to: 5627 + /* 5302 */ MCD_OPC_Decode, + 210, + 29, + 248, + 3, // Opcode: VSTR_P0_pre + /* 5307 */ MCD_OPC_FilterValue, + 12, + 47, + 0, + 0, // Skip to: 5359 + /* 5312 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5315 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5337 + /* 5320 */ MCD_OPC_CheckPredicate, + 75, + 46, + 1, + 0, // Skip to: 5627 + /* 5325 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 39, + 1, + 0, // Skip to: 5627 + /* 5332 */ MCD_OPC_Decode, + 197, + 29, + 248, + 3, // Opcode: VSTR_FPCXTNS_post + /* 5337 */ MCD_OPC_FilterValue, + 13, + 29, + 1, + 0, // Skip to: 5627 + /* 5342 */ MCD_OPC_CheckPredicate, + 75, + 24, + 1, + 0, // Skip to: 5627 + /* 5347 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 17, + 1, + 0, // Skip to: 5627 + /* 5354 */ MCD_OPC_Decode, + 198, + 29, + 248, + 3, // Opcode: VSTR_FPCXTNS_pre + /* 5359 */ MCD_OPC_FilterValue, + 14, + 7, + 1, + 0, // Skip to: 5627 + /* 5364 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5367 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5389 + /* 5372 */ MCD_OPC_CheckPredicate, + 75, + 250, + 0, + 0, // Skip to: 5627 + /* 5377 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 243, + 0, + 0, // Skip to: 5627 + /* 5384 */ MCD_OPC_Decode, + 200, + 29, + 248, + 3, // Opcode: VSTR_FPCXTS_post + /* 5389 */ MCD_OPC_FilterValue, + 13, + 233, + 0, + 0, // Skip to: 5627 + /* 5394 */ MCD_OPC_CheckPredicate, + 75, + 228, + 0, + 0, // Skip to: 5627 + /* 5399 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 221, + 0, + 0, // Skip to: 5627 + /* 5406 */ MCD_OPC_Decode, + 201, + 29, + 248, + 3, // Opcode: VSTR_FPCXTS_pre + /* 5411 */ MCD_OPC_FilterValue, + 7, + 211, + 0, + 0, // Skip to: 5627 + /* 5416 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5419 */ MCD_OPC_FilterValue, + 8, + 47, + 0, + 0, // Skip to: 5471 + /* 5424 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5427 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5449 + /* 5432 */ MCD_OPC_CheckPredicate, + 23, + 190, + 0, + 0, // Skip to: 5627 + /* 5437 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 183, + 0, + 0, // Skip to: 5627 + /* 5444 */ MCD_OPC_Decode, + 249, + 21, + 248, + 3, // Opcode: VLDR_VPR_post + /* 5449 */ MCD_OPC_FilterValue, + 13, + 173, + 0, + 0, // Skip to: 5627 + /* 5454 */ MCD_OPC_CheckPredicate, + 23, + 168, + 0, + 0, // Skip to: 5627 + /* 5459 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 161, + 0, + 0, // Skip to: 5627 + /* 5466 */ MCD_OPC_Decode, + 250, + 21, + 248, + 3, // Opcode: VLDR_VPR_pre + /* 5471 */ MCD_OPC_FilterValue, + 10, + 47, + 0, + 0, // Skip to: 5523 + /* 5476 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5479 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5501 + /* 5484 */ MCD_OPC_CheckPredicate, + 23, + 138, + 0, + 0, // Skip to: 5627 + /* 5489 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 131, + 0, + 0, // Skip to: 5627 + /* 5496 */ MCD_OPC_Decode, + 246, + 21, + 248, + 3, // Opcode: VLDR_P0_post + /* 5501 */ MCD_OPC_FilterValue, + 13, + 121, + 0, + 0, // Skip to: 5627 + /* 5506 */ MCD_OPC_CheckPredicate, + 23, + 116, + 0, + 0, // Skip to: 5627 + /* 5511 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 109, + 0, + 0, // Skip to: 5627 + /* 5518 */ MCD_OPC_Decode, + 247, + 21, + 248, + 3, // Opcode: VLDR_P0_pre + /* 5523 */ MCD_OPC_FilterValue, + 12, + 47, + 0, + 0, // Skip to: 5575 + /* 5528 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5531 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5553 + /* 5536 */ MCD_OPC_CheckPredicate, + 75, + 86, + 0, + 0, // Skip to: 5627 + /* 5541 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 79, + 0, + 0, // Skip to: 5627 + /* 5548 */ MCD_OPC_Decode, + 234, + 21, + 248, + 3, // Opcode: VLDR_FPCXTNS_post + /* 5553 */ MCD_OPC_FilterValue, + 13, + 69, + 0, + 0, // Skip to: 5627 + /* 5558 */ MCD_OPC_CheckPredicate, + 75, + 64, + 0, + 0, // Skip to: 5627 + /* 5563 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 57, + 0, + 0, // Skip to: 5627 + /* 5570 */ MCD_OPC_Decode, + 235, + 21, + 248, + 3, // Opcode: VLDR_FPCXTNS_pre + /* 5575 */ MCD_OPC_FilterValue, + 14, + 47, + 0, + 0, // Skip to: 5627 + /* 5580 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 5583 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 5605 + /* 5588 */ MCD_OPC_CheckPredicate, + 75, + 34, + 0, + 0, // Skip to: 5627 + /* 5593 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 27, + 0, + 0, // Skip to: 5627 + /* 5600 */ MCD_OPC_Decode, + 237, + 21, + 248, + 3, // Opcode: VLDR_FPCXTS_post + /* 5605 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 5627 + /* 5610 */ MCD_OPC_CheckPredicate, + 75, + 12, + 0, + 0, // Skip to: 5627 + /* 5615 */ MCD_OPC_CheckField, + 7, + 1, + 1, + 5, + 0, + 0, // Skip to: 5627 + /* 5622 */ MCD_OPC_Decode, + 238, + 21, + 248, + 3, // Opcode: VLDR_FPCXTS_pre + /* 5627 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableVFPV832[] = { -/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 3 */ MCD_OPC_FilterValue, 8, 87, 1, 0, // Skip to: 351 -/* 8 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 11 */ MCD_OPC_FilterValue, 0, 165, 0, 0, // Skip to: 181 -/* 16 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 19 */ MCD_OPC_FilterValue, 126, 105, 0, 0, // Skip to: 129 -/* 24 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 27 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 56 -/* 32 */ MCD_OPC_CheckPredicate, 71, 220, 9, 0, // Skip to: 2561 -/* 37 */ MCD_OPC_CheckField, 23, 1, 1, 213, 9, 0, // Skip to: 2561 -/* 44 */ MCD_OPC_CheckField, 4, 1, 0, 206, 9, 0, // Skip to: 2561 -/* 51 */ MCD_OPC_Decode, 152, 8, 230, 2, // Opcode: VCADDv4f16 -/* 56 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 85 -/* 61 */ MCD_OPC_CheckPredicate, 72, 191, 9, 0, // Skip to: 2561 -/* 66 */ MCD_OPC_CheckField, 23, 1, 1, 184, 9, 0, // Skip to: 2561 -/* 73 */ MCD_OPC_CheckField, 4, 1, 0, 177, 9, 0, // Skip to: 2561 -/* 80 */ MCD_OPC_Decode, 151, 8, 230, 2, // Opcode: VCADDv2f32 -/* 85 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 107 -/* 90 */ MCD_OPC_CheckPredicate, 71, 162, 9, 0, // Skip to: 2561 -/* 95 */ MCD_OPC_CheckField, 4, 1, 0, 155, 9, 0, // Skip to: 2561 -/* 102 */ MCD_OPC_Decode, 133, 9, 231, 2, // Opcode: VCMLAv4f16 -/* 107 */ MCD_OPC_FilterValue, 3, 145, 9, 0, // Skip to: 2561 -/* 112 */ MCD_OPC_CheckPredicate, 72, 140, 9, 0, // Skip to: 2561 -/* 117 */ MCD_OPC_CheckField, 4, 1, 0, 133, 9, 0, // Skip to: 2561 -/* 124 */ MCD_OPC_Decode, 131, 9, 231, 2, // Opcode: VCMLAv2f32 -/* 129 */ MCD_OPC_FilterValue, 127, 123, 9, 0, // Skip to: 2561 -/* 134 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 137 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 159 -/* 142 */ MCD_OPC_CheckPredicate, 71, 110, 9, 0, // Skip to: 2561 -/* 147 */ MCD_OPC_CheckField, 4, 1, 0, 103, 9, 0, // Skip to: 2561 -/* 154 */ MCD_OPC_Decode, 134, 9, 232, 2, // Opcode: VCMLAv4f16_indexed -/* 159 */ MCD_OPC_FilterValue, 1, 93, 9, 0, // Skip to: 2561 -/* 164 */ MCD_OPC_CheckPredicate, 72, 88, 9, 0, // Skip to: 2561 -/* 169 */ MCD_OPC_CheckField, 4, 1, 0, 81, 9, 0, // Skip to: 2561 -/* 176 */ MCD_OPC_Decode, 132, 9, 233, 2, // Opcode: VCMLAv2f32_indexed -/* 181 */ MCD_OPC_FilterValue, 1, 71, 9, 0, // Skip to: 2561 -/* 186 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 189 */ MCD_OPC_FilterValue, 126, 105, 0, 0, // Skip to: 299 -/* 194 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 197 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 226 -/* 202 */ MCD_OPC_CheckPredicate, 71, 50, 9, 0, // Skip to: 2561 -/* 207 */ MCD_OPC_CheckField, 23, 1, 1, 43, 9, 0, // Skip to: 2561 -/* 214 */ MCD_OPC_CheckField, 4, 1, 0, 36, 9, 0, // Skip to: 2561 -/* 221 */ MCD_OPC_Decode, 154, 8, 234, 2, // Opcode: VCADDv8f16 -/* 226 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 255 -/* 231 */ MCD_OPC_CheckPredicate, 72, 21, 9, 0, // Skip to: 2561 -/* 236 */ MCD_OPC_CheckField, 23, 1, 1, 14, 9, 0, // Skip to: 2561 -/* 243 */ MCD_OPC_CheckField, 4, 1, 0, 7, 9, 0, // Skip to: 2561 -/* 250 */ MCD_OPC_Decode, 153, 8, 234, 2, // Opcode: VCADDv4f32 -/* 255 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 277 -/* 260 */ MCD_OPC_CheckPredicate, 71, 248, 8, 0, // Skip to: 2561 -/* 265 */ MCD_OPC_CheckField, 4, 1, 0, 241, 8, 0, // Skip to: 2561 -/* 272 */ MCD_OPC_Decode, 137, 9, 235, 2, // Opcode: VCMLAv8f16 -/* 277 */ MCD_OPC_FilterValue, 3, 231, 8, 0, // Skip to: 2561 -/* 282 */ MCD_OPC_CheckPredicate, 72, 226, 8, 0, // Skip to: 2561 -/* 287 */ MCD_OPC_CheckField, 4, 1, 0, 219, 8, 0, // Skip to: 2561 -/* 294 */ MCD_OPC_Decode, 135, 9, 235, 2, // Opcode: VCMLAv4f32 -/* 299 */ MCD_OPC_FilterValue, 127, 209, 8, 0, // Skip to: 2561 -/* 304 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... -/* 307 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 329 -/* 312 */ MCD_OPC_CheckPredicate, 71, 196, 8, 0, // Skip to: 2561 -/* 317 */ MCD_OPC_CheckField, 4, 1, 0, 189, 8, 0, // Skip to: 2561 -/* 324 */ MCD_OPC_Decode, 138, 9, 236, 2, // Opcode: VCMLAv8f16_indexed -/* 329 */ MCD_OPC_FilterValue, 1, 179, 8, 0, // Skip to: 2561 -/* 334 */ MCD_OPC_CheckPredicate, 72, 174, 8, 0, // Skip to: 2561 -/* 339 */ MCD_OPC_CheckField, 4, 1, 0, 167, 8, 0, // Skip to: 2561 -/* 346 */ MCD_OPC_Decode, 136, 9, 233, 2, // Opcode: VCMLAv4f32_indexed -/* 351 */ MCD_OPC_FilterValue, 9, 123, 2, 0, // Skip to: 991 -/* 356 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 359 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 451 -/* 364 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 367 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 421 -/* 372 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 375 */ MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 398 -/* 381 */ MCD_OPC_CheckPredicate, 60, 127, 8, 0, // Skip to: 2561 -/* 386 */ MCD_OPC_CheckField, 4, 1, 0, 120, 8, 0, // Skip to: 2561 -/* 393 */ MCD_OPC_Decode, 233, 17, 237, 2, // Opcode: VSELEQH -/* 398 */ MCD_OPC_FilterValue, 253, 3, 109, 8, 0, // Skip to: 2561 -/* 404 */ MCD_OPC_CheckPredicate, 60, 104, 8, 0, // Skip to: 2561 -/* 409 */ MCD_OPC_CheckField, 4, 1, 0, 97, 8, 0, // Skip to: 2561 -/* 416 */ MCD_OPC_Decode, 157, 13, 237, 2, // Opcode: VMAXNMH -/* 421 */ MCD_OPC_FilterValue, 1, 87, 8, 0, // Skip to: 2561 -/* 426 */ MCD_OPC_CheckPredicate, 60, 82, 8, 0, // Skip to: 2561 -/* 431 */ MCD_OPC_CheckField, 23, 9, 253, 3, 74, 8, 0, // Skip to: 2561 -/* 439 */ MCD_OPC_CheckField, 4, 1, 0, 67, 8, 0, // Skip to: 2561 -/* 446 */ MCD_OPC_Decode, 180, 13, 237, 2, // Opcode: VMINNMH -/* 451 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 488 -/* 456 */ MCD_OPC_CheckPredicate, 60, 52, 8, 0, // Skip to: 2561 -/* 461 */ MCD_OPC_CheckField, 23, 9, 252, 3, 44, 8, 0, // Skip to: 2561 -/* 469 */ MCD_OPC_CheckField, 6, 1, 0, 37, 8, 0, // Skip to: 2561 -/* 476 */ MCD_OPC_CheckField, 4, 1, 0, 30, 8, 0, // Skip to: 2561 -/* 483 */ MCD_OPC_Decode, 242, 17, 237, 2, // Opcode: VSELVSH -/* 488 */ MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 525 -/* 493 */ MCD_OPC_CheckPredicate, 60, 15, 8, 0, // Skip to: 2561 -/* 498 */ MCD_OPC_CheckField, 23, 9, 252, 3, 7, 8, 0, // Skip to: 2561 -/* 506 */ MCD_OPC_CheckField, 6, 1, 0, 0, 8, 0, // Skip to: 2561 -/* 513 */ MCD_OPC_CheckField, 4, 1, 0, 249, 7, 0, // Skip to: 2561 -/* 520 */ MCD_OPC_Decode, 236, 17, 237, 2, // Opcode: VSELGEH -/* 525 */ MCD_OPC_FilterValue, 3, 239, 7, 0, // Skip to: 2561 -/* 530 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 533 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 563 -/* 538 */ MCD_OPC_CheckPredicate, 60, 226, 7, 0, // Skip to: 2561 -/* 543 */ MCD_OPC_CheckField, 23, 9, 252, 3, 218, 7, 0, // Skip to: 2561 -/* 551 */ MCD_OPC_CheckField, 4, 1, 0, 211, 7, 0, // Skip to: 2561 -/* 558 */ MCD_OPC_Decode, 239, 17, 237, 2, // Opcode: VSELGTH -/* 563 */ MCD_OPC_FilterValue, 1, 201, 7, 0, // Skip to: 2561 -/* 568 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 571 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 608 -/* 576 */ MCD_OPC_CheckPredicate, 60, 188, 7, 0, // Skip to: 2561 -/* 581 */ MCD_OPC_CheckField, 23, 9, 253, 3, 180, 7, 0, // Skip to: 2561 -/* 589 */ MCD_OPC_CheckField, 7, 1, 0, 173, 7, 0, // Skip to: 2561 -/* 596 */ MCD_OPC_CheckField, 4, 1, 0, 166, 7, 0, // Skip to: 2561 -/* 603 */ MCD_OPC_Decode, 248, 16, 238, 2, // Opcode: VRINTAH -/* 608 */ MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 645 -/* 613 */ MCD_OPC_CheckPredicate, 60, 151, 7, 0, // Skip to: 2561 -/* 618 */ MCD_OPC_CheckField, 23, 9, 253, 3, 143, 7, 0, // Skip to: 2561 -/* 626 */ MCD_OPC_CheckField, 7, 1, 0, 136, 7, 0, // Skip to: 2561 -/* 633 */ MCD_OPC_CheckField, 4, 1, 0, 129, 7, 0, // Skip to: 2561 -/* 640 */ MCD_OPC_Decode, 134, 17, 238, 2, // Opcode: VRINTNH -/* 645 */ MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 682 -/* 650 */ MCD_OPC_CheckPredicate, 60, 114, 7, 0, // Skip to: 2561 -/* 655 */ MCD_OPC_CheckField, 23, 9, 253, 3, 106, 7, 0, // Skip to: 2561 -/* 663 */ MCD_OPC_CheckField, 7, 1, 0, 99, 7, 0, // Skip to: 2561 -/* 670 */ MCD_OPC_CheckField, 4, 1, 0, 92, 7, 0, // Skip to: 2561 -/* 677 */ MCD_OPC_Decode, 141, 17, 238, 2, // Opcode: VRINTPH -/* 682 */ MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 719 -/* 687 */ MCD_OPC_CheckPredicate, 60, 77, 7, 0, // Skip to: 2561 -/* 692 */ MCD_OPC_CheckField, 23, 9, 253, 3, 69, 7, 0, // Skip to: 2561 -/* 700 */ MCD_OPC_CheckField, 7, 1, 0, 62, 7, 0, // Skip to: 2561 -/* 707 */ MCD_OPC_CheckField, 4, 1, 0, 55, 7, 0, // Skip to: 2561 -/* 714 */ MCD_OPC_Decode, 255, 16, 238, 2, // Opcode: VRINTMH -/* 719 */ MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 787 -/* 724 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 727 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 757 -/* 732 */ MCD_OPC_CheckPredicate, 60, 32, 7, 0, // Skip to: 2561 -/* 737 */ MCD_OPC_CheckField, 23, 9, 253, 3, 24, 7, 0, // Skip to: 2561 -/* 745 */ MCD_OPC_CheckField, 4, 1, 0, 17, 7, 0, // Skip to: 2561 -/* 752 */ MCD_OPC_Decode, 165, 9, 239, 2, // Opcode: VCVTAUH -/* 757 */ MCD_OPC_FilterValue, 1, 7, 7, 0, // Skip to: 2561 -/* 762 */ MCD_OPC_CheckPredicate, 60, 2, 7, 0, // Skip to: 2561 -/* 767 */ MCD_OPC_CheckField, 23, 9, 253, 3, 250, 6, 0, // Skip to: 2561 -/* 775 */ MCD_OPC_CheckField, 4, 1, 0, 243, 6, 0, // Skip to: 2561 -/* 782 */ MCD_OPC_Decode, 162, 9, 239, 2, // Opcode: VCVTASH -/* 787 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 855 -/* 792 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 795 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 825 -/* 800 */ MCD_OPC_CheckPredicate, 60, 220, 6, 0, // Skip to: 2561 -/* 805 */ MCD_OPC_CheckField, 23, 9, 253, 3, 212, 6, 0, // Skip to: 2561 -/* 813 */ MCD_OPC_CheckField, 4, 1, 0, 205, 6, 0, // Skip to: 2561 -/* 820 */ MCD_OPC_Decode, 198, 9, 239, 2, // Opcode: VCVTNUH -/* 825 */ MCD_OPC_FilterValue, 1, 195, 6, 0, // Skip to: 2561 -/* 830 */ MCD_OPC_CheckPredicate, 60, 190, 6, 0, // Skip to: 2561 -/* 835 */ MCD_OPC_CheckField, 23, 9, 253, 3, 182, 6, 0, // Skip to: 2561 -/* 843 */ MCD_OPC_CheckField, 4, 1, 0, 175, 6, 0, // Skip to: 2561 -/* 850 */ MCD_OPC_Decode, 195, 9, 239, 2, // Opcode: VCVTNSH -/* 855 */ MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 923 -/* 860 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 863 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 893 -/* 868 */ MCD_OPC_CheckPredicate, 60, 152, 6, 0, // Skip to: 2561 -/* 873 */ MCD_OPC_CheckField, 23, 9, 253, 3, 144, 6, 0, // Skip to: 2561 -/* 881 */ MCD_OPC_CheckField, 4, 1, 0, 137, 6, 0, // Skip to: 2561 -/* 888 */ MCD_OPC_Decode, 212, 9, 239, 2, // Opcode: VCVTPUH -/* 893 */ MCD_OPC_FilterValue, 1, 127, 6, 0, // Skip to: 2561 -/* 898 */ MCD_OPC_CheckPredicate, 60, 122, 6, 0, // Skip to: 2561 -/* 903 */ MCD_OPC_CheckField, 23, 9, 253, 3, 114, 6, 0, // Skip to: 2561 -/* 911 */ MCD_OPC_CheckField, 4, 1, 0, 107, 6, 0, // Skip to: 2561 -/* 918 */ MCD_OPC_Decode, 209, 9, 239, 2, // Opcode: VCVTPSH -/* 923 */ MCD_OPC_FilterValue, 15, 97, 6, 0, // Skip to: 2561 -/* 928 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 931 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 961 -/* 936 */ MCD_OPC_CheckPredicate, 60, 84, 6, 0, // Skip to: 2561 -/* 941 */ MCD_OPC_CheckField, 23, 9, 253, 3, 76, 6, 0, // Skip to: 2561 -/* 949 */ MCD_OPC_CheckField, 4, 1, 0, 69, 6, 0, // Skip to: 2561 -/* 956 */ MCD_OPC_Decode, 184, 9, 239, 2, // Opcode: VCVTMUH -/* 961 */ MCD_OPC_FilterValue, 1, 59, 6, 0, // Skip to: 2561 -/* 966 */ MCD_OPC_CheckPredicate, 60, 54, 6, 0, // Skip to: 2561 -/* 971 */ MCD_OPC_CheckField, 23, 9, 253, 3, 46, 6, 0, // Skip to: 2561 -/* 979 */ MCD_OPC_CheckField, 4, 1, 0, 39, 6, 0, // Skip to: 2561 -/* 986 */ MCD_OPC_Decode, 181, 9, 239, 2, // Opcode: VCVTMSH -/* 991 */ MCD_OPC_FilterValue, 10, 191, 2, 0, // Skip to: 1699 -/* 996 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 999 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 1091 -/* 1004 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1007 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 1061 -/* 1012 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1015 */ MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 1038 -/* 1021 */ MCD_OPC_CheckPredicate, 66, 255, 5, 0, // Skip to: 2561 -/* 1026 */ MCD_OPC_CheckField, 4, 1, 0, 248, 5, 0, // Skip to: 2561 -/* 1033 */ MCD_OPC_Decode, 234, 17, 240, 2, // Opcode: VSELEQS -/* 1038 */ MCD_OPC_FilterValue, 253, 3, 237, 5, 0, // Skip to: 2561 -/* 1044 */ MCD_OPC_CheckPredicate, 66, 232, 5, 0, // Skip to: 2561 -/* 1049 */ MCD_OPC_CheckField, 4, 1, 0, 225, 5, 0, // Skip to: 2561 -/* 1056 */ MCD_OPC_Decode, 162, 13, 240, 2, // Opcode: VMAXNMS -/* 1061 */ MCD_OPC_FilterValue, 1, 215, 5, 0, // Skip to: 2561 -/* 1066 */ MCD_OPC_CheckPredicate, 66, 210, 5, 0, // Skip to: 2561 -/* 1071 */ MCD_OPC_CheckField, 23, 9, 253, 3, 202, 5, 0, // Skip to: 2561 -/* 1079 */ MCD_OPC_CheckField, 4, 1, 0, 195, 5, 0, // Skip to: 2561 -/* 1086 */ MCD_OPC_Decode, 185, 13, 240, 2, // Opcode: VMINNMS -/* 1091 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 1128 -/* 1096 */ MCD_OPC_CheckPredicate, 66, 180, 5, 0, // Skip to: 2561 -/* 1101 */ MCD_OPC_CheckField, 23, 9, 252, 3, 172, 5, 0, // Skip to: 2561 -/* 1109 */ MCD_OPC_CheckField, 6, 1, 0, 165, 5, 0, // Skip to: 2561 -/* 1116 */ MCD_OPC_CheckField, 4, 1, 0, 158, 5, 0, // Skip to: 2561 -/* 1123 */ MCD_OPC_Decode, 243, 17, 240, 2, // Opcode: VSELVSS -/* 1128 */ MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 1165 -/* 1133 */ MCD_OPC_CheckPredicate, 66, 143, 5, 0, // Skip to: 2561 -/* 1138 */ MCD_OPC_CheckField, 23, 9, 252, 3, 135, 5, 0, // Skip to: 2561 -/* 1146 */ MCD_OPC_CheckField, 6, 1, 0, 128, 5, 0, // Skip to: 2561 -/* 1153 */ MCD_OPC_CheckField, 4, 1, 0, 121, 5, 0, // Skip to: 2561 -/* 1160 */ MCD_OPC_Decode, 237, 17, 240, 2, // Opcode: VSELGES -/* 1165 */ MCD_OPC_FilterValue, 3, 111, 5, 0, // Skip to: 2561 -/* 1170 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1173 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1203 -/* 1178 */ MCD_OPC_CheckPredicate, 66, 98, 5, 0, // Skip to: 2561 -/* 1183 */ MCD_OPC_CheckField, 23, 9, 252, 3, 90, 5, 0, // Skip to: 2561 -/* 1191 */ MCD_OPC_CheckField, 4, 1, 0, 83, 5, 0, // Skip to: 2561 -/* 1198 */ MCD_OPC_Decode, 240, 17, 240, 2, // Opcode: VSELGTS -/* 1203 */ MCD_OPC_FilterValue, 1, 73, 5, 0, // Skip to: 2561 -/* 1208 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 1211 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 1279 -/* 1216 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 1219 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1249 -/* 1224 */ MCD_OPC_CheckPredicate, 60, 52, 5, 0, // Skip to: 2561 -/* 1229 */ MCD_OPC_CheckField, 23, 9, 253, 3, 44, 5, 0, // Skip to: 2561 -/* 1237 */ MCD_OPC_CheckField, 4, 1, 0, 37, 5, 0, // Skip to: 2561 -/* 1244 */ MCD_OPC_Decode, 138, 14, 238, 2, // Opcode: VMOVH -/* 1249 */ MCD_OPC_FilterValue, 1, 27, 5, 0, // Skip to: 2561 -/* 1254 */ MCD_OPC_CheckPredicate, 60, 22, 5, 0, // Skip to: 2561 -/* 1259 */ MCD_OPC_CheckField, 23, 9, 253, 3, 14, 5, 0, // Skip to: 2561 -/* 1267 */ MCD_OPC_CheckField, 4, 1, 0, 7, 5, 0, // Skip to: 2561 -/* 1274 */ MCD_OPC_Decode, 198, 10, 238, 2, // Opcode: VINSH -/* 1279 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 1316 -/* 1284 */ MCD_OPC_CheckPredicate, 66, 248, 4, 0, // Skip to: 2561 -/* 1289 */ MCD_OPC_CheckField, 23, 9, 253, 3, 240, 4, 0, // Skip to: 2561 -/* 1297 */ MCD_OPC_CheckField, 7, 1, 0, 233, 4, 0, // Skip to: 2561 -/* 1304 */ MCD_OPC_CheckField, 4, 1, 0, 226, 4, 0, // Skip to: 2561 -/* 1311 */ MCD_OPC_Decode, 253, 16, 238, 2, // Opcode: VRINTAS -/* 1316 */ MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 1353 -/* 1321 */ MCD_OPC_CheckPredicate, 66, 211, 4, 0, // Skip to: 2561 -/* 1326 */ MCD_OPC_CheckField, 23, 9, 253, 3, 203, 4, 0, // Skip to: 2561 -/* 1334 */ MCD_OPC_CheckField, 7, 1, 0, 196, 4, 0, // Skip to: 2561 -/* 1341 */ MCD_OPC_CheckField, 4, 1, 0, 189, 4, 0, // Skip to: 2561 -/* 1348 */ MCD_OPC_Decode, 139, 17, 238, 2, // Opcode: VRINTNS -/* 1353 */ MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 1390 -/* 1358 */ MCD_OPC_CheckPredicate, 66, 174, 4, 0, // Skip to: 2561 -/* 1363 */ MCD_OPC_CheckField, 23, 9, 253, 3, 166, 4, 0, // Skip to: 2561 -/* 1371 */ MCD_OPC_CheckField, 7, 1, 0, 159, 4, 0, // Skip to: 2561 -/* 1378 */ MCD_OPC_CheckField, 4, 1, 0, 152, 4, 0, // Skip to: 2561 -/* 1385 */ MCD_OPC_Decode, 146, 17, 238, 2, // Opcode: VRINTPS -/* 1390 */ MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 1427 -/* 1395 */ MCD_OPC_CheckPredicate, 66, 137, 4, 0, // Skip to: 2561 -/* 1400 */ MCD_OPC_CheckField, 23, 9, 253, 3, 129, 4, 0, // Skip to: 2561 -/* 1408 */ MCD_OPC_CheckField, 7, 1, 0, 122, 4, 0, // Skip to: 2561 -/* 1415 */ MCD_OPC_CheckField, 4, 1, 0, 115, 4, 0, // Skip to: 2561 -/* 1422 */ MCD_OPC_Decode, 132, 17, 238, 2, // Opcode: VRINTMS -/* 1427 */ MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 1495 -/* 1432 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 1435 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1465 -/* 1440 */ MCD_OPC_CheckPredicate, 66, 92, 4, 0, // Skip to: 2561 -/* 1445 */ MCD_OPC_CheckField, 23, 9, 253, 3, 84, 4, 0, // Skip to: 2561 -/* 1453 */ MCD_OPC_CheckField, 4, 1, 0, 77, 4, 0, // Skip to: 2561 -/* 1460 */ MCD_OPC_Decode, 166, 9, 238, 2, // Opcode: VCVTAUS -/* 1465 */ MCD_OPC_FilterValue, 1, 67, 4, 0, // Skip to: 2561 -/* 1470 */ MCD_OPC_CheckPredicate, 66, 62, 4, 0, // Skip to: 2561 -/* 1475 */ MCD_OPC_CheckField, 23, 9, 253, 3, 54, 4, 0, // Skip to: 2561 -/* 1483 */ MCD_OPC_CheckField, 4, 1, 0, 47, 4, 0, // Skip to: 2561 -/* 1490 */ MCD_OPC_Decode, 163, 9, 238, 2, // Opcode: VCVTASS -/* 1495 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1563 -/* 1500 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 1503 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1533 -/* 1508 */ MCD_OPC_CheckPredicate, 66, 24, 4, 0, // Skip to: 2561 -/* 1513 */ MCD_OPC_CheckField, 23, 9, 253, 3, 16, 4, 0, // Skip to: 2561 -/* 1521 */ MCD_OPC_CheckField, 4, 1, 0, 9, 4, 0, // Skip to: 2561 -/* 1528 */ MCD_OPC_Decode, 199, 9, 238, 2, // Opcode: VCVTNUS -/* 1533 */ MCD_OPC_FilterValue, 1, 255, 3, 0, // Skip to: 2561 -/* 1538 */ MCD_OPC_CheckPredicate, 66, 250, 3, 0, // Skip to: 2561 -/* 1543 */ MCD_OPC_CheckField, 23, 9, 253, 3, 242, 3, 0, // Skip to: 2561 -/* 1551 */ MCD_OPC_CheckField, 4, 1, 0, 235, 3, 0, // Skip to: 2561 -/* 1558 */ MCD_OPC_Decode, 196, 9, 238, 2, // Opcode: VCVTNSS -/* 1563 */ MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 1631 -/* 1568 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 1571 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1601 -/* 1576 */ MCD_OPC_CheckPredicate, 66, 212, 3, 0, // Skip to: 2561 -/* 1581 */ MCD_OPC_CheckField, 23, 9, 253, 3, 204, 3, 0, // Skip to: 2561 -/* 1589 */ MCD_OPC_CheckField, 4, 1, 0, 197, 3, 0, // Skip to: 2561 -/* 1596 */ MCD_OPC_Decode, 213, 9, 238, 2, // Opcode: VCVTPUS -/* 1601 */ MCD_OPC_FilterValue, 1, 187, 3, 0, // Skip to: 2561 -/* 1606 */ MCD_OPC_CheckPredicate, 66, 182, 3, 0, // Skip to: 2561 -/* 1611 */ MCD_OPC_CheckField, 23, 9, 253, 3, 174, 3, 0, // Skip to: 2561 -/* 1619 */ MCD_OPC_CheckField, 4, 1, 0, 167, 3, 0, // Skip to: 2561 -/* 1626 */ MCD_OPC_Decode, 210, 9, 238, 2, // Opcode: VCVTPSS -/* 1631 */ MCD_OPC_FilterValue, 15, 157, 3, 0, // Skip to: 2561 -/* 1636 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 1639 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1669 -/* 1644 */ MCD_OPC_CheckPredicate, 66, 144, 3, 0, // Skip to: 2561 -/* 1649 */ MCD_OPC_CheckField, 23, 9, 253, 3, 136, 3, 0, // Skip to: 2561 -/* 1657 */ MCD_OPC_CheckField, 4, 1, 0, 129, 3, 0, // Skip to: 2561 -/* 1664 */ MCD_OPC_Decode, 185, 9, 238, 2, // Opcode: VCVTMUS -/* 1669 */ MCD_OPC_FilterValue, 1, 119, 3, 0, // Skip to: 2561 -/* 1674 */ MCD_OPC_CheckPredicate, 66, 114, 3, 0, // Skip to: 2561 -/* 1679 */ MCD_OPC_CheckField, 23, 9, 253, 3, 106, 3, 0, // Skip to: 2561 -/* 1687 */ MCD_OPC_CheckField, 4, 1, 0, 99, 3, 0, // Skip to: 2561 -/* 1694 */ MCD_OPC_Decode, 182, 9, 238, 2, // Opcode: VCVTMSS -/* 1699 */ MCD_OPC_FilterValue, 11, 113, 2, 0, // Skip to: 2329 -/* 1704 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 1707 */ MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 1796 -/* 1712 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1715 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1767 -/* 1720 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 1723 */ MCD_OPC_FilterValue, 252, 3, 16, 0, 0, // Skip to: 1745 -/* 1729 */ MCD_OPC_CheckPredicate, 69, 59, 3, 0, // Skip to: 2561 -/* 1734 */ MCD_OPC_CheckField, 4, 1, 0, 52, 3, 0, // Skip to: 2561 -/* 1741 */ MCD_OPC_Decode, 232, 17, 97, // Opcode: VSELEQD -/* 1745 */ MCD_OPC_FilterValue, 253, 3, 42, 3, 0, // Skip to: 2561 -/* 1751 */ MCD_OPC_CheckPredicate, 69, 37, 3, 0, // Skip to: 2561 -/* 1756 */ MCD_OPC_CheckField, 4, 1, 0, 30, 3, 0, // Skip to: 2561 -/* 1763 */ MCD_OPC_Decode, 156, 13, 97, // Opcode: VMAXNMD -/* 1767 */ MCD_OPC_FilterValue, 1, 21, 3, 0, // Skip to: 2561 -/* 1772 */ MCD_OPC_CheckPredicate, 69, 16, 3, 0, // Skip to: 2561 -/* 1777 */ MCD_OPC_CheckField, 23, 9, 253, 3, 8, 3, 0, // Skip to: 2561 -/* 1785 */ MCD_OPC_CheckField, 4, 1, 0, 1, 3, 0, // Skip to: 2561 -/* 1792 */ MCD_OPC_Decode, 179, 13, 97, // Opcode: VMINNMD -/* 1796 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 1832 -/* 1801 */ MCD_OPC_CheckPredicate, 69, 243, 2, 0, // Skip to: 2561 -/* 1806 */ MCD_OPC_CheckField, 23, 9, 252, 3, 235, 2, 0, // Skip to: 2561 -/* 1814 */ MCD_OPC_CheckField, 6, 1, 0, 228, 2, 0, // Skip to: 2561 -/* 1821 */ MCD_OPC_CheckField, 4, 1, 0, 221, 2, 0, // Skip to: 2561 -/* 1828 */ MCD_OPC_Decode, 241, 17, 97, // Opcode: VSELVSD -/* 1832 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1868 -/* 1837 */ MCD_OPC_CheckPredicate, 69, 207, 2, 0, // Skip to: 2561 -/* 1842 */ MCD_OPC_CheckField, 23, 9, 252, 3, 199, 2, 0, // Skip to: 2561 -/* 1850 */ MCD_OPC_CheckField, 6, 1, 0, 192, 2, 0, // Skip to: 2561 -/* 1857 */ MCD_OPC_CheckField, 4, 1, 0, 185, 2, 0, // Skip to: 2561 -/* 1864 */ MCD_OPC_Decode, 235, 17, 97, // Opcode: VSELGED -/* 1868 */ MCD_OPC_FilterValue, 3, 176, 2, 0, // Skip to: 2561 -/* 1873 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1876 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1905 -/* 1881 */ MCD_OPC_CheckPredicate, 69, 163, 2, 0, // Skip to: 2561 -/* 1886 */ MCD_OPC_CheckField, 23, 9, 252, 3, 155, 2, 0, // Skip to: 2561 -/* 1894 */ MCD_OPC_CheckField, 4, 1, 0, 148, 2, 0, // Skip to: 2561 -/* 1901 */ MCD_OPC_Decode, 238, 17, 97, // Opcode: VSELGTD -/* 1905 */ MCD_OPC_FilterValue, 1, 139, 2, 0, // Skip to: 2561 -/* 1910 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 1913 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 1949 -/* 1918 */ MCD_OPC_CheckPredicate, 69, 126, 2, 0, // Skip to: 2561 -/* 1923 */ MCD_OPC_CheckField, 23, 9, 253, 3, 118, 2, 0, // Skip to: 2561 -/* 1931 */ MCD_OPC_CheckField, 7, 1, 0, 111, 2, 0, // Skip to: 2561 -/* 1938 */ MCD_OPC_CheckField, 4, 1, 0, 104, 2, 0, // Skip to: 2561 -/* 1945 */ MCD_OPC_Decode, 247, 16, 126, // Opcode: VRINTAD -/* 1949 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 1985 -/* 1954 */ MCD_OPC_CheckPredicate, 69, 90, 2, 0, // Skip to: 2561 -/* 1959 */ MCD_OPC_CheckField, 23, 9, 253, 3, 82, 2, 0, // Skip to: 2561 -/* 1967 */ MCD_OPC_CheckField, 7, 1, 0, 75, 2, 0, // Skip to: 2561 -/* 1974 */ MCD_OPC_CheckField, 4, 1, 0, 68, 2, 0, // Skip to: 2561 -/* 1981 */ MCD_OPC_Decode, 133, 17, 126, // Opcode: VRINTND -/* 1985 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 2021 -/* 1990 */ MCD_OPC_CheckPredicate, 69, 54, 2, 0, // Skip to: 2561 -/* 1995 */ MCD_OPC_CheckField, 23, 9, 253, 3, 46, 2, 0, // Skip to: 2561 -/* 2003 */ MCD_OPC_CheckField, 7, 1, 0, 39, 2, 0, // Skip to: 2561 -/* 2010 */ MCD_OPC_CheckField, 4, 1, 0, 32, 2, 0, // Skip to: 2561 -/* 2017 */ MCD_OPC_Decode, 140, 17, 126, // Opcode: VRINTPD -/* 2021 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 2057 -/* 2026 */ MCD_OPC_CheckPredicate, 69, 18, 2, 0, // Skip to: 2561 -/* 2031 */ MCD_OPC_CheckField, 23, 9, 253, 3, 10, 2, 0, // Skip to: 2561 -/* 2039 */ MCD_OPC_CheckField, 7, 1, 0, 3, 2, 0, // Skip to: 2561 -/* 2046 */ MCD_OPC_CheckField, 4, 1, 0, 252, 1, 0, // Skip to: 2561 -/* 2053 */ MCD_OPC_Decode, 254, 16, 126, // Opcode: VRINTMD -/* 2057 */ MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 2125 -/* 2062 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 2065 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2095 -/* 2070 */ MCD_OPC_CheckPredicate, 69, 230, 1, 0, // Skip to: 2561 -/* 2075 */ MCD_OPC_CheckField, 23, 9, 253, 3, 222, 1, 0, // Skip to: 2561 -/* 2083 */ MCD_OPC_CheckField, 4, 1, 0, 215, 1, 0, // Skip to: 2561 -/* 2090 */ MCD_OPC_Decode, 164, 9, 241, 2, // Opcode: VCVTAUD -/* 2095 */ MCD_OPC_FilterValue, 1, 205, 1, 0, // Skip to: 2561 -/* 2100 */ MCD_OPC_CheckPredicate, 69, 200, 1, 0, // Skip to: 2561 -/* 2105 */ MCD_OPC_CheckField, 23, 9, 253, 3, 192, 1, 0, // Skip to: 2561 -/* 2113 */ MCD_OPC_CheckField, 4, 1, 0, 185, 1, 0, // Skip to: 2561 -/* 2120 */ MCD_OPC_Decode, 161, 9, 241, 2, // Opcode: VCVTASD -/* 2125 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 2193 -/* 2130 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 2133 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2163 -/* 2138 */ MCD_OPC_CheckPredicate, 69, 162, 1, 0, // Skip to: 2561 -/* 2143 */ MCD_OPC_CheckField, 23, 9, 253, 3, 154, 1, 0, // Skip to: 2561 -/* 2151 */ MCD_OPC_CheckField, 4, 1, 0, 147, 1, 0, // Skip to: 2561 -/* 2158 */ MCD_OPC_Decode, 197, 9, 241, 2, // Opcode: VCVTNUD -/* 2163 */ MCD_OPC_FilterValue, 1, 137, 1, 0, // Skip to: 2561 -/* 2168 */ MCD_OPC_CheckPredicate, 69, 132, 1, 0, // Skip to: 2561 -/* 2173 */ MCD_OPC_CheckField, 23, 9, 253, 3, 124, 1, 0, // Skip to: 2561 -/* 2181 */ MCD_OPC_CheckField, 4, 1, 0, 117, 1, 0, // Skip to: 2561 -/* 2188 */ MCD_OPC_Decode, 194, 9, 241, 2, // Opcode: VCVTNSD -/* 2193 */ MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 2261 -/* 2198 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 2201 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2231 -/* 2206 */ MCD_OPC_CheckPredicate, 69, 94, 1, 0, // Skip to: 2561 -/* 2211 */ MCD_OPC_CheckField, 23, 9, 253, 3, 86, 1, 0, // Skip to: 2561 -/* 2219 */ MCD_OPC_CheckField, 4, 1, 0, 79, 1, 0, // Skip to: 2561 -/* 2226 */ MCD_OPC_Decode, 211, 9, 241, 2, // Opcode: VCVTPUD -/* 2231 */ MCD_OPC_FilterValue, 1, 69, 1, 0, // Skip to: 2561 -/* 2236 */ MCD_OPC_CheckPredicate, 69, 64, 1, 0, // Skip to: 2561 -/* 2241 */ MCD_OPC_CheckField, 23, 9, 253, 3, 56, 1, 0, // Skip to: 2561 -/* 2249 */ MCD_OPC_CheckField, 4, 1, 0, 49, 1, 0, // Skip to: 2561 -/* 2256 */ MCD_OPC_Decode, 208, 9, 241, 2, // Opcode: VCVTPSD -/* 2261 */ MCD_OPC_FilterValue, 15, 39, 1, 0, // Skip to: 2561 -/* 2266 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... -/* 2269 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2299 -/* 2274 */ MCD_OPC_CheckPredicate, 69, 26, 1, 0, // Skip to: 2561 -/* 2279 */ MCD_OPC_CheckField, 23, 9, 253, 3, 18, 1, 0, // Skip to: 2561 -/* 2287 */ MCD_OPC_CheckField, 4, 1, 0, 11, 1, 0, // Skip to: 2561 -/* 2294 */ MCD_OPC_Decode, 183, 9, 241, 2, // Opcode: VCVTMUD -/* 2299 */ MCD_OPC_FilterValue, 1, 1, 1, 0, // Skip to: 2561 -/* 2304 */ MCD_OPC_CheckPredicate, 69, 252, 0, 0, // Skip to: 2561 -/* 2309 */ MCD_OPC_CheckField, 23, 9, 253, 3, 244, 0, 0, // Skip to: 2561 -/* 2317 */ MCD_OPC_CheckField, 4, 1, 0, 237, 0, 0, // Skip to: 2561 -/* 2324 */ MCD_OPC_Decode, 180, 9, 241, 2, // Opcode: VCVTMSD -/* 2329 */ MCD_OPC_FilterValue, 13, 227, 0, 0, // Skip to: 2561 -/* 2334 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 2337 */ MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 2449 -/* 2342 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2345 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 2397 -/* 2350 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2353 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2375 -/* 2359 */ MCD_OPC_CheckPredicate, 73, 197, 0, 0, // Skip to: 2561 -/* 2364 */ MCD_OPC_CheckField, 20, 2, 2, 190, 0, 0, // Skip to: 2561 -/* 2371 */ MCD_OPC_Decode, 228, 17, 105, // Opcode: VSDOTD -/* 2375 */ MCD_OPC_FilterValue, 252, 3, 180, 0, 0, // Skip to: 2561 -/* 2381 */ MCD_OPC_CheckPredicate, 73, 175, 0, 0, // Skip to: 2561 -/* 2386 */ MCD_OPC_CheckField, 20, 2, 2, 168, 0, 0, // Skip to: 2561 -/* 2393 */ MCD_OPC_Decode, 229, 17, 113, // Opcode: VSDOTDI -/* 2397 */ MCD_OPC_FilterValue, 1, 159, 0, 0, // Skip to: 2561 -/* 2402 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2405 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2427 -/* 2411 */ MCD_OPC_CheckPredicate, 73, 145, 0, 0, // Skip to: 2561 -/* 2416 */ MCD_OPC_CheckField, 20, 2, 2, 138, 0, 0, // Skip to: 2561 -/* 2423 */ MCD_OPC_Decode, 230, 17, 106, // Opcode: VSDOTQ -/* 2427 */ MCD_OPC_FilterValue, 252, 3, 128, 0, 0, // Skip to: 2561 -/* 2433 */ MCD_OPC_CheckPredicate, 73, 123, 0, 0, // Skip to: 2561 -/* 2438 */ MCD_OPC_CheckField, 20, 2, 2, 116, 0, 0, // Skip to: 2561 -/* 2445 */ MCD_OPC_Decode, 231, 17, 114, // Opcode: VSDOTQI -/* 2449 */ MCD_OPC_FilterValue, 1, 107, 0, 0, // Skip to: 2561 -/* 2454 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2457 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 2509 -/* 2462 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2465 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2487 -/* 2471 */ MCD_OPC_CheckPredicate, 73, 85, 0, 0, // Skip to: 2561 -/* 2476 */ MCD_OPC_CheckField, 20, 2, 2, 78, 0, 0, // Skip to: 2561 -/* 2483 */ MCD_OPC_Decode, 159, 21, 105, // Opcode: VUDOTD -/* 2487 */ MCD_OPC_FilterValue, 252, 3, 68, 0, 0, // Skip to: 2561 -/* 2493 */ MCD_OPC_CheckPredicate, 73, 63, 0, 0, // Skip to: 2561 -/* 2498 */ MCD_OPC_CheckField, 20, 2, 2, 56, 0, 0, // Skip to: 2561 -/* 2505 */ MCD_OPC_Decode, 160, 21, 113, // Opcode: VUDOTDI -/* 2509 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 2561 -/* 2514 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 2517 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2539 -/* 2523 */ MCD_OPC_CheckPredicate, 73, 33, 0, 0, // Skip to: 2561 -/* 2528 */ MCD_OPC_CheckField, 20, 2, 2, 26, 0, 0, // Skip to: 2561 -/* 2535 */ MCD_OPC_Decode, 161, 21, 106, // Opcode: VUDOTQ -/* 2539 */ MCD_OPC_FilterValue, 252, 3, 16, 0, 0, // Skip to: 2561 -/* 2545 */ MCD_OPC_CheckPredicate, 73, 11, 0, 0, // Skip to: 2561 -/* 2550 */ MCD_OPC_CheckField, 20, 2, 2, 4, 0, 0, // Skip to: 2561 -/* 2557 */ MCD_OPC_Decode, 162, 21, 114, // Opcode: VUDOTQI -/* 2561 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3 */ MCD_OPC_FilterValue, + 8, + 47, + 2, + 0, // Skip to: 567 + /* 8 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 3, + 1, + 0, // Skip to: 275 + /* 16 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 123, + 0, + 0, // Skip to: 147 + /* 24 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 27 */ MCD_OPC_FilterValue, + 126, + 77, + 0, + 0, // Skip to: 109 + /* 32 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 35 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 57 + /* 40 */ MCD_OPC_CheckPredicate, + 88, + 119, + 12, + 0, // Skip to: 3236 + /* 45 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 112, + 12, + 0, // Skip to: 3236 + /* 52 */ MCD_OPC_Decode, + 185, + 16, + 249, + 3, // Opcode: VCADDv4f16 + /* 57 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 79 + /* 62 */ MCD_OPC_CheckPredicate, + 89, + 97, + 12, + 0, // Skip to: 3236 + /* 67 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 90, + 12, + 0, // Skip to: 3236 + /* 74 */ MCD_OPC_Decode, + 184, + 16, + 249, + 3, // Opcode: VCADDv2f32 + /* 79 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 94 + /* 84 */ MCD_OPC_CheckPredicate, + 88, + 75, + 12, + 0, // Skip to: 3236 + /* 89 */ MCD_OPC_Decode, + 166, + 17, + 250, + 3, // Opcode: VCMLAv4f16 + /* 94 */ MCD_OPC_FilterValue, + 3, + 65, + 12, + 0, // Skip to: 3236 + /* 99 */ MCD_OPC_CheckPredicate, + 89, + 60, + 12, + 0, // Skip to: 3236 + /* 104 */ MCD_OPC_Decode, + 164, + 17, + 250, + 3, // Opcode: VCMLAv2f32 + /* 109 */ MCD_OPC_FilterValue, + 127, + 50, + 12, + 0, // Skip to: 3236 + /* 114 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 117 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 132 + /* 122 */ MCD_OPC_CheckPredicate, + 88, + 37, + 12, + 0, // Skip to: 3236 + /* 127 */ MCD_OPC_Decode, + 167, + 17, + 251, + 3, // Opcode: VCMLAv4f16_indexed + /* 132 */ MCD_OPC_FilterValue, + 1, + 27, + 12, + 0, // Skip to: 3236 + /* 137 */ MCD_OPC_CheckPredicate, + 89, + 22, + 12, + 0, // Skip to: 3236 + /* 142 */ MCD_OPC_Decode, + 165, + 17, + 252, + 3, // Opcode: VCMLAv2f32_indexed + /* 147 */ MCD_OPC_FilterValue, + 1, + 12, + 12, + 0, // Skip to: 3236 + /* 152 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 155 */ MCD_OPC_FilterValue, + 126, + 77, + 0, + 0, // Skip to: 237 + /* 160 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 163 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 185 + /* 168 */ MCD_OPC_CheckPredicate, + 88, + 247, + 11, + 0, // Skip to: 3236 + /* 173 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 240, + 11, + 0, // Skip to: 3236 + /* 180 */ MCD_OPC_Decode, + 187, + 16, + 253, + 3, // Opcode: VCADDv8f16 + /* 185 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 207 + /* 190 */ MCD_OPC_CheckPredicate, + 89, + 225, + 11, + 0, // Skip to: 3236 + /* 195 */ MCD_OPC_CheckField, + 23, + 1, + 1, + 218, + 11, + 0, // Skip to: 3236 + /* 202 */ MCD_OPC_Decode, + 186, + 16, + 253, + 3, // Opcode: VCADDv4f32 + /* 207 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 222 + /* 212 */ MCD_OPC_CheckPredicate, + 88, + 203, + 11, + 0, // Skip to: 3236 + /* 217 */ MCD_OPC_Decode, + 170, + 17, + 254, + 3, // Opcode: VCMLAv8f16 + /* 222 */ MCD_OPC_FilterValue, + 3, + 193, + 11, + 0, // Skip to: 3236 + /* 227 */ MCD_OPC_CheckPredicate, + 89, + 188, + 11, + 0, // Skip to: 3236 + /* 232 */ MCD_OPC_Decode, + 168, + 17, + 254, + 3, // Opcode: VCMLAv4f32 + /* 237 */ MCD_OPC_FilterValue, + 127, + 178, + 11, + 0, // Skip to: 3236 + /* 242 */ MCD_OPC_ExtractField, + 23, + 2, // Inst{24-23} ... + /* 245 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 260 + /* 250 */ MCD_OPC_CheckPredicate, + 88, + 165, + 11, + 0, // Skip to: 3236 + /* 255 */ MCD_OPC_Decode, + 171, + 17, + 255, + 3, // Opcode: VCMLAv8f16_indexed + /* 260 */ MCD_OPC_FilterValue, + 1, + 155, + 11, + 0, // Skip to: 3236 + /* 265 */ MCD_OPC_CheckPredicate, + 89, + 150, + 11, + 0, // Skip to: 3236 + /* 270 */ MCD_OPC_Decode, + 169, + 17, + 252, + 3, // Opcode: VCMLAv4f32_indexed + /* 275 */ MCD_OPC_FilterValue, + 1, + 140, + 11, + 0, // Skip to: 3236 + /* 280 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 283 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 337 + /* 288 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 291 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 314 + /* 296 */ MCD_OPC_CheckPredicate, + 90, + 119, + 11, + 0, // Skip to: 3236 + /* 301 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 111, + 11, + 0, // Skip to: 3236 + /* 309 */ MCD_OPC_Decode, + 185, + 18, + 128, + 4, // Opcode: VFMALDI + /* 314 */ MCD_OPC_FilterValue, + 1, + 101, + 11, + 0, // Skip to: 3236 + /* 319 */ MCD_OPC_CheckPredicate, + 90, + 96, + 11, + 0, // Skip to: 3236 + /* 324 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 88, + 11, + 0, // Skip to: 3236 + /* 332 */ MCD_OPC_Decode, + 187, + 18, + 215, + 1, // Opcode: VFMALQI + /* 337 */ MCD_OPC_FilterValue, + 1, + 49, + 0, + 0, // Skip to: 391 + /* 342 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 345 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 368 + /* 350 */ MCD_OPC_CheckPredicate, + 90, + 65, + 11, + 0, // Skip to: 3236 + /* 355 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 57, + 11, + 0, // Skip to: 3236 + /* 363 */ MCD_OPC_Decode, + 196, + 18, + 128, + 4, // Opcode: VFMSLDI + /* 368 */ MCD_OPC_FilterValue, + 1, + 47, + 11, + 0, // Skip to: 3236 + /* 373 */ MCD_OPC_CheckPredicate, + 90, + 42, + 11, + 0, // Skip to: 3236 + /* 378 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 34, + 11, + 0, // Skip to: 3236 + /* 386 */ MCD_OPC_Decode, + 198, + 18, + 215, + 1, // Opcode: VFMSLQI + /* 391 */ MCD_OPC_FilterValue, + 2, + 83, + 0, + 0, // Skip to: 479 + /* 396 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 399 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 439 + /* 404 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 407 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 423 + /* 413 */ MCD_OPC_CheckPredicate, + 90, + 2, + 11, + 0, // Skip to: 3236 + /* 418 */ MCD_OPC_Decode, + 184, + 18, + 129, + 4, // Opcode: VFMALD + /* 423 */ MCD_OPC_FilterValue, + 249, + 3, + 247, + 10, + 0, // Skip to: 3236 + /* 429 */ MCD_OPC_CheckPredicate, + 90, + 242, + 10, + 0, // Skip to: 3236 + /* 434 */ MCD_OPC_Decode, + 195, + 18, + 129, + 4, // Opcode: VFMSLD + /* 439 */ MCD_OPC_FilterValue, + 1, + 232, + 10, + 0, // Skip to: 3236 + /* 444 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 447 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 463 + /* 453 */ MCD_OPC_CheckPredicate, + 90, + 218, + 10, + 0, // Skip to: 3236 + /* 458 */ MCD_OPC_Decode, + 186, + 18, + 202, + 1, // Opcode: VFMALQ + /* 463 */ MCD_OPC_FilterValue, + 249, + 3, + 207, + 10, + 0, // Skip to: 3236 + /* 469 */ MCD_OPC_CheckPredicate, + 90, + 202, + 10, + 0, // Skip to: 3236 + /* 474 */ MCD_OPC_Decode, + 197, + 18, + 202, + 1, // Opcode: VFMSLQ + /* 479 */ MCD_OPC_FilterValue, + 3, + 192, + 10, + 0, // Skip to: 3236 + /* 484 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 487 */ MCD_OPC_FilterValue, + 0, + 35, + 0, + 0, // Skip to: 527 + /* 492 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 495 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 511 + /* 501 */ MCD_OPC_CheckPredicate, + 31, + 170, + 10, + 0, // Skip to: 3236 + /* 506 */ MCD_OPC_Decode, + 166, + 16, + 209, + 1, // Opcode: VBF16MALBQ + /* 511 */ MCD_OPC_FilterValue, + 252, + 3, + 159, + 10, + 0, // Skip to: 3236 + /* 517 */ MCD_OPC_CheckPredicate, + 31, + 154, + 10, + 0, // Skip to: 3236 + /* 522 */ MCD_OPC_Decode, + 167, + 16, + 211, + 1, // Opcode: VBF16MALBQI + /* 527 */ MCD_OPC_FilterValue, + 1, + 144, + 10, + 0, // Skip to: 3236 + /* 532 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 535 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 551 + /* 541 */ MCD_OPC_CheckPredicate, + 31, + 130, + 10, + 0, // Skip to: 3236 + /* 546 */ MCD_OPC_Decode, + 168, + 16, + 209, + 1, // Opcode: VBF16MALTQ + /* 551 */ MCD_OPC_FilterValue, + 252, + 3, + 119, + 10, + 0, // Skip to: 3236 + /* 557 */ MCD_OPC_CheckPredicate, + 31, + 114, + 10, + 0, // Skip to: 3236 + /* 562 */ MCD_OPC_Decode, + 169, + 16, + 211, + 1, // Opcode: VBF16MALTQI + /* 567 */ MCD_OPC_FilterValue, + 9, + 189, + 2, + 0, // Skip to: 1273 + /* 572 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 575 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 667 + /* 580 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 583 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 637 + /* 588 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 591 */ MCD_OPC_FilterValue, + 252, + 3, + 17, + 0, + 0, // Skip to: 614 + /* 597 */ MCD_OPC_CheckPredicate, + 74, + 74, + 10, + 0, // Skip to: 3236 + /* 602 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 67, + 10, + 0, // Skip to: 3236 + /* 609 */ MCD_OPC_Decode, + 201, + 26, + 130, + 4, // Opcode: VSELEQH + /* 614 */ MCD_OPC_FilterValue, + 253, + 3, + 56, + 10, + 0, // Skip to: 3236 + /* 620 */ MCD_OPC_CheckPredicate, + 74, + 51, + 10, + 0, // Skip to: 3236 + /* 625 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 44, + 10, + 0, // Skip to: 3236 + /* 632 */ MCD_OPC_Decode, + 211, + 18, + 130, + 4, // Opcode: VFP_VMAXNMH + /* 637 */ MCD_OPC_FilterValue, + 1, + 34, + 10, + 0, // Skip to: 3236 + /* 642 */ MCD_OPC_CheckPredicate, + 74, + 29, + 10, + 0, // Skip to: 3236 + /* 647 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 21, + 10, + 0, // Skip to: 3236 + /* 655 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 14, + 10, + 0, // Skip to: 3236 + /* 662 */ MCD_OPC_Decode, + 214, + 18, + 130, + 4, // Opcode: VFP_VMINNMH + /* 667 */ MCD_OPC_FilterValue, + 1, + 32, + 0, + 0, // Skip to: 704 + /* 672 */ MCD_OPC_CheckPredicate, + 74, + 255, + 9, + 0, // Skip to: 3236 + /* 677 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 247, + 9, + 0, // Skip to: 3236 + /* 685 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 240, + 9, + 0, // Skip to: 3236 + /* 692 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 233, + 9, + 0, // Skip to: 3236 + /* 699 */ MCD_OPC_Decode, + 210, + 26, + 130, + 4, // Opcode: VSELVSH + /* 704 */ MCD_OPC_FilterValue, + 2, + 32, + 0, + 0, // Skip to: 741 + /* 709 */ MCD_OPC_CheckPredicate, + 74, + 218, + 9, + 0, // Skip to: 3236 + /* 714 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 210, + 9, + 0, // Skip to: 3236 + /* 722 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 203, + 9, + 0, // Skip to: 3236 + /* 729 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 196, + 9, + 0, // Skip to: 3236 + /* 736 */ MCD_OPC_Decode, + 204, + 26, + 130, + 4, // Opcode: VSELGEH + /* 741 */ MCD_OPC_FilterValue, + 3, + 186, + 9, + 0, // Skip to: 3236 + /* 746 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 749 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 779 + /* 754 */ MCD_OPC_CheckPredicate, + 74, + 173, + 9, + 0, // Skip to: 3236 + /* 759 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 165, + 9, + 0, // Skip to: 3236 + /* 767 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 158, + 9, + 0, // Skip to: 3236 + /* 774 */ MCD_OPC_Decode, + 207, + 26, + 130, + 4, // Opcode: VSELGTH + /* 779 */ MCD_OPC_FilterValue, + 1, + 148, + 9, + 0, // Skip to: 3236 + /* 784 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 787 */ MCD_OPC_FilterValue, + 3, + 61, + 0, + 0, // Skip to: 853 + /* 792 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 795 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 824 + /* 800 */ MCD_OPC_CheckPredicate, + 91, + 127, + 9, + 0, // Skip to: 3236 + /* 805 */ MCD_OPC_CheckField, + 23, + 5, + 29, + 120, + 9, + 0, // Skip to: 3236 + /* 812 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 113, + 9, + 0, // Skip to: 3236 + /* 819 */ MCD_OPC_Decode, + 197, + 5, + 131, + 4, // Opcode: BF16_VCVTB + /* 824 */ MCD_OPC_FilterValue, + 1, + 103, + 9, + 0, // Skip to: 3236 + /* 829 */ MCD_OPC_CheckPredicate, + 91, + 98, + 9, + 0, // Skip to: 3236 + /* 834 */ MCD_OPC_CheckField, + 23, + 5, + 29, + 91, + 9, + 0, // Skip to: 3236 + /* 841 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 84, + 9, + 0, // Skip to: 3236 + /* 848 */ MCD_OPC_Decode, + 198, + 5, + 131, + 4, // Opcode: BF16_VCVTT + /* 853 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 890 + /* 858 */ MCD_OPC_CheckPredicate, + 74, + 69, + 9, + 0, // Skip to: 3236 + /* 863 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 61, + 9, + 0, // Skip to: 3236 + /* 871 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 54, + 9, + 0, // Skip to: 3236 + /* 878 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 47, + 9, + 0, // Skip to: 3236 + /* 885 */ MCD_OPC_Decode, + 214, + 25, + 132, + 4, // Opcode: VRINTAH + /* 890 */ MCD_OPC_FilterValue, + 9, + 32, + 0, + 0, // Skip to: 927 + /* 895 */ MCD_OPC_CheckPredicate, + 74, + 32, + 9, + 0, // Skip to: 3236 + /* 900 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 24, + 9, + 0, // Skip to: 3236 + /* 908 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 17, + 9, + 0, // Skip to: 3236 + /* 915 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 10, + 9, + 0, // Skip to: 3236 + /* 922 */ MCD_OPC_Decode, + 228, + 25, + 132, + 4, // Opcode: VRINTNH + /* 927 */ MCD_OPC_FilterValue, + 10, + 32, + 0, + 0, // Skip to: 964 + /* 932 */ MCD_OPC_CheckPredicate, + 74, + 251, + 8, + 0, // Skip to: 3236 + /* 937 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 243, + 8, + 0, // Skip to: 3236 + /* 945 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 236, + 8, + 0, // Skip to: 3236 + /* 952 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 229, + 8, + 0, // Skip to: 3236 + /* 959 */ MCD_OPC_Decode, + 235, + 25, + 132, + 4, // Opcode: VRINTPH + /* 964 */ MCD_OPC_FilterValue, + 11, + 32, + 0, + 0, // Skip to: 1001 + /* 969 */ MCD_OPC_CheckPredicate, + 74, + 214, + 8, + 0, // Skip to: 3236 + /* 974 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 206, + 8, + 0, // Skip to: 3236 + /* 982 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 199, + 8, + 0, // Skip to: 3236 + /* 989 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 192, + 8, + 0, // Skip to: 3236 + /* 996 */ MCD_OPC_Decode, + 221, + 25, + 132, + 4, // Opcode: VRINTMH + /* 1001 */ MCD_OPC_FilterValue, + 12, + 63, + 0, + 0, // Skip to: 1069 + /* 1006 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1009 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1039 + /* 1014 */ MCD_OPC_CheckPredicate, + 74, + 169, + 8, + 0, // Skip to: 3236 + /* 1019 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 161, + 8, + 0, // Skip to: 3236 + /* 1027 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 154, + 8, + 0, // Skip to: 3236 + /* 1034 */ MCD_OPC_Decode, + 198, + 17, + 133, + 4, // Opcode: VCVTAUH + /* 1039 */ MCD_OPC_FilterValue, + 1, + 144, + 8, + 0, // Skip to: 3236 + /* 1044 */ MCD_OPC_CheckPredicate, + 74, + 139, + 8, + 0, // Skip to: 3236 + /* 1049 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 131, + 8, + 0, // Skip to: 3236 + /* 1057 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 124, + 8, + 0, // Skip to: 3236 + /* 1064 */ MCD_OPC_Decode, + 195, + 17, + 133, + 4, // Opcode: VCVTASH + /* 1069 */ MCD_OPC_FilterValue, + 13, + 63, + 0, + 0, // Skip to: 1137 + /* 1074 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1077 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1107 + /* 1082 */ MCD_OPC_CheckPredicate, + 74, + 101, + 8, + 0, // Skip to: 3236 + /* 1087 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 93, + 8, + 0, // Skip to: 3236 + /* 1095 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 86, + 8, + 0, // Skip to: 3236 + /* 1102 */ MCD_OPC_Decode, + 231, + 17, + 133, + 4, // Opcode: VCVTNUH + /* 1107 */ MCD_OPC_FilterValue, + 1, + 76, + 8, + 0, // Skip to: 3236 + /* 1112 */ MCD_OPC_CheckPredicate, + 74, + 71, + 8, + 0, // Skip to: 3236 + /* 1117 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 63, + 8, + 0, // Skip to: 3236 + /* 1125 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 56, + 8, + 0, // Skip to: 3236 + /* 1132 */ MCD_OPC_Decode, + 228, + 17, + 133, + 4, // Opcode: VCVTNSH + /* 1137 */ MCD_OPC_FilterValue, + 14, + 63, + 0, + 0, // Skip to: 1205 + /* 1142 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1145 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1175 + /* 1150 */ MCD_OPC_CheckPredicate, + 74, + 33, + 8, + 0, // Skip to: 3236 + /* 1155 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 25, + 8, + 0, // Skip to: 3236 + /* 1163 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 18, + 8, + 0, // Skip to: 3236 + /* 1170 */ MCD_OPC_Decode, + 245, + 17, + 133, + 4, // Opcode: VCVTPUH + /* 1175 */ MCD_OPC_FilterValue, + 1, + 8, + 8, + 0, // Skip to: 3236 + /* 1180 */ MCD_OPC_CheckPredicate, + 74, + 3, + 8, + 0, // Skip to: 3236 + /* 1185 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 251, + 7, + 0, // Skip to: 3236 + /* 1193 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 7, + 0, // Skip to: 3236 + /* 1200 */ MCD_OPC_Decode, + 242, + 17, + 133, + 4, // Opcode: VCVTPSH + /* 1205 */ MCD_OPC_FilterValue, + 15, + 234, + 7, + 0, // Skip to: 3236 + /* 1210 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1213 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1243 + /* 1218 */ MCD_OPC_CheckPredicate, + 74, + 221, + 7, + 0, // Skip to: 3236 + /* 1223 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 213, + 7, + 0, // Skip to: 3236 + /* 1231 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 206, + 7, + 0, // Skip to: 3236 + /* 1238 */ MCD_OPC_Decode, + 217, + 17, + 133, + 4, // Opcode: VCVTMUH + /* 1243 */ MCD_OPC_FilterValue, + 1, + 196, + 7, + 0, // Skip to: 3236 + /* 1248 */ MCD_OPC_CheckPredicate, + 74, + 191, + 7, + 0, // Skip to: 3236 + /* 1253 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 183, + 7, + 0, // Skip to: 3236 + /* 1261 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 176, + 7, + 0, // Skip to: 3236 + /* 1268 */ MCD_OPC_Decode, + 214, + 17, + 133, + 4, // Opcode: VCVTMSH + /* 1273 */ MCD_OPC_FilterValue, + 10, + 191, + 2, + 0, // Skip to: 1981 + /* 1278 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1281 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 1373 + /* 1286 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1289 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 1343 + /* 1294 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 1297 */ MCD_OPC_FilterValue, + 252, + 3, + 17, + 0, + 0, // Skip to: 1320 + /* 1303 */ MCD_OPC_CheckPredicate, + 81, + 136, + 7, + 0, // Skip to: 3236 + /* 1308 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 129, + 7, + 0, // Skip to: 3236 + /* 1315 */ MCD_OPC_Decode, + 202, + 26, + 134, + 4, // Opcode: VSELEQS + /* 1320 */ MCD_OPC_FilterValue, + 253, + 3, + 118, + 7, + 0, // Skip to: 3236 + /* 1326 */ MCD_OPC_CheckPredicate, + 81, + 113, + 7, + 0, // Skip to: 3236 + /* 1331 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 106, + 7, + 0, // Skip to: 3236 + /* 1338 */ MCD_OPC_Decode, + 212, + 18, + 134, + 4, // Opcode: VFP_VMAXNMS + /* 1343 */ MCD_OPC_FilterValue, + 1, + 96, + 7, + 0, // Skip to: 3236 + /* 1348 */ MCD_OPC_CheckPredicate, + 81, + 91, + 7, + 0, // Skip to: 3236 + /* 1353 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 83, + 7, + 0, // Skip to: 3236 + /* 1361 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 76, + 7, + 0, // Skip to: 3236 + /* 1368 */ MCD_OPC_Decode, + 215, + 18, + 134, + 4, // Opcode: VFP_VMINNMS + /* 1373 */ MCD_OPC_FilterValue, + 1, + 32, + 0, + 0, // Skip to: 1410 + /* 1378 */ MCD_OPC_CheckPredicate, + 81, + 61, + 7, + 0, // Skip to: 3236 + /* 1383 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 53, + 7, + 0, // Skip to: 3236 + /* 1391 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 46, + 7, + 0, // Skip to: 3236 + /* 1398 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 39, + 7, + 0, // Skip to: 3236 + /* 1405 */ MCD_OPC_Decode, + 211, + 26, + 134, + 4, // Opcode: VSELVSS + /* 1410 */ MCD_OPC_FilterValue, + 2, + 32, + 0, + 0, // Skip to: 1447 + /* 1415 */ MCD_OPC_CheckPredicate, + 81, + 24, + 7, + 0, // Skip to: 3236 + /* 1420 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 16, + 7, + 0, // Skip to: 3236 + /* 1428 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 9, + 7, + 0, // Skip to: 3236 + /* 1435 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 2, + 7, + 0, // Skip to: 3236 + /* 1442 */ MCD_OPC_Decode, + 205, + 26, + 134, + 4, // Opcode: VSELGES + /* 1447 */ MCD_OPC_FilterValue, + 3, + 248, + 6, + 0, // Skip to: 3236 + /* 1452 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1455 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1485 + /* 1460 */ MCD_OPC_CheckPredicate, + 81, + 235, + 6, + 0, // Skip to: 3236 + /* 1465 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 227, + 6, + 0, // Skip to: 3236 + /* 1473 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 220, + 6, + 0, // Skip to: 3236 + /* 1480 */ MCD_OPC_Decode, + 208, + 26, + 134, + 4, // Opcode: VSELGTS + /* 1485 */ MCD_OPC_FilterValue, + 1, + 210, + 6, + 0, // Skip to: 3236 + /* 1490 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 1493 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 1561 + /* 1498 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1501 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1531 + /* 1506 */ MCD_OPC_CheckPredicate, + 74, + 189, + 6, + 0, // Skip to: 3236 + /* 1511 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 181, + 6, + 0, // Skip to: 3236 + /* 1519 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 174, + 6, + 0, // Skip to: 3236 + /* 1526 */ MCD_OPC_Decode, + 222, + 22, + 135, + 4, // Opcode: VMOVH + /* 1531 */ MCD_OPC_FilterValue, + 1, + 164, + 6, + 0, // Skip to: 3236 + /* 1536 */ MCD_OPC_CheckPredicate, + 74, + 159, + 6, + 0, // Skip to: 3236 + /* 1541 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 151, + 6, + 0, // Skip to: 3236 + /* 1549 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 144, + 6, + 0, // Skip to: 3236 + /* 1556 */ MCD_OPC_Decode, + 245, + 18, + 136, + 4, // Opcode: VINSH + /* 1561 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 1598 + /* 1566 */ MCD_OPC_CheckPredicate, + 81, + 129, + 6, + 0, // Skip to: 3236 + /* 1571 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 121, + 6, + 0, // Skip to: 3236 + /* 1579 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 114, + 6, + 0, // Skip to: 3236 + /* 1586 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 107, + 6, + 0, // Skip to: 3236 + /* 1593 */ MCD_OPC_Decode, + 219, + 25, + 135, + 4, // Opcode: VRINTAS + /* 1598 */ MCD_OPC_FilterValue, + 9, + 32, + 0, + 0, // Skip to: 1635 + /* 1603 */ MCD_OPC_CheckPredicate, + 81, + 92, + 6, + 0, // Skip to: 3236 + /* 1608 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 84, + 6, + 0, // Skip to: 3236 + /* 1616 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 77, + 6, + 0, // Skip to: 3236 + /* 1623 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 70, + 6, + 0, // Skip to: 3236 + /* 1630 */ MCD_OPC_Decode, + 233, + 25, + 135, + 4, // Opcode: VRINTNS + /* 1635 */ MCD_OPC_FilterValue, + 10, + 32, + 0, + 0, // Skip to: 1672 + /* 1640 */ MCD_OPC_CheckPredicate, + 81, + 55, + 6, + 0, // Skip to: 3236 + /* 1645 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 47, + 6, + 0, // Skip to: 3236 + /* 1653 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 40, + 6, + 0, // Skip to: 3236 + /* 1660 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 33, + 6, + 0, // Skip to: 3236 + /* 1667 */ MCD_OPC_Decode, + 240, + 25, + 135, + 4, // Opcode: VRINTPS + /* 1672 */ MCD_OPC_FilterValue, + 11, + 32, + 0, + 0, // Skip to: 1709 + /* 1677 */ MCD_OPC_CheckPredicate, + 81, + 18, + 6, + 0, // Skip to: 3236 + /* 1682 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 10, + 6, + 0, // Skip to: 3236 + /* 1690 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 3, + 6, + 0, // Skip to: 3236 + /* 1697 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 252, + 5, + 0, // Skip to: 3236 + /* 1704 */ MCD_OPC_Decode, + 226, + 25, + 135, + 4, // Opcode: VRINTMS + /* 1709 */ MCD_OPC_FilterValue, + 12, + 63, + 0, + 0, // Skip to: 1777 + /* 1714 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1717 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1747 + /* 1722 */ MCD_OPC_CheckPredicate, + 81, + 229, + 5, + 0, // Skip to: 3236 + /* 1727 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 221, + 5, + 0, // Skip to: 3236 + /* 1735 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 214, + 5, + 0, // Skip to: 3236 + /* 1742 */ MCD_OPC_Decode, + 199, + 17, + 135, + 4, // Opcode: VCVTAUS + /* 1747 */ MCD_OPC_FilterValue, + 1, + 204, + 5, + 0, // Skip to: 3236 + /* 1752 */ MCD_OPC_CheckPredicate, + 81, + 199, + 5, + 0, // Skip to: 3236 + /* 1757 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 191, + 5, + 0, // Skip to: 3236 + /* 1765 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 184, + 5, + 0, // Skip to: 3236 + /* 1772 */ MCD_OPC_Decode, + 196, + 17, + 135, + 4, // Opcode: VCVTASS + /* 1777 */ MCD_OPC_FilterValue, + 13, + 63, + 0, + 0, // Skip to: 1845 + /* 1782 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1785 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1815 + /* 1790 */ MCD_OPC_CheckPredicate, + 81, + 161, + 5, + 0, // Skip to: 3236 + /* 1795 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 153, + 5, + 0, // Skip to: 3236 + /* 1803 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 146, + 5, + 0, // Skip to: 3236 + /* 1810 */ MCD_OPC_Decode, + 232, + 17, + 135, + 4, // Opcode: VCVTNUS + /* 1815 */ MCD_OPC_FilterValue, + 1, + 136, + 5, + 0, // Skip to: 3236 + /* 1820 */ MCD_OPC_CheckPredicate, + 81, + 131, + 5, + 0, // Skip to: 3236 + /* 1825 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 123, + 5, + 0, // Skip to: 3236 + /* 1833 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 116, + 5, + 0, // Skip to: 3236 + /* 1840 */ MCD_OPC_Decode, + 229, + 17, + 135, + 4, // Opcode: VCVTNSS + /* 1845 */ MCD_OPC_FilterValue, + 14, + 63, + 0, + 0, // Skip to: 1913 + /* 1850 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1853 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1883 + /* 1858 */ MCD_OPC_CheckPredicate, + 81, + 93, + 5, + 0, // Skip to: 3236 + /* 1863 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 85, + 5, + 0, // Skip to: 3236 + /* 1871 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 78, + 5, + 0, // Skip to: 3236 + /* 1878 */ MCD_OPC_Decode, + 246, + 17, + 135, + 4, // Opcode: VCVTPUS + /* 1883 */ MCD_OPC_FilterValue, + 1, + 68, + 5, + 0, // Skip to: 3236 + /* 1888 */ MCD_OPC_CheckPredicate, + 81, + 63, + 5, + 0, // Skip to: 3236 + /* 1893 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 55, + 5, + 0, // Skip to: 3236 + /* 1901 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 48, + 5, + 0, // Skip to: 3236 + /* 1908 */ MCD_OPC_Decode, + 243, + 17, + 135, + 4, // Opcode: VCVTPSS + /* 1913 */ MCD_OPC_FilterValue, + 15, + 38, + 5, + 0, // Skip to: 3236 + /* 1918 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 1921 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 1951 + /* 1926 */ MCD_OPC_CheckPredicate, + 81, + 25, + 5, + 0, // Skip to: 3236 + /* 1931 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 17, + 5, + 0, // Skip to: 3236 + /* 1939 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 10, + 5, + 0, // Skip to: 3236 + /* 1946 */ MCD_OPC_Decode, + 218, + 17, + 135, + 4, // Opcode: VCVTMUS + /* 1951 */ MCD_OPC_FilterValue, + 1, + 0, + 5, + 0, // Skip to: 3236 + /* 1956 */ MCD_OPC_CheckPredicate, + 81, + 251, + 4, + 0, // Skip to: 3236 + /* 1961 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 243, + 4, + 0, // Skip to: 3236 + /* 1969 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 236, + 4, + 0, // Skip to: 3236 + /* 1976 */ MCD_OPC_Decode, + 215, + 17, + 135, + 4, // Opcode: VCVTMSS + /* 1981 */ MCD_OPC_FilterValue, + 11, + 123, + 2, + 0, // Skip to: 2621 + /* 1986 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1989 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 2081 + /* 1994 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1997 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 2051 + /* 2002 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2005 */ MCD_OPC_FilterValue, + 252, + 3, + 17, + 0, + 0, // Skip to: 2028 + /* 2011 */ MCD_OPC_CheckPredicate, + 86, + 196, + 4, + 0, // Skip to: 3236 + /* 2016 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 189, + 4, + 0, // Skip to: 3236 + /* 2023 */ MCD_OPC_Decode, + 200, + 26, + 200, + 1, // Opcode: VSELEQD + /* 2028 */ MCD_OPC_FilterValue, + 253, + 3, + 178, + 4, + 0, // Skip to: 3236 + /* 2034 */ MCD_OPC_CheckPredicate, + 86, + 173, + 4, + 0, // Skip to: 3236 + /* 2039 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 166, + 4, + 0, // Skip to: 3236 + /* 2046 */ MCD_OPC_Decode, + 210, + 18, + 200, + 1, // Opcode: VFP_VMAXNMD + /* 2051 */ MCD_OPC_FilterValue, + 1, + 156, + 4, + 0, // Skip to: 3236 + /* 2056 */ MCD_OPC_CheckPredicate, + 86, + 151, + 4, + 0, // Skip to: 3236 + /* 2061 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 143, + 4, + 0, // Skip to: 3236 + /* 2069 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 136, + 4, + 0, // Skip to: 3236 + /* 2076 */ MCD_OPC_Decode, + 213, + 18, + 200, + 1, // Opcode: VFP_VMINNMD + /* 2081 */ MCD_OPC_FilterValue, + 1, + 32, + 0, + 0, // Skip to: 2118 + /* 2086 */ MCD_OPC_CheckPredicate, + 86, + 121, + 4, + 0, // Skip to: 3236 + /* 2091 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 113, + 4, + 0, // Skip to: 3236 + /* 2099 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 106, + 4, + 0, // Skip to: 3236 + /* 2106 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 99, + 4, + 0, // Skip to: 3236 + /* 2113 */ MCD_OPC_Decode, + 209, + 26, + 200, + 1, // Opcode: VSELVSD + /* 2118 */ MCD_OPC_FilterValue, + 2, + 32, + 0, + 0, // Skip to: 2155 + /* 2123 */ MCD_OPC_CheckPredicate, + 86, + 84, + 4, + 0, // Skip to: 3236 + /* 2128 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 76, + 4, + 0, // Skip to: 3236 + /* 2136 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 69, + 4, + 0, // Skip to: 3236 + /* 2143 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 62, + 4, + 0, // Skip to: 3236 + /* 2150 */ MCD_OPC_Decode, + 203, + 26, + 200, + 1, // Opcode: VSELGED + /* 2155 */ MCD_OPC_FilterValue, + 3, + 52, + 4, + 0, // Skip to: 3236 + /* 2160 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2163 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2193 + /* 2168 */ MCD_OPC_CheckPredicate, + 86, + 39, + 4, + 0, // Skip to: 3236 + /* 2173 */ MCD_OPC_CheckField, + 23, + 9, + 252, + 3, + 31, + 4, + 0, // Skip to: 3236 + /* 2181 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 24, + 4, + 0, // Skip to: 3236 + /* 2188 */ MCD_OPC_Decode, + 206, + 26, + 200, + 1, // Opcode: VSELGTD + /* 2193 */ MCD_OPC_FilterValue, + 1, + 14, + 4, + 0, // Skip to: 3236 + /* 2198 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 2201 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 2238 + /* 2206 */ MCD_OPC_CheckPredicate, + 86, + 1, + 4, + 0, // Skip to: 3236 + /* 2211 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 249, + 3, + 0, // Skip to: 3236 + /* 2219 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 242, + 3, + 0, // Skip to: 3236 + /* 2226 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 235, + 3, + 0, // Skip to: 3236 + /* 2233 */ MCD_OPC_Decode, + 213, + 25, + 229, + 1, // Opcode: VRINTAD + /* 2238 */ MCD_OPC_FilterValue, + 9, + 32, + 0, + 0, // Skip to: 2275 + /* 2243 */ MCD_OPC_CheckPredicate, + 86, + 220, + 3, + 0, // Skip to: 3236 + /* 2248 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 212, + 3, + 0, // Skip to: 3236 + /* 2256 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 205, + 3, + 0, // Skip to: 3236 + /* 2263 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 198, + 3, + 0, // Skip to: 3236 + /* 2270 */ MCD_OPC_Decode, + 227, + 25, + 229, + 1, // Opcode: VRINTND + /* 2275 */ MCD_OPC_FilterValue, + 10, + 32, + 0, + 0, // Skip to: 2312 + /* 2280 */ MCD_OPC_CheckPredicate, + 86, + 183, + 3, + 0, // Skip to: 3236 + /* 2285 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 175, + 3, + 0, // Skip to: 3236 + /* 2293 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 168, + 3, + 0, // Skip to: 3236 + /* 2300 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 161, + 3, + 0, // Skip to: 3236 + /* 2307 */ MCD_OPC_Decode, + 234, + 25, + 229, + 1, // Opcode: VRINTPD + /* 2312 */ MCD_OPC_FilterValue, + 11, + 32, + 0, + 0, // Skip to: 2349 + /* 2317 */ MCD_OPC_CheckPredicate, + 86, + 146, + 3, + 0, // Skip to: 3236 + /* 2322 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 138, + 3, + 0, // Skip to: 3236 + /* 2330 */ MCD_OPC_CheckField, + 7, + 1, + 0, + 131, + 3, + 0, // Skip to: 3236 + /* 2337 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 124, + 3, + 0, // Skip to: 3236 + /* 2344 */ MCD_OPC_Decode, + 220, + 25, + 229, + 1, // Opcode: VRINTMD + /* 2349 */ MCD_OPC_FilterValue, + 12, + 63, + 0, + 0, // Skip to: 2417 + /* 2354 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2357 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2387 + /* 2362 */ MCD_OPC_CheckPredicate, + 86, + 101, + 3, + 0, // Skip to: 3236 + /* 2367 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 93, + 3, + 0, // Skip to: 3236 + /* 2375 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 86, + 3, + 0, // Skip to: 3236 + /* 2382 */ MCD_OPC_Decode, + 197, + 17, + 137, + 4, // Opcode: VCVTAUD + /* 2387 */ MCD_OPC_FilterValue, + 1, + 76, + 3, + 0, // Skip to: 3236 + /* 2392 */ MCD_OPC_CheckPredicate, + 86, + 71, + 3, + 0, // Skip to: 3236 + /* 2397 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 63, + 3, + 0, // Skip to: 3236 + /* 2405 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 56, + 3, + 0, // Skip to: 3236 + /* 2412 */ MCD_OPC_Decode, + 194, + 17, + 137, + 4, // Opcode: VCVTASD + /* 2417 */ MCD_OPC_FilterValue, + 13, + 63, + 0, + 0, // Skip to: 2485 + /* 2422 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2425 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2455 + /* 2430 */ MCD_OPC_CheckPredicate, + 86, + 33, + 3, + 0, // Skip to: 3236 + /* 2435 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 25, + 3, + 0, // Skip to: 3236 + /* 2443 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 18, + 3, + 0, // Skip to: 3236 + /* 2450 */ MCD_OPC_Decode, + 230, + 17, + 137, + 4, // Opcode: VCVTNUD + /* 2455 */ MCD_OPC_FilterValue, + 1, + 8, + 3, + 0, // Skip to: 3236 + /* 2460 */ MCD_OPC_CheckPredicate, + 86, + 3, + 3, + 0, // Skip to: 3236 + /* 2465 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 251, + 2, + 0, // Skip to: 3236 + /* 2473 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 244, + 2, + 0, // Skip to: 3236 + /* 2480 */ MCD_OPC_Decode, + 227, + 17, + 137, + 4, // Opcode: VCVTNSD + /* 2485 */ MCD_OPC_FilterValue, + 14, + 63, + 0, + 0, // Skip to: 2553 + /* 2490 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2493 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2523 + /* 2498 */ MCD_OPC_CheckPredicate, + 86, + 221, + 2, + 0, // Skip to: 3236 + /* 2503 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 213, + 2, + 0, // Skip to: 3236 + /* 2511 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 206, + 2, + 0, // Skip to: 3236 + /* 2518 */ MCD_OPC_Decode, + 244, + 17, + 137, + 4, // Opcode: VCVTPUD + /* 2523 */ MCD_OPC_FilterValue, + 1, + 196, + 2, + 0, // Skip to: 3236 + /* 2528 */ MCD_OPC_CheckPredicate, + 86, + 191, + 2, + 0, // Skip to: 3236 + /* 2533 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 183, + 2, + 0, // Skip to: 3236 + /* 2541 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 176, + 2, + 0, // Skip to: 3236 + /* 2548 */ MCD_OPC_Decode, + 241, + 17, + 137, + 4, // Opcode: VCVTPSD + /* 2553 */ MCD_OPC_FilterValue, + 15, + 166, + 2, + 0, // Skip to: 3236 + /* 2558 */ MCD_OPC_ExtractField, + 7, + 1, // Inst{7} ... + /* 2561 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2591 + /* 2566 */ MCD_OPC_CheckPredicate, + 86, + 153, + 2, + 0, // Skip to: 3236 + /* 2571 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 145, + 2, + 0, // Skip to: 3236 + /* 2579 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 138, + 2, + 0, // Skip to: 3236 + /* 2586 */ MCD_OPC_Decode, + 216, + 17, + 137, + 4, // Opcode: VCVTMUD + /* 2591 */ MCD_OPC_FilterValue, + 1, + 128, + 2, + 0, // Skip to: 3236 + /* 2596 */ MCD_OPC_CheckPredicate, + 86, + 123, + 2, + 0, // Skip to: 3236 + /* 2601 */ MCD_OPC_CheckField, + 23, + 9, + 253, + 3, + 115, + 2, + 0, // Skip to: 3236 + /* 2609 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 108, + 2, + 0, // Skip to: 3236 + /* 2616 */ MCD_OPC_Decode, + 213, + 17, + 137, + 4, // Opcode: VCVTMSD + /* 2621 */ MCD_OPC_FilterValue, + 12, + 132, + 0, + 0, // Skip to: 2758 + /* 2626 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2629 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 2721 + /* 2634 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2637 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2667 + /* 2642 */ MCD_OPC_CheckPredicate, + 31, + 77, + 2, + 0, // Skip to: 3236 + /* 2647 */ MCD_OPC_CheckField, + 23, + 9, + 248, + 3, + 69, + 2, + 0, // Skip to: 3236 + /* 2655 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 62, + 2, + 0, // Skip to: 3236 + /* 2662 */ MCD_OPC_Decode, + 219, + 22, + 209, + 1, // Opcode: VMMLA + /* 2667 */ MCD_OPC_FilterValue, + 2, + 52, + 2, + 0, // Skip to: 3236 + /* 2672 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2675 */ MCD_OPC_FilterValue, + 248, + 3, + 17, + 0, + 0, // Skip to: 2698 + /* 2681 */ MCD_OPC_CheckPredicate, + 92, + 38, + 2, + 0, // Skip to: 3236 + /* 2686 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 31, + 2, + 0, // Skip to: 3236 + /* 2693 */ MCD_OPC_Decode, + 156, + 27, + 209, + 1, // Opcode: VSMMLA + /* 2698 */ MCD_OPC_FilterValue, + 249, + 3, + 20, + 2, + 0, // Skip to: 3236 + /* 2704 */ MCD_OPC_CheckPredicate, + 92, + 15, + 2, + 0, // Skip to: 3236 + /* 2709 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 8, + 2, + 0, // Skip to: 3236 + /* 2716 */ MCD_OPC_Decode, + 186, + 30, + 209, + 1, // Opcode: VUSMMLA + /* 2721 */ MCD_OPC_FilterValue, + 1, + 254, + 1, + 0, // Skip to: 3236 + /* 2726 */ MCD_OPC_CheckPredicate, + 92, + 249, + 1, + 0, // Skip to: 3236 + /* 2731 */ MCD_OPC_CheckField, + 23, + 9, + 248, + 3, + 241, + 1, + 0, // Skip to: 3236 + /* 2739 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 234, + 1, + 0, // Skip to: 3236 + /* 2746 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 227, + 1, + 0, // Skip to: 3236 + /* 2753 */ MCD_OPC_Decode, + 181, + 30, + 209, + 1, // Opcode: VUMMLA + /* 2758 */ MCD_OPC_FilterValue, + 13, + 217, + 1, + 0, // Skip to: 3236 + /* 2763 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 2766 */ MCD_OPC_FilterValue, + 248, + 3, + 139, + 0, + 0, // Skip to: 2911 + /* 2772 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2775 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 2859 + /* 2780 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2783 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 2821 + /* 2788 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2791 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2806 + /* 2796 */ MCD_OPC_CheckPredicate, + 31, + 179, + 1, + 0, // Skip to: 3236 + /* 2801 */ MCD_OPC_Decode, + 194, + 5, + 208, + 1, // Opcode: BF16VDOTS_VDOTD + /* 2806 */ MCD_OPC_FilterValue, + 2, + 169, + 1, + 0, // Skip to: 3236 + /* 2811 */ MCD_OPC_CheckPredicate, + 93, + 164, + 1, + 0, // Skip to: 3236 + /* 2816 */ MCD_OPC_Decode, + 196, + 26, + 208, + 1, // Opcode: VSDOTD + /* 2821 */ MCD_OPC_FilterValue, + 1, + 154, + 1, + 0, // Skip to: 3236 + /* 2826 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 2829 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2844 + /* 2834 */ MCD_OPC_CheckPredicate, + 31, + 141, + 1, + 0, // Skip to: 3236 + /* 2839 */ MCD_OPC_Decode, + 195, + 5, + 209, + 1, // Opcode: BF16VDOTS_VDOTQ + /* 2844 */ MCD_OPC_FilterValue, + 2, + 131, + 1, + 0, // Skip to: 3236 + /* 2849 */ MCD_OPC_CheckPredicate, + 93, + 126, + 1, + 0, // Skip to: 3236 + /* 2854 */ MCD_OPC_Decode, + 198, + 26, + 209, + 1, // Opcode: VSDOTQ + /* 2859 */ MCD_OPC_FilterValue, + 1, + 116, + 1, + 0, // Skip to: 3236 + /* 2864 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2867 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2889 + /* 2872 */ MCD_OPC_CheckPredicate, + 93, + 103, + 1, + 0, // Skip to: 3236 + /* 2877 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 96, + 1, + 0, // Skip to: 3236 + /* 2884 */ MCD_OPC_Decode, + 168, + 30, + 208, + 1, // Opcode: VUDOTD + /* 2889 */ MCD_OPC_FilterValue, + 1, + 86, + 1, + 0, // Skip to: 3236 + /* 2894 */ MCD_OPC_CheckPredicate, + 93, + 81, + 1, + 0, // Skip to: 3236 + /* 2899 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 74, + 1, + 0, // Skip to: 3236 + /* 2906 */ MCD_OPC_Decode, + 170, + 30, + 209, + 1, // Opcode: VUDOTQ + /* 2911 */ MCD_OPC_FilterValue, + 249, + 3, + 61, + 0, + 0, // Skip to: 2978 + /* 2917 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2920 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 2949 + /* 2925 */ MCD_OPC_CheckPredicate, + 92, + 50, + 1, + 0, // Skip to: 3236 + /* 2930 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 43, + 1, + 0, // Skip to: 3236 + /* 2937 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 36, + 1, + 0, // Skip to: 3236 + /* 2944 */ MCD_OPC_Decode, + 182, + 30, + 208, + 1, // Opcode: VUSDOTD + /* 2949 */ MCD_OPC_FilterValue, + 1, + 26, + 1, + 0, // Skip to: 3236 + /* 2954 */ MCD_OPC_CheckPredicate, + 92, + 21, + 1, + 0, // Skip to: 3236 + /* 2959 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 14, + 1, + 0, // Skip to: 3236 + /* 2966 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 7, + 1, + 0, // Skip to: 3236 + /* 2973 */ MCD_OPC_Decode, + 184, + 30, + 209, + 1, // Opcode: VUSDOTQ + /* 2978 */ MCD_OPC_FilterValue, + 252, + 3, + 139, + 0, + 0, // Skip to: 3123 + /* 2984 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 2987 */ MCD_OPC_FilterValue, + 0, + 79, + 0, + 0, // Skip to: 3071 + /* 2992 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2995 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 3033 + /* 3000 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3003 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3018 + /* 3008 */ MCD_OPC_CheckPredicate, + 31, + 223, + 0, + 0, // Skip to: 3236 + /* 3013 */ MCD_OPC_Decode, + 192, + 5, + 216, + 1, // Opcode: BF16VDOTI_VDOTD + /* 3018 */ MCD_OPC_FilterValue, + 2, + 213, + 0, + 0, // Skip to: 3236 + /* 3023 */ MCD_OPC_CheckPredicate, + 93, + 208, + 0, + 0, // Skip to: 3236 + /* 3028 */ MCD_OPC_Decode, + 197, + 26, + 216, + 1, // Opcode: VSDOTDI + /* 3033 */ MCD_OPC_FilterValue, + 1, + 198, + 0, + 0, // Skip to: 3236 + /* 3038 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3041 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3056 + /* 3046 */ MCD_OPC_CheckPredicate, + 31, + 185, + 0, + 0, // Skip to: 3236 + /* 3051 */ MCD_OPC_Decode, + 193, + 5, + 217, + 1, // Opcode: BF16VDOTI_VDOTQ + /* 3056 */ MCD_OPC_FilterValue, + 2, + 175, + 0, + 0, // Skip to: 3236 + /* 3061 */ MCD_OPC_CheckPredicate, + 93, + 170, + 0, + 0, // Skip to: 3236 + /* 3066 */ MCD_OPC_Decode, + 199, + 26, + 217, + 1, // Opcode: VSDOTQI + /* 3071 */ MCD_OPC_FilterValue, + 1, + 160, + 0, + 0, // Skip to: 3236 + /* 3076 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3079 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3101 + /* 3084 */ MCD_OPC_CheckPredicate, + 93, + 147, + 0, + 0, // Skip to: 3236 + /* 3089 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 140, + 0, + 0, // Skip to: 3236 + /* 3096 */ MCD_OPC_Decode, + 169, + 30, + 216, + 1, // Opcode: VUDOTDI + /* 3101 */ MCD_OPC_FilterValue, + 1, + 130, + 0, + 0, // Skip to: 3236 + /* 3106 */ MCD_OPC_CheckPredicate, + 93, + 125, + 0, + 0, // Skip to: 3236 + /* 3111 */ MCD_OPC_CheckField, + 20, + 2, + 2, + 118, + 0, + 0, // Skip to: 3236 + /* 3118 */ MCD_OPC_Decode, + 171, + 30, + 217, + 1, // Opcode: VUDOTQI + /* 3123 */ MCD_OPC_FilterValue, + 253, + 3, + 107, + 0, + 0, // Skip to: 3236 + /* 3129 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 3132 */ MCD_OPC_FilterValue, + 0, + 47, + 0, + 0, // Skip to: 3184 + /* 3137 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3140 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3162 + /* 3145 */ MCD_OPC_CheckPredicate, + 92, + 86, + 0, + 0, // Skip to: 3236 + /* 3150 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 79, + 0, + 0, // Skip to: 3236 + /* 3157 */ MCD_OPC_Decode, + 183, + 30, + 216, + 1, // Opcode: VUSDOTDI + /* 3162 */ MCD_OPC_FilterValue, + 1, + 69, + 0, + 0, // Skip to: 3236 + /* 3167 */ MCD_OPC_CheckPredicate, + 92, + 64, + 0, + 0, // Skip to: 3236 + /* 3172 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 57, + 0, + 0, // Skip to: 3236 + /* 3179 */ MCD_OPC_Decode, + 185, + 30, + 217, + 1, // Opcode: VUSDOTQI + /* 3184 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 3236 + /* 3189 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 3192 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 3214 + /* 3197 */ MCD_OPC_CheckPredicate, + 92, + 34, + 0, + 0, // Skip to: 3236 + /* 3202 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 27, + 0, + 0, // Skip to: 3236 + /* 3209 */ MCD_OPC_Decode, + 244, + 29, + 216, + 1, // Opcode: VSUDOTDI + /* 3214 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 3236 + /* 3219 */ MCD_OPC_CheckPredicate, + 92, + 12, + 0, + 0, // Skip to: 3236 + /* 3224 */ MCD_OPC_CheckField, + 20, + 2, + 0, + 5, + 0, + 0, // Skip to: 3236 + /* 3231 */ MCD_OPC_Decode, + 245, + 29, + 217, + 1, // Opcode: VSUDOTQI + /* 3236 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTablev8Crypto32[] = { -/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 3 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 83 -/* 8 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 11 */ MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 47 -/* 17 */ MCD_OPC_CheckPredicate, 24, 12, 2, 0, // Skip to: 546 -/* 22 */ MCD_OPC_CheckField, 8, 4, 12, 5, 2, 0, // Skip to: 546 -/* 29 */ MCD_OPC_CheckField, 6, 1, 1, 254, 1, 0, // Skip to: 546 -/* 36 */ MCD_OPC_CheckField, 4, 1, 0, 247, 1, 0, // Skip to: 546 -/* 43 */ MCD_OPC_Decode, 247, 5, 106, // Opcode: SHA1C -/* 47 */ MCD_OPC_FilterValue, 230, 3, 237, 1, 0, // Skip to: 546 -/* 53 */ MCD_OPC_CheckPredicate, 24, 232, 1, 0, // Skip to: 546 -/* 58 */ MCD_OPC_CheckField, 8, 4, 12, 225, 1, 0, // Skip to: 546 -/* 65 */ MCD_OPC_CheckField, 6, 1, 1, 218, 1, 0, // Skip to: 546 -/* 72 */ MCD_OPC_CheckField, 4, 1, 0, 211, 1, 0, // Skip to: 546 -/* 79 */ MCD_OPC_Decode, 253, 5, 106, // Opcode: SHA256H -/* 83 */ MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 163 -/* 88 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 91 */ MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 127 -/* 97 */ MCD_OPC_CheckPredicate, 24, 188, 1, 0, // Skip to: 546 -/* 102 */ MCD_OPC_CheckField, 8, 4, 12, 181, 1, 0, // Skip to: 546 -/* 109 */ MCD_OPC_CheckField, 6, 1, 1, 174, 1, 0, // Skip to: 546 -/* 116 */ MCD_OPC_CheckField, 4, 1, 0, 167, 1, 0, // Skip to: 546 -/* 123 */ MCD_OPC_Decode, 250, 5, 106, // Opcode: SHA1P -/* 127 */ MCD_OPC_FilterValue, 230, 3, 157, 1, 0, // Skip to: 546 -/* 133 */ MCD_OPC_CheckPredicate, 24, 152, 1, 0, // Skip to: 546 -/* 138 */ MCD_OPC_CheckField, 8, 4, 12, 145, 1, 0, // Skip to: 546 -/* 145 */ MCD_OPC_CheckField, 6, 1, 1, 138, 1, 0, // Skip to: 546 -/* 152 */ MCD_OPC_CheckField, 4, 1, 0, 131, 1, 0, // Skip to: 546 -/* 159 */ MCD_OPC_Decode, 254, 5, 106, // Opcode: SHA256H2 -/* 163 */ MCD_OPC_FilterValue, 2, 75, 0, 0, // Skip to: 243 -/* 168 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... -/* 171 */ MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 207 -/* 177 */ MCD_OPC_CheckPredicate, 24, 108, 1, 0, // Skip to: 546 -/* 182 */ MCD_OPC_CheckField, 8, 4, 12, 101, 1, 0, // Skip to: 546 -/* 189 */ MCD_OPC_CheckField, 6, 1, 1, 94, 1, 0, // Skip to: 546 -/* 196 */ MCD_OPC_CheckField, 4, 1, 0, 87, 1, 0, // Skip to: 546 -/* 203 */ MCD_OPC_Decode, 249, 5, 106, // Opcode: SHA1M -/* 207 */ MCD_OPC_FilterValue, 230, 3, 77, 1, 0, // Skip to: 546 -/* 213 */ MCD_OPC_CheckPredicate, 24, 72, 1, 0, // Skip to: 546 -/* 218 */ MCD_OPC_CheckField, 8, 4, 12, 65, 1, 0, // Skip to: 546 -/* 225 */ MCD_OPC_CheckField, 6, 1, 1, 58, 1, 0, // Skip to: 546 -/* 232 */ MCD_OPC_CheckField, 4, 1, 0, 51, 1, 0, // Skip to: 546 -/* 239 */ MCD_OPC_Decode, 128, 6, 106, // Opcode: SHA256SU1 -/* 243 */ MCD_OPC_FilterValue, 3, 42, 1, 0, // Skip to: 546 -/* 248 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 251 */ MCD_OPC_FilterValue, 2, 38, 0, 0, // Skip to: 294 -/* 256 */ MCD_OPC_CheckPredicate, 24, 29, 1, 0, // Skip to: 546 -/* 261 */ MCD_OPC_CheckField, 23, 9, 231, 3, 21, 1, 0, // Skip to: 546 -/* 269 */ MCD_OPC_CheckField, 16, 4, 9, 14, 1, 0, // Skip to: 546 -/* 276 */ MCD_OPC_CheckField, 6, 2, 3, 7, 1, 0, // Skip to: 546 -/* 283 */ MCD_OPC_CheckField, 4, 1, 0, 0, 1, 0, // Skip to: 546 -/* 290 */ MCD_OPC_Decode, 248, 5, 127, // Opcode: SHA1H -/* 294 */ MCD_OPC_FilterValue, 3, 211, 0, 0, // Skip to: 510 -/* 299 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 302 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 339 -/* 307 */ MCD_OPC_CheckPredicate, 24, 234, 0, 0, // Skip to: 546 -/* 312 */ MCD_OPC_CheckField, 23, 9, 231, 3, 226, 0, 0, // Skip to: 546 -/* 320 */ MCD_OPC_CheckField, 16, 4, 0, 219, 0, 0, // Skip to: 546 -/* 327 */ MCD_OPC_CheckField, 4, 1, 0, 212, 0, 0, // Skip to: 546 -/* 334 */ MCD_OPC_Decode, 155, 4, 133, 1, // Opcode: AESE -/* 339 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 376 -/* 344 */ MCD_OPC_CheckPredicate, 24, 197, 0, 0, // Skip to: 546 -/* 349 */ MCD_OPC_CheckField, 23, 9, 231, 3, 189, 0, 0, // Skip to: 546 -/* 357 */ MCD_OPC_CheckField, 16, 4, 0, 182, 0, 0, // Skip to: 546 -/* 364 */ MCD_OPC_CheckField, 4, 1, 0, 175, 0, 0, // Skip to: 546 -/* 371 */ MCD_OPC_Decode, 154, 4, 133, 1, // Opcode: AESD -/* 376 */ MCD_OPC_FilterValue, 2, 62, 0, 0, // Skip to: 443 -/* 381 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 384 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 413 -/* 389 */ MCD_OPC_CheckPredicate, 24, 152, 0, 0, // Skip to: 546 -/* 394 */ MCD_OPC_CheckField, 23, 9, 231, 3, 144, 0, 0, // Skip to: 546 -/* 402 */ MCD_OPC_CheckField, 4, 1, 0, 137, 0, 0, // Skip to: 546 -/* 409 */ MCD_OPC_Decode, 157, 4, 127, // Opcode: AESMC -/* 413 */ MCD_OPC_FilterValue, 10, 128, 0, 0, // Skip to: 546 -/* 418 */ MCD_OPC_CheckPredicate, 24, 123, 0, 0, // Skip to: 546 -/* 423 */ MCD_OPC_CheckField, 23, 9, 231, 3, 115, 0, 0, // Skip to: 546 -/* 431 */ MCD_OPC_CheckField, 4, 1, 0, 108, 0, 0, // Skip to: 546 -/* 438 */ MCD_OPC_Decode, 252, 5, 133, 1, // Opcode: SHA1SU1 -/* 443 */ MCD_OPC_FilterValue, 3, 98, 0, 0, // Skip to: 546 -/* 448 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 451 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 480 -/* 456 */ MCD_OPC_CheckPredicate, 24, 85, 0, 0, // Skip to: 546 -/* 461 */ MCD_OPC_CheckField, 23, 9, 231, 3, 77, 0, 0, // Skip to: 546 -/* 469 */ MCD_OPC_CheckField, 4, 1, 0, 70, 0, 0, // Skip to: 546 -/* 476 */ MCD_OPC_Decode, 156, 4, 127, // Opcode: AESIMC -/* 480 */ MCD_OPC_FilterValue, 10, 61, 0, 0, // Skip to: 546 -/* 485 */ MCD_OPC_CheckPredicate, 24, 56, 0, 0, // Skip to: 546 -/* 490 */ MCD_OPC_CheckField, 23, 9, 231, 3, 48, 0, 0, // Skip to: 546 -/* 498 */ MCD_OPC_CheckField, 4, 1, 0, 41, 0, 0, // Skip to: 546 -/* 505 */ MCD_OPC_Decode, 255, 5, 133, 1, // Opcode: SHA256SU0 -/* 510 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 546 -/* 515 */ MCD_OPC_CheckPredicate, 24, 26, 0, 0, // Skip to: 546 -/* 520 */ MCD_OPC_CheckField, 23, 9, 228, 3, 18, 0, 0, // Skip to: 546 -/* 528 */ MCD_OPC_CheckField, 6, 1, 1, 11, 0, 0, // Skip to: 546 -/* 535 */ MCD_OPC_CheckField, 4, 1, 0, 4, 0, 0, // Skip to: 546 -/* 542 */ MCD_OPC_Decode, 251, 5, 106, // Opcode: SHA1SU0 -/* 546 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 77, + 0, + 0, // Skip to: 85 + /* 8 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 11 */ MCD_OPC_FilterValue, + 228, + 3, + 31, + 0, + 0, // Skip to: 48 + /* 17 */ MCD_OPC_CheckPredicate, + 94, + 22, + 2, + 0, // Skip to: 556 + /* 22 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 15, + 2, + 0, // Skip to: 556 + /* 29 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 8, + 2, + 0, // Skip to: 556 + /* 36 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 1, + 2, + 0, // Skip to: 556 + /* 43 */ MCD_OPC_Decode, + 146, + 14, + 209, + 1, // Opcode: SHA1C + /* 48 */ MCD_OPC_FilterValue, + 230, + 3, + 246, + 1, + 0, // Skip to: 556 + /* 54 */ MCD_OPC_CheckPredicate, + 94, + 241, + 1, + 0, // Skip to: 556 + /* 59 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 234, + 1, + 0, // Skip to: 556 + /* 66 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 227, + 1, + 0, // Skip to: 556 + /* 73 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 220, + 1, + 0, // Skip to: 556 + /* 80 */ MCD_OPC_Decode, + 152, + 14, + 209, + 1, // Opcode: SHA256H + /* 85 */ MCD_OPC_FilterValue, + 1, + 77, + 0, + 0, // Skip to: 167 + /* 90 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 93 */ MCD_OPC_FilterValue, + 228, + 3, + 31, + 0, + 0, // Skip to: 130 + /* 99 */ MCD_OPC_CheckPredicate, + 94, + 196, + 1, + 0, // Skip to: 556 + /* 104 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 189, + 1, + 0, // Skip to: 556 + /* 111 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 182, + 1, + 0, // Skip to: 556 + /* 118 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 175, + 1, + 0, // Skip to: 556 + /* 125 */ MCD_OPC_Decode, + 149, + 14, + 209, + 1, // Opcode: SHA1P + /* 130 */ MCD_OPC_FilterValue, + 230, + 3, + 164, + 1, + 0, // Skip to: 556 + /* 136 */ MCD_OPC_CheckPredicate, + 94, + 159, + 1, + 0, // Skip to: 556 + /* 141 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 152, + 1, + 0, // Skip to: 556 + /* 148 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 145, + 1, + 0, // Skip to: 556 + /* 155 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 138, + 1, + 0, // Skip to: 556 + /* 162 */ MCD_OPC_Decode, + 153, + 14, + 209, + 1, // Opcode: SHA256H2 + /* 167 */ MCD_OPC_FilterValue, + 2, + 77, + 0, + 0, // Skip to: 249 + /* 172 */ MCD_OPC_ExtractField, + 23, + 9, // Inst{31-23} ... + /* 175 */ MCD_OPC_FilterValue, + 228, + 3, + 31, + 0, + 0, // Skip to: 212 + /* 181 */ MCD_OPC_CheckPredicate, + 94, + 114, + 1, + 0, // Skip to: 556 + /* 186 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 107, + 1, + 0, // Skip to: 556 + /* 193 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 100, + 1, + 0, // Skip to: 556 + /* 200 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 93, + 1, + 0, // Skip to: 556 + /* 207 */ MCD_OPC_Decode, + 148, + 14, + 209, + 1, // Opcode: SHA1M + /* 212 */ MCD_OPC_FilterValue, + 230, + 3, + 82, + 1, + 0, // Skip to: 556 + /* 218 */ MCD_OPC_CheckPredicate, + 94, + 77, + 1, + 0, // Skip to: 556 + /* 223 */ MCD_OPC_CheckField, + 8, + 4, + 12, + 70, + 1, + 0, // Skip to: 556 + /* 230 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 63, + 1, + 0, // Skip to: 556 + /* 237 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 56, + 1, + 0, // Skip to: 556 + /* 244 */ MCD_OPC_Decode, + 155, + 14, + 209, + 1, // Opcode: SHA256SU1 + /* 249 */ MCD_OPC_FilterValue, + 3, + 46, + 1, + 0, // Skip to: 556 + /* 254 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 257 */ MCD_OPC_FilterValue, + 2, + 39, + 0, + 0, // Skip to: 301 + /* 262 */ MCD_OPC_CheckPredicate, + 94, + 33, + 1, + 0, // Skip to: 556 + /* 267 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 25, + 1, + 0, // Skip to: 556 + /* 275 */ MCD_OPC_CheckField, + 16, + 4, + 9, + 18, + 1, + 0, // Skip to: 556 + /* 282 */ MCD_OPC_CheckField, + 6, + 2, + 3, + 11, + 1, + 0, // Skip to: 556 + /* 289 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 4, + 1, + 0, // Skip to: 556 + /* 296 */ MCD_OPC_Decode, + 147, + 14, + 230, + 1, // Opcode: SHA1H + /* 301 */ MCD_OPC_FilterValue, + 3, + 213, + 0, + 0, // Skip to: 519 + /* 306 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 309 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 346 + /* 314 */ MCD_OPC_CheckPredicate, + 29, + 237, + 0, + 0, // Skip to: 556 + /* 319 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 229, + 0, + 0, // Skip to: 556 + /* 327 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 222, + 0, + 0, // Skip to: 556 + /* 334 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 215, + 0, + 0, // Skip to: 556 + /* 341 */ MCD_OPC_Decode, + 185, + 5, + 236, + 1, // Opcode: AESE + /* 346 */ MCD_OPC_FilterValue, + 1, + 32, + 0, + 0, // Skip to: 383 + /* 351 */ MCD_OPC_CheckPredicate, + 29, + 200, + 0, + 0, // Skip to: 556 + /* 356 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 192, + 0, + 0, // Skip to: 556 + /* 364 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 185, + 0, + 0, // Skip to: 556 + /* 371 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 178, + 0, + 0, // Skip to: 556 + /* 378 */ MCD_OPC_Decode, + 184, + 5, + 236, + 1, // Opcode: AESD + /* 383 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 451 + /* 388 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 391 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 421 + /* 396 */ MCD_OPC_CheckPredicate, + 29, + 155, + 0, + 0, // Skip to: 556 + /* 401 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 147, + 0, + 0, // Skip to: 556 + /* 409 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 140, + 0, + 0, // Skip to: 556 + /* 416 */ MCD_OPC_Decode, + 187, + 5, + 230, + 1, // Opcode: AESMC + /* 421 */ MCD_OPC_FilterValue, + 10, + 130, + 0, + 0, // Skip to: 556 + /* 426 */ MCD_OPC_CheckPredicate, + 94, + 125, + 0, + 0, // Skip to: 556 + /* 431 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 117, + 0, + 0, // Skip to: 556 + /* 439 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 110, + 0, + 0, // Skip to: 556 + /* 446 */ MCD_OPC_Decode, + 151, + 14, + 236, + 1, // Opcode: SHA1SU1 + /* 451 */ MCD_OPC_FilterValue, + 3, + 100, + 0, + 0, // Skip to: 556 + /* 456 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 459 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 489 + /* 464 */ MCD_OPC_CheckPredicate, + 29, + 87, + 0, + 0, // Skip to: 556 + /* 469 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 79, + 0, + 0, // Skip to: 556 + /* 477 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 72, + 0, + 0, // Skip to: 556 + /* 484 */ MCD_OPC_Decode, + 186, + 5, + 230, + 1, // Opcode: AESIMC + /* 489 */ MCD_OPC_FilterValue, + 10, + 62, + 0, + 0, // Skip to: 556 + /* 494 */ MCD_OPC_CheckPredicate, + 94, + 57, + 0, + 0, // Skip to: 556 + /* 499 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 49, + 0, + 0, // Skip to: 556 + /* 507 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 42, + 0, + 0, // Skip to: 556 + /* 514 */ MCD_OPC_Decode, + 154, + 14, + 236, + 1, // Opcode: SHA256SU0 + /* 519 */ MCD_OPC_FilterValue, + 12, + 32, + 0, + 0, // Skip to: 556 + /* 524 */ MCD_OPC_CheckPredicate, + 94, + 27, + 0, + 0, // Skip to: 556 + /* 529 */ MCD_OPC_CheckField, + 23, + 9, + 228, + 3, + 19, + 0, + 0, // Skip to: 556 + /* 537 */ MCD_OPC_CheckField, + 6, + 1, + 1, + 12, + 0, + 0, // Skip to: 556 + /* 544 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 5, + 0, + 0, // Skip to: 556 + /* 551 */ MCD_OPC_Decode, + 150, + 14, + 209, + 1, // Opcode: SHA1SU0 + /* 556 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTablev8NEON32[] = { -/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 3 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 275 -/* 8 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 11 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 77 -/* 16 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 19 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 48 -/* 24 */ MCD_OPC_CheckPredicate, 74, 110, 8, 0, // Skip to: 2187 -/* 29 */ MCD_OPC_CheckField, 23, 9, 231, 3, 102, 8, 0, // Skip to: 2187 -/* 37 */ MCD_OPC_CheckField, 4, 1, 0, 95, 8, 0, // Skip to: 2187 -/* 44 */ MCD_OPC_Decode, 154, 9, 126, // Opcode: VCVTANSDh -/* 48 */ MCD_OPC_FilterValue, 59, 86, 8, 0, // Skip to: 2187 -/* 53 */ MCD_OPC_CheckPredicate, 75, 81, 8, 0, // Skip to: 2187 -/* 58 */ MCD_OPC_CheckField, 23, 9, 231, 3, 73, 8, 0, // Skip to: 2187 -/* 66 */ MCD_OPC_CheckField, 4, 1, 0, 66, 8, 0, // Skip to: 2187 -/* 73 */ MCD_OPC_Decode, 153, 9, 126, // Opcode: VCVTANSDf -/* 77 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 143 -/* 82 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 85 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 114 -/* 90 */ MCD_OPC_CheckPredicate, 74, 44, 8, 0, // Skip to: 2187 -/* 95 */ MCD_OPC_CheckField, 23, 9, 231, 3, 36, 8, 0, // Skip to: 2187 -/* 103 */ MCD_OPC_CheckField, 4, 1, 0, 29, 8, 0, // Skip to: 2187 -/* 110 */ MCD_OPC_Decode, 156, 9, 127, // Opcode: VCVTANSQh -/* 114 */ MCD_OPC_FilterValue, 59, 20, 8, 0, // Skip to: 2187 -/* 119 */ MCD_OPC_CheckPredicate, 75, 15, 8, 0, // Skip to: 2187 -/* 124 */ MCD_OPC_CheckField, 23, 9, 231, 3, 7, 8, 0, // Skip to: 2187 -/* 132 */ MCD_OPC_CheckField, 4, 1, 0, 0, 8, 0, // Skip to: 2187 -/* 139 */ MCD_OPC_Decode, 155, 9, 127, // Opcode: VCVTANSQf -/* 143 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 209 -/* 148 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 151 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 180 -/* 156 */ MCD_OPC_CheckPredicate, 74, 234, 7, 0, // Skip to: 2187 -/* 161 */ MCD_OPC_CheckField, 23, 9, 231, 3, 226, 7, 0, // Skip to: 2187 -/* 169 */ MCD_OPC_CheckField, 4, 1, 0, 219, 7, 0, // Skip to: 2187 -/* 176 */ MCD_OPC_Decode, 158, 9, 126, // Opcode: VCVTANUDh -/* 180 */ MCD_OPC_FilterValue, 59, 210, 7, 0, // Skip to: 2187 -/* 185 */ MCD_OPC_CheckPredicate, 75, 205, 7, 0, // Skip to: 2187 -/* 190 */ MCD_OPC_CheckField, 23, 9, 231, 3, 197, 7, 0, // Skip to: 2187 -/* 198 */ MCD_OPC_CheckField, 4, 1, 0, 190, 7, 0, // Skip to: 2187 -/* 205 */ MCD_OPC_Decode, 157, 9, 126, // Opcode: VCVTANUDf -/* 209 */ MCD_OPC_FilterValue, 3, 181, 7, 0, // Skip to: 2187 -/* 214 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 217 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 246 -/* 222 */ MCD_OPC_CheckPredicate, 74, 168, 7, 0, // Skip to: 2187 -/* 227 */ MCD_OPC_CheckField, 23, 9, 231, 3, 160, 7, 0, // Skip to: 2187 -/* 235 */ MCD_OPC_CheckField, 4, 1, 0, 153, 7, 0, // Skip to: 2187 -/* 242 */ MCD_OPC_Decode, 160, 9, 127, // Opcode: VCVTANUQh -/* 246 */ MCD_OPC_FilterValue, 59, 144, 7, 0, // Skip to: 2187 -/* 251 */ MCD_OPC_CheckPredicate, 75, 139, 7, 0, // Skip to: 2187 -/* 256 */ MCD_OPC_CheckField, 23, 9, 231, 3, 131, 7, 0, // Skip to: 2187 -/* 264 */ MCD_OPC_CheckField, 4, 1, 0, 124, 7, 0, // Skip to: 2187 -/* 271 */ MCD_OPC_Decode, 159, 9, 127, // Opcode: VCVTANUQf -/* 275 */ MCD_OPC_FilterValue, 1, 11, 1, 0, // Skip to: 547 -/* 280 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 283 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 349 -/* 288 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 291 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 320 -/* 296 */ MCD_OPC_CheckPredicate, 74, 94, 7, 0, // Skip to: 2187 -/* 301 */ MCD_OPC_CheckField, 23, 9, 231, 3, 86, 7, 0, // Skip to: 2187 -/* 309 */ MCD_OPC_CheckField, 4, 1, 0, 79, 7, 0, // Skip to: 2187 -/* 316 */ MCD_OPC_Decode, 187, 9, 126, // Opcode: VCVTNNSDh -/* 320 */ MCD_OPC_FilterValue, 59, 70, 7, 0, // Skip to: 2187 -/* 325 */ MCD_OPC_CheckPredicate, 75, 65, 7, 0, // Skip to: 2187 -/* 330 */ MCD_OPC_CheckField, 23, 9, 231, 3, 57, 7, 0, // Skip to: 2187 -/* 338 */ MCD_OPC_CheckField, 4, 1, 0, 50, 7, 0, // Skip to: 2187 -/* 345 */ MCD_OPC_Decode, 186, 9, 126, // Opcode: VCVTNNSDf -/* 349 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 415 -/* 354 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 357 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 386 -/* 362 */ MCD_OPC_CheckPredicate, 74, 28, 7, 0, // Skip to: 2187 -/* 367 */ MCD_OPC_CheckField, 23, 9, 231, 3, 20, 7, 0, // Skip to: 2187 -/* 375 */ MCD_OPC_CheckField, 4, 1, 0, 13, 7, 0, // Skip to: 2187 -/* 382 */ MCD_OPC_Decode, 189, 9, 127, // Opcode: VCVTNNSQh -/* 386 */ MCD_OPC_FilterValue, 59, 4, 7, 0, // Skip to: 2187 -/* 391 */ MCD_OPC_CheckPredicate, 75, 255, 6, 0, // Skip to: 2187 -/* 396 */ MCD_OPC_CheckField, 23, 9, 231, 3, 247, 6, 0, // Skip to: 2187 -/* 404 */ MCD_OPC_CheckField, 4, 1, 0, 240, 6, 0, // Skip to: 2187 -/* 411 */ MCD_OPC_Decode, 188, 9, 127, // Opcode: VCVTNNSQf -/* 415 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 481 -/* 420 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 423 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 452 -/* 428 */ MCD_OPC_CheckPredicate, 74, 218, 6, 0, // Skip to: 2187 -/* 433 */ MCD_OPC_CheckField, 23, 9, 231, 3, 210, 6, 0, // Skip to: 2187 -/* 441 */ MCD_OPC_CheckField, 4, 1, 0, 203, 6, 0, // Skip to: 2187 -/* 448 */ MCD_OPC_Decode, 191, 9, 126, // Opcode: VCVTNNUDh -/* 452 */ MCD_OPC_FilterValue, 59, 194, 6, 0, // Skip to: 2187 -/* 457 */ MCD_OPC_CheckPredicate, 75, 189, 6, 0, // Skip to: 2187 -/* 462 */ MCD_OPC_CheckField, 23, 9, 231, 3, 181, 6, 0, // Skip to: 2187 -/* 470 */ MCD_OPC_CheckField, 4, 1, 0, 174, 6, 0, // Skip to: 2187 -/* 477 */ MCD_OPC_Decode, 190, 9, 126, // Opcode: VCVTNNUDf -/* 481 */ MCD_OPC_FilterValue, 3, 165, 6, 0, // Skip to: 2187 -/* 486 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 489 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 518 -/* 494 */ MCD_OPC_CheckPredicate, 74, 152, 6, 0, // Skip to: 2187 -/* 499 */ MCD_OPC_CheckField, 23, 9, 231, 3, 144, 6, 0, // Skip to: 2187 -/* 507 */ MCD_OPC_CheckField, 4, 1, 0, 137, 6, 0, // Skip to: 2187 -/* 514 */ MCD_OPC_Decode, 193, 9, 127, // Opcode: VCVTNNUQh -/* 518 */ MCD_OPC_FilterValue, 59, 128, 6, 0, // Skip to: 2187 -/* 523 */ MCD_OPC_CheckPredicate, 75, 123, 6, 0, // Skip to: 2187 -/* 528 */ MCD_OPC_CheckField, 23, 9, 231, 3, 115, 6, 0, // Skip to: 2187 -/* 536 */ MCD_OPC_CheckField, 4, 1, 0, 108, 6, 0, // Skip to: 2187 -/* 543 */ MCD_OPC_Decode, 192, 9, 127, // Opcode: VCVTNNUQf -/* 547 */ MCD_OPC_FilterValue, 2, 11, 1, 0, // Skip to: 819 -/* 552 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 555 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 621 -/* 560 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 563 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 592 -/* 568 */ MCD_OPC_CheckPredicate, 74, 78, 6, 0, // Skip to: 2187 -/* 573 */ MCD_OPC_CheckField, 23, 9, 231, 3, 70, 6, 0, // Skip to: 2187 -/* 581 */ MCD_OPC_CheckField, 4, 1, 0, 63, 6, 0, // Skip to: 2187 -/* 588 */ MCD_OPC_Decode, 201, 9, 126, // Opcode: VCVTPNSDh -/* 592 */ MCD_OPC_FilterValue, 59, 54, 6, 0, // Skip to: 2187 -/* 597 */ MCD_OPC_CheckPredicate, 75, 49, 6, 0, // Skip to: 2187 -/* 602 */ MCD_OPC_CheckField, 23, 9, 231, 3, 41, 6, 0, // Skip to: 2187 -/* 610 */ MCD_OPC_CheckField, 4, 1, 0, 34, 6, 0, // Skip to: 2187 -/* 617 */ MCD_OPC_Decode, 200, 9, 126, // Opcode: VCVTPNSDf -/* 621 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 687 -/* 626 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 629 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 658 -/* 634 */ MCD_OPC_CheckPredicate, 74, 12, 6, 0, // Skip to: 2187 -/* 639 */ MCD_OPC_CheckField, 23, 9, 231, 3, 4, 6, 0, // Skip to: 2187 -/* 647 */ MCD_OPC_CheckField, 4, 1, 0, 253, 5, 0, // Skip to: 2187 -/* 654 */ MCD_OPC_Decode, 203, 9, 127, // Opcode: VCVTPNSQh -/* 658 */ MCD_OPC_FilterValue, 59, 244, 5, 0, // Skip to: 2187 -/* 663 */ MCD_OPC_CheckPredicate, 75, 239, 5, 0, // Skip to: 2187 -/* 668 */ MCD_OPC_CheckField, 23, 9, 231, 3, 231, 5, 0, // Skip to: 2187 -/* 676 */ MCD_OPC_CheckField, 4, 1, 0, 224, 5, 0, // Skip to: 2187 -/* 683 */ MCD_OPC_Decode, 202, 9, 127, // Opcode: VCVTPNSQf -/* 687 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 753 -/* 692 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 695 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 724 -/* 700 */ MCD_OPC_CheckPredicate, 74, 202, 5, 0, // Skip to: 2187 -/* 705 */ MCD_OPC_CheckField, 23, 9, 231, 3, 194, 5, 0, // Skip to: 2187 -/* 713 */ MCD_OPC_CheckField, 4, 1, 0, 187, 5, 0, // Skip to: 2187 -/* 720 */ MCD_OPC_Decode, 205, 9, 126, // Opcode: VCVTPNUDh -/* 724 */ MCD_OPC_FilterValue, 59, 178, 5, 0, // Skip to: 2187 -/* 729 */ MCD_OPC_CheckPredicate, 75, 173, 5, 0, // Skip to: 2187 -/* 734 */ MCD_OPC_CheckField, 23, 9, 231, 3, 165, 5, 0, // Skip to: 2187 -/* 742 */ MCD_OPC_CheckField, 4, 1, 0, 158, 5, 0, // Skip to: 2187 -/* 749 */ MCD_OPC_Decode, 204, 9, 126, // Opcode: VCVTPNUDf -/* 753 */ MCD_OPC_FilterValue, 3, 149, 5, 0, // Skip to: 2187 -/* 758 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 761 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 790 -/* 766 */ MCD_OPC_CheckPredicate, 74, 136, 5, 0, // Skip to: 2187 -/* 771 */ MCD_OPC_CheckField, 23, 9, 231, 3, 128, 5, 0, // Skip to: 2187 -/* 779 */ MCD_OPC_CheckField, 4, 1, 0, 121, 5, 0, // Skip to: 2187 -/* 786 */ MCD_OPC_Decode, 207, 9, 127, // Opcode: VCVTPNUQh -/* 790 */ MCD_OPC_FilterValue, 59, 112, 5, 0, // Skip to: 2187 -/* 795 */ MCD_OPC_CheckPredicate, 75, 107, 5, 0, // Skip to: 2187 -/* 800 */ MCD_OPC_CheckField, 23, 9, 231, 3, 99, 5, 0, // Skip to: 2187 -/* 808 */ MCD_OPC_CheckField, 4, 1, 0, 92, 5, 0, // Skip to: 2187 -/* 815 */ MCD_OPC_Decode, 206, 9, 127, // Opcode: VCVTPNUQf -/* 819 */ MCD_OPC_FilterValue, 3, 11, 1, 0, // Skip to: 1091 -/* 824 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 827 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 893 -/* 832 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 835 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 864 -/* 840 */ MCD_OPC_CheckPredicate, 74, 62, 5, 0, // Skip to: 2187 -/* 845 */ MCD_OPC_CheckField, 23, 9, 231, 3, 54, 5, 0, // Skip to: 2187 -/* 853 */ MCD_OPC_CheckField, 4, 1, 0, 47, 5, 0, // Skip to: 2187 -/* 860 */ MCD_OPC_Decode, 173, 9, 126, // Opcode: VCVTMNSDh -/* 864 */ MCD_OPC_FilterValue, 59, 38, 5, 0, // Skip to: 2187 -/* 869 */ MCD_OPC_CheckPredicate, 75, 33, 5, 0, // Skip to: 2187 -/* 874 */ MCD_OPC_CheckField, 23, 9, 231, 3, 25, 5, 0, // Skip to: 2187 -/* 882 */ MCD_OPC_CheckField, 4, 1, 0, 18, 5, 0, // Skip to: 2187 -/* 889 */ MCD_OPC_Decode, 172, 9, 126, // Opcode: VCVTMNSDf -/* 893 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 959 -/* 898 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 901 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 930 -/* 906 */ MCD_OPC_CheckPredicate, 74, 252, 4, 0, // Skip to: 2187 -/* 911 */ MCD_OPC_CheckField, 23, 9, 231, 3, 244, 4, 0, // Skip to: 2187 -/* 919 */ MCD_OPC_CheckField, 4, 1, 0, 237, 4, 0, // Skip to: 2187 -/* 926 */ MCD_OPC_Decode, 175, 9, 127, // Opcode: VCVTMNSQh -/* 930 */ MCD_OPC_FilterValue, 59, 228, 4, 0, // Skip to: 2187 -/* 935 */ MCD_OPC_CheckPredicate, 75, 223, 4, 0, // Skip to: 2187 -/* 940 */ MCD_OPC_CheckField, 23, 9, 231, 3, 215, 4, 0, // Skip to: 2187 -/* 948 */ MCD_OPC_CheckField, 4, 1, 0, 208, 4, 0, // Skip to: 2187 -/* 955 */ MCD_OPC_Decode, 174, 9, 127, // Opcode: VCVTMNSQf -/* 959 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1025 -/* 964 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 967 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 996 -/* 972 */ MCD_OPC_CheckPredicate, 74, 186, 4, 0, // Skip to: 2187 -/* 977 */ MCD_OPC_CheckField, 23, 9, 231, 3, 178, 4, 0, // Skip to: 2187 -/* 985 */ MCD_OPC_CheckField, 4, 1, 0, 171, 4, 0, // Skip to: 2187 -/* 992 */ MCD_OPC_Decode, 177, 9, 126, // Opcode: VCVTMNUDh -/* 996 */ MCD_OPC_FilterValue, 59, 162, 4, 0, // Skip to: 2187 -/* 1001 */ MCD_OPC_CheckPredicate, 75, 157, 4, 0, // Skip to: 2187 -/* 1006 */ MCD_OPC_CheckField, 23, 9, 231, 3, 149, 4, 0, // Skip to: 2187 -/* 1014 */ MCD_OPC_CheckField, 4, 1, 0, 142, 4, 0, // Skip to: 2187 -/* 1021 */ MCD_OPC_Decode, 176, 9, 126, // Opcode: VCVTMNUDf -/* 1025 */ MCD_OPC_FilterValue, 3, 133, 4, 0, // Skip to: 2187 -/* 1030 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1033 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 1062 -/* 1038 */ MCD_OPC_CheckPredicate, 74, 120, 4, 0, // Skip to: 2187 -/* 1043 */ MCD_OPC_CheckField, 23, 9, 231, 3, 112, 4, 0, // Skip to: 2187 -/* 1051 */ MCD_OPC_CheckField, 4, 1, 0, 105, 4, 0, // Skip to: 2187 -/* 1058 */ MCD_OPC_Decode, 179, 9, 127, // Opcode: VCVTMNUQh -/* 1062 */ MCD_OPC_FilterValue, 59, 96, 4, 0, // Skip to: 2187 -/* 1067 */ MCD_OPC_CheckPredicate, 75, 91, 4, 0, // Skip to: 2187 -/* 1072 */ MCD_OPC_CheckField, 23, 9, 231, 3, 83, 4, 0, // Skip to: 2187 -/* 1080 */ MCD_OPC_CheckField, 4, 1, 0, 76, 4, 0, // Skip to: 2187 -/* 1087 */ MCD_OPC_Decode, 178, 9, 127, // Opcode: VCVTMNUQf -/* 1091 */ MCD_OPC_FilterValue, 4, 11, 1, 0, // Skip to: 1363 -/* 1096 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 1099 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1165 -/* 1104 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1107 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1136 -/* 1112 */ MCD_OPC_CheckPredicate, 74, 46, 4, 0, // Skip to: 2187 -/* 1117 */ MCD_OPC_CheckField, 23, 9, 231, 3, 38, 4, 0, // Skip to: 2187 -/* 1125 */ MCD_OPC_CheckField, 4, 1, 0, 31, 4, 0, // Skip to: 2187 -/* 1132 */ MCD_OPC_Decode, 136, 17, 126, // Opcode: VRINTNNDh -/* 1136 */ MCD_OPC_FilterValue, 58, 22, 4, 0, // Skip to: 2187 -/* 1141 */ MCD_OPC_CheckPredicate, 75, 17, 4, 0, // Skip to: 2187 -/* 1146 */ MCD_OPC_CheckField, 23, 9, 231, 3, 9, 4, 0, // Skip to: 2187 -/* 1154 */ MCD_OPC_CheckField, 4, 1, 0, 2, 4, 0, // Skip to: 2187 -/* 1161 */ MCD_OPC_Decode, 135, 17, 126, // Opcode: VRINTNNDf -/* 1165 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 1231 -/* 1170 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1173 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1202 -/* 1178 */ MCD_OPC_CheckPredicate, 74, 236, 3, 0, // Skip to: 2187 -/* 1183 */ MCD_OPC_CheckField, 23, 9, 231, 3, 228, 3, 0, // Skip to: 2187 -/* 1191 */ MCD_OPC_CheckField, 4, 1, 0, 221, 3, 0, // Skip to: 2187 -/* 1198 */ MCD_OPC_Decode, 138, 17, 127, // Opcode: VRINTNNQh -/* 1202 */ MCD_OPC_FilterValue, 58, 212, 3, 0, // Skip to: 2187 -/* 1207 */ MCD_OPC_CheckPredicate, 75, 207, 3, 0, // Skip to: 2187 -/* 1212 */ MCD_OPC_CheckField, 23, 9, 231, 3, 199, 3, 0, // Skip to: 2187 -/* 1220 */ MCD_OPC_CheckField, 4, 1, 0, 192, 3, 0, // Skip to: 2187 -/* 1227 */ MCD_OPC_Decode, 137, 17, 127, // Opcode: VRINTNNQf -/* 1231 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1297 -/* 1236 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1239 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1268 -/* 1244 */ MCD_OPC_CheckPredicate, 74, 170, 3, 0, // Skip to: 2187 -/* 1249 */ MCD_OPC_CheckField, 23, 9, 231, 3, 162, 3, 0, // Skip to: 2187 -/* 1257 */ MCD_OPC_CheckField, 4, 1, 0, 155, 3, 0, // Skip to: 2187 -/* 1264 */ MCD_OPC_Decode, 153, 17, 126, // Opcode: VRINTXNDh -/* 1268 */ MCD_OPC_FilterValue, 58, 146, 3, 0, // Skip to: 2187 -/* 1273 */ MCD_OPC_CheckPredicate, 75, 141, 3, 0, // Skip to: 2187 -/* 1278 */ MCD_OPC_CheckField, 23, 9, 231, 3, 133, 3, 0, // Skip to: 2187 -/* 1286 */ MCD_OPC_CheckField, 4, 1, 0, 126, 3, 0, // Skip to: 2187 -/* 1293 */ MCD_OPC_Decode, 152, 17, 126, // Opcode: VRINTXNDf -/* 1297 */ MCD_OPC_FilterValue, 3, 117, 3, 0, // Skip to: 2187 -/* 1302 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1305 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1334 -/* 1310 */ MCD_OPC_CheckPredicate, 74, 104, 3, 0, // Skip to: 2187 -/* 1315 */ MCD_OPC_CheckField, 23, 9, 231, 3, 96, 3, 0, // Skip to: 2187 -/* 1323 */ MCD_OPC_CheckField, 4, 1, 0, 89, 3, 0, // Skip to: 2187 -/* 1330 */ MCD_OPC_Decode, 155, 17, 127, // Opcode: VRINTXNQh -/* 1334 */ MCD_OPC_FilterValue, 58, 80, 3, 0, // Skip to: 2187 -/* 1339 */ MCD_OPC_CheckPredicate, 75, 75, 3, 0, // Skip to: 2187 -/* 1344 */ MCD_OPC_CheckField, 23, 9, 231, 3, 67, 3, 0, // Skip to: 2187 -/* 1352 */ MCD_OPC_CheckField, 4, 1, 0, 60, 3, 0, // Skip to: 2187 -/* 1359 */ MCD_OPC_Decode, 154, 17, 127, // Opcode: VRINTXNQf -/* 1363 */ MCD_OPC_FilterValue, 5, 11, 1, 0, // Skip to: 1635 -/* 1368 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 1371 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1437 -/* 1376 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1379 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1408 -/* 1384 */ MCD_OPC_CheckPredicate, 74, 30, 3, 0, // Skip to: 2187 -/* 1389 */ MCD_OPC_CheckField, 23, 9, 231, 3, 22, 3, 0, // Skip to: 2187 -/* 1397 */ MCD_OPC_CheckField, 4, 1, 0, 15, 3, 0, // Skip to: 2187 -/* 1404 */ MCD_OPC_Decode, 250, 16, 126, // Opcode: VRINTANDh -/* 1408 */ MCD_OPC_FilterValue, 58, 6, 3, 0, // Skip to: 2187 -/* 1413 */ MCD_OPC_CheckPredicate, 75, 1, 3, 0, // Skip to: 2187 -/* 1418 */ MCD_OPC_CheckField, 23, 9, 231, 3, 249, 2, 0, // Skip to: 2187 -/* 1426 */ MCD_OPC_CheckField, 4, 1, 0, 242, 2, 0, // Skip to: 2187 -/* 1433 */ MCD_OPC_Decode, 249, 16, 126, // Opcode: VRINTANDf -/* 1437 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 1503 -/* 1442 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1445 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1474 -/* 1450 */ MCD_OPC_CheckPredicate, 74, 220, 2, 0, // Skip to: 2187 -/* 1455 */ MCD_OPC_CheckField, 23, 9, 231, 3, 212, 2, 0, // Skip to: 2187 -/* 1463 */ MCD_OPC_CheckField, 4, 1, 0, 205, 2, 0, // Skip to: 2187 -/* 1470 */ MCD_OPC_Decode, 252, 16, 127, // Opcode: VRINTANQh -/* 1474 */ MCD_OPC_FilterValue, 58, 196, 2, 0, // Skip to: 2187 -/* 1479 */ MCD_OPC_CheckPredicate, 75, 191, 2, 0, // Skip to: 2187 -/* 1484 */ MCD_OPC_CheckField, 23, 9, 231, 3, 183, 2, 0, // Skip to: 2187 -/* 1492 */ MCD_OPC_CheckField, 4, 1, 0, 176, 2, 0, // Skip to: 2187 -/* 1499 */ MCD_OPC_Decode, 251, 16, 127, // Opcode: VRINTANQf -/* 1503 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1569 -/* 1508 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1511 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1540 -/* 1516 */ MCD_OPC_CheckPredicate, 74, 154, 2, 0, // Skip to: 2187 -/* 1521 */ MCD_OPC_CheckField, 23, 9, 231, 3, 146, 2, 0, // Skip to: 2187 -/* 1529 */ MCD_OPC_CheckField, 4, 1, 0, 139, 2, 0, // Skip to: 2187 -/* 1536 */ MCD_OPC_Decode, 160, 17, 126, // Opcode: VRINTZNDh -/* 1540 */ MCD_OPC_FilterValue, 58, 130, 2, 0, // Skip to: 2187 -/* 1545 */ MCD_OPC_CheckPredicate, 75, 125, 2, 0, // Skip to: 2187 -/* 1550 */ MCD_OPC_CheckField, 23, 9, 231, 3, 117, 2, 0, // Skip to: 2187 -/* 1558 */ MCD_OPC_CheckField, 4, 1, 0, 110, 2, 0, // Skip to: 2187 -/* 1565 */ MCD_OPC_Decode, 159, 17, 126, // Opcode: VRINTZNDf -/* 1569 */ MCD_OPC_FilterValue, 3, 101, 2, 0, // Skip to: 2187 -/* 1574 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1577 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1606 -/* 1582 */ MCD_OPC_CheckPredicate, 74, 88, 2, 0, // Skip to: 2187 -/* 1587 */ MCD_OPC_CheckField, 23, 9, 231, 3, 80, 2, 0, // Skip to: 2187 -/* 1595 */ MCD_OPC_CheckField, 4, 1, 0, 73, 2, 0, // Skip to: 2187 -/* 1602 */ MCD_OPC_Decode, 162, 17, 127, // Opcode: VRINTZNQh -/* 1606 */ MCD_OPC_FilterValue, 58, 64, 2, 0, // Skip to: 2187 -/* 1611 */ MCD_OPC_CheckPredicate, 75, 59, 2, 0, // Skip to: 2187 -/* 1616 */ MCD_OPC_CheckField, 23, 9, 231, 3, 51, 2, 0, // Skip to: 2187 -/* 1624 */ MCD_OPC_CheckField, 4, 1, 0, 44, 2, 0, // Skip to: 2187 -/* 1631 */ MCD_OPC_Decode, 161, 17, 127, // Opcode: VRINTZNQf -/* 1635 */ MCD_OPC_FilterValue, 6, 135, 0, 0, // Skip to: 1775 -/* 1640 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 1643 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1709 -/* 1648 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1651 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1680 -/* 1656 */ MCD_OPC_CheckPredicate, 74, 14, 2, 0, // Skip to: 2187 -/* 1661 */ MCD_OPC_CheckField, 23, 9, 231, 3, 6, 2, 0, // Skip to: 2187 -/* 1669 */ MCD_OPC_CheckField, 4, 1, 0, 255, 1, 0, // Skip to: 2187 -/* 1676 */ MCD_OPC_Decode, 129, 17, 126, // Opcode: VRINTMNDh -/* 1680 */ MCD_OPC_FilterValue, 58, 246, 1, 0, // Skip to: 2187 -/* 1685 */ MCD_OPC_CheckPredicate, 75, 241, 1, 0, // Skip to: 2187 -/* 1690 */ MCD_OPC_CheckField, 23, 9, 231, 3, 233, 1, 0, // Skip to: 2187 -/* 1698 */ MCD_OPC_CheckField, 4, 1, 0, 226, 1, 0, // Skip to: 2187 -/* 1705 */ MCD_OPC_Decode, 128, 17, 126, // Opcode: VRINTMNDf -/* 1709 */ MCD_OPC_FilterValue, 3, 217, 1, 0, // Skip to: 2187 -/* 1714 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1717 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1746 -/* 1722 */ MCD_OPC_CheckPredicate, 74, 204, 1, 0, // Skip to: 2187 -/* 1727 */ MCD_OPC_CheckField, 23, 9, 231, 3, 196, 1, 0, // Skip to: 2187 -/* 1735 */ MCD_OPC_CheckField, 4, 1, 0, 189, 1, 0, // Skip to: 2187 -/* 1742 */ MCD_OPC_Decode, 131, 17, 127, // Opcode: VRINTMNQh -/* 1746 */ MCD_OPC_FilterValue, 58, 180, 1, 0, // Skip to: 2187 -/* 1751 */ MCD_OPC_CheckPredicate, 75, 175, 1, 0, // Skip to: 2187 -/* 1756 */ MCD_OPC_CheckField, 23, 9, 231, 3, 167, 1, 0, // Skip to: 2187 -/* 1764 */ MCD_OPC_CheckField, 4, 1, 0, 160, 1, 0, // Skip to: 2187 -/* 1771 */ MCD_OPC_Decode, 130, 17, 127, // Opcode: VRINTMNQf -/* 1775 */ MCD_OPC_FilterValue, 7, 135, 0, 0, // Skip to: 1915 -/* 1780 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 1783 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1849 -/* 1788 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1791 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1820 -/* 1796 */ MCD_OPC_CheckPredicate, 74, 130, 1, 0, // Skip to: 2187 -/* 1801 */ MCD_OPC_CheckField, 23, 9, 231, 3, 122, 1, 0, // Skip to: 2187 -/* 1809 */ MCD_OPC_CheckField, 4, 1, 0, 115, 1, 0, // Skip to: 2187 -/* 1816 */ MCD_OPC_Decode, 143, 17, 126, // Opcode: VRINTPNDh -/* 1820 */ MCD_OPC_FilterValue, 58, 106, 1, 0, // Skip to: 2187 -/* 1825 */ MCD_OPC_CheckPredicate, 75, 101, 1, 0, // Skip to: 2187 -/* 1830 */ MCD_OPC_CheckField, 23, 9, 231, 3, 93, 1, 0, // Skip to: 2187 -/* 1838 */ MCD_OPC_CheckField, 4, 1, 0, 86, 1, 0, // Skip to: 2187 -/* 1845 */ MCD_OPC_Decode, 142, 17, 126, // Opcode: VRINTPNDf -/* 1849 */ MCD_OPC_FilterValue, 3, 77, 1, 0, // Skip to: 2187 -/* 1854 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 1857 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1886 -/* 1862 */ MCD_OPC_CheckPredicate, 74, 64, 1, 0, // Skip to: 2187 -/* 1867 */ MCD_OPC_CheckField, 23, 9, 231, 3, 56, 1, 0, // Skip to: 2187 -/* 1875 */ MCD_OPC_CheckField, 4, 1, 0, 49, 1, 0, // Skip to: 2187 -/* 1882 */ MCD_OPC_Decode, 145, 17, 127, // Opcode: VRINTPNQh -/* 1886 */ MCD_OPC_FilterValue, 58, 40, 1, 0, // Skip to: 2187 -/* 1891 */ MCD_OPC_CheckPredicate, 75, 35, 1, 0, // Skip to: 2187 -/* 1896 */ MCD_OPC_CheckField, 23, 9, 231, 3, 27, 1, 0, // Skip to: 2187 -/* 1904 */ MCD_OPC_CheckField, 4, 1, 0, 20, 1, 0, // Skip to: 2187 -/* 1911 */ MCD_OPC_Decode, 144, 17, 127, // Opcode: VRINTPNQf -/* 1915 */ MCD_OPC_FilterValue, 15, 11, 1, 0, // Skip to: 2187 -/* 1920 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... -/* 1923 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1989 -/* 1928 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1931 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1960 -/* 1936 */ MCD_OPC_CheckPredicate, 75, 246, 0, 0, // Skip to: 2187 -/* 1941 */ MCD_OPC_CheckField, 23, 9, 230, 3, 238, 0, 0, // Skip to: 2187 -/* 1949 */ MCD_OPC_CheckField, 4, 1, 1, 231, 0, 0, // Skip to: 2187 -/* 1956 */ MCD_OPC_Decode, 158, 13, 97, // Opcode: VMAXNMNDf -/* 1960 */ MCD_OPC_FilterValue, 1, 222, 0, 0, // Skip to: 2187 -/* 1965 */ MCD_OPC_CheckPredicate, 75, 217, 0, 0, // Skip to: 2187 -/* 1970 */ MCD_OPC_CheckField, 23, 9, 230, 3, 209, 0, 0, // Skip to: 2187 -/* 1978 */ MCD_OPC_CheckField, 4, 1, 1, 202, 0, 0, // Skip to: 2187 -/* 1985 */ MCD_OPC_Decode, 160, 13, 98, // Opcode: VMAXNMNQf -/* 1989 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 2055 -/* 1994 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 1997 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2026 -/* 2002 */ MCD_OPC_CheckPredicate, 74, 180, 0, 0, // Skip to: 2187 -/* 2007 */ MCD_OPC_CheckField, 23, 9, 230, 3, 172, 0, 0, // Skip to: 2187 -/* 2015 */ MCD_OPC_CheckField, 4, 1, 1, 165, 0, 0, // Skip to: 2187 -/* 2022 */ MCD_OPC_Decode, 159, 13, 97, // Opcode: VMAXNMNDh -/* 2026 */ MCD_OPC_FilterValue, 1, 156, 0, 0, // Skip to: 2187 -/* 2031 */ MCD_OPC_CheckPredicate, 74, 151, 0, 0, // Skip to: 2187 -/* 2036 */ MCD_OPC_CheckField, 23, 9, 230, 3, 143, 0, 0, // Skip to: 2187 -/* 2044 */ MCD_OPC_CheckField, 4, 1, 1, 136, 0, 0, // Skip to: 2187 -/* 2051 */ MCD_OPC_Decode, 161, 13, 98, // Opcode: VMAXNMNQh -/* 2055 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 2121 -/* 2060 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2063 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2092 -/* 2068 */ MCD_OPC_CheckPredicate, 75, 114, 0, 0, // Skip to: 2187 -/* 2073 */ MCD_OPC_CheckField, 23, 9, 230, 3, 106, 0, 0, // Skip to: 2187 -/* 2081 */ MCD_OPC_CheckField, 4, 1, 1, 99, 0, 0, // Skip to: 2187 -/* 2088 */ MCD_OPC_Decode, 181, 13, 97, // Opcode: VMINNMNDf -/* 2092 */ MCD_OPC_FilterValue, 1, 90, 0, 0, // Skip to: 2187 -/* 2097 */ MCD_OPC_CheckPredicate, 75, 85, 0, 0, // Skip to: 2187 -/* 2102 */ MCD_OPC_CheckField, 23, 9, 230, 3, 77, 0, 0, // Skip to: 2187 -/* 2110 */ MCD_OPC_CheckField, 4, 1, 1, 70, 0, 0, // Skip to: 2187 -/* 2117 */ MCD_OPC_Decode, 183, 13, 98, // Opcode: VMINNMNQf -/* 2121 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 2187 -/* 2126 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 2129 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2158 -/* 2134 */ MCD_OPC_CheckPredicate, 74, 48, 0, 0, // Skip to: 2187 -/* 2139 */ MCD_OPC_CheckField, 23, 9, 230, 3, 40, 0, 0, // Skip to: 2187 -/* 2147 */ MCD_OPC_CheckField, 4, 1, 1, 33, 0, 0, // Skip to: 2187 -/* 2154 */ MCD_OPC_Decode, 182, 13, 97, // Opcode: VMINNMNDh -/* 2158 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2187 -/* 2163 */ MCD_OPC_CheckPredicate, 74, 19, 0, 0, // Skip to: 2187 -/* 2168 */ MCD_OPC_CheckField, 23, 9, 230, 3, 11, 0, 0, // Skip to: 2187 -/* 2176 */ MCD_OPC_CheckField, 4, 1, 1, 4, 0, 0, // Skip to: 2187 -/* 2183 */ MCD_OPC_Decode, 184, 13, 98, // Opcode: VMINNMNQh -/* 2187 */ MCD_OPC_Fail, - 0 -}; - -static bool checkDecoderPredicate(unsigned Idx, MCInst *MI) -{ + /* 0 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 19, + 1, + 0, // Skip to: 283 + /* 8 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 79 + /* 16 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 19 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 49 + /* 24 */ MCD_OPC_CheckPredicate, + 95, + 174, + 8, + 0, // Skip to: 2251 + /* 29 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 166, + 8, + 0, // Skip to: 2251 + /* 37 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 159, + 8, + 0, // Skip to: 2251 + /* 44 */ MCD_OPC_Decode, + 187, + 17, + 229, + 1, // Opcode: VCVTANSDh + /* 49 */ MCD_OPC_FilterValue, + 59, + 149, + 8, + 0, // Skip to: 2251 + /* 54 */ MCD_OPC_CheckPredicate, + 96, + 144, + 8, + 0, // Skip to: 2251 + /* 59 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 136, + 8, + 0, // Skip to: 2251 + /* 67 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 129, + 8, + 0, // Skip to: 2251 + /* 74 */ MCD_OPC_Decode, + 186, + 17, + 229, + 1, // Opcode: VCVTANSDf + /* 79 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 147 + /* 84 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 87 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 117 + /* 92 */ MCD_OPC_CheckPredicate, + 95, + 106, + 8, + 0, // Skip to: 2251 + /* 97 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 98, + 8, + 0, // Skip to: 2251 + /* 105 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 91, + 8, + 0, // Skip to: 2251 + /* 112 */ MCD_OPC_Decode, + 189, + 17, + 230, + 1, // Opcode: VCVTANSQh + /* 117 */ MCD_OPC_FilterValue, + 59, + 81, + 8, + 0, // Skip to: 2251 + /* 122 */ MCD_OPC_CheckPredicate, + 96, + 76, + 8, + 0, // Skip to: 2251 + /* 127 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 68, + 8, + 0, // Skip to: 2251 + /* 135 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 61, + 8, + 0, // Skip to: 2251 + /* 142 */ MCD_OPC_Decode, + 188, + 17, + 230, + 1, // Opcode: VCVTANSQf + /* 147 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 215 + /* 152 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 155 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 185 + /* 160 */ MCD_OPC_CheckPredicate, + 95, + 38, + 8, + 0, // Skip to: 2251 + /* 165 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 30, + 8, + 0, // Skip to: 2251 + /* 173 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 23, + 8, + 0, // Skip to: 2251 + /* 180 */ MCD_OPC_Decode, + 191, + 17, + 229, + 1, // Opcode: VCVTANUDh + /* 185 */ MCD_OPC_FilterValue, + 59, + 13, + 8, + 0, // Skip to: 2251 + /* 190 */ MCD_OPC_CheckPredicate, + 96, + 8, + 8, + 0, // Skip to: 2251 + /* 195 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 0, + 8, + 0, // Skip to: 2251 + /* 203 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 249, + 7, + 0, // Skip to: 2251 + /* 210 */ MCD_OPC_Decode, + 190, + 17, + 229, + 1, // Opcode: VCVTANUDf + /* 215 */ MCD_OPC_FilterValue, + 3, + 239, + 7, + 0, // Skip to: 2251 + /* 220 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 223 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 253 + /* 228 */ MCD_OPC_CheckPredicate, + 95, + 226, + 7, + 0, // Skip to: 2251 + /* 233 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 218, + 7, + 0, // Skip to: 2251 + /* 241 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 211, + 7, + 0, // Skip to: 2251 + /* 248 */ MCD_OPC_Decode, + 193, + 17, + 230, + 1, // Opcode: VCVTANUQh + /* 253 */ MCD_OPC_FilterValue, + 59, + 201, + 7, + 0, // Skip to: 2251 + /* 258 */ MCD_OPC_CheckPredicate, + 96, + 196, + 7, + 0, // Skip to: 2251 + /* 263 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 188, + 7, + 0, // Skip to: 2251 + /* 271 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 181, + 7, + 0, // Skip to: 2251 + /* 278 */ MCD_OPC_Decode, + 192, + 17, + 230, + 1, // Opcode: VCVTANUQf + /* 283 */ MCD_OPC_FilterValue, + 1, + 19, + 1, + 0, // Skip to: 563 + /* 288 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 291 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 359 + /* 296 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 299 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 329 + /* 304 */ MCD_OPC_CheckPredicate, + 95, + 150, + 7, + 0, // Skip to: 2251 + /* 309 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 142, + 7, + 0, // Skip to: 2251 + /* 317 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 135, + 7, + 0, // Skip to: 2251 + /* 324 */ MCD_OPC_Decode, + 220, + 17, + 229, + 1, // Opcode: VCVTNNSDh + /* 329 */ MCD_OPC_FilterValue, + 59, + 125, + 7, + 0, // Skip to: 2251 + /* 334 */ MCD_OPC_CheckPredicate, + 96, + 120, + 7, + 0, // Skip to: 2251 + /* 339 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 112, + 7, + 0, // Skip to: 2251 + /* 347 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 105, + 7, + 0, // Skip to: 2251 + /* 354 */ MCD_OPC_Decode, + 219, + 17, + 229, + 1, // Opcode: VCVTNNSDf + /* 359 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 427 + /* 364 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 367 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 397 + /* 372 */ MCD_OPC_CheckPredicate, + 95, + 82, + 7, + 0, // Skip to: 2251 + /* 377 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 74, + 7, + 0, // Skip to: 2251 + /* 385 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 67, + 7, + 0, // Skip to: 2251 + /* 392 */ MCD_OPC_Decode, + 222, + 17, + 230, + 1, // Opcode: VCVTNNSQh + /* 397 */ MCD_OPC_FilterValue, + 59, + 57, + 7, + 0, // Skip to: 2251 + /* 402 */ MCD_OPC_CheckPredicate, + 96, + 52, + 7, + 0, // Skip to: 2251 + /* 407 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 44, + 7, + 0, // Skip to: 2251 + /* 415 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 37, + 7, + 0, // Skip to: 2251 + /* 422 */ MCD_OPC_Decode, + 221, + 17, + 230, + 1, // Opcode: VCVTNNSQf + /* 427 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 495 + /* 432 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 435 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 465 + /* 440 */ MCD_OPC_CheckPredicate, + 95, + 14, + 7, + 0, // Skip to: 2251 + /* 445 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 6, + 7, + 0, // Skip to: 2251 + /* 453 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 255, + 6, + 0, // Skip to: 2251 + /* 460 */ MCD_OPC_Decode, + 224, + 17, + 229, + 1, // Opcode: VCVTNNUDh + /* 465 */ MCD_OPC_FilterValue, + 59, + 245, + 6, + 0, // Skip to: 2251 + /* 470 */ MCD_OPC_CheckPredicate, + 96, + 240, + 6, + 0, // Skip to: 2251 + /* 475 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 232, + 6, + 0, // Skip to: 2251 + /* 483 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 225, + 6, + 0, // Skip to: 2251 + /* 490 */ MCD_OPC_Decode, + 223, + 17, + 229, + 1, // Opcode: VCVTNNUDf + /* 495 */ MCD_OPC_FilterValue, + 3, + 215, + 6, + 0, // Skip to: 2251 + /* 500 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 503 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 533 + /* 508 */ MCD_OPC_CheckPredicate, + 95, + 202, + 6, + 0, // Skip to: 2251 + /* 513 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 194, + 6, + 0, // Skip to: 2251 + /* 521 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 187, + 6, + 0, // Skip to: 2251 + /* 528 */ MCD_OPC_Decode, + 226, + 17, + 230, + 1, // Opcode: VCVTNNUQh + /* 533 */ MCD_OPC_FilterValue, + 59, + 177, + 6, + 0, // Skip to: 2251 + /* 538 */ MCD_OPC_CheckPredicate, + 96, + 172, + 6, + 0, // Skip to: 2251 + /* 543 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 164, + 6, + 0, // Skip to: 2251 + /* 551 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 157, + 6, + 0, // Skip to: 2251 + /* 558 */ MCD_OPC_Decode, + 225, + 17, + 230, + 1, // Opcode: VCVTNNUQf + /* 563 */ MCD_OPC_FilterValue, + 2, + 19, + 1, + 0, // Skip to: 843 + /* 568 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 571 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 639 + /* 576 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 579 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 609 + /* 584 */ MCD_OPC_CheckPredicate, + 95, + 126, + 6, + 0, // Skip to: 2251 + /* 589 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 118, + 6, + 0, // Skip to: 2251 + /* 597 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 111, + 6, + 0, // Skip to: 2251 + /* 604 */ MCD_OPC_Decode, + 234, + 17, + 229, + 1, // Opcode: VCVTPNSDh + /* 609 */ MCD_OPC_FilterValue, + 59, + 101, + 6, + 0, // Skip to: 2251 + /* 614 */ MCD_OPC_CheckPredicate, + 96, + 96, + 6, + 0, // Skip to: 2251 + /* 619 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 88, + 6, + 0, // Skip to: 2251 + /* 627 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 81, + 6, + 0, // Skip to: 2251 + /* 634 */ MCD_OPC_Decode, + 233, + 17, + 229, + 1, // Opcode: VCVTPNSDf + /* 639 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 707 + /* 644 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 647 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 677 + /* 652 */ MCD_OPC_CheckPredicate, + 95, + 58, + 6, + 0, // Skip to: 2251 + /* 657 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 50, + 6, + 0, // Skip to: 2251 + /* 665 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 43, + 6, + 0, // Skip to: 2251 + /* 672 */ MCD_OPC_Decode, + 236, + 17, + 230, + 1, // Opcode: VCVTPNSQh + /* 677 */ MCD_OPC_FilterValue, + 59, + 33, + 6, + 0, // Skip to: 2251 + /* 682 */ MCD_OPC_CheckPredicate, + 96, + 28, + 6, + 0, // Skip to: 2251 + /* 687 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 20, + 6, + 0, // Skip to: 2251 + /* 695 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 13, + 6, + 0, // Skip to: 2251 + /* 702 */ MCD_OPC_Decode, + 235, + 17, + 230, + 1, // Opcode: VCVTPNSQf + /* 707 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 775 + /* 712 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 715 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 745 + /* 720 */ MCD_OPC_CheckPredicate, + 95, + 246, + 5, + 0, // Skip to: 2251 + /* 725 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 238, + 5, + 0, // Skip to: 2251 + /* 733 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 231, + 5, + 0, // Skip to: 2251 + /* 740 */ MCD_OPC_Decode, + 238, + 17, + 229, + 1, // Opcode: VCVTPNUDh + /* 745 */ MCD_OPC_FilterValue, + 59, + 221, + 5, + 0, // Skip to: 2251 + /* 750 */ MCD_OPC_CheckPredicate, + 96, + 216, + 5, + 0, // Skip to: 2251 + /* 755 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 208, + 5, + 0, // Skip to: 2251 + /* 763 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 201, + 5, + 0, // Skip to: 2251 + /* 770 */ MCD_OPC_Decode, + 237, + 17, + 229, + 1, // Opcode: VCVTPNUDf + /* 775 */ MCD_OPC_FilterValue, + 3, + 191, + 5, + 0, // Skip to: 2251 + /* 780 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 783 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 813 + /* 788 */ MCD_OPC_CheckPredicate, + 95, + 178, + 5, + 0, // Skip to: 2251 + /* 793 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 170, + 5, + 0, // Skip to: 2251 + /* 801 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 163, + 5, + 0, // Skip to: 2251 + /* 808 */ MCD_OPC_Decode, + 240, + 17, + 230, + 1, // Opcode: VCVTPNUQh + /* 813 */ MCD_OPC_FilterValue, + 59, + 153, + 5, + 0, // Skip to: 2251 + /* 818 */ MCD_OPC_CheckPredicate, + 96, + 148, + 5, + 0, // Skip to: 2251 + /* 823 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 140, + 5, + 0, // Skip to: 2251 + /* 831 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 133, + 5, + 0, // Skip to: 2251 + /* 838 */ MCD_OPC_Decode, + 239, + 17, + 230, + 1, // Opcode: VCVTPNUQf + /* 843 */ MCD_OPC_FilterValue, + 3, + 19, + 1, + 0, // Skip to: 1123 + /* 848 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 851 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 919 + /* 856 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 859 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 889 + /* 864 */ MCD_OPC_CheckPredicate, + 95, + 102, + 5, + 0, // Skip to: 2251 + /* 869 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 94, + 5, + 0, // Skip to: 2251 + /* 877 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 87, + 5, + 0, // Skip to: 2251 + /* 884 */ MCD_OPC_Decode, + 206, + 17, + 229, + 1, // Opcode: VCVTMNSDh + /* 889 */ MCD_OPC_FilterValue, + 59, + 77, + 5, + 0, // Skip to: 2251 + /* 894 */ MCD_OPC_CheckPredicate, + 96, + 72, + 5, + 0, // Skip to: 2251 + /* 899 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 64, + 5, + 0, // Skip to: 2251 + /* 907 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 57, + 5, + 0, // Skip to: 2251 + /* 914 */ MCD_OPC_Decode, + 205, + 17, + 229, + 1, // Opcode: VCVTMNSDf + /* 919 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 987 + /* 924 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 927 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 957 + /* 932 */ MCD_OPC_CheckPredicate, + 95, + 34, + 5, + 0, // Skip to: 2251 + /* 937 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 26, + 5, + 0, // Skip to: 2251 + /* 945 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 19, + 5, + 0, // Skip to: 2251 + /* 952 */ MCD_OPC_Decode, + 208, + 17, + 230, + 1, // Opcode: VCVTMNSQh + /* 957 */ MCD_OPC_FilterValue, + 59, + 9, + 5, + 0, // Skip to: 2251 + /* 962 */ MCD_OPC_CheckPredicate, + 96, + 4, + 5, + 0, // Skip to: 2251 + /* 967 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 252, + 4, + 0, // Skip to: 2251 + /* 975 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 245, + 4, + 0, // Skip to: 2251 + /* 982 */ MCD_OPC_Decode, + 207, + 17, + 230, + 1, // Opcode: VCVTMNSQf + /* 987 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1055 + /* 992 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 995 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 1025 + /* 1000 */ MCD_OPC_CheckPredicate, + 95, + 222, + 4, + 0, // Skip to: 2251 + /* 1005 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 214, + 4, + 0, // Skip to: 2251 + /* 1013 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 207, + 4, + 0, // Skip to: 2251 + /* 1020 */ MCD_OPC_Decode, + 210, + 17, + 229, + 1, // Opcode: VCVTMNUDh + /* 1025 */ MCD_OPC_FilterValue, + 59, + 197, + 4, + 0, // Skip to: 2251 + /* 1030 */ MCD_OPC_CheckPredicate, + 96, + 192, + 4, + 0, // Skip to: 2251 + /* 1035 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 184, + 4, + 0, // Skip to: 2251 + /* 1043 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 177, + 4, + 0, // Skip to: 2251 + /* 1050 */ MCD_OPC_Decode, + 209, + 17, + 229, + 1, // Opcode: VCVTMNUDf + /* 1055 */ MCD_OPC_FilterValue, + 3, + 167, + 4, + 0, // Skip to: 2251 + /* 1060 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1063 */ MCD_OPC_FilterValue, + 55, + 25, + 0, + 0, // Skip to: 1093 + /* 1068 */ MCD_OPC_CheckPredicate, + 95, + 154, + 4, + 0, // Skip to: 2251 + /* 1073 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 146, + 4, + 0, // Skip to: 2251 + /* 1081 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 139, + 4, + 0, // Skip to: 2251 + /* 1088 */ MCD_OPC_Decode, + 212, + 17, + 230, + 1, // Opcode: VCVTMNUQh + /* 1093 */ MCD_OPC_FilterValue, + 59, + 129, + 4, + 0, // Skip to: 2251 + /* 1098 */ MCD_OPC_CheckPredicate, + 96, + 124, + 4, + 0, // Skip to: 2251 + /* 1103 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 116, + 4, + 0, // Skip to: 2251 + /* 1111 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 109, + 4, + 0, // Skip to: 2251 + /* 1118 */ MCD_OPC_Decode, + 211, + 17, + 230, + 1, // Opcode: VCVTMNUQf + /* 1123 */ MCD_OPC_FilterValue, + 4, + 19, + 1, + 0, // Skip to: 1403 + /* 1128 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1131 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 1199 + /* 1136 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1139 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1169 + /* 1144 */ MCD_OPC_CheckPredicate, + 95, + 78, + 4, + 0, // Skip to: 2251 + /* 1149 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 70, + 4, + 0, // Skip to: 2251 + /* 1157 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 63, + 4, + 0, // Skip to: 2251 + /* 1164 */ MCD_OPC_Decode, + 230, + 25, + 229, + 1, // Opcode: VRINTNNDh + /* 1169 */ MCD_OPC_FilterValue, + 58, + 53, + 4, + 0, // Skip to: 2251 + /* 1174 */ MCD_OPC_CheckPredicate, + 96, + 48, + 4, + 0, // Skip to: 2251 + /* 1179 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 40, + 4, + 0, // Skip to: 2251 + /* 1187 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 33, + 4, + 0, // Skip to: 2251 + /* 1194 */ MCD_OPC_Decode, + 229, + 25, + 229, + 1, // Opcode: VRINTNNDf + /* 1199 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 1267 + /* 1204 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1207 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1237 + /* 1212 */ MCD_OPC_CheckPredicate, + 95, + 10, + 4, + 0, // Skip to: 2251 + /* 1217 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 2, + 4, + 0, // Skip to: 2251 + /* 1225 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 251, + 3, + 0, // Skip to: 2251 + /* 1232 */ MCD_OPC_Decode, + 232, + 25, + 230, + 1, // Opcode: VRINTNNQh + /* 1237 */ MCD_OPC_FilterValue, + 58, + 241, + 3, + 0, // Skip to: 2251 + /* 1242 */ MCD_OPC_CheckPredicate, + 96, + 236, + 3, + 0, // Skip to: 2251 + /* 1247 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 228, + 3, + 0, // Skip to: 2251 + /* 1255 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 221, + 3, + 0, // Skip to: 2251 + /* 1262 */ MCD_OPC_Decode, + 231, + 25, + 230, + 1, // Opcode: VRINTNNQf + /* 1267 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1335 + /* 1272 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1275 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1305 + /* 1280 */ MCD_OPC_CheckPredicate, + 95, + 198, + 3, + 0, // Skip to: 2251 + /* 1285 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 190, + 3, + 0, // Skip to: 2251 + /* 1293 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 183, + 3, + 0, // Skip to: 2251 + /* 1300 */ MCD_OPC_Decode, + 247, + 25, + 229, + 1, // Opcode: VRINTXNDh + /* 1305 */ MCD_OPC_FilterValue, + 58, + 173, + 3, + 0, // Skip to: 2251 + /* 1310 */ MCD_OPC_CheckPredicate, + 96, + 168, + 3, + 0, // Skip to: 2251 + /* 1315 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 160, + 3, + 0, // Skip to: 2251 + /* 1323 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 153, + 3, + 0, // Skip to: 2251 + /* 1330 */ MCD_OPC_Decode, + 246, + 25, + 229, + 1, // Opcode: VRINTXNDf + /* 1335 */ MCD_OPC_FilterValue, + 3, + 143, + 3, + 0, // Skip to: 2251 + /* 1340 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1343 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1373 + /* 1348 */ MCD_OPC_CheckPredicate, + 95, + 130, + 3, + 0, // Skip to: 2251 + /* 1353 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 122, + 3, + 0, // Skip to: 2251 + /* 1361 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 115, + 3, + 0, // Skip to: 2251 + /* 1368 */ MCD_OPC_Decode, + 249, + 25, + 230, + 1, // Opcode: VRINTXNQh + /* 1373 */ MCD_OPC_FilterValue, + 58, + 105, + 3, + 0, // Skip to: 2251 + /* 1378 */ MCD_OPC_CheckPredicate, + 96, + 100, + 3, + 0, // Skip to: 2251 + /* 1383 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 92, + 3, + 0, // Skip to: 2251 + /* 1391 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 85, + 3, + 0, // Skip to: 2251 + /* 1398 */ MCD_OPC_Decode, + 248, + 25, + 230, + 1, // Opcode: VRINTXNQf + /* 1403 */ MCD_OPC_FilterValue, + 5, + 19, + 1, + 0, // Skip to: 1683 + /* 1408 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1411 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 1479 + /* 1416 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1419 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1449 + /* 1424 */ MCD_OPC_CheckPredicate, + 95, + 54, + 3, + 0, // Skip to: 2251 + /* 1429 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 46, + 3, + 0, // Skip to: 2251 + /* 1437 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 39, + 3, + 0, // Skip to: 2251 + /* 1444 */ MCD_OPC_Decode, + 216, + 25, + 229, + 1, // Opcode: VRINTANDh + /* 1449 */ MCD_OPC_FilterValue, + 58, + 29, + 3, + 0, // Skip to: 2251 + /* 1454 */ MCD_OPC_CheckPredicate, + 96, + 24, + 3, + 0, // Skip to: 2251 + /* 1459 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 16, + 3, + 0, // Skip to: 2251 + /* 1467 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 9, + 3, + 0, // Skip to: 2251 + /* 1474 */ MCD_OPC_Decode, + 215, + 25, + 229, + 1, // Opcode: VRINTANDf + /* 1479 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 1547 + /* 1484 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1487 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1517 + /* 1492 */ MCD_OPC_CheckPredicate, + 95, + 242, + 2, + 0, // Skip to: 2251 + /* 1497 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 234, + 2, + 0, // Skip to: 2251 + /* 1505 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 227, + 2, + 0, // Skip to: 2251 + /* 1512 */ MCD_OPC_Decode, + 218, + 25, + 230, + 1, // Opcode: VRINTANQh + /* 1517 */ MCD_OPC_FilterValue, + 58, + 217, + 2, + 0, // Skip to: 2251 + /* 1522 */ MCD_OPC_CheckPredicate, + 96, + 212, + 2, + 0, // Skip to: 2251 + /* 1527 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 204, + 2, + 0, // Skip to: 2251 + /* 1535 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 197, + 2, + 0, // Skip to: 2251 + /* 1542 */ MCD_OPC_Decode, + 217, + 25, + 230, + 1, // Opcode: VRINTANQf + /* 1547 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1615 + /* 1552 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1555 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1585 + /* 1560 */ MCD_OPC_CheckPredicate, + 95, + 174, + 2, + 0, // Skip to: 2251 + /* 1565 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 166, + 2, + 0, // Skip to: 2251 + /* 1573 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 159, + 2, + 0, // Skip to: 2251 + /* 1580 */ MCD_OPC_Decode, + 254, + 25, + 229, + 1, // Opcode: VRINTZNDh + /* 1585 */ MCD_OPC_FilterValue, + 58, + 149, + 2, + 0, // Skip to: 2251 + /* 1590 */ MCD_OPC_CheckPredicate, + 96, + 144, + 2, + 0, // Skip to: 2251 + /* 1595 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 136, + 2, + 0, // Skip to: 2251 + /* 1603 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 129, + 2, + 0, // Skip to: 2251 + /* 1610 */ MCD_OPC_Decode, + 253, + 25, + 229, + 1, // Opcode: VRINTZNDf + /* 1615 */ MCD_OPC_FilterValue, + 3, + 119, + 2, + 0, // Skip to: 2251 + /* 1620 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1623 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1653 + /* 1628 */ MCD_OPC_CheckPredicate, + 95, + 106, + 2, + 0, // Skip to: 2251 + /* 1633 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 98, + 2, + 0, // Skip to: 2251 + /* 1641 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 91, + 2, + 0, // Skip to: 2251 + /* 1648 */ MCD_OPC_Decode, + 128, + 26, + 230, + 1, // Opcode: VRINTZNQh + /* 1653 */ MCD_OPC_FilterValue, + 58, + 81, + 2, + 0, // Skip to: 2251 + /* 1658 */ MCD_OPC_CheckPredicate, + 96, + 76, + 2, + 0, // Skip to: 2251 + /* 1663 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 68, + 2, + 0, // Skip to: 2251 + /* 1671 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 61, + 2, + 0, // Skip to: 2251 + /* 1678 */ MCD_OPC_Decode, + 255, + 25, + 230, + 1, // Opcode: VRINTZNQf + /* 1683 */ MCD_OPC_FilterValue, + 6, + 139, + 0, + 0, // Skip to: 1827 + /* 1688 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1691 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1759 + /* 1696 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1699 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1729 + /* 1704 */ MCD_OPC_CheckPredicate, + 95, + 30, + 2, + 0, // Skip to: 2251 + /* 1709 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 22, + 2, + 0, // Skip to: 2251 + /* 1717 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 15, + 2, + 0, // Skip to: 2251 + /* 1724 */ MCD_OPC_Decode, + 223, + 25, + 229, + 1, // Opcode: VRINTMNDh + /* 1729 */ MCD_OPC_FilterValue, + 58, + 5, + 2, + 0, // Skip to: 2251 + /* 1734 */ MCD_OPC_CheckPredicate, + 96, + 0, + 2, + 0, // Skip to: 2251 + /* 1739 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 248, + 1, + 0, // Skip to: 2251 + /* 1747 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 241, + 1, + 0, // Skip to: 2251 + /* 1754 */ MCD_OPC_Decode, + 222, + 25, + 229, + 1, // Opcode: VRINTMNDf + /* 1759 */ MCD_OPC_FilterValue, + 3, + 231, + 1, + 0, // Skip to: 2251 + /* 1764 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1767 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1797 + /* 1772 */ MCD_OPC_CheckPredicate, + 95, + 218, + 1, + 0, // Skip to: 2251 + /* 1777 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 210, + 1, + 0, // Skip to: 2251 + /* 1785 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 203, + 1, + 0, // Skip to: 2251 + /* 1792 */ MCD_OPC_Decode, + 225, + 25, + 230, + 1, // Opcode: VRINTMNQh + /* 1797 */ MCD_OPC_FilterValue, + 58, + 193, + 1, + 0, // Skip to: 2251 + /* 1802 */ MCD_OPC_CheckPredicate, + 96, + 188, + 1, + 0, // Skip to: 2251 + /* 1807 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 180, + 1, + 0, // Skip to: 2251 + /* 1815 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 173, + 1, + 0, // Skip to: 2251 + /* 1822 */ MCD_OPC_Decode, + 224, + 25, + 230, + 1, // Opcode: VRINTMNQf + /* 1827 */ MCD_OPC_FilterValue, + 7, + 139, + 0, + 0, // Skip to: 1971 + /* 1832 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 1835 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 1903 + /* 1840 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1843 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1873 + /* 1848 */ MCD_OPC_CheckPredicate, + 95, + 142, + 1, + 0, // Skip to: 2251 + /* 1853 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 134, + 1, + 0, // Skip to: 2251 + /* 1861 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 127, + 1, + 0, // Skip to: 2251 + /* 1868 */ MCD_OPC_Decode, + 237, + 25, + 229, + 1, // Opcode: VRINTPNDh + /* 1873 */ MCD_OPC_FilterValue, + 58, + 117, + 1, + 0, // Skip to: 2251 + /* 1878 */ MCD_OPC_CheckPredicate, + 96, + 112, + 1, + 0, // Skip to: 2251 + /* 1883 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 104, + 1, + 0, // Skip to: 2251 + /* 1891 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 97, + 1, + 0, // Skip to: 2251 + /* 1898 */ MCD_OPC_Decode, + 236, + 25, + 229, + 1, // Opcode: VRINTPNDf + /* 1903 */ MCD_OPC_FilterValue, + 3, + 87, + 1, + 0, // Skip to: 2251 + /* 1908 */ MCD_OPC_ExtractField, + 16, + 6, // Inst{21-16} ... + /* 1911 */ MCD_OPC_FilterValue, + 54, + 25, + 0, + 0, // Skip to: 1941 + /* 1916 */ MCD_OPC_CheckPredicate, + 95, + 74, + 1, + 0, // Skip to: 2251 + /* 1921 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 66, + 1, + 0, // Skip to: 2251 + /* 1929 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 59, + 1, + 0, // Skip to: 2251 + /* 1936 */ MCD_OPC_Decode, + 239, + 25, + 230, + 1, // Opcode: VRINTPNQh + /* 1941 */ MCD_OPC_FilterValue, + 58, + 49, + 1, + 0, // Skip to: 2251 + /* 1946 */ MCD_OPC_CheckPredicate, + 96, + 44, + 1, + 0, // Skip to: 2251 + /* 1951 */ MCD_OPC_CheckField, + 23, + 9, + 231, + 3, + 36, + 1, + 0, // Skip to: 2251 + /* 1959 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 29, + 1, + 0, // Skip to: 2251 + /* 1966 */ MCD_OPC_Decode, + 238, + 25, + 230, + 1, // Opcode: VRINTPNQf + /* 1971 */ MCD_OPC_FilterValue, + 15, + 19, + 1, + 0, // Skip to: 2251 + /* 1976 */ MCD_OPC_ExtractField, + 20, + 2, // Inst{21-20} ... + /* 1979 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 2047 + /* 1984 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 1987 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2017 + /* 1992 */ MCD_OPC_CheckPredicate, + 96, + 254, + 0, + 0, // Skip to: 2251 + /* 1997 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 246, + 0, + 0, // Skip to: 2251 + /* 2005 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 239, + 0, + 0, // Skip to: 2251 + /* 2012 */ MCD_OPC_Decode, + 211, + 13, + 200, + 1, // Opcode: NEON_VMAXNMNDf + /* 2017 */ MCD_OPC_FilterValue, + 1, + 229, + 0, + 0, // Skip to: 2251 + /* 2022 */ MCD_OPC_CheckPredicate, + 96, + 224, + 0, + 0, // Skip to: 2251 + /* 2027 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 216, + 0, + 0, // Skip to: 2251 + /* 2035 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 209, + 0, + 0, // Skip to: 2251 + /* 2042 */ MCD_OPC_Decode, + 213, + 13, + 201, + 1, // Opcode: NEON_VMAXNMNQf + /* 2047 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 2115 + /* 2052 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2055 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2085 + /* 2060 */ MCD_OPC_CheckPredicate, + 95, + 186, + 0, + 0, // Skip to: 2251 + /* 2065 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 178, + 0, + 0, // Skip to: 2251 + /* 2073 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 171, + 0, + 0, // Skip to: 2251 + /* 2080 */ MCD_OPC_Decode, + 212, + 13, + 200, + 1, // Opcode: NEON_VMAXNMNDh + /* 2085 */ MCD_OPC_FilterValue, + 1, + 161, + 0, + 0, // Skip to: 2251 + /* 2090 */ MCD_OPC_CheckPredicate, + 95, + 156, + 0, + 0, // Skip to: 2251 + /* 2095 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 148, + 0, + 0, // Skip to: 2251 + /* 2103 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 141, + 0, + 0, // Skip to: 2251 + /* 2110 */ MCD_OPC_Decode, + 214, + 13, + 201, + 1, // Opcode: NEON_VMAXNMNQh + /* 2115 */ MCD_OPC_FilterValue, + 2, + 63, + 0, + 0, // Skip to: 2183 + /* 2120 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2123 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2153 + /* 2128 */ MCD_OPC_CheckPredicate, + 96, + 118, + 0, + 0, // Skip to: 2251 + /* 2133 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 110, + 0, + 0, // Skip to: 2251 + /* 2141 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 103, + 0, + 0, // Skip to: 2251 + /* 2148 */ MCD_OPC_Decode, + 215, + 13, + 200, + 1, // Opcode: NEON_VMINNMNDf + /* 2153 */ MCD_OPC_FilterValue, + 1, + 93, + 0, + 0, // Skip to: 2251 + /* 2158 */ MCD_OPC_CheckPredicate, + 96, + 88, + 0, + 0, // Skip to: 2251 + /* 2163 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 80, + 0, + 0, // Skip to: 2251 + /* 2171 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 73, + 0, + 0, // Skip to: 2251 + /* 2178 */ MCD_OPC_Decode, + 217, + 13, + 201, + 1, // Opcode: NEON_VMINNMNQf + /* 2183 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 2251 + /* 2188 */ MCD_OPC_ExtractField, + 6, + 1, // Inst{6} ... + /* 2191 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2221 + /* 2196 */ MCD_OPC_CheckPredicate, + 95, + 50, + 0, + 0, // Skip to: 2251 + /* 2201 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 42, + 0, + 0, // Skip to: 2251 + /* 2209 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 35, + 0, + 0, // Skip to: 2251 + /* 2216 */ MCD_OPC_Decode, + 216, + 13, + 200, + 1, // Opcode: NEON_VMINNMNDh + /* 2221 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 2251 + /* 2226 */ MCD_OPC_CheckPredicate, + 95, + 20, + 0, + 0, // Skip to: 2251 + /* 2231 */ MCD_OPC_CheckField, + 23, + 9, + 230, + 3, + 12, + 0, + 0, // Skip to: 2251 + /* 2239 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 5, + 0, + 0, // Skip to: 2251 + /* 2246 */ MCD_OPC_Decode, + 218, + 13, + 201, + 1, // Opcode: NEON_VMINNMNQh + /* 2251 */ MCD_OPC_Fail, + 0}; + +static bool getbool(uint64_t b) { return b != 0; } +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { - default: /* llvm_unreachable("Invalid index!");*/ + default: + llvm_unreachable("Invalid index!"); case 0: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0)); case 1: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6Ops)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV6Ops, 1)); case 2: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCRC)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV8Ops, 1) && + checkFeatureRequired(Bits, ARM_FeatureCRC, 1)); case 3: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TEOps)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV5TEOps, 1)); case 4: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV8Ops, 0)); case 5: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV8Ops, 1)); case 6: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV8Ops, 1) && + checkFeatureRequired(Bits, ARM_HasV8_1aOps, 1)); case 7: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_FeatureVirtualization, 1)); case 8: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_FeatureAcquireRelease, 1)); case 9: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_FeatureAcquireRelease, 1) && + checkFeatureRequired(Bits, ARM_FeatureV7Clrex, 1)); case 10: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV4TOps)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV4TOps, 1)); case 11: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV5TOps, 1)); case 12: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureTrustZone)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_FeatureTrustZone, 1)); case 13: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6T2Ops)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV6T2Ops, 1)); case 14: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_4aOps)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV8_4aOps, 1)); case 15: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV7Ops, 1)); case 16: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMP)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV7Ops, 1) && + checkFeatureRequired(Bits, ARM_FeatureMP, 1)); case 17: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_HasV6KOps, 1)); case 18: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDB)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_FeatureDB, 1)); case 19: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureHWDivARM)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_FeatureSB, 1)); case 20: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNaClTrap)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_FeatureHWDivARM, 1)); case 21: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 0) && + checkFeatureRequired(Bits, ARM_FeatureNaClTrap, 1)); case 22: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); + return getbool(checkFeatureRequired(Bits, ARM_HasMVEIntegerOps, 1)); case 23: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps)); + return getbool(checkFeatureRequired(Bits, ARM_HasV8_1MMainlineOps, 1) && + checkFeatureRequired(Bits, ARM_HasMVEIntegerOps, 1)); case 24: - return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCrypto)); + return getbool(checkFeatureRequired(Bits, ARM_HasMVEFloatOps, 1)); case 25: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFP16)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureFPRegs, 1) && + checkFeatureRequired(Bits, ARM_HasV8_1MMainlineOps, 1)); case 26: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureNEON, 1)); case 27: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP2)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureNEON, 1) && + checkFeatureRequired(Bits, ARM_FeatureFullFP16, 1)); case 28: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureNEON, 1) && + checkFeatureRequired(Bits, ARM_HasV8_1aOps, 1)); case 29: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt)); + return getbool(checkFeatureRequired(Bits, ARM_HasV8Ops, 1) && + checkFeatureRequired(Bits, ARM_FeatureAES, 1)); case 30: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureNEON, 1) && + checkFeatureRequired(Bits, ARM_FeatureFP16, 1)); case 31: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6Ops)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureBF16, 1) && + checkFeatureRequired(Bits, ARM_FeatureNEON, 1)); case 32: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MBaselineOps)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureNEON, 1) && + checkFeatureRequired(Bits, ARM_FeatureVFP4_D16_SP, 1)); case 33: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureVFP2_SP, 1)); case 34: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureFPRegs, 1)); case 35: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1)); case 36: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_Feature8MSecExt, 1)); case 37: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_HasV5TOps, 1)); case 38: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_HasV6Ops, 1)); case 39: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_HasV8MBaselineOps, 1)); case 40: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_HasV8Ops, 1) && + checkFeatureRequired(Bits, ARM_HasV8_1aOps, 1)); case 41: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureMClass, 0)); case 42: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_HasV8Ops, 1)); case 43: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_HasV6MOps, 1)); case 44: - return (ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_HasV5TOps, 1) && + checkFeatureRequired(Bits, ARM_FeatureMClass, 0)); case 45: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1)); case 46: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_FeatureMClass, 0)); case 47: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_4aOps)); + return getbool(checkFeatureRequired(Bits, ARM_HasV8_1MMainlineOps, 1)); case 48: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureAcquireRelease, 1)); case 49: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDB)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureAcquireRelease, 1) && + checkFeatureRequired(Bits, ARM_FeatureV7Clrex, 1)); case 50: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureAcquireRelease, 1) && + checkFeatureRequired(Bits, ARM_FeatureV7Clrex, 1) && + checkFeatureRequired(Bits, ARM_FeatureMClass, 0)); case 51: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureDSP, 1) && + checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1)); case 52: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureTrustZone)); + return getbool(checkFeatureRequired(Bits, ARM_Feature8MSecExt, 1)); case 53: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_FeatureDSP, 1)); case 54: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_HasV8Ops, 1)); case 55: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureHWDivThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MBaselineOps)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_HasV8_4aOps, 1)); case 56: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMP)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureV7Clrex, 1)); case 57: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCRC)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureDB, 1)); case 58: - return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && !ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_FeatureSB, 1)); case 59: - return (!ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_FeatureVirtualization, 1)); case 60: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_FeatureTrustZone, 1)); case 61: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP2) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureVirtualization, 1)); case 62: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureMClass, 1)); case 63: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_HasV8_1MMainlineOps, 1) && + checkFeatureRequired(Bits, ARM_FeatureLOB, 1)); case 64: - return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MMainlineOps) && ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_HasV7Ops, 1)); case 65: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP3)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureHWDivThumb, 1) && + checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_HasV8MBaselineOps, 1)); case 66: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_HasV7Ops, 1) && + checkFeatureRequired(Bits, ARM_FeatureMP, 1)); case 67: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFP16)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_HasV8Ops, 1) && + checkFeatureRequired(Bits, ARM_FeatureCRC, 1)); case 68: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP3) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); + return getbool(checkFeatureRequired(Bits, ARM_HasCDEOps, 1) && + checkFeatureRequired(Bits, ARM_FeatureFPRegs, 1)); case 69: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); + return getbool(checkFeatureRequired(Bits, ARM_HasCDEOps, 1) && + checkFeatureRequired(Bits, ARM_HasMVEIntegerOps, 1)); case 70: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps)); + return getbool(checkFeatureRequired(Bits, ARM_HasCDEOps, 1)); case 71: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); + return getbool(checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1) && + checkFeatureRequired(Bits, ARM_HasV8Ops, 0)); case 72: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps)); + return getbool(checkFeatureRequired(Bits, ARM_HasV8Ops, 0) && + checkFeatureRequired(Bits, ARM_ModeThumb, 1) && + checkFeatureRequired(Bits, ARM_FeatureThumb2, 1)); case 73: - return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDotProd)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureFPRegs16, 1)); case 74: - return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); + return getbool(checkFeatureRequired(Bits, ARM_FeatureFullFP16, 1)); case 75: - return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON)); + return getbool(checkFeatureRequired(Bits, ARM_HasV8_1MMainlineOps, 1) && + checkFeatureRequired(Bits, ARM_Feature8MSecExt, 1)); + case 76: + return getbool(checkFeatureRequired(Bits, ARM_FeatureVFP4_D16_SP, 1)); + case 77: + return getbool(checkFeatureRequired(Bits, ARM_HasV8MMainlineOps, 1) && + checkFeatureRequired(Bits, ARM_Feature8MSecExt, 1)); + case 78: + return getbool(checkFeatureRequired(Bits, ARM_HasV8_1MMainlineOps, 1) && + checkFeatureRequired(Bits, ARM_FeatureFPRegs, 1)); + case 79: + return getbool(checkFeatureRequired(Bits, ARM_FeatureVFP3_D16_SP, 1)); + case 80: + return getbool(checkFeatureRequired(Bits, ARM_FeatureFP16, 1)); + case 81: + return getbool(checkFeatureRequired(Bits, ARM_FeatureFPARMv8_D16_SP, 1)); + case 82: + return getbool(checkFeatureRequired(Bits, ARM_FeatureVFP2_SP, 1) && + checkFeatureRequired(Bits, ARM_FeatureFP64, 1)); + case 83: + return getbool(checkFeatureRequired(Bits, ARM_FeatureVFP4_D16_SP, 1) && + checkFeatureRequired(Bits, ARM_FeatureFP64, 1)); + case 84: + return getbool(checkFeatureRequired(Bits, ARM_FeatureVFP3_D16_SP, 1) && + checkFeatureRequired(Bits, ARM_FeatureFP64, 1)); + case 85: + return getbool(checkFeatureRequired(Bits, ARM_FeatureFPRegs64, 1)); + case 86: + return getbool(checkFeatureRequired(Bits, ARM_FeatureFPARMv8_D16_SP, 1) && + checkFeatureRequired(Bits, ARM_FeatureFP64, 1)); + case 87: + return getbool(checkFeatureRequired(Bits, ARM_FeatureFPARMv8_D16_SP, 1) && + checkFeatureRequired(Bits, ARM_HasV8_3aOps, 1)); + case 88: + return getbool(checkFeatureRequired(Bits, ARM_FeatureNEON, 1) && + checkFeatureRequired(Bits, ARM_HasV8_3aOps, 1) && + checkFeatureRequired(Bits, ARM_FeatureFullFP16, 1)); + case 89: + return getbool(checkFeatureRequired(Bits, ARM_FeatureNEON, 1) && + checkFeatureRequired(Bits, ARM_HasV8_3aOps, 1)); + case 90: + return getbool(checkFeatureRequired(Bits, ARM_FeatureNEON, 1) && + checkFeatureRequired(Bits, ARM_FeatureFP16FML, 1)); + case 91: + return getbool(checkFeatureRequired(Bits, ARM_FeatureBF16, 1)); + case 92: + return getbool(checkFeatureRequired(Bits, ARM_FeatureMatMulInt8, 1)); + case 93: + return getbool(checkFeatureRequired(Bits, ARM_FeatureDotProd, 1)); + case 94: + return getbool(checkFeatureRequired(Bits, ARM_HasV8Ops, 1) && + checkFeatureRequired(Bits, ARM_FeatureSHA2, 1)); + case 95: + return getbool(checkFeatureRequired(Bits, ARM_HasV8Ops, 1) && + checkFeatureRequired(Bits, ARM_FeatureNEON, 1) && + checkFeatureRequired(Bits, ARM_FeatureFullFP16, 1)); + case 96: + return getbool(checkFeatureRequired(Bits, ARM_HasV8Ops, 1) && + checkFeatureRequired(Bits, ARM_FeatureNEON, 1)); } } -#define DecodeToMCInst(fname, fieldname, InsnType) \ -static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, bool *Decoder) \ -{ \ - InsnType tmp; \ - /* printf("Idx = %u\n", Idx); */\ - switch (Idx) { \ - default: /* llvm_unreachable("Invalid index!");*/ \ - case 0: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 1: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 7) << 5; \ - if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 2: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 2) << 5; \ - tmp |= fieldname(insn, 8, 4) << 8; \ - if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 3: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 2) << 5; \ - tmp |= fieldname(insn, 8, 4) << 8; \ - if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 4: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 5: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 6: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 7: \ - if (!Check(&S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 8: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 9: \ - if (!Check(&S, DecodeCPSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 10: \ - tmp = fieldname(insn, 9, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 11: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 12: \ - if (!Check(&S, DecodeQADDInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 13: \ - if (!Check(&S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 14: \ - if (!Check(&S, DecodeSwap(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 15: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 8, 12) << 4; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 16: \ - if (!Check(&S, DecodeTSTInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 17: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 7) << 5; \ - if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 18: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 2) << 5; \ - tmp |= fieldname(insn, 8, 4) << 8; \ - if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 19: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 20: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 21: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 22: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 23: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 24: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 25: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 5; \ - if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 26: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 27: \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 5; \ - if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 28: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 29: \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 30: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 31: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 32: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 33: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 7) << 5; \ - if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 34: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 35: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 36: \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 37: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 2) << 5; \ - tmp |= fieldname(insn, 8, 4) << 8; \ - if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 38: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 39: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 40: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 41: \ - if (!Check(&S, DecodeDoubleRegStore(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 42: \ - if (!Check(&S, DecodeDoubleRegLoad(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 43: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 23, 1) << 4; \ - if (!Check(&S, DecodePostIdxReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 44: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 8, 4) << 4; \ - tmp |= fieldname(insn, 23, 1) << 8; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 45: \ - if (!Check(&S, DecodeLDR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 46: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 8, 4) << 4; \ - tmp |= fieldname(insn, 23, 1) << 8; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 47: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 12); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 48: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 12) << 0; \ - tmp |= fieldname(insn, 22, 2) << 12; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 49: \ - if (!Check(&S, DecodeArmMOVTWInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 50: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 12); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 51: \ - return S; \ - case 52: \ - if (!Check(&S, DecodeHINTInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 53: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 12); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 54: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 12); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 55: \ - if (!Check(&S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 56: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 12) << 0; \ - tmp |= fieldname(insn, 16, 4) << 13; \ - tmp |= fieldname(insn, 23, 1) << 12; \ - if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 57: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 12) << 0; \ - tmp |= fieldname(insn, 16, 4) << 13; \ - tmp |= fieldname(insn, 23, 1) << 12; \ - if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 58: \ - if (!Check(&S, DecodeSTRPreImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 59: \ - if (!Check(&S, DecodeLDRPreImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 60: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 12) << 0; \ - tmp |= fieldname(insn, 16, 4) << 13; \ - tmp |= fieldname(insn, 23, 1) << 12; \ - if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 61: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 62: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 63: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 7) << 5; \ - tmp |= fieldname(insn, 16, 4) << 13; \ - tmp |= fieldname(insn, 23, 1) << 12; \ - if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 64: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 7) << 5; \ - tmp |= fieldname(insn, 16, 4) << 13; \ - tmp |= fieldname(insn, 23, 1) << 12; \ - if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 65: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 66: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 7, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 67: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 68: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 69: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 70: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 71: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 72: \ - if (!Check(&S, DecodeSTRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 73: \ - if (!Check(&S, DecodeLDRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 74: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 6, 1) << 5; \ - tmp |= fieldname(insn, 7, 5) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 75: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 76: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 7, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 77: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 7) << 5; \ - tmp |= fieldname(insn, 16, 4) << 13; \ - tmp |= fieldname(insn, 23, 1) << 12; \ - if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 78: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 5; \ - if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 79: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 5; \ - if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 80: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 81: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 82: \ - if (!Check(&S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 83: \ - tmp = fieldname(insn, 0, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 84: \ - if (!Check(&S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 85: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 24) << 1; \ - tmp |= fieldname(insn, 24, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 86: \ - if (!Check(&S, DecoderForMRRC2AndMCRR2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 87: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 4, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 88: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 4, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 89: \ - tmp = fieldname(insn, 0, 24); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 90: \ - if (!Check(&S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 91: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 92: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 93: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 94: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 95: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 96: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 97: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 98: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 99: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 100: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 101: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 102: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 103: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 104: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 105: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 106: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 107: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 1) << 0; \ - tmp |= fieldname(insn, 5, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 108: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 1) << 0; \ - tmp |= fieldname(insn, 5, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 109: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 1) << 0; \ - tmp |= fieldname(insn, 5, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 110: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 1) << 0; \ - tmp |= fieldname(insn, 5, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 111: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 1) << 0; \ - tmp |= fieldname(insn, 5, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 112: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 1) << 0; \ - tmp |= fieldname(insn, 5, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 113: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 114: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 115: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 116: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 117: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 118: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 119: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 120: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 9, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 121: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 122: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 123: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 10, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 124: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 9, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 125: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 126: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 127: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 128: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 129: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 130: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 131: \ - if (!Check(&S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 132: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 133: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 134: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 135: \ - if (!Check(&S, DecodeTBLInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 136: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 137: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 138: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 17, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 139: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 19, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 140: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 141: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 17, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 142: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 143: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 144: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 145: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 146: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 147: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 148: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 149: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 150: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 151: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 152: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 153: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 154: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 155: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 156: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 157: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 158: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 159: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 160: \ - if (!Check(&S, DecodeVCVTD(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 161: \ - if (!Check(&S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 162: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 163: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 164: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 165: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 166: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 167: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 168: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 169: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 170: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 171: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 172: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 173: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 174: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 175: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 176: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 177: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 178: \ - if (!Check(&S, DecodeVCVTQ(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 179: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 180: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 181: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 182: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 183: \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 184: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 185: \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 6, 1) << 0; \ - tmp |= fieldname(insn, 21, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 186: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 6, 1) << 0; \ - tmp |= fieldname(insn, 21, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 187: \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 2) << 0; \ - tmp |= fieldname(insn, 21, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 188: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 2) << 0; \ - tmp |= fieldname(insn, 21, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 189: \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 190: \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 191: \ - if (!Check(&S, DecodeVLDST4Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 192: \ - if (!Check(&S, DecodeVST1LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 193: \ - if (!Check(&S, DecodeVLD1LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 194: \ - if (!Check(&S, DecodeVST2LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 195: \ - if (!Check(&S, DecodeVLD2LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 196: \ - if (!Check(&S, DecodeVLDST1Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 197: \ - if (!Check(&S, DecodeVST3LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 198: \ - if (!Check(&S, DecodeVLD3LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 199: \ - if (!Check(&S, DecodeVLDST2Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 200: \ - if (!Check(&S, DecodeVST4LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 201: \ - if (!Check(&S, DecodeVLD4LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 202: \ - if (!Check(&S, DecodeVLDST3Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 203: \ - if (!Check(&S, DecodeVLD1DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 204: \ - if (!Check(&S, DecodeVLD2DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 205: \ - if (!Check(&S, DecodeVLD3DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 206: \ - if (!Check(&S, DecodeVLD4DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 207: \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 208: \ - tmp = fieldname(insn, 8, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 209: \ - if (!Check(&S, DecodeThumbAddSPReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 210: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 3) << 0; \ - tmp |= fieldname(insn, 7, 1) << 3; \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 3) << 0; \ - tmp |= fieldname(insn, 7, 1) << 3; \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 211: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 3) << 0; \ - tmp |= fieldname(insn, 7, 1) << 3; \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 212: \ - tmp = fieldname(insn, 3, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 213: \ - tmp = fieldname(insn, 3, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 214: \ - tmp = fieldname(insn, 8, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 8); \ - if (!Check(&S, DecodeThumbAddrModePC(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 215: \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 6); \ - if (!Check(&S, DecodeThumbAddrModeRR(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 216: \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 8); \ - if (!Check(&S, DecodeThumbAddrModeIS(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 217: \ - tmp = fieldname(insn, 8, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 8); \ - if (!Check(&S, DecodeThumbAddrModeSP(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 218: \ - if (!Check(&S, DecodeThumbAddSpecialReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 219: \ - if (!Check(&S, DecodeThumbAddSPImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 220: \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 5) << 0; \ - tmp |= fieldname(insn, 9, 1) << 5; \ - if (!Check(&S, DecodeThumbCmpBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 221: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 8, 1) << 14; \ - if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 222: \ - tmp = fieldname(insn, 3, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 223: \ - if (!Check(&S, DecodeThumbCPS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 224: \ - tmp = fieldname(insn, 0, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 225: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 8, 1) << 15; \ - if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 226: \ - tmp = fieldname(insn, 0, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 227: \ - tmp = fieldname(insn, 4, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 228: \ - tmp = fieldname(insn, 8, 3); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 8); \ - if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 229: \ - tmp = fieldname(insn, 8, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 8); \ - if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 230: \ - tmp = fieldname(insn, 0, 8); \ - if (!Check(&S, DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 231: \ - tmp = fieldname(insn, 0, 11); \ - if (!Check(&S, DecodeThumbBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 232: \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 10) << 1; \ - tmp |= fieldname(insn, 11, 1) << 21; \ - tmp |= fieldname(insn, 13, 1) << 22; \ - tmp |= fieldname(insn, 16, 10) << 11; \ - tmp |= fieldname(insn, 26, 1) << 23; \ - if (!Check(&S, DecodeThumbBLXOffset(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 233: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 11) << 0; \ - tmp |= fieldname(insn, 11, 1) << 21; \ - tmp |= fieldname(insn, 13, 1) << 22; \ - tmp |= fieldname(insn, 16, 10) << 11; \ - tmp |= fieldname(insn, 26, 1) << 23; \ - if (!Check(&S, DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 234: \ - if (!Check(&S, DecodeIT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 235: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 13) << 0; \ - tmp |= fieldname(insn, 14, 1) << 14; \ - if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 236: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 237: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 238: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 4, 4) << 5; \ - tmp |= fieldname(insn, 12, 3) << 9; \ - if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 239: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 240: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 4, 4) << 5; \ - tmp |= fieldname(insn, 12, 3) << 9; \ - if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 241: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 242: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 4, 4) << 5; \ - tmp |= fieldname(insn, 12, 3) << 9; \ - if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 243: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 13) << 0; \ - tmp |= fieldname(insn, 14, 1) << 14; \ - if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 244: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 245: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 246: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 16, 4) << 8; \ - if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 247: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 248: \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 249: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 250: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 16, 4) << 8; \ - if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 251: \ - if (!Check(&S, DecodeThumbTableBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 252: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 253: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 16, 4) << 9; \ - tmp |= fieldname(insn, 23, 1) << 8; \ - if (!Check(&S, DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 254: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 255: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 256: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 6, 2) << 0; \ - tmp |= fieldname(insn, 12, 3) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 257: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 6, 2) << 0; \ - tmp |= fieldname(insn, 12, 3) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 258: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 23, 1) << 8; \ - if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 259: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 23, 1) << 8; \ - if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 260: \ - if (!Check(&S, DecodeT2STRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 261: \ - if (!Check(&S, DecodeT2LDRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 262: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 4, 4) << 5; \ - tmp |= fieldname(insn, 12, 3) << 9; \ - if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 263: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 12, 3) << 8; \ - tmp |= fieldname(insn, 26, 1) << 11; \ - if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 264: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 12, 3) << 8; \ - tmp |= fieldname(insn, 26, 1) << 11; \ - if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 265: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 12, 3) << 8; \ - tmp |= fieldname(insn, 26, 1) << 11; \ - if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 266: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 12, 3) << 8; \ - tmp |= fieldname(insn, 26, 1) << 11; \ - if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 20, 1); \ - if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 267: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 12, 3) << 8; \ - tmp |= fieldname(insn, 26, 1) << 11; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 268: \ - if (!Check(&S, DecodeT2Adr(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 269: \ - if (!Check(&S, DecodeT2MOVTWInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 270: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 271: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 6, 2) << 0; \ - tmp |= fieldname(insn, 12, 3) << 2; \ - tmp |= fieldname(insn, 21, 1) << 5; \ - if (!Check(&S, DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 272: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 6, 2) << 0; \ - tmp |= fieldname(insn, 12, 3) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 273: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 5) << 5; \ - tmp |= fieldname(insn, 6, 2) << 0; \ - tmp |= fieldname(insn, 12, 3) << 2; \ - if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 274: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 5) << 5; \ - tmp |= fieldname(insn, 6, 2) << 0; \ - tmp |= fieldname(insn, 12, 3) << 2; \ - if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 275: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 276: \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 277: \ - if (!Check(&S, DecodeT2CPSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 278: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 279: \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 4) << 0; \ - tmp |= fieldname(insn, 20, 1) << 4; \ - if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 280: \ - tmp = 0; \ - tmp |= fieldname(insn, 4, 1) << 4; \ - tmp |= fieldname(insn, 8, 4) << 0; \ - tmp |= fieldname(insn, 20, 1) << 5; \ - if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 281: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 4, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - tmp |= fieldname(insn, 20, 1) << 5; \ - if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 282: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 12) << 0; \ - tmp |= fieldname(insn, 16, 4) << 12; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 283: \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 284: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 10, 2) << 10; \ - if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 285: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 8); \ - if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 286: \ - if (!Check(&S, DecodeThumb2BCCInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 287: \ - if (!Check(&S, DecodeT2BInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 288: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 2; \ - tmp |= fieldname(insn, 4, 2) << 0; \ - tmp |= fieldname(insn, 16, 4) << 6; \ - if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 289: \ - if (!Check(&S, DecodeT2LdStPre(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 290: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 16, 4) << 9; \ - if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 291: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 9, 1) << 8; \ - tmp |= fieldname(insn, 16, 4) << 9; \ - if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 292: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 12) << 0; \ - tmp |= fieldname(insn, 16, 4) << 13; \ - if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 293: \ - if (!Check(&S, DecodeT2LoadShift(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 294: \ - if (!Check(&S, DecodeT2LoadImm8(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 295: \ - if (!Check(&S, DecodeT2LoadT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 296: \ - if (!Check(&S, DecodeT2LoadImm12(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 297: \ - if (!Check(&S, DecodeT2LoadLabel(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 298: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 299: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 4, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 300: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 4, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 301: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 302: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 303: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 304: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 305: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 306: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 2; \ - tmp |= fieldname(insn, 4, 2) << 0; \ - tmp |= fieldname(insn, 16, 4) << 6; \ - if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 307: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 9, 1) << 8; \ - tmp |= fieldname(insn, 16, 4) << 9; \ - if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 308: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 12) << 0; \ - tmp |= fieldname(insn, 16, 4) << 13; \ - if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 309: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 310: \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 4, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 311: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 4); \ - if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 4, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 312: \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 313: \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 314: \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 315: \ - tmp = fieldname(insn, 8, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 316: \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 317: \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 3, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 3); \ - if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 318: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 16, 4) << 9; \ - tmp |= fieldname(insn, 23, 1) << 8; \ - if (!Check(&S, DecodeAddrMode5FP16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 319: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 320: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 321: \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 322: \ - if (!Check(&S, DecodeVMOVSRR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 323: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 12, 4) << 9; \ - tmp |= fieldname(insn, 22, 1) << 8; \ - if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 324: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 16, 4) << 9; \ - tmp |= fieldname(insn, 23, 1) << 8; \ - if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 325: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 326: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 327: \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 328: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 329: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 7) << 1; \ - tmp |= fieldname(insn, 12, 4) << 8; \ - tmp |= fieldname(insn, 22, 1) << 12; \ - if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 330: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 7) << 1; \ - tmp |= fieldname(insn, 12, 4) << 8; \ - if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 331: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 16, 4) << 9; \ - tmp |= fieldname(insn, 23, 1) << 8; \ - if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 332: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 333: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 334: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 335: \ - if (!Check(&S, DecodeVMOVRRS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 336: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 337: \ - tmp = fieldname(insn, 12, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 338: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 339: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 8) << 0; \ - tmp |= fieldname(insn, 12, 4) << 9; \ - tmp |= fieldname(insn, 22, 1) << 8; \ - if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 340: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 7) << 1; \ - tmp |= fieldname(insn, 12, 4) << 8; \ - tmp |= fieldname(insn, 22, 1) << 12; \ - if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 341: \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 7) << 1; \ - tmp |= fieldname(insn, 12, 4) << 8; \ - if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 342: \ - if (!Check(&S, DecodeForVMRSandVMSR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 343: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 16, 4) << 4; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 344: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 345: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 346: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 347: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 348: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 349: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 350: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 16, 4) << 4; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 351: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 352: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 353: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 16, 4) << 4; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 354: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 355: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 356: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 357: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 28, 4); \ - if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 358: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 24, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 359: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 23, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 360: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 20, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 361: \ - if (!Check(&S, DecodeNEONComplexLane64Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 362: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 24, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 363: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 23, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 364: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - tmp |= fieldname(insn, 22, 1) << 4; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 4; \ - tmp |= fieldname(insn, 16, 4) << 0; \ - if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 4); \ - if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 5, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 20, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 365: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 366: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 367: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 368: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 0; \ - tmp |= fieldname(insn, 16, 4) << 1; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 1; \ - tmp |= fieldname(insn, 5, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - case 369: \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 4) << 1; \ - tmp |= fieldname(insn, 22, 1) << 0; \ - if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 4) << 0; \ - tmp |= fieldname(insn, 5, 1) << 4; \ - if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ - return S; \ - } \ -} +#define DecodeToMCInst(fname, fieldname, InsnType) \ + static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, \ + MCInst *MI, uint64_t Address, bool *Decoder) { \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + llvm_unreachable("Invalid index!"); \ + case 0: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 1: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + if (DecodeSORegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 2: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (DecodeSORegRegOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 3: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (DecodeSORegRegOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 5: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 6: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 7: \ + if (DecodeAddrMode3Instruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 8: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 9: \ + if (DecodeCPSInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 10: \ + tmp = fieldname(insn, 9, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 11: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 12: \ + if (DecodeQADDInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 13: \ + if (DecodeSMLAInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 14: \ + if (DecodeSwap(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 15: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 8, 12) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 16: \ + if (DecodeTSTInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + if (DecodeSORegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (DecodeSORegRegOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 21: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (DecodeBankedReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 26: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeMSRMask(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 27: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (DecodeBankedReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 31: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodetcGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodetcGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + if (DecodeSORegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 34: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 35: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 37: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (DecodeSORegRegOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 41: \ + if (DecodeDoubleRegStore(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 42: \ + if (DecodeDoubleRegLoad(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 23, 1) << 4; \ + if (DecodePostIdxReg(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 8, 4) << 4; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 45: \ + if (DecodeLDR(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 46: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 8, 4) << 4; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 47: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 48: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 22, 2) << 12; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 49: \ + if (DecodeArmMOVTWInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 50: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 51: \ + return S; \ + case 52: \ + if (DecodeHINTInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 53: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeMSRMask(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 55: \ + if (DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 57: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 58: \ + if (DecodeSTRPreImm(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 59: \ + if (DecodeLDRPreImm(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 60: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 61: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeMemBarrierOption(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 62: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (DecodeSORegMemOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 64: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (DecodeSORegMemOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 65: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 66: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 68: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 69: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 70: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 72: \ + if (DecodeSTRPreReg(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 73: \ + if (DecodeLDRPreReg(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 74: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 5; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 75: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 76: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 77: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (DecodeSORegMemOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 78: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 5; \ + if (DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 79: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 5; \ + if (DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 80: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 82: \ + if (DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 83: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 84: \ + if (DecodeBranchImmInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 85: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 24) << 1; \ + tmp |= fieldname(insn, 24, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 86: \ + if (DecoderForMRRC2AndMCRR2(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 87: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 88: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 89: \ + tmp = fieldname(insn, 0, 24); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 90: \ + if (DecodeCopMemInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 91: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 92: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 93: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 94: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 95: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 96: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 97: \ + if (DecodeMveVCTP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 98: \ + if (DecodeMVEOverlappingLongShift(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 99: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 100: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (DecodeLongShiftOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 101: \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 3) << 1; \ + if (DecodetGPROddRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 3) << 1; \ + if (DecodetGPROddRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (DecodeLongShiftOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 102: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 103: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 23, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 104: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 16, 4) << 3; \ + if (DecodeMveAddrModeRQ(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 105: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 3) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeTAddrModeImm7(MI, tmp, Address, Decoder, 0) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 106: \ + tmp = fieldname(insn, 16, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeT2Imm7(MI, tmp, Address, Decoder, 0) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 107: \ + if (DecodeMVE_MEM_1_pre(MI, tmp, Address, Decoder, 0) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 108: \ + if (DecodeMVEVMOVQtoDReg(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 109: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 3) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeTAddrModeImm7(MI, tmp, Address, Decoder, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 110: \ + if (DecodeMVEVMOVDRegtoQ(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 111: \ + tmp = fieldname(insn, 16, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeT2Imm7(MI, tmp, Address, Decoder, 1) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 112: \ + if (DecodeMVE_MEM_1_pre(MI, tmp, Address, Decoder, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 113: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 114: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 115: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeT2AddrModeImm7(MI, tmp, Address, Decoder, 0, 0) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 116: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 17, 3) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeMveAddrModeQ(MI, tmp, Address, Decoder, 2) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 117: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeT2AddrModeImm7(MI, tmp, Address, Decoder, 1, 0) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 118: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 119: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 120: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeT2Imm7(MI, tmp, Address, Decoder, 0) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 121: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 122: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 123: \ + if (DecodeMVE_MEM_2_pre(MI, tmp, Address, Decoder, 0) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 124: \ + if (DecodeMVE_MEM_3_pre(MI, tmp, Address, Decoder, 2) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 125: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeT2Imm7(MI, tmp, Address, Decoder, 1) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 126: \ + if (DecodeMVE_MEM_2_pre(MI, tmp, Address, Decoder, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 127: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 128: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 129: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeT2AddrModeImm7(MI, tmp, Address, Decoder, 2, 0) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 130: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 17, 3) << 8; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeMveAddrModeQ(MI, tmp, Address, Decoder, 3) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 131: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 7) << 0; \ + tmp |= fieldname(insn, 23, 1) << 7; \ + if (DecodeT2Imm7(MI, tmp, Address, Decoder, 2) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 132: \ + if (DecodeMVE_MEM_2_pre(MI, tmp, Address, Decoder, 2) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 133: \ + if (DecodeMVE_MEM_3_pre(MI, tmp, Address, Decoder, 3) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 134: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 135: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 16, 1) << 2; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 136: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 16, 1) << 3; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 137: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 138: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 16, 1) << 2; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 139: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 16, 1) << 3; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 140: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 141: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 142: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 143: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 144: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 12, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 145: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 146: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 147: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 148: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 149: \ + if (DecodeMVEVCMP(MI, tmp, Address, Decoder, false, \ + DecodeRestrictedIPredicateOperand) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 150: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVPTMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 1); \ + if (DecodeRestrictedIPredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 151: \ + if (DecodeMVEVCMP(MI, tmp, Address, Decoder, false, \ + DecodeRestrictedUPredicateOperand) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 152: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVPTMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 1); \ + if (DecodeRestrictedUPredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 153: \ + if (DecodeMVEVCMP(MI, tmp, Address, Decoder, false, \ + DecodeRestrictedSPredicateOperand) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 154: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVPTMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 1; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + if (DecodeRestrictedSPredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 155: \ + if (DecodeMVEVCMP(MI, tmp, Address, Decoder, true, \ + DecodeRestrictedIPredicateOperand) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 156: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVPTMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 1); \ + if (DecodeRestrictedIPredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 157: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + if (DecodePowerTwoOperand(MI, tmp, Address, Decoder, 0, 3) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 158: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3) << 1; \ + if (DecodetGPROddRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + if (DecodePowerTwoOperand(MI, tmp, Address, Decoder, 0, 3) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 159: \ + if (DecodeMVEVCMP(MI, tmp, Address, Decoder, true, \ + DecodeRestrictedUPredicateOperand) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 160: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVPTMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 1); \ + if (DecodeRestrictedUPredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 161: \ + if (DecodeMVEVCMP(MI, tmp, Address, Decoder, true, \ + DecodeRestrictedSPredicateOperand) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 162: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVPTMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + if (DecodeRestrictedSPredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 163: \ + if (DecodeMVEVADCInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 164: \ + if (DecodeMVEVCMP(MI, tmp, Address, Decoder, false, \ + DecodeRestrictedFPPredicateOperand) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 165: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVPTMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 1) << 1; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 12, 1) << 2; \ + if (DecodeRestrictedFPPredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 166: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 167: \ + if (DecodeMVEVCMP(MI, tmp, Address, Decoder, true, \ + DecodeRestrictedFPPredicateOperand) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 168: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVPTMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 12, 1) << 2; \ + if (DecodeRestrictedFPPredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 169: \ + if (DecodeMVEVPNOT(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 170: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVPTMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 171: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 172: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 173: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (DecodetGPROddRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 174: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 175: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (DecodetGPROddRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (DecodetGPROddRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 176: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 177: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 178: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (DecodetGPROddRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 179: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 180: \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (DecodetGPROddRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3) << 1; \ + if (DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 3) << 1; \ + if (DecodetGPROddRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 181: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 182: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeShiftRight8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 183: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeShiftRight16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 184: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 185: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 186: \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeLongShiftOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 187: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + tmp |= fieldname(insn, 17, 3) << 0; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 188: \ + if (DecodeMVEModImmInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 189: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 9, 2) << 9; \ + tmp |= fieldname(insn, 16, 3) << 4; \ + tmp |= fieldname(insn, 28, 1) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 190: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 9, 1) << 9; \ + tmp |= fieldname(insn, 16, 3) << 4; \ + tmp |= fieldname(insn, 28, 1) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 191: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeShiftRight8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 192: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 193: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeShiftRight16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 194: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 195: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeShiftRight32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 196: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeShiftRight32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 197: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 198: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 13, 3) << 0; \ + tmp |= fieldname(insn, 22, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 3) << 0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 199: \ + if (DecodeMVEVCVTt1fp(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 200: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 201: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 202: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 203: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 204: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 205: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 206: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 207: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 208: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 209: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 210: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 211: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 212: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 213: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 214: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 215: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 216: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 217: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 218: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 219: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 220: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 221: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 222: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 223: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 224: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 225: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 226: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 227: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 228: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 229: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 230: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 231: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 232: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 233: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 234: \ + if (DecodeVSHLMaxInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 235: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 236: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 237: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 238: \ + if (DecodeTBLInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 239: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 240: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 241: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 242: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 19, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 243: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 244: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 245: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeShiftRight8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 246: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeShiftRight16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 247: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeShiftRight32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 248: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeShiftRight8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 249: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeShiftRight16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 250: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeShiftRight32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 251: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 252: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 253: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 254: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 255: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 256: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 257: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeShiftRight8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 258: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeShiftRight16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 259: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeShiftRight32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 260: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 261: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 262: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 263: \ + if (DecodeVCVTD(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 264: \ + if (DecodeVMOVModImmInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 265: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeShiftRight64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 266: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeShiftRight64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 267: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 268: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 269: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeShiftRight8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 270: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeShiftRight16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 271: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeShiftRight32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 272: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (DecodeShiftRight8Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 273: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeShiftRight16Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 274: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeShiftRight32Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 275: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 276: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 277: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 278: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 279: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 280: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 281: \ + if (DecodeVCVTQ(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 282: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeShiftRight64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 283: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeShiftRight64Imm(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 284: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 285: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 286: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 287: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 288: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 289: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 290: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 291: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 292: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 293: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 294: \ + if (DecodeVLDST4Instruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 295: \ + if (DecodeVST1LN(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 296: \ + if (DecodeVLD1LN(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 297: \ + if (DecodeVST2LN(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 298: \ + if (DecodeVLD2LN(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 299: \ + if (DecodeVLDST1Instruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 300: \ + if (DecodeVST3LN(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 301: \ + if (DecodeVLD3LN(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 302: \ + if (DecodeVLDST2Instruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 303: \ + if (DecodeVST4LN(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 304: \ + if (DecodeVLD4LN(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 305: \ + if (DecodeVLDST3Instruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 306: \ + if (DecodeVLD1DupInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 307: \ + if (DecodeVLD2DupInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 308: \ + if (DecodeVLD3DupInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 309: \ + if (DecodeVLD4DupInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 310: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 311: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 312: \ + if (DecodeThumbAddSPReg(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 313: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 314: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 315: \ + tmp = fieldname(insn, 3, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 316: \ + tmp = fieldname(insn, 3, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 317: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (DecodeThumbAddrModePC(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 318: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 6); \ + if (DecodeThumbAddrModeRR(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 319: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 8); \ + if (DecodeThumbAddrModeIS(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 320: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (DecodeThumbAddrModeSP(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 321: \ + if (DecodeThumbAddSpecialReg(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 322: \ + if (DecodeThumbAddSPImm(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 323: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 5) << 0; \ + tmp |= fieldname(insn, 9, 1) << 5; \ + if (DecodeThumbCmpBROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 324: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 8, 1) << 14; \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 325: \ + tmp = fieldname(insn, 3, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 326: \ + if (DecodeThumbCPS(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 327: \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 328: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 8, 1) << 15; \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 329: \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 330: \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 331: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 332: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 333: \ + tmp = fieldname(insn, 0, 8); \ + if (DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 334: \ + tmp = fieldname(insn, 0, 11); \ + if (DecodeThumbBROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 335: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + tmp |= fieldname(insn, 11, 1) << 21; \ + tmp |= fieldname(insn, 13, 1) << 22; \ + tmp |= fieldname(insn, 16, 10) << 11; \ + tmp |= fieldname(insn, 26, 1) << 23; \ + if (DecodeThumbBLXOffset(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 336: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 11) << 0; \ + tmp |= fieldname(insn, 11, 1) << 21; \ + tmp |= fieldname(insn, 13, 1) << 22; \ + tmp |= fieldname(insn, 16, 10) << 11; \ + tmp |= fieldname(insn, 26, 1) << 23; \ + if (DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 337: \ + if (DecodeIT(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 338: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 13) << 0; \ + tmp |= fieldname(insn, 14, 1) << 14; \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 339: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 13) << 0; \ + tmp |= fieldname(insn, 14, 2) << 14; \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 340: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 341: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 342: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (DecodeSORegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 343: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 344: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (DecodeSORegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 345: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 346: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (DecodeSORegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 347: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 348: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (DecodeSORegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 349: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 13) << 0; \ + tmp |= fieldname(insn, 14, 1) << 14; \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 350: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 351: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 352: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + if (DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 353: \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 354: \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 355: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 356: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + if (DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 357: \ + if (DecodeThumbTableBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 358: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 359: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 360: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 361: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 362: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 363: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRwithZRnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRwithZRnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodePredNoALOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 364: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 365: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (DecodeT2Imm8S4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 366: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAddrMode7Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (DecodeT2Imm8S4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 367: \ + if (DecodeT2STRDPreInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 368: \ + if (DecodeT2LDRDPreInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 369: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (DecodeSORegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 370: \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (DecodeT2SOImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 371: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (DecodeT2SOImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 372: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (DecodeT2SOImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 373: \ + if (DecodeT2AddSubSPImm(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 374: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (DecodeT2SOImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 375: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (DecodeT2SOImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 1); \ + if (DecodeCCOutOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 376: \ + if (DecodeT2Adr(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 377: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 378: \ + if (DecodeT2MOVTWInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 379: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 380: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + tmp |= fieldname(insn, 21, 1) << 5; \ + if (DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 381: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 382: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 5; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 383: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 5; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 384: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 385: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 386: \ + if (DecodeT2CPSInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 387: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 388: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 12; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 389: \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 390: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 4; \ + if (DecodeMSRMask(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 391: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 5; \ + if (DecodeBankedReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 392: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 10, 2) << 10; \ + if (DecodeMSRMask(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 393: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 5; \ + if (DecodeBankedReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 394: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + if (DecodeMSRMask(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 395: \ + if (DecodeThumb2BCCInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 396: \ + if (DecodeLOLoop(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 397: \ + tmp = fieldname(insn, 23, 4); \ + if (DecodeBFLabelOperand(MI, tmp, Address, Decoder, false, false, false, \ + 4) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 16, 7) << 11; \ + if (DecodeBFLabelOperand(MI, tmp, Address, Decoder, true, false, true, \ + 18) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 398: \ + tmp = fieldname(insn, 23, 4); \ + if (DecodeBFLabelOperand(MI, tmp, Address, Decoder, false, false, false, \ + 4) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 16, 1) << 11; \ + if (DecodeBFLabelOperand(MI, tmp, Address, Decoder, true, false, true, \ + 12) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 1); \ + if (DecodeBFAfterTargetOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 4); \ + if (DecodePredNoALOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 399: \ + tmp = fieldname(insn, 23, 4); \ + if (DecodeBFLabelOperand(MI, tmp, Address, Decoder, false, false, false, \ + 4) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + tmp |= fieldname(insn, 11, 1) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + if (DecodeBFLabelOperand(MI, tmp, Address, Decoder, true, false, true, \ + 16) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 400: \ + tmp = fieldname(insn, 23, 4); \ + if (DecodeBFLabelOperand(MI, tmp, Address, Decoder, false, false, false, \ + 4) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 401: \ + if (DecodeT2BInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 402: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 2; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 16, 4) << 6; \ + if (DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 403: \ + if (DecodeT2LdStPre(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 404: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + if (DecodeT2AddrModeImm8(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 405: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 9, 1) << 8; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + if (DecodeT2AddrModeImm8(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 406: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x1000; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + if (DecodeT2AddrModeImm12(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 407: \ + if (DecodeT2LoadShift(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 408: \ + if (DecodeT2LoadImm8(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 409: \ + if (DecodeT2LoadT(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 410: \ + if (DecodeT2LoadImm12(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 411: \ + if (DecodeT2LoadLabel(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 412: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 413: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 414: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 415: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 416: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 417: \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 418: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 419: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 420: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 2; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 16, 4) << 6; \ + if (DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 421: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 9, 1) << 8; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + if (DecodeT2AddrModeImm8(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 422: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x1000; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + if (DecodeT2AddrModeImm12(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 423: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 424: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 425: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 426: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 427: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 428: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 429: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 430: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + tmp |= fieldname(insn, 24, 1) << 11; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 431: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + tmp |= fieldname(insn, 24, 1) << 6; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 432: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + tmp |= fieldname(insn, 24, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeVpredROperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 433: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 6) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 434: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 20, 2) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 435: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 7, 1) << 2; \ + tmp |= fieldname(insn, 20, 3) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 436: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 6) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 437: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 20, 2) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 438: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 7, 1) << 2; \ + tmp |= fieldname(insn, 20, 3) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 439: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 440: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 441: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 442: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 443: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 444: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 445: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 4) << 7; \ + tmp |= fieldname(insn, 24, 1) << 11; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 446: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 7, 1) << 1; \ + tmp |= fieldname(insn, 16, 4) << 2; \ + tmp |= fieldname(insn, 24, 1) << 6; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 447: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 17, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeMQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 1) << 0; \ + tmp |= fieldname(insn, 20, 2) << 1; \ + tmp |= fieldname(insn, 24, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 448: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 6) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 449: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 20, 2) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 450: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 7, 1) << 2; \ + tmp |= fieldname(insn, 20, 3) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 451: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 16, 6) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 452: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 6) << 0; \ + tmp |= fieldname(insn, 7, 1) << 6; \ + tmp |= fieldname(insn, 20, 2) << 7; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 453: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRwithAPSR_NZCVnospRegisterClass( \ + MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 7, 1) << 2; \ + tmp |= fieldname(insn, 20, 3) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 454: \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 455: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (DecodeCoprocessor(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 456: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 457: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 458: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 459: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 460: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 461: \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodetGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 462: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (DecodeAddrMode5FP16Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 463: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 464: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 465: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 466: \ + tmp = fieldname(insn, 12, 4); \ + if (DecoderGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 467: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 468: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 469: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 470: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 471: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 472: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 473: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 474: \ + if (DecodeVMOVSRR(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 475: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 4) << 9; \ + tmp |= fieldname(insn, 22, 1) << 8; \ + if (DecodeSPRRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 476: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (DecodeAddrMode5Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 477: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 478: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 479: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 480: \ + if (DecodeVMOVRRS(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 481: \ + if (DecodeVSCCLRM(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 482: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 483: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 484: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 4) << 9; \ + tmp |= fieldname(insn, 22, 1) << 8; \ + if (DecodeSPRRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 485: \ + if (DecodeForVMRSandVMSR(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 486: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 487: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 488: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 489: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 490: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + tmp |= fieldname(insn, 22, 1) << 12; \ + if (DecodeDPRRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 491: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + if (DecodeDPRRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 492: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (DecodeAddrMode5Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 493: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 494: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 495: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 496: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + tmp |= fieldname(insn, 22, 1) << 12; \ + if (DecodeDPRRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 497: \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + if (DecodeDPRRegListOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 498: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 499: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 500: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 501: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 502: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 503: \ + if (DecodeVSTRVLDR_SYSREG(MI, tmp, Address, Decoder, false) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 504: \ + if (DecodeVSTRVLDR_SYSREG(MI, tmp, Address, Decoder, true) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 505: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 506: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 23, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 507: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 508: \ + if (DecodeNEONComplexLane64Instruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 509: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 510: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 23, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 511: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (DecodeQPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 512: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 3) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPR_8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 513: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 514: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 515: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodePredicateOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 516: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 517: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeHPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 518: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 519: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 520: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 521: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (DecodeSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (DecodeDPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + } \ + } -#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address) \ -{ \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail, DecodeComplete = true; \ - uint32_t ExpectedValue; \ - const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0; \ - DecodeStatus S = MCDisassembler_Success; \ - while (true) { \ - switch (*Ptr) { \ - default: \ - return MCDisassembler_Fail; \ - case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - ++Ptr; \ - CurFieldValue = fieldname(insn, Start, Len); \ - break; \ - } \ - case MCD_OPC_FilterValue: { \ - /* Decode the field value. */ \ - Val = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - /* NumToSkip is a plain 24-bit integer. */ \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - NumToSkip |= (*Ptr++) << 16; \ - /* Perform the filter operation. */ \ - if (Val != CurFieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - /* Decode the field value. */ \ - ExpectedValue = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - /* NumToSkip is a plain 24-bit integer. */ \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - NumToSkip |= (*Ptr++) << 16; \ - /* If the actual and expected values don't match, skip. */ \ - if (ExpectedValue != FieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckPredicate: { \ - /* Decode the Predicate Index value. */ \ - PIdx = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - /* NumToSkip is a plain 24-bit integer. */ \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - NumToSkip |= (*Ptr++) << 16; \ - /* Check the predicate. */ \ - if (!(Pred = checkDecoderPredicate(PIdx, MI))) \ - Ptr += NumToSkip; \ - /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ - (void)Pred; \ - break; \ - } \ - case MCD_OPC_Decode: { \ - /* Decode the Opcode value. */ \ - Opc = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - DecodeIdx = decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - MCInst_clear(MI); \ - MCInst_setOpcode(MI, Opc); \ - S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ - /* assert(DecodeComplete); */ \ - return S; \ - } \ - case MCD_OPC_TryDecode: { \ - /* Decode the Opcode value. */ \ - Opc = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - DecodeIdx = decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - /* NumToSkip is a plain 24-bit integer. */ \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - NumToSkip |= (*Ptr++) << 16; \ - /* Perform the decode operation. */ \ - MCInst_setOpcode(MI, Opc); \ - S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ - if (DecodeComplete) { \ - /* Decoding complete. */ \ - return S; \ - } else { \ - /* assert(S == MCDisassembler_Fail); */ \ - /* If the decoding was incomplete, skip. */ \ - Ptr += NumToSkip; \ - /* Reset decode status. This also drops a SoftFail status that could be */ \ - /* set before the decode attempt. */ \ - S = MCDisassembler_Success; \ - } \ - break; \ - } \ - case MCD_OPC_SoftFail: { \ - /* Decode the mask values. */ \ - PositiveMask = decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NegativeMask = decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ - if (Fail) \ - S = MCDisassembler_SoftFail; \ - break; \ - } \ - case MCD_OPC_Fail: { \ - return MCDisassembler_Fail; \ - } \ - } \ - } \ - /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ -} +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ + static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + MCRegisterInfo *MRI, int feature) { \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, feature))) \ + Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could \ + * be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ + } + +FieldFromInstruction(fieldFromInstruction, uint32_t) + DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) + DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) + +#endif // MIPS_GET_DISASSEMBLER +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +#define ARM_APSR 1 +#define ARM_APSR_NZCV 2 +#define ARM_CPSR 3 +#define ARM_FPCXTNS 4 +#define ARM_FPCXTS 5 +#define ARM_FPEXC 6 +#define ARM_FPINST 7 +#define ARM_FPSCR 8 +#define ARM_FPSCR_NZCV 9 +#define ARM_FPSCR_NZCVQC 10 +#define ARM_FPSID 11 +#define ARM_ITSTATE 12 +#define ARM_LR 13 +#define ARM_PC 14 +#define ARM_SP 15 +#define ARM_SPSR 16 +#define ARM_VPR 17 +#define ARM_ZR 18 +#define ARM_D0 19 +#define ARM_D1 20 +#define ARM_D2 21 +#define ARM_D3 22 +#define ARM_D4 23 +#define ARM_D5 24 +#define ARM_D6 25 +#define ARM_D7 26 +#define ARM_D8 27 +#define ARM_D9 28 +#define ARM_D10 29 +#define ARM_D11 30 +#define ARM_D12 31 +#define ARM_D13 32 +#define ARM_D14 33 +#define ARM_D15 34 +#define ARM_D16 35 +#define ARM_D17 36 +#define ARM_D18 37 +#define ARM_D19 38 +#define ARM_D20 39 +#define ARM_D21 40 +#define ARM_D22 41 +#define ARM_D23 42 +#define ARM_D24 43 +#define ARM_D25 44 +#define ARM_D26 45 +#define ARM_D27 46 +#define ARM_D28 47 +#define ARM_D29 48 +#define ARM_D30 49 +#define ARM_D31 50 +#define ARM_FPINST2 51 +#define ARM_MVFR0 52 +#define ARM_MVFR1 53 +#define ARM_MVFR2 54 +#define ARM_P0 55 +#define ARM_Q0 56 +#define ARM_Q1 57 +#define ARM_Q2 58 +#define ARM_Q3 59 +#define ARM_Q4 60 +#define ARM_Q5 61 +#define ARM_Q6 62 +#define ARM_Q7 63 +#define ARM_Q8 64 +#define ARM_Q9 65 +#define ARM_Q10 66 +#define ARM_Q11 67 +#define ARM_Q12 68 +#define ARM_Q13 69 +#define ARM_Q14 70 +#define ARM_Q15 71 +#define ARM_R0 72 +#define ARM_R1 73 +#define ARM_R2 74 +#define ARM_R3 75 +#define ARM_R4 76 +#define ARM_R5 77 +#define ARM_R6 78 +#define ARM_R7 79 +#define ARM_R8 80 +#define ARM_R9 81 +#define ARM_R10 82 +#define ARM_R11 83 +#define ARM_R12 84 +#define ARM_S0 85 +#define ARM_S1 86 +#define ARM_S2 87 +#define ARM_S3 88 +#define ARM_S4 89 +#define ARM_S5 90 +#define ARM_S6 91 +#define ARM_S7 92 +#define ARM_S8 93 +#define ARM_S9 94 +#define ARM_S10 95 +#define ARM_S11 96 +#define ARM_S12 97 +#define ARM_S13 98 +#define ARM_S14 99 +#define ARM_S15 100 +#define ARM_S16 101 +#define ARM_S17 102 +#define ARM_S18 103 +#define ARM_S19 104 +#define ARM_S20 105 +#define ARM_S21 106 +#define ARM_S22 107 +#define ARM_S23 108 +#define ARM_S24 109 +#define ARM_S25 110 +#define ARM_S26 111 +#define ARM_S27 112 +#define ARM_S28 113 +#define ARM_S29 114 +#define ARM_S30 115 +#define ARM_S31 116 +#define ARM_D0_D2 117 +#define ARM_D1_D3 118 +#define ARM_D2_D4 119 +#define ARM_D3_D5 120 +#define ARM_D4_D6 121 +#define ARM_D5_D7 122 +#define ARM_D6_D8 123 +#define ARM_D7_D9 124 +#define ARM_D8_D10 125 +#define ARM_D9_D11 126 +#define ARM_D10_D12 127 +#define ARM_D11_D13 128 +#define ARM_D12_D14 129 +#define ARM_D13_D15 130 +#define ARM_D14_D16 131 +#define ARM_D15_D17 132 +#define ARM_D16_D18 133 +#define ARM_D17_D19 134 +#define ARM_D18_D20 135 +#define ARM_D19_D21 136 +#define ARM_D20_D22 137 +#define ARM_D21_D23 138 +#define ARM_D22_D24 139 +#define ARM_D23_D25 140 +#define ARM_D24_D26 141 +#define ARM_D25_D27 142 +#define ARM_D26_D28 143 +#define ARM_D27_D29 144 +#define ARM_D28_D30 145 +#define ARM_D29_D31 146 +#define ARM_Q0_Q1 147 +#define ARM_Q1_Q2 148 +#define ARM_Q2_Q3 149 +#define ARM_Q3_Q4 150 +#define ARM_Q4_Q5 151 +#define ARM_Q5_Q6 152 +#define ARM_Q6_Q7 153 +#define ARM_Q7_Q8 154 +#define ARM_Q8_Q9 155 +#define ARM_Q9_Q10 156 +#define ARM_Q10_Q11 157 +#define ARM_Q11_Q12 158 +#define ARM_Q12_Q13 159 +#define ARM_Q13_Q14 160 +#define ARM_Q14_Q15 161 +#define ARM_Q0_Q1_Q2_Q3 162 +#define ARM_Q1_Q2_Q3_Q4 163 +#define ARM_Q2_Q3_Q4_Q5 164 +#define ARM_Q3_Q4_Q5_Q6 165 +#define ARM_Q4_Q5_Q6_Q7 166 +#define ARM_Q5_Q6_Q7_Q8 167 +#define ARM_Q6_Q7_Q8_Q9 168 +#define ARM_Q7_Q8_Q9_Q10 169 +#define ARM_Q8_Q9_Q10_Q11 170 +#define ARM_Q9_Q10_Q11_Q12 171 +#define ARM_Q10_Q11_Q12_Q13 172 +#define ARM_Q11_Q12_Q13_Q14 173 +#define ARM_Q12_Q13_Q14_Q15 174 +#define ARM_R0_R1 175 +#define ARM_R2_R3 176 +#define ARM_R4_R5 177 +#define ARM_R6_R7 178 +#define ARM_R8_R9 179 +#define ARM_R10_R11 180 +#define ARM_R12_SP 181 +#define ARM_D0_D1_D2 182 +#define ARM_D1_D2_D3 183 +#define ARM_D2_D3_D4 184 +#define ARM_D3_D4_D5 185 +#define ARM_D4_D5_D6 186 +#define ARM_D5_D6_D7 187 +#define ARM_D6_D7_D8 188 +#define ARM_D7_D8_D9 189 +#define ARM_D8_D9_D10 190 +#define ARM_D9_D10_D11 191 +#define ARM_D10_D11_D12 192 +#define ARM_D11_D12_D13 193 +#define ARM_D12_D13_D14 194 +#define ARM_D13_D14_D15 195 +#define ARM_D14_D15_D16 196 +#define ARM_D15_D16_D17 197 +#define ARM_D16_D17_D18 198 +#define ARM_D17_D18_D19 199 +#define ARM_D18_D19_D20 200 +#define ARM_D19_D20_D21 201 +#define ARM_D20_D21_D22 202 +#define ARM_D21_D22_D23 203 +#define ARM_D22_D23_D24 204 +#define ARM_D23_D24_D25 205 +#define ARM_D24_D25_D26 206 +#define ARM_D25_D26_D27 207 +#define ARM_D26_D27_D28 208 +#define ARM_D27_D28_D29 209 +#define ARM_D28_D29_D30 210 +#define ARM_D29_D30_D31 211 +#define ARM_D0_D2_D4 212 +#define ARM_D1_D3_D5 213 +#define ARM_D2_D4_D6 214 +#define ARM_D3_D5_D7 215 +#define ARM_D4_D6_D8 216 +#define ARM_D5_D7_D9 217 +#define ARM_D6_D8_D10 218 +#define ARM_D7_D9_D11 219 +#define ARM_D8_D10_D12 220 +#define ARM_D9_D11_D13 221 +#define ARM_D10_D12_D14 222 +#define ARM_D11_D13_D15 223 +#define ARM_D12_D14_D16 224 +#define ARM_D13_D15_D17 225 +#define ARM_D14_D16_D18 226 +#define ARM_D15_D17_D19 227 +#define ARM_D16_D18_D20 228 +#define ARM_D17_D19_D21 229 +#define ARM_D18_D20_D22 230 +#define ARM_D19_D21_D23 231 +#define ARM_D20_D22_D24 232 +#define ARM_D21_D23_D25 233 +#define ARM_D22_D24_D26 234 +#define ARM_D23_D25_D27 235 +#define ARM_D24_D26_D28 236 +#define ARM_D25_D27_D29 237 +#define ARM_D26_D28_D30 238 +#define ARM_D27_D29_D31 239 +#define ARM_D0_D2_D4_D6 240 +#define ARM_D1_D3_D5_D7 241 +#define ARM_D2_D4_D6_D8 242 +#define ARM_D3_D5_D7_D9 243 +#define ARM_D4_D6_D8_D10 244 +#define ARM_D5_D7_D9_D11 245 +#define ARM_D6_D8_D10_D12 246 +#define ARM_D7_D9_D11_D13 247 +#define ARM_D8_D10_D12_D14 248 +#define ARM_D9_D11_D13_D15 249 +#define ARM_D10_D12_D14_D16 250 +#define ARM_D11_D13_D15_D17 251 +#define ARM_D12_D14_D16_D18 252 +#define ARM_D13_D15_D17_D19 253 +#define ARM_D14_D16_D18_D20 254 +#define ARM_D15_D17_D19_D21 255 +#define ARM_D16_D18_D20_D22 256 +#define ARM_D17_D19_D21_D23 257 +#define ARM_D18_D20_D22_D24 258 +#define ARM_D19_D21_D23_D25 259 +#define ARM_D20_D22_D24_D26 260 +#define ARM_D21_D23_D25_D27 261 +#define ARM_D22_D24_D26_D28 262 +#define ARM_D23_D25_D27_D29 263 +#define ARM_D24_D26_D28_D30 264 +#define ARM_D25_D27_D29_D31 265 +#define ARM_D1_D2 266 +#define ARM_D3_D4 267 +#define ARM_D5_D6 268 +#define ARM_D7_D8 269 +#define ARM_D9_D10 270 +#define ARM_D11_D12 271 +#define ARM_D13_D14 272 +#define ARM_D15_D16 273 +#define ARM_D17_D18 274 +#define ARM_D19_D20 275 +#define ARM_D21_D22 276 +#define ARM_D23_D24 277 +#define ARM_D25_D26 278 +#define ARM_D27_D28 279 +#define ARM_D29_D30 280 +#define ARM_D1_D2_D3_D4 281 +#define ARM_D3_D4_D5_D6 282 +#define ARM_D5_D6_D7_D8 283 +#define ARM_D7_D8_D9_D10 284 +#define ARM_D9_D10_D11_D12 285 +#define ARM_D11_D12_D13_D14 286 +#define ARM_D13_D14_D15_D16 287 +#define ARM_D15_D16_D17_D18 288 +#define ARM_D17_D18_D19_D20 289 +#define ARM_D19_D20_D21_D22 290 +#define ARM_D21_D22_D23_D24 291 +#define ARM_D23_D24_D25_D26 292 +#define ARM_D25_D26_D27_D28 293 +#define ARM_D27_D28_D29_D30 294 +#define ARM_NUM_TARGET_REGS 295 + +// Register classes + +#define ARM_HPRRegClassID 0 +#define ARM_FPWithVPRRegClassID 1 +#define ARM_SPRRegClassID 2 +#define ARM_FPWithVPR_with_ssub_0RegClassID 3 +#define ARM_GPRRegClassID 4 +#define ARM_GPRwithAPSRRegClassID 5 +#define ARM_GPRwithZRRegClassID 6 +#define ARM_SPR_8RegClassID 7 +#define ARM_GPRnopcRegClassID 8 +#define ARM_GPRwithAPSR_NZCVnospRegClassID 9 +#define ARM_GPRwithAPSRnospRegClassID 10 +#define ARM_GPRwithZRnospRegClassID 11 +#define ARM_GPRnoipRegClassID 12 +#define ARM_rGPRRegClassID 13 +#define ARM_GPRnoip_and_GPRnopcRegClassID 14 +#define ARM_GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID 15 +#define ARM_tGPRwithpcRegClassID 16 +#define ARM_FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID 17 +#define ARM_hGPRRegClassID 18 +#define ARM_tGPRRegClassID 19 +#define ARM_tGPREvenRegClassID 20 +#define ARM_GPRnopc_and_hGPRRegClassID 21 +#define ARM_GPRnoip_and_hGPRRegClassID 22 +#define ARM_GPRnoip_and_tGPREvenRegClassID 23 +#define ARM_GPRwithAPSR_NZCVnosp_and_hGPRRegClassID 24 +#define ARM_tGPROddRegClassID 25 +#define ARM_GPRnopc_and_GPRnoip_and_hGPRRegClassID 26 +#define ARM_tcGPRRegClassID 27 +#define ARM_GPRnoip_and_tcGPRRegClassID 28 +#define ARM_GPRwithAPSR_NZCVnosp_and_GPRnoip_and_hGPRRegClassID 29 +#define ARM_hGPR_and_tGPREvenRegClassID 30 +#define ARM_tGPR_and_tGPREvenRegClassID 31 +#define ARM_tGPR_and_tGPROddRegClassID 32 +#define ARM_tGPREven_and_tcGPRRegClassID 33 +#define ARM_hGPR_and_GPRnoip_and_tGPREvenRegClassID 34 +#define ARM_hGPR_and_tGPROddRegClassID 35 +#define ARM_tGPREven_and_GPRnoip_and_tcGPRRegClassID 36 +#define ARM_tGPROdd_and_tcGPRRegClassID 37 +#define ARM_CCRRegClassID 38 +#define ARM_FPCXTRegsRegClassID 39 +#define ARM_GPRlrRegClassID 40 +#define ARM_GPRspRegClassID 41 +#define ARM_VCCRRegClassID 42 +#define ARM_cl_FPSCR_NZCVRegClassID 43 +#define ARM_hGPR_and_tGPRwithpcRegClassID 44 +#define ARM_hGPR_and_tcGPRRegClassID 45 +#define ARM_DPRRegClassID 46 +#define ARM_DPR_VFP2RegClassID 47 +#define ARM_DPR_8RegClassID 48 +#define ARM_GPRPairRegClassID 49 +#define ARM_GPRPairnospRegClassID 50 +#define ARM_GPRPair_with_gsub_0_in_tGPRRegClassID 51 +#define ARM_GPRPair_with_gsub_0_in_hGPRRegClassID 52 +#define ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID 53 +#define ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID 54 +#define ARM_GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID 55 +#define ARM_GPRPair_with_gsub_1_in_GPRspRegClassID 56 +#define ARM_DPairSpcRegClassID 57 +#define ARM_DPairSpc_with_ssub_0RegClassID 58 +#define ARM_DPairSpc_with_ssub_4RegClassID 59 +#define ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID 60 +#define ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID 61 +#define ARM_DPairRegClassID 62 +#define ARM_DPair_with_ssub_0RegClassID 63 +#define ARM_QPRRegClassID 64 +#define ARM_DPair_with_ssub_2RegClassID 65 +#define ARM_DPair_with_dsub_0_in_DPR_8RegClassID 66 +#define ARM_MQPRRegClassID 67 +#define ARM_QPR_VFP2RegClassID 68 +#define ARM_DPair_with_dsub_1_in_DPR_8RegClassID 69 +#define ARM_QPR_8RegClassID 70 +#define ARM_DTripleRegClassID 71 +#define ARM_DTripleSpcRegClassID 72 +#define ARM_DTripleSpc_with_ssub_0RegClassID 73 +#define ARM_DTriple_with_ssub_0RegClassID 74 +#define ARM_DTriple_with_qsub_0_in_QPRRegClassID 75 +#define ARM_DTriple_with_ssub_2RegClassID 76 +#define ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID 77 +#define ARM_DTripleSpc_with_ssub_4RegClassID 78 +#define ARM_DTriple_with_ssub_4RegClassID 79 +#define ARM_DTripleSpc_with_ssub_8RegClassID 80 +#define ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID 81 +#define ARM_DTriple_with_dsub_0_in_DPR_8RegClassID 82 +#define ARM_DTriple_with_qsub_0_in_MQPRRegClassID 83 +#define ARM_DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID \ + 84 +#define ARM_DTriple_with_dsub_1_in_DPR_8RegClassID 85 +#define ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID 86 +#define ARM_DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID 87 +#define ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID 88 +#define ARM_DTriple_with_dsub_2_in_DPR_8RegClassID 89 +#define ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID 90 +#define ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID \ + 91 +#define ARM_DTriple_with_qsub_0_in_QPR_8RegClassID 92 +#define ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID \ + 93 +#define ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID 94 +#define ARM_DQuadSpcRegClassID 95 +#define ARM_DQuadSpc_with_ssub_0RegClassID 96 +#define ARM_DQuadSpc_with_ssub_4RegClassID 97 +#define ARM_DQuadSpc_with_ssub_8RegClassID 98 +#define ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID 99 +#define ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID 100 +#define ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID 101 +#define ARM_DQuadRegClassID 102 +#define ARM_DQuad_with_ssub_0RegClassID 103 +#define ARM_DQuad_with_ssub_2RegClassID 104 +#define ARM_QQPRRegClassID 105 +#define ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID 106 +#define ARM_DQuad_with_ssub_4RegClassID 107 +#define ARM_DQuad_with_ssub_6RegClassID 108 +#define ARM_DQuad_with_dsub_0_in_DPR_8RegClassID 109 +#define ARM_DQuad_with_qsub_0_in_MQPRRegClassID 110 +#define ARM_DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID \ + 111 +#define ARM_DQuad_with_dsub_1_in_DPR_8RegClassID 112 +#define ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID 113 +#define ARM_MQQPRRegClassID 114 +#define ARM_DQuad_with_dsub_2_in_DPR_8RegClassID 115 +#define ARM_DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID \ + 116 +#define ARM_DQuad_with_dsub_3_in_DPR_8RegClassID 117 +#define ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID \ + 118 +#define ARM_DQuad_with_qsub_0_in_QPR_8RegClassID 119 +#define ARM_DQuad_with_qsub_1_in_QPR_8RegClassID 120 +#define ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID 121 +#define ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID \ + 122 +#define ARM_QQQQPRRegClassID 123 +#define ARM_QQQQPR_with_ssub_0RegClassID 124 +#define ARM_QQQQPR_with_ssub_4RegClassID 125 +#define ARM_QQQQPR_with_ssub_8RegClassID 126 +#define ARM_MQQQQPRRegClassID 127 +#define ARM_MQQQQPR_with_dsub_0_in_DPR_8RegClassID 128 +#define ARM_MQQQQPR_with_dsub_2_in_DPR_8RegClassID 129 +#define ARM_MQQQQPR_with_dsub_4_in_DPR_8RegClassID 130 +#define ARM_MQQQQPR_with_dsub_6_in_DPR_8RegClassID 131 + +#endif // GET_REGINFO_ENUM + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +#define ARM_PHI 0 +#define ARM_INLINEASM 1 +#define ARM_INLINEASM_BR 2 +#define ARM_CFI_INSTRUCTION 3 +#define ARM_EH_LABEL 4 +#define ARM_GC_LABEL 5 +#define ARM_ANNOTATION_LABEL 6 +#define ARM_KILL 7 +#define ARM_EXTRACT_SUBREG 8 +#define ARM_INSERT_SUBREG 9 +#define ARM_IMPLICIT_DEF 10 +#define ARM_SUBREG_TO_REG 11 +#define ARM_COPY_TO_REGCLASS 12 +#define ARM_DBG_VALUE 13 +#define ARM_DBG_VALUE_LIST 14 +#define ARM_DBG_INSTR_REF 15 +#define ARM_DBG_PHI 16 +#define ARM_DBG_LABEL 17 +#define ARM_REG_SEQUENCE 18 +#define ARM_COPY 19 +#define ARM_BUNDLE 20 +#define ARM_LIFETIME_START 21 +#define ARM_LIFETIME_END 22 +#define ARM_PSEUDO_PROBE 23 +#define ARM_ARITH_FENCE 24 +#define ARM_STACKMAP 25 +#define ARM_FENTRY_CALL 26 +#define ARM_PATCHPOINT 27 +#define ARM_LOAD_STACK_GUARD 28 +#define ARM_PREALLOCATED_SETUP 29 +#define ARM_PREALLOCATED_ARG 30 +#define ARM_STATEPOINT 31 +#define ARM_LOCAL_ESCAPE 32 +#define ARM_FAULTING_OP 33 +#define ARM_PATCHABLE_OP 34 +#define ARM_PATCHABLE_FUNCTION_ENTER 35 +#define ARM_PATCHABLE_RET 36 +#define ARM_PATCHABLE_FUNCTION_EXIT 37 +#define ARM_PATCHABLE_TAIL_CALL 38 +#define ARM_PATCHABLE_EVENT_CALL 39 +#define ARM_PATCHABLE_TYPED_EVENT_CALL 40 +#define ARM_ICALL_BRANCH_FUNNEL 41 +#define ARM_G_ASSERT_SEXT 42 +#define ARM_G_ASSERT_ZEXT 43 +#define ARM_G_ADD 44 +#define ARM_G_SUB 45 +#define ARM_G_MUL 46 +#define ARM_G_SDIV 47 +#define ARM_G_UDIV 48 +#define ARM_G_SREM 49 +#define ARM_G_UREM 50 +#define ARM_G_SDIVREM 51 +#define ARM_G_UDIVREM 52 +#define ARM_G_AND 53 +#define ARM_G_OR 54 +#define ARM_G_XOR 55 +#define ARM_G_IMPLICIT_DEF 56 +#define ARM_G_PHI 57 +#define ARM_G_FRAME_INDEX 58 +#define ARM_G_GLOBAL_VALUE 59 +#define ARM_G_EXTRACT 60 +#define ARM_G_UNMERGE_VALUES 61 +#define ARM_G_INSERT 62 +#define ARM_G_MERGE_VALUES 63 +#define ARM_G_BUILD_VECTOR 64 +#define ARM_G_BUILD_VECTOR_TRUNC 65 +#define ARM_G_CONCAT_VECTORS 66 +#define ARM_G_PTRTOINT 67 +#define ARM_G_INTTOPTR 68 +#define ARM_G_BITCAST 69 +#define ARM_G_FREEZE 70 +#define ARM_G_INTRINSIC_TRUNC 71 +#define ARM_G_INTRINSIC_ROUND 72 +#define ARM_G_INTRINSIC_LRINT 73 +#define ARM_G_INTRINSIC_ROUNDEVEN 74 +#define ARM_G_READCYCLECOUNTER 75 +#define ARM_G_LOAD 76 +#define ARM_G_SEXTLOAD 77 +#define ARM_G_ZEXTLOAD 78 +#define ARM_G_INDEXED_LOAD 79 +#define ARM_G_INDEXED_SEXTLOAD 80 +#define ARM_G_INDEXED_ZEXTLOAD 81 +#define ARM_G_STORE 82 +#define ARM_G_INDEXED_STORE 83 +#define ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS 84 +#define ARM_G_ATOMIC_CMPXCHG 85 +#define ARM_G_ATOMICRMW_XCHG 86 +#define ARM_G_ATOMICRMW_ADD 87 +#define ARM_G_ATOMICRMW_SUB 88 +#define ARM_G_ATOMICRMW_AND 89 +#define ARM_G_ATOMICRMW_NAND 90 +#define ARM_G_ATOMICRMW_OR 91 +#define ARM_G_ATOMICRMW_XOR 92 +#define ARM_G_ATOMICRMW_MAX 93 +#define ARM_G_ATOMICRMW_MIN 94 +#define ARM_G_ATOMICRMW_UMAX 95 +#define ARM_G_ATOMICRMW_UMIN 96 +#define ARM_G_ATOMICRMW_FADD 97 +#define ARM_G_ATOMICRMW_FSUB 98 +#define ARM_G_FENCE 99 +#define ARM_G_BRCOND 100 +#define ARM_G_BRINDIRECT 101 +#define ARM_G_INTRINSIC 102 +#define ARM_G_INTRINSIC_W_SIDE_EFFECTS 103 +#define ARM_G_ANYEXT 104 +#define ARM_G_TRUNC 105 +#define ARM_G_CONSTANT 106 +#define ARM_G_FCONSTANT 107 +#define ARM_G_VASTART 108 +#define ARM_G_VAARG 109 +#define ARM_G_SEXT 110 +#define ARM_G_SEXT_INREG 111 +#define ARM_G_ZEXT 112 +#define ARM_G_SHL 113 +#define ARM_G_LSHR 114 +#define ARM_G_ASHR 115 +#define ARM_G_FSHL 116 +#define ARM_G_FSHR 117 +#define ARM_G_ROTR 118 +#define ARM_G_ROTL 119 +#define ARM_G_ICMP 120 +#define ARM_G_FCMP 121 +#define ARM_G_SELECT 122 +#define ARM_G_UADDO 123 +#define ARM_G_UADDE 124 +#define ARM_G_USUBO 125 +#define ARM_G_USUBE 126 +#define ARM_G_SADDO 127 +#define ARM_G_SADDE 128 +#define ARM_G_SSUBO 129 +#define ARM_G_SSUBE 130 +#define ARM_G_UMULO 131 +#define ARM_G_SMULO 132 +#define ARM_G_UMULH 133 +#define ARM_G_SMULH 134 +#define ARM_G_UADDSAT 135 +#define ARM_G_SADDSAT 136 +#define ARM_G_USUBSAT 137 +#define ARM_G_SSUBSAT 138 +#define ARM_G_USHLSAT 139 +#define ARM_G_SSHLSAT 140 +#define ARM_G_SMULFIX 141 +#define ARM_G_UMULFIX 142 +#define ARM_G_SMULFIXSAT 143 +#define ARM_G_UMULFIXSAT 144 +#define ARM_G_SDIVFIX 145 +#define ARM_G_UDIVFIX 146 +#define ARM_G_SDIVFIXSAT 147 +#define ARM_G_UDIVFIXSAT 148 +#define ARM_G_FADD 149 +#define ARM_G_FSUB 150 +#define ARM_G_FMUL 151 +#define ARM_G_FMA 152 +#define ARM_G_FMAD 153 +#define ARM_G_FDIV 154 +#define ARM_G_FREM 155 +#define ARM_G_FPOW 156 +#define ARM_G_FPOWI 157 +#define ARM_G_FEXP 158 +#define ARM_G_FEXP2 159 +#define ARM_G_FLOG 160 +#define ARM_G_FLOG2 161 +#define ARM_G_FLOG10 162 +#define ARM_G_FNEG 163 +#define ARM_G_FPEXT 164 +#define ARM_G_FPTRUNC 165 +#define ARM_G_FPTOSI 166 +#define ARM_G_FPTOUI 167 +#define ARM_G_SITOFP 168 +#define ARM_G_UITOFP 169 +#define ARM_G_FABS 170 +#define ARM_G_FCOPYSIGN 171 +#define ARM_G_FCANONICALIZE 172 +#define ARM_G_FMINNUM 173 +#define ARM_G_FMAXNUM 174 +#define ARM_G_FMINNUM_IEEE 175 +#define ARM_G_FMAXNUM_IEEE 176 +#define ARM_G_FMINIMUM 177 +#define ARM_G_FMAXIMUM 178 +#define ARM_G_PTR_ADD 179 +#define ARM_G_PTRMASK 180 +#define ARM_G_SMIN 181 +#define ARM_G_SMAX 182 +#define ARM_G_UMIN 183 +#define ARM_G_UMAX 184 +#define ARM_G_ABS 185 +#define ARM_G_LROUND 186 +#define ARM_G_LLROUND 187 +#define ARM_G_BR 188 +#define ARM_G_BRJT 189 +#define ARM_G_INSERT_VECTOR_ELT 190 +#define ARM_G_EXTRACT_VECTOR_ELT 191 +#define ARM_G_SHUFFLE_VECTOR 192 +#define ARM_G_CTTZ 193 +#define ARM_G_CTTZ_ZERO_UNDEF 194 +#define ARM_G_CTLZ 195 +#define ARM_G_CTLZ_ZERO_UNDEF 196 +#define ARM_G_CTPOP 197 +#define ARM_G_BSWAP 198 +#define ARM_G_BITREVERSE 199 +#define ARM_G_FCEIL 200 +#define ARM_G_FCOS 201 +#define ARM_G_FSIN 202 +#define ARM_G_FSQRT 203 +#define ARM_G_FFLOOR 204 +#define ARM_G_FRINT 205 +#define ARM_G_FNEARBYINT 206 +#define ARM_G_ADDRSPACE_CAST 207 +#define ARM_G_BLOCK_ADDR 208 +#define ARM_G_JUMP_TABLE 209 +#define ARM_G_DYN_STACKALLOC 210 +#define ARM_G_STRICT_FADD 211 +#define ARM_G_STRICT_FSUB 212 +#define ARM_G_STRICT_FMUL 213 +#define ARM_G_STRICT_FDIV 214 +#define ARM_G_STRICT_FREM 215 +#define ARM_G_STRICT_FMA 216 +#define ARM_G_STRICT_FSQRT 217 +#define ARM_G_READ_REGISTER 218 +#define ARM_G_WRITE_REGISTER 219 +#define ARM_G_MEMCPY 220 +#define ARM_G_MEMCPY_INLINE 221 +#define ARM_G_MEMMOVE 222 +#define ARM_G_MEMSET 223 +#define ARM_G_BZERO 224 +#define ARM_G_VECREDUCE_SEQ_FADD 225 +#define ARM_G_VECREDUCE_SEQ_FMUL 226 +#define ARM_G_VECREDUCE_FADD 227 +#define ARM_G_VECREDUCE_FMUL 228 +#define ARM_G_VECREDUCE_FMAX 229 +#define ARM_G_VECREDUCE_FMIN 230 +#define ARM_G_VECREDUCE_ADD 231 +#define ARM_G_VECREDUCE_MUL 232 +#define ARM_G_VECREDUCE_AND 233 +#define ARM_G_VECREDUCE_OR 234 +#define ARM_G_VECREDUCE_XOR 235 +#define ARM_G_VECREDUCE_SMAX 236 +#define ARM_G_VECREDUCE_SMIN 237 +#define ARM_G_VECREDUCE_UMAX 238 +#define ARM_G_VECREDUCE_UMIN 239 +#define ARM_G_SBFX 240 +#define ARM_G_UBFX 241 +#define ARM_ABS 242 +#define ARM_ADDSri 243 +#define ARM_ADDSrr 244 +#define ARM_ADDSrsi 245 +#define ARM_ADDSrsr 246 +#define ARM_ADJCALLSTACKDOWN 247 +#define ARM_ADJCALLSTACKUP 248 +#define ARM_ASRi 249 +#define ARM_ASRr 250 +#define ARM_B 251 +#define ARM_BCCZi64 252 +#define ARM_BCCi64 253 +#define ARM_BLX_noip 254 +#define ARM_BLX_pred_noip 255 +#define ARM_BL_PUSHLR 256 +#define ARM_BMOVPCB_CALL 257 +#define ARM_BMOVPCRX_CALL 258 +#define ARM_BR_JTadd 259 +#define ARM_BR_JTm_i12 260 +#define ARM_BR_JTm_rs 261 +#define ARM_BR_JTr 262 +#define ARM_BX_CALL 263 +#define ARM_CMP_SWAP_16 264 +#define ARM_CMP_SWAP_32 265 +#define ARM_CMP_SWAP_64 266 +#define ARM_CMP_SWAP_8 267 +#define ARM_CONSTPOOL_ENTRY 268 +#define ARM_COPY_STRUCT_BYVAL_I32 269 +#define ARM_CompilerBarrier 270 +#define ARM_ITasm 271 +#define ARM_Int_eh_sjlj_dispatchsetup 272 +#define ARM_Int_eh_sjlj_longjmp 273 +#define ARM_Int_eh_sjlj_setjmp 274 +#define ARM_Int_eh_sjlj_setjmp_nofp 275 +#define ARM_Int_eh_sjlj_setup_dispatch 276 +#define ARM_JUMPTABLE_ADDRS 277 +#define ARM_JUMPTABLE_INSTS 278 +#define ARM_JUMPTABLE_TBB 279 +#define ARM_JUMPTABLE_TBH 280 +#define ARM_LDMIA_RET 281 +#define ARM_LDRBT_POST 282 +#define ARM_LDRConstPool 283 +#define ARM_LDRHTii 284 +#define ARM_LDRLIT_ga_abs 285 +#define ARM_LDRLIT_ga_pcrel 286 +#define ARM_LDRLIT_ga_pcrel_ldr 287 +#define ARM_LDRSBTii 288 +#define ARM_LDRSHTii 289 +#define ARM_LDRT_POST 290 +#define ARM_LEApcrel 291 +#define ARM_LEApcrelJT 292 +#define ARM_LOADDUAL 293 +#define ARM_LSLi 294 +#define ARM_LSLr 295 +#define ARM_LSRi 296 +#define ARM_LSRr 297 +#define ARM_MEMCPY 298 +#define ARM_MLAv5 299 +#define ARM_MOVCCi 300 +#define ARM_MOVCCi16 301 +#define ARM_MOVCCi32imm 302 +#define ARM_MOVCCr 303 +#define ARM_MOVCCsi 304 +#define ARM_MOVCCsr 305 +#define ARM_MOVPCRX 306 +#define ARM_MOVTi16_ga_pcrel 307 +#define ARM_MOV_ga_pcrel 308 +#define ARM_MOV_ga_pcrel_ldr 309 +#define ARM_MOVi16_ga_pcrel 310 +#define ARM_MOVi32imm 311 +#define ARM_MOVsra_flag 312 +#define ARM_MOVsrl_flag 313 +#define ARM_MQPRCopy 314 +#define ARM_MQQPRLoad 315 +#define ARM_MQQPRStore 316 +#define ARM_MQQQQPRLoad 317 +#define ARM_MQQQQPRStore 318 +#define ARM_MULv5 319 +#define ARM_MVE_MEMCPYLOOPINST 320 +#define ARM_MVE_MEMSETLOOPINST 321 +#define ARM_MVNCCi 322 +#define ARM_PICADD 323 +#define ARM_PICLDR 324 +#define ARM_PICLDRB 325 +#define ARM_PICLDRH 326 +#define ARM_PICLDRSB 327 +#define ARM_PICLDRSH 328 +#define ARM_PICSTR 329 +#define ARM_PICSTRB 330 +#define ARM_PICSTRH 331 +#define ARM_RORi 332 +#define ARM_RORr 333 +#define ARM_RRX 334 +#define ARM_RRXi 335 +#define ARM_RSBSri 336 +#define ARM_RSBSrsi 337 +#define ARM_RSBSrsr 338 +#define ARM_SMLALv5 339 +#define ARM_SMULLv5 340 +#define ARM_SPACE 341 +#define ARM_STOREDUAL 342 +#define ARM_STRBT_POST 343 +#define ARM_STRBi_preidx 344 +#define ARM_STRBr_preidx 345 +#define ARM_STRH_preidx 346 +#define ARM_STRT_POST 347 +#define ARM_STRi_preidx 348 +#define ARM_STRr_preidx 349 +#define ARM_SUBS_PC_LR 350 +#define ARM_SUBSri 351 +#define ARM_SUBSrr 352 +#define ARM_SUBSrsi 353 +#define ARM_SUBSrsr 354 +#define ARM_SpeculationBarrierISBDSBEndBB 355 +#define ARM_SpeculationBarrierSBEndBB 356 +#define ARM_TAILJMPd 357 +#define ARM_TAILJMPr 358 +#define ARM_TAILJMPr4 359 +#define ARM_TCRETURNdi 360 +#define ARM_TCRETURNri 361 +#define ARM_TPsoft 362 +#define ARM_UMLALv5 363 +#define ARM_UMULLv5 364 +#define ARM_VLD1LNdAsm_16 365 +#define ARM_VLD1LNdAsm_32 366 +#define ARM_VLD1LNdAsm_8 367 +#define ARM_VLD1LNdWB_fixed_Asm_16 368 +#define ARM_VLD1LNdWB_fixed_Asm_32 369 +#define ARM_VLD1LNdWB_fixed_Asm_8 370 +#define ARM_VLD1LNdWB_register_Asm_16 371 +#define ARM_VLD1LNdWB_register_Asm_32 372 +#define ARM_VLD1LNdWB_register_Asm_8 373 +#define ARM_VLD2LNdAsm_16 374 +#define ARM_VLD2LNdAsm_32 375 +#define ARM_VLD2LNdAsm_8 376 +#define ARM_VLD2LNdWB_fixed_Asm_16 377 +#define ARM_VLD2LNdWB_fixed_Asm_32 378 +#define ARM_VLD2LNdWB_fixed_Asm_8 379 +#define ARM_VLD2LNdWB_register_Asm_16 380 +#define ARM_VLD2LNdWB_register_Asm_32 381 +#define ARM_VLD2LNdWB_register_Asm_8 382 +#define ARM_VLD2LNqAsm_16 383 +#define ARM_VLD2LNqAsm_32 384 +#define ARM_VLD2LNqWB_fixed_Asm_16 385 +#define ARM_VLD2LNqWB_fixed_Asm_32 386 +#define ARM_VLD2LNqWB_register_Asm_16 387 +#define ARM_VLD2LNqWB_register_Asm_32 388 +#define ARM_VLD3DUPdAsm_16 389 +#define ARM_VLD3DUPdAsm_32 390 +#define ARM_VLD3DUPdAsm_8 391 +#define ARM_VLD3DUPdWB_fixed_Asm_16 392 +#define ARM_VLD3DUPdWB_fixed_Asm_32 393 +#define ARM_VLD3DUPdWB_fixed_Asm_8 394 +#define ARM_VLD3DUPdWB_register_Asm_16 395 +#define ARM_VLD3DUPdWB_register_Asm_32 396 +#define ARM_VLD3DUPdWB_register_Asm_8 397 +#define ARM_VLD3DUPqAsm_16 398 +#define ARM_VLD3DUPqAsm_32 399 +#define ARM_VLD3DUPqAsm_8 400 +#define ARM_VLD3DUPqWB_fixed_Asm_16 401 +#define ARM_VLD3DUPqWB_fixed_Asm_32 402 +#define ARM_VLD3DUPqWB_fixed_Asm_8 403 +#define ARM_VLD3DUPqWB_register_Asm_16 404 +#define ARM_VLD3DUPqWB_register_Asm_32 405 +#define ARM_VLD3DUPqWB_register_Asm_8 406 +#define ARM_VLD3LNdAsm_16 407 +#define ARM_VLD3LNdAsm_32 408 +#define ARM_VLD3LNdAsm_8 409 +#define ARM_VLD3LNdWB_fixed_Asm_16 410 +#define ARM_VLD3LNdWB_fixed_Asm_32 411 +#define ARM_VLD3LNdWB_fixed_Asm_8 412 +#define ARM_VLD3LNdWB_register_Asm_16 413 +#define ARM_VLD3LNdWB_register_Asm_32 414 +#define ARM_VLD3LNdWB_register_Asm_8 415 +#define ARM_VLD3LNqAsm_16 416 +#define ARM_VLD3LNqAsm_32 417 +#define ARM_VLD3LNqWB_fixed_Asm_16 418 +#define ARM_VLD3LNqWB_fixed_Asm_32 419 +#define ARM_VLD3LNqWB_register_Asm_16 420 +#define ARM_VLD3LNqWB_register_Asm_32 421 +#define ARM_VLD3dAsm_16 422 +#define ARM_VLD3dAsm_32 423 +#define ARM_VLD3dAsm_8 424 +#define ARM_VLD3dWB_fixed_Asm_16 425 +#define ARM_VLD3dWB_fixed_Asm_32 426 +#define ARM_VLD3dWB_fixed_Asm_8 427 +#define ARM_VLD3dWB_register_Asm_16 428 +#define ARM_VLD3dWB_register_Asm_32 429 +#define ARM_VLD3dWB_register_Asm_8 430 +#define ARM_VLD3qAsm_16 431 +#define ARM_VLD3qAsm_32 432 +#define ARM_VLD3qAsm_8 433 +#define ARM_VLD3qWB_fixed_Asm_16 434 +#define ARM_VLD3qWB_fixed_Asm_32 435 +#define ARM_VLD3qWB_fixed_Asm_8 436 +#define ARM_VLD3qWB_register_Asm_16 437 +#define ARM_VLD3qWB_register_Asm_32 438 +#define ARM_VLD3qWB_register_Asm_8 439 +#define ARM_VLD4DUPdAsm_16 440 +#define ARM_VLD4DUPdAsm_32 441 +#define ARM_VLD4DUPdAsm_8 442 +#define ARM_VLD4DUPdWB_fixed_Asm_16 443 +#define ARM_VLD4DUPdWB_fixed_Asm_32 444 +#define ARM_VLD4DUPdWB_fixed_Asm_8 445 +#define ARM_VLD4DUPdWB_register_Asm_16 446 +#define ARM_VLD4DUPdWB_register_Asm_32 447 +#define ARM_VLD4DUPdWB_register_Asm_8 448 +#define ARM_VLD4DUPqAsm_16 449 +#define ARM_VLD4DUPqAsm_32 450 +#define ARM_VLD4DUPqAsm_8 451 +#define ARM_VLD4DUPqWB_fixed_Asm_16 452 +#define ARM_VLD4DUPqWB_fixed_Asm_32 453 +#define ARM_VLD4DUPqWB_fixed_Asm_8 454 +#define ARM_VLD4DUPqWB_register_Asm_16 455 +#define ARM_VLD4DUPqWB_register_Asm_32 456 +#define ARM_VLD4DUPqWB_register_Asm_8 457 +#define ARM_VLD4LNdAsm_16 458 +#define ARM_VLD4LNdAsm_32 459 +#define ARM_VLD4LNdAsm_8 460 +#define ARM_VLD4LNdWB_fixed_Asm_16 461 +#define ARM_VLD4LNdWB_fixed_Asm_32 462 +#define ARM_VLD4LNdWB_fixed_Asm_8 463 +#define ARM_VLD4LNdWB_register_Asm_16 464 +#define ARM_VLD4LNdWB_register_Asm_32 465 +#define ARM_VLD4LNdWB_register_Asm_8 466 +#define ARM_VLD4LNqAsm_16 467 +#define ARM_VLD4LNqAsm_32 468 +#define ARM_VLD4LNqWB_fixed_Asm_16 469 +#define ARM_VLD4LNqWB_fixed_Asm_32 470 +#define ARM_VLD4LNqWB_register_Asm_16 471 +#define ARM_VLD4LNqWB_register_Asm_32 472 +#define ARM_VLD4dAsm_16 473 +#define ARM_VLD4dAsm_32 474 +#define ARM_VLD4dAsm_8 475 +#define ARM_VLD4dWB_fixed_Asm_16 476 +#define ARM_VLD4dWB_fixed_Asm_32 477 +#define ARM_VLD4dWB_fixed_Asm_8 478 +#define ARM_VLD4dWB_register_Asm_16 479 +#define ARM_VLD4dWB_register_Asm_32 480 +#define ARM_VLD4dWB_register_Asm_8 481 +#define ARM_VLD4qAsm_16 482 +#define ARM_VLD4qAsm_32 483 +#define ARM_VLD4qAsm_8 484 +#define ARM_VLD4qWB_fixed_Asm_16 485 +#define ARM_VLD4qWB_fixed_Asm_32 486 +#define ARM_VLD4qWB_fixed_Asm_8 487 +#define ARM_VLD4qWB_register_Asm_16 488 +#define ARM_VLD4qWB_register_Asm_32 489 +#define ARM_VLD4qWB_register_Asm_8 490 +#define ARM_VMOVD0 491 +#define ARM_VMOVDcc 492 +#define ARM_VMOVHcc 493 +#define ARM_VMOVQ0 494 +#define ARM_VMOVScc 495 +#define ARM_VST1LNdAsm_16 496 +#define ARM_VST1LNdAsm_32 497 +#define ARM_VST1LNdAsm_8 498 +#define ARM_VST1LNdWB_fixed_Asm_16 499 +#define ARM_VST1LNdWB_fixed_Asm_32 500 +#define ARM_VST1LNdWB_fixed_Asm_8 501 +#define ARM_VST1LNdWB_register_Asm_16 502 +#define ARM_VST1LNdWB_register_Asm_32 503 +#define ARM_VST1LNdWB_register_Asm_8 504 +#define ARM_VST2LNdAsm_16 505 +#define ARM_VST2LNdAsm_32 506 +#define ARM_VST2LNdAsm_8 507 +#define ARM_VST2LNdWB_fixed_Asm_16 508 +#define ARM_VST2LNdWB_fixed_Asm_32 509 +#define ARM_VST2LNdWB_fixed_Asm_8 510 +#define ARM_VST2LNdWB_register_Asm_16 511 +#define ARM_VST2LNdWB_register_Asm_32 512 +#define ARM_VST2LNdWB_register_Asm_8 513 +#define ARM_VST2LNqAsm_16 514 +#define ARM_VST2LNqAsm_32 515 +#define ARM_VST2LNqWB_fixed_Asm_16 516 +#define ARM_VST2LNqWB_fixed_Asm_32 517 +#define ARM_VST2LNqWB_register_Asm_16 518 +#define ARM_VST2LNqWB_register_Asm_32 519 +#define ARM_VST3LNdAsm_16 520 +#define ARM_VST3LNdAsm_32 521 +#define ARM_VST3LNdAsm_8 522 +#define ARM_VST3LNdWB_fixed_Asm_16 523 +#define ARM_VST3LNdWB_fixed_Asm_32 524 +#define ARM_VST3LNdWB_fixed_Asm_8 525 +#define ARM_VST3LNdWB_register_Asm_16 526 +#define ARM_VST3LNdWB_register_Asm_32 527 +#define ARM_VST3LNdWB_register_Asm_8 528 +#define ARM_VST3LNqAsm_16 529 +#define ARM_VST3LNqAsm_32 530 +#define ARM_VST3LNqWB_fixed_Asm_16 531 +#define ARM_VST3LNqWB_fixed_Asm_32 532 +#define ARM_VST3LNqWB_register_Asm_16 533 +#define ARM_VST3LNqWB_register_Asm_32 534 +#define ARM_VST3dAsm_16 535 +#define ARM_VST3dAsm_32 536 +#define ARM_VST3dAsm_8 537 +#define ARM_VST3dWB_fixed_Asm_16 538 +#define ARM_VST3dWB_fixed_Asm_32 539 +#define ARM_VST3dWB_fixed_Asm_8 540 +#define ARM_VST3dWB_register_Asm_16 541 +#define ARM_VST3dWB_register_Asm_32 542 +#define ARM_VST3dWB_register_Asm_8 543 +#define ARM_VST3qAsm_16 544 +#define ARM_VST3qAsm_32 545 +#define ARM_VST3qAsm_8 546 +#define ARM_VST3qWB_fixed_Asm_16 547 +#define ARM_VST3qWB_fixed_Asm_32 548 +#define ARM_VST3qWB_fixed_Asm_8 549 +#define ARM_VST3qWB_register_Asm_16 550 +#define ARM_VST3qWB_register_Asm_32 551 +#define ARM_VST3qWB_register_Asm_8 552 +#define ARM_VST4LNdAsm_16 553 +#define ARM_VST4LNdAsm_32 554 +#define ARM_VST4LNdAsm_8 555 +#define ARM_VST4LNdWB_fixed_Asm_16 556 +#define ARM_VST4LNdWB_fixed_Asm_32 557 +#define ARM_VST4LNdWB_fixed_Asm_8 558 +#define ARM_VST4LNdWB_register_Asm_16 559 +#define ARM_VST4LNdWB_register_Asm_32 560 +#define ARM_VST4LNdWB_register_Asm_8 561 +#define ARM_VST4LNqAsm_16 562 +#define ARM_VST4LNqAsm_32 563 +#define ARM_VST4LNqWB_fixed_Asm_16 564 +#define ARM_VST4LNqWB_fixed_Asm_32 565 +#define ARM_VST4LNqWB_register_Asm_16 566 +#define ARM_VST4LNqWB_register_Asm_32 567 +#define ARM_VST4dAsm_16 568 +#define ARM_VST4dAsm_32 569 +#define ARM_VST4dAsm_8 570 +#define ARM_VST4dWB_fixed_Asm_16 571 +#define ARM_VST4dWB_fixed_Asm_32 572 +#define ARM_VST4dWB_fixed_Asm_8 573 +#define ARM_VST4dWB_register_Asm_16 574 +#define ARM_VST4dWB_register_Asm_32 575 +#define ARM_VST4dWB_register_Asm_8 576 +#define ARM_VST4qAsm_16 577 +#define ARM_VST4qAsm_32 578 +#define ARM_VST4qAsm_8 579 +#define ARM_VST4qWB_fixed_Asm_16 580 +#define ARM_VST4qWB_fixed_Asm_32 581 +#define ARM_VST4qWB_fixed_Asm_8 582 +#define ARM_VST4qWB_register_Asm_16 583 +#define ARM_VST4qWB_register_Asm_32 584 +#define ARM_VST4qWB_register_Asm_8 585 +#define ARM_WIN__CHKSTK 586 +#define ARM_WIN__DBZCHK 587 +#define ARM_t2ABS 588 +#define ARM_t2ADDSri 589 +#define ARM_t2ADDSrr 590 +#define ARM_t2ADDSrs 591 +#define ARM_t2BF_LabelPseudo 592 +#define ARM_t2BR_JT 593 +#define ARM_t2DoLoopStart 594 +#define ARM_t2DoLoopStartTP 595 +#define ARM_t2LDMIA_RET 596 +#define ARM_t2LDRBpcrel 597 +#define ARM_t2LDRConstPool 598 +#define ARM_t2LDRHpcrel 599 +#define ARM_t2LDRSBpcrel 600 +#define ARM_t2LDRSHpcrel 601 +#define ARM_t2LDR_POST_imm 602 +#define ARM_t2LDR_PRE_imm 603 +#define ARM_t2LDRpci_pic 604 +#define ARM_t2LDRpcrel 605 +#define ARM_t2LEApcrel 606 +#define ARM_t2LEApcrelJT 607 +#define ARM_t2LoopDec 608 +#define ARM_t2LoopEnd 609 +#define ARM_t2LoopEndDec 610 +#define ARM_t2MOVCCasr 611 +#define ARM_t2MOVCCi 612 +#define ARM_t2MOVCCi16 613 +#define ARM_t2MOVCCi32imm 614 +#define ARM_t2MOVCClsl 615 +#define ARM_t2MOVCClsr 616 +#define ARM_t2MOVCCr 617 +#define ARM_t2MOVCCror 618 +#define ARM_t2MOVSsi 619 +#define ARM_t2MOVSsr 620 +#define ARM_t2MOVTi16_ga_pcrel 621 +#define ARM_t2MOV_ga_pcrel 622 +#define ARM_t2MOVi16_ga_pcrel 623 +#define ARM_t2MOVi32imm 624 +#define ARM_t2MOVsi 625 +#define ARM_t2MOVsr 626 +#define ARM_t2MVNCCi 627 +#define ARM_t2RSBSri 628 +#define ARM_t2RSBSrs 629 +#define ARM_t2STRB_preidx 630 +#define ARM_t2STRH_preidx 631 +#define ARM_t2STR_POST_imm 632 +#define ARM_t2STR_PRE_imm 633 +#define ARM_t2STR_preidx 634 +#define ARM_t2SUBSri 635 +#define ARM_t2SUBSrr 636 +#define ARM_t2SUBSrs 637 +#define ARM_t2SpeculationBarrierISBDSBEndBB 638 +#define ARM_t2SpeculationBarrierSBEndBB 639 +#define ARM_t2TBB_JT 640 +#define ARM_t2TBH_JT 641 +#define ARM_t2WhileLoopSetup 642 +#define ARM_t2WhileLoopStart 643 +#define ARM_t2WhileLoopStartLR 644 +#define ARM_t2WhileLoopStartTP 645 +#define ARM_tADCS 646 +#define ARM_tADDSi3 647 +#define ARM_tADDSi8 648 +#define ARM_tADDSrr 649 +#define ARM_tADDframe 650 +#define ARM_tADJCALLSTACKDOWN 651 +#define ARM_tADJCALLSTACKUP 652 +#define ARM_tBLXNS_CALL 653 +#define ARM_tBLXr_noip 654 +#define ARM_tBL_PUSHLR 655 +#define ARM_tBRIND 656 +#define ARM_tBR_JTr 657 +#define ARM_tBXNS_RET 658 +#define ARM_tBX_CALL 659 +#define ARM_tBX_RET 660 +#define ARM_tBX_RET_vararg 661 +#define ARM_tBfar 662 +#define ARM_tCMP_SWAP_16 663 +#define ARM_tCMP_SWAP_8 664 +#define ARM_tLDMIA_UPD 665 +#define ARM_tLDRConstPool 666 +#define ARM_tLDRLIT_ga_abs 667 +#define ARM_tLDRLIT_ga_pcrel 668 +#define ARM_tLDR_postidx 669 +#define ARM_tLDRpci_pic 670 +#define ARM_tLEApcrel 671 +#define ARM_tLEApcrelJT 672 +#define ARM_tLSLSri 673 +#define ARM_tMOVCCr_pseudo 674 +#define ARM_tPOP_RET 675 +#define ARM_tRSBS 676 +#define ARM_tSBCS 677 +#define ARM_tSUBSi3 678 +#define ARM_tSUBSi8 679 +#define ARM_tSUBSrr 680 +#define ARM_tTAILJMPd 681 +#define ARM_tTAILJMPdND 682 +#define ARM_tTAILJMPr 683 +#define ARM_tTBB_JT 684 +#define ARM_tTBH_JT 685 +#define ARM_tTPsoft 686 +#define ARM_ADCri 687 +#define ARM_ADCrr 688 +#define ARM_ADCrsi 689 +#define ARM_ADCrsr 690 +#define ARM_ADDri 691 +#define ARM_ADDrr 692 +#define ARM_ADDrsi 693 +#define ARM_ADDrsr 694 +#define ARM_ADR 695 +#define ARM_AESD 696 +#define ARM_AESE 697 +#define ARM_AESIMC 698 +#define ARM_AESMC 699 +#define ARM_ANDri 700 +#define ARM_ANDrr 701 +#define ARM_ANDrsi 702 +#define ARM_ANDrsr 703 +#define ARM_BF16VDOTI_VDOTD 704 +#define ARM_BF16VDOTI_VDOTQ 705 +#define ARM_BF16VDOTS_VDOTD 706 +#define ARM_BF16VDOTS_VDOTQ 707 +#define ARM_BF16_VCVT 708 +#define ARM_BF16_VCVTB 709 +#define ARM_BF16_VCVTT 710 +#define ARM_BFC 711 +#define ARM_BFI 712 +#define ARM_BICri 713 +#define ARM_BICrr 714 +#define ARM_BICrsi 715 +#define ARM_BICrsr 716 +#define ARM_BKPT 717 +#define ARM_BL 718 +#define ARM_BLX 719 +#define ARM_BLX_pred 720 +#define ARM_BLXi 721 +#define ARM_BL_pred 722 +#define ARM_BX 723 +#define ARM_BXJ 724 +#define ARM_BX_RET 725 +#define ARM_BX_pred 726 +#define ARM_Bcc 727 +#define ARM_CDE_CX1 728 +#define ARM_CDE_CX1A 729 +#define ARM_CDE_CX1D 730 +#define ARM_CDE_CX1DA 731 +#define ARM_CDE_CX2 732 +#define ARM_CDE_CX2A 733 +#define ARM_CDE_CX2D 734 +#define ARM_CDE_CX2DA 735 +#define ARM_CDE_CX3 736 +#define ARM_CDE_CX3A 737 +#define ARM_CDE_CX3D 738 +#define ARM_CDE_CX3DA 739 +#define ARM_CDE_VCX1A_fpdp 740 +#define ARM_CDE_VCX1A_fpsp 741 +#define ARM_CDE_VCX1A_vec 742 +#define ARM_CDE_VCX1_fpdp 743 +#define ARM_CDE_VCX1_fpsp 744 +#define ARM_CDE_VCX1_vec 745 +#define ARM_CDE_VCX2A_fpdp 746 +#define ARM_CDE_VCX2A_fpsp 747 +#define ARM_CDE_VCX2A_vec 748 +#define ARM_CDE_VCX2_fpdp 749 +#define ARM_CDE_VCX2_fpsp 750 +#define ARM_CDE_VCX2_vec 751 +#define ARM_CDE_VCX3A_fpdp 752 +#define ARM_CDE_VCX3A_fpsp 753 +#define ARM_CDE_VCX3A_vec 754 +#define ARM_CDE_VCX3_fpdp 755 +#define ARM_CDE_VCX3_fpsp 756 +#define ARM_CDE_VCX3_vec 757 +#define ARM_CDP 758 +#define ARM_CDP2 759 +#define ARM_CLREX 760 +#define ARM_CLZ 761 +#define ARM_CMNri 762 +#define ARM_CMNzrr 763 +#define ARM_CMNzrsi 764 +#define ARM_CMNzrsr 765 +#define ARM_CMPri 766 +#define ARM_CMPrr 767 +#define ARM_CMPrsi 768 +#define ARM_CMPrsr 769 +#define ARM_CPS1p 770 +#define ARM_CPS2p 771 +#define ARM_CPS3p 772 +#define ARM_CRC32B 773 +#define ARM_CRC32CB 774 +#define ARM_CRC32CH 775 +#define ARM_CRC32CW 776 +#define ARM_CRC32H 777 +#define ARM_CRC32W 778 +#define ARM_DBG 779 +#define ARM_DMB 780 +#define ARM_DSB 781 +#define ARM_EORri 782 +#define ARM_EORrr 783 +#define ARM_EORrsi 784 +#define ARM_EORrsr 785 +#define ARM_ERET 786 +#define ARM_FCONSTD 787 +#define ARM_FCONSTH 788 +#define ARM_FCONSTS 789 +#define ARM_FLDMXDB_UPD 790 +#define ARM_FLDMXIA 791 +#define ARM_FLDMXIA_UPD 792 +#define ARM_FMSTAT 793 +#define ARM_FSTMXDB_UPD 794 +#define ARM_FSTMXIA 795 +#define ARM_FSTMXIA_UPD 796 +#define ARM_HINT 797 +#define ARM_HLT 798 +#define ARM_HVC 799 +#define ARM_ISB 800 +#define ARM_LDA 801 +#define ARM_LDAB 802 +#define ARM_LDAEX 803 +#define ARM_LDAEXB 804 +#define ARM_LDAEXD 805 +#define ARM_LDAEXH 806 +#define ARM_LDAH 807 +#define ARM_LDC2L_OFFSET 808 +#define ARM_LDC2L_OPTION 809 +#define ARM_LDC2L_POST 810 +#define ARM_LDC2L_PRE 811 +#define ARM_LDC2_OFFSET 812 +#define ARM_LDC2_OPTION 813 +#define ARM_LDC2_POST 814 +#define ARM_LDC2_PRE 815 +#define ARM_LDCL_OFFSET 816 +#define ARM_LDCL_OPTION 817 +#define ARM_LDCL_POST 818 +#define ARM_LDCL_PRE 819 +#define ARM_LDC_OFFSET 820 +#define ARM_LDC_OPTION 821 +#define ARM_LDC_POST 822 +#define ARM_LDC_PRE 823 +#define ARM_LDMDA 824 +#define ARM_LDMDA_UPD 825 +#define ARM_LDMDB 826 +#define ARM_LDMDB_UPD 827 +#define ARM_LDMIA 828 +#define ARM_LDMIA_UPD 829 +#define ARM_LDMIB 830 +#define ARM_LDMIB_UPD 831 +#define ARM_LDRBT_POST_IMM 832 +#define ARM_LDRBT_POST_REG 833 +#define ARM_LDRB_POST_IMM 834 +#define ARM_LDRB_POST_REG 835 +#define ARM_LDRB_PRE_IMM 836 +#define ARM_LDRB_PRE_REG 837 +#define ARM_LDRBi12 838 +#define ARM_LDRBrs 839 +#define ARM_LDRD 840 +#define ARM_LDRD_POST 841 +#define ARM_LDRD_PRE 842 +#define ARM_LDREX 843 +#define ARM_LDREXB 844 +#define ARM_LDREXD 845 +#define ARM_LDREXH 846 +#define ARM_LDRH 847 +#define ARM_LDRHTi 848 +#define ARM_LDRHTr 849 +#define ARM_LDRH_POST 850 +#define ARM_LDRH_PRE 851 +#define ARM_LDRSB 852 +#define ARM_LDRSBTi 853 +#define ARM_LDRSBTr 854 +#define ARM_LDRSB_POST 855 +#define ARM_LDRSB_PRE 856 +#define ARM_LDRSH 857 +#define ARM_LDRSHTi 858 +#define ARM_LDRSHTr 859 +#define ARM_LDRSH_POST 860 +#define ARM_LDRSH_PRE 861 +#define ARM_LDRT_POST_IMM 862 +#define ARM_LDRT_POST_REG 863 +#define ARM_LDR_POST_IMM 864 +#define ARM_LDR_POST_REG 865 +#define ARM_LDR_PRE_IMM 866 +#define ARM_LDR_PRE_REG 867 +#define ARM_LDRcp 868 +#define ARM_LDRi12 869 +#define ARM_LDRrs 870 +#define ARM_MCR 871 +#define ARM_MCR2 872 +#define ARM_MCRR 873 +#define ARM_MCRR2 874 +#define ARM_MLA 875 +#define ARM_MLS 876 +#define ARM_MOVPCLR 877 +#define ARM_MOVTi16 878 +#define ARM_MOVi 879 +#define ARM_MOVi16 880 +#define ARM_MOVr 881 +#define ARM_MOVr_TC 882 +#define ARM_MOVsi 883 +#define ARM_MOVsr 884 +#define ARM_MRC 885 +#define ARM_MRC2 886 +#define ARM_MRRC 887 +#define ARM_MRRC2 888 +#define ARM_MRS 889 +#define ARM_MRSbanked 890 +#define ARM_MRSsys 891 +#define ARM_MSR 892 +#define ARM_MSRbanked 893 +#define ARM_MSRi 894 +#define ARM_MUL 895 +#define ARM_MVE_ASRLi 896 +#define ARM_MVE_ASRLr 897 +#define ARM_MVE_DLSTP_16 898 +#define ARM_MVE_DLSTP_32 899 +#define ARM_MVE_DLSTP_64 900 +#define ARM_MVE_DLSTP_8 901 +#define ARM_MVE_LCTP 902 +#define ARM_MVE_LETP 903 +#define ARM_MVE_LSLLi 904 +#define ARM_MVE_LSLLr 905 +#define ARM_MVE_LSRL 906 +#define ARM_MVE_SQRSHR 907 +#define ARM_MVE_SQRSHRL 908 +#define ARM_MVE_SQSHL 909 +#define ARM_MVE_SQSHLL 910 +#define ARM_MVE_SRSHR 911 +#define ARM_MVE_SRSHRL 912 +#define ARM_MVE_UQRSHL 913 +#define ARM_MVE_UQRSHLL 914 +#define ARM_MVE_UQSHL 915 +#define ARM_MVE_UQSHLL 916 +#define ARM_MVE_URSHR 917 +#define ARM_MVE_URSHRL 918 +#define ARM_MVE_VABAVs16 919 +#define ARM_MVE_VABAVs32 920 +#define ARM_MVE_VABAVs8 921 +#define ARM_MVE_VABAVu16 922 +#define ARM_MVE_VABAVu32 923 +#define ARM_MVE_VABAVu8 924 +#define ARM_MVE_VABDf16 925 +#define ARM_MVE_VABDf32 926 +#define ARM_MVE_VABDs16 927 +#define ARM_MVE_VABDs32 928 +#define ARM_MVE_VABDs8 929 +#define ARM_MVE_VABDu16 930 +#define ARM_MVE_VABDu32 931 +#define ARM_MVE_VABDu8 932 +#define ARM_MVE_VABSf16 933 +#define ARM_MVE_VABSf32 934 +#define ARM_MVE_VABSs16 935 +#define ARM_MVE_VABSs32 936 +#define ARM_MVE_VABSs8 937 +#define ARM_MVE_VADC 938 +#define ARM_MVE_VADCI 939 +#define ARM_MVE_VADDLVs32acc 940 +#define ARM_MVE_VADDLVs32no_acc 941 +#define ARM_MVE_VADDLVu32acc 942 +#define ARM_MVE_VADDLVu32no_acc 943 +#define ARM_MVE_VADDVs16acc 944 +#define ARM_MVE_VADDVs16no_acc 945 +#define ARM_MVE_VADDVs32acc 946 +#define ARM_MVE_VADDVs32no_acc 947 +#define ARM_MVE_VADDVs8acc 948 +#define ARM_MVE_VADDVs8no_acc 949 +#define ARM_MVE_VADDVu16acc 950 +#define ARM_MVE_VADDVu16no_acc 951 +#define ARM_MVE_VADDVu32acc 952 +#define ARM_MVE_VADDVu32no_acc 953 +#define ARM_MVE_VADDVu8acc 954 +#define ARM_MVE_VADDVu8no_acc 955 +#define ARM_MVE_VADD_qr_f16 956 +#define ARM_MVE_VADD_qr_f32 957 +#define ARM_MVE_VADD_qr_i16 958 +#define ARM_MVE_VADD_qr_i32 959 +#define ARM_MVE_VADD_qr_i8 960 +#define ARM_MVE_VADDf16 961 +#define ARM_MVE_VADDf32 962 +#define ARM_MVE_VADDi16 963 +#define ARM_MVE_VADDi32 964 +#define ARM_MVE_VADDi8 965 +#define ARM_MVE_VAND 966 +#define ARM_MVE_VBIC 967 +#define ARM_MVE_VBICimmi16 968 +#define ARM_MVE_VBICimmi32 969 +#define ARM_MVE_VBRSR16 970 +#define ARM_MVE_VBRSR32 971 +#define ARM_MVE_VBRSR8 972 +#define ARM_MVE_VCADDf16 973 +#define ARM_MVE_VCADDf32 974 +#define ARM_MVE_VCADDi16 975 +#define ARM_MVE_VCADDi32 976 +#define ARM_MVE_VCADDi8 977 +#define ARM_MVE_VCLSs16 978 +#define ARM_MVE_VCLSs32 979 +#define ARM_MVE_VCLSs8 980 +#define ARM_MVE_VCLZs16 981 +#define ARM_MVE_VCLZs32 982 +#define ARM_MVE_VCLZs8 983 +#define ARM_MVE_VCMLAf16 984 +#define ARM_MVE_VCMLAf32 985 +#define ARM_MVE_VCMPf16 986 +#define ARM_MVE_VCMPf16r 987 +#define ARM_MVE_VCMPf32 988 +#define ARM_MVE_VCMPf32r 989 +#define ARM_MVE_VCMPi16 990 +#define ARM_MVE_VCMPi16r 991 +#define ARM_MVE_VCMPi32 992 +#define ARM_MVE_VCMPi32r 993 +#define ARM_MVE_VCMPi8 994 +#define ARM_MVE_VCMPi8r 995 +#define ARM_MVE_VCMPs16 996 +#define ARM_MVE_VCMPs16r 997 +#define ARM_MVE_VCMPs32 998 +#define ARM_MVE_VCMPs32r 999 +#define ARM_MVE_VCMPs8 1000 +#define ARM_MVE_VCMPs8r 1001 +#define ARM_MVE_VCMPu16 1002 +#define ARM_MVE_VCMPu16r 1003 +#define ARM_MVE_VCMPu32 1004 +#define ARM_MVE_VCMPu32r 1005 +#define ARM_MVE_VCMPu8 1006 +#define ARM_MVE_VCMPu8r 1007 +#define ARM_MVE_VCMULf16 1008 +#define ARM_MVE_VCMULf32 1009 +#define ARM_MVE_VCTP16 1010 +#define ARM_MVE_VCTP32 1011 +#define ARM_MVE_VCTP64 1012 +#define ARM_MVE_VCTP8 1013 +#define ARM_MVE_VCVTf16f32bh 1014 +#define ARM_MVE_VCVTf16f32th 1015 +#define ARM_MVE_VCVTf16s16_fix 1016 +#define ARM_MVE_VCVTf16s16n 1017 +#define ARM_MVE_VCVTf16u16_fix 1018 +#define ARM_MVE_VCVTf16u16n 1019 +#define ARM_MVE_VCVTf32f16bh 1020 +#define ARM_MVE_VCVTf32f16th 1021 +#define ARM_MVE_VCVTf32s32_fix 1022 +#define ARM_MVE_VCVTf32s32n 1023 +#define ARM_MVE_VCVTf32u32_fix 1024 +#define ARM_MVE_VCVTf32u32n 1025 +#define ARM_MVE_VCVTs16f16_fix 1026 +#define ARM_MVE_VCVTs16f16a 1027 +#define ARM_MVE_VCVTs16f16m 1028 +#define ARM_MVE_VCVTs16f16n 1029 +#define ARM_MVE_VCVTs16f16p 1030 +#define ARM_MVE_VCVTs16f16z 1031 +#define ARM_MVE_VCVTs32f32_fix 1032 +#define ARM_MVE_VCVTs32f32a 1033 +#define ARM_MVE_VCVTs32f32m 1034 +#define ARM_MVE_VCVTs32f32n 1035 +#define ARM_MVE_VCVTs32f32p 1036 +#define ARM_MVE_VCVTs32f32z 1037 +#define ARM_MVE_VCVTu16f16_fix 1038 +#define ARM_MVE_VCVTu16f16a 1039 +#define ARM_MVE_VCVTu16f16m 1040 +#define ARM_MVE_VCVTu16f16n 1041 +#define ARM_MVE_VCVTu16f16p 1042 +#define ARM_MVE_VCVTu16f16z 1043 +#define ARM_MVE_VCVTu32f32_fix 1044 +#define ARM_MVE_VCVTu32f32a 1045 +#define ARM_MVE_VCVTu32f32m 1046 +#define ARM_MVE_VCVTu32f32n 1047 +#define ARM_MVE_VCVTu32f32p 1048 +#define ARM_MVE_VCVTu32f32z 1049 +#define ARM_MVE_VDDUPu16 1050 +#define ARM_MVE_VDDUPu32 1051 +#define ARM_MVE_VDDUPu8 1052 +#define ARM_MVE_VDUP16 1053 +#define ARM_MVE_VDUP32 1054 +#define ARM_MVE_VDUP8 1055 +#define ARM_MVE_VDWDUPu16 1056 +#define ARM_MVE_VDWDUPu32 1057 +#define ARM_MVE_VDWDUPu8 1058 +#define ARM_MVE_VEOR 1059 +#define ARM_MVE_VFMA_qr_Sf16 1060 +#define ARM_MVE_VFMA_qr_Sf32 1061 +#define ARM_MVE_VFMA_qr_f16 1062 +#define ARM_MVE_VFMA_qr_f32 1063 +#define ARM_MVE_VFMAf16 1064 +#define ARM_MVE_VFMAf32 1065 +#define ARM_MVE_VFMSf16 1066 +#define ARM_MVE_VFMSf32 1067 +#define ARM_MVE_VHADD_qr_s16 1068 +#define ARM_MVE_VHADD_qr_s32 1069 +#define ARM_MVE_VHADD_qr_s8 1070 +#define ARM_MVE_VHADD_qr_u16 1071 +#define ARM_MVE_VHADD_qr_u32 1072 +#define ARM_MVE_VHADD_qr_u8 1073 +#define ARM_MVE_VHADDs16 1074 +#define ARM_MVE_VHADDs32 1075 +#define ARM_MVE_VHADDs8 1076 +#define ARM_MVE_VHADDu16 1077 +#define ARM_MVE_VHADDu32 1078 +#define ARM_MVE_VHADDu8 1079 +#define ARM_MVE_VHCADDs16 1080 +#define ARM_MVE_VHCADDs32 1081 +#define ARM_MVE_VHCADDs8 1082 +#define ARM_MVE_VHSUB_qr_s16 1083 +#define ARM_MVE_VHSUB_qr_s32 1084 +#define ARM_MVE_VHSUB_qr_s8 1085 +#define ARM_MVE_VHSUB_qr_u16 1086 +#define ARM_MVE_VHSUB_qr_u32 1087 +#define ARM_MVE_VHSUB_qr_u8 1088 +#define ARM_MVE_VHSUBs16 1089 +#define ARM_MVE_VHSUBs32 1090 +#define ARM_MVE_VHSUBs8 1091 +#define ARM_MVE_VHSUBu16 1092 +#define ARM_MVE_VHSUBu32 1093 +#define ARM_MVE_VHSUBu8 1094 +#define ARM_MVE_VIDUPu16 1095 +#define ARM_MVE_VIDUPu32 1096 +#define ARM_MVE_VIDUPu8 1097 +#define ARM_MVE_VIWDUPu16 1098 +#define ARM_MVE_VIWDUPu32 1099 +#define ARM_MVE_VIWDUPu8 1100 +#define ARM_MVE_VLD20_16 1101 +#define ARM_MVE_VLD20_16_wb 1102 +#define ARM_MVE_VLD20_32 1103 +#define ARM_MVE_VLD20_32_wb 1104 +#define ARM_MVE_VLD20_8 1105 +#define ARM_MVE_VLD20_8_wb 1106 +#define ARM_MVE_VLD21_16 1107 +#define ARM_MVE_VLD21_16_wb 1108 +#define ARM_MVE_VLD21_32 1109 +#define ARM_MVE_VLD21_32_wb 1110 +#define ARM_MVE_VLD21_8 1111 +#define ARM_MVE_VLD21_8_wb 1112 +#define ARM_MVE_VLD40_16 1113 +#define ARM_MVE_VLD40_16_wb 1114 +#define ARM_MVE_VLD40_32 1115 +#define ARM_MVE_VLD40_32_wb 1116 +#define ARM_MVE_VLD40_8 1117 +#define ARM_MVE_VLD40_8_wb 1118 +#define ARM_MVE_VLD41_16 1119 +#define ARM_MVE_VLD41_16_wb 1120 +#define ARM_MVE_VLD41_32 1121 +#define ARM_MVE_VLD41_32_wb 1122 +#define ARM_MVE_VLD41_8 1123 +#define ARM_MVE_VLD41_8_wb 1124 +#define ARM_MVE_VLD42_16 1125 +#define ARM_MVE_VLD42_16_wb 1126 +#define ARM_MVE_VLD42_32 1127 +#define ARM_MVE_VLD42_32_wb 1128 +#define ARM_MVE_VLD42_8 1129 +#define ARM_MVE_VLD42_8_wb 1130 +#define ARM_MVE_VLD43_16 1131 +#define ARM_MVE_VLD43_16_wb 1132 +#define ARM_MVE_VLD43_32 1133 +#define ARM_MVE_VLD43_32_wb 1134 +#define ARM_MVE_VLD43_8 1135 +#define ARM_MVE_VLD43_8_wb 1136 +#define ARM_MVE_VLDRBS16 1137 +#define ARM_MVE_VLDRBS16_post 1138 +#define ARM_MVE_VLDRBS16_pre 1139 +#define ARM_MVE_VLDRBS16_rq 1140 +#define ARM_MVE_VLDRBS32 1141 +#define ARM_MVE_VLDRBS32_post 1142 +#define ARM_MVE_VLDRBS32_pre 1143 +#define ARM_MVE_VLDRBS32_rq 1144 +#define ARM_MVE_VLDRBU16 1145 +#define ARM_MVE_VLDRBU16_post 1146 +#define ARM_MVE_VLDRBU16_pre 1147 +#define ARM_MVE_VLDRBU16_rq 1148 +#define ARM_MVE_VLDRBU32 1149 +#define ARM_MVE_VLDRBU32_post 1150 +#define ARM_MVE_VLDRBU32_pre 1151 +#define ARM_MVE_VLDRBU32_rq 1152 +#define ARM_MVE_VLDRBU8 1153 +#define ARM_MVE_VLDRBU8_post 1154 +#define ARM_MVE_VLDRBU8_pre 1155 +#define ARM_MVE_VLDRBU8_rq 1156 +#define ARM_MVE_VLDRDU64_qi 1157 +#define ARM_MVE_VLDRDU64_qi_pre 1158 +#define ARM_MVE_VLDRDU64_rq 1159 +#define ARM_MVE_VLDRDU64_rq_u 1160 +#define ARM_MVE_VLDRHS32 1161 +#define ARM_MVE_VLDRHS32_post 1162 +#define ARM_MVE_VLDRHS32_pre 1163 +#define ARM_MVE_VLDRHS32_rq 1164 +#define ARM_MVE_VLDRHS32_rq_u 1165 +#define ARM_MVE_VLDRHU16 1166 +#define ARM_MVE_VLDRHU16_post 1167 +#define ARM_MVE_VLDRHU16_pre 1168 +#define ARM_MVE_VLDRHU16_rq 1169 +#define ARM_MVE_VLDRHU16_rq_u 1170 +#define ARM_MVE_VLDRHU32 1171 +#define ARM_MVE_VLDRHU32_post 1172 +#define ARM_MVE_VLDRHU32_pre 1173 +#define ARM_MVE_VLDRHU32_rq 1174 +#define ARM_MVE_VLDRHU32_rq_u 1175 +#define ARM_MVE_VLDRWU32 1176 +#define ARM_MVE_VLDRWU32_post 1177 +#define ARM_MVE_VLDRWU32_pre 1178 +#define ARM_MVE_VLDRWU32_qi 1179 +#define ARM_MVE_VLDRWU32_qi_pre 1180 +#define ARM_MVE_VLDRWU32_rq 1181 +#define ARM_MVE_VLDRWU32_rq_u 1182 +#define ARM_MVE_VMAXAVs16 1183 +#define ARM_MVE_VMAXAVs32 1184 +#define ARM_MVE_VMAXAVs8 1185 +#define ARM_MVE_VMAXAs16 1186 +#define ARM_MVE_VMAXAs32 1187 +#define ARM_MVE_VMAXAs8 1188 +#define ARM_MVE_VMAXNMAVf16 1189 +#define ARM_MVE_VMAXNMAVf32 1190 +#define ARM_MVE_VMAXNMAf16 1191 +#define ARM_MVE_VMAXNMAf32 1192 +#define ARM_MVE_VMAXNMVf16 1193 +#define ARM_MVE_VMAXNMVf32 1194 +#define ARM_MVE_VMAXNMf16 1195 +#define ARM_MVE_VMAXNMf32 1196 +#define ARM_MVE_VMAXVs16 1197 +#define ARM_MVE_VMAXVs32 1198 +#define ARM_MVE_VMAXVs8 1199 +#define ARM_MVE_VMAXVu16 1200 +#define ARM_MVE_VMAXVu32 1201 +#define ARM_MVE_VMAXVu8 1202 +#define ARM_MVE_VMAXs16 1203 +#define ARM_MVE_VMAXs32 1204 +#define ARM_MVE_VMAXs8 1205 +#define ARM_MVE_VMAXu16 1206 +#define ARM_MVE_VMAXu32 1207 +#define ARM_MVE_VMAXu8 1208 +#define ARM_MVE_VMINAVs16 1209 +#define ARM_MVE_VMINAVs32 1210 +#define ARM_MVE_VMINAVs8 1211 +#define ARM_MVE_VMINAs16 1212 +#define ARM_MVE_VMINAs32 1213 +#define ARM_MVE_VMINAs8 1214 +#define ARM_MVE_VMINNMAVf16 1215 +#define ARM_MVE_VMINNMAVf32 1216 +#define ARM_MVE_VMINNMAf16 1217 +#define ARM_MVE_VMINNMAf32 1218 +#define ARM_MVE_VMINNMVf16 1219 +#define ARM_MVE_VMINNMVf32 1220 +#define ARM_MVE_VMINNMf16 1221 +#define ARM_MVE_VMINNMf32 1222 +#define ARM_MVE_VMINVs16 1223 +#define ARM_MVE_VMINVs32 1224 +#define ARM_MVE_VMINVs8 1225 +#define ARM_MVE_VMINVu16 1226 +#define ARM_MVE_VMINVu32 1227 +#define ARM_MVE_VMINVu8 1228 +#define ARM_MVE_VMINs16 1229 +#define ARM_MVE_VMINs32 1230 +#define ARM_MVE_VMINs8 1231 +#define ARM_MVE_VMINu16 1232 +#define ARM_MVE_VMINu32 1233 +#define ARM_MVE_VMINu8 1234 +#define ARM_MVE_VMLADAVas16 1235 +#define ARM_MVE_VMLADAVas32 1236 +#define ARM_MVE_VMLADAVas8 1237 +#define ARM_MVE_VMLADAVau16 1238 +#define ARM_MVE_VMLADAVau32 1239 +#define ARM_MVE_VMLADAVau8 1240 +#define ARM_MVE_VMLADAVaxs16 1241 +#define ARM_MVE_VMLADAVaxs32 1242 +#define ARM_MVE_VMLADAVaxs8 1243 +#define ARM_MVE_VMLADAVs16 1244 +#define ARM_MVE_VMLADAVs32 1245 +#define ARM_MVE_VMLADAVs8 1246 +#define ARM_MVE_VMLADAVu16 1247 +#define ARM_MVE_VMLADAVu32 1248 +#define ARM_MVE_VMLADAVu8 1249 +#define ARM_MVE_VMLADAVxs16 1250 +#define ARM_MVE_VMLADAVxs32 1251 +#define ARM_MVE_VMLADAVxs8 1252 +#define ARM_MVE_VMLALDAVas16 1253 +#define ARM_MVE_VMLALDAVas32 1254 +#define ARM_MVE_VMLALDAVau16 1255 +#define ARM_MVE_VMLALDAVau32 1256 +#define ARM_MVE_VMLALDAVaxs16 1257 +#define ARM_MVE_VMLALDAVaxs32 1258 +#define ARM_MVE_VMLALDAVs16 1259 +#define ARM_MVE_VMLALDAVs32 1260 +#define ARM_MVE_VMLALDAVu16 1261 +#define ARM_MVE_VMLALDAVu32 1262 +#define ARM_MVE_VMLALDAVxs16 1263 +#define ARM_MVE_VMLALDAVxs32 1264 +#define ARM_MVE_VMLAS_qr_s16 1265 +#define ARM_MVE_VMLAS_qr_s32 1266 +#define ARM_MVE_VMLAS_qr_s8 1267 +#define ARM_MVE_VMLAS_qr_u16 1268 +#define ARM_MVE_VMLAS_qr_u32 1269 +#define ARM_MVE_VMLAS_qr_u8 1270 +#define ARM_MVE_VMLA_qr_s16 1271 +#define ARM_MVE_VMLA_qr_s32 1272 +#define ARM_MVE_VMLA_qr_s8 1273 +#define ARM_MVE_VMLA_qr_u16 1274 +#define ARM_MVE_VMLA_qr_u32 1275 +#define ARM_MVE_VMLA_qr_u8 1276 +#define ARM_MVE_VMLSDAVas16 1277 +#define ARM_MVE_VMLSDAVas32 1278 +#define ARM_MVE_VMLSDAVas8 1279 +#define ARM_MVE_VMLSDAVaxs16 1280 +#define ARM_MVE_VMLSDAVaxs32 1281 +#define ARM_MVE_VMLSDAVaxs8 1282 +#define ARM_MVE_VMLSDAVs16 1283 +#define ARM_MVE_VMLSDAVs32 1284 +#define ARM_MVE_VMLSDAVs8 1285 +#define ARM_MVE_VMLSDAVxs16 1286 +#define ARM_MVE_VMLSDAVxs32 1287 +#define ARM_MVE_VMLSDAVxs8 1288 +#define ARM_MVE_VMLSLDAVas16 1289 +#define ARM_MVE_VMLSLDAVas32 1290 +#define ARM_MVE_VMLSLDAVaxs16 1291 +#define ARM_MVE_VMLSLDAVaxs32 1292 +#define ARM_MVE_VMLSLDAVs16 1293 +#define ARM_MVE_VMLSLDAVs32 1294 +#define ARM_MVE_VMLSLDAVxs16 1295 +#define ARM_MVE_VMLSLDAVxs32 1296 +#define ARM_MVE_VMOVLs16bh 1297 +#define ARM_MVE_VMOVLs16th 1298 +#define ARM_MVE_VMOVLs8bh 1299 +#define ARM_MVE_VMOVLs8th 1300 +#define ARM_MVE_VMOVLu16bh 1301 +#define ARM_MVE_VMOVLu16th 1302 +#define ARM_MVE_VMOVLu8bh 1303 +#define ARM_MVE_VMOVLu8th 1304 +#define ARM_MVE_VMOVNi16bh 1305 +#define ARM_MVE_VMOVNi16th 1306 +#define ARM_MVE_VMOVNi32bh 1307 +#define ARM_MVE_VMOVNi32th 1308 +#define ARM_MVE_VMOV_from_lane_32 1309 +#define ARM_MVE_VMOV_from_lane_s16 1310 +#define ARM_MVE_VMOV_from_lane_s8 1311 +#define ARM_MVE_VMOV_from_lane_u16 1312 +#define ARM_MVE_VMOV_from_lane_u8 1313 +#define ARM_MVE_VMOV_q_rr 1314 +#define ARM_MVE_VMOV_rr_q 1315 +#define ARM_MVE_VMOV_to_lane_16 1316 +#define ARM_MVE_VMOV_to_lane_32 1317 +#define ARM_MVE_VMOV_to_lane_8 1318 +#define ARM_MVE_VMOVimmf32 1319 +#define ARM_MVE_VMOVimmi16 1320 +#define ARM_MVE_VMOVimmi32 1321 +#define ARM_MVE_VMOVimmi64 1322 +#define ARM_MVE_VMOVimmi8 1323 +#define ARM_MVE_VMULHs16 1324 +#define ARM_MVE_VMULHs32 1325 +#define ARM_MVE_VMULHs8 1326 +#define ARM_MVE_VMULHu16 1327 +#define ARM_MVE_VMULHu32 1328 +#define ARM_MVE_VMULHu8 1329 +#define ARM_MVE_VMULLBp16 1330 +#define ARM_MVE_VMULLBp8 1331 +#define ARM_MVE_VMULLBs16 1332 +#define ARM_MVE_VMULLBs32 1333 +#define ARM_MVE_VMULLBs8 1334 +#define ARM_MVE_VMULLBu16 1335 +#define ARM_MVE_VMULLBu32 1336 +#define ARM_MVE_VMULLBu8 1337 +#define ARM_MVE_VMULLTp16 1338 +#define ARM_MVE_VMULLTp8 1339 +#define ARM_MVE_VMULLTs16 1340 +#define ARM_MVE_VMULLTs32 1341 +#define ARM_MVE_VMULLTs8 1342 +#define ARM_MVE_VMULLTu16 1343 +#define ARM_MVE_VMULLTu32 1344 +#define ARM_MVE_VMULLTu8 1345 +#define ARM_MVE_VMUL_qr_f16 1346 +#define ARM_MVE_VMUL_qr_f32 1347 +#define ARM_MVE_VMUL_qr_i16 1348 +#define ARM_MVE_VMUL_qr_i32 1349 +#define ARM_MVE_VMUL_qr_i8 1350 +#define ARM_MVE_VMULf16 1351 +#define ARM_MVE_VMULf32 1352 +#define ARM_MVE_VMULi16 1353 +#define ARM_MVE_VMULi32 1354 +#define ARM_MVE_VMULi8 1355 +#define ARM_MVE_VMVN 1356 +#define ARM_MVE_VMVNimmi16 1357 +#define ARM_MVE_VMVNimmi32 1358 +#define ARM_MVE_VNEGf16 1359 +#define ARM_MVE_VNEGf32 1360 +#define ARM_MVE_VNEGs16 1361 +#define ARM_MVE_VNEGs32 1362 +#define ARM_MVE_VNEGs8 1363 +#define ARM_MVE_VORN 1364 +#define ARM_MVE_VORR 1365 +#define ARM_MVE_VORRimmi16 1366 +#define ARM_MVE_VORRimmi32 1367 +#define ARM_MVE_VPNOT 1368 +#define ARM_MVE_VPSEL 1369 +#define ARM_MVE_VPST 1370 +#define ARM_MVE_VPTv16i8 1371 +#define ARM_MVE_VPTv16i8r 1372 +#define ARM_MVE_VPTv16s8 1373 +#define ARM_MVE_VPTv16s8r 1374 +#define ARM_MVE_VPTv16u8 1375 +#define ARM_MVE_VPTv16u8r 1376 +#define ARM_MVE_VPTv4f32 1377 +#define ARM_MVE_VPTv4f32r 1378 +#define ARM_MVE_VPTv4i32 1379 +#define ARM_MVE_VPTv4i32r 1380 +#define ARM_MVE_VPTv4s32 1381 +#define ARM_MVE_VPTv4s32r 1382 +#define ARM_MVE_VPTv4u32 1383 +#define ARM_MVE_VPTv4u32r 1384 +#define ARM_MVE_VPTv8f16 1385 +#define ARM_MVE_VPTv8f16r 1386 +#define ARM_MVE_VPTv8i16 1387 +#define ARM_MVE_VPTv8i16r 1388 +#define ARM_MVE_VPTv8s16 1389 +#define ARM_MVE_VPTv8s16r 1390 +#define ARM_MVE_VPTv8u16 1391 +#define ARM_MVE_VPTv8u16r 1392 +#define ARM_MVE_VQABSs16 1393 +#define ARM_MVE_VQABSs32 1394 +#define ARM_MVE_VQABSs8 1395 +#define ARM_MVE_VQADD_qr_s16 1396 +#define ARM_MVE_VQADD_qr_s32 1397 +#define ARM_MVE_VQADD_qr_s8 1398 +#define ARM_MVE_VQADD_qr_u16 1399 +#define ARM_MVE_VQADD_qr_u32 1400 +#define ARM_MVE_VQADD_qr_u8 1401 +#define ARM_MVE_VQADDs16 1402 +#define ARM_MVE_VQADDs32 1403 +#define ARM_MVE_VQADDs8 1404 +#define ARM_MVE_VQADDu16 1405 +#define ARM_MVE_VQADDu32 1406 +#define ARM_MVE_VQADDu8 1407 +#define ARM_MVE_VQDMLADHXs16 1408 +#define ARM_MVE_VQDMLADHXs32 1409 +#define ARM_MVE_VQDMLADHXs8 1410 +#define ARM_MVE_VQDMLADHs16 1411 +#define ARM_MVE_VQDMLADHs32 1412 +#define ARM_MVE_VQDMLADHs8 1413 +#define ARM_MVE_VQDMLAH_qrs16 1414 +#define ARM_MVE_VQDMLAH_qrs32 1415 +#define ARM_MVE_VQDMLAH_qrs8 1416 +#define ARM_MVE_VQDMLASH_qrs16 1417 +#define ARM_MVE_VQDMLASH_qrs32 1418 +#define ARM_MVE_VQDMLASH_qrs8 1419 +#define ARM_MVE_VQDMLSDHXs16 1420 +#define ARM_MVE_VQDMLSDHXs32 1421 +#define ARM_MVE_VQDMLSDHXs8 1422 +#define ARM_MVE_VQDMLSDHs16 1423 +#define ARM_MVE_VQDMLSDHs32 1424 +#define ARM_MVE_VQDMLSDHs8 1425 +#define ARM_MVE_VQDMULH_qr_s16 1426 +#define ARM_MVE_VQDMULH_qr_s32 1427 +#define ARM_MVE_VQDMULH_qr_s8 1428 +#define ARM_MVE_VQDMULHi16 1429 +#define ARM_MVE_VQDMULHi32 1430 +#define ARM_MVE_VQDMULHi8 1431 +#define ARM_MVE_VQDMULL_qr_s16bh 1432 +#define ARM_MVE_VQDMULL_qr_s16th 1433 +#define ARM_MVE_VQDMULL_qr_s32bh 1434 +#define ARM_MVE_VQDMULL_qr_s32th 1435 +#define ARM_MVE_VQDMULLs16bh 1436 +#define ARM_MVE_VQDMULLs16th 1437 +#define ARM_MVE_VQDMULLs32bh 1438 +#define ARM_MVE_VQDMULLs32th 1439 +#define ARM_MVE_VQMOVNs16bh 1440 +#define ARM_MVE_VQMOVNs16th 1441 +#define ARM_MVE_VQMOVNs32bh 1442 +#define ARM_MVE_VQMOVNs32th 1443 +#define ARM_MVE_VQMOVNu16bh 1444 +#define ARM_MVE_VQMOVNu16th 1445 +#define ARM_MVE_VQMOVNu32bh 1446 +#define ARM_MVE_VQMOVNu32th 1447 +#define ARM_MVE_VQMOVUNs16bh 1448 +#define ARM_MVE_VQMOVUNs16th 1449 +#define ARM_MVE_VQMOVUNs32bh 1450 +#define ARM_MVE_VQMOVUNs32th 1451 +#define ARM_MVE_VQNEGs16 1452 +#define ARM_MVE_VQNEGs32 1453 +#define ARM_MVE_VQNEGs8 1454 +#define ARM_MVE_VQRDMLADHXs16 1455 +#define ARM_MVE_VQRDMLADHXs32 1456 +#define ARM_MVE_VQRDMLADHXs8 1457 +#define ARM_MVE_VQRDMLADHs16 1458 +#define ARM_MVE_VQRDMLADHs32 1459 +#define ARM_MVE_VQRDMLADHs8 1460 +#define ARM_MVE_VQRDMLAH_qrs16 1461 +#define ARM_MVE_VQRDMLAH_qrs32 1462 +#define ARM_MVE_VQRDMLAH_qrs8 1463 +#define ARM_MVE_VQRDMLASH_qrs16 1464 +#define ARM_MVE_VQRDMLASH_qrs32 1465 +#define ARM_MVE_VQRDMLASH_qrs8 1466 +#define ARM_MVE_VQRDMLSDHXs16 1467 +#define ARM_MVE_VQRDMLSDHXs32 1468 +#define ARM_MVE_VQRDMLSDHXs8 1469 +#define ARM_MVE_VQRDMLSDHs16 1470 +#define ARM_MVE_VQRDMLSDHs32 1471 +#define ARM_MVE_VQRDMLSDHs8 1472 +#define ARM_MVE_VQRDMULH_qr_s16 1473 +#define ARM_MVE_VQRDMULH_qr_s32 1474 +#define ARM_MVE_VQRDMULH_qr_s8 1475 +#define ARM_MVE_VQRDMULHi16 1476 +#define ARM_MVE_VQRDMULHi32 1477 +#define ARM_MVE_VQRDMULHi8 1478 +#define ARM_MVE_VQRSHL_by_vecs16 1479 +#define ARM_MVE_VQRSHL_by_vecs32 1480 +#define ARM_MVE_VQRSHL_by_vecs8 1481 +#define ARM_MVE_VQRSHL_by_vecu16 1482 +#define ARM_MVE_VQRSHL_by_vecu32 1483 +#define ARM_MVE_VQRSHL_by_vecu8 1484 +#define ARM_MVE_VQRSHL_qrs16 1485 +#define ARM_MVE_VQRSHL_qrs32 1486 +#define ARM_MVE_VQRSHL_qrs8 1487 +#define ARM_MVE_VQRSHL_qru16 1488 +#define ARM_MVE_VQRSHL_qru32 1489 +#define ARM_MVE_VQRSHL_qru8 1490 +#define ARM_MVE_VQRSHRNbhs16 1491 +#define ARM_MVE_VQRSHRNbhs32 1492 +#define ARM_MVE_VQRSHRNbhu16 1493 +#define ARM_MVE_VQRSHRNbhu32 1494 +#define ARM_MVE_VQRSHRNths16 1495 +#define ARM_MVE_VQRSHRNths32 1496 +#define ARM_MVE_VQRSHRNthu16 1497 +#define ARM_MVE_VQRSHRNthu32 1498 +#define ARM_MVE_VQRSHRUNs16bh 1499 +#define ARM_MVE_VQRSHRUNs16th 1500 +#define ARM_MVE_VQRSHRUNs32bh 1501 +#define ARM_MVE_VQRSHRUNs32th 1502 +#define ARM_MVE_VQSHLU_imms16 1503 +#define ARM_MVE_VQSHLU_imms32 1504 +#define ARM_MVE_VQSHLU_imms8 1505 +#define ARM_MVE_VQSHL_by_vecs16 1506 +#define ARM_MVE_VQSHL_by_vecs32 1507 +#define ARM_MVE_VQSHL_by_vecs8 1508 +#define ARM_MVE_VQSHL_by_vecu16 1509 +#define ARM_MVE_VQSHL_by_vecu32 1510 +#define ARM_MVE_VQSHL_by_vecu8 1511 +#define ARM_MVE_VQSHL_qrs16 1512 +#define ARM_MVE_VQSHL_qrs32 1513 +#define ARM_MVE_VQSHL_qrs8 1514 +#define ARM_MVE_VQSHL_qru16 1515 +#define ARM_MVE_VQSHL_qru32 1516 +#define ARM_MVE_VQSHL_qru8 1517 +#define ARM_MVE_VQSHLimms16 1518 +#define ARM_MVE_VQSHLimms32 1519 +#define ARM_MVE_VQSHLimms8 1520 +#define ARM_MVE_VQSHLimmu16 1521 +#define ARM_MVE_VQSHLimmu32 1522 +#define ARM_MVE_VQSHLimmu8 1523 +#define ARM_MVE_VQSHRNbhs16 1524 +#define ARM_MVE_VQSHRNbhs32 1525 +#define ARM_MVE_VQSHRNbhu16 1526 +#define ARM_MVE_VQSHRNbhu32 1527 +#define ARM_MVE_VQSHRNths16 1528 +#define ARM_MVE_VQSHRNths32 1529 +#define ARM_MVE_VQSHRNthu16 1530 +#define ARM_MVE_VQSHRNthu32 1531 +#define ARM_MVE_VQSHRUNs16bh 1532 +#define ARM_MVE_VQSHRUNs16th 1533 +#define ARM_MVE_VQSHRUNs32bh 1534 +#define ARM_MVE_VQSHRUNs32th 1535 +#define ARM_MVE_VQSUB_qr_s16 1536 +#define ARM_MVE_VQSUB_qr_s32 1537 +#define ARM_MVE_VQSUB_qr_s8 1538 +#define ARM_MVE_VQSUB_qr_u16 1539 +#define ARM_MVE_VQSUB_qr_u32 1540 +#define ARM_MVE_VQSUB_qr_u8 1541 +#define ARM_MVE_VQSUBs16 1542 +#define ARM_MVE_VQSUBs32 1543 +#define ARM_MVE_VQSUBs8 1544 +#define ARM_MVE_VQSUBu16 1545 +#define ARM_MVE_VQSUBu32 1546 +#define ARM_MVE_VQSUBu8 1547 +#define ARM_MVE_VREV16_8 1548 +#define ARM_MVE_VREV32_16 1549 +#define ARM_MVE_VREV32_8 1550 +#define ARM_MVE_VREV64_16 1551 +#define ARM_MVE_VREV64_32 1552 +#define ARM_MVE_VREV64_8 1553 +#define ARM_MVE_VRHADDs16 1554 +#define ARM_MVE_VRHADDs32 1555 +#define ARM_MVE_VRHADDs8 1556 +#define ARM_MVE_VRHADDu16 1557 +#define ARM_MVE_VRHADDu32 1558 +#define ARM_MVE_VRHADDu8 1559 +#define ARM_MVE_VRINTf16A 1560 +#define ARM_MVE_VRINTf16M 1561 +#define ARM_MVE_VRINTf16N 1562 +#define ARM_MVE_VRINTf16P 1563 +#define ARM_MVE_VRINTf16X 1564 +#define ARM_MVE_VRINTf16Z 1565 +#define ARM_MVE_VRINTf32A 1566 +#define ARM_MVE_VRINTf32M 1567 +#define ARM_MVE_VRINTf32N 1568 +#define ARM_MVE_VRINTf32P 1569 +#define ARM_MVE_VRINTf32X 1570 +#define ARM_MVE_VRINTf32Z 1571 +#define ARM_MVE_VRMLALDAVHas32 1572 +#define ARM_MVE_VRMLALDAVHau32 1573 +#define ARM_MVE_VRMLALDAVHaxs32 1574 +#define ARM_MVE_VRMLALDAVHs32 1575 +#define ARM_MVE_VRMLALDAVHu32 1576 +#define ARM_MVE_VRMLALDAVHxs32 1577 +#define ARM_MVE_VRMLSLDAVHas32 1578 +#define ARM_MVE_VRMLSLDAVHaxs32 1579 +#define ARM_MVE_VRMLSLDAVHs32 1580 +#define ARM_MVE_VRMLSLDAVHxs32 1581 +#define ARM_MVE_VRMULHs16 1582 +#define ARM_MVE_VRMULHs32 1583 +#define ARM_MVE_VRMULHs8 1584 +#define ARM_MVE_VRMULHu16 1585 +#define ARM_MVE_VRMULHu32 1586 +#define ARM_MVE_VRMULHu8 1587 +#define ARM_MVE_VRSHL_by_vecs16 1588 +#define ARM_MVE_VRSHL_by_vecs32 1589 +#define ARM_MVE_VRSHL_by_vecs8 1590 +#define ARM_MVE_VRSHL_by_vecu16 1591 +#define ARM_MVE_VRSHL_by_vecu32 1592 +#define ARM_MVE_VRSHL_by_vecu8 1593 +#define ARM_MVE_VRSHL_qrs16 1594 +#define ARM_MVE_VRSHL_qrs32 1595 +#define ARM_MVE_VRSHL_qrs8 1596 +#define ARM_MVE_VRSHL_qru16 1597 +#define ARM_MVE_VRSHL_qru32 1598 +#define ARM_MVE_VRSHL_qru8 1599 +#define ARM_MVE_VRSHRNi16bh 1600 +#define ARM_MVE_VRSHRNi16th 1601 +#define ARM_MVE_VRSHRNi32bh 1602 +#define ARM_MVE_VRSHRNi32th 1603 +#define ARM_MVE_VRSHR_imms16 1604 +#define ARM_MVE_VRSHR_imms32 1605 +#define ARM_MVE_VRSHR_imms8 1606 +#define ARM_MVE_VRSHR_immu16 1607 +#define ARM_MVE_VRSHR_immu32 1608 +#define ARM_MVE_VRSHR_immu8 1609 +#define ARM_MVE_VSBC 1610 +#define ARM_MVE_VSBCI 1611 +#define ARM_MVE_VSHLC 1612 +#define ARM_MVE_VSHLL_imms16bh 1613 +#define ARM_MVE_VSHLL_imms16th 1614 +#define ARM_MVE_VSHLL_imms8bh 1615 +#define ARM_MVE_VSHLL_imms8th 1616 +#define ARM_MVE_VSHLL_immu16bh 1617 +#define ARM_MVE_VSHLL_immu16th 1618 +#define ARM_MVE_VSHLL_immu8bh 1619 +#define ARM_MVE_VSHLL_immu8th 1620 +#define ARM_MVE_VSHLL_lws16bh 1621 +#define ARM_MVE_VSHLL_lws16th 1622 +#define ARM_MVE_VSHLL_lws8bh 1623 +#define ARM_MVE_VSHLL_lws8th 1624 +#define ARM_MVE_VSHLL_lwu16bh 1625 +#define ARM_MVE_VSHLL_lwu16th 1626 +#define ARM_MVE_VSHLL_lwu8bh 1627 +#define ARM_MVE_VSHLL_lwu8th 1628 +#define ARM_MVE_VSHL_by_vecs16 1629 +#define ARM_MVE_VSHL_by_vecs32 1630 +#define ARM_MVE_VSHL_by_vecs8 1631 +#define ARM_MVE_VSHL_by_vecu16 1632 +#define ARM_MVE_VSHL_by_vecu32 1633 +#define ARM_MVE_VSHL_by_vecu8 1634 +#define ARM_MVE_VSHL_immi16 1635 +#define ARM_MVE_VSHL_immi32 1636 +#define ARM_MVE_VSHL_immi8 1637 +#define ARM_MVE_VSHL_qrs16 1638 +#define ARM_MVE_VSHL_qrs32 1639 +#define ARM_MVE_VSHL_qrs8 1640 +#define ARM_MVE_VSHL_qru16 1641 +#define ARM_MVE_VSHL_qru32 1642 +#define ARM_MVE_VSHL_qru8 1643 +#define ARM_MVE_VSHRNi16bh 1644 +#define ARM_MVE_VSHRNi16th 1645 +#define ARM_MVE_VSHRNi32bh 1646 +#define ARM_MVE_VSHRNi32th 1647 +#define ARM_MVE_VSHR_imms16 1648 +#define ARM_MVE_VSHR_imms32 1649 +#define ARM_MVE_VSHR_imms8 1650 +#define ARM_MVE_VSHR_immu16 1651 +#define ARM_MVE_VSHR_immu32 1652 +#define ARM_MVE_VSHR_immu8 1653 +#define ARM_MVE_VSLIimm16 1654 +#define ARM_MVE_VSLIimm32 1655 +#define ARM_MVE_VSLIimm8 1656 +#define ARM_MVE_VSRIimm16 1657 +#define ARM_MVE_VSRIimm32 1658 +#define ARM_MVE_VSRIimm8 1659 +#define ARM_MVE_VST20_16 1660 +#define ARM_MVE_VST20_16_wb 1661 +#define ARM_MVE_VST20_32 1662 +#define ARM_MVE_VST20_32_wb 1663 +#define ARM_MVE_VST20_8 1664 +#define ARM_MVE_VST20_8_wb 1665 +#define ARM_MVE_VST21_16 1666 +#define ARM_MVE_VST21_16_wb 1667 +#define ARM_MVE_VST21_32 1668 +#define ARM_MVE_VST21_32_wb 1669 +#define ARM_MVE_VST21_8 1670 +#define ARM_MVE_VST21_8_wb 1671 +#define ARM_MVE_VST40_16 1672 +#define ARM_MVE_VST40_16_wb 1673 +#define ARM_MVE_VST40_32 1674 +#define ARM_MVE_VST40_32_wb 1675 +#define ARM_MVE_VST40_8 1676 +#define ARM_MVE_VST40_8_wb 1677 +#define ARM_MVE_VST41_16 1678 +#define ARM_MVE_VST41_16_wb 1679 +#define ARM_MVE_VST41_32 1680 +#define ARM_MVE_VST41_32_wb 1681 +#define ARM_MVE_VST41_8 1682 +#define ARM_MVE_VST41_8_wb 1683 +#define ARM_MVE_VST42_16 1684 +#define ARM_MVE_VST42_16_wb 1685 +#define ARM_MVE_VST42_32 1686 +#define ARM_MVE_VST42_32_wb 1687 +#define ARM_MVE_VST42_8 1688 +#define ARM_MVE_VST42_8_wb 1689 +#define ARM_MVE_VST43_16 1690 +#define ARM_MVE_VST43_16_wb 1691 +#define ARM_MVE_VST43_32 1692 +#define ARM_MVE_VST43_32_wb 1693 +#define ARM_MVE_VST43_8 1694 +#define ARM_MVE_VST43_8_wb 1695 +#define ARM_MVE_VSTRB16 1696 +#define ARM_MVE_VSTRB16_post 1697 +#define ARM_MVE_VSTRB16_pre 1698 +#define ARM_MVE_VSTRB16_rq 1699 +#define ARM_MVE_VSTRB32 1700 +#define ARM_MVE_VSTRB32_post 1701 +#define ARM_MVE_VSTRB32_pre 1702 +#define ARM_MVE_VSTRB32_rq 1703 +#define ARM_MVE_VSTRB8_rq 1704 +#define ARM_MVE_VSTRBU8 1705 +#define ARM_MVE_VSTRBU8_post 1706 +#define ARM_MVE_VSTRBU8_pre 1707 +#define ARM_MVE_VSTRD64_qi 1708 +#define ARM_MVE_VSTRD64_qi_pre 1709 +#define ARM_MVE_VSTRD64_rq 1710 +#define ARM_MVE_VSTRD64_rq_u 1711 +#define ARM_MVE_VSTRH16_rq 1712 +#define ARM_MVE_VSTRH16_rq_u 1713 +#define ARM_MVE_VSTRH32 1714 +#define ARM_MVE_VSTRH32_post 1715 +#define ARM_MVE_VSTRH32_pre 1716 +#define ARM_MVE_VSTRH32_rq 1717 +#define ARM_MVE_VSTRH32_rq_u 1718 +#define ARM_MVE_VSTRHU16 1719 +#define ARM_MVE_VSTRHU16_post 1720 +#define ARM_MVE_VSTRHU16_pre 1721 +#define ARM_MVE_VSTRW32_qi 1722 +#define ARM_MVE_VSTRW32_qi_pre 1723 +#define ARM_MVE_VSTRW32_rq 1724 +#define ARM_MVE_VSTRW32_rq_u 1725 +#define ARM_MVE_VSTRWU32 1726 +#define ARM_MVE_VSTRWU32_post 1727 +#define ARM_MVE_VSTRWU32_pre 1728 +#define ARM_MVE_VSUB_qr_f16 1729 +#define ARM_MVE_VSUB_qr_f32 1730 +#define ARM_MVE_VSUB_qr_i16 1731 +#define ARM_MVE_VSUB_qr_i32 1732 +#define ARM_MVE_VSUB_qr_i8 1733 +#define ARM_MVE_VSUBf16 1734 +#define ARM_MVE_VSUBf32 1735 +#define ARM_MVE_VSUBi16 1736 +#define ARM_MVE_VSUBi32 1737 +#define ARM_MVE_VSUBi8 1738 +#define ARM_MVE_WLSTP_16 1739 +#define ARM_MVE_WLSTP_32 1740 +#define ARM_MVE_WLSTP_64 1741 +#define ARM_MVE_WLSTP_8 1742 +#define ARM_MVNi 1743 +#define ARM_MVNr 1744 +#define ARM_MVNsi 1745 +#define ARM_MVNsr 1746 +#define ARM_NEON_VMAXNMNDf 1747 +#define ARM_NEON_VMAXNMNDh 1748 +#define ARM_NEON_VMAXNMNQf 1749 +#define ARM_NEON_VMAXNMNQh 1750 +#define ARM_NEON_VMINNMNDf 1751 +#define ARM_NEON_VMINNMNDh 1752 +#define ARM_NEON_VMINNMNQf 1753 +#define ARM_NEON_VMINNMNQh 1754 +#define ARM_ORRri 1755 +#define ARM_ORRrr 1756 +#define ARM_ORRrsi 1757 +#define ARM_ORRrsr 1758 +#define ARM_PKHBT 1759 +#define ARM_PKHTB 1760 +#define ARM_PLDWi12 1761 +#define ARM_PLDWrs 1762 +#define ARM_PLDi12 1763 +#define ARM_PLDrs 1764 +#define ARM_PLIi12 1765 +#define ARM_PLIrs 1766 +#define ARM_QADD 1767 +#define ARM_QADD16 1768 +#define ARM_QADD8 1769 +#define ARM_QASX 1770 +#define ARM_QDADD 1771 +#define ARM_QDSUB 1772 +#define ARM_QSAX 1773 +#define ARM_QSUB 1774 +#define ARM_QSUB16 1775 +#define ARM_QSUB8 1776 +#define ARM_RBIT 1777 +#define ARM_REV 1778 +#define ARM_REV16 1779 +#define ARM_REVSH 1780 +#define ARM_RFEDA 1781 +#define ARM_RFEDA_UPD 1782 +#define ARM_RFEDB 1783 +#define ARM_RFEDB_UPD 1784 +#define ARM_RFEIA 1785 +#define ARM_RFEIA_UPD 1786 +#define ARM_RFEIB 1787 +#define ARM_RFEIB_UPD 1788 +#define ARM_RSBri 1789 +#define ARM_RSBrr 1790 +#define ARM_RSBrsi 1791 +#define ARM_RSBrsr 1792 +#define ARM_RSCri 1793 +#define ARM_RSCrr 1794 +#define ARM_RSCrsi 1795 +#define ARM_RSCrsr 1796 +#define ARM_SADD16 1797 +#define ARM_SADD8 1798 +#define ARM_SASX 1799 +#define ARM_SB 1800 +#define ARM_SBCri 1801 +#define ARM_SBCrr 1802 +#define ARM_SBCrsi 1803 +#define ARM_SBCrsr 1804 +#define ARM_SBFX 1805 +#define ARM_SDIV 1806 +#define ARM_SEL 1807 +#define ARM_SETEND 1808 +#define ARM_SETPAN 1809 +#define ARM_SHA1C 1810 +#define ARM_SHA1H 1811 +#define ARM_SHA1M 1812 +#define ARM_SHA1P 1813 +#define ARM_SHA1SU0 1814 +#define ARM_SHA1SU1 1815 +#define ARM_SHA256H 1816 +#define ARM_SHA256H2 1817 +#define ARM_SHA256SU0 1818 +#define ARM_SHA256SU1 1819 +#define ARM_SHADD16 1820 +#define ARM_SHADD8 1821 +#define ARM_SHASX 1822 +#define ARM_SHSAX 1823 +#define ARM_SHSUB16 1824 +#define ARM_SHSUB8 1825 +#define ARM_SMC 1826 +#define ARM_SMLABB 1827 +#define ARM_SMLABT 1828 +#define ARM_SMLAD 1829 +#define ARM_SMLADX 1830 +#define ARM_SMLAL 1831 +#define ARM_SMLALBB 1832 +#define ARM_SMLALBT 1833 +#define ARM_SMLALD 1834 +#define ARM_SMLALDX 1835 +#define ARM_SMLALTB 1836 +#define ARM_SMLALTT 1837 +#define ARM_SMLATB 1838 +#define ARM_SMLATT 1839 +#define ARM_SMLAWB 1840 +#define ARM_SMLAWT 1841 +#define ARM_SMLSD 1842 +#define ARM_SMLSDX 1843 +#define ARM_SMLSLD 1844 +#define ARM_SMLSLDX 1845 +#define ARM_SMMLA 1846 +#define ARM_SMMLAR 1847 +#define ARM_SMMLS 1848 +#define ARM_SMMLSR 1849 +#define ARM_SMMUL 1850 +#define ARM_SMMULR 1851 +#define ARM_SMUAD 1852 +#define ARM_SMUADX 1853 +#define ARM_SMULBB 1854 +#define ARM_SMULBT 1855 +#define ARM_SMULL 1856 +#define ARM_SMULTB 1857 +#define ARM_SMULTT 1858 +#define ARM_SMULWB 1859 +#define ARM_SMULWT 1860 +#define ARM_SMUSD 1861 +#define ARM_SMUSDX 1862 +#define ARM_SRSDA 1863 +#define ARM_SRSDA_UPD 1864 +#define ARM_SRSDB 1865 +#define ARM_SRSDB_UPD 1866 +#define ARM_SRSIA 1867 +#define ARM_SRSIA_UPD 1868 +#define ARM_SRSIB 1869 +#define ARM_SRSIB_UPD 1870 +#define ARM_SSAT 1871 +#define ARM_SSAT16 1872 +#define ARM_SSAX 1873 +#define ARM_SSUB16 1874 +#define ARM_SSUB8 1875 +#define ARM_STC2L_OFFSET 1876 +#define ARM_STC2L_OPTION 1877 +#define ARM_STC2L_POST 1878 +#define ARM_STC2L_PRE 1879 +#define ARM_STC2_OFFSET 1880 +#define ARM_STC2_OPTION 1881 +#define ARM_STC2_POST 1882 +#define ARM_STC2_PRE 1883 +#define ARM_STCL_OFFSET 1884 +#define ARM_STCL_OPTION 1885 +#define ARM_STCL_POST 1886 +#define ARM_STCL_PRE 1887 +#define ARM_STC_OFFSET 1888 +#define ARM_STC_OPTION 1889 +#define ARM_STC_POST 1890 +#define ARM_STC_PRE 1891 +#define ARM_STL 1892 +#define ARM_STLB 1893 +#define ARM_STLEX 1894 +#define ARM_STLEXB 1895 +#define ARM_STLEXD 1896 +#define ARM_STLEXH 1897 +#define ARM_STLH 1898 +#define ARM_STMDA 1899 +#define ARM_STMDA_UPD 1900 +#define ARM_STMDB 1901 +#define ARM_STMDB_UPD 1902 +#define ARM_STMIA 1903 +#define ARM_STMIA_UPD 1904 +#define ARM_STMIB 1905 +#define ARM_STMIB_UPD 1906 +#define ARM_STRBT_POST_IMM 1907 +#define ARM_STRBT_POST_REG 1908 +#define ARM_STRB_POST_IMM 1909 +#define ARM_STRB_POST_REG 1910 +#define ARM_STRB_PRE_IMM 1911 +#define ARM_STRB_PRE_REG 1912 +#define ARM_STRBi12 1913 +#define ARM_STRBrs 1914 +#define ARM_STRD 1915 +#define ARM_STRD_POST 1916 +#define ARM_STRD_PRE 1917 +#define ARM_STREX 1918 +#define ARM_STREXB 1919 +#define ARM_STREXD 1920 +#define ARM_STREXH 1921 +#define ARM_STRH 1922 +#define ARM_STRHTi 1923 +#define ARM_STRHTr 1924 +#define ARM_STRH_POST 1925 +#define ARM_STRH_PRE 1926 +#define ARM_STRT_POST_IMM 1927 +#define ARM_STRT_POST_REG 1928 +#define ARM_STR_POST_IMM 1929 +#define ARM_STR_POST_REG 1930 +#define ARM_STR_PRE_IMM 1931 +#define ARM_STR_PRE_REG 1932 +#define ARM_STRi12 1933 +#define ARM_STRrs 1934 +#define ARM_SUBri 1935 +#define ARM_SUBrr 1936 +#define ARM_SUBrsi 1937 +#define ARM_SUBrsr 1938 +#define ARM_SVC 1939 +#define ARM_SWP 1940 +#define ARM_SWPB 1941 +#define ARM_SXTAB 1942 +#define ARM_SXTAB16 1943 +#define ARM_SXTAH 1944 +#define ARM_SXTB 1945 +#define ARM_SXTB16 1946 +#define ARM_SXTH 1947 +#define ARM_TEQri 1948 +#define ARM_TEQrr 1949 +#define ARM_TEQrsi 1950 +#define ARM_TEQrsr 1951 +#define ARM_TRAP 1952 +#define ARM_TRAPNaCl 1953 +#define ARM_TSB 1954 +#define ARM_TSTri 1955 +#define ARM_TSTrr 1956 +#define ARM_TSTrsi 1957 +#define ARM_TSTrsr 1958 +#define ARM_UADD16 1959 +#define ARM_UADD8 1960 +#define ARM_UASX 1961 +#define ARM_UBFX 1962 +#define ARM_UDF 1963 +#define ARM_UDIV 1964 +#define ARM_UHADD16 1965 +#define ARM_UHADD8 1966 +#define ARM_UHASX 1967 +#define ARM_UHSAX 1968 +#define ARM_UHSUB16 1969 +#define ARM_UHSUB8 1970 +#define ARM_UMAAL 1971 +#define ARM_UMLAL 1972 +#define ARM_UMULL 1973 +#define ARM_UQADD16 1974 +#define ARM_UQADD8 1975 +#define ARM_UQASX 1976 +#define ARM_UQSAX 1977 +#define ARM_UQSUB16 1978 +#define ARM_UQSUB8 1979 +#define ARM_USAD8 1980 +#define ARM_USADA8 1981 +#define ARM_USAT 1982 +#define ARM_USAT16 1983 +#define ARM_USAX 1984 +#define ARM_USUB16 1985 +#define ARM_USUB8 1986 +#define ARM_UXTAB 1987 +#define ARM_UXTAB16 1988 +#define ARM_UXTAH 1989 +#define ARM_UXTB 1990 +#define ARM_UXTB16 1991 +#define ARM_UXTH 1992 +#define ARM_VABALsv2i64 1993 +#define ARM_VABALsv4i32 1994 +#define ARM_VABALsv8i16 1995 +#define ARM_VABALuv2i64 1996 +#define ARM_VABALuv4i32 1997 +#define ARM_VABALuv8i16 1998 +#define ARM_VABAsv16i8 1999 +#define ARM_VABAsv2i32 2000 +#define ARM_VABAsv4i16 2001 +#define ARM_VABAsv4i32 2002 +#define ARM_VABAsv8i16 2003 +#define ARM_VABAsv8i8 2004 +#define ARM_VABAuv16i8 2005 +#define ARM_VABAuv2i32 2006 +#define ARM_VABAuv4i16 2007 +#define ARM_VABAuv4i32 2008 +#define ARM_VABAuv8i16 2009 +#define ARM_VABAuv8i8 2010 +#define ARM_VABDLsv2i64 2011 +#define ARM_VABDLsv4i32 2012 +#define ARM_VABDLsv8i16 2013 +#define ARM_VABDLuv2i64 2014 +#define ARM_VABDLuv4i32 2015 +#define ARM_VABDLuv8i16 2016 +#define ARM_VABDfd 2017 +#define ARM_VABDfq 2018 +#define ARM_VABDhd 2019 +#define ARM_VABDhq 2020 +#define ARM_VABDsv16i8 2021 +#define ARM_VABDsv2i32 2022 +#define ARM_VABDsv4i16 2023 +#define ARM_VABDsv4i32 2024 +#define ARM_VABDsv8i16 2025 +#define ARM_VABDsv8i8 2026 +#define ARM_VABDuv16i8 2027 +#define ARM_VABDuv2i32 2028 +#define ARM_VABDuv4i16 2029 +#define ARM_VABDuv4i32 2030 +#define ARM_VABDuv8i16 2031 +#define ARM_VABDuv8i8 2032 +#define ARM_VABSD 2033 +#define ARM_VABSH 2034 +#define ARM_VABSS 2035 +#define ARM_VABSfd 2036 +#define ARM_VABSfq 2037 +#define ARM_VABShd 2038 +#define ARM_VABShq 2039 +#define ARM_VABSv16i8 2040 +#define ARM_VABSv2i32 2041 +#define ARM_VABSv4i16 2042 +#define ARM_VABSv4i32 2043 +#define ARM_VABSv8i16 2044 +#define ARM_VABSv8i8 2045 +#define ARM_VACGEfd 2046 +#define ARM_VACGEfq 2047 +#define ARM_VACGEhd 2048 +#define ARM_VACGEhq 2049 +#define ARM_VACGTfd 2050 +#define ARM_VACGTfq 2051 +#define ARM_VACGThd 2052 +#define ARM_VACGThq 2053 +#define ARM_VADDD 2054 +#define ARM_VADDH 2055 +#define ARM_VADDHNv2i32 2056 +#define ARM_VADDHNv4i16 2057 +#define ARM_VADDHNv8i8 2058 +#define ARM_VADDLsv2i64 2059 +#define ARM_VADDLsv4i32 2060 +#define ARM_VADDLsv8i16 2061 +#define ARM_VADDLuv2i64 2062 +#define ARM_VADDLuv4i32 2063 +#define ARM_VADDLuv8i16 2064 +#define ARM_VADDS 2065 +#define ARM_VADDWsv2i64 2066 +#define ARM_VADDWsv4i32 2067 +#define ARM_VADDWsv8i16 2068 +#define ARM_VADDWuv2i64 2069 +#define ARM_VADDWuv4i32 2070 +#define ARM_VADDWuv8i16 2071 +#define ARM_VADDfd 2072 +#define ARM_VADDfq 2073 +#define ARM_VADDhd 2074 +#define ARM_VADDhq 2075 +#define ARM_VADDv16i8 2076 +#define ARM_VADDv1i64 2077 +#define ARM_VADDv2i32 2078 +#define ARM_VADDv2i64 2079 +#define ARM_VADDv4i16 2080 +#define ARM_VADDv4i32 2081 +#define ARM_VADDv8i16 2082 +#define ARM_VADDv8i8 2083 +#define ARM_VANDd 2084 +#define ARM_VANDq 2085 +#define ARM_VBF16MALBQ 2086 +#define ARM_VBF16MALBQI 2087 +#define ARM_VBF16MALTQ 2088 +#define ARM_VBF16MALTQI 2089 +#define ARM_VBICd 2090 +#define ARM_VBICiv2i32 2091 +#define ARM_VBICiv4i16 2092 +#define ARM_VBICiv4i32 2093 +#define ARM_VBICiv8i16 2094 +#define ARM_VBICq 2095 +#define ARM_VBIFd 2096 +#define ARM_VBIFq 2097 +#define ARM_VBITd 2098 +#define ARM_VBITq 2099 +#define ARM_VBSLd 2100 +#define ARM_VBSLq 2101 +#define ARM_VBSPd 2102 +#define ARM_VBSPq 2103 +#define ARM_VCADDv2f32 2104 +#define ARM_VCADDv4f16 2105 +#define ARM_VCADDv4f32 2106 +#define ARM_VCADDv8f16 2107 +#define ARM_VCEQfd 2108 +#define ARM_VCEQfq 2109 +#define ARM_VCEQhd 2110 +#define ARM_VCEQhq 2111 +#define ARM_VCEQv16i8 2112 +#define ARM_VCEQv2i32 2113 +#define ARM_VCEQv4i16 2114 +#define ARM_VCEQv4i32 2115 +#define ARM_VCEQv8i16 2116 +#define ARM_VCEQv8i8 2117 +#define ARM_VCEQzv16i8 2118 +#define ARM_VCEQzv2f32 2119 +#define ARM_VCEQzv2i32 2120 +#define ARM_VCEQzv4f16 2121 +#define ARM_VCEQzv4f32 2122 +#define ARM_VCEQzv4i16 2123 +#define ARM_VCEQzv4i32 2124 +#define ARM_VCEQzv8f16 2125 +#define ARM_VCEQzv8i16 2126 +#define ARM_VCEQzv8i8 2127 +#define ARM_VCGEfd 2128 +#define ARM_VCGEfq 2129 +#define ARM_VCGEhd 2130 +#define ARM_VCGEhq 2131 +#define ARM_VCGEsv16i8 2132 +#define ARM_VCGEsv2i32 2133 +#define ARM_VCGEsv4i16 2134 +#define ARM_VCGEsv4i32 2135 +#define ARM_VCGEsv8i16 2136 +#define ARM_VCGEsv8i8 2137 +#define ARM_VCGEuv16i8 2138 +#define ARM_VCGEuv2i32 2139 +#define ARM_VCGEuv4i16 2140 +#define ARM_VCGEuv4i32 2141 +#define ARM_VCGEuv8i16 2142 +#define ARM_VCGEuv8i8 2143 +#define ARM_VCGEzv16i8 2144 +#define ARM_VCGEzv2f32 2145 +#define ARM_VCGEzv2i32 2146 +#define ARM_VCGEzv4f16 2147 +#define ARM_VCGEzv4f32 2148 +#define ARM_VCGEzv4i16 2149 +#define ARM_VCGEzv4i32 2150 +#define ARM_VCGEzv8f16 2151 +#define ARM_VCGEzv8i16 2152 +#define ARM_VCGEzv8i8 2153 +#define ARM_VCGTfd 2154 +#define ARM_VCGTfq 2155 +#define ARM_VCGThd 2156 +#define ARM_VCGThq 2157 +#define ARM_VCGTsv16i8 2158 +#define ARM_VCGTsv2i32 2159 +#define ARM_VCGTsv4i16 2160 +#define ARM_VCGTsv4i32 2161 +#define ARM_VCGTsv8i16 2162 +#define ARM_VCGTsv8i8 2163 +#define ARM_VCGTuv16i8 2164 +#define ARM_VCGTuv2i32 2165 +#define ARM_VCGTuv4i16 2166 +#define ARM_VCGTuv4i32 2167 +#define ARM_VCGTuv8i16 2168 +#define ARM_VCGTuv8i8 2169 +#define ARM_VCGTzv16i8 2170 +#define ARM_VCGTzv2f32 2171 +#define ARM_VCGTzv2i32 2172 +#define ARM_VCGTzv4f16 2173 +#define ARM_VCGTzv4f32 2174 +#define ARM_VCGTzv4i16 2175 +#define ARM_VCGTzv4i32 2176 +#define ARM_VCGTzv8f16 2177 +#define ARM_VCGTzv8i16 2178 +#define ARM_VCGTzv8i8 2179 +#define ARM_VCLEzv16i8 2180 +#define ARM_VCLEzv2f32 2181 +#define ARM_VCLEzv2i32 2182 +#define ARM_VCLEzv4f16 2183 +#define ARM_VCLEzv4f32 2184 +#define ARM_VCLEzv4i16 2185 +#define ARM_VCLEzv4i32 2186 +#define ARM_VCLEzv8f16 2187 +#define ARM_VCLEzv8i16 2188 +#define ARM_VCLEzv8i8 2189 +#define ARM_VCLSv16i8 2190 +#define ARM_VCLSv2i32 2191 +#define ARM_VCLSv4i16 2192 +#define ARM_VCLSv4i32 2193 +#define ARM_VCLSv8i16 2194 +#define ARM_VCLSv8i8 2195 +#define ARM_VCLTzv16i8 2196 +#define ARM_VCLTzv2f32 2197 +#define ARM_VCLTzv2i32 2198 +#define ARM_VCLTzv4f16 2199 +#define ARM_VCLTzv4f32 2200 +#define ARM_VCLTzv4i16 2201 +#define ARM_VCLTzv4i32 2202 +#define ARM_VCLTzv8f16 2203 +#define ARM_VCLTzv8i16 2204 +#define ARM_VCLTzv8i8 2205 +#define ARM_VCLZv16i8 2206 +#define ARM_VCLZv2i32 2207 +#define ARM_VCLZv4i16 2208 +#define ARM_VCLZv4i32 2209 +#define ARM_VCLZv8i16 2210 +#define ARM_VCLZv8i8 2211 +#define ARM_VCMLAv2f32 2212 +#define ARM_VCMLAv2f32_indexed 2213 +#define ARM_VCMLAv4f16 2214 +#define ARM_VCMLAv4f16_indexed 2215 +#define ARM_VCMLAv4f32 2216 +#define ARM_VCMLAv4f32_indexed 2217 +#define ARM_VCMLAv8f16 2218 +#define ARM_VCMLAv8f16_indexed 2219 +#define ARM_VCMPD 2220 +#define ARM_VCMPED 2221 +#define ARM_VCMPEH 2222 +#define ARM_VCMPES 2223 +#define ARM_VCMPEZD 2224 +#define ARM_VCMPEZH 2225 +#define ARM_VCMPEZS 2226 +#define ARM_VCMPH 2227 +#define ARM_VCMPS 2228 +#define ARM_VCMPZD 2229 +#define ARM_VCMPZH 2230 +#define ARM_VCMPZS 2231 +#define ARM_VCNTd 2232 +#define ARM_VCNTq 2233 +#define ARM_VCVTANSDf 2234 +#define ARM_VCVTANSDh 2235 +#define ARM_VCVTANSQf 2236 +#define ARM_VCVTANSQh 2237 +#define ARM_VCVTANUDf 2238 +#define ARM_VCVTANUDh 2239 +#define ARM_VCVTANUQf 2240 +#define ARM_VCVTANUQh 2241 +#define ARM_VCVTASD 2242 +#define ARM_VCVTASH 2243 +#define ARM_VCVTASS 2244 +#define ARM_VCVTAUD 2245 +#define ARM_VCVTAUH 2246 +#define ARM_VCVTAUS 2247 +#define ARM_VCVTBDH 2248 +#define ARM_VCVTBHD 2249 +#define ARM_VCVTBHS 2250 +#define ARM_VCVTBSH 2251 +#define ARM_VCVTDS 2252 +#define ARM_VCVTMNSDf 2253 +#define ARM_VCVTMNSDh 2254 +#define ARM_VCVTMNSQf 2255 +#define ARM_VCVTMNSQh 2256 +#define ARM_VCVTMNUDf 2257 +#define ARM_VCVTMNUDh 2258 +#define ARM_VCVTMNUQf 2259 +#define ARM_VCVTMNUQh 2260 +#define ARM_VCVTMSD 2261 +#define ARM_VCVTMSH 2262 +#define ARM_VCVTMSS 2263 +#define ARM_VCVTMUD 2264 +#define ARM_VCVTMUH 2265 +#define ARM_VCVTMUS 2266 +#define ARM_VCVTNNSDf 2267 +#define ARM_VCVTNNSDh 2268 +#define ARM_VCVTNNSQf 2269 +#define ARM_VCVTNNSQh 2270 +#define ARM_VCVTNNUDf 2271 +#define ARM_VCVTNNUDh 2272 +#define ARM_VCVTNNUQf 2273 +#define ARM_VCVTNNUQh 2274 +#define ARM_VCVTNSD 2275 +#define ARM_VCVTNSH 2276 +#define ARM_VCVTNSS 2277 +#define ARM_VCVTNUD 2278 +#define ARM_VCVTNUH 2279 +#define ARM_VCVTNUS 2280 +#define ARM_VCVTPNSDf 2281 +#define ARM_VCVTPNSDh 2282 +#define ARM_VCVTPNSQf 2283 +#define ARM_VCVTPNSQh 2284 +#define ARM_VCVTPNUDf 2285 +#define ARM_VCVTPNUDh 2286 +#define ARM_VCVTPNUQf 2287 +#define ARM_VCVTPNUQh 2288 +#define ARM_VCVTPSD 2289 +#define ARM_VCVTPSH 2290 +#define ARM_VCVTPSS 2291 +#define ARM_VCVTPUD 2292 +#define ARM_VCVTPUH 2293 +#define ARM_VCVTPUS 2294 +#define ARM_VCVTSD 2295 +#define ARM_VCVTTDH 2296 +#define ARM_VCVTTHD 2297 +#define ARM_VCVTTHS 2298 +#define ARM_VCVTTSH 2299 +#define ARM_VCVTf2h 2300 +#define ARM_VCVTf2sd 2301 +#define ARM_VCVTf2sq 2302 +#define ARM_VCVTf2ud 2303 +#define ARM_VCVTf2uq 2304 +#define ARM_VCVTf2xsd 2305 +#define ARM_VCVTf2xsq 2306 +#define ARM_VCVTf2xud 2307 +#define ARM_VCVTf2xuq 2308 +#define ARM_VCVTh2f 2309 +#define ARM_VCVTh2sd 2310 +#define ARM_VCVTh2sq 2311 +#define ARM_VCVTh2ud 2312 +#define ARM_VCVTh2uq 2313 +#define ARM_VCVTh2xsd 2314 +#define ARM_VCVTh2xsq 2315 +#define ARM_VCVTh2xud 2316 +#define ARM_VCVTh2xuq 2317 +#define ARM_VCVTs2fd 2318 +#define ARM_VCVTs2fq 2319 +#define ARM_VCVTs2hd 2320 +#define ARM_VCVTs2hq 2321 +#define ARM_VCVTu2fd 2322 +#define ARM_VCVTu2fq 2323 +#define ARM_VCVTu2hd 2324 +#define ARM_VCVTu2hq 2325 +#define ARM_VCVTxs2fd 2326 +#define ARM_VCVTxs2fq 2327 +#define ARM_VCVTxs2hd 2328 +#define ARM_VCVTxs2hq 2329 +#define ARM_VCVTxu2fd 2330 +#define ARM_VCVTxu2fq 2331 +#define ARM_VCVTxu2hd 2332 +#define ARM_VCVTxu2hq 2333 +#define ARM_VDIVD 2334 +#define ARM_VDIVH 2335 +#define ARM_VDIVS 2336 +#define ARM_VDUP16d 2337 +#define ARM_VDUP16q 2338 +#define ARM_VDUP32d 2339 +#define ARM_VDUP32q 2340 +#define ARM_VDUP8d 2341 +#define ARM_VDUP8q 2342 +#define ARM_VDUPLN16d 2343 +#define ARM_VDUPLN16q 2344 +#define ARM_VDUPLN32d 2345 +#define ARM_VDUPLN32q 2346 +#define ARM_VDUPLN8d 2347 +#define ARM_VDUPLN8q 2348 +#define ARM_VEORd 2349 +#define ARM_VEORq 2350 +#define ARM_VEXTd16 2351 +#define ARM_VEXTd32 2352 +#define ARM_VEXTd8 2353 +#define ARM_VEXTq16 2354 +#define ARM_VEXTq32 2355 +#define ARM_VEXTq64 2356 +#define ARM_VEXTq8 2357 +#define ARM_VFMAD 2358 +#define ARM_VFMAH 2359 +#define ARM_VFMALD 2360 +#define ARM_VFMALDI 2361 +#define ARM_VFMALQ 2362 +#define ARM_VFMALQI 2363 +#define ARM_VFMAS 2364 +#define ARM_VFMAfd 2365 +#define ARM_VFMAfq 2366 +#define ARM_VFMAhd 2367 +#define ARM_VFMAhq 2368 +#define ARM_VFMSD 2369 +#define ARM_VFMSH 2370 +#define ARM_VFMSLD 2371 +#define ARM_VFMSLDI 2372 +#define ARM_VFMSLQ 2373 +#define ARM_VFMSLQI 2374 +#define ARM_VFMSS 2375 +#define ARM_VFMSfd 2376 +#define ARM_VFMSfq 2377 +#define ARM_VFMShd 2378 +#define ARM_VFMShq 2379 +#define ARM_VFNMAD 2380 +#define ARM_VFNMAH 2381 +#define ARM_VFNMAS 2382 +#define ARM_VFNMSD 2383 +#define ARM_VFNMSH 2384 +#define ARM_VFNMSS 2385 +#define ARM_VFP_VMAXNMD 2386 +#define ARM_VFP_VMAXNMH 2387 +#define ARM_VFP_VMAXNMS 2388 +#define ARM_VFP_VMINNMD 2389 +#define ARM_VFP_VMINNMH 2390 +#define ARM_VFP_VMINNMS 2391 +#define ARM_VGETLNi32 2392 +#define ARM_VGETLNs16 2393 +#define ARM_VGETLNs8 2394 +#define ARM_VGETLNu16 2395 +#define ARM_VGETLNu8 2396 +#define ARM_VHADDsv16i8 2397 +#define ARM_VHADDsv2i32 2398 +#define ARM_VHADDsv4i16 2399 +#define ARM_VHADDsv4i32 2400 +#define ARM_VHADDsv8i16 2401 +#define ARM_VHADDsv8i8 2402 +#define ARM_VHADDuv16i8 2403 +#define ARM_VHADDuv2i32 2404 +#define ARM_VHADDuv4i16 2405 +#define ARM_VHADDuv4i32 2406 +#define ARM_VHADDuv8i16 2407 +#define ARM_VHADDuv8i8 2408 +#define ARM_VHSUBsv16i8 2409 +#define ARM_VHSUBsv2i32 2410 +#define ARM_VHSUBsv4i16 2411 +#define ARM_VHSUBsv4i32 2412 +#define ARM_VHSUBsv8i16 2413 +#define ARM_VHSUBsv8i8 2414 +#define ARM_VHSUBuv16i8 2415 +#define ARM_VHSUBuv2i32 2416 +#define ARM_VHSUBuv4i16 2417 +#define ARM_VHSUBuv4i32 2418 +#define ARM_VHSUBuv8i16 2419 +#define ARM_VHSUBuv8i8 2420 +#define ARM_VINSH 2421 +#define ARM_VJCVT 2422 +#define ARM_VLD1DUPd16 2423 +#define ARM_VLD1DUPd16wb_fixed 2424 +#define ARM_VLD1DUPd16wb_register 2425 +#define ARM_VLD1DUPd32 2426 +#define ARM_VLD1DUPd32wb_fixed 2427 +#define ARM_VLD1DUPd32wb_register 2428 +#define ARM_VLD1DUPd8 2429 +#define ARM_VLD1DUPd8wb_fixed 2430 +#define ARM_VLD1DUPd8wb_register 2431 +#define ARM_VLD1DUPq16 2432 +#define ARM_VLD1DUPq16wb_fixed 2433 +#define ARM_VLD1DUPq16wb_register 2434 +#define ARM_VLD1DUPq32 2435 +#define ARM_VLD1DUPq32wb_fixed 2436 +#define ARM_VLD1DUPq32wb_register 2437 +#define ARM_VLD1DUPq8 2438 +#define ARM_VLD1DUPq8wb_fixed 2439 +#define ARM_VLD1DUPq8wb_register 2440 +#define ARM_VLD1LNd16 2441 +#define ARM_VLD1LNd16_UPD 2442 +#define ARM_VLD1LNd32 2443 +#define ARM_VLD1LNd32_UPD 2444 +#define ARM_VLD1LNd8 2445 +#define ARM_VLD1LNd8_UPD 2446 +#define ARM_VLD1LNq16Pseudo 2447 +#define ARM_VLD1LNq16Pseudo_UPD 2448 +#define ARM_VLD1LNq32Pseudo 2449 +#define ARM_VLD1LNq32Pseudo_UPD 2450 +#define ARM_VLD1LNq8Pseudo 2451 +#define ARM_VLD1LNq8Pseudo_UPD 2452 +#define ARM_VLD1d16 2453 +#define ARM_VLD1d16Q 2454 +#define ARM_VLD1d16QPseudo 2455 +#define ARM_VLD1d16QPseudoWB_fixed 2456 +#define ARM_VLD1d16QPseudoWB_register 2457 +#define ARM_VLD1d16Qwb_fixed 2458 +#define ARM_VLD1d16Qwb_register 2459 +#define ARM_VLD1d16T 2460 +#define ARM_VLD1d16TPseudo 2461 +#define ARM_VLD1d16TPseudoWB_fixed 2462 +#define ARM_VLD1d16TPseudoWB_register 2463 +#define ARM_VLD1d16Twb_fixed 2464 +#define ARM_VLD1d16Twb_register 2465 +#define ARM_VLD1d16wb_fixed 2466 +#define ARM_VLD1d16wb_register 2467 +#define ARM_VLD1d32 2468 +#define ARM_VLD1d32Q 2469 +#define ARM_VLD1d32QPseudo 2470 +#define ARM_VLD1d32QPseudoWB_fixed 2471 +#define ARM_VLD1d32QPseudoWB_register 2472 +#define ARM_VLD1d32Qwb_fixed 2473 +#define ARM_VLD1d32Qwb_register 2474 +#define ARM_VLD1d32T 2475 +#define ARM_VLD1d32TPseudo 2476 +#define ARM_VLD1d32TPseudoWB_fixed 2477 +#define ARM_VLD1d32TPseudoWB_register 2478 +#define ARM_VLD1d32Twb_fixed 2479 +#define ARM_VLD1d32Twb_register 2480 +#define ARM_VLD1d32wb_fixed 2481 +#define ARM_VLD1d32wb_register 2482 +#define ARM_VLD1d64 2483 +#define ARM_VLD1d64Q 2484 +#define ARM_VLD1d64QPseudo 2485 +#define ARM_VLD1d64QPseudoWB_fixed 2486 +#define ARM_VLD1d64QPseudoWB_register 2487 +#define ARM_VLD1d64Qwb_fixed 2488 +#define ARM_VLD1d64Qwb_register 2489 +#define ARM_VLD1d64T 2490 +#define ARM_VLD1d64TPseudo 2491 +#define ARM_VLD1d64TPseudoWB_fixed 2492 +#define ARM_VLD1d64TPseudoWB_register 2493 +#define ARM_VLD1d64Twb_fixed 2494 +#define ARM_VLD1d64Twb_register 2495 +#define ARM_VLD1d64wb_fixed 2496 +#define ARM_VLD1d64wb_register 2497 +#define ARM_VLD1d8 2498 +#define ARM_VLD1d8Q 2499 +#define ARM_VLD1d8QPseudo 2500 +#define ARM_VLD1d8QPseudoWB_fixed 2501 +#define ARM_VLD1d8QPseudoWB_register 2502 +#define ARM_VLD1d8Qwb_fixed 2503 +#define ARM_VLD1d8Qwb_register 2504 +#define ARM_VLD1d8T 2505 +#define ARM_VLD1d8TPseudo 2506 +#define ARM_VLD1d8TPseudoWB_fixed 2507 +#define ARM_VLD1d8TPseudoWB_register 2508 +#define ARM_VLD1d8Twb_fixed 2509 +#define ARM_VLD1d8Twb_register 2510 +#define ARM_VLD1d8wb_fixed 2511 +#define ARM_VLD1d8wb_register 2512 +#define ARM_VLD1q16 2513 +#define ARM_VLD1q16HighQPseudo 2514 +#define ARM_VLD1q16HighQPseudo_UPD 2515 +#define ARM_VLD1q16HighTPseudo 2516 +#define ARM_VLD1q16HighTPseudo_UPD 2517 +#define ARM_VLD1q16LowQPseudo_UPD 2518 +#define ARM_VLD1q16LowTPseudo_UPD 2519 +#define ARM_VLD1q16wb_fixed 2520 +#define ARM_VLD1q16wb_register 2521 +#define ARM_VLD1q32 2522 +#define ARM_VLD1q32HighQPseudo 2523 +#define ARM_VLD1q32HighQPseudo_UPD 2524 +#define ARM_VLD1q32HighTPseudo 2525 +#define ARM_VLD1q32HighTPseudo_UPD 2526 +#define ARM_VLD1q32LowQPseudo_UPD 2527 +#define ARM_VLD1q32LowTPseudo_UPD 2528 +#define ARM_VLD1q32wb_fixed 2529 +#define ARM_VLD1q32wb_register 2530 +#define ARM_VLD1q64 2531 +#define ARM_VLD1q64HighQPseudo 2532 +#define ARM_VLD1q64HighQPseudo_UPD 2533 +#define ARM_VLD1q64HighTPseudo 2534 +#define ARM_VLD1q64HighTPseudo_UPD 2535 +#define ARM_VLD1q64LowQPseudo_UPD 2536 +#define ARM_VLD1q64LowTPseudo_UPD 2537 +#define ARM_VLD1q64wb_fixed 2538 +#define ARM_VLD1q64wb_register 2539 +#define ARM_VLD1q8 2540 +#define ARM_VLD1q8HighQPseudo 2541 +#define ARM_VLD1q8HighQPseudo_UPD 2542 +#define ARM_VLD1q8HighTPseudo 2543 +#define ARM_VLD1q8HighTPseudo_UPD 2544 +#define ARM_VLD1q8LowQPseudo_UPD 2545 +#define ARM_VLD1q8LowTPseudo_UPD 2546 +#define ARM_VLD1q8wb_fixed 2547 +#define ARM_VLD1q8wb_register 2548 +#define ARM_VLD2DUPd16 2549 +#define ARM_VLD2DUPd16wb_fixed 2550 +#define ARM_VLD2DUPd16wb_register 2551 +#define ARM_VLD2DUPd16x2 2552 +#define ARM_VLD2DUPd16x2wb_fixed 2553 +#define ARM_VLD2DUPd16x2wb_register 2554 +#define ARM_VLD2DUPd32 2555 +#define ARM_VLD2DUPd32wb_fixed 2556 +#define ARM_VLD2DUPd32wb_register 2557 +#define ARM_VLD2DUPd32x2 2558 +#define ARM_VLD2DUPd32x2wb_fixed 2559 +#define ARM_VLD2DUPd32x2wb_register 2560 +#define ARM_VLD2DUPd8 2561 +#define ARM_VLD2DUPd8wb_fixed 2562 +#define ARM_VLD2DUPd8wb_register 2563 +#define ARM_VLD2DUPd8x2 2564 +#define ARM_VLD2DUPd8x2wb_fixed 2565 +#define ARM_VLD2DUPd8x2wb_register 2566 +#define ARM_VLD2DUPq16EvenPseudo 2567 +#define ARM_VLD2DUPq16OddPseudo 2568 +#define ARM_VLD2DUPq16OddPseudoWB_fixed 2569 +#define ARM_VLD2DUPq16OddPseudoWB_register 2570 +#define ARM_VLD2DUPq32EvenPseudo 2571 +#define ARM_VLD2DUPq32OddPseudo 2572 +#define ARM_VLD2DUPq32OddPseudoWB_fixed 2573 +#define ARM_VLD2DUPq32OddPseudoWB_register 2574 +#define ARM_VLD2DUPq8EvenPseudo 2575 +#define ARM_VLD2DUPq8OddPseudo 2576 +#define ARM_VLD2DUPq8OddPseudoWB_fixed 2577 +#define ARM_VLD2DUPq8OddPseudoWB_register 2578 +#define ARM_VLD2LNd16 2579 +#define ARM_VLD2LNd16Pseudo 2580 +#define ARM_VLD2LNd16Pseudo_UPD 2581 +#define ARM_VLD2LNd16_UPD 2582 +#define ARM_VLD2LNd32 2583 +#define ARM_VLD2LNd32Pseudo 2584 +#define ARM_VLD2LNd32Pseudo_UPD 2585 +#define ARM_VLD2LNd32_UPD 2586 +#define ARM_VLD2LNd8 2587 +#define ARM_VLD2LNd8Pseudo 2588 +#define ARM_VLD2LNd8Pseudo_UPD 2589 +#define ARM_VLD2LNd8_UPD 2590 +#define ARM_VLD2LNq16 2591 +#define ARM_VLD2LNq16Pseudo 2592 +#define ARM_VLD2LNq16Pseudo_UPD 2593 +#define ARM_VLD2LNq16_UPD 2594 +#define ARM_VLD2LNq32 2595 +#define ARM_VLD2LNq32Pseudo 2596 +#define ARM_VLD2LNq32Pseudo_UPD 2597 +#define ARM_VLD2LNq32_UPD 2598 +#define ARM_VLD2b16 2599 +#define ARM_VLD2b16wb_fixed 2600 +#define ARM_VLD2b16wb_register 2601 +#define ARM_VLD2b32 2602 +#define ARM_VLD2b32wb_fixed 2603 +#define ARM_VLD2b32wb_register 2604 +#define ARM_VLD2b8 2605 +#define ARM_VLD2b8wb_fixed 2606 +#define ARM_VLD2b8wb_register 2607 +#define ARM_VLD2d16 2608 +#define ARM_VLD2d16wb_fixed 2609 +#define ARM_VLD2d16wb_register 2610 +#define ARM_VLD2d32 2611 +#define ARM_VLD2d32wb_fixed 2612 +#define ARM_VLD2d32wb_register 2613 +#define ARM_VLD2d8 2614 +#define ARM_VLD2d8wb_fixed 2615 +#define ARM_VLD2d8wb_register 2616 +#define ARM_VLD2q16 2617 +#define ARM_VLD2q16Pseudo 2618 +#define ARM_VLD2q16PseudoWB_fixed 2619 +#define ARM_VLD2q16PseudoWB_register 2620 +#define ARM_VLD2q16wb_fixed 2621 +#define ARM_VLD2q16wb_register 2622 +#define ARM_VLD2q32 2623 +#define ARM_VLD2q32Pseudo 2624 +#define ARM_VLD2q32PseudoWB_fixed 2625 +#define ARM_VLD2q32PseudoWB_register 2626 +#define ARM_VLD2q32wb_fixed 2627 +#define ARM_VLD2q32wb_register 2628 +#define ARM_VLD2q8 2629 +#define ARM_VLD2q8Pseudo 2630 +#define ARM_VLD2q8PseudoWB_fixed 2631 +#define ARM_VLD2q8PseudoWB_register 2632 +#define ARM_VLD2q8wb_fixed 2633 +#define ARM_VLD2q8wb_register 2634 +#define ARM_VLD3DUPd16 2635 +#define ARM_VLD3DUPd16Pseudo 2636 +#define ARM_VLD3DUPd16Pseudo_UPD 2637 +#define ARM_VLD3DUPd16_UPD 2638 +#define ARM_VLD3DUPd32 2639 +#define ARM_VLD3DUPd32Pseudo 2640 +#define ARM_VLD3DUPd32Pseudo_UPD 2641 +#define ARM_VLD3DUPd32_UPD 2642 +#define ARM_VLD3DUPd8 2643 +#define ARM_VLD3DUPd8Pseudo 2644 +#define ARM_VLD3DUPd8Pseudo_UPD 2645 +#define ARM_VLD3DUPd8_UPD 2646 +#define ARM_VLD3DUPq16 2647 +#define ARM_VLD3DUPq16EvenPseudo 2648 +#define ARM_VLD3DUPq16OddPseudo 2649 +#define ARM_VLD3DUPq16OddPseudo_UPD 2650 +#define ARM_VLD3DUPq16_UPD 2651 +#define ARM_VLD3DUPq32 2652 +#define ARM_VLD3DUPq32EvenPseudo 2653 +#define ARM_VLD3DUPq32OddPseudo 2654 +#define ARM_VLD3DUPq32OddPseudo_UPD 2655 +#define ARM_VLD3DUPq32_UPD 2656 +#define ARM_VLD3DUPq8 2657 +#define ARM_VLD3DUPq8EvenPseudo 2658 +#define ARM_VLD3DUPq8OddPseudo 2659 +#define ARM_VLD3DUPq8OddPseudo_UPD 2660 +#define ARM_VLD3DUPq8_UPD 2661 +#define ARM_VLD3LNd16 2662 +#define ARM_VLD3LNd16Pseudo 2663 +#define ARM_VLD3LNd16Pseudo_UPD 2664 +#define ARM_VLD3LNd16_UPD 2665 +#define ARM_VLD3LNd32 2666 +#define ARM_VLD3LNd32Pseudo 2667 +#define ARM_VLD3LNd32Pseudo_UPD 2668 +#define ARM_VLD3LNd32_UPD 2669 +#define ARM_VLD3LNd8 2670 +#define ARM_VLD3LNd8Pseudo 2671 +#define ARM_VLD3LNd8Pseudo_UPD 2672 +#define ARM_VLD3LNd8_UPD 2673 +#define ARM_VLD3LNq16 2674 +#define ARM_VLD3LNq16Pseudo 2675 +#define ARM_VLD3LNq16Pseudo_UPD 2676 +#define ARM_VLD3LNq16_UPD 2677 +#define ARM_VLD3LNq32 2678 +#define ARM_VLD3LNq32Pseudo 2679 +#define ARM_VLD3LNq32Pseudo_UPD 2680 +#define ARM_VLD3LNq32_UPD 2681 +#define ARM_VLD3d16 2682 +#define ARM_VLD3d16Pseudo 2683 +#define ARM_VLD3d16Pseudo_UPD 2684 +#define ARM_VLD3d16_UPD 2685 +#define ARM_VLD3d32 2686 +#define ARM_VLD3d32Pseudo 2687 +#define ARM_VLD3d32Pseudo_UPD 2688 +#define ARM_VLD3d32_UPD 2689 +#define ARM_VLD3d8 2690 +#define ARM_VLD3d8Pseudo 2691 +#define ARM_VLD3d8Pseudo_UPD 2692 +#define ARM_VLD3d8_UPD 2693 +#define ARM_VLD3q16 2694 +#define ARM_VLD3q16Pseudo_UPD 2695 +#define ARM_VLD3q16_UPD 2696 +#define ARM_VLD3q16oddPseudo 2697 +#define ARM_VLD3q16oddPseudo_UPD 2698 +#define ARM_VLD3q32 2699 +#define ARM_VLD3q32Pseudo_UPD 2700 +#define ARM_VLD3q32_UPD 2701 +#define ARM_VLD3q32oddPseudo 2702 +#define ARM_VLD3q32oddPseudo_UPD 2703 +#define ARM_VLD3q8 2704 +#define ARM_VLD3q8Pseudo_UPD 2705 +#define ARM_VLD3q8_UPD 2706 +#define ARM_VLD3q8oddPseudo 2707 +#define ARM_VLD3q8oddPseudo_UPD 2708 +#define ARM_VLD4DUPd16 2709 +#define ARM_VLD4DUPd16Pseudo 2710 +#define ARM_VLD4DUPd16Pseudo_UPD 2711 +#define ARM_VLD4DUPd16_UPD 2712 +#define ARM_VLD4DUPd32 2713 +#define ARM_VLD4DUPd32Pseudo 2714 +#define ARM_VLD4DUPd32Pseudo_UPD 2715 +#define ARM_VLD4DUPd32_UPD 2716 +#define ARM_VLD4DUPd8 2717 +#define ARM_VLD4DUPd8Pseudo 2718 +#define ARM_VLD4DUPd8Pseudo_UPD 2719 +#define ARM_VLD4DUPd8_UPD 2720 +#define ARM_VLD4DUPq16 2721 +#define ARM_VLD4DUPq16EvenPseudo 2722 +#define ARM_VLD4DUPq16OddPseudo 2723 +#define ARM_VLD4DUPq16OddPseudo_UPD 2724 +#define ARM_VLD4DUPq16_UPD 2725 +#define ARM_VLD4DUPq32 2726 +#define ARM_VLD4DUPq32EvenPseudo 2727 +#define ARM_VLD4DUPq32OddPseudo 2728 +#define ARM_VLD4DUPq32OddPseudo_UPD 2729 +#define ARM_VLD4DUPq32_UPD 2730 +#define ARM_VLD4DUPq8 2731 +#define ARM_VLD4DUPq8EvenPseudo 2732 +#define ARM_VLD4DUPq8OddPseudo 2733 +#define ARM_VLD4DUPq8OddPseudo_UPD 2734 +#define ARM_VLD4DUPq8_UPD 2735 +#define ARM_VLD4LNd16 2736 +#define ARM_VLD4LNd16Pseudo 2737 +#define ARM_VLD4LNd16Pseudo_UPD 2738 +#define ARM_VLD4LNd16_UPD 2739 +#define ARM_VLD4LNd32 2740 +#define ARM_VLD4LNd32Pseudo 2741 +#define ARM_VLD4LNd32Pseudo_UPD 2742 +#define ARM_VLD4LNd32_UPD 2743 +#define ARM_VLD4LNd8 2744 +#define ARM_VLD4LNd8Pseudo 2745 +#define ARM_VLD4LNd8Pseudo_UPD 2746 +#define ARM_VLD4LNd8_UPD 2747 +#define ARM_VLD4LNq16 2748 +#define ARM_VLD4LNq16Pseudo 2749 +#define ARM_VLD4LNq16Pseudo_UPD 2750 +#define ARM_VLD4LNq16_UPD 2751 +#define ARM_VLD4LNq32 2752 +#define ARM_VLD4LNq32Pseudo 2753 +#define ARM_VLD4LNq32Pseudo_UPD 2754 +#define ARM_VLD4LNq32_UPD 2755 +#define ARM_VLD4d16 2756 +#define ARM_VLD4d16Pseudo 2757 +#define ARM_VLD4d16Pseudo_UPD 2758 +#define ARM_VLD4d16_UPD 2759 +#define ARM_VLD4d32 2760 +#define ARM_VLD4d32Pseudo 2761 +#define ARM_VLD4d32Pseudo_UPD 2762 +#define ARM_VLD4d32_UPD 2763 +#define ARM_VLD4d8 2764 +#define ARM_VLD4d8Pseudo 2765 +#define ARM_VLD4d8Pseudo_UPD 2766 +#define ARM_VLD4d8_UPD 2767 +#define ARM_VLD4q16 2768 +#define ARM_VLD4q16Pseudo_UPD 2769 +#define ARM_VLD4q16_UPD 2770 +#define ARM_VLD4q16oddPseudo 2771 +#define ARM_VLD4q16oddPseudo_UPD 2772 +#define ARM_VLD4q32 2773 +#define ARM_VLD4q32Pseudo_UPD 2774 +#define ARM_VLD4q32_UPD 2775 +#define ARM_VLD4q32oddPseudo 2776 +#define ARM_VLD4q32oddPseudo_UPD 2777 +#define ARM_VLD4q8 2778 +#define ARM_VLD4q8Pseudo_UPD 2779 +#define ARM_VLD4q8_UPD 2780 +#define ARM_VLD4q8oddPseudo 2781 +#define ARM_VLD4q8oddPseudo_UPD 2782 +#define ARM_VLDMDDB_UPD 2783 +#define ARM_VLDMDIA 2784 +#define ARM_VLDMDIA_UPD 2785 +#define ARM_VLDMQIA 2786 +#define ARM_VLDMSDB_UPD 2787 +#define ARM_VLDMSIA 2788 +#define ARM_VLDMSIA_UPD 2789 +#define ARM_VLDRD 2790 +#define ARM_VLDRH 2791 +#define ARM_VLDRS 2792 +#define ARM_VLDR_FPCXTNS_off 2793 +#define ARM_VLDR_FPCXTNS_post 2794 +#define ARM_VLDR_FPCXTNS_pre 2795 +#define ARM_VLDR_FPCXTS_off 2796 +#define ARM_VLDR_FPCXTS_post 2797 +#define ARM_VLDR_FPCXTS_pre 2798 +#define ARM_VLDR_FPSCR_NZCVQC_off 2799 +#define ARM_VLDR_FPSCR_NZCVQC_post 2800 +#define ARM_VLDR_FPSCR_NZCVQC_pre 2801 +#define ARM_VLDR_FPSCR_off 2802 +#define ARM_VLDR_FPSCR_post 2803 +#define ARM_VLDR_FPSCR_pre 2804 +#define ARM_VLDR_P0_off 2805 +#define ARM_VLDR_P0_post 2806 +#define ARM_VLDR_P0_pre 2807 +#define ARM_VLDR_VPR_off 2808 +#define ARM_VLDR_VPR_post 2809 +#define ARM_VLDR_VPR_pre 2810 +#define ARM_VLLDM 2811 +#define ARM_VLSTM 2812 +#define ARM_VMAXfd 2813 +#define ARM_VMAXfq 2814 +#define ARM_VMAXhd 2815 +#define ARM_VMAXhq 2816 +#define ARM_VMAXsv16i8 2817 +#define ARM_VMAXsv2i32 2818 +#define ARM_VMAXsv4i16 2819 +#define ARM_VMAXsv4i32 2820 +#define ARM_VMAXsv8i16 2821 +#define ARM_VMAXsv8i8 2822 +#define ARM_VMAXuv16i8 2823 +#define ARM_VMAXuv2i32 2824 +#define ARM_VMAXuv4i16 2825 +#define ARM_VMAXuv4i32 2826 +#define ARM_VMAXuv8i16 2827 +#define ARM_VMAXuv8i8 2828 +#define ARM_VMINfd 2829 +#define ARM_VMINfq 2830 +#define ARM_VMINhd 2831 +#define ARM_VMINhq 2832 +#define ARM_VMINsv16i8 2833 +#define ARM_VMINsv2i32 2834 +#define ARM_VMINsv4i16 2835 +#define ARM_VMINsv4i32 2836 +#define ARM_VMINsv8i16 2837 +#define ARM_VMINsv8i8 2838 +#define ARM_VMINuv16i8 2839 +#define ARM_VMINuv2i32 2840 +#define ARM_VMINuv4i16 2841 +#define ARM_VMINuv4i32 2842 +#define ARM_VMINuv8i16 2843 +#define ARM_VMINuv8i8 2844 +#define ARM_VMLAD 2845 +#define ARM_VMLAH 2846 +#define ARM_VMLALslsv2i32 2847 +#define ARM_VMLALslsv4i16 2848 +#define ARM_VMLALsluv2i32 2849 +#define ARM_VMLALsluv4i16 2850 +#define ARM_VMLALsv2i64 2851 +#define ARM_VMLALsv4i32 2852 +#define ARM_VMLALsv8i16 2853 +#define ARM_VMLALuv2i64 2854 +#define ARM_VMLALuv4i32 2855 +#define ARM_VMLALuv8i16 2856 +#define ARM_VMLAS 2857 +#define ARM_VMLAfd 2858 +#define ARM_VMLAfq 2859 +#define ARM_VMLAhd 2860 +#define ARM_VMLAhq 2861 +#define ARM_VMLAslfd 2862 +#define ARM_VMLAslfq 2863 +#define ARM_VMLAslhd 2864 +#define ARM_VMLAslhq 2865 +#define ARM_VMLAslv2i32 2866 +#define ARM_VMLAslv4i16 2867 +#define ARM_VMLAslv4i32 2868 +#define ARM_VMLAslv8i16 2869 +#define ARM_VMLAv16i8 2870 +#define ARM_VMLAv2i32 2871 +#define ARM_VMLAv4i16 2872 +#define ARM_VMLAv4i32 2873 +#define ARM_VMLAv8i16 2874 +#define ARM_VMLAv8i8 2875 +#define ARM_VMLSD 2876 +#define ARM_VMLSH 2877 +#define ARM_VMLSLslsv2i32 2878 +#define ARM_VMLSLslsv4i16 2879 +#define ARM_VMLSLsluv2i32 2880 +#define ARM_VMLSLsluv4i16 2881 +#define ARM_VMLSLsv2i64 2882 +#define ARM_VMLSLsv4i32 2883 +#define ARM_VMLSLsv8i16 2884 +#define ARM_VMLSLuv2i64 2885 +#define ARM_VMLSLuv4i32 2886 +#define ARM_VMLSLuv8i16 2887 +#define ARM_VMLSS 2888 +#define ARM_VMLSfd 2889 +#define ARM_VMLSfq 2890 +#define ARM_VMLShd 2891 +#define ARM_VMLShq 2892 +#define ARM_VMLSslfd 2893 +#define ARM_VMLSslfq 2894 +#define ARM_VMLSslhd 2895 +#define ARM_VMLSslhq 2896 +#define ARM_VMLSslv2i32 2897 +#define ARM_VMLSslv4i16 2898 +#define ARM_VMLSslv4i32 2899 +#define ARM_VMLSslv8i16 2900 +#define ARM_VMLSv16i8 2901 +#define ARM_VMLSv2i32 2902 +#define ARM_VMLSv4i16 2903 +#define ARM_VMLSv4i32 2904 +#define ARM_VMLSv8i16 2905 +#define ARM_VMLSv8i8 2906 +#define ARM_VMMLA 2907 +#define ARM_VMOVD 2908 +#define ARM_VMOVDRR 2909 +#define ARM_VMOVH 2910 +#define ARM_VMOVHR 2911 +#define ARM_VMOVLsv2i64 2912 +#define ARM_VMOVLsv4i32 2913 +#define ARM_VMOVLsv8i16 2914 +#define ARM_VMOVLuv2i64 2915 +#define ARM_VMOVLuv4i32 2916 +#define ARM_VMOVLuv8i16 2917 +#define ARM_VMOVNv2i32 2918 +#define ARM_VMOVNv4i16 2919 +#define ARM_VMOVNv8i8 2920 +#define ARM_VMOVRH 2921 +#define ARM_VMOVRRD 2922 +#define ARM_VMOVRRS 2923 +#define ARM_VMOVRS 2924 +#define ARM_VMOVS 2925 +#define ARM_VMOVSR 2926 +#define ARM_VMOVSRR 2927 +#define ARM_VMOVv16i8 2928 +#define ARM_VMOVv1i64 2929 +#define ARM_VMOVv2f32 2930 +#define ARM_VMOVv2i32 2931 +#define ARM_VMOVv2i64 2932 +#define ARM_VMOVv4f32 2933 +#define ARM_VMOVv4i16 2934 +#define ARM_VMOVv4i32 2935 +#define ARM_VMOVv8i16 2936 +#define ARM_VMOVv8i8 2937 +#define ARM_VMRS 2938 +#define ARM_VMRS_FPCXTNS 2939 +#define ARM_VMRS_FPCXTS 2940 +#define ARM_VMRS_FPEXC 2941 +#define ARM_VMRS_FPINST 2942 +#define ARM_VMRS_FPINST2 2943 +#define ARM_VMRS_FPSCR_NZCVQC 2944 +#define ARM_VMRS_FPSID 2945 +#define ARM_VMRS_MVFR0 2946 +#define ARM_VMRS_MVFR1 2947 +#define ARM_VMRS_MVFR2 2948 +#define ARM_VMRS_P0 2949 +#define ARM_VMRS_VPR 2950 +#define ARM_VMSR 2951 +#define ARM_VMSR_FPCXTNS 2952 +#define ARM_VMSR_FPCXTS 2953 +#define ARM_VMSR_FPEXC 2954 +#define ARM_VMSR_FPINST 2955 +#define ARM_VMSR_FPINST2 2956 +#define ARM_VMSR_FPSCR_NZCVQC 2957 +#define ARM_VMSR_FPSID 2958 +#define ARM_VMSR_P0 2959 +#define ARM_VMSR_VPR 2960 +#define ARM_VMULD 2961 +#define ARM_VMULH 2962 +#define ARM_VMULLp64 2963 +#define ARM_VMULLp8 2964 +#define ARM_VMULLslsv2i32 2965 +#define ARM_VMULLslsv4i16 2966 +#define ARM_VMULLsluv2i32 2967 +#define ARM_VMULLsluv4i16 2968 +#define ARM_VMULLsv2i64 2969 +#define ARM_VMULLsv4i32 2970 +#define ARM_VMULLsv8i16 2971 +#define ARM_VMULLuv2i64 2972 +#define ARM_VMULLuv4i32 2973 +#define ARM_VMULLuv8i16 2974 +#define ARM_VMULS 2975 +#define ARM_VMULfd 2976 +#define ARM_VMULfq 2977 +#define ARM_VMULhd 2978 +#define ARM_VMULhq 2979 +#define ARM_VMULpd 2980 +#define ARM_VMULpq 2981 +#define ARM_VMULslfd 2982 +#define ARM_VMULslfq 2983 +#define ARM_VMULslhd 2984 +#define ARM_VMULslhq 2985 +#define ARM_VMULslv2i32 2986 +#define ARM_VMULslv4i16 2987 +#define ARM_VMULslv4i32 2988 +#define ARM_VMULslv8i16 2989 +#define ARM_VMULv16i8 2990 +#define ARM_VMULv2i32 2991 +#define ARM_VMULv4i16 2992 +#define ARM_VMULv4i32 2993 +#define ARM_VMULv8i16 2994 +#define ARM_VMULv8i8 2995 +#define ARM_VMVNd 2996 +#define ARM_VMVNq 2997 +#define ARM_VMVNv2i32 2998 +#define ARM_VMVNv4i16 2999 +#define ARM_VMVNv4i32 3000 +#define ARM_VMVNv8i16 3001 +#define ARM_VNEGD 3002 +#define ARM_VNEGH 3003 +#define ARM_VNEGS 3004 +#define ARM_VNEGf32q 3005 +#define ARM_VNEGfd 3006 +#define ARM_VNEGhd 3007 +#define ARM_VNEGhq 3008 +#define ARM_VNEGs16d 3009 +#define ARM_VNEGs16q 3010 +#define ARM_VNEGs32d 3011 +#define ARM_VNEGs32q 3012 +#define ARM_VNEGs8d 3013 +#define ARM_VNEGs8q 3014 +#define ARM_VNMLAD 3015 +#define ARM_VNMLAH 3016 +#define ARM_VNMLAS 3017 +#define ARM_VNMLSD 3018 +#define ARM_VNMLSH 3019 +#define ARM_VNMLSS 3020 +#define ARM_VNMULD 3021 +#define ARM_VNMULH 3022 +#define ARM_VNMULS 3023 +#define ARM_VORNd 3024 +#define ARM_VORNq 3025 +#define ARM_VORRd 3026 +#define ARM_VORRiv2i32 3027 +#define ARM_VORRiv4i16 3028 +#define ARM_VORRiv4i32 3029 +#define ARM_VORRiv8i16 3030 +#define ARM_VORRq 3031 +#define ARM_VPADALsv16i8 3032 +#define ARM_VPADALsv2i32 3033 +#define ARM_VPADALsv4i16 3034 +#define ARM_VPADALsv4i32 3035 +#define ARM_VPADALsv8i16 3036 +#define ARM_VPADALsv8i8 3037 +#define ARM_VPADALuv16i8 3038 +#define ARM_VPADALuv2i32 3039 +#define ARM_VPADALuv4i16 3040 +#define ARM_VPADALuv4i32 3041 +#define ARM_VPADALuv8i16 3042 +#define ARM_VPADALuv8i8 3043 +#define ARM_VPADDLsv16i8 3044 +#define ARM_VPADDLsv2i32 3045 +#define ARM_VPADDLsv4i16 3046 +#define ARM_VPADDLsv4i32 3047 +#define ARM_VPADDLsv8i16 3048 +#define ARM_VPADDLsv8i8 3049 +#define ARM_VPADDLuv16i8 3050 +#define ARM_VPADDLuv2i32 3051 +#define ARM_VPADDLuv4i16 3052 +#define ARM_VPADDLuv4i32 3053 +#define ARM_VPADDLuv8i16 3054 +#define ARM_VPADDLuv8i8 3055 +#define ARM_VPADDf 3056 +#define ARM_VPADDh 3057 +#define ARM_VPADDi16 3058 +#define ARM_VPADDi32 3059 +#define ARM_VPADDi8 3060 +#define ARM_VPMAXf 3061 +#define ARM_VPMAXh 3062 +#define ARM_VPMAXs16 3063 +#define ARM_VPMAXs32 3064 +#define ARM_VPMAXs8 3065 +#define ARM_VPMAXu16 3066 +#define ARM_VPMAXu32 3067 +#define ARM_VPMAXu8 3068 +#define ARM_VPMINf 3069 +#define ARM_VPMINh 3070 +#define ARM_VPMINs16 3071 +#define ARM_VPMINs32 3072 +#define ARM_VPMINs8 3073 +#define ARM_VPMINu16 3074 +#define ARM_VPMINu32 3075 +#define ARM_VPMINu8 3076 +#define ARM_VQABSv16i8 3077 +#define ARM_VQABSv2i32 3078 +#define ARM_VQABSv4i16 3079 +#define ARM_VQABSv4i32 3080 +#define ARM_VQABSv8i16 3081 +#define ARM_VQABSv8i8 3082 +#define ARM_VQADDsv16i8 3083 +#define ARM_VQADDsv1i64 3084 +#define ARM_VQADDsv2i32 3085 +#define ARM_VQADDsv2i64 3086 +#define ARM_VQADDsv4i16 3087 +#define ARM_VQADDsv4i32 3088 +#define ARM_VQADDsv8i16 3089 +#define ARM_VQADDsv8i8 3090 +#define ARM_VQADDuv16i8 3091 +#define ARM_VQADDuv1i64 3092 +#define ARM_VQADDuv2i32 3093 +#define ARM_VQADDuv2i64 3094 +#define ARM_VQADDuv4i16 3095 +#define ARM_VQADDuv4i32 3096 +#define ARM_VQADDuv8i16 3097 +#define ARM_VQADDuv8i8 3098 +#define ARM_VQDMLALslv2i32 3099 +#define ARM_VQDMLALslv4i16 3100 +#define ARM_VQDMLALv2i64 3101 +#define ARM_VQDMLALv4i32 3102 +#define ARM_VQDMLSLslv2i32 3103 +#define ARM_VQDMLSLslv4i16 3104 +#define ARM_VQDMLSLv2i64 3105 +#define ARM_VQDMLSLv4i32 3106 +#define ARM_VQDMULHslv2i32 3107 +#define ARM_VQDMULHslv4i16 3108 +#define ARM_VQDMULHslv4i32 3109 +#define ARM_VQDMULHslv8i16 3110 +#define ARM_VQDMULHv2i32 3111 +#define ARM_VQDMULHv4i16 3112 +#define ARM_VQDMULHv4i32 3113 +#define ARM_VQDMULHv8i16 3114 +#define ARM_VQDMULLslv2i32 3115 +#define ARM_VQDMULLslv4i16 3116 +#define ARM_VQDMULLv2i64 3117 +#define ARM_VQDMULLv4i32 3118 +#define ARM_VQMOVNsuv2i32 3119 +#define ARM_VQMOVNsuv4i16 3120 +#define ARM_VQMOVNsuv8i8 3121 +#define ARM_VQMOVNsv2i32 3122 +#define ARM_VQMOVNsv4i16 3123 +#define ARM_VQMOVNsv8i8 3124 +#define ARM_VQMOVNuv2i32 3125 +#define ARM_VQMOVNuv4i16 3126 +#define ARM_VQMOVNuv8i8 3127 +#define ARM_VQNEGv16i8 3128 +#define ARM_VQNEGv2i32 3129 +#define ARM_VQNEGv4i16 3130 +#define ARM_VQNEGv4i32 3131 +#define ARM_VQNEGv8i16 3132 +#define ARM_VQNEGv8i8 3133 +#define ARM_VQRDMLAHslv2i32 3134 +#define ARM_VQRDMLAHslv4i16 3135 +#define ARM_VQRDMLAHslv4i32 3136 +#define ARM_VQRDMLAHslv8i16 3137 +#define ARM_VQRDMLAHv2i32 3138 +#define ARM_VQRDMLAHv4i16 3139 +#define ARM_VQRDMLAHv4i32 3140 +#define ARM_VQRDMLAHv8i16 3141 +#define ARM_VQRDMLSHslv2i32 3142 +#define ARM_VQRDMLSHslv4i16 3143 +#define ARM_VQRDMLSHslv4i32 3144 +#define ARM_VQRDMLSHslv8i16 3145 +#define ARM_VQRDMLSHv2i32 3146 +#define ARM_VQRDMLSHv4i16 3147 +#define ARM_VQRDMLSHv4i32 3148 +#define ARM_VQRDMLSHv8i16 3149 +#define ARM_VQRDMULHslv2i32 3150 +#define ARM_VQRDMULHslv4i16 3151 +#define ARM_VQRDMULHslv4i32 3152 +#define ARM_VQRDMULHslv8i16 3153 +#define ARM_VQRDMULHv2i32 3154 +#define ARM_VQRDMULHv4i16 3155 +#define ARM_VQRDMULHv4i32 3156 +#define ARM_VQRDMULHv8i16 3157 +#define ARM_VQRSHLsv16i8 3158 +#define ARM_VQRSHLsv1i64 3159 +#define ARM_VQRSHLsv2i32 3160 +#define ARM_VQRSHLsv2i64 3161 +#define ARM_VQRSHLsv4i16 3162 +#define ARM_VQRSHLsv4i32 3163 +#define ARM_VQRSHLsv8i16 3164 +#define ARM_VQRSHLsv8i8 3165 +#define ARM_VQRSHLuv16i8 3166 +#define ARM_VQRSHLuv1i64 3167 +#define ARM_VQRSHLuv2i32 3168 +#define ARM_VQRSHLuv2i64 3169 +#define ARM_VQRSHLuv4i16 3170 +#define ARM_VQRSHLuv4i32 3171 +#define ARM_VQRSHLuv8i16 3172 +#define ARM_VQRSHLuv8i8 3173 +#define ARM_VQRSHRNsv2i32 3174 +#define ARM_VQRSHRNsv4i16 3175 +#define ARM_VQRSHRNsv8i8 3176 +#define ARM_VQRSHRNuv2i32 3177 +#define ARM_VQRSHRNuv4i16 3178 +#define ARM_VQRSHRNuv8i8 3179 +#define ARM_VQRSHRUNv2i32 3180 +#define ARM_VQRSHRUNv4i16 3181 +#define ARM_VQRSHRUNv8i8 3182 +#define ARM_VQSHLsiv16i8 3183 +#define ARM_VQSHLsiv1i64 3184 +#define ARM_VQSHLsiv2i32 3185 +#define ARM_VQSHLsiv2i64 3186 +#define ARM_VQSHLsiv4i16 3187 +#define ARM_VQSHLsiv4i32 3188 +#define ARM_VQSHLsiv8i16 3189 +#define ARM_VQSHLsiv8i8 3190 +#define ARM_VQSHLsuv16i8 3191 +#define ARM_VQSHLsuv1i64 3192 +#define ARM_VQSHLsuv2i32 3193 +#define ARM_VQSHLsuv2i64 3194 +#define ARM_VQSHLsuv4i16 3195 +#define ARM_VQSHLsuv4i32 3196 +#define ARM_VQSHLsuv8i16 3197 +#define ARM_VQSHLsuv8i8 3198 +#define ARM_VQSHLsv16i8 3199 +#define ARM_VQSHLsv1i64 3200 +#define ARM_VQSHLsv2i32 3201 +#define ARM_VQSHLsv2i64 3202 +#define ARM_VQSHLsv4i16 3203 +#define ARM_VQSHLsv4i32 3204 +#define ARM_VQSHLsv8i16 3205 +#define ARM_VQSHLsv8i8 3206 +#define ARM_VQSHLuiv16i8 3207 +#define ARM_VQSHLuiv1i64 3208 +#define ARM_VQSHLuiv2i32 3209 +#define ARM_VQSHLuiv2i64 3210 +#define ARM_VQSHLuiv4i16 3211 +#define ARM_VQSHLuiv4i32 3212 +#define ARM_VQSHLuiv8i16 3213 +#define ARM_VQSHLuiv8i8 3214 +#define ARM_VQSHLuv16i8 3215 +#define ARM_VQSHLuv1i64 3216 +#define ARM_VQSHLuv2i32 3217 +#define ARM_VQSHLuv2i64 3218 +#define ARM_VQSHLuv4i16 3219 +#define ARM_VQSHLuv4i32 3220 +#define ARM_VQSHLuv8i16 3221 +#define ARM_VQSHLuv8i8 3222 +#define ARM_VQSHRNsv2i32 3223 +#define ARM_VQSHRNsv4i16 3224 +#define ARM_VQSHRNsv8i8 3225 +#define ARM_VQSHRNuv2i32 3226 +#define ARM_VQSHRNuv4i16 3227 +#define ARM_VQSHRNuv8i8 3228 +#define ARM_VQSHRUNv2i32 3229 +#define ARM_VQSHRUNv4i16 3230 +#define ARM_VQSHRUNv8i8 3231 +#define ARM_VQSUBsv16i8 3232 +#define ARM_VQSUBsv1i64 3233 +#define ARM_VQSUBsv2i32 3234 +#define ARM_VQSUBsv2i64 3235 +#define ARM_VQSUBsv4i16 3236 +#define ARM_VQSUBsv4i32 3237 +#define ARM_VQSUBsv8i16 3238 +#define ARM_VQSUBsv8i8 3239 +#define ARM_VQSUBuv16i8 3240 +#define ARM_VQSUBuv1i64 3241 +#define ARM_VQSUBuv2i32 3242 +#define ARM_VQSUBuv2i64 3243 +#define ARM_VQSUBuv4i16 3244 +#define ARM_VQSUBuv4i32 3245 +#define ARM_VQSUBuv8i16 3246 +#define ARM_VQSUBuv8i8 3247 +#define ARM_VRADDHNv2i32 3248 +#define ARM_VRADDHNv4i16 3249 +#define ARM_VRADDHNv8i8 3250 +#define ARM_VRECPEd 3251 +#define ARM_VRECPEfd 3252 +#define ARM_VRECPEfq 3253 +#define ARM_VRECPEhd 3254 +#define ARM_VRECPEhq 3255 +#define ARM_VRECPEq 3256 +#define ARM_VRECPSfd 3257 +#define ARM_VRECPSfq 3258 +#define ARM_VRECPShd 3259 +#define ARM_VRECPShq 3260 +#define ARM_VREV16d8 3261 +#define ARM_VREV16q8 3262 +#define ARM_VREV32d16 3263 +#define ARM_VREV32d8 3264 +#define ARM_VREV32q16 3265 +#define ARM_VREV32q8 3266 +#define ARM_VREV64d16 3267 +#define ARM_VREV64d32 3268 +#define ARM_VREV64d8 3269 +#define ARM_VREV64q16 3270 +#define ARM_VREV64q32 3271 +#define ARM_VREV64q8 3272 +#define ARM_VRHADDsv16i8 3273 +#define ARM_VRHADDsv2i32 3274 +#define ARM_VRHADDsv4i16 3275 +#define ARM_VRHADDsv4i32 3276 +#define ARM_VRHADDsv8i16 3277 +#define ARM_VRHADDsv8i8 3278 +#define ARM_VRHADDuv16i8 3279 +#define ARM_VRHADDuv2i32 3280 +#define ARM_VRHADDuv4i16 3281 +#define ARM_VRHADDuv4i32 3282 +#define ARM_VRHADDuv8i16 3283 +#define ARM_VRHADDuv8i8 3284 +#define ARM_VRINTAD 3285 +#define ARM_VRINTAH 3286 +#define ARM_VRINTANDf 3287 +#define ARM_VRINTANDh 3288 +#define ARM_VRINTANQf 3289 +#define ARM_VRINTANQh 3290 +#define ARM_VRINTAS 3291 +#define ARM_VRINTMD 3292 +#define ARM_VRINTMH 3293 +#define ARM_VRINTMNDf 3294 +#define ARM_VRINTMNDh 3295 +#define ARM_VRINTMNQf 3296 +#define ARM_VRINTMNQh 3297 +#define ARM_VRINTMS 3298 +#define ARM_VRINTND 3299 +#define ARM_VRINTNH 3300 +#define ARM_VRINTNNDf 3301 +#define ARM_VRINTNNDh 3302 +#define ARM_VRINTNNQf 3303 +#define ARM_VRINTNNQh 3304 +#define ARM_VRINTNS 3305 +#define ARM_VRINTPD 3306 +#define ARM_VRINTPH 3307 +#define ARM_VRINTPNDf 3308 +#define ARM_VRINTPNDh 3309 +#define ARM_VRINTPNQf 3310 +#define ARM_VRINTPNQh 3311 +#define ARM_VRINTPS 3312 +#define ARM_VRINTRD 3313 +#define ARM_VRINTRH 3314 +#define ARM_VRINTRS 3315 +#define ARM_VRINTXD 3316 +#define ARM_VRINTXH 3317 +#define ARM_VRINTXNDf 3318 +#define ARM_VRINTXNDh 3319 +#define ARM_VRINTXNQf 3320 +#define ARM_VRINTXNQh 3321 +#define ARM_VRINTXS 3322 +#define ARM_VRINTZD 3323 +#define ARM_VRINTZH 3324 +#define ARM_VRINTZNDf 3325 +#define ARM_VRINTZNDh 3326 +#define ARM_VRINTZNQf 3327 +#define ARM_VRINTZNQh 3328 +#define ARM_VRINTZS 3329 +#define ARM_VRSHLsv16i8 3330 +#define ARM_VRSHLsv1i64 3331 +#define ARM_VRSHLsv2i32 3332 +#define ARM_VRSHLsv2i64 3333 +#define ARM_VRSHLsv4i16 3334 +#define ARM_VRSHLsv4i32 3335 +#define ARM_VRSHLsv8i16 3336 +#define ARM_VRSHLsv8i8 3337 +#define ARM_VRSHLuv16i8 3338 +#define ARM_VRSHLuv1i64 3339 +#define ARM_VRSHLuv2i32 3340 +#define ARM_VRSHLuv2i64 3341 +#define ARM_VRSHLuv4i16 3342 +#define ARM_VRSHLuv4i32 3343 +#define ARM_VRSHLuv8i16 3344 +#define ARM_VRSHLuv8i8 3345 +#define ARM_VRSHRNv2i32 3346 +#define ARM_VRSHRNv4i16 3347 +#define ARM_VRSHRNv8i8 3348 +#define ARM_VRSHRsv16i8 3349 +#define ARM_VRSHRsv1i64 3350 +#define ARM_VRSHRsv2i32 3351 +#define ARM_VRSHRsv2i64 3352 +#define ARM_VRSHRsv4i16 3353 +#define ARM_VRSHRsv4i32 3354 +#define ARM_VRSHRsv8i16 3355 +#define ARM_VRSHRsv8i8 3356 +#define ARM_VRSHRuv16i8 3357 +#define ARM_VRSHRuv1i64 3358 +#define ARM_VRSHRuv2i32 3359 +#define ARM_VRSHRuv2i64 3360 +#define ARM_VRSHRuv4i16 3361 +#define ARM_VRSHRuv4i32 3362 +#define ARM_VRSHRuv8i16 3363 +#define ARM_VRSHRuv8i8 3364 +#define ARM_VRSQRTEd 3365 +#define ARM_VRSQRTEfd 3366 +#define ARM_VRSQRTEfq 3367 +#define ARM_VRSQRTEhd 3368 +#define ARM_VRSQRTEhq 3369 +#define ARM_VRSQRTEq 3370 +#define ARM_VRSQRTSfd 3371 +#define ARM_VRSQRTSfq 3372 +#define ARM_VRSQRTShd 3373 +#define ARM_VRSQRTShq 3374 +#define ARM_VRSRAsv16i8 3375 +#define ARM_VRSRAsv1i64 3376 +#define ARM_VRSRAsv2i32 3377 +#define ARM_VRSRAsv2i64 3378 +#define ARM_VRSRAsv4i16 3379 +#define ARM_VRSRAsv4i32 3380 +#define ARM_VRSRAsv8i16 3381 +#define ARM_VRSRAsv8i8 3382 +#define ARM_VRSRAuv16i8 3383 +#define ARM_VRSRAuv1i64 3384 +#define ARM_VRSRAuv2i32 3385 +#define ARM_VRSRAuv2i64 3386 +#define ARM_VRSRAuv4i16 3387 +#define ARM_VRSRAuv4i32 3388 +#define ARM_VRSRAuv8i16 3389 +#define ARM_VRSRAuv8i8 3390 +#define ARM_VRSUBHNv2i32 3391 +#define ARM_VRSUBHNv4i16 3392 +#define ARM_VRSUBHNv8i8 3393 +#define ARM_VSCCLRMD 3394 +#define ARM_VSCCLRMS 3395 +#define ARM_VSDOTD 3396 +#define ARM_VSDOTDI 3397 +#define ARM_VSDOTQ 3398 +#define ARM_VSDOTQI 3399 +#define ARM_VSELEQD 3400 +#define ARM_VSELEQH 3401 +#define ARM_VSELEQS 3402 +#define ARM_VSELGED 3403 +#define ARM_VSELGEH 3404 +#define ARM_VSELGES 3405 +#define ARM_VSELGTD 3406 +#define ARM_VSELGTH 3407 +#define ARM_VSELGTS 3408 +#define ARM_VSELVSD 3409 +#define ARM_VSELVSH 3410 +#define ARM_VSELVSS 3411 +#define ARM_VSETLNi16 3412 +#define ARM_VSETLNi32 3413 +#define ARM_VSETLNi8 3414 +#define ARM_VSHLLi16 3415 +#define ARM_VSHLLi32 3416 +#define ARM_VSHLLi8 3417 +#define ARM_VSHLLsv2i64 3418 +#define ARM_VSHLLsv4i32 3419 +#define ARM_VSHLLsv8i16 3420 +#define ARM_VSHLLuv2i64 3421 +#define ARM_VSHLLuv4i32 3422 +#define ARM_VSHLLuv8i16 3423 +#define ARM_VSHLiv16i8 3424 +#define ARM_VSHLiv1i64 3425 +#define ARM_VSHLiv2i32 3426 +#define ARM_VSHLiv2i64 3427 +#define ARM_VSHLiv4i16 3428 +#define ARM_VSHLiv4i32 3429 +#define ARM_VSHLiv8i16 3430 +#define ARM_VSHLiv8i8 3431 +#define ARM_VSHLsv16i8 3432 +#define ARM_VSHLsv1i64 3433 +#define ARM_VSHLsv2i32 3434 +#define ARM_VSHLsv2i64 3435 +#define ARM_VSHLsv4i16 3436 +#define ARM_VSHLsv4i32 3437 +#define ARM_VSHLsv8i16 3438 +#define ARM_VSHLsv8i8 3439 +#define ARM_VSHLuv16i8 3440 +#define ARM_VSHLuv1i64 3441 +#define ARM_VSHLuv2i32 3442 +#define ARM_VSHLuv2i64 3443 +#define ARM_VSHLuv4i16 3444 +#define ARM_VSHLuv4i32 3445 +#define ARM_VSHLuv8i16 3446 +#define ARM_VSHLuv8i8 3447 +#define ARM_VSHRNv2i32 3448 +#define ARM_VSHRNv4i16 3449 +#define ARM_VSHRNv8i8 3450 +#define ARM_VSHRsv16i8 3451 +#define ARM_VSHRsv1i64 3452 +#define ARM_VSHRsv2i32 3453 +#define ARM_VSHRsv2i64 3454 +#define ARM_VSHRsv4i16 3455 +#define ARM_VSHRsv4i32 3456 +#define ARM_VSHRsv8i16 3457 +#define ARM_VSHRsv8i8 3458 +#define ARM_VSHRuv16i8 3459 +#define ARM_VSHRuv1i64 3460 +#define ARM_VSHRuv2i32 3461 +#define ARM_VSHRuv2i64 3462 +#define ARM_VSHRuv4i16 3463 +#define ARM_VSHRuv4i32 3464 +#define ARM_VSHRuv8i16 3465 +#define ARM_VSHRuv8i8 3466 +#define ARM_VSHTOD 3467 +#define ARM_VSHTOH 3468 +#define ARM_VSHTOS 3469 +#define ARM_VSITOD 3470 +#define ARM_VSITOH 3471 +#define ARM_VSITOS 3472 +#define ARM_VSLIv16i8 3473 +#define ARM_VSLIv1i64 3474 +#define ARM_VSLIv2i32 3475 +#define ARM_VSLIv2i64 3476 +#define ARM_VSLIv4i16 3477 +#define ARM_VSLIv4i32 3478 +#define ARM_VSLIv8i16 3479 +#define ARM_VSLIv8i8 3480 +#define ARM_VSLTOD 3481 +#define ARM_VSLTOH 3482 +#define ARM_VSLTOS 3483 +#define ARM_VSMMLA 3484 +#define ARM_VSQRTD 3485 +#define ARM_VSQRTH 3486 +#define ARM_VSQRTS 3487 +#define ARM_VSRAsv16i8 3488 +#define ARM_VSRAsv1i64 3489 +#define ARM_VSRAsv2i32 3490 +#define ARM_VSRAsv2i64 3491 +#define ARM_VSRAsv4i16 3492 +#define ARM_VSRAsv4i32 3493 +#define ARM_VSRAsv8i16 3494 +#define ARM_VSRAsv8i8 3495 +#define ARM_VSRAuv16i8 3496 +#define ARM_VSRAuv1i64 3497 +#define ARM_VSRAuv2i32 3498 +#define ARM_VSRAuv2i64 3499 +#define ARM_VSRAuv4i16 3500 +#define ARM_VSRAuv4i32 3501 +#define ARM_VSRAuv8i16 3502 +#define ARM_VSRAuv8i8 3503 +#define ARM_VSRIv16i8 3504 +#define ARM_VSRIv1i64 3505 +#define ARM_VSRIv2i32 3506 +#define ARM_VSRIv2i64 3507 +#define ARM_VSRIv4i16 3508 +#define ARM_VSRIv4i32 3509 +#define ARM_VSRIv8i16 3510 +#define ARM_VSRIv8i8 3511 +#define ARM_VST1LNd16 3512 +#define ARM_VST1LNd16_UPD 3513 +#define ARM_VST1LNd32 3514 +#define ARM_VST1LNd32_UPD 3515 +#define ARM_VST1LNd8 3516 +#define ARM_VST1LNd8_UPD 3517 +#define ARM_VST1LNq16Pseudo 3518 +#define ARM_VST1LNq16Pseudo_UPD 3519 +#define ARM_VST1LNq32Pseudo 3520 +#define ARM_VST1LNq32Pseudo_UPD 3521 +#define ARM_VST1LNq8Pseudo 3522 +#define ARM_VST1LNq8Pseudo_UPD 3523 +#define ARM_VST1d16 3524 +#define ARM_VST1d16Q 3525 +#define ARM_VST1d16QPseudo 3526 +#define ARM_VST1d16QPseudoWB_fixed 3527 +#define ARM_VST1d16QPseudoWB_register 3528 +#define ARM_VST1d16Qwb_fixed 3529 +#define ARM_VST1d16Qwb_register 3530 +#define ARM_VST1d16T 3531 +#define ARM_VST1d16TPseudo 3532 +#define ARM_VST1d16TPseudoWB_fixed 3533 +#define ARM_VST1d16TPseudoWB_register 3534 +#define ARM_VST1d16Twb_fixed 3535 +#define ARM_VST1d16Twb_register 3536 +#define ARM_VST1d16wb_fixed 3537 +#define ARM_VST1d16wb_register 3538 +#define ARM_VST1d32 3539 +#define ARM_VST1d32Q 3540 +#define ARM_VST1d32QPseudo 3541 +#define ARM_VST1d32QPseudoWB_fixed 3542 +#define ARM_VST1d32QPseudoWB_register 3543 +#define ARM_VST1d32Qwb_fixed 3544 +#define ARM_VST1d32Qwb_register 3545 +#define ARM_VST1d32T 3546 +#define ARM_VST1d32TPseudo 3547 +#define ARM_VST1d32TPseudoWB_fixed 3548 +#define ARM_VST1d32TPseudoWB_register 3549 +#define ARM_VST1d32Twb_fixed 3550 +#define ARM_VST1d32Twb_register 3551 +#define ARM_VST1d32wb_fixed 3552 +#define ARM_VST1d32wb_register 3553 +#define ARM_VST1d64 3554 +#define ARM_VST1d64Q 3555 +#define ARM_VST1d64QPseudo 3556 +#define ARM_VST1d64QPseudoWB_fixed 3557 +#define ARM_VST1d64QPseudoWB_register 3558 +#define ARM_VST1d64Qwb_fixed 3559 +#define ARM_VST1d64Qwb_register 3560 +#define ARM_VST1d64T 3561 +#define ARM_VST1d64TPseudo 3562 +#define ARM_VST1d64TPseudoWB_fixed 3563 +#define ARM_VST1d64TPseudoWB_register 3564 +#define ARM_VST1d64Twb_fixed 3565 +#define ARM_VST1d64Twb_register 3566 +#define ARM_VST1d64wb_fixed 3567 +#define ARM_VST1d64wb_register 3568 +#define ARM_VST1d8 3569 +#define ARM_VST1d8Q 3570 +#define ARM_VST1d8QPseudo 3571 +#define ARM_VST1d8QPseudoWB_fixed 3572 +#define ARM_VST1d8QPseudoWB_register 3573 +#define ARM_VST1d8Qwb_fixed 3574 +#define ARM_VST1d8Qwb_register 3575 +#define ARM_VST1d8T 3576 +#define ARM_VST1d8TPseudo 3577 +#define ARM_VST1d8TPseudoWB_fixed 3578 +#define ARM_VST1d8TPseudoWB_register 3579 +#define ARM_VST1d8Twb_fixed 3580 +#define ARM_VST1d8Twb_register 3581 +#define ARM_VST1d8wb_fixed 3582 +#define ARM_VST1d8wb_register 3583 +#define ARM_VST1q16 3584 +#define ARM_VST1q16HighQPseudo 3585 +#define ARM_VST1q16HighQPseudo_UPD 3586 +#define ARM_VST1q16HighTPseudo 3587 +#define ARM_VST1q16HighTPseudo_UPD 3588 +#define ARM_VST1q16LowQPseudo_UPD 3589 +#define ARM_VST1q16LowTPseudo_UPD 3590 +#define ARM_VST1q16wb_fixed 3591 +#define ARM_VST1q16wb_register 3592 +#define ARM_VST1q32 3593 +#define ARM_VST1q32HighQPseudo 3594 +#define ARM_VST1q32HighQPseudo_UPD 3595 +#define ARM_VST1q32HighTPseudo 3596 +#define ARM_VST1q32HighTPseudo_UPD 3597 +#define ARM_VST1q32LowQPseudo_UPD 3598 +#define ARM_VST1q32LowTPseudo_UPD 3599 +#define ARM_VST1q32wb_fixed 3600 +#define ARM_VST1q32wb_register 3601 +#define ARM_VST1q64 3602 +#define ARM_VST1q64HighQPseudo 3603 +#define ARM_VST1q64HighQPseudo_UPD 3604 +#define ARM_VST1q64HighTPseudo 3605 +#define ARM_VST1q64HighTPseudo_UPD 3606 +#define ARM_VST1q64LowQPseudo_UPD 3607 +#define ARM_VST1q64LowTPseudo_UPD 3608 +#define ARM_VST1q64wb_fixed 3609 +#define ARM_VST1q64wb_register 3610 +#define ARM_VST1q8 3611 +#define ARM_VST1q8HighQPseudo 3612 +#define ARM_VST1q8HighQPseudo_UPD 3613 +#define ARM_VST1q8HighTPseudo 3614 +#define ARM_VST1q8HighTPseudo_UPD 3615 +#define ARM_VST1q8LowQPseudo_UPD 3616 +#define ARM_VST1q8LowTPseudo_UPD 3617 +#define ARM_VST1q8wb_fixed 3618 +#define ARM_VST1q8wb_register 3619 +#define ARM_VST2LNd16 3620 +#define ARM_VST2LNd16Pseudo 3621 +#define ARM_VST2LNd16Pseudo_UPD 3622 +#define ARM_VST2LNd16_UPD 3623 +#define ARM_VST2LNd32 3624 +#define ARM_VST2LNd32Pseudo 3625 +#define ARM_VST2LNd32Pseudo_UPD 3626 +#define ARM_VST2LNd32_UPD 3627 +#define ARM_VST2LNd8 3628 +#define ARM_VST2LNd8Pseudo 3629 +#define ARM_VST2LNd8Pseudo_UPD 3630 +#define ARM_VST2LNd8_UPD 3631 +#define ARM_VST2LNq16 3632 +#define ARM_VST2LNq16Pseudo 3633 +#define ARM_VST2LNq16Pseudo_UPD 3634 +#define ARM_VST2LNq16_UPD 3635 +#define ARM_VST2LNq32 3636 +#define ARM_VST2LNq32Pseudo 3637 +#define ARM_VST2LNq32Pseudo_UPD 3638 +#define ARM_VST2LNq32_UPD 3639 +#define ARM_VST2b16 3640 +#define ARM_VST2b16wb_fixed 3641 +#define ARM_VST2b16wb_register 3642 +#define ARM_VST2b32 3643 +#define ARM_VST2b32wb_fixed 3644 +#define ARM_VST2b32wb_register 3645 +#define ARM_VST2b8 3646 +#define ARM_VST2b8wb_fixed 3647 +#define ARM_VST2b8wb_register 3648 +#define ARM_VST2d16 3649 +#define ARM_VST2d16wb_fixed 3650 +#define ARM_VST2d16wb_register 3651 +#define ARM_VST2d32 3652 +#define ARM_VST2d32wb_fixed 3653 +#define ARM_VST2d32wb_register 3654 +#define ARM_VST2d8 3655 +#define ARM_VST2d8wb_fixed 3656 +#define ARM_VST2d8wb_register 3657 +#define ARM_VST2q16 3658 +#define ARM_VST2q16Pseudo 3659 +#define ARM_VST2q16PseudoWB_fixed 3660 +#define ARM_VST2q16PseudoWB_register 3661 +#define ARM_VST2q16wb_fixed 3662 +#define ARM_VST2q16wb_register 3663 +#define ARM_VST2q32 3664 +#define ARM_VST2q32Pseudo 3665 +#define ARM_VST2q32PseudoWB_fixed 3666 +#define ARM_VST2q32PseudoWB_register 3667 +#define ARM_VST2q32wb_fixed 3668 +#define ARM_VST2q32wb_register 3669 +#define ARM_VST2q8 3670 +#define ARM_VST2q8Pseudo 3671 +#define ARM_VST2q8PseudoWB_fixed 3672 +#define ARM_VST2q8PseudoWB_register 3673 +#define ARM_VST2q8wb_fixed 3674 +#define ARM_VST2q8wb_register 3675 +#define ARM_VST3LNd16 3676 +#define ARM_VST3LNd16Pseudo 3677 +#define ARM_VST3LNd16Pseudo_UPD 3678 +#define ARM_VST3LNd16_UPD 3679 +#define ARM_VST3LNd32 3680 +#define ARM_VST3LNd32Pseudo 3681 +#define ARM_VST3LNd32Pseudo_UPD 3682 +#define ARM_VST3LNd32_UPD 3683 +#define ARM_VST3LNd8 3684 +#define ARM_VST3LNd8Pseudo 3685 +#define ARM_VST3LNd8Pseudo_UPD 3686 +#define ARM_VST3LNd8_UPD 3687 +#define ARM_VST3LNq16 3688 +#define ARM_VST3LNq16Pseudo 3689 +#define ARM_VST3LNq16Pseudo_UPD 3690 +#define ARM_VST3LNq16_UPD 3691 +#define ARM_VST3LNq32 3692 +#define ARM_VST3LNq32Pseudo 3693 +#define ARM_VST3LNq32Pseudo_UPD 3694 +#define ARM_VST3LNq32_UPD 3695 +#define ARM_VST3d16 3696 +#define ARM_VST3d16Pseudo 3697 +#define ARM_VST3d16Pseudo_UPD 3698 +#define ARM_VST3d16_UPD 3699 +#define ARM_VST3d32 3700 +#define ARM_VST3d32Pseudo 3701 +#define ARM_VST3d32Pseudo_UPD 3702 +#define ARM_VST3d32_UPD 3703 +#define ARM_VST3d8 3704 +#define ARM_VST3d8Pseudo 3705 +#define ARM_VST3d8Pseudo_UPD 3706 +#define ARM_VST3d8_UPD 3707 +#define ARM_VST3q16 3708 +#define ARM_VST3q16Pseudo_UPD 3709 +#define ARM_VST3q16_UPD 3710 +#define ARM_VST3q16oddPseudo 3711 +#define ARM_VST3q16oddPseudo_UPD 3712 +#define ARM_VST3q32 3713 +#define ARM_VST3q32Pseudo_UPD 3714 +#define ARM_VST3q32_UPD 3715 +#define ARM_VST3q32oddPseudo 3716 +#define ARM_VST3q32oddPseudo_UPD 3717 +#define ARM_VST3q8 3718 +#define ARM_VST3q8Pseudo_UPD 3719 +#define ARM_VST3q8_UPD 3720 +#define ARM_VST3q8oddPseudo 3721 +#define ARM_VST3q8oddPseudo_UPD 3722 +#define ARM_VST4LNd16 3723 +#define ARM_VST4LNd16Pseudo 3724 +#define ARM_VST4LNd16Pseudo_UPD 3725 +#define ARM_VST4LNd16_UPD 3726 +#define ARM_VST4LNd32 3727 +#define ARM_VST4LNd32Pseudo 3728 +#define ARM_VST4LNd32Pseudo_UPD 3729 +#define ARM_VST4LNd32_UPD 3730 +#define ARM_VST4LNd8 3731 +#define ARM_VST4LNd8Pseudo 3732 +#define ARM_VST4LNd8Pseudo_UPD 3733 +#define ARM_VST4LNd8_UPD 3734 +#define ARM_VST4LNq16 3735 +#define ARM_VST4LNq16Pseudo 3736 +#define ARM_VST4LNq16Pseudo_UPD 3737 +#define ARM_VST4LNq16_UPD 3738 +#define ARM_VST4LNq32 3739 +#define ARM_VST4LNq32Pseudo 3740 +#define ARM_VST4LNq32Pseudo_UPD 3741 +#define ARM_VST4LNq32_UPD 3742 +#define ARM_VST4d16 3743 +#define ARM_VST4d16Pseudo 3744 +#define ARM_VST4d16Pseudo_UPD 3745 +#define ARM_VST4d16_UPD 3746 +#define ARM_VST4d32 3747 +#define ARM_VST4d32Pseudo 3748 +#define ARM_VST4d32Pseudo_UPD 3749 +#define ARM_VST4d32_UPD 3750 +#define ARM_VST4d8 3751 +#define ARM_VST4d8Pseudo 3752 +#define ARM_VST4d8Pseudo_UPD 3753 +#define ARM_VST4d8_UPD 3754 +#define ARM_VST4q16 3755 +#define ARM_VST4q16Pseudo_UPD 3756 +#define ARM_VST4q16_UPD 3757 +#define ARM_VST4q16oddPseudo 3758 +#define ARM_VST4q16oddPseudo_UPD 3759 +#define ARM_VST4q32 3760 +#define ARM_VST4q32Pseudo_UPD 3761 +#define ARM_VST4q32_UPD 3762 +#define ARM_VST4q32oddPseudo 3763 +#define ARM_VST4q32oddPseudo_UPD 3764 +#define ARM_VST4q8 3765 +#define ARM_VST4q8Pseudo_UPD 3766 +#define ARM_VST4q8_UPD 3767 +#define ARM_VST4q8oddPseudo 3768 +#define ARM_VST4q8oddPseudo_UPD 3769 +#define ARM_VSTMDDB_UPD 3770 +#define ARM_VSTMDIA 3771 +#define ARM_VSTMDIA_UPD 3772 +#define ARM_VSTMQIA 3773 +#define ARM_VSTMSDB_UPD 3774 +#define ARM_VSTMSIA 3775 +#define ARM_VSTMSIA_UPD 3776 +#define ARM_VSTRD 3777 +#define ARM_VSTRH 3778 +#define ARM_VSTRS 3779 +#define ARM_VSTR_FPCXTNS_off 3780 +#define ARM_VSTR_FPCXTNS_post 3781 +#define ARM_VSTR_FPCXTNS_pre 3782 +#define ARM_VSTR_FPCXTS_off 3783 +#define ARM_VSTR_FPCXTS_post 3784 +#define ARM_VSTR_FPCXTS_pre 3785 +#define ARM_VSTR_FPSCR_NZCVQC_off 3786 +#define ARM_VSTR_FPSCR_NZCVQC_post 3787 +#define ARM_VSTR_FPSCR_NZCVQC_pre 3788 +#define ARM_VSTR_FPSCR_off 3789 +#define ARM_VSTR_FPSCR_post 3790 +#define ARM_VSTR_FPSCR_pre 3791 +#define ARM_VSTR_P0_off 3792 +#define ARM_VSTR_P0_post 3793 +#define ARM_VSTR_P0_pre 3794 +#define ARM_VSTR_VPR_off 3795 +#define ARM_VSTR_VPR_post 3796 +#define ARM_VSTR_VPR_pre 3797 +#define ARM_VSUBD 3798 +#define ARM_VSUBH 3799 +#define ARM_VSUBHNv2i32 3800 +#define ARM_VSUBHNv4i16 3801 +#define ARM_VSUBHNv8i8 3802 +#define ARM_VSUBLsv2i64 3803 +#define ARM_VSUBLsv4i32 3804 +#define ARM_VSUBLsv8i16 3805 +#define ARM_VSUBLuv2i64 3806 +#define ARM_VSUBLuv4i32 3807 +#define ARM_VSUBLuv8i16 3808 +#define ARM_VSUBS 3809 +#define ARM_VSUBWsv2i64 3810 +#define ARM_VSUBWsv4i32 3811 +#define ARM_VSUBWsv8i16 3812 +#define ARM_VSUBWuv2i64 3813 +#define ARM_VSUBWuv4i32 3814 +#define ARM_VSUBWuv8i16 3815 +#define ARM_VSUBfd 3816 +#define ARM_VSUBfq 3817 +#define ARM_VSUBhd 3818 +#define ARM_VSUBhq 3819 +#define ARM_VSUBv16i8 3820 +#define ARM_VSUBv1i64 3821 +#define ARM_VSUBv2i32 3822 +#define ARM_VSUBv2i64 3823 +#define ARM_VSUBv4i16 3824 +#define ARM_VSUBv4i32 3825 +#define ARM_VSUBv8i16 3826 +#define ARM_VSUBv8i8 3827 +#define ARM_VSUDOTDI 3828 +#define ARM_VSUDOTQI 3829 +#define ARM_VSWPd 3830 +#define ARM_VSWPq 3831 +#define ARM_VTBL1 3832 +#define ARM_VTBL2 3833 +#define ARM_VTBL3 3834 +#define ARM_VTBL3Pseudo 3835 +#define ARM_VTBL4 3836 +#define ARM_VTBL4Pseudo 3837 +#define ARM_VTBX1 3838 +#define ARM_VTBX2 3839 +#define ARM_VTBX3 3840 +#define ARM_VTBX3Pseudo 3841 +#define ARM_VTBX4 3842 +#define ARM_VTBX4Pseudo 3843 +#define ARM_VTOSHD 3844 +#define ARM_VTOSHH 3845 +#define ARM_VTOSHS 3846 +#define ARM_VTOSIRD 3847 +#define ARM_VTOSIRH 3848 +#define ARM_VTOSIRS 3849 +#define ARM_VTOSIZD 3850 +#define ARM_VTOSIZH 3851 +#define ARM_VTOSIZS 3852 +#define ARM_VTOSLD 3853 +#define ARM_VTOSLH 3854 +#define ARM_VTOSLS 3855 +#define ARM_VTOUHD 3856 +#define ARM_VTOUHH 3857 +#define ARM_VTOUHS 3858 +#define ARM_VTOUIRD 3859 +#define ARM_VTOUIRH 3860 +#define ARM_VTOUIRS 3861 +#define ARM_VTOUIZD 3862 +#define ARM_VTOUIZH 3863 +#define ARM_VTOUIZS 3864 +#define ARM_VTOULD 3865 +#define ARM_VTOULH 3866 +#define ARM_VTOULS 3867 +#define ARM_VTRNd16 3868 +#define ARM_VTRNd32 3869 +#define ARM_VTRNd8 3870 +#define ARM_VTRNq16 3871 +#define ARM_VTRNq32 3872 +#define ARM_VTRNq8 3873 +#define ARM_VTSTv16i8 3874 +#define ARM_VTSTv2i32 3875 +#define ARM_VTSTv4i16 3876 +#define ARM_VTSTv4i32 3877 +#define ARM_VTSTv8i16 3878 +#define ARM_VTSTv8i8 3879 +#define ARM_VUDOTD 3880 +#define ARM_VUDOTDI 3881 +#define ARM_VUDOTQ 3882 +#define ARM_VUDOTQI 3883 +#define ARM_VUHTOD 3884 +#define ARM_VUHTOH 3885 +#define ARM_VUHTOS 3886 +#define ARM_VUITOD 3887 +#define ARM_VUITOH 3888 +#define ARM_VUITOS 3889 +#define ARM_VULTOD 3890 +#define ARM_VULTOH 3891 +#define ARM_VULTOS 3892 +#define ARM_VUMMLA 3893 +#define ARM_VUSDOTD 3894 +#define ARM_VUSDOTDI 3895 +#define ARM_VUSDOTQ 3896 +#define ARM_VUSDOTQI 3897 +#define ARM_VUSMMLA 3898 +#define ARM_VUZPd16 3899 +#define ARM_VUZPd8 3900 +#define ARM_VUZPq16 3901 +#define ARM_VUZPq32 3902 +#define ARM_VUZPq8 3903 +#define ARM_VZIPd16 3904 +#define ARM_VZIPd8 3905 +#define ARM_VZIPq16 3906 +#define ARM_VZIPq32 3907 +#define ARM_VZIPq8 3908 +#define ARM_sysLDMDA 3909 +#define ARM_sysLDMDA_UPD 3910 +#define ARM_sysLDMDB 3911 +#define ARM_sysLDMDB_UPD 3912 +#define ARM_sysLDMIA 3913 +#define ARM_sysLDMIA_UPD 3914 +#define ARM_sysLDMIB 3915 +#define ARM_sysLDMIB_UPD 3916 +#define ARM_sysSTMDA 3917 +#define ARM_sysSTMDA_UPD 3918 +#define ARM_sysSTMDB 3919 +#define ARM_sysSTMDB_UPD 3920 +#define ARM_sysSTMIA 3921 +#define ARM_sysSTMIA_UPD 3922 +#define ARM_sysSTMIB 3923 +#define ARM_sysSTMIB_UPD 3924 +#define ARM_t2ADCri 3925 +#define ARM_t2ADCrr 3926 +#define ARM_t2ADCrs 3927 +#define ARM_t2ADDri 3928 +#define ARM_t2ADDri12 3929 +#define ARM_t2ADDrr 3930 +#define ARM_t2ADDrs 3931 +#define ARM_t2ADDspImm 3932 +#define ARM_t2ADDspImm12 3933 +#define ARM_t2ADR 3934 +#define ARM_t2ANDri 3935 +#define ARM_t2ANDrr 3936 +#define ARM_t2ANDrs 3937 +#define ARM_t2ASRri 3938 +#define ARM_t2ASRrr 3939 +#define ARM_t2B 3940 +#define ARM_t2BFC 3941 +#define ARM_t2BFI 3942 +#define ARM_t2BFLi 3943 +#define ARM_t2BFLr 3944 +#define ARM_t2BFi 3945 +#define ARM_t2BFic 3946 +#define ARM_t2BFr 3947 +#define ARM_t2BICri 3948 +#define ARM_t2BICrr 3949 +#define ARM_t2BICrs 3950 +#define ARM_t2BXJ 3951 +#define ARM_t2Bcc 3952 +#define ARM_t2CDP 3953 +#define ARM_t2CDP2 3954 +#define ARM_t2CLREX 3955 +#define ARM_t2CLRM 3956 +#define ARM_t2CLZ 3957 +#define ARM_t2CMNri 3958 +#define ARM_t2CMNzrr 3959 +#define ARM_t2CMNzrs 3960 +#define ARM_t2CMPri 3961 +#define ARM_t2CMPrr 3962 +#define ARM_t2CMPrs 3963 +#define ARM_t2CPS1p 3964 +#define ARM_t2CPS2p 3965 +#define ARM_t2CPS3p 3966 +#define ARM_t2CRC32B 3967 +#define ARM_t2CRC32CB 3968 +#define ARM_t2CRC32CH 3969 +#define ARM_t2CRC32CW 3970 +#define ARM_t2CRC32H 3971 +#define ARM_t2CRC32W 3972 +#define ARM_t2CSEL 3973 +#define ARM_t2CSINC 3974 +#define ARM_t2CSINV 3975 +#define ARM_t2CSNEG 3976 +#define ARM_t2DBG 3977 +#define ARM_t2DCPS1 3978 +#define ARM_t2DCPS2 3979 +#define ARM_t2DCPS3 3980 +#define ARM_t2DLS 3981 +#define ARM_t2DMB 3982 +#define ARM_t2DSB 3983 +#define ARM_t2EORri 3984 +#define ARM_t2EORrr 3985 +#define ARM_t2EORrs 3986 +#define ARM_t2HINT 3987 +#define ARM_t2HVC 3988 +#define ARM_t2ISB 3989 +#define ARM_t2IT 3990 +#define ARM_t2Int_eh_sjlj_setjmp 3991 +#define ARM_t2Int_eh_sjlj_setjmp_nofp 3992 +#define ARM_t2LDA 3993 +#define ARM_t2LDAB 3994 +#define ARM_t2LDAEX 3995 +#define ARM_t2LDAEXB 3996 +#define ARM_t2LDAEXD 3997 +#define ARM_t2LDAEXH 3998 +#define ARM_t2LDAH 3999 +#define ARM_t2LDC2L_OFFSET 4000 +#define ARM_t2LDC2L_OPTION 4001 +#define ARM_t2LDC2L_POST 4002 +#define ARM_t2LDC2L_PRE 4003 +#define ARM_t2LDC2_OFFSET 4004 +#define ARM_t2LDC2_OPTION 4005 +#define ARM_t2LDC2_POST 4006 +#define ARM_t2LDC2_PRE 4007 +#define ARM_t2LDCL_OFFSET 4008 +#define ARM_t2LDCL_OPTION 4009 +#define ARM_t2LDCL_POST 4010 +#define ARM_t2LDCL_PRE 4011 +#define ARM_t2LDC_OFFSET 4012 +#define ARM_t2LDC_OPTION 4013 +#define ARM_t2LDC_POST 4014 +#define ARM_t2LDC_PRE 4015 +#define ARM_t2LDMDB 4016 +#define ARM_t2LDMDB_UPD 4017 +#define ARM_t2LDMIA 4018 +#define ARM_t2LDMIA_UPD 4019 +#define ARM_t2LDRBT 4020 +#define ARM_t2LDRB_POST 4021 +#define ARM_t2LDRB_PRE 4022 +#define ARM_t2LDRBi12 4023 +#define ARM_t2LDRBi8 4024 +#define ARM_t2LDRBpci 4025 +#define ARM_t2LDRBs 4026 +#define ARM_t2LDRD_POST 4027 +#define ARM_t2LDRD_PRE 4028 +#define ARM_t2LDRDi8 4029 +#define ARM_t2LDREX 4030 +#define ARM_t2LDREXB 4031 +#define ARM_t2LDREXD 4032 +#define ARM_t2LDREXH 4033 +#define ARM_t2LDRHT 4034 +#define ARM_t2LDRH_POST 4035 +#define ARM_t2LDRH_PRE 4036 +#define ARM_t2LDRHi12 4037 +#define ARM_t2LDRHi8 4038 +#define ARM_t2LDRHpci 4039 +#define ARM_t2LDRHs 4040 +#define ARM_t2LDRSBT 4041 +#define ARM_t2LDRSB_POST 4042 +#define ARM_t2LDRSB_PRE 4043 +#define ARM_t2LDRSBi12 4044 +#define ARM_t2LDRSBi8 4045 +#define ARM_t2LDRSBpci 4046 +#define ARM_t2LDRSBs 4047 +#define ARM_t2LDRSHT 4048 +#define ARM_t2LDRSH_POST 4049 +#define ARM_t2LDRSH_PRE 4050 +#define ARM_t2LDRSHi12 4051 +#define ARM_t2LDRSHi8 4052 +#define ARM_t2LDRSHpci 4053 +#define ARM_t2LDRSHs 4054 +#define ARM_t2LDRT 4055 +#define ARM_t2LDR_POST 4056 +#define ARM_t2LDR_PRE 4057 +#define ARM_t2LDRi12 4058 +#define ARM_t2LDRi8 4059 +#define ARM_t2LDRpci 4060 +#define ARM_t2LDRs 4061 +#define ARM_t2LE 4062 +#define ARM_t2LEUpdate 4063 +#define ARM_t2LSLri 4064 +#define ARM_t2LSLrr 4065 +#define ARM_t2LSRri 4066 +#define ARM_t2LSRrr 4067 +#define ARM_t2MCR 4068 +#define ARM_t2MCR2 4069 +#define ARM_t2MCRR 4070 +#define ARM_t2MCRR2 4071 +#define ARM_t2MLA 4072 +#define ARM_t2MLS 4073 +#define ARM_t2MOVTi16 4074 +#define ARM_t2MOVi 4075 +#define ARM_t2MOVi16 4076 +#define ARM_t2MOVr 4077 +#define ARM_t2MOVsra_flag 4078 +#define ARM_t2MOVsrl_flag 4079 +#define ARM_t2MRC 4080 +#define ARM_t2MRC2 4081 +#define ARM_t2MRRC 4082 +#define ARM_t2MRRC2 4083 +#define ARM_t2MRS_AR 4084 +#define ARM_t2MRS_M 4085 +#define ARM_t2MRSbanked 4086 +#define ARM_t2MRSsys_AR 4087 +#define ARM_t2MSR_AR 4088 +#define ARM_t2MSR_M 4089 +#define ARM_t2MSRbanked 4090 +#define ARM_t2MUL 4091 +#define ARM_t2MVNi 4092 +#define ARM_t2MVNr 4093 +#define ARM_t2MVNs 4094 +#define ARM_t2ORNri 4095 +#define ARM_t2ORNrr 4096 +#define ARM_t2ORNrs 4097 +#define ARM_t2ORRri 4098 +#define ARM_t2ORRrr 4099 +#define ARM_t2ORRrs 4100 +#define ARM_t2PKHBT 4101 +#define ARM_t2PKHTB 4102 +#define ARM_t2PLDWi12 4103 +#define ARM_t2PLDWi8 4104 +#define ARM_t2PLDWs 4105 +#define ARM_t2PLDi12 4106 +#define ARM_t2PLDi8 4107 +#define ARM_t2PLDpci 4108 +#define ARM_t2PLDs 4109 +#define ARM_t2PLIi12 4110 +#define ARM_t2PLIi8 4111 +#define ARM_t2PLIpci 4112 +#define ARM_t2PLIs 4113 +#define ARM_t2QADD 4114 +#define ARM_t2QADD16 4115 +#define ARM_t2QADD8 4116 +#define ARM_t2QASX 4117 +#define ARM_t2QDADD 4118 +#define ARM_t2QDSUB 4119 +#define ARM_t2QSAX 4120 +#define ARM_t2QSUB 4121 +#define ARM_t2QSUB16 4122 +#define ARM_t2QSUB8 4123 +#define ARM_t2RBIT 4124 +#define ARM_t2REV 4125 +#define ARM_t2REV16 4126 +#define ARM_t2REVSH 4127 +#define ARM_t2RFEDB 4128 +#define ARM_t2RFEDBW 4129 +#define ARM_t2RFEIA 4130 +#define ARM_t2RFEIAW 4131 +#define ARM_t2RORri 4132 +#define ARM_t2RORrr 4133 +#define ARM_t2RRX 4134 +#define ARM_t2RSBri 4135 +#define ARM_t2RSBrr 4136 +#define ARM_t2RSBrs 4137 +#define ARM_t2SADD16 4138 +#define ARM_t2SADD8 4139 +#define ARM_t2SASX 4140 +#define ARM_t2SB 4141 +#define ARM_t2SBCri 4142 +#define ARM_t2SBCrr 4143 +#define ARM_t2SBCrs 4144 +#define ARM_t2SBFX 4145 +#define ARM_t2SDIV 4146 +#define ARM_t2SEL 4147 +#define ARM_t2SETPAN 4148 +#define ARM_t2SG 4149 +#define ARM_t2SHADD16 4150 +#define ARM_t2SHADD8 4151 +#define ARM_t2SHASX 4152 +#define ARM_t2SHSAX 4153 +#define ARM_t2SHSUB16 4154 +#define ARM_t2SHSUB8 4155 +#define ARM_t2SMC 4156 +#define ARM_t2SMLABB 4157 +#define ARM_t2SMLABT 4158 +#define ARM_t2SMLAD 4159 +#define ARM_t2SMLADX 4160 +#define ARM_t2SMLAL 4161 +#define ARM_t2SMLALBB 4162 +#define ARM_t2SMLALBT 4163 +#define ARM_t2SMLALD 4164 +#define ARM_t2SMLALDX 4165 +#define ARM_t2SMLALTB 4166 +#define ARM_t2SMLALTT 4167 +#define ARM_t2SMLATB 4168 +#define ARM_t2SMLATT 4169 +#define ARM_t2SMLAWB 4170 +#define ARM_t2SMLAWT 4171 +#define ARM_t2SMLSD 4172 +#define ARM_t2SMLSDX 4173 +#define ARM_t2SMLSLD 4174 +#define ARM_t2SMLSLDX 4175 +#define ARM_t2SMMLA 4176 +#define ARM_t2SMMLAR 4177 +#define ARM_t2SMMLS 4178 +#define ARM_t2SMMLSR 4179 +#define ARM_t2SMMUL 4180 +#define ARM_t2SMMULR 4181 +#define ARM_t2SMUAD 4182 +#define ARM_t2SMUADX 4183 +#define ARM_t2SMULBB 4184 +#define ARM_t2SMULBT 4185 +#define ARM_t2SMULL 4186 +#define ARM_t2SMULTB 4187 +#define ARM_t2SMULTT 4188 +#define ARM_t2SMULWB 4189 +#define ARM_t2SMULWT 4190 +#define ARM_t2SMUSD 4191 +#define ARM_t2SMUSDX 4192 +#define ARM_t2SRSDB 4193 +#define ARM_t2SRSDB_UPD 4194 +#define ARM_t2SRSIA 4195 +#define ARM_t2SRSIA_UPD 4196 +#define ARM_t2SSAT 4197 +#define ARM_t2SSAT16 4198 +#define ARM_t2SSAX 4199 +#define ARM_t2SSUB16 4200 +#define ARM_t2SSUB8 4201 +#define ARM_t2STC2L_OFFSET 4202 +#define ARM_t2STC2L_OPTION 4203 +#define ARM_t2STC2L_POST 4204 +#define ARM_t2STC2L_PRE 4205 +#define ARM_t2STC2_OFFSET 4206 +#define ARM_t2STC2_OPTION 4207 +#define ARM_t2STC2_POST 4208 +#define ARM_t2STC2_PRE 4209 +#define ARM_t2STCL_OFFSET 4210 +#define ARM_t2STCL_OPTION 4211 +#define ARM_t2STCL_POST 4212 +#define ARM_t2STCL_PRE 4213 +#define ARM_t2STC_OFFSET 4214 +#define ARM_t2STC_OPTION 4215 +#define ARM_t2STC_POST 4216 +#define ARM_t2STC_PRE 4217 +#define ARM_t2STL 4218 +#define ARM_t2STLB 4219 +#define ARM_t2STLEX 4220 +#define ARM_t2STLEXB 4221 +#define ARM_t2STLEXD 4222 +#define ARM_t2STLEXH 4223 +#define ARM_t2STLH 4224 +#define ARM_t2STMDB 4225 +#define ARM_t2STMDB_UPD 4226 +#define ARM_t2STMIA 4227 +#define ARM_t2STMIA_UPD 4228 +#define ARM_t2STRBT 4229 +#define ARM_t2STRB_POST 4230 +#define ARM_t2STRB_PRE 4231 +#define ARM_t2STRBi12 4232 +#define ARM_t2STRBi8 4233 +#define ARM_t2STRBs 4234 +#define ARM_t2STRD_POST 4235 +#define ARM_t2STRD_PRE 4236 +#define ARM_t2STRDi8 4237 +#define ARM_t2STREX 4238 +#define ARM_t2STREXB 4239 +#define ARM_t2STREXD 4240 +#define ARM_t2STREXH 4241 +#define ARM_t2STRHT 4242 +#define ARM_t2STRH_POST 4243 +#define ARM_t2STRH_PRE 4244 +#define ARM_t2STRHi12 4245 +#define ARM_t2STRHi8 4246 +#define ARM_t2STRHs 4247 +#define ARM_t2STRT 4248 +#define ARM_t2STR_POST 4249 +#define ARM_t2STR_PRE 4250 +#define ARM_t2STRi12 4251 +#define ARM_t2STRi8 4252 +#define ARM_t2STRs 4253 +#define ARM_t2SUBS_PC_LR 4254 +#define ARM_t2SUBri 4255 +#define ARM_t2SUBri12 4256 +#define ARM_t2SUBrr 4257 +#define ARM_t2SUBrs 4258 +#define ARM_t2SUBspImm 4259 +#define ARM_t2SUBspImm12 4260 +#define ARM_t2SXTAB 4261 +#define ARM_t2SXTAB16 4262 +#define ARM_t2SXTAH 4263 +#define ARM_t2SXTB 4264 +#define ARM_t2SXTB16 4265 +#define ARM_t2SXTH 4266 +#define ARM_t2TBB 4267 +#define ARM_t2TBH 4268 +#define ARM_t2TEQri 4269 +#define ARM_t2TEQrr 4270 +#define ARM_t2TEQrs 4271 +#define ARM_t2TSB 4272 +#define ARM_t2TSTri 4273 +#define ARM_t2TSTrr 4274 +#define ARM_t2TSTrs 4275 +#define ARM_t2TT 4276 +#define ARM_t2TTA 4277 +#define ARM_t2TTAT 4278 +#define ARM_t2TTT 4279 +#define ARM_t2UADD16 4280 +#define ARM_t2UADD8 4281 +#define ARM_t2UASX 4282 +#define ARM_t2UBFX 4283 +#define ARM_t2UDF 4284 +#define ARM_t2UDIV 4285 +#define ARM_t2UHADD16 4286 +#define ARM_t2UHADD8 4287 +#define ARM_t2UHASX 4288 +#define ARM_t2UHSAX 4289 +#define ARM_t2UHSUB16 4290 +#define ARM_t2UHSUB8 4291 +#define ARM_t2UMAAL 4292 +#define ARM_t2UMLAL 4293 +#define ARM_t2UMULL 4294 +#define ARM_t2UQADD16 4295 +#define ARM_t2UQADD8 4296 +#define ARM_t2UQASX 4297 +#define ARM_t2UQSAX 4298 +#define ARM_t2UQSUB16 4299 +#define ARM_t2UQSUB8 4300 +#define ARM_t2USAD8 4301 +#define ARM_t2USADA8 4302 +#define ARM_t2USAT 4303 +#define ARM_t2USAT16 4304 +#define ARM_t2USAX 4305 +#define ARM_t2USUB16 4306 +#define ARM_t2USUB8 4307 +#define ARM_t2UXTAB 4308 +#define ARM_t2UXTAB16 4309 +#define ARM_t2UXTAH 4310 +#define ARM_t2UXTB 4311 +#define ARM_t2UXTB16 4312 +#define ARM_t2UXTH 4313 +#define ARM_t2WLS 4314 +#define ARM_tADC 4315 +#define ARM_tADDhirr 4316 +#define ARM_tADDi3 4317 +#define ARM_tADDi8 4318 +#define ARM_tADDrSP 4319 +#define ARM_tADDrSPi 4320 +#define ARM_tADDrr 4321 +#define ARM_tADDspi 4322 +#define ARM_tADDspr 4323 +#define ARM_tADR 4324 +#define ARM_tAND 4325 +#define ARM_tASRri 4326 +#define ARM_tASRrr 4327 +#define ARM_tB 4328 +#define ARM_tBIC 4329 +#define ARM_tBKPT 4330 +#define ARM_tBL 4331 +#define ARM_tBLXNSr 4332 +#define ARM_tBLXi 4333 +#define ARM_tBLXr 4334 +#define ARM_tBX 4335 +#define ARM_tBXNS 4336 +#define ARM_tBcc 4337 +#define ARM_tCBNZ 4338 +#define ARM_tCBZ 4339 +#define ARM_tCMNz 4340 +#define ARM_tCMPhir 4341 +#define ARM_tCMPi8 4342 +#define ARM_tCMPr 4343 +#define ARM_tCPS 4344 +#define ARM_tEOR 4345 +#define ARM_tHINT 4346 +#define ARM_tHLT 4347 +#define ARM_tInt_WIN_eh_sjlj_longjmp 4348 +#define ARM_tInt_eh_sjlj_longjmp 4349 +#define ARM_tInt_eh_sjlj_setjmp 4350 +#define ARM_tLDMIA 4351 +#define ARM_tLDRBi 4352 +#define ARM_tLDRBr 4353 +#define ARM_tLDRHi 4354 +#define ARM_tLDRHr 4355 +#define ARM_tLDRSB 4356 +#define ARM_tLDRSH 4357 +#define ARM_tLDRi 4358 +#define ARM_tLDRpci 4359 +#define ARM_tLDRr 4360 +#define ARM_tLDRspi 4361 +#define ARM_tLSLri 4362 +#define ARM_tLSLrr 4363 +#define ARM_tLSRri 4364 +#define ARM_tLSRrr 4365 +#define ARM_tMOVSr 4366 +#define ARM_tMOVi8 4367 +#define ARM_tMOVr 4368 +#define ARM_tMUL 4369 +#define ARM_tMVN 4370 +#define ARM_tORR 4371 +#define ARM_tPICADD 4372 +#define ARM_tPOP 4373 +#define ARM_tPUSH 4374 +#define ARM_tREV 4375 +#define ARM_tREV16 4376 +#define ARM_tREVSH 4377 +#define ARM_tROR 4378 +#define ARM_tRSB 4379 +#define ARM_tSBC 4380 +#define ARM_tSETEND 4381 +#define ARM_tSTMIA_UPD 4382 +#define ARM_tSTRBi 4383 +#define ARM_tSTRBr 4384 +#define ARM_tSTRHi 4385 +#define ARM_tSTRHr 4386 +#define ARM_tSTRi 4387 +#define ARM_tSTRr 4388 +#define ARM_tSTRspi 4389 +#define ARM_tSUBi3 4390 +#define ARM_tSUBi8 4391 +#define ARM_tSUBrr 4392 +#define ARM_tSUBspi 4393 +#define ARM_tSVC 4394 +#define ARM_tSXTB 4395 +#define ARM_tSXTH 4396 +#define ARM_tTRAP 4397 +#define ARM_tTST 4398 +#define ARM_tUDF 4399 +#define ARM_tUXTB 4400 +#define ARM_tUXTH 4401 +#define ARM_t__brkdiv0 4402 +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_REGINFO_EXTRA +#undef GET_REGINFO_EXTRA + + // Register alternate name indices + + enum { + ARM_NoRegAltName, // 0 + ARM_RegNamesRaw, // 1 + ARM_NUM_TARGET_REG_ALT_NAMES = 2 + }; + +// Subregister indices + +enum { + NoSubRegister, + ARM_dsub_0, // 1 + ARM_dsub_1, // 2 + ARM_dsub_2, // 3 + ARM_dsub_3, // 4 + ARM_dsub_4, // 5 + ARM_dsub_5, // 6 + ARM_dsub_6, // 7 + ARM_dsub_7, // 8 + ARM_gsub_0, // 9 + ARM_gsub_1, // 10 + ARM_qqsub_0, // 11 + ARM_qqsub_1, // 12 + ARM_qsub_0, // 13 + ARM_qsub_1, // 14 + ARM_qsub_2, // 15 + ARM_qsub_3, // 16 + ARM_ssub_0, // 17 + ARM_ssub_1, // 18 + ARM_ssub_2, // 19 + ARM_ssub_3, // 20 + ARM_ssub_4, // 21 + ARM_ssub_5, // 22 + ARM_ssub_6, // 23 + ARM_ssub_7, // 24 + ARM_ssub_8, // 25 + ARM_ssub_9, // 26 + ARM_ssub_10, // 27 + ARM_ssub_11, // 28 + ARM_ssub_12, // 29 + ARM_ssub_13, // 30 + ARM_ssub_14, // 31 + ARM_ssub_15, // 32 + ARM_ssub_0_ssub_1_ssub_4_ssub_5, // 33 + ARM_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34 + ARM_ssub_2_ssub_3_ssub_6_ssub_7, // 35 + ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36 + ARM_ssub_2_ssub_3_ssub_4_ssub_5, // 37 + ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38 + ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39 + ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40 + ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41 + ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42 + ARM_ssub_4_ssub_5_ssub_8_ssub_9, // 43 + ARM_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44 + ARM_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45 + ARM_ssub_6_ssub_7_dsub_5, // 46 + ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47 + ARM_ssub_6_ssub_7_dsub_5_dsub_7, // 48 + ARM_ssub_6_ssub_7_ssub_8_ssub_9, // 49 + ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50 + ARM_ssub_8_ssub_9_ssub_12_ssub_13, // 51 + ARM_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52 + ARM_dsub_5_dsub_7, // 53 + ARM_dsub_5_ssub_12_ssub_13_dsub_7, // 54 + ARM_dsub_5_ssub_12_ssub_13, // 55 + ARM_ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56 + ARM_NUM_TARGET_SUBREGS +}; +#endif // GET_REGINFO_EXTRA + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg ARMRegDiffLists[] = { + /* 0 */ 64905, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 17 */ 37, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 32 */ 41, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 45 */ 45, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 56 */ 64431, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 65 */ 64965, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 74 */ 65245, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 83 */ 43, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 91 */ 45, + 1, + 1, + 1, + 1, + 1, + 0, + /* 98 */ 65189, + 1, + 1, + 1, + 1, + 1, + 0, + /* 105 */ 45, + 1, + 1, + 1, + 1, + 0, + /* 111 */ 47, + 1, + 1, + 1, + 1, + 0, + /* 117 */ 47, + 1, + 1, + 1, + 0, + /* 122 */ 64491, + 1, + 1, + 1, + 0, + /* 127 */ 65008, + 1, + 1, + 1, + 0, + /* 132 */ 65275, + 1, + 1, + 1, + 0, + /* 137 */ 65329, + 1, + 1, + 1, + 0, + /* 142 */ 13, + 1, + 1, + 0, + /* 146 */ 47, + 1, + 1, + 0, + /* 150 */ 65387, + 1, + 1, + 0, + /* 154 */ 137, + 65489, + 48, + 65489, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 164 */ 136, + 65490, + 47, + 65490, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 174 */ 135, + 65491, + 46, + 65491, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 184 */ 134, + 65492, + 45, + 65492, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 194 */ 133, + 65493, + 44, + 65493, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 204 */ 132, + 65494, + 43, + 65494, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 214 */ 131, + 65495, + 42, + 65495, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 224 */ 130, + 65496, + 41, + 65496, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 234 */ 129, + 65497, + 40, + 65497, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 244 */ 128, + 65498, + 39, + 65498, + 12, + 121, + 65416, + 1, + 1, + 0, + /* 254 */ 65489, + 133, + 65416, + 1, + 1, + 0, + /* 260 */ 65490, + 133, + 65416, + 1, + 1, + 0, + /* 266 */ 65491, + 133, + 65416, + 1, + 1, + 0, + /* 272 */ 65492, + 133, + 65416, + 1, + 1, + 0, + /* 278 */ 65493, + 133, + 65416, + 1, + 1, + 0, + /* 284 */ 65494, + 133, + 65416, + 1, + 1, + 0, + /* 290 */ 65495, + 133, + 65416, + 1, + 1, + 0, + /* 296 */ 65496, + 133, + 65416, + 1, + 1, + 0, + /* 302 */ 65497, + 133, + 65416, + 1, + 1, + 0, + /* 308 */ 65498, + 133, + 65416, + 1, + 1, + 0, + /* 314 */ 127, + 65499, + 38, + 65499, + 133, + 65416, + 1, + 1, + 0, + /* 323 */ 65073, + 1, + 3, + 1, + 3, + 1, + 3, + 1, + 0, + /* 332 */ 65129, + 1, + 3, + 1, + 3, + 1, + 0, + /* 339 */ 65319, + 1, + 3, + 1, + 0, + /* 344 */ 13, + 1, + 0, + /* 347 */ 14, + 1, + 0, + /* 350 */ 66, + 1, + 0, + /* 353 */ 65499, + 66, + 1, + 65470, + 67, + 1, + 0, + /* 360 */ 65290, + 67, + 1, + 65469, + 68, + 1, + 0, + /* 367 */ 65438, + 66, + 1, + 65471, + 68, + 1, + 0, + /* 374 */ 65500, + 68, + 1, + 65468, + 69, + 1, + 0, + /* 381 */ 65438, + 67, + 1, + 65470, + 69, + 1, + 0, + /* 388 */ 65291, + 69, + 1, + 65467, + 70, + 1, + 0, + /* 395 */ 65438, + 68, + 1, + 65469, + 70, + 1, + 0, + /* 402 */ 65501, + 70, + 1, + 65466, + 71, + 1, + 0, + /* 409 */ 65438, + 69, + 1, + 65468, + 71, + 1, + 0, + /* 416 */ 65292, + 71, + 1, + 65465, + 72, + 1, + 0, + /* 423 */ 65438, + 70, + 1, + 65467, + 72, + 1, + 0, + /* 430 */ 65502, + 72, + 1, + 65464, + 73, + 1, + 0, + /* 437 */ 65438, + 71, + 1, + 65466, + 73, + 1, + 0, + /* 444 */ 65293, + 73, + 1, + 65463, + 74, + 1, + 0, + /* 451 */ 65438, + 72, + 1, + 65465, + 74, + 1, + 0, + /* 458 */ 65503, + 74, + 1, + 65462, + 75, + 1, + 0, + /* 465 */ 65438, + 73, + 1, + 65464, + 75, + 1, + 0, + /* 472 */ 65294, + 75, + 1, + 65461, + 76, + 1, + 0, + /* 479 */ 65438, + 74, + 1, + 65463, + 76, + 1, + 0, + /* 486 */ 65504, + 76, + 1, + 65460, + 77, + 1, + 0, + /* 493 */ 65438, + 75, + 1, + 65462, + 77, + 1, + 0, + /* 500 */ 65295, + 77, + 1, + 65459, + 78, + 1, + 0, + /* 507 */ 65438, + 76, + 1, + 65461, + 78, + 1, + 0, + /* 514 */ 65505, + 78, + 1, + 65458, + 79, + 1, + 0, + /* 521 */ 65438, + 77, + 1, + 65460, + 79, + 1, + 0, + /* 528 */ 65296, + 79, + 1, + 65457, + 80, + 1, + 0, + /* 535 */ 65438, + 78, + 1, + 65459, + 80, + 1, + 0, + /* 542 */ 65506, + 80, + 1, + 65456, + 81, + 1, + 0, + /* 549 */ 65438, + 79, + 1, + 65458, + 81, + 1, + 0, + /* 556 */ 65038, + 1, + 0, + /* 559 */ 65256, + 1, + 0, + /* 562 */ 65298, + 1, + 0, + /* 565 */ 65299, + 1, + 0, + /* 568 */ 65300, + 1, + 0, + /* 571 */ 65301, + 1, + 0, + /* 574 */ 65302, + 1, + 0, + /* 577 */ 65303, + 1, + 0, + /* 580 */ 65304, + 1, + 0, + /* 583 */ 65453, + 1, + 65499, + 133, + 1, + 65416, + 1, + 0, + /* 591 */ 138, + 65488, + 49, + 65488, + 12, + 121, + 65416, + 1, + 0, + /* 600 */ 65488, + 13, + 121, + 65416, + 1, + 0, + /* 606 */ 65489, + 13, + 121, + 65416, + 1, + 0, + /* 612 */ 65490, + 13, + 121, + 65416, + 1, + 0, + /* 618 */ 65491, + 13, + 121, + 65416, + 1, + 0, + /* 624 */ 65492, + 13, + 121, + 65416, + 1, + 0, + /* 630 */ 65493, + 13, + 121, + 65416, + 1, + 0, + /* 636 */ 65494, + 13, + 121, + 65416, + 1, + 0, + /* 642 */ 65495, + 13, + 121, + 65416, + 1, + 0, + /* 648 */ 65496, + 13, + 121, + 65416, + 1, + 0, + /* 654 */ 65497, + 13, + 121, + 65416, + 1, + 0, + /* 660 */ 65498, + 13, + 121, + 65416, + 1, + 0, + /* 666 */ 65464, + 1, + 65488, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 675 */ 65463, + 1, + 65489, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 684 */ 65462, + 1, + 65490, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 693 */ 65461, + 1, + 65491, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 702 */ 65460, + 1, + 65492, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 711 */ 65459, + 1, + 65493, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 720 */ 65458, + 1, + 65494, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 729 */ 65457, + 1, + 65495, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 738 */ 65456, + 1, + 65496, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 747 */ 65455, + 1, + 65497, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 756 */ 65454, + 1, + 65498, + 133, + 65416, + 121, + 65416, + 1, + 0, + /* 765 */ 65488, + 133, + 65416, + 1, + 0, + /* 770 */ 65499, + 134, + 65416, + 1, + 0, + /* 775 */ 126, + 65500, + 37, + 65500, + 133, + 65417, + 1, + 0, + /* 783 */ 65433, + 1, + 0, + /* 786 */ 65434, + 1, + 0, + /* 789 */ 65435, + 1, + 0, + /* 792 */ 65436, + 1, + 0, + /* 795 */ 65437, + 1, + 0, + /* 798 */ 65438, + 1, + 0, + /* 801 */ 65457, + 1, + 0, + /* 804 */ 65507, + 1, + 0, + /* 807 */ 65508, + 1, + 0, + /* 810 */ 65509, + 1, + 0, + /* 813 */ 65510, + 1, + 0, + /* 816 */ 65511, + 1, + 0, + /* 819 */ 65512, + 1, + 0, + /* 822 */ 65513, + 1, + 0, + /* 825 */ 65514, + 1, + 0, + /* 828 */ 65515, + 1, + 0, + /* 831 */ 65073, + 1, + 3, + 1, + 3, + 1, + 2, + 0, + /* 839 */ 65129, + 1, + 3, + 1, + 2, + 0, + /* 845 */ 65319, + 1, + 2, + 0, + /* 849 */ 65073, + 1, + 3, + 1, + 2, + 2, + 0, + /* 856 */ 65129, + 1, + 2, + 2, + 0, + /* 861 */ 65073, + 1, + 2, + 2, + 2, + 0, + /* 867 */ 65329, + 2, + 2, + 2, + 0, + /* 872 */ 65073, + 1, + 3, + 2, + 2, + 0, + /* 878 */ 65357, + 2, + 2, + 0, + /* 882 */ 65073, + 1, + 3, + 1, + 3, + 2, + 0, + /* 889 */ 65129, + 1, + 3, + 2, + 0, + /* 894 */ 65343, + 77, + 1, + 65460, + 79, + 1, + 65458, + 81, + 1, + 12, + 2, + 0, + /* 906 */ 65343, + 76, + 1, + 65461, + 78, + 1, + 65459, + 80, + 1, + 13, + 2, + 0, + /* 918 */ 65343, + 75, + 1, + 65462, + 77, + 1, + 65460, + 79, + 1, + 14, + 2, + 0, + /* 930 */ 65343, + 74, + 1, + 65463, + 76, + 1, + 65461, + 78, + 1, + 15, + 2, + 0, + /* 942 */ 65343, + 73, + 1, + 65464, + 75, + 1, + 65462, + 77, + 1, + 16, + 2, + 0, + /* 954 */ 65343, + 72, + 1, + 65465, + 74, + 1, + 65463, + 76, + 1, + 17, + 2, + 0, + /* 966 */ 65343, + 71, + 1, + 65466, + 73, + 1, + 65464, + 75, + 1, + 18, + 2, + 0, + /* 978 */ 65343, + 70, + 1, + 65467, + 72, + 1, + 65465, + 74, + 1, + 19, + 2, + 0, + /* 990 */ 65343, + 69, + 1, + 65468, + 71, + 1, + 65466, + 73, + 1, + 20, + 2, + 0, + /* 1002 */ 65343, + 68, + 1, + 65469, + 70, + 1, + 65467, + 72, + 1, + 21, + 2, + 0, + /* 1014 */ 65343, + 67, + 1, + 65470, + 69, + 1, + 65468, + 71, + 1, + 22, + 2, + 0, + /* 1026 */ 65343, + 66, + 1, + 65471, + 68, + 1, + 65469, + 70, + 1, + 23, + 2, + 0, + /* 1038 */ 65343, + 2, + 2, + 94, + 2, + 0, + /* 1044 */ 65343, + 81, + 1, + 65456, + 2, + 94, + 2, + 0, + /* 1052 */ 65343, + 80, + 1, + 65457, + 2, + 94, + 2, + 0, + /* 1060 */ 65343, + 79, + 1, + 65458, + 81, + 1, + 65456, + 94, + 2, + 0, + /* 1070 */ 65343, + 78, + 1, + 65459, + 80, + 1, + 65457, + 94, + 2, + 0, + /* 1080 */ 65438, + 2, + 0, + /* 1083 */ 65452, + 2, + 0, + /* 1086 */ 65073, + 1, + 3, + 1, + 3, + 1, + 3, + 0, + /* 1094 */ 65129, + 1, + 3, + 1, + 3, + 0, + /* 1100 */ 65319, + 1, + 3, + 0, + /* 1104 */ 7, + 0, + /* 1106 */ 140, + 65486, + 13, + 0, + /* 1110 */ 14, + 0, + /* 1112 */ 126, + 65501, + 15, + 0, + /* 1116 */ 13, + 69, + 0, + /* 1119 */ 65445, + 65513, + 1, + 23, + 65514, + 1, + 95, + 65, + 65472, + 65, + 69, + 0, + /* 1131 */ 65445, + 65512, + 1, + 24, + 65513, + 1, + 95, + 65, + 65472, + 65, + 70, + 0, + /* 1143 */ 65445, + 65511, + 1, + 25, + 65512, + 1, + 95, + 65, + 65472, + 65, + 71, + 0, + /* 1155 */ 65445, + 65510, + 1, + 26, + 65511, + 1, + 95, + 65, + 65472, + 65, + 72, + 0, + /* 1167 */ 65445, + 65509, + 1, + 27, + 65510, + 1, + 95, + 65, + 65472, + 65, + 73, + 0, + /* 1179 */ 65445, + 65508, + 1, + 28, + 65509, + 1, + 95, + 65, + 65472, + 65, + 74, + 0, + /* 1191 */ 65445, + 65507, + 1, + 29, + 65508, + 1, + 95, + 65, + 65472, + 65, + 75, + 0, + /* 1203 */ 65445, + 65506, + 80, + 1, + 65456, + 81, + 1, + 65484, + 65507, + 1, + 95, + 65, + 65472, + 65, + 76, + 0, + /* 1219 */ 65445, + 65505, + 78, + 1, + 65458, + 79, + 1, + 65487, + 65506, + 80, + 1, + 65456, + 81, + 1, + 13, + 65, + 65472, + 65, + 77, + 0, + /* 1239 */ 65445, + 65504, + 76, + 1, + 65460, + 77, + 1, + 65490, + 65505, + 78, + 1, + 65458, + 79, + 1, + 15, + 65, + 65472, + 65, + 78, + 0, + /* 1259 */ 65445, + 65503, + 74, + 1, + 65462, + 75, + 1, + 65493, + 65504, + 76, + 1, + 65460, + 77, + 1, + 17, + 65, + 65472, + 65, + 79, + 0, + /* 1279 */ 65445, + 65502, + 72, + 1, + 65464, + 73, + 1, + 65496, + 65503, + 74, + 1, + 65462, + 75, + 1, + 19, + 65, + 65472, + 65, + 80, + 0, + /* 1299 */ 65445, + 65501, + 70, + 1, + 65466, + 71, + 1, + 65499, + 65502, + 72, + 1, + 65464, + 73, + 1, + 21, + 65, + 65472, + 65, + 81, + 0, + /* 1319 */ 65445, + 65500, + 68, + 1, + 65468, + 69, + 1, + 65502, + 65501, + 70, + 1, + 65466, + 71, + 1, + 23, + 65, + 65472, + 65, + 82, + 0, + /* 1339 */ 65445, + 65499, + 66, + 1, + 65470, + 67, + 1, + 65505, + 65500, + 68, + 1, + 65468, + 69, + 1, + 25, + 65, + 65472, + 65, + 83, + 0, + /* 1359 */ 97, + 0, + /* 1361 */ 98, + 0, + /* 1363 */ 99, + 0, + /* 1365 */ 100, + 0, + /* 1367 */ 101, + 0, + /* 1369 */ 102, + 0, + /* 1371 */ 103, + 0, + /* 1373 */ 65373, + 1, + 1, + 21, + 75, + 135, + 0, + /* 1380 */ 65373, + 1, + 1, + 22, + 74, + 136, + 0, + /* 1387 */ 65373, + 1, + 1, + 23, + 73, + 137, + 0, + /* 1394 */ 65373, + 1, + 1, + 24, + 72, + 138, + 0, + /* 1401 */ 65373, + 1, + 1, + 25, + 71, + 139, + 0, + /* 1408 */ 65373, + 1, + 1, + 26, + 70, + 140, + 0, + /* 1415 */ 65373, + 1, + 1, + 27, + 69, + 141, + 0, + /* 1422 */ 65373, + 80, + 1, + 65456, + 81, + 1, + 65455, + 28, + 68, + 142, + 0, + /* 1433 */ 65373, + 78, + 1, + 65458, + 79, + 1, + 65457, + 80, + 1, + 65484, + 67, + 143, + 0, + /* 1446 */ 65373, + 76, + 1, + 65460, + 77, + 1, + 65459, + 78, + 1, + 65487, + 66, + 144, + 0, + /* 1459 */ 65373, + 74, + 1, + 65462, + 75, + 1, + 65461, + 76, + 1, + 65490, + 65, + 145, + 0, + /* 1472 */ 65373, + 72, + 1, + 65464, + 73, + 1, + 65463, + 74, + 1, + 65493, + 64, + 146, + 0, + /* 1485 */ 65373, + 70, + 1, + 65466, + 71, + 1, + 65465, + 72, + 1, + 65496, + 63, + 147, + 0, + /* 1498 */ 65373, + 68, + 1, + 65468, + 69, + 1, + 65467, + 70, + 1, + 65499, + 62, + 148, + 0, + /* 1511 */ 65373, + 66, + 1, + 65470, + 67, + 1, + 65469, + 68, + 1, + 65502, + 61, + 149, + 0, + /* 1524 */ 166, + 0, + /* 1526 */ 65288, + 1, + 1, + 1, + 230, + 1, + 65400, + 65, + 65472, + 65, + 65396, + 0, + /* 1538 */ 65287, + 1, + 1, + 1, + 231, + 1, + 65399, + 65, + 65472, + 65, + 65397, + 0, + /* 1550 */ 65286, + 1, + 1, + 1, + 232, + 1, + 65398, + 65, + 65472, + 65, + 65398, + 0, + /* 1562 */ 65285, + 1, + 1, + 1, + 233, + 1, + 65397, + 65, + 65472, + 65, + 65399, + 0, + /* 1574 */ 65284, + 1, + 1, + 1, + 234, + 1, + 65396, + 65, + 65472, + 65, + 65400, + 0, + /* 1586 */ 65283, + 1, + 1, + 1, + 235, + 1, + 65395, + 65, + 65472, + 65, + 65401, + 0, + /* 1598 */ 65521, + 65445, + 65511, + 1, + 25, + 65512, + 1, + 95, + 65, + 65472, + 65, + 71, + 65419, + 65445, + 65513, + 1, + 23, + 65514, + 1, + 95, + 65, + 65472, + 65, + 69, + 65492, + 28, + 65509, + 28, + 28, + 65386, + 65, + 30, + 65442, + 65, + 30, + 40, + 15, + 65402, + 0, + /* 1637 */ 65521, + 65445, + 65510, + 1, + 26, + 65511, + 1, + 95, + 65, + 65472, + 65, + 72, + 65419, + 65445, + 65512, + 1, + 24, + 65513, + 1, + 95, + 65, + 65472, + 65, + 70, + 65491, + 28, + 65509, + 28, + 29, + 65385, + 65, + 30, + 65442, + 65, + 30, + 41, + 15, + 65402, + 0, + /* 1676 */ 65521, + 65445, + 65509, + 1, + 27, + 65510, + 1, + 95, + 65, + 65472, + 65, + 73, + 65419, + 65445, + 65511, + 1, + 25, + 65512, + 1, + 95, + 65, + 65472, + 65, + 71, + 65490, + 28, + 65509, + 28, + 30, + 65384, + 65, + 30, + 65442, + 65, + 30, + 42, + 15, + 65402, + 0, + /* 1715 */ 65521, + 65445, + 65508, + 1, + 28, + 65509, + 1, + 95, + 65, + 65472, + 65, + 74, + 65419, + 65445, + 65510, + 1, + 26, + 65511, + 1, + 95, + 65, + 65472, + 65, + 72, + 65489, + 28, + 65509, + 28, + 31, + 65383, + 65, + 30, + 65442, + 65, + 30, + 43, + 15, + 65402, + 0, + /* 1754 */ 65521, + 65445, + 65507, + 1, + 29, + 65508, + 1, + 95, + 65, + 65472, + 65, + 75, + 65419, + 65445, + 65509, + 1, + 27, + 65510, + 1, + 95, + 65, + 65472, + 65, + 73, + 65488, + 28, + 65509, + 28, + 32, + 65382, + 65, + 30, + 65442, + 65, + 30, + 44, + 15, + 65402, + 0, + /* 1793 */ 65521, + 65445, + 65506, + 80, + 1, + 65456, + 81, + 1, + 65484, + 65507, + 1, + 95, + 65, + 65472, + 65, + 76, + 65419, + 65445, + 65508, + 1, + 28, + 65509, + 1, + 95, + 65, + 65472, + 65, + 74, + 65487, + 28, + 65509, + 28, + 33, + 65381, + 65, + 30, + 65442, + 65, + 30, + 45, + 15, + 65402, + 0, + /* 1836 */ 65521, + 65445, + 65505, + 78, + 1, + 65458, + 79, + 1, + 65487, + 65506, + 80, + 1, + 65456, + 81, + 1, + 13, + 65, + 65472, + 65, + 77, + 65419, + 65445, + 65507, + 1, + 29, + 65508, + 1, + 95, + 65, + 65472, + 65, + 75, + 65486, + 28, + 65509, + 28, + 34, + 65380, + 65, + 30, + 65442, + 65, + 30, + 46, + 15, + 65402, + 0, + /* 1883 */ 65521, + 65445, + 65504, + 76, + 1, + 65460, + 77, + 1, + 65490, + 65505, + 78, + 1, + 65458, + 79, + 1, + 15, + 65, + 65472, + 65, + 78, + 65419, + 65445, + 65506, + 80, + 1, + 65456, + 81, + 1, + 65484, + 65507, + 1, + 95, + 65, + 65472, + 65, + 76, + 65485, + 28, + 65509, + 28, + 35, + 65379, + 65, + 30, + 65442, + 65, + 30, + 47, + 15, + 65402, + 0, + /* 1934 */ 65521, + 65445, + 65503, + 74, + 1, + 65462, + 75, + 1, + 65493, + 65504, + 76, + 1, + 65460, + 77, + 1, + 17, + 65, + 65472, + 65, + 79, + 65419, + 65445, + 65505, + 78, + 1, + 65458, + 79, + 1, + 65487, + 65506, + 80, + 1, + 65456, + 81, + 1, + 13, + 65, + 65472, + 65, + 77, + 65484, + 28, + 65509, + 28, + 36, + 65378, + 65, + 30, + 65442, + 65, + 30, + 48, + 15, + 65402, + 0, + /* 1989 */ 65521, + 65445, + 65502, + 72, + 1, + 65464, + 73, + 1, + 65496, + 65503, + 74, + 1, + 65462, + 75, + 1, + 19, + 65, + 65472, + 65, + 80, + 65419, + 65445, + 65504, + 76, + 1, + 65460, + 77, + 1, + 65490, + 65505, + 78, + 1, + 65458, + 79, + 1, + 15, + 65, + 65472, + 65, + 78, + 65483, + 28, + 65509, + 28, + 37, + 65377, + 65, + 30, + 65442, + 65, + 30, + 49, + 15, + 65402, + 0, + /* 2044 */ 65521, + 65445, + 65501, + 70, + 1, + 65466, + 71, + 1, + 65499, + 65502, + 72, + 1, + 65464, + 73, + 1, + 21, + 65, + 65472, + 65, + 81, + 65419, + 65445, + 65503, + 74, + 1, + 65462, + 75, + 1, + 65493, + 65504, + 76, + 1, + 65460, + 77, + 1, + 17, + 65, + 65472, + 65, + 79, + 65482, + 28, + 65509, + 28, + 38, + 65376, + 65, + 30, + 65442, + 65, + 30, + 50, + 15, + 65402, + 0, + /* 2099 */ 65521, + 65445, + 65500, + 68, + 1, + 65468, + 69, + 1, + 65502, + 65501, + 70, + 1, + 65466, + 71, + 1, + 23, + 65, + 65472, + 65, + 82, + 65419, + 65445, + 65502, + 72, + 1, + 65464, + 73, + 1, + 65496, + 65503, + 74, + 1, + 65462, + 75, + 1, + 19, + 65, + 65472, + 65, + 80, + 65481, + 28, + 65509, + 28, + 39, + 65375, + 65, + 30, + 65442, + 65, + 30, + 51, + 15, + 65402, + 0, + /* 2154 */ 65521, + 65445, + 65499, + 66, + 1, + 65470, + 67, + 1, + 65505, + 65500, + 68, + 1, + 65468, + 69, + 1, + 25, + 65, + 65472, + 65, + 83, + 65419, + 65445, + 65501, + 70, + 1, + 65466, + 71, + 1, + 65499, + 65502, + 72, + 1, + 65464, + 73, + 1, + 21, + 65, + 65472, + 65, + 81, + 65480, + 28, + 65509, + 28, + 40, + 65374, + 65, + 30, + 65442, + 65, + 30, + 52, + 15, + 65402, + 0, + /* 2209 */ 65282, + 81, + 1, + 65455, + 1, + 1, + 236, + 1, + 65394, + 65, + 65472, + 65, + 65402, + 0, + /* 2223 */ 65281, + 79, + 1, + 65457, + 80, + 1, + 65456, + 81, + 1, + 65455, + 237, + 1, + 65393, + 65, + 65472, + 65, + 65403, + 0, + /* 2241 */ 65280, + 77, + 1, + 65459, + 78, + 1, + 65458, + 79, + 1, + 65457, + 80, + 1, + 157, + 1, + 65392, + 65, + 65472, + 65, + 65404, + 0, + /* 2261 */ 65279, + 75, + 1, + 65461, + 76, + 1, + 65460, + 77, + 1, + 65459, + 78, + 1, + 160, + 1, + 65391, + 65, + 65472, + 65, + 65405, + 0, + /* 2281 */ 65278, + 73, + 1, + 65463, + 74, + 1, + 65462, + 75, + 1, + 65461, + 76, + 1, + 163, + 1, + 65390, + 65, + 65472, + 65, + 65406, + 0, + /* 2301 */ 65277, + 71, + 1, + 65465, + 72, + 1, + 65464, + 73, + 1, + 65463, + 74, + 1, + 166, + 1, + 65389, + 65, + 65472, + 65, + 65407, + 0, + /* 2321 */ 65276, + 69, + 1, + 65467, + 70, + 1, + 65466, + 71, + 1, + 65465, + 72, + 1, + 169, + 1, + 65388, + 65, + 65472, + 65, + 65408, + 0, + /* 2341 */ 65275, + 67, + 1, + 65469, + 68, + 1, + 65468, + 69, + 1, + 65467, + 70, + 1, + 172, + 1, + 65387, + 65, + 65472, + 65, + 65409, + 0, + /* 2361 */ 23, + 73, + 2, + 63, + 65488, + 120, + 65465, + 1, + 65487, + 75, + 26, + 65447, + 65, + 26, + 30, + 65416, + 66, + 26, + 29, + 65416, + 0, + /* 2382 */ 22, + 74, + 2, + 63, + 65487, + 120, + 65466, + 1, + 65486, + 76, + 26, + 65446, + 66, + 26, + 29, + 65416, + 0, + /* 2399 */ 65, + 65487, + 77, + 26, + 65446, + 66, + 26, + 29, + 65416, + 0, + /* 2409 */ 23, + 73, + 2, + 134, + 65465, + 1, + 65487, + 50, + 65487, + 75, + 26, + 31, + 65416, + 65, + 26, + 30, + 65416, + 0, + /* 2427 */ 22, + 74, + 135, + 65466, + 1, + 65486, + 77, + 26, + 30, + 65416, + 0, + /* 2438 */ 65, + 65487, + 77, + 26, + 30, + 65416, + 0, + /* 2445 */ 139, + 65487, + 50, + 65487, + 12, + 121, + 65416, + 0, + /* 2453 */ 65487, + 13, + 121, + 65416, + 0, + /* 2458 */ 65465, + 1, + 65487, + 133, + 65416, + 121, + 65416, + 0, + /* 2466 */ 65466, + 1, + 65486, + 133, + 65416, + 0, + /* 2472 */ 65487, + 133, + 65416, + 0, + /* 2476 */ 65468, + 36, + 62, + 148, + 65452, + 1, + 65500, + 66, + 28, + 40, + 65417, + 0, + /* 2488 */ 65469, + 36, + 62, + 148, + 65452, + 1, + 65500, + 66, + 28, + 40, + 65417, + 0, + /* 2500 */ 65, + 65500, + 66, + 28, + 40, + 65417, + 0, + /* 2507 */ 65452, + 1, + 65500, + 134, + 65417, + 0, + /* 2513 */ 65315, + 75, + 1, + 65462, + 77, + 1, + 65460, + 79, + 1, + 65458, + 81, + 1, + 10, + 95, + 65443, + 95, + 65443, + 0, + /* 2531 */ 65315, + 74, + 1, + 65463, + 76, + 1, + 65461, + 78, + 1, + 65459, + 80, + 1, + 11, + 95, + 65443, + 95, + 65443, + 0, + /* 2549 */ 65315, + 73, + 1, + 65464, + 75, + 1, + 65462, + 77, + 1, + 65460, + 79, + 1, + 12, + 95, + 65443, + 95, + 65443, + 0, + /* 2567 */ 65315, + 72, + 1, + 65465, + 74, + 1, + 65463, + 76, + 1, + 65461, + 78, + 1, + 13, + 95, + 65443, + 95, + 65443, + 0, + /* 2585 */ 65315, + 71, + 1, + 65466, + 73, + 1, + 65464, + 75, + 1, + 65462, + 77, + 1, + 14, + 95, + 65443, + 95, + 65443, + 0, + /* 2603 */ 65315, + 70, + 1, + 65467, + 72, + 1, + 65465, + 74, + 1, + 65463, + 76, + 1, + 15, + 95, + 65443, + 95, + 65443, + 0, + /* 2621 */ 65315, + 69, + 1, + 65468, + 71, + 1, + 65466, + 73, + 1, + 65464, + 75, + 1, + 16, + 95, + 65443, + 95, + 65443, + 0, + /* 2639 */ 65315, + 68, + 1, + 65469, + 70, + 1, + 65467, + 72, + 1, + 65465, + 74, + 1, + 17, + 95, + 65443, + 95, + 65443, + 0, + /* 2657 */ 65315, + 67, + 1, + 65470, + 69, + 1, + 65468, + 71, + 1, + 65466, + 73, + 1, + 18, + 95, + 65443, + 95, + 65443, + 0, + /* 2675 */ 65315, + 66, + 1, + 65471, + 68, + 1, + 65469, + 70, + 1, + 65467, + 72, + 1, + 19, + 95, + 65443, + 95, + 65443, + 0, + /* 2693 */ 65315, + 2, + 2, + 2, + 92, + 95, + 65443, + 95, + 65443, + 0, + /* 2703 */ 65315, + 81, + 1, + 65456, + 2, + 2, + 92, + 95, + 65443, + 95, + 65443, + 0, + /* 2715 */ 65315, + 80, + 1, + 65457, + 2, + 2, + 92, + 95, + 65443, + 95, + 65443, + 0, + /* 2727 */ 65315, + 79, + 1, + 65458, + 81, + 1, + 65456, + 2, + 92, + 95, + 65443, + 95, + 65443, + 0, + /* 2741 */ 65315, + 78, + 1, + 65459, + 80, + 1, + 65457, + 2, + 92, + 95, + 65443, + 95, + 65443, + 0, + /* 2755 */ 65315, + 77, + 1, + 65460, + 79, + 1, + 65458, + 81, + 1, + 65456, + 92, + 95, + 65443, + 95, + 65443, + 0, + /* 2771 */ 65315, + 76, + 1, + 65461, + 78, + 1, + 65459, + 80, + 1, + 65457, + 92, + 95, + 65443, + 95, + 65443, + 0, + /* 2787 */ 21, + 75, + 65, + 65486, + 78, + 26, + 65445, + 0, + /* 2795 */ 24, + 72, + 2, + 63, + 65489, + 120, + 65464, + 1, + 65488, + 74, + 26, + 65448, + 64, + 26, + 31, + 65416, + 65, + 26, + 30, + 65416, + 92, + 65445, + 0, + /* 2818 */ 65, + 65488, + 76, + 26, + 65447, + 65, + 26, + 30, + 65416, + 92, + 65445, + 0, + /* 2830 */ 26, + 65446, + 92, + 65445, + 0, + /* 2835 */ 24, + 72, + 2, + 135, + 65464, + 1, + 65488, + 49, + 65488, + 74, + 26, + 32, + 65416, + 64, + 26, + 31, + 65416, + 65, + 26, + 65446, + 0, + /* 2856 */ 65, + 65488, + 76, + 26, + 31, + 65416, + 65, + 26, + 65446, + 0, + /* 2866 */ 25, + 71, + 2, + 63, + 65490, + 120, + 65463, + 1, + 65489, + 73, + 26, + 65449, + 63, + 26, + 32, + 65416, + 64, + 26, + 31, + 65416, + 91, + 65446, + 0, + /* 2889 */ 65, + 65489, + 75, + 26, + 65448, + 64, + 26, + 31, + 65416, + 91, + 65446, + 0, + /* 2901 */ 25, + 71, + 2, + 136, + 65463, + 1, + 65489, + 48, + 65489, + 73, + 26, + 33, + 65416, + 63, + 26, + 32, + 65416, + 64, + 26, + 65447, + 91, + 65446, + 0, + /* 2924 */ 65, + 65489, + 75, + 26, + 32, + 65416, + 64, + 26, + 65447, + 91, + 65446, + 0, + /* 2936 */ 26, + 70, + 2, + 63, + 65491, + 120, + 65462, + 1, + 65490, + 72, + 26, + 65450, + 62, + 26, + 33, + 65416, + 63, + 26, + 32, + 65416, + 90, + 65447, + 0, + /* 2959 */ 65, + 65490, + 74, + 26, + 65449, + 63, + 26, + 32, + 65416, + 90, + 65447, + 0, + /* 2971 */ 26, + 70, + 2, + 137, + 65462, + 1, + 65490, + 47, + 65490, + 72, + 26, + 34, + 65416, + 62, + 26, + 33, + 65416, + 63, + 26, + 65448, + 90, + 65447, + 0, + /* 2994 */ 65, + 65490, + 74, + 26, + 33, + 65416, + 63, + 26, + 65448, + 90, + 65447, + 0, + /* 3006 */ 27, + 69, + 2, + 63, + 65492, + 120, + 65461, + 1, + 65491, + 71, + 26, + 65451, + 61, + 26, + 34, + 65416, + 62, + 26, + 33, + 65416, + 89, + 65448, + 0, + /* 3029 */ 65, + 65491, + 73, + 26, + 65450, + 62, + 26, + 33, + 65416, + 89, + 65448, + 0, + /* 3041 */ 27, + 69, + 2, + 138, + 65461, + 1, + 65491, + 46, + 65491, + 71, + 26, + 35, + 65416, + 61, + 26, + 34, + 65416, + 62, + 26, + 65449, + 89, + 65448, + 0, + /* 3064 */ 65, + 65491, + 73, + 26, + 34, + 65416, + 62, + 26, + 65449, + 89, + 65448, + 0, + /* 3076 */ 28, + 68, + 2, + 63, + 65493, + 120, + 65460, + 1, + 65492, + 70, + 26, + 65452, + 60, + 26, + 35, + 65416, + 61, + 26, + 34, + 65416, + 88, + 65449, + 0, + /* 3099 */ 65, + 65492, + 72, + 26, + 65451, + 61, + 26, + 34, + 65416, + 88, + 65449, + 0, + /* 3111 */ 28, + 68, + 2, + 139, + 65460, + 1, + 65492, + 45, + 65492, + 70, + 26, + 36, + 65416, + 60, + 26, + 35, + 65416, + 61, + 26, + 65450, + 88, + 65449, + 0, + /* 3134 */ 65, + 65492, + 72, + 26, + 35, + 65416, + 61, + 26, + 65450, + 88, + 65449, + 0, + /* 3146 */ 65454, + 29, + 67, + 2, + 63, + 65494, + 120, + 65459, + 1, + 65493, + 69, + 26, + 65453, + 59, + 26, + 36, + 65416, + 60, + 26, + 35, + 65416, + 87, + 65450, + 0, + /* 3170 */ 65455, + 29, + 67, + 2, + 63, + 65494, + 120, + 65459, + 1, + 65493, + 69, + 26, + 65453, + 59, + 26, + 36, + 65416, + 60, + 26, + 35, + 65416, + 87, + 65450, + 0, + /* 3194 */ 65, + 65493, + 71, + 26, + 65452, + 60, + 26, + 35, + 65416, + 87, + 65450, + 0, + /* 3206 */ 29, + 67, + 2, + 140, + 65459, + 1, + 65493, + 44, + 65493, + 69, + 26, + 37, + 65416, + 59, + 26, + 36, + 65416, + 60, + 26, + 65451, + 87, + 65450, + 0, + /* 3229 */ 65, + 65493, + 71, + 26, + 36, + 65416, + 60, + 26, + 65451, + 87, + 65450, + 0, + /* 3241 */ 65456, + 30, + 66, + 2, + 63, + 65495, + 120, + 65458, + 1, + 65494, + 68, + 26, + 65454, + 58, + 26, + 37, + 65416, + 59, + 26, + 36, + 65416, + 86, + 65451, + 0, + /* 3265 */ 65457, + 30, + 66, + 2, + 63, + 65495, + 120, + 65458, + 1, + 65494, + 68, + 26, + 65454, + 58, + 26, + 37, + 65416, + 59, + 26, + 36, + 65416, + 86, + 65451, + 0, + /* 3289 */ 65, + 65494, + 70, + 26, + 65453, + 59, + 26, + 36, + 65416, + 86, + 65451, + 0, + /* 3301 */ 65455, + 30, + 66, + 2, + 141, + 65458, + 1, + 65494, + 43, + 65494, + 68, + 26, + 38, + 65416, + 58, + 26, + 37, + 65416, + 59, + 26, + 65452, + 86, + 65451, + 0, + /* 3325 */ 65456, + 30, + 66, + 2, + 141, + 65458, + 1, + 65494, + 43, + 65494, + 68, + 26, + 38, + 65416, + 58, + 26, + 37, + 65416, + 59, + 26, + 65452, + 86, + 65451, + 0, + /* 3349 */ 65, + 65494, + 70, + 26, + 37, + 65416, + 59, + 26, + 65452, + 86, + 65451, + 0, + /* 3361 */ 65458, + 31, + 65, + 2, + 63, + 65496, + 120, + 65457, + 1, + 65495, + 67, + 26, + 65455, + 57, + 26, + 38, + 65416, + 58, + 26, + 37, + 65416, + 85, + 65452, + 0, + /* 3385 */ 65459, + 31, + 65, + 2, + 63, + 65496, + 120, + 65457, + 1, + 65495, + 67, + 26, + 65455, + 57, + 26, + 38, + 65416, + 58, + 26, + 37, + 65416, + 85, + 65452, + 0, + /* 3409 */ 65, + 65495, + 69, + 26, + 65454, + 58, + 26, + 37, + 65416, + 85, + 65452, + 0, + /* 3421 */ 65457, + 31, + 65, + 2, + 142, + 65457, + 1, + 65495, + 42, + 65495, + 67, + 26, + 39, + 65416, + 57, + 26, + 38, + 65416, + 58, + 26, + 65453, + 85, + 65452, + 0, + /* 3445 */ 65458, + 31, + 65, + 2, + 142, + 65457, + 1, + 65495, + 42, + 65495, + 67, + 26, + 39, + 65416, + 57, + 26, + 38, + 65416, + 58, + 26, + 65453, + 85, + 65452, + 0, + /* 3469 */ 65, + 65495, + 69, + 26, + 38, + 65416, + 58, + 26, + 65453, + 85, + 65452, + 0, + /* 3481 */ 65460, + 32, + 64, + 2, + 63, + 65497, + 120, + 65456, + 1, + 65496, + 66, + 26, + 65456, + 56, + 26, + 39, + 65416, + 57, + 26, + 38, + 65416, + 84, + 65453, + 0, + /* 3505 */ 65461, + 32, + 64, + 2, + 63, + 65497, + 120, + 65456, + 1, + 65496, + 66, + 26, + 65456, + 56, + 26, + 39, + 65416, + 57, + 26, + 38, + 65416, + 84, + 65453, + 0, + /* 3529 */ 65, + 65496, + 68, + 26, + 65455, + 57, + 26, + 38, + 65416, + 84, + 65453, + 0, + /* 3541 */ 65459, + 32, + 64, + 2, + 143, + 65456, + 1, + 65496, + 41, + 65496, + 66, + 26, + 40, + 65416, + 56, + 26, + 39, + 65416, + 57, + 26, + 65454, + 84, + 65453, + 0, + /* 3565 */ 65460, + 32, + 64, + 2, + 143, + 65456, + 1, + 65496, + 41, + 65496, + 66, + 26, + 40, + 65416, + 56, + 26, + 39, + 65416, + 57, + 26, + 65454, + 84, + 65453, + 0, + /* 3589 */ 65, + 65496, + 68, + 26, + 39, + 65416, + 57, + 26, + 65454, + 84, + 65453, + 0, + /* 3601 */ 65462, + 33, + 63, + 2, + 63, + 65498, + 120, + 65455, + 1, + 65497, + 65, + 26, + 65457, + 55, + 26, + 40, + 65416, + 56, + 26, + 39, + 65416, + 83, + 65454, + 0, + /* 3625 */ 65463, + 33, + 63, + 2, + 63, + 65498, + 120, + 65455, + 1, + 65497, + 65, + 26, + 65457, + 55, + 26, + 40, + 65416, + 56, + 26, + 39, + 65416, + 83, + 65454, + 0, + /* 3649 */ 65, + 65497, + 67, + 26, + 65456, + 56, + 26, + 39, + 65416, + 83, + 65454, + 0, + /* 3661 */ 65461, + 33, + 63, + 2, + 144, + 65455, + 1, + 65497, + 40, + 65497, + 65, + 26, + 41, + 65416, + 55, + 26, + 40, + 65416, + 56, + 26, + 65455, + 83, + 65454, + 0, + /* 3685 */ 65462, + 33, + 63, + 2, + 144, + 65455, + 1, + 65497, + 40, + 65497, + 65, + 26, + 41, + 65416, + 55, + 26, + 40, + 65416, + 56, + 26, + 65455, + 83, + 65454, + 0, + /* 3709 */ 65, + 65497, + 67, + 26, + 40, + 65416, + 56, + 26, + 65455, + 83, + 65454, + 0, + /* 3721 */ 65297, + 81, + 1, + 65455, + 0, + /* 3726 */ 65464, + 34, + 62, + 2, + 63, + 65499, + 120, + 65454, + 1, + 65498, + 64, + 2, + 26, + 41, + 65416, + 55, + 26, + 40, + 65416, + 82, + 65455, + 0, + /* 3748 */ 65465, + 34, + 62, + 2, + 63, + 65499, + 120, + 65454, + 1, + 65498, + 64, + 2, + 26, + 41, + 65416, + 55, + 26, + 40, + 65416, + 82, + 65455, + 0, + /* 3770 */ 65, + 65498, + 66, + 26, + 65457, + 55, + 26, + 40, + 65416, + 82, + 65455, + 0, + /* 3782 */ 65463, + 34, + 62, + 2, + 145, + 65454, + 1, + 65498, + 39, + 65498, + 64, + 26, + 42, + 65416, + 54, + 26, + 41, + 65416, + 55, + 26, + 65456, + 82, + 65455, + 0, + /* 3806 */ 65464, + 34, + 62, + 2, + 145, + 65454, + 1, + 65498, + 39, + 65498, + 64, + 26, + 42, + 65416, + 54, + 26, + 41, + 65416, + 55, + 26, + 65456, + 82, + 65455, + 0, + /* 3830 */ 65, + 65498, + 66, + 26, + 41, + 65416, + 55, + 26, + 65456, + 82, + 65455, + 0, + /* 3842 */ 65438, + 81, + 1, + 65456, + 0, + /* 3847 */ 65466, + 35, + 61, + 2, + 63, + 65500, + 120, + 65453, + 1, + 65499, + 65, + 2, + 26, + 40, + 1, + 65416, + 81, + 65456, + 0, + /* 3866 */ 65467, + 35, + 61, + 2, + 63, + 65500, + 120, + 65453, + 1, + 65499, + 65, + 2, + 26, + 40, + 1, + 65416, + 81, + 65456, + 0, + /* 3885 */ 65, + 65499, + 65, + 2, + 26, + 41, + 65416, + 81, + 65456, + 0, + /* 3895 */ 65465, + 35, + 61, + 2, + 146, + 65453, + 1, + 65499, + 38, + 65499, + 63, + 2, + 26, + 41, + 1, + 65416, + 54, + 26, + 65457, + 81, + 65456, + 0, + /* 3917 */ 65466, + 35, + 61, + 2, + 146, + 65453, + 1, + 65499, + 38, + 65499, + 63, + 2, + 26, + 41, + 1, + 65416, + 54, + 26, + 65457, + 81, + 65456, + 0, + /* 3939 */ 65, + 65499, + 65, + 26, + 42, + 65416, + 54, + 26, + 65457, + 81, + 65456, + 0, + /* 3951 */ 65438, + 80, + 1, + 65457, + 0, + /* 3956 */ 28, + 65457, + 0, + /* 3959 */ 65467, + 36, + 60, + 2, + 147, + 65452, + 1, + 65500, + 37, + 65500, + 64, + 2, + 26, + 41, + 65417, + 80, + 65457, + 0, + /* 3977 */ 65468, + 36, + 60, + 2, + 147, + 65452, + 1, + 65500, + 37, + 65500, + 64, + 2, + 26, + 41, + 65417, + 80, + 65457, + 0, + /* 3995 */ 65, + 65500, + 64, + 2, + 26, + 41, + 65417, + 80, + 65457, + 0, + /* 4005 */ 26, + 65458, + 80, + 65457, + 0, + /* 4010 */ 65469, + 37, + 61, + 65, + 65501, + 65, + 28, + 65458, + 0, + /* 4019 */ 65470, + 37, + 61, + 65, + 65501, + 65, + 28, + 65458, + 0, + /* 4028 */ 65373, + 1, + 1, + 230, + 65402, + 65461, + 0, + /* 4035 */ 65373, + 1, + 1, + 231, + 65401, + 65462, + 0, + /* 4042 */ 65373, + 1, + 1, + 232, + 65400, + 65463, + 0, + /* 4049 */ 65373, + 1, + 1, + 233, + 65399, + 65464, + 0, + /* 4056 */ 65373, + 1, + 1, + 234, + 65398, + 65465, + 0, + /* 4063 */ 65373, + 1, + 1, + 235, + 65397, + 65466, + 0, + /* 4070 */ 65373, + 1, + 1, + 236, + 65396, + 65467, + 0, + /* 4077 */ 65439, + 65467, + 0, + /* 4080 */ 65373, + 81, + 1, + 65455, + 1, + 237, + 65395, + 65468, + 0, + /* 4089 */ 65373, + 79, + 1, + 65457, + 80, + 1, + 65456, + 81, + 1, + 156, + 65394, + 65469, + 0, + /* 4102 */ 65373, + 77, + 1, + 65459, + 78, + 1, + 65458, + 79, + 1, + 159, + 65393, + 65470, + 0, + /* 4115 */ 65373, + 75, + 1, + 65461, + 76, + 1, + 65460, + 77, + 1, + 162, + 65392, + 65471, + 0, + /* 4128 */ 65373, + 73, + 1, + 65463, + 74, + 1, + 65462, + 75, + 1, + 165, + 65391, + 65472, + 0, + /* 4141 */ 65373, + 71, + 1, + 65465, + 72, + 1, + 65464, + 73, + 1, + 168, + 65390, + 65473, + 0, + /* 4154 */ 65373, + 69, + 1, + 65467, + 70, + 1, + 65466, + 71, + 1, + 171, + 65389, + 65474, + 0, + /* 4167 */ 65373, + 67, + 1, + 65469, + 68, + 1, + 65468, + 69, + 1, + 174, + 65388, + 65475, + 0, + /* 4180 */ 65534, + 0, + /* 4182 */ 65535, + 0, +}; + +static const uint16_t ARMSubRegIdxLists[] = { + /* 0 */ 1, + 2, + 0, + /* 3 */ 1, + 17, + 18, + 2, + 0, + /* 8 */ 1, + 3, + 0, + /* 11 */ 1, + 17, + 18, + 3, + 0, + /* 16 */ 9, + 10, + 0, + /* 19 */ 17, + 18, + 0, + /* 22 */ 1, + 17, + 18, + 2, + 19, + 20, + 0, + /* 29 */ 1, + 17, + 18, + 3, + 21, + 22, + 0, + /* 36 */ 1, + 2, + 3, + 13, + 33, + 37, + 0, + /* 43 */ 1, + 17, + 18, + 2, + 3, + 13, + 33, + 37, + 0, + /* 52 */ 1, + 17, + 18, + 2, + 19, + 20, + 3, + 13, + 33, + 37, + 0, + /* 63 */ 1, + 17, + 18, + 2, + 19, + 20, + 3, + 21, + 22, + 13, + 33, + 37, + 0, + /* 76 */ 13, + 1, + 2, + 14, + 3, + 4, + 33, + 34, + 35, + 36, + 37, + 0, + /* 88 */ 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 4, + 33, + 34, + 35, + 36, + 37, + 0, + /* 104 */ 1, + 2, + 3, + 4, + 13, + 14, + 33, + 34, + 35, + 36, + 37, + 0, + /* 116 */ 1, + 17, + 18, + 2, + 3, + 4, + 13, + 14, + 33, + 34, + 35, + 36, + 37, + 0, + /* 130 */ 1, + 17, + 18, + 2, + 19, + 20, + 3, + 21, + 22, + 4, + 13, + 14, + 33, + 34, + 35, + 36, + 37, + 0, + /* 148 */ 1, + 17, + 18, + 2, + 19, + 20, + 3, + 21, + 22, + 4, + 23, + 24, + 13, + 14, + 33, + 34, + 35, + 36, + 37, + 0, + /* 168 */ 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 21, + 22, + 4, + 23, + 24, + 33, + 34, + 35, + 36, + 37, + 0, + /* 188 */ 1, + 3, + 5, + 33, + 43, + 0, + /* 194 */ 1, + 17, + 18, + 3, + 5, + 33, + 43, + 0, + /* 202 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 33, + 43, + 0, + /* 212 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 25, + 26, + 33, + 43, + 0, + /* 224 */ 1, + 3, + 5, + 7, + 33, + 38, + 43, + 45, + 51, + 0, + /* 234 */ 1, + 17, + 18, + 3, + 5, + 7, + 33, + 38, + 43, + 45, + 51, + 0, + /* 246 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 7, + 33, + 38, + 43, + 45, + 51, + 0, + /* 260 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 25, + 26, + 7, + 33, + 38, + 43, + 45, + 51, + 0, + /* 276 */ 1, + 17, + 18, + 3, + 21, + 22, + 5, + 25, + 26, + 7, + 29, + 30, + 33, + 38, + 43, + 45, + 51, + 0, + /* 294 */ 11, + 13, + 1, + 2, + 14, + 3, + 4, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 6, + 16, + 7, + 8, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, + /* 333 */ 11, + 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 4, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 6, + 16, + 7, + 8, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, + /* 376 */ 11, + 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 21, + 22, + 4, + 23, + 24, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 6, + 16, + 7, + 8, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, + /* 423 */ 11, + 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 21, + 22, + 4, + 23, + 24, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 25, + 26, + 6, + 27, + 28, + 16, + 7, + 8, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, + /* 474 */ 11, + 13, + 1, + 17, + 18, + 2, + 19, + 20, + 14, + 3, + 21, + 22, + 4, + 23, + 24, + 33, + 34, + 35, + 36, + 37, + 12, + 15, + 5, + 25, + 26, + 6, + 27, + 28, + 16, + 7, + 29, + 30, + 8, + 31, + 32, + 51, + 52, + 53, + 54, + 55, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 56, + 0, +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char ARMRegStrings[] = { + /* 0 */ "D4_D6_D8_D10\0" + /* 13 */ "D7_D8_D9_D10\0" + /* 26 */ "Q7_Q8_Q9_Q10\0" + /* 39 */ "R10\0" + /* 43 */ "S10\0" + /* 47 */ "D14_D16_D18_D20\0" + /* 63 */ "D17_D18_D19_D20\0" + /* 79 */ "S20\0" + /* 83 */ "D24_D26_D28_D30\0" + /* 99 */ "D27_D28_D29_D30\0" + /* 115 */ "S30\0" + /* 119 */ "D0\0" + /* 122 */ "P0\0" + /* 125 */ "Q0\0" + /* 128 */ "MVFR0\0" + /* 134 */ "S0\0" + /* 137 */ "D9_D10_D11\0" + /* 148 */ "D5_D7_D9_D11\0" + /* 161 */ "Q8_Q9_Q10_Q11\0" + /* 175 */ "R10_R11\0" + /* 183 */ "S11\0" + /* 187 */ "D19_D20_D21\0" + /* 199 */ "D15_D17_D19_D21\0" + /* 215 */ "S21\0" + /* 219 */ "D29_D30_D31\0" + /* 231 */ "D25_D27_D29_D31\0" + /* 247 */ "S31\0" + /* 251 */ "D1\0" + /* 254 */ "Q0_Q1\0" + /* 260 */ "MVFR1\0" + /* 266 */ "R0_R1\0" + /* 272 */ "S1\0" + /* 275 */ "D6_D8_D10_D12\0" + /* 289 */ "D9_D10_D11_D12\0" + /* 304 */ "Q9_Q10_Q11_Q12\0" + /* 319 */ "R12\0" + /* 323 */ "S12\0" + /* 327 */ "D16_D18_D20_D22\0" + /* 343 */ "D19_D20_D21_D22\0" + /* 359 */ "S22\0" + /* 363 */ "D0_D2\0" + /* 369 */ "D0_D1_D2\0" + /* 378 */ "Q1_Q2\0" + /* 384 */ "MVFR2\0" + /* 390 */ "S2\0" + /* 393 */ "FPINST2\0" + /* 401 */ "D7_D9_D11_D13\0" + /* 415 */ "D11_D12_D13\0" + /* 427 */ "Q10_Q11_Q12_Q13\0" + /* 443 */ "S13\0" + /* 447 */ "D17_D19_D21_D23\0" + /* 463 */ "D21_D22_D23\0" + /* 475 */ "S23\0" + /* 479 */ "D1_D3\0" + /* 485 */ "D1_D2_D3\0" + /* 494 */ "Q0_Q1_Q2_Q3\0" + /* 506 */ "R2_R3\0" + /* 512 */ "S3\0" + /* 515 */ "D8_D10_D12_D14\0" + /* 530 */ "D11_D12_D13_D14\0" + /* 546 */ "Q11_Q12_Q13_Q14\0" + /* 562 */ "S14\0" + /* 566 */ "D18_D20_D22_D24\0" + /* 582 */ "D21_D22_D23_D24\0" + /* 598 */ "S24\0" + /* 602 */ "D0_D2_D4\0" + /* 611 */ "D1_D2_D3_D4\0" + /* 623 */ "Q1_Q2_Q3_Q4\0" + /* 635 */ "R4\0" + /* 638 */ "S4\0" + /* 641 */ "D9_D11_D13_D15\0" + /* 656 */ "D13_D14_D15\0" + /* 668 */ "Q12_Q13_Q14_Q15\0" + /* 684 */ "S15\0" + /* 688 */ "D19_D21_D23_D25\0" + /* 704 */ "D23_D24_D25\0" + /* 716 */ "S25\0" + /* 720 */ "D1_D3_D5\0" + /* 729 */ "D3_D4_D5\0" + /* 738 */ "Q2_Q3_Q4_Q5\0" + /* 750 */ "R4_R5\0" + /* 756 */ "S5\0" + /* 759 */ "D10_D12_D14_D16\0" + /* 775 */ "D13_D14_D15_D16\0" + /* 791 */ "S16\0" + /* 795 */ "D20_D22_D24_D26\0" + /* 811 */ "D23_D24_D25_D26\0" + /* 827 */ "S26\0" + /* 831 */ "D0_D2_D4_D6\0" + /* 843 */ "D3_D4_D5_D6\0" + /* 855 */ "Q3_Q4_Q5_Q6\0" + /* 867 */ "R6\0" + /* 870 */ "S6\0" + /* 873 */ "D11_D13_D15_D17\0" + /* 889 */ "D15_D16_D17\0" + /* 901 */ "S17\0" + /* 905 */ "D21_D23_D25_D27\0" + /* 921 */ "D25_D26_D27\0" + /* 933 */ "S27\0" + /* 937 */ "D1_D3_D5_D7\0" + /* 949 */ "D5_D6_D7\0" + /* 958 */ "Q4_Q5_Q6_Q7\0" + /* 970 */ "R6_R7\0" + /* 976 */ "S7\0" + /* 979 */ "D12_D14_D16_D18\0" + /* 995 */ "D15_D16_D17_D18\0" + /* 1011 */ "S18\0" + /* 1015 */ "D22_D24_D26_D28\0" + /* 1031 */ "D25_D26_D27_D28\0" + /* 1047 */ "S28\0" + /* 1051 */ "D2_D4_D6_D8\0" + /* 1063 */ "D5_D6_D7_D8\0" + /* 1075 */ "Q5_Q6_Q7_Q8\0" + /* 1087 */ "R8\0" + /* 1090 */ "S8\0" + /* 1093 */ "D13_D15_D17_D19\0" + /* 1109 */ "D17_D18_D19\0" + /* 1121 */ "S19\0" + /* 1125 */ "D23_D25_D27_D29\0" + /* 1141 */ "D27_D28_D29\0" + /* 1153 */ "S29\0" + /* 1157 */ "D3_D5_D7_D9\0" + /* 1169 */ "D7_D8_D9\0" + /* 1178 */ "Q6_Q7_Q8_Q9\0" + /* 1190 */ "R8_R9\0" + /* 1196 */ "S9\0" + /* 1199 */ "PC\0" + /* 1202 */ "FPSCR_NZCVQC\0" + /* 1215 */ "FPEXC\0" + /* 1221 */ "FPSID\0" + /* 1227 */ "ITSTATE\0" + /* 1235 */ "R12_SP\0" + /* 1242 */ "FPSCR\0" + /* 1248 */ "LR\0" + /* 1251 */ "VPR\0" + /* 1255 */ "APSR\0" + /* 1260 */ "CPSR\0" + /* 1265 */ "SPSR\0" + /* 1270 */ "ZR\0" + /* 1273 */ "FPCXTNS\0" + /* 1281 */ "FPCXTS\0" + /* 1288 */ "FPINST\0" + /* 1295 */ "FPSCR_NZCV\0" + /* 1306 */ "APSR_NZCV\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterDesc ARMRegDesc[] = { + // Descriptors + {12, 0, 0, 0, 0, 0}, + {1255, 16, 16, 2, 66913, 1216}, + {1306, 16, 16, 2, 66913, 967}, + {1260, 16, 16, 2, 66913, 587}, + {1273, 16, 16, 2, 66913, 585}, + {1281, 16, 16, 2, 66913, 378}, + {1215, 16, 16, 2, 66913, 2}, + {1288, 16, 16, 2, 66913, 835}, + {1242, 16, 16, 2, 17664, 428}, + {1295, 16, 16, 2, 17664, 518}, + {1202, 16, 16, 2, 66881, 328}, + {1221, 16, 16, 2, 66881, 573}, + {1227, 16, 16, 2, 66881, 2}, + {1248, 16, 16, 2, 66881, 1218}, + {1199, 16, 16, 2, 66881, 822}, + {1239, 16, 1524, 2, 66881, 516}, + {1265, 16, 16, 2, 66881, 557}, + {1251, 16, 16, 2, 66881, 837}, + {1270, 16, 16, 2, 66881, 568}, + {119, 350, 4011, 19, 13250, 488}, + {251, 357, 2477, 19, 13250, 485}, + {366, 364, 3960, 19, 13250, 157}, + {482, 378, 3848, 19, 13250, 396}, + {608, 392, 3896, 19, 13250, 627}, + {726, 406, 3727, 19, 13250, 952}, + {840, 420, 3783, 19, 13250, 955}, + {946, 434, 3602, 19, 13250, 606}, + {1060, 448, 3662, 19, 13250, 824}, + {1166, 462, 3482, 19, 13250, 886}, + {9, 476, 3542, 19, 13250, 1220}, + {144, 490, 3362, 19, 13250, 1223}, + {285, 504, 3422, 19, 13250, 1208}, + {411, 518, 3242, 19, 13250, 589}, + {526, 532, 3302, 19, 13250, 552}, + {652, 546, 3147, 19, 13250, 1201}, + {771, 16, 3206, 2, 17761, 575}, + {885, 16, 3076, 2, 17761, 369}, + {991, 16, 3111, 2, 17761, 1157}, + {1105, 16, 3006, 2, 17761, 428}, + {59, 16, 3041, 2, 17761, 714}, + {195, 16, 2936, 2, 17761, 428}, + {339, 16, 2971, 2, 17761, 428}, + {459, 16, 2866, 2, 17761, 514}, + {578, 16, 2901, 2, 17761, 428}, + {700, 16, 2795, 2, 17761, 428}, + {807, 16, 2835, 2, 17761, 428}, + {917, 16, 2361, 2, 17761, 428}, + {1027, 16, 2409, 2, 17761, 937}, + {1137, 16, 2382, 2, 17761, 939}, + {95, 16, 2427, 2, 17761, 1150}, + {227, 16, 2787, 2, 17761, 2}, + {393, 16, 16, 2, 17761, 428}, + {128, 16, 16, 2, 17761, 960}, + {260, 16, 16, 2, 17761, 932}, + {384, 16, 16, 2, 17761, 716}, + {122, 16, 16, 2, 17761, 880}, + {125, 353, 1112, 22, 2196, 39}, + {257, 374, 775, 22, 2196, 434}, + {381, 402, 314, 22, 2196, 1152}, + {503, 430, 244, 22, 2196, 251}, + {632, 458, 234, 22, 2196, 301}, + {747, 486, 224, 22, 2196, 947}, + {864, 514, 214, 22, 2196, 287}, + {967, 542, 204, 22, 2196, 827}, + {1084, 804, 194, 0, 12818, 976}, + {1187, 807, 184, 0, 12818, 934}, + {35, 810, 174, 0, 12818, 501}, + {171, 813, 164, 0, 12818, 127}, + {315, 816, 154, 0, 12818, 875}, + {439, 819, 591, 0, 12818, 449}, + {558, 822, 2445, 0, 12818, 832}, + {680, 825, 1106, 0, 12818, 315}, + {131, 16, 1371, 2, 66881, 1006}, + {263, 16, 1369, 2, 66881, 143}, + {387, 16, 1369, 2, 66881, 215}, + {509, 16, 1367, 2, 66881, 2}, + {635, 16, 1367, 2, 66881, 958}, + {753, 16, 1365, 2, 66881, 428}, + {867, 16, 1365, 2, 66881, 2}, + {973, 16, 1363, 2, 66881, 199}, + {1087, 16, 1363, 2, 66881, 855}, + {1193, 16, 1361, 2, 66881, 1021}, + {39, 16, 1361, 2, 66881, 979}, + {179, 16, 1359, 2, 66881, 943}, + {319, 16, 1359, 2, 66881, 428}, + {134, 16, 4019, 2, 65393, 271}, + {272, 16, 4010, 2, 65393, 326}, + {390, 16, 2488, 2, 65393, 2}, + {512, 16, 2476, 2, 65393, 945}, + {638, 16, 3977, 2, 65393, 941}, + {756, 16, 3959, 2, 65393, 2}, + {870, 16, 3866, 2, 65393, 197}, + {976, 16, 3847, 2, 65393, 864}, + {1090, 16, 3917, 2, 65393, 2}, + {1196, 16, 3895, 2, 65393, 866}, + {43, 16, 3748, 2, 65393, 1017}, + {183, 16, 3726, 2, 65393, 1008}, + {323, 16, 3806, 2, 65393, 1023}, + {443, 16, 3782, 2, 65393, 1025}, + {562, 16, 3625, 2, 65393, 613}, + {684, 16, 3601, 2, 65393, 617}, + {791, 16, 3685, 2, 65393, 615}, + {901, 16, 3661, 2, 65393, 514}, + {1011, 16, 3505, 2, 65393, 378}, + {1121, 16, 3481, 2, 65393, 428}, + {79, 16, 3565, 2, 65393, 428}, + {215, 16, 3541, 2, 65393, 555}, + {359, 16, 3385, 2, 65393, 999}, + {475, 16, 3361, 2, 65393, 878}, + {598, 16, 3445, 2, 65393, 1015}, + {716, 16, 3421, 2, 65393, 1019}, + {827, 16, 3265, 2, 65393, 271}, + {933, 16, 3241, 2, 65393, 862}, + {1047, 16, 3325, 2, 65393, 981}, + {1153, 16, 3301, 2, 65393, 428}, + {115, 16, 3170, 2, 65393, 2}, + {247, 16, 3146, 2, 65393, 969}, + {363, 367, 4013, 29, 5426, 98}, + {479, 381, 2500, 29, 5426, 282}, + {605, 395, 3995, 29, 5426, 962}, + {723, 409, 3885, 29, 5426, 989}, + {837, 423, 3939, 29, 5426, 994}, + {943, 437, 3770, 29, 5426, 857}, + {1057, 451, 3830, 29, 5426, 1010}, + {1163, 465, 3649, 29, 5426, 1001}, + {6, 479, 3709, 29, 5426, 520}, + {154, 493, 3529, 29, 5426, 563}, + {281, 507, 3589, 29, 5426, 509}, + {407, 521, 3409, 29, 5426, 538}, + {522, 535, 3469, 29, 5426, 504}, + {648, 549, 3289, 29, 5426, 525}, + {767, 3951, 3349, 11, 17602, 322}, + {881, 3842, 3194, 11, 13522, 0}, + {987, 1080, 3229, 8, 17329, 842}, + {1101, 1080, 3099, 8, 17329, 839}, + {55, 1080, 3134, 8, 17329, 986}, + {207, 1080, 3029, 8, 17329, 570}, + {335, 1080, 3064, 8, 17329, 983}, + {455, 1080, 2959, 8, 17329, 1}, + {574, 1080, 2994, 8, 17329, 449}, + {696, 1080, 2889, 8, 17329, 427}, + {803, 1080, 2924, 8, 17329, 449}, + {913, 1080, 2818, 8, 17329, 852}, + {1023, 1080, 2856, 8, 17329, 819}, + {1133, 1080, 2399, 8, 17329, 224}, + {91, 1080, 2438, 8, 17329, 103}, + {239, 1080, 2789, 8, 17329, 154}, + {254, 1339, 1114, 168, 1044, 1100}, + {378, 1319, 347, 168, 1044, 80}, + {500, 1299, 142, 168, 1044, 1127}, + {629, 1279, 142, 168, 1044, 89}, + {744, 1259, 142, 168, 1044, 1118}, + {861, 1239, 142, 168, 1044, 1109}, + {964, 1219, 142, 168, 1044, 1136}, + {1081, 1203, 142, 88, 1456, 138}, + {1184, 1191, 142, 76, 2114, 635}, + {32, 1179, 142, 76, 2114, 630}, + {167, 1167, 142, 76, 2114, 971}, + {311, 1155, 142, 76, 2114, 601}, + {435, 1143, 142, 76, 2114, 22}, + {554, 1131, 344, 76, 2114, 1145}, + {676, 1119, 1108, 76, 2114, 1183}, + {494, 2154, 16, 474, 4, 640}, + {623, 2099, 16, 474, 4, 44}, + {738, 2044, 16, 474, 4, 674}, + {855, 1989, 16, 474, 4, 657}, + {958, 1934, 16, 474, 4, 227}, + {1075, 1883, 16, 423, 272, 691}, + {1178, 1836, 16, 376, 512, 461}, + {26, 1793, 16, 333, 720, 474}, + {161, 1754, 16, 294, 1186, 262}, + {304, 1715, 16, 294, 1186, 414}, + {427, 1676, 16, 294, 1186, 1159}, + {546, 1637, 16, 294, 1186, 443}, + {668, 1598, 16, 294, 1186, 387}, + {266, 783, 16, 16, 8946, 224}, + {506, 786, 16, 16, 8946, 491}, + {750, 789, 16, 16, 8946, 449}, + {970, 792, 16, 16, 8946, 377}, + {1190, 795, 16, 16, 8946, 347}, + {175, 798, 16, 16, 8946, 1}, + {1235, 4077, 16, 16, 17856, 160}, + {369, 1511, 1113, 63, 1570, 330}, + {485, 4167, 2509, 63, 1570, 897}, + {614, 1498, 778, 63, 1570, 904}, + {729, 4154, 770, 63, 1570, 244}, + {846, 1485, 317, 63, 1570, 404}, + {949, 4141, 660, 63, 1570, 380}, + {1066, 1472, 308, 63, 1570, 201}, + {1169, 4128, 654, 63, 1570, 350}, + {16, 1459, 302, 63, 1570, 66}, + {137, 4115, 648, 63, 1570, 373}, + {292, 1446, 296, 63, 1570, 911}, + {415, 4102, 642, 63, 1570, 925}, + {534, 1433, 290, 63, 1570, 494}, + {656, 4089, 636, 63, 1570, 918}, + {779, 1422, 284, 52, 1680, 163}, + {889, 4080, 630, 43, 1872, 1211}, + {999, 1415, 278, 36, 2401, 609}, + {1109, 4070, 624, 36, 2401, 1226}, + {67, 1408, 272, 36, 2401, 706}, + {187, 4063, 618, 36, 2401, 619}, + {347, 1401, 266, 36, 2401, 623}, + {463, 4056, 612, 36, 2401, 1034}, + {586, 1394, 260, 36, 2401, 297}, + {704, 4049, 606, 36, 2401, 882}, + {815, 1387, 254, 36, 2401, 577}, + {921, 4042, 600, 36, 2401, 559}, + {1035, 1380, 765, 36, 2401, 439}, + {1141, 4035, 2453, 36, 2401, 186}, + {103, 1373, 2472, 36, 2401, 581}, + {219, 4028, 1107, 36, 2401, 710}, + {602, 1026, 4016, 212, 5314, 120}, + {720, 1014, 3956, 212, 5314, 1047}, + {834, 1002, 4005, 212, 5314, 337}, + {940, 990, 3912, 212, 5314, 868}, + {1054, 978, 3912, 212, 5314, 845}, + {1160, 966, 3801, 212, 5314, 1027}, + {3, 954, 3801, 212, 5314, 73}, + {151, 942, 3680, 212, 5314, 1067}, + {278, 930, 3680, 212, 5314, 1194}, + {404, 918, 3560, 212, 5314, 190}, + {518, 906, 3560, 212, 5314, 1054}, + {644, 894, 3440, 212, 5314, 208}, + {763, 1070, 3440, 202, 17506, 1188}, + {877, 1060, 3320, 202, 13426, 1061}, + {983, 1052, 3320, 194, 14226, 217}, + {1097, 1044, 3224, 194, 13698, 1074}, + {51, 1038, 3224, 188, 14049, 423}, + {203, 1038, 3129, 188, 14049, 1096}, + {331, 1038, 3129, 188, 14049, 130}, + {451, 1038, 3059, 188, 14049, 1204}, + {570, 1038, 3059, 188, 14049, 182}, + {692, 1038, 2989, 188, 14049, 1079}, + {799, 1038, 2989, 188, 14049, 169}, + {909, 1038, 2919, 188, 14049, 430}, + {1019, 1038, 2919, 188, 14049, 4}, + {1129, 1038, 2830, 188, 14049, 178}, + {87, 1038, 2853, 188, 14049, 1083}, + {235, 1038, 2792, 188, 14049, 134}, + {831, 2675, 4017, 276, 5170, 1087}, + {937, 2657, 3954, 276, 5170, 1038}, + {1051, 2639, 3954, 276, 5170, 718}, + {1157, 2621, 3845, 276, 5170, 810}, + {0, 2603, 3845, 276, 5170, 733}, + {148, 2585, 3724, 276, 5170, 543}, + {275, 2567, 3724, 276, 5170, 592}, + {401, 2549, 3623, 276, 5170, 306}, + {515, 2531, 3623, 276, 5170, 742}, + {641, 2513, 3503, 276, 5170, 452}, + {759, 2771, 3503, 260, 17378, 530}, + {873, 2755, 3383, 260, 13298, 751}, + {979, 2741, 3383, 246, 14114, 27}, + {1093, 2727, 3263, 246, 13586, 759}, + {47, 2715, 3263, 234, 13954, 256}, + {199, 2703, 3168, 234, 13778, 727}, + {327, 2693, 3168, 224, 13873, 766}, + {447, 2693, 3097, 224, 13873, 399}, + {566, 2693, 3097, 224, 13873, 106}, + {688, 2693, 3027, 224, 13873, 8}, + {795, 2693, 3027, 224, 13873, 771}, + {905, 2693, 2957, 224, 13873, 776}, + {1015, 2693, 2957, 224, 13873, 1173}, + {1125, 2693, 2854, 224, 13873, 781}, + {83, 2693, 2854, 224, 13873, 1168}, + {231, 2693, 2793, 224, 13873, 786}, + {372, 360, 2507, 22, 1956, 456}, + {617, 388, 583, 22, 1956, 173}, + {849, 416, 756, 22, 1956, 173}, + {1069, 444, 747, 22, 1956, 222}, + {19, 472, 738, 22, 1956, 791}, + {296, 500, 729, 22, 1956, 217}, + {538, 528, 720, 22, 1956, 34}, + {783, 3721, 711, 3, 2336, 318}, + {1003, 562, 702, 0, 8898, 219}, + {71, 565, 693, 0, 8898, 205}, + {351, 568, 684, 0, 8898, 344}, + {590, 571, 675, 0, 8898, 1}, + {819, 574, 666, 0, 8898, 796}, + {1039, 577, 2458, 0, 8898, 411}, + {107, 580, 2466, 0, 8898, 1}, + {611, 2341, 2486, 148, 900, 273}, + {843, 2321, 588, 148, 900, 362}, + {1063, 2301, 588, 148, 900, 111}, + {13, 2281, 588, 148, 900, 13}, + {289, 2261, 588, 148, 900, 145}, + {530, 2241, 588, 148, 900, 371}, + {775, 2223, 588, 130, 1328, 889}, + {995, 2209, 588, 116, 1776, 799}, + {63, 1586, 588, 104, 2034, 292}, + {343, 1574, 588, 104, 2034, 805}, + {582, 1562, 588, 104, 2034, 8}, + {811, 1550, 588, 104, 2034, 61}, + {1031, 1538, 588, 104, 2034, 357}, + {99, 1526, 2380, 104, 2034, 1178}, +}; + +// HPR Register Class... +static const MCPhysReg HPR[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, + ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, + ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, +}; + +// HPR Bit set. +static const uint8_t HPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, +}; + +// FPWithVPR Register Class... +static const MCPhysReg FPWithVPR[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, + ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, + ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, + ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, + ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, + ARM_VPR, +}; + +// FPWithVPR Bit set. +static const uint8_t FPWithVPRBits[] = { + 0x00, 0x00, 0xfa, 0xff, 0xff, 0xff, 0x07, 0x00, + 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, +}; + +// SPR Register Class... +static const MCPhysReg SPR[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, + ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, + ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, +}; + +// SPR Bit set. +static const uint8_t SPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, +}; + +// FPWithVPR_with_ssub_0 Register Class... +static const MCPhysReg FPWithVPR_with_ssub_0[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, +}; + +// FPWithVPR_with_ssub_0 Bit set. +static const uint8_t FPWithVPR_with_ssub_0Bits[] = { + 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// GPR Register Class... +static const MCPhysReg GPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, +}; + +// GPR Bit set. +static const uint8_t GPRBits[] = { + 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, +}; + +// GPRwithAPSR Register Class... +static const MCPhysReg GPRwithAPSR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV, +}; + +// GPRwithAPSR Bit set. +static const uint8_t GPRwithAPSRBits[] = { + 0x04, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, +}; + +// GPRwithZR Register Class... +static const MCPhysReg GPRwithZR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_ZR, +}; + +// GPRwithZR Bit set. +static const uint8_t GPRwithZRBits[] = { + 0x00, 0xa0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, +}; + +// SPR_8 Register Class... +static const MCPhysReg SPR_8[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, +}; + +// SPR_8 Bit set. +static const uint8_t SPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, +}; + +// GPRnopc Register Class... +static const MCPhysReg GPRnopc[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, +}; + +// GPRnopc Bit set. +static const uint8_t GPRnopcBits[] = { + 0x00, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, +}; + +// GPRwithAPSR_NZCVnosp Register Class... +static const MCPhysReg GPRwithAPSR_NZCVnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_APSR_NZCV, +}; + +// GPRwithAPSR_NZCVnosp Bit set. +static const uint8_t GPRwithAPSR_NZCVnospBits[] = { + 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, +}; + +// GPRwithAPSRnosp Register Class... +static const MCPhysReg GPRwithAPSRnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_APSR, +}; + +// GPRwithAPSRnosp Bit set. +static const uint8_t GPRwithAPSRnospBits[] = { + 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, +}; + +// GPRwithZRnosp Register Class... +static const MCPhysReg GPRwithZRnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_ZR, +}; + +// GPRwithZRnosp Bit set. +static const uint8_t GPRwithZRnospBits[] = { + 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, +}; + +// GPRnoip Register Class... +static const MCPhysReg GPRnoip[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, + ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, ARM_PC, +}; + +// GPRnoip Bit set. +static const uint8_t GPRnoipBits[] = { + 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0f, +}; + +// rGPR Register Class... +static const MCPhysReg rGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, + ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, +}; + +// rGPR Bit set. +static const uint8_t rGPRBits[] = { + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, +}; + +// GPRnoip_and_GPRnopc Register Class... +static const MCPhysReg GPRnoip_and_GPRnopc[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, + ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, +}; + +// GPRnoip_and_GPRnopc Bit set. +static const uint8_t GPRnoip_and_GPRnopcBits[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0f, +}; + +// GPRnoip_and_GPRwithAPSR_NZCVnosp Register Class... +static const MCPhysReg GPRnoip_and_GPRwithAPSR_NZCVnosp[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, + ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, +}; + +// GPRnoip_and_GPRwithAPSR_NZCVnosp Bit set. +static const uint8_t GPRnoip_and_GPRwithAPSR_NZCVnospBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0f, +}; + +// tGPRwithpc Register Class... +static const MCPhysReg tGPRwithpc[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_PC, +}; + +// tGPRwithpc Bit set. +static const uint8_t tGPRwithpcBits[] = { + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, +}; + +// FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Register Class... +static const MCPhysReg FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, +}; + +// FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Bit set. +static const uint8_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits[] = { + 0x00, + 0x00, + 0xf8, + 0x07, +}; + +// hGPR Register Class... +static const MCPhysReg hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, +}; + +// hGPR Bit set. +static const uint8_t hGPRBits[] = { + 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, +}; + +// tGPR Register Class... +static const MCPhysReg tGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, +}; + +// tGPR Bit set. +static const uint8_t tGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, +}; + +// tGPREven Register Class... +static const MCPhysReg tGPREven[] = { + ARM_R0, ARM_R2, ARM_R4, ARM_R6, ARM_R8, ARM_R10, ARM_R12, ARM_LR, +}; + +// tGPREven Bit set. +static const uint8_t tGPREvenBits[] = { + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, +}; + +// GPRnopc_and_hGPR Register Class... +static const MCPhysReg GPRnopc_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, +}; + +// GPRnopc_and_hGPR Bit set. +static const uint8_t GPRnopc_and_hGPRBits[] = { + 0x00, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, +}; + +// GPRnoip_and_hGPR Register Class... +static const MCPhysReg GPRnoip_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, ARM_PC, +}; + +// GPRnoip_and_hGPR Bit set. +static const uint8_t GPRnoip_and_hGPRBits[] = { + 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, +}; + +// GPRnoip_and_tGPREven Register Class... +static const MCPhysReg GPRnoip_and_tGPREven[] = { + ARM_R0, ARM_R2, ARM_R4, ARM_R6, ARM_R8, ARM_R10, +}; + +// GPRnoip_and_tGPREven Bit set. +static const uint8_t GPRnoip_and_tGPREvenBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x05, +}; + +// GPRwithAPSR_NZCVnosp_and_hGPR Register Class... +static const MCPhysReg GPRwithAPSR_NZCVnosp_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, +}; + +// GPRwithAPSR_NZCVnosp_and_hGPR Bit set. +static const uint8_t GPRwithAPSR_NZCVnosp_and_hGPRBits[] = { + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, +}; + +// tGPROdd Register Class... +static const MCPhysReg tGPROdd[] = { + ARM_R1, ARM_R3, ARM_R5, ARM_R7, ARM_R9, ARM_R11, +}; + +// tGPROdd Bit set. +static const uint8_t tGPROddBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x0a, +}; + +// GPRnopc_and_GPRnoip_and_hGPR Register Class... +static const MCPhysReg GPRnopc_and_GPRnoip_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, +}; + +// GPRnopc_and_GPRnoip_and_hGPR Bit set. +static const uint8_t GPRnopc_and_GPRnoip_and_hGPRBits[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, +}; + +// tcGPR Register Class... +static const MCPhysReg tcGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12, +}; + +// tcGPR Bit set. +static const uint8_t tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x10, +}; + +// GPRnoip_and_tcGPR Register Class... +static const MCPhysReg GPRnoip_and_tcGPR[] = { + ARM_R0, + ARM_R1, + ARM_R2, + ARM_R3, +}; + +// GPRnoip_and_tcGPR Bit set. +static const uint8_t GPRnoip_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, +}; + +// GPRwithAPSR_NZCVnosp_and_GPRnoip_and_hGPR Register Class... +static const MCPhysReg GPRwithAPSR_NZCVnosp_and_GPRnoip_and_hGPR[] = { + ARM_R8, + ARM_R9, + ARM_R10, + ARM_R11, +}; + +// GPRwithAPSR_NZCVnosp_and_GPRnoip_and_hGPR Bit set. +static const uint8_t GPRwithAPSR_NZCVnosp_and_GPRnoip_and_hGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, +}; + +// hGPR_and_tGPREven Register Class... +static const MCPhysReg hGPR_and_tGPREven[] = { + ARM_R8, + ARM_R10, + ARM_R12, + ARM_LR, +}; + +// hGPR_and_tGPREven Bit set. +static const uint8_t hGPR_and_tGPREvenBits[] = { + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, +}; + +// tGPR_and_tGPREven Register Class... +static const MCPhysReg tGPR_and_tGPREven[] = { + ARM_R0, + ARM_R2, + ARM_R4, + ARM_R6, +}; + +// tGPR_and_tGPREven Bit set. +static const uint8_t tGPR_and_tGPREvenBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, +}; + +// tGPR_and_tGPROdd Register Class... +static const MCPhysReg tGPR_and_tGPROdd[] = { + ARM_R1, + ARM_R3, + ARM_R5, + ARM_R7, +}; + +// tGPR_and_tGPROdd Bit set. +static const uint8_t tGPR_and_tGPROddBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, +}; + +// tGPREven_and_tcGPR Register Class... +static const MCPhysReg tGPREven_and_tcGPR[] = { + ARM_R0, + ARM_R2, + ARM_R12, +}; + +// tGPREven_and_tcGPR Bit set. +static const uint8_t tGPREven_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x10, +}; + +// hGPR_and_GPRnoip_and_tGPREven Register Class... +static const MCPhysReg hGPR_and_GPRnoip_and_tGPREven[] = { + ARM_R8, + ARM_R10, +}; + +// hGPR_and_GPRnoip_and_tGPREven Bit set. +static const uint8_t hGPR_and_GPRnoip_and_tGPREvenBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, +}; + +// hGPR_and_tGPROdd Register Class... +static const MCPhysReg hGPR_and_tGPROdd[] = { + ARM_R9, + ARM_R11, +}; + +// hGPR_and_tGPROdd Bit set. +static const uint8_t hGPR_and_tGPROddBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, +}; + +// tGPREven_and_GPRnoip_and_tcGPR Register Class... +static const MCPhysReg tGPREven_and_GPRnoip_and_tcGPR[] = { + ARM_R0, + ARM_R2, +}; + +// tGPREven_and_GPRnoip_and_tcGPR Bit set. +static const uint8_t tGPREven_and_GPRnoip_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, +}; + +// tGPROdd_and_tcGPR Register Class... +static const MCPhysReg tGPROdd_and_tcGPR[] = { + ARM_R1, + ARM_R3, +}; + +// tGPROdd_and_tcGPR Bit set. +static const uint8_t tGPROdd_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, +}; + +// CCR Register Class... +static const MCPhysReg CCR[] = { + ARM_CPSR, +}; + +// CCR Bit set. +static const uint8_t CCRBits[] = { + 0x08, +}; + +// FPCXTRegs Register Class... +static const MCPhysReg FPCXTRegs[] = { + ARM_FPCXTNS, +}; + +// FPCXTRegs Bit set. +static const uint8_t FPCXTRegsBits[] = { + 0x10, +}; + +// GPRlr Register Class... +static const MCPhysReg GPRlr[] = { + ARM_LR, +}; + +// GPRlr Bit set. +static const uint8_t GPRlrBits[] = { + 0x00, + 0x20, +}; + +// GPRsp Register Class... +static const MCPhysReg GPRsp[] = { + ARM_SP, +}; + +// GPRsp Bit set. +static const uint8_t GPRspBits[] = { + 0x00, + 0x80, +}; + +// VCCR Register Class... +static const MCPhysReg VCCR[] = { + ARM_VPR, +}; + +// VCCR Bit set. +static const uint8_t VCCRBits[] = { + 0x00, + 0x00, + 0x02, +}; + +// cl_FPSCR_NZCV Register Class... +static const MCPhysReg cl_FPSCR_NZCV[] = { + ARM_FPSCR_NZCV, +}; + +// cl_FPSCR_NZCV Bit set. +static const uint8_t cl_FPSCR_NZCVBits[] = { + 0x00, + 0x02, +}; + +// hGPR_and_tGPRwithpc Register Class... +static const MCPhysReg hGPR_and_tGPRwithpc[] = { + ARM_PC, +}; + +// hGPR_and_tGPRwithpc Bit set. +static const uint8_t hGPR_and_tGPRwithpcBits[] = { + 0x00, + 0x40, +}; + +// hGPR_and_tcGPR Register Class... +static const MCPhysReg hGPR_and_tcGPR[] = { + ARM_R12, +}; + +// hGPR_and_tcGPR Bit set. +static const uint8_t hGPR_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, +}; + +// DPR Register Class... +static const MCPhysReg DPR[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, + ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, + ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, +}; + +// DPR Bit set. +static const uint8_t DPRBits[] = { + 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// DPR_VFP2 Register Class... +static const MCPhysReg DPR_VFP2[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, +}; + +// DPR_VFP2 Bit set. +static const uint8_t DPR_VFP2Bits[] = { + 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// DPR_8 Register Class... +static const MCPhysReg DPR_8[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, +}; + +// DPR_8 Bit set. +static const uint8_t DPR_8Bits[] = { + 0x00, + 0x00, + 0xf8, + 0x07, +}; + +// GPRPair Register Class... +static const MCPhysReg GPRPair[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, + ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, +}; + +// GPRPair Bit set. +static const uint8_t GPRPairBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, +}; + +// GPRPairnosp Register Class... +static const MCPhysReg GPRPairnosp[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, +}; + +// GPRPairnosp Bit set. +static const uint8_t GPRPairnospBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, +}; + +// GPRPair_with_gsub_0_in_tGPR Register Class... +static const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = { + ARM_R0_R1, + ARM_R2_R3, + ARM_R4_R5, + ARM_R6_R7, +}; +// GPRPair_with_gsub_0_in_tGPR Bit set. +static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, +}; +// GPRPair_with_gsub_0_in_hGPR Register Class... +static const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = { + ARM_R8_R9, + ARM_R10_R11, + ARM_R12_SP, +}; -FieldFromInstruction(fieldFromInstruction_2, uint16_t) -DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) -DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) +// GPRPair_with_gsub_0_in_hGPR Bit set. +static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, +}; -FieldFromInstruction(fieldFromInstruction_4, uint32_t) -DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) -DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) +// GPRPair_with_gsub_0_in_tcGPR Register Class... +static const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = { + ARM_R0_R1, + ARM_R2_R3, + ARM_R12_SP, +}; + +// GPRPair_with_gsub_0_in_tcGPR Bit set. +static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x21, +}; + +// GPRPair_with_gsub_1_in_tcGPR Register Class... +static const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = { + ARM_R0_R1, + ARM_R2_R3, +}; + +// GPRPair_with_gsub_1_in_tcGPR Bit set. +static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, +}; + +// GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Register Class... +static const MCPhysReg GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR[] = { + ARM_R8_R9, + ARM_R10_R11, +}; + +// GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Bit set. +static const uint8_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, +}; + +// GPRPair_with_gsub_1_in_GPRsp Register Class... +static const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = { + ARM_R12_SP, +}; + +// GPRPair_with_gsub_1_in_GPRsp Bit set. +static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// DPairSpc Register Class... +static const MCPhysReg DPairSpc[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, + ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, + ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, + ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, + ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, + ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31, +}; + +// DPairSpc Bit set. +static const uint8_t DPairSpcBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x07, +}; + +// DPairSpc_with_ssub_0 Register Class... +static const MCPhysReg DPairSpc_with_ssub_0[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, + ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, + ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, + ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, +}; + +// DPairSpc_with_ssub_0 Bit set. +static const uint8_t DPairSpc_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, +}; + +// DPairSpc_with_ssub_4 Register Class... +static const MCPhysReg DPairSpc_with_ssub_4[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, + ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, + ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, +}; + +// DPairSpc_with_ssub_4 Bit set. +static const uint8_t DPairSpc_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, +}; + +// DPairSpc_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, + ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, +}; + +// DPairSpc_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, +}; + +// DPairSpc_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, +}; + +// DPairSpc_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, +}; + +// DPair Register Class... +static const MCPhysReg DPair[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, + ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, + ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, + ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, + ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, + ARM_Q15, +}; + +// DPair Bit set. +static const uint8_t DPairBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, +}; + +// DPair_with_ssub_0 Register Class... +static const MCPhysReg DPair_with_ssub_0[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, + ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, + ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, +}; + +// DPair_with_ssub_0 Bit set. +static const uint8_t DPair_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, +}; + +// QPR Register Class... +static const MCPhysReg QPR[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, + ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, +}; + +// QPR Bit set. +static const uint8_t QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, +}; + +// DPair_with_ssub_2 Register Class... +static const MCPhysReg DPair_with_ssub_2[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, + ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, + ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, +}; + +// DPair_with_ssub_2 Bit set. +static const uint8_t DPair_with_ssub_2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, +}; + +// DPair_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, +}; + +// DPair_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, +}; + +// MQPR Register Class... +static const MCPhysReg MQPR[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, +}; + +// MQPR Bit set. +static const uint8_t MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, +}; + +// QPR_VFP2 Register Class... +static const MCPhysReg QPR_VFP2[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, +}; + +// QPR_VFP2 Bit set. +static const uint8_t QPR_VFP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, +}; + +// DPair_with_dsub_1_in_DPR_8 Register Class... +static const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, +}; + +// DPair_with_dsub_1_in_DPR_8 Bit set. +static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, +}; + +// QPR_8 Register Class... +static const MCPhysReg QPR_8[] = { + ARM_Q0, + ARM_Q1, + ARM_Q2, + ARM_Q3, +}; + +// QPR_8 Bit set. +static const uint8_t QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, +}; + +// DTriple Register Class... +static const MCPhysReg DTriple[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, + ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, + ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, + ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, + ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, + ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, + ARM_D28_D29_D30, ARM_D29_D30_D31, +}; + +// DTriple Bit set. +static const uint8_t DTripleBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, +}; + +// DTripleSpc Register Class... +static const MCPhysReg DTripleSpc[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, + ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, + ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, + ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, +}; + +// DTripleSpc Bit set. +static const uint8_t DTripleSpcBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, +}; + +// DTripleSpc_with_ssub_0 Register Class... +static const MCPhysReg DTripleSpc_with_ssub_0[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, +}; + +// DTripleSpc_with_ssub_0 Bit set. +static const uint8_t DTripleSpc_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, +}; + +// DTriple_with_ssub_0 Register Class... +static const MCPhysReg DTriple_with_ssub_0[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, + ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, + ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, +}; + +// DTriple_with_ssub_0 Bit set. +static const uint8_t DTriple_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, +}; + +// DTriple_with_qsub_0_in_QPR Register Class... +static const MCPhysReg DTriple_with_qsub_0_in_QPR[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, + ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, + ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, + ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30, +}; + +// DTriple_with_qsub_0_in_QPR Bit set. +static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x55, 0x55, 0x05, +}; + +// DTriple_with_ssub_2 Register Class... +static const MCPhysReg DTriple_with_ssub_2[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, + ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, + ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, +}; + +// DTriple_with_ssub_2 Bit set. +static const uint8_t DTriple_with_ssub_2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... +static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, + ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, + ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, + ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. +static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x0a, +}; + +// DTripleSpc_with_ssub_4 Register Class... +static const MCPhysReg DTripleSpc_with_ssub_4[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, +}; + +// DTripleSpc_with_ssub_4 Bit set. +static const uint8_t DTripleSpc_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, +}; + +// DTriple_with_ssub_4 Register Class... +static const MCPhysReg DTriple_with_ssub_4[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, + ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, + ARM_D12_D13_D14, ARM_D13_D14_D15, +}; + +// DTriple_with_ssub_4 Bit set. +static const uint8_t DTriple_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, +}; + +// DTripleSpc_with_ssub_8 Register Class... +static const MCPhysReg DTripleSpc_with_ssub_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, +}; + +// DTripleSpc_with_ssub_8 Bit set. +static const uint8_t DTripleSpc_with_ssub_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, +}; + +// DTripleSpc_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, +}; + +// DTripleSpc_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, +}; + +// DTriple_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, +}; + +// DTriple_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, +}; + +// DTriple_with_qsub_0_in_MQPR Register Class... +static const MCPhysReg DTriple_with_qsub_0_in_MQPR[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, + ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, +}; + +// DTriple_with_qsub_0_in_MQPR Bit set. +static const uint8_t DTriple_with_qsub_0_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x15, +}; + +// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR +// Register Class... +static const MCPhysReg + DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = + { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, + ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, +}; + +// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit +// set. +static const uint8_t + DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a, +}; + +// DTriple_with_dsub_1_in_DPR_8 Register Class... +static const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, + ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, +}; + +// DTriple_with_dsub_1_in_DPR_8 Bit set. +static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... +static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, + ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. +static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a, +}; + +// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Register Class... +static const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, + ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, +}; + +// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Bit set. +static const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x05, +}; + +// DTripleSpc_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, + ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, +}; + +// DTripleSpc_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, +}; + +// DTriple_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, + ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, +}; + +// DTriple_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, +}; + +// DTripleSpc_with_dsub_4_in_DPR_8 Register Class... +static const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = { + ARM_D0_D2_D4, + ARM_D1_D3_D5, + ARM_D2_D4_D6, + ARM_D3_D5_D7, +}; + +// DTripleSpc_with_dsub_4_in_DPR_8 Bit set. +static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, +}; + +// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR +// Register Class... +static const MCPhysReg + DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR + [] = { + ARM_D1_D2_D3, + ARM_D3_D4_D5, + ARM_D5_D6_D7, + ARM_D7_D8_D9, +}; + +// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR +// Bit set. +static const uint8_t + DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a, +}; + +// DTriple_with_qsub_0_in_QPR_8 Register Class... +static const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = { + ARM_D0_D1_D2, + ARM_D2_D3_D4, + ARM_D4_D5_D6, + ARM_D6_D7_D8, +}; + +// DTriple_with_qsub_0_in_QPR_8 Bit set. +static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x15, +}; + +// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Register +// Class... +static const MCPhysReg + DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR[] = { + ARM_D0_D1_D2, + ARM_D2_D3_D4, + ARM_D4_D5_D6, +}; + +// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Bit set. +static const uint8_t + DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... +static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { + ARM_D1_D2_D3, + ARM_D3_D4_D5, + ARM_D5_D6_D7, +}; + +// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. +static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a, +}; + +// DQuadSpc Register Class... +static const MCPhysReg DQuadSpc[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, + ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, + ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, + ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, +}; + +// DQuadSpc Bit set. +static const uint8_t DQuadSpcBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, +}; + +// DQuadSpc_with_ssub_0 Register Class... +static const MCPhysReg DQuadSpc_with_ssub_0[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, +}; + +// DQuadSpc_with_ssub_0 Bit set. +static const uint8_t DQuadSpc_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, +}; + +// DQuadSpc_with_ssub_4 Register Class... +static const MCPhysReg DQuadSpc_with_ssub_4[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + ARM_D12_D14_D16, ARM_D13_D15_D17, +}; + +// DQuadSpc_with_ssub_4 Bit set. +static const uint8_t DQuadSpc_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, +}; + +// DQuadSpc_with_ssub_8 Register Class... +static const MCPhysReg DQuadSpc_with_ssub_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, +}; + +// DQuadSpc_with_ssub_8 Bit set. +static const uint8_t DQuadSpc_with_ssub_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, +}; + +// DQuadSpc_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, +}; + +// DQuadSpc_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, +}; + +// DQuadSpc_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, + ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, +}; + +// DQuadSpc_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, +}; + +// DQuadSpc_with_dsub_4_in_DPR_8 Register Class... +static const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = { + ARM_D0_D2_D4, + ARM_D1_D3_D5, + ARM_D2_D4_D6, + ARM_D3_D5_D7, +}; + +// DQuadSpc_with_dsub_4_in_DPR_8 Bit set. +static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, +}; + +// DQuad Register Class... +static const MCPhysReg DQuad[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, + ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, + ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, + ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, + ARM_Q14_Q15, +}; + +// DQuad Bit set. +static const uint8_t DQuadBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, + 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, +}; + +// DQuad_with_ssub_0 Register Class... +static const MCPhysReg DQuad_with_ssub_0[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, +}; + +// DQuad_with_ssub_0 Bit set. +static const uint8_t DQuad_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, +}; + +// DQuad_with_ssub_2 Register Class... +static const MCPhysReg DQuad_with_ssub_2[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, +}; + +// DQuad_with_ssub_2 Bit set. +static const uint8_t DQuad_with_ssub_2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, +}; + +// QQPR Register Class... +static const MCPhysReg QQPR[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, + ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, + ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15, +}; + +// QQPR Bit set. +static const uint8_t QQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... +static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, + ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, + ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, + ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. +static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, +}; + +// DQuad_with_ssub_4 Register Class... +static const MCPhysReg DQuad_with_ssub_4[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, ARM_D13_D14_D15_D16, +}; + +// DQuad_with_ssub_4 Bit set. +static const uint8_t DQuad_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, +}; + +// DQuad_with_ssub_6 Register Class... +static const MCPhysReg DQuad_with_ssub_6[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, + ARM_Q6_Q7, +}; + +// DQuad_with_ssub_6 Bit set. +static const uint8_t DQuad_with_ssub_6Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, +}; + +// DQuad_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, +}; + +// DQuad_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, +}; + +// DQuad_with_qsub_0_in_MQPR Register Class... +static const MCPhysReg DQuad_with_qsub_0_in_MQPR[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, + ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, +}; + +// DQuad_with_qsub_0_in_MQPR Bit set. +static const uint8_t DQuad_with_qsub_0_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, +}; + +// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register +// Class... +static const MCPhysReg + DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, + ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, +}; + +// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. +static const uint8_t + DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, +}; + +// DQuad_with_dsub_1_in_DPR_8 Register Class... +static const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, + ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, +}; + +// DQuad_with_dsub_1_in_DPR_8 Bit set. +static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... +static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, + ARM_D13_D14_D15_D16, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. +static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, +}; + +// MQQPR Register Class... +static const MCPhysReg MQQPR[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, +}; + +// MQQPR Bit set. +static const uint8_t MQQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, +}; + +// DQuad_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, + ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, +}; + +// DQuad_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, +}; + +// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register +// Class... +static const MCPhysReg + DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, +}; + +// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. +static const uint8_t + DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, +}; + +// DQuad_with_dsub_3_in_DPR_8 Register Class... +static const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, +}; + +// DQuad_with_dsub_3_in_DPR_8 Bit set. +static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, +}; + +// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR +// Register Class... +static const MCPhysReg + DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR + [] = { + ARM_D1_D2_D3_D4, + ARM_D3_D4_D5_D6, + ARM_D5_D6_D7_D8, + ARM_D7_D8_D9_D10, +}; + +// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR +// Bit set. +static const uint8_t + DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, +}; + +// DQuad_with_qsub_0_in_QPR_8 Register Class... +static const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = { + ARM_Q0_Q1, + ARM_Q1_Q2, + ARM_Q2_Q3, + ARM_Q3_Q4, +}; + +// DQuad_with_qsub_0_in_QPR_8 Bit set. +static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, +}; + +// DQuad_with_qsub_1_in_QPR_8 Register Class... +static const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = { + ARM_Q0_Q1, + ARM_Q1_Q2, + ARM_Q2_Q3, +}; + +// DQuad_with_qsub_1_in_QPR_8 Bit set. +static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... +static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { + ARM_D1_D2_D3_D4, + ARM_D3_D4_D5_D6, + ARM_D5_D6_D7_D8, +}; + +// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. +static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, +}; + +// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR +// Register Class... +static const MCPhysReg + DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR + [] = { + ARM_D1_D2_D3_D4, + ARM_D3_D4_D5_D6, +}; + +// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR +// Bit set. +static const uint8_t + DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, +}; + +// QQQQPR Register Class... +static const MCPhysReg QQQQPR[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, + ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, + ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, + ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, + ARM_Q12_Q13_Q14_Q15, +}; + +// QQQQPR Bit set. +static const uint8_t QQQQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, +}; + +// QQQQPR_with_ssub_0 Register Class... +static const MCPhysReg QQQQPR_with_ssub_0[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, + ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, +}; + +// QQQQPR_with_ssub_0 Bit set. +static const uint8_t QQQQPR_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, +}; + +// QQQQPR_with_ssub_4 Register Class... +static const MCPhysReg QQQQPR_with_ssub_4[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, + ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, +}; + +// QQQQPR_with_ssub_4 Bit set. +static const uint8_t QQQQPR_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, +}; + +// QQQQPR_with_ssub_8 Register Class... +static const MCPhysReg QQQQPR_with_ssub_8[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, + ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, +}; + +// QQQQPR_with_ssub_8 Bit set. +static const uint8_t QQQQPR_with_ssub_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, +}; + +// MQQQQPR Register Class... +static const MCPhysReg MQQQQPR[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, + ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, +}; + +// MQQQQPR Bit set. +static const uint8_t MQQQQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, +}; + +// MQQQQPR_with_dsub_0_in_DPR_8 Register Class... +static const MCPhysReg MQQQQPR_with_dsub_0_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, + ARM_Q1_Q2_Q3_Q4, + ARM_Q2_Q3_Q4_Q5, + ARM_Q3_Q4_Q5_Q6, +}; + +// MQQQQPR_with_dsub_0_in_DPR_8 Bit set. +static const uint8_t MQQQQPR_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, +}; + +// MQQQQPR_with_dsub_2_in_DPR_8 Register Class... +static const MCPhysReg MQQQQPR_with_dsub_2_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, + ARM_Q1_Q2_Q3_Q4, + ARM_Q2_Q3_Q4_Q5, +}; + +// MQQQQPR_with_dsub_2_in_DPR_8 Bit set. +static const uint8_t MQQQQPR_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, +}; + +// MQQQQPR_with_dsub_4_in_DPR_8 Register Class... +static const MCPhysReg MQQQQPR_with_dsub_4_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, + ARM_Q1_Q2_Q3_Q4, +}; + +// MQQQQPR_with_dsub_4_in_DPR_8 Bit set. +static const uint8_t MQQQQPR_with_dsub_4_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, +}; + +// MQQQQPR_with_dsub_6_in_DPR_8 Register Class... +static const MCPhysReg MQQQQPR_with_dsub_6_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, +}; + +// MQQQQPR_with_dsub_6_in_DPR_8 Bit set. +static const uint8_t MQQQQPR_with_dsub_6_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, +}; + +// end of register classes misc + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char ARMRegClassStrings[] = { + /* 0 */ "QQQQPR_with_ssub_0\0" + /* 19 */ "FPWithVPR_with_ssub_0\0" + /* 41 */ "DQuadSpc_with_ssub_0\0" + /* 62 */ "DTripleSpc_with_ssub_0\0" + /* 85 */ "DPairSpc_with_ssub_0\0" + /* 106 */ "DQuad_with_ssub_0\0" + /* 124 */ "DTriple_with_ssub_0\0" + /* 144 */ "DPair_with_ssub_0\0" + /* 162 */ "DPR_VFP2\0" + /* 171 */ "QPR_VFP2\0" + /* 180 */ "DQuad_with_ssub_2\0" + /* 198 */ "DTriple_with_ssub_2\0" + /* 218 */ "DPair_with_ssub_2\0" + /* 236 */ "QQQQPR_with_ssub_4\0" + /* 255 */ "DQuadSpc_with_ssub_4\0" + /* 276 */ "DTripleSpc_with_ssub_4\0" + /* 299 */ "DPairSpc_with_ssub_4\0" + /* 320 */ "DQuad_with_ssub_4\0" + /* 338 */ "DTriple_with_ssub_4\0" + /* 358 */ "DQuad_with_ssub_6\0" + /* 376 */ "MQQQQPR_with_dsub_0_in_DPR_8\0" + /* 405 */ "DQuadSpc_with_dsub_0_in_DPR_8\0" + /* 435 */ "DTripleSpc_with_dsub_0_in_DPR_8\0" + /* 467 */ "DPairSpc_with_dsub_0_in_DPR_8\0" + /* 497 */ "DQuad_with_dsub_0_in_DPR_8\0" + /* 524 */ "DTriple_with_dsub_0_in_DPR_8\0" + /* 553 */ "DPair_with_dsub_0_in_DPR_8\0" + /* 580 */ "DQuad_with_dsub_1_in_DPR_8\0" + /* 607 */ "DTriple_with_dsub_1_in_DPR_8\0" + /* 636 */ "DPair_with_dsub_1_in_DPR_8\0" + /* 663 */ "MQQQQPR_with_dsub_2_in_DPR_8\0" + /* 692 */ "DQuadSpc_with_dsub_2_in_DPR_8\0" + /* 722 */ "DTripleSpc_with_dsub_2_in_DPR_8\0" + /* 754 */ "DPairSpc_with_dsub_2_in_DPR_8\0" + /* 784 */ "DQuad_with_dsub_2_in_DPR_8\0" + /* 811 */ "DTriple_with_dsub_2_in_DPR_8\0" + /* 840 */ "DQuad_with_dsub_3_in_DPR_8\0" + /* 867 */ "MQQQQPR_with_dsub_4_in_DPR_8\0" + /* 896 */ "DQuadSpc_with_dsub_4_in_DPR_8\0" + /* 926 */ "DTripleSpc_with_dsub_4_in_DPR_8\0" + /* 958 */ "MQQQQPR_with_dsub_6_in_DPR_8\0" + /* 987 */ "DQuad_with_qsub_0_in_QPR_8\0" + /* 1014 */ "DTriple_with_qsub_0_in_QPR_8\0" + /* 1043 */ "DQuad_with_qsub_1_in_QPR_8\0" + /* 1070 */ "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\0" + /* 1118 */ "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8\0" + /* 1168 */ "FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8\0" + /* 1211 */ "QQQQPR_with_ssub_8\0" + /* 1230 */ "DQuadSpc_with_ssub_8\0" + /* 1251 */ "DTripleSpc_with_ssub_8\0" + /* 1274 */ "VCCR\0" + /* 1279 */ "DPR\0" + /* 1283 */ "hGPR_and_tcGPR\0" + /* 1298 */ "tGPROdd_and_tcGPR\0" + /* 1316 */ "tGPREven_and_tcGPR\0" + /* 1335 */ "tGPREven_and_GPRnoip_and_tcGPR\0" + /* 1366 */ "GPRPair_with_gsub_0_in_tcGPR\0" + /* 1395 */ "GPRPair_with_gsub_1_in_tcGPR\0" + /* 1424 */ "GPRnopc_and_hGPR\0" + /* 1441 */ "GPRnopc_and_GPRnoip_and_hGPR\0" + /* 1470 */ "GPRwithAPSR_NZCVnosp_and_GPRnoip_and_hGPR\0" + /* 1512 */ "GPRwithAPSR_NZCVnosp_and_hGPR\0" + /* 1542 */ "GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR\0" + /* 1586 */ "rGPR\0" + /* 1591 */ "GPRPair_with_gsub_0_in_tGPR\0" + /* 1619 */ "HPR\0" + /* 1623 */ "DQuad_with_qsub_0_in_MQPR\0" + /* 1649 */ "DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR\0" + /* 1701 */ "DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_" + "in_MQPR\0" + /* 1762 */ "DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_" + "ssub_5_in_MQPR\0" + /* 1831 */ "DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_" + "3_ssub_4_ssub_5_in_MQPR\0" + /* 1909 */ "DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_" + "3_ssub_4_ssub_5_in_MQPR\0" + /* 1987 */ "DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_" + "ssub_3_ssub_4_ssub_5_in_MQPR\0" + /* 2069 */ "MQQPR\0" + /* 2075 */ "MQQQQPR\0" + /* 2083 */ "DTriple_with_qsub_0_in_QPR\0" + /* 2110 */ "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_" + "ssub_5_in_QPR\0" + /* 2178 */ "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_" + "ssub_4_ssub_5_in_QPR\0" + /* 2250 */ "SPR\0" + /* 2254 */ "FPWithVPR\0" + /* 2264 */ "GPRwithAPSR\0" + /* 2276 */ "GPRwithZR\0" + /* 2286 */ "cl_FPSCR_NZCV\0" + /* 2300 */ "DQuadSpc\0" + /* 2309 */ "DTripleSpc\0" + /* 2320 */ "DPairSpc\0" + /* 2329 */ "hGPR_and_tGPRwithpc\0" + /* 2349 */ "GPRnoip_and_GPRnopc\0" + /* 2369 */ "DQuad\0" + /* 2375 */ "hGPR_and_tGPROdd\0" + /* 2392 */ "tGPR_and_tGPROdd\0" + /* 2409 */ "DTriple\0" + /* 2417 */ "hGPR_and_tGPREven\0" + /* 2435 */ "tGPR_and_tGPREven\0" + /* 2453 */ "hGPR_and_GPRnoip_and_tGPREven\0" + /* 2483 */ "GPRnoip\0" + /* 2491 */ "GPRPair_with_gsub_1_in_GPRsp\0" + /* 2520 */ "GPRwithAPSRnosp\0" + /* 2536 */ "GPRwithZRnosp\0" + /* 2550 */ "GPRnoip_and_GPRwithAPSR_NZCVnosp\0" + /* 2583 */ "GPRPairnosp\0" + /* 2595 */ "DPair\0" + /* 2601 */ "GPRPair\0" + /* 2609 */ "GPRlr\0" + /* 2615 */ "FPCXTRegs\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterClass ARMMCRegisterClasses[] = { + {HPR, HPRBits, sizeof(HPRBits)}, + {FPWithVPR, FPWithVPRBits, sizeof(FPWithVPRBits)}, + {SPR, SPRBits, sizeof(SPRBits)}, + {FPWithVPR_with_ssub_0, FPWithVPR_with_ssub_0Bits, + sizeof(FPWithVPR_with_ssub_0Bits)}, + {GPR, GPRBits, sizeof(GPRBits)}, + {GPRwithAPSR, GPRwithAPSRBits, sizeof(GPRwithAPSRBits)}, + {GPRwithZR, GPRwithZRBits, sizeof(GPRwithZRBits)}, + {SPR_8, SPR_8Bits, sizeof(SPR_8Bits)}, + {GPRnopc, GPRnopcBits, sizeof(GPRnopcBits)}, + {GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnospBits, + sizeof(GPRwithAPSR_NZCVnospBits)}, + {GPRwithAPSRnosp, GPRwithAPSRnospBits, sizeof(GPRwithAPSRnospBits)}, + {GPRwithZRnosp, GPRwithZRnospBits, sizeof(GPRwithZRnospBits)}, + {GPRnoip, GPRnoipBits, sizeof(GPRnoipBits)}, + {rGPR, rGPRBits, sizeof(rGPRBits)}, + {GPRnoip_and_GPRnopc, GPRnoip_and_GPRnopcBits, + sizeof(GPRnoip_and_GPRnopcBits)}, + {GPRnoip_and_GPRwithAPSR_NZCVnosp, GPRnoip_and_GPRwithAPSR_NZCVnospBits, + sizeof(GPRnoip_and_GPRwithAPSR_NZCVnospBits)}, + {tGPRwithpc, tGPRwithpcBits, sizeof(tGPRwithpcBits)}, + {FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8, + FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits, + sizeof(FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits)}, + {hGPR, hGPRBits, sizeof(hGPRBits)}, + {tGPR, tGPRBits, sizeof(tGPRBits)}, + {tGPREven, tGPREvenBits, sizeof(tGPREvenBits)}, + {GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, sizeof(GPRnopc_and_hGPRBits)}, + {GPRnoip_and_hGPR, GPRnoip_and_hGPRBits, sizeof(GPRnoip_and_hGPRBits)}, + {GPRnoip_and_tGPREven, GPRnoip_and_tGPREvenBits, + sizeof(GPRnoip_and_tGPREvenBits)}, + {GPRwithAPSR_NZCVnosp_and_hGPR, GPRwithAPSR_NZCVnosp_and_hGPRBits, + sizeof(GPRwithAPSR_NZCVnosp_and_hGPRBits)}, + {tGPROdd, tGPROddBits, sizeof(tGPROddBits)}, + {GPRnopc_and_GPRnoip_and_hGPR, GPRnopc_and_GPRnoip_and_hGPRBits, + sizeof(GPRnopc_and_GPRnoip_and_hGPRBits)}, + {tcGPR, tcGPRBits, sizeof(tcGPRBits)}, + {GPRnoip_and_tcGPR, GPRnoip_and_tcGPRBits, sizeof(GPRnoip_and_tcGPRBits)}, + {GPRwithAPSR_NZCVnosp_and_GPRnoip_and_hGPR, + GPRwithAPSR_NZCVnosp_and_GPRnoip_and_hGPRBits, + sizeof(GPRwithAPSR_NZCVnosp_and_GPRnoip_and_hGPRBits)}, + {hGPR_and_tGPREven, hGPR_and_tGPREvenBits, sizeof(hGPR_and_tGPREvenBits)}, + {tGPR_and_tGPREven, tGPR_and_tGPREvenBits, sizeof(tGPR_and_tGPREvenBits)}, + {tGPR_and_tGPROdd, tGPR_and_tGPROddBits, sizeof(tGPR_and_tGPROddBits)}, + {tGPREven_and_tcGPR, tGPREven_and_tcGPRBits, + sizeof(tGPREven_and_tcGPRBits)}, + {hGPR_and_GPRnoip_and_tGPREven, hGPR_and_GPRnoip_and_tGPREvenBits, + sizeof(hGPR_and_GPRnoip_and_tGPREvenBits)}, + {hGPR_and_tGPROdd, hGPR_and_tGPROddBits, sizeof(hGPR_and_tGPROddBits)}, + {tGPREven_and_GPRnoip_and_tcGPR, tGPREven_and_GPRnoip_and_tcGPRBits, + sizeof(tGPREven_and_GPRnoip_and_tcGPRBits)}, + {tGPROdd_and_tcGPR, tGPROdd_and_tcGPRBits, sizeof(tGPROdd_and_tcGPRBits)}, + {CCR, CCRBits, sizeof(CCRBits)}, + {FPCXTRegs, FPCXTRegsBits, sizeof(FPCXTRegsBits)}, + {GPRlr, GPRlrBits, sizeof(GPRlrBits)}, + {GPRsp, GPRspBits, sizeof(GPRspBits)}, + {VCCR, VCCRBits, sizeof(VCCRBits)}, + {cl_FPSCR_NZCV, cl_FPSCR_NZCVBits, sizeof(cl_FPSCR_NZCVBits)}, + {hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, + sizeof(hGPR_and_tGPRwithpcBits)}, + {hGPR_and_tcGPR, hGPR_and_tcGPRBits, sizeof(hGPR_and_tcGPRBits)}, + {DPR, DPRBits, sizeof(DPRBits)}, + {DPR_VFP2, DPR_VFP2Bits, sizeof(DPR_VFP2Bits)}, + {DPR_8, DPR_8Bits, sizeof(DPR_8Bits)}, + {GPRPair, GPRPairBits, sizeof(GPRPairBits)}, + {GPRPairnosp, GPRPairnospBits, sizeof(GPRPairnospBits)}, + {GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, + sizeof(GPRPair_with_gsub_0_in_tGPRBits)}, + {GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, + sizeof(GPRPair_with_gsub_0_in_hGPRBits)}, + {GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, + sizeof(GPRPair_with_gsub_0_in_tcGPRBits)}, + {GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, + sizeof(GPRPair_with_gsub_1_in_tcGPRBits)}, + {GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR, + GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits, + sizeof(GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits)}, + {GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, + sizeof(GPRPair_with_gsub_1_in_GPRspBits)}, + {DPairSpc, DPairSpcBits, sizeof(DPairSpcBits)}, + {DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, + sizeof(DPairSpc_with_ssub_0Bits)}, + {DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, + sizeof(DPairSpc_with_ssub_4Bits)}, + {DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, + sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits)}, + {DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, + sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits)}, + {DPair, DPairBits, sizeof(DPairBits)}, + {DPair_with_ssub_0, DPair_with_ssub_0Bits, sizeof(DPair_with_ssub_0Bits)}, + {QPR, QPRBits, sizeof(QPRBits)}, + {DPair_with_ssub_2, DPair_with_ssub_2Bits, sizeof(DPair_with_ssub_2Bits)}, + {DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, + sizeof(DPair_with_dsub_0_in_DPR_8Bits)}, + {MQPR, MQPRBits, sizeof(MQPRBits)}, + {QPR_VFP2, QPR_VFP2Bits, sizeof(QPR_VFP2Bits)}, + {DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, + sizeof(DPair_with_dsub_1_in_DPR_8Bits)}, + {QPR_8, QPR_8Bits, sizeof(QPR_8Bits)}, + {DTriple, DTripleBits, sizeof(DTripleBits)}, + {DTripleSpc, DTripleSpcBits, sizeof(DTripleSpcBits)}, + {DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, + sizeof(DTripleSpc_with_ssub_0Bits)}, + {DTriple_with_ssub_0, DTriple_with_ssub_0Bits, + sizeof(DTriple_with_ssub_0Bits)}, + {DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, + sizeof(DTriple_with_qsub_0_in_QPRBits)}, + {DTriple_with_ssub_2, DTriple_with_ssub_2Bits, + sizeof(DTriple_with_ssub_2Bits)}, + {DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, + DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, + sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits)}, + {DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, + sizeof(DTripleSpc_with_ssub_4Bits)}, + {DTriple_with_ssub_4, DTriple_with_ssub_4Bits, + sizeof(DTriple_with_ssub_4Bits)}, + {DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, + sizeof(DTripleSpc_with_ssub_8Bits)}, + {DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, + sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits)}, + {DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, + sizeof(DTriple_with_dsub_0_in_DPR_8Bits)}, + {DTriple_with_qsub_0_in_MQPR, DTriple_with_qsub_0_in_MQPRBits, + sizeof(DTriple_with_qsub_0_in_MQPRBits)}, + {DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, + DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, + sizeof( + DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits)}, + {DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, + sizeof(DTriple_with_dsub_1_in_DPR_8Bits)}, + {DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits)}, + {DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR, + DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits, + sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits)}, + {DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, + sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits)}, + {DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, + sizeof(DTriple_with_dsub_2_in_DPR_8Bits)}, + {DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, + sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits)}, + {DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof( + DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits)}, + {DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, + sizeof(DTriple_with_qsub_0_in_QPR_8Bits)}, + {DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR, + DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits, + sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits)}, + {DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, + DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, + sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits)}, + {DQuadSpc, DQuadSpcBits, sizeof(DQuadSpcBits)}, + {DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, + sizeof(DQuadSpc_with_ssub_0Bits)}, + {DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, + sizeof(DQuadSpc_with_ssub_4Bits)}, + {DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, + sizeof(DQuadSpc_with_ssub_8Bits)}, + {DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, + sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits)}, + {DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, + sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits)}, + {DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, + sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits)}, + {DQuad, DQuadBits, sizeof(DQuadBits)}, + {DQuad_with_ssub_0, DQuad_with_ssub_0Bits, sizeof(DQuad_with_ssub_0Bits)}, + {DQuad_with_ssub_2, DQuad_with_ssub_2Bits, sizeof(DQuad_with_ssub_2Bits)}, + {QQPR, QQPRBits, sizeof(QQPRBits)}, + {DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, + DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, + sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits)}, + {DQuad_with_ssub_4, DQuad_with_ssub_4Bits, sizeof(DQuad_with_ssub_4Bits)}, + {DQuad_with_ssub_6, DQuad_with_ssub_6Bits, sizeof(DQuad_with_ssub_6Bits)}, + {DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, + sizeof(DQuad_with_dsub_0_in_DPR_8Bits)}, + {DQuad_with_qsub_0_in_MQPR, DQuad_with_qsub_0_in_MQPRBits, + sizeof(DQuad_with_qsub_0_in_MQPRBits)}, + {DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, + DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, + sizeof( + DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits)}, + {DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, + sizeof(DQuad_with_dsub_1_in_DPR_8Bits)}, + {DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits)}, + {MQQPR, MQQPRBits, sizeof(MQQPRBits)}, + {DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, + sizeof(DQuad_with_dsub_2_in_DPR_8Bits)}, + {DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof( + DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits)}, + {DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, + sizeof(DQuad_with_dsub_3_in_DPR_8Bits)}, + {DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof( + DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits)}, + {DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, + sizeof(DQuad_with_qsub_0_in_QPR_8Bits)}, + {DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, + sizeof(DQuad_with_qsub_1_in_QPR_8Bits)}, + {DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, + DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, + sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits)}, + {DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, + DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, + sizeof( + DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits)}, + {QQQQPR, QQQQPRBits, sizeof(QQQQPRBits)}, + {QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, + sizeof(QQQQPR_with_ssub_0Bits)}, + {QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, + sizeof(QQQQPR_with_ssub_4Bits)}, + {QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, + sizeof(QQQQPR_with_ssub_8Bits)}, + {MQQQQPR, MQQQQPRBits, sizeof(MQQQQPRBits)}, + {MQQQQPR_with_dsub_0_in_DPR_8, MQQQQPR_with_dsub_0_in_DPR_8Bits, + sizeof(MQQQQPR_with_dsub_0_in_DPR_8Bits)}, + {MQQQQPR_with_dsub_2_in_DPR_8, MQQQQPR_with_dsub_2_in_DPR_8Bits, + sizeof(MQQQQPR_with_dsub_2_in_DPR_8Bits)}, + {MQQQQPR_with_dsub_4_in_DPR_8, MQQQQPR_with_dsub_4_in_DPR_8Bits, + sizeof(MQQQQPR_with_dsub_4_in_DPR_8Bits)}, + {MQQQQPR_with_dsub_6_in_DPR_8, MQQQQPR_with_dsub_6_in_DPR_8Bits, + sizeof(MQQQQPR_with_dsub_6_in_DPR_8Bits)}, +}; + +#endif // GET_REGINFO_MC_DESC + +#ifdef GET_ASM_WRITER +#undef GET_ASM_WRITER + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +typedef struct MCMnemonic { + const char *first; + uint64_t second; +} MCMnemonic; + +static MCMnemonic createMnemonic(const char *first, uint64_t second) { + MCMnemonic mnemonic; + mnemonic.first = first; + mnemonic.second = second; + return mnemonic; +} + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +MCMnemonic ARM_getMnemonic(const MCInst *MI) { + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "vcx1\t\0" + /* 6 */ "vld20.32\t\0" + /* 16 */ "vst20.32\t\0" + /* 26 */ "vld40.32\t\0" + /* 36 */ "vst40.32\t\0" + /* 46 */ "sha1su0.32\t\0" + /* 58 */ "sha256su0.32\t\0" + /* 72 */ "vld21.32\t\0" + /* 82 */ "vst21.32\t\0" + /* 92 */ "vld41.32\t\0" + /* 102 */ "vst41.32\t\0" + /* 112 */ "sha1su1.32\t\0" + /* 124 */ "sha256su1.32\t\0" + /* 138 */ "vld42.32\t\0" + /* 148 */ "vst42.32\t\0" + /* 158 */ "sha256h2.32\t\0" + /* 171 */ "vld43.32\t\0" + /* 181 */ "vst43.32\t\0" + /* 191 */ "sha1c.32\t\0" + /* 201 */ "sha1h.32\t\0" + /* 211 */ "sha256h.32\t\0" + /* 223 */ "sha1m.32\t\0" + /* 233 */ "sha1p.32\t\0" + /* 243 */ "dlstp.32\t\0" + /* 253 */ "wlstp.32\t\0" + /* 263 */ "vcvta.s32.f32\t\0" + /* 278 */ "vcvtm.s32.f32\t\0" + /* 293 */ "vcvtn.s32.f32\t\0" + /* 308 */ "vcvtp.s32.f32\t\0" + /* 323 */ "vcvta.u32.f32\t\0" + /* 338 */ "vcvtm.u32.f32\t\0" + /* 353 */ "vcvtn.u32.f32\t\0" + /* 368 */ "vcvtp.u32.f32\t\0" + /* 383 */ "vcmla.f32\t\0" + /* 394 */ "vrinta.f32\t\0" + /* 406 */ "vcadd.f32\t\0" + /* 417 */ "vselge.f32\t\0" + /* 429 */ "vminnm.f32\t\0" + /* 441 */ "vmaxnm.f32\t\0" + /* 453 */ "vrintm.f32\t\0" + /* 465 */ "vrintn.f32\t\0" + /* 477 */ "vrintp.f32\t\0" + /* 489 */ "vseleq.f32\t\0" + /* 501 */ "vselvs.f32\t\0" + /* 513 */ "vselgt.f32\t\0" + /* 525 */ "vrintx.f32\t\0" + /* 537 */ "vrintz.f32\t\0" + /* 549 */ "ldc2\t\0" + /* 555 */ "mrc2\t\0" + /* 561 */ "mrrc2\t\0" + /* 568 */ "stc2\t\0" + /* 574 */ "cdp2\t\0" + /* 580 */ "mcr2\t\0" + /* 586 */ "mcrr2\t\0" + /* 593 */ "vcx2\t\0" + /* 599 */ "vcx3\t\0" + /* 605 */ "dlstp.64\t\0" + /* 615 */ "wlstp.64\t\0" + /* 625 */ "vcvta.s32.f64\t\0" + /* 640 */ "vcvtm.s32.f64\t\0" + /* 655 */ "vcvtn.s32.f64\t\0" + /* 670 */ "vcvtp.s32.f64\t\0" + /* 685 */ "vcvta.u32.f64\t\0" + /* 700 */ "vcvtm.u32.f64\t\0" + /* 715 */ "vcvtn.u32.f64\t\0" + /* 730 */ "vcvtp.u32.f64\t\0" + /* 745 */ "vrinta.f64\t\0" + /* 757 */ "vselge.f64\t\0" + /* 769 */ "vminnm.f64\t\0" + /* 781 */ "vmaxnm.f64\t\0" + /* 793 */ "vrintm.f64\t\0" + /* 805 */ "vrintn.f64\t\0" + /* 817 */ "vrintp.f64\t\0" + /* 829 */ "vseleq.f64\t\0" + /* 841 */ "vselvs.f64\t\0" + /* 853 */ "vselgt.f64\t\0" + /* 865 */ "vmull.p64\t\0" + /* 876 */ "vld20.16\t\0" + /* 886 */ "vst20.16\t\0" + /* 896 */ "vld40.16\t\0" + /* 906 */ "vst40.16\t\0" + /* 916 */ "vld21.16\t\0" + /* 926 */ "vst21.16\t\0" + /* 936 */ "vld41.16\t\0" + /* 946 */ "vst41.16\t\0" + /* 956 */ "vld42.16\t\0" + /* 966 */ "vst42.16\t\0" + /* 976 */ "vld43.16\t\0" + /* 986 */ "vst43.16\t\0" + /* 996 */ "dlstp.16\t\0" + /* 1006 */ "wlstp.16\t\0" + /* 1016 */ "vcvta.s32.f16\t\0" + /* 1031 */ "vcvtm.s32.f16\t\0" + /* 1046 */ "vcvtn.s32.f16\t\0" + /* 1061 */ "vcvtp.s32.f16\t\0" + /* 1076 */ "vcvta.u32.f16\t\0" + /* 1091 */ "vcvtm.u32.f16\t\0" + /* 1106 */ "vcvtn.u32.f16\t\0" + /* 1121 */ "vcvtp.u32.f16\t\0" + /* 1136 */ "vcvta.s16.f16\t\0" + /* 1151 */ "vcvtm.s16.f16\t\0" + /* 1166 */ "vcvtn.s16.f16\t\0" + /* 1181 */ "vcvtp.s16.f16\t\0" + /* 1196 */ "vcvta.u16.f16\t\0" + /* 1211 */ "vcvtm.u16.f16\t\0" + /* 1226 */ "vcvtn.u16.f16\t\0" + /* 1241 */ "vcvtp.u16.f16\t\0" + /* 1256 */ "vcmla.f16\t\0" + /* 1267 */ "vrinta.f16\t\0" + /* 1279 */ "vcadd.f16\t\0" + /* 1290 */ "vselge.f16\t\0" + /* 1302 */ "vfmal.f16\t\0" + /* 1313 */ "vfmsl.f16\t\0" + /* 1324 */ "vminnm.f16\t\0" + /* 1336 */ "vmaxnm.f16\t\0" + /* 1348 */ "vrintm.f16\t\0" + /* 1360 */ "vrintn.f16\t\0" + /* 1372 */ "vrintp.f16\t\0" + /* 1384 */ "vseleq.f16\t\0" + /* 1396 */ "vins.f16\t\0" + /* 1406 */ "vselvs.f16\t\0" + /* 1418 */ "vselgt.f16\t\0" + /* 1430 */ "vrintx.f16\t\0" + /* 1442 */ "vmovx.f16\t\0" + /* 1453 */ "vrintz.f16\t\0" + /* 1465 */ "vmmla.bf16\t\0" + /* 1477 */ "vfmab.bf16\t\0" + /* 1489 */ "vfmat.bf16\t\0" + /* 1501 */ "vdot.bf16\t\0" + /* 1512 */ "vld20.8\t\0" + /* 1521 */ "vst20.8\t\0" + /* 1530 */ "vld40.8\t\0" + /* 1539 */ "vst40.8\t\0" + /* 1548 */ "vld21.8\t\0" + /* 1557 */ "vst21.8\t\0" + /* 1566 */ "vld41.8\t\0" + /* 1575 */ "vst41.8\t\0" + /* 1584 */ "vld42.8\t\0" + /* 1593 */ "vst42.8\t\0" + /* 1602 */ "vld43.8\t\0" + /* 1611 */ "vst43.8\t\0" + /* 1620 */ "aesimc.8\t\0" + /* 1630 */ "aesmc.8\t\0" + /* 1639 */ "aesd.8\t\0" + /* 1647 */ "aese.8\t\0" + /* 1655 */ "dlstp.8\t\0" + /* 1664 */ "wlstp.8\t\0" + /* 1673 */ "vusmmla.s8\t\0" + /* 1685 */ "vsmmla.s8\t\0" + /* 1696 */ "vusdot.s8\t\0" + /* 1707 */ "vsdot.s8\t\0" + /* 1717 */ "vummla.u8\t\0" + /* 1728 */ "vsudot.u8\t\0" + /* 1739 */ "vudot.u8\t\0" + /* 1749 */ "vcx1a\t\0" + /* 1756 */ "vcx2a\t\0" + /* 1763 */ "vcx3a\t\0" + /* 1770 */ "rfeda\t\0" + /* 1777 */ "rfeia\t\0" + /* 1784 */ "crc32b\t\0" + /* 1792 */ "crc32cb\t\0" + /* 1801 */ "rfedb\t\0" + /* 1808 */ "rfeib\t\0" + /* 1815 */ "dmb\t\0" + /* 1820 */ "dsb\t\0" + /* 1825 */ "isb\t\0" + /* 1830 */ "tsb\t\0" + /* 1835 */ "csinc\t\0" + /* 1842 */ "hvc\t\0" + /* 1847 */ "cx1d\t\0" + /* 1853 */ "cx2d\t\0" + /* 1859 */ "cx3d\t\0" + /* 1865 */ "pld\t\0" + /* 1870 */ "setend\t\0" + /* 1878 */ "le\t\0" + /* 1882 */ "udf\t\0" + /* 1887 */ "csneg\t\0" + /* 1894 */ "crc32h\t\0" + /* 1902 */ "crc32ch\t\0" + /* 1911 */ "pli\t\0" + /* 1916 */ "ldc2l\t\0" + /* 1923 */ "stc2l\t\0" + /* 1930 */ "bl\t\0" + /* 1934 */ "bfcsel\t\0" + /* 1942 */ "setpan\t\0" + /* 1950 */ "letp\t\0" + /* 1956 */ "dls\t\0" + /* 1961 */ "wls\t\0" + /* 1966 */ "cps\t\0" + /* 1971 */ "movs\t\0" + /* 1977 */ "hlt\t\0" + /* 1982 */ "bkpt\t\0" + /* 1988 */ "csinv\t\0" + /* 1995 */ "hvc.w\t\0" + /* 2002 */ "udf.w\t\0" + /* 2009 */ "crc32w\t\0" + /* 2017 */ "crc32cw\t\0" + /* 2026 */ "pldw\t\0" + /* 2032 */ "bx\t\0" + /* 2036 */ "blx\t\0" + /* 2041 */ "cbz\t\0" + /* 2046 */ "cbnz\t\0" + /* 2052 */ "srsda\tsp!, \0" + /* 2064 */ "srsia\tsp!, \0" + /* 2076 */ "srsdb\tsp!, \0" + /* 2088 */ "srsib\tsp!, \0" + /* 2100 */ "srsda\tsp, \0" + /* 2111 */ "srsia\tsp, \0" + /* 2122 */ "srsdb\tsp, \0" + /* 2133 */ "srsib\tsp, \0" + /* 2144 */ "# XRay Function Patchable RET.\0" + /* 2175 */ "# XRay Typed Event Log.\0" + /* 2199 */ "# XRay Custom Event Log.\0" + /* 2224 */ "# XRay Function Enter.\0" + /* 2247 */ "# XRay Tail Call Exit.\0" + /* 2270 */ "# XRay Function Exit.\0" + /* 2292 */ "__brkdiv0\0" + /* 2302 */ "vld1\0" + /* 2307 */ "dcps1\0" + /* 2313 */ "vst1\0" + /* 2318 */ "vcx1\0" + /* 2323 */ "vrev32\0" + /* 2330 */ "ldc2\0" + /* 2335 */ "mrc2\0" + /* 2340 */ "mrrc2\0" + /* 2346 */ "stc2\0" + /* 2351 */ "vld2\0" + /* 2356 */ "cdp2\0" + /* 2361 */ "mcr2\0" + /* 2366 */ "mcrr2\0" + /* 2372 */ "dcps2\0" + /* 2378 */ "vst2\0" + /* 2383 */ "vcx2\0" + /* 2388 */ "vld3\0" + /* 2393 */ "dcps3\0" + /* 2399 */ "vst3\0" + /* 2404 */ "vcx3\0" + /* 2409 */ "vrev64\0" + /* 2416 */ "vld4\0" + /* 2421 */ "vst4\0" + /* 2426 */ "sxtab16\0" + /* 2434 */ "uxtab16\0" + /* 2442 */ "sxtb16\0" + /* 2449 */ "uxtb16\0" + /* 2456 */ "shsub16\0" + /* 2464 */ "uhsub16\0" + /* 2472 */ "uqsub16\0" + /* 2480 */ "ssub16\0" + /* 2487 */ "usub16\0" + /* 2494 */ "shadd16\0" + /* 2502 */ "uhadd16\0" + /* 2510 */ "uqadd16\0" + /* 2518 */ "sadd16\0" + /* 2525 */ "uadd16\0" + /* 2532 */ "ssat16\0" + /* 2539 */ "usat16\0" + /* 2546 */ "vrev16\0" + /* 2553 */ "usada8\0" + /* 2560 */ "shsub8\0" + /* 2567 */ "uhsub8\0" + /* 2574 */ "uqsub8\0" + /* 2581 */ "ssub8\0" + /* 2587 */ "usub8\0" + /* 2593 */ "usad8\0" + /* 2599 */ "shadd8\0" + /* 2606 */ "uhadd8\0" + /* 2613 */ "uqadd8\0" + /* 2620 */ "sadd8\0" + /* 2626 */ "uadd8\0" + /* 2632 */ "LIFETIME_END\0" + /* 2645 */ "PSEUDO_PROBE\0" + /* 2658 */ "BUNDLE\0" + /* 2665 */ "DBG_VALUE\0" + /* 2675 */ "DBG_INSTR_REF\0" + /* 2689 */ "DBG_PHI\0" + /* 2697 */ "DBG_LABEL\0" + /* 2707 */ "@ COMPILER BARRIER\0" + /* 2726 */ "LIFETIME_START\0" + /* 2741 */ "DBG_VALUE_LIST\0" + /* 2756 */ "vcx1a\0" + /* 2762 */ "vcx2a\0" + /* 2768 */ "vcx3a\0" + /* 2774 */ "vaba\0" + /* 2779 */ "cx1da\0" + /* 2785 */ "cx2da\0" + /* 2791 */ "cx3da\0" + /* 2797 */ "lda\0" + /* 2801 */ "ldmda\0" + /* 2807 */ "stmda\0" + /* 2813 */ "vrmlaldavha\0" + /* 2825 */ "vrmlsldavha\0" + /* 2837 */ "rfeia\0" + /* 2843 */ "vldmia\0" + /* 2850 */ "vstmia\0" + /* 2857 */ "srsia\0" + /* 2863 */ "vcmla\0" + /* 2869 */ "smmla\0" + /* 2875 */ "vnmla\0" + /* 2881 */ "vmla\0" + /* 2886 */ "vfma\0" + /* 2891 */ "vfnma\0" + /* 2897 */ "vminnma\0" + /* 2905 */ "vmaxnma\0" + /* 2913 */ "vmina\0" + /* 2919 */ "vrsra\0" + /* 2925 */ "vsra\0" + /* 2930 */ "vrinta\0" + /* 2937 */ "tta\0" + /* 2941 */ "vcvta\0" + /* 2947 */ "vmladava\0" + /* 2956 */ "vmlaldava\0" + /* 2966 */ "vmlsldava\0" + /* 2976 */ "vmlsdava\0" + /* 2985 */ "vaddva\0" + /* 2992 */ "vaddlva\0" + /* 3000 */ "vmaxa\0" + /* 3006 */ "ldab\0" + /* 3011 */ "sxtab\0" + /* 3017 */ "uxtab\0" + /* 3023 */ "smlabb\0" + /* 3030 */ "smlalbb\0" + /* 3038 */ "smulbb\0" + /* 3045 */ "tbb\0" + /* 3049 */ "rfedb\0" + /* 3055 */ "vldmdb\0" + /* 3062 */ "vstmdb\0" + /* 3069 */ "srsdb\0" + /* 3075 */ "ldmib\0" + /* 3081 */ "stmib\0" + /* 3087 */ "vshllb\0" + /* 3094 */ "vqdmullb\0" + /* 3103 */ "vmullb\0" + /* 3110 */ "stlb\0" + /* 3115 */ "vmovlb\0" + /* 3122 */ "dmb\0" + /* 3126 */ "vqshrnb\0" + /* 3134 */ "vqrshrnb\0" + /* 3143 */ "vrshrnb\0" + /* 3151 */ "vshrnb\0" + /* 3158 */ "vqshrunb\0" + /* 3167 */ "vqrshrunb\0" + /* 3177 */ "vqmovunb\0" + /* 3186 */ "vqmovnb\0" + /* 3194 */ "vmovnb\0" + /* 3201 */ "swpb\0" + /* 3206 */ "vldrb\0" + /* 3212 */ "vstrb\0" + /* 3218 */ "dsb\0" + /* 3222 */ "isb\0" + /* 3226 */ "ldrsb\0" + /* 3232 */ "tsb\0" + /* 3236 */ "smlatb\0" + /* 3243 */ "pkhtb\0" + /* 3249 */ "smlaltb\0" + /* 3257 */ "smultb\0" + /* 3264 */ "vcvtb\0" + /* 3270 */ "sxtb\0" + /* 3275 */ "uxtb\0" + /* 3280 */ "qdsub\0" + /* 3286 */ "vhsub\0" + /* 3292 */ "vqsub\0" + /* 3298 */ "vsub\0" + /* 3303 */ "smlawb\0" + /* 3310 */ "smulwb\0" + /* 3317 */ "ldaexb\0" + /* 3324 */ "stlexb\0" + /* 3331 */ "ldrexb\0" + /* 3338 */ "strexb\0" + /* 3345 */ "vsbc\0" + /* 3350 */ "vadc\0" + /* 3355 */ "ldc\0" + /* 3359 */ "bfc\0" + /* 3363 */ "vbic\0" + /* 3368 */ "vshlc\0" + /* 3374 */ "smc\0" + /* 3378 */ "mrc\0" + /* 3382 */ "mrrc\0" + /* 3387 */ "rsc\0" + /* 3391 */ "stc\0" + /* 3395 */ "svc\0" + /* 3399 */ "smlad\0" + /* 3405 */ "smuad\0" + /* 3411 */ "vabd\0" + /* 3416 */ "vhcadd\0" + /* 3423 */ "vcadd\0" + /* 3429 */ "qdadd\0" + /* 3435 */ "vrhadd\0" + /* 3442 */ "vhadd\0" + /* 3448 */ "vpadd\0" + /* 3454 */ "vqadd\0" + /* 3460 */ "vadd\0" + /* 3465 */ "smlald\0" + /* 3472 */ "pld\0" + /* 3476 */ "smlsld\0" + /* 3483 */ "vand\0" + /* 3488 */ "vldrd\0" + /* 3494 */ "vstrd\0" + /* 3500 */ "smlsd\0" + /* 3506 */ "smusd\0" + /* 3512 */ "ldaexd\0" + /* 3519 */ "stlexd\0" + /* 3526 */ "ldrexd\0" + /* 3533 */ "strexd\0" + /* 3540 */ "vacge\0" + /* 3546 */ "vcge\0" + /* 3551 */ "vcle\0" + /* 3556 */ "vrecpe\0" + /* 3563 */ "vcmpe\0" + /* 3569 */ "vrsqrte\0" + /* 3577 */ "bf\0" + /* 3580 */ "vbif\0" + /* 3585 */ "dbg\0" + /* 3589 */ "vqneg\0" + /* 3595 */ "vneg\0" + /* 3600 */ "sg\0" + /* 3603 */ "ldah\0" + /* 3608 */ "vqdmlah\0" + /* 3616 */ "vqrdmlah\0" + /* 3625 */ "sxtah\0" + /* 3631 */ "uxtah\0" + /* 3637 */ "tbh\0" + /* 3641 */ "vqdmladh\0" + /* 3650 */ "vqrdmladh\0" + /* 3660 */ "vqdmlsdh\0" + /* 3669 */ "vqrdmlsdh\0" + /* 3679 */ "stlh\0" + /* 3684 */ "vqdmulh\0" + /* 3692 */ "vqrdmulh\0" + /* 3701 */ "vrmulh\0" + /* 3708 */ "vmulh\0" + /* 3714 */ "vldrh\0" + /* 3720 */ "vstrh\0" + /* 3726 */ "vqdmlash\0" + /* 3735 */ "vqrdmlash\0" + /* 3745 */ "vqrdmlsh\0" + /* 3754 */ "ldrsh\0" + /* 3760 */ "push\0" + /* 3765 */ "revsh\0" + /* 3771 */ "sxth\0" + /* 3776 */ "uxth\0" + /* 3781 */ "vrmlaldavh\0" + /* 3792 */ "vrmlsldavh\0" + /* 3803 */ "ldaexh\0" + /* 3810 */ "stlexh\0" + /* 3817 */ "ldrexh\0" + /* 3824 */ "strexh\0" + /* 3831 */ "vsbci\0" + /* 3837 */ "vadci\0" + /* 3843 */ "bfi\0" + /* 3847 */ "pli\0" + /* 3851 */ "vsli\0" + /* 3856 */ "vsri\0" + /* 3861 */ "bxj\0" + /* 3865 */ "ldc2l\0" + /* 3871 */ "stc2l\0" + /* 3877 */ "umaal\0" + /* 3883 */ "vabal\0" + /* 3889 */ "vpadal\0" + /* 3896 */ "vqdmlal\0" + /* 3904 */ "smlal\0" + /* 3910 */ "umlal\0" + /* 3916 */ "vmlal\0" + /* 3922 */ "vtbl\0" + /* 3927 */ "vsubl\0" + /* 3933 */ "ldcl\0" + /* 3938 */ "stcl\0" + /* 3943 */ "vabdl\0" + /* 3949 */ "vpaddl\0" + /* 3956 */ "vaddl\0" + /* 3962 */ "vpsel\0" + /* 3968 */ "bfl\0" + /* 3972 */ "sqshl\0" + /* 3978 */ "uqshl\0" + /* 3984 */ "vqshl\0" + /* 3990 */ "uqrshl\0" + /* 3997 */ "vqrshl\0" + /* 4004 */ "vrshl\0" + /* 4010 */ "vshl\0" + /* 4015 */ "# FEntry call\0" + /* 4029 */ "sqshll\0" + /* 4036 */ "uqshll\0" + /* 4043 */ "uqrshll\0" + /* 4051 */ "vshll\0" + /* 4057 */ "lsll\0" + /* 4062 */ "vqdmull\0" + /* 4070 */ "smull\0" + /* 4076 */ "umull\0" + /* 4082 */ "vmull\0" + /* 4088 */ "sqrshrl\0" + /* 4096 */ "srshrl\0" + /* 4103 */ "urshrl\0" + /* 4110 */ "asrl\0" + /* 4115 */ "lsrl\0" + /* 4120 */ "vbsl\0" + /* 4125 */ "vqdmlsl\0" + /* 4133 */ "vmlsl\0" + /* 4139 */ "stl\0" + /* 4143 */ "vcmul\0" + /* 4149 */ "smmul\0" + /* 4155 */ "vnmul\0" + /* 4161 */ "vmul\0" + /* 4166 */ "vmovl\0" + /* 4172 */ "vlldm\0" + /* 4178 */ "vminnm\0" + /* 4185 */ "vmaxnm\0" + /* 4192 */ "vscclrm\0" + /* 4200 */ "vrintm\0" + /* 4207 */ "vlstm\0" + /* 4213 */ "vcvtm\0" + /* 4219 */ "vrsubhn\0" + /* 4227 */ "vsubhn\0" + /* 4234 */ "vraddhn\0" + /* 4242 */ "vaddhn\0" + /* 4249 */ "vpmin\0" + /* 4255 */ "vmin\0" + /* 4260 */ "cmn\0" + /* 4264 */ "vqshrn\0" + /* 4271 */ "vqrshrn\0" + /* 4279 */ "vrshrn\0" + /* 4286 */ "vshrn\0" + /* 4292 */ "vorn\0" + /* 4297 */ "vtrn\0" + /* 4302 */ "vrintn\0" + /* 4309 */ "vcvtn\0" + /* 4315 */ "vqshrun\0" + /* 4323 */ "vqrshrun\0" + /* 4332 */ "vqmovun\0" + /* 4340 */ "vmvn\0" + /* 4345 */ "vqmovn\0" + /* 4352 */ "vmovn\0" + /* 4358 */ "trap\0" + /* 4363 */ "cdp\0" + /* 4367 */ "vzip\0" + /* 4372 */ "vcmp\0" + /* 4377 */ "pop\0" + /* 4381 */ "lctp\0" + /* 4386 */ "vctp\0" + /* 4391 */ "vrintp\0" + /* 4398 */ "vcvtp\0" + /* 4404 */ "vddup\0" + /* 4410 */ "vidup\0" + /* 4416 */ "vdup\0" + /* 4421 */ "vdwdup\0" + /* 4428 */ "viwdup\0" + /* 4435 */ "vswp\0" + /* 4440 */ "vuzp\0" + /* 4445 */ "vceq\0" + /* 4450 */ "teq\0" + /* 4454 */ "smmlar\0" + /* 4461 */ "mcr\0" + /* 4465 */ "adr\0" + /* 4469 */ "vldr\0" + /* 4474 */ "sqrshr\0" + /* 4481 */ "srshr\0" + /* 4487 */ "urshr\0" + /* 4493 */ "vrshr\0" + /* 4499 */ "vshr\0" + /* 4504 */ "smmulr\0" + /* 4511 */ "veor\0" + /* 4516 */ "ror\0" + /* 4520 */ "mcrr\0" + /* 4525 */ "vorr\0" + /* 4530 */ "asr\0" + /* 4534 */ "smmlsr\0" + /* 4541 */ "vmsr\0" + /* 4546 */ "vbrsr\0" + /* 4552 */ "vrintr\0" + /* 4559 */ "vstr\0" + /* 4564 */ "vcvtr\0" + /* 4570 */ "vmlas\0" + /* 4576 */ "vfmas\0" + /* 4582 */ "vqabs\0" + /* 4588 */ "vabs\0" + /* 4593 */ "subs\0" + /* 4598 */ "vcls\0" + /* 4603 */ "smmls\0" + /* 4609 */ "vnmls\0" + /* 4615 */ "vmls\0" + /* 4620 */ "vfms\0" + /* 4625 */ "vfnms\0" + /* 4631 */ "bxns\0" + /* 4636 */ "blxns\0" + /* 4642 */ "vrecps\0" + /* 4649 */ "vmrs\0" + /* 4654 */ "asrs\0" + /* 4659 */ "lsrs\0" + /* 4664 */ "vrsqrts\0" + /* 4672 */ "movs\0" + /* 4677 */ "ssat\0" + /* 4682 */ "usat\0" + /* 4687 */ "ttat\0" + /* 4692 */ "smlabt\0" + /* 4699 */ "pkhbt\0" + /* 4705 */ "smlalbt\0" + /* 4713 */ "smulbt\0" + /* 4720 */ "ldrbt\0" + /* 4726 */ "strbt\0" + /* 4732 */ "ldrsbt\0" + /* 4739 */ "eret\0" + /* 4744 */ "vacgt\0" + /* 4750 */ "vcgt\0" + /* 4755 */ "ldrht\0" + /* 4761 */ "strht\0" + /* 4767 */ "ldrsht\0" + /* 4774 */ "rbit\0" + /* 4779 */ "vbit\0" + /* 4784 */ "vclt\0" + /* 4789 */ "vshllt\0" + /* 4796 */ "vqdmullt\0" + /* 4805 */ "vmullt\0" + /* 4812 */ "vmovlt\0" + /* 4819 */ "vcnt\0" + /* 4824 */ "hint\0" + /* 4829 */ "vqshrnt\0" + /* 4837 */ "vqrshrnt\0" + /* 4846 */ "vrshrnt\0" + /* 4854 */ "vshrnt\0" + /* 4861 */ "vqshrunt\0" + /* 4870 */ "vqrshrunt\0" + /* 4880 */ "vqmovunt\0" + /* 4889 */ "vqmovnt\0" + /* 4897 */ "vmovnt\0" + /* 4904 */ "vpnot\0" + /* 4910 */ "vpt\0" + /* 4914 */ "ldrt\0" + /* 4919 */ "vsqrt\0" + /* 4925 */ "strt\0" + /* 4930 */ "vpst\0" + /* 4935 */ "vtst\0" + /* 4940 */ "smlatt\0" + /* 4947 */ "smlaltt\0" + /* 4955 */ "smultt\0" + /* 4962 */ "ttt\0" + /* 4966 */ "vcvtt\0" + /* 4972 */ "vjcvt\0" + /* 4978 */ "vcvt\0" + /* 4983 */ "movt\0" + /* 4988 */ "smlawt\0" + /* 4995 */ "smulwt\0" + /* 5002 */ "vext\0" + /* 5007 */ "vqshlu\0" + /* 5014 */ "vabav\0" + /* 5020 */ "vmladav\0" + /* 5028 */ "vmlaldav\0" + /* 5037 */ "vmlsldav\0" + /* 5046 */ "vmlsdav\0" + /* 5054 */ "vminnmav\0" + /* 5063 */ "vmaxnmav\0" + /* 5072 */ "vminav\0" + /* 5079 */ "vmaxav\0" + /* 5086 */ "vaddv\0" + /* 5092 */ "rev\0" + /* 5096 */ "sdiv\0" + /* 5101 */ "udiv\0" + /* 5106 */ "vdiv\0" + /* 5111 */ "vaddlv\0" + /* 5118 */ "vminnmv\0" + /* 5126 */ "vmaxnmv\0" + /* 5134 */ "vminv\0" + /* 5140 */ "vmov\0" + /* 5145 */ "vmaxv\0" + /* 5151 */ "vsubw\0" + /* 5157 */ "vaddw\0" + /* 5163 */ "pldw\0" + /* 5168 */ "vldrw\0" + /* 5174 */ "vstrw\0" + /* 5180 */ "movw\0" + /* 5185 */ "vrmlaldavhax\0" + /* 5198 */ "vrmlsldavhax\0" + /* 5211 */ "fldmiax\0" + /* 5219 */ "fstmiax\0" + /* 5227 */ "vpmax\0" + /* 5233 */ "vmax\0" + /* 5238 */ "shsax\0" + /* 5244 */ "uhsax\0" + /* 5250 */ "uqsax\0" + /* 5256 */ "ssax\0" + /* 5261 */ "usax\0" + /* 5266 */ "vmladavax\0" + /* 5276 */ "vmlaldavax\0" + /* 5287 */ "vmlsldavax\0" + /* 5298 */ "vmlsdavax\0" + /* 5308 */ "fldmdbx\0" + /* 5316 */ "fstmdbx\0" + /* 5324 */ "vtbx\0" + /* 5329 */ "smladx\0" + /* 5336 */ "smuadx\0" + /* 5343 */ "smlaldx\0" + /* 5351 */ "smlsldx\0" + /* 5359 */ "smlsdx\0" + /* 5366 */ "smusdx\0" + /* 5373 */ "ldaex\0" + /* 5379 */ "stlex\0" + /* 5385 */ "ldrex\0" + /* 5391 */ "clrex\0" + /* 5397 */ "strex\0" + /* 5403 */ "sbfx\0" + /* 5408 */ "ubfx\0" + /* 5413 */ "vqdmladhx\0" + /* 5423 */ "vqrdmladhx\0" + /* 5434 */ "vqdmlsdhx\0" + /* 5444 */ "vqrdmlsdhx\0" + /* 5455 */ "vrmlaldavhx\0" + /* 5467 */ "vrmlsldavhx\0" + /* 5479 */ "blx\0" + /* 5483 */ "bflx\0" + /* 5488 */ "rrx\0" + /* 5492 */ "shasx\0" + /* 5498 */ "uhasx\0" + /* 5504 */ "uqasx\0" + /* 5510 */ "sasx\0" + /* 5515 */ "uasx\0" + /* 5520 */ "vrintx\0" + /* 5527 */ "vmladavx\0" + /* 5536 */ "vmlaldavx\0" + /* 5546 */ "vmlsldavx\0" + /* 5556 */ "vmlsdavx\0" + /* 5565 */ "vclz\0" + /* 5570 */ "vrintz\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2666U, // DBG_VALUE + 2742U, // DBG_VALUE_LIST + 2676U, // DBG_INSTR_REF + 2690U, // DBG_PHI + 2698U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 2659U, // BUNDLE + 2727U, // LIFETIME_START + 2633U, // LIFETIME_END + 2646U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 4016U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 2225U, // PATCHABLE_FUNCTION_ENTER + 2145U, // PATCHABLE_RET + 2271U, // PATCHABLE_FUNCTION_EXIT + 2248U, // PATCHABLE_TAIL_CALL + 2200U, // PATCHABLE_EVENT_CALL + 2176U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABS + 0U, // ADDSri + 0U, // ADDSrr + 0U, // ADDSrsi + 0U, // ADDSrsr + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 12723U, // ASRi + 12723U, // ASRr + 0U, // B + 0U, // BCCZi64 + 0U, // BCCi64 + 0U, // BLX_noip + 0U, // BLX_pred_noip + 0U, // BL_PUSHLR + 0U, // BMOVPCB_CALL + 0U, // BMOVPCRX_CALL + 0U, // BR_JTadd + 0U, // BR_JTm_i12 + 0U, // BR_JTm_rs + 0U, // BR_JTr + 0U, // BX_CALL + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_STRUCT_BYVAL_I32 + 2708U, // CompilerBarrier + 67130025U, // ITasm + 0U, // Int_eh_sjlj_dispatchsetup + 0U, // Int_eh_sjlj_longjmp + 0U, // Int_eh_sjlj_setjmp + 0U, // Int_eh_sjlj_setjmp_nofp + 0U, // Int_eh_sjlj_setup_dispatch + 0U, // JUMPTABLE_ADDRS + 0U, // JUMPTABLE_INSTS + 0U, // JUMPTABLE_TBB + 0U, // JUMPTABLE_TBH + 0U, // LDMIA_RET + 29297U, // LDRBT_POST + 29047U, // LDRConstPool + 29332U, // LDRHTii + 0U, // LDRLIT_ga_abs + 0U, // LDRLIT_ga_pcrel + 0U, // LDRLIT_ga_pcrel_ldr + 29309U, // LDRSBTii + 29344U, // LDRSHTii + 29491U, // LDRT_POST + 0U, // LEApcrel + 0U, // LEApcrelJT + 0U, // LOADDUAL + 12322U, // LSLi + 12322U, // LSLr + 12730U, // LSRi + 12730U, // LSRr + 0U, // MEMCPY + 0U, // MLAv5 + 0U, // MOVCCi + 0U, // MOVCCi16 + 0U, // MOVCCi32imm + 0U, // MOVCCr + 0U, // MOVCCsi + 0U, // MOVCCsr + 0U, // MOVPCRX + 0U, // MOVTi16_ga_pcrel + 0U, // MOV_ga_pcrel + 0U, // MOV_ga_pcrel_ldr + 0U, // MOVi16_ga_pcrel + 0U, // MOVi32imm + 0U, // MOVsra_flag + 0U, // MOVsrl_flag + 0U, // MQPRCopy + 0U, // MQQPRLoad + 0U, // MQQPRStore + 0U, // MQQQQPRLoad + 0U, // MQQQQPRStore + 0U, // MULv5 + 0U, // MVE_MEMCPYLOOPINST + 0U, // MVE_MEMSETLOOPINST + 0U, // MVNCCi + 0U, // PICADD + 0U, // PICLDR + 0U, // PICLDRB + 0U, // PICLDRH + 0U, // PICLDRSB + 0U, // PICLDRSH + 0U, // PICSTR + 0U, // PICSTRB + 0U, // PICSTRH + 12709U, // RORi + 12709U, // RORr + 0U, // RRX + 38257U, // RRXi + 0U, // RSBSri + 0U, // RSBSrsi + 0U, // RSBSrsr + 0U, // SMLALv5 + 0U, // SMULLv5 + 0U, // SPACE + 0U, // STOREDUAL + 29303U, // STRBT_POST + 0U, // STRBi_preidx + 0U, // STRBr_preidx + 0U, // STRH_preidx + 29502U, // STRT_POST + 0U, // STRi_preidx + 0U, // STRr_preidx + 0U, // SUBS_PC_LR + 0U, // SUBSri + 0U, // SUBSrr + 0U, // SUBSrsi + 0U, // SUBSrsr + 0U, // SpeculationBarrierISBDSBEndBB + 0U, // SpeculationBarrierSBEndBB + 0U, // TAILJMPd + 0U, // TAILJMPr + 0U, // TAILJMPr4 + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TPsoft + 0U, // UMLALv5 + 0U, // UMULLv5 + 567551U, // VLD1LNdAsm_16 + 1091839U, // VLD1LNdAsm_32 + 1616127U, // VLD1LNdAsm_8 + 567551U, // VLD1LNdWB_fixed_Asm_16 + 1091839U, // VLD1LNdWB_fixed_Asm_32 + 1616127U, // VLD1LNdWB_fixed_Asm_8 + 575743U, // VLD1LNdWB_register_Asm_16 + 1100031U, // VLD1LNdWB_register_Asm_32 + 1624319U, // VLD1LNdWB_register_Asm_8 + 567600U, // VLD2LNdAsm_16 + 1091888U, // VLD2LNdAsm_32 + 1616176U, // VLD2LNdAsm_8 + 567600U, // VLD2LNdWB_fixed_Asm_16 + 1091888U, // VLD2LNdWB_fixed_Asm_32 + 1616176U, // VLD2LNdWB_fixed_Asm_8 + 575792U, // VLD2LNdWB_register_Asm_16 + 1100080U, // VLD2LNdWB_register_Asm_32 + 1624368U, // VLD2LNdWB_register_Asm_8 + 567600U, // VLD2LNqAsm_16 + 1091888U, // VLD2LNqAsm_32 + 567600U, // VLD2LNqWB_fixed_Asm_16 + 1091888U, // VLD2LNqWB_fixed_Asm_32 + 575792U, // VLD2LNqWB_register_Asm_16 + 1100080U, // VLD2LNqWB_register_Asm_32 + 134801749U, // VLD3DUPdAsm_16 + 135326037U, // VLD3DUPdAsm_32 + 135850325U, // VLD3DUPdAsm_8 + 134801749U, // VLD3DUPdWB_fixed_Asm_16 + 135326037U, // VLD3DUPdWB_fixed_Asm_32 + 135850325U, // VLD3DUPdWB_fixed_Asm_8 + 134785365U, // VLD3DUPdWB_register_Asm_16 + 135309653U, // VLD3DUPdWB_register_Asm_32 + 135833941U, // VLD3DUPdWB_register_Asm_8 + 201910613U, // VLD3DUPqAsm_16 + 202434901U, // VLD3DUPqAsm_32 + 202959189U, // VLD3DUPqAsm_8 + 201910613U, // VLD3DUPqWB_fixed_Asm_16 + 202434901U, // VLD3DUPqWB_fixed_Asm_32 + 202959189U, // VLD3DUPqWB_fixed_Asm_8 + 201894229U, // VLD3DUPqWB_register_Asm_16 + 202418517U, // VLD3DUPqWB_register_Asm_32 + 202942805U, // VLD3DUPqWB_register_Asm_8 + 567637U, // VLD3LNdAsm_16 + 1091925U, // VLD3LNdAsm_32 + 1616213U, // VLD3LNdAsm_8 + 567637U, // VLD3LNdWB_fixed_Asm_16 + 1091925U, // VLD3LNdWB_fixed_Asm_32 + 1616213U, // VLD3LNdWB_fixed_Asm_8 + 575829U, // VLD3LNdWB_register_Asm_16 + 1100117U, // VLD3LNdWB_register_Asm_32 + 1624405U, // VLD3LNdWB_register_Asm_8 + 567637U, // VLD3LNqAsm_16 + 1091925U, // VLD3LNqAsm_32 + 567637U, // VLD3LNqWB_fixed_Asm_16 + 1091925U, // VLD3LNqWB_fixed_Asm_32 + 575829U, // VLD3LNqWB_register_Asm_16 + 1100117U, // VLD3LNqWB_register_Asm_32 + 269019477U, // VLD3dAsm_16 + 269543765U, // VLD3dAsm_32 + 270068053U, // VLD3dAsm_8 + 269019477U, // VLD3dWB_fixed_Asm_16 + 269543765U, // VLD3dWB_fixed_Asm_32 + 270068053U, // VLD3dWB_fixed_Asm_8 + 269003093U, // VLD3dWB_register_Asm_16 + 269527381U, // VLD3dWB_register_Asm_32 + 270051669U, // VLD3dWB_register_Asm_8 + 336128341U, // VLD3qAsm_16 + 336652629U, // VLD3qAsm_32 + 337176917U, // VLD3qAsm_8 + 336128341U, // VLD3qWB_fixed_Asm_16 + 336652629U, // VLD3qWB_fixed_Asm_32 + 337176917U, // VLD3qWB_fixed_Asm_8 + 336111957U, // VLD3qWB_register_Asm_16 + 336636245U, // VLD3qWB_register_Asm_32 + 337160533U, // VLD3qWB_register_Asm_8 + 403237233U, // VLD4DUPdAsm_16 + 403761521U, // VLD4DUPdAsm_32 + 404285809U, // VLD4DUPdAsm_8 + 403237233U, // VLD4DUPdWB_fixed_Asm_16 + 403761521U, // VLD4DUPdWB_fixed_Asm_32 + 404285809U, // VLD4DUPdWB_fixed_Asm_8 + 403220849U, // VLD4DUPdWB_register_Asm_16 + 403745137U, // VLD4DUPdWB_register_Asm_32 + 404269425U, // VLD4DUPdWB_register_Asm_8 + 470346097U, // VLD4DUPqAsm_16 + 470870385U, // VLD4DUPqAsm_32 + 471394673U, // VLD4DUPqAsm_8 + 470346097U, // VLD4DUPqWB_fixed_Asm_16 + 470870385U, // VLD4DUPqWB_fixed_Asm_32 + 471394673U, // VLD4DUPqWB_fixed_Asm_8 + 470329713U, // VLD4DUPqWB_register_Asm_16 + 470854001U, // VLD4DUPqWB_register_Asm_32 + 471378289U, // VLD4DUPqWB_register_Asm_8 + 567665U, // VLD4LNdAsm_16 + 1091953U, // VLD4LNdAsm_32 + 1616241U, // VLD4LNdAsm_8 + 567665U, // VLD4LNdWB_fixed_Asm_16 + 1091953U, // VLD4LNdWB_fixed_Asm_32 + 1616241U, // VLD4LNdWB_fixed_Asm_8 + 575857U, // VLD4LNdWB_register_Asm_16 + 1100145U, // VLD4LNdWB_register_Asm_32 + 1624433U, // VLD4LNdWB_register_Asm_8 + 567665U, // VLD4LNqAsm_16 + 1091953U, // VLD4LNqAsm_32 + 567665U, // VLD4LNqWB_fixed_Asm_16 + 1091953U, // VLD4LNqWB_fixed_Asm_32 + 575857U, // VLD4LNqWB_register_Asm_16 + 1100145U, // VLD4LNqWB_register_Asm_32 + 537454961U, // VLD4dAsm_16 + 537979249U, // VLD4dAsm_32 + 538503537U, // VLD4dAsm_8 + 537454961U, // VLD4dWB_fixed_Asm_16 + 537979249U, // VLD4dWB_fixed_Asm_32 + 538503537U, // VLD4dWB_fixed_Asm_8 + 537438577U, // VLD4dWB_register_Asm_16 + 537962865U, // VLD4dWB_register_Asm_32 + 538487153U, // VLD4dWB_register_Asm_8 + 604563825U, // VLD4qAsm_16 + 605088113U, // VLD4qAsm_32 + 605612401U, // VLD4qAsm_8 + 604563825U, // VLD4qWB_fixed_Asm_16 + 605088113U, // VLD4qWB_fixed_Asm_32 + 605612401U, // VLD4qWB_fixed_Asm_8 + 604547441U, // VLD4qWB_register_Asm_16 + 605071729U, // VLD4qWB_register_Asm_32 + 605596017U, // VLD4qWB_register_Asm_8 + 0U, // VMOVD0 + 0U, // VMOVDcc + 0U, // VMOVHcc + 0U, // VMOVQ0 + 0U, // VMOVScc + 567562U, // VST1LNdAsm_16 + 1091850U, // VST1LNdAsm_32 + 1616138U, // VST1LNdAsm_8 + 567562U, // VST1LNdWB_fixed_Asm_16 + 1091850U, // VST1LNdWB_fixed_Asm_32 + 1616138U, // VST1LNdWB_fixed_Asm_8 + 575754U, // VST1LNdWB_register_Asm_16 + 1100042U, // VST1LNdWB_register_Asm_32 + 1624330U, // VST1LNdWB_register_Asm_8 + 567627U, // VST2LNdAsm_16 + 1091915U, // VST2LNdAsm_32 + 1616203U, // VST2LNdAsm_8 + 567627U, // VST2LNdWB_fixed_Asm_16 + 1091915U, // VST2LNdWB_fixed_Asm_32 + 1616203U, // VST2LNdWB_fixed_Asm_8 + 575819U, // VST2LNdWB_register_Asm_16 + 1100107U, // VST2LNdWB_register_Asm_32 + 1624395U, // VST2LNdWB_register_Asm_8 + 567627U, // VST2LNqAsm_16 + 1091915U, // VST2LNqAsm_32 + 567627U, // VST2LNqWB_fixed_Asm_16 + 1091915U, // VST2LNqWB_fixed_Asm_32 + 575819U, // VST2LNqWB_register_Asm_16 + 1100107U, // VST2LNqWB_register_Asm_32 + 567648U, // VST3LNdAsm_16 + 1091936U, // VST3LNdAsm_32 + 1616224U, // VST3LNdAsm_8 + 567648U, // VST3LNdWB_fixed_Asm_16 + 1091936U, // VST3LNdWB_fixed_Asm_32 + 1616224U, // VST3LNdWB_fixed_Asm_8 + 575840U, // VST3LNdWB_register_Asm_16 + 1100128U, // VST3LNdWB_register_Asm_32 + 1624416U, // VST3LNdWB_register_Asm_8 + 567648U, // VST3LNqAsm_16 + 1091936U, // VST3LNqAsm_32 + 567648U, // VST3LNqWB_fixed_Asm_16 + 1091936U, // VST3LNqWB_fixed_Asm_32 + 575840U, // VST3LNqWB_register_Asm_16 + 1100128U, // VST3LNqWB_register_Asm_32 + 269019488U, // VST3dAsm_16 + 269543776U, // VST3dAsm_32 + 270068064U, // VST3dAsm_8 + 269019488U, // VST3dWB_fixed_Asm_16 + 269543776U, // VST3dWB_fixed_Asm_32 + 270068064U, // VST3dWB_fixed_Asm_8 + 269003104U, // VST3dWB_register_Asm_16 + 269527392U, // VST3dWB_register_Asm_32 + 270051680U, // VST3dWB_register_Asm_8 + 336128352U, // VST3qAsm_16 + 336652640U, // VST3qAsm_32 + 337176928U, // VST3qAsm_8 + 336128352U, // VST3qWB_fixed_Asm_16 + 336652640U, // VST3qWB_fixed_Asm_32 + 337176928U, // VST3qWB_fixed_Asm_8 + 336111968U, // VST3qWB_register_Asm_16 + 336636256U, // VST3qWB_register_Asm_32 + 337160544U, // VST3qWB_register_Asm_8 + 567670U, // VST4LNdAsm_16 + 1091958U, // VST4LNdAsm_32 + 1616246U, // VST4LNdAsm_8 + 567670U, // VST4LNdWB_fixed_Asm_16 + 1091958U, // VST4LNdWB_fixed_Asm_32 + 1616246U, // VST4LNdWB_fixed_Asm_8 + 575862U, // VST4LNdWB_register_Asm_16 + 1100150U, // VST4LNdWB_register_Asm_32 + 1624438U, // VST4LNdWB_register_Asm_8 + 567670U, // VST4LNqAsm_16 + 1091958U, // VST4LNqAsm_32 + 567670U, // VST4LNqWB_fixed_Asm_16 + 1091958U, // VST4LNqWB_fixed_Asm_32 + 575862U, // VST4LNqWB_register_Asm_16 + 1100150U, // VST4LNqWB_register_Asm_32 + 537454966U, // VST4dAsm_16 + 537979254U, // VST4dAsm_32 + 538503542U, // VST4dAsm_8 + 537454966U, // VST4dWB_fixed_Asm_16 + 537979254U, // VST4dWB_fixed_Asm_32 + 538503542U, // VST4dWB_fixed_Asm_8 + 537438582U, // VST4dWB_register_Asm_16 + 537962870U, // VST4dWB_register_Asm_32 + 538487158U, // VST4dWB_register_Asm_8 + 604563830U, // VST4qAsm_16 + 605088118U, // VST4qAsm_32 + 605612406U, // VST4qAsm_8 + 604563830U, // VST4qWB_fixed_Asm_16 + 605088118U, // VST4qWB_fixed_Asm_32 + 605612406U, // VST4qWB_fixed_Asm_8 + 604547446U, // VST4qWB_register_Asm_16 + 605071734U, // VST4qWB_register_Asm_32 + 605596022U, // VST4qWB_register_Asm_8 + 0U, // WIN__CHKSTK + 0U, // WIN__DBZCHK + 0U, // t2ABS + 0U, // t2ADDSri + 0U, // t2ADDSrr + 0U, // t2ADDSrs + 0U, // t2BF_LabelPseudo + 0U, // t2BR_JT + 0U, // t2DoLoopStart + 0U, // t2DoLoopStartTP + 0U, // t2LDMIA_RET + 27784U, // t2LDRBpcrel + 29047U, // t2LDRConstPool + 28292U, // t2LDRHpcrel + 27803U, // t2LDRSBpcrel + 28331U, // t2LDRSHpcrel + 673247607U, // t2LDR_POST_imm + 740356471U, // t2LDR_PRE_imm + 0U, // t2LDRpci_pic + 29047U, // t2LDRpcrel + 0U, // t2LEApcrel + 0U, // t2LEApcrelJT + 0U, // t2LoopDec + 0U, // t2LoopEnd + 0U, // t2LoopEndDec + 0U, // t2MOVCCasr + 0U, // t2MOVCCi + 0U, // t2MOVCCi16 + 0U, // t2MOVCCi32imm + 0U, // t2MOVCClsl + 0U, // t2MOVCClsr + 0U, // t2MOVCCr + 0U, // t2MOVCCror + 62017U, // t2MOVSsi + 45633U, // t2MOVSsr + 0U, // t2MOVTi16_ga_pcrel + 0U, // t2MOV_ga_pcrel + 0U, // t2MOVi16_ga_pcrel + 0U, // t2MOVi32imm + 62486U, // t2MOVsi + 46102U, // t2MOVsr + 0U, // t2MVNCCi + 0U, // t2RSBSri + 0U, // t2RSBSrs + 0U, // t2STRB_preidx + 0U, // t2STRH_preidx + 673247697U, // t2STR_POST_imm + 740356561U, // t2STR_PRE_imm + 0U, // t2STR_preidx + 0U, // t2SUBSri + 0U, // t2SUBSrr + 0U, // t2SUBSrs + 0U, // t2SpeculationBarrierISBDSBEndBB + 0U, // t2SpeculationBarrierSBEndBB + 0U, // t2TBB_JT + 0U, // t2TBH_JT + 0U, // t2WhileLoopSetup + 0U, // t2WhileLoopStart + 0U, // t2WhileLoopStartLR + 0U, // t2WhileLoopStartTP + 0U, // tADCS + 0U, // tADDSi3 + 0U, // tADDSi8 + 0U, // tADDSrr + 0U, // tADDframe + 0U, // tADJCALLSTACKDOWN + 0U, // tADJCALLSTACKUP + 0U, // tBLXNS_CALL + 0U, // tBLXr_noip + 0U, // tBL_PUSHLR + 0U, // tBRIND + 0U, // tBR_JTr + 0U, // tBXNS_RET + 0U, // tBX_CALL + 0U, // tBX_RET + 0U, // tBX_RET_vararg + 0U, // tBfar + 0U, // tCMP_SWAP_16 + 0U, // tCMP_SWAP_8 + 0U, // tLDMIA_UPD + 29047U, // tLDRConstPool + 0U, // tLDRLIT_ga_abs + 0U, // tLDRLIT_ga_pcrel + 0U, // tLDR_postidx + 0U, // tLDRpci_pic + 0U, // tLEApcrel + 0U, // tLEApcrelJT + 0U, // tLSLSri + 0U, // tMOVCCr_pseudo + 0U, // tPOP_RET + 0U, // tRSBS + 0U, // tSBCS + 0U, // tSUBSi3 + 0U, // tSUBSi8 + 0U, // tSUBSrr + 0U, // tTAILJMPd + 0U, // tTAILJMPdND + 0U, // tTAILJMPr + 0U, // tTBB_JT + 0U, // tTBH_JT + 0U, // tTPsoft + 2632984U, // ADCri + 2632984U, // ADCrr + 2690328U, // ADCrsi + 77080U, // ADCrsr + 2633052U, // ADDri + 2633052U, // ADDrr + 2690396U, // ADDrsi + 77148U, // ADDrsr + 2650482U, // ADR + 808535656U, // AESD + 808535664U, // AESE + 875644501U, // AESIMC + 875644511U, // AESMC + 2633117U, // ANDri + 2633117U, // ANDrr + 2690461U, // ANDrsi + 77213U, // ANDrsr + 943285726U, // BF16VDOTI_VDOTD + 943285726U, // BF16VDOTI_VDOTQ + 943285726U, // BF16VDOTS_VDOTD + 943285726U, // BF16VDOTS_VDOTQ + 876639091U, // BF16_VCVT + 809561281U, // BF16_VCVTB + 809562983U, // BF16_VCVTT + 2682144U, // BFC + 2666244U, // BFI + 2632997U, // BICri + 2632997U, // BICrr + 2690341U, // BICrsi + 77093U, // BICrsr + 4802495U, // BKPT + 4802443U, // BL + 4802549U, // BLX + 2725224U, // BLX_pred + 4802549U, // BLXi + 2723669U, // BL_pred + 4802545U, // BX + 2723606U, // BXJ + 5354690U, // BX_RET + 2725058U, // BX_pred + 2722754U, // Bcc + 811188226U, // CDE_CX1 + 1009298118U, // CDE_CX1A + 1080149816U, // CDE_CX1D + 1009298140U, // CDE_CX1DA + 811188819U, // CDE_CX2 + 1009306316U, // CDE_CX2A + 945932094U, // CDE_CX2D + 1009306338U, // CDE_CX2DA + 811188825U, // CDE_CX3 + 1009380050U, // CDE_CX3A + 945932100U, // CDE_CX3D + 1009380072U, // CDE_CX3DA + 1146734294U, // CDE_VCX1A_fpdp + 1146734294U, // CDE_VCX1A_fpsp + 1009388229U, // CDE_VCX1A_vec + 811188225U, // CDE_VCX1_fpdp + 811188225U, // CDE_VCX1_fpsp + 1009395983U, // CDE_VCX1_vec + 1146734301U, // CDE_VCX2A_fpdp + 1146734301U, // CDE_VCX2A_fpsp + 1009404619U, // CDE_VCX2A_vec + 811188818U, // CDE_VCX2_fpdp + 811188818U, // CDE_VCX2_fpsp + 1009387856U, // CDE_VCX2_vec + 1146734308U, // CDE_VCX3A_fpdp + 1146734308U, // CDE_VCX3A_fpsp + 1009412817U, // CDE_VCX3A_vec + 811188824U, // CDE_VCX3_fpdp + 811188824U, // CDE_VCX3_fpsp + 1009404261U, // CDE_VCX3_vec + 1210708236U, // CDP + 1282048575U, // CDP2 + 5392U, // CLREX + 2651583U, // CLZ + 2650277U, // CMNri + 2650277U, // CMNzrr + 2683045U, // CMNzrsi + 2666661U, // CMNzrsr + 2650390U, // CMPri + 2650390U, // CMPrr + 2683158U, // CMPrsi + 2666774U, // CMPrsr + 4802479U, // CPS1p + 1344975398U, // CPS2p + 1344975398U, // CPS3p + 875644665U, // CRC32B + 875644673U, // CRC32CB + 875644783U, // CRC32CH + 875644898U, // CRC32CW + 875644775U, // CRC32H + 875644890U, // CRC32W + 2723330U, // DBG + 182040U, // DMB + 182045U, // DSB + 2634145U, // EORri + 2634145U, // EORrr + 2691489U, // EORrsi + 78241U, // EORrsr + 4829828U, // ERET + 946893845U, // FCONSTD + 7894037U, // FCONSTH + 8418325U, // FCONSTS + 875066557U, // FLDMXDB_UPD + 2724956U, // FLDMXIA + 875066460U, // FLDMXIA_UPD + 9024042U, // FMSTAT + 875066565U, // FSTMXDB_UPD + 2724964U, // FSTMXIA + 875066468U, // FSTMXIA_UPD + 2724569U, // HINT + 4802490U, // HLT + 4802355U, // HVC + 190242U, // ISB + 2648814U, // LDA + 2649023U, // LDAB + 2651390U, // LDAEX + 2649334U, // LDAEXB + 1411935673U, // LDAEXD + 2649820U, // LDAEXH + 2649620U, // LDAH + 1485997949U, // LDC2L_OFFSET + 1553106813U, // LDC2L_OPTION + 1553106813U, // LDC2L_POST + 1620215677U, // LDC2L_PRE + 1485996582U, // LDC2_OFFSET + 1553105446U, // LDC2_OPTION + 1553105446U, // LDC2_POST + 1620214310U, // LDC2_PRE + 1210625886U, // LDCL_OFFSET + 1210625886U, // LDCL_OPTION + 1210625886U, // LDCL_POST + 1210625886U, // LDCL_PRE + 1210625308U, // LDC_OFFSET + 1210625308U, // LDC_OPTION + 1210625308U, // LDC_POST + 1210625308U, // LDC_PRE + 2722546U, // LDMDA + 875064050U, // LDMDA_UPD + 2722801U, // LDMDB + 875064305U, // LDMDB_UPD + 2723919U, // LDMIA + 875065423U, // LDMIA_UPD + 2722820U, // LDMIB + 875064324U, // LDMIB_UPD + 2675313U, // LDRBT_POST_IMM + 2675313U, // LDRBT_POST_REG + 2673800U, // LDRB_POST_IMM + 2673800U, // LDRB_POST_REG + 2665608U, // LDRB_PRE_IMM + 2673800U, // LDRB_PRE_REG + 2681992U, // LDRBi12 + 2665608U, // LDRBrs + 2674082U, // LDRD + 2747810U, // LDRD_POST + 2747810U, // LDRD_PRE + 2651402U, // LDREX + 2649348U, // LDREXB + 1411935687U, // LDREXD + 2649834U, // LDREXH + 2666116U, // LDRH + 2667156U, // LDRHTi + 2675348U, // LDRHTr + 2674308U, // LDRH_POST + 2674308U, // LDRH_PRE + 2665627U, // LDRSB + 2667133U, // LDRSBTi + 2675325U, // LDRSBTr + 2673819U, // LDRSB_POST + 2673819U, // LDRSB_PRE + 2666155U, // LDRSH + 2667168U, // LDRSHTi + 2675360U, // LDRSHTr + 2674347U, // LDRSH_POST + 2674347U, // LDRSH_PRE + 2675507U, // LDRT_POST_IMM + 2675507U, // LDRT_POST_REG + 2675063U, // LDR_POST_IMM + 2675063U, // LDR_POST_REG + 2666871U, // LDR_PRE_IMM + 2675063U, // LDR_PRE_REG + 2683255U, // LDRcp + 2683255U, // LDRi12 + 2666871U, // LDRrs + 1210708334U, // MCR + 812286533U, // MCR2 + 1210634665U, // MCRR + 812286539U, // MCRR2 + 2689842U, // MLA + 2667006U, // MLS + 10073110U, // MOVPCLR + 2683768U, // MOVTi16 + 2659350U, // MOVi + 2651197U, // MOVi16 + 2659350U, // MOVr + 2659350U, // MOVr_TC + 2634774U, // MOVsi + 2692118U, // MOVsr + 1009380659U, // MRC + 943309356U, // MRC2 + 1680395575U, // MRRC + 197170U, // MRRC2 + 2724395U, // MRS + 2650667U, // MRSbanked + 2724395U, // MRSsys + 1747481023U, // MSR + 1814589887U, // MSRbanked + 1747481023U, // MSRi + 2633778U, // MUL + 2674703U, // MVE_ASRLi + 2674703U, // MVE_ASRLr + 875643877U, // MVE_DLSTP_16 + 875643124U, // MVE_DLSTP_32 + 875643486U, // MVE_DLSTP_64 + 875644536U, // MVE_DLSTP_8 + 1076474142U, // MVE_LCTP + 1077503903U, // MVE_LETP + 2674650U, // MVE_LSLLi + 2674650U, // MVE_LSLLr + 2674708U, // MVE_LSRL + 875098491U, // MVE_SQRSHR + 2748409U, // MVE_SQRSHRL + 875097989U, // MVE_SQSHL + 2674622U, // MVE_SQSHLL + 875098498U, // MVE_SRSHR + 2674689U, // MVE_SRSHRL + 875098007U, // MVE_UQRSHL + 2748364U, // MVE_UQRSHLL + 875097995U, // MVE_UQSHL + 2674629U, // MVE_UQSHLL + 875098504U, // MVE_URSHR + 2674696U, // MVE_URSHRL + 10621847U, // MVE_VABAVs16 + 11146135U, // MVE_VABAVs32 + 11670423U, // MVE_VABAVs8 + 12194711U, // MVE_VABAVu16 + 12718999U, // MVE_VABAVu32 + 13243287U, // MVE_VABAVu8 + 8006996U, // MVE_VABDf16 + 8531284U, // MVE_VABDf32 + 10628436U, // MVE_VABDs16 + 11152724U, // MVE_VABDs32 + 11677012U, // MVE_VABDs8 + 12201300U, // MVE_VABDu16 + 12725588U, // MVE_VABDu32 + 13249876U, // MVE_VABDu8 + 8073709U, // MVE_VABSf16 + 8597997U, // MVE_VABSf32 + 10695149U, // MVE_VABSs16 + 11219437U, // MVE_VABSs32 + 11743725U, // MVE_VABSs8 + 13782295U, // MVE_VADC + 13766398U, // MVE_VADCI + 11160497U, // MVE_VADDLVs32acc + 11154424U, // MVE_VADDLVs32no_acc + 12733361U, // MVE_VADDLVu32acc + 12727288U, // MVE_VADDLVu32no_acc + 10628010U, // MVE_VADDVs16acc + 10695647U, // MVE_VADDVs16no_acc + 11152298U, // MVE_VADDVs32acc + 11219935U, // MVE_VADDVs32no_acc + 11676586U, // MVE_VADDVs8acc + 11744223U, // MVE_VADDVs8no_acc + 12200874U, // MVE_VADDVu16acc + 12268511U, // MVE_VADDVu16no_acc + 12725162U, // MVE_VADDVu32acc + 12792799U, // MVE_VADDVu32no_acc + 13249450U, // MVE_VADDVu8acc + 13317087U, // MVE_VADDVu8no_acc + 8007045U, // MVE_VADD_qr_f16 + 8531333U, // MVE_VADD_qr_f32 + 14298501U, // MVE_VADD_qr_i16 + 13774213U, // MVE_VADD_qr_i32 + 14822789U, // MVE_VADD_qr_i8 + 8007045U, // MVE_VADDf16 + 8531333U, // MVE_VADDf32 + 14298501U, // MVE_VADDi16 + 13774213U, // MVE_VADDi32 + 14822789U, // MVE_VADDi8 + 2764188U, // MVE_VAND + 2764068U, // MVE_VBIC + 14298404U, // MVE_VBICimmi16 + 13774116U, // MVE_VBICimmi32 + 668099U, // MVE_VBRSR16 + 1192387U, // MVE_VBRSR32 + 1716675U, // MVE_VBRSR8 + 7998816U, // MVE_VCADDf16 + 8523104U, // MVE_VCADDf32 + 14290272U, // MVE_VCADDi16 + 13765984U, // MVE_VCADDi32 + 14814560U, // MVE_VCADDi8 + 10695159U, // MVE_VCLSs16 + 11219447U, // MVE_VCLSs32 + 11743735U, // MVE_VCLSs8 + 14366142U, // MVE_VCLZs16 + 13841854U, // MVE_VCLZs32 + 14890430U, // MVE_VCLZs8 + 8014640U, // MVE_VCMLAf16 + 8538928U, // MVE_VCMLAf32 + 1887047957U, // MVE_VCMPf16 + 1887047957U, // MVE_VCMPf16r + 1887572245U, // MVE_VCMPf32 + 1887572245U, // MVE_VCMPf32r + 1893339413U, // MVE_VCMPi16 + 1893339413U, // MVE_VCMPi16r + 1892815125U, // MVE_VCMPi32 + 1892815125U, // MVE_VCMPi32r + 1893863701U, // MVE_VCMPi8 + 1893863701U, // MVE_VCMPi8r + 1889669397U, // MVE_VCMPs16 + 1889669397U, // MVE_VCMPs16r + 1890193685U, // MVE_VCMPs32 + 1890193685U, // MVE_VCMPs32r + 1890717973U, // MVE_VCMPs8 + 1890717973U, // MVE_VCMPs8r + 1891242261U, // MVE_VCMPu16 + 1891242261U, // MVE_VCMPu16r + 1891766549U, // MVE_VCMPu32 + 1891766549U, // MVE_VCMPu32r + 1892290837U, // MVE_VCMPu8 + 1892290837U, // MVE_VCMPu8r + 7999536U, // MVE_VCMULf16 + 8523824U, // MVE_VCMULf32 + 873148707U, // MVE_VCTP16 + 873672995U, // MVE_VCTP32 + 887828771U, // MVE_VCTP64 + 874197283U, // MVE_VCTP8 + 821177537U, // MVE_VCVTf16f32bh + 821179239U, // MVE_VCVTf16f32th + 955921267U, // MVE_VCVTf16s16_fix + 1090204531U, // MVE_VCVTf16s16n + 956445555U, // MVE_VCVTf16u16_fix + 1090728819U, // MVE_VCVTf16u16n + 17509569U, // MVE_VCVTf32f16bh + 17511271U, // MVE_VCVTf32f16th + 957494131U, // MVE_VCVTf32s32_fix + 1091777395U, // MVE_VCVTf32s32n + 958018419U, // MVE_VCVTf32u32_fix + 1092301683U, // MVE_VCVTf32u32n + 958542707U, // MVE_VCVTs16f16_fix + 1092823934U, // MVE_VCVTs16f16a + 1092825206U, // MVE_VCVTs16f16m + 1092825302U, // MVE_VCVTs16f16n + 1092825391U, // MVE_VCVTs16f16p + 1092825971U, // MVE_VCVTs16f16z + 959066995U, // MVE_VCVTs32f32_fix + 1093348222U, // MVE_VCVTs32f32a + 1093349494U, // MVE_VCVTs32f32m + 1093349590U, // MVE_VCVTs32f32n + 1093349679U, // MVE_VCVTs32f32p + 1093350259U, // MVE_VCVTs32f32z + 959591283U, // MVE_VCVTu16f16_fix + 1093872510U, // MVE_VCVTu16f16a + 1093873782U, // MVE_VCVTu16f16m + 1093873878U, // MVE_VCVTu16f16n + 1093873967U, // MVE_VCVTu16f16p + 1093874547U, // MVE_VCVTu16f16z + 960115571U, // MVE_VCVTu32f32_fix + 1094396798U, // MVE_VCVTu32f32a + 1094398070U, // MVE_VCVTu32f32m + 1094398166U, // MVE_VCVTu32f32n + 1094398255U, // MVE_VCVTu32f32p + 1094398835U, // MVE_VCVTu32f32z + 12194101U, // MVE_VDDUPu16 + 12718389U, // MVE_VDDUPu32 + 13242677U, // MVE_VDDUPu8 + 733505U, // MVE_VDUP16 + 1257793U, // MVE_VDUP32 + 1782081U, // MVE_VDUP8 + 12210502U, // MVE_VDWDUPu16 + 12734790U, // MVE_VDWDUPu32 + 13259078U, // MVE_VDWDUPu8 + 2765216U, // MVE_VEOR + 7999969U, // MVE_VFMA_qr_Sf16 + 8524257U, // MVE_VFMA_qr_Sf32 + 7998279U, // MVE_VFMA_qr_f16 + 8522567U, // MVE_VFMA_qr_f32 + 7998279U, // MVE_VFMAf16 + 8522567U, // MVE_VFMAf32 + 8000013U, // MVE_VFMSf16 + 8524301U, // MVE_VFMSf32 + 10628467U, // MVE_VHADD_qr_s16 + 11152755U, // MVE_VHADD_qr_s32 + 11677043U, // MVE_VHADD_qr_s8 + 12201331U, // MVE_VHADD_qr_u16 + 12725619U, // MVE_VHADD_qr_u32 + 13249907U, // MVE_VHADD_qr_u8 + 10628467U, // MVE_VHADDs16 + 11152755U, // MVE_VHADDs32 + 11677043U, // MVE_VHADDs8 + 12201331U, // MVE_VHADDu16 + 12725619U, // MVE_VHADDu32 + 13249907U, // MVE_VHADDu8 + 10620249U, // MVE_VHCADDs16 + 11144537U, // MVE_VHCADDs32 + 11668825U, // MVE_VHCADDs8 + 10628311U, // MVE_VHSUB_qr_s16 + 11152599U, // MVE_VHSUB_qr_s32 + 11676887U, // MVE_VHSUB_qr_s8 + 12201175U, // MVE_VHSUB_qr_u16 + 12725463U, // MVE_VHSUB_qr_u32 + 13249751U, // MVE_VHSUB_qr_u8 + 10628311U, // MVE_VHSUBs16 + 11152599U, // MVE_VHSUBs32 + 11676887U, // MVE_VHSUBs8 + 12201175U, // MVE_VHSUBu16 + 12725463U, // MVE_VHSUBu32 + 13249751U, // MVE_VHSUBu8 + 12194107U, // MVE_VIDUPu16 + 12718395U, // MVE_VIDUPu32 + 13242683U, // MVE_VIDUPu8 + 12210509U, // MVE_VIWDUPu16 + 12734797U, // MVE_VIWDUPu32 + 13259085U, // MVE_VIWDUPu8 + 21185389U, // MVE_VLD20_16 + 21709677U, // MVE_VLD20_16_wb + 21184519U, // MVE_VLD20_32 + 21708807U, // MVE_VLD20_32_wb + 21186025U, // MVE_VLD20_8 + 21710313U, // MVE_VLD20_8_wb + 21185429U, // MVE_VLD21_16 + 21709717U, // MVE_VLD21_16_wb + 21184585U, // MVE_VLD21_32 + 21708873U, // MVE_VLD21_32_wb + 21186061U, // MVE_VLD21_8 + 21710349U, // MVE_VLD21_8_wb + 21193601U, // MVE_VLD40_16 + 21717889U, // MVE_VLD40_16_wb + 21192731U, // MVE_VLD40_32 + 21717019U, // MVE_VLD40_32_wb + 21194235U, // MVE_VLD40_8 + 21718523U, // MVE_VLD40_8_wb + 21193641U, // MVE_VLD41_16 + 21717929U, // MVE_VLD41_16_wb + 21192797U, // MVE_VLD41_32 + 21717085U, // MVE_VLD41_32_wb + 21194271U, // MVE_VLD41_8 + 21718559U, // MVE_VLD41_8_wb + 21193661U, // MVE_VLD42_16 + 21717949U, // MVE_VLD42_16_wb + 21192843U, // MVE_VLD42_32 + 21717131U, // MVE_VLD42_32_wb + 21194289U, // MVE_VLD42_8 + 21718577U, // MVE_VLD42_8_wb + 21193681U, // MVE_VLD43_16 + 21717969U, // MVE_VLD43_16_wb + 21192876U, // MVE_VLD43_32 + 21717164U, // MVE_VLD43_32_wb + 21194307U, // MVE_VLD43_8 + 21718595U, // MVE_VLD43_8_wb + 10628231U, // MVE_VLDRBS16 + 883035271U, // MVE_VLDRBS16_post + 883035271U, // MVE_VLDRBS16_pre + 10628231U, // MVE_VLDRBS16_rq + 11152519U, // MVE_VLDRBS32 + 883559559U, // MVE_VLDRBS32_post + 883559559U, // MVE_VLDRBS32_pre + 11152519U, // MVE_VLDRBS32_rq + 12201095U, // MVE_VLDRBU16 + 884608135U, // MVE_VLDRBU16_post + 884608135U, // MVE_VLDRBU16_pre + 12201095U, // MVE_VLDRBU16_rq + 12725383U, // MVE_VLDRBU32 + 885132423U, // MVE_VLDRBU32_post + 885132423U, // MVE_VLDRBU32_pre + 12725383U, // MVE_VLDRBU32_rq + 13249671U, // MVE_VLDRBU8 + 885656711U, // MVE_VLDRBU8_post + 885656711U, // MVE_VLDRBU8_pre + 13249671U, // MVE_VLDRBU8_rq + 22162849U, // MVE_VLDRDU64_qi + 894569889U, // MVE_VLDRDU64_qi_pre + 22162849U, // MVE_VLDRDU64_rq + 22162849U, // MVE_VLDRDU64_rq_u + 11153027U, // MVE_VLDRHS32 + 883560067U, // MVE_VLDRHS32_post + 883560067U, // MVE_VLDRHS32_pre + 11153027U, // MVE_VLDRHS32_rq + 11153027U, // MVE_VLDRHS32_rq_u + 12201603U, // MVE_VLDRHU16 + 884608643U, // MVE_VLDRHU16_post + 884608643U, // MVE_VLDRHU16_pre + 12201603U, // MVE_VLDRHU16_rq + 12201603U, // MVE_VLDRHU16_rq_u + 12725891U, // MVE_VLDRHU32 + 885132931U, // MVE_VLDRHU32_post + 885132931U, // MVE_VLDRHU32_pre + 12725891U, // MVE_VLDRHU32_rq + 12725891U, // MVE_VLDRHU32_rq_u + 12727345U, // MVE_VLDRWU32 + 885134385U, // MVE_VLDRWU32_post + 885134385U, // MVE_VLDRWU32_pre + 12727345U, // MVE_VLDRWU32_qi + 885134385U, // MVE_VLDRWU32_qi_pre + 12727345U, // MVE_VLDRWU32_rq + 12727345U, // MVE_VLDRWU32_rq_u + 883045336U, // MVE_VMAXAVs16 + 883569624U, // MVE_VMAXAVs32 + 884093912U, // MVE_VMAXAVs8 + 10628025U, // MVE_VMAXAs16 + 11152313U, // MVE_VMAXAs32 + 11676601U, // MVE_VMAXAs8 + 880423880U, // MVE_VMAXNMAVf16 + 880948168U, // MVE_VMAXNMAVf32 + 8006490U, // MVE_VMAXNMAf16 + 8530778U, // MVE_VMAXNMAf32 + 880423943U, // MVE_VMAXNMVf16 + 880948231U, // MVE_VMAXNMVf32 + 8007770U, // MVE_VMAXNMf16 + 8532058U, // MVE_VMAXNMf32 + 883045402U, // MVE_VMAXVs16 + 883569690U, // MVE_VMAXVs32 + 884093978U, // MVE_VMAXVs8 + 884618266U, // MVE_VMAXVu16 + 885142554U, // MVE_VMAXVu32 + 885666842U, // MVE_VMAXVu8 + 10630258U, // MVE_VMAXs16 + 11154546U, // MVE_VMAXs32 + 11678834U, // MVE_VMAXs8 + 12203122U, // MVE_VMAXu16 + 12727410U, // MVE_VMAXu32 + 13251698U, // MVE_VMAXu8 + 883045329U, // MVE_VMINAVs16 + 883569617U, // MVE_VMINAVs32 + 884093905U, // MVE_VMINAVs8 + 10627938U, // MVE_VMINAs16 + 11152226U, // MVE_VMINAs32 + 11676514U, // MVE_VMINAs8 + 880423871U, // MVE_VMINNMAVf16 + 880948159U, // MVE_VMINNMAVf32 + 8006482U, // MVE_VMINNMAf16 + 8530770U, // MVE_VMINNMAf32 + 880423935U, // MVE_VMINNMVf16 + 880948223U, // MVE_VMINNMVf32 + 8007763U, // MVE_VMINNMf16 + 8532051U, // MVE_VMINNMf32 + 883045391U, // MVE_VMINVs16 + 883569679U, // MVE_VMINVs32 + 884093967U, // MVE_VMINVs8 + 884618255U, // MVE_VMINVu16 + 885142543U, // MVE_VMINVu32 + 885666831U, // MVE_VMINVu8 + 10629280U, // MVE_VMINs16 + 11153568U, // MVE_VMINs32 + 11677856U, // MVE_VMINs8 + 12202144U, // MVE_VMINu16 + 12726432U, // MVE_VMINu32 + 13250720U, // MVE_VMINu8 + 10619780U, // MVE_VMLADAVas16 + 11144068U, // MVE_VMLADAVas32 + 11668356U, // MVE_VMLADAVas8 + 12192644U, // MVE_VMLADAVau16 + 12716932U, // MVE_VMLADAVau32 + 13241220U, // MVE_VMLADAVau8 + 10622099U, // MVE_VMLADAVaxs16 + 11146387U, // MVE_VMLADAVaxs32 + 11670675U, // MVE_VMLADAVaxs8 + 10630045U, // MVE_VMLADAVs16 + 11154333U, // MVE_VMLADAVs32 + 11678621U, // MVE_VMLADAVs8 + 12202909U, // MVE_VMLADAVu16 + 12727197U, // MVE_VMLADAVu32 + 13251485U, // MVE_VMLADAVu8 + 10630552U, // MVE_VMLADAVxs16 + 11154840U, // MVE_VMLADAVxs32 + 11679128U, // MVE_VMLADAVxs8 + 10644365U, // MVE_VMLALDAVas16 + 11168653U, // MVE_VMLALDAVas32 + 12217229U, // MVE_VMLALDAVau16 + 12741517U, // MVE_VMLALDAVau32 + 10646685U, // MVE_VMLALDAVaxs16 + 11170973U, // MVE_VMLALDAVaxs32 + 10621861U, // MVE_VMLALDAVs16 + 11146149U, // MVE_VMLALDAVs32 + 12194725U, // MVE_VMLALDAVu16 + 12719013U, // MVE_VMLALDAVu32 + 10622369U, // MVE_VMLALDAVxs16 + 11146657U, // MVE_VMLALDAVxs32 + 10621403U, // MVE_VMLAS_qr_s16 + 11145691U, // MVE_VMLAS_qr_s32 + 11669979U, // MVE_VMLAS_qr_s8 + 12194267U, // MVE_VMLAS_qr_u16 + 12718555U, // MVE_VMLAS_qr_u32 + 13242843U, // MVE_VMLAS_qr_u8 + 10619714U, // MVE_VMLA_qr_s16 + 11144002U, // MVE_VMLA_qr_s32 + 11668290U, // MVE_VMLA_qr_s8 + 12192578U, // MVE_VMLA_qr_u16 + 12716866U, // MVE_VMLA_qr_u32 + 13241154U, // MVE_VMLA_qr_u8 + 10619809U, // MVE_VMLSDAVas16 + 11144097U, // MVE_VMLSDAVas32 + 11668385U, // MVE_VMLSDAVas8 + 10622131U, // MVE_VMLSDAVaxs16 + 11146419U, // MVE_VMLSDAVaxs32 + 11670707U, // MVE_VMLSDAVaxs8 + 10630071U, // MVE_VMLSDAVs16 + 11154359U, // MVE_VMLSDAVs32 + 11678647U, // MVE_VMLSDAVs8 + 10630581U, // MVE_VMLSDAVxs16 + 11154869U, // MVE_VMLSDAVxs32 + 11679157U, // MVE_VMLSDAVxs8 + 10644375U, // MVE_VMLSLDAVas16 + 11168663U, // MVE_VMLSLDAVas32 + 10646696U, // MVE_VMLSLDAVaxs16 + 11170984U, // MVE_VMLSLDAVaxs32 + 10621870U, // MVE_VMLSLDAVs16 + 11146158U, // MVE_VMLSLDAVs32 + 10622379U, // MVE_VMLSLDAVxs16 + 11146667U, // MVE_VMLSLDAVxs32 + 10693676U, // MVE_VMOVLs16bh + 10695373U, // MVE_VMOVLs16th + 11742252U, // MVE_VMOVLs8bh + 11743949U, // MVE_VMOVLs8th + 12266540U, // MVE_VMOVLu16bh + 12268237U, // MVE_VMOVLu16th + 13315116U, // MVE_VMOVLu8bh + 13316813U, // MVE_VMOVLu8th + 14298235U, // MVE_VMOVNi16bh + 14299938U, // MVE_VMOVNi16th + 13773947U, // MVE_VMOVNi32bh + 13775650U, // MVE_VMOVNi32th + 1111061U, // MVE_VMOV_from_lane_32 + 10548245U, // MVE_VMOV_from_lane_s16 + 11596821U, // MVE_VMOV_from_lane_s8 + 12121109U, // MVE_VMOV_from_lane_u16 + 13169685U, // MVE_VMOV_from_lane_u8 + 2749461U, // MVE_VMOV_q_rr + 2675733U, // MVE_VMOV_rr_q + 570389U, // MVE_VMOV_to_lane_16 + 1094677U, // MVE_VMOV_to_lane_32 + 1618965U, // MVE_VMOV_to_lane_8 + 8598549U, // MVE_VMOVimmf32 + 14365717U, // MVE_VMOVimmi16 + 13841429U, // MVE_VMOVimmi32 + 1968911381U, // MVE_VMOVimmi64 + 14890005U, // MVE_VMOVimmi8 + 10628733U, // MVE_VMULHs16 + 11153021U, // MVE_VMULHs32 + 11677309U, // MVE_VMULHs8 + 12201597U, // MVE_VMULHu16 + 12725885U, // MVE_VMULHu32 + 13250173U, // MVE_VMULHu8 + 23211040U, // MVE_VMULLBp16 + 23735328U, // MVE_VMULLBp8 + 10628128U, // MVE_VMULLBs16 + 11152416U, // MVE_VMULLBs32 + 11676704U, // MVE_VMULLBs8 + 12200992U, // MVE_VMULLBu16 + 12725280U, // MVE_VMULLBu32 + 13249568U, // MVE_VMULLBu8 + 23212742U, // MVE_VMULLTp16 + 23737030U, // MVE_VMULLTp8 + 10629830U, // MVE_VMULLTs16 + 11154118U, // MVE_VMULLTs32 + 11678406U, // MVE_VMULLTs8 + 12202694U, // MVE_VMULLTu16 + 12726982U, // MVE_VMULLTu32 + 13251270U, // MVE_VMULLTu8 + 8007746U, // MVE_VMUL_qr_f16 + 8532034U, // MVE_VMUL_qr_f32 + 14299202U, // MVE_VMUL_qr_i16 + 13774914U, // MVE_VMUL_qr_i32 + 14823490U, // MVE_VMUL_qr_i8 + 8007746U, // MVE_VMULf16 + 8532034U, // MVE_VMULf32 + 14299202U, // MVE_VMULi16 + 13774914U, // MVE_VMULi32 + 14823490U, // MVE_VMULi8 + 2830581U, // MVE_VMVN + 14364917U, // MVE_VMVNimmi16 + 13840629U, // MVE_VMVNimmi32 + 8072716U, // MVE_VNEGf16 + 8597004U, // MVE_VNEGf32 + 10694156U, // MVE_VNEGs16 + 11218444U, // MVE_VNEGs32 + 11742732U, // MVE_VNEGs8 + 2764997U, // MVE_VORN + 2765230U, // MVE_VORR + 14299566U, // MVE_VORRimmi16 + 13775278U, // MVE_VORRimmi32 + 1076572969U, // MVE_VPNOT + 2764667U, // MVE_VPSEL + 1076597571U, // MVE_VPST + 1893962543U, // MVE_VPTv16i8 + 1893962543U, // MVE_VPTv16i8r + 1890816815U, // MVE_VPTv16s8 + 1890816815U, // MVE_VPTv16s8r + 1892389679U, // MVE_VPTv16u8 + 1892389679U, // MVE_VPTv16u8r + 1887671087U, // MVE_VPTv4f32 + 1887671087U, // MVE_VPTv4f32r + 1892913967U, // MVE_VPTv4i32 + 1892913967U, // MVE_VPTv4i32r + 1890292527U, // MVE_VPTv4s32 + 1890292527U, // MVE_VPTv4s32r + 1891865391U, // MVE_VPTv4u32 + 1891865391U, // MVE_VPTv4u32r + 1887146799U, // MVE_VPTv8f16 + 1887146799U, // MVE_VPTv8f16r + 1893438255U, // MVE_VPTv8i16 + 1893438255U, // MVE_VPTv8i16r + 1889768239U, // MVE_VPTv8s16 + 1889768239U, // MVE_VPTv8s16r + 1891341103U, // MVE_VPTv8u16 + 1891341103U, // MVE_VPTv8u16r + 10695143U, // MVE_VQABSs16 + 11219431U, // MVE_VQABSs32 + 11743719U, // MVE_VQABSs8 + 10628479U, // MVE_VQADD_qr_s16 + 11152767U, // MVE_VQADD_qr_s32 + 11677055U, // MVE_VQADD_qr_s8 + 12201343U, // MVE_VQADD_qr_u16 + 12725631U, // MVE_VQADD_qr_u32 + 13249919U, // MVE_VQADD_qr_u8 + 10628479U, // MVE_VQADDs16 + 11152767U, // MVE_VQADDs32 + 11677055U, // MVE_VQADDs8 + 12201343U, // MVE_VQADDu16 + 12725631U, // MVE_VQADDu32 + 13249919U, // MVE_VQADDu8 + 10622246U, // MVE_VQDMLADHXs16 + 11146534U, // MVE_VQDMLADHXs32 + 11670822U, // MVE_VQDMLADHXs8 + 10620474U, // MVE_VQDMLADHs16 + 11144762U, // MVE_VQDMLADHs32 + 11669050U, // MVE_VQDMLADHs8 + 10620441U, // MVE_VQDMLAH_qrs16 + 11144729U, // MVE_VQDMLAH_qrs32 + 11669017U, // MVE_VQDMLAH_qrs8 + 10620559U, // MVE_VQDMLASH_qrs16 + 11144847U, // MVE_VQDMLASH_qrs32 + 11669135U, // MVE_VQDMLASH_qrs8 + 10622267U, // MVE_VQDMLSDHXs16 + 11146555U, // MVE_VQDMLSDHXs32 + 11670843U, // MVE_VQDMLSDHXs8 + 10620493U, // MVE_VQDMLSDHs16 + 11144781U, // MVE_VQDMLSDHs32 + 11669069U, // MVE_VQDMLSDHs8 + 10628709U, // MVE_VQDMULH_qr_s16 + 11152997U, // MVE_VQDMULH_qr_s32 + 11677285U, // MVE_VQDMULH_qr_s8 + 10628709U, // MVE_VQDMULHi16 + 11152997U, // MVE_VQDMULHi32 + 11677285U, // MVE_VQDMULHi8 + 10628119U, // MVE_VQDMULL_qr_s16bh + 10629821U, // MVE_VQDMULL_qr_s16th + 11152407U, // MVE_VQDMULL_qr_s32bh + 11154109U, // MVE_VQDMULL_qr_s32th + 10628119U, // MVE_VQDMULLs16bh + 10629821U, // MVE_VQDMULLs16th + 11152407U, // MVE_VQDMULLs32bh + 11154109U, // MVE_VQDMULLs32th + 10628211U, // MVE_VQMOVNs16bh + 10629914U, // MVE_VQMOVNs16th + 11152499U, // MVE_VQMOVNs32bh + 11154202U, // MVE_VQMOVNs32th + 12201075U, // MVE_VQMOVNu16bh + 12202778U, // MVE_VQMOVNu16th + 12725363U, // MVE_VQMOVNu32bh + 12727066U, // MVE_VQMOVNu32th + 10628202U, // MVE_VQMOVUNs16bh + 10629905U, // MVE_VQMOVUNs16th + 11152490U, // MVE_VQMOVUNs32bh + 11154193U, // MVE_VQMOVUNs32th + 10694150U, // MVE_VQNEGs16 + 11218438U, // MVE_VQNEGs32 + 11742726U, // MVE_VQNEGs8 + 10622256U, // MVE_VQRDMLADHXs16 + 11146544U, // MVE_VQRDMLADHXs32 + 11670832U, // MVE_VQRDMLADHXs8 + 10620483U, // MVE_VQRDMLADHs16 + 11144771U, // MVE_VQRDMLADHs32 + 11669059U, // MVE_VQRDMLADHs8 + 10620449U, // MVE_VQRDMLAH_qrs16 + 11144737U, // MVE_VQRDMLAH_qrs32 + 11669025U, // MVE_VQRDMLAH_qrs8 + 10620568U, // MVE_VQRDMLASH_qrs16 + 11144856U, // MVE_VQRDMLASH_qrs32 + 11669144U, // MVE_VQRDMLASH_qrs8 + 10622277U, // MVE_VQRDMLSDHXs16 + 11146565U, // MVE_VQRDMLSDHXs32 + 11670853U, // MVE_VQRDMLSDHXs8 + 10620502U, // MVE_VQRDMLSDHs16 + 11144790U, // MVE_VQRDMLSDHs32 + 11669078U, // MVE_VQRDMLSDHs8 + 10628717U, // MVE_VQRDMULH_qr_s16 + 11153005U, // MVE_VQRDMULH_qr_s32 + 11677293U, // MVE_VQRDMULH_qr_s8 + 10628717U, // MVE_VQRDMULHi16 + 11153005U, // MVE_VQRDMULHi32 + 11677293U, // MVE_VQRDMULHi8 + 10629022U, // MVE_VQRSHL_by_vecs16 + 11153310U, // MVE_VQRSHL_by_vecs32 + 11677598U, // MVE_VQRSHL_by_vecs8 + 12201886U, // MVE_VQRSHL_by_vecu16 + 12726174U, // MVE_VQRSHL_by_vecu32 + 13250462U, // MVE_VQRSHL_by_vecu8 + 10629022U, // MVE_VQRSHL_qrs16 + 11153310U, // MVE_VQRSHL_qrs32 + 11677598U, // MVE_VQRSHL_qrs8 + 12201886U, // MVE_VQRSHL_qru16 + 12726174U, // MVE_VQRSHL_qru32 + 13250462U, // MVE_VQRSHL_qru8 + 10619967U, // MVE_VQRSHRNbhs16 + 11144255U, // MVE_VQRSHRNbhs32 + 12192831U, // MVE_VQRSHRNbhu16 + 12717119U, // MVE_VQRSHRNbhu32 + 10621670U, // MVE_VQRSHRNths16 + 11145958U, // MVE_VQRSHRNths32 + 12194534U, // MVE_VQRSHRNthu16 + 12718822U, // MVE_VQRSHRNthu32 + 10620000U, // MVE_VQRSHRUNs16bh + 10621703U, // MVE_VQRSHRUNs16th + 11144288U, // MVE_VQRSHRUNs32bh + 11145991U, // MVE_VQRSHRUNs32th + 10630032U, // MVE_VQSHLU_imms16 + 11154320U, // MVE_VQSHLU_imms32 + 11678608U, // MVE_VQSHLU_imms8 + 10629009U, // MVE_VQSHL_by_vecs16 + 11153297U, // MVE_VQSHL_by_vecs32 + 11677585U, // MVE_VQSHL_by_vecs8 + 12201873U, // MVE_VQSHL_by_vecu16 + 12726161U, // MVE_VQSHL_by_vecu32 + 13250449U, // MVE_VQSHL_by_vecu8 + 10629009U, // MVE_VQSHL_qrs16 + 11153297U, // MVE_VQSHL_qrs32 + 11677585U, // MVE_VQSHL_qrs8 + 12201873U, // MVE_VQSHL_qru16 + 12726161U, // MVE_VQSHL_qru32 + 13250449U, // MVE_VQSHL_qru8 + 10629009U, // MVE_VQSHLimms16 + 11153297U, // MVE_VQSHLimms32 + 11677585U, // MVE_VQSHLimms8 + 12201873U, // MVE_VQSHLimmu16 + 12726161U, // MVE_VQSHLimmu32 + 13250449U, // MVE_VQSHLimmu8 + 10619959U, // MVE_VQSHRNbhs16 + 11144247U, // MVE_VQSHRNbhs32 + 12192823U, // MVE_VQSHRNbhu16 + 12717111U, // MVE_VQSHRNbhu32 + 10621662U, // MVE_VQSHRNths16 + 11145950U, // MVE_VQSHRNths32 + 12194526U, // MVE_VQSHRNthu16 + 12718814U, // MVE_VQSHRNthu32 + 10619991U, // MVE_VQSHRUNs16bh + 10621694U, // MVE_VQSHRUNs16th + 11144279U, // MVE_VQSHRUNs32bh + 11145982U, // MVE_VQSHRUNs32th + 10628317U, // MVE_VQSUB_qr_s16 + 11152605U, // MVE_VQSUB_qr_s32 + 11676893U, // MVE_VQSUB_qr_s8 + 12201181U, // MVE_VQSUB_qr_u16 + 12725469U, // MVE_VQSUB_qr_u32 + 13249757U, // MVE_VQSUB_qr_u8 + 10628317U, // MVE_VQSUBs16 + 11152605U, // MVE_VQSUBs32 + 11676893U, // MVE_VQSUBs8 + 12201181U, // MVE_VQSUBu16 + 12725469U, // MVE_VQSUBu32 + 13249757U, // MVE_VQSUBu8 + 1780211U, // MVE_VREV16_8 + 731412U, // MVE_VREV32_16 + 1779988U, // MVE_VREV32_8 + 731498U, // MVE_VREV64_16 + 1255786U, // MVE_VREV64_32 + 1780074U, // MVE_VREV64_8 + 10628460U, // MVE_VRHADDs16 + 11152748U, // MVE_VRHADDs32 + 11677036U, // MVE_VRHADDs8 + 12201324U, // MVE_VRHADDu16 + 12725612U, // MVE_VRHADDu32 + 13249900U, // MVE_VRHADDu8 + 8072051U, // MVE_VRINTf16A + 8073321U, // MVE_VRINTf16M + 8073423U, // MVE_VRINTf16N + 8073512U, // MVE_VRINTf16P + 8074641U, // MVE_VRINTf16X + 8074691U, // MVE_VRINTf16Z + 8596339U, // MVE_VRINTf32A + 8597609U, // MVE_VRINTf32M + 8597711U, // MVE_VRINTf32N + 8597800U, // MVE_VRINTf32P + 8598929U, // MVE_VRINTf32X + 8598979U, // MVE_VRINTf32Z + 11168510U, // MVE_VRMLALDAVHas32 + 12741374U, // MVE_VRMLALDAVHau32 + 11170882U, // MVE_VRMLALDAVHaxs32 + 11144902U, // MVE_VRMLALDAVHs32 + 12717766U, // MVE_VRMLALDAVHu32 + 11146576U, // MVE_VRMLALDAVHxs32 + 11168522U, // MVE_VRMLSLDAVHas32 + 11170895U, // MVE_VRMLSLDAVHaxs32 + 11144913U, // MVE_VRMLSLDAVHs32 + 11146588U, // MVE_VRMLSLDAVHxs32 + 10628726U, // MVE_VRMULHs16 + 11153014U, // MVE_VRMULHs32 + 11677302U, // MVE_VRMULHs8 + 12201590U, // MVE_VRMULHu16 + 12725878U, // MVE_VRMULHu32 + 13250166U, // MVE_VRMULHu8 + 10629029U, // MVE_VRSHL_by_vecs16 + 11153317U, // MVE_VRSHL_by_vecs32 + 11677605U, // MVE_VRSHL_by_vecs8 + 12201893U, // MVE_VRSHL_by_vecu16 + 12726181U, // MVE_VRSHL_by_vecu32 + 13250469U, // MVE_VRSHL_by_vecu8 + 10629029U, // MVE_VRSHL_qrs16 + 11153317U, // MVE_VRSHL_qrs32 + 11677605U, // MVE_VRSHL_qrs8 + 12201893U, // MVE_VRSHL_qru16 + 12726181U, // MVE_VRSHL_qru32 + 13250469U, // MVE_VRSHL_qru8 + 14289992U, // MVE_VRSHRNi16bh + 14291695U, // MVE_VRSHRNi16th + 13765704U, // MVE_VRSHRNi32bh + 13767407U, // MVE_VRSHRNi32th + 10629518U, // MVE_VRSHR_imms16 + 11153806U, // MVE_VRSHR_imms32 + 11678094U, // MVE_VRSHR_imms8 + 12202382U, // MVE_VRSHR_immu16 + 12726670U, // MVE_VRSHR_immu32 + 13250958U, // MVE_VRSHR_immu8 + 13782290U, // MVE_VSBC + 13766392U, // MVE_VSBCI + 808078633U, // MVE_VSHLC + 10628112U, // MVE_VSHLL_imms16bh + 10629814U, // MVE_VSHLL_imms16th + 11676688U, // MVE_VSHLL_imms8bh + 11678390U, // MVE_VSHLL_imms8th + 12200976U, // MVE_VSHLL_immu16bh + 12202678U, // MVE_VSHLL_immu16th + 13249552U, // MVE_VSHLL_immu8bh + 13251254U, // MVE_VSHLL_immu8th + 10693648U, // MVE_VSHLL_lws16bh + 10695350U, // MVE_VSHLL_lws16th + 11742224U, // MVE_VSHLL_lws8bh + 11743926U, // MVE_VSHLL_lws8th + 12266512U, // MVE_VSHLL_lwu16bh + 12268214U, // MVE_VSHLL_lwu16th + 13315088U, // MVE_VSHLL_lwu8bh + 13316790U, // MVE_VSHLL_lwu8th + 10629035U, // MVE_VSHL_by_vecs16 + 11153323U, // MVE_VSHL_by_vecs32 + 11677611U, // MVE_VSHL_by_vecs8 + 12201899U, // MVE_VSHL_by_vecu16 + 12726187U, // MVE_VSHL_by_vecu32 + 13250475U, // MVE_VSHL_by_vecu8 + 14299051U, // MVE_VSHL_immi16 + 13774763U, // MVE_VSHL_immi32 + 14823339U, // MVE_VSHL_immi8 + 10629035U, // MVE_VSHL_qrs16 + 11153323U, // MVE_VSHL_qrs32 + 11677611U, // MVE_VSHL_qrs8 + 12201899U, // MVE_VSHL_qru16 + 12726187U, // MVE_VSHL_qru32 + 13250475U, // MVE_VSHL_qru8 + 14290000U, // MVE_VSHRNi16bh + 14291703U, // MVE_VSHRNi16th + 13765712U, // MVE_VSHRNi32bh + 13767415U, // MVE_VSHRNi32th + 10629524U, // MVE_VSHR_imms16 + 11153812U, // MVE_VSHR_imms32 + 11678100U, // MVE_VSHR_imms8 + 12202388U, // MVE_VSHR_immu16 + 12726676U, // MVE_VSHR_immu32 + 13250964U, // MVE_VSHR_immu8 + 659212U, // MVE_VSLIimm16 + 1183500U, // MVE_VSLIimm32 + 1707788U, // MVE_VSLIimm8 + 659217U, // MVE_VSRIimm16 + 1183505U, // MVE_VSRIimm32 + 1707793U, // MVE_VSRIimm8 + 24331127U, // MVE_VST20_16 + 238455U, // MVE_VST20_16_wb + 24330257U, // MVE_VST20_32 + 237585U, // MVE_VST20_32_wb + 24331762U, // MVE_VST20_8 + 239090U, // MVE_VST20_8_wb + 24331167U, // MVE_VST21_16 + 238495U, // MVE_VST21_16_wb + 24330323U, // MVE_VST21_32 + 237651U, // MVE_VST21_32_wb + 24331798U, // MVE_VST21_8 + 239126U, // MVE_VST21_8_wb + 24339339U, // MVE_VST40_16 + 246667U, // MVE_VST40_16_wb + 24338469U, // MVE_VST40_32 + 245797U, // MVE_VST40_32_wb + 24339972U, // MVE_VST40_8 + 247300U, // MVE_VST40_8_wb + 24339379U, // MVE_VST41_16 + 246707U, // MVE_VST41_16_wb + 24338535U, // MVE_VST41_32 + 245863U, // MVE_VST41_32_wb + 24340008U, // MVE_VST41_8 + 247336U, // MVE_VST41_8_wb + 24339399U, // MVE_VST42_16 + 246727U, // MVE_VST42_16_wb + 24338581U, // MVE_VST42_32 + 245909U, // MVE_VST42_32_wb + 24340026U, // MVE_VST42_8 + 247354U, // MVE_VST42_8_wb + 24339419U, // MVE_VST43_16 + 246747U, // MVE_VST43_16_wb + 24338614U, // MVE_VST43_32 + 245942U, // MVE_VST43_32_wb + 24340044U, // MVE_VST43_8 + 247372U, // MVE_VST43_8_wb + 666765U, // MVE_VSTRB16 + 873073805U, // MVE_VSTRB16_post + 873073805U, // MVE_VSTRB16_pre + 666765U, // MVE_VSTRB16_rq + 1191053U, // MVE_VSTRB32 + 873598093U, // MVE_VSTRB32_post + 873598093U, // MVE_VSTRB32_pre + 1191053U, // MVE_VSTRB32_rq + 1715341U, // MVE_VSTRB8_rq + 1715341U, // MVE_VSTRBU8 + 874122381U, // MVE_VSTRBU8_post + 874122381U, // MVE_VSTRBU8_pre + 15347111U, // MVE_VSTRD64_qi + 887754151U, // MVE_VSTRD64_qi_pre + 15347111U, // MVE_VSTRD64_rq + 15347111U, // MVE_VSTRD64_rq_u + 667273U, // MVE_VSTRH16_rq + 667273U, // MVE_VSTRH16_rq_u + 1191561U, // MVE_VSTRH32 + 873598601U, // MVE_VSTRH32_post + 873598601U, // MVE_VSTRH32_pre + 1191561U, // MVE_VSTRH32_rq + 1191561U, // MVE_VSTRH32_rq_u + 667273U, // MVE_VSTRHU16 + 873074313U, // MVE_VSTRHU16_post + 873074313U, // MVE_VSTRHU16_pre + 1193015U, // MVE_VSTRW32_qi + 873600055U, // MVE_VSTRW32_qi_pre + 1193015U, // MVE_VSTRW32_rq + 1193015U, // MVE_VSTRW32_rq_u + 1193015U, // MVE_VSTRWU32 + 873600055U, // MVE_VSTRWU32_post + 873600055U, // MVE_VSTRWU32_pre + 8006883U, // MVE_VSUB_qr_f16 + 8531171U, // MVE_VSUB_qr_f32 + 14298339U, // MVE_VSUB_qr_i16 + 13774051U, // MVE_VSUB_qr_i32 + 14822627U, // MVE_VSUB_qr_i8 + 8006883U, // MVE_VSUBf16 + 8531171U, // MVE_VSUBf32 + 14298339U, // MVE_VSUBi16 + 13774051U, // MVE_VSUBi32 + 14822627U, // MVE_VSUBi8 + 875643887U, // MVE_WLSTP_16 + 875643134U, // MVE_WLSTP_32 + 875643496U, // MVE_WLSTP_64 + 875644545U, // MVE_WLSTP_8 + 2658550U, // MVNi + 2658550U, // MVNr + 2633974U, // MVNsi + 2691318U, // MVNsr + 875643322U, // NEON_VMAXNMNDf + 875644217U, // NEON_VMAXNMNDh + 875643322U, // NEON_VMAXNMNQf + 875644217U, // NEON_VMAXNMNQh + 875643310U, // NEON_VMINNMNDf + 875644205U, // NEON_VMINNMNDh + 875643310U, // NEON_VMINNMNQf + 875644205U, // NEON_VMINNMNQh + 2634159U, // ORRri + 2634159U, // ORRrr + 2691503U, // ORRrsi + 78255U, // ORRrsr + 2667100U, // PKHBT + 2665644U, // PKHTB + 255979U, // PLDWi12 + 264171U, // PLDWrs + 255818U, // PLDi12 + 264010U, // PLDrs + 255864U, // PLIi12 + 264056U, // PLIrs + 2682240U, // QADD + 2681296U, // QADD16 + 2681399U, // QADD8 + 2684290U, // QASX + 2682214U, // QDADD + 2682065U, // QDSUB + 2684036U, // QSAX + 2682078U, // QSUB + 2681258U, // QSUB16 + 2681360U, // QSUB8 + 2650791U, // RBIT + 2651109U, // REV + 2648564U, // REV16 + 2649782U, // REVSH + 4802283U, // RFEDA + 24725227U, // RFEDA_UPD + 4802314U, // RFEDB + 24725258U, // RFEDB_UPD + 4802290U, // RFEIA + 24725234U, // RFEIA_UPD + 4802321U, // RFEIB + 24725265U, // RFEIB_UPD + 2632861U, // RSBri + 2632861U, // RSBrr + 2690205U, // RSBrsi + 76957U, // RSBrsr + 2633020U, // RSCri + 2633020U, // RSCrr + 2690364U, // RSCrsi + 77116U, // RSCrsr + 2681303U, // SADD16 + 2681405U, // SADD8 + 2684295U, // SASX + 3220U, // SB + 2632979U, // SBCri + 2632979U, // SBCrr + 2690323U, // SBCrsi + 77075U, // SBCrsr + 2667804U, // SBFX + 2683881U, // SDIV + 2682749U, // SEL + 272207U, // SETEND + 4802455U, // SETPAN + 808534208U, // SHA1C + 875643082U, // SHA1H + 808534240U, // SHA1M + 808534250U, // SHA1P + 808534063U, // SHA1SU0 + 808534129U, // SHA1SU1 + 808534228U, // SHA256H + 808534175U, // SHA256H2 + 808534075U, // SHA256SU0 + 808534141U, // SHA256SU1 + 2681279U, // SHADD16 + 2681384U, // SHADD8 + 2684277U, // SHASX + 2684023U, // SHSAX + 2681241U, // SHSUB16 + 2681345U, // SHSUB8 + 2723119U, // SMC + 2665424U, // SMLABB + 2667093U, // SMLABT + 2665800U, // SMLAD + 2667730U, // SMLADX + 282433U, // SMLAL + 2747351U, // SMLALBB + 2749026U, // SMLALBT + 2747786U, // SMLALD + 2749664U, // SMLALDX + 2747570U, // SMLALTB + 2749268U, // SMLALTT + 2665637U, // SMLATB + 2667341U, // SMLATT + 2665704U, // SMLAWB + 2667389U, // SMLAWT + 2665901U, // SMLSD + 2667760U, // SMLSDX + 2747797U, // SMLSLD + 2749672U, // SMLSLDX + 2665270U, // SMMLA + 2666855U, // SMMLAR + 2667004U, // SMMLS + 2666935U, // SMMLSR + 2682934U, // SMMUL + 2683289U, // SMMULR + 2682190U, // SMUAD + 2684121U, // SMUADX + 2681823U, // SMULBB + 2683498U, // SMULBT + 2691047U, // SMULL + 2682042U, // SMULTB + 2683740U, // SMULTT + 2682095U, // SMULWB + 2683780U, // SMULWT + 2682291U, // SMUSD + 2684151U, // SMUSDX + 4802613U, // SRSDA + 4802565U, // SRSDA_UPD + 4802635U, // SRSDB + 4802589U, // SRSDB_UPD + 4802624U, // SRSIA + 4802577U, // SRSIA_UPD + 4802646U, // SRSIB + 4802601U, // SRSIB_UPD + 2667078U, // SSAT + 2681317U, // SSAT16 + 2684041U, // SSAX + 2681265U, // SSUB16 + 2681366U, // SSUB8 + 1485997956U, // STC2L_OFFSET + 1553106820U, // STC2L_OPTION + 1553106820U, // STC2L_POST + 1620215684U, // STC2L_PRE + 1485996601U, // STC2_OFFSET + 1553105465U, // STC2_OPTION + 1553105465U, // STC2_POST + 1620214329U, // STC2_PRE + 1210625891U, // STCL_OFFSET + 1210625891U, // STCL_OPTION + 1210625891U, // STCL_POST + 1210625891U, // STCL_PRE + 1210625344U, // STC_OFFSET + 1210625344U, // STC_OPTION + 1210625344U, // STC_POST + 1210625344U, // STC_PRE + 2650156U, // STL + 2649127U, // STLB + 2684164U, // STLEX + 2682109U, // STLEXB + 2682304U, // STLEXD + 2682595U, // STLEXH + 2649696U, // STLH + 2722552U, // STMDA + 875064056U, // STMDA_UPD + 2722808U, // STMDB + 875064312U, // STMDB_UPD + 2723954U, // STMIA + 875065458U, // STMIA_UPD + 2722826U, // STMIB + 875064330U, // STMIB_UPD + 875090551U, // STRBT_POST_IMM + 875090551U, // STRBT_POST_REG + 875089038U, // STRB_POST_IMM + 875089038U, // STRB_POST_REG + 875080846U, // STRB_PRE_IMM + 875089038U, // STRB_PRE_REG + 2681998U, // STRBi12 + 2665614U, // STRBrs + 2674088U, // STRD + 875163048U, // STRD_POST + 875163048U, // STRD_PRE + 2684182U, // STREX + 2682123U, // STREXB + 2682318U, // STREXD + 2682609U, // STREXH + 2666122U, // STRH + 875082394U, // STRHTi + 875090586U, // STRHTr + 875089546U, // STRH_POST + 875089546U, // STRH_PRE + 875090750U, // STRT_POST_IMM + 875090750U, // STRT_POST_REG + 875090385U, // STR_POST_IMM + 875090385U, // STR_POST_REG + 875082193U, // STR_PRE_IMM + 875090385U, // STR_PRE_REG + 2683345U, // STRi12 + 2666961U, // STRrs + 2632915U, // SUBri + 2632915U, // SUBrr + 2690259U, // SUBrsi + 77011U, // SUBrsr + 2723140U, // SVC + 2683221U, // SWP + 2681986U, // SWPB + 2665412U, // SXTAB + 2664827U, // SXTAB16 + 2666026U, // SXTAH + 2682055U, // SXTB + 2681227U, // SXTB16 + 2682556U, // SXTH + 2650467U, // TEQri + 2650467U, // TEQrr + 2683235U, // TEQrsi + 2666851U, // TEQrsr + 4359U, // TRAP + 4359U, // TRAPNaCl + 288551U, // TSB + 2650953U, // TSTri + 2650953U, // TSTrr + 2683721U, // TSTrsi + 2667337U, // TSTrsr + 2681310U, // UADD16 + 2681411U, // UADD8 + 2684300U, // UASX + 2667809U, // UBFX + 4802395U, // UDF + 2683886U, // UDIV + 2681287U, // UHADD16 + 2681391U, // UHADD8 + 2684283U, // UHASX + 2684029U, // UHSAX + 2681249U, // UHSUB16 + 2681352U, // UHSUB8 + 2748198U, // UMAAL + 282439U, // UMLAL + 2691053U, // UMULL + 2681295U, // UQADD16 + 2681398U, // UQADD8 + 2684289U, // UQASX + 2684035U, // UQSAX + 2681257U, // UQSUB16 + 2681359U, // UQSUB8 + 2681378U, // USAD8 + 2664954U, // USADA8 + 2667083U, // USAT + 2681324U, // USAT16 + 2684046U, // USAX + 2681272U, // USUB16 + 2681372U, // USUB8 + 2665418U, // UXTAB + 2664835U, // UXTAB16 + 2666032U, // UXTAH + 2682060U, // UXTB + 2681234U, // UXTB16 + 2682561U, // UXTH + 11054892U, // VABALsv2i64 + 10530604U, // VABALsv4i32 + 11579180U, // VABALsv8i16 + 12627756U, // VABALuv2i64 + 12103468U, // VABALuv4i32 + 13152044U, // VABALuv8i16 + 11578071U, // VABAsv16i8 + 11053783U, // VABAsv2i32 + 10529495U, // VABAsv4i16 + 11053783U, // VABAsv4i32 + 10529495U, // VABAsv8i16 + 11578071U, // VABAsv8i8 + 13150935U, // VABAuv16i8 + 12626647U, // VABAuv2i32 + 12102359U, // VABAuv4i16 + 12626647U, // VABAuv4i32 + 12102359U, // VABAuv8i16 + 13150935U, // VABAuv8i8 + 11071336U, // VABDLsv2i64 + 10547048U, // VABDLsv4i32 + 11595624U, // VABDLsv8i16 + 12644200U, // VABDLuv2i64 + 12119912U, // VABDLuv4i32 + 13168488U, // VABDLuv8i16 + 8449364U, // VABDfd + 8449364U, // VABDfq + 7925076U, // VABDhd + 7925076U, // VABDhq + 11595092U, // VABDsv16i8 + 11070804U, // VABDsv2i32 + 10546516U, // VABDsv4i16 + 11070804U, // VABDsv4i32 + 10546516U, // VABDsv8i16 + 11595092U, // VABDsv8i8 + 13167956U, // VABDuv16i8 + 12643668U, // VABDuv2i32 + 12119380U, // VABDuv4i16 + 12643668U, // VABDuv4i32 + 12119380U, // VABDuv8i16 + 13167956U, // VABDuv8i8 + 946893293U, // VABSD + 7893485U, // VABSH + 8417773U, // VABSS + 8417773U, // VABSfd + 8417773U, // VABSfq + 7893485U, // VABShd + 7893485U, // VABShq + 11563501U, // VABSv16i8 + 11039213U, // VABSv2i32 + 10514925U, // VABSv4i16 + 11039213U, // VABSv4i32 + 10514925U, // VABSv8i16 + 11563501U, // VABSv8i8 + 8449493U, // VACGEfd + 8449493U, // VACGEfq + 7925205U, // VACGEhd + 7925205U, // VACGEhq + 8450697U, // VACGTfd + 8450697U, // VACGTfq + 7926409U, // VACGThd + 7926409U, // VACGThq + 946924933U, // VADDD + 7925125U, // VADDH + 895021203U, // VADDHNv2i32 + 13693075U, // VADDHNv4i16 + 14217363U, // VADDHNv8i8 + 11071349U, // VADDLsv2i64 + 10547061U, // VADDLsv4i32 + 11595637U, // VADDLsv8i16 + 12644213U, // VADDLuv2i64 + 12119925U, // VADDLuv4i32 + 13168501U, // VADDLuv8i16 + 8449413U, // VADDS + 11072550U, // VADDWsv2i64 + 10548262U, // VADDWsv4i32 + 11596838U, // VADDWsv8i16 + 12645414U, // VADDWuv2i64 + 12121126U, // VADDWuv4i32 + 13169702U, // VADDWuv8i16 + 8449413U, // VADDfd + 8449413U, // VADDfq + 7925125U, // VADDhd + 7925125U, // VADDhq + 14740869U, // VADDv16i8 + 895020421U, // VADDv1i64 + 13692293U, // VADDv2i32 + 895020421U, // VADDv2i64 + 14216581U, // VADDv4i16 + 13692293U, // VADDv4i32 + 14216581U, // VADDv8i16 + 14740869U, // VADDv8i8 + 2682268U, // VANDd + 2682268U, // VANDq + 943285702U, // VBF16MALBQ + 943285702U, // VBF16MALBQI + 943285714U, // VBF16MALTQ + 943285714U, // VBF16MALTQI + 2682148U, // VBICd + 13692196U, // VBICiv2i32 + 14216484U, // VBICiv4i16 + 13692196U, // VBICiv4i32 + 14216484U, // VBICiv8i16 + 2682148U, // VBICq + 2665981U, // VBIFd + 2665981U, // VBIFq + 2667180U, // VBITd + 2667180U, // VBITq + 2666521U, // VBSLd + 2666521U, // VBSLq + 0U, // VBSPd + 0U, // VBSPq + 875643287U, // VCADDv2f32 + 875644160U, // VCADDv4f16 + 875643287U, // VCADDv4f32 + 875644160U, // VCADDv8f16 + 8450398U, // VCEQfd + 8450398U, // VCEQfq + 7926110U, // VCEQhd + 7926110U, // VCEQhq + 14741854U, // VCEQv16i8 + 13693278U, // VCEQv2i32 + 14217566U, // VCEQv4i16 + 13693278U, // VCEQv4i32 + 14217566U, // VCEQv8i16 + 14741854U, // VCEQv8i8 + 14709086U, // VCEQzv16i8 + 8417630U, // VCEQzv2f32 + 13660510U, // VCEQzv2i32 + 7893342U, // VCEQzv4f16 + 8417630U, // VCEQzv4f32 + 14184798U, // VCEQzv4i16 + 13660510U, // VCEQzv4i32 + 7893342U, // VCEQzv8f16 + 14184798U, // VCEQzv8i16 + 14709086U, // VCEQzv8i8 + 8449499U, // VCGEfd + 8449499U, // VCGEfq + 7925211U, // VCGEhd + 7925211U, // VCGEhq + 11595227U, // VCGEsv16i8 + 11070939U, // VCGEsv2i32 + 10546651U, // VCGEsv4i16 + 11070939U, // VCGEsv4i32 + 10546651U, // VCGEsv8i16 + 11595227U, // VCGEsv8i8 + 13168091U, // VCGEuv16i8 + 12643803U, // VCGEuv2i32 + 12119515U, // VCGEuv4i16 + 12643803U, // VCGEuv4i32 + 12119515U, // VCGEuv8i16 + 13168091U, // VCGEuv8i8 + 11562459U, // VCGEzv16i8 + 8416731U, // VCGEzv2f32 + 11038171U, // VCGEzv2i32 + 7892443U, // VCGEzv4f16 + 8416731U, // VCGEzv4f32 + 10513883U, // VCGEzv4i16 + 11038171U, // VCGEzv4i32 + 7892443U, // VCGEzv8f16 + 10513883U, // VCGEzv8i16 + 11562459U, // VCGEzv8i8 + 8450703U, // VCGTfd + 8450703U, // VCGTfq + 7926415U, // VCGThd + 7926415U, // VCGThq + 11596431U, // VCGTsv16i8 + 11072143U, // VCGTsv2i32 + 10547855U, // VCGTsv4i16 + 11072143U, // VCGTsv4i32 + 10547855U, // VCGTsv8i16 + 11596431U, // VCGTsv8i8 + 13169295U, // VCGTuv16i8 + 12645007U, // VCGTuv2i32 + 12120719U, // VCGTuv4i16 + 12645007U, // VCGTuv4i32 + 12120719U, // VCGTuv8i16 + 13169295U, // VCGTuv8i8 + 11563663U, // VCGTzv16i8 + 8417935U, // VCGTzv2f32 + 11039375U, // VCGTzv2i32 + 7893647U, // VCGTzv4f16 + 8417935U, // VCGTzv4f32 + 10515087U, // VCGTzv4i16 + 11039375U, // VCGTzv4i32 + 7893647U, // VCGTzv8f16 + 10515087U, // VCGTzv8i16 + 11563663U, // VCGTzv8i8 + 11562464U, // VCLEzv16i8 + 8416736U, // VCLEzv2f32 + 11038176U, // VCLEzv2i32 + 7892448U, // VCLEzv4f16 + 8416736U, // VCLEzv4f32 + 10513888U, // VCLEzv4i16 + 11038176U, // VCLEzv4i32 + 7892448U, // VCLEzv8f16 + 10513888U, // VCLEzv8i16 + 11562464U, // VCLEzv8i8 + 11563511U, // VCLSv16i8 + 11039223U, // VCLSv2i32 + 10514935U, // VCLSv4i16 + 11039223U, // VCLSv4i32 + 10514935U, // VCLSv8i16 + 11563511U, // VCLSv8i8 + 11563697U, // VCLTzv16i8 + 8417969U, // VCLTzv2f32 + 11039409U, // VCLTzv2i32 + 7893681U, // VCLTzv4f16 + 8417969U, // VCLTzv4f32 + 10515121U, // VCLTzv4i16 + 11039409U, // VCLTzv4i32 + 7893681U, // VCLTzv8f16 + 10515121U, // VCLTzv8i16 + 11563697U, // VCLTzv8i8 + 14710206U, // VCLZv16i8 + 13661630U, // VCLZv2i32 + 14185918U, // VCLZv4i16 + 13661630U, // VCLZv4i32 + 14185918U, // VCLZv8i16 + 14710206U, // VCLZv8i8 + 808534400U, // VCMLAv2f32 + 808534400U, // VCMLAv2f32_indexed + 808535273U, // VCMLAv4f16 + 808535273U, // VCMLAv4f16_indexed + 808534400U, // VCMLAv4f32 + 808534400U, // VCMLAv4f32_indexed + 808535273U, // VCMLAv8f16 + 808535273U, // VCMLAv8f16_indexed + 946893077U, // VCMPD + 946892268U, // VCMPED + 7892460U, // VCMPEH + 8416748U, // VCMPES + 2020707820U, // VCMPEZD + 7966188U, // VCMPEZH + 8490476U, // VCMPEZS + 7893269U, // VCMPH + 8417557U, // VCMPS + 2020708629U, // VCMPZD + 7966997U, // VCMPZH + 8491285U, // VCMPZS + 1602260U, // VCNTd + 1602260U, // VCNTq + 875643144U, // VCVTANSDf + 875644017U, // VCVTANSDh + 875643144U, // VCVTANSQf + 875644017U, // VCVTANSQh + 875643204U, // VCVTANUDf + 875644077U, // VCVTANUDh + 875643204U, // VCVTANUQf + 875644077U, // VCVTANUQh + 875643506U, // VCVTASD + 875643897U, // VCVTASH + 875643144U, // VCVTASS + 875643566U, // VCVTAUD + 875643957U, // VCVTAUH + 875643204U, // VCVTAUS + 25193665U, // VCVTBDH + 25717953U, // VCVTBHD + 17329345U, // VCVTBHS + 888171713U, // VCVTBSH + 26243955U, // VCVTDS + 875643159U, // VCVTMNSDf + 875644032U, // VCVTMNSDh + 875643159U, // VCVTMNSQf + 875644032U, // VCVTMNSQh + 875643219U, // VCVTMNUDf + 875644092U, // VCVTMNUDh + 875643219U, // VCVTMNUQf + 875644092U, // VCVTMNUQh + 875643521U, // VCVTMSD + 875643912U, // VCVTMSH + 875643159U, // VCVTMSS + 875643581U, // VCVTMUD + 875643972U, // VCVTMUH + 875643219U, // VCVTMUS + 875643174U, // VCVTNNSDf + 875644047U, // VCVTNNSDh + 875643174U, // VCVTNNSQf + 875644047U, // VCVTNNSQh + 875643234U, // VCVTNNUDf + 875644107U, // VCVTNNUDh + 875643234U, // VCVTNNUQf + 875644107U, // VCVTNNUQh + 875643536U, // VCVTNSD + 875643927U, // VCVTNSH + 875643174U, // VCVTNSS + 875643596U, // VCVTNUD + 875643987U, // VCVTNUH + 875643234U, // VCVTNUS + 875643189U, // VCVTPNSDf + 875644062U, // VCVTPNSDh + 875643189U, // VCVTPNSQf + 875644062U, // VCVTPNSQh + 875643249U, // VCVTPNUDf + 875644122U, // VCVTPNUDh + 875643249U, // VCVTPNUQf + 875644122U, // VCVTPNUQh + 875643551U, // VCVTPSD + 875643942U, // VCVTPSH + 875643189U, // VCVTPSS + 875643611U, // VCVTPUD + 875644002U, // VCVTPUH + 875643249U, // VCVTPUS + 26768243U, // VCVTSD + 25195367U, // VCVTTDH + 25719655U, // VCVTTHD + 17331047U, // VCVTTHS + 888173415U, // VCVTTSH + 888173427U, // VCVTf2h + 1093170035U, // VCVTf2sd + 1093170035U, // VCVTf2sq + 1094218611U, // VCVTf2ud + 1094218611U, // VCVTf2uq + 958985075U, // VCVTf2xsd + 958985075U, // VCVTf2xsq + 960033651U, // VCVTf2xud + 960033651U, // VCVTf2xuq + 17331059U, // VCVTh2f + 1092645747U, // VCVTh2sd + 1092645747U, // VCVTh2sq + 1093694323U, // VCVTh2ud + 1093694323U, // VCVTh2uq + 958460787U, // VCVTh2xsd + 958460787U, // VCVTh2xsq + 959509363U, // VCVTh2xud + 959509363U, // VCVTh2xuq + 1091597171U, // VCVTs2fd + 1091597171U, // VCVTs2fq + 1090024307U, // VCVTs2hd + 1090024307U, // VCVTs2hq + 1092121459U, // VCVTu2fd + 1092121459U, // VCVTu2fq + 1090548595U, // VCVTu2hd + 1090548595U, // VCVTu2hq + 957412211U, // VCVTxs2fd + 957412211U, // VCVTxs2fq + 955839347U, // VCVTxs2hd + 955839347U, // VCVTxs2hq + 957936499U, // VCVTxu2fd + 957936499U, // VCVTxu2fq + 956363635U, // VCVTxu2hd + 956363635U, // VCVTxu2hq + 946926579U, // VDIVD + 7926771U, // VDIVH + 8451059U, // VDIVS + 553281U, // VDUP16d + 553281U, // VDUP16q + 1077569U, // VDUP32d + 1077569U, // VDUP32q + 1601857U, // VDUP8d + 1601857U, // VDUP8q + 586049U, // VDUPLN16d + 586049U, // VDUPLN16q + 1110337U, // VDUPLN32d + 1110337U, // VDUPLN32q + 1634625U, // VDUPLN8d + 1634625U, // VDUPLN8q + 2683296U, // VEORd + 2683296U, // VEORq + 570251U, // VEXTd16 + 1094539U, // VEXTd32 + 1618827U, // VEXTd8 + 570251U, // VEXTq16 + 1094539U, // VEXTq32 + 15250315U, // VEXTq64 + 1618827U, // VEXTq8 + 946907975U, // VFMAD + 7908167U, // VFMAH + 875644183U, // VFMALD + 875644183U, // VFMALDI + 875644183U, // VFMALQ + 875644183U, // VFMALQI + 8432455U, // VFMAS + 8432455U, // VFMAfd + 8432455U, // VFMAfq + 7908167U, // VFMAhd + 7908167U, // VFMAhq + 946909709U, // VFMSD + 7909901U, // VFMSH + 875644194U, // VFMSLD + 875644194U, // VFMSLDI + 875644194U, // VFMSLQ + 875644194U, // VFMSLQI + 8434189U, // VFMSS + 8434189U, // VFMSfd + 8434189U, // VFMSfq + 7909901U, // VFMShd + 7909901U, // VFMShq + 946907980U, // VFNMAD + 7908172U, // VFNMAH + 8432460U, // VFNMAS + 946909714U, // VFNMSD + 7909906U, // VFNMSH + 8434194U, // VFNMSS + 875643662U, // VFP_VMAXNMD + 875644217U, // VFP_VMAXNMH + 875643322U, // VFP_VMAXNMS + 875643650U, // VFP_VMINNMD + 875644205U, // VFP_VMINNMH + 875643310U, // VFP_VMINNMS + 1111061U, // VGETLNi32 + 10548245U, // VGETLNs16 + 11596821U, // VGETLNs8 + 12121109U, // VGETLNu16 + 13169685U, // VGETLNu8 + 11595123U, // VHADDsv16i8 + 11070835U, // VHADDsv2i32 + 10546547U, // VHADDsv4i16 + 11070835U, // VHADDsv4i32 + 10546547U, // VHADDsv8i16 + 11595123U, // VHADDsv8i8 + 13167987U, // VHADDuv16i8 + 12643699U, // VHADDuv2i32 + 12119411U, // VHADDuv4i16 + 12643699U, // VHADDuv4i32 + 12119411U, // VHADDuv8i16 + 13167987U, // VHADDuv8i8 + 11594967U, // VHSUBsv16i8 + 11070679U, // VHSUBsv2i32 + 10546391U, // VHSUBsv4i16 + 11070679U, // VHSUBsv4i32 + 10546391U, // VHSUBsv8i16 + 11594967U, // VHSUBsv8i8 + 13167831U, // VHSUBuv16i8 + 12643543U, // VHSUBuv2i32 + 12119255U, // VHSUBuv4i16 + 12643543U, // VHSUBuv4i32 + 12119255U, // VHSUBuv8i16 + 13167831U, // VHSUBuv8i8 + 808535413U, // VINSH + 1101034349U, // VJCVT + 2080958719U, // VLD1DUPd16 + 2080942335U, // VLD1DUPd16wb_fixed + 2080950527U, // VLD1DUPd16wb_register + 2081483007U, // VLD1DUPd32 + 2081466623U, // VLD1DUPd32wb_fixed + 2081474815U, // VLD1DUPd32wb_register + 2082007295U, // VLD1DUPd8 + 2081990911U, // VLD1DUPd8wb_fixed + 2081999103U, // VLD1DUPd8wb_register + 2148067583U, // VLD1DUPq16 + 2148051199U, // VLD1DUPq16wb_fixed + 2148059391U, // VLD1DUPq16wb_register + 2148591871U, // VLD1DUPq32 + 2148575487U, // VLD1DUPq32wb_fixed + 2148583679U, // VLD1DUPq32wb_register + 2149116159U, // VLD1DUPq8 + 2149099775U, // VLD1DUPq8wb_fixed + 2149107967U, // VLD1DUPq8wb_register + 27838719U, // VLD1LNd16 + 28084479U, // VLD1LNd16_UPD + 28363007U, // VLD1LNd32 + 28608767U, // VLD1LNd32_UPD + 28887295U, // VLD1LNd8 + 29133055U, // VLD1LNd8_UPD + 0U, // VLD1LNq16Pseudo + 0U, // VLD1LNq16Pseudo_UPD + 0U, // VLD1LNq32Pseudo + 0U, // VLD1LNq32Pseudo_UPD + 0U, // VLD1LNq8Pseudo + 0U, // VLD1LNq8Pseudo_UPD + 2215176447U, // VLD1d16 + 537454847U, // VLD1d16Q + 0U, // VLD1d16QPseudo + 0U, // VLD1d16QPseudoWB_fixed + 0U, // VLD1d16QPseudoWB_register + 537438463U, // VLD1d16Qwb_fixed + 537446655U, // VLD1d16Qwb_register + 269019391U, // VLD1d16T + 0U, // VLD1d16TPseudo + 0U, // VLD1d16TPseudoWB_fixed + 0U, // VLD1d16TPseudoWB_register + 269003007U, // VLD1d16Twb_fixed + 269011199U, // VLD1d16Twb_register + 2215160063U, // VLD1d16wb_fixed + 2215168255U, // VLD1d16wb_register + 2215700735U, // VLD1d32 + 537979135U, // VLD1d32Q + 0U, // VLD1d32QPseudo + 0U, // VLD1d32QPseudoWB_fixed + 0U, // VLD1d32QPseudoWB_register + 537962751U, // VLD1d32Qwb_fixed + 537970943U, // VLD1d32Qwb_register + 269543679U, // VLD1d32T + 0U, // VLD1d32TPseudo + 0U, // VLD1d32TPseudoWB_fixed + 0U, // VLD1d32TPseudoWB_register + 269527295U, // VLD1d32Twb_fixed + 269535487U, // VLD1d32Twb_register + 2215684351U, // VLD1d32wb_fixed + 2215692543U, // VLD1d32wb_register + 2229856511U, // VLD1d64 + 552134911U, // VLD1d64Q + 0U, // VLD1d64QPseudo + 0U, // VLD1d64QPseudoWB_fixed + 0U, // VLD1d64QPseudoWB_register + 552118527U, // VLD1d64Qwb_fixed + 552126719U, // VLD1d64Qwb_register + 283699455U, // VLD1d64T + 0U, // VLD1d64TPseudo + 0U, // VLD1d64TPseudoWB_fixed + 0U, // VLD1d64TPseudoWB_register + 283683071U, // VLD1d64Twb_fixed + 283691263U, // VLD1d64Twb_register + 2229840127U, // VLD1d64wb_fixed + 2229848319U, // VLD1d64wb_register + 2216225023U, // VLD1d8 + 538503423U, // VLD1d8Q + 0U, // VLD1d8QPseudo + 0U, // VLD1d8QPseudoWB_fixed + 0U, // VLD1d8QPseudoWB_register + 538487039U, // VLD1d8Qwb_fixed + 538495231U, // VLD1d8Qwb_register + 270067967U, // VLD1d8T + 0U, // VLD1d8TPseudo + 0U, // VLD1d8TPseudoWB_fixed + 0U, // VLD1d8TPseudoWB_register + 270051583U, // VLD1d8Twb_fixed + 270059775U, // VLD1d8Twb_register + 2216208639U, // VLD1d8wb_fixed + 2216216831U, // VLD1d8wb_register + 2282285311U, // VLD1q16 + 0U, // VLD1q16HighQPseudo + 0U, // VLD1q16HighQPseudo_UPD + 0U, // VLD1q16HighTPseudo + 0U, // VLD1q16HighTPseudo_UPD + 0U, // VLD1q16LowQPseudo_UPD + 0U, // VLD1q16LowTPseudo_UPD + 2282268927U, // VLD1q16wb_fixed + 2282277119U, // VLD1q16wb_register + 2282809599U, // VLD1q32 + 0U, // VLD1q32HighQPseudo + 0U, // VLD1q32HighQPseudo_UPD + 0U, // VLD1q32HighTPseudo + 0U, // VLD1q32HighTPseudo_UPD + 0U, // VLD1q32LowQPseudo_UPD + 0U, // VLD1q32LowTPseudo_UPD + 2282793215U, // VLD1q32wb_fixed + 2282801407U, // VLD1q32wb_register + 2296965375U, // VLD1q64 + 0U, // VLD1q64HighQPseudo + 0U, // VLD1q64HighQPseudo_UPD + 0U, // VLD1q64HighTPseudo + 0U, // VLD1q64HighTPseudo_UPD + 0U, // VLD1q64LowQPseudo_UPD + 0U, // VLD1q64LowTPseudo_UPD + 2296948991U, // VLD1q64wb_fixed + 2296957183U, // VLD1q64wb_register + 2283333887U, // VLD1q8 + 0U, // VLD1q8HighQPseudo + 0U, // VLD1q8HighQPseudo_UPD + 0U, // VLD1q8HighTPseudo + 0U, // VLD1q8HighTPseudo_UPD + 0U, // VLD1q8LowQPseudo_UPD + 0U, // VLD1q8LowTPseudo_UPD + 2283317503U, // VLD1q8wb_fixed + 2283325695U, // VLD1q8wb_register + 2148067632U, // VLD2DUPd16 + 2148051248U, // VLD2DUPd16wb_fixed + 2148059440U, // VLD2DUPd16wb_register + 2349394224U, // VLD2DUPd16x2 + 2349377840U, // VLD2DUPd16x2wb_fixed + 2349386032U, // VLD2DUPd16x2wb_register + 2148591920U, // VLD2DUPd32 + 2148575536U, // VLD2DUPd32wb_fixed + 2148583728U, // VLD2DUPd32wb_register + 2349918512U, // VLD2DUPd32x2 + 2349902128U, // VLD2DUPd32x2wb_fixed + 2349910320U, // VLD2DUPd32x2wb_register + 2149116208U, // VLD2DUPd8 + 2149099824U, // VLD2DUPd8wb_fixed + 2149108016U, // VLD2DUPd8wb_register + 2350442800U, // VLD2DUPd8x2 + 2350426416U, // VLD2DUPd8x2wb_fixed + 2350434608U, // VLD2DUPd8x2wb_register + 0U, // VLD2DUPq16EvenPseudo + 0U, // VLD2DUPq16OddPseudo + 0U, // VLD2DUPq16OddPseudoWB_fixed + 0U, // VLD2DUPq16OddPseudoWB_register + 0U, // VLD2DUPq32EvenPseudo + 0U, // VLD2DUPq32OddPseudo + 0U, // VLD2DUPq32OddPseudoWB_fixed + 0U, // VLD2DUPq32OddPseudoWB_register + 0U, // VLD2DUPq8EvenPseudo + 0U, // VLD2DUPq8OddPseudo + 0U, // VLD2DUPq8OddPseudoWB_fixed + 0U, // VLD2DUPq8OddPseudoWB_register + 28084528U, // VLD2LNd16 + 0U, // VLD2LNd16Pseudo + 0U, // VLD2LNd16Pseudo_UPD + 28092720U, // VLD2LNd16_UPD + 28608816U, // VLD2LNd32 + 0U, // VLD2LNd32Pseudo + 0U, // VLD2LNd32Pseudo_UPD + 28617008U, // VLD2LNd32_UPD + 29133104U, // VLD2LNd8 + 0U, // VLD2LNd8Pseudo + 0U, // VLD2LNd8Pseudo_UPD + 29141296U, // VLD2LNd8_UPD + 28084528U, // VLD2LNq16 + 0U, // VLD2LNq16Pseudo + 0U, // VLD2LNq16Pseudo_UPD + 28092720U, // VLD2LNq16_UPD + 28608816U, // VLD2LNq32 + 0U, // VLD2LNq32Pseudo + 0U, // VLD2LNq32Pseudo_UPD + 28617008U, // VLD2LNq32_UPD + 2416503088U, // VLD2b16 + 2416486704U, // VLD2b16wb_fixed + 2416494896U, // VLD2b16wb_register + 2417027376U, // VLD2b32 + 2417010992U, // VLD2b32wb_fixed + 2417019184U, // VLD2b32wb_register + 2417551664U, // VLD2b8 + 2417535280U, // VLD2b8wb_fixed + 2417543472U, // VLD2b8wb_register + 2282285360U, // VLD2d16 + 2282268976U, // VLD2d16wb_fixed + 2282277168U, // VLD2d16wb_register + 2282809648U, // VLD2d32 + 2282793264U, // VLD2d32wb_fixed + 2282801456U, // VLD2d32wb_register + 2283333936U, // VLD2d8 + 2283317552U, // VLD2d8wb_fixed + 2283325744U, // VLD2d8wb_register + 537454896U, // VLD2q16 + 0U, // VLD2q16Pseudo + 0U, // VLD2q16PseudoWB_fixed + 0U, // VLD2q16PseudoWB_register + 537438512U, // VLD2q16wb_fixed + 537446704U, // VLD2q16wb_register + 537979184U, // VLD2q32 + 0U, // VLD2q32Pseudo + 0U, // VLD2q32PseudoWB_fixed + 0U, // VLD2q32PseudoWB_register + 537962800U, // VLD2q32wb_fixed + 537970992U, // VLD2q32wb_register + 538503472U, // VLD2q8 + 0U, // VLD2q8Pseudo + 0U, // VLD2q8PseudoWB_fixed + 0U, // VLD2q8PseudoWB_register + 538487088U, // VLD2q8wb_fixed + 538495280U, // VLD2q8wb_register + 27838805U, // VLD3DUPd16 + 0U, // VLD3DUPd16Pseudo + 0U, // VLD3DUPd16Pseudo_UPD + 28084565U, // VLD3DUPd16_UPD + 28363093U, // VLD3DUPd32 + 0U, // VLD3DUPd32Pseudo + 0U, // VLD3DUPd32Pseudo_UPD + 28608853U, // VLD3DUPd32_UPD + 28887381U, // VLD3DUPd8 + 0U, // VLD3DUPd8Pseudo + 0U, // VLD3DUPd8Pseudo_UPD + 29133141U, // VLD3DUPd8_UPD + 27838805U, // VLD3DUPq16 + 0U, // VLD3DUPq16EvenPseudo + 0U, // VLD3DUPq16OddPseudo + 0U, // VLD3DUPq16OddPseudo_UPD + 28084565U, // VLD3DUPq16_UPD + 28363093U, // VLD3DUPq32 + 0U, // VLD3DUPq32EvenPseudo + 0U, // VLD3DUPq32OddPseudo + 0U, // VLD3DUPq32OddPseudo_UPD + 28608853U, // VLD3DUPq32_UPD + 28887381U, // VLD3DUPq8 + 0U, // VLD3DUPq8EvenPseudo + 0U, // VLD3DUPq8OddPseudo + 0U, // VLD3DUPq8OddPseudo_UPD + 29133141U, // VLD3DUPq8_UPD + 28092757U, // VLD3LNd16 + 0U, // VLD3LNd16Pseudo + 0U, // VLD3LNd16Pseudo_UPD + 28100949U, // VLD3LNd16_UPD + 28617045U, // VLD3LNd32 + 0U, // VLD3LNd32Pseudo + 0U, // VLD3LNd32Pseudo_UPD + 28625237U, // VLD3LNd32_UPD + 29141333U, // VLD3LNd8 + 0U, // VLD3LNd8Pseudo + 0U, // VLD3LNd8Pseudo_UPD + 29149525U, // VLD3LNd8_UPD + 28092757U, // VLD3LNq16 + 0U, // VLD3LNq16Pseudo + 0U, // VLD3LNq16Pseudo_UPD + 28100949U, // VLD3LNq16_UPD + 28617045U, // VLD3LNq32 + 0U, // VLD3LNq32Pseudo + 0U, // VLD3LNq32Pseudo_UPD + 28625237U, // VLD3LNq32_UPD + 27838805U, // VLD3d16 + 0U, // VLD3d16Pseudo + 0U, // VLD3d16Pseudo_UPD + 28084565U, // VLD3d16_UPD + 28363093U, // VLD3d32 + 0U, // VLD3d32Pseudo + 0U, // VLD3d32Pseudo_UPD + 28608853U, // VLD3d32_UPD + 28887381U, // VLD3d8 + 0U, // VLD3d8Pseudo + 0U, // VLD3d8Pseudo_UPD + 29133141U, // VLD3d8_UPD + 27838805U, // VLD3q16 + 0U, // VLD3q16Pseudo_UPD + 28084565U, // VLD3q16_UPD + 0U, // VLD3q16oddPseudo + 0U, // VLD3q16oddPseudo_UPD + 28363093U, // VLD3q32 + 0U, // VLD3q32Pseudo_UPD + 28608853U, // VLD3q32_UPD + 0U, // VLD3q32oddPseudo + 0U, // VLD3q32oddPseudo_UPD + 28887381U, // VLD3q8 + 0U, // VLD3q8Pseudo_UPD + 29133141U, // VLD3q8_UPD + 0U, // VLD3q8oddPseudo + 0U, // VLD3q8oddPseudo_UPD + 27912561U, // VLD4DUPd16 + 0U, // VLD4DUPd16Pseudo + 0U, // VLD4DUPd16Pseudo_UPD + 28109169U, // VLD4DUPd16_UPD + 28436849U, // VLD4DUPd32 + 0U, // VLD4DUPd32Pseudo + 0U, // VLD4DUPd32Pseudo_UPD + 28633457U, // VLD4DUPd32_UPD + 28961137U, // VLD4DUPd8 + 0U, // VLD4DUPd8Pseudo + 0U, // VLD4DUPd8Pseudo_UPD + 29157745U, // VLD4DUPd8_UPD + 27912561U, // VLD4DUPq16 + 0U, // VLD4DUPq16EvenPseudo + 0U, // VLD4DUPq16OddPseudo + 0U, // VLD4DUPq16OddPseudo_UPD + 28109169U, // VLD4DUPq16_UPD + 28436849U, // VLD4DUPq32 + 0U, // VLD4DUPq32EvenPseudo + 0U, // VLD4DUPq32OddPseudo + 0U, // VLD4DUPq32OddPseudo_UPD + 28633457U, // VLD4DUPq32_UPD + 28961137U, // VLD4DUPq8 + 0U, // VLD4DUPq8EvenPseudo + 0U, // VLD4DUPq8OddPseudo + 0U, // VLD4DUPq8OddPseudo_UPD + 29157745U, // VLD4DUPq8_UPD + 28100977U, // VLD4LNd16 + 0U, // VLD4LNd16Pseudo + 0U, // VLD4LNd16Pseudo_UPD + 28117361U, // VLD4LNd16_UPD + 28625265U, // VLD4LNd32 + 0U, // VLD4LNd32Pseudo + 0U, // VLD4LNd32Pseudo_UPD + 28641649U, // VLD4LNd32_UPD + 29149553U, // VLD4LNd8 + 0U, // VLD4LNd8Pseudo + 0U, // VLD4LNd8Pseudo_UPD + 29165937U, // VLD4LNd8_UPD + 28100977U, // VLD4LNq16 + 0U, // VLD4LNq16Pseudo + 0U, // VLD4LNq16Pseudo_UPD + 28117361U, // VLD4LNq16_UPD + 28625265U, // VLD4LNq32 + 0U, // VLD4LNq32Pseudo + 0U, // VLD4LNq32Pseudo_UPD + 28641649U, // VLD4LNq32_UPD + 27912561U, // VLD4d16 + 0U, // VLD4d16Pseudo + 0U, // VLD4d16Pseudo_UPD + 28109169U, // VLD4d16_UPD + 28436849U, // VLD4d32 + 0U, // VLD4d32Pseudo + 0U, // VLD4d32Pseudo_UPD + 28633457U, // VLD4d32_UPD + 28961137U, // VLD4d8 + 0U, // VLD4d8Pseudo + 0U, // VLD4d8Pseudo_UPD + 29157745U, // VLD4d8_UPD + 27912561U, // VLD4q16 + 0U, // VLD4q16Pseudo_UPD + 28109169U, // VLD4q16_UPD + 0U, // VLD4q16oddPseudo + 0U, // VLD4q16oddPseudo_UPD + 28436849U, // VLD4q32 + 0U, // VLD4q32Pseudo_UPD + 28633457U, // VLD4q32_UPD + 0U, // VLD4q32oddPseudo + 0U, // VLD4q32oddPseudo_UPD + 28961137U, // VLD4q8 + 0U, // VLD4q8Pseudo_UPD + 29157745U, // VLD4q8_UPD + 0U, // VLD4q8oddPseudo + 0U, // VLD4q8oddPseudo_UPD + 875064304U, // VLDMDDB_UPD + 2722588U, // VLDMDIA + 875064092U, // VLDMDIA_UPD + 0U, // VLDMQIA + 875064304U, // VLDMSDB_UPD + 2722588U, // VLDMSIA + 875064092U, // VLDMSIA_UPD + 2683254U, // VLDRD + 586102U, // VLDRH + 2683254U, // VLDRS + 2512417142U, // VLDR_FPCXTNS_off + 700510582U, // VLDR_FPCXTNS_post + 2579558774U, // VLDR_FPCXTNS_pre + 2512941430U, // VLDR_FPCXTS_off + 701034870U, // VLDR_FPCXTS_post + 2580083062U, // VLDR_FPCXTS_pre + 2513465718U, // VLDR_FPSCR_NZCVQC_off + 701559158U, // VLDR_FPSCR_NZCVQC_post + 2580607350U, // VLDR_FPSCR_NZCVQC_pre + 2513990006U, // VLDR_FPSCR_off + 702083446U, // VLDR_FPSCR_post + 2581131638U, // VLDR_FPSCR_pre + 2648764790U, // VLDR_P0_off + 1575006582U, // VLDR_P0_post + 2715857270U, // VLDR_P0_pre + 2515038582U, // VLDR_VPR_off + 703132022U, // VLDR_VPR_post + 2582180214U, // VLDR_VPR_pre + 2723917U, // VLLDM + 2723952U, // VLSTM + 8451186U, // VMAXfd + 8451186U, // VMAXfq + 7926898U, // VMAXhd + 7926898U, // VMAXhq + 11596914U, // VMAXsv16i8 + 11072626U, // VMAXsv2i32 + 10548338U, // VMAXsv4i16 + 11072626U, // VMAXsv4i32 + 10548338U, // VMAXsv8i16 + 11596914U, // VMAXsv8i8 + 13169778U, // VMAXuv16i8 + 12645490U, // VMAXuv2i32 + 12121202U, // VMAXuv4i16 + 12645490U, // VMAXuv4i32 + 12121202U, // VMAXuv8i16 + 13169778U, // VMAXuv8i8 + 8450208U, // VMINfd + 8450208U, // VMINfq + 7925920U, // VMINhd + 7925920U, // VMINhq + 11595936U, // VMINsv16i8 + 11071648U, // VMINsv2i32 + 10547360U, // VMINsv4i16 + 11071648U, // VMINsv4i32 + 10547360U, // VMINsv8i16 + 11595936U, // VMINsv8i8 + 13168800U, // VMINuv16i8 + 12644512U, // VMINuv2i32 + 12120224U, // VMINuv4i16 + 12644512U, // VMINuv4i32 + 12120224U, // VMINuv8i16 + 13168800U, // VMINuv8i8 + 946907970U, // VMLAD + 7908162U, // VMLAH + 11063117U, // VMLALslsv2i32 + 10538829U, // VMLALslsv4i16 + 12635981U, // VMLALsluv2i32 + 12111693U, // VMLALsluv4i16 + 11054925U, // VMLALsv2i64 + 10530637U, // VMLALsv4i32 + 11579213U, // VMLALsv8i16 + 12627789U, // VMLALuv2i64 + 12103501U, // VMLALuv4i32 + 13152077U, // VMLALuv8i16 + 8432450U, // VMLAS + 8432450U, // VMLAfd + 8432450U, // VMLAfq + 7908162U, // VMLAhd + 7908162U, // VMLAhq + 8440642U, // VMLAslfd + 8440642U, // VMLAslfq + 7916354U, // VMLAslhd + 7916354U, // VMLAslhq + 13683522U, // VMLAslv2i32 + 14207810U, // VMLAslv4i16 + 13683522U, // VMLAslv4i32 + 14207810U, // VMLAslv8i16 + 14723906U, // VMLAv16i8 + 13675330U, // VMLAv2i32 + 14199618U, // VMLAv4i16 + 13675330U, // VMLAv4i32 + 14199618U, // VMLAv8i16 + 14723906U, // VMLAv8i8 + 946909704U, // VMLSD + 7909896U, // VMLSH + 11063334U, // VMLSLslsv2i32 + 10539046U, // VMLSLslsv4i16 + 12636198U, // VMLSLsluv2i32 + 12111910U, // VMLSLsluv4i16 + 11055142U, // VMLSLsv2i64 + 10530854U, // VMLSLsv4i32 + 11579430U, // VMLSLsv8i16 + 12628006U, // VMLSLuv2i64 + 12103718U, // VMLSLuv4i32 + 13152294U, // VMLSLuv8i16 + 8434184U, // VMLSS + 8434184U, // VMLSfd + 8434184U, // VMLSfq + 7909896U, // VMLShd + 7909896U, // VMLShq + 8442376U, // VMLSslfd + 8442376U, // VMLSslfq + 7918088U, // VMLSslhd + 7918088U, // VMLSslhq + 13685256U, // VMLSslv2i32 + 14209544U, // VMLSslv4i16 + 13685256U, // VMLSslv4i32 + 14209544U, // VMLSslv8i16 + 14725640U, // VMLSv16i8 + 13677064U, // VMLSv2i32 + 14201352U, // VMLSv4i16 + 13677064U, // VMLSv4i32 + 14201352U, // VMLSv8i16 + 14725640U, // VMLSv8i8 + 943285690U, // VMMLA + 946893845U, // VMOVD + 2683925U, // VMOVDRR + 875644323U, // VMOVH + 7894037U, // VMOVHR + 11038791U, // VMOVLsv2i64 + 10514503U, // VMOVLsv4i32 + 11563079U, // VMOVLsv8i16 + 12611655U, // VMOVLuv2i64 + 12087367U, // VMOVLuv4i32 + 13135943U, // VMOVLuv8i16 + 894988545U, // VMOVNv2i32 + 13660417U, // VMOVNv4i16 + 14184705U, // VMOVNv8i8 + 7894037U, // VMOVRH + 2683925U, // VMOVRRD + 2667541U, // VMOVRRS + 2651157U, // VMOVRS + 8418325U, // VMOVS + 2651157U, // VMOVSR + 2667541U, // VMOVSRR + 14709781U, // VMOVv16i8 + 1968731157U, // VMOVv1i64 + 8418325U, // VMOVv2f32 + 13661205U, // VMOVv2i32 + 1968731157U, // VMOVv2i64 + 8418325U, // VMOVv4f32 + 14185493U, // VMOVv4i16 + 13661205U, // VMOVv4i32 + 14185493U, // VMOVv8i16 + 14709781U, // VMOVv8i8 + 2724394U, // VMRS + 2724394U, // VMRS_FPCXTNS + 2724394U, // VMRS_FPCXTS + 2724394U, // VMRS_FPEXC + 2724394U, // VMRS_FPINST + 2724394U, // VMRS_FPINST2 + 2650666U, // VMRS_FPSCR_NZCVQC + 2724394U, // VMRS_FPSID + 2724394U, // VMRS_MVFR0 + 2724394U, // VMRS_MVFR1 + 2724394U, // VMRS_MVFR2 + 2650666U, // VMRS_P0 + 2724394U, // VMRS_VPR + 31035838U, // VMSR + 29462974U, // VMSR_FPCXTNS + 29987262U, // VMSR_FPCXTS + 32608702U, // VMSR_FPEXC + 33132990U, // VMSR_FPINST + 33657278U, // VMSR_FPINST2 + 902853054U, // VMSR_FPSCR_NZCVQC + 34181566U, // VMSR_FPSID + 903901630U, // VMSR_P0 + 32084414U, // VMSR_VPR + 946925634U, // VMULD + 7925826U, // VMULH + 875643746U, // VMULLp64 + 23654387U, // VMULLp8 + 11055091U, // VMULLslsv2i32 + 10530803U, // VMULLslsv4i16 + 12627955U, // VMULLsluv2i32 + 12103667U, // VMULLsluv4i16 + 11071475U, // VMULLsv2i64 + 10547187U, // VMULLsv4i32 + 11595763U, // VMULLsv8i16 + 12644339U, // VMULLuv2i64 + 12120051U, // VMULLuv4i32 + 13168627U, // VMULLuv8i16 + 8450114U, // VMULS + 8450114U, // VMULfd + 8450114U, // VMULfq + 7925826U, // VMULhd + 7925826U, // VMULhq + 23654466U, // VMULpd + 23654466U, // VMULpq + 8433730U, // VMULslfd + 8433730U, // VMULslfq + 7909442U, // VMULslhd + 7909442U, // VMULslhq + 13676610U, // VMULslv2i32 + 14200898U, // VMULslv4i16 + 13676610U, // VMULslv4i32 + 14200898U, // VMULslv8i16 + 14741570U, // VMULv16i8 + 13692994U, // VMULv2i32 + 14217282U, // VMULv4i16 + 13692994U, // VMULv4i32 + 14217282U, // VMULv8i16 + 14741570U, // VMULv8i8 + 2650357U, // VMVNd + 2650357U, // VMVNq + 13660405U, // VMVNv2i32 + 14184693U, // VMVNv4i16 + 13660405U, // VMVNv4i32 + 14184693U, // VMVNv8i16 + 946892300U, // VNEGD + 7892492U, // VNEGH + 8416780U, // VNEGS + 8416780U, // VNEGf32q + 8416780U, // VNEGfd + 7892492U, // VNEGhd + 7892492U, // VNEGhq + 10513932U, // VNEGs16d + 10513932U, // VNEGs16q + 11038220U, // VNEGs32d + 11038220U, // VNEGs32q + 11562508U, // VNEGs8d + 11562508U, // VNEGs8q + 946907964U, // VNMLAD + 7908156U, // VNMLAH + 8432444U, // VNMLAS + 946909698U, // VNMLSD + 7909890U, // VNMLSH + 8434178U, // VNMLSS + 946925628U, // VNMULD + 7925820U, // VNMULH + 8450108U, // VNMULS + 2683077U, // VORNd + 2683077U, // VORNq + 2683310U, // VORRd + 13693358U, // VORRiv2i32 + 14217646U, // VORRiv4i16 + 13693358U, // VORRiv4i32 + 14217646U, // VORRiv8i16 + 2683310U, // VORRq + 11595570U, // VPADALsv16i8 + 11071282U, // VPADALsv2i32 + 10546994U, // VPADALsv4i16 + 11071282U, // VPADALsv4i32 + 10546994U, // VPADALsv8i16 + 11595570U, // VPADALsv8i8 + 13168434U, // VPADALuv16i8 + 12644146U, // VPADALuv2i32 + 12119858U, // VPADALuv4i16 + 12644146U, // VPADALuv4i32 + 12119858U, // VPADALuv8i16 + 13168434U, // VPADALuv8i8 + 11562862U, // VPADDLsv16i8 + 11038574U, // VPADDLsv2i32 + 10514286U, // VPADDLsv4i16 + 11038574U, // VPADDLsv4i32 + 10514286U, // VPADDLsv8i16 + 11562862U, // VPADDLsv8i8 + 13135726U, // VPADDLuv16i8 + 12611438U, // VPADDLuv2i32 + 12087150U, // VPADDLuv4i16 + 12611438U, // VPADDLuv4i32 + 12087150U, // VPADDLuv8i16 + 13135726U, // VPADDLuv8i8 + 8449401U, // VPADDf + 7925113U, // VPADDh + 14216569U, // VPADDi16 + 13692281U, // VPADDi32 + 14740857U, // VPADDi8 + 8451180U, // VPMAXf + 7926892U, // VPMAXh + 10548332U, // VPMAXs16 + 11072620U, // VPMAXs32 + 11596908U, // VPMAXs8 + 12121196U, // VPMAXu16 + 12645484U, // VPMAXu32 + 13169772U, // VPMAXu8 + 8450202U, // VPMINf + 7925914U, // VPMINh + 10547354U, // VPMINs16 + 11071642U, // VPMINs32 + 11595930U, // VPMINs8 + 12120218U, // VPMINu16 + 12644506U, // VPMINu32 + 13168794U, // VPMINu8 + 11563495U, // VQABSv16i8 + 11039207U, // VQABSv2i32 + 10514919U, // VQABSv4i16 + 11039207U, // VQABSv4i32 + 10514919U, // VQABSv8i16 + 11563495U, // VQABSv8i8 + 11595135U, // VQADDsv16i8 + 907079039U, // VQADDsv1i64 + 11070847U, // VQADDsv2i32 + 907079039U, // VQADDsv2i64 + 10546559U, // VQADDsv4i16 + 11070847U, // VQADDsv4i32 + 10546559U, // VQADDsv8i16 + 11595135U, // VQADDsv8i8 + 13167999U, // VQADDuv16i8 + 22080895U, // VQADDuv1i64 + 12643711U, // VQADDuv2i32 + 22080895U, // VQADDuv2i64 + 12119423U, // VQADDuv4i16 + 12643711U, // VQADDuv4i32 + 12119423U, // VQADDuv8i16 + 13167999U, // VQADDuv8i8 + 11063097U, // VQDMLALslv2i32 + 10538809U, // VQDMLALslv4i16 + 11054905U, // VQDMLALv2i64 + 10530617U, // VQDMLALv4i32 + 11063326U, // VQDMLSLslv2i32 + 10539038U, // VQDMLSLslv4i16 + 11055134U, // VQDMLSLv2i64 + 10530846U, // VQDMLSLv4i32 + 11054693U, // VQDMULHslv2i32 + 10530405U, // VQDMULHslv4i16 + 11054693U, // VQDMULHslv4i32 + 10530405U, // VQDMULHslv8i16 + 11071077U, // VQDMULHv2i32 + 10546789U, // VQDMULHv4i16 + 11071077U, // VQDMULHv4i32 + 10546789U, // VQDMULHv8i16 + 11055071U, // VQDMULLslv2i32 + 10530783U, // VQDMULLslv4i16 + 11071455U, // VQDMULLv2i64 + 10547167U, // VQDMULLv4i32 + 907047149U, // VQMOVNsuv2i32 + 11038957U, // VQMOVNsuv4i16 + 10514669U, // VQMOVNsuv8i8 + 907047162U, // VQMOVNsv2i32 + 11038970U, // VQMOVNsv4i16 + 10514682U, // VQMOVNsv8i8 + 22049018U, // VQMOVNuv2i32 + 12611834U, // VQMOVNuv4i16 + 12087546U, // VQMOVNuv8i8 + 11562502U, // VQNEGv16i8 + 11038214U, // VQNEGv2i32 + 10513926U, // VQNEGv4i16 + 11038214U, // VQNEGv4i32 + 10513926U, // VQNEGv8i16 + 11562502U, // VQNEGv8i8 + 11062817U, // VQRDMLAHslv2i32 + 10538529U, // VQRDMLAHslv4i16 + 11062817U, // VQRDMLAHslv4i32 + 10538529U, // VQRDMLAHslv8i16 + 11054625U, // VQRDMLAHv2i32 + 10530337U, // VQRDMLAHv4i16 + 11054625U, // VQRDMLAHv4i32 + 10530337U, // VQRDMLAHv8i16 + 11062946U, // VQRDMLSHslv2i32 + 10538658U, // VQRDMLSHslv4i16 + 11062946U, // VQRDMLSHslv4i32 + 10538658U, // VQRDMLSHslv8i16 + 11054754U, // VQRDMLSHv2i32 + 10530466U, // VQRDMLSHv4i16 + 11054754U, // VQRDMLSHv4i32 + 10530466U, // VQRDMLSHv8i16 + 11054701U, // VQRDMULHslv2i32 + 10530413U, // VQRDMULHslv4i16 + 11054701U, // VQRDMULHslv4i32 + 10530413U, // VQRDMULHslv8i16 + 11071085U, // VQRDMULHv2i32 + 10546797U, // VQRDMULHv4i16 + 11071085U, // VQRDMULHv4i32 + 10546797U, // VQRDMULHv8i16 + 11595678U, // VQRSHLsv16i8 + 907079582U, // VQRSHLsv1i64 + 11071390U, // VQRSHLsv2i32 + 907079582U, // VQRSHLsv2i64 + 10547102U, // VQRSHLsv4i16 + 11071390U, // VQRSHLsv4i32 + 10547102U, // VQRSHLsv8i16 + 11595678U, // VQRSHLsv8i8 + 13168542U, // VQRSHLuv16i8 + 22081438U, // VQRSHLuv1i64 + 12644254U, // VQRSHLuv2i32 + 22081438U, // VQRSHLuv2i64 + 12119966U, // VQRSHLuv4i16 + 12644254U, // VQRSHLuv4i32 + 12119966U, // VQRSHLuv8i16 + 13168542U, // VQRSHLuv8i8 + 907079856U, // VQRSHRNsv2i32 + 11071664U, // VQRSHRNsv4i16 + 10547376U, // VQRSHRNsv8i8 + 22081712U, // VQRSHRNuv2i32 + 12644528U, // VQRSHRNuv4i16 + 12120240U, // VQRSHRNuv8i8 + 907079908U, // VQRSHRUNv2i32 + 11071716U, // VQRSHRUNv4i16 + 10547428U, // VQRSHRUNv8i8 + 11595665U, // VQSHLsiv16i8 + 907079569U, // VQSHLsiv1i64 + 11071377U, // VQSHLsiv2i32 + 907079569U, // VQSHLsiv2i64 + 10547089U, // VQSHLsiv4i16 + 11071377U, // VQSHLsiv4i32 + 10547089U, // VQSHLsiv8i16 + 11595665U, // VQSHLsiv8i8 + 11596688U, // VQSHLsuv16i8 + 907080592U, // VQSHLsuv1i64 + 11072400U, // VQSHLsuv2i32 + 907080592U, // VQSHLsuv2i64 + 10548112U, // VQSHLsuv4i16 + 11072400U, // VQSHLsuv4i32 + 10548112U, // VQSHLsuv8i16 + 11596688U, // VQSHLsuv8i8 + 11595665U, // VQSHLsv16i8 + 907079569U, // VQSHLsv1i64 + 11071377U, // VQSHLsv2i32 + 907079569U, // VQSHLsv2i64 + 10547089U, // VQSHLsv4i16 + 11071377U, // VQSHLsv4i32 + 10547089U, // VQSHLsv8i16 + 11595665U, // VQSHLsv8i8 + 13168529U, // VQSHLuiv16i8 + 22081425U, // VQSHLuiv1i64 + 12644241U, // VQSHLuiv2i32 + 22081425U, // VQSHLuiv2i64 + 12119953U, // VQSHLuiv4i16 + 12644241U, // VQSHLuiv4i32 + 12119953U, // VQSHLuiv8i16 + 13168529U, // VQSHLuiv8i8 + 13168529U, // VQSHLuv16i8 + 22081425U, // VQSHLuv1i64 + 12644241U, // VQSHLuv2i32 + 22081425U, // VQSHLuv2i64 + 12119953U, // VQSHLuv4i16 + 12644241U, // VQSHLuv4i32 + 12119953U, // VQSHLuv8i16 + 13168529U, // VQSHLuv8i8 + 907079849U, // VQSHRNsv2i32 + 11071657U, // VQSHRNsv4i16 + 10547369U, // VQSHRNsv8i8 + 22081705U, // VQSHRNuv2i32 + 12644521U, // VQSHRNuv4i16 + 12120233U, // VQSHRNuv8i8 + 907079900U, // VQSHRUNv2i32 + 11071708U, // VQSHRUNv4i16 + 10547420U, // VQSHRUNv8i8 + 11594973U, // VQSUBsv16i8 + 907078877U, // VQSUBsv1i64 + 11070685U, // VQSUBsv2i32 + 907078877U, // VQSUBsv2i64 + 10546397U, // VQSUBsv4i16 + 11070685U, // VQSUBsv4i32 + 10546397U, // VQSUBsv8i16 + 11594973U, // VQSUBsv8i8 + 13167837U, // VQSUBuv16i8 + 22080733U, // VQSUBuv1i64 + 12643549U, // VQSUBuv2i32 + 22080733U, // VQSUBuv2i64 + 12119261U, // VQSUBuv4i16 + 12643549U, // VQSUBuv4i32 + 12119261U, // VQSUBuv8i16 + 13167837U, // VQSUBuv8i8 + 895021195U, // VRADDHNv2i32 + 13693067U, // VRADDHNv4i16 + 14217355U, // VRADDHNv8i8 + 12611045U, // VRECPEd + 8416741U, // VRECPEfd + 8416741U, // VRECPEfq + 7892453U, // VRECPEhd + 7892453U, // VRECPEhq + 12611045U, // VRECPEq + 8450595U, // VRECPSfd + 8450595U, // VRECPSfq + 7926307U, // VRECPShd + 7926307U, // VRECPShq + 1599987U, // VREV16d8 + 1599987U, // VREV16q8 + 551188U, // VREV32d16 + 1599764U, // VREV32d8 + 551188U, // VREV32q16 + 1599764U, // VREV32q8 + 551274U, // VREV64d16 + 1075562U, // VREV64d32 + 1599850U, // VREV64d8 + 551274U, // VREV64q16 + 1075562U, // VREV64q32 + 1599850U, // VREV64q8 + 11595116U, // VRHADDsv16i8 + 11070828U, // VRHADDsv2i32 + 10546540U, // VRHADDsv4i16 + 11070828U, // VRHADDsv4i32 + 10546540U, // VRHADDsv8i16 + 11595116U, // VRHADDsv8i8 + 13167980U, // VRHADDuv16i8 + 12643692U, // VRHADDuv2i32 + 12119404U, // VRHADDuv4i16 + 12643692U, // VRHADDuv4i32 + 12119404U, // VRHADDuv8i16 + 13167980U, // VRHADDuv8i8 + 875643626U, // VRINTAD + 875644148U, // VRINTAH + 875643275U, // VRINTANDf + 875644148U, // VRINTANDh + 875643275U, // VRINTANQf + 875644148U, // VRINTANQh + 875643275U, // VRINTAS + 875643674U, // VRINTMD + 875644229U, // VRINTMH + 875643334U, // VRINTMNDf + 875644229U, // VRINTMNDh + 875643334U, // VRINTMNQf + 875644229U, // VRINTMNQh + 875643334U, // VRINTMS + 875643686U, // VRINTND + 875644241U, // VRINTNH + 875643346U, // VRINTNNDf + 875644241U, // VRINTNNDh + 875643346U, // VRINTNNQf + 875644241U, // VRINTNNQh + 875643346U, // VRINTNS + 875643698U, // VRINTPD + 875644253U, // VRINTPH + 875643358U, // VRINTPNDf + 875644253U, // VRINTPNDh + 875643358U, // VRINTPNQf + 875644253U, // VRINTPNQh + 875643358U, // VRINTPS + 946893257U, // VRINTRD + 7893449U, // VRINTRH + 8417737U, // VRINTRS + 946894225U, // VRINTXD + 7894417U, // VRINTXH + 875643406U, // VRINTXNDf + 875644311U, // VRINTXNDh + 875643406U, // VRINTXNQf + 875644311U, // VRINTXNQh + 8418705U, // VRINTXS + 946894275U, // VRINTZD + 7894467U, // VRINTZH + 875643418U, // VRINTZNDf + 875644334U, // VRINTZNDh + 875643418U, // VRINTZNQf + 875644334U, // VRINTZNQh + 8418755U, // VRINTZS + 11595685U, // VRSHLsv16i8 + 907079589U, // VRSHLsv1i64 + 11071397U, // VRSHLsv2i32 + 907079589U, // VRSHLsv2i64 + 10547109U, // VRSHLsv4i16 + 11071397U, // VRSHLsv4i32 + 10547109U, // VRSHLsv8i16 + 11595685U, // VRSHLsv8i8 + 13168549U, // VRSHLuv16i8 + 22081445U, // VRSHLuv1i64 + 12644261U, // VRSHLuv2i32 + 22081445U, // VRSHLuv2i64 + 12119973U, // VRSHLuv4i16 + 12644261U, // VRSHLuv4i32 + 12119973U, // VRSHLuv8i16 + 13168549U, // VRSHLuv8i8 + 895021240U, // VRSHRNv2i32 + 13693112U, // VRSHRNv4i16 + 14217400U, // VRSHRNv8i8 + 11596174U, // VRSHRsv16i8 + 907080078U, // VRSHRsv1i64 + 11071886U, // VRSHRsv2i32 + 907080078U, // VRSHRsv2i64 + 10547598U, // VRSHRsv4i16 + 11071886U, // VRSHRsv4i32 + 10547598U, // VRSHRsv8i16 + 11596174U, // VRSHRsv8i8 + 13169038U, // VRSHRuv16i8 + 22081934U, // VRSHRuv1i64 + 12644750U, // VRSHRuv2i32 + 22081934U, // VRSHRuv2i64 + 12120462U, // VRSHRuv4i16 + 12644750U, // VRSHRuv4i32 + 12120462U, // VRSHRuv8i16 + 13169038U, // VRSHRuv8i8 + 12611058U, // VRSQRTEd + 8416754U, // VRSQRTEfd + 8416754U, // VRSQRTEfq + 7892466U, // VRSQRTEhd + 7892466U, // VRSQRTEhq + 12611058U, // VRSQRTEq + 8450617U, // VRSQRTSfd + 8450617U, // VRSQRTSfq + 7926329U, // VRSQRTShd + 7926329U, // VRSQRTShq + 11578216U, // VRSRAsv16i8 + 839953256U, // VRSRAsv1i64 + 11053928U, // VRSRAsv2i32 + 839953256U, // VRSRAsv2i64 + 10529640U, // VRSRAsv4i16 + 11053928U, // VRSRAsv4i32 + 10529640U, // VRSRAsv8i16 + 11578216U, // VRSRAsv8i8 + 13151080U, // VRSRAuv16i8 + 22063976U, // VRSRAuv1i64 + 12626792U, // VRSRAuv2i32 + 22063976U, // VRSRAuv2i64 + 12102504U, // VRSRAuv4i16 + 12626792U, // VRSRAuv4i32 + 12102504U, // VRSRAuv8i16 + 13151080U, // VRSRAuv8i8 + 895021180U, // VRSUBHNv2i32 + 13693052U, // VRSUBHNv4i16 + 14217340U, // VRSUBHNv8i8 + 2754195553U, // VSCCLRMD + 2754195553U, // VSCCLRMS + 943285932U, // VSDOTD + 943285932U, // VSDOTDI + 943285932U, // VSDOTQ + 943285932U, // VSDOTQI + 875643710U, // VSELEQD + 875644265U, // VSELEQH + 875643370U, // VSELEQS + 875643638U, // VSELGED + 875644171U, // VSELGEH + 875643298U, // VSELGES + 875643734U, // VSELGTD + 875644299U, // VSELGTH + 875643394U, // VSELGTS + 875643722U, // VSELVSD + 875644287U, // VSELVSH + 875643382U, // VSELVSS + 570389U, // VSETLNi16 + 1094677U, // VSETLNi32 + 1618965U, // VSETLNi8 + 14217172U, // VSHLLi16 + 13692884U, // VSHLLi32 + 14741460U, // VSHLLi8 + 11071444U, // VSHLLsv2i64 + 10547156U, // VSHLLsv4i32 + 11595732U, // VSHLLsv8i16 + 12644308U, // VSHLLuv2i64 + 12120020U, // VSHLLuv4i32 + 13168596U, // VSHLLuv8i16 + 14741419U, // VSHLiv16i8 + 895020971U, // VSHLiv1i64 + 13692843U, // VSHLiv2i32 + 895020971U, // VSHLiv2i64 + 14217131U, // VSHLiv4i16 + 13692843U, // VSHLiv4i32 + 14217131U, // VSHLiv8i16 + 14741419U, // VSHLiv8i8 + 11595691U, // VSHLsv16i8 + 907079595U, // VSHLsv1i64 + 11071403U, // VSHLsv2i32 + 907079595U, // VSHLsv2i64 + 10547115U, // VSHLsv4i16 + 11071403U, // VSHLsv4i32 + 10547115U, // VSHLsv8i16 + 11595691U, // VSHLsv8i8 + 13168555U, // VSHLuv16i8 + 22081451U, // VSHLuv1i64 + 12644267U, // VSHLuv2i32 + 22081451U, // VSHLuv2i64 + 12119979U, // VSHLuv4i16 + 12644267U, // VSHLuv4i32 + 12119979U, // VSHLuv8i16 + 13168555U, // VSHLuv8i8 + 895021247U, // VSHRNv2i32 + 13693119U, // VSHRNv4i16 + 14217407U, // VSHRNv8i8 + 11596180U, // VSHRsv16i8 + 907080084U, // VSHRsv1i64 + 11071892U, // VSHRsv2i32 + 907080084U, // VSHRsv2i64 + 10547604U, // VSHRsv4i16 + 11071892U, // VSHRsv4i32 + 10547604U, // VSHRsv8i16 + 11596180U, // VSHRsv8i8 + 13169044U, // VSHRuv16i8 + 22081940U, // VSHRuv1i64 + 12644756U, // VSHRuv2i32 + 22081940U, // VSHRuv2i64 + 12120468U, // VSHRuv4i16 + 12644756U, // VSHRuv4i32 + 12120468U, // VSHRuv8i16 + 13169044U, // VSHRuv8i8 + 35189619U, // VSHTOD + 955839347U, // VSHTOH + 35713907U, // VSHTOS + 1109947251U, // VSITOD + 1110471539U, // VSITOH + 1091597171U, // VSITOS + 1617676U, // VSLIv16i8 + 15249164U, // VSLIv1i64 + 1093388U, // VSLIv2i32 + 15249164U, // VSLIv2i64 + 569100U, // VSLIv4i16 + 1093388U, // VSLIv4i32 + 569100U, // VSLIv8i16 + 1617676U, // VSLIv8i8 + 975762291U, // VSLTOD + 976286579U, // VSLTOH + 957412211U, // VSLTOS + 943285910U, // VSMMLA + 946893624U, // VSQRTD + 7893816U, // VSQRTH + 8418104U, // VSQRTS + 11578222U, // VSRAsv16i8 + 839953262U, // VSRAsv1i64 + 11053934U, // VSRAsv2i32 + 839953262U, // VSRAsv2i64 + 10529646U, // VSRAsv4i16 + 11053934U, // VSRAsv4i32 + 10529646U, // VSRAsv8i16 + 11578222U, // VSRAsv8i8 + 13151086U, // VSRAuv16i8 + 22063982U, // VSRAuv1i64 + 12626798U, // VSRAuv2i32 + 22063982U, // VSRAuv2i64 + 12102510U, // VSRAuv4i16 + 12626798U, // VSRAuv4i32 + 12102510U, // VSRAuv8i16 + 13151086U, // VSRAuv8i8 + 1617681U, // VSRIv16i8 + 15249169U, // VSRIv1i64 + 1093393U, // VSRIv2i32 + 15249169U, // VSRIv2i64 + 569105U, // VSRIv4i16 + 1093393U, // VSRIv4i32 + 569105U, // VSRIv8i16 + 1617681U, // VSRIv8i8 + 833136906U, // VST1LNd16 + 2846484746U, // VST1LNd16_UPD + 833661194U, // VST1LNd32 + 2847009034U, // VST1LNd32_UPD + 834185482U, // VST1LNd8 + 2847533322U, // VST1LNd8_UPD + 0U, // VST1LNq16Pseudo + 0U, // VST1LNq16Pseudo_UPD + 0U, // VST1LNq32Pseudo + 0U, // VST1LNq32Pseudo_UPD + 0U, // VST1LNq8Pseudo + 0U, // VST1LNq8Pseudo_UPD + 2886265098U, // VST1d16 + 2953373962U, // VST1d16Q + 0U, // VST1d16QPseudo + 0U, // VST1d16QPseudoWB_fixed + 0U, // VST1d16QPseudoWB_register + 3020466442U, // VST1d16Qwb_fixed + 3087583498U, // VST1d16Qwb_register + 3154700554U, // VST1d16T + 0U, // VST1d16TPseudo + 0U, // VST1d16TPseudoWB_fixed + 0U, // VST1d16TPseudoWB_register + 3221793034U, // VST1d16Twb_fixed + 3288910090U, // VST1d16Twb_register + 3356010762U, // VST1d16wb_fixed + 3423127818U, // VST1d16wb_register + 2886789386U, // VST1d32 + 2953898250U, // VST1d32Q + 0U, // VST1d32QPseudo + 0U, // VST1d32QPseudoWB_fixed + 0U, // VST1d32QPseudoWB_register + 3020990730U, // VST1d32Qwb_fixed + 3088107786U, // VST1d32Qwb_register + 3155224842U, // VST1d32T + 0U, // VST1d32TPseudo + 0U, // VST1d32TPseudoWB_fixed + 0U, // VST1d32TPseudoWB_register + 3222317322U, // VST1d32Twb_fixed + 3289434378U, // VST1d32Twb_register + 3356535050U, // VST1d32wb_fixed + 3423652106U, // VST1d32wb_register + 2900945162U, // VST1d64 + 2968054026U, // VST1d64Q + 0U, // VST1d64QPseudo + 0U, // VST1d64QPseudoWB_fixed + 0U, // VST1d64QPseudoWB_register + 3035146506U, // VST1d64Qwb_fixed + 3102263562U, // VST1d64Qwb_register + 3169380618U, // VST1d64T + 0U, // VST1d64TPseudo + 0U, // VST1d64TPseudoWB_fixed + 0U, // VST1d64TPseudoWB_register + 3236473098U, // VST1d64Twb_fixed + 3303590154U, // VST1d64Twb_register + 3370690826U, // VST1d64wb_fixed + 3437807882U, // VST1d64wb_register + 2887313674U, // VST1d8 + 2954422538U, // VST1d8Q + 0U, // VST1d8QPseudo + 0U, // VST1d8QPseudoWB_fixed + 0U, // VST1d8QPseudoWB_register + 3021515018U, // VST1d8Qwb_fixed + 3088632074U, // VST1d8Qwb_register + 3155749130U, // VST1d8T + 0U, // VST1d8TPseudo + 0U, // VST1d8TPseudoWB_fixed + 0U, // VST1d8TPseudoWB_register + 3222841610U, // VST1d8Twb_fixed + 3289958666U, // VST1d8Twb_register + 3357059338U, // VST1d8wb_fixed + 3424176394U, // VST1d8wb_register + 3490244874U, // VST1q16 + 0U, // VST1q16HighQPseudo + 0U, // VST1q16HighQPseudo_UPD + 0U, // VST1q16HighTPseudo + 0U, // VST1q16HighTPseudo_UPD + 0U, // VST1q16LowQPseudo_UPD + 0U, // VST1q16LowTPseudo_UPD + 3557337354U, // VST1q16wb_fixed + 3624454410U, // VST1q16wb_register + 3490769162U, // VST1q32 + 0U, // VST1q32HighQPseudo + 0U, // VST1q32HighQPseudo_UPD + 0U, // VST1q32HighTPseudo + 0U, // VST1q32HighTPseudo_UPD + 0U, // VST1q32LowQPseudo_UPD + 0U, // VST1q32LowTPseudo_UPD + 3557861642U, // VST1q32wb_fixed + 3624978698U, // VST1q32wb_register + 3504924938U, // VST1q64 + 0U, // VST1q64HighQPseudo + 0U, // VST1q64HighQPseudo_UPD + 0U, // VST1q64HighTPseudo + 0U, // VST1q64HighTPseudo_UPD + 0U, // VST1q64LowQPseudo_UPD + 0U, // VST1q64LowTPseudo_UPD + 3572017418U, // VST1q64wb_fixed + 3639134474U, // VST1q64wb_register + 3491293450U, // VST1q8 + 0U, // VST1q8HighQPseudo + 0U, // VST1q8HighQPseudo_UPD + 0U, // VST1q8HighTPseudo + 0U, // VST1q8HighTPseudo_UPD + 0U, // VST1q8LowQPseudo_UPD + 0U, // VST1q8LowTPseudo_UPD + 3558385930U, // VST1q8wb_fixed + 3625502986U, // VST1q8wb_register + 833145163U, // VST2LNd16 + 0U, // VST2LNd16Pseudo + 0U, // VST2LNd16Pseudo_UPD + 2846656843U, // VST2LNd16_UPD + 833669451U, // VST2LNd32 + 0U, // VST2LNd32Pseudo + 0U, // VST2LNd32Pseudo_UPD + 2847181131U, // VST2LNd32_UPD + 834193739U, // VST2LNd8 + 0U, // VST2LNd8Pseudo + 0U, // VST2LNd8Pseudo_UPD + 2847705419U, // VST2LNd8_UPD + 833145163U, // VST2LNq16 + 0U, // VST2LNq16Pseudo + 0U, // VST2LNq16Pseudo_UPD + 2846656843U, // VST2LNq16_UPD + 833669451U, // VST2LNq32 + 0U, // VST2LNq32Pseudo + 0U, // VST2LNq32Pseudo_UPD + 2847181131U, // VST2LNq32_UPD + 3691571531U, // VST2b16 + 3758664011U, // VST2b16wb_fixed + 3825781067U, // VST2b16wb_register + 3692095819U, // VST2b32 + 3759188299U, // VST2b32wb_fixed + 3826305355U, // VST2b32wb_register + 3692620107U, // VST2b8 + 3759712587U, // VST2b8wb_fixed + 3826829643U, // VST2b8wb_register + 3490244939U, // VST2d16 + 3557337419U, // VST2d16wb_fixed + 3624454475U, // VST2d16wb_register + 3490769227U, // VST2d32 + 3557861707U, // VST2d32wb_fixed + 3624978763U, // VST2d32wb_register + 3491293515U, // VST2d8 + 3558385995U, // VST2d8wb_fixed + 3625503051U, // VST2d8wb_register + 2953374027U, // VST2q16 + 0U, // VST2q16Pseudo + 0U, // VST2q16PseudoWB_fixed + 0U, // VST2q16PseudoWB_register + 3020466507U, // VST2q16wb_fixed + 3087583563U, // VST2q16wb_register + 2953898315U, // VST2q32 + 0U, // VST2q32Pseudo + 0U, // VST2q32PseudoWB_fixed + 0U, // VST2q32PseudoWB_register + 3020990795U, // VST2q32wb_fixed + 3088107851U, // VST2q32wb_register + 2954422603U, // VST2q8 + 0U, // VST2q8Pseudo + 0U, // VST2q8PseudoWB_fixed + 0U, // VST2q8PseudoWB_register + 3021515083U, // VST2q8wb_fixed + 3088632139U, // VST2q8wb_register + 833218912U, // VST3LNd16 + 0U, // VST3LNd16Pseudo + 0U, // VST3LNd16Pseudo_UPD + 2846681440U, // VST3LNd16_UPD + 833743200U, // VST3LNd32 + 0U, // VST3LNd32Pseudo + 0U, // VST3LNd32Pseudo_UPD + 2847205728U, // VST3LNd32_UPD + 834267488U, // VST3LNd8 + 0U, // VST3LNd8Pseudo + 0U, // VST3LNd8Pseudo_UPD + 2847730016U, // VST3LNd8_UPD + 833218912U, // VST3LNq16 + 0U, // VST3LNq16Pseudo + 0U, // VST3LNq16Pseudo_UPD + 2846681440U, // VST3LNq16_UPD + 833743200U, // VST3LNq32 + 0U, // VST3LNq32Pseudo + 0U, // VST3LNq32Pseudo_UPD + 2847205728U, // VST3LNq32_UPD + 833145184U, // VST3d16 + 0U, // VST3d16Pseudo + 0U, // VST3d16Pseudo_UPD + 2846656864U, // VST3d16_UPD + 833669472U, // VST3d32 + 0U, // VST3d32Pseudo + 0U, // VST3d32Pseudo_UPD + 2847181152U, // VST3d32_UPD + 834193760U, // VST3d8 + 0U, // VST3d8Pseudo + 0U, // VST3d8Pseudo_UPD + 2847705440U, // VST3d8_UPD + 833145184U, // VST3q16 + 0U, // VST3q16Pseudo_UPD + 2846656864U, // VST3q16_UPD + 0U, // VST3q16oddPseudo + 0U, // VST3q16oddPseudo_UPD + 833669472U, // VST3q32 + 0U, // VST3q32Pseudo_UPD + 2847181152U, // VST3q32_UPD + 0U, // VST3q32oddPseudo + 0U, // VST3q32oddPseudo_UPD + 834193760U, // VST3q8 + 0U, // VST3q8Pseudo_UPD + 2847705440U, // VST3q8_UPD + 0U, // VST3q8oddPseudo + 0U, // VST3q8oddPseudo_UPD + 833390966U, // VST4LNd16 + 0U, // VST4LNd16Pseudo + 0U, // VST4LNd16Pseudo_UPD + 2846665078U, // VST4LNd16_UPD + 833915254U, // VST4LNd32 + 0U, // VST4LNd32Pseudo + 0U, // VST4LNd32Pseudo_UPD + 2847189366U, // VST4LNd32_UPD + 834439542U, // VST4LNd8 + 0U, // VST4LNd8Pseudo + 0U, // VST4LNd8Pseudo_UPD + 2847713654U, // VST4LNd8_UPD + 833390966U, // VST4LNq16 + 0U, // VST4LNq16Pseudo + 0U, // VST4LNq16Pseudo_UPD + 2846665078U, // VST4LNq16_UPD + 833915254U, // VST4LNq32 + 0U, // VST4LNq32Pseudo + 0U, // VST4LNq32Pseudo_UPD + 2847189366U, // VST4LNq32_UPD + 833218934U, // VST4d16 + 0U, // VST4d16Pseudo + 0U, // VST4d16Pseudo_UPD + 2846681462U, // VST4d16_UPD + 833743222U, // VST4d32 + 0U, // VST4d32Pseudo + 0U, // VST4d32Pseudo_UPD + 2847205750U, // VST4d32_UPD + 834267510U, // VST4d8 + 0U, // VST4d8Pseudo + 0U, // VST4d8Pseudo_UPD + 2847730038U, // VST4d8_UPD + 833218934U, // VST4q16 + 0U, // VST4q16Pseudo_UPD + 2846681462U, // VST4q16_UPD + 0U, // VST4q16oddPseudo + 0U, // VST4q16oddPseudo_UPD + 833743222U, // VST4q32 + 0U, // VST4q32Pseudo_UPD + 2847205750U, // VST4q32_UPD + 0U, // VST4q32oddPseudo + 0U, // VST4q32oddPseudo_UPD + 834267510U, // VST4q8 + 0U, // VST4q8Pseudo_UPD + 2847730038U, // VST4q8_UPD + 0U, // VST4q8oddPseudo + 0U, // VST4q8oddPseudo_UPD + 875064311U, // VSTMDDB_UPD + 2722595U, // VSTMDIA + 875064099U, // VSTMDIA_UPD + 0U, // VSTMQIA + 875064311U, // VSTMSDB_UPD + 2722595U, // VSTMSIA + 875064099U, // VSTMSIA_UPD + 2683344U, // VSTRD + 586192U, // VSTRH + 2683344U, // VSTRS + 2512417232U, // VSTR_FPCXTNS_off + 700510672U, // VSTR_FPCXTNS_post + 2579558864U, // VSTR_FPCXTNS_pre + 2512941520U, // VSTR_FPCXTS_off + 701034960U, // VSTR_FPCXTS_post + 2580083152U, // VSTR_FPCXTS_pre + 2513465808U, // VSTR_FPSCR_NZCVQC_off + 701559248U, // VSTR_FPSCR_NZCVQC_post + 2580607440U, // VSTR_FPSCR_NZCVQC_pre + 2513990096U, // VSTR_FPSCR_off + 702083536U, // VSTR_FPSCR_post + 2581131728U, // VSTR_FPSCR_pre + 2648764880U, // VSTR_P0_off + 1575006672U, // VSTR_P0_post + 2715857360U, // VSTR_P0_pre + 2515038672U, // VSTR_VPR_off + 703132112U, // VSTR_VPR_post + 2582180304U, // VSTR_VPR_pre + 946924771U, // VSUBD + 7924963U, // VSUBH + 895021188U, // VSUBHNv2i32 + 13693060U, // VSUBHNv4i16 + 14217348U, // VSUBHNv8i8 + 11071320U, // VSUBLsv2i64 + 10547032U, // VSUBLsv4i32 + 11595608U, // VSUBLsv8i16 + 12644184U, // VSUBLuv2i64 + 12119896U, // VSUBLuv4i32 + 13168472U, // VSUBLuv8i16 + 8449251U, // VSUBS + 11072544U, // VSUBWsv2i64 + 10548256U, // VSUBWsv4i32 + 11596832U, // VSUBWsv8i16 + 12645408U, // VSUBWuv2i64 + 12121120U, // VSUBWuv4i32 + 13169696U, // VSUBWuv8i16 + 8449251U, // VSUBfd + 8449251U, // VSUBfq + 7924963U, // VSUBhd + 7924963U, // VSUBhq + 14740707U, // VSUBv16i8 + 895020259U, // VSUBv1i64 + 13692131U, // VSUBv2i32 + 895020259U, // VSUBv2i64 + 14216419U, // VSUBv4i16 + 13692131U, // VSUBv4i32 + 14216419U, // VSUBv8i16 + 14740707U, // VSUBv8i8 + 943285953U, // VSUDOTDI + 943285953U, // VSUDOTQI + 2666836U, // VSWPd + 2666836U, // VSWPq + 1634131U, // VTBL1 + 1634131U, // VTBL2 + 1634131U, // VTBL3 + 0U, // VTBL3Pseudo + 1634131U, // VTBL4 + 0U, // VTBL4Pseudo + 1619149U, // VTBX1 + 1619149U, // VTBX2 + 1619149U, // VTBX3 + 0U, // VTBX3Pseudo + 1619149U, // VTBX4 + 0U, // VTBX4Pseudo + 37286771U, // VTOSHD + 958460787U, // VTOSHH + 37811059U, // VTOSHS + 1101033941U, // VTOSIRD + 1112043989U, // VTOSIRH + 1093169621U, // VTOSIRS + 1101034355U, // VTOSIZD + 1112044403U, // VTOSIZH + 1093170035U, // VTOSIZS + 966849395U, // VTOSLD + 977859443U, // VTOSLH + 958985075U, // VTOSLS + 38859635U, // VTOUHD + 959509363U, // VTOUHH + 39383923U, // VTOUHS + 1113616853U, // VTOUIRD + 1114141141U, // VTOUIRH + 1094218197U, // VTOUIRS + 1113617267U, // VTOUIZD + 1114141555U, // VTOUIZH + 1094218611U, // VTOUIZS + 979432307U, // VTOULD + 979956595U, // VTOULH + 960033651U, // VTOULS + 569546U, // VTRNd16 + 1093834U, // VTRNd32 + 1618122U, // VTRNd8 + 569546U, // VTRNq16 + 1093834U, // VTRNq32 + 1618122U, // VTRNq8 + 1635144U, // VTSTv16i8 + 1110856U, // VTSTv2i32 + 586568U, // VTSTv4i16 + 1110856U, // VTSTv4i32 + 586568U, // VTSTv8i16 + 1635144U, // VTSTv8i8 + 943285964U, // VUDOTD + 943285964U, // VUDOTDI + 943285964U, // VUDOTQ + 943285964U, // VUDOTQI + 40956787U, // VUHTOD + 956363635U, // VUHTOH + 41481075U, // VUHTOS + 1115714419U, // VUITOD + 1116238707U, // VUITOH + 1092121459U, // VUITOS + 981529459U, // VULTOD + 982053747U, // VULTOH + 957936499U, // VULTOS + 943285942U, // VUMMLA + 943285921U, // VUSDOTD + 943285921U, // VUSDOTDI + 943285921U, // VUSDOTQ + 943285921U, // VUSDOTQI + 943285898U, // VUSMMLA + 569689U, // VUZPd16 + 1618265U, // VUZPd8 + 569689U, // VUZPq16 + 1093977U, // VUZPq32 + 1618265U, // VUZPq8 + 569616U, // VZIPd16 + 1618192U, // VZIPd8 + 569616U, // VZIPq16 + 1093904U, // VZIPq32 + 1618192U, // VZIPq8 + 2722546U, // sysLDMDA + 875064050U, // sysLDMDA_UPD + 2722801U, // sysLDMDB + 875064305U, // sysLDMDB_UPD + 2723919U, // sysLDMIA + 875065423U, // sysLDMIA_UPD + 2722820U, // sysLDMIB + 875064324U, // sysLDMIB_UPD + 2722552U, // sysSTMDA + 875064056U, // sysSTMDA_UPD + 2722808U, // sysSTMDB + 875064312U, // sysSTMDB_UPD + 2723954U, // sysSTMIA + 875065458U, // sysSTMIA_UPD + 2722826U, // sysSTMIB + 875064330U, // sysSTMIB_UPD + 2632984U, // t2ADCri + 43003160U, // t2ADCrr + 43060504U, // t2ADCrs + 43003228U, // t2ADDri + 2683943U, // t2ADDri12 + 43003228U, // t2ADDrr + 43060572U, // t2ADDrs + 43003228U, // t2ADDspImm + 2683943U, // t2ADDspImm12 + 43020658U, // t2ADR + 2633117U, // t2ANDri + 43003293U, // t2ANDrr + 43060637U, // t2ANDrs + 43004339U, // t2ASRri + 43004339U, // t2ASRrr + 43092930U, // t2B + 2682144U, // t2BFC + 2666244U, // t2BFI + 2649985U, // t2BFLi + 2651500U, // t2BFLr + 2649594U, // t2BFi + 875644815U, // t2BFic + 2651421U, // t2BFr + 2632997U, // t2BICri + 43003173U, // t2BICrr + 43060517U, // t2BICrs + 2723606U, // t2BXJ + 43092930U, // t2Bcc + 1210708236U, // t2CDP + 1210706229U, // t2CDP2 + 4830480U, // t2CLREX + 2754195556U, // t2CLRM + 2651583U, // t2CLZ + 43020453U, // t2CMNri + 43020453U, // t2CMNzrr + 43053221U, // t2CMNzrs + 43020566U, // t2CMPri + 43020566U, // t2CMPrr + 43053334U, // t2CMPrs + 4802479U, // t2CPS1p + 1385345574U, // t2CPS2p + 1344975398U, // t2CPS3p + 875644665U, // t2CRC32B + 875644673U, // t2CRC32CB + 875644783U, // t2CRC32CH + 875644898U, // t2CRC32CW + 875644775U, // t2CRC32H + 875644890U, // t2CRC32W + 875644817U, // t2CSEL + 875644716U, // t2CSINC + 875644869U, // t2CSINV + 875644768U, // t2CSNEG + 2723330U, // t2DBG + 4827396U, // t2DCPS1 + 4827461U, // t2DCPS2 + 4827482U, // t2DCPS3 + 875644837U, // t2DLS + 3895036979U, // t2DMB + 3895037075U, // t2DSB + 2634145U, // t2EORri + 43004321U, // t2EORrr + 43061665U, // t2EORrs + 43094745U, // t2HINT + 4802508U, // t2HVC + 3962145943U, // t2ISB + 69751465U, // t2IT + 0U, // t2Int_eh_sjlj_setjmp + 0U, // t2Int_eh_sjlj_setjmp_nofp + 2648814U, // t2LDA + 2649023U, // t2LDAB + 2651390U, // t2LDAEX + 2649334U, // t2LDAEXB + 2682297U, // t2LDAEXD + 2649820U, // t2LDAEXH + 2649620U, // t2LDAH + 1210625818U, // t2LDC2L_OFFSET + 1210625818U, // t2LDC2L_OPTION + 1210625818U, // t2LDC2L_POST + 1210625818U, // t2LDC2L_PRE + 1210624283U, // t2LDC2_OFFSET + 1210624283U, // t2LDC2_OPTION + 1210624283U, // t2LDC2_POST + 1210624283U, // t2LDC2_PRE + 1210625886U, // t2LDCL_OFFSET + 1210625886U, // t2LDCL_OPTION + 1210625886U, // t2LDCL_POST + 1210625886U, // t2LDCL_PRE + 1210625308U, // t2LDC_OFFSET + 1210625308U, // t2LDC_OPTION + 1210625308U, // t2LDC_POST + 1210625308U, // t2LDC_PRE + 2722801U, // t2LDMDB + 875064305U, // t2LDMDB_UPD + 43094095U, // t2LDMIA + 915435599U, // t2LDMIA_UPD + 2683505U, // t2LDRBT + 2665608U, // t2LDRB_POST + 2665608U, // t2LDRB_PRE + 43052168U, // t2LDRBi12 + 2681992U, // t2LDRBi8 + 43019400U, // t2LDRBpci + 43035784U, // t2LDRBs + 2674082U, // t2LDRD_POST + 2674082U, // t2LDRD_PRE + 2665890U, // t2LDRDi8 + 2684170U, // t2LDREX + 2649348U, // t2LDREXB + 2682311U, // t2LDREXD + 2649834U, // t2LDREXH + 2683540U, // t2LDRHT + 2666116U, // t2LDRH_POST + 2666116U, // t2LDRH_PRE + 43052676U, // t2LDRHi12 + 2682500U, // t2LDRHi8 + 43019908U, // t2LDRHpci + 43036292U, // t2LDRHs + 2683517U, // t2LDRSBT + 2665627U, // t2LDRSB_POST + 2665627U, // t2LDRSB_PRE + 43052187U, // t2LDRSBi12 + 2682011U, // t2LDRSBi8 + 43019419U, // t2LDRSBpci + 43035803U, // t2LDRSBs + 2683552U, // t2LDRSHT + 2666155U, // t2LDRSH_POST + 2666155U, // t2LDRSH_PRE + 43052715U, // t2LDRSHi12 + 2682539U, // t2LDRSHi8 + 43019947U, // t2LDRSHpci + 43036331U, // t2LDRSHs + 2683699U, // t2LDRT + 2666871U, // t2LDR_POST + 2666871U, // t2LDR_PRE + 43053431U, // t2LDRi12 + 2683255U, // t2LDRi8 + 43020663U, // t2LDRpci + 43037047U, // t2LDRs + 4802391U, // t2LE + 1077503831U, // t2LEUpdate + 43003938U, // t2LSLri + 43003938U, // t2LSLrr + 43004346U, // t2LSRri + 43004346U, // t2LSRrr + 1210708334U, // t2MCR + 1210706234U, // t2MCR2 + 1210634665U, // t2MCRR + 1210632511U, // t2MCRR2 + 2665266U, // t2MLA + 2667006U, // t2MLS + 2683768U, // t2MOVTi16 + 43029526U, // t2MOVi + 2651197U, // t2MOVi16 + 43029526U, // t2MOVr + 43020847U, // t2MOVsra_flag + 43020852U, // t2MOVsrl_flag + 1009380659U, // t2MRC + 1009379616U, // t2MRC2 + 1680395575U, // t2MRRC + 1680394533U, // t2MRRC2 + 2724395U, // t2MRS_AR + 2650667U, // t2MRS_M + 2650667U, // t2MRSbanked + 2724395U, // t2MRSsys_AR + 1747481023U, // t2MSR_AR + 1747481023U, // t2MSR_M + 1814589887U, // t2MSRbanked + 2682930U, // t2MUL + 2658550U, // t2MVNi + 43028726U, // t2MVNr + 43004150U, // t2MVNs + 2633926U, // t2ORNri + 2633926U, // t2ORNrr + 2691270U, // t2ORNrs + 2634159U, // t2ORRri + 43004335U, // t2ORRrr + 43061679U, // t2ORRrs + 2667100U, // t2PKHBT + 2665644U, // t2PKHTB + 4029183020U, // t2PLDWi12 + 4096291884U, // t2PLDWi8 + 4163433516U, // t2PLDWs + 4029181329U, // t2PLDi12 + 4096290193U, // t2PLDi8 + 4230581649U, // t2PLDpci + 4163431825U, // t2PLDs + 4029181704U, // t2PLIi12 + 4096290568U, // t2PLIi8 + 4230582024U, // t2PLIpci + 4163432200U, // t2PLIs + 2682240U, // t2QADD + 2681296U, // t2QADD16 + 2681399U, // t2QADD8 + 2684290U, // t2QASX + 2682214U, // t2QDADD + 2682065U, // t2QDSUB + 2684036U, // t2QSAX + 2682078U, // t2QSUB + 2681258U, // t2QSUB16 + 2681360U, // t2QSUB8 + 2650791U, // t2RBIT + 43021285U, // t2REV + 43018740U, // t2REV16 + 43019958U, // t2REVSH + 2722794U, // t2RFEDB + 2722794U, // t2RFEDBW + 2722582U, // t2RFEIA + 2722582U, // t2RFEIAW + 43004325U, // t2RORri + 43004325U, // t2RORrr + 2659697U, // t2RRX + 43003037U, // t2RSBri + 2632861U, // t2RSBrr + 2690205U, // t2RSBrs + 2681303U, // t2SADD16 + 2681405U, // t2SADD8 + 2684295U, // t2SASX + 3220U, // t2SB + 2632979U, // t2SBCri + 43003155U, // t2SBCrr + 43060499U, // t2SBCrs + 2667804U, // t2SBFX + 2683881U, // t2SDIV + 2682749U, // t2SEL + 4802455U, // t2SETPAN + 4828689U, // t2SG + 2681279U, // t2SHADD16 + 2681384U, // t2SHADD8 + 2684277U, // t2SHASX + 2684023U, // t2SHSAX + 2681241U, // t2SHSUB16 + 2681345U, // t2SHSUB8 + 2723119U, // t2SMC + 2665424U, // t2SMLABB + 2667093U, // t2SMLABT + 2665800U, // t2SMLAD + 2667730U, // t2SMLADX + 2748225U, // t2SMLAL + 2747351U, // t2SMLALBB + 2749026U, // t2SMLALBT + 2747786U, // t2SMLALD + 2749664U, // t2SMLALDX + 2747570U, // t2SMLALTB + 2749268U, // t2SMLALTT + 2665637U, // t2SMLATB + 2667341U, // t2SMLATT + 2665704U, // t2SMLAWB + 2667389U, // t2SMLAWT + 2665901U, // t2SMLSD + 2667760U, // t2SMLSDX + 2747797U, // t2SMLSLD + 2749672U, // t2SMLSLDX + 2665270U, // t2SMMLA + 2666855U, // t2SMMLAR + 2667004U, // t2SMMLS + 2666935U, // t2SMMLSR + 2682934U, // t2SMMUL + 2683289U, // t2SMMULR + 2682190U, // t2SMUAD + 2684121U, // t2SMUADX + 2681823U, // t2SMULBB + 2683498U, // t2SMULBT + 2666471U, // t2SMULL + 2682042U, // t2SMULTB + 2683740U, // t2SMULTT + 2682095U, // t2SMULWB + 2683780U, // t2SMULWT + 2682291U, // t2SMUSD + 2684151U, // t2SMUSDX + 43617278U, // t2SRSDB + 44141566U, // t2SRSDB_UPD + 43617066U, // t2SRSIA + 44141354U, // t2SRSIA_UPD + 2667078U, // t2SSAT + 2681317U, // t2SSAT16 + 2684041U, // t2SSAX + 2681265U, // t2SSUB16 + 2681366U, // t2SSUB8 + 1210625824U, // t2STC2L_OFFSET + 1210625824U, // t2STC2L_OPTION + 1210625824U, // t2STC2L_POST + 1210625824U, // t2STC2L_PRE + 1210624299U, // t2STC2_OFFSET + 1210624299U, // t2STC2_OPTION + 1210624299U, // t2STC2_POST + 1210624299U, // t2STC2_PRE + 1210625891U, // t2STCL_OFFSET + 1210625891U, // t2STCL_OPTION + 1210625891U, // t2STCL_POST + 1210625891U, // t2STCL_PRE + 1210625344U, // t2STC_OFFSET + 1210625344U, // t2STC_OPTION + 1210625344U, // t2STC_POST + 1210625344U, // t2STC_PRE + 2650156U, // t2STL + 2649127U, // t2STLB + 2684164U, // t2STLEX + 2682109U, // t2STLEXB + 2665920U, // t2STLEXD + 2682595U, // t2STLEXH + 2649696U, // t2STLH + 2722808U, // t2STMDB + 875064312U, // t2STMDB_UPD + 43094130U, // t2STMIA + 915435634U, // t2STMIA_UPD + 2683511U, // t2STRBT + 875080846U, // t2STRB_POST + 875080846U, // t2STRB_PRE + 43052174U, // t2STRBi12 + 2681998U, // t2STRBi8 + 43035790U, // t2STRBs + 875089320U, // t2STRD_POST + 875089320U, // t2STRD_PRE + 2665896U, // t2STRDi8 + 2667798U, // t2STREX + 2682123U, // t2STREXB + 2665934U, // t2STREXD + 2682609U, // t2STREXH + 2683546U, // t2STRHT + 875081354U, // t2STRH_POST + 875081354U, // t2STRH_PRE + 43052682U, // t2STRHi12 + 2682506U, // t2STRHi8 + 43036298U, // t2STRHs + 2683710U, // t2STRT + 875082193U, // t2STR_POST + 875082193U, // t2STR_PRE + 43053521U, // t2STRi12 + 2683345U, // t2STRi8 + 43037137U, // t2STRs + 44667378U, // t2SUBS_PC_LR + 43003091U, // t2SUBri + 2683937U, // t2SUBri12 + 43003091U, // t2SUBrr + 43060435U, // t2SUBrs + 43003091U, // t2SUBspImm + 2683937U, // t2SUBspImm12 + 2665412U, // t2SXTAB + 2664827U, // t2SXTAB16 + 2666026U, // t2SXTAH + 43052231U, // t2SXTB + 2681227U, // t2SXTB16 + 43052732U, // t2SXTH + 2649062U, // t2TBB + 69758518U, // t2TBH + 43020643U, // t2TEQri + 43020643U, // t2TEQrr + 43053411U, // t2TEQrs + 136940705U, // t2TSB + 43021129U, // t2TSTri + 43021129U, // t2TSTrr + 43053897U, // t2TSTrs + 2650961U, // t2TT + 2648954U, // t2TTA + 2650704U, // t2TTAT + 2650979U, // t2TTT + 2681310U, // t2UADD16 + 2681411U, // t2UADD8 + 2684300U, // t2UASX + 2667809U, // t2UBFX + 4802515U, // t2UDF + 2683886U, // t2UDIV + 2681287U, // t2UHADD16 + 2681391U, // t2UHADD8 + 2684283U, // t2UHASX + 2684029U, // t2UHSAX + 2681249U, // t2UHSUB16 + 2681352U, // t2UHSUB8 + 2748198U, // t2UMAAL + 2748231U, // t2UMLAL + 2666477U, // t2UMULL + 2681295U, // t2UQADD16 + 2681398U, // t2UQADD8 + 2684289U, // t2UQASX + 2684035U, // t2UQSAX + 2681257U, // t2UQSUB16 + 2681359U, // t2UQSUB8 + 2681378U, // t2USAD8 + 2664954U, // t2USADA8 + 2667083U, // t2USAT + 2681324U, // t2USAT16 + 2684046U, // t2USAX + 2681272U, // t2USUB16 + 2681372U, // t2USUB8 + 2665418U, // t2UXTAB + 2664835U, // t2UXTAB16 + 2666032U, // t2UXTAH + 43052236U, // t2UXTB + 2681234U, // t2UXTB16 + 43052737U, // t2UXTH + 875644842U, // t2WLS + 1186278680U, // tADC + 2682204U, // tADDhirr + 850734428U, // tADDi3 + 1186278748U, // tADDi8 + 2682204U, // tADDrSP + 2682204U, // tADDrSPi + 850734428U, // tADDrr + 2682204U, // tADDspi + 2682204U, // tADDspr + 2650482U, // tADR + 1186278813U, // tAND + 850735539U, // tASRri + 1186279859U, // tASRrr + 2722754U, // tB + 1186278693U, // tBIC + 4802495U, // tBKPT + 808038229U, // tBL + 808038941U, // tBLXNSr + 808039784U, // tBLXi + 808039784U, // tBLXr + 2725058U, // tBX + 2724376U, // tBXNS + 2722754U, // tBcc + 875644927U, // tCBNZ + 875644922U, // tCBZ + 2650277U, // tCMNz + 2650390U, // tCMPhir + 2650390U, // tCMPi8 + 2650390U, // tCMPr + 1342353958U, // tCPS + 1186279841U, // tEOR + 2724569U, // tHINT + 4802490U, // tHLT + 0U, // tInt_WIN_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_setjmp + 2723919U, // tLDMIA + 2681992U, // tLDRBi + 2681992U, // tLDRBr + 2682500U, // tLDRHi + 2682500U, // tLDRHr + 2682011U, // tLDRSB + 2682539U, // tLDRSH + 2683255U, // tLDRi + 2650487U, // tLDRpci + 2683255U, // tLDRr + 2683255U, // tLDRspi + 850735138U, // tLSLri + 1186279458U, // tLSLrr + 850735546U, // tLSRri + 1186279866U, // tLSRrr + 875644852U, // tMOVSr + 1119695894U, // tMOVi8 + 2651158U, // tMOVr + 850735154U, // tMUL + 1119695094U, // tMVN + 1186279855U, // tORR + 0U, // tPICADD + 2754195738U, // tPOP + 2754195121U, // tPUSH + 2651109U, // tREV + 2648564U, // tREV16 + 2649782U, // tREVSH + 1186279845U, // tROR + 2059218077U, // tRSB + 1186278675U, // tSBC + 272207U, // tSETEND + 875065458U, // tSTMIA_UPD + 2681998U, // tSTRBi + 2681998U, // tSTRBr + 2682506U, // tSTRHi + 2682506U, // tSTRHr + 2683345U, // tSTRi + 2683345U, // tSTRr + 2683345U, // tSTRspi + 850734291U, // tSUBi3 + 1186278611U, // tSUBi8 + 850734291U, // tSUBrr + 2682067U, // tSUBspi + 2723140U, // tSVC + 2649287U, // tSXTB + 2649788U, // tSXTH + 4359U, // tTRAP + 2650953U, // tTST + 4802395U, // tUDF + 2649292U, // tUXTB + 2649793U, // tUXTH + 2293U, // t__brkdiv0 + }; + + static const uint32_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABS + 0U, // ADDSri + 0U, // ADDSrr + 0U, // ADDSrsi + 0U, // ADDSrsr + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ASRi + 0U, // ASRr + 0U, // B + 0U, // BCCZi64 + 0U, // BCCi64 + 0U, // BLX_noip + 0U, // BLX_pred_noip + 0U, // BL_PUSHLR + 0U, // BMOVPCB_CALL + 0U, // BMOVPCRX_CALL + 0U, // BR_JTadd + 0U, // BR_JTm_i12 + 0U, // BR_JTm_rs + 0U, // BR_JTr + 0U, // BX_CALL + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_STRUCT_BYVAL_I32 + 0U, // CompilerBarrier + 0U, // ITasm + 0U, // Int_eh_sjlj_dispatchsetup + 0U, // Int_eh_sjlj_longjmp + 0U, // Int_eh_sjlj_setjmp + 0U, // Int_eh_sjlj_setjmp_nofp + 0U, // Int_eh_sjlj_setup_dispatch + 0U, // JUMPTABLE_ADDRS + 0U, // JUMPTABLE_INSTS + 0U, // JUMPTABLE_TBB + 0U, // JUMPTABLE_TBH + 0U, // LDMIA_RET + 128U, // LDRBT_POST + 16384U, // LDRConstPool + 128U, // LDRHTii + 0U, // LDRLIT_ga_abs + 0U, // LDRLIT_ga_pcrel + 0U, // LDRLIT_ga_pcrel_ldr + 128U, // LDRSBTii + 128U, // LDRSHTii + 128U, // LDRT_POST + 0U, // LEApcrel + 0U, // LEApcrelJT + 0U, // LOADDUAL + 0U, // LSLi + 0U, // LSLr + 0U, // LSRi + 0U, // LSRr + 0U, // MEMCPY + 0U, // MLAv5 + 0U, // MOVCCi + 0U, // MOVCCi16 + 0U, // MOVCCi32imm + 0U, // MOVCCr + 0U, // MOVCCsi + 0U, // MOVCCsr + 0U, // MOVPCRX + 0U, // MOVTi16_ga_pcrel + 0U, // MOV_ga_pcrel + 0U, // MOV_ga_pcrel_ldr + 0U, // MOVi16_ga_pcrel + 0U, // MOVi32imm + 0U, // MOVsra_flag + 0U, // MOVsrl_flag + 0U, // MQPRCopy + 0U, // MQQPRLoad + 0U, // MQQPRStore + 0U, // MQQQQPRLoad + 0U, // MQQQQPRStore + 0U, // MULv5 + 0U, // MVE_MEMCPYLOOPINST + 0U, // MVE_MEMSETLOOPINST + 0U, // MVNCCi + 0U, // PICADD + 0U, // PICLDR + 0U, // PICLDRB + 0U, // PICLDRH + 0U, // PICLDRSB + 0U, // PICLDRSH + 0U, // PICSTR + 0U, // PICSTRB + 0U, // PICSTRH + 0U, // RORi + 0U, // RORr + 0U, // RRX + 16384U, // RRXi + 0U, // RSBSri + 0U, // RSBSrsi + 0U, // RSBSrsr + 0U, // SMLALv5 + 0U, // SMULLv5 + 0U, // SPACE + 0U, // STOREDUAL + 128U, // STRBT_POST + 0U, // STRBi_preidx + 0U, // STRBr_preidx + 0U, // STRH_preidx + 128U, // STRT_POST + 0U, // STRi_preidx + 0U, // STRr_preidx + 0U, // SUBS_PC_LR + 0U, // SUBSri + 0U, // SUBSrr + 0U, // SUBSrsi + 0U, // SUBSrsr + 0U, // SpeculationBarrierISBDSBEndBB + 0U, // SpeculationBarrierSBEndBB + 0U, // TAILJMPd + 0U, // TAILJMPr + 0U, // TAILJMPr4 + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TPsoft + 0U, // UMLALv5 + 0U, // UMULLv5 + 16640U, // VLD1LNdAsm_16 + 16640U, // VLD1LNdAsm_32 + 16640U, // VLD1LNdAsm_8 + 33024U, // VLD1LNdWB_fixed_Asm_16 + 33024U, // VLD1LNdWB_fixed_Asm_32 + 33024U, // VLD1LNdWB_fixed_Asm_8 + 524544U, // VLD1LNdWB_register_Asm_16 + 524544U, // VLD1LNdWB_register_Asm_32 + 524544U, // VLD1LNdWB_register_Asm_8 + 16640U, // VLD2LNdAsm_16 + 16640U, // VLD2LNdAsm_32 + 16640U, // VLD2LNdAsm_8 + 33024U, // VLD2LNdWB_fixed_Asm_16 + 33024U, // VLD2LNdWB_fixed_Asm_32 + 33024U, // VLD2LNdWB_fixed_Asm_8 + 524544U, // VLD2LNdWB_register_Asm_16 + 524544U, // VLD2LNdWB_register_Asm_32 + 524544U, // VLD2LNdWB_register_Asm_8 + 16640U, // VLD2LNqAsm_16 + 16640U, // VLD2LNqAsm_32 + 33024U, // VLD2LNqWB_fixed_Asm_16 + 33024U, // VLD2LNqWB_fixed_Asm_32 + 524544U, // VLD2LNqWB_register_Asm_16 + 524544U, // VLD2LNqWB_register_Asm_32 + 2U, // VLD3DUPdAsm_16 + 2U, // VLD3DUPdAsm_32 + 2U, // VLD3DUPdAsm_8 + 4U, // VLD3DUPdWB_fixed_Asm_16 + 4U, // VLD3DUPdWB_fixed_Asm_32 + 4U, // VLD3DUPdWB_fixed_Asm_8 + 16768U, // VLD3DUPdWB_register_Asm_16 + 16768U, // VLD3DUPdWB_register_Asm_32 + 16768U, // VLD3DUPdWB_register_Asm_8 + 2U, // VLD3DUPqAsm_16 + 2U, // VLD3DUPqAsm_32 + 2U, // VLD3DUPqAsm_8 + 4U, // VLD3DUPqWB_fixed_Asm_16 + 4U, // VLD3DUPqWB_fixed_Asm_32 + 4U, // VLD3DUPqWB_fixed_Asm_8 + 16768U, // VLD3DUPqWB_register_Asm_16 + 16768U, // VLD3DUPqWB_register_Asm_32 + 16768U, // VLD3DUPqWB_register_Asm_8 + 16640U, // VLD3LNdAsm_16 + 16640U, // VLD3LNdAsm_32 + 16640U, // VLD3LNdAsm_8 + 33024U, // VLD3LNdWB_fixed_Asm_16 + 33024U, // VLD3LNdWB_fixed_Asm_32 + 33024U, // VLD3LNdWB_fixed_Asm_8 + 524544U, // VLD3LNdWB_register_Asm_16 + 524544U, // VLD3LNdWB_register_Asm_32 + 524544U, // VLD3LNdWB_register_Asm_8 + 16640U, // VLD3LNqAsm_16 + 16640U, // VLD3LNqAsm_32 + 33024U, // VLD3LNqWB_fixed_Asm_16 + 33024U, // VLD3LNqWB_fixed_Asm_32 + 524544U, // VLD3LNqWB_register_Asm_16 + 524544U, // VLD3LNqWB_register_Asm_32 + 518U, // VLD3dAsm_16 + 518U, // VLD3dAsm_32 + 518U, // VLD3dAsm_8 + 646U, // VLD3dWB_fixed_Asm_16 + 646U, // VLD3dWB_fixed_Asm_32 + 646U, // VLD3dWB_fixed_Asm_8 + 49926U, // VLD3dWB_register_Asm_16 + 49926U, // VLD3dWB_register_Asm_32 + 49926U, // VLD3dWB_register_Asm_8 + 2U, // VLD3qAsm_16 + 2U, // VLD3qAsm_32 + 2U, // VLD3qAsm_8 + 4U, // VLD3qWB_fixed_Asm_16 + 4U, // VLD3qWB_fixed_Asm_32 + 4U, // VLD3qWB_fixed_Asm_8 + 16768U, // VLD3qWB_register_Asm_16 + 16768U, // VLD3qWB_register_Asm_32 + 16768U, // VLD3qWB_register_Asm_8 + 2U, // VLD4DUPdAsm_16 + 2U, // VLD4DUPdAsm_32 + 2U, // VLD4DUPdAsm_8 + 4U, // VLD4DUPdWB_fixed_Asm_16 + 4U, // VLD4DUPdWB_fixed_Asm_32 + 4U, // VLD4DUPdWB_fixed_Asm_8 + 16768U, // VLD4DUPdWB_register_Asm_16 + 16768U, // VLD4DUPdWB_register_Asm_32 + 16768U, // VLD4DUPdWB_register_Asm_8 + 2U, // VLD4DUPqAsm_16 + 2U, // VLD4DUPqAsm_32 + 2U, // VLD4DUPqAsm_8 + 4U, // VLD4DUPqWB_fixed_Asm_16 + 4U, // VLD4DUPqWB_fixed_Asm_32 + 4U, // VLD4DUPqWB_fixed_Asm_8 + 16768U, // VLD4DUPqWB_register_Asm_16 + 16768U, // VLD4DUPqWB_register_Asm_32 + 16768U, // VLD4DUPqWB_register_Asm_8 + 16640U, // VLD4LNdAsm_16 + 16640U, // VLD4LNdAsm_32 + 16640U, // VLD4LNdAsm_8 + 33024U, // VLD4LNdWB_fixed_Asm_16 + 33024U, // VLD4LNdWB_fixed_Asm_32 + 33024U, // VLD4LNdWB_fixed_Asm_8 + 524544U, // VLD4LNdWB_register_Asm_16 + 524544U, // VLD4LNdWB_register_Asm_32 + 524544U, // VLD4LNdWB_register_Asm_8 + 16640U, // VLD4LNqAsm_16 + 16640U, // VLD4LNqAsm_32 + 33024U, // VLD4LNqWB_fixed_Asm_16 + 33024U, // VLD4LNqWB_fixed_Asm_32 + 524544U, // VLD4LNqWB_register_Asm_16 + 524544U, // VLD4LNqWB_register_Asm_32 + 518U, // VLD4dAsm_16 + 518U, // VLD4dAsm_32 + 518U, // VLD4dAsm_8 + 646U, // VLD4dWB_fixed_Asm_16 + 646U, // VLD4dWB_fixed_Asm_32 + 646U, // VLD4dWB_fixed_Asm_8 + 49926U, // VLD4dWB_register_Asm_16 + 49926U, // VLD4dWB_register_Asm_32 + 49926U, // VLD4dWB_register_Asm_8 + 2U, // VLD4qAsm_16 + 2U, // VLD4qAsm_32 + 2U, // VLD4qAsm_8 + 4U, // VLD4qWB_fixed_Asm_16 + 4U, // VLD4qWB_fixed_Asm_32 + 4U, // VLD4qWB_fixed_Asm_8 + 16768U, // VLD4qWB_register_Asm_16 + 16768U, // VLD4qWB_register_Asm_32 + 16768U, // VLD4qWB_register_Asm_8 + 0U, // VMOVD0 + 0U, // VMOVDcc + 0U, // VMOVHcc + 0U, // VMOVQ0 + 0U, // VMOVScc + 16640U, // VST1LNdAsm_16 + 16640U, // VST1LNdAsm_32 + 16640U, // VST1LNdAsm_8 + 33024U, // VST1LNdWB_fixed_Asm_16 + 33024U, // VST1LNdWB_fixed_Asm_32 + 33024U, // VST1LNdWB_fixed_Asm_8 + 524544U, // VST1LNdWB_register_Asm_16 + 524544U, // VST1LNdWB_register_Asm_32 + 524544U, // VST1LNdWB_register_Asm_8 + 16640U, // VST2LNdAsm_16 + 16640U, // VST2LNdAsm_32 + 16640U, // VST2LNdAsm_8 + 33024U, // VST2LNdWB_fixed_Asm_16 + 33024U, // VST2LNdWB_fixed_Asm_32 + 33024U, // VST2LNdWB_fixed_Asm_8 + 524544U, // VST2LNdWB_register_Asm_16 + 524544U, // VST2LNdWB_register_Asm_32 + 524544U, // VST2LNdWB_register_Asm_8 + 16640U, // VST2LNqAsm_16 + 16640U, // VST2LNqAsm_32 + 33024U, // VST2LNqWB_fixed_Asm_16 + 33024U, // VST2LNqWB_fixed_Asm_32 + 524544U, // VST2LNqWB_register_Asm_16 + 524544U, // VST2LNqWB_register_Asm_32 + 16640U, // VST3LNdAsm_16 + 16640U, // VST3LNdAsm_32 + 16640U, // VST3LNdAsm_8 + 33024U, // VST3LNdWB_fixed_Asm_16 + 33024U, // VST3LNdWB_fixed_Asm_32 + 33024U, // VST3LNdWB_fixed_Asm_8 + 524544U, // VST3LNdWB_register_Asm_16 + 524544U, // VST3LNdWB_register_Asm_32 + 524544U, // VST3LNdWB_register_Asm_8 + 16640U, // VST3LNqAsm_16 + 16640U, // VST3LNqAsm_32 + 33024U, // VST3LNqWB_fixed_Asm_16 + 33024U, // VST3LNqWB_fixed_Asm_32 + 524544U, // VST3LNqWB_register_Asm_16 + 524544U, // VST3LNqWB_register_Asm_32 + 518U, // VST3dAsm_16 + 518U, // VST3dAsm_32 + 518U, // VST3dAsm_8 + 646U, // VST3dWB_fixed_Asm_16 + 646U, // VST3dWB_fixed_Asm_32 + 646U, // VST3dWB_fixed_Asm_8 + 49926U, // VST3dWB_register_Asm_16 + 49926U, // VST3dWB_register_Asm_32 + 49926U, // VST3dWB_register_Asm_8 + 2U, // VST3qAsm_16 + 2U, // VST3qAsm_32 + 2U, // VST3qAsm_8 + 4U, // VST3qWB_fixed_Asm_16 + 4U, // VST3qWB_fixed_Asm_32 + 4U, // VST3qWB_fixed_Asm_8 + 16768U, // VST3qWB_register_Asm_16 + 16768U, // VST3qWB_register_Asm_32 + 16768U, // VST3qWB_register_Asm_8 + 16640U, // VST4LNdAsm_16 + 16640U, // VST4LNdAsm_32 + 16640U, // VST4LNdAsm_8 + 33024U, // VST4LNdWB_fixed_Asm_16 + 33024U, // VST4LNdWB_fixed_Asm_32 + 33024U, // VST4LNdWB_fixed_Asm_8 + 524544U, // VST4LNdWB_register_Asm_16 + 524544U, // VST4LNdWB_register_Asm_32 + 524544U, // VST4LNdWB_register_Asm_8 + 16640U, // VST4LNqAsm_16 + 16640U, // VST4LNqAsm_32 + 33024U, // VST4LNqWB_fixed_Asm_16 + 33024U, // VST4LNqWB_fixed_Asm_32 + 524544U, // VST4LNqWB_register_Asm_16 + 524544U, // VST4LNqWB_register_Asm_32 + 518U, // VST4dAsm_16 + 518U, // VST4dAsm_32 + 518U, // VST4dAsm_8 + 646U, // VST4dWB_fixed_Asm_16 + 646U, // VST4dWB_fixed_Asm_32 + 646U, // VST4dWB_fixed_Asm_8 + 49926U, // VST4dWB_register_Asm_16 + 49926U, // VST4dWB_register_Asm_32 + 49926U, // VST4dWB_register_Asm_8 + 2U, // VST4qAsm_16 + 2U, // VST4qAsm_32 + 2U, // VST4qAsm_8 + 4U, // VST4qWB_fixed_Asm_16 + 4U, // VST4qWB_fixed_Asm_32 + 4U, // VST4qWB_fixed_Asm_8 + 16768U, // VST4qWB_register_Asm_16 + 16768U, // VST4qWB_register_Asm_32 + 16768U, // VST4qWB_register_Asm_8 + 0U, // WIN__CHKSTK + 0U, // WIN__DBZCHK + 0U, // t2ABS + 0U, // t2ADDSri + 0U, // t2ADDSrr + 0U, // t2ADDSrs + 0U, // t2BF_LabelPseudo + 0U, // t2BR_JT + 0U, // t2DoLoopStart + 0U, // t2DoLoopStartTP + 0U, // t2LDMIA_RET + 16384U, // t2LDRBpcrel + 16384U, // t2LDRConstPool + 16384U, // t2LDRHpcrel + 16384U, // t2LDRSBpcrel + 16384U, // t2LDRSHpcrel + 896U, // t2LDR_POST_imm + 0U, // t2LDR_PRE_imm + 0U, // t2LDRpci_pic + 16384U, // t2LDRpcrel + 0U, // t2LEApcrel + 0U, // t2LEApcrelJT + 0U, // t2LoopDec + 0U, // t2LoopEnd + 0U, // t2LoopEndDec + 0U, // t2MOVCCasr + 0U, // t2MOVCCi + 0U, // t2MOVCCi16 + 0U, // t2MOVCCi32imm + 0U, // t2MOVCClsl + 0U, // t2MOVCClsr + 0U, // t2MOVCCr + 0U, // t2MOVCCror + 1024U, // t2MOVSsi + 1152U, // t2MOVSsr + 0U, // t2MOVTi16_ga_pcrel + 0U, // t2MOV_ga_pcrel + 0U, // t2MOVi16_ga_pcrel + 0U, // t2MOVi32imm + 1024U, // t2MOVsi + 1152U, // t2MOVsr + 0U, // t2MVNCCi + 0U, // t2RSBSri + 0U, // t2RSBSrs + 0U, // t2STRB_preidx + 0U, // t2STRH_preidx + 896U, // t2STR_POST_imm + 0U, // t2STR_PRE_imm + 0U, // t2STR_preidx + 0U, // t2SUBSri + 0U, // t2SUBSrr + 0U, // t2SUBSrs + 0U, // t2SpeculationBarrierISBDSBEndBB + 0U, // t2SpeculationBarrierSBEndBB + 0U, // t2TBB_JT + 0U, // t2TBH_JT + 0U, // t2WhileLoopSetup + 0U, // t2WhileLoopStart + 0U, // t2WhileLoopStartLR + 0U, // t2WhileLoopStartTP + 0U, // tADCS + 0U, // tADDSi3 + 0U, // tADDSi8 + 0U, // tADDSrr + 0U, // tADDframe + 0U, // tADJCALLSTACKDOWN + 0U, // tADJCALLSTACKUP + 0U, // tBLXNS_CALL + 0U, // tBLXr_noip + 0U, // tBL_PUSHLR + 0U, // tBRIND + 0U, // tBR_JTr + 0U, // tBXNS_RET + 0U, // tBX_CALL + 0U, // tBX_RET + 0U, // tBX_RET_vararg + 0U, // tBfar + 0U, // tCMP_SWAP_16 + 0U, // tCMP_SWAP_8 + 0U, // tLDMIA_UPD + 16384U, // tLDRConstPool + 0U, // tLDRLIT_ga_abs + 0U, // tLDRLIT_ga_pcrel + 0U, // tLDR_postidx + 0U, // tLDRpci_pic + 0U, // tLEApcrel + 0U, // tLEApcrelJT + 0U, // tLSLSri + 0U, // tMOVCCr_pseudo + 0U, // tPOP_RET + 0U, // tRSBS + 0U, // tSBCS + 0U, // tSUBSi3 + 0U, // tSUBSi8 + 0U, // tSUBSrr + 0U, // tTAILJMPd + 0U, // tTAILJMPdND + 0U, // tTAILJMPr + 0U, // tTBB_JT + 0U, // tTBH_JT + 0U, // tTPsoft + 1048576U, // ADCri + 0U, // ADCrr + 1572864U, // ADCrsi + 0U, // ADCrsr + 1048576U, // ADDri + 0U, // ADDrr + 1572864U, // ADDrsi + 0U, // ADDrsr + 1280U, // ADR + 2U, // AESD + 2U, // AESE + 2U, // AESIMC + 2U, // AESMC + 1048576U, // ANDri + 0U, // ANDrr + 1572864U, // ANDrsi + 0U, // ANDrsr + 1416U, // BF16VDOTI_VDOTD + 1416U, // BF16VDOTI_VDOTQ + 520U, // BF16VDOTS_VDOTD + 520U, // BF16VDOTS_VDOTQ + 2U, // BF16_VCVT + 2U, // BF16_VCVTB + 2U, // BF16_VCVTT + 1536U, // BFC + 2098816U, // BFI + 1048576U, // BICri + 0U, // BICrr + 1572864U, // BICrsi + 0U, // BICrsr + 0U, // BKPT + 0U, // BL + 0U, // BLX + 2U, // BLX_pred + 0U, // BLXi + 2U, // BL_pred + 0U, // BX + 2U, // BXJ + 0U, // BX_RET + 2U, // BX_pred + 2U, // Bcc + 2U, // CDE_CX1 + 16778U, // CDE_CX1A + 0U, // CDE_CX1D + 524U, // CDE_CX1DA + 16768U, // CDE_CX2 + 524682U, // CDE_CX2A + 520U, // CDE_CX2D + 2687756U, // CDE_CX2DA + 524672U, // CDE_CX3 + 34079114U, // CDE_CX3A + 2687752U, // CDE_CX3D + 70320908U, // CDE_CX3DA + 2U, // CDE_VCX1A_fpdp + 2U, // CDE_VCX1A_fpsp + 16778U, // CDE_VCX1A_vec + 2U, // CDE_VCX1_fpdp + 2U, // CDE_VCX1_fpsp + 18058U, // CDE_VCX1_vec + 18176U, // CDE_VCX2A_fpdp + 18176U, // CDE_VCX2A_fpsp + 524682U, // CDE_VCX2A_vec + 16768U, // CDE_VCX2_fpdp + 16768U, // CDE_VCX2_fpsp + 3671690U, // CDE_VCX2_vec + 4196096U, // CDE_VCX3A_fpdp + 4196096U, // CDE_VCX3A_fpsp + 34079114U, // CDE_VCX3A_vec + 524672U, // CDE_VCX3_fpdp + 524672U, // CDE_VCX3_fpsp + 37226122U, // CDE_VCX3_vec + 82702U, // CDP + 0U, // CDP2 + 0U, // CLREX + 16384U, // CLZ + 1920U, // CMNri + 16384U, // CMNzrr + 2048U, // CMNzrsi + 1152U, // CMNzrsr + 1920U, // CMPri + 16384U, // CMPrr + 2048U, // CMPrsi + 1152U, // CMPrsr + 0U, // CPS1p + 2U, // CPS2p + 18048U, // CPS3p + 18048U, // CRC32B + 18048U, // CRC32CB + 18048U, // CRC32CH + 18048U, // CRC32CW + 18048U, // CRC32H + 18048U, // CRC32W + 2U, // DBG + 0U, // DMB + 0U, // DSB + 1048576U, // EORri + 0U, // EORrr + 1572864U, // EORrsi + 0U, // EORrsr + 0U, // ERET + 16U, // FCONSTD + 2176U, // FCONSTH + 2176U, // FCONSTS + 530U, // FLDMXDB_UPD + 18688U, // FLDMXIA + 530U, // FLDMXIA_UPD + 0U, // FMSTAT + 530U, // FSTMXDB_UPD + 18688U, // FSTMXIA + 530U, // FSTMXIA_UPD + 2U, // HINT + 0U, // HLT + 0U, // HVC + 0U, // ISB + 128U, // LDA + 128U, // LDAB + 128U, // LDAEX + 128U, // LDAEXB + 0U, // LDAEXD + 128U, // LDAEXH + 128U, // LDAH + 0U, // LDC2L_OFFSET + 2432U, // LDC2L_OPTION + 2560U, // LDC2L_POST + 0U, // LDC2L_PRE + 0U, // LDC2_OFFSET + 2432U, // LDC2_OPTION + 2560U, // LDC2_POST + 0U, // LDC2_PRE + 2708U, // LDCL_OFFSET + 4721428U, // LDCL_OPTION + 5245716U, // LDCL_POST + 2964U, // LDCL_PRE + 2708U, // LDC_OFFSET + 4721428U, // LDC_OPTION + 5245716U, // LDC_POST + 2964U, // LDC_PRE + 18688U, // LDMDA + 530U, // LDMDA_UPD + 18688U, // LDMDB + 530U, // LDMDB_UPD + 18688U, // LDMIA + 530U, // LDMIA_UPD + 18688U, // LDMIB + 530U, // LDMIB_UPD + 5769984U, // LDRBT_POST_IMM + 5769984U, // LDRBT_POST_REG + 5769984U, // LDRB_POST_IMM + 5769984U, // LDRB_POST_REG + 3072U, // LDRB_PRE_IMM + 3200U, // LDRB_PRE_REG + 3328U, // LDRBi12 + 3456U, // LDRBrs + 6291456U, // LDRD + 40370176U, // LDRD_POST + 7340032U, // LDRD_PRE + 128U, // LDREX + 128U, // LDREXB + 0U, // LDREXD + 128U, // LDREXH + 3584U, // LDRH + 7867136U, // LDRHTi + 8391424U, // LDRHTr + 8915712U, // LDRH_POST + 3712U, // LDRH_PRE + 3584U, // LDRSB + 7867136U, // LDRSBTi + 8391424U, // LDRSBTr + 8915712U, // LDRSB_POST + 3712U, // LDRSB_PRE + 3584U, // LDRSH + 7867136U, // LDRSHTi + 8391424U, // LDRSHTr + 8915712U, // LDRSH_POST + 3712U, // LDRSH_PRE + 5769984U, // LDRT_POST_IMM + 5769984U, // LDRT_POST_REG + 5769984U, // LDR_POST_IMM + 5769984U, // LDR_POST_REG + 3072U, // LDR_PRE_IMM + 3200U, // LDR_PRE_REG + 3328U, // LDRcp + 3328U, // LDRi12 + 3456U, // LDRrs + 103908110U, // MCR + 3840U, // MCR2 + 137462542U, // MCRR + 9437568U, // MCRR2 + 33554432U, // MLA + 33554432U, // MLS + 0U, // MOVPCLR + 18048U, // MOVTi16 + 1920U, // MOVi + 16384U, // MOVi16 + 16384U, // MOVr + 16384U, // MOVr_TC + 2048U, // MOVsi + 1152U, // MOVsr + 115478U, // MRC + 3850U, // MRC2 + 0U, // MRRC + 0U, // MRRC2 + 24U, // MRS + 3968U, // MRSbanked + 26U, // MRSsys + 526U, // MSR + 0U, // MSRbanked + 28U, // MSRi + 0U, // MUL + 524288U, // MVE_ASRLi + 524288U, // MVE_ASRLr + 2U, // MVE_DLSTP_16 + 2U, // MVE_DLSTP_32 + 2U, // MVE_DLSTP_64 + 2U, // MVE_DLSTP_8 + 0U, // MVE_LCTP + 0U, // MVE_LETP + 524288U, // MVE_LSLLi + 524288U, // MVE_LSLLr + 524288U, // MVE_LSRL + 18048U, // MVE_SQRSHR + 9961472U, // MVE_SQRSHRL + 18048U, // MVE_SQSHL + 524288U, // MVE_SQSHLL + 18048U, // MVE_SRSHR + 524288U, // MVE_SRSHRL + 18048U, // MVE_UQRSHL + 9961472U, // MVE_UQRSHLL + 18048U, // MVE_UQSHL + 524288U, // MVE_UQSHLL + 18048U, // MVE_URSHR + 524288U, // MVE_URSHRL + 3671680U, // MVE_VABAVs16 + 3671680U, // MVE_VABAVs32 + 3671680U, // MVE_VABAVs8 + 3671680U, // MVE_VABAVu16 + 3671680U, // MVE_VABAVu32 + 3671680U, // MVE_VABAVu8 + 0U, // MVE_VABDf16 + 0U, // MVE_VABDf32 + 0U, // MVE_VABDs16 + 0U, // MVE_VABDs32 + 0U, // MVE_VABDs8 + 0U, // MVE_VABDu16 + 0U, // MVE_VABDu32 + 0U, // MVE_VABDu8 + 16384U, // MVE_VABSf16 + 16384U, // MVE_VABSf32 + 16384U, // MVE_VABSs16 + 16384U, // MVE_VABSs32 + 16384U, // MVE_VABSs8 + 3671680U, // MVE_VADC + 3671680U, // MVE_VADCI + 524288U, // MVE_VADDLVs32acc + 0U, // MVE_VADDLVs32no_acc + 524288U, // MVE_VADDLVu32acc + 0U, // MVE_VADDLVu32no_acc + 18048U, // MVE_VADDVs16acc + 16384U, // MVE_VADDVs16no_acc + 18048U, // MVE_VADDVs32acc + 16384U, // MVE_VADDVs32no_acc + 18048U, // MVE_VADDVs8acc + 16384U, // MVE_VADDVs8no_acc + 18048U, // MVE_VADDVu16acc + 16384U, // MVE_VADDVu16no_acc + 18048U, // MVE_VADDVu32acc + 16384U, // MVE_VADDVu32no_acc + 18048U, // MVE_VADDVu8acc + 16384U, // MVE_VADDVu8no_acc + 0U, // MVE_VADD_qr_f16 + 0U, // MVE_VADD_qr_f32 + 0U, // MVE_VADD_qr_i16 + 0U, // MVE_VADD_qr_i32 + 0U, // MVE_VADD_qr_i8 + 0U, // MVE_VADDf16 + 0U, // MVE_VADDf32 + 0U, // MVE_VADDi16 + 0U, // MVE_VADDi32 + 0U, // MVE_VADDi8 + 0U, // MVE_VAND + 0U, // MVE_VBIC + 4096U, // MVE_VBICimmi16 + 4096U, // MVE_VBICimmi32 + 0U, // MVE_VBRSR16 + 0U, // MVE_VBRSR32 + 0U, // MVE_VBRSR8 + 33554432U, // MVE_VCADDf16 + 33554432U, // MVE_VCADDf32 + 33554432U, // MVE_VCADDi16 + 33554432U, // MVE_VCADDi32 + 33554432U, // MVE_VCADDi8 + 16384U, // MVE_VCLSs16 + 16384U, // MVE_VCLSs32 + 16384U, // MVE_VCLSs8 + 16384U, // MVE_VCLZs16 + 16384U, // MVE_VCLZs32 + 16384U, // MVE_VCLZs8 + 37226112U, // MVE_VCMLAf16 + 37226112U, // MVE_VCMLAf32 + 0U, // MVE_VCMPf16 + 0U, // MVE_VCMPf16r + 0U, // MVE_VCMPf32 + 0U, // MVE_VCMPf32r + 0U, // MVE_VCMPi16 + 0U, // MVE_VCMPi16r + 0U, // MVE_VCMPi32 + 0U, // MVE_VCMPi32r + 0U, // MVE_VCMPi8 + 0U, // MVE_VCMPi8r + 0U, // MVE_VCMPs16 + 0U, // MVE_VCMPs16r + 0U, // MVE_VCMPs32 + 0U, // MVE_VCMPs32r + 0U, // MVE_VCMPs8 + 0U, // MVE_VCMPs8r + 0U, // MVE_VCMPu16 + 0U, // MVE_VCMPu16r + 0U, // MVE_VCMPu32 + 0U, // MVE_VCMPu32r + 0U, // MVE_VCMPu8 + 0U, // MVE_VCMPu8r + 33554432U, // MVE_VCMULf16 + 33554432U, // MVE_VCMULf32 + 2U, // MVE_VCTP16 + 2U, // MVE_VCTP32 + 2U, // MVE_VCTP64 + 2U, // MVE_VCTP8 + 2U, // MVE_VCVTf16f32bh + 2U, // MVE_VCVTf16f32th + 534U, // MVE_VCVTf16s16_fix + 0U, // MVE_VCVTf16s16n + 534U, // MVE_VCVTf16u16_fix + 0U, // MVE_VCVTf16u16n + 0U, // MVE_VCVTf32f16bh + 0U, // MVE_VCVTf32f16th + 534U, // MVE_VCVTf32s32_fix + 0U, // MVE_VCVTf32s32n + 534U, // MVE_VCVTf32u32_fix + 0U, // MVE_VCVTf32u32n + 534U, // MVE_VCVTs16f16_fix + 0U, // MVE_VCVTs16f16a + 0U, // MVE_VCVTs16f16m + 0U, // MVE_VCVTs16f16n + 0U, // MVE_VCVTs16f16p + 0U, // MVE_VCVTs16f16z + 534U, // MVE_VCVTs32f32_fix + 0U, // MVE_VCVTs32f32a + 0U, // MVE_VCVTs32f32m + 0U, // MVE_VCVTs32f32n + 0U, // MVE_VCVTs32f32p + 0U, // MVE_VCVTs32f32z + 534U, // MVE_VCVTu16f16_fix + 0U, // MVE_VCVTu16f16a + 0U, // MVE_VCVTu16f16m + 0U, // MVE_VCVTu16f16n + 0U, // MVE_VCVTu16f16p + 0U, // MVE_VCVTu16f16z + 534U, // MVE_VCVTu32f32_fix + 0U, // MVE_VCVTu32f32a + 0U, // MVE_VCVTu32f32m + 0U, // MVE_VCVTu32f32n + 0U, // MVE_VCVTu32f32p + 0U, // MVE_VCVTu32f32z + 3670016U, // MVE_VDDUPu16 + 3670016U, // MVE_VDDUPu32 + 3670016U, // MVE_VDDUPu8 + 16384U, // MVE_VDUP16 + 16384U, // MVE_VDUP32 + 16384U, // MVE_VDUP8 + 37224448U, // MVE_VDWDUPu16 + 37224448U, // MVE_VDWDUPu32 + 37224448U, // MVE_VDWDUPu8 + 0U, // MVE_VEOR + 3671680U, // MVE_VFMA_qr_Sf16 + 3671680U, // MVE_VFMA_qr_Sf32 + 3671680U, // MVE_VFMA_qr_f16 + 3671680U, // MVE_VFMA_qr_f32 + 3671680U, // MVE_VFMAf16 + 3671680U, // MVE_VFMAf32 + 3671680U, // MVE_VFMSf16 + 3671680U, // MVE_VFMSf32 + 0U, // MVE_VHADD_qr_s16 + 0U, // MVE_VHADD_qr_s32 + 0U, // MVE_VHADD_qr_s8 + 0U, // MVE_VHADD_qr_u16 + 0U, // MVE_VHADD_qr_u32 + 0U, // MVE_VHADD_qr_u8 + 0U, // MVE_VHADDs16 + 0U, // MVE_VHADDs32 + 0U, // MVE_VHADDs8 + 0U, // MVE_VHADDu16 + 0U, // MVE_VHADDu32 + 0U, // MVE_VHADDu8 + 33554432U, // MVE_VHCADDs16 + 33554432U, // MVE_VHCADDs32 + 33554432U, // MVE_VHCADDs8 + 0U, // MVE_VHSUB_qr_s16 + 0U, // MVE_VHSUB_qr_s32 + 0U, // MVE_VHSUB_qr_s8 + 0U, // MVE_VHSUB_qr_u16 + 0U, // MVE_VHSUB_qr_u32 + 0U, // MVE_VHSUB_qr_u8 + 0U, // MVE_VHSUBs16 + 0U, // MVE_VHSUBs32 + 0U, // MVE_VHSUBs8 + 0U, // MVE_VHSUBu16 + 0U, // MVE_VHSUBu32 + 0U, // MVE_VHSUBu8 + 3670016U, // MVE_VIDUPu16 + 3670016U, // MVE_VIDUPu32 + 3670016U, // MVE_VIDUPu8 + 37224448U, // MVE_VIWDUPu16 + 37224448U, // MVE_VIWDUPu32 + 37224448U, // MVE_VIWDUPu8 + 0U, // MVE_VLD20_16 + 0U, // MVE_VLD20_16_wb + 0U, // MVE_VLD20_32 + 0U, // MVE_VLD20_32_wb + 0U, // MVE_VLD20_8 + 0U, // MVE_VLD20_8_wb + 0U, // MVE_VLD21_16 + 0U, // MVE_VLD21_16_wb + 0U, // MVE_VLD21_32 + 0U, // MVE_VLD21_32_wb + 0U, // MVE_VLD21_8 + 0U, // MVE_VLD21_8_wb + 0U, // MVE_VLD40_16 + 0U, // MVE_VLD40_16_wb + 0U, // MVE_VLD40_32 + 0U, // MVE_VLD40_32_wb + 0U, // MVE_VLD40_8 + 0U, // MVE_VLD40_8_wb + 0U, // MVE_VLD41_16 + 0U, // MVE_VLD41_16_wb + 0U, // MVE_VLD41_32 + 0U, // MVE_VLD41_32_wb + 0U, // MVE_VLD41_8 + 0U, // MVE_VLD41_8_wb + 0U, // MVE_VLD42_16 + 0U, // MVE_VLD42_16_wb + 0U, // MVE_VLD42_32 + 0U, // MVE_VLD42_32_wb + 0U, // MVE_VLD42_8 + 0U, // MVE_VLD42_8_wb + 0U, // MVE_VLD43_16 + 0U, // MVE_VLD43_16_wb + 0U, // MVE_VLD43_32 + 0U, // MVE_VLD43_32_wb + 0U, // MVE_VLD43_8 + 0U, // MVE_VLD43_8_wb + 4224U, // MVE_VLDRBS16 + 133888U, // MVE_VLDRBS16_post + 4352U, // MVE_VLDRBS16_pre + 4480U, // MVE_VLDRBS16_rq + 4224U, // MVE_VLDRBS32 + 133888U, // MVE_VLDRBS32_post + 4352U, // MVE_VLDRBS32_pre + 4480U, // MVE_VLDRBS32_rq + 4224U, // MVE_VLDRBU16 + 133888U, // MVE_VLDRBU16_post + 4352U, // MVE_VLDRBU16_pre + 4480U, // MVE_VLDRBU16_rq + 4224U, // MVE_VLDRBU32 + 133888U, // MVE_VLDRBU32_post + 4352U, // MVE_VLDRBU32_pre + 4480U, // MVE_VLDRBU32_rq + 4224U, // MVE_VLDRBU8 + 133888U, // MVE_VLDRBU8_post + 4608U, // MVE_VLDRBU8_pre + 4480U, // MVE_VLDRBU8_rq + 4224U, // MVE_VLDRDU64_qi + 4352U, // MVE_VLDRDU64_qi_pre + 4736U, // MVE_VLDRDU64_rq + 4480U, // MVE_VLDRDU64_rq_u + 4224U, // MVE_VLDRHS32 + 133888U, // MVE_VLDRHS32_post + 4352U, // MVE_VLDRHS32_pre + 4864U, // MVE_VLDRHS32_rq + 4480U, // MVE_VLDRHS32_rq_u + 4224U, // MVE_VLDRHU16 + 133888U, // MVE_VLDRHU16_post + 4608U, // MVE_VLDRHU16_pre + 4864U, // MVE_VLDRHU16_rq + 4480U, // MVE_VLDRHU16_rq_u + 4224U, // MVE_VLDRHU32 + 133888U, // MVE_VLDRHU32_post + 4352U, // MVE_VLDRHU32_pre + 4864U, // MVE_VLDRHU32_rq + 4480U, // MVE_VLDRHU32_rq_u + 4224U, // MVE_VLDRWU32 + 133888U, // MVE_VLDRWU32_post + 4608U, // MVE_VLDRWU32_pre + 4224U, // MVE_VLDRWU32_qi + 4352U, // MVE_VLDRWU32_qi_pre + 4992U, // MVE_VLDRWU32_rq + 4480U, // MVE_VLDRWU32_rq_u + 18048U, // MVE_VMAXAVs16 + 18048U, // MVE_VMAXAVs32 + 18048U, // MVE_VMAXAVs8 + 18048U, // MVE_VMAXAs16 + 18048U, // MVE_VMAXAs32 + 18048U, // MVE_VMAXAs8 + 18048U, // MVE_VMAXNMAVf16 + 18048U, // MVE_VMAXNMAVf32 + 18048U, // MVE_VMAXNMAf16 + 18048U, // MVE_VMAXNMAf32 + 18048U, // MVE_VMAXNMVf16 + 18048U, // MVE_VMAXNMVf32 + 0U, // MVE_VMAXNMf16 + 0U, // MVE_VMAXNMf32 + 18048U, // MVE_VMAXVs16 + 18048U, // MVE_VMAXVs32 + 18048U, // MVE_VMAXVs8 + 18048U, // MVE_VMAXVu16 + 18048U, // MVE_VMAXVu32 + 18048U, // MVE_VMAXVu8 + 0U, // MVE_VMAXs16 + 0U, // MVE_VMAXs32 + 0U, // MVE_VMAXs8 + 0U, // MVE_VMAXu16 + 0U, // MVE_VMAXu32 + 0U, // MVE_VMAXu8 + 18048U, // MVE_VMINAVs16 + 18048U, // MVE_VMINAVs32 + 18048U, // MVE_VMINAVs8 + 18048U, // MVE_VMINAs16 + 18048U, // MVE_VMINAs32 + 18048U, // MVE_VMINAs8 + 18048U, // MVE_VMINNMAVf16 + 18048U, // MVE_VMINNMAVf32 + 18048U, // MVE_VMINNMAf16 + 18048U, // MVE_VMINNMAf32 + 18048U, // MVE_VMINNMVf16 + 18048U, // MVE_VMINNMVf32 + 0U, // MVE_VMINNMf16 + 0U, // MVE_VMINNMf32 + 18048U, // MVE_VMINVs16 + 18048U, // MVE_VMINVs32 + 18048U, // MVE_VMINVs8 + 18048U, // MVE_VMINVu16 + 18048U, // MVE_VMINVu32 + 18048U, // MVE_VMINVu8 + 0U, // MVE_VMINs16 + 0U, // MVE_VMINs32 + 0U, // MVE_VMINs8 + 0U, // MVE_VMINu16 + 0U, // MVE_VMINu32 + 0U, // MVE_VMINu8 + 3671680U, // MVE_VMLADAVas16 + 3671680U, // MVE_VMLADAVas32 + 3671680U, // MVE_VMLADAVas8 + 3671680U, // MVE_VMLADAVau16 + 3671680U, // MVE_VMLADAVau32 + 3671680U, // MVE_VMLADAVau8 + 3671680U, // MVE_VMLADAVaxs16 + 3671680U, // MVE_VMLADAVaxs32 + 3671680U, // MVE_VMLADAVaxs8 + 0U, // MVE_VMLADAVs16 + 0U, // MVE_VMLADAVs32 + 0U, // MVE_VMLADAVs8 + 0U, // MVE_VMLADAVu16 + 0U, // MVE_VMLADAVu32 + 0U, // MVE_VMLADAVu8 + 0U, // MVE_VMLADAVxs16 + 0U, // MVE_VMLADAVxs32 + 0U, // MVE_VMLADAVxs8 + 34078720U, // MVE_VMLALDAVas16 + 34078720U, // MVE_VMLALDAVas32 + 34078720U, // MVE_VMLALDAVau16 + 34078720U, // MVE_VMLALDAVau32 + 34078720U, // MVE_VMLALDAVaxs16 + 34078720U, // MVE_VMLALDAVaxs32 + 33554432U, // MVE_VMLALDAVs16 + 33554432U, // MVE_VMLALDAVs32 + 33554432U, // MVE_VMLALDAVu16 + 33554432U, // MVE_VMLALDAVu32 + 33554432U, // MVE_VMLALDAVxs16 + 33554432U, // MVE_VMLALDAVxs32 + 3671680U, // MVE_VMLAS_qr_s16 + 3671680U, // MVE_VMLAS_qr_s32 + 3671680U, // MVE_VMLAS_qr_s8 + 3671680U, // MVE_VMLAS_qr_u16 + 3671680U, // MVE_VMLAS_qr_u32 + 3671680U, // MVE_VMLAS_qr_u8 + 3671680U, // MVE_VMLA_qr_s16 + 3671680U, // MVE_VMLA_qr_s32 + 3671680U, // MVE_VMLA_qr_s8 + 3671680U, // MVE_VMLA_qr_u16 + 3671680U, // MVE_VMLA_qr_u32 + 3671680U, // MVE_VMLA_qr_u8 + 3671680U, // MVE_VMLSDAVas16 + 3671680U, // MVE_VMLSDAVas32 + 3671680U, // MVE_VMLSDAVas8 + 3671680U, // MVE_VMLSDAVaxs16 + 3671680U, // MVE_VMLSDAVaxs32 + 3671680U, // MVE_VMLSDAVaxs8 + 0U, // MVE_VMLSDAVs16 + 0U, // MVE_VMLSDAVs32 + 0U, // MVE_VMLSDAVs8 + 0U, // MVE_VMLSDAVxs16 + 0U, // MVE_VMLSDAVxs32 + 0U, // MVE_VMLSDAVxs8 + 34078720U, // MVE_VMLSLDAVas16 + 34078720U, // MVE_VMLSLDAVas32 + 34078720U, // MVE_VMLSLDAVaxs16 + 34078720U, // MVE_VMLSLDAVaxs32 + 33554432U, // MVE_VMLSLDAVs16 + 33554432U, // MVE_VMLSLDAVs32 + 33554432U, // MVE_VMLSLDAVxs16 + 33554432U, // MVE_VMLSLDAVxs32 + 16384U, // MVE_VMOVLs16bh + 16384U, // MVE_VMOVLs16th + 16384U, // MVE_VMOVLs8bh + 16384U, // MVE_VMOVLs8th + 16384U, // MVE_VMOVLu16bh + 16384U, // MVE_VMOVLu16th + 16384U, // MVE_VMOVLu8bh + 16384U, // MVE_VMOVLu8th + 18048U, // MVE_VMOVNi16bh + 18048U, // MVE_VMOVNi16th + 18048U, // MVE_VMOVNi32bh + 18048U, // MVE_VMOVNi32th + 147456U, // MVE_VMOV_from_lane_32 + 147456U, // MVE_VMOV_from_lane_s16 + 147456U, // MVE_VMOV_from_lane_s8 + 147456U, // MVE_VMOV_from_lane_u16 + 147456U, // MVE_VMOV_from_lane_u8 + 30U, // MVE_VMOV_q_rr + 167772160U, // MVE_VMOV_rr_q + 32U, // MVE_VMOV_to_lane_16 + 32U, // MVE_VMOV_to_lane_32 + 32U, // MVE_VMOV_to_lane_8 + 2176U, // MVE_VMOVimmf32 + 5120U, // MVE_VMOVimmi16 + 5120U, // MVE_VMOVimmi32 + 0U, // MVE_VMOVimmi64 + 5120U, // MVE_VMOVimmi8 + 0U, // MVE_VMULHs16 + 0U, // MVE_VMULHs32 + 0U, // MVE_VMULHs8 + 0U, // MVE_VMULHu16 + 0U, // MVE_VMULHu32 + 0U, // MVE_VMULHu8 + 0U, // MVE_VMULLBp16 + 0U, // MVE_VMULLBp8 + 0U, // MVE_VMULLBs16 + 0U, // MVE_VMULLBs32 + 0U, // MVE_VMULLBs8 + 0U, // MVE_VMULLBu16 + 0U, // MVE_VMULLBu32 + 0U, // MVE_VMULLBu8 + 0U, // MVE_VMULLTp16 + 0U, // MVE_VMULLTp8 + 0U, // MVE_VMULLTs16 + 0U, // MVE_VMULLTs32 + 0U, // MVE_VMULLTs8 + 0U, // MVE_VMULLTu16 + 0U, // MVE_VMULLTu32 + 0U, // MVE_VMULLTu8 + 0U, // MVE_VMUL_qr_f16 + 0U, // MVE_VMUL_qr_f32 + 0U, // MVE_VMUL_qr_i16 + 0U, // MVE_VMUL_qr_i32 + 0U, // MVE_VMUL_qr_i8 + 0U, // MVE_VMULf16 + 0U, // MVE_VMULf32 + 0U, // MVE_VMULi16 + 0U, // MVE_VMULi32 + 0U, // MVE_VMULi8 + 16384U, // MVE_VMVN + 5120U, // MVE_VMVNimmi16 + 5120U, // MVE_VMVNimmi32 + 16384U, // MVE_VNEGf16 + 16384U, // MVE_VNEGf32 + 16384U, // MVE_VNEGs16 + 16384U, // MVE_VNEGs32 + 16384U, // MVE_VNEGs8 + 0U, // MVE_VORN + 0U, // MVE_VORR + 4096U, // MVE_VORRimmi16 + 4096U, // MVE_VORRimmi32 + 0U, // MVE_VPNOT + 0U, // MVE_VPSEL + 0U, // MVE_VPST + 0U, // MVE_VPTv16i8 + 0U, // MVE_VPTv16i8r + 0U, // MVE_VPTv16s8 + 0U, // MVE_VPTv16s8r + 0U, // MVE_VPTv16u8 + 0U, // MVE_VPTv16u8r + 0U, // MVE_VPTv4f32 + 0U, // MVE_VPTv4f32r + 0U, // MVE_VPTv4i32 + 0U, // MVE_VPTv4i32r + 0U, // MVE_VPTv4s32 + 0U, // MVE_VPTv4s32r + 0U, // MVE_VPTv4u32 + 0U, // MVE_VPTv4u32r + 0U, // MVE_VPTv8f16 + 0U, // MVE_VPTv8f16r + 0U, // MVE_VPTv8i16 + 0U, // MVE_VPTv8i16r + 0U, // MVE_VPTv8s16 + 0U, // MVE_VPTv8s16r + 0U, // MVE_VPTv8u16 + 0U, // MVE_VPTv8u16r + 16384U, // MVE_VQABSs16 + 16384U, // MVE_VQABSs32 + 16384U, // MVE_VQABSs8 + 0U, // MVE_VQADD_qr_s16 + 0U, // MVE_VQADD_qr_s32 + 0U, // MVE_VQADD_qr_s8 + 0U, // MVE_VQADD_qr_u16 + 0U, // MVE_VQADD_qr_u32 + 0U, // MVE_VQADD_qr_u8 + 0U, // MVE_VQADDs16 + 0U, // MVE_VQADDs32 + 0U, // MVE_VQADDs8 + 0U, // MVE_VQADDu16 + 0U, // MVE_VQADDu32 + 0U, // MVE_VQADDu8 + 3671680U, // MVE_VQDMLADHXs16 + 3671680U, // MVE_VQDMLADHXs32 + 3671680U, // MVE_VQDMLADHXs8 + 3671680U, // MVE_VQDMLADHs16 + 3671680U, // MVE_VQDMLADHs32 + 3671680U, // MVE_VQDMLADHs8 + 3671680U, // MVE_VQDMLAH_qrs16 + 3671680U, // MVE_VQDMLAH_qrs32 + 3671680U, // MVE_VQDMLAH_qrs8 + 3671680U, // MVE_VQDMLASH_qrs16 + 3671680U, // MVE_VQDMLASH_qrs32 + 3671680U, // MVE_VQDMLASH_qrs8 + 3671680U, // MVE_VQDMLSDHXs16 + 3671680U, // MVE_VQDMLSDHXs32 + 3671680U, // MVE_VQDMLSDHXs8 + 3671680U, // MVE_VQDMLSDHs16 + 3671680U, // MVE_VQDMLSDHs32 + 3671680U, // MVE_VQDMLSDHs8 + 0U, // MVE_VQDMULH_qr_s16 + 0U, // MVE_VQDMULH_qr_s32 + 0U, // MVE_VQDMULH_qr_s8 + 0U, // MVE_VQDMULHi16 + 0U, // MVE_VQDMULHi32 + 0U, // MVE_VQDMULHi8 + 0U, // MVE_VQDMULL_qr_s16bh + 0U, // MVE_VQDMULL_qr_s16th + 0U, // MVE_VQDMULL_qr_s32bh + 0U, // MVE_VQDMULL_qr_s32th + 0U, // MVE_VQDMULLs16bh + 0U, // MVE_VQDMULLs16th + 0U, // MVE_VQDMULLs32bh + 0U, // MVE_VQDMULLs32th + 18048U, // MVE_VQMOVNs16bh + 18048U, // MVE_VQMOVNs16th + 18048U, // MVE_VQMOVNs32bh + 18048U, // MVE_VQMOVNs32th + 18048U, // MVE_VQMOVNu16bh + 18048U, // MVE_VQMOVNu16th + 18048U, // MVE_VQMOVNu32bh + 18048U, // MVE_VQMOVNu32th + 18048U, // MVE_VQMOVUNs16bh + 18048U, // MVE_VQMOVUNs16th + 18048U, // MVE_VQMOVUNs32bh + 18048U, // MVE_VQMOVUNs32th + 16384U, // MVE_VQNEGs16 + 16384U, // MVE_VQNEGs32 + 16384U, // MVE_VQNEGs8 + 3671680U, // MVE_VQRDMLADHXs16 + 3671680U, // MVE_VQRDMLADHXs32 + 3671680U, // MVE_VQRDMLADHXs8 + 3671680U, // MVE_VQRDMLADHs16 + 3671680U, // MVE_VQRDMLADHs32 + 3671680U, // MVE_VQRDMLADHs8 + 3671680U, // MVE_VQRDMLAH_qrs16 + 3671680U, // MVE_VQRDMLAH_qrs32 + 3671680U, // MVE_VQRDMLAH_qrs8 + 3671680U, // MVE_VQRDMLASH_qrs16 + 3671680U, // MVE_VQRDMLASH_qrs32 + 3671680U, // MVE_VQRDMLASH_qrs8 + 3671680U, // MVE_VQRDMLSDHXs16 + 3671680U, // MVE_VQRDMLSDHXs32 + 3671680U, // MVE_VQRDMLSDHXs8 + 3671680U, // MVE_VQRDMLSDHs16 + 3671680U, // MVE_VQRDMLSDHs32 + 3671680U, // MVE_VQRDMLSDHs8 + 0U, // MVE_VQRDMULH_qr_s16 + 0U, // MVE_VQRDMULH_qr_s32 + 0U, // MVE_VQRDMULH_qr_s8 + 0U, // MVE_VQRDMULHi16 + 0U, // MVE_VQRDMULHi32 + 0U, // MVE_VQRDMULHi8 + 0U, // MVE_VQRSHL_by_vecs16 + 0U, // MVE_VQRSHL_by_vecs32 + 0U, // MVE_VQRSHL_by_vecs8 + 0U, // MVE_VQRSHL_by_vecu16 + 0U, // MVE_VQRSHL_by_vecu32 + 0U, // MVE_VQRSHL_by_vecu8 + 18048U, // MVE_VQRSHL_qrs16 + 18048U, // MVE_VQRSHL_qrs32 + 18048U, // MVE_VQRSHL_qrs8 + 18048U, // MVE_VQRSHL_qru16 + 18048U, // MVE_VQRSHL_qru32 + 18048U, // MVE_VQRSHL_qru8 + 3671680U, // MVE_VQRSHRNbhs16 + 3671680U, // MVE_VQRSHRNbhs32 + 3671680U, // MVE_VQRSHRNbhu16 + 3671680U, // MVE_VQRSHRNbhu32 + 3671680U, // MVE_VQRSHRNths16 + 3671680U, // MVE_VQRSHRNths32 + 3671680U, // MVE_VQRSHRNthu16 + 3671680U, // MVE_VQRSHRNthu32 + 3671680U, // MVE_VQRSHRUNs16bh + 3671680U, // MVE_VQRSHRUNs16th + 3671680U, // MVE_VQRSHRUNs32bh + 3671680U, // MVE_VQRSHRUNs32th + 0U, // MVE_VQSHLU_imms16 + 0U, // MVE_VQSHLU_imms32 + 0U, // MVE_VQSHLU_imms8 + 0U, // MVE_VQSHL_by_vecs16 + 0U, // MVE_VQSHL_by_vecs32 + 0U, // MVE_VQSHL_by_vecs8 + 0U, // MVE_VQSHL_by_vecu16 + 0U, // MVE_VQSHL_by_vecu32 + 0U, // MVE_VQSHL_by_vecu8 + 18048U, // MVE_VQSHL_qrs16 + 18048U, // MVE_VQSHL_qrs32 + 18048U, // MVE_VQSHL_qrs8 + 18048U, // MVE_VQSHL_qru16 + 18048U, // MVE_VQSHL_qru32 + 18048U, // MVE_VQSHL_qru8 + 0U, // MVE_VQSHLimms16 + 0U, // MVE_VQSHLimms32 + 0U, // MVE_VQSHLimms8 + 0U, // MVE_VQSHLimmu16 + 0U, // MVE_VQSHLimmu32 + 0U, // MVE_VQSHLimmu8 + 3671680U, // MVE_VQSHRNbhs16 + 3671680U, // MVE_VQSHRNbhs32 + 3671680U, // MVE_VQSHRNbhu16 + 3671680U, // MVE_VQSHRNbhu32 + 3671680U, // MVE_VQSHRNths16 + 3671680U, // MVE_VQSHRNths32 + 3671680U, // MVE_VQSHRNthu16 + 3671680U, // MVE_VQSHRNthu32 + 3671680U, // MVE_VQSHRUNs16bh + 3671680U, // MVE_VQSHRUNs16th + 3671680U, // MVE_VQSHRUNs32bh + 3671680U, // MVE_VQSHRUNs32th + 0U, // MVE_VQSUB_qr_s16 + 0U, // MVE_VQSUB_qr_s32 + 0U, // MVE_VQSUB_qr_s8 + 0U, // MVE_VQSUB_qr_u16 + 0U, // MVE_VQSUB_qr_u32 + 0U, // MVE_VQSUB_qr_u8 + 0U, // MVE_VQSUBs16 + 0U, // MVE_VQSUBs32 + 0U, // MVE_VQSUBs8 + 0U, // MVE_VQSUBu16 + 0U, // MVE_VQSUBu32 + 0U, // MVE_VQSUBu8 + 16384U, // MVE_VREV16_8 + 16384U, // MVE_VREV32_16 + 16384U, // MVE_VREV32_8 + 16384U, // MVE_VREV64_16 + 16384U, // MVE_VREV64_32 + 16384U, // MVE_VREV64_8 + 0U, // MVE_VRHADDs16 + 0U, // MVE_VRHADDs32 + 0U, // MVE_VRHADDs8 + 0U, // MVE_VRHADDu16 + 0U, // MVE_VRHADDu32 + 0U, // MVE_VRHADDu8 + 16384U, // MVE_VRINTf16A + 16384U, // MVE_VRINTf16M + 16384U, // MVE_VRINTf16N + 16384U, // MVE_VRINTf16P + 16384U, // MVE_VRINTf16X + 16384U, // MVE_VRINTf16Z + 16384U, // MVE_VRINTf32A + 16384U, // MVE_VRINTf32M + 16384U, // MVE_VRINTf32N + 16384U, // MVE_VRINTf32P + 16384U, // MVE_VRINTf32X + 16384U, // MVE_VRINTf32Z + 34078720U, // MVE_VRMLALDAVHas32 + 34078720U, // MVE_VRMLALDAVHau32 + 34078720U, // MVE_VRMLALDAVHaxs32 + 33554432U, // MVE_VRMLALDAVHs32 + 33554432U, // MVE_VRMLALDAVHu32 + 33554432U, // MVE_VRMLALDAVHxs32 + 34078720U, // MVE_VRMLSLDAVHas32 + 34078720U, // MVE_VRMLSLDAVHaxs32 + 33554432U, // MVE_VRMLSLDAVHs32 + 33554432U, // MVE_VRMLSLDAVHxs32 + 0U, // MVE_VRMULHs16 + 0U, // MVE_VRMULHs32 + 0U, // MVE_VRMULHs8 + 0U, // MVE_VRMULHu16 + 0U, // MVE_VRMULHu32 + 0U, // MVE_VRMULHu8 + 0U, // MVE_VRSHL_by_vecs16 + 0U, // MVE_VRSHL_by_vecs32 + 0U, // MVE_VRSHL_by_vecs8 + 0U, // MVE_VRSHL_by_vecu16 + 0U, // MVE_VRSHL_by_vecu32 + 0U, // MVE_VRSHL_by_vecu8 + 18048U, // MVE_VRSHL_qrs16 + 18048U, // MVE_VRSHL_qrs32 + 18048U, // MVE_VRSHL_qrs8 + 18048U, // MVE_VRSHL_qru16 + 18048U, // MVE_VRSHL_qru32 + 18048U, // MVE_VRSHL_qru8 + 3671680U, // MVE_VRSHRNi16bh + 3671680U, // MVE_VRSHRNi16th + 3671680U, // MVE_VRSHRNi32bh + 3671680U, // MVE_VRSHRNi32th + 0U, // MVE_VRSHR_imms16 + 0U, // MVE_VRSHR_imms32 + 0U, // MVE_VRSHR_imms8 + 0U, // MVE_VRSHR_immu16 + 0U, // MVE_VRSHR_immu32 + 0U, // MVE_VRSHR_immu8 + 3671680U, // MVE_VSBC + 3671680U, // MVE_VSBCI + 524672U, // MVE_VSHLC + 0U, // MVE_VSHLL_imms16bh + 0U, // MVE_VSHLL_imms16th + 0U, // MVE_VSHLL_imms8bh + 0U, // MVE_VSHLL_imms8th + 0U, // MVE_VSHLL_immu16bh + 0U, // MVE_VSHLL_immu16th + 0U, // MVE_VSHLL_immu8bh + 0U, // MVE_VSHLL_immu8th + 163840U, // MVE_VSHLL_lws16bh + 163840U, // MVE_VSHLL_lws16th + 180224U, // MVE_VSHLL_lws8bh + 180224U, // MVE_VSHLL_lws8th + 163840U, // MVE_VSHLL_lwu16bh + 163840U, // MVE_VSHLL_lwu16th + 180224U, // MVE_VSHLL_lwu8bh + 180224U, // MVE_VSHLL_lwu8th + 0U, // MVE_VSHL_by_vecs16 + 0U, // MVE_VSHL_by_vecs32 + 0U, // MVE_VSHL_by_vecs8 + 0U, // MVE_VSHL_by_vecu16 + 0U, // MVE_VSHL_by_vecu32 + 0U, // MVE_VSHL_by_vecu8 + 0U, // MVE_VSHL_immi16 + 0U, // MVE_VSHL_immi32 + 0U, // MVE_VSHL_immi8 + 18048U, // MVE_VSHL_qrs16 + 18048U, // MVE_VSHL_qrs32 + 18048U, // MVE_VSHL_qrs8 + 18048U, // MVE_VSHL_qru16 + 18048U, // MVE_VSHL_qru32 + 18048U, // MVE_VSHL_qru8 + 3671680U, // MVE_VSHRNi16bh + 3671680U, // MVE_VSHRNi16th + 3671680U, // MVE_VSHRNi32bh + 3671680U, // MVE_VSHRNi32th + 0U, // MVE_VSHR_imms16 + 0U, // MVE_VSHR_imms32 + 0U, // MVE_VSHR_imms8 + 0U, // MVE_VSHR_immu16 + 0U, // MVE_VSHR_immu32 + 0U, // MVE_VSHR_immu8 + 3671680U, // MVE_VSLIimm16 + 3671680U, // MVE_VSLIimm32 + 3671680U, // MVE_VSLIimm8 + 3671680U, // MVE_VSRIimm16 + 3671680U, // MVE_VSRIimm32 + 3671680U, // MVE_VSRIimm8 + 0U, // MVE_VST20_16 + 0U, // MVE_VST20_16_wb + 0U, // MVE_VST20_32 + 0U, // MVE_VST20_32_wb + 0U, // MVE_VST20_8 + 0U, // MVE_VST20_8_wb + 0U, // MVE_VST21_16 + 0U, // MVE_VST21_16_wb + 0U, // MVE_VST21_32 + 0U, // MVE_VST21_32_wb + 0U, // MVE_VST21_8 + 0U, // MVE_VST21_8_wb + 0U, // MVE_VST40_16 + 0U, // MVE_VST40_16_wb + 0U, // MVE_VST40_32 + 0U, // MVE_VST40_32_wb + 0U, // MVE_VST40_8 + 0U, // MVE_VST40_8_wb + 0U, // MVE_VST41_16 + 0U, // MVE_VST41_16_wb + 0U, // MVE_VST41_32 + 0U, // MVE_VST41_32_wb + 0U, // MVE_VST41_8 + 0U, // MVE_VST41_8_wb + 0U, // MVE_VST42_16 + 0U, // MVE_VST42_16_wb + 0U, // MVE_VST42_32 + 0U, // MVE_VST42_32_wb + 0U, // MVE_VST42_8 + 0U, // MVE_VST42_8_wb + 0U, // MVE_VST43_16 + 0U, // MVE_VST43_16_wb + 0U, // MVE_VST43_32 + 0U, // MVE_VST43_32_wb + 0U, // MVE_VST43_8 + 0U, // MVE_VST43_8_wb + 4224U, // MVE_VSTRB16 + 133888U, // MVE_VSTRB16_post + 4352U, // MVE_VSTRB16_pre + 4480U, // MVE_VSTRB16_rq + 4224U, // MVE_VSTRB32 + 133888U, // MVE_VSTRB32_post + 4352U, // MVE_VSTRB32_pre + 4480U, // MVE_VSTRB32_rq + 4480U, // MVE_VSTRB8_rq + 4224U, // MVE_VSTRBU8 + 133888U, // MVE_VSTRBU8_post + 4608U, // MVE_VSTRBU8_pre + 4224U, // MVE_VSTRD64_qi + 4352U, // MVE_VSTRD64_qi_pre + 4736U, // MVE_VSTRD64_rq + 4480U, // MVE_VSTRD64_rq_u + 4864U, // MVE_VSTRH16_rq + 4480U, // MVE_VSTRH16_rq_u + 4224U, // MVE_VSTRH32 + 133888U, // MVE_VSTRH32_post + 4352U, // MVE_VSTRH32_pre + 4864U, // MVE_VSTRH32_rq + 4480U, // MVE_VSTRH32_rq_u + 4224U, // MVE_VSTRHU16 + 133888U, // MVE_VSTRHU16_post + 4608U, // MVE_VSTRHU16_pre + 4224U, // MVE_VSTRW32_qi + 4352U, // MVE_VSTRW32_qi_pre + 4992U, // MVE_VSTRW32_rq + 4480U, // MVE_VSTRW32_rq_u + 4224U, // MVE_VSTRWU32 + 133888U, // MVE_VSTRWU32_post + 4608U, // MVE_VSTRWU32_pre + 0U, // MVE_VSUB_qr_f16 + 0U, // MVE_VSUB_qr_f32 + 0U, // MVE_VSUB_qr_i16 + 0U, // MVE_VSUB_qr_i32 + 0U, // MVE_VSUB_qr_i8 + 0U, // MVE_VSUBf16 + 0U, // MVE_VSUBf32 + 0U, // MVE_VSUBi16 + 0U, // MVE_VSUBi32 + 0U, // MVE_VSUBi8 + 18048U, // MVE_WLSTP_16 + 18048U, // MVE_WLSTP_32 + 18048U, // MVE_WLSTP_64 + 18048U, // MVE_WLSTP_8 + 1920U, // MVNi + 16384U, // MVNr + 2048U, // MVNsi + 1152U, // MVNsr + 18048U, // NEON_VMAXNMNDf + 18048U, // NEON_VMAXNMNDh + 18048U, // NEON_VMAXNMNQf + 18048U, // NEON_VMAXNMNQh + 18048U, // NEON_VMINNMNDf + 18048U, // NEON_VMINNMNDh + 18048U, // NEON_VMINNMNQf + 18048U, // NEON_VMINNMNQh + 1048576U, // ORRri + 0U, // ORRrr + 1572864U, // ORRrsi + 0U, // ORRrsr + 201326592U, // PKHBT + 234881024U, // PKHTB + 0U, // PLDWi12 + 0U, // PLDWrs + 0U, // PLDi12 + 0U, // PLDrs + 0U, // PLIi12 + 0U, // PLIrs + 0U, // QADD + 0U, // QADD16 + 0U, // QADD8 + 0U, // QASX + 0U, // QDADD + 0U, // QDSUB + 0U, // QSAX + 0U, // QSUB + 0U, // QSUB16 + 0U, // QSUB8 + 16384U, // RBIT + 16384U, // REV + 16384U, // REV16 + 16384U, // REVSH + 0U, // RFEDA + 0U, // RFEDA_UPD + 0U, // RFEDB + 0U, // RFEDB_UPD + 0U, // RFEIA + 0U, // RFEIA_UPD + 0U, // RFEIB + 0U, // RFEIB_UPD + 1048576U, // RSBri + 0U, // RSBrr + 1572864U, // RSBrsi + 0U, // RSBrsr + 1048576U, // RSCri + 0U, // RSCrr + 1572864U, // RSCrsi + 0U, // RSCrsr + 0U, // SADD16 + 0U, // SADD8 + 0U, // SASX + 0U, // SB + 1048576U, // SBCri + 0U, // SBCrr + 1572864U, // SBCrsi + 0U, // SBCrsr + 33554432U, // SBFX + 0U, // SDIV + 0U, // SEL + 0U, // SETEND + 0U, // SETPAN + 16768U, // SHA1C + 2U, // SHA1H + 16768U, // SHA1M + 16768U, // SHA1P + 16768U, // SHA1SU0 + 2U, // SHA1SU1 + 16768U, // SHA256H + 16768U, // SHA256H2 + 2U, // SHA256SU0 + 16768U, // SHA256SU1 + 0U, // SHADD16 + 0U, // SHADD8 + 0U, // SHASX + 0U, // SHSAX + 0U, // SHSUB16 + 0U, // SHSUB8 + 2U, // SMC + 33554432U, // SMLABB + 33554432U, // SMLABT + 33554432U, // SMLAD + 33554432U, // SMLADX + 0U, // SMLAL + 33554432U, // SMLALBB + 33554432U, // SMLALBT + 33554432U, // SMLALD + 33554432U, // SMLALDX + 33554432U, // SMLALTB + 33554432U, // SMLALTT + 33554432U, // SMLATB + 33554432U, // SMLATT + 33554432U, // SMLAWB + 33554432U, // SMLAWT + 33554432U, // SMLSD + 33554432U, // SMLSDX + 33554432U, // SMLSLD + 33554432U, // SMLSLDX + 33554432U, // SMMLA + 33554432U, // SMMLAR + 33554432U, // SMMLS + 33554432U, // SMMLSR + 0U, // SMMUL + 0U, // SMMULR + 0U, // SMUAD + 0U, // SMUADX + 0U, // SMULBB + 0U, // SMULBT + 33554432U, // SMULL + 0U, // SMULTB + 0U, // SMULTT + 0U, // SMULWB + 0U, // SMULWT + 0U, // SMUSD + 0U, // SMUSDX + 0U, // SRSDA + 0U, // SRSDA_UPD + 0U, // SRSDB + 0U, // SRSDB_UPD + 0U, // SRSIA + 0U, // SRSIA_UPD + 0U, // SRSIB + 0U, // SRSIB_UPD + 201856U, // SSAT + 21632U, // SSAT16 + 0U, // SSAX + 0U, // SSUB16 + 0U, // SSUB8 + 0U, // STC2L_OFFSET + 2432U, // STC2L_OPTION + 2560U, // STC2L_POST + 0U, // STC2L_PRE + 0U, // STC2_OFFSET + 2432U, // STC2_OPTION + 2560U, // STC2_POST + 0U, // STC2_PRE + 2708U, // STCL_OFFSET + 4721428U, // STCL_OPTION + 5245716U, // STCL_POST + 2964U, // STCL_PRE + 2708U, // STC_OFFSET + 4721428U, // STC_OPTION + 5245716U, // STC_POST + 2964U, // STC_PRE + 128U, // STL + 128U, // STLB + 10485760U, // STLEX + 10485760U, // STLEXB + 5376U, // STLEXD + 10485760U, // STLEXH + 128U, // STLH + 18688U, // STMDA + 530U, // STMDA_UPD + 18688U, // STMDB + 530U, // STMDB_UPD + 18688U, // STMIA + 530U, // STMIA_UPD + 18688U, // STMIB + 530U, // STMIB_UPD + 5769984U, // STRBT_POST_IMM + 5769984U, // STRBT_POST_REG + 5769984U, // STRB_POST_IMM + 5769984U, // STRB_POST_REG + 3072U, // STRB_PRE_IMM + 3200U, // STRB_PRE_REG + 3328U, // STRBi12 + 3456U, // STRBrs + 6291456U, // STRD + 40371840U, // STRD_POST + 7341696U, // STRD_PRE + 10485760U, // STREX + 10485760U, // STREXB + 5376U, // STREXD + 10485760U, // STREXH + 3584U, // STRH + 7867136U, // STRHTi + 8391424U, // STRHTr + 8915712U, // STRH_POST + 3712U, // STRH_PRE + 5769984U, // STRT_POST_IMM + 5769984U, // STRT_POST_REG + 5769984U, // STR_POST_IMM + 5769984U, // STR_POST_REG + 3072U, // STR_PRE_IMM + 3200U, // STR_PRE_REG + 3328U, // STRi12 + 3456U, // STRrs + 1048576U, // SUBri + 0U, // SUBrr + 1572864U, // SUBrsi + 0U, // SUBrsr + 2U, // SVC + 10485760U, // SWP + 10485760U, // SWPB + 268435456U, // SXTAB + 268435456U, // SXTAB16 + 268435456U, // SXTAH + 212992U, // SXTB + 212992U, // SXTB16 + 212992U, // SXTH + 1920U, // TEQri + 16384U, // TEQrr + 2048U, // TEQrsi + 1152U, // TEQrsr + 0U, // TRAP + 0U, // TRAPNaCl + 0U, // TSB + 1920U, // TSTri + 16384U, // TSTrr + 2048U, // TSTrsi + 1152U, // TSTrsr + 0U, // UADD16 + 0U, // UADD8 + 0U, // UASX + 33554432U, // UBFX + 0U, // UDF + 0U, // UDIV + 0U, // UHADD16 + 0U, // UHADD8 + 0U, // UHASX + 0U, // UHSAX + 0U, // UHSUB16 + 0U, // UHSUB8 + 33554432U, // UMAAL + 0U, // UMLAL + 33554432U, // UMULL + 0U, // UQADD16 + 0U, // UQADD8 + 0U, // UQASX + 0U, // UQSAX + 0U, // UQSUB16 + 0U, // UQSUB8 + 0U, // USAD8 + 33554432U, // USADA8 + 301989888U, // USAT + 0U, // USAT16 + 0U, // USAX + 0U, // USUB16 + 0U, // USUB8 + 268435456U, // UXTAB + 268435456U, // UXTAB16 + 268435456U, // UXTAH + 212992U, // UXTB + 212992U, // UXTB16 + 212992U, // UXTH + 3671680U, // VABALsv2i64 + 3671680U, // VABALsv4i32 + 3671680U, // VABALsv8i16 + 3671680U, // VABALuv2i64 + 3671680U, // VABALuv4i32 + 3671680U, // VABALuv8i16 + 3671680U, // VABAsv16i8 + 3671680U, // VABAsv2i32 + 3671680U, // VABAsv4i16 + 3671680U, // VABAsv4i32 + 3671680U, // VABAsv8i16 + 3671680U, // VABAsv8i8 + 3671680U, // VABAuv16i8 + 3671680U, // VABAuv2i32 + 3671680U, // VABAuv4i16 + 3671680U, // VABAuv4i32 + 3671680U, // VABAuv8i16 + 3671680U, // VABAuv8i8 + 0U, // VABDLsv2i64 + 0U, // VABDLsv4i32 + 0U, // VABDLsv8i16 + 0U, // VABDLuv2i64 + 0U, // VABDLuv4i32 + 0U, // VABDLuv8i16 + 0U, // VABDfd + 0U, // VABDfq + 0U, // VABDhd + 0U, // VABDhq + 0U, // VABDsv16i8 + 0U, // VABDsv2i32 + 0U, // VABDsv4i16 + 0U, // VABDsv4i32 + 0U, // VABDsv8i16 + 0U, // VABDsv8i8 + 0U, // VABDuv16i8 + 0U, // VABDuv2i32 + 0U, // VABDuv4i16 + 0U, // VABDuv4i32 + 0U, // VABDuv8i16 + 0U, // VABDuv8i8 + 526U, // VABSD + 16384U, // VABSH + 16384U, // VABSS + 16384U, // VABSfd + 16384U, // VABSfq + 16384U, // VABShd + 16384U, // VABShq + 16384U, // VABSv16i8 + 16384U, // VABSv2i32 + 16384U, // VABSv4i16 + 16384U, // VABSv4i32 + 16384U, // VABSv8i16 + 16384U, // VABSv8i8 + 0U, // VACGEfd + 0U, // VACGEfq + 0U, // VACGEhd + 0U, // VACGEhq + 0U, // VACGTfd + 0U, // VACGTfq + 0U, // VACGThd + 0U, // VACGThq + 2720526U, // VADDD + 0U, // VADDH + 18048U, // VADDHNv2i32 + 0U, // VADDHNv4i16 + 0U, // VADDHNv8i8 + 0U, // VADDLsv2i64 + 0U, // VADDLsv4i32 + 0U, // VADDLsv8i16 + 0U, // VADDLuv2i64 + 0U, // VADDLuv4i32 + 0U, // VADDLuv8i16 + 0U, // VADDS + 0U, // VADDWsv2i64 + 0U, // VADDWsv4i32 + 0U, // VADDWsv8i16 + 0U, // VADDWuv2i64 + 0U, // VADDWuv4i32 + 0U, // VADDWuv8i16 + 0U, // VADDfd + 0U, // VADDfq + 0U, // VADDhd + 0U, // VADDhq + 0U, // VADDv16i8 + 18048U, // VADDv1i64 + 0U, // VADDv2i32 + 18048U, // VADDv2i64 + 0U, // VADDv4i16 + 0U, // VADDv4i32 + 0U, // VADDv8i16 + 0U, // VADDv8i8 + 0U, // VANDd + 0U, // VANDq + 520U, // VBF16MALBQ + 1416U, // VBF16MALBQI + 520U, // VBF16MALTQ + 1416U, // VBF16MALTQI + 0U, // VBICd + 5120U, // VBICiv2i32 + 5120U, // VBICiv4i16 + 5120U, // VBICiv4i32 + 5120U, // VBICiv8i16 + 0U, // VBICq + 3671680U, // VBIFd + 3671680U, // VBIFq + 3671680U, // VBITd + 3671680U, // VBITq + 3671680U, // VBSLd + 3671680U, // VBSLq + 0U, // VBSPd + 0U, // VBSPq + 11011712U, // VCADDv2f32 + 11011712U, // VCADDv4f16 + 11011712U, // VCADDv4f32 + 11011712U, // VCADDv8f16 + 0U, // VCEQfd + 0U, // VCEQfq + 0U, // VCEQhd + 0U, // VCEQhq + 0U, // VCEQv16i8 + 0U, // VCEQv2i32 + 0U, // VCEQv4i16 + 0U, // VCEQv4i32 + 0U, // VCEQv8i16 + 0U, // VCEQv8i8 + 229376U, // VCEQzv16i8 + 229376U, // VCEQzv2f32 + 229376U, // VCEQzv2i32 + 229376U, // VCEQzv4f16 + 229376U, // VCEQzv4f32 + 229376U, // VCEQzv4i16 + 229376U, // VCEQzv4i32 + 229376U, // VCEQzv8f16 + 229376U, // VCEQzv8i16 + 229376U, // VCEQzv8i8 + 0U, // VCGEfd + 0U, // VCGEfq + 0U, // VCGEhd + 0U, // VCGEhq + 0U, // VCGEsv16i8 + 0U, // VCGEsv2i32 + 0U, // VCGEsv4i16 + 0U, // VCGEsv4i32 + 0U, // VCGEsv8i16 + 0U, // VCGEsv8i8 + 0U, // VCGEuv16i8 + 0U, // VCGEuv2i32 + 0U, // VCGEuv4i16 + 0U, // VCGEuv4i32 + 0U, // VCGEuv8i16 + 0U, // VCGEuv8i8 + 229376U, // VCGEzv16i8 + 229376U, // VCGEzv2f32 + 229376U, // VCGEzv2i32 + 229376U, // VCGEzv4f16 + 229376U, // VCGEzv4f32 + 229376U, // VCGEzv4i16 + 229376U, // VCGEzv4i32 + 229376U, // VCGEzv8f16 + 229376U, // VCGEzv8i16 + 229376U, // VCGEzv8i8 + 0U, // VCGTfd + 0U, // VCGTfq + 0U, // VCGThd + 0U, // VCGThq + 0U, // VCGTsv16i8 + 0U, // VCGTsv2i32 + 0U, // VCGTsv4i16 + 0U, // VCGTsv4i32 + 0U, // VCGTsv8i16 + 0U, // VCGTsv8i8 + 0U, // VCGTuv16i8 + 0U, // VCGTuv2i32 + 0U, // VCGTuv4i16 + 0U, // VCGTuv4i32 + 0U, // VCGTuv8i16 + 0U, // VCGTuv8i8 + 229376U, // VCGTzv16i8 + 229376U, // VCGTzv2f32 + 229376U, // VCGTzv2i32 + 229376U, // VCGTzv4f16 + 229376U, // VCGTzv4f32 + 229376U, // VCGTzv4i16 + 229376U, // VCGTzv4i32 + 229376U, // VCGTzv8f16 + 229376U, // VCGTzv8i16 + 229376U, // VCGTzv8i8 + 229376U, // VCLEzv16i8 + 229376U, // VCLEzv2f32 + 229376U, // VCLEzv2i32 + 229376U, // VCLEzv4f16 + 229376U, // VCLEzv4f32 + 229376U, // VCLEzv4i16 + 229376U, // VCLEzv4i32 + 229376U, // VCLEzv8f16 + 229376U, // VCLEzv8i16 + 229376U, // VCLEzv8i8 + 16384U, // VCLSv16i8 + 16384U, // VCLSv2i32 + 16384U, // VCLSv4i16 + 16384U, // VCLSv4i32 + 16384U, // VCLSv8i16 + 16384U, // VCLSv8i8 + 229376U, // VCLTzv16i8 + 229376U, // VCLTzv2f32 + 229376U, // VCLTzv2i32 + 229376U, // VCLTzv4f16 + 229376U, // VCLTzv4f32 + 229376U, // VCLTzv4i16 + 229376U, // VCLTzv4i32 + 229376U, // VCLTzv8f16 + 229376U, // VCLTzv8i16 + 229376U, // VCLTzv8i8 + 16384U, // VCLZv16i8 + 16384U, // VCLZv2i32 + 16384U, // VCLZv4i16 + 16384U, // VCLZv4i32 + 16384U, // VCLZv8i16 + 16384U, // VCLZv8i8 + 11534720U, // VCMLAv2f32 + 246144U, // VCMLAv2f32_indexed + 11534720U, // VCMLAv4f16 + 246144U, // VCMLAv4f16_indexed + 11534720U, // VCMLAv4f32 + 246144U, // VCMLAv4f32_indexed + 11534720U, // VCMLAv8f16 + 246144U, // VCMLAv8f16_indexed + 526U, // VCMPD + 526U, // VCMPED + 16384U, // VCMPEH + 16384U, // VCMPES + 0U, // VCMPEZD + 34U, // VCMPEZH + 34U, // VCMPEZS + 16384U, // VCMPH + 16384U, // VCMPS + 0U, // VCMPZD + 34U, // VCMPZH + 34U, // VCMPZS + 16384U, // VCNTd + 16384U, // VCNTq + 2U, // VCVTANSDf + 2U, // VCVTANSDh + 2U, // VCVTANSQf + 2U, // VCVTANSQh + 2U, // VCVTANUDf + 2U, // VCVTANUDh + 2U, // VCVTANUQf + 2U, // VCVTANUQh + 2U, // VCVTASD + 2U, // VCVTASH + 2U, // VCVTASS + 2U, // VCVTAUD + 2U, // VCVTAUH + 2U, // VCVTAUS + 0U, // VCVTBDH + 0U, // VCVTBHD + 0U, // VCVTBHS + 2U, // VCVTBSH + 0U, // VCVTDS + 2U, // VCVTMNSDf + 2U, // VCVTMNSDh + 2U, // VCVTMNSQf + 2U, // VCVTMNSQh + 2U, // VCVTMNUDf + 2U, // VCVTMNUDh + 2U, // VCVTMNUQf + 2U, // VCVTMNUQh + 2U, // VCVTMSD + 2U, // VCVTMSH + 2U, // VCVTMSS + 2U, // VCVTMUD + 2U, // VCVTMUH + 2U, // VCVTMUS + 2U, // VCVTNNSDf + 2U, // VCVTNNSDh + 2U, // VCVTNNSQf + 2U, // VCVTNNSQh + 2U, // VCVTNNUDf + 2U, // VCVTNNUDh + 2U, // VCVTNNUQf + 2U, // VCVTNNUQh + 2U, // VCVTNSD + 2U, // VCVTNSH + 2U, // VCVTNSS + 2U, // VCVTNUD + 2U, // VCVTNUH + 2U, // VCVTNUS + 2U, // VCVTPNSDf + 2U, // VCVTPNSDh + 2U, // VCVTPNSQf + 2U, // VCVTPNSQh + 2U, // VCVTPNUDf + 2U, // VCVTPNUDh + 2U, // VCVTPNUQf + 2U, // VCVTPNUQh + 2U, // VCVTPSD + 2U, // VCVTPSH + 2U, // VCVTPSS + 2U, // VCVTPUD + 2U, // VCVTPUH + 2U, // VCVTPUS + 0U, // VCVTSD + 0U, // VCVTTDH + 0U, // VCVTTHD + 0U, // VCVTTHS + 2U, // VCVTTSH + 2U, // VCVTf2h + 0U, // VCVTf2sd + 0U, // VCVTf2sq + 0U, // VCVTf2ud + 0U, // VCVTf2uq + 534U, // VCVTf2xsd + 534U, // VCVTf2xsq + 534U, // VCVTf2xud + 534U, // VCVTf2xuq + 0U, // VCVTh2f + 0U, // VCVTh2sd + 0U, // VCVTh2sq + 0U, // VCVTh2ud + 0U, // VCVTh2uq + 534U, // VCVTh2xsd + 534U, // VCVTh2xsq + 534U, // VCVTh2xud + 534U, // VCVTh2xuq + 0U, // VCVTs2fd + 0U, // VCVTs2fq + 0U, // VCVTs2hd + 0U, // VCVTs2hq + 0U, // VCVTu2fd + 0U, // VCVTu2fq + 0U, // VCVTu2hd + 0U, // VCVTu2hq + 534U, // VCVTxs2fd + 534U, // VCVTxs2fq + 534U, // VCVTxs2hd + 534U, // VCVTxs2hq + 534U, // VCVTxu2fd + 534U, // VCVTxu2fq + 534U, // VCVTxu2hd + 534U, // VCVTxu2hq + 2720526U, // VDIVD + 0U, // VDIVH + 0U, // VDIVS + 16384U, // VDUP16d + 16384U, // VDUP16q + 16384U, // VDUP32d + 16384U, // VDUP32q + 16384U, // VDUP8d + 16384U, // VDUP8q + 147456U, // VDUPLN16d + 147456U, // VDUPLN16q + 147456U, // VDUPLN32d + 147456U, // VDUPLN32q + 147456U, // VDUPLN8d + 147456U, // VDUPLN8q + 0U, // VEORd + 0U, // VEORq + 33554432U, // VEXTd16 + 33554432U, // VEXTd32 + 33554432U, // VEXTd8 + 33554432U, // VEXTq16 + 33554432U, // VEXTq32 + 33554432U, // VEXTq64 + 33554432U, // VEXTq8 + 49942U, // VFMAD + 3671680U, // VFMAH + 18048U, // VFMALD + 263808U, // VFMALDI + 18048U, // VFMALQ + 263808U, // VFMALQI + 3671680U, // VFMAS + 3671680U, // VFMAfd + 3671680U, // VFMAfq + 3671680U, // VFMAhd + 3671680U, // VFMAhq + 49942U, // VFMSD + 3671680U, // VFMSH + 18048U, // VFMSLD + 263808U, // VFMSLDI + 18048U, // VFMSLQ + 263808U, // VFMSLQI + 3671680U, // VFMSS + 3671680U, // VFMSfd + 3671680U, // VFMSfq + 3671680U, // VFMShd + 3671680U, // VFMShq + 49942U, // VFNMAD + 3671680U, // VFNMAH + 3671680U, // VFNMAS + 49942U, // VFNMSD + 3671680U, // VFNMSH + 3671680U, // VFNMSS + 18048U, // VFP_VMAXNMD + 18048U, // VFP_VMAXNMH + 18048U, // VFP_VMAXNMS + 18048U, // VFP_VMINNMD + 18048U, // VFP_VMINNMH + 18048U, // VFP_VMINNMS + 147456U, // VGETLNi32 + 147456U, // VGETLNs16 + 147456U, // VGETLNs8 + 147456U, // VGETLNu16 + 147456U, // VGETLNu8 + 0U, // VHADDsv16i8 + 0U, // VHADDsv2i32 + 0U, // VHADDsv4i16 + 0U, // VHADDsv4i32 + 0U, // VHADDsv8i16 + 0U, // VHADDsv8i8 + 0U, // VHADDuv16i8 + 0U, // VHADDuv2i32 + 0U, // VHADDuv4i16 + 0U, // VHADDuv4i32 + 0U, // VHADDuv8i16 + 0U, // VHADDuv8i8 + 0U, // VHSUBsv16i8 + 0U, // VHSUBsv2i32 + 0U, // VHSUBsv4i16 + 0U, // VHSUBsv4i32 + 0U, // VHSUBsv8i16 + 0U, // VHSUBsv8i8 + 0U, // VHSUBuv16i8 + 0U, // VHSUBuv2i32 + 0U, // VHSUBuv4i16 + 0U, // VHSUBuv4i32 + 0U, // VHSUBuv8i16 + 0U, // VHSUBuv8i8 + 2U, // VINSH + 0U, // VJCVT + 518U, // VLD1DUPd16 + 676U, // VLD1DUPd16wb_fixed + 2687780U, // VLD1DUPd16wb_register + 518U, // VLD1DUPd32 + 676U, // VLD1DUPd32wb_fixed + 2687780U, // VLD1DUPd32wb_register + 518U, // VLD1DUPd8 + 676U, // VLD1DUPd8wb_fixed + 2687780U, // VLD1DUPd8wb_register + 518U, // VLD1DUPq16 + 676U, // VLD1DUPq16wb_fixed + 2687780U, // VLD1DUPq16wb_register + 518U, // VLD1DUPq32 + 676U, // VLD1DUPq32wb_fixed + 2687780U, // VLD1DUPq32wb_register + 518U, // VLD1DUPq8 + 676U, // VLD1DUPq8wb_fixed + 2687780U, // VLD1DUPq8wb_register + 12342694U, // VLD1LNd16 + 12867110U, // VLD1LNd16_UPD + 12342694U, // VLD1LNd32 + 12867110U, // VLD1LNd32_UPD + 12342694U, // VLD1LNd8 + 12867110U, // VLD1LNd8_UPD + 0U, // VLD1LNq16Pseudo + 0U, // VLD1LNq16Pseudo_UPD + 0U, // VLD1LNq32Pseudo + 0U, // VLD1LNq32Pseudo_UPD + 0U, // VLD1LNq8Pseudo + 0U, // VLD1LNq8Pseudo_UPD + 518U, // VLD1d16 + 518U, // VLD1d16Q + 0U, // VLD1d16QPseudo + 0U, // VLD1d16QPseudoWB_fixed + 0U, // VLD1d16QPseudoWB_register + 676U, // VLD1d16Qwb_fixed + 2687780U, // VLD1d16Qwb_register + 518U, // VLD1d16T + 0U, // VLD1d16TPseudo + 0U, // VLD1d16TPseudoWB_fixed + 0U, // VLD1d16TPseudoWB_register + 676U, // VLD1d16Twb_fixed + 2687780U, // VLD1d16Twb_register + 676U, // VLD1d16wb_fixed + 2687780U, // VLD1d16wb_register + 518U, // VLD1d32 + 518U, // VLD1d32Q + 0U, // VLD1d32QPseudo + 0U, // VLD1d32QPseudoWB_fixed + 0U, // VLD1d32QPseudoWB_register + 676U, // VLD1d32Qwb_fixed + 2687780U, // VLD1d32Qwb_register + 518U, // VLD1d32T + 0U, // VLD1d32TPseudo + 0U, // VLD1d32TPseudoWB_fixed + 0U, // VLD1d32TPseudoWB_register + 676U, // VLD1d32Twb_fixed + 2687780U, // VLD1d32Twb_register + 676U, // VLD1d32wb_fixed + 2687780U, // VLD1d32wb_register + 518U, // VLD1d64 + 518U, // VLD1d64Q + 0U, // VLD1d64QPseudo + 0U, // VLD1d64QPseudoWB_fixed + 0U, // VLD1d64QPseudoWB_register + 676U, // VLD1d64Qwb_fixed + 2687780U, // VLD1d64Qwb_register + 518U, // VLD1d64T + 0U, // VLD1d64TPseudo + 0U, // VLD1d64TPseudoWB_fixed + 0U, // VLD1d64TPseudoWB_register + 676U, // VLD1d64Twb_fixed + 2687780U, // VLD1d64Twb_register + 676U, // VLD1d64wb_fixed + 2687780U, // VLD1d64wb_register + 518U, // VLD1d8 + 518U, // VLD1d8Q + 0U, // VLD1d8QPseudo + 0U, // VLD1d8QPseudoWB_fixed + 0U, // VLD1d8QPseudoWB_register + 676U, // VLD1d8Qwb_fixed + 2687780U, // VLD1d8Qwb_register + 518U, // VLD1d8T + 0U, // VLD1d8TPseudo + 0U, // VLD1d8TPseudoWB_fixed + 0U, // VLD1d8TPseudoWB_register + 676U, // VLD1d8Twb_fixed + 2687780U, // VLD1d8Twb_register + 676U, // VLD1d8wb_fixed + 2687780U, // VLD1d8wb_register + 518U, // VLD1q16 + 0U, // VLD1q16HighQPseudo + 0U, // VLD1q16HighQPseudo_UPD + 0U, // VLD1q16HighTPseudo + 0U, // VLD1q16HighTPseudo_UPD + 0U, // VLD1q16LowQPseudo_UPD + 0U, // VLD1q16LowTPseudo_UPD + 676U, // VLD1q16wb_fixed + 2687780U, // VLD1q16wb_register + 518U, // VLD1q32 + 0U, // VLD1q32HighQPseudo + 0U, // VLD1q32HighQPseudo_UPD + 0U, // VLD1q32HighTPseudo + 0U, // VLD1q32HighTPseudo_UPD + 0U, // VLD1q32LowQPseudo_UPD + 0U, // VLD1q32LowTPseudo_UPD + 676U, // VLD1q32wb_fixed + 2687780U, // VLD1q32wb_register + 518U, // VLD1q64 + 0U, // VLD1q64HighQPseudo + 0U, // VLD1q64HighQPseudo_UPD + 0U, // VLD1q64HighTPseudo + 0U, // VLD1q64HighTPseudo_UPD + 0U, // VLD1q64LowQPseudo_UPD + 0U, // VLD1q64LowTPseudo_UPD + 676U, // VLD1q64wb_fixed + 2687780U, // VLD1q64wb_register + 518U, // VLD1q8 + 0U, // VLD1q8HighQPseudo + 0U, // VLD1q8HighQPseudo_UPD + 0U, // VLD1q8HighTPseudo + 0U, // VLD1q8HighTPseudo_UPD + 0U, // VLD1q8LowQPseudo_UPD + 0U, // VLD1q8LowTPseudo_UPD + 676U, // VLD1q8wb_fixed + 2687780U, // VLD1q8wb_register + 518U, // VLD2DUPd16 + 676U, // VLD2DUPd16wb_fixed + 2687780U, // VLD2DUPd16wb_register + 518U, // VLD2DUPd16x2 + 676U, // VLD2DUPd16x2wb_fixed + 2687780U, // VLD2DUPd16x2wb_register + 518U, // VLD2DUPd32 + 676U, // VLD2DUPd32wb_fixed + 2687780U, // VLD2DUPd32wb_register + 518U, // VLD2DUPd32x2 + 676U, // VLD2DUPd32x2wb_fixed + 2687780U, // VLD2DUPd32x2wb_register + 518U, // VLD2DUPd8 + 676U, // VLD2DUPd8wb_fixed + 2687780U, // VLD2DUPd8wb_register + 518U, // VLD2DUPd8x2 + 676U, // VLD2DUPd8x2wb_fixed + 2687780U, // VLD2DUPd8x2wb_register + 0U, // VLD2DUPq16EvenPseudo + 0U, // VLD2DUPq16OddPseudo + 0U, // VLD2DUPq16OddPseudoWB_fixed + 0U, // VLD2DUPq16OddPseudoWB_register + 0U, // VLD2DUPq32EvenPseudo + 0U, // VLD2DUPq32OddPseudo + 0U, // VLD2DUPq32OddPseudoWB_fixed + 0U, // VLD2DUPq32OddPseudoWB_register + 0U, // VLD2DUPq8EvenPseudo + 0U, // VLD2DUPq8OddPseudo + 0U, // VLD2DUPq8OddPseudoWB_fixed + 0U, // VLD2DUPq8OddPseudoWB_register + 13407782U, // VLD2LNd16 + 0U, // VLD2LNd16Pseudo + 0U, // VLD2LNd16Pseudo_UPD + 13948582U, // VLD2LNd16_UPD + 13407782U, // VLD2LNd32 + 0U, // VLD2LNd32Pseudo + 0U, // VLD2LNd32Pseudo_UPD + 13948582U, // VLD2LNd32_UPD + 13407782U, // VLD2LNd8 + 0U, // VLD2LNd8Pseudo + 0U, // VLD2LNd8Pseudo_UPD + 13948582U, // VLD2LNd8_UPD + 13407782U, // VLD2LNq16 + 0U, // VLD2LNq16Pseudo + 0U, // VLD2LNq16Pseudo_UPD + 13948582U, // VLD2LNq16_UPD + 13407782U, // VLD2LNq32 + 0U, // VLD2LNq32Pseudo + 0U, // VLD2LNq32Pseudo_UPD + 13948582U, // VLD2LNq32_UPD + 518U, // VLD2b16 + 676U, // VLD2b16wb_fixed + 2687780U, // VLD2b16wb_register + 518U, // VLD2b32 + 676U, // VLD2b32wb_fixed + 2687780U, // VLD2b32wb_register + 518U, // VLD2b8 + 676U, // VLD2b8wb_fixed + 2687780U, // VLD2b8wb_register + 518U, // VLD2d16 + 676U, // VLD2d16wb_fixed + 2687780U, // VLD2d16wb_register + 518U, // VLD2d32 + 676U, // VLD2d32wb_fixed + 2687780U, // VLD2d32wb_register + 518U, // VLD2d8 + 676U, // VLD2d8wb_fixed + 2687780U, // VLD2d8wb_register + 518U, // VLD2q16 + 0U, // VLD2q16Pseudo + 0U, // VLD2q16PseudoWB_fixed + 0U, // VLD2q16PseudoWB_register + 676U, // VLD2q16wb_fixed + 2687780U, // VLD2q16wb_register + 518U, // VLD2q32 + 0U, // VLD2q32Pseudo + 0U, // VLD2q32PseudoWB_fixed + 0U, // VLD2q32PseudoWB_register + 676U, // VLD2q32wb_fixed + 2687780U, // VLD2q32wb_register + 518U, // VLD2q8 + 0U, // VLD2q8Pseudo + 0U, // VLD2q8PseudoWB_fixed + 0U, // VLD2q8PseudoWB_register + 676U, // VLD2q8wb_fixed + 2687780U, // VLD2q8wb_register + 333608U, // VLD3DUPd16 + 0U, // VLD3DUPd16Pseudo + 0U, // VLD3DUPd16Pseudo_UPD + 14505768U, // VLD3DUPd16_UPD + 333608U, // VLD3DUPd32 + 0U, // VLD3DUPd32Pseudo + 0U, // VLD3DUPd32Pseudo_UPD + 14505768U, // VLD3DUPd32_UPD + 333608U, // VLD3DUPd8 + 0U, // VLD3DUPd8Pseudo + 0U, // VLD3DUPd8Pseudo_UPD + 14505768U, // VLD3DUPd8_UPD + 333608U, // VLD3DUPq16 + 0U, // VLD3DUPq16EvenPseudo + 0U, // VLD3DUPq16OddPseudo + 0U, // VLD3DUPq16OddPseudo_UPD + 14505768U, // VLD3DUPq16_UPD + 333608U, // VLD3DUPq32 + 0U, // VLD3DUPq32EvenPseudo + 0U, // VLD3DUPq32OddPseudo + 0U, // VLD3DUPq32OddPseudo_UPD + 14505768U, // VLD3DUPq32_UPD + 333608U, // VLD3DUPq8 + 0U, // VLD3DUPq8EvenPseudo + 0U, // VLD3DUPq8OddPseudo + 0U, // VLD3DUPq8OddPseudo_UPD + 14505768U, // VLD3DUPq8_UPD + 14997158U, // VLD3LNd16 + 0U, // VLD3LNd16Pseudo + 0U, // VLD3LNd16Pseudo_UPD + 15488934U, // VLD3LNd16_UPD + 14997158U, // VLD3LNd32 + 0U, // VLD3LNd32Pseudo + 0U, // VLD3LNd32Pseudo_UPD + 15488934U, // VLD3LNd32_UPD + 14997158U, // VLD3LNd8 + 0U, // VLD3LNd8Pseudo + 0U, // VLD3LNd8Pseudo_UPD + 15488934U, // VLD3LNd8_UPD + 14997158U, // VLD3LNq16 + 0U, // VLD3LNq16Pseudo + 0U, // VLD3LNq16Pseudo_UPD + 15488934U, // VLD3LNq16_UPD + 14997158U, // VLD3LNq32 + 0U, // VLD3LNq32Pseudo + 0U, // VLD3LNq32Pseudo_UPD + 15488934U, // VLD3LNq32_UPD + 335544320U, // VLD3d16 + 0U, // VLD3d16Pseudo + 0U, // VLD3d16Pseudo_UPD + 335544320U, // VLD3d16_UPD + 335544320U, // VLD3d32 + 0U, // VLD3d32Pseudo + 0U, // VLD3d32Pseudo_UPD + 335544320U, // VLD3d32_UPD + 335544320U, // VLD3d8 + 0U, // VLD3d8Pseudo + 0U, // VLD3d8Pseudo_UPD + 335544320U, // VLD3d8_UPD + 335544320U, // VLD3q16 + 0U, // VLD3q16Pseudo_UPD + 335544320U, // VLD3q16_UPD + 0U, // VLD3q16oddPseudo + 0U, // VLD3q16oddPseudo_UPD + 335544320U, // VLD3q32 + 0U, // VLD3q32Pseudo_UPD + 335544320U, // VLD3q32_UPD + 0U, // VLD3q32oddPseudo + 0U, // VLD3q32oddPseudo_UPD + 335544320U, // VLD3q8 + 0U, // VLD3q8Pseudo_UPD + 335544320U, // VLD3q8_UPD + 0U, // VLD3q8oddPseudo + 0U, // VLD3q8oddPseudo_UPD + 2971688U, // VLD4DUPd16 + 0U, // VLD4DUPd16Pseudo + 0U, // VLD4DUPd16Pseudo_UPD + 366632U, // VLD4DUPd16_UPD + 2971688U, // VLD4DUPd32 + 0U, // VLD4DUPd32Pseudo + 0U, // VLD4DUPd32Pseudo_UPD + 366632U, // VLD4DUPd32_UPD + 2971688U, // VLD4DUPd8 + 0U, // VLD4DUPd8Pseudo + 0U, // VLD4DUPd8Pseudo_UPD + 366632U, // VLD4DUPd8_UPD + 2971688U, // VLD4DUPq16 + 0U, // VLD4DUPq16EvenPseudo + 0U, // VLD4DUPq16OddPseudo + 0U, // VLD4DUPq16OddPseudo_UPD + 366632U, // VLD4DUPq16_UPD + 2971688U, // VLD4DUPq32 + 0U, // VLD4DUPq32EvenPseudo + 0U, // VLD4DUPq32OddPseudo + 0U, // VLD4DUPq32OddPseudo_UPD + 366632U, // VLD4DUPq32_UPD + 2971688U, // VLD4DUPq8 + 0U, // VLD4DUPq8EvenPseudo + 0U, // VLD4DUPq8OddPseudo + 0U, // VLD4DUPq8OddPseudo_UPD + 366632U, // VLD4DUPq8_UPD + 373069734U, // VLD4LNd16 + 0U, // VLD4LNd16Pseudo + 0U, // VLD4LNd16Pseudo_UPD + 6310U, // VLD4LNd16_UPD + 373069734U, // VLD4LNd32 + 0U, // VLD4LNd32Pseudo + 0U, // VLD4LNd32Pseudo_UPD + 6310U, // VLD4LNd32_UPD + 373069734U, // VLD4LNd8 + 0U, // VLD4LNd8Pseudo + 0U, // VLD4LNd8Pseudo_UPD + 6310U, // VLD4LNd8_UPD + 373069734U, // VLD4LNq16 + 0U, // VLD4LNq16Pseudo + 0U, // VLD4LNq16Pseudo_UPD + 6310U, // VLD4LNq16_UPD + 373069734U, // VLD4LNq32 + 0U, // VLD4LNq32Pseudo + 0U, // VLD4LNq32Pseudo_UPD + 6310U, // VLD4LNq32_UPD + 33554432U, // VLD4d16 + 0U, // VLD4d16Pseudo + 0U, // VLD4d16Pseudo_UPD + 33554432U, // VLD4d16_UPD + 33554432U, // VLD4d32 + 0U, // VLD4d32Pseudo + 0U, // VLD4d32Pseudo_UPD + 33554432U, // VLD4d32_UPD + 33554432U, // VLD4d8 + 0U, // VLD4d8Pseudo + 0U, // VLD4d8Pseudo_UPD + 33554432U, // VLD4d8_UPD + 33554432U, // VLD4q16 + 0U, // VLD4q16Pseudo_UPD + 33554432U, // VLD4q16_UPD + 0U, // VLD4q16oddPseudo + 0U, // VLD4q16oddPseudo_UPD + 33554432U, // VLD4q32 + 0U, // VLD4q32Pseudo_UPD + 33554432U, // VLD4q32_UPD + 0U, // VLD4q32oddPseudo + 0U, // VLD4q32oddPseudo_UPD + 33554432U, // VLD4q8 + 0U, // VLD4q8Pseudo_UPD + 33554432U, // VLD4q8_UPD + 0U, // VLD4q8oddPseudo + 0U, // VLD4q8oddPseudo_UPD + 530U, // VLDMDDB_UPD + 18688U, // VLDMDIA + 530U, // VLDMDIA_UPD + 0U, // VLDMQIA + 530U, // VLDMSDB_UPD + 18688U, // VLDMSIA + 530U, // VLDMSIA_UPD + 6400U, // VLDRD + 6528U, // VLDRH + 6400U, // VLDRS + 0U, // VLDR_FPCXTNS_off + 42U, // VLDR_FPCXTNS_post + 0U, // VLDR_FPCXTNS_pre + 0U, // VLDR_FPCXTS_off + 42U, // VLDR_FPCXTS_post + 0U, // VLDR_FPCXTS_pre + 0U, // VLDR_FPSCR_NZCVQC_off + 42U, // VLDR_FPSCR_NZCVQC_post + 0U, // VLDR_FPSCR_NZCVQC_pre + 0U, // VLDR_FPSCR_off + 42U, // VLDR_FPSCR_post + 0U, // VLDR_FPSCR_pre + 0U, // VLDR_P0_off + 44U, // VLDR_P0_post + 0U, // VLDR_P0_pre + 0U, // VLDR_VPR_off + 42U, // VLDR_VPR_post + 0U, // VLDR_VPR_pre + 2U, // VLLDM + 2U, // VLSTM + 0U, // VMAXfd + 0U, // VMAXfq + 0U, // VMAXhd + 0U, // VMAXhq + 0U, // VMAXsv16i8 + 0U, // VMAXsv2i32 + 0U, // VMAXsv4i16 + 0U, // VMAXsv4i32 + 0U, // VMAXsv8i16 + 0U, // VMAXsv8i8 + 0U, // VMAXuv16i8 + 0U, // VMAXuv2i32 + 0U, // VMAXuv4i16 + 0U, // VMAXuv4i32 + 0U, // VMAXuv8i16 + 0U, // VMAXuv8i8 + 0U, // VMINfd + 0U, // VMINfq + 0U, // VMINhd + 0U, // VMINhq + 0U, // VMINsv16i8 + 0U, // VMINsv2i32 + 0U, // VMINsv4i16 + 0U, // VMINsv4i32 + 0U, // VMINsv8i16 + 0U, // VMINsv8i8 + 0U, // VMINuv16i8 + 0U, // VMINuv2i32 + 0U, // VMINuv4i16 + 0U, // VMINuv4i32 + 0U, // VMINuv8i16 + 0U, // VMINuv8i8 + 49942U, // VMLAD + 3671680U, // VMLAH + 406324864U, // VMLALslsv2i32 + 406324864U, // VMLALslsv4i16 + 406324864U, // VMLALsluv2i32 + 406324864U, // VMLALsluv4i16 + 3671680U, // VMLALsv2i64 + 3671680U, // VMLALsv4i32 + 3671680U, // VMLALsv8i16 + 3671680U, // VMLALuv2i64 + 3671680U, // VMLALuv4i32 + 3671680U, // VMLALuv8i16 + 3671680U, // VMLAS + 3671680U, // VMLAfd + 3671680U, // VMLAfq + 3671680U, // VMLAhd + 3671680U, // VMLAhq + 406324864U, // VMLAslfd + 406324864U, // VMLAslfq + 406324864U, // VMLAslhd + 406324864U, // VMLAslhq + 406324864U, // VMLAslv2i32 + 406324864U, // VMLAslv4i16 + 406324864U, // VMLAslv4i32 + 406324864U, // VMLAslv8i16 + 3671680U, // VMLAv16i8 + 3671680U, // VMLAv2i32 + 3671680U, // VMLAv4i16 + 3671680U, // VMLAv4i32 + 3671680U, // VMLAv8i16 + 3671680U, // VMLAv8i8 + 49942U, // VMLSD + 3671680U, // VMLSH + 406324864U, // VMLSLslsv2i32 + 406324864U, // VMLSLslsv4i16 + 406324864U, // VMLSLsluv2i32 + 406324864U, // VMLSLsluv4i16 + 3671680U, // VMLSLsv2i64 + 3671680U, // VMLSLsv4i32 + 3671680U, // VMLSLsv8i16 + 3671680U, // VMLSLuv2i64 + 3671680U, // VMLSLuv4i32 + 3671680U, // VMLSLuv8i16 + 3671680U, // VMLSS + 3671680U, // VMLSfd + 3671680U, // VMLSfq + 3671680U, // VMLShd + 3671680U, // VMLShq + 406324864U, // VMLSslfd + 406324864U, // VMLSslfq + 406324864U, // VMLSslhd + 406324864U, // VMLSslhq + 406324864U, // VMLSslv2i32 + 406324864U, // VMLSslv4i16 + 406324864U, // VMLSslv4i32 + 406324864U, // VMLSslv8i16 + 3671680U, // VMLSv16i8 + 3671680U, // VMLSv2i32 + 3671680U, // VMLSv4i16 + 3671680U, // VMLSv4i32 + 3671680U, // VMLSv8i16 + 3671680U, // VMLSv8i8 + 520U, // VMMLA + 526U, // VMOVD + 0U, // VMOVDRR + 2U, // VMOVH + 16384U, // VMOVHR + 16384U, // VMOVLsv2i64 + 16384U, // VMOVLsv4i32 + 16384U, // VMOVLsv8i16 + 16384U, // VMOVLuv2i64 + 16384U, // VMOVLuv4i32 + 16384U, // VMOVLuv8i16 + 2U, // VMOVNv2i32 + 16384U, // VMOVNv4i16 + 16384U, // VMOVNv8i8 + 16384U, // VMOVRH + 0U, // VMOVRRD + 33554432U, // VMOVRRS + 16384U, // VMOVRS + 16384U, // VMOVS + 16384U, // VMOVSR + 33554432U, // VMOVSRR + 5120U, // VMOVv16i8 + 0U, // VMOVv1i64 + 2176U, // VMOVv2f32 + 5120U, // VMOVv2i32 + 0U, // VMOVv2i64 + 2176U, // VMOVv4f32 + 5120U, // VMOVv4i16 + 5120U, // VMOVv4i32 + 5120U, // VMOVv8i16 + 5120U, // VMOVv8i8 + 46U, // VMRS + 48U, // VMRS_FPCXTNS + 50U, // VMRS_FPCXTS + 52U, // VMRS_FPEXC + 54U, // VMRS_FPINST + 56U, // VMRS_FPINST2 + 58U, // VMRS_FPSCR_NZCVQC + 60U, // VMRS_FPSID + 62U, // VMRS_MVFR0 + 64U, // VMRS_MVFR1 + 66U, // VMRS_MVFR2 + 68U, // VMRS_P0 + 70U, // VMRS_VPR + 2U, // VMSR + 2U, // VMSR_FPCXTNS + 2U, // VMSR_FPCXTS + 0U, // VMSR_FPEXC + 0U, // VMSR_FPINST + 0U, // VMSR_FPINST2 + 2U, // VMSR_FPSCR_NZCVQC + 0U, // VMSR_FPSID + 2U, // VMSR_P0 + 2U, // VMSR_VPR + 2720526U, // VMULD + 0U, // VMULH + 18048U, // VMULLp64 + 0U, // VMULLp8 + 167772160U, // VMULLslsv2i32 + 167772160U, // VMULLslsv4i16 + 167772160U, // VMULLsluv2i32 + 167772160U, // VMULLsluv4i16 + 0U, // VMULLsv2i64 + 0U, // VMULLsv4i32 + 0U, // VMULLsv8i16 + 0U, // VMULLuv2i64 + 0U, // VMULLuv4i32 + 0U, // VMULLuv8i16 + 0U, // VMULS + 0U, // VMULfd + 0U, // VMULfq + 0U, // VMULhd + 0U, // VMULhq + 0U, // VMULpd + 0U, // VMULpq + 167772160U, // VMULslfd + 167772160U, // VMULslfq + 167772160U, // VMULslhd + 167772160U, // VMULslhq + 167772160U, // VMULslv2i32 + 167772160U, // VMULslv4i16 + 167772160U, // VMULslv4i32 + 167772160U, // VMULslv8i16 + 0U, // VMULv16i8 + 0U, // VMULv2i32 + 0U, // VMULv4i16 + 0U, // VMULv4i32 + 0U, // VMULv8i16 + 0U, // VMULv8i8 + 16384U, // VMVNd + 16384U, // VMVNq + 5120U, // VMVNv2i32 + 5120U, // VMVNv4i16 + 5120U, // VMVNv4i32 + 5120U, // VMVNv8i16 + 526U, // VNEGD + 16384U, // VNEGH + 16384U, // VNEGS + 16384U, // VNEGf32q + 16384U, // VNEGfd + 16384U, // VNEGhd + 16384U, // VNEGhq + 16384U, // VNEGs16d + 16384U, // VNEGs16q + 16384U, // VNEGs32d + 16384U, // VNEGs32q + 16384U, // VNEGs8d + 16384U, // VNEGs8q + 49942U, // VNMLAD + 3671680U, // VNMLAH + 3671680U, // VNMLAS + 49942U, // VNMLSD + 3671680U, // VNMLSH + 3671680U, // VNMLSS + 2720526U, // VNMULD + 0U, // VNMULH + 0U, // VNMULS + 0U, // VORNd + 0U, // VORNq + 0U, // VORRd + 5120U, // VORRiv2i32 + 5120U, // VORRiv4i16 + 5120U, // VORRiv4i32 + 5120U, // VORRiv8i16 + 0U, // VORRq + 18048U, // VPADALsv16i8 + 18048U, // VPADALsv2i32 + 18048U, // VPADALsv4i16 + 18048U, // VPADALsv4i32 + 18048U, // VPADALsv8i16 + 18048U, // VPADALsv8i8 + 18048U, // VPADALuv16i8 + 18048U, // VPADALuv2i32 + 18048U, // VPADALuv4i16 + 18048U, // VPADALuv4i32 + 18048U, // VPADALuv8i16 + 18048U, // VPADALuv8i8 + 16384U, // VPADDLsv16i8 + 16384U, // VPADDLsv2i32 + 16384U, // VPADDLsv4i16 + 16384U, // VPADDLsv4i32 + 16384U, // VPADDLsv8i16 + 16384U, // VPADDLsv8i8 + 16384U, // VPADDLuv16i8 + 16384U, // VPADDLuv2i32 + 16384U, // VPADDLuv4i16 + 16384U, // VPADDLuv4i32 + 16384U, // VPADDLuv8i16 + 16384U, // VPADDLuv8i8 + 0U, // VPADDf + 0U, // VPADDh + 0U, // VPADDi16 + 0U, // VPADDi32 + 0U, // VPADDi8 + 0U, // VPMAXf + 0U, // VPMAXh + 0U, // VPMAXs16 + 0U, // VPMAXs32 + 0U, // VPMAXs8 + 0U, // VPMAXu16 + 0U, // VPMAXu32 + 0U, // VPMAXu8 + 0U, // VPMINf + 0U, // VPMINh + 0U, // VPMINs16 + 0U, // VPMINs32 + 0U, // VPMINs8 + 0U, // VPMINu16 + 0U, // VPMINu32 + 0U, // VPMINu8 + 16384U, // VQABSv16i8 + 16384U, // VQABSv2i32 + 16384U, // VQABSv4i16 + 16384U, // VQABSv4i32 + 16384U, // VQABSv8i16 + 16384U, // VQABSv8i8 + 0U, // VQADDsv16i8 + 18048U, // VQADDsv1i64 + 0U, // VQADDsv2i32 + 18048U, // VQADDsv2i64 + 0U, // VQADDsv4i16 + 0U, // VQADDsv4i32 + 0U, // VQADDsv8i16 + 0U, // VQADDsv8i8 + 0U, // VQADDuv16i8 + 0U, // VQADDuv1i64 + 0U, // VQADDuv2i32 + 0U, // VQADDuv2i64 + 0U, // VQADDuv4i16 + 0U, // VQADDuv4i32 + 0U, // VQADDuv8i16 + 0U, // VQADDuv8i8 + 406324864U, // VQDMLALslv2i32 + 406324864U, // VQDMLALslv4i16 + 3671680U, // VQDMLALv2i64 + 3671680U, // VQDMLALv4i32 + 406324864U, // VQDMLSLslv2i32 + 406324864U, // VQDMLSLslv4i16 + 3671680U, // VQDMLSLv2i64 + 3671680U, // VQDMLSLv4i32 + 167772160U, // VQDMULHslv2i32 + 167772160U, // VQDMULHslv4i16 + 167772160U, // VQDMULHslv4i32 + 167772160U, // VQDMULHslv8i16 + 0U, // VQDMULHv2i32 + 0U, // VQDMULHv4i16 + 0U, // VQDMULHv4i32 + 0U, // VQDMULHv8i16 + 167772160U, // VQDMULLslv2i32 + 167772160U, // VQDMULLslv4i16 + 0U, // VQDMULLv2i64 + 0U, // VQDMULLv4i32 + 2U, // VQMOVNsuv2i32 + 16384U, // VQMOVNsuv4i16 + 16384U, // VQMOVNsuv8i8 + 2U, // VQMOVNsv2i32 + 16384U, // VQMOVNsv4i16 + 16384U, // VQMOVNsv8i8 + 16384U, // VQMOVNuv2i32 + 16384U, // VQMOVNuv4i16 + 16384U, // VQMOVNuv8i8 + 16384U, // VQNEGv16i8 + 16384U, // VQNEGv2i32 + 16384U, // VQNEGv4i16 + 16384U, // VQNEGv4i32 + 16384U, // VQNEGv8i16 + 16384U, // VQNEGv8i8 + 406324864U, // VQRDMLAHslv2i32 + 406324864U, // VQRDMLAHslv4i16 + 406324864U, // VQRDMLAHslv4i32 + 406324864U, // VQRDMLAHslv8i16 + 3671680U, // VQRDMLAHv2i32 + 3671680U, // VQRDMLAHv4i16 + 3671680U, // VQRDMLAHv4i32 + 3671680U, // VQRDMLAHv8i16 + 406324864U, // VQRDMLSHslv2i32 + 406324864U, // VQRDMLSHslv4i16 + 406324864U, // VQRDMLSHslv4i32 + 406324864U, // VQRDMLSHslv8i16 + 3671680U, // VQRDMLSHv2i32 + 3671680U, // VQRDMLSHv4i16 + 3671680U, // VQRDMLSHv4i32 + 3671680U, // VQRDMLSHv8i16 + 167772160U, // VQRDMULHslv2i32 + 167772160U, // VQRDMULHslv4i16 + 167772160U, // VQRDMULHslv4i32 + 167772160U, // VQRDMULHslv8i16 + 0U, // VQRDMULHv2i32 + 0U, // VQRDMULHv4i16 + 0U, // VQRDMULHv4i32 + 0U, // VQRDMULHv8i16 + 0U, // VQRSHLsv16i8 + 18048U, // VQRSHLsv1i64 + 0U, // VQRSHLsv2i32 + 18048U, // VQRSHLsv2i64 + 0U, // VQRSHLsv4i16 + 0U, // VQRSHLsv4i32 + 0U, // VQRSHLsv8i16 + 0U, // VQRSHLsv8i8 + 0U, // VQRSHLuv16i8 + 0U, // VQRSHLuv1i64 + 0U, // VQRSHLuv2i32 + 0U, // VQRSHLuv2i64 + 0U, // VQRSHLuv4i16 + 0U, // VQRSHLuv4i32 + 0U, // VQRSHLuv8i16 + 0U, // VQRSHLuv8i8 + 18048U, // VQRSHRNsv2i32 + 0U, // VQRSHRNsv4i16 + 0U, // VQRSHRNsv8i8 + 0U, // VQRSHRNuv2i32 + 0U, // VQRSHRNuv4i16 + 0U, // VQRSHRNuv8i8 + 18048U, // VQRSHRUNv2i32 + 0U, // VQRSHRUNv4i16 + 0U, // VQRSHRUNv8i8 + 0U, // VQSHLsiv16i8 + 18048U, // VQSHLsiv1i64 + 0U, // VQSHLsiv2i32 + 18048U, // VQSHLsiv2i64 + 0U, // VQSHLsiv4i16 + 0U, // VQSHLsiv4i32 + 0U, // VQSHLsiv8i16 + 0U, // VQSHLsiv8i8 + 0U, // VQSHLsuv16i8 + 18048U, // VQSHLsuv1i64 + 0U, // VQSHLsuv2i32 + 18048U, // VQSHLsuv2i64 + 0U, // VQSHLsuv4i16 + 0U, // VQSHLsuv4i32 + 0U, // VQSHLsuv8i16 + 0U, // VQSHLsuv8i8 + 0U, // VQSHLsv16i8 + 18048U, // VQSHLsv1i64 + 0U, // VQSHLsv2i32 + 18048U, // VQSHLsv2i64 + 0U, // VQSHLsv4i16 + 0U, // VQSHLsv4i32 + 0U, // VQSHLsv8i16 + 0U, // VQSHLsv8i8 + 0U, // VQSHLuiv16i8 + 0U, // VQSHLuiv1i64 + 0U, // VQSHLuiv2i32 + 0U, // VQSHLuiv2i64 + 0U, // VQSHLuiv4i16 + 0U, // VQSHLuiv4i32 + 0U, // VQSHLuiv8i16 + 0U, // VQSHLuiv8i8 + 0U, // VQSHLuv16i8 + 0U, // VQSHLuv1i64 + 0U, // VQSHLuv2i32 + 0U, // VQSHLuv2i64 + 0U, // VQSHLuv4i16 + 0U, // VQSHLuv4i32 + 0U, // VQSHLuv8i16 + 0U, // VQSHLuv8i8 + 18048U, // VQSHRNsv2i32 + 0U, // VQSHRNsv4i16 + 0U, // VQSHRNsv8i8 + 0U, // VQSHRNuv2i32 + 0U, // VQSHRNuv4i16 + 0U, // VQSHRNuv8i8 + 18048U, // VQSHRUNv2i32 + 0U, // VQSHRUNv4i16 + 0U, // VQSHRUNv8i8 + 0U, // VQSUBsv16i8 + 18048U, // VQSUBsv1i64 + 0U, // VQSUBsv2i32 + 18048U, // VQSUBsv2i64 + 0U, // VQSUBsv4i16 + 0U, // VQSUBsv4i32 + 0U, // VQSUBsv8i16 + 0U, // VQSUBsv8i8 + 0U, // VQSUBuv16i8 + 0U, // VQSUBuv1i64 + 0U, // VQSUBuv2i32 + 0U, // VQSUBuv2i64 + 0U, // VQSUBuv4i16 + 0U, // VQSUBuv4i32 + 0U, // VQSUBuv8i16 + 0U, // VQSUBuv8i8 + 18048U, // VRADDHNv2i32 + 0U, // VRADDHNv4i16 + 0U, // VRADDHNv8i8 + 16384U, // VRECPEd + 16384U, // VRECPEfd + 16384U, // VRECPEfq + 16384U, // VRECPEhd + 16384U, // VRECPEhq + 16384U, // VRECPEq + 0U, // VRECPSfd + 0U, // VRECPSfq + 0U, // VRECPShd + 0U, // VRECPShq + 16384U, // VREV16d8 + 16384U, // VREV16q8 + 16384U, // VREV32d16 + 16384U, // VREV32d8 + 16384U, // VREV32q16 + 16384U, // VREV32q8 + 16384U, // VREV64d16 + 16384U, // VREV64d32 + 16384U, // VREV64d8 + 16384U, // VREV64q16 + 16384U, // VREV64q32 + 16384U, // VREV64q8 + 0U, // VRHADDsv16i8 + 0U, // VRHADDsv2i32 + 0U, // VRHADDsv4i16 + 0U, // VRHADDsv4i32 + 0U, // VRHADDsv8i16 + 0U, // VRHADDsv8i8 + 0U, // VRHADDuv16i8 + 0U, // VRHADDuv2i32 + 0U, // VRHADDuv4i16 + 0U, // VRHADDuv4i32 + 0U, // VRHADDuv8i16 + 0U, // VRHADDuv8i8 + 2U, // VRINTAD + 2U, // VRINTAH + 2U, // VRINTANDf + 2U, // VRINTANDh + 2U, // VRINTANQf + 2U, // VRINTANQh + 2U, // VRINTAS + 2U, // VRINTMD + 2U, // VRINTMH + 2U, // VRINTMNDf + 2U, // VRINTMNDh + 2U, // VRINTMNQf + 2U, // VRINTMNQh + 2U, // VRINTMS + 2U, // VRINTND + 2U, // VRINTNH + 2U, // VRINTNNDf + 2U, // VRINTNNDh + 2U, // VRINTNNQf + 2U, // VRINTNNQh + 2U, // VRINTNS + 2U, // VRINTPD + 2U, // VRINTPH + 2U, // VRINTPNDf + 2U, // VRINTPNDh + 2U, // VRINTPNQf + 2U, // VRINTPNQh + 2U, // VRINTPS + 526U, // VRINTRD + 16384U, // VRINTRH + 16384U, // VRINTRS + 526U, // VRINTXD + 16384U, // VRINTXH + 2U, // VRINTXNDf + 2U, // VRINTXNDh + 2U, // VRINTXNQf + 2U, // VRINTXNQh + 16384U, // VRINTXS + 526U, // VRINTZD + 16384U, // VRINTZH + 2U, // VRINTZNDf + 2U, // VRINTZNDh + 2U, // VRINTZNQf + 2U, // VRINTZNQh + 16384U, // VRINTZS + 0U, // VRSHLsv16i8 + 18048U, // VRSHLsv1i64 + 0U, // VRSHLsv2i32 + 18048U, // VRSHLsv2i64 + 0U, // VRSHLsv4i16 + 0U, // VRSHLsv4i32 + 0U, // VRSHLsv8i16 + 0U, // VRSHLsv8i8 + 0U, // VRSHLuv16i8 + 0U, // VRSHLuv1i64 + 0U, // VRSHLuv2i32 + 0U, // VRSHLuv2i64 + 0U, // VRSHLuv4i16 + 0U, // VRSHLuv4i32 + 0U, // VRSHLuv8i16 + 0U, // VRSHLuv8i8 + 18048U, // VRSHRNv2i32 + 0U, // VRSHRNv4i16 + 0U, // VRSHRNv8i8 + 0U, // VRSHRsv16i8 + 18048U, // VRSHRsv1i64 + 0U, // VRSHRsv2i32 + 18048U, // VRSHRsv2i64 + 0U, // VRSHRsv4i16 + 0U, // VRSHRsv4i32 + 0U, // VRSHRsv8i16 + 0U, // VRSHRsv8i8 + 0U, // VRSHRuv16i8 + 0U, // VRSHRuv1i64 + 0U, // VRSHRuv2i32 + 0U, // VRSHRuv2i64 + 0U, // VRSHRuv4i16 + 0U, // VRSHRuv4i32 + 0U, // VRSHRuv8i16 + 0U, // VRSHRuv8i8 + 16384U, // VRSQRTEd + 16384U, // VRSQRTEfd + 16384U, // VRSQRTEfq + 16384U, // VRSQRTEhd + 16384U, // VRSQRTEhq + 16384U, // VRSQRTEq + 0U, // VRSQRTSfd + 0U, // VRSQRTSfq + 0U, // VRSQRTShd + 0U, // VRSQRTShq + 3671680U, // VRSRAsv16i8 + 16768U, // VRSRAsv1i64 + 3671680U, // VRSRAsv2i32 + 16768U, // VRSRAsv2i64 + 3671680U, // VRSRAsv4i16 + 3671680U, // VRSRAsv4i32 + 3671680U, // VRSRAsv8i16 + 3671680U, // VRSRAsv8i8 + 3671680U, // VRSRAuv16i8 + 3671680U, // VRSRAuv1i64 + 3671680U, // VRSRAuv2i32 + 3671680U, // VRSRAuv2i64 + 3671680U, // VRSRAuv4i16 + 3671680U, // VRSRAuv4i32 + 3671680U, // VRSRAuv8i16 + 3671680U, // VRSRAuv8i8 + 18048U, // VRSUBHNv2i32 + 0U, // VRSUBHNv4i16 + 0U, // VRSUBHNv8i8 + 0U, // VSCCLRMD + 0U, // VSCCLRMS + 520U, // VSDOTD + 1416U, // VSDOTDI + 520U, // VSDOTQ + 1416U, // VSDOTQI + 18048U, // VSELEQD + 18048U, // VSELEQH + 18048U, // VSELEQS + 18048U, // VSELGED + 18048U, // VSELGEH + 18048U, // VSELGES + 18048U, // VSELGTD + 18048U, // VSELGTH + 18048U, // VSELGTS + 18048U, // VSELVSD + 18048U, // VSELVSH + 18048U, // VSELVSS + 32U, // VSETLNi16 + 32U, // VSETLNi32 + 32U, // VSETLNi8 + 0U, // VSHLLi16 + 0U, // VSHLLi32 + 0U, // VSHLLi8 + 0U, // VSHLLsv2i64 + 0U, // VSHLLsv4i32 + 0U, // VSHLLsv8i16 + 0U, // VSHLLuv2i64 + 0U, // VSHLLuv4i32 + 0U, // VSHLLuv8i16 + 0U, // VSHLiv16i8 + 18048U, // VSHLiv1i64 + 0U, // VSHLiv2i32 + 18048U, // VSHLiv2i64 + 0U, // VSHLiv4i16 + 0U, // VSHLiv4i32 + 0U, // VSHLiv8i16 + 0U, // VSHLiv8i8 + 0U, // VSHLsv16i8 + 18048U, // VSHLsv1i64 + 0U, // VSHLsv2i32 + 18048U, // VSHLsv2i64 + 0U, // VSHLsv4i16 + 0U, // VSHLsv4i32 + 0U, // VSHLsv8i16 + 0U, // VSHLsv8i8 + 0U, // VSHLuv16i8 + 0U, // VSHLuv1i64 + 0U, // VSHLuv2i32 + 0U, // VSHLuv2i64 + 0U, // VSHLuv4i16 + 0U, // VSHLuv4i32 + 0U, // VSHLuv8i16 + 0U, // VSHLuv8i8 + 18048U, // VSHRNv2i32 + 0U, // VSHRNv4i16 + 0U, // VSHRNv8i8 + 0U, // VSHRsv16i8 + 18048U, // VSHRsv1i64 + 0U, // VSHRsv2i32 + 18048U, // VSHRsv2i64 + 0U, // VSHRsv4i16 + 0U, // VSHRsv4i32 + 0U, // VSHRsv8i16 + 0U, // VSHRsv8i8 + 0U, // VSHRuv16i8 + 0U, // VSHRuv1i64 + 0U, // VSHRuv2i32 + 0U, // VSHRuv2i64 + 0U, // VSHRuv4i16 + 0U, // VSHRuv4i32 + 0U, // VSHRuv8i16 + 0U, // VSHRuv8i8 + 0U, // VSHTOD + 72U, // VSHTOH + 0U, // VSHTOS + 0U, // VSITOD + 0U, // VSITOH + 0U, // VSITOS + 3671680U, // VSLIv16i8 + 3671680U, // VSLIv1i64 + 3671680U, // VSLIv2i32 + 3671680U, // VSLIv2i64 + 3671680U, // VSLIv4i16 + 3671680U, // VSLIv4i32 + 3671680U, // VSLIv8i16 + 3671680U, // VSLIv8i8 + 74U, // VSLTOD + 74U, // VSLTOH + 74U, // VSLTOS + 520U, // VSMMLA + 526U, // VSQRTD + 16384U, // VSQRTH + 16384U, // VSQRTS + 3671680U, // VSRAsv16i8 + 16768U, // VSRAsv1i64 + 3671680U, // VSRAsv2i32 + 16768U, // VSRAsv2i64 + 3671680U, // VSRAsv4i16 + 3671680U, // VSRAsv4i32 + 3671680U, // VSRAsv8i16 + 3671680U, // VSRAsv8i8 + 3671680U, // VSRAuv16i8 + 3671680U, // VSRAuv1i64 + 3671680U, // VSRAuv2i32 + 3671680U, // VSRAuv2i64 + 3671680U, // VSRAuv4i16 + 3671680U, // VSRAuv4i32 + 3671680U, // VSRAuv8i16 + 3671680U, // VSRAuv8i8 + 3671680U, // VSRIv16i8 + 3671680U, // VSRIv1i64 + 3671680U, // VSRIv2i32 + 3671680U, // VSRIv2i64 + 3671680U, // VSRIv4i16 + 3671680U, // VSRIv4i32 + 3671680U, // VSRIv8i16 + 3671680U, // VSRIv8i8 + 6694U, // VST1LNd16 + 448551590U, // VST1LNd16_UPD + 6694U, // VST1LNd32 + 448551590U, // VST1LNd32_UPD + 6694U, // VST1LNd8 + 448551590U, // VST1LNd8_UPD + 0U, // VST1LNq16Pseudo + 0U, // VST1LNq16Pseudo_UPD + 0U, // VST1LNq32Pseudo + 0U, // VST1LNq32Pseudo_UPD + 0U, // VST1LNq8Pseudo + 0U, // VST1LNq8Pseudo_UPD + 0U, // VST1d16 + 0U, // VST1d16Q + 0U, // VST1d16QPseudo + 0U, // VST1d16QPseudoWB_fixed + 0U, // VST1d16QPseudoWB_register + 0U, // VST1d16Qwb_fixed + 0U, // VST1d16Qwb_register + 0U, // VST1d16T + 0U, // VST1d16TPseudo + 0U, // VST1d16TPseudoWB_fixed + 0U, // VST1d16TPseudoWB_register + 0U, // VST1d16Twb_fixed + 0U, // VST1d16Twb_register + 0U, // VST1d16wb_fixed + 0U, // VST1d16wb_register + 0U, // VST1d32 + 0U, // VST1d32Q + 0U, // VST1d32QPseudo + 0U, // VST1d32QPseudoWB_fixed + 0U, // VST1d32QPseudoWB_register + 0U, // VST1d32Qwb_fixed + 0U, // VST1d32Qwb_register + 0U, // VST1d32T + 0U, // VST1d32TPseudo + 0U, // VST1d32TPseudoWB_fixed + 0U, // VST1d32TPseudoWB_register + 0U, // VST1d32Twb_fixed + 0U, // VST1d32Twb_register + 0U, // VST1d32wb_fixed + 0U, // VST1d32wb_register + 0U, // VST1d64 + 0U, // VST1d64Q + 0U, // VST1d64QPseudo + 0U, // VST1d64QPseudoWB_fixed + 0U, // VST1d64QPseudoWB_register + 0U, // VST1d64Qwb_fixed + 0U, // VST1d64Qwb_register + 0U, // VST1d64T + 0U, // VST1d64TPseudo + 0U, // VST1d64TPseudoWB_fixed + 0U, // VST1d64TPseudoWB_register + 0U, // VST1d64Twb_fixed + 0U, // VST1d64Twb_register + 0U, // VST1d64wb_fixed + 0U, // VST1d64wb_register + 0U, // VST1d8 + 0U, // VST1d8Q + 0U, // VST1d8QPseudo + 0U, // VST1d8QPseudoWB_fixed + 0U, // VST1d8QPseudoWB_register + 0U, // VST1d8Qwb_fixed + 0U, // VST1d8Qwb_register + 0U, // VST1d8T + 0U, // VST1d8TPseudo + 0U, // VST1d8TPseudoWB_fixed + 0U, // VST1d8TPseudoWB_register + 0U, // VST1d8Twb_fixed + 0U, // VST1d8Twb_register + 0U, // VST1d8wb_fixed + 0U, // VST1d8wb_register + 0U, // VST1q16 + 0U, // VST1q16HighQPseudo + 0U, // VST1q16HighQPseudo_UPD + 0U, // VST1q16HighTPseudo + 0U, // VST1q16HighTPseudo_UPD + 0U, // VST1q16LowQPseudo_UPD + 0U, // VST1q16LowTPseudo_UPD + 0U, // VST1q16wb_fixed + 0U, // VST1q16wb_register + 0U, // VST1q32 + 0U, // VST1q32HighQPseudo + 0U, // VST1q32HighQPseudo_UPD + 0U, // VST1q32HighTPseudo + 0U, // VST1q32HighTPseudo_UPD + 0U, // VST1q32LowQPseudo_UPD + 0U, // VST1q32LowTPseudo_UPD + 0U, // VST1q32wb_fixed + 0U, // VST1q32wb_register + 0U, // VST1q64 + 0U, // VST1q64HighQPseudo + 0U, // VST1q64HighQPseudo_UPD + 0U, // VST1q64HighTPseudo + 0U, // VST1q64HighTPseudo_UPD + 0U, // VST1q64LowQPseudo_UPD + 0U, // VST1q64LowTPseudo_UPD + 0U, // VST1q64wb_fixed + 0U, // VST1q64wb_register + 0U, // VST1q8 + 0U, // VST1q8HighQPseudo + 0U, // VST1q8HighQPseudo_UPD + 0U, // VST1q8HighTPseudo + 0U, // VST1q8HighTPseudo_UPD + 0U, // VST1q8LowQPseudo_UPD + 0U, // VST1q8LowTPseudo_UPD + 0U, // VST1q8wb_fixed + 0U, // VST1q8wb_register + 373069222U, // VST2LNd16 + 0U, // VST2LNd16Pseudo + 0U, // VST2LNd16Pseudo_UPD + 373593638U, // VST2LNd16_UPD + 373069222U, // VST2LNd32 + 0U, // VST2LNd32Pseudo + 0U, // VST2LNd32Pseudo_UPD + 373593638U, // VST2LNd32_UPD + 373069222U, // VST2LNd8 + 0U, // VST2LNd8Pseudo + 0U, // VST2LNd8Pseudo_UPD + 373593638U, // VST2LNd8_UPD + 373069222U, // VST2LNq16 + 0U, // VST2LNq16Pseudo + 0U, // VST2LNq16Pseudo_UPD + 373593638U, // VST2LNq16_UPD + 373069222U, // VST2LNq32 + 0U, // VST2LNq32Pseudo + 0U, // VST2LNq32Pseudo_UPD + 373593638U, // VST2LNq32_UPD + 0U, // VST2b16 + 0U, // VST2b16wb_fixed + 0U, // VST2b16wb_register + 0U, // VST2b32 + 0U, // VST2b32wb_fixed + 0U, // VST2b32wb_register + 0U, // VST2b8 + 0U, // VST2b8wb_fixed + 0U, // VST2b8wb_register + 0U, // VST2d16 + 0U, // VST2d16wb_fixed + 0U, // VST2d16wb_register + 0U, // VST2d32 + 0U, // VST2d32wb_fixed + 0U, // VST2d32wb_register + 0U, // VST2d8 + 0U, // VST2d8wb_fixed + 0U, // VST2d8wb_register + 0U, // VST2q16 + 0U, // VST2q16Pseudo + 0U, // VST2q16PseudoWB_fixed + 0U, // VST2q16PseudoWB_register + 0U, // VST2q16wb_fixed + 0U, // VST2q16wb_register + 0U, // VST2q32 + 0U, // VST2q32Pseudo + 0U, // VST2q32PseudoWB_fixed + 0U, // VST2q32PseudoWB_register + 0U, // VST2q32wb_fixed + 0U, // VST2q32wb_register + 0U, // VST2q8 + 0U, // VST2q8Pseudo + 0U, // VST2q8PseudoWB_fixed + 0U, // VST2q8PseudoWB_register + 0U, // VST2q8wb_fixed + 0U, // VST2q8wb_register + 373070502U, // VST3LNd16 + 0U, // VST3LNd16Pseudo + 0U, // VST3LNd16Pseudo_UPD + 6950U, // VST3LNd16_UPD + 373070502U, // VST3LNd32 + 0U, // VST3LNd32Pseudo + 0U, // VST3LNd32Pseudo_UPD + 6950U, // VST3LNd32_UPD + 373070502U, // VST3LNd8 + 0U, // VST3LNd8Pseudo + 0U, // VST3LNd8Pseudo_UPD + 6950U, // VST3LNd8_UPD + 373070502U, // VST3LNq16 + 0U, // VST3LNq16Pseudo + 0U, // VST3LNq16Pseudo_UPD + 6950U, // VST3LNq16_UPD + 373070502U, // VST3LNq32 + 0U, // VST3LNq32Pseudo + 0U, // VST3LNq32Pseudo_UPD + 6950U, // VST3LNq32_UPD + 336068992U, // VST3d16 + 0U, // VST3d16Pseudo + 0U, // VST3d16Pseudo_UPD + 383872U, // VST3d16_UPD + 336068992U, // VST3d32 + 0U, // VST3d32Pseudo + 0U, // VST3d32Pseudo_UPD + 383872U, // VST3d32_UPD + 336068992U, // VST3d8 + 0U, // VST3d8Pseudo + 0U, // VST3d8Pseudo_UPD + 383872U, // VST3d8_UPD + 336068992U, // VST3q16 + 0U, // VST3q16Pseudo_UPD + 383872U, // VST3q16_UPD + 0U, // VST3q16oddPseudo + 0U, // VST3q16oddPseudo_UPD + 336068992U, // VST3q32 + 0U, // VST3q32Pseudo_UPD + 383872U, // VST3q32_UPD + 0U, // VST3q32oddPseudo + 0U, // VST3q32oddPseudo_UPD + 336068992U, // VST3q8 + 0U, // VST3q8Pseudo_UPD + 383872U, // VST3q8_UPD + 0U, // VST3q8oddPseudo + 0U, // VST3q8oddPseudo_UPD + 373069350U, // VST4LNd16 + 0U, // VST4LNd16Pseudo + 0U, // VST4LNd16Pseudo_UPD + 399014U, // VST4LNd16_UPD + 373069350U, // VST4LNd32 + 0U, // VST4LNd32Pseudo + 0U, // VST4LNd32Pseudo_UPD + 399014U, // VST4LNd32_UPD + 373069350U, // VST4LNd8 + 0U, // VST4LNd8Pseudo + 0U, // VST4LNd8Pseudo_UPD + 399014U, // VST4LNd8_UPD + 373069350U, // VST4LNq16 + 0U, // VST4LNq16Pseudo + 0U, // VST4LNq16Pseudo_UPD + 399014U, // VST4LNq16_UPD + 373069350U, // VST4LNq32 + 0U, // VST4LNq32Pseudo + 0U, // VST4LNq32Pseudo_UPD + 399014U, // VST4LNq32_UPD + 34079104U, // VST4d16 + 0U, // VST4d16Pseudo + 0U, // VST4d16Pseudo_UPD + 15735680U, // VST4d16_UPD + 34079104U, // VST4d32 + 0U, // VST4d32Pseudo + 0U, // VST4d32Pseudo_UPD + 15735680U, // VST4d32_UPD + 34079104U, // VST4d8 + 0U, // VST4d8Pseudo + 0U, // VST4d8Pseudo_UPD + 15735680U, // VST4d8_UPD + 34079104U, // VST4q16 + 0U, // VST4q16Pseudo_UPD + 15735680U, // VST4q16_UPD + 0U, // VST4q16oddPseudo + 0U, // VST4q16oddPseudo_UPD + 34079104U, // VST4q32 + 0U, // VST4q32Pseudo_UPD + 15735680U, // VST4q32_UPD + 0U, // VST4q32oddPseudo + 0U, // VST4q32oddPseudo_UPD + 34079104U, // VST4q8 + 0U, // VST4q8Pseudo_UPD + 15735680U, // VST4q8_UPD + 0U, // VST4q8oddPseudo + 0U, // VST4q8oddPseudo_UPD + 530U, // VSTMDDB_UPD + 18688U, // VSTMDIA + 530U, // VSTMDIA_UPD + 0U, // VSTMQIA + 530U, // VSTMSDB_UPD + 18688U, // VSTMSIA + 530U, // VSTMSIA_UPD + 6400U, // VSTRD + 6528U, // VSTRH + 6400U, // VSTRS + 0U, // VSTR_FPCXTNS_off + 42U, // VSTR_FPCXTNS_post + 0U, // VSTR_FPCXTNS_pre + 0U, // VSTR_FPCXTS_off + 42U, // VSTR_FPCXTS_post + 0U, // VSTR_FPCXTS_pre + 0U, // VSTR_FPSCR_NZCVQC_off + 42U, // VSTR_FPSCR_NZCVQC_post + 0U, // VSTR_FPSCR_NZCVQC_pre + 0U, // VSTR_FPSCR_off + 42U, // VSTR_FPSCR_post + 0U, // VSTR_FPSCR_pre + 0U, // VSTR_P0_off + 44U, // VSTR_P0_post + 0U, // VSTR_P0_pre + 0U, // VSTR_VPR_off + 42U, // VSTR_VPR_post + 0U, // VSTR_VPR_pre + 2720526U, // VSUBD + 0U, // VSUBH + 18048U, // VSUBHNv2i32 + 0U, // VSUBHNv4i16 + 0U, // VSUBHNv8i8 + 0U, // VSUBLsv2i64 + 0U, // VSUBLsv4i32 + 0U, // VSUBLsv8i16 + 0U, // VSUBLuv2i64 + 0U, // VSUBLuv4i32 + 0U, // VSUBLuv8i16 + 0U, // VSUBS + 0U, // VSUBWsv2i64 + 0U, // VSUBWsv4i32 + 0U, // VSUBWsv8i16 + 0U, // VSUBWuv2i64 + 0U, // VSUBWuv4i32 + 0U, // VSUBWuv8i16 + 0U, // VSUBfd + 0U, // VSUBfq + 0U, // VSUBhd + 0U, // VSUBhq + 0U, // VSUBv16i8 + 18048U, // VSUBv1i64 + 0U, // VSUBv2i32 + 18048U, // VSUBv2i64 + 0U, // VSUBv4i16 + 0U, // VSUBv4i32 + 0U, // VSUBv8i16 + 0U, // VSUBv8i8 + 1416U, // VSUDOTDI + 1416U, // VSUDOTQI + 16384U, // VSWPd + 16384U, // VSWPq + 7168U, // VTBL1 + 7296U, // VTBL2 + 7424U, // VTBL3 + 0U, // VTBL3Pseudo + 7552U, // VTBL4 + 0U, // VTBL4Pseudo + 7680U, // VTBX1 + 7808U, // VTBX2 + 7936U, // VTBX3 + 0U, // VTBX3Pseudo + 8064U, // VTBX4 + 0U, // VTBX4Pseudo + 0U, // VTOSHD + 72U, // VTOSHH + 0U, // VTOSHS + 0U, // VTOSIRD + 0U, // VTOSIRH + 0U, // VTOSIRS + 0U, // VTOSIZD + 0U, // VTOSIZH + 0U, // VTOSIZS + 74U, // VTOSLD + 74U, // VTOSLH + 74U, // VTOSLS + 0U, // VTOUHD + 72U, // VTOUHH + 0U, // VTOUHS + 0U, // VTOUIRD + 0U, // VTOUIRH + 0U, // VTOUIRS + 0U, // VTOUIZD + 0U, // VTOUIZH + 0U, // VTOUIZS + 74U, // VTOULD + 74U, // VTOULH + 74U, // VTOULS + 16384U, // VTRNd16 + 16384U, // VTRNd32 + 16384U, // VTRNd8 + 16384U, // VTRNq16 + 16384U, // VTRNq32 + 16384U, // VTRNq8 + 0U, // VTSTv16i8 + 0U, // VTSTv2i32 + 0U, // VTSTv4i16 + 0U, // VTSTv4i32 + 0U, // VTSTv8i16 + 0U, // VTSTv8i8 + 520U, // VUDOTD + 1416U, // VUDOTDI + 520U, // VUDOTQ + 1416U, // VUDOTQI + 0U, // VUHTOD + 72U, // VUHTOH + 0U, // VUHTOS + 0U, // VUITOD + 0U, // VUITOH + 0U, // VUITOS + 74U, // VULTOD + 74U, // VULTOH + 74U, // VULTOS + 520U, // VUMMLA + 520U, // VUSDOTD + 1416U, // VUSDOTDI + 520U, // VUSDOTQ + 1416U, // VUSDOTQI + 520U, // VUSMMLA + 16384U, // VUZPd16 + 16384U, // VUZPd8 + 16384U, // VUZPq16 + 16384U, // VUZPq32 + 16384U, // VUZPq8 + 16384U, // VZIPd16 + 16384U, // VZIPd8 + 16384U, // VZIPq16 + 16384U, // VZIPq32 + 16384U, // VZIPq8 + 411904U, // sysLDMDA + 8210U, // sysLDMDA_UPD + 411904U, // sysLDMDB + 8210U, // sysLDMDB_UPD + 411904U, // sysLDMIA + 8210U, // sysLDMIA_UPD + 411904U, // sysLDMIB + 8210U, // sysLDMIB_UPD + 411904U, // sysSTMDA + 8210U, // sysSTMDA_UPD + 411904U, // sysSTMDB + 8210U, // sysSTMDB_UPD + 411904U, // sysSTMIA + 8210U, // sysSTMIA_UPD + 411904U, // sysSTMIB + 8210U, // sysSTMIB_UPD + 0U, // t2ADCri + 0U, // t2ADCrr + 16252928U, // t2ADCrs + 0U, // t2ADDri + 0U, // t2ADDri12 + 0U, // t2ADDrr + 16252928U, // t2ADDrs + 0U, // t2ADDspImm + 0U, // t2ADDspImm12 + 1280U, // t2ADR + 0U, // t2ANDri + 0U, // t2ANDrr + 16252928U, // t2ANDrs + 16777216U, // t2ASRri + 0U, // t2ASRrr + 2U, // t2B + 1536U, // t2BFC + 2098816U, // t2BFI + 16384U, // t2BFLi + 16384U, // t2BFLr + 16384U, // t2BFi + 17303168U, // t2BFic + 16384U, // t2BFr + 0U, // t2BICri + 0U, // t2BICrr + 16252928U, // t2BICrs + 2U, // t2BXJ + 2U, // t2Bcc + 82702U, // t2CDP + 82702U, // t2CDP2 + 0U, // t2CLREX + 0U, // t2CLRM + 16384U, // t2CLZ + 16384U, // t2CMNri + 16384U, // t2CMNzrr + 1024U, // t2CMNzrs + 16384U, // t2CMPri + 16384U, // t2CMPrr + 1024U, // t2CMPrs + 0U, // t2CPS1p + 2U, // t2CPS2p + 18048U, // t2CPS3p + 18048U, // t2CRC32B + 18048U, // t2CRC32CB + 18048U, // t2CRC32CH + 18048U, // t2CRC32CW + 18048U, // t2CRC32H + 18048U, // t2CRC32W + 17303168U, // t2CSEL + 17303168U, // t2CSINC + 17303168U, // t2CSINV + 17303168U, // t2CSNEG + 2U, // t2DBG + 0U, // t2DCPS1 + 0U, // t2DCPS2 + 0U, // t2DCPS3 + 2U, // t2DLS + 0U, // t2DMB + 0U, // t2DSB + 0U, // t2EORri + 0U, // t2EORrr + 16252928U, // t2EORrs + 2U, // t2HINT + 0U, // t2HVC + 0U, // t2ISB + 0U, // t2IT + 0U, // t2Int_eh_sjlj_setjmp + 0U, // t2Int_eh_sjlj_setjmp_nofp + 128U, // t2LDA + 128U, // t2LDAB + 128U, // t2LDAEX + 128U, // t2LDAEXB + 10485760U, // t2LDAEXD + 128U, // t2LDAEXH + 128U, // t2LDAH + 2708U, // t2LDC2L_OFFSET + 4721428U, // t2LDC2L_OPTION + 5245716U, // t2LDC2L_POST + 2964U, // t2LDC2L_PRE + 2708U, // t2LDC2_OFFSET + 4721428U, // t2LDC2_OPTION + 5245716U, // t2LDC2_POST + 2964U, // t2LDC2_PRE + 2708U, // t2LDCL_OFFSET + 4721428U, // t2LDCL_OPTION + 5245716U, // t2LDCL_POST + 2964U, // t2LDCL_PRE + 2708U, // t2LDC_OFFSET + 4721428U, // t2LDC_OPTION + 5245716U, // t2LDC_POST + 2964U, // t2LDC_PRE + 18688U, // t2LDMDB + 530U, // t2LDMDB_UPD + 18688U, // t2LDMIA + 530U, // t2LDMIA_UPD + 4224U, // t2LDRBT + 133888U, // t2LDRB_POST + 4608U, // t2LDRB_PRE + 3328U, // t2LDRBi12 + 4224U, // t2LDRBi8 + 8320U, // t2LDRBpci + 8448U, // t2LDRBs + 476577792U, // t2LDRD_POST + 17825792U, // t2LDRD_PRE + 18350080U, // t2LDRDi8 + 8576U, // t2LDREX + 128U, // t2LDREXB + 10485760U, // t2LDREXD + 128U, // t2LDREXH + 4224U, // t2LDRHT + 133888U, // t2LDRH_POST + 4608U, // t2LDRH_PRE + 3328U, // t2LDRHi12 + 4224U, // t2LDRHi8 + 8320U, // t2LDRHpci + 8448U, // t2LDRHs + 4224U, // t2LDRSBT + 133888U, // t2LDRSB_POST + 4608U, // t2LDRSB_PRE + 3328U, // t2LDRSBi12 + 4224U, // t2LDRSBi8 + 8320U, // t2LDRSBpci + 8448U, // t2LDRSBs + 4224U, // t2LDRSHT + 133888U, // t2LDRSH_POST + 4608U, // t2LDRSH_PRE + 3328U, // t2LDRSHi12 + 4224U, // t2LDRSHi8 + 8320U, // t2LDRSHpci + 8448U, // t2LDRSHs + 4224U, // t2LDRT + 133888U, // t2LDR_POST + 4608U, // t2LDR_PRE + 3328U, // t2LDRi12 + 4224U, // t2LDRi8 + 8320U, // t2LDRpci + 8448U, // t2LDRs + 0U, // t2LE + 0U, // t2LEUpdate + 0U, // t2LSLri + 0U, // t2LSLrr + 16777216U, // t2LSRri + 0U, // t2LSRrr + 103908110U, // t2MCR + 103908110U, // t2MCR2 + 137462542U, // t2MCRR + 137462542U, // t2MCRR2 + 33554432U, // t2MLA + 33554432U, // t2MLS + 18048U, // t2MOVTi16 + 16384U, // t2MOVi + 16384U, // t2MOVi16 + 16384U, // t2MOVr + 425984U, // t2MOVsra_flag + 425984U, // t2MOVsrl_flag + 115478U, // t2MRC + 115478U, // t2MRC2 + 0U, // t2MRRC + 0U, // t2MRRC2 + 24U, // t2MRS_AR + 8704U, // t2MRS_M + 3968U, // t2MRSbanked + 26U, // t2MRSsys_AR + 526U, // t2MSR_AR + 526U, // t2MSR_M + 0U, // t2MSRbanked + 0U, // t2MUL + 16384U, // t2MVNi + 16384U, // t2MVNr + 1024U, // t2MVNs + 0U, // t2ORNri + 0U, // t2ORNrr + 16252928U, // t2ORNrs + 0U, // t2ORRri + 0U, // t2ORRrr + 16252928U, // t2ORRrs + 201326592U, // t2PKHBT + 234881024U, // t2PKHTB + 0U, // t2PLDWi12 + 0U, // t2PLDWi8 + 0U, // t2PLDWs + 0U, // t2PLDi12 + 0U, // t2PLDi8 + 0U, // t2PLDpci + 0U, // t2PLDs + 0U, // t2PLIi12 + 0U, // t2PLIi8 + 0U, // t2PLIpci + 0U, // t2PLIs + 0U, // t2QADD + 0U, // t2QADD16 + 0U, // t2QADD8 + 0U, // t2QASX + 0U, // t2QDADD + 0U, // t2QDSUB + 0U, // t2QSAX + 0U, // t2QSUB + 0U, // t2QSUB16 + 0U, // t2QSUB8 + 16384U, // t2RBIT + 16384U, // t2REV + 16384U, // t2REV16 + 16384U, // t2REVSH + 2U, // t2RFEDB + 4U, // t2RFEDBW + 2U, // t2RFEIA + 4U, // t2RFEIAW + 0U, // t2RORri + 0U, // t2RORrr + 16384U, // t2RRX + 0U, // t2RSBri + 0U, // t2RSBrr + 16252928U, // t2RSBrs + 0U, // t2SADD16 + 0U, // t2SADD8 + 0U, // t2SASX + 0U, // t2SB + 0U, // t2SBCri + 0U, // t2SBCrr + 16252928U, // t2SBCrs + 33554432U, // t2SBFX + 0U, // t2SDIV + 0U, // t2SEL + 0U, // t2SETPAN + 0U, // t2SG + 0U, // t2SHADD16 + 0U, // t2SHADD8 + 0U, // t2SHASX + 0U, // t2SHSAX + 0U, // t2SHSUB16 + 0U, // t2SHSUB8 + 2U, // t2SMC + 33554432U, // t2SMLABB + 33554432U, // t2SMLABT + 33554432U, // t2SMLAD + 33554432U, // t2SMLADX + 33554432U, // t2SMLAL + 33554432U, // t2SMLALBB + 33554432U, // t2SMLALBT + 33554432U, // t2SMLALD + 33554432U, // t2SMLALDX + 33554432U, // t2SMLALTB + 33554432U, // t2SMLALTT + 33554432U, // t2SMLATB + 33554432U, // t2SMLATT + 33554432U, // t2SMLAWB + 33554432U, // t2SMLAWT + 33554432U, // t2SMLSD + 33554432U, // t2SMLSDX + 33554432U, // t2SMLSLD + 33554432U, // t2SMLSLDX + 33554432U, // t2SMMLA + 33554432U, // t2SMMLAR + 33554432U, // t2SMMLS + 33554432U, // t2SMMLSR + 0U, // t2SMMUL + 0U, // t2SMMULR + 0U, // t2SMUAD + 0U, // t2SMUADX + 0U, // t2SMULBB + 0U, // t2SMULBT + 33554432U, // t2SMULL + 0U, // t2SMULTB + 0U, // t2SMULTT + 0U, // t2SMULWB + 0U, // t2SMULWT + 0U, // t2SMUSD + 0U, // t2SMUSDX + 0U, // t2SRSDB + 0U, // t2SRSDB_UPD + 0U, // t2SRSIA + 0U, // t2SRSIA_UPD + 201856U, // t2SSAT + 21632U, // t2SSAT16 + 0U, // t2SSAX + 0U, // t2SSUB16 + 0U, // t2SSUB8 + 2708U, // t2STC2L_OFFSET + 4721428U, // t2STC2L_OPTION + 5245716U, // t2STC2L_POST + 2964U, // t2STC2L_PRE + 2708U, // t2STC2_OFFSET + 4721428U, // t2STC2_OPTION + 5245716U, // t2STC2_POST + 2964U, // t2STC2_PRE + 2708U, // t2STCL_OFFSET + 4721428U, // t2STCL_OPTION + 5245716U, // t2STCL_POST + 2964U, // t2STCL_PRE + 2708U, // t2STC_OFFSET + 4721428U, // t2STC_OPTION + 5245716U, // t2STC_POST + 2964U, // t2STC_PRE + 128U, // t2STL + 128U, // t2STLB + 10485760U, // t2STLEX + 10485760U, // t2STLEXB + 33554432U, // t2STLEXD + 10485760U, // t2STLEXH + 128U, // t2STLH + 18688U, // t2STMDB + 530U, // t2STMDB_UPD + 18688U, // t2STMIA + 530U, // t2STMIA_UPD + 4224U, // t2STRBT + 133888U, // t2STRB_POST + 4608U, // t2STRB_PRE + 3328U, // t2STRBi12 + 4224U, // t2STRBi8 + 8448U, // t2STRBs + 476579456U, // t2STRD_POST + 17827456U, // t2STRD_PRE + 18350080U, // t2STRDi8 + 18874368U, // t2STREX + 10485760U, // t2STREXB + 33554432U, // t2STREXD + 10485760U, // t2STREXH + 4224U, // t2STRHT + 133888U, // t2STRH_POST + 4608U, // t2STRH_PRE + 3328U, // t2STRHi12 + 4224U, // t2STRHi8 + 8448U, // t2STRHs + 4224U, // t2STRT + 133888U, // t2STR_POST + 4608U, // t2STR_PRE + 3328U, // t2STRi12 + 4224U, // t2STRi8 + 8448U, // t2STRs + 0U, // t2SUBS_PC_LR + 0U, // t2SUBri + 0U, // t2SUBri12 + 0U, // t2SUBrr + 16252928U, // t2SUBrs + 0U, // t2SUBspImm + 0U, // t2SUBspImm12 + 268435456U, // t2SXTAB + 268435456U, // t2SXTAB16 + 268435456U, // t2SXTAH + 212992U, // t2SXTB + 212992U, // t2SXTB16 + 212992U, // t2SXTH + 1U, // t2TBB + 1U, // t2TBH + 16384U, // t2TEQri + 16384U, // t2TEQrr + 1024U, // t2TEQrs + 1U, // t2TSB + 16384U, // t2TSTri + 16384U, // t2TSTrr + 1024U, // t2TSTrs + 16384U, // t2TT + 16384U, // t2TTA + 16384U, // t2TTAT + 16384U, // t2TTT + 0U, // t2UADD16 + 0U, // t2UADD8 + 0U, // t2UASX + 33554432U, // t2UBFX + 0U, // t2UDF + 0U, // t2UDIV + 0U, // t2UHADD16 + 0U, // t2UHADD8 + 0U, // t2UHASX + 0U, // t2UHSAX + 0U, // t2UHSUB16 + 0U, // t2UHSUB8 + 33554432U, // t2UMAAL + 33554432U, // t2UMLAL + 33554432U, // t2UMULL + 0U, // t2UQADD16 + 0U, // t2UQADD8 + 0U, // t2UQASX + 0U, // t2UQSAX + 0U, // t2UQSUB16 + 0U, // t2UQSUB8 + 0U, // t2USAD8 + 33554432U, // t2USADA8 + 301989888U, // t2USAT + 0U, // t2USAT16 + 0U, // t2USAX + 0U, // t2USUB16 + 0U, // t2USUB8 + 268435456U, // t2UXTAB + 268435456U, // t2UXTAB16 + 268435456U, // t2UXTAH + 212992U, // t2UXTB + 212992U, // t2UXTB16 + 212992U, // t2UXTH + 18048U, // t2WLS + 2U, // tADC + 18048U, // tADDhirr + 16768U, // tADDi3 + 2U, // tADDi8 + 0U, // tADDrSP + 19398656U, // tADDrSPi + 16768U, // tADDrr + 8832U, // tADDspi + 18048U, // tADDspr + 8960U, // tADR + 2U, // tAND + 9088U, // tASRri + 2U, // tASRrr + 2U, // tB + 2U, // tBIC + 0U, // tBKPT + 2U, // tBL + 2U, // tBLXNSr + 2U, // tBLXi + 2U, // tBLXr + 2U, // tBX + 2U, // tBXNS + 2U, // tBcc + 2U, // tCBNZ + 2U, // tCBZ + 16384U, // tCMNz + 16384U, // tCMPhir + 16384U, // tCMPi8 + 16384U, // tCMPr + 2U, // tCPS + 2U, // tEOR + 2U, // tHINT + 0U, // tHLT + 0U, // tInt_WIN_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_setjmp + 18688U, // tLDMIA + 9216U, // tLDRBi + 9344U, // tLDRBr + 9472U, // tLDRHi + 9344U, // tLDRHr + 9344U, // tLDRSB + 9344U, // tLDRSH + 9600U, // tLDRi + 8320U, // tLDRpci + 9344U, // tLDRr + 9728U, // tLDRspi + 16768U, // tLSLri + 2U, // tLSLrr + 9088U, // tLSRri + 2U, // tLSRrr + 2U, // tMOVSr + 0U, // tMOVi8 + 16384U, // tMOVr + 16768U, // tMUL + 0U, // tMVN + 2U, // tORR + 0U, // tPICADD + 0U, // tPOP + 0U, // tPUSH + 16384U, // tREV + 16384U, // tREV16 + 16384U, // tREVSH + 2U, // tROR + 0U, // tRSB + 2U, // tSBC + 0U, // tSETEND + 530U, // tSTMIA_UPD + 9216U, // tSTRBi + 9344U, // tSTRBr + 9472U, // tSTRHi + 9344U, // tSTRHr + 9600U, // tSTRi + 9344U, // tSTRr + 9728U, // tSTRspi + 16768U, // tSUBi3 + 2U, // tSUBi8 + 16768U, // tSUBrr + 8832U, // tSUBspi + 2U, // tSVC + 16384U, // tSXTB + 16384U, // tSXTH + 0U, // tTRAP + 16384U, // tTST + 0U, // tUDF + 16384U, // tUXTB + 16384U, // tUXTH + 0U, // t__brkdiv0 + }; + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + return createMnemonic(AsmStrs + (Bits & 8191) - 1, Bits); +} +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) { + MCMnemonic MnemonicInfo = ARM_getMnemonic(MI); + +#ifndef CAPSTONE_DIET + + SStream_concat0(O, MnemonicInfo.first); +#endif + + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 6 bits for 42 unique commands. + switch ((Bits >> 13) & 63) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCri, ADCrr, ADDri, A... + printSBitModifierOperand /* printSBitModifierOperand (+ ) */ (MI, 5, O); + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 3, O); + break; + case 2: + // ITasm, t2IT + printThumbITMask /* printThumbITMask (+ ) */ (MI, 1, O); + break; + case 3: + // LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRB... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 2, O); + break; + case 4: + // RRXi, MOVi, MOVr, MOVr_TC, MVNi, MVNr, t2MOVi, t2MOVr, t2MVNi, t2MVNr,... + printSBitModifierOperand /* printSBitModifierOperand (+ ) */ (MI, 4, O); + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 2, O); + break; + case 5: + // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 4, O); + break; + case 6: + // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 5, O); + break; + case 7: + // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 3, O); + break; + case 8: + // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, MLA, MOVsr, MVNsr, ORRrsi, RSB... + printSBitModifierOperand /* printSBitModifierOperand (+ ) */ (MI, 6, O); + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 4, O); + break; + case 9: + // ADCrsr, ADDrsr, ANDrsr, BICrsr, EORrsr, ORRrsr, RSBrsr, RSCrsr, SBCrsr... + printSBitModifierOperand /* printSBitModifierOperand (+ ) */ (MI, 7, O); + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 5, O); + SStream_concat0(O, "\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printSORegRegOperand /* printSORegRegOperand (+ ) */ (MI, 2, O); + return; + break; + case 10: + // AESD, AESE, AESIMC, AESMC, BKPT, BL, BLX, BLXi, BX, CPS1p, CRC32B, CRC... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 11: + // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, MV... + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 12: + // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 1, O); + break; + case 13: + // BX_RET, ERET, FMSTAT, MOVPCLR, MVE_LCTP, VSCCLRMD, VSCCLRMS, t2CLREX, ... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 0, O); + break; + case 14: + // CDE_CX1, CDE_CX1D, CDE_CX2, CDE_CX2D, CDE_CX3, CDE_CX3D, CDE_VCX1A_fpd... + printPImmediate /* printPImmediate (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 15: + // CDE_CX3A, CDE_CX3DA, CDP, LDRD_POST, LDRD_PRE, MCR, MRC, MVE_SQRSHRL, ... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 6, O); + break; + case 16: + // CDE_VCX1A_vec, CDE_VCX2_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, ... + printVPTPredicateOperand /* printVPTPredicateOperand (+ ) */ (MI, 4, O); + break; + case 17: + // CDE_VCX1_vec, MVE_VABDf16, MVE_VABDf32, MVE_VABDs16, MVE_VABDs32, MVE_... + printVPTPredicateOperand /* printVPTPredicateOperand (+ ) */ (MI, 3, O); + break; + case 18: + // CDE_VCX2A_vec, CDE_VCX3_vec, MVE_VADC, MVE_VADDLVs32acc, MVE_VADDLVu32... + printVPTPredicateOperand /* printVPTPredicateOperand (+ ) */ (MI, 5, O); + break; + case 19: + // CDE_VCX3A_vec, MVE_VMLALDAVas16, MVE_VMLALDAVas32, MVE_VMLALDAVau16, M... + printVPTPredicateOperand /* printVPTPredicateOperand (+ ) */ (MI, 6, O); + break; + case 20: + // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, ... + printPImmediate /* printPImmediate (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 21: + // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS + printCPSIMod /* printCPSIMod (+ ) */ (MI, 0, O); + break; + case 22: + // DMB, DSB + printMemBOption /* printMemBOption (+ ) */ (MI, 0, O); + return; + break; + case 23: + // ISB + printInstSyncBOption /* printInstSyncBOption (+ ) */ (MI, 0, O); + return; + break; + case 24: + // MRRC2 + printPImmediate /* printPImmediate (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 4, O); + return; + break; + case 25: + // MVE_VABSf16, MVE_VABSf32, MVE_VABSs16, MVE_VABSs32, MVE_VABSs8, MVE_VA... + printVPTPredicateOperand /* printVPTPredicateOperand (+ ) */ (MI, 2, O); + break; + case 26: + // MVE_VLD20_16, MVE_VLD20_16_wb, MVE_VLD20_32, MVE_VLD20_32_wb, MVE_VLD2... + printMVEVectorList /* printMVEVectorList<2> (+ ) */ (MI, 0, O, 2); + SStream_concat0(O, ", "); + break; + case 27: + // MVE_VLD40_16, MVE_VLD40_16_wb, MVE_VLD40_32, MVE_VLD40_32_wb, MVE_VLD4... + printMVEVectorList /* printMVEVectorList<4> (+ ) */ (MI, 0, O, 4); + SStream_concat0(O, ", "); + break; + case 28: + // MVE_VPST, MVE_VPTv16i8, MVE_VPTv16i8r, MVE_VPTv16s8, MVE_VPTv16s8r, MV... + printVPTMask /* printVPTMask (+ ) */ (MI, 0, O); + break; + case 29: + // MVE_VST20_16_wb, MVE_VST20_32_wb, MVE_VST20_8_wb, MVE_VST21_16_wb, MVE... + printMVEVectorList /* printMVEVectorList<2> (+ ) */ (MI, 1, O, 2); + SStream_concat0(O, ", "); + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 2, O); + SStream_concat0(O, "!"); + return; + break; + case 30: + // MVE_VST40_16_wb, MVE_VST40_32_wb, MVE_VST40_8_wb, MVE_VST41_16_wb, MVE... + printMVEVectorList /* printMVEVectorList<4> (+ ) */ (MI, 1, O, 4); + SStream_concat0(O, ", "); + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 2, O); + SStream_concat0(O, "!"); + return; + break; + case 31: + // PLDWi12, PLDi12, PLIi12 + printAddrModeImm12Operand /* printAddrModeImm12Operand (+ ) */ ( + MI, 0, O, false); + return; + break; + case 32: + // PLDWrs, PLDrs, PLIrs + printAddrMode2Operand /* printAddrMode2Operand (+ ) */ (MI, 0, O); + return; + break; + case 33: + // SETEND, tSETEND + printSetendOperand /* printSetendOperand (+ ) */ (MI, 0, O); + return; + break; + case 34: + // SMLAL, UMLAL + printSBitModifierOperand /* printSBitModifierOperand (+ ) */ (MI, 8, O); + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 6, O); + SStream_concat0(O, "\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 35: + // TSB + printTraceSyncBOption /* printTraceSyncBOption (+ ) */ (MI, 0, O); + return; + break; + case 36: + // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 7, O); + break; + case 37: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 9, O); + break; + case 38: + // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 11, O); + break; + case 39: + // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 8, O); + break; + case 40: + // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 13, O); + break; + case 41: + // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... + printSBitModifierOperand /* printSBitModifierOperand (+ ) */ (MI, 1, O); + break; + } + + // Fragment 1 encoded into 7 bits for 88 unique commands. + switch ((Bits >> 19) & 127) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHT... + SStream_concat0(O, " "); + break; + case 1: + // VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2... + SStream_concat0(O, ".16\t"); + break; + case 2: + // VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2... + SStream_concat0(O, ".32\t"); + break; + case 3: + // VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd... + SStream_concat0(O, ".8\t"); + break; + case 4: + // t2LDR_POST_imm, t2LDR_PRE_imm, t2STR_POST_imm, t2STR_PRE_imm + SStream_concat0(O, ".w "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 5: + // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... + SStream_concat0(O, "\t"); + break; + case 6: + // AESD, AESE, AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, ... + SStream_concat0(O, ", "); + break; + case 7: + // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, MR... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 8: + // BF16_VCVT, BF16_VCVTB, BF16_VCVTT + SStream_concat0(O, ".bf16.f32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 9: + // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R... + return; + break; + case 10: + // BX_RET + SStream_concat0(O, "\tlr"); + return; + break; + case 11: + // CDE_CX1, CDE_CX2, CDE_CX3, CDE_VCX1A_fpdp, CDE_VCX1A_fpsp, CDE_VCX1_fp... + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 12: + // CDE_CX1D, CDE_CX2D, CDE_CX3D + printGPRPairOperand /* printGPRPairOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 13: + // CDP2, MCR2, MCRR2 + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 14: + // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V... + SStream_concat0(O, ".f64\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 15: + // FCONSTH, MVE_VABDf16, MVE_VABSf16, MVE_VADD_qr_f16, MVE_VADDf16, MVE_V... + SStream_concat0(O, ".f16\t"); + break; + case 16: + // FCONSTS, MVE_VABDf32, MVE_VABSf32, MVE_VADD_qr_f32, MVE_VADDf32, MVE_V... + SStream_concat0(O, ".f32\t"); + break; + case 17: + // FMSTAT + SStream_concat0(O, "\tAPSR_nzcv, fpscr"); + return; + break; + case 18: + // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, LDC2_O... + printCImmediate /* printCImmediate (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 19: + // MOVPCLR + SStream_concat0(O, "\tpc, lr"); + return; + break; + case 20: + // MVE_VABAVs16, MVE_VABDs16, MVE_VABSs16, MVE_VADDVs16acc, MVE_VADDVs16n... + SStream_concat0(O, ".s16\t"); + break; + case 21: + // MVE_VABAVs32, MVE_VABDs32, MVE_VABSs32, MVE_VADDLVs32acc, MVE_VADDLVs3... + SStream_concat0(O, ".s32\t"); + break; + case 22: + // MVE_VABAVs8, MVE_VABDs8, MVE_VABSs8, MVE_VADDVs8acc, MVE_VADDVs8no_acc... + SStream_concat0(O, ".s8\t"); + break; + case 23: + // MVE_VABAVu16, MVE_VABDu16, MVE_VADDVu16acc, MVE_VADDVu16no_acc, MVE_VC... + SStream_concat0(O, ".u16\t"); + break; + case 24: + // MVE_VABAVu32, MVE_VABDu32, MVE_VADDLVu32acc, MVE_VADDLVu32no_acc, MVE_... + SStream_concat0(O, ".u32\t"); + break; + case 25: + // MVE_VABAVu8, MVE_VABDu8, MVE_VADDVu8acc, MVE_VADDVu8no_acc, MVE_VCMPu8... + SStream_concat0(O, ".u8\t"); + break; + case 26: + // MVE_VADC, MVE_VADCI, MVE_VADD_qr_i32, MVE_VADDi32, MVE_VBICimmi32, MVE... + SStream_concat0(O, ".i32\t"); + break; + case 27: + // MVE_VADD_qr_i16, MVE_VADDi16, MVE_VBICimmi16, MVE_VCADDi16, MVE_VCLZs1... + SStream_concat0(O, ".i16\t"); + break; + case 28: + // MVE_VADD_qr_i8, MVE_VADDi8, MVE_VCADDi8, MVE_VCLZs8, MVE_VCMPi8, MVE_V... + SStream_concat0(O, ".i8\t"); + break; + case 29: + // MVE_VCTP64, MVE_VSTRD64_qi, MVE_VSTRD64_qi_pre, MVE_VSTRD64_rq, MVE_VS... + SStream_concat0(O, ".64\t"); + break; + case 30: + // MVE_VCVTf16f32bh, MVE_VCVTf16f32th, VCVTBSH, VCVTTSH, VCVTf2h + SStream_concat0(O, ".f16.f32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 31: + // MVE_VCVTf16s16_fix, MVE_VCVTf16s16n, VCVTs2hd, VCVTs2hq, VCVTxs2hd, VC... + SStream_concat0(O, ".f16.s16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 32: + // MVE_VCVTf16u16_fix, MVE_VCVTf16u16n, VCVTu2hd, VCVTu2hq, VCVTxu2hd, VC... + SStream_concat0(O, ".f16.u16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 33: + // MVE_VCVTf32f16bh, MVE_VCVTf32f16th, VCVTBHS, VCVTTHS, VCVTh2f + SStream_concat0(O, ".f32.f16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 34: + // MVE_VCVTf32s32_fix, MVE_VCVTf32s32n, VCVTs2fd, VCVTs2fq, VCVTxs2fd, VC... + SStream_concat0(O, ".f32.s32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 35: + // MVE_VCVTf32u32_fix, MVE_VCVTf32u32n, VCVTu2fd, VCVTu2fq, VCVTxu2fd, VC... + SStream_concat0(O, ".f32.u32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 36: + // MVE_VCVTs16f16_fix, MVE_VCVTs16f16a, MVE_VCVTs16f16m, MVE_VCVTs16f16n,... + SStream_concat0(O, ".s16.f16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 37: + // MVE_VCVTs32f32_fix, MVE_VCVTs32f32a, MVE_VCVTs32f32m, MVE_VCVTs32f32n,... + SStream_concat0(O, ".s32.f32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 38: + // MVE_VCVTu16f16_fix, MVE_VCVTu16f16a, MVE_VCVTu16f16m, MVE_VCVTu16f16n,... + SStream_concat0(O, ".u16.f16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 39: + // MVE_VCVTu32f32_fix, MVE_VCVTu32f32a, MVE_VCVTu32f32m, MVE_VCVTu32f32n,... + SStream_concat0(O, ".u32.f32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 40: + // MVE_VLD20_16, MVE_VLD20_32, MVE_VLD20_8, MVE_VLD21_16, MVE_VLD21_32, M... + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 2, O); + return; + break; + case 41: + // MVE_VLD20_16_wb, MVE_VLD20_32_wb, MVE_VLD20_8_wb, MVE_VLD21_16_wb, MVE... + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 3, O); + SStream_concat0(O, "!"); + return; + break; + case 42: + // MVE_VLDRDU64_qi, MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq, MVE_VLDRDU64_rq... + SStream_concat0(O, ".u64\t"); + break; + case 43: + // MVE_VMOVimmi64, VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i... + SStream_concat0(O, ".i64\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 44: + // MVE_VMULLBp16, MVE_VMULLTp16 + SStream_concat0(O, ".p16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 45: + // MVE_VMULLBp8, MVE_VMULLTp8, VMULLp8, VMULpd, VMULpq + SStream_concat0(O, ".p8\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 46: + // MVE_VST20_16, MVE_VST20_32, MVE_VST20_8, MVE_VST21_16, MVE_VST21_32, M... + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 1, O); + return; + break; + case 47: + // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD + SStream_concat0(O, "!"); + return; + break; + case 48: + // VCVTBDH, VCVTTDH + SStream_concat0(O, ".f16.f64\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 49: + // VCVTBHD, VCVTTHD + SStream_concat0(O, ".f64.f16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 50: + // VCVTDS + SStream_concat0(O, ".f64.f32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 51: + // VCVTSD + SStream_concat0(O, ".f32.f64\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 52: + // VJCVT, VTOSIRD, VTOSIZD, VTOSLD + SStream_concat0(O, ".s32.f64\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 53: + // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq... + SStream_concat0(O, ".16\t{"); + break; + case 54: + // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq... + SStream_concat0(O, ".32\t{"); + break; + case 55: + // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U... + SStream_concat0(O, ".8\t{"); + break; + case 56: + // VLDR_FPCXTNS_off, VLDR_FPCXTNS_post, VLDR_FPCXTNS_pre, VMSR_FPCXTNS, V... + SStream_concat0(O, "\tfpcxtns, "); + break; + case 57: + // VLDR_FPCXTS_off, VLDR_FPCXTS_post, VLDR_FPCXTS_pre, VMSR_FPCXTS, VSTR_... + SStream_concat0(O, "\tfpcxts, "); + break; + case 58: + // VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_NZCVQC_post, VLDR_FPSCR_NZCVQC_pre, ... + SStream_concat0(O, "\tfpscr_nzcvqc, "); + break; + case 59: + // VLDR_FPSCR_off, VLDR_FPSCR_post, VLDR_FPSCR_pre, VMSR, VSTR_FPSCR_off,... + SStream_concat0(O, "\tfpscr, "); + break; + case 60: + // VLDR_P0_off, VLDR_P0_post, VLDR_P0_pre, VMSR_P0, VSTR_P0_off, VSTR_P0_... + SStream_concat0(O, "\tp0, "); + break; + case 61: + // VLDR_VPR_off, VLDR_VPR_post, VLDR_VPR_pre, VMSR_VPR, VSTR_VPR_off, VST... + SStream_concat0(O, "\tvpr, "); + break; + case 62: + // VMSR_FPEXC + SStream_concat0(O, "\tfpexc, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 63: + // VMSR_FPINST + SStream_concat0(O, "\tfpinst, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 64: + // VMSR_FPINST2 + SStream_concat0(O, "\tfpinst2, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 65: + // VMSR_FPSID + SStream_concat0(O, "\tfpsid, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 66: + // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V... + SStream_concat0(O, ".s64\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 67: + // VSHTOD + SStream_concat0(O, ".f64.s16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printFBits16 /* printFBits16 (+ ) */ (MI, 2, O); + return; + break; + case 68: + // VSHTOS + SStream_concat0(O, ".f32.s16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printFBits16 /* printFBits16 (+ ) */ (MI, 2, O); + return; + break; + case 69: + // VSITOD, VSLTOD + SStream_concat0(O, ".f64.s32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 70: + // VSITOH, VSLTOH + SStream_concat0(O, ".f16.s32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 71: + // VTOSHD + SStream_concat0(O, ".s16.f64\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printFBits16 /* printFBits16 (+ ) */ (MI, 2, O); + return; + break; + case 72: + // VTOSHS + SStream_concat0(O, ".s16.f32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printFBits16 /* printFBits16 (+ ) */ (MI, 2, O); + return; + break; + case 73: + // VTOSIRH, VTOSIZH, VTOSLH + SStream_concat0(O, ".s32.f16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 74: + // VTOUHD + SStream_concat0(O, ".u16.f64\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printFBits16 /* printFBits16 (+ ) */ (MI, 2, O); + return; + break; + case 75: + // VTOUHS + SStream_concat0(O, ".u16.f32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printFBits16 /* printFBits16 (+ ) */ (MI, 2, O); + return; + break; + case 76: + // VTOUIRD, VTOUIZD, VTOULD + SStream_concat0(O, ".u32.f64\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 77: + // VTOUIRH, VTOUIZH, VTOULH + SStream_concat0(O, ".u32.f16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 78: + // VUHTOD + SStream_concat0(O, ".f64.u16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printFBits16 /* printFBits16 (+ ) */ (MI, 2, O); + return; + break; + case 79: + // VUHTOS + SStream_concat0(O, ".f32.u16\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printFBits16 /* printFBits16 (+ ) */ (MI, 2, O); + return; + break; + case 80: + // VUITOD, VULTOD + SStream_concat0(O, ".f64.u32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 81: + // VUITOH, VULTOH + SStream_concat0(O, ".f16.u32\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 82: + // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADDspImm, t2ADR, t2ANDr... + SStream_concat0(O, ".w\t"); + break; + case 83: + // t2SRSDB, t2SRSIA + SStream_concat0(O, "\tsp, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 84: + // t2SRSDB_UPD, t2SRSIA_UPD + SStream_concat0(O, "\tsp!, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 85: + // t2SUBS_PC_LR + SStream_concat0(O, "\tpc, lr, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 86: + // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, "\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 87: + // tMOVi8, tMVN, tRSB + printPredicateOperand /* printPredicateOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + } + + // Fragment 2 encoded into 7 bits for 67 unique commands. + switch ((Bits >> 26) & 127) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 1: + // ITasm, t2IT + printMandatoryPredicateOperand /* printMandatoryPredicateOperand (+ ) */ ( + MI, 0, O); + return; + break; + case 2: + // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... + printVectorListThreeAllLanes /* printVectorListThreeAllLanes (+ ) */ (MI, 0, + O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + break; + case 3: + // VLD3DUPqAsm_16, VLD3DUPqAsm_32, VLD3DUPqAsm_8, VLD3DUPqWB_fixed_Asm_16... + printVectorListThreeSpacedAllLanes /* printVectorListThreeSpacedAllLanes (+ + ) */ + (MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + break; + case 4: + // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... + printVectorListThree /* printVectorListThree (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 5: + // VLD3qAsm_16, VLD3qAsm_32, VLD3qAsm_8, VLD3qWB_fixed_Asm_16, VLD3qWB_fi... + printVectorListThreeSpaced /* printVectorListThreeSpaced (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + break; + case 6: + // VLD4DUPdAsm_16, VLD4DUPdAsm_32, VLD4DUPdAsm_8, VLD4DUPdWB_fixed_Asm_16... + printVectorListFourAllLanes /* printVectorListFourAllLanes (+ ) */ (MI, 0, + O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + break; + case 7: + // VLD4DUPqAsm_16, VLD4DUPqAsm_32, VLD4DUPqAsm_8, VLD4DUPqWB_fixed_Asm_16... + printVectorListFourSpacedAllLanes /* printVectorListFourSpacedAllLanes (+ ) + */ + (MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + break; + case 8: + // VLD4dAsm_16, VLD4dAsm_32, VLD4dAsm_8, VLD4dWB_fixed_Asm_16, VLD4dWB_fi... + printVectorListFour /* printVectorListFour (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 9: + // VLD4qAsm_16, VLD4qAsm_32, VLD4qAsm_8, VLD4qWB_fixed_Asm_16, VLD4qWB_fi... + printVectorListFourSpaced /* printVectorListFourSpaced (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + break; + case 10: + // t2LDR_POST_imm, t2STR_POST_imm, VLDR_FPCXTNS_post, VLDR_FPCXTS_post, V... + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 1, O); + break; + case 11: + // t2LDR_PRE_imm, t2STR_PRE_imm + printT2AddrModeImm8Operand /* printT2AddrModeImm8Operand (+ ) */ ( + MI, 1, O, true); + SStream_concat0(O, "!"); + return; + break; + case 12: + // AESD, AESE, BF16_VCVTB, BF16_VCVTT, CDE_CX1, CDE_CX2, CDE_CX3, CDE_VCX... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 13: + // AESIMC, AESMC, BF16_VCVT, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, C... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 14: + // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, CD... + SStream_concat0(O, ", "); + break; + case 15: + // CDE_CX1A, CDE_CX1DA, CDE_CX2A, CDE_CX2DA, CDE_CX3A, CDE_CX3DA, CDE_VCX... + printPImmediate /* printPImmediate (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 16: + // CDE_CX1D, MVE_LCTP, MVE_LETP, MVE_VCVTf16s16n, MVE_VCVTf16u16n, MVE_VC... + return; + break; + case 17: + // CDE_VCX1A_fpdp, CDE_VCX1A_fpsp, CDE_VCX2A_fpdp, CDE_VCX2A_fpsp, CDE_VC... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 18: + // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OP... + printPImmediate /* printPImmediate (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 19: + // CDP2 + printCImmediate /* printCImmediate (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + case 20: + // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS + printCPSIFlag /* printCPSIFlag (+ ) */ (MI, 1, O); + break; + case 21: + // LDAEXD, LDREXD + printGPRPairOperand /* printGPRPairOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 1, O); + return; + break; + case 22: + // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET + printAddrMode5Operand /* printAddrMode5Operand (+ ) */ (MI, 2, O, + false); + return; + break; + case 23: + // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_... + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 2, O); + break; + case 24: + // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE + printAddrMode5Operand /* printAddrMode5Operand (+ ) */ (MI, 2, O, + true); + SStream_concat0(O, "!"); + return; + break; + case 25: + // MRRC, t2MRRC, t2MRRC2 + printPImmediate /* printPImmediate (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 4, O); + return; + break; + case 26: + // MSR, MSRi, t2MSR_AR, t2MSR_M + printMSRMaskOperand /* printMSRMaskOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 27: + // MSRbanked, t2MSRbanked + printBankedRegOperand /* printBankedRegOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 28: + // MVE_VCMPf16, MVE_VCMPf16r, MVE_VCMPf32, MVE_VCMPf32r, MVE_VCMPi16, MVE... + printMandatoryRestrictedPredicateOperand /* printMandatoryRestrictedPredicateOperand + (+ ) */ + (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 29: + // MVE_VMOVimmi64, VMOVv1i64, VMOVv2i64 + printVMOVModImmOperand /* printVMOVModImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 30: + // VCMPEZD, VCMPZD, tRSB + SStream_concat0(O, ", #0"); + return; + break; + case 31: + // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD... + printVectorListOneAllLanes /* printVectorListOneAllLanes (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 32: + // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD... + printVectorListTwoAllLanes /* printVectorListTwoAllLanes (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 33: + // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed... + printVectorListOne /* printVectorListOne (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 34: + // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed... + printVectorListTwo /* printVectorListTwo (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 35: + // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3... + printVectorListTwoSpacedAllLanes /* printVectorListTwoSpacedAllLanes (+ ) */ + (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 36: + // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed... + printVectorListTwoSpaced /* printVectorListTwoSpaced (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 37: + // VLDR_FPCXTNS_off, VLDR_FPCXTS_off, VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_o... + printT2AddrModeImm8s4Operand /* printT2AddrModeImm8s4Operand (+ ) */ + (MI, 0, O, false); + return; + break; + case 38: + // VLDR_FPCXTNS_pre, VLDR_FPCXTS_pre, VLDR_FPSCR_NZCVQC_pre, VLDR_FPSCR_p... + printT2AddrModeImm8s4Operand /* printT2AddrModeImm8s4Operand (+ ) */ ( + MI, 1, O, true); + SStream_concat0(O, "!"); + return; + break; + case 39: + // VLDR_P0_off, VSTR_P0_off + printT2AddrModeImm8s4Operand /* printT2AddrModeImm8s4Operand (+ ) */ + (MI, 1, O, false); + return; + break; + case 40: + // VLDR_P0_pre, VSTR_P0_pre + printT2AddrModeImm8s4Operand /* printT2AddrModeImm8s4Operand (+ ) */ ( + MI, 2, O, true); + SStream_concat0(O, "!"); + return; + break; + case 41: + // VSCCLRMD, VSCCLRMS, t2CLRM, tPOP, tPUSH + printRegisterList /* printRegisterList (+ ) */ (MI, 2, O); + return; + break; + case 42: + // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U... + printOperand /* printOperand (+ ) */ (MI, 4, O); + break; + case 43: + // VST1d16, VST1d32, VST1d64, VST1d8 + printVectorListOne /* printVectorListOne (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + case 44: + // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8 + printVectorListFour /* printVectorListFour (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + case 45: + // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,... + printVectorListFour /* printVectorListFour (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 46: + // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q... + printVectorListFour /* printVectorListFour (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 47: + // VST1d16T, VST1d32T, VST1d64T, VST1d8T + printVectorListThree /* printVectorListThree (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + case 48: + // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed + printVectorListThree /* printVectorListThree (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 49: + // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T... + printVectorListThree /* printVectorListThree (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 50: + // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed + printVectorListOne /* printVectorListOne (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 51: + // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r... + printVectorListOne /* printVectorListOne (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 52: + // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8 + printVectorListTwo /* printVectorListTwo (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + case 53: + // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST... + printVectorListTwo /* printVectorListTwo (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 54: + // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r... + printVectorListTwo /* printVectorListTwo (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 55: + // VST2b16, VST2b32, VST2b8 + printVectorListTwoSpaced /* printVectorListTwoSpaced (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + case 56: + // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed + printVectorListTwoSpaced /* printVectorListTwoSpaced (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 57: + // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register + printVectorListTwoSpaced /* printVectorListTwoSpaced (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 58: + // t2DMB, t2DSB + printMemBOption /* printMemBOption (+ ) */ (MI, 0, O); + return; + break; + case 59: + // t2ISB + printInstSyncBOption /* printInstSyncBOption (+ ) */ (MI, 0, O); + return; + break; + case 60: + // t2PLDWi12, t2PLDi12, t2PLIi12 + printAddrModeImm12Operand /* printAddrModeImm12Operand (+ ) */ ( + MI, 0, O, false); + return; + break; + case 61: + // t2PLDWi8, t2PLDi8, t2PLIi8 + printT2AddrModeImm8Operand /* printT2AddrModeImm8Operand (+ ) */ ( + MI, 0, O, false); + return; + break; + case 62: + // t2PLDWs, t2PLDs, t2PLIs + printT2AddrModeSoRegOperand /* printT2AddrModeSoRegOperand (+ ) */ (MI, 0, + O); + return; + break; + case 63: + // t2PLDpci, t2PLIpci + printThumbLdrLabelOperand /* printThumbLdrLabelOperand (+ ) */ (MI, 0, O); + return; + break; + case 64: + // t2TBB + printAddrModeTBB /* printAddrModeTBB (+ ) */ (MI, 0, O); + return; + break; + case 65: + // t2TBH + printAddrModeTBH /* printAddrModeTBH (+ ) */ (MI, 0, O); + return; + break; + case 66: + // t2TSB + printTraceSyncBOption /* printTraceSyncBOption (+ ) */ (MI, 0, O); + return; + break; + } + + // Fragment 3 encoded into 6 bits for 38 unique commands. + switch ((Bits >> 33) & 63) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR... + SStream_concat0(O, ", "); + break; + case 1: + // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPqAsm_16, VLD3DUP... + return; + break; + case 2: + // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm... + SStream_concat0(O, "!"); + return; + break; + case 3: + // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + break; + case 4: + // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, CD... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 5: + // CDE_CX1A, CDE_CX2A, CDE_CX3A, CDE_VCX1A_vec, CDE_VCX1_vec, CDE_VCX2A_v... + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 6: + // CDE_CX1DA, CDE_CX2DA, CDE_CX3DA + printGPRPairOperand /* printGPRPairOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 7: + // CDP, MCR, MCRR, MSR, VABSD, VADDD, VCMPD, VCMPED, VDIVD, VMOVD, VMULD,... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 8: + // FCONSTD + printFPImmOperand /* printFPImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 9: + // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... + SStream_concat0(O, "!, "); + printRegisterList /* printRegisterList (+ ) */ (MI, 4, O); + break; + case 10: + // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OPTION,... + printCImmediate /* printCImmediate (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 11: + // MRC, MVE_VCVTf16s16_fix, MVE_VCVTf16u16_fix, MVE_VCVTf32s32_fix, MVE_V... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 12: + // MRS, t2MRS_AR + SStream_concat0(O, ", apsr"); + return; + break; + case 13: + // MRSsys, t2MRSsys_AR + SStream_concat0(O, ", spsr"); + return; + break; + case 14: + // MSRi + printModImmOperand /* printModImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 15: + // MVE_VMOV_q_rr + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 5, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 16: + // MVE_VMOV_to_lane_16, MVE_VMOV_to_lane_32, MVE_VMOV_to_lane_8, VSETLNi1... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 17: + // VCMPEZH, VCMPEZS, VCMPZH, VCMPZS + SStream_concat0(O, ", #0"); + return; + break; + case 18: + // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP... + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 2, O); + break; + case 19: + // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... + SStream_concat0(O, "["); + break; + case 20: + // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... + SStream_concat0(O, "[], "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "[], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 21: + // VLDR_FPCXTNS_post, VLDR_FPCXTS_post, VLDR_FPSCR_NZCVQC_post, VLDR_FPSC... + printT2AddrModeImm8s4OffsetOperand /* printT2AddrModeImm8s4OffsetOperand (+ + ) */ + (MI, 2, O); + return; + break; + case 22: + // VLDR_P0_post, VSTR_P0_post + printT2AddrModeImm8s4OffsetOperand /* printT2AddrModeImm8s4OffsetOperand (+ + ) */ + (MI, 3, O); + return; + break; + case 23: + // VMRS + SStream_concat0(O, ", fpscr"); + return; + break; + case 24: + // VMRS_FPCXTNS + SStream_concat0(O, ", fpcxtns"); + return; + break; + case 25: + // VMRS_FPCXTS + SStream_concat0(O, ", fpcxts"); + return; + break; + case 26: + // VMRS_FPEXC + SStream_concat0(O, ", fpexc"); + return; + break; + case 27: + // VMRS_FPINST + SStream_concat0(O, ", fpinst"); + return; + break; + case 28: + // VMRS_FPINST2 + SStream_concat0(O, ", fpinst2"); + return; + break; + case 29: + // VMRS_FPSCR_NZCVQC + SStream_concat0(O, ", fpscr_nzcvqc"); + return; + break; + case 30: + // VMRS_FPSID + SStream_concat0(O, ", fpsid"); + return; + break; + case 31: + // VMRS_MVFR0 + SStream_concat0(O, ", mvfr0"); + return; + break; + case 32: + // VMRS_MVFR1 + SStream_concat0(O, ", mvfr1"); + return; + break; + case 33: + // VMRS_MVFR2 + SStream_concat0(O, ", mvfr2"); + return; + break; + case 34: + // VMRS_P0 + SStream_concat0(O, ", p0"); + return; + break; + case 35: + // VMRS_VPR + SStream_concat0(O, ", vpr"); + return; + break; + case 36: + // VSHTOH, VTOSHH, VTOUHH, VUHTOH + printFBits16 /* printFBits16 (+ ) */ (MI, 2, O); + return; + break; + case 37: + // VSLTOD, VSLTOH, VSLTOS, VTOSLD, VTOSLH, VTOSLS, VTOULD, VTOULH, VTOULS... + printFBits32 /* printFBits32 (+ ) */ (MI, 2, O); + return; + break; + } + + // Fragment 4 encoded into 7 bits for 77 unique commands. + switch ((Bits >> 39) & 127) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ASRi, ASRr, LDRConstPool, LSLi, LSLr, LSRi, LSRr, RORi, RORr, RRXi, t2... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 1: + // LDRBT_POST, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRBT_POST, STRT_P... + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 1, O); + return; + break; + case 2: + // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 2, O); + break; + case 3: + // VLD3DUPdWB_register_Asm_16, VLD3DUPdWB_register_Asm_32, VLD3DUPdWB_reg... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 4: + // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD4dAsm_16, VLD4dAsm_32, VLD4dA... + return; + break; + case 5: + // VLD3dWB_fixed_Asm_16, VLD3dWB_fixed_Asm_32, VLD3dWB_fixed_Asm_8, VLD4d... + SStream_concat0(O, "!"); + return; + break; + case 6: + // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... + SStream_concat0(O, ", "); + break; + case 7: + // t2LDR_POST_imm, t2STR_POST_imm + printT2AddrModeImm8OffsetOperand /* printT2AddrModeImm8OffsetOperand (+ ) */ + (MI, 2, O); + return; + break; + case 8: + // t2MOVSsi, t2MOVsi, t2CMNzrs, t2CMPrs, t2MVNs, t2TEQrs, t2TSTrs + printT2SOOperand /* printT2SOOperand (+ ) */ (MI, 1, O); + return; + break; + case 9: + // t2MOVSsr, t2MOVsr, CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr + printSORegRegOperand /* printSORegRegOperand (+ ) */ (MI, 1, O); + return; + break; + case 10: + // ADR, t2ADR + printAdrLabelOperand /* printAdrLabelOperand<0> (+ ) */ (MI, 1, O, 0); + return; + break; + case 11: + // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, VBF16MALBQI, VBF16MALTQI, VSDOTDI, V... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + return; + break; + case 12: + // BFC, t2BFC + printBitfieldInvMaskImmOperand /* printBitfieldInvMaskImmOperand (+ ) */ ( + MI, 2, O); + return; + break; + case 13: + // BFI, CDE_VCX1_vec, CDE_VCX2_vec, CDE_VCX3_vec, CPS3p, CRC32B, CRC32CB,... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 14: + // CDE_VCX2A_fpdp, CDE_VCX2A_fpsp, CDE_VCX3A_fpdp, CDE_VCX3A_fpsp + printOperand /* printOperand (+ ) */ (MI, 4, O); + break; + case 15: + // CMNri, CMPri, MOVi, MVNi, TEQri, TSTri + printModImmOperand /* printModImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 16: + // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi + printSORegImmOperand /* printSORegImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 17: + // FCONSTH, FCONSTS, MVE_VMOVimmf32, VMOVv2f32, VMOVv4f32 + printFPImmOperand /* printFPImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 18: + // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM... + printRegisterList /* printRegisterList (+ ) */ (MI, 3, O); + break; + case 19: + // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION + printCoprocOptionImm /* printCoprocOptionImm (+ ) */ (MI, 3, O); + return; + break; + case 20: + // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST + printPostIdxImm8s4Operand /* printPostIdxImm8s4Operand (+ ) */ (MI, 3, O); + return; + break; + case 21: + // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD... + printAddrMode5Operand /* printAddrMode5Operand (+ ) */ (MI, 2, O, + false); + return; + break; + case 22: + // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO... + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 2, O); + break; + case 23: + // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_... + printAddrMode5Operand /* printAddrMode5Operand (+ ) */ (MI, 2, O, + true); + SStream_concat0(O, "!"); + return; + break; + case 24: + // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM + printAddrModeImm12Operand /* printAddrModeImm12Operand (+ ) */ ( + MI, 2, O, true); + SStream_concat0(O, "!"); + return; + break; + case 25: + // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG + printAddrMode2Operand /* printAddrMode2Operand (+ ) */ (MI, 2, O); + SStream_concat0(O, "!"); + return; + break; + case 26: + // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB... + printAddrModeImm12Operand /* printAddrModeImm12Operand (+ ) */ ( + MI, 1, O, false); + return; + break; + case 27: + // LDRBrs, LDRrs, STRBrs, STRrs + printAddrMode2Operand /* printAddrMode2Operand (+ ) */ (MI, 1, O); + return; + break; + case 28: + // LDRH, LDRSB, LDRSH, STRH + printAddrMode3Operand /* printAddrMode3Operand (+ ) */ (MI, 1, O, + false); + return; + break; + case 29: + // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE + printAddrMode3Operand /* printAddrMode3Operand (+ ) */ (MI, 2, O, + true); + SStream_concat0(O, "!"); + return; + break; + case 30: + // MCR2, MRC2 + printCImmediate /* printCImmediate (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + case 31: + // MRSbanked, t2MRSbanked + printBankedRegOperand /* printBankedRegOperand (+ ) */ (MI, 1, O); + return; + break; + case 32: + // MVE_VBICimmi16, MVE_VBICimmi32, MVE_VORRimmi16, MVE_VORRimmi32 + printVMOVModImmOperand /* printVMOVModImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 33: + // MVE_VLDRBS16, MVE_VLDRBS32, MVE_VLDRBU16, MVE_VLDRBU32, MVE_VLDRBU8, M... + printT2AddrModeImm8Operand /* printT2AddrModeImm8Operand (+ ) */ ( + MI, 1, O, false); + return; + break; + case 34: + // MVE_VLDRBS16_pre, MVE_VLDRBS32_pre, MVE_VLDRBU16_pre, MVE_VLDRBU32_pre... + printT2AddrModeImm8Operand /* printT2AddrModeImm8Operand (+ ) */ ( + MI, 2, O, false); + SStream_concat0(O, "!"); + return; + break; + case 35: + // MVE_VLDRBS16_rq, MVE_VLDRBS32_rq, MVE_VLDRBU16_rq, MVE_VLDRBU32_rq, MV... + printMveAddrModeRQOperand /* printMveAddrModeRQOperand<0> (+ ) */ (MI, 1, O, + 0); + return; + break; + case 36: + // MVE_VLDRBU8_pre, MVE_VLDRHU16_pre, MVE_VLDRWU32_pre, MVE_VSTRBU8_pre, ... + printT2AddrModeImm8Operand /* printT2AddrModeImm8Operand (+ ) */ ( + MI, 2, O, true); + SStream_concat0(O, "!"); + return; + break; + case 37: + // MVE_VLDRDU64_rq, MVE_VSTRD64_rq + printMveAddrModeRQOperand /* printMveAddrModeRQOperand<3> (+ ) */ (MI, 1, O, + 3); + return; + break; + case 38: + // MVE_VLDRHS32_rq, MVE_VLDRHU16_rq, MVE_VLDRHU32_rq, MVE_VSTRH16_rq, MVE... + printMveAddrModeRQOperand /* printMveAddrModeRQOperand<1> (+ ) */ (MI, 1, O, + 1); + return; + break; + case 39: + // MVE_VLDRWU32_rq, MVE_VSTRW32_rq + printMveAddrModeRQOperand /* printMveAddrModeRQOperand<2> (+ ) */ (MI, 1, O, + 2); + return; + break; + case 40: + // MVE_VMOVimmi16, MVE_VMOVimmi32, MVE_VMOVimmi8, MVE_VMVNimmi16, MVE_VMV... + printVMOVModImmOperand /* printVMOVModImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 41: + // SSAT, SSAT16, t2SSAT, t2SSAT16 + printImmPlusOneOperand /* printImmPlusOneOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 42: + // STLEXD, STREXD + printGPRPairOperand /* printGPRPairOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 2, O); + return; + break; + case 43: + // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN... + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 4, O); + break; + case 44: + // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 6, O); + break; + case 45: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 8, O); + SStream_concat0(O, "], "); + break; + case 46: + // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... + SStream_concat0(O, "[]}, "); + break; + case 47: + // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 10, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 10, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 10, O); + break; + case 48: + // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD... + SStream_concat0(O, "[], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "[]}, "); + break; + case 49: + // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 12, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 12, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 12, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 12, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 5, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 7, + O); + return; + break; + case 50: + // VLDRD, VLDRS, VSTRD, VSTRS + printAddrMode5Operand /* printAddrMode5Operand (+ ) */ (MI, 1, O, + false); + return; + break; + case 51: + // VLDRH, VSTRH + printAddrMode5FP16Operand /* printAddrMode5FP16Operand (+ ) */ ( + MI, 1, O, false); + return; + break; + case 52: + // VST1LNd16, VST1LNd32, VST1LNd8 + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 3, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + case 53: + // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3... + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 5, O); + break; + case 54: + // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U... + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 7, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 7, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 6, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 7, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 3, + O); + return; + break; + case 55: + // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... + printOperand /* printOperand (+ ) */ (MI, 5, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 6, O); + break; + case 56: + // VTBL1 + printVectorListOne /* printVectorListOne (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 57: + // VTBL2 + printVectorListTwo /* printVectorListTwo (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 58: + // VTBL3 + printVectorListThree /* printVectorListThree (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 59: + // VTBL4 + printVectorListFour /* printVectorListFour (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 60: + // VTBX1 + printVectorListOne /* printVectorListOne (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 61: + // VTBX2 + printVectorListTwo /* printVectorListTwo (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 62: + // VTBX3 + printVectorListThree /* printVectorListThree (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 63: + // VTBX4 + printVectorListFour /* printVectorListFour (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 64: + // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ... + SStream_concat0(O, " ^"); + return; + break; + case 65: + // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci + printThumbLdrLabelOperand /* printThumbLdrLabelOperand (+ ) */ (MI, 1, O); + return; + break; + case 66: + // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs + printT2AddrModeSoRegOperand /* printT2AddrModeSoRegOperand (+ ) */ (MI, 1, + O); + return; + break; + case 67: + // t2LDREX + printT2AddrModeImm0_1020s4Operand /* printT2AddrModeImm0_1020s4Operand (+ ) + */ + (MI, 1, O); + return; + break; + case 68: + // t2MRS_M + printMSRMaskOperand /* printMSRMaskOperand (+ ) */ (MI, 1, O); + return; + break; + case 69: + // tADDspi, tSUBspi + printThumbS4ImmOperand /* printThumbS4ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 70: + // tADR + printAdrLabelOperand /* printAdrLabelOperand<2> (+ ) */ (MI, 1, O, 2); + return; + break; + case 71: + // tASRri, tLSRri + printThumbSRImm /* printThumbSRImm (+ ) */ (MI, 3, O); + return; + break; + case 72: + // tLDRBi, tSTRBi + printThumbAddrModeImm5S1Operand /* printThumbAddrModeImm5S1Operand (+ ) */ ( + MI, 1, O); + return; + break; + case 73: + // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr + printThumbAddrModeRROperand /* printThumbAddrModeRROperand (+ ) */ (MI, 1, + O); + return; + break; + case 74: + // tLDRHi, tSTRHi + printThumbAddrModeImm5S2Operand /* printThumbAddrModeImm5S2Operand (+ ) */ ( + MI, 1, O); + return; + break; + case 75: + // tLDRi, tSTRi + printThumbAddrModeImm5S4Operand /* printThumbAddrModeImm5S4Operand (+ ) */ ( + MI, 1, O); + return; + break; + case 76: + // tLDRspi, tSTRspi + printThumbAddrModeSPOperand /* printThumbAddrModeSPOperand (+ ) */ (MI, 1, + O); + return; + break; + } + + // Fragment 5 encoded into 5 bits for 27 unique commands. + switch ((Bits >> 46) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... + SStream_concat0(O, ", "); + break; + case 1: + // LDRConstPool, RRXi, VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD2LN... + return; + break; + case 2: + // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,... + SStream_concat0(O, "!"); + return; + break; + case 3: + // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 4: + // CDE_CX2DA, CDE_CX3D, CDE_CX3DA, VLD1DUPd16wb_register, VLD1DUPd32wb_re... + printOperand /* printOperand (+ ) */ (MI, 4, O); + break; + case 5: + // CDP, t2CDP, t2CDP2 + printCImmediate /* printCImmediate (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + case 6: + // MCR, MCRR, VADDD, VDIVD, VMULD, VNMULD, VSUBD, t2MCR, t2MCR2, t2MCRR, ... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 7: + // MRC, t2MRC, t2MRC2 + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + case 8: + // MVE_VLDRBS16_post, MVE_VLDRBS32_post, MVE_VLDRBU16_post, MVE_VLDRBU32_... + printT2AddrModeImm8OffsetOperand /* printT2AddrModeImm8OffsetOperand (+ ) */ + (MI, 3, O); + return; + break; + case 9: + // MVE_VMOV_from_lane_32, MVE_VMOV_from_lane_s16, MVE_VMOV_from_lane_s8, ... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 2, O); + return; + break; + case 10: + // MVE_VSHLL_lws16bh, MVE_VSHLL_lws16th, MVE_VSHLL_lwu16bh, MVE_VSHLL_lwu... + SStream_concat0(O, ", #16"); + return; + break; + case 11: + // MVE_VSHLL_lws8bh, MVE_VSHLL_lws8th, MVE_VSHLL_lwu8bh, MVE_VSHLL_lwu8th + SStream_concat0(O, ", #8"); + return; + break; + case 12: + // SSAT, t2SSAT + printShiftImmOperand /* printShiftImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 13: + // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX... + printRotImmOperand /* printRotImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 14: + // VCEQzv16i8, VCEQzv2f32, VCEQzv2i32, VCEQzv4f16, VCEQzv4f32, VCEQzv4i16... + SStream_concat0(O, ", #0"); + return; + break; + case 15: + // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printComplexRotationOp /* printComplexRotationOp<90, 0> (+ ) */ (MI, 5, O, + 90, 0); + return; + break; + case 16: + // VFMALDI, VFMALQI, VFMSLDI, VFMSLQI + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + return; + break; + case 17: + // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... + SStream_concat0(O, "]}, "); + break; + case 18: + // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L... + SStream_concat0(O, "], "); + break; + case 19: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 8, O); + break; + case 20: + // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8 + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 3, O); + return; + break; + case 21: + // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 4, O); + break; + case 22: + // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 5, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 7, + O); + return; + break; + case 23: + // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... + SStream_concat0(O, "}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 3, + O); + return; + break; + case 24: + // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U... + printOperand /* printOperand (+ ) */ (MI, 5, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 8, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 6, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 8, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 7, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 8, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 3, + O); + return; + break; + case 25: + // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ... + SStream_concat0(O, " ^"); + return; + break; + case 26: + // t2MOVsra_flag, t2MOVsrl_flag + SStream_concat0(O, ", #1"); + return; + break; + } + + // Fragment 6 encoded into 6 bits for 38 unique commands. + switch ((Bits >> 51) & 63) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCrr, ADDrr, ANDrr, B... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 1: + // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... + printOperand /* printOperand (+ ) */ (MI, 4, O); + break; + case 2: + // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri + printModImmOperand /* printModImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 3: + // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi... + printSORegImmOperand /* printSORegImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 4: + // BFI, t2BFI + printBitfieldInvMaskImmOperand /* printBitfieldInvMaskImmOperand (+ ) */ ( + MI, 3, O); + return; + break; + case 5: + // CDE_CX2DA, CDE_CX3D, VADDD, VDIVD, VLD1DUPd16wb_register, VLD1DUPd32wb... + return; + break; + case 6: + // CDE_CX3DA, MCR, MCRR, t2MCR, t2MCR2, t2MCRR, t2MCRR2 + SStream_concat0(O, ", "); + break; + case 7: + // CDE_VCX2_vec, CDE_VCX3_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, M... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 8: + // CDE_VCX3A_fpdp, CDE_VCX3A_fpsp, VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8... + printOperand /* printOperand (+ ) */ (MI, 5, O); + break; + case 9: + // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD... + printCoprocOptionImm /* printCoprocOptionImm (+ ) */ (MI, 3, O); + return; + break; + case 10: + // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t... + printPostIdxImm8s4Operand /* printPostIdxImm8s4Operand (+ ) */ (MI, 3, O); + return; + break; + case 11: + // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS... + printAddrMode2OffsetOperand /* printAddrMode2OffsetOperand (+ ) */ (MI, 3, + O); + return; + break; + case 12: + // LDRD, STRD + printAddrMode3Operand /* printAddrMode3Operand (+ ) */ (MI, 2, O, + false); + return; + break; + case 13: + // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 3, O); + break; + case 14: + // LDRD_PRE, STRD_PRE + printAddrMode3Operand /* printAddrMode3Operand (+ ) */ (MI, 3, O, + true); + SStream_concat0(O, "!"); + return; + break; + case 15: + // LDRHTi, LDRSBTi, LDRSHTi, STRHTi + printPostIdxImm8Operand /* printPostIdxImm8Operand (+ ) */ (MI, 3, O); + return; + break; + case 16: + // LDRHTr, LDRSBTr, LDRSHTr, STRHTr + printPostIdxRegOperand /* printPostIdxRegOperand (+ ) */ (MI, 3, O); + return; + break; + case 17: + // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST + printAddrMode3OffsetOperand /* printAddrMode3OffsetOperand (+ ) */ (MI, 3, + O); + return; + break; + case 18: + // MCRR2 + printCImmediate /* printCImmediate (+ ) */ (MI, 4, O); + return; + break; + case 19: + // MVE_SQRSHRL, MVE_UQRSHLL + printMveSaturateOp /* printMveSaturateOp (+ ) */ (MI, 5, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + return; + break; + case 20: + // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L... + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 2, O); + return; + break; + case 21: + // VCADDv2f32, VCADDv4f16, VCADDv4f32, VCADDv8f16 + printComplexRotationOp /* printComplexRotationOp<180, 90> (+ ) */ (MI, 3, O, + 180, 90); + return; + break; + case 22: + // VCMLAv2f32, VCMLAv4f16, VCMLAv4f32, VCMLAv8f16 + printComplexRotationOp /* printComplexRotationOp<90, 0> (+ ) */ (MI, 4, O, + 90, 0); + return; + break; + case 23: + // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8... + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + break; + case 24: + // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 2, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 4, + O); + return; + break; + case 25: + // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32 + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 6, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 2, O); + return; + break; + case 26: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 3, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 5, + O); + return; + break; + case 27: + // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 6, + O); + return; + break; + case 28: + // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32 + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 8, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 3, O); + return; + break; + case 29: + // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 4, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 6, + O); + return; + break; + case 30: + // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8... + printOperand /* printOperand (+ ) */ (MI, 7, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 3, + O); + return; + break; + case 31: + // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs... + printT2SOOperand /* printT2SOOperand (+ ) */ (MI, 2, O); + return; + break; + case 32: + // t2ASRri, t2LSRri + printThumbSRImm /* printThumbSRImm (+ ) */ (MI, 2, O); + return; + break; + case 33: + // t2BFic, t2CSEL, t2CSINC, t2CSINV, t2CSNEG + printMandatoryPredicateOperand /* printMandatoryPredicateOperand (+ ) */ ( + MI, 3, O); + return; + break; + case 34: + // t2LDRD_PRE, t2STRD_PRE + printT2AddrModeImm8s4Operand /* printT2AddrModeImm8s4Operand (+ ) */ ( + MI, 3, O, true); + SStream_concat0(O, "!"); + return; + break; + case 35: + // t2LDRDi8, t2STRDi8 + printT2AddrModeImm8s4Operand /* printT2AddrModeImm8s4Operand (+ ) */ + (MI, 2, O, false); + return; + break; + case 36: + // t2STREX + printT2AddrModeImm0_1020s4Operand /* printT2AddrModeImm0_1020s4Operand (+ ) + */ + (MI, 2, O); + return; + break; + case 37: + // tADDrSPi + printThumbS4ImmOperand /* printThumbS4ImmOperand (+ ) */ (MI, 2, O); + return; + break; + } + + // Fragment 7 encoded into 4 bits for 15 unique commands. + switch ((Bits >> 57) & 15) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... + return; + break; + case 1: + // CDE_CX3A, CDE_VCX3A_vec, CDE_VCX3_vec, LDRD_POST, MLA, MLS, MVE_VCADDf... + SStream_concat0(O, ", "); + break; + case 2: + // CDE_CX3DA + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + case 3: + // MCR, t2MCR, t2MCR2 + printCImmediate /* printCImmediate (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + case 4: + // MCRR, t2MCRR, t2MCRR2 + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate /* printCImmediate (+ ) */ (MI, 4, O); + return; + break; + case 5: + // MVE_VMOV_rr_q, VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 3, O); + break; + case 6: + // PKHBT, t2PKHBT + printPKHLSLShiftImm /* printPKHLSLShiftImm (+ ) */ (MI, 3, O); + return; + break; + case 7: + // PKHTB, t2PKHTB + printPKHASRShiftImm /* printPKHASRShiftImm (+ ) */ (MI, 3, O); + return; + break; + case 8: + // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX... + printRotImmOperand /* printRotImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 9: + // USAT, t2USAT + printShiftImmOperand /* printShiftImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 10: + // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1... + SStream_concat0(O, "}, "); + break; + case 11: + // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L... + SStream_concat0(O, "["); + break; + case 12: + // VMLALslsv2i32, VMLALslsv4i16, VMLALsluv2i32, VMLALsluv4i16, VMLAslfd, ... + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + return; + break; + case 13: + // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 3, + O); + return; + break; + case 14: + // t2LDRD_POST, t2STRD_POST + printT2AddrModeImm8s4OffsetOperand /* printT2AddrModeImm8s4OffsetOperand (+ + ) */ + (MI, 4, O); + return; + break; + } + + switch (MCInst_getOpcode(MI)) { + default: + llvm_unreachable("Unexpected opcode."); + case ARM_CDE_CX3A: + case ARM_CDE_VCX3A_vec: + case ARM_CDE_VCX3_vec: + case ARM_LDRD_POST: + case ARM_MLA: + case ARM_MLS: + case ARM_MVE_VCADDf16: + case ARM_MVE_VCADDf32: + case ARM_MVE_VCADDi16: + case ARM_MVE_VCADDi32: + case ARM_MVE_VCADDi8: + case ARM_MVE_VCMLAf16: + case ARM_MVE_VCMLAf32: + case ARM_MVE_VCMULf16: + case ARM_MVE_VCMULf32: + case ARM_MVE_VDWDUPu16: + case ARM_MVE_VDWDUPu32: + case ARM_MVE_VDWDUPu8: + case ARM_MVE_VHCADDs16: + case ARM_MVE_VHCADDs32: + case ARM_MVE_VHCADDs8: + case ARM_MVE_VIWDUPu16: + case ARM_MVE_VIWDUPu32: + case ARM_MVE_VIWDUPu8: + case ARM_MVE_VMLALDAVas16: + case ARM_MVE_VMLALDAVas32: + case ARM_MVE_VMLALDAVau16: + case ARM_MVE_VMLALDAVau32: + case ARM_MVE_VMLALDAVaxs16: + case ARM_MVE_VMLALDAVaxs32: + case ARM_MVE_VMLALDAVs16: + case ARM_MVE_VMLALDAVs32: + case ARM_MVE_VMLALDAVu16: + case ARM_MVE_VMLALDAVu32: + case ARM_MVE_VMLALDAVxs16: + case ARM_MVE_VMLALDAVxs32: + case ARM_MVE_VMLSLDAVas16: + case ARM_MVE_VMLSLDAVas32: + case ARM_MVE_VMLSLDAVaxs16: + case ARM_MVE_VMLSLDAVaxs32: + case ARM_MVE_VMLSLDAVs16: + case ARM_MVE_VMLSLDAVs32: + case ARM_MVE_VMLSLDAVxs16: + case ARM_MVE_VMLSLDAVxs32: + case ARM_MVE_VRMLALDAVHas32: + case ARM_MVE_VRMLALDAVHau32: + case ARM_MVE_VRMLALDAVHaxs32: + case ARM_MVE_VRMLALDAVHs32: + case ARM_MVE_VRMLALDAVHu32: + case ARM_MVE_VRMLALDAVHxs32: + case ARM_MVE_VRMLSLDAVHas32: + case ARM_MVE_VRMLSLDAVHaxs32: + case ARM_MVE_VRMLSLDAVHs32: + case ARM_MVE_VRMLSLDAVHxs32: + case ARM_SBFX: + case ARM_SMLABB: + case ARM_SMLABT: + case ARM_SMLAD: + case ARM_SMLADX: + case ARM_SMLALBB: + case ARM_SMLALBT: + case ARM_SMLALD: + case ARM_SMLALDX: + case ARM_SMLALTB: + case ARM_SMLALTT: + case ARM_SMLATB: + case ARM_SMLATT: + case ARM_SMLAWB: + case ARM_SMLAWT: + case ARM_SMLSD: + case ARM_SMLSDX: + case ARM_SMLSLD: + case ARM_SMLSLDX: + case ARM_SMMLA: + case ARM_SMMLAR: + case ARM_SMMLS: + case ARM_SMMLSR: + case ARM_SMULL: + case ARM_STRD_POST: + case ARM_UBFX: + case ARM_UMAAL: + case ARM_UMULL: + case ARM_USADA8: + case ARM_VEXTd16: + case ARM_VEXTd32: + case ARM_VEXTd8: + case ARM_VEXTq16: + case ARM_VEXTq32: + case ARM_VEXTq64: + case ARM_VEXTq8: + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8: + case ARM_VMOVRRS: + case ARM_VMOVSRR: + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8: + case ARM_t2MLA: + case ARM_t2MLS: + case ARM_t2SBFX: + case ARM_t2SMLABB: + case ARM_t2SMLABT: + case ARM_t2SMLAD: + case ARM_t2SMLADX: + case ARM_t2SMLAL: + case ARM_t2SMLALBB: + case ARM_t2SMLALBT: + case ARM_t2SMLALD: + case ARM_t2SMLALDX: + case ARM_t2SMLALTB: + case ARM_t2SMLALTT: + case ARM_t2SMLATB: + case ARM_t2SMLATT: + case ARM_t2SMLAWB: + case ARM_t2SMLAWT: + case ARM_t2SMLSD: + case ARM_t2SMLSDX: + case ARM_t2SMLSLD: + case ARM_t2SMLSLDX: + case ARM_t2SMMLA: + case ARM_t2SMMLAR: + case ARM_t2SMMLS: + case ARM_t2SMMLSR: + case ARM_t2SMULL: + case ARM_t2STLEXD: + case ARM_t2STREXD: + case ARM_t2UBFX: + case ARM_t2UMAAL: + case ARM_t2UMLAL: + case ARM_t2UMULL: + case ARM_t2USADA8: + switch (MCInst_getOpcode(MI)) { + default: + llvm_unreachable("Unexpected opcode."); + case ARM_CDE_CX3A: + case ARM_CDE_VCX3A_vec: + case ARM_MVE_VMLALDAVas16: + case ARM_MVE_VMLALDAVas32: + case ARM_MVE_VMLALDAVau16: + case ARM_MVE_VMLALDAVau32: + case ARM_MVE_VMLALDAVaxs16: + case ARM_MVE_VMLALDAVaxs32: + case ARM_MVE_VMLSLDAVas16: + case ARM_MVE_VMLSLDAVas32: + case ARM_MVE_VMLSLDAVaxs16: + case ARM_MVE_VMLSLDAVaxs32: + case ARM_MVE_VRMLALDAVHas32: + case ARM_MVE_VRMLALDAVHau32: + case ARM_MVE_VRMLALDAVHaxs32: + case ARM_MVE_VRMLSLDAVHas32: + case ARM_MVE_VRMLSLDAVHaxs32: + printOperand /* printOperand (+ ) */ (MI, 5, O); + break; + case ARM_CDE_VCX3_vec: + case ARM_MVE_VDWDUPu16: + case ARM_MVE_VDWDUPu32: + case ARM_MVE_VDWDUPu8: + case ARM_MVE_VIWDUPu16: + case ARM_MVE_VIWDUPu32: + case ARM_MVE_VIWDUPu8: + printOperand /* printOperand (+ ) */ (MI, 4, O); + break; + case ARM_LDRD_POST: + case ARM_STRD_POST: + printAddrMode3OffsetOperand /* printAddrMode3OffsetOperand (+ ) */ (MI, 4, + O); + break; + case ARM_MLA: + case ARM_MLS: + case ARM_MVE_VMLALDAVs16: + case ARM_MVE_VMLALDAVs32: + case ARM_MVE_VMLALDAVu16: + case ARM_MVE_VMLALDAVu32: + case ARM_MVE_VMLALDAVxs16: + case ARM_MVE_VMLALDAVxs32: + case ARM_MVE_VMLSLDAVs16: + case ARM_MVE_VMLSLDAVs32: + case ARM_MVE_VMLSLDAVxs16: + case ARM_MVE_VMLSLDAVxs32: + case ARM_MVE_VRMLALDAVHs32: + case ARM_MVE_VRMLALDAVHu32: + case ARM_MVE_VRMLALDAVHxs32: + case ARM_MVE_VRMLSLDAVHs32: + case ARM_MVE_VRMLSLDAVHxs32: + case ARM_SMLABB: + case ARM_SMLABT: + case ARM_SMLAD: + case ARM_SMLADX: + case ARM_SMLALBB: + case ARM_SMLALBT: + case ARM_SMLALD: + case ARM_SMLALDX: + case ARM_SMLALTB: + case ARM_SMLALTT: + case ARM_SMLATB: + case ARM_SMLATT: + case ARM_SMLAWB: + case ARM_SMLAWT: + case ARM_SMLSD: + case ARM_SMLSDX: + case ARM_SMLSLD: + case ARM_SMLSLDX: + case ARM_SMMLA: + case ARM_SMMLAR: + case ARM_SMMLS: + case ARM_SMMLSR: + case ARM_SMULL: + case ARM_UMAAL: + case ARM_UMULL: + case ARM_USADA8: + case ARM_VEXTd16: + case ARM_VEXTd32: + case ARM_VEXTd8: + case ARM_VEXTq16: + case ARM_VEXTq32: + case ARM_VEXTq64: + case ARM_VEXTq8: + case ARM_VMOVRRS: + case ARM_VMOVSRR: + case ARM_t2MLA: + case ARM_t2MLS: + case ARM_t2SMLABB: + case ARM_t2SMLABT: + case ARM_t2SMLAD: + case ARM_t2SMLADX: + case ARM_t2SMLAL: + case ARM_t2SMLALBB: + case ARM_t2SMLALBT: + case ARM_t2SMLALD: + case ARM_t2SMLALDX: + case ARM_t2SMLALTB: + case ARM_t2SMLALTT: + case ARM_t2SMLATB: + case ARM_t2SMLATT: + case ARM_t2SMLAWB: + case ARM_t2SMLAWT: + case ARM_t2SMLSD: + case ARM_t2SMLSDX: + case ARM_t2SMLSLD: + case ARM_t2SMLSLDX: + case ARM_t2SMMLA: + case ARM_t2SMMLAR: + case ARM_t2SMMLS: + case ARM_t2SMMLSR: + case ARM_t2SMULL: + case ARM_t2UMAAL: + case ARM_t2UMLAL: + case ARM_t2UMULL: + case ARM_t2USADA8: + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case ARM_MVE_VCADDf16: + case ARM_MVE_VCADDf32: + case ARM_MVE_VCADDi16: + case ARM_MVE_VCADDi32: + case ARM_MVE_VCADDi8: + case ARM_MVE_VHCADDs16: + case ARM_MVE_VHCADDs32: + case ARM_MVE_VHCADDs8: + printComplexRotationOp /* printComplexRotationOp<180, 90> (+ ) */ ( + MI, 3, O, 180, 90); + break; + case ARM_MVE_VCMLAf16: + case ARM_MVE_VCMLAf32: + printComplexRotationOp /* printComplexRotationOp<90, 0> (+ ) */ (MI, 4, O, + 90, 0); + break; + case ARM_MVE_VCMULf16: + case ARM_MVE_VCMULf32: + printComplexRotationOp /* printComplexRotationOp<90, 0> (+ ) */ (MI, 3, O, + 90, 0); + break; + case ARM_SBFX: + case ARM_UBFX: + case ARM_t2SBFX: + case ARM_t2UBFX: + printImmPlusOneOperand /* printImmPlusOneOperand (+ ) */ (MI, 3, O); + break; + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8: + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 3, O); + break; + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8: + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + break; + case ARM_t2STLEXD: + case ARM_t2STREXD: + printAddrMode7Operand /* printAddrMode7Operand (+ ) */ (MI, 3, O); + break; + } + return; + break; + case ARM_MVE_VMOV_rr_q: + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + printVectorIndex /* printVectorIndex (+ ) */ (MI, 4, O); + return; + break; + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD3d8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD3q8_UPD: + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 4, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 6, + O); + return; + break; + case ARM_VLD4LNd16: + case ARM_VLD4LNd32: + case ARM_VLD4LNd8: + case ARM_VLD4LNq16: + case ARM_VLD4LNq32: + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 10, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 4, O); + return; + break; + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8: + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 4, O); + return; + break; + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + case ARM_VLD4d8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + case ARM_VLD4q8_UPD: + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 5, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 7, + O); + return; + break; + case ARM_VMULLslsv2i32: + case ARM_VMULLslsv4i16: + case ARM_VMULLsluv2i32: + case ARM_VMULLsluv4i16: + case ARM_VMULslfd: + case ARM_VMULslfq: + case ARM_VMULslhd: + case ARM_VMULslhq: + case ARM_VMULslv2i32: + case ARM_VMULslv4i16: + case ARM_VMULslv4i32: + case ARM_VMULslv8i16: + case ARM_VQDMULHslv2i32: + case ARM_VQDMULHslv4i16: + case ARM_VQDMULHslv4i32: + case ARM_VQDMULHslv8i16: + case ARM_VQDMULLslv2i32: + case ARM_VQDMULLslv4i16: + case ARM_VQRDMULHslv2i32: + case ARM_VQRDMULHslv4i16: + case ARM_VQRDMULHslv4i32: + case ARM_VQRDMULHslv8i16: + return; + break; + case ARM_VST2LNd16: + case ARM_VST2LNd32: + case ARM_VST2LNd8: + case ARM_VST2LNq16: + case ARM_VST2LNq32: + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 4, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + case ARM_VST2LNd16_UPD: + case ARM_VST2LNd32_UPD: + case ARM_VST2LNd8_UPD: + case ARM_VST2LNq16_UPD: + case ARM_VST2LNq32_UPD: + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 6, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 1, O); + printAddrMode6OffsetOperand /* printAddrMode6OffsetOperand (+ ) */ (MI, 3, + O); + return; + break; + case ARM_VST3LNd16: + case ARM_VST3LNd32: + case ARM_VST3LNd8: + case ARM_VST3LNq16: + case ARM_VST3LNq32: + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 5, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 5, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + case ARM_VST4LNd16: + case ARM_VST4LNd32: + case ARM_VST4LNd8: + case ARM_VST4LNq16: + case ARM_VST4LNq32: + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 6, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 6, O); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + SStream_concat0(O, "["); + printNoHashImmediate /* printNoHashImmediate (+ ) */ (MI, 6, O); + SStream_concat0(O, "]}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8: + printOperand /* printOperand (+ ) */ (MI, 5, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand /* printAddrMode6Operand (+ ) */ (MI, 0, O); + return; + break; + } +} + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo, unsigned AltIdx) { + assert(RegNo && RegNo < 295 && "Invalid register number!"); + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrsNoRegAltName[] = { + /* 0 */ "D4_D6_D8_D10\0" + /* 13 */ "D7_D8_D9_D10\0" + /* 26 */ "Q7_Q8_Q9_Q10\0" + /* 39 */ "d10\0" + /* 43 */ "q10\0" + /* 47 */ "r10\0" + /* 51 */ "s10\0" + /* 55 */ "D14_D16_D18_D20\0" + /* 71 */ "D17_D18_D19_D20\0" + /* 87 */ "d20\0" + /* 91 */ "s20\0" + /* 95 */ "D24_D26_D28_D30\0" + /* 111 */ "D27_D28_D29_D30\0" + /* 127 */ "d30\0" + /* 131 */ "s30\0" + /* 135 */ "d0\0" + /* 138 */ "p0\0" + /* 141 */ "q0\0" + /* 144 */ "mvfr0\0" + /* 150 */ "s0\0" + /* 153 */ "D9_D10_D11\0" + /* 164 */ "D5_D7_D9_D11\0" + /* 177 */ "Q8_Q9_Q10_Q11\0" + /* 191 */ "R10_R11\0" + /* 199 */ "d11\0" + /* 203 */ "q11\0" + /* 207 */ "r11\0" + /* 211 */ "s11\0" + /* 215 */ "D19_D20_D21\0" + /* 227 */ "D15_D17_D19_D21\0" + /* 243 */ "d21\0" + /* 247 */ "s21\0" + /* 251 */ "D29_D30_D31\0" + /* 263 */ "D25_D27_D29_D31\0" + /* 279 */ "d31\0" + /* 283 */ "s31\0" + /* 287 */ "Q0_Q1\0" + /* 293 */ "R0_R1\0" + /* 299 */ "d1\0" + /* 302 */ "q1\0" + /* 305 */ "mvfr1\0" + /* 311 */ "s1\0" + /* 314 */ "D6_D8_D10_D12\0" + /* 328 */ "D9_D10_D11_D12\0" + /* 343 */ "Q9_Q10_Q11_Q12\0" + /* 358 */ "d12\0" + /* 362 */ "q12\0" + /* 366 */ "r12\0" + /* 370 */ "s12\0" + /* 374 */ "D16_D18_D20_D22\0" + /* 390 */ "D19_D20_D21_D22\0" + /* 406 */ "d22\0" + /* 410 */ "s22\0" + /* 414 */ "D0_D2\0" + /* 420 */ "D0_D1_D2\0" + /* 429 */ "Q1_Q2\0" + /* 435 */ "d2\0" + /* 438 */ "q2\0" + /* 441 */ "mvfr2\0" + /* 447 */ "s2\0" + /* 450 */ "fpinst2\0" + /* 458 */ "D7_D9_D11_D13\0" + /* 472 */ "D11_D12_D13\0" + /* 484 */ "Q10_Q11_Q12_Q13\0" + /* 500 */ "d13\0" + /* 504 */ "q13\0" + /* 508 */ "s13\0" + /* 512 */ "D17_D19_D21_D23\0" + /* 528 */ "D21_D22_D23\0" + /* 540 */ "d23\0" + /* 544 */ "s23\0" + /* 548 */ "D1_D3\0" + /* 554 */ "D1_D2_D3\0" + /* 563 */ "Q0_Q1_Q2_Q3\0" + /* 575 */ "R2_R3\0" + /* 581 */ "d3\0" + /* 584 */ "q3\0" + /* 587 */ "r3\0" + /* 590 */ "s3\0" + /* 593 */ "D8_D10_D12_D14\0" + /* 608 */ "D11_D12_D13_D14\0" + /* 624 */ "Q11_Q12_Q13_Q14\0" + /* 640 */ "d14\0" + /* 644 */ "q14\0" + /* 648 */ "s14\0" + /* 652 */ "D18_D20_D22_D24\0" + /* 668 */ "D21_D22_D23_D24\0" + /* 684 */ "d24\0" + /* 688 */ "s24\0" + /* 692 */ "D0_D2_D4\0" + /* 701 */ "D1_D2_D3_D4\0" + /* 713 */ "Q1_Q2_Q3_Q4\0" + /* 725 */ "d4\0" + /* 728 */ "q4\0" + /* 731 */ "r4\0" + /* 734 */ "s4\0" + /* 737 */ "D9_D11_D13_D15\0" + /* 752 */ "D13_D14_D15\0" + /* 764 */ "Q12_Q13_Q14_Q15\0" + /* 780 */ "d15\0" + /* 784 */ "q15\0" + /* 788 */ "s15\0" + /* 792 */ "D19_D21_D23_D25\0" + /* 808 */ "D23_D24_D25\0" + /* 820 */ "d25\0" + /* 824 */ "s25\0" + /* 828 */ "D1_D3_D5\0" + /* 837 */ "D3_D4_D5\0" + /* 846 */ "Q2_Q3_Q4_Q5\0" + /* 858 */ "R4_R5\0" + /* 864 */ "d5\0" + /* 867 */ "q5\0" + /* 870 */ "r5\0" + /* 873 */ "s5\0" + /* 876 */ "D10_D12_D14_D16\0" + /* 892 */ "D13_D14_D15_D16\0" + /* 908 */ "d16\0" + /* 912 */ "s16\0" + /* 916 */ "D20_D22_D24_D26\0" + /* 932 */ "D23_D24_D25_D26\0" + /* 948 */ "d26\0" + /* 952 */ "s26\0" + /* 956 */ "D0_D2_D4_D6\0" + /* 968 */ "D3_D4_D5_D6\0" + /* 980 */ "Q3_Q4_Q5_Q6\0" + /* 992 */ "d6\0" + /* 995 */ "q6\0" + /* 998 */ "r6\0" + /* 1001 */ "s6\0" + /* 1004 */ "D11_D13_D15_D17\0" + /* 1020 */ "D15_D16_D17\0" + /* 1032 */ "d17\0" + /* 1036 */ "s17\0" + /* 1040 */ "D21_D23_D25_D27\0" + /* 1056 */ "D25_D26_D27\0" + /* 1068 */ "d27\0" + /* 1072 */ "s27\0" + /* 1076 */ "D1_D3_D5_D7\0" + /* 1088 */ "D5_D6_D7\0" + /* 1097 */ "Q4_Q5_Q6_Q7\0" + /* 1109 */ "R6_R7\0" + /* 1115 */ "d7\0" + /* 1118 */ "q7\0" + /* 1121 */ "r7\0" + /* 1124 */ "s7\0" + /* 1127 */ "D12_D14_D16_D18\0" + /* 1143 */ "D15_D16_D17_D18\0" + /* 1159 */ "d18\0" + /* 1163 */ "s18\0" + /* 1167 */ "D22_D24_D26_D28\0" + /* 1183 */ "D25_D26_D27_D28\0" + /* 1199 */ "d28\0" + /* 1203 */ "s28\0" + /* 1207 */ "D2_D4_D6_D8\0" + /* 1219 */ "D5_D6_D7_D8\0" + /* 1231 */ "Q5_Q6_Q7_Q8\0" + /* 1243 */ "d8\0" + /* 1246 */ "q8\0" + /* 1249 */ "r8\0" + /* 1252 */ "s8\0" + /* 1255 */ "D13_D15_D17_D19\0" + /* 1271 */ "D17_D18_D19\0" + /* 1283 */ "d19\0" + /* 1287 */ "s19\0" + /* 1291 */ "D23_D25_D27_D29\0" + /* 1307 */ "D27_D28_D29\0" + /* 1319 */ "d29\0" + /* 1323 */ "s29\0" + /* 1327 */ "D3_D5_D7_D9\0" + /* 1339 */ "D7_D8_D9\0" + /* 1348 */ "Q6_Q7_Q8_Q9\0" + /* 1360 */ "R8_R9\0" + /* 1366 */ "d9\0" + /* 1369 */ "q9\0" + /* 1372 */ "r9\0" + /* 1375 */ "s9\0" + /* 1378 */ "R12_SP\0" + /* 1385 */ "pc\0" + /* 1388 */ "fpscr_nzcvqc\0" + /* 1401 */ "fpexc\0" + /* 1407 */ "fpsid\0" + /* 1413 */ "itstate\0" + /* 1421 */ "sp\0" + /* 1424 */ "fpscr\0" + /* 1430 */ "lr\0" + /* 1433 */ "vpr\0" + /* 1437 */ "apsr\0" + /* 1442 */ "cpsr\0" + /* 1447 */ "spsr\0" + /* 1452 */ "zr\0" + /* 1455 */ "fpcxtns\0" + /* 1463 */ "fpcxts\0" + /* 1470 */ "fpinst\0" + /* 1477 */ "fpscr_nzcv\0" + /* 1488 */ "apsr_nzcv\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint16_t RegAsmOffsetNoRegAltName[] = { + 1437, 1488, 1442, 1455, 1463, 1401, 1470, 1424, 1477, 1388, 1407, 1413, + 1430, 1385, 1421, 1447, 1433, 1452, 135, 299, 435, 581, 725, 864, + 992, 1115, 1243, 1366, 39, 199, 358, 500, 640, 780, 908, 1032, + 1159, 1283, 87, 243, 406, 540, 684, 820, 948, 1068, 1199, 1319, + 127, 279, 450, 144, 305, 441, 138, 141, 302, 438, 584, 728, + 867, 995, 1118, 1246, 1369, 43, 203, 362, 504, 644, 784, 147, + 308, 444, 587, 731, 870, 998, 1121, 1249, 1372, 47, 207, 366, + 150, 311, 447, 590, 734, 873, 1001, 1124, 1252, 1375, 51, 211, + 370, 508, 648, 788, 912, 1036, 1163, 1287, 91, 247, 410, 544, + 688, 824, 952, 1072, 1203, 1323, 131, 283, 414, 548, 695, 831, + 962, 1082, 1213, 1333, 6, 170, 320, 464, 600, 744, 884, 1012, + 1135, 1263, 63, 235, 382, 520, 660, 800, 924, 1048, 1175, 1299, + 103, 271, 287, 429, 569, 719, 852, 986, 1103, 1237, 1354, 32, + 183, 350, 492, 632, 772, 563, 713, 846, 980, 1097, 1231, 1348, + 26, 177, 343, 484, 624, 764, 293, 575, 858, 1109, 1360, 191, + 1378, 420, 554, 704, 837, 971, 1088, 1222, 1339, 16, 153, 331, + 472, 612, 752, 896, 1020, 1147, 1271, 75, 215, 394, 528, 672, + 808, 936, 1056, 1187, 1307, 115, 251, 692, 828, 959, 1079, 1210, + 1330, 3, 167, 317, 461, 596, 740, 880, 1008, 1131, 1259, 59, + 231, 378, 516, 656, 796, 920, 1044, 1171, 1295, 99, 267, 956, + 1076, 1207, 1327, 0, 164, 314, 458, 593, 737, 876, 1004, 1127, + 1255, 55, 227, 374, 512, 652, 792, 916, 1040, 1167, 1291, 95, + 263, 423, 707, 974, 1225, 19, 335, 616, 900, 1151, 79, 398, + 676, 940, 1191, 119, 701, 968, 1219, 13, 328, 608, 892, 1143, + 71, 390, 668, 932, 1183, 111, + }; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrsRegNamesRaw[] = {/* 0 */ "r13\0" + /* 4 */ "r14\0" + /* 8 */ "r15\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint8_t RegAsmOffsetRegNamesRaw[] = { + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 8, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + }; + + switch (AltIdx) { + default: + llvm_unreachable("Invalid register alt name index!"); + case ARM_NoRegAltName: + assert(*(AsmStrsNoRegAltName + RegAsmOffsetNoRegAltName[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrsNoRegAltName + RegAsmOffsetNoRegAltName[RegNo - 1]; + case ARM_RegNamesRaw: + if (!*(AsmStrsRegNamesRaw + RegAsmOffsetRegNamesRaw[RegNo - 1])) + return getRegisterName(RegNo, ARM_NoRegAltName); + return AsmStrsRegNamesRaw + RegAsmOffsetRegNamesRaw[RegNo - 1]; + } +} +#endif +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +static char *printAliasInstr(MCInst *MI, SStream *OS) { + static const PatternsForOpcode OpToPatterns[] = { + {ARM_DSB, 0, 3}, + {ARM_HINT, 3, 8}, + {ARM_MVE_VMLADAVas16, 11, 1}, + {ARM_MVE_VMLADAVas32, 12, 1}, + {ARM_MVE_VMLADAVas8, 13, 1}, + {ARM_MVE_VMLADAVau16, 14, 1}, + {ARM_MVE_VMLADAVau32, 15, 1}, + {ARM_MVE_VMLADAVau8, 16, 1}, + {ARM_MVE_VMLADAVs16, 17, 1}, + {ARM_MVE_VMLADAVs32, 18, 1}, + {ARM_MVE_VMLADAVs8, 19, 1}, + {ARM_MVE_VMLADAVu16, 20, 1}, + {ARM_MVE_VMLADAVu32, 21, 1}, + {ARM_MVE_VMLADAVu8, 22, 1}, + {ARM_MVE_VMLALDAVas16, 23, 1}, + {ARM_MVE_VMLALDAVas32, 24, 1}, + {ARM_MVE_VMLALDAVau16, 25, 1}, + {ARM_MVE_VMLALDAVau32, 26, 1}, + {ARM_MVE_VMLALDAVs16, 27, 1}, + {ARM_MVE_VMLALDAVs32, 28, 1}, + {ARM_MVE_VMLALDAVu16, 29, 1}, + {ARM_MVE_VMLALDAVu32, 30, 1}, + {ARM_MVE_VORR, 31, 1}, + {ARM_MVE_VRMLALDAVHas32, 32, 1}, + {ARM_MVE_VRMLALDAVHau32, 33, 1}, + {ARM_MVE_VRMLALDAVHs32, 34, 1}, + {ARM_MVE_VRMLALDAVHu32, 35, 1}, + {ARM_t2CSINC, 36, 2}, + {ARM_t2CSINV, 38, 2}, + {ARM_t2CSNEG, 40, 1}, + {ARM_t2DSB, 41, 3}, + {ARM_t2HINT, 44, 8}, + {ARM_t2SUBS_PC_LR, 52, 1}, + {ARM_tHINT, 53, 6}, + }; + + static const AliasPattern Patterns[] = { + // ARM::DSB - 0 + {0, 0, 1, 3}, + {5, 3, 1, 3}, + {11, 6, 1, 3}, + // ARM::HINT - 3 + {15, 9, 3, 3}, + {23, 12, 3, 3}, + {33, 15, 3, 3}, + {41, 18, 3, 3}, + {49, 21, 3, 3}, + {57, 24, 3, 3}, + {66, 27, 3, 3}, + {74, 30, 3, 3}, + // ARM::MVE_VMLADAVas16 - 11 + {83, 33, 7, 6}, + // ARM::MVE_VMLADAVas32 - 12 + {109, 39, 7, 6}, + // ARM::MVE_VMLADAVas8 - 13 + {135, 45, 7, 6}, + // ARM::MVE_VMLADAVau16 - 14 + {160, 51, 7, 6}, + // ARM::MVE_VMLADAVau32 - 15 + {186, 57, 7, 6}, + // ARM::MVE_VMLADAVau8 - 16 + {212, 63, 7, 6}, + // ARM::MVE_VMLADAVs16 - 17 + {237, 69, 6, 5}, + // ARM::MVE_VMLADAVs32 - 18 + {262, 74, 6, 5}, + // ARM::MVE_VMLADAVs8 - 19 + {287, 79, 6, 5}, + // ARM::MVE_VMLADAVu16 - 20 + {311, 84, 6, 5}, + // ARM::MVE_VMLADAVu32 - 21 + {336, 89, 6, 5}, + // ARM::MVE_VMLADAVu8 - 22 + {361, 94, 6, 5}, + // ARM::MVE_VMLALDAVas16 - 23 + {385, 99, 9, 8}, + // ARM::MVE_VMLALDAVas32 - 24 + {416, 107, 9, 8}, + // ARM::MVE_VMLALDAVau16 - 25 + {447, 115, 9, 8}, + // ARM::MVE_VMLALDAVau32 - 26 + {478, 123, 9, 8}, + // ARM::MVE_VMLALDAVs16 - 27 + {509, 131, 7, 6}, + // ARM::MVE_VMLALDAVs32 - 28 + {539, 137, 7, 6}, + // ARM::MVE_VMLALDAVu16 - 29 + {569, 143, 7, 6}, + // ARM::MVE_VMLALDAVu32 - 30 + {599, 149, 7, 6}, + // ARM::MVE_VORR - 31 + {629, 155, 7, 5}, + // ARM::MVE_VRMLALDAVHas32 - 32 + {645, 160, 9, 8}, + // ARM::MVE_VRMLALDAVHau32 - 33 + {678, 168, 9, 8}, + // ARM::MVE_VRMLALDAVHs32 - 34 + {711, 176, 7, 6}, + // ARM::MVE_VRMLALDAVHu32 - 35 + {743, 182, 7, 6}, + // ARM::t2CSINC - 36 + {775, 188, 4, 4}, + {789, 192, 4, 4}, + // ARM::t2CSINV - 38 + {807, 196, 4, 4}, + {822, 200, 4, 4}, + // ARM::t2CSNEG - 40 + {840, 204, 4, 4}, + // ARM::t2DSB - 41 + {0, 208, 3, 6}, + {5, 214, 3, 6}, + {858, 220, 3, 2}, + // ARM::t2HINT - 44 + {866, 222, 3, 3}, + {876, 225, 3, 3}, + {888, 228, 3, 3}, + {898, 231, 3, 3}, + {908, 234, 3, 3}, + {918, 237, 3, 4}, + {929, 241, 3, 4}, + {74, 245, 3, 3}, + // ARM::t2SUBS_PC_LR - 52 + {939, 248, 3, 4}, + // ARM::tHINT - 53 + {15, 252, 3, 3}, + {23, 255, 3, 3}, + {33, 258, 3, 3}, + {41, 261, 3, 3}, + {49, 264, 3, 3}, + {57, 267, 3, 4}, + }; + + static const AliasPatternCond Conds[] = { + // (DSB 0) - 0 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureDB}, + // (DSB 4) - 3 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureDB}, + // (DSB 12) - 6 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureDFB}, + // (HINT 0, pred:$p) - 9 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6KOps}, + // (HINT 1, pred:$p) - 12 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6KOps}, + // (HINT 2, pred:$p) - 15 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6KOps}, + // (HINT 3, pred:$p) - 18 + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6KOps}, + // (HINT 4, pred:$p) - 21 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6KOps}, + // (HINT 5, pred:$p) - 24 + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV8Ops}, + // (HINT 16, pred:$p) - 27 + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureRAS}, + // (HINT 20, pred:$p) - 30 + {AliasPatternCond_K_Imm, (uint32_t)20}, + {AliasPatternCond_K_NegFeature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6KOps}, + // (MVE_VMLADAVas16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 33 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVas32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 39 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVas8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 45 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVau16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 51 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVau32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 57 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVau8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 63 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVs16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 69 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVs32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 74 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVs8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 79 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVu16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 84 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVu32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - + // 89 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLADAVu8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 94 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLALDAVas16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 99 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLALDAVas32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 107 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLALDAVau16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 115 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLALDAVau32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 123 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLALDAVs16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 131 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLALDAVs32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 137 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLALDAVu16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 143 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VMLALDAVu32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 149 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp) - 155 + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VRMLALDAVHas32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 160 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VRMLALDAVHau32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, + // MQPR:$Qm, vpred_n:$vp) - 168 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VRMLALDAVHs32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, + // vpred_n:$vp) - 176 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (MVE_VRMLALDAVHu32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, + // vpred_n:$vp) - 182 + {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID}, + {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID}, + {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + // (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 188 + {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID}, + {AliasPatternCond_K_Reg, ARM_ZR}, + {AliasPatternCond_K_Reg, ARM_ZR}, + {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps}, + // (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, + // pred_noal_inv:$fcond) - 192 + {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps}, + // (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 196 + {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID}, + {AliasPatternCond_K_Reg, ARM_ZR}, + {AliasPatternCond_K_Reg, ARM_ZR}, + {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps}, + // (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, + // pred_noal_inv:$fcond) - 200 + {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps}, + // (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, + // pred_noal_inv:$fcond) - 204 + {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID}, + {AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps}, + // (t2DSB 0, 14, 0) - 208 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, ARM_FeatureDB}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + // (t2DSB 4, 14, 0) - 214 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, ARM_FeatureDB}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + // (t2DSB 12, pred:$p) - 220 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, ARM_FeatureDFB}, + // (t2HINT 0, pred:$p) - 222 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + // (t2HINT 1, pred:$p) - 225 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + // (t2HINT 2, pred:$p) - 228 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + // (t2HINT 3, pred:$p) - 231 + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + // (t2HINT 4, pred:$p) - 234 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + // (t2HINT 5, pred:$p) - 237 + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + {AliasPatternCond_K_Feature, ARM_HasV8Ops}, + // (t2HINT 16, pred:$p) - 241 + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + {AliasPatternCond_K_Feature, ARM_FeatureRAS}, + // (t2HINT 20, pred:$p) - 245 + {AliasPatternCond_K_Imm, (uint32_t)20}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + // (t2SUBS_PC_LR 0, pred:$p) - 248 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + {AliasPatternCond_K_Feature, ARM_FeatureVirtualization}, + // (tHINT 0, pred:$p) - 252 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6MOps}, + // (tHINT 1, pred:$p) - 255 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6MOps}, + // (tHINT 2, pred:$p) - 258 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6MOps}, + // (tHINT 3, pred:$p) - 261 + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6MOps}, + // (tHINT 4, pred:$p) - 264 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_HasV6MOps}, + // (tHINT 5, pred:$p) - 267 + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, ARM_ModeThumb}, + {AliasPatternCond_K_Feature, ARM_FeatureThumb2}, + {AliasPatternCond_K_Feature, ARM_HasV8Ops}, + }; + + static const char *AsmStrings[] = { + /* 0 */ + "ssbb\0" + /* 5 */ "pssbb\0" + /* 11 */ "dfb\0" + /* 15 */ "nop$\xFF\x02\x01\0" + /* 23 */ "yield$\xFF\x02\x01\0" + /* 33 */ "wfe$\xFF\x02\x01\0" + /* 41 */ "wfi$\xFF\x02\x01\0" + /* 49 */ "sev$\xFF\x02\x01\0" + /* 57 */ "sevl$\xFF\x02\x01\0" + /* 66 */ "esb$\xFF\x02\x01\0" + /* 74 */ "csdb$\xFF\x02\x01\0" + /* 83 */ "vmlava$\xFF\x05\x02.s16 $\x01, $\x03, $\x04\0" + /* 109 */ "vmlava$\xFF\x05\x02.s32 $\x01, $\x03, $\x04\0" + /* 135 */ "vmlava$\xFF\x05\x02.s8 $\x01, $\x03, $\x04\0" + /* 160 */ "vmlava$\xFF\x05\x02.u16 $\x01, $\x03, $\x04\0" + /* 186 */ "vmlava$\xFF\x05\x02.u32 $\x01, $\x03, $\x04\0" + /* 212 */ "vmlava$\xFF\x05\x02.u8 $\x01, $\x03, $\x04\0" + /* 237 */ "vmlav$\xFF\x04\x02.s16 $\x01, $\x02, $\x03\0" + /* 262 */ "vmlav$\xFF\x04\x02.s32 $\x01, $\x02, $\x03\0" + /* 287 */ "vmlav$\xFF\x04\x02.s8 $\x01, $\x02, $\x03\0" + /* 311 */ "vmlav$\xFF\x04\x02.u16 $\x01, $\x02, $\x03\0" + /* 336 */ "vmlav$\xFF\x04\x02.u32 $\x01, $\x02, $\x03\0" + /* 361 */ "vmlav$\xFF\x04\x02.u8 $\x01, $\x02, $\x03\0" + /* 385 */ "vmlalva$\xFF\x07\x02.s16 $\x01, $\x02, $\x05, $\x06\0" + /* 416 */ "vmlalva$\xFF\x07\x02.s32 $\x01, $\x02, $\x05, $\x06\0" + /* 447 */ "vmlalva$\xFF\x07\x02.u16 $\x01, $\x02, $\x05, $\x06\0" + /* 478 */ "vmlalva$\xFF\x07\x02.u32 $\x01, $\x02, $\x05, $\x06\0" + /* 509 */ "vmlalv$\xFF\x05\x02.s16 $\x01, $\x02, $\x03, $\x04\0" + /* 539 */ "vmlalv$\xFF\x05\x02.s32 $\x01, $\x02, $\x03, $\x04\0" + /* 569 */ "vmlalv$\xFF\x05\x02.u16 $\x01, $\x02, $\x03, $\x04\0" + /* 599 */ "vmlalv$\xFF\x05\x02.u32 $\x01, $\x02, $\x03, $\x04\0" + /* 629 */ "vmov$\xFF\x04\x02 $\x01, $\x02\0" + /* 645 */ "vrmlalvha$\xFF\x07\x02.s32 $\x01, $\x02, $\x05, $\x06\0" + /* 678 */ "vrmlalvha$\xFF\x07\x02.u32 $\x01, $\x02, $\x05, $\x06\0" + /* 711 */ "vrmlalvh$\xFF\x05\x02.s32 $\x01, $\x02, $\x03, $\x04\0" + /* 743 */ "vrmlalvh$\xFF\x05\x02.u32 $\x01, $\x02, $\x03, $\x04\0" + /* 775 */ "cset $\x01, $\xFF\x04\x03\0" + /* 789 */ "cinc $\x01, $\x02, $\xFF\x04\x03\0" + /* 807 */ "csetm $\x01, $\xFF\x04\x03\0" + /* 822 */ "cinv $\x01, $\x02, $\xFF\x04\x03\0" + /* 840 */ "cneg $\x01, $\x02, $\xFF\x04\x03\0" + /* 858 */ "dfb$\xFF\x02\x01\0" + /* 866 */ "nop$\xFF\x02\x01.w\0" + /* 876 */ "yield$\xFF\x02\x01.w\0" + /* 888 */ "wfe$\xFF\x02\x01.w\0" + /* 898 */ "wfi$\xFF\x02\x01.w\0" + /* 908 */ "sev$\xFF\x02\x01.w\0" + /* 918 */ "sevl$\xFF\x02\x01.w\0" + /* 929 */ "esb$\xFF\x02\x01.w\0" + /* 939 */ "eret$\xFF\x02\x01\0"}; + + const char *AsmString = MCInstPrinter_matchAliasPatterns( + MI, OpToPatterns, Patterns, Conds, AsmStrings, 34); + if (!AsmString) + return false; + + char *tmpString = cs_strdup(AsmString); + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, "\t"); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, *(tmpString + (I++))); + } + } while (AsmString[I] != '\0'); + } + + return tmpString; +} + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { + switch (PrintMethodIdx) { + default: + llvm_unreachable("Unknown PrintMethod kind"); + break; + // printPredicateOperand + case 0: + printPredicateOperand(MI, OpIdx, OS); + break; + // printVPTPredicateOperand + case 1: + printVPTPredicateOperand(MI, OpIdx, OS); + break; + // printMandatoryInvertedPredicateOperand + case 2: + printMandatoryInvertedPredicateOperand(MI, OpIdx, OS); + break; + } +} + +#endif // PRINT_ALIAS_INSTR +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo3[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo4[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo5[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo6[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo7[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo8[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo9[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo10[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo11[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo12[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo13[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo14[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo15[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo16[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo17[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo18[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo19[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo20[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo21[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo22[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo23[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo24[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo25[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo26[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo27[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo28[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo29[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo30[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo31[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo32[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo33[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo34[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo35[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo36[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo37[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo38[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo39[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo40[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo41[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo42[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo43[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo44[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo45[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo46[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo47[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo48[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo49[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo50[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo51[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo52[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo53[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo54[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo55[] = { + {ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo56[] = { + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo57[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo58[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo59[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo60[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo61[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo62[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo63[] = { + {ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo64[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo65[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo66[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo67[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo68[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo69[] = { + {ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo70[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo71[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo72[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo73[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo74[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo75[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo76[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo77[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo78[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo79[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo80[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo81[] = { + {ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo82[] = { + {ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo83[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo84[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo85[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo86[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo87[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo88[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo89[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo90[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo91[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo92[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo93[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo94[] = { + {ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo95[] = { + {ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo96[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo97[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo98[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo99[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo100[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo101[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo102[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo103[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo104[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo105[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo106[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo107[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo108[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo109[] = { + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo110[] = { + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo111[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo112[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo113[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo114[] = { + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo115[] = { + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo116[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo117[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo118[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo119[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo120[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo121[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo122[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo123[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo124[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo125[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo126[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo127[] = { + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo128[] = { + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo129[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo130[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo131[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo132[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo133[] = { + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo134[] = { + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo135[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo136[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo137[] = { + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo138[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo139[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo140[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo141[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo142[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo143[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo144[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo145[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo146[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo147[] = { + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo148[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo149[] = { + {ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo150[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo151[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo152[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo153[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo154[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo155[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo156[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo157[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo158[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo159[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo160[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo161[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo162[] = { + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo163[] = { + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, + MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo164[] = { + {ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo165[] = { + {ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo166[] = { + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo167[] = { + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, + MCOI_TIED_TO /*0*/}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo168[] = { + {ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo169[] = { + {ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo170[] = { + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo171[] = { + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, + MCOI_TIED_TO /*0*/}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo172[] = { + {ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo173[] = { + {ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo174[] = { + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo175[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo176[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo177[] = { + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo178[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo179[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo180[] = { + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo181[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo182[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo183[] = { + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo184[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo185[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo186[] = { + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo187[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo188[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo189[] = { + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo190[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo191[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo192[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo193[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo194[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo195[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo196[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo197[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo198[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo199[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo200[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo201[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo202[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo203[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo204[] = { + {ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo205[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo206[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo207[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo208[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo209[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo210[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo211[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo212[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo213[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo214[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*2*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo215[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo216[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo217[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo218[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo219[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo220[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo221[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo222[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo223[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo224[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo225[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo226[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo227[] = { + {ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo228[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo229[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo230[] = { + {ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo231[] = { + {ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo232[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo233[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo234[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo235[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo236[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo237[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo238[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo239[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo240[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo241[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo242[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo243[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo244[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo245[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo246[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo247[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo248[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo249[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo250[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo251[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo252[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo253[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo254[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo255[] = { + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo256[] = { + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo257[] = { + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo258[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo259[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo260[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo261[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo262[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo263[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo264[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo265[] = { + {ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo266[] = { + {ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, +}; +static const MCOperandInfo OperandInfo267[] = { + {ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo268[] = { + {ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, +}; +static const MCOperandInfo OperandInfo269[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo270[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo271[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo272[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo273[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo274[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo275[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo276[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo277[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo278[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo279[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo280[] = { + {ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo281[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo282[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo283[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo284[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo285[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo286[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo287[] = { + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo288[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo289[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo290[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo291[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo292[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo293[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo294[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo295[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo296[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo297[] = { + {ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo298[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo299[] = { + {ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo300[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo301[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo302[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo303[] = { + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRlrRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo304[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo305[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo306[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo307[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo308[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo309[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo310[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo311[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo312[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo313[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo314[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo315[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo316[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo317[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo318[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo319[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo320[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo321[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo322[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo323[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo324[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo325[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo326[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo327[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo328[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo329[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo330[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo331[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo332[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo333[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo334[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo335[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo336[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo337[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo338[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo339[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo340[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo341[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo342[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo343[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo344[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo345[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo346[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo347[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo348[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo349[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo350[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo351[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo352[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo353[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo354[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo355[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo356[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo357[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo358[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo359[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo360[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo361[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo362[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo363[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo364[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo365[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo366[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo367[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo368[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo369[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo370[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo371[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo372[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo373[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo374[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo375[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo376[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo377[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo378[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo379[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo380[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo381[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo382[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo383[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo384[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo385[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo386[] = { + {ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo387[] = { + {ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo388[] = { + {ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo389[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo390[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo391[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo392[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo393[] = { + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo394[] = { + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo395[] = { + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo396[] = { + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo397[] = { + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo398[] = { + {ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo399[] = { + {ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo400[] = { + {ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo401[] = { + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo402[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo403[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*2*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo404[] = { + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo405[] = { + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo406[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo407[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*3*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo408[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*2*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo409[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*3*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*2*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo410[] = { + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo411[] = { + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo412[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo413[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*4*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo414[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*2*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*3*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo415[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*4*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*2*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*3*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo416[] = { + {ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo417[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo418[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo419[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo420[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo421[] = { + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo422[] = { + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo423[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo424[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo425[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo426[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo427[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo428[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo429[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo430[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo431[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo432[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo433[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo434[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo435[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo436[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo437[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo438[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo439[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo440[] = { + {ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo441[] = { + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo442[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo443[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo444[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo445[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo446[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo447[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo448[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo449[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo450[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo451[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo452[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo453[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo454[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo455[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo456[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo457[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo458[] = { + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo459[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo460[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo461[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo462[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo463[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo464[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo465[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo466[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo467[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo468[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo469[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo470[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo471[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo472[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo473[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo474[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo475[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo476[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo477[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo478[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo479[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo480[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo481[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo482[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo483[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo484[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo485[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo486[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo487[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo488[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo489[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo490[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo491[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo492[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo493[] = { + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo494[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo495[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo496[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo497[] = { + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo498[] = { + {ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo499[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo500[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo501[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo502[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo503[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo504[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo505[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo506[] = { + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo507[] = { + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo508[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo509[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo510[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo511[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo512[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo513[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo514[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo515[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo516[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo517[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo518[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo519[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo520[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo521[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo522[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*2*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo523[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo524[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo525[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo526[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo527[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo528[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo529[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo530[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo531[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo532[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo533[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo534[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo535[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo536[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo537[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo538[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo539[] = { + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo540[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo541[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo542[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo543[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo544[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo545[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo546[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo547[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo548[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo549[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo550[] = { + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo551[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo552[] = { + {ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo553[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo554[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo555[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo556[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo557[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo558[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo559[] = { + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo560[] = { + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo561[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo562[] = { + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo563[] = { + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo564[] = { + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo565[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo566[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo567[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo568[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo569[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo570[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo571[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo572[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo573[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo574[] = { + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0}, + {ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo575[] = { + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; + +extern const MCInstrDesc ARMInsts[] = { + {1, OperandInfo2}, // Inst #0 = PHI + {0, NULL}, // Inst #1 = INLINEASM + {0, NULL}, // Inst #2 = INLINEASM_BR + {1, OperandInfo3}, // Inst #3 = CFI_INSTRUCTION + {1, OperandInfo3}, // Inst #4 = EH_LABEL + {1, OperandInfo3}, // Inst #5 = GC_LABEL + {1, OperandInfo3}, // Inst #6 = ANNOTATION_LABEL + {0, NULL}, // Inst #7 = KILL + {3, OperandInfo4}, // Inst #8 = EXTRACT_SUBREG + {4, OperandInfo5}, // Inst #9 = INSERT_SUBREG + {1, OperandInfo2}, // Inst #10 = IMPLICIT_DEF + {4, OperandInfo6}, // Inst #11 = SUBREG_TO_REG + {3, OperandInfo4}, // Inst #12 = COPY_TO_REGCLASS + {0, NULL}, // Inst #13 = DBG_VALUE + {0, NULL}, // Inst #14 = DBG_VALUE_LIST + {0, NULL}, // Inst #15 = DBG_INSTR_REF + {0, NULL}, // Inst #16 = DBG_PHI + {1, OperandInfo2}, // Inst #17 = DBG_LABEL + {2, OperandInfo7}, // Inst #18 = REG_SEQUENCE + {2, OperandInfo7}, // Inst #19 = COPY + {0, NULL}, // Inst #20 = BUNDLE + {1, OperandInfo3}, // Inst #21 = LIFETIME_START + {1, OperandInfo3}, // Inst #22 = LIFETIME_END + {4, OperandInfo8}, // Inst #23 = PSEUDO_PROBE + {2, OperandInfo9}, // Inst #24 = ARITH_FENCE + {2, OperandInfo10}, // Inst #25 = STACKMAP + {0, NULL}, // Inst #26 = FENTRY_CALL + {6, OperandInfo11}, // Inst #27 = PATCHPOINT + {1, OperandInfo12}, // Inst #28 = LOAD_STACK_GUARD + {1, OperandInfo3}, // Inst #29 = PREALLOCATED_SETUP + {3, OperandInfo13}, // Inst #30 = PREALLOCATED_ARG + {0, NULL}, // Inst #31 = STATEPOINT + {2, OperandInfo14}, // Inst #32 = LOCAL_ESCAPE + {1, OperandInfo2}, // Inst #33 = FAULTING_OP + {0, NULL}, // Inst #34 = PATCHABLE_OP + {0, NULL}, // Inst #35 = PATCHABLE_FUNCTION_ENTER + {0, NULL}, // Inst #36 = PATCHABLE_RET + {0, NULL}, // Inst #37 = PATCHABLE_FUNCTION_EXIT + {0, NULL}, // Inst #38 = PATCHABLE_TAIL_CALL + {2, OperandInfo15}, // Inst #39 = PATCHABLE_EVENT_CALL + {3, OperandInfo16}, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + {0, NULL}, // Inst #41 = ICALL_BRANCH_FUNNEL + {3, OperandInfo17}, // Inst #42 = G_ASSERT_SEXT + {3, OperandInfo17}, // Inst #43 = G_ASSERT_ZEXT + {3, OperandInfo18}, // Inst #44 = G_ADD + {3, OperandInfo18}, // Inst #45 = G_SUB + {3, OperandInfo18}, // Inst #46 = G_MUL + {3, OperandInfo18}, // Inst #47 = G_SDIV + {3, OperandInfo18}, // Inst #48 = G_UDIV + {3, OperandInfo18}, // Inst #49 = G_SREM + {3, OperandInfo18}, // Inst #50 = G_UREM + {4, OperandInfo19}, // Inst #51 = G_SDIVREM + {4, OperandInfo19}, // Inst #52 = G_UDIVREM + {3, OperandInfo18}, // Inst #53 = G_AND + {3, OperandInfo18}, // Inst #54 = G_OR + {3, OperandInfo18}, // Inst #55 = G_XOR + {1, OperandInfo20}, // Inst #56 = G_IMPLICIT_DEF + {1, OperandInfo20}, // Inst #57 = G_PHI + {2, OperandInfo21}, // Inst #58 = G_FRAME_INDEX + {2, OperandInfo21}, // Inst #59 = G_GLOBAL_VALUE + {3, OperandInfo22}, // Inst #60 = G_EXTRACT + {2, OperandInfo23}, // Inst #61 = G_UNMERGE_VALUES + {4, OperandInfo24}, // Inst #62 = G_INSERT + {2, OperandInfo23}, // Inst #63 = G_MERGE_VALUES + {2, OperandInfo23}, // Inst #64 = G_BUILD_VECTOR + {2, OperandInfo23}, // Inst #65 = G_BUILD_VECTOR_TRUNC + {2, OperandInfo23}, // Inst #66 = G_CONCAT_VECTORS + {2, OperandInfo23}, // Inst #67 = G_PTRTOINT + {2, OperandInfo23}, // Inst #68 = G_INTTOPTR + {2, OperandInfo23}, // Inst #69 = G_BITCAST + {2, OperandInfo25}, // Inst #70 = G_FREEZE + {2, OperandInfo25}, // Inst #71 = G_INTRINSIC_TRUNC + {2, OperandInfo25}, // Inst #72 = G_INTRINSIC_ROUND + {2, OperandInfo23}, // Inst #73 = G_INTRINSIC_LRINT + {2, OperandInfo25}, // Inst #74 = G_INTRINSIC_ROUNDEVEN + {1, OperandInfo20}, // Inst #75 = G_READCYCLECOUNTER + {2, OperandInfo23}, // Inst #76 = G_LOAD + {2, OperandInfo23}, // Inst #77 = G_SEXTLOAD + {2, OperandInfo23}, // Inst #78 = G_ZEXTLOAD + {5, OperandInfo26}, // Inst #79 = G_INDEXED_LOAD + {5, OperandInfo26}, // Inst #80 = G_INDEXED_SEXTLOAD + {5, OperandInfo26}, // Inst #81 = G_INDEXED_ZEXTLOAD + {2, OperandInfo23}, // Inst #82 = G_STORE + {5, OperandInfo27}, // Inst #83 = G_INDEXED_STORE + {5, OperandInfo28}, // Inst #84 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + {4, OperandInfo29}, // Inst #85 = G_ATOMIC_CMPXCHG + {3, OperandInfo30}, // Inst #86 = G_ATOMICRMW_XCHG + {3, OperandInfo30}, // Inst #87 = G_ATOMICRMW_ADD + {3, OperandInfo30}, // Inst #88 = G_ATOMICRMW_SUB + {3, OperandInfo30}, // Inst #89 = G_ATOMICRMW_AND + {3, OperandInfo30}, // Inst #90 = G_ATOMICRMW_NAND + {3, OperandInfo30}, // Inst #91 = G_ATOMICRMW_OR + {3, OperandInfo30}, // Inst #92 = G_ATOMICRMW_XOR + {3, OperandInfo30}, // Inst #93 = G_ATOMICRMW_MAX + {3, OperandInfo30}, // Inst #94 = G_ATOMICRMW_MIN + {3, OperandInfo30}, // Inst #95 = G_ATOMICRMW_UMAX + {3, OperandInfo30}, // Inst #96 = G_ATOMICRMW_UMIN + {3, OperandInfo30}, // Inst #97 = G_ATOMICRMW_FADD + {3, OperandInfo30}, // Inst #98 = G_ATOMICRMW_FSUB + {2, OperandInfo10}, // Inst #99 = G_FENCE + {2, OperandInfo21}, // Inst #100 = G_BRCOND + {1, OperandInfo20}, // Inst #101 = G_BRINDIRECT + {1, OperandInfo2}, // Inst #102 = G_INTRINSIC + {1, OperandInfo2}, // Inst #103 = G_INTRINSIC_W_SIDE_EFFECTS + {2, OperandInfo23}, // Inst #104 = G_ANYEXT + {2, OperandInfo23}, // Inst #105 = G_TRUNC + {2, OperandInfo21}, // Inst #106 = G_CONSTANT + {2, OperandInfo21}, // Inst #107 = G_FCONSTANT + {1, OperandInfo20}, // Inst #108 = G_VASTART + {3, OperandInfo31}, // Inst #109 = G_VAARG + {2, OperandInfo23}, // Inst #110 = G_SEXT + {3, OperandInfo17}, // Inst #111 = G_SEXT_INREG + {2, OperandInfo23}, // Inst #112 = G_ZEXT + {3, OperandInfo32}, // Inst #113 = G_SHL + {3, OperandInfo32}, // Inst #114 = G_LSHR + {3, OperandInfo32}, // Inst #115 = G_ASHR + {4, OperandInfo33}, // Inst #116 = G_FSHL + {4, OperandInfo33}, // Inst #117 = G_FSHR + {3, OperandInfo32}, // Inst #118 = G_ROTR + {3, OperandInfo32}, // Inst #119 = G_ROTL + {4, OperandInfo34}, // Inst #120 = G_ICMP + {4, OperandInfo34}, // Inst #121 = G_FCMP + {4, OperandInfo29}, // Inst #122 = G_SELECT + {4, OperandInfo29}, // Inst #123 = G_UADDO + {5, OperandInfo35}, // Inst #124 = G_UADDE + {4, OperandInfo29}, // Inst #125 = G_USUBO + {5, OperandInfo35}, // Inst #126 = G_USUBE + {4, OperandInfo29}, // Inst #127 = G_SADDO + {5, OperandInfo35}, // Inst #128 = G_SADDE + {4, OperandInfo29}, // Inst #129 = G_SSUBO + {5, OperandInfo35}, // Inst #130 = G_SSUBE + {4, OperandInfo29}, // Inst #131 = G_UMULO + {4, OperandInfo29}, // Inst #132 = G_SMULO + {3, OperandInfo18}, // Inst #133 = G_UMULH + {3, OperandInfo18}, // Inst #134 = G_SMULH + {3, OperandInfo18}, // Inst #135 = G_UADDSAT + {3, OperandInfo18}, // Inst #136 = G_SADDSAT + {3, OperandInfo18}, // Inst #137 = G_USUBSAT + {3, OperandInfo18}, // Inst #138 = G_SSUBSAT + {3, OperandInfo32}, // Inst #139 = G_USHLSAT + {3, OperandInfo32}, // Inst #140 = G_SSHLSAT + {4, OperandInfo36}, // Inst #141 = G_SMULFIX + {4, OperandInfo36}, // Inst #142 = G_UMULFIX + {4, OperandInfo36}, // Inst #143 = G_SMULFIXSAT + {4, OperandInfo36}, // Inst #144 = G_UMULFIXSAT + {4, OperandInfo36}, // Inst #145 = G_SDIVFIX + {4, OperandInfo36}, // Inst #146 = G_UDIVFIX + {4, OperandInfo36}, // Inst #147 = G_SDIVFIXSAT + {4, OperandInfo36}, // Inst #148 = G_UDIVFIXSAT + {3, OperandInfo18}, // Inst #149 = G_FADD + {3, OperandInfo18}, // Inst #150 = G_FSUB + {3, OperandInfo18}, // Inst #151 = G_FMUL + {4, OperandInfo19}, // Inst #152 = G_FMA + {4, OperandInfo19}, // Inst #153 = G_FMAD + {3, OperandInfo18}, // Inst #154 = G_FDIV + {3, OperandInfo18}, // Inst #155 = G_FREM + {3, OperandInfo18}, // Inst #156 = G_FPOW + {3, OperandInfo32}, // Inst #157 = G_FPOWI + {2, OperandInfo25}, // Inst #158 = G_FEXP + {2, OperandInfo25}, // Inst #159 = G_FEXP2 + {2, OperandInfo25}, // Inst #160 = G_FLOG + {2, OperandInfo25}, // Inst #161 = G_FLOG2 + {2, OperandInfo25}, // Inst #162 = G_FLOG10 + {2, OperandInfo25}, // Inst #163 = G_FNEG + {2, OperandInfo23}, // Inst #164 = G_FPEXT + {2, OperandInfo23}, // Inst #165 = G_FPTRUNC + {2, OperandInfo23}, // Inst #166 = G_FPTOSI + {2, OperandInfo23}, // Inst #167 = G_FPTOUI + {2, OperandInfo23}, // Inst #168 = G_SITOFP + {2, OperandInfo23}, // Inst #169 = G_UITOFP + {2, OperandInfo25}, // Inst #170 = G_FABS + {3, OperandInfo32}, // Inst #171 = G_FCOPYSIGN + {2, OperandInfo25}, // Inst #172 = G_FCANONICALIZE + {3, OperandInfo18}, // Inst #173 = G_FMINNUM + {3, OperandInfo18}, // Inst #174 = G_FMAXNUM + {3, OperandInfo18}, // Inst #175 = G_FMINNUM_IEEE + {3, OperandInfo18}, // Inst #176 = G_FMAXNUM_IEEE + {3, OperandInfo18}, // Inst #177 = G_FMINIMUM + {3, OperandInfo18}, // Inst #178 = G_FMAXIMUM + {3, OperandInfo32}, // Inst #179 = G_PTR_ADD + {3, OperandInfo32}, // Inst #180 = G_PTRMASK + {3, OperandInfo18}, // Inst #181 = G_SMIN + {3, OperandInfo18}, // Inst #182 = G_SMAX + {3, OperandInfo18}, // Inst #183 = G_UMIN + {3, OperandInfo18}, // Inst #184 = G_UMAX + {2, OperandInfo25}, // Inst #185 = G_ABS + {2, OperandInfo23}, // Inst #186 = G_LROUND + {2, OperandInfo23}, // Inst #187 = G_LLROUND + {1, OperandInfo2}, // Inst #188 = G_BR + {3, OperandInfo37}, // Inst #189 = G_BRJT + {4, OperandInfo38}, // Inst #190 = G_INSERT_VECTOR_ELT + {3, OperandInfo39}, // Inst #191 = G_EXTRACT_VECTOR_ELT + {4, OperandInfo40}, // Inst #192 = G_SHUFFLE_VECTOR + {2, OperandInfo23}, // Inst #193 = G_CTTZ + {2, OperandInfo23}, // Inst #194 = G_CTTZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #195 = G_CTLZ + {2, OperandInfo23}, // Inst #196 = G_CTLZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #197 = G_CTPOP + {2, OperandInfo25}, // Inst #198 = G_BSWAP + {2, OperandInfo25}, // Inst #199 = G_BITREVERSE + {2, OperandInfo25}, // Inst #200 = G_FCEIL + {2, OperandInfo25}, // Inst #201 = G_FCOS + {2, OperandInfo25}, // Inst #202 = G_FSIN + {2, OperandInfo25}, // Inst #203 = G_FSQRT + {2, OperandInfo25}, // Inst #204 = G_FFLOOR + {2, OperandInfo25}, // Inst #205 = G_FRINT + {2, OperandInfo25}, // Inst #206 = G_FNEARBYINT + {2, OperandInfo23}, // Inst #207 = G_ADDRSPACE_CAST + {2, OperandInfo21}, // Inst #208 = G_BLOCK_ADDR + {2, OperandInfo21}, // Inst #209 = G_JUMP_TABLE + {3, OperandInfo22}, // Inst #210 = G_DYN_STACKALLOC + {3, OperandInfo18}, // Inst #211 = G_STRICT_FADD + {3, OperandInfo18}, // Inst #212 = G_STRICT_FSUB + {3, OperandInfo18}, // Inst #213 = G_STRICT_FMUL + {3, OperandInfo18}, // Inst #214 = G_STRICT_FDIV + {3, OperandInfo18}, // Inst #215 = G_STRICT_FREM + {4, OperandInfo19}, // Inst #216 = G_STRICT_FMA + {2, OperandInfo25}, // Inst #217 = G_STRICT_FSQRT + {2, OperandInfo21}, // Inst #218 = G_READ_REGISTER + {2, OperandInfo41}, // Inst #219 = G_WRITE_REGISTER + {4, OperandInfo42}, // Inst #220 = G_MEMCPY + {3, OperandInfo39}, // Inst #221 = G_MEMCPY_INLINE + {4, OperandInfo42}, // Inst #222 = G_MEMMOVE + {4, OperandInfo42}, // Inst #223 = G_MEMSET + {3, OperandInfo22}, // Inst #224 = G_BZERO + {3, OperandInfo39}, // Inst #225 = G_VECREDUCE_SEQ_FADD + {3, OperandInfo39}, // Inst #226 = G_VECREDUCE_SEQ_FMUL + {2, OperandInfo23}, // Inst #227 = G_VECREDUCE_FADD + {2, OperandInfo23}, // Inst #228 = G_VECREDUCE_FMUL + {2, OperandInfo23}, // Inst #229 = G_VECREDUCE_FMAX + {2, OperandInfo23}, // Inst #230 = G_VECREDUCE_FMIN + {2, OperandInfo23}, // Inst #231 = G_VECREDUCE_ADD + {2, OperandInfo23}, // Inst #232 = G_VECREDUCE_MUL + {2, OperandInfo23}, // Inst #233 = G_VECREDUCE_AND + {2, OperandInfo23}, // Inst #234 = G_VECREDUCE_OR + {2, OperandInfo23}, // Inst #235 = G_VECREDUCE_XOR + {2, OperandInfo23}, // Inst #236 = G_VECREDUCE_SMAX + {2, OperandInfo23}, // Inst #237 = G_VECREDUCE_SMIN + {2, OperandInfo23}, // Inst #238 = G_VECREDUCE_UMAX + {2, OperandInfo23}, // Inst #239 = G_VECREDUCE_UMIN + {4, OperandInfo43}, // Inst #240 = G_SBFX + {4, OperandInfo43}, // Inst #241 = G_UBFX + {2, OperandInfo44}, // Inst #242 = ABS + {5, OperandInfo45}, // Inst #243 = ADDSri + {5, OperandInfo46}, // Inst #244 = ADDSrr + {6, OperandInfo47}, // Inst #245 = ADDSrsi + {7, OperandInfo48}, // Inst #246 = ADDSrsr + {4, OperandInfo49}, // Inst #247 = ADJCALLSTACKDOWN + {4, OperandInfo49}, // Inst #248 = ADJCALLSTACKUP + {6, OperandInfo50}, // Inst #249 = ASRi + {6, OperandInfo51}, // Inst #250 = ASRr + {1, OperandInfo52}, // Inst #251 = B + {4, OperandInfo53}, // Inst #252 = BCCZi64 + {6, OperandInfo54}, // Inst #253 = BCCi64 + {1, OperandInfo55}, // Inst #254 = BLX_noip + {1, OperandInfo55}, // Inst #255 = BLX_pred_noip + {2, OperandInfo56}, // Inst #256 = BL_PUSHLR + {1, OperandInfo52}, // Inst #257 = BMOVPCB_CALL + {1, OperandInfo57}, // Inst #258 = BMOVPCRX_CALL + {3, OperandInfo58}, // Inst #259 = BR_JTadd + {3, OperandInfo59}, // Inst #260 = BR_JTm_i12 + {4, OperandInfo60}, // Inst #261 = BR_JTm_rs + {2, OperandInfo61}, // Inst #262 = BR_JTr + {1, OperandInfo57}, // Inst #263 = BX_CALL + {5, OperandInfo62}, // Inst #264 = CMP_SWAP_16 + {5, OperandInfo62}, // Inst #265 = CMP_SWAP_32 + {5, OperandInfo63}, // Inst #266 = CMP_SWAP_64 + {5, OperandInfo62}, // Inst #267 = CMP_SWAP_8 + {3, OperandInfo4}, // Inst #268 = CONSTPOOL_ENTRY + {4, OperandInfo64}, // Inst #269 = COPY_STRUCT_BYVAL_I32 + {1, OperandInfo3}, // Inst #270 = CompilerBarrier + {2, OperandInfo7}, // Inst #271 = ITasm + {0, NULL}, // Inst #272 = Int_eh_sjlj_dispatchsetup + {2, OperandInfo44}, // Inst #273 = Int_eh_sjlj_longjmp + {2, OperandInfo44}, // Inst #274 = Int_eh_sjlj_setjmp + {2, OperandInfo44}, // Inst #275 = Int_eh_sjlj_setjmp_nofp + {0, NULL}, // Inst #276 = Int_eh_sjlj_setup_dispatch + {3, OperandInfo4}, // Inst #277 = JUMPTABLE_ADDRS + {3, OperandInfo4}, // Inst #278 = JUMPTABLE_INSTS + {3, OperandInfo4}, // Inst #279 = JUMPTABLE_TBB + {3, OperandInfo4}, // Inst #280 = JUMPTABLE_TBH + {5, OperandInfo65}, // Inst #281 = LDMIA_RET + {4, OperandInfo66}, // Inst #282 = LDRBT_POST + {4, OperandInfo67}, // Inst #283 = LDRConstPool + {4, OperandInfo66}, // Inst #284 = LDRHTii + {2, OperandInfo61}, // Inst #285 = LDRLIT_ga_abs + {2, OperandInfo61}, // Inst #286 = LDRLIT_ga_pcrel + {2, OperandInfo61}, // Inst #287 = LDRLIT_ga_pcrel_ldr + {4, OperandInfo66}, // Inst #288 = LDRSBTii + {4, OperandInfo66}, // Inst #289 = LDRSHTii + {4, OperandInfo66}, // Inst #290 = LDRT_POST + {4, OperandInfo68}, // Inst #291 = LEApcrel + {4, OperandInfo68}, // Inst #292 = LEApcrelJT + {4, OperandInfo69}, // Inst #293 = LOADDUAL + {6, OperandInfo50}, // Inst #294 = LSLi + {6, OperandInfo51}, // Inst #295 = LSLr + {6, OperandInfo50}, // Inst #296 = LSRi + {6, OperandInfo51}, // Inst #297 = LSRr + {5, OperandInfo70}, // Inst #298 = MEMCPY + {7, OperandInfo71}, // Inst #299 = MLAv5 + {5, OperandInfo72}, // Inst #300 = MOVCCi + {5, OperandInfo72}, // Inst #301 = MOVCCi16 + {5, OperandInfo73}, // Inst #302 = MOVCCi32imm + {5, OperandInfo74}, // Inst #303 = MOVCCr + {6, OperandInfo75}, // Inst #304 = MOVCCsi + {7, OperandInfo76}, // Inst #305 = MOVCCsr + {1, OperandInfo77}, // Inst #306 = MOVPCRX + {4, OperandInfo78}, // Inst #307 = MOVTi16_ga_pcrel + {2, OperandInfo61}, // Inst #308 = MOV_ga_pcrel + {2, OperandInfo61}, // Inst #309 = MOV_ga_pcrel_ldr + {3, OperandInfo79}, // Inst #310 = MOVi16_ga_pcrel + {2, OperandInfo61}, // Inst #311 = MOVi32imm + {2, OperandInfo44}, // Inst #312 = MOVsra_flag + {2, OperandInfo44}, // Inst #313 = MOVsrl_flag + {2, OperandInfo80}, // Inst #314 = MQPRCopy + {2, OperandInfo81}, // Inst #315 = MQQPRLoad + {2, OperandInfo81}, // Inst #316 = MQQPRStore + {2, OperandInfo82}, // Inst #317 = MQQQQPRLoad + {2, OperandInfo82}, // Inst #318 = MQQQQPRStore + {6, OperandInfo83}, // Inst #319 = MULv5 + {3, OperandInfo84}, // Inst #320 = MVE_MEMCPYLOOPINST + {3, OperandInfo85}, // Inst #321 = MVE_MEMSETLOOPINST + {5, OperandInfo72}, // Inst #322 = MVNCCi + {5, OperandInfo45}, // Inst #323 = PICADD + {5, OperandInfo86}, // Inst #324 = PICLDR + {5, OperandInfo86}, // Inst #325 = PICLDRB + {5, OperandInfo86}, // Inst #326 = PICLDRH + {5, OperandInfo86}, // Inst #327 = PICLDRSB + {5, OperandInfo86}, // Inst #328 = PICLDRSH + {5, OperandInfo86}, // Inst #329 = PICSTR + {5, OperandInfo86}, // Inst #330 = PICSTRB + {5, OperandInfo86}, // Inst #331 = PICSTRH + {6, OperandInfo50}, // Inst #332 = RORi + {6, OperandInfo51}, // Inst #333 = RORr + {2, OperandInfo44}, // Inst #334 = RRX + {5, OperandInfo87}, // Inst #335 = RRXi + {5, OperandInfo45}, // Inst #336 = RSBSri + {6, OperandInfo47}, // Inst #337 = RSBSrsi + {7, OperandInfo48}, // Inst #338 = RSBSrsr + {9, OperandInfo88}, // Inst #339 = SMLALv5 + {7, OperandInfo89}, // Inst #340 = SMULLv5 + {3, OperandInfo90}, // Inst #341 = SPACE + {4, OperandInfo69}, // Inst #342 = STOREDUAL + {4, OperandInfo66}, // Inst #343 = STRBT_POST + {7, OperandInfo91}, // Inst #344 = STRBi_preidx + {7, OperandInfo91}, // Inst #345 = STRBr_preidx + {7, OperandInfo92}, // Inst #346 = STRH_preidx + {4, OperandInfo66}, // Inst #347 = STRT_POST + {7, OperandInfo91}, // Inst #348 = STRi_preidx + {7, OperandInfo91}, // Inst #349 = STRr_preidx + {3, OperandInfo93}, // Inst #350 = SUBS_PC_LR + {5, OperandInfo45}, // Inst #351 = SUBSri + {5, OperandInfo46}, // Inst #352 = SUBSrr + {6, OperandInfo47}, // Inst #353 = SUBSrsi + {7, OperandInfo48}, // Inst #354 = SUBSrsr + {0, NULL}, // Inst #355 = SpeculationBarrierISBDSBEndBB + {0, NULL}, // Inst #356 = SpeculationBarrierSBEndBB + {1, OperandInfo52}, // Inst #357 = TAILJMPd + {1, OperandInfo94}, // Inst #358 = TAILJMPr + {1, OperandInfo77}, // Inst #359 = TAILJMPr4 + {2, OperandInfo10}, // Inst #360 = TCRETURNdi + {2, OperandInfo95}, // Inst #361 = TCRETURNri + {0, NULL}, // Inst #362 = TPsoft + {9, OperandInfo88}, // Inst #363 = UMLALv5 + {7, OperandInfo89}, // Inst #364 = UMULLv5 + {6, OperandInfo96}, // Inst #365 = VLD1LNdAsm_16 + {6, OperandInfo96}, // Inst #366 = VLD1LNdAsm_32 + {6, OperandInfo96}, // Inst #367 = VLD1LNdAsm_8 + {6, OperandInfo96}, // Inst #368 = VLD1LNdWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #369 = VLD1LNdWB_fixed_Asm_32 + {6, OperandInfo96}, // Inst #370 = VLD1LNdWB_fixed_Asm_8 + {7, OperandInfo97}, // Inst #371 = VLD1LNdWB_register_Asm_16 + {7, OperandInfo97}, // Inst #372 = VLD1LNdWB_register_Asm_32 + {7, OperandInfo97}, // Inst #373 = VLD1LNdWB_register_Asm_8 + {6, OperandInfo96}, // Inst #374 = VLD2LNdAsm_16 + {6, OperandInfo96}, // Inst #375 = VLD2LNdAsm_32 + {6, OperandInfo96}, // Inst #376 = VLD2LNdAsm_8 + {6, OperandInfo96}, // Inst #377 = VLD2LNdWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #378 = VLD2LNdWB_fixed_Asm_32 + {6, OperandInfo96}, // Inst #379 = VLD2LNdWB_fixed_Asm_8 + {7, OperandInfo97}, // Inst #380 = VLD2LNdWB_register_Asm_16 + {7, OperandInfo97}, // Inst #381 = VLD2LNdWB_register_Asm_32 + {7, OperandInfo97}, // Inst #382 = VLD2LNdWB_register_Asm_8 + {6, OperandInfo96}, // Inst #383 = VLD2LNqAsm_16 + {6, OperandInfo96}, // Inst #384 = VLD2LNqAsm_32 + {6, OperandInfo96}, // Inst #385 = VLD2LNqWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #386 = VLD2LNqWB_fixed_Asm_32 + {7, OperandInfo97}, // Inst #387 = VLD2LNqWB_register_Asm_16 + {7, OperandInfo97}, // Inst #388 = VLD2LNqWB_register_Asm_32 + {5, OperandInfo98}, // Inst #389 = VLD3DUPdAsm_16 + {5, OperandInfo98}, // Inst #390 = VLD3DUPdAsm_32 + {5, OperandInfo98}, // Inst #391 = VLD3DUPdAsm_8 + {5, OperandInfo98}, // Inst #392 = VLD3DUPdWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #393 = VLD3DUPdWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #394 = VLD3DUPdWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #395 = VLD3DUPdWB_register_Asm_16 + {6, OperandInfo99}, // Inst #396 = VLD3DUPdWB_register_Asm_32 + {6, OperandInfo99}, // Inst #397 = VLD3DUPdWB_register_Asm_8 + {5, OperandInfo98}, // Inst #398 = VLD3DUPqAsm_16 + {5, OperandInfo98}, // Inst #399 = VLD3DUPqAsm_32 + {5, OperandInfo98}, // Inst #400 = VLD3DUPqAsm_8 + {5, OperandInfo98}, // Inst #401 = VLD3DUPqWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #402 = VLD3DUPqWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #403 = VLD3DUPqWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #404 = VLD3DUPqWB_register_Asm_16 + {6, OperandInfo99}, // Inst #405 = VLD3DUPqWB_register_Asm_32 + {6, OperandInfo99}, // Inst #406 = VLD3DUPqWB_register_Asm_8 + {6, OperandInfo96}, // Inst #407 = VLD3LNdAsm_16 + {6, OperandInfo96}, // Inst #408 = VLD3LNdAsm_32 + {6, OperandInfo96}, // Inst #409 = VLD3LNdAsm_8 + {6, OperandInfo96}, // Inst #410 = VLD3LNdWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #411 = VLD3LNdWB_fixed_Asm_32 + {6, OperandInfo96}, // Inst #412 = VLD3LNdWB_fixed_Asm_8 + {7, OperandInfo97}, // Inst #413 = VLD3LNdWB_register_Asm_16 + {7, OperandInfo97}, // Inst #414 = VLD3LNdWB_register_Asm_32 + {7, OperandInfo97}, // Inst #415 = VLD3LNdWB_register_Asm_8 + {6, OperandInfo96}, // Inst #416 = VLD3LNqAsm_16 + {6, OperandInfo96}, // Inst #417 = VLD3LNqAsm_32 + {6, OperandInfo96}, // Inst #418 = VLD3LNqWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #419 = VLD3LNqWB_fixed_Asm_32 + {7, OperandInfo97}, // Inst #420 = VLD3LNqWB_register_Asm_16 + {7, OperandInfo97}, // Inst #421 = VLD3LNqWB_register_Asm_32 + {5, OperandInfo98}, // Inst #422 = VLD3dAsm_16 + {5, OperandInfo98}, // Inst #423 = VLD3dAsm_32 + {5, OperandInfo98}, // Inst #424 = VLD3dAsm_8 + {5, OperandInfo98}, // Inst #425 = VLD3dWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #426 = VLD3dWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #427 = VLD3dWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #428 = VLD3dWB_register_Asm_16 + {6, OperandInfo99}, // Inst #429 = VLD3dWB_register_Asm_32 + {6, OperandInfo99}, // Inst #430 = VLD3dWB_register_Asm_8 + {5, OperandInfo98}, // Inst #431 = VLD3qAsm_16 + {5, OperandInfo98}, // Inst #432 = VLD3qAsm_32 + {5, OperandInfo98}, // Inst #433 = VLD3qAsm_8 + {5, OperandInfo98}, // Inst #434 = VLD3qWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #435 = VLD3qWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #436 = VLD3qWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #437 = VLD3qWB_register_Asm_16 + {6, OperandInfo99}, // Inst #438 = VLD3qWB_register_Asm_32 + {6, OperandInfo99}, // Inst #439 = VLD3qWB_register_Asm_8 + {5, OperandInfo98}, // Inst #440 = VLD4DUPdAsm_16 + {5, OperandInfo98}, // Inst #441 = VLD4DUPdAsm_32 + {5, OperandInfo98}, // Inst #442 = VLD4DUPdAsm_8 + {5, OperandInfo98}, // Inst #443 = VLD4DUPdWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #444 = VLD4DUPdWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #445 = VLD4DUPdWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #446 = VLD4DUPdWB_register_Asm_16 + {6, OperandInfo99}, // Inst #447 = VLD4DUPdWB_register_Asm_32 + {6, OperandInfo99}, // Inst #448 = VLD4DUPdWB_register_Asm_8 + {5, OperandInfo98}, // Inst #449 = VLD4DUPqAsm_16 + {5, OperandInfo98}, // Inst #450 = VLD4DUPqAsm_32 + {5, OperandInfo98}, // Inst #451 = VLD4DUPqAsm_8 + {5, OperandInfo98}, // Inst #452 = VLD4DUPqWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #453 = VLD4DUPqWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #454 = VLD4DUPqWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #455 = VLD4DUPqWB_register_Asm_16 + {6, OperandInfo99}, // Inst #456 = VLD4DUPqWB_register_Asm_32 + {6, OperandInfo99}, // Inst #457 = VLD4DUPqWB_register_Asm_8 + {6, OperandInfo96}, // Inst #458 = VLD4LNdAsm_16 + {6, OperandInfo96}, // Inst #459 = VLD4LNdAsm_32 + {6, OperandInfo96}, // Inst #460 = VLD4LNdAsm_8 + {6, OperandInfo96}, // Inst #461 = VLD4LNdWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #462 = VLD4LNdWB_fixed_Asm_32 + {6, OperandInfo96}, // Inst #463 = VLD4LNdWB_fixed_Asm_8 + {7, OperandInfo97}, // Inst #464 = VLD4LNdWB_register_Asm_16 + {7, OperandInfo97}, // Inst #465 = VLD4LNdWB_register_Asm_32 + {7, OperandInfo97}, // Inst #466 = VLD4LNdWB_register_Asm_8 + {6, OperandInfo96}, // Inst #467 = VLD4LNqAsm_16 + {6, OperandInfo96}, // Inst #468 = VLD4LNqAsm_32 + {6, OperandInfo96}, // Inst #469 = VLD4LNqWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #470 = VLD4LNqWB_fixed_Asm_32 + {7, OperandInfo97}, // Inst #471 = VLD4LNqWB_register_Asm_16 + {7, OperandInfo97}, // Inst #472 = VLD4LNqWB_register_Asm_32 + {5, OperandInfo98}, // Inst #473 = VLD4dAsm_16 + {5, OperandInfo98}, // Inst #474 = VLD4dAsm_32 + {5, OperandInfo98}, // Inst #475 = VLD4dAsm_8 + {5, OperandInfo98}, // Inst #476 = VLD4dWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #477 = VLD4dWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #478 = VLD4dWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #479 = VLD4dWB_register_Asm_16 + {6, OperandInfo99}, // Inst #480 = VLD4dWB_register_Asm_32 + {6, OperandInfo99}, // Inst #481 = VLD4dWB_register_Asm_8 + {5, OperandInfo98}, // Inst #482 = VLD4qAsm_16 + {5, OperandInfo98}, // Inst #483 = VLD4qAsm_32 + {5, OperandInfo98}, // Inst #484 = VLD4qAsm_8 + {5, OperandInfo98}, // Inst #485 = VLD4qWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #486 = VLD4qWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #487 = VLD4qWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #488 = VLD4qWB_register_Asm_16 + {6, OperandInfo99}, // Inst #489 = VLD4qWB_register_Asm_32 + {6, OperandInfo99}, // Inst #490 = VLD4qWB_register_Asm_8 + {1, OperandInfo100}, // Inst #491 = VMOVD0 + {5, OperandInfo101}, // Inst #492 = VMOVDcc + {5, OperandInfo102}, // Inst #493 = VMOVHcc + {1, OperandInfo103}, // Inst #494 = VMOVQ0 + {5, OperandInfo104}, // Inst #495 = VMOVScc + {6, OperandInfo96}, // Inst #496 = VST1LNdAsm_16 + {6, OperandInfo96}, // Inst #497 = VST1LNdAsm_32 + {6, OperandInfo96}, // Inst #498 = VST1LNdAsm_8 + {6, OperandInfo96}, // Inst #499 = VST1LNdWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #500 = VST1LNdWB_fixed_Asm_32 + {6, OperandInfo96}, // Inst #501 = VST1LNdWB_fixed_Asm_8 + {7, OperandInfo97}, // Inst #502 = VST1LNdWB_register_Asm_16 + {7, OperandInfo97}, // Inst #503 = VST1LNdWB_register_Asm_32 + {7, OperandInfo97}, // Inst #504 = VST1LNdWB_register_Asm_8 + {6, OperandInfo96}, // Inst #505 = VST2LNdAsm_16 + {6, OperandInfo96}, // Inst #506 = VST2LNdAsm_32 + {6, OperandInfo96}, // Inst #507 = VST2LNdAsm_8 + {6, OperandInfo96}, // Inst #508 = VST2LNdWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #509 = VST2LNdWB_fixed_Asm_32 + {6, OperandInfo96}, // Inst #510 = VST2LNdWB_fixed_Asm_8 + {7, OperandInfo97}, // Inst #511 = VST2LNdWB_register_Asm_16 + {7, OperandInfo97}, // Inst #512 = VST2LNdWB_register_Asm_32 + {7, OperandInfo97}, // Inst #513 = VST2LNdWB_register_Asm_8 + {6, OperandInfo96}, // Inst #514 = VST2LNqAsm_16 + {6, OperandInfo96}, // Inst #515 = VST2LNqAsm_32 + {6, OperandInfo96}, // Inst #516 = VST2LNqWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #517 = VST2LNqWB_fixed_Asm_32 + {7, OperandInfo97}, // Inst #518 = VST2LNqWB_register_Asm_16 + {7, OperandInfo97}, // Inst #519 = VST2LNqWB_register_Asm_32 + {6, OperandInfo96}, // Inst #520 = VST3LNdAsm_16 + {6, OperandInfo96}, // Inst #521 = VST3LNdAsm_32 + {6, OperandInfo96}, // Inst #522 = VST3LNdAsm_8 + {6, OperandInfo96}, // Inst #523 = VST3LNdWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #524 = VST3LNdWB_fixed_Asm_32 + {6, OperandInfo96}, // Inst #525 = VST3LNdWB_fixed_Asm_8 + {7, OperandInfo97}, // Inst #526 = VST3LNdWB_register_Asm_16 + {7, OperandInfo97}, // Inst #527 = VST3LNdWB_register_Asm_32 + {7, OperandInfo97}, // Inst #528 = VST3LNdWB_register_Asm_8 + {6, OperandInfo96}, // Inst #529 = VST3LNqAsm_16 + {6, OperandInfo96}, // Inst #530 = VST3LNqAsm_32 + {6, OperandInfo96}, // Inst #531 = VST3LNqWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #532 = VST3LNqWB_fixed_Asm_32 + {7, OperandInfo97}, // Inst #533 = VST3LNqWB_register_Asm_16 + {7, OperandInfo97}, // Inst #534 = VST3LNqWB_register_Asm_32 + {5, OperandInfo98}, // Inst #535 = VST3dAsm_16 + {5, OperandInfo98}, // Inst #536 = VST3dAsm_32 + {5, OperandInfo98}, // Inst #537 = VST3dAsm_8 + {5, OperandInfo98}, // Inst #538 = VST3dWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #539 = VST3dWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #540 = VST3dWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #541 = VST3dWB_register_Asm_16 + {6, OperandInfo99}, // Inst #542 = VST3dWB_register_Asm_32 + {6, OperandInfo99}, // Inst #543 = VST3dWB_register_Asm_8 + {5, OperandInfo98}, // Inst #544 = VST3qAsm_16 + {5, OperandInfo98}, // Inst #545 = VST3qAsm_32 + {5, OperandInfo98}, // Inst #546 = VST3qAsm_8 + {5, OperandInfo98}, // Inst #547 = VST3qWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #548 = VST3qWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #549 = VST3qWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #550 = VST3qWB_register_Asm_16 + {6, OperandInfo99}, // Inst #551 = VST3qWB_register_Asm_32 + {6, OperandInfo99}, // Inst #552 = VST3qWB_register_Asm_8 + {6, OperandInfo96}, // Inst #553 = VST4LNdAsm_16 + {6, OperandInfo96}, // Inst #554 = VST4LNdAsm_32 + {6, OperandInfo96}, // Inst #555 = VST4LNdAsm_8 + {6, OperandInfo96}, // Inst #556 = VST4LNdWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #557 = VST4LNdWB_fixed_Asm_32 + {6, OperandInfo96}, // Inst #558 = VST4LNdWB_fixed_Asm_8 + {7, OperandInfo97}, // Inst #559 = VST4LNdWB_register_Asm_16 + {7, OperandInfo97}, // Inst #560 = VST4LNdWB_register_Asm_32 + {7, OperandInfo97}, // Inst #561 = VST4LNdWB_register_Asm_8 + {6, OperandInfo96}, // Inst #562 = VST4LNqAsm_16 + {6, OperandInfo96}, // Inst #563 = VST4LNqAsm_32 + {6, OperandInfo96}, // Inst #564 = VST4LNqWB_fixed_Asm_16 + {6, OperandInfo96}, // Inst #565 = VST4LNqWB_fixed_Asm_32 + {7, OperandInfo97}, // Inst #566 = VST4LNqWB_register_Asm_16 + {7, OperandInfo97}, // Inst #567 = VST4LNqWB_register_Asm_32 + {5, OperandInfo98}, // Inst #568 = VST4dAsm_16 + {5, OperandInfo98}, // Inst #569 = VST4dAsm_32 + {5, OperandInfo98}, // Inst #570 = VST4dAsm_8 + {5, OperandInfo98}, // Inst #571 = VST4dWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #572 = VST4dWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #573 = VST4dWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #574 = VST4dWB_register_Asm_16 + {6, OperandInfo99}, // Inst #575 = VST4dWB_register_Asm_32 + {6, OperandInfo99}, // Inst #576 = VST4dWB_register_Asm_8 + {5, OperandInfo98}, // Inst #577 = VST4qAsm_16 + {5, OperandInfo98}, // Inst #578 = VST4qAsm_32 + {5, OperandInfo98}, // Inst #579 = VST4qAsm_8 + {5, OperandInfo98}, // Inst #580 = VST4qWB_fixed_Asm_16 + {5, OperandInfo98}, // Inst #581 = VST4qWB_fixed_Asm_32 + {5, OperandInfo98}, // Inst #582 = VST4qWB_fixed_Asm_8 + {6, OperandInfo99}, // Inst #583 = VST4qWB_register_Asm_16 + {6, OperandInfo99}, // Inst #584 = VST4qWB_register_Asm_32 + {6, OperandInfo99}, // Inst #585 = VST4qWB_register_Asm_8 + {0, NULL}, // Inst #586 = WIN__CHKSTK + {1, OperandInfo57}, // Inst #587 = WIN__DBZCHK + {2, OperandInfo105}, // Inst #588 = t2ABS + {5, OperandInfo106}, // Inst #589 = t2ADDSri + {5, OperandInfo107}, // Inst #590 = t2ADDSrr + {6, OperandInfo108}, // Inst #591 = t2ADDSrs + {1, OperandInfo2}, // Inst #592 = t2BF_LabelPseudo + {3, OperandInfo58}, // Inst #593 = t2BR_JT + {2, OperandInfo109}, // Inst #594 = t2DoLoopStart + {3, OperandInfo110}, // Inst #595 = t2DoLoopStartTP + {5, OperandInfo65}, // Inst #596 = t2LDMIA_RET + {4, OperandInfo111}, // Inst #597 = t2LDRBpcrel + {4, OperandInfo67}, // Inst #598 = t2LDRConstPool + {4, OperandInfo111}, // Inst #599 = t2LDRHpcrel + {4, OperandInfo111}, // Inst #600 = t2LDRSBpcrel + {4, OperandInfo111}, // Inst #601 = t2LDRSHpcrel + {5, OperandInfo86}, // Inst #602 = t2LDR_POST_imm + {5, OperandInfo86}, // Inst #603 = t2LDR_PRE_imm + {3, OperandInfo112}, // Inst #604 = t2LDRpci_pic + {4, OperandInfo67}, // Inst #605 = t2LDRpcrel + {4, OperandInfo113}, // Inst #606 = t2LEApcrel + {4, OperandInfo113}, // Inst #607 = t2LEApcrelJT + {3, OperandInfo114}, // Inst #608 = t2LoopDec + {2, OperandInfo56}, // Inst #609 = t2LoopEnd + {3, OperandInfo115}, // Inst #610 = t2LoopEndDec + {6, OperandInfo116}, // Inst #611 = t2MOVCCasr + {5, OperandInfo117}, // Inst #612 = t2MOVCCi + {5, OperandInfo117}, // Inst #613 = t2MOVCCi16 + {5, OperandInfo118}, // Inst #614 = t2MOVCCi32imm + {6, OperandInfo116}, // Inst #615 = t2MOVCClsl + {6, OperandInfo116}, // Inst #616 = t2MOVCClsr + {5, OperandInfo119}, // Inst #617 = t2MOVCCr + {6, OperandInfo116}, // Inst #618 = t2MOVCCror + {5, OperandInfo120}, // Inst #619 = t2MOVSsi + {6, OperandInfo121}, // Inst #620 = t2MOVSsr + {4, OperandInfo122}, // Inst #621 = t2MOVTi16_ga_pcrel + {2, OperandInfo123}, // Inst #622 = t2MOV_ga_pcrel + {3, OperandInfo112}, // Inst #623 = t2MOVi16_ga_pcrel + {2, OperandInfo123}, // Inst #624 = t2MOVi32imm + {5, OperandInfo120}, // Inst #625 = t2MOVsi + {6, OperandInfo121}, // Inst #626 = t2MOVsr + {5, OperandInfo117}, // Inst #627 = t2MVNCCi + {5, OperandInfo124}, // Inst #628 = t2RSBSri + {6, OperandInfo125}, // Inst #629 = t2RSBSrs + {6, OperandInfo126}, // Inst #630 = t2STRB_preidx + {6, OperandInfo126}, // Inst #631 = t2STRH_preidx + {5, OperandInfo86}, // Inst #632 = t2STR_POST_imm + {5, OperandInfo86}, // Inst #633 = t2STR_PRE_imm + {6, OperandInfo126}, // Inst #634 = t2STR_preidx + {5, OperandInfo106}, // Inst #635 = t2SUBSri + {5, OperandInfo107}, // Inst #636 = t2SUBSrr + {6, OperandInfo108}, // Inst #637 = t2SUBSrs + {0, NULL}, // Inst #638 = t2SpeculationBarrierISBDSBEndBB + {0, NULL}, // Inst #639 = t2SpeculationBarrierSBEndBB + {4, OperandInfo64}, // Inst #640 = t2TBB_JT + {4, OperandInfo64}, // Inst #641 = t2TBH_JT + {2, OperandInfo109}, // Inst #642 = t2WhileLoopSetup + {2, OperandInfo56}, // Inst #643 = t2WhileLoopStart + {3, OperandInfo127}, // Inst #644 = t2WhileLoopStartLR + {4, OperandInfo128}, // Inst #645 = t2WhileLoopStartTP + {3, OperandInfo129}, // Inst #646 = tADCS + {3, OperandInfo130}, // Inst #647 = tADDSi3 + {3, OperandInfo130}, // Inst #648 = tADDSi8 + {3, OperandInfo129}, // Inst #649 = tADDSrr + {3, OperandInfo131}, // Inst #650 = tADDframe + {2, OperandInfo10}, // Inst #651 = tADJCALLSTACKDOWN + {2, OperandInfo10}, // Inst #652 = tADJCALLSTACKUP + {1, OperandInfo132}, // Inst #653 = tBLXNS_CALL + {3, OperandInfo133}, // Inst #654 = tBLXr_noip + {4, OperandInfo134}, // Inst #655 = tBL_PUSHLR + {3, OperandInfo135}, // Inst #656 = tBRIND + {2, OperandInfo136}, // Inst #657 = tBR_JTr + {0, NULL}, // Inst #658 = tBXNS_RET + {1, OperandInfo57}, // Inst #659 = tBX_CALL + {2, OperandInfo137}, // Inst #660 = tBX_RET + {3, OperandInfo138}, // Inst #661 = tBX_RET_vararg + {3, OperandInfo139}, // Inst #662 = tBfar + {5, OperandInfo140}, // Inst #663 = tCMP_SWAP_16 + {5, OperandInfo140}, // Inst #664 = tCMP_SWAP_8 + {5, OperandInfo141}, // Inst #665 = tLDMIA_UPD + {4, OperandInfo142}, // Inst #666 = tLDRConstPool + {2, OperandInfo136}, // Inst #667 = tLDRLIT_ga_abs + {2, OperandInfo136}, // Inst #668 = tLDRLIT_ga_pcrel + {5, OperandInfo143}, // Inst #669 = tLDR_postidx + {3, OperandInfo144}, // Inst #670 = tLDRpci_pic + {4, OperandInfo145}, // Inst #671 = tLEApcrel + {4, OperandInfo145}, // Inst #672 = tLEApcrelJT + {3, OperandInfo130}, // Inst #673 = tLSLSri + {5, OperandInfo146}, // Inst #674 = tMOVCCr_pseudo + {3, OperandInfo147}, // Inst #675 = tPOP_RET + {2, OperandInfo148}, // Inst #676 = tRSBS + {3, OperandInfo129}, // Inst #677 = tSBCS + {3, OperandInfo130}, // Inst #678 = tSUBSi3 + {3, OperandInfo130}, // Inst #679 = tSUBSi8 + {3, OperandInfo129}, // Inst #680 = tSUBSrr + {3, OperandInfo139}, // Inst #681 = tTAILJMPd + {3, OperandInfo139}, // Inst #682 = tTAILJMPdND + {1, OperandInfo94}, // Inst #683 = tTAILJMPr + {4, OperandInfo149}, // Inst #684 = tTBB_JT + {4, OperandInfo149}, // Inst #685 = tTBH_JT + {0, NULL}, // Inst #686 = tTPsoft + {6, OperandInfo50}, // Inst #687 = ADCri + {6, OperandInfo150}, // Inst #688 = ADCrr + {7, OperandInfo151}, // Inst #689 = ADCrsi + {8, OperandInfo152}, // Inst #690 = ADCrsr + {6, OperandInfo50}, // Inst #691 = ADDri + {6, OperandInfo150}, // Inst #692 = ADDrr + {7, OperandInfo151}, // Inst #693 = ADDrsi + {8, OperandInfo153}, // Inst #694 = ADDrsr + {4, OperandInfo67}, // Inst #695 = ADR + {3, OperandInfo154}, // Inst #696 = AESD + {3, OperandInfo154}, // Inst #697 = AESE + {2, OperandInfo155}, // Inst #698 = AESIMC + {2, OperandInfo155}, // Inst #699 = AESMC + {6, OperandInfo50}, // Inst #700 = ANDri + {6, OperandInfo150}, // Inst #701 = ANDrr + {7, OperandInfo151}, // Inst #702 = ANDrsi + {8, OperandInfo153}, // Inst #703 = ANDrsr + {5, OperandInfo156}, // Inst #704 = BF16VDOTI_VDOTD + {5, OperandInfo157}, // Inst #705 = BF16VDOTI_VDOTQ + {4, OperandInfo158}, // Inst #706 = BF16VDOTS_VDOTD + {4, OperandInfo159}, // Inst #707 = BF16VDOTS_VDOTQ + {4, OperandInfo160}, // Inst #708 = BF16_VCVT + {5, OperandInfo104}, // Inst #709 = BF16_VCVTB + {5, OperandInfo104}, // Inst #710 = BF16_VCVTT + {5, OperandInfo72}, // Inst #711 = BFC + {6, OperandInfo161}, // Inst #712 = BFI + {6, OperandInfo50}, // Inst #713 = BICri + {6, OperandInfo150}, // Inst #714 = BICrr + {7, OperandInfo151}, // Inst #715 = BICrsi + {8, OperandInfo153}, // Inst #716 = BICrsr + {1, OperandInfo2}, // Inst #717 = BKPT + {1, OperandInfo52}, // Inst #718 = BL + {1, OperandInfo77}, // Inst #719 = BLX + {3, OperandInfo135}, // Inst #720 = BLX_pred + {1, OperandInfo52}, // Inst #721 = BLXi + {3, OperandInfo139}, // Inst #722 = BL_pred + {1, OperandInfo77}, // Inst #723 = BX + {3, OperandInfo135}, // Inst #724 = BXJ + {2, OperandInfo137}, // Inst #725 = BX_RET + {3, OperandInfo135}, // Inst #726 = BX_pred + {3, OperandInfo139}, // Inst #727 = Bcc + {3, OperandInfo162}, // Inst #728 = CDE_CX1 + {6, OperandInfo163}, // Inst #729 = CDE_CX1A + {3, OperandInfo164}, // Inst #730 = CDE_CX1D + {6, OperandInfo165}, // Inst #731 = CDE_CX1DA + {4, OperandInfo166}, // Inst #732 = CDE_CX2 + {7, OperandInfo167}, // Inst #733 = CDE_CX2A + {4, OperandInfo168}, // Inst #734 = CDE_CX2D + {7, OperandInfo169}, // Inst #735 = CDE_CX2DA + {5, OperandInfo170}, // Inst #736 = CDE_CX3 + {8, OperandInfo171}, // Inst #737 = CDE_CX3A + {5, OperandInfo172}, // Inst #738 = CDE_CX3D + {8, OperandInfo173}, // Inst #739 = CDE_CX3DA + {4, OperandInfo174}, // Inst #740 = CDE_VCX1A_fpdp + {4, OperandInfo175}, // Inst #741 = CDE_VCX1A_fpsp + {7, OperandInfo176}, // Inst #742 = CDE_VCX1A_vec + {3, OperandInfo177}, // Inst #743 = CDE_VCX1_fpdp + {3, OperandInfo178}, // Inst #744 = CDE_VCX1_fpsp + {7, OperandInfo179}, // Inst #745 = CDE_VCX1_vec + {5, OperandInfo180}, // Inst #746 = CDE_VCX2A_fpdp + {5, OperandInfo181}, // Inst #747 = CDE_VCX2A_fpsp + {8, OperandInfo182}, // Inst #748 = CDE_VCX2A_vec + {4, OperandInfo183}, // Inst #749 = CDE_VCX2_fpdp + {4, OperandInfo184}, // Inst #750 = CDE_VCX2_fpsp + {8, OperandInfo185}, // Inst #751 = CDE_VCX2_vec + {6, OperandInfo186}, // Inst #752 = CDE_VCX3A_fpdp + {6, OperandInfo187}, // Inst #753 = CDE_VCX3A_fpsp + {9, OperandInfo188}, // Inst #754 = CDE_VCX3A_vec + {5, OperandInfo189}, // Inst #755 = CDE_VCX3_fpdp + {5, OperandInfo190}, // Inst #756 = CDE_VCX3_fpsp + {9, OperandInfo191}, // Inst #757 = CDE_VCX3_vec + {8, OperandInfo192}, // Inst #758 = CDP + {6, OperandInfo193}, // Inst #759 = CDP2 + {0, NULL}, // Inst #760 = CLREX + {4, OperandInfo194}, // Inst #761 = CLZ + {4, OperandInfo67}, // Inst #762 = CMNri + {4, OperandInfo194}, // Inst #763 = CMNzrr + {5, OperandInfo195}, // Inst #764 = CMNzrsi + {6, OperandInfo196}, // Inst #765 = CMNzrsr + {4, OperandInfo67}, // Inst #766 = CMPri + {4, OperandInfo194}, // Inst #767 = CMPrr + {5, OperandInfo195}, // Inst #768 = CMPrsi + {6, OperandInfo196}, // Inst #769 = CMPrsr + {1, OperandInfo2}, // Inst #770 = CPS1p + {2, OperandInfo7}, // Inst #771 = CPS2p + {3, OperandInfo197}, // Inst #772 = CPS3p + {3, OperandInfo198}, // Inst #773 = CRC32B + {3, OperandInfo198}, // Inst #774 = CRC32CB + {3, OperandInfo198}, // Inst #775 = CRC32CH + {3, OperandInfo198}, // Inst #776 = CRC32CW + {3, OperandInfo198}, // Inst #777 = CRC32H + {3, OperandInfo198}, // Inst #778 = CRC32W + {3, OperandInfo199}, // Inst #779 = DBG + {1, OperandInfo2}, // Inst #780 = DMB + {1, OperandInfo2}, // Inst #781 = DSB + {6, OperandInfo50}, // Inst #782 = EORri + {6, OperandInfo150}, // Inst #783 = EORrr + {7, OperandInfo151}, // Inst #784 = EORrsi + {8, OperandInfo153}, // Inst #785 = EORrsr + {2, OperandInfo137}, // Inst #786 = ERET + {4, OperandInfo200}, // Inst #787 = FCONSTD + {4, OperandInfo201}, // Inst #788 = FCONSTH + {4, OperandInfo202}, // Inst #789 = FCONSTS + {5, OperandInfo65}, // Inst #790 = FLDMXDB_UPD + {4, OperandInfo203}, // Inst #791 = FLDMXIA + {5, OperandInfo65}, // Inst #792 = FLDMXIA_UPD + {2, OperandInfo137}, // Inst #793 = FMSTAT + {5, OperandInfo65}, // Inst #794 = FSTMXDB_UPD + {4, OperandInfo203}, // Inst #795 = FSTMXIA + {5, OperandInfo65}, // Inst #796 = FSTMXIA_UPD + {3, OperandInfo199}, // Inst #797 = HINT + {1, OperandInfo2}, // Inst #798 = HLT + {1, OperandInfo2}, // Inst #799 = HVC + {1, OperandInfo2}, // Inst #800 = ISB + {4, OperandInfo66}, // Inst #801 = LDA + {4, OperandInfo66}, // Inst #802 = LDAB + {4, OperandInfo66}, // Inst #803 = LDAEX + {4, OperandInfo66}, // Inst #804 = LDAEXB + {4, OperandInfo204}, // Inst #805 = LDAEXD + {4, OperandInfo66}, // Inst #806 = LDAEXH + {4, OperandInfo66}, // Inst #807 = LDAH + {4, OperandInfo205}, // Inst #808 = LDC2L_OFFSET + {4, OperandInfo206}, // Inst #809 = LDC2L_OPTION + {4, OperandInfo205}, // Inst #810 = LDC2L_POST + {4, OperandInfo205}, // Inst #811 = LDC2L_PRE + {4, OperandInfo205}, // Inst #812 = LDC2_OFFSET + {4, OperandInfo206}, // Inst #813 = LDC2_OPTION + {4, OperandInfo205}, // Inst #814 = LDC2_POST + {4, OperandInfo205}, // Inst #815 = LDC2_PRE + {6, OperandInfo207}, // Inst #816 = LDCL_OFFSET + {6, OperandInfo208}, // Inst #817 = LDCL_OPTION + {6, OperandInfo207}, // Inst #818 = LDCL_POST + {6, OperandInfo207}, // Inst #819 = LDCL_PRE + {6, OperandInfo207}, // Inst #820 = LDC_OFFSET + {6, OperandInfo208}, // Inst #821 = LDC_OPTION + {6, OperandInfo207}, // Inst #822 = LDC_POST + {6, OperandInfo207}, // Inst #823 = LDC_PRE + {4, OperandInfo203}, // Inst #824 = LDMDA + {5, OperandInfo65}, // Inst #825 = LDMDA_UPD + {4, OperandInfo203}, // Inst #826 = LDMDB + {5, OperandInfo65}, // Inst #827 = LDMDB_UPD + {4, OperandInfo203}, // Inst #828 = LDMIA + {5, OperandInfo65}, // Inst #829 = LDMIA_UPD + {4, OperandInfo203}, // Inst #830 = LDMIB + {5, OperandInfo65}, // Inst #831 = LDMIB_UPD + {7, OperandInfo209}, // Inst #832 = LDRBT_POST_IMM + {7, OperandInfo209}, // Inst #833 = LDRBT_POST_REG + {7, OperandInfo209}, // Inst #834 = LDRB_POST_IMM + {7, OperandInfo209}, // Inst #835 = LDRB_POST_REG + {6, OperandInfo210}, // Inst #836 = LDRB_PRE_IMM + {7, OperandInfo209}, // Inst #837 = LDRB_PRE_REG + {5, OperandInfo211}, // Inst #838 = LDRBi12 + {6, OperandInfo212}, // Inst #839 = LDRBrs + {7, OperandInfo213}, // Inst #840 = LDRD + {8, OperandInfo214}, // Inst #841 = LDRD_POST + {8, OperandInfo214}, // Inst #842 = LDRD_PRE + {4, OperandInfo66}, // Inst #843 = LDREX + {4, OperandInfo66}, // Inst #844 = LDREXB + {4, OperandInfo204}, // Inst #845 = LDREXD + {4, OperandInfo66}, // Inst #846 = LDREXH + {6, OperandInfo215}, // Inst #847 = LDRH + {6, OperandInfo210}, // Inst #848 = LDRHTi + {7, OperandInfo216}, // Inst #849 = LDRHTr + {7, OperandInfo217}, // Inst #850 = LDRH_POST + {7, OperandInfo217}, // Inst #851 = LDRH_PRE + {6, OperandInfo215}, // Inst #852 = LDRSB + {6, OperandInfo210}, // Inst #853 = LDRSBTi + {7, OperandInfo216}, // Inst #854 = LDRSBTr + {7, OperandInfo217}, // Inst #855 = LDRSB_POST + {7, OperandInfo217}, // Inst #856 = LDRSB_PRE + {6, OperandInfo215}, // Inst #857 = LDRSH + {6, OperandInfo210}, // Inst #858 = LDRSHTi + {7, OperandInfo216}, // Inst #859 = LDRSHTr + {7, OperandInfo217}, // Inst #860 = LDRSH_POST + {7, OperandInfo217}, // Inst #861 = LDRSH_PRE + {7, OperandInfo209}, // Inst #862 = LDRT_POST_IMM + {7, OperandInfo209}, // Inst #863 = LDRT_POST_REG + {7, OperandInfo209}, // Inst #864 = LDR_POST_IMM + {7, OperandInfo209}, // Inst #865 = LDR_POST_REG + {6, OperandInfo210}, // Inst #866 = LDR_PRE_IMM + {7, OperandInfo209}, // Inst #867 = LDR_PRE_REG + {5, OperandInfo86}, // Inst #868 = LDRcp + {5, OperandInfo86}, // Inst #869 = LDRi12 + {6, OperandInfo218}, // Inst #870 = LDRrs + {8, OperandInfo219}, // Inst #871 = MCR + {6, OperandInfo220}, // Inst #872 = MCR2 + {7, OperandInfo221}, // Inst #873 = MCRR + {5, OperandInfo222}, // Inst #874 = MCRR2 + {7, OperandInfo223}, // Inst #875 = MLA + {6, OperandInfo224}, // Inst #876 = MLS + {2, OperandInfo137}, // Inst #877 = MOVPCLR + {5, OperandInfo225}, // Inst #878 = MOVTi16 + {5, OperandInfo226}, // Inst #879 = MOVi + {4, OperandInfo67}, // Inst #880 = MOVi16 + {5, OperandInfo87}, // Inst #881 = MOVr + {5, OperandInfo227}, // Inst #882 = MOVr_TC + {6, OperandInfo228}, // Inst #883 = MOVsi + {7, OperandInfo229}, // Inst #884 = MOVsr + {8, OperandInfo230}, // Inst #885 = MRC + {6, OperandInfo231}, // Inst #886 = MRC2 + {7, OperandInfo232}, // Inst #887 = MRRC + {5, OperandInfo233}, // Inst #888 = MRRC2 + {3, OperandInfo234}, // Inst #889 = MRS + {4, OperandInfo111}, // Inst #890 = MRSbanked + {3, OperandInfo234}, // Inst #891 = MRSsys + {4, OperandInfo235}, // Inst #892 = MSR + {4, OperandInfo236}, // Inst #893 = MSRbanked + {4, OperandInfo237}, // Inst #894 = MSRi + {6, OperandInfo51}, // Inst #895 = MUL + {7, OperandInfo238}, // Inst #896 = MVE_ASRLi + {7, OperandInfo239}, // Inst #897 = MVE_ASRLr + {2, OperandInfo109}, // Inst #898 = MVE_DLSTP_16 + {2, OperandInfo109}, // Inst #899 = MVE_DLSTP_32 + {2, OperandInfo109}, // Inst #900 = MVE_DLSTP_64 + {2, OperandInfo109}, // Inst #901 = MVE_DLSTP_8 + {2, OperandInfo137}, // Inst #902 = MVE_LCTP + {3, OperandInfo115}, // Inst #903 = MVE_LETP + {7, OperandInfo238}, // Inst #904 = MVE_LSLLi + {7, OperandInfo239}, // Inst #905 = MVE_LSLLr + {7, OperandInfo238}, // Inst #906 = MVE_LSRL + {5, OperandInfo119}, // Inst #907 = MVE_SQRSHR + {8, OperandInfo240}, // Inst #908 = MVE_SQRSHRL + {5, OperandInfo117}, // Inst #909 = MVE_SQSHL + {7, OperandInfo238}, // Inst #910 = MVE_SQSHLL + {5, OperandInfo117}, // Inst #911 = MVE_SRSHR + {7, OperandInfo238}, // Inst #912 = MVE_SRSHRL + {5, OperandInfo119}, // Inst #913 = MVE_UQRSHL + {8, OperandInfo240}, // Inst #914 = MVE_UQRSHLL + {5, OperandInfo117}, // Inst #915 = MVE_UQSHL + {7, OperandInfo238}, // Inst #916 = MVE_UQSHLL + {5, OperandInfo117}, // Inst #917 = MVE_URSHR + {7, OperandInfo238}, // Inst #918 = MVE_URSHRL + {7, OperandInfo241}, // Inst #919 = MVE_VABAVs16 + {7, OperandInfo241}, // Inst #920 = MVE_VABAVs32 + {7, OperandInfo241}, // Inst #921 = MVE_VABAVs8 + {7, OperandInfo241}, // Inst #922 = MVE_VABAVu16 + {7, OperandInfo241}, // Inst #923 = MVE_VABAVu32 + {7, OperandInfo241}, // Inst #924 = MVE_VABAVu8 + {7, OperandInfo242}, // Inst #925 = MVE_VABDf16 + {7, OperandInfo242}, // Inst #926 = MVE_VABDf32 + {7, OperandInfo242}, // Inst #927 = MVE_VABDs16 + {7, OperandInfo242}, // Inst #928 = MVE_VABDs32 + {7, OperandInfo242}, // Inst #929 = MVE_VABDs8 + {7, OperandInfo242}, // Inst #930 = MVE_VABDu16 + {7, OperandInfo242}, // Inst #931 = MVE_VABDu32 + {7, OperandInfo242}, // Inst #932 = MVE_VABDu8 + {6, OperandInfo243}, // Inst #933 = MVE_VABSf16 + {6, OperandInfo243}, // Inst #934 = MVE_VABSf32 + {6, OperandInfo243}, // Inst #935 = MVE_VABSs16 + {6, OperandInfo243}, // Inst #936 = MVE_VABSs32 + {6, OperandInfo243}, // Inst #937 = MVE_VABSs8 + {9, OperandInfo244}, // Inst #938 = MVE_VADC + {8, OperandInfo245}, // Inst #939 = MVE_VADCI + {8, OperandInfo246}, // Inst #940 = MVE_VADDLVs32acc + {6, OperandInfo247}, // Inst #941 = MVE_VADDLVs32no_acc + {8, OperandInfo246}, // Inst #942 = MVE_VADDLVu32acc + {6, OperandInfo247}, // Inst #943 = MVE_VADDLVu32no_acc + {6, OperandInfo248}, // Inst #944 = MVE_VADDVs16acc + {5, OperandInfo249}, // Inst #945 = MVE_VADDVs16no_acc + {6, OperandInfo248}, // Inst #946 = MVE_VADDVs32acc + {5, OperandInfo249}, // Inst #947 = MVE_VADDVs32no_acc + {6, OperandInfo248}, // Inst #948 = MVE_VADDVs8acc + {5, OperandInfo249}, // Inst #949 = MVE_VADDVs8no_acc + {6, OperandInfo248}, // Inst #950 = MVE_VADDVu16acc + {5, OperandInfo249}, // Inst #951 = MVE_VADDVu16no_acc + {6, OperandInfo248}, // Inst #952 = MVE_VADDVu32acc + {5, OperandInfo249}, // Inst #953 = MVE_VADDVu32no_acc + {6, OperandInfo248}, // Inst #954 = MVE_VADDVu8acc + {5, OperandInfo249}, // Inst #955 = MVE_VADDVu8no_acc + {7, OperandInfo250}, // Inst #956 = MVE_VADD_qr_f16 + {7, OperandInfo250}, // Inst #957 = MVE_VADD_qr_f32 + {7, OperandInfo250}, // Inst #958 = MVE_VADD_qr_i16 + {7, OperandInfo250}, // Inst #959 = MVE_VADD_qr_i32 + {7, OperandInfo250}, // Inst #960 = MVE_VADD_qr_i8 + {7, OperandInfo242}, // Inst #961 = MVE_VADDf16 + {7, OperandInfo242}, // Inst #962 = MVE_VADDf32 + {7, OperandInfo242}, // Inst #963 = MVE_VADDi16 + {7, OperandInfo242}, // Inst #964 = MVE_VADDi32 + {7, OperandInfo242}, // Inst #965 = MVE_VADDi8 + {7, OperandInfo242}, // Inst #966 = MVE_VAND + {7, OperandInfo242}, // Inst #967 = MVE_VBIC + {6, OperandInfo251}, // Inst #968 = MVE_VBICimmi16 + {6, OperandInfo251}, // Inst #969 = MVE_VBICimmi32 + {7, OperandInfo250}, // Inst #970 = MVE_VBRSR16 + {7, OperandInfo250}, // Inst #971 = MVE_VBRSR32 + {7, OperandInfo250}, // Inst #972 = MVE_VBRSR8 + {8, OperandInfo252}, // Inst #973 = MVE_VCADDf16 + {8, OperandInfo253}, // Inst #974 = MVE_VCADDf32 + {8, OperandInfo252}, // Inst #975 = MVE_VCADDi16 + {8, OperandInfo253}, // Inst #976 = MVE_VCADDi32 + {8, OperandInfo252}, // Inst #977 = MVE_VCADDi8 + {6, OperandInfo243}, // Inst #978 = MVE_VCLSs16 + {6, OperandInfo243}, // Inst #979 = MVE_VCLSs32 + {6, OperandInfo243}, // Inst #980 = MVE_VCLSs8 + {6, OperandInfo243}, // Inst #981 = MVE_VCLZs16 + {6, OperandInfo243}, // Inst #982 = MVE_VCLZs32 + {6, OperandInfo243}, // Inst #983 = MVE_VCLZs8 + {8, OperandInfo254}, // Inst #984 = MVE_VCMLAf16 + {8, OperandInfo254}, // Inst #985 = MVE_VCMLAf32 + {7, OperandInfo255}, // Inst #986 = MVE_VCMPf16 + {7, OperandInfo256}, // Inst #987 = MVE_VCMPf16r + {7, OperandInfo255}, // Inst #988 = MVE_VCMPf32 + {7, OperandInfo256}, // Inst #989 = MVE_VCMPf32r + {7, OperandInfo255}, // Inst #990 = MVE_VCMPi16 + {7, OperandInfo256}, // Inst #991 = MVE_VCMPi16r + {7, OperandInfo255}, // Inst #992 = MVE_VCMPi32 + {7, OperandInfo256}, // Inst #993 = MVE_VCMPi32r + {7, OperandInfo255}, // Inst #994 = MVE_VCMPi8 + {7, OperandInfo256}, // Inst #995 = MVE_VCMPi8r + {7, OperandInfo255}, // Inst #996 = MVE_VCMPs16 + {7, OperandInfo256}, // Inst #997 = MVE_VCMPs16r + {7, OperandInfo255}, // Inst #998 = MVE_VCMPs32 + {7, OperandInfo256}, // Inst #999 = MVE_VCMPs32r + {7, OperandInfo255}, // Inst #1000 = MVE_VCMPs8 + {7, OperandInfo256}, // Inst #1001 = MVE_VCMPs8r + {7, OperandInfo255}, // Inst #1002 = MVE_VCMPu16 + {7, OperandInfo256}, // Inst #1003 = MVE_VCMPu16r + {7, OperandInfo255}, // Inst #1004 = MVE_VCMPu32 + {7, OperandInfo256}, // Inst #1005 = MVE_VCMPu32r + {7, OperandInfo255}, // Inst #1006 = MVE_VCMPu8 + {7, OperandInfo256}, // Inst #1007 = MVE_VCMPu8r + {8, OperandInfo252}, // Inst #1008 = MVE_VCMULf16 + {8, OperandInfo253}, // Inst #1009 = MVE_VCMULf32 + {5, OperandInfo257}, // Inst #1010 = MVE_VCTP16 + {5, OperandInfo257}, // Inst #1011 = MVE_VCTP32 + {5, OperandInfo257}, // Inst #1012 = MVE_VCTP64 + {5, OperandInfo257}, // Inst #1013 = MVE_VCTP8 + {6, OperandInfo258}, // Inst #1014 = MVE_VCVTf16f32bh + {6, OperandInfo258}, // Inst #1015 = MVE_VCVTf16f32th + {7, OperandInfo259}, // Inst #1016 = MVE_VCVTf16s16_fix + {6, OperandInfo243}, // Inst #1017 = MVE_VCVTf16s16n + {7, OperandInfo259}, // Inst #1018 = MVE_VCVTf16u16_fix + {6, OperandInfo243}, // Inst #1019 = MVE_VCVTf16u16n + {6, OperandInfo243}, // Inst #1020 = MVE_VCVTf32f16bh + {6, OperandInfo243}, // Inst #1021 = MVE_VCVTf32f16th + {7, OperandInfo259}, // Inst #1022 = MVE_VCVTf32s32_fix + {6, OperandInfo243}, // Inst #1023 = MVE_VCVTf32s32n + {7, OperandInfo259}, // Inst #1024 = MVE_VCVTf32u32_fix + {6, OperandInfo243}, // Inst #1025 = MVE_VCVTf32u32n + {7, OperandInfo259}, // Inst #1026 = MVE_VCVTs16f16_fix + {6, OperandInfo243}, // Inst #1027 = MVE_VCVTs16f16a + {6, OperandInfo243}, // Inst #1028 = MVE_VCVTs16f16m + {6, OperandInfo243}, // Inst #1029 = MVE_VCVTs16f16n + {6, OperandInfo243}, // Inst #1030 = MVE_VCVTs16f16p + {6, OperandInfo243}, // Inst #1031 = MVE_VCVTs16f16z + {7, OperandInfo259}, // Inst #1032 = MVE_VCVTs32f32_fix + {6, OperandInfo243}, // Inst #1033 = MVE_VCVTs32f32a + {6, OperandInfo243}, // Inst #1034 = MVE_VCVTs32f32m + {6, OperandInfo243}, // Inst #1035 = MVE_VCVTs32f32n + {6, OperandInfo243}, // Inst #1036 = MVE_VCVTs32f32p + {6, OperandInfo243}, // Inst #1037 = MVE_VCVTs32f32z + {7, OperandInfo259}, // Inst #1038 = MVE_VCVTu16f16_fix + {6, OperandInfo243}, // Inst #1039 = MVE_VCVTu16f16a + {6, OperandInfo243}, // Inst #1040 = MVE_VCVTu16f16m + {6, OperandInfo243}, // Inst #1041 = MVE_VCVTu16f16n + {6, OperandInfo243}, // Inst #1042 = MVE_VCVTu16f16p + {6, OperandInfo243}, // Inst #1043 = MVE_VCVTu16f16z + {7, OperandInfo259}, // Inst #1044 = MVE_VCVTu32f32_fix + {6, OperandInfo243}, // Inst #1045 = MVE_VCVTu32f32a + {6, OperandInfo243}, // Inst #1046 = MVE_VCVTu32f32m + {6, OperandInfo243}, // Inst #1047 = MVE_VCVTu32f32n + {6, OperandInfo243}, // Inst #1048 = MVE_VCVTu32f32p + {6, OperandInfo243}, // Inst #1049 = MVE_VCVTu32f32z + {8, OperandInfo260}, // Inst #1050 = MVE_VDDUPu16 + {8, OperandInfo260}, // Inst #1051 = MVE_VDDUPu32 + {8, OperandInfo260}, // Inst #1052 = MVE_VDDUPu8 + {6, OperandInfo261}, // Inst #1053 = MVE_VDUP16 + {6, OperandInfo261}, // Inst #1054 = MVE_VDUP32 + {6, OperandInfo261}, // Inst #1055 = MVE_VDUP8 + {9, OperandInfo262}, // Inst #1056 = MVE_VDWDUPu16 + {9, OperandInfo262}, // Inst #1057 = MVE_VDWDUPu32 + {9, OperandInfo262}, // Inst #1058 = MVE_VDWDUPu8 + {7, OperandInfo242}, // Inst #1059 = MVE_VEOR + {7, OperandInfo263}, // Inst #1060 = MVE_VFMA_qr_Sf16 + {7, OperandInfo263}, // Inst #1061 = MVE_VFMA_qr_Sf32 + {7, OperandInfo263}, // Inst #1062 = MVE_VFMA_qr_f16 + {7, OperandInfo263}, // Inst #1063 = MVE_VFMA_qr_f32 + {7, OperandInfo264}, // Inst #1064 = MVE_VFMAf16 + {7, OperandInfo264}, // Inst #1065 = MVE_VFMAf32 + {7, OperandInfo264}, // Inst #1066 = MVE_VFMSf16 + {7, OperandInfo264}, // Inst #1067 = MVE_VFMSf32 + {7, OperandInfo250}, // Inst #1068 = MVE_VHADD_qr_s16 + {7, OperandInfo250}, // Inst #1069 = MVE_VHADD_qr_s32 + {7, OperandInfo250}, // Inst #1070 = MVE_VHADD_qr_s8 + {7, OperandInfo250}, // Inst #1071 = MVE_VHADD_qr_u16 + {7, OperandInfo250}, // Inst #1072 = MVE_VHADD_qr_u32 + {7, OperandInfo250}, // Inst #1073 = MVE_VHADD_qr_u8 + {7, OperandInfo242}, // Inst #1074 = MVE_VHADDs16 + {7, OperandInfo242}, // Inst #1075 = MVE_VHADDs32 + {7, OperandInfo242}, // Inst #1076 = MVE_VHADDs8 + {7, OperandInfo242}, // Inst #1077 = MVE_VHADDu16 + {7, OperandInfo242}, // Inst #1078 = MVE_VHADDu32 + {7, OperandInfo242}, // Inst #1079 = MVE_VHADDu8 + {8, OperandInfo252}, // Inst #1080 = MVE_VHCADDs16 + {8, OperandInfo253}, // Inst #1081 = MVE_VHCADDs32 + {8, OperandInfo252}, // Inst #1082 = MVE_VHCADDs8 + {7, OperandInfo250}, // Inst #1083 = MVE_VHSUB_qr_s16 + {7, OperandInfo250}, // Inst #1084 = MVE_VHSUB_qr_s32 + {7, OperandInfo250}, // Inst #1085 = MVE_VHSUB_qr_s8 + {7, OperandInfo250}, // Inst #1086 = MVE_VHSUB_qr_u16 + {7, OperandInfo250}, // Inst #1087 = MVE_VHSUB_qr_u32 + {7, OperandInfo250}, // Inst #1088 = MVE_VHSUB_qr_u8 + {7, OperandInfo242}, // Inst #1089 = MVE_VHSUBs16 + {7, OperandInfo242}, // Inst #1090 = MVE_VHSUBs32 + {7, OperandInfo242}, // Inst #1091 = MVE_VHSUBs8 + {7, OperandInfo242}, // Inst #1092 = MVE_VHSUBu16 + {7, OperandInfo242}, // Inst #1093 = MVE_VHSUBu32 + {7, OperandInfo242}, // Inst #1094 = MVE_VHSUBu8 + {8, OperandInfo260}, // Inst #1095 = MVE_VIDUPu16 + {8, OperandInfo260}, // Inst #1096 = MVE_VIDUPu32 + {8, OperandInfo260}, // Inst #1097 = MVE_VIDUPu8 + {9, OperandInfo262}, // Inst #1098 = MVE_VIWDUPu16 + {9, OperandInfo262}, // Inst #1099 = MVE_VIWDUPu32 + {9, OperandInfo262}, // Inst #1100 = MVE_VIWDUPu8 + {3, OperandInfo265}, // Inst #1101 = MVE_VLD20_16 + {4, OperandInfo266}, // Inst #1102 = MVE_VLD20_16_wb + {3, OperandInfo265}, // Inst #1103 = MVE_VLD20_32 + {4, OperandInfo266}, // Inst #1104 = MVE_VLD20_32_wb + {3, OperandInfo265}, // Inst #1105 = MVE_VLD20_8 + {4, OperandInfo266}, // Inst #1106 = MVE_VLD20_8_wb + {3, OperandInfo265}, // Inst #1107 = MVE_VLD21_16 + {4, OperandInfo266}, // Inst #1108 = MVE_VLD21_16_wb + {3, OperandInfo265}, // Inst #1109 = MVE_VLD21_32 + {4, OperandInfo266}, // Inst #1110 = MVE_VLD21_32_wb + {3, OperandInfo265}, // Inst #1111 = MVE_VLD21_8 + {4, OperandInfo266}, // Inst #1112 = MVE_VLD21_8_wb + {3, OperandInfo267}, // Inst #1113 = MVE_VLD40_16 + {4, OperandInfo268}, // Inst #1114 = MVE_VLD40_16_wb + {3, OperandInfo267}, // Inst #1115 = MVE_VLD40_32 + {4, OperandInfo268}, // Inst #1116 = MVE_VLD40_32_wb + {3, OperandInfo267}, // Inst #1117 = MVE_VLD40_8 + {4, OperandInfo268}, // Inst #1118 = MVE_VLD40_8_wb + {3, OperandInfo267}, // Inst #1119 = MVE_VLD41_16 + {4, OperandInfo268}, // Inst #1120 = MVE_VLD41_16_wb + {3, OperandInfo267}, // Inst #1121 = MVE_VLD41_32 + {4, OperandInfo268}, // Inst #1122 = MVE_VLD41_32_wb + {3, OperandInfo267}, // Inst #1123 = MVE_VLD41_8 + {4, OperandInfo268}, // Inst #1124 = MVE_VLD41_8_wb + {3, OperandInfo267}, // Inst #1125 = MVE_VLD42_16 + {4, OperandInfo268}, // Inst #1126 = MVE_VLD42_16_wb + {3, OperandInfo267}, // Inst #1127 = MVE_VLD42_32 + {4, OperandInfo268}, // Inst #1128 = MVE_VLD42_32_wb + {3, OperandInfo267}, // Inst #1129 = MVE_VLD42_8 + {4, OperandInfo268}, // Inst #1130 = MVE_VLD42_8_wb + {3, OperandInfo267}, // Inst #1131 = MVE_VLD43_16 + {4, OperandInfo268}, // Inst #1132 = MVE_VLD43_16_wb + {3, OperandInfo267}, // Inst #1133 = MVE_VLD43_32 + {4, OperandInfo268}, // Inst #1134 = MVE_VLD43_32_wb + {3, OperandInfo267}, // Inst #1135 = MVE_VLD43_8 + {4, OperandInfo268}, // Inst #1136 = MVE_VLD43_8_wb + {6, OperandInfo269}, // Inst #1137 = MVE_VLDRBS16 + {7, OperandInfo270}, // Inst #1138 = MVE_VLDRBS16_post + {7, OperandInfo270}, // Inst #1139 = MVE_VLDRBS16_pre + {6, OperandInfo271}, // Inst #1140 = MVE_VLDRBS16_rq + {6, OperandInfo269}, // Inst #1141 = MVE_VLDRBS32 + {7, OperandInfo270}, // Inst #1142 = MVE_VLDRBS32_post + {7, OperandInfo270}, // Inst #1143 = MVE_VLDRBS32_pre + {6, OperandInfo271}, // Inst #1144 = MVE_VLDRBS32_rq + {6, OperandInfo269}, // Inst #1145 = MVE_VLDRBU16 + {7, OperandInfo270}, // Inst #1146 = MVE_VLDRBU16_post + {7, OperandInfo270}, // Inst #1147 = MVE_VLDRBU16_pre + {6, OperandInfo271}, // Inst #1148 = MVE_VLDRBU16_rq + {6, OperandInfo269}, // Inst #1149 = MVE_VLDRBU32 + {7, OperandInfo270}, // Inst #1150 = MVE_VLDRBU32_post + {7, OperandInfo270}, // Inst #1151 = MVE_VLDRBU32_pre + {6, OperandInfo271}, // Inst #1152 = MVE_VLDRBU32_rq + {6, OperandInfo272}, // Inst #1153 = MVE_VLDRBU8 + {7, OperandInfo273}, // Inst #1154 = MVE_VLDRBU8_post + {7, OperandInfo273}, // Inst #1155 = MVE_VLDRBU8_pre + {6, OperandInfo271}, // Inst #1156 = MVE_VLDRBU8_rq + {6, OperandInfo274}, // Inst #1157 = MVE_VLDRDU64_qi + {7, OperandInfo275}, // Inst #1158 = MVE_VLDRDU64_qi_pre + {6, OperandInfo271}, // Inst #1159 = MVE_VLDRDU64_rq + {6, OperandInfo271}, // Inst #1160 = MVE_VLDRDU64_rq_u + {6, OperandInfo269}, // Inst #1161 = MVE_VLDRHS32 + {7, OperandInfo270}, // Inst #1162 = MVE_VLDRHS32_post + {7, OperandInfo270}, // Inst #1163 = MVE_VLDRHS32_pre + {6, OperandInfo271}, // Inst #1164 = MVE_VLDRHS32_rq + {6, OperandInfo271}, // Inst #1165 = MVE_VLDRHS32_rq_u + {6, OperandInfo272}, // Inst #1166 = MVE_VLDRHU16 + {7, OperandInfo273}, // Inst #1167 = MVE_VLDRHU16_post + {7, OperandInfo273}, // Inst #1168 = MVE_VLDRHU16_pre + {6, OperandInfo271}, // Inst #1169 = MVE_VLDRHU16_rq + {6, OperandInfo271}, // Inst #1170 = MVE_VLDRHU16_rq_u + {6, OperandInfo269}, // Inst #1171 = MVE_VLDRHU32 + {7, OperandInfo270}, // Inst #1172 = MVE_VLDRHU32_post + {7, OperandInfo270}, // Inst #1173 = MVE_VLDRHU32_pre + {6, OperandInfo271}, // Inst #1174 = MVE_VLDRHU32_rq + {6, OperandInfo271}, // Inst #1175 = MVE_VLDRHU32_rq_u + {6, OperandInfo272}, // Inst #1176 = MVE_VLDRWU32 + {7, OperandInfo273}, // Inst #1177 = MVE_VLDRWU32_post + {7, OperandInfo273}, // Inst #1178 = MVE_VLDRWU32_pre + {6, OperandInfo274}, // Inst #1179 = MVE_VLDRWU32_qi + {7, OperandInfo275}, // Inst #1180 = MVE_VLDRWU32_qi_pre + {6, OperandInfo271}, // Inst #1181 = MVE_VLDRWU32_rq + {6, OperandInfo271}, // Inst #1182 = MVE_VLDRWU32_rq_u + {6, OperandInfo276}, // Inst #1183 = MVE_VMAXAVs16 + {6, OperandInfo276}, // Inst #1184 = MVE_VMAXAVs32 + {6, OperandInfo276}, // Inst #1185 = MVE_VMAXAVs8 + {6, OperandInfo258}, // Inst #1186 = MVE_VMAXAs16 + {6, OperandInfo258}, // Inst #1187 = MVE_VMAXAs32 + {6, OperandInfo258}, // Inst #1188 = MVE_VMAXAs8 + {6, OperandInfo276}, // Inst #1189 = MVE_VMAXNMAVf16 + {6, OperandInfo276}, // Inst #1190 = MVE_VMAXNMAVf32 + {6, OperandInfo258}, // Inst #1191 = MVE_VMAXNMAf16 + {6, OperandInfo258}, // Inst #1192 = MVE_VMAXNMAf32 + {6, OperandInfo276}, // Inst #1193 = MVE_VMAXNMVf16 + {6, OperandInfo276}, // Inst #1194 = MVE_VMAXNMVf32 + {7, OperandInfo242}, // Inst #1195 = MVE_VMAXNMf16 + {7, OperandInfo242}, // Inst #1196 = MVE_VMAXNMf32 + {6, OperandInfo276}, // Inst #1197 = MVE_VMAXVs16 + {6, OperandInfo276}, // Inst #1198 = MVE_VMAXVs32 + {6, OperandInfo276}, // Inst #1199 = MVE_VMAXVs8 + {6, OperandInfo276}, // Inst #1200 = MVE_VMAXVu16 + {6, OperandInfo276}, // Inst #1201 = MVE_VMAXVu32 + {6, OperandInfo276}, // Inst #1202 = MVE_VMAXVu8 + {7, OperandInfo242}, // Inst #1203 = MVE_VMAXs16 + {7, OperandInfo242}, // Inst #1204 = MVE_VMAXs32 + {7, OperandInfo242}, // Inst #1205 = MVE_VMAXs8 + {7, OperandInfo242}, // Inst #1206 = MVE_VMAXu16 + {7, OperandInfo242}, // Inst #1207 = MVE_VMAXu32 + {7, OperandInfo242}, // Inst #1208 = MVE_VMAXu8 + {6, OperandInfo276}, // Inst #1209 = MVE_VMINAVs16 + {6, OperandInfo276}, // Inst #1210 = MVE_VMINAVs32 + {6, OperandInfo276}, // Inst #1211 = MVE_VMINAVs8 + {6, OperandInfo258}, // Inst #1212 = MVE_VMINAs16 + {6, OperandInfo258}, // Inst #1213 = MVE_VMINAs32 + {6, OperandInfo258}, // Inst #1214 = MVE_VMINAs8 + {6, OperandInfo276}, // Inst #1215 = MVE_VMINNMAVf16 + {6, OperandInfo276}, // Inst #1216 = MVE_VMINNMAVf32 + {6, OperandInfo258}, // Inst #1217 = MVE_VMINNMAf16 + {6, OperandInfo258}, // Inst #1218 = MVE_VMINNMAf32 + {6, OperandInfo276}, // Inst #1219 = MVE_VMINNMVf16 + {6, OperandInfo276}, // Inst #1220 = MVE_VMINNMVf32 + {7, OperandInfo242}, // Inst #1221 = MVE_VMINNMf16 + {7, OperandInfo242}, // Inst #1222 = MVE_VMINNMf32 + {6, OperandInfo276}, // Inst #1223 = MVE_VMINVs16 + {6, OperandInfo276}, // Inst #1224 = MVE_VMINVs32 + {6, OperandInfo276}, // Inst #1225 = MVE_VMINVs8 + {6, OperandInfo276}, // Inst #1226 = MVE_VMINVu16 + {6, OperandInfo276}, // Inst #1227 = MVE_VMINVu32 + {6, OperandInfo276}, // Inst #1228 = MVE_VMINVu8 + {7, OperandInfo242}, // Inst #1229 = MVE_VMINs16 + {7, OperandInfo242}, // Inst #1230 = MVE_VMINs32 + {7, OperandInfo242}, // Inst #1231 = MVE_VMINs8 + {7, OperandInfo242}, // Inst #1232 = MVE_VMINu16 + {7, OperandInfo242}, // Inst #1233 = MVE_VMINu32 + {7, OperandInfo242}, // Inst #1234 = MVE_VMINu8 + {7, OperandInfo277}, // Inst #1235 = MVE_VMLADAVas16 + {7, OperandInfo277}, // Inst #1236 = MVE_VMLADAVas32 + {7, OperandInfo277}, // Inst #1237 = MVE_VMLADAVas8 + {7, OperandInfo277}, // Inst #1238 = MVE_VMLADAVau16 + {7, OperandInfo277}, // Inst #1239 = MVE_VMLADAVau32 + {7, OperandInfo277}, // Inst #1240 = MVE_VMLADAVau8 + {7, OperandInfo277}, // Inst #1241 = MVE_VMLADAVaxs16 + {7, OperandInfo277}, // Inst #1242 = MVE_VMLADAVaxs32 + {7, OperandInfo277}, // Inst #1243 = MVE_VMLADAVaxs8 + {6, OperandInfo278}, // Inst #1244 = MVE_VMLADAVs16 + {6, OperandInfo278}, // Inst #1245 = MVE_VMLADAVs32 + {6, OperandInfo278}, // Inst #1246 = MVE_VMLADAVs8 + {6, OperandInfo278}, // Inst #1247 = MVE_VMLADAVu16 + {6, OperandInfo278}, // Inst #1248 = MVE_VMLADAVu32 + {6, OperandInfo278}, // Inst #1249 = MVE_VMLADAVu8 + {6, OperandInfo278}, // Inst #1250 = MVE_VMLADAVxs16 + {6, OperandInfo278}, // Inst #1251 = MVE_VMLADAVxs32 + {6, OperandInfo278}, // Inst #1252 = MVE_VMLADAVxs8 + {9, OperandInfo279}, // Inst #1253 = MVE_VMLALDAVas16 + {9, OperandInfo279}, // Inst #1254 = MVE_VMLALDAVas32 + {9, OperandInfo279}, // Inst #1255 = MVE_VMLALDAVau16 + {9, OperandInfo279}, // Inst #1256 = MVE_VMLALDAVau32 + {9, OperandInfo279}, // Inst #1257 = MVE_VMLALDAVaxs16 + {9, OperandInfo279}, // Inst #1258 = MVE_VMLALDAVaxs32 + {7, OperandInfo280}, // Inst #1259 = MVE_VMLALDAVs16 + {7, OperandInfo280}, // Inst #1260 = MVE_VMLALDAVs32 + {7, OperandInfo280}, // Inst #1261 = MVE_VMLALDAVu16 + {7, OperandInfo280}, // Inst #1262 = MVE_VMLALDAVu32 + {7, OperandInfo280}, // Inst #1263 = MVE_VMLALDAVxs16 + {7, OperandInfo280}, // Inst #1264 = MVE_VMLALDAVxs32 + {7, OperandInfo263}, // Inst #1265 = MVE_VMLAS_qr_s16 + {7, OperandInfo263}, // Inst #1266 = MVE_VMLAS_qr_s32 + {7, OperandInfo263}, // Inst #1267 = MVE_VMLAS_qr_s8 + {7, OperandInfo263}, // Inst #1268 = MVE_VMLAS_qr_u16 + {7, OperandInfo263}, // Inst #1269 = MVE_VMLAS_qr_u32 + {7, OperandInfo263}, // Inst #1270 = MVE_VMLAS_qr_u8 + {7, OperandInfo263}, // Inst #1271 = MVE_VMLA_qr_s16 + {7, OperandInfo263}, // Inst #1272 = MVE_VMLA_qr_s32 + {7, OperandInfo263}, // Inst #1273 = MVE_VMLA_qr_s8 + {7, OperandInfo263}, // Inst #1274 = MVE_VMLA_qr_u16 + {7, OperandInfo263}, // Inst #1275 = MVE_VMLA_qr_u32 + {7, OperandInfo263}, // Inst #1276 = MVE_VMLA_qr_u8 + {7, OperandInfo277}, // Inst #1277 = MVE_VMLSDAVas16 + {7, OperandInfo277}, // Inst #1278 = MVE_VMLSDAVas32 + {7, OperandInfo277}, // Inst #1279 = MVE_VMLSDAVas8 + {7, OperandInfo277}, // Inst #1280 = MVE_VMLSDAVaxs16 + {7, OperandInfo277}, // Inst #1281 = MVE_VMLSDAVaxs32 + {7, OperandInfo277}, // Inst #1282 = MVE_VMLSDAVaxs8 + {6, OperandInfo278}, // Inst #1283 = MVE_VMLSDAVs16 + {6, OperandInfo278}, // Inst #1284 = MVE_VMLSDAVs32 + {6, OperandInfo278}, // Inst #1285 = MVE_VMLSDAVs8 + {6, OperandInfo278}, // Inst #1286 = MVE_VMLSDAVxs16 + {6, OperandInfo278}, // Inst #1287 = MVE_VMLSDAVxs32 + {6, OperandInfo278}, // Inst #1288 = MVE_VMLSDAVxs8 + {9, OperandInfo279}, // Inst #1289 = MVE_VMLSLDAVas16 + {9, OperandInfo279}, // Inst #1290 = MVE_VMLSLDAVas32 + {9, OperandInfo279}, // Inst #1291 = MVE_VMLSLDAVaxs16 + {9, OperandInfo279}, // Inst #1292 = MVE_VMLSLDAVaxs32 + {7, OperandInfo280}, // Inst #1293 = MVE_VMLSLDAVs16 + {7, OperandInfo280}, // Inst #1294 = MVE_VMLSLDAVs32 + {7, OperandInfo280}, // Inst #1295 = MVE_VMLSLDAVxs16 + {7, OperandInfo280}, // Inst #1296 = MVE_VMLSLDAVxs32 + {6, OperandInfo243}, // Inst #1297 = MVE_VMOVLs16bh + {6, OperandInfo243}, // Inst #1298 = MVE_VMOVLs16th + {6, OperandInfo243}, // Inst #1299 = MVE_VMOVLs8bh + {6, OperandInfo243}, // Inst #1300 = MVE_VMOVLs8th + {6, OperandInfo243}, // Inst #1301 = MVE_VMOVLu16bh + {6, OperandInfo243}, // Inst #1302 = MVE_VMOVLu16th + {6, OperandInfo243}, // Inst #1303 = MVE_VMOVLu8bh + {6, OperandInfo243}, // Inst #1304 = MVE_VMOVLu8th + {6, OperandInfo258}, // Inst #1305 = MVE_VMOVNi16bh + {6, OperandInfo258}, // Inst #1306 = MVE_VMOVNi16th + {6, OperandInfo258}, // Inst #1307 = MVE_VMOVNi32bh + {6, OperandInfo258}, // Inst #1308 = MVE_VMOVNi32th + {5, OperandInfo281}, // Inst #1309 = MVE_VMOV_from_lane_32 + {5, OperandInfo281}, // Inst #1310 = MVE_VMOV_from_lane_s16 + {5, OperandInfo281}, // Inst #1311 = MVE_VMOV_from_lane_s8 + {5, OperandInfo281}, // Inst #1312 = MVE_VMOV_from_lane_u16 + {5, OperandInfo281}, // Inst #1313 = MVE_VMOV_from_lane_u8 + {8, OperandInfo282}, // Inst #1314 = MVE_VMOV_q_rr + {7, OperandInfo283}, // Inst #1315 = MVE_VMOV_rr_q + {6, OperandInfo284}, // Inst #1316 = MVE_VMOV_to_lane_16 + {6, OperandInfo284}, // Inst #1317 = MVE_VMOV_to_lane_32 + {6, OperandInfo284}, // Inst #1318 = MVE_VMOV_to_lane_8 + {6, OperandInfo285}, // Inst #1319 = MVE_VMOVimmf32 + {6, OperandInfo285}, // Inst #1320 = MVE_VMOVimmi16 + {6, OperandInfo285}, // Inst #1321 = MVE_VMOVimmi32 + {6, OperandInfo285}, // Inst #1322 = MVE_VMOVimmi64 + {6, OperandInfo285}, // Inst #1323 = MVE_VMOVimmi8 + {7, OperandInfo242}, // Inst #1324 = MVE_VMULHs16 + {7, OperandInfo242}, // Inst #1325 = MVE_VMULHs32 + {7, OperandInfo242}, // Inst #1326 = MVE_VMULHs8 + {7, OperandInfo242}, // Inst #1327 = MVE_VMULHu16 + {7, OperandInfo242}, // Inst #1328 = MVE_VMULHu32 + {7, OperandInfo242}, // Inst #1329 = MVE_VMULHu8 + {7, OperandInfo242}, // Inst #1330 = MVE_VMULLBp16 + {7, OperandInfo242}, // Inst #1331 = MVE_VMULLBp8 + {7, OperandInfo242}, // Inst #1332 = MVE_VMULLBs16 + {7, OperandInfo286}, // Inst #1333 = MVE_VMULLBs32 + {7, OperandInfo242}, // Inst #1334 = MVE_VMULLBs8 + {7, OperandInfo242}, // Inst #1335 = MVE_VMULLBu16 + {7, OperandInfo286}, // Inst #1336 = MVE_VMULLBu32 + {7, OperandInfo242}, // Inst #1337 = MVE_VMULLBu8 + {7, OperandInfo242}, // Inst #1338 = MVE_VMULLTp16 + {7, OperandInfo242}, // Inst #1339 = MVE_VMULLTp8 + {7, OperandInfo242}, // Inst #1340 = MVE_VMULLTs16 + {7, OperandInfo286}, // Inst #1341 = MVE_VMULLTs32 + {7, OperandInfo242}, // Inst #1342 = MVE_VMULLTs8 + {7, OperandInfo242}, // Inst #1343 = MVE_VMULLTu16 + {7, OperandInfo286}, // Inst #1344 = MVE_VMULLTu32 + {7, OperandInfo242}, // Inst #1345 = MVE_VMULLTu8 + {7, OperandInfo250}, // Inst #1346 = MVE_VMUL_qr_f16 + {7, OperandInfo250}, // Inst #1347 = MVE_VMUL_qr_f32 + {7, OperandInfo250}, // Inst #1348 = MVE_VMUL_qr_i16 + {7, OperandInfo250}, // Inst #1349 = MVE_VMUL_qr_i32 + {7, OperandInfo250}, // Inst #1350 = MVE_VMUL_qr_i8 + {7, OperandInfo242}, // Inst #1351 = MVE_VMULf16 + {7, OperandInfo242}, // Inst #1352 = MVE_VMULf32 + {7, OperandInfo242}, // Inst #1353 = MVE_VMULi16 + {7, OperandInfo242}, // Inst #1354 = MVE_VMULi32 + {7, OperandInfo242}, // Inst #1355 = MVE_VMULi8 + {6, OperandInfo243}, // Inst #1356 = MVE_VMVN + {6, OperandInfo285}, // Inst #1357 = MVE_VMVNimmi16 + {6, OperandInfo285}, // Inst #1358 = MVE_VMVNimmi32 + {6, OperandInfo243}, // Inst #1359 = MVE_VNEGf16 + {6, OperandInfo243}, // Inst #1360 = MVE_VNEGf32 + {6, OperandInfo243}, // Inst #1361 = MVE_VNEGs16 + {6, OperandInfo243}, // Inst #1362 = MVE_VNEGs32 + {6, OperandInfo243}, // Inst #1363 = MVE_VNEGs8 + {7, OperandInfo242}, // Inst #1364 = MVE_VORN + {7, OperandInfo242}, // Inst #1365 = MVE_VORR + {6, OperandInfo251}, // Inst #1366 = MVE_VORRimmi16 + {6, OperandInfo251}, // Inst #1367 = MVE_VORRimmi32 + {5, OperandInfo287}, // Inst #1368 = MVE_VPNOT + {6, OperandInfo288}, // Inst #1369 = MVE_VPSEL + {1, OperandInfo2}, // Inst #1370 = MVE_VPST + {4, OperandInfo289}, // Inst #1371 = MVE_VPTv16i8 + {4, OperandInfo290}, // Inst #1372 = MVE_VPTv16i8r + {4, OperandInfo289}, // Inst #1373 = MVE_VPTv16s8 + {4, OperandInfo290}, // Inst #1374 = MVE_VPTv16s8r + {4, OperandInfo289}, // Inst #1375 = MVE_VPTv16u8 + {4, OperandInfo290}, // Inst #1376 = MVE_VPTv16u8r + {4, OperandInfo289}, // Inst #1377 = MVE_VPTv4f32 + {4, OperandInfo290}, // Inst #1378 = MVE_VPTv4f32r + {4, OperandInfo289}, // Inst #1379 = MVE_VPTv4i32 + {4, OperandInfo290}, // Inst #1380 = MVE_VPTv4i32r + {4, OperandInfo289}, // Inst #1381 = MVE_VPTv4s32 + {4, OperandInfo290}, // Inst #1382 = MVE_VPTv4s32r + {4, OperandInfo289}, // Inst #1383 = MVE_VPTv4u32 + {4, OperandInfo290}, // Inst #1384 = MVE_VPTv4u32r + {4, OperandInfo289}, // Inst #1385 = MVE_VPTv8f16 + {4, OperandInfo290}, // Inst #1386 = MVE_VPTv8f16r + {4, OperandInfo289}, // Inst #1387 = MVE_VPTv8i16 + {4, OperandInfo290}, // Inst #1388 = MVE_VPTv8i16r + {4, OperandInfo289}, // Inst #1389 = MVE_VPTv8s16 + {4, OperandInfo290}, // Inst #1390 = MVE_VPTv8s16r + {4, OperandInfo289}, // Inst #1391 = MVE_VPTv8u16 + {4, OperandInfo290}, // Inst #1392 = MVE_VPTv8u16r + {6, OperandInfo243}, // Inst #1393 = MVE_VQABSs16 + {6, OperandInfo243}, // Inst #1394 = MVE_VQABSs32 + {6, OperandInfo243}, // Inst #1395 = MVE_VQABSs8 + {7, OperandInfo250}, // Inst #1396 = MVE_VQADD_qr_s16 + {7, OperandInfo250}, // Inst #1397 = MVE_VQADD_qr_s32 + {7, OperandInfo250}, // Inst #1398 = MVE_VQADD_qr_s8 + {7, OperandInfo250}, // Inst #1399 = MVE_VQADD_qr_u16 + {7, OperandInfo250}, // Inst #1400 = MVE_VQADD_qr_u32 + {7, OperandInfo250}, // Inst #1401 = MVE_VQADD_qr_u8 + {7, OperandInfo242}, // Inst #1402 = MVE_VQADDs16 + {7, OperandInfo242}, // Inst #1403 = MVE_VQADDs32 + {7, OperandInfo242}, // Inst #1404 = MVE_VQADDs8 + {7, OperandInfo242}, // Inst #1405 = MVE_VQADDu16 + {7, OperandInfo242}, // Inst #1406 = MVE_VQADDu32 + {7, OperandInfo242}, // Inst #1407 = MVE_VQADDu8 + {7, OperandInfo264}, // Inst #1408 = MVE_VQDMLADHXs16 + {7, OperandInfo291}, // Inst #1409 = MVE_VQDMLADHXs32 + {7, OperandInfo264}, // Inst #1410 = MVE_VQDMLADHXs8 + {7, OperandInfo264}, // Inst #1411 = MVE_VQDMLADHs16 + {7, OperandInfo291}, // Inst #1412 = MVE_VQDMLADHs32 + {7, OperandInfo264}, // Inst #1413 = MVE_VQDMLADHs8 + {7, OperandInfo263}, // Inst #1414 = MVE_VQDMLAH_qrs16 + {7, OperandInfo263}, // Inst #1415 = MVE_VQDMLAH_qrs32 + {7, OperandInfo263}, // Inst #1416 = MVE_VQDMLAH_qrs8 + {7, OperandInfo263}, // Inst #1417 = MVE_VQDMLASH_qrs16 + {7, OperandInfo263}, // Inst #1418 = MVE_VQDMLASH_qrs32 + {7, OperandInfo263}, // Inst #1419 = MVE_VQDMLASH_qrs8 + {7, OperandInfo264}, // Inst #1420 = MVE_VQDMLSDHXs16 + {7, OperandInfo291}, // Inst #1421 = MVE_VQDMLSDHXs32 + {7, OperandInfo264}, // Inst #1422 = MVE_VQDMLSDHXs8 + {7, OperandInfo264}, // Inst #1423 = MVE_VQDMLSDHs16 + {7, OperandInfo291}, // Inst #1424 = MVE_VQDMLSDHs32 + {7, OperandInfo264}, // Inst #1425 = MVE_VQDMLSDHs8 + {7, OperandInfo250}, // Inst #1426 = MVE_VQDMULH_qr_s16 + {7, OperandInfo250}, // Inst #1427 = MVE_VQDMULH_qr_s32 + {7, OperandInfo250}, // Inst #1428 = MVE_VQDMULH_qr_s8 + {7, OperandInfo242}, // Inst #1429 = MVE_VQDMULHi16 + {7, OperandInfo242}, // Inst #1430 = MVE_VQDMULHi32 + {7, OperandInfo242}, // Inst #1431 = MVE_VQDMULHi8 + {7, OperandInfo250}, // Inst #1432 = MVE_VQDMULL_qr_s16bh + {7, OperandInfo250}, // Inst #1433 = MVE_VQDMULL_qr_s16th + {7, OperandInfo292}, // Inst #1434 = MVE_VQDMULL_qr_s32bh + {7, OperandInfo292}, // Inst #1435 = MVE_VQDMULL_qr_s32th + {7, OperandInfo242}, // Inst #1436 = MVE_VQDMULLs16bh + {7, OperandInfo242}, // Inst #1437 = MVE_VQDMULLs16th + {7, OperandInfo286}, // Inst #1438 = MVE_VQDMULLs32bh + {7, OperandInfo286}, // Inst #1439 = MVE_VQDMULLs32th + {6, OperandInfo258}, // Inst #1440 = MVE_VQMOVNs16bh + {6, OperandInfo258}, // Inst #1441 = MVE_VQMOVNs16th + {6, OperandInfo258}, // Inst #1442 = MVE_VQMOVNs32bh + {6, OperandInfo258}, // Inst #1443 = MVE_VQMOVNs32th + {6, OperandInfo258}, // Inst #1444 = MVE_VQMOVNu16bh + {6, OperandInfo258}, // Inst #1445 = MVE_VQMOVNu16th + {6, OperandInfo258}, // Inst #1446 = MVE_VQMOVNu32bh + {6, OperandInfo258}, // Inst #1447 = MVE_VQMOVNu32th + {6, OperandInfo258}, // Inst #1448 = MVE_VQMOVUNs16bh + {6, OperandInfo258}, // Inst #1449 = MVE_VQMOVUNs16th + {6, OperandInfo258}, // Inst #1450 = MVE_VQMOVUNs32bh + {6, OperandInfo258}, // Inst #1451 = MVE_VQMOVUNs32th + {6, OperandInfo243}, // Inst #1452 = MVE_VQNEGs16 + {6, OperandInfo243}, // Inst #1453 = MVE_VQNEGs32 + {6, OperandInfo243}, // Inst #1454 = MVE_VQNEGs8 + {7, OperandInfo264}, // Inst #1455 = MVE_VQRDMLADHXs16 + {7, OperandInfo291}, // Inst #1456 = MVE_VQRDMLADHXs32 + {7, OperandInfo264}, // Inst #1457 = MVE_VQRDMLADHXs8 + {7, OperandInfo264}, // Inst #1458 = MVE_VQRDMLADHs16 + {7, OperandInfo291}, // Inst #1459 = MVE_VQRDMLADHs32 + {7, OperandInfo264}, // Inst #1460 = MVE_VQRDMLADHs8 + {7, OperandInfo263}, // Inst #1461 = MVE_VQRDMLAH_qrs16 + {7, OperandInfo263}, // Inst #1462 = MVE_VQRDMLAH_qrs32 + {7, OperandInfo263}, // Inst #1463 = MVE_VQRDMLAH_qrs8 + {7, OperandInfo263}, // Inst #1464 = MVE_VQRDMLASH_qrs16 + {7, OperandInfo263}, // Inst #1465 = MVE_VQRDMLASH_qrs32 + {7, OperandInfo263}, // Inst #1466 = MVE_VQRDMLASH_qrs8 + {7, OperandInfo264}, // Inst #1467 = MVE_VQRDMLSDHXs16 + {7, OperandInfo291}, // Inst #1468 = MVE_VQRDMLSDHXs32 + {7, OperandInfo264}, // Inst #1469 = MVE_VQRDMLSDHXs8 + {7, OperandInfo264}, // Inst #1470 = MVE_VQRDMLSDHs16 + {7, OperandInfo291}, // Inst #1471 = MVE_VQRDMLSDHs32 + {7, OperandInfo264}, // Inst #1472 = MVE_VQRDMLSDHs8 + {7, OperandInfo250}, // Inst #1473 = MVE_VQRDMULH_qr_s16 + {7, OperandInfo250}, // Inst #1474 = MVE_VQRDMULH_qr_s32 + {7, OperandInfo250}, // Inst #1475 = MVE_VQRDMULH_qr_s8 + {7, OperandInfo242}, // Inst #1476 = MVE_VQRDMULHi16 + {7, OperandInfo242}, // Inst #1477 = MVE_VQRDMULHi32 + {7, OperandInfo242}, // Inst #1478 = MVE_VQRDMULHi8 + {7, OperandInfo242}, // Inst #1479 = MVE_VQRSHL_by_vecs16 + {7, OperandInfo242}, // Inst #1480 = MVE_VQRSHL_by_vecs32 + {7, OperandInfo242}, // Inst #1481 = MVE_VQRSHL_by_vecs8 + {7, OperandInfo242}, // Inst #1482 = MVE_VQRSHL_by_vecu16 + {7, OperandInfo242}, // Inst #1483 = MVE_VQRSHL_by_vecu32 + {7, OperandInfo242}, // Inst #1484 = MVE_VQRSHL_by_vecu8 + {6, OperandInfo293}, // Inst #1485 = MVE_VQRSHL_qrs16 + {6, OperandInfo293}, // Inst #1486 = MVE_VQRSHL_qrs32 + {6, OperandInfo293}, // Inst #1487 = MVE_VQRSHL_qrs8 + {6, OperandInfo293}, // Inst #1488 = MVE_VQRSHL_qru16 + {6, OperandInfo293}, // Inst #1489 = MVE_VQRSHL_qru32 + {6, OperandInfo293}, // Inst #1490 = MVE_VQRSHL_qru8 + {7, OperandInfo294}, // Inst #1491 = MVE_VQRSHRNbhs16 + {7, OperandInfo294}, // Inst #1492 = MVE_VQRSHRNbhs32 + {7, OperandInfo294}, // Inst #1493 = MVE_VQRSHRNbhu16 + {7, OperandInfo294}, // Inst #1494 = MVE_VQRSHRNbhu32 + {7, OperandInfo294}, // Inst #1495 = MVE_VQRSHRNths16 + {7, OperandInfo294}, // Inst #1496 = MVE_VQRSHRNths32 + {7, OperandInfo294}, // Inst #1497 = MVE_VQRSHRNthu16 + {7, OperandInfo294}, // Inst #1498 = MVE_VQRSHRNthu32 + {7, OperandInfo294}, // Inst #1499 = MVE_VQRSHRUNs16bh + {7, OperandInfo294}, // Inst #1500 = MVE_VQRSHRUNs16th + {7, OperandInfo294}, // Inst #1501 = MVE_VQRSHRUNs32bh + {7, OperandInfo294}, // Inst #1502 = MVE_VQRSHRUNs32th + {7, OperandInfo259}, // Inst #1503 = MVE_VQSHLU_imms16 + {7, OperandInfo259}, // Inst #1504 = MVE_VQSHLU_imms32 + {7, OperandInfo259}, // Inst #1505 = MVE_VQSHLU_imms8 + {7, OperandInfo242}, // Inst #1506 = MVE_VQSHL_by_vecs16 + {7, OperandInfo242}, // Inst #1507 = MVE_VQSHL_by_vecs32 + {7, OperandInfo242}, // Inst #1508 = MVE_VQSHL_by_vecs8 + {7, OperandInfo242}, // Inst #1509 = MVE_VQSHL_by_vecu16 + {7, OperandInfo242}, // Inst #1510 = MVE_VQSHL_by_vecu32 + {7, OperandInfo242}, // Inst #1511 = MVE_VQSHL_by_vecu8 + {6, OperandInfo293}, // Inst #1512 = MVE_VQSHL_qrs16 + {6, OperandInfo293}, // Inst #1513 = MVE_VQSHL_qrs32 + {6, OperandInfo293}, // Inst #1514 = MVE_VQSHL_qrs8 + {6, OperandInfo293}, // Inst #1515 = MVE_VQSHL_qru16 + {6, OperandInfo293}, // Inst #1516 = MVE_VQSHL_qru32 + {6, OperandInfo293}, // Inst #1517 = MVE_VQSHL_qru8 + {7, OperandInfo259}, // Inst #1518 = MVE_VQSHLimms16 + {7, OperandInfo259}, // Inst #1519 = MVE_VQSHLimms32 + {7, OperandInfo259}, // Inst #1520 = MVE_VQSHLimms8 + {7, OperandInfo259}, // Inst #1521 = MVE_VQSHLimmu16 + {7, OperandInfo259}, // Inst #1522 = MVE_VQSHLimmu32 + {7, OperandInfo259}, // Inst #1523 = MVE_VQSHLimmu8 + {7, OperandInfo294}, // Inst #1524 = MVE_VQSHRNbhs16 + {7, OperandInfo294}, // Inst #1525 = MVE_VQSHRNbhs32 + {7, OperandInfo294}, // Inst #1526 = MVE_VQSHRNbhu16 + {7, OperandInfo294}, // Inst #1527 = MVE_VQSHRNbhu32 + {7, OperandInfo294}, // Inst #1528 = MVE_VQSHRNths16 + {7, OperandInfo294}, // Inst #1529 = MVE_VQSHRNths32 + {7, OperandInfo294}, // Inst #1530 = MVE_VQSHRNthu16 + {7, OperandInfo294}, // Inst #1531 = MVE_VQSHRNthu32 + {7, OperandInfo294}, // Inst #1532 = MVE_VQSHRUNs16bh + {7, OperandInfo294}, // Inst #1533 = MVE_VQSHRUNs16th + {7, OperandInfo294}, // Inst #1534 = MVE_VQSHRUNs32bh + {7, OperandInfo294}, // Inst #1535 = MVE_VQSHRUNs32th + {7, OperandInfo250}, // Inst #1536 = MVE_VQSUB_qr_s16 + {7, OperandInfo250}, // Inst #1537 = MVE_VQSUB_qr_s32 + {7, OperandInfo250}, // Inst #1538 = MVE_VQSUB_qr_s8 + {7, OperandInfo250}, // Inst #1539 = MVE_VQSUB_qr_u16 + {7, OperandInfo250}, // Inst #1540 = MVE_VQSUB_qr_u32 + {7, OperandInfo250}, // Inst #1541 = MVE_VQSUB_qr_u8 + {7, OperandInfo242}, // Inst #1542 = MVE_VQSUBs16 + {7, OperandInfo242}, // Inst #1543 = MVE_VQSUBs32 + {7, OperandInfo242}, // Inst #1544 = MVE_VQSUBs8 + {7, OperandInfo242}, // Inst #1545 = MVE_VQSUBu16 + {7, OperandInfo242}, // Inst #1546 = MVE_VQSUBu32 + {7, OperandInfo242}, // Inst #1547 = MVE_VQSUBu8 + {6, OperandInfo243}, // Inst #1548 = MVE_VREV16_8 + {6, OperandInfo243}, // Inst #1549 = MVE_VREV32_16 + {6, OperandInfo243}, // Inst #1550 = MVE_VREV32_8 + {6, OperandInfo295}, // Inst #1551 = MVE_VREV64_16 + {6, OperandInfo295}, // Inst #1552 = MVE_VREV64_32 + {6, OperandInfo295}, // Inst #1553 = MVE_VREV64_8 + {7, OperandInfo242}, // Inst #1554 = MVE_VRHADDs16 + {7, OperandInfo242}, // Inst #1555 = MVE_VRHADDs32 + {7, OperandInfo242}, // Inst #1556 = MVE_VRHADDs8 + {7, OperandInfo242}, // Inst #1557 = MVE_VRHADDu16 + {7, OperandInfo242}, // Inst #1558 = MVE_VRHADDu32 + {7, OperandInfo242}, // Inst #1559 = MVE_VRHADDu8 + {6, OperandInfo243}, // Inst #1560 = MVE_VRINTf16A + {6, OperandInfo243}, // Inst #1561 = MVE_VRINTf16M + {6, OperandInfo243}, // Inst #1562 = MVE_VRINTf16N + {6, OperandInfo243}, // Inst #1563 = MVE_VRINTf16P + {6, OperandInfo243}, // Inst #1564 = MVE_VRINTf16X + {6, OperandInfo243}, // Inst #1565 = MVE_VRINTf16Z + {6, OperandInfo243}, // Inst #1566 = MVE_VRINTf32A + {6, OperandInfo243}, // Inst #1567 = MVE_VRINTf32M + {6, OperandInfo243}, // Inst #1568 = MVE_VRINTf32N + {6, OperandInfo243}, // Inst #1569 = MVE_VRINTf32P + {6, OperandInfo243}, // Inst #1570 = MVE_VRINTf32X + {6, OperandInfo243}, // Inst #1571 = MVE_VRINTf32Z + {9, OperandInfo279}, // Inst #1572 = MVE_VRMLALDAVHas32 + {9, OperandInfo279}, // Inst #1573 = MVE_VRMLALDAVHau32 + {9, OperandInfo279}, // Inst #1574 = MVE_VRMLALDAVHaxs32 + {7, OperandInfo280}, // Inst #1575 = MVE_VRMLALDAVHs32 + {7, OperandInfo280}, // Inst #1576 = MVE_VRMLALDAVHu32 + {7, OperandInfo280}, // Inst #1577 = MVE_VRMLALDAVHxs32 + {9, OperandInfo279}, // Inst #1578 = MVE_VRMLSLDAVHas32 + {9, OperandInfo279}, // Inst #1579 = MVE_VRMLSLDAVHaxs32 + {7, OperandInfo280}, // Inst #1580 = MVE_VRMLSLDAVHs32 + {7, OperandInfo280}, // Inst #1581 = MVE_VRMLSLDAVHxs32 + {7, OperandInfo242}, // Inst #1582 = MVE_VRMULHs16 + {7, OperandInfo242}, // Inst #1583 = MVE_VRMULHs32 + {7, OperandInfo242}, // Inst #1584 = MVE_VRMULHs8 + {7, OperandInfo242}, // Inst #1585 = MVE_VRMULHu16 + {7, OperandInfo242}, // Inst #1586 = MVE_VRMULHu32 + {7, OperandInfo242}, // Inst #1587 = MVE_VRMULHu8 + {7, OperandInfo242}, // Inst #1588 = MVE_VRSHL_by_vecs16 + {7, OperandInfo242}, // Inst #1589 = MVE_VRSHL_by_vecs32 + {7, OperandInfo242}, // Inst #1590 = MVE_VRSHL_by_vecs8 + {7, OperandInfo242}, // Inst #1591 = MVE_VRSHL_by_vecu16 + {7, OperandInfo242}, // Inst #1592 = MVE_VRSHL_by_vecu32 + {7, OperandInfo242}, // Inst #1593 = MVE_VRSHL_by_vecu8 + {6, OperandInfo293}, // Inst #1594 = MVE_VRSHL_qrs16 + {6, OperandInfo293}, // Inst #1595 = MVE_VRSHL_qrs32 + {6, OperandInfo293}, // Inst #1596 = MVE_VRSHL_qrs8 + {6, OperandInfo293}, // Inst #1597 = MVE_VRSHL_qru16 + {6, OperandInfo293}, // Inst #1598 = MVE_VRSHL_qru32 + {6, OperandInfo293}, // Inst #1599 = MVE_VRSHL_qru8 + {7, OperandInfo294}, // Inst #1600 = MVE_VRSHRNi16bh + {7, OperandInfo294}, // Inst #1601 = MVE_VRSHRNi16th + {7, OperandInfo294}, // Inst #1602 = MVE_VRSHRNi32bh + {7, OperandInfo294}, // Inst #1603 = MVE_VRSHRNi32th + {7, OperandInfo259}, // Inst #1604 = MVE_VRSHR_imms16 + {7, OperandInfo259}, // Inst #1605 = MVE_VRSHR_imms32 + {7, OperandInfo259}, // Inst #1606 = MVE_VRSHR_imms8 + {7, OperandInfo259}, // Inst #1607 = MVE_VRSHR_immu16 + {7, OperandInfo259}, // Inst #1608 = MVE_VRSHR_immu32 + {7, OperandInfo259}, // Inst #1609 = MVE_VRSHR_immu8 + {9, OperandInfo244}, // Inst #1610 = MVE_VSBC + {8, OperandInfo245}, // Inst #1611 = MVE_VSBCI + {8, OperandInfo296}, // Inst #1612 = MVE_VSHLC + {7, OperandInfo259}, // Inst #1613 = MVE_VSHLL_imms16bh + {7, OperandInfo259}, // Inst #1614 = MVE_VSHLL_imms16th + {7, OperandInfo259}, // Inst #1615 = MVE_VSHLL_imms8bh + {7, OperandInfo259}, // Inst #1616 = MVE_VSHLL_imms8th + {7, OperandInfo259}, // Inst #1617 = MVE_VSHLL_immu16bh + {7, OperandInfo259}, // Inst #1618 = MVE_VSHLL_immu16th + {7, OperandInfo259}, // Inst #1619 = MVE_VSHLL_immu8bh + {7, OperandInfo259}, // Inst #1620 = MVE_VSHLL_immu8th + {6, OperandInfo243}, // Inst #1621 = MVE_VSHLL_lws16bh + {6, OperandInfo243}, // Inst #1622 = MVE_VSHLL_lws16th + {6, OperandInfo243}, // Inst #1623 = MVE_VSHLL_lws8bh + {6, OperandInfo243}, // Inst #1624 = MVE_VSHLL_lws8th + {6, OperandInfo243}, // Inst #1625 = MVE_VSHLL_lwu16bh + {6, OperandInfo243}, // Inst #1626 = MVE_VSHLL_lwu16th + {6, OperandInfo243}, // Inst #1627 = MVE_VSHLL_lwu8bh + {6, OperandInfo243}, // Inst #1628 = MVE_VSHLL_lwu8th + {7, OperandInfo242}, // Inst #1629 = MVE_VSHL_by_vecs16 + {7, OperandInfo242}, // Inst #1630 = MVE_VSHL_by_vecs32 + {7, OperandInfo242}, // Inst #1631 = MVE_VSHL_by_vecs8 + {7, OperandInfo242}, // Inst #1632 = MVE_VSHL_by_vecu16 + {7, OperandInfo242}, // Inst #1633 = MVE_VSHL_by_vecu32 + {7, OperandInfo242}, // Inst #1634 = MVE_VSHL_by_vecu8 + {7, OperandInfo259}, // Inst #1635 = MVE_VSHL_immi16 + {7, OperandInfo259}, // Inst #1636 = MVE_VSHL_immi32 + {7, OperandInfo259}, // Inst #1637 = MVE_VSHL_immi8 + {6, OperandInfo293}, // Inst #1638 = MVE_VSHL_qrs16 + {6, OperandInfo293}, // Inst #1639 = MVE_VSHL_qrs32 + {6, OperandInfo293}, // Inst #1640 = MVE_VSHL_qrs8 + {6, OperandInfo293}, // Inst #1641 = MVE_VSHL_qru16 + {6, OperandInfo293}, // Inst #1642 = MVE_VSHL_qru32 + {6, OperandInfo293}, // Inst #1643 = MVE_VSHL_qru8 + {7, OperandInfo294}, // Inst #1644 = MVE_VSHRNi16bh + {7, OperandInfo294}, // Inst #1645 = MVE_VSHRNi16th + {7, OperandInfo294}, // Inst #1646 = MVE_VSHRNi32bh + {7, OperandInfo294}, // Inst #1647 = MVE_VSHRNi32th + {7, OperandInfo259}, // Inst #1648 = MVE_VSHR_imms16 + {7, OperandInfo259}, // Inst #1649 = MVE_VSHR_imms32 + {7, OperandInfo259}, // Inst #1650 = MVE_VSHR_imms8 + {7, OperandInfo259}, // Inst #1651 = MVE_VSHR_immu16 + {7, OperandInfo259}, // Inst #1652 = MVE_VSHR_immu32 + {7, OperandInfo259}, // Inst #1653 = MVE_VSHR_immu8 + {7, OperandInfo294}, // Inst #1654 = MVE_VSLIimm16 + {7, OperandInfo294}, // Inst #1655 = MVE_VSLIimm32 + {7, OperandInfo294}, // Inst #1656 = MVE_VSLIimm8 + {7, OperandInfo294}, // Inst #1657 = MVE_VSRIimm16 + {7, OperandInfo294}, // Inst #1658 = MVE_VSRIimm32 + {7, OperandInfo294}, // Inst #1659 = MVE_VSRIimm8 + {2, OperandInfo297}, // Inst #1660 = MVE_VST20_16 + {3, OperandInfo298}, // Inst #1661 = MVE_VST20_16_wb + {2, OperandInfo297}, // Inst #1662 = MVE_VST20_32 + {3, OperandInfo298}, // Inst #1663 = MVE_VST20_32_wb + {2, OperandInfo297}, // Inst #1664 = MVE_VST20_8 + {3, OperandInfo298}, // Inst #1665 = MVE_VST20_8_wb + {2, OperandInfo297}, // Inst #1666 = MVE_VST21_16 + {3, OperandInfo298}, // Inst #1667 = MVE_VST21_16_wb + {2, OperandInfo297}, // Inst #1668 = MVE_VST21_32 + {3, OperandInfo298}, // Inst #1669 = MVE_VST21_32_wb + {2, OperandInfo297}, // Inst #1670 = MVE_VST21_8 + {3, OperandInfo298}, // Inst #1671 = MVE_VST21_8_wb + {2, OperandInfo299}, // Inst #1672 = MVE_VST40_16 + {3, OperandInfo300}, // Inst #1673 = MVE_VST40_16_wb + {2, OperandInfo299}, // Inst #1674 = MVE_VST40_32 + {3, OperandInfo300}, // Inst #1675 = MVE_VST40_32_wb + {2, OperandInfo299}, // Inst #1676 = MVE_VST40_8 + {3, OperandInfo300}, // Inst #1677 = MVE_VST40_8_wb + {2, OperandInfo299}, // Inst #1678 = MVE_VST41_16 + {3, OperandInfo300}, // Inst #1679 = MVE_VST41_16_wb + {2, OperandInfo299}, // Inst #1680 = MVE_VST41_32 + {3, OperandInfo300}, // Inst #1681 = MVE_VST41_32_wb + {2, OperandInfo299}, // Inst #1682 = MVE_VST41_8 + {3, OperandInfo300}, // Inst #1683 = MVE_VST41_8_wb + {2, OperandInfo299}, // Inst #1684 = MVE_VST42_16 + {3, OperandInfo300}, // Inst #1685 = MVE_VST42_16_wb + {2, OperandInfo299}, // Inst #1686 = MVE_VST42_32 + {3, OperandInfo300}, // Inst #1687 = MVE_VST42_32_wb + {2, OperandInfo299}, // Inst #1688 = MVE_VST42_8 + {3, OperandInfo300}, // Inst #1689 = MVE_VST42_8_wb + {2, OperandInfo299}, // Inst #1690 = MVE_VST43_16 + {3, OperandInfo300}, // Inst #1691 = MVE_VST43_16_wb + {2, OperandInfo299}, // Inst #1692 = MVE_VST43_32 + {3, OperandInfo300}, // Inst #1693 = MVE_VST43_32_wb + {2, OperandInfo299}, // Inst #1694 = MVE_VST43_8 + {3, OperandInfo300}, // Inst #1695 = MVE_VST43_8_wb + {6, OperandInfo269}, // Inst #1696 = MVE_VSTRB16 + {7, OperandInfo270}, // Inst #1697 = MVE_VSTRB16_post + {7, OperandInfo270}, // Inst #1698 = MVE_VSTRB16_pre + {6, OperandInfo301}, // Inst #1699 = MVE_VSTRB16_rq + {6, OperandInfo269}, // Inst #1700 = MVE_VSTRB32 + {7, OperandInfo270}, // Inst #1701 = MVE_VSTRB32_post + {7, OperandInfo270}, // Inst #1702 = MVE_VSTRB32_pre + {6, OperandInfo301}, // Inst #1703 = MVE_VSTRB32_rq + {6, OperandInfo301}, // Inst #1704 = MVE_VSTRB8_rq + {6, OperandInfo272}, // Inst #1705 = MVE_VSTRBU8 + {7, OperandInfo273}, // Inst #1706 = MVE_VSTRBU8_post + {7, OperandInfo273}, // Inst #1707 = MVE_VSTRBU8_pre + {6, OperandInfo302}, // Inst #1708 = MVE_VSTRD64_qi + {7, OperandInfo303}, // Inst #1709 = MVE_VSTRD64_qi_pre + {6, OperandInfo301}, // Inst #1710 = MVE_VSTRD64_rq + {6, OperandInfo301}, // Inst #1711 = MVE_VSTRD64_rq_u + {6, OperandInfo301}, // Inst #1712 = MVE_VSTRH16_rq + {6, OperandInfo301}, // Inst #1713 = MVE_VSTRH16_rq_u + {6, OperandInfo269}, // Inst #1714 = MVE_VSTRH32 + {7, OperandInfo270}, // Inst #1715 = MVE_VSTRH32_post + {7, OperandInfo270}, // Inst #1716 = MVE_VSTRH32_pre + {6, OperandInfo301}, // Inst #1717 = MVE_VSTRH32_rq + {6, OperandInfo301}, // Inst #1718 = MVE_VSTRH32_rq_u + {6, OperandInfo272}, // Inst #1719 = MVE_VSTRHU16 + {7, OperandInfo273}, // Inst #1720 = MVE_VSTRHU16_post + {7, OperandInfo273}, // Inst #1721 = MVE_VSTRHU16_pre + {6, OperandInfo302}, // Inst #1722 = MVE_VSTRW32_qi + {7, OperandInfo303}, // Inst #1723 = MVE_VSTRW32_qi_pre + {6, OperandInfo301}, // Inst #1724 = MVE_VSTRW32_rq + {6, OperandInfo301}, // Inst #1725 = MVE_VSTRW32_rq_u + {6, OperandInfo272}, // Inst #1726 = MVE_VSTRWU32 + {7, OperandInfo273}, // Inst #1727 = MVE_VSTRWU32_post + {7, OperandInfo273}, // Inst #1728 = MVE_VSTRWU32_pre + {7, OperandInfo250}, // Inst #1729 = MVE_VSUB_qr_f16 + {7, OperandInfo250}, // Inst #1730 = MVE_VSUB_qr_f32 + {7, OperandInfo250}, // Inst #1731 = MVE_VSUB_qr_i16 + {7, OperandInfo250}, // Inst #1732 = MVE_VSUB_qr_i32 + {7, OperandInfo250}, // Inst #1733 = MVE_VSUB_qr_i8 + {7, OperandInfo242}, // Inst #1734 = MVE_VSUBf16 + {7, OperandInfo242}, // Inst #1735 = MVE_VSUBf32 + {7, OperandInfo242}, // Inst #1736 = MVE_VSUBi16 + {7, OperandInfo242}, // Inst #1737 = MVE_VSUBi32 + {7, OperandInfo242}, // Inst #1738 = MVE_VSUBi8 + {3, OperandInfo127}, // Inst #1739 = MVE_WLSTP_16 + {3, OperandInfo127}, // Inst #1740 = MVE_WLSTP_32 + {3, OperandInfo127}, // Inst #1741 = MVE_WLSTP_64 + {3, OperandInfo127}, // Inst #1742 = MVE_WLSTP_8 + {5, OperandInfo226}, // Inst #1743 = MVNi + {5, OperandInfo87}, // Inst #1744 = MVNr + {6, OperandInfo228}, // Inst #1745 = MVNsi + {7, OperandInfo304}, // Inst #1746 = MVNsr + {3, OperandInfo305}, // Inst #1747 = NEON_VMAXNMNDf + {3, OperandInfo305}, // Inst #1748 = NEON_VMAXNMNDh + {3, OperandInfo306}, // Inst #1749 = NEON_VMAXNMNQf + {3, OperandInfo306}, // Inst #1750 = NEON_VMAXNMNQh + {3, OperandInfo305}, // Inst #1751 = NEON_VMINNMNDf + {3, OperandInfo305}, // Inst #1752 = NEON_VMINNMNDh + {3, OperandInfo306}, // Inst #1753 = NEON_VMINNMNQf + {3, OperandInfo306}, // Inst #1754 = NEON_VMINNMNQh + {6, OperandInfo50}, // Inst #1755 = ORRri + {6, OperandInfo150}, // Inst #1756 = ORRrr + {7, OperandInfo151}, // Inst #1757 = ORRrsi + {8, OperandInfo153}, // Inst #1758 = ORRrsr + {6, OperandInfo307}, // Inst #1759 = PKHBT + {6, OperandInfo307}, // Inst #1760 = PKHTB + {2, OperandInfo308}, // Inst #1761 = PLDWi12 + {3, OperandInfo309}, // Inst #1762 = PLDWrs + {2, OperandInfo308}, // Inst #1763 = PLDi12 + {3, OperandInfo309}, // Inst #1764 = PLDrs + {2, OperandInfo308}, // Inst #1765 = PLIi12 + {3, OperandInfo309}, // Inst #1766 = PLIrs + {5, OperandInfo310}, // Inst #1767 = QADD + {5, OperandInfo310}, // Inst #1768 = QADD16 + {5, OperandInfo310}, // Inst #1769 = QADD8 + {5, OperandInfo310}, // Inst #1770 = QASX + {5, OperandInfo310}, // Inst #1771 = QDADD + {5, OperandInfo310}, // Inst #1772 = QDSUB + {5, OperandInfo310}, // Inst #1773 = QSAX + {5, OperandInfo310}, // Inst #1774 = QSUB + {5, OperandInfo310}, // Inst #1775 = QSUB16 + {5, OperandInfo310}, // Inst #1776 = QSUB8 + {4, OperandInfo194}, // Inst #1777 = RBIT + {4, OperandInfo194}, // Inst #1778 = REV + {4, OperandInfo194}, // Inst #1779 = REV16 + {4, OperandInfo194}, // Inst #1780 = REVSH + {1, OperandInfo77}, // Inst #1781 = RFEDA + {1, OperandInfo77}, // Inst #1782 = RFEDA_UPD + {1, OperandInfo77}, // Inst #1783 = RFEDB + {1, OperandInfo77}, // Inst #1784 = RFEDB_UPD + {1, OperandInfo77}, // Inst #1785 = RFEIA + {1, OperandInfo77}, // Inst #1786 = RFEIA_UPD + {1, OperandInfo77}, // Inst #1787 = RFEIB + {1, OperandInfo77}, // Inst #1788 = RFEIB_UPD + {6, OperandInfo50}, // Inst #1789 = RSBri + {6, OperandInfo150}, // Inst #1790 = RSBrr + {7, OperandInfo151}, // Inst #1791 = RSBrsi + {8, OperandInfo153}, // Inst #1792 = RSBrsr + {6, OperandInfo50}, // Inst #1793 = RSCri + {6, OperandInfo150}, // Inst #1794 = RSCrr + {7, OperandInfo151}, // Inst #1795 = RSCrsi + {8, OperandInfo153}, // Inst #1796 = RSCrsr + {5, OperandInfo310}, // Inst #1797 = SADD16 + {5, OperandInfo310}, // Inst #1798 = SADD8 + {5, OperandInfo310}, // Inst #1799 = SASX + {0, NULL}, // Inst #1800 = SB + {6, OperandInfo50}, // Inst #1801 = SBCri + {6, OperandInfo150}, // Inst #1802 = SBCrr + {7, OperandInfo151}, // Inst #1803 = SBCrsi + {8, OperandInfo152}, // Inst #1804 = SBCrsr + {6, OperandInfo311}, // Inst #1805 = SBFX + {5, OperandInfo46}, // Inst #1806 = SDIV + {5, OperandInfo46}, // Inst #1807 = SEL + {1, OperandInfo2}, // Inst #1808 = SETEND + {1, OperandInfo2}, // Inst #1809 = SETPAN + {4, OperandInfo159}, // Inst #1810 = SHA1C + {2, OperandInfo155}, // Inst #1811 = SHA1H + {4, OperandInfo159}, // Inst #1812 = SHA1M + {4, OperandInfo159}, // Inst #1813 = SHA1P + {4, OperandInfo159}, // Inst #1814 = SHA1SU0 + {3, OperandInfo154}, // Inst #1815 = SHA1SU1 + {4, OperandInfo159}, // Inst #1816 = SHA256H + {4, OperandInfo159}, // Inst #1817 = SHA256H2 + {3, OperandInfo154}, // Inst #1818 = SHA256SU0 + {4, OperandInfo159}, // Inst #1819 = SHA256SU1 + {5, OperandInfo310}, // Inst #1820 = SHADD16 + {5, OperandInfo310}, // Inst #1821 = SHADD8 + {5, OperandInfo310}, // Inst #1822 = SHASX + {5, OperandInfo310}, // Inst #1823 = SHSAX + {5, OperandInfo310}, // Inst #1824 = SHSUB16 + {5, OperandInfo310}, // Inst #1825 = SHSUB8 + {3, OperandInfo199}, // Inst #1826 = SMC + {6, OperandInfo312}, // Inst #1827 = SMLABB + {6, OperandInfo312}, // Inst #1828 = SMLABT + {6, OperandInfo312}, // Inst #1829 = SMLAD + {6, OperandInfo312}, // Inst #1830 = SMLADX + {9, OperandInfo313}, // Inst #1831 = SMLAL + {8, OperandInfo314}, // Inst #1832 = SMLALBB + {8, OperandInfo314}, // Inst #1833 = SMLALBT + {8, OperandInfo314}, // Inst #1834 = SMLALD + {8, OperandInfo314}, // Inst #1835 = SMLALDX + {8, OperandInfo314}, // Inst #1836 = SMLALTB + {8, OperandInfo314}, // Inst #1837 = SMLALTT + {6, OperandInfo312}, // Inst #1838 = SMLATB + {6, OperandInfo312}, // Inst #1839 = SMLATT + {6, OperandInfo312}, // Inst #1840 = SMLAWB + {6, OperandInfo312}, // Inst #1841 = SMLAWT + {6, OperandInfo312}, // Inst #1842 = SMLSD + {6, OperandInfo312}, // Inst #1843 = SMLSDX + {8, OperandInfo314}, // Inst #1844 = SMLSLD + {8, OperandInfo314}, // Inst #1845 = SMLSLDX + {6, OperandInfo224}, // Inst #1846 = SMMLA + {6, OperandInfo224}, // Inst #1847 = SMMLAR + {6, OperandInfo224}, // Inst #1848 = SMMLS + {6, OperandInfo224}, // Inst #1849 = SMMLSR + {5, OperandInfo46}, // Inst #1850 = SMMUL + {5, OperandInfo46}, // Inst #1851 = SMMULR + {5, OperandInfo310}, // Inst #1852 = SMUAD + {5, OperandInfo310}, // Inst #1853 = SMUADX + {5, OperandInfo46}, // Inst #1854 = SMULBB + {5, OperandInfo46}, // Inst #1855 = SMULBT + {7, OperandInfo315}, // Inst #1856 = SMULL + {5, OperandInfo46}, // Inst #1857 = SMULTB + {5, OperandInfo46}, // Inst #1858 = SMULTT + {5, OperandInfo46}, // Inst #1859 = SMULWB + {5, OperandInfo46}, // Inst #1860 = SMULWT + {5, OperandInfo310}, // Inst #1861 = SMUSD + {5, OperandInfo310}, // Inst #1862 = SMUSDX + {1, OperandInfo2}, // Inst #1863 = SRSDA + {1, OperandInfo2}, // Inst #1864 = SRSDA_UPD + {1, OperandInfo2}, // Inst #1865 = SRSDB + {1, OperandInfo2}, // Inst #1866 = SRSDB_UPD + {1, OperandInfo2}, // Inst #1867 = SRSIA + {1, OperandInfo2}, // Inst #1868 = SRSIA_UPD + {1, OperandInfo2}, // Inst #1869 = SRSIB + {1, OperandInfo2}, // Inst #1870 = SRSIB_UPD + {6, OperandInfo316}, // Inst #1871 = SSAT + {5, OperandInfo317}, // Inst #1872 = SSAT16 + {5, OperandInfo310}, // Inst #1873 = SSAX + {5, OperandInfo310}, // Inst #1874 = SSUB16 + {5, OperandInfo310}, // Inst #1875 = SSUB8 + {4, OperandInfo205}, // Inst #1876 = STC2L_OFFSET + {4, OperandInfo206}, // Inst #1877 = STC2L_OPTION + {4, OperandInfo205}, // Inst #1878 = STC2L_POST + {4, OperandInfo205}, // Inst #1879 = STC2L_PRE + {4, OperandInfo205}, // Inst #1880 = STC2_OFFSET + {4, OperandInfo206}, // Inst #1881 = STC2_OPTION + {4, OperandInfo205}, // Inst #1882 = STC2_POST + {4, OperandInfo205}, // Inst #1883 = STC2_PRE + {6, OperandInfo207}, // Inst #1884 = STCL_OFFSET + {6, OperandInfo208}, // Inst #1885 = STCL_OPTION + {6, OperandInfo207}, // Inst #1886 = STCL_POST + {6, OperandInfo207}, // Inst #1887 = STCL_PRE + {6, OperandInfo207}, // Inst #1888 = STC_OFFSET + {6, OperandInfo208}, // Inst #1889 = STC_OPTION + {6, OperandInfo207}, // Inst #1890 = STC_POST + {6, OperandInfo207}, // Inst #1891 = STC_PRE + {4, OperandInfo66}, // Inst #1892 = STL + {4, OperandInfo66}, // Inst #1893 = STLB + {5, OperandInfo318}, // Inst #1894 = STLEX + {5, OperandInfo318}, // Inst #1895 = STLEXB + {5, OperandInfo319}, // Inst #1896 = STLEXD + {5, OperandInfo318}, // Inst #1897 = STLEXH + {4, OperandInfo66}, // Inst #1898 = STLH + {4, OperandInfo203}, // Inst #1899 = STMDA + {5, OperandInfo65}, // Inst #1900 = STMDA_UPD + {4, OperandInfo203}, // Inst #1901 = STMDB + {5, OperandInfo65}, // Inst #1902 = STMDB_UPD + {4, OperandInfo203}, // Inst #1903 = STMIA + {5, OperandInfo65}, // Inst #1904 = STMIA_UPD + {4, OperandInfo203}, // Inst #1905 = STMIB + {5, OperandInfo65}, // Inst #1906 = STMIB_UPD + {7, OperandInfo320}, // Inst #1907 = STRBT_POST_IMM + {7, OperandInfo320}, // Inst #1908 = STRBT_POST_REG + {7, OperandInfo321}, // Inst #1909 = STRB_POST_IMM + {7, OperandInfo321}, // Inst #1910 = STRB_POST_REG + {6, OperandInfo322}, // Inst #1911 = STRB_PRE_IMM + {7, OperandInfo321}, // Inst #1912 = STRB_PRE_REG + {5, OperandInfo211}, // Inst #1913 = STRBi12 + {6, OperandInfo212}, // Inst #1914 = STRBrs + {7, OperandInfo213}, // Inst #1915 = STRD + {8, OperandInfo323}, // Inst #1916 = STRD_POST + {8, OperandInfo323}, // Inst #1917 = STRD_PRE + {5, OperandInfo318}, // Inst #1918 = STREX + {5, OperandInfo318}, // Inst #1919 = STREXB + {5, OperandInfo319}, // Inst #1920 = STREXD + {5, OperandInfo318}, // Inst #1921 = STREXH + {6, OperandInfo215}, // Inst #1922 = STRH + {6, OperandInfo324}, // Inst #1923 = STRHTi + {7, OperandInfo320}, // Inst #1924 = STRHTr + {7, OperandInfo325}, // Inst #1925 = STRH_POST + {7, OperandInfo325}, // Inst #1926 = STRH_PRE + {7, OperandInfo320}, // Inst #1927 = STRT_POST_IMM + {7, OperandInfo320}, // Inst #1928 = STRT_POST_REG + {7, OperandInfo321}, // Inst #1929 = STR_POST_IMM + {7, OperandInfo321}, // Inst #1930 = STR_POST_REG + {6, OperandInfo322}, // Inst #1931 = STR_PRE_IMM + {7, OperandInfo321}, // Inst #1932 = STR_PRE_REG + {5, OperandInfo86}, // Inst #1933 = STRi12 + {6, OperandInfo218}, // Inst #1934 = STRrs + {6, OperandInfo50}, // Inst #1935 = SUBri + {6, OperandInfo150}, // Inst #1936 = SUBrr + {7, OperandInfo151}, // Inst #1937 = SUBrsi + {8, OperandInfo153}, // Inst #1938 = SUBrsr + {3, OperandInfo199}, // Inst #1939 = SVC + {5, OperandInfo326}, // Inst #1940 = SWP + {5, OperandInfo326}, // Inst #1941 = SWPB + {6, OperandInfo327}, // Inst #1942 = SXTAB + {6, OperandInfo327}, // Inst #1943 = SXTAB16 + {6, OperandInfo327}, // Inst #1944 = SXTAH + {5, OperandInfo328}, // Inst #1945 = SXTB + {5, OperandInfo328}, // Inst #1946 = SXTB16 + {5, OperandInfo328}, // Inst #1947 = SXTH + {4, OperandInfo67}, // Inst #1948 = TEQri + {4, OperandInfo194}, // Inst #1949 = TEQrr + {5, OperandInfo195}, // Inst #1950 = TEQrsi + {6, OperandInfo196}, // Inst #1951 = TEQrsr + {0, NULL}, // Inst #1952 = TRAP + {0, NULL}, // Inst #1953 = TRAPNaCl + {1, OperandInfo2}, // Inst #1954 = TSB + {4, OperandInfo67}, // Inst #1955 = TSTri + {4, OperandInfo194}, // Inst #1956 = TSTrr + {5, OperandInfo195}, // Inst #1957 = TSTrsi + {6, OperandInfo196}, // Inst #1958 = TSTrsr + {5, OperandInfo310}, // Inst #1959 = UADD16 + {5, OperandInfo310}, // Inst #1960 = UADD8 + {5, OperandInfo310}, // Inst #1961 = UASX + {6, OperandInfo311}, // Inst #1962 = UBFX + {1, OperandInfo2}, // Inst #1963 = UDF + {5, OperandInfo46}, // Inst #1964 = UDIV + {5, OperandInfo310}, // Inst #1965 = UHADD16 + {5, OperandInfo310}, // Inst #1966 = UHADD8 + {5, OperandInfo310}, // Inst #1967 = UHASX + {5, OperandInfo310}, // Inst #1968 = UHSAX + {5, OperandInfo310}, // Inst #1969 = UHSUB16 + {5, OperandInfo310}, // Inst #1970 = UHSUB8 + {8, OperandInfo329}, // Inst #1971 = UMAAL + {9, OperandInfo313}, // Inst #1972 = UMLAL + {7, OperandInfo315}, // Inst #1973 = UMULL + {5, OperandInfo310}, // Inst #1974 = UQADD16 + {5, OperandInfo310}, // Inst #1975 = UQADD8 + {5, OperandInfo310}, // Inst #1976 = UQASX + {5, OperandInfo310}, // Inst #1977 = UQSAX + {5, OperandInfo310}, // Inst #1978 = UQSUB16 + {5, OperandInfo310}, // Inst #1979 = UQSUB8 + {5, OperandInfo46}, // Inst #1980 = USAD8 + {6, OperandInfo224}, // Inst #1981 = USADA8 + {6, OperandInfo316}, // Inst #1982 = USAT + {5, OperandInfo317}, // Inst #1983 = USAT16 + {5, OperandInfo310}, // Inst #1984 = USAX + {5, OperandInfo310}, // Inst #1985 = USUB16 + {5, OperandInfo310}, // Inst #1986 = USUB8 + {6, OperandInfo327}, // Inst #1987 = UXTAB + {6, OperandInfo327}, // Inst #1988 = UXTAB16 + {6, OperandInfo327}, // Inst #1989 = UXTAH + {5, OperandInfo328}, // Inst #1990 = UXTB + {5, OperandInfo328}, // Inst #1991 = UXTB16 + {5, OperandInfo328}, // Inst #1992 = UXTH + {6, OperandInfo330}, // Inst #1993 = VABALsv2i64 + {6, OperandInfo330}, // Inst #1994 = VABALsv4i32 + {6, OperandInfo330}, // Inst #1995 = VABALsv8i16 + {6, OperandInfo330}, // Inst #1996 = VABALuv2i64 + {6, OperandInfo330}, // Inst #1997 = VABALuv4i32 + {6, OperandInfo330}, // Inst #1998 = VABALuv8i16 + {6, OperandInfo331}, // Inst #1999 = VABAsv16i8 + {6, OperandInfo332}, // Inst #2000 = VABAsv2i32 + {6, OperandInfo332}, // Inst #2001 = VABAsv4i16 + {6, OperandInfo331}, // Inst #2002 = VABAsv4i32 + {6, OperandInfo331}, // Inst #2003 = VABAsv8i16 + {6, OperandInfo332}, // Inst #2004 = VABAsv8i8 + {6, OperandInfo331}, // Inst #2005 = VABAuv16i8 + {6, OperandInfo332}, // Inst #2006 = VABAuv2i32 + {6, OperandInfo332}, // Inst #2007 = VABAuv4i16 + {6, OperandInfo331}, // Inst #2008 = VABAuv4i32 + {6, OperandInfo331}, // Inst #2009 = VABAuv8i16 + {6, OperandInfo332}, // Inst #2010 = VABAuv8i8 + {5, OperandInfo333}, // Inst #2011 = VABDLsv2i64 + {5, OperandInfo333}, // Inst #2012 = VABDLsv4i32 + {5, OperandInfo333}, // Inst #2013 = VABDLsv8i16 + {5, OperandInfo333}, // Inst #2014 = VABDLuv2i64 + {5, OperandInfo333}, // Inst #2015 = VABDLuv4i32 + {5, OperandInfo333}, // Inst #2016 = VABDLuv8i16 + {5, OperandInfo334}, // Inst #2017 = VABDfd + {5, OperandInfo335}, // Inst #2018 = VABDfq + {5, OperandInfo334}, // Inst #2019 = VABDhd + {5, OperandInfo335}, // Inst #2020 = VABDhq + {5, OperandInfo335}, // Inst #2021 = VABDsv16i8 + {5, OperandInfo334}, // Inst #2022 = VABDsv2i32 + {5, OperandInfo334}, // Inst #2023 = VABDsv4i16 + {5, OperandInfo335}, // Inst #2024 = VABDsv4i32 + {5, OperandInfo335}, // Inst #2025 = VABDsv8i16 + {5, OperandInfo334}, // Inst #2026 = VABDsv8i8 + {5, OperandInfo335}, // Inst #2027 = VABDuv16i8 + {5, OperandInfo334}, // Inst #2028 = VABDuv2i32 + {5, OperandInfo334}, // Inst #2029 = VABDuv4i16 + {5, OperandInfo335}, // Inst #2030 = VABDuv4i32 + {5, OperandInfo335}, // Inst #2031 = VABDuv8i16 + {5, OperandInfo334}, // Inst #2032 = VABDuv8i8 + {4, OperandInfo336}, // Inst #2033 = VABSD + {4, OperandInfo337}, // Inst #2034 = VABSH + {4, OperandInfo338}, // Inst #2035 = VABSS + {4, OperandInfo336}, // Inst #2036 = VABSfd + {4, OperandInfo339}, // Inst #2037 = VABSfq + {4, OperandInfo336}, // Inst #2038 = VABShd + {4, OperandInfo339}, // Inst #2039 = VABShq + {4, OperandInfo339}, // Inst #2040 = VABSv16i8 + {4, OperandInfo336}, // Inst #2041 = VABSv2i32 + {4, OperandInfo336}, // Inst #2042 = VABSv4i16 + {4, OperandInfo339}, // Inst #2043 = VABSv4i32 + {4, OperandInfo339}, // Inst #2044 = VABSv8i16 + {4, OperandInfo336}, // Inst #2045 = VABSv8i8 + {5, OperandInfo334}, // Inst #2046 = VACGEfd + {5, OperandInfo335}, // Inst #2047 = VACGEfq + {5, OperandInfo334}, // Inst #2048 = VACGEhd + {5, OperandInfo335}, // Inst #2049 = VACGEhq + {5, OperandInfo334}, // Inst #2050 = VACGTfd + {5, OperandInfo335}, // Inst #2051 = VACGTfq + {5, OperandInfo334}, // Inst #2052 = VACGThd + {5, OperandInfo335}, // Inst #2053 = VACGThq + {5, OperandInfo334}, // Inst #2054 = VADDD + {5, OperandInfo340}, // Inst #2055 = VADDH + {5, OperandInfo341}, // Inst #2056 = VADDHNv2i32 + {5, OperandInfo341}, // Inst #2057 = VADDHNv4i16 + {5, OperandInfo341}, // Inst #2058 = VADDHNv8i8 + {5, OperandInfo333}, // Inst #2059 = VADDLsv2i64 + {5, OperandInfo333}, // Inst #2060 = VADDLsv4i32 + {5, OperandInfo333}, // Inst #2061 = VADDLsv8i16 + {5, OperandInfo333}, // Inst #2062 = VADDLuv2i64 + {5, OperandInfo333}, // Inst #2063 = VADDLuv4i32 + {5, OperandInfo333}, // Inst #2064 = VADDLuv8i16 + {5, OperandInfo342}, // Inst #2065 = VADDS + {5, OperandInfo343}, // Inst #2066 = VADDWsv2i64 + {5, OperandInfo343}, // Inst #2067 = VADDWsv4i32 + {5, OperandInfo343}, // Inst #2068 = VADDWsv8i16 + {5, OperandInfo343}, // Inst #2069 = VADDWuv2i64 + {5, OperandInfo343}, // Inst #2070 = VADDWuv4i32 + {5, OperandInfo343}, // Inst #2071 = VADDWuv8i16 + {5, OperandInfo334}, // Inst #2072 = VADDfd + {5, OperandInfo335}, // Inst #2073 = VADDfq + {5, OperandInfo334}, // Inst #2074 = VADDhd + {5, OperandInfo335}, // Inst #2075 = VADDhq + {5, OperandInfo335}, // Inst #2076 = VADDv16i8 + {5, OperandInfo334}, // Inst #2077 = VADDv1i64 + {5, OperandInfo334}, // Inst #2078 = VADDv2i32 + {5, OperandInfo335}, // Inst #2079 = VADDv2i64 + {5, OperandInfo334}, // Inst #2080 = VADDv4i16 + {5, OperandInfo335}, // Inst #2081 = VADDv4i32 + {5, OperandInfo335}, // Inst #2082 = VADDv8i16 + {5, OperandInfo334}, // Inst #2083 = VADDv8i8 + {5, OperandInfo334}, // Inst #2084 = VANDd + {5, OperandInfo335}, // Inst #2085 = VANDq + {4, OperandInfo159}, // Inst #2086 = VBF16MALBQ + {5, OperandInfo344}, // Inst #2087 = VBF16MALBQI + {4, OperandInfo159}, // Inst #2088 = VBF16MALTQ + {5, OperandInfo344}, // Inst #2089 = VBF16MALTQI + {5, OperandInfo334}, // Inst #2090 = VBICd + {5, OperandInfo345}, // Inst #2091 = VBICiv2i32 + {5, OperandInfo345}, // Inst #2092 = VBICiv4i16 + {5, OperandInfo346}, // Inst #2093 = VBICiv4i32 + {5, OperandInfo346}, // Inst #2094 = VBICiv8i16 + {5, OperandInfo335}, // Inst #2095 = VBICq + {6, OperandInfo332}, // Inst #2096 = VBIFd + {6, OperandInfo331}, // Inst #2097 = VBIFq + {6, OperandInfo332}, // Inst #2098 = VBITd + {6, OperandInfo331}, // Inst #2099 = VBITq + {6, OperandInfo332}, // Inst #2100 = VBSLd + {6, OperandInfo331}, // Inst #2101 = VBSLq + {6, OperandInfo347}, // Inst #2102 = VBSPd + {6, OperandInfo348}, // Inst #2103 = VBSPq + {4, OperandInfo349}, // Inst #2104 = VCADDv2f32 + {4, OperandInfo349}, // Inst #2105 = VCADDv4f16 + {4, OperandInfo350}, // Inst #2106 = VCADDv4f32 + {4, OperandInfo350}, // Inst #2107 = VCADDv8f16 + {5, OperandInfo334}, // Inst #2108 = VCEQfd + {5, OperandInfo335}, // Inst #2109 = VCEQfq + {5, OperandInfo334}, // Inst #2110 = VCEQhd + {5, OperandInfo335}, // Inst #2111 = VCEQhq + {5, OperandInfo335}, // Inst #2112 = VCEQv16i8 + {5, OperandInfo334}, // Inst #2113 = VCEQv2i32 + {5, OperandInfo334}, // Inst #2114 = VCEQv4i16 + {5, OperandInfo335}, // Inst #2115 = VCEQv4i32 + {5, OperandInfo335}, // Inst #2116 = VCEQv8i16 + {5, OperandInfo334}, // Inst #2117 = VCEQv8i8 + {4, OperandInfo339}, // Inst #2118 = VCEQzv16i8 + {4, OperandInfo336}, // Inst #2119 = VCEQzv2f32 + {4, OperandInfo336}, // Inst #2120 = VCEQzv2i32 + {4, OperandInfo336}, // Inst #2121 = VCEQzv4f16 + {4, OperandInfo339}, // Inst #2122 = VCEQzv4f32 + {4, OperandInfo336}, // Inst #2123 = VCEQzv4i16 + {4, OperandInfo339}, // Inst #2124 = VCEQzv4i32 + {4, OperandInfo339}, // Inst #2125 = VCEQzv8f16 + {4, OperandInfo339}, // Inst #2126 = VCEQzv8i16 + {4, OperandInfo336}, // Inst #2127 = VCEQzv8i8 + {5, OperandInfo334}, // Inst #2128 = VCGEfd + {5, OperandInfo335}, // Inst #2129 = VCGEfq + {5, OperandInfo334}, // Inst #2130 = VCGEhd + {5, OperandInfo335}, // Inst #2131 = VCGEhq + {5, OperandInfo335}, // Inst #2132 = VCGEsv16i8 + {5, OperandInfo334}, // Inst #2133 = VCGEsv2i32 + {5, OperandInfo334}, // Inst #2134 = VCGEsv4i16 + {5, OperandInfo335}, // Inst #2135 = VCGEsv4i32 + {5, OperandInfo335}, // Inst #2136 = VCGEsv8i16 + {5, OperandInfo334}, // Inst #2137 = VCGEsv8i8 + {5, OperandInfo335}, // Inst #2138 = VCGEuv16i8 + {5, OperandInfo334}, // Inst #2139 = VCGEuv2i32 + {5, OperandInfo334}, // Inst #2140 = VCGEuv4i16 + {5, OperandInfo335}, // Inst #2141 = VCGEuv4i32 + {5, OperandInfo335}, // Inst #2142 = VCGEuv8i16 + {5, OperandInfo334}, // Inst #2143 = VCGEuv8i8 + {4, OperandInfo339}, // Inst #2144 = VCGEzv16i8 + {4, OperandInfo336}, // Inst #2145 = VCGEzv2f32 + {4, OperandInfo336}, // Inst #2146 = VCGEzv2i32 + {4, OperandInfo336}, // Inst #2147 = VCGEzv4f16 + {4, OperandInfo339}, // Inst #2148 = VCGEzv4f32 + {4, OperandInfo336}, // Inst #2149 = VCGEzv4i16 + {4, OperandInfo339}, // Inst #2150 = VCGEzv4i32 + {4, OperandInfo339}, // Inst #2151 = VCGEzv8f16 + {4, OperandInfo339}, // Inst #2152 = VCGEzv8i16 + {4, OperandInfo336}, // Inst #2153 = VCGEzv8i8 + {5, OperandInfo334}, // Inst #2154 = VCGTfd + {5, OperandInfo335}, // Inst #2155 = VCGTfq + {5, OperandInfo334}, // Inst #2156 = VCGThd + {5, OperandInfo335}, // Inst #2157 = VCGThq + {5, OperandInfo335}, // Inst #2158 = VCGTsv16i8 + {5, OperandInfo334}, // Inst #2159 = VCGTsv2i32 + {5, OperandInfo334}, // Inst #2160 = VCGTsv4i16 + {5, OperandInfo335}, // Inst #2161 = VCGTsv4i32 + {5, OperandInfo335}, // Inst #2162 = VCGTsv8i16 + {5, OperandInfo334}, // Inst #2163 = VCGTsv8i8 + {5, OperandInfo335}, // Inst #2164 = VCGTuv16i8 + {5, OperandInfo334}, // Inst #2165 = VCGTuv2i32 + {5, OperandInfo334}, // Inst #2166 = VCGTuv4i16 + {5, OperandInfo335}, // Inst #2167 = VCGTuv4i32 + {5, OperandInfo335}, // Inst #2168 = VCGTuv8i16 + {5, OperandInfo334}, // Inst #2169 = VCGTuv8i8 + {4, OperandInfo339}, // Inst #2170 = VCGTzv16i8 + {4, OperandInfo336}, // Inst #2171 = VCGTzv2f32 + {4, OperandInfo336}, // Inst #2172 = VCGTzv2i32 + {4, OperandInfo336}, // Inst #2173 = VCGTzv4f16 + {4, OperandInfo339}, // Inst #2174 = VCGTzv4f32 + {4, OperandInfo336}, // Inst #2175 = VCGTzv4i16 + {4, OperandInfo339}, // Inst #2176 = VCGTzv4i32 + {4, OperandInfo339}, // Inst #2177 = VCGTzv8f16 + {4, OperandInfo339}, // Inst #2178 = VCGTzv8i16 + {4, OperandInfo336}, // Inst #2179 = VCGTzv8i8 + {4, OperandInfo339}, // Inst #2180 = VCLEzv16i8 + {4, OperandInfo336}, // Inst #2181 = VCLEzv2f32 + {4, OperandInfo336}, // Inst #2182 = VCLEzv2i32 + {4, OperandInfo336}, // Inst #2183 = VCLEzv4f16 + {4, OperandInfo339}, // Inst #2184 = VCLEzv4f32 + {4, OperandInfo336}, // Inst #2185 = VCLEzv4i16 + {4, OperandInfo339}, // Inst #2186 = VCLEzv4i32 + {4, OperandInfo339}, // Inst #2187 = VCLEzv8f16 + {4, OperandInfo339}, // Inst #2188 = VCLEzv8i16 + {4, OperandInfo336}, // Inst #2189 = VCLEzv8i8 + {4, OperandInfo339}, // Inst #2190 = VCLSv16i8 + {4, OperandInfo336}, // Inst #2191 = VCLSv2i32 + {4, OperandInfo336}, // Inst #2192 = VCLSv4i16 + {4, OperandInfo339}, // Inst #2193 = VCLSv4i32 + {4, OperandInfo339}, // Inst #2194 = VCLSv8i16 + {4, OperandInfo336}, // Inst #2195 = VCLSv8i8 + {4, OperandInfo339}, // Inst #2196 = VCLTzv16i8 + {4, OperandInfo336}, // Inst #2197 = VCLTzv2f32 + {4, OperandInfo336}, // Inst #2198 = VCLTzv2i32 + {4, OperandInfo336}, // Inst #2199 = VCLTzv4f16 + {4, OperandInfo339}, // Inst #2200 = VCLTzv4f32 + {4, OperandInfo336}, // Inst #2201 = VCLTzv4i16 + {4, OperandInfo339}, // Inst #2202 = VCLTzv4i32 + {4, OperandInfo339}, // Inst #2203 = VCLTzv8f16 + {4, OperandInfo339}, // Inst #2204 = VCLTzv8i16 + {4, OperandInfo336}, // Inst #2205 = VCLTzv8i8 + {4, OperandInfo339}, // Inst #2206 = VCLZv16i8 + {4, OperandInfo336}, // Inst #2207 = VCLZv2i32 + {4, OperandInfo336}, // Inst #2208 = VCLZv4i16 + {4, OperandInfo339}, // Inst #2209 = VCLZv4i32 + {4, OperandInfo339}, // Inst #2210 = VCLZv8i16 + {4, OperandInfo336}, // Inst #2211 = VCLZv8i8 + {5, OperandInfo351}, // Inst #2212 = VCMLAv2f32 + {6, OperandInfo352}, // Inst #2213 = VCMLAv2f32_indexed + {5, OperandInfo351}, // Inst #2214 = VCMLAv4f16 + {6, OperandInfo353}, // Inst #2215 = VCMLAv4f16_indexed + {5, OperandInfo354}, // Inst #2216 = VCMLAv4f32 + {6, OperandInfo355}, // Inst #2217 = VCMLAv4f32_indexed + {5, OperandInfo354}, // Inst #2218 = VCMLAv8f16 + {6, OperandInfo356}, // Inst #2219 = VCMLAv8f16_indexed + {4, OperandInfo336}, // Inst #2220 = VCMPD + {4, OperandInfo336}, // Inst #2221 = VCMPED + {4, OperandInfo337}, // Inst #2222 = VCMPEH + {4, OperandInfo338}, // Inst #2223 = VCMPES + {3, OperandInfo357}, // Inst #2224 = VCMPEZD + {3, OperandInfo358}, // Inst #2225 = VCMPEZH + {3, OperandInfo359}, // Inst #2226 = VCMPEZS + {4, OperandInfo337}, // Inst #2227 = VCMPH + {4, OperandInfo338}, // Inst #2228 = VCMPS + {3, OperandInfo357}, // Inst #2229 = VCMPZD + {3, OperandInfo358}, // Inst #2230 = VCMPZH + {3, OperandInfo359}, // Inst #2231 = VCMPZS + {4, OperandInfo336}, // Inst #2232 = VCNTd + {4, OperandInfo339}, // Inst #2233 = VCNTq + {2, OperandInfo360}, // Inst #2234 = VCVTANSDf + {2, OperandInfo360}, // Inst #2235 = VCVTANSDh + {2, OperandInfo155}, // Inst #2236 = VCVTANSQf + {2, OperandInfo155}, // Inst #2237 = VCVTANSQh + {2, OperandInfo360}, // Inst #2238 = VCVTANUDf + {2, OperandInfo360}, // Inst #2239 = VCVTANUDh + {2, OperandInfo155}, // Inst #2240 = VCVTANUQf + {2, OperandInfo155}, // Inst #2241 = VCVTANUQh + {2, OperandInfo361}, // Inst #2242 = VCVTASD + {2, OperandInfo362}, // Inst #2243 = VCVTASH + {2, OperandInfo363}, // Inst #2244 = VCVTASS + {2, OperandInfo361}, // Inst #2245 = VCVTAUD + {2, OperandInfo362}, // Inst #2246 = VCVTAUH + {2, OperandInfo363}, // Inst #2247 = VCVTAUS + {4, OperandInfo364}, // Inst #2248 = VCVTBDH + {4, OperandInfo365}, // Inst #2249 = VCVTBHD + {4, OperandInfo338}, // Inst #2250 = VCVTBHS + {4, OperandInfo338}, // Inst #2251 = VCVTBSH + {4, OperandInfo365}, // Inst #2252 = VCVTDS + {2, OperandInfo360}, // Inst #2253 = VCVTMNSDf + {2, OperandInfo360}, // Inst #2254 = VCVTMNSDh + {2, OperandInfo155}, // Inst #2255 = VCVTMNSQf + {2, OperandInfo155}, // Inst #2256 = VCVTMNSQh + {2, OperandInfo360}, // Inst #2257 = VCVTMNUDf + {2, OperandInfo360}, // Inst #2258 = VCVTMNUDh + {2, OperandInfo155}, // Inst #2259 = VCVTMNUQf + {2, OperandInfo155}, // Inst #2260 = VCVTMNUQh + {2, OperandInfo361}, // Inst #2261 = VCVTMSD + {2, OperandInfo362}, // Inst #2262 = VCVTMSH + {2, OperandInfo363}, // Inst #2263 = VCVTMSS + {2, OperandInfo361}, // Inst #2264 = VCVTMUD + {2, OperandInfo362}, // Inst #2265 = VCVTMUH + {2, OperandInfo363}, // Inst #2266 = VCVTMUS + {2, OperandInfo360}, // Inst #2267 = VCVTNNSDf + {2, OperandInfo360}, // Inst #2268 = VCVTNNSDh + {2, OperandInfo155}, // Inst #2269 = VCVTNNSQf + {2, OperandInfo155}, // Inst #2270 = VCVTNNSQh + {2, OperandInfo360}, // Inst #2271 = VCVTNNUDf + {2, OperandInfo360}, // Inst #2272 = VCVTNNUDh + {2, OperandInfo155}, // Inst #2273 = VCVTNNUQf + {2, OperandInfo155}, // Inst #2274 = VCVTNNUQh + {2, OperandInfo361}, // Inst #2275 = VCVTNSD + {2, OperandInfo362}, // Inst #2276 = VCVTNSH + {2, OperandInfo363}, // Inst #2277 = VCVTNSS + {2, OperandInfo361}, // Inst #2278 = VCVTNUD + {2, OperandInfo362}, // Inst #2279 = VCVTNUH + {2, OperandInfo363}, // Inst #2280 = VCVTNUS + {2, OperandInfo360}, // Inst #2281 = VCVTPNSDf + {2, OperandInfo360}, // Inst #2282 = VCVTPNSDh + {2, OperandInfo155}, // Inst #2283 = VCVTPNSQf + {2, OperandInfo155}, // Inst #2284 = VCVTPNSQh + {2, OperandInfo360}, // Inst #2285 = VCVTPNUDf + {2, OperandInfo360}, // Inst #2286 = VCVTPNUDh + {2, OperandInfo155}, // Inst #2287 = VCVTPNUQf + {2, OperandInfo155}, // Inst #2288 = VCVTPNUQh + {2, OperandInfo361}, // Inst #2289 = VCVTPSD + {2, OperandInfo362}, // Inst #2290 = VCVTPSH + {2, OperandInfo363}, // Inst #2291 = VCVTPSS + {2, OperandInfo361}, // Inst #2292 = VCVTPUD + {2, OperandInfo362}, // Inst #2293 = VCVTPUH + {2, OperandInfo363}, // Inst #2294 = VCVTPUS + {4, OperandInfo364}, // Inst #2295 = VCVTSD + {4, OperandInfo364}, // Inst #2296 = VCVTTDH + {4, OperandInfo365}, // Inst #2297 = VCVTTHD + {4, OperandInfo338}, // Inst #2298 = VCVTTHS + {4, OperandInfo338}, // Inst #2299 = VCVTTSH + {4, OperandInfo160}, // Inst #2300 = VCVTf2h + {4, OperandInfo336}, // Inst #2301 = VCVTf2sd + {4, OperandInfo339}, // Inst #2302 = VCVTf2sq + {4, OperandInfo336}, // Inst #2303 = VCVTf2ud + {4, OperandInfo339}, // Inst #2304 = VCVTf2uq + {5, OperandInfo366}, // Inst #2305 = VCVTf2xsd + {5, OperandInfo367}, // Inst #2306 = VCVTf2xsq + {5, OperandInfo366}, // Inst #2307 = VCVTf2xud + {5, OperandInfo367}, // Inst #2308 = VCVTf2xuq + {4, OperandInfo368}, // Inst #2309 = VCVTh2f + {4, OperandInfo336}, // Inst #2310 = VCVTh2sd + {4, OperandInfo339}, // Inst #2311 = VCVTh2sq + {4, OperandInfo336}, // Inst #2312 = VCVTh2ud + {4, OperandInfo339}, // Inst #2313 = VCVTh2uq + {5, OperandInfo366}, // Inst #2314 = VCVTh2xsd + {5, OperandInfo367}, // Inst #2315 = VCVTh2xsq + {5, OperandInfo366}, // Inst #2316 = VCVTh2xud + {5, OperandInfo367}, // Inst #2317 = VCVTh2xuq + {4, OperandInfo336}, // Inst #2318 = VCVTs2fd + {4, OperandInfo339}, // Inst #2319 = VCVTs2fq + {4, OperandInfo336}, // Inst #2320 = VCVTs2hd + {4, OperandInfo339}, // Inst #2321 = VCVTs2hq + {4, OperandInfo336}, // Inst #2322 = VCVTu2fd + {4, OperandInfo339}, // Inst #2323 = VCVTu2fq + {4, OperandInfo336}, // Inst #2324 = VCVTu2hd + {4, OperandInfo339}, // Inst #2325 = VCVTu2hq + {5, OperandInfo366}, // Inst #2326 = VCVTxs2fd + {5, OperandInfo367}, // Inst #2327 = VCVTxs2fq + {5, OperandInfo366}, // Inst #2328 = VCVTxs2hd + {5, OperandInfo367}, // Inst #2329 = VCVTxs2hq + {5, OperandInfo366}, // Inst #2330 = VCVTxu2fd + {5, OperandInfo367}, // Inst #2331 = VCVTxu2fq + {5, OperandInfo366}, // Inst #2332 = VCVTxu2hd + {5, OperandInfo367}, // Inst #2333 = VCVTxu2hq + {5, OperandInfo334}, // Inst #2334 = VDIVD + {5, OperandInfo340}, // Inst #2335 = VDIVH + {5, OperandInfo342}, // Inst #2336 = VDIVS + {4, OperandInfo369}, // Inst #2337 = VDUP16d + {4, OperandInfo370}, // Inst #2338 = VDUP16q + {4, OperandInfo369}, // Inst #2339 = VDUP32d + {4, OperandInfo370}, // Inst #2340 = VDUP32q + {4, OperandInfo369}, // Inst #2341 = VDUP8d + {4, OperandInfo370}, // Inst #2342 = VDUP8q + {5, OperandInfo366}, // Inst #2343 = VDUPLN16d + {5, OperandInfo371}, // Inst #2344 = VDUPLN16q + {5, OperandInfo366}, // Inst #2345 = VDUPLN32d + {5, OperandInfo371}, // Inst #2346 = VDUPLN32q + {5, OperandInfo366}, // Inst #2347 = VDUPLN8d + {5, OperandInfo371}, // Inst #2348 = VDUPLN8q + {5, OperandInfo334}, // Inst #2349 = VEORd + {5, OperandInfo335}, // Inst #2350 = VEORq + {6, OperandInfo372}, // Inst #2351 = VEXTd16 + {6, OperandInfo372}, // Inst #2352 = VEXTd32 + {6, OperandInfo372}, // Inst #2353 = VEXTd8 + {6, OperandInfo373}, // Inst #2354 = VEXTq16 + {6, OperandInfo373}, // Inst #2355 = VEXTq32 + {6, OperandInfo373}, // Inst #2356 = VEXTq64 + {6, OperandInfo373}, // Inst #2357 = VEXTq8 + {6, OperandInfo332}, // Inst #2358 = VFMAD + {6, OperandInfo374}, // Inst #2359 = VFMAH + {3, OperandInfo375}, // Inst #2360 = VFMALD + {4, OperandInfo376}, // Inst #2361 = VFMALDI + {3, OperandInfo377}, // Inst #2362 = VFMALQ + {4, OperandInfo378}, // Inst #2363 = VFMALQI + {6, OperandInfo379}, // Inst #2364 = VFMAS + {6, OperandInfo332}, // Inst #2365 = VFMAfd + {6, OperandInfo331}, // Inst #2366 = VFMAfq + {6, OperandInfo332}, // Inst #2367 = VFMAhd + {6, OperandInfo331}, // Inst #2368 = VFMAhq + {6, OperandInfo332}, // Inst #2369 = VFMSD + {6, OperandInfo374}, // Inst #2370 = VFMSH + {3, OperandInfo375}, // Inst #2371 = VFMSLD + {4, OperandInfo376}, // Inst #2372 = VFMSLDI + {3, OperandInfo377}, // Inst #2373 = VFMSLQ + {4, OperandInfo378}, // Inst #2374 = VFMSLQI + {6, OperandInfo379}, // Inst #2375 = VFMSS + {6, OperandInfo332}, // Inst #2376 = VFMSfd + {6, OperandInfo331}, // Inst #2377 = VFMSfq + {6, OperandInfo332}, // Inst #2378 = VFMShd + {6, OperandInfo331}, // Inst #2379 = VFMShq + {6, OperandInfo332}, // Inst #2380 = VFNMAD + {6, OperandInfo374}, // Inst #2381 = VFNMAH + {6, OperandInfo379}, // Inst #2382 = VFNMAS + {6, OperandInfo332}, // Inst #2383 = VFNMSD + {6, OperandInfo374}, // Inst #2384 = VFNMSH + {6, OperandInfo379}, // Inst #2385 = VFNMSS + {3, OperandInfo305}, // Inst #2386 = VFP_VMAXNMD + {3, OperandInfo380}, // Inst #2387 = VFP_VMAXNMH + {3, OperandInfo381}, // Inst #2388 = VFP_VMAXNMS + {3, OperandInfo305}, // Inst #2389 = VFP_VMINNMD + {3, OperandInfo380}, // Inst #2390 = VFP_VMINNMH + {3, OperandInfo381}, // Inst #2391 = VFP_VMINNMS + {5, OperandInfo382}, // Inst #2392 = VGETLNi32 + {5, OperandInfo382}, // Inst #2393 = VGETLNs16 + {5, OperandInfo382}, // Inst #2394 = VGETLNs8 + {5, OperandInfo382}, // Inst #2395 = VGETLNu16 + {5, OperandInfo382}, // Inst #2396 = VGETLNu8 + {5, OperandInfo335}, // Inst #2397 = VHADDsv16i8 + {5, OperandInfo334}, // Inst #2398 = VHADDsv2i32 + {5, OperandInfo334}, // Inst #2399 = VHADDsv4i16 + {5, OperandInfo335}, // Inst #2400 = VHADDsv4i32 + {5, OperandInfo335}, // Inst #2401 = VHADDsv8i16 + {5, OperandInfo334}, // Inst #2402 = VHADDsv8i8 + {5, OperandInfo335}, // Inst #2403 = VHADDuv16i8 + {5, OperandInfo334}, // Inst #2404 = VHADDuv2i32 + {5, OperandInfo334}, // Inst #2405 = VHADDuv4i16 + {5, OperandInfo335}, // Inst #2406 = VHADDuv4i32 + {5, OperandInfo335}, // Inst #2407 = VHADDuv8i16 + {5, OperandInfo334}, // Inst #2408 = VHADDuv8i8 + {5, OperandInfo335}, // Inst #2409 = VHSUBsv16i8 + {5, OperandInfo334}, // Inst #2410 = VHSUBsv2i32 + {5, OperandInfo334}, // Inst #2411 = VHSUBsv4i16 + {5, OperandInfo335}, // Inst #2412 = VHSUBsv4i32 + {5, OperandInfo335}, // Inst #2413 = VHSUBsv8i16 + {5, OperandInfo334}, // Inst #2414 = VHSUBsv8i8 + {5, OperandInfo335}, // Inst #2415 = VHSUBuv16i8 + {5, OperandInfo334}, // Inst #2416 = VHSUBuv2i32 + {5, OperandInfo334}, // Inst #2417 = VHSUBuv4i16 + {5, OperandInfo335}, // Inst #2418 = VHSUBuv4i32 + {5, OperandInfo335}, // Inst #2419 = VHSUBuv8i16 + {5, OperandInfo334}, // Inst #2420 = VHSUBuv8i8 + {3, OperandInfo383}, // Inst #2421 = VINSH + {4, OperandInfo364}, // Inst #2422 = VJCVT + {5, OperandInfo98}, // Inst #2423 = VLD1DUPd16 + {6, OperandInfo384}, // Inst #2424 = VLD1DUPd16wb_fixed + {7, OperandInfo385}, // Inst #2425 = VLD1DUPd16wb_register + {5, OperandInfo98}, // Inst #2426 = VLD1DUPd32 + {6, OperandInfo384}, // Inst #2427 = VLD1DUPd32wb_fixed + {7, OperandInfo385}, // Inst #2428 = VLD1DUPd32wb_register + {5, OperandInfo98}, // Inst #2429 = VLD1DUPd8 + {6, OperandInfo384}, // Inst #2430 = VLD1DUPd8wb_fixed + {7, OperandInfo385}, // Inst #2431 = VLD1DUPd8wb_register + {5, OperandInfo386}, // Inst #2432 = VLD1DUPq16 + {6, OperandInfo387}, // Inst #2433 = VLD1DUPq16wb_fixed + {7, OperandInfo388}, // Inst #2434 = VLD1DUPq16wb_register + {5, OperandInfo386}, // Inst #2435 = VLD1DUPq32 + {6, OperandInfo387}, // Inst #2436 = VLD1DUPq32wb_fixed + {7, OperandInfo388}, // Inst #2437 = VLD1DUPq32wb_register + {5, OperandInfo386}, // Inst #2438 = VLD1DUPq8 + {6, OperandInfo387}, // Inst #2439 = VLD1DUPq8wb_fixed + {7, OperandInfo388}, // Inst #2440 = VLD1DUPq8wb_register + {7, OperandInfo389}, // Inst #2441 = VLD1LNd16 + {9, OperandInfo390}, // Inst #2442 = VLD1LNd16_UPD + {7, OperandInfo389}, // Inst #2443 = VLD1LNd32 + {9, OperandInfo390}, // Inst #2444 = VLD1LNd32_UPD + {7, OperandInfo389}, // Inst #2445 = VLD1LNd8 + {9, OperandInfo390}, // Inst #2446 = VLD1LNd8_UPD + {7, OperandInfo391}, // Inst #2447 = VLD1LNq16Pseudo + {9, OperandInfo392}, // Inst #2448 = VLD1LNq16Pseudo_UPD + {7, OperandInfo391}, // Inst #2449 = VLD1LNq32Pseudo + {9, OperandInfo392}, // Inst #2450 = VLD1LNq32Pseudo_UPD + {7, OperandInfo391}, // Inst #2451 = VLD1LNq8Pseudo + {9, OperandInfo392}, // Inst #2452 = VLD1LNq8Pseudo_UPD + {5, OperandInfo98}, // Inst #2453 = VLD1d16 + {5, OperandInfo98}, // Inst #2454 = VLD1d16Q + {5, OperandInfo393}, // Inst #2455 = VLD1d16QPseudo + {6, OperandInfo394}, // Inst #2456 = VLD1d16QPseudoWB_fixed + {7, OperandInfo395}, // Inst #2457 = VLD1d16QPseudoWB_register + {6, OperandInfo384}, // Inst #2458 = VLD1d16Qwb_fixed + {7, OperandInfo385}, // Inst #2459 = VLD1d16Qwb_register + {5, OperandInfo98}, // Inst #2460 = VLD1d16T + {5, OperandInfo393}, // Inst #2461 = VLD1d16TPseudo + {6, OperandInfo394}, // Inst #2462 = VLD1d16TPseudoWB_fixed + {7, OperandInfo395}, // Inst #2463 = VLD1d16TPseudoWB_register + {6, OperandInfo384}, // Inst #2464 = VLD1d16Twb_fixed + {7, OperandInfo385}, // Inst #2465 = VLD1d16Twb_register + {6, OperandInfo384}, // Inst #2466 = VLD1d16wb_fixed + {7, OperandInfo385}, // Inst #2467 = VLD1d16wb_register + {5, OperandInfo98}, // Inst #2468 = VLD1d32 + {5, OperandInfo98}, // Inst #2469 = VLD1d32Q + {5, OperandInfo393}, // Inst #2470 = VLD1d32QPseudo + {6, OperandInfo394}, // Inst #2471 = VLD1d32QPseudoWB_fixed + {7, OperandInfo395}, // Inst #2472 = VLD1d32QPseudoWB_register + {6, OperandInfo384}, // Inst #2473 = VLD1d32Qwb_fixed + {7, OperandInfo385}, // Inst #2474 = VLD1d32Qwb_register + {5, OperandInfo98}, // Inst #2475 = VLD1d32T + {5, OperandInfo393}, // Inst #2476 = VLD1d32TPseudo + {6, OperandInfo394}, // Inst #2477 = VLD1d32TPseudoWB_fixed + {7, OperandInfo395}, // Inst #2478 = VLD1d32TPseudoWB_register + {6, OperandInfo384}, // Inst #2479 = VLD1d32Twb_fixed + {7, OperandInfo385}, // Inst #2480 = VLD1d32Twb_register + {6, OperandInfo384}, // Inst #2481 = VLD1d32wb_fixed + {7, OperandInfo385}, // Inst #2482 = VLD1d32wb_register + {5, OperandInfo98}, // Inst #2483 = VLD1d64 + {5, OperandInfo98}, // Inst #2484 = VLD1d64Q + {5, OperandInfo393}, // Inst #2485 = VLD1d64QPseudo + {6, OperandInfo394}, // Inst #2486 = VLD1d64QPseudoWB_fixed + {7, OperandInfo395}, // Inst #2487 = VLD1d64QPseudoWB_register + {6, OperandInfo384}, // Inst #2488 = VLD1d64Qwb_fixed + {7, OperandInfo385}, // Inst #2489 = VLD1d64Qwb_register + {5, OperandInfo98}, // Inst #2490 = VLD1d64T + {5, OperandInfo393}, // Inst #2491 = VLD1d64TPseudo + {6, OperandInfo394}, // Inst #2492 = VLD1d64TPseudoWB_fixed + {7, OperandInfo395}, // Inst #2493 = VLD1d64TPseudoWB_register + {6, OperandInfo384}, // Inst #2494 = VLD1d64Twb_fixed + {7, OperandInfo385}, // Inst #2495 = VLD1d64Twb_register + {6, OperandInfo384}, // Inst #2496 = VLD1d64wb_fixed + {7, OperandInfo385}, // Inst #2497 = VLD1d64wb_register + {5, OperandInfo98}, // Inst #2498 = VLD1d8 + {5, OperandInfo98}, // Inst #2499 = VLD1d8Q + {5, OperandInfo393}, // Inst #2500 = VLD1d8QPseudo + {6, OperandInfo394}, // Inst #2501 = VLD1d8QPseudoWB_fixed + {7, OperandInfo395}, // Inst #2502 = VLD1d8QPseudoWB_register + {6, OperandInfo384}, // Inst #2503 = VLD1d8Qwb_fixed + {7, OperandInfo385}, // Inst #2504 = VLD1d8Qwb_register + {5, OperandInfo98}, // Inst #2505 = VLD1d8T + {5, OperandInfo393}, // Inst #2506 = VLD1d8TPseudo + {6, OperandInfo394}, // Inst #2507 = VLD1d8TPseudoWB_fixed + {7, OperandInfo395}, // Inst #2508 = VLD1d8TPseudoWB_register + {6, OperandInfo384}, // Inst #2509 = VLD1d8Twb_fixed + {7, OperandInfo385}, // Inst #2510 = VLD1d8Twb_register + {6, OperandInfo384}, // Inst #2511 = VLD1d8wb_fixed + {7, OperandInfo385}, // Inst #2512 = VLD1d8wb_register + {5, OperandInfo386}, // Inst #2513 = VLD1q16 + {6, OperandInfo396}, // Inst #2514 = VLD1q16HighQPseudo + {8, OperandInfo397}, // Inst #2515 = VLD1q16HighQPseudo_UPD + {6, OperandInfo396}, // Inst #2516 = VLD1q16HighTPseudo + {8, OperandInfo397}, // Inst #2517 = VLD1q16HighTPseudo_UPD + {8, OperandInfo397}, // Inst #2518 = VLD1q16LowQPseudo_UPD + {8, OperandInfo397}, // Inst #2519 = VLD1q16LowTPseudo_UPD + {6, OperandInfo387}, // Inst #2520 = VLD1q16wb_fixed + {7, OperandInfo388}, // Inst #2521 = VLD1q16wb_register + {5, OperandInfo386}, // Inst #2522 = VLD1q32 + {6, OperandInfo396}, // Inst #2523 = VLD1q32HighQPseudo + {8, OperandInfo397}, // Inst #2524 = VLD1q32HighQPseudo_UPD + {6, OperandInfo396}, // Inst #2525 = VLD1q32HighTPseudo + {8, OperandInfo397}, // Inst #2526 = VLD1q32HighTPseudo_UPD + {8, OperandInfo397}, // Inst #2527 = VLD1q32LowQPseudo_UPD + {8, OperandInfo397}, // Inst #2528 = VLD1q32LowTPseudo_UPD + {6, OperandInfo387}, // Inst #2529 = VLD1q32wb_fixed + {7, OperandInfo388}, // Inst #2530 = VLD1q32wb_register + {5, OperandInfo386}, // Inst #2531 = VLD1q64 + {6, OperandInfo396}, // Inst #2532 = VLD1q64HighQPseudo + {8, OperandInfo397}, // Inst #2533 = VLD1q64HighQPseudo_UPD + {6, OperandInfo396}, // Inst #2534 = VLD1q64HighTPseudo + {8, OperandInfo397}, // Inst #2535 = VLD1q64HighTPseudo_UPD + {8, OperandInfo397}, // Inst #2536 = VLD1q64LowQPseudo_UPD + {8, OperandInfo397}, // Inst #2537 = VLD1q64LowTPseudo_UPD + {6, OperandInfo387}, // Inst #2538 = VLD1q64wb_fixed + {7, OperandInfo388}, // Inst #2539 = VLD1q64wb_register + {5, OperandInfo386}, // Inst #2540 = VLD1q8 + {6, OperandInfo396}, // Inst #2541 = VLD1q8HighQPseudo + {8, OperandInfo397}, // Inst #2542 = VLD1q8HighQPseudo_UPD + {6, OperandInfo396}, // Inst #2543 = VLD1q8HighTPseudo + {8, OperandInfo397}, // Inst #2544 = VLD1q8HighTPseudo_UPD + {8, OperandInfo397}, // Inst #2545 = VLD1q8LowQPseudo_UPD + {8, OperandInfo397}, // Inst #2546 = VLD1q8LowTPseudo_UPD + {6, OperandInfo387}, // Inst #2547 = VLD1q8wb_fixed + {7, OperandInfo388}, // Inst #2548 = VLD1q8wb_register + {5, OperandInfo386}, // Inst #2549 = VLD2DUPd16 + {6, OperandInfo387}, // Inst #2550 = VLD2DUPd16wb_fixed + {7, OperandInfo388}, // Inst #2551 = VLD2DUPd16wb_register + {5, OperandInfo398}, // Inst #2552 = VLD2DUPd16x2 + {6, OperandInfo399}, // Inst #2553 = VLD2DUPd16x2wb_fixed + {7, OperandInfo400}, // Inst #2554 = VLD2DUPd16x2wb_register + {5, OperandInfo386}, // Inst #2555 = VLD2DUPd32 + {6, OperandInfo387}, // Inst #2556 = VLD2DUPd32wb_fixed + {7, OperandInfo388}, // Inst #2557 = VLD2DUPd32wb_register + {5, OperandInfo398}, // Inst #2558 = VLD2DUPd32x2 + {6, OperandInfo399}, // Inst #2559 = VLD2DUPd32x2wb_fixed + {7, OperandInfo400}, // Inst #2560 = VLD2DUPd32x2wb_register + {5, OperandInfo386}, // Inst #2561 = VLD2DUPd8 + {6, OperandInfo387}, // Inst #2562 = VLD2DUPd8wb_fixed + {7, OperandInfo388}, // Inst #2563 = VLD2DUPd8wb_register + {5, OperandInfo398}, // Inst #2564 = VLD2DUPd8x2 + {6, OperandInfo399}, // Inst #2565 = VLD2DUPd8x2wb_fixed + {7, OperandInfo400}, // Inst #2566 = VLD2DUPd8x2wb_register + {5, OperandInfo393}, // Inst #2567 = VLD2DUPq16EvenPseudo + {5, OperandInfo393}, // Inst #2568 = VLD2DUPq16OddPseudo + {6, OperandInfo394}, // Inst #2569 = VLD2DUPq16OddPseudoWB_fixed + {7, OperandInfo401}, // Inst #2570 = VLD2DUPq16OddPseudoWB_register + {5, OperandInfo393}, // Inst #2571 = VLD2DUPq32EvenPseudo + {5, OperandInfo393}, // Inst #2572 = VLD2DUPq32OddPseudo + {6, OperandInfo394}, // Inst #2573 = VLD2DUPq32OddPseudoWB_fixed + {7, OperandInfo401}, // Inst #2574 = VLD2DUPq32OddPseudoWB_register + {5, OperandInfo393}, // Inst #2575 = VLD2DUPq8EvenPseudo + {5, OperandInfo393}, // Inst #2576 = VLD2DUPq8OddPseudo + {6, OperandInfo394}, // Inst #2577 = VLD2DUPq8OddPseudoWB_fixed + {7, OperandInfo401}, // Inst #2578 = VLD2DUPq8OddPseudoWB_register + {9, OperandInfo402}, // Inst #2579 = VLD2LNd16 + {7, OperandInfo391}, // Inst #2580 = VLD2LNd16Pseudo + {9, OperandInfo392}, // Inst #2581 = VLD2LNd16Pseudo_UPD + {11, OperandInfo403}, // Inst #2582 = VLD2LNd16_UPD + {9, OperandInfo402}, // Inst #2583 = VLD2LNd32 + {7, OperandInfo391}, // Inst #2584 = VLD2LNd32Pseudo + {9, OperandInfo392}, // Inst #2585 = VLD2LNd32Pseudo_UPD + {11, OperandInfo403}, // Inst #2586 = VLD2LNd32_UPD + {9, OperandInfo402}, // Inst #2587 = VLD2LNd8 + {7, OperandInfo391}, // Inst #2588 = VLD2LNd8Pseudo + {9, OperandInfo392}, // Inst #2589 = VLD2LNd8Pseudo_UPD + {11, OperandInfo403}, // Inst #2590 = VLD2LNd8_UPD + {9, OperandInfo402}, // Inst #2591 = VLD2LNq16 + {7, OperandInfo404}, // Inst #2592 = VLD2LNq16Pseudo + {9, OperandInfo405}, // Inst #2593 = VLD2LNq16Pseudo_UPD + {11, OperandInfo403}, // Inst #2594 = VLD2LNq16_UPD + {9, OperandInfo402}, // Inst #2595 = VLD2LNq32 + {7, OperandInfo404}, // Inst #2596 = VLD2LNq32Pseudo + {9, OperandInfo405}, // Inst #2597 = VLD2LNq32Pseudo_UPD + {11, OperandInfo403}, // Inst #2598 = VLD2LNq32_UPD + {5, OperandInfo386}, // Inst #2599 = VLD2b16 + {6, OperandInfo387}, // Inst #2600 = VLD2b16wb_fixed + {7, OperandInfo388}, // Inst #2601 = VLD2b16wb_register + {5, OperandInfo386}, // Inst #2602 = VLD2b32 + {6, OperandInfo387}, // Inst #2603 = VLD2b32wb_fixed + {7, OperandInfo388}, // Inst #2604 = VLD2b32wb_register + {5, OperandInfo386}, // Inst #2605 = VLD2b8 + {6, OperandInfo387}, // Inst #2606 = VLD2b8wb_fixed + {7, OperandInfo388}, // Inst #2607 = VLD2b8wb_register + {5, OperandInfo386}, // Inst #2608 = VLD2d16 + {6, OperandInfo387}, // Inst #2609 = VLD2d16wb_fixed + {7, OperandInfo388}, // Inst #2610 = VLD2d16wb_register + {5, OperandInfo386}, // Inst #2611 = VLD2d32 + {6, OperandInfo387}, // Inst #2612 = VLD2d32wb_fixed + {7, OperandInfo388}, // Inst #2613 = VLD2d32wb_register + {5, OperandInfo386}, // Inst #2614 = VLD2d8 + {6, OperandInfo387}, // Inst #2615 = VLD2d8wb_fixed + {7, OperandInfo388}, // Inst #2616 = VLD2d8wb_register + {5, OperandInfo98}, // Inst #2617 = VLD2q16 + {5, OperandInfo393}, // Inst #2618 = VLD2q16Pseudo + {6, OperandInfo394}, // Inst #2619 = VLD2q16PseudoWB_fixed + {7, OperandInfo395}, // Inst #2620 = VLD2q16PseudoWB_register + {6, OperandInfo384}, // Inst #2621 = VLD2q16wb_fixed + {7, OperandInfo385}, // Inst #2622 = VLD2q16wb_register + {5, OperandInfo98}, // Inst #2623 = VLD2q32 + {5, OperandInfo393}, // Inst #2624 = VLD2q32Pseudo + {6, OperandInfo394}, // Inst #2625 = VLD2q32PseudoWB_fixed + {7, OperandInfo395}, // Inst #2626 = VLD2q32PseudoWB_register + {6, OperandInfo384}, // Inst #2627 = VLD2q32wb_fixed + {7, OperandInfo385}, // Inst #2628 = VLD2q32wb_register + {5, OperandInfo98}, // Inst #2629 = VLD2q8 + {5, OperandInfo393}, // Inst #2630 = VLD2q8Pseudo + {6, OperandInfo394}, // Inst #2631 = VLD2q8PseudoWB_fixed + {7, OperandInfo395}, // Inst #2632 = VLD2q8PseudoWB_register + {6, OperandInfo384}, // Inst #2633 = VLD2q8wb_fixed + {7, OperandInfo385}, // Inst #2634 = VLD2q8wb_register + {7, OperandInfo406}, // Inst #2635 = VLD3DUPd16 + {5, OperandInfo393}, // Inst #2636 = VLD3DUPd16Pseudo + {7, OperandInfo401}, // Inst #2637 = VLD3DUPd16Pseudo_UPD + {9, OperandInfo407}, // Inst #2638 = VLD3DUPd16_UPD + {7, OperandInfo406}, // Inst #2639 = VLD3DUPd32 + {5, OperandInfo393}, // Inst #2640 = VLD3DUPd32Pseudo + {7, OperandInfo401}, // Inst #2641 = VLD3DUPd32Pseudo_UPD + {9, OperandInfo407}, // Inst #2642 = VLD3DUPd32_UPD + {7, OperandInfo406}, // Inst #2643 = VLD3DUPd8 + {5, OperandInfo393}, // Inst #2644 = VLD3DUPd8Pseudo + {7, OperandInfo401}, // Inst #2645 = VLD3DUPd8Pseudo_UPD + {9, OperandInfo407}, // Inst #2646 = VLD3DUPd8_UPD + {7, OperandInfo406}, // Inst #2647 = VLD3DUPq16 + {6, OperandInfo396}, // Inst #2648 = VLD3DUPq16EvenPseudo + {6, OperandInfo396}, // Inst #2649 = VLD3DUPq16OddPseudo + {8, OperandInfo397}, // Inst #2650 = VLD3DUPq16OddPseudo_UPD + {9, OperandInfo407}, // Inst #2651 = VLD3DUPq16_UPD + {7, OperandInfo406}, // Inst #2652 = VLD3DUPq32 + {6, OperandInfo396}, // Inst #2653 = VLD3DUPq32EvenPseudo + {6, OperandInfo396}, // Inst #2654 = VLD3DUPq32OddPseudo + {8, OperandInfo397}, // Inst #2655 = VLD3DUPq32OddPseudo_UPD + {9, OperandInfo407}, // Inst #2656 = VLD3DUPq32_UPD + {7, OperandInfo406}, // Inst #2657 = VLD3DUPq8 + {6, OperandInfo396}, // Inst #2658 = VLD3DUPq8EvenPseudo + {6, OperandInfo396}, // Inst #2659 = VLD3DUPq8OddPseudo + {8, OperandInfo397}, // Inst #2660 = VLD3DUPq8OddPseudo_UPD + {9, OperandInfo407}, // Inst #2661 = VLD3DUPq8_UPD + {11, OperandInfo408}, // Inst #2662 = VLD3LNd16 + {7, OperandInfo404}, // Inst #2663 = VLD3LNd16Pseudo + {9, OperandInfo405}, // Inst #2664 = VLD3LNd16Pseudo_UPD + {13, OperandInfo409}, // Inst #2665 = VLD3LNd16_UPD + {11, OperandInfo408}, // Inst #2666 = VLD3LNd32 + {7, OperandInfo404}, // Inst #2667 = VLD3LNd32Pseudo + {9, OperandInfo405}, // Inst #2668 = VLD3LNd32Pseudo_UPD + {13, OperandInfo409}, // Inst #2669 = VLD3LNd32_UPD + {11, OperandInfo408}, // Inst #2670 = VLD3LNd8 + {7, OperandInfo404}, // Inst #2671 = VLD3LNd8Pseudo + {9, OperandInfo405}, // Inst #2672 = VLD3LNd8Pseudo_UPD + {13, OperandInfo409}, // Inst #2673 = VLD3LNd8_UPD + {11, OperandInfo408}, // Inst #2674 = VLD3LNq16 + {7, OperandInfo410}, // Inst #2675 = VLD3LNq16Pseudo + {9, OperandInfo411}, // Inst #2676 = VLD3LNq16Pseudo_UPD + {13, OperandInfo409}, // Inst #2677 = VLD3LNq16_UPD + {11, OperandInfo408}, // Inst #2678 = VLD3LNq32 + {7, OperandInfo410}, // Inst #2679 = VLD3LNq32Pseudo + {9, OperandInfo411}, // Inst #2680 = VLD3LNq32Pseudo_UPD + {13, OperandInfo409}, // Inst #2681 = VLD3LNq32_UPD + {7, OperandInfo406}, // Inst #2682 = VLD3d16 + {5, OperandInfo393}, // Inst #2683 = VLD3d16Pseudo + {7, OperandInfo401}, // Inst #2684 = VLD3d16Pseudo_UPD + {9, OperandInfo407}, // Inst #2685 = VLD3d16_UPD + {7, OperandInfo406}, // Inst #2686 = VLD3d32 + {5, OperandInfo393}, // Inst #2687 = VLD3d32Pseudo + {7, OperandInfo401}, // Inst #2688 = VLD3d32Pseudo_UPD + {9, OperandInfo407}, // Inst #2689 = VLD3d32_UPD + {7, OperandInfo406}, // Inst #2690 = VLD3d8 + {5, OperandInfo393}, // Inst #2691 = VLD3d8Pseudo + {7, OperandInfo401}, // Inst #2692 = VLD3d8Pseudo_UPD + {9, OperandInfo407}, // Inst #2693 = VLD3d8_UPD + {7, OperandInfo406}, // Inst #2694 = VLD3q16 + {8, OperandInfo397}, // Inst #2695 = VLD3q16Pseudo_UPD + {9, OperandInfo407}, // Inst #2696 = VLD3q16_UPD + {6, OperandInfo396}, // Inst #2697 = VLD3q16oddPseudo + {8, OperandInfo397}, // Inst #2698 = VLD3q16oddPseudo_UPD + {7, OperandInfo406}, // Inst #2699 = VLD3q32 + {8, OperandInfo397}, // Inst #2700 = VLD3q32Pseudo_UPD + {9, OperandInfo407}, // Inst #2701 = VLD3q32_UPD + {6, OperandInfo396}, // Inst #2702 = VLD3q32oddPseudo + {8, OperandInfo397}, // Inst #2703 = VLD3q32oddPseudo_UPD + {7, OperandInfo406}, // Inst #2704 = VLD3q8 + {8, OperandInfo397}, // Inst #2705 = VLD3q8Pseudo_UPD + {9, OperandInfo407}, // Inst #2706 = VLD3q8_UPD + {6, OperandInfo396}, // Inst #2707 = VLD3q8oddPseudo + {8, OperandInfo397}, // Inst #2708 = VLD3q8oddPseudo_UPD + {8, OperandInfo412}, // Inst #2709 = VLD4DUPd16 + {5, OperandInfo393}, // Inst #2710 = VLD4DUPd16Pseudo + {7, OperandInfo401}, // Inst #2711 = VLD4DUPd16Pseudo_UPD + {10, OperandInfo413}, // Inst #2712 = VLD4DUPd16_UPD + {8, OperandInfo412}, // Inst #2713 = VLD4DUPd32 + {5, OperandInfo393}, // Inst #2714 = VLD4DUPd32Pseudo + {7, OperandInfo401}, // Inst #2715 = VLD4DUPd32Pseudo_UPD + {10, OperandInfo413}, // Inst #2716 = VLD4DUPd32_UPD + {8, OperandInfo412}, // Inst #2717 = VLD4DUPd8 + {5, OperandInfo393}, // Inst #2718 = VLD4DUPd8Pseudo + {7, OperandInfo401}, // Inst #2719 = VLD4DUPd8Pseudo_UPD + {10, OperandInfo413}, // Inst #2720 = VLD4DUPd8_UPD + {8, OperandInfo412}, // Inst #2721 = VLD4DUPq16 + {6, OperandInfo396}, // Inst #2722 = VLD4DUPq16EvenPseudo + {6, OperandInfo396}, // Inst #2723 = VLD4DUPq16OddPseudo + {8, OperandInfo397}, // Inst #2724 = VLD4DUPq16OddPseudo_UPD + {10, OperandInfo413}, // Inst #2725 = VLD4DUPq16_UPD + {8, OperandInfo412}, // Inst #2726 = VLD4DUPq32 + {6, OperandInfo396}, // Inst #2727 = VLD4DUPq32EvenPseudo + {6, OperandInfo396}, // Inst #2728 = VLD4DUPq32OddPseudo + {8, OperandInfo397}, // Inst #2729 = VLD4DUPq32OddPseudo_UPD + {10, OperandInfo413}, // Inst #2730 = VLD4DUPq32_UPD + {8, OperandInfo412}, // Inst #2731 = VLD4DUPq8 + {6, OperandInfo396}, // Inst #2732 = VLD4DUPq8EvenPseudo + {6, OperandInfo396}, // Inst #2733 = VLD4DUPq8OddPseudo + {8, OperandInfo397}, // Inst #2734 = VLD4DUPq8OddPseudo_UPD + {10, OperandInfo413}, // Inst #2735 = VLD4DUPq8_UPD + {13, OperandInfo414}, // Inst #2736 = VLD4LNd16 + {7, OperandInfo404}, // Inst #2737 = VLD4LNd16Pseudo + {9, OperandInfo405}, // Inst #2738 = VLD4LNd16Pseudo_UPD + {15, OperandInfo415}, // Inst #2739 = VLD4LNd16_UPD + {13, OperandInfo414}, // Inst #2740 = VLD4LNd32 + {7, OperandInfo404}, // Inst #2741 = VLD4LNd32Pseudo + {9, OperandInfo405}, // Inst #2742 = VLD4LNd32Pseudo_UPD + {15, OperandInfo415}, // Inst #2743 = VLD4LNd32_UPD + {13, OperandInfo414}, // Inst #2744 = VLD4LNd8 + {7, OperandInfo404}, // Inst #2745 = VLD4LNd8Pseudo + {9, OperandInfo405}, // Inst #2746 = VLD4LNd8Pseudo_UPD + {15, OperandInfo415}, // Inst #2747 = VLD4LNd8_UPD + {13, OperandInfo414}, // Inst #2748 = VLD4LNq16 + {7, OperandInfo410}, // Inst #2749 = VLD4LNq16Pseudo + {9, OperandInfo411}, // Inst #2750 = VLD4LNq16Pseudo_UPD + {15, OperandInfo415}, // Inst #2751 = VLD4LNq16_UPD + {13, OperandInfo414}, // Inst #2752 = VLD4LNq32 + {7, OperandInfo410}, // Inst #2753 = VLD4LNq32Pseudo + {9, OperandInfo411}, // Inst #2754 = VLD4LNq32Pseudo_UPD + {15, OperandInfo415}, // Inst #2755 = VLD4LNq32_UPD + {8, OperandInfo412}, // Inst #2756 = VLD4d16 + {5, OperandInfo393}, // Inst #2757 = VLD4d16Pseudo + {7, OperandInfo401}, // Inst #2758 = VLD4d16Pseudo_UPD + {10, OperandInfo413}, // Inst #2759 = VLD4d16_UPD + {8, OperandInfo412}, // Inst #2760 = VLD4d32 + {5, OperandInfo393}, // Inst #2761 = VLD4d32Pseudo + {7, OperandInfo401}, // Inst #2762 = VLD4d32Pseudo_UPD + {10, OperandInfo413}, // Inst #2763 = VLD4d32_UPD + {8, OperandInfo412}, // Inst #2764 = VLD4d8 + {5, OperandInfo393}, // Inst #2765 = VLD4d8Pseudo + {7, OperandInfo401}, // Inst #2766 = VLD4d8Pseudo_UPD + {10, OperandInfo413}, // Inst #2767 = VLD4d8_UPD + {8, OperandInfo412}, // Inst #2768 = VLD4q16 + {8, OperandInfo397}, // Inst #2769 = VLD4q16Pseudo_UPD + {10, OperandInfo413}, // Inst #2770 = VLD4q16_UPD + {6, OperandInfo396}, // Inst #2771 = VLD4q16oddPseudo + {8, OperandInfo397}, // Inst #2772 = VLD4q16oddPseudo_UPD + {8, OperandInfo412}, // Inst #2773 = VLD4q32 + {8, OperandInfo397}, // Inst #2774 = VLD4q32Pseudo_UPD + {10, OperandInfo413}, // Inst #2775 = VLD4q32_UPD + {6, OperandInfo396}, // Inst #2776 = VLD4q32oddPseudo + {8, OperandInfo397}, // Inst #2777 = VLD4q32oddPseudo_UPD + {8, OperandInfo412}, // Inst #2778 = VLD4q8 + {8, OperandInfo397}, // Inst #2779 = VLD4q8Pseudo_UPD + {10, OperandInfo413}, // Inst #2780 = VLD4q8_UPD + {6, OperandInfo396}, // Inst #2781 = VLD4q8oddPseudo + {8, OperandInfo397}, // Inst #2782 = VLD4q8oddPseudo_UPD + {5, OperandInfo65}, // Inst #2783 = VLDMDDB_UPD + {4, OperandInfo203}, // Inst #2784 = VLDMDIA + {5, OperandInfo65}, // Inst #2785 = VLDMDIA_UPD + {4, OperandInfo416}, // Inst #2786 = VLDMQIA + {5, OperandInfo65}, // Inst #2787 = VLDMSDB_UPD + {4, OperandInfo203}, // Inst #2788 = VLDMSIA + {5, OperandInfo65}, // Inst #2789 = VLDMSIA_UPD + {5, OperandInfo98}, // Inst #2790 = VLDRD + {5, OperandInfo417}, // Inst #2791 = VLDRH + {5, OperandInfo418}, // Inst #2792 = VLDRS + {4, OperandInfo419}, // Inst #2793 = VLDR_FPCXTNS_off + {5, OperandInfo420}, // Inst #2794 = VLDR_FPCXTNS_post + {5, OperandInfo420}, // Inst #2795 = VLDR_FPCXTNS_pre + {4, OperandInfo419}, // Inst #2796 = VLDR_FPCXTS_off + {5, OperandInfo420}, // Inst #2797 = VLDR_FPCXTS_post + {5, OperandInfo420}, // Inst #2798 = VLDR_FPCXTS_pre + {4, OperandInfo419}, // Inst #2799 = VLDR_FPSCR_NZCVQC_off + {5, OperandInfo420}, // Inst #2800 = VLDR_FPSCR_NZCVQC_post + {5, OperandInfo420}, // Inst #2801 = VLDR_FPSCR_NZCVQC_pre + {4, OperandInfo419}, // Inst #2802 = VLDR_FPSCR_off + {5, OperandInfo420}, // Inst #2803 = VLDR_FPSCR_post + {5, OperandInfo420}, // Inst #2804 = VLDR_FPSCR_pre + {5, OperandInfo421}, // Inst #2805 = VLDR_P0_off + {6, OperandInfo422}, // Inst #2806 = VLDR_P0_post + {6, OperandInfo422}, // Inst #2807 = VLDR_P0_pre + {4, OperandInfo419}, // Inst #2808 = VLDR_VPR_off + {5, OperandInfo420}, // Inst #2809 = VLDR_VPR_post + {5, OperandInfo420}, // Inst #2810 = VLDR_VPR_pre + {3, OperandInfo234}, // Inst #2811 = VLLDM + {3, OperandInfo234}, // Inst #2812 = VLSTM + {5, OperandInfo334}, // Inst #2813 = VMAXfd + {5, OperandInfo335}, // Inst #2814 = VMAXfq + {5, OperandInfo334}, // Inst #2815 = VMAXhd + {5, OperandInfo335}, // Inst #2816 = VMAXhq + {5, OperandInfo335}, // Inst #2817 = VMAXsv16i8 + {5, OperandInfo334}, // Inst #2818 = VMAXsv2i32 + {5, OperandInfo334}, // Inst #2819 = VMAXsv4i16 + {5, OperandInfo335}, // Inst #2820 = VMAXsv4i32 + {5, OperandInfo335}, // Inst #2821 = VMAXsv8i16 + {5, OperandInfo334}, // Inst #2822 = VMAXsv8i8 + {5, OperandInfo335}, // Inst #2823 = VMAXuv16i8 + {5, OperandInfo334}, // Inst #2824 = VMAXuv2i32 + {5, OperandInfo334}, // Inst #2825 = VMAXuv4i16 + {5, OperandInfo335}, // Inst #2826 = VMAXuv4i32 + {5, OperandInfo335}, // Inst #2827 = VMAXuv8i16 + {5, OperandInfo334}, // Inst #2828 = VMAXuv8i8 + {5, OperandInfo334}, // Inst #2829 = VMINfd + {5, OperandInfo335}, // Inst #2830 = VMINfq + {5, OperandInfo334}, // Inst #2831 = VMINhd + {5, OperandInfo335}, // Inst #2832 = VMINhq + {5, OperandInfo335}, // Inst #2833 = VMINsv16i8 + {5, OperandInfo334}, // Inst #2834 = VMINsv2i32 + {5, OperandInfo334}, // Inst #2835 = VMINsv4i16 + {5, OperandInfo335}, // Inst #2836 = VMINsv4i32 + {5, OperandInfo335}, // Inst #2837 = VMINsv8i16 + {5, OperandInfo334}, // Inst #2838 = VMINsv8i8 + {5, OperandInfo335}, // Inst #2839 = VMINuv16i8 + {5, OperandInfo334}, // Inst #2840 = VMINuv2i32 + {5, OperandInfo334}, // Inst #2841 = VMINuv4i16 + {5, OperandInfo335}, // Inst #2842 = VMINuv4i32 + {5, OperandInfo335}, // Inst #2843 = VMINuv8i16 + {5, OperandInfo334}, // Inst #2844 = VMINuv8i8 + {6, OperandInfo332}, // Inst #2845 = VMLAD + {6, OperandInfo374}, // Inst #2846 = VMLAH + {7, OperandInfo423}, // Inst #2847 = VMLALslsv2i32 + {7, OperandInfo424}, // Inst #2848 = VMLALslsv4i16 + {7, OperandInfo423}, // Inst #2849 = VMLALsluv2i32 + {7, OperandInfo424}, // Inst #2850 = VMLALsluv4i16 + {6, OperandInfo330}, // Inst #2851 = VMLALsv2i64 + {6, OperandInfo330}, // Inst #2852 = VMLALsv4i32 + {6, OperandInfo330}, // Inst #2853 = VMLALsv8i16 + {6, OperandInfo330}, // Inst #2854 = VMLALuv2i64 + {6, OperandInfo330}, // Inst #2855 = VMLALuv4i32 + {6, OperandInfo330}, // Inst #2856 = VMLALuv8i16 + {6, OperandInfo379}, // Inst #2857 = VMLAS + {6, OperandInfo332}, // Inst #2858 = VMLAfd + {6, OperandInfo331}, // Inst #2859 = VMLAfq + {6, OperandInfo332}, // Inst #2860 = VMLAhd + {6, OperandInfo331}, // Inst #2861 = VMLAhq + {7, OperandInfo425}, // Inst #2862 = VMLAslfd + {7, OperandInfo426}, // Inst #2863 = VMLAslfq + {7, OperandInfo427}, // Inst #2864 = VMLAslhd + {7, OperandInfo428}, // Inst #2865 = VMLAslhq + {7, OperandInfo425}, // Inst #2866 = VMLAslv2i32 + {7, OperandInfo427}, // Inst #2867 = VMLAslv4i16 + {7, OperandInfo426}, // Inst #2868 = VMLAslv4i32 + {7, OperandInfo428}, // Inst #2869 = VMLAslv8i16 + {6, OperandInfo331}, // Inst #2870 = VMLAv16i8 + {6, OperandInfo332}, // Inst #2871 = VMLAv2i32 + {6, OperandInfo332}, // Inst #2872 = VMLAv4i16 + {6, OperandInfo331}, // Inst #2873 = VMLAv4i32 + {6, OperandInfo331}, // Inst #2874 = VMLAv8i16 + {6, OperandInfo332}, // Inst #2875 = VMLAv8i8 + {6, OperandInfo332}, // Inst #2876 = VMLSD + {6, OperandInfo374}, // Inst #2877 = VMLSH + {7, OperandInfo423}, // Inst #2878 = VMLSLslsv2i32 + {7, OperandInfo424}, // Inst #2879 = VMLSLslsv4i16 + {7, OperandInfo423}, // Inst #2880 = VMLSLsluv2i32 + {7, OperandInfo424}, // Inst #2881 = VMLSLsluv4i16 + {6, OperandInfo330}, // Inst #2882 = VMLSLsv2i64 + {6, OperandInfo330}, // Inst #2883 = VMLSLsv4i32 + {6, OperandInfo330}, // Inst #2884 = VMLSLsv8i16 + {6, OperandInfo330}, // Inst #2885 = VMLSLuv2i64 + {6, OperandInfo330}, // Inst #2886 = VMLSLuv4i32 + {6, OperandInfo330}, // Inst #2887 = VMLSLuv8i16 + {6, OperandInfo379}, // Inst #2888 = VMLSS + {6, OperandInfo332}, // Inst #2889 = VMLSfd + {6, OperandInfo331}, // Inst #2890 = VMLSfq + {6, OperandInfo332}, // Inst #2891 = VMLShd + {6, OperandInfo331}, // Inst #2892 = VMLShq + {7, OperandInfo425}, // Inst #2893 = VMLSslfd + {7, OperandInfo426}, // Inst #2894 = VMLSslfq + {7, OperandInfo427}, // Inst #2895 = VMLSslhd + {7, OperandInfo428}, // Inst #2896 = VMLSslhq + {7, OperandInfo425}, // Inst #2897 = VMLSslv2i32 + {7, OperandInfo427}, // Inst #2898 = VMLSslv4i16 + {7, OperandInfo426}, // Inst #2899 = VMLSslv4i32 + {7, OperandInfo428}, // Inst #2900 = VMLSslv8i16 + {6, OperandInfo331}, // Inst #2901 = VMLSv16i8 + {6, OperandInfo332}, // Inst #2902 = VMLSv2i32 + {6, OperandInfo332}, // Inst #2903 = VMLSv4i16 + {6, OperandInfo331}, // Inst #2904 = VMLSv4i32 + {6, OperandInfo331}, // Inst #2905 = VMLSv8i16 + {6, OperandInfo332}, // Inst #2906 = VMLSv8i8 + {4, OperandInfo159}, // Inst #2907 = VMMLA + {4, OperandInfo336}, // Inst #2908 = VMOVD + {5, OperandInfo429}, // Inst #2909 = VMOVDRR + {2, OperandInfo363}, // Inst #2910 = VMOVH + {4, OperandInfo430}, // Inst #2911 = VMOVHR + {4, OperandInfo368}, // Inst #2912 = VMOVLsv2i64 + {4, OperandInfo368}, // Inst #2913 = VMOVLsv4i32 + {4, OperandInfo368}, // Inst #2914 = VMOVLsv8i16 + {4, OperandInfo368}, // Inst #2915 = VMOVLuv2i64 + {4, OperandInfo368}, // Inst #2916 = VMOVLuv4i32 + {4, OperandInfo368}, // Inst #2917 = VMOVLuv8i16 + {4, OperandInfo160}, // Inst #2918 = VMOVNv2i32 + {4, OperandInfo160}, // Inst #2919 = VMOVNv4i16 + {4, OperandInfo160}, // Inst #2920 = VMOVNv8i8 + {4, OperandInfo431}, // Inst #2921 = VMOVRH + {5, OperandInfo432}, // Inst #2922 = VMOVRRD + {6, OperandInfo433}, // Inst #2923 = VMOVRRS + {4, OperandInfo434}, // Inst #2924 = VMOVRS + {4, OperandInfo338}, // Inst #2925 = VMOVS + {4, OperandInfo435}, // Inst #2926 = VMOVSR + {6, OperandInfo436}, // Inst #2927 = VMOVSRR + {4, OperandInfo437}, // Inst #2928 = VMOVv16i8 + {4, OperandInfo200}, // Inst #2929 = VMOVv1i64 + {4, OperandInfo200}, // Inst #2930 = VMOVv2f32 + {4, OperandInfo200}, // Inst #2931 = VMOVv2i32 + {4, OperandInfo437}, // Inst #2932 = VMOVv2i64 + {4, OperandInfo437}, // Inst #2933 = VMOVv4f32 + {4, OperandInfo200}, // Inst #2934 = VMOVv4i16 + {4, OperandInfo437}, // Inst #2935 = VMOVv4i32 + {4, OperandInfo437}, // Inst #2936 = VMOVv8i16 + {4, OperandInfo200}, // Inst #2937 = VMOVv8i8 + {3, OperandInfo234}, // Inst #2938 = VMRS + {3, OperandInfo135}, // Inst #2939 = VMRS_FPCXTNS + {3, OperandInfo135}, // Inst #2940 = VMRS_FPCXTS + {3, OperandInfo234}, // Inst #2941 = VMRS_FPEXC + {3, OperandInfo234}, // Inst #2942 = VMRS_FPINST + {3, OperandInfo234}, // Inst #2943 = VMRS_FPINST2 + {4, OperandInfo438}, // Inst #2944 = VMRS_FPSCR_NZCVQC + {3, OperandInfo234}, // Inst #2945 = VMRS_FPSID + {3, OperandInfo234}, // Inst #2946 = VMRS_MVFR0 + {3, OperandInfo234}, // Inst #2947 = VMRS_MVFR1 + {3, OperandInfo234}, // Inst #2948 = VMRS_MVFR2 + {4, OperandInfo439}, // Inst #2949 = VMRS_P0 + {3, OperandInfo135}, // Inst #2950 = VMRS_VPR + {3, OperandInfo234}, // Inst #2951 = VMSR + {3, OperandInfo135}, // Inst #2952 = VMSR_FPCXTNS + {3, OperandInfo135}, // Inst #2953 = VMSR_FPCXTS + {3, OperandInfo234}, // Inst #2954 = VMSR_FPEXC + {3, OperandInfo234}, // Inst #2955 = VMSR_FPINST + {3, OperandInfo234}, // Inst #2956 = VMSR_FPINST2 + {4, OperandInfo440}, // Inst #2957 = VMSR_FPSCR_NZCVQC + {3, OperandInfo234}, // Inst #2958 = VMSR_FPSID + {4, OperandInfo441}, // Inst #2959 = VMSR_P0 + {3, OperandInfo135}, // Inst #2960 = VMSR_VPR + {5, OperandInfo334}, // Inst #2961 = VMULD + {5, OperandInfo340}, // Inst #2962 = VMULH + {3, OperandInfo377}, // Inst #2963 = VMULLp64 + {5, OperandInfo333}, // Inst #2964 = VMULLp8 + {6, OperandInfo442}, // Inst #2965 = VMULLslsv2i32 + {6, OperandInfo443}, // Inst #2966 = VMULLslsv4i16 + {6, OperandInfo442}, // Inst #2967 = VMULLsluv2i32 + {6, OperandInfo443}, // Inst #2968 = VMULLsluv4i16 + {5, OperandInfo333}, // Inst #2969 = VMULLsv2i64 + {5, OperandInfo333}, // Inst #2970 = VMULLsv4i32 + {5, OperandInfo333}, // Inst #2971 = VMULLsv8i16 + {5, OperandInfo333}, // Inst #2972 = VMULLuv2i64 + {5, OperandInfo333}, // Inst #2973 = VMULLuv4i32 + {5, OperandInfo333}, // Inst #2974 = VMULLuv8i16 + {5, OperandInfo342}, // Inst #2975 = VMULS + {5, OperandInfo334}, // Inst #2976 = VMULfd + {5, OperandInfo335}, // Inst #2977 = VMULfq + {5, OperandInfo334}, // Inst #2978 = VMULhd + {5, OperandInfo335}, // Inst #2979 = VMULhq + {5, OperandInfo334}, // Inst #2980 = VMULpd + {5, OperandInfo335}, // Inst #2981 = VMULpq + {6, OperandInfo444}, // Inst #2982 = VMULslfd + {6, OperandInfo445}, // Inst #2983 = VMULslfq + {6, OperandInfo446}, // Inst #2984 = VMULslhd + {6, OperandInfo447}, // Inst #2985 = VMULslhq + {6, OperandInfo444}, // Inst #2986 = VMULslv2i32 + {6, OperandInfo446}, // Inst #2987 = VMULslv4i16 + {6, OperandInfo445}, // Inst #2988 = VMULslv4i32 + {6, OperandInfo447}, // Inst #2989 = VMULslv8i16 + {5, OperandInfo335}, // Inst #2990 = VMULv16i8 + {5, OperandInfo334}, // Inst #2991 = VMULv2i32 + {5, OperandInfo334}, // Inst #2992 = VMULv4i16 + {5, OperandInfo335}, // Inst #2993 = VMULv4i32 + {5, OperandInfo335}, // Inst #2994 = VMULv8i16 + {5, OperandInfo334}, // Inst #2995 = VMULv8i8 + {4, OperandInfo336}, // Inst #2996 = VMVNd + {4, OperandInfo339}, // Inst #2997 = VMVNq + {4, OperandInfo200}, // Inst #2998 = VMVNv2i32 + {4, OperandInfo200}, // Inst #2999 = VMVNv4i16 + {4, OperandInfo437}, // Inst #3000 = VMVNv4i32 + {4, OperandInfo437}, // Inst #3001 = VMVNv8i16 + {4, OperandInfo336}, // Inst #3002 = VNEGD + {4, OperandInfo337}, // Inst #3003 = VNEGH + {4, OperandInfo338}, // Inst #3004 = VNEGS + {4, OperandInfo339}, // Inst #3005 = VNEGf32q + {4, OperandInfo336}, // Inst #3006 = VNEGfd + {4, OperandInfo336}, // Inst #3007 = VNEGhd + {4, OperandInfo339}, // Inst #3008 = VNEGhq + {4, OperandInfo336}, // Inst #3009 = VNEGs16d + {4, OperandInfo339}, // Inst #3010 = VNEGs16q + {4, OperandInfo336}, // Inst #3011 = VNEGs32d + {4, OperandInfo339}, // Inst #3012 = VNEGs32q + {4, OperandInfo336}, // Inst #3013 = VNEGs8d + {4, OperandInfo339}, // Inst #3014 = VNEGs8q + {6, OperandInfo332}, // Inst #3015 = VNMLAD + {6, OperandInfo374}, // Inst #3016 = VNMLAH + {6, OperandInfo379}, // Inst #3017 = VNMLAS + {6, OperandInfo332}, // Inst #3018 = VNMLSD + {6, OperandInfo374}, // Inst #3019 = VNMLSH + {6, OperandInfo379}, // Inst #3020 = VNMLSS + {5, OperandInfo334}, // Inst #3021 = VNMULD + {5, OperandInfo340}, // Inst #3022 = VNMULH + {5, OperandInfo342}, // Inst #3023 = VNMULS + {5, OperandInfo334}, // Inst #3024 = VORNd + {5, OperandInfo335}, // Inst #3025 = VORNq + {5, OperandInfo334}, // Inst #3026 = VORRd + {5, OperandInfo345}, // Inst #3027 = VORRiv2i32 + {5, OperandInfo345}, // Inst #3028 = VORRiv4i16 + {5, OperandInfo346}, // Inst #3029 = VORRiv4i32 + {5, OperandInfo346}, // Inst #3030 = VORRiv8i16 + {5, OperandInfo335}, // Inst #3031 = VORRq + {5, OperandInfo448}, // Inst #3032 = VPADALsv16i8 + {5, OperandInfo101}, // Inst #3033 = VPADALsv2i32 + {5, OperandInfo101}, // Inst #3034 = VPADALsv4i16 + {5, OperandInfo448}, // Inst #3035 = VPADALsv4i32 + {5, OperandInfo448}, // Inst #3036 = VPADALsv8i16 + {5, OperandInfo101}, // Inst #3037 = VPADALsv8i8 + {5, OperandInfo448}, // Inst #3038 = VPADALuv16i8 + {5, OperandInfo101}, // Inst #3039 = VPADALuv2i32 + {5, OperandInfo101}, // Inst #3040 = VPADALuv4i16 + {5, OperandInfo448}, // Inst #3041 = VPADALuv4i32 + {5, OperandInfo448}, // Inst #3042 = VPADALuv8i16 + {5, OperandInfo101}, // Inst #3043 = VPADALuv8i8 + {4, OperandInfo339}, // Inst #3044 = VPADDLsv16i8 + {4, OperandInfo336}, // Inst #3045 = VPADDLsv2i32 + {4, OperandInfo336}, // Inst #3046 = VPADDLsv4i16 + {4, OperandInfo339}, // Inst #3047 = VPADDLsv4i32 + {4, OperandInfo339}, // Inst #3048 = VPADDLsv8i16 + {4, OperandInfo336}, // Inst #3049 = VPADDLsv8i8 + {4, OperandInfo339}, // Inst #3050 = VPADDLuv16i8 + {4, OperandInfo336}, // Inst #3051 = VPADDLuv2i32 + {4, OperandInfo336}, // Inst #3052 = VPADDLuv4i16 + {4, OperandInfo339}, // Inst #3053 = VPADDLuv4i32 + {4, OperandInfo339}, // Inst #3054 = VPADDLuv8i16 + {4, OperandInfo336}, // Inst #3055 = VPADDLuv8i8 + {5, OperandInfo334}, // Inst #3056 = VPADDf + {5, OperandInfo334}, // Inst #3057 = VPADDh + {5, OperandInfo334}, // Inst #3058 = VPADDi16 + {5, OperandInfo334}, // Inst #3059 = VPADDi32 + {5, OperandInfo334}, // Inst #3060 = VPADDi8 + {5, OperandInfo334}, // Inst #3061 = VPMAXf + {5, OperandInfo334}, // Inst #3062 = VPMAXh + {5, OperandInfo334}, // Inst #3063 = VPMAXs16 + {5, OperandInfo334}, // Inst #3064 = VPMAXs32 + {5, OperandInfo334}, // Inst #3065 = VPMAXs8 + {5, OperandInfo334}, // Inst #3066 = VPMAXu16 + {5, OperandInfo334}, // Inst #3067 = VPMAXu32 + {5, OperandInfo334}, // Inst #3068 = VPMAXu8 + {5, OperandInfo334}, // Inst #3069 = VPMINf + {5, OperandInfo334}, // Inst #3070 = VPMINh + {5, OperandInfo334}, // Inst #3071 = VPMINs16 + {5, OperandInfo334}, // Inst #3072 = VPMINs32 + {5, OperandInfo334}, // Inst #3073 = VPMINs8 + {5, OperandInfo334}, // Inst #3074 = VPMINu16 + {5, OperandInfo334}, // Inst #3075 = VPMINu32 + {5, OperandInfo334}, // Inst #3076 = VPMINu8 + {4, OperandInfo339}, // Inst #3077 = VQABSv16i8 + {4, OperandInfo336}, // Inst #3078 = VQABSv2i32 + {4, OperandInfo336}, // Inst #3079 = VQABSv4i16 + {4, OperandInfo339}, // Inst #3080 = VQABSv4i32 + {4, OperandInfo339}, // Inst #3081 = VQABSv8i16 + {4, OperandInfo336}, // Inst #3082 = VQABSv8i8 + {5, OperandInfo335}, // Inst #3083 = VQADDsv16i8 + {5, OperandInfo334}, // Inst #3084 = VQADDsv1i64 + {5, OperandInfo334}, // Inst #3085 = VQADDsv2i32 + {5, OperandInfo335}, // Inst #3086 = VQADDsv2i64 + {5, OperandInfo334}, // Inst #3087 = VQADDsv4i16 + {5, OperandInfo335}, // Inst #3088 = VQADDsv4i32 + {5, OperandInfo335}, // Inst #3089 = VQADDsv8i16 + {5, OperandInfo334}, // Inst #3090 = VQADDsv8i8 + {5, OperandInfo335}, // Inst #3091 = VQADDuv16i8 + {5, OperandInfo334}, // Inst #3092 = VQADDuv1i64 + {5, OperandInfo334}, // Inst #3093 = VQADDuv2i32 + {5, OperandInfo335}, // Inst #3094 = VQADDuv2i64 + {5, OperandInfo334}, // Inst #3095 = VQADDuv4i16 + {5, OperandInfo335}, // Inst #3096 = VQADDuv4i32 + {5, OperandInfo335}, // Inst #3097 = VQADDuv8i16 + {5, OperandInfo334}, // Inst #3098 = VQADDuv8i8 + {7, OperandInfo423}, // Inst #3099 = VQDMLALslv2i32 + {7, OperandInfo424}, // Inst #3100 = VQDMLALslv4i16 + {6, OperandInfo330}, // Inst #3101 = VQDMLALv2i64 + {6, OperandInfo330}, // Inst #3102 = VQDMLALv4i32 + {7, OperandInfo423}, // Inst #3103 = VQDMLSLslv2i32 + {7, OperandInfo424}, // Inst #3104 = VQDMLSLslv4i16 + {6, OperandInfo330}, // Inst #3105 = VQDMLSLv2i64 + {6, OperandInfo330}, // Inst #3106 = VQDMLSLv4i32 + {6, OperandInfo444}, // Inst #3107 = VQDMULHslv2i32 + {6, OperandInfo446}, // Inst #3108 = VQDMULHslv4i16 + {6, OperandInfo445}, // Inst #3109 = VQDMULHslv4i32 + {6, OperandInfo447}, // Inst #3110 = VQDMULHslv8i16 + {5, OperandInfo334}, // Inst #3111 = VQDMULHv2i32 + {5, OperandInfo334}, // Inst #3112 = VQDMULHv4i16 + {5, OperandInfo335}, // Inst #3113 = VQDMULHv4i32 + {5, OperandInfo335}, // Inst #3114 = VQDMULHv8i16 + {6, OperandInfo442}, // Inst #3115 = VQDMULLslv2i32 + {6, OperandInfo443}, // Inst #3116 = VQDMULLslv4i16 + {5, OperandInfo333}, // Inst #3117 = VQDMULLv2i64 + {5, OperandInfo333}, // Inst #3118 = VQDMULLv4i32 + {4, OperandInfo160}, // Inst #3119 = VQMOVNsuv2i32 + {4, OperandInfo160}, // Inst #3120 = VQMOVNsuv4i16 + {4, OperandInfo160}, // Inst #3121 = VQMOVNsuv8i8 + {4, OperandInfo160}, // Inst #3122 = VQMOVNsv2i32 + {4, OperandInfo160}, // Inst #3123 = VQMOVNsv4i16 + {4, OperandInfo160}, // Inst #3124 = VQMOVNsv8i8 + {4, OperandInfo160}, // Inst #3125 = VQMOVNuv2i32 + {4, OperandInfo160}, // Inst #3126 = VQMOVNuv4i16 + {4, OperandInfo160}, // Inst #3127 = VQMOVNuv8i8 + {4, OperandInfo339}, // Inst #3128 = VQNEGv16i8 + {4, OperandInfo336}, // Inst #3129 = VQNEGv2i32 + {4, OperandInfo336}, // Inst #3130 = VQNEGv4i16 + {4, OperandInfo339}, // Inst #3131 = VQNEGv4i32 + {4, OperandInfo339}, // Inst #3132 = VQNEGv8i16 + {4, OperandInfo336}, // Inst #3133 = VQNEGv8i8 + {7, OperandInfo425}, // Inst #3134 = VQRDMLAHslv2i32 + {7, OperandInfo427}, // Inst #3135 = VQRDMLAHslv4i16 + {7, OperandInfo426}, // Inst #3136 = VQRDMLAHslv4i32 + {7, OperandInfo428}, // Inst #3137 = VQRDMLAHslv8i16 + {6, OperandInfo332}, // Inst #3138 = VQRDMLAHv2i32 + {6, OperandInfo332}, // Inst #3139 = VQRDMLAHv4i16 + {6, OperandInfo331}, // Inst #3140 = VQRDMLAHv4i32 + {6, OperandInfo331}, // Inst #3141 = VQRDMLAHv8i16 + {7, OperandInfo425}, // Inst #3142 = VQRDMLSHslv2i32 + {7, OperandInfo427}, // Inst #3143 = VQRDMLSHslv4i16 + {7, OperandInfo426}, // Inst #3144 = VQRDMLSHslv4i32 + {7, OperandInfo428}, // Inst #3145 = VQRDMLSHslv8i16 + {6, OperandInfo332}, // Inst #3146 = VQRDMLSHv2i32 + {6, OperandInfo332}, // Inst #3147 = VQRDMLSHv4i16 + {6, OperandInfo331}, // Inst #3148 = VQRDMLSHv4i32 + {6, OperandInfo331}, // Inst #3149 = VQRDMLSHv8i16 + {6, OperandInfo444}, // Inst #3150 = VQRDMULHslv2i32 + {6, OperandInfo446}, // Inst #3151 = VQRDMULHslv4i16 + {6, OperandInfo445}, // Inst #3152 = VQRDMULHslv4i32 + {6, OperandInfo447}, // Inst #3153 = VQRDMULHslv8i16 + {5, OperandInfo334}, // Inst #3154 = VQRDMULHv2i32 + {5, OperandInfo334}, // Inst #3155 = VQRDMULHv4i16 + {5, OperandInfo335}, // Inst #3156 = VQRDMULHv4i32 + {5, OperandInfo335}, // Inst #3157 = VQRDMULHv8i16 + {5, OperandInfo335}, // Inst #3158 = VQRSHLsv16i8 + {5, OperandInfo334}, // Inst #3159 = VQRSHLsv1i64 + {5, OperandInfo334}, // Inst #3160 = VQRSHLsv2i32 + {5, OperandInfo335}, // Inst #3161 = VQRSHLsv2i64 + {5, OperandInfo334}, // Inst #3162 = VQRSHLsv4i16 + {5, OperandInfo335}, // Inst #3163 = VQRSHLsv4i32 + {5, OperandInfo335}, // Inst #3164 = VQRSHLsv8i16 + {5, OperandInfo334}, // Inst #3165 = VQRSHLsv8i8 + {5, OperandInfo335}, // Inst #3166 = VQRSHLuv16i8 + {5, OperandInfo334}, // Inst #3167 = VQRSHLuv1i64 + {5, OperandInfo334}, // Inst #3168 = VQRSHLuv2i32 + {5, OperandInfo335}, // Inst #3169 = VQRSHLuv2i64 + {5, OperandInfo334}, // Inst #3170 = VQRSHLuv4i16 + {5, OperandInfo335}, // Inst #3171 = VQRSHLuv4i32 + {5, OperandInfo335}, // Inst #3172 = VQRSHLuv8i16 + {5, OperandInfo334}, // Inst #3173 = VQRSHLuv8i8 + {5, OperandInfo449}, // Inst #3174 = VQRSHRNsv2i32 + {5, OperandInfo449}, // Inst #3175 = VQRSHRNsv4i16 + {5, OperandInfo449}, // Inst #3176 = VQRSHRNsv8i8 + {5, OperandInfo449}, // Inst #3177 = VQRSHRNuv2i32 + {5, OperandInfo449}, // Inst #3178 = VQRSHRNuv4i16 + {5, OperandInfo449}, // Inst #3179 = VQRSHRNuv8i8 + {5, OperandInfo449}, // Inst #3180 = VQRSHRUNv2i32 + {5, OperandInfo449}, // Inst #3181 = VQRSHRUNv4i16 + {5, OperandInfo449}, // Inst #3182 = VQRSHRUNv8i8 + {5, OperandInfo450}, // Inst #3183 = VQSHLsiv16i8 + {5, OperandInfo451}, // Inst #3184 = VQSHLsiv1i64 + {5, OperandInfo451}, // Inst #3185 = VQSHLsiv2i32 + {5, OperandInfo450}, // Inst #3186 = VQSHLsiv2i64 + {5, OperandInfo451}, // Inst #3187 = VQSHLsiv4i16 + {5, OperandInfo450}, // Inst #3188 = VQSHLsiv4i32 + {5, OperandInfo450}, // Inst #3189 = VQSHLsiv8i16 + {5, OperandInfo451}, // Inst #3190 = VQSHLsiv8i8 + {5, OperandInfo450}, // Inst #3191 = VQSHLsuv16i8 + {5, OperandInfo451}, // Inst #3192 = VQSHLsuv1i64 + {5, OperandInfo451}, // Inst #3193 = VQSHLsuv2i32 + {5, OperandInfo450}, // Inst #3194 = VQSHLsuv2i64 + {5, OperandInfo451}, // Inst #3195 = VQSHLsuv4i16 + {5, OperandInfo450}, // Inst #3196 = VQSHLsuv4i32 + {5, OperandInfo450}, // Inst #3197 = VQSHLsuv8i16 + {5, OperandInfo451}, // Inst #3198 = VQSHLsuv8i8 + {5, OperandInfo335}, // Inst #3199 = VQSHLsv16i8 + {5, OperandInfo334}, // Inst #3200 = VQSHLsv1i64 + {5, OperandInfo334}, // Inst #3201 = VQSHLsv2i32 + {5, OperandInfo335}, // Inst #3202 = VQSHLsv2i64 + {5, OperandInfo334}, // Inst #3203 = VQSHLsv4i16 + {5, OperandInfo335}, // Inst #3204 = VQSHLsv4i32 + {5, OperandInfo335}, // Inst #3205 = VQSHLsv8i16 + {5, OperandInfo334}, // Inst #3206 = VQSHLsv8i8 + {5, OperandInfo450}, // Inst #3207 = VQSHLuiv16i8 + {5, OperandInfo451}, // Inst #3208 = VQSHLuiv1i64 + {5, OperandInfo451}, // Inst #3209 = VQSHLuiv2i32 + {5, OperandInfo450}, // Inst #3210 = VQSHLuiv2i64 + {5, OperandInfo451}, // Inst #3211 = VQSHLuiv4i16 + {5, OperandInfo450}, // Inst #3212 = VQSHLuiv4i32 + {5, OperandInfo450}, // Inst #3213 = VQSHLuiv8i16 + {5, OperandInfo451}, // Inst #3214 = VQSHLuiv8i8 + {5, OperandInfo335}, // Inst #3215 = VQSHLuv16i8 + {5, OperandInfo334}, // Inst #3216 = VQSHLuv1i64 + {5, OperandInfo334}, // Inst #3217 = VQSHLuv2i32 + {5, OperandInfo335}, // Inst #3218 = VQSHLuv2i64 + {5, OperandInfo334}, // Inst #3219 = VQSHLuv4i16 + {5, OperandInfo335}, // Inst #3220 = VQSHLuv4i32 + {5, OperandInfo335}, // Inst #3221 = VQSHLuv8i16 + {5, OperandInfo334}, // Inst #3222 = VQSHLuv8i8 + {5, OperandInfo449}, // Inst #3223 = VQSHRNsv2i32 + {5, OperandInfo449}, // Inst #3224 = VQSHRNsv4i16 + {5, OperandInfo449}, // Inst #3225 = VQSHRNsv8i8 + {5, OperandInfo449}, // Inst #3226 = VQSHRNuv2i32 + {5, OperandInfo449}, // Inst #3227 = VQSHRNuv4i16 + {5, OperandInfo449}, // Inst #3228 = VQSHRNuv8i8 + {5, OperandInfo449}, // Inst #3229 = VQSHRUNv2i32 + {5, OperandInfo449}, // Inst #3230 = VQSHRUNv4i16 + {5, OperandInfo449}, // Inst #3231 = VQSHRUNv8i8 + {5, OperandInfo335}, // Inst #3232 = VQSUBsv16i8 + {5, OperandInfo334}, // Inst #3233 = VQSUBsv1i64 + {5, OperandInfo334}, // Inst #3234 = VQSUBsv2i32 + {5, OperandInfo335}, // Inst #3235 = VQSUBsv2i64 + {5, OperandInfo334}, // Inst #3236 = VQSUBsv4i16 + {5, OperandInfo335}, // Inst #3237 = VQSUBsv4i32 + {5, OperandInfo335}, // Inst #3238 = VQSUBsv8i16 + {5, OperandInfo334}, // Inst #3239 = VQSUBsv8i8 + {5, OperandInfo335}, // Inst #3240 = VQSUBuv16i8 + {5, OperandInfo334}, // Inst #3241 = VQSUBuv1i64 + {5, OperandInfo334}, // Inst #3242 = VQSUBuv2i32 + {5, OperandInfo335}, // Inst #3243 = VQSUBuv2i64 + {5, OperandInfo334}, // Inst #3244 = VQSUBuv4i16 + {5, OperandInfo335}, // Inst #3245 = VQSUBuv4i32 + {5, OperandInfo335}, // Inst #3246 = VQSUBuv8i16 + {5, OperandInfo334}, // Inst #3247 = VQSUBuv8i8 + {5, OperandInfo341}, // Inst #3248 = VRADDHNv2i32 + {5, OperandInfo341}, // Inst #3249 = VRADDHNv4i16 + {5, OperandInfo341}, // Inst #3250 = VRADDHNv8i8 + {4, OperandInfo336}, // Inst #3251 = VRECPEd + {4, OperandInfo336}, // Inst #3252 = VRECPEfd + {4, OperandInfo339}, // Inst #3253 = VRECPEfq + {4, OperandInfo336}, // Inst #3254 = VRECPEhd + {4, OperandInfo339}, // Inst #3255 = VRECPEhq + {4, OperandInfo339}, // Inst #3256 = VRECPEq + {5, OperandInfo334}, // Inst #3257 = VRECPSfd + {5, OperandInfo335}, // Inst #3258 = VRECPSfq + {5, OperandInfo334}, // Inst #3259 = VRECPShd + {5, OperandInfo335}, // Inst #3260 = VRECPShq + {4, OperandInfo336}, // Inst #3261 = VREV16d8 + {4, OperandInfo339}, // Inst #3262 = VREV16q8 + {4, OperandInfo336}, // Inst #3263 = VREV32d16 + {4, OperandInfo336}, // Inst #3264 = VREV32d8 + {4, OperandInfo339}, // Inst #3265 = VREV32q16 + {4, OperandInfo339}, // Inst #3266 = VREV32q8 + {4, OperandInfo336}, // Inst #3267 = VREV64d16 + {4, OperandInfo336}, // Inst #3268 = VREV64d32 + {4, OperandInfo336}, // Inst #3269 = VREV64d8 + {4, OperandInfo339}, // Inst #3270 = VREV64q16 + {4, OperandInfo339}, // Inst #3271 = VREV64q32 + {4, OperandInfo339}, // Inst #3272 = VREV64q8 + {5, OperandInfo335}, // Inst #3273 = VRHADDsv16i8 + {5, OperandInfo334}, // Inst #3274 = VRHADDsv2i32 + {5, OperandInfo334}, // Inst #3275 = VRHADDsv4i16 + {5, OperandInfo335}, // Inst #3276 = VRHADDsv4i32 + {5, OperandInfo335}, // Inst #3277 = VRHADDsv8i16 + {5, OperandInfo334}, // Inst #3278 = VRHADDsv8i8 + {5, OperandInfo335}, // Inst #3279 = VRHADDuv16i8 + {5, OperandInfo334}, // Inst #3280 = VRHADDuv2i32 + {5, OperandInfo334}, // Inst #3281 = VRHADDuv4i16 + {5, OperandInfo335}, // Inst #3282 = VRHADDuv4i32 + {5, OperandInfo335}, // Inst #3283 = VRHADDuv8i16 + {5, OperandInfo334}, // Inst #3284 = VRHADDuv8i8 + {2, OperandInfo360}, // Inst #3285 = VRINTAD + {2, OperandInfo452}, // Inst #3286 = VRINTAH + {2, OperandInfo360}, // Inst #3287 = VRINTANDf + {2, OperandInfo360}, // Inst #3288 = VRINTANDh + {2, OperandInfo155}, // Inst #3289 = VRINTANQf + {2, OperandInfo155}, // Inst #3290 = VRINTANQh + {2, OperandInfo363}, // Inst #3291 = VRINTAS + {2, OperandInfo360}, // Inst #3292 = VRINTMD + {2, OperandInfo452}, // Inst #3293 = VRINTMH + {2, OperandInfo360}, // Inst #3294 = VRINTMNDf + {2, OperandInfo360}, // Inst #3295 = VRINTMNDh + {2, OperandInfo155}, // Inst #3296 = VRINTMNQf + {2, OperandInfo155}, // Inst #3297 = VRINTMNQh + {2, OperandInfo363}, // Inst #3298 = VRINTMS + {2, OperandInfo360}, // Inst #3299 = VRINTND + {2, OperandInfo452}, // Inst #3300 = VRINTNH + {2, OperandInfo360}, // Inst #3301 = VRINTNNDf + {2, OperandInfo360}, // Inst #3302 = VRINTNNDh + {2, OperandInfo155}, // Inst #3303 = VRINTNNQf + {2, OperandInfo155}, // Inst #3304 = VRINTNNQh + {2, OperandInfo363}, // Inst #3305 = VRINTNS + {2, OperandInfo360}, // Inst #3306 = VRINTPD + {2, OperandInfo452}, // Inst #3307 = VRINTPH + {2, OperandInfo360}, // Inst #3308 = VRINTPNDf + {2, OperandInfo360}, // Inst #3309 = VRINTPNDh + {2, OperandInfo155}, // Inst #3310 = VRINTPNQf + {2, OperandInfo155}, // Inst #3311 = VRINTPNQh + {2, OperandInfo363}, // Inst #3312 = VRINTPS + {4, OperandInfo336}, // Inst #3313 = VRINTRD + {4, OperandInfo337}, // Inst #3314 = VRINTRH + {4, OperandInfo338}, // Inst #3315 = VRINTRS + {4, OperandInfo336}, // Inst #3316 = VRINTXD + {4, OperandInfo337}, // Inst #3317 = VRINTXH + {2, OperandInfo360}, // Inst #3318 = VRINTXNDf + {2, OperandInfo360}, // Inst #3319 = VRINTXNDh + {2, OperandInfo155}, // Inst #3320 = VRINTXNQf + {2, OperandInfo155}, // Inst #3321 = VRINTXNQh + {4, OperandInfo338}, // Inst #3322 = VRINTXS + {4, OperandInfo336}, // Inst #3323 = VRINTZD + {4, OperandInfo337}, // Inst #3324 = VRINTZH + {2, OperandInfo360}, // Inst #3325 = VRINTZNDf + {2, OperandInfo360}, // Inst #3326 = VRINTZNDh + {2, OperandInfo155}, // Inst #3327 = VRINTZNQf + {2, OperandInfo155}, // Inst #3328 = VRINTZNQh + {4, OperandInfo338}, // Inst #3329 = VRINTZS + {5, OperandInfo335}, // Inst #3330 = VRSHLsv16i8 + {5, OperandInfo334}, // Inst #3331 = VRSHLsv1i64 + {5, OperandInfo334}, // Inst #3332 = VRSHLsv2i32 + {5, OperandInfo335}, // Inst #3333 = VRSHLsv2i64 + {5, OperandInfo334}, // Inst #3334 = VRSHLsv4i16 + {5, OperandInfo335}, // Inst #3335 = VRSHLsv4i32 + {5, OperandInfo335}, // Inst #3336 = VRSHLsv8i16 + {5, OperandInfo334}, // Inst #3337 = VRSHLsv8i8 + {5, OperandInfo335}, // Inst #3338 = VRSHLuv16i8 + {5, OperandInfo334}, // Inst #3339 = VRSHLuv1i64 + {5, OperandInfo334}, // Inst #3340 = VRSHLuv2i32 + {5, OperandInfo335}, // Inst #3341 = VRSHLuv2i64 + {5, OperandInfo334}, // Inst #3342 = VRSHLuv4i16 + {5, OperandInfo335}, // Inst #3343 = VRSHLuv4i32 + {5, OperandInfo335}, // Inst #3344 = VRSHLuv8i16 + {5, OperandInfo334}, // Inst #3345 = VRSHLuv8i8 + {5, OperandInfo449}, // Inst #3346 = VRSHRNv2i32 + {5, OperandInfo449}, // Inst #3347 = VRSHRNv4i16 + {5, OperandInfo449}, // Inst #3348 = VRSHRNv8i8 + {5, OperandInfo367}, // Inst #3349 = VRSHRsv16i8 + {5, OperandInfo366}, // Inst #3350 = VRSHRsv1i64 + {5, OperandInfo366}, // Inst #3351 = VRSHRsv2i32 + {5, OperandInfo367}, // Inst #3352 = VRSHRsv2i64 + {5, OperandInfo366}, // Inst #3353 = VRSHRsv4i16 + {5, OperandInfo367}, // Inst #3354 = VRSHRsv4i32 + {5, OperandInfo367}, // Inst #3355 = VRSHRsv8i16 + {5, OperandInfo366}, // Inst #3356 = VRSHRsv8i8 + {5, OperandInfo367}, // Inst #3357 = VRSHRuv16i8 + {5, OperandInfo366}, // Inst #3358 = VRSHRuv1i64 + {5, OperandInfo366}, // Inst #3359 = VRSHRuv2i32 + {5, OperandInfo367}, // Inst #3360 = VRSHRuv2i64 + {5, OperandInfo366}, // Inst #3361 = VRSHRuv4i16 + {5, OperandInfo367}, // Inst #3362 = VRSHRuv4i32 + {5, OperandInfo367}, // Inst #3363 = VRSHRuv8i16 + {5, OperandInfo366}, // Inst #3364 = VRSHRuv8i8 + {4, OperandInfo336}, // Inst #3365 = VRSQRTEd + {4, OperandInfo336}, // Inst #3366 = VRSQRTEfd + {4, OperandInfo339}, // Inst #3367 = VRSQRTEfq + {4, OperandInfo336}, // Inst #3368 = VRSQRTEhd + {4, OperandInfo339}, // Inst #3369 = VRSQRTEhq + {4, OperandInfo339}, // Inst #3370 = VRSQRTEq + {5, OperandInfo334}, // Inst #3371 = VRSQRTSfd + {5, OperandInfo335}, // Inst #3372 = VRSQRTSfq + {5, OperandInfo334}, // Inst #3373 = VRSQRTShd + {5, OperandInfo335}, // Inst #3374 = VRSQRTShq + {6, OperandInfo453}, // Inst #3375 = VRSRAsv16i8 + {6, OperandInfo454}, // Inst #3376 = VRSRAsv1i64 + {6, OperandInfo454}, // Inst #3377 = VRSRAsv2i32 + {6, OperandInfo453}, // Inst #3378 = VRSRAsv2i64 + {6, OperandInfo454}, // Inst #3379 = VRSRAsv4i16 + {6, OperandInfo453}, // Inst #3380 = VRSRAsv4i32 + {6, OperandInfo453}, // Inst #3381 = VRSRAsv8i16 + {6, OperandInfo454}, // Inst #3382 = VRSRAsv8i8 + {6, OperandInfo453}, // Inst #3383 = VRSRAuv16i8 + {6, OperandInfo454}, // Inst #3384 = VRSRAuv1i64 + {6, OperandInfo454}, // Inst #3385 = VRSRAuv2i32 + {6, OperandInfo453}, // Inst #3386 = VRSRAuv2i64 + {6, OperandInfo454}, // Inst #3387 = VRSRAuv4i16 + {6, OperandInfo453}, // Inst #3388 = VRSRAuv4i32 + {6, OperandInfo453}, // Inst #3389 = VRSRAuv8i16 + {6, OperandInfo454}, // Inst #3390 = VRSRAuv8i8 + {5, OperandInfo341}, // Inst #3391 = VRSUBHNv2i32 + {5, OperandInfo341}, // Inst #3392 = VRSUBHNv4i16 + {5, OperandInfo341}, // Inst #3393 = VRSUBHNv8i8 + {3, OperandInfo147}, // Inst #3394 = VSCCLRMD + {3, OperandInfo147}, // Inst #3395 = VSCCLRMS + {4, OperandInfo158}, // Inst #3396 = VSDOTD + {5, OperandInfo156}, // Inst #3397 = VSDOTDI + {4, OperandInfo159}, // Inst #3398 = VSDOTQ + {5, OperandInfo157}, // Inst #3399 = VSDOTQI + {3, OperandInfo305}, // Inst #3400 = VSELEQD + {3, OperandInfo380}, // Inst #3401 = VSELEQH + {3, OperandInfo381}, // Inst #3402 = VSELEQS + {3, OperandInfo305}, // Inst #3403 = VSELGED + {3, OperandInfo380}, // Inst #3404 = VSELGEH + {3, OperandInfo381}, // Inst #3405 = VSELGES + {3, OperandInfo305}, // Inst #3406 = VSELGTD + {3, OperandInfo380}, // Inst #3407 = VSELGTH + {3, OperandInfo381}, // Inst #3408 = VSELGTS + {3, OperandInfo305}, // Inst #3409 = VSELVSD + {3, OperandInfo380}, // Inst #3410 = VSELVSH + {3, OperandInfo381}, // Inst #3411 = VSELVSS + {6, OperandInfo455}, // Inst #3412 = VSETLNi16 + {6, OperandInfo455}, // Inst #3413 = VSETLNi32 + {6, OperandInfo455}, // Inst #3414 = VSETLNi8 + {5, OperandInfo371}, // Inst #3415 = VSHLLi16 + {5, OperandInfo371}, // Inst #3416 = VSHLLi32 + {5, OperandInfo371}, // Inst #3417 = VSHLLi8 + {5, OperandInfo371}, // Inst #3418 = VSHLLsv2i64 + {5, OperandInfo371}, // Inst #3419 = VSHLLsv4i32 + {5, OperandInfo371}, // Inst #3420 = VSHLLsv8i16 + {5, OperandInfo371}, // Inst #3421 = VSHLLuv2i64 + {5, OperandInfo371}, // Inst #3422 = VSHLLuv4i32 + {5, OperandInfo371}, // Inst #3423 = VSHLLuv8i16 + {5, OperandInfo450}, // Inst #3424 = VSHLiv16i8 + {5, OperandInfo451}, // Inst #3425 = VSHLiv1i64 + {5, OperandInfo451}, // Inst #3426 = VSHLiv2i32 + {5, OperandInfo450}, // Inst #3427 = VSHLiv2i64 + {5, OperandInfo451}, // Inst #3428 = VSHLiv4i16 + {5, OperandInfo450}, // Inst #3429 = VSHLiv4i32 + {5, OperandInfo450}, // Inst #3430 = VSHLiv8i16 + {5, OperandInfo451}, // Inst #3431 = VSHLiv8i8 + {5, OperandInfo335}, // Inst #3432 = VSHLsv16i8 + {5, OperandInfo334}, // Inst #3433 = VSHLsv1i64 + {5, OperandInfo334}, // Inst #3434 = VSHLsv2i32 + {5, OperandInfo335}, // Inst #3435 = VSHLsv2i64 + {5, OperandInfo334}, // Inst #3436 = VSHLsv4i16 + {5, OperandInfo335}, // Inst #3437 = VSHLsv4i32 + {5, OperandInfo335}, // Inst #3438 = VSHLsv8i16 + {5, OperandInfo334}, // Inst #3439 = VSHLsv8i8 + {5, OperandInfo335}, // Inst #3440 = VSHLuv16i8 + {5, OperandInfo334}, // Inst #3441 = VSHLuv1i64 + {5, OperandInfo334}, // Inst #3442 = VSHLuv2i32 + {5, OperandInfo335}, // Inst #3443 = VSHLuv2i64 + {5, OperandInfo334}, // Inst #3444 = VSHLuv4i16 + {5, OperandInfo335}, // Inst #3445 = VSHLuv4i32 + {5, OperandInfo335}, // Inst #3446 = VSHLuv8i16 + {5, OperandInfo334}, // Inst #3447 = VSHLuv8i8 + {5, OperandInfo449}, // Inst #3448 = VSHRNv2i32 + {5, OperandInfo449}, // Inst #3449 = VSHRNv4i16 + {5, OperandInfo449}, // Inst #3450 = VSHRNv8i8 + {5, OperandInfo367}, // Inst #3451 = VSHRsv16i8 + {5, OperandInfo366}, // Inst #3452 = VSHRsv1i64 + {5, OperandInfo366}, // Inst #3453 = VSHRsv2i32 + {5, OperandInfo367}, // Inst #3454 = VSHRsv2i64 + {5, OperandInfo366}, // Inst #3455 = VSHRsv4i16 + {5, OperandInfo367}, // Inst #3456 = VSHRsv4i32 + {5, OperandInfo367}, // Inst #3457 = VSHRsv8i16 + {5, OperandInfo366}, // Inst #3458 = VSHRsv8i8 + {5, OperandInfo367}, // Inst #3459 = VSHRuv16i8 + {5, OperandInfo366}, // Inst #3460 = VSHRuv1i64 + {5, OperandInfo366}, // Inst #3461 = VSHRuv2i32 + {5, OperandInfo367}, // Inst #3462 = VSHRuv2i64 + {5, OperandInfo366}, // Inst #3463 = VSHRuv4i16 + {5, OperandInfo367}, // Inst #3464 = VSHRuv4i32 + {5, OperandInfo367}, // Inst #3465 = VSHRuv8i16 + {5, OperandInfo366}, // Inst #3466 = VSHRuv8i8 + {5, OperandInfo456}, // Inst #3467 = VSHTOD + {5, OperandInfo457}, // Inst #3468 = VSHTOH + {5, OperandInfo457}, // Inst #3469 = VSHTOS + {4, OperandInfo365}, // Inst #3470 = VSITOD + {4, OperandInfo458}, // Inst #3471 = VSITOH + {4, OperandInfo338}, // Inst #3472 = VSITOS + {6, OperandInfo459}, // Inst #3473 = VSLIv16i8 + {6, OperandInfo460}, // Inst #3474 = VSLIv1i64 + {6, OperandInfo460}, // Inst #3475 = VSLIv2i32 + {6, OperandInfo459}, // Inst #3476 = VSLIv2i64 + {6, OperandInfo460}, // Inst #3477 = VSLIv4i16 + {6, OperandInfo459}, // Inst #3478 = VSLIv4i32 + {6, OperandInfo459}, // Inst #3479 = VSLIv8i16 + {6, OperandInfo460}, // Inst #3480 = VSLIv8i8 + {5, OperandInfo456}, // Inst #3481 = VSLTOD + {5, OperandInfo457}, // Inst #3482 = VSLTOH + {5, OperandInfo457}, // Inst #3483 = VSLTOS + {4, OperandInfo159}, // Inst #3484 = VSMMLA + {4, OperandInfo336}, // Inst #3485 = VSQRTD + {4, OperandInfo337}, // Inst #3486 = VSQRTH + {4, OperandInfo338}, // Inst #3487 = VSQRTS + {6, OperandInfo453}, // Inst #3488 = VSRAsv16i8 + {6, OperandInfo454}, // Inst #3489 = VSRAsv1i64 + {6, OperandInfo454}, // Inst #3490 = VSRAsv2i32 + {6, OperandInfo453}, // Inst #3491 = VSRAsv2i64 + {6, OperandInfo454}, // Inst #3492 = VSRAsv4i16 + {6, OperandInfo453}, // Inst #3493 = VSRAsv4i32 + {6, OperandInfo453}, // Inst #3494 = VSRAsv8i16 + {6, OperandInfo454}, // Inst #3495 = VSRAsv8i8 + {6, OperandInfo453}, // Inst #3496 = VSRAuv16i8 + {6, OperandInfo454}, // Inst #3497 = VSRAuv1i64 + {6, OperandInfo454}, // Inst #3498 = VSRAuv2i32 + {6, OperandInfo453}, // Inst #3499 = VSRAuv2i64 + {6, OperandInfo454}, // Inst #3500 = VSRAuv4i16 + {6, OperandInfo453}, // Inst #3501 = VSRAuv4i32 + {6, OperandInfo453}, // Inst #3502 = VSRAuv8i16 + {6, OperandInfo454}, // Inst #3503 = VSRAuv8i8 + {6, OperandInfo453}, // Inst #3504 = VSRIv16i8 + {6, OperandInfo454}, // Inst #3505 = VSRIv1i64 + {6, OperandInfo454}, // Inst #3506 = VSRIv2i32 + {6, OperandInfo453}, // Inst #3507 = VSRIv2i64 + {6, OperandInfo454}, // Inst #3508 = VSRIv4i16 + {6, OperandInfo453}, // Inst #3509 = VSRIv4i32 + {6, OperandInfo453}, // Inst #3510 = VSRIv8i16 + {6, OperandInfo454}, // Inst #3511 = VSRIv8i8 + {6, OperandInfo461}, // Inst #3512 = VST1LNd16 + {8, OperandInfo462}, // Inst #3513 = VST1LNd16_UPD + {6, OperandInfo461}, // Inst #3514 = VST1LNd32 + {8, OperandInfo462}, // Inst #3515 = VST1LNd32_UPD + {6, OperandInfo461}, // Inst #3516 = VST1LNd8 + {8, OperandInfo462}, // Inst #3517 = VST1LNd8_UPD + {6, OperandInfo463}, // Inst #3518 = VST1LNq16Pseudo + {8, OperandInfo464}, // Inst #3519 = VST1LNq16Pseudo_UPD + {6, OperandInfo463}, // Inst #3520 = VST1LNq32Pseudo + {8, OperandInfo464}, // Inst #3521 = VST1LNq32Pseudo_UPD + {6, OperandInfo463}, // Inst #3522 = VST1LNq8Pseudo + {8, OperandInfo464}, // Inst #3523 = VST1LNq8Pseudo_UPD + {5, OperandInfo465}, // Inst #3524 = VST1d16 + {5, OperandInfo465}, // Inst #3525 = VST1d16Q + {5, OperandInfo466}, // Inst #3526 = VST1d16QPseudo + {6, OperandInfo467}, // Inst #3527 = VST1d16QPseudoWB_fixed + {7, OperandInfo468}, // Inst #3528 = VST1d16QPseudoWB_register + {6, OperandInfo469}, // Inst #3529 = VST1d16Qwb_fixed + {7, OperandInfo470}, // Inst #3530 = VST1d16Qwb_register + {5, OperandInfo465}, // Inst #3531 = VST1d16T + {5, OperandInfo466}, // Inst #3532 = VST1d16TPseudo + {6, OperandInfo467}, // Inst #3533 = VST1d16TPseudoWB_fixed + {7, OperandInfo468}, // Inst #3534 = VST1d16TPseudoWB_register + {6, OperandInfo469}, // Inst #3535 = VST1d16Twb_fixed + {7, OperandInfo470}, // Inst #3536 = VST1d16Twb_register + {6, OperandInfo469}, // Inst #3537 = VST1d16wb_fixed + {7, OperandInfo470}, // Inst #3538 = VST1d16wb_register + {5, OperandInfo465}, // Inst #3539 = VST1d32 + {5, OperandInfo465}, // Inst #3540 = VST1d32Q + {5, OperandInfo466}, // Inst #3541 = VST1d32QPseudo + {6, OperandInfo467}, // Inst #3542 = VST1d32QPseudoWB_fixed + {7, OperandInfo468}, // Inst #3543 = VST1d32QPseudoWB_register + {6, OperandInfo469}, // Inst #3544 = VST1d32Qwb_fixed + {7, OperandInfo470}, // Inst #3545 = VST1d32Qwb_register + {5, OperandInfo465}, // Inst #3546 = VST1d32T + {5, OperandInfo466}, // Inst #3547 = VST1d32TPseudo + {6, OperandInfo467}, // Inst #3548 = VST1d32TPseudoWB_fixed + {7, OperandInfo468}, // Inst #3549 = VST1d32TPseudoWB_register + {6, OperandInfo469}, // Inst #3550 = VST1d32Twb_fixed + {7, OperandInfo470}, // Inst #3551 = VST1d32Twb_register + {6, OperandInfo469}, // Inst #3552 = VST1d32wb_fixed + {7, OperandInfo470}, // Inst #3553 = VST1d32wb_register + {5, OperandInfo465}, // Inst #3554 = VST1d64 + {5, OperandInfo465}, // Inst #3555 = VST1d64Q + {5, OperandInfo466}, // Inst #3556 = VST1d64QPseudo + {6, OperandInfo467}, // Inst #3557 = VST1d64QPseudoWB_fixed + {7, OperandInfo468}, // Inst #3558 = VST1d64QPseudoWB_register + {6, OperandInfo469}, // Inst #3559 = VST1d64Qwb_fixed + {7, OperandInfo470}, // Inst #3560 = VST1d64Qwb_register + {5, OperandInfo465}, // Inst #3561 = VST1d64T + {5, OperandInfo466}, // Inst #3562 = VST1d64TPseudo + {6, OperandInfo467}, // Inst #3563 = VST1d64TPseudoWB_fixed + {7, OperandInfo468}, // Inst #3564 = VST1d64TPseudoWB_register + {6, OperandInfo469}, // Inst #3565 = VST1d64Twb_fixed + {7, OperandInfo470}, // Inst #3566 = VST1d64Twb_register + {6, OperandInfo469}, // Inst #3567 = VST1d64wb_fixed + {7, OperandInfo470}, // Inst #3568 = VST1d64wb_register + {5, OperandInfo465}, // Inst #3569 = VST1d8 + {5, OperandInfo465}, // Inst #3570 = VST1d8Q + {5, OperandInfo466}, // Inst #3571 = VST1d8QPseudo + {6, OperandInfo467}, // Inst #3572 = VST1d8QPseudoWB_fixed + {7, OperandInfo468}, // Inst #3573 = VST1d8QPseudoWB_register + {6, OperandInfo469}, // Inst #3574 = VST1d8Qwb_fixed + {7, OperandInfo470}, // Inst #3575 = VST1d8Qwb_register + {5, OperandInfo465}, // Inst #3576 = VST1d8T + {5, OperandInfo466}, // Inst #3577 = VST1d8TPseudo + {6, OperandInfo467}, // Inst #3578 = VST1d8TPseudoWB_fixed + {7, OperandInfo468}, // Inst #3579 = VST1d8TPseudoWB_register + {6, OperandInfo469}, // Inst #3580 = VST1d8Twb_fixed + {7, OperandInfo470}, // Inst #3581 = VST1d8Twb_register + {6, OperandInfo469}, // Inst #3582 = VST1d8wb_fixed + {7, OperandInfo470}, // Inst #3583 = VST1d8wb_register + {5, OperandInfo471}, // Inst #3584 = VST1q16 + {5, OperandInfo472}, // Inst #3585 = VST1q16HighQPseudo + {7, OperandInfo473}, // Inst #3586 = VST1q16HighQPseudo_UPD + {5, OperandInfo472}, // Inst #3587 = VST1q16HighTPseudo + {7, OperandInfo473}, // Inst #3588 = VST1q16HighTPseudo_UPD + {7, OperandInfo473}, // Inst #3589 = VST1q16LowQPseudo_UPD + {7, OperandInfo473}, // Inst #3590 = VST1q16LowTPseudo_UPD + {6, OperandInfo474}, // Inst #3591 = VST1q16wb_fixed + {7, OperandInfo475}, // Inst #3592 = VST1q16wb_register + {5, OperandInfo471}, // Inst #3593 = VST1q32 + {5, OperandInfo472}, // Inst #3594 = VST1q32HighQPseudo + {7, OperandInfo473}, // Inst #3595 = VST1q32HighQPseudo_UPD + {5, OperandInfo472}, // Inst #3596 = VST1q32HighTPseudo + {7, OperandInfo473}, // Inst #3597 = VST1q32HighTPseudo_UPD + {7, OperandInfo473}, // Inst #3598 = VST1q32LowQPseudo_UPD + {7, OperandInfo473}, // Inst #3599 = VST1q32LowTPseudo_UPD + {6, OperandInfo474}, // Inst #3600 = VST1q32wb_fixed + {7, OperandInfo475}, // Inst #3601 = VST1q32wb_register + {5, OperandInfo471}, // Inst #3602 = VST1q64 + {5, OperandInfo472}, // Inst #3603 = VST1q64HighQPseudo + {7, OperandInfo473}, // Inst #3604 = VST1q64HighQPseudo_UPD + {5, OperandInfo472}, // Inst #3605 = VST1q64HighTPseudo + {7, OperandInfo473}, // Inst #3606 = VST1q64HighTPseudo_UPD + {7, OperandInfo473}, // Inst #3607 = VST1q64LowQPseudo_UPD + {7, OperandInfo473}, // Inst #3608 = VST1q64LowTPseudo_UPD + {6, OperandInfo474}, // Inst #3609 = VST1q64wb_fixed + {7, OperandInfo475}, // Inst #3610 = VST1q64wb_register + {5, OperandInfo471}, // Inst #3611 = VST1q8 + {5, OperandInfo472}, // Inst #3612 = VST1q8HighQPseudo + {7, OperandInfo473}, // Inst #3613 = VST1q8HighQPseudo_UPD + {5, OperandInfo472}, // Inst #3614 = VST1q8HighTPseudo + {7, OperandInfo473}, // Inst #3615 = VST1q8HighTPseudo_UPD + {7, OperandInfo473}, // Inst #3616 = VST1q8LowQPseudo_UPD + {7, OperandInfo473}, // Inst #3617 = VST1q8LowTPseudo_UPD + {6, OperandInfo474}, // Inst #3618 = VST1q8wb_fixed + {7, OperandInfo475}, // Inst #3619 = VST1q8wb_register + {7, OperandInfo476}, // Inst #3620 = VST2LNd16 + {6, OperandInfo463}, // Inst #3621 = VST2LNd16Pseudo + {8, OperandInfo464}, // Inst #3622 = VST2LNd16Pseudo_UPD + {9, OperandInfo477}, // Inst #3623 = VST2LNd16_UPD + {7, OperandInfo476}, // Inst #3624 = VST2LNd32 + {6, OperandInfo463}, // Inst #3625 = VST2LNd32Pseudo + {8, OperandInfo464}, // Inst #3626 = VST2LNd32Pseudo_UPD + {9, OperandInfo477}, // Inst #3627 = VST2LNd32_UPD + {7, OperandInfo476}, // Inst #3628 = VST2LNd8 + {6, OperandInfo463}, // Inst #3629 = VST2LNd8Pseudo + {8, OperandInfo464}, // Inst #3630 = VST2LNd8Pseudo_UPD + {9, OperandInfo477}, // Inst #3631 = VST2LNd8_UPD + {7, OperandInfo476}, // Inst #3632 = VST2LNq16 + {6, OperandInfo478}, // Inst #3633 = VST2LNq16Pseudo + {8, OperandInfo479}, // Inst #3634 = VST2LNq16Pseudo_UPD + {9, OperandInfo477}, // Inst #3635 = VST2LNq16_UPD + {7, OperandInfo476}, // Inst #3636 = VST2LNq32 + {6, OperandInfo478}, // Inst #3637 = VST2LNq32Pseudo + {8, OperandInfo479}, // Inst #3638 = VST2LNq32Pseudo_UPD + {9, OperandInfo477}, // Inst #3639 = VST2LNq32_UPD + {5, OperandInfo471}, // Inst #3640 = VST2b16 + {6, OperandInfo474}, // Inst #3641 = VST2b16wb_fixed + {7, OperandInfo475}, // Inst #3642 = VST2b16wb_register + {5, OperandInfo471}, // Inst #3643 = VST2b32 + {6, OperandInfo474}, // Inst #3644 = VST2b32wb_fixed + {7, OperandInfo475}, // Inst #3645 = VST2b32wb_register + {5, OperandInfo471}, // Inst #3646 = VST2b8 + {6, OperandInfo474}, // Inst #3647 = VST2b8wb_fixed + {7, OperandInfo475}, // Inst #3648 = VST2b8wb_register + {5, OperandInfo471}, // Inst #3649 = VST2d16 + {6, OperandInfo474}, // Inst #3650 = VST2d16wb_fixed + {7, OperandInfo475}, // Inst #3651 = VST2d16wb_register + {5, OperandInfo471}, // Inst #3652 = VST2d32 + {6, OperandInfo474}, // Inst #3653 = VST2d32wb_fixed + {7, OperandInfo475}, // Inst #3654 = VST2d32wb_register + {5, OperandInfo471}, // Inst #3655 = VST2d8 + {6, OperandInfo474}, // Inst #3656 = VST2d8wb_fixed + {7, OperandInfo475}, // Inst #3657 = VST2d8wb_register + {5, OperandInfo465}, // Inst #3658 = VST2q16 + {5, OperandInfo466}, // Inst #3659 = VST2q16Pseudo + {6, OperandInfo467}, // Inst #3660 = VST2q16PseudoWB_fixed + {7, OperandInfo480}, // Inst #3661 = VST2q16PseudoWB_register + {6, OperandInfo469}, // Inst #3662 = VST2q16wb_fixed + {7, OperandInfo470}, // Inst #3663 = VST2q16wb_register + {5, OperandInfo465}, // Inst #3664 = VST2q32 + {5, OperandInfo466}, // Inst #3665 = VST2q32Pseudo + {6, OperandInfo467}, // Inst #3666 = VST2q32PseudoWB_fixed + {7, OperandInfo480}, // Inst #3667 = VST2q32PseudoWB_register + {6, OperandInfo469}, // Inst #3668 = VST2q32wb_fixed + {7, OperandInfo470}, // Inst #3669 = VST2q32wb_register + {5, OperandInfo465}, // Inst #3670 = VST2q8 + {5, OperandInfo466}, // Inst #3671 = VST2q8Pseudo + {6, OperandInfo467}, // Inst #3672 = VST2q8PseudoWB_fixed + {7, OperandInfo480}, // Inst #3673 = VST2q8PseudoWB_register + {6, OperandInfo469}, // Inst #3674 = VST2q8wb_fixed + {7, OperandInfo470}, // Inst #3675 = VST2q8wb_register + {8, OperandInfo481}, // Inst #3676 = VST3LNd16 + {6, OperandInfo478}, // Inst #3677 = VST3LNd16Pseudo + {8, OperandInfo479}, // Inst #3678 = VST3LNd16Pseudo_UPD + {10, OperandInfo482}, // Inst #3679 = VST3LNd16_UPD + {8, OperandInfo481}, // Inst #3680 = VST3LNd32 + {6, OperandInfo478}, // Inst #3681 = VST3LNd32Pseudo + {8, OperandInfo479}, // Inst #3682 = VST3LNd32Pseudo_UPD + {10, OperandInfo482}, // Inst #3683 = VST3LNd32_UPD + {8, OperandInfo481}, // Inst #3684 = VST3LNd8 + {6, OperandInfo478}, // Inst #3685 = VST3LNd8Pseudo + {8, OperandInfo479}, // Inst #3686 = VST3LNd8Pseudo_UPD + {10, OperandInfo482}, // Inst #3687 = VST3LNd8_UPD + {8, OperandInfo481}, // Inst #3688 = VST3LNq16 + {6, OperandInfo483}, // Inst #3689 = VST3LNq16Pseudo + {8, OperandInfo484}, // Inst #3690 = VST3LNq16Pseudo_UPD + {10, OperandInfo482}, // Inst #3691 = VST3LNq16_UPD + {8, OperandInfo481}, // Inst #3692 = VST3LNq32 + {6, OperandInfo483}, // Inst #3693 = VST3LNq32Pseudo + {8, OperandInfo484}, // Inst #3694 = VST3LNq32Pseudo_UPD + {10, OperandInfo482}, // Inst #3695 = VST3LNq32_UPD + {7, OperandInfo485}, // Inst #3696 = VST3d16 + {5, OperandInfo466}, // Inst #3697 = VST3d16Pseudo + {7, OperandInfo468}, // Inst #3698 = VST3d16Pseudo_UPD + {9, OperandInfo486}, // Inst #3699 = VST3d16_UPD + {7, OperandInfo485}, // Inst #3700 = VST3d32 + {5, OperandInfo466}, // Inst #3701 = VST3d32Pseudo + {7, OperandInfo468}, // Inst #3702 = VST3d32Pseudo_UPD + {9, OperandInfo486}, // Inst #3703 = VST3d32_UPD + {7, OperandInfo485}, // Inst #3704 = VST3d8 + {5, OperandInfo466}, // Inst #3705 = VST3d8Pseudo + {7, OperandInfo468}, // Inst #3706 = VST3d8Pseudo_UPD + {9, OperandInfo486}, // Inst #3707 = VST3d8_UPD + {7, OperandInfo485}, // Inst #3708 = VST3q16 + {7, OperandInfo473}, // Inst #3709 = VST3q16Pseudo_UPD + {9, OperandInfo486}, // Inst #3710 = VST3q16_UPD + {5, OperandInfo472}, // Inst #3711 = VST3q16oddPseudo + {7, OperandInfo473}, // Inst #3712 = VST3q16oddPseudo_UPD + {7, OperandInfo485}, // Inst #3713 = VST3q32 + {7, OperandInfo473}, // Inst #3714 = VST3q32Pseudo_UPD + {9, OperandInfo486}, // Inst #3715 = VST3q32_UPD + {5, OperandInfo472}, // Inst #3716 = VST3q32oddPseudo + {7, OperandInfo473}, // Inst #3717 = VST3q32oddPseudo_UPD + {7, OperandInfo485}, // Inst #3718 = VST3q8 + {7, OperandInfo473}, // Inst #3719 = VST3q8Pseudo_UPD + {9, OperandInfo486}, // Inst #3720 = VST3q8_UPD + {5, OperandInfo472}, // Inst #3721 = VST3q8oddPseudo + {7, OperandInfo473}, // Inst #3722 = VST3q8oddPseudo_UPD + {9, OperandInfo487}, // Inst #3723 = VST4LNd16 + {6, OperandInfo478}, // Inst #3724 = VST4LNd16Pseudo + {8, OperandInfo479}, // Inst #3725 = VST4LNd16Pseudo_UPD + {11, OperandInfo488}, // Inst #3726 = VST4LNd16_UPD + {9, OperandInfo487}, // Inst #3727 = VST4LNd32 + {6, OperandInfo478}, // Inst #3728 = VST4LNd32Pseudo + {8, OperandInfo479}, // Inst #3729 = VST4LNd32Pseudo_UPD + {11, OperandInfo488}, // Inst #3730 = VST4LNd32_UPD + {9, OperandInfo487}, // Inst #3731 = VST4LNd8 + {6, OperandInfo478}, // Inst #3732 = VST4LNd8Pseudo + {8, OperandInfo479}, // Inst #3733 = VST4LNd8Pseudo_UPD + {11, OperandInfo488}, // Inst #3734 = VST4LNd8_UPD + {9, OperandInfo487}, // Inst #3735 = VST4LNq16 + {6, OperandInfo483}, // Inst #3736 = VST4LNq16Pseudo + {8, OperandInfo484}, // Inst #3737 = VST4LNq16Pseudo_UPD + {11, OperandInfo488}, // Inst #3738 = VST4LNq16_UPD + {9, OperandInfo487}, // Inst #3739 = VST4LNq32 + {6, OperandInfo483}, // Inst #3740 = VST4LNq32Pseudo + {8, OperandInfo484}, // Inst #3741 = VST4LNq32Pseudo_UPD + {11, OperandInfo488}, // Inst #3742 = VST4LNq32_UPD + {8, OperandInfo489}, // Inst #3743 = VST4d16 + {5, OperandInfo466}, // Inst #3744 = VST4d16Pseudo + {7, OperandInfo468}, // Inst #3745 = VST4d16Pseudo_UPD + {10, OperandInfo490}, // Inst #3746 = VST4d16_UPD + {8, OperandInfo489}, // Inst #3747 = VST4d32 + {5, OperandInfo466}, // Inst #3748 = VST4d32Pseudo + {7, OperandInfo468}, // Inst #3749 = VST4d32Pseudo_UPD + {10, OperandInfo490}, // Inst #3750 = VST4d32_UPD + {8, OperandInfo489}, // Inst #3751 = VST4d8 + {5, OperandInfo466}, // Inst #3752 = VST4d8Pseudo + {7, OperandInfo468}, // Inst #3753 = VST4d8Pseudo_UPD + {10, OperandInfo490}, // Inst #3754 = VST4d8_UPD + {8, OperandInfo489}, // Inst #3755 = VST4q16 + {7, OperandInfo473}, // Inst #3756 = VST4q16Pseudo_UPD + {10, OperandInfo490}, // Inst #3757 = VST4q16_UPD + {5, OperandInfo472}, // Inst #3758 = VST4q16oddPseudo + {7, OperandInfo473}, // Inst #3759 = VST4q16oddPseudo_UPD + {8, OperandInfo489}, // Inst #3760 = VST4q32 + {7, OperandInfo473}, // Inst #3761 = VST4q32Pseudo_UPD + {10, OperandInfo490}, // Inst #3762 = VST4q32_UPD + {5, OperandInfo472}, // Inst #3763 = VST4q32oddPseudo + {7, OperandInfo473}, // Inst #3764 = VST4q32oddPseudo_UPD + {8, OperandInfo489}, // Inst #3765 = VST4q8 + {7, OperandInfo473}, // Inst #3766 = VST4q8Pseudo_UPD + {10, OperandInfo490}, // Inst #3767 = VST4q8_UPD + {5, OperandInfo472}, // Inst #3768 = VST4q8oddPseudo + {7, OperandInfo473}, // Inst #3769 = VST4q8oddPseudo_UPD + {5, OperandInfo65}, // Inst #3770 = VSTMDDB_UPD + {4, OperandInfo203}, // Inst #3771 = VSTMDIA + {5, OperandInfo65}, // Inst #3772 = VSTMDIA_UPD + {4, OperandInfo416}, // Inst #3773 = VSTMQIA + {5, OperandInfo65}, // Inst #3774 = VSTMSDB_UPD + {4, OperandInfo203}, // Inst #3775 = VSTMSIA + {5, OperandInfo65}, // Inst #3776 = VSTMSIA_UPD + {5, OperandInfo98}, // Inst #3777 = VSTRD + {5, OperandInfo417}, // Inst #3778 = VSTRH + {5, OperandInfo418}, // Inst #3779 = VSTRS + {4, OperandInfo419}, // Inst #3780 = VSTR_FPCXTNS_off + {5, OperandInfo420}, // Inst #3781 = VSTR_FPCXTNS_post + {5, OperandInfo420}, // Inst #3782 = VSTR_FPCXTNS_pre + {4, OperandInfo419}, // Inst #3783 = VSTR_FPCXTS_off + {5, OperandInfo420}, // Inst #3784 = VSTR_FPCXTS_post + {5, OperandInfo420}, // Inst #3785 = VSTR_FPCXTS_pre + {4, OperandInfo419}, // Inst #3786 = VSTR_FPSCR_NZCVQC_off + {5, OperandInfo420}, // Inst #3787 = VSTR_FPSCR_NZCVQC_post + {5, OperandInfo420}, // Inst #3788 = VSTR_FPSCR_NZCVQC_pre + {4, OperandInfo419}, // Inst #3789 = VSTR_FPSCR_off + {5, OperandInfo420}, // Inst #3790 = VSTR_FPSCR_post + {5, OperandInfo420}, // Inst #3791 = VSTR_FPSCR_pre + {5, OperandInfo421}, // Inst #3792 = VSTR_P0_off + {6, OperandInfo491}, // Inst #3793 = VSTR_P0_post + {6, OperandInfo491}, // Inst #3794 = VSTR_P0_pre + {4, OperandInfo419}, // Inst #3795 = VSTR_VPR_off + {5, OperandInfo420}, // Inst #3796 = VSTR_VPR_post + {5, OperandInfo420}, // Inst #3797 = VSTR_VPR_pre + {5, OperandInfo334}, // Inst #3798 = VSUBD + {5, OperandInfo340}, // Inst #3799 = VSUBH + {5, OperandInfo341}, // Inst #3800 = VSUBHNv2i32 + {5, OperandInfo341}, // Inst #3801 = VSUBHNv4i16 + {5, OperandInfo341}, // Inst #3802 = VSUBHNv8i8 + {5, OperandInfo333}, // Inst #3803 = VSUBLsv2i64 + {5, OperandInfo333}, // Inst #3804 = VSUBLsv4i32 + {5, OperandInfo333}, // Inst #3805 = VSUBLsv8i16 + {5, OperandInfo333}, // Inst #3806 = VSUBLuv2i64 + {5, OperandInfo333}, // Inst #3807 = VSUBLuv4i32 + {5, OperandInfo333}, // Inst #3808 = VSUBLuv8i16 + {5, OperandInfo342}, // Inst #3809 = VSUBS + {5, OperandInfo343}, // Inst #3810 = VSUBWsv2i64 + {5, OperandInfo343}, // Inst #3811 = VSUBWsv4i32 + {5, OperandInfo343}, // Inst #3812 = VSUBWsv8i16 + {5, OperandInfo343}, // Inst #3813 = VSUBWuv2i64 + {5, OperandInfo343}, // Inst #3814 = VSUBWuv4i32 + {5, OperandInfo343}, // Inst #3815 = VSUBWuv8i16 + {5, OperandInfo334}, // Inst #3816 = VSUBfd + {5, OperandInfo335}, // Inst #3817 = VSUBfq + {5, OperandInfo334}, // Inst #3818 = VSUBhd + {5, OperandInfo335}, // Inst #3819 = VSUBhq + {5, OperandInfo335}, // Inst #3820 = VSUBv16i8 + {5, OperandInfo334}, // Inst #3821 = VSUBv1i64 + {5, OperandInfo334}, // Inst #3822 = VSUBv2i32 + {5, OperandInfo335}, // Inst #3823 = VSUBv2i64 + {5, OperandInfo334}, // Inst #3824 = VSUBv4i16 + {5, OperandInfo335}, // Inst #3825 = VSUBv4i32 + {5, OperandInfo335}, // Inst #3826 = VSUBv8i16 + {5, OperandInfo334}, // Inst #3827 = VSUBv8i8 + {5, OperandInfo156}, // Inst #3828 = VSUDOTDI + {5, OperandInfo157}, // Inst #3829 = VSUDOTQI + {6, OperandInfo492}, // Inst #3830 = VSWPd + {6, OperandInfo493}, // Inst #3831 = VSWPq + {5, OperandInfo334}, // Inst #3832 = VTBL1 + {5, OperandInfo494}, // Inst #3833 = VTBL2 + {5, OperandInfo334}, // Inst #3834 = VTBL3 + {5, OperandInfo495}, // Inst #3835 = VTBL3Pseudo + {5, OperandInfo334}, // Inst #3836 = VTBL4 + {5, OperandInfo495}, // Inst #3837 = VTBL4Pseudo + {6, OperandInfo332}, // Inst #3838 = VTBX1 + {6, OperandInfo496}, // Inst #3839 = VTBX2 + {6, OperandInfo332}, // Inst #3840 = VTBX3 + {6, OperandInfo497}, // Inst #3841 = VTBX3Pseudo + {6, OperandInfo332}, // Inst #3842 = VTBX4 + {6, OperandInfo497}, // Inst #3843 = VTBX4Pseudo + {5, OperandInfo456}, // Inst #3844 = VTOSHD + {5, OperandInfo457}, // Inst #3845 = VTOSHH + {5, OperandInfo457}, // Inst #3846 = VTOSHS + {4, OperandInfo364}, // Inst #3847 = VTOSIRD + {4, OperandInfo338}, // Inst #3848 = VTOSIRH + {4, OperandInfo338}, // Inst #3849 = VTOSIRS + {4, OperandInfo364}, // Inst #3850 = VTOSIZD + {4, OperandInfo498}, // Inst #3851 = VTOSIZH + {4, OperandInfo338}, // Inst #3852 = VTOSIZS + {5, OperandInfo456}, // Inst #3853 = VTOSLD + {5, OperandInfo457}, // Inst #3854 = VTOSLH + {5, OperandInfo457}, // Inst #3855 = VTOSLS + {5, OperandInfo456}, // Inst #3856 = VTOUHD + {5, OperandInfo457}, // Inst #3857 = VTOUHH + {5, OperandInfo457}, // Inst #3858 = VTOUHS + {4, OperandInfo364}, // Inst #3859 = VTOUIRD + {4, OperandInfo338}, // Inst #3860 = VTOUIRH + {4, OperandInfo338}, // Inst #3861 = VTOUIRS + {4, OperandInfo364}, // Inst #3862 = VTOUIZD + {4, OperandInfo498}, // Inst #3863 = VTOUIZH + {4, OperandInfo338}, // Inst #3864 = VTOUIZS + {5, OperandInfo456}, // Inst #3865 = VTOULD + {5, OperandInfo457}, // Inst #3866 = VTOULH + {5, OperandInfo457}, // Inst #3867 = VTOULS + {6, OperandInfo492}, // Inst #3868 = VTRNd16 + {6, OperandInfo492}, // Inst #3869 = VTRNd32 + {6, OperandInfo492}, // Inst #3870 = VTRNd8 + {6, OperandInfo493}, // Inst #3871 = VTRNq16 + {6, OperandInfo493}, // Inst #3872 = VTRNq32 + {6, OperandInfo493}, // Inst #3873 = VTRNq8 + {5, OperandInfo335}, // Inst #3874 = VTSTv16i8 + {5, OperandInfo334}, // Inst #3875 = VTSTv2i32 + {5, OperandInfo334}, // Inst #3876 = VTSTv4i16 + {5, OperandInfo335}, // Inst #3877 = VTSTv4i32 + {5, OperandInfo335}, // Inst #3878 = VTSTv8i16 + {5, OperandInfo334}, // Inst #3879 = VTSTv8i8 + {4, OperandInfo158}, // Inst #3880 = VUDOTD + {5, OperandInfo156}, // Inst #3881 = VUDOTDI + {4, OperandInfo159}, // Inst #3882 = VUDOTQ + {5, OperandInfo157}, // Inst #3883 = VUDOTQI + {5, OperandInfo456}, // Inst #3884 = VUHTOD + {5, OperandInfo457}, // Inst #3885 = VUHTOH + {5, OperandInfo457}, // Inst #3886 = VUHTOS + {4, OperandInfo365}, // Inst #3887 = VUITOD + {4, OperandInfo458}, // Inst #3888 = VUITOH + {4, OperandInfo338}, // Inst #3889 = VUITOS + {5, OperandInfo456}, // Inst #3890 = VULTOD + {5, OperandInfo457}, // Inst #3891 = VULTOH + {5, OperandInfo457}, // Inst #3892 = VULTOS + {4, OperandInfo159}, // Inst #3893 = VUMMLA + {4, OperandInfo158}, // Inst #3894 = VUSDOTD + {5, OperandInfo156}, // Inst #3895 = VUSDOTDI + {4, OperandInfo159}, // Inst #3896 = VUSDOTQ + {5, OperandInfo157}, // Inst #3897 = VUSDOTQI + {4, OperandInfo159}, // Inst #3898 = VUSMMLA + {6, OperandInfo492}, // Inst #3899 = VUZPd16 + {6, OperandInfo492}, // Inst #3900 = VUZPd8 + {6, OperandInfo493}, // Inst #3901 = VUZPq16 + {6, OperandInfo493}, // Inst #3902 = VUZPq32 + {6, OperandInfo493}, // Inst #3903 = VUZPq8 + {6, OperandInfo492}, // Inst #3904 = VZIPd16 + {6, OperandInfo492}, // Inst #3905 = VZIPd8 + {6, OperandInfo493}, // Inst #3906 = VZIPq16 + {6, OperandInfo493}, // Inst #3907 = VZIPq32 + {6, OperandInfo493}, // Inst #3908 = VZIPq8 + {4, OperandInfo203}, // Inst #3909 = sysLDMDA + {5, OperandInfo65}, // Inst #3910 = sysLDMDA_UPD + {4, OperandInfo203}, // Inst #3911 = sysLDMDB + {5, OperandInfo65}, // Inst #3912 = sysLDMDB_UPD + {4, OperandInfo203}, // Inst #3913 = sysLDMIA + {5, OperandInfo65}, // Inst #3914 = sysLDMIA_UPD + {4, OperandInfo203}, // Inst #3915 = sysLDMIB + {5, OperandInfo65}, // Inst #3916 = sysLDMIB_UPD + {4, OperandInfo203}, // Inst #3917 = sysSTMDA + {5, OperandInfo65}, // Inst #3918 = sysSTMDA_UPD + {4, OperandInfo203}, // Inst #3919 = sysSTMDB + {5, OperandInfo65}, // Inst #3920 = sysSTMDB_UPD + {4, OperandInfo203}, // Inst #3921 = sysSTMIA + {5, OperandInfo65}, // Inst #3922 = sysSTMIA_UPD + {4, OperandInfo203}, // Inst #3923 = sysSTMIB + {5, OperandInfo65}, // Inst #3924 = sysSTMIB_UPD + {6, OperandInfo499}, // Inst #3925 = t2ADCri + {6, OperandInfo500}, // Inst #3926 = t2ADCrr + {7, OperandInfo501}, // Inst #3927 = t2ADCrs + {6, OperandInfo502}, // Inst #3928 = t2ADDri + {5, OperandInfo503}, // Inst #3929 = t2ADDri12 + {6, OperandInfo504}, // Inst #3930 = t2ADDrr + {7, OperandInfo505}, // Inst #3931 = t2ADDrs + {6, OperandInfo506}, // Inst #3932 = t2ADDspImm + {5, OperandInfo507}, // Inst #3933 = t2ADDspImm12 + {4, OperandInfo508}, // Inst #3934 = t2ADR + {6, OperandInfo499}, // Inst #3935 = t2ANDri + {6, OperandInfo500}, // Inst #3936 = t2ANDrr + {7, OperandInfo501}, // Inst #3937 = t2ANDrs + {6, OperandInfo499}, // Inst #3938 = t2ASRri + {6, OperandInfo500}, // Inst #3939 = t2ASRrr + {3, OperandInfo139}, // Inst #3940 = t2B + {5, OperandInfo117}, // Inst #3941 = t2BFC + {6, OperandInfo509}, // Inst #3942 = t2BFI + {4, OperandInfo510}, // Inst #3943 = t2BFLi + {4, OperandInfo511}, // Inst #3944 = t2BFLr + {4, OperandInfo510}, // Inst #3945 = t2BFi + {4, OperandInfo512}, // Inst #3946 = t2BFic + {4, OperandInfo511}, // Inst #3947 = t2BFr + {6, OperandInfo499}, // Inst #3948 = t2BICri + {6, OperandInfo500}, // Inst #3949 = t2BICrr + {7, OperandInfo501}, // Inst #3950 = t2BICrs + {3, OperandInfo234}, // Inst #3951 = t2BXJ + {3, OperandInfo139}, // Inst #3952 = t2Bcc + {8, OperandInfo192}, // Inst #3953 = t2CDP + {8, OperandInfo192}, // Inst #3954 = t2CDP2 + {2, OperandInfo137}, // Inst #3955 = t2CLREX + {3, OperandInfo147}, // Inst #3956 = t2CLRM + {4, OperandInfo513}, // Inst #3957 = t2CLZ + {4, OperandInfo111}, // Inst #3958 = t2CMNri + {4, OperandInfo514}, // Inst #3959 = t2CMNzrr + {5, OperandInfo515}, // Inst #3960 = t2CMNzrs + {4, OperandInfo111}, // Inst #3961 = t2CMPri + {4, OperandInfo514}, // Inst #3962 = t2CMPrr + {5, OperandInfo515}, // Inst #3963 = t2CMPrs + {1, OperandInfo2}, // Inst #3964 = t2CPS1p + {2, OperandInfo7}, // Inst #3965 = t2CPS2p + {3, OperandInfo4}, // Inst #3966 = t2CPS3p + {3, OperandInfo84}, // Inst #3967 = t2CRC32B + {3, OperandInfo84}, // Inst #3968 = t2CRC32CB + {3, OperandInfo84}, // Inst #3969 = t2CRC32CH + {3, OperandInfo84}, // Inst #3970 = t2CRC32CW + {3, OperandInfo84}, // Inst #3971 = t2CRC32H + {3, OperandInfo84}, // Inst #3972 = t2CRC32W + {4, OperandInfo516}, // Inst #3973 = t2CSEL + {4, OperandInfo516}, // Inst #3974 = t2CSINC + {4, OperandInfo516}, // Inst #3975 = t2CSINV + {4, OperandInfo516}, // Inst #3976 = t2CSNEG + {3, OperandInfo199}, // Inst #3977 = t2DBG + {2, OperandInfo137}, // Inst #3978 = t2DCPS1 + {2, OperandInfo137}, // Inst #3979 = t2DCPS2 + {2, OperandInfo137}, // Inst #3980 = t2DCPS3 + {2, OperandInfo109}, // Inst #3981 = t2DLS + {3, OperandInfo199}, // Inst #3982 = t2DMB + {3, OperandInfo199}, // Inst #3983 = t2DSB + {6, OperandInfo499}, // Inst #3984 = t2EORri + {6, OperandInfo500}, // Inst #3985 = t2EORrr + {7, OperandInfo501}, // Inst #3986 = t2EORrs + {3, OperandInfo199}, // Inst #3987 = t2HINT + {1, OperandInfo2}, // Inst #3988 = t2HVC + {3, OperandInfo199}, // Inst #3989 = t2ISB + {2, OperandInfo7}, // Inst #3990 = t2IT + {2, OperandInfo148}, // Inst #3991 = t2Int_eh_sjlj_setjmp + {2, OperandInfo148}, // Inst #3992 = t2Int_eh_sjlj_setjmp_nofp + {4, OperandInfo517}, // Inst #3993 = t2LDA + {4, OperandInfo517}, // Inst #3994 = t2LDAB + {4, OperandInfo517}, // Inst #3995 = t2LDAEX + {4, OperandInfo517}, // Inst #3996 = t2LDAEXB + {5, OperandInfo518}, // Inst #3997 = t2LDAEXD + {4, OperandInfo517}, // Inst #3998 = t2LDAEXH + {4, OperandInfo517}, // Inst #3999 = t2LDAH + {6, OperandInfo207}, // Inst #4000 = t2LDC2L_OFFSET + {6, OperandInfo208}, // Inst #4001 = t2LDC2L_OPTION + {6, OperandInfo207}, // Inst #4002 = t2LDC2L_POST + {6, OperandInfo207}, // Inst #4003 = t2LDC2L_PRE + {6, OperandInfo207}, // Inst #4004 = t2LDC2_OFFSET + {6, OperandInfo208}, // Inst #4005 = t2LDC2_OPTION + {6, OperandInfo207}, // Inst #4006 = t2LDC2_POST + {6, OperandInfo207}, // Inst #4007 = t2LDC2_PRE + {6, OperandInfo207}, // Inst #4008 = t2LDCL_OFFSET + {6, OperandInfo208}, // Inst #4009 = t2LDCL_OPTION + {6, OperandInfo207}, // Inst #4010 = t2LDCL_POST + {6, OperandInfo207}, // Inst #4011 = t2LDCL_PRE + {6, OperandInfo207}, // Inst #4012 = t2LDC_OFFSET + {6, OperandInfo208}, // Inst #4013 = t2LDC_OPTION + {6, OperandInfo207}, // Inst #4014 = t2LDC_POST + {6, OperandInfo207}, // Inst #4015 = t2LDC_PRE + {4, OperandInfo203}, // Inst #4016 = t2LDMDB + {5, OperandInfo65}, // Inst #4017 = t2LDMDB_UPD + {4, OperandInfo203}, // Inst #4018 = t2LDMIA + {5, OperandInfo65}, // Inst #4019 = t2LDMIA_UPD + {5, OperandInfo519}, // Inst #4020 = t2LDRBT + {6, OperandInfo210}, // Inst #4021 = t2LDRB_POST + {6, OperandInfo210}, // Inst #4022 = t2LDRB_PRE + {5, OperandInfo211}, // Inst #4023 = t2LDRBi12 + {5, OperandInfo211}, // Inst #4024 = t2LDRBi8 + {4, OperandInfo520}, // Inst #4025 = t2LDRBpci + {6, OperandInfo521}, // Inst #4026 = t2LDRBs + {7, OperandInfo522}, // Inst #4027 = t2LDRD_POST + {7, OperandInfo522}, // Inst #4028 = t2LDRD_PRE + {6, OperandInfo523}, // Inst #4029 = t2LDRDi8 + {5, OperandInfo524}, // Inst #4030 = t2LDREX + {4, OperandInfo517}, // Inst #4031 = t2LDREXB + {5, OperandInfo518}, // Inst #4032 = t2LDREXD + {4, OperandInfo517}, // Inst #4033 = t2LDREXH + {5, OperandInfo519}, // Inst #4034 = t2LDRHT + {6, OperandInfo210}, // Inst #4035 = t2LDRH_POST + {6, OperandInfo210}, // Inst #4036 = t2LDRH_PRE + {5, OperandInfo211}, // Inst #4037 = t2LDRHi12 + {5, OperandInfo211}, // Inst #4038 = t2LDRHi8 + {4, OperandInfo520}, // Inst #4039 = t2LDRHpci + {6, OperandInfo521}, // Inst #4040 = t2LDRHs + {5, OperandInfo519}, // Inst #4041 = t2LDRSBT + {6, OperandInfo210}, // Inst #4042 = t2LDRSB_POST + {6, OperandInfo210}, // Inst #4043 = t2LDRSB_PRE + {5, OperandInfo211}, // Inst #4044 = t2LDRSBi12 + {5, OperandInfo211}, // Inst #4045 = t2LDRSBi8 + {4, OperandInfo520}, // Inst #4046 = t2LDRSBpci + {6, OperandInfo521}, // Inst #4047 = t2LDRSBs + {5, OperandInfo519}, // Inst #4048 = t2LDRSHT + {6, OperandInfo210}, // Inst #4049 = t2LDRSH_POST + {6, OperandInfo210}, // Inst #4050 = t2LDRSH_PRE + {5, OperandInfo211}, // Inst #4051 = t2LDRSHi12 + {5, OperandInfo211}, // Inst #4052 = t2LDRSHi8 + {4, OperandInfo520}, // Inst #4053 = t2LDRSHpci + {6, OperandInfo521}, // Inst #4054 = t2LDRSHs + {5, OperandInfo519}, // Inst #4055 = t2LDRT + {6, OperandInfo210}, // Inst #4056 = t2LDR_POST + {6, OperandInfo210}, // Inst #4057 = t2LDR_PRE + {5, OperandInfo86}, // Inst #4058 = t2LDRi12 + {5, OperandInfo86}, // Inst #4059 = t2LDRi8 + {4, OperandInfo525}, // Inst #4060 = t2LDRpci + {6, OperandInfo526}, // Inst #4061 = t2LDRs + {1, OperandInfo52}, // Inst #4062 = t2LE + {3, OperandInfo115}, // Inst #4063 = t2LEUpdate + {6, OperandInfo499}, // Inst #4064 = t2LSLri + {6, OperandInfo500}, // Inst #4065 = t2LSLrr + {6, OperandInfo499}, // Inst #4066 = t2LSRri + {6, OperandInfo500}, // Inst #4067 = t2LSRrr + {8, OperandInfo219}, // Inst #4068 = t2MCR + {8, OperandInfo219}, // Inst #4069 = t2MCR2 + {7, OperandInfo527}, // Inst #4070 = t2MCRR + {7, OperandInfo527}, // Inst #4071 = t2MCRR2 + {6, OperandInfo528}, // Inst #4072 = t2MLA + {6, OperandInfo528}, // Inst #4073 = t2MLS + {5, OperandInfo117}, // Inst #4074 = t2MOVTi16 + {5, OperandInfo529}, // Inst #4075 = t2MOVi + {4, OperandInfo508}, // Inst #4076 = t2MOVi16 + {5, OperandInfo530}, // Inst #4077 = t2MOVr + {4, OperandInfo513}, // Inst #4078 = t2MOVsra_flag + {4, OperandInfo513}, // Inst #4079 = t2MOVsrl_flag + {8, OperandInfo230}, // Inst #4080 = t2MRC + {8, OperandInfo230}, // Inst #4081 = t2MRC2 + {7, OperandInfo531}, // Inst #4082 = t2MRRC + {7, OperandInfo531}, // Inst #4083 = t2MRRC2 + {3, OperandInfo135}, // Inst #4084 = t2MRS_AR + {4, OperandInfo508}, // Inst #4085 = t2MRS_M + {4, OperandInfo508}, // Inst #4086 = t2MRSbanked + {3, OperandInfo135}, // Inst #4087 = t2MRSsys_AR + {4, OperandInfo532}, // Inst #4088 = t2MSR_AR + {4, OperandInfo532}, // Inst #4089 = t2MSR_M + {4, OperandInfo532}, // Inst #4090 = t2MSRbanked + {5, OperandInfo533}, // Inst #4091 = t2MUL + {5, OperandInfo529}, // Inst #4092 = t2MVNi + {5, OperandInfo534}, // Inst #4093 = t2MVNr + {6, OperandInfo535}, // Inst #4094 = t2MVNs + {6, OperandInfo499}, // Inst #4095 = t2ORNri + {6, OperandInfo500}, // Inst #4096 = t2ORNrr + {7, OperandInfo501}, // Inst #4097 = t2ORNrs + {6, OperandInfo499}, // Inst #4098 = t2ORRri + {6, OperandInfo500}, // Inst #4099 = t2ORRrr + {7, OperandInfo501}, // Inst #4100 = t2ORRrs + {6, OperandInfo536}, // Inst #4101 = t2PKHBT + {6, OperandInfo536}, // Inst #4102 = t2PKHTB + {4, OperandInfo537}, // Inst #4103 = t2PLDWi12 + {4, OperandInfo537}, // Inst #4104 = t2PLDWi8 + {5, OperandInfo538}, // Inst #4105 = t2PLDWs + {4, OperandInfo537}, // Inst #4106 = t2PLDi12 + {4, OperandInfo537}, // Inst #4107 = t2PLDi8 + {3, OperandInfo539}, // Inst #4108 = t2PLDpci + {5, OperandInfo538}, // Inst #4109 = t2PLDs + {4, OperandInfo537}, // Inst #4110 = t2PLIi12 + {4, OperandInfo537}, // Inst #4111 = t2PLIi8 + {3, OperandInfo539}, // Inst #4112 = t2PLIpci + {5, OperandInfo538}, // Inst #4113 = t2PLIs + {5, OperandInfo533}, // Inst #4114 = t2QADD + {5, OperandInfo533}, // Inst #4115 = t2QADD16 + {5, OperandInfo533}, // Inst #4116 = t2QADD8 + {5, OperandInfo533}, // Inst #4117 = t2QASX + {5, OperandInfo533}, // Inst #4118 = t2QDADD + {5, OperandInfo533}, // Inst #4119 = t2QDSUB + {5, OperandInfo533}, // Inst #4120 = t2QSAX + {5, OperandInfo533}, // Inst #4121 = t2QSUB + {5, OperandInfo533}, // Inst #4122 = t2QSUB16 + {5, OperandInfo533}, // Inst #4123 = t2QSUB8 + {4, OperandInfo513}, // Inst #4124 = t2RBIT + {4, OperandInfo513}, // Inst #4125 = t2REV + {4, OperandInfo513}, // Inst #4126 = t2REV16 + {4, OperandInfo513}, // Inst #4127 = t2REVSH + {3, OperandInfo135}, // Inst #4128 = t2RFEDB + {3, OperandInfo135}, // Inst #4129 = t2RFEDBW + {3, OperandInfo135}, // Inst #4130 = t2RFEIA + {3, OperandInfo135}, // Inst #4131 = t2RFEIAW + {6, OperandInfo499}, // Inst #4132 = t2RORri + {6, OperandInfo500}, // Inst #4133 = t2RORrr + {5, OperandInfo534}, // Inst #4134 = t2RRX + {6, OperandInfo499}, // Inst #4135 = t2RSBri + {6, OperandInfo500}, // Inst #4136 = t2RSBrr + {7, OperandInfo501}, // Inst #4137 = t2RSBrs + {5, OperandInfo533}, // Inst #4138 = t2SADD16 + {5, OperandInfo533}, // Inst #4139 = t2SADD8 + {5, OperandInfo533}, // Inst #4140 = t2SASX + {0, NULL}, // Inst #4141 = t2SB + {6, OperandInfo499}, // Inst #4142 = t2SBCri + {6, OperandInfo500}, // Inst #4143 = t2SBCrr + {7, OperandInfo501}, // Inst #4144 = t2SBCrs + {6, OperandInfo540}, // Inst #4145 = t2SBFX + {5, OperandInfo533}, // Inst #4146 = t2SDIV + {5, OperandInfo46}, // Inst #4147 = t2SEL + {1, OperandInfo2}, // Inst #4148 = t2SETPAN + {2, OperandInfo137}, // Inst #4149 = t2SG + {5, OperandInfo533}, // Inst #4150 = t2SHADD16 + {5, OperandInfo533}, // Inst #4151 = t2SHADD8 + {5, OperandInfo533}, // Inst #4152 = t2SHASX + {5, OperandInfo533}, // Inst #4153 = t2SHSAX + {5, OperandInfo533}, // Inst #4154 = t2SHSUB16 + {5, OperandInfo533}, // Inst #4155 = t2SHSUB8 + {3, OperandInfo199}, // Inst #4156 = t2SMC + {6, OperandInfo528}, // Inst #4157 = t2SMLABB + {6, OperandInfo528}, // Inst #4158 = t2SMLABT + {6, OperandInfo528}, // Inst #4159 = t2SMLAD + {6, OperandInfo528}, // Inst #4160 = t2SMLADX + {8, OperandInfo541}, // Inst #4161 = t2SMLAL + {8, OperandInfo541}, // Inst #4162 = t2SMLALBB + {8, OperandInfo541}, // Inst #4163 = t2SMLALBT + {8, OperandInfo541}, // Inst #4164 = t2SMLALD + {8, OperandInfo541}, // Inst #4165 = t2SMLALDX + {8, OperandInfo541}, // Inst #4166 = t2SMLALTB + {8, OperandInfo541}, // Inst #4167 = t2SMLALTT + {6, OperandInfo528}, // Inst #4168 = t2SMLATB + {6, OperandInfo528}, // Inst #4169 = t2SMLATT + {6, OperandInfo528}, // Inst #4170 = t2SMLAWB + {6, OperandInfo528}, // Inst #4171 = t2SMLAWT + {6, OperandInfo528}, // Inst #4172 = t2SMLSD + {6, OperandInfo528}, // Inst #4173 = t2SMLSDX + {8, OperandInfo541}, // Inst #4174 = t2SMLSLD + {8, OperandInfo541}, // Inst #4175 = t2SMLSLDX + {6, OperandInfo528}, // Inst #4176 = t2SMMLA + {6, OperandInfo528}, // Inst #4177 = t2SMMLAR + {6, OperandInfo528}, // Inst #4178 = t2SMMLS + {6, OperandInfo528}, // Inst #4179 = t2SMMLSR + {5, OperandInfo533}, // Inst #4180 = t2SMMUL + {5, OperandInfo533}, // Inst #4181 = t2SMMULR + {5, OperandInfo533}, // Inst #4182 = t2SMUAD + {5, OperandInfo533}, // Inst #4183 = t2SMUADX + {5, OperandInfo533}, // Inst #4184 = t2SMULBB + {5, OperandInfo533}, // Inst #4185 = t2SMULBT + {6, OperandInfo528}, // Inst #4186 = t2SMULL + {5, OperandInfo533}, // Inst #4187 = t2SMULTB + {5, OperandInfo533}, // Inst #4188 = t2SMULTT + {5, OperandInfo533}, // Inst #4189 = t2SMULWB + {5, OperandInfo533}, // Inst #4190 = t2SMULWT + {5, OperandInfo533}, // Inst #4191 = t2SMUSD + {5, OperandInfo533}, // Inst #4192 = t2SMUSDX + {3, OperandInfo199}, // Inst #4193 = t2SRSDB + {3, OperandInfo199}, // Inst #4194 = t2SRSDB_UPD + {3, OperandInfo199}, // Inst #4195 = t2SRSIA + {3, OperandInfo199}, // Inst #4196 = t2SRSIA_UPD + {6, OperandInfo542}, // Inst #4197 = t2SSAT + {5, OperandInfo543}, // Inst #4198 = t2SSAT16 + {5, OperandInfo533}, // Inst #4199 = t2SSAX + {5, OperandInfo533}, // Inst #4200 = t2SSUB16 + {5, OperandInfo533}, // Inst #4201 = t2SSUB8 + {6, OperandInfo207}, // Inst #4202 = t2STC2L_OFFSET + {6, OperandInfo208}, // Inst #4203 = t2STC2L_OPTION + {6, OperandInfo207}, // Inst #4204 = t2STC2L_POST + {6, OperandInfo207}, // Inst #4205 = t2STC2L_PRE + {6, OperandInfo207}, // Inst #4206 = t2STC2_OFFSET + {6, OperandInfo208}, // Inst #4207 = t2STC2_OPTION + {6, OperandInfo207}, // Inst #4208 = t2STC2_POST + {6, OperandInfo207}, // Inst #4209 = t2STC2_PRE + {6, OperandInfo207}, // Inst #4210 = t2STCL_OFFSET + {6, OperandInfo208}, // Inst #4211 = t2STCL_OPTION + {6, OperandInfo207}, // Inst #4212 = t2STCL_POST + {6, OperandInfo207}, // Inst #4213 = t2STCL_PRE + {6, OperandInfo207}, // Inst #4214 = t2STC_OFFSET + {6, OperandInfo208}, // Inst #4215 = t2STC_OPTION + {6, OperandInfo207}, // Inst #4216 = t2STC_POST + {6, OperandInfo207}, // Inst #4217 = t2STC_PRE + {4, OperandInfo517}, // Inst #4218 = t2STL + {4, OperandInfo517}, // Inst #4219 = t2STLB + {5, OperandInfo544}, // Inst #4220 = t2STLEX + {5, OperandInfo544}, // Inst #4221 = t2STLEXB + {6, OperandInfo545}, // Inst #4222 = t2STLEXD + {5, OperandInfo544}, // Inst #4223 = t2STLEXH + {4, OperandInfo517}, // Inst #4224 = t2STLH + {4, OperandInfo203}, // Inst #4225 = t2STMDB + {5, OperandInfo65}, // Inst #4226 = t2STMDB_UPD + {4, OperandInfo203}, // Inst #4227 = t2STMIA + {5, OperandInfo65}, // Inst #4228 = t2STMIA_UPD + {5, OperandInfo519}, // Inst #4229 = t2STRBT + {6, OperandInfo546}, // Inst #4230 = t2STRB_POST + {6, OperandInfo546}, // Inst #4231 = t2STRB_PRE + {5, OperandInfo519}, // Inst #4232 = t2STRBi12 + {5, OperandInfo519}, // Inst #4233 = t2STRBi8 + {6, OperandInfo547}, // Inst #4234 = t2STRBs + {7, OperandInfo548}, // Inst #4235 = t2STRD_POST + {7, OperandInfo548}, // Inst #4236 = t2STRD_PRE + {6, OperandInfo523}, // Inst #4237 = t2STRDi8 + {6, OperandInfo549}, // Inst #4238 = t2STREX + {5, OperandInfo544}, // Inst #4239 = t2STREXB + {6, OperandInfo545}, // Inst #4240 = t2STREXD + {5, OperandInfo544}, // Inst #4241 = t2STREXH + {5, OperandInfo519}, // Inst #4242 = t2STRHT + {6, OperandInfo546}, // Inst #4243 = t2STRH_POST + {6, OperandInfo546}, // Inst #4244 = t2STRH_PRE + {5, OperandInfo519}, // Inst #4245 = t2STRHi12 + {5, OperandInfo519}, // Inst #4246 = t2STRHi8 + {6, OperandInfo547}, // Inst #4247 = t2STRHs + {5, OperandInfo519}, // Inst #4248 = t2STRT + {6, OperandInfo550}, // Inst #4249 = t2STR_POST + {6, OperandInfo550}, // Inst #4250 = t2STR_PRE + {5, OperandInfo86}, // Inst #4251 = t2STRi12 + {5, OperandInfo86}, // Inst #4252 = t2STRi8 + {6, OperandInfo526}, // Inst #4253 = t2STRs + {3, OperandInfo199}, // Inst #4254 = t2SUBS_PC_LR + {6, OperandInfo502}, // Inst #4255 = t2SUBri + {5, OperandInfo503}, // Inst #4256 = t2SUBri12 + {6, OperandInfo504}, // Inst #4257 = t2SUBrr + {7, OperandInfo505}, // Inst #4258 = t2SUBrs + {6, OperandInfo506}, // Inst #4259 = t2SUBspImm + {5, OperandInfo507}, // Inst #4260 = t2SUBspImm12 + {6, OperandInfo536}, // Inst #4261 = t2SXTAB + {6, OperandInfo536}, // Inst #4262 = t2SXTAB16 + {6, OperandInfo536}, // Inst #4263 = t2SXTAH + {5, OperandInfo124}, // Inst #4264 = t2SXTB + {5, OperandInfo124}, // Inst #4265 = t2SXTB16 + {5, OperandInfo124}, // Inst #4266 = t2SXTH + {4, OperandInfo551}, // Inst #4267 = t2TBB + {4, OperandInfo551}, // Inst #4268 = t2TBH + {4, OperandInfo508}, // Inst #4269 = t2TEQri + {4, OperandInfo513}, // Inst #4270 = t2TEQrr + {5, OperandInfo120}, // Inst #4271 = t2TEQrs + {3, OperandInfo199}, // Inst #4272 = t2TSB + {4, OperandInfo508}, // Inst #4273 = t2TSTri + {4, OperandInfo513}, // Inst #4274 = t2TSTrr + {5, OperandInfo120}, // Inst #4275 = t2TSTrs + {4, OperandInfo552}, // Inst #4276 = t2TT + {4, OperandInfo552}, // Inst #4277 = t2TTA + {4, OperandInfo552}, // Inst #4278 = t2TTAT + {4, OperandInfo552}, // Inst #4279 = t2TTT + {5, OperandInfo533}, // Inst #4280 = t2UADD16 + {5, OperandInfo533}, // Inst #4281 = t2UADD8 + {5, OperandInfo533}, // Inst #4282 = t2UASX + {6, OperandInfo540}, // Inst #4283 = t2UBFX + {1, OperandInfo2}, // Inst #4284 = t2UDF + {5, OperandInfo533}, // Inst #4285 = t2UDIV + {5, OperandInfo533}, // Inst #4286 = t2UHADD16 + {5, OperandInfo533}, // Inst #4287 = t2UHADD8 + {5, OperandInfo533}, // Inst #4288 = t2UHASX + {5, OperandInfo533}, // Inst #4289 = t2UHSAX + {5, OperandInfo533}, // Inst #4290 = t2UHSUB16 + {5, OperandInfo533}, // Inst #4291 = t2UHSUB8 + {8, OperandInfo541}, // Inst #4292 = t2UMAAL + {8, OperandInfo541}, // Inst #4293 = t2UMLAL + {6, OperandInfo528}, // Inst #4294 = t2UMULL + {5, OperandInfo533}, // Inst #4295 = t2UQADD16 + {5, OperandInfo533}, // Inst #4296 = t2UQADD8 + {5, OperandInfo533}, // Inst #4297 = t2UQASX + {5, OperandInfo533}, // Inst #4298 = t2UQSAX + {5, OperandInfo533}, // Inst #4299 = t2UQSUB16 + {5, OperandInfo533}, // Inst #4300 = t2UQSUB8 + {5, OperandInfo533}, // Inst #4301 = t2USAD8 + {6, OperandInfo528}, // Inst #4302 = t2USADA8 + {6, OperandInfo542}, // Inst #4303 = t2USAT + {5, OperandInfo543}, // Inst #4304 = t2USAT16 + {5, OperandInfo533}, // Inst #4305 = t2USAX + {5, OperandInfo533}, // Inst #4306 = t2USUB16 + {5, OperandInfo533}, // Inst #4307 = t2USUB8 + {6, OperandInfo536}, // Inst #4308 = t2UXTAB + {6, OperandInfo536}, // Inst #4309 = t2UXTAB16 + {6, OperandInfo536}, // Inst #4310 = t2UXTAH + {5, OperandInfo124}, // Inst #4311 = t2UXTB + {5, OperandInfo124}, // Inst #4312 = t2UXTB16 + {5, OperandInfo124}, // Inst #4313 = t2UXTH + {3, OperandInfo127}, // Inst #4314 = t2WLS + {6, OperandInfo553}, // Inst #4315 = tADC + {5, OperandInfo74}, // Inst #4316 = tADDhirr + {6, OperandInfo554}, // Inst #4317 = tADDi3 + {6, OperandInfo555}, // Inst #4318 = tADDi8 + {5, OperandInfo556}, // Inst #4319 = tADDrSP + {5, OperandInfo557}, // Inst #4320 = tADDrSPi + {6, OperandInfo558}, // Inst #4321 = tADDrr + {5, OperandInfo559}, // Inst #4322 = tADDspi + {5, OperandInfo560}, // Inst #4323 = tADDspr + {4, OperandInfo561}, // Inst #4324 = tADR + {6, OperandInfo553}, // Inst #4325 = tAND + {6, OperandInfo554}, // Inst #4326 = tASRri + {6, OperandInfo553}, // Inst #4327 = tASRrr + {3, OperandInfo139}, // Inst #4328 = tB + {6, OperandInfo553}, // Inst #4329 = tBIC + {1, OperandInfo2}, // Inst #4330 = tBKPT + {3, OperandInfo562}, // Inst #4331 = tBL + {3, OperandInfo563}, // Inst #4332 = tBLXNSr + {3, OperandInfo562}, // Inst #4333 = tBLXi + {3, OperandInfo564}, // Inst #4334 = tBLXr + {3, OperandInfo135}, // Inst #4335 = tBX + {3, OperandInfo135}, // Inst #4336 = tBXNS + {3, OperandInfo139}, // Inst #4337 = tBcc + {2, OperandInfo565}, // Inst #4338 = tCBNZ + {2, OperandInfo565}, // Inst #4339 = tCBZ + {4, OperandInfo566}, // Inst #4340 = tCMNz + {4, OperandInfo194}, // Inst #4341 = tCMPhir + {4, OperandInfo142}, // Inst #4342 = tCMPi8 + {4, OperandInfo566}, // Inst #4343 = tCMPr + {2, OperandInfo7}, // Inst #4344 = tCPS + {6, OperandInfo553}, // Inst #4345 = tEOR + {3, OperandInfo199}, // Inst #4346 = tHINT + {1, OperandInfo2}, // Inst #4347 = tHLT + {2, OperandInfo44}, // Inst #4348 = tInt_WIN_eh_sjlj_longjmp + {2, OperandInfo148}, // Inst #4349 = tInt_eh_sjlj_longjmp + {2, OperandInfo148}, // Inst #4350 = tInt_eh_sjlj_setjmp + {4, OperandInfo567}, // Inst #4351 = tLDMIA + {5, OperandInfo568}, // Inst #4352 = tLDRBi + {5, OperandInfo569}, // Inst #4353 = tLDRBr + {5, OperandInfo568}, // Inst #4354 = tLDRHi + {5, OperandInfo569}, // Inst #4355 = tLDRHr + {5, OperandInfo569}, // Inst #4356 = tLDRSB + {5, OperandInfo569}, // Inst #4357 = tLDRSH + {5, OperandInfo568}, // Inst #4358 = tLDRi + {4, OperandInfo570}, // Inst #4359 = tLDRpci + {5, OperandInfo569}, // Inst #4360 = tLDRr + {5, OperandInfo571}, // Inst #4361 = tLDRspi + {6, OperandInfo554}, // Inst #4362 = tLSLri + {6, OperandInfo553}, // Inst #4363 = tLSLrr + {6, OperandInfo554}, // Inst #4364 = tLSRri + {6, OperandInfo553}, // Inst #4365 = tLSRrr + {2, OperandInfo148}, // Inst #4366 = tMOVSr + {5, OperandInfo572}, // Inst #4367 = tMOVi8 + {4, OperandInfo194}, // Inst #4368 = tMOVr + {6, OperandInfo573}, // Inst #4369 = tMUL + {5, OperandInfo574}, // Inst #4370 = tMVN + {6, OperandInfo553}, // Inst #4371 = tORR + {3, OperandInfo575}, // Inst #4372 = tPICADD + {3, OperandInfo147}, // Inst #4373 = tPOP + {3, OperandInfo147}, // Inst #4374 = tPUSH + {4, OperandInfo566}, // Inst #4375 = tREV + {4, OperandInfo566}, // Inst #4376 = tREV16 + {4, OperandInfo566}, // Inst #4377 = tREVSH + {6, OperandInfo553}, // Inst #4378 = tROR + {5, OperandInfo574}, // Inst #4379 = tRSB + {6, OperandInfo553}, // Inst #4380 = tSBC + {1, OperandInfo2}, // Inst #4381 = tSETEND + {5, OperandInfo141}, // Inst #4382 = tSTMIA_UPD + {5, OperandInfo568}, // Inst #4383 = tSTRBi + {5, OperandInfo569}, // Inst #4384 = tSTRBr + {5, OperandInfo568}, // Inst #4385 = tSTRHi + {5, OperandInfo569}, // Inst #4386 = tSTRHr + {5, OperandInfo568}, // Inst #4387 = tSTRi + {5, OperandInfo569}, // Inst #4388 = tSTRr + {5, OperandInfo571}, // Inst #4389 = tSTRspi + {6, OperandInfo554}, // Inst #4390 = tSUBi3 + {6, OperandInfo555}, // Inst #4391 = tSUBi8 + {6, OperandInfo558}, // Inst #4392 = tSUBrr + {5, OperandInfo559}, // Inst #4393 = tSUBspi + {3, OperandInfo199}, // Inst #4394 = tSVC + {4, OperandInfo566}, // Inst #4395 = tSXTB + {4, OperandInfo566}, // Inst #4396 = tSXTH + {0, NULL}, // Inst #4397 = tTRAP + {4, OperandInfo566}, // Inst #4398 = tTST + {1, OperandInfo2}, // Inst #4399 = tUDF + {4, OperandInfo566}, // Inst #4400 = tUXTB + {4, OperandInfo566}, // Inst #4401 = tUXTH + {0, NULL}, // Inst #4402 = t__brkdiv0 +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +extern const char ARMInstrNameData[] = { + /* 0 */ "G_FLOG10\0" + /* 9 */ "VMOVD0\0" + /* 16 */ "VMSR_P0\0" + /* 24 */ "VMRS_P0\0" + /* 32 */ "VMOVQ0\0" + /* 39 */ "VMRS_MVFR0\0" + /* 50 */ "SHA1SU0\0" + /* 58 */ "SHA256SU0\0" + /* 68 */ "t__brkdiv0\0" + /* 79 */ "VTBL1\0" + /* 85 */ "VMRS_MVFR1\0" + /* 96 */ "t2DCPS1\0" + /* 104 */ "SHA1SU1\0" + /* 112 */ "SHA256SU1\0" + /* 122 */ "VTBX1\0" + /* 128 */ "CDE_CX1\0" + /* 136 */ "t2LDRBi12\0" + /* 146 */ "t2STRBi12\0" + /* 156 */ "t2LDRSBi12\0" + /* 167 */ "t2PLDi12\0" + /* 176 */ "t2LDRHi12\0" + /* 186 */ "t2STRHi12\0" + /* 196 */ "t2LDRSHi12\0" + /* 207 */ "t2PLIi12\0" + /* 216 */ "t2LDRi12\0" + /* 225 */ "t2STRi12\0" + /* 234 */ "t2PLDWi12\0" + /* 244 */ "BR_JTm_i12\0" + /* 255 */ "t2SUBri12\0" + /* 265 */ "t2ADDri12\0" + /* 275 */ "t2SUBspImm12\0" + /* 288 */ "t2ADDspImm12\0" + /* 301 */ "MVE_VSTRB32\0" + /* 313 */ "MVE_VSTRH32\0" + /* 325 */ "COPY_STRUCT_BYVAL_I32\0" + /* 347 */ "MVE_VCTP32\0" + /* 358 */ "MVE_VDUP32\0" + /* 369 */ "MVE_VBRSR32\0" + /* 381 */ "MVE_VLDRBS32\0" + /* 394 */ "MVE_VLDRHS32\0" + /* 407 */ "MVE_VLDRBU32\0" + /* 420 */ "MVE_VLDRHU32\0" + /* 433 */ "MVE_VLDRWU32\0" + /* 446 */ "MVE_VSTRWU32\0" + /* 459 */ "MVE_VLD20_32\0" + /* 472 */ "MVE_VST20_32\0" + /* 485 */ "MVE_VLD40_32\0" + /* 498 */ "MVE_VST40_32\0" + /* 511 */ "MVE_VLD21_32\0" + /* 524 */ "MVE_VST21_32\0" + /* 537 */ "MVE_VLD41_32\0" + /* 550 */ "MVE_VST41_32\0" + /* 563 */ "MVE_VLD42_32\0" + /* 576 */ "MVE_VST42_32\0" + /* 589 */ "MVE_VLD43_32\0" + /* 602 */ "MVE_VST43_32\0" + /* 615 */ "MVE_VREV64_32\0" + /* 629 */ "CMP_SWAP_32\0" + /* 641 */ "MVE_DLSTP_32\0" + /* 654 */ "MVE_WLSTP_32\0" + /* 667 */ "MVE_VMOV_from_lane_32\0" + /* 689 */ "MVE_VMOV_to_lane_32\0" + /* 709 */ "VLD3dWB_fixed_Asm_32\0" + /* 730 */ "VST3dWB_fixed_Asm_32\0" + /* 751 */ "VLD4dWB_fixed_Asm_32\0" + /* 772 */ "VST4dWB_fixed_Asm_32\0" + /* 793 */ "VLD1LNdWB_fixed_Asm_32\0" + /* 816 */ "VST1LNdWB_fixed_Asm_32\0" + /* 839 */ "VLD2LNdWB_fixed_Asm_32\0" + /* 862 */ "VST2LNdWB_fixed_Asm_32\0" + /* 885 */ "VLD3LNdWB_fixed_Asm_32\0" + /* 908 */ "VST3LNdWB_fixed_Asm_32\0" + /* 931 */ "VLD4LNdWB_fixed_Asm_32\0" + /* 954 */ "VST4LNdWB_fixed_Asm_32\0" + /* 977 */ "VLD3DUPdWB_fixed_Asm_32\0" + /* 1001 */ "VLD4DUPdWB_fixed_Asm_32\0" + /* 1025 */ "VLD3qWB_fixed_Asm_32\0" + /* 1046 */ "VST3qWB_fixed_Asm_32\0" + /* 1067 */ "VLD4qWB_fixed_Asm_32\0" + /* 1088 */ "VST4qWB_fixed_Asm_32\0" + /* 1109 */ "VLD2LNqWB_fixed_Asm_32\0" + /* 1132 */ "VST2LNqWB_fixed_Asm_32\0" + /* 1155 */ "VLD3LNqWB_fixed_Asm_32\0" + /* 1178 */ "VST3LNqWB_fixed_Asm_32\0" + /* 1201 */ "VLD4LNqWB_fixed_Asm_32\0" + /* 1224 */ "VST4LNqWB_fixed_Asm_32\0" + /* 1247 */ "VLD3DUPqWB_fixed_Asm_32\0" + /* 1271 */ "VLD4DUPqWB_fixed_Asm_32\0" + /* 1295 */ "VLD3dWB_register_Asm_32\0" + /* 1319 */ "VST3dWB_register_Asm_32\0" + /* 1343 */ "VLD4dWB_register_Asm_32\0" + /* 1367 */ "VST4dWB_register_Asm_32\0" + /* 1391 */ "VLD1LNdWB_register_Asm_32\0" + /* 1417 */ "VST1LNdWB_register_Asm_32\0" + /* 1443 */ "VLD2LNdWB_register_Asm_32\0" + /* 1469 */ "VST2LNdWB_register_Asm_32\0" + /* 1495 */ "VLD3LNdWB_register_Asm_32\0" + /* 1521 */ "VST3LNdWB_register_Asm_32\0" + /* 1547 */ "VLD4LNdWB_register_Asm_32\0" + /* 1573 */ "VST4LNdWB_register_Asm_32\0" + /* 1599 */ "VLD3DUPdWB_register_Asm_32\0" + /* 1626 */ "VLD4DUPdWB_register_Asm_32\0" + /* 1653 */ "VLD3qWB_register_Asm_32\0" + /* 1677 */ "VST3qWB_register_Asm_32\0" + /* 1701 */ "VLD4qWB_register_Asm_32\0" + /* 1725 */ "VST4qWB_register_Asm_32\0" + /* 1749 */ "VLD2LNqWB_register_Asm_32\0" + /* 1775 */ "VST2LNqWB_register_Asm_32\0" + /* 1801 */ "VLD3LNqWB_register_Asm_32\0" + /* 1827 */ "VST3LNqWB_register_Asm_32\0" + /* 1853 */ "VLD4LNqWB_register_Asm_32\0" + /* 1879 */ "VST4LNqWB_register_Asm_32\0" + /* 1905 */ "VLD3DUPqWB_register_Asm_32\0" + /* 1932 */ "VLD4DUPqWB_register_Asm_32\0" + /* 1959 */ "VLD3dAsm_32\0" + /* 1971 */ "VST3dAsm_32\0" + /* 1983 */ "VLD4dAsm_32\0" + /* 1995 */ "VST4dAsm_32\0" + /* 2007 */ "VLD1LNdAsm_32\0" + /* 2021 */ "VST1LNdAsm_32\0" + /* 2035 */ "VLD2LNdAsm_32\0" + /* 2049 */ "VST2LNdAsm_32\0" + /* 2063 */ "VLD3LNdAsm_32\0" + /* 2077 */ "VST3LNdAsm_32\0" + /* 2091 */ "VLD4LNdAsm_32\0" + /* 2105 */ "VST4LNdAsm_32\0" + /* 2119 */ "VLD3DUPdAsm_32\0" + /* 2134 */ "VLD4DUPdAsm_32\0" + /* 2149 */ "VLD3qAsm_32\0" + /* 2161 */ "VST3qAsm_32\0" + /* 2173 */ "VLD4qAsm_32\0" + /* 2185 */ "VST4qAsm_32\0" + /* 2197 */ "VLD2LNqAsm_32\0" + /* 2211 */ "VST2LNqAsm_32\0" + /* 2225 */ "VLD3LNqAsm_32\0" + /* 2239 */ "VST3LNqAsm_32\0" + /* 2253 */ "VLD4LNqAsm_32\0" + /* 2267 */ "VST4LNqAsm_32\0" + /* 2281 */ "VLD3DUPqAsm_32\0" + /* 2296 */ "VLD4DUPqAsm_32\0" + /* 2311 */ "VLD2b32\0" + /* 2319 */ "VST2b32\0" + /* 2327 */ "VLD1d32\0" + /* 2335 */ "VST1d32\0" + /* 2343 */ "VLD2d32\0" + /* 2351 */ "VST2d32\0" + /* 2359 */ "VLD3d32\0" + /* 2367 */ "VST3d32\0" + /* 2375 */ "VREV64d32\0" + /* 2385 */ "VLD4d32\0" + /* 2393 */ "VST4d32\0" + /* 2401 */ "VLD1LNd32\0" + /* 2411 */ "VST1LNd32\0" + /* 2421 */ "VLD2LNd32\0" + /* 2431 */ "VST2LNd32\0" + /* 2441 */ "VLD3LNd32\0" + /* 2451 */ "VST3LNd32\0" + /* 2461 */ "VLD4LNd32\0" + /* 2471 */ "VST4LNd32\0" + /* 2481 */ "VTRNd32\0" + /* 2489 */ "VLD1DUPd32\0" + /* 2500 */ "VLD2DUPd32\0" + /* 2511 */ "VLD3DUPd32\0" + /* 2522 */ "VLD4DUPd32\0" + /* 2533 */ "VEXTd32\0" + /* 2541 */ "VCMLAv2f32\0" + /* 2552 */ "VCADDv2f32\0" + /* 2563 */ "VMOVv2f32\0" + /* 2573 */ "VCGEzv2f32\0" + /* 2584 */ "VCLEzv2f32\0" + /* 2595 */ "VCEQzv2f32\0" + /* 2606 */ "VCGTzv2f32\0" + /* 2617 */ "VCLTzv2f32\0" + /* 2628 */ "VCMLAv4f32\0" + /* 2639 */ "VCADDv4f32\0" + /* 2650 */ "MVE_VPTv4f32\0" + /* 2663 */ "VMOVv4f32\0" + /* 2673 */ "VCGEzv4f32\0" + /* 2684 */ "VCLEzv4f32\0" + /* 2695 */ "VCEQzv4f32\0" + /* 2706 */ "VCGTzv4f32\0" + /* 2717 */ "VCLTzv4f32\0" + /* 2728 */ "MVE_VCMLAf32\0" + /* 2741 */ "MVE_VFMAf32\0" + /* 2753 */ "MVE_VMINNMAf32\0" + /* 2768 */ "MVE_VMAXNMAf32\0" + /* 2783 */ "MVE_VSUBf32\0" + /* 2795 */ "MVE_VABDf32\0" + /* 2807 */ "MVE_VCADDf32\0" + /* 2820 */ "MVE_VADDf32\0" + /* 2832 */ "MVE_VNEGf32\0" + /* 2844 */ "MVE_VCMULf32\0" + /* 2857 */ "MVE_VMULf32\0" + /* 2869 */ "MVE_VMINNMf32\0" + /* 2883 */ "MVE_VMAXNMf32\0" + /* 2897 */ "MVE_VCMPf32\0" + /* 2909 */ "MVE_VABSf32\0" + /* 2921 */ "MVE_VFMSf32\0" + /* 2933 */ "MVE_VFMA_qr_Sf32\0" + /* 2950 */ "MVE_VMINNMAVf32\0" + /* 2966 */ "MVE_VMAXNMAVf32\0" + /* 2982 */ "MVE_VMINNMVf32\0" + /* 2997 */ "MVE_VMAXNMVf32\0" + /* 3012 */ "MVE_VFMA_qr_f32\0" + /* 3028 */ "MVE_VSUB_qr_f32\0" + /* 3044 */ "MVE_VADD_qr_f32\0" + /* 3060 */ "MVE_VMUL_qr_f32\0" + /* 3076 */ "MVE_VMOVimmf32\0" + /* 3091 */ "VMLAv2i32\0" + /* 3101 */ "VSUBv2i32\0" + /* 3111 */ "VADDv2i32\0" + /* 3121 */ "VQNEGv2i32\0" + /* 3132 */ "VQRDMLAHv2i32\0" + /* 3146 */ "VQDMULHv2i32\0" + /* 3159 */ "VQRDMULHv2i32\0" + /* 3173 */ "VQRDMLSHv2i32\0" + /* 3187 */ "VSLIv2i32\0" + /* 3197 */ "VSRIv2i32\0" + /* 3207 */ "VMULv2i32\0" + /* 3217 */ "VRSUBHNv2i32\0" + /* 3230 */ "VSUBHNv2i32\0" + /* 3242 */ "VRADDHNv2i32\0" + /* 3255 */ "VADDHNv2i32\0" + /* 3267 */ "VRSHRNv2i32\0" + /* 3279 */ "VSHRNv2i32\0" + /* 3290 */ "VQSHRUNv2i32\0" + /* 3303 */ "VQRSHRUNv2i32\0" + /* 3317 */ "VMVNv2i32\0" + /* 3327 */ "VMOVNv2i32\0" + /* 3338 */ "VCEQv2i32\0" + /* 3348 */ "VQABSv2i32\0" + /* 3359 */ "VABSv2i32\0" + /* 3369 */ "VCLSv2i32\0" + /* 3379 */ "VMLSv2i32\0" + /* 3389 */ "VTSTv2i32\0" + /* 3399 */ "VMOVv2i32\0" + /* 3409 */ "VCLZv2i32\0" + /* 3419 */ "VBICiv2i32\0" + /* 3430 */ "VSHLiv2i32\0" + /* 3441 */ "VORRiv2i32\0" + /* 3452 */ "VQSHLsiv2i32\0" + /* 3465 */ "VQSHLuiv2i32\0" + /* 3478 */ "VMLAslv2i32\0" + /* 3490 */ "VQRDMLAHslv2i32\0" + /* 3506 */ "VQDMULHslv2i32\0" + /* 3521 */ "VQRDMULHslv2i32\0" + /* 3537 */ "VQRDMLSHslv2i32\0" + /* 3553 */ "VQDMLALslv2i32\0" + /* 3568 */ "VQDMULLslv2i32\0" + /* 3583 */ "VQDMLSLslv2i32\0" + /* 3598 */ "VMULslv2i32\0" + /* 3610 */ "VMLSslv2i32\0" + /* 3622 */ "VABAsv2i32\0" + /* 3633 */ "VRSRAsv2i32\0" + /* 3645 */ "VSRAsv2i32\0" + /* 3656 */ "VHSUBsv2i32\0" + /* 3668 */ "VQSUBsv2i32\0" + /* 3680 */ "VABDsv2i32\0" + /* 3691 */ "VRHADDsv2i32\0" + /* 3704 */ "VHADDsv2i32\0" + /* 3716 */ "VQADDsv2i32\0" + /* 3728 */ "VCGEsv2i32\0" + /* 3739 */ "VPADALsv2i32\0" + /* 3752 */ "VPADDLsv2i32\0" + /* 3765 */ "VQSHLsv2i32\0" + /* 3777 */ "VQRSHLsv2i32\0" + /* 3790 */ "VRSHLsv2i32\0" + /* 3802 */ "VSHLsv2i32\0" + /* 3813 */ "VMINsv2i32\0" + /* 3824 */ "VQSHRNsv2i32\0" + /* 3837 */ "VQRSHRNsv2i32\0" + /* 3851 */ "VQMOVNsv2i32\0" + /* 3864 */ "VRSHRsv2i32\0" + /* 3876 */ "VSHRsv2i32\0" + /* 3887 */ "VCGTsv2i32\0" + /* 3898 */ "VMAXsv2i32\0" + /* 3909 */ "VMLALslsv2i32\0" + /* 3923 */ "VMULLslsv2i32\0" + /* 3937 */ "VMLSLslsv2i32\0" + /* 3951 */ "VABAuv2i32\0" + /* 3962 */ "VRSRAuv2i32\0" + /* 3974 */ "VSRAuv2i32\0" + /* 3985 */ "VHSUBuv2i32\0" + /* 3997 */ "VQSUBuv2i32\0" + /* 4009 */ "VABDuv2i32\0" + /* 4020 */ "VRHADDuv2i32\0" + /* 4033 */ "VHADDuv2i32\0" + /* 4045 */ "VQADDuv2i32\0" + /* 4057 */ "VCGEuv2i32\0" + /* 4068 */ "VPADALuv2i32\0" + /* 4081 */ "VPADDLuv2i32\0" + /* 4094 */ "VQSHLuv2i32\0" + /* 4106 */ "VQRSHLuv2i32\0" + /* 4119 */ "VRSHLuv2i32\0" + /* 4131 */ "VSHLuv2i32\0" + /* 4142 */ "VMINuv2i32\0" + /* 4153 */ "VQSHRNuv2i32\0" + /* 4166 */ "VQRSHRNuv2i32\0" + /* 4180 */ "VQMOVNuv2i32\0" + /* 4193 */ "VRSHRuv2i32\0" + /* 4205 */ "VSHRuv2i32\0" + /* 4216 */ "VCGTuv2i32\0" + /* 4227 */ "VMAXuv2i32\0" + /* 4238 */ "VMLALsluv2i32\0" + /* 4252 */ "VMULLsluv2i32\0" + /* 4266 */ "VMLSLsluv2i32\0" + /* 4280 */ "VQSHLsuv2i32\0" + /* 4293 */ "VQMOVNsuv2i32\0" + /* 4307 */ "VCGEzv2i32\0" + /* 4318 */ "VCLEzv2i32\0" + /* 4329 */ "VCEQzv2i32\0" + /* 4340 */ "VCGTzv2i32\0" + /* 4351 */ "VCLTzv2i32\0" + /* 4362 */ "VMLAv4i32\0" + /* 4372 */ "VSUBv4i32\0" + /* 4382 */ "VADDv4i32\0" + /* 4392 */ "VQNEGv4i32\0" + /* 4403 */ "VQRDMLAHv4i32\0" + /* 4417 */ "VQDMULHv4i32\0" + /* 4430 */ "VQRDMULHv4i32\0" + /* 4444 */ "VQRDMLSHv4i32\0" + /* 4458 */ "VSLIv4i32\0" + /* 4468 */ "VSRIv4i32\0" + /* 4478 */ "VQDMLALv4i32\0" + /* 4491 */ "VQDMULLv4i32\0" + /* 4504 */ "VQDMLSLv4i32\0" + /* 4517 */ "VMULv4i32\0" + /* 4527 */ "VMVNv4i32\0" + /* 4537 */ "VCEQv4i32\0" + /* 4547 */ "VQABSv4i32\0" + /* 4558 */ "VABSv4i32\0" + /* 4568 */ "VCLSv4i32\0" + /* 4578 */ "VMLSv4i32\0" + /* 4588 */ "MVE_VPTv4i32\0" + /* 4601 */ "VTSTv4i32\0" + /* 4611 */ "VMOVv4i32\0" + /* 4621 */ "VCLZv4i32\0" + /* 4631 */ "VBICiv4i32\0" + /* 4642 */ "VSHLiv4i32\0" + /* 4653 */ "VORRiv4i32\0" + /* 4664 */ "VQSHLsiv4i32\0" + /* 4677 */ "VQSHLuiv4i32\0" + /* 4690 */ "VMLAslv4i32\0" + /* 4702 */ "VQRDMLAHslv4i32\0" + /* 4718 */ "VQDMULHslv4i32\0" + /* 4733 */ "VQRDMULHslv4i32\0" + /* 4749 */ "VQRDMLSHslv4i32\0" + /* 4765 */ "VMULslv4i32\0" + /* 4777 */ "VMLSslv4i32\0" + /* 4789 */ "VABAsv4i32\0" + /* 4800 */ "VRSRAsv4i32\0" + /* 4812 */ "VSRAsv4i32\0" + /* 4823 */ "VHSUBsv4i32\0" + /* 4835 */ "VQSUBsv4i32\0" + /* 4847 */ "VABDsv4i32\0" + /* 4858 */ "VRHADDsv4i32\0" + /* 4871 */ "VHADDsv4i32\0" + /* 4883 */ "VQADDsv4i32\0" + /* 4895 */ "VCGEsv4i32\0" + /* 4906 */ "VABALsv4i32\0" + /* 4918 */ "VPADALsv4i32\0" + /* 4931 */ "VMLALsv4i32\0" + /* 4943 */ "VSUBLsv4i32\0" + /* 4955 */ "VABDLsv4i32\0" + /* 4967 */ "VPADDLsv4i32\0" + /* 4980 */ "VADDLsv4i32\0" + /* 4992 */ "VQSHLsv4i32\0" + /* 5004 */ "VQRSHLsv4i32\0" + /* 5017 */ "VRSHLsv4i32\0" + /* 5029 */ "VSHLsv4i32\0" + /* 5040 */ "VSHLLsv4i32\0" + /* 5052 */ "VMULLsv4i32\0" + /* 5064 */ "VMLSLsv4i32\0" + /* 5076 */ "VMOVLsv4i32\0" + /* 5088 */ "VMINsv4i32\0" + /* 5099 */ "VRSHRsv4i32\0" + /* 5111 */ "VSHRsv4i32\0" + /* 5122 */ "VCGTsv4i32\0" + /* 5133 */ "VSUBWsv4i32\0" + /* 5145 */ "VADDWsv4i32\0" + /* 5157 */ "VMAXsv4i32\0" + /* 5168 */ "VABAuv4i32\0" + /* 5179 */ "VRSRAuv4i32\0" + /* 5191 */ "VSRAuv4i32\0" + /* 5202 */ "VHSUBuv4i32\0" + /* 5214 */ "VQSUBuv4i32\0" + /* 5226 */ "VABDuv4i32\0" + /* 5237 */ "VRHADDuv4i32\0" + /* 5250 */ "VHADDuv4i32\0" + /* 5262 */ "VQADDuv4i32\0" + /* 5274 */ "VCGEuv4i32\0" + /* 5285 */ "VABALuv4i32\0" + /* 5297 */ "VPADALuv4i32\0" + /* 5310 */ "VMLALuv4i32\0" + /* 5322 */ "VSUBLuv4i32\0" + /* 5334 */ "VABDLuv4i32\0" + /* 5346 */ "VPADDLuv4i32\0" + /* 5359 */ "VADDLuv4i32\0" + /* 5371 */ "VQSHLuv4i32\0" + /* 5383 */ "VQRSHLuv4i32\0" + /* 5396 */ "VRSHLuv4i32\0" + /* 5408 */ "VSHLuv4i32\0" + /* 5419 */ "VSHLLuv4i32\0" + /* 5431 */ "VMULLuv4i32\0" + /* 5443 */ "VMLSLuv4i32\0" + /* 5455 */ "VMOVLuv4i32\0" + /* 5467 */ "VMINuv4i32\0" + /* 5478 */ "VRSHRuv4i32\0" + /* 5490 */ "VSHRuv4i32\0" + /* 5501 */ "VCGTuv4i32\0" + /* 5512 */ "VSUBWuv4i32\0" + /* 5524 */ "VADDWuv4i32\0" + /* 5536 */ "VMAXuv4i32\0" + /* 5547 */ "VQSHLsuv4i32\0" + /* 5560 */ "VCGEzv4i32\0" + /* 5571 */ "VCLEzv4i32\0" + /* 5582 */ "VCEQzv4i32\0" + /* 5593 */ "VCGTzv4i32\0" + /* 5604 */ "VCLTzv4i32\0" + /* 5615 */ "MVE_VSUBi32\0" + /* 5627 */ "MVE_VCADDi32\0" + /* 5640 */ "VPADDi32\0" + /* 5649 */ "MVE_VADDi32\0" + /* 5661 */ "MVE_VQDMULHi32\0" + /* 5676 */ "MVE_VQRDMULHi32\0" + /* 5692 */ "VSHLLi32\0" + /* 5701 */ "MVE_VMULi32\0" + /* 5713 */ "VGETLNi32\0" + /* 5723 */ "VSETLNi32\0" + /* 5733 */ "MVE_VCMPi32\0" + /* 5745 */ "MVE_VSUB_qr_i32\0" + /* 5761 */ "MVE_VADD_qr_i32\0" + /* 5777 */ "MVE_VMUL_qr_i32\0" + /* 5793 */ "MVE_VBICimmi32\0" + /* 5808 */ "MVE_VMVNimmi32\0" + /* 5823 */ "MVE_VORRimmi32\0" + /* 5838 */ "MVE_VMOVimmi32\0" + /* 5853 */ "MVE_VSHL_immi32\0" + /* 5869 */ "MVE_VSLIimm32\0" + /* 5883 */ "MVE_VSRIimm32\0" + /* 5897 */ "VLD1q32\0" + /* 5905 */ "VST1q32\0" + /* 5913 */ "VLD2q32\0" + /* 5921 */ "VST2q32\0" + /* 5929 */ "VLD3q32\0" + /* 5937 */ "VST3q32\0" + /* 5945 */ "VREV64q32\0" + /* 5955 */ "VLD4q32\0" + /* 5963 */ "VST4q32\0" + /* 5971 */ "VLD2LNq32\0" + /* 5981 */ "VST2LNq32\0" + /* 5991 */ "VLD3LNq32\0" + /* 6001 */ "VST3LNq32\0" + /* 6011 */ "VLD4LNq32\0" + /* 6021 */ "VST4LNq32\0" + /* 6031 */ "VTRNq32\0" + /* 6039 */ "VZIPq32\0" + /* 6047 */ "VLD1DUPq32\0" + /* 6058 */ "VLD3DUPq32\0" + /* 6069 */ "VLD4DUPq32\0" + /* 6080 */ "VUZPq32\0" + /* 6088 */ "VEXTq32\0" + /* 6096 */ "MVE_VPTv4s32\0" + /* 6109 */ "MVE_VMINAs32\0" + /* 6122 */ "MVE_VMAXAs32\0" + /* 6135 */ "MVE_VMULLBs32\0" + /* 6149 */ "MVE_VHSUBs32\0" + /* 6162 */ "MVE_VQSUBs32\0" + /* 6175 */ "MVE_VABDs32\0" + /* 6187 */ "MVE_VHCADDs32\0" + /* 6201 */ "MVE_VRHADDs32\0" + /* 6215 */ "MVE_VHADDs32\0" + /* 6228 */ "MVE_VQADDs32\0" + /* 6241 */ "MVE_VQNEGs32\0" + /* 6254 */ "MVE_VNEGs32\0" + /* 6266 */ "MVE_VQDMLADHs32\0" + /* 6282 */ "MVE_VQRDMLADHs32\0" + /* 6299 */ "MVE_VQDMLSDHs32\0" + /* 6315 */ "MVE_VQRDMLSDHs32\0" + /* 6332 */ "MVE_VRMULHs32\0" + /* 6346 */ "MVE_VMULHs32\0" + /* 6359 */ "MVE_VRMLALDAVHs32\0" + /* 6377 */ "MVE_VRMLSLDAVHs32\0" + /* 6395 */ "VPMINs32\0" + /* 6404 */ "MVE_VMINs32\0" + /* 6416 */ "MVE_VCMPs32\0" + /* 6428 */ "MVE_VQABSs32\0" + /* 6441 */ "MVE_VABSs32\0" + /* 6453 */ "MVE_VCLSs32\0" + /* 6465 */ "MVE_VMULLTs32\0" + /* 6479 */ "MVE_VABAVs32\0" + /* 6492 */ "MVE_VMLADAVs32\0" + /* 6507 */ "MVE_VMLALDAVs32\0" + /* 6523 */ "MVE_VMLSLDAVs32\0" + /* 6539 */ "MVE_VMLSDAVs32\0" + /* 6554 */ "MVE_VMINAVs32\0" + /* 6568 */ "MVE_VMAXAVs32\0" + /* 6582 */ "MVE_VMINVs32\0" + /* 6595 */ "MVE_VMAXVs32\0" + /* 6608 */ "VPMAXs32\0" + /* 6617 */ "MVE_VMAXs32\0" + /* 6629 */ "MVE_VQDMLADHXs32\0" + /* 6646 */ "MVE_VQRDMLADHXs32\0" + /* 6664 */ "MVE_VQDMLSDHXs32\0" + /* 6681 */ "MVE_VQRDMLSDHXs32\0" + /* 6699 */ "MVE_VCLZs32\0" + /* 6711 */ "MVE_VMLA_qr_s32\0" + /* 6727 */ "MVE_VHSUB_qr_s32\0" + /* 6744 */ "MVE_VQSUB_qr_s32\0" + /* 6761 */ "MVE_VHADD_qr_s32\0" + /* 6778 */ "MVE_VQADD_qr_s32\0" + /* 6795 */ "MVE_VQDMULH_qr_s32\0" + /* 6814 */ "MVE_VQRDMULH_qr_s32\0" + /* 6834 */ "MVE_VMLAS_qr_s32\0" + /* 6851 */ "MVE_VRMLALDAVHas32\0" + /* 6870 */ "MVE_VRMLSLDAVHas32\0" + /* 6889 */ "MVE_VMLADAVas32\0" + /* 6905 */ "MVE_VMLALDAVas32\0" + /* 6922 */ "MVE_VMLSLDAVas32\0" + /* 6939 */ "MVE_VMLSDAVas32\0" + /* 6955 */ "MVE_VQSHL_by_vecs32\0" + /* 6975 */ "MVE_VQRSHL_by_vecs32\0" + /* 6996 */ "MVE_VRSHL_by_vecs32\0" + /* 7016 */ "MVE_VSHL_by_vecs32\0" + /* 7035 */ "MVE_VQSHRNbhs32\0" + /* 7051 */ "MVE_VQRSHRNbhs32\0" + /* 7068 */ "MVE_VQSHRNths32\0" + /* 7084 */ "MVE_VQRSHRNths32\0" + /* 7101 */ "MVE_VQSHLimms32\0" + /* 7117 */ "MVE_VRSHR_imms32\0" + /* 7134 */ "MVE_VSHR_imms32\0" + /* 7150 */ "MVE_VQSHLU_imms32\0" + /* 7168 */ "MVE_VQDMLAH_qrs32\0" + /* 7186 */ "MVE_VQRDMLAH_qrs32\0" + /* 7205 */ "MVE_VQDMLASH_qrs32\0" + /* 7224 */ "MVE_VQRDMLASH_qrs32\0" + /* 7244 */ "MVE_VQSHL_qrs32\0" + /* 7260 */ "MVE_VQRSHL_qrs32\0" + /* 7277 */ "MVE_VRSHL_qrs32\0" + /* 7293 */ "MVE_VSHL_qrs32\0" + /* 7308 */ "MVE_VRMLALDAVHxs32\0" + /* 7327 */ "MVE_VRMLSLDAVHxs32\0" + /* 7346 */ "MVE_VMLADAVxs32\0" + /* 7362 */ "MVE_VMLALDAVxs32\0" + /* 7379 */ "MVE_VMLSLDAVxs32\0" + /* 7396 */ "MVE_VMLSDAVxs32\0" + /* 7412 */ "MVE_VRMLALDAVHaxs32\0" + /* 7432 */ "MVE_VRMLSLDAVHaxs32\0" + /* 7452 */ "MVE_VMLADAVaxs32\0" + /* 7469 */ "MVE_VMLALDAVaxs32\0" + /* 7487 */ "MVE_VMLSLDAVaxs32\0" + /* 7505 */ "MVE_VMLSDAVaxs32\0" + /* 7522 */ "MVE_VPTv4u32\0" + /* 7535 */ "MVE_VMULLBu32\0" + /* 7549 */ "MVE_VHSUBu32\0" + /* 7562 */ "MVE_VQSUBu32\0" + /* 7575 */ "MVE_VABDu32\0" + /* 7587 */ "MVE_VRHADDu32\0" + /* 7601 */ "MVE_VHADDu32\0" + /* 7614 */ "MVE_VQADDu32\0" + /* 7627 */ "MVE_VRMULHu32\0" + /* 7641 */ "MVE_VMULHu32\0" + /* 7654 */ "MVE_VRMLALDAVHu32\0" + /* 7672 */ "VPMINu32\0" + /* 7681 */ "MVE_VMINu32\0" + /* 7693 */ "MVE_VCMPu32\0" + /* 7705 */ "MVE_VDDUPu32\0" + /* 7718 */ "MVE_VIDUPu32\0" + /* 7731 */ "MVE_VDWDUPu32\0" + /* 7745 */ "MVE_VIWDUPu32\0" + /* 7759 */ "MVE_VMULLTu32\0" + /* 7773 */ "MVE_VABAVu32\0" + /* 7786 */ "MVE_VMLADAVu32\0" + /* 7801 */ "MVE_VMLALDAVu32\0" + /* 7817 */ "MVE_VMINVu32\0" + /* 7830 */ "MVE_VMAXVu32\0" + /* 7843 */ "VPMAXu32\0" + /* 7852 */ "MVE_VMAXu32\0" + /* 7864 */ "MVE_VMLA_qr_u32\0" + /* 7880 */ "MVE_VHSUB_qr_u32\0" + /* 7897 */ "MVE_VQSUB_qr_u32\0" + /* 7914 */ "MVE_VHADD_qr_u32\0" + /* 7931 */ "MVE_VQADD_qr_u32\0" + /* 7948 */ "MVE_VMLAS_qr_u32\0" + /* 7965 */ "MVE_VRMLALDAVHau32\0" + /* 7984 */ "MVE_VMLADAVau32\0" + /* 8000 */ "MVE_VMLALDAVau32\0" + /* 8017 */ "MVE_VQSHL_by_vecu32\0" + /* 8037 */ "MVE_VQRSHL_by_vecu32\0" + /* 8058 */ "MVE_VRSHL_by_vecu32\0" + /* 8078 */ "MVE_VSHL_by_vecu32\0" + /* 8097 */ "MVE_VQSHRNbhu32\0" + /* 8113 */ "MVE_VQRSHRNbhu32\0" + /* 8130 */ "MVE_VQSHRNthu32\0" + /* 8146 */ "MVE_VQRSHRNthu32\0" + /* 8163 */ "MVE_VQSHLimmu32\0" + /* 8179 */ "MVE_VRSHR_immu32\0" + /* 8196 */ "MVE_VSHR_immu32\0" + /* 8212 */ "MVE_VQSHL_qru32\0" + /* 8228 */ "MVE_VQRSHL_qru32\0" + /* 8245 */ "MVE_VRSHL_qru32\0" + /* 8261 */ "MVE_VSHL_qru32\0" + /* 8276 */ "t2MRC2\0" + /* 8283 */ "t2MRRC2\0" + /* 8291 */ "G_FLOG2\0" + /* 8299 */ "SHA256H2\0" + /* 8308 */ "VTBL2\0" + /* 8314 */ "t2CDP2\0" + /* 8321 */ "G_FEXP2\0" + /* 8329 */ "t2MCR2\0" + /* 8336 */ "VMRS_MVFR2\0" + /* 8347 */ "t2MCRR2\0" + /* 8355 */ "t2DCPS2\0" + /* 8363 */ "VMSR_FPINST2\0" + /* 8376 */ "VMRS_FPINST2\0" + /* 8389 */ "VTBX2\0" + /* 8395 */ "CDE_CX2\0" + /* 8403 */ "VLD2DUPd32x2\0" + /* 8416 */ "VLD2DUPd16x2\0" + /* 8429 */ "VLD2DUPd8x2\0" + /* 8441 */ "VTBL3\0" + /* 8447 */ "t2DCPS3\0" + /* 8455 */ "VTBX3\0" + /* 8461 */ "CDE_CX3\0" + /* 8469 */ "tSUBi3\0" + /* 8476 */ "tADDi3\0" + /* 8483 */ "tSUBSi3\0" + /* 8491 */ "tADDSi3\0" + /* 8499 */ "MVE_VCTP64\0" + /* 8510 */ "CMP_SWAP_64\0" + /* 8522 */ "MVE_DLSTP_64\0" + /* 8535 */ "MVE_WLSTP_64\0" + /* 8548 */ "VLD1d64\0" + /* 8556 */ "VST1d64\0" + /* 8564 */ "VSUBv1i64\0" + /* 8574 */ "VADDv1i64\0" + /* 8584 */ "VSLIv1i64\0" + /* 8594 */ "VSRIv1i64\0" + /* 8604 */ "VMOVv1i64\0" + /* 8614 */ "VSHLiv1i64\0" + /* 8625 */ "VQSHLsiv1i64\0" + /* 8638 */ "VQSHLuiv1i64\0" + /* 8651 */ "VRSRAsv1i64\0" + /* 8663 */ "VSRAsv1i64\0" + /* 8674 */ "VQSUBsv1i64\0" + /* 8686 */ "VQADDsv1i64\0" + /* 8698 */ "VQSHLsv1i64\0" + /* 8710 */ "VQRSHLsv1i64\0" + /* 8723 */ "VRSHLsv1i64\0" + /* 8735 */ "VSHLsv1i64\0" + /* 8746 */ "VRSHRsv1i64\0" + /* 8758 */ "VSHRsv1i64\0" + /* 8769 */ "VRSRAuv1i64\0" + /* 8781 */ "VSRAuv1i64\0" + /* 8792 */ "VQSUBuv1i64\0" + /* 8804 */ "VQADDuv1i64\0" + /* 8816 */ "VQSHLuv1i64\0" + /* 8828 */ "VQRSHLuv1i64\0" + /* 8841 */ "VRSHLuv1i64\0" + /* 8853 */ "VSHLuv1i64\0" + /* 8864 */ "VRSHRuv1i64\0" + /* 8876 */ "VSHRuv1i64\0" + /* 8887 */ "VQSHLsuv1i64\0" + /* 8900 */ "VSUBv2i64\0" + /* 8910 */ "VADDv2i64\0" + /* 8920 */ "VSLIv2i64\0" + /* 8930 */ "VSRIv2i64\0" + /* 8940 */ "VQDMLALv2i64\0" + /* 8953 */ "VQDMULLv2i64\0" + /* 8966 */ "VQDMLSLv2i64\0" + /* 8979 */ "VMOVv2i64\0" + /* 8989 */ "VSHLiv2i64\0" + /* 9000 */ "VQSHLsiv2i64\0" + /* 9013 */ "VQSHLuiv2i64\0" + /* 9026 */ "VRSRAsv2i64\0" + /* 9038 */ "VSRAsv2i64\0" + /* 9049 */ "VQSUBsv2i64\0" + /* 9061 */ "VQADDsv2i64\0" + /* 9073 */ "VABALsv2i64\0" + /* 9085 */ "VMLALsv2i64\0" + /* 9097 */ "VSUBLsv2i64\0" + /* 9109 */ "VABDLsv2i64\0" + /* 9121 */ "VADDLsv2i64\0" + /* 9133 */ "VQSHLsv2i64\0" + /* 9145 */ "VQRSHLsv2i64\0" + /* 9158 */ "VRSHLsv2i64\0" + /* 9170 */ "VSHLsv2i64\0" + /* 9181 */ "VSHLLsv2i64\0" + /* 9193 */ "VMULLsv2i64\0" + /* 9205 */ "VMLSLsv2i64\0" + /* 9217 */ "VMOVLsv2i64\0" + /* 9229 */ "VRSHRsv2i64\0" + /* 9241 */ "VSHRsv2i64\0" + /* 9252 */ "VSUBWsv2i64\0" + /* 9264 */ "VADDWsv2i64\0" + /* 9276 */ "VRSRAuv2i64\0" + /* 9288 */ "VSRAuv2i64\0" + /* 9299 */ "VQSUBuv2i64\0" + /* 9311 */ "VQADDuv2i64\0" + /* 9323 */ "VABALuv2i64\0" + /* 9335 */ "VMLALuv2i64\0" + /* 9347 */ "VSUBLuv2i64\0" + /* 9359 */ "VABDLuv2i64\0" + /* 9371 */ "VADDLuv2i64\0" + /* 9383 */ "VQSHLuv2i64\0" + /* 9395 */ "VQRSHLuv2i64\0" + /* 9408 */ "VRSHLuv2i64\0" + /* 9420 */ "VSHLuv2i64\0" + /* 9431 */ "VSHLLuv2i64\0" + /* 9443 */ "VMULLuv2i64\0" + /* 9455 */ "VMLSLuv2i64\0" + /* 9467 */ "VMOVLuv2i64\0" + /* 9479 */ "VRSHRuv2i64\0" + /* 9491 */ "VSHRuv2i64\0" + /* 9502 */ "VSUBWuv2i64\0" + /* 9514 */ "VADDWuv2i64\0" + /* 9526 */ "VQSHLsuv2i64\0" + /* 9539 */ "BCCi64\0" + /* 9546 */ "BCCZi64\0" + /* 9554 */ "MVE_VMOVimmi64\0" + /* 9569 */ "VMULLp64\0" + /* 9578 */ "VLD1q64\0" + /* 9586 */ "VST1q64\0" + /* 9594 */ "VEXTq64\0" + /* 9602 */ "VTBL4\0" + /* 9608 */ "VTBX4\0" + /* 9614 */ "TAILJMPr4\0" + /* 9624 */ "MLAv5\0" + /* 9630 */ "SMLALv5\0" + /* 9638 */ "UMLALv5\0" + /* 9646 */ "SMULLv5\0" + /* 9654 */ "UMULLv5\0" + /* 9662 */ "MULv5\0" + /* 9668 */ "t2SXTAB16\0" + /* 9678 */ "t2UXTAB16\0" + /* 9688 */ "MVE_VSTRB16\0" + /* 9700 */ "t2SXTB16\0" + /* 9709 */ "t2UXTB16\0" + /* 9718 */ "t2SHSUB16\0" + /* 9728 */ "t2UHSUB16\0" + /* 9738 */ "t2QSUB16\0" + /* 9747 */ "t2UQSUB16\0" + /* 9757 */ "t2SSUB16\0" + /* 9766 */ "t2USUB16\0" + /* 9775 */ "t2SHADD16\0" + /* 9785 */ "t2UHADD16\0" + /* 9795 */ "t2QADD16\0" + /* 9804 */ "t2UQADD16\0" + /* 9814 */ "t2SADD16\0" + /* 9823 */ "t2UADD16\0" + /* 9832 */ "MVE_VCTP16\0" + /* 9843 */ "MVE_VDUP16\0" + /* 9854 */ "MVE_VBRSR16\0" + /* 9866 */ "MVE_VLDRBS16\0" + /* 9879 */ "t2SSAT16\0" + /* 9888 */ "t2USAT16\0" + /* 9897 */ "MVE_VLDRBU16\0" + /* 9910 */ "MVE_VLDRHU16\0" + /* 9923 */ "MVE_VSTRHU16\0" + /* 9936 */ "t2REV16\0" + /* 9944 */ "tREV16\0" + /* 9951 */ "MVE_VLD20_16\0" + /* 9964 */ "MVE_VST20_16\0" + /* 9977 */ "MVE_VLD40_16\0" + /* 9990 */ "MVE_VST40_16\0" + /* 10003 */ "MVE_VLD21_16\0" + /* 10016 */ "MVE_VST21_16\0" + /* 10029 */ "MVE_VLD41_16\0" + /* 10042 */ "MVE_VST41_16\0" + /* 10055 */ "MVE_VREV32_16\0" + /* 10069 */ "MVE_VLD42_16\0" + /* 10082 */ "MVE_VST42_16\0" + /* 10095 */ "MVE_VLD43_16\0" + /* 10108 */ "MVE_VST43_16\0" + /* 10121 */ "MVE_VREV64_16\0" + /* 10135 */ "tCMP_SWAP_16\0" + /* 10148 */ "MVE_DLSTP_16\0" + /* 10161 */ "MVE_WLSTP_16\0" + /* 10174 */ "MVE_VMOV_to_lane_16\0" + /* 10194 */ "VLD3dWB_fixed_Asm_16\0" + /* 10215 */ "VST3dWB_fixed_Asm_16\0" + /* 10236 */ "VLD4dWB_fixed_Asm_16\0" + /* 10257 */ "VST4dWB_fixed_Asm_16\0" + /* 10278 */ "VLD1LNdWB_fixed_Asm_16\0" + /* 10301 */ "VST1LNdWB_fixed_Asm_16\0" + /* 10324 */ "VLD2LNdWB_fixed_Asm_16\0" + /* 10347 */ "VST2LNdWB_fixed_Asm_16\0" + /* 10370 */ "VLD3LNdWB_fixed_Asm_16\0" + /* 10393 */ "VST3LNdWB_fixed_Asm_16\0" + /* 10416 */ "VLD4LNdWB_fixed_Asm_16\0" + /* 10439 */ "VST4LNdWB_fixed_Asm_16\0" + /* 10462 */ "VLD3DUPdWB_fixed_Asm_16\0" + /* 10486 */ "VLD4DUPdWB_fixed_Asm_16\0" + /* 10510 */ "VLD3qWB_fixed_Asm_16\0" + /* 10531 */ "VST3qWB_fixed_Asm_16\0" + /* 10552 */ "VLD4qWB_fixed_Asm_16\0" + /* 10573 */ "VST4qWB_fixed_Asm_16\0" + /* 10594 */ "VLD2LNqWB_fixed_Asm_16\0" + /* 10617 */ "VST2LNqWB_fixed_Asm_16\0" + /* 10640 */ "VLD3LNqWB_fixed_Asm_16\0" + /* 10663 */ "VST3LNqWB_fixed_Asm_16\0" + /* 10686 */ "VLD4LNqWB_fixed_Asm_16\0" + /* 10709 */ "VST4LNqWB_fixed_Asm_16\0" + /* 10732 */ "VLD3DUPqWB_fixed_Asm_16\0" + /* 10756 */ "VLD4DUPqWB_fixed_Asm_16\0" + /* 10780 */ "VLD3dWB_register_Asm_16\0" + /* 10804 */ "VST3dWB_register_Asm_16\0" + /* 10828 */ "VLD4dWB_register_Asm_16\0" + /* 10852 */ "VST4dWB_register_Asm_16\0" + /* 10876 */ "VLD1LNdWB_register_Asm_16\0" + /* 10902 */ "VST1LNdWB_register_Asm_16\0" + /* 10928 */ "VLD2LNdWB_register_Asm_16\0" + /* 10954 */ "VST2LNdWB_register_Asm_16\0" + /* 10980 */ "VLD3LNdWB_register_Asm_16\0" + /* 11006 */ "VST3LNdWB_register_Asm_16\0" + /* 11032 */ "VLD4LNdWB_register_Asm_16\0" + /* 11058 */ "VST4LNdWB_register_Asm_16\0" + /* 11084 */ "VLD3DUPdWB_register_Asm_16\0" + /* 11111 */ "VLD4DUPdWB_register_Asm_16\0" + /* 11138 */ "VLD3qWB_register_Asm_16\0" + /* 11162 */ "VST3qWB_register_Asm_16\0" + /* 11186 */ "VLD4qWB_register_Asm_16\0" + /* 11210 */ "VST4qWB_register_Asm_16\0" + /* 11234 */ "VLD2LNqWB_register_Asm_16\0" + /* 11260 */ "VST2LNqWB_register_Asm_16\0" + /* 11286 */ "VLD3LNqWB_register_Asm_16\0" + /* 11312 */ "VST3LNqWB_register_Asm_16\0" + /* 11338 */ "VLD4LNqWB_register_Asm_16\0" + /* 11364 */ "VST4LNqWB_register_Asm_16\0" + /* 11390 */ "VLD3DUPqWB_register_Asm_16\0" + /* 11417 */ "VLD4DUPqWB_register_Asm_16\0" + /* 11444 */ "VLD3dAsm_16\0" + /* 11456 */ "VST3dAsm_16\0" + /* 11468 */ "VLD4dAsm_16\0" + /* 11480 */ "VST4dAsm_16\0" + /* 11492 */ "VLD1LNdAsm_16\0" + /* 11506 */ "VST1LNdAsm_16\0" + /* 11520 */ "VLD2LNdAsm_16\0" + /* 11534 */ "VST2LNdAsm_16\0" + /* 11548 */ "VLD3LNdAsm_16\0" + /* 11562 */ "VST3LNdAsm_16\0" + /* 11576 */ "VLD4LNdAsm_16\0" + /* 11590 */ "VST4LNdAsm_16\0" + /* 11604 */ "VLD3DUPdAsm_16\0" + /* 11619 */ "VLD4DUPdAsm_16\0" + /* 11634 */ "VLD3qAsm_16\0" + /* 11646 */ "VST3qAsm_16\0" + /* 11658 */ "VLD4qAsm_16\0" + /* 11670 */ "VST4qAsm_16\0" + /* 11682 */ "VLD2LNqAsm_16\0" + /* 11696 */ "VST2LNqAsm_16\0" + /* 11710 */ "VLD3LNqAsm_16\0" + /* 11724 */ "VST3LNqAsm_16\0" + /* 11738 */ "VLD4LNqAsm_16\0" + /* 11752 */ "VST4LNqAsm_16\0" + /* 11766 */ "VLD3DUPqAsm_16\0" + /* 11781 */ "VLD4DUPqAsm_16\0" + /* 11796 */ "VLD2b16\0" + /* 11804 */ "VST2b16\0" + /* 11812 */ "VLD1d16\0" + /* 11820 */ "VST1d16\0" + /* 11828 */ "VREV32d16\0" + /* 11838 */ "VLD2d16\0" + /* 11846 */ "VST2d16\0" + /* 11854 */ "VLD3d16\0" + /* 11862 */ "VST3d16\0" + /* 11870 */ "VREV64d16\0" + /* 11880 */ "VLD4d16\0" + /* 11888 */ "VST4d16\0" + /* 11896 */ "VLD1LNd16\0" + /* 11906 */ "VST1LNd16\0" + /* 11916 */ "VLD2LNd16\0" + /* 11926 */ "VST2LNd16\0" + /* 11936 */ "VLD3LNd16\0" + /* 11946 */ "VST3LNd16\0" + /* 11956 */ "VLD4LNd16\0" + /* 11966 */ "VST4LNd16\0" + /* 11976 */ "VTRNd16\0" + /* 11984 */ "VZIPd16\0" + /* 11992 */ "VLD1DUPd16\0" + /* 12003 */ "VLD2DUPd16\0" + /* 12014 */ "VLD3DUPd16\0" + /* 12025 */ "VLD4DUPd16\0" + /* 12036 */ "VUZPd16\0" + /* 12044 */ "VEXTd16\0" + /* 12052 */ "VCMLAv4f16\0" + /* 12063 */ "VCADDv4f16\0" + /* 12074 */ "VCGEzv4f16\0" + /* 12085 */ "VCLEzv4f16\0" + /* 12096 */ "VCEQzv4f16\0" + /* 12107 */ "VCGTzv4f16\0" + /* 12118 */ "VCLTzv4f16\0" + /* 12129 */ "VCMLAv8f16\0" + /* 12140 */ "VCADDv8f16\0" + /* 12151 */ "MVE_VPTv8f16\0" + /* 12164 */ "VCGEzv8f16\0" + /* 12175 */ "VCLEzv8f16\0" + /* 12186 */ "VCEQzv8f16\0" + /* 12197 */ "VCGTzv8f16\0" + /* 12208 */ "VCLTzv8f16\0" + /* 12219 */ "MVE_VCMLAf16\0" + /* 12232 */ "MVE_VFMAf16\0" + /* 12244 */ "MVE_VMINNMAf16\0" + /* 12259 */ "MVE_VMAXNMAf16\0" + /* 12274 */ "MVE_VSUBf16\0" + /* 12286 */ "MVE_VABDf16\0" + /* 12298 */ "MVE_VCADDf16\0" + /* 12311 */ "MVE_VADDf16\0" + /* 12323 */ "MVE_VNEGf16\0" + /* 12335 */ "MVE_VCMULf16\0" + /* 12348 */ "MVE_VMULf16\0" + /* 12360 */ "MVE_VMINNMf16\0" + /* 12374 */ "MVE_VMAXNMf16\0" + /* 12388 */ "MVE_VCMPf16\0" + /* 12400 */ "MVE_VABSf16\0" + /* 12412 */ "MVE_VFMSf16\0" + /* 12424 */ "MVE_VFMA_qr_Sf16\0" + /* 12441 */ "MVE_VMINNMAVf16\0" + /* 12457 */ "MVE_VMAXNMAVf16\0" + /* 12473 */ "MVE_VMINNMVf16\0" + /* 12488 */ "MVE_VMAXNMVf16\0" + /* 12503 */ "MVE_VFMA_qr_f16\0" + /* 12519 */ "MVE_VSUB_qr_f16\0" + /* 12535 */ "MVE_VADD_qr_f16\0" + /* 12551 */ "MVE_VMUL_qr_f16\0" + /* 12567 */ "VMLAv4i16\0" + /* 12577 */ "VSUBv4i16\0" + /* 12587 */ "VADDv4i16\0" + /* 12597 */ "VQNEGv4i16\0" + /* 12608 */ "VQRDMLAHv4i16\0" + /* 12622 */ "VQDMULHv4i16\0" + /* 12635 */ "VQRDMULHv4i16\0" + /* 12649 */ "VQRDMLSHv4i16\0" + /* 12663 */ "VSLIv4i16\0" + /* 12673 */ "VSRIv4i16\0" + /* 12683 */ "VMULv4i16\0" + /* 12693 */ "VRSUBHNv4i16\0" + /* 12706 */ "VSUBHNv4i16\0" + /* 12718 */ "VRADDHNv4i16\0" + /* 12731 */ "VADDHNv4i16\0" + /* 12743 */ "VRSHRNv4i16\0" + /* 12755 */ "VSHRNv4i16\0" + /* 12766 */ "VQSHRUNv4i16\0" + /* 12779 */ "VQRSHRUNv4i16\0" + /* 12793 */ "VMVNv4i16\0" + /* 12803 */ "VMOVNv4i16\0" + /* 12814 */ "VCEQv4i16\0" + /* 12824 */ "VQABSv4i16\0" + /* 12835 */ "VABSv4i16\0" + /* 12845 */ "VCLSv4i16\0" + /* 12855 */ "VMLSv4i16\0" + /* 12865 */ "VTSTv4i16\0" + /* 12875 */ "VMOVv4i16\0" + /* 12885 */ "VCLZv4i16\0" + /* 12895 */ "VBICiv4i16\0" + /* 12906 */ "VSHLiv4i16\0" + /* 12917 */ "VORRiv4i16\0" + /* 12928 */ "VQSHLsiv4i16\0" + /* 12941 */ "VQSHLuiv4i16\0" + /* 12954 */ "VMLAslv4i16\0" + /* 12966 */ "VQRDMLAHslv4i16\0" + /* 12982 */ "VQDMULHslv4i16\0" + /* 12997 */ "VQRDMULHslv4i16\0" + /* 13013 */ "VQRDMLSHslv4i16\0" + /* 13029 */ "VQDMLALslv4i16\0" + /* 13044 */ "VQDMULLslv4i16\0" + /* 13059 */ "VQDMLSLslv4i16\0" + /* 13074 */ "VMULslv4i16\0" + /* 13086 */ "VMLSslv4i16\0" + /* 13098 */ "VABAsv4i16\0" + /* 13109 */ "VRSRAsv4i16\0" + /* 13121 */ "VSRAsv4i16\0" + /* 13132 */ "VHSUBsv4i16\0" + /* 13144 */ "VQSUBsv4i16\0" + /* 13156 */ "VABDsv4i16\0" + /* 13167 */ "VRHADDsv4i16\0" + /* 13180 */ "VHADDsv4i16\0" + /* 13192 */ "VQADDsv4i16\0" + /* 13204 */ "VCGEsv4i16\0" + /* 13215 */ "VPADALsv4i16\0" + /* 13228 */ "VPADDLsv4i16\0" + /* 13241 */ "VQSHLsv4i16\0" + /* 13253 */ "VQRSHLsv4i16\0" + /* 13266 */ "VRSHLsv4i16\0" + /* 13278 */ "VSHLsv4i16\0" + /* 13289 */ "VMINsv4i16\0" + /* 13300 */ "VQSHRNsv4i16\0" + /* 13313 */ "VQRSHRNsv4i16\0" + /* 13327 */ "VQMOVNsv4i16\0" + /* 13340 */ "VRSHRsv4i16\0" + /* 13352 */ "VSHRsv4i16\0" + /* 13363 */ "VCGTsv4i16\0" + /* 13374 */ "VMAXsv4i16\0" + /* 13385 */ "VMLALslsv4i16\0" + /* 13399 */ "VMULLslsv4i16\0" + /* 13413 */ "VMLSLslsv4i16\0" + /* 13427 */ "VABAuv4i16\0" + /* 13438 */ "VRSRAuv4i16\0" + /* 13450 */ "VSRAuv4i16\0" + /* 13461 */ "VHSUBuv4i16\0" + /* 13473 */ "VQSUBuv4i16\0" + /* 13485 */ "VABDuv4i16\0" + /* 13496 */ "VRHADDuv4i16\0" + /* 13509 */ "VHADDuv4i16\0" + /* 13521 */ "VQADDuv4i16\0" + /* 13533 */ "VCGEuv4i16\0" + /* 13544 */ "VPADALuv4i16\0" + /* 13557 */ "VPADDLuv4i16\0" + /* 13570 */ "VQSHLuv4i16\0" + /* 13582 */ "VQRSHLuv4i16\0" + /* 13595 */ "VRSHLuv4i16\0" + /* 13607 */ "VSHLuv4i16\0" + /* 13618 */ "VMINuv4i16\0" + /* 13629 */ "VQSHRNuv4i16\0" + /* 13642 */ "VQRSHRNuv4i16\0" + /* 13656 */ "VQMOVNuv4i16\0" + /* 13669 */ "VRSHRuv4i16\0" + /* 13681 */ "VSHRuv4i16\0" + /* 13692 */ "VCGTuv4i16\0" + /* 13703 */ "VMAXuv4i16\0" + /* 13714 */ "VMLALsluv4i16\0" + /* 13728 */ "VMULLsluv4i16\0" + /* 13742 */ "VMLSLsluv4i16\0" + /* 13756 */ "VQSHLsuv4i16\0" + /* 13769 */ "VQMOVNsuv4i16\0" + /* 13783 */ "VCGEzv4i16\0" + /* 13794 */ "VCLEzv4i16\0" + /* 13805 */ "VCEQzv4i16\0" + /* 13816 */ "VCGTzv4i16\0" + /* 13827 */ "VCLTzv4i16\0" + /* 13838 */ "VMLAv8i16\0" + /* 13848 */ "VSUBv8i16\0" + /* 13858 */ "VADDv8i16\0" + /* 13868 */ "VQNEGv8i16\0" + /* 13879 */ "VQRDMLAHv8i16\0" + /* 13893 */ "VQDMULHv8i16\0" + /* 13906 */ "VQRDMULHv8i16\0" + /* 13920 */ "VQRDMLSHv8i16\0" + /* 13934 */ "VSLIv8i16\0" + /* 13944 */ "VSRIv8i16\0" + /* 13954 */ "VMULv8i16\0" + /* 13964 */ "VMVNv8i16\0" + /* 13974 */ "VCEQv8i16\0" + /* 13984 */ "VQABSv8i16\0" + /* 13995 */ "VABSv8i16\0" + /* 14005 */ "VCLSv8i16\0" + /* 14015 */ "VMLSv8i16\0" + /* 14025 */ "MVE_VPTv8i16\0" + /* 14038 */ "VTSTv8i16\0" + /* 14048 */ "VMOVv8i16\0" + /* 14058 */ "VCLZv8i16\0" + /* 14068 */ "VBICiv8i16\0" + /* 14079 */ "VSHLiv8i16\0" + /* 14090 */ "VORRiv8i16\0" + /* 14101 */ "VQSHLsiv8i16\0" + /* 14114 */ "VQSHLuiv8i16\0" + /* 14127 */ "VMLAslv8i16\0" + /* 14139 */ "VQRDMLAHslv8i16\0" + /* 14155 */ "VQDMULHslv8i16\0" + /* 14170 */ "VQRDMULHslv8i16\0" + /* 14186 */ "VQRDMLSHslv8i16\0" + /* 14202 */ "VMULslv8i16\0" + /* 14214 */ "VMLSslv8i16\0" + /* 14226 */ "VABAsv8i16\0" + /* 14237 */ "VRSRAsv8i16\0" + /* 14249 */ "VSRAsv8i16\0" + /* 14260 */ "VHSUBsv8i16\0" + /* 14272 */ "VQSUBsv8i16\0" + /* 14284 */ "VABDsv8i16\0" + /* 14295 */ "VRHADDsv8i16\0" + /* 14308 */ "VHADDsv8i16\0" + /* 14320 */ "VQADDsv8i16\0" + /* 14332 */ "VCGEsv8i16\0" + /* 14343 */ "VABALsv8i16\0" + /* 14355 */ "VPADALsv8i16\0" + /* 14368 */ "VMLALsv8i16\0" + /* 14380 */ "VSUBLsv8i16\0" + /* 14392 */ "VABDLsv8i16\0" + /* 14404 */ "VPADDLsv8i16\0" + /* 14417 */ "VADDLsv8i16\0" + /* 14429 */ "VQSHLsv8i16\0" + /* 14441 */ "VQRSHLsv8i16\0" + /* 14454 */ "VRSHLsv8i16\0" + /* 14466 */ "VSHLsv8i16\0" + /* 14477 */ "VSHLLsv8i16\0" + /* 14489 */ "VMULLsv8i16\0" + /* 14501 */ "VMLSLsv8i16\0" + /* 14513 */ "VMOVLsv8i16\0" + /* 14525 */ "VMINsv8i16\0" + /* 14536 */ "VRSHRsv8i16\0" + /* 14548 */ "VSHRsv8i16\0" + /* 14559 */ "VCGTsv8i16\0" + /* 14570 */ "VSUBWsv8i16\0" + /* 14582 */ "VADDWsv8i16\0" + /* 14594 */ "VMAXsv8i16\0" + /* 14605 */ "VABAuv8i16\0" + /* 14616 */ "VRSRAuv8i16\0" + /* 14628 */ "VSRAuv8i16\0" + /* 14639 */ "VHSUBuv8i16\0" + /* 14651 */ "VQSUBuv8i16\0" + /* 14663 */ "VABDuv8i16\0" + /* 14674 */ "VRHADDuv8i16\0" + /* 14687 */ "VHADDuv8i16\0" + /* 14699 */ "VQADDuv8i16\0" + /* 14711 */ "VCGEuv8i16\0" + /* 14722 */ "VABALuv8i16\0" + /* 14734 */ "VPADALuv8i16\0" + /* 14747 */ "VMLALuv8i16\0" + /* 14759 */ "VSUBLuv8i16\0" + /* 14771 */ "VABDLuv8i16\0" + /* 14783 */ "VPADDLuv8i16\0" + /* 14796 */ "VADDLuv8i16\0" + /* 14808 */ "VQSHLuv8i16\0" + /* 14820 */ "VQRSHLuv8i16\0" + /* 14833 */ "VRSHLuv8i16\0" + /* 14845 */ "VSHLuv8i16\0" + /* 14856 */ "VSHLLuv8i16\0" + /* 14868 */ "VMULLuv8i16\0" + /* 14880 */ "VMLSLuv8i16\0" + /* 14892 */ "VMOVLuv8i16\0" + /* 14904 */ "VMINuv8i16\0" + /* 14915 */ "VRSHRuv8i16\0" + /* 14927 */ "VSHRuv8i16\0" + /* 14938 */ "VCGTuv8i16\0" + /* 14949 */ "VSUBWuv8i16\0" + /* 14961 */ "VADDWuv8i16\0" + /* 14973 */ "VMAXuv8i16\0" + /* 14984 */ "VQSHLsuv8i16\0" + /* 14997 */ "VCGEzv8i16\0" + /* 15008 */ "VCLEzv8i16\0" + /* 15019 */ "VCEQzv8i16\0" + /* 15030 */ "VCGTzv8i16\0" + /* 15041 */ "VCLTzv8i16\0" + /* 15052 */ "MVE_VSUBi16\0" + /* 15064 */ "t2MOVCCi16\0" + /* 15075 */ "MVE_VCADDi16\0" + /* 15088 */ "VPADDi16\0" + /* 15097 */ "MVE_VADDi16\0" + /* 15109 */ "MVE_VQDMULHi16\0" + /* 15124 */ "MVE_VQRDMULHi16\0" + /* 15140 */ "VSHLLi16\0" + /* 15149 */ "MVE_VMULi16\0" + /* 15161 */ "VSETLNi16\0" + /* 15171 */ "MVE_VCMPi16\0" + /* 15183 */ "t2MOVTi16\0" + /* 15193 */ "t2MOVi16\0" + /* 15202 */ "MVE_VSUB_qr_i16\0" + /* 15218 */ "MVE_VADD_qr_i16\0" + /* 15234 */ "MVE_VMUL_qr_i16\0" + /* 15250 */ "MVE_VBICimmi16\0" + /* 15265 */ "MVE_VMVNimmi16\0" + /* 15280 */ "MVE_VORRimmi16\0" + /* 15295 */ "MVE_VMOVimmi16\0" + /* 15310 */ "MVE_VSHL_immi16\0" + /* 15326 */ "MVE_VSLIimm16\0" + /* 15340 */ "MVE_VSRIimm16\0" + /* 15354 */ "MVE_VMULLBp16\0" + /* 15368 */ "MVE_VMULLTp16\0" + /* 15382 */ "VLD1q16\0" + /* 15390 */ "VST1q16\0" + /* 15398 */ "VREV32q16\0" + /* 15408 */ "VLD2q16\0" + /* 15416 */ "VST2q16\0" + /* 15424 */ "VLD3q16\0" + /* 15432 */ "VST3q16\0" + /* 15440 */ "VREV64q16\0" + /* 15450 */ "VLD4q16\0" + /* 15458 */ "VST4q16\0" + /* 15466 */ "VLD2LNq16\0" + /* 15476 */ "VST2LNq16\0" + /* 15486 */ "VLD3LNq16\0" + /* 15496 */ "VST3LNq16\0" + /* 15506 */ "VLD4LNq16\0" + /* 15516 */ "VST4LNq16\0" + /* 15526 */ "VTRNq16\0" + /* 15534 */ "VZIPq16\0" + /* 15542 */ "VLD1DUPq16\0" + /* 15553 */ "VLD3DUPq16\0" + /* 15564 */ "VLD4DUPq16\0" + /* 15575 */ "VUZPq16\0" + /* 15583 */ "VEXTq16\0" + /* 15591 */ "MVE_VPTv8s16\0" + /* 15604 */ "MVE_VMINAs16\0" + /* 15617 */ "MVE_VMAXAs16\0" + /* 15630 */ "MVE_VMULLBs16\0" + /* 15644 */ "MVE_VHSUBs16\0" + /* 15657 */ "MVE_VQSUBs16\0" + /* 15670 */ "MVE_VABDs16\0" + /* 15682 */ "MVE_VHCADDs16\0" + /* 15696 */ "MVE_VRHADDs16\0" + /* 15710 */ "MVE_VHADDs16\0" + /* 15723 */ "MVE_VQADDs16\0" + /* 15736 */ "MVE_VQNEGs16\0" + /* 15749 */ "MVE_VNEGs16\0" + /* 15761 */ "MVE_VQDMLADHs16\0" + /* 15777 */ "MVE_VQRDMLADHs16\0" + /* 15794 */ "MVE_VQDMLSDHs16\0" + /* 15810 */ "MVE_VQRDMLSDHs16\0" + /* 15827 */ "MVE_VRMULHs16\0" + /* 15841 */ "MVE_VMULHs16\0" + /* 15854 */ "VPMINs16\0" + /* 15863 */ "MVE_VMINs16\0" + /* 15875 */ "VGETLNs16\0" + /* 15885 */ "MVE_VCMPs16\0" + /* 15897 */ "MVE_VQABSs16\0" + /* 15910 */ "MVE_VABSs16\0" + /* 15922 */ "MVE_VCLSs16\0" + /* 15934 */ "MVE_VMULLTs16\0" + /* 15948 */ "MVE_VABAVs16\0" + /* 15961 */ "MVE_VMLADAVs16\0" + /* 15976 */ "MVE_VMLALDAVs16\0" + /* 15992 */ "MVE_VMLSLDAVs16\0" + /* 16008 */ "MVE_VMLSDAVs16\0" + /* 16023 */ "MVE_VMINAVs16\0" + /* 16037 */ "MVE_VMAXAVs16\0" + /* 16051 */ "MVE_VMINVs16\0" + /* 16064 */ "MVE_VMAXVs16\0" + /* 16077 */ "VPMAXs16\0" + /* 16086 */ "MVE_VMAXs16\0" + /* 16098 */ "MVE_VQDMLADHXs16\0" + /* 16115 */ "MVE_VQRDMLADHXs16\0" + /* 16133 */ "MVE_VQDMLSDHXs16\0" + /* 16150 */ "MVE_VQRDMLSDHXs16\0" + /* 16168 */ "MVE_VCLZs16\0" + /* 16180 */ "MVE_VMOV_from_lane_s16\0" + /* 16203 */ "MVE_VMLA_qr_s16\0" + /* 16219 */ "MVE_VHSUB_qr_s16\0" + /* 16236 */ "MVE_VQSUB_qr_s16\0" + /* 16253 */ "MVE_VHADD_qr_s16\0" + /* 16270 */ "MVE_VQADD_qr_s16\0" + /* 16287 */ "MVE_VQDMULH_qr_s16\0" + /* 16306 */ "MVE_VQRDMULH_qr_s16\0" + /* 16326 */ "MVE_VMLAS_qr_s16\0" + /* 16343 */ "MVE_VMLADAVas16\0" + /* 16359 */ "MVE_VMLALDAVas16\0" + /* 16376 */ "MVE_VMLSLDAVas16\0" + /* 16393 */ "MVE_VMLSDAVas16\0" + /* 16409 */ "MVE_VQSHL_by_vecs16\0" + /* 16429 */ "MVE_VQRSHL_by_vecs16\0" + /* 16450 */ "MVE_VRSHL_by_vecs16\0" + /* 16470 */ "MVE_VSHL_by_vecs16\0" + /* 16489 */ "MVE_VQSHRNbhs16\0" + /* 16505 */ "MVE_VQRSHRNbhs16\0" + /* 16522 */ "MVE_VQSHRNths16\0" + /* 16538 */ "MVE_VQRSHRNths16\0" + /* 16555 */ "MVE_VQSHLimms16\0" + /* 16571 */ "MVE_VRSHR_imms16\0" + /* 16588 */ "MVE_VSHR_imms16\0" + /* 16604 */ "MVE_VQSHLU_imms16\0" + /* 16622 */ "MVE_VQDMLAH_qrs16\0" + /* 16640 */ "MVE_VQRDMLAH_qrs16\0" + /* 16659 */ "MVE_VQDMLASH_qrs16\0" + /* 16678 */ "MVE_VQRDMLASH_qrs16\0" + /* 16698 */ "MVE_VQSHL_qrs16\0" + /* 16714 */ "MVE_VQRSHL_qrs16\0" + /* 16731 */ "MVE_VRSHL_qrs16\0" + /* 16747 */ "MVE_VSHL_qrs16\0" + /* 16762 */ "MVE_VMLADAVxs16\0" + /* 16778 */ "MVE_VMLALDAVxs16\0" + /* 16795 */ "MVE_VMLSLDAVxs16\0" + /* 16812 */ "MVE_VMLSDAVxs16\0" + /* 16828 */ "MVE_VMLADAVaxs16\0" + /* 16845 */ "MVE_VMLALDAVaxs16\0" + /* 16863 */ "MVE_VMLSLDAVaxs16\0" + /* 16881 */ "MVE_VMLSDAVaxs16\0" + /* 16898 */ "MVE_VPTv8u16\0" + /* 16911 */ "MVE_VMULLBu16\0" + /* 16925 */ "MVE_VHSUBu16\0" + /* 16938 */ "MVE_VQSUBu16\0" + /* 16951 */ "MVE_VABDu16\0" + /* 16963 */ "MVE_VRHADDu16\0" + /* 16977 */ "MVE_VHADDu16\0" + /* 16990 */ "MVE_VQADDu16\0" + /* 17003 */ "MVE_VRMULHu16\0" + /* 17017 */ "MVE_VMULHu16\0" + /* 17030 */ "VPMINu16\0" + /* 17039 */ "MVE_VMINu16\0" + /* 17051 */ "VGETLNu16\0" + /* 17061 */ "MVE_VCMPu16\0" + /* 17073 */ "MVE_VDDUPu16\0" + /* 17086 */ "MVE_VIDUPu16\0" + /* 17099 */ "MVE_VDWDUPu16\0" + /* 17113 */ "MVE_VIWDUPu16\0" + /* 17127 */ "MVE_VMULLTu16\0" + /* 17141 */ "MVE_VABAVu16\0" + /* 17154 */ "MVE_VMLADAVu16\0" + /* 17169 */ "MVE_VMLALDAVu16\0" + /* 17185 */ "MVE_VMINVu16\0" + /* 17198 */ "MVE_VMAXVu16\0" + /* 17211 */ "VPMAXu16\0" + /* 17220 */ "MVE_VMAXu16\0" + /* 17232 */ "MVE_VMOV_from_lane_u16\0" + /* 17255 */ "MVE_VMLA_qr_u16\0" + /* 17271 */ "MVE_VHSUB_qr_u16\0" + /* 17288 */ "MVE_VQSUB_qr_u16\0" + /* 17305 */ "MVE_VHADD_qr_u16\0" + /* 17322 */ "MVE_VQADD_qr_u16\0" + /* 17339 */ "MVE_VMLAS_qr_u16\0" + /* 17356 */ "MVE_VMLADAVau16\0" + /* 17372 */ "MVE_VMLALDAVau16\0" + /* 17389 */ "MVE_VQSHL_by_vecu16\0" + /* 17409 */ "MVE_VQRSHL_by_vecu16\0" + /* 17430 */ "MVE_VRSHL_by_vecu16\0" + /* 17450 */ "MVE_VSHL_by_vecu16\0" + /* 17469 */ "MVE_VQSHRNbhu16\0" + /* 17485 */ "MVE_VQRSHRNbhu16\0" + /* 17502 */ "MVE_VQSHRNthu16\0" + /* 17518 */ "MVE_VQRSHRNthu16\0" + /* 17535 */ "MVE_VQSHLimmu16\0" + /* 17551 */ "MVE_VRSHR_immu16\0" + /* 17568 */ "MVE_VSHR_immu16\0" + /* 17584 */ "MVE_VQSHL_qru16\0" + /* 17600 */ "MVE_VQRSHL_qru16\0" + /* 17617 */ "MVE_VRSHL_qru16\0" + /* 17633 */ "MVE_VSHL_qru16\0" + /* 17648 */ "t2USADA8\0" + /* 17657 */ "t2SHSUB8\0" + /* 17666 */ "t2UHSUB8\0" + /* 17675 */ "t2QSUB8\0" + /* 17683 */ "t2UQSUB8\0" + /* 17692 */ "t2SSUB8\0" + /* 17700 */ "t2USUB8\0" + /* 17708 */ "t2USAD8\0" + /* 17716 */ "t2SHADD8\0" + /* 17725 */ "t2UHADD8\0" + /* 17734 */ "t2QADD8\0" + /* 17742 */ "t2UQADD8\0" + /* 17751 */ "t2SADD8\0" + /* 17759 */ "t2UADD8\0" + /* 17767 */ "MVE_VCTP8\0" + /* 17777 */ "MVE_VDUP8\0" + /* 17787 */ "MVE_VBRSR8\0" + /* 17798 */ "MVE_VLDRBU8\0" + /* 17810 */ "MVE_VSTRBU8\0" + /* 17822 */ "MVE_VLD20_8\0" + /* 17834 */ "MVE_VST20_8\0" + /* 17846 */ "MVE_VLD40_8\0" + /* 17858 */ "MVE_VST40_8\0" + /* 17870 */ "MVE_VLD21_8\0" + /* 17882 */ "MVE_VST21_8\0" + /* 17894 */ "MVE_VLD41_8\0" + /* 17906 */ "MVE_VST41_8\0" + /* 17918 */ "MVE_VREV32_8\0" + /* 17931 */ "MVE_VLD42_8\0" + /* 17943 */ "MVE_VST42_8\0" + /* 17955 */ "MVE_VLD43_8\0" + /* 17967 */ "MVE_VST43_8\0" + /* 17979 */ "MVE_VREV64_8\0" + /* 17992 */ "MVE_VREV16_8\0" + /* 18005 */ "tCMP_SWAP_8\0" + /* 18017 */ "MVE_DLSTP_8\0" + /* 18029 */ "MVE_WLSTP_8\0" + /* 18041 */ "MVE_VMOV_to_lane_8\0" + /* 18060 */ "VLD3dWB_fixed_Asm_8\0" + /* 18080 */ "VST3dWB_fixed_Asm_8\0" + /* 18100 */ "VLD4dWB_fixed_Asm_8\0" + /* 18120 */ "VST4dWB_fixed_Asm_8\0" + /* 18140 */ "VLD1LNdWB_fixed_Asm_8\0" + /* 18162 */ "VST1LNdWB_fixed_Asm_8\0" + /* 18184 */ "VLD2LNdWB_fixed_Asm_8\0" + /* 18206 */ "VST2LNdWB_fixed_Asm_8\0" + /* 18228 */ "VLD3LNdWB_fixed_Asm_8\0" + /* 18250 */ "VST3LNdWB_fixed_Asm_8\0" + /* 18272 */ "VLD4LNdWB_fixed_Asm_8\0" + /* 18294 */ "VST4LNdWB_fixed_Asm_8\0" + /* 18316 */ "VLD3DUPdWB_fixed_Asm_8\0" + /* 18339 */ "VLD4DUPdWB_fixed_Asm_8\0" + /* 18362 */ "VLD3qWB_fixed_Asm_8\0" + /* 18382 */ "VST3qWB_fixed_Asm_8\0" + /* 18402 */ "VLD4qWB_fixed_Asm_8\0" + /* 18422 */ "VST4qWB_fixed_Asm_8\0" + /* 18442 */ "VLD3DUPqWB_fixed_Asm_8\0" + /* 18465 */ "VLD4DUPqWB_fixed_Asm_8\0" + /* 18488 */ "VLD3dWB_register_Asm_8\0" + /* 18511 */ "VST3dWB_register_Asm_8\0" + /* 18534 */ "VLD4dWB_register_Asm_8\0" + /* 18557 */ "VST4dWB_register_Asm_8\0" + /* 18580 */ "VLD1LNdWB_register_Asm_8\0" + /* 18605 */ "VST1LNdWB_register_Asm_8\0" + /* 18630 */ "VLD2LNdWB_register_Asm_8\0" + /* 18655 */ "VST2LNdWB_register_Asm_8\0" + /* 18680 */ "VLD3LNdWB_register_Asm_8\0" + /* 18705 */ "VST3LNdWB_register_Asm_8\0" + /* 18730 */ "VLD4LNdWB_register_Asm_8\0" + /* 18755 */ "VST4LNdWB_register_Asm_8\0" + /* 18780 */ "VLD3DUPdWB_register_Asm_8\0" + /* 18806 */ "VLD4DUPdWB_register_Asm_8\0" + /* 18832 */ "VLD3qWB_register_Asm_8\0" + /* 18855 */ "VST3qWB_register_Asm_8\0" + /* 18878 */ "VLD4qWB_register_Asm_8\0" + /* 18901 */ "VST4qWB_register_Asm_8\0" + /* 18924 */ "VLD3DUPqWB_register_Asm_8\0" + /* 18950 */ "VLD4DUPqWB_register_Asm_8\0" + /* 18976 */ "VLD3dAsm_8\0" + /* 18987 */ "VST3dAsm_8\0" + /* 18998 */ "VLD4dAsm_8\0" + /* 19009 */ "VST4dAsm_8\0" + /* 19020 */ "VLD1LNdAsm_8\0" + /* 19033 */ "VST1LNdAsm_8\0" + /* 19046 */ "VLD2LNdAsm_8\0" + /* 19059 */ "VST2LNdAsm_8\0" + /* 19072 */ "VLD3LNdAsm_8\0" + /* 19085 */ "VST3LNdAsm_8\0" + /* 19098 */ "VLD4LNdAsm_8\0" + /* 19111 */ "VST4LNdAsm_8\0" + /* 19124 */ "VLD3DUPdAsm_8\0" + /* 19138 */ "VLD4DUPdAsm_8\0" + /* 19152 */ "VLD3qAsm_8\0" + /* 19163 */ "VST3qAsm_8\0" + /* 19174 */ "VLD4qAsm_8\0" + /* 19185 */ "VST4qAsm_8\0" + /* 19196 */ "VLD3DUPqAsm_8\0" + /* 19210 */ "VLD4DUPqAsm_8\0" + /* 19224 */ "VLD2b8\0" + /* 19231 */ "VST2b8\0" + /* 19238 */ "VLD1d8\0" + /* 19245 */ "VST1d8\0" + /* 19252 */ "VREV32d8\0" + /* 19261 */ "VLD2d8\0" + /* 19268 */ "VST2d8\0" + /* 19275 */ "VLD3d8\0" + /* 19282 */ "VST3d8\0" + /* 19289 */ "VREV64d8\0" + /* 19298 */ "VLD4d8\0" + /* 19305 */ "VST4d8\0" + /* 19312 */ "VREV16d8\0" + /* 19321 */ "VLD1LNd8\0" + /* 19330 */ "VST1LNd8\0" + /* 19339 */ "VLD2LNd8\0" + /* 19348 */ "VST2LNd8\0" + /* 19357 */ "VLD3LNd8\0" + /* 19366 */ "VST3LNd8\0" + /* 19375 */ "VLD4LNd8\0" + /* 19384 */ "VST4LNd8\0" + /* 19393 */ "VTRNd8\0" + /* 19400 */ "VZIPd8\0" + /* 19407 */ "VLD1DUPd8\0" + /* 19417 */ "VLD2DUPd8\0" + /* 19427 */ "VLD3DUPd8\0" + /* 19437 */ "VLD4DUPd8\0" + /* 19447 */ "VUZPd8\0" + /* 19454 */ "VEXTd8\0" + /* 19461 */ "VMLAv16i8\0" + /* 19471 */ "VSUBv16i8\0" + /* 19481 */ "VADDv16i8\0" + /* 19491 */ "VQNEGv16i8\0" + /* 19502 */ "VSLIv16i8\0" + /* 19512 */ "VSRIv16i8\0" + /* 19522 */ "VMULv16i8\0" + /* 19532 */ "VCEQv16i8\0" + /* 19542 */ "VQABSv16i8\0" + /* 19553 */ "VABSv16i8\0" + /* 19563 */ "VCLSv16i8\0" + /* 19573 */ "VMLSv16i8\0" + /* 19583 */ "MVE_VPTv16i8\0" + /* 19596 */ "VTSTv16i8\0" + /* 19606 */ "VMOVv16i8\0" + /* 19616 */ "VCLZv16i8\0" + /* 19626 */ "VSHLiv16i8\0" + /* 19637 */ "VQSHLsiv16i8\0" + /* 19650 */ "VQSHLuiv16i8\0" + /* 19663 */ "VABAsv16i8\0" + /* 19674 */ "VRSRAsv16i8\0" + /* 19686 */ "VSRAsv16i8\0" + /* 19697 */ "VHSUBsv16i8\0" + /* 19709 */ "VQSUBsv16i8\0" + /* 19721 */ "VABDsv16i8\0" + /* 19732 */ "VRHADDsv16i8\0" + /* 19745 */ "VHADDsv16i8\0" + /* 19757 */ "VQADDsv16i8\0" + /* 19769 */ "VCGEsv16i8\0" + /* 19780 */ "VPADALsv16i8\0" + /* 19793 */ "VPADDLsv16i8\0" + /* 19806 */ "VQSHLsv16i8\0" + /* 19818 */ "VQRSHLsv16i8\0" + /* 19831 */ "VRSHLsv16i8\0" + /* 19843 */ "VSHLsv16i8\0" + /* 19854 */ "VMINsv16i8\0" + /* 19865 */ "VRSHRsv16i8\0" + /* 19877 */ "VSHRsv16i8\0" + /* 19888 */ "VCGTsv16i8\0" + /* 19899 */ "VMAXsv16i8\0" + /* 19910 */ "VABAuv16i8\0" + /* 19921 */ "VRSRAuv16i8\0" + /* 19933 */ "VSRAuv16i8\0" + /* 19944 */ "VHSUBuv16i8\0" + /* 19956 */ "VQSUBuv16i8\0" + /* 19968 */ "VABDuv16i8\0" + /* 19979 */ "VRHADDuv16i8\0" + /* 19992 */ "VHADDuv16i8\0" + /* 20004 */ "VQADDuv16i8\0" + /* 20016 */ "VCGEuv16i8\0" + /* 20027 */ "VPADALuv16i8\0" + /* 20040 */ "VPADDLuv16i8\0" + /* 20053 */ "VQSHLuv16i8\0" + /* 20065 */ "VQRSHLuv16i8\0" + /* 20078 */ "VRSHLuv16i8\0" + /* 20090 */ "VSHLuv16i8\0" + /* 20101 */ "VMINuv16i8\0" + /* 20112 */ "VRSHRuv16i8\0" + /* 20124 */ "VSHRuv16i8\0" + /* 20135 */ "VCGTuv16i8\0" + /* 20146 */ "VMAXuv16i8\0" + /* 20157 */ "VQSHLsuv16i8\0" + /* 20170 */ "VCGEzv16i8\0" + /* 20181 */ "VCLEzv16i8\0" + /* 20192 */ "VCEQzv16i8\0" + /* 20203 */ "VCGTzv16i8\0" + /* 20214 */ "VCLTzv16i8\0" + /* 20225 */ "VMLAv8i8\0" + /* 20234 */ "VSUBv8i8\0" + /* 20243 */ "VADDv8i8\0" + /* 20252 */ "VQNEGv8i8\0" + /* 20262 */ "VSLIv8i8\0" + /* 20271 */ "VSRIv8i8\0" + /* 20280 */ "VMULv8i8\0" + /* 20289 */ "VRSUBHNv8i8\0" + /* 20301 */ "VSUBHNv8i8\0" + /* 20312 */ "VRADDHNv8i8\0" + /* 20324 */ "VADDHNv8i8\0" + /* 20335 */ "VRSHRNv8i8\0" + /* 20346 */ "VSHRNv8i8\0" + /* 20356 */ "VQSHRUNv8i8\0" + /* 20368 */ "VQRSHRUNv8i8\0" + /* 20381 */ "VMOVNv8i8\0" + /* 20391 */ "VCEQv8i8\0" + /* 20400 */ "VQABSv8i8\0" + /* 20410 */ "VABSv8i8\0" + /* 20419 */ "VCLSv8i8\0" + /* 20428 */ "VMLSv8i8\0" + /* 20437 */ "VTSTv8i8\0" + /* 20446 */ "VMOVv8i8\0" + /* 20455 */ "VCLZv8i8\0" + /* 20464 */ "VSHLiv8i8\0" + /* 20474 */ "VQSHLsiv8i8\0" + /* 20486 */ "VQSHLuiv8i8\0" + /* 20498 */ "VABAsv8i8\0" + /* 20508 */ "VRSRAsv8i8\0" + /* 20519 */ "VSRAsv8i8\0" + /* 20529 */ "VHSUBsv8i8\0" + /* 20540 */ "VQSUBsv8i8\0" + /* 20551 */ "VABDsv8i8\0" + /* 20561 */ "VRHADDsv8i8\0" + /* 20573 */ "VHADDsv8i8\0" + /* 20584 */ "VQADDsv8i8\0" + /* 20595 */ "VCGEsv8i8\0" + /* 20605 */ "VPADALsv8i8\0" + /* 20617 */ "VPADDLsv8i8\0" + /* 20629 */ "VQSHLsv8i8\0" + /* 20640 */ "VQRSHLsv8i8\0" + /* 20652 */ "VRSHLsv8i8\0" + /* 20663 */ "VSHLsv8i8\0" + /* 20673 */ "VMINsv8i8\0" + /* 20683 */ "VQSHRNsv8i8\0" + /* 20695 */ "VQRSHRNsv8i8\0" + /* 20708 */ "VQMOVNsv8i8\0" + /* 20720 */ "VRSHRsv8i8\0" + /* 20731 */ "VSHRsv8i8\0" + /* 20741 */ "VCGTsv8i8\0" + /* 20751 */ "VMAXsv8i8\0" + /* 20761 */ "VABAuv8i8\0" + /* 20771 */ "VRSRAuv8i8\0" + /* 20782 */ "VSRAuv8i8\0" + /* 20792 */ "VHSUBuv8i8\0" + /* 20803 */ "VQSUBuv8i8\0" + /* 20814 */ "VABDuv8i8\0" + /* 20824 */ "VRHADDuv8i8\0" + /* 20836 */ "VHADDuv8i8\0" + /* 20847 */ "VQADDuv8i8\0" + /* 20858 */ "VCGEuv8i8\0" + /* 20868 */ "VPADALuv8i8\0" + /* 20880 */ "VPADDLuv8i8\0" + /* 20892 */ "VQSHLuv8i8\0" + /* 20903 */ "VQRSHLuv8i8\0" + /* 20915 */ "VRSHLuv8i8\0" + /* 20926 */ "VSHLuv8i8\0" + /* 20936 */ "VMINuv8i8\0" + /* 20946 */ "VQSHRNuv8i8\0" + /* 20958 */ "VQRSHRNuv8i8\0" + /* 20971 */ "VQMOVNuv8i8\0" + /* 20983 */ "VRSHRuv8i8\0" + /* 20994 */ "VSHRuv8i8\0" + /* 21004 */ "VCGTuv8i8\0" + /* 21014 */ "VMAXuv8i8\0" + /* 21024 */ "VQSHLsuv8i8\0" + /* 21036 */ "VQMOVNsuv8i8\0" + /* 21049 */ "VCGEzv8i8\0" + /* 21059 */ "VCLEzv8i8\0" + /* 21069 */ "VCEQzv8i8\0" + /* 21079 */ "VCGTzv8i8\0" + /* 21089 */ "VCLTzv8i8\0" + /* 21099 */ "t2LDRBi8\0" + /* 21108 */ "t2STRBi8\0" + /* 21117 */ "t2LDRSBi8\0" + /* 21127 */ "MVE_VSUBi8\0" + /* 21138 */ "tSUBi8\0" + /* 21145 */ "MVE_VCADDi8\0" + /* 21157 */ "VPADDi8\0" + /* 21165 */ "MVE_VADDi8\0" + /* 21176 */ "tADDi8\0" + /* 21183 */ "t2PLDi8\0" + /* 21191 */ "t2LDRDi8\0" + /* 21200 */ "t2STRDi8\0" + /* 21209 */ "MVE_VQDMULHi8\0" + /* 21223 */ "MVE_VQRDMULHi8\0" + /* 21238 */ "t2LDRHi8\0" + /* 21247 */ "t2STRHi8\0" + /* 21256 */ "t2LDRSHi8\0" + /* 21266 */ "t2PLIi8\0" + /* 21274 */ "VSHLLi8\0" + /* 21282 */ "MVE_VMULi8\0" + /* 21293 */ "VSETLNi8\0" + /* 21302 */ "MVE_VCMPi8\0" + /* 21313 */ "tCMPi8\0" + /* 21320 */ "t2LDRi8\0" + /* 21328 */ "t2STRi8\0" + /* 21336 */ "tSUBSi8\0" + /* 21344 */ "tADDSi8\0" + /* 21352 */ "tMOVi8\0" + /* 21359 */ "t2PLDWi8\0" + /* 21368 */ "MVE_VSUB_qr_i8\0" + /* 21383 */ "MVE_VADD_qr_i8\0" + /* 21398 */ "MVE_VMUL_qr_i8\0" + /* 21413 */ "MVE_VMOVimmi8\0" + /* 21427 */ "MVE_VSHL_immi8\0" + /* 21442 */ "MVE_VSLIimm8\0" + /* 21455 */ "MVE_VSRIimm8\0" + /* 21468 */ "MVE_VMULLBp8\0" + /* 21481 */ "VMULLp8\0" + /* 21489 */ "MVE_VMULLTp8\0" + /* 21502 */ "VLD1q8\0" + /* 21509 */ "VST1q8\0" + /* 21516 */ "VREV32q8\0" + /* 21525 */ "VLD2q8\0" + /* 21532 */ "VST2q8\0" + /* 21539 */ "VLD3q8\0" + /* 21546 */ "VST3q8\0" + /* 21553 */ "VREV64q8\0" + /* 21562 */ "VLD4q8\0" + /* 21569 */ "VST4q8\0" + /* 21576 */ "VREV16q8\0" + /* 21585 */ "VTRNq8\0" + /* 21592 */ "VZIPq8\0" + /* 21599 */ "VLD1DUPq8\0" + /* 21609 */ "VLD3DUPq8\0" + /* 21619 */ "VLD4DUPq8\0" + /* 21629 */ "VUZPq8\0" + /* 21636 */ "VEXTq8\0" + /* 21643 */ "MVE_VPTv16s8\0" + /* 21656 */ "MVE_VMINAs8\0" + /* 21668 */ "MVE_VMAXAs8\0" + /* 21680 */ "MVE_VMULLBs8\0" + /* 21693 */ "MVE_VHSUBs8\0" + /* 21705 */ "MVE_VQSUBs8\0" + /* 21717 */ "MVE_VABDs8\0" + /* 21728 */ "MVE_VHCADDs8\0" + /* 21741 */ "MVE_VRHADDs8\0" + /* 21754 */ "MVE_VHADDs8\0" + /* 21766 */ "MVE_VQADDs8\0" + /* 21778 */ "MVE_VQNEGs8\0" + /* 21790 */ "MVE_VNEGs8\0" + /* 21801 */ "MVE_VQDMLADHs8\0" + /* 21816 */ "MVE_VQRDMLADHs8\0" + /* 21832 */ "MVE_VQDMLSDHs8\0" + /* 21847 */ "MVE_VQRDMLSDHs8\0" + /* 21863 */ "MVE_VRMULHs8\0" + /* 21876 */ "MVE_VMULHs8\0" + /* 21888 */ "VPMINs8\0" + /* 21896 */ "MVE_VMINs8\0" + /* 21907 */ "VGETLNs8\0" + /* 21916 */ "MVE_VCMPs8\0" + /* 21927 */ "MVE_VQABSs8\0" + /* 21939 */ "MVE_VABSs8\0" + /* 21950 */ "MVE_VCLSs8\0" + /* 21961 */ "MVE_VMULLTs8\0" + /* 21974 */ "MVE_VABAVs8\0" + /* 21986 */ "MVE_VMLADAVs8\0" + /* 22000 */ "MVE_VMLSDAVs8\0" + /* 22014 */ "MVE_VMINAVs8\0" + /* 22027 */ "MVE_VMAXAVs8\0" + /* 22040 */ "MVE_VMINVs8\0" + /* 22052 */ "MVE_VMAXVs8\0" + /* 22064 */ "VPMAXs8\0" + /* 22072 */ "MVE_VMAXs8\0" + /* 22083 */ "MVE_VQDMLADHXs8\0" + /* 22099 */ "MVE_VQRDMLADHXs8\0" + /* 22116 */ "MVE_VQDMLSDHXs8\0" + /* 22132 */ "MVE_VQRDMLSDHXs8\0" + /* 22149 */ "MVE_VCLZs8\0" + /* 22160 */ "MVE_VMOV_from_lane_s8\0" + /* 22182 */ "MVE_VMLA_qr_s8\0" + /* 22197 */ "MVE_VHSUB_qr_s8\0" + /* 22213 */ "MVE_VQSUB_qr_s8\0" + /* 22229 */ "MVE_VHADD_qr_s8\0" + /* 22245 */ "MVE_VQADD_qr_s8\0" + /* 22261 */ "MVE_VQDMULH_qr_s8\0" + /* 22279 */ "MVE_VQRDMULH_qr_s8\0" + /* 22298 */ "MVE_VMLAS_qr_s8\0" + /* 22314 */ "MVE_VMLADAVas8\0" + /* 22329 */ "MVE_VMLSDAVas8\0" + /* 22344 */ "MVE_VQSHL_by_vecs8\0" + /* 22363 */ "MVE_VQRSHL_by_vecs8\0" + /* 22383 */ "MVE_VRSHL_by_vecs8\0" + /* 22402 */ "MVE_VSHL_by_vecs8\0" + /* 22420 */ "MVE_VQSHLimms8\0" + /* 22435 */ "MVE_VRSHR_imms8\0" + /* 22451 */ "MVE_VSHR_imms8\0" + /* 22466 */ "MVE_VQSHLU_imms8\0" + /* 22483 */ "MVE_VQDMLAH_qrs8\0" + /* 22500 */ "MVE_VQRDMLAH_qrs8\0" + /* 22518 */ "MVE_VQDMLASH_qrs8\0" + /* 22536 */ "MVE_VQRDMLASH_qrs8\0" + /* 22555 */ "MVE_VQSHL_qrs8\0" + /* 22570 */ "MVE_VQRSHL_qrs8\0" + /* 22586 */ "MVE_VRSHL_qrs8\0" + /* 22601 */ "MVE_VSHL_qrs8\0" + /* 22615 */ "MVE_VMLADAVxs8\0" + /* 22630 */ "MVE_VMLSDAVxs8\0" + /* 22645 */ "MVE_VMLADAVaxs8\0" + /* 22661 */ "MVE_VMLSDAVaxs8\0" + /* 22677 */ "MVE_VPTv16u8\0" + /* 22690 */ "MVE_VMULLBu8\0" + /* 22703 */ "MVE_VHSUBu8\0" + /* 22715 */ "MVE_VQSUBu8\0" + /* 22727 */ "MVE_VABDu8\0" + /* 22738 */ "MVE_VRHADDu8\0" + /* 22751 */ "MVE_VHADDu8\0" + /* 22763 */ "MVE_VQADDu8\0" + /* 22775 */ "MVE_VRMULHu8\0" + /* 22788 */ "MVE_VMULHu8\0" + /* 22800 */ "VPMINu8\0" + /* 22808 */ "MVE_VMINu8\0" + /* 22819 */ "VGETLNu8\0" + /* 22828 */ "MVE_VCMPu8\0" + /* 22839 */ "MVE_VDDUPu8\0" + /* 22851 */ "MVE_VIDUPu8\0" + /* 22863 */ "MVE_VDWDUPu8\0" + /* 22876 */ "MVE_VIWDUPu8\0" + /* 22889 */ "MVE_VMULLTu8\0" + /* 22902 */ "MVE_VABAVu8\0" + /* 22914 */ "MVE_VMLADAVu8\0" + /* 22928 */ "MVE_VMINVu8\0" + /* 22940 */ "MVE_VMAXVu8\0" + /* 22952 */ "VPMAXu8\0" + /* 22960 */ "MVE_VMAXu8\0" + /* 22971 */ "MVE_VMOV_from_lane_u8\0" + /* 22993 */ "MVE_VMLA_qr_u8\0" + /* 23008 */ "MVE_VHSUB_qr_u8\0" + /* 23024 */ "MVE_VQSUB_qr_u8\0" + /* 23040 */ "MVE_VHADD_qr_u8\0" + /* 23056 */ "MVE_VQADD_qr_u8\0" + /* 23072 */ "MVE_VMLAS_qr_u8\0" + /* 23088 */ "MVE_VMLADAVau8\0" + /* 23103 */ "MVE_VQSHL_by_vecu8\0" + /* 23122 */ "MVE_VQRSHL_by_vecu8\0" + /* 23142 */ "MVE_VRSHL_by_vecu8\0" + /* 23161 */ "MVE_VSHL_by_vecu8\0" + /* 23179 */ "MVE_VQSHLimmu8\0" + /* 23194 */ "MVE_VRSHR_immu8\0" + /* 23210 */ "MVE_VSHR_immu8\0" + /* 23225 */ "MVE_VQSHL_qru8\0" + /* 23240 */ "MVE_VQRSHL_qru8\0" + /* 23256 */ "MVE_VRSHL_qru8\0" + /* 23271 */ "MVE_VSHL_qru8\0" + /* 23285 */ "CDE_CX1A\0" + /* 23294 */ "MVE_VRINTf32A\0" + /* 23308 */ "CDE_CX2A\0" + /* 23317 */ "CDE_CX3A\0" + /* 23326 */ "MVE_VRINTf16A\0" + /* 23340 */ "CDE_CX1DA\0" + /* 23350 */ "CDE_CX2DA\0" + /* 23360 */ "CDE_CX3DA\0" + /* 23370 */ "RFEDA\0" + /* 23376 */ "t2LDA\0" + /* 23382 */ "sysLDMDA\0" + /* 23391 */ "sysSTMDA\0" + /* 23400 */ "SRSDA\0" + /* 23406 */ "VLDMDIA\0" + /* 23414 */ "VSTMDIA\0" + /* 23422 */ "t2RFEIA\0" + /* 23430 */ "t2LDMIA\0" + /* 23438 */ "sysLDMIA\0" + /* 23447 */ "tLDMIA\0" + /* 23454 */ "t2STMIA\0" + /* 23462 */ "sysSTMIA\0" + /* 23471 */ "VLDMQIA\0" + /* 23479 */ "VSTMQIA\0" + /* 23487 */ "VLDMSIA\0" + /* 23495 */ "VSTMSIA\0" + /* 23503 */ "t2SRSIA\0" + /* 23511 */ "FLDMXIA\0" + /* 23519 */ "FSTMXIA\0" + /* 23527 */ "t2MLA\0" + /* 23533 */ "t2SMMLA\0" + /* 23541 */ "VUSMMLA\0" + /* 23549 */ "VSMMLA\0" + /* 23556 */ "VUMMLA\0" + /* 23563 */ "VMMLA\0" + /* 23569 */ "G_FMA\0" + /* 23575 */ "G_STRICT_FMA\0" + /* 23588 */ "t2TTA\0" + /* 23594 */ "t2CRC32B\0" + /* 23603 */ "t2B\0" + /* 23607 */ "t2LDAB\0" + /* 23614 */ "t2SXTAB\0" + /* 23622 */ "t2UXTAB\0" + /* 23630 */ "t2SMLABB\0" + /* 23639 */ "t2SMLALBB\0" + /* 23649 */ "t2SMULBB\0" + /* 23658 */ "t2TBB\0" + /* 23664 */ "JUMPTABLE_TBB\0" + /* 23678 */ "t2SpeculationBarrierISBDSBEndBB\0" + /* 23710 */ "t2SpeculationBarrierSBEndBB\0" + /* 23738 */ "t2CRC32CB\0" + /* 23748 */ "t2RFEDB\0" + /* 23756 */ "t2LDMDB\0" + /* 23764 */ "sysLDMDB\0" + /* 23773 */ "t2STMDB\0" + /* 23781 */ "sysSTMDB\0" + /* 23790 */ "t2SRSDB\0" + /* 23798 */ "RFEIB\0" + /* 23804 */ "sysLDMIB\0" + /* 23813 */ "sysSTMIB\0" + /* 23822 */ "SRSIB\0" + /* 23828 */ "t2STLB\0" + /* 23835 */ "t2DMB\0" + /* 23841 */ "SWPB\0" + /* 23846 */ "PICLDRB\0" + /* 23854 */ "PICSTRB\0" + /* 23862 */ "t2SB\0" + /* 23867 */ "t2DSB\0" + /* 23873 */ "t2ISB\0" + /* 23879 */ "PICLDRSB\0" + /* 23888 */ "tLDRSB\0" + /* 23895 */ "tRSB\0" + /* 23900 */ "t2TSB\0" + /* 23906 */ "t2SMLATB\0" + /* 23915 */ "t2PKHTB\0" + /* 23923 */ "t2SMLALTB\0" + /* 23933 */ "t2SMULTB\0" + /* 23942 */ "BF16_VCVTB\0" + /* 23953 */ "t2SXTB\0" + /* 23960 */ "tSXTB\0" + /* 23966 */ "t2UXTB\0" + /* 23973 */ "tUXTB\0" + /* 23979 */ "t2QDSUB\0" + /* 23987 */ "G_FSUB\0" + /* 23994 */ "G_STRICT_FSUB\0" + /* 24008 */ "G_ATOMICRMW_FSUB\0" + /* 24025 */ "t2QSUB\0" + /* 24032 */ "G_SUB\0" + /* 24038 */ "G_ATOMICRMW_SUB\0" + /* 24054 */ "t2SMLAWB\0" + /* 24063 */ "t2SMULWB\0" + /* 24072 */ "t2LDAEXB\0" + /* 24081 */ "t2STLEXB\0" + /* 24090 */ "t2LDREXB\0" + /* 24099 */ "t2STREXB\0" + /* 24108 */ "tB\0" + /* 24111 */ "SHA1C\0" + /* 24117 */ "MVE_VSBC\0" + /* 24126 */ "tSBC\0" + /* 24131 */ "MVE_VADC\0" + /* 24140 */ "tADC\0" + /* 24145 */ "t2BFC\0" + /* 24151 */ "MVE_VBIC\0" + /* 24160 */ "tBIC\0" + /* 24165 */ "G_INTRINSIC\0" + /* 24177 */ "MVE_VSHLC\0" + /* 24187 */ "AESIMC\0" + /* 24194 */ "t2SMC\0" + /* 24200 */ "AESMC\0" + /* 24206 */ "t2CSINC\0" + /* 24214 */ "G_FPTRUNC\0" + /* 24224 */ "G_INTRINSIC_TRUNC\0" + /* 24242 */ "G_TRUNC\0" + /* 24250 */ "G_BUILD_VECTOR_TRUNC\0" + /* 24271 */ "G_DYN_STACKALLOC\0" + /* 24288 */ "VMSR_FPSCR_NZCVQC\0" + /* 24306 */ "VMRS_FPSCR_NZCVQC\0" + /* 24324 */ "t2MRC\0" + /* 24330 */ "t2MRRC\0" + /* 24337 */ "MOVr_TC\0" + /* 24345 */ "t2HVC\0" + /* 24351 */ "tSVC\0" + /* 24356 */ "VMSR_FPEXC\0" + /* 24367 */ "VMRS_FPEXC\0" + /* 24378 */ "CDE_CX1D\0" + /* 24387 */ "CDE_CX2D\0" + /* 24396 */ "CDE_CX3D\0" + /* 24405 */ "VNMLAD\0" + /* 24412 */ "t2SMLAD\0" + /* 24420 */ "VMLAD\0" + /* 24426 */ "VFMAD\0" + /* 24432 */ "G_FMAD\0" + /* 24439 */ "VFNMAD\0" + /* 24446 */ "G_INDEXED_SEXTLOAD\0" + /* 24465 */ "G_SEXTLOAD\0" + /* 24476 */ "G_INDEXED_ZEXTLOAD\0" + /* 24495 */ "G_ZEXTLOAD\0" + /* 24506 */ "G_INDEXED_LOAD\0" + /* 24521 */ "G_LOAD\0" + /* 24528 */ "VRINTAD\0" + /* 24536 */ "t2SMUAD\0" + /* 24544 */ "VSUBD\0" + /* 24550 */ "tPICADD\0" + /* 24558 */ "t2QDADD\0" + /* 24566 */ "G_VECREDUCE_FADD\0" + /* 24583 */ "G_FADD\0" + /* 24590 */ "G_VECREDUCE_SEQ_FADD\0" + /* 24611 */ "G_STRICT_FADD\0" + /* 24625 */ "G_ATOMICRMW_FADD\0" + /* 24642 */ "t2QADD\0" + /* 24649 */ "G_VECREDUCE_ADD\0" + /* 24665 */ "G_ADD\0" + /* 24671 */ "G_PTR_ADD\0" + /* 24681 */ "G_ATOMICRMW_ADD\0" + /* 24697 */ "VADDD\0" + /* 24703 */ "VSELGED\0" + /* 24711 */ "VCMPED\0" + /* 24718 */ "VNEGD\0" + /* 24724 */ "VCVTBHD\0" + /* 24732 */ "VTOSHD\0" + /* 24739 */ "VCVTTHD\0" + /* 24747 */ "VTOUHD\0" + /* 24754 */ "VMSR_FPSID\0" + /* 24765 */ "VMRS_FPSID\0" + /* 24776 */ "t2SMLALD\0" + /* 24785 */ "VFMALD\0" + /* 24792 */ "t2SMLSLD\0" + /* 24801 */ "VFMSLD\0" + /* 24808 */ "VTOSLD\0" + /* 24815 */ "VNMULD\0" + /* 24822 */ "VMULD\0" + /* 24828 */ "VTOULD\0" + /* 24835 */ "VFP_VMINNMD\0" + /* 24847 */ "VFP_VMAXNMD\0" + /* 24859 */ "VSCCLRMD\0" + /* 24868 */ "VRINTMD\0" + /* 24876 */ "G_ATOMICRMW_NAND\0" + /* 24893 */ "MVE_VAND\0" + /* 24902 */ "G_VECREDUCE_AND\0" + /* 24918 */ "G_AND\0" + /* 24924 */ "G_ATOMICRMW_AND\0" + /* 24940 */ "tAND\0" + /* 24945 */ "tSETEND\0" + /* 24953 */ "LIFETIME_END\0" + /* 24966 */ "tBRIND\0" + /* 24973 */ "G_BRCOND\0" + /* 24982 */ "VRINTND\0" + /* 24990 */ "G_LLROUND\0" + /* 25000 */ "G_LROUND\0" + /* 25009 */ "G_INTRINSIC_ROUND\0" + /* 25027 */ "tTAILJMPdND\0" + /* 25039 */ "VSHTOD\0" + /* 25046 */ "VUHTOD\0" + /* 25053 */ "VSITOD\0" + /* 25060 */ "VUITOD\0" + /* 25067 */ "VSLTOD\0" + /* 25074 */ "VULTOD\0" + /* 25081 */ "VCMPD\0" + /* 25087 */ "VRINTPD\0" + /* 25095 */ "VLD3d32_UPD\0" + /* 25107 */ "VST3d32_UPD\0" + /* 25119 */ "VLD4d32_UPD\0" + /* 25131 */ "VST4d32_UPD\0" + /* 25143 */ "VLD1LNd32_UPD\0" + /* 25157 */ "VST1LNd32_UPD\0" + /* 25171 */ "VLD2LNd32_UPD\0" + /* 25185 */ "VST2LNd32_UPD\0" + /* 25199 */ "VLD3LNd32_UPD\0" + /* 25213 */ "VST3LNd32_UPD\0" + /* 25227 */ "VLD4LNd32_UPD\0" + /* 25241 */ "VST4LNd32_UPD\0" + /* 25255 */ "VLD3DUPd32_UPD\0" + /* 25270 */ "VLD4DUPd32_UPD\0" + /* 25285 */ "VLD3q32_UPD\0" + /* 25297 */ "VST3q32_UPD\0" + /* 25309 */ "VLD4q32_UPD\0" + /* 25321 */ "VST4q32_UPD\0" + /* 25333 */ "VLD2LNq32_UPD\0" + /* 25347 */ "VST2LNq32_UPD\0" + /* 25361 */ "VLD3LNq32_UPD\0" + /* 25375 */ "VST3LNq32_UPD\0" + /* 25389 */ "VLD4LNq32_UPD\0" + /* 25403 */ "VST4LNq32_UPD\0" + /* 25417 */ "VLD3DUPq32_UPD\0" + /* 25432 */ "VLD4DUPq32_UPD\0" + /* 25447 */ "VLD3d16_UPD\0" + /* 25459 */ "VST3d16_UPD\0" + /* 25471 */ "VLD4d16_UPD\0" + /* 25483 */ "VST4d16_UPD\0" + /* 25495 */ "VLD1LNd16_UPD\0" + /* 25509 */ "VST1LNd16_UPD\0" + /* 25523 */ "VLD2LNd16_UPD\0" + /* 25537 */ "VST2LNd16_UPD\0" + /* 25551 */ "VLD3LNd16_UPD\0" + /* 25565 */ "VST3LNd16_UPD\0" + /* 25579 */ "VLD4LNd16_UPD\0" + /* 25593 */ "VST4LNd16_UPD\0" + /* 25607 */ "VLD3DUPd16_UPD\0" + /* 25622 */ "VLD4DUPd16_UPD\0" + /* 25637 */ "VLD3q16_UPD\0" + /* 25649 */ "VST3q16_UPD\0" + /* 25661 */ "VLD4q16_UPD\0" + /* 25673 */ "VST4q16_UPD\0" + /* 25685 */ "VLD2LNq16_UPD\0" + /* 25699 */ "VST2LNq16_UPD\0" + /* 25713 */ "VLD3LNq16_UPD\0" + /* 25727 */ "VST3LNq16_UPD\0" + /* 25741 */ "VLD4LNq16_UPD\0" + /* 25755 */ "VST4LNq16_UPD\0" + /* 25769 */ "VLD3DUPq16_UPD\0" + /* 25784 */ "VLD4DUPq16_UPD\0" + /* 25799 */ "VLD3d8_UPD\0" + /* 25810 */ "VST3d8_UPD\0" + /* 25821 */ "VLD4d8_UPD\0" + /* 25832 */ "VST4d8_UPD\0" + /* 25843 */ "VLD1LNd8_UPD\0" + /* 25856 */ "VST1LNd8_UPD\0" + /* 25869 */ "VLD2LNd8_UPD\0" + /* 25882 */ "VST2LNd8_UPD\0" + /* 25895 */ "VLD3LNd8_UPD\0" + /* 25908 */ "VST3LNd8_UPD\0" + /* 25921 */ "VLD4LNd8_UPD\0" + /* 25934 */ "VST4LNd8_UPD\0" + /* 25947 */ "VLD3DUPd8_UPD\0" + /* 25961 */ "VLD4DUPd8_UPD\0" + /* 25975 */ "VLD3q8_UPD\0" + /* 25986 */ "VST3q8_UPD\0" + /* 25997 */ "VLD4q8_UPD\0" + /* 26008 */ "VST4q8_UPD\0" + /* 26019 */ "VLD3DUPq8_UPD\0" + /* 26033 */ "VLD4DUPq8_UPD\0" + /* 26047 */ "RFEDA_UPD\0" + /* 26057 */ "sysLDMDA_UPD\0" + /* 26070 */ "sysSTMDA_UPD\0" + /* 26083 */ "SRSDA_UPD\0" + /* 26093 */ "VLDMDIA_UPD\0" + /* 26105 */ "VSTMDIA_UPD\0" + /* 26117 */ "RFEIA_UPD\0" + /* 26127 */ "t2LDMIA_UPD\0" + /* 26139 */ "sysLDMIA_UPD\0" + /* 26152 */ "tLDMIA_UPD\0" + /* 26163 */ "t2STMIA_UPD\0" + /* 26175 */ "sysSTMIA_UPD\0" + /* 26188 */ "tSTMIA_UPD\0" + /* 26199 */ "VLDMSIA_UPD\0" + /* 26211 */ "VSTMSIA_UPD\0" + /* 26223 */ "t2SRSIA_UPD\0" + /* 26235 */ "FLDMXIA_UPD\0" + /* 26247 */ "FSTMXIA_UPD\0" + /* 26259 */ "VLDMDDB_UPD\0" + /* 26271 */ "VSTMDDB_UPD\0" + /* 26283 */ "RFEDB_UPD\0" + /* 26293 */ "t2LDMDB_UPD\0" + /* 26305 */ "sysLDMDB_UPD\0" + /* 26318 */ "t2STMDB_UPD\0" + /* 26330 */ "sysSTMDB_UPD\0" + /* 26343 */ "VLDMSDB_UPD\0" + /* 26355 */ "VSTMSDB_UPD\0" + /* 26367 */ "t2SRSDB_UPD\0" + /* 26379 */ "FLDMXDB_UPD\0" + /* 26391 */ "FSTMXDB_UPD\0" + /* 26403 */ "RFEIB_UPD\0" + /* 26413 */ "sysLDMIB_UPD\0" + /* 26426 */ "sysSTMIB_UPD\0" + /* 26439 */ "SRSIB_UPD\0" + /* 26449 */ "VLD3d32Pseudo_UPD\0" + /* 26467 */ "VST3d32Pseudo_UPD\0" + /* 26485 */ "VLD4d32Pseudo_UPD\0" + /* 26503 */ "VST4d32Pseudo_UPD\0" + /* 26521 */ "VLD2LNd32Pseudo_UPD\0" + /* 26541 */ "VST2LNd32Pseudo_UPD\0" + /* 26561 */ "VLD3LNd32Pseudo_UPD\0" + /* 26581 */ "VST3LNd32Pseudo_UPD\0" + /* 26601 */ "VLD4LNd32Pseudo_UPD\0" + /* 26621 */ "VST4LNd32Pseudo_UPD\0" + /* 26641 */ "VLD3DUPd32Pseudo_UPD\0" + /* 26662 */ "VLD4DUPd32Pseudo_UPD\0" + /* 26683 */ "VLD3q32Pseudo_UPD\0" + /* 26701 */ "VST3q32Pseudo_UPD\0" + /* 26719 */ "VLD4q32Pseudo_UPD\0" + /* 26737 */ "VST4q32Pseudo_UPD\0" + /* 26755 */ "VLD1LNq32Pseudo_UPD\0" + /* 26775 */ "VST1LNq32Pseudo_UPD\0" + /* 26795 */ "VLD2LNq32Pseudo_UPD\0" + /* 26815 */ "VST2LNq32Pseudo_UPD\0" + /* 26835 */ "VLD3LNq32Pseudo_UPD\0" + /* 26855 */ "VST3LNq32Pseudo_UPD\0" + /* 26875 */ "VLD4LNq32Pseudo_UPD\0" + /* 26895 */ "VST4LNq32Pseudo_UPD\0" + /* 26915 */ "VLD3d16Pseudo_UPD\0" + /* 26933 */ "VST3d16Pseudo_UPD\0" + /* 26951 */ "VLD4d16Pseudo_UPD\0" + /* 26969 */ "VST4d16Pseudo_UPD\0" + /* 26987 */ "VLD2LNd16Pseudo_UPD\0" + /* 27007 */ "VST2LNd16Pseudo_UPD\0" + /* 27027 */ "VLD3LNd16Pseudo_UPD\0" + /* 27047 */ "VST3LNd16Pseudo_UPD\0" + /* 27067 */ "VLD4LNd16Pseudo_UPD\0" + /* 27087 */ "VST4LNd16Pseudo_UPD\0" + /* 27107 */ "VLD3DUPd16Pseudo_UPD\0" + /* 27128 */ "VLD4DUPd16Pseudo_UPD\0" + /* 27149 */ "VLD3q16Pseudo_UPD\0" + /* 27167 */ "VST3q16Pseudo_UPD\0" + /* 27185 */ "VLD4q16Pseudo_UPD\0" + /* 27203 */ "VST4q16Pseudo_UPD\0" + /* 27221 */ "VLD1LNq16Pseudo_UPD\0" + /* 27241 */ "VST1LNq16Pseudo_UPD\0" + /* 27261 */ "VLD2LNq16Pseudo_UPD\0" + /* 27281 */ "VST2LNq16Pseudo_UPD\0" + /* 27301 */ "VLD3LNq16Pseudo_UPD\0" + /* 27321 */ "VST3LNq16Pseudo_UPD\0" + /* 27341 */ "VLD4LNq16Pseudo_UPD\0" + /* 27361 */ "VST4LNq16Pseudo_UPD\0" + /* 27381 */ "VLD3d8Pseudo_UPD\0" + /* 27398 */ "VST3d8Pseudo_UPD\0" + /* 27415 */ "VLD4d8Pseudo_UPD\0" + /* 27432 */ "VST4d8Pseudo_UPD\0" + /* 27449 */ "VLD2LNd8Pseudo_UPD\0" + /* 27468 */ "VST2LNd8Pseudo_UPD\0" + /* 27487 */ "VLD3LNd8Pseudo_UPD\0" + /* 27506 */ "VST3LNd8Pseudo_UPD\0" + /* 27525 */ "VLD4LNd8Pseudo_UPD\0" + /* 27544 */ "VST4LNd8Pseudo_UPD\0" + /* 27563 */ "VLD3DUPd8Pseudo_UPD\0" + /* 27583 */ "VLD4DUPd8Pseudo_UPD\0" + /* 27603 */ "VLD3q8Pseudo_UPD\0" + /* 27620 */ "VST3q8Pseudo_UPD\0" + /* 27637 */ "VLD4q8Pseudo_UPD\0" + /* 27654 */ "VST4q8Pseudo_UPD\0" + /* 27671 */ "VLD1LNq8Pseudo_UPD\0" + /* 27690 */ "VST1LNq8Pseudo_UPD\0" + /* 27709 */ "VLD1q32HighQPseudo_UPD\0" + /* 27732 */ "VST1q32HighQPseudo_UPD\0" + /* 27755 */ "VLD1q64HighQPseudo_UPD\0" + /* 27778 */ "VST1q64HighQPseudo_UPD\0" + /* 27801 */ "VLD1q16HighQPseudo_UPD\0" + /* 27824 */ "VST1q16HighQPseudo_UPD\0" + /* 27847 */ "VLD1q8HighQPseudo_UPD\0" + /* 27869 */ "VST1q8HighQPseudo_UPD\0" + /* 27891 */ "VLD1q32LowQPseudo_UPD\0" + /* 27913 */ "VST1q32LowQPseudo_UPD\0" + /* 27935 */ "VLD1q64LowQPseudo_UPD\0" + /* 27957 */ "VST1q64LowQPseudo_UPD\0" + /* 27979 */ "VLD1q16LowQPseudo_UPD\0" + /* 28001 */ "VST1q16LowQPseudo_UPD\0" + /* 28023 */ "VLD1q8LowQPseudo_UPD\0" + /* 28044 */ "VST1q8LowQPseudo_UPD\0" + /* 28065 */ "VLD1q32HighTPseudo_UPD\0" + /* 28088 */ "VST1q32HighTPseudo_UPD\0" + /* 28111 */ "VLD1q64HighTPseudo_UPD\0" + /* 28134 */ "VST1q64HighTPseudo_UPD\0" + /* 28157 */ "VLD1q16HighTPseudo_UPD\0" + /* 28180 */ "VST1q16HighTPseudo_UPD\0" + /* 28203 */ "VLD1q8HighTPseudo_UPD\0" + /* 28225 */ "VST1q8HighTPseudo_UPD\0" + /* 28247 */ "VLD1q32LowTPseudo_UPD\0" + /* 28269 */ "VST1q32LowTPseudo_UPD\0" + /* 28291 */ "VLD1q64LowTPseudo_UPD\0" + /* 28313 */ "VST1q64LowTPseudo_UPD\0" + /* 28335 */ "VLD1q16LowTPseudo_UPD\0" + /* 28357 */ "VST1q16LowTPseudo_UPD\0" + /* 28379 */ "VLD1q8LowTPseudo_UPD\0" + /* 28400 */ "VST1q8LowTPseudo_UPD\0" + /* 28421 */ "VLD3DUPq32OddPseudo_UPD\0" + /* 28445 */ "VLD4DUPq32OddPseudo_UPD\0" + /* 28469 */ "VLD3DUPq16OddPseudo_UPD\0" + /* 28493 */ "VLD4DUPq16OddPseudo_UPD\0" + /* 28517 */ "VLD3DUPq8OddPseudo_UPD\0" + /* 28540 */ "VLD4DUPq8OddPseudo_UPD\0" + /* 28563 */ "VLD3q32oddPseudo_UPD\0" + /* 28584 */ "VST3q32oddPseudo_UPD\0" + /* 28605 */ "VLD4q32oddPseudo_UPD\0" + /* 28626 */ "VST4q32oddPseudo_UPD\0" + /* 28647 */ "VLD3q16oddPseudo_UPD\0" + /* 28668 */ "VST3q16oddPseudo_UPD\0" + /* 28689 */ "VLD4q16oddPseudo_UPD\0" + /* 28710 */ "VST4q16oddPseudo_UPD\0" + /* 28731 */ "VLD3q8oddPseudo_UPD\0" + /* 28751 */ "VST3q8oddPseudo_UPD\0" + /* 28771 */ "VLD4q8oddPseudo_UPD\0" + /* 28791 */ "VST4q8oddPseudo_UPD\0" + /* 28811 */ "VSELEQD\0" + /* 28819 */ "LOAD_STACK_GUARD\0" + /* 28836 */ "VLDRD\0" + /* 28842 */ "VTOSIRD\0" + /* 28850 */ "VTOUIRD\0" + /* 28858 */ "VMOVRRD\0" + /* 28866 */ "VRINTRD\0" + /* 28874 */ "VSTRD\0" + /* 28880 */ "VCVTASD\0" + /* 28888 */ "VABSD\0" + /* 28894 */ "AESD\0" + /* 28899 */ "VNMLSD\0" + /* 28906 */ "t2SMLSD\0" + /* 28914 */ "VMLSD\0" + /* 28920 */ "VFMSD\0" + /* 28926 */ "VFNMSD\0" + /* 28933 */ "VCVTMSD\0" + /* 28941 */ "VCVTNSD\0" + /* 28949 */ "VCVTPSD\0" + /* 28957 */ "VCVTSD\0" + /* 28964 */ "t2SMUSD\0" + /* 28972 */ "VSELVSD\0" + /* 28980 */ "VSELGTD\0" + /* 28988 */ "VUSDOTD\0" + /* 28996 */ "VSDOTD\0" + /* 29003 */ "VUDOTD\0" + /* 29010 */ "BF16VDOTI_VDOTD\0" + /* 29026 */ "BF16VDOTS_VDOTD\0" + /* 29042 */ "VSQRTD\0" + /* 29049 */ "FCONSTD\0" + /* 29057 */ "VCVTAUD\0" + /* 29065 */ "VCVTMUD\0" + /* 29073 */ "VCVTNUD\0" + /* 29081 */ "VCVTPUD\0" + /* 29089 */ "VDIVD\0" + /* 29095 */ "VMOVD\0" + /* 29101 */ "t2LDAEXD\0" + /* 29110 */ "t2STLEXD\0" + /* 29119 */ "t2LDREXD\0" + /* 29128 */ "t2STREXD\0" + /* 29137 */ "VRINTXD\0" + /* 29145 */ "VCMPEZD\0" + /* 29153 */ "VTOSIZD\0" + /* 29161 */ "VTOUIZD\0" + /* 29169 */ "VCMPZD\0" + /* 29176 */ "VRINTZD\0" + /* 29184 */ "PSEUDO_PROBE\0" + /* 29197 */ "G_SSUBE\0" + /* 29205 */ "G_USUBE\0" + /* 29213 */ "SPACE\0" + /* 29219 */ "G_FENCE\0" + /* 29227 */ "ARITH_FENCE\0" + /* 29239 */ "REG_SEQUENCE\0" + /* 29252 */ "G_SADDE\0" + /* 29260 */ "G_UADDE\0" + /* 29268 */ "G_FMINNUM_IEEE\0" + /* 29283 */ "G_FMAXNUM_IEEE\0" + /* 29298 */ "t2LE\0" + /* 29303 */ "G_JUMP_TABLE\0" + /* 29316 */ "BUNDLE\0" + /* 29323 */ "G_MEMCPY_INLINE\0" + /* 29339 */ "LOCAL_ESCAPE\0" + /* 29352 */ "G_INDEXED_STORE\0" + /* 29368 */ "G_STORE\0" + /* 29376 */ "t2LDC2_PRE\0" + /* 29387 */ "t2STC2_PRE\0" + /* 29398 */ "t2LDRB_PRE\0" + /* 29409 */ "t2STRB_PRE\0" + /* 29420 */ "t2LDRSB_PRE\0" + /* 29432 */ "t2LDC_PRE\0" + /* 29442 */ "t2STC_PRE\0" + /* 29452 */ "t2LDRD_PRE\0" + /* 29463 */ "t2STRD_PRE\0" + /* 29474 */ "t2LDRH_PRE\0" + /* 29485 */ "t2STRH_PRE\0" + /* 29496 */ "t2LDRSH_PRE\0" + /* 29508 */ "t2LDC2L_PRE\0" + /* 29520 */ "t2STC2L_PRE\0" + /* 29532 */ "t2LDCL_PRE\0" + /* 29543 */ "t2STCL_PRE\0" + /* 29554 */ "t2LDR_PRE\0" + /* 29564 */ "t2STR_PRE\0" + /* 29574 */ "AESE\0" + /* 29579 */ "G_BITREVERSE\0" + /* 29592 */ "DBG_VALUE\0" + /* 29602 */ "G_GLOBAL_VALUE\0" + /* 29617 */ "G_MEMMOVE\0" + /* 29627 */ "G_FREEZE\0" + /* 29636 */ "G_FCANONICALIZE\0" + /* 29652 */ "t2UDF\0" + /* 29658 */ "tUDF\0" + /* 29663 */ "G_CTLZ_ZERO_UNDEF\0" + /* 29681 */ "G_CTTZ_ZERO_UNDEF\0" + /* 29699 */ "G_IMPLICIT_DEF\0" + /* 29714 */ "DBG_INSTR_REF\0" + /* 29728 */ "t2DBG\0" + /* 29734 */ "G_FNEG\0" + /* 29741 */ "t2CSNEG\0" + /* 29749 */ "EXTRACT_SUBREG\0" + /* 29764 */ "INSERT_SUBREG\0" + /* 29778 */ "G_SEXT_INREG\0" + /* 29791 */ "LDRB_PRE_REG\0" + /* 29804 */ "STRB_PRE_REG\0" + /* 29817 */ "LDR_PRE_REG\0" + /* 29829 */ "STR_PRE_REG\0" + /* 29841 */ "SUBREG_TO_REG\0" + /* 29855 */ "LDRB_POST_REG\0" + /* 29869 */ "STRB_POST_REG\0" + /* 29883 */ "LDR_POST_REG\0" + /* 29896 */ "STR_POST_REG\0" + /* 29909 */ "LDRBT_POST_REG\0" + /* 29924 */ "STRBT_POST_REG\0" + /* 29939 */ "LDRT_POST_REG\0" + /* 29953 */ "STRT_POST_REG\0" + /* 29967 */ "G_ATOMIC_CMPXCHG\0" + /* 29984 */ "G_ATOMICRMW_XCHG\0" + /* 30001 */ "G_FLOG\0" + /* 30008 */ "G_VAARG\0" + /* 30016 */ "PREALLOCATED_ARG\0" + /* 30033 */ "t2SG\0" + /* 30038 */ "SHA1H\0" + /* 30044 */ "t2CRC32H\0" + /* 30053 */ "SHA256H\0" + /* 30061 */ "t2LDAH\0" + /* 30068 */ "VNMLAH\0" + /* 30075 */ "VMLAH\0" + /* 30081 */ "VFMAH\0" + /* 30087 */ "VFNMAH\0" + /* 30094 */ "VRINTAH\0" + /* 30102 */ "t2SXTAH\0" + /* 30110 */ "t2UXTAH\0" + /* 30118 */ "t2TBH\0" + /* 30124 */ "JUMPTABLE_TBH\0" + /* 30138 */ "VSUBH\0" + /* 30144 */ "t2CRC32CH\0" + /* 30154 */ "VCVTBDH\0" + /* 30162 */ "VADDH\0" + /* 30168 */ "VCVTTDH\0" + /* 30176 */ "VSELGEH\0" + /* 30184 */ "VCMPEH\0" + /* 30191 */ "VNEGH\0" + /* 30197 */ "VTOSHH\0" + /* 30204 */ "VTOUHH\0" + /* 30211 */ "VTOSLH\0" + /* 30218 */ "t2STLH\0" + /* 30225 */ "VNMULH\0" + /* 30232 */ "G_SMULH\0" + /* 30240 */ "G_UMULH\0" + /* 30248 */ "VMULH\0" + /* 30254 */ "VTOULH\0" + /* 30261 */ "VFP_VMINNMH\0" + /* 30273 */ "VFP_VMAXNMH\0" + /* 30285 */ "VRINTMH\0" + /* 30293 */ "VRINTNH\0" + /* 30301 */ "VSHTOH\0" + /* 30308 */ "VUHTOH\0" + /* 30315 */ "VSITOH\0" + /* 30322 */ "VUITOH\0" + /* 30329 */ "VSLTOH\0" + /* 30336 */ "VULTOH\0" + /* 30343 */ "VCMPH\0" + /* 30349 */ "VRINTPH\0" + /* 30357 */ "VSELEQH\0" + /* 30365 */ "PICLDRH\0" + /* 30373 */ "VLDRH\0" + /* 30379 */ "VTOSIRH\0" + /* 30387 */ "VTOUIRH\0" + /* 30395 */ "VRINTRH\0" + /* 30403 */ "PICSTRH\0" + /* 30411 */ "VSTRH\0" + /* 30417 */ "VMOVRH\0" + /* 30424 */ "VCVTASH\0" + /* 30432 */ "VABSH\0" + /* 30438 */ "VCVTBSH\0" + /* 30446 */ "VNMLSH\0" + /* 30453 */ "VMLSH\0" + /* 30459 */ "VFMSH\0" + /* 30465 */ "VFNMSH\0" + /* 30472 */ "VCVTMSH\0" + /* 30480 */ "VINSH\0" + /* 30486 */ "VCVTNSH\0" + /* 30494 */ "VCVTPSH\0" + /* 30502 */ "PICLDRSH\0" + /* 30511 */ "tLDRSH\0" + /* 30518 */ "VCVTTSH\0" + /* 30526 */ "tPUSH\0" + /* 30532 */ "t2REVSH\0" + /* 30540 */ "tREVSH\0" + /* 30547 */ "VSELVSH\0" + /* 30555 */ "VSELGTH\0" + /* 30563 */ "VSQRTH\0" + /* 30570 */ "FCONSTH\0" + /* 30578 */ "t2SXTH\0" + /* 30585 */ "tSXTH\0" + /* 30591 */ "t2UXTH\0" + /* 30598 */ "tUXTH\0" + /* 30604 */ "VCVTAUH\0" + /* 30612 */ "VCVTMUH\0" + /* 30620 */ "VCVTNUH\0" + /* 30628 */ "VCVTPUH\0" + /* 30636 */ "VDIVH\0" + /* 30642 */ "VMOVH\0" + /* 30648 */ "t2LDAEXH\0" + /* 30657 */ "t2STLEXH\0" + /* 30666 */ "t2LDREXH\0" + /* 30675 */ "t2STREXH\0" + /* 30684 */ "VRINTXH\0" + /* 30692 */ "VCMPEZH\0" + /* 30700 */ "VTOSIZH\0" + /* 30708 */ "VTOUIZH\0" + /* 30716 */ "VCMPZH\0" + /* 30723 */ "VRINTZH\0" + /* 30731 */ "MVE_VSBCI\0" + /* 30741 */ "MVE_VADCI\0" + /* 30751 */ "VFMALDI\0" + /* 30759 */ "VFMSLDI\0" + /* 30767 */ "VUSDOTDI\0" + /* 30776 */ "VSDOTDI\0" + /* 30784 */ "VSUDOTDI\0" + /* 30793 */ "VUDOTDI\0" + /* 30801 */ "t2BFI\0" + /* 30807 */ "DBG_PHI\0" + /* 30815 */ "VBF16MALBQI\0" + /* 30827 */ "VFMALQI\0" + /* 30835 */ "VFMSLQI\0" + /* 30843 */ "VBF16MALTQI\0" + /* 30855 */ "VUSDOTQI\0" + /* 30864 */ "VSDOTQI\0" + /* 30872 */ "VSUDOTQI\0" + /* 30881 */ "VUDOTQI\0" + /* 30889 */ "G_FPTOSI\0" + /* 30898 */ "G_FPTOUI\0" + /* 30907 */ "G_FPOWI\0" + /* 30915 */ "t2BXJ\0" + /* 30921 */ "WIN__DBZCHK\0" + /* 30933 */ "G_PTRMASK\0" + /* 30943 */ "WIN__CHKSTK\0" + /* 30955 */ "t2UMAAL\0" + /* 30963 */ "t2SMLAL\0" + /* 30971 */ "t2UMLAL\0" + /* 30979 */ "LOADDUAL\0" + /* 30988 */ "STOREDUAL\0" + /* 30998 */ "tBL\0" + /* 31002 */ "GC_LABEL\0" + /* 31011 */ "DBG_LABEL\0" + /* 31021 */ "EH_LABEL\0" + /* 31030 */ "ANNOTATION_LABEL\0" + /* 31047 */ "ICALL_BRANCH_FUNNEL\0" + /* 31067 */ "t2SEL\0" + /* 31073 */ "t2CSEL\0" + /* 31080 */ "MVE_VPSEL\0" + /* 31090 */ "G_FSHL\0" + /* 31097 */ "MVE_SQSHL\0" + /* 31107 */ "MVE_UQSHL\0" + /* 31117 */ "MVE_UQRSHL\0" + /* 31128 */ "G_SHL\0" + /* 31134 */ "G_FCEIL\0" + /* 31142 */ "BMOVPCB_CALL\0" + /* 31155 */ "PATCHABLE_TAIL_CALL\0" + /* 31175 */ "tBLXNS_CALL\0" + /* 31187 */ "PATCHABLE_TYPED_EVENT_CALL\0" + /* 31214 */ "PATCHABLE_EVENT_CALL\0" + /* 31235 */ "tBX_CALL\0" + /* 31244 */ "BMOVPCRX_CALL\0" + /* 31258 */ "FENTRY_CALL\0" + /* 31270 */ "MVE_SQSHLL\0" + /* 31281 */ "MVE_UQSHLL\0" + /* 31292 */ "MVE_UQRSHLL\0" + /* 31304 */ "KILL\0" + /* 31309 */ "t2SMULL\0" + /* 31317 */ "t2UMULL\0" + /* 31325 */ "MVE_SQRSHRL\0" + /* 31337 */ "MVE_SRSHRL\0" + /* 31348 */ "MVE_URSHRL\0" + /* 31359 */ "MVE_LSRL\0" + /* 31368 */ "G_ROTL\0" + /* 31375 */ "t2STL\0" + /* 31381 */ "t2MUL\0" + /* 31387 */ "G_VECREDUCE_FMUL\0" + /* 31404 */ "G_FMUL\0" + /* 31411 */ "G_VECREDUCE_SEQ_FMUL\0" + /* 31432 */ "G_STRICT_FMUL\0" + /* 31446 */ "t2SMMUL\0" + /* 31454 */ "G_VECREDUCE_MUL\0" + /* 31470 */ "G_MUL\0" + /* 31476 */ "tMUL\0" + /* 31481 */ "SHA1M\0" + /* 31487 */ "MVE_VRINTf32M\0" + /* 31501 */ "MVE_VRINTf16M\0" + /* 31515 */ "VLLDM\0" + /* 31521 */ "G_FREM\0" + /* 31528 */ "G_STRICT_FREM\0" + /* 31542 */ "G_SREM\0" + /* 31549 */ "G_UREM\0" + /* 31556 */ "G_SDIVREM\0" + /* 31566 */ "G_UDIVREM\0" + /* 31576 */ "LDRB_PRE_IMM\0" + /* 31589 */ "STRB_PRE_IMM\0" + /* 31602 */ "LDR_PRE_IMM\0" + /* 31614 */ "STR_PRE_IMM\0" + /* 31626 */ "LDRB_POST_IMM\0" + /* 31640 */ "STRB_POST_IMM\0" + /* 31654 */ "LDR_POST_IMM\0" + /* 31667 */ "STR_POST_IMM\0" + /* 31680 */ "LDRBT_POST_IMM\0" + /* 31695 */ "STRBT_POST_IMM\0" + /* 31710 */ "LDRT_POST_IMM\0" + /* 31724 */ "STRT_POST_IMM\0" + /* 31738 */ "t2CLRM\0" + /* 31745 */ "INLINEASM\0" + /* 31755 */ "VLSTM\0" + /* 31761 */ "G_FMINIMUM\0" + /* 31772 */ "G_FMAXIMUM\0" + /* 31783 */ "G_FMINNUM\0" + /* 31793 */ "G_FMAXNUM\0" + /* 31803 */ "t2MSR_M\0" + /* 31811 */ "t2MRS_M\0" + /* 31819 */ "MVE_VRINTf32N\0" + /* 31833 */ "MVE_VRINTf16N\0" + /* 31847 */ "t2SETPAN\0" + /* 31856 */ "G_INTRINSIC_ROUNDEVEN\0" + /* 31878 */ "G_FCOPYSIGN\0" + /* 31890 */ "G_VECREDUCE_FMIN\0" + /* 31907 */ "G_VECREDUCE_SMIN\0" + /* 31924 */ "G_SMIN\0" + /* 31931 */ "G_VECREDUCE_UMIN\0" + /* 31948 */ "G_UMIN\0" + /* 31955 */ "G_ATOMICRMW_UMIN\0" + /* 31972 */ "G_ATOMICRMW_MIN\0" + /* 31988 */ "G_FSIN\0" + /* 31995 */ "CFI_INSTRUCTION\0" + /* 32011 */ "t2LDC2_OPTION\0" + /* 32025 */ "t2STC2_OPTION\0" + /* 32039 */ "t2LDC_OPTION\0" + /* 32052 */ "t2STC_OPTION\0" + /* 32065 */ "t2LDC2L_OPTION\0" + /* 32080 */ "t2STC2L_OPTION\0" + /* 32095 */ "t2LDCL_OPTION\0" + /* 32109 */ "t2STCL_OPTION\0" + /* 32123 */ "MVE_VORN\0" + /* 32132 */ "MVE_VMVN\0" + /* 32141 */ "tMVN\0" + /* 32146 */ "tADJCALLSTACKDOWN\0" + /* 32164 */ "G_SSUBO\0" + /* 32172 */ "G_USUBO\0" + /* 32180 */ "G_SADDO\0" + /* 32188 */ "G_UADDO\0" + /* 32196 */ "G_SMULO\0" + /* 32204 */ "G_UMULO\0" + /* 32212 */ "G_BZERO\0" + /* 32220 */ "SHA1P\0" + /* 32226 */ "MVE_VRINTf32P\0" + /* 32240 */ "MVE_VRINTf16P\0" + /* 32254 */ "STACKMAP\0" + /* 32263 */ "tTRAP\0" + /* 32269 */ "G_BSWAP\0" + /* 32277 */ "t2CDP\0" + /* 32283 */ "G_SITOFP\0" + /* 32292 */ "G_UITOFP\0" + /* 32301 */ "G_FCMP\0" + /* 32308 */ "G_ICMP\0" + /* 32315 */ "G_CTPOP\0" + /* 32323 */ "tPOP\0" + /* 32328 */ "PATCHABLE_OP\0" + /* 32341 */ "FAULTING_OP\0" + /* 32353 */ "tADDrSP\0" + /* 32361 */ "MVE_LCTP\0" + /* 32370 */ "MVE_LETP\0" + /* 32379 */ "t2WhileLoopStartTP\0" + /* 32398 */ "t2DoLoopStartTP\0" + /* 32414 */ "tADJCALLSTACKUP\0" + /* 32430 */ "PREALLOCATED_SETUP\0" + /* 32449 */ "SWP\0" + /* 32453 */ "G_FEXP\0" + /* 32460 */ "VLD1d32Q\0" + /* 32469 */ "VST1d32Q\0" + /* 32478 */ "VLD1d64Q\0" + /* 32487 */ "VST1d64Q\0" + /* 32496 */ "VLD1d16Q\0" + /* 32505 */ "VST1d16Q\0" + /* 32514 */ "VLD1d8Q\0" + /* 32522 */ "VST1d8Q\0" + /* 32530 */ "VBF16MALBQ\0" + /* 32541 */ "VFMALQ\0" + /* 32548 */ "VFMSLQ\0" + /* 32555 */ "VBF16MALTQ\0" + /* 32566 */ "VUSDOTQ\0" + /* 32574 */ "VSDOTQ\0" + /* 32581 */ "VUDOTQ\0" + /* 32588 */ "BF16VDOTI_VDOTQ\0" + /* 32604 */ "BF16VDOTS_VDOTQ\0" + /* 32620 */ "t2SMMLAR\0" + /* 32629 */ "t2MSR_AR\0" + /* 32638 */ "t2MRS_AR\0" + /* 32647 */ "t2MRSsys_AR\0" + /* 32659 */ "G_BR\0" + /* 32664 */ "INLINEASM_BR\0" + /* 32677 */ "t2MCR\0" + /* 32683 */ "t2ADR\0" + /* 32689 */ "tADR\0" + /* 32694 */ "G_BLOCK_ADDR\0" + /* 32707 */ "PICLDR\0" + /* 32714 */ "PATCHABLE_FUNCTION_ENTER\0" + /* 32739 */ "G_READCYCLECOUNTER\0" + /* 32758 */ "G_READ_REGISTER\0" + /* 32774 */ "G_WRITE_REGISTER\0" + /* 32791 */ "G_ASHR\0" + /* 32798 */ "G_FSHR\0" + /* 32805 */ "G_LSHR\0" + /* 32812 */ "MVE_SQRSHR\0" + /* 32823 */ "MVE_SRSHR\0" + /* 32833 */ "MVE_URSHR\0" + /* 32843 */ "VMOVHR\0" + /* 32850 */ "MOVPCLR\0" + /* 32858 */ "tBL_PUSHLR\0" + /* 32869 */ "t2SMMULR\0" + /* 32878 */ "t2SUBS_PC_LR\0" + /* 32891 */ "t2WhileLoopStartLR\0" + /* 32910 */ "MVE_VEOR\0" + /* 32919 */ "tEOR\0" + /* 32924 */ "G_FFLOOR\0" + /* 32933 */ "tROR\0" + /* 32938 */ "G_BUILD_VECTOR\0" + /* 32953 */ "G_SHUFFLE_VECTOR\0" + /* 32970 */ "G_VECREDUCE_XOR\0" + /* 32986 */ "G_XOR\0" + /* 32992 */ "G_ATOMICRMW_XOR\0" + /* 33008 */ "G_VECREDUCE_OR\0" + /* 33023 */ "G_OR\0" + /* 33028 */ "G_ATOMICRMW_OR\0" + /* 33043 */ "VMSR_VPR\0" + /* 33052 */ "VMRS_VPR\0" + /* 33061 */ "t2MCRR\0" + /* 33068 */ "VMOVDRR\0" + /* 33076 */ "MVE_VORR\0" + /* 33085 */ "tORR\0" + /* 33090 */ "VMOVSRR\0" + /* 33098 */ "t2SMMLSR\0" + /* 33107 */ "VMSR\0" + /* 33112 */ "VMOVSR\0" + /* 33119 */ "G_ROTR\0" + /* 33126 */ "G_INTTOPTR\0" + /* 33137 */ "PICSTR\0" + /* 33144 */ "VNMLAS\0" + /* 33151 */ "VMLAS\0" + /* 33157 */ "VFMAS\0" + /* 33163 */ "VFNMAS\0" + /* 33170 */ "VRINTAS\0" + /* 33178 */ "t2ABS\0" + /* 33184 */ "G_FABS\0" + /* 33191 */ "G_ABS\0" + /* 33197 */ "tRSBS\0" + /* 33203 */ "VSUBS\0" + /* 33209 */ "tSBCS\0" + /* 33215 */ "tADCS\0" + /* 33221 */ "VADDS\0" + /* 33227 */ "VCVTDS\0" + /* 33234 */ "VSELGES\0" + /* 33242 */ "VCMPES\0" + /* 33249 */ "G_UNMERGE_VALUES\0" + /* 33266 */ "G_MERGE_VALUES\0" + /* 33281 */ "VNEGS\0" + /* 33287 */ "VCVTBHS\0" + /* 33295 */ "VTOSHS\0" + /* 33302 */ "VCVTTHS\0" + /* 33310 */ "VTOUHS\0" + /* 33317 */ "t2DLS\0" + /* 33323 */ "t2MLS\0" + /* 33329 */ "t2SMMLS\0" + /* 33337 */ "VTOSLS\0" + /* 33344 */ "VNMULS\0" + /* 33351 */ "VMULS\0" + /* 33357 */ "VTOULS\0" + /* 33364 */ "t2WLS\0" + /* 33370 */ "VFP_VMINNMS\0" + /* 33382 */ "VFP_VMAXNMS\0" + /* 33394 */ "VSCCLRMS\0" + /* 33403 */ "VRINTMS\0" + /* 33411 */ "VRINTNS\0" + /* 33419 */ "VMSR_FPCXTNS\0" + /* 33432 */ "VMRS_FPCXTNS\0" + /* 33445 */ "tBXNS\0" + /* 33451 */ "G_FCOS\0" + /* 33458 */ "VSHTOS\0" + /* 33465 */ "VUHTOS\0" + /* 33472 */ "VSITOS\0" + /* 33479 */ "VUITOS\0" + /* 33486 */ "VSLTOS\0" + /* 33493 */ "VULTOS\0" + /* 33500 */ "tCPS\0" + /* 33505 */ "VCMPS\0" + /* 33511 */ "VRINTPS\0" + /* 33519 */ "VSELEQS\0" + /* 33527 */ "JUMPTABLE_ADDRS\0" + /* 33543 */ "VLDRS\0" + /* 33549 */ "VTOSIRS\0" + /* 33557 */ "VTOUIRS\0" + /* 33565 */ "VMRS\0" + /* 33570 */ "G_CONCAT_VECTORS\0" + /* 33587 */ "VMOVRRS\0" + /* 33595 */ "VRINTRS\0" + /* 33603 */ "VSTRS\0" + /* 33609 */ "VMOVRS\0" + /* 33616 */ "COPY_TO_REGCLASS\0" + /* 33633 */ "VCVTASS\0" + /* 33641 */ "VABSS\0" + /* 33647 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" + /* 33677 */ "VNMLSS\0" + /* 33684 */ "VMLSS\0" + /* 33690 */ "VFMSS\0" + /* 33696 */ "VFNMSS\0" + /* 33703 */ "VCVTMSS\0" + /* 33711 */ "VCVTNSS\0" + /* 33719 */ "VCVTPSS\0" + /* 33727 */ "VSELVSS\0" + /* 33735 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" + /* 33762 */ "VSELGTS\0" + /* 33770 */ "VSQRTS\0" + /* 33777 */ "JUMPTABLE_INSTS\0" + /* 33793 */ "FCONSTS\0" + /* 33801 */ "VMSR_FPCXTS\0" + /* 33813 */ "VMRS_FPCXTS\0" + /* 33825 */ "VCVTAUS\0" + /* 33833 */ "VCVTMUS\0" + /* 33841 */ "VCVTNUS\0" + /* 33849 */ "VCVTPUS\0" + /* 33857 */ "VDIVS\0" + /* 33863 */ "VMOVS\0" + /* 33869 */ "VRINTXS\0" + /* 33877 */ "VCMPEZS\0" + /* 33885 */ "VTOSIZS\0" + /* 33893 */ "VTOUIZS\0" + /* 33901 */ "VCMPZS\0" + /* 33908 */ "VRINTZS\0" + /* 33916 */ "VLD1d32T\0" + /* 33925 */ "VST1d32T\0" + /* 33934 */ "VLD1d64T\0" + /* 33943 */ "VST1d64T\0" + /* 33952 */ "VLD1d16T\0" + /* 33961 */ "VST1d16T\0" + /* 33970 */ "VLD1d8T\0" + /* 33978 */ "VST1d8T\0" + /* 33986 */ "G_SSUBSAT\0" + /* 33996 */ "G_USUBSAT\0" + /* 34006 */ "G_SADDSAT\0" + /* 34016 */ "G_UADDSAT\0" + /* 34026 */ "G_SSHLSAT\0" + /* 34036 */ "G_USHLSAT\0" + /* 34046 */ "t2SSAT\0" + /* 34053 */ "t2USAT\0" + /* 34060 */ "G_SMULFIXSAT\0" + /* 34073 */ "G_UMULFIXSAT\0" + /* 34086 */ "G_SDIVFIXSAT\0" + /* 34099 */ "G_UDIVFIXSAT\0" + /* 34112 */ "FMSTAT\0" + /* 34119 */ "t2TTAT\0" + /* 34126 */ "t2SMLABT\0" + /* 34135 */ "t2PKHBT\0" + /* 34143 */ "t2SMLALBT\0" + /* 34153 */ "t2SMULBT\0" + /* 34162 */ "t2LDRBT\0" + /* 34170 */ "t2STRBT\0" + /* 34178 */ "t2LDRSBT\0" + /* 34187 */ "G_EXTRACT\0" + /* 34197 */ "G_SELECT\0" + /* 34206 */ "G_BRINDIRECT\0" + /* 34219 */ "ERET\0" + /* 34224 */ "t2LDMIA_RET\0" + /* 34236 */ "PATCHABLE_RET\0" + /* 34250 */ "tPOP_RET\0" + /* 34259 */ "tBXNS_RET\0" + /* 34269 */ "tBX_RET\0" + /* 34277 */ "t2LDC2_OFFSET\0" + /* 34291 */ "t2STC2_OFFSET\0" + /* 34305 */ "t2LDC_OFFSET\0" + /* 34318 */ "t2STC_OFFSET\0" + /* 34331 */ "t2LDC2L_OFFSET\0" + /* 34346 */ "t2STC2L_OFFSET\0" + /* 34361 */ "t2LDCL_OFFSET\0" + /* 34375 */ "t2STCL_OFFSET\0" + /* 34389 */ "G_MEMSET\0" + /* 34398 */ "t2LDRHT\0" + /* 34406 */ "t2STRHT\0" + /* 34414 */ "t2LDRSHT\0" + /* 34423 */ "t2IT\0" + /* 34428 */ "t2RBIT\0" + /* 34435 */ "PATCHABLE_FUNCTION_EXIT\0" + /* 34459 */ "G_BRJT\0" + /* 34466 */ "t2TBB_JT\0" + /* 34475 */ "tTBB_JT\0" + /* 34483 */ "t2TBH_JT\0" + /* 34492 */ "tTBH_JT\0" + /* 34500 */ "t2BR_JT\0" + /* 34508 */ "t2LEApcrelJT\0" + /* 34521 */ "tLEApcrelJT\0" + /* 34533 */ "G_EXTRACT_VECTOR_ELT\0" + /* 34554 */ "G_INSERT_VECTOR_ELT\0" + /* 34574 */ "tHLT\0" + /* 34579 */ "G_FCONSTANT\0" + /* 34591 */ "G_CONSTANT\0" + /* 34602 */ "t2HINT\0" + /* 34609 */ "tHINT\0" + /* 34615 */ "STATEPOINT\0" + /* 34626 */ "PATCHPOINT\0" + /* 34637 */ "G_PTRTOINT\0" + /* 34648 */ "G_FRINT\0" + /* 34656 */ "G_INTRINSIC_LRINT\0" + /* 34674 */ "G_FNEARBYINT\0" + /* 34687 */ "MVE_VPNOT\0" + /* 34697 */ "tBKPT\0" + /* 34703 */ "G_VASTART\0" + /* 34713 */ "LIFETIME_START\0" + /* 34728 */ "t2LDRT\0" + /* 34735 */ "G_INSERT\0" + /* 34744 */ "G_FSQRT\0" + /* 34752 */ "G_STRICT_FSQRT\0" + /* 34767 */ "t2STRT\0" + /* 34774 */ "G_BITCAST\0" + /* 34784 */ "G_ADDRSPACE_CAST\0" + /* 34801 */ "DBG_VALUE_LIST\0" + /* 34816 */ "VMSR_FPINST\0" + /* 34828 */ "VMRS_FPINST\0" + /* 34840 */ "MVE_MEMSETLOOPINST\0" + /* 34859 */ "MVE_MEMCPYLOOPINST\0" + /* 34878 */ "t2LDC2_POST\0" + /* 34890 */ "t2STC2_POST\0" + /* 34902 */ "t2LDRB_POST\0" + /* 34914 */ "t2STRB_POST\0" + /* 34926 */ "t2LDRSB_POST\0" + /* 34939 */ "t2LDC_POST\0" + /* 34950 */ "t2STC_POST\0" + /* 34961 */ "t2LDRD_POST\0" + /* 34973 */ "t2STRD_POST\0" + /* 34985 */ "t2LDRH_POST\0" + /* 34997 */ "t2STRH_POST\0" + /* 35009 */ "t2LDRSH_POST\0" + /* 35022 */ "t2LDC2L_POST\0" + /* 35035 */ "t2STC2L_POST\0" + /* 35048 */ "t2LDCL_POST\0" + /* 35060 */ "t2STCL_POST\0" + /* 35072 */ "t2LDR_POST\0" + /* 35083 */ "t2STR_POST\0" + /* 35094 */ "LDRBT_POST\0" + /* 35105 */ "STRBT_POST\0" + /* 35116 */ "LDRT_POST\0" + /* 35126 */ "STRT_POST\0" + /* 35136 */ "MVE_VPST\0" + /* 35145 */ "tTST\0" + /* 35150 */ "t2TT\0" + /* 35155 */ "t2SMLATT\0" + /* 35164 */ "t2SMLALTT\0" + /* 35174 */ "t2SMULTT\0" + /* 35183 */ "t2TTT\0" + /* 35189 */ "BF16_VCVTT\0" + /* 35200 */ "VJCVT\0" + /* 35206 */ "BF16_VCVT\0" + /* 35216 */ "t2SMLAWT\0" + /* 35225 */ "t2SMULWT\0" + /* 35234 */ "G_FPEXT\0" + /* 35242 */ "G_SEXT\0" + /* 35249 */ "G_ASSERT_SEXT\0" + /* 35263 */ "G_ANYEXT\0" + /* 35272 */ "G_ZEXT\0" + /* 35279 */ "G_ASSERT_ZEXT\0" + /* 35293 */ "t2REV\0" + /* 35299 */ "tREV\0" + /* 35304 */ "G_FDIV\0" + /* 35311 */ "G_STRICT_FDIV\0" + /* 35325 */ "t2SDIV\0" + /* 35332 */ "G_SDIV\0" + /* 35339 */ "t2UDIV\0" + /* 35346 */ "G_UDIV\0" + /* 35353 */ "t2CSINV\0" + /* 35361 */ "t2CRC32W\0" + /* 35370 */ "t2RFEIAW\0" + /* 35379 */ "t2RFEDBW\0" + /* 35388 */ "t2CRC32CW\0" + /* 35398 */ "G_FPOW\0" + /* 35405 */ "MVE_VRINTf32X\0" + /* 35419 */ "MVE_VRINTf16X\0" + /* 35433 */ "G_VECREDUCE_FMAX\0" + /* 35450 */ "G_VECREDUCE_SMAX\0" + /* 35467 */ "G_SMAX\0" + /* 35474 */ "G_VECREDUCE_UMAX\0" + /* 35491 */ "G_UMAX\0" + /* 35498 */ "G_ATOMICRMW_UMAX\0" + /* 35515 */ "G_ATOMICRMW_MAX\0" + /* 35531 */ "t2SHSAX\0" + /* 35539 */ "t2UHSAX\0" + /* 35547 */ "t2QSAX\0" + /* 35554 */ "t2UQSAX\0" + /* 35562 */ "t2SSAX\0" + /* 35569 */ "t2USAX\0" + /* 35576 */ "tBX\0" + /* 35580 */ "t2SMLADX\0" + /* 35589 */ "t2SMUADX\0" + /* 35598 */ "t2SMLALDX\0" + /* 35608 */ "t2SMLSLDX\0" + /* 35618 */ "t2SMLSDX\0" + /* 35627 */ "t2SMUSDX\0" + /* 35636 */ "t2LDAEX\0" + /* 35644 */ "G_FRAME_INDEX\0" + /* 35658 */ "t2STLEX\0" + /* 35666 */ "t2LDREX\0" + /* 35674 */ "t2CLREX\0" + /* 35682 */ "t2STREX\0" + /* 35690 */ "t2SBFX\0" + /* 35697 */ "G_SBFX\0" + /* 35704 */ "t2UBFX\0" + /* 35711 */ "G_UBFX\0" + /* 35718 */ "G_SMULFIX\0" + /* 35728 */ "G_UMULFIX\0" + /* 35738 */ "G_SDIVFIX\0" + /* 35748 */ "G_UDIVFIX\0" + /* 35758 */ "BLX\0" + /* 35762 */ "MOVPCRX\0" + /* 35770 */ "t2RRX\0" + /* 35776 */ "t2SHASX\0" + /* 35784 */ "t2UHASX\0" + /* 35792 */ "t2QASX\0" + /* 35799 */ "t2UQASX\0" + /* 35807 */ "t2SASX\0" + /* 35814 */ "t2UASX\0" + /* 35821 */ "G_MEMCPY\0" + /* 35830 */ "COPY\0" + /* 35835 */ "CONSTPOOL_ENTRY\0" + /* 35851 */ "MVE_VRINTf32Z\0" + /* 35865 */ "MVE_VRINTf16Z\0" + /* 35879 */ "tCBZ\0" + /* 35884 */ "t2CLZ\0" + /* 35890 */ "G_CTLZ\0" + /* 35897 */ "tCBNZ\0" + /* 35903 */ "G_CTTZ\0" + /* 35910 */ "MVE_VCVTs32f32a\0" + /* 35926 */ "MVE_VCVTu32f32a\0" + /* 35942 */ "MVE_VCVTs16f16a\0" + /* 35958 */ "MVE_VCVTu16f16a\0" + /* 35974 */ "MVE_VLD20_32_wb\0" + /* 35990 */ "MVE_VST20_32_wb\0" + /* 36006 */ "MVE_VLD40_32_wb\0" + /* 36022 */ "MVE_VST40_32_wb\0" + /* 36038 */ "MVE_VLD21_32_wb\0" + /* 36054 */ "MVE_VST21_32_wb\0" + /* 36070 */ "MVE_VLD41_32_wb\0" + /* 36086 */ "MVE_VST41_32_wb\0" + /* 36102 */ "MVE_VLD42_32_wb\0" + /* 36118 */ "MVE_VST42_32_wb\0" + /* 36134 */ "MVE_VLD43_32_wb\0" + /* 36150 */ "MVE_VST43_32_wb\0" + /* 36166 */ "MVE_VLD20_16_wb\0" + /* 36182 */ "MVE_VST20_16_wb\0" + /* 36198 */ "MVE_VLD40_16_wb\0" + /* 36214 */ "MVE_VST40_16_wb\0" + /* 36230 */ "MVE_VLD21_16_wb\0" + /* 36246 */ "MVE_VST21_16_wb\0" + /* 36262 */ "MVE_VLD41_16_wb\0" + /* 36278 */ "MVE_VST41_16_wb\0" + /* 36294 */ "MVE_VLD42_16_wb\0" + /* 36310 */ "MVE_VST42_16_wb\0" + /* 36326 */ "MVE_VLD43_16_wb\0" + /* 36342 */ "MVE_VST43_16_wb\0" + /* 36358 */ "MVE_VLD20_8_wb\0" + /* 36373 */ "MVE_VST20_8_wb\0" + /* 36388 */ "MVE_VLD40_8_wb\0" + /* 36403 */ "MVE_VST40_8_wb\0" + /* 36418 */ "MVE_VLD21_8_wb\0" + /* 36433 */ "MVE_VST21_8_wb\0" + /* 36448 */ "MVE_VLD41_8_wb\0" + /* 36463 */ "MVE_VST41_8_wb\0" + /* 36478 */ "MVE_VLD42_8_wb\0" + /* 36493 */ "MVE_VST42_8_wb\0" + /* 36508 */ "MVE_VLD43_8_wb\0" + /* 36523 */ "MVE_VST43_8_wb\0" + /* 36538 */ "t2Bcc\0" + /* 36544 */ "tBcc\0" + /* 36549 */ "VMOVDcc\0" + /* 36557 */ "VMOVHcc\0" + /* 36565 */ "VMOVScc\0" + /* 36573 */ "MVE_VADDVs32acc\0" + /* 36589 */ "MVE_VADDLVs32acc\0" + /* 36606 */ "MVE_VADDVu32acc\0" + /* 36622 */ "MVE_VADDLVu32acc\0" + /* 36639 */ "MVE_VADDVs16acc\0" + /* 36655 */ "MVE_VADDVu16acc\0" + /* 36671 */ "MVE_VADDVs8acc\0" + /* 36686 */ "MVE_VADDVu8acc\0" + /* 36701 */ "MVE_VADDVs32no_acc\0" + /* 36720 */ "MVE_VADDLVs32no_acc\0" + /* 36740 */ "MVE_VADDVu32no_acc\0" + /* 36759 */ "MVE_VADDLVu32no_acc\0" + /* 36779 */ "MVE_VADDVs16no_acc\0" + /* 36798 */ "MVE_VADDVu16no_acc\0" + /* 36817 */ "MVE_VADDVs8no_acc\0" + /* 36835 */ "MVE_VADDVu8no_acc\0" + /* 36853 */ "t2LoopEndDec\0" + /* 36866 */ "t2LoopDec\0" + /* 36876 */ "CDE_VCX1_vec\0" + /* 36889 */ "CDE_VCX2_vec\0" + /* 36902 */ "CDE_VCX3_vec\0" + /* 36915 */ "CDE_VCX1A_vec\0" + /* 36929 */ "CDE_VCX2A_vec\0" + /* 36943 */ "CDE_VCX3A_vec\0" + /* 36957 */ "t2BFic\0" + /* 36964 */ "t2LDRpci_pic\0" + /* 36977 */ "tLDRpci_pic\0" + /* 36989 */ "VDUPLN32d\0" + /* 36999 */ "VDUP32d\0" + /* 37007 */ "VNEGs32d\0" + /* 37016 */ "VDUPLN16d\0" + /* 37026 */ "VDUP16d\0" + /* 37034 */ "VNEGs16d\0" + /* 37043 */ "VDUPLN8d\0" + /* 37052 */ "VDUP8d\0" + /* 37059 */ "VNEGs8d\0" + /* 37067 */ "VBICd\0" + /* 37073 */ "VANDd\0" + /* 37079 */ "VRECPEd\0" + /* 37087 */ "VRSQRTEd\0" + /* 37096 */ "VBIFd\0" + /* 37102 */ "VBSLd\0" + /* 37108 */ "VORNd\0" + /* 37114 */ "VMVNd\0" + /* 37120 */ "tTAILJMPd\0" + /* 37130 */ "VBSPd\0" + /* 37136 */ "VSWPd\0" + /* 37142 */ "VEORd\0" + /* 37148 */ "VORRd\0" + /* 37154 */ "VBITd\0" + /* 37160 */ "VCNTd\0" + /* 37166 */ "MQQPRLoad\0" + /* 37176 */ "MQQQQPRLoad\0" + /* 37188 */ "BR_JTadd\0" + /* 37197 */ "t2MSRbanked\0" + /* 37209 */ "t2MRSbanked\0" + /* 37221 */ "BL_pred\0" + /* 37229 */ "BX_pred\0" + /* 37237 */ "BLX_pred\0" + /* 37246 */ "VCMLAv2f32_indexed\0" + /* 37265 */ "VCMLAv4f32_indexed\0" + /* 37284 */ "VCMLAv4f16_indexed\0" + /* 37303 */ "VCMLAv8f16_indexed\0" + /* 37322 */ "VLD2q32PseudoWB_fixed\0" + /* 37344 */ "VST2q32PseudoWB_fixed\0" + /* 37366 */ "VLD2q16PseudoWB_fixed\0" + /* 37388 */ "VST2q16PseudoWB_fixed\0" + /* 37410 */ "VLD2q8PseudoWB_fixed\0" + /* 37431 */ "VST2q8PseudoWB_fixed\0" + /* 37452 */ "VLD1d32QPseudoWB_fixed\0" + /* 37475 */ "VST1d32QPseudoWB_fixed\0" + /* 37498 */ "VLD1d64QPseudoWB_fixed\0" + /* 37521 */ "VST1d64QPseudoWB_fixed\0" + /* 37544 */ "VLD1d16QPseudoWB_fixed\0" + /* 37567 */ "VST1d16QPseudoWB_fixed\0" + /* 37590 */ "VLD1d8QPseudoWB_fixed\0" + /* 37612 */ "VST1d8QPseudoWB_fixed\0" + /* 37634 */ "VLD1d32TPseudoWB_fixed\0" + /* 37657 */ "VST1d32TPseudoWB_fixed\0" + /* 37680 */ "VLD1d64TPseudoWB_fixed\0" + /* 37703 */ "VST1d64TPseudoWB_fixed\0" + /* 37726 */ "VLD1d16TPseudoWB_fixed\0" + /* 37749 */ "VST1d16TPseudoWB_fixed\0" + /* 37772 */ "VLD1d8TPseudoWB_fixed\0" + /* 37794 */ "VST1d8TPseudoWB_fixed\0" + /* 37816 */ "VLD2DUPq32OddPseudoWB_fixed\0" + /* 37844 */ "VLD2DUPq16OddPseudoWB_fixed\0" + /* 37872 */ "VLD2DUPq8OddPseudoWB_fixed\0" + /* 37899 */ "VLD2b32wb_fixed\0" + /* 37915 */ "VST2b32wb_fixed\0" + /* 37931 */ "VLD1d32wb_fixed\0" + /* 37947 */ "VST1d32wb_fixed\0" + /* 37963 */ "VLD2d32wb_fixed\0" + /* 37979 */ "VST2d32wb_fixed\0" + /* 37995 */ "VLD1DUPd32wb_fixed\0" + /* 38014 */ "VLD2DUPd32wb_fixed\0" + /* 38033 */ "VLD1q32wb_fixed\0" + /* 38049 */ "VST1q32wb_fixed\0" + /* 38065 */ "VLD2q32wb_fixed\0" + /* 38081 */ "VST2q32wb_fixed\0" + /* 38097 */ "VLD1DUPq32wb_fixed\0" + /* 38116 */ "VLD2DUPd32x2wb_fixed\0" + /* 38137 */ "VLD2DUPd16x2wb_fixed\0" + /* 38158 */ "VLD2DUPd8x2wb_fixed\0" + /* 38178 */ "VLD1d64wb_fixed\0" + /* 38194 */ "VST1d64wb_fixed\0" + /* 38210 */ "VLD1q64wb_fixed\0" + /* 38226 */ "VST1q64wb_fixed\0" + /* 38242 */ "VLD2b16wb_fixed\0" + /* 38258 */ "VST2b16wb_fixed\0" + /* 38274 */ "VLD1d16wb_fixed\0" + /* 38290 */ "VST1d16wb_fixed\0" + /* 38306 */ "VLD2d16wb_fixed\0" + /* 38322 */ "VST2d16wb_fixed\0" + /* 38338 */ "VLD1DUPd16wb_fixed\0" + /* 38357 */ "VLD2DUPd16wb_fixed\0" + /* 38376 */ "VLD1q16wb_fixed\0" + /* 38392 */ "VST1q16wb_fixed\0" + /* 38408 */ "VLD2q16wb_fixed\0" + /* 38424 */ "VST2q16wb_fixed\0" + /* 38440 */ "VLD1DUPq16wb_fixed\0" + /* 38459 */ "VLD2b8wb_fixed\0" + /* 38474 */ "VST2b8wb_fixed\0" + /* 38489 */ "VLD1d8wb_fixed\0" + /* 38504 */ "VST1d8wb_fixed\0" + /* 38519 */ "VLD2d8wb_fixed\0" + /* 38534 */ "VST2d8wb_fixed\0" + /* 38549 */ "VLD1DUPd8wb_fixed\0" + /* 38567 */ "VLD2DUPd8wb_fixed\0" + /* 38585 */ "VLD1q8wb_fixed\0" + /* 38600 */ "VST1q8wb_fixed\0" + /* 38615 */ "VLD2q8wb_fixed\0" + /* 38630 */ "VST2q8wb_fixed\0" + /* 38645 */ "VLD1DUPq8wb_fixed\0" + /* 38663 */ "VLD1d32Qwb_fixed\0" + /* 38680 */ "VST1d32Qwb_fixed\0" + /* 38697 */ "VLD1d64Qwb_fixed\0" + /* 38714 */ "VST1d64Qwb_fixed\0" + /* 38731 */ "VLD1d16Qwb_fixed\0" + /* 38748 */ "VST1d16Qwb_fixed\0" + /* 38765 */ "VLD1d8Qwb_fixed\0" + /* 38781 */ "VST1d8Qwb_fixed\0" + /* 38797 */ "VLD1d32Twb_fixed\0" + /* 38814 */ "VST1d32Twb_fixed\0" + /* 38831 */ "VLD1d64Twb_fixed\0" + /* 38848 */ "VST1d64Twb_fixed\0" + /* 38865 */ "VLD1d16Twb_fixed\0" + /* 38882 */ "VST1d16Twb_fixed\0" + /* 38899 */ "VLD1d8Twb_fixed\0" + /* 38915 */ "VST1d8Twb_fixed\0" + /* 38931 */ "VCVTs2fd\0" + /* 38940 */ "VCVTxs2fd\0" + /* 38950 */ "VCVTu2fd\0" + /* 38959 */ "VCVTxu2fd\0" + /* 38969 */ "VMLAfd\0" + /* 38976 */ "VFMAfd\0" + /* 38983 */ "VSUBfd\0" + /* 38990 */ "VABDfd\0" + /* 38997 */ "VADDfd\0" + /* 39004 */ "VACGEfd\0" + /* 39012 */ "VCGEfd\0" + /* 39019 */ "VRECPEfd\0" + /* 39028 */ "VRSQRTEfd\0" + /* 39038 */ "VNEGfd\0" + /* 39045 */ "VMULfd\0" + /* 39052 */ "VMINfd\0" + /* 39059 */ "VCEQfd\0" + /* 39066 */ "VABSfd\0" + /* 39073 */ "VMLSfd\0" + /* 39080 */ "VFMSfd\0" + /* 39087 */ "VRECPSfd\0" + /* 39096 */ "VRSQRTSfd\0" + /* 39106 */ "VACGTfd\0" + /* 39114 */ "VCGTfd\0" + /* 39121 */ "VMAXfd\0" + /* 39128 */ "VMLAslfd\0" + /* 39137 */ "VMULslfd\0" + /* 39146 */ "VMLSslfd\0" + /* 39155 */ "VCVTs2hd\0" + /* 39164 */ "VCVTxs2hd\0" + /* 39174 */ "VCVTu2hd\0" + /* 39183 */ "VCVTxu2hd\0" + /* 39193 */ "VMLAhd\0" + /* 39200 */ "VFMAhd\0" + /* 39207 */ "VSUBhd\0" + /* 39214 */ "VABDhd\0" + /* 39221 */ "VADDhd\0" + /* 39228 */ "VACGEhd\0" + /* 39236 */ "VCGEhd\0" + /* 39243 */ "VRECPEhd\0" + /* 39252 */ "VRSQRTEhd\0" + /* 39262 */ "VNEGhd\0" + /* 39269 */ "VMULhd\0" + /* 39276 */ "VMINhd\0" + /* 39283 */ "VCEQhd\0" + /* 39290 */ "VABShd\0" + /* 39297 */ "VMLShd\0" + /* 39304 */ "VFMShd\0" + /* 39311 */ "VRECPShd\0" + /* 39320 */ "VRSQRTShd\0" + /* 39330 */ "VACGThd\0" + /* 39338 */ "VCGThd\0" + /* 39345 */ "VMAXhd\0" + /* 39352 */ "VMLAslhd\0" + /* 39361 */ "VMULslhd\0" + /* 39370 */ "VMLSslhd\0" + /* 39379 */ "t2LoopEnd\0" + /* 39389 */ "VMULpd\0" + /* 39396 */ "VCVTf2sd\0" + /* 39405 */ "VCVTh2sd\0" + /* 39414 */ "VCVTf2xsd\0" + /* 39424 */ "VCVTh2xsd\0" + /* 39434 */ "VCVTf2ud\0" + /* 39443 */ "VCVTh2ud\0" + /* 39452 */ "VCVTf2xud\0" + /* 39462 */ "VCVTh2xud\0" + /* 39472 */ "tADDframe\0" + /* 39482 */ "MQQPRStore\0" + /* 39493 */ "MQQQQPRStore\0" + /* 39506 */ "VLDR_P0_pre\0" + /* 39518 */ "VSTR_P0_pre\0" + /* 39530 */ "MVE_VSTRB32_pre\0" + /* 39546 */ "MVE_VSTRH32_pre\0" + /* 39562 */ "MVE_VLDRBS32_pre\0" + /* 39579 */ "MVE_VLDRHS32_pre\0" + /* 39596 */ "MVE_VLDRBU32_pre\0" + /* 39613 */ "MVE_VLDRHU32_pre\0" + /* 39630 */ "MVE_VLDRWU32_pre\0" + /* 39647 */ "MVE_VSTRWU32_pre\0" + /* 39664 */ "MVE_VSTRB16_pre\0" + /* 39680 */ "MVE_VLDRBS16_pre\0" + /* 39697 */ "MVE_VLDRBU16_pre\0" + /* 39714 */ "MVE_VLDRHU16_pre\0" + /* 39731 */ "MVE_VSTRHU16_pre\0" + /* 39748 */ "MVE_VLDRBU8_pre\0" + /* 39764 */ "MVE_VSTRBU8_pre\0" + /* 39780 */ "VLDR_FPSCR_NZCVQC_pre\0" + /* 39802 */ "VSTR_FPSCR_NZCVQC_pre\0" + /* 39824 */ "VLDR_FPSCR_pre\0" + /* 39839 */ "VSTR_FPSCR_pre\0" + /* 39854 */ "VLDR_VPR_pre\0" + /* 39867 */ "VSTR_VPR_pre\0" + /* 39880 */ "VLDR_FPCXTNS_pre\0" + /* 39897 */ "VSTR_FPCXTNS_pre\0" + /* 39914 */ "VLDR_FPCXTS_pre\0" + /* 39930 */ "VSTR_FPCXTS_pre\0" + /* 39946 */ "MVE_VLDRWU32_qi_pre\0" + /* 39966 */ "MVE_VSTRW32_qi_pre\0" + /* 39985 */ "MVE_VSTRD64_qi_pre\0" + /* 40004 */ "MVE_VLDRDU64_qi_pre\0" + /* 40024 */ "t2LEUpdate\0" + /* 40035 */ "VCVTh2f\0" + /* 40043 */ "VPADDf\0" + /* 40050 */ "VRINTANDf\0" + /* 40060 */ "NEON_VMINNMNDf\0" + /* 40075 */ "NEON_VMAXNMNDf\0" + /* 40090 */ "VRINTMNDf\0" + /* 40100 */ "VRINTNNDf\0" + /* 40110 */ "VRINTPNDf\0" + /* 40120 */ "VRINTXNDf\0" + /* 40130 */ "VRINTZNDf\0" + /* 40140 */ "VCVTANSDf\0" + /* 40150 */ "VCVTMNSDf\0" + /* 40160 */ "VCVTNNSDf\0" + /* 40170 */ "VCVTPNSDf\0" + /* 40180 */ "VCVTANUDf\0" + /* 40190 */ "VCVTMNUDf\0" + /* 40200 */ "VCVTNNUDf\0" + /* 40210 */ "VCVTPNUDf\0" + /* 40220 */ "VPMINf\0" + /* 40227 */ "VRINTANQf\0" + /* 40237 */ "NEON_VMINNMNQf\0" + /* 40252 */ "NEON_VMAXNMNQf\0" + /* 40267 */ "VRINTMNQf\0" + /* 40277 */ "VRINTNNQf\0" + /* 40287 */ "VRINTPNQf\0" + /* 40297 */ "VRINTXNQf\0" + /* 40307 */ "VRINTZNQf\0" + /* 40317 */ "VCVTANSQf\0" + /* 40327 */ "VCVTMNSQf\0" + /* 40337 */ "VCVTNNSQf\0" + /* 40347 */ "VCVTPNSQf\0" + /* 40357 */ "VCVTANUQf\0" + /* 40367 */ "VCVTMNUQf\0" + /* 40377 */ "VCVTNNUQf\0" + /* 40387 */ "VCVTPNUQf\0" + /* 40397 */ "VPMAXf\0" + /* 40404 */ "VLDR_P0_off\0" + /* 40416 */ "VSTR_P0_off\0" + /* 40428 */ "VLDR_FPSCR_NZCVQC_off\0" + /* 40450 */ "VSTR_FPSCR_NZCVQC_off\0" + /* 40472 */ "VLDR_FPSCR_off\0" + /* 40487 */ "VSTR_FPSCR_off\0" + /* 40502 */ "VLDR_VPR_off\0" + /* 40515 */ "VSTR_VPR_off\0" + /* 40528 */ "VLDR_FPCXTNS_off\0" + /* 40545 */ "VSTR_FPCXTNS_off\0" + /* 40562 */ "VLDR_FPCXTS_off\0" + /* 40578 */ "VSTR_FPCXTS_off\0" + /* 40594 */ "t2MOVsra_flag\0" + /* 40608 */ "t2MOVsrl_flag\0" + /* 40622 */ "tBX_RET_vararg\0" + /* 40637 */ "VCVTf2h\0" + /* 40645 */ "VPADDh\0" + /* 40652 */ "VRINTANDh\0" + /* 40662 */ "NEON_VMINNMNDh\0" + /* 40677 */ "NEON_VMAXNMNDh\0" + /* 40692 */ "VRINTMNDh\0" + /* 40702 */ "VRINTNNDh\0" + /* 40712 */ "VRINTPNDh\0" + /* 40722 */ "VRINTXNDh\0" + /* 40732 */ "VRINTZNDh\0" + /* 40742 */ "VCVTANSDh\0" + /* 40752 */ "VCVTMNSDh\0" + /* 40762 */ "VCVTNNSDh\0" + /* 40772 */ "VCVTPNSDh\0" + /* 40782 */ "VCVTANUDh\0" + /* 40792 */ "VCVTMNUDh\0" + /* 40802 */ "VCVTNNUDh\0" + /* 40812 */ "VCVTPNUDh\0" + /* 40822 */ "VPMINh\0" + /* 40829 */ "VRINTANQh\0" + /* 40839 */ "NEON_VMINNMNQh\0" + /* 40854 */ "NEON_VMAXNMNQh\0" + /* 40869 */ "VRINTMNQh\0" + /* 40879 */ "VRINTNNQh\0" + /* 40889 */ "VRINTPNQh\0" + /* 40899 */ "VRINTXNQh\0" + /* 40909 */ "VRINTZNQh\0" + /* 40919 */ "VCVTANSQh\0" + /* 40929 */ "VCVTMNSQh\0" + /* 40939 */ "VCVTNNSQh\0" + /* 40949 */ "VCVTPNSQh\0" + /* 40959 */ "VCVTANUQh\0" + /* 40969 */ "VCVTMNUQh\0" + /* 40979 */ "VCVTNNUQh\0" + /* 40989 */ "VCVTPNUQh\0" + /* 40999 */ "VPMAXh\0" + /* 41006 */ "MVE_VCVTf16f32bh\0" + /* 41023 */ "MVE_VRSHRNi32bh\0" + /* 41039 */ "MVE_VSHRNi32bh\0" + /* 41054 */ "MVE_VMOVNi32bh\0" + /* 41069 */ "MVE_VQDMULLs32bh\0" + /* 41086 */ "MVE_VQSHRUNs32bh\0" + /* 41103 */ "MVE_VQRSHRUNs32bh\0" + /* 41121 */ "MVE_VQMOVUNs32bh\0" + /* 41138 */ "MVE_VQMOVNs32bh\0" + /* 41154 */ "MVE_VQDMULL_qr_s32bh\0" + /* 41175 */ "MVE_VQMOVNu32bh\0" + /* 41191 */ "MVE_VCVTf32f16bh\0" + /* 41208 */ "MVE_VRSHRNi16bh\0" + /* 41224 */ "MVE_VSHRNi16bh\0" + /* 41239 */ "MVE_VMOVNi16bh\0" + /* 41254 */ "MVE_VQDMULLs16bh\0" + /* 41271 */ "MVE_VMOVLs16bh\0" + /* 41286 */ "MVE_VQSHRUNs16bh\0" + /* 41303 */ "MVE_VQRSHRUNs16bh\0" + /* 41321 */ "MVE_VQMOVUNs16bh\0" + /* 41338 */ "MVE_VQMOVNs16bh\0" + /* 41354 */ "MVE_VQDMULL_qr_s16bh\0" + /* 41375 */ "MVE_VSHLL_imms16bh\0" + /* 41394 */ "MVE_VSHLL_lws16bh\0" + /* 41412 */ "MVE_VMOVLu16bh\0" + /* 41427 */ "MVE_VQMOVNu16bh\0" + /* 41443 */ "MVE_VSHLL_immu16bh\0" + /* 41462 */ "MVE_VSHLL_lwu16bh\0" + /* 41480 */ "MVE_VMOVLs8bh\0" + /* 41494 */ "MVE_VSHLL_imms8bh\0" + /* 41512 */ "MVE_VSHLL_lws8bh\0" + /* 41529 */ "MVE_VMOVLu8bh\0" + /* 41543 */ "MVE_VSHLL_immu8bh\0" + /* 41561 */ "MVE_VSHLL_lwu8bh\0" + /* 41578 */ "Int_eh_sjlj_setup_dispatch\0" + /* 41605 */ "MVE_VCVTf16f32th\0" + /* 41622 */ "MVE_VRSHRNi32th\0" + /* 41638 */ "MVE_VSHRNi32th\0" + /* 41653 */ "MVE_VMOVNi32th\0" + /* 41668 */ "MVE_VQDMULLs32th\0" + /* 41685 */ "MVE_VQSHRUNs32th\0" + /* 41702 */ "MVE_VQRSHRUNs32th\0" + /* 41720 */ "MVE_VQMOVUNs32th\0" + /* 41737 */ "MVE_VQMOVNs32th\0" + /* 41753 */ "MVE_VQDMULL_qr_s32th\0" + /* 41774 */ "MVE_VQMOVNu32th\0" + /* 41790 */ "MVE_VCVTf32f16th\0" + /* 41807 */ "MVE_VRSHRNi16th\0" + /* 41823 */ "MVE_VSHRNi16th\0" + /* 41838 */ "MVE_VMOVNi16th\0" + /* 41853 */ "MVE_VQDMULLs16th\0" + /* 41870 */ "MVE_VMOVLs16th\0" + /* 41885 */ "MVE_VQSHRUNs16th\0" + /* 41902 */ "MVE_VQRSHRUNs16th\0" + /* 41920 */ "MVE_VQMOVUNs16th\0" + /* 41937 */ "MVE_VQMOVNs16th\0" + /* 41953 */ "MVE_VQDMULL_qr_s16th\0" + /* 41974 */ "MVE_VSHLL_imms16th\0" + /* 41993 */ "MVE_VSHLL_lws16th\0" + /* 42011 */ "MVE_VMOVLu16th\0" + /* 42026 */ "MVE_VQMOVNu16th\0" + /* 42042 */ "MVE_VSHLL_immu16th\0" + /* 42061 */ "MVE_VSHLL_lwu16th\0" + /* 42079 */ "MVE_VMOVLs8th\0" + /* 42093 */ "MVE_VSHLL_imms8th\0" + /* 42111 */ "MVE_VSHLL_lws8th\0" + /* 42128 */ "MVE_VMOVLu8th\0" + /* 42142 */ "MVE_VSHLL_immu8th\0" + /* 42160 */ "MVE_VSHLL_lwu8th\0" + /* 42177 */ "tLDRBi\0" + /* 42184 */ "tSTRBi\0" + /* 42191 */ "t2MVNCCi\0" + /* 42200 */ "t2MOVCCi\0" + /* 42209 */ "t2BFi\0" + /* 42215 */ "tLDRHi\0" + /* 42222 */ "tSTRHi\0" + /* 42229 */ "t2BFLi\0" + /* 42236 */ "MVE_LSLLi\0" + /* 42246 */ "MVE_ASRLi\0" + /* 42256 */ "LSLi\0" + /* 42261 */ "t2MVNi\0" + /* 42268 */ "tADDrSPi\0" + /* 42277 */ "tLDRi\0" + /* 42283 */ "RORi\0" + /* 42288 */ "ASRi\0" + /* 42293 */ "LSRi\0" + /* 42298 */ "MSRi\0" + /* 42303 */ "tSTRi\0" + /* 42309 */ "LDRSBTi\0" + /* 42317 */ "LDRHTi\0" + /* 42324 */ "STRHTi\0" + /* 42331 */ "LDRSHTi\0" + /* 42339 */ "t2MOVi\0" + /* 42346 */ "tBLXi\0" + /* 42352 */ "RRXi\0" + /* 42357 */ "t2LDRBpci\0" + /* 42367 */ "t2LDRSBpci\0" + /* 42378 */ "t2PLDpci\0" + /* 42387 */ "t2LDRHpci\0" + /* 42397 */ "t2LDRSHpci\0" + /* 42408 */ "t2PLIpci\0" + /* 42417 */ "t2LDRpci\0" + /* 42426 */ "tLDRpci\0" + /* 42434 */ "TCRETURNdi\0" + /* 42445 */ "LDRSBTii\0" + /* 42454 */ "LDRHTii\0" + /* 42462 */ "LDRSHTii\0" + /* 42471 */ "tSUBspi\0" + /* 42479 */ "tADDspi\0" + /* 42487 */ "tLDRspi\0" + /* 42495 */ "tSTRspi\0" + /* 42503 */ "MVE_VLDRWU32_qi\0" + /* 42519 */ "MVE_VSTRW32_qi\0" + /* 42534 */ "MVE_VSTRD64_qi\0" + /* 42549 */ "MVE_VLDRDU64_qi\0" + /* 42565 */ "t2RSBri\0" + /* 42573 */ "t2SUBri\0" + /* 42581 */ "t2SBCri\0" + /* 42589 */ "t2ADCri\0" + /* 42597 */ "t2BICri\0" + /* 42605 */ "RSCri\0" + /* 42611 */ "t2ADDri\0" + /* 42619 */ "t2ANDri\0" + /* 42627 */ "t2LSLri\0" + /* 42635 */ "tLSLri\0" + /* 42642 */ "t2CMNri\0" + /* 42650 */ "t2ORNri\0" + /* 42658 */ "TCRETURNri\0" + /* 42669 */ "t2CMPri\0" + /* 42677 */ "t2TEQri\0" + /* 42685 */ "t2EORri\0" + /* 42693 */ "t2RORri\0" + /* 42701 */ "t2ORRri\0" + /* 42709 */ "t2ASRri\0" + /* 42717 */ "tASRri\0" + /* 42724 */ "t2LSRri\0" + /* 42732 */ "tLSRri\0" + /* 42739 */ "t2RSBSri\0" + /* 42748 */ "t2SUBSri\0" + /* 42757 */ "t2ADDSri\0" + /* 42766 */ "tLSLSri\0" + /* 42774 */ "t2TSTri\0" + /* 42782 */ "MOVCCsi\0" + /* 42790 */ "MVNsi\0" + /* 42796 */ "t2MOVSsi\0" + /* 42805 */ "t2MOVsi\0" + /* 42813 */ "RSBrsi\0" + /* 42820 */ "SUBrsi\0" + /* 42827 */ "SBCrsi\0" + /* 42834 */ "ADCrsi\0" + /* 42841 */ "BICrsi\0" + /* 42848 */ "RSCrsi\0" + /* 42855 */ "ADDrsi\0" + /* 42862 */ "ANDrsi\0" + /* 42869 */ "CMPrsi\0" + /* 42876 */ "TEQrsi\0" + /* 42883 */ "EORrsi\0" + /* 42890 */ "ORRrsi\0" + /* 42897 */ "RSBSrsi\0" + /* 42905 */ "SUBSrsi\0" + /* 42913 */ "ADDSrsi\0" + /* 42921 */ "TSTrsi\0" + /* 42928 */ "CMNzrsi\0" + /* 42936 */ "TRAPNaCl\0" + /* 42945 */ "t2LEApcrel\0" + /* 42956 */ "tLEApcrel\0" + /* 42966 */ "t2LDRBpcrel\0" + /* 42978 */ "t2LDRSBpcrel\0" + /* 42991 */ "t2LDRHpcrel\0" + /* 43003 */ "t2LDRSHpcrel\0" + /* 43016 */ "t2LDRpcrel\0" + /* 43027 */ "t2MOVTi16_ga_pcrel\0" + /* 43046 */ "t2MOVi16_ga_pcrel\0" + /* 43064 */ "tLDRLIT_ga_pcrel\0" + /* 43081 */ "t2MOV_ga_pcrel\0" + /* 43096 */ "t2LDRConstPool\0" + /* 43111 */ "tLDRConstPool\0" + /* 43125 */ "t2MOVCClsl\0" + /* 43136 */ "MVE_VCVTs32f32m\0" + /* 43152 */ "MVE_VCVTu32f32m\0" + /* 43168 */ "MVE_VCVTs16f16m\0" + /* 43184 */ "MVE_VCVTu16f16m\0" + /* 43200 */ "t2SUBspImm\0" + /* 43211 */ "t2ADDspImm\0" + /* 43222 */ "t2MOVCCi32imm\0" + /* 43236 */ "t2MOVi32imm\0" + /* 43248 */ "t2LDR_PRE_imm\0" + /* 43262 */ "t2STR_PRE_imm\0" + /* 43276 */ "t2LDR_POST_imm\0" + /* 43291 */ "t2STR_POST_imm\0" + /* 43306 */ "ITasm\0" + /* 43312 */ "MVE_VCVTs32f32n\0" + /* 43328 */ "MVE_VCVTu32f32n\0" + /* 43344 */ "MVE_VCVTf32s32n\0" + /* 43360 */ "MVE_VCVTf32u32n\0" + /* 43376 */ "MVE_VCVTs16f16n\0" + /* 43392 */ "MVE_VCVTu16f16n\0" + /* 43408 */ "MVE_VCVTf16s16n\0" + /* 43424 */ "MVE_VCVTf16u16n\0" + /* 43440 */ "VLD3d32Pseudo\0" + /* 43454 */ "VST3d32Pseudo\0" + /* 43468 */ "VLD4d32Pseudo\0" + /* 43482 */ "VST4d32Pseudo\0" + /* 43496 */ "VLD2LNd32Pseudo\0" + /* 43512 */ "VST2LNd32Pseudo\0" + /* 43528 */ "VLD3LNd32Pseudo\0" + /* 43544 */ "VST3LNd32Pseudo\0" + /* 43560 */ "VLD4LNd32Pseudo\0" + /* 43576 */ "VST4LNd32Pseudo\0" + /* 43592 */ "VLD3DUPd32Pseudo\0" + /* 43609 */ "VLD4DUPd32Pseudo\0" + /* 43626 */ "VLD2q32Pseudo\0" + /* 43640 */ "VST2q32Pseudo\0" + /* 43654 */ "VLD1LNq32Pseudo\0" + /* 43670 */ "VST1LNq32Pseudo\0" + /* 43686 */ "VLD2LNq32Pseudo\0" + /* 43702 */ "VST2LNq32Pseudo\0" + /* 43718 */ "VLD3LNq32Pseudo\0" + /* 43734 */ "VST3LNq32Pseudo\0" + /* 43750 */ "VLD4LNq32Pseudo\0" + /* 43766 */ "VST4LNq32Pseudo\0" + /* 43782 */ "VTBL3Pseudo\0" + /* 43794 */ "VTBX3Pseudo\0" + /* 43806 */ "VTBL4Pseudo\0" + /* 43818 */ "VTBX4Pseudo\0" + /* 43830 */ "VLD3d16Pseudo\0" + /* 43844 */ "VST3d16Pseudo\0" + /* 43858 */ "VLD4d16Pseudo\0" + /* 43872 */ "VST4d16Pseudo\0" + /* 43886 */ "VLD2LNd16Pseudo\0" + /* 43902 */ "VST2LNd16Pseudo\0" + /* 43918 */ "VLD3LNd16Pseudo\0" + /* 43934 */ "VST3LNd16Pseudo\0" + /* 43950 */ "VLD4LNd16Pseudo\0" + /* 43966 */ "VST4LNd16Pseudo\0" + /* 43982 */ "VLD3DUPd16Pseudo\0" + /* 43999 */ "VLD4DUPd16Pseudo\0" + /* 44016 */ "VLD2q16Pseudo\0" + /* 44030 */ "VST2q16Pseudo\0" + /* 44044 */ "VLD1LNq16Pseudo\0" + /* 44060 */ "VST1LNq16Pseudo\0" + /* 44076 */ "VLD2LNq16Pseudo\0" + /* 44092 */ "VST2LNq16Pseudo\0" + /* 44108 */ "VLD3LNq16Pseudo\0" + /* 44124 */ "VST3LNq16Pseudo\0" + /* 44140 */ "VLD4LNq16Pseudo\0" + /* 44156 */ "VST4LNq16Pseudo\0" + /* 44172 */ "VLD3d8Pseudo\0" + /* 44185 */ "VST3d8Pseudo\0" + /* 44198 */ "VLD4d8Pseudo\0" + /* 44211 */ "VST4d8Pseudo\0" + /* 44224 */ "VLD2LNd8Pseudo\0" + /* 44239 */ "VST2LNd8Pseudo\0" + /* 44254 */ "VLD3LNd8Pseudo\0" + /* 44269 */ "VST3LNd8Pseudo\0" + /* 44284 */ "VLD4LNd8Pseudo\0" + /* 44299 */ "VST4LNd8Pseudo\0" + /* 44314 */ "VLD3DUPd8Pseudo\0" + /* 44330 */ "VLD4DUPd8Pseudo\0" + /* 44346 */ "VLD2q8Pseudo\0" + /* 44359 */ "VST2q8Pseudo\0" + /* 44372 */ "VLD1LNq8Pseudo\0" + /* 44387 */ "VST1LNq8Pseudo\0" + /* 44402 */ "VLD1d32QPseudo\0" + /* 44417 */ "VST1d32QPseudo\0" + /* 44432 */ "VLD1d64QPseudo\0" + /* 44447 */ "VST1d64QPseudo\0" + /* 44462 */ "VLD1d16QPseudo\0" + /* 44477 */ "VST1d16QPseudo\0" + /* 44492 */ "VLD1d8QPseudo\0" + /* 44506 */ "VST1d8QPseudo\0" + /* 44520 */ "VLD1q32HighQPseudo\0" + /* 44539 */ "VST1q32HighQPseudo\0" + /* 44558 */ "VLD1q64HighQPseudo\0" + /* 44577 */ "VST1q64HighQPseudo\0" + /* 44596 */ "VLD1q16HighQPseudo\0" + /* 44615 */ "VST1q16HighQPseudo\0" + /* 44634 */ "VLD1q8HighQPseudo\0" + /* 44652 */ "VST1q8HighQPseudo\0" + /* 44670 */ "VLD1d32TPseudo\0" + /* 44685 */ "VST1d32TPseudo\0" + /* 44700 */ "VLD1d64TPseudo\0" + /* 44715 */ "VST1d64TPseudo\0" + /* 44730 */ "VLD1d16TPseudo\0" + /* 44745 */ "VST1d16TPseudo\0" + /* 44760 */ "VLD1d8TPseudo\0" + /* 44774 */ "VST1d8TPseudo\0" + /* 44788 */ "VLD1q32HighTPseudo\0" + /* 44807 */ "VST1q32HighTPseudo\0" + /* 44826 */ "VLD1q64HighTPseudo\0" + /* 44845 */ "VST1q64HighTPseudo\0" + /* 44864 */ "VLD1q16HighTPseudo\0" + /* 44883 */ "VST1q16HighTPseudo\0" + /* 44902 */ "VLD1q8HighTPseudo\0" + /* 44920 */ "VST1q8HighTPseudo\0" + /* 44938 */ "VLD2DUPq32OddPseudo\0" + /* 44958 */ "VLD3DUPq32OddPseudo\0" + /* 44978 */ "VLD4DUPq32OddPseudo\0" + /* 44998 */ "VLD2DUPq16OddPseudo\0" + /* 45018 */ "VLD3DUPq16OddPseudo\0" + /* 45038 */ "VLD4DUPq16OddPseudo\0" + /* 45058 */ "VLD2DUPq8OddPseudo\0" + /* 45077 */ "VLD3DUPq8OddPseudo\0" + /* 45096 */ "VLD4DUPq8OddPseudo\0" + /* 45115 */ "VLD3q32oddPseudo\0" + /* 45132 */ "VST3q32oddPseudo\0" + /* 45149 */ "VLD4q32oddPseudo\0" + /* 45166 */ "VST4q32oddPseudo\0" + /* 45183 */ "VLD3q16oddPseudo\0" + /* 45200 */ "VST3q16oddPseudo\0" + /* 45217 */ "VLD4q16oddPseudo\0" + /* 45234 */ "VST4q16oddPseudo\0" + /* 45251 */ "VLD3q8oddPseudo\0" + /* 45267 */ "VST3q8oddPseudo\0" + /* 45283 */ "VLD4q8oddPseudo\0" + /* 45299 */ "VST4q8oddPseudo\0" + /* 45315 */ "t2BF_LabelPseudo\0" + /* 45332 */ "VLD2DUPq32EvenPseudo\0" + /* 45353 */ "VLD3DUPq32EvenPseudo\0" + /* 45374 */ "VLD4DUPq32EvenPseudo\0" + /* 45395 */ "VLD2DUPq16EvenPseudo\0" + /* 45416 */ "VLD3DUPq16EvenPseudo\0" + /* 45437 */ "VLD4DUPq16EvenPseudo\0" + /* 45458 */ "VLD2DUPq8EvenPseudo\0" + /* 45478 */ "VLD3DUPq8EvenPseudo\0" + /* 45498 */ "VLD4DUPq8EvenPseudo\0" + /* 45518 */ "tMOVCCr_pseudo\0" + /* 45533 */ "t2CPS1p\0" + /* 45541 */ "MVE_VCVTs32f32p\0" + /* 45557 */ "MVE_VCVTu32f32p\0" + /* 45573 */ "t2CPS2p\0" + /* 45581 */ "t2CPS3p\0" + /* 45589 */ "MVE_VCVTs16f16p\0" + /* 45605 */ "MVE_VCVTu16f16p\0" + /* 45621 */ "LDRcp\0" + /* 45627 */ "CDE_VCX1_fpdp\0" + /* 45641 */ "CDE_VCX2_fpdp\0" + /* 45655 */ "CDE_VCX3_fpdp\0" + /* 45669 */ "CDE_VCX1A_fpdp\0" + /* 45684 */ "CDE_VCX2A_fpdp\0" + /* 45699 */ "CDE_VCX3A_fpdp\0" + /* 45714 */ "t2Int_eh_sjlj_setjmp_nofp\0" + /* 45740 */ "BLX_noip\0" + /* 45749 */ "BLX_pred_noip\0" + /* 45763 */ "tBLXr_noip\0" + /* 45774 */ "tInt_WIN_eh_sjlj_longjmp\0" + /* 45799 */ "tInt_eh_sjlj_longjmp\0" + /* 45820 */ "t2Int_eh_sjlj_setjmp\0" + /* 45841 */ "tInt_eh_sjlj_setjmp\0" + /* 45861 */ "CDE_VCX1_fpsp\0" + /* 45875 */ "CDE_VCX2_fpsp\0" + /* 45889 */ "CDE_VCX3_fpsp\0" + /* 45903 */ "CDE_VCX1A_fpsp\0" + /* 45918 */ "CDE_VCX2A_fpsp\0" + /* 45933 */ "CDE_VCX3A_fpsp\0" + /* 45948 */ "t2WhileLoopSetup\0" + /* 45965 */ "Int_eh_sjlj_dispatchsetup\0" + /* 45991 */ "VDUPLN32q\0" + /* 46001 */ "VDUP32q\0" + /* 46009 */ "VNEGf32q\0" + /* 46018 */ "VNEGs32q\0" + /* 46027 */ "VDUPLN16q\0" + /* 46037 */ "VDUP16q\0" + /* 46045 */ "VNEGs16q\0" + /* 46054 */ "VDUPLN8q\0" + /* 46063 */ "VDUP8q\0" + /* 46070 */ "VNEGs8q\0" + /* 46078 */ "VBICq\0" + /* 46084 */ "VANDq\0" + /* 46090 */ "VRECPEq\0" + /* 46098 */ "VRSQRTEq\0" + /* 46107 */ "VBIFq\0" + /* 46113 */ "VBSLq\0" + /* 46119 */ "VORNq\0" + /* 46125 */ "VMVNq\0" + /* 46131 */ "VBSPq\0" + /* 46137 */ "VSWPq\0" + /* 46143 */ "VEORq\0" + /* 46149 */ "VORRq\0" + /* 46155 */ "VBITq\0" + /* 46161 */ "VCNTq\0" + /* 46167 */ "MVE_VMOV_rr_q\0" + /* 46181 */ "VCVTs2fq\0" + /* 46190 */ "VCVTxs2fq\0" + /* 46200 */ "VCVTu2fq\0" + /* 46209 */ "VCVTxu2fq\0" + /* 46219 */ "VMLAfq\0" + /* 46226 */ "VFMAfq\0" + /* 46233 */ "VSUBfq\0" + /* 46240 */ "VABDfq\0" + /* 46247 */ "VADDfq\0" + /* 46254 */ "VACGEfq\0" + /* 46262 */ "VCGEfq\0" + /* 46269 */ "VRECPEfq\0" + /* 46278 */ "VRSQRTEfq\0" + /* 46288 */ "VMULfq\0" + /* 46295 */ "VMINfq\0" + /* 46302 */ "VCEQfq\0" + /* 46309 */ "VABSfq\0" + /* 46316 */ "VMLSfq\0" + /* 46323 */ "VFMSfq\0" + /* 46330 */ "VRECPSfq\0" + /* 46339 */ "VRSQRTSfq\0" + /* 46349 */ "VACGTfq\0" + /* 46357 */ "VCGTfq\0" + /* 46364 */ "VMAXfq\0" + /* 46371 */ "VMLAslfq\0" + /* 46380 */ "VMULslfq\0" + /* 46389 */ "VMLSslfq\0" + /* 46398 */ "VCVTs2hq\0" + /* 46407 */ "VCVTxs2hq\0" + /* 46417 */ "VCVTu2hq\0" + /* 46426 */ "VCVTxu2hq\0" + /* 46436 */ "VMLAhq\0" + /* 46443 */ "VFMAhq\0" + /* 46450 */ "VSUBhq\0" + /* 46457 */ "VABDhq\0" + /* 46464 */ "VADDhq\0" + /* 46471 */ "VACGEhq\0" + /* 46479 */ "VCGEhq\0" + /* 46486 */ "VRECPEhq\0" + /* 46495 */ "VRSQRTEhq\0" + /* 46505 */ "VNEGhq\0" + /* 46512 */ "VMULhq\0" + /* 46519 */ "VMINhq\0" + /* 46526 */ "VCEQhq\0" + /* 46533 */ "VABShq\0" + /* 46540 */ "VMLShq\0" + /* 46547 */ "VFMShq\0" + /* 46554 */ "VRECPShq\0" + /* 46563 */ "VRSQRTShq\0" + /* 46573 */ "VACGThq\0" + /* 46581 */ "VCGThq\0" + /* 46588 */ "VMAXhq\0" + /* 46595 */ "VMLAslhq\0" + /* 46604 */ "VMULslhq\0" + /* 46613 */ "VMLSslhq\0" + /* 46622 */ "VMULpq\0" + /* 46629 */ "MVE_VSTRB32_rq\0" + /* 46644 */ "MVE_VSTRH32_rq\0" + /* 46659 */ "MVE_VLDRBS32_rq\0" + /* 46675 */ "MVE_VLDRHS32_rq\0" + /* 46691 */ "MVE_VLDRBU32_rq\0" + /* 46707 */ "MVE_VLDRHU32_rq\0" + /* 46723 */ "MVE_VLDRWU32_rq\0" + /* 46739 */ "MVE_VSTRW32_rq\0" + /* 46754 */ "MVE_VSTRD64_rq\0" + /* 46769 */ "MVE_VLDRDU64_rq\0" + /* 46785 */ "MVE_VSTRB16_rq\0" + /* 46800 */ "MVE_VSTRH16_rq\0" + /* 46815 */ "MVE_VLDRBS16_rq\0" + /* 46831 */ "MVE_VLDRBU16_rq\0" + /* 46847 */ "MVE_VLDRHU16_rq\0" + /* 46863 */ "MVE_VSTRB8_rq\0" + /* 46877 */ "MVE_VLDRBU8_rq\0" + /* 46892 */ "VCVTf2sq\0" + /* 46901 */ "VCVTh2sq\0" + /* 46910 */ "VCVTf2xsq\0" + /* 46920 */ "VCVTh2xsq\0" + /* 46930 */ "VCVTf2uq\0" + /* 46939 */ "VCVTh2uq\0" + /* 46948 */ "VCVTf2xuq\0" + /* 46958 */ "VCVTh2xuq\0" + /* 46968 */ "MVE_VPTv4f32r\0" + /* 46982 */ "MVE_VCMPf32r\0" + /* 46995 */ "MVE_VPTv4i32r\0" + /* 47009 */ "MVE_VCMPi32r\0" + /* 47022 */ "MVE_VPTv4s32r\0" + /* 47036 */ "MVE_VCMPs32r\0" + /* 47049 */ "MVE_VPTv4u32r\0" + /* 47063 */ "MVE_VCMPu32r\0" + /* 47076 */ "MVE_VPTv8f16r\0" + /* 47090 */ "MVE_VCMPf16r\0" + /* 47103 */ "MVE_VPTv8i16r\0" + /* 47117 */ "MVE_VCMPi16r\0" + /* 47130 */ "MVE_VPTv8s16r\0" + /* 47144 */ "MVE_VCMPs16r\0" + /* 47157 */ "MVE_VPTv8u16r\0" + /* 47171 */ "MVE_VCMPu16r\0" + /* 47184 */ "MVE_VPTv16i8r\0" + /* 47198 */ "MVE_VCMPi8r\0" + /* 47210 */ "MVE_VPTv16s8r\0" + /* 47224 */ "MVE_VCMPs8r\0" + /* 47236 */ "MVE_VPTv16u8r\0" + /* 47250 */ "MVE_VCMPu8r\0" + /* 47262 */ "tLDRBr\0" + /* 47269 */ "tSTRBr\0" + /* 47276 */ "t2MOVCCr\0" + /* 47285 */ "t2BFr\0" + /* 47291 */ "tLDRHr\0" + /* 47298 */ "tSTRHr\0" + /* 47305 */ "t2BFLr\0" + /* 47312 */ "MVE_LSLLr\0" + /* 47322 */ "MVE_ASRLr\0" + /* 47332 */ "LSLr\0" + /* 47337 */ "t2MVNr\0" + /* 47344 */ "tCMPr\0" + /* 47350 */ "tTAILJMPr\0" + /* 47360 */ "tLDRr\0" + /* 47366 */ "RORr\0" + /* 47371 */ "ASRr\0" + /* 47376 */ "LSRr\0" + /* 47381 */ "tSTRr\0" + /* 47387 */ "tBLXNSr\0" + /* 47395 */ "tMOVSr\0" + /* 47402 */ "LDRSBTr\0" + /* 47410 */ "LDRHTr\0" + /* 47417 */ "STRHTr\0" + /* 47424 */ "LDRSHTr\0" + /* 47432 */ "tBR_JTr\0" + /* 47440 */ "t2MOVr\0" + /* 47447 */ "tMOVr\0" + /* 47453 */ "tBLXr\0" + /* 47459 */ "tBfar\0" + /* 47465 */ "LDRLIT_ga_pcrel_ldr\0" + /* 47485 */ "MOV_ga_pcrel_ldr\0" + /* 47502 */ "CompilerBarrier\0" + /* 47518 */ "VLD2q32PseudoWB_register\0" + /* 47543 */ "VST2q32PseudoWB_register\0" + /* 47568 */ "VLD2q16PseudoWB_register\0" + /* 47593 */ "VST2q16PseudoWB_register\0" + /* 47618 */ "VLD2q8PseudoWB_register\0" + /* 47642 */ "VST2q8PseudoWB_register\0" + /* 47666 */ "VLD1d32QPseudoWB_register\0" + /* 47692 */ "VST1d32QPseudoWB_register\0" + /* 47718 */ "VLD1d64QPseudoWB_register\0" + /* 47744 */ "VST1d64QPseudoWB_register\0" + /* 47770 */ "VLD1d16QPseudoWB_register\0" + /* 47796 */ "VST1d16QPseudoWB_register\0" + /* 47822 */ "VLD1d8QPseudoWB_register\0" + /* 47847 */ "VST1d8QPseudoWB_register\0" + /* 47872 */ "VLD1d32TPseudoWB_register\0" + /* 47898 */ "VST1d32TPseudoWB_register\0" + /* 47924 */ "VLD1d64TPseudoWB_register\0" + /* 47950 */ "VST1d64TPseudoWB_register\0" + /* 47976 */ "VLD1d16TPseudoWB_register\0" + /* 48002 */ "VST1d16TPseudoWB_register\0" + /* 48028 */ "VLD1d8TPseudoWB_register\0" + /* 48053 */ "VST1d8TPseudoWB_register\0" + /* 48078 */ "VLD2DUPq32OddPseudoWB_register\0" + /* 48109 */ "VLD2DUPq16OddPseudoWB_register\0" + /* 48140 */ "VLD2DUPq8OddPseudoWB_register\0" + /* 48170 */ "VLD2b32wb_register\0" + /* 48189 */ "VST2b32wb_register\0" + /* 48208 */ "VLD1d32wb_register\0" + /* 48227 */ "VST1d32wb_register\0" + /* 48246 */ "VLD2d32wb_register\0" + /* 48265 */ "VST2d32wb_register\0" + /* 48284 */ "VLD1DUPd32wb_register\0" + /* 48306 */ "VLD2DUPd32wb_register\0" + /* 48328 */ "VLD1q32wb_register\0" + /* 48347 */ "VST1q32wb_register\0" + /* 48366 */ "VLD2q32wb_register\0" + /* 48385 */ "VST2q32wb_register\0" + /* 48404 */ "VLD1DUPq32wb_register\0" + /* 48426 */ "VLD2DUPd32x2wb_register\0" + /* 48450 */ "VLD2DUPd16x2wb_register\0" + /* 48474 */ "VLD2DUPd8x2wb_register\0" + /* 48497 */ "VLD1d64wb_register\0" + /* 48516 */ "VST1d64wb_register\0" + /* 48535 */ "VLD1q64wb_register\0" + /* 48554 */ "VST1q64wb_register\0" + /* 48573 */ "VLD2b16wb_register\0" + /* 48592 */ "VST2b16wb_register\0" + /* 48611 */ "VLD1d16wb_register\0" + /* 48630 */ "VST1d16wb_register\0" + /* 48649 */ "VLD2d16wb_register\0" + /* 48668 */ "VST2d16wb_register\0" + /* 48687 */ "VLD1DUPd16wb_register\0" + /* 48709 */ "VLD2DUPd16wb_register\0" + /* 48731 */ "VLD1q16wb_register\0" + /* 48750 */ "VST1q16wb_register\0" + /* 48769 */ "VLD2q16wb_register\0" + /* 48788 */ "VST2q16wb_register\0" + /* 48807 */ "VLD1DUPq16wb_register\0" + /* 48829 */ "VLD2b8wb_register\0" + /* 48847 */ "VST2b8wb_register\0" + /* 48865 */ "VLD1d8wb_register\0" + /* 48883 */ "VST1d8wb_register\0" + /* 48901 */ "VLD2d8wb_register\0" + /* 48919 */ "VST2d8wb_register\0" + /* 48937 */ "VLD1DUPd8wb_register\0" + /* 48958 */ "VLD2DUPd8wb_register\0" + /* 48979 */ "VLD1q8wb_register\0" + /* 48997 */ "VST1q8wb_register\0" + /* 49015 */ "VLD2q8wb_register\0" + /* 49033 */ "VST2q8wb_register\0" + /* 49051 */ "VLD1DUPq8wb_register\0" + /* 49072 */ "VLD1d32Qwb_register\0" + /* 49092 */ "VST1d32Qwb_register\0" + /* 49112 */ "VLD1d64Qwb_register\0" + /* 49132 */ "VST1d64Qwb_register\0" + /* 49152 */ "VLD1d16Qwb_register\0" + /* 49172 */ "VST1d16Qwb_register\0" + /* 49192 */ "VLD1d8Qwb_register\0" + /* 49211 */ "VST1d8Qwb_register\0" + /* 49230 */ "VLD1d32Twb_register\0" + /* 49250 */ "VST1d32Twb_register\0" + /* 49270 */ "VLD1d64Twb_register\0" + /* 49290 */ "VST1d64Twb_register\0" + /* 49310 */ "VLD1d16Twb_register\0" + /* 49330 */ "VST1d16Twb_register\0" + /* 49350 */ "VLD1d8Twb_register\0" + /* 49369 */ "VST1d8Twb_register\0" + /* 49388 */ "tCMPhir\0" + /* 49396 */ "t2MOVCCror\0" + /* 49407 */ "tADDspr\0" + /* 49415 */ "t2RSBrr\0" + /* 49423 */ "t2SUBrr\0" + /* 49431 */ "tSUBrr\0" + /* 49438 */ "t2SBCrr\0" + /* 49446 */ "t2ADCrr\0" + /* 49454 */ "t2BICrr\0" + /* 49462 */ "RSCrr\0" + /* 49468 */ "t2ADDrr\0" + /* 49476 */ "tADDrr\0" + /* 49483 */ "t2ANDrr\0" + /* 49491 */ "t2LSLrr\0" + /* 49499 */ "tLSLrr\0" + /* 49506 */ "t2ORNrr\0" + /* 49514 */ "t2CMPrr\0" + /* 49522 */ "t2TEQrr\0" + /* 49530 */ "t2EORrr\0" + /* 49538 */ "t2RORrr\0" + /* 49546 */ "t2ORRrr\0" + /* 49554 */ "t2ASRrr\0" + /* 49562 */ "tASRrr\0" + /* 49569 */ "t2LSRrr\0" + /* 49577 */ "tLSRrr\0" + /* 49584 */ "t2SUBSrr\0" + /* 49593 */ "tSUBSrr\0" + /* 49601 */ "t2ADDSrr\0" + /* 49610 */ "tADDSrr\0" + /* 49618 */ "t2TSTrr\0" + /* 49626 */ "MVE_VMOV_q_rr\0" + /* 49640 */ "tADDhirr\0" + /* 49649 */ "t2CMNzrr\0" + /* 49658 */ "MOVCCsr\0" + /* 49666 */ "MVNsr\0" + /* 49672 */ "t2MOVSsr\0" + /* 49681 */ "t2MOVsr\0" + /* 49689 */ "t2MOVCCasr\0" + /* 49700 */ "t2MOVCClsr\0" + /* 49711 */ "RSBrsr\0" + /* 49718 */ "SUBrsr\0" + /* 49725 */ "SBCrsr\0" + /* 49732 */ "ADCrsr\0" + /* 49739 */ "BICrsr\0" + /* 49746 */ "RSCrsr\0" + /* 49753 */ "ADDrsr\0" + /* 49760 */ "ANDrsr\0" + /* 49767 */ "CMPrsr\0" + /* 49774 */ "TEQrsr\0" + /* 49781 */ "EORrsr\0" + /* 49788 */ "ORRrsr\0" + /* 49795 */ "RSBSrsr\0" + /* 49803 */ "SUBSrsr\0" + /* 49811 */ "ADDSrsr\0" + /* 49819 */ "TSTrsr\0" + /* 49826 */ "CMNzrsr\0" + /* 49834 */ "t2LDRBs\0" + /* 49842 */ "t2STRBs\0" + /* 49850 */ "t2LDRSBs\0" + /* 49859 */ "t2PLDs\0" + /* 49866 */ "t2LDRHs\0" + /* 49874 */ "t2STRHs\0" + /* 49882 */ "t2LDRSHs\0" + /* 49891 */ "t2PLIs\0" + /* 49898 */ "t2MVNs\0" + /* 49905 */ "t2LDRs\0" + /* 49912 */ "t2STRs\0" + /* 49919 */ "t2PLDWs\0" + /* 49927 */ "tLDRLIT_ga_abs\0" + /* 49942 */ "LDRBrs\0" + /* 49949 */ "STRBrs\0" + /* 49956 */ "t2RSBrs\0" + /* 49964 */ "t2SUBrs\0" + /* 49972 */ "t2SBCrs\0" + /* 49980 */ "t2ADCrs\0" + /* 49988 */ "t2BICrs\0" + /* 49996 */ "t2ADDrs\0" + /* 50004 */ "PLDrs\0" + /* 50010 */ "t2ANDrs\0" + /* 50018 */ "PLIrs\0" + /* 50024 */ "t2ORNrs\0" + /* 50032 */ "t2CMPrs\0" + /* 50040 */ "t2TEQrs\0" + /* 50048 */ "LDRrs\0" + /* 50054 */ "t2EORrs\0" + /* 50062 */ "t2ORRrs\0" + /* 50070 */ "STRrs\0" + /* 50076 */ "t2RSBSrs\0" + /* 50085 */ "t2SUBSrs\0" + /* 50094 */ "t2ADDSrs\0" + /* 50103 */ "t2TSTrs\0" + /* 50111 */ "PLDWrs\0" + /* 50118 */ "BR_JTm_rs\0" + /* 50128 */ "t2CMNzrs\0" + /* 50137 */ "MRSsys\0" + /* 50144 */ "tTPsoft\0" + /* 50152 */ "t2WhileLoopStart\0" + /* 50169 */ "t2DoLoopStart\0" + /* 50183 */ "VLDR_P0_post\0" + /* 50196 */ "VSTR_P0_post\0" + /* 50209 */ "MVE_VSTRB32_post\0" + /* 50226 */ "MVE_VSTRH32_post\0" + /* 50243 */ "MVE_VLDRBS32_post\0" + /* 50261 */ "MVE_VLDRHS32_post\0" + /* 50279 */ "MVE_VLDRBU32_post\0" + /* 50297 */ "MVE_VLDRHU32_post\0" + /* 50315 */ "MVE_VLDRWU32_post\0" + /* 50333 */ "MVE_VSTRWU32_post\0" + /* 50351 */ "MVE_VSTRB16_post\0" + /* 50368 */ "MVE_VLDRBS16_post\0" + /* 50386 */ "MVE_VLDRBU16_post\0" + /* 50404 */ "MVE_VLDRHU16_post\0" + /* 50422 */ "MVE_VSTRHU16_post\0" + /* 50440 */ "MVE_VLDRBU8_post\0" + /* 50457 */ "MVE_VSTRBU8_post\0" + /* 50474 */ "VLDR_FPSCR_NZCVQC_post\0" + /* 50497 */ "VSTR_FPSCR_NZCVQC_post\0" + /* 50520 */ "VLDR_FPSCR_post\0" + /* 50536 */ "VSTR_FPSCR_post\0" + /* 50552 */ "VLDR_VPR_post\0" + /* 50566 */ "VSTR_VPR_post\0" + /* 50580 */ "VLDR_FPCXTNS_post\0" + /* 50598 */ "VSTR_FPCXTNS_post\0" + /* 50616 */ "VLDR_FPCXTS_post\0" + /* 50633 */ "VSTR_FPCXTS_post\0" + /* 50650 */ "MVE_VSTRH32_rq_u\0" + /* 50667 */ "MVE_VLDRHS32_rq_u\0" + /* 50685 */ "MVE_VLDRHU32_rq_u\0" + /* 50703 */ "MVE_VLDRWU32_rq_u\0" + /* 50721 */ "MVE_VSTRW32_rq_u\0" + /* 50738 */ "MVE_VSTRD64_rq_u\0" + /* 50755 */ "MVE_VLDRDU64_rq_u\0" + /* 50773 */ "MVE_VSTRH16_rq_u\0" + /* 50790 */ "MVE_VLDRHU16_rq_u\0" + /* 50808 */ "t2STRB_preidx\0" + /* 50822 */ "t2STRH_preidx\0" + /* 50836 */ "t2STR_preidx\0" + /* 50849 */ "STRBi_preidx\0" + /* 50862 */ "STRi_preidx\0" + /* 50874 */ "STRBr_preidx\0" + /* 50887 */ "STRr_preidx\0" + /* 50899 */ "tLDR_postidx\0" + /* 50912 */ "MVE_VCVTs32f32_fix\0" + /* 50931 */ "MVE_VCVTu32f32_fix\0" + /* 50950 */ "MVE_VCVTf32s32_fix\0" + /* 50969 */ "MVE_VCVTf32u32_fix\0" + /* 50988 */ "MVE_VCVTs16f16_fix\0" + /* 51007 */ "MVE_VCVTu16f16_fix\0" + /* 51026 */ "MVE_VCVTf16s16_fix\0" + /* 51045 */ "MVE_VCVTf16u16_fix\0" + /* 51064 */ "MQPRCopy\0" + /* 51073 */ "MVE_VCVTs32f32z\0" + /* 51089 */ "MVE_VCVTu32f32z\0" + /* 51105 */ "MVE_VCVTs16f16z\0" + /* 51121 */ "MVE_VCVTu16f16z\0" + /* 51137 */ "tCMNz\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern const unsigned ARMInstrNameIndices[] = { + 30811U, 31745U, 32664U, 31995U, 31021U, 31002U, 31030U, 31304U, 29749U, + 29764U, 29701U, 29841U, 33616U, 29592U, 34801U, 29714U, 30807U, 31011U, + 29239U, 35830U, 29316U, 34713U, 24953U, 29184U, 29227U, 32254U, 31258U, + 34626U, 28819U, 32430U, 30016U, 34615U, 29339U, 32341U, 32328U, 32714U, + 34236U, 34435U, 31155U, 31214U, 31187U, 31047U, 35249U, 35279U, 24665U, + 24032U, 31470U, 35332U, 35346U, 31542U, 31549U, 31556U, 31566U, 24918U, + 33023U, 32986U, 29699U, 30809U, 35644U, 29602U, 34187U, 33249U, 34735U, + 33266U, 32938U, 24250U, 33570U, 34637U, 33126U, 34774U, 29627U, 24224U, + 25009U, 34656U, 31856U, 32739U, 24521U, 24465U, 24495U, 24506U, 24446U, + 24476U, 29368U, 29352U, 33647U, 29967U, 29984U, 24681U, 24038U, 24924U, + 24876U, 33028U, 32992U, 35515U, 31972U, 35498U, 31955U, 24625U, 24008U, + 29219U, 24973U, 34206U, 24165U, 33735U, 35263U, 24242U, 34591U, 34579U, + 34703U, 30008U, 35242U, 29778U, 35272U, 31128U, 32805U, 32791U, 31090U, + 32798U, 33119U, 31368U, 32308U, 32301U, 34197U, 32188U, 29260U, 32172U, + 29205U, 32180U, 29252U, 32164U, 29197U, 32204U, 32196U, 30240U, 30232U, + 34016U, 34006U, 33996U, 33986U, 34036U, 34026U, 35718U, 35728U, 34060U, + 34073U, 35738U, 35748U, 34086U, 34099U, 24583U, 23987U, 31404U, 23569U, + 24432U, 35304U, 31521U, 35398U, 30907U, 32453U, 8321U, 30001U, 8291U, + 0U, 29734U, 35234U, 24214U, 30889U, 30898U, 32283U, 32292U, 33184U, + 31878U, 29636U, 31783U, 31793U, 29268U, 29283U, 31761U, 31772U, 24671U, + 30933U, 31924U, 35467U, 31948U, 35491U, 33191U, 25000U, 24990U, 32659U, + 34459U, 34554U, 34533U, 32953U, 35903U, 29681U, 35890U, 29663U, 32315U, + 32269U, 29579U, 31134U, 33451U, 31988U, 34744U, 32924U, 34648U, 34674U, + 34784U, 32694U, 29303U, 24271U, 24611U, 23994U, 31432U, 35311U, 31528U, + 23575U, 34752U, 32758U, 32774U, 35821U, 29323U, 29617U, 34389U, 32212U, + 24590U, 31411U, 24566U, 31387U, 35433U, 31890U, 24649U, 31454U, 24902U, + 33008U, 32970U, 35450U, 31907U, 35474U, 31931U, 35697U, 35711U, 33180U, + 42759U, 49603U, 42913U, 49811U, 32147U, 32415U, 42288U, 47371U, 23601U, + 9546U, 9539U, 45740U, 45749U, 32859U, 31142U, 31244U, 37188U, 244U, + 50118U, 47433U, 31236U, 10136U, 629U, 8510U, 18006U, 35835U, 325U, + 47502U, 43306U, 45965U, 45800U, 45822U, 45716U, 41578U, 33527U, 33777U, + 23664U, 30124U, 34226U, 35094U, 43098U, 42454U, 49928U, 43065U, 47465U, + 42445U, 42462U, 35116U, 42947U, 34510U, 30979U, 42256U, 47332U, 42293U, + 47376U, 35823U, 9624U, 42202U, 15066U, 43224U, 47278U, 42782U, 49658U, + 35762U, 43029U, 43083U, 47485U, 43048U, 43238U, 40596U, 40610U, 51064U, + 37166U, 39482U, 37176U, 39493U, 9662U, 34859U, 34840U, 42193U, 24551U, + 32707U, 23846U, 30365U, 23879U, 30502U, 33137U, 23854U, 30403U, 42283U, + 47366U, 35772U, 42352U, 42741U, 42897U, 49795U, 9630U, 9646U, 29213U, + 30988U, 35105U, 50849U, 50874U, 50824U, 35126U, 50862U, 50887U, 32880U, + 42750U, 49586U, 42905U, 49803U, 23680U, 23712U, 37121U, 47351U, 9614U, + 42434U, 42658U, 50145U, 9638U, 9654U, 11492U, 2007U, 19020U, 10278U, + 793U, 18140U, 10876U, 1391U, 18580U, 11520U, 2035U, 19046U, 10324U, + 839U, 18184U, 10928U, 1443U, 18630U, 11682U, 2197U, 10594U, 1109U, + 11234U, 1749U, 11604U, 2119U, 19124U, 10462U, 977U, 18316U, 11084U, + 1599U, 18780U, 11766U, 2281U, 19196U, 10732U, 1247U, 18442U, 11390U, + 1905U, 18924U, 11548U, 2063U, 19072U, 10370U, 885U, 18228U, 10980U, + 1495U, 18680U, 11710U, 2225U, 10640U, 1155U, 11286U, 1801U, 11444U, + 1959U, 18976U, 10194U, 709U, 18060U, 10780U, 1295U, 18488U, 11634U, + 2149U, 19152U, 10510U, 1025U, 18362U, 11138U, 1653U, 18832U, 11619U, + 2134U, 19138U, 10486U, 1001U, 18339U, 11111U, 1626U, 18806U, 11781U, + 2296U, 19210U, 10756U, 1271U, 18465U, 11417U, 1932U, 18950U, 11576U, + 2091U, 19098U, 10416U, 931U, 18272U, 11032U, 1547U, 18730U, 11738U, + 2253U, 10686U, 1201U, 11338U, 1853U, 11468U, 1983U, 18998U, 10236U, + 751U, 18100U, 10828U, 1343U, 18534U, 11658U, 2173U, 19174U, 10552U, + 1067U, 18402U, 11186U, 1701U, 18878U, 9U, 36549U, 36557U, 32U, + 36565U, 11506U, 2021U, 19033U, 10301U, 816U, 18162U, 10902U, 1417U, + 18605U, 11534U, 2049U, 19059U, 10347U, 862U, 18206U, 10954U, 1469U, + 18655U, 11696U, 2211U, 10617U, 1132U, 11260U, 1775U, 11562U, 2077U, + 19085U, 10393U, 908U, 18250U, 11006U, 1521U, 18705U, 11724U, 2239U, + 10663U, 1178U, 11312U, 1827U, 11456U, 1971U, 18987U, 10215U, 730U, + 18080U, 10804U, 1319U, 18511U, 11646U, 2161U, 19163U, 10531U, 1046U, + 18382U, 11162U, 1677U, 18855U, 11590U, 2105U, 19111U, 10439U, 954U, + 18294U, 11058U, 1573U, 18755U, 11752U, 2267U, 10709U, 1224U, 11364U, + 1879U, 11480U, 1995U, 19009U, 10257U, 772U, 18120U, 10852U, 1367U, + 18557U, 11670U, 2185U, 19185U, 10573U, 1088U, 18422U, 11210U, 1725U, + 18901U, 30943U, 30921U, 33178U, 42757U, 49601U, 50094U, 45315U, 34500U, + 50169U, 32398U, 34224U, 42966U, 43096U, 42991U, 42978U, 43003U, 43276U, + 43248U, 36964U, 43016U, 42945U, 34508U, 36866U, 39379U, 36853U, 49689U, + 42200U, 15064U, 43222U, 43125U, 49700U, 47276U, 49396U, 42796U, 49672U, + 43027U, 43081U, 43046U, 43236U, 42805U, 49681U, 42191U, 42739U, 50076U, + 50808U, 50822U, 43291U, 43262U, 50836U, 42748U, 49584U, 50085U, 23678U, + 23710U, 34466U, 34483U, 45948U, 50152U, 32891U, 32379U, 33215U, 8491U, + 21344U, 49610U, 39472U, 32146U, 32414U, 31175U, 45763U, 32858U, 24966U, + 47432U, 34259U, 31235U, 34269U, 40622U, 47459U, 10135U, 18005U, 26152U, + 43111U, 49927U, 43064U, 50899U, 36977U, 42956U, 34521U, 42766U, 45518U, + 34250U, 33197U, 33209U, 8483U, 21336U, 49593U, 37120U, 25027U, 47350U, + 34475U, 34492U, 50144U, 42591U, 49448U, 42834U, 49732U, 42613U, 49470U, + 42855U, 49753U, 32685U, 28894U, 29574U, 24187U, 24200U, 42621U, 49485U, + 42862U, 49760U, 29010U, 32588U, 29026U, 32604U, 35206U, 23942U, 35189U, + 24147U, 30803U, 42599U, 49456U, 42841U, 49739U, 34698U, 30999U, 35758U, + 37237U, 42347U, 37221U, 35577U, 30917U, 34270U, 37229U, 36540U, 128U, + 23285U, 24378U, 23340U, 8395U, 23308U, 24387U, 23350U, 8461U, 23317U, + 24396U, 23360U, 45669U, 45903U, 36915U, 45627U, 45861U, 36876U, 45684U, + 45918U, 36929U, 45641U, 45875U, 36889U, 45699U, 45933U, 36943U, 45655U, + 45889U, 36902U, 32279U, 8316U, 35676U, 35886U, 42644U, 49651U, 42928U, + 49826U, 42671U, 49516U, 42869U, 49767U, 45535U, 45575U, 45583U, 23596U, + 23740U, 30146U, 35390U, 30046U, 35363U, 29730U, 23837U, 23869U, 42687U, + 49532U, 42883U, 49781U, 34219U, 29049U, 30570U, 33793U, 26379U, 23511U, + 26235U, 34112U, 26391U, 23519U, 26247U, 34604U, 34575U, 24347U, 23875U, + 23378U, 23609U, 35638U, 24074U, 29103U, 30650U, 30063U, 34333U, 32067U, + 35024U, 29510U, 34279U, 32013U, 34880U, 29378U, 34363U, 32097U, 35050U, + 29534U, 34307U, 32041U, 34941U, 29434U, 23385U, 26060U, 23758U, 26295U, + 23432U, 26129U, 23807U, 26416U, 31680U, 29909U, 31626U, 29855U, 31576U, + 29791U, 138U, 49942U, 28837U, 34963U, 29454U, 35668U, 24092U, 29121U, + 30668U, 30368U, 42317U, 47410U, 34987U, 29476U, 23882U, 42309U, 47402U, + 34928U, 29422U, 30505U, 42331U, 47424U, 35011U, 29498U, 31710U, 29939U, + 31654U, 29883U, 31602U, 29817U, 45621U, 218U, 50048U, 32679U, 8331U, + 33063U, 8349U, 23529U, 33325U, 32850U, 15185U, 42341U, 15195U, 47442U, + 24337U, 42807U, 49683U, 24326U, 8278U, 24332U, 8285U, 33566U, 37211U, + 50137U, 33108U, 37199U, 42298U, 31383U, 42246U, 47322U, 10148U, 641U, + 8522U, 18017U, 32361U, 32370U, 42236U, 47312U, 31359U, 32812U, 31325U, + 31097U, 31270U, 32823U, 31337U, 31117U, 31292U, 31107U, 31281U, 32833U, + 31348U, 15948U, 6479U, 21974U, 17141U, 7773U, 22902U, 12286U, 2795U, + 15670U, 6175U, 21717U, 16951U, 7575U, 22727U, 12400U, 2909U, 15910U, + 6441U, 21939U, 24131U, 30741U, 36589U, 36720U, 36622U, 36759U, 36639U, + 36779U, 36573U, 36701U, 36671U, 36817U, 36655U, 36798U, 36606U, 36740U, + 36686U, 36835U, 12535U, 3044U, 15218U, 5761U, 21383U, 12311U, 2820U, + 15097U, 5649U, 21165U, 24893U, 24151U, 15250U, 5793U, 9854U, 369U, + 17787U, 12298U, 2807U, 15075U, 5627U, 21145U, 15922U, 6453U, 21950U, + 16168U, 6699U, 22149U, 12219U, 2728U, 12388U, 47090U, 2897U, 46982U, + 15171U, 47117U, 5733U, 47009U, 21302U, 47198U, 15885U, 47144U, 6416U, + 47036U, 21916U, 47224U, 17061U, 47171U, 7693U, 47063U, 22828U, 47250U, + 12335U, 2844U, 9832U, 347U, 8499U, 17767U, 41006U, 41605U, 51026U, + 43408U, 51045U, 43424U, 41191U, 41790U, 50950U, 43344U, 50969U, 43360U, + 50988U, 35942U, 43168U, 43376U, 45589U, 51105U, 50912U, 35910U, 43136U, + 43312U, 45541U, 51073U, 51007U, 35958U, 43184U, 43392U, 45605U, 51121U, + 50931U, 35926U, 43152U, 43328U, 45557U, 51089U, 17073U, 7705U, 22839U, + 9843U, 358U, 17777U, 17099U, 7731U, 22863U, 32910U, 12424U, 2933U, + 12503U, 3012U, 12232U, 2741U, 12412U, 2921U, 16253U, 6761U, 22229U, + 17305U, 7914U, 23040U, 15710U, 6215U, 21754U, 16977U, 7601U, 22751U, + 15682U, 6187U, 21728U, 16219U, 6727U, 22197U, 17271U, 7880U, 23008U, + 15644U, 6149U, 21693U, 16925U, 7549U, 22703U, 17086U, 7718U, 22851U, + 17113U, 7745U, 22876U, 9951U, 36166U, 459U, 35974U, 17822U, 36358U, + 10003U, 36230U, 511U, 36038U, 17870U, 36418U, 9977U, 36198U, 485U, + 36006U, 17846U, 36388U, 10029U, 36262U, 537U, 36070U, 17894U, 36448U, + 10069U, 36294U, 563U, 36102U, 17931U, 36478U, 10095U, 36326U, 589U, + 36134U, 17955U, 36508U, 9866U, 50368U, 39680U, 46815U, 381U, 50243U, + 39562U, 46659U, 9897U, 50386U, 39697U, 46831U, 407U, 50279U, 39596U, + 46691U, 17798U, 50440U, 39748U, 46877U, 42549U, 40004U, 46769U, 50755U, + 394U, 50261U, 39579U, 46675U, 50667U, 9910U, 50404U, 39714U, 46847U, + 50790U, 420U, 50297U, 39613U, 46707U, 50685U, 433U, 50315U, 39630U, + 42503U, 39946U, 46723U, 50703U, 16037U, 6568U, 22027U, 15617U, 6122U, + 21668U, 12457U, 2966U, 12259U, 2768U, 12488U, 2997U, 12374U, 2883U, + 16064U, 6595U, 22052U, 17198U, 7830U, 22940U, 16086U, 6617U, 22072U, + 17220U, 7852U, 22960U, 16023U, 6554U, 22014U, 15604U, 6109U, 21656U, + 12441U, 2950U, 12244U, 2753U, 12473U, 2982U, 12360U, 2869U, 16051U, + 6582U, 22040U, 17185U, 7817U, 22928U, 15863U, 6404U, 21896U, 17039U, + 7681U, 22808U, 16343U, 6889U, 22314U, 17356U, 7984U, 23088U, 16828U, + 7452U, 22645U, 15961U, 6492U, 21986U, 17154U, 7786U, 22914U, 16762U, + 7346U, 22615U, 16359U, 6905U, 17372U, 8000U, 16845U, 7469U, 15976U, + 6507U, 17169U, 7801U, 16778U, 7362U, 16326U, 6834U, 22298U, 17339U, + 7948U, 23072U, 16203U, 6711U, 22182U, 17255U, 7864U, 22993U, 16393U, + 6939U, 22329U, 16881U, 7505U, 22661U, 16008U, 6539U, 22000U, 16812U, + 7396U, 22630U, 16376U, 6922U, 16863U, 7487U, 15992U, 6523U, 16795U, + 7379U, 41271U, 41870U, 41480U, 42079U, 41412U, 42011U, 41529U, 42128U, + 41239U, 41838U, 41054U, 41653U, 667U, 16180U, 22160U, 17232U, 22971U, + 49626U, 46167U, 10174U, 689U, 18041U, 3076U, 15295U, 5838U, 9554U, + 21413U, 15841U, 6346U, 21876U, 17017U, 7641U, 22788U, 15354U, 21468U, + 15630U, 6135U, 21680U, 16911U, 7535U, 22690U, 15368U, 21489U, 15934U, + 6465U, 21961U, 17127U, 7759U, 22889U, 12551U, 3060U, 15234U, 5777U, + 21398U, 12348U, 2857U, 15149U, 5701U, 21282U, 32132U, 15265U, 5808U, + 12323U, 2832U, 15749U, 6254U, 21790U, 32123U, 33076U, 15280U, 5823U, + 34687U, 31080U, 35136U, 19583U, 47184U, 21643U, 47210U, 22677U, 47236U, + 2650U, 46968U, 4588U, 46995U, 6096U, 47022U, 7522U, 47049U, 12151U, + 47076U, 14025U, 47103U, 15591U, 47130U, 16898U, 47157U, 15897U, 6428U, + 21927U, 16270U, 6778U, 22245U, 17322U, 7931U, 23056U, 15723U, 6228U, + 21766U, 16990U, 7614U, 22763U, 16098U, 6629U, 22083U, 15761U, 6266U, + 21801U, 16622U, 7168U, 22483U, 16659U, 7205U, 22518U, 16133U, 6664U, + 22116U, 15794U, 6299U, 21832U, 16287U, 6795U, 22261U, 15109U, 5661U, + 21209U, 41354U, 41953U, 41154U, 41753U, 41254U, 41853U, 41069U, 41668U, + 41338U, 41937U, 41138U, 41737U, 41427U, 42026U, 41175U, 41774U, 41321U, + 41920U, 41121U, 41720U, 15736U, 6241U, 21778U, 16115U, 6646U, 22099U, + 15777U, 6282U, 21816U, 16640U, 7186U, 22500U, 16678U, 7224U, 22536U, + 16150U, 6681U, 22132U, 15810U, 6315U, 21847U, 16306U, 6814U, 22279U, + 15124U, 5676U, 21223U, 16429U, 6975U, 22363U, 17409U, 8037U, 23122U, + 16714U, 7260U, 22570U, 17600U, 8228U, 23240U, 16505U, 7051U, 17485U, + 8113U, 16538U, 7084U, 17518U, 8146U, 41303U, 41902U, 41103U, 41702U, + 16604U, 7150U, 22466U, 16409U, 6955U, 22344U, 17389U, 8017U, 23103U, + 16698U, 7244U, 22555U, 17584U, 8212U, 23225U, 16555U, 7101U, 22420U, + 17535U, 8163U, 23179U, 16489U, 7035U, 17469U, 8097U, 16522U, 7068U, + 17502U, 8130U, 41286U, 41885U, 41086U, 41685U, 16236U, 6744U, 22213U, + 17288U, 7897U, 23024U, 15657U, 6162U, 21705U, 16938U, 7562U, 22715U, + 17992U, 10055U, 17918U, 10121U, 615U, 17979U, 15696U, 6201U, 21741U, + 16963U, 7587U, 22738U, 23326U, 31501U, 31833U, 32240U, 35419U, 35865U, + 23294U, 31487U, 31819U, 32226U, 35405U, 35851U, 6851U, 7965U, 7412U, + 6359U, 7654U, 7308U, 6870U, 7432U, 6377U, 7327U, 15827U, 6332U, + 21863U, 17003U, 7627U, 22775U, 16450U, 6996U, 22383U, 17430U, 8058U, + 23142U, 16731U, 7277U, 22586U, 17617U, 8245U, 23256U, 41208U, 41807U, + 41023U, 41622U, 16571U, 7117U, 22435U, 17551U, 8179U, 23194U, 24117U, + 30731U, 24177U, 41375U, 41974U, 41494U, 42093U, 41443U, 42042U, 41543U, + 42142U, 41394U, 41993U, 41512U, 42111U, 41462U, 42061U, 41561U, 42160U, + 16470U, 7016U, 22402U, 17450U, 8078U, 23161U, 15310U, 5853U, 21427U, + 16747U, 7293U, 22601U, 17633U, 8261U, 23271U, 41224U, 41823U, 41039U, + 41638U, 16588U, 7134U, 22451U, 17568U, 8196U, 23210U, 15326U, 5869U, + 21442U, 15340U, 5883U, 21455U, 9964U, 36182U, 472U, 35990U, 17834U, + 36373U, 10016U, 36246U, 524U, 36054U, 17882U, 36433U, 9990U, 36214U, + 498U, 36022U, 17858U, 36403U, 10042U, 36278U, 550U, 36086U, 17906U, + 36463U, 10082U, 36310U, 576U, 36118U, 17943U, 36493U, 10108U, 36342U, + 602U, 36150U, 17967U, 36523U, 9688U, 50351U, 39664U, 46785U, 301U, + 50209U, 39530U, 46629U, 46863U, 17810U, 50457U, 39764U, 42534U, 39985U, + 46754U, 50738U, 46800U, 50773U, 313U, 50226U, 39546U, 46644U, 50650U, + 9923U, 50422U, 39731U, 42519U, 39966U, 46739U, 50721U, 446U, 50333U, + 39647U, 12519U, 3028U, 15202U, 5745U, 21368U, 12274U, 2783U, 15052U, + 5615U, 21127U, 10161U, 654U, 8535U, 18029U, 42263U, 47339U, 42790U, + 49666U, 40075U, 40677U, 40252U, 40854U, 40060U, 40662U, 40237U, 40839U, + 42703U, 49548U, 42890U, 49788U, 34137U, 23917U, 236U, 50111U, 169U, + 50004U, 209U, 50018U, 24644U, 9797U, 17736U, 35794U, 24560U, 23981U, + 35549U, 24027U, 9740U, 17677U, 34430U, 35295U, 9938U, 30534U, 23370U, + 26047U, 23750U, 26283U, 23424U, 26117U, 23798U, 26403U, 42567U, 49417U, + 42813U, 49711U, 42605U, 49462U, 42848U, 49746U, 9816U, 17753U, 35809U, + 23864U, 42583U, 49440U, 42827U, 49725U, 35692U, 35327U, 31069U, 24946U, + 31849U, 24111U, 30038U, 31481U, 32220U, 50U, 104U, 30053U, 8299U, + 58U, 112U, 9777U, 17718U, 35778U, 35533U, 9720U, 17659U, 24196U, + 23632U, 34128U, 24414U, 35582U, 30965U, 23641U, 34145U, 24778U, 35600U, + 23925U, 35166U, 23908U, 35157U, 24056U, 35218U, 28908U, 35620U, 24794U, + 35610U, 23535U, 32622U, 33331U, 33100U, 31448U, 32871U, 24538U, 35591U, + 23651U, 34155U, 31311U, 23935U, 35176U, 24065U, 35227U, 28966U, 35629U, + 23400U, 26083U, 23792U, 26369U, 23505U, 26225U, 23822U, 26439U, 34048U, + 9881U, 35564U, 9759U, 17694U, 34348U, 32082U, 35037U, 29522U, 34293U, + 32027U, 34892U, 29389U, 34377U, 32111U, 35062U, 29545U, 34320U, 32054U, + 34952U, 29444U, 31377U, 23830U, 35660U, 24083U, 29112U, 30659U, 30220U, + 23394U, 26073U, 23775U, 26320U, 23456U, 26165U, 23816U, 26429U, 31695U, + 29924U, 31640U, 29869U, 31589U, 29804U, 148U, 49949U, 28875U, 34975U, + 29465U, 35684U, 24101U, 29130U, 30677U, 30406U, 42324U, 47417U, 34999U, + 29487U, 31724U, 29953U, 31667U, 29896U, 31614U, 29829U, 227U, 50070U, + 42575U, 49425U, 42820U, 49718U, 24352U, 32449U, 23841U, 23616U, 9670U, + 30104U, 23955U, 9702U, 30580U, 42679U, 49524U, 42876U, 49774U, 32264U, + 42936U, 23902U, 42776U, 49620U, 42921U, 49819U, 9825U, 17761U, 35816U, + 35706U, 29654U, 35341U, 9787U, 17727U, 35786U, 35541U, 9730U, 17668U, + 30957U, 30973U, 31319U, 9806U, 17744U, 35801U, 35556U, 9749U, 17685U, + 17710U, 17650U, 34055U, 9890U, 35571U, 9768U, 17702U, 23624U, 9680U, + 30112U, 23968U, 9711U, 30593U, 9073U, 4906U, 14343U, 9323U, 5285U, + 14722U, 19663U, 3622U, 13098U, 4789U, 14226U, 20498U, 19910U, 3951U, + 13427U, 5168U, 14605U, 20761U, 9109U, 4955U, 14392U, 9359U, 5334U, + 14771U, 38990U, 46240U, 39214U, 46457U, 19721U, 3680U, 13156U, 4847U, + 14284U, 20551U, 19968U, 4009U, 13485U, 5226U, 14663U, 20814U, 28888U, + 30432U, 33641U, 39066U, 46309U, 39290U, 46533U, 19553U, 3359U, 12835U, + 4558U, 13995U, 20410U, 39004U, 46254U, 39228U, 46471U, 39106U, 46349U, + 39330U, 46573U, 24697U, 30162U, 3255U, 12731U, 20324U, 9121U, 4980U, + 14417U, 9371U, 5359U, 14796U, 33221U, 9264U, 5145U, 14582U, 9514U, + 5524U, 14961U, 38997U, 46247U, 39221U, 46464U, 19481U, 8574U, 3111U, + 8910U, 12587U, 4382U, 13858U, 20243U, 37073U, 46084U, 32530U, 30815U, + 32555U, 30843U, 37067U, 3419U, 12895U, 4631U, 14068U, 46078U, 37096U, + 46107U, 37154U, 46155U, 37102U, 46113U, 37130U, 46131U, 2552U, 12063U, + 2639U, 12140U, 39059U, 46302U, 39283U, 46526U, 19532U, 3338U, 12814U, + 4537U, 13974U, 20391U, 20192U, 2595U, 4329U, 12096U, 2695U, 13805U, + 5582U, 12186U, 15019U, 21069U, 39012U, 46262U, 39236U, 46479U, 19769U, + 3728U, 13204U, 4895U, 14332U, 20595U, 20016U, 4057U, 13533U, 5274U, + 14711U, 20858U, 20170U, 2573U, 4307U, 12074U, 2673U, 13783U, 5560U, + 12164U, 14997U, 21049U, 39114U, 46357U, 39338U, 46581U, 19888U, 3887U, + 13363U, 5122U, 14559U, 20741U, 20135U, 4216U, 13692U, 5501U, 14938U, + 21004U, 20203U, 2606U, 4340U, 12107U, 2706U, 13816U, 5593U, 12197U, + 15030U, 21079U, 20181U, 2584U, 4318U, 12085U, 2684U, 13794U, 5571U, + 12175U, 15008U, 21059U, 19563U, 3369U, 12845U, 4568U, 14005U, 20419U, + 20214U, 2617U, 4351U, 12118U, 2717U, 13827U, 5604U, 12208U, 15041U, + 21089U, 19616U, 3409U, 12885U, 4621U, 14058U, 20455U, 2541U, 37246U, + 12052U, 37284U, 2628U, 37265U, 12129U, 37303U, 25081U, 24711U, 30184U, + 33242U, 29145U, 30692U, 33877U, 30343U, 33505U, 29169U, 30716U, 33901U, + 37160U, 46161U, 40140U, 40742U, 40317U, 40919U, 40180U, 40782U, 40357U, + 40959U, 28880U, 30424U, 33633U, 29057U, 30604U, 33825U, 30154U, 24724U, + 33287U, 30438U, 33227U, 40150U, 40752U, 40327U, 40929U, 40190U, 40792U, + 40367U, 40969U, 28933U, 30472U, 33703U, 29065U, 30612U, 33833U, 40160U, + 40762U, 40337U, 40939U, 40200U, 40802U, 40377U, 40979U, 28941U, 30486U, + 33711U, 29073U, 30620U, 33841U, 40170U, 40772U, 40347U, 40949U, 40210U, + 40812U, 40387U, 40989U, 28949U, 30494U, 33719U, 29081U, 30628U, 33849U, + 28957U, 30168U, 24739U, 33302U, 30518U, 40637U, 39396U, 46892U, 39434U, + 46930U, 39414U, 46910U, 39452U, 46948U, 40035U, 39405U, 46901U, 39443U, + 46939U, 39424U, 46920U, 39462U, 46958U, 38931U, 46181U, 39155U, 46398U, + 38950U, 46200U, 39174U, 46417U, 38940U, 46190U, 39164U, 46407U, 38959U, + 46209U, 39183U, 46426U, 29089U, 30636U, 33857U, 37026U, 46037U, 36999U, + 46001U, 37052U, 46063U, 37016U, 46027U, 36989U, 45991U, 37043U, 46054U, + 37142U, 46143U, 12044U, 2533U, 19454U, 15583U, 6088U, 9594U, 21636U, + 24426U, 30081U, 24785U, 30751U, 32541U, 30827U, 33157U, 38976U, 46226U, + 39200U, 46443U, 28920U, 30459U, 24801U, 30759U, 32548U, 30835U, 33690U, + 39080U, 46323U, 39304U, 46547U, 24439U, 30087U, 33163U, 28926U, 30465U, + 33696U, 24847U, 30273U, 33382U, 24835U, 30261U, 33370U, 5713U, 15875U, + 21907U, 17051U, 22819U, 19745U, 3704U, 13180U, 4871U, 14308U, 20573U, + 19992U, 4033U, 13509U, 5250U, 14687U, 20836U, 19697U, 3656U, 13132U, + 4823U, 14260U, 20529U, 19944U, 3985U, 13461U, 5202U, 14639U, 20792U, + 30480U, 35200U, 11992U, 38338U, 48687U, 2489U, 37995U, 48284U, 19407U, + 38549U, 48937U, 15542U, 38440U, 48807U, 6047U, 38097U, 48404U, 21599U, + 38645U, 49051U, 11896U, 25495U, 2401U, 25143U, 19321U, 25843U, 44044U, + 27221U, 43654U, 26755U, 44372U, 27671U, 11812U, 32496U, 44462U, 37544U, + 47770U, 38731U, 49152U, 33952U, 44730U, 37726U, 47976U, 38865U, 49310U, + 38274U, 48611U, 2327U, 32460U, 44402U, 37452U, 47666U, 38663U, 49072U, + 33916U, 44670U, 37634U, 47872U, 38797U, 49230U, 37931U, 48208U, 8548U, + 32478U, 44432U, 37498U, 47718U, 38697U, 49112U, 33934U, 44700U, 37680U, + 47924U, 38831U, 49270U, 38178U, 48497U, 19238U, 32514U, 44492U, 37590U, + 47822U, 38765U, 49192U, 33970U, 44760U, 37772U, 48028U, 38899U, 49350U, + 38489U, 48865U, 15382U, 44596U, 27801U, 44864U, 28157U, 27979U, 28335U, + 38376U, 48731U, 5897U, 44520U, 27709U, 44788U, 28065U, 27891U, 28247U, + 38033U, 48328U, 9578U, 44558U, 27755U, 44826U, 28111U, 27935U, 28291U, + 38210U, 48535U, 21502U, 44634U, 27847U, 44902U, 28203U, 28023U, 28379U, + 38585U, 48979U, 12003U, 38357U, 48709U, 8416U, 38137U, 48450U, 2500U, + 38014U, 48306U, 8403U, 38116U, 48426U, 19417U, 38567U, 48958U, 8429U, + 38158U, 48474U, 45395U, 44998U, 37844U, 48109U, 45332U, 44938U, 37816U, + 48078U, 45458U, 45058U, 37872U, 48140U, 11916U, 43886U, 26987U, 25523U, + 2421U, 43496U, 26521U, 25171U, 19339U, 44224U, 27449U, 25869U, 15466U, + 44076U, 27261U, 25685U, 5971U, 43686U, 26795U, 25333U, 11796U, 38242U, + 48573U, 2311U, 37899U, 48170U, 19224U, 38459U, 48829U, 11838U, 38306U, + 48649U, 2343U, 37963U, 48246U, 19261U, 38519U, 48901U, 15408U, 44016U, + 37366U, 47568U, 38408U, 48769U, 5913U, 43626U, 37322U, 47518U, 38065U, + 48366U, 21525U, 44346U, 37410U, 47618U, 38615U, 49015U, 12014U, 43982U, + 27107U, 25607U, 2511U, 43592U, 26641U, 25255U, 19427U, 44314U, 27563U, + 25947U, 15553U, 45416U, 45018U, 28469U, 25769U, 6058U, 45353U, 44958U, + 28421U, 25417U, 21609U, 45478U, 45077U, 28517U, 26019U, 11936U, 43918U, + 27027U, 25551U, 2441U, 43528U, 26561U, 25199U, 19357U, 44254U, 27487U, + 25895U, 15486U, 44108U, 27301U, 25713U, 5991U, 43718U, 26835U, 25361U, + 11854U, 43830U, 26915U, 25447U, 2359U, 43440U, 26449U, 25095U, 19275U, + 44172U, 27381U, 25799U, 15424U, 27149U, 25637U, 45183U, 28647U, 5929U, + 26683U, 25285U, 45115U, 28563U, 21539U, 27603U, 25975U, 45251U, 28731U, + 12025U, 43999U, 27128U, 25622U, 2522U, 43609U, 26662U, 25270U, 19437U, + 44330U, 27583U, 25961U, 15564U, 45437U, 45038U, 28493U, 25784U, 6069U, + 45374U, 44978U, 28445U, 25432U, 21619U, 45498U, 45096U, 28540U, 26033U, + 11956U, 43950U, 27067U, 25579U, 2461U, 43560U, 26601U, 25227U, 19375U, + 44284U, 27525U, 25921U, 15506U, 44140U, 27341U, 25741U, 6011U, 43750U, + 26875U, 25389U, 11880U, 43858U, 26951U, 25471U, 2385U, 43468U, 26485U, + 25119U, 19298U, 44198U, 27415U, 25821U, 15450U, 27185U, 25661U, 45217U, + 28689U, 5955U, 26719U, 25309U, 45149U, 28605U, 21562U, 27637U, 25997U, + 45283U, 28771U, 26259U, 23406U, 26093U, 23471U, 26343U, 23487U, 26199U, + 28836U, 30373U, 33543U, 40528U, 50580U, 39880U, 40562U, 50616U, 39914U, + 40428U, 50474U, 39780U, 40472U, 50520U, 39824U, 40404U, 50183U, 39506U, + 40502U, 50552U, 39854U, 31515U, 31755U, 39121U, 46364U, 39345U, 46588U, + 19899U, 3898U, 13374U, 5157U, 14594U, 20751U, 20146U, 4227U, 13703U, + 5536U, 14973U, 21014U, 39052U, 46295U, 39276U, 46519U, 19854U, 3813U, + 13289U, 5088U, 14525U, 20673U, 20101U, 4142U, 13618U, 5467U, 14904U, + 20936U, 24420U, 30075U, 3909U, 13385U, 4238U, 13714U, 9085U, 4931U, + 14368U, 9335U, 5310U, 14747U, 33151U, 38969U, 46219U, 39193U, 46436U, + 39128U, 46371U, 39352U, 46595U, 3478U, 12954U, 4690U, 14127U, 19461U, + 3091U, 12567U, 4362U, 13838U, 20225U, 28914U, 30453U, 3937U, 13413U, + 4266U, 13742U, 9205U, 5064U, 14501U, 9455U, 5443U, 14880U, 33684U, + 39073U, 46316U, 39297U, 46540U, 39146U, 46389U, 39370U, 46613U, 3610U, + 13086U, 4777U, 14214U, 19573U, 3379U, 12855U, 4578U, 14015U, 20428U, + 23563U, 29095U, 33068U, 30642U, 32843U, 9217U, 5076U, 14513U, 9467U, + 5455U, 14892U, 3327U, 12803U, 20381U, 30417U, 28858U, 33587U, 33609U, + 33863U, 33112U, 33090U, 19606U, 8604U, 2563U, 3399U, 8979U, 2663U, + 12875U, 4611U, 14048U, 20446U, 33565U, 33432U, 33813U, 24367U, 34828U, + 8376U, 24306U, 24765U, 39U, 85U, 8336U, 24U, 33052U, 33107U, + 33419U, 33801U, 24356U, 34816U, 8363U, 24288U, 24754U, 16U, 33043U, + 24822U, 30248U, 9569U, 21481U, 3923U, 13399U, 4252U, 13728U, 9193U, + 5052U, 14489U, 9443U, 5431U, 14868U, 33351U, 39045U, 46288U, 39269U, + 46512U, 39389U, 46622U, 39137U, 46380U, 39361U, 46604U, 3598U, 13074U, + 4765U, 14202U, 19522U, 3207U, 12683U, 4517U, 13954U, 20280U, 37114U, + 46125U, 3317U, 12793U, 4527U, 13964U, 24718U, 30191U, 33281U, 46009U, + 39038U, 39262U, 46505U, 37034U, 46045U, 37007U, 46018U, 37059U, 46070U, + 24405U, 30068U, 33144U, 28899U, 30446U, 33677U, 24815U, 30225U, 33344U, + 37108U, 46119U, 37148U, 3441U, 12917U, 4653U, 14090U, 46149U, 19780U, + 3739U, 13215U, 4918U, 14355U, 20605U, 20027U, 4068U, 13544U, 5297U, + 14734U, 20868U, 19793U, 3752U, 13228U, 4967U, 14404U, 20617U, 20040U, + 4081U, 13557U, 5346U, 14783U, 20880U, 40043U, 40645U, 15088U, 5640U, + 21157U, 40397U, 40999U, 16077U, 6608U, 22064U, 17211U, 7843U, 22952U, + 40220U, 40822U, 15854U, 6395U, 21888U, 17030U, 7672U, 22800U, 19542U, + 3348U, 12824U, 4547U, 13984U, 20400U, 19757U, 8686U, 3716U, 9061U, + 13192U, 4883U, 14320U, 20584U, 20004U, 8804U, 4045U, 9311U, 13521U, + 5262U, 14699U, 20847U, 3553U, 13029U, 8940U, 4478U, 3583U, 13059U, + 8966U, 4504U, 3506U, 12982U, 4718U, 14155U, 3146U, 12622U, 4417U, + 13893U, 3568U, 13044U, 8953U, 4491U, 4293U, 13769U, 21036U, 3851U, + 13327U, 20708U, 4180U, 13656U, 20971U, 19491U, 3121U, 12597U, 4392U, + 13868U, 20252U, 3490U, 12966U, 4702U, 14139U, 3132U, 12608U, 4403U, + 13879U, 3537U, 13013U, 4749U, 14186U, 3173U, 12649U, 4444U, 13920U, + 3521U, 12997U, 4733U, 14170U, 3159U, 12635U, 4430U, 13906U, 19818U, + 8710U, 3777U, 9145U, 13253U, 5004U, 14441U, 20640U, 20065U, 8828U, + 4106U, 9395U, 13582U, 5383U, 14820U, 20903U, 3837U, 13313U, 20695U, + 4166U, 13642U, 20958U, 3303U, 12779U, 20368U, 19637U, 8625U, 3452U, + 9000U, 12928U, 4664U, 14101U, 20474U, 20157U, 8887U, 4280U, 9526U, + 13756U, 5547U, 14984U, 21024U, 19806U, 8698U, 3765U, 9133U, 13241U, + 4992U, 14429U, 20629U, 19650U, 8638U, 3465U, 9013U, 12941U, 4677U, + 14114U, 20486U, 20053U, 8816U, 4094U, 9383U, 13570U, 5371U, 14808U, + 20892U, 3824U, 13300U, 20683U, 4153U, 13629U, 20946U, 3290U, 12766U, + 20356U, 19709U, 8674U, 3668U, 9049U, 13144U, 4835U, 14272U, 20540U, + 19956U, 8792U, 3997U, 9299U, 13473U, 5214U, 14651U, 20803U, 3242U, + 12718U, 20312U, 37079U, 39019U, 46269U, 39243U, 46486U, 46090U, 39087U, + 46330U, 39311U, 46554U, 19312U, 21576U, 11828U, 19252U, 15398U, 21516U, + 11870U, 2375U, 19289U, 15440U, 5945U, 21553U, 19732U, 3691U, 13167U, + 4858U, 14295U, 20561U, 19979U, 4020U, 13496U, 5237U, 14674U, 20824U, + 24528U, 30094U, 40050U, 40652U, 40227U, 40829U, 33170U, 24868U, 30285U, + 40090U, 40692U, 40267U, 40869U, 33403U, 24982U, 30293U, 40100U, 40702U, + 40277U, 40879U, 33411U, 25087U, 30349U, 40110U, 40712U, 40287U, 40889U, + 33511U, 28866U, 30395U, 33595U, 29137U, 30684U, 40120U, 40722U, 40297U, + 40899U, 33869U, 29176U, 30723U, 40130U, 40732U, 40307U, 40909U, 33908U, + 19831U, 8723U, 3790U, 9158U, 13266U, 5017U, 14454U, 20652U, 20078U, + 8841U, 4119U, 9408U, 13595U, 5396U, 14833U, 20915U, 3267U, 12743U, + 20335U, 19865U, 8746U, 3864U, 9229U, 13340U, 5099U, 14536U, 20720U, + 20112U, 8864U, 4193U, 9479U, 13669U, 5478U, 14915U, 20983U, 37087U, + 39028U, 46278U, 39252U, 46495U, 46098U, 39096U, 46339U, 39320U, 46563U, + 19674U, 8651U, 3633U, 9026U, 13109U, 4800U, 14237U, 20508U, 19921U, + 8769U, 3962U, 9276U, 13438U, 5179U, 14616U, 20771U, 3217U, 12693U, + 20289U, 24859U, 33394U, 28996U, 30776U, 32574U, 30864U, 28811U, 30357U, + 33519U, 24703U, 30176U, 33234U, 28980U, 30555U, 33762U, 28972U, 30547U, + 33727U, 15161U, 5723U, 21293U, 15140U, 5692U, 21274U, 9181U, 5040U, + 14477U, 9431U, 5419U, 14856U, 19626U, 8614U, 3430U, 8989U, 12906U, + 4642U, 14079U, 20464U, 19843U, 8735U, 3802U, 9170U, 13278U, 5029U, + 14466U, 20663U, 20090U, 8853U, 4131U, 9420U, 13607U, 5408U, 14845U, + 20926U, 3279U, 12755U, 20346U, 19877U, 8758U, 3876U, 9241U, 13352U, + 5111U, 14548U, 20731U, 20124U, 8876U, 4205U, 9491U, 13681U, 5490U, + 14927U, 20994U, 25039U, 30301U, 33458U, 25053U, 30315U, 33472U, 19502U, + 8584U, 3187U, 8920U, 12663U, 4458U, 13934U, 20262U, 25067U, 30329U, + 33486U, 23549U, 29042U, 30563U, 33770U, 19686U, 8663U, 3645U, 9038U, + 13121U, 4812U, 14249U, 20519U, 19933U, 8781U, 3974U, 9288U, 13450U, + 5191U, 14628U, 20782U, 19512U, 8594U, 3197U, 8930U, 12673U, 4468U, + 13944U, 20271U, 11906U, 25509U, 2411U, 25157U, 19330U, 25856U, 44060U, + 27241U, 43670U, 26775U, 44387U, 27690U, 11820U, 32505U, 44477U, 37567U, + 47796U, 38748U, 49172U, 33961U, 44745U, 37749U, 48002U, 38882U, 49330U, + 38290U, 48630U, 2335U, 32469U, 44417U, 37475U, 47692U, 38680U, 49092U, + 33925U, 44685U, 37657U, 47898U, 38814U, 49250U, 37947U, 48227U, 8556U, + 32487U, 44447U, 37521U, 47744U, 38714U, 49132U, 33943U, 44715U, 37703U, + 47950U, 38848U, 49290U, 38194U, 48516U, 19245U, 32522U, 44506U, 37612U, + 47847U, 38781U, 49211U, 33978U, 44774U, 37794U, 48053U, 38915U, 49369U, + 38504U, 48883U, 15390U, 44615U, 27824U, 44883U, 28180U, 28001U, 28357U, + 38392U, 48750U, 5905U, 44539U, 27732U, 44807U, 28088U, 27913U, 28269U, + 38049U, 48347U, 9586U, 44577U, 27778U, 44845U, 28134U, 27957U, 28313U, + 38226U, 48554U, 21509U, 44652U, 27869U, 44920U, 28225U, 28044U, 28400U, + 38600U, 48997U, 11926U, 43902U, 27007U, 25537U, 2431U, 43512U, 26541U, + 25185U, 19348U, 44239U, 27468U, 25882U, 15476U, 44092U, 27281U, 25699U, + 5981U, 43702U, 26815U, 25347U, 11804U, 38258U, 48592U, 2319U, 37915U, + 48189U, 19231U, 38474U, 48847U, 11846U, 38322U, 48668U, 2351U, 37979U, + 48265U, 19268U, 38534U, 48919U, 15416U, 44030U, 37388U, 47593U, 38424U, + 48788U, 5921U, 43640U, 37344U, 47543U, 38081U, 48385U, 21532U, 44359U, + 37431U, 47642U, 38630U, 49033U, 11946U, 43934U, 27047U, 25565U, 2451U, + 43544U, 26581U, 25213U, 19366U, 44269U, 27506U, 25908U, 15496U, 44124U, + 27321U, 25727U, 6001U, 43734U, 26855U, 25375U, 11862U, 43844U, 26933U, + 25459U, 2367U, 43454U, 26467U, 25107U, 19282U, 44185U, 27398U, 25810U, + 15432U, 27167U, 25649U, 45200U, 28668U, 5937U, 26701U, 25297U, 45132U, + 28584U, 21546U, 27620U, 25986U, 45267U, 28751U, 11966U, 43966U, 27087U, + 25593U, 2471U, 43576U, 26621U, 25241U, 19384U, 44299U, 27544U, 25934U, + 15516U, 44156U, 27361U, 25755U, 6021U, 43766U, 26895U, 25403U, 11888U, + 43872U, 26969U, 25483U, 2393U, 43482U, 26503U, 25131U, 19305U, 44211U, + 27432U, 25832U, 15458U, 27203U, 25673U, 45234U, 28710U, 5963U, 26737U, + 25321U, 45166U, 28626U, 21569U, 27654U, 26008U, 45299U, 28791U, 26271U, + 23414U, 26105U, 23479U, 26355U, 23495U, 26211U, 28874U, 30411U, 33603U, + 40545U, 50598U, 39897U, 40578U, 50633U, 39930U, 40450U, 50497U, 39802U, + 40487U, 50536U, 39839U, 40416U, 50196U, 39518U, 40515U, 50566U, 39867U, + 24544U, 30138U, 3230U, 12706U, 20301U, 9097U, 4943U, 14380U, 9347U, + 5322U, 14759U, 33203U, 9252U, 5133U, 14570U, 9502U, 5512U, 14949U, + 38983U, 46233U, 39207U, 46450U, 19471U, 8564U, 3101U, 8900U, 12577U, + 4372U, 13848U, 20234U, 30784U, 30872U, 37136U, 46137U, 79U, 8308U, + 8441U, 43782U, 9602U, 43806U, 122U, 8389U, 8455U, 43794U, 9608U, + 43818U, 24732U, 30197U, 33295U, 28842U, 30379U, 33549U, 29153U, 30700U, + 33885U, 24808U, 30211U, 33337U, 24747U, 30204U, 33310U, 28850U, 30387U, + 33557U, 29161U, 30708U, 33893U, 24828U, 30254U, 33357U, 11976U, 2481U, + 19393U, 15526U, 6031U, 21585U, 19596U, 3389U, 12865U, 4601U, 14038U, + 20437U, 29003U, 30793U, 32581U, 30881U, 25046U, 30308U, 33465U, 25060U, + 30322U, 33479U, 25074U, 30336U, 33493U, 23556U, 28988U, 30767U, 32566U, + 30855U, 23541U, 12036U, 19447U, 15575U, 6080U, 21629U, 11984U, 19400U, + 15534U, 6039U, 21592U, 23382U, 26057U, 23764U, 26305U, 23438U, 26139U, + 23804U, 26413U, 23391U, 26070U, 23781U, 26330U, 23462U, 26175U, 23813U, + 26426U, 42589U, 49446U, 49980U, 42611U, 265U, 49468U, 49996U, 43211U, + 288U, 32683U, 42619U, 49483U, 50010U, 42709U, 49554U, 23603U, 24145U, + 30801U, 42229U, 47305U, 42209U, 36957U, 47285U, 42597U, 49454U, 49988U, + 30915U, 36538U, 32277U, 8314U, 35674U, 31738U, 35884U, 42642U, 49649U, + 50128U, 42669U, 49514U, 50032U, 45533U, 45573U, 45581U, 23594U, 23738U, + 30144U, 35388U, 30044U, 35361U, 31073U, 24206U, 35353U, 29741U, 29728U, + 96U, 8355U, 8447U, 33317U, 23835U, 23867U, 42685U, 49530U, 50054U, + 34602U, 24345U, 23873U, 34423U, 45820U, 45714U, 23376U, 23607U, 35636U, + 24072U, 29101U, 30648U, 30061U, 34331U, 32065U, 35022U, 29508U, 34277U, + 32011U, 34878U, 29376U, 34361U, 32095U, 35048U, 29532U, 34305U, 32039U, + 34939U, 29432U, 23756U, 26293U, 23430U, 26127U, 34162U, 34902U, 29398U, + 136U, 21099U, 42357U, 49834U, 34961U, 29452U, 21191U, 35666U, 24090U, + 29119U, 30666U, 34398U, 34985U, 29474U, 176U, 21238U, 42387U, 49866U, + 34178U, 34926U, 29420U, 156U, 21117U, 42367U, 49850U, 34414U, 35009U, + 29496U, 196U, 21256U, 42397U, 49882U, 34728U, 35072U, 29554U, 216U, + 21320U, 42417U, 49905U, 29298U, 40024U, 42627U, 49491U, 42724U, 49569U, + 32677U, 8329U, 33061U, 8347U, 23527U, 33323U, 15183U, 42339U, 15193U, + 47440U, 40594U, 40608U, 24324U, 8276U, 24330U, 8283U, 32638U, 31811U, + 37209U, 32647U, 32629U, 31803U, 37197U, 31381U, 42261U, 47337U, 49898U, + 42650U, 49506U, 50024U, 42701U, 49546U, 50062U, 34135U, 23915U, 234U, + 21359U, 49919U, 167U, 21183U, 42378U, 49859U, 207U, 21266U, 42408U, + 49891U, 24642U, 9795U, 17734U, 35792U, 24558U, 23979U, 35547U, 24025U, + 9738U, 17675U, 34428U, 35293U, 9936U, 30532U, 23748U, 35379U, 23422U, + 35370U, 42693U, 49538U, 35770U, 42565U, 49415U, 49956U, 9814U, 17751U, + 35807U, 23862U, 42581U, 49438U, 49972U, 35690U, 35325U, 31067U, 31847U, + 30033U, 9775U, 17716U, 35776U, 35531U, 9718U, 17657U, 24194U, 23630U, + 34126U, 24412U, 35580U, 30963U, 23639U, 34143U, 24776U, 35598U, 23923U, + 35164U, 23906U, 35155U, 24054U, 35216U, 28906U, 35618U, 24792U, 35608U, + 23533U, 32620U, 33329U, 33098U, 31446U, 32869U, 24536U, 35589U, 23649U, + 34153U, 31309U, 23933U, 35174U, 24063U, 35225U, 28964U, 35627U, 23790U, + 26367U, 23503U, 26223U, 34046U, 9879U, 35562U, 9757U, 17692U, 34346U, + 32080U, 35035U, 29520U, 34291U, 32025U, 34890U, 29387U, 34375U, 32109U, + 35060U, 29543U, 34318U, 32052U, 34950U, 29442U, 31375U, 23828U, 35658U, + 24081U, 29110U, 30657U, 30218U, 23773U, 26318U, 23454U, 26163U, 34170U, + 34914U, 29409U, 146U, 21108U, 49842U, 34973U, 29463U, 21200U, 35682U, + 24099U, 29128U, 30675U, 34406U, 34997U, 29485U, 186U, 21247U, 49874U, + 34767U, 35083U, 29564U, 225U, 21328U, 49912U, 32878U, 42573U, 255U, + 49423U, 49964U, 43200U, 275U, 23614U, 9668U, 30102U, 23953U, 9700U, + 30578U, 23658U, 30118U, 42677U, 49522U, 50040U, 23900U, 42774U, 49618U, + 50103U, 35150U, 23588U, 34119U, 35183U, 9823U, 17759U, 35814U, 35704U, + 29652U, 35339U, 9785U, 17725U, 35784U, 35539U, 9728U, 17666U, 30955U, + 30971U, 31317U, 9804U, 17742U, 35799U, 35554U, 9747U, 17683U, 17708U, + 17648U, 34053U, 9888U, 35569U, 9766U, 17700U, 23622U, 9678U, 30110U, + 23966U, 9709U, 30591U, 33364U, 24140U, 49640U, 8476U, 21176U, 32353U, + 42268U, 49476U, 42479U, 49407U, 32689U, 24940U, 42717U, 49562U, 24108U, + 24160U, 34697U, 30998U, 47387U, 42346U, 47453U, 35576U, 33445U, 36544U, + 35897U, 35879U, 51137U, 49388U, 21313U, 47344U, 33500U, 32919U, 34609U, + 34574U, 45774U, 45799U, 45841U, 23447U, 42177U, 47262U, 42215U, 47291U, + 23888U, 30511U, 42277U, 42426U, 47360U, 42487U, 42635U, 49499U, 42732U, + 49577U, 47395U, 21352U, 47447U, 31476U, 32141U, 33085U, 24550U, 32323U, + 30526U, 35299U, 9944U, 30540U, 32933U, 23895U, 24126U, 24945U, 26188U, + 42184U, 47269U, 42222U, 47298U, 42303U, 47381U, 42495U, 8469U, 21138U, + 49431U, 42471U, 24351U, 23960U, 30585U, 32263U, 35145U, 29658U, 23973U, + 30598U, 68U, +}; +#endif // GET_INSTRINFO_MC_DESC diff --git a/arch/ARM/ARMGenInstrInfo.inc b/arch/ARM/ARMGenInstrInfo.inc index 82178f342b..c66fc3603b 100644 --- a/arch/ARM/ARMGenInstrInfo.inc +++ b/arch/ARM/ARMGenInstrInfo.inc @@ -2,7 +2,8 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +/*===- TableGen'erated file -------------------------------------*- C++ +-*-===*|* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| @@ -13,2974 +14,2974 @@ #undef GET_INSTRINFO_ENUM enum { - ARM_PHI = 0, - ARM_INLINEASM = 1, - ARM_CFI_INSTRUCTION = 2, - ARM_EH_LABEL = 3, - ARM_GC_LABEL = 4, - ARM_ANNOTATION_LABEL = 5, - ARM_KILL = 6, - ARM_EXTRACT_SUBREG = 7, - ARM_INSERT_SUBREG = 8, - ARM_IMPLICIT_DEF = 9, - ARM_SUBREG_TO_REG = 10, - ARM_COPY_TO_REGCLASS = 11, - ARM_DBG_VALUE = 12, - ARM_DBG_LABEL = 13, - ARM_REG_SEQUENCE = 14, - ARM_COPY = 15, - ARM_BUNDLE = 16, - ARM_LIFETIME_START = 17, - ARM_LIFETIME_END = 18, - ARM_STACKMAP = 19, - ARM_FENTRY_CALL = 20, - ARM_PATCHPOINT = 21, - ARM_LOAD_STACK_GUARD = 22, - ARM_STATEPOINT = 23, - ARM_LOCAL_ESCAPE = 24, - ARM_FAULTING_OP = 25, - ARM_PATCHABLE_OP = 26, - ARM_PATCHABLE_FUNCTION_ENTER = 27, - ARM_PATCHABLE_RET = 28, - ARM_PATCHABLE_FUNCTION_EXIT = 29, - ARM_PATCHABLE_TAIL_CALL = 30, - ARM_PATCHABLE_EVENT_CALL = 31, - ARM_PATCHABLE_TYPED_EVENT_CALL = 32, - ARM_ICALL_BRANCH_FUNNEL = 33, - ARM_G_ADD = 34, - ARM_G_SUB = 35, - ARM_G_MUL = 36, - ARM_G_SDIV = 37, - ARM_G_UDIV = 38, - ARM_G_SREM = 39, - ARM_G_UREM = 40, - ARM_G_AND = 41, - ARM_G_OR = 42, - ARM_G_XOR = 43, - ARM_G_IMPLICIT_DEF = 44, - ARM_G_PHI = 45, - ARM_G_FRAME_INDEX = 46, - ARM_G_GLOBAL_VALUE = 47, - ARM_G_EXTRACT = 48, - ARM_G_UNMERGE_VALUES = 49, - ARM_G_INSERT = 50, - ARM_G_MERGE_VALUES = 51, - ARM_G_PTRTOINT = 52, - ARM_G_INTTOPTR = 53, - ARM_G_BITCAST = 54, - ARM_G_LOAD = 55, - ARM_G_SEXTLOAD = 56, - ARM_G_ZEXTLOAD = 57, - ARM_G_STORE = 58, - ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, - ARM_G_ATOMIC_CMPXCHG = 60, - ARM_G_ATOMICRMW_XCHG = 61, - ARM_G_ATOMICRMW_ADD = 62, - ARM_G_ATOMICRMW_SUB = 63, - ARM_G_ATOMICRMW_AND = 64, - ARM_G_ATOMICRMW_NAND = 65, - ARM_G_ATOMICRMW_OR = 66, - ARM_G_ATOMICRMW_XOR = 67, - ARM_G_ATOMICRMW_MAX = 68, - ARM_G_ATOMICRMW_MIN = 69, - ARM_G_ATOMICRMW_UMAX = 70, - ARM_G_ATOMICRMW_UMIN = 71, - ARM_G_BRCOND = 72, - ARM_G_BRINDIRECT = 73, - ARM_G_INTRINSIC = 74, - ARM_G_INTRINSIC_W_SIDE_EFFECTS = 75, - ARM_G_ANYEXT = 76, - ARM_G_TRUNC = 77, - ARM_G_CONSTANT = 78, - ARM_G_FCONSTANT = 79, - ARM_G_VASTART = 80, - ARM_G_VAARG = 81, - ARM_G_SEXT = 82, - ARM_G_ZEXT = 83, - ARM_G_SHL = 84, - ARM_G_LSHR = 85, - ARM_G_ASHR = 86, - ARM_G_ICMP = 87, - ARM_G_FCMP = 88, - ARM_G_SELECT = 89, - ARM_G_UADDE = 90, - ARM_G_USUBE = 91, - ARM_G_SADDO = 92, - ARM_G_SSUBO = 93, - ARM_G_UMULO = 94, - ARM_G_SMULO = 95, - ARM_G_UMULH = 96, - ARM_G_SMULH = 97, - ARM_G_FADD = 98, - ARM_G_FSUB = 99, - ARM_G_FMUL = 100, - ARM_G_FMA = 101, - ARM_G_FDIV = 102, - ARM_G_FREM = 103, - ARM_G_FPOW = 104, - ARM_G_FEXP = 105, - ARM_G_FEXP2 = 106, - ARM_G_FLOG = 107, - ARM_G_FLOG2 = 108, - ARM_G_FNEG = 109, - ARM_G_FPEXT = 110, - ARM_G_FPTRUNC = 111, - ARM_G_FPTOSI = 112, - ARM_G_FPTOUI = 113, - ARM_G_SITOFP = 114, - ARM_G_UITOFP = 115, - ARM_G_FABS = 116, - ARM_G_GEP = 117, - ARM_G_PTR_MASK = 118, - ARM_G_BR = 119, - ARM_G_INSERT_VECTOR_ELT = 120, - ARM_G_EXTRACT_VECTOR_ELT = 121, - ARM_G_SHUFFLE_VECTOR = 122, - ARM_G_BSWAP = 123, - ARM_G_ADDRSPACE_CAST = 124, - ARM_G_BLOCK_ADDR = 125, - ARM_ABS = 126, - ARM_ADDSri = 127, - ARM_ADDSrr = 128, - ARM_ADDSrsi = 129, - ARM_ADDSrsr = 130, - ARM_ADJCALLSTACKDOWN = 131, - ARM_ADJCALLSTACKUP = 132, - ARM_ASRi = 133, - ARM_ASRr = 134, - ARM_B = 135, - ARM_BCCZi64 = 136, - ARM_BCCi64 = 137, - ARM_BMOVPCB_CALL = 138, - ARM_BMOVPCRX_CALL = 139, - ARM_BR_JTadd = 140, - ARM_BR_JTm_i12 = 141, - ARM_BR_JTm_rs = 142, - ARM_BR_JTr = 143, - ARM_BX_CALL = 144, - ARM_CMP_SWAP_16 = 145, - ARM_CMP_SWAP_32 = 146, - ARM_CMP_SWAP_64 = 147, - ARM_CMP_SWAP_8 = 148, - ARM_CONSTPOOL_ENTRY = 149, - ARM_COPY_STRUCT_BYVAL_I32 = 150, - ARM_CompilerBarrier = 151, - ARM_ITasm = 152, - ARM_Int_eh_sjlj_dispatchsetup = 153, - ARM_Int_eh_sjlj_setup_dispatch = 157, - ARM_JUMPTABLE_ADDRS = 158, - ARM_JUMPTABLE_INSTS = 159, - ARM_JUMPTABLE_TBB = 160, - ARM_JUMPTABLE_TBH = 161, - ARM_LDMIA_RET = 162, - ARM_LDRBT_POST = 163, - ARM_LDRConstPool = 164, - ARM_LDRLIT_ga_abs = 165, - ARM_LDRLIT_ga_pcrel = 166, - ARM_LDRLIT_ga_pcrel_ldr = 167, - ARM_LDRT_POST = 168, - ARM_LEApcrel = 169, - ARM_LEApcrelJT = 170, - ARM_LSLi = 171, - ARM_LSLr = 172, - ARM_LSRi = 173, - ARM_LSRr = 174, - ARM_MEMCPY = 175, - ARM_MLAv5 = 176, - ARM_MOVCCi = 177, - ARM_MOVCCi16 = 178, - ARM_MOVCCi32imm = 179, - ARM_MOVCCr = 180, - ARM_MOVCCsi = 181, - ARM_MOVCCsr = 182, - ARM_MOVPCRX = 183, - ARM_MOVTi16_ga_pcrel = 184, - ARM_MOV_ga_pcrel = 185, - ARM_MOV_ga_pcrel_ldr = 186, - ARM_MOVi16_ga_pcrel = 187, - ARM_MOVi32imm = 188, - ARM_MOVsra_flag = 189, - ARM_MOVsrl_flag = 190, - ARM_MULv5 = 191, - ARM_MVNCCi = 192, - ARM_PICADD = 193, - ARM_PICLDR = 194, - ARM_PICLDRB = 195, - ARM_PICLDRH = 196, - ARM_PICLDRSB = 197, - ARM_PICLDRSH = 198, - ARM_PICSTR = 199, - ARM_PICSTRB = 200, - ARM_PICSTRH = 201, - ARM_RORi = 202, - ARM_RORr = 203, - ARM_RRX = 204, - ARM_RRXi = 205, - ARM_RSBSri = 206, - ARM_RSBSrsi = 207, - ARM_RSBSrsr = 208, - ARM_SMLALv5 = 209, - ARM_SMULLv5 = 210, - ARM_SPACE = 211, - ARM_STRBT_POST = 212, - ARM_STRBi_preidx = 213, - ARM_STRBr_preidx = 214, - ARM_STRH_preidx = 215, - ARM_STRT_POST = 216, - ARM_STRi_preidx = 217, - ARM_STRr_preidx = 218, - ARM_SUBS_PC_LR = 219, - ARM_SUBSri = 220, - ARM_SUBSrr = 221, - ARM_SUBSrsi = 222, - ARM_SUBSrsr = 223, - ARM_TAILJMPd = 224, - ARM_TAILJMPr = 225, - ARM_TAILJMPr4 = 226, - ARM_TCRETURNdi = 227, - ARM_TCRETURNri = 228, - ARM_TPsoft = 229, - ARM_UMLALv5 = 230, - ARM_UMULLv5 = 231, - ARM_VLD1LNdAsm_16 = 232, - ARM_VLD1LNdAsm_32 = 233, - ARM_VLD1LNdAsm_8 = 234, - ARM_VLD1LNdWB_fixed_Asm_16 = 235, - ARM_VLD1LNdWB_fixed_Asm_32 = 236, - ARM_VLD1LNdWB_fixed_Asm_8 = 237, - ARM_VLD1LNdWB_register_Asm_16 = 238, - ARM_VLD1LNdWB_register_Asm_32 = 239, - ARM_VLD1LNdWB_register_Asm_8 = 240, - ARM_VLD2LNdAsm_16 = 241, - ARM_VLD2LNdAsm_32 = 242, - ARM_VLD2LNdAsm_8 = 243, - ARM_VLD2LNdWB_fixed_Asm_16 = 244, - ARM_VLD2LNdWB_fixed_Asm_32 = 245, - ARM_VLD2LNdWB_fixed_Asm_8 = 246, - ARM_VLD2LNdWB_register_Asm_16 = 247, - ARM_VLD2LNdWB_register_Asm_32 = 248, - ARM_VLD2LNdWB_register_Asm_8 = 249, - ARM_VLD2LNqAsm_16 = 250, - ARM_VLD2LNqAsm_32 = 251, - ARM_VLD2LNqWB_fixed_Asm_16 = 252, - ARM_VLD2LNqWB_fixed_Asm_32 = 253, - ARM_VLD2LNqWB_register_Asm_16 = 254, - ARM_VLD2LNqWB_register_Asm_32 = 255, - ARM_VLD3DUPdAsm_16 = 256, - ARM_VLD3DUPdAsm_32 = 257, - ARM_VLD3DUPdAsm_8 = 258, - ARM_VLD3DUPdWB_fixed_Asm_16 = 259, - ARM_VLD3DUPdWB_fixed_Asm_32 = 260, - ARM_VLD3DUPdWB_fixed_Asm_8 = 261, - ARM_VLD3DUPdWB_register_Asm_16 = 262, - ARM_VLD3DUPdWB_register_Asm_32 = 263, - ARM_VLD3DUPdWB_register_Asm_8 = 264, - ARM_VLD3DUPqAsm_16 = 265, - ARM_VLD3DUPqAsm_32 = 266, - ARM_VLD3DUPqAsm_8 = 267, - ARM_VLD3DUPqWB_fixed_Asm_16 = 268, - ARM_VLD3DUPqWB_fixed_Asm_32 = 269, - ARM_VLD3DUPqWB_fixed_Asm_8 = 270, - ARM_VLD3DUPqWB_register_Asm_16 = 271, - ARM_VLD3DUPqWB_register_Asm_32 = 272, - ARM_VLD3DUPqWB_register_Asm_8 = 273, - ARM_VLD3LNdAsm_16 = 274, - ARM_VLD3LNdAsm_32 = 275, - ARM_VLD3LNdAsm_8 = 276, - ARM_VLD3LNdWB_fixed_Asm_16 = 277, - ARM_VLD3LNdWB_fixed_Asm_32 = 278, - ARM_VLD3LNdWB_fixed_Asm_8 = 279, - ARM_VLD3LNdWB_register_Asm_16 = 280, - ARM_VLD3LNdWB_register_Asm_32 = 281, - ARM_VLD3LNdWB_register_Asm_8 = 282, - ARM_VLD3LNqAsm_16 = 283, - ARM_VLD3LNqAsm_32 = 284, - ARM_VLD3LNqWB_fixed_Asm_16 = 285, - ARM_VLD3LNqWB_fixed_Asm_32 = 286, - ARM_VLD3LNqWB_register_Asm_16 = 287, - ARM_VLD3LNqWB_register_Asm_32 = 288, - ARM_VLD3dAsm_16 = 289, - ARM_VLD3dAsm_32 = 290, - ARM_VLD3dAsm_8 = 291, - ARM_VLD3dWB_fixed_Asm_16 = 292, - ARM_VLD3dWB_fixed_Asm_32 = 293, - ARM_VLD3dWB_fixed_Asm_8 = 294, - ARM_VLD3dWB_register_Asm_16 = 295, - ARM_VLD3dWB_register_Asm_32 = 296, - ARM_VLD3dWB_register_Asm_8 = 297, - ARM_VLD3qAsm_16 = 298, - ARM_VLD3qAsm_32 = 299, - ARM_VLD3qAsm_8 = 300, - ARM_VLD3qWB_fixed_Asm_16 = 301, - ARM_VLD3qWB_fixed_Asm_32 = 302, - ARM_VLD3qWB_fixed_Asm_8 = 303, - ARM_VLD3qWB_register_Asm_16 = 304, - ARM_VLD3qWB_register_Asm_32 = 305, - ARM_VLD3qWB_register_Asm_8 = 306, - ARM_VLD4DUPdAsm_16 = 307, - ARM_VLD4DUPdAsm_32 = 308, - ARM_VLD4DUPdAsm_8 = 309, - ARM_VLD4DUPdWB_fixed_Asm_16 = 310, - ARM_VLD4DUPdWB_fixed_Asm_32 = 311, - ARM_VLD4DUPdWB_fixed_Asm_8 = 312, - ARM_VLD4DUPdWB_register_Asm_16 = 313, - ARM_VLD4DUPdWB_register_Asm_32 = 314, - ARM_VLD4DUPdWB_register_Asm_8 = 315, - ARM_VLD4DUPqAsm_16 = 316, - ARM_VLD4DUPqAsm_32 = 317, - ARM_VLD4DUPqAsm_8 = 318, - ARM_VLD4DUPqWB_fixed_Asm_16 = 319, - ARM_VLD4DUPqWB_fixed_Asm_32 = 320, - ARM_VLD4DUPqWB_fixed_Asm_8 = 321, - ARM_VLD4DUPqWB_register_Asm_16 = 322, - ARM_VLD4DUPqWB_register_Asm_32 = 323, - ARM_VLD4DUPqWB_register_Asm_8 = 324, - ARM_VLD4LNdAsm_16 = 325, - ARM_VLD4LNdAsm_32 = 326, - ARM_VLD4LNdAsm_8 = 327, - ARM_VLD4LNdWB_fixed_Asm_16 = 328, - ARM_VLD4LNdWB_fixed_Asm_32 = 329, - ARM_VLD4LNdWB_fixed_Asm_8 = 330, - ARM_VLD4LNdWB_register_Asm_16 = 331, - ARM_VLD4LNdWB_register_Asm_32 = 332, - ARM_VLD4LNdWB_register_Asm_8 = 333, - ARM_VLD4LNqAsm_16 = 334, - ARM_VLD4LNqAsm_32 = 335, - ARM_VLD4LNqWB_fixed_Asm_16 = 336, - ARM_VLD4LNqWB_fixed_Asm_32 = 337, - ARM_VLD4LNqWB_register_Asm_16 = 338, - ARM_VLD4LNqWB_register_Asm_32 = 339, - ARM_VLD4dAsm_16 = 340, - ARM_VLD4dAsm_32 = 341, - ARM_VLD4dAsm_8 = 342, - ARM_VLD4dWB_fixed_Asm_16 = 343, - ARM_VLD4dWB_fixed_Asm_32 = 344, - ARM_VLD4dWB_fixed_Asm_8 = 345, - ARM_VLD4dWB_register_Asm_16 = 346, - ARM_VLD4dWB_register_Asm_32 = 347, - ARM_VLD4dWB_register_Asm_8 = 348, - ARM_VLD4qAsm_16 = 349, - ARM_VLD4qAsm_32 = 350, - ARM_VLD4qAsm_8 = 351, - ARM_VLD4qWB_fixed_Asm_16 = 352, - ARM_VLD4qWB_fixed_Asm_32 = 353, - ARM_VLD4qWB_fixed_Asm_8 = 354, - ARM_VLD4qWB_register_Asm_16 = 355, - ARM_VLD4qWB_register_Asm_32 = 356, - ARM_VLD4qWB_register_Asm_8 = 357, - ARM_VMOVD0 = 358, - ARM_VMOVDcc = 359, - ARM_VMOVQ0 = 360, - ARM_VMOVScc = 361, - ARM_VST1LNdAsm_16 = 362, - ARM_VST1LNdAsm_32 = 363, - ARM_VST1LNdAsm_8 = 364, - ARM_VST1LNdWB_fixed_Asm_16 = 365, - ARM_VST1LNdWB_fixed_Asm_32 = 366, - ARM_VST1LNdWB_fixed_Asm_8 = 367, - ARM_VST1LNdWB_register_Asm_16 = 368, - ARM_VST1LNdWB_register_Asm_32 = 369, - ARM_VST1LNdWB_register_Asm_8 = 370, - ARM_VST2LNdAsm_16 = 371, - ARM_VST2LNdAsm_32 = 372, - ARM_VST2LNdAsm_8 = 373, - ARM_VST2LNdWB_fixed_Asm_16 = 374, - ARM_VST2LNdWB_fixed_Asm_32 = 375, - ARM_VST2LNdWB_fixed_Asm_8 = 376, - ARM_VST2LNdWB_register_Asm_16 = 377, - ARM_VST2LNdWB_register_Asm_32 = 378, - ARM_VST2LNdWB_register_Asm_8 = 379, - ARM_VST2LNqAsm_16 = 380, - ARM_VST2LNqAsm_32 = 381, - ARM_VST2LNqWB_fixed_Asm_16 = 382, - ARM_VST2LNqWB_fixed_Asm_32 = 383, - ARM_VST2LNqWB_register_Asm_16 = 384, - ARM_VST2LNqWB_register_Asm_32 = 385, - ARM_VST3LNdAsm_16 = 386, - ARM_VST3LNdAsm_32 = 387, - ARM_VST3LNdAsm_8 = 388, - ARM_VST3LNdWB_fixed_Asm_16 = 389, - ARM_VST3LNdWB_fixed_Asm_32 = 390, - ARM_VST3LNdWB_fixed_Asm_8 = 391, - ARM_VST3LNdWB_register_Asm_16 = 392, - ARM_VST3LNdWB_register_Asm_32 = 393, - ARM_VST3LNdWB_register_Asm_8 = 394, - ARM_VST3LNqAsm_16 = 395, - ARM_VST3LNqAsm_32 = 396, - ARM_VST3LNqWB_fixed_Asm_16 = 397, - ARM_VST3LNqWB_fixed_Asm_32 = 398, - ARM_VST3LNqWB_register_Asm_16 = 399, - ARM_VST3LNqWB_register_Asm_32 = 400, - ARM_VST3dAsm_16 = 401, - ARM_VST3dAsm_32 = 402, - ARM_VST3dAsm_8 = 403, - ARM_VST3dWB_fixed_Asm_16 = 404, - ARM_VST3dWB_fixed_Asm_32 = 405, - ARM_VST3dWB_fixed_Asm_8 = 406, - ARM_VST3dWB_register_Asm_16 = 407, - ARM_VST3dWB_register_Asm_32 = 408, - ARM_VST3dWB_register_Asm_8 = 409, - ARM_VST3qAsm_16 = 410, - ARM_VST3qAsm_32 = 411, - ARM_VST3qAsm_8 = 412, - ARM_VST3qWB_fixed_Asm_16 = 413, - ARM_VST3qWB_fixed_Asm_32 = 414, - ARM_VST3qWB_fixed_Asm_8 = 415, - ARM_VST3qWB_register_Asm_16 = 416, - ARM_VST3qWB_register_Asm_32 = 417, - ARM_VST3qWB_register_Asm_8 = 418, - ARM_VST4LNdAsm_16 = 419, - ARM_VST4LNdAsm_32 = 420, - ARM_VST4LNdAsm_8 = 421, - ARM_VST4LNdWB_fixed_Asm_16 = 422, - ARM_VST4LNdWB_fixed_Asm_32 = 423, - ARM_VST4LNdWB_fixed_Asm_8 = 424, - ARM_VST4LNdWB_register_Asm_16 = 425, - ARM_VST4LNdWB_register_Asm_32 = 426, - ARM_VST4LNdWB_register_Asm_8 = 427, - ARM_VST4LNqAsm_16 = 428, - ARM_VST4LNqAsm_32 = 429, - ARM_VST4LNqWB_fixed_Asm_16 = 430, - ARM_VST4LNqWB_fixed_Asm_32 = 431, - ARM_VST4LNqWB_register_Asm_16 = 432, - ARM_VST4LNqWB_register_Asm_32 = 433, - ARM_VST4dAsm_16 = 434, - ARM_VST4dAsm_32 = 435, - ARM_VST4dAsm_8 = 436, - ARM_VST4dWB_fixed_Asm_16 = 437, - ARM_VST4dWB_fixed_Asm_32 = 438, - ARM_VST4dWB_fixed_Asm_8 = 439, - ARM_VST4dWB_register_Asm_16 = 440, - ARM_VST4dWB_register_Asm_32 = 441, - ARM_VST4dWB_register_Asm_8 = 442, - ARM_VST4qAsm_16 = 443, - ARM_VST4qAsm_32 = 444, - ARM_VST4qAsm_8 = 445, - ARM_VST4qWB_fixed_Asm_16 = 446, - ARM_VST4qWB_fixed_Asm_32 = 447, - ARM_VST4qWB_fixed_Asm_8 = 448, - ARM_VST4qWB_register_Asm_16 = 449, - ARM_VST4qWB_register_Asm_32 = 450, - ARM_VST4qWB_register_Asm_8 = 451, - ARM_t2ABS = 454, - ARM_t2ADDSri = 455, - ARM_t2ADDSrr = 456, - ARM_t2ADDSrs = 457, - ARM_t2BR_JT = 458, - ARM_t2LDMIA_RET = 459, - ARM_t2LDRBpcrel = 460, - ARM_t2LDRConstPool = 461, - ARM_t2LDRHpcrel = 462, - ARM_t2LDRSBpcrel = 463, - ARM_t2LDRSHpcrel = 464, - ARM_t2LDRpci_pic = 465, - ARM_t2LDRpcrel = 466, - ARM_t2LEApcrel = 467, - ARM_t2LEApcrelJT = 468, - ARM_t2MOVCCasr = 469, - ARM_t2MOVCCi = 470, - ARM_t2MOVCCi16 = 471, - ARM_t2MOVCCi32imm = 472, - ARM_t2MOVCClsl = 473, - ARM_t2MOVCClsr = 474, - ARM_t2MOVCCr = 475, - ARM_t2MOVCCror = 476, - ARM_t2MOVSsi = 477, - ARM_t2MOVSsr = 478, - ARM_t2MOVTi16_ga_pcrel = 479, - ARM_t2MOV_ga_pcrel = 480, - ARM_t2MOVi16_ga_pcrel = 481, - ARM_t2MOVi32imm = 482, - ARM_t2MOVsi = 483, - ARM_t2MOVsr = 484, - ARM_t2MVNCCi = 485, - ARM_t2RSBSri = 486, - ARM_t2RSBSrs = 487, - ARM_t2STRB_preidx = 488, - ARM_t2STRH_preidx = 489, - ARM_t2STR_preidx = 490, - ARM_t2SUBSri = 491, - ARM_t2SUBSrr = 492, - ARM_t2SUBSrs = 493, - ARM_t2TBB_JT = 494, - ARM_t2TBH_JT = 495, - ARM_tADCS = 496, - ARM_tADDSi3 = 497, - ARM_tADDSi8 = 498, - ARM_tADDSrr = 499, - ARM_tADDframe = 500, - ARM_tADJCALLSTACKDOWN = 501, - ARM_tADJCALLSTACKUP = 502, - ARM_tBRIND = 503, - ARM_tBR_JTr = 504, - ARM_tBX_CALL = 505, - ARM_tBX_RET = 506, - ARM_tBX_RET_vararg = 507, - ARM_tBfar = 508, - ARM_tLDMIA_UPD = 509, - ARM_tLDRConstPool = 510, - ARM_tLDRLIT_ga_abs = 511, - ARM_tLDRLIT_ga_pcrel = 512, - ARM_tLDR_postidx = 513, - ARM_tLDRpci_pic = 514, - ARM_tLEApcrel = 515, - ARM_tLEApcrelJT = 516, - ARM_tMOVCCr_pseudo = 517, - ARM_tPOP_RET = 518, - ARM_tSBCS = 519, - ARM_tSUBSi3 = 520, - ARM_tSUBSi8 = 521, - ARM_tSUBSrr = 522, - ARM_tTAILJMPd = 523, - ARM_tTAILJMPdND = 524, - ARM_tTAILJMPr = 525, - ARM_tTBB_JT = 526, - ARM_tTBH_JT = 527, - ARM_tTPsoft = 528, - ARM_ADCri = 529, - ARM_ADCrr = 530, - ARM_ADCrsi = 531, - ARM_ADCrsr = 532, - ARM_ADDri = 533, - ARM_ADDrr = 534, - ARM_ADDrsi = 535, - ARM_ADDrsr = 536, - ARM_ADR = 537, - ARM_AESD = 538, - ARM_AESE = 539, - ARM_AESIMC = 540, - ARM_AESMC = 541, - ARM_ANDri = 542, - ARM_ANDrr = 543, - ARM_ANDrsi = 544, - ARM_ANDrsr = 545, - ARM_BFC = 546, - ARM_BFI = 547, - ARM_BICri = 548, - ARM_BICrr = 549, - ARM_BICrsi = 550, - ARM_BICrsr = 551, - ARM_BKPT = 552, - ARM_BL = 553, - ARM_BLX = 554, - ARM_BLX_pred = 555, - ARM_BLXi = 556, - ARM_BL_pred = 557, - ARM_BX = 558, - ARM_BXJ = 559, - ARM_BX_RET = 560, - ARM_BX_pred = 561, - ARM_Bcc = 562, - ARM_CDP = 563, - ARM_CDP2 = 564, - ARM_CLREX = 565, - ARM_CLZ = 566, - ARM_CMNri = 567, - ARM_CMNzrr = 568, - ARM_CMNzrsi = 569, - ARM_CMNzrsr = 570, - ARM_CMPri = 571, - ARM_CMPrr = 572, - ARM_CMPrsi = 573, - ARM_CMPrsr = 574, - ARM_CPS1p = 575, - ARM_CPS2p = 576, - ARM_CPS3p = 577, - ARM_CRC32B = 578, - ARM_CRC32CB = 579, - ARM_CRC32CH = 580, - ARM_CRC32CW = 581, - ARM_CRC32H = 582, - ARM_CRC32W = 583, - ARM_DBG = 584, - ARM_DMB = 585, - ARM_DSB = 586, - ARM_EORri = 587, - ARM_EORrr = 588, - ARM_EORrsi = 589, - ARM_EORrsr = 590, - ARM_ERET = 591, - ARM_FCONSTD = 592, - ARM_FCONSTH = 593, - ARM_FCONSTS = 594, - ARM_FLDMXDB_UPD = 595, - ARM_FLDMXIA = 596, - ARM_FLDMXIA_UPD = 597, - ARM_FMSTAT = 598, - ARM_FSTMXDB_UPD = 599, - ARM_FSTMXIA = 600, - ARM_FSTMXIA_UPD = 601, - ARM_HINT = 602, - ARM_HLT = 603, - ARM_HVC = 604, - ARM_ISB = 605, - ARM_LDA = 606, - ARM_LDAB = 607, - ARM_LDAEX = 608, - ARM_LDAEXB = 609, - ARM_LDAEXD = 610, - ARM_LDAEXH = 611, - ARM_LDAH = 612, - ARM_LDC2L_OFFSET = 613, - ARM_LDC2L_OPTION = 614, - ARM_LDC2L_POST = 615, - ARM_LDC2L_PRE = 616, - ARM_LDC2_OFFSET = 617, - ARM_LDC2_OPTION = 618, - ARM_LDC2_POST = 619, - ARM_LDC2_PRE = 620, - ARM_LDCL_OFFSET = 621, - ARM_LDCL_OPTION = 622, - ARM_LDCL_POST = 623, - ARM_LDCL_PRE = 624, - ARM_LDC_OFFSET = 625, - ARM_LDC_OPTION = 626, - ARM_LDC_POST = 627, - ARM_LDC_PRE = 628, - ARM_LDMDA = 629, - ARM_LDMDA_UPD = 630, - ARM_LDMDB = 631, - ARM_LDMDB_UPD = 632, - ARM_LDMIA = 633, - ARM_LDMIA_UPD = 634, - ARM_LDMIB = 635, - ARM_LDMIB_UPD = 636, - ARM_LDRBT_POST_IMM = 637, - ARM_LDRBT_POST_REG = 638, - ARM_LDRB_POST_IMM = 639, - ARM_LDRB_POST_REG = 640, - ARM_LDRB_PRE_IMM = 641, - ARM_LDRB_PRE_REG = 642, - ARM_LDRBi12 = 643, - ARM_LDRBrs = 644, - ARM_LDRD = 645, - ARM_LDRD_POST = 646, - ARM_LDRD_PRE = 647, - ARM_LDREX = 648, - ARM_LDREXB = 649, - ARM_LDREXD = 650, - ARM_LDREXH = 651, - ARM_LDRH = 652, - ARM_LDRHTi = 653, - ARM_LDRHTr = 654, - ARM_LDRH_POST = 655, - ARM_LDRH_PRE = 656, - ARM_LDRSB = 657, - ARM_LDRSBTi = 658, - ARM_LDRSBTr = 659, - ARM_LDRSB_POST = 660, - ARM_LDRSB_PRE = 661, - ARM_LDRSH = 662, - ARM_LDRSHTi = 663, - ARM_LDRSHTr = 664, - ARM_LDRSH_POST = 665, - ARM_LDRSH_PRE = 666, - ARM_LDRT_POST_IMM = 667, - ARM_LDRT_POST_REG = 668, - ARM_LDR_POST_IMM = 669, - ARM_LDR_POST_REG = 670, - ARM_LDR_PRE_IMM = 671, - ARM_LDR_PRE_REG = 672, - ARM_LDRcp = 673, - ARM_LDRi12 = 674, - ARM_LDRrs = 675, - ARM_MCR = 676, - ARM_MCR2 = 677, - ARM_MCRR = 678, - ARM_MCRR2 = 679, - ARM_MLA = 680, - ARM_MLS = 681, - ARM_MOVPCLR = 682, - ARM_MOVTi16 = 683, - ARM_MOVi = 684, - ARM_MOVi16 = 685, - ARM_MOVr = 686, - ARM_MOVr_TC = 687, - ARM_MOVsi = 688, - ARM_MOVsr = 689, - ARM_MRC = 690, - ARM_MRC2 = 691, - ARM_MRRC = 692, - ARM_MRRC2 = 693, - ARM_MRS = 694, - ARM_MRSbanked = 695, - ARM_MRSsys = 696, - ARM_MSR = 697, - ARM_MSRbanked = 698, - ARM_MSRi = 699, - ARM_MUL = 700, - ARM_MVNi = 701, - ARM_MVNr = 702, - ARM_MVNsi = 703, - ARM_MVNsr = 704, - ARM_ORRri = 705, - ARM_ORRrr = 706, - ARM_ORRrsi = 707, - ARM_ORRrsr = 708, - ARM_PKHBT = 709, - ARM_PKHTB = 710, - ARM_PLDWi12 = 711, - ARM_PLDWrs = 712, - ARM_PLDi12 = 713, - ARM_PLDrs = 714, - ARM_PLIi12 = 715, - ARM_PLIrs = 716, - ARM_QADD = 717, - ARM_QADD16 = 718, - ARM_QADD8 = 719, - ARM_QASX = 720, - ARM_QDADD = 721, - ARM_QDSUB = 722, - ARM_QSAX = 723, - ARM_QSUB = 724, - ARM_QSUB16 = 725, - ARM_QSUB8 = 726, - ARM_RBIT = 727, - ARM_REV = 728, - ARM_REV16 = 729, - ARM_REVSH = 730, - ARM_RFEDA = 731, - ARM_RFEDA_UPD = 732, - ARM_RFEDB = 733, - ARM_RFEDB_UPD = 734, - ARM_RFEIA = 735, - ARM_RFEIA_UPD = 736, - ARM_RFEIB = 737, - ARM_RFEIB_UPD = 738, - ARM_RSBri = 739, - ARM_RSBrr = 740, - ARM_RSBrsi = 741, - ARM_RSBrsr = 742, - ARM_RSCri = 743, - ARM_RSCrr = 744, - ARM_RSCrsi = 745, - ARM_RSCrsr = 746, - ARM_SADD16 = 747, - ARM_SADD8 = 748, - ARM_SASX = 749, - ARM_SBCri = 750, - ARM_SBCrr = 751, - ARM_SBCrsi = 752, - ARM_SBCrsr = 753, - ARM_SBFX = 754, - ARM_SDIV = 755, - ARM_SEL = 756, - ARM_SETEND = 757, - ARM_SETPAN = 758, - ARM_SHA1C = 759, - ARM_SHA1H = 760, - ARM_SHA1M = 761, - ARM_SHA1P = 762, - ARM_SHA1SU0 = 763, - ARM_SHA1SU1 = 764, - ARM_SHA256H = 765, - ARM_SHA256H2 = 766, - ARM_SHA256SU0 = 767, - ARM_SHA256SU1 = 768, - ARM_SHADD16 = 769, - ARM_SHADD8 = 770, - ARM_SHASX = 771, - ARM_SHSAX = 772, - ARM_SHSUB16 = 773, - ARM_SHSUB8 = 774, - ARM_SMC = 775, - ARM_SMLABB = 776, - ARM_SMLABT = 777, - ARM_SMLAD = 778, - ARM_SMLADX = 779, - ARM_SMLAL = 780, - ARM_SMLALBB = 781, - ARM_SMLALBT = 782, - ARM_SMLALD = 783, - ARM_SMLALDX = 784, - ARM_SMLALTB = 785, - ARM_SMLALTT = 786, - ARM_SMLATB = 787, - ARM_SMLATT = 788, - ARM_SMLAWB = 789, - ARM_SMLAWT = 790, - ARM_SMLSD = 791, - ARM_SMLSDX = 792, - ARM_SMLSLD = 793, - ARM_SMLSLDX = 794, - ARM_SMMLA = 795, - ARM_SMMLAR = 796, - ARM_SMMLS = 797, - ARM_SMMLSR = 798, - ARM_SMMUL = 799, - ARM_SMMULR = 800, - ARM_SMUAD = 801, - ARM_SMUADX = 802, - ARM_SMULBB = 803, - ARM_SMULBT = 804, - ARM_SMULL = 805, - ARM_SMULTB = 806, - ARM_SMULTT = 807, - ARM_SMULWB = 808, - ARM_SMULWT = 809, - ARM_SMUSD = 810, - ARM_SMUSDX = 811, - ARM_SRSDA = 812, - ARM_SRSDA_UPD = 813, - ARM_SRSDB = 814, - ARM_SRSDB_UPD = 815, - ARM_SRSIA = 816, - ARM_SRSIA_UPD = 817, - ARM_SRSIB = 818, - ARM_SRSIB_UPD = 819, - ARM_SSAT = 820, - ARM_SSAT16 = 821, - ARM_SSAX = 822, - ARM_SSUB16 = 823, - ARM_SSUB8 = 824, - ARM_STC2L_OFFSET = 825, - ARM_STC2L_OPTION = 826, - ARM_STC2L_POST = 827, - ARM_STC2L_PRE = 828, - ARM_STC2_OFFSET = 829, - ARM_STC2_OPTION = 830, - ARM_STC2_POST = 831, - ARM_STC2_PRE = 832, - ARM_STCL_OFFSET = 833, - ARM_STCL_OPTION = 834, - ARM_STCL_POST = 835, - ARM_STCL_PRE = 836, - ARM_STC_OFFSET = 837, - ARM_STC_OPTION = 838, - ARM_STC_POST = 839, - ARM_STC_PRE = 840, - ARM_STL = 841, - ARM_STLB = 842, - ARM_STLEX = 843, - ARM_STLEXB = 844, - ARM_STLEXD = 845, - ARM_STLEXH = 846, - ARM_STLH = 847, - ARM_STMDA = 848, - ARM_STMDA_UPD = 849, - ARM_STMDB = 850, - ARM_STMDB_UPD = 851, - ARM_STMIA = 852, - ARM_STMIA_UPD = 853, - ARM_STMIB = 854, - ARM_STMIB_UPD = 855, - ARM_STRBT_POST_IMM = 856, - ARM_STRBT_POST_REG = 857, - ARM_STRB_POST_IMM = 858, - ARM_STRB_POST_REG = 859, - ARM_STRB_PRE_IMM = 860, - ARM_STRB_PRE_REG = 861, - ARM_STRBi12 = 862, - ARM_STRBrs = 863, - ARM_STRD = 864, - ARM_STRD_POST = 865, - ARM_STRD_PRE = 866, - ARM_STREX = 867, - ARM_STREXB = 868, - ARM_STREXD = 869, - ARM_STREXH = 870, - ARM_STRH = 871, - ARM_STRHTi = 872, - ARM_STRHTr = 873, - ARM_STRH_POST = 874, - ARM_STRH_PRE = 875, - ARM_STRT_POST_IMM = 876, - ARM_STRT_POST_REG = 877, - ARM_STR_POST_IMM = 878, - ARM_STR_POST_REG = 879, - ARM_STR_PRE_IMM = 880, - ARM_STR_PRE_REG = 881, - ARM_STRi12 = 882, - ARM_STRrs = 883, - ARM_SUBri = 884, - ARM_SUBrr = 885, - ARM_SUBrsi = 886, - ARM_SUBrsr = 887, - ARM_SVC = 888, - ARM_SWP = 889, - ARM_SWPB = 890, - ARM_SXTAB = 891, - ARM_SXTAB16 = 892, - ARM_SXTAH = 893, - ARM_SXTB = 894, - ARM_SXTB16 = 895, - ARM_SXTH = 896, - ARM_TEQri = 897, - ARM_TEQrr = 898, - ARM_TEQrsi = 899, - ARM_TEQrsr = 900, - ARM_TRAP = 901, - ARM_TRAPNaCl = 902, - ARM_TSB = 903, - ARM_TSTri = 904, - ARM_TSTrr = 905, - ARM_TSTrsi = 906, - ARM_TSTrsr = 907, - ARM_UADD16 = 908, - ARM_UADD8 = 909, - ARM_UASX = 910, - ARM_UBFX = 911, - ARM_UDF = 912, - ARM_UDIV = 913, - ARM_UHADD16 = 914, - ARM_UHADD8 = 915, - ARM_UHASX = 916, - ARM_UHSAX = 917, - ARM_UHSUB16 = 918, - ARM_UHSUB8 = 919, - ARM_UMAAL = 920, - ARM_UMLAL = 921, - ARM_UMULL = 922, - ARM_UQADD16 = 923, - ARM_UQADD8 = 924, - ARM_UQASX = 925, - ARM_UQSAX = 926, - ARM_UQSUB16 = 927, - ARM_UQSUB8 = 928, - ARM_USAD8 = 929, - ARM_USADA8 = 930, - ARM_USAT = 931, - ARM_USAT16 = 932, - ARM_USAX = 933, - ARM_USUB16 = 934, - ARM_USUB8 = 935, - ARM_UXTAB = 936, - ARM_UXTAB16 = 937, - ARM_UXTAH = 938, - ARM_UXTB = 939, - ARM_UXTB16 = 940, - ARM_UXTH = 941, - ARM_VABALsv2i64 = 942, - ARM_VABALsv4i32 = 943, - ARM_VABALsv8i16 = 944, - ARM_VABALuv2i64 = 945, - ARM_VABALuv4i32 = 946, - ARM_VABALuv8i16 = 947, - ARM_VABAsv16i8 = 948, - ARM_VABAsv2i32 = 949, - ARM_VABAsv4i16 = 950, - ARM_VABAsv4i32 = 951, - ARM_VABAsv8i16 = 952, - ARM_VABAsv8i8 = 953, - ARM_VABAuv16i8 = 954, - ARM_VABAuv2i32 = 955, - ARM_VABAuv4i16 = 956, - ARM_VABAuv4i32 = 957, - ARM_VABAuv8i16 = 958, - ARM_VABAuv8i8 = 959, - ARM_VABDLsv2i64 = 960, - ARM_VABDLsv4i32 = 961, - ARM_VABDLsv8i16 = 962, - ARM_VABDLuv2i64 = 963, - ARM_VABDLuv4i32 = 964, - ARM_VABDLuv8i16 = 965, - ARM_VABDfd = 966, - ARM_VABDfq = 967, - ARM_VABDhd = 968, - ARM_VABDhq = 969, - ARM_VABDsv16i8 = 970, - ARM_VABDsv2i32 = 971, - ARM_VABDsv4i16 = 972, - ARM_VABDsv4i32 = 973, - ARM_VABDsv8i16 = 974, - ARM_VABDsv8i8 = 975, - ARM_VABDuv16i8 = 976, - ARM_VABDuv2i32 = 977, - ARM_VABDuv4i16 = 978, - ARM_VABDuv4i32 = 979, - ARM_VABDuv8i16 = 980, - ARM_VABDuv8i8 = 981, - ARM_VABSD = 982, - ARM_VABSH = 983, - ARM_VABSS = 984, - ARM_VABSfd = 985, - ARM_VABSfq = 986, - ARM_VABShd = 987, - ARM_VABShq = 988, - ARM_VABSv16i8 = 989, - ARM_VABSv2i32 = 990, - ARM_VABSv4i16 = 991, - ARM_VABSv4i32 = 992, - ARM_VABSv8i16 = 993, - ARM_VABSv8i8 = 994, - ARM_VACGEfd = 995, - ARM_VACGEfq = 996, - ARM_VACGEhd = 997, - ARM_VACGEhq = 998, - ARM_VACGTfd = 999, - ARM_VACGTfq = 1000, - ARM_VACGThd = 1001, - ARM_VACGThq = 1002, - ARM_VADDD = 1003, - ARM_VADDH = 1004, - ARM_VADDHNv2i32 = 1005, - ARM_VADDHNv4i16 = 1006, - ARM_VADDHNv8i8 = 1007, - ARM_VADDLsv2i64 = 1008, - ARM_VADDLsv4i32 = 1009, - ARM_VADDLsv8i16 = 1010, - ARM_VADDLuv2i64 = 1011, - ARM_VADDLuv4i32 = 1012, - ARM_VADDLuv8i16 = 1013, - ARM_VADDS = 1014, - ARM_VADDWsv2i64 = 1015, - ARM_VADDWsv4i32 = 1016, - ARM_VADDWsv8i16 = 1017, - ARM_VADDWuv2i64 = 1018, - ARM_VADDWuv4i32 = 1019, - ARM_VADDWuv8i16 = 1020, - ARM_VADDfd = 1021, - ARM_VADDfq = 1022, - ARM_VADDhd = 1023, - ARM_VADDhq = 1024, - ARM_VADDv16i8 = 1025, - ARM_VADDv1i64 = 1026, - ARM_VADDv2i32 = 1027, - ARM_VADDv2i64 = 1028, - ARM_VADDv4i16 = 1029, - ARM_VADDv4i32 = 1030, - ARM_VADDv8i16 = 1031, - ARM_VADDv8i8 = 1032, - ARM_VANDd = 1033, - ARM_VANDq = 1034, - ARM_VBICd = 1035, - ARM_VBICiv2i32 = 1036, - ARM_VBICiv4i16 = 1037, - ARM_VBICiv4i32 = 1038, - ARM_VBICiv8i16 = 1039, - ARM_VBICq = 1040, - ARM_VBIFd = 1041, - ARM_VBIFq = 1042, - ARM_VBITd = 1043, - ARM_VBITq = 1044, - ARM_VBSLd = 1045, - ARM_VBSLq = 1046, - ARM_VCADDv2f32 = 1047, - ARM_VCADDv4f16 = 1048, - ARM_VCADDv4f32 = 1049, - ARM_VCADDv8f16 = 1050, - ARM_VCEQfd = 1051, - ARM_VCEQfq = 1052, - ARM_VCEQhd = 1053, - ARM_VCEQhq = 1054, - ARM_VCEQv16i8 = 1055, - ARM_VCEQv2i32 = 1056, - ARM_VCEQv4i16 = 1057, - ARM_VCEQv4i32 = 1058, - ARM_VCEQv8i16 = 1059, - ARM_VCEQv8i8 = 1060, - ARM_VCEQzv16i8 = 1061, - ARM_VCEQzv2f32 = 1062, - ARM_VCEQzv2i32 = 1063, - ARM_VCEQzv4f16 = 1064, - ARM_VCEQzv4f32 = 1065, - ARM_VCEQzv4i16 = 1066, - ARM_VCEQzv4i32 = 1067, - ARM_VCEQzv8f16 = 1068, - ARM_VCEQzv8i16 = 1069, - ARM_VCEQzv8i8 = 1070, - ARM_VCGEfd = 1071, - ARM_VCGEfq = 1072, - ARM_VCGEhd = 1073, - ARM_VCGEhq = 1074, - ARM_VCGEsv16i8 = 1075, - ARM_VCGEsv2i32 = 1076, - ARM_VCGEsv4i16 = 1077, - ARM_VCGEsv4i32 = 1078, - ARM_VCGEsv8i16 = 1079, - ARM_VCGEsv8i8 = 1080, - ARM_VCGEuv16i8 = 1081, - ARM_VCGEuv2i32 = 1082, - ARM_VCGEuv4i16 = 1083, - ARM_VCGEuv4i32 = 1084, - ARM_VCGEuv8i16 = 1085, - ARM_VCGEuv8i8 = 1086, - ARM_VCGEzv16i8 = 1087, - ARM_VCGEzv2f32 = 1088, - ARM_VCGEzv2i32 = 1089, - ARM_VCGEzv4f16 = 1090, - ARM_VCGEzv4f32 = 1091, - ARM_VCGEzv4i16 = 1092, - ARM_VCGEzv4i32 = 1093, - ARM_VCGEzv8f16 = 1094, - ARM_VCGEzv8i16 = 1095, - ARM_VCGEzv8i8 = 1096, - ARM_VCGTfd = 1097, - ARM_VCGTfq = 1098, - ARM_VCGThd = 1099, - ARM_VCGThq = 1100, - ARM_VCGTsv16i8 = 1101, - ARM_VCGTsv2i32 = 1102, - ARM_VCGTsv4i16 = 1103, - ARM_VCGTsv4i32 = 1104, - ARM_VCGTsv8i16 = 1105, - ARM_VCGTsv8i8 = 1106, - ARM_VCGTuv16i8 = 1107, - ARM_VCGTuv2i32 = 1108, - ARM_VCGTuv4i16 = 1109, - ARM_VCGTuv4i32 = 1110, - ARM_VCGTuv8i16 = 1111, - ARM_VCGTuv8i8 = 1112, - ARM_VCGTzv16i8 = 1113, - ARM_VCGTzv2f32 = 1114, - ARM_VCGTzv2i32 = 1115, - ARM_VCGTzv4f16 = 1116, - ARM_VCGTzv4f32 = 1117, - ARM_VCGTzv4i16 = 1118, - ARM_VCGTzv4i32 = 1119, - ARM_VCGTzv8f16 = 1120, - ARM_VCGTzv8i16 = 1121, - ARM_VCGTzv8i8 = 1122, - ARM_VCLEzv16i8 = 1123, - ARM_VCLEzv2f32 = 1124, - ARM_VCLEzv2i32 = 1125, - ARM_VCLEzv4f16 = 1126, - ARM_VCLEzv4f32 = 1127, - ARM_VCLEzv4i16 = 1128, - ARM_VCLEzv4i32 = 1129, - ARM_VCLEzv8f16 = 1130, - ARM_VCLEzv8i16 = 1131, - ARM_VCLEzv8i8 = 1132, - ARM_VCLSv16i8 = 1133, - ARM_VCLSv2i32 = 1134, - ARM_VCLSv4i16 = 1135, - ARM_VCLSv4i32 = 1136, - ARM_VCLSv8i16 = 1137, - ARM_VCLSv8i8 = 1138, - ARM_VCLTzv16i8 = 1139, - ARM_VCLTzv2f32 = 1140, - ARM_VCLTzv2i32 = 1141, - ARM_VCLTzv4f16 = 1142, - ARM_VCLTzv4f32 = 1143, - ARM_VCLTzv4i16 = 1144, - ARM_VCLTzv4i32 = 1145, - ARM_VCLTzv8f16 = 1146, - ARM_VCLTzv8i16 = 1147, - ARM_VCLTzv8i8 = 1148, - ARM_VCLZv16i8 = 1149, - ARM_VCLZv2i32 = 1150, - ARM_VCLZv4i16 = 1151, - ARM_VCLZv4i32 = 1152, - ARM_VCLZv8i16 = 1153, - ARM_VCLZv8i8 = 1154, - ARM_VCMLAv2f32 = 1155, - ARM_VCMLAv2f32_indexed = 1156, - ARM_VCMLAv4f16 = 1157, - ARM_VCMLAv4f16_indexed = 1158, - ARM_VCMLAv4f32 = 1159, - ARM_VCMLAv4f32_indexed = 1160, - ARM_VCMLAv8f16 = 1161, - ARM_VCMLAv8f16_indexed = 1162, - ARM_VCMPD = 1163, - ARM_VCMPED = 1164, - ARM_VCMPEH = 1165, - ARM_VCMPES = 1166, - ARM_VCMPEZD = 1167, - ARM_VCMPEZH = 1168, - ARM_VCMPEZS = 1169, - ARM_VCMPH = 1170, - ARM_VCMPS = 1171, - ARM_VCMPZD = 1172, - ARM_VCMPZH = 1173, - ARM_VCMPZS = 1174, - ARM_VCNTd = 1175, - ARM_VCNTq = 1176, - ARM_VCVTANSDf = 1177, - ARM_VCVTANSDh = 1178, - ARM_VCVTANSQf = 1179, - ARM_VCVTANSQh = 1180, - ARM_VCVTANUDf = 1181, - ARM_VCVTANUDh = 1182, - ARM_VCVTANUQf = 1183, - ARM_VCVTANUQh = 1184, - ARM_VCVTASD = 1185, - ARM_VCVTASH = 1186, - ARM_VCVTASS = 1187, - ARM_VCVTAUD = 1188, - ARM_VCVTAUH = 1189, - ARM_VCVTAUS = 1190, - ARM_VCVTBDH = 1191, - ARM_VCVTBHD = 1192, - ARM_VCVTBHS = 1193, - ARM_VCVTBSH = 1194, - ARM_VCVTDS = 1195, - ARM_VCVTMNSDf = 1196, - ARM_VCVTMNSDh = 1197, - ARM_VCVTMNSQf = 1198, - ARM_VCVTMNSQh = 1199, - ARM_VCVTMNUDf = 1200, - ARM_VCVTMNUDh = 1201, - ARM_VCVTMNUQf = 1202, - ARM_VCVTMNUQh = 1203, - ARM_VCVTMSD = 1204, - ARM_VCVTMSH = 1205, - ARM_VCVTMSS = 1206, - ARM_VCVTMUD = 1207, - ARM_VCVTMUH = 1208, - ARM_VCVTMUS = 1209, - ARM_VCVTNNSDf = 1210, - ARM_VCVTNNSDh = 1211, - ARM_VCVTNNSQf = 1212, - ARM_VCVTNNSQh = 1213, - ARM_VCVTNNUDf = 1214, - ARM_VCVTNNUDh = 1215, - ARM_VCVTNNUQf = 1216, - ARM_VCVTNNUQh = 1217, - ARM_VCVTNSD = 1218, - ARM_VCVTNSH = 1219, - ARM_VCVTNSS = 1220, - ARM_VCVTNUD = 1221, - ARM_VCVTNUH = 1222, - ARM_VCVTNUS = 1223, - ARM_VCVTPNSDf = 1224, - ARM_VCVTPNSDh = 1225, - ARM_VCVTPNSQf = 1226, - ARM_VCVTPNSQh = 1227, - ARM_VCVTPNUDf = 1228, - ARM_VCVTPNUDh = 1229, - ARM_VCVTPNUQf = 1230, - ARM_VCVTPNUQh = 1231, - ARM_VCVTPSD = 1232, - ARM_VCVTPSH = 1233, - ARM_VCVTPSS = 1234, - ARM_VCVTPUD = 1235, - ARM_VCVTPUH = 1236, - ARM_VCVTPUS = 1237, - ARM_VCVTSD = 1238, - ARM_VCVTTDH = 1239, - ARM_VCVTTHD = 1240, - ARM_VCVTTHS = 1241, - ARM_VCVTTSH = 1242, - ARM_VCVTf2h = 1243, - ARM_VCVTf2sd = 1244, - ARM_VCVTf2sq = 1245, - ARM_VCVTf2ud = 1246, - ARM_VCVTf2uq = 1247, - ARM_VCVTf2xsd = 1248, - ARM_VCVTf2xsq = 1249, - ARM_VCVTf2xud = 1250, - ARM_VCVTf2xuq = 1251, - ARM_VCVTh2f = 1252, - ARM_VCVTh2sd = 1253, - ARM_VCVTh2sq = 1254, - ARM_VCVTh2ud = 1255, - ARM_VCVTh2uq = 1256, - ARM_VCVTh2xsd = 1257, - ARM_VCVTh2xsq = 1258, - ARM_VCVTh2xud = 1259, - ARM_VCVTh2xuq = 1260, - ARM_VCVTs2fd = 1261, - ARM_VCVTs2fq = 1262, - ARM_VCVTs2hd = 1263, - ARM_VCVTs2hq = 1264, - ARM_VCVTu2fd = 1265, - ARM_VCVTu2fq = 1266, - ARM_VCVTu2hd = 1267, - ARM_VCVTu2hq = 1268, - ARM_VCVTxs2fd = 1269, - ARM_VCVTxs2fq = 1270, - ARM_VCVTxs2hd = 1271, - ARM_VCVTxs2hq = 1272, - ARM_VCVTxu2fd = 1273, - ARM_VCVTxu2fq = 1274, - ARM_VCVTxu2hd = 1275, - ARM_VCVTxu2hq = 1276, - ARM_VDIVD = 1277, - ARM_VDIVH = 1278, - ARM_VDIVS = 1279, - ARM_VDUP16d = 1280, - ARM_VDUP16q = 1281, - ARM_VDUP32d = 1282, - ARM_VDUP32q = 1283, - ARM_VDUP8d = 1284, - ARM_VDUP8q = 1285, - ARM_VDUPLN16d = 1286, - ARM_VDUPLN16q = 1287, - ARM_VDUPLN32d = 1288, - ARM_VDUPLN32q = 1289, - ARM_VDUPLN8d = 1290, - ARM_VDUPLN8q = 1291, - ARM_VEORd = 1292, - ARM_VEORq = 1293, - ARM_VEXTd16 = 1294, - ARM_VEXTd32 = 1295, - ARM_VEXTd8 = 1296, - ARM_VEXTq16 = 1297, - ARM_VEXTq32 = 1298, - ARM_VEXTq64 = 1299, - ARM_VEXTq8 = 1300, - ARM_VFMAD = 1301, - ARM_VFMAH = 1302, - ARM_VFMAS = 1303, - ARM_VFMAfd = 1304, - ARM_VFMAfq = 1305, - ARM_VFMAhd = 1306, - ARM_VFMAhq = 1307, - ARM_VFMSD = 1308, - ARM_VFMSH = 1309, - ARM_VFMSS = 1310, - ARM_VFMSfd = 1311, - ARM_VFMSfq = 1312, - ARM_VFMShd = 1313, - ARM_VFMShq = 1314, - ARM_VFNMAD = 1315, - ARM_VFNMAH = 1316, - ARM_VFNMAS = 1317, - ARM_VFNMSD = 1318, - ARM_VFNMSH = 1319, - ARM_VFNMSS = 1320, - ARM_VGETLNi32 = 1321, - ARM_VGETLNs16 = 1322, - ARM_VGETLNs8 = 1323, - ARM_VGETLNu16 = 1324, - ARM_VGETLNu8 = 1325, - ARM_VHADDsv16i8 = 1326, - ARM_VHADDsv2i32 = 1327, - ARM_VHADDsv4i16 = 1328, - ARM_VHADDsv4i32 = 1329, - ARM_VHADDsv8i16 = 1330, - ARM_VHADDsv8i8 = 1331, - ARM_VHADDuv16i8 = 1332, - ARM_VHADDuv2i32 = 1333, - ARM_VHADDuv4i16 = 1334, - ARM_VHADDuv4i32 = 1335, - ARM_VHADDuv8i16 = 1336, - ARM_VHADDuv8i8 = 1337, - ARM_VHSUBsv16i8 = 1338, - ARM_VHSUBsv2i32 = 1339, - ARM_VHSUBsv4i16 = 1340, - ARM_VHSUBsv4i32 = 1341, - ARM_VHSUBsv8i16 = 1342, - ARM_VHSUBsv8i8 = 1343, - ARM_VHSUBuv16i8 = 1344, - ARM_VHSUBuv2i32 = 1345, - ARM_VHSUBuv4i16 = 1346, - ARM_VHSUBuv4i32 = 1347, - ARM_VHSUBuv8i16 = 1348, - ARM_VHSUBuv8i8 = 1349, - ARM_VINSH = 1350, - ARM_VJCVT = 1351, - ARM_VLD1DUPd16 = 1352, - ARM_VLD1DUPd16wb_fixed = 1353, - ARM_VLD1DUPd16wb_register = 1354, - ARM_VLD1DUPd32 = 1355, - ARM_VLD1DUPd32wb_fixed = 1356, - ARM_VLD1DUPd32wb_register = 1357, - ARM_VLD1DUPd8 = 1358, - ARM_VLD1DUPd8wb_fixed = 1359, - ARM_VLD1DUPd8wb_register = 1360, - ARM_VLD1DUPq16 = 1361, - ARM_VLD1DUPq16wb_fixed = 1362, - ARM_VLD1DUPq16wb_register = 1363, - ARM_VLD1DUPq32 = 1364, - ARM_VLD1DUPq32wb_fixed = 1365, - ARM_VLD1DUPq32wb_register = 1366, - ARM_VLD1DUPq8 = 1367, - ARM_VLD1DUPq8wb_fixed = 1368, - ARM_VLD1DUPq8wb_register = 1369, - ARM_VLD1LNd16 = 1370, - ARM_VLD1LNd16_UPD = 1371, - ARM_VLD1LNd32 = 1372, - ARM_VLD1LNd32_UPD = 1373, - ARM_VLD1LNd8 = 1374, - ARM_VLD1LNd8_UPD = 1375, - ARM_VLD1d16 = 1382, - ARM_VLD1d16Q = 1383, - ARM_VLD1d16Qwb_fixed = 1385, - ARM_VLD1d16Qwb_register = 1386, - ARM_VLD1d16T = 1387, - ARM_VLD1d16Twb_fixed = 1389, - ARM_VLD1d16Twb_register = 1390, - ARM_VLD1d16wb_fixed = 1391, - ARM_VLD1d16wb_register = 1392, - ARM_VLD1d32 = 1393, - ARM_VLD1d32Q = 1394, - ARM_VLD1d32Qwb_fixed = 1396, - ARM_VLD1d32Qwb_register = 1397, - ARM_VLD1d32T = 1398, - ARM_VLD1d32Twb_fixed = 1400, - ARM_VLD1d32Twb_register = 1401, - ARM_VLD1d32wb_fixed = 1402, - ARM_VLD1d32wb_register = 1403, - ARM_VLD1d64 = 1404, - ARM_VLD1d64Q = 1405, - ARM_VLD1d64Qwb_fixed = 1409, - ARM_VLD1d64Qwb_register = 1410, - ARM_VLD1d64T = 1411, - ARM_VLD1d64Twb_fixed = 1415, - ARM_VLD1d64Twb_register = 1416, - ARM_VLD1d64wb_fixed = 1417, - ARM_VLD1d64wb_register = 1418, - ARM_VLD1d8 = 1419, - ARM_VLD1d8Q = 1420, - ARM_VLD1d8Qwb_fixed = 1422, - ARM_VLD1d8Qwb_register = 1423, - ARM_VLD1d8T = 1424, - ARM_VLD1d8Twb_fixed = 1426, - ARM_VLD1d8Twb_register = 1427, - ARM_VLD1d8wb_fixed = 1428, - ARM_VLD1d8wb_register = 1429, - ARM_VLD1q16 = 1430, - ARM_VLD1q16wb_fixed = 1435, - ARM_VLD1q16wb_register = 1436, - ARM_VLD1q32 = 1437, - ARM_VLD1q32wb_fixed = 1442, - ARM_VLD1q32wb_register = 1443, - ARM_VLD1q64 = 1444, - ARM_VLD1q64wb_fixed = 1449, - ARM_VLD1q64wb_register = 1450, - ARM_VLD1q8 = 1451, - ARM_VLD1q8wb_fixed = 1456, - ARM_VLD1q8wb_register = 1457, - ARM_VLD2DUPd16 = 1458, - ARM_VLD2DUPd16wb_fixed = 1459, - ARM_VLD2DUPd16wb_register = 1460, - ARM_VLD2DUPd16x2 = 1461, - ARM_VLD2DUPd16x2wb_fixed = 1462, - ARM_VLD2DUPd16x2wb_register = 1463, - ARM_VLD2DUPd32 = 1464, - ARM_VLD2DUPd32wb_fixed = 1465, - ARM_VLD2DUPd32wb_register = 1466, - ARM_VLD2DUPd32x2 = 1467, - ARM_VLD2DUPd32x2wb_fixed = 1468, - ARM_VLD2DUPd32x2wb_register = 1469, - ARM_VLD2DUPd8 = 1470, - ARM_VLD2DUPd8wb_fixed = 1471, - ARM_VLD2DUPd8wb_register = 1472, - ARM_VLD2DUPd8x2 = 1473, - ARM_VLD2DUPd8x2wb_fixed = 1474, - ARM_VLD2DUPd8x2wb_register = 1475, - ARM_VLD2LNd16 = 1482, - ARM_VLD2LNd16_UPD = 1485, - ARM_VLD2LNd32 = 1486, - ARM_VLD2LNd32_UPD = 1489, - ARM_VLD2LNd8 = 1490, - ARM_VLD2LNd8_UPD = 1493, - ARM_VLD2LNq16 = 1494, - ARM_VLD2LNq16_UPD = 1497, - ARM_VLD2LNq32 = 1498, - ARM_VLD2LNq32_UPD = 1501, - ARM_VLD2b16 = 1502, - ARM_VLD2b16wb_fixed = 1503, - ARM_VLD2b16wb_register = 1504, - ARM_VLD2b32 = 1505, - ARM_VLD2b32wb_fixed = 1506, - ARM_VLD2b32wb_register = 1507, - ARM_VLD2b8 = 1508, - ARM_VLD2b8wb_fixed = 1509, - ARM_VLD2b8wb_register = 1510, - ARM_VLD2d16 = 1511, - ARM_VLD2d16wb_fixed = 1512, - ARM_VLD2d16wb_register = 1513, - ARM_VLD2d32 = 1514, - ARM_VLD2d32wb_fixed = 1515, - ARM_VLD2d32wb_register = 1516, - ARM_VLD2d8 = 1517, - ARM_VLD2d8wb_fixed = 1518, - ARM_VLD2d8wb_register = 1519, - ARM_VLD2q16 = 1520, - ARM_VLD2q16wb_fixed = 1524, - ARM_VLD2q16wb_register = 1525, - ARM_VLD2q32 = 1526, - ARM_VLD2q32wb_fixed = 1530, - ARM_VLD2q32wb_register = 1531, - ARM_VLD2q8 = 1532, - ARM_VLD2q8wb_fixed = 1536, - ARM_VLD2q8wb_register = 1537, - ARM_VLD3DUPd16 = 1538, - ARM_VLD3DUPd16_UPD = 1541, - ARM_VLD3DUPd32 = 1542, - ARM_VLD3DUPd32_UPD = 1545, - ARM_VLD3DUPd8 = 1546, - ARM_VLD3DUPd8_UPD = 1549, - ARM_VLD3DUPq16 = 1550, - ARM_VLD3DUPq16_UPD = 1553, - ARM_VLD3DUPq32 = 1554, - ARM_VLD3DUPq32_UPD = 1557, - ARM_VLD3DUPq8 = 1558, - ARM_VLD3DUPq8_UPD = 1561, - ARM_VLD3LNd16 = 1562, - ARM_VLD3LNd16_UPD = 1565, - ARM_VLD3LNd32 = 1566, - ARM_VLD3LNd32_UPD = 1569, - ARM_VLD3LNd8 = 1570, - ARM_VLD3LNd8_UPD = 1573, - ARM_VLD3LNq16 = 1574, - ARM_VLD3LNq16_UPD = 1577, - ARM_VLD3LNq32 = 1578, - ARM_VLD3LNq32_UPD = 1581, - ARM_VLD3d16 = 1582, - ARM_VLD3d16_UPD = 1585, - ARM_VLD3d32 = 1586, - ARM_VLD3d32_UPD = 1589, - ARM_VLD3d8 = 1590, - ARM_VLD3d8_UPD = 1593, - ARM_VLD3q16 = 1594, - ARM_VLD3q16_UPD = 1596, - ARM_VLD3q32 = 1599, - ARM_VLD3q32_UPD = 1601, - ARM_VLD3q8 = 1604, - ARM_VLD3q8_UPD = 1606, - ARM_VLD4DUPd16 = 1609, - ARM_VLD4DUPd16_UPD = 1612, - ARM_VLD4DUPd32 = 1613, - ARM_VLD4DUPd32_UPD = 1616, - ARM_VLD4DUPd8 = 1617, - ARM_VLD4DUPd8_UPD = 1620, - ARM_VLD4DUPq16 = 1621, - ARM_VLD4DUPq16_UPD = 1624, - ARM_VLD4DUPq32 = 1625, - ARM_VLD4DUPq32_UPD = 1628, - ARM_VLD4DUPq8 = 1629, - ARM_VLD4DUPq8_UPD = 1632, - ARM_VLD4LNd16 = 1633, - ARM_VLD4LNd16_UPD = 1636, - ARM_VLD4LNd32 = 1637, - ARM_VLD4LNd32_UPD = 1640, - ARM_VLD4LNd8 = 1641, - ARM_VLD4LNd8_UPD = 1644, - ARM_VLD4LNq16 = 1645, - ARM_VLD4LNq16_UPD = 1648, - ARM_VLD4LNq32 = 1649, - ARM_VLD4LNq32_UPD = 1652, - ARM_VLD4d16 = 1653, - ARM_VLD4d16_UPD = 1656, - ARM_VLD4d32 = 1657, - ARM_VLD4d32_UPD = 1660, - ARM_VLD4d8 = 1661, - ARM_VLD4d8_UPD = 1664, - ARM_VLD4q16 = 1665, - ARM_VLD4q16_UPD = 1667, - ARM_VLD4q32 = 1670, - ARM_VLD4q32_UPD = 1672, - ARM_VLD4q8 = 1675, - ARM_VLD4q8_UPD = 1677, - ARM_VLDMDDB_UPD = 1680, - ARM_VLDMDIA = 1681, - ARM_VLDMDIA_UPD = 1682, - ARM_VLDMQIA = 1683, - ARM_VLDMSDB_UPD = 1684, - ARM_VLDMSIA = 1685, - ARM_VLDMSIA_UPD = 1686, - ARM_VLDRD = 1687, - ARM_VLDRH = 1688, - ARM_VLDRS = 1689, - ARM_VLLDM = 1690, - ARM_VLSTM = 1691, - ARM_VMAXNMD = 1692, - ARM_VMAXNMH = 1693, - ARM_VMAXNMNDf = 1694, - ARM_VMAXNMNDh = 1695, - ARM_VMAXNMNQf = 1696, - ARM_VMAXNMNQh = 1697, - ARM_VMAXNMS = 1698, - ARM_VMAXfd = 1699, - ARM_VMAXfq = 1700, - ARM_VMAXhd = 1701, - ARM_VMAXhq = 1702, - ARM_VMAXsv16i8 = 1703, - ARM_VMAXsv2i32 = 1704, - ARM_VMAXsv4i16 = 1705, - ARM_VMAXsv4i32 = 1706, - ARM_VMAXsv8i16 = 1707, - ARM_VMAXsv8i8 = 1708, - ARM_VMAXuv16i8 = 1709, - ARM_VMAXuv2i32 = 1710, - ARM_VMAXuv4i16 = 1711, - ARM_VMAXuv4i32 = 1712, - ARM_VMAXuv8i16 = 1713, - ARM_VMAXuv8i8 = 1714, - ARM_VMINNMD = 1715, - ARM_VMINNMH = 1716, - ARM_VMINNMNDf = 1717, - ARM_VMINNMNDh = 1718, - ARM_VMINNMNQf = 1719, - ARM_VMINNMNQh = 1720, - ARM_VMINNMS = 1721, - ARM_VMINfd = 1722, - ARM_VMINfq = 1723, - ARM_VMINhd = 1724, - ARM_VMINhq = 1725, - ARM_VMINsv16i8 = 1726, - ARM_VMINsv2i32 = 1727, - ARM_VMINsv4i16 = 1728, - ARM_VMINsv4i32 = 1729, - ARM_VMINsv8i16 = 1730, - ARM_VMINsv8i8 = 1731, - ARM_VMINuv16i8 = 1732, - ARM_VMINuv2i32 = 1733, - ARM_VMINuv4i16 = 1734, - ARM_VMINuv4i32 = 1735, - ARM_VMINuv8i16 = 1736, - ARM_VMINuv8i8 = 1737, - ARM_VMLAD = 1738, - ARM_VMLAH = 1739, - ARM_VMLALslsv2i32 = 1740, - ARM_VMLALslsv4i16 = 1741, - ARM_VMLALsluv2i32 = 1742, - ARM_VMLALsluv4i16 = 1743, - ARM_VMLALsv2i64 = 1744, - ARM_VMLALsv4i32 = 1745, - ARM_VMLALsv8i16 = 1746, - ARM_VMLALuv2i64 = 1747, - ARM_VMLALuv4i32 = 1748, - ARM_VMLALuv8i16 = 1749, - ARM_VMLAS = 1750, - ARM_VMLAfd = 1751, - ARM_VMLAfq = 1752, - ARM_VMLAhd = 1753, - ARM_VMLAhq = 1754, - ARM_VMLAslfd = 1755, - ARM_VMLAslfq = 1756, - ARM_VMLAslhd = 1757, - ARM_VMLAslhq = 1758, - ARM_VMLAslv2i32 = 1759, - ARM_VMLAslv4i16 = 1760, - ARM_VMLAslv4i32 = 1761, - ARM_VMLAslv8i16 = 1762, - ARM_VMLAv16i8 = 1763, - ARM_VMLAv2i32 = 1764, - ARM_VMLAv4i16 = 1765, - ARM_VMLAv4i32 = 1766, - ARM_VMLAv8i16 = 1767, - ARM_VMLAv8i8 = 1768, - ARM_VMLSD = 1769, - ARM_VMLSH = 1770, - ARM_VMLSLslsv2i32 = 1771, - ARM_VMLSLslsv4i16 = 1772, - ARM_VMLSLsluv2i32 = 1773, - ARM_VMLSLsluv4i16 = 1774, - ARM_VMLSLsv2i64 = 1775, - ARM_VMLSLsv4i32 = 1776, - ARM_VMLSLsv8i16 = 1777, - ARM_VMLSLuv2i64 = 1778, - ARM_VMLSLuv4i32 = 1779, - ARM_VMLSLuv8i16 = 1780, - ARM_VMLSS = 1781, - ARM_VMLSfd = 1782, - ARM_VMLSfq = 1783, - ARM_VMLShd = 1784, - ARM_VMLShq = 1785, - ARM_VMLSslfd = 1786, - ARM_VMLSslfq = 1787, - ARM_VMLSslhd = 1788, - ARM_VMLSslhq = 1789, - ARM_VMLSslv2i32 = 1790, - ARM_VMLSslv4i16 = 1791, - ARM_VMLSslv4i32 = 1792, - ARM_VMLSslv8i16 = 1793, - ARM_VMLSv16i8 = 1794, - ARM_VMLSv2i32 = 1795, - ARM_VMLSv4i16 = 1796, - ARM_VMLSv4i32 = 1797, - ARM_VMLSv8i16 = 1798, - ARM_VMLSv8i8 = 1799, - ARM_VMOVD = 1800, - ARM_VMOVDRR = 1801, - ARM_VMOVH = 1802, - ARM_VMOVHR = 1803, - ARM_VMOVLsv2i64 = 1804, - ARM_VMOVLsv4i32 = 1805, - ARM_VMOVLsv8i16 = 1806, - ARM_VMOVLuv2i64 = 1807, - ARM_VMOVLuv4i32 = 1808, - ARM_VMOVLuv8i16 = 1809, - ARM_VMOVNv2i32 = 1810, - ARM_VMOVNv4i16 = 1811, - ARM_VMOVNv8i8 = 1812, - ARM_VMOVRH = 1813, - ARM_VMOVRRD = 1814, - ARM_VMOVRRS = 1815, - ARM_VMOVRS = 1816, - ARM_VMOVS = 1817, - ARM_VMOVSR = 1818, - ARM_VMOVSRR = 1819, - ARM_VMOVv16i8 = 1820, - ARM_VMOVv1i64 = 1821, - ARM_VMOVv2f32 = 1822, - ARM_VMOVv2i32 = 1823, - ARM_VMOVv2i64 = 1824, - ARM_VMOVv4f32 = 1825, - ARM_VMOVv4i16 = 1826, - ARM_VMOVv4i32 = 1827, - ARM_VMOVv8i16 = 1828, - ARM_VMOVv8i8 = 1829, - ARM_VMRS = 1830, - ARM_VMRS_FPEXC = 1831, - ARM_VMRS_FPINST = 1832, - ARM_VMRS_FPINST2 = 1833, - ARM_VMRS_FPSID = 1834, - ARM_VMRS_MVFR0 = 1835, - ARM_VMRS_MVFR1 = 1836, - ARM_VMRS_MVFR2 = 1837, - ARM_VMSR = 1838, - ARM_VMSR_FPEXC = 1839, - ARM_VMSR_FPINST = 1840, - ARM_VMSR_FPINST2 = 1841, - ARM_VMSR_FPSID = 1842, - ARM_VMULD = 1843, - ARM_VMULH = 1844, - ARM_VMULLp64 = 1845, - ARM_VMULLp8 = 1846, - ARM_VMULLslsv2i32 = 1847, - ARM_VMULLslsv4i16 = 1848, - ARM_VMULLsluv2i32 = 1849, - ARM_VMULLsluv4i16 = 1850, - ARM_VMULLsv2i64 = 1851, - ARM_VMULLsv4i32 = 1852, - ARM_VMULLsv8i16 = 1853, - ARM_VMULLuv2i64 = 1854, - ARM_VMULLuv4i32 = 1855, - ARM_VMULLuv8i16 = 1856, - ARM_VMULS = 1857, - ARM_VMULfd = 1858, - ARM_VMULfq = 1859, - ARM_VMULhd = 1860, - ARM_VMULhq = 1861, - ARM_VMULpd = 1862, - ARM_VMULpq = 1863, - ARM_VMULslfd = 1864, - ARM_VMULslfq = 1865, - ARM_VMULslhd = 1866, - ARM_VMULslhq = 1867, - ARM_VMULslv2i32 = 1868, - ARM_VMULslv4i16 = 1869, - ARM_VMULslv4i32 = 1870, - ARM_VMULslv8i16 = 1871, - ARM_VMULv16i8 = 1872, - ARM_VMULv2i32 = 1873, - ARM_VMULv4i16 = 1874, - ARM_VMULv4i32 = 1875, - ARM_VMULv8i16 = 1876, - ARM_VMULv8i8 = 1877, - ARM_VMVNd = 1878, - ARM_VMVNq = 1879, - ARM_VMVNv2i32 = 1880, - ARM_VMVNv4i16 = 1881, - ARM_VMVNv4i32 = 1882, - ARM_VMVNv8i16 = 1883, - ARM_VNEGD = 1884, - ARM_VNEGH = 1885, - ARM_VNEGS = 1886, - ARM_VNEGf32q = 1887, - ARM_VNEGfd = 1888, - ARM_VNEGhd = 1889, - ARM_VNEGhq = 1890, - ARM_VNEGs16d = 1891, - ARM_VNEGs16q = 1892, - ARM_VNEGs32d = 1893, - ARM_VNEGs32q = 1894, - ARM_VNEGs8d = 1895, - ARM_VNEGs8q = 1896, - ARM_VNMLAD = 1897, - ARM_VNMLAH = 1898, - ARM_VNMLAS = 1899, - ARM_VNMLSD = 1900, - ARM_VNMLSH = 1901, - ARM_VNMLSS = 1902, - ARM_VNMULD = 1903, - ARM_VNMULH = 1904, - ARM_VNMULS = 1905, - ARM_VORNd = 1906, - ARM_VORNq = 1907, - ARM_VORRd = 1908, - ARM_VORRiv2i32 = 1909, - ARM_VORRiv4i16 = 1910, - ARM_VORRiv4i32 = 1911, - ARM_VORRiv8i16 = 1912, - ARM_VORRq = 1913, - ARM_VPADALsv16i8 = 1914, - ARM_VPADALsv2i32 = 1915, - ARM_VPADALsv4i16 = 1916, - ARM_VPADALsv4i32 = 1917, - ARM_VPADALsv8i16 = 1918, - ARM_VPADALsv8i8 = 1919, - ARM_VPADALuv16i8 = 1920, - ARM_VPADALuv2i32 = 1921, - ARM_VPADALuv4i16 = 1922, - ARM_VPADALuv4i32 = 1923, - ARM_VPADALuv8i16 = 1924, - ARM_VPADALuv8i8 = 1925, - ARM_VPADDLsv16i8 = 1926, - ARM_VPADDLsv2i32 = 1927, - ARM_VPADDLsv4i16 = 1928, - ARM_VPADDLsv4i32 = 1929, - ARM_VPADDLsv8i16 = 1930, - ARM_VPADDLsv8i8 = 1931, - ARM_VPADDLuv16i8 = 1932, - ARM_VPADDLuv2i32 = 1933, - ARM_VPADDLuv4i16 = 1934, - ARM_VPADDLuv4i32 = 1935, - ARM_VPADDLuv8i16 = 1936, - ARM_VPADDLuv8i8 = 1937, - ARM_VPADDf = 1938, - ARM_VPADDh = 1939, - ARM_VPADDi16 = 1940, - ARM_VPADDi32 = 1941, - ARM_VPADDi8 = 1942, - ARM_VPMAXf = 1943, - ARM_VPMAXh = 1944, - ARM_VPMAXs16 = 1945, - ARM_VPMAXs32 = 1946, - ARM_VPMAXs8 = 1947, - ARM_VPMAXu16 = 1948, - ARM_VPMAXu32 = 1949, - ARM_VPMAXu8 = 1950, - ARM_VPMINf = 1951, - ARM_VPMINh = 1952, - ARM_VPMINs16 = 1953, - ARM_VPMINs32 = 1954, - ARM_VPMINs8 = 1955, - ARM_VPMINu16 = 1956, - ARM_VPMINu32 = 1957, - ARM_VPMINu8 = 1958, - ARM_VQABSv16i8 = 1959, - ARM_VQABSv2i32 = 1960, - ARM_VQABSv4i16 = 1961, - ARM_VQABSv4i32 = 1962, - ARM_VQABSv8i16 = 1963, - ARM_VQABSv8i8 = 1964, - ARM_VQADDsv16i8 = 1965, - ARM_VQADDsv1i64 = 1966, - ARM_VQADDsv2i32 = 1967, - ARM_VQADDsv2i64 = 1968, - ARM_VQADDsv4i16 = 1969, - ARM_VQADDsv4i32 = 1970, - ARM_VQADDsv8i16 = 1971, - ARM_VQADDsv8i8 = 1972, - ARM_VQADDuv16i8 = 1973, - ARM_VQADDuv1i64 = 1974, - ARM_VQADDuv2i32 = 1975, - ARM_VQADDuv2i64 = 1976, - ARM_VQADDuv4i16 = 1977, - ARM_VQADDuv4i32 = 1978, - ARM_VQADDuv8i16 = 1979, - ARM_VQADDuv8i8 = 1980, - ARM_VQDMLALslv2i32 = 1981, - ARM_VQDMLALslv4i16 = 1982, - ARM_VQDMLALv2i64 = 1983, - ARM_VQDMLALv4i32 = 1984, - ARM_VQDMLSLslv2i32 = 1985, - ARM_VQDMLSLslv4i16 = 1986, - ARM_VQDMLSLv2i64 = 1987, - ARM_VQDMLSLv4i32 = 1988, - ARM_VQDMULHslv2i32 = 1989, - ARM_VQDMULHslv4i16 = 1990, - ARM_VQDMULHslv4i32 = 1991, - ARM_VQDMULHslv8i16 = 1992, - ARM_VQDMULHv2i32 = 1993, - ARM_VQDMULHv4i16 = 1994, - ARM_VQDMULHv4i32 = 1995, - ARM_VQDMULHv8i16 = 1996, - ARM_VQDMULLslv2i32 = 1997, - ARM_VQDMULLslv4i16 = 1998, - ARM_VQDMULLv2i64 = 1999, - ARM_VQDMULLv4i32 = 2000, - ARM_VQMOVNsuv2i32 = 2001, - ARM_VQMOVNsuv4i16 = 2002, - ARM_VQMOVNsuv8i8 = 2003, - ARM_VQMOVNsv2i32 = 2004, - ARM_VQMOVNsv4i16 = 2005, - ARM_VQMOVNsv8i8 = 2006, - ARM_VQMOVNuv2i32 = 2007, - ARM_VQMOVNuv4i16 = 2008, - ARM_VQMOVNuv8i8 = 2009, - ARM_VQNEGv16i8 = 2010, - ARM_VQNEGv2i32 = 2011, - ARM_VQNEGv4i16 = 2012, - ARM_VQNEGv4i32 = 2013, - ARM_VQNEGv8i16 = 2014, - ARM_VQNEGv8i8 = 2015, - ARM_VQRDMLAHslv2i32 = 2016, - ARM_VQRDMLAHslv4i16 = 2017, - ARM_VQRDMLAHslv4i32 = 2018, - ARM_VQRDMLAHslv8i16 = 2019, - ARM_VQRDMLAHv2i32 = 2020, - ARM_VQRDMLAHv4i16 = 2021, - ARM_VQRDMLAHv4i32 = 2022, - ARM_VQRDMLAHv8i16 = 2023, - ARM_VQRDMLSHslv2i32 = 2024, - ARM_VQRDMLSHslv4i16 = 2025, - ARM_VQRDMLSHslv4i32 = 2026, - ARM_VQRDMLSHslv8i16 = 2027, - ARM_VQRDMLSHv2i32 = 2028, - ARM_VQRDMLSHv4i16 = 2029, - ARM_VQRDMLSHv4i32 = 2030, - ARM_VQRDMLSHv8i16 = 2031, - ARM_VQRDMULHslv2i32 = 2032, - ARM_VQRDMULHslv4i16 = 2033, - ARM_VQRDMULHslv4i32 = 2034, - ARM_VQRDMULHslv8i16 = 2035, - ARM_VQRDMULHv2i32 = 2036, - ARM_VQRDMULHv4i16 = 2037, - ARM_VQRDMULHv4i32 = 2038, - ARM_VQRDMULHv8i16 = 2039, - ARM_VQRSHLsv16i8 = 2040, - ARM_VQRSHLsv1i64 = 2041, - ARM_VQRSHLsv2i32 = 2042, - ARM_VQRSHLsv2i64 = 2043, - ARM_VQRSHLsv4i16 = 2044, - ARM_VQRSHLsv4i32 = 2045, - ARM_VQRSHLsv8i16 = 2046, - ARM_VQRSHLsv8i8 = 2047, - ARM_VQRSHLuv16i8 = 2048, - ARM_VQRSHLuv1i64 = 2049, - ARM_VQRSHLuv2i32 = 2050, - ARM_VQRSHLuv2i64 = 2051, - ARM_VQRSHLuv4i16 = 2052, - ARM_VQRSHLuv4i32 = 2053, - ARM_VQRSHLuv8i16 = 2054, - ARM_VQRSHLuv8i8 = 2055, - ARM_VQRSHRNsv2i32 = 2056, - ARM_VQRSHRNsv4i16 = 2057, - ARM_VQRSHRNsv8i8 = 2058, - ARM_VQRSHRNuv2i32 = 2059, - ARM_VQRSHRNuv4i16 = 2060, - ARM_VQRSHRNuv8i8 = 2061, - ARM_VQRSHRUNv2i32 = 2062, - ARM_VQRSHRUNv4i16 = 2063, - ARM_VQRSHRUNv8i8 = 2064, - ARM_VQSHLsiv16i8 = 2065, - ARM_VQSHLsiv1i64 = 2066, - ARM_VQSHLsiv2i32 = 2067, - ARM_VQSHLsiv2i64 = 2068, - ARM_VQSHLsiv4i16 = 2069, - ARM_VQSHLsiv4i32 = 2070, - ARM_VQSHLsiv8i16 = 2071, - ARM_VQSHLsiv8i8 = 2072, - ARM_VQSHLsuv16i8 = 2073, - ARM_VQSHLsuv1i64 = 2074, - ARM_VQSHLsuv2i32 = 2075, - ARM_VQSHLsuv2i64 = 2076, - ARM_VQSHLsuv4i16 = 2077, - ARM_VQSHLsuv4i32 = 2078, - ARM_VQSHLsuv8i16 = 2079, - ARM_VQSHLsuv8i8 = 2080, - ARM_VQSHLsv16i8 = 2081, - ARM_VQSHLsv1i64 = 2082, - ARM_VQSHLsv2i32 = 2083, - ARM_VQSHLsv2i64 = 2084, - ARM_VQSHLsv4i16 = 2085, - ARM_VQSHLsv4i32 = 2086, - ARM_VQSHLsv8i16 = 2087, - ARM_VQSHLsv8i8 = 2088, - ARM_VQSHLuiv16i8 = 2089, - ARM_VQSHLuiv1i64 = 2090, - ARM_VQSHLuiv2i32 = 2091, - ARM_VQSHLuiv2i64 = 2092, - ARM_VQSHLuiv4i16 = 2093, - ARM_VQSHLuiv4i32 = 2094, - ARM_VQSHLuiv8i16 = 2095, - ARM_VQSHLuiv8i8 = 2096, - ARM_VQSHLuv16i8 = 2097, - ARM_VQSHLuv1i64 = 2098, - ARM_VQSHLuv2i32 = 2099, - ARM_VQSHLuv2i64 = 2100, - ARM_VQSHLuv4i16 = 2101, - ARM_VQSHLuv4i32 = 2102, - ARM_VQSHLuv8i16 = 2103, - ARM_VQSHLuv8i8 = 2104, - ARM_VQSHRNsv2i32 = 2105, - ARM_VQSHRNsv4i16 = 2106, - ARM_VQSHRNsv8i8 = 2107, - ARM_VQSHRNuv2i32 = 2108, - ARM_VQSHRNuv4i16 = 2109, - ARM_VQSHRNuv8i8 = 2110, - ARM_VQSHRUNv2i32 = 2111, - ARM_VQSHRUNv4i16 = 2112, - ARM_VQSHRUNv8i8 = 2113, - ARM_VQSUBsv16i8 = 2114, - ARM_VQSUBsv1i64 = 2115, - ARM_VQSUBsv2i32 = 2116, - ARM_VQSUBsv2i64 = 2117, - ARM_VQSUBsv4i16 = 2118, - ARM_VQSUBsv4i32 = 2119, - ARM_VQSUBsv8i16 = 2120, - ARM_VQSUBsv8i8 = 2121, - ARM_VQSUBuv16i8 = 2122, - ARM_VQSUBuv1i64 = 2123, - ARM_VQSUBuv2i32 = 2124, - ARM_VQSUBuv2i64 = 2125, - ARM_VQSUBuv4i16 = 2126, - ARM_VQSUBuv4i32 = 2127, - ARM_VQSUBuv8i16 = 2128, - ARM_VQSUBuv8i8 = 2129, - ARM_VRADDHNv2i32 = 2130, - ARM_VRADDHNv4i16 = 2131, - ARM_VRADDHNv8i8 = 2132, - ARM_VRECPEd = 2133, - ARM_VRECPEfd = 2134, - ARM_VRECPEfq = 2135, - ARM_VRECPEhd = 2136, - ARM_VRECPEhq = 2137, - ARM_VRECPEq = 2138, - ARM_VRECPSfd = 2139, - ARM_VRECPSfq = 2140, - ARM_VRECPShd = 2141, - ARM_VRECPShq = 2142, - ARM_VREV16d8 = 2143, - ARM_VREV16q8 = 2144, - ARM_VREV32d16 = 2145, - ARM_VREV32d8 = 2146, - ARM_VREV32q16 = 2147, - ARM_VREV32q8 = 2148, - ARM_VREV64d16 = 2149, - ARM_VREV64d32 = 2150, - ARM_VREV64d8 = 2151, - ARM_VREV64q16 = 2152, - ARM_VREV64q32 = 2153, - ARM_VREV64q8 = 2154, - ARM_VRHADDsv16i8 = 2155, - ARM_VRHADDsv2i32 = 2156, - ARM_VRHADDsv4i16 = 2157, - ARM_VRHADDsv4i32 = 2158, - ARM_VRHADDsv8i16 = 2159, - ARM_VRHADDsv8i8 = 2160, - ARM_VRHADDuv16i8 = 2161, - ARM_VRHADDuv2i32 = 2162, - ARM_VRHADDuv4i16 = 2163, - ARM_VRHADDuv4i32 = 2164, - ARM_VRHADDuv8i16 = 2165, - ARM_VRHADDuv8i8 = 2166, - ARM_VRINTAD = 2167, - ARM_VRINTAH = 2168, - ARM_VRINTANDf = 2169, - ARM_VRINTANDh = 2170, - ARM_VRINTANQf = 2171, - ARM_VRINTANQh = 2172, - ARM_VRINTAS = 2173, - ARM_VRINTMD = 2174, - ARM_VRINTMH = 2175, - ARM_VRINTMNDf = 2176, - ARM_VRINTMNDh = 2177, - ARM_VRINTMNQf = 2178, - ARM_VRINTMNQh = 2179, - ARM_VRINTMS = 2180, - ARM_VRINTND = 2181, - ARM_VRINTNH = 2182, - ARM_VRINTNNDf = 2183, - ARM_VRINTNNDh = 2184, - ARM_VRINTNNQf = 2185, - ARM_VRINTNNQh = 2186, - ARM_VRINTNS = 2187, - ARM_VRINTPD = 2188, - ARM_VRINTPH = 2189, - ARM_VRINTPNDf = 2190, - ARM_VRINTPNDh = 2191, - ARM_VRINTPNQf = 2192, - ARM_VRINTPNQh = 2193, - ARM_VRINTPS = 2194, - ARM_VRINTRD = 2195, - ARM_VRINTRH = 2196, - ARM_VRINTRS = 2197, - ARM_VRINTXD = 2198, - ARM_VRINTXH = 2199, - ARM_VRINTXNDf = 2200, - ARM_VRINTXNDh = 2201, - ARM_VRINTXNQf = 2202, - ARM_VRINTXNQh = 2203, - ARM_VRINTXS = 2204, - ARM_VRINTZD = 2205, - ARM_VRINTZH = 2206, - ARM_VRINTZNDf = 2207, - ARM_VRINTZNDh = 2208, - ARM_VRINTZNQf = 2209, - ARM_VRINTZNQh = 2210, - ARM_VRINTZS = 2211, - ARM_VRSHLsv16i8 = 2212, - ARM_VRSHLsv1i64 = 2213, - ARM_VRSHLsv2i32 = 2214, - ARM_VRSHLsv2i64 = 2215, - ARM_VRSHLsv4i16 = 2216, - ARM_VRSHLsv4i32 = 2217, - ARM_VRSHLsv8i16 = 2218, - ARM_VRSHLsv8i8 = 2219, - ARM_VRSHLuv16i8 = 2220, - ARM_VRSHLuv1i64 = 2221, - ARM_VRSHLuv2i32 = 2222, - ARM_VRSHLuv2i64 = 2223, - ARM_VRSHLuv4i16 = 2224, - ARM_VRSHLuv4i32 = 2225, - ARM_VRSHLuv8i16 = 2226, - ARM_VRSHLuv8i8 = 2227, - ARM_VRSHRNv2i32 = 2228, - ARM_VRSHRNv4i16 = 2229, - ARM_VRSHRNv8i8 = 2230, - ARM_VRSHRsv16i8 = 2231, - ARM_VRSHRsv1i64 = 2232, - ARM_VRSHRsv2i32 = 2233, - ARM_VRSHRsv2i64 = 2234, - ARM_VRSHRsv4i16 = 2235, - ARM_VRSHRsv4i32 = 2236, - ARM_VRSHRsv8i16 = 2237, - ARM_VRSHRsv8i8 = 2238, - ARM_VRSHRuv16i8 = 2239, - ARM_VRSHRuv1i64 = 2240, - ARM_VRSHRuv2i32 = 2241, - ARM_VRSHRuv2i64 = 2242, - ARM_VRSHRuv4i16 = 2243, - ARM_VRSHRuv4i32 = 2244, - ARM_VRSHRuv8i16 = 2245, - ARM_VRSHRuv8i8 = 2246, - ARM_VRSQRTEd = 2247, - ARM_VRSQRTEfd = 2248, - ARM_VRSQRTEfq = 2249, - ARM_VRSQRTEhd = 2250, - ARM_VRSQRTEhq = 2251, - ARM_VRSQRTEq = 2252, - ARM_VRSQRTSfd = 2253, - ARM_VRSQRTSfq = 2254, - ARM_VRSQRTShd = 2255, - ARM_VRSQRTShq = 2256, - ARM_VRSRAsv16i8 = 2257, - ARM_VRSRAsv1i64 = 2258, - ARM_VRSRAsv2i32 = 2259, - ARM_VRSRAsv2i64 = 2260, - ARM_VRSRAsv4i16 = 2261, - ARM_VRSRAsv4i32 = 2262, - ARM_VRSRAsv8i16 = 2263, - ARM_VRSRAsv8i8 = 2264, - ARM_VRSRAuv16i8 = 2265, - ARM_VRSRAuv1i64 = 2266, - ARM_VRSRAuv2i32 = 2267, - ARM_VRSRAuv2i64 = 2268, - ARM_VRSRAuv4i16 = 2269, - ARM_VRSRAuv4i32 = 2270, - ARM_VRSRAuv8i16 = 2271, - ARM_VRSRAuv8i8 = 2272, - ARM_VRSUBHNv2i32 = 2273, - ARM_VRSUBHNv4i16 = 2274, - ARM_VRSUBHNv8i8 = 2275, - ARM_VSDOTD = 2276, - ARM_VSDOTDI = 2277, - ARM_VSDOTQ = 2278, - ARM_VSDOTQI = 2279, - ARM_VSELEQD = 2280, - ARM_VSELEQH = 2281, - ARM_VSELEQS = 2282, - ARM_VSELGED = 2283, - ARM_VSELGEH = 2284, - ARM_VSELGES = 2285, - ARM_VSELGTD = 2286, - ARM_VSELGTH = 2287, - ARM_VSELGTS = 2288, - ARM_VSELVSD = 2289, - ARM_VSELVSH = 2290, - ARM_VSELVSS = 2291, - ARM_VSETLNi16 = 2292, - ARM_VSETLNi32 = 2293, - ARM_VSETLNi8 = 2294, - ARM_VSHLLi16 = 2295, - ARM_VSHLLi32 = 2296, - ARM_VSHLLi8 = 2297, - ARM_VSHLLsv2i64 = 2298, - ARM_VSHLLsv4i32 = 2299, - ARM_VSHLLsv8i16 = 2300, - ARM_VSHLLuv2i64 = 2301, - ARM_VSHLLuv4i32 = 2302, - ARM_VSHLLuv8i16 = 2303, - ARM_VSHLiv16i8 = 2304, - ARM_VSHLiv1i64 = 2305, - ARM_VSHLiv2i32 = 2306, - ARM_VSHLiv2i64 = 2307, - ARM_VSHLiv4i16 = 2308, - ARM_VSHLiv4i32 = 2309, - ARM_VSHLiv8i16 = 2310, - ARM_VSHLiv8i8 = 2311, - ARM_VSHLsv16i8 = 2312, - ARM_VSHLsv1i64 = 2313, - ARM_VSHLsv2i32 = 2314, - ARM_VSHLsv2i64 = 2315, - ARM_VSHLsv4i16 = 2316, - ARM_VSHLsv4i32 = 2317, - ARM_VSHLsv8i16 = 2318, - ARM_VSHLsv8i8 = 2319, - ARM_VSHLuv16i8 = 2320, - ARM_VSHLuv1i64 = 2321, - ARM_VSHLuv2i32 = 2322, - ARM_VSHLuv2i64 = 2323, - ARM_VSHLuv4i16 = 2324, - ARM_VSHLuv4i32 = 2325, - ARM_VSHLuv8i16 = 2326, - ARM_VSHLuv8i8 = 2327, - ARM_VSHRNv2i32 = 2328, - ARM_VSHRNv4i16 = 2329, - ARM_VSHRNv8i8 = 2330, - ARM_VSHRsv16i8 = 2331, - ARM_VSHRsv1i64 = 2332, - ARM_VSHRsv2i32 = 2333, - ARM_VSHRsv2i64 = 2334, - ARM_VSHRsv4i16 = 2335, - ARM_VSHRsv4i32 = 2336, - ARM_VSHRsv8i16 = 2337, - ARM_VSHRsv8i8 = 2338, - ARM_VSHRuv16i8 = 2339, - ARM_VSHRuv1i64 = 2340, - ARM_VSHRuv2i32 = 2341, - ARM_VSHRuv2i64 = 2342, - ARM_VSHRuv4i16 = 2343, - ARM_VSHRuv4i32 = 2344, - ARM_VSHRuv8i16 = 2345, - ARM_VSHRuv8i8 = 2346, - ARM_VSHTOD = 2347, - ARM_VSHTOH = 2348, - ARM_VSHTOS = 2349, - ARM_VSITOD = 2350, - ARM_VSITOH = 2351, - ARM_VSITOS = 2352, - ARM_VSLIv16i8 = 2353, - ARM_VSLIv1i64 = 2354, - ARM_VSLIv2i32 = 2355, - ARM_VSLIv2i64 = 2356, - ARM_VSLIv4i16 = 2357, - ARM_VSLIv4i32 = 2358, - ARM_VSLIv8i16 = 2359, - ARM_VSLIv8i8 = 2360, - ARM_VSLTOD = 2361, - ARM_VSLTOH = 2362, - ARM_VSLTOS = 2363, - ARM_VSQRTD = 2364, - ARM_VSQRTH = 2365, - ARM_VSQRTS = 2366, - ARM_VSRAsv16i8 = 2367, - ARM_VSRAsv1i64 = 2368, - ARM_VSRAsv2i32 = 2369, - ARM_VSRAsv2i64 = 2370, - ARM_VSRAsv4i16 = 2371, - ARM_VSRAsv4i32 = 2372, - ARM_VSRAsv8i16 = 2373, - ARM_VSRAsv8i8 = 2374, - ARM_VSRAuv16i8 = 2375, - ARM_VSRAuv1i64 = 2376, - ARM_VSRAuv2i32 = 2377, - ARM_VSRAuv2i64 = 2378, - ARM_VSRAuv4i16 = 2379, - ARM_VSRAuv4i32 = 2380, - ARM_VSRAuv8i16 = 2381, - ARM_VSRAuv8i8 = 2382, - ARM_VSRIv16i8 = 2383, - ARM_VSRIv1i64 = 2384, - ARM_VSRIv2i32 = 2385, - ARM_VSRIv2i64 = 2386, - ARM_VSRIv4i16 = 2387, - ARM_VSRIv4i32 = 2388, - ARM_VSRIv8i16 = 2389, - ARM_VSRIv8i8 = 2390, - ARM_VST1LNd16 = 2391, - ARM_VST1LNd16_UPD = 2392, - ARM_VST1LNd32 = 2393, - ARM_VST1LNd32_UPD = 2394, - ARM_VST1LNd8 = 2395, - ARM_VST1LNd8_UPD = 2396, - ARM_VST1d16 = 2403, - ARM_VST1d16Q = 2404, - ARM_VST1d16Qwb_fixed = 2406, - ARM_VST1d16Qwb_register = 2407, - ARM_VST1d16T = 2408, - ARM_VST1d16Twb_fixed = 2410, - ARM_VST1d16Twb_register = 2411, - ARM_VST1d16wb_fixed = 2412, - ARM_VST1d16wb_register = 2413, - ARM_VST1d32 = 2414, - ARM_VST1d32Q = 2415, - ARM_VST1d32Qwb_fixed = 2417, - ARM_VST1d32Qwb_register = 2418, - ARM_VST1d32T = 2419, - ARM_VST1d32Twb_fixed = 2421, - ARM_VST1d32Twb_register = 2422, - ARM_VST1d32wb_fixed = 2423, - ARM_VST1d32wb_register = 2424, - ARM_VST1d64 = 2425, - ARM_VST1d64Q = 2426, - ARM_VST1d64Qwb_fixed = 2430, - ARM_VST1d64Qwb_register = 2431, - ARM_VST1d64T = 2432, - ARM_VST1d64Twb_fixed = 2436, - ARM_VST1d64Twb_register = 2437, - ARM_VST1d64wb_fixed = 2438, - ARM_VST1d64wb_register = 2439, - ARM_VST1d8 = 2440, - ARM_VST1d8Q = 2441, - ARM_VST1d8Qwb_fixed = 2443, - ARM_VST1d8Qwb_register = 2444, - ARM_VST1d8T = 2445, - ARM_VST1d8Twb_fixed = 2447, - ARM_VST1d8Twb_register = 2448, - ARM_VST1d8wb_fixed = 2449, - ARM_VST1d8wb_register = 2450, - ARM_VST1q16 = 2451, - ARM_VST1q16wb_fixed = 2456, - ARM_VST1q16wb_register = 2457, - ARM_VST1q32 = 2458, - ARM_VST1q32wb_fixed = 2463, - ARM_VST1q32wb_register = 2464, - ARM_VST1q64 = 2465, - ARM_VST1q64wb_fixed = 2470, - ARM_VST1q64wb_register = 2471, - ARM_VST1q8 = 2472, - ARM_VST1q8wb_fixed = 2477, - ARM_VST1q8wb_register = 2478, - ARM_VST2LNd16 = 2479, - ARM_VST2LNd16_UPD = 2482, - ARM_VST2LNd32 = 2483, - ARM_VST2LNd32_UPD = 2486, - ARM_VST2LNd8 = 2487, - ARM_VST2LNd8_UPD = 2490, - ARM_VST2LNq16 = 2491, - ARM_VST2LNq16_UPD = 2494, - ARM_VST2LNq32 = 2495, - ARM_VST2LNq32_UPD = 2498, - ARM_VST2b16 = 2499, - ARM_VST2b16wb_fixed = 2500, - ARM_VST2b16wb_register = 2501, - ARM_VST2b32 = 2502, - ARM_VST2b32wb_fixed = 2503, - ARM_VST2b32wb_register = 2504, - ARM_VST2b8 = 2505, - ARM_VST2b8wb_fixed = 2506, - ARM_VST2b8wb_register = 2507, - ARM_VST2d16 = 2508, - ARM_VST2d16wb_fixed = 2509, - ARM_VST2d16wb_register = 2510, - ARM_VST2d32 = 2511, - ARM_VST2d32wb_fixed = 2512, - ARM_VST2d32wb_register = 2513, - ARM_VST2d8 = 2514, - ARM_VST2d8wb_fixed = 2515, - ARM_VST2d8wb_register = 2516, - ARM_VST2q16 = 2517, - ARM_VST2q16wb_fixed = 2521, - ARM_VST2q16wb_register = 2522, - ARM_VST2q32 = 2523, - ARM_VST2q32wb_fixed = 2527, - ARM_VST2q32wb_register = 2528, - ARM_VST2q8 = 2529, - ARM_VST2q8wb_fixed = 2533, - ARM_VST2q8wb_register = 2534, - ARM_VST3LNd16 = 2535, - ARM_VST3LNd16_UPD = 2538, - ARM_VST3LNd32 = 2539, - ARM_VST3LNd32_UPD = 2542, - ARM_VST3LNd8 = 2543, - ARM_VST3LNd8_UPD = 2546, - ARM_VST3LNq16 = 2547, - ARM_VST3LNq16_UPD = 2550, - ARM_VST3LNq32 = 2551, - ARM_VST3LNq32_UPD = 2554, - ARM_VST3d16 = 2555, - ARM_VST3d16_UPD = 2558, - ARM_VST3d32 = 2559, - ARM_VST3d32_UPD = 2562, - ARM_VST3d8 = 2563, - ARM_VST3d8_UPD = 2566, - ARM_VST3q16 = 2567, - ARM_VST3q16_UPD = 2569, - ARM_VST3q32 = 2572, - ARM_VST3q32_UPD = 2574, - ARM_VST3q8 = 2577, - ARM_VST3q8_UPD = 2579, - ARM_VST4LNd16 = 2582, - ARM_VST4LNd16_UPD = 2585, - ARM_VST4LNd32 = 2586, - ARM_VST4LNd32_UPD = 2589, - ARM_VST4LNd8 = 2590, - ARM_VST4LNd8_UPD = 2593, - ARM_VST4LNq16 = 2594, - ARM_VST4LNq16_UPD = 2597, - ARM_VST4LNq32 = 2598, - ARM_VST4LNq32_UPD = 2601, - ARM_VST4d16 = 2602, - ARM_VST4d16_UPD = 2605, - ARM_VST4d32 = 2606, - ARM_VST4d32_UPD = 2609, - ARM_VST4d8 = 2610, - ARM_VST4d8_UPD = 2613, - ARM_VST4q16 = 2614, - ARM_VST4q16_UPD = 2616, - ARM_VST4q32 = 2619, - ARM_VST4q32_UPD = 2621, - ARM_VST4q8 = 2624, - ARM_VST4q8_UPD = 2626, - ARM_VSTMDDB_UPD = 2629, - ARM_VSTMDIA = 2630, - ARM_VSTMDIA_UPD = 2631, - ARM_VSTMQIA = 2632, - ARM_VSTMSDB_UPD = 2633, - ARM_VSTMSIA = 2634, - ARM_VSTMSIA_UPD = 2635, - ARM_VSTRD = 2636, - ARM_VSTRH = 2637, - ARM_VSTRS = 2638, - ARM_VSUBD = 2639, - ARM_VSUBH = 2640, - ARM_VSUBHNv2i32 = 2641, - ARM_VSUBHNv4i16 = 2642, - ARM_VSUBHNv8i8 = 2643, - ARM_VSUBLsv2i64 = 2644, - ARM_VSUBLsv4i32 = 2645, - ARM_VSUBLsv8i16 = 2646, - ARM_VSUBLuv2i64 = 2647, - ARM_VSUBLuv4i32 = 2648, - ARM_VSUBLuv8i16 = 2649, - ARM_VSUBS = 2650, - ARM_VSUBWsv2i64 = 2651, - ARM_VSUBWsv4i32 = 2652, - ARM_VSUBWsv8i16 = 2653, - ARM_VSUBWuv2i64 = 2654, - ARM_VSUBWuv4i32 = 2655, - ARM_VSUBWuv8i16 = 2656, - ARM_VSUBfd = 2657, - ARM_VSUBfq = 2658, - ARM_VSUBhd = 2659, - ARM_VSUBhq = 2660, - ARM_VSUBv16i8 = 2661, - ARM_VSUBv1i64 = 2662, - ARM_VSUBv2i32 = 2663, - ARM_VSUBv2i64 = 2664, - ARM_VSUBv4i16 = 2665, - ARM_VSUBv4i32 = 2666, - ARM_VSUBv8i16 = 2667, - ARM_VSUBv8i8 = 2668, - ARM_VSWPd = 2669, - ARM_VSWPq = 2670, - ARM_VTBL1 = 2671, - ARM_VTBL2 = 2672, - ARM_VTBL3 = 2673, - ARM_VTBL4 = 2675, - ARM_VTBX1 = 2677, - ARM_VTBX2 = 2678, - ARM_VTBX3 = 2679, - ARM_VTBX4 = 2681, - ARM_VTOSHD = 2683, - ARM_VTOSHH = 2684, - ARM_VTOSHS = 2685, - ARM_VTOSIRD = 2686, - ARM_VTOSIRH = 2687, - ARM_VTOSIRS = 2688, - ARM_VTOSIZD = 2689, - ARM_VTOSIZH = 2690, - ARM_VTOSIZS = 2691, - ARM_VTOSLD = 2692, - ARM_VTOSLH = 2693, - ARM_VTOSLS = 2694, - ARM_VTOUHD = 2695, - ARM_VTOUHH = 2696, - ARM_VTOUHS = 2697, - ARM_VTOUIRD = 2698, - ARM_VTOUIRH = 2699, - ARM_VTOUIRS = 2700, - ARM_VTOUIZD = 2701, - ARM_VTOUIZH = 2702, - ARM_VTOUIZS = 2703, - ARM_VTOULD = 2704, - ARM_VTOULH = 2705, - ARM_VTOULS = 2706, - ARM_VTRNd16 = 2707, - ARM_VTRNd32 = 2708, - ARM_VTRNd8 = 2709, - ARM_VTRNq16 = 2710, - ARM_VTRNq32 = 2711, - ARM_VTRNq8 = 2712, - ARM_VTSTv16i8 = 2713, - ARM_VTSTv2i32 = 2714, - ARM_VTSTv4i16 = 2715, - ARM_VTSTv4i32 = 2716, - ARM_VTSTv8i16 = 2717, - ARM_VTSTv8i8 = 2718, - ARM_VUDOTD = 2719, - ARM_VUDOTDI = 2720, - ARM_VUDOTQ = 2721, - ARM_VUDOTQI = 2722, - ARM_VUHTOD = 2723, - ARM_VUHTOH = 2724, - ARM_VUHTOS = 2725, - ARM_VUITOD = 2726, - ARM_VUITOH = 2727, - ARM_VUITOS = 2728, - ARM_VULTOD = 2729, - ARM_VULTOH = 2730, - ARM_VULTOS = 2731, - ARM_VUZPd16 = 2732, - ARM_VUZPd8 = 2733, - ARM_VUZPq16 = 2734, - ARM_VUZPq32 = 2735, - ARM_VUZPq8 = 2736, - ARM_VZIPd16 = 2737, - ARM_VZIPd8 = 2738, - ARM_VZIPq16 = 2739, - ARM_VZIPq32 = 2740, - ARM_VZIPq8 = 2741, - ARM_sysLDMDA = 2742, - ARM_sysLDMDA_UPD = 2743, - ARM_sysLDMDB = 2744, - ARM_sysLDMDB_UPD = 2745, - ARM_sysLDMIA = 2746, - ARM_sysLDMIA_UPD = 2747, - ARM_sysLDMIB = 2748, - ARM_sysLDMIB_UPD = 2749, - ARM_sysSTMDA = 2750, - ARM_sysSTMDA_UPD = 2751, - ARM_sysSTMDB = 2752, - ARM_sysSTMDB_UPD = 2753, - ARM_sysSTMIA = 2754, - ARM_sysSTMIA_UPD = 2755, - ARM_sysSTMIB = 2756, - ARM_sysSTMIB_UPD = 2757, - ARM_t2ADCri = 2758, - ARM_t2ADCrr = 2759, - ARM_t2ADCrs = 2760, - ARM_t2ADDri = 2761, - ARM_t2ADDri12 = 2762, - ARM_t2ADDrr = 2763, - ARM_t2ADDrs = 2764, - ARM_t2ADR = 2765, - ARM_t2ANDri = 2766, - ARM_t2ANDrr = 2767, - ARM_t2ANDrs = 2768, - ARM_t2ASRri = 2769, - ARM_t2ASRrr = 2770, - ARM_t2B = 2771, - ARM_t2BFC = 2772, - ARM_t2BFI = 2773, - ARM_t2BICri = 2774, - ARM_t2BICrr = 2775, - ARM_t2BICrs = 2776, - ARM_t2BXJ = 2777, - ARM_t2Bcc = 2778, - ARM_t2CDP = 2779, - ARM_t2CDP2 = 2780, - ARM_t2CLREX = 2781, - ARM_t2CLZ = 2782, - ARM_t2CMNri = 2783, - ARM_t2CMNzrr = 2784, - ARM_t2CMNzrs = 2785, - ARM_t2CMPri = 2786, - ARM_t2CMPrr = 2787, - ARM_t2CMPrs = 2788, - ARM_t2CPS1p = 2789, - ARM_t2CPS2p = 2790, - ARM_t2CPS3p = 2791, - ARM_t2CRC32B = 2792, - ARM_t2CRC32CB = 2793, - ARM_t2CRC32CH = 2794, - ARM_t2CRC32CW = 2795, - ARM_t2CRC32H = 2796, - ARM_t2CRC32W = 2797, - ARM_t2DBG = 2798, - ARM_t2DCPS1 = 2799, - ARM_t2DCPS2 = 2800, - ARM_t2DCPS3 = 2801, - ARM_t2DMB = 2802, - ARM_t2DSB = 2803, - ARM_t2EORri = 2804, - ARM_t2EORrr = 2805, - ARM_t2EORrs = 2806, - ARM_t2HINT = 2807, - ARM_t2HVC = 2808, - ARM_t2ISB = 2809, - ARM_t2IT = 2810, - ARM_t2LDA = 2813, - ARM_t2LDAB = 2814, - ARM_t2LDAEX = 2815, - ARM_t2LDAEXB = 2816, - ARM_t2LDAEXD = 2817, - ARM_t2LDAEXH = 2818, - ARM_t2LDAH = 2819, - ARM_t2LDC2L_OFFSET = 2820, - ARM_t2LDC2L_OPTION = 2821, - ARM_t2LDC2L_POST = 2822, - ARM_t2LDC2L_PRE = 2823, - ARM_t2LDC2_OFFSET = 2824, - ARM_t2LDC2_OPTION = 2825, - ARM_t2LDC2_POST = 2826, - ARM_t2LDC2_PRE = 2827, - ARM_t2LDCL_OFFSET = 2828, - ARM_t2LDCL_OPTION = 2829, - ARM_t2LDCL_POST = 2830, - ARM_t2LDCL_PRE = 2831, - ARM_t2LDC_OFFSET = 2832, - ARM_t2LDC_OPTION = 2833, - ARM_t2LDC_POST = 2834, - ARM_t2LDC_PRE = 2835, - ARM_t2LDMDB = 2836, - ARM_t2LDMDB_UPD = 2837, - ARM_t2LDMIA = 2838, - ARM_t2LDMIA_UPD = 2839, - ARM_t2LDRBT = 2840, - ARM_t2LDRB_POST = 2841, - ARM_t2LDRB_PRE = 2842, - ARM_t2LDRBi12 = 2843, - ARM_t2LDRBi8 = 2844, - ARM_t2LDRBpci = 2845, - ARM_t2LDRBs = 2846, - ARM_t2LDRD_POST = 2847, - ARM_t2LDRD_PRE = 2848, - ARM_t2LDRDi8 = 2849, - ARM_t2LDREX = 2850, - ARM_t2LDREXB = 2851, - ARM_t2LDREXD = 2852, - ARM_t2LDREXH = 2853, - ARM_t2LDRHT = 2854, - ARM_t2LDRH_POST = 2855, - ARM_t2LDRH_PRE = 2856, - ARM_t2LDRHi12 = 2857, - ARM_t2LDRHi8 = 2858, - ARM_t2LDRHpci = 2859, - ARM_t2LDRHs = 2860, - ARM_t2LDRSBT = 2861, - ARM_t2LDRSB_POST = 2862, - ARM_t2LDRSB_PRE = 2863, - ARM_t2LDRSBi12 = 2864, - ARM_t2LDRSBi8 = 2865, - ARM_t2LDRSBpci = 2866, - ARM_t2LDRSBs = 2867, - ARM_t2LDRSHT = 2868, - ARM_t2LDRSH_POST = 2869, - ARM_t2LDRSH_PRE = 2870, - ARM_t2LDRSHi12 = 2871, - ARM_t2LDRSHi8 = 2872, - ARM_t2LDRSHpci = 2873, - ARM_t2LDRSHs = 2874, - ARM_t2LDRT = 2875, - ARM_t2LDR_POST = 2876, - ARM_t2LDR_PRE = 2877, - ARM_t2LDRi12 = 2878, - ARM_t2LDRi8 = 2879, - ARM_t2LDRpci = 2880, - ARM_t2LDRs = 2881, - ARM_t2LSLri = 2882, - ARM_t2LSLrr = 2883, - ARM_t2LSRri = 2884, - ARM_t2LSRrr = 2885, - ARM_t2MCR = 2886, - ARM_t2MCR2 = 2887, - ARM_t2MCRR = 2888, - ARM_t2MCRR2 = 2889, - ARM_t2MLA = 2890, - ARM_t2MLS = 2891, - ARM_t2MOVTi16 = 2892, - ARM_t2MOVi = 2893, - ARM_t2MOVi16 = 2894, - ARM_t2MOVr = 2895, - ARM_t2MOVsra_flag = 2896, - ARM_t2MOVsrl_flag = 2897, - ARM_t2MRC = 2898, - ARM_t2MRC2 = 2899, - ARM_t2MRRC = 2900, - ARM_t2MRRC2 = 2901, - ARM_t2MRS_AR = 2902, - ARM_t2MRS_M = 2903, - ARM_t2MRSbanked = 2904, - ARM_t2MRSsys_AR = 2905, - ARM_t2MSR_AR = 2906, - ARM_t2MSR_M = 2907, - ARM_t2MSRbanked = 2908, - ARM_t2MUL = 2909, - ARM_t2MVNi = 2910, - ARM_t2MVNr = 2911, - ARM_t2MVNs = 2912, - ARM_t2ORNri = 2913, - ARM_t2ORNrr = 2914, - ARM_t2ORNrs = 2915, - ARM_t2ORRri = 2916, - ARM_t2ORRrr = 2917, - ARM_t2ORRrs = 2918, - ARM_t2PKHBT = 2919, - ARM_t2PKHTB = 2920, - ARM_t2PLDWi12 = 2921, - ARM_t2PLDWi8 = 2922, - ARM_t2PLDWs = 2923, - ARM_t2PLDi12 = 2924, - ARM_t2PLDi8 = 2925, - ARM_t2PLDpci = 2926, - ARM_t2PLDs = 2927, - ARM_t2PLIi12 = 2928, - ARM_t2PLIi8 = 2929, - ARM_t2PLIpci = 2930, - ARM_t2PLIs = 2931, - ARM_t2QADD = 2932, - ARM_t2QADD16 = 2933, - ARM_t2QADD8 = 2934, - ARM_t2QASX = 2935, - ARM_t2QDADD = 2936, - ARM_t2QDSUB = 2937, - ARM_t2QSAX = 2938, - ARM_t2QSUB = 2939, - ARM_t2QSUB16 = 2940, - ARM_t2QSUB8 = 2941, - ARM_t2RBIT = 2942, - ARM_t2REV = 2943, - ARM_t2REV16 = 2944, - ARM_t2REVSH = 2945, - ARM_t2RFEDB = 2946, - ARM_t2RFEDBW = 2947, - ARM_t2RFEIA = 2948, - ARM_t2RFEIAW = 2949, - ARM_t2RORri = 2950, - ARM_t2RORrr = 2951, - ARM_t2RRX = 2952, - ARM_t2RSBri = 2953, - ARM_t2RSBrr = 2954, - ARM_t2RSBrs = 2955, - ARM_t2SADD16 = 2956, - ARM_t2SADD8 = 2957, - ARM_t2SASX = 2958, - ARM_t2SBCri = 2959, - ARM_t2SBCrr = 2960, - ARM_t2SBCrs = 2961, - ARM_t2SBFX = 2962, - ARM_t2SDIV = 2963, - ARM_t2SEL = 2964, - ARM_t2SETPAN = 2965, - ARM_t2SG = 2966, - ARM_t2SHADD16 = 2967, - ARM_t2SHADD8 = 2968, - ARM_t2SHASX = 2969, - ARM_t2SHSAX = 2970, - ARM_t2SHSUB16 = 2971, - ARM_t2SHSUB8 = 2972, - ARM_t2SMC = 2973, - ARM_t2SMLABB = 2974, - ARM_t2SMLABT = 2975, - ARM_t2SMLAD = 2976, - ARM_t2SMLADX = 2977, - ARM_t2SMLAL = 2978, - ARM_t2SMLALBB = 2979, - ARM_t2SMLALBT = 2980, - ARM_t2SMLALD = 2981, - ARM_t2SMLALDX = 2982, - ARM_t2SMLALTB = 2983, - ARM_t2SMLALTT = 2984, - ARM_t2SMLATB = 2985, - ARM_t2SMLATT = 2986, - ARM_t2SMLAWB = 2987, - ARM_t2SMLAWT = 2988, - ARM_t2SMLSD = 2989, - ARM_t2SMLSDX = 2990, - ARM_t2SMLSLD = 2991, - ARM_t2SMLSLDX = 2992, - ARM_t2SMMLA = 2993, - ARM_t2SMMLAR = 2994, - ARM_t2SMMLS = 2995, - ARM_t2SMMLSR = 2996, - ARM_t2SMMUL = 2997, - ARM_t2SMMULR = 2998, - ARM_t2SMUAD = 2999, - ARM_t2SMUADX = 3000, - ARM_t2SMULBB = 3001, - ARM_t2SMULBT = 3002, - ARM_t2SMULL = 3003, - ARM_t2SMULTB = 3004, - ARM_t2SMULTT = 3005, - ARM_t2SMULWB = 3006, - ARM_t2SMULWT = 3007, - ARM_t2SMUSD = 3008, - ARM_t2SMUSDX = 3009, - ARM_t2SRSDB = 3010, - ARM_t2SRSDB_UPD = 3011, - ARM_t2SRSIA = 3012, - ARM_t2SRSIA_UPD = 3013, - ARM_t2SSAT = 3014, - ARM_t2SSAT16 = 3015, - ARM_t2SSAX = 3016, - ARM_t2SSUB16 = 3017, - ARM_t2SSUB8 = 3018, - ARM_t2STC2L_OFFSET = 3019, - ARM_t2STC2L_OPTION = 3020, - ARM_t2STC2L_POST = 3021, - ARM_t2STC2L_PRE = 3022, - ARM_t2STC2_OFFSET = 3023, - ARM_t2STC2_OPTION = 3024, - ARM_t2STC2_POST = 3025, - ARM_t2STC2_PRE = 3026, - ARM_t2STCL_OFFSET = 3027, - ARM_t2STCL_OPTION = 3028, - ARM_t2STCL_POST = 3029, - ARM_t2STCL_PRE = 3030, - ARM_t2STC_OFFSET = 3031, - ARM_t2STC_OPTION = 3032, - ARM_t2STC_POST = 3033, - ARM_t2STC_PRE = 3034, - ARM_t2STL = 3035, - ARM_t2STLB = 3036, - ARM_t2STLEX = 3037, - ARM_t2STLEXB = 3038, - ARM_t2STLEXD = 3039, - ARM_t2STLEXH = 3040, - ARM_t2STLH = 3041, - ARM_t2STMDB = 3042, - ARM_t2STMDB_UPD = 3043, - ARM_t2STMIA = 3044, - ARM_t2STMIA_UPD = 3045, - ARM_t2STRBT = 3046, - ARM_t2STRB_POST = 3047, - ARM_t2STRB_PRE = 3048, - ARM_t2STRBi12 = 3049, - ARM_t2STRBi8 = 3050, - ARM_t2STRBs = 3051, - ARM_t2STRD_POST = 3052, - ARM_t2STRD_PRE = 3053, - ARM_t2STRDi8 = 3054, - ARM_t2STREX = 3055, - ARM_t2STREXB = 3056, - ARM_t2STREXD = 3057, - ARM_t2STREXH = 3058, - ARM_t2STRHT = 3059, - ARM_t2STRH_POST = 3060, - ARM_t2STRH_PRE = 3061, - ARM_t2STRHi12 = 3062, - ARM_t2STRHi8 = 3063, - ARM_t2STRHs = 3064, - ARM_t2STRT = 3065, - ARM_t2STR_POST = 3066, - ARM_t2STR_PRE = 3067, - ARM_t2STRi12 = 3068, - ARM_t2STRi8 = 3069, - ARM_t2STRs = 3070, - ARM_t2SUBS_PC_LR = 3071, - ARM_t2SUBri = 3072, - ARM_t2SUBri12 = 3073, - ARM_t2SUBrr = 3074, - ARM_t2SUBrs = 3075, - ARM_t2SXTAB = 3076, - ARM_t2SXTAB16 = 3077, - ARM_t2SXTAH = 3078, - ARM_t2SXTB = 3079, - ARM_t2SXTB16 = 3080, - ARM_t2SXTH = 3081, - ARM_t2TBB = 3082, - ARM_t2TBH = 3083, - ARM_t2TEQri = 3084, - ARM_t2TEQrr = 3085, - ARM_t2TEQrs = 3086, - ARM_t2TSB = 3087, - ARM_t2TSTri = 3088, - ARM_t2TSTrr = 3089, - ARM_t2TSTrs = 3090, - ARM_t2TT = 3091, - ARM_t2TTA = 3092, - ARM_t2TTAT = 3093, - ARM_t2TTT = 3094, - ARM_t2UADD16 = 3095, - ARM_t2UADD8 = 3096, - ARM_t2UASX = 3097, - ARM_t2UBFX = 3098, - ARM_t2UDF = 3099, - ARM_t2UDIV = 3100, - ARM_t2UHADD16 = 3101, - ARM_t2UHADD8 = 3102, - ARM_t2UHASX = 3103, - ARM_t2UHSAX = 3104, - ARM_t2UHSUB16 = 3105, - ARM_t2UHSUB8 = 3106, - ARM_t2UMAAL = 3107, - ARM_t2UMLAL = 3108, - ARM_t2UMULL = 3109, - ARM_t2UQADD16 = 3110, - ARM_t2UQADD8 = 3111, - ARM_t2UQASX = 3112, - ARM_t2UQSAX = 3113, - ARM_t2UQSUB16 = 3114, - ARM_t2UQSUB8 = 3115, - ARM_t2USAD8 = 3116, - ARM_t2USADA8 = 3117, - ARM_t2USAT = 3118, - ARM_t2USAT16 = 3119, - ARM_t2USAX = 3120, - ARM_t2USUB16 = 3121, - ARM_t2USUB8 = 3122, - ARM_t2UXTAB = 3123, - ARM_t2UXTAB16 = 3124, - ARM_t2UXTAH = 3125, - ARM_t2UXTB = 3126, - ARM_t2UXTB16 = 3127, - ARM_t2UXTH = 3128, - ARM_tADC = 3129, - ARM_tADDhirr = 3130, - ARM_tADDi3 = 3131, - ARM_tADDi8 = 3132, - ARM_tADDrSP = 3133, - ARM_tADDrSPi = 3134, - ARM_tADDrr = 3135, - ARM_tADDspi = 3136, - ARM_tADDspr = 3137, - ARM_tADR = 3138, - ARM_tAND = 3139, - ARM_tASRri = 3140, - ARM_tASRrr = 3141, - ARM_tB = 3142, - ARM_tBIC = 3143, - ARM_tBKPT = 3144, - ARM_tBL = 3145, - ARM_tBLXNSr = 3146, - ARM_tBLXi = 3147, - ARM_tBLXr = 3148, - ARM_tBX = 3149, - ARM_tBXNS = 3150, - ARM_tBcc = 3151, - ARM_tCBNZ = 3152, - ARM_tCBZ = 3153, - ARM_tCMNz = 3154, - ARM_tCMPhir = 3155, - ARM_tCMPi8 = 3156, - ARM_tCMPr = 3157, - ARM_tCPS = 3158, - ARM_tEOR = 3159, - ARM_tHINT = 3160, - ARM_tHLT = 3161, - ARM_tLDMIA = 3165, - ARM_tLDRBi = 3166, - ARM_tLDRBr = 3167, - ARM_tLDRHi = 3168, - ARM_tLDRHr = 3169, - ARM_tLDRSB = 3170, - ARM_tLDRSH = 3171, - ARM_tLDRi = 3172, - ARM_tLDRpci = 3173, - ARM_tLDRr = 3174, - ARM_tLDRspi = 3175, - ARM_tLSLri = 3176, - ARM_tLSLrr = 3177, - ARM_tLSRri = 3178, - ARM_tLSRrr = 3179, - ARM_tMOVSr = 3180, - ARM_tMOVi8 = 3181, - ARM_tMOVr = 3182, - ARM_tMUL = 3183, - ARM_tMVN = 3184, - ARM_tORR = 3185, - ARM_tPICADD = 3186, - ARM_tPOP = 3187, - ARM_tPUSH = 3188, - ARM_tREV = 3189, - ARM_tREV16 = 3190, - ARM_tREVSH = 3191, - ARM_tROR = 3192, - ARM_tRSB = 3193, - ARM_tSBC = 3194, - ARM_tSETEND = 3195, - ARM_tSTMIA_UPD = 3196, - ARM_tSTRBi = 3197, - ARM_tSTRBr = 3198, - ARM_tSTRHi = 3199, - ARM_tSTRHr = 3200, - ARM_tSTRi = 3201, - ARM_tSTRr = 3202, - ARM_tSTRspi = 3203, - ARM_tSUBi3 = 3204, - ARM_tSUBi8 = 3205, - ARM_tSUBrr = 3206, - ARM_tSUBspi = 3207, - ARM_tSVC = 3208, - ARM_tSXTB = 3209, - ARM_tSXTH = 3210, - ARM_tTRAP = 3211, - ARM_tTST = 3212, - ARM_tUDF = 3213, - ARM_tUXTB = 3214, - ARM_tUXTH = 3215, - ARM_t__brkdiv0 = 3216, - ARM_INSTRUCTION_LIST_END = 3217 + ARM_PHI = 0, + ARM_INLINEASM = 1, + ARM_CFI_INSTRUCTION = 2, + ARM_EH_LABEL = 3, + ARM_GC_LABEL = 4, + ARM_ANNOTATION_LABEL = 5, + ARM_KILL = 6, + ARM_EXTRACT_SUBREG = 7, + ARM_INSERT_SUBREG = 8, + ARM_IMPLICIT_DEF = 9, + ARM_SUBREG_TO_REG = 10, + ARM_COPY_TO_REGCLASS = 11, + ARM_DBG_VALUE = 12, + ARM_DBG_LABEL = 13, + ARM_REG_SEQUENCE = 14, + ARM_COPY = 15, + ARM_BUNDLE = 16, + ARM_LIFETIME_START = 17, + ARM_LIFETIME_END = 18, + ARM_STACKMAP = 19, + ARM_FENTRY_CALL = 20, + ARM_PATCHPOINT = 21, + ARM_LOAD_STACK_GUARD = 22, + ARM_STATEPOINT = 23, + ARM_LOCAL_ESCAPE = 24, + ARM_FAULTING_OP = 25, + ARM_PATCHABLE_OP = 26, + ARM_PATCHABLE_FUNCTION_ENTER = 27, + ARM_PATCHABLE_RET = 28, + ARM_PATCHABLE_FUNCTION_EXIT = 29, + ARM_PATCHABLE_TAIL_CALL = 30, + ARM_PATCHABLE_EVENT_CALL = 31, + ARM_PATCHABLE_TYPED_EVENT_CALL = 32, + ARM_ICALL_BRANCH_FUNNEL = 33, + ARM_G_ADD = 34, + ARM_G_SUB = 35, + ARM_G_MUL = 36, + ARM_G_SDIV = 37, + ARM_G_UDIV = 38, + ARM_G_SREM = 39, + ARM_G_UREM = 40, + ARM_G_AND = 41, + ARM_G_OR = 42, + ARM_G_XOR = 43, + ARM_G_IMPLICIT_DEF = 44, + ARM_G_PHI = 45, + ARM_G_FRAME_INDEX = 46, + ARM_G_GLOBAL_VALUE = 47, + ARM_G_EXTRACT = 48, + ARM_G_UNMERGE_VALUES = 49, + ARM_G_INSERT = 50, + ARM_G_MERGE_VALUES = 51, + ARM_G_PTRTOINT = 52, + ARM_G_INTTOPTR = 53, + ARM_G_BITCAST = 54, + ARM_G_LOAD = 55, + ARM_G_SEXTLOAD = 56, + ARM_G_ZEXTLOAD = 57, + ARM_G_STORE = 58, + ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, + ARM_G_ATOMIC_CMPXCHG = 60, + ARM_G_ATOMICRMW_XCHG = 61, + ARM_G_ATOMICRMW_ADD = 62, + ARM_G_ATOMICRMW_SUB = 63, + ARM_G_ATOMICRMW_AND = 64, + ARM_G_ATOMICRMW_NAND = 65, + ARM_G_ATOMICRMW_OR = 66, + ARM_G_ATOMICRMW_XOR = 67, + ARM_G_ATOMICRMW_MAX = 68, + ARM_G_ATOMICRMW_MIN = 69, + ARM_G_ATOMICRMW_UMAX = 70, + ARM_G_ATOMICRMW_UMIN = 71, + ARM_G_BRCOND = 72, + ARM_G_BRINDIRECT = 73, + ARM_G_INTRINSIC = 74, + ARM_G_INTRINSIC_W_SIDE_EFFECTS = 75, + ARM_G_ANYEXT = 76, + ARM_G_TRUNC = 77, + ARM_G_CONSTANT = 78, + ARM_G_FCONSTANT = 79, + ARM_G_VASTART = 80, + ARM_G_VAARG = 81, + ARM_G_SEXT = 82, + ARM_G_ZEXT = 83, + ARM_G_SHL = 84, + ARM_G_LSHR = 85, + ARM_G_ASHR = 86, + ARM_G_ICMP = 87, + ARM_G_FCMP = 88, + ARM_G_SELECT = 89, + ARM_G_UADDE = 90, + ARM_G_USUBE = 91, + ARM_G_SADDO = 92, + ARM_G_SSUBO = 93, + ARM_G_UMULO = 94, + ARM_G_SMULO = 95, + ARM_G_UMULH = 96, + ARM_G_SMULH = 97, + ARM_G_FADD = 98, + ARM_G_FSUB = 99, + ARM_G_FMUL = 100, + ARM_G_FMA = 101, + ARM_G_FDIV = 102, + ARM_G_FREM = 103, + ARM_G_FPOW = 104, + ARM_G_FEXP = 105, + ARM_G_FEXP2 = 106, + ARM_G_FLOG = 107, + ARM_G_FLOG2 = 108, + ARM_G_FNEG = 109, + ARM_G_FPEXT = 110, + ARM_G_FPTRUNC = 111, + ARM_G_FPTOSI = 112, + ARM_G_FPTOUI = 113, + ARM_G_SITOFP = 114, + ARM_G_UITOFP = 115, + ARM_G_FABS = 116, + ARM_G_GEP = 117, + ARM_G_PTR_MASK = 118, + ARM_G_BR = 119, + ARM_G_INSERT_VECTOR_ELT = 120, + ARM_G_EXTRACT_VECTOR_ELT = 121, + ARM_G_SHUFFLE_VECTOR = 122, + ARM_G_BSWAP = 123, + ARM_G_ADDRSPACE_CAST = 124, + ARM_G_BLOCK_ADDR = 125, + ARM_ABS = 126, + ARM_ADDSri = 127, + ARM_ADDSrr = 128, + ARM_ADDSrsi = 129, + ARM_ADDSrsr = 130, + ARM_ADJCALLSTACKDOWN = 131, + ARM_ADJCALLSTACKUP = 132, + ARM_ASRi = 133, + ARM_ASRr = 134, + ARM_B = 135, + ARM_BCCZi64 = 136, + ARM_BCCi64 = 137, + ARM_BMOVPCB_CALL = 138, + ARM_BMOVPCRX_CALL = 139, + ARM_BR_JTadd = 140, + ARM_BR_JTm_i12 = 141, + ARM_BR_JTm_rs = 142, + ARM_BR_JTr = 143, + ARM_BX_CALL = 144, + ARM_CMP_SWAP_16 = 145, + ARM_CMP_SWAP_32 = 146, + ARM_CMP_SWAP_64 = 147, + ARM_CMP_SWAP_8 = 148, + ARM_CONSTPOOL_ENTRY = 149, + ARM_COPY_STRUCT_BYVAL_I32 = 150, + ARM_CompilerBarrier = 151, + ARM_ITasm = 152, + ARM_Int_eh_sjlj_dispatchsetup = 153, + ARM_Int_eh_sjlj_setup_dispatch = 157, + ARM_JUMPTABLE_ADDRS = 158, + ARM_JUMPTABLE_INSTS = 159, + ARM_JUMPTABLE_TBB = 160, + ARM_JUMPTABLE_TBH = 161, + ARM_LDMIA_RET = 162, + ARM_LDRBT_POST = 163, + ARM_LDRConstPool = 164, + ARM_LDRLIT_ga_abs = 165, + ARM_LDRLIT_ga_pcrel = 166, + ARM_LDRLIT_ga_pcrel_ldr = 167, + ARM_LDRT_POST = 168, + ARM_LEApcrel = 169, + ARM_LEApcrelJT = 170, + ARM_LSLi = 171, + ARM_LSLr = 172, + ARM_LSRi = 173, + ARM_LSRr = 174, + ARM_MEMCPY = 175, + ARM_MLAv5 = 176, + ARM_MOVCCi = 177, + ARM_MOVCCi16 = 178, + ARM_MOVCCi32imm = 179, + ARM_MOVCCr = 180, + ARM_MOVCCsi = 181, + ARM_MOVCCsr = 182, + ARM_MOVPCRX = 183, + ARM_MOVTi16_ga_pcrel = 184, + ARM_MOV_ga_pcrel = 185, + ARM_MOV_ga_pcrel_ldr = 186, + ARM_MOVi16_ga_pcrel = 187, + ARM_MOVi32imm = 188, + ARM_MOVsra_flag = 189, + ARM_MOVsrl_flag = 190, + ARM_MULv5 = 191, + ARM_MVNCCi = 192, + ARM_PICADD = 193, + ARM_PICLDR = 194, + ARM_PICLDRB = 195, + ARM_PICLDRH = 196, + ARM_PICLDRSB = 197, + ARM_PICLDRSH = 198, + ARM_PICSTR = 199, + ARM_PICSTRB = 200, + ARM_PICSTRH = 201, + ARM_RORi = 202, + ARM_RORr = 203, + ARM_RRX = 204, + ARM_RRXi = 205, + ARM_RSBSri = 206, + ARM_RSBSrsi = 207, + ARM_RSBSrsr = 208, + ARM_SMLALv5 = 209, + ARM_SMULLv5 = 210, + ARM_SPACE = 211, + ARM_STRBT_POST = 212, + ARM_STRBi_preidx = 213, + ARM_STRBr_preidx = 214, + ARM_STRH_preidx = 215, + ARM_STRT_POST = 216, + ARM_STRi_preidx = 217, + ARM_STRr_preidx = 218, + ARM_SUBS_PC_LR = 219, + ARM_SUBSri = 220, + ARM_SUBSrr = 221, + ARM_SUBSrsi = 222, + ARM_SUBSrsr = 223, + ARM_TAILJMPd = 224, + ARM_TAILJMPr = 225, + ARM_TAILJMPr4 = 226, + ARM_TCRETURNdi = 227, + ARM_TCRETURNri = 228, + ARM_TPsoft = 229, + ARM_UMLALv5 = 230, + ARM_UMULLv5 = 231, + ARM_VLD1LNdAsm_16 = 232, + ARM_VLD1LNdAsm_32 = 233, + ARM_VLD1LNdAsm_8 = 234, + ARM_VLD1LNdWB_fixed_Asm_16 = 235, + ARM_VLD1LNdWB_fixed_Asm_32 = 236, + ARM_VLD1LNdWB_fixed_Asm_8 = 237, + ARM_VLD1LNdWB_register_Asm_16 = 238, + ARM_VLD1LNdWB_register_Asm_32 = 239, + ARM_VLD1LNdWB_register_Asm_8 = 240, + ARM_VLD2LNdAsm_16 = 241, + ARM_VLD2LNdAsm_32 = 242, + ARM_VLD2LNdAsm_8 = 243, + ARM_VLD2LNdWB_fixed_Asm_16 = 244, + ARM_VLD2LNdWB_fixed_Asm_32 = 245, + ARM_VLD2LNdWB_fixed_Asm_8 = 246, + ARM_VLD2LNdWB_register_Asm_16 = 247, + ARM_VLD2LNdWB_register_Asm_32 = 248, + ARM_VLD2LNdWB_register_Asm_8 = 249, + ARM_VLD2LNqAsm_16 = 250, + ARM_VLD2LNqAsm_32 = 251, + ARM_VLD2LNqWB_fixed_Asm_16 = 252, + ARM_VLD2LNqWB_fixed_Asm_32 = 253, + ARM_VLD2LNqWB_register_Asm_16 = 254, + ARM_VLD2LNqWB_register_Asm_32 = 255, + ARM_VLD3DUPdAsm_16 = 256, + ARM_VLD3DUPdAsm_32 = 257, + ARM_VLD3DUPdAsm_8 = 258, + ARM_VLD3DUPdWB_fixed_Asm_16 = 259, + ARM_VLD3DUPdWB_fixed_Asm_32 = 260, + ARM_VLD3DUPdWB_fixed_Asm_8 = 261, + ARM_VLD3DUPdWB_register_Asm_16 = 262, + ARM_VLD3DUPdWB_register_Asm_32 = 263, + ARM_VLD3DUPdWB_register_Asm_8 = 264, + ARM_VLD3DUPqAsm_16 = 265, + ARM_VLD3DUPqAsm_32 = 266, + ARM_VLD3DUPqAsm_8 = 267, + ARM_VLD3DUPqWB_fixed_Asm_16 = 268, + ARM_VLD3DUPqWB_fixed_Asm_32 = 269, + ARM_VLD3DUPqWB_fixed_Asm_8 = 270, + ARM_VLD3DUPqWB_register_Asm_16 = 271, + ARM_VLD3DUPqWB_register_Asm_32 = 272, + ARM_VLD3DUPqWB_register_Asm_8 = 273, + ARM_VLD3LNdAsm_16 = 274, + ARM_VLD3LNdAsm_32 = 275, + ARM_VLD3LNdAsm_8 = 276, + ARM_VLD3LNdWB_fixed_Asm_16 = 277, + ARM_VLD3LNdWB_fixed_Asm_32 = 278, + ARM_VLD3LNdWB_fixed_Asm_8 = 279, + ARM_VLD3LNdWB_register_Asm_16 = 280, + ARM_VLD3LNdWB_register_Asm_32 = 281, + ARM_VLD3LNdWB_register_Asm_8 = 282, + ARM_VLD3LNqAsm_16 = 283, + ARM_VLD3LNqAsm_32 = 284, + ARM_VLD3LNqWB_fixed_Asm_16 = 285, + ARM_VLD3LNqWB_fixed_Asm_32 = 286, + ARM_VLD3LNqWB_register_Asm_16 = 287, + ARM_VLD3LNqWB_register_Asm_32 = 288, + ARM_VLD3dAsm_16 = 289, + ARM_VLD3dAsm_32 = 290, + ARM_VLD3dAsm_8 = 291, + ARM_VLD3dWB_fixed_Asm_16 = 292, + ARM_VLD3dWB_fixed_Asm_32 = 293, + ARM_VLD3dWB_fixed_Asm_8 = 294, + ARM_VLD3dWB_register_Asm_16 = 295, + ARM_VLD3dWB_register_Asm_32 = 296, + ARM_VLD3dWB_register_Asm_8 = 297, + ARM_VLD3qAsm_16 = 298, + ARM_VLD3qAsm_32 = 299, + ARM_VLD3qAsm_8 = 300, + ARM_VLD3qWB_fixed_Asm_16 = 301, + ARM_VLD3qWB_fixed_Asm_32 = 302, + ARM_VLD3qWB_fixed_Asm_8 = 303, + ARM_VLD3qWB_register_Asm_16 = 304, + ARM_VLD3qWB_register_Asm_32 = 305, + ARM_VLD3qWB_register_Asm_8 = 306, + ARM_VLD4DUPdAsm_16 = 307, + ARM_VLD4DUPdAsm_32 = 308, + ARM_VLD4DUPdAsm_8 = 309, + ARM_VLD4DUPdWB_fixed_Asm_16 = 310, + ARM_VLD4DUPdWB_fixed_Asm_32 = 311, + ARM_VLD4DUPdWB_fixed_Asm_8 = 312, + ARM_VLD4DUPdWB_register_Asm_16 = 313, + ARM_VLD4DUPdWB_register_Asm_32 = 314, + ARM_VLD4DUPdWB_register_Asm_8 = 315, + ARM_VLD4DUPqAsm_16 = 316, + ARM_VLD4DUPqAsm_32 = 317, + ARM_VLD4DUPqAsm_8 = 318, + ARM_VLD4DUPqWB_fixed_Asm_16 = 319, + ARM_VLD4DUPqWB_fixed_Asm_32 = 320, + ARM_VLD4DUPqWB_fixed_Asm_8 = 321, + ARM_VLD4DUPqWB_register_Asm_16 = 322, + ARM_VLD4DUPqWB_register_Asm_32 = 323, + ARM_VLD4DUPqWB_register_Asm_8 = 324, + ARM_VLD4LNdAsm_16 = 325, + ARM_VLD4LNdAsm_32 = 326, + ARM_VLD4LNdAsm_8 = 327, + ARM_VLD4LNdWB_fixed_Asm_16 = 328, + ARM_VLD4LNdWB_fixed_Asm_32 = 329, + ARM_VLD4LNdWB_fixed_Asm_8 = 330, + ARM_VLD4LNdWB_register_Asm_16 = 331, + ARM_VLD4LNdWB_register_Asm_32 = 332, + ARM_VLD4LNdWB_register_Asm_8 = 333, + ARM_VLD4LNqAsm_16 = 334, + ARM_VLD4LNqAsm_32 = 335, + ARM_VLD4LNqWB_fixed_Asm_16 = 336, + ARM_VLD4LNqWB_fixed_Asm_32 = 337, + ARM_VLD4LNqWB_register_Asm_16 = 338, + ARM_VLD4LNqWB_register_Asm_32 = 339, + ARM_VLD4dAsm_16 = 340, + ARM_VLD4dAsm_32 = 341, + ARM_VLD4dAsm_8 = 342, + ARM_VLD4dWB_fixed_Asm_16 = 343, + ARM_VLD4dWB_fixed_Asm_32 = 344, + ARM_VLD4dWB_fixed_Asm_8 = 345, + ARM_VLD4dWB_register_Asm_16 = 346, + ARM_VLD4dWB_register_Asm_32 = 347, + ARM_VLD4dWB_register_Asm_8 = 348, + ARM_VLD4qAsm_16 = 349, + ARM_VLD4qAsm_32 = 350, + ARM_VLD4qAsm_8 = 351, + ARM_VLD4qWB_fixed_Asm_16 = 352, + ARM_VLD4qWB_fixed_Asm_32 = 353, + ARM_VLD4qWB_fixed_Asm_8 = 354, + ARM_VLD4qWB_register_Asm_16 = 355, + ARM_VLD4qWB_register_Asm_32 = 356, + ARM_VLD4qWB_register_Asm_8 = 357, + ARM_VMOVD0 = 358, + ARM_VMOVDcc = 359, + ARM_VMOVQ0 = 360, + ARM_VMOVScc = 361, + ARM_VST1LNdAsm_16 = 362, + ARM_VST1LNdAsm_32 = 363, + ARM_VST1LNdAsm_8 = 364, + ARM_VST1LNdWB_fixed_Asm_16 = 365, + ARM_VST1LNdWB_fixed_Asm_32 = 366, + ARM_VST1LNdWB_fixed_Asm_8 = 367, + ARM_VST1LNdWB_register_Asm_16 = 368, + ARM_VST1LNdWB_register_Asm_32 = 369, + ARM_VST1LNdWB_register_Asm_8 = 370, + ARM_VST2LNdAsm_16 = 371, + ARM_VST2LNdAsm_32 = 372, + ARM_VST2LNdAsm_8 = 373, + ARM_VST2LNdWB_fixed_Asm_16 = 374, + ARM_VST2LNdWB_fixed_Asm_32 = 375, + ARM_VST2LNdWB_fixed_Asm_8 = 376, + ARM_VST2LNdWB_register_Asm_16 = 377, + ARM_VST2LNdWB_register_Asm_32 = 378, + ARM_VST2LNdWB_register_Asm_8 = 379, + ARM_VST2LNqAsm_16 = 380, + ARM_VST2LNqAsm_32 = 381, + ARM_VST2LNqWB_fixed_Asm_16 = 382, + ARM_VST2LNqWB_fixed_Asm_32 = 383, + ARM_VST2LNqWB_register_Asm_16 = 384, + ARM_VST2LNqWB_register_Asm_32 = 385, + ARM_VST3LNdAsm_16 = 386, + ARM_VST3LNdAsm_32 = 387, + ARM_VST3LNdAsm_8 = 388, + ARM_VST3LNdWB_fixed_Asm_16 = 389, + ARM_VST3LNdWB_fixed_Asm_32 = 390, + ARM_VST3LNdWB_fixed_Asm_8 = 391, + ARM_VST3LNdWB_register_Asm_16 = 392, + ARM_VST3LNdWB_register_Asm_32 = 393, + ARM_VST3LNdWB_register_Asm_8 = 394, + ARM_VST3LNqAsm_16 = 395, + ARM_VST3LNqAsm_32 = 396, + ARM_VST3LNqWB_fixed_Asm_16 = 397, + ARM_VST3LNqWB_fixed_Asm_32 = 398, + ARM_VST3LNqWB_register_Asm_16 = 399, + ARM_VST3LNqWB_register_Asm_32 = 400, + ARM_VST3dAsm_16 = 401, + ARM_VST3dAsm_32 = 402, + ARM_VST3dAsm_8 = 403, + ARM_VST3dWB_fixed_Asm_16 = 404, + ARM_VST3dWB_fixed_Asm_32 = 405, + ARM_VST3dWB_fixed_Asm_8 = 406, + ARM_VST3dWB_register_Asm_16 = 407, + ARM_VST3dWB_register_Asm_32 = 408, + ARM_VST3dWB_register_Asm_8 = 409, + ARM_VST3qAsm_16 = 410, + ARM_VST3qAsm_32 = 411, + ARM_VST3qAsm_8 = 412, + ARM_VST3qWB_fixed_Asm_16 = 413, + ARM_VST3qWB_fixed_Asm_32 = 414, + ARM_VST3qWB_fixed_Asm_8 = 415, + ARM_VST3qWB_register_Asm_16 = 416, + ARM_VST3qWB_register_Asm_32 = 417, + ARM_VST3qWB_register_Asm_8 = 418, + ARM_VST4LNdAsm_16 = 419, + ARM_VST4LNdAsm_32 = 420, + ARM_VST4LNdAsm_8 = 421, + ARM_VST4LNdWB_fixed_Asm_16 = 422, + ARM_VST4LNdWB_fixed_Asm_32 = 423, + ARM_VST4LNdWB_fixed_Asm_8 = 424, + ARM_VST4LNdWB_register_Asm_16 = 425, + ARM_VST4LNdWB_register_Asm_32 = 426, + ARM_VST4LNdWB_register_Asm_8 = 427, + ARM_VST4LNqAsm_16 = 428, + ARM_VST4LNqAsm_32 = 429, + ARM_VST4LNqWB_fixed_Asm_16 = 430, + ARM_VST4LNqWB_fixed_Asm_32 = 431, + ARM_VST4LNqWB_register_Asm_16 = 432, + ARM_VST4LNqWB_register_Asm_32 = 433, + ARM_VST4dAsm_16 = 434, + ARM_VST4dAsm_32 = 435, + ARM_VST4dAsm_8 = 436, + ARM_VST4dWB_fixed_Asm_16 = 437, + ARM_VST4dWB_fixed_Asm_32 = 438, + ARM_VST4dWB_fixed_Asm_8 = 439, + ARM_VST4dWB_register_Asm_16 = 440, + ARM_VST4dWB_register_Asm_32 = 441, + ARM_VST4dWB_register_Asm_8 = 442, + ARM_VST4qAsm_16 = 443, + ARM_VST4qAsm_32 = 444, + ARM_VST4qAsm_8 = 445, + ARM_VST4qWB_fixed_Asm_16 = 446, + ARM_VST4qWB_fixed_Asm_32 = 447, + ARM_VST4qWB_fixed_Asm_8 = 448, + ARM_VST4qWB_register_Asm_16 = 449, + ARM_VST4qWB_register_Asm_32 = 450, + ARM_VST4qWB_register_Asm_8 = 451, + ARM_t2ABS = 454, + ARM_t2ADDSri = 455, + ARM_t2ADDSrr = 456, + ARM_t2ADDSrs = 457, + ARM_t2BR_JT = 458, + ARM_t2LDMIA_RET = 459, + ARM_t2LDRBpcrel = 460, + ARM_t2LDRConstPool = 461, + ARM_t2LDRHpcrel = 462, + ARM_t2LDRSBpcrel = 463, + ARM_t2LDRSHpcrel = 464, + ARM_t2LDRpci_pic = 465, + ARM_t2LDRpcrel = 466, + ARM_t2LEApcrel = 467, + ARM_t2LEApcrelJT = 468, + ARM_t2MOVCCasr = 469, + ARM_t2MOVCCi = 470, + ARM_t2MOVCCi16 = 471, + ARM_t2MOVCCi32imm = 472, + ARM_t2MOVCClsl = 473, + ARM_t2MOVCClsr = 474, + ARM_t2MOVCCr = 475, + ARM_t2MOVCCror = 476, + ARM_t2MOVSsi = 477, + ARM_t2MOVSsr = 478, + ARM_t2MOVTi16_ga_pcrel = 479, + ARM_t2MOV_ga_pcrel = 480, + ARM_t2MOVi16_ga_pcrel = 481, + ARM_t2MOVi32imm = 482, + ARM_t2MOVsi = 483, + ARM_t2MOVsr = 484, + ARM_t2MVNCCi = 485, + ARM_t2RSBSri = 486, + ARM_t2RSBSrs = 487, + ARM_t2STRB_preidx = 488, + ARM_t2STRH_preidx = 489, + ARM_t2STR_preidx = 490, + ARM_t2SUBSri = 491, + ARM_t2SUBSrr = 492, + ARM_t2SUBSrs = 493, + ARM_t2TBB_JT = 494, + ARM_t2TBH_JT = 495, + ARM_tADCS = 496, + ARM_tADDSi3 = 497, + ARM_tADDSi8 = 498, + ARM_tADDSrr = 499, + ARM_tADDframe = 500, + ARM_tADJCALLSTACKDOWN = 501, + ARM_tADJCALLSTACKUP = 502, + ARM_tBRIND = 503, + ARM_tBR_JTr = 504, + ARM_tBX_CALL = 505, + ARM_tBX_RET = 506, + ARM_tBX_RET_vararg = 507, + ARM_tBfar = 508, + ARM_tLDMIA_UPD = 509, + ARM_tLDRConstPool = 510, + ARM_tLDRLIT_ga_abs = 511, + ARM_tLDRLIT_ga_pcrel = 512, + ARM_tLDR_postidx = 513, + ARM_tLDRpci_pic = 514, + ARM_tLEApcrel = 515, + ARM_tLEApcrelJT = 516, + ARM_tMOVCCr_pseudo = 517, + ARM_tPOP_RET = 518, + ARM_tSBCS = 519, + ARM_tSUBSi3 = 520, + ARM_tSUBSi8 = 521, + ARM_tSUBSrr = 522, + ARM_tTAILJMPd = 523, + ARM_tTAILJMPdND = 524, + ARM_tTAILJMPr = 525, + ARM_tTBB_JT = 526, + ARM_tTBH_JT = 527, + ARM_tTPsoft = 528, + ARM_ADCri = 529, + ARM_ADCrr = 530, + ARM_ADCrsi = 531, + ARM_ADCrsr = 532, + ARM_ADDri = 533, + ARM_ADDrr = 534, + ARM_ADDrsi = 535, + ARM_ADDrsr = 536, + ARM_ADR = 537, + ARM_AESD = 538, + ARM_AESE = 539, + ARM_AESIMC = 540, + ARM_AESMC = 541, + ARM_ANDri = 542, + ARM_ANDrr = 543, + ARM_ANDrsi = 544, + ARM_ANDrsr = 545, + ARM_BFC = 546, + ARM_BFI = 547, + ARM_BICri = 548, + ARM_BICrr = 549, + ARM_BICrsi = 550, + ARM_BICrsr = 551, + ARM_BKPT = 552, + ARM_BL = 553, + ARM_BLX = 554, + ARM_BLX_pred = 555, + ARM_BLXi = 556, + ARM_BL_pred = 557, + ARM_BX = 558, + ARM_BXJ = 559, + ARM_BX_RET = 560, + ARM_BX_pred = 561, + ARM_Bcc = 562, + ARM_CDP = 563, + ARM_CDP2 = 564, + ARM_CLREX = 565, + ARM_CLZ = 566, + ARM_CMNri = 567, + ARM_CMNzrr = 568, + ARM_CMNzrsi = 569, + ARM_CMNzrsr = 570, + ARM_CMPri = 571, + ARM_CMPrr = 572, + ARM_CMPrsi = 573, + ARM_CMPrsr = 574, + ARM_CPS1p = 575, + ARM_CPS2p = 576, + ARM_CPS3p = 577, + ARM_CRC32B = 578, + ARM_CRC32CB = 579, + ARM_CRC32CH = 580, + ARM_CRC32CW = 581, + ARM_CRC32H = 582, + ARM_CRC32W = 583, + ARM_DBG = 584, + ARM_DMB = 585, + ARM_DSB = 586, + ARM_EORri = 587, + ARM_EORrr = 588, + ARM_EORrsi = 589, + ARM_EORrsr = 590, + ARM_ERET = 591, + ARM_FCONSTD = 592, + ARM_FCONSTH = 593, + ARM_FCONSTS = 594, + ARM_FLDMXDB_UPD = 595, + ARM_FLDMXIA = 596, + ARM_FLDMXIA_UPD = 597, + ARM_FMSTAT = 598, + ARM_FSTMXDB_UPD = 599, + ARM_FSTMXIA = 600, + ARM_FSTMXIA_UPD = 601, + ARM_HINT = 602, + ARM_HLT = 603, + ARM_HVC = 604, + ARM_ISB = 605, + ARM_LDA = 606, + ARM_LDAB = 607, + ARM_LDAEX = 608, + ARM_LDAEXB = 609, + ARM_LDAEXD = 610, + ARM_LDAEXH = 611, + ARM_LDAH = 612, + ARM_LDC2L_OFFSET = 613, + ARM_LDC2L_OPTION = 614, + ARM_LDC2L_POST = 615, + ARM_LDC2L_PRE = 616, + ARM_LDC2_OFFSET = 617, + ARM_LDC2_OPTION = 618, + ARM_LDC2_POST = 619, + ARM_LDC2_PRE = 620, + ARM_LDCL_OFFSET = 621, + ARM_LDCL_OPTION = 622, + ARM_LDCL_POST = 623, + ARM_LDCL_PRE = 624, + ARM_LDC_OFFSET = 625, + ARM_LDC_OPTION = 626, + ARM_LDC_POST = 627, + ARM_LDC_PRE = 628, + ARM_LDMDA = 629, + ARM_LDMDA_UPD = 630, + ARM_LDMDB = 631, + ARM_LDMDB_UPD = 632, + ARM_LDMIA = 633, + ARM_LDMIA_UPD = 634, + ARM_LDMIB = 635, + ARM_LDMIB_UPD = 636, + ARM_LDRBT_POST_IMM = 637, + ARM_LDRBT_POST_REG = 638, + ARM_LDRB_POST_IMM = 639, + ARM_LDRB_POST_REG = 640, + ARM_LDRB_PRE_IMM = 641, + ARM_LDRB_PRE_REG = 642, + ARM_LDRBi12 = 643, + ARM_LDRBrs = 644, + ARM_LDRD = 645, + ARM_LDRD_POST = 646, + ARM_LDRD_PRE = 647, + ARM_LDREX = 648, + ARM_LDREXB = 649, + ARM_LDREXD = 650, + ARM_LDREXH = 651, + ARM_LDRH = 652, + ARM_LDRHTi = 653, + ARM_LDRHTr = 654, + ARM_LDRH_POST = 655, + ARM_LDRH_PRE = 656, + ARM_LDRSB = 657, + ARM_LDRSBTi = 658, + ARM_LDRSBTr = 659, + ARM_LDRSB_POST = 660, + ARM_LDRSB_PRE = 661, + ARM_LDRSH = 662, + ARM_LDRSHTi = 663, + ARM_LDRSHTr = 664, + ARM_LDRSH_POST = 665, + ARM_LDRSH_PRE = 666, + ARM_LDRT_POST_IMM = 667, + ARM_LDRT_POST_REG = 668, + ARM_LDR_POST_IMM = 669, + ARM_LDR_POST_REG = 670, + ARM_LDR_PRE_IMM = 671, + ARM_LDR_PRE_REG = 672, + ARM_LDRcp = 673, + ARM_LDRi12 = 674, + ARM_LDRrs = 675, + ARM_MCR = 676, + ARM_MCR2 = 677, + ARM_MCRR = 678, + ARM_MCRR2 = 679, + ARM_MLA = 680, + ARM_MLS = 681, + ARM_MOVPCLR = 682, + ARM_MOVTi16 = 683, + ARM_MOVi = 684, + ARM_MOVi16 = 685, + ARM_MOVr = 686, + ARM_MOVr_TC = 687, + ARM_MOVsi = 688, + ARM_MOVsr = 689, + ARM_MRC = 690, + ARM_MRC2 = 691, + ARM_MRRC = 692, + ARM_MRRC2 = 693, + ARM_MRS = 694, + ARM_MRSbanked = 695, + ARM_MRSsys = 696, + ARM_MSR = 697, + ARM_MSRbanked = 698, + ARM_MSRi = 699, + ARM_MUL = 700, + ARM_MVNi = 701, + ARM_MVNr = 702, + ARM_MVNsi = 703, + ARM_MVNsr = 704, + ARM_ORRri = 705, + ARM_ORRrr = 706, + ARM_ORRrsi = 707, + ARM_ORRrsr = 708, + ARM_PKHBT = 709, + ARM_PKHTB = 710, + ARM_PLDWi12 = 711, + ARM_PLDWrs = 712, + ARM_PLDi12 = 713, + ARM_PLDrs = 714, + ARM_PLIi12 = 715, + ARM_PLIrs = 716, + ARM_QADD = 717, + ARM_QADD16 = 718, + ARM_QADD8 = 719, + ARM_QASX = 720, + ARM_QDADD = 721, + ARM_QDSUB = 722, + ARM_QSAX = 723, + ARM_QSUB = 724, + ARM_QSUB16 = 725, + ARM_QSUB8 = 726, + ARM_RBIT = 727, + ARM_REV = 728, + ARM_REV16 = 729, + ARM_REVSH = 730, + ARM_RFEDA = 731, + ARM_RFEDA_UPD = 732, + ARM_RFEDB = 733, + ARM_RFEDB_UPD = 734, + ARM_RFEIA = 735, + ARM_RFEIA_UPD = 736, + ARM_RFEIB = 737, + ARM_RFEIB_UPD = 738, + ARM_RSBri = 739, + ARM_RSBrr = 740, + ARM_RSBrsi = 741, + ARM_RSBrsr = 742, + ARM_RSCri = 743, + ARM_RSCrr = 744, + ARM_RSCrsi = 745, + ARM_RSCrsr = 746, + ARM_SADD16 = 747, + ARM_SADD8 = 748, + ARM_SASX = 749, + ARM_SBCri = 750, + ARM_SBCrr = 751, + ARM_SBCrsi = 752, + ARM_SBCrsr = 753, + ARM_SBFX = 754, + ARM_SDIV = 755, + ARM_SEL = 756, + ARM_SETEND = 757, + ARM_SETPAN = 758, + ARM_SHA1C = 759, + ARM_SHA1H = 760, + ARM_SHA1M = 761, + ARM_SHA1P = 762, + ARM_SHA1SU0 = 763, + ARM_SHA1SU1 = 764, + ARM_SHA256H = 765, + ARM_SHA256H2 = 766, + ARM_SHA256SU0 = 767, + ARM_SHA256SU1 = 768, + ARM_SHADD16 = 769, + ARM_SHADD8 = 770, + ARM_SHASX = 771, + ARM_SHSAX = 772, + ARM_SHSUB16 = 773, + ARM_SHSUB8 = 774, + ARM_SMC = 775, + ARM_SMLABB = 776, + ARM_SMLABT = 777, + ARM_SMLAD = 778, + ARM_SMLADX = 779, + ARM_SMLAL = 780, + ARM_SMLALBB = 781, + ARM_SMLALBT = 782, + ARM_SMLALD = 783, + ARM_SMLALDX = 784, + ARM_SMLALTB = 785, + ARM_SMLALTT = 786, + ARM_SMLATB = 787, + ARM_SMLATT = 788, + ARM_SMLAWB = 789, + ARM_SMLAWT = 790, + ARM_SMLSD = 791, + ARM_SMLSDX = 792, + ARM_SMLSLD = 793, + ARM_SMLSLDX = 794, + ARM_SMMLA = 795, + ARM_SMMLAR = 796, + ARM_SMMLS = 797, + ARM_SMMLSR = 798, + ARM_SMMUL = 799, + ARM_SMMULR = 800, + ARM_SMUAD = 801, + ARM_SMUADX = 802, + ARM_SMULBB = 803, + ARM_SMULBT = 804, + ARM_SMULL = 805, + ARM_SMULTB = 806, + ARM_SMULTT = 807, + ARM_SMULWB = 808, + ARM_SMULWT = 809, + ARM_SMUSD = 810, + ARM_SMUSDX = 811, + ARM_SRSDA = 812, + ARM_SRSDA_UPD = 813, + ARM_SRSDB = 814, + ARM_SRSDB_UPD = 815, + ARM_SRSIA = 816, + ARM_SRSIA_UPD = 817, + ARM_SRSIB = 818, + ARM_SRSIB_UPD = 819, + ARM_SSAT = 820, + ARM_SSAT16 = 821, + ARM_SSAX = 822, + ARM_SSUB16 = 823, + ARM_SSUB8 = 824, + ARM_STC2L_OFFSET = 825, + ARM_STC2L_OPTION = 826, + ARM_STC2L_POST = 827, + ARM_STC2L_PRE = 828, + ARM_STC2_OFFSET = 829, + ARM_STC2_OPTION = 830, + ARM_STC2_POST = 831, + ARM_STC2_PRE = 832, + ARM_STCL_OFFSET = 833, + ARM_STCL_OPTION = 834, + ARM_STCL_POST = 835, + ARM_STCL_PRE = 836, + ARM_STC_OFFSET = 837, + ARM_STC_OPTION = 838, + ARM_STC_POST = 839, + ARM_STC_PRE = 840, + ARM_STL = 841, + ARM_STLB = 842, + ARM_STLEX = 843, + ARM_STLEXB = 844, + ARM_STLEXD = 845, + ARM_STLEXH = 846, + ARM_STLH = 847, + ARM_STMDA = 848, + ARM_STMDA_UPD = 849, + ARM_STMDB = 850, + ARM_STMDB_UPD = 851, + ARM_STMIA = 852, + ARM_STMIA_UPD = 853, + ARM_STMIB = 854, + ARM_STMIB_UPD = 855, + ARM_STRBT_POST_IMM = 856, + ARM_STRBT_POST_REG = 857, + ARM_STRB_POST_IMM = 858, + ARM_STRB_POST_REG = 859, + ARM_STRB_PRE_IMM = 860, + ARM_STRB_PRE_REG = 861, + ARM_STRBi12 = 862, + ARM_STRBrs = 863, + ARM_STRD = 864, + ARM_STRD_POST = 865, + ARM_STRD_PRE = 866, + ARM_STREX = 867, + ARM_STREXB = 868, + ARM_STREXD = 869, + ARM_STREXH = 870, + ARM_STRH = 871, + ARM_STRHTi = 872, + ARM_STRHTr = 873, + ARM_STRH_POST = 874, + ARM_STRH_PRE = 875, + ARM_STRT_POST_IMM = 876, + ARM_STRT_POST_REG = 877, + ARM_STR_POST_IMM = 878, + ARM_STR_POST_REG = 879, + ARM_STR_PRE_IMM = 880, + ARM_STR_PRE_REG = 881, + ARM_STRi12 = 882, + ARM_STRrs = 883, + ARM_SUBri = 884, + ARM_SUBrr = 885, + ARM_SUBrsi = 886, + ARM_SUBrsr = 887, + ARM_SVC = 888, + ARM_SWP = 889, + ARM_SWPB = 890, + ARM_SXTAB = 891, + ARM_SXTAB16 = 892, + ARM_SXTAH = 893, + ARM_SXTB = 894, + ARM_SXTB16 = 895, + ARM_SXTH = 896, + ARM_TEQri = 897, + ARM_TEQrr = 898, + ARM_TEQrsi = 899, + ARM_TEQrsr = 900, + ARM_TRAP = 901, + ARM_TRAPNaCl = 902, + ARM_TSB = 903, + ARM_TSTri = 904, + ARM_TSTrr = 905, + ARM_TSTrsi = 906, + ARM_TSTrsr = 907, + ARM_UADD16 = 908, + ARM_UADD8 = 909, + ARM_UASX = 910, + ARM_UBFX = 911, + ARM_UDF = 912, + ARM_UDIV = 913, + ARM_UHADD16 = 914, + ARM_UHADD8 = 915, + ARM_UHASX = 916, + ARM_UHSAX = 917, + ARM_UHSUB16 = 918, + ARM_UHSUB8 = 919, + ARM_UMAAL = 920, + ARM_UMLAL = 921, + ARM_UMULL = 922, + ARM_UQADD16 = 923, + ARM_UQADD8 = 924, + ARM_UQASX = 925, + ARM_UQSAX = 926, + ARM_UQSUB16 = 927, + ARM_UQSUB8 = 928, + ARM_USAD8 = 929, + ARM_USADA8 = 930, + ARM_USAT = 931, + ARM_USAT16 = 932, + ARM_USAX = 933, + ARM_USUB16 = 934, + ARM_USUB8 = 935, + ARM_UXTAB = 936, + ARM_UXTAB16 = 937, + ARM_UXTAH = 938, + ARM_UXTB = 939, + ARM_UXTB16 = 940, + ARM_UXTH = 941, + ARM_VABALsv2i64 = 942, + ARM_VABALsv4i32 = 943, + ARM_VABALsv8i16 = 944, + ARM_VABALuv2i64 = 945, + ARM_VABALuv4i32 = 946, + ARM_VABALuv8i16 = 947, + ARM_VABAsv16i8 = 948, + ARM_VABAsv2i32 = 949, + ARM_VABAsv4i16 = 950, + ARM_VABAsv4i32 = 951, + ARM_VABAsv8i16 = 952, + ARM_VABAsv8i8 = 953, + ARM_VABAuv16i8 = 954, + ARM_VABAuv2i32 = 955, + ARM_VABAuv4i16 = 956, + ARM_VABAuv4i32 = 957, + ARM_VABAuv8i16 = 958, + ARM_VABAuv8i8 = 959, + ARM_VABDLsv2i64 = 960, + ARM_VABDLsv4i32 = 961, + ARM_VABDLsv8i16 = 962, + ARM_VABDLuv2i64 = 963, + ARM_VABDLuv4i32 = 964, + ARM_VABDLuv8i16 = 965, + ARM_VABDfd = 966, + ARM_VABDfq = 967, + ARM_VABDhd = 968, + ARM_VABDhq = 969, + ARM_VABDsv16i8 = 970, + ARM_VABDsv2i32 = 971, + ARM_VABDsv4i16 = 972, + ARM_VABDsv4i32 = 973, + ARM_VABDsv8i16 = 974, + ARM_VABDsv8i8 = 975, + ARM_VABDuv16i8 = 976, + ARM_VABDuv2i32 = 977, + ARM_VABDuv4i16 = 978, + ARM_VABDuv4i32 = 979, + ARM_VABDuv8i16 = 980, + ARM_VABDuv8i8 = 981, + ARM_VABSD = 982, + ARM_VABSH = 983, + ARM_VABSS = 984, + ARM_VABSfd = 985, + ARM_VABSfq = 986, + ARM_VABShd = 987, + ARM_VABShq = 988, + ARM_VABSv16i8 = 989, + ARM_VABSv2i32 = 990, + ARM_VABSv4i16 = 991, + ARM_VABSv4i32 = 992, + ARM_VABSv8i16 = 993, + ARM_VABSv8i8 = 994, + ARM_VACGEfd = 995, + ARM_VACGEfq = 996, + ARM_VACGEhd = 997, + ARM_VACGEhq = 998, + ARM_VACGTfd = 999, + ARM_VACGTfq = 1000, + ARM_VACGThd = 1001, + ARM_VACGThq = 1002, + ARM_VADDD = 1003, + ARM_VADDH = 1004, + ARM_VADDHNv2i32 = 1005, + ARM_VADDHNv4i16 = 1006, + ARM_VADDHNv8i8 = 1007, + ARM_VADDLsv2i64 = 1008, + ARM_VADDLsv4i32 = 1009, + ARM_VADDLsv8i16 = 1010, + ARM_VADDLuv2i64 = 1011, + ARM_VADDLuv4i32 = 1012, + ARM_VADDLuv8i16 = 1013, + ARM_VADDS = 1014, + ARM_VADDWsv2i64 = 1015, + ARM_VADDWsv4i32 = 1016, + ARM_VADDWsv8i16 = 1017, + ARM_VADDWuv2i64 = 1018, + ARM_VADDWuv4i32 = 1019, + ARM_VADDWuv8i16 = 1020, + ARM_VADDfd = 1021, + ARM_VADDfq = 1022, + ARM_VADDhd = 1023, + ARM_VADDhq = 1024, + ARM_VADDv16i8 = 1025, + ARM_VADDv1i64 = 1026, + ARM_VADDv2i32 = 1027, + ARM_VADDv2i64 = 1028, + ARM_VADDv4i16 = 1029, + ARM_VADDv4i32 = 1030, + ARM_VADDv8i16 = 1031, + ARM_VADDv8i8 = 1032, + ARM_VANDd = 1033, + ARM_VANDq = 1034, + ARM_VBICd = 1035, + ARM_VBICiv2i32 = 1036, + ARM_VBICiv4i16 = 1037, + ARM_VBICiv4i32 = 1038, + ARM_VBICiv8i16 = 1039, + ARM_VBICq = 1040, + ARM_VBIFd = 1041, + ARM_VBIFq = 1042, + ARM_VBITd = 1043, + ARM_VBITq = 1044, + ARM_VBSLd = 1045, + ARM_VBSLq = 1046, + ARM_VCADDv2f32 = 1047, + ARM_VCADDv4f16 = 1048, + ARM_VCADDv4f32 = 1049, + ARM_VCADDv8f16 = 1050, + ARM_VCEQfd = 1051, + ARM_VCEQfq = 1052, + ARM_VCEQhd = 1053, + ARM_VCEQhq = 1054, + ARM_VCEQv16i8 = 1055, + ARM_VCEQv2i32 = 1056, + ARM_VCEQv4i16 = 1057, + ARM_VCEQv4i32 = 1058, + ARM_VCEQv8i16 = 1059, + ARM_VCEQv8i8 = 1060, + ARM_VCEQzv16i8 = 1061, + ARM_VCEQzv2f32 = 1062, + ARM_VCEQzv2i32 = 1063, + ARM_VCEQzv4f16 = 1064, + ARM_VCEQzv4f32 = 1065, + ARM_VCEQzv4i16 = 1066, + ARM_VCEQzv4i32 = 1067, + ARM_VCEQzv8f16 = 1068, + ARM_VCEQzv8i16 = 1069, + ARM_VCEQzv8i8 = 1070, + ARM_VCGEfd = 1071, + ARM_VCGEfq = 1072, + ARM_VCGEhd = 1073, + ARM_VCGEhq = 1074, + ARM_VCGEsv16i8 = 1075, + ARM_VCGEsv2i32 = 1076, + ARM_VCGEsv4i16 = 1077, + ARM_VCGEsv4i32 = 1078, + ARM_VCGEsv8i16 = 1079, + ARM_VCGEsv8i8 = 1080, + ARM_VCGEuv16i8 = 1081, + ARM_VCGEuv2i32 = 1082, + ARM_VCGEuv4i16 = 1083, + ARM_VCGEuv4i32 = 1084, + ARM_VCGEuv8i16 = 1085, + ARM_VCGEuv8i8 = 1086, + ARM_VCGEzv16i8 = 1087, + ARM_VCGEzv2f32 = 1088, + ARM_VCGEzv2i32 = 1089, + ARM_VCGEzv4f16 = 1090, + ARM_VCGEzv4f32 = 1091, + ARM_VCGEzv4i16 = 1092, + ARM_VCGEzv4i32 = 1093, + ARM_VCGEzv8f16 = 1094, + ARM_VCGEzv8i16 = 1095, + ARM_VCGEzv8i8 = 1096, + ARM_VCGTfd = 1097, + ARM_VCGTfq = 1098, + ARM_VCGThd = 1099, + ARM_VCGThq = 1100, + ARM_VCGTsv16i8 = 1101, + ARM_VCGTsv2i32 = 1102, + ARM_VCGTsv4i16 = 1103, + ARM_VCGTsv4i32 = 1104, + ARM_VCGTsv8i16 = 1105, + ARM_VCGTsv8i8 = 1106, + ARM_VCGTuv16i8 = 1107, + ARM_VCGTuv2i32 = 1108, + ARM_VCGTuv4i16 = 1109, + ARM_VCGTuv4i32 = 1110, + ARM_VCGTuv8i16 = 1111, + ARM_VCGTuv8i8 = 1112, + ARM_VCGTzv16i8 = 1113, + ARM_VCGTzv2f32 = 1114, + ARM_VCGTzv2i32 = 1115, + ARM_VCGTzv4f16 = 1116, + ARM_VCGTzv4f32 = 1117, + ARM_VCGTzv4i16 = 1118, + ARM_VCGTzv4i32 = 1119, + ARM_VCGTzv8f16 = 1120, + ARM_VCGTzv8i16 = 1121, + ARM_VCGTzv8i8 = 1122, + ARM_VCLEzv16i8 = 1123, + ARM_VCLEzv2f32 = 1124, + ARM_VCLEzv2i32 = 1125, + ARM_VCLEzv4f16 = 1126, + ARM_VCLEzv4f32 = 1127, + ARM_VCLEzv4i16 = 1128, + ARM_VCLEzv4i32 = 1129, + ARM_VCLEzv8f16 = 1130, + ARM_VCLEzv8i16 = 1131, + ARM_VCLEzv8i8 = 1132, + ARM_VCLSv16i8 = 1133, + ARM_VCLSv2i32 = 1134, + ARM_VCLSv4i16 = 1135, + ARM_VCLSv4i32 = 1136, + ARM_VCLSv8i16 = 1137, + ARM_VCLSv8i8 = 1138, + ARM_VCLTzv16i8 = 1139, + ARM_VCLTzv2f32 = 1140, + ARM_VCLTzv2i32 = 1141, + ARM_VCLTzv4f16 = 1142, + ARM_VCLTzv4f32 = 1143, + ARM_VCLTzv4i16 = 1144, + ARM_VCLTzv4i32 = 1145, + ARM_VCLTzv8f16 = 1146, + ARM_VCLTzv8i16 = 1147, + ARM_VCLTzv8i8 = 1148, + ARM_VCLZv16i8 = 1149, + ARM_VCLZv2i32 = 1150, + ARM_VCLZv4i16 = 1151, + ARM_VCLZv4i32 = 1152, + ARM_VCLZv8i16 = 1153, + ARM_VCLZv8i8 = 1154, + ARM_VCMLAv2f32 = 1155, + ARM_VCMLAv2f32_indexed = 1156, + ARM_VCMLAv4f16 = 1157, + ARM_VCMLAv4f16_indexed = 1158, + ARM_VCMLAv4f32 = 1159, + ARM_VCMLAv4f32_indexed = 1160, + ARM_VCMLAv8f16 = 1161, + ARM_VCMLAv8f16_indexed = 1162, + ARM_VCMPD = 1163, + ARM_VCMPED = 1164, + ARM_VCMPEH = 1165, + ARM_VCMPES = 1166, + ARM_VCMPEZD = 1167, + ARM_VCMPEZH = 1168, + ARM_VCMPEZS = 1169, + ARM_VCMPH = 1170, + ARM_VCMPS = 1171, + ARM_VCMPZD = 1172, + ARM_VCMPZH = 1173, + ARM_VCMPZS = 1174, + ARM_VCNTd = 1175, + ARM_VCNTq = 1176, + ARM_VCVTANSDf = 1177, + ARM_VCVTANSDh = 1178, + ARM_VCVTANSQf = 1179, + ARM_VCVTANSQh = 1180, + ARM_VCVTANUDf = 1181, + ARM_VCVTANUDh = 1182, + ARM_VCVTANUQf = 1183, + ARM_VCVTANUQh = 1184, + ARM_VCVTASD = 1185, + ARM_VCVTASH = 1186, + ARM_VCVTASS = 1187, + ARM_VCVTAUD = 1188, + ARM_VCVTAUH = 1189, + ARM_VCVTAUS = 1190, + ARM_VCVTBDH = 1191, + ARM_VCVTBHD = 1192, + ARM_VCVTBHS = 1193, + ARM_VCVTBSH = 1194, + ARM_VCVTDS = 1195, + ARM_VCVTMNSDf = 1196, + ARM_VCVTMNSDh = 1197, + ARM_VCVTMNSQf = 1198, + ARM_VCVTMNSQh = 1199, + ARM_VCVTMNUDf = 1200, + ARM_VCVTMNUDh = 1201, + ARM_VCVTMNUQf = 1202, + ARM_VCVTMNUQh = 1203, + ARM_VCVTMSD = 1204, + ARM_VCVTMSH = 1205, + ARM_VCVTMSS = 1206, + ARM_VCVTMUD = 1207, + ARM_VCVTMUH = 1208, + ARM_VCVTMUS = 1209, + ARM_VCVTNNSDf = 1210, + ARM_VCVTNNSDh = 1211, + ARM_VCVTNNSQf = 1212, + ARM_VCVTNNSQh = 1213, + ARM_VCVTNNUDf = 1214, + ARM_VCVTNNUDh = 1215, + ARM_VCVTNNUQf = 1216, + ARM_VCVTNNUQh = 1217, + ARM_VCVTNSD = 1218, + ARM_VCVTNSH = 1219, + ARM_VCVTNSS = 1220, + ARM_VCVTNUD = 1221, + ARM_VCVTNUH = 1222, + ARM_VCVTNUS = 1223, + ARM_VCVTPNSDf = 1224, + ARM_VCVTPNSDh = 1225, + ARM_VCVTPNSQf = 1226, + ARM_VCVTPNSQh = 1227, + ARM_VCVTPNUDf = 1228, + ARM_VCVTPNUDh = 1229, + ARM_VCVTPNUQf = 1230, + ARM_VCVTPNUQh = 1231, + ARM_VCVTPSD = 1232, + ARM_VCVTPSH = 1233, + ARM_VCVTPSS = 1234, + ARM_VCVTPUD = 1235, + ARM_VCVTPUH = 1236, + ARM_VCVTPUS = 1237, + ARM_VCVTSD = 1238, + ARM_VCVTTDH = 1239, + ARM_VCVTTHD = 1240, + ARM_VCVTTHS = 1241, + ARM_VCVTTSH = 1242, + ARM_VCVTf2h = 1243, + ARM_VCVTf2sd = 1244, + ARM_VCVTf2sq = 1245, + ARM_VCVTf2ud = 1246, + ARM_VCVTf2uq = 1247, + ARM_VCVTf2xsd = 1248, + ARM_VCVTf2xsq = 1249, + ARM_VCVTf2xud = 1250, + ARM_VCVTf2xuq = 1251, + ARM_VCVTh2f = 1252, + ARM_VCVTh2sd = 1253, + ARM_VCVTh2sq = 1254, + ARM_VCVTh2ud = 1255, + ARM_VCVTh2uq = 1256, + ARM_VCVTh2xsd = 1257, + ARM_VCVTh2xsq = 1258, + ARM_VCVTh2xud = 1259, + ARM_VCVTh2xuq = 1260, + ARM_VCVTs2fd = 1261, + ARM_VCVTs2fq = 1262, + ARM_VCVTs2hd = 1263, + ARM_VCVTs2hq = 1264, + ARM_VCVTu2fd = 1265, + ARM_VCVTu2fq = 1266, + ARM_VCVTu2hd = 1267, + ARM_VCVTu2hq = 1268, + ARM_VCVTxs2fd = 1269, + ARM_VCVTxs2fq = 1270, + ARM_VCVTxs2hd = 1271, + ARM_VCVTxs2hq = 1272, + ARM_VCVTxu2fd = 1273, + ARM_VCVTxu2fq = 1274, + ARM_VCVTxu2hd = 1275, + ARM_VCVTxu2hq = 1276, + ARM_VDIVD = 1277, + ARM_VDIVH = 1278, + ARM_VDIVS = 1279, + ARM_VDUP16d = 1280, + ARM_VDUP16q = 1281, + ARM_VDUP32d = 1282, + ARM_VDUP32q = 1283, + ARM_VDUP8d = 1284, + ARM_VDUP8q = 1285, + ARM_VDUPLN16d = 1286, + ARM_VDUPLN16q = 1287, + ARM_VDUPLN32d = 1288, + ARM_VDUPLN32q = 1289, + ARM_VDUPLN8d = 1290, + ARM_VDUPLN8q = 1291, + ARM_VEORd = 1292, + ARM_VEORq = 1293, + ARM_VEXTd16 = 1294, + ARM_VEXTd32 = 1295, + ARM_VEXTd8 = 1296, + ARM_VEXTq16 = 1297, + ARM_VEXTq32 = 1298, + ARM_VEXTq64 = 1299, + ARM_VEXTq8 = 1300, + ARM_VFMAD = 1301, + ARM_VFMAH = 1302, + ARM_VFMAS = 1303, + ARM_VFMAfd = 1304, + ARM_VFMAfq = 1305, + ARM_VFMAhd = 1306, + ARM_VFMAhq = 1307, + ARM_VFMSD = 1308, + ARM_VFMSH = 1309, + ARM_VFMSS = 1310, + ARM_VFMSfd = 1311, + ARM_VFMSfq = 1312, + ARM_VFMShd = 1313, + ARM_VFMShq = 1314, + ARM_VFNMAD = 1315, + ARM_VFNMAH = 1316, + ARM_VFNMAS = 1317, + ARM_VFNMSD = 1318, + ARM_VFNMSH = 1319, + ARM_VFNMSS = 1320, + ARM_VGETLNi32 = 1321, + ARM_VGETLNs16 = 1322, + ARM_VGETLNs8 = 1323, + ARM_VGETLNu16 = 1324, + ARM_VGETLNu8 = 1325, + ARM_VHADDsv16i8 = 1326, + ARM_VHADDsv2i32 = 1327, + ARM_VHADDsv4i16 = 1328, + ARM_VHADDsv4i32 = 1329, + ARM_VHADDsv8i16 = 1330, + ARM_VHADDsv8i8 = 1331, + ARM_VHADDuv16i8 = 1332, + ARM_VHADDuv2i32 = 1333, + ARM_VHADDuv4i16 = 1334, + ARM_VHADDuv4i32 = 1335, + ARM_VHADDuv8i16 = 1336, + ARM_VHADDuv8i8 = 1337, + ARM_VHSUBsv16i8 = 1338, + ARM_VHSUBsv2i32 = 1339, + ARM_VHSUBsv4i16 = 1340, + ARM_VHSUBsv4i32 = 1341, + ARM_VHSUBsv8i16 = 1342, + ARM_VHSUBsv8i8 = 1343, + ARM_VHSUBuv16i8 = 1344, + ARM_VHSUBuv2i32 = 1345, + ARM_VHSUBuv4i16 = 1346, + ARM_VHSUBuv4i32 = 1347, + ARM_VHSUBuv8i16 = 1348, + ARM_VHSUBuv8i8 = 1349, + ARM_VINSH = 1350, + ARM_VJCVT = 1351, + ARM_VLD1DUPd16 = 1352, + ARM_VLD1DUPd16wb_fixed = 1353, + ARM_VLD1DUPd16wb_register = 1354, + ARM_VLD1DUPd32 = 1355, + ARM_VLD1DUPd32wb_fixed = 1356, + ARM_VLD1DUPd32wb_register = 1357, + ARM_VLD1DUPd8 = 1358, + ARM_VLD1DUPd8wb_fixed = 1359, + ARM_VLD1DUPd8wb_register = 1360, + ARM_VLD1DUPq16 = 1361, + ARM_VLD1DUPq16wb_fixed = 1362, + ARM_VLD1DUPq16wb_register = 1363, + ARM_VLD1DUPq32 = 1364, + ARM_VLD1DUPq32wb_fixed = 1365, + ARM_VLD1DUPq32wb_register = 1366, + ARM_VLD1DUPq8 = 1367, + ARM_VLD1DUPq8wb_fixed = 1368, + ARM_VLD1DUPq8wb_register = 1369, + ARM_VLD1LNd16 = 1370, + ARM_VLD1LNd16_UPD = 1371, + ARM_VLD1LNd32 = 1372, + ARM_VLD1LNd32_UPD = 1373, + ARM_VLD1LNd8 = 1374, + ARM_VLD1LNd8_UPD = 1375, + ARM_VLD1d16 = 1382, + ARM_VLD1d16Q = 1383, + ARM_VLD1d16Qwb_fixed = 1385, + ARM_VLD1d16Qwb_register = 1386, + ARM_VLD1d16T = 1387, + ARM_VLD1d16Twb_fixed = 1389, + ARM_VLD1d16Twb_register = 1390, + ARM_VLD1d16wb_fixed = 1391, + ARM_VLD1d16wb_register = 1392, + ARM_VLD1d32 = 1393, + ARM_VLD1d32Q = 1394, + ARM_VLD1d32Qwb_fixed = 1396, + ARM_VLD1d32Qwb_register = 1397, + ARM_VLD1d32T = 1398, + ARM_VLD1d32Twb_fixed = 1400, + ARM_VLD1d32Twb_register = 1401, + ARM_VLD1d32wb_fixed = 1402, + ARM_VLD1d32wb_register = 1403, + ARM_VLD1d64 = 1404, + ARM_VLD1d64Q = 1405, + ARM_VLD1d64Qwb_fixed = 1409, + ARM_VLD1d64Qwb_register = 1410, + ARM_VLD1d64T = 1411, + ARM_VLD1d64Twb_fixed = 1415, + ARM_VLD1d64Twb_register = 1416, + ARM_VLD1d64wb_fixed = 1417, + ARM_VLD1d64wb_register = 1418, + ARM_VLD1d8 = 1419, + ARM_VLD1d8Q = 1420, + ARM_VLD1d8Qwb_fixed = 1422, + ARM_VLD1d8Qwb_register = 1423, + ARM_VLD1d8T = 1424, + ARM_VLD1d8Twb_fixed = 1426, + ARM_VLD1d8Twb_register = 1427, + ARM_VLD1d8wb_fixed = 1428, + ARM_VLD1d8wb_register = 1429, + ARM_VLD1q16 = 1430, + ARM_VLD1q16wb_fixed = 1435, + ARM_VLD1q16wb_register = 1436, + ARM_VLD1q32 = 1437, + ARM_VLD1q32wb_fixed = 1442, + ARM_VLD1q32wb_register = 1443, + ARM_VLD1q64 = 1444, + ARM_VLD1q64wb_fixed = 1449, + ARM_VLD1q64wb_register = 1450, + ARM_VLD1q8 = 1451, + ARM_VLD1q8wb_fixed = 1456, + ARM_VLD1q8wb_register = 1457, + ARM_VLD2DUPd16 = 1458, + ARM_VLD2DUPd16wb_fixed = 1459, + ARM_VLD2DUPd16wb_register = 1460, + ARM_VLD2DUPd16x2 = 1461, + ARM_VLD2DUPd16x2wb_fixed = 1462, + ARM_VLD2DUPd16x2wb_register = 1463, + ARM_VLD2DUPd32 = 1464, + ARM_VLD2DUPd32wb_fixed = 1465, + ARM_VLD2DUPd32wb_register = 1466, + ARM_VLD2DUPd32x2 = 1467, + ARM_VLD2DUPd32x2wb_fixed = 1468, + ARM_VLD2DUPd32x2wb_register = 1469, + ARM_VLD2DUPd8 = 1470, + ARM_VLD2DUPd8wb_fixed = 1471, + ARM_VLD2DUPd8wb_register = 1472, + ARM_VLD2DUPd8x2 = 1473, + ARM_VLD2DUPd8x2wb_fixed = 1474, + ARM_VLD2DUPd8x2wb_register = 1475, + ARM_VLD2LNd16 = 1482, + ARM_VLD2LNd16_UPD = 1485, + ARM_VLD2LNd32 = 1486, + ARM_VLD2LNd32_UPD = 1489, + ARM_VLD2LNd8 = 1490, + ARM_VLD2LNd8_UPD = 1493, + ARM_VLD2LNq16 = 1494, + ARM_VLD2LNq16_UPD = 1497, + ARM_VLD2LNq32 = 1498, + ARM_VLD2LNq32_UPD = 1501, + ARM_VLD2b16 = 1502, + ARM_VLD2b16wb_fixed = 1503, + ARM_VLD2b16wb_register = 1504, + ARM_VLD2b32 = 1505, + ARM_VLD2b32wb_fixed = 1506, + ARM_VLD2b32wb_register = 1507, + ARM_VLD2b8 = 1508, + ARM_VLD2b8wb_fixed = 1509, + ARM_VLD2b8wb_register = 1510, + ARM_VLD2d16 = 1511, + ARM_VLD2d16wb_fixed = 1512, + ARM_VLD2d16wb_register = 1513, + ARM_VLD2d32 = 1514, + ARM_VLD2d32wb_fixed = 1515, + ARM_VLD2d32wb_register = 1516, + ARM_VLD2d8 = 1517, + ARM_VLD2d8wb_fixed = 1518, + ARM_VLD2d8wb_register = 1519, + ARM_VLD2q16 = 1520, + ARM_VLD2q16wb_fixed = 1524, + ARM_VLD2q16wb_register = 1525, + ARM_VLD2q32 = 1526, + ARM_VLD2q32wb_fixed = 1530, + ARM_VLD2q32wb_register = 1531, + ARM_VLD2q8 = 1532, + ARM_VLD2q8wb_fixed = 1536, + ARM_VLD2q8wb_register = 1537, + ARM_VLD3DUPd16 = 1538, + ARM_VLD3DUPd16_UPD = 1541, + ARM_VLD3DUPd32 = 1542, + ARM_VLD3DUPd32_UPD = 1545, + ARM_VLD3DUPd8 = 1546, + ARM_VLD3DUPd8_UPD = 1549, + ARM_VLD3DUPq16 = 1550, + ARM_VLD3DUPq16_UPD = 1553, + ARM_VLD3DUPq32 = 1554, + ARM_VLD3DUPq32_UPD = 1557, + ARM_VLD3DUPq8 = 1558, + ARM_VLD3DUPq8_UPD = 1561, + ARM_VLD3LNd16 = 1562, + ARM_VLD3LNd16_UPD = 1565, + ARM_VLD3LNd32 = 1566, + ARM_VLD3LNd32_UPD = 1569, + ARM_VLD3LNd8 = 1570, + ARM_VLD3LNd8_UPD = 1573, + ARM_VLD3LNq16 = 1574, + ARM_VLD3LNq16_UPD = 1577, + ARM_VLD3LNq32 = 1578, + ARM_VLD3LNq32_UPD = 1581, + ARM_VLD3d16 = 1582, + ARM_VLD3d16_UPD = 1585, + ARM_VLD3d32 = 1586, + ARM_VLD3d32_UPD = 1589, + ARM_VLD3d8 = 1590, + ARM_VLD3d8_UPD = 1593, + ARM_VLD3q16 = 1594, + ARM_VLD3q16_UPD = 1596, + ARM_VLD3q32 = 1599, + ARM_VLD3q32_UPD = 1601, + ARM_VLD3q8 = 1604, + ARM_VLD3q8_UPD = 1606, + ARM_VLD4DUPd16 = 1609, + ARM_VLD4DUPd16_UPD = 1612, + ARM_VLD4DUPd32 = 1613, + ARM_VLD4DUPd32_UPD = 1616, + ARM_VLD4DUPd8 = 1617, + ARM_VLD4DUPd8_UPD = 1620, + ARM_VLD4DUPq16 = 1621, + ARM_VLD4DUPq16_UPD = 1624, + ARM_VLD4DUPq32 = 1625, + ARM_VLD4DUPq32_UPD = 1628, + ARM_VLD4DUPq8 = 1629, + ARM_VLD4DUPq8_UPD = 1632, + ARM_VLD4LNd16 = 1633, + ARM_VLD4LNd16_UPD = 1636, + ARM_VLD4LNd32 = 1637, + ARM_VLD4LNd32_UPD = 1640, + ARM_VLD4LNd8 = 1641, + ARM_VLD4LNd8_UPD = 1644, + ARM_VLD4LNq16 = 1645, + ARM_VLD4LNq16_UPD = 1648, + ARM_VLD4LNq32 = 1649, + ARM_VLD4LNq32_UPD = 1652, + ARM_VLD4d16 = 1653, + ARM_VLD4d16_UPD = 1656, + ARM_VLD4d32 = 1657, + ARM_VLD4d32_UPD = 1660, + ARM_VLD4d8 = 1661, + ARM_VLD4d8_UPD = 1664, + ARM_VLD4q16 = 1665, + ARM_VLD4q16_UPD = 1667, + ARM_VLD4q32 = 1670, + ARM_VLD4q32_UPD = 1672, + ARM_VLD4q8 = 1675, + ARM_VLD4q8_UPD = 1677, + ARM_VLDMDDB_UPD = 1680, + ARM_VLDMDIA = 1681, + ARM_VLDMDIA_UPD = 1682, + ARM_VLDMQIA = 1683, + ARM_VLDMSDB_UPD = 1684, + ARM_VLDMSIA = 1685, + ARM_VLDMSIA_UPD = 1686, + ARM_VLDRD = 1687, + ARM_VLDRH = 1688, + ARM_VLDRS = 1689, + ARM_VLLDM = 1690, + ARM_VLSTM = 1691, + ARM_VMAXNMD = 1692, + ARM_VMAXNMH = 1693, + ARM_VMAXNMNDf = 1694, + ARM_VMAXNMNDh = 1695, + ARM_VMAXNMNQf = 1696, + ARM_VMAXNMNQh = 1697, + ARM_VMAXNMS = 1698, + ARM_VMAXfd = 1699, + ARM_VMAXfq = 1700, + ARM_VMAXhd = 1701, + ARM_VMAXhq = 1702, + ARM_VMAXsv16i8 = 1703, + ARM_VMAXsv2i32 = 1704, + ARM_VMAXsv4i16 = 1705, + ARM_VMAXsv4i32 = 1706, + ARM_VMAXsv8i16 = 1707, + ARM_VMAXsv8i8 = 1708, + ARM_VMAXuv16i8 = 1709, + ARM_VMAXuv2i32 = 1710, + ARM_VMAXuv4i16 = 1711, + ARM_VMAXuv4i32 = 1712, + ARM_VMAXuv8i16 = 1713, + ARM_VMAXuv8i8 = 1714, + ARM_VMINNMD = 1715, + ARM_VMINNMH = 1716, + ARM_VMINNMNDf = 1717, + ARM_VMINNMNDh = 1718, + ARM_VMINNMNQf = 1719, + ARM_VMINNMNQh = 1720, + ARM_VMINNMS = 1721, + ARM_VMINfd = 1722, + ARM_VMINfq = 1723, + ARM_VMINhd = 1724, + ARM_VMINhq = 1725, + ARM_VMINsv16i8 = 1726, + ARM_VMINsv2i32 = 1727, + ARM_VMINsv4i16 = 1728, + ARM_VMINsv4i32 = 1729, + ARM_VMINsv8i16 = 1730, + ARM_VMINsv8i8 = 1731, + ARM_VMINuv16i8 = 1732, + ARM_VMINuv2i32 = 1733, + ARM_VMINuv4i16 = 1734, + ARM_VMINuv4i32 = 1735, + ARM_VMINuv8i16 = 1736, + ARM_VMINuv8i8 = 1737, + ARM_VMLAD = 1738, + ARM_VMLAH = 1739, + ARM_VMLALslsv2i32 = 1740, + ARM_VMLALslsv4i16 = 1741, + ARM_VMLALsluv2i32 = 1742, + ARM_VMLALsluv4i16 = 1743, + ARM_VMLALsv2i64 = 1744, + ARM_VMLALsv4i32 = 1745, + ARM_VMLALsv8i16 = 1746, + ARM_VMLALuv2i64 = 1747, + ARM_VMLALuv4i32 = 1748, + ARM_VMLALuv8i16 = 1749, + ARM_VMLAS = 1750, + ARM_VMLAfd = 1751, + ARM_VMLAfq = 1752, + ARM_VMLAhd = 1753, + ARM_VMLAhq = 1754, + ARM_VMLAslfd = 1755, + ARM_VMLAslfq = 1756, + ARM_VMLAslhd = 1757, + ARM_VMLAslhq = 1758, + ARM_VMLAslv2i32 = 1759, + ARM_VMLAslv4i16 = 1760, + ARM_VMLAslv4i32 = 1761, + ARM_VMLAslv8i16 = 1762, + ARM_VMLAv16i8 = 1763, + ARM_VMLAv2i32 = 1764, + ARM_VMLAv4i16 = 1765, + ARM_VMLAv4i32 = 1766, + ARM_VMLAv8i16 = 1767, + ARM_VMLAv8i8 = 1768, + ARM_VMLSD = 1769, + ARM_VMLSH = 1770, + ARM_VMLSLslsv2i32 = 1771, + ARM_VMLSLslsv4i16 = 1772, + ARM_VMLSLsluv2i32 = 1773, + ARM_VMLSLsluv4i16 = 1774, + ARM_VMLSLsv2i64 = 1775, + ARM_VMLSLsv4i32 = 1776, + ARM_VMLSLsv8i16 = 1777, + ARM_VMLSLuv2i64 = 1778, + ARM_VMLSLuv4i32 = 1779, + ARM_VMLSLuv8i16 = 1780, + ARM_VMLSS = 1781, + ARM_VMLSfd = 1782, + ARM_VMLSfq = 1783, + ARM_VMLShd = 1784, + ARM_VMLShq = 1785, + ARM_VMLSslfd = 1786, + ARM_VMLSslfq = 1787, + ARM_VMLSslhd = 1788, + ARM_VMLSslhq = 1789, + ARM_VMLSslv2i32 = 1790, + ARM_VMLSslv4i16 = 1791, + ARM_VMLSslv4i32 = 1792, + ARM_VMLSslv8i16 = 1793, + ARM_VMLSv16i8 = 1794, + ARM_VMLSv2i32 = 1795, + ARM_VMLSv4i16 = 1796, + ARM_VMLSv4i32 = 1797, + ARM_VMLSv8i16 = 1798, + ARM_VMLSv8i8 = 1799, + ARM_VMOVD = 1800, + ARM_VMOVDRR = 1801, + ARM_VMOVH = 1802, + ARM_VMOVHR = 1803, + ARM_VMOVLsv2i64 = 1804, + ARM_VMOVLsv4i32 = 1805, + ARM_VMOVLsv8i16 = 1806, + ARM_VMOVLuv2i64 = 1807, + ARM_VMOVLuv4i32 = 1808, + ARM_VMOVLuv8i16 = 1809, + ARM_VMOVNv2i32 = 1810, + ARM_VMOVNv4i16 = 1811, + ARM_VMOVNv8i8 = 1812, + ARM_VMOVRH = 1813, + ARM_VMOVRRD = 1814, + ARM_VMOVRRS = 1815, + ARM_VMOVRS = 1816, + ARM_VMOVS = 1817, + ARM_VMOVSR = 1818, + ARM_VMOVSRR = 1819, + ARM_VMOVv16i8 = 1820, + ARM_VMOVv1i64 = 1821, + ARM_VMOVv2f32 = 1822, + ARM_VMOVv2i32 = 1823, + ARM_VMOVv2i64 = 1824, + ARM_VMOVv4f32 = 1825, + ARM_VMOVv4i16 = 1826, + ARM_VMOVv4i32 = 1827, + ARM_VMOVv8i16 = 1828, + ARM_VMOVv8i8 = 1829, + ARM_VMRS = 1830, + ARM_VMRS_FPEXC = 1831, + ARM_VMRS_FPINST = 1832, + ARM_VMRS_FPINST2 = 1833, + ARM_VMRS_FPSID = 1834, + ARM_VMRS_MVFR0 = 1835, + ARM_VMRS_MVFR1 = 1836, + ARM_VMRS_MVFR2 = 1837, + ARM_VMSR = 1838, + ARM_VMSR_FPEXC = 1839, + ARM_VMSR_FPINST = 1840, + ARM_VMSR_FPINST2 = 1841, + ARM_VMSR_FPSID = 1842, + ARM_VMULD = 1843, + ARM_VMULH = 1844, + ARM_VMULLp64 = 1845, + ARM_VMULLp8 = 1846, + ARM_VMULLslsv2i32 = 1847, + ARM_VMULLslsv4i16 = 1848, + ARM_VMULLsluv2i32 = 1849, + ARM_VMULLsluv4i16 = 1850, + ARM_VMULLsv2i64 = 1851, + ARM_VMULLsv4i32 = 1852, + ARM_VMULLsv8i16 = 1853, + ARM_VMULLuv2i64 = 1854, + ARM_VMULLuv4i32 = 1855, + ARM_VMULLuv8i16 = 1856, + ARM_VMULS = 1857, + ARM_VMULfd = 1858, + ARM_VMULfq = 1859, + ARM_VMULhd = 1860, + ARM_VMULhq = 1861, + ARM_VMULpd = 1862, + ARM_VMULpq = 1863, + ARM_VMULslfd = 1864, + ARM_VMULslfq = 1865, + ARM_VMULslhd = 1866, + ARM_VMULslhq = 1867, + ARM_VMULslv2i32 = 1868, + ARM_VMULslv4i16 = 1869, + ARM_VMULslv4i32 = 1870, + ARM_VMULslv8i16 = 1871, + ARM_VMULv16i8 = 1872, + ARM_VMULv2i32 = 1873, + ARM_VMULv4i16 = 1874, + ARM_VMULv4i32 = 1875, + ARM_VMULv8i16 = 1876, + ARM_VMULv8i8 = 1877, + ARM_VMVNd = 1878, + ARM_VMVNq = 1879, + ARM_VMVNv2i32 = 1880, + ARM_VMVNv4i16 = 1881, + ARM_VMVNv4i32 = 1882, + ARM_VMVNv8i16 = 1883, + ARM_VNEGD = 1884, + ARM_VNEGH = 1885, + ARM_VNEGS = 1886, + ARM_VNEGf32q = 1887, + ARM_VNEGfd = 1888, + ARM_VNEGhd = 1889, + ARM_VNEGhq = 1890, + ARM_VNEGs16d = 1891, + ARM_VNEGs16q = 1892, + ARM_VNEGs32d = 1893, + ARM_VNEGs32q = 1894, + ARM_VNEGs8d = 1895, + ARM_VNEGs8q = 1896, + ARM_VNMLAD = 1897, + ARM_VNMLAH = 1898, + ARM_VNMLAS = 1899, + ARM_VNMLSD = 1900, + ARM_VNMLSH = 1901, + ARM_VNMLSS = 1902, + ARM_VNMULD = 1903, + ARM_VNMULH = 1904, + ARM_VNMULS = 1905, + ARM_VORNd = 1906, + ARM_VORNq = 1907, + ARM_VORRd = 1908, + ARM_VORRiv2i32 = 1909, + ARM_VORRiv4i16 = 1910, + ARM_VORRiv4i32 = 1911, + ARM_VORRiv8i16 = 1912, + ARM_VORRq = 1913, + ARM_VPADALsv16i8 = 1914, + ARM_VPADALsv2i32 = 1915, + ARM_VPADALsv4i16 = 1916, + ARM_VPADALsv4i32 = 1917, + ARM_VPADALsv8i16 = 1918, + ARM_VPADALsv8i8 = 1919, + ARM_VPADALuv16i8 = 1920, + ARM_VPADALuv2i32 = 1921, + ARM_VPADALuv4i16 = 1922, + ARM_VPADALuv4i32 = 1923, + ARM_VPADALuv8i16 = 1924, + ARM_VPADALuv8i8 = 1925, + ARM_VPADDLsv16i8 = 1926, + ARM_VPADDLsv2i32 = 1927, + ARM_VPADDLsv4i16 = 1928, + ARM_VPADDLsv4i32 = 1929, + ARM_VPADDLsv8i16 = 1930, + ARM_VPADDLsv8i8 = 1931, + ARM_VPADDLuv16i8 = 1932, + ARM_VPADDLuv2i32 = 1933, + ARM_VPADDLuv4i16 = 1934, + ARM_VPADDLuv4i32 = 1935, + ARM_VPADDLuv8i16 = 1936, + ARM_VPADDLuv8i8 = 1937, + ARM_VPADDf = 1938, + ARM_VPADDh = 1939, + ARM_VPADDi16 = 1940, + ARM_VPADDi32 = 1941, + ARM_VPADDi8 = 1942, + ARM_VPMAXf = 1943, + ARM_VPMAXh = 1944, + ARM_VPMAXs16 = 1945, + ARM_VPMAXs32 = 1946, + ARM_VPMAXs8 = 1947, + ARM_VPMAXu16 = 1948, + ARM_VPMAXu32 = 1949, + ARM_VPMAXu8 = 1950, + ARM_VPMINf = 1951, + ARM_VPMINh = 1952, + ARM_VPMINs16 = 1953, + ARM_VPMINs32 = 1954, + ARM_VPMINs8 = 1955, + ARM_VPMINu16 = 1956, + ARM_VPMINu32 = 1957, + ARM_VPMINu8 = 1958, + ARM_VQABSv16i8 = 1959, + ARM_VQABSv2i32 = 1960, + ARM_VQABSv4i16 = 1961, + ARM_VQABSv4i32 = 1962, + ARM_VQABSv8i16 = 1963, + ARM_VQABSv8i8 = 1964, + ARM_VQADDsv16i8 = 1965, + ARM_VQADDsv1i64 = 1966, + ARM_VQADDsv2i32 = 1967, + ARM_VQADDsv2i64 = 1968, + ARM_VQADDsv4i16 = 1969, + ARM_VQADDsv4i32 = 1970, + ARM_VQADDsv8i16 = 1971, + ARM_VQADDsv8i8 = 1972, + ARM_VQADDuv16i8 = 1973, + ARM_VQADDuv1i64 = 1974, + ARM_VQADDuv2i32 = 1975, + ARM_VQADDuv2i64 = 1976, + ARM_VQADDuv4i16 = 1977, + ARM_VQADDuv4i32 = 1978, + ARM_VQADDuv8i16 = 1979, + ARM_VQADDuv8i8 = 1980, + ARM_VQDMLALslv2i32 = 1981, + ARM_VQDMLALslv4i16 = 1982, + ARM_VQDMLALv2i64 = 1983, + ARM_VQDMLALv4i32 = 1984, + ARM_VQDMLSLslv2i32 = 1985, + ARM_VQDMLSLslv4i16 = 1986, + ARM_VQDMLSLv2i64 = 1987, + ARM_VQDMLSLv4i32 = 1988, + ARM_VQDMULHslv2i32 = 1989, + ARM_VQDMULHslv4i16 = 1990, + ARM_VQDMULHslv4i32 = 1991, + ARM_VQDMULHslv8i16 = 1992, + ARM_VQDMULHv2i32 = 1993, + ARM_VQDMULHv4i16 = 1994, + ARM_VQDMULHv4i32 = 1995, + ARM_VQDMULHv8i16 = 1996, + ARM_VQDMULLslv2i32 = 1997, + ARM_VQDMULLslv4i16 = 1998, + ARM_VQDMULLv2i64 = 1999, + ARM_VQDMULLv4i32 = 2000, + ARM_VQMOVNsuv2i32 = 2001, + ARM_VQMOVNsuv4i16 = 2002, + ARM_VQMOVNsuv8i8 = 2003, + ARM_VQMOVNsv2i32 = 2004, + ARM_VQMOVNsv4i16 = 2005, + ARM_VQMOVNsv8i8 = 2006, + ARM_VQMOVNuv2i32 = 2007, + ARM_VQMOVNuv4i16 = 2008, + ARM_VQMOVNuv8i8 = 2009, + ARM_VQNEGv16i8 = 2010, + ARM_VQNEGv2i32 = 2011, + ARM_VQNEGv4i16 = 2012, + ARM_VQNEGv4i32 = 2013, + ARM_VQNEGv8i16 = 2014, + ARM_VQNEGv8i8 = 2015, + ARM_VQRDMLAHslv2i32 = 2016, + ARM_VQRDMLAHslv4i16 = 2017, + ARM_VQRDMLAHslv4i32 = 2018, + ARM_VQRDMLAHslv8i16 = 2019, + ARM_VQRDMLAHv2i32 = 2020, + ARM_VQRDMLAHv4i16 = 2021, + ARM_VQRDMLAHv4i32 = 2022, + ARM_VQRDMLAHv8i16 = 2023, + ARM_VQRDMLSHslv2i32 = 2024, + ARM_VQRDMLSHslv4i16 = 2025, + ARM_VQRDMLSHslv4i32 = 2026, + ARM_VQRDMLSHslv8i16 = 2027, + ARM_VQRDMLSHv2i32 = 2028, + ARM_VQRDMLSHv4i16 = 2029, + ARM_VQRDMLSHv4i32 = 2030, + ARM_VQRDMLSHv8i16 = 2031, + ARM_VQRDMULHslv2i32 = 2032, + ARM_VQRDMULHslv4i16 = 2033, + ARM_VQRDMULHslv4i32 = 2034, + ARM_VQRDMULHslv8i16 = 2035, + ARM_VQRDMULHv2i32 = 2036, + ARM_VQRDMULHv4i16 = 2037, + ARM_VQRDMULHv4i32 = 2038, + ARM_VQRDMULHv8i16 = 2039, + ARM_VQRSHLsv16i8 = 2040, + ARM_VQRSHLsv1i64 = 2041, + ARM_VQRSHLsv2i32 = 2042, + ARM_VQRSHLsv2i64 = 2043, + ARM_VQRSHLsv4i16 = 2044, + ARM_VQRSHLsv4i32 = 2045, + ARM_VQRSHLsv8i16 = 2046, + ARM_VQRSHLsv8i8 = 2047, + ARM_VQRSHLuv16i8 = 2048, + ARM_VQRSHLuv1i64 = 2049, + ARM_VQRSHLuv2i32 = 2050, + ARM_VQRSHLuv2i64 = 2051, + ARM_VQRSHLuv4i16 = 2052, + ARM_VQRSHLuv4i32 = 2053, + ARM_VQRSHLuv8i16 = 2054, + ARM_VQRSHLuv8i8 = 2055, + ARM_VQRSHRNsv2i32 = 2056, + ARM_VQRSHRNsv4i16 = 2057, + ARM_VQRSHRNsv8i8 = 2058, + ARM_VQRSHRNuv2i32 = 2059, + ARM_VQRSHRNuv4i16 = 2060, + ARM_VQRSHRNuv8i8 = 2061, + ARM_VQRSHRUNv2i32 = 2062, + ARM_VQRSHRUNv4i16 = 2063, + ARM_VQRSHRUNv8i8 = 2064, + ARM_VQSHLsiv16i8 = 2065, + ARM_VQSHLsiv1i64 = 2066, + ARM_VQSHLsiv2i32 = 2067, + ARM_VQSHLsiv2i64 = 2068, + ARM_VQSHLsiv4i16 = 2069, + ARM_VQSHLsiv4i32 = 2070, + ARM_VQSHLsiv8i16 = 2071, + ARM_VQSHLsiv8i8 = 2072, + ARM_VQSHLsuv16i8 = 2073, + ARM_VQSHLsuv1i64 = 2074, + ARM_VQSHLsuv2i32 = 2075, + ARM_VQSHLsuv2i64 = 2076, + ARM_VQSHLsuv4i16 = 2077, + ARM_VQSHLsuv4i32 = 2078, + ARM_VQSHLsuv8i16 = 2079, + ARM_VQSHLsuv8i8 = 2080, + ARM_VQSHLsv16i8 = 2081, + ARM_VQSHLsv1i64 = 2082, + ARM_VQSHLsv2i32 = 2083, + ARM_VQSHLsv2i64 = 2084, + ARM_VQSHLsv4i16 = 2085, + ARM_VQSHLsv4i32 = 2086, + ARM_VQSHLsv8i16 = 2087, + ARM_VQSHLsv8i8 = 2088, + ARM_VQSHLuiv16i8 = 2089, + ARM_VQSHLuiv1i64 = 2090, + ARM_VQSHLuiv2i32 = 2091, + ARM_VQSHLuiv2i64 = 2092, + ARM_VQSHLuiv4i16 = 2093, + ARM_VQSHLuiv4i32 = 2094, + ARM_VQSHLuiv8i16 = 2095, + ARM_VQSHLuiv8i8 = 2096, + ARM_VQSHLuv16i8 = 2097, + ARM_VQSHLuv1i64 = 2098, + ARM_VQSHLuv2i32 = 2099, + ARM_VQSHLuv2i64 = 2100, + ARM_VQSHLuv4i16 = 2101, + ARM_VQSHLuv4i32 = 2102, + ARM_VQSHLuv8i16 = 2103, + ARM_VQSHLuv8i8 = 2104, + ARM_VQSHRNsv2i32 = 2105, + ARM_VQSHRNsv4i16 = 2106, + ARM_VQSHRNsv8i8 = 2107, + ARM_VQSHRNuv2i32 = 2108, + ARM_VQSHRNuv4i16 = 2109, + ARM_VQSHRNuv8i8 = 2110, + ARM_VQSHRUNv2i32 = 2111, + ARM_VQSHRUNv4i16 = 2112, + ARM_VQSHRUNv8i8 = 2113, + ARM_VQSUBsv16i8 = 2114, + ARM_VQSUBsv1i64 = 2115, + ARM_VQSUBsv2i32 = 2116, + ARM_VQSUBsv2i64 = 2117, + ARM_VQSUBsv4i16 = 2118, + ARM_VQSUBsv4i32 = 2119, + ARM_VQSUBsv8i16 = 2120, + ARM_VQSUBsv8i8 = 2121, + ARM_VQSUBuv16i8 = 2122, + ARM_VQSUBuv1i64 = 2123, + ARM_VQSUBuv2i32 = 2124, + ARM_VQSUBuv2i64 = 2125, + ARM_VQSUBuv4i16 = 2126, + ARM_VQSUBuv4i32 = 2127, + ARM_VQSUBuv8i16 = 2128, + ARM_VQSUBuv8i8 = 2129, + ARM_VRADDHNv2i32 = 2130, + ARM_VRADDHNv4i16 = 2131, + ARM_VRADDHNv8i8 = 2132, + ARM_VRECPEd = 2133, + ARM_VRECPEfd = 2134, + ARM_VRECPEfq = 2135, + ARM_VRECPEhd = 2136, + ARM_VRECPEhq = 2137, + ARM_VRECPEq = 2138, + ARM_VRECPSfd = 2139, + ARM_VRECPSfq = 2140, + ARM_VRECPShd = 2141, + ARM_VRECPShq = 2142, + ARM_VREV16d8 = 2143, + ARM_VREV16q8 = 2144, + ARM_VREV32d16 = 2145, + ARM_VREV32d8 = 2146, + ARM_VREV32q16 = 2147, + ARM_VREV32q8 = 2148, + ARM_VREV64d16 = 2149, + ARM_VREV64d32 = 2150, + ARM_VREV64d8 = 2151, + ARM_VREV64q16 = 2152, + ARM_VREV64q32 = 2153, + ARM_VREV64q8 = 2154, + ARM_VRHADDsv16i8 = 2155, + ARM_VRHADDsv2i32 = 2156, + ARM_VRHADDsv4i16 = 2157, + ARM_VRHADDsv4i32 = 2158, + ARM_VRHADDsv8i16 = 2159, + ARM_VRHADDsv8i8 = 2160, + ARM_VRHADDuv16i8 = 2161, + ARM_VRHADDuv2i32 = 2162, + ARM_VRHADDuv4i16 = 2163, + ARM_VRHADDuv4i32 = 2164, + ARM_VRHADDuv8i16 = 2165, + ARM_VRHADDuv8i8 = 2166, + ARM_VRINTAD = 2167, + ARM_VRINTAH = 2168, + ARM_VRINTANDf = 2169, + ARM_VRINTANDh = 2170, + ARM_VRINTANQf = 2171, + ARM_VRINTANQh = 2172, + ARM_VRINTAS = 2173, + ARM_VRINTMD = 2174, + ARM_VRINTMH = 2175, + ARM_VRINTMNDf = 2176, + ARM_VRINTMNDh = 2177, + ARM_VRINTMNQf = 2178, + ARM_VRINTMNQh = 2179, + ARM_VRINTMS = 2180, + ARM_VRINTND = 2181, + ARM_VRINTNH = 2182, + ARM_VRINTNNDf = 2183, + ARM_VRINTNNDh = 2184, + ARM_VRINTNNQf = 2185, + ARM_VRINTNNQh = 2186, + ARM_VRINTNS = 2187, + ARM_VRINTPD = 2188, + ARM_VRINTPH = 2189, + ARM_VRINTPNDf = 2190, + ARM_VRINTPNDh = 2191, + ARM_VRINTPNQf = 2192, + ARM_VRINTPNQh = 2193, + ARM_VRINTPS = 2194, + ARM_VRINTRD = 2195, + ARM_VRINTRH = 2196, + ARM_VRINTRS = 2197, + ARM_VRINTXD = 2198, + ARM_VRINTXH = 2199, + ARM_VRINTXNDf = 2200, + ARM_VRINTXNDh = 2201, + ARM_VRINTXNQf = 2202, + ARM_VRINTXNQh = 2203, + ARM_VRINTXS = 2204, + ARM_VRINTZD = 2205, + ARM_VRINTZH = 2206, + ARM_VRINTZNDf = 2207, + ARM_VRINTZNDh = 2208, + ARM_VRINTZNQf = 2209, + ARM_VRINTZNQh = 2210, + ARM_VRINTZS = 2211, + ARM_VRSHLsv16i8 = 2212, + ARM_VRSHLsv1i64 = 2213, + ARM_VRSHLsv2i32 = 2214, + ARM_VRSHLsv2i64 = 2215, + ARM_VRSHLsv4i16 = 2216, + ARM_VRSHLsv4i32 = 2217, + ARM_VRSHLsv8i16 = 2218, + ARM_VRSHLsv8i8 = 2219, + ARM_VRSHLuv16i8 = 2220, + ARM_VRSHLuv1i64 = 2221, + ARM_VRSHLuv2i32 = 2222, + ARM_VRSHLuv2i64 = 2223, + ARM_VRSHLuv4i16 = 2224, + ARM_VRSHLuv4i32 = 2225, + ARM_VRSHLuv8i16 = 2226, + ARM_VRSHLuv8i8 = 2227, + ARM_VRSHRNv2i32 = 2228, + ARM_VRSHRNv4i16 = 2229, + ARM_VRSHRNv8i8 = 2230, + ARM_VRSHRsv16i8 = 2231, + ARM_VRSHRsv1i64 = 2232, + ARM_VRSHRsv2i32 = 2233, + ARM_VRSHRsv2i64 = 2234, + ARM_VRSHRsv4i16 = 2235, + ARM_VRSHRsv4i32 = 2236, + ARM_VRSHRsv8i16 = 2237, + ARM_VRSHRsv8i8 = 2238, + ARM_VRSHRuv16i8 = 2239, + ARM_VRSHRuv1i64 = 2240, + ARM_VRSHRuv2i32 = 2241, + ARM_VRSHRuv2i64 = 2242, + ARM_VRSHRuv4i16 = 2243, + ARM_VRSHRuv4i32 = 2244, + ARM_VRSHRuv8i16 = 2245, + ARM_VRSHRuv8i8 = 2246, + ARM_VRSQRTEd = 2247, + ARM_VRSQRTEfd = 2248, + ARM_VRSQRTEfq = 2249, + ARM_VRSQRTEhd = 2250, + ARM_VRSQRTEhq = 2251, + ARM_VRSQRTEq = 2252, + ARM_VRSQRTSfd = 2253, + ARM_VRSQRTSfq = 2254, + ARM_VRSQRTShd = 2255, + ARM_VRSQRTShq = 2256, + ARM_VRSRAsv16i8 = 2257, + ARM_VRSRAsv1i64 = 2258, + ARM_VRSRAsv2i32 = 2259, + ARM_VRSRAsv2i64 = 2260, + ARM_VRSRAsv4i16 = 2261, + ARM_VRSRAsv4i32 = 2262, + ARM_VRSRAsv8i16 = 2263, + ARM_VRSRAsv8i8 = 2264, + ARM_VRSRAuv16i8 = 2265, + ARM_VRSRAuv1i64 = 2266, + ARM_VRSRAuv2i32 = 2267, + ARM_VRSRAuv2i64 = 2268, + ARM_VRSRAuv4i16 = 2269, + ARM_VRSRAuv4i32 = 2270, + ARM_VRSRAuv8i16 = 2271, + ARM_VRSRAuv8i8 = 2272, + ARM_VRSUBHNv2i32 = 2273, + ARM_VRSUBHNv4i16 = 2274, + ARM_VRSUBHNv8i8 = 2275, + ARM_VSDOTD = 2276, + ARM_VSDOTDI = 2277, + ARM_VSDOTQ = 2278, + ARM_VSDOTQI = 2279, + ARM_VSELEQD = 2280, + ARM_VSELEQH = 2281, + ARM_VSELEQS = 2282, + ARM_VSELGED = 2283, + ARM_VSELGEH = 2284, + ARM_VSELGES = 2285, + ARM_VSELGTD = 2286, + ARM_VSELGTH = 2287, + ARM_VSELGTS = 2288, + ARM_VSELVSD = 2289, + ARM_VSELVSH = 2290, + ARM_VSELVSS = 2291, + ARM_VSETLNi16 = 2292, + ARM_VSETLNi32 = 2293, + ARM_VSETLNi8 = 2294, + ARM_VSHLLi16 = 2295, + ARM_VSHLLi32 = 2296, + ARM_VSHLLi8 = 2297, + ARM_VSHLLsv2i64 = 2298, + ARM_VSHLLsv4i32 = 2299, + ARM_VSHLLsv8i16 = 2300, + ARM_VSHLLuv2i64 = 2301, + ARM_VSHLLuv4i32 = 2302, + ARM_VSHLLuv8i16 = 2303, + ARM_VSHLiv16i8 = 2304, + ARM_VSHLiv1i64 = 2305, + ARM_VSHLiv2i32 = 2306, + ARM_VSHLiv2i64 = 2307, + ARM_VSHLiv4i16 = 2308, + ARM_VSHLiv4i32 = 2309, + ARM_VSHLiv8i16 = 2310, + ARM_VSHLiv8i8 = 2311, + ARM_VSHLsv16i8 = 2312, + ARM_VSHLsv1i64 = 2313, + ARM_VSHLsv2i32 = 2314, + ARM_VSHLsv2i64 = 2315, + ARM_VSHLsv4i16 = 2316, + ARM_VSHLsv4i32 = 2317, + ARM_VSHLsv8i16 = 2318, + ARM_VSHLsv8i8 = 2319, + ARM_VSHLuv16i8 = 2320, + ARM_VSHLuv1i64 = 2321, + ARM_VSHLuv2i32 = 2322, + ARM_VSHLuv2i64 = 2323, + ARM_VSHLuv4i16 = 2324, + ARM_VSHLuv4i32 = 2325, + ARM_VSHLuv8i16 = 2326, + ARM_VSHLuv8i8 = 2327, + ARM_VSHRNv2i32 = 2328, + ARM_VSHRNv4i16 = 2329, + ARM_VSHRNv8i8 = 2330, + ARM_VSHRsv16i8 = 2331, + ARM_VSHRsv1i64 = 2332, + ARM_VSHRsv2i32 = 2333, + ARM_VSHRsv2i64 = 2334, + ARM_VSHRsv4i16 = 2335, + ARM_VSHRsv4i32 = 2336, + ARM_VSHRsv8i16 = 2337, + ARM_VSHRsv8i8 = 2338, + ARM_VSHRuv16i8 = 2339, + ARM_VSHRuv1i64 = 2340, + ARM_VSHRuv2i32 = 2341, + ARM_VSHRuv2i64 = 2342, + ARM_VSHRuv4i16 = 2343, + ARM_VSHRuv4i32 = 2344, + ARM_VSHRuv8i16 = 2345, + ARM_VSHRuv8i8 = 2346, + ARM_VSHTOD = 2347, + ARM_VSHTOH = 2348, + ARM_VSHTOS = 2349, + ARM_VSITOD = 2350, + ARM_VSITOH = 2351, + ARM_VSITOS = 2352, + ARM_VSLIv16i8 = 2353, + ARM_VSLIv1i64 = 2354, + ARM_VSLIv2i32 = 2355, + ARM_VSLIv2i64 = 2356, + ARM_VSLIv4i16 = 2357, + ARM_VSLIv4i32 = 2358, + ARM_VSLIv8i16 = 2359, + ARM_VSLIv8i8 = 2360, + ARM_VSLTOD = 2361, + ARM_VSLTOH = 2362, + ARM_VSLTOS = 2363, + ARM_VSQRTD = 2364, + ARM_VSQRTH = 2365, + ARM_VSQRTS = 2366, + ARM_VSRAsv16i8 = 2367, + ARM_VSRAsv1i64 = 2368, + ARM_VSRAsv2i32 = 2369, + ARM_VSRAsv2i64 = 2370, + ARM_VSRAsv4i16 = 2371, + ARM_VSRAsv4i32 = 2372, + ARM_VSRAsv8i16 = 2373, + ARM_VSRAsv8i8 = 2374, + ARM_VSRAuv16i8 = 2375, + ARM_VSRAuv1i64 = 2376, + ARM_VSRAuv2i32 = 2377, + ARM_VSRAuv2i64 = 2378, + ARM_VSRAuv4i16 = 2379, + ARM_VSRAuv4i32 = 2380, + ARM_VSRAuv8i16 = 2381, + ARM_VSRAuv8i8 = 2382, + ARM_VSRIv16i8 = 2383, + ARM_VSRIv1i64 = 2384, + ARM_VSRIv2i32 = 2385, + ARM_VSRIv2i64 = 2386, + ARM_VSRIv4i16 = 2387, + ARM_VSRIv4i32 = 2388, + ARM_VSRIv8i16 = 2389, + ARM_VSRIv8i8 = 2390, + ARM_VST1LNd16 = 2391, + ARM_VST1LNd16_UPD = 2392, + ARM_VST1LNd32 = 2393, + ARM_VST1LNd32_UPD = 2394, + ARM_VST1LNd8 = 2395, + ARM_VST1LNd8_UPD = 2396, + ARM_VST1d16 = 2403, + ARM_VST1d16Q = 2404, + ARM_VST1d16Qwb_fixed = 2406, + ARM_VST1d16Qwb_register = 2407, + ARM_VST1d16T = 2408, + ARM_VST1d16Twb_fixed = 2410, + ARM_VST1d16Twb_register = 2411, + ARM_VST1d16wb_fixed = 2412, + ARM_VST1d16wb_register = 2413, + ARM_VST1d32 = 2414, + ARM_VST1d32Q = 2415, + ARM_VST1d32Qwb_fixed = 2417, + ARM_VST1d32Qwb_register = 2418, + ARM_VST1d32T = 2419, + ARM_VST1d32Twb_fixed = 2421, + ARM_VST1d32Twb_register = 2422, + ARM_VST1d32wb_fixed = 2423, + ARM_VST1d32wb_register = 2424, + ARM_VST1d64 = 2425, + ARM_VST1d64Q = 2426, + ARM_VST1d64Qwb_fixed = 2430, + ARM_VST1d64Qwb_register = 2431, + ARM_VST1d64T = 2432, + ARM_VST1d64Twb_fixed = 2436, + ARM_VST1d64Twb_register = 2437, + ARM_VST1d64wb_fixed = 2438, + ARM_VST1d64wb_register = 2439, + ARM_VST1d8 = 2440, + ARM_VST1d8Q = 2441, + ARM_VST1d8Qwb_fixed = 2443, + ARM_VST1d8Qwb_register = 2444, + ARM_VST1d8T = 2445, + ARM_VST1d8Twb_fixed = 2447, + ARM_VST1d8Twb_register = 2448, + ARM_VST1d8wb_fixed = 2449, + ARM_VST1d8wb_register = 2450, + ARM_VST1q16 = 2451, + ARM_VST1q16wb_fixed = 2456, + ARM_VST1q16wb_register = 2457, + ARM_VST1q32 = 2458, + ARM_VST1q32wb_fixed = 2463, + ARM_VST1q32wb_register = 2464, + ARM_VST1q64 = 2465, + ARM_VST1q64wb_fixed = 2470, + ARM_VST1q64wb_register = 2471, + ARM_VST1q8 = 2472, + ARM_VST1q8wb_fixed = 2477, + ARM_VST1q8wb_register = 2478, + ARM_VST2LNd16 = 2479, + ARM_VST2LNd16_UPD = 2482, + ARM_VST2LNd32 = 2483, + ARM_VST2LNd32_UPD = 2486, + ARM_VST2LNd8 = 2487, + ARM_VST2LNd8_UPD = 2490, + ARM_VST2LNq16 = 2491, + ARM_VST2LNq16_UPD = 2494, + ARM_VST2LNq32 = 2495, + ARM_VST2LNq32_UPD = 2498, + ARM_VST2b16 = 2499, + ARM_VST2b16wb_fixed = 2500, + ARM_VST2b16wb_register = 2501, + ARM_VST2b32 = 2502, + ARM_VST2b32wb_fixed = 2503, + ARM_VST2b32wb_register = 2504, + ARM_VST2b8 = 2505, + ARM_VST2b8wb_fixed = 2506, + ARM_VST2b8wb_register = 2507, + ARM_VST2d16 = 2508, + ARM_VST2d16wb_fixed = 2509, + ARM_VST2d16wb_register = 2510, + ARM_VST2d32 = 2511, + ARM_VST2d32wb_fixed = 2512, + ARM_VST2d32wb_register = 2513, + ARM_VST2d8 = 2514, + ARM_VST2d8wb_fixed = 2515, + ARM_VST2d8wb_register = 2516, + ARM_VST2q16 = 2517, + ARM_VST2q16wb_fixed = 2521, + ARM_VST2q16wb_register = 2522, + ARM_VST2q32 = 2523, + ARM_VST2q32wb_fixed = 2527, + ARM_VST2q32wb_register = 2528, + ARM_VST2q8 = 2529, + ARM_VST2q8wb_fixed = 2533, + ARM_VST2q8wb_register = 2534, + ARM_VST3LNd16 = 2535, + ARM_VST3LNd16_UPD = 2538, + ARM_VST3LNd32 = 2539, + ARM_VST3LNd32_UPD = 2542, + ARM_VST3LNd8 = 2543, + ARM_VST3LNd8_UPD = 2546, + ARM_VST3LNq16 = 2547, + ARM_VST3LNq16_UPD = 2550, + ARM_VST3LNq32 = 2551, + ARM_VST3LNq32_UPD = 2554, + ARM_VST3d16 = 2555, + ARM_VST3d16_UPD = 2558, + ARM_VST3d32 = 2559, + ARM_VST3d32_UPD = 2562, + ARM_VST3d8 = 2563, + ARM_VST3d8_UPD = 2566, + ARM_VST3q16 = 2567, + ARM_VST3q16_UPD = 2569, + ARM_VST3q32 = 2572, + ARM_VST3q32_UPD = 2574, + ARM_VST3q8 = 2577, + ARM_VST3q8_UPD = 2579, + ARM_VST4LNd16 = 2582, + ARM_VST4LNd16_UPD = 2585, + ARM_VST4LNd32 = 2586, + ARM_VST4LNd32_UPD = 2589, + ARM_VST4LNd8 = 2590, + ARM_VST4LNd8_UPD = 2593, + ARM_VST4LNq16 = 2594, + ARM_VST4LNq16_UPD = 2597, + ARM_VST4LNq32 = 2598, + ARM_VST4LNq32_UPD = 2601, + ARM_VST4d16 = 2602, + ARM_VST4d16_UPD = 2605, + ARM_VST4d32 = 2606, + ARM_VST4d32_UPD = 2609, + ARM_VST4d8 = 2610, + ARM_VST4d8_UPD = 2613, + ARM_VST4q16 = 2614, + ARM_VST4q16_UPD = 2616, + ARM_VST4q32 = 2619, + ARM_VST4q32_UPD = 2621, + ARM_VST4q8 = 2624, + ARM_VST4q8_UPD = 2626, + ARM_VSTMDDB_UPD = 2629, + ARM_VSTMDIA = 2630, + ARM_VSTMDIA_UPD = 2631, + ARM_VSTMQIA = 2632, + ARM_VSTMSDB_UPD = 2633, + ARM_VSTMSIA = 2634, + ARM_VSTMSIA_UPD = 2635, + ARM_VSTRD = 2636, + ARM_VSTRH = 2637, + ARM_VSTRS = 2638, + ARM_VSUBD = 2639, + ARM_VSUBH = 2640, + ARM_VSUBHNv2i32 = 2641, + ARM_VSUBHNv4i16 = 2642, + ARM_VSUBHNv8i8 = 2643, + ARM_VSUBLsv2i64 = 2644, + ARM_VSUBLsv4i32 = 2645, + ARM_VSUBLsv8i16 = 2646, + ARM_VSUBLuv2i64 = 2647, + ARM_VSUBLuv4i32 = 2648, + ARM_VSUBLuv8i16 = 2649, + ARM_VSUBS = 2650, + ARM_VSUBWsv2i64 = 2651, + ARM_VSUBWsv4i32 = 2652, + ARM_VSUBWsv8i16 = 2653, + ARM_VSUBWuv2i64 = 2654, + ARM_VSUBWuv4i32 = 2655, + ARM_VSUBWuv8i16 = 2656, + ARM_VSUBfd = 2657, + ARM_VSUBfq = 2658, + ARM_VSUBhd = 2659, + ARM_VSUBhq = 2660, + ARM_VSUBv16i8 = 2661, + ARM_VSUBv1i64 = 2662, + ARM_VSUBv2i32 = 2663, + ARM_VSUBv2i64 = 2664, + ARM_VSUBv4i16 = 2665, + ARM_VSUBv4i32 = 2666, + ARM_VSUBv8i16 = 2667, + ARM_VSUBv8i8 = 2668, + ARM_VSWPd = 2669, + ARM_VSWPq = 2670, + ARM_VTBL1 = 2671, + ARM_VTBL2 = 2672, + ARM_VTBL3 = 2673, + ARM_VTBL4 = 2675, + ARM_VTBX1 = 2677, + ARM_VTBX2 = 2678, + ARM_VTBX3 = 2679, + ARM_VTBX4 = 2681, + ARM_VTOSHD = 2683, + ARM_VTOSHH = 2684, + ARM_VTOSHS = 2685, + ARM_VTOSIRD = 2686, + ARM_VTOSIRH = 2687, + ARM_VTOSIRS = 2688, + ARM_VTOSIZD = 2689, + ARM_VTOSIZH = 2690, + ARM_VTOSIZS = 2691, + ARM_VTOSLD = 2692, + ARM_VTOSLH = 2693, + ARM_VTOSLS = 2694, + ARM_VTOUHD = 2695, + ARM_VTOUHH = 2696, + ARM_VTOUHS = 2697, + ARM_VTOUIRD = 2698, + ARM_VTOUIRH = 2699, + ARM_VTOUIRS = 2700, + ARM_VTOUIZD = 2701, + ARM_VTOUIZH = 2702, + ARM_VTOUIZS = 2703, + ARM_VTOULD = 2704, + ARM_VTOULH = 2705, + ARM_VTOULS = 2706, + ARM_VTRNd16 = 2707, + ARM_VTRNd32 = 2708, + ARM_VTRNd8 = 2709, + ARM_VTRNq16 = 2710, + ARM_VTRNq32 = 2711, + ARM_VTRNq8 = 2712, + ARM_VTSTv16i8 = 2713, + ARM_VTSTv2i32 = 2714, + ARM_VTSTv4i16 = 2715, + ARM_VTSTv4i32 = 2716, + ARM_VTSTv8i16 = 2717, + ARM_VTSTv8i8 = 2718, + ARM_VUDOTD = 2719, + ARM_VUDOTDI = 2720, + ARM_VUDOTQ = 2721, + ARM_VUDOTQI = 2722, + ARM_VUHTOD = 2723, + ARM_VUHTOH = 2724, + ARM_VUHTOS = 2725, + ARM_VUITOD = 2726, + ARM_VUITOH = 2727, + ARM_VUITOS = 2728, + ARM_VULTOD = 2729, + ARM_VULTOH = 2730, + ARM_VULTOS = 2731, + ARM_VUZPd16 = 2732, + ARM_VUZPd8 = 2733, + ARM_VUZPq16 = 2734, + ARM_VUZPq32 = 2735, + ARM_VUZPq8 = 2736, + ARM_VZIPd16 = 2737, + ARM_VZIPd8 = 2738, + ARM_VZIPq16 = 2739, + ARM_VZIPq32 = 2740, + ARM_VZIPq8 = 2741, + ARM_sysLDMDA = 2742, + ARM_sysLDMDA_UPD = 2743, + ARM_sysLDMDB = 2744, + ARM_sysLDMDB_UPD = 2745, + ARM_sysLDMIA = 2746, + ARM_sysLDMIA_UPD = 2747, + ARM_sysLDMIB = 2748, + ARM_sysLDMIB_UPD = 2749, + ARM_sysSTMDA = 2750, + ARM_sysSTMDA_UPD = 2751, + ARM_sysSTMDB = 2752, + ARM_sysSTMDB_UPD = 2753, + ARM_sysSTMIA = 2754, + ARM_sysSTMIA_UPD = 2755, + ARM_sysSTMIB = 2756, + ARM_sysSTMIB_UPD = 2757, + ARM_t2ADCri = 2758, + ARM_t2ADCrr = 2759, + ARM_t2ADCrs = 2760, + ARM_t2ADDri = 2761, + ARM_t2ADDri12 = 2762, + ARM_t2ADDrr = 2763, + ARM_t2ADDrs = 2764, + ARM_t2ADR = 2765, + ARM_t2ANDri = 2766, + ARM_t2ANDrr = 2767, + ARM_t2ANDrs = 2768, + ARM_t2ASRri = 2769, + ARM_t2ASRrr = 2770, + ARM_t2B = 2771, + ARM_t2BFC = 2772, + ARM_t2BFI = 2773, + ARM_t2BICri = 2774, + ARM_t2BICrr = 2775, + ARM_t2BICrs = 2776, + ARM_t2BXJ = 2777, + ARM_t2Bcc = 2778, + ARM_t2CDP = 2779, + ARM_t2CDP2 = 2780, + ARM_t2CLREX = 2781, + ARM_t2CLZ = 2782, + ARM_t2CMNri = 2783, + ARM_t2CMNzrr = 2784, + ARM_t2CMNzrs = 2785, + ARM_t2CMPri = 2786, + ARM_t2CMPrr = 2787, + ARM_t2CMPrs = 2788, + ARM_t2CPS1p = 2789, + ARM_t2CPS2p = 2790, + ARM_t2CPS3p = 2791, + ARM_t2CRC32B = 2792, + ARM_t2CRC32CB = 2793, + ARM_t2CRC32CH = 2794, + ARM_t2CRC32CW = 2795, + ARM_t2CRC32H = 2796, + ARM_t2CRC32W = 2797, + ARM_t2DBG = 2798, + ARM_t2DCPS1 = 2799, + ARM_t2DCPS2 = 2800, + ARM_t2DCPS3 = 2801, + ARM_t2DMB = 2802, + ARM_t2DSB = 2803, + ARM_t2EORri = 2804, + ARM_t2EORrr = 2805, + ARM_t2EORrs = 2806, + ARM_t2HINT = 2807, + ARM_t2HVC = 2808, + ARM_t2ISB = 2809, + ARM_t2IT = 2810, + ARM_t2LDA = 2813, + ARM_t2LDAB = 2814, + ARM_t2LDAEX = 2815, + ARM_t2LDAEXB = 2816, + ARM_t2LDAEXD = 2817, + ARM_t2LDAEXH = 2818, + ARM_t2LDAH = 2819, + ARM_t2LDC2L_OFFSET = 2820, + ARM_t2LDC2L_OPTION = 2821, + ARM_t2LDC2L_POST = 2822, + ARM_t2LDC2L_PRE = 2823, + ARM_t2LDC2_OFFSET = 2824, + ARM_t2LDC2_OPTION = 2825, + ARM_t2LDC2_POST = 2826, + ARM_t2LDC2_PRE = 2827, + ARM_t2LDCL_OFFSET = 2828, + ARM_t2LDCL_OPTION = 2829, + ARM_t2LDCL_POST = 2830, + ARM_t2LDCL_PRE = 2831, + ARM_t2LDC_OFFSET = 2832, + ARM_t2LDC_OPTION = 2833, + ARM_t2LDC_POST = 2834, + ARM_t2LDC_PRE = 2835, + ARM_t2LDMDB = 2836, + ARM_t2LDMDB_UPD = 2837, + ARM_t2LDMIA = 2838, + ARM_t2LDMIA_UPD = 2839, + ARM_t2LDRBT = 2840, + ARM_t2LDRB_POST = 2841, + ARM_t2LDRB_PRE = 2842, + ARM_t2LDRBi12 = 2843, + ARM_t2LDRBi8 = 2844, + ARM_t2LDRBpci = 2845, + ARM_t2LDRBs = 2846, + ARM_t2LDRD_POST = 2847, + ARM_t2LDRD_PRE = 2848, + ARM_t2LDRDi8 = 2849, + ARM_t2LDREX = 2850, + ARM_t2LDREXB = 2851, + ARM_t2LDREXD = 2852, + ARM_t2LDREXH = 2853, + ARM_t2LDRHT = 2854, + ARM_t2LDRH_POST = 2855, + ARM_t2LDRH_PRE = 2856, + ARM_t2LDRHi12 = 2857, + ARM_t2LDRHi8 = 2858, + ARM_t2LDRHpci = 2859, + ARM_t2LDRHs = 2860, + ARM_t2LDRSBT = 2861, + ARM_t2LDRSB_POST = 2862, + ARM_t2LDRSB_PRE = 2863, + ARM_t2LDRSBi12 = 2864, + ARM_t2LDRSBi8 = 2865, + ARM_t2LDRSBpci = 2866, + ARM_t2LDRSBs = 2867, + ARM_t2LDRSHT = 2868, + ARM_t2LDRSH_POST = 2869, + ARM_t2LDRSH_PRE = 2870, + ARM_t2LDRSHi12 = 2871, + ARM_t2LDRSHi8 = 2872, + ARM_t2LDRSHpci = 2873, + ARM_t2LDRSHs = 2874, + ARM_t2LDRT = 2875, + ARM_t2LDR_POST = 2876, + ARM_t2LDR_PRE = 2877, + ARM_t2LDRi12 = 2878, + ARM_t2LDRi8 = 2879, + ARM_t2LDRpci = 2880, + ARM_t2LDRs = 2881, + ARM_t2LSLri = 2882, + ARM_t2LSLrr = 2883, + ARM_t2LSRri = 2884, + ARM_t2LSRrr = 2885, + ARM_t2MCR = 2886, + ARM_t2MCR2 = 2887, + ARM_t2MCRR = 2888, + ARM_t2MCRR2 = 2889, + ARM_t2MLA = 2890, + ARM_t2MLS = 2891, + ARM_t2MOVTi16 = 2892, + ARM_t2MOVi = 2893, + ARM_t2MOVi16 = 2894, + ARM_t2MOVr = 2895, + ARM_t2MOVsra_flag = 2896, + ARM_t2MOVsrl_flag = 2897, + ARM_t2MRC = 2898, + ARM_t2MRC2 = 2899, + ARM_t2MRRC = 2900, + ARM_t2MRRC2 = 2901, + ARM_t2MRS_AR = 2902, + ARM_t2MRS_M = 2903, + ARM_t2MRSbanked = 2904, + ARM_t2MRSsys_AR = 2905, + ARM_t2MSR_AR = 2906, + ARM_t2MSR_M = 2907, + ARM_t2MSRbanked = 2908, + ARM_t2MUL = 2909, + ARM_t2MVNi = 2910, + ARM_t2MVNr = 2911, + ARM_t2MVNs = 2912, + ARM_t2ORNri = 2913, + ARM_t2ORNrr = 2914, + ARM_t2ORNrs = 2915, + ARM_t2ORRri = 2916, + ARM_t2ORRrr = 2917, + ARM_t2ORRrs = 2918, + ARM_t2PKHBT = 2919, + ARM_t2PKHTB = 2920, + ARM_t2PLDWi12 = 2921, + ARM_t2PLDWi8 = 2922, + ARM_t2PLDWs = 2923, + ARM_t2PLDi12 = 2924, + ARM_t2PLDi8 = 2925, + ARM_t2PLDpci = 2926, + ARM_t2PLDs = 2927, + ARM_t2PLIi12 = 2928, + ARM_t2PLIi8 = 2929, + ARM_t2PLIpci = 2930, + ARM_t2PLIs = 2931, + ARM_t2QADD = 2932, + ARM_t2QADD16 = 2933, + ARM_t2QADD8 = 2934, + ARM_t2QASX = 2935, + ARM_t2QDADD = 2936, + ARM_t2QDSUB = 2937, + ARM_t2QSAX = 2938, + ARM_t2QSUB = 2939, + ARM_t2QSUB16 = 2940, + ARM_t2QSUB8 = 2941, + ARM_t2RBIT = 2942, + ARM_t2REV = 2943, + ARM_t2REV16 = 2944, + ARM_t2REVSH = 2945, + ARM_t2RFEDB = 2946, + ARM_t2RFEDBW = 2947, + ARM_t2RFEIA = 2948, + ARM_t2RFEIAW = 2949, + ARM_t2RORri = 2950, + ARM_t2RORrr = 2951, + ARM_t2RRX = 2952, + ARM_t2RSBri = 2953, + ARM_t2RSBrr = 2954, + ARM_t2RSBrs = 2955, + ARM_t2SADD16 = 2956, + ARM_t2SADD8 = 2957, + ARM_t2SASX = 2958, + ARM_t2SBCri = 2959, + ARM_t2SBCrr = 2960, + ARM_t2SBCrs = 2961, + ARM_t2SBFX = 2962, + ARM_t2SDIV = 2963, + ARM_t2SEL = 2964, + ARM_t2SETPAN = 2965, + ARM_t2SG = 2966, + ARM_t2SHADD16 = 2967, + ARM_t2SHADD8 = 2968, + ARM_t2SHASX = 2969, + ARM_t2SHSAX = 2970, + ARM_t2SHSUB16 = 2971, + ARM_t2SHSUB8 = 2972, + ARM_t2SMC = 2973, + ARM_t2SMLABB = 2974, + ARM_t2SMLABT = 2975, + ARM_t2SMLAD = 2976, + ARM_t2SMLADX = 2977, + ARM_t2SMLAL = 2978, + ARM_t2SMLALBB = 2979, + ARM_t2SMLALBT = 2980, + ARM_t2SMLALD = 2981, + ARM_t2SMLALDX = 2982, + ARM_t2SMLALTB = 2983, + ARM_t2SMLALTT = 2984, + ARM_t2SMLATB = 2985, + ARM_t2SMLATT = 2986, + ARM_t2SMLAWB = 2987, + ARM_t2SMLAWT = 2988, + ARM_t2SMLSD = 2989, + ARM_t2SMLSDX = 2990, + ARM_t2SMLSLD = 2991, + ARM_t2SMLSLDX = 2992, + ARM_t2SMMLA = 2993, + ARM_t2SMMLAR = 2994, + ARM_t2SMMLS = 2995, + ARM_t2SMMLSR = 2996, + ARM_t2SMMUL = 2997, + ARM_t2SMMULR = 2998, + ARM_t2SMUAD = 2999, + ARM_t2SMUADX = 3000, + ARM_t2SMULBB = 3001, + ARM_t2SMULBT = 3002, + ARM_t2SMULL = 3003, + ARM_t2SMULTB = 3004, + ARM_t2SMULTT = 3005, + ARM_t2SMULWB = 3006, + ARM_t2SMULWT = 3007, + ARM_t2SMUSD = 3008, + ARM_t2SMUSDX = 3009, + ARM_t2SRSDB = 3010, + ARM_t2SRSDB_UPD = 3011, + ARM_t2SRSIA = 3012, + ARM_t2SRSIA_UPD = 3013, + ARM_t2SSAT = 3014, + ARM_t2SSAT16 = 3015, + ARM_t2SSAX = 3016, + ARM_t2SSUB16 = 3017, + ARM_t2SSUB8 = 3018, + ARM_t2STC2L_OFFSET = 3019, + ARM_t2STC2L_OPTION = 3020, + ARM_t2STC2L_POST = 3021, + ARM_t2STC2L_PRE = 3022, + ARM_t2STC2_OFFSET = 3023, + ARM_t2STC2_OPTION = 3024, + ARM_t2STC2_POST = 3025, + ARM_t2STC2_PRE = 3026, + ARM_t2STCL_OFFSET = 3027, + ARM_t2STCL_OPTION = 3028, + ARM_t2STCL_POST = 3029, + ARM_t2STCL_PRE = 3030, + ARM_t2STC_OFFSET = 3031, + ARM_t2STC_OPTION = 3032, + ARM_t2STC_POST = 3033, + ARM_t2STC_PRE = 3034, + ARM_t2STL = 3035, + ARM_t2STLB = 3036, + ARM_t2STLEX = 3037, + ARM_t2STLEXB = 3038, + ARM_t2STLEXD = 3039, + ARM_t2STLEXH = 3040, + ARM_t2STLH = 3041, + ARM_t2STMDB = 3042, + ARM_t2STMDB_UPD = 3043, + ARM_t2STMIA = 3044, + ARM_t2STMIA_UPD = 3045, + ARM_t2STRBT = 3046, + ARM_t2STRB_POST = 3047, + ARM_t2STRB_PRE = 3048, + ARM_t2STRBi12 = 3049, + ARM_t2STRBi8 = 3050, + ARM_t2STRBs = 3051, + ARM_t2STRD_POST = 3052, + ARM_t2STRD_PRE = 3053, + ARM_t2STRDi8 = 3054, + ARM_t2STREX = 3055, + ARM_t2STREXB = 3056, + ARM_t2STREXD = 3057, + ARM_t2STREXH = 3058, + ARM_t2STRHT = 3059, + ARM_t2STRH_POST = 3060, + ARM_t2STRH_PRE = 3061, + ARM_t2STRHi12 = 3062, + ARM_t2STRHi8 = 3063, + ARM_t2STRHs = 3064, + ARM_t2STRT = 3065, + ARM_t2STR_POST = 3066, + ARM_t2STR_PRE = 3067, + ARM_t2STRi12 = 3068, + ARM_t2STRi8 = 3069, + ARM_t2STRs = 3070, + ARM_t2SUBS_PC_LR = 3071, + ARM_t2SUBri = 3072, + ARM_t2SUBri12 = 3073, + ARM_t2SUBrr = 3074, + ARM_t2SUBrs = 3075, + ARM_t2SXTAB = 3076, + ARM_t2SXTAB16 = 3077, + ARM_t2SXTAH = 3078, + ARM_t2SXTB = 3079, + ARM_t2SXTB16 = 3080, + ARM_t2SXTH = 3081, + ARM_t2TBB = 3082, + ARM_t2TBH = 3083, + ARM_t2TEQri = 3084, + ARM_t2TEQrr = 3085, + ARM_t2TEQrs = 3086, + ARM_t2TSB = 3087, + ARM_t2TSTri = 3088, + ARM_t2TSTrr = 3089, + ARM_t2TSTrs = 3090, + ARM_t2TT = 3091, + ARM_t2TTA = 3092, + ARM_t2TTAT = 3093, + ARM_t2TTT = 3094, + ARM_t2UADD16 = 3095, + ARM_t2UADD8 = 3096, + ARM_t2UASX = 3097, + ARM_t2UBFX = 3098, + ARM_t2UDF = 3099, + ARM_t2UDIV = 3100, + ARM_t2UHADD16 = 3101, + ARM_t2UHADD8 = 3102, + ARM_t2UHASX = 3103, + ARM_t2UHSAX = 3104, + ARM_t2UHSUB16 = 3105, + ARM_t2UHSUB8 = 3106, + ARM_t2UMAAL = 3107, + ARM_t2UMLAL = 3108, + ARM_t2UMULL = 3109, + ARM_t2UQADD16 = 3110, + ARM_t2UQADD8 = 3111, + ARM_t2UQASX = 3112, + ARM_t2UQSAX = 3113, + ARM_t2UQSUB16 = 3114, + ARM_t2UQSUB8 = 3115, + ARM_t2USAD8 = 3116, + ARM_t2USADA8 = 3117, + ARM_t2USAT = 3118, + ARM_t2USAT16 = 3119, + ARM_t2USAX = 3120, + ARM_t2USUB16 = 3121, + ARM_t2USUB8 = 3122, + ARM_t2UXTAB = 3123, + ARM_t2UXTAB16 = 3124, + ARM_t2UXTAH = 3125, + ARM_t2UXTB = 3126, + ARM_t2UXTB16 = 3127, + ARM_t2UXTH = 3128, + ARM_tADC = 3129, + ARM_tADDhirr = 3130, + ARM_tADDi3 = 3131, + ARM_tADDi8 = 3132, + ARM_tADDrSP = 3133, + ARM_tADDrSPi = 3134, + ARM_tADDrr = 3135, + ARM_tADDspi = 3136, + ARM_tADDspr = 3137, + ARM_tADR = 3138, + ARM_tAND = 3139, + ARM_tASRri = 3140, + ARM_tASRrr = 3141, + ARM_tB = 3142, + ARM_tBIC = 3143, + ARM_tBKPT = 3144, + ARM_tBL = 3145, + ARM_tBLXNSr = 3146, + ARM_tBLXi = 3147, + ARM_tBLXr = 3148, + ARM_tBX = 3149, + ARM_tBXNS = 3150, + ARM_tBcc = 3151, + ARM_tCBNZ = 3152, + ARM_tCBZ = 3153, + ARM_tCMNz = 3154, + ARM_tCMPhir = 3155, + ARM_tCMPi8 = 3156, + ARM_tCMPr = 3157, + ARM_tCPS = 3158, + ARM_tEOR = 3159, + ARM_tHINT = 3160, + ARM_tHLT = 3161, + ARM_tLDMIA = 3165, + ARM_tLDRBi = 3166, + ARM_tLDRBr = 3167, + ARM_tLDRHi = 3168, + ARM_tLDRHr = 3169, + ARM_tLDRSB = 3170, + ARM_tLDRSH = 3171, + ARM_tLDRi = 3172, + ARM_tLDRpci = 3173, + ARM_tLDRr = 3174, + ARM_tLDRspi = 3175, + ARM_tLSLri = 3176, + ARM_tLSLrr = 3177, + ARM_tLSRri = 3178, + ARM_tLSRrr = 3179, + ARM_tMOVSr = 3180, + ARM_tMOVi8 = 3181, + ARM_tMOVr = 3182, + ARM_tMUL = 3183, + ARM_tMVN = 3184, + ARM_tORR = 3185, + ARM_tPICADD = 3186, + ARM_tPOP = 3187, + ARM_tPUSH = 3188, + ARM_tREV = 3189, + ARM_tREV16 = 3190, + ARM_tREVSH = 3191, + ARM_tROR = 3192, + ARM_tRSB = 3193, + ARM_tSBC = 3194, + ARM_tSETEND = 3195, + ARM_tSTMIA_UPD = 3196, + ARM_tSTRBi = 3197, + ARM_tSTRBr = 3198, + ARM_tSTRHi = 3199, + ARM_tSTRHr = 3200, + ARM_tSTRi = 3201, + ARM_tSTRr = 3202, + ARM_tSTRspi = 3203, + ARM_tSUBi3 = 3204, + ARM_tSUBi8 = 3205, + ARM_tSUBrr = 3206, + ARM_tSUBspi = 3207, + ARM_tSVC = 3208, + ARM_tSXTB = 3209, + ARM_tSXTH = 3210, + ARM_tTRAP = 3211, + ARM_tTST = 3212, + ARM_tUDF = 3213, + ARM_tUXTB = 3214, + ARM_tUXTH = 3215, + ARM_t__brkdiv0 = 3216, + ARM_INSTRUCTION_LIST_END = 3217 }; #endif // GET_INSTRINFO_ENUM @@ -2990,3643 +2991,4269 @@ enum { #define nullptr 0 -static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<, 2013-2019 */ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +/*===- TableGen'erated file -------------------------------------*- C++ +-*-===*|* *| |* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ - enum { ARM_ARMv2 = 0, ARM_ARMv2a = 1, @@ -159,4 +159,3 @@ enum { ARM_ProcSwift = 145, ARM_XScale = 146, }; - diff --git a/arch/ARM/ARMGenSystemRegister.inc b/arch/ARM/ARMGenSystemRegister.inc index 4c5ce124d8..ad65a24f0f 100644 --- a/arch/ARM/ARMGenSystemRegister.inc +++ b/arch/ARM/ARMGenSystemRegister.inc @@ -2,167 +2,217 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +/*===- TableGen'erated file -------------------------------------*- C++ +-*-===*|* *| |* GenSystemRegister Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ - enum BankedRegValues { - elr_hyp = 0, - lr_abt = 1, - lr_fiq = 2, - lr_irq = 3, - lr_mon = 4, - lr_svc = 5, - lr_und = 6, - lr_usr = 7, - r10_fiq = 8, - r10_usr = 9, - r11_fiq = 10, - r11_usr = 11, - r12_fiq = 12, - r12_usr = 13, - r8_fiq = 14, - r8_usr = 15, - r9_fiq = 16, - r9_usr = 17, - sp_abt = 18, - sp_fiq = 19, - sp_hyp = 20, - sp_irq = 21, - sp_mon = 22, - sp_svc = 23, - sp_und = 24, - sp_usr = 25, - spsr_abt = 26, - spsr_fiq = 27, - spsr_hyp = 28, - spsr_irq = 29, - spsr_mon = 30, - spsr_svc = 31, - spsr_und = 32, + elr_hyp = 0, + lr_abt = 1, + lr_fiq = 2, + lr_irq = 3, + lr_mon = 4, + lr_svc = 5, + lr_und = 6, + lr_usr = 7, + r10_fiq = 8, + r10_usr = 9, + r11_fiq = 10, + r11_usr = 11, + r12_fiq = 12, + r12_usr = 13, + r8_fiq = 14, + r8_usr = 15, + r9_fiq = 16, + r9_usr = 17, + sp_abt = 18, + sp_fiq = 19, + sp_hyp = 20, + sp_irq = 21, + sp_mon = 22, + sp_svc = 23, + sp_und = 24, + sp_usr = 25, + spsr_abt = 26, + spsr_fiq = 27, + spsr_hyp = 28, + spsr_irq = 29, + spsr_mon = 30, + spsr_svc = 31, + spsr_und = 32, }; static const MClassSysReg MClassSysRegsList[] = { - { "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400, {ARM_FeatureDSP} }, // 0 - { "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00, {ARM_FeatureDSP} }, // 1 - { "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401, {ARM_FeatureDSP} }, // 2 - { "iapsr_nzcvqg", ARM_SYSREG_IAPSR_NZCVQG, 0xC01, 0x301, 0xC01, {ARM_FeatureDSP} }, // 3 - { "eapsr_g", ARM_SYSREG_EAPSR_G, 0x402, 0x2, 0x402, {ARM_FeatureDSP} }, // 4 - { "eapsr_nzcvqg", ARM_SYSREG_EAPSR_NZCVQG, 0xC02, 0x302, 0xC02, {ARM_FeatureDSP} }, // 5 - { "xpsr_g", ARM_SYSREG_XPSR_G, 0x403, 0x3, 0x403, {ARM_FeatureDSP} }, // 6 - { "xpsr_nzcvqg", ARM_SYSREG_XPSR_NZCVQG, 0xC03, 0x303, 0xC03, {ARM_FeatureDSP} }, // 7 - { "apsr", ARM_SYSREG_APSR, 0x800, 0x100, 0x800, { 0 } }, // 8 - { "apsr_nzcvq", ARM_SYSREG_APSR_NZCVQ, 0x1800, 0x200, 0x800, { 0 } }, // 9 - { "iapsr", ARM_SYSREG_IAPSR, 0x801, 0x101, 0x801, { 0 } }, // 10 - { "iapsr_nzcvq", ARM_SYSREG_IAPSR_NZCVQ, 0x1801, 0x201, 0x801, { 0 } }, // 11 - { "eapsr", ARM_SYSREG_EAPSR, 0x802, 0x102, 0x802, { 0 } }, // 12 - { "eapsr_nzcvq", ARM_SYSREG_EAPSR_NZCVQ, 0x1802, 0x202, 0x802, { 0 } }, // 13 - { "xpsr", ARM_SYSREG_XPSR, 0x803, 0x103, 0x803, { 0 } }, // 14 - { "xpsr_nzcvq", ARM_SYSREG_XPSR_NZCVQ, 0x1803, 0x203, 0x803, { 0 } }, // 15 - { "ipsr", ARM_SYSREG_IPSR, 0x805, 0x105, 0x805, { 0 } }, // 16 - { "epsr", ARM_SYSREG_EPSR, 0x806, 0x106, 0x806, { 0 } }, // 17 - { "iepsr", ARM_SYSREG_IEPSR, 0x807, 0x107, 0x807, { 0 } }, // 18 - { "msp", ARM_SYSREG_MSP, 0x808, 0x108, 0x808, { 0 } }, // 19 - { "psp", ARM_SYSREG_PSP, 0x809, 0x109, 0x809, { 0 } }, // 20 - { "msplim", ARM_SYSREG_MSPLIM, 0x80A, 0x10A, 0x80A, {ARM_HasV8MBaselineOps} }, // 21 - { "psplim", ARM_SYSREG_PSPLIM, 0x80B, 0x10B, 0x80B, {ARM_HasV8MBaselineOps} }, // 22 - { "primask", ARM_SYSREG_PRIMASK, 0x810, 0x110, 0x810, { 0 } }, // 23 - { "basepri", ARM_SYSREG_BASEPRI, 0x811, 0x111, 0x811, {ARM_HasV7Ops} }, // 24 - { "basepri_max", ARM_SYSREG_BASEPRI_MAX, 0x812, 0x112, 0x812, {ARM_HasV7Ops} }, // 25 - { "faultmask", ARM_SYSREG_FAULTMASK, 0x813, 0x113, 0x813, {ARM_HasV7Ops} }, // 26 - { "control", ARM_SYSREG_CONTROL, 0x814, 0x114, 0x814, { 0 } }, // 27 - { "msp_ns", ARM_SYSREG_MSP_NS, 0x888, 0x188, 0x888, {ARM_Feature8MSecExt} }, // 28 - { "psp_ns", ARM_SYSREG_PSP_NS, 0x889, 0x189, 0x889, {ARM_Feature8MSecExt} }, // 29 - { "msplim_ns", ARM_SYSREG_MSPLIM_NS, 0x88A, 0x18A, 0x88A, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 30 - { "psplim_ns", ARM_SYSREG_PSPLIM_NS, 0x88B, 0x18B, 0x88B, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 31 - { "primask_ns", ARM_SYSREG_PRIMASK_NS, 0x890, 0x190, 0x890, { 0 } }, // 32 - { "basepri_ns", ARM_SYSREG_BASEPRI_NS, 0x891, 0x191, 0x891, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 33 - { "faultmask_ns", ARM_SYSREG_FAULTMASK_NS, 0x893, 0x193, 0x893, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 34 - { "control_ns", ARM_SYSREG_CONTROL_NS, 0x894, 0x194, 0x894, {ARM_Feature8MSecExt} }, // 35 - { "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898, {ARM_Feature8MSecExt} }, // 36 + {"apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400, {ARM_FeatureDSP}}, // 0 + {"apsr_nzcvqg", + ARM_SYSREG_APSR_NZCVQG, + 0xC00, + 0x300, + 0xC00, + {ARM_FeatureDSP}}, // 1 + {"iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401, {ARM_FeatureDSP}}, // 2 + {"iapsr_nzcvqg", + ARM_SYSREG_IAPSR_NZCVQG, + 0xC01, + 0x301, + 0xC01, + {ARM_FeatureDSP}}, // 3 + {"eapsr_g", ARM_SYSREG_EAPSR_G, 0x402, 0x2, 0x402, {ARM_FeatureDSP}}, // 4 + {"eapsr_nzcvqg", + ARM_SYSREG_EAPSR_NZCVQG, + 0xC02, + 0x302, + 0xC02, + {ARM_FeatureDSP}}, // 5 + {"xpsr_g", ARM_SYSREG_XPSR_G, 0x403, 0x3, 0x403, {ARM_FeatureDSP}}, // 6 + {"xpsr_nzcvqg", + ARM_SYSREG_XPSR_NZCVQG, + 0xC03, + 0x303, + 0xC03, + {ARM_FeatureDSP}}, // 7 + {"apsr", ARM_SYSREG_APSR, 0x800, 0x100, 0x800, {0}}, // 8 + {"apsr_nzcvq", ARM_SYSREG_APSR_NZCVQ, 0x1800, 0x200, 0x800, {0}}, // 9 + {"iapsr", ARM_SYSREG_IAPSR, 0x801, 0x101, 0x801, {0}}, // 10 + {"iapsr_nzcvq", ARM_SYSREG_IAPSR_NZCVQ, 0x1801, 0x201, 0x801, {0}}, // 11 + {"eapsr", ARM_SYSREG_EAPSR, 0x802, 0x102, 0x802, {0}}, // 12 + {"eapsr_nzcvq", ARM_SYSREG_EAPSR_NZCVQ, 0x1802, 0x202, 0x802, {0}}, // 13 + {"xpsr", ARM_SYSREG_XPSR, 0x803, 0x103, 0x803, {0}}, // 14 + {"xpsr_nzcvq", ARM_SYSREG_XPSR_NZCVQ, 0x1803, 0x203, 0x803, {0}}, // 15 + {"ipsr", ARM_SYSREG_IPSR, 0x805, 0x105, 0x805, {0}}, // 16 + {"epsr", ARM_SYSREG_EPSR, 0x806, 0x106, 0x806, {0}}, // 17 + {"iepsr", ARM_SYSREG_IEPSR, 0x807, 0x107, 0x807, {0}}, // 18 + {"msp", ARM_SYSREG_MSP, 0x808, 0x108, 0x808, {0}}, // 19 + {"psp", ARM_SYSREG_PSP, 0x809, 0x109, 0x809, {0}}, // 20 + {"msplim", + ARM_SYSREG_MSPLIM, + 0x80A, + 0x10A, + 0x80A, + {ARM_HasV8MBaselineOps}}, // 21 + {"psplim", + ARM_SYSREG_PSPLIM, + 0x80B, + 0x10B, + 0x80B, + {ARM_HasV8MBaselineOps}}, // 22 + {"primask", ARM_SYSREG_PRIMASK, 0x810, 0x110, 0x810, {0}}, // 23 + {"basepri", ARM_SYSREG_BASEPRI, 0x811, 0x111, 0x811, {ARM_HasV7Ops}}, // 24 + {"basepri_max", + ARM_SYSREG_BASEPRI_MAX, + 0x812, + 0x112, + 0x812, + {ARM_HasV7Ops}}, // 25 + {"faultmask", + ARM_SYSREG_FAULTMASK, + 0x813, + 0x113, + 0x813, + {ARM_HasV7Ops}}, // 26 + {"control", ARM_SYSREG_CONTROL, 0x814, 0x114, 0x814, {0}}, // 27 + {"msp_ns", + ARM_SYSREG_MSP_NS, + 0x888, + 0x188, + 0x888, + {ARM_Feature8MSecExt}}, // 28 + {"psp_ns", + ARM_SYSREG_PSP_NS, + 0x889, + 0x189, + 0x889, + {ARM_Feature8MSecExt}}, // 29 + {"msplim_ns", + ARM_SYSREG_MSPLIM_NS, + 0x88A, + 0x18A, + 0x88A, + {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}}, // 30 + {"psplim_ns", + ARM_SYSREG_PSPLIM_NS, + 0x88B, + 0x18B, + 0x88B, + {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}}, // 31 + {"primask_ns", ARM_SYSREG_PRIMASK_NS, 0x890, 0x190, 0x890, {0}}, // 32 + {"basepri_ns", + ARM_SYSREG_BASEPRI_NS, + 0x891, + 0x191, + 0x891, + {ARM_Feature8MSecExt, ARM_HasV7Ops}}, // 33 + {"faultmask_ns", + ARM_SYSREG_FAULTMASK_NS, + 0x893, + 0x193, + 0x893, + {ARM_Feature8MSecExt, ARM_HasV7Ops}}, // 34 + {"control_ns", + ARM_SYSREG_CONTROL_NS, + 0x894, + 0x194, + 0x894, + {ARM_Feature8MSecExt}}, // 35 + {"sp_ns", + ARM_SYSREG_SP_NS, + 0x898, + 0x198, + 0x898, + {ARM_Feature8MSecExt}}, // 36 }; static const BankedReg BankedRegsList[] = { - { "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0 - { "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1 - { "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2 - { "r11_usr", ARM_SYSREG_R11_USR, 0x3 }, // 3 - { "r12_usr", ARM_SYSREG_R12_USR, 0x4 }, // 4 - { "sp_usr", ARM_SYSREG_SP_USR, 0x5 }, // 5 - { "lr_usr", ARM_SYSREG_LR_USR, 0x6 }, // 6 - { "r8_fiq", ARM_SYSREG_R8_FIQ, 0x8 }, // 7 - { "r9_fiq", ARM_SYSREG_R9_FIQ, 0x9 }, // 8 - { "r10_fiq", ARM_SYSREG_R10_FIQ, 0xA }, // 9 - { "r11_fiq", ARM_SYSREG_R11_FIQ, 0xB }, // 10 - { "r12_fiq", ARM_SYSREG_R12_FIQ, 0xC }, // 11 - { "sp_fiq", ARM_SYSREG_SP_FIQ, 0xD }, // 12 - { "lr_fiq", ARM_SYSREG_LR_FIQ, 0xE }, // 13 - { "lr_irq", ARM_SYSREG_LR_IRQ, 0x10 }, // 14 - { "sp_irq", ARM_SYSREG_SP_IRQ, 0x11 }, // 15 - { "lr_svc", ARM_SYSREG_LR_SVC, 0x12 }, // 16 - { "sp_svc", ARM_SYSREG_SP_SVC, 0x13 }, // 17 - { "lr_abt", ARM_SYSREG_LR_ABT, 0x14 }, // 18 - { "sp_abt", ARM_SYSREG_SP_ABT, 0x15 }, // 19 - { "lr_und", ARM_SYSREG_LR_UND, 0x16 }, // 20 - { "sp_und", ARM_SYSREG_SP_UND, 0x17 }, // 21 - { "lr_mon", ARM_SYSREG_LR_MON, 0x1C }, // 22 - { "sp_mon", ARM_SYSREG_SP_MON, 0x1D }, // 23 - { "elr_hyp", ARM_SYSREG_ELR_HYP, 0x1E }, // 24 - { "sp_hyp", ARM_SYSREG_SP_HYP, 0x1F }, // 25 - { "spsr_fiq", ARM_SYSREG_SPSR_FIQ, 0x2E }, // 26 - { "spsr_irq", ARM_SYSREG_SPSR_IRQ, 0x30 }, // 27 - { "spsr_svc", ARM_SYSREG_SPSR_SVC, 0x32 }, // 28 - { "spsr_abt", ARM_SYSREG_SPSR_ABT, 0x34 }, // 29 - { "spsr_und", ARM_SYSREG_SPSR_UND, 0x36 }, // 30 - { "spsr_mon", ARM_SYSREG_SPSR_MON, 0x3C }, // 31 - { "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32 + {"r8_usr", ARM_SYSREG_R8_USR, 0x0}, // 0 + {"r9_usr", ARM_SYSREG_R9_USR, 0x1}, // 1 + {"r10_usr", ARM_SYSREG_R10_USR, 0x2}, // 2 + {"r11_usr", ARM_SYSREG_R11_USR, 0x3}, // 3 + {"r12_usr", ARM_SYSREG_R12_USR, 0x4}, // 4 + {"sp_usr", ARM_SYSREG_SP_USR, 0x5}, // 5 + {"lr_usr", ARM_SYSREG_LR_USR, 0x6}, // 6 + {"r8_fiq", ARM_SYSREG_R8_FIQ, 0x8}, // 7 + {"r9_fiq", ARM_SYSREG_R9_FIQ, 0x9}, // 8 + {"r10_fiq", ARM_SYSREG_R10_FIQ, 0xA}, // 9 + {"r11_fiq", ARM_SYSREG_R11_FIQ, 0xB}, // 10 + {"r12_fiq", ARM_SYSREG_R12_FIQ, 0xC}, // 11 + {"sp_fiq", ARM_SYSREG_SP_FIQ, 0xD}, // 12 + {"lr_fiq", ARM_SYSREG_LR_FIQ, 0xE}, // 13 + {"lr_irq", ARM_SYSREG_LR_IRQ, 0x10}, // 14 + {"sp_irq", ARM_SYSREG_SP_IRQ, 0x11}, // 15 + {"lr_svc", ARM_SYSREG_LR_SVC, 0x12}, // 16 + {"sp_svc", ARM_SYSREG_SP_SVC, 0x13}, // 17 + {"lr_abt", ARM_SYSREG_LR_ABT, 0x14}, // 18 + {"sp_abt", ARM_SYSREG_SP_ABT, 0x15}, // 19 + {"lr_und", ARM_SYSREG_LR_UND, 0x16}, // 20 + {"sp_und", ARM_SYSREG_SP_UND, 0x17}, // 21 + {"lr_mon", ARM_SYSREG_LR_MON, 0x1C}, // 22 + {"sp_mon", ARM_SYSREG_SP_MON, 0x1D}, // 23 + {"elr_hyp", ARM_SYSREG_ELR_HYP, 0x1E}, // 24 + {"sp_hyp", ARM_SYSREG_SP_HYP, 0x1F}, // 25 + {"spsr_fiq", ARM_SYSREG_SPSR_FIQ, 0x2E}, // 26 + {"spsr_irq", ARM_SYSREG_SPSR_IRQ, 0x30}, // 27 + {"spsr_svc", ARM_SYSREG_SPSR_SVC, 0x32}, // 28 + {"spsr_abt", ARM_SYSREG_SPSR_ABT, 0x34}, // 29 + {"spsr_und", ARM_SYSREG_SPSR_UND, 0x36}, // 30 + {"spsr_mon", ARM_SYSREG_SPSR_MON, 0x3C}, // 31 + {"spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E}, // 32 }; -const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding) -{ +const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x0, 0 }, - { 0x1, 2 }, - { 0x2, 4 }, - { 0x3, 6 }, - { 0x100, 8 }, - { 0x101, 10 }, - { 0x102, 12 }, - { 0x103, 14 }, - { 0x105, 16 }, - { 0x106, 17 }, - { 0x107, 18 }, - { 0x108, 19 }, - { 0x109, 20 }, - { 0x10A, 21 }, - { 0x10B, 22 }, - { 0x110, 23 }, - { 0x111, 24 }, - { 0x112, 25 }, - { 0x113, 26 }, - { 0x114, 27 }, - { 0x188, 28 }, - { 0x189, 29 }, - { 0x18A, 30 }, - { 0x18B, 31 }, - { 0x190, 32 }, - { 0x191, 33 }, - { 0x193, 34 }, - { 0x194, 35 }, - { 0x198, 36 }, - { 0x200, 9 }, - { 0x201, 11 }, - { 0x202, 13 }, - { 0x203, 15 }, - { 0x300, 1 }, - { 0x301, 3 }, - { 0x302, 5 }, - { 0x303, 7 }, + {0x0, 0}, {0x1, 2}, {0x2, 4}, {0x3, 6}, {0x100, 8}, + {0x101, 10}, {0x102, 12}, {0x103, 14}, {0x105, 16}, {0x106, 17}, + {0x107, 18}, {0x108, 19}, {0x109, 20}, {0x10A, 21}, {0x10B, 22}, + {0x110, 23}, {0x111, 24}, {0x112, 25}, {0x113, 26}, {0x114, 27}, + {0x188, 28}, {0x189, 29}, {0x18A, 30}, {0x18B, 31}, {0x190, 32}, + {0x191, 33}, {0x193, 34}, {0x194, 35}, {0x198, 36}, {0x200, 9}, + {0x201, 11}, {0x202, 13}, {0x203, 15}, {0x300, 1}, {0x301, 3}, + {0x302, 5}, {0x303, 7}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); @@ -172,47 +222,17 @@ const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding) return &MClassSysRegsList[Index[i].index]; } -const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding) -{ +const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x400, 0 }, - { 0x401, 2 }, - { 0x402, 4 }, - { 0x403, 6 }, - { 0x800, 8 }, - { 0x801, 10 }, - { 0x802, 12 }, - { 0x803, 14 }, - { 0x805, 16 }, - { 0x806, 17 }, - { 0x807, 18 }, - { 0x808, 19 }, - { 0x809, 20 }, - { 0x80A, 21 }, - { 0x80B, 22 }, - { 0x810, 23 }, - { 0x811, 24 }, - { 0x812, 25 }, - { 0x813, 26 }, - { 0x814, 27 }, - { 0x888, 28 }, - { 0x889, 29 }, - { 0x88A, 30 }, - { 0x88B, 31 }, - { 0x890, 32 }, - { 0x891, 33 }, - { 0x893, 34 }, - { 0x894, 35 }, - { 0x898, 36 }, - { 0xC00, 1 }, - { 0xC01, 3 }, - { 0xC02, 5 }, - { 0xC03, 7 }, - { 0x1800, 9 }, - { 0x1801, 11 }, - { 0x1802, 13 }, - { 0x1803, 15 }, + {0x400, 0}, {0x401, 2}, {0x402, 4}, {0x403, 6}, {0x800, 8}, + {0x801, 10}, {0x802, 12}, {0x803, 14}, {0x805, 16}, {0x806, 17}, + {0x807, 18}, {0x808, 19}, {0x809, 20}, {0x80A, 21}, {0x80B, 22}, + {0x810, 23}, {0x811, 24}, {0x812, 25}, {0x813, 26}, {0x814, 27}, + {0x888, 28}, {0x889, 29}, {0x88A, 30}, {0x88B, 31}, {0x890, 32}, + {0x891, 33}, {0x893, 34}, {0x894, 35}, {0x898, 36}, {0xC00, 1}, + {0xC01, 3}, {0xC02, 5}, {0xC03, 7}, {0x1800, 9}, {0x1801, 11}, + {0x1802, 13}, {0x1803, 15}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); @@ -222,43 +242,15 @@ const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding) return &MClassSysRegsList[Index[i].index]; } -const BankedReg *lookupBankedRegByEncoding(uint8_t encoding) -{ +const BankedReg *lookupBankedRegByEncoding(uint8_t encoding) { unsigned int i; static const struct IndexType Index[] = { - { 0x0, 0 }, - { 0x1, 1 }, - { 0x2, 2 }, - { 0x3, 3 }, - { 0x4, 4 }, - { 0x5, 5 }, - { 0x6, 6 }, - { 0x8, 7 }, - { 0x9, 8 }, - { 0xA, 9 }, - { 0xB, 10 }, - { 0xC, 11 }, - { 0xD, 12 }, - { 0xE, 13 }, - { 0x10, 14 }, - { 0x11, 15 }, - { 0x12, 16 }, - { 0x13, 17 }, - { 0x14, 18 }, - { 0x15, 19 }, - { 0x16, 20 }, - { 0x17, 21 }, - { 0x1C, 22 }, - { 0x1D, 23 }, - { 0x1E, 24 }, - { 0x1F, 25 }, - { 0x2E, 26 }, - { 0x30, 27 }, - { 0x32, 28 }, - { 0x34, 29 }, - { 0x36, 30 }, - { 0x3C, 31 }, - { 0x3E, 32 }, + {0x0, 0}, {0x1, 1}, {0x2, 2}, {0x3, 3}, {0x4, 4}, {0x5, 5}, + {0x6, 6}, {0x8, 7}, {0x9, 8}, {0xA, 9}, {0xB, 10}, {0xC, 11}, + {0xD, 12}, {0xE, 13}, {0x10, 14}, {0x11, 15}, {0x12, 16}, {0x13, 17}, + {0x14, 18}, {0x15, 19}, {0x16, 20}, {0x17, 21}, {0x1C, 22}, {0x1D, 23}, + {0x1E, 24}, {0x1F, 25}, {0x2E, 26}, {0x30, 27}, {0x32, 28}, {0x34, 29}, + {0x36, 30}, {0x3C, 31}, {0x3E, 32}, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); @@ -267,4 +259,3 @@ const BankedReg *lookupBankedRegByEncoding(uint8_t encoding) else return &BankedRegsList[Index[i].index]; } - diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index 47263ed680..e10e52d769 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -16,926 +16,1121 @@ #ifdef CAPSTONE_HAS_ARM -#include // DEBUG +#include +#include // DEBUG #include #include -#include -#include "ARMInstPrinter.h" -#include "ARMAddressingModes.h" -#include "ARMBaseInfo.h" -#include "ARMDisassembler.h" #include "../../MCInst.h" -#include "../../SStream.h" #include "../../MCRegisterInfo.h" +#include "../../SStream.h" #include "../../utils.h" +#include "ARMAddressingModes.h" +#include "ARMBaseInfo.h" +#include "ARMDisassembler.h" +#include "ARMInstPrinter.h" #include "ARMMapping.h" #define GET_SUBTARGETINFO_ENUM -#include "ARMGenSubtargetInfo.inc" - +#include "ARMGenDisassemblerTables.inc" #include "ARMGenSystemRegister.inc" static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo); // Autogenerated by tblgen. static void printInstruction(MCInst *MI, SStream *O); + static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); + static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O); + static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O); + static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O); + static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O); + static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); -static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); + +static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool AlwaysPrintImm0); + static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); -static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0); + +static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, + bool AlwaysPrintImm0); + static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O); + static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O); -static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); + +static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool AlwaysPrintImm0); + static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O); + static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O); + static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); -static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, + SStream *O); + static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O); + static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O); + static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O); -static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned); + +static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, + unsigned); + static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O); + static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O); + static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O); -static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale); -static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O); -static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O); -static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O); + +static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, + SStream *O, unsigned Scale); + +static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, + SStream *O); + +static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, + SStream *O); + +static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, + SStream *O); + static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O); -static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); -static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); -static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); -static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O); -static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); -static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); + +static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool AlwaysPrintImm0); + +static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool); + +static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool); + +static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, + SStream *O); + +static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, + SStream *O); + +static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, + SStream *O); + static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O); + static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O); + static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); -static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); + +static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O); + static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O); + static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O); + static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O); + static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O); + static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O); + static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O); + static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O); + static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O); + static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O); + static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O); + static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O); + static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O); + static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O); + static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O); + static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O); -static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O); + +static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, + SStream *O); + static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O); -static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); -static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); -static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); + +static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, + SStream *O); + +static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, + SStream *O); + +static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, + SStream *O); + static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O); + static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O); + static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O); + static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printVPTPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); + +static void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O); + +static void printMVEVectorList(MCInst *MI, unsigned NumRegs, SStream *O, + unsigned OpNum); + +static void printVMOVModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); + +static void printMveAddrModeRQOperand(MCInst *MI, unsigned OpNum, SStream *O, + int shift); + +static void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O); + +static void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O); + +static void printMveSaturateOp(MCInst *MI, unsigned OpNum, SStream *O); + +// -- mark the line of inserted print functions + static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); + static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); -static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder); -static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); +static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, + int64_t Angle, int64_t Remainder); + +static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool AlwaysPrintImm0); #ifndef CAPSTONE_DIET + // copy & normalize access info -static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index) -{ - const uint8_t *arr = ARM_get_op_access(h, id); +static uint8_t get_op_access(cs_struct *h, unsigned int id, + unsigned int index) { + const uint8_t *arr = ARM_get_op_access(h, id); - if (!arr || arr[index] == CS_AC_IGNORE) - return 0; + if (!arr || arr[index] == CS_AC_IGNORE) + return 0; - return arr[index]; + return arr[index]; } + #endif -static void set_mem_access(MCInst *MI, bool status) -{ - if (MI->csh->detail != CS_OPT_ON) - return; +static void set_mem_access(MCInst *MI, bool status) { + if (MI->csh->detail != CS_OPT_ON) + return; - MI->csh->doing_mem = status; - if (status) { + MI->csh->doing_mem = status; + if (status) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; #endif - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_MEM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.scale = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = 0; #ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; - MI->ac_idx++; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; + MI->ac_idx++; #endif - } else { - // done, create the next operand slot - MI->flat_insn->detail->arm.op_count++; - } + } else { + // done, create the next operand slot + MI->flat_insn->detail->arm.op_count++; + } } -static void op_addImm(MCInst *MI, int v) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; - MI->flat_insn->detail->arm.op_count++; - } +static void op_addImm(MCInst *MI, int v) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = v; + MI->flat_insn->detail->arm.op_count++; + } } -#define GET_INSTRINFO_ENUM -#include "ARMGenInstrInfo.inc" +#include "../MCInstPrinter.h" -static void printCustomAliasOperand(MCInst *MI, - unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS); +static void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); +#define GET_INSTRINFO_ENUM +#define GET_REGINFO_ENUM +#define GET_ASM_WRITER +#define GET_REGINFO_EXTRA #define PRINT_ALIAS_INSTR -#include "ARMGenAsmWriter.inc" -#include "ARMGenRegisterName.inc" -#include "ARMGenRegisterName_digit.inc" -void ARM_getRegName(cs_struct *handle, int value) -{ - if (value == CS_OPT_SYNTAX_NOREGNAME) { - handle->get_regname = getRegisterName_digit; - handle->reg_name = ARM_reg_name2;; - } else { - handle->get_regname = getRegisterName; - handle->reg_name = ARM_reg_name;; - } +#include "../../sync/logger.h" +#include "ARMGenDisassemblerTables.inc" + +const char *getRegisterNameNoRaw(unsigned RegNo) { + debugln("request reg num %d", RegNo); + unsigned Mapped = RegNo; + if (ARM_reg_name(0, Mapped)) + return ARM_reg_name(0, Mapped); + return getRegisterName(RegNo, ARM_NoRegAltName); +} + +const char *getRegisterNameRaw(unsigned RegNo) { + return getRegisterName(RegNo, ARM_RegNamesRaw); +} + +void ARM_getRegName(cs_struct *handle, int value) { + if (value == CS_OPT_SYNTAX_NOREGNAME) { + // handle->get_regname = getRegisterName_digit; + handle->get_regname = getRegisterNameRaw; + handle->reg_name = ARM_reg_name2; + debugln("using raw"); + } else { + handle->get_regname = getRegisterNameNoRaw; + handle->reg_name = ARM_reg_name; + debugln("using non raw"); + } } /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. /// /// getSORegOffset returns an integer from 0-31, representing '32' as 0. -static unsigned translateShiftImm(unsigned imm) -{ - // lsr #32 and asr #32 exist, but should be encoded as a 0. - //assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); - if (imm == 0) - return 32; - return imm; +static unsigned translateShiftImm(unsigned imm) { + // lsr #32 and asr #32 exist, but should be encoded as a 0. + // assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); + if (imm == 0) + return 32; + return imm; } /// Prints the shift value with an immediate value. -static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm) -{ - if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) - return; +static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, + unsigned ShImm) { + debugln("printing shift imm"); + if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) + return; - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - //assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0"); - SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); + // assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0"); + SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); - if (MI->csh->detail) { - if (MI->csh->doing_mem) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc; - else - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc; - } + if (MI->csh->detail) { + if (MI->csh->doing_mem) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .shift.type = (arm_shifter)ShOpc; + else + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.type = (arm_shifter)ShOpc; + } - if (ShOpc != ARM_AM_rrx) { - SStream_concat0(O, " "); - SStream_concat(O, "#%u", translateShiftImm(ShImm)); - if (MI->csh->detail) { - if (MI->csh->doing_mem) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm); - else - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm); - } - } + if (ShOpc != ARM_AM_rrx) { + SStream_concat0(O, " "); + SStream_concat(O, "#%u", translateShiftImm(ShImm)); + if (MI->csh->detail) { + if (MI->csh->doing_mem) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .shift.value = translateShiftImm(ShImm); + else + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.value = translateShiftImm(ShImm); + } + } } -static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo) -{ +static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo) { #ifndef CAPSTONE_DIET - SStream_concat0(OS, h->get_regname(RegNo)); + if (RegNo == 0) + return; + SStream_concat0(OS, h->get_regname(RegNo)); #endif } // TODO static const name_map insn_update_flgs[] = { - { ARM_INS_CMN, "cmn" }, - { ARM_INS_CMP, "cmp" }, - { ARM_INS_TEQ, "teq" }, - { ARM_INS_TST, "tst" }, - - { ARM_INS_ADC, "adcs" }, - { ARM_INS_ADD, "adds" }, - { ARM_INS_AND, "ands" }, - { ARM_INS_ASR, "asrs" }, - { ARM_INS_BIC, "bics" }, - { ARM_INS_EOR, "eors" }, - { ARM_INS_LSL, "lsls" }, - { ARM_INS_LSR, "lsrs" }, - { ARM_INS_MLA, "mlas" }, - { ARM_INS_MOV, "movs" }, - { ARM_INS_MUL, "muls" }, - { ARM_INS_MVN, "mvns" }, - { ARM_INS_ORN, "orns" }, - { ARM_INS_ORR, "orrs" }, - { ARM_INS_ROR, "rors" }, - { ARM_INS_RRX, "rrxs" }, - { ARM_INS_RSB, "rsbs" }, - { ARM_INS_RSC, "rscs" }, - { ARM_INS_SBC, "sbcs" }, - { ARM_INS_SMLAL, "smlals" }, - { ARM_INS_SMULL, "smulls" }, - { ARM_INS_SUB, "subs" }, - { ARM_INS_UMLAL, "umlals" }, - { ARM_INS_UMULL, "umulls" }, - - { ARM_INS_UADD8, "uadd8" }, + {ARM_INS_CMN, "cmn"}, {ARM_INS_CMP, "cmp"}, + {ARM_INS_TEQ, "teq"}, {ARM_INS_TST, "tst"}, + + {ARM_INS_ADC, "adcs"}, {ARM_INS_ADD, "adds"}, + {ARM_INS_AND, "ands"}, {ARM_INS_ASR, "asrs"}, + {ARM_INS_BIC, "bics"}, {ARM_INS_EOR, "eors"}, + {ARM_INS_LSL, "lsls"}, {ARM_INS_LSR, "lsrs"}, + {ARM_INS_MLA, "mlas"}, {ARM_INS_MOV, "movs"}, + {ARM_INS_MUL, "muls"}, {ARM_INS_MVN, "mvns"}, + {ARM_INS_ORN, "orns"}, {ARM_INS_ORR, "orrs"}, + {ARM_INS_ROR, "rors"}, {ARM_INS_RRX, "rrxs"}, + {ARM_INS_RSB, "rsbs"}, {ARM_INS_RSC, "rscs"}, + {ARM_INS_SBC, "sbcs"}, {ARM_INS_SMLAL, "smlals"}, + {ARM_INS_SMULL, "smulls"}, {ARM_INS_SUB, "subs"}, + {ARM_INS_UMLAL, "umlals"}, {ARM_INS_UMULL, "umulls"}, + + {ARM_INS_UADD8, "uadd8"}, }; -void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) -{ - if (((cs_struct *)ud)->detail != CS_OPT_ON) - return; - - // check if this insn requests write-back - if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) { - insn->detail->arm.writeback = true; - } else if (mci->csh->mode & CS_MODE_THUMB) { - // handle some special instructions with writeback - //printf(">> Opcode = %u\n", mci->Opcode); - switch(mci->Opcode) { - default: - break; - case ARM_t2LDC2L_PRE: - case ARM_t2LDC2_PRE: - case ARM_t2LDCL_PRE: - case ARM_t2LDC_PRE: - - case ARM_t2LDRB_PRE: - case ARM_t2LDRD_PRE: - case ARM_t2LDRH_PRE: - case ARM_t2LDRSB_PRE: - case ARM_t2LDRSH_PRE: - case ARM_t2LDR_PRE: - - case ARM_t2STC2L_PRE: - case ARM_t2STC2_PRE: - case ARM_t2STCL_PRE: - case ARM_t2STC_PRE: - - case ARM_t2STRB_PRE: - case ARM_t2STRD_PRE: - case ARM_t2STRH_PRE: - case ARM_t2STR_PRE: - - case ARM_t2LDC2L_POST: - case ARM_t2LDC2_POST: - case ARM_t2LDCL_POST: - case ARM_t2LDC_POST: - - case ARM_t2LDRB_POST: - case ARM_t2LDRD_POST: - case ARM_t2LDRH_POST: - case ARM_t2LDRSB_POST: - case ARM_t2LDRSH_POST: - case ARM_t2LDR_POST: - - case ARM_t2STC2L_POST: - case ARM_t2STC2_POST: - case ARM_t2STCL_POST: - case ARM_t2STC_POST: - - case ARM_t2STRB_POST: - case ARM_t2STRD_POST: - case ARM_t2STRH_POST: - case ARM_t2STR_POST: - insn->detail->arm.writeback = true; - break; - } - } else { // ARM mode - // handle some special instructions with writeback - //printf(">> Opcode = %u\n", mci->Opcode); - switch(mci->Opcode) { - default: - break; - case ARM_LDC2L_PRE: - case ARM_LDC2_PRE: - case ARM_LDCL_PRE: - case ARM_LDC_PRE: - - case ARM_LDRD_PRE: - case ARM_LDRH_PRE: - case ARM_LDRSB_PRE: - case ARM_LDRSH_PRE: - - case ARM_STC2L_PRE: - case ARM_STC2_PRE: - case ARM_STCL_PRE: - case ARM_STC_PRE: - - case ARM_STRD_PRE: - case ARM_STRH_PRE: - - case ARM_LDC2L_POST: - case ARM_LDC2_POST: - case ARM_LDCL_POST: - case ARM_LDC_POST: - - case ARM_LDRBT_POST: - case ARM_LDRD_POST: - case ARM_LDRH_POST: - case ARM_LDRSB_POST: - case ARM_LDRSH_POST: - - case ARM_STC2L_POST: - case ARM_STC2_POST: - case ARM_STCL_POST: - case ARM_STC_POST: - - case ARM_STRBT_POST: - case ARM_STRD_POST: - case ARM_STRH_POST: - - case ARM_LDRB_POST_IMM: - case ARM_LDR_POST_IMM: - case ARM_LDR_POST_REG: - case ARM_STRB_POST_IMM: - - case ARM_STR_POST_IMM: - case ARM_STR_POST_REG: - - insn->detail->arm.writeback = true; - break; - } - } - - // check if this insn requests update flags - if (insn->detail->arm.update_flags == false) { - // some insn still update flags, regardless of tabgen info - unsigned int i, j; - - for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) { - if (insn->id == insn_update_flgs[i].id && - !strncmp(insn_asm, insn_update_flgs[i].name, - strlen(insn_update_flgs[i].name))) { - insn->detail->arm.update_flags = true; - // we have to update regs_write array as well - for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) { - if (insn->detail->regs_write[j] == 0) { - insn->detail->regs_write[j] = ARM_REG_CPSR; - break; - } - } - break; - } - } - } - - // instruction should not have invalid CC - if (insn->detail->arm.cc == ARM_CC_INVALID) { - insn->detail->arm.cc = ARM_CC_AL; - } - - // manual fix for some special instructions - // printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode); - switch(mci->Opcode) { - default: - break; - case ARM_MOVPCLR: - insn->detail->arm.operands[0].type = ARM_OP_REG; - insn->detail->arm.operands[0].reg = ARM_REG_PC; - insn->detail->arm.operands[0].access = CS_AC_WRITE; - insn->detail->arm.operands[1].type = ARM_OP_REG; - insn->detail->arm.operands[1].reg = ARM_REG_LR; - insn->detail->arm.operands[1].access = CS_AC_READ; - insn->detail->arm.op_count = 2; - break; - } -} - -void ARM_printInst(MCInst *MI, SStream *O, void *Info) -{ - MCRegisterInfo *MRI = (MCRegisterInfo *)Info; - unsigned Opcode = MCInst_getOpcode(MI), tmp, i; - - //printf(">>> Opcode = %u\n", Opcode); - switch (Opcode) { - // Check for MOVs and print canonical forms, instead. - case ARM_MOVsr: { - // FIXME: Thumb variants? - unsigned int opc; - MCOperand *Dst = MCInst_getOperand(MI, 0); - MCOperand *MO1 = MCInst_getOperand(MI, 1); - MCOperand *MO2 = MCInst_getOperand(MI, 2); - MCOperand *MO3 = MCInst_getOperand(MI, 3); - - opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); - SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); - - switch (opc) { - default: break; - case ARM_AM_asr: - MCInst_setOpcodePub(MI, ARM_INS_ASR); - break; - case ARM_AM_lsl: - MCInst_setOpcodePub(MI, ARM_INS_LSL); - break; - case ARM_AM_lsr: - MCInst_setOpcodePub(MI, ARM_INS_LSR); - break; - case ARM_AM_ror: - MCInst_setOpcodePub(MI, ARM_INS_ROR); - break; - case ARM_AM_rrx: - MCInst_setOpcodePub(MI, ARM_INS_RRX); - break; - } - - printSBitModifierOperand(MI, 6, O); - printPredicateOperand(MI, 4, O); - - SStream_concat0(O, "\t"); - printRegName(MI->csh, O, MCOperand_getReg(Dst)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; - MI->flat_insn->detail->arm.op_count++; - } - - SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.op_count++; - } - - SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MO2)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.op_count++; - } - - return; - } - - case ARM_MOVsi: { - // FIXME: Thumb variants? - unsigned int opc; - MCOperand *Dst = MCInst_getOperand(MI, 0); - MCOperand *MO1 = MCInst_getOperand(MI, 1); - MCOperand *MO2 = MCInst_getOperand(MI, 2); - - opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)); - SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); - - switch(opc) { - default: - break; - case ARM_AM_asr: - MCInst_setOpcodePub(MI, ARM_INS_ASR); - break; - case ARM_AM_lsl: - MCInst_setOpcodePub(MI, ARM_INS_LSL); - break; - case ARM_AM_lsr: - MCInst_setOpcodePub(MI, ARM_INS_LSR); - break; - case ARM_AM_ror: - MCInst_setOpcodePub(MI, ARM_INS_ROR); - break; - case ARM_AM_rrx: - MCInst_setOpcodePub(MI, ARM_INS_RRX); - break; - } - - printSBitModifierOperand(MI, 5, O); - printPredicateOperand(MI, 3, O); - - SStream_concat0(O, "\t"); - printRegName(MI->csh, O, MCOperand_getReg(Dst)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; - MI->flat_insn->detail->arm.op_count++; - } - - SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.op_count++; - } - - if (opc == ARM_AM_rrx) { - //printAnnotation(O, Annot); - return; - } - - SStream_concat0(O, ", "); - tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2))); - printUInt32Bang(O, tmp); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = - (arm_shifter)opc; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; - } - - return; - } - - // A8.6.123 PUSH - case ARM_STMDB_UPD: - case ARM_t2STMDB_UPD: - if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && - MCInst_getNumOperands(MI) > 5) { - // Should only print PUSH if there are at least two registers in the list. - SStream_concat0(O, "push"); - MCInst_setOpcodePub(MI, ARM_INS_PUSH); - printPredicateOperand(MI, 2, O); - - if (Opcode == ARM_t2STMDB_UPD) - SStream_concat0(O, ".w"); - - SStream_concat0(O, "\t"); - - if (MI->csh->detail) { - MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; - MI->flat_insn->detail->regs_read_count++; - MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; - MI->flat_insn->detail->regs_write_count++; - } - - printRegisterList(MI, 4, O); - return; - } else - break; - - case ARM_STR_PRE_IMM: - if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP && - MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) { - SStream_concat0(O, "push"); - MCInst_setOpcodePub(MI, ARM_INS_PUSH); - - printPredicateOperand(MI, 4, O); - - SStream_concat0(O, "\t{"); - - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1))); - - if (MI->csh->detail) { -#ifndef CAPSTONE_DIET - uint8_t access; -#endif - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm.op_count++; - } - - SStream_concat0(O, "}"); - - return; - } else - break; - - // A8.6.122 POP - case ARM_LDMIA_UPD: - case ARM_t2LDMIA_UPD: - if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && - MCInst_getNumOperands(MI) > 5) { - // Should only print POP if there are at least two registers in the list. - SStream_concat0(O, "pop"); - MCInst_setOpcodePub(MI, ARM_INS_POP); - - printPredicateOperand(MI, 2, O); - if (Opcode == ARM_t2LDMIA_UPD) - SStream_concat0(O, ".w"); - - SStream_concat0(O, "\t"); - - // unlike LDM, POP only write to registers, so skip the 1st access code - MI->ac_idx = 1; - if (MI->csh->detail) { - MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; - MI->flat_insn->detail->regs_read_count++; - MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; - MI->flat_insn->detail->regs_write_count++; - } - - printRegisterList(MI, 4, O); - - return; - } - break; - - case ARM_LDR_POST_IMM: - if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) { - MCOperand *MO2 = MCInst_getOperand(MI, 4); - - if (getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) { - SStream_concat0(O, "pop"); - MCInst_setOpcodePub(MI, ARM_INS_POP); - printPredicateOperand(MI, 5, O); - SStream_concat0(O, "\t{"); - - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0))); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; - MI->flat_insn->detail->arm.op_count++; - // this instruction implicitly read/write SP register - MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; - MI->flat_insn->detail->regs_read_count++; - MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; - MI->flat_insn->detail->regs_write_count++; - } - SStream_concat0(O, "}"); - return; - } - } - break; - - // A8.6.355 VPUSH - case ARM_VSTMSDB_UPD: - case ARM_VSTMDDB_UPD: - if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { - SStream_concat0(O, "vpush"); - MCInst_setOpcodePub(MI, ARM_INS_VPUSH); - printPredicateOperand(MI, 2, O); - SStream_concat0(O, "\t"); - printRegisterList(MI, 4, O); - return; - } - break; - - // A8.6.354 VPOP - case ARM_VLDMSIA_UPD: - case ARM_VLDMDIA_UPD: - if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { - SStream_concat0(O, "vpop"); - MCInst_setOpcodePub(MI, ARM_INS_VPOP); - printPredicateOperand(MI, 2, O); - SStream_concat0(O, "\t"); - printRegisterList(MI, 4, O); - return; - } - break; - - case ARM_tLDMIA: { - bool Writeback = true; - unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0)); - unsigned i; - - for (i = 3; i < MCInst_getNumOperands(MI); ++i) { - if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg) - Writeback = false; - } - - SStream_concat0(O, "ldm"); - MCInst_setOpcodePub(MI, ARM_INS_LDM); - - printPredicateOperand(MI, 1, O); - SStream_concat0(O, "\t"); - printRegName(MI->csh, O, BaseReg); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ | CS_AC_WRITE; - MI->flat_insn->detail->arm.op_count++; - } - - if (Writeback) { - MI->writeback = true; - SStream_concat0(O, "!"); - } - - SStream_concat0(O, ", "); - printRegisterList(MI, 3, O); - return; - } - - // Combine 2 GPRs from disassember into a GPRPair to match with instr def. - // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, - // a single GPRPair reg operand is used in the .td file to replace the two - // GPRs. However, when decoding them, the two GRPs cannot be automatically - // expressed as a GPRPair, so we have to manually merge them. - // FIXME: We would really like to be able to tablegen'erate this. - case ARM_LDREXD: - case ARM_STREXD: - case ARM_LDAEXD: - case ARM_STLEXD: { - const MCRegisterClass *MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID); - bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0)); - - if (MCRegisterClass_contains(MRC, Reg)) { - MCInst NewMI; - - MCInst_Init(&NewMI); - MCInst_setOpcode(&NewMI, Opcode); - - if (isStore) - MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0)); - - MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0, - MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID))); - - // Copy the rest operands into NewMI. - for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i) - MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i)); - - printInstruction(&NewMI, O); - return; - } - break; - } - - case ARM_TSB: - case ARM_t2TSB: - SStream_concat0(O, "tsb\tcsync"); - MCInst_setOpcodePub(MI, ARM_INS_TSB); - // TODO: add csync to operands[]? - return; - } - - MI->MRI = MRI; - - if (!printAliasInstr(MI, O)) { - printInstruction(MI, O); - } -} - -static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - int32_t imm; - MCOperand *Op = MCInst_getOperand(MI, OpNo); - - if (MCOperand_isReg(Op)) { - unsigned Reg = MCOperand_getReg(Op); - - printRegName(MI->csh, O, Reg); - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg; - else - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg; - } else { -#ifndef CAPSTONE_DIET - uint8_t access; -#endif - - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm.op_count++; - } - } - } else if (MCOperand_isImm(Op)) { - unsigned int opc = MCInst_getOpcode(MI); - - imm = (int32_t)MCOperand_getImm(Op); - - // relative branch only has relative offset, so we have to update it - // to reflect absolute address. - // Note: in ARM, PC is always 2 instructions ahead, so we have to - // add 8 in ARM mode, or 4 in Thumb mode - // printf(">> opcode: %u\n", MCInst_getOpcode(MI)); - if (ARM_rel_branch(MI->csh, opc)) { - uint32_t address; - - // only do this for relative branch - if (MI->csh->mode & CS_MODE_THUMB) { - address = (uint32_t)MI->address + 4; - if (ARM_blx_to_arm_mode(MI->csh, opc)) { - // here need to align down to the nearest 4-byte address -#define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width) - address = _ALIGN_DOWN(address, 4); +void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + + // check if this insn requests write-back + if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) { + insn->detail->arm.writeback = true; + } else if (mci->csh->mode & CS_MODE_THUMB) { + // handle some special instructions with writeback + // printf(">> Opcode = %u\n", mci->Opcode); + switch (mci->Opcode) { + default: + break; + case ARM_t2LDC2L_PRE: + case ARM_t2LDC2_PRE: + case ARM_t2LDCL_PRE: + case ARM_t2LDC_PRE: + + case ARM_t2LDRB_PRE: + case ARM_t2LDRD_PRE: + case ARM_t2LDRH_PRE: + case ARM_t2LDRSB_PRE: + case ARM_t2LDRSH_PRE: + case ARM_t2LDR_PRE: + + case ARM_t2STC2L_PRE: + case ARM_t2STC2_PRE: + case ARM_t2STCL_PRE: + case ARM_t2STC_PRE: + + case ARM_t2STRB_PRE: + case ARM_t2STRD_PRE: + case ARM_t2STRH_PRE: + case ARM_t2STR_PRE: + + case ARM_t2LDC2L_POST: + case ARM_t2LDC2_POST: + case ARM_t2LDCL_POST: + case ARM_t2LDC_POST: + + case ARM_t2LDRB_POST: + case ARM_t2LDRD_POST: + case ARM_t2LDRH_POST: + case ARM_t2LDRSB_POST: + case ARM_t2LDRSH_POST: + case ARM_t2LDR_POST: + + case ARM_t2STC2L_POST: + case ARM_t2STC2_POST: + case ARM_t2STCL_POST: + case ARM_t2STC_POST: + + case ARM_t2STRB_POST: + case ARM_t2STRD_POST: + case ARM_t2STRH_POST: + case ARM_t2STR_POST: + insn->detail->arm.writeback = true; + break; + } + } else { // ARM mode + // handle some special instructions with writeback + // printf(">> Opcode = %u\n", mci->Opcode); + switch (mci->Opcode) { + default: + break; + case ARM_LDC2L_PRE: + case ARM_LDC2_PRE: + case ARM_LDCL_PRE: + case ARM_LDC_PRE: + + case ARM_LDRD_PRE: + case ARM_LDRH_PRE: + case ARM_LDRSB_PRE: + case ARM_LDRSH_PRE: + + case ARM_STC2L_PRE: + case ARM_STC2_PRE: + case ARM_STCL_PRE: + case ARM_STC_PRE: + + case ARM_STRD_PRE: + case ARM_STRH_PRE: + + case ARM_LDC2L_POST: + case ARM_LDC2_POST: + case ARM_LDCL_POST: + case ARM_LDC_POST: + + case ARM_LDRBT_POST: + case ARM_LDRD_POST: + case ARM_LDRH_POST: + case ARM_LDRSB_POST: + case ARM_LDRSH_POST: + + case ARM_STC2L_POST: + case ARM_STC2_POST: + case ARM_STCL_POST: + case ARM_STC_POST: + + case ARM_STRBT_POST: + case ARM_STRD_POST: + case ARM_STRH_POST: + + case ARM_LDRB_POST_IMM: + case ARM_LDR_POST_IMM: + case ARM_LDR_POST_REG: + case ARM_STRB_POST_IMM: + + case ARM_STR_POST_IMM: + case ARM_STR_POST_REG: + + insn->detail->arm.writeback = true; + break; + } + } + + // check if this insn requests update flags + if (insn->detail->arm.update_flags == false) { + // some insn still update flags, regardless of tabgen info + unsigned int i, j; + + for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) { + if (insn->id == insn_update_flgs[i].id && + !strncmp(insn_asm, insn_update_flgs[i].name, + strlen(insn_update_flgs[i].name))) { + insn->detail->arm.update_flags = true; + // we have to update regs_write array as well + for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) { + if (insn->detail->regs_write[j] == 0) { + insn->detail->regs_write[j] = ARM_REG_CPSR; + break; + } + } + break; + } + } + } + + // instruction should not have invalid CC + if (insn->detail->arm.cc == ARM_CC_INVALID) { + insn->detail->arm.cc = ARM_CC_AL; + } + + // manual fix for some special instructions + // printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode); + switch (mci->Opcode) { + default: + break; + case ARM_MOVPCLR: + insn->detail->arm.operands[0].type = ARM_OP_REG; + insn->detail->arm.operands[0].reg = ARM_REG_PC; + insn->detail->arm.operands[0].access = CS_AC_WRITE; + insn->detail->arm.operands[1].type = ARM_OP_REG; + insn->detail->arm.operands[1].reg = ARM_REG_LR; + insn->detail->arm.operands[1].access = CS_AC_READ; + insn->detail->arm.op_count = 2; + break; + } +} + +void ARM_printInst(MCInst *MI, SStream *O, void *Info) { + MCRegisterInfo *MRI = (MCRegisterInfo *)Info; + unsigned Opcode = MCInst_getOpcode(MI), tmp, i; + + // printf(">>> Opcode = %u\n", Opcode); + switch (Opcode) { + // Check for MOVs and print canonical forms, instead. + case ARM_MOVsr: { + // FIXME: Thumb variants? + unsigned int opc; + MCOperand *Dst = MCInst_getOperand(MI, 0); + MCOperand *MO1 = MCInst_getOperand(MI, 1); + MCOperand *MO2 = MCInst_getOperand(MI, 2); + MCOperand *MO3 = MCInst_getOperand(MI, 3); + + opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); + SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); + + switch (opc) { + default: + break; + case ARM_AM_asr: + MCInst_setOpcodePub(MI, ARM_INS_ASR); + break; + case ARM_AM_lsl: + MCInst_setOpcodePub(MI, ARM_INS_LSL); + break; + case ARM_AM_lsr: + MCInst_setOpcodePub(MI, ARM_INS_LSR); + break; + case ARM_AM_ror: + MCInst_setOpcodePub(MI, ARM_INS_ROR); + break; + case ARM_AM_rrx: + MCInst_setOpcodePub(MI, ARM_INS_RRX); + break; + } + + printSBitModifierOperand(MI, 6, O); + printPredicateOperand(MI, 4, O); + + SStream_concat0(O, "\t"); + printRegName(MI->csh, O, MCOperand_getReg(Dst)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(Dst); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_WRITE; + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MO2); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + + return; + } + + case ARM_MOVsi: { + // FIXME: Thumb variants? + unsigned int opc; + MCOperand *Dst = MCInst_getOperand(MI, 0); + MCOperand *MO1 = MCInst_getOperand(MI, 1); + MCOperand *MO2 = MCInst_getOperand(MI, 2); + + opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)); + SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); + + switch (opc) { + default: + break; + case ARM_AM_asr: + MCInst_setOpcodePub(MI, ARM_INS_ASR); + break; + case ARM_AM_lsl: + MCInst_setOpcodePub(MI, ARM_INS_LSL); + break; + case ARM_AM_lsr: + MCInst_setOpcodePub(MI, ARM_INS_LSR); + break; + case ARM_AM_ror: + MCInst_setOpcodePub(MI, ARM_INS_ROR); + break; + case ARM_AM_rrx: + MCInst_setOpcodePub(MI, ARM_INS_RRX); + break; + } + + printSBitModifierOperand(MI, 5, O); + printPredicateOperand(MI, 3, O); + + SStream_concat0(O, "\t"); + printRegName(MI->csh, O, MCOperand_getReg(Dst)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(Dst); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_WRITE; + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + + if (opc == ARM_AM_rrx) { + // printAnnotation(O, Annot); + return; + } + + SStream_concat0(O, ", "); + tmp = + translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2))); + printUInt32Bang(O, tmp); + if (MI->csh->detail) { + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.type = (arm_shifter)opc; + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.value = tmp; + } + + return; + } + + // A8.6.123 PUSH + case ARM_STMDB_UPD: + case ARM_t2STMDB_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && + MCInst_getNumOperands(MI) > 5) { + // Should only print PUSH if there are at least two registers in the list. + SStream_concat0(O, "push"); + MCInst_setOpcodePub(MI, ARM_INS_PUSH); + printPredicateOperand(MI, 2, O); + + if (Opcode == ARM_t2STMDB_UPD) + SStream_concat0(O, ".w"); + + SStream_concat0(O, "\t"); + + if (MI->csh->detail) { + MI->flat_insn->detail + ->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_read_count++; + MI->flat_insn->detail + ->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_write_count++; + } + + printRegisterList(MI, 4, O); + return; + } else + break; + + case ARM_STR_PRE_IMM: + if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) { + SStream_concat0(O, "push"); + MCInst_setOpcodePub(MI, ARM_INS_PUSH); + + printPredicateOperand(MI, 4, O); + + SStream_concat0(O, "\t{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1))); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; +#endif + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "}"); + + return; + } else + break; + + // A8.6.122 POP + case ARM_LDMIA_UPD: + case ARM_t2LDMIA_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && + MCInst_getNumOperands(MI) > 5) { + // Should only print POP if there are at least two registers in the list. + SStream_concat0(O, "pop"); + MCInst_setOpcodePub(MI, ARM_INS_POP); + + printPredicateOperand(MI, 2, O); + if (Opcode == ARM_t2LDMIA_UPD) + SStream_concat0(O, ".w"); + + SStream_concat0(O, "\t"); + + // unlike LDM, POP only write to registers, so skip the 1st access code + MI->ac_idx = 1; + if (MI->csh->detail) { + MI->flat_insn->detail + ->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_read_count++; + MI->flat_insn->detail + ->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_write_count++; + } + + printRegisterList(MI, 4, O); + + return; + } + break; + + case ARM_LDR_POST_IMM: + if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) { + MCOperand *MO2 = MCInst_getOperand(MI, 4); + + if (getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) { + SStream_concat0(O, "pop"); + MCInst_setOpcodePub(MI, ARM_INS_POP); + printPredicateOperand(MI, 5, O); + SStream_concat0(O, "\t{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_WRITE; + MI->flat_insn->detail->arm.op_count++; + // this instruction implicitly read/write SP register + MI->flat_insn->detail + ->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_read_count++; + MI->flat_insn->detail + ->regs_write[MI->flat_insn->detail->regs_write_count] = + ARM_REG_SP; + MI->flat_insn->detail->regs_write_count++; + } + SStream_concat0(O, "}"); + return; + } + } + break; + + // A8.6.355 VPUSH + case ARM_VSTMSDB_UPD: + case ARM_VSTMDDB_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { + SStream_concat0(O, "vpush"); + MCInst_setOpcodePub(MI, ARM_INS_VPUSH); + printPredicateOperand(MI, 2, O); + SStream_concat0(O, "\t"); + printRegisterList(MI, 4, O); + return; + } + break; + + // A8.6.354 VPOP + case ARM_VLDMSIA_UPD: + case ARM_VLDMDIA_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { + SStream_concat0(O, "vpop"); + MCInst_setOpcodePub(MI, ARM_INS_VPOP); + printPredicateOperand(MI, 2, O); + SStream_concat0(O, "\t"); + printRegisterList(MI, 4, O); + return; + } + break; + + case ARM_tLDMIA: { + bool Writeback = true; + unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + unsigned i; + + for (i = 3; i < MCInst_getNumOperands(MI); ++i) { + if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg) + Writeback = false; + } + + SStream_concat0(O, "ldm"); + MCInst_setOpcodePub(MI, ARM_INS_LDM); + + printPredicateOperand(MI, 1, O); + SStream_concat0(O, "\t"); + printRegName(MI->csh, O, BaseReg); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = BaseReg; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ | CS_AC_WRITE; + MI->flat_insn->detail->arm.op_count++; + } + + if (Writeback) { + MI->writeback = true; + SStream_concat0(O, "!"); + } + + SStream_concat0(O, ", "); + printRegisterList(MI, 3, O); + return; + } + + // Combine 2 GPRs from disassember into a GPRPair to match with instr def. + // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, + // a single GPRPair reg operand is used in the .td file to replace the two + // GPRs. However, when decoding them, the two GRPs cannot be automatically + // expressed as a GPRPair, so we have to manually merge them. + // FIXME: We would really like to be able to tablegen'erate this. + case ARM_LDREXD: + case ARM_STREXD: + case ARM_LDAEXD: + case ARM_STLEXD: { + const MCRegisterClass *MRC = + MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID); + bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0)); + + if (MCRegisterClass_contains(MRC, Reg)) { + MCInst NewMI; + + MCInst_Init(&NewMI); + MCInst_setOpcode(&NewMI, Opcode); + + if (isStore) + MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0)); + + MCOperand_CreateReg0( + &NewMI, MCRegisterInfo_getMatchingSuperReg( + MRI, Reg, ARM_gsub_0, + MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID))); + + // Copy the rest operands into NewMI. + for (i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i) + MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i)); + + printInstruction(&NewMI, O); + return; + } + break; + } + + case ARM_TSB: + case ARM_t2TSB: + SStream_concat0(O, "tsb\tcsync"); + MCInst_setOpcodePub(MI, ARM_INS_TSB); + // TODO: add csync to operands[]? + return; + } + + MI->MRI = MRI; + + if (!printAliasInstr(MI, O)) { + printInstruction(MI, O); + } +} + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { + int32_t imm; + MCOperand *Op = MCInst_getOperand(MI, OpNo); + + if (MCOperand_isReg(Op)) { + unsigned Reg = MCOperand_getReg(Op); + + printRegName(MI->csh, O, Reg); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + if (MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count] + .mem.base == ARM_REG_INVALID) + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count] + .mem.base = Reg; + else + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count] + .mem.index = Reg; + } else { +#ifndef CAPSTONE_DIET + uint8_t access; +#endif + + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm.op_count++; + } + } + } else if (MCOperand_isImm(Op)) { + unsigned int opc = MCInst_getOpcode(MI); + + imm = (int32_t)MCOperand_getImm(Op); + + // relative branch only has relative offset, so we have to update it + // to reflect absolute address. + // Note: in ARM, PC is always 2 instructions ahead, so we have to + // add 8 in ARM mode, or 4 in Thumb mode + // printf(">> opcode: %u\n", MCInst_getOpcode(MI)); + if (ARM_rel_branch(MI->csh, opc)) { + uint32_t address; + + // only do this for relative branch + if (MI->csh->mode & CS_MODE_THUMB) { + address = (uint32_t)MI->address + 4; + if (ARM_blx_to_arm_mode(MI->csh, opc)) { + // here need to align down to the nearest 4-byte address +#define _ALIGN_DOWN(v, align_width) ((v / align_width) * align_width) + address = _ALIGN_DOWN(address, 4); #undef _ALIGN_DOWN - } - } else { - address = (uint32_t)MI->address + 8; - } - - imm += address; - printUInt32Bang(O, imm); - } else { - switch(MI->flat_insn->id) { - default: - if (MI->csh->imm_unsigned) - printUInt32Bang(O, imm); - else - printInt32Bang(O, imm); - break; - case ARM_INS_AND: - case ARM_INS_ORR: - case ARM_INS_EOR: - case ARM_INS_BIC: - case ARM_INS_MVN: - // do not print number in negative form - printUInt32Bang(O, imm); - break; - } - } - - if (MI->csh->detail) { - if (MI->csh->doing_mem) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm; - else { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; - MI->flat_insn->detail->arm.op_count++; - } - } - } -} - -static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - int32_t OffImm; - bool isSub; - SStream_concat0(O, "[pc, "); - - OffImm = (int32_t)MCOperand_getImm(MO1); - isSub = OffImm < 0; - - // Special value for #-0. All others are normal. - if (OffImm == INT32_MIN) - OffImm = 0; - - if (isSub) { - SStream_concat(O, "#-0x%x", -OffImm); - } else { - printUInt32Bang(O, OffImm); - } - - SStream_concat0(O, "]"); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.op_count++; - } + } + } else { + address = (uint32_t)MI->address + 8; + } + + imm += address; + printUInt32Bang(O, imm); + } else { + switch (MI->flat_insn->id) { + default: + if (MI->csh->imm_unsigned) + printUInt32Bang(O, imm); + else + printInt32Bang(O, imm); + break; + case ARM_INS_AND: + case ARM_INS_ORR: + case ARM_INS_EOR: + case ARM_INS_BIC: + case ARM_INS_MVN: + // do not print number in negative form + printUInt32Bang(O, imm); + break; + } + } + + if (MI->csh->detail) { + if (MI->csh->doing_mem) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = imm; + else { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = imm; + MI->flat_insn->detail->arm.op_count++; + } + } + } +} + +static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + int32_t OffImm; + bool isSub; + SStream_concat0(O, "[pc, "); + + OffImm = (int32_t)MCOperand_getImm(MO1); + isSub = OffImm < 0; + + // Special value for #-0. All others are normal. + if (OffImm == INT32_MIN) + OffImm = 0; + + if (isSub) { + SStream_concat(O, "#-0x%x", -OffImm); + } else { + printUInt32Bang(O, OffImm); + } + + SStream_concat0(O, "]"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_MEM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = ARM_REG_PC; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.scale = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = OffImm; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } } // so_reg is a 4-operand unit corresponding to register forms of the A5.1 @@ -943,222 +1138,245 @@ static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) // REG 0 0 - e.g. R5 // REG REG 0,SH_OPC - e.g. R5, ROR R3 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 -static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - MCOperand *MO3 = MCInst_getOperand(MI, OpNum + 2); - ARM_AM_ShiftOpc ShOpc; - - printRegName(MI->csh, O, MCOperand_getReg(MO1)); +static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + MCOperand *MO3 = MCInst_getOperand(MI, OpNum + 2); + ARM_AM_ShiftOpc ShOpc; - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1; - MI->flat_insn->detail->arm.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1; + MI->flat_insn->detail->arm.op_count++; + } - // Print the shift opc. - ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); - SStream_concat0(O, ", "); - SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); - if (ShOpc == ARM_AM_rrx) - return; + // Print the shift opc. + ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); + SStream_concat0(O, ", "); + SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); + if (ShOpc == ARM_AM_rrx) + return; - SStream_concat0(O, " "); + SStream_concat0(O, " "); - printRegName(MI->csh, O, MCOperand_getReg(MO2)); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2); + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.value = MCOperand_getReg(MO2); } -static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); +static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } - // Print the shift opc. - printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), - getSORegOffset((unsigned int)MCOperand_getImm(MO2))); + // Print the shift opc. + printRegImmShift(MI, O, + ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), + getSORegOffset((unsigned int)MCOperand_getImm(MO2))); } //===--------------------------------------------------------------------===// // Addressing Mode #2 //===--------------------------------------------------------------------===// -static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, Op); - MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); - MCOperand *MO3 = MCInst_getOperand(MI, Op + 2); - unsigned int imm3 = (unsigned int)MCOperand_getImm(MO3); - ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); - - SStream_concat0(O, "["); - set_mem_access(MI, true); +static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); + MCOperand *MO3 = MCInst_getOperand(MI, Op + 2); + unsigned int imm3 = (unsigned int)MCOperand_getImm(MO3); + ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); - } + SStream_concat0(O, "["); + set_mem_access(MI, true); - if (!MCOperand_getReg(MO2)) { - unsigned tmp = getAM2Offset(imm3); - if (tmp) { // Don't print +0. - subtracted = getAM2Op(imm3); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); + } - SStream_concat0(O, ", "); - if (tmp > HEX_THRESHOLD) - SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp); - else - SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op(imm3); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; - } - } + if (!MCOperand_getReg(MO2)) { + unsigned tmp = getAM2Offset(imm3); + if (tmp) { // Don't print +0. + subtracted = getAM2Op(imm3); + + SStream_concat0(O, ", "); + if (tmp > HEX_THRESHOLD) + SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp); + else + SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .shift.type = (arm_shifter)getAM2Op(imm3); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .shift.value = tmp; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .subtracted = subtracted == ARM_AM_sub; + } + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); + + return; + } - SStream_concat0(O, "]"); - set_mem_access(MI, false); + SStream_concat0(O, ", "); + SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = MCOperand_getReg(MO2); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .subtracted = subtracted == ARM_AM_sub; + } - return; - } + printRegImmShift(MI, O, getAM2ShiftOpc(imm3), getAM2Offset(imm3)); + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} - SStream_concat0(O, ", "); - SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); - printRegName(MI->csh, O, MCOperand_getReg(MO2)); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; - } +static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); - printRegImmShift(MI, O, getAM2ShiftOpc(imm3), getAM2Offset(imm3)); - SStream_concat0(O, "]"); - set_mem_access(MI, false); -} + SStream_concat0(O, "["); + set_mem_access(MI, true); -static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, Op); - MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); - - SStream_concat0(O, "["); - set_mem_access(MI, true); - - printRegName(MI->csh, O, MCOperand_getReg(MO1)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); - SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MO2)); + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = MCOperand_getReg(MO2); - SStream_concat0(O, "]"); - set_mem_access(MI, false); + SStream_concat0(O, "]"); + set_mem_access(MI, false); } -static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, Op); - MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); +static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); - SStream_concat0(O, "["); - set_mem_access(MI, true); + SStream_concat0(O, "["); + set_mem_access(MI, true); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); - SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MO2)); + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = MCOperand_getReg(MO2); - SStream_concat0(O, ", lsl #1]"); + SStream_concat0(O, ", lsl #1]"); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = 1; - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .shift.type = ARM_SFT_LSL; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .shift.value = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.lshift = 1; + } - set_mem_access(MI, false); + set_mem_access(MI, false); } -static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, Op); +static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, Op); - if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op, O); - return; - } + if (!MCOperand_isReg( + MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, Op, O); + return; + } -//#ifndef NDEBUG -// const MCOperand &MO3 = MI->getOperand(Op + 2); -// unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); -// assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op"); -//#endif + //#ifndef NDEBUG + // const MCOperand &MO3 = MI->getOperand(Op + 2); + // unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); + // assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index + // op"); + //#endif - printAM2PreOrOffsetIndexOp(MI, Op, O); + printAM2PreOrOffsetIndexOp(MI, Op, O); } -static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2)); - - if (!MCOperand_getReg(MO1)) { - unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2)); - if (ImmOffs > HEX_THRESHOLD) - SStream_concat(O, "#%s0x%x", - ARM_AM_getAddrOpcStr(subtracted), ImmOffs); - else - SStream_concat(O, "#%s%u", - ARM_AM_getAddrOpcStr(subtracted), ImmOffs); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; - MI->flat_insn->detail->arm.op_count++; - } - return; - } +static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2)); + + if (!MCOperand_getReg(MO1)) { + unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2)); + if (ImmOffs > HEX_THRESHOLD) + SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); + else + SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = ImmOffs; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .subtracted = subtracted == ARM_AM_sub; + MI->flat_insn->detail->arm.op_count++; + } + return; + } - SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); + SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; - MI->flat_insn->detail->arm.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .subtracted = subtracted == ARM_AM_sub; + MI->flat_insn->detail->arm.op_count++; + } - printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)), - getAM2Offset((unsigned int)MCOperand_getImm(MO2))); + printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)), + getAM2Offset((unsigned int)MCOperand_getImm(MO2))); } //===--------------------------------------------------------------------===// @@ -1166,2196 +1384,2488 @@ static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) //===--------------------------------------------------------------------===// static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, - bool AlwaysPrintImm0) -{ - MCOperand *MO1 = MCInst_getOperand(MI, Op); - MCOperand *MO2 = MCInst_getOperand(MI, Op+1); - MCOperand *MO3 = MCInst_getOperand(MI, Op+2); - ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3)); - unsigned ImmOffs; + bool AlwaysPrintImm0) { + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); + MCOperand *MO3 = MCInst_getOperand(MI, Op + 2); + ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3)); + unsigned ImmOffs; - SStream_concat0(O, "["); - set_mem_access(MI, true); + SStream_concat0(O, "["); + set_mem_access(MI, true); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); - if (MCOperand_getReg(MO2)) { - SStream_concat0(O, ", "); - SStream_concat0(O, ARM_AM_getAddrOpcStr(sign)); + if (MCOperand_getReg(MO2)) { + SStream_concat0(O, ", "); + SStream_concat0(O, ARM_AM_getAddrOpcStr(sign)); - printRegName(MI->csh, O, MCOperand_getReg(MO2)); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); - if (sign == ARM_AM_sub) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; - } - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = MCOperand_getReg(MO2); + if (sign == ARM_AM_sub) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.scale = -1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .subtracted = true; + } + } - SStream_concat0(O, "]"); - set_mem_access(MI, false); + SStream_concat0(O, "]"); + set_mem_access(MI, false); - return; - } + return; + } - // If the op is sub we have to print the immediate even if it is 0 - ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3)); + // If the op is sub we have to print the immediate even if it is 0 + ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3)); - if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) { - if (ImmOffs > HEX_THRESHOLD) - SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs); - else - SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs); - } + if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) { + if (ImmOffs > HEX_THRESHOLD) + SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs); + else + SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs); + } - if (MI->csh->detail) { - if (sign == ARM_AM_sub) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; - } else - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs; - } + if (MI->csh->detail) { + if (sign == ARM_AM_sub) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = -(int)ImmOffs; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .subtracted = true; + } else + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = (int)ImmOffs; + } - SStream_concat0(O, "]"); - set_mem_access(MI, false); + SStream_concat0(O, "]"); + set_mem_access(MI, false); } static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O, - bool AlwaysPrintImm0) -{ - MCOperand *MO1 = MCInst_getOperand(MI, Op); - - if (!MCOperand_isReg(MO1)) { // For label symbolic references. - printOperand(MI, Op, O); - return; - } - - printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); -} - -static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2)); - unsigned ImmOffs; - - if (MCOperand_getReg(MO1)) { - SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; - MI->flat_insn->detail->arm.op_count++; - } - - return; - } - - ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2)); - if (ImmOffs > HEX_THRESHOLD) - SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); - else - SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); - unsigned Imm = (unsigned int)MCOperand_getImm(MO); - - if ((Imm & 0xff) > HEX_THRESHOLD) - SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); - else - SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff; - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - - SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-")); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); - int Imm = (int)MCOperand_getImm(MO); - - if (((Imm & 0xff) << 2) > HEX_THRESHOLD) { - SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); - } else { - SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); - } - - if (MI->csh->detail) { - int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((Imm & 0xff) << 2); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; - MI->flat_insn->detail->arm.op_count++; - } + bool AlwaysPrintImm0) { + MCOperand *MO1 = MCInst_getOperand(MI, Op); + + if (!MCOperand_isReg(MO1)) { // For label symbolic references. + printOperand(MI, Op, O); + return; + } + + printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); +} + +static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2)); + unsigned ImmOffs; + + if (MCOperand_getReg(MO1)) { + SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .subtracted = subtracted == ARM_AM_sub; + MI->flat_insn->detail->arm.op_count++; + } + + return; + } + + ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2)); + if (ImmOffs > HEX_THRESHOLD) + SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); + else + SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = ImmOffs; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .subtracted = subtracted == ARM_AM_sub; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); + unsigned Imm = (unsigned int)MCOperand_getImm(MO); + + if ((Imm & 0xff) > HEX_THRESHOLD) + SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); + else + SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = Imm & 0xff; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + + SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-")); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); + int Imm = (int)MCOperand_getImm(MO); + + if (((Imm & 0xff) << 2) > HEX_THRESHOLD) { + SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); + } else { + SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); + } + + if (MI->csh->detail) { + int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((Imm & 0xff) << 2); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = v; + MI->flat_insn->detail->arm.op_count++; + } } static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, - bool AlwaysPrintImm0) -{ - unsigned ImmOffs; - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - ARM_AM_AddrOpc Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2)); - - if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, OpNum, O); - return; - } - - SStream_concat0(O, "["); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - } - - ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2)); - if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) { - if (ImmOffs * 4 > HEX_THRESHOLD) - SStream_concat(O, ", #%s0x%x", - ARM_AM_getAddrOpcStr(Op), - ImmOffs * 4); - else - SStream_concat(O, ", #%s%u", - ARM_AM_getAddrOpcStr(Op), - ImmOffs * 4); - - if (MI->csh->detail) { - if (Op) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4; - else - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4; - } - } - - SStream_concat0(O, "]"); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.op_count++; - } + bool AlwaysPrintImm0) { + unsigned ImmOffs; + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + ARM_AM_AddrOpc Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2)); + + if (!MCOperand_isReg( + MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, OpNum, O); + return; + } + + SStream_concat0(O, "["); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_MEM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.scale = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = 0; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + } + + ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2)); + if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) { + if (ImmOffs * 4 > HEX_THRESHOLD) + SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(Op), ImmOffs * 4); + else + SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(Op), ImmOffs * 4); + + if (MI->csh->detail) { + if (Op) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = ImmOffs * 4; + else + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = -(int)ImmOffs * 4; + } + } + + SStream_concat0(O, "]"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.op_count++; + } } static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, - bool AlwaysPrintImm0) -{ + bool AlwaysPrintImm0) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); unsigned ImmOffs = getAM5FP16Offset((unsigned)MCOperand_getImm(MO2)); unsigned Op = getAM5FP16Op((unsigned)MCOperand_getImm(MO2)); - if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, OpNum, O); - return; + if (!MCOperand_isReg( + MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, OpNum, O); + return; } SStream_concat0(O, "["); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_MEM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.scale = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = 0; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; } if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) { - if (ImmOffs * 2 > HEX_THRESHOLD) - SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2); - else - SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2); + if (ImmOffs * 2 > HEX_THRESHOLD) + SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2); + else + SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2); + + if (MI->csh->detail) { + if (Op) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = ImmOffs * 2; + else + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = -(int)ImmOffs * 2; + } + } - if (MI->csh->detail) { - if (Op) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 2; - else - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 2; - } + SStream_concat0(O, "]"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.op_count++; } +} + +static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + unsigned tmp; + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); + + tmp = (unsigned int)MCOperand_getImm(MO2); + if (tmp) { + if (tmp << 3 > HEX_THRESHOLD) + SStream_concat(O, ":0x%x", (tmp << 3)); + else + SStream_concat(O, ":%u", (tmp << 3)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = tmp << 3; + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); + + if (MCOperand_getReg(MO) == 0) { + MI->writeback = true; + SStream_concat0(O, "!"); + } else { + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MO); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + } +} + +static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); + uint32_t v = ~(uint32_t)MCOperand_getImm(MO); + int32_t lsb = CountTrailingZeros_32(v); + int32_t width = (32 - CountLeadingZeros_32(v)) - lsb; + + // assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); + printUInt32Bang(O, lsb); + + if (width > HEX_THRESHOLD) + SStream_concat(O, ", #0x%x", width); + else + SStream_concat(O, ", #%u", width); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = lsb; + MI->flat_insn->detail->arm.op_count++; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = width; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, ARM_MB_MemBOptToString( + val, ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1); + } +} + +static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val)); +} + +static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, ARM_TSB_TraceSyncBOptToString(val)); + // TODO: add to detail? +} + +static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned ShiftOp = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + bool isASR = (ShiftOp & (1 << 5)) != 0; + unsigned Amt = ShiftOp & 0x1f; + + if (isASR) { + unsigned tmp = Amt == 0 ? 32 : Amt; + if (tmp > HEX_THRESHOLD) + SStream_concat(O, ", asr #0x%x", tmp); + else + SStream_concat(O, ", asr #%u", tmp); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.type = ARM_SFT_ASR; + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.value = tmp; + } + } else if (Amt) { + if (Amt > HEX_THRESHOLD) + SStream_concat(O, ", lsl #0x%x", Amt); + else + SStream_concat(O, ", lsl #%u", Amt); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.type = ARM_SFT_LSL; + MI->flat_insn->detail->arm + .operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.value = Amt; + } + } +} + +static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + if (Imm == 0) + return; + + // assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); + if (Imm > HEX_THRESHOLD) + SStream_concat(O, ", lsl #0x%x", Imm); + else + SStream_concat(O, ", lsl #%u", Imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.type = ARM_SFT_LSL; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.value = Imm; + } +} + +static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + // A shift amount of 32 is encoded as 0. + if (Imm == 0) + Imm = 32; + + // assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); + if (Imm > HEX_THRESHOLD) + SStream_concat(O, ", asr #0x%x", Imm); + else + SStream_concat(O, ", asr #%u", Imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.type = ARM_SFT_ASR; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.value = Imm; + } +} + +// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst +// struct +static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned i, e; +#ifndef CAPSTONE_DIET + uint8_t access = 0; +#endif + + SStream_concat0(O, "{"); + +#ifndef CAPSTONE_DIET + if (MI->csh->detail) { + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + } +#endif + + for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) { + if (i != OpNum) + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, i)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + } + + SStream_concat0(O, "}"); + +#ifndef CAPSTONE_DIET + if (MI->csh->detail) { + MI->ac_idx++; + } +#endif +} + +static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + + printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0); + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1)); if (MI->csh->detail) { - MI->flat_insn->detail->arm.op_count++; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1); + MI->flat_insn->detail->arm.op_count++; } } -static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - unsigned tmp; - - SStream_concat0(O, "["); - set_mem_access(MI, true); - - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); +// SETEND BE/LE +static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + + if (MCOperand_getImm(Op)) { + SStream_concat0(O, "be"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_SETEND; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .setend = ARM_SETEND_BE; + MI->flat_insn->detail->arm.op_count++; + } + } else { + SStream_concat0(O, "le"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_SETEND; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .setend = ARM_SETEND_LE; + MI->flat_insn->detail->arm.op_count++; + } + } +} - tmp = (unsigned int)MCOperand_getImm(MO2); - if (tmp) { - if (tmp << 3 > HEX_THRESHOLD) - SStream_concat(O, ":0x%x", (tmp << 3)); - else - SStream_concat(O, ":%u", (tmp << 3)); +static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned int mode = (unsigned int)MCOperand_getImm(Op); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3; - } + SStream_concat0(O, ARM_PROC_IModToString(mode)); - SStream_concat0(O, "]"); - set_mem_access(MI, false); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.cps_mode = mode; + } } -static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); +static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned IFlags = (unsigned int)MCOperand_getImm(Op); + int i; - SStream_concat0(O, "["); - set_mem_access(MI, true); + for (i = 2; i >= 0; --i) + if (IFlags & (1 << i)) { + SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i)); + } - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + if (IFlags == 0) { + SStream_concat0(O, "none"); + IFlags = ARM_CPSFLAG_NONE; + } - SStream_concat0(O, "]"); - set_mem_access(MI, false); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.cps_flag = IFlags; + } } -static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); +static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4; + unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf; + unsigned reg; + + if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) { + const MClassSysReg *TheReg; + unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF; // 12-bit SYMm + unsigned Opcode = MCInst_getOpcode(MI); + + if (Opcode == ARM_t2MSR_M && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) { + TheReg = lookupMClassSysRegBy12bitSYSmValue(SYSm); + if (TheReg && MClassSysReg_isInRequiredFeatures(TheReg, ARM_FeatureDSP)) { + SStream_concat0(O, TheReg->Name); + ARM_addSysReg(MI, TheReg->sysreg); + return; + } + } + + // Handle the basic 8-bit mask. + SYSm &= 0xff; + if (Opcode == ARM_t2MSR_M && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) { + // ARMv7-M deprecates using MSR APSR without a _ qualifier as an + // alias for MSR APSR_nzcvq. + TheReg = lookupMClassSysRegAPSRNonDeprecated(SYSm); + if (TheReg) { + SStream_concat0(O, TheReg->Name); + ARM_addSysReg(MI, TheReg->sysreg); + return; + } + } + + TheReg = lookupMClassSysRegBy8bitSYSmValue(SYSm); + if (TheReg) { + SStream_concat0(O, TheReg->Name); + ARM_addSysReg(MI, TheReg->sysreg); + return; + } + + if (SYSm > HEX_THRESHOLD) + SStream_concat(O, "%x", SYSm); + else + SStream_concat(O, "%u", SYSm); + + if (MI->csh->detail) + MCOperand_CreateImm0(MI, SYSm); + + return; + } - if (MCOperand_getReg(MO) == 0) { - MI->writeback = true; - SStream_concat0(O, "!"); - } else { - SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MO)); + // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as + // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. + if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { + SStream_concat0(O, "apsr_"); + switch (Mask) { + default: // llvm_unreachable("Unexpected mask value!"); + case 4: + SStream_concat0(O, "g"); + ARM_addSysReg(MI, ARM_SYSREG_APSR_G); + return; + case 8: + SStream_concat0(O, "nzcvq"); + ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); + return; + case 12: + SStream_concat0(O, "nzcvqg"); + ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); + return; + } + } - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO); - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.op_count++; - } - } -} + if (SpecRegRBit) { + SStream_concat0(O, "spsr"); + } else { + SStream_concat0(O, "cpsr"); + } -static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); - uint32_t v = ~(uint32_t)MCOperand_getImm(MO); - int32_t lsb = CountTrailingZeros_32(v); - int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; + reg = 0; + if (Mask) { + SStream_concat0(O, "_"); - //assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); - printUInt32Bang(O, lsb); + if (Mask & 8) { + SStream_concat0(O, "f"); + reg += ARM_SYSREG_SPSR_F; + } - if (width > HEX_THRESHOLD) - SStream_concat(O, ", #0x%x", width); - else - SStream_concat(O, ", #%u", width); + if (Mask & 4) { + SStream_concat0(O, "s"); + reg += ARM_SYSREG_SPSR_S; + } - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb; - MI->flat_insn->detail->arm.op_count++; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width; - MI->flat_insn->detail->arm.op_count++; - } -} + if (Mask & 2) { + SStream_concat0(O, "x"); + reg += ARM_SYSREG_SPSR_X; + } -static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - SStream_concat0(O, ARM_MB_MemBOptToString(val, - ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops))); + if (Mask & 1) { + SStream_concat0(O, "c"); + reg += ARM_SYSREG_SPSR_C; + } - if (MI->csh->detail) { - MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1); - } + ARM_addSysReg(MI, reg); + } } -static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val)); -} +static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { + uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + const BankedReg *TheReg = lookupBankedRegByEncoding(Banked); -static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - SStream_concat0(O, ARM_TSB_TraceSyncBOptToString(val)); - // TODO: add to detail? + SStream_concat0(O, TheReg->Name); + ARM_addSysReg(MI, TheReg->sysreg); } -static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - bool isASR = (ShiftOp & (1 << 5)) != 0; - unsigned Amt = ShiftOp & 0x1f; - - if (isASR) { - unsigned tmp = Amt == 0 ? 32 : Amt; - if (tmp > HEX_THRESHOLD) - SStream_concat(O, ", asr #0x%x", tmp); - else - SStream_concat(O, ", asr #%u", tmp); +static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { + ARMCC_CondCodes CC = + (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // Handle the undefined 15 CC value here for printing so we don't abort(). + if ((unsigned)CC == 15) { + SStream_concat0(O, ""); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; - } - } else if (Amt) { - if (Amt > HEX_THRESHOLD) - SStream_concat(O, ", lsl #0x%x", Amt); - else - SStream_concat(O, ", lsl #%u", Amt); + if (MI->csh->detail) + MI->flat_insn->detail->arm.cc = ARM_CC_INVALID; + } else { + if (CC != ARMCC_AL) { + SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); + } - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt; - } - } + if (MI->csh->detail) + MI->flat_insn->detail->arm.cc = CC + 1; + } } -static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); +static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + ARMCC_CondCodes CC = + (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); - if (Imm == 0) - return; + if (MI->csh->detail) + MI->flat_insn->detail->arm.cc = CC + 1; +} - //assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); - if (Imm > HEX_THRESHOLD) - SStream_concat(O, ", lsl #0x%x", Imm); - else - SStream_concat(O, ", lsl #%u", Imm); +static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O) { + if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) { + // assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR && + // "Expect ARM CPSR register!"); + SStream_concat0(O, "s"); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; - } + if (MI->csh->detail) + MI->flat_insn->detail->arm.update_flags = true; + } } -static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - - // A shift amount of 32 is encoded as 0. - if (Imm == 0) - Imm = 32; +static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - //assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); - if (Imm > HEX_THRESHOLD) - SStream_concat(O, ", asr #0x%x", Imm); - else - SStream_concat(O, ", asr #%u", Imm); + printUInt32(O, tmp); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; - } + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->arm.op_count--; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .neon_lane = (int8_t)tmp; + MI->ac_idx--; // consecutive operands share the same access right + } else { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } + } } -// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct -static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned i, e; -#ifndef CAPSTONE_DIET - uint8_t access = 0; -#endif +static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - SStream_concat0(O, "{"); + SStream_concat(O, "p%u", imm); -#ifndef CAPSTONE_DIET - if (MI->csh->detail) { - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - } -#endif + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_PIMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = imm; + MI->flat_insn->detail->arm.op_count++; + } +} - for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) { - if (i != OpNum) - SStream_concat0(O, ", "); +static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i))); + SStream_concat(O, "c%u", imm); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i)); -#ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; -#endif - MI->flat_insn->detail->arm.op_count++; - } - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_CIMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = imm; + MI->flat_insn->detail->arm.op_count++; + } +} - SStream_concat0(O, "}"); +static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + if (tmp > HEX_THRESHOLD) + SStream_concat(O, "{0x%x}", tmp); + else + SStream_concat(O, "{%u}", tmp); -#ifndef CAPSTONE_DIET - if (MI->csh->detail) { - MI->ac_idx++; - } -#endif + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, + unsigned scale) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); + + int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale; + + if (OffImm == INT32_MIN) { + SStream_concat0(O, "#-0"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = 0; + MI->flat_insn->detail->arm.op_count++; + } + } else { + if (OffImm < 0) + SStream_concat(O, "#-0x%x", -OffImm); + else { + if (OffImm > HEX_THRESHOLD) + SStream_concat(O, "#0x%x", OffImm); + else + SStream_concat(O, "#%u", OffImm); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = OffImm; + MI->flat_insn->detail->arm.op_count++; + } + } } -static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned tmp = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4; - printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0)); + printUInt32Bang(O, tmp); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0); - MI->flat_insn->detail->arm.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } +} - SStream_concat0(O, ", "); +static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned tmp = Imm == 0 ? 32 : Imm; - printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1)); + printUInt32Bang(O, tmp); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1); - MI->flat_insn->detail->arm.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } } -// SETEND BE/LE -static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - - if (MCOperand_getImm(Op)) { - SStream_concat0(O, "be"); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE; - MI->flat_insn->detail->arm.op_count++; - } - } else { - SStream_concat0(O, "le"); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE; - MI->flat_insn->detail->arm.op_count++; - } - } -} - -static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - unsigned int mode = (unsigned int)MCOperand_getImm(Op); - - SStream_concat0(O, ARM_PROC_IModToString(mode)); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.cps_mode = mode; - } -} - -static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - unsigned IFlags = (unsigned int)MCOperand_getImm(Op); - int i; - - for (i = 2; i >= 0; --i) - if (IFlags & (1 << i)) { - SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i)); - } - - if (IFlags == 0) { - SStream_concat0(O, "none"); - IFlags = ARM_CPSFLAG_NONE; - } - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.cps_flag = IFlags; - } -} - -static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4; - unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf; - unsigned reg; - - if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) { - const MClassSysReg *TheReg; - unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF; // 12-bit SYMm - unsigned Opcode = MCInst_getOpcode(MI); - - if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) { - TheReg = lookupMClassSysRegBy12bitSYSmValue(SYSm); - if (TheReg && MClassSysReg_isInRequiredFeatures(TheReg, ARM_FeatureDSP)) { - SStream_concat0(O, TheReg->Name); - ARM_addSysReg(MI, TheReg->sysreg); - return; - } - } - - // Handle the basic 8-bit mask. - SYSm &= 0xff; - if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) { - // ARMv7-M deprecates using MSR APSR without a _ qualifier as an - // alias for MSR APSR_nzcvq. - TheReg = lookupMClassSysRegAPSRNonDeprecated(SYSm); - if (TheReg) { - SStream_concat0(O, TheReg->Name); - ARM_addSysReg(MI, TheReg->sysreg); - return; - } - } - - TheReg = lookupMClassSysRegBy8bitSYSmValue(SYSm); - if (TheReg) { - SStream_concat0(O, TheReg->Name); - ARM_addSysReg(MI, TheReg->sysreg); - return; - } - - if (SYSm > HEX_THRESHOLD) - SStream_concat(O, "%x", SYSm); - else - SStream_concat(O, "%u", SYSm); - - if (MI->csh->detail) - MCOperand_CreateImm0(MI, SYSm); - - return; - } - - // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as - // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. - if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { - SStream_concat0(O, "apsr_"); - switch (Mask) { - default: // llvm_unreachable("Unexpected mask value!"); - case 4: SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return; - case 8: SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return; - case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return; - } - } - - if (SpecRegRBit) { - SStream_concat0(O, "spsr"); - } else { - SStream_concat0(O, "cpsr"); - } - - reg = 0; - if (Mask) { - SStream_concat0(O, "_"); - - if (Mask & 8) { - SStream_concat0(O, "f"); - reg += ARM_SYSREG_SPSR_F; - } - - if (Mask & 4) { - SStream_concat0(O, "s"); - reg += ARM_SYSREG_SPSR_S; - } - - if (Mask & 2) { - SStream_concat0(O, "x"); - reg += ARM_SYSREG_SPSR_X; - } - - if (Mask & 1) { - SStream_concat0(O, "c"); - reg += ARM_SYSREG_SPSR_C; - } - - ARM_addSysReg(MI, reg); - } -} - -static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - const BankedReg *TheReg = lookupBankedRegByEncoding(Banked); - - SStream_concat0(O, TheReg->Name); - ARM_addSysReg(MI, TheReg->sysreg); -} - -static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // Handle the undefined 15 CC value here for printing so we don't abort(). - if ((unsigned)CC == 15) { - SStream_concat0(O, ""); - - if (MI->csh->detail) - MI->flat_insn->detail->arm.cc = ARM_CC_INVALID; - } else { - if (CC != ARMCC_AL) { - SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); - } - - if (MI->csh->detail) - MI->flat_insn->detail->arm.cc = CC + 1; - } -} - -static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); - - if (MI->csh->detail) - MI->flat_insn->detail->arm.cc = CC + 1; -} - -static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) { - //assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR && - // "Expect ARM CPSR register!"); - SStream_concat0(O, "s"); - - if (MI->csh->detail) - MI->flat_insn->detail->arm.update_flags = true; - } -} - -static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - - printUInt32(O, tmp); - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->arm.op_count--; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = (int8_t)tmp; - MI->ac_idx--; // consecutive operands share the same access right - } else { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; - MI->flat_insn->detail->arm.op_count++; - } - } -} +static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O) { + // (3 - the number of trailing zeros) is the number of then / else. + unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned Firstcond = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum - 1)); + unsigned CondBit0 = Firstcond & 1; + unsigned NumTZ = CountTrailingZeros_32(Mask); + // assert(NumTZ <= 3 && "Invalid IT mask!"); + unsigned Pos, e; + + for (Pos = 3, e = NumTZ; Pos > e; --Pos) { + bool T = ((Mask >> Pos) & 1) == CondBit0; + if (T) + SStream_concat0(O, "e"); + else + SStream_concat0(O, "t"); + // TODO: detail for this t/e + } +} -static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); +static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); + unsigned RegNum; - SStream_concat(O, "p%u", imm); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - - SStream_concat(O, "c%u", imm); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - if (tmp > HEX_THRESHOLD) - SStream_concat(O, "{0x%x}", tmp); - else - SStream_concat(O, "{%u}", tmp); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); - - int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale; - - if (OffImm == INT32_MIN) { - SStream_concat0(O, "#-0"); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; - MI->flat_insn->detail->arm.op_count++; - } - } else { - if (OffImm < 0) - SStream_concat(O, "#-0x%x", -OffImm); - else { - if (OffImm > HEX_THRESHOLD) - SStream_concat(O, "#0x%x", OffImm); - else - SStream_concat(O, "#%u", OffImm); - } + if (!MCOperand_isReg( + MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, Op, O); + return; + } - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; - MI->flat_insn->detail->arm.op_count++; - } - } -} - -static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4; - - printUInt32Bang(O, tmp); + SStream_concat0(O, "["); + set_mem_access(MI, true); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - unsigned tmp = Imm == 0 ? 32 : Imm; - - printUInt32Bang(O, tmp); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; - MI->flat_insn->detail->arm.op_count++; - } -} + printRegName(MI->csh, O, MCOperand_getReg(MO1)); -static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O) -{ - // (3 - the number of trailing zeros) is the number of then / else. - unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum - 1)); - unsigned CondBit0 = Firstcond & 1; - unsigned NumTZ = CountTrailingZeros_32(Mask); - //assert(NumTZ <= 3 && "Invalid IT mask!"); - unsigned Pos, e; + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); - for (Pos = 3, e = NumTZ; Pos > e; --Pos) { - bool T = ((Mask >> Pos) & 1) == CondBit0; - if (T) - SStream_concat0(O, "t"); - else - SStream_concat0(O, "e"); - // TODO: detail for this t/e - } -} - -static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, Op); - MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); - unsigned RegNum; - - if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op, O); - return; - } - - SStream_concat0(O, "["); - set_mem_access(MI, true); + RegNum = MCOperand_getReg(MO2); + if (RegNum) { + SStream_concat0(O, ", "); + printRegName(MI->csh, O, RegNum); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = RegNum; + } - RegNum = MCOperand_getReg(MO2); - if (RegNum) { - SStream_concat0(O, ", "); - printRegName(MI->csh, O, RegNum); - - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum; - } - - SStream_concat0(O, "]"); - set_mem_access(MI, false); + SStream_concat0(O, "]"); + set_mem_access(MI, false); } static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O, - unsigned Scale) -{ - MCOperand *MO1 = MCInst_getOperand(MI, Op); - MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); - unsigned ImmOffs, tmp; - - if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op, O); - return; - } + unsigned Scale) { + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); + unsigned ImmOffs, tmp; + + if (!MCOperand_isReg( + MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, Op, O); + return; + } - SStream_concat0(O, "["); - set_mem_access(MI, true); + SStream_concat0(O, "["); + set_mem_access(MI, true); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); - ImmOffs = (unsigned int)MCOperand_getImm(MO2); - if (ImmOffs) { - tmp = ImmOffs * Scale; - SStream_concat0(O, ", "); - printUInt32Bang(O, tmp); + ImmOffs = (unsigned int)MCOperand_getImm(MO2); + if (ImmOffs) { + tmp = ImmOffs * Scale; + SStream_concat0(O, ", "); + printUInt32Bang(O, tmp); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; - } + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = tmp; + } - SStream_concat0(O, "]"); - set_mem_access(MI, false); + SStream_concat0(O, "]"); + set_mem_access(MI, false); } -static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O) -{ - printThumbAddrModeImm5SOperand(MI, Op, O, 1); +static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, + SStream *O) { + printThumbAddrModeImm5SOperand(MI, Op, O, 1); } -static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O) -{ - printThumbAddrModeImm5SOperand(MI, Op, O, 2); +static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, + SStream *O) { + printThumbAddrModeImm5SOperand(MI, Op, O, 2); } -static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O) -{ - printThumbAddrModeImm5SOperand(MI, Op, O, 4); +static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, + SStream *O) { + printThumbAddrModeImm5SOperand(MI, Op, O, 4); } -static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O) -{ - printThumbAddrModeImm5SOperand(MI, Op, O, 4); +static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O) { + printThumbAddrModeImm5SOperand(MI, Op, O, 4); } // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 // register with shift forms. // REG 0 0 - e.g. R5 // REG IMM, SH_OPC - e.g. R5, LSL #3 -static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - unsigned Reg = MCOperand_getReg(MO1); - - printRegName(MI->csh, O, Reg); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; - MI->flat_insn->detail->arm.op_count++; - } - - // Print the shift opc. - //assert(MO2.isImm() && "Not a valid t2_so_reg value!"); - printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), - getSORegOffset((unsigned int)MCOperand_getImm(MO2))); -} - -static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, - SStream *O, bool AlwaysPrintImm0) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); - int32_t OffImm; - bool isSub; - - if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, OpNum, O); - return; - } - - SStream_concat0(O, "["); - set_mem_access(MI, true); - - printRegName(MI->csh, O, MCOperand_getReg(MO1)); - - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); - - OffImm = (int32_t)MCOperand_getImm(MO2); - isSub = OffImm < 0; - - // Special value for #-0. All others are normal. - if (OffImm == INT32_MIN) - OffImm = 0; - - if (isSub) { - if (OffImm < -HEX_THRESHOLD) - SStream_concat(O, ", #-0x%x", -OffImm); - else - SStream_concat(O, ", #-%u", -OffImm); - } else if (AlwaysPrintImm0 || OffImm > 0) { - if (OffImm >= 0) { - if (OffImm > HEX_THRESHOLD) - SStream_concat(O, ", #0x%x", OffImm); - else - SStream_concat(O, ", #%u", OffImm); - } else { - if (OffImm < -HEX_THRESHOLD) - SStream_concat(O, ", #-0x%x", -OffImm); - else - SStream_concat(O, ", #-%u", -OffImm); - } - } - - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; - - SStream_concat0(O, "]"); - set_mem_access(MI, false); +static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + unsigned Reg = MCOperand_getReg(MO1); + + printRegName(MI->csh, O, Reg); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + + // Print the shift opc. + // assert(MO2.isImm() && "Not a valid t2_so_reg value!"); + printRegImmShift(MI, O, + ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), + getSORegOffset((unsigned int)MCOperand_getImm(MO2))); +} + +static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool AlwaysPrintImm0) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + int32_t OffImm; + bool isSub; + + if (!MCOperand_isReg( + MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, OpNum, O); + return; + } + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); + + OffImm = (int32_t)MCOperand_getImm(MO2); + isSub = OffImm < 0; + + // Special value for #-0. All others are normal. + if (OffImm == INT32_MIN) + OffImm = 0; + + if (isSub) { + if (OffImm < -HEX_THRESHOLD) + SStream_concat(O, ", #-0x%x", -OffImm); + else + SStream_concat(O, ", #-%u", -OffImm); + } else if (AlwaysPrintImm0 || OffImm > 0) { + if (OffImm >= 0) { + if (OffImm > HEX_THRESHOLD) + SStream_concat(O, ", #0x%x", OffImm); + else + SStream_concat(O, ", #%u", OffImm); + } else { + if (OffImm < -HEX_THRESHOLD) + SStream_concat(O, ", #-0x%x", -OffImm); + else + SStream_concat(O, ", #-%u", -OffImm); + } + } + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = OffImm; + + SStream_concat0(O, "]"); + set_mem_access(MI, false); } static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, - bool AlwaysPrintImm0) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); - int32_t OffImm; - bool isSub; + bool AlwaysPrintImm0) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + int32_t OffImm; + bool isSub; - SStream_concat0(O, "["); - set_mem_access(MI, true); + SStream_concat0(O, "["); + set_mem_access(MI, true); - printRegName(MI->csh, O, MCOperand_getReg(MO1)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); - OffImm = (int32_t)MCOperand_getImm(MO2); - isSub = OffImm < 0; + OffImm = (int32_t)MCOperand_getImm(MO2); + isSub = OffImm < 0; - // Don't print +0. - if (OffImm == INT32_MIN) - OffImm = 0; + // Don't print +0. + if (OffImm == INT32_MIN) + OffImm = 0; - if (isSub) - SStream_concat(O, ", #-0x%x", -OffImm); - else if (AlwaysPrintImm0 || OffImm > 0) { - if (OffImm > HEX_THRESHOLD) - SStream_concat(O, ", #0x%x", OffImm); - else - SStream_concat(O, ", #%u", OffImm); - } + if (isSub) + SStream_concat(O, ", #-0x%x", -OffImm); + else if (AlwaysPrintImm0 || OffImm > 0) { + if (OffImm > HEX_THRESHOLD) + SStream_concat(O, ", #0x%x", OffImm); + else + SStream_concat(O, ", #%u", OffImm); + } - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = OffImm; - SStream_concat0(O, "]"); - set_mem_access(MI, false); + SStream_concat0(O, "]"); + set_mem_access(MI, false); } -static void printT2AddrModeImm8s4Operand(MCInst *MI, - unsigned OpNum, SStream *O, bool AlwaysPrintImm0) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - int32_t OffImm; - bool isSub; +static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool AlwaysPrintImm0) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + int32_t OffImm; + bool isSub; + + if (!MCOperand_isReg(MO1)) { // For label symbolic references. + printOperand(MI, OpNum, O); + return; + } + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); + + OffImm = (int32_t)MCOperand_getImm(MO2); + isSub = OffImm < 0; + + // assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); - if (!MCOperand_isReg(MO1)) { // For label symbolic references. - printOperand(MI, OpNum, O); - return; - } + // Don't print +0. + if (OffImm == INT32_MIN) + OffImm = 0; - SStream_concat0(O, "["); - set_mem_access(MI, true); + if (isSub) { + SStream_concat(O, ", #-0x%x", -OffImm); + } else if (AlwaysPrintImm0 || OffImm > 0) { + if (OffImm > HEX_THRESHOLD) + SStream_concat(O, ", #0x%x", OffImm); + else + SStream_concat(O, ", #%u", OffImm); + } + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = OffImm; + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} - printRegName(MI->csh, O, MCOperand_getReg(MO1)); +static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, + SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + unsigned tmp; - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + SStream_concat0(O, "["); + set_mem_access(MI, true); - OffImm = (int32_t)MCOperand_getImm(MO2); - isSub = OffImm < 0; + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); - - // Don't print +0. - if (OffImm == INT32_MIN) - OffImm = 0; + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); - if (isSub) { - SStream_concat(O, ", #-0x%x", -OffImm); - } else if (AlwaysPrintImm0 || OffImm > 0) { - if (OffImm > HEX_THRESHOLD) - SStream_concat(O, ", #0x%x", OffImm); - else - SStream_concat(O, ", #%u", OffImm); - } + if (MCOperand_getImm(MO2)) { + SStream_concat0(O, ", "); + tmp = (unsigned int)MCOperand_getImm(MO2) * 4; + printUInt32Bang(O, tmp); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.disp = tmp; + } - SStream_concat0(O, "]"); - set_mem_access(MI, false); + SStream_concat0(O, "]"); + set_mem_access(MI, false); } -static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); - unsigned tmp; +static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + int32_t OffImm = (int32_t)MCOperand_getImm(MO1); + + SStream_concat0(O, ", "); + if (OffImm == INT32_MIN) { + SStream_concat0(O, "#-0"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = 0; + MI->flat_insn->detail->arm.op_count++; + } + } else { + printInt32Bang(O, OffImm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = OffImm; + MI->flat_insn->detail->arm.op_count++; + } + } +} - SStream_concat0(O, "["); - set_mem_access(MI, true); +static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + int32_t OffImm = (int32_t)MCOperand_getImm(MO1); + + // assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); + + SStream_concat0(O, ", "); + + if (OffImm == INT32_MIN) { + SStream_concat0(O, "#-0"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = 0; + MI->flat_insn->detail->arm.op_count++; + } + } else { + printInt32Bang(O, OffImm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = OffImm; + MI->flat_insn->detail->arm.op_count++; + } + } +} - printRegName(MI->csh, O, MCOperand_getReg(MO1)); +static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + MCOperand *MO3 = MCInst_getOperand(MI, OpNum + 2); + unsigned ShAmt; - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + SStream_concat0(O, "["); + set_mem_access(MI, true); - if (MCOperand_getImm(MO2)) { - SStream_concat0(O, ", "); - tmp = (unsigned int)MCOperand_getImm(MO2) * 4; - printUInt32Bang(O, tmp); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; - } + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.base = MCOperand_getReg(MO1); + + // assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store + // address!"); + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .mem.index = MCOperand_getReg(MO2); + + ShAmt = (unsigned int)MCOperand_getImm(MO3); + if (ShAmt) { + // assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); + SStream_concat0(O, ", lsl "); + SStream_concat(O, "#%u", ShAmt); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .shift.type = ARM_SFT_LSL; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .shift.value = ShAmt; + } + } - SStream_concat0(O, "]"); - set_mem_access(MI, false); + SStream_concat0(O, "]"); + set_mem_access(MI, false); } -static void printT2AddrModeImm8OffsetOperand(MCInst *MI, - unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - int32_t OffImm = (int32_t)MCOperand_getImm(MO1); +static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); + +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + SStream_concat(O, "#"); +#else + SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO))); +#endif + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_FP; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO)); + MI->flat_insn->detail->arm.op_count++; + } +} - SStream_concat0(O, ", "); - if (OffImm == INT32_MIN) { - SStream_concat0(O, "#-0"); +static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned EncodedImm = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned EltBits; + uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; - MI->flat_insn->detail->arm.op_count++; - } - } else { - printInt32Bang(O, OffImm); + if (Val > HEX_THRESHOLD) + SStream_concat(O, "#0x%" PRIx64, Val); + else + SStream_concat(O, "#%" PRIu64, Val); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; - MI->flat_insn->detail->arm.op_count++; - } - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = (unsigned int)Val; + MI->flat_insn->detail->arm.op_count++; + } } -static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, - unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - int32_t OffImm = (int32_t)MCOperand_getImm(MO1); +static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + printUInt32Bang(O, Imm + 1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = Imm + 1; + MI->flat_insn->detail->arm.op_count++; + } +} - //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); +static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - SStream_concat0(O, ", "); + if (Imm == 0) + return; - if (OffImm == INT32_MIN) { - SStream_concat0(O, "#-0"); + SStream_concat0(O, ", ror #"); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; - MI->flat_insn->detail->arm.op_count++; - } - } else { - printInt32Bang(O, OffImm); + switch (Imm) { + default: // assert (0 && "illegal ror immediate!"); + case 1: + SStream_concat0(O, "8"); + break; + case 2: + SStream_concat0(O, "16"); + break; + case 3: + SStream_concat0(O, "24"); + break; + } - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; - MI->flat_insn->detail->arm.op_count++; - } - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.type = ARM_SFT_ROR; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1] + .shift.value = Imm * 8; + } } -static void printT2AddrModeSoRegOperand(MCInst *MI, - unsigned OpNum, SStream *O) -{ - MCOperand *MO1 = MCInst_getOperand(MI, OpNum); - MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); - MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2); - unsigned ShAmt; +static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned Bits = MCOperand_getImm(Op) & 0xFF; + unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7; + int32_t Rotated; + bool PrintUnsigned = false; + + switch (MCInst_getOpcode(MI)) { + case ARM_MOVi: + // Movs to PC should be treated unsigned + PrintUnsigned = + (MCOperand_getReg(MCInst_getOperand(MI, OpNum - 1)) == ARM_PC); + break; + case ARM_MSRi: + // Movs to special registers should be treated unsigned + PrintUnsigned = true; + break; + } - SStream_concat0(O, "["); - set_mem_access(MI, true); + Rotated = rotr32(Bits, Rot); + if (getSOImmVal(Rotated) == MCOperand_getImm(Op)) { + // #rot has the least possible value + if (PrintUnsigned) { + if (Rotated > HEX_THRESHOLD || Rotated < -HEX_THRESHOLD) + SStream_concat(O, "#0x%x", Rotated); + else + SStream_concat(O, "#%u", Rotated); + } else if (Rotated >= 0) { + if (Rotated > HEX_THRESHOLD) + SStream_concat(O, "#0x%x", Rotated); + else + SStream_concat(O, "#%u", Rotated); + } else { + SStream_concat(O, "#0x%x", Rotated); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = Rotated; + MI->flat_insn->detail->arm.op_count++; + } + + return; + } - printRegName(MI->csh, O, MCOperand_getReg(MO1)); + // Explicit #bits, #rot implied + SStream_concat(O, "#%u, #%u", Bits, Rot); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = Bits; + MI->flat_insn->detail->arm.op_count++; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = Rot; + MI->flat_insn->detail->arm.op_count++; + } +} - //assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!"); - SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MO2)); +static void printVPTPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { + VPTCodes CCCode = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - if (MI->csh->detail) - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); + if (CCCode != ARMVCC_None) + SStream_concat0(O, ARMVPTPredToString(CCCode)); +} - ShAmt = (unsigned int)MCOperand_getImm(MO3); - if (ShAmt) { - //assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); - SStream_concat0(O, ", lsl "); - SStream_concat(O, "#%u", ShAmt); +static void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O) { + // (3 - the number of trailing zeroes) is the number of them / else. + unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = ShAmt; - } - } + unsigned NumTZ = countTrailingZeros(Mask); + for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { + bool T = ((Mask >> Pos) & 1) == 0; + if (T) + SStream_concat1(O, 't'); + else + SStream_concat1(O, 'e'); + } +} - SStream_concat0(O, "]"); - set_mem_access(MI, false); +void printMVEVectorList(MCInst *MI, unsigned OpNum, SStream *O, + unsigned NumRegs) { + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + for (unsigned i = 0; i < NumRegs; i++) { + SStream_concat1(O, '{'); + printRegName(MI->csh, O, + MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_qsub_0 + i)); + SStream_concat0(O, ", "); + } + SStream_concat1(O, '}'); } -static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); +static void printVMOVModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned EncodedImm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned EltBits; + uint64_t Val = ARM_AM_decodeVMOVModImm(EncodedImm, &EltBits); + SStream_concat(O, "#0x%lx", Val); +} -#if defined(_KERNEL_MODE) - // Issue #681: Windows kernel does not support formatting float point - SStream_concat(O, "#"); -#else - SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO))); -#endif - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO)); - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - unsigned EltBits; - uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits); - - if (Val > HEX_THRESHOLD) - SStream_concat(O, "#0x%"PRIx64, Val); - else - SStream_concat(O, "#%"PRIu64, Val); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val; - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - - printUInt32Bang(O, Imm + 1); - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1; - MI->flat_insn->detail->arm.op_count++; - } -} - -static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - - if (Imm == 0) - return; - - SStream_concat0(O, ", ror #"); - - switch (Imm) { - default: //assert (0 && "illegal ror immediate!"); - case 1: SStream_concat0(O, "8"); break; - case 2: SStream_concat0(O, "16"); break; - case 3: SStream_concat0(O, "24"); break; - } - - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8; - } -} - -static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNum); - unsigned Bits = MCOperand_getImm(Op) & 0xFF; - unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7; - int32_t Rotated; - bool PrintUnsigned = false; +static void printMveAddrModeRQOperand(MCInst *MI, unsigned OpNum, SStream *O, + int shift) { + unsigned MO1 = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned MO2 = MCOperand_getReg(MCInst_getOperand(MI, OpNum + 1)); - switch (MCInst_getOpcode(MI)) { - case ARM_MOVi: - // Movs to PC should be treated unsigned - PrintUnsigned = (MCOperand_getReg(MCInst_getOperand(MI, OpNum - 1)) == ARM_PC); - break; - case ARM_MSRi: - // Movs to special registers should be treated unsigned - PrintUnsigned = true; - break; - } + SStream_concat0(O, "["); + printRegName(MI->csh, O, MO1); + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MO2); - Rotated = rotr32(Bits, Rot); - if (getSOImmVal(Rotated) == MCOperand_getImm(Op)) { - // #rot has the least possible value - if (PrintUnsigned) { - if (Rotated > HEX_THRESHOLD || Rotated < -HEX_THRESHOLD) - SStream_concat(O, "#0x%x", Rotated); - else - SStream_concat(O, "#%u", Rotated); - } else if (Rotated >= 0) { - if (Rotated > HEX_THRESHOLD) - SStream_concat(O, "#0x%x", Rotated); - else - SStream_concat(O, "#%u", Rotated); - } else { - SStream_concat(O, "#0x%x", Rotated); - } + if (shift > 0) + printRegImmShift(MI, O, ARM_AM_uxtw, shift); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rotated; - MI->flat_insn->detail->arm.op_count++; - } + SStream_concat0(O, "]"); +} - return; - } +static void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + if (MCOperand_getImm(MCInst_getOperand(MI, OpNum)) == ARMCC_HS) { + SStream_concat0(O, "cs"); + } else + printMandatoryPredicateOperand(MI, OpNum, O); +} - // Explicit #bits, #rot implied - SStream_concat(O, "#%u, #%u", Bits, Rot); +static void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum, + SStream *O) { + ARMCC_CondCodes CC = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, ARMCC_ARMCondCodeToString(ARMCC_getOppositeCondition(CC))); +} - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Bits; - MI->flat_insn->detail->arm.op_count++; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rot; - MI->flat_insn->detail->arm.op_count++; - } +static void printMveSaturateOp(MCInst *MI, unsigned OpNum, SStream *O) { + uint32_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, "#"); + SStream_concat0(O, Val == 1 ? "48" : "64"); } -static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned tmp; +static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned tmp; - tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - printUInt32Bang(O, tmp); + printUInt32Bang(O, tmp); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; - MI->flat_insn->detail->arm.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } } -static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned tmp; +static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned tmp; - tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - printUInt32Bang(O, tmp); + printUInt32Bang(O, tmp); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; - MI->flat_insn->detail->arm.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } } -static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) -{ - unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); +static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) { + unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - if (tmp > HEX_THRESHOLD) - SStream_concat(O, "[0x%x]", tmp); - else - SStream_concat(O, "[%u]", tmp); + if (tmp > HEX_THRESHOLD) + SStream_concat(O, "[0x%x]", tmp); + else + SStream_concat(O, "[%u]", tmp); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp; - } + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1] + .vector_index = tmp; + } } -static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) -{ - SStream_concat0(O, "{"); +static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) { + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; + MI->flat_insn->detail->arm.op_count++; #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif - } + } - SStream_concat0(O, "}"); + SStream_concat0(O, "}"); } -static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; #endif - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); - unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); #ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - SStream_concat0(O, "{"); + SStream_concat0(O, "{"); - printRegName(MI->csh, O, Reg0); + printRegName(MI->csh, O, Reg0); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg0; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, Reg1); + printRegName(MI->csh, O, Reg1); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg1; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "}"); + SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; #endif - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); - unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); #ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - SStream_concat0(O, "{"); + SStream_concat0(O, "{"); - printRegName(MI->csh, O, Reg0); + printRegName(MI->csh, O, Reg0); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg0; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, Reg1); + printRegName(MI->csh, O, Reg1); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg1; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "}"); + SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - SStream_concat0(O, "{"); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "}"); + SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - SStream_concat0(O, "{"); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "}"); + SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - SStream_concat0(O, "{"); + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[]}"); + SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; #endif - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); - unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); #ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - SStream_concat0(O, "{"); + SStream_concat0(O, "{"); - printRegName(MI->csh, O, Reg0); + printRegName(MI->csh, O, Reg0); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg0; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, Reg1); + printRegName(MI->csh, O, Reg1); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg1; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[]}"); + SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, + SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - SStream_concat0(O, "{"); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[]}"); + SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, + SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - SStream_concat0(O, "{"); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[]}"); + SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, + SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; #endif - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); - unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); #ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - SStream_concat0(O, "{"); + SStream_concat0(O, "{"); - printRegName(MI->csh, O, Reg0); + printRegName(MI->csh, O, Reg0); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg0; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, Reg1); + printRegName(MI->csh, O, Reg1); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = Reg1; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[]}"); + SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListThreeSpacedAllLanes(MCInst *MI, - unsigned OpNum, SStream *O) -{ +static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, + SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - SStream_concat0(O, "{"); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[]}"); + SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListFourSpacedAllLanes(MCInst *MI, - unsigned OpNum, SStream *O) -{ +static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, + SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - SStream_concat0(O, "{"); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[], "); + SStream_concat0(O, "[], "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "[]}"); + SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - SStream_concat0(O, "{"); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "}"); + SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O) -{ +static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET - uint8_t access; + uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D. - SStream_concat0(O, "{"); + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D. + SStream_concat0(O, "{"); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); - printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; #ifndef CAPSTONE_DIET - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .access = access; #endif - MI->flat_insn->detail->arm.op_count++; - } + MI->flat_insn->detail->arm.op_count++; + } - SStream_concat0(O, "}"); + SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET - MI->ac_idx++; + MI->ac_idx++; #endif } -static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder) -{ - unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - unsigned tmp = (unsigned)((Val * Angle) + Remainder); +static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, + int64_t Angle, int64_t Remainder) { + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + unsigned tmp = (unsigned)((Val * Angle) + Remainder); - printUInt32Bang(O, tmp); - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; - MI->flat_insn->detail->arm.op_count++; - } + printUInt32Bang(O, tmp); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } } -void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm.vector_data = vd; - } +void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm.vector_data = vd; + } } -void ARM_addVectorDataSize(MCInst *MI, int size) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm.vector_size = size; - } +void ARM_addVectorDataSize(MCInst *MI, int size) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm.vector_size = size; + } } -void ARM_addReg(MCInst *MI, int reg) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; - MI->flat_insn->detail->arm.op_count++; - } +void ARM_addReg(MCInst *MI, int reg) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = reg; + MI->flat_insn->detail->arm.op_count++; + } } -void ARM_addUserMode(MCInst *MI) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm.usermode = true; - } +void ARM_addUserMode(MCInst *MI) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm.usermode = true; + } } -void ARM_addSysReg(MCInst *MI, arm_sysreg reg) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG; - MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; - MI->flat_insn->detail->arm.op_count++; - } +void ARM_addSysReg(MCInst *MI, arm_sysreg reg) { + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .type = ARM_OP_SYSREG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count] + .reg = reg; + MI->flat_insn->detail->arm.op_count++; + } } #endif diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index a8d8698c05..0acad57e31 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -3,7 +3,7 @@ #ifdef CAPSTONE_HAS_ARM -#include // debug +#include // debug #include #include "../../cs_priv.h" @@ -11,540 +11,540 @@ #include "ARMMapping.h" #define GET_INSTRINFO_ENUM -#include "ARMGenInstrInfo.inc" +#define GET_REGINFO_ENUM +#include "ARMGenDisassemblerTables.inc" #ifndef CAPSTONE_DIET + static const name_map reg_name_maps[] = { - { ARM_REG_INVALID, NULL }, - { ARM_REG_APSR, "apsr"}, - { ARM_REG_APSR_NZCV, "apsr_nzcv"}, - { ARM_REG_CPSR, "cpsr"}, - { ARM_REG_FPEXC, "fpexc"}, - { ARM_REG_FPINST, "fpinst"}, - { ARM_REG_FPSCR, "fpscr"}, - { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, - { ARM_REG_FPSID, "fpsid"}, - { ARM_REG_ITSTATE, "itstate"}, - { ARM_REG_LR, "lr"}, - { ARM_REG_PC, "pc"}, - { ARM_REG_SP, "sp"}, - { ARM_REG_SPSR, "spsr"}, - { ARM_REG_D0, "d0"}, - { ARM_REG_D1, "d1"}, - { ARM_REG_D2, "d2"}, - { ARM_REG_D3, "d3"}, - { ARM_REG_D4, "d4"}, - { ARM_REG_D5, "d5"}, - { ARM_REG_D6, "d6"}, - { ARM_REG_D7, "d7"}, - { ARM_REG_D8, "d8"}, - { ARM_REG_D9, "d9"}, - { ARM_REG_D10, "d10"}, - { ARM_REG_D11, "d11"}, - { ARM_REG_D12, "d12"}, - { ARM_REG_D13, "d13"}, - { ARM_REG_D14, "d14"}, - { ARM_REG_D15, "d15"}, - { ARM_REG_D16, "d16"}, - { ARM_REG_D17, "d17"}, - { ARM_REG_D18, "d18"}, - { ARM_REG_D19, "d19"}, - { ARM_REG_D20, "d20"}, - { ARM_REG_D21, "d21"}, - { ARM_REG_D22, "d22"}, - { ARM_REG_D23, "d23"}, - { ARM_REG_D24, "d24"}, - { ARM_REG_D25, "d25"}, - { ARM_REG_D26, "d26"}, - { ARM_REG_D27, "d27"}, - { ARM_REG_D28, "d28"}, - { ARM_REG_D29, "d29"}, - { ARM_REG_D30, "d30"}, - { ARM_REG_D31, "d31"}, - { ARM_REG_FPINST2, "fpinst2"}, - { ARM_REG_MVFR0, "mvfr0"}, - { ARM_REG_MVFR1, "mvfr1"}, - { ARM_REG_MVFR2, "mvfr2"}, - { ARM_REG_Q0, "q0"}, - { ARM_REG_Q1, "q1"}, - { ARM_REG_Q2, "q2"}, - { ARM_REG_Q3, "q3"}, - { ARM_REG_Q4, "q4"}, - { ARM_REG_Q5, "q5"}, - { ARM_REG_Q6, "q6"}, - { ARM_REG_Q7, "q7"}, - { ARM_REG_Q8, "q8"}, - { ARM_REG_Q9, "q9"}, - { ARM_REG_Q10, "q10"}, - { ARM_REG_Q11, "q11"}, - { ARM_REG_Q12, "q12"}, - { ARM_REG_Q13, "q13"}, - { ARM_REG_Q14, "q14"}, - { ARM_REG_Q15, "q15"}, - { ARM_REG_R0, "r0"}, - { ARM_REG_R1, "r1"}, - { ARM_REG_R2, "r2"}, - { ARM_REG_R3, "r3"}, - { ARM_REG_R4, "r4"}, - { ARM_REG_R5, "r5"}, - { ARM_REG_R6, "r6"}, - { ARM_REG_R7, "r7"}, - { ARM_REG_R8, "r8"}, - { ARM_REG_R9, "sb"}, - { ARM_REG_R10, "sl"}, - { ARM_REG_R11, "fp"}, - { ARM_REG_R12, "ip"}, - { ARM_REG_S0, "s0"}, - { ARM_REG_S1, "s1"}, - { ARM_REG_S2, "s2"}, - { ARM_REG_S3, "s3"}, - { ARM_REG_S4, "s4"}, - { ARM_REG_S5, "s5"}, - { ARM_REG_S6, "s6"}, - { ARM_REG_S7, "s7"}, - { ARM_REG_S8, "s8"}, - { ARM_REG_S9, "s9"}, - { ARM_REG_S10, "s10"}, - { ARM_REG_S11, "s11"}, - { ARM_REG_S12, "s12"}, - { ARM_REG_S13, "s13"}, - { ARM_REG_S14, "s14"}, - { ARM_REG_S15, "s15"}, - { ARM_REG_S16, "s16"}, - { ARM_REG_S17, "s17"}, - { ARM_REG_S18, "s18"}, - { ARM_REG_S19, "s19"}, - { ARM_REG_S20, "s20"}, - { ARM_REG_S21, "s21"}, - { ARM_REG_S22, "s22"}, - { ARM_REG_S23, "s23"}, - { ARM_REG_S24, "s24"}, - { ARM_REG_S25, "s25"}, - { ARM_REG_S26, "s26"}, - { ARM_REG_S27, "s27"}, - { ARM_REG_S28, "s28"}, - { ARM_REG_S29, "s29"}, - { ARM_REG_S30, "s30"}, - { ARM_REG_S31, "s31"}, + {ARM_REG_INVALID, NULL}, + {ARM_APSR, "apsr"}, + {ARM_APSR_NZCV, "apsr_nzcv"}, + {ARM_CPSR, "cpsr"}, + {ARM_FPEXC, "fpexc"}, + {ARM_FPINST, "fpinst"}, + {ARM_FPSCR, "fpscr"}, + {ARM_FPSCR_NZCV, "fpscr_nzcv"}, + {ARM_FPSID, "fpsid"}, + {ARM_ITSTATE, "itstate"}, + {ARM_LR, "lr"}, + {ARM_PC, "pc"}, + {ARM_SP, "sp"}, + {ARM_SPSR, "spsr"}, + {ARM_D0, "d0"}, + {ARM_D1, "d1"}, + {ARM_D2, "d2"}, + {ARM_D3, "d3"}, + {ARM_D4, "d4"}, + {ARM_D5, "d5"}, + {ARM_D6, "d6"}, + {ARM_D7, "d7"}, + {ARM_D8, "d8"}, + {ARM_D9, "d9"}, + {ARM_D10, "d10"}, + {ARM_D11, "d11"}, + {ARM_D12, "d12"}, + {ARM_D13, "d13"}, + {ARM_D14, "d14"}, + {ARM_D15, "d15"}, + {ARM_D16, "d16"}, + {ARM_D17, "d17"}, + {ARM_D18, "d18"}, + {ARM_D19, "d19"}, + {ARM_D20, "d20"}, + {ARM_D21, "d21"}, + {ARM_D22, "d22"}, + {ARM_D23, "d23"}, + {ARM_D24, "d24"}, + {ARM_D25, "d25"}, + {ARM_D26, "d26"}, + {ARM_D27, "d27"}, + {ARM_D28, "d28"}, + {ARM_D29, "d29"}, + {ARM_D30, "d30"}, + {ARM_D31, "d31"}, + {ARM_FPINST2, "fpinst2"}, + {ARM_MVFR0, "mvfr0"}, + {ARM_MVFR1, "mvfr1"}, + {ARM_MVFR2, "mvfr2"}, + {ARM_Q0, "q0"}, + {ARM_Q1, "q1"}, + {ARM_Q2, "q2"}, + {ARM_Q3, "q3"}, + {ARM_Q4, "q4"}, + {ARM_Q5, "q5"}, + {ARM_Q6, "q6"}, + {ARM_Q7, "q7"}, + {ARM_Q8, "q8"}, + {ARM_Q9, "q9"}, + {ARM_Q10, "q10"}, + {ARM_Q11, "q11"}, + {ARM_Q12, "q12"}, + {ARM_Q13, "q13"}, + {ARM_Q14, "q14"}, + {ARM_Q15, "q15"}, + {ARM_R0, "r0"}, + {ARM_R1, "r1"}, + {ARM_R2, "r2"}, + {ARM_R3, "r3"}, + {ARM_R4, "r4"}, + {ARM_R5, "r5"}, + {ARM_R6, "r6"}, + {ARM_R7, "r7"}, + {ARM_R8, "r8"}, + {ARM_R9, "sb"}, + {ARM_R10, "sl"}, + {ARM_R11, "fp"}, + {ARM_R12, "ip"}, + {ARM_S0, "s0"}, + {ARM_S1, "s1"}, + {ARM_S2, "s2"}, + {ARM_S3, "s3"}, + {ARM_S4, "s4"}, + {ARM_S5, "s5"}, + {ARM_S6, "s6"}, + {ARM_S7, "s7"}, + {ARM_S8, "s8"}, + {ARM_S9, "s9"}, + {ARM_S10, "s10"}, + {ARM_S11, "s11"}, + {ARM_S12, "s12"}, + {ARM_S13, "s13"}, + {ARM_S14, "s14"}, + {ARM_S15, "s15"}, + {ARM_S16, "s16"}, + {ARM_S17, "s17"}, + {ARM_S18, "s18"}, + {ARM_S19, "s19"}, + {ARM_S20, "s20"}, + {ARM_S21, "s21"}, + {ARM_S22, "s22"}, + {ARM_S23, "s23"}, + {ARM_S24, "s24"}, + {ARM_S25, "s25"}, + {ARM_S26, "s26"}, + {ARM_S27, "s27"}, + {ARM_S28, "s28"}, + {ARM_S29, "s29"}, + {ARM_S30, "s30"}, + {ARM_S31, "s31"}, }; static const name_map reg_name_maps2[] = { - { ARM_REG_INVALID, NULL }, - { ARM_REG_APSR, "apsr"}, - { ARM_REG_APSR_NZCV, "apsr_nzcv"}, - { ARM_REG_CPSR, "cpsr"}, - { ARM_REG_FPEXC, "fpexc"}, - { ARM_REG_FPINST, "fpinst"}, - { ARM_REG_FPSCR, "fpscr"}, - { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, - { ARM_REG_FPSID, "fpsid"}, - { ARM_REG_ITSTATE, "itstate"}, - { ARM_REG_LR, "lr"}, - { ARM_REG_PC, "pc"}, - { ARM_REG_SP, "sp"}, - { ARM_REG_SPSR, "spsr"}, - { ARM_REG_D0, "d0"}, - { ARM_REG_D1, "d1"}, - { ARM_REG_D2, "d2"}, - { ARM_REG_D3, "d3"}, - { ARM_REG_D4, "d4"}, - { ARM_REG_D5, "d5"}, - { ARM_REG_D6, "d6"}, - { ARM_REG_D7, "d7"}, - { ARM_REG_D8, "d8"}, - { ARM_REG_D9, "d9"}, - { ARM_REG_D10, "d10"}, - { ARM_REG_D11, "d11"}, - { ARM_REG_D12, "d12"}, - { ARM_REG_D13, "d13"}, - { ARM_REG_D14, "d14"}, - { ARM_REG_D15, "d15"}, - { ARM_REG_D16, "d16"}, - { ARM_REG_D17, "d17"}, - { ARM_REG_D18, "d18"}, - { ARM_REG_D19, "d19"}, - { ARM_REG_D20, "d20"}, - { ARM_REG_D21, "d21"}, - { ARM_REG_D22, "d22"}, - { ARM_REG_D23, "d23"}, - { ARM_REG_D24, "d24"}, - { ARM_REG_D25, "d25"}, - { ARM_REG_D26, "d26"}, - { ARM_REG_D27, "d27"}, - { ARM_REG_D28, "d28"}, - { ARM_REG_D29, "d29"}, - { ARM_REG_D30, "d30"}, - { ARM_REG_D31, "d31"}, - { ARM_REG_FPINST2, "fpinst2"}, - { ARM_REG_MVFR0, "mvfr0"}, - { ARM_REG_MVFR1, "mvfr1"}, - { ARM_REG_MVFR2, "mvfr2"}, - { ARM_REG_Q0, "q0"}, - { ARM_REG_Q1, "q1"}, - { ARM_REG_Q2, "q2"}, - { ARM_REG_Q3, "q3"}, - { ARM_REG_Q4, "q4"}, - { ARM_REG_Q5, "q5"}, - { ARM_REG_Q6, "q6"}, - { ARM_REG_Q7, "q7"}, - { ARM_REG_Q8, "q8"}, - { ARM_REG_Q9, "q9"}, - { ARM_REG_Q10, "q10"}, - { ARM_REG_Q11, "q11"}, - { ARM_REG_Q12, "q12"}, - { ARM_REG_Q13, "q13"}, - { ARM_REG_Q14, "q14"}, - { ARM_REG_Q15, "q15"}, - { ARM_REG_R0, "r0"}, - { ARM_REG_R1, "r1"}, - { ARM_REG_R2, "r2"}, - { ARM_REG_R3, "r3"}, - { ARM_REG_R4, "r4"}, - { ARM_REG_R5, "r5"}, - { ARM_REG_R6, "r6"}, - { ARM_REG_R7, "r7"}, - { ARM_REG_R8, "r8"}, - { ARM_REG_R9, "r9"}, - { ARM_REG_R10, "r10"}, - { ARM_REG_R11, "r11"}, - { ARM_REG_R12, "r12"}, - { ARM_REG_S0, "s0"}, - { ARM_REG_S1, "s1"}, - { ARM_REG_S2, "s2"}, - { ARM_REG_S3, "s3"}, - { ARM_REG_S4, "s4"}, - { ARM_REG_S5, "s5"}, - { ARM_REG_S6, "s6"}, - { ARM_REG_S7, "s7"}, - { ARM_REG_S8, "s8"}, - { ARM_REG_S9, "s9"}, - { ARM_REG_S10, "s10"}, - { ARM_REG_S11, "s11"}, - { ARM_REG_S12, "s12"}, - { ARM_REG_S13, "s13"}, - { ARM_REG_S14, "s14"}, - { ARM_REG_S15, "s15"}, - { ARM_REG_S16, "s16"}, - { ARM_REG_S17, "s17"}, - { ARM_REG_S18, "s18"}, - { ARM_REG_S19, "s19"}, - { ARM_REG_S20, "s20"}, - { ARM_REG_S21, "s21"}, - { ARM_REG_S22, "s22"}, - { ARM_REG_S23, "s23"}, - { ARM_REG_S24, "s24"}, - { ARM_REG_S25, "s25"}, - { ARM_REG_S26, "s26"}, - { ARM_REG_S27, "s27"}, - { ARM_REG_S28, "s28"}, - { ARM_REG_S29, "s29"}, - { ARM_REG_S30, "s30"}, - { ARM_REG_S31, "s31"}, + {ARM_REG_INVALID, NULL}, + {ARM_APSR, "apsr"}, + {ARM_APSR_NZCV, "apsr_nzcv"}, + {ARM_CPSR, "cpsr"}, + {ARM_FPEXC, "fpexc"}, + {ARM_FPINST, "fpinst"}, + {ARM_FPSCR, "fpscr"}, + {ARM_FPSCR_NZCV, "fpscr_nzcv"}, + {ARM_FPSID, "fpsid"}, + {ARM_ITSTATE, "itstate"}, + {ARM_LR, "lr"}, + {ARM_PC, "pc"}, + {ARM_SP, "sp"}, + {ARM_SPSR, "spsr"}, + {ARM_D0, "d0"}, + {ARM_D1, "d1"}, + {ARM_D2, "d2"}, + {ARM_D3, "d3"}, + {ARM_D4, "d4"}, + {ARM_D5, "d5"}, + {ARM_D6, "d6"}, + {ARM_D7, "d7"}, + {ARM_D8, "d8"}, + {ARM_D9, "d9"}, + {ARM_D10, "d10"}, + {ARM_D11, "d11"}, + {ARM_D12, "d12"}, + {ARM_D13, "d13"}, + {ARM_D14, "d14"}, + {ARM_D15, "d15"}, + {ARM_D16, "d16"}, + {ARM_D17, "d17"}, + {ARM_D18, "d18"}, + {ARM_D19, "d19"}, + {ARM_D20, "d20"}, + {ARM_D21, "d21"}, + {ARM_D22, "d22"}, + {ARM_D23, "d23"}, + {ARM_D24, "d24"}, + {ARM_D25, "d25"}, + {ARM_D26, "d26"}, + {ARM_D27, "d27"}, + {ARM_D28, "d28"}, + {ARM_D29, "d29"}, + {ARM_D30, "d30"}, + {ARM_D31, "d31"}, + {ARM_FPINST2, "fpinst2"}, + {ARM_MVFR0, "mvfr0"}, + {ARM_MVFR1, "mvfr1"}, + {ARM_MVFR2, "mvfr2"}, + {ARM_Q0, "q0"}, + {ARM_Q1, "q1"}, + {ARM_Q2, "q2"}, + {ARM_Q3, "q3"}, + {ARM_Q4, "q4"}, + {ARM_Q5, "q5"}, + {ARM_Q6, "q6"}, + {ARM_Q7, "q7"}, + {ARM_Q8, "q8"}, + {ARM_Q9, "q9"}, + {ARM_Q10, "q10"}, + {ARM_Q11, "q11"}, + {ARM_Q12, "q12"}, + {ARM_Q13, "q13"}, + {ARM_Q14, "q14"}, + {ARM_Q15, "q15"}, + {ARM_R0, "r0"}, + {ARM_R1, "r1"}, + {ARM_R2, "r2"}, + {ARM_R3, "r3"}, + {ARM_R4, "r4"}, + {ARM_R5, "r5"}, + {ARM_R6, "r6"}, + {ARM_R7, "r7"}, + {ARM_R8, "r8"}, + {ARM_R9, "r9"}, + {ARM_R10, "r10"}, + {ARM_R11, "r11"}, + {ARM_R12, "r12"}, + {ARM_S0, "s0"}, + {ARM_S1, "s1"}, + {ARM_S2, "s2"}, + {ARM_S3, "s3"}, + {ARM_S4, "s4"}, + {ARM_S5, "s5"}, + {ARM_S6, "s6"}, + {ARM_S7, "s7"}, + {ARM_S8, "s8"}, + {ARM_S9, "s9"}, + {ARM_S10, "s10"}, + {ARM_S11, "s11"}, + {ARM_S12, "s12"}, + {ARM_S13, "s13"}, + {ARM_S14, "s14"}, + {ARM_S15, "s15"}, + {ARM_S16, "s16"}, + {ARM_S17, "s17"}, + {ARM_S18, "s18"}, + {ARM_S19, "s19"}, + {ARM_S20, "s20"}, + {ARM_S21, "s21"}, + {ARM_S22, "s22"}, + {ARM_S23, "s23"}, + {ARM_S24, "s24"}, + {ARM_S25, "s25"}, + {ARM_S26, "s26"}, + {ARM_S27, "s27"}, + {ARM_S28, "s28"}, + {ARM_S29, "s29"}, + {ARM_S30, "s30"}, + {ARM_S31, "s31"}, }; #endif -const char *ARM_reg_name(csh handle, unsigned int reg) -{ +const char *ARM_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; - return reg_name_maps[reg].name; + for (int i = 0; i < ARR_SIZE(reg_name_maps); i++) { + if (reg_name_maps[i].id == reg) { + return reg_name_maps[i].name; + } + } + + // invalid + return "invalid"; #else - return NULL; + return NULL; #endif } -const char *ARM_reg_name2(csh handle, unsigned int reg) -{ +const char *ARM_reg_name2(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps2)) - return NULL; - - return reg_name_maps2[reg].name; + for (int i = 0; i < ARR_SIZE(reg_name_maps2); i++) { + if (reg_name_maps2[i].id == reg) { + return reg_name_maps2[i].name; + } + } + + // invalid + return NULL; #else - return NULL; + return NULL; #endif } static const insn_map insns[] = { - // dummy item - { - 0, 0, + // dummy item + {0, + 0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif - }, + }, #include "ARMMappingInsn.inc" }; // look for @id in @insns // return -1 if not found -static unsigned int find_insn(unsigned int id) -{ - // binary searching since the IDs are sorted in order - unsigned int left, right, m; - unsigned int max = ARR_SIZE(insns); - - right = max - 1; - - if (id < insns[0].id || id > insns[right].id) - // not found - return -1; - - left = 0; - - while(left <= right) { - m = (left + right) / 2; - if (id == insns[m].id) { - return m; - } - - if (id < insns[m].id) - right = m - 1; - else - left = m + 1; - } - - // not found - // printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id); - return -1; +static unsigned int find_insn(unsigned int id) { + // binary searching since the IDs are sorted in order + unsigned int left, right, m; + unsigned int max = ARR_SIZE(insns); + + right = max - 1; + + if (id < insns[0].id || id > insns[right].id) + // not found + return -1; + + left = 0; + + while (left <= right) { + m = (left + right) / 2; + if (id == insns[m].id) { + return m; + } + + if (id < insns[m].id) + right = m - 1; + else + left = m + 1; + } + + // not found + // printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id); + return -1; } -void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) -{ - unsigned int i = find_insn(id); - if (i != -1) { - insn->id = insns[i].mapid; +void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { + unsigned int i = find_insn(id); + if (i != -1) { + insn->id = insns[i].mapid; - // printf("id = %u, mapid = %u\n", id, insn->id); + // printf("id = %u, mapid = %u\n", id, insn->id); - if (h->detail) { + if (h->detail) { #ifndef CAPSTONE_DIET - cs_struct handle; - handle.detail = h->detail; - - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); - - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); - - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - - insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR); - - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP; - insn->detail->groups_count++; - } + cs_struct handle; + handle.detail = h->detail; + + memcpy(insn->detail->regs_read, insns[i].regs_use, + sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = + (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, + sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = + (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + insn->detail->arm.update_flags = + cs_reg_write((csh)&handle, insn, ARM_REG_CPSR); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP; + insn->detail->groups_count++; + } #endif - } - } + } + } } #ifndef CAPSTONE_DIET -static const char * const insn_name_maps[] = { - NULL, // ARM_INS_INVALID +static const char *const insn_name_maps[] = { + NULL, // ARM_INS_INVALID #include "ARMMappingInsnName.inc" }; #endif -const char *ARM_insn_name(csh handle, unsigned int id) -{ +const char *ARM_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - if (id >= ARM_INS_ENDING) - return NULL; + if (id >= ARM_INS_ENDING) + return NULL; - return insn_name_maps[id]; + return insn_name_maps[id]; #else - return NULL; + return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { - // generic groups - { ARM_GRP_INVALID, NULL }, - { ARM_GRP_JUMP, "jump" }, - { ARM_GRP_CALL, "call" }, - { ARM_GRP_INT, "int" }, - { ARM_GRP_PRIVILEGE, "privilege" }, - { ARM_GRP_BRANCH_RELATIVE, "branch_relative" }, - - // architecture-specific groups - { ARM_GRP_CRYPTO, "crypto" }, - { ARM_GRP_DATABARRIER, "databarrier" }, - { ARM_GRP_DIVIDE, "divide" }, - { ARM_GRP_FPARMV8, "fparmv8" }, - { ARM_GRP_MULTPRO, "multpro" }, - { ARM_GRP_NEON, "neon" }, - { ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" }, - { ARM_GRP_THUMB2DSP, "THUMB2DSP" }, - { ARM_GRP_TRUSTZONE, "TRUSTZONE" }, - { ARM_GRP_V4T, "v4t" }, - { ARM_GRP_V5T, "v5t" }, - { ARM_GRP_V5TE, "v5te" }, - { ARM_GRP_V6, "v6" }, - { ARM_GRP_V6T2, "v6t2" }, - { ARM_GRP_V7, "v7" }, - { ARM_GRP_V8, "v8" }, - { ARM_GRP_VFP2, "vfp2" }, - { ARM_GRP_VFP3, "vfp3" }, - { ARM_GRP_VFP4, "vfp4" }, - { ARM_GRP_ARM, "arm" }, - { ARM_GRP_MCLASS, "mclass" }, - { ARM_GRP_NOTMCLASS, "notmclass" }, - { ARM_GRP_THUMB, "thumb" }, - { ARM_GRP_THUMB1ONLY, "thumb1only" }, - { ARM_GRP_THUMB2, "thumb2" }, - { ARM_GRP_PREV8, "prev8" }, - { ARM_GRP_FPVMLX, "fpvmlx" }, - { ARM_GRP_MULOPS, "mulops" }, - { ARM_GRP_CRC, "crc" }, - { ARM_GRP_DPVFP, "dpvfp" }, - { ARM_GRP_V6M, "v6m" }, - { ARM_GRP_VIRTUALIZATION, "virtualization" }, + // generic groups + {ARM_GRP_INVALID, NULL}, + {ARM_GRP_JUMP, "jump"}, + {ARM_GRP_CALL, "call"}, + {ARM_GRP_INT, "int"}, + {ARM_GRP_PRIVILEGE, "privilege"}, + {ARM_GRP_BRANCH_RELATIVE, "branch_relative"}, + + // architecture-specific groups + {ARM_GRP_CRYPTO, "crypto"}, + {ARM_GRP_DATABARRIER, "databarrier"}, + {ARM_GRP_DIVIDE, "divide"}, + {ARM_GRP_FPARMV8, "fparmv8"}, + {ARM_GRP_MULTPRO, "multpro"}, + {ARM_GRP_NEON, "neon"}, + {ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK"}, + {ARM_GRP_THUMB2DSP, "THUMB2DSP"}, + {ARM_GRP_TRUSTZONE, "TRUSTZONE"}, + {ARM_GRP_V4T, "v4t"}, + {ARM_GRP_V5T, "v5t"}, + {ARM_GRP_V5TE, "v5te"}, + {ARM_GRP_V6, "v6"}, + {ARM_GRP_V6T2, "v6t2"}, + {ARM_GRP_V7, "v7"}, + {ARM_GRP_V8, "v8"}, + {ARM_GRP_VFP2, "vfp2"}, + {ARM_GRP_VFP3, "vfp3"}, + {ARM_GRP_VFP4, "vfp4"}, + {ARM_GRP_ARM, "arm"}, + {ARM_GRP_MCLASS, "mclass"}, + {ARM_GRP_NOTMCLASS, "notmclass"}, + {ARM_GRP_THUMB, "thumb"}, + {ARM_GRP_THUMB1ONLY, "thumb1only"}, + {ARM_GRP_THUMB2, "thumb2"}, + {ARM_GRP_PREV8, "prev8"}, + {ARM_GRP_FPVMLX, "fpvmlx"}, + {ARM_GRP_MULOPS, "mulops"}, + {ARM_GRP_CRC, "crc"}, + {ARM_GRP_DPVFP, "dpvfp"}, + {ARM_GRP_V6M, "v6m"}, + {ARM_GRP_VIRTUALIZATION, "virtualization"}, }; #endif -const char *ARM_group_name(csh handle, unsigned int id) -{ +const char *ARM_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else - return NULL; + return NULL; #endif } // list all relative branch instructions // ie: insns[i].branch && !insns[i].indirect_branch static const unsigned int insn_rel[] = { - ARM_BL, - ARM_BLX_pred, - ARM_Bcc, - ARM_t2B, - ARM_t2Bcc, - ARM_tB, - ARM_tBcc, - ARM_tCBNZ, - ARM_tCBZ, - ARM_BL_pred, - ARM_BLXi, - ARM_tBL, - ARM_tBLXi, - 0 -}; + ARM_BL, ARM_BLX_pred, ARM_Bcc, ARM_t2B, ARM_t2Bcc, + ARM_tB, ARM_tBcc, ARM_tCBNZ, ARM_tCBZ, ARM_BL_pred, + ARM_BLXi, ARM_tBL, ARM_tBLXi, 0}; -static const unsigned int insn_blx_rel_to_arm[] = { - ARM_tBLXi, - 0 -}; +static const unsigned int insn_blx_rel_to_arm[] = {ARM_tBLXi, 0}; // check if this insn is relative branch -bool ARM_rel_branch(cs_struct *h, unsigned int id) -{ - int i; - - for (i = 0; insn_rel[i]; i++) { - if (id == insn_rel[i]) { - return true; - } - } - - // not found - return false; +bool ARM_rel_branch(cs_struct *h, unsigned int id) { + int i; + + for (i = 0; insn_rel[i]; i++) { + if (id == insn_rel[i]) { + return true; + } + } + + // not found + return false; } bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) { - int i; - - for (i = 0; insn_blx_rel_to_arm[i]; i++) - if (id == insn_blx_rel_to_arm[i]) - return true; + int i; - // not found - return false; + for (i = 0; insn_blx_rel_to_arm[i]; i++) + if (id == insn_blx_rel_to_arm[i]) + return true; + // not found + return false; } #ifndef CAPSTONE_DIET // map instruction to its characteristics typedef struct insn_op { - uint8_t access[7]; + uint8_t access[7]; } insn_op; static const insn_op insn_ops[] = { - { - // NULL item - { 0 } - }, + {// NULL item + {0}}, #include "ARMMappingInsnOp.inc" }; // given internal insn id, return operand access info -const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id) -{ - int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - return insn_ops[i].access; - } - - return NULL; +const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id) { + int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + return insn_ops[i].access; + } + + return NULL; } -void ARM_reg_access(const cs_insn *insn, - cs_regs regs_read, uint8_t *regs_read_count, - cs_regs regs_write, uint8_t *regs_write_count) -{ - uint8_t i; - uint8_t read_count, write_count; - cs_arm *arm = &(insn->detail->arm); - - read_count = insn->detail->regs_read_count; - write_count = insn->detail->regs_write_count; - - // implicit registers - memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); - memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); - - // explicit registers - for (i = 0; i < arm->op_count; i++) { - cs_arm_op *op = &(arm->operands[i]); - switch((int)op->type) { - case ARM_OP_REG: - if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { - regs_read[read_count] = (uint16_t)op->reg; - read_count++; - } - if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { - regs_write[write_count] = (uint16_t)op->reg; - write_count++; - } - break; - case ARM_OP_MEM: - // registers appeared in memory references always being read - if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { - regs_read[read_count] = (uint16_t)op->mem.base; - read_count++; - } - if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { - regs_read[read_count] = (uint16_t)op->mem.index; - read_count++; - } - if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) { - regs_write[write_count] = (uint16_t)op->mem.base; - write_count++; - } - default: - break; - } - } - - *regs_read_count = read_count; - *regs_write_count = write_count; +void ARM_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count) { + uint8_t i; + uint8_t read_count, write_count; + cs_arm *arm = &(insn->detail->arm); + + read_count = insn->detail->regs_read_count; + write_count = insn->detail->regs_write_count; + + // implicit registers + memcpy(regs_read, insn->detail->regs_read, + read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, + write_count * sizeof(insn->detail->regs_write[0])); + + // explicit registers + for (i = 0; i < arm->op_count; i++) { + cs_arm_op *op = &(arm->operands[i]); + switch ((int)op->type) { + case ARM_OP_REG: + if ((op->access & CS_AC_READ) && + !arr_exist(regs_read, read_count, op->reg)) { + regs_read[read_count] = (uint16_t)op->reg; + read_count++; + } + if ((op->access & CS_AC_WRITE) && + !arr_exist(regs_write, write_count, op->reg)) { + regs_write[write_count] = (uint16_t)op->reg; + write_count++; + } + break; + case ARM_OP_MEM: + // registers appeared in memory references always being read + if ((op->mem.base != ARM_REG_INVALID) && + !arr_exist(regs_read, read_count, op->mem.base)) { + regs_read[read_count] = (uint16_t)op->mem.base; + read_count++; + } + if ((op->mem.index != ARM_REG_INVALID) && + !arr_exist(regs_read, read_count, op->mem.index)) { + regs_read[read_count] = (uint16_t)op->mem.index; + read_count++; + } + if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && + !arr_exist(regs_write, write_count, op->mem.base)) { + regs_write[write_count] = (uint16_t)op->mem.base; + write_count++; + } + default: + break; + } + } + + *regs_read_count = read_count; + *regs_write_count = write_count; } #endif diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h index 1f413d0ce7..c307e83906 100644 --- a/arch/ARM/ARMMapping.h +++ b/arch/ARM/ARMMapping.h @@ -25,14 +25,14 @@ bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id); -void ARM_reg_access(const cs_insn *insn, - cs_regs regs_read, uint8_t *regs_read_count, - cs_regs regs_write, uint8_t *regs_write_count); +void ARM_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count); typedef struct BankedReg { - const char *Name; - arm_sysreg sysreg; - uint16_t Encoding; + const char *Name; + arm_sysreg sysreg; + uint16_t Encoding; } BankedReg; const BankedReg *lookupBankedRegByEncoding(uint8_t encoding); diff --git a/arch/ARM/ARMMappingInsn.inc b/arch/ARM/ARMMappingInsn.inc index 0bb23c67d0..5a61b1a362 100644 --- a/arch/ARM/ARMMappingInsn.inc +++ b/arch/ARM/ARMMappingInsn.inc @@ -1,18772 +1,27091 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* This is auto-gen data for Capstone disassembly engine + * (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ - -{ - ARM_ASRi, ARM_INS_ASR, +{ARM_ASRi, ARM_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif }, -{ - ARM_ASRr, ARM_INS_ASR, + {ARM_ASRr, ARM_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_ITasm, ARM_INS_IT, + {ARM_ITasm, ARM_INS_IT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - ARM_LDRBT_POST, ARM_INS_LDRBT, + {ARM_LDRBT_POST, + ARM_INS_LDRBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRConstPool, ARM_INS_LDR, + {ARM_LDRConstPool, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRT_POST, ARM_INS_LDRT, + {ARM_LDRT_POST, + ARM_INS_LDRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_LSLi, ARM_INS_LSL, + {ARM_LSLi, ARM_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_LSLr, ARM_INS_LSL, + {ARM_LSLr, ARM_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_LSRi, ARM_INS_LSR, + {ARM_LSRi, ARM_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_LSRr, ARM_INS_LSR, + {ARM_LSRr, ARM_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_RORi, ARM_INS_ROR, + {ARM_RORi, ARM_INS_ROR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_RORr, ARM_INS_ROR, + {ARM_RORr, ARM_INS_ROR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_RRXi, ARM_INS_RRX, + {ARM_RRXi, ARM_INS_RRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_STRBT_POST, ARM_INS_STRBT, + {ARM_STRBT_POST, + ARM_INS_STRBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRT_POST, ARM_INS_STRT, + {ARM_STRT_POST, + ARM_INS_STRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNdAsm_16, ARM_INS_VLD1, + {ARM_VLD1LNdAsm_16, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNdAsm_32, ARM_INS_VLD1, + {ARM_VLD1LNdAsm_32, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNdAsm_8, ARM_INS_VLD1, + {ARM_VLD1LNdAsm_8, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNdWB_fixed_Asm_16, ARM_INS_VLD1, + {ARM_VLD1LNdWB_fixed_Asm_16, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNdWB_fixed_Asm_32, ARM_INS_VLD1, + {ARM_VLD1LNdWB_fixed_Asm_32, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNdWB_fixed_Asm_8, ARM_INS_VLD1, + {ARM_VLD1LNdWB_fixed_Asm_8, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNdWB_register_Asm_16, ARM_INS_VLD1, + {ARM_VLD1LNdWB_register_Asm_16, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNdWB_register_Asm_32, ARM_INS_VLD1, + {ARM_VLD1LNdWB_register_Asm_32, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNdWB_register_Asm_8, ARM_INS_VLD1, + {ARM_VLD1LNdWB_register_Asm_8, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNdAsm_16, ARM_INS_VLD2, + {ARM_VLD2LNdAsm_16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNdAsm_32, ARM_INS_VLD2, + {ARM_VLD2LNdAsm_32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNdAsm_8, ARM_INS_VLD2, + {ARM_VLD2LNdAsm_8, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNdWB_fixed_Asm_16, ARM_INS_VLD2, + {ARM_VLD2LNdWB_fixed_Asm_16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNdWB_fixed_Asm_32, ARM_INS_VLD2, + {ARM_VLD2LNdWB_fixed_Asm_32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNdWB_fixed_Asm_8, ARM_INS_VLD2, + {ARM_VLD2LNdWB_fixed_Asm_8, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNdWB_register_Asm_16, ARM_INS_VLD2, + {ARM_VLD2LNdWB_register_Asm_16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNdWB_register_Asm_32, ARM_INS_VLD2, + {ARM_VLD2LNdWB_register_Asm_32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNdWB_register_Asm_8, ARM_INS_VLD2, + {ARM_VLD2LNdWB_register_Asm_8, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNqAsm_16, ARM_INS_VLD2, + {ARM_VLD2LNqAsm_16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNqAsm_32, ARM_INS_VLD2, + {ARM_VLD2LNqAsm_32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNqWB_fixed_Asm_16, ARM_INS_VLD2, + {ARM_VLD2LNqWB_fixed_Asm_16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNqWB_fixed_Asm_32, ARM_INS_VLD2, + {ARM_VLD2LNqWB_fixed_Asm_32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNqWB_register_Asm_16, ARM_INS_VLD2, + {ARM_VLD2LNqWB_register_Asm_16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNqWB_register_Asm_32, ARM_INS_VLD2, + {ARM_VLD2LNqWB_register_Asm_32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPdAsm_16, ARM_INS_VLD3, + {ARM_VLD3DUPdAsm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPdAsm_32, ARM_INS_VLD3, + {ARM_VLD3DUPdAsm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPdAsm_8, ARM_INS_VLD3, + {ARM_VLD3DUPdAsm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPdWB_fixed_Asm_16, ARM_INS_VLD3, + {ARM_VLD3DUPdWB_fixed_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPdWB_fixed_Asm_32, ARM_INS_VLD3, + {ARM_VLD3DUPdWB_fixed_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPdWB_fixed_Asm_8, ARM_INS_VLD3, + {ARM_VLD3DUPdWB_fixed_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPdWB_register_Asm_16, ARM_INS_VLD3, + {ARM_VLD3DUPdWB_register_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPdWB_register_Asm_32, ARM_INS_VLD3, + {ARM_VLD3DUPdWB_register_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPdWB_register_Asm_8, ARM_INS_VLD3, + {ARM_VLD3DUPdWB_register_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPqAsm_16, ARM_INS_VLD3, + {ARM_VLD3DUPqAsm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPqAsm_32, ARM_INS_VLD3, + {ARM_VLD3DUPqAsm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPqAsm_8, ARM_INS_VLD3, + {ARM_VLD3DUPqAsm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPqWB_fixed_Asm_16, ARM_INS_VLD3, + {ARM_VLD3DUPqWB_fixed_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPqWB_fixed_Asm_32, ARM_INS_VLD3, + {ARM_VLD3DUPqWB_fixed_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPqWB_fixed_Asm_8, ARM_INS_VLD3, + {ARM_VLD3DUPqWB_fixed_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPqWB_register_Asm_16, ARM_INS_VLD3, + {ARM_VLD3DUPqWB_register_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPqWB_register_Asm_32, ARM_INS_VLD3, + {ARM_VLD3DUPqWB_register_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPqWB_register_Asm_8, ARM_INS_VLD3, + {ARM_VLD3DUPqWB_register_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNdAsm_16, ARM_INS_VLD3, + {ARM_VLD3LNdAsm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNdAsm_32, ARM_INS_VLD3, + {ARM_VLD3LNdAsm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNdAsm_8, ARM_INS_VLD3, + {ARM_VLD3LNdAsm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNdWB_fixed_Asm_16, ARM_INS_VLD3, + {ARM_VLD3LNdWB_fixed_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNdWB_fixed_Asm_32, ARM_INS_VLD3, + {ARM_VLD3LNdWB_fixed_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNdWB_fixed_Asm_8, ARM_INS_VLD3, + {ARM_VLD3LNdWB_fixed_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNdWB_register_Asm_16, ARM_INS_VLD3, + {ARM_VLD3LNdWB_register_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNdWB_register_Asm_32, ARM_INS_VLD3, + {ARM_VLD3LNdWB_register_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNdWB_register_Asm_8, ARM_INS_VLD3, + {ARM_VLD3LNdWB_register_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNqAsm_16, ARM_INS_VLD3, + {ARM_VLD3LNqAsm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNqAsm_32, ARM_INS_VLD3, + {ARM_VLD3LNqAsm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNqWB_fixed_Asm_16, ARM_INS_VLD3, + {ARM_VLD3LNqWB_fixed_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNqWB_fixed_Asm_32, ARM_INS_VLD3, + {ARM_VLD3LNqWB_fixed_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNqWB_register_Asm_16, ARM_INS_VLD3, + {ARM_VLD3LNqWB_register_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNqWB_register_Asm_32, ARM_INS_VLD3, + {ARM_VLD3LNqWB_register_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3dAsm_16, ARM_INS_VLD3, + {ARM_VLD3dAsm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3dAsm_32, ARM_INS_VLD3, + {ARM_VLD3dAsm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3dAsm_8, ARM_INS_VLD3, + {ARM_VLD3dAsm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3dWB_fixed_Asm_16, ARM_INS_VLD3, + {ARM_VLD3dWB_fixed_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3dWB_fixed_Asm_32, ARM_INS_VLD3, + {ARM_VLD3dWB_fixed_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3dWB_fixed_Asm_8, ARM_INS_VLD3, + {ARM_VLD3dWB_fixed_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3dWB_register_Asm_16, ARM_INS_VLD3, + {ARM_VLD3dWB_register_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3dWB_register_Asm_32, ARM_INS_VLD3, + {ARM_VLD3dWB_register_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3dWB_register_Asm_8, ARM_INS_VLD3, + {ARM_VLD3dWB_register_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3qAsm_16, ARM_INS_VLD3, + {ARM_VLD3qAsm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3qAsm_32, ARM_INS_VLD3, + {ARM_VLD3qAsm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3qAsm_8, ARM_INS_VLD3, + {ARM_VLD3qAsm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3qWB_fixed_Asm_16, ARM_INS_VLD3, + {ARM_VLD3qWB_fixed_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3qWB_fixed_Asm_32, ARM_INS_VLD3, + {ARM_VLD3qWB_fixed_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3qWB_fixed_Asm_8, ARM_INS_VLD3, + {ARM_VLD3qWB_fixed_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3qWB_register_Asm_16, ARM_INS_VLD3, + {ARM_VLD3qWB_register_Asm_16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3qWB_register_Asm_32, ARM_INS_VLD3, + {ARM_VLD3qWB_register_Asm_32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3qWB_register_Asm_8, ARM_INS_VLD3, + {ARM_VLD3qWB_register_Asm_8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPdAsm_16, ARM_INS_VLD4, + {ARM_VLD4DUPdAsm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPdAsm_32, ARM_INS_VLD4, + {ARM_VLD4DUPdAsm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPdAsm_8, ARM_INS_VLD4, + {ARM_VLD4DUPdAsm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPdWB_fixed_Asm_16, ARM_INS_VLD4, + {ARM_VLD4DUPdWB_fixed_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPdWB_fixed_Asm_32, ARM_INS_VLD4, + {ARM_VLD4DUPdWB_fixed_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPdWB_fixed_Asm_8, ARM_INS_VLD4, + {ARM_VLD4DUPdWB_fixed_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPdWB_register_Asm_16, ARM_INS_VLD4, + {ARM_VLD4DUPdWB_register_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPdWB_register_Asm_32, ARM_INS_VLD4, + {ARM_VLD4DUPdWB_register_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPdWB_register_Asm_8, ARM_INS_VLD4, + {ARM_VLD4DUPdWB_register_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPqAsm_16, ARM_INS_VLD4, + {ARM_VLD4DUPqAsm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPqAsm_32, ARM_INS_VLD4, + {ARM_VLD4DUPqAsm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPqAsm_8, ARM_INS_VLD4, + {ARM_VLD4DUPqAsm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPqWB_fixed_Asm_16, ARM_INS_VLD4, + {ARM_VLD4DUPqWB_fixed_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPqWB_fixed_Asm_32, ARM_INS_VLD4, + {ARM_VLD4DUPqWB_fixed_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPqWB_fixed_Asm_8, ARM_INS_VLD4, + {ARM_VLD4DUPqWB_fixed_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPqWB_register_Asm_16, ARM_INS_VLD4, + {ARM_VLD4DUPqWB_register_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPqWB_register_Asm_32, ARM_INS_VLD4, + {ARM_VLD4DUPqWB_register_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPqWB_register_Asm_8, ARM_INS_VLD4, + {ARM_VLD4DUPqWB_register_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNdAsm_16, ARM_INS_VLD4, + {ARM_VLD4LNdAsm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNdAsm_32, ARM_INS_VLD4, + {ARM_VLD4LNdAsm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNdAsm_8, ARM_INS_VLD4, + {ARM_VLD4LNdAsm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNdWB_fixed_Asm_16, ARM_INS_VLD4, + {ARM_VLD4LNdWB_fixed_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNdWB_fixed_Asm_32, ARM_INS_VLD4, + {ARM_VLD4LNdWB_fixed_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNdWB_fixed_Asm_8, ARM_INS_VLD4, + {ARM_VLD4LNdWB_fixed_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNdWB_register_Asm_16, ARM_INS_VLD4, + {ARM_VLD4LNdWB_register_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNdWB_register_Asm_32, ARM_INS_VLD4, + {ARM_VLD4LNdWB_register_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNdWB_register_Asm_8, ARM_INS_VLD4, + {ARM_VLD4LNdWB_register_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNqAsm_16, ARM_INS_VLD4, + {ARM_VLD4LNqAsm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNqAsm_32, ARM_INS_VLD4, + {ARM_VLD4LNqAsm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNqWB_fixed_Asm_16, ARM_INS_VLD4, + {ARM_VLD4LNqWB_fixed_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNqWB_fixed_Asm_32, ARM_INS_VLD4, + {ARM_VLD4LNqWB_fixed_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNqWB_register_Asm_16, ARM_INS_VLD4, + {ARM_VLD4LNqWB_register_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNqWB_register_Asm_32, ARM_INS_VLD4, + {ARM_VLD4LNqWB_register_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4dAsm_16, ARM_INS_VLD4, + {ARM_VLD4dAsm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4dAsm_32, ARM_INS_VLD4, + {ARM_VLD4dAsm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4dAsm_8, ARM_INS_VLD4, + {ARM_VLD4dAsm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4dWB_fixed_Asm_16, ARM_INS_VLD4, + {ARM_VLD4dWB_fixed_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4dWB_fixed_Asm_32, ARM_INS_VLD4, + {ARM_VLD4dWB_fixed_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4dWB_fixed_Asm_8, ARM_INS_VLD4, + {ARM_VLD4dWB_fixed_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4dWB_register_Asm_16, ARM_INS_VLD4, + {ARM_VLD4dWB_register_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4dWB_register_Asm_32, ARM_INS_VLD4, + {ARM_VLD4dWB_register_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4dWB_register_Asm_8, ARM_INS_VLD4, + {ARM_VLD4dWB_register_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4qAsm_16, ARM_INS_VLD4, + {ARM_VLD4qAsm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4qAsm_32, ARM_INS_VLD4, + {ARM_VLD4qAsm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4qAsm_8, ARM_INS_VLD4, + {ARM_VLD4qAsm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4qWB_fixed_Asm_16, ARM_INS_VLD4, + {ARM_VLD4qWB_fixed_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4qWB_fixed_Asm_32, ARM_INS_VLD4, + {ARM_VLD4qWB_fixed_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4qWB_fixed_Asm_8, ARM_INS_VLD4, + {ARM_VLD4qWB_fixed_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4qWB_register_Asm_16, ARM_INS_VLD4, + {ARM_VLD4qWB_register_Asm_16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4qWB_register_Asm_32, ARM_INS_VLD4, + {ARM_VLD4qWB_register_Asm_32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4qWB_register_Asm_8, ARM_INS_VLD4, + {ARM_VLD4qWB_register_Asm_8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNdAsm_16, ARM_INS_VST1, + {ARM_VST1LNdAsm_16, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNdAsm_32, ARM_INS_VST1, + {ARM_VST1LNdAsm_32, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNdAsm_8, ARM_INS_VST1, + {ARM_VST1LNdAsm_8, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNdWB_fixed_Asm_16, ARM_INS_VST1, + {ARM_VST1LNdWB_fixed_Asm_16, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNdWB_fixed_Asm_32, ARM_INS_VST1, + {ARM_VST1LNdWB_fixed_Asm_32, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNdWB_fixed_Asm_8, ARM_INS_VST1, + {ARM_VST1LNdWB_fixed_Asm_8, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNdWB_register_Asm_16, ARM_INS_VST1, + {ARM_VST1LNdWB_register_Asm_16, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNdWB_register_Asm_32, ARM_INS_VST1, + {ARM_VST1LNdWB_register_Asm_32, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNdWB_register_Asm_8, ARM_INS_VST1, + {ARM_VST1LNdWB_register_Asm_8, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNdAsm_16, ARM_INS_VST2, + {ARM_VST2LNdAsm_16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNdAsm_32, ARM_INS_VST2, + {ARM_VST2LNdAsm_32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNdAsm_8, ARM_INS_VST2, + {ARM_VST2LNdAsm_8, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNdWB_fixed_Asm_16, ARM_INS_VST2, + {ARM_VST2LNdWB_fixed_Asm_16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNdWB_fixed_Asm_32, ARM_INS_VST2, + {ARM_VST2LNdWB_fixed_Asm_32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNdWB_fixed_Asm_8, ARM_INS_VST2, + {ARM_VST2LNdWB_fixed_Asm_8, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNdWB_register_Asm_16, ARM_INS_VST2, + {ARM_VST2LNdWB_register_Asm_16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNdWB_register_Asm_32, ARM_INS_VST2, + {ARM_VST2LNdWB_register_Asm_32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNdWB_register_Asm_8, ARM_INS_VST2, + {ARM_VST2LNdWB_register_Asm_8, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNqAsm_16, ARM_INS_VST2, + {ARM_VST2LNqAsm_16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNqAsm_32, ARM_INS_VST2, + {ARM_VST2LNqAsm_32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNqWB_fixed_Asm_16, ARM_INS_VST2, + {ARM_VST2LNqWB_fixed_Asm_16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNqWB_fixed_Asm_32, ARM_INS_VST2, + {ARM_VST2LNqWB_fixed_Asm_32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNqWB_register_Asm_16, ARM_INS_VST2, + {ARM_VST2LNqWB_register_Asm_16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNqWB_register_Asm_32, ARM_INS_VST2, + {ARM_VST2LNqWB_register_Asm_32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNdAsm_16, ARM_INS_VST3, + {ARM_VST3LNdAsm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNdAsm_32, ARM_INS_VST3, + {ARM_VST3LNdAsm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNdAsm_8, ARM_INS_VST3, + {ARM_VST3LNdAsm_8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNdWB_fixed_Asm_16, ARM_INS_VST3, + {ARM_VST3LNdWB_fixed_Asm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNdWB_fixed_Asm_32, ARM_INS_VST3, + {ARM_VST3LNdWB_fixed_Asm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNdWB_fixed_Asm_8, ARM_INS_VST3, + {ARM_VST3LNdWB_fixed_Asm_8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNdWB_register_Asm_16, ARM_INS_VST3, + {ARM_VST3LNdWB_register_Asm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNdWB_register_Asm_32, ARM_INS_VST3, + {ARM_VST3LNdWB_register_Asm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNdWB_register_Asm_8, ARM_INS_VST3, + {ARM_VST3LNdWB_register_Asm_8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNqAsm_16, ARM_INS_VST3, + {ARM_VST3LNqAsm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNqAsm_32, ARM_INS_VST3, + {ARM_VST3LNqAsm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNqWB_fixed_Asm_16, ARM_INS_VST3, + {ARM_VST3LNqWB_fixed_Asm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNqWB_fixed_Asm_32, ARM_INS_VST3, + {ARM_VST3LNqWB_fixed_Asm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNqWB_register_Asm_16, ARM_INS_VST3, + {ARM_VST3LNqWB_register_Asm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNqWB_register_Asm_32, ARM_INS_VST3, + {ARM_VST3LNqWB_register_Asm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3dAsm_16, ARM_INS_VST3, + {ARM_VST3dAsm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3dAsm_32, ARM_INS_VST3, + {ARM_VST3dAsm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3dAsm_8, ARM_INS_VST3, + {ARM_VST3dAsm_8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3dWB_fixed_Asm_16, ARM_INS_VST3, + {ARM_VST3dWB_fixed_Asm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3dWB_fixed_Asm_32, ARM_INS_VST3, + {ARM_VST3dWB_fixed_Asm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3dWB_fixed_Asm_8, ARM_INS_VST3, + {ARM_VST3dWB_fixed_Asm_8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3dWB_register_Asm_16, ARM_INS_VST3, + {ARM_VST3dWB_register_Asm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3dWB_register_Asm_32, ARM_INS_VST3, + {ARM_VST3dWB_register_Asm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3dWB_register_Asm_8, ARM_INS_VST3, + {ARM_VST3dWB_register_Asm_8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3qAsm_16, ARM_INS_VST3, + {ARM_VST3qAsm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3qAsm_32, ARM_INS_VST3, + {ARM_VST3qAsm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3qAsm_8, ARM_INS_VST3, + {ARM_VST3qAsm_8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3qWB_fixed_Asm_16, ARM_INS_VST3, + {ARM_VST3qWB_fixed_Asm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3qWB_fixed_Asm_32, ARM_INS_VST3, + {ARM_VST3qWB_fixed_Asm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3qWB_fixed_Asm_8, ARM_INS_VST3, + {ARM_VST3qWB_fixed_Asm_8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3qWB_register_Asm_16, ARM_INS_VST3, + {ARM_VST3qWB_register_Asm_16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3qWB_register_Asm_32, ARM_INS_VST3, + {ARM_VST3qWB_register_Asm_32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3qWB_register_Asm_8, ARM_INS_VST3, + {ARM_VST3qWB_register_Asm_8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNdAsm_16, ARM_INS_VST4, + {ARM_VST4LNdAsm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNdAsm_32, ARM_INS_VST4, + {ARM_VST4LNdAsm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNdAsm_8, ARM_INS_VST4, + {ARM_VST4LNdAsm_8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNdWB_fixed_Asm_16, ARM_INS_VST4, + {ARM_VST4LNdWB_fixed_Asm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNdWB_fixed_Asm_32, ARM_INS_VST4, + {ARM_VST4LNdWB_fixed_Asm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNdWB_fixed_Asm_8, ARM_INS_VST4, + {ARM_VST4LNdWB_fixed_Asm_8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNdWB_register_Asm_16, ARM_INS_VST4, + {ARM_VST4LNdWB_register_Asm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNdWB_register_Asm_32, ARM_INS_VST4, + {ARM_VST4LNdWB_register_Asm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNdWB_register_Asm_8, ARM_INS_VST4, + {ARM_VST4LNdWB_register_Asm_8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNqAsm_16, ARM_INS_VST4, + {ARM_VST4LNqAsm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNqAsm_32, ARM_INS_VST4, + {ARM_VST4LNqAsm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNqWB_fixed_Asm_16, ARM_INS_VST4, + {ARM_VST4LNqWB_fixed_Asm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNqWB_fixed_Asm_32, ARM_INS_VST4, + {ARM_VST4LNqWB_fixed_Asm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNqWB_register_Asm_16, ARM_INS_VST4, + {ARM_VST4LNqWB_register_Asm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNqWB_register_Asm_32, ARM_INS_VST4, + {ARM_VST4LNqWB_register_Asm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4dAsm_16, ARM_INS_VST4, + {ARM_VST4dAsm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4dAsm_32, ARM_INS_VST4, + {ARM_VST4dAsm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4dAsm_8, ARM_INS_VST4, + {ARM_VST4dAsm_8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4dWB_fixed_Asm_16, ARM_INS_VST4, + {ARM_VST4dWB_fixed_Asm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4dWB_fixed_Asm_32, ARM_INS_VST4, + {ARM_VST4dWB_fixed_Asm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4dWB_fixed_Asm_8, ARM_INS_VST4, + {ARM_VST4dWB_fixed_Asm_8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4dWB_register_Asm_16, ARM_INS_VST4, + {ARM_VST4dWB_register_Asm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4dWB_register_Asm_32, ARM_INS_VST4, + {ARM_VST4dWB_register_Asm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4dWB_register_Asm_8, ARM_INS_VST4, + {ARM_VST4dWB_register_Asm_8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4qAsm_16, ARM_INS_VST4, + {ARM_VST4qAsm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4qAsm_32, ARM_INS_VST4, + {ARM_VST4qAsm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4qAsm_8, ARM_INS_VST4, + {ARM_VST4qAsm_8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4qWB_fixed_Asm_16, ARM_INS_VST4, + {ARM_VST4qWB_fixed_Asm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4qWB_fixed_Asm_32, ARM_INS_VST4, + {ARM_VST4qWB_fixed_Asm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4qWB_fixed_Asm_8, ARM_INS_VST4, + {ARM_VST4qWB_fixed_Asm_8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4qWB_register_Asm_16, ARM_INS_VST4, + {ARM_VST4qWB_register_Asm_16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4qWB_register_Asm_32, ARM_INS_VST4, + {ARM_VST4qWB_register_Asm_32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4qWB_register_Asm_8, ARM_INS_VST4, + {ARM_VST4qWB_register_Asm_8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRBpcrel, ARM_INS_LDRB, + {ARM_t2LDRBpcrel, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRConstPool, ARM_INS_LDR, + {ARM_t2LDRConstPool, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRHpcrel, ARM_INS_LDRH, + {ARM_t2LDRHpcrel, + ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSBpcrel, ARM_INS_LDRSB, + {ARM_t2LDRSBpcrel, + ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSHpcrel, ARM_INS_LDRSH, + {ARM_t2LDRSHpcrel, + ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRpcrel, ARM_INS_LDR, + {ARM_t2LDRpcrel, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MOVSsi, ARM_INS_MOVS, + {ARM_t2MOVSsi, + ARM_INS_MOVS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MOVSsr, ARM_INS_MOVS, + {ARM_t2MOVSsr, + ARM_INS_MOVS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MOVsi, ARM_INS_MOV, + {ARM_t2MOVsi, + ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MOVsr, ARM_INS_MOV, + {ARM_t2MOVsr, + ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_tLDRConstPool, ARM_INS_LDR, + {ARM_tLDRConstPool, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_ADCri, ARM_INS_ADC, + {ARM_ADCri, + ARM_INS_ADC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_ADCrr, ARM_INS_ADC, + {ARM_ADCrr, + ARM_INS_ADC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_ADCrsi, ARM_INS_ADC, + {ARM_ADCrsi, + ARM_INS_ADC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_ADCrsr, ARM_INS_ADC, + {ARM_ADCrsr, + ARM_INS_ADC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_ADDri, ARM_INS_ADD, + {ARM_ADDri, ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ADDrr, ARM_INS_ADD, + {ARM_ADDrr, ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ADDrsi, ARM_INS_ADD, + {ARM_ADDrsi, ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ADDrsr, ARM_INS_ADD, + {ARM_ADDrsr, ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ADR, ARM_INS_ADR, + {ARM_ADR, ARM_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_AESD, ARM_INS_AESD, + {ARM_AESD, ARM_INS_AESD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, 0, + 0 #endif -}, + }, -{ - ARM_AESE, ARM_INS_AESE, + {ARM_AESE, ARM_INS_AESE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, 0, + 0 #endif -}, + }, -{ - ARM_AESIMC, ARM_INS_AESIMC, + {ARM_AESIMC, + ARM_INS_AESIMC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_AESMC, ARM_INS_AESMC, + {ARM_AESMC, ARM_INS_AESMC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ANDri, ARM_INS_AND, + {ARM_ANDri, ARM_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ANDrr, ARM_INS_AND, + {ARM_ANDrr, ARM_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ANDrsi, ARM_INS_AND, + {ARM_ANDrsi, ARM_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ANDrsr, ARM_INS_AND, + {ARM_ANDrsr, ARM_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_BFC, ARM_INS_BFC, + {ARM_BFC, ARM_INS_BFC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6T2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_BFI, ARM_INS_BFI, + {ARM_BFI, ARM_INS_BFI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6T2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_BICri, ARM_INS_BIC, + {ARM_BICri, ARM_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_BICrr, ARM_INS_BIC, + {ARM_BICrr, ARM_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_BICrsi, ARM_INS_BIC, + {ARM_BICrsi, ARM_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_BICrsr, ARM_INS_BIC, + {ARM_BICrsr, ARM_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_BKPT, ARM_INS_BKPT, + {ARM_BKPT, ARM_INS_BKPT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_BL, ARM_INS_BL, + {ARM_BL, + ARM_INS_BL, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 + {ARM_REG_PC, 0}, + {ARM_REG_LR, ARM_REG_PC, 0}, + {ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0}, + 1, + 0 #endif -}, + }, -{ - ARM_BLX, ARM_INS_BLX, + {ARM_BLX, + ARM_INS_BLX, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_V5T, 0 }, 0, 1 + {ARM_REG_PC, 0}, + {ARM_REG_LR, ARM_REG_PC, 0}, + {ARM_GRP_CALL, ARM_GRP_V5T, 0}, + 0, + 1 #endif -}, + }, -{ - ARM_BLX_pred, ARM_INS_BLX, + {ARM_BLX_pred, + ARM_INS_BLX, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 1 + {ARM_REG_PC, 0}, + {ARM_REG_LR, ARM_REG_PC, 0}, + {ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0}, + 0, + 1 #endif -}, + }, -{ - ARM_BLXi, ARM_INS_BLX, + {ARM_BLXi, + ARM_INS_BLX, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0 + {ARM_REG_PC, 0}, + {ARM_REG_LR, ARM_REG_PC, 0}, + {ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, 0}, + 1, + 0 #endif -}, + }, -{ - ARM_BL_pred, ARM_INS_BL, + {ARM_BL_pred, + ARM_INS_BL, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 + {ARM_REG_PC, 0}, + {ARM_REG_LR, ARM_REG_PC, 0}, + {ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0}, + 1, + 0 #endif -}, + }, -{ - ARM_BX, ARM_INS_BX, + {ARM_BX, ARM_INS_BX, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 + {0}, {ARM_REG_PC, 0}, {ARM_GRP_ARM, ARM_GRP_V4T, 0}, 0, + 1 #endif -}, + }, -{ - ARM_BXJ, ARM_INS_BXJ, + {ARM_BXJ, ARM_INS_BXJ, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, 0 }, 0, 1 + {0}, {ARM_REG_PC, 0}, {ARM_GRP_ARM, 0}, 0, + 1 #endif -}, + }, -{ - ARM_BX_RET, ARM_INS_BX, + {ARM_BX_RET, ARM_INS_BX, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 + {0}, {ARM_REG_PC, 0}, {ARM_GRP_ARM, ARM_GRP_V4T, 0}, 0, + 1 #endif -}, + }, -{ - ARM_BX_pred, ARM_INS_BX, + {ARM_BX_pred, + ARM_INS_BX, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 + {0}, + {ARM_REG_PC, 0}, + {ARM_GRP_ARM, ARM_GRP_V4T, 0}, + 0, + 1 #endif -}, + }, -{ - ARM_Bcc, ARM_INS_B, + {ARM_Bcc, + ARM_INS_B, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 + {ARM_REG_PC, 0}, + {ARM_REG_PC, 0}, + {ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0}, + 1, + 0 #endif -}, + }, -{ - ARM_CDP, ARM_INS_CDP, + {ARM_CDP, ARM_INS_CDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CDP2, ARM_INS_CDP2, + {ARM_CDP2, ARM_INS_CDP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CLREX, ARM_INS_CLREX, + {ARM_CLREX, ARM_INS_CLREX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V7, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CLZ, ARM_INS_CLZ, + {ARM_CLZ, ARM_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V5T, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CMNri, ARM_INS_CMN, + {ARM_CMNri, ARM_INS_CMN, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CMNzrr, ARM_INS_CMN, + {ARM_CMNzrr, ARM_INS_CMN, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CMNzrsi, ARM_INS_CMN, + {ARM_CMNzrsi, + ARM_INS_CMN, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_CMNzrsr, ARM_INS_CMN, + {ARM_CMNzrsr, + ARM_INS_CMN, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_CMPri, ARM_INS_CMP, + {ARM_CMPri, ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CMPrr, ARM_INS_CMP, + {ARM_CMPrr, ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CMPrsi, ARM_INS_CMP, + {ARM_CMPrsi, ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CMPrsr, ARM_INS_CMP, + {ARM_CMPrsr, ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CPS1p, ARM_INS_CPS, + {ARM_CPS1p, ARM_INS_CPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CPS2p, ARM_INS_CPS, + {ARM_CPS2p, ARM_INS_CPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CPS3p, ARM_INS_CPS, + {ARM_CPS3p, ARM_INS_CPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_CRC32B, ARM_INS_CRC32B, + {ARM_CRC32B, + ARM_INS_CRC32B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_CRC32CB, ARM_INS_CRC32CB, + {ARM_CRC32CB, + ARM_INS_CRC32CB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_CRC32CH, ARM_INS_CRC32CH, + {ARM_CRC32CH, + ARM_INS_CRC32CH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_CRC32CW, ARM_INS_CRC32CW, + {ARM_CRC32CW, + ARM_INS_CRC32CW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_CRC32H, ARM_INS_CRC32H, + {ARM_CRC32H, + ARM_INS_CRC32H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_CRC32W, ARM_INS_CRC32W, + {ARM_CRC32W, + ARM_INS_CRC32W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_DBG, ARM_INS_DBG, + {ARM_DBG, ARM_INS_DBG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V7, 0}, 0, + 0 #endif -}, + }, -{ - ARM_DMB, ARM_INS_DMB, + {ARM_DMB, ARM_INS_DMB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0}, 0, + 0 #endif -}, + }, -{ - ARM_DSB, ARM_INS_DSB, + {ARM_DSB, ARM_INS_DSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0}, 0, + 0 #endif -}, + }, -{ - ARM_EORri, ARM_INS_EOR, + {ARM_EORri, ARM_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_EORrr, ARM_INS_EOR, + {ARM_EORrr, ARM_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_EORrsi, ARM_INS_EOR, + {ARM_EORrsi, ARM_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_EORrsr, ARM_INS_EOR, + {ARM_EORrsr, ARM_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ERET, ARM_INS_ERET, + {ARM_ERET, ARM_INS_ERET, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 + {0}, {ARM_REG_PC, 0}, {ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0}, 0, + 0 #endif -}, + }, -{ - ARM_FCONSTD, ARM_INS_FCONSTD, + {ARM_FCONSTD, + ARM_INS_FCONSTD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP3, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_FCONSTH, ARM_INS_VMOV, + {ARM_FCONSTH, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_FCONSTS, ARM_INS_FCONSTS, + {ARM_FCONSTS, + ARM_INS_FCONSTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP3, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX, + {ARM_FLDMXDB_UPD, + ARM_INS_FLDMDBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_FLDMXIA, ARM_INS_FLDMIAX, + {ARM_FLDMXIA, + ARM_INS_FLDMIAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX, + {ARM_FLDMXIA_UPD, + ARM_INS_FLDMIAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_FMSTAT, ARM_INS_FMSTAT, + {ARM_FMSTAT, + ARM_INS_FMSTAT, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {ARM_REG_FPSCR_NZCV, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX, + {ARM_FSTMXDB_UPD, + ARM_INS_FSTMDBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_FSTMXIA, ARM_INS_FSTMIAX, + {ARM_FSTMXIA, + ARM_INS_FSTMIAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX, + {ARM_FSTMXIA_UPD, + ARM_INS_FSTMIAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_HINT, ARM_INS_HINT, + {ARM_HINT, ARM_INS_HINT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_HLT, ARM_INS_HLT, + {ARM_HLT, ARM_INS_HLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_HVC, ARM_INS_HVC, + {ARM_HVC, ARM_INS_HVC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ISB, ARM_INS_ISB, + {ARM_ISB, ARM_INS_ISB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDA, ARM_INS_LDA, + {ARM_LDA, ARM_INS_LDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDAB, ARM_INS_LDAB, + {ARM_LDAB, ARM_INS_LDAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDAEX, ARM_INS_LDAEX, + {ARM_LDAEX, ARM_INS_LDAEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDAEXB, ARM_INS_LDAEXB, + {ARM_LDAEXB, + ARM_INS_LDAEXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDAEXD, ARM_INS_LDAEXD, + {ARM_LDAEXD, + ARM_INS_LDAEXD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDAEXH, ARM_INS_LDAEXH, + {ARM_LDAEXH, + ARM_INS_LDAEXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDAH, ARM_INS_LDAH, + {ARM_LDAH, ARM_INS_LDAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDC2L_OFFSET, ARM_INS_LDC2L, + {ARM_LDC2L_OFFSET, + ARM_INS_LDC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC2L_OPTION, ARM_INS_LDC2L, + {ARM_LDC2L_OPTION, + ARM_INS_LDC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC2L_POST, ARM_INS_LDC2L, + {ARM_LDC2L_POST, + ARM_INS_LDC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC2L_PRE, ARM_INS_LDC2L, + {ARM_LDC2L_PRE, + ARM_INS_LDC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC2_OFFSET, ARM_INS_LDC2, + {ARM_LDC2_OFFSET, + ARM_INS_LDC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC2_OPTION, ARM_INS_LDC2, + {ARM_LDC2_OPTION, + ARM_INS_LDC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC2_POST, ARM_INS_LDC2, + {ARM_LDC2_POST, + ARM_INS_LDC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC2_PRE, ARM_INS_LDC2, + {ARM_LDC2_PRE, + ARM_INS_LDC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDCL_OFFSET, ARM_INS_LDCL, + {ARM_LDCL_OFFSET, + ARM_INS_LDCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDCL_OPTION, ARM_INS_LDCL, + {ARM_LDCL_OPTION, + ARM_INS_LDCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDCL_POST, ARM_INS_LDCL, + {ARM_LDCL_POST, + ARM_INS_LDCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDCL_PRE, ARM_INS_LDCL, + {ARM_LDCL_PRE, + ARM_INS_LDCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC_OFFSET, ARM_INS_LDC, + {ARM_LDC_OFFSET, + ARM_INS_LDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC_OPTION, ARM_INS_LDC, + {ARM_LDC_OPTION, + ARM_INS_LDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC_POST, ARM_INS_LDC, + {ARM_LDC_POST, + ARM_INS_LDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDC_PRE, ARM_INS_LDC, + {ARM_LDC_PRE, + ARM_INS_LDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDMDA, ARM_INS_LDMDA, + {ARM_LDMDA, ARM_INS_LDMDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDMDA_UPD, ARM_INS_LDMDA, + {ARM_LDMDA_UPD, + ARM_INS_LDMDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDMDB, ARM_INS_LDMDB, + {ARM_LDMDB, ARM_INS_LDMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDMDB_UPD, ARM_INS_LDMDB, + {ARM_LDMDB_UPD, + ARM_INS_LDMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDMIA, ARM_INS_LDM, + {ARM_LDMIA, ARM_INS_LDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDMIA_UPD, ARM_INS_LDM, + {ARM_LDMIA_UPD, + ARM_INS_LDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDMIB, ARM_INS_LDMIB, + {ARM_LDMIB, ARM_INS_LDMIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDMIB_UPD, ARM_INS_LDMIB, + {ARM_LDMIB_UPD, + ARM_INS_LDMIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRBT_POST_IMM, ARM_INS_LDRBT, + {ARM_LDRBT_POST_IMM, + ARM_INS_LDRBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRBT_POST_REG, ARM_INS_LDRBT, + {ARM_LDRBT_POST_REG, + ARM_INS_LDRBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRB_POST_IMM, ARM_INS_LDRB, + {ARM_LDRB_POST_IMM, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRB_POST_REG, ARM_INS_LDRB, + {ARM_LDRB_POST_REG, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRB_PRE_IMM, ARM_INS_LDRB, + {ARM_LDRB_PRE_IMM, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRB_PRE_REG, ARM_INS_LDRB, + {ARM_LDRB_PRE_REG, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRBi12, ARM_INS_LDRB, + {ARM_LDRBi12, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRBrs, ARM_INS_LDRB, + {ARM_LDRBrs, ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDRD, ARM_INS_LDRD, + {ARM_LDRD, ARM_INS_LDRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDRD_POST, ARM_INS_LDRD, + {ARM_LDRD_POST, + ARM_INS_LDRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRD_PRE, ARM_INS_LDRD, + {ARM_LDRD_PRE, + ARM_INS_LDRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDREX, ARM_INS_LDREX, + {ARM_LDREX, ARM_INS_LDREX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDREXB, ARM_INS_LDREXB, + {ARM_LDREXB, + ARM_INS_LDREXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDREXD, ARM_INS_LDREXD, + {ARM_LDREXD, + ARM_INS_LDREXD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDREXH, ARM_INS_LDREXH, + {ARM_LDREXH, + ARM_INS_LDREXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRH, ARM_INS_LDRH, + {ARM_LDRH, ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDRHTi, ARM_INS_LDRHT, + {ARM_LDRHTi, ARM_INS_LDRHT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDRHTr, ARM_INS_LDRHT, + {ARM_LDRHTr, ARM_INS_LDRHT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDRH_POST, ARM_INS_LDRH, + {ARM_LDRH_POST, + ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRH_PRE, ARM_INS_LDRH, + {ARM_LDRH_PRE, + ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRSB, ARM_INS_LDRSB, + {ARM_LDRSB, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDRSBTi, ARM_INS_LDRSBT, + {ARM_LDRSBTi, + ARM_INS_LDRSBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRSBTr, ARM_INS_LDRSBT, + {ARM_LDRSBTr, + ARM_INS_LDRSBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRSB_POST, ARM_INS_LDRSB, + {ARM_LDRSB_POST, + ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRSB_PRE, ARM_INS_LDRSB, + {ARM_LDRSB_PRE, + ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRSH, ARM_INS_LDRSH, + {ARM_LDRSH, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDRSHTi, ARM_INS_LDRSHT, + {ARM_LDRSHTi, + ARM_INS_LDRSHT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRSHTr, ARM_INS_LDRSHT, + {ARM_LDRSHTr, + ARM_INS_LDRSHT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRSH_POST, ARM_INS_LDRSH, + {ARM_LDRSH_POST, + ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRSH_PRE, ARM_INS_LDRSH, + {ARM_LDRSH_PRE, + ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRT_POST_IMM, ARM_INS_LDRT, + {ARM_LDRT_POST_IMM, + ARM_INS_LDRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRT_POST_REG, ARM_INS_LDRT, + {ARM_LDRT_POST_REG, + ARM_INS_LDRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDR_POST_IMM, ARM_INS_LDR, + {ARM_LDR_POST_IMM, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDR_POST_REG, ARM_INS_LDR, + {ARM_LDR_POST_REG, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDR_PRE_IMM, ARM_INS_LDR, + {ARM_LDR_PRE_IMM, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDR_PRE_REG, ARM_INS_LDR, + {ARM_LDR_PRE_REG, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_LDRcp, ARM_INS_LDR, + {ARM_LDRcp, ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDRi12, ARM_INS_LDR, + {ARM_LDRi12, ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_LDRrs, ARM_INS_LDR, + {ARM_LDRrs, ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MCR, ARM_INS_MCR, + {ARM_MCR, ARM_INS_MCR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MCR2, ARM_INS_MCR2, + {ARM_MCR2, ARM_INS_MCR2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MCRR, ARM_INS_MCRR, + {ARM_MCRR, ARM_INS_MCRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MCRR2, ARM_INS_MCRR2, + {ARM_MCRR2, ARM_INS_MCRR2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MLA, ARM_INS_MLA, + {ARM_MLA, ARM_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MLS, ARM_INS_MLS, + {ARM_MLS, ARM_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MOVPCLR, ARM_INS_MOV, + {ARM_MOVPCLR, + ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_MOVTi16, ARM_INS_MOVT, + {ARM_MOVTi16, + ARM_INS_MOVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6T2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_MOVi, ARM_INS_MOV, + {ARM_MOVi, ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MOVi16, ARM_INS_MOV, + {ARM_MOVi16, ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6T2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MOVr, ARM_INS_MOV, + {ARM_MOVr, ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MOVr_TC, ARM_INS_MOV, + {ARM_MOVr_TC, + ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_MOVsi, ARM_INS_MOV, + {ARM_MOVsi, ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MOVsr, ARM_INS_MOV, + {ARM_MOVsr, ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MRC, ARM_INS_MRC, + {ARM_MRC, ARM_INS_MRC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MRC2, ARM_INS_MRC2, + {ARM_MRC2, ARM_INS_MRC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MRRC, ARM_INS_MRRC, + {ARM_MRRC, ARM_INS_MRRC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MRRC2, ARM_INS_MRRC2, + {ARM_MRRC2, ARM_INS_MRRC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PREV8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MRS, ARM_INS_MRS, + {ARM_MRS, ARM_INS_MRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MRSbanked, ARM_INS_MRS, + {ARM_MRSbanked, + ARM_INS_MRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_MRSsys, ARM_INS_MRS, + {ARM_MRSsys, ARM_INS_MRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MSR, ARM_INS_MSR, + {ARM_MSR, ARM_INS_MSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MSRbanked, ARM_INS_MSR, + {ARM_MSRbanked, + ARM_INS_MSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_MSRi, ARM_INS_MSR, + {ARM_MSRi, ARM_INS_MSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MUL, ARM_INS_MUL, + {ARM_MUL, ARM_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MVNi, ARM_INS_MVN, + {ARM_MVNi, ARM_INS_MVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MVNr, ARM_INS_MVN, + {ARM_MVNr, ARM_INS_MVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MVNsi, ARM_INS_MVN, + {ARM_MVNsi, ARM_INS_MVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_MVNsr, ARM_INS_MVN, + {ARM_MVNsr, ARM_INS_MVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ORRri, ARM_INS_ORR, + {ARM_ORRri, ARM_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ORRrr, ARM_INS_ORR, + {ARM_ORRrr, ARM_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ORRrsi, ARM_INS_ORR, + {ARM_ORRrsi, ARM_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_ORRrsr, ARM_INS_ORR, + {ARM_ORRrsr, ARM_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_PKHBT, ARM_INS_PKHBT, + {ARM_PKHBT, ARM_INS_PKHBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_PKHTB, ARM_INS_PKHTB, + {ARM_PKHTB, ARM_INS_PKHTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_PLDWi12, ARM_INS_PLDW, + {ARM_PLDWi12, + ARM_INS_PLDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_PLDWrs, ARM_INS_PLDW, + {ARM_PLDWrs, ARM_INS_PLDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0}, 0, + 0 #endif -}, + }, -{ - ARM_PLDi12, ARM_INS_PLD, + {ARM_PLDi12, ARM_INS_PLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_PLDrs, ARM_INS_PLD, + {ARM_PLDrs, ARM_INS_PLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_PLIi12, ARM_INS_PLI, + {ARM_PLIi12, ARM_INS_PLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V7, 0}, 0, + 0 #endif -}, + }, -{ - ARM_PLIrs, ARM_INS_PLI, + {ARM_PLIrs, ARM_INS_PLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V7, 0}, 0, + 0 #endif -}, + }, -{ - ARM_QADD, ARM_INS_QADD, + {ARM_QADD, ARM_INS_QADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_QADD16, ARM_INS_QADD16, + {ARM_QADD16, + ARM_INS_QADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_QADD8, ARM_INS_QADD8, + {ARM_QADD8, ARM_INS_QADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_QASX, ARM_INS_QASX, + {ARM_QASX, ARM_INS_QASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_QDADD, ARM_INS_QDADD, + {ARM_QDADD, ARM_INS_QDADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_QDSUB, ARM_INS_QDSUB, + {ARM_QDSUB, ARM_INS_QDSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_QSAX, ARM_INS_QSAX, + {ARM_QSAX, ARM_INS_QSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_QSUB, ARM_INS_QSUB, + {ARM_QSUB, ARM_INS_QSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_QSUB16, ARM_INS_QSUB16, + {ARM_QSUB16, + ARM_INS_QSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_QSUB8, ARM_INS_QSUB8, + {ARM_QSUB8, ARM_INS_QSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RBIT, ARM_INS_RBIT, + {ARM_RBIT, ARM_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6T2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_REV, ARM_INS_REV, + {ARM_REV, ARM_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_REV16, ARM_INS_REV16, + {ARM_REV16, ARM_INS_REV16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_REVSH, ARM_INS_REVSH, + {ARM_REVSH, ARM_INS_REVSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RFEDA, ARM_INS_RFEDA, + {ARM_RFEDA, ARM_INS_RFEDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RFEDA_UPD, ARM_INS_RFEDA, + {ARM_RFEDA_UPD, + ARM_INS_RFEDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_RFEDB, ARM_INS_RFEDB, + {ARM_RFEDB, ARM_INS_RFEDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RFEDB_UPD, ARM_INS_RFEDB, + {ARM_RFEDB_UPD, + ARM_INS_RFEDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_RFEIA, ARM_INS_RFEIA, + {ARM_RFEIA, ARM_INS_RFEIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RFEIA_UPD, ARM_INS_RFEIA, + {ARM_RFEIA_UPD, + ARM_INS_RFEIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_RFEIB, ARM_INS_RFEIB, + {ARM_RFEIB, ARM_INS_RFEIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RFEIB_UPD, ARM_INS_RFEIB, + {ARM_RFEIB_UPD, + ARM_INS_RFEIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_RSBri, ARM_INS_RSB, + {ARM_RSBri, ARM_INS_RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RSBrr, ARM_INS_RSB, + {ARM_RSBrr, ARM_INS_RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RSBrsi, ARM_INS_RSB, + {ARM_RSBrsi, ARM_INS_RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RSBrsr, ARM_INS_RSB, + {ARM_RSBrsr, ARM_INS_RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_RSCri, ARM_INS_RSC, + {ARM_RSCri, + ARM_INS_RSC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_RSCrr, ARM_INS_RSC, + {ARM_RSCrr, + ARM_INS_RSC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_RSCrsi, ARM_INS_RSC, + {ARM_RSCrsi, + ARM_INS_RSC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_RSCrsr, ARM_INS_RSC, + {ARM_RSCrsr, + ARM_INS_RSC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SADD16, ARM_INS_SADD16, + {ARM_SADD16, + ARM_INS_SADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SADD8, ARM_INS_SADD8, + {ARM_SADD8, ARM_INS_SADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SASX, ARM_INS_SASX, + {ARM_SASX, ARM_INS_SASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SBCri, ARM_INS_SBC, + {ARM_SBCri, + ARM_INS_SBC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SBCrr, ARM_INS_SBC, + {ARM_SBCrr, + ARM_INS_SBC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SBCrsi, ARM_INS_SBC, + {ARM_SBCrsi, + ARM_INS_SBC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SBCrsr, ARM_INS_SBC, + {ARM_SBCrsr, + ARM_INS_SBC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SBFX, ARM_INS_SBFX, + {ARM_SBFX, ARM_INS_SBFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6T2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SDIV, ARM_INS_SDIV, + {ARM_SDIV, ARM_INS_SDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SEL, ARM_INS_SEL, + {ARM_SEL, ARM_INS_SEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SETEND, ARM_INS_SETEND, + {ARM_SETEND, + ARM_INS_SETEND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SETPAN, ARM_INS_SETPAN, + {ARM_SETPAN, ARM_INS_SETPAN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - ARM_SHA1C, ARM_INS_SHA1C, + {ARM_SHA1C, ARM_INS_SHA1C, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SHA1H, ARM_INS_SHA1H, + {ARM_SHA1H, ARM_INS_SHA1H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SHA1M, ARM_INS_SHA1M, + {ARM_SHA1M, ARM_INS_SHA1M, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SHA1P, ARM_INS_SHA1P, + {ARM_SHA1P, ARM_INS_SHA1P, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SHA1SU0, ARM_INS_SHA1SU0, + {ARM_SHA1SU0, + ARM_INS_SHA1SU0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SHA1SU1, ARM_INS_SHA1SU1, + {ARM_SHA1SU1, + ARM_INS_SHA1SU1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SHA256H, ARM_INS_SHA256H, + {ARM_SHA256H, + ARM_INS_SHA256H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SHA256H2, ARM_INS_SHA256H2, + {ARM_SHA256H2, + ARM_INS_SHA256H2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SHA256SU0, ARM_INS_SHA256SU0, + {ARM_SHA256SU0, + ARM_INS_SHA256SU0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SHA256SU1, ARM_INS_SHA256SU1, + {ARM_SHA256SU1, + ARM_INS_SHA256SU1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SHADD16, ARM_INS_SHADD16, + {ARM_SHADD16, + ARM_INS_SHADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SHADD8, ARM_INS_SHADD8, + {ARM_SHADD8, + ARM_INS_SHADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SHASX, ARM_INS_SHASX, + {ARM_SHASX, ARM_INS_SHASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SHSAX, ARM_INS_SHSAX, + {ARM_SHSAX, ARM_INS_SHSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SHSUB16, ARM_INS_SHSUB16, + {ARM_SHSUB16, + ARM_INS_SHSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SHSUB8, ARM_INS_SHSUB8, + {ARM_SHSUB8, + ARM_INS_SHSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMC, ARM_INS_SMC, + {ARM_SMC, + ARM_INS_SMC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PRIVILEGE, ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLABB, ARM_INS_SMLABB, + {ARM_SMLABB, + ARM_INS_SMLABB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLABT, ARM_INS_SMLABT, + {ARM_SMLABT, + ARM_INS_SMLABT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLAD, ARM_INS_SMLAD, + {ARM_SMLAD, ARM_INS_SMLAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SMLADX, ARM_INS_SMLADX, + {ARM_SMLADX, + ARM_INS_SMLADX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLAL, ARM_INS_SMLAL, + {ARM_SMLAL, ARM_INS_SMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SMLALBB, ARM_INS_SMLALBB, + {ARM_SMLALBB, + ARM_INS_SMLALBB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLALBT, ARM_INS_SMLALBT, + {ARM_SMLALBT, + ARM_INS_SMLALBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLALD, ARM_INS_SMLALD, + {ARM_SMLALD, + ARM_INS_SMLALD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLALDX, ARM_INS_SMLALDX, + {ARM_SMLALDX, + ARM_INS_SMLALDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLALTB, ARM_INS_SMLALTB, + {ARM_SMLALTB, + ARM_INS_SMLALTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLALTT, ARM_INS_SMLALTT, + {ARM_SMLALTT, + ARM_INS_SMLALTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLATB, ARM_INS_SMLATB, + {ARM_SMLATB, + ARM_INS_SMLATB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLATT, ARM_INS_SMLATT, + {ARM_SMLATT, + ARM_INS_SMLATT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLAWB, ARM_INS_SMLAWB, + {ARM_SMLAWB, + ARM_INS_SMLAWB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLAWT, ARM_INS_SMLAWT, + {ARM_SMLAWT, + ARM_INS_SMLAWT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLSD, ARM_INS_SMLSD, + {ARM_SMLSD, ARM_INS_SMLSD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SMLSDX, ARM_INS_SMLSDX, + {ARM_SMLSDX, + ARM_INS_SMLSDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLSLD, ARM_INS_SMLSLD, + {ARM_SMLSLD, + ARM_INS_SMLSLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMLSLDX, ARM_INS_SMLSLDX, + {ARM_SMLSLDX, + ARM_INS_SMLSLDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMMLA, ARM_INS_SMMLA, + {ARM_SMMLA, ARM_INS_SMMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SMMLAR, ARM_INS_SMMLAR, + {ARM_SMMLAR, + ARM_INS_SMMLAR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMMLS, ARM_INS_SMMLS, + {ARM_SMMLS, ARM_INS_SMMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SMMLSR, ARM_INS_SMMLSR, + {ARM_SMMLSR, + ARM_INS_SMMLSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMMUL, ARM_INS_SMMUL, + {ARM_SMMUL, ARM_INS_SMMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SMMULR, ARM_INS_SMMULR, + {ARM_SMMULR, + ARM_INS_SMMULR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMUAD, ARM_INS_SMUAD, + {ARM_SMUAD, ARM_INS_SMUAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SMUADX, ARM_INS_SMUADX, + {ARM_SMUADX, + ARM_INS_SMUADX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMULBB, ARM_INS_SMULBB, + {ARM_SMULBB, + ARM_INS_SMULBB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMULBT, ARM_INS_SMULBT, + {ARM_SMULBT, + ARM_INS_SMULBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMULL, ARM_INS_SMULL, + {ARM_SMULL, ARM_INS_SMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SMULTB, ARM_INS_SMULTB, + {ARM_SMULTB, + ARM_INS_SMULTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMULTT, ARM_INS_SMULTT, + {ARM_SMULTT, + ARM_INS_SMULTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMULWB, ARM_INS_SMULWB, + {ARM_SMULWB, + ARM_INS_SMULWB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMULWT, ARM_INS_SMULWT, + {ARM_SMULWT, + ARM_INS_SMULWT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SMUSD, ARM_INS_SMUSD, + {ARM_SMUSD, ARM_INS_SMUSD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SMUSDX, ARM_INS_SMUSDX, + {ARM_SMUSDX, + ARM_INS_SMUSDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SRSDA, ARM_INS_SRSDA, + {ARM_SRSDA, ARM_INS_SRSDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SRSDA_UPD, ARM_INS_SRSDA, + {ARM_SRSDA_UPD, + ARM_INS_SRSDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SRSDB, ARM_INS_SRSDB, + {ARM_SRSDB, ARM_INS_SRSDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SRSDB_UPD, ARM_INS_SRSDB, + {ARM_SRSDB_UPD, + ARM_INS_SRSDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SRSIA, ARM_INS_SRSIA, + {ARM_SRSIA, ARM_INS_SRSIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SRSIA_UPD, ARM_INS_SRSIA, + {ARM_SRSIA_UPD, + ARM_INS_SRSIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SRSIB, ARM_INS_SRSIB, + {ARM_SRSIB, ARM_INS_SRSIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SRSIB_UPD, ARM_INS_SRSIB, + {ARM_SRSIB_UPD, + ARM_INS_SRSIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SSAT, ARM_INS_SSAT, + {ARM_SSAT, ARM_INS_SSAT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SSAT16, ARM_INS_SSAT16, + {ARM_SSAT16, + ARM_INS_SSAT16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SSAX, ARM_INS_SSAX, + {ARM_SSAX, ARM_INS_SSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SSUB16, ARM_INS_SSUB16, + {ARM_SSUB16, + ARM_INS_SSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SSUB8, ARM_INS_SSUB8, + {ARM_SSUB8, ARM_INS_SSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STC2L_OFFSET, ARM_INS_STC2L, + {ARM_STC2L_OFFSET, + ARM_INS_STC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC2L_OPTION, ARM_INS_STC2L, + {ARM_STC2L_OPTION, + ARM_INS_STC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC2L_POST, ARM_INS_STC2L, + {ARM_STC2L_POST, + ARM_INS_STC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC2L_PRE, ARM_INS_STC2L, + {ARM_STC2L_PRE, + ARM_INS_STC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC2_OFFSET, ARM_INS_STC2, + {ARM_STC2_OFFSET, + ARM_INS_STC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC2_OPTION, ARM_INS_STC2, + {ARM_STC2_OPTION, + ARM_INS_STC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC2_POST, ARM_INS_STC2, + {ARM_STC2_POST, + ARM_INS_STC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC2_PRE, ARM_INS_STC2, + {ARM_STC2_PRE, + ARM_INS_STC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STCL_OFFSET, ARM_INS_STCL, + {ARM_STCL_OFFSET, + ARM_INS_STCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STCL_OPTION, ARM_INS_STCL, + {ARM_STCL_OPTION, + ARM_INS_STCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STCL_POST, ARM_INS_STCL, + {ARM_STCL_POST, + ARM_INS_STCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STCL_PRE, ARM_INS_STCL, + {ARM_STCL_PRE, + ARM_INS_STCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC_OFFSET, ARM_INS_STC, + {ARM_STC_OFFSET, + ARM_INS_STC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC_OPTION, ARM_INS_STC, + {ARM_STC_OPTION, + ARM_INS_STC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC_POST, ARM_INS_STC, + {ARM_STC_POST, + ARM_INS_STC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STC_PRE, ARM_INS_STC, + {ARM_STC_PRE, + ARM_INS_STC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STL, ARM_INS_STL, + {ARM_STL, ARM_INS_STL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STLB, ARM_INS_STLB, + {ARM_STLB, ARM_INS_STLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STLEX, ARM_INS_STLEX, + {ARM_STLEX, ARM_INS_STLEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STLEXB, ARM_INS_STLEXB, + {ARM_STLEXB, + ARM_INS_STLEXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STLEXD, ARM_INS_STLEXD, + {ARM_STLEXD, + ARM_INS_STLEXD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STLEXH, ARM_INS_STLEXH, + {ARM_STLEXH, + ARM_INS_STLEXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STLH, ARM_INS_STLH, + {ARM_STLH, ARM_INS_STLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STMDA, ARM_INS_STMDA, + {ARM_STMDA, ARM_INS_STMDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STMDA_UPD, ARM_INS_STMDA, + {ARM_STMDA_UPD, + ARM_INS_STMDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STMDB, ARM_INS_STMDB, + {ARM_STMDB, ARM_INS_STMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STMDB_UPD, ARM_INS_STMDB, + {ARM_STMDB_UPD, + ARM_INS_STMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STMIA, ARM_INS_STM, + {ARM_STMIA, ARM_INS_STM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STMIA_UPD, ARM_INS_STM, + {ARM_STMIA_UPD, + ARM_INS_STM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STMIB, ARM_INS_STMIB, + {ARM_STMIB, ARM_INS_STMIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STMIB_UPD, ARM_INS_STMIB, + {ARM_STMIB_UPD, + ARM_INS_STMIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRBT_POST_IMM, ARM_INS_STRBT, + {ARM_STRBT_POST_IMM, + ARM_INS_STRBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRBT_POST_REG, ARM_INS_STRBT, + {ARM_STRBT_POST_REG, + ARM_INS_STRBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRB_POST_IMM, ARM_INS_STRB, + {ARM_STRB_POST_IMM, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRB_POST_REG, ARM_INS_STRB, + {ARM_STRB_POST_REG, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRB_PRE_IMM, ARM_INS_STRB, + {ARM_STRB_PRE_IMM, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRB_PRE_REG, ARM_INS_STRB, + {ARM_STRB_PRE_REG, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRBi12, ARM_INS_STRB, + {ARM_STRBi12, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRBrs, ARM_INS_STRB, + {ARM_STRBrs, ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STRD, ARM_INS_STRD, + {ARM_STRD, ARM_INS_STRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V5TE, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STRD_POST, ARM_INS_STRD, + {ARM_STRD_POST, + ARM_INS_STRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRD_PRE, ARM_INS_STRD, + {ARM_STRD_PRE, + ARM_INS_STRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STREX, ARM_INS_STREX, + {ARM_STREX, ARM_INS_STREX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STREXB, ARM_INS_STREXB, + {ARM_STREXB, + ARM_INS_STREXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STREXD, ARM_INS_STREXD, + {ARM_STREXD, + ARM_INS_STREXD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STREXH, ARM_INS_STREXH, + {ARM_STREXH, + ARM_INS_STREXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRH, ARM_INS_STRH, + {ARM_STRH, ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STRHTi, ARM_INS_STRHT, + {ARM_STRHTi, ARM_INS_STRHT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STRHTr, ARM_INS_STRHT, + {ARM_STRHTr, ARM_INS_STRHT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STRH_POST, ARM_INS_STRH, + {ARM_STRH_POST, + ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRH_PRE, ARM_INS_STRH, + {ARM_STRH_PRE, + ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRT_POST_IMM, ARM_INS_STRT, + {ARM_STRT_POST_IMM, + ARM_INS_STRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRT_POST_REG, ARM_INS_STRT, + {ARM_STRT_POST_REG, + ARM_INS_STRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STR_POST_IMM, ARM_INS_STR, + {ARM_STR_POST_IMM, + ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STR_POST_REG, ARM_INS_STR, + {ARM_STR_POST_REG, + ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STR_PRE_IMM, ARM_INS_STR, + {ARM_STR_PRE_IMM, + ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STR_PRE_REG, ARM_INS_STR, + {ARM_STR_PRE_REG, + ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_STRi12, ARM_INS_STR, + {ARM_STRi12, ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_STRrs, ARM_INS_STR, + {ARM_STRrs, ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SUBri, ARM_INS_SUB, + {ARM_SUBri, ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SUBrr, ARM_INS_SUB, + {ARM_SUBrr, ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SUBrsi, ARM_INS_SUB, + {ARM_SUBrsi, ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SUBrsr, ARM_INS_SUB, + {ARM_SUBrsr, ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SVC, ARM_INS_SVC, + {ARM_SVC, + ARM_INS_SVC, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_INT, 0 }, 0, 0 + {ARM_REG_PC, 0}, + {ARM_REG_LR, 0}, + {ARM_GRP_ARM, ARM_GRP_INT, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SWP, ARM_INS_SWP, + {ARM_SWP, ARM_INS_SWP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PREV8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SWPB, ARM_INS_SWPB, + {ARM_SWPB, ARM_INS_SWPB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PREV8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SXTAB, ARM_INS_SXTAB, + {ARM_SXTAB, ARM_INS_SXTAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SXTAB16, ARM_INS_SXTAB16, + {ARM_SXTAB16, + ARM_INS_SXTAB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SXTAH, ARM_INS_SXTAH, + {ARM_SXTAH, ARM_INS_SXTAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SXTB, ARM_INS_SXTB, + {ARM_SXTB, ARM_INS_SXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_SXTB16, ARM_INS_SXTB16, + {ARM_SXTB16, + ARM_INS_SXTB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_SXTH, ARM_INS_SXTH, + {ARM_SXTH, ARM_INS_SXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_TEQri, ARM_INS_TEQ, + {ARM_TEQri, ARM_INS_TEQ, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_TEQrr, ARM_INS_TEQ, + {ARM_TEQrr, ARM_INS_TEQ, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_TEQrsi, ARM_INS_TEQ, + {ARM_TEQrsi, ARM_INS_TEQ, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_TEQrsr, ARM_INS_TEQ, + {ARM_TEQrsr, ARM_INS_TEQ, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_TRAP, ARM_INS_TRAP, + {ARM_TRAP, ARM_INS_TRAP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_TRAPNaCl, ARM_INS_TRAP, + {ARM_TRAPNaCl, + ARM_INS_TRAP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_TSB, ARM_INS_TSB, + {ARM_TSB, ARM_INS_TSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_TSTri, ARM_INS_TST, + {ARM_TSTri, ARM_INS_TST, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_TSTrr, ARM_INS_TST, + {ARM_TSTrr, ARM_INS_TST, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_TSTrsi, ARM_INS_TST, + {ARM_TSTrsi, ARM_INS_TST, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_TSTrsr, ARM_INS_TST, + {ARM_TSTrsr, ARM_INS_TST, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UADD16, ARM_INS_UADD16, + {ARM_UADD16, + ARM_INS_UADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UADD8, ARM_INS_UADD8, + {ARM_UADD8, ARM_INS_UADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UASX, ARM_INS_UASX, + {ARM_UASX, ARM_INS_UASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UBFX, ARM_INS_UBFX, + {ARM_UBFX, ARM_INS_UBFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6T2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UDF, ARM_INS_UDF, + {ARM_UDF, ARM_INS_UDF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UDIV, ARM_INS_UDIV, + {ARM_UDIV, ARM_INS_UDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UHADD16, ARM_INS_UHADD16, + {ARM_UHADD16, + ARM_INS_UHADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UHADD8, ARM_INS_UHADD8, + {ARM_UHADD8, + ARM_INS_UHADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UHASX, ARM_INS_UHASX, + {ARM_UHASX, ARM_INS_UHASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UHSAX, ARM_INS_UHSAX, + {ARM_UHSAX, ARM_INS_UHSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UHSUB16, ARM_INS_UHSUB16, + {ARM_UHSUB16, + ARM_INS_UHSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UHSUB8, ARM_INS_UHSUB8, + {ARM_UHSUB8, + ARM_INS_UHSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UMAAL, ARM_INS_UMAAL, + {ARM_UMAAL, ARM_INS_UMAAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UMLAL, ARM_INS_UMLAL, + {ARM_UMLAL, ARM_INS_UMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UMULL, ARM_INS_UMULL, + {ARM_UMULL, ARM_INS_UMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UQADD16, ARM_INS_UQADD16, + {ARM_UQADD16, + ARM_INS_UQADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UQADD8, ARM_INS_UQADD8, + {ARM_UQADD8, + ARM_INS_UQADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UQASX, ARM_INS_UQASX, + {ARM_UQASX, ARM_INS_UQASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UQSAX, ARM_INS_UQSAX, + {ARM_UQSAX, ARM_INS_UQSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UQSUB16, ARM_INS_UQSUB16, + {ARM_UQSUB16, + ARM_INS_UQSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UQSUB8, ARM_INS_UQSUB8, + {ARM_UQSUB8, + ARM_INS_UQSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_USAD8, ARM_INS_USAD8, + {ARM_USAD8, ARM_INS_USAD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_USADA8, ARM_INS_USADA8, + {ARM_USADA8, + ARM_INS_USADA8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_USAT, ARM_INS_USAT, + {ARM_USAT, ARM_INS_USAT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_USAT16, ARM_INS_USAT16, + {ARM_USAT16, + ARM_INS_USAT16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_USAX, ARM_INS_USAX, + {ARM_USAX, ARM_INS_USAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_USUB16, ARM_INS_USUB16, + {ARM_USUB16, + ARM_INS_USUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_USUB8, ARM_INS_USUB8, + {ARM_USUB8, ARM_INS_USUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UXTAB, ARM_INS_UXTAB, + {ARM_UXTAB, ARM_INS_UXTAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UXTAB16, ARM_INS_UXTAB16, + {ARM_UXTAB16, + ARM_INS_UXTAB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UXTAH, ARM_INS_UXTAH, + {ARM_UXTAH, ARM_INS_UXTAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UXTB, ARM_INS_UXTB, + {ARM_UXTB, ARM_INS_UXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_UXTB16, ARM_INS_UXTB16, + {ARM_UXTB16, + ARM_INS_UXTB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_UXTH, ARM_INS_UXTH, + {ARM_UXTH, ARM_INS_UXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_ARM, ARM_GRP_V6, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VABALsv2i64, ARM_INS_VABAL, + {ARM_VABALsv2i64, + ARM_INS_VABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABALsv4i32, ARM_INS_VABAL, + {ARM_VABALsv4i32, + ARM_INS_VABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABALsv8i16, ARM_INS_VABAL, + {ARM_VABALsv8i16, + ARM_INS_VABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABALuv2i64, ARM_INS_VABAL, + {ARM_VABALuv2i64, + ARM_INS_VABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABALuv4i32, ARM_INS_VABAL, + {ARM_VABALuv4i32, + ARM_INS_VABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABALuv8i16, ARM_INS_VABAL, + {ARM_VABALuv8i16, + ARM_INS_VABAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAsv16i8, ARM_INS_VABA, + {ARM_VABAsv16i8, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAsv2i32, ARM_INS_VABA, + {ARM_VABAsv2i32, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAsv4i16, ARM_INS_VABA, + {ARM_VABAsv4i16, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAsv4i32, ARM_INS_VABA, + {ARM_VABAsv4i32, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAsv8i16, ARM_INS_VABA, + {ARM_VABAsv8i16, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAsv8i8, ARM_INS_VABA, + {ARM_VABAsv8i8, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAuv16i8, ARM_INS_VABA, + {ARM_VABAuv16i8, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAuv2i32, ARM_INS_VABA, + {ARM_VABAuv2i32, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAuv4i16, ARM_INS_VABA, + {ARM_VABAuv4i16, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAuv4i32, ARM_INS_VABA, + {ARM_VABAuv4i32, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAuv8i16, ARM_INS_VABA, + {ARM_VABAuv8i16, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABAuv8i8, ARM_INS_VABA, + {ARM_VABAuv8i8, + ARM_INS_VABA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDLsv2i64, ARM_INS_VABDL, + {ARM_VABDLsv2i64, + ARM_INS_VABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDLsv4i32, ARM_INS_VABDL, + {ARM_VABDLsv4i32, + ARM_INS_VABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDLsv8i16, ARM_INS_VABDL, + {ARM_VABDLsv8i16, + ARM_INS_VABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDLuv2i64, ARM_INS_VABDL, + {ARM_VABDLuv2i64, + ARM_INS_VABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDLuv4i32, ARM_INS_VABDL, + {ARM_VABDLuv4i32, + ARM_INS_VABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDLuv8i16, ARM_INS_VABDL, + {ARM_VABDLuv8i16, + ARM_INS_VABDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDfd, ARM_INS_VABD, + {ARM_VABDfd, ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VABDfq, ARM_INS_VABD, + {ARM_VABDfq, ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VABDhd, ARM_INS_VABD, + {ARM_VABDhd, ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VABDhq, ARM_INS_VABD, + {ARM_VABDhq, ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VABDsv16i8, ARM_INS_VABD, + {ARM_VABDsv16i8, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDsv2i32, ARM_INS_VABD, + {ARM_VABDsv2i32, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDsv4i16, ARM_INS_VABD, + {ARM_VABDsv4i16, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDsv4i32, ARM_INS_VABD, + {ARM_VABDsv4i32, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDsv8i16, ARM_INS_VABD, + {ARM_VABDsv8i16, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDsv8i8, ARM_INS_VABD, + {ARM_VABDsv8i8, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDuv16i8, ARM_INS_VABD, + {ARM_VABDuv16i8, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDuv2i32, ARM_INS_VABD, + {ARM_VABDuv2i32, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDuv4i16, ARM_INS_VABD, + {ARM_VABDuv4i16, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDuv4i32, ARM_INS_VABD, + {ARM_VABDuv4i32, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDuv8i16, ARM_INS_VABD, + {ARM_VABDuv8i16, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABDuv8i8, ARM_INS_VABD, + {ARM_VABDuv8i8, + ARM_INS_VABD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABSD, ARM_INS_VABS, + {ARM_VABSD, ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VABSH, ARM_INS_VABS, + {ARM_VABSH, ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VABSS, ARM_INS_VABS, + {ARM_VABSS, ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VABSfd, ARM_INS_VABS, + {ARM_VABSfd, ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VABSfq, ARM_INS_VABS, + {ARM_VABSfq, ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VABShd, ARM_INS_VABS, + {ARM_VABShd, ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VABShq, ARM_INS_VABS, + {ARM_VABShq, ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VABSv16i8, ARM_INS_VABS, + {ARM_VABSv16i8, + ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABSv2i32, ARM_INS_VABS, + {ARM_VABSv2i32, + ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABSv4i16, ARM_INS_VABS, + {ARM_VABSv4i16, + ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABSv4i32, ARM_INS_VABS, + {ARM_VABSv4i32, + ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABSv8i16, ARM_INS_VABS, + {ARM_VABSv8i16, + ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VABSv8i8, ARM_INS_VABS, + {ARM_VABSv8i8, + ARM_INS_VABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VACGEfd, ARM_INS_VACGE, + {ARM_VACGEfd, + ARM_INS_VACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VACGEfq, ARM_INS_VACGE, + {ARM_VACGEfq, + ARM_INS_VACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VACGEhd, ARM_INS_VACGE, + {ARM_VACGEhd, + ARM_INS_VACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VACGEhq, ARM_INS_VACGE, + {ARM_VACGEhq, + ARM_INS_VACGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VACGTfd, ARM_INS_VACGT, + {ARM_VACGTfd, + ARM_INS_VACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VACGTfq, ARM_INS_VACGT, + {ARM_VACGTfq, + ARM_INS_VACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VACGThd, ARM_INS_VACGT, + {ARM_VACGThd, + ARM_INS_VACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VACGThq, ARM_INS_VACGT, + {ARM_VACGThq, + ARM_INS_VACGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDD, ARM_INS_VADD, + {ARM_VADDD, ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VADDH, ARM_INS_VADD, + {ARM_VADDH, ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VADDHNv2i32, ARM_INS_VADDHN, + {ARM_VADDHNv2i32, + ARM_INS_VADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDHNv4i16, ARM_INS_VADDHN, + {ARM_VADDHNv4i16, + ARM_INS_VADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDHNv8i8, ARM_INS_VADDHN, + {ARM_VADDHNv8i8, + ARM_INS_VADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDLsv2i64, ARM_INS_VADDL, + {ARM_VADDLsv2i64, + ARM_INS_VADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDLsv4i32, ARM_INS_VADDL, + {ARM_VADDLsv4i32, + ARM_INS_VADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDLsv8i16, ARM_INS_VADDL, + {ARM_VADDLsv8i16, + ARM_INS_VADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDLuv2i64, ARM_INS_VADDL, + {ARM_VADDLuv2i64, + ARM_INS_VADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDLuv4i32, ARM_INS_VADDL, + {ARM_VADDLuv4i32, + ARM_INS_VADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDLuv8i16, ARM_INS_VADDL, + {ARM_VADDLuv8i16, + ARM_INS_VADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDS, ARM_INS_VADD, + {ARM_VADDS, ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VADDWsv2i64, ARM_INS_VADDW, + {ARM_VADDWsv2i64, + ARM_INS_VADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDWsv4i32, ARM_INS_VADDW, + {ARM_VADDWsv4i32, + ARM_INS_VADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDWsv8i16, ARM_INS_VADDW, + {ARM_VADDWsv8i16, + ARM_INS_VADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDWuv2i64, ARM_INS_VADDW, + {ARM_VADDWuv2i64, + ARM_INS_VADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDWuv4i32, ARM_INS_VADDW, + {ARM_VADDWuv4i32, + ARM_INS_VADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDWuv8i16, ARM_INS_VADDW, + {ARM_VADDWuv8i16, + ARM_INS_VADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDfd, ARM_INS_VADD, + {ARM_VADDfd, ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VADDfq, ARM_INS_VADD, + {ARM_VADDfq, ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VADDhd, ARM_INS_VADD, + {ARM_VADDhd, ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VADDhq, ARM_INS_VADD, + {ARM_VADDhq, ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VADDv16i8, ARM_INS_VADD, + {ARM_VADDv16i8, + ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDv1i64, ARM_INS_VADD, + {ARM_VADDv1i64, + ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDv2i32, ARM_INS_VADD, + {ARM_VADDv2i32, + ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDv2i64, ARM_INS_VADD, + {ARM_VADDv2i64, + ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDv4i16, ARM_INS_VADD, + {ARM_VADDv4i16, + ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDv4i32, ARM_INS_VADD, + {ARM_VADDv4i32, + ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDv8i16, ARM_INS_VADD, + {ARM_VADDv8i16, + ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VADDv8i8, ARM_INS_VADD, + {ARM_VADDv8i8, + ARM_INS_VADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VANDd, ARM_INS_VAND, + {ARM_VANDd, ARM_INS_VAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VANDq, ARM_INS_VAND, + {ARM_VANDq, ARM_INS_VAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VBICd, ARM_INS_VBIC, + {ARM_VBICd, ARM_INS_VBIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VBICiv2i32, ARM_INS_VBIC, + {ARM_VBICiv2i32, + ARM_INS_VBIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VBICiv4i16, ARM_INS_VBIC, + {ARM_VBICiv4i16, + ARM_INS_VBIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VBICiv4i32, ARM_INS_VBIC, + {ARM_VBICiv4i32, + ARM_INS_VBIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VBICiv8i16, ARM_INS_VBIC, + {ARM_VBICiv8i16, + ARM_INS_VBIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VBICq, ARM_INS_VBIC, + {ARM_VBICq, ARM_INS_VBIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VBIFd, ARM_INS_VBIF, + {ARM_VBIFd, ARM_INS_VBIF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VBIFq, ARM_INS_VBIF, + {ARM_VBIFq, ARM_INS_VBIF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VBITd, ARM_INS_VBIT, + {ARM_VBITd, ARM_INS_VBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VBITq, ARM_INS_VBIT, + {ARM_VBITq, ARM_INS_VBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VBSLd, ARM_INS_VBSL, + {ARM_VBSLd, ARM_INS_VBSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VBSLq, ARM_INS_VBSL, + {ARM_VBSLq, ARM_INS_VBSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCADDv2f32, ARM_INS_VCADD, + {ARM_VCADDv2f32, + ARM_INS_VCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCADDv4f16, ARM_INS_VCADD, + {ARM_VCADDv4f16, + ARM_INS_VCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCADDv4f32, ARM_INS_VCADD, + {ARM_VCADDv4f32, + ARM_INS_VCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCADDv8f16, ARM_INS_VCADD, + {ARM_VCADDv8f16, + ARM_INS_VCADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQfd, ARM_INS_VCEQ, + {ARM_VCEQfd, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCEQfq, ARM_INS_VCEQ, + {ARM_VCEQfq, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCEQhd, ARM_INS_VCEQ, + {ARM_VCEQhd, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VCEQhq, ARM_INS_VCEQ, + {ARM_VCEQhq, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VCEQv16i8, ARM_INS_VCEQ, + {ARM_VCEQv16i8, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQv2i32, ARM_INS_VCEQ, + {ARM_VCEQv2i32, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQv4i16, ARM_INS_VCEQ, + {ARM_VCEQv4i16, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQv4i32, ARM_INS_VCEQ, + {ARM_VCEQv4i32, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQv8i16, ARM_INS_VCEQ, + {ARM_VCEQv8i16, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQv8i8, ARM_INS_VCEQ, + {ARM_VCEQv8i8, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv16i8, ARM_INS_VCEQ, + {ARM_VCEQzv16i8, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv2f32, ARM_INS_VCEQ, + {ARM_VCEQzv2f32, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv2i32, ARM_INS_VCEQ, + {ARM_VCEQzv2i32, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv4f16, ARM_INS_VCEQ, + {ARM_VCEQzv4f16, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv4f32, ARM_INS_VCEQ, + {ARM_VCEQzv4f32, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv4i16, ARM_INS_VCEQ, + {ARM_VCEQzv4i16, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv4i32, ARM_INS_VCEQ, + {ARM_VCEQzv4i32, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv8f16, ARM_INS_VCEQ, + {ARM_VCEQzv8f16, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv8i16, ARM_INS_VCEQ, + {ARM_VCEQzv8i16, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCEQzv8i8, ARM_INS_VCEQ, + {ARM_VCEQzv8i8, + ARM_INS_VCEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEfd, ARM_INS_VCGE, + {ARM_VCGEfd, ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCGEfq, ARM_INS_VCGE, + {ARM_VCGEfq, ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCGEhd, ARM_INS_VCGE, + {ARM_VCGEhd, ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VCGEhq, ARM_INS_VCGE, + {ARM_VCGEhq, ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VCGEsv16i8, ARM_INS_VCGE, + {ARM_VCGEsv16i8, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEsv2i32, ARM_INS_VCGE, + {ARM_VCGEsv2i32, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEsv4i16, ARM_INS_VCGE, + {ARM_VCGEsv4i16, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEsv4i32, ARM_INS_VCGE, + {ARM_VCGEsv4i32, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEsv8i16, ARM_INS_VCGE, + {ARM_VCGEsv8i16, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEsv8i8, ARM_INS_VCGE, + {ARM_VCGEsv8i8, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEuv16i8, ARM_INS_VCGE, + {ARM_VCGEuv16i8, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEuv2i32, ARM_INS_VCGE, + {ARM_VCGEuv2i32, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEuv4i16, ARM_INS_VCGE, + {ARM_VCGEuv4i16, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEuv4i32, ARM_INS_VCGE, + {ARM_VCGEuv4i32, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEuv8i16, ARM_INS_VCGE, + {ARM_VCGEuv8i16, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEuv8i8, ARM_INS_VCGE, + {ARM_VCGEuv8i8, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv16i8, ARM_INS_VCGE, + {ARM_VCGEzv16i8, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv2f32, ARM_INS_VCGE, + {ARM_VCGEzv2f32, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv2i32, ARM_INS_VCGE, + {ARM_VCGEzv2i32, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv4f16, ARM_INS_VCGE, + {ARM_VCGEzv4f16, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv4f32, ARM_INS_VCGE, + {ARM_VCGEzv4f32, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv4i16, ARM_INS_VCGE, + {ARM_VCGEzv4i16, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv4i32, ARM_INS_VCGE, + {ARM_VCGEzv4i32, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv8f16, ARM_INS_VCGE, + {ARM_VCGEzv8f16, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv8i16, ARM_INS_VCGE, + {ARM_VCGEzv8i16, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGEzv8i8, ARM_INS_VCGE, + {ARM_VCGEzv8i8, + ARM_INS_VCGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTfd, ARM_INS_VCGT, + {ARM_VCGTfd, ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCGTfq, ARM_INS_VCGT, + {ARM_VCGTfq, ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCGThd, ARM_INS_VCGT, + {ARM_VCGThd, ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VCGThq, ARM_INS_VCGT, + {ARM_VCGThq, ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VCGTsv16i8, ARM_INS_VCGT, + {ARM_VCGTsv16i8, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTsv2i32, ARM_INS_VCGT, + {ARM_VCGTsv2i32, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTsv4i16, ARM_INS_VCGT, + {ARM_VCGTsv4i16, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTsv4i32, ARM_INS_VCGT, + {ARM_VCGTsv4i32, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTsv8i16, ARM_INS_VCGT, + {ARM_VCGTsv8i16, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTsv8i8, ARM_INS_VCGT, + {ARM_VCGTsv8i8, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTuv16i8, ARM_INS_VCGT, + {ARM_VCGTuv16i8, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTuv2i32, ARM_INS_VCGT, + {ARM_VCGTuv2i32, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTuv4i16, ARM_INS_VCGT, + {ARM_VCGTuv4i16, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTuv4i32, ARM_INS_VCGT, + {ARM_VCGTuv4i32, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTuv8i16, ARM_INS_VCGT, + {ARM_VCGTuv8i16, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTuv8i8, ARM_INS_VCGT, + {ARM_VCGTuv8i8, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv16i8, ARM_INS_VCGT, + {ARM_VCGTzv16i8, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv2f32, ARM_INS_VCGT, + {ARM_VCGTzv2f32, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv2i32, ARM_INS_VCGT, + {ARM_VCGTzv2i32, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv4f16, ARM_INS_VCGT, + {ARM_VCGTzv4f16, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv4f32, ARM_INS_VCGT, + {ARM_VCGTzv4f32, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv4i16, ARM_INS_VCGT, + {ARM_VCGTzv4i16, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv4i32, ARM_INS_VCGT, + {ARM_VCGTzv4i32, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv8f16, ARM_INS_VCGT, + {ARM_VCGTzv8f16, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv8i16, ARM_INS_VCGT, + {ARM_VCGTzv8i16, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCGTzv8i8, ARM_INS_VCGT, + {ARM_VCGTzv8i8, + ARM_INS_VCGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv16i8, ARM_INS_VCLE, + {ARM_VCLEzv16i8, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv2f32, ARM_INS_VCLE, + {ARM_VCLEzv2f32, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv2i32, ARM_INS_VCLE, + {ARM_VCLEzv2i32, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv4f16, ARM_INS_VCLE, + {ARM_VCLEzv4f16, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv4f32, ARM_INS_VCLE, + {ARM_VCLEzv4f32, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv4i16, ARM_INS_VCLE, + {ARM_VCLEzv4i16, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv4i32, ARM_INS_VCLE, + {ARM_VCLEzv4i32, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv8f16, ARM_INS_VCLE, + {ARM_VCLEzv8f16, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv8i16, ARM_INS_VCLE, + {ARM_VCLEzv8i16, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLEzv8i8, ARM_INS_VCLE, + {ARM_VCLEzv8i8, + ARM_INS_VCLE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLSv16i8, ARM_INS_VCLS, + {ARM_VCLSv16i8, + ARM_INS_VCLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLSv2i32, ARM_INS_VCLS, + {ARM_VCLSv2i32, + ARM_INS_VCLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLSv4i16, ARM_INS_VCLS, + {ARM_VCLSv4i16, + ARM_INS_VCLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLSv4i32, ARM_INS_VCLS, + {ARM_VCLSv4i32, + ARM_INS_VCLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLSv8i16, ARM_INS_VCLS, + {ARM_VCLSv8i16, + ARM_INS_VCLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLSv8i8, ARM_INS_VCLS, + {ARM_VCLSv8i8, + ARM_INS_VCLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv16i8, ARM_INS_VCLT, + {ARM_VCLTzv16i8, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv2f32, ARM_INS_VCLT, + {ARM_VCLTzv2f32, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv2i32, ARM_INS_VCLT, + {ARM_VCLTzv2i32, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv4f16, ARM_INS_VCLT, + {ARM_VCLTzv4f16, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv4f32, ARM_INS_VCLT, + {ARM_VCLTzv4f32, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv4i16, ARM_INS_VCLT, + {ARM_VCLTzv4i16, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv4i32, ARM_INS_VCLT, + {ARM_VCLTzv4i32, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv8f16, ARM_INS_VCLT, + {ARM_VCLTzv8f16, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv8i16, ARM_INS_VCLT, + {ARM_VCLTzv8i16, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLTzv8i8, ARM_INS_VCLT, + {ARM_VCLTzv8i8, + ARM_INS_VCLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLZv16i8, ARM_INS_VCLZ, + {ARM_VCLZv16i8, + ARM_INS_VCLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLZv2i32, ARM_INS_VCLZ, + {ARM_VCLZv2i32, + ARM_INS_VCLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLZv4i16, ARM_INS_VCLZ, + {ARM_VCLZv4i16, + ARM_INS_VCLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLZv4i32, ARM_INS_VCLZ, + {ARM_VCLZv4i32, + ARM_INS_VCLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLZv8i16, ARM_INS_VCLZ, + {ARM_VCLZv8i16, + ARM_INS_VCLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCLZv8i8, ARM_INS_VCLZ, + {ARM_VCLZv8i8, + ARM_INS_VCLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMLAv2f32, ARM_INS_VCMLA, + {ARM_VCMLAv2f32, + ARM_INS_VCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMLAv2f32_indexed, ARM_INS_VCMLA, + {ARM_VCMLAv2f32_indexed, + ARM_INS_VCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMLAv4f16, ARM_INS_VCMLA, + {ARM_VCMLAv4f16, + ARM_INS_VCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMLAv4f16_indexed, ARM_INS_VCMLA, + {ARM_VCMLAv4f16_indexed, + ARM_INS_VCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMLAv4f32, ARM_INS_VCMLA, + {ARM_VCMLAv4f32, + ARM_INS_VCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMLAv4f32_indexed, ARM_INS_VCMLA, + {ARM_VCMLAv4f32_indexed, + ARM_INS_VCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMLAv8f16, ARM_INS_VCMLA, + {ARM_VCMLAv8f16, + ARM_INS_VCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMLAv8f16_indexed, ARM_INS_VCMLA, + {ARM_VCMLAv8f16_indexed, + ARM_INS_VCMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMPD, ARM_INS_VCMP, + {ARM_VCMPD, + ARM_INS_VCMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR_NZCV, 0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMPED, ARM_INS_VCMPE, + {ARM_VCMPED, ARM_INS_VCMPE, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {ARM_REG_FPSCR_NZCV, 0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCMPEH, ARM_INS_VCMPE, + {ARM_VCMPEH, ARM_INS_VCMPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VCMPES, ARM_INS_VCMPE, + {ARM_VCMPES, ARM_INS_VCMPE, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {ARM_REG_FPSCR_NZCV, 0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCMPEZD, ARM_INS_VCMPE, + {ARM_VCMPEZD, + ARM_INS_VCMPE, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR_NZCV, 0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMPEZH, ARM_INS_VCMPE, + {ARM_VCMPEZH, + ARM_INS_VCMPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMPEZS, ARM_INS_VCMPE, + {ARM_VCMPEZS, + ARM_INS_VCMPE, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR_NZCV, 0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMPH, ARM_INS_VCMP, + {ARM_VCMPH, ARM_INS_VCMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VCMPS, ARM_INS_VCMP, + {ARM_VCMPS, + ARM_INS_VCMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR_NZCV, 0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMPZD, ARM_INS_VCMP, + {ARM_VCMPZD, + ARM_INS_VCMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR_NZCV, 0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCMPZH, ARM_INS_VCMP, + {ARM_VCMPZH, ARM_INS_VCMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VCMPZS, ARM_INS_VCMP, + {ARM_VCMPZS, + ARM_INS_VCMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR_NZCV, 0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCNTd, ARM_INS_VCNT, + {ARM_VCNTd, ARM_INS_VCNT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCNTq, ARM_INS_VCNT, + {ARM_VCNTq, ARM_INS_VCNT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCVTANSDf, ARM_INS_VCVTA, + {ARM_VCVTANSDf, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTANSDh, ARM_INS_VCVTA, + {ARM_VCVTANSDh, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTANSQf, ARM_INS_VCVTA, + {ARM_VCVTANSQf, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTANSQh, ARM_INS_VCVTA, + {ARM_VCVTANSQh, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTANUDf, ARM_INS_VCVTA, + {ARM_VCVTANUDf, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTANUDh, ARM_INS_VCVTA, + {ARM_VCVTANUDh, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTANUQf, ARM_INS_VCVTA, + {ARM_VCVTANUQf, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTANUQh, ARM_INS_VCVTA, + {ARM_VCVTANUQh, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTASD, ARM_INS_VCVTA, + {ARM_VCVTASD, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTASH, ARM_INS_VCVTA, + {ARM_VCVTASH, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTASS, ARM_INS_VCVTA, + {ARM_VCVTASS, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTAUD, ARM_INS_VCVTA, + {ARM_VCVTAUD, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTAUH, ARM_INS_VCVTA, + {ARM_VCVTAUH, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTAUS, ARM_INS_VCVTA, + {ARM_VCVTAUS, + ARM_INS_VCVTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTBDH, ARM_INS_VCVTB, + {ARM_VCVTBDH, + ARM_INS_VCVTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTBHD, ARM_INS_VCVTB, + {ARM_VCVTBHD, + ARM_INS_VCVTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTBHS, ARM_INS_VCVTB, + {ARM_VCVTBHS, + ARM_INS_VCVTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTBSH, ARM_INS_VCVTB, + {ARM_VCVTBSH, + ARM_INS_VCVTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTDS, ARM_INS_VCVT, + {ARM_VCVTDS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCVTMNSDf, ARM_INS_VCVTM, + {ARM_VCVTMNSDf, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMNSDh, ARM_INS_VCVTM, + {ARM_VCVTMNSDh, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMNSQf, ARM_INS_VCVTM, + {ARM_VCVTMNSQf, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMNSQh, ARM_INS_VCVTM, + {ARM_VCVTMNSQh, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMNUDf, ARM_INS_VCVTM, + {ARM_VCVTMNUDf, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMNUDh, ARM_INS_VCVTM, + {ARM_VCVTMNUDh, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMNUQf, ARM_INS_VCVTM, + {ARM_VCVTMNUQf, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMNUQh, ARM_INS_VCVTM, + {ARM_VCVTMNUQh, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMSD, ARM_INS_VCVTM, + {ARM_VCVTMSD, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMSH, ARM_INS_VCVTM, + {ARM_VCVTMSH, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMSS, ARM_INS_VCVTM, + {ARM_VCVTMSS, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMUD, ARM_INS_VCVTM, + {ARM_VCVTMUD, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMUH, ARM_INS_VCVTM, + {ARM_VCVTMUH, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTMUS, ARM_INS_VCVTM, + {ARM_VCVTMUS, + ARM_INS_VCVTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNNSDf, ARM_INS_VCVTN, + {ARM_VCVTNNSDf, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNNSDh, ARM_INS_VCVTN, + {ARM_VCVTNNSDh, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNNSQf, ARM_INS_VCVTN, + {ARM_VCVTNNSQf, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNNSQh, ARM_INS_VCVTN, + {ARM_VCVTNNSQh, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNNUDf, ARM_INS_VCVTN, + {ARM_VCVTNNUDf, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNNUDh, ARM_INS_VCVTN, + {ARM_VCVTNNUDh, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNNUQf, ARM_INS_VCVTN, + {ARM_VCVTNNUQf, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNNUQh, ARM_INS_VCVTN, + {ARM_VCVTNNUQh, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNSD, ARM_INS_VCVTN, + {ARM_VCVTNSD, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNSH, ARM_INS_VCVTN, + {ARM_VCVTNSH, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNSS, ARM_INS_VCVTN, + {ARM_VCVTNSS, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNUD, ARM_INS_VCVTN, + {ARM_VCVTNUD, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNUH, ARM_INS_VCVTN, + {ARM_VCVTNUH, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTNUS, ARM_INS_VCVTN, + {ARM_VCVTNUS, + ARM_INS_VCVTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPNSDf, ARM_INS_VCVTP, + {ARM_VCVTPNSDf, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPNSDh, ARM_INS_VCVTP, + {ARM_VCVTPNSDh, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPNSQf, ARM_INS_VCVTP, + {ARM_VCVTPNSQf, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPNSQh, ARM_INS_VCVTP, + {ARM_VCVTPNSQh, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPNUDf, ARM_INS_VCVTP, + {ARM_VCVTPNUDf, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPNUDh, ARM_INS_VCVTP, + {ARM_VCVTPNUDh, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPNUQf, ARM_INS_VCVTP, + {ARM_VCVTPNUQf, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPNUQh, ARM_INS_VCVTP, + {ARM_VCVTPNUQh, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPSD, ARM_INS_VCVTP, + {ARM_VCVTPSD, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPSH, ARM_INS_VCVTP, + {ARM_VCVTPSH, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPSS, ARM_INS_VCVTP, + {ARM_VCVTPSS, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPUD, ARM_INS_VCVTP, + {ARM_VCVTPUD, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPUH, ARM_INS_VCVTP, + {ARM_VCVTPUH, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTPUS, ARM_INS_VCVTP, + {ARM_VCVTPUS, + ARM_INS_VCVTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTSD, ARM_INS_VCVT, + {ARM_VCVTSD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VCVTTDH, ARM_INS_VCVTT, + {ARM_VCVTTDH, + ARM_INS_VCVTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTTHD, ARM_INS_VCVTT, + {ARM_VCVTTHD, + ARM_INS_VCVTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTTHS, ARM_INS_VCVTT, + {ARM_VCVTTHS, + ARM_INS_VCVTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTTSH, ARM_INS_VCVTT, + {ARM_VCVTTSH, + ARM_INS_VCVTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTf2h, ARM_INS_VCVT, + {ARM_VCVTf2h, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTf2sd, ARM_INS_VCVT, + {ARM_VCVTf2sd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTf2sq, ARM_INS_VCVT, + {ARM_VCVTf2sq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTf2ud, ARM_INS_VCVT, + {ARM_VCVTf2ud, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTf2uq, ARM_INS_VCVT, + {ARM_VCVTf2uq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTf2xsd, ARM_INS_VCVT, + {ARM_VCVTf2xsd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTf2xsq, ARM_INS_VCVT, + {ARM_VCVTf2xsq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTf2xud, ARM_INS_VCVT, + {ARM_VCVTf2xud, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTf2xuq, ARM_INS_VCVT, + {ARM_VCVTf2xuq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTh2f, ARM_INS_VCVT, + {ARM_VCVTh2f, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTh2sd, ARM_INS_VCVT, + {ARM_VCVTh2sd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTh2sq, ARM_INS_VCVT, + {ARM_VCVTh2sq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTh2ud, ARM_INS_VCVT, + {ARM_VCVTh2ud, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTh2uq, ARM_INS_VCVT, + {ARM_VCVTh2uq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTh2xsd, ARM_INS_VCVT, + {ARM_VCVTh2xsd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTh2xsq, ARM_INS_VCVT, + {ARM_VCVTh2xsq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTh2xud, ARM_INS_VCVT, + {ARM_VCVTh2xud, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTh2xuq, ARM_INS_VCVT, + {ARM_VCVTh2xuq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTs2fd, ARM_INS_VCVT, + {ARM_VCVTs2fd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTs2fq, ARM_INS_VCVT, + {ARM_VCVTs2fq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTs2hd, ARM_INS_VCVT, + {ARM_VCVTs2hd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTs2hq, ARM_INS_VCVT, + {ARM_VCVTs2hq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTu2fd, ARM_INS_VCVT, + {ARM_VCVTu2fd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTu2fq, ARM_INS_VCVT, + {ARM_VCVTu2fq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTu2hd, ARM_INS_VCVT, + {ARM_VCVTu2hd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTu2hq, ARM_INS_VCVT, + {ARM_VCVTu2hq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTxs2fd, ARM_INS_VCVT, + {ARM_VCVTxs2fd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTxs2fq, ARM_INS_VCVT, + {ARM_VCVTxs2fq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTxs2hd, ARM_INS_VCVT, + {ARM_VCVTxs2hd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTxs2hq, ARM_INS_VCVT, + {ARM_VCVTxs2hq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTxu2fd, ARM_INS_VCVT, + {ARM_VCVTxu2fd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTxu2fq, ARM_INS_VCVT, + {ARM_VCVTxu2fq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTxu2hd, ARM_INS_VCVT, + {ARM_VCVTxu2hd, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VCVTxu2hq, ARM_INS_VCVT, + {ARM_VCVTxu2hq, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDIVD, ARM_INS_VDIV, + {ARM_VDIVD, ARM_INS_VDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VDIVH, ARM_INS_VDIV, + {ARM_VDIVH, ARM_INS_VDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VDIVS, ARM_INS_VDIV, + {ARM_VDIVS, ARM_INS_VDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VDUP16d, ARM_INS_VDUP, + {ARM_VDUP16d, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDUP16q, ARM_INS_VDUP, + {ARM_VDUP16q, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDUP32d, ARM_INS_VDUP, + {ARM_VDUP32d, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDUP32q, ARM_INS_VDUP, + {ARM_VDUP32q, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDUP8d, ARM_INS_VDUP, + {ARM_VDUP8d, ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VDUP8q, ARM_INS_VDUP, + {ARM_VDUP8q, ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VDUPLN16d, ARM_INS_VDUP, + {ARM_VDUPLN16d, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDUPLN16q, ARM_INS_VDUP, + {ARM_VDUPLN16q, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDUPLN32d, ARM_INS_VDUP, + {ARM_VDUPLN32d, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDUPLN32q, ARM_INS_VDUP, + {ARM_VDUPLN32q, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDUPLN8d, ARM_INS_VDUP, + {ARM_VDUPLN8d, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VDUPLN8q, ARM_INS_VDUP, + {ARM_VDUPLN8q, + ARM_INS_VDUP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VEORd, ARM_INS_VEOR, + {ARM_VEORd, ARM_INS_VEOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VEORq, ARM_INS_VEOR, + {ARM_VEORq, ARM_INS_VEOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VEXTd16, ARM_INS_VEXT, + {ARM_VEXTd16, + ARM_INS_VEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VEXTd32, ARM_INS_VEXT, + {ARM_VEXTd32, + ARM_INS_VEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VEXTd8, ARM_INS_VEXT, + {ARM_VEXTd8, ARM_INS_VEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VEXTq16, ARM_INS_VEXT, + {ARM_VEXTq16, + ARM_INS_VEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VEXTq32, ARM_INS_VEXT, + {ARM_VEXTq32, + ARM_INS_VEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VEXTq64, ARM_INS_VEXT, + {ARM_VEXTq64, + ARM_INS_VEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VEXTq8, ARM_INS_VEXT, + {ARM_VEXTq8, ARM_INS_VEXT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMAD, ARM_INS_VFMA, + {ARM_VFMAD, ARM_INS_VFMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP4, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMAH, ARM_INS_VFMA, + {ARM_VFMAH, ARM_INS_VFMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMAS, ARM_INS_VFMA, + {ARM_VFMAS, ARM_INS_VFMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP4, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMAfd, ARM_INS_VFMA, + {ARM_VFMAfd, ARM_INS_VFMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, ARM_GRP_VFP4, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMAfq, ARM_INS_VFMA, + {ARM_VFMAfq, ARM_INS_VFMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, ARM_GRP_VFP4, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMAhd, ARM_INS_VFMA, + {ARM_VFMAhd, ARM_INS_VFMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMAhq, ARM_INS_VFMA, + {ARM_VFMAhq, ARM_INS_VFMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMSD, ARM_INS_VFMS, + {ARM_VFMSD, ARM_INS_VFMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP4, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMSH, ARM_INS_VFMS, + {ARM_VFMSH, ARM_INS_VFMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMSS, ARM_INS_VFMS, + {ARM_VFMSS, ARM_INS_VFMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP4, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMSfd, ARM_INS_VFMS, + {ARM_VFMSfd, ARM_INS_VFMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, ARM_GRP_VFP4, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMSfq, ARM_INS_VFMS, + {ARM_VFMSfq, ARM_INS_VFMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, ARM_GRP_VFP4, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMShd, ARM_INS_VFMS, + {ARM_VFMShd, ARM_INS_VFMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VFMShq, ARM_INS_VFMS, + {ARM_VFMShq, ARM_INS_VFMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VFNMAD, ARM_INS_VFNMA, + {ARM_VFNMAD, ARM_INS_VFNMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP4, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFNMAH, ARM_INS_VFNMA, + {ARM_VFNMAH, ARM_INS_VFNMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VFNMAS, ARM_INS_VFNMA, + {ARM_VFNMAS, ARM_INS_VFNMA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP4, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFNMSD, ARM_INS_VFNMS, + {ARM_VFNMSD, ARM_INS_VFNMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP4, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VFNMSH, ARM_INS_VFNMS, + {ARM_VFNMSH, ARM_INS_VFNMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VFNMSS, ARM_INS_VFNMS, + {ARM_VFNMSS, ARM_INS_VFNMS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP4, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VGETLNi32, ARM_INS_VMOV, + {ARM_VGETLNi32, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VGETLNs16, ARM_INS_VMOV, + {ARM_VGETLNs16, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VGETLNs8, ARM_INS_VMOV, + {ARM_VGETLNs8, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VGETLNu16, ARM_INS_VMOV, + {ARM_VGETLNu16, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VGETLNu8, ARM_INS_VMOV, + {ARM_VGETLNu8, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDsv16i8, ARM_INS_VHADD, + {ARM_VHADDsv16i8, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDsv2i32, ARM_INS_VHADD, + {ARM_VHADDsv2i32, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDsv4i16, ARM_INS_VHADD, + {ARM_VHADDsv4i16, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDsv4i32, ARM_INS_VHADD, + {ARM_VHADDsv4i32, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDsv8i16, ARM_INS_VHADD, + {ARM_VHADDsv8i16, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDsv8i8, ARM_INS_VHADD, + {ARM_VHADDsv8i8, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDuv16i8, ARM_INS_VHADD, + {ARM_VHADDuv16i8, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDuv2i32, ARM_INS_VHADD, + {ARM_VHADDuv2i32, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDuv4i16, ARM_INS_VHADD, + {ARM_VHADDuv4i16, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDuv4i32, ARM_INS_VHADD, + {ARM_VHADDuv4i32, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDuv8i16, ARM_INS_VHADD, + {ARM_VHADDuv8i16, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHADDuv8i8, ARM_INS_VHADD, + {ARM_VHADDuv8i8, + ARM_INS_VHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBsv16i8, ARM_INS_VHSUB, + {ARM_VHSUBsv16i8, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBsv2i32, ARM_INS_VHSUB, + {ARM_VHSUBsv2i32, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBsv4i16, ARM_INS_VHSUB, + {ARM_VHSUBsv4i16, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBsv4i32, ARM_INS_VHSUB, + {ARM_VHSUBsv4i32, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBsv8i16, ARM_INS_VHSUB, + {ARM_VHSUBsv8i16, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBsv8i8, ARM_INS_VHSUB, + {ARM_VHSUBsv8i8, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBuv16i8, ARM_INS_VHSUB, + {ARM_VHSUBuv16i8, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBuv2i32, ARM_INS_VHSUB, + {ARM_VHSUBuv2i32, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBuv4i16, ARM_INS_VHSUB, + {ARM_VHSUBuv4i16, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBuv4i32, ARM_INS_VHSUB, + {ARM_VHSUBuv4i32, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBuv8i16, ARM_INS_VHSUB, + {ARM_VHSUBuv8i16, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VHSUBuv8i8, ARM_INS_VHSUB, + {ARM_VHSUBuv8i8, + ARM_INS_VHSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VINSH, ARM_INS_VINS, + {ARM_VINSH, ARM_INS_VINS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VJCVT, ARM_INS_VJCVT, + {ARM_VJCVT, ARM_INS_VJCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPd16, ARM_INS_VLD1, + {ARM_VLD1DUPd16, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1, + {ARM_VLD1DUPd16wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPd16wb_register, ARM_INS_VLD1, + {ARM_VLD1DUPd16wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPd32, ARM_INS_VLD1, + {ARM_VLD1DUPd32, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1, + {ARM_VLD1DUPd32wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPd32wb_register, ARM_INS_VLD1, + {ARM_VLD1DUPd32wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPd8, ARM_INS_VLD1, + {ARM_VLD1DUPd8, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1, + {ARM_VLD1DUPd8wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPd8wb_register, ARM_INS_VLD1, + {ARM_VLD1DUPd8wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPq16, ARM_INS_VLD1, + {ARM_VLD1DUPq16, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1, + {ARM_VLD1DUPq16wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPq16wb_register, ARM_INS_VLD1, + {ARM_VLD1DUPq16wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPq32, ARM_INS_VLD1, + {ARM_VLD1DUPq32, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1, + {ARM_VLD1DUPq32wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPq32wb_register, ARM_INS_VLD1, + {ARM_VLD1DUPq32wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPq8, ARM_INS_VLD1, + {ARM_VLD1DUPq8, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1, + {ARM_VLD1DUPq8wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1DUPq8wb_register, ARM_INS_VLD1, + {ARM_VLD1DUPq8wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNd16, ARM_INS_VLD1, + {ARM_VLD1LNd16, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNd16_UPD, ARM_INS_VLD1, + {ARM_VLD1LNd16_UPD, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNd32, ARM_INS_VLD1, + {ARM_VLD1LNd32, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNd32_UPD, ARM_INS_VLD1, + {ARM_VLD1LNd32_UPD, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNd8, ARM_INS_VLD1, + {ARM_VLD1LNd8, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1LNd8_UPD, ARM_INS_VLD1, + {ARM_VLD1LNd8_UPD, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d16, ARM_INS_VLD1, + {ARM_VLD1d16, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d16Q, ARM_INS_VLD1, + {ARM_VLD1d16Q, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1, + {ARM_VLD1d16Qwb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d16Qwb_register, ARM_INS_VLD1, + {ARM_VLD1d16Qwb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d16T, ARM_INS_VLD1, + {ARM_VLD1d16T, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d16Twb_fixed, ARM_INS_VLD1, + {ARM_VLD1d16Twb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d16Twb_register, ARM_INS_VLD1, + {ARM_VLD1d16Twb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d16wb_fixed, ARM_INS_VLD1, + {ARM_VLD1d16wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d16wb_register, ARM_INS_VLD1, + {ARM_VLD1d16wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d32, ARM_INS_VLD1, + {ARM_VLD1d32, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d32Q, ARM_INS_VLD1, + {ARM_VLD1d32Q, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1, + {ARM_VLD1d32Qwb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d32Qwb_register, ARM_INS_VLD1, + {ARM_VLD1d32Qwb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d32T, ARM_INS_VLD1, + {ARM_VLD1d32T, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d32Twb_fixed, ARM_INS_VLD1, + {ARM_VLD1d32Twb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d32Twb_register, ARM_INS_VLD1, + {ARM_VLD1d32Twb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d32wb_fixed, ARM_INS_VLD1, + {ARM_VLD1d32wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d32wb_register, ARM_INS_VLD1, + {ARM_VLD1d32wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d64, ARM_INS_VLD1, + {ARM_VLD1d64, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d64Q, ARM_INS_VLD1, + {ARM_VLD1d64Q, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1, + {ARM_VLD1d64Qwb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d64Qwb_register, ARM_INS_VLD1, + {ARM_VLD1d64Qwb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d64T, ARM_INS_VLD1, + {ARM_VLD1d64T, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d64Twb_fixed, ARM_INS_VLD1, + {ARM_VLD1d64Twb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d64Twb_register, ARM_INS_VLD1, + {ARM_VLD1d64Twb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d64wb_fixed, ARM_INS_VLD1, + {ARM_VLD1d64wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d64wb_register, ARM_INS_VLD1, + {ARM_VLD1d64wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d8, ARM_INS_VLD1, + {ARM_VLD1d8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD1d8Q, ARM_INS_VLD1, + {ARM_VLD1d8Q, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1, + {ARM_VLD1d8Qwb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d8Qwb_register, ARM_INS_VLD1, + {ARM_VLD1d8Qwb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d8T, ARM_INS_VLD1, + {ARM_VLD1d8T, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d8Twb_fixed, ARM_INS_VLD1, + {ARM_VLD1d8Twb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d8Twb_register, ARM_INS_VLD1, + {ARM_VLD1d8Twb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d8wb_fixed, ARM_INS_VLD1, + {ARM_VLD1d8wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1d8wb_register, ARM_INS_VLD1, + {ARM_VLD1d8wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q16, ARM_INS_VLD1, + {ARM_VLD1q16, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q16wb_fixed, ARM_INS_VLD1, + {ARM_VLD1q16wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q16wb_register, ARM_INS_VLD1, + {ARM_VLD1q16wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q32, ARM_INS_VLD1, + {ARM_VLD1q32, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q32wb_fixed, ARM_INS_VLD1, + {ARM_VLD1q32wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q32wb_register, ARM_INS_VLD1, + {ARM_VLD1q32wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q64, ARM_INS_VLD1, + {ARM_VLD1q64, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q64wb_fixed, ARM_INS_VLD1, + {ARM_VLD1q64wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q64wb_register, ARM_INS_VLD1, + {ARM_VLD1q64wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q8, ARM_INS_VLD1, + {ARM_VLD1q8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD1q8wb_fixed, ARM_INS_VLD1, + {ARM_VLD1q8wb_fixed, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD1q8wb_register, ARM_INS_VLD1, + {ARM_VLD1q8wb_register, + ARM_INS_VLD1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd16, ARM_INS_VLD2, + {ARM_VLD2DUPd16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2, + {ARM_VLD2DUPd16wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd16wb_register, ARM_INS_VLD2, + {ARM_VLD2DUPd16wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd16x2, ARM_INS_VLD2, + {ARM_VLD2DUPd16x2, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2, + {ARM_VLD2DUPd16x2wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2, + {ARM_VLD2DUPd16x2wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd32, ARM_INS_VLD2, + {ARM_VLD2DUPd32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2, + {ARM_VLD2DUPd32wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd32wb_register, ARM_INS_VLD2, + {ARM_VLD2DUPd32wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd32x2, ARM_INS_VLD2, + {ARM_VLD2DUPd32x2, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2, + {ARM_VLD2DUPd32x2wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2, + {ARM_VLD2DUPd32x2wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd8, ARM_INS_VLD2, + {ARM_VLD2DUPd8, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2, + {ARM_VLD2DUPd8wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd8wb_register, ARM_INS_VLD2, + {ARM_VLD2DUPd8wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd8x2, ARM_INS_VLD2, + {ARM_VLD2DUPd8x2, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2, + {ARM_VLD2DUPd8x2wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2, + {ARM_VLD2DUPd8x2wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNd16, ARM_INS_VLD2, + {ARM_VLD2LNd16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNd16_UPD, ARM_INS_VLD2, + {ARM_VLD2LNd16_UPD, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNd32, ARM_INS_VLD2, + {ARM_VLD2LNd32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNd32_UPD, ARM_INS_VLD2, + {ARM_VLD2LNd32_UPD, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNd8, ARM_INS_VLD2, + {ARM_VLD2LNd8, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNd8_UPD, ARM_INS_VLD2, + {ARM_VLD2LNd8_UPD, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNq16, ARM_INS_VLD2, + {ARM_VLD2LNq16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNq16_UPD, ARM_INS_VLD2, + {ARM_VLD2LNq16_UPD, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNq32, ARM_INS_VLD2, + {ARM_VLD2LNq32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2LNq32_UPD, ARM_INS_VLD2, + {ARM_VLD2LNq32_UPD, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2b16, ARM_INS_VLD2, + {ARM_VLD2b16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2b16wb_fixed, ARM_INS_VLD2, + {ARM_VLD2b16wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2b16wb_register, ARM_INS_VLD2, + {ARM_VLD2b16wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2b32, ARM_INS_VLD2, + {ARM_VLD2b32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2b32wb_fixed, ARM_INS_VLD2, + {ARM_VLD2b32wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2b32wb_register, ARM_INS_VLD2, + {ARM_VLD2b32wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2b8, ARM_INS_VLD2, + {ARM_VLD2b8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD2b8wb_fixed, ARM_INS_VLD2, + {ARM_VLD2b8wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2b8wb_register, ARM_INS_VLD2, + {ARM_VLD2b8wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2d16, ARM_INS_VLD2, + {ARM_VLD2d16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2d16wb_fixed, ARM_INS_VLD2, + {ARM_VLD2d16wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2d16wb_register, ARM_INS_VLD2, + {ARM_VLD2d16wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2d32, ARM_INS_VLD2, + {ARM_VLD2d32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2d32wb_fixed, ARM_INS_VLD2, + {ARM_VLD2d32wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2d32wb_register, ARM_INS_VLD2, + {ARM_VLD2d32wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2d8, ARM_INS_VLD2, + {ARM_VLD2d8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD2d8wb_fixed, ARM_INS_VLD2, + {ARM_VLD2d8wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2d8wb_register, ARM_INS_VLD2, + {ARM_VLD2d8wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2q16, ARM_INS_VLD2, + {ARM_VLD2q16, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2q16wb_fixed, ARM_INS_VLD2, + {ARM_VLD2q16wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2q16wb_register, ARM_INS_VLD2, + {ARM_VLD2q16wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2q32, ARM_INS_VLD2, + {ARM_VLD2q32, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2q32wb_fixed, ARM_INS_VLD2, + {ARM_VLD2q32wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2q32wb_register, ARM_INS_VLD2, + {ARM_VLD2q32wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2q8, ARM_INS_VLD2, + {ARM_VLD2q8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD2q8wb_fixed, ARM_INS_VLD2, + {ARM_VLD2q8wb_fixed, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD2q8wb_register, ARM_INS_VLD2, + {ARM_VLD2q8wb_register, + ARM_INS_VLD2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPd16, ARM_INS_VLD3, + {ARM_VLD3DUPd16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPd16_UPD, ARM_INS_VLD3, + {ARM_VLD3DUPd16_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPd32, ARM_INS_VLD3, + {ARM_VLD3DUPd32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPd32_UPD, ARM_INS_VLD3, + {ARM_VLD3DUPd32_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPd8, ARM_INS_VLD3, + {ARM_VLD3DUPd8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPd8_UPD, ARM_INS_VLD3, + {ARM_VLD3DUPd8_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPq16, ARM_INS_VLD3, + {ARM_VLD3DUPq16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPq16_UPD, ARM_INS_VLD3, + {ARM_VLD3DUPq16_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPq32, ARM_INS_VLD3, + {ARM_VLD3DUPq32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPq32_UPD, ARM_INS_VLD3, + {ARM_VLD3DUPq32_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPq8, ARM_INS_VLD3, + {ARM_VLD3DUPq8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3DUPq8_UPD, ARM_INS_VLD3, + {ARM_VLD3DUPq8_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNd16, ARM_INS_VLD3, + {ARM_VLD3LNd16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNd16_UPD, ARM_INS_VLD3, + {ARM_VLD3LNd16_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNd32, ARM_INS_VLD3, + {ARM_VLD3LNd32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNd32_UPD, ARM_INS_VLD3, + {ARM_VLD3LNd32_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNd8, ARM_INS_VLD3, + {ARM_VLD3LNd8, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNd8_UPD, ARM_INS_VLD3, + {ARM_VLD3LNd8_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNq16, ARM_INS_VLD3, + {ARM_VLD3LNq16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNq16_UPD, ARM_INS_VLD3, + {ARM_VLD3LNq16_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNq32, ARM_INS_VLD3, + {ARM_VLD3LNq32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3LNq32_UPD, ARM_INS_VLD3, + {ARM_VLD3LNq32_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3d16, ARM_INS_VLD3, + {ARM_VLD3d16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3d16_UPD, ARM_INS_VLD3, + {ARM_VLD3d16_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3d32, ARM_INS_VLD3, + {ARM_VLD3d32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3d32_UPD, ARM_INS_VLD3, + {ARM_VLD3d32_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3d8, ARM_INS_VLD3, + {ARM_VLD3d8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD3d8_UPD, ARM_INS_VLD3, + {ARM_VLD3d8_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3q16, ARM_INS_VLD3, + {ARM_VLD3q16, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3q16_UPD, ARM_INS_VLD3, + {ARM_VLD3q16_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3q32, ARM_INS_VLD3, + {ARM_VLD3q32, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3q32_UPD, ARM_INS_VLD3, + {ARM_VLD3q32_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD3q8, ARM_INS_VLD3, + {ARM_VLD3q8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD3q8_UPD, ARM_INS_VLD3, + {ARM_VLD3q8_UPD, + ARM_INS_VLD3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPd16, ARM_INS_VLD4, + {ARM_VLD4DUPd16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPd16_UPD, ARM_INS_VLD4, + {ARM_VLD4DUPd16_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPd32, ARM_INS_VLD4, + {ARM_VLD4DUPd32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPd32_UPD, ARM_INS_VLD4, + {ARM_VLD4DUPd32_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPd8, ARM_INS_VLD4, + {ARM_VLD4DUPd8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPd8_UPD, ARM_INS_VLD4, + {ARM_VLD4DUPd8_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPq16, ARM_INS_VLD4, + {ARM_VLD4DUPq16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPq16_UPD, ARM_INS_VLD4, + {ARM_VLD4DUPq16_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPq32, ARM_INS_VLD4, + {ARM_VLD4DUPq32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPq32_UPD, ARM_INS_VLD4, + {ARM_VLD4DUPq32_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPq8, ARM_INS_VLD4, + {ARM_VLD4DUPq8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4DUPq8_UPD, ARM_INS_VLD4, + {ARM_VLD4DUPq8_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNd16, ARM_INS_VLD4, + {ARM_VLD4LNd16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNd16_UPD, ARM_INS_VLD4, + {ARM_VLD4LNd16_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNd32, ARM_INS_VLD4, + {ARM_VLD4LNd32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNd32_UPD, ARM_INS_VLD4, + {ARM_VLD4LNd32_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNd8, ARM_INS_VLD4, + {ARM_VLD4LNd8, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNd8_UPD, ARM_INS_VLD4, + {ARM_VLD4LNd8_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNq16, ARM_INS_VLD4, + {ARM_VLD4LNq16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNq16_UPD, ARM_INS_VLD4, + {ARM_VLD4LNq16_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNq32, ARM_INS_VLD4, + {ARM_VLD4LNq32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4LNq32_UPD, ARM_INS_VLD4, + {ARM_VLD4LNq32_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4d16, ARM_INS_VLD4, + {ARM_VLD4d16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4d16_UPD, ARM_INS_VLD4, + {ARM_VLD4d16_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4d32, ARM_INS_VLD4, + {ARM_VLD4d32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4d32_UPD, ARM_INS_VLD4, + {ARM_VLD4d32_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4d8, ARM_INS_VLD4, + {ARM_VLD4d8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD4d8_UPD, ARM_INS_VLD4, + {ARM_VLD4d8_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4q16, ARM_INS_VLD4, + {ARM_VLD4q16, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4q16_UPD, ARM_INS_VLD4, + {ARM_VLD4q16_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4q32, ARM_INS_VLD4, + {ARM_VLD4q32, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4q32_UPD, ARM_INS_VLD4, + {ARM_VLD4q32_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLD4q8, ARM_INS_VLD4, + {ARM_VLD4q8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLD4q8_UPD, ARM_INS_VLD4, + {ARM_VLD4q8_UPD, + ARM_INS_VLD4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLDMDDB_UPD, ARM_INS_VLDMDB, + {ARM_VLDMDDB_UPD, + ARM_INS_VLDMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLDMDIA, ARM_INS_VLDMIA, + {ARM_VLDMDIA, + ARM_INS_VLDMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLDMDIA_UPD, ARM_INS_VLDMIA, + {ARM_VLDMDIA_UPD, + ARM_INS_VLDMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLDMSDB_UPD, ARM_INS_VLDMDB, + {ARM_VLDMSDB_UPD, + ARM_INS_VLDMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLDMSIA, ARM_INS_VLDMIA, + {ARM_VLDMSIA, + ARM_INS_VLDMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLDMSIA_UPD, ARM_INS_VLDMIA, + {ARM_VLDMSIA_UPD, + ARM_INS_VLDMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VLDRD, ARM_INS_VLDR, + {ARM_VLDRD, ARM_INS_VLDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLDRH, ARM_INS_VLDR, + {ARM_VLDRH, ARM_INS_VLDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VLDRS, ARM_INS_VLDR, + {ARM_VLDRS, ARM_INS_VLDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VLLDM, ARM_INS_VLLDM, + {ARM_VLLDM, ARM_INS_VLLDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VLSTM, ARM_INS_VLSTM, + {ARM_VLSTM, ARM_INS_VLSTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMAXNMD, ARM_INS_VMAXNM, + {ARM_VMAXfd, ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMAXNMH, ARM_INS_VMAXNM, + {ARM_VMAXfq, ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMAXNMNDf, ARM_INS_VMAXNM, + {ARM_VMAXhd, ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMAXNMNDh, ARM_INS_VMAXNM, + {ARM_VMAXhq, ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMAXNMNQf, ARM_INS_VMAXNM, + {ARM_VMAXsv16i8, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXNMNQh, ARM_INS_VMAXNM, + {ARM_VMAXsv2i32, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXNMS, ARM_INS_VMAXNM, + {ARM_VMAXsv4i16, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXfd, ARM_INS_VMAX, + {ARM_VMAXsv4i32, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXfq, ARM_INS_VMAX, + {ARM_VMAXsv8i16, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXhd, ARM_INS_VMAX, + {ARM_VMAXsv8i8, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXhq, ARM_INS_VMAX, + {ARM_VMAXuv16i8, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXsv16i8, ARM_INS_VMAX, + {ARM_VMAXuv2i32, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXsv2i32, ARM_INS_VMAX, + {ARM_VMAXuv4i16, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXsv4i16, ARM_INS_VMAX, + {ARM_VMAXuv4i32, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXsv4i32, ARM_INS_VMAX, + {ARM_VMAXuv8i16, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXsv8i16, ARM_INS_VMAX, + {ARM_VMAXuv8i8, + ARM_INS_VMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXsv8i8, ARM_INS_VMAX, + {ARM_VMINfd, ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMAXuv16i8, ARM_INS_VMAX, + {ARM_VMINfq, ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMAXuv2i32, ARM_INS_VMAX, + {ARM_VMINhd, ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMAXuv4i16, ARM_INS_VMAX, + {ARM_VMINhq, ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMAXuv4i32, ARM_INS_VMAX, + {ARM_VMINsv16i8, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXuv8i16, ARM_INS_VMAX, + {ARM_VMINsv2i32, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMAXuv8i8, ARM_INS_VMAX, + {ARM_VMINsv4i16, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINNMD, ARM_INS_VMINNM, + {ARM_VMINsv4i32, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINNMH, ARM_INS_VMINNM, + {ARM_VMINsv8i16, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINNMNDf, ARM_INS_VMINNM, + {ARM_VMINsv8i8, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINNMNDh, ARM_INS_VMINNM, + {ARM_VMINuv16i8, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINNMNQf, ARM_INS_VMINNM, + {ARM_VMINuv2i32, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINNMNQh, ARM_INS_VMINNM, + {ARM_VMINuv4i16, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINNMS, ARM_INS_VMINNM, + {ARM_VMINuv4i32, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINfd, ARM_INS_VMIN, + {ARM_VMINuv8i16, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINfq, ARM_INS_VMIN, + {ARM_VMINuv8i8, + ARM_INS_VMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINhd, ARM_INS_VMIN, + {ARM_VMLAD, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINhq, ARM_INS_VMIN, + {ARM_VMLAH, ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMINsv16i8, ARM_INS_VMIN, + {ARM_VMLALslsv2i32, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINsv2i32, ARM_INS_VMIN, + {ARM_VMLALslsv4i16, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINsv4i16, ARM_INS_VMIN, + {ARM_VMLALsluv2i32, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINsv4i32, ARM_INS_VMIN, + {ARM_VMLALsluv4i16, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINsv8i16, ARM_INS_VMIN, + {ARM_VMLALsv2i64, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINsv8i8, ARM_INS_VMIN, + {ARM_VMLALsv4i32, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINuv16i8, ARM_INS_VMIN, + {ARM_VMLALsv8i16, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINuv2i32, ARM_INS_VMIN, + {ARM_VMLALuv2i64, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINuv4i16, ARM_INS_VMIN, + {ARM_VMLALuv4i32, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINuv4i32, ARM_INS_VMIN, + {ARM_VMLALuv8i16, + ARM_INS_VMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMINuv8i16, ARM_INS_VMIN, + {ARM_VMLAS, ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMINuv8i8, ARM_INS_VMIN, + {ARM_VMLAfd, ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, ARM_GRP_FPVMLX, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLAD, ARM_INS_VMLA, + {ARM_VMLAfq, ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, ARM_GRP_FPVMLX, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLAH, ARM_INS_VMLA, + {ARM_VMLAhd, ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLALslsv2i32, ARM_INS_VMLAL, + {ARM_VMLAhq, ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLALslsv4i16, ARM_INS_VMLAL, + {ARM_VMLAslfd, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, ARM_GRP_FPVMLX, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLALsluv2i32, ARM_INS_VMLAL, + {ARM_VMLAslfq, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, ARM_GRP_FPVMLX, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLALsluv4i16, ARM_INS_VMLAL, + {ARM_VMLAslhd, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLALsv2i64, ARM_INS_VMLAL, + {ARM_VMLAslhq, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLALsv4i32, ARM_INS_VMLAL, + {ARM_VMLAslv2i32, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLALsv8i16, ARM_INS_VMLAL, + {ARM_VMLAslv4i16, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLALuv2i64, ARM_INS_VMLAL, + {ARM_VMLAslv4i32, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLALuv4i32, ARM_INS_VMLAL, + {ARM_VMLAslv8i16, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLALuv8i16, ARM_INS_VMLAL, + {ARM_VMLAv16i8, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAS, ARM_INS_VMLA, + {ARM_VMLAv2i32, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAfd, ARM_INS_VMLA, + {ARM_VMLAv4i16, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAfq, ARM_INS_VMLA, + {ARM_VMLAv4i32, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAhd, ARM_INS_VMLA, + {ARM_VMLAv8i16, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAhq, ARM_INS_VMLA, + {ARM_VMLAv8i8, + ARM_INS_VMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAslfd, ARM_INS_VMLA, + {ARM_VMLSD, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAslfq, ARM_INS_VMLA, + {ARM_VMLSH, ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLAslhd, ARM_INS_VMLA, + {ARM_VMLSLslsv2i32, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAslhq, ARM_INS_VMLA, + {ARM_VMLSLslsv4i16, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAslv2i32, ARM_INS_VMLA, + {ARM_VMLSLsluv2i32, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAslv4i16, ARM_INS_VMLA, + {ARM_VMLSLsluv4i16, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAslv4i32, ARM_INS_VMLA, + {ARM_VMLSLsv2i64, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAslv8i16, ARM_INS_VMLA, + {ARM_VMLSLsv4i32, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAv16i8, ARM_INS_VMLA, + {ARM_VMLSLsv8i16, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAv2i32, ARM_INS_VMLA, + {ARM_VMLSLuv2i64, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAv4i16, ARM_INS_VMLA, + {ARM_VMLSLuv4i32, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAv4i32, ARM_INS_VMLA, + {ARM_VMLSLuv8i16, + ARM_INS_VMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLAv8i16, ARM_INS_VMLA, + {ARM_VMLSS, ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLAv8i8, ARM_INS_VMLA, + {ARM_VMLSfd, ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, ARM_GRP_FPVMLX, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLSD, ARM_INS_VMLS, + {ARM_VMLSfq, ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, ARM_GRP_FPVMLX, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLSH, ARM_INS_VMLS, + {ARM_VMLShd, ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLSLslsv2i32, ARM_INS_VMLSL, + {ARM_VMLShq, ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLSLslsv4i16, ARM_INS_VMLSL, + {ARM_VMLSslfd, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, ARM_GRP_FPVMLX, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSLsluv2i32, ARM_INS_VMLSL, + {ARM_VMLSslfq, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, ARM_GRP_FPVMLX, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSLsluv4i16, ARM_INS_VMLSL, + {ARM_VMLSslhd, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSLsv2i64, ARM_INS_VMLSL, + {ARM_VMLSslhq, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSLsv4i32, ARM_INS_VMLSL, + {ARM_VMLSslv2i32, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSLsv8i16, ARM_INS_VMLSL, + {ARM_VMLSslv4i16, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSLuv2i64, ARM_INS_VMLSL, + {ARM_VMLSslv4i32, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSLuv4i32, ARM_INS_VMLSL, + {ARM_VMLSslv8i16, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSLuv8i16, ARM_INS_VMLSL, + {ARM_VMLSv16i8, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSS, ARM_INS_VMLS, + {ARM_VMLSv2i32, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSfd, ARM_INS_VMLS, + {ARM_VMLSv4i16, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSfq, ARM_INS_VMLS, + {ARM_VMLSv4i32, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLShd, ARM_INS_VMLS, + {ARM_VMLSv8i16, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLShq, ARM_INS_VMLS, + {ARM_VMLSv8i8, + ARM_INS_VMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSslfd, ARM_INS_VMLS, + {ARM_VMOVD, ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLSslfq, ARM_INS_VMLS, + {ARM_VMOVDRR, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSslhd, ARM_INS_VMLS, + {ARM_VMOVH, ARM_INS_VMOVX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLSslhq, ARM_INS_VMLS, + {ARM_VMOVHR, ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMLSslv2i32, ARM_INS_VMLS, + {ARM_VMOVLsv2i64, + ARM_INS_VMOVL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSslv4i16, ARM_INS_VMLS, + {ARM_VMOVLsv4i32, + ARM_INS_VMOVL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSslv4i32, ARM_INS_VMLS, + {ARM_VMOVLsv8i16, + ARM_INS_VMOVL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSslv8i16, ARM_INS_VMLS, + {ARM_VMOVLuv2i64, + ARM_INS_VMOVL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSv16i8, ARM_INS_VMLS, + {ARM_VMOVLuv4i32, + ARM_INS_VMOVL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSv2i32, ARM_INS_VMLS, + {ARM_VMOVLuv8i16, + ARM_INS_VMOVL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSv4i16, ARM_INS_VMLS, + {ARM_VMOVNv2i32, + ARM_INS_VMOVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSv4i32, ARM_INS_VMLS, + {ARM_VMOVNv4i16, + ARM_INS_VMOVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSv8i16, ARM_INS_VMLS, + {ARM_VMOVNv8i8, + ARM_INS_VMOVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMLSv8i8, ARM_INS_VMLS, + {ARM_VMOVRH, ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMOVD, ARM_INS_VMOV, + {ARM_VMOVRRD, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVDRR, ARM_INS_VMOV, + {ARM_VMOVRRS, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVH, ARM_INS_VMOVX, + {ARM_VMOVRS, ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMOVHR, ARM_INS_VMOV, + {ARM_VMOVS, ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMOVLsv2i64, ARM_INS_VMOVL, + {ARM_VMOVSR, ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMOVLsv4i32, ARM_INS_VMOVL, + {ARM_VMOVSRR, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVLsv8i16, ARM_INS_VMOVL, + {ARM_VMOVv16i8, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVLuv2i64, ARM_INS_VMOVL, + {ARM_VMOVv1i64, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVLuv4i32, ARM_INS_VMOVL, + {ARM_VMOVv2f32, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVLuv8i16, ARM_INS_VMOVL, + {ARM_VMOVv2i32, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVNv2i32, ARM_INS_VMOVN, + {ARM_VMOVv2i64, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVNv4i16, ARM_INS_VMOVN, + {ARM_VMOVv4f32, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVNv8i8, ARM_INS_VMOVN, + {ARM_VMOVv4i16, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVRH, ARM_INS_VMOV, + {ARM_VMOVv4i32, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVRRD, ARM_INS_VMOV, + {ARM_VMOVv8i16, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVRRS, ARM_INS_VMOV, + {ARM_VMOVv8i8, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVRS, ARM_INS_VMOV, + {ARM_VMRS, + ARM_INS_VMRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVS, ARM_INS_VMOV, + {ARM_VMRS_FPEXC, + ARM_INS_VMRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVSR, ARM_INS_VMOV, + {ARM_VMRS_FPINST, + ARM_INS_VMRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVSRR, ARM_INS_VMOV, + {ARM_VMRS_FPINST2, + ARM_INS_VMRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVv16i8, ARM_INS_VMOV, + {ARM_VMRS_FPSID, + ARM_INS_VMRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVv1i64, ARM_INS_VMOV, + {ARM_VMRS_MVFR0, + ARM_INS_VMRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVv2f32, ARM_INS_VMOV, + {ARM_VMRS_MVFR1, + ARM_INS_VMRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVv2i32, ARM_INS_VMOV, + {ARM_VMRS_MVFR2, + ARM_INS_VMRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVv2i64, ARM_INS_VMOV, + {ARM_VMSR, ARM_INS_VMSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {ARM_REG_FPSCR, 0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMOVv4f32, ARM_INS_VMOV, + {ARM_VMSR_FPEXC, + ARM_INS_VMSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR, 0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVv4i16, ARM_INS_VMOV, + {ARM_VMSR_FPINST, + ARM_INS_VMSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR, 0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVv4i32, ARM_INS_VMOV, + {ARM_VMSR_FPINST2, + ARM_INS_VMSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR, 0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVv8i16, ARM_INS_VMOV, + {ARM_VMSR_FPSID, + ARM_INS_VMSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {ARM_REG_FPSCR, 0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMOVv8i8, ARM_INS_VMOV, + {ARM_VMULD, ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMRS, ARM_INS_VMRS, + {ARM_VMULH, ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMRS_FPEXC, ARM_INS_VMRS, + {ARM_VMULLp64, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_V8, ARM_GRP_CRYPTO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMRS_FPINST, ARM_INS_VMRS, + {ARM_VMULLp8, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMRS_FPINST2, ARM_INS_VMRS, + {ARM_VMULLslsv2i32, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMRS_FPSID, ARM_INS_VMRS, + {ARM_VMULLslsv4i16, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMRS_MVFR0, ARM_INS_VMRS, + {ARM_VMULLsluv2i32, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMRS_MVFR1, ARM_INS_VMRS, + {ARM_VMULLsluv4i16, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMRS_MVFR2, ARM_INS_VMRS, + {ARM_VMULLsv2i64, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMSR, ARM_INS_VMSR, + {ARM_VMULLsv4i32, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMSR_FPEXC, ARM_INS_VMSR, + {ARM_VMULLsv8i16, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMSR_FPINST, ARM_INS_VMSR, + {ARM_VMULLuv2i64, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMSR_FPINST2, ARM_INS_VMSR, + {ARM_VMULLuv4i32, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMSR_FPSID, ARM_INS_VMSR, + {ARM_VMULLuv8i16, + ARM_INS_VMULL, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULD, ARM_INS_VMUL, + {ARM_VMULS, ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULH, ARM_INS_VMUL, + {ARM_VMULfd, ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULLp64, ARM_INS_VMULL, + {ARM_VMULfq, ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULLp8, ARM_INS_VMULL, + {ARM_VMULhd, ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULLslsv2i32, ARM_INS_VMULL, + {ARM_VMULhq, ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULLslsv4i16, ARM_INS_VMULL, + {ARM_VMULpd, ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULLsluv2i32, ARM_INS_VMULL, + {ARM_VMULpq, ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULLsluv4i16, ARM_INS_VMULL, + {ARM_VMULslfd, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULLsv2i64, ARM_INS_VMULL, + {ARM_VMULslfq, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULLsv4i32, ARM_INS_VMULL, + {ARM_VMULslhd, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULLsv8i16, ARM_INS_VMULL, + {ARM_VMULslhq, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULLuv2i64, ARM_INS_VMULL, + {ARM_VMULslv2i32, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULLuv4i32, ARM_INS_VMULL, + {ARM_VMULslv4i16, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULLuv8i16, ARM_INS_VMULL, + {ARM_VMULslv4i32, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULS, ARM_INS_VMUL, + {ARM_VMULslv8i16, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULfd, ARM_INS_VMUL, + {ARM_VMULv16i8, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULfq, ARM_INS_VMUL, + {ARM_VMULv2i32, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULhd, ARM_INS_VMUL, + {ARM_VMULv4i16, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULhq, ARM_INS_VMUL, + {ARM_VMULv4i32, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULpd, ARM_INS_VMUL, + {ARM_VMULv8i16, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULpq, ARM_INS_VMUL, + {ARM_VMULv8i8, + ARM_INS_VMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULslfd, ARM_INS_VMUL, + {ARM_VMVNd, ARM_INS_VMVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULslfq, ARM_INS_VMUL, + {ARM_VMVNq, ARM_INS_VMVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULslhd, ARM_INS_VMUL, + {ARM_VMVNv2i32, + ARM_INS_VMVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULslhq, ARM_INS_VMUL, + {ARM_VMVNv4i16, + ARM_INS_VMVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULslv2i32, ARM_INS_VMUL, + {ARM_VMVNv4i32, + ARM_INS_VMVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULslv4i16, ARM_INS_VMUL, + {ARM_VMVNv8i16, + ARM_INS_VMVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULslv4i32, ARM_INS_VMUL, + {ARM_VNEGD, ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULslv8i16, ARM_INS_VMUL, + {ARM_VNEGH, ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULv16i8, ARM_INS_VMUL, + {ARM_VNEGS, ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULv2i32, ARM_INS_VMUL, + {ARM_VNEGf32q, + ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMULv4i16, ARM_INS_VMUL, + {ARM_VNEGfd, ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULv4i32, ARM_INS_VMUL, + {ARM_VNEGhd, ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULv8i16, ARM_INS_VMUL, + {ARM_VNEGhq, ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VMULv8i8, ARM_INS_VMUL, + {ARM_VNEGs16d, + ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMVNd, ARM_INS_VMVN, + {ARM_VNEGs16q, + ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMVNq, ARM_INS_VMVN, + {ARM_VNEGs32d, + ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMVNv2i32, ARM_INS_VMVN, + {ARM_VNEGs32q, + ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMVNv4i16, ARM_INS_VMVN, + {ARM_VNEGs8d, + ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMVNv4i32, ARM_INS_VMVN, + {ARM_VNEGs8q, + ARM_INS_VNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VMVNv8i16, ARM_INS_VMVN, + {ARM_VNMLAD, + ARM_INS_VNMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNEGD, ARM_INS_VNEG, + {ARM_VNMLAH, ARM_INS_VNMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGH, ARM_INS_VNEG, + {ARM_VNMLAS, ARM_INS_VNMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGS, ARM_INS_VNEG, + {ARM_VNMLSD, + ARM_INS_VNMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNEGf32q, ARM_INS_VNEG, + {ARM_VNMLSH, ARM_INS_VNMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGfd, ARM_INS_VNEG, + {ARM_VNMLSS, ARM_INS_VNMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGhd, ARM_INS_VNEG, + {ARM_VNMULD, ARM_INS_VNMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGhq, ARM_INS_VNEG, + {ARM_VNMULH, ARM_INS_VNMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGs16d, ARM_INS_VNEG, + {ARM_VNMULS, ARM_INS_VNMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGs16q, ARM_INS_VNEG, + {ARM_VORNd, ARM_INS_VORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGs32d, ARM_INS_VNEG, + {ARM_VORNq, ARM_INS_VORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGs32q, ARM_INS_VNEG, + {ARM_VORRd, ARM_INS_VORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VNEGs8d, ARM_INS_VNEG, + {ARM_VORRiv2i32, + ARM_INS_VORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNEGs8q, ARM_INS_VNEG, + {ARM_VORRiv4i16, + ARM_INS_VORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNMLAD, ARM_INS_VNMLA, + {ARM_VORRiv4i32, + ARM_INS_VORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNMLAH, ARM_INS_VNMLA, + {ARM_VORRiv8i16, + ARM_INS_VORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNMLAS, ARM_INS_VNMLA, + {ARM_VORRq, ARM_INS_VORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VNMLSD, ARM_INS_VNMLS, + {ARM_VPADALsv16i8, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNMLSH, ARM_INS_VNMLS, + {ARM_VPADALsv2i32, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNMLSS, ARM_INS_VNMLS, + {ARM_VPADALsv4i16, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNMULD, ARM_INS_VNMUL, + {ARM_VPADALsv4i32, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNMULH, ARM_INS_VNMUL, + {ARM_VPADALsv8i16, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VNMULS, ARM_INS_VNMUL, + {ARM_VPADALsv8i8, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VORNd, ARM_INS_VORN, + {ARM_VPADALuv16i8, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VORNq, ARM_INS_VORN, + {ARM_VPADALuv2i32, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VORRd, ARM_INS_VORR, + {ARM_VPADALuv4i16, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VORRiv2i32, ARM_INS_VORR, + {ARM_VPADALuv4i32, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VORRiv4i16, ARM_INS_VORR, + {ARM_VPADALuv8i16, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VORRiv4i32, ARM_INS_VORR, + {ARM_VPADALuv8i8, + ARM_INS_VPADAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VORRiv8i16, ARM_INS_VORR, + {ARM_VPADDLsv16i8, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VORRq, ARM_INS_VORR, + {ARM_VPADDLsv2i32, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALsv16i8, ARM_INS_VPADAL, + {ARM_VPADDLsv4i16, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALsv2i32, ARM_INS_VPADAL, + {ARM_VPADDLsv4i32, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALsv4i16, ARM_INS_VPADAL, + {ARM_VPADDLsv8i16, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALsv4i32, ARM_INS_VPADAL, + {ARM_VPADDLsv8i8, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALsv8i16, ARM_INS_VPADAL, + {ARM_VPADDLuv16i8, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALsv8i8, ARM_INS_VPADAL, + {ARM_VPADDLuv2i32, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALuv16i8, ARM_INS_VPADAL, + {ARM_VPADDLuv4i16, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALuv2i32, ARM_INS_VPADAL, + {ARM_VPADDLuv4i32, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALuv4i16, ARM_INS_VPADAL, + {ARM_VPADDLuv8i16, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALuv4i32, ARM_INS_VPADAL, + {ARM_VPADDLuv8i8, + ARM_INS_VPADDL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADALuv8i16, ARM_INS_VPADAL, + {ARM_VPADDf, ARM_INS_VPADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VPADALuv8i8, ARM_INS_VPADAL, + {ARM_VPADDh, ARM_INS_VPADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VPADDLsv16i8, ARM_INS_VPADDL, + {ARM_VPADDi16, + ARM_INS_VPADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDLsv2i32, ARM_INS_VPADDL, + {ARM_VPADDi32, + ARM_INS_VPADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDLsv4i16, ARM_INS_VPADDL, + {ARM_VPADDi8, + ARM_INS_VPADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDLsv4i32, ARM_INS_VPADDL, + {ARM_VPMAXf, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VPADDLsv8i16, ARM_INS_VPADDL, + {ARM_VPMAXh, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VPADDLsv8i8, ARM_INS_VPADDL, + {ARM_VPMAXs16, + ARM_INS_VPMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDLuv16i8, ARM_INS_VPADDL, + {ARM_VPMAXs32, + ARM_INS_VPMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDLuv2i32, ARM_INS_VPADDL, + {ARM_VPMAXs8, + ARM_INS_VPMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDLuv4i16, ARM_INS_VPADDL, + {ARM_VPMAXu16, + ARM_INS_VPMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDLuv4i32, ARM_INS_VPADDL, + {ARM_VPMAXu32, + ARM_INS_VPMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDLuv8i16, ARM_INS_VPADDL, + {ARM_VPMAXu8, + ARM_INS_VPMAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDLuv8i8, ARM_INS_VPADDL, + {ARM_VPMINf, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VPADDf, ARM_INS_VPADD, + {ARM_VPMINh, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VPADDh, ARM_INS_VPADD, + {ARM_VPMINs16, + ARM_INS_VPMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDi16, ARM_INS_VPADD, + {ARM_VPMINs32, + ARM_INS_VPMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDi32, ARM_INS_VPADD, + {ARM_VPMINs8, + ARM_INS_VPMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPADDi8, ARM_INS_VPADD, + {ARM_VPMINu16, + ARM_INS_VPMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMAXf, ARM_INS_VPMAX, + {ARM_VPMINu32, + ARM_INS_VPMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMAXh, ARM_INS_VPMAX, + {ARM_VPMINu8, + ARM_INS_VPMIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMAXs16, ARM_INS_VPMAX, + {ARM_VQABSv16i8, + ARM_INS_VQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMAXs32, ARM_INS_VPMAX, + {ARM_VQABSv2i32, + ARM_INS_VQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMAXs8, ARM_INS_VPMAX, + {ARM_VQABSv4i16, + ARM_INS_VQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMAXu16, ARM_INS_VPMAX, + {ARM_VQABSv4i32, + ARM_INS_VQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMAXu32, ARM_INS_VPMAX, + {ARM_VQABSv8i16, + ARM_INS_VQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMAXu8, ARM_INS_VPMAX, + {ARM_VQABSv8i8, + ARM_INS_VQABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMINf, ARM_INS_VPMIN, + {ARM_VQADDsv16i8, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMINh, ARM_INS_VPMIN, + {ARM_VQADDsv1i64, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMINs16, ARM_INS_VPMIN, + {ARM_VQADDsv2i32, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMINs32, ARM_INS_VPMIN, + {ARM_VQADDsv2i64, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMINs8, ARM_INS_VPMIN, + {ARM_VQADDsv4i16, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMINu16, ARM_INS_VPMIN, + {ARM_VQADDsv4i32, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMINu32, ARM_INS_VPMIN, + {ARM_VQADDsv8i16, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VPMINu8, ARM_INS_VPMIN, + {ARM_VQADDsv8i8, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQABSv16i8, ARM_INS_VQABS, + {ARM_VQADDuv16i8, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQABSv2i32, ARM_INS_VQABS, + {ARM_VQADDuv1i64, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQABSv4i16, ARM_INS_VQABS, + {ARM_VQADDuv2i32, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQABSv4i32, ARM_INS_VQABS, + {ARM_VQADDuv2i64, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQABSv8i16, ARM_INS_VQABS, + {ARM_VQADDuv4i16, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQABSv8i8, ARM_INS_VQABS, + {ARM_VQADDuv4i32, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDsv16i8, ARM_INS_VQADD, + {ARM_VQADDuv8i16, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDsv1i64, ARM_INS_VQADD, + {ARM_VQADDuv8i8, + ARM_INS_VQADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDsv2i32, ARM_INS_VQADD, + {ARM_VQDMLALslv2i32, + ARM_INS_VQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDsv2i64, ARM_INS_VQADD, + {ARM_VQDMLALslv4i16, + ARM_INS_VQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDsv4i16, ARM_INS_VQADD, + {ARM_VQDMLALv2i64, + ARM_INS_VQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDsv4i32, ARM_INS_VQADD, + {ARM_VQDMLALv4i32, + ARM_INS_VQDMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDsv8i16, ARM_INS_VQADD, + {ARM_VQDMLSLslv2i32, + ARM_INS_VQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDsv8i8, ARM_INS_VQADD, + {ARM_VQDMLSLslv4i16, + ARM_INS_VQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDuv16i8, ARM_INS_VQADD, + {ARM_VQDMLSLv2i64, + ARM_INS_VQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDuv1i64, ARM_INS_VQADD, + {ARM_VQDMLSLv4i32, + ARM_INS_VQDMLSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDuv2i32, ARM_INS_VQADD, + {ARM_VQDMULHslv2i32, + ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDuv2i64, ARM_INS_VQADD, + {ARM_VQDMULHslv4i16, + ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDuv4i16, ARM_INS_VQADD, + {ARM_VQDMULHslv4i32, + ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDuv4i32, ARM_INS_VQADD, + {ARM_VQDMULHslv8i16, + ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDuv8i16, ARM_INS_VQADD, + {ARM_VQDMULHv2i32, + ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQADDuv8i8, ARM_INS_VQADD, + {ARM_VQDMULHv4i16, + ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL, + {ARM_VQDMULHv4i32, + ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL, + {ARM_VQDMULHv8i16, + ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMLALv2i64, ARM_INS_VQDMLAL, + {ARM_VQDMULLslv2i32, + ARM_INS_VQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMLALv4i32, ARM_INS_VQDMLAL, + {ARM_VQDMULLslv4i16, + ARM_INS_VQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL, + {ARM_VQDMULLv2i64, + ARM_INS_VQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL, + {ARM_VQDMULLv4i32, + ARM_INS_VQDMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL, + {ARM_VQMOVNsuv2i32, + ARM_INS_VQMOVUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL, + {ARM_VQMOVNsuv4i16, + ARM_INS_VQMOVUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULHslv2i32, ARM_INS_VQDMULH, + {ARM_VQMOVNsuv8i8, + ARM_INS_VQMOVUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULHslv4i16, ARM_INS_VQDMULH, + {ARM_VQMOVNsv2i32, + ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULHslv4i32, ARM_INS_VQDMULH, + {ARM_VQMOVNsv4i16, + ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULHslv8i16, ARM_INS_VQDMULH, + {ARM_VQMOVNsv8i8, + ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULHv2i32, ARM_INS_VQDMULH, + {ARM_VQMOVNuv2i32, + ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULHv4i16, ARM_INS_VQDMULH, + {ARM_VQMOVNuv4i16, + ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULHv4i32, ARM_INS_VQDMULH, + {ARM_VQMOVNuv8i8, + ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULHv8i16, ARM_INS_VQDMULH, + {ARM_VQNEGv16i8, + ARM_INS_VQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULLslv2i32, ARM_INS_VQDMULL, + {ARM_VQNEGv2i32, + ARM_INS_VQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULLslv4i16, ARM_INS_VQDMULL, + {ARM_VQNEGv4i16, + ARM_INS_VQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULLv2i64, ARM_INS_VQDMULL, + {ARM_VQNEGv4i32, + ARM_INS_VQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQDMULLv4i32, ARM_INS_VQDMULL, + {ARM_VQNEGv8i16, + ARM_INS_VQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN, + {ARM_VQNEGv8i8, + ARM_INS_VQNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN, + {ARM_VQRDMLAHslv2i32, + ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN, + {ARM_VQRDMLAHslv4i16, + ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQMOVNsv2i32, ARM_INS_VQMOVN, + {ARM_VQRDMLAHslv4i32, + ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQMOVNsv4i16, ARM_INS_VQMOVN, + {ARM_VQRDMLAHslv8i16, + ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQMOVNsv8i8, ARM_INS_VQMOVN, + {ARM_VQRDMLAHv2i32, + ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQMOVNuv2i32, ARM_INS_VQMOVN, + {ARM_VQRDMLAHv4i16, + ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQMOVNuv4i16, ARM_INS_VQMOVN, + {ARM_VQRDMLAHv4i32, + ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQMOVNuv8i8, ARM_INS_VQMOVN, + {ARM_VQRDMLAHv8i16, + ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQNEGv16i8, ARM_INS_VQNEG, + {ARM_VQRDMLSHslv2i32, + ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQNEGv2i32, ARM_INS_VQNEG, + {ARM_VQRDMLSHslv4i16, + ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQNEGv4i16, ARM_INS_VQNEG, + {ARM_VQRDMLSHslv4i32, + ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQNEGv4i32, ARM_INS_VQNEG, + {ARM_VQRDMLSHslv8i16, + ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQNEGv8i16, ARM_INS_VQNEG, + {ARM_VQRDMLSHv2i32, + ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQNEGv8i8, ARM_INS_VQNEG, + {ARM_VQRDMLSHv4i16, + ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLAHslv2i32, ARM_INS_VQRDMLAH, + {ARM_VQRDMLSHv4i32, + ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLAHslv4i16, ARM_INS_VQRDMLAH, + {ARM_VQRDMLSHv8i16, + ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLAHslv4i32, ARM_INS_VQRDMLAH, + {ARM_VQRDMULHslv2i32, + ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLAHslv8i16, ARM_INS_VQRDMLAH, + {ARM_VQRDMULHslv4i16, + ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLAHv2i32, ARM_INS_VQRDMLAH, + {ARM_VQRDMULHslv4i32, + ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLAHv4i16, ARM_INS_VQRDMLAH, + {ARM_VQRDMULHslv8i16, + ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLAHv4i32, ARM_INS_VQRDMLAH, + {ARM_VQRDMULHv2i32, + ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLAHv8i16, ARM_INS_VQRDMLAH, + {ARM_VQRDMULHv4i16, + ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLSHslv2i32, ARM_INS_VQRDMLSH, + {ARM_VQRDMULHv4i32, + ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLSHslv4i16, ARM_INS_VQRDMLSH, + {ARM_VQRDMULHv8i16, + ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLSHslv4i32, ARM_INS_VQRDMLSH, + {ARM_VQRSHLsv16i8, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLSHslv8i16, ARM_INS_VQRDMLSH, + {ARM_VQRSHLsv1i64, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLSHv2i32, ARM_INS_VQRDMLSH, + {ARM_VQRSHLsv2i32, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLSHv4i16, ARM_INS_VQRDMLSH, + {ARM_VQRSHLsv2i64, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLSHv4i32, ARM_INS_VQRDMLSH, + {ARM_VQRSHLsv4i16, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMLSHv8i16, ARM_INS_VQRDMLSH, + {ARM_VQRSHLsv4i32, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH, + {ARM_VQRSHLsv8i16, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH, + {ARM_VQRSHLsv8i8, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH, + {ARM_VQRSHLuv16i8, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH, + {ARM_VQRSHLuv1i64, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH, + {ARM_VQRSHLuv2i32, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH, + {ARM_VQRSHLuv2i64, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH, + {ARM_VQRSHLuv4i16, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH, + {ARM_VQRSHLuv4i32, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLsv16i8, ARM_INS_VQRSHL, + {ARM_VQRSHLuv8i16, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLsv1i64, ARM_INS_VQRSHL, + {ARM_VQRSHLuv8i8, + ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLsv2i32, ARM_INS_VQRSHL, + {ARM_VQRSHRNsv2i32, + ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLsv2i64, ARM_INS_VQRSHL, + {ARM_VQRSHRNsv4i16, + ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLsv4i16, ARM_INS_VQRSHL, + {ARM_VQRSHRNsv8i8, + ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLsv4i32, ARM_INS_VQRSHL, + {ARM_VQRSHRNuv2i32, + ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLsv8i16, ARM_INS_VQRSHL, + {ARM_VQRSHRNuv4i16, + ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLsv8i8, ARM_INS_VQRSHL, + {ARM_VQRSHRNuv8i8, + ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLuv16i8, ARM_INS_VQRSHL, + {ARM_VQRSHRUNv2i32, + ARM_INS_VQRSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLuv1i64, ARM_INS_VQRSHL, + {ARM_VQRSHRUNv4i16, + ARM_INS_VQRSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLuv2i32, ARM_INS_VQRSHL, + {ARM_VQRSHRUNv8i8, + ARM_INS_VQRSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLuv2i64, ARM_INS_VQRSHL, + {ARM_VQSHLsiv16i8, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLuv4i16, ARM_INS_VQRSHL, + {ARM_VQSHLsiv1i64, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLuv4i32, ARM_INS_VQRSHL, + {ARM_VQSHLsiv2i32, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLuv8i16, ARM_INS_VQRSHL, + {ARM_VQSHLsiv2i64, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHLuv8i8, ARM_INS_VQRSHL, + {ARM_VQSHLsiv4i16, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN, + {ARM_VQSHLsiv4i32, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN, + {ARM_VQSHLsiv8i16, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN, + {ARM_VQSHLsiv8i8, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN, + {ARM_VQSHLsuv16i8, + ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN, + {ARM_VQSHLsuv1i64, + ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN, + {ARM_VQSHLsuv2i32, + ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN, + {ARM_VQSHLsuv2i64, + ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN, + {ARM_VQSHLsuv4i16, + ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN, + {ARM_VQSHLsuv4i32, + ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsiv16i8, ARM_INS_VQSHL, + {ARM_VQSHLsuv8i16, + ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsiv1i64, ARM_INS_VQSHL, + {ARM_VQSHLsuv8i8, + ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsiv2i32, ARM_INS_VQSHL, + {ARM_VQSHLsv16i8, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsiv2i64, ARM_INS_VQSHL, + {ARM_VQSHLsv1i64, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsiv4i16, ARM_INS_VQSHL, + {ARM_VQSHLsv2i32, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsiv4i32, ARM_INS_VQSHL, + {ARM_VQSHLsv2i64, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsiv8i16, ARM_INS_VQSHL, + {ARM_VQSHLsv4i16, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsiv8i8, ARM_INS_VQSHL, + {ARM_VQSHLsv4i32, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsuv16i8, ARM_INS_VQSHLU, + {ARM_VQSHLsv8i16, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsuv1i64, ARM_INS_VQSHLU, + {ARM_VQSHLsv8i8, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsuv2i32, ARM_INS_VQSHLU, + {ARM_VQSHLuiv16i8, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsuv2i64, ARM_INS_VQSHLU, + {ARM_VQSHLuiv1i64, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsuv4i16, ARM_INS_VQSHLU, + {ARM_VQSHLuiv2i32, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsuv4i32, ARM_INS_VQSHLU, + {ARM_VQSHLuiv2i64, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsuv8i16, ARM_INS_VQSHLU, + {ARM_VQSHLuiv4i16, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsuv8i8, ARM_INS_VQSHLU, + {ARM_VQSHLuiv4i32, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsv16i8, ARM_INS_VQSHL, + {ARM_VQSHLuiv8i16, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsv1i64, ARM_INS_VQSHL, + {ARM_VQSHLuiv8i8, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsv2i32, ARM_INS_VQSHL, + {ARM_VQSHLuv16i8, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsv2i64, ARM_INS_VQSHL, + {ARM_VQSHLuv1i64, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsv4i16, ARM_INS_VQSHL, + {ARM_VQSHLuv2i32, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsv4i32, ARM_INS_VQSHL, + {ARM_VQSHLuv2i64, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsv8i16, ARM_INS_VQSHL, + {ARM_VQSHLuv4i16, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLsv8i8, ARM_INS_VQSHL, + {ARM_VQSHLuv4i32, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuiv16i8, ARM_INS_VQSHL, + {ARM_VQSHLuv8i16, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuiv1i64, ARM_INS_VQSHL, + {ARM_VQSHLuv8i8, + ARM_INS_VQSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuiv2i32, ARM_INS_VQSHL, + {ARM_VQSHRNsv2i32, + ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuiv2i64, ARM_INS_VQSHL, + {ARM_VQSHRNsv4i16, + ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuiv4i16, ARM_INS_VQSHL, + {ARM_VQSHRNsv8i8, + ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuiv4i32, ARM_INS_VQSHL, + {ARM_VQSHRNuv2i32, + ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuiv8i16, ARM_INS_VQSHL, + {ARM_VQSHRNuv4i16, + ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuiv8i8, ARM_INS_VQSHL, + {ARM_VQSHRNuv8i8, + ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuv16i8, ARM_INS_VQSHL, + {ARM_VQSHRUNv2i32, + ARM_INS_VQSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuv1i64, ARM_INS_VQSHL, + {ARM_VQSHRUNv4i16, + ARM_INS_VQSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuv2i32, ARM_INS_VQSHL, + {ARM_VQSHRUNv8i8, + ARM_INS_VQSHRUN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuv2i64, ARM_INS_VQSHL, + {ARM_VQSUBsv16i8, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuv4i16, ARM_INS_VQSHL, + {ARM_VQSUBsv1i64, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuv4i32, ARM_INS_VQSHL, + {ARM_VQSUBsv2i32, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuv8i16, ARM_INS_VQSHL, + {ARM_VQSUBsv2i64, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHLuv8i8, ARM_INS_VQSHL, + {ARM_VQSUBsv4i16, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHRNsv2i32, ARM_INS_VQSHRN, + {ARM_VQSUBsv4i32, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHRNsv4i16, ARM_INS_VQSHRN, + {ARM_VQSUBsv8i16, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHRNsv8i8, ARM_INS_VQSHRN, + {ARM_VQSUBsv8i8, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHRNuv2i32, ARM_INS_VQSHRN, + {ARM_VQSUBuv16i8, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHRNuv4i16, ARM_INS_VQSHRN, + {ARM_VQSUBuv1i64, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHRNuv8i8, ARM_INS_VQSHRN, + {ARM_VQSUBuv2i32, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN, + {ARM_VQSUBuv2i64, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN, + {ARM_VQSUBuv4i16, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN, + {ARM_VQSUBuv4i32, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBsv16i8, ARM_INS_VQSUB, + {ARM_VQSUBuv8i16, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBsv1i64, ARM_INS_VQSUB, + {ARM_VQSUBuv8i8, + ARM_INS_VQSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBsv2i32, ARM_INS_VQSUB, + {ARM_VRADDHNv2i32, + ARM_INS_VRADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBsv2i64, ARM_INS_VQSUB, + {ARM_VRADDHNv4i16, + ARM_INS_VRADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBsv4i16, ARM_INS_VQSUB, + {ARM_VRADDHNv8i8, + ARM_INS_VRADDHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBsv4i32, ARM_INS_VQSUB, + {ARM_VRECPEd, + ARM_INS_VRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBsv8i16, ARM_INS_VQSUB, + {ARM_VRECPEfd, + ARM_INS_VRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBsv8i8, ARM_INS_VQSUB, + {ARM_VRECPEfq, + ARM_INS_VRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBuv16i8, ARM_INS_VQSUB, + {ARM_VRECPEhd, + ARM_INS_VRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBuv1i64, ARM_INS_VQSUB, + {ARM_VRECPEhq, + ARM_INS_VRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBuv2i32, ARM_INS_VQSUB, + {ARM_VRECPEq, + ARM_INS_VRECPE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBuv2i64, ARM_INS_VQSUB, + {ARM_VRECPSfd, + ARM_INS_VRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBuv4i16, ARM_INS_VQSUB, + {ARM_VRECPSfq, + ARM_INS_VRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBuv4i32, ARM_INS_VQSUB, + {ARM_VRECPShd, + ARM_INS_VRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBuv8i16, ARM_INS_VQSUB, + {ARM_VRECPShq, + ARM_INS_VRECPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VQSUBuv8i8, ARM_INS_VQSUB, + {ARM_VREV16d8, + ARM_INS_VREV16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRADDHNv2i32, ARM_INS_VRADDHN, + {ARM_VREV16q8, + ARM_INS_VREV16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRADDHNv4i16, ARM_INS_VRADDHN, + {ARM_VREV32d16, + ARM_INS_VREV32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRADDHNv8i8, ARM_INS_VRADDHN, + {ARM_VREV32d8, + ARM_INS_VREV32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPEd, ARM_INS_VRECPE, + {ARM_VREV32q16, + ARM_INS_VREV32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPEfd, ARM_INS_VRECPE, + {ARM_VREV32q8, + ARM_INS_VREV32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPEfq, ARM_INS_VRECPE, + {ARM_VREV64d16, + ARM_INS_VREV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPEhd, ARM_INS_VRECPE, + {ARM_VREV64d32, + ARM_INS_VREV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPEhq, ARM_INS_VRECPE, + {ARM_VREV64d8, + ARM_INS_VREV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPEq, ARM_INS_VRECPE, + {ARM_VREV64q16, + ARM_INS_VREV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPSfd, ARM_INS_VRECPS, + {ARM_VREV64q32, + ARM_INS_VREV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPSfq, ARM_INS_VRECPS, + {ARM_VREV64q8, + ARM_INS_VREV64, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPShd, ARM_INS_VRECPS, + {ARM_VRHADDsv16i8, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRECPShq, ARM_INS_VRECPS, + {ARM_VRHADDsv2i32, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV16d8, ARM_INS_VREV16, + {ARM_VRHADDsv4i16, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV16q8, ARM_INS_VREV16, + {ARM_VRHADDsv4i32, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV32d16, ARM_INS_VREV32, + {ARM_VRHADDsv8i16, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV32d8, ARM_INS_VREV32, + {ARM_VRHADDsv8i8, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV32q16, ARM_INS_VREV32, + {ARM_VRHADDuv16i8, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV32q8, ARM_INS_VREV32, + {ARM_VRHADDuv2i32, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV64d16, ARM_INS_VREV64, + {ARM_VRHADDuv4i16, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV64d32, ARM_INS_VREV64, + {ARM_VRHADDuv4i32, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV64d8, ARM_INS_VREV64, + {ARM_VRHADDuv8i16, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV64q16, ARM_INS_VREV64, + {ARM_VRHADDuv8i8, + ARM_INS_VRHADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV64q32, ARM_INS_VREV64, + {ARM_VRINTAD, + ARM_INS_VRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VREV64q8, ARM_INS_VREV64, + {ARM_VRINTAH, + ARM_INS_VRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDsv16i8, ARM_INS_VRHADD, + {ARM_VRINTANDf, + ARM_INS_VRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDsv2i32, ARM_INS_VRHADD, + {ARM_VRINTANDh, + ARM_INS_VRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDsv4i16, ARM_INS_VRHADD, + {ARM_VRINTANQf, + ARM_INS_VRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDsv4i32, ARM_INS_VRHADD, + {ARM_VRINTANQh, + ARM_INS_VRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDsv8i16, ARM_INS_VRHADD, + {ARM_VRINTAS, + ARM_INS_VRINTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDsv8i8, ARM_INS_VRHADD, + {ARM_VRINTMD, + ARM_INS_VRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDuv16i8, ARM_INS_VRHADD, + {ARM_VRINTMH, + ARM_INS_VRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDuv2i32, ARM_INS_VRHADD, + {ARM_VRINTMNDf, + ARM_INS_VRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDuv4i16, ARM_INS_VRHADD, + {ARM_VRINTMNDh, + ARM_INS_VRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDuv4i32, ARM_INS_VRHADD, + {ARM_VRINTMNQf, + ARM_INS_VRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDuv8i16, ARM_INS_VRHADD, + {ARM_VRINTMNQh, + ARM_INS_VRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRHADDuv8i8, ARM_INS_VRHADD, + {ARM_VRINTMS, + ARM_INS_VRINTM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTAD, ARM_INS_VRINTA, + {ARM_VRINTND, + ARM_INS_VRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTAH, ARM_INS_VRINTA, + {ARM_VRINTNH, + ARM_INS_VRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTANDf, ARM_INS_VRINTA, + {ARM_VRINTNNDf, + ARM_INS_VRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTANDh, ARM_INS_VRINTA, + {ARM_VRINTNNDh, + ARM_INS_VRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTANQf, ARM_INS_VRINTA, + {ARM_VRINTNNQf, + ARM_INS_VRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTANQh, ARM_INS_VRINTA, + {ARM_VRINTNNQh, + ARM_INS_VRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTAS, ARM_INS_VRINTA, + {ARM_VRINTNS, + ARM_INS_VRINTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTMD, ARM_INS_VRINTM, + {ARM_VRINTPD, + ARM_INS_VRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTMH, ARM_INS_VRINTM, + {ARM_VRINTPH, + ARM_INS_VRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTMNDf, ARM_INS_VRINTM, + {ARM_VRINTPNDf, + ARM_INS_VRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTMNDh, ARM_INS_VRINTM, + {ARM_VRINTPNDh, + ARM_INS_VRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTMNQf, ARM_INS_VRINTM, + {ARM_VRINTPNQf, + ARM_INS_VRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTMNQh, ARM_INS_VRINTM, + {ARM_VRINTPNQh, + ARM_INS_VRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTMS, ARM_INS_VRINTM, + {ARM_VRINTPS, + ARM_INS_VRINTP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTND, ARM_INS_VRINTN, + {ARM_VRINTRD, + ARM_INS_VRINTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTNH, ARM_INS_VRINTN, + {ARM_VRINTRH, + ARM_INS_VRINTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTNNDf, ARM_INS_VRINTN, + {ARM_VRINTRS, + ARM_INS_VRINTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTNNDh, ARM_INS_VRINTN, + {ARM_VRINTXD, + ARM_INS_VRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTNNQf, ARM_INS_VRINTN, + {ARM_VRINTXH, + ARM_INS_VRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTNNQh, ARM_INS_VRINTN, + {ARM_VRINTXNDf, + ARM_INS_VRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTNS, ARM_INS_VRINTN, + {ARM_VRINTXNDh, + ARM_INS_VRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTPD, ARM_INS_VRINTP, + {ARM_VRINTXNQf, + ARM_INS_VRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTPH, ARM_INS_VRINTP, + {ARM_VRINTXNQh, + ARM_INS_VRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTPNDf, ARM_INS_VRINTP, + {ARM_VRINTXS, + ARM_INS_VRINTX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTPNDh, ARM_INS_VRINTP, + {ARM_VRINTZD, + ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTPNQf, ARM_INS_VRINTP, + {ARM_VRINTZH, + ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTPNQh, ARM_INS_VRINTP, + {ARM_VRINTZNDf, + ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTPS, ARM_INS_VRINTP, + {ARM_VRINTZNDh, + ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTRD, ARM_INS_VRINTR, + {ARM_VRINTZNQf, + ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTRH, ARM_INS_VRINTR, + {ARM_VRINTZNQh, + ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTRS, ARM_INS_VRINTR, + {ARM_VRINTZS, + ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTXD, ARM_INS_VRINTX, + {ARM_VRSHLsv16i8, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTXH, ARM_INS_VRINTX, + {ARM_VRSHLsv1i64, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTXNDf, ARM_INS_VRINTX, + {ARM_VRSHLsv2i32, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTXNDh, ARM_INS_VRINTX, + {ARM_VRSHLsv2i64, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTXNQf, ARM_INS_VRINTX, + {ARM_VRSHLsv4i16, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTXNQh, ARM_INS_VRINTX, + {ARM_VRSHLsv4i32, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTXS, ARM_INS_VRINTX, + {ARM_VRSHLsv8i16, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTZD, ARM_INS_VRINTZ, + {ARM_VRSHLsv8i8, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTZH, ARM_INS_VRINTZ, + {ARM_VRSHLuv16i8, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTZNDf, ARM_INS_VRINTZ, + {ARM_VRSHLuv1i64, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTZNDh, ARM_INS_VRINTZ, + {ARM_VRSHLuv2i32, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTZNQf, ARM_INS_VRINTZ, + {ARM_VRSHLuv2i64, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTZNQh, ARM_INS_VRINTZ, + {ARM_VRSHLuv4i16, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRINTZS, ARM_INS_VRINTZ, + {ARM_VRSHLuv4i32, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLsv16i8, ARM_INS_VRSHL, + {ARM_VRSHLuv8i16, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLsv1i64, ARM_INS_VRSHL, + {ARM_VRSHLuv8i8, + ARM_INS_VRSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLsv2i32, ARM_INS_VRSHL, + {ARM_VRSHRNv2i32, + ARM_INS_VRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLsv2i64, ARM_INS_VRSHL, + {ARM_VRSHRNv4i16, + ARM_INS_VRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLsv4i16, ARM_INS_VRSHL, + {ARM_VRSHRNv8i8, + ARM_INS_VRSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLsv4i32, ARM_INS_VRSHL, + {ARM_VRSHRsv16i8, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLsv8i16, ARM_INS_VRSHL, + {ARM_VRSHRsv1i64, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLsv8i8, ARM_INS_VRSHL, + {ARM_VRSHRsv2i32, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLuv16i8, ARM_INS_VRSHL, + {ARM_VRSHRsv2i64, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLuv1i64, ARM_INS_VRSHL, + {ARM_VRSHRsv4i16, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLuv2i32, ARM_INS_VRSHL, + {ARM_VRSHRsv4i32, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLuv2i64, ARM_INS_VRSHL, + {ARM_VRSHRsv8i16, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLuv4i16, ARM_INS_VRSHL, + {ARM_VRSHRsv8i8, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLuv4i32, ARM_INS_VRSHL, + {ARM_VRSHRuv16i8, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLuv8i16, ARM_INS_VRSHL, + {ARM_VRSHRuv1i64, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHLuv8i8, ARM_INS_VRSHL, + {ARM_VRSHRuv2i32, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRNv2i32, ARM_INS_VRSHRN, + {ARM_VRSHRuv2i64, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRNv4i16, ARM_INS_VRSHRN, + {ARM_VRSHRuv4i16, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRNv8i8, ARM_INS_VRSHRN, + {ARM_VRSHRuv4i32, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRsv16i8, ARM_INS_VRSHR, + {ARM_VRSHRuv8i16, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRsv1i64, ARM_INS_VRSHR, + {ARM_VRSHRuv8i8, + ARM_INS_VRSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRsv2i32, ARM_INS_VRSHR, + {ARM_VRSQRTEd, + ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRsv2i64, ARM_INS_VRSHR, + {ARM_VRSQRTEfd, + ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRsv4i16, ARM_INS_VRSHR, + {ARM_VRSQRTEfq, + ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRsv4i32, ARM_INS_VRSHR, + {ARM_VRSQRTEhd, + ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRsv8i16, ARM_INS_VRSHR, + {ARM_VRSQRTEhq, + ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRsv8i8, ARM_INS_VRSHR, + {ARM_VRSQRTEq, + ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRuv16i8, ARM_INS_VRSHR, + {ARM_VRSQRTSfd, + ARM_INS_VRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRuv1i64, ARM_INS_VRSHR, + {ARM_VRSQRTSfq, + ARM_INS_VRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRuv2i32, ARM_INS_VRSHR, + {ARM_VRSQRTShd, + ARM_INS_VRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRuv2i64, ARM_INS_VRSHR, + {ARM_VRSQRTShq, + ARM_INS_VRSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRuv4i16, ARM_INS_VRSHR, + {ARM_VRSRAsv16i8, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRuv4i32, ARM_INS_VRSHR, + {ARM_VRSRAsv1i64, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRuv8i16, ARM_INS_VRSHR, + {ARM_VRSRAsv2i32, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSHRuv8i8, ARM_INS_VRSHR, + {ARM_VRSRAsv2i64, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTEd, ARM_INS_VRSQRTE, + {ARM_VRSRAsv4i16, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTEfd, ARM_INS_VRSQRTE, + {ARM_VRSRAsv4i32, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTEfq, ARM_INS_VRSQRTE, + {ARM_VRSRAsv8i16, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTEhd, ARM_INS_VRSQRTE, + {ARM_VRSRAsv8i8, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTEhq, ARM_INS_VRSQRTE, + {ARM_VRSRAuv16i8, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTEq, ARM_INS_VRSQRTE, + {ARM_VRSRAuv1i64, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTSfd, ARM_INS_VRSQRTS, + {ARM_VRSRAuv2i32, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTSfq, ARM_INS_VRSQRTS, + {ARM_VRSRAuv2i64, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTShd, ARM_INS_VRSQRTS, + {ARM_VRSRAuv4i16, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSQRTShq, ARM_INS_VRSQRTS, + {ARM_VRSRAuv4i32, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAsv16i8, ARM_INS_VRSRA, + {ARM_VRSRAuv8i16, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAsv1i64, ARM_INS_VRSRA, + {ARM_VRSRAuv8i8, + ARM_INS_VRSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAsv2i32, ARM_INS_VRSRA, + {ARM_VRSUBHNv2i32, + ARM_INS_VRSUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAsv2i64, ARM_INS_VRSRA, + {ARM_VRSUBHNv4i16, + ARM_INS_VRSUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAsv4i16, ARM_INS_VRSRA, + {ARM_VRSUBHNv8i8, + ARM_INS_VRSUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAsv4i32, ARM_INS_VRSRA, + {ARM_VSDOTD, ARM_INS_VSDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VRSRAsv8i16, ARM_INS_VRSRA, + {ARM_VSDOTDI, + ARM_INS_VSDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAsv8i8, ARM_INS_VRSRA, + {ARM_VSDOTQ, ARM_INS_VSDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VRSRAuv16i8, ARM_INS_VRSRA, + {ARM_VSDOTQI, + ARM_INS_VSDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAuv1i64, ARM_INS_VRSRA, + {ARM_VSELEQD, + ARM_INS_VSELEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAuv2i32, ARM_INS_VRSRA, + {ARM_VSELEQH, + ARM_INS_VSELEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAuv2i64, ARM_INS_VRSRA, + {ARM_VSELEQS, + ARM_INS_VSELEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAuv4i16, ARM_INS_VRSRA, + {ARM_VSELGED, + ARM_INS_VSELGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAuv4i32, ARM_INS_VRSRA, + {ARM_VSELGEH, + ARM_INS_VSELGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAuv8i16, ARM_INS_VRSRA, + {ARM_VSELGES, + ARM_INS_VSELGE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSRAuv8i8, ARM_INS_VRSRA, + {ARM_VSELGTD, + ARM_INS_VSELGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN, + {ARM_VSELGTH, + ARM_INS_VSELGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN, + {ARM_VSELGTS, + ARM_INS_VSELGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN, + {ARM_VSELVSD, + ARM_INS_VSELVS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSDOTD, ARM_INS_VSDOT, + {ARM_VSELVSH, + ARM_INS_VSELVS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSDOTDI, ARM_INS_VSDOT, + {ARM_VSELVSS, + ARM_INS_VSELVS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_FPARMV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSDOTQ, ARM_INS_VSDOT, + {ARM_VSETLNi16, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSDOTQI, ARM_INS_VSDOT, + {ARM_VSETLNi32, + ARM_INS_FMDHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELEQD, ARM_INS_VSELEQ, + {ARM_VSETLNi8, + ARM_INS_VMOV, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELEQH, ARM_INS_VSELEQ, + {ARM_VSHLLi16, + ARM_INS_VSHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELEQS, ARM_INS_VSELEQ, + {ARM_VSHLLi32, + ARM_INS_VSHLL, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELGED, ARM_INS_VSELGE, + {ARM_VSHLLi8, + ARM_INS_VSHLL, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELGEH, ARM_INS_VSELGE, + {ARM_VSHLLsv2i64, + ARM_INS_VSHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELGES, ARM_INS_VSELGE, + {ARM_VSHLLsv4i32, + ARM_INS_VSHLL, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELGTD, ARM_INS_VSELGT, + {ARM_VSHLLsv8i16, + ARM_INS_VSHLL, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELGTH, ARM_INS_VSELGT, + {ARM_VSHLLuv2i64, + ARM_INS_VSHLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELGTS, ARM_INS_VSELGT, + {ARM_VSHLLuv4i32, + ARM_INS_VSHLL, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELVSD, ARM_INS_VSELVS, + {ARM_VSHLLuv8i16, + ARM_INS_VSHLL, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELVSH, ARM_INS_VSELVS, + {ARM_VSHLiv16i8, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSELVSS, ARM_INS_VSELVS, + {ARM_VSHLiv1i64, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSETLNi16, ARM_INS_VMOV, + {ARM_VSHLiv2i32, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSETLNi32, ARM_INS_FMDHR, + {ARM_VSHLiv2i64, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSETLNi8, ARM_INS_VMOV, + {ARM_VSHLiv4i16, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLLi16, ARM_INS_VSHLL, + {ARM_VSHLiv4i32, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLLi32, ARM_INS_VSHLL, + {ARM_VSHLiv8i16, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLLi8, ARM_INS_VSHLL, + {ARM_VSHLiv8i8, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLLsv2i64, ARM_INS_VSHLL, + {ARM_VSHLsv16i8, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLLsv4i32, ARM_INS_VSHLL, + {ARM_VSHLsv1i64, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLLsv8i16, ARM_INS_VSHLL, + {ARM_VSHLsv2i32, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLLuv2i64, ARM_INS_VSHLL, + {ARM_VSHLsv2i64, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLLuv4i32, ARM_INS_VSHLL, + {ARM_VSHLsv4i16, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLLuv8i16, ARM_INS_VSHLL, + {ARM_VSHLsv4i32, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLiv16i8, ARM_INS_VSHL, + {ARM_VSHLsv8i16, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLiv1i64, ARM_INS_VSHL, + {ARM_VSHLsv8i8, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLiv2i32, ARM_INS_VSHL, + {ARM_VSHLuv16i8, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLiv2i64, ARM_INS_VSHL, + {ARM_VSHLuv1i64, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLiv4i16, ARM_INS_VSHL, + {ARM_VSHLuv2i32, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLiv4i32, ARM_INS_VSHL, + {ARM_VSHLuv2i64, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLiv8i16, ARM_INS_VSHL, + {ARM_VSHLuv4i16, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLiv8i8, ARM_INS_VSHL, + {ARM_VSHLuv4i32, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLsv16i8, ARM_INS_VSHL, + {ARM_VSHLuv8i16, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLsv1i64, ARM_INS_VSHL, + {ARM_VSHLuv8i8, + ARM_INS_VSHL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLsv2i32, ARM_INS_VSHL, + {ARM_VSHRNv2i32, + ARM_INS_VSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLsv2i64, ARM_INS_VSHL, + {ARM_VSHRNv4i16, + ARM_INS_VSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLsv4i16, ARM_INS_VSHL, + {ARM_VSHRNv8i8, + ARM_INS_VSHRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLsv4i32, ARM_INS_VSHL, + {ARM_VSHRsv16i8, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLsv8i16, ARM_INS_VSHL, + {ARM_VSHRsv1i64, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLsv8i8, ARM_INS_VSHL, + {ARM_VSHRsv2i32, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLuv16i8, ARM_INS_VSHL, + {ARM_VSHRsv2i64, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLuv1i64, ARM_INS_VSHL, + {ARM_VSHRsv4i16, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLuv2i32, ARM_INS_VSHL, + {ARM_VSHRsv4i32, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLuv2i64, ARM_INS_VSHL, + {ARM_VSHRsv8i16, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLuv4i16, ARM_INS_VSHL, + {ARM_VSHRsv8i8, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLuv4i32, ARM_INS_VSHL, + {ARM_VSHRuv16i8, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLuv8i16, ARM_INS_VSHL, + {ARM_VSHRuv1i64, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHLuv8i8, ARM_INS_VSHL, + {ARM_VSHRuv2i32, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRNv2i32, ARM_INS_VSHRN, + {ARM_VSHRuv2i64, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRNv4i16, ARM_INS_VSHRN, + {ARM_VSHRuv4i16, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRNv8i8, ARM_INS_VSHRN, + {ARM_VSHRuv4i32, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRsv16i8, ARM_INS_VSHR, + {ARM_VSHRuv8i16, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRsv1i64, ARM_INS_VSHR, + {ARM_VSHRuv8i8, + ARM_INS_VSHR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRsv2i32, ARM_INS_VSHR, + {ARM_VSHTOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSHRsv2i64, ARM_INS_VSHR, + {ARM_VSHTOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VSHRsv4i16, ARM_INS_VSHR, + {ARM_VSHTOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSHRsv4i32, ARM_INS_VSHR, + {ARM_VSITOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSHRsv8i16, ARM_INS_VSHR, + {ARM_VSITOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VSHRsv8i8, ARM_INS_VSHR, + {ARM_VSITOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSHRuv16i8, ARM_INS_VSHR, + {ARM_VSLIv16i8, + ARM_INS_VSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRuv1i64, ARM_INS_VSHR, + {ARM_VSLIv1i64, + ARM_INS_VSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRuv2i32, ARM_INS_VSHR, + {ARM_VSLIv2i32, + ARM_INS_VSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRuv2i64, ARM_INS_VSHR, + {ARM_VSLIv2i64, + ARM_INS_VSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRuv4i16, ARM_INS_VSHR, + {ARM_VSLIv4i16, + ARM_INS_VSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRuv4i32, ARM_INS_VSHR, + {ARM_VSLIv4i32, + ARM_INS_VSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRuv8i16, ARM_INS_VSHR, + {ARM_VSLIv8i16, + ARM_INS_VSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHRuv8i8, ARM_INS_VSHR, + {ARM_VSLIv8i8, + ARM_INS_VSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSHTOD, ARM_INS_VCVT, + {ARM_VSLTOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSHTOH, ARM_INS_VCVT, + {ARM_VSLTOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VSHTOS, ARM_INS_VCVT, + {ARM_VSLTOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSITOD, ARM_INS_VCVT, + {ARM_VSQRTD, ARM_INS_VSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSITOH, ARM_INS_VCVT, + {ARM_VSQRTH, ARM_INS_VSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VSITOS, ARM_INS_VCVT, + {ARM_VSQRTS, ARM_INS_VSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSLIv16i8, ARM_INS_VSLI, + {ARM_VSRAsv16i8, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLIv1i64, ARM_INS_VSLI, + {ARM_VSRAsv1i64, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLIv2i32, ARM_INS_VSLI, + {ARM_VSRAsv2i32, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLIv2i64, ARM_INS_VSLI, + {ARM_VSRAsv2i64, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLIv4i16, ARM_INS_VSLI, + {ARM_VSRAsv4i16, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLIv4i32, ARM_INS_VSLI, + {ARM_VSRAsv4i32, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLIv8i16, ARM_INS_VSLI, + {ARM_VSRAsv8i16, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLIv8i8, ARM_INS_VSLI, + {ARM_VSRAsv8i8, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLTOD, ARM_INS_VCVT, + {ARM_VSRAuv16i8, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLTOH, ARM_INS_VCVT, + {ARM_VSRAuv1i64, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSLTOS, ARM_INS_VCVT, + {ARM_VSRAuv2i32, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSQRTD, ARM_INS_VSQRT, + {ARM_VSRAuv2i64, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSQRTH, ARM_INS_VSQRT, + {ARM_VSRAuv4i16, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSQRTS, ARM_INS_VSQRT, + {ARM_VSRAuv4i32, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAsv16i8, ARM_INS_VSRA, + {ARM_VSRAuv8i16, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAsv1i64, ARM_INS_VSRA, + {ARM_VSRAuv8i8, + ARM_INS_VSRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAsv2i32, ARM_INS_VSRA, + {ARM_VSRIv16i8, + ARM_INS_VSRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAsv2i64, ARM_INS_VSRA, + {ARM_VSRIv1i64, + ARM_INS_VSRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAsv4i16, ARM_INS_VSRA, + {ARM_VSRIv2i32, + ARM_INS_VSRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAsv4i32, ARM_INS_VSRA, + {ARM_VSRIv2i64, + ARM_INS_VSRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAsv8i16, ARM_INS_VSRA, + {ARM_VSRIv4i16, + ARM_INS_VSRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAsv8i8, ARM_INS_VSRA, + {ARM_VSRIv4i32, + ARM_INS_VSRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAuv16i8, ARM_INS_VSRA, + {ARM_VSRIv8i16, + ARM_INS_VSRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAuv1i64, ARM_INS_VSRA, + {ARM_VSRIv8i8, + ARM_INS_VSRI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAuv2i32, ARM_INS_VSRA, + {ARM_VST1LNd16, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAuv2i64, ARM_INS_VSRA, + {ARM_VST1LNd16_UPD, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAuv4i16, ARM_INS_VSRA, + {ARM_VST1LNd32, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAuv4i32, ARM_INS_VSRA, + {ARM_VST1LNd32_UPD, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAuv8i16, ARM_INS_VSRA, + {ARM_VST1LNd8, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRAuv8i8, ARM_INS_VSRA, + {ARM_VST1LNd8_UPD, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRIv16i8, ARM_INS_VSRI, + {ARM_VST1d16, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRIv1i64, ARM_INS_VSRI, + {ARM_VST1d16Q, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRIv2i32, ARM_INS_VSRI, + {ARM_VST1d16Qwb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRIv2i64, ARM_INS_VSRI, + {ARM_VST1d16Qwb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRIv4i16, ARM_INS_VSRI, + {ARM_VST1d16T, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRIv4i32, ARM_INS_VSRI, + {ARM_VST1d16Twb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRIv8i16, ARM_INS_VSRI, + {ARM_VST1d16Twb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSRIv8i8, ARM_INS_VSRI, + {ARM_VST1d16wb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNd16, ARM_INS_VST1, + {ARM_VST1d16wb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNd16_UPD, ARM_INS_VST1, + {ARM_VST1d32, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNd32, ARM_INS_VST1, + {ARM_VST1d32Q, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNd32_UPD, ARM_INS_VST1, + {ARM_VST1d32Qwb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNd8, ARM_INS_VST1, + {ARM_VST1d32Qwb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1LNd8_UPD, ARM_INS_VST1, + {ARM_VST1d32T, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d16, ARM_INS_VST1, + {ARM_VST1d32Twb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d16Q, ARM_INS_VST1, + {ARM_VST1d32Twb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d16Qwb_fixed, ARM_INS_VST1, + {ARM_VST1d32wb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d16Qwb_register, ARM_INS_VST1, + {ARM_VST1d32wb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d16T, ARM_INS_VST1, + {ARM_VST1d64, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d16Twb_fixed, ARM_INS_VST1, + {ARM_VST1d64Q, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d16Twb_register, ARM_INS_VST1, + {ARM_VST1d64Qwb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d16wb_fixed, ARM_INS_VST1, + {ARM_VST1d64Qwb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d16wb_register, ARM_INS_VST1, + {ARM_VST1d64T, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d32, ARM_INS_VST1, + {ARM_VST1d64Twb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d32Q, ARM_INS_VST1, + {ARM_VST1d64Twb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d32Qwb_fixed, ARM_INS_VST1, + {ARM_VST1d64wb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d32Qwb_register, ARM_INS_VST1, + {ARM_VST1d64wb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d32T, ARM_INS_VST1, + {ARM_VST1d8, ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST1d32Twb_fixed, ARM_INS_VST1, + {ARM_VST1d8Q, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d32Twb_register, ARM_INS_VST1, + {ARM_VST1d8Qwb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d32wb_fixed, ARM_INS_VST1, + {ARM_VST1d8Qwb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d32wb_register, ARM_INS_VST1, + {ARM_VST1d8T, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d64, ARM_INS_VST1, + {ARM_VST1d8Twb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d64Q, ARM_INS_VST1, + {ARM_VST1d8Twb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d64Qwb_fixed, ARM_INS_VST1, + {ARM_VST1d8wb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d64Qwb_register, ARM_INS_VST1, + {ARM_VST1d8wb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d64T, ARM_INS_VST1, + {ARM_VST1q16, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d64Twb_fixed, ARM_INS_VST1, + {ARM_VST1q16wb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d64Twb_register, ARM_INS_VST1, + {ARM_VST1q16wb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d64wb_fixed, ARM_INS_VST1, + {ARM_VST1q32, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d64wb_register, ARM_INS_VST1, + {ARM_VST1q32wb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d8, ARM_INS_VST1, + {ARM_VST1q32wb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d8Q, ARM_INS_VST1, + {ARM_VST1q64, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d8Qwb_fixed, ARM_INS_VST1, + {ARM_VST1q64wb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d8Qwb_register, ARM_INS_VST1, + {ARM_VST1q64wb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d8T, ARM_INS_VST1, + {ARM_VST1q8, ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST1d8Twb_fixed, ARM_INS_VST1, + {ARM_VST1q8wb_fixed, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d8Twb_register, ARM_INS_VST1, + {ARM_VST1q8wb_register, + ARM_INS_VST1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d8wb_fixed, ARM_INS_VST1, + {ARM_VST2LNd16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1d8wb_register, ARM_INS_VST1, + {ARM_VST2LNd16_UPD, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q16, ARM_INS_VST1, + {ARM_VST2LNd32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q16wb_fixed, ARM_INS_VST1, + {ARM_VST2LNd32_UPD, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q16wb_register, ARM_INS_VST1, + {ARM_VST2LNd8, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q32, ARM_INS_VST1, + {ARM_VST2LNd8_UPD, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q32wb_fixed, ARM_INS_VST1, + {ARM_VST2LNq16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q32wb_register, ARM_INS_VST1, + {ARM_VST2LNq16_UPD, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q64, ARM_INS_VST1, + {ARM_VST2LNq32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q64wb_fixed, ARM_INS_VST1, + {ARM_VST2LNq32_UPD, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q64wb_register, ARM_INS_VST1, + {ARM_VST2b16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q8, ARM_INS_VST1, + {ARM_VST2b16wb_fixed, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q8wb_fixed, ARM_INS_VST1, + {ARM_VST2b16wb_register, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST1q8wb_register, ARM_INS_VST1, + {ARM_VST2b32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNd16, ARM_INS_VST2, + {ARM_VST2b32wb_fixed, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNd16_UPD, ARM_INS_VST2, + {ARM_VST2b32wb_register, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNd32, ARM_INS_VST2, + {ARM_VST2b8, ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST2LNd32_UPD, ARM_INS_VST2, + {ARM_VST2b8wb_fixed, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNd8, ARM_INS_VST2, + {ARM_VST2b8wb_register, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNd8_UPD, ARM_INS_VST2, + {ARM_VST2d16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNq16, ARM_INS_VST2, + {ARM_VST2d16wb_fixed, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNq16_UPD, ARM_INS_VST2, + {ARM_VST2d16wb_register, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNq32, ARM_INS_VST2, + {ARM_VST2d32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2LNq32_UPD, ARM_INS_VST2, + {ARM_VST2d32wb_fixed, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2b16, ARM_INS_VST2, + {ARM_VST2d32wb_register, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2b16wb_fixed, ARM_INS_VST2, + {ARM_VST2d8, ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST2b16wb_register, ARM_INS_VST2, + {ARM_VST2d8wb_fixed, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2b32, ARM_INS_VST2, + {ARM_VST2d8wb_register, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2b32wb_fixed, ARM_INS_VST2, + {ARM_VST2q16, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2b32wb_register, ARM_INS_VST2, + {ARM_VST2q16wb_fixed, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2b8, ARM_INS_VST2, + {ARM_VST2q16wb_register, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2b8wb_fixed, ARM_INS_VST2, + {ARM_VST2q32, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2b8wb_register, ARM_INS_VST2, + {ARM_VST2q32wb_fixed, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2d16, ARM_INS_VST2, + {ARM_VST2q32wb_register, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2d16wb_fixed, ARM_INS_VST2, + {ARM_VST2q8, ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST2d16wb_register, ARM_INS_VST2, + {ARM_VST2q8wb_fixed, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2d32, ARM_INS_VST2, + {ARM_VST2q8wb_register, + ARM_INS_VST2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2d32wb_fixed, ARM_INS_VST2, + {ARM_VST3LNd16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2d32wb_register, ARM_INS_VST2, + {ARM_VST3LNd16_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2d8, ARM_INS_VST2, + {ARM_VST3LNd32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2d8wb_fixed, ARM_INS_VST2, + {ARM_VST3LNd32_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2d8wb_register, ARM_INS_VST2, + {ARM_VST3LNd8, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2q16, ARM_INS_VST2, + {ARM_VST3LNd8_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2q16wb_fixed, ARM_INS_VST2, + {ARM_VST3LNq16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2q16wb_register, ARM_INS_VST2, + {ARM_VST3LNq16_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2q32, ARM_INS_VST2, + {ARM_VST3LNq32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2q32wb_fixed, ARM_INS_VST2, + {ARM_VST3LNq32_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2q32wb_register, ARM_INS_VST2, + {ARM_VST3d16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2q8, ARM_INS_VST2, + {ARM_VST3d16_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2q8wb_fixed, ARM_INS_VST2, + {ARM_VST3d32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST2q8wb_register, ARM_INS_VST2, + {ARM_VST3d32_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNd16, ARM_INS_VST3, + {ARM_VST3d8, ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST3LNd16_UPD, ARM_INS_VST3, + {ARM_VST3d8_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNd32, ARM_INS_VST3, + {ARM_VST3q16, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNd32_UPD, ARM_INS_VST3, + {ARM_VST3q16_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNd8, ARM_INS_VST3, + {ARM_VST3q32, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNd8_UPD, ARM_INS_VST3, + {ARM_VST3q32_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNq16, ARM_INS_VST3, + {ARM_VST3q8, ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST3LNq16_UPD, ARM_INS_VST3, + {ARM_VST3q8_UPD, + ARM_INS_VST3, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNq32, ARM_INS_VST3, + {ARM_VST4LNd16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3LNq32_UPD, ARM_INS_VST3, + {ARM_VST4LNd16_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3d16, ARM_INS_VST3, + {ARM_VST4LNd32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3d16_UPD, ARM_INS_VST3, + {ARM_VST4LNd32_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3d32, ARM_INS_VST3, + {ARM_VST4LNd8, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3d32_UPD, ARM_INS_VST3, + {ARM_VST4LNd8_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3d8, ARM_INS_VST3, + {ARM_VST4LNq16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3d8_UPD, ARM_INS_VST3, + {ARM_VST4LNq16_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3q16, ARM_INS_VST3, + {ARM_VST4LNq32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3q16_UPD, ARM_INS_VST3, + {ARM_VST4LNq32_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3q32, ARM_INS_VST3, + {ARM_VST4d16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3q32_UPD, ARM_INS_VST3, + {ARM_VST4d16_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3q8, ARM_INS_VST3, + {ARM_VST4d32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST3q8_UPD, ARM_INS_VST3, + {ARM_VST4d32_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNd16, ARM_INS_VST4, + {ARM_VST4d8, ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST4LNd16_UPD, ARM_INS_VST4, + {ARM_VST4d8_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNd32, ARM_INS_VST4, + {ARM_VST4q16, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNd32_UPD, ARM_INS_VST4, + {ARM_VST4q16_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNd8, ARM_INS_VST4, + {ARM_VST4q32, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNd8_UPD, ARM_INS_VST4, + {ARM_VST4q32_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNq16, ARM_INS_VST4, + {ARM_VST4q8, ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST4LNq16_UPD, ARM_INS_VST4, + {ARM_VST4q8_UPD, + ARM_INS_VST4, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNq32, ARM_INS_VST4, + {ARM_VSTMDDB_UPD, + ARM_INS_VSTMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4LNq32_UPD, ARM_INS_VST4, + {ARM_VSTMDIA, + ARM_INS_VSTMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4d16, ARM_INS_VST4, + {ARM_VSTMDIA_UPD, + ARM_INS_VSTMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4d16_UPD, ARM_INS_VST4, + {ARM_VSTMSDB_UPD, + ARM_INS_VSTMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4d32, ARM_INS_VST4, + {ARM_VSTMSIA, + ARM_INS_VSTMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4d32_UPD, ARM_INS_VST4, + {ARM_VSTMSIA_UPD, + ARM_INS_VSTMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4d8, ARM_INS_VST4, + {ARM_VSTRD, ARM_INS_VSTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST4d8_UPD, ARM_INS_VST4, + {ARM_VSTRH, ARM_INS_VSTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VST4q16, ARM_INS_VST4, + {ARM_VSTRS, ARM_INS_VSTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST4q16_UPD, ARM_INS_VST4, + {ARM_VSUBD, ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VST4q32, ARM_INS_VST4, + {ARM_VSUBH, ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VST4q32_UPD, ARM_INS_VST4, + {ARM_VSUBHNv2i32, + ARM_INS_VSUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4q8, ARM_INS_VST4, + {ARM_VSUBHNv4i16, + ARM_INS_VSUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VST4q8_UPD, ARM_INS_VST4, + {ARM_VSUBHNv8i8, + ARM_INS_VSUBHN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSTMDDB_UPD, ARM_INS_VSTMDB, + {ARM_VSUBLsv2i64, + ARM_INS_VSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSTMDIA, ARM_INS_VSTMIA, + {ARM_VSUBLsv4i32, + ARM_INS_VSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSTMDIA_UPD, ARM_INS_VSTMIA, + {ARM_VSUBLsv8i16, + ARM_INS_VSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSTMSDB_UPD, ARM_INS_VSTMDB, + {ARM_VSUBLuv2i64, + ARM_INS_VSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSTMSIA, ARM_INS_VSTMIA, + {ARM_VSUBLuv4i32, + ARM_INS_VSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSTMSIA_UPD, ARM_INS_VSTMIA, + {ARM_VSUBLuv8i16, + ARM_INS_VSUBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSTRD, ARM_INS_VSTR, + {ARM_VSUBS, ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSTRH, ARM_INS_VSTR, + {ARM_VSUBWsv2i64, + ARM_INS_VSUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSTRS, ARM_INS_VSTR, + {ARM_VSUBWsv4i32, + ARM_INS_VSUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBD, ARM_INS_VSUB, + {ARM_VSUBWsv8i16, + ARM_INS_VSUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBH, ARM_INS_VSUB, + {ARM_VSUBWuv2i64, + ARM_INS_VSUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBHNv2i32, ARM_INS_VSUBHN, + {ARM_VSUBWuv4i32, + ARM_INS_VSUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBHNv4i16, ARM_INS_VSUBHN, + {ARM_VSUBWuv8i16, + ARM_INS_VSUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBHNv8i8, ARM_INS_VSUBHN, + {ARM_VSUBfd, ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBLsv2i64, ARM_INS_VSUBL, + {ARM_VSUBfq, ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBLsv4i32, ARM_INS_VSUBL, + {ARM_VSUBhd, ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBLsv8i16, ARM_INS_VSUBL, + {ARM_VSUBhq, ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBLuv2i64, ARM_INS_VSUBL, + {ARM_VSUBv16i8, + ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBLuv4i32, ARM_INS_VSUBL, + {ARM_VSUBv1i64, + ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBLuv8i16, ARM_INS_VSUBL, + {ARM_VSUBv2i32, + ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBS, ARM_INS_VSUB, + {ARM_VSUBv2i64, + ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBWsv2i64, ARM_INS_VSUBW, + {ARM_VSUBv4i16, + ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBWsv4i32, ARM_INS_VSUBW, + {ARM_VSUBv4i32, + ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBWsv8i16, ARM_INS_VSUBW, + {ARM_VSUBv8i16, + ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBWuv2i64, ARM_INS_VSUBW, + {ARM_VSUBv8i8, + ARM_INS_VSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSUBWuv4i32, ARM_INS_VSUBW, + {ARM_VSWPd, ARM_INS_VSWP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBWuv8i16, ARM_INS_VSUBW, + {ARM_VSWPq, ARM_INS_VSWP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBfd, ARM_INS_VSUB, + {ARM_VTBL1, ARM_INS_VTBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBfq, ARM_INS_VSUB, + {ARM_VTBL2, ARM_INS_VTBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBhd, ARM_INS_VSUB, + {ARM_VTBL3, ARM_INS_VTBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBhq, ARM_INS_VSUB, + {ARM_VTBL4, ARM_INS_VTBL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBv16i8, ARM_INS_VSUB, + {ARM_VTBX1, ARM_INS_VTBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBv1i64, ARM_INS_VSUB, + {ARM_VTBX2, ARM_INS_VTBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBv2i32, ARM_INS_VSUB, + {ARM_VTBX3, ARM_INS_VTBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBv2i64, ARM_INS_VSUB, + {ARM_VTBX4, ARM_INS_VTBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBv4i16, ARM_INS_VSUB, + {ARM_VTOSHD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBv4i32, ARM_INS_VSUB, + {ARM_VTOSHH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBv8i16, ARM_INS_VSUB, + {ARM_VTOSHS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VSUBv8i8, ARM_INS_VSUB, + {ARM_VTOSIRD, + ARM_INS_VCVTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSWPd, ARM_INS_VSWP, + {ARM_VTOSIRH, + ARM_INS_VCVTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VSWPq, ARM_INS_VSWP, + {ARM_VTOSIRS, + ARM_INS_VCVTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTBL1, ARM_INS_VTBL, + {ARM_VTOSIZD, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTBL2, ARM_INS_VTBL, + {ARM_VTOSIZH, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTBL3, ARM_INS_VTBL, + {ARM_VTOSIZS, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTBL4, ARM_INS_VTBL, + {ARM_VTOSLD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTBX1, ARM_INS_VTBX, + {ARM_VTOSLH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VTBX2, ARM_INS_VTBX, + {ARM_VTOSLS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTBX3, ARM_INS_VTBX, + {ARM_VTOUHD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTBX4, ARM_INS_VTBX, + {ARM_VTOUHH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VTOSHD, ARM_INS_VCVT, + {ARM_VTOUHS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTOSHH, ARM_INS_VCVT, + {ARM_VTOUIRD, + ARM_INS_VCVTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOSHS, ARM_INS_VCVT, + {ARM_VTOUIRH, + ARM_INS_VCVTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOSIRD, ARM_INS_VCVTR, + {ARM_VTOUIRS, + ARM_INS_VCVTR, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {ARM_REG_FPSCR, 0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOSIRH, ARM_INS_VCVTR, + {ARM_VTOUIZD, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOSIRS, ARM_INS_VCVTR, + {ARM_VTOUIZH, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOSIZD, ARM_INS_VCVT, + {ARM_VTOUIZS, + ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_VFP2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOSIZH, ARM_INS_VCVT, + {ARM_VTOULD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTOSIZS, ARM_INS_VCVT, + {ARM_VTOULH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VTOSLD, ARM_INS_VCVT, + {ARM_VTOULS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTOSLH, ARM_INS_VCVT, + {ARM_VTRNd16, + ARM_INS_VTRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOSLS, ARM_INS_VCVT, + {ARM_VTRNd32, + ARM_INS_VTRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOUHD, ARM_INS_VCVT, + {ARM_VTRNd8, ARM_INS_VTRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTOUHH, ARM_INS_VCVT, + {ARM_VTRNq16, + ARM_INS_VTRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOUHS, ARM_INS_VCVT, + {ARM_VTRNq32, + ARM_INS_VTRN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOUIRD, ARM_INS_VCVTR, + {ARM_VTRNq8, ARM_INS_VTRN, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTOUIRH, ARM_INS_VCVTR, + {ARM_VTSTv16i8, + ARM_INS_VTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOUIRS, ARM_INS_VCVTR, + {ARM_VTSTv2i32, + ARM_INS_VTST, #ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOUIZD, ARM_INS_VCVT, + {ARM_VTSTv4i16, + ARM_INS_VTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOUIZH, ARM_INS_VCVT, + {ARM_VTSTv4i32, + ARM_INS_VTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOUIZS, ARM_INS_VCVT, + {ARM_VTSTv8i16, + ARM_INS_VTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOULD, ARM_INS_VCVT, + {ARM_VTSTv8i8, + ARM_INS_VTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTOULH, ARM_INS_VCVT, + {ARM_VUDOTD, ARM_INS_VUDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VTOULS, ARM_INS_VCVT, + {ARM_VUDOTDI, + ARM_INS_VUDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTRNd16, ARM_INS_VTRN, + {ARM_VUDOTQ, ARM_INS_VUDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VTRNd32, ARM_INS_VTRN, + {ARM_VUDOTQI, + ARM_INS_VUDOT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_VTRNd8, ARM_INS_VTRN, + {ARM_VUHTOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTRNq16, ARM_INS_VTRN, + {ARM_VUHTOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VTRNq32, ARM_INS_VTRN, + {ARM_VUHTOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTRNq8, ARM_INS_VTRN, + {ARM_VUITOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTSTv16i8, ARM_INS_VTST, + {ARM_VUITOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VTSTv2i32, ARM_INS_VTST, + {ARM_VUITOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTSTv4i16, ARM_INS_VTST, + {ARM_VULTOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, ARM_GRP_DPVFP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTSTv4i32, ARM_INS_VTST, + {ARM_VULTOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_VTSTv8i16, ARM_INS_VTST, + {ARM_VULTOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_VFP2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VTSTv8i8, ARM_INS_VTST, + {ARM_VUZPd16, + ARM_INS_VUZP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUDOTD, ARM_INS_VUDOT, + {ARM_VUZPd8, ARM_INS_VUZP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VUDOTDI, ARM_INS_VUDOT, + {ARM_VUZPq16, + ARM_INS_VUZP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUDOTQ, ARM_INS_VUDOT, + {ARM_VUZPq32, + ARM_INS_VUZP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUDOTQI, ARM_INS_VUDOT, + {ARM_VUZPq8, ARM_INS_VUZP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VUHTOD, ARM_INS_VCVT, + {ARM_VZIPd16, + ARM_INS_VZIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUHTOH, ARM_INS_VCVT, + {ARM_VZIPd8, ARM_INS_VZIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VUHTOS, ARM_INS_VCVT, + {ARM_VZIPq16, + ARM_INS_VZIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUITOD, ARM_INS_VCVT, + {ARM_VZIPq32, + ARM_INS_VZIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_NEON, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUITOH, ARM_INS_VCVT, + {ARM_VZIPq8, ARM_INS_VZIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {ARM_GRP_NEON, 0}, 0, + 0 #endif -}, + }, -{ - ARM_VUITOS, ARM_INS_VCVT, + {ARM_sysLDMDA, + ARM_INS_LDMDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VULTOD, ARM_INS_VCVT, + {ARM_sysLDMDA_UPD, + ARM_INS_LDMDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VULTOH, ARM_INS_VCVT, + {ARM_sysLDMDB, + ARM_INS_LDMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VULTOS, ARM_INS_VCVT, + {ARM_sysLDMDB_UPD, + ARM_INS_LDMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUZPd16, ARM_INS_VUZP, + {ARM_sysLDMIA, + ARM_INS_LDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUZPd8, ARM_INS_VUZP, + {ARM_sysLDMIA_UPD, + ARM_INS_LDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUZPq16, ARM_INS_VUZP, + {ARM_sysLDMIB, + ARM_INS_LDMIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUZPq32, ARM_INS_VUZP, + {ARM_sysLDMIB_UPD, + ARM_INS_LDMIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VUZPq8, ARM_INS_VUZP, + {ARM_sysSTMDA, + ARM_INS_STMDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VZIPd16, ARM_INS_VZIP, + {ARM_sysSTMDA_UPD, + ARM_INS_STMDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VZIPd8, ARM_INS_VZIP, + {ARM_sysSTMDB, + ARM_INS_STMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VZIPq16, ARM_INS_VZIP, + {ARM_sysSTMDB_UPD, + ARM_INS_STMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VZIPq32, ARM_INS_VZIP, + {ARM_sysSTMIA, + ARM_INS_STM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_VZIPq8, ARM_INS_VZIP, + {ARM_sysSTMIA_UPD, + ARM_INS_STM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysLDMDA, ARM_INS_LDMDA, + {ARM_sysSTMIB, + ARM_INS_STMIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysLDMDA_UPD, ARM_INS_LDMDA, + {ARM_sysSTMIB_UPD, + ARM_INS_STMIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_ARM, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysLDMDB, ARM_INS_LDMDB, + {ARM_t2ADCri, + ARM_INS_ADC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysLDMDB_UPD, ARM_INS_LDMDB, + {ARM_t2ADCrr, + ARM_INS_ADC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysLDMIA, ARM_INS_LDM, + {ARM_t2ADCrs, + ARM_INS_ADC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysLDMIA_UPD, ARM_INS_LDM, + {ARM_t2ADDri, + ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysLDMIB, ARM_INS_LDMIB, + {ARM_t2ADDri12, + ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysLDMIB_UPD, ARM_INS_LDMIB, + {ARM_t2ADDrr, + ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysSTMDA, ARM_INS_STMDA, + {ARM_t2ADDrs, + ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysSTMDA_UPD, ARM_INS_STMDA, + {ARM_t2ADR, ARM_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_sysSTMDB, ARM_INS_STMDB, + {ARM_t2ANDri, + ARM_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysSTMDB_UPD, ARM_INS_STMDB, + {ARM_t2ANDrr, + ARM_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysSTMIA, ARM_INS_STM, + {ARM_t2ANDrs, + ARM_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysSTMIA_UPD, ARM_INS_STM, + {ARM_t2ASRri, + ARM_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysSTMIB, ARM_INS_STMIB, + {ARM_t2ASRrr, + ARM_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_sysSTMIB_UPD, ARM_INS_STMIB, + {ARM_t2B, ARM_INS_B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0}, + 1, 0 #endif -}, + }, -{ - ARM_t2ADCri, ARM_INS_ADC, + {ARM_t2BFC, ARM_INS_BFC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2ADCrr, ARM_INS_ADC, + {ARM_t2BFI, ARM_INS_BFI, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2ADCrs, ARM_INS_ADC, + {ARM_t2BICri, + ARM_INS_BIC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ADDri, ARM_INS_ADD, + {ARM_t2BICrr, + ARM_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ADDri12, ARM_INS_ADD, + {ARM_t2BICrs, + ARM_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ADDrr, ARM_INS_ADD, + {ARM_t2BXJ, + ARM_INS_BXJ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, ARM_GRP_PREV8, 0}, + 0, + 1 #endif -}, + }, -{ - ARM_t2ADDrs, ARM_INS_ADD, + {ARM_t2Bcc, ARM_INS_B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0}, + 1, 0 #endif -}, + }, -{ - ARM_t2ADR, ARM_INS_ADR, + {ARM_t2CDP, + ARM_INS_CDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ANDri, ARM_INS_AND, + {ARM_t2CDP2, + ARM_INS_CDP2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ANDrr, ARM_INS_AND, + {ARM_t2CLREX, + ARM_INS_CLREX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V7, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ANDrs, ARM_INS_AND, + {ARM_t2CLZ, ARM_INS_CLZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2ASRri, ARM_INS_ASR, + {ARM_t2CMNri, + ARM_INS_CMN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ASRrr, ARM_INS_ASR, + {ARM_t2CMNzrr, + ARM_INS_CMN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2B, ARM_INS_B, + {ARM_t2CMNzrs, + ARM_INS_CMN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2BFC, ARM_INS_BFC, + {ARM_t2CMPri, + ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2BFI, ARM_INS_BFI, + {ARM_t2CMPrr, + ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2BICri, ARM_INS_BIC, + {ARM_t2CMPrs, + ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2BICrr, ARM_INS_BIC, + {ARM_t2CPS1p, + ARM_INS_CPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2BICrs, ARM_INS_BIC, + {ARM_t2CPS2p, + ARM_INS_CPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2BXJ, ARM_INS_BXJ, + {ARM_t2CPS3p, + ARM_INS_CPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, ARM_GRP_PREV8, 0 }, 0, 1 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2Bcc, ARM_INS_B, + {ARM_t2CRC32B, + ARM_INS_CRC32B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CDP, ARM_INS_CDP, + {ARM_t2CRC32CB, + ARM_INS_CRC32CB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CDP2, ARM_INS_CDP2, + {ARM_t2CRC32CH, + ARM_INS_CRC32CH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CLREX, ARM_INS_CLREX, + {ARM_t2CRC32CW, + ARM_INS_CRC32CW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CLZ, ARM_INS_CLZ, + {ARM_t2CRC32H, + ARM_INS_CRC32H, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CMNri, ARM_INS_CMN, + {ARM_t2CRC32W, + ARM_INS_CRC32W, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CMNzrr, ARM_INS_CMN, + {ARM_t2DBG, ARM_INS_DBG, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2CMNzrs, ARM_INS_CMN, + {ARM_t2DCPS1, + ARM_INS_DCPS1, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CMPri, ARM_INS_CMP, + {ARM_t2DCPS2, + ARM_INS_DCPS2, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CMPrr, ARM_INS_CMP, + {ARM_t2DCPS3, + ARM_INS_DCPS3, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CMPrs, ARM_INS_CMP, + {ARM_t2DMB, ARM_INS_DMB, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2CPS1p, ARM_INS_CPS, + {ARM_t2DSB, ARM_INS_DSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2CPS2p, ARM_INS_CPS, + {ARM_t2EORri, + ARM_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CPS3p, ARM_INS_CPS, + {ARM_t2EORrr, + ARM_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CRC32B, ARM_INS_CRC32B, + {ARM_t2EORrs, + ARM_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2CRC32CB, ARM_INS_CRC32CB, + {ARM_t2HINT, ARM_INS_HINT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2CRC32CH, ARM_INS_CRC32CH, + {ARM_t2HVC, ARM_INS_HVC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_VIRTUALIZATION, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2CRC32CW, ARM_INS_CRC32CW, + {ARM_t2ISB, ARM_INS_ISB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2CRC32H, ARM_INS_CRC32H, + {ARM_t2IT, ARM_INS_IT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, {ARM_REG_ITSTATE, 0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2CRC32W, ARM_INS_CRC32W, + {ARM_t2LDA, ARM_INS_LDA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2DBG, ARM_INS_DBG, + {ARM_t2LDAB, ARM_INS_LDAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2DCPS1, ARM_INS_DCPS1, + {ARM_t2LDAEX, + ARM_INS_LDAEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2DCPS2, ARM_INS_DCPS2, + {ARM_t2LDAEXB, + ARM_INS_LDAEXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2DCPS3, ARM_INS_DCPS3, + {ARM_t2LDAEXD, + ARM_INS_LDAEXD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2DMB, ARM_INS_DMB, + {ARM_t2LDAEXH, + ARM_INS_LDAEXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2DSB, ARM_INS_DSB, + {ARM_t2LDAH, ARM_INS_LDAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2EORri, ARM_INS_EOR, + {ARM_t2LDC2L_OFFSET, + ARM_INS_LDC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2EORrr, ARM_INS_EOR, + {ARM_t2LDC2L_OPTION, + ARM_INS_LDC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2EORrs, ARM_INS_EOR, + {ARM_t2LDC2L_POST, + ARM_INS_LDC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2HINT, ARM_INS_HINT, + {ARM_t2LDC2L_PRE, + ARM_INS_LDC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2HVC, ARM_INS_HVC, + {ARM_t2LDC2_OFFSET, + ARM_INS_LDC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ISB, ARM_INS_ISB, + {ARM_t2LDC2_OPTION, + ARM_INS_LDC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2IT, ARM_INS_IT, + {ARM_t2LDC2_POST, + ARM_INS_LDC2, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_ITSTATE, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDA, ARM_INS_LDA, + {ARM_t2LDC2_PRE, + ARM_INS_LDC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDAB, ARM_INS_LDAB, + {ARM_t2LDCL_OFFSET, + ARM_INS_LDCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDAEX, ARM_INS_LDAEX, + {ARM_t2LDCL_OPTION, + ARM_INS_LDCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDAEXB, ARM_INS_LDAEXB, + {ARM_t2LDCL_POST, + ARM_INS_LDCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDAEXD, ARM_INS_LDAEXD, + {ARM_t2LDCL_PRE, + ARM_INS_LDCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDAEXH, ARM_INS_LDAEXH, + {ARM_t2LDC_OFFSET, + ARM_INS_LDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDAH, ARM_INS_LDAH, + {ARM_t2LDC_OPTION, + ARM_INS_LDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L, + {ARM_t2LDC_POST, + ARM_INS_LDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC2L_OPTION, ARM_INS_LDC2L, + {ARM_t2LDC_PRE, + ARM_INS_LDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC2L_POST, ARM_INS_LDC2L, + {ARM_t2LDMDB, + ARM_INS_LDMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC2L_PRE, ARM_INS_LDC2L, + {ARM_t2LDMDB_UPD, + ARM_INS_LDMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC2_OFFSET, ARM_INS_LDC2, + {ARM_t2LDMIA, + ARM_INS_LDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC2_OPTION, ARM_INS_LDC2, + {ARM_t2LDMIA_UPD, + ARM_INS_LDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC2_POST, ARM_INS_LDC2, + {ARM_t2LDRBT, + ARM_INS_LDRBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC2_PRE, ARM_INS_LDC2, + {ARM_t2LDRB_POST, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDCL_OFFSET, ARM_INS_LDCL, + {ARM_t2LDRB_PRE, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDCL_OPTION, ARM_INS_LDCL, + {ARM_t2LDRBi12, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDCL_POST, ARM_INS_LDCL, + {ARM_t2LDRBi8, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDCL_PRE, ARM_INS_LDCL, + {ARM_t2LDRBpci, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC_OFFSET, ARM_INS_LDC, + {ARM_t2LDRBs, + ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC_OPTION, ARM_INS_LDC, + {ARM_t2LDRD_POST, + ARM_INS_LDRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC_POST, ARM_INS_LDC, + {ARM_t2LDRD_PRE, + ARM_INS_LDRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDC_PRE, ARM_INS_LDC, + {ARM_t2LDRDi8, + ARM_INS_LDRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDMDB, ARM_INS_LDMDB, + {ARM_t2LDREX, + ARM_INS_LDREX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDMDB_UPD, ARM_INS_LDMDB, + {ARM_t2LDREXB, + ARM_INS_LDREXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDMIA, ARM_INS_LDM, + {ARM_t2LDREXD, + ARM_INS_LDREXD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDMIA_UPD, ARM_INS_LDM, + {ARM_t2LDREXH, + ARM_INS_LDREXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRBT, ARM_INS_LDRBT, + {ARM_t2LDRHT, + ARM_INS_LDRHT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRB_POST, ARM_INS_LDRB, + {ARM_t2LDRH_POST, + ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRB_PRE, ARM_INS_LDRB, + {ARM_t2LDRH_PRE, + ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRBi12, ARM_INS_LDRB, + {ARM_t2LDRHi12, + ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRBi8, ARM_INS_LDRB, + {ARM_t2LDRHi8, + ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRBpci, ARM_INS_LDRB, + {ARM_t2LDRHpci, + ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRBs, ARM_INS_LDRB, + {ARM_t2LDRHs, + ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRD_POST, ARM_INS_LDRD, + {ARM_t2LDRSBT, + ARM_INS_LDRSBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRD_PRE, ARM_INS_LDRD, + {ARM_t2LDRSB_POST, + ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRDi8, ARM_INS_LDRD, + {ARM_t2LDRSB_PRE, + ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDREX, ARM_INS_LDREX, + {ARM_t2LDRSBi12, + ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDREXB, ARM_INS_LDREXB, + {ARM_t2LDRSBi8, + ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDREXD, ARM_INS_LDREXD, + {ARM_t2LDRSBpci, + ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDREXH, ARM_INS_LDREXH, + {ARM_t2LDRSBs, + ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRHT, ARM_INS_LDRHT, + {ARM_t2LDRSHT, + ARM_INS_LDRSHT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRH_POST, ARM_INS_LDRH, + {ARM_t2LDRSH_POST, + ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRH_PRE, ARM_INS_LDRH, + {ARM_t2LDRSH_PRE, + ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRHi12, ARM_INS_LDRH, + {ARM_t2LDRSHi12, + ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRHi8, ARM_INS_LDRH, + {ARM_t2LDRSHi8, + ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRHpci, ARM_INS_LDRH, + {ARM_t2LDRSHpci, + ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRHs, ARM_INS_LDRH, + {ARM_t2LDRSHs, + ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSBT, ARM_INS_LDRSBT, + {ARM_t2LDRT, ARM_INS_LDRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSB_POST, ARM_INS_LDRSB, + {ARM_t2LDR_POST, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSB_PRE, ARM_INS_LDRSB, + {ARM_t2LDR_PRE, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSBi12, ARM_INS_LDRSB, + {ARM_t2LDRi12, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSBi8, ARM_INS_LDRSB, + {ARM_t2LDRi8, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSBpci, ARM_INS_LDRSB, + {ARM_t2LDRpci, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSBs, ARM_INS_LDRSB, + {ARM_t2LDRs, ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSHT, ARM_INS_LDRSHT, + {ARM_t2LSLri, + ARM_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSH_POST, ARM_INS_LDRSH, + {ARM_t2LSLrr, + ARM_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, - -{ - ARM_t2LDRSH_PRE, ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, + }, -{ - ARM_t2LDRSHi12, ARM_INS_LDRSH, + {ARM_t2LSRri, + ARM_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSHi8, ARM_INS_LDRSH, + {ARM_t2LSRrr, + ARM_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSHpci, ARM_INS_LDRSH, + {ARM_t2MCR, ARM_INS_MCR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2LDRSHs, ARM_INS_LDRSH, + {ARM_t2MCR2, + ARM_INS_MCR2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRT, ARM_INS_LDRT, + {ARM_t2MCRR, ARM_INS_MCRR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2LDR_POST, ARM_INS_LDR, + {ARM_t2MCRR2, + ARM_INS_MCRR2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDR_PRE, ARM_INS_LDR, + {ARM_t2MLA, ARM_INS_MLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2LDRi12, ARM_INS_LDR, + {ARM_t2MLS, ARM_INS_MLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2LDRi8, ARM_INS_LDR, + {ARM_t2MOVTi16, + ARM_INS_MOVT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LDRpci, ARM_INS_LDR, + {ARM_t2MOVi, ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2LDRs, ARM_INS_LDR, + {ARM_t2MOVi16, + ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LSLri, ARM_INS_LSL, + {ARM_t2MOVr, ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2LSLrr, ARM_INS_LSL, + {ARM_t2MOVsra_flag, + ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2LSRri, ARM_INS_LSR, + {ARM_t2MOVsrl_flag, + ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, - -{ - ARM_t2LSRrr, ARM_INS_LSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MCR, ARM_INS_MCR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MCR2, ARM_INS_MCR2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MCRR, ARM_INS_MCRR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MCRR2, ARM_INS_MCRR2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MLA, ARM_INS_MLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MLS, ARM_INS_MLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MOVTi16, ARM_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MOVi, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MOVi16, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MOVr, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MOVsra_flag, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, - -{ - ARM_t2MOVsrl_flag, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif -}, + }, -{ - ARM_t2MRC, ARM_INS_MRC, + {ARM_t2MRC, ARM_INS_MRC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2MRC2, ARM_INS_MRC2, + {ARM_t2MRC2, + ARM_INS_MRC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MRRC, ARM_INS_MRRC, + {ARM_t2MRRC, ARM_INS_MRRC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2MRRC2, ARM_INS_MRRC2, + {ARM_t2MRRC2, + ARM_INS_MRRC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_PREV8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MRS_AR, ARM_INS_MRS, + {ARM_t2MRS_AR, + ARM_INS_MRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MRS_M, ARM_INS_MRS, + {ARM_t2MRS_M, + ARM_INS_MRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_MCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MRSbanked, ARM_INS_MRS, + {ARM_t2MRSbanked, + ARM_INS_MRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MRSsys_AR, ARM_INS_MRS, + {ARM_t2MRSsys_AR, + ARM_INS_MRS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MSR_AR, ARM_INS_MSR, + {ARM_t2MSR_AR, + ARM_INS_MSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MSR_M, ARM_INS_MSR, + {ARM_t2MSR_M, + ARM_INS_MSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_MCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MSRbanked, ARM_INS_MSR, + {ARM_t2MSRbanked, + ARM_INS_MSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2MUL, ARM_INS_MUL, + {ARM_t2MUL, ARM_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2MVNi, ARM_INS_MVN, + {ARM_t2MVNi, ARM_INS_MVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2MVNr, ARM_INS_MVN, + {ARM_t2MVNr, ARM_INS_MVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2MVNs, ARM_INS_MVN, + {ARM_t2MVNs, ARM_INS_MVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2ORNri, ARM_INS_ORN, + {ARM_t2ORNri, + ARM_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ORNrr, ARM_INS_ORN, + {ARM_t2ORNrr, + ARM_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ORNrs, ARM_INS_ORN, + {ARM_t2ORNrs, + ARM_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ORRri, ARM_INS_ORR, + {ARM_t2ORRri, + ARM_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ORRrr, ARM_INS_ORR, + {ARM_t2ORRrr, + ARM_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2ORRrs, ARM_INS_ORR, + {ARM_t2ORRrs, + ARM_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PKHBT, ARM_INS_PKHBT, + {ARM_t2PKHBT, + ARM_INS_PKHBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PKHTB, ARM_INS_PKHTB, + {ARM_t2PKHTB, + ARM_INS_PKHTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLDWi12, ARM_INS_PLDW, + {ARM_t2PLDWi12, + ARM_INS_PLDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLDWi8, ARM_INS_PLDW, + {ARM_t2PLDWi8, + ARM_INS_PLDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLDWs, ARM_INS_PLDW, + {ARM_t2PLDWs, + ARM_INS_PLDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLDi12, ARM_INS_PLD, + {ARM_t2PLDi12, + ARM_INS_PLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLDi8, ARM_INS_PLD, + {ARM_t2PLDi8, + ARM_INS_PLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLDpci, ARM_INS_PLD, + {ARM_t2PLDpci, + ARM_INS_PLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLDs, ARM_INS_PLD, + {ARM_t2PLDs, ARM_INS_PLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2PLIi12, ARM_INS_PLI, + {ARM_t2PLIi12, + ARM_INS_PLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V7, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLIi8, ARM_INS_PLI, + {ARM_t2PLIi8, + ARM_INS_PLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V7, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLIpci, ARM_INS_PLI, + {ARM_t2PLIpci, + ARM_INS_PLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_V7, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2PLIs, ARM_INS_PLI, + {ARM_t2PLIs, ARM_INS_PLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_V7, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2QADD, ARM_INS_QADD, + {ARM_t2QADD, ARM_INS_QADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2QADD16, ARM_INS_QADD16, + {ARM_t2QADD16, + ARM_INS_QADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2QADD8, ARM_INS_QADD8, + {ARM_t2QADD8, + ARM_INS_QADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2QASX, ARM_INS_QASX, + {ARM_t2QASX, ARM_INS_QASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2QDADD, ARM_INS_QDADD, + {ARM_t2QDADD, + ARM_INS_QDADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2QDSUB, ARM_INS_QDSUB, + {ARM_t2QDSUB, + ARM_INS_QDSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2QSAX, ARM_INS_QSAX, + {ARM_t2QSAX, ARM_INS_QSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2QSUB, ARM_INS_QSUB, + {ARM_t2QSUB, ARM_INS_QSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2QSUB16, ARM_INS_QSUB16, + {ARM_t2QSUB16, + ARM_INS_QSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2QSUB8, ARM_INS_QSUB8, + {ARM_t2QSUB8, + ARM_INS_QSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RBIT, ARM_INS_RBIT, + {ARM_t2RBIT, ARM_INS_RBIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2REV, ARM_INS_REV, + {ARM_t2REV, ARM_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2REV16, ARM_INS_REV16, + {ARM_t2REV16, + ARM_INS_REV16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2REVSH, ARM_INS_REVSH, + {ARM_t2REVSH, + ARM_INS_REVSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RFEDB, ARM_INS_RFEDB, + {ARM_t2RFEDB, + ARM_INS_RFEDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RFEDBW, ARM_INS_RFEDB, + {ARM_t2RFEDBW, + ARM_INS_RFEDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RFEIA, ARM_INS_RFEIA, + {ARM_t2RFEIA, + ARM_INS_RFEIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RFEIAW, ARM_INS_RFEIA, + {ARM_t2RFEIAW, + ARM_INS_RFEIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RORri, ARM_INS_ROR, + {ARM_t2RORri, + ARM_INS_ROR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RORrr, ARM_INS_ROR, + {ARM_t2RORrr, + ARM_INS_ROR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RRX, ARM_INS_RRX, + {ARM_t2RRX, + ARM_INS_RRX, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RSBri, ARM_INS_RSB, + {ARM_t2RSBri, + ARM_INS_RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RSBrr, ARM_INS_RSB, + {ARM_t2RSBrr, + ARM_INS_RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2RSBrs, ARM_INS_RSB, + {ARM_t2RSBrs, + ARM_INS_RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SADD16, ARM_INS_SADD16, + {ARM_t2SADD16, + ARM_INS_SADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SADD8, ARM_INS_SADD8, + {ARM_t2SADD8, + ARM_INS_SADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SASX, ARM_INS_SASX, + {ARM_t2SASX, ARM_INS_SASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2SBCri, ARM_INS_SBC, + {ARM_t2SBCri, + ARM_INS_SBC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SBCrr, ARM_INS_SBC, + {ARM_t2SBCrr, + ARM_INS_SBC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SBCrs, ARM_INS_SBC, + {ARM_t2SBCrs, + ARM_INS_SBC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SBFX, ARM_INS_SBFX, + {ARM_t2SBFX, ARM_INS_SBFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2SDIV, ARM_INS_SDIV, + {ARM_t2SDIV, ARM_INS_SDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2SEL, ARM_INS_SEL, + {ARM_t2SEL, ARM_INS_SEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2SETPAN, ARM_INS_SETPAN, + {ARM_t2SETPAN, + ARM_INS_SETPAN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SG, ARM_INS_SG, + {ARM_t2SG, ARM_INS_SG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - ARM_t2SHADD16, ARM_INS_SHADD16, + {ARM_t2SHADD16, + ARM_INS_SHADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SHADD8, ARM_INS_SHADD8, + {ARM_t2SHADD8, + ARM_INS_SHADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SHASX, ARM_INS_SHASX, + {ARM_t2SHASX, + ARM_INS_SHASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SHSAX, ARM_INS_SHSAX, + {ARM_t2SHSAX, + ARM_INS_SHSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SHSUB16, ARM_INS_SHSUB16, + {ARM_t2SHSUB16, + ARM_INS_SHSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SHSUB8, ARM_INS_SHSUB8, + {ARM_t2SHSUB8, + ARM_INS_SHSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMC, ARM_INS_SMC, + {ARM_t2SMC, + ARM_INS_SMC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLABB, ARM_INS_SMLABB, + {ARM_t2SMLABB, + ARM_INS_SMLABB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLABT, ARM_INS_SMLABT, + {ARM_t2SMLABT, + ARM_INS_SMLABT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLAD, ARM_INS_SMLAD, + {ARM_t2SMLAD, + ARM_INS_SMLAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLADX, ARM_INS_SMLADX, + {ARM_t2SMLADX, + ARM_INS_SMLADX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLAL, ARM_INS_SMLAL, + {ARM_t2SMLAL, + ARM_INS_SMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLALBB, ARM_INS_SMLALBB, + {ARM_t2SMLALBB, + ARM_INS_SMLALBB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLALBT, ARM_INS_SMLALBT, + {ARM_t2SMLALBT, + ARM_INS_SMLALBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLALD, ARM_INS_SMLALD, + {ARM_t2SMLALD, + ARM_INS_SMLALD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLALDX, ARM_INS_SMLALDX, + {ARM_t2SMLALDX, + ARM_INS_SMLALDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLALTB, ARM_INS_SMLALTB, + {ARM_t2SMLALTB, + ARM_INS_SMLALTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLALTT, ARM_INS_SMLALTT, + {ARM_t2SMLALTT, + ARM_INS_SMLALTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLATB, ARM_INS_SMLATB, + {ARM_t2SMLATB, + ARM_INS_SMLATB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLATT, ARM_INS_SMLATT, + {ARM_t2SMLATT, + ARM_INS_SMLATT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLAWB, ARM_INS_SMLAWB, + {ARM_t2SMLAWB, + ARM_INS_SMLAWB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLAWT, ARM_INS_SMLAWT, + {ARM_t2SMLAWT, + ARM_INS_SMLAWT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLSD, ARM_INS_SMLSD, + {ARM_t2SMLSD, + ARM_INS_SMLSD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLSDX, ARM_INS_SMLSDX, + {ARM_t2SMLSDX, + ARM_INS_SMLSDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLSLD, ARM_INS_SMLSLD, + {ARM_t2SMLSLD, + ARM_INS_SMLSLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMLSLDX, ARM_INS_SMLSLDX, + {ARM_t2SMLSLDX, + ARM_INS_SMLSLDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMMLA, ARM_INS_SMMLA, + {ARM_t2SMMLA, + ARM_INS_SMMLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMMLAR, ARM_INS_SMMLAR, + {ARM_t2SMMLAR, + ARM_INS_SMMLAR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMMLS, ARM_INS_SMMLS, + {ARM_t2SMMLS, + ARM_INS_SMMLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMMLSR, ARM_INS_SMMLSR, + {ARM_t2SMMLSR, + ARM_INS_SMMLSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMMUL, ARM_INS_SMMUL, + {ARM_t2SMMUL, + ARM_INS_SMMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMMULR, ARM_INS_SMMULR, + {ARM_t2SMMULR, + ARM_INS_SMMULR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMUAD, ARM_INS_SMUAD, + {ARM_t2SMUAD, + ARM_INS_SMUAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMUADX, ARM_INS_SMUADX, + {ARM_t2SMUADX, + ARM_INS_SMUADX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMULBB, ARM_INS_SMULBB, + {ARM_t2SMULBB, + ARM_INS_SMULBB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMULBT, ARM_INS_SMULBT, + {ARM_t2SMULBT, + ARM_INS_SMULBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMULL, ARM_INS_SMULL, + {ARM_t2SMULL, + ARM_INS_SMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMULTB, ARM_INS_SMULTB, + {ARM_t2SMULTB, + ARM_INS_SMULTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMULTT, ARM_INS_SMULTT, + {ARM_t2SMULTT, + ARM_INS_SMULTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMULWB, ARM_INS_SMULWB, + {ARM_t2SMULWB, + ARM_INS_SMULWB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMULWT, ARM_INS_SMULWT, + {ARM_t2SMULWT, + ARM_INS_SMULWT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMUSD, ARM_INS_SMUSD, + {ARM_t2SMUSD, + ARM_INS_SMUSD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SMUSDX, ARM_INS_SMUSDX, + {ARM_t2SMUSDX, + ARM_INS_SMUSDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SRSDB, ARM_INS_SRSDB, + {ARM_t2SRSDB, + ARM_INS_SRSDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SRSDB_UPD, ARM_INS_SRSDB, + {ARM_t2SRSDB_UPD, + ARM_INS_SRSDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SRSIA, ARM_INS_SRSIA, + {ARM_t2SRSIA, + ARM_INS_SRSIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SRSIA_UPD, ARM_INS_SRSIA, + {ARM_t2SRSIA_UPD, + ARM_INS_SRSIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SSAT, ARM_INS_SSAT, + {ARM_t2SSAT, ARM_INS_SSAT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2SSAT16, ARM_INS_SSAT16, + {ARM_t2SSAT16, + ARM_INS_SSAT16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SSAX, ARM_INS_SSAX, + {ARM_t2SSAX, ARM_INS_SSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2SSUB16, ARM_INS_SSUB16, + {ARM_t2SSUB16, + ARM_INS_SSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SSUB8, ARM_INS_SSUB8, + {ARM_t2SSUB8, + ARM_INS_SSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC2L_OFFSET, ARM_INS_STC2L, + {ARM_t2STC2L_OFFSET, + ARM_INS_STC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC2L_OPTION, ARM_INS_STC2L, + {ARM_t2STC2L_OPTION, + ARM_INS_STC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC2L_POST, ARM_INS_STC2L, + {ARM_t2STC2L_POST, + ARM_INS_STC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC2L_PRE, ARM_INS_STC2L, + {ARM_t2STC2L_PRE, + ARM_INS_STC2L, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC2_OFFSET, ARM_INS_STC2, + {ARM_t2STC2_OFFSET, + ARM_INS_STC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC2_OPTION, ARM_INS_STC2, + {ARM_t2STC2_OPTION, + ARM_INS_STC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC2_POST, ARM_INS_STC2, + {ARM_t2STC2_POST, + ARM_INS_STC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC2_PRE, ARM_INS_STC2, + {ARM_t2STC2_PRE, + ARM_INS_STC2, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_PREV8, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STCL_OFFSET, ARM_INS_STCL, + {ARM_t2STCL_OFFSET, + ARM_INS_STCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STCL_OPTION, ARM_INS_STCL, + {ARM_t2STCL_OPTION, + ARM_INS_STCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STCL_POST, ARM_INS_STCL, + {ARM_t2STCL_POST, + ARM_INS_STCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STCL_PRE, ARM_INS_STCL, + {ARM_t2STCL_PRE, + ARM_INS_STCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC_OFFSET, ARM_INS_STC, + {ARM_t2STC_OFFSET, + ARM_INS_STC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC_OPTION, ARM_INS_STC, + {ARM_t2STC_OPTION, + ARM_INS_STC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC_POST, ARM_INS_STC, + {ARM_t2STC_POST, + ARM_INS_STC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STC_PRE, ARM_INS_STC, + {ARM_t2STC_PRE, + ARM_INS_STC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STL, ARM_INS_STL, + {ARM_t2STL, ARM_INS_STL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2STLB, ARM_INS_STLB, + {ARM_t2STLB, ARM_INS_STLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2STLEX, ARM_INS_STLEX, + {ARM_t2STLEX, + ARM_INS_STLEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STLEXB, ARM_INS_STLEXB, + {ARM_t2STLEXB, + ARM_INS_STLEXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STLEXD, ARM_INS_STLEXD, + {ARM_t2STLEXD, + ARM_INS_STLEXD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STLEXH, ARM_INS_STLEXH, + {ARM_t2STLEXH, + ARM_INS_STLEXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_V8, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STLH, ARM_INS_STLH, + {ARM_t2STLH, ARM_INS_STLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2STMDB, ARM_INS_STMDB, + {ARM_t2STMDB, + ARM_INS_STMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STMDB_UPD, ARM_INS_STMDB, + {ARM_t2STMDB_UPD, + ARM_INS_STMDB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STMIA, ARM_INS_STM, + {ARM_t2STMIA, + ARM_INS_STM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STMIA_UPD, ARM_INS_STM, + {ARM_t2STMIA_UPD, + ARM_INS_STM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRBT, ARM_INS_STRBT, + {ARM_t2STRBT, + ARM_INS_STRBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRB_POST, ARM_INS_STRB, + {ARM_t2STRB_POST, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRB_PRE, ARM_INS_STRB, + {ARM_t2STRB_PRE, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRBi12, ARM_INS_STRB, + {ARM_t2STRBi12, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRBi8, ARM_INS_STRB, + {ARM_t2STRBi8, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRBs, ARM_INS_STRB, + {ARM_t2STRBs, + ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRD_POST, ARM_INS_STRD, + {ARM_t2STRD_POST, + ARM_INS_STRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRD_PRE, ARM_INS_STRD, + {ARM_t2STRD_PRE, + ARM_INS_STRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRDi8, ARM_INS_STRD, + {ARM_t2STRDi8, + ARM_INS_STRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STREX, ARM_INS_STREX, + {ARM_t2STREX, + ARM_INS_STREX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STREXB, ARM_INS_STREXB, + {ARM_t2STREXB, + ARM_INS_STREXB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STREXD, ARM_INS_STREXD, + {ARM_t2STREXD, + ARM_INS_STREXD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STREXH, ARM_INS_STREXH, + {ARM_t2STREXH, + ARM_INS_STREXH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRHT, ARM_INS_STRHT, + {ARM_t2STRHT, + ARM_INS_STRHT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRH_POST, ARM_INS_STRH, + {ARM_t2STRH_POST, + ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRH_PRE, ARM_INS_STRH, + {ARM_t2STRH_PRE, + ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRHi12, ARM_INS_STRH, + {ARM_t2STRHi12, + ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRHi8, ARM_INS_STRH, + {ARM_t2STRHi8, + ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRHs, ARM_INS_STRH, + {ARM_t2STRHs, + ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRT, ARM_INS_STRT, + {ARM_t2STRT, ARM_INS_STRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2STR_POST, ARM_INS_STR, + {ARM_t2STR_POST, + ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STR_PRE, ARM_INS_STR, + {ARM_t2STR_PRE, + ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRi12, ARM_INS_STR, + {ARM_t2STRi12, + ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRi8, ARM_INS_STR, + {ARM_t2STRi8, + ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2STRs, ARM_INS_STR, + {ARM_t2STRs, ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2SUBS_PC_LR, ARM_INS_SUBS, + {ARM_t2SUBS_PC_LR, + ARM_INS_SUBS, #ifndef CAPSTONE_DIET - { ARM_REG_SPSR, ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_REG_CPSR, ARM_REG_PC, 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {ARM_REG_SPSR, ARM_REG_LR, ARM_REG_PC, 0}, + {ARM_REG_CPSR, ARM_REG_PC, 0}, + {ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SUBri, ARM_INS_SUB, + {ARM_t2SUBri, + ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SUBri12, ARM_INS_SUB, + {ARM_t2SUBri12, + ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SUBrr, ARM_INS_SUB, + {ARM_t2SUBrr, + ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SUBrs, ARM_INS_SUB, + {ARM_t2SUBrs, + ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SXTAB, ARM_INS_SXTAB, + {ARM_t2SXTAB, + ARM_INS_SXTAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SXTAB16, ARM_INS_SXTAB16, + {ARM_t2SXTAB16, + ARM_INS_SXTAB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SXTAH, ARM_INS_SXTAH, + {ARM_t2SXTAH, + ARM_INS_SXTAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SXTB, ARM_INS_SXTB, + {ARM_t2SXTB, ARM_INS_SXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2SXTB16, ARM_INS_SXTB16, + {ARM_t2SXTB16, + ARM_INS_SXTB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2SXTH, ARM_INS_SXTH, + {ARM_t2SXTH, ARM_INS_SXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2TBB, ARM_INS_TBB, + {ARM_t2TBB, ARM_INS_TBB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 1 #endif -}, + }, -{ - ARM_t2TBH, ARM_INS_TBH, + {ARM_t2TBH, ARM_INS_TBH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 1 #endif -}, + }, -{ - ARM_t2TEQri, ARM_INS_TEQ, + {ARM_t2TEQri, + ARM_INS_TEQ, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2TEQrr, ARM_INS_TEQ, + {ARM_t2TEQrr, + ARM_INS_TEQ, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2TEQrs, ARM_INS_TEQ, + {ARM_t2TEQrs, + ARM_INS_TEQ, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2TSB, ARM_INS_TSB, + {ARM_t2TSB, ARM_INS_TSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_t2TSTri, ARM_INS_TST, + {ARM_t2TSTri, + ARM_INS_TST, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2TSTrr, ARM_INS_TST, + {ARM_t2TSTrr, + ARM_INS_TST, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2TSTrs, ARM_INS_TST, + {ARM_t2TSTrs, + ARM_INS_TST, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2TT, ARM_INS_TT, + {ARM_t2TT, ARM_INS_TT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - ARM_t2TTA, ARM_INS_TTA, + {ARM_t2TTA, ARM_INS_TTA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_t2TTAT, ARM_INS_TTAT, + {ARM_t2TTAT, ARM_INS_TTAT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_t2TTT, ARM_INS_TTT, + {ARM_t2TTT, ARM_INS_TTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_t2UADD16, ARM_INS_UADD16, + {ARM_t2UADD16, + ARM_INS_UADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UADD8, ARM_INS_UADD8, + {ARM_t2UADD8, + ARM_INS_UADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UASX, ARM_INS_UASX, + {ARM_t2UASX, ARM_INS_UASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2UBFX, ARM_INS_UBFX, + {ARM_t2UBFX, ARM_INS_UBFX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2UDF, ARM_INS_UDF, + {ARM_t2UDF, ARM_INS_UDF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2UDIV, ARM_INS_UDIV, + {ARM_t2UDIV, ARM_INS_UDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2UHADD16, ARM_INS_UHADD16, + {ARM_t2UHADD16, + ARM_INS_UHADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UHADD8, ARM_INS_UHADD8, + {ARM_t2UHADD8, + ARM_INS_UHADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UHASX, ARM_INS_UHASX, + {ARM_t2UHASX, + ARM_INS_UHASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UHSAX, ARM_INS_UHSAX, + {ARM_t2UHSAX, + ARM_INS_UHSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UHSUB16, ARM_INS_UHSUB16, + {ARM_t2UHSUB16, + ARM_INS_UHSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UHSUB8, ARM_INS_UHSUB8, + {ARM_t2UHSUB8, + ARM_INS_UHSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UMAAL, ARM_INS_UMAAL, + {ARM_t2UMAAL, + ARM_INS_UMAAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UMLAL, ARM_INS_UMLAL, + {ARM_t2UMLAL, + ARM_INS_UMLAL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UMULL, ARM_INS_UMULL, + {ARM_t2UMULL, + ARM_INS_UMULL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UQADD16, ARM_INS_UQADD16, + {ARM_t2UQADD16, + ARM_INS_UQADD16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UQADD8, ARM_INS_UQADD8, + {ARM_t2UQADD8, + ARM_INS_UQADD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UQASX, ARM_INS_UQASX, + {ARM_t2UQASX, + ARM_INS_UQASX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UQSAX, ARM_INS_UQSAX, + {ARM_t2UQSAX, + ARM_INS_UQSAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UQSUB16, ARM_INS_UQSUB16, + {ARM_t2UQSUB16, + ARM_INS_UQSUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UQSUB8, ARM_INS_UQSUB8, + {ARM_t2UQSUB8, + ARM_INS_UQSUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2USAD8, ARM_INS_USAD8, + {ARM_t2USAD8, + ARM_INS_USAD8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2USADA8, ARM_INS_USADA8, + {ARM_t2USADA8, + ARM_INS_USADA8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2USAT, ARM_INS_USAT, + {ARM_t2USAT, ARM_INS_USAT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2USAT16, ARM_INS_USAT16, + {ARM_t2USAT16, + ARM_INS_USAT16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2USAX, ARM_INS_USAX, + {ARM_t2USAX, ARM_INS_USAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2USUB16, ARM_INS_USUB16, + {ARM_t2USUB16, + ARM_INS_USUB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2USUB8, ARM_INS_USUB8, + {ARM_t2USUB8, + ARM_INS_USUB8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UXTAB, ARM_INS_UXTAB, + {ARM_t2UXTAB, + ARM_INS_UXTAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UXTAB16, ARM_INS_UXTAB16, + {ARM_t2UXTAB16, + ARM_INS_UXTAB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UXTAH, ARM_INS_UXTAH, + {ARM_t2UXTAH, + ARM_INS_UXTAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UXTB, ARM_INS_UXTB, + {ARM_t2UXTB, ARM_INS_UXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_t2UXTB16, ARM_INS_UXTB16, + {ARM_t2UXTB16, + ARM_INS_UXTB16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_t2UXTH, ARM_INS_UXTH, + {ARM_t2UXTH, ARM_INS_UXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB2, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tADC, ARM_INS_ADC, + {ARM_tADC, + ARM_INS_ADC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tADDhirr, ARM_INS_ADD, + {ARM_tADDhirr, + ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tADDi3, ARM_INS_ADD, + {ARM_tADDi3, ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tADDi8, ARM_INS_ADD, + {ARM_tADDi8, ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tADDrSP, ARM_INS_ADD, + {ARM_tADDrSP, + ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tADDrSPi, ARM_INS_ADD, + {ARM_tADDrSPi, + ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tADDrr, ARM_INS_ADD, + {ARM_tADDrr, ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tADDspi, ARM_INS_ADD, + {ARM_tADDspi, + ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tADDspr, ARM_INS_ADD, + {ARM_tADDspr, + ARM_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tADR, ARM_INS_ADR, + {ARM_tADR, ARM_INS_ADR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tAND, ARM_INS_AND, + {ARM_tAND, ARM_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tASRri, ARM_INS_ASR, + {ARM_tASRri, ARM_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tASRrr, ARM_INS_ASR, + {ARM_tASRrr, ARM_INS_ASR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tB, ARM_INS_B, + {ARM_tB, + ARM_INS_B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 + {0}, + {0}, + {ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 1, + 0 #endif -}, + }, -{ - ARM_tBIC, ARM_INS_BIC, + {ARM_tBIC, ARM_INS_BIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tBKPT, ARM_INS_BKPT, + {ARM_tBKPT, ARM_INS_BKPT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tBL, ARM_INS_BL, + {ARM_tBL, + ARM_INS_BL, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, 1, 0 + {ARM_REG_PC, 0}, + {ARM_REG_LR, ARM_REG_PC, 0}, + {ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0}, + 1, + 0 #endif -}, + }, -{ - ARM_tBLXNSr, ARM_INS_BLXNS, + {ARM_tBLXNSr, + ARM_INS_BLXNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - ARM_tBLXi, ARM_INS_BLX, + {ARM_tBLXi, + ARM_INS_BLX, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, 1, 0 + {ARM_REG_PC, 0}, + {ARM_REG_LR, ARM_REG_PC, 0}, + {ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, + ARM_GRP_CALL, 0}, + 1, + 0 #endif -}, + }, -{ - ARM_tBLXr, ARM_INS_BLX, + {ARM_tBLXr, + ARM_INS_BLX, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_CALL, 0 }, 0, 1 + {ARM_REG_PC, 0}, + {ARM_REG_LR, ARM_REG_PC, 0}, + {ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_CALL, 0}, + 0, + 1 #endif -}, + }, -{ - ARM_tBX, ARM_INS_BX, + {ARM_tBX, ARM_INS_BX, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB, 0 }, 0, 1 + {0}, {ARM_REG_PC, 0}, {ARM_GRP_THUMB, 0}, 0, + 1 #endif -}, + }, -{ - ARM_tBXNS, ARM_INS_BXNS, + {ARM_tBXNS, ARM_INS_BXNS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - ARM_tBcc, ARM_INS_B, + {ARM_tBcc, + ARM_INS_B, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 + {0}, + {ARM_REG_PC, 0}, + {ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 1, + 0 #endif -}, + }, -{ - ARM_tCBNZ, ARM_INS_CBNZ, + {ARM_tCBNZ, ARM_INS_CBNZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 + {0}, {0}, {ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0}, 1, + 0 #endif -}, + }, -{ - ARM_tCBZ, ARM_INS_CBZ, + {ARM_tCBZ, ARM_INS_CBZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 + {0}, {0}, {ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0}, 1, + 0 #endif -}, + }, -{ - ARM_tCMNz, ARM_INS_CMN, + {ARM_tCMNz, ARM_INS_CMN, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tCMPhir, ARM_INS_CMP, + {ARM_tCMPhir, + ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {ARM_REG_CPSR, 0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tCMPi8, ARM_INS_CMP, + {ARM_tCMPi8, ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tCMPr, ARM_INS_CMP, + {ARM_tCMPr, ARM_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tCPS, ARM_INS_CPS, + {ARM_tCPS, ARM_INS_CPS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tEOR, ARM_INS_EOR, + {ARM_tEOR, ARM_INS_EOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tHINT, ARM_INS_HINT, + {ARM_tHINT, ARM_INS_HINT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6M, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_V6M, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tHLT, ARM_INS_HLT, + {ARM_tHLT, ARM_INS_HLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_V8, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDMIA, ARM_INS_LDM, + {ARM_tLDMIA, ARM_INS_LDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDRBi, ARM_INS_LDRB, + {ARM_tLDRBi, ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDRBr, ARM_INS_LDRB, + {ARM_tLDRBr, ARM_INS_LDRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDRHi, ARM_INS_LDRH, + {ARM_tLDRHi, ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDRHr, ARM_INS_LDRH, + {ARM_tLDRHr, ARM_INS_LDRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDRSB, ARM_INS_LDRSB, + {ARM_tLDRSB, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDRSH, ARM_INS_LDRSH, + {ARM_tLDRSH, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDRi, ARM_INS_LDR, + {ARM_tLDRi, ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDRpci, ARM_INS_LDR, + {ARM_tLDRpci, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tLDRr, ARM_INS_LDR, + {ARM_tLDRr, ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLDRspi, ARM_INS_LDR, + {ARM_tLDRspi, + ARM_INS_LDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tLSLri, ARM_INS_LSL, + {ARM_tLSLri, ARM_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLSLrr, ARM_INS_LSL, + {ARM_tLSLrr, ARM_INS_LSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLSRri, ARM_INS_LSR, + {ARM_tLSRri, ARM_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tLSRrr, ARM_INS_LSR, + {ARM_tLSRrr, ARM_INS_LSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tMOVSr, ARM_INS_MOVS, + {ARM_tMOVSr, ARM_INS_MOVS, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tMOVi8, ARM_INS_MOV, + {ARM_tMOVi8, ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tMOVr, ARM_INS_MOV, + {ARM_tMOVr, ARM_INS_MOV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tMUL, ARM_INS_MUL, + {ARM_tMUL, ARM_INS_MUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tMVN, ARM_INS_MVN, + {ARM_tMVN, ARM_INS_MVN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tORR, ARM_INS_ORR, + {ARM_tORR, ARM_INS_ORR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tPOP, ARM_INS_POP, + {ARM_tPOP, + ARM_INS_POP, #ifndef CAPSTONE_DIET - { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {ARM_REG_SP, 0}, + {ARM_REG_SP, 0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tPUSH, ARM_INS_PUSH, + {ARM_tPUSH, + ARM_INS_PUSH, #ifndef CAPSTONE_DIET - { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {ARM_REG_SP, 0}, + {ARM_REG_SP, 0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tREV, ARM_INS_REV, + {ARM_tREV, + ARM_INS_REV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tREV16, ARM_INS_REV16, + {ARM_tREV16, + ARM_INS_REV16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tREVSH, ARM_INS_REVSH, + {ARM_tREVSH, + ARM_INS_REVSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tROR, ARM_INS_ROR, + {ARM_tROR, ARM_INS_ROR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tRSB, ARM_INS_RSB, + {ARM_tRSB, ARM_INS_RSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSBC, ARM_INS_SBC, + {ARM_tSBC, + ARM_INS_SBC, #ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {ARM_REG_CPSR, 0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tSETEND, ARM_INS_SETEND, + {ARM_tSETEND, + ARM_INS_SETEND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tSTMIA_UPD, ARM_INS_STM, + {ARM_tSTMIA_UPD, + ARM_INS_STM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tSTRBi, ARM_INS_STRB, + {ARM_tSTRBi, ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSTRBr, ARM_INS_STRB, + {ARM_tSTRBr, ARM_INS_STRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSTRHi, ARM_INS_STRH, + {ARM_tSTRHi, ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSTRHr, ARM_INS_STRH, + {ARM_tSTRHr, ARM_INS_STRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSTRi, ARM_INS_STR, + {ARM_tSTRi, ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSTRr, ARM_INS_STR, + {ARM_tSTRr, ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSTRspi, ARM_INS_STR, + {ARM_tSTRspi, + ARM_INS_STR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tSUBi3, ARM_INS_SUB, + {ARM_tSUBi3, ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSUBi8, ARM_INS_SUB, + {ARM_tSUBi8, ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSUBrr, ARM_INS_SUB, + {ARM_tSUBrr, ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tSUBspi, ARM_INS_SUB, + {ARM_tSUBspi, + ARM_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tSVC, ARM_INS_SVC, + {ARM_tSVC, + ARM_INS_SVC, #ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_INT, 0 }, 0, 0 + {ARM_REG_PC, 0}, + {ARM_REG_LR, 0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_INT, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tSXTB, ARM_INS_SXTB, + {ARM_tSXTB, + ARM_INS_SXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tSXTH, ARM_INS_SXTH, + {ARM_tSXTH, + ARM_INS_SXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tTRAP, ARM_INS_TRAP, + {ARM_tTRAP, ARM_INS_TRAP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tTST, ARM_INS_TST, + {ARM_tTST, ARM_INS_TST, #ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 + {0}, {ARM_REG_CPSR, 0}, {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tUDF, ARM_INS_UDF, + {ARM_tUDF, ARM_INS_UDF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 + {0}, {0}, {ARM_GRP_THUMB, 0}, 0, + 0 #endif -}, + }, -{ - ARM_tUXTB, ARM_INS_UXTB, + {ARM_tUXTB, + ARM_INS_UXTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, + }, -{ - ARM_tUXTH, ARM_INS_UXTH, + {ARM_tUXTH, + ARM_INS_UXTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 + {0}, + {0}, + {ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0}, + 0, + 0 #endif -}, - + }, diff --git a/arch/ARM/ARMMappingInsnName.inc b/arch/ARM/ARMMappingInsnName.inc index 405d03fbba..b92bb02b7d 100644 --- a/arch/ARM/ARMMappingInsnName.inc +++ b/arch/ARM/ARMMappingInsnName.inc @@ -1,475 +1,476 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* This is auto-gen data for Capstone disassembly engine + * (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ - "adc", // ARM_INS_ADC, - "add", // ARM_INS_ADD, - "addw", // ARM_INS_ADDW, - "adr", // ARM_INS_ADR, - "aesd", // ARM_INS_AESD, - "aese", // ARM_INS_AESE, - "aesimc", // ARM_INS_AESIMC, - "aesmc", // ARM_INS_AESMC, - "and", // ARM_INS_AND, - "asr", // ARM_INS_ASR, - "b", // ARM_INS_B, - "bfc", // ARM_INS_BFC, - "bfi", // ARM_INS_BFI, - "bic", // ARM_INS_BIC, - "bkpt", // ARM_INS_BKPT, - "bl", // ARM_INS_BL, - "blx", // ARM_INS_BLX, - "blxns", // ARM_INS_BLXNS, - "bx", // ARM_INS_BX, - "bxj", // ARM_INS_BXJ, - "bxns", // ARM_INS_BXNS, - "cbnz", // ARM_INS_CBNZ, - "cbz", // ARM_INS_CBZ, - "cdp", // ARM_INS_CDP, - "cdp2", // ARM_INS_CDP2, - "clrex", // ARM_INS_CLREX, - "clz", // ARM_INS_CLZ, - "cmn", // ARM_INS_CMN, - "cmp", // ARM_INS_CMP, - "cps", // ARM_INS_CPS, - "crc32b", // ARM_INS_CRC32B, - "crc32cb", // ARM_INS_CRC32CB, - "crc32ch", // ARM_INS_CRC32CH, - "crc32cw", // ARM_INS_CRC32CW, - "crc32h", // ARM_INS_CRC32H, - "crc32w", // ARM_INS_CRC32W, - "csdb", // ARM_INS_CSDB, - "dbg", // ARM_INS_DBG, - "dcps1", // ARM_INS_DCPS1, - "dcps2", // ARM_INS_DCPS2, - "dcps3", // ARM_INS_DCPS3, - "dfb", // ARM_INS_DFB, - "dmb", // ARM_INS_DMB, - "dsb", // ARM_INS_DSB, - "eor", // ARM_INS_EOR, - "eret", // ARM_INS_ERET, - "esb", // ARM_INS_ESB, - "faddd", // ARM_INS_FADDD, - "fadds", // ARM_INS_FADDS, - "fcmpzd", // ARM_INS_FCMPZD, - "fcmpzs", // ARM_INS_FCMPZS, - "fconstd", // ARM_INS_FCONSTD, - "fconsts", // ARM_INS_FCONSTS, - "fldmdbx", // ARM_INS_FLDMDBX, - "fldmiax", // ARM_INS_FLDMIAX, - "fmdhr", // ARM_INS_FMDHR, - "fmdlr", // ARM_INS_FMDLR, - "fmstat", // ARM_INS_FMSTAT, - "fstmdbx", // ARM_INS_FSTMDBX, - "fstmiax", // ARM_INS_FSTMIAX, - "fsubd", // ARM_INS_FSUBD, - "fsubs", // ARM_INS_FSUBS, - "hint", // ARM_INS_HINT, - "hlt", // ARM_INS_HLT, - "hvc", // ARM_INS_HVC, - "isb", // ARM_INS_ISB, - "it", // ARM_INS_IT, - "lda", // ARM_INS_LDA, - "ldab", // ARM_INS_LDAB, - "ldaex", // ARM_INS_LDAEX, - "ldaexb", // ARM_INS_LDAEXB, - "ldaexd", // ARM_INS_LDAEXD, - "ldaexh", // ARM_INS_LDAEXH, - "ldah", // ARM_INS_LDAH, - "ldc", // ARM_INS_LDC, - "ldc2", // ARM_INS_LDC2, - "ldc2l", // ARM_INS_LDC2L, - "ldcl", // ARM_INS_LDCL, - "ldm", // ARM_INS_LDM, - "ldmda", // ARM_INS_LDMDA, - "ldmdb", // ARM_INS_LDMDB, - "ldmib", // ARM_INS_LDMIB, - "ldr", // ARM_INS_LDR, - "ldrb", // ARM_INS_LDRB, - "ldrbt", // ARM_INS_LDRBT, - "ldrd", // ARM_INS_LDRD, - "ldrex", // ARM_INS_LDREX, - "ldrexb", // ARM_INS_LDREXB, - "ldrexd", // ARM_INS_LDREXD, - "ldrexh", // ARM_INS_LDREXH, - "ldrh", // ARM_INS_LDRH, - "ldrht", // ARM_INS_LDRHT, - "ldrsb", // ARM_INS_LDRSB, - "ldrsbt", // ARM_INS_LDRSBT, - "ldrsh", // ARM_INS_LDRSH, - "ldrsht", // ARM_INS_LDRSHT, - "ldrt", // ARM_INS_LDRT, - "lsl", // ARM_INS_LSL, - "lsr", // ARM_INS_LSR, - "mcr", // ARM_INS_MCR, - "mcr2", // ARM_INS_MCR2, - "mcrr", // ARM_INS_MCRR, - "mcrr2", // ARM_INS_MCRR2, - "mla", // ARM_INS_MLA, - "mls", // ARM_INS_MLS, - "mov", // ARM_INS_MOV, - "movs", // ARM_INS_MOVS, - "movt", // ARM_INS_MOVT, - "movw", // ARM_INS_MOVW, - "mrc", // ARM_INS_MRC, - "mrc2", // ARM_INS_MRC2, - "mrrc", // ARM_INS_MRRC, - "mrrc2", // ARM_INS_MRRC2, - "mrs", // ARM_INS_MRS, - "msr", // ARM_INS_MSR, - "mul", // ARM_INS_MUL, - "mvn", // ARM_INS_MVN, - "neg", // ARM_INS_NEG, - "nop", // ARM_INS_NOP, - "orn", // ARM_INS_ORN, - "orr", // ARM_INS_ORR, - "pkhbt", // ARM_INS_PKHBT, - "pkhtb", // ARM_INS_PKHTB, - "pld", // ARM_INS_PLD, - "pldw", // ARM_INS_PLDW, - "pli", // ARM_INS_PLI, - "pop", // ARM_INS_POP, - "push", // ARM_INS_PUSH, - "qadd", // ARM_INS_QADD, - "qadd16", // ARM_INS_QADD16, - "qadd8", // ARM_INS_QADD8, - "qasx", // ARM_INS_QASX, - "qdadd", // ARM_INS_QDADD, - "qdsub", // ARM_INS_QDSUB, - "qsax", // ARM_INS_QSAX, - "qsub", // ARM_INS_QSUB, - "qsub16", // ARM_INS_QSUB16, - "qsub8", // ARM_INS_QSUB8, - "rbit", // ARM_INS_RBIT, - "rev", // ARM_INS_REV, - "rev16", // ARM_INS_REV16, - "revsh", // ARM_INS_REVSH, - "rfeda", // ARM_INS_RFEDA, - "rfedb", // ARM_INS_RFEDB, - "rfeia", // ARM_INS_RFEIA, - "rfeib", // ARM_INS_RFEIB, - "ror", // ARM_INS_ROR, - "rrx", // ARM_INS_RRX, - "rsb", // ARM_INS_RSB, - "rsc", // ARM_INS_RSC, - "sadd16", // ARM_INS_SADD16, - "sadd8", // ARM_INS_SADD8, - "sasx", // ARM_INS_SASX, - "sbc", // ARM_INS_SBC, - "sbfx", // ARM_INS_SBFX, - "sdiv", // ARM_INS_SDIV, - "sel", // ARM_INS_SEL, - "setend", // ARM_INS_SETEND, - "setpan", // ARM_INS_SETPAN, - "sev", // ARM_INS_SEV, - "sevl", // ARM_INS_SEVL, - "sg", // ARM_INS_SG, - "sha1c", // ARM_INS_SHA1C, - "sha1h", // ARM_INS_SHA1H, - "sha1m", // ARM_INS_SHA1M, - "sha1p", // ARM_INS_SHA1P, - "sha1su0", // ARM_INS_SHA1SU0, - "sha1su1", // ARM_INS_SHA1SU1, - "sha256h", // ARM_INS_SHA256H, - "sha256h2", // ARM_INS_SHA256H2, - "sha256su0", // ARM_INS_SHA256SU0, - "sha256su1", // ARM_INS_SHA256SU1, - "shadd16", // ARM_INS_SHADD16, - "shadd8", // ARM_INS_SHADD8, - "shasx", // ARM_INS_SHASX, - "shsax", // ARM_INS_SHSAX, - "shsub16", // ARM_INS_SHSUB16, - "shsub8", // ARM_INS_SHSUB8, - "smc", // ARM_INS_SMC, - "smlabb", // ARM_INS_SMLABB, - "smlabt", // ARM_INS_SMLABT, - "smlad", // ARM_INS_SMLAD, - "smladx", // ARM_INS_SMLADX, - "smlal", // ARM_INS_SMLAL, - "smlalbb", // ARM_INS_SMLALBB, - "smlalbt", // ARM_INS_SMLALBT, - "smlald", // ARM_INS_SMLALD, - "smlaldx", // ARM_INS_SMLALDX, - "smlaltb", // ARM_INS_SMLALTB, - "smlaltt", // ARM_INS_SMLALTT, - "smlatb", // ARM_INS_SMLATB, - "smlatt", // ARM_INS_SMLATT, - "smlawb", // ARM_INS_SMLAWB, - "smlawt", // ARM_INS_SMLAWT, - "smlsd", // ARM_INS_SMLSD, - "smlsdx", // ARM_INS_SMLSDX, - "smlsld", // ARM_INS_SMLSLD, - "smlsldx", // ARM_INS_SMLSLDX, - "smmla", // ARM_INS_SMMLA, - "smmlar", // ARM_INS_SMMLAR, - "smmls", // ARM_INS_SMMLS, - "smmlsr", // ARM_INS_SMMLSR, - "smmul", // ARM_INS_SMMUL, - "smmulr", // ARM_INS_SMMULR, - "smuad", // ARM_INS_SMUAD, - "smuadx", // ARM_INS_SMUADX, - "smulbb", // ARM_INS_SMULBB, - "smulbt", // ARM_INS_SMULBT, - "smull", // ARM_INS_SMULL, - "smultb", // ARM_INS_SMULTB, - "smultt", // ARM_INS_SMULTT, - "smulwb", // ARM_INS_SMULWB, - "smulwt", // ARM_INS_SMULWT, - "smusd", // ARM_INS_SMUSD, - "smusdx", // ARM_INS_SMUSDX, - "srsda", // ARM_INS_SRSDA, - "srsdb", // ARM_INS_SRSDB, - "srsia", // ARM_INS_SRSIA, - "srsib", // ARM_INS_SRSIB, - "ssat", // ARM_INS_SSAT, - "ssat16", // ARM_INS_SSAT16, - "ssax", // ARM_INS_SSAX, - "ssub16", // ARM_INS_SSUB16, - "ssub8", // ARM_INS_SSUB8, - "stc", // ARM_INS_STC, - "stc2", // ARM_INS_STC2, - "stc2l", // ARM_INS_STC2L, - "stcl", // ARM_INS_STCL, - "stl", // ARM_INS_STL, - "stlb", // ARM_INS_STLB, - "stlex", // ARM_INS_STLEX, - "stlexb", // ARM_INS_STLEXB, - "stlexd", // ARM_INS_STLEXD, - "stlexh", // ARM_INS_STLEXH, - "stlh", // ARM_INS_STLH, - "stm", // ARM_INS_STM, - "stmda", // ARM_INS_STMDA, - "stmdb", // ARM_INS_STMDB, - "stmib", // ARM_INS_STMIB, - "str", // ARM_INS_STR, - "strb", // ARM_INS_STRB, - "strbt", // ARM_INS_STRBT, - "strd", // ARM_INS_STRD, - "strex", // ARM_INS_STREX, - "strexb", // ARM_INS_STREXB, - "strexd", // ARM_INS_STREXD, - "strexh", // ARM_INS_STREXH, - "strh", // ARM_INS_STRH, - "strht", // ARM_INS_STRHT, - "strt", // ARM_INS_STRT, - "sub", // ARM_INS_SUB, - "subs", // ARM_INS_SUBS, - "subw", // ARM_INS_SUBW, - "svc", // ARM_INS_SVC, - "swp", // ARM_INS_SWP, - "swpb", // ARM_INS_SWPB, - "sxtab", // ARM_INS_SXTAB, - "sxtab16", // ARM_INS_SXTAB16, - "sxtah", // ARM_INS_SXTAH, - "sxtb", // ARM_INS_SXTB, - "sxtb16", // ARM_INS_SXTB16, - "sxth", // ARM_INS_SXTH, - "tbb", // ARM_INS_TBB, - "tbh", // ARM_INS_TBH, - "teq", // ARM_INS_TEQ, - "trap", // ARM_INS_TRAP, - "tsb", // ARM_INS_TSB, - "tst", // ARM_INS_TST, - "tt", // ARM_INS_TT, - "tta", // ARM_INS_TTA, - "ttat", // ARM_INS_TTAT, - "ttt", // ARM_INS_TTT, - "uadd16", // ARM_INS_UADD16, - "uadd8", // ARM_INS_UADD8, - "uasx", // ARM_INS_UASX, - "ubfx", // ARM_INS_UBFX, - "udf", // ARM_INS_UDF, - "udiv", // ARM_INS_UDIV, - "uhadd16", // ARM_INS_UHADD16, - "uhadd8", // ARM_INS_UHADD8, - "uhasx", // ARM_INS_UHASX, - "uhsax", // ARM_INS_UHSAX, - "uhsub16", // ARM_INS_UHSUB16, - "uhsub8", // ARM_INS_UHSUB8, - "umaal", // ARM_INS_UMAAL, - "umlal", // ARM_INS_UMLAL, - "umull", // ARM_INS_UMULL, - "uqadd16", // ARM_INS_UQADD16, - "uqadd8", // ARM_INS_UQADD8, - "uqasx", // ARM_INS_UQASX, - "uqsax", // ARM_INS_UQSAX, - "uqsub16", // ARM_INS_UQSUB16, - "uqsub8", // ARM_INS_UQSUB8, - "usad8", // ARM_INS_USAD8, - "usada8", // ARM_INS_USADA8, - "usat", // ARM_INS_USAT, - "usat16", // ARM_INS_USAT16, - "usax", // ARM_INS_USAX, - "usub16", // ARM_INS_USUB16, - "usub8", // ARM_INS_USUB8, - "uxtab", // ARM_INS_UXTAB, - "uxtab16", // ARM_INS_UXTAB16, - "uxtah", // ARM_INS_UXTAH, - "uxtb", // ARM_INS_UXTB, - "uxtb16", // ARM_INS_UXTB16, - "uxth", // ARM_INS_UXTH, - "vaba", // ARM_INS_VABA, - "vabal", // ARM_INS_VABAL, - "vabd", // ARM_INS_VABD, - "vabdl", // ARM_INS_VABDL, - "vabs", // ARM_INS_VABS, - "vacge", // ARM_INS_VACGE, - "vacgt", // ARM_INS_VACGT, - "vacle", // ARM_INS_VACLE, - "vaclt", // ARM_INS_VACLT, - "vadd", // ARM_INS_VADD, - "vaddhn", // ARM_INS_VADDHN, - "vaddl", // ARM_INS_VADDL, - "vaddw", // ARM_INS_VADDW, - "vand", // ARM_INS_VAND, - "vbic", // ARM_INS_VBIC, - "vbif", // ARM_INS_VBIF, - "vbit", // ARM_INS_VBIT, - "vbsl", // ARM_INS_VBSL, - "vcadd", // ARM_INS_VCADD, - "vceq", // ARM_INS_VCEQ, - "vcge", // ARM_INS_VCGE, - "vcgt", // ARM_INS_VCGT, - "vcle", // ARM_INS_VCLE, - "vcls", // ARM_INS_VCLS, - "vclt", // ARM_INS_VCLT, - "vclz", // ARM_INS_VCLZ, - "vcmla", // ARM_INS_VCMLA, - "vcmp", // ARM_INS_VCMP, - "vcmpe", // ARM_INS_VCMPE, - "vcnt", // ARM_INS_VCNT, - "vcvt", // ARM_INS_VCVT, - "vcvta", // ARM_INS_VCVTA, - "vcvtb", // ARM_INS_VCVTB, - "vcvtm", // ARM_INS_VCVTM, - "vcvtn", // ARM_INS_VCVTN, - "vcvtp", // ARM_INS_VCVTP, - "vcvtr", // ARM_INS_VCVTR, - "vcvtt", // ARM_INS_VCVTT, - "vdiv", // ARM_INS_VDIV, - "vdup", // ARM_INS_VDUP, - "veor", // ARM_INS_VEOR, - "vext", // ARM_INS_VEXT, - "vfma", // ARM_INS_VFMA, - "vfms", // ARM_INS_VFMS, - "vfnma", // ARM_INS_VFNMA, - "vfnms", // ARM_INS_VFNMS, - "vhadd", // ARM_INS_VHADD, - "vhsub", // ARM_INS_VHSUB, - "vins", // ARM_INS_VINS, - "vjcvt", // ARM_INS_VJCVT, - "vld1", // ARM_INS_VLD1, - "vld2", // ARM_INS_VLD2, - "vld3", // ARM_INS_VLD3, - "vld4", // ARM_INS_VLD4, - "vldmdb", // ARM_INS_VLDMDB, - "vldmia", // ARM_INS_VLDMIA, - "vldr", // ARM_INS_VLDR, - "vlldm", // ARM_INS_VLLDM, - "vlstm", // ARM_INS_VLSTM, - "vmax", // ARM_INS_VMAX, - "vmaxnm", // ARM_INS_VMAXNM, - "vmin", // ARM_INS_VMIN, - "vminnm", // ARM_INS_VMINNM, - "vmla", // ARM_INS_VMLA, - "vmlal", // ARM_INS_VMLAL, - "vmls", // ARM_INS_VMLS, - "vmlsl", // ARM_INS_VMLSL, - "vmov", // ARM_INS_VMOV, - "vmovl", // ARM_INS_VMOVL, - "vmovn", // ARM_INS_VMOVN, - "vmovx", // ARM_INS_VMOVX, - "vmrs", // ARM_INS_VMRS, - "vmsr", // ARM_INS_VMSR, - "vmul", // ARM_INS_VMUL, - "vmull", // ARM_INS_VMULL, - "vmvn", // ARM_INS_VMVN, - "vneg", // ARM_INS_VNEG, - "vnmla", // ARM_INS_VNMLA, - "vnmls", // ARM_INS_VNMLS, - "vnmul", // ARM_INS_VNMUL, - "vorn", // ARM_INS_VORN, - "vorr", // ARM_INS_VORR, - "vpadal", // ARM_INS_VPADAL, - "vpadd", // ARM_INS_VPADD, - "vpaddl", // ARM_INS_VPADDL, - "vpmax", // ARM_INS_VPMAX, - "vpmin", // ARM_INS_VPMIN, - "vpop", // ARM_INS_VPOP, - "vpush", // ARM_INS_VPUSH, - "vqabs", // ARM_INS_VQABS, - "vqadd", // ARM_INS_VQADD, - "vqdmlal", // ARM_INS_VQDMLAL, - "vqdmlsl", // ARM_INS_VQDMLSL, - "vqdmulh", // ARM_INS_VQDMULH, - "vqdmull", // ARM_INS_VQDMULL, - "vqmovn", // ARM_INS_VQMOVN, - "vqmovun", // ARM_INS_VQMOVUN, - "vqneg", // ARM_INS_VQNEG, - "vqrdmlah", // ARM_INS_VQRDMLAH, - "vqrdmlsh", // ARM_INS_VQRDMLSH, - "vqrdmulh", // ARM_INS_VQRDMULH, - "vqrshl", // ARM_INS_VQRSHL, - "vqrshrn", // ARM_INS_VQRSHRN, - "vqrshrun", // ARM_INS_VQRSHRUN, - "vqshl", // ARM_INS_VQSHL, - "vqshlu", // ARM_INS_VQSHLU, - "vqshrn", // ARM_INS_VQSHRN, - "vqshrun", // ARM_INS_VQSHRUN, - "vqsub", // ARM_INS_VQSUB, - "vraddhn", // ARM_INS_VRADDHN, - "vrecpe", // ARM_INS_VRECPE, - "vrecps", // ARM_INS_VRECPS, - "vrev16", // ARM_INS_VREV16, - "vrev32", // ARM_INS_VREV32, - "vrev64", // ARM_INS_VREV64, - "vrhadd", // ARM_INS_VRHADD, - "vrinta", // ARM_INS_VRINTA, - "vrintm", // ARM_INS_VRINTM, - "vrintn", // ARM_INS_VRINTN, - "vrintp", // ARM_INS_VRINTP, - "vrintr", // ARM_INS_VRINTR, - "vrintx", // ARM_INS_VRINTX, - "vrintz", // ARM_INS_VRINTZ, - "vrshl", // ARM_INS_VRSHL, - "vrshr", // ARM_INS_VRSHR, - "vrshrn", // ARM_INS_VRSHRN, - "vrsqrte", // ARM_INS_VRSQRTE, - "vrsqrts", // ARM_INS_VRSQRTS, - "vrsra", // ARM_INS_VRSRA, - "vrsubhn", // ARM_INS_VRSUBHN, - "vsdot", // ARM_INS_VSDOT, - "vseleq", // ARM_INS_VSELEQ, - "vselge", // ARM_INS_VSELGE, - "vselgt", // ARM_INS_VSELGT, - "vselvs", // ARM_INS_VSELVS, - "vshl", // ARM_INS_VSHL, - "vshll", // ARM_INS_VSHLL, - "vshr", // ARM_INS_VSHR, - "vshrn", // ARM_INS_VSHRN, - "vsli", // ARM_INS_VSLI, - "vsqrt", // ARM_INS_VSQRT, - "vsra", // ARM_INS_VSRA, - "vsri", // ARM_INS_VSRI, - "vst1", // ARM_INS_VST1, - "vst2", // ARM_INS_VST2, - "vst3", // ARM_INS_VST3, - "vst4", // ARM_INS_VST4, - "vstmdb", // ARM_INS_VSTMDB, - "vstmia", // ARM_INS_VSTMIA, - "vstr", // ARM_INS_VSTR, - "vsub", // ARM_INS_VSUB, - "vsubhn", // ARM_INS_VSUBHN, - "vsubl", // ARM_INS_VSUBL, - "vsubw", // ARM_INS_VSUBW, - "vswp", // ARM_INS_VSWP, - "vtbl", // ARM_INS_VTBL, - "vtbx", // ARM_INS_VTBX, - "vtrn", // ARM_INS_VTRN, - "vtst", // ARM_INS_VTST, - "vudot", // ARM_INS_VUDOT, - "vuzp", // ARM_INS_VUZP, - "vzip", // ARM_INS_VZIP, - "wfe", // ARM_INS_WFE, - "wfi", // ARM_INS_WFI, - "yield", // ARM_INS_YIELD, +"adc", // ARM_INS_ADC, + "add", // ARM_INS_ADD, + "addw", // ARM_INS_ADDW, + "adr", // ARM_INS_ADR, + "aesd", // ARM_INS_AESD, + "aese", // ARM_INS_AESE, + "aesimc", // ARM_INS_AESIMC, + "aesmc", // ARM_INS_AESMC, + "and", // ARM_INS_AND, + "asr", // ARM_INS_ASR, + "b", // ARM_INS_B, + "bfc", // ARM_INS_BFC, + "bfi", // ARM_INS_BFI, + "bic", // ARM_INS_BIC, + "bkpt", // ARM_INS_BKPT, + "bl", // ARM_INS_BL, + "blx", // ARM_INS_BLX, + "blxns", // ARM_INS_BLXNS, + "bx", // ARM_INS_BX, + "bxj", // ARM_INS_BXJ, + "bxns", // ARM_INS_BXNS, + "cbnz", // ARM_INS_CBNZ, + "cbz", // ARM_INS_CBZ, + "cdp", // ARM_INS_CDP, + "cdp2", // ARM_INS_CDP2, + "clrex", // ARM_INS_CLREX, + "clz", // ARM_INS_CLZ, + "cmn", // ARM_INS_CMN, + "cmp", // ARM_INS_CMP, + "cps", // ARM_INS_CPS, + "crc32b", // ARM_INS_CRC32B, + "crc32cb", // ARM_INS_CRC32CB, + "crc32ch", // ARM_INS_CRC32CH, + "crc32cw", // ARM_INS_CRC32CW, + "crc32h", // ARM_INS_CRC32H, + "crc32w", // ARM_INS_CRC32W, + "csdb", // ARM_INS_CSDB, + "dbg", // ARM_INS_DBG, + "dcps1", // ARM_INS_DCPS1, + "dcps2", // ARM_INS_DCPS2, + "dcps3", // ARM_INS_DCPS3, + "dfb", // ARM_INS_DFB, + "dmb", // ARM_INS_DMB, + "dsb", // ARM_INS_DSB, + "eor", // ARM_INS_EOR, + "eret", // ARM_INS_ERET, + "esb", // ARM_INS_ESB, + "faddd", // ARM_INS_FADDD, + "fadds", // ARM_INS_FADDS, + "fcmpzd", // ARM_INS_FCMPZD, + "fcmpzs", // ARM_INS_FCMPZS, + "fconstd", // ARM_INS_FCONSTD, + "fconsts", // ARM_INS_FCONSTS, + "fldmdbx", // ARM_INS_FLDMDBX, + "fldmiax", // ARM_INS_FLDMIAX, + "fmdhr", // ARM_INS_FMDHR, + "fmdlr", // ARM_INS_FMDLR, + "fmstat", // ARM_INS_FMSTAT, + "fstmdbx", // ARM_INS_FSTMDBX, + "fstmiax", // ARM_INS_FSTMIAX, + "fsubd", // ARM_INS_FSUBD, + "fsubs", // ARM_INS_FSUBS, + "hint", // ARM_INS_HINT, + "hlt", // ARM_INS_HLT, + "hvc", // ARM_INS_HVC, + "isb", // ARM_INS_ISB, + "it", // ARM_INS_IT, + "lda", // ARM_INS_LDA, + "ldab", // ARM_INS_LDAB, + "ldaex", // ARM_INS_LDAEX, + "ldaexb", // ARM_INS_LDAEXB, + "ldaexd", // ARM_INS_LDAEXD, + "ldaexh", // ARM_INS_LDAEXH, + "ldah", // ARM_INS_LDAH, + "ldc", // ARM_INS_LDC, + "ldc2", // ARM_INS_LDC2, + "ldc2l", // ARM_INS_LDC2L, + "ldcl", // ARM_INS_LDCL, + "ldm", // ARM_INS_LDM, + "ldmda", // ARM_INS_LDMDA, + "ldmdb", // ARM_INS_LDMDB, + "ldmib", // ARM_INS_LDMIB, + "ldr", // ARM_INS_LDR, + "ldrb", // ARM_INS_LDRB, + "ldrbt", // ARM_INS_LDRBT, + "ldrd", // ARM_INS_LDRD, + "ldrex", // ARM_INS_LDREX, + "ldrexb", // ARM_INS_LDREXB, + "ldrexd", // ARM_INS_LDREXD, + "ldrexh", // ARM_INS_LDREXH, + "ldrh", // ARM_INS_LDRH, + "ldrht", // ARM_INS_LDRHT, + "ldrsb", // ARM_INS_LDRSB, + "ldrsbt", // ARM_INS_LDRSBT, + "ldrsh", // ARM_INS_LDRSH, + "ldrsht", // ARM_INS_LDRSHT, + "ldrt", // ARM_INS_LDRT, + "lsl", // ARM_INS_LSL, + "lsr", // ARM_INS_LSR, + "mcr", // ARM_INS_MCR, + "mcr2", // ARM_INS_MCR2, + "mcrr", // ARM_INS_MCRR, + "mcrr2", // ARM_INS_MCRR2, + "mla", // ARM_INS_MLA, + "mls", // ARM_INS_MLS, + "mov", // ARM_INS_MOV, + "movs", // ARM_INS_MOVS, + "movt", // ARM_INS_MOVT, + "movw", // ARM_INS_MOVW, + "mrc", // ARM_INS_MRC, + "mrc2", // ARM_INS_MRC2, + "mrrc", // ARM_INS_MRRC, + "mrrc2", // ARM_INS_MRRC2, + "mrs", // ARM_INS_MRS, + "msr", // ARM_INS_MSR, + "mul", // ARM_INS_MUL, + "mvn", // ARM_INS_MVN, + "neg", // ARM_INS_NEG, + "nop", // ARM_INS_NOP, + "orn", // ARM_INS_ORN, + "orr", // ARM_INS_ORR, + "pkhbt", // ARM_INS_PKHBT, + "pkhtb", // ARM_INS_PKHTB, + "pld", // ARM_INS_PLD, + "pldw", // ARM_INS_PLDW, + "pli", // ARM_INS_PLI, + "pop", // ARM_INS_POP, + "push", // ARM_INS_PUSH, + "qadd", // ARM_INS_QADD, + "qadd16", // ARM_INS_QADD16, + "qadd8", // ARM_INS_QADD8, + "qasx", // ARM_INS_QASX, + "qdadd", // ARM_INS_QDADD, + "qdsub", // ARM_INS_QDSUB, + "qsax", // ARM_INS_QSAX, + "qsub", // ARM_INS_QSUB, + "qsub16", // ARM_INS_QSUB16, + "qsub8", // ARM_INS_QSUB8, + "rbit", // ARM_INS_RBIT, + "rev", // ARM_INS_REV, + "rev16", // ARM_INS_REV16, + "revsh", // ARM_INS_REVSH, + "rfeda", // ARM_INS_RFEDA, + "rfedb", // ARM_INS_RFEDB, + "rfeia", // ARM_INS_RFEIA, + "rfeib", // ARM_INS_RFEIB, + "ror", // ARM_INS_ROR, + "rrx", // ARM_INS_RRX, + "rsb", // ARM_INS_RSB, + "rsc", // ARM_INS_RSC, + "sadd16", // ARM_INS_SADD16, + "sadd8", // ARM_INS_SADD8, + "sasx", // ARM_INS_SASX, + "sbc", // ARM_INS_SBC, + "sbfx", // ARM_INS_SBFX, + "sdiv", // ARM_INS_SDIV, + "sel", // ARM_INS_SEL, + "setend", // ARM_INS_SETEND, + "setpan", // ARM_INS_SETPAN, + "sev", // ARM_INS_SEV, + "sevl", // ARM_INS_SEVL, + "sg", // ARM_INS_SG, + "sha1c", // ARM_INS_SHA1C, + "sha1h", // ARM_INS_SHA1H, + "sha1m", // ARM_INS_SHA1M, + "sha1p", // ARM_INS_SHA1P, + "sha1su0", // ARM_INS_SHA1SU0, + "sha1su1", // ARM_INS_SHA1SU1, + "sha256h", // ARM_INS_SHA256H, + "sha256h2", // ARM_INS_SHA256H2, + "sha256su0", // ARM_INS_SHA256SU0, + "sha256su1", // ARM_INS_SHA256SU1, + "shadd16", // ARM_INS_SHADD16, + "shadd8", // ARM_INS_SHADD8, + "shasx", // ARM_INS_SHASX, + "shsax", // ARM_INS_SHSAX, + "shsub16", // ARM_INS_SHSUB16, + "shsub8", // ARM_INS_SHSUB8, + "smc", // ARM_INS_SMC, + "smlabb", // ARM_INS_SMLABB, + "smlabt", // ARM_INS_SMLABT, + "smlad", // ARM_INS_SMLAD, + "smladx", // ARM_INS_SMLADX, + "smlal", // ARM_INS_SMLAL, + "smlalbb", // ARM_INS_SMLALBB, + "smlalbt", // ARM_INS_SMLALBT, + "smlald", // ARM_INS_SMLALD, + "smlaldx", // ARM_INS_SMLALDX, + "smlaltb", // ARM_INS_SMLALTB, + "smlaltt", // ARM_INS_SMLALTT, + "smlatb", // ARM_INS_SMLATB, + "smlatt", // ARM_INS_SMLATT, + "smlawb", // ARM_INS_SMLAWB, + "smlawt", // ARM_INS_SMLAWT, + "smlsd", // ARM_INS_SMLSD, + "smlsdx", // ARM_INS_SMLSDX, + "smlsld", // ARM_INS_SMLSLD, + "smlsldx", // ARM_INS_SMLSLDX, + "smmla", // ARM_INS_SMMLA, + "smmlar", // ARM_INS_SMMLAR, + "smmls", // ARM_INS_SMMLS, + "smmlsr", // ARM_INS_SMMLSR, + "smmul", // ARM_INS_SMMUL, + "smmulr", // ARM_INS_SMMULR, + "smuad", // ARM_INS_SMUAD, + "smuadx", // ARM_INS_SMUADX, + "smulbb", // ARM_INS_SMULBB, + "smulbt", // ARM_INS_SMULBT, + "smull", // ARM_INS_SMULL, + "smultb", // ARM_INS_SMULTB, + "smultt", // ARM_INS_SMULTT, + "smulwb", // ARM_INS_SMULWB, + "smulwt", // ARM_INS_SMULWT, + "smusd", // ARM_INS_SMUSD, + "smusdx", // ARM_INS_SMUSDX, + "srsda", // ARM_INS_SRSDA, + "srsdb", // ARM_INS_SRSDB, + "srsia", // ARM_INS_SRSIA, + "srsib", // ARM_INS_SRSIB, + "ssat", // ARM_INS_SSAT, + "ssat16", // ARM_INS_SSAT16, + "ssax", // ARM_INS_SSAX, + "ssub16", // ARM_INS_SSUB16, + "ssub8", // ARM_INS_SSUB8, + "stc", // ARM_INS_STC, + "stc2", // ARM_INS_STC2, + "stc2l", // ARM_INS_STC2L, + "stcl", // ARM_INS_STCL, + "stl", // ARM_INS_STL, + "stlb", // ARM_INS_STLB, + "stlex", // ARM_INS_STLEX, + "stlexb", // ARM_INS_STLEXB, + "stlexd", // ARM_INS_STLEXD, + "stlexh", // ARM_INS_STLEXH, + "stlh", // ARM_INS_STLH, + "stm", // ARM_INS_STM, + "stmda", // ARM_INS_STMDA, + "stmdb", // ARM_INS_STMDB, + "stmib", // ARM_INS_STMIB, + "str", // ARM_INS_STR, + "strb", // ARM_INS_STRB, + "strbt", // ARM_INS_STRBT, + "strd", // ARM_INS_STRD, + "strex", // ARM_INS_STREX, + "strexb", // ARM_INS_STREXB, + "strexd", // ARM_INS_STREXD, + "strexh", // ARM_INS_STREXH, + "strh", // ARM_INS_STRH, + "strht", // ARM_INS_STRHT, + "strt", // ARM_INS_STRT, + "sub", // ARM_INS_SUB, + "subs", // ARM_INS_SUBS, + "subw", // ARM_INS_SUBW, + "svc", // ARM_INS_SVC, + "swp", // ARM_INS_SWP, + "swpb", // ARM_INS_SWPB, + "sxtab", // ARM_INS_SXTAB, + "sxtab16", // ARM_INS_SXTAB16, + "sxtah", // ARM_INS_SXTAH, + "sxtb", // ARM_INS_SXTB, + "sxtb16", // ARM_INS_SXTB16, + "sxth", // ARM_INS_SXTH, + "tbb", // ARM_INS_TBB, + "tbh", // ARM_INS_TBH, + "teq", // ARM_INS_TEQ, + "trap", // ARM_INS_TRAP, + "tsb", // ARM_INS_TSB, + "tst", // ARM_INS_TST, + "tt", // ARM_INS_TT, + "tta", // ARM_INS_TTA, + "ttat", // ARM_INS_TTAT, + "ttt", // ARM_INS_TTT, + "uadd16", // ARM_INS_UADD16, + "uadd8", // ARM_INS_UADD8, + "uasx", // ARM_INS_UASX, + "ubfx", // ARM_INS_UBFX, + "udf", // ARM_INS_UDF, + "udiv", // ARM_INS_UDIV, + "uhadd16", // ARM_INS_UHADD16, + "uhadd8", // ARM_INS_UHADD8, + "uhasx", // ARM_INS_UHASX, + "uhsax", // ARM_INS_UHSAX, + "uhsub16", // ARM_INS_UHSUB16, + "uhsub8", // ARM_INS_UHSUB8, + "umaal", // ARM_INS_UMAAL, + "umlal", // ARM_INS_UMLAL, + "umull", // ARM_INS_UMULL, + "uqadd16", // ARM_INS_UQADD16, + "uqadd8", // ARM_INS_UQADD8, + "uqasx", // ARM_INS_UQASX, + "uqsax", // ARM_INS_UQSAX, + "uqsub16", // ARM_INS_UQSUB16, + "uqsub8", // ARM_INS_UQSUB8, + "usad8", // ARM_INS_USAD8, + "usada8", // ARM_INS_USADA8, + "usat", // ARM_INS_USAT, + "usat16", // ARM_INS_USAT16, + "usax", // ARM_INS_USAX, + "usub16", // ARM_INS_USUB16, + "usub8", // ARM_INS_USUB8, + "uxtab", // ARM_INS_UXTAB, + "uxtab16", // ARM_INS_UXTAB16, + "uxtah", // ARM_INS_UXTAH, + "uxtb", // ARM_INS_UXTB, + "uxtb16", // ARM_INS_UXTB16, + "uxth", // ARM_INS_UXTH, + "vaba", // ARM_INS_VABA, + "vabal", // ARM_INS_VABAL, + "vabd", // ARM_INS_VABD, + "vabdl", // ARM_INS_VABDL, + "vabs", // ARM_INS_VABS, + "vacge", // ARM_INS_VACGE, + "vacgt", // ARM_INS_VACGT, + "vacle", // ARM_INS_VACLE, + "vaclt", // ARM_INS_VACLT, + "vadd", // ARM_INS_VADD, + "vaddhn", // ARM_INS_VADDHN, + "vaddl", // ARM_INS_VADDL, + "vaddw", // ARM_INS_VADDW, + "vand", // ARM_INS_VAND, + "vbic", // ARM_INS_VBIC, + "vbif", // ARM_INS_VBIF, + "vbit", // ARM_INS_VBIT, + "vbsl", // ARM_INS_VBSL, + "vcadd", // ARM_INS_VCADD, + "vceq", // ARM_INS_VCEQ, + "vcge", // ARM_INS_VCGE, + "vcgt", // ARM_INS_VCGT, + "vcle", // ARM_INS_VCLE, + "vcls", // ARM_INS_VCLS, + "vclt", // ARM_INS_VCLT, + "vclz", // ARM_INS_VCLZ, + "vcmla", // ARM_INS_VCMLA, + "vcmp", // ARM_INS_VCMP, + "vcmpe", // ARM_INS_VCMPE, + "vcnt", // ARM_INS_VCNT, + "vcvt", // ARM_INS_VCVT, + "vcvta", // ARM_INS_VCVTA, + "vcvtb", // ARM_INS_VCVTB, + "vcvtm", // ARM_INS_VCVTM, + "vcvtn", // ARM_INS_VCVTN, + "vcvtp", // ARM_INS_VCVTP, + "vcvtr", // ARM_INS_VCVTR, + "vcvtt", // ARM_INS_VCVTT, + "vdiv", // ARM_INS_VDIV, + "vdup", // ARM_INS_VDUP, + "veor", // ARM_INS_VEOR, + "vext", // ARM_INS_VEXT, + "vfma", // ARM_INS_VFMA, + "vfms", // ARM_INS_VFMS, + "vfnma", // ARM_INS_VFNMA, + "vfnms", // ARM_INS_VFNMS, + "vhadd", // ARM_INS_VHADD, + "vhsub", // ARM_INS_VHSUB, + "vins", // ARM_INS_VINS, + "vjcvt", // ARM_INS_VJCVT, + "vld1", // ARM_INS_VLD1, + "vld2", // ARM_INS_VLD2, + "vld3", // ARM_INS_VLD3, + "vld4", // ARM_INS_VLD4, + "vldmdb", // ARM_INS_VLDMDB, + "vldmia", // ARM_INS_VLDMIA, + "vldr", // ARM_INS_VLDR, + "vlldm", // ARM_INS_VLLDM, + "vlstm", // ARM_INS_VLSTM, + "vmax", // ARM_INS_VMAX, + "vmaxnm", // ARM_INS_VMAXNM, + "vmin", // ARM_INS_VMIN, + "vminnm", // ARM_INS_VMINNM, + "vmla", // ARM_INS_VMLA, + "vmlal", // ARM_INS_VMLAL, + "vmls", // ARM_INS_VMLS, + "vmlsl", // ARM_INS_VMLSL, + "vmov", // ARM_INS_VMOV, + "vmovl", // ARM_INS_VMOVL, + "vmovn", // ARM_INS_VMOVN, + "vmovx", // ARM_INS_VMOVX, + "vmrs", // ARM_INS_VMRS, + "vmsr", // ARM_INS_VMSR, + "vmul", // ARM_INS_VMUL, + "vmull", // ARM_INS_VMULL, + "vmvn", // ARM_INS_VMVN, + "vneg", // ARM_INS_VNEG, + "vnmla", // ARM_INS_VNMLA, + "vnmls", // ARM_INS_VNMLS, + "vnmul", // ARM_INS_VNMUL, + "vorn", // ARM_INS_VORN, + "vorr", // ARM_INS_VORR, + "vpadal", // ARM_INS_VPADAL, + "vpadd", // ARM_INS_VPADD, + "vpaddl", // ARM_INS_VPADDL, + "vpmax", // ARM_INS_VPMAX, + "vpmin", // ARM_INS_VPMIN, + "vpop", // ARM_INS_VPOP, + "vpush", // ARM_INS_VPUSH, + "vqabs", // ARM_INS_VQABS, + "vqadd", // ARM_INS_VQADD, + "vqdmlal", // ARM_INS_VQDMLAL, + "vqdmlsl", // ARM_INS_VQDMLSL, + "vqdmulh", // ARM_INS_VQDMULH, + "vqdmull", // ARM_INS_VQDMULL, + "vqmovn", // ARM_INS_VQMOVN, + "vqmovun", // ARM_INS_VQMOVUN, + "vqneg", // ARM_INS_VQNEG, + "vqrdmlah", // ARM_INS_VQRDMLAH, + "vqrdmlsh", // ARM_INS_VQRDMLSH, + "vqrdmulh", // ARM_INS_VQRDMULH, + "vqrshl", // ARM_INS_VQRSHL, + "vqrshrn", // ARM_INS_VQRSHRN, + "vqrshrun", // ARM_INS_VQRSHRUN, + "vqshl", // ARM_INS_VQSHL, + "vqshlu", // ARM_INS_VQSHLU, + "vqshrn", // ARM_INS_VQSHRN, + "vqshrun", // ARM_INS_VQSHRUN, + "vqsub", // ARM_INS_VQSUB, + "vraddhn", // ARM_INS_VRADDHN, + "vrecpe", // ARM_INS_VRECPE, + "vrecps", // ARM_INS_VRECPS, + "vrev16", // ARM_INS_VREV16, + "vrev32", // ARM_INS_VREV32, + "vrev64", // ARM_INS_VREV64, + "vrhadd", // ARM_INS_VRHADD, + "vrinta", // ARM_INS_VRINTA, + "vrintm", // ARM_INS_VRINTM, + "vrintn", // ARM_INS_VRINTN, + "vrintp", // ARM_INS_VRINTP, + "vrintr", // ARM_INS_VRINTR, + "vrintx", // ARM_INS_VRINTX, + "vrintz", // ARM_INS_VRINTZ, + "vrshl", // ARM_INS_VRSHL, + "vrshr", // ARM_INS_VRSHR, + "vrshrn", // ARM_INS_VRSHRN, + "vrsqrte", // ARM_INS_VRSQRTE, + "vrsqrts", // ARM_INS_VRSQRTS, + "vrsra", // ARM_INS_VRSRA, + "vrsubhn", // ARM_INS_VRSUBHN, + "vsdot", // ARM_INS_VSDOT, + "vseleq", // ARM_INS_VSELEQ, + "vselge", // ARM_INS_VSELGE, + "vselgt", // ARM_INS_VSELGT, + "vselvs", // ARM_INS_VSELVS, + "vshl", // ARM_INS_VSHL, + "vshll", // ARM_INS_VSHLL, + "vshr", // ARM_INS_VSHR, + "vshrn", // ARM_INS_VSHRN, + "vsli", // ARM_INS_VSLI, + "vsqrt", // ARM_INS_VSQRT, + "vsra", // ARM_INS_VSRA, + "vsri", // ARM_INS_VSRI, + "vst1", // ARM_INS_VST1, + "vst2", // ARM_INS_VST2, + "vst3", // ARM_INS_VST3, + "vst4", // ARM_INS_VST4, + "vstmdb", // ARM_INS_VSTMDB, + "vstmia", // ARM_INS_VSTMIA, + "vstr", // ARM_INS_VSTR, + "vsub", // ARM_INS_VSUB, + "vsubhn", // ARM_INS_VSUBHN, + "vsubl", // ARM_INS_VSUBL, + "vsubw", // ARM_INS_VSUBW, + "vswp", // ARM_INS_VSWP, + "vtbl", // ARM_INS_VTBL, + "vtbx", // ARM_INS_VTBX, + "vtrn", // ARM_INS_VTRN, + "vtst", // ARM_INS_VTST, + "vudot", // ARM_INS_VUDOT, + "vuzp", // ARM_INS_VUZP, + "vzip", // ARM_INS_VZIP, + "wfe", // ARM_INS_WFE, + "wfi", // ARM_INS_WFI, + "yield", // ARM_INS_YIELD, diff --git a/arch/ARM/ARMMappingInsnOp.inc b/arch/ARM/ARMMappingInsnOp.inc index 767ab6aa97..f3b1af6b28 100644 --- a/arch/ARM/ARMMappingInsnOp.inc +++ b/arch/ARM/ARMMappingInsnOp.inc @@ -1,10729 +1,8119 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* This is auto-gen data for Capstone disassembly engine + * (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ +{/* ARM_ASRi, ARM_INS_ASR: asr */ + {0}}, -{ /* ARM_ASRi, ARM_INS_ASR: asr */ - { 0 } -}, + {/* ARM_ASRr, ARM_INS_ASR: asr */ + {0}}, -{ /* ARM_ASRr, ARM_INS_ASR: asr */ - { 0 } -}, + {/* ARM_ITasm, ARM_INS_IT: it */ + {0}}, -{ /* ARM_ITasm, ARM_INS_IT: it */ - { 0 } -}, + {/* ARM_LDRBT_POST, ARM_INS_LDRBT: ldrbt */ + {0}}, -{ /* ARM_LDRBT_POST, ARM_INS_LDRBT: ldrbt */ - { 0 } -}, + {/* ARM_LDRConstPool, ARM_INS_LDR: ldr */ + {0}}, -{ /* ARM_LDRConstPool, ARM_INS_LDR: ldr */ - { 0 } -}, + {/* ARM_LDRT_POST, ARM_INS_LDRT: ldrt */ + {0}}, -{ /* ARM_LDRT_POST, ARM_INS_LDRT: ldrt */ - { 0 } -}, + {/* ARM_LSLi, ARM_INS_LSL: lsl */ + {0}}, -{ /* ARM_LSLi, ARM_INS_LSL: lsl */ - { 0 } -}, + {/* ARM_LSLr, ARM_INS_LSL: lsl */ + {0}}, -{ /* ARM_LSLr, ARM_INS_LSL: lsl */ - { 0 } -}, + {/* ARM_LSRi, ARM_INS_LSR: lsr */ + {0}}, -{ /* ARM_LSRi, ARM_INS_LSR: lsr */ - { 0 } -}, + {/* ARM_LSRr, ARM_INS_LSR: lsr */ + {0}}, -{ /* ARM_LSRr, ARM_INS_LSR: lsr */ - { 0 } -}, + {/* ARM_RORi, ARM_INS_ROR: ror */ + {0}}, -{ /* ARM_RORi, ARM_INS_ROR: ror */ - { 0 } -}, + {/* ARM_RORr, ARM_INS_ROR: ror */ + {0}}, -{ /* ARM_RORr, ARM_INS_ROR: ror */ - { 0 } -}, + {/* ARM_RRXi, ARM_INS_RRX: rrx */ + {0}}, -{ /* ARM_RRXi, ARM_INS_RRX: rrx */ - { 0 } -}, + {/* ARM_STRBT_POST, ARM_INS_STRBT: strbt */ + {0}}, -{ /* ARM_STRBT_POST, ARM_INS_STRBT: strbt */ - { 0 } -}, + {/* ARM_STRT_POST, ARM_INS_STRT: strt */ + {0}}, -{ /* ARM_STRT_POST, ARM_INS_STRT: strt */ - { 0 } -}, + {/* ARM_VLD1LNdAsm_16, ARM_INS_VLD1: vld1 */ + {0}}, -{ /* ARM_VLD1LNdAsm_16, ARM_INS_VLD1: vld1 */ - { 0 } -}, + {/* ARM_VLD1LNdAsm_32, ARM_INS_VLD1: vld1 */ + {0}}, -{ /* ARM_VLD1LNdAsm_32, ARM_INS_VLD1: vld1 */ - { 0 } -}, + {/* ARM_VLD1LNdAsm_8, ARM_INS_VLD1: vld1 */ + {0}}, -{ /* ARM_VLD1LNdAsm_8, ARM_INS_VLD1: vld1 */ - { 0 } -}, + {/* ARM_VLD1LNdWB_fixed_Asm_16, ARM_INS_VLD1: vld1 */ + {0}}, -{ /* ARM_VLD1LNdWB_fixed_Asm_16, ARM_INS_VLD1: vld1 */ - { 0 } -}, + {/* ARM_VLD1LNdWB_fixed_Asm_32, ARM_INS_VLD1: vld1 */ + {0}}, -{ /* ARM_VLD1LNdWB_fixed_Asm_32, ARM_INS_VLD1: vld1 */ - { 0 } -}, + {/* ARM_VLD1LNdWB_fixed_Asm_8, ARM_INS_VLD1: vld1 */ + {0}}, -{ /* ARM_VLD1LNdWB_fixed_Asm_8, ARM_INS_VLD1: vld1 */ - { 0 } -}, + {/* ARM_VLD1LNdWB_register_Asm_16, ARM_INS_VLD1: vld1 */ + {0}}, -{ /* ARM_VLD1LNdWB_register_Asm_16, ARM_INS_VLD1: vld1 */ - { 0 } -}, + {/* ARM_VLD1LNdWB_register_Asm_32, ARM_INS_VLD1: vld1 */ + {0}}, -{ /* ARM_VLD1LNdWB_register_Asm_32, ARM_INS_VLD1: vld1 */ - { 0 } -}, + {/* ARM_VLD1LNdWB_register_Asm_8, ARM_INS_VLD1: vld1 */ + {0}}, -{ /* ARM_VLD1LNdWB_register_Asm_8, ARM_INS_VLD1: vld1 */ - { 0 } -}, + {/* ARM_VLD2LNdAsm_16, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNdAsm_16, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNdAsm_32, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNdAsm_32, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNdAsm_8, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNdAsm_8, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNdWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNdWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNdWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNdWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNdWB_fixed_Asm_8, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNdWB_fixed_Asm_8, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNdWB_register_Asm_16, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNdWB_register_Asm_16, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNdWB_register_Asm_32, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNdWB_register_Asm_32, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNdWB_register_Asm_8, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNdWB_register_Asm_8, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNqAsm_16, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNqAsm_16, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNqAsm_32, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNqAsm_32, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNqWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNqWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNqWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNqWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNqWB_register_Asm_16, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNqWB_register_Asm_16, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD2LNqWB_register_Asm_32, ARM_INS_VLD2: vld2 */ + {0}}, -{ /* ARM_VLD2LNqWB_register_Asm_32, ARM_INS_VLD2: vld2 */ - { 0 } -}, + {/* ARM_VLD3DUPdAsm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPdAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPdAsm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPdAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPdAsm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPdAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPqAsm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPqAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPqAsm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPqAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPqAsm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPqAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPqWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPqWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3DUPqWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3DUPqWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNdAsm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNdAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNdAsm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNdAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNdAsm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNdAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNqAsm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNqAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNqAsm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNqAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3LNqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3LNqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3dAsm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3dAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3dAsm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3dAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3dAsm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3dAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3dWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3dWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3dWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3dWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3dWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3dWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3dWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3dWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3dWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3dWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3dWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3dWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3qAsm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3qAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3qAsm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3qAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3qAsm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3qAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3qWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3qWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3qWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3qWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3qWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3qWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3qWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3qWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3qWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3qWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD3qWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + {0}}, -{ /* ARM_VLD3qWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } -}, + {/* ARM_VLD4DUPdAsm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPdAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPdAsm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPdAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPdAsm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPdAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPqAsm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPqAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPqAsm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPqAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPqAsm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPqAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPqWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPqWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4DUPqWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4DUPqWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNdAsm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNdAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNdAsm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNdAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNdAsm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNdAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNqAsm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNqAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNqAsm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNqAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4LNqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4LNqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4dAsm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4dAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4dAsm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4dAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4dAsm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4dAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4dWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4dWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4dWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4dWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4dWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4dWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4dWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4dWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4dWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4dWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4dWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4dWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4qAsm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4qAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4qAsm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4qAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4qAsm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4qAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4qWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4qWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4qWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4qWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4qWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4qWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4qWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4qWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4qWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4qWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VLD4qWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + {0}}, -{ /* ARM_VLD4qWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } -}, + {/* ARM_VST1LNdAsm_16, ARM_INS_VST1: vst1 */ + {0}}, -{ /* ARM_VST1LNdAsm_16, ARM_INS_VST1: vst1 */ - { 0 } -}, + {/* ARM_VST1LNdAsm_32, ARM_INS_VST1: vst1 */ + {0}}, -{ /* ARM_VST1LNdAsm_32, ARM_INS_VST1: vst1 */ - { 0 } -}, + {/* ARM_VST1LNdAsm_8, ARM_INS_VST1: vst1 */ + {0}}, -{ /* ARM_VST1LNdAsm_8, ARM_INS_VST1: vst1 */ - { 0 } -}, + {/* ARM_VST1LNdWB_fixed_Asm_16, ARM_INS_VST1: vst1 */ + {0}}, -{ /* ARM_VST1LNdWB_fixed_Asm_16, ARM_INS_VST1: vst1 */ - { 0 } -}, + {/* ARM_VST1LNdWB_fixed_Asm_32, ARM_INS_VST1: vst1 */ + {0}}, -{ /* ARM_VST1LNdWB_fixed_Asm_32, ARM_INS_VST1: vst1 */ - { 0 } -}, + {/* ARM_VST1LNdWB_fixed_Asm_8, ARM_INS_VST1: vst1 */ + {0}}, -{ /* ARM_VST1LNdWB_fixed_Asm_8, ARM_INS_VST1: vst1 */ - { 0 } -}, + {/* ARM_VST1LNdWB_register_Asm_16, ARM_INS_VST1: vst1 */ + {0}}, -{ /* ARM_VST1LNdWB_register_Asm_16, ARM_INS_VST1: vst1 */ - { 0 } -}, + {/* ARM_VST1LNdWB_register_Asm_32, ARM_INS_VST1: vst1 */ + {0}}, -{ /* ARM_VST1LNdWB_register_Asm_32, ARM_INS_VST1: vst1 */ - { 0 } -}, + {/* ARM_VST1LNdWB_register_Asm_8, ARM_INS_VST1: vst1 */ + {0}}, -{ /* ARM_VST1LNdWB_register_Asm_8, ARM_INS_VST1: vst1 */ - { 0 } -}, + {/* ARM_VST2LNdAsm_16, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNdAsm_16, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNdAsm_32, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNdAsm_32, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNdAsm_8, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNdAsm_8, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNdWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNdWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNdWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNdWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNdWB_fixed_Asm_8, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNdWB_fixed_Asm_8, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNdWB_register_Asm_16, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNdWB_register_Asm_16, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNdWB_register_Asm_32, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNdWB_register_Asm_32, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNdWB_register_Asm_8, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNdWB_register_Asm_8, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNqAsm_16, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNqAsm_16, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNqAsm_32, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNqAsm_32, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNqWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNqWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNqWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNqWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNqWB_register_Asm_16, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNqWB_register_Asm_16, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST2LNqWB_register_Asm_32, ARM_INS_VST2: vst2 */ + {0}}, -{ /* ARM_VST2LNqWB_register_Asm_32, ARM_INS_VST2: vst2 */ - { 0 } -}, + {/* ARM_VST3LNdAsm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNdAsm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNdAsm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNdAsm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNdAsm_8, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNdAsm_8, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNdWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNdWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNdWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNdWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNdWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNdWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNdWB_register_Asm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNdWB_register_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNdWB_register_Asm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNdWB_register_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNdWB_register_Asm_8, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNdWB_register_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNqAsm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNqAsm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNqAsm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNqAsm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNqWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNqWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNqWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNqWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNqWB_register_Asm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNqWB_register_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3LNqWB_register_Asm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3LNqWB_register_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3dAsm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3dAsm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3dAsm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3dAsm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3dAsm_8, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3dAsm_8, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3dWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3dWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3dWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3dWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3dWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3dWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3dWB_register_Asm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3dWB_register_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3dWB_register_Asm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3dWB_register_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3dWB_register_Asm_8, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3dWB_register_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3qAsm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3qAsm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3qAsm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3qAsm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3qAsm_8, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3qAsm_8, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3qWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3qWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3qWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3qWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3qWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3qWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3qWB_register_Asm_16, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3qWB_register_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3qWB_register_Asm_32, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3qWB_register_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST3qWB_register_Asm_8, ARM_INS_VST3: vst3 */ + {0}}, -{ /* ARM_VST3qWB_register_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } -}, + {/* ARM_VST4LNdAsm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNdAsm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNdAsm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNdAsm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNdAsm_8, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNdAsm_8, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNdWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNdWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNdWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNdWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNdWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNdWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNdWB_register_Asm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNdWB_register_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNdWB_register_Asm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNdWB_register_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNdWB_register_Asm_8, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNdWB_register_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNqAsm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNqAsm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNqAsm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNqAsm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNqWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNqWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNqWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNqWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNqWB_register_Asm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNqWB_register_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4LNqWB_register_Asm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4LNqWB_register_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4dAsm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4dAsm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4dAsm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4dAsm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4dAsm_8, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4dAsm_8, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4dWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4dWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4dWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4dWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4dWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4dWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4dWB_register_Asm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4dWB_register_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4dWB_register_Asm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4dWB_register_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4dWB_register_Asm_8, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4dWB_register_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4qAsm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4qAsm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4qAsm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4qAsm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4qAsm_8, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4qAsm_8, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4qWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4qWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4qWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4qWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4qWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4qWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4qWB_register_Asm_16, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4qWB_register_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4qWB_register_Asm_32, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4qWB_register_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_VST4qWB_register_Asm_8, ARM_INS_VST4: vst4 */ + {0}}, -{ /* ARM_VST4qWB_register_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } -}, + {/* ARM_t2LDRBpcrel, ARM_INS_LDRB: ldrb */ + {0}}, -{ /* ARM_t2LDRBpcrel, ARM_INS_LDRB: ldrb */ - { 0 } -}, + {/* ARM_t2LDRConstPool, ARM_INS_LDR: ldr */ + {0}}, -{ /* ARM_t2LDRConstPool, ARM_INS_LDR: ldr */ - { 0 } -}, + {/* ARM_t2LDRHpcrel, ARM_INS_LDRH: ldrh */ + {0}}, -{ /* ARM_t2LDRHpcrel, ARM_INS_LDRH: ldrh */ - { 0 } -}, + {/* ARM_t2LDRSBpcrel, ARM_INS_LDRSB: ldrsb */ + {0}}, -{ /* ARM_t2LDRSBpcrel, ARM_INS_LDRSB: ldrsb */ - { 0 } -}, + {/* ARM_t2LDRSHpcrel, ARM_INS_LDRSH: ldrsh */ + {0}}, -{ /* ARM_t2LDRSHpcrel, ARM_INS_LDRSH: ldrsh */ - { 0 } -}, + {/* ARM_t2LDRpcrel, ARM_INS_LDR: ldr */ + {0}}, -{ /* ARM_t2LDRpcrel, ARM_INS_LDR: ldr */ - { 0 } -}, + {/* ARM_t2MOVSsi, ARM_INS_MOVS: movs */ + {0}}, -{ /* ARM_t2MOVSsi, ARM_INS_MOVS: movs */ - { 0 } -}, + {/* ARM_t2MOVSsr, ARM_INS_MOVS: movs */ + {0}}, -{ /* ARM_t2MOVSsr, ARM_INS_MOVS: movs */ - { 0 } -}, + {/* ARM_t2MOVsi, ARM_INS_MOV: mov */ + {0}}, -{ /* ARM_t2MOVsi, ARM_INS_MOV: mov */ - { 0 } -}, + {/* ARM_t2MOVsr, ARM_INS_MOV: mov */ + {0}}, -{ /* ARM_t2MOVsr, ARM_INS_MOV: mov */ - { 0 } -}, + {/* ARM_tLDRConstPool, ARM_INS_LDR: ldr */ + {0}}, -{ /* ARM_tLDRConstPool, ARM_INS_LDR: ldr */ - { 0 } -}, + {/* ARM_ADCri, ARM_INS_ADC: adc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_ADCri, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ADCrr, ARM_INS_ADC: adc */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_ADCrr, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_ADCrsi, ARM_INS_ADC: adc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_ADCrsi, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ADCrsr, ARM_INS_ADC: adc */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_ADCrsr, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_ADDri, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_ADDri, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ADDrr, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_ADDrr, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_ADDrsi, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_ADDrsi, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ADDrsr, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_ADDrsr, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_ADR, ARM_INS_ADR: adr */ + {CS_AC_WRITE, 0}}, -{ /* ARM_ADR, ARM_INS_ADR: adr */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_AESD, ARM_INS_AESD: aesd */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_AESD, ARM_INS_AESD: aesd */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_AESE, ARM_INS_AESE: aese */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_AESE, ARM_INS_AESE: aese */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_AESIMC, ARM_INS_AESIMC: aesimc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_AESIMC, ARM_INS_AESIMC: aesimc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_AESMC, ARM_INS_AESMC: aesmc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_AESMC, ARM_INS_AESMC: aesmc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ANDri, ARM_INS_AND: and */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_ANDri, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ANDrr, ARM_INS_AND: and */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_ANDrr, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_ANDrsi, ARM_INS_AND: and */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_ANDrsi, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ANDrsr, ARM_INS_AND: and */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_ANDrsr, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_BFC, ARM_INS_BFC: bfc */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_BFC, ARM_INS_BFC: bfc */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_BFI, ARM_INS_BFI: bfi */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_BFI, ARM_INS_BFI: bfi */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_BICri, ARM_INS_AND: and */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_BICri, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_BICrr, ARM_INS_BIC: bic */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_BICrr, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_BICrsi, ARM_INS_BIC: bic */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_BICrsi, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_BICrsr, ARM_INS_BIC: bic */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_BICrsr, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_BKPT, ARM_INS_BKPT: bkpt */ + {0}}, -{ /* ARM_BKPT, ARM_INS_BKPT: bkpt */ - { 0 } -}, + {/* ARM_BL, ARM_INS_BL: bl */ + {0}}, -{ /* ARM_BL, ARM_INS_BL: bl */ - { 0 } -}, + {/* ARM_BLX, ARM_INS_BLX: blx */ + {CS_AC_READ, 0}}, -{ /* ARM_BLX, ARM_INS_BLX: blx */ - { CS_AC_READ, 0 } -}, + {/* ARM_BLX_pred, ARM_INS_BLX: blx */ + {CS_AC_READ, 0}}, -{ /* ARM_BLX_pred, ARM_INS_BLX: blx */ - { CS_AC_READ, 0 } -}, + {/* ARM_BLXi, ARM_INS_BLX: blx */ + {0}}, -{ /* ARM_BLXi, ARM_INS_BLX: blx */ - { 0 } -}, + {/* ARM_BL_pred, ARM_INS_BL: bl */ + {0}}, -{ /* ARM_BL_pred, ARM_INS_BL: bl */ - { 0 } -}, + {/* ARM_BX, ARM_INS_BX: bx */ + {CS_AC_READ, 0}}, -{ /* ARM_BX, ARM_INS_BX: bx */ - { CS_AC_READ, 0 } -}, + {/* ARM_BXJ, ARM_INS_BXJ: bxj */ + {CS_AC_READ, 0}}, -{ /* ARM_BXJ, ARM_INS_BXJ: bxj */ - { CS_AC_READ, 0 } -}, + {/* ARM_BX_RET, ARM_INS_BX: bx */ + {0}}, -{ /* ARM_BX_RET, ARM_INS_BX: bx */ - { 0 } -}, + {/* ARM_BX_pred, ARM_INS_BX: bx */ + {CS_AC_READ, 0}}, -{ /* ARM_BX_pred, ARM_INS_BX: bx */ - { CS_AC_READ, 0 } -}, + {/* ARM_Bcc, ARM_INS_B: b */ + {0}}, -{ /* ARM_Bcc, ARM_INS_B: b */ - { 0 } -}, + {/* ARM_CDP, ARM_INS_CDP: cdp */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_CDP, ARM_INS_CDP: cdp */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_CDP2, ARM_INS_CDP2: cdp2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_CDP2, ARM_INS_CDP2: cdp2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_CLREX, ARM_INS_CLREX: clrex */ + {0}}, -{ /* ARM_CLREX, ARM_INS_CLREX: clrex */ - { 0 } -}, + {/* ARM_CLZ, ARM_INS_CLZ: clz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_CLZ, ARM_INS_CLZ: clz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_CMNri, ARM_INS_CMN: cmn */ + {CS_AC_READ, 0}}, -{ /* ARM_CMNri, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } -}, + {/* ARM_CMNzrr, ARM_INS_CMN: cmn */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CMNzrr, ARM_INS_CMN: cmn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_CMNzrsi, ARM_INS_CMN: cmn */ + {CS_AC_READ, 0}}, -{ /* ARM_CMNzrsi, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } -}, + {/* ARM_CMNzrsr, ARM_INS_CMN: cmn */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CMNzrsr, ARM_INS_CMN: cmn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_CMPri, ARM_INS_CMN: cmn */ + {CS_AC_READ, 0}}, -{ /* ARM_CMPri, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } -}, + {/* ARM_CMPrr, ARM_INS_CMP: cmp */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CMPrr, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_CMPrsi, ARM_INS_CMP: cmp */ + {CS_AC_READ, 0}}, -{ /* ARM_CMPrsi, ARM_INS_CMP: cmp */ - { CS_AC_READ, 0 } -}, + {/* ARM_CMPrsr, ARM_INS_CMP: cmp */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CMPrsr, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_CPS1p, ARM_INS_CPS: cps */ + {0}}, -{ /* ARM_CPS1p, ARM_INS_CPS: cps */ - { 0 } -}, + {/* ARM_CPS2p, ARM_INS_CPS: cps */ + {0}}, -{ /* ARM_CPS2p, ARM_INS_CPS: cps */ - { 0 } -}, + {/* ARM_CPS3p, ARM_INS_CPS: cps */ + {0}}, -{ /* ARM_CPS3p, ARM_INS_CPS: cps */ - { 0 } -}, + {/* ARM_CRC32B, ARM_INS_CRC32B: crc32b */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CRC32B, ARM_INS_CRC32B: crc32b */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_CRC32H, ARM_INS_CRC32H: crc32h */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CRC32H, ARM_INS_CRC32H: crc32h */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_CRC32W, ARM_INS_CRC32W: crc32w */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_CRC32W, ARM_INS_CRC32W: crc32w */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_DBG, ARM_INS_DBG: dbg */ + {0}}, -{ /* ARM_DBG, ARM_INS_DBG: dbg */ - { 0 } -}, + {/* ARM_DMB, ARM_INS_DMB: dmb */ + {0}}, -{ /* ARM_DMB, ARM_INS_DMB: dmb */ - { 0 } -}, + {/* ARM_DSB, ARM_INS_DFB: dfb */ + {0}}, -{ /* ARM_DSB, ARM_INS_DFB: dfb */ - { 0 } -}, + {/* ARM_EORri, ARM_INS_EOR: eor */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_EORri, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_EORrr, ARM_INS_EOR: eor */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_EORrr, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_EORrsi, ARM_INS_EOR: eor */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_EORrsi, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_EORrsr, ARM_INS_EOR: eor */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_EORrsr, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_ERET, ARM_INS_ERET: eret */ + {0}}, -{ /* ARM_ERET, ARM_INS_ERET: eret */ - { 0 } -}, + {/* ARM_FCONSTD, ARM_INS_FCONSTD: fconstd */ + {CS_AC_WRITE, 0}}, -{ /* ARM_FCONSTD, ARM_INS_FCONSTD: fconstd */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_FCONSTH, ARM_INS_VMOV: vmov */ + {0}}, -{ /* ARM_FCONSTH, ARM_INS_VMOV: vmov */ - { 0 } -}, + {/* ARM_FCONSTS, ARM_INS_FCONSTS: fconsts */ + {CS_AC_WRITE, 0}}, -{ /* ARM_FCONSTS, ARM_INS_FCONSTS: fconsts */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax */ + {CS_AC_READ, 0}}, -{ /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax */ - { CS_AC_READ, 0 } -}, + {/* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_FMSTAT, ARM_INS_FMSTAT: fmstat */ + {0}}, -{ /* ARM_FMSTAT, ARM_INS_FMSTAT: fmstat */ - { 0 } -}, + {/* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax */ + {CS_AC_READ, 0}}, -{ /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax */ - { CS_AC_READ, 0 } -}, + {/* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_HINT, ARM_INS_CSDB: csdb */ + {0}}, -{ /* ARM_HINT, ARM_INS_CSDB: csdb */ - { 0 } -}, + {/* ARM_HLT, ARM_INS_HLT: hlt */ + {0}}, -{ /* ARM_HLT, ARM_INS_HLT: hlt */ - { 0 } -}, + {/* ARM_HVC, ARM_INS_HVC: hvc */ + {0}}, -{ /* ARM_HVC, ARM_INS_HVC: hvc */ - { 0 } -}, + {/* ARM_ISB, ARM_INS_ISB: isb */ + {0}}, -{ /* ARM_ISB, ARM_INS_ISB: isb */ - { 0 } -}, + {/* ARM_LDA, ARM_INS_LDA: lda */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDA, ARM_INS_LDA: lda */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDAB, ARM_INS_LDAB: ldab */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDAB, ARM_INS_LDAB: ldab */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDAEX, ARM_INS_LDAEX: ldaex */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDAEX, ARM_INS_LDAEX: ldaex */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDAH, ARM_INS_LDAH: ldah */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDAH, ARM_INS_LDAH: ldah */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDCL_POST, ARM_INS_LDCL: ldcl */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC_OFFSET, ARM_INS_LDC: ldc */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC_OPTION, ARM_INS_LDC: ldc */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC_OPTION, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC_POST, ARM_INS_LDC: ldc */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC_POST, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDC_PRE, ARM_INS_LDC: ldc */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDC_PRE, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDMDA, ARM_INS_LDMDA: ldmda */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_LDMDA, ARM_INS_LDMDA: ldmda */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_LDMDB, ARM_INS_LDMDB: ldmdb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_LDMIA, ARM_INS_LDM: ldm */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_LDMIA, ARM_INS_LDM: ldm */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_LDMIA_UPD, ARM_INS_LDM: ldm */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_LDMIB, ARM_INS_LDMIB: ldmib */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_LDMIB, ARM_INS_LDMIB: ldmib */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRBi12, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRBi12, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRBrs, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRBrs, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRD, ARM_INS_LDRD: ldrd */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_LDRD, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_LDRD_POST, ARM_INS_LDRD: ldrd */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_LDREX, ARM_INS_LDREX: ldrex */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDREX, ARM_INS_LDREX: ldrex */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDREXB, ARM_INS_LDREXB: ldrexb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDREXD, ARM_INS_LDREXD: ldrexd */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDREXH, ARM_INS_LDREXH: ldrexh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRH, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, 0}}, -{ /* ARM_LDRH, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_LDRHTi, ARM_INS_LDRHT: ldrht */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRHTr, ARM_INS_LDRHT: ldrht */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDRH_POST, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, 0}}, -{ /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_LDRSB, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_LDRSH, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, 0}}, -{ /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, 0}}, -{ /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDR_POST_REG, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt $addr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRi12, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRi12, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_LDRrs, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_LDRrs, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_MCR, ARM_INS_MCR: mcr */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_MCR, ARM_INS_MCR: mcr */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_MCR2, ARM_INS_MCR2: mcr2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_MCR2, ARM_INS_MCR2: mcr2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_MCRR, ARM_INS_MCRR: mcrr */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_MCRR, ARM_INS_MCRR: mcrr */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_MLA, ARM_INS_MLA: mla */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_MLA, ARM_INS_MLA: mla */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_MLS, ARM_INS_MLS: mls */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_MLS, ARM_INS_MLS: mls */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_MOVPCLR, ARM_INS_MOV: mov */ + {0}}, -{ /* ARM_MOVPCLR, ARM_INS_MOV: mov */ - { 0 } -}, + {/* ARM_MOVTi16, ARM_INS_MOVT: movt */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_MOVTi16, ARM_INS_MOVT: movt */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_MOVi, ARM_INS_MOV: mov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_MOVi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_MOVi16, ARM_INS_MOV: mov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_MOVi16, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_MOVr, ARM_INS_MOV: mov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_MOVr, ARM_INS_MOV: mov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_MOVr_TC, ARM_INS_MOV: mov */ + {0}}, -{ /* ARM_MOVr_TC, ARM_INS_MOV: mov */ - { 0 } -}, + {/* ARM_MOVsi, ARM_INS_MOV: mov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_MOVsi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_MOVsr, ARM_INS_MOV: mov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_MOVsr, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_MRC, ARM_INS_MRC: mrc */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_MRC, ARM_INS_MRC: mrc */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_MRC2, ARM_INS_MRC2: mrc2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_MRC2, ARM_INS_MRC2: mrc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_MRRC, ARM_INS_MRRC: mrrc */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_MRRC, ARM_INS_MRRC: mrrc */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_MRS, ARM_INS_MRS: mrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_MRS, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_MRSbanked, ARM_INS_MRS: mrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_MRSbanked, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_MRSsys, ARM_INS_MRS: mrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_MRSsys, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_MSR, ARM_INS_MSR: msr */ + {CS_AC_READ, 0}}, -{ /* ARM_MSR, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } -}, + {/* ARM_MSRbanked, ARM_INS_MSR: msr */ + {CS_AC_READ, 0}}, -{ /* ARM_MSRbanked, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } -}, + {/* ARM_MSRi, ARM_INS_MSR: msr */ + {0}}, -{ /* ARM_MSRi, ARM_INS_MSR: msr */ - { 0 } -}, + {/* ARM_MUL, ARM_INS_MUL: mul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_MUL, ARM_INS_MUL: mul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_MVNi, ARM_INS_MOV: mov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_MVNi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_MVNr, ARM_INS_MVN: mvn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_MVNr, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_MVNsi, ARM_INS_MVN: mvn */ + {CS_AC_WRITE, 0}}, -{ /* ARM_MVNsi, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_MVNsr, ARM_INS_MVN: mvn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_MVNsr, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ORRri, ARM_INS_ORR: orr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_ORRri, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ORRrr, ARM_INS_ORR: orr */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_ORRrr, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_ORRrsi, ARM_INS_ORR: orr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_ORRrsi, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_ORRrsr, ARM_INS_ORR: orr */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_ORRrsr, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_PKHBT, ARM_INS_PKHBT: pkhbt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_PKHTB, ARM_INS_PKHTB: pkhtb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_PLDWi12, ARM_INS_PLDW: pldw */ + {CS_AC_READ, 0}}, -{ /* ARM_PLDWi12, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } -}, + {/* ARM_PLDWrs, ARM_INS_PLDW: pldw */ + {CS_AC_READ, 0}}, -{ /* ARM_PLDWrs, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } -}, + {/* ARM_PLDi12, ARM_INS_PLD: pld */ + {CS_AC_READ, 0}}, -{ /* ARM_PLDi12, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } -}, + {/* ARM_PLDrs, ARM_INS_PLD: pld */ + {CS_AC_READ, 0}}, -{ /* ARM_PLDrs, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } -}, + {/* ARM_PLIi12, ARM_INS_PLI: pli */ + {CS_AC_READ, 0}}, -{ /* ARM_PLIi12, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } -}, + {/* ARM_PLIrs, ARM_INS_PLI: pli */ + {CS_AC_READ, 0}}, -{ /* ARM_PLIrs, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } -}, + {/* ARM_QADD, ARM_INS_QADD: qadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QADD, ARM_INS_QADD: qadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_QADD16, ARM_INS_QADD16: qadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QADD16, ARM_INS_QADD16: qadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_QADD8, ARM_INS_QADD8: qadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QADD8, ARM_INS_QADD8: qadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_QASX, ARM_INS_QASX: qasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QASX, ARM_INS_QASX: qasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_QDADD, ARM_INS_QDADD: qdadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QDADD, ARM_INS_QDADD: qdadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_QDSUB, ARM_INS_QDSUB: qdsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QDSUB, ARM_INS_QDSUB: qdsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_QSAX, ARM_INS_QSAX: qsax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QSAX, ARM_INS_QSAX: qsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_QSUB, ARM_INS_QSUB: qsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QSUB, ARM_INS_QSUB: qsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_QSUB16, ARM_INS_QSUB16: qsub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QSUB16, ARM_INS_QSUB16: qsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_QSUB8, ARM_INS_QSUB8: qsub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_QSUB8, ARM_INS_QSUB8: qsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_RBIT, ARM_INS_RBIT: rbit */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_RBIT, ARM_INS_RBIT: rbit */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_REV, ARM_INS_REV: rev */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_REV, ARM_INS_REV: rev */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_REV16, ARM_INS_REV16: rev16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_REV16, ARM_INS_REV16: rev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_REVSH, ARM_INS_REVSH: revsh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_REVSH, ARM_INS_REVSH: revsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_RFEDA, ARM_INS_RFEDA: rfeda */ + {CS_AC_READ, 0}}, -{ /* ARM_RFEDA, ARM_INS_RFEDA: rfeda */ - { CS_AC_READ, 0 } -}, + {/* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda */ + {CS_AC_READ, 0}}, -{ /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda */ - { CS_AC_READ, 0 } -}, + {/* ARM_RFEDB, ARM_INS_RFEDB: rfedb */ + {CS_AC_READ, 0}}, -{ /* ARM_RFEDB, ARM_INS_RFEDB: rfedb */ - { CS_AC_READ, 0 } -}, + {/* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb */ + {CS_AC_READ, 0}}, -{ /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb */ - { CS_AC_READ, 0 } -}, + {/* ARM_RFEIA, ARM_INS_RFEIA: rfeia */ + {CS_AC_READ, 0}}, -{ /* ARM_RFEIA, ARM_INS_RFEIA: rfeia */ - { CS_AC_READ, 0 } -}, + {/* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia */ + {CS_AC_READ, 0}}, -{ /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia */ - { CS_AC_READ, 0 } -}, + {/* ARM_RFEIB, ARM_INS_RFEIB: rfeib */ + {CS_AC_READ, 0}}, -{ /* ARM_RFEIB, ARM_INS_RFEIB: rfeib */ - { CS_AC_READ, 0 } -}, + {/* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib */ + {CS_AC_READ, 0}}, -{ /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib */ - { CS_AC_READ, 0 } -}, + {/* ARM_RSBri, ARM_INS_NEG: neg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_RSBri, ARM_INS_NEG: neg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_RSBrr, ARM_INS_RSB: rsb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_RSBrr, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_RSBrsi, ARM_INS_RSB: rsb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_RSBrsi, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_RSBrsr, ARM_INS_RSB: rsb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_RSBrsr, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_RSCri, ARM_INS_RSC: rsc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_RSCri, ARM_INS_RSC: rsc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_RSCrr, ARM_INS_RSC: rsc */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_RSCrr, ARM_INS_RSC: rsc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_RSCrsi, ARM_INS_RSC: rsc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_RSCrsi, ARM_INS_RSC: rsc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_RSCrsr, ARM_INS_RSC: rsc */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_RSCrsr, ARM_INS_RSC: rsc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SADD16, ARM_INS_SADD16: sadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SADD16, ARM_INS_SADD16: sadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SADD8, ARM_INS_SADD8: sadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SADD8, ARM_INS_SADD8: sadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SASX, ARM_INS_SASX: sasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SASX, ARM_INS_SASX: sasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SBCri, ARM_INS_ADC: adc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SBCri, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SBCrr, ARM_INS_SBC: sbc */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SBCrr, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SBCrsi, ARM_INS_SBC: sbc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SBCrsi, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SBCrsr, ARM_INS_SBC: sbc */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SBCrsr, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SBFX, ARM_INS_SBFX: sbfx */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SBFX, ARM_INS_SBFX: sbfx */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SDIV, ARM_INS_SDIV: sdiv */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SDIV, ARM_INS_SDIV: sdiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SEL, ARM_INS_SEL: sel */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SEL, ARM_INS_SEL: sel */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SETEND, ARM_INS_SETEND: setend */ + {0}}, -{ /* ARM_SETEND, ARM_INS_SETEND: setend */ - { 0 } -}, + {/* ARM_SETPAN, ARM_INS_SETPAN: setpan */ + {0}}, -{ /* ARM_SETPAN, ARM_INS_SETPAN: setpan */ - { 0 } -}, + {/* ARM_SHA1C, ARM_INS_SHA1C: sha1c */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHA1C, ARM_INS_SHA1C: sha1c */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHA1H, ARM_INS_SHA1H: sha1h */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SHA1H, ARM_INS_SHA1H: sha1h */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SHA1M, ARM_INS_SHA1M: sha1m */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHA1M, ARM_INS_SHA1M: sha1m */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHA1P, ARM_INS_SHA1P: sha1p */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHA1P, ARM_INS_SHA1P: sha1p */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0 */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1 */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SHA256H, ARM_INS_SHA256H: sha256h */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHA256H, ARM_INS_SHA256H: sha256h */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2 */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0 */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1 */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHADD16, ARM_INS_SHADD16: shadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHADD16, ARM_INS_SHADD16: shadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHADD8, ARM_INS_SHADD8: shadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHADD8, ARM_INS_SHADD8: shadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHASX, ARM_INS_SHASX: shasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHASX, ARM_INS_SHASX: shasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHSAX, ARM_INS_SHSAX: shsax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHSAX, ARM_INS_SHSAX: shsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMC, ARM_INS_SMC: smc */ + {0}}, -{ /* ARM_SMC, ARM_INS_SMC: smc */ - { 0 } -}, + {/* ARM_SMLABB, ARM_INS_SMLABB: smlabb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLABB, ARM_INS_SMLABB: smlabb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLABT, ARM_INS_SMLABT: smlabt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLABT, ARM_INS_SMLABT: smlabt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLAD, ARM_INS_SMLAD: smlad */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLAD, ARM_INS_SMLAD: smlad */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLADX, ARM_INS_SMLADX: smladx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLADX, ARM_INS_SMLADX: smladx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLAL, ARM_INS_SMLAL: smlal */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLAL, ARM_INS_SMLAL: smlal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLALD, ARM_INS_SMLALD: smlald */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLALD, ARM_INS_SMLALD: smlald */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLATB, ARM_INS_SMLATB: smlatb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLATB, ARM_INS_SMLATB: smlatb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLATT, ARM_INS_SMLATT: smlatt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLATT, ARM_INS_SMLATT: smlatt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLSD, ARM_INS_SMLSD: smlsd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLSD, ARM_INS_SMLSD: smlsd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMMLA, ARM_INS_SMMLA: smmla */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMMLA, ARM_INS_SMMLA: smmla */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMMLS, ARM_INS_SMMLS: smmls */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMMLS, ARM_INS_SMMLS: smmls */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMMUL, ARM_INS_SMMUL: smmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMMUL, ARM_INS_SMMUL: smmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMMULR, ARM_INS_SMMULR: smmulr */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMMULR, ARM_INS_SMMULR: smmulr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMUAD, ARM_INS_SMUAD: smuad */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMUAD, ARM_INS_SMUAD: smuad */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMUADX, ARM_INS_SMUADX: smuadx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMUADX, ARM_INS_SMUADX: smuadx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMULBB, ARM_INS_SMULBB: smulbb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMULBB, ARM_INS_SMULBB: smulbb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMULBT, ARM_INS_SMULBT: smulbt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMULBT, ARM_INS_SMULBT: smulbt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMULL, ARM_INS_SMULL: smull */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMULL, ARM_INS_SMULL: smull */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMULTB, ARM_INS_SMULTB: smultb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMULTB, ARM_INS_SMULTB: smultb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMULTT, ARM_INS_SMULTT: smultt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMULTT, ARM_INS_SMULTT: smultt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMULWB, ARM_INS_SMULWB: smulwb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMULWB, ARM_INS_SMULWB: smulwb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMULWT, ARM_INS_SMULWT: smulwt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMULWT, ARM_INS_SMULWT: smulwt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMUSD, ARM_INS_SMUSD: smusd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMUSD, ARM_INS_SMUSD: smusd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SRSDA, ARM_INS_SRSDA: srsda */ + {0}}, -{ /* ARM_SRSDA, ARM_INS_SRSDA: srsda */ - { 0 } -}, + {/* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda */ + {0}}, -{ /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda */ - { 0 } -}, + {/* ARM_SRSDB, ARM_INS_SRSDB: srsdb */ + {0}}, -{ /* ARM_SRSDB, ARM_INS_SRSDB: srsdb */ - { 0 } -}, + {/* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb */ + {0}}, -{ /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb */ - { 0 } -}, + {/* ARM_SRSIA, ARM_INS_SRSIA: srsia */ + {0}}, -{ /* ARM_SRSIA, ARM_INS_SRSIA: srsia */ - { 0 } -}, + {/* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia */ + {0}}, -{ /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia */ - { 0 } -}, + {/* ARM_SRSIB, ARM_INS_SRSIB: srsib */ + {0}}, -{ /* ARM_SRSIB, ARM_INS_SRSIB: srsib */ - { 0 } -}, + {/* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib */ + {0}}, -{ /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib */ - { 0 } -}, + {/* ARM_SSAT, ARM_INS_SSAT: ssat */ + {CS_AC_WRITE, 0}}, -{ /* ARM_SSAT, ARM_INS_SSAT: ssat */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_SSAT16, ARM_INS_SSAT16: ssat16 */ + {CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0}}, -{ /* ARM_SSAT16, ARM_INS_SSAT16: ssat16 */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } -}, + {/* ARM_SSAX, ARM_INS_SSAX: ssax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SSAX, ARM_INS_SSAX: ssax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SSUB16, ARM_INS_SSUB16: ssub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SSUB16, ARM_INS_SSUB16: ssub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SSUB8, ARM_INS_SSUB8: ssub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SSUB8, ARM_INS_SSUB8: ssub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC2L_POST, ARM_INS_STC2L: stc2l */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC2_OPTION, ARM_INS_STC2: stc2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC2_POST, ARM_INS_STC2: stc2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC2_POST, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC2_PRE, ARM_INS_STC2: stc2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC2_PRE, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STCL_OFFSET, ARM_INS_STCL: stcl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STCL_OPTION, ARM_INS_STCL: stcl */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STCL_OPTION, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STCL_POST, ARM_INS_STCL: stcl */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STCL_POST, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STCL_PRE, ARM_INS_STCL: stcl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STCL_PRE, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC_OFFSET, ARM_INS_STC: stc */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC_OFFSET, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC_OPTION, ARM_INS_STC: stc */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC_OPTION, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC_POST, ARM_INS_STC: stc */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC_POST, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STC_PRE, ARM_INS_STC: stc */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STC_PRE, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STL, ARM_INS_STL: stl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STL, ARM_INS_STL: stl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STLB, ARM_INS_STLB: stlb */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STLB, ARM_INS_STLB: stlb */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STLEX, ARM_INS_STLEX: stlex */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STLEX, ARM_INS_STLEX: stlex */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STLEXB, ARM_INS_STLEXB: stlexb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STLEXB, ARM_INS_STLEXB: stlexb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STLEXD, ARM_INS_STLEXD: stlexd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STLEXD, ARM_INS_STLEXD: stlexd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STLEXH, ARM_INS_STLEXH: stlexh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STLEXH, ARM_INS_STLEXH: stlexh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STLH, ARM_INS_STLH: stlh */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STLH, ARM_INS_STLH: stlh */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STMDA, ARM_INS_STMDA: stmda */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STMDA, ARM_INS_STMDA: stmda */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STMDA_UPD, ARM_INS_STMDA: stmda */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_STMDB, ARM_INS_STMDB: stmdb */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STMDB, ARM_INS_STMDB: stmdb */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STMDB_UPD, ARM_INS_PUSH: push */ + {CS_AC_READ, 0}}, -{ /* ARM_STMDB_UPD, ARM_INS_PUSH: push */ - { CS_AC_READ, 0 } -}, + {/* ARM_STMIA, ARM_INS_STM: stm */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STMIA, ARM_INS_STM: stm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STMIA_UPD, ARM_INS_STM: stm */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_STMIA_UPD, ARM_INS_STM: stm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_STMIB, ARM_INS_STMIB: stmib */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STMIB, ARM_INS_STMIB: stmib */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STMIB_UPD, ARM_INS_STMIB: stmib */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STRB_POST_IMM, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRB_POST_REG, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRB_POST_REG, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRB_PRE_REG, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRBi12, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRBi12, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRBrs, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRBrs, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRD, ARM_INS_STRD: strd */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STRD, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STRD_POST, ARM_INS_STRD: strd */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STRD_POST, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STRD_PRE, ARM_INS_STRD: strd */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STRD_PRE, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STREX, ARM_INS_STREX: strex */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STREX, ARM_INS_STREX: strex */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STREXB, ARM_INS_STREXB: strexb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STREXB, ARM_INS_STREXB: strexb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STREXD, ARM_INS_STREXD: strexd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STREXD, ARM_INS_STREXD: strexd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STREXH, ARM_INS_STREXH: strexh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STREXH, ARM_INS_STREXH: strexh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STRH, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRH, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRHTi, ARM_INS_STRHT: strht */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STRHTi, ARM_INS_STRHT: strht */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STRHTr, ARM_INS_STRHT: strht */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STRHTr, ARM_INS_STRHT: strht */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STRH_POST, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_STRH_POST, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_STRH_PRE, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRH_PRE, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRT_POST_IMM, ARM_INS_STRT: strt */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRT_POST_REG, ARM_INS_STRT: strt */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRT_POST_REG, ARM_INS_STRT: strt */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STR_POST_IMM, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STR_POST_IMM, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STR_POST_REG, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STR_POST_REG, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STR_PRE_IMM, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STR_PRE_IMM, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STR_PRE_REG, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STR_PRE_REG, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRi12, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_STRi12, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_STRrs, ARM_INS_STR: str */ + {CS_AC_READ, 0}}, -{ /* ARM_STRrs, ARM_INS_STR: str */ - { CS_AC_READ, 0 } -}, + {/* ARM_SUBri, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SUBri, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SUBrr, ARM_INS_SUB: sub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SUBrr, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SUBrsi, ARM_INS_SUB: sub */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SUBrsi, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SUBrsr, ARM_INS_SUB: sub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SUBrsr, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SVC, ARM_INS_SVC: svc */ + {0}}, -{ /* ARM_SVC, ARM_INS_SVC: svc */ - { 0 } -}, + {/* ARM_SWP, ARM_INS_SWP: swp */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SWP, ARM_INS_SWP: swp */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SWPB, ARM_INS_SWPB: swpb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_SWPB, ARM_INS_SWPB: swpb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_SXTAB, ARM_INS_SXTAB: sxtab */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SXTAB, ARM_INS_SXTAB: sxtab */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SXTAH, ARM_INS_SXTAH: sxtah */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_SXTAH, ARM_INS_SXTAH: sxtah */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_SXTB, ARM_INS_SXTB: sxtb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_SXTB, ARM_INS_SXTB: sxtb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_SXTB16, ARM_INS_SXTB16: sxtb16 */ + {CS_AC_WRITE, 0}}, -{ /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16 */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_SXTH, ARM_INS_SXTH: sxth */ + {CS_AC_WRITE, 0}}, -{ /* ARM_SXTH, ARM_INS_SXTH: sxth */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_TEQri, ARM_INS_TEQ: teq */ + {CS_AC_READ, 0}}, -{ /* ARM_TEQri, ARM_INS_TEQ: teq */ - { CS_AC_READ, 0 } -}, + {/* ARM_TEQrr, ARM_INS_TEQ: teq */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_TEQrr, ARM_INS_TEQ: teq */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_TEQrsi, ARM_INS_TEQ: teq */ + {CS_AC_READ, 0}}, -{ /* ARM_TEQrsi, ARM_INS_TEQ: teq */ - { CS_AC_READ, 0 } -}, + {/* ARM_TEQrsr, ARM_INS_TEQ: teq */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_TEQrsr, ARM_INS_TEQ: teq */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_TRAP, ARM_INS_TRAP: trap */ + {0}}, -{ /* ARM_TRAP, ARM_INS_TRAP: trap */ - { 0 } -}, + {/* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ + {0}}, -{ /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ - { 0 } -}, + {/* ARM_TSB, ARM_INS_TSB: tsb */ + {0}}, -{ /* ARM_TSB, ARM_INS_TSB: tsb */ - { 0 } -}, + {/* ARM_TSTri, ARM_INS_TST: tst */ + {CS_AC_READ, 0}}, -{ /* ARM_TSTri, ARM_INS_TST: tst */ - { CS_AC_READ, 0 } -}, + {/* ARM_TSTrr, ARM_INS_TST: tst */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_TSTrr, ARM_INS_TST: tst */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_TSTrsi, ARM_INS_TST: tst */ + {CS_AC_READ, 0}}, -{ /* ARM_TSTrsi, ARM_INS_TST: tst */ - { CS_AC_READ, 0 } -}, + {/* ARM_TSTrsr, ARM_INS_TST: tst */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_TSTrsr, ARM_INS_TST: tst */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UADD16, ARM_INS_UADD16: uadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UADD16, ARM_INS_UADD16: uadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UADD8, ARM_INS_UADD8: uadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UADD8, ARM_INS_UADD8: uadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UASX, ARM_INS_UASX: uasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UASX, ARM_INS_UASX: uasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UBFX, ARM_INS_UBFX: ubfx */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_UBFX, ARM_INS_UBFX: ubfx */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_UDF, ARM_INS_UDF: udf */ + {0}}, -{ /* ARM_UDF, ARM_INS_UDF: udf */ - { 0 } -}, + {/* ARM_UDIV, ARM_INS_UDIV: udiv */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UDIV, ARM_INS_UDIV: udiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UHADD16, ARM_INS_UHADD16: uhadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UHADD8, ARM_INS_UHADD8: uhadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UHASX, ARM_INS_UHASX: uhasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UHASX, ARM_INS_UHASX: uhasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UHSAX, ARM_INS_UHSAX: uhsax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UHSAX, ARM_INS_UHSAX: uhsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UMAAL, ARM_INS_UMAAL: umaal */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UMAAL, ARM_INS_UMAAL: umaal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UMLAL, ARM_INS_UMLAL: umlal */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UMLAL, ARM_INS_UMLAL: umlal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UMULL, ARM_INS_UMULL: umull */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UMULL, ARM_INS_UMULL: umull */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UQADD16, ARM_INS_UQADD16: uqadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UQADD8, ARM_INS_UQADD8: uqadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UQASX, ARM_INS_UQASX: uqasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UQASX, ARM_INS_UQASX: uqasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UQSAX, ARM_INS_UQSAX: uqsax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UQSAX, ARM_INS_UQSAX: uqsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_USAD8, ARM_INS_USAD8: usad8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_USAD8, ARM_INS_USAD8: usad8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_USADA8, ARM_INS_USADA8: usada8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_USADA8, ARM_INS_USADA8: usada8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_USAT, ARM_INS_USAT: usat */ + {CS_AC_WRITE, 0}}, -{ /* ARM_USAT, ARM_INS_USAT: usat */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_USAT16, ARM_INS_USAT16: usat16 */ + {CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0}}, -{ /* ARM_USAT16, ARM_INS_USAT16: usat16 */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } -}, + {/* ARM_USAX, ARM_INS_USAX: usax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_USAX, ARM_INS_USAX: usax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_USUB16, ARM_INS_USUB16: usub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_USUB16, ARM_INS_USUB16: usub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_USUB8, ARM_INS_USUB8: usub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_USUB8, ARM_INS_USUB8: usub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_UXTAB, ARM_INS_UXTAB: uxtab */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_UXTAB, ARM_INS_UXTAB: uxtab */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_UXTAH, ARM_INS_UXTAH: uxtah */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_UXTAH, ARM_INS_UXTAH: uxtah */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_UXTB, ARM_INS_UXTB: uxtb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_UXTB, ARM_INS_UXTB: uxtb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_UXTB16, ARM_INS_UXTB16: uxtb16 */ + {CS_AC_WRITE, 0}}, -{ /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16 */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_UXTH, ARM_INS_UXTH: uxth */ + {CS_AC_WRITE, 0}}, -{ /* ARM_UXTH, ARM_INS_UXTH: uxth */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VABALsv2i64, ARM_INS_VABAL: vabal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABALsv4i32, ARM_INS_VABAL: vabal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABALsv8i16, ARM_INS_VABAL: vabal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABALuv2i64, ARM_INS_VABAL: vabal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABALuv4i32, ARM_INS_VABAL: vabal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABALuv8i16, ARM_INS_VABAL: vabal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAsv16i8, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAsv16i8, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAsv2i32, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAsv2i32, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAsv4i16, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAsv4i16, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAsv4i32, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAsv4i32, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAsv8i16, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAsv8i16, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAsv8i8, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAsv8i8, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAuv16i8, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAuv16i8, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAuv2i32, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAuv2i32, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAuv4i16, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAuv4i16, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAuv4i32, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAuv4i32, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAuv8i16, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAuv8i16, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABAuv8i8, ARM_INS_VABA: vaba */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABAuv8i8, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDfd, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDfd, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDfq, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDfq, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDhd, ARM_INS_VABD: vabd */ + {0}}, -{ /* ARM_VABDhd, ARM_INS_VABD: vabd */ - { 0 } -}, + {/* ARM_VABDhq, ARM_INS_VABD: vabd */ + {0}}, -{ /* ARM_VABDhq, ARM_INS_VABD: vabd */ - { 0 } -}, + {/* ARM_VABDsv16i8, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDsv16i8, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDsv2i32, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDsv2i32, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDsv4i16, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDsv4i16, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDsv4i32, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDsv4i32, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDsv8i16, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDsv8i16, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDsv8i8, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDsv8i8, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDuv16i8, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDuv16i8, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDuv2i32, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDuv2i32, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDuv4i16, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDuv4i16, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDuv4i32, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDuv4i32, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDuv8i16, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDuv8i16, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABDuv8i8, ARM_INS_VABD: vabd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VABDuv8i8, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VABSD, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSD, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VABSH, ARM_INS_VABS: vabs */ + {0}}, -{ /* ARM_VABSH, ARM_INS_VABS: vabs */ - { 0 } -}, + {/* ARM_VABSS, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSS, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VABSfd, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSfd, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VABSfq, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSfq, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VABShd, ARM_INS_VABS: vabs */ + {0}}, -{ /* ARM_VABShd, ARM_INS_VABS: vabs */ - { 0 } -}, + {/* ARM_VABShq, ARM_INS_VABS: vabs */ + {0}}, -{ /* ARM_VABShq, ARM_INS_VABS: vabs */ - { 0 } -}, + {/* ARM_VABSv16i8, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSv16i8, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VABSv2i32, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSv2i32, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VABSv4i16, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSv4i16, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VABSv4i32, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSv4i32, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VABSv8i16, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSv8i16, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VABSv8i8, ARM_INS_VABS: vabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VABSv8i8, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VACGEfd, ARM_INS_VACGE: vacge */ + {0}}, -{ /* ARM_VACGEfd, ARM_INS_VACGE: vacge */ - { 0 } -}, + {/* ARM_VACGEfq, ARM_INS_VACGE: vacge */ + {0}}, -{ /* ARM_VACGEfq, ARM_INS_VACGE: vacge */ - { 0 } -}, + {/* ARM_VACGEhd, ARM_INS_VACGE: vacge */ + {0}}, -{ /* ARM_VACGEhd, ARM_INS_VACGE: vacge */ - { 0 } -}, + {/* ARM_VACGEhq, ARM_INS_VACGE: vacge */ + {0}}, -{ /* ARM_VACGEhq, ARM_INS_VACGE: vacge */ - { 0 } -}, + {/* ARM_VACGTfd, ARM_INS_VACGT: vacgt */ + {0}}, -{ /* ARM_VACGTfd, ARM_INS_VACGT: vacgt */ - { 0 } -}, + {/* ARM_VACGTfq, ARM_INS_VACGT: vacgt */ + {0}}, -{ /* ARM_VACGTfq, ARM_INS_VACGT: vacgt */ - { 0 } -}, + {/* ARM_VACGThd, ARM_INS_VACGT: vacgt */ + {0}}, -{ /* ARM_VACGThd, ARM_INS_VACGT: vacgt */ - { 0 } -}, + {/* ARM_VACGThq, ARM_INS_VACGT: vacgt */ + {0}}, -{ /* ARM_VACGThq, ARM_INS_VACGT: vacgt */ - { 0 } -}, + {/* ARM_VADDD, ARM_INS_FADDD: faddd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDD, ARM_INS_FADDD: faddd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDH, ARM_INS_VADD: vadd */ + {0}}, -{ /* ARM_VADDH, ARM_INS_VADD: vadd */ - { 0 } -}, + {/* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDS, ARM_INS_FADDS: fadds */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDS, ARM_INS_FADDS: fadds */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDfd, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDfd, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDfq, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDfq, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDhd, ARM_INS_VADD: vadd */ + {0}}, -{ /* ARM_VADDhd, ARM_INS_VADD: vadd */ - { 0 } -}, + {/* ARM_VADDhq, ARM_INS_VADD: vadd */ + {0}}, -{ /* ARM_VADDhq, ARM_INS_VADD: vadd */ - { 0 } -}, + {/* ARM_VADDv16i8, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDv16i8, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDv1i64, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDv1i64, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDv2i32, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDv2i32, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDv2i64, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDv2i64, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDv4i16, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDv4i16, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDv4i32, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDv4i32, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDv8i16, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDv8i16, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VADDv8i8, ARM_INS_VADD: vadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VADDv8i8, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VANDd, ARM_INS_VAND: vand */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VANDd, ARM_INS_VAND: vand */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VANDq, ARM_INS_VAND: vand */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VANDq, ARM_INS_VAND: vand */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VBICd, ARM_INS_VBIC: vbic */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VBICd, ARM_INS_VBIC: vbic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VBICiv2i32, ARM_INS_VAND: vand */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VBICiv2i32, ARM_INS_VAND: vand */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VBICiv4i16, ARM_INS_VAND: vand */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VBICiv4i16, ARM_INS_VAND: vand */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VBICiv4i32, ARM_INS_VAND: vand */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VBICiv4i32, ARM_INS_VAND: vand */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VBICiv8i16, ARM_INS_VAND: vand */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VBICiv8i16, ARM_INS_VAND: vand */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VBICq, ARM_INS_VBIC: vbic */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VBICq, ARM_INS_VBIC: vbic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VBIFd, ARM_INS_VBIF: vbif */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VBIFd, ARM_INS_VBIF: vbif */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VBIFq, ARM_INS_VBIF: vbif */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VBIFq, ARM_INS_VBIF: vbif */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VBITd, ARM_INS_VBIT: vbit */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VBITd, ARM_INS_VBIT: vbit */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VBITq, ARM_INS_VBIT: vbit */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VBITq, ARM_INS_VBIT: vbit */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VBSLd, ARM_INS_VBSL: vbsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VBSLd, ARM_INS_VBSL: vbsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VBSLq, ARM_INS_VBSL: vbsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VBSLq, ARM_INS_VBSL: vbsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCADDv2f32, ARM_INS_VCADD: vcadd */ + {0}}, -{ /* ARM_VCADDv2f32, ARM_INS_VCADD: vcadd */ - { 0 } -}, + {/* ARM_VCADDv4f16, ARM_INS_VCADD: vcadd */ + {0}}, -{ /* ARM_VCADDv4f16, ARM_INS_VCADD: vcadd */ - { 0 } -}, + {/* ARM_VCADDv4f32, ARM_INS_VCADD: vcadd */ + {0}}, -{ /* ARM_VCADDv4f32, ARM_INS_VCADD: vcadd */ - { 0 } -}, + {/* ARM_VCADDv8f16, ARM_INS_VCADD: vcadd */ + {0}}, -{ /* ARM_VCADDv8f16, ARM_INS_VCADD: vcadd */ - { 0 } -}, + {/* ARM_VCEQfd, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCEQfd, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCEQfq, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCEQfq, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCEQhd, ARM_INS_VCEQ: vceq */ + {0}}, -{ /* ARM_VCEQhd, ARM_INS_VCEQ: vceq */ - { 0 } -}, + {/* ARM_VCEQhq, ARM_INS_VCEQ: vceq */ + {0}}, -{ /* ARM_VCEQhq, ARM_INS_VCEQ: vceq */ - { 0 } -}, + {/* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCEQzv4f16, ARM_INS_VCEQ: vceq */ + {0}}, -{ /* ARM_VCEQzv4f16, ARM_INS_VCEQ: vceq */ - { 0 } -}, + {/* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCEQzv8f16, ARM_INS_VCEQ: vceq */ + {0}}, -{ /* ARM_VCEQzv8f16, ARM_INS_VCEQ: vceq */ - { 0 } -}, + {/* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGEfd, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEfd, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEfq, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEfq, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEhd, ARM_INS_VCGE: vcge */ + {0}}, -{ /* ARM_VCGEhd, ARM_INS_VCGE: vcge */ - { 0 } -}, + {/* ARM_VCGEhq, ARM_INS_VCGE: vcge */ + {0}}, -{ /* ARM_VCGEhq, ARM_INS_VCGE: vcge */ - { 0 } -}, + {/* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGEzv4f16, ARM_INS_VCGE: vcge */ + {0}}, -{ /* ARM_VCGEzv4f16, ARM_INS_VCGE: vcge */ - { 0 } -}, + {/* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGEzv8f16, ARM_INS_VCGE: vcge */ + {0}}, -{ /* ARM_VCGEzv8f16, ARM_INS_VCGE: vcge */ - { 0 } -}, + {/* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGTfd, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTfd, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTfq, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTfq, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGThd, ARM_INS_VCGT: vcgt */ + {0}}, -{ /* ARM_VCGThd, ARM_INS_VCGT: vcgt */ - { 0 } -}, + {/* ARM_VCGThq, ARM_INS_VCGT: vcgt */ + {0}}, -{ /* ARM_VCGThq, ARM_INS_VCGT: vcgt */ - { 0 } -}, + {/* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGTzv4f16, ARM_INS_VCGT: vcgt */ + {0}}, -{ /* ARM_VCGTzv4f16, ARM_INS_VCGT: vcgt */ - { 0 } -}, + {/* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGTzv8f16, ARM_INS_VCGT: vcgt */ + {0}}, -{ /* ARM_VCGTzv8f16, ARM_INS_VCGT: vcgt */ - { 0 } -}, + {/* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLEzv4f16, ARM_INS_VCLE: vcle */ + {0}}, -{ /* ARM_VCLEzv4f16, ARM_INS_VCLE: vcle */ - { 0 } -}, + {/* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLEzv8f16, ARM_INS_VCLE: vcle */ + {0}}, -{ /* ARM_VCLEzv8f16, ARM_INS_VCLE: vcle */ - { 0 } -}, + {/* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLSv16i8, ARM_INS_VCLS: vcls */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLSv2i32, ARM_INS_VCLS: vcls */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLSv4i16, ARM_INS_VCLS: vcls */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLSv4i32, ARM_INS_VCLS: vcls */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLSv8i16, ARM_INS_VCLS: vcls */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLSv8i8, ARM_INS_VCLS: vcls */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLTzv4f16, ARM_INS_VCLT: vclt */ + {0}}, -{ /* ARM_VCLTzv4f16, ARM_INS_VCLT: vclt */ - { 0 } -}, + {/* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLTzv8f16, ARM_INS_VCLT: vclt */ + {0}}, -{ /* ARM_VCLTzv8f16, ARM_INS_VCLT: vclt */ - { 0 } -}, + {/* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCMLAv2f32, ARM_INS_VCMLA: vcmla */ + {0}}, -{ /* ARM_VCMLAv2f32, ARM_INS_VCMLA: vcmla */ - { 0 } -}, + {/* ARM_VCMLAv2f32_indexed, ARM_INS_VCMLA: vcmla */ + {0}}, -{ /* ARM_VCMLAv2f32_indexed, ARM_INS_VCMLA: vcmla */ - { 0 } -}, + {/* ARM_VCMLAv4f16, ARM_INS_VCMLA: vcmla */ + {0}}, -{ /* ARM_VCMLAv4f16, ARM_INS_VCMLA: vcmla */ - { 0 } -}, + {/* ARM_VCMLAv4f16_indexed, ARM_INS_VCMLA: vcmla */ + {0}}, -{ /* ARM_VCMLAv4f16_indexed, ARM_INS_VCMLA: vcmla */ - { 0 } -}, + {/* ARM_VCMLAv4f32, ARM_INS_VCMLA: vcmla */ + {0}}, -{ /* ARM_VCMLAv4f32, ARM_INS_VCMLA: vcmla */ - { 0 } -}, + {/* ARM_VCMLAv4f32_indexed, ARM_INS_VCMLA: vcmla */ + {0}}, -{ /* ARM_VCMLAv4f32_indexed, ARM_INS_VCMLA: vcmla */ - { 0 } -}, + {/* ARM_VCMLAv8f16, ARM_INS_VCMLA: vcmla */ + {0}}, -{ /* ARM_VCMLAv8f16, ARM_INS_VCMLA: vcmla */ - { 0 } -}, + {/* ARM_VCMLAv8f16_indexed, ARM_INS_VCMLA: vcmla */ + {0}}, -{ /* ARM_VCMLAv8f16_indexed, ARM_INS_VCMLA: vcmla */ - { 0 } -}, + {/* ARM_VCMPD, ARM_INS_VCMP: vcmp */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCMPD, ARM_INS_VCMP: vcmp */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCMPED, ARM_INS_VCMPE: vcmpe */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCMPEH, ARM_INS_VCMPE: vcmpe */ + {0}}, -{ /* ARM_VCMPEH, ARM_INS_VCMPE: vcmpe */ - { 0 } -}, + {/* ARM_VCMPES, ARM_INS_VCMPE: vcmpe */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe */ + {CS_AC_READ, 0}}, -{ /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe */ - { CS_AC_READ, 0 } -}, + {/* ARM_VCMPEZH, ARM_INS_VCMPE: vcmpe */ + {0}}, -{ /* ARM_VCMPEZH, ARM_INS_VCMPE: vcmpe */ - { 0 } -}, + {/* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe */ + {CS_AC_READ, 0}}, -{ /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe */ - { CS_AC_READ, 0 } -}, + {/* ARM_VCMPH, ARM_INS_VCMP: vcmp */ + {0}}, -{ /* ARM_VCMPH, ARM_INS_VCMP: vcmp */ - { 0 } -}, + {/* ARM_VCMPS, ARM_INS_VCMP: vcmp */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VCMPS, ARM_INS_VCMP: vcmp */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VCMPZD, ARM_INS_FCMPZD: fcmpzd */ + {CS_AC_READ, 0}}, -{ /* ARM_VCMPZD, ARM_INS_FCMPZD: fcmpzd */ - { CS_AC_READ, 0 } -}, + {/* ARM_VCMPZH, ARM_INS_VCMP: vcmp */ + {0}}, -{ /* ARM_VCMPZH, ARM_INS_VCMP: vcmp */ - { 0 } -}, + {/* ARM_VCMPZS, ARM_INS_FCMPZS: fcmpzs */ + {CS_AC_READ, 0}}, -{ /* ARM_VCMPZS, ARM_INS_FCMPZS: fcmpzs */ - { CS_AC_READ, 0 } -}, + {/* ARM_VCNTd, ARM_INS_VCNT: vcnt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCNTd, ARM_INS_VCNT: vcnt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCNTq, ARM_INS_VCNT: vcnt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCNTq, ARM_INS_VCNT: vcnt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTANSDf, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTANSDf, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTANSDh, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTANSDh, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTANSQf, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTANSQf, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTANSQh, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTANSQh, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTANUDf, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTANUDf, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTANUDh, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTANUDh, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTANUQf, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTANUQf, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTANUQh, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTANUQh, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTASD, ARM_INS_VCVTA: vcvta */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTASH, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTASH, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTASS, ARM_INS_VCVTA: vcvta */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTAUH, ARM_INS_VCVTA: vcvta */ + {0}}, -{ /* ARM_VCVTAUH, ARM_INS_VCVTA: vcvta */ - { 0 } -}, + {/* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTDS, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTDS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTMNSDf, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMNSDf, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMNSDh, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMNSDh, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMNSQf, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMNSQf, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMNSQh, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMNSQh, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMNUDf, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMNUDf, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMNUDh, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMNUDh, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMNUQf, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMNUQf, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMNUQh, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMNUQh, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTMSH, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMSH, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTMUH, ARM_INS_VCVTM: vcvtm */ + {0}}, -{ /* ARM_VCVTMUH, ARM_INS_VCVTM: vcvtm */ - { 0 } -}, + {/* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTNNSDf, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNNSDf, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNNSDh, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNNSDh, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNNSQf, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNNSQf, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNNSQh, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNNSQh, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNNUDf, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNNUDf, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNNUDh, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNNUDh, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNNUQf, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNNUQf, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNNUQh, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNNUQh, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTNSH, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNSH, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTNUH, ARM_INS_VCVTN: vcvtn */ + {0}}, -{ /* ARM_VCVTNUH, ARM_INS_VCVTN: vcvtn */ - { 0 } -}, + {/* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTPNSDf, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPNSDf, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPNSDh, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPNSDh, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPNSQf, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPNSQf, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPNSQh, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPNSQh, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPNUDf, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPNUDf, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPNUDh, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPNUDh, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPNUQf, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPNUQf, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPNUQh, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPNUQh, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTPSH, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPSH, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTPUH, ARM_INS_VCVTP: vcvtp */ + {0}}, -{ /* ARM_VCVTPUH, ARM_INS_VCVTP: vcvtp */ - { 0 } -}, + {/* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTSD, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTSD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTf2h, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTh2f, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTh2sd, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTh2sd, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTh2sq, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTh2sq, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTh2ud, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTh2ud, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTh2uq, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTh2uq, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTh2xsd, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTh2xsd, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTh2xsq, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTh2xsq, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTh2xud, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTh2xud, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTh2xuq, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTh2xuq, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTs2hd, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTs2hd, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTs2hq, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTs2hq, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTu2hd, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTu2hd, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTu2hq, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTu2hq, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTxs2hd, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTxs2hd, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTxs2hq, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTxs2hq, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VCVTxu2hd, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTxu2hd, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VCVTxu2hq, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VCVTxu2hq, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VDIVD, ARM_INS_VDIV: vdiv */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VDIVD, ARM_INS_VDIV: vdiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VDIVH, ARM_INS_VDIV: vdiv */ + {0}}, -{ /* ARM_VDIVH, ARM_INS_VDIV: vdiv */ - { 0 } -}, + {/* ARM_VDIVS, ARM_INS_VDIV: vdiv */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VDIVS, ARM_INS_VDIV: vdiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VDUP16d, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUP16d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUP16q, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUP16q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUP32d, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUP32d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUP32q, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUP32q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUP8d, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUP8d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUP8q, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUP8q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUPLN16d, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUPLN16q, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUPLN32d, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUPLN32q, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUPLN8d, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VDUPLN8q, ARM_INS_VDUP: vdup */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VEORd, ARM_INS_VEOR: veor */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VEORd, ARM_INS_VEOR: veor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VEORq, ARM_INS_VEOR: veor */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VEORq, ARM_INS_VEOR: veor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VEXTd16, ARM_INS_VEXT: vext */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VEXTd16, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VEXTd32, ARM_INS_VEXT: vext */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VEXTd32, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VEXTd8, ARM_INS_VEXT: vext */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VEXTd8, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VEXTq16, ARM_INS_VEXT: vext */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VEXTq16, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VEXTq32, ARM_INS_VEXT: vext */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VEXTq32, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VEXTq64, ARM_INS_VEXT: vext */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VEXTq64, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VEXTq8, ARM_INS_VEXT: vext */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VEXTq8, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFMAD, ARM_INS_VFMA: vfma */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFMAD, ARM_INS_VFMA: vfma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFMAH, ARM_INS_VFMA: vfma */ + {0}}, -{ /* ARM_VFMAH, ARM_INS_VFMA: vfma */ - { 0 } -}, + {/* ARM_VFMAS, ARM_INS_VFMA: vfma */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFMAS, ARM_INS_VFMA: vfma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFMAfd, ARM_INS_VFMA: vfma */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFMAfd, ARM_INS_VFMA: vfma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFMAfq, ARM_INS_VFMA: vfma */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFMAfq, ARM_INS_VFMA: vfma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFMAhd, ARM_INS_VFMA: vfma */ + {0}}, -{ /* ARM_VFMAhd, ARM_INS_VFMA: vfma */ - { 0 } -}, + {/* ARM_VFMAhq, ARM_INS_VFMA: vfma */ + {0}}, -{ /* ARM_VFMAhq, ARM_INS_VFMA: vfma */ - { 0 } -}, + {/* ARM_VFMSD, ARM_INS_VFMS: vfms */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFMSD, ARM_INS_VFMS: vfms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFMSH, ARM_INS_VFMS: vfms */ + {0}}, -{ /* ARM_VFMSH, ARM_INS_VFMS: vfms */ - { 0 } -}, + {/* ARM_VFMSS, ARM_INS_VFMS: vfms */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFMSS, ARM_INS_VFMS: vfms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFMSfd, ARM_INS_VFMS: vfms */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFMSfd, ARM_INS_VFMS: vfms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFMSfq, ARM_INS_VFMS: vfms */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFMSfq, ARM_INS_VFMS: vfms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFMShd, ARM_INS_VFMS: vfms */ + {0}}, -{ /* ARM_VFMShd, ARM_INS_VFMS: vfms */ - { 0 } -}, + {/* ARM_VFMShq, ARM_INS_VFMS: vfms */ + {0}}, -{ /* ARM_VFMShq, ARM_INS_VFMS: vfms */ - { 0 } -}, + {/* ARM_VFNMAD, ARM_INS_VFNMA: vfnma */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFNMAH, ARM_INS_VFNMA: vfnma */ + {0}}, -{ /* ARM_VFNMAH, ARM_INS_VFNMA: vfnma */ - { 0 } -}, + {/* ARM_VFNMAS, ARM_INS_VFNMA: vfnma */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFNMSD, ARM_INS_VFNMS: vfnms */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VFNMSH, ARM_INS_VFNMS: vfnms */ + {0}}, -{ /* ARM_VFNMSH, ARM_INS_VFNMS: vfnms */ - { 0 } -}, + {/* ARM_VFNMSS, ARM_INS_VFNMS: vfnms */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VGETLNi32, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VGETLNi32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VGETLNs16, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VGETLNs16, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VGETLNs8, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VGETLNs8, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VGETLNu16, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VGETLNu16, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VGETLNu8, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VGETLNu8, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VINSH, ARM_INS_VINS: vins */ + {0}}, -{ /* ARM_VINSH, ARM_INS_VINS: vins */ - { 0 } -}, + {/* ARM_VJCVT, ARM_INS_VJCVT: vjcvt */ + {0}}, -{ /* ARM_VJCVT, ARM_INS_VJCVT: vjcvt */ - { 0 } -}, + {/* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1LNd16, ARM_INS_VLD1: vld1 */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VLD1LNd32, ARM_INS_VLD1: vld1 */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1 */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VLD1LNd8, ARM_INS_VLD1: vld1 */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VLD1d16, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d16, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d16Q, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d16T, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d16T, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d32, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d32, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d32Q, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d32T, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d32T, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d64, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d64, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d64Q, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d64T, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d64T, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d8, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d8, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d8Q, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d8T, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d8T, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q16, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1q16, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q32, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1q32, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q64, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1q64, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q8, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1q8, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} + $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] + $dst2[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} + $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] + $dst2[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn + */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} + $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} + $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] + $dst2[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} + $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] + $dst2[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD2b16, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2b16, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2b32, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2b32, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2b8, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2b8, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2d16, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2d16, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2d32, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2d32, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2d8, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2d8, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2q16, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2q16, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2q32, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2q32, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD2q8, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2q8, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] + $dst3[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3d16, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3d16, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3d32, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3d32, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3d8, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3d8, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3q16, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3q16, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3q32, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3q32, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD3q8, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD3q8, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] + $dst3[$lane] $dst4[$lane]\} $rn$rm */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4d16, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4d16, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4d32, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4d32, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4d8, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4d8, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4q16, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4q16, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4q32, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4q32, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLD4q8, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VLD4q8, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4 */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia */ + {CS_AC_READ, 0}}, -{ /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia */ - { CS_AC_READ, 0 } -}, + {/* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia */ + {CS_AC_READ, 0}}, -{ /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia */ - { CS_AC_READ, 0 } -}, + {/* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VLDRD, ARM_INS_VLDR: vldr */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VLDRD, ARM_INS_VLDR: vldr */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VLDRH, ARM_INS_VLDR: vldr */ + {0}}, -{ /* ARM_VLDRH, ARM_INS_VLDR: vldr */ - { 0 } -}, + {/* ARM_VLDRS, ARM_INS_VLDR: vldr */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VLDRS, ARM_INS_VLDR: vldr */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VLLDM, ARM_INS_VLLDM: vlldm */ + {0}}, -{ /* ARM_VLLDM, ARM_INS_VLLDM: vlldm */ - { 0 } -}, + {/* ARM_VLSTM, ARM_INS_VLSTM: vlstm */ + {0}}, -{ /* ARM_VLSTM, ARM_INS_VLSTM: vlstm */ - { 0 } -}, + {/* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXNMH, ARM_INS_VMAXNM: vmaxnm */ + {0}}, -{ /* ARM_VMAXNMH, ARM_INS_VMAXNM: vmaxnm */ - { 0 } -}, + {/* ARM_VMAXNMNDf, ARM_INS_VMAXNM: vmaxnm */ + {0}}, -{ /* ARM_VMAXNMNDf, ARM_INS_VMAXNM: vmaxnm */ - { 0 } -}, + {/* ARM_VMAXNMNDh, ARM_INS_VMAXNM: vmaxnm */ + {0}}, -{ /* ARM_VMAXNMNDh, ARM_INS_VMAXNM: vmaxnm */ - { 0 } -}, + {/* ARM_VMAXNMNQf, ARM_INS_VMAXNM: vmaxnm */ + {0}}, -{ /* ARM_VMAXNMNQf, ARM_INS_VMAXNM: vmaxnm */ - { 0 } -}, + {/* ARM_VMAXNMNQh, ARM_INS_VMAXNM: vmaxnm */ + {0}}, -{ /* ARM_VMAXNMNQh, ARM_INS_VMAXNM: vmaxnm */ - { 0 } -}, + {/* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXfd, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXfd, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXfq, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXfq, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXhd, ARM_INS_VMAX: vmax */ + {0}}, -{ /* ARM_VMAXhd, ARM_INS_VMAX: vmax */ - { 0 } -}, + {/* ARM_VMAXhq, ARM_INS_VMAX: vmax */ + {0}}, -{ /* ARM_VMAXhq, ARM_INS_VMAX: vmax */ - { 0 } -}, + {/* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINNMD, ARM_INS_VMINNM: vminnm */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINNMH, ARM_INS_VMINNM: vminnm */ + {0}}, -{ /* ARM_VMINNMH, ARM_INS_VMINNM: vminnm */ - { 0 } -}, + {/* ARM_VMINNMNDf, ARM_INS_VMINNM: vminnm */ + {0}}, -{ /* ARM_VMINNMNDf, ARM_INS_VMINNM: vminnm */ - { 0 } -}, + {/* ARM_VMINNMNDh, ARM_INS_VMINNM: vminnm */ + {0}}, -{ /* ARM_VMINNMNDh, ARM_INS_VMINNM: vminnm */ - { 0 } -}, + {/* ARM_VMINNMNQf, ARM_INS_VMINNM: vminnm */ + {0}}, -{ /* ARM_VMINNMNQf, ARM_INS_VMINNM: vminnm */ - { 0 } -}, + {/* ARM_VMINNMNQh, ARM_INS_VMINNM: vminnm */ + {0}}, -{ /* ARM_VMINNMNQh, ARM_INS_VMINNM: vminnm */ - { 0 } -}, + {/* ARM_VMINNMS, ARM_INS_VMINNM: vminnm */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINfd, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINfd, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINfq, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINfq, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINhd, ARM_INS_VMIN: vmin */ + {0}}, -{ /* ARM_VMINhd, ARM_INS_VMIN: vmin */ - { 0 } -}, + {/* ARM_VMINhq, ARM_INS_VMIN: vmin */ + {0}}, -{ /* ARM_VMINhq, ARM_INS_VMIN: vmin */ - { 0 } -}, + {/* ARM_VMINsv16i8, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINsv2i32, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINsv4i16, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINsv4i32, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINsv8i16, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINsv8i8, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINuv16i8, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINuv2i32, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINuv4i16, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINuv4i32, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINuv8i16, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMINuv8i8, ARM_INS_VMIN: vmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAD, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAD, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAH, ARM_INS_VMLA: vmla */ + {0}}, -{ /* ARM_VMLAH, ARM_INS_VMLA: vmla */ - { 0 } -}, + {/* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAS, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAS, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAfd, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAfd, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAfq, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAfq, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAhd, ARM_INS_VMLA: vmla */ + {0}}, -{ /* ARM_VMLAhd, ARM_INS_VMLA: vmla */ - { 0 } -}, + {/* ARM_VMLAhq, ARM_INS_VMLA: vmla */ + {0}}, -{ /* ARM_VMLAhq, ARM_INS_VMLA: vmla */ - { 0 } -}, + {/* ARM_VMLAslfd, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLAslfd, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLAslfq, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLAslfq, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLAslhd, ARM_INS_VMLA: vmla */ + {0}}, -{ /* ARM_VMLAslhd, ARM_INS_VMLA: vmla */ - { 0 } -}, + {/* ARM_VMLAslhq, ARM_INS_VMLA: vmla */ + {0}}, -{ /* ARM_VMLAslhq, ARM_INS_VMLA: vmla */ - { 0 } -}, + {/* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLAv16i8, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAv2i32, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAv4i16, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAv4i32, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAv8i16, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLAv8i8, ARM_INS_VMLA: vmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSD, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSD, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSH, ARM_INS_VMLS: vmls */ + {0}}, -{ /* ARM_VMLSH, ARM_INS_VMLS: vmls */ - { 0 } -}, + {/* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSS, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSS, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSfd, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSfd, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSfq, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSfq, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLShd, ARM_INS_VMLS: vmls */ + {0}}, -{ /* ARM_VMLShd, ARM_INS_VMLS: vmls */ - { 0 } -}, + {/* ARM_VMLShq, ARM_INS_VMLS: vmls */ + {0}}, -{ /* ARM_VMLShq, ARM_INS_VMLS: vmls */ - { 0 } -}, + {/* ARM_VMLSslfd, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSslfd, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSslfq, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSslfq, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSslhd, ARM_INS_VMLS: vmls */ + {0}}, -{ /* ARM_VMLSslhd, ARM_INS_VMLS: vmls */ - { 0 } -}, + {/* ARM_VMLSslhq, ARM_INS_VMLS: vmls */ + {0}}, -{ /* ARM_VMLSslhq, ARM_INS_VMLS: vmls */ - { 0 } -}, + {/* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMLSv16i8, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSv16i8, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSv2i32, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSv2i32, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSv4i16, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSv4i16, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSv4i32, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSv4i32, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSv8i16, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSv8i16, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMLSv8i8, ARM_INS_VMLS: vmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMLSv8i8, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMOVD, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVD, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVDRR, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMOVDRR, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMOVH, ARM_INS_VMOVX: vmovx */ + {0}}, -{ /* ARM_VMOVH, ARM_INS_VMOVX: vmovx */ - { 0 } -}, + {/* ARM_VMOVHR, ARM_INS_VMOV: vmov */ + {0}}, -{ /* ARM_VMOVHR, ARM_INS_VMOV: vmov */ - { 0 } -}, + {/* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVRH, ARM_INS_VMOV: vmov */ + {0}}, -{ /* ARM_VMOVRH, ARM_INS_VMOV: vmov */ - { 0 } -}, + {/* ARM_VMOVRRD, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVRRD, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVRRS, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMOVRRS, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMOVRS, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVRS, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVS, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVS, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVSR, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMOVSR, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMOVSRR, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMOVSRR, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMOVv16i8, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv16i8, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMOVv1i64, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv1i64, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMOVv2f32, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv2f32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMOVv2i32, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv2i32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMOVv2i64, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv2i64, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMOVv4f32, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv4f32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMOVv4i16, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv4i16, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMOVv4i32, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv4i32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMOVv8i16, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv8i16, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMOVv8i8, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMOVv8i8, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMRS, ARM_INS_VMRS: vmrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMRS, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMSR, ARM_INS_VMSR: vmsr */ + {CS_AC_IGNORE, CS_AC_READ, 0}}, -{ /* ARM_VMSR, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, + {/* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr */ + {CS_AC_IGNORE, CS_AC_READ, 0}}, -{ /* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, + {/* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr */ + {CS_AC_IGNORE, CS_AC_READ, 0}}, -{ /* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, + {/* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr */ + {CS_AC_IGNORE, CS_AC_READ, 0}}, -{ /* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, + {/* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr */ + {CS_AC_IGNORE, CS_AC_READ, 0}}, -{ /* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, + {/* ARM_VMULD, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULD, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULH, ARM_INS_VMUL: vmul */ + {0}}, -{ /* ARM_VMULH, ARM_INS_VMUL: vmul */ - { 0 } -}, + {/* ARM_VMULLp64, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULLp64, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULLp8, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULLp8, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULS, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULS, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULfd, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULfd, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULfq, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULfq, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULhd, ARM_INS_VMUL: vmul */ + {0}}, -{ /* ARM_VMULhd, ARM_INS_VMUL: vmul */ - { 0 } -}, + {/* ARM_VMULhq, ARM_INS_VMUL: vmul */ + {0}}, -{ /* ARM_VMULhq, ARM_INS_VMUL: vmul */ - { 0 } -}, + {/* ARM_VMULpd, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULpd, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULpq, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULpq, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULslfd, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULslfd, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULslfq, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULslfq, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULslhd, ARM_INS_VMUL: vmul */ + {0}}, -{ /* ARM_VMULslhd, ARM_INS_VMUL: vmul */ - { 0 } -}, + {/* ARM_VMULslhq, ARM_INS_VMUL: vmul */ + {0}}, -{ /* ARM_VMULslhq, ARM_INS_VMUL: vmul */ - { 0 } -}, + {/* ARM_VMULslv2i32, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULslv2i32, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULslv4i16, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULslv4i16, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULslv4i32, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULslv4i32, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULslv8i16, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMULslv8i16, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMULv16i8, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULv16i8, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULv2i32, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULv2i32, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULv4i16, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULv4i16, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULv4i32, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULv4i32, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULv8i16, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULv8i16, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMULv8i8, ARM_INS_VMUL: vmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VMULv8i8, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VMVNd, ARM_INS_VMVN: vmvn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMVNd, ARM_INS_VMVN: vmvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMVNq, ARM_INS_VMVN: vmvn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VMVNq, ARM_INS_VMVN: vmvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VMVNv2i32, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMVNv2i32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMVNv4i32, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMVNv4i32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn */ + {CS_AC_WRITE, 0}}, -{ /* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_VNEGD, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGD, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNEGH, ARM_INS_VNEG: vneg */ + {0}}, -{ /* ARM_VNEGH, ARM_INS_VNEG: vneg */ - { 0 } -}, + {/* ARM_VNEGS, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGS, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNEGf32q, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGf32q, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNEGfd, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGfd, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNEGhd, ARM_INS_VNEG: vneg */ + {0}}, -{ /* ARM_VNEGhd, ARM_INS_VNEG: vneg */ - { 0 } -}, + {/* ARM_VNEGhq, ARM_INS_VNEG: vneg */ + {0}}, -{ /* ARM_VNEGhq, ARM_INS_VNEG: vneg */ - { 0 } -}, + {/* ARM_VNEGs16d, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGs16d, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNEGs16q, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGs16q, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNEGs32d, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGs32d, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNEGs32q, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGs32q, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNEGs8d, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGs8d, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNEGs8q, ARM_INS_VNEG: vneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VNEGs8q, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VNMLAD, ARM_INS_VNMLA: vnmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VNMLAD, ARM_INS_VNMLA: vnmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VNMLAH, ARM_INS_VNMLA: vnmla */ + {0}}, -{ /* ARM_VNMLAH, ARM_INS_VNMLA: vnmla */ - { 0 } -}, + {/* ARM_VNMLAS, ARM_INS_VNMLA: vnmla */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VNMLAS, ARM_INS_VNMLA: vnmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VNMLSD, ARM_INS_VNMLS: vnmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VNMLSD, ARM_INS_VNMLS: vnmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VNMLSH, ARM_INS_VNMLS: vnmls */ + {0}}, -{ /* ARM_VNMLSH, ARM_INS_VNMLS: vnmls */ - { 0 } -}, + {/* ARM_VNMLSS, ARM_INS_VNMLS: vnmls */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VNMLSS, ARM_INS_VNMLS: vnmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VNMULD, ARM_INS_VNMUL: vnmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VNMULD, ARM_INS_VNMUL: vnmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VNMULH, ARM_INS_VNMUL: vnmul */ + {0}}, -{ /* ARM_VNMULH, ARM_INS_VNMUL: vnmul */ - { 0 } -}, + {/* ARM_VNMULS, ARM_INS_VNMUL: vnmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VNMULS, ARM_INS_VNMUL: vnmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VORNd, ARM_INS_VORN: vorn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VORNd, ARM_INS_VORN: vorn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VORNq, ARM_INS_VORN: vorn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VORNq, ARM_INS_VORN: vorn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VORRd, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VORRd, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VORRiv2i32, ARM_INS_VORR: vorr */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VORRiv2i32, ARM_INS_VORR: vorr */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VORRiv4i16, ARM_INS_VORR: vorr */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VORRiv4i16, ARM_INS_VORR: vorr */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VORRiv4i32, ARM_INS_VORR: vorr */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VORRiv4i32, ARM_INS_VORR: vorr */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VORRiv8i16, ARM_INS_VORR: vorr */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VORRiv8i16, ARM_INS_VORR: vorr */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VORRq, ARM_INS_VMOV: vmov */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VORRq, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VPADDf, ARM_INS_VPADD: vpadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPADDf, ARM_INS_VPADD: vpadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPADDh, ARM_INS_VPADD: vpadd */ + {0}}, -{ /* ARM_VPADDh, ARM_INS_VPADD: vpadd */ - { 0 } -}, + {/* ARM_VPADDi16, ARM_INS_VPADD: vpadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPADDi16, ARM_INS_VPADD: vpadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPADDi32, ARM_INS_VPADD: vpadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPADDi32, ARM_INS_VPADD: vpadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPADDi8, ARM_INS_VPADD: vpadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPADDi8, ARM_INS_VPADD: vpadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMAXf, ARM_INS_VPMAX: vpmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMAXf, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMAXh, ARM_INS_VPMAX: vpmax */ + {0}}, -{ /* ARM_VPMAXh, ARM_INS_VPMAX: vpmax */ - { 0 } -}, + {/* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMINf, ARM_INS_VPMIN: vpmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMINf, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMINh, ARM_INS_VPMIN: vpmin */ + {0}}, -{ /* ARM_VPMINh, ARM_INS_VPMIN: vpmin */ - { 0 } -}, + {/* ARM_VPMINs16, ARM_INS_VPMIN: vpmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMINs16, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMINs32, ARM_INS_VPMIN: vpmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMINs32, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMINs8, ARM_INS_VPMIN: vpmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMINs8, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMINu16, ARM_INS_VPMIN: vpmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMINu16, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMINu32, ARM_INS_VPMIN: vpmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMINu32, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VPMINu8, ARM_INS_VPMIN: vpmin */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VPMINu8, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRDMLAHslv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ + {0}}, -{ /* ARM_VQRDMLAHslv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } -}, + {/* ARM_VQRDMLAHslv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ + {0}}, -{ /* ARM_VQRDMLAHslv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } -}, + {/* ARM_VQRDMLAHslv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ + {0}}, -{ /* ARM_VQRDMLAHslv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } -}, + {/* ARM_VQRDMLAHslv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ + {0}}, -{ /* ARM_VQRDMLAHslv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } -}, + {/* ARM_VQRDMLAHv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ + {0}}, -{ /* ARM_VQRDMLAHv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } -}, + {/* ARM_VQRDMLAHv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ + {0}}, -{ /* ARM_VQRDMLAHv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } -}, + {/* ARM_VQRDMLAHv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ + {0}}, -{ /* ARM_VQRDMLAHv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } -}, + {/* ARM_VQRDMLAHv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ + {0}}, -{ /* ARM_VQRDMLAHv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } -}, + {/* ARM_VQRDMLSHslv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + {0}}, -{ /* ARM_VQRDMLSHslv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } -}, + {/* ARM_VQRDMLSHslv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + {0}}, -{ /* ARM_VQRDMLSHslv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } -}, + {/* ARM_VQRDMLSHslv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + {0}}, -{ /* ARM_VQRDMLSHslv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } -}, + {/* ARM_VQRDMLSHslv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + {0}}, -{ /* ARM_VQRDMLSHslv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } -}, + {/* ARM_VQRDMLSHv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + {0}}, -{ /* ARM_VQRDMLSHv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } -}, + {/* ARM_VQRDMLSHv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + {0}}, -{ /* ARM_VQRDMLSHv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } -}, + {/* ARM_VQRDMLSHv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + {0}}, -{ /* ARM_VQRDMLSHv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } -}, + {/* ARM_VQRDMLSHv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + {0}}, -{ /* ARM_VQRDMLSHv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } -}, + {/* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRECPEhd, ARM_INS_VRECPE: vrecpe */ + {0}}, -{ /* ARM_VRECPEhd, ARM_INS_VRECPE: vrecpe */ - { 0 } -}, + {/* ARM_VRECPEhq, ARM_INS_VRECPE: vrecpe */ + {0}}, -{ /* ARM_VRECPEhq, ARM_INS_VRECPE: vrecpe */ - { 0 } -}, + {/* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRECPShd, ARM_INS_VRECPS: vrecps */ + {0}}, -{ /* ARM_VRECPShd, ARM_INS_VRECPS: vrecps */ - { 0 } -}, + {/* ARM_VRECPShq, ARM_INS_VRECPS: vrecps */ + {0}}, -{ /* ARM_VRECPShq, ARM_INS_VRECPS: vrecps */ - { 0 } -}, + {/* ARM_VREV16d8, ARM_INS_VREV16: vrev16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV16d8, ARM_INS_VREV16: vrev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV16q8, ARM_INS_VREV16: vrev16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV16q8, ARM_INS_VREV16: vrev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV32d16, ARM_INS_VREV32: vrev32 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV32d16, ARM_INS_VREV32: vrev32 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV32d8, ARM_INS_VREV32: vrev32 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV32d8, ARM_INS_VREV32: vrev32 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV32q16, ARM_INS_VREV32: vrev32 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV32q16, ARM_INS_VREV32: vrev32 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV32q8, ARM_INS_VREV32: vrev32 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV32q8, ARM_INS_VREV32: vrev32 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV64d16, ARM_INS_VREV64: vrev64 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV64d16, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV64d32, ARM_INS_VREV64: vrev64 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV64d32, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV64d8, ARM_INS_VREV64: vrev64 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV64d8, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV64q16, ARM_INS_VREV64: vrev64 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV64q16, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV64q32, ARM_INS_VREV64: vrev64 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV64q32, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VREV64q8, ARM_INS_VREV64: vrev64 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VREV64q8, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRINTAD, ARM_INS_VRINTA: vrinta */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTAD, ARM_INS_VRINTA: vrinta */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTAH, ARM_INS_VRINTA: vrinta */ + {0}}, -{ /* ARM_VRINTAH, ARM_INS_VRINTA: vrinta */ - { 0 } -}, + {/* ARM_VRINTANDf, ARM_INS_VRINTA: vrinta */ + {0}}, -{ /* ARM_VRINTANDf, ARM_INS_VRINTA: vrinta */ - { 0 } -}, + {/* ARM_VRINTANDh, ARM_INS_VRINTA: vrinta */ + {0}}, -{ /* ARM_VRINTANDh, ARM_INS_VRINTA: vrinta */ - { 0 } -}, + {/* ARM_VRINTANQf, ARM_INS_VRINTA: vrinta */ + {0}}, -{ /* ARM_VRINTANQf, ARM_INS_VRINTA: vrinta */ - { 0 } -}, + {/* ARM_VRINTANQh, ARM_INS_VRINTA: vrinta */ + {0}}, -{ /* ARM_VRINTANQh, ARM_INS_VRINTA: vrinta */ - { 0 } -}, + {/* ARM_VRINTAS, ARM_INS_VRINTA: vrinta */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTAS, ARM_INS_VRINTA: vrinta */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTMD, ARM_INS_VRINTM: vrintm */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTMD, ARM_INS_VRINTM: vrintm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTMH, ARM_INS_VRINTM: vrintm */ + {0}}, -{ /* ARM_VRINTMH, ARM_INS_VRINTM: vrintm */ - { 0 } -}, + {/* ARM_VRINTMNDf, ARM_INS_VRINTM: vrintm */ + {0}}, -{ /* ARM_VRINTMNDf, ARM_INS_VRINTM: vrintm */ - { 0 } -}, + {/* ARM_VRINTMNDh, ARM_INS_VRINTM: vrintm */ + {0}}, -{ /* ARM_VRINTMNDh, ARM_INS_VRINTM: vrintm */ - { 0 } -}, + {/* ARM_VRINTMNQf, ARM_INS_VRINTM: vrintm */ + {0}}, -{ /* ARM_VRINTMNQf, ARM_INS_VRINTM: vrintm */ - { 0 } -}, + {/* ARM_VRINTMNQh, ARM_INS_VRINTM: vrintm */ + {0}}, -{ /* ARM_VRINTMNQh, ARM_INS_VRINTM: vrintm */ - { 0 } -}, + {/* ARM_VRINTMS, ARM_INS_VRINTM: vrintm */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTMS, ARM_INS_VRINTM: vrintm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTND, ARM_INS_VRINTN: vrintn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTND, ARM_INS_VRINTN: vrintn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTNH, ARM_INS_VRINTN: vrintn */ + {0}}, -{ /* ARM_VRINTNH, ARM_INS_VRINTN: vrintn */ - { 0 } -}, + {/* ARM_VRINTNNDf, ARM_INS_VRINTN: vrintn */ + {0}}, -{ /* ARM_VRINTNNDf, ARM_INS_VRINTN: vrintn */ - { 0 } -}, + {/* ARM_VRINTNNDh, ARM_INS_VRINTN: vrintn */ + {0}}, -{ /* ARM_VRINTNNDh, ARM_INS_VRINTN: vrintn */ - { 0 } -}, + {/* ARM_VRINTNNQf, ARM_INS_VRINTN: vrintn */ + {0}}, -{ /* ARM_VRINTNNQf, ARM_INS_VRINTN: vrintn */ - { 0 } -}, + {/* ARM_VRINTNNQh, ARM_INS_VRINTN: vrintn */ + {0}}, -{ /* ARM_VRINTNNQh, ARM_INS_VRINTN: vrintn */ - { 0 } -}, + {/* ARM_VRINTNS, ARM_INS_VRINTN: vrintn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTNS, ARM_INS_VRINTN: vrintn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTPD, ARM_INS_VRINTP: vrintp */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTPD, ARM_INS_VRINTP: vrintp */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTPH, ARM_INS_VRINTP: vrintp */ + {0}}, -{ /* ARM_VRINTPH, ARM_INS_VRINTP: vrintp */ - { 0 } -}, + {/* ARM_VRINTPNDf, ARM_INS_VRINTP: vrintp */ + {0}}, -{ /* ARM_VRINTPNDf, ARM_INS_VRINTP: vrintp */ - { 0 } -}, + {/* ARM_VRINTPNDh, ARM_INS_VRINTP: vrintp */ + {0}}, -{ /* ARM_VRINTPNDh, ARM_INS_VRINTP: vrintp */ - { 0 } -}, + {/* ARM_VRINTPNQf, ARM_INS_VRINTP: vrintp */ + {0}}, -{ /* ARM_VRINTPNQf, ARM_INS_VRINTP: vrintp */ - { 0 } -}, + {/* ARM_VRINTPNQh, ARM_INS_VRINTP: vrintp */ + {0}}, -{ /* ARM_VRINTPNQh, ARM_INS_VRINTP: vrintp */ - { 0 } -}, + {/* ARM_VRINTPS, ARM_INS_VRINTP: vrintp */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTPS, ARM_INS_VRINTP: vrintp */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTRD, ARM_INS_VRINTR: vrintr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTRD, ARM_INS_VRINTR: vrintr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTRH, ARM_INS_VRINTR: vrintr */ + {0}}, -{ /* ARM_VRINTRH, ARM_INS_VRINTR: vrintr */ - { 0 } -}, + {/* ARM_VRINTRS, ARM_INS_VRINTR: vrintr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTRS, ARM_INS_VRINTR: vrintr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTXD, ARM_INS_VRINTX: vrintx */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTXD, ARM_INS_VRINTX: vrintx */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTXH, ARM_INS_VRINTX: vrintx */ + {0}}, -{ /* ARM_VRINTXH, ARM_INS_VRINTX: vrintx */ - { 0 } -}, + {/* ARM_VRINTXNDf, ARM_INS_VRINTX: vrintx */ + {0}}, -{ /* ARM_VRINTXNDf, ARM_INS_VRINTX: vrintx */ - { 0 } -}, + {/* ARM_VRINTXNDh, ARM_INS_VRINTX: vrintx */ + {0}}, -{ /* ARM_VRINTXNDh, ARM_INS_VRINTX: vrintx */ - { 0 } -}, + {/* ARM_VRINTXNQf, ARM_INS_VRINTX: vrintx */ + {0}}, -{ /* ARM_VRINTXNQf, ARM_INS_VRINTX: vrintx */ - { 0 } -}, + {/* ARM_VRINTXNQh, ARM_INS_VRINTX: vrintx */ + {0}}, -{ /* ARM_VRINTXNQh, ARM_INS_VRINTX: vrintx */ - { 0 } -}, + {/* ARM_VRINTXS, ARM_INS_VRINTX: vrintx */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTXS, ARM_INS_VRINTX: vrintx */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRINTZH, ARM_INS_VRINTZ: vrintz */ + {0}}, -{ /* ARM_VRINTZH, ARM_INS_VRINTZ: vrintz */ - { 0 } -}, + {/* ARM_VRINTZNDf, ARM_INS_VRINTZ: vrintz */ + {0}}, -{ /* ARM_VRINTZNDf, ARM_INS_VRINTZ: vrintz */ - { 0 } -}, + {/* ARM_VRINTZNDh, ARM_INS_VRINTZ: vrintz */ + {0}}, -{ /* ARM_VRINTZNDh, ARM_INS_VRINTZ: vrintz */ - { 0 } -}, + {/* ARM_VRINTZNQf, ARM_INS_VRINTZ: vrintz */ + {0}}, -{ /* ARM_VRINTZNQf, ARM_INS_VRINTZ: vrintz */ - { 0 } -}, + {/* ARM_VRINTZNQh, ARM_INS_VRINTZ: vrintz */ + {0}}, -{ /* ARM_VRINTZNQh, ARM_INS_VRINTZ: vrintz */ - { 0 } -}, + {/* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSQRTEhd, ARM_INS_VRSQRTE: vrsqrte */ + {0}}, -{ /* ARM_VRSQRTEhd, ARM_INS_VRSQRTE: vrsqrte */ - { 0 } -}, + {/* ARM_VRSQRTEhq, ARM_INS_VRSQRTE: vrsqrte */ + {0}}, -{ /* ARM_VRSQRTEhq, ARM_INS_VRSQRTE: vrsqrte */ - { 0 } -}, + {/* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSQRTShd, ARM_INS_VRSQRTS: vrsqrts */ + {0}}, -{ /* ARM_VRSQRTShd, ARM_INS_VRSQRTS: vrsqrts */ - { 0 } -}, + {/* ARM_VRSQRTShq, ARM_INS_VRSQRTS: vrsqrts */ + {0}}, -{ /* ARM_VRSQRTShq, ARM_INS_VRSQRTS: vrsqrts */ - { 0 } -}, + {/* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSDOTD, ARM_INS_VSDOT: vsdot */ + {0}}, -{ /* ARM_VSDOTD, ARM_INS_VSDOT: vsdot */ - { 0 } -}, + {/* ARM_VSDOTDI, ARM_INS_VSDOT: vsdot */ + {0}}, -{ /* ARM_VSDOTDI, ARM_INS_VSDOT: vsdot */ - { 0 } -}, + {/* ARM_VSDOTQ, ARM_INS_VSDOT: vsdot */ + {0}}, -{ /* ARM_VSDOTQ, ARM_INS_VSDOT: vsdot */ - { 0 } -}, + {/* ARM_VSDOTQI, ARM_INS_VSDOT: vsdot */ + {0}}, -{ /* ARM_VSDOTQI, ARM_INS_VSDOT: vsdot */ - { 0 } -}, + {/* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSELEQH, ARM_INS_VSELEQ: vseleq */ + {0}}, -{ /* ARM_VSELEQH, ARM_INS_VSELEQ: vseleq */ - { 0 } -}, + {/* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSELGED, ARM_INS_VSELGE: vselge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSELGED, ARM_INS_VSELGE: vselge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSELGEH, ARM_INS_VSELGE: vselge */ + {0}}, -{ /* ARM_VSELGEH, ARM_INS_VSELGE: vselge */ - { 0 } -}, + {/* ARM_VSELGES, ARM_INS_VSELGE: vselge */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSELGES, ARM_INS_VSELGE: vselge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSELGTD, ARM_INS_VSELGT: vselgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSELGTD, ARM_INS_VSELGT: vselgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSELGTH, ARM_INS_VSELGT: vselgt */ + {0}}, -{ /* ARM_VSELGTH, ARM_INS_VSELGT: vselgt */ - { 0 } -}, + {/* ARM_VSELGTS, ARM_INS_VSELGT: vselgt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSELGTS, ARM_INS_VSELGT: vselgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSELVSD, ARM_INS_VSELVS: vselvs */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSELVSD, ARM_INS_VSELVS: vselvs */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSELVSH, ARM_INS_VSELVS: vselvs */ + {0}}, -{ /* ARM_VSELVSH, ARM_INS_VSELVS: vselvs */ - { 0 } -}, + {/* ARM_VSELVSS, ARM_INS_VSELVS: vselvs */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSELVSS, ARM_INS_VSELVS: vselvs */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSETLNi16, ARM_INS_VMOV: vmov */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSETLNi16, ARM_INS_VMOV: vmov */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSETLNi32, ARM_INS_FMDHR: fmdhr */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSETLNi32, ARM_INS_FMDHR: fmdhr */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSETLNi8, ARM_INS_VMOV: vmov */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSETLNi8, ARM_INS_VMOV: vmov */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLLi16, ARM_INS_VSHLL: vshll */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLLi16, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLLi32, ARM_INS_VSHLL: vshll */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLLi32, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLLi8, ARM_INS_VSHLL: vshll */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLLi8, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSHTOD, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VSHTOD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VSHTOH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VSHTOH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VSHTOS, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VSHTOS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VSITOD, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSITOD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSITOH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VSITOH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VSITOS, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSITOS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSLIv16i8, ARM_INS_VSLI: vsli */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSLIv16i8, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSLIv1i64, ARM_INS_VSLI: vsli */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSLIv1i64, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSLIv2i32, ARM_INS_VSLI: vsli */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSLIv2i32, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSLIv2i64, ARM_INS_VSLI: vsli */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSLIv2i64, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSLIv4i16, ARM_INS_VSLI: vsli */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSLIv4i16, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSLIv4i32, ARM_INS_VSLI: vsli */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSLIv4i32, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSLIv8i16, ARM_INS_VSLI: vsli */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSLIv8i16, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSLIv8i8, ARM_INS_VSLI: vsli */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSLIv8i8, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSLTOD, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VSLTOD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VSLTOH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VSLTOH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VSLTOS, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VSLTOS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSQRTH, ARM_INS_VSQRT: vsqrt */ + {0}}, -{ /* ARM_VSQRTH, ARM_INS_VSQRT: vsqrt */ - { 0 } -}, + {/* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRIv16i8, ARM_INS_VSRI: vsri */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRIv16i8, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRIv1i64, ARM_INS_VSRI: vsri */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRIv1i64, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRIv2i32, ARM_INS_VSRI: vsri */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRIv2i32, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRIv2i64, ARM_INS_VSRI: vsri */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRIv2i64, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRIv4i16, ARM_INS_VSRI: vsri */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRIv4i16, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRIv4i32, ARM_INS_VSRI: vsri */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRIv4i32, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRIv8i16, ARM_INS_VSRI: vsri */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRIv8i16, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VSRIv8i8, ARM_INS_VSRI: vsri */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VSRIv8i8, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VST1LNd16, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1LNd16, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1 */ + {CS_AC_READ, 0}}, -{ /* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1 */ - { CS_AC_READ, 0 } -}, + {/* ARM_VST1LNd32, ARM_INS_VST1: vst1 */ + {CS_AC_READ, 0}}, -{ /* ARM_VST1LNd32, ARM_INS_VST1: vst1 */ - { CS_AC_READ, 0 } -}, + {/* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1 */ + {CS_AC_READ, 0}}, -{ /* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1 */ - { CS_AC_READ, 0 } -}, + {/* ARM_VST1LNd8, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1LNd8, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1 */ + {CS_AC_READ, 0}}, -{ /* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1 */ - { CS_AC_READ, 0 } -}, + {/* ARM_VST1d16, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d16, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d16Q, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d16Q, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d16T, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d16T, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d16wb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d16wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d32, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d32, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d32Q, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d32Q, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d32T, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d32T, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d32wb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d32wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d64, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d64, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d64Q, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d64Q, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d64T, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d64T, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d64wb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d64wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d8, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d8, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d8Q, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d8Q, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d8T, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d8T, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1d8wb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1d8wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q16, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q16, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q16wb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q16wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q32, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q32, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q32wb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q32wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q64, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q64, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q64wb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q64wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q8, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q8, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST1q8wb_register, ARM_INS_VST1: vst1 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST1q8wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} + $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] + $src2[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} + $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] + $src2[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn + */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} + $rn$rm */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} + $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] + $src2[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} + $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] + $src2[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2b16, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2b16, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2b16wb_register, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2b16wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2b32, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2b32, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2b32wb_register, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2b32wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2b8, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2b8, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2b8wb_register, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2b8wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2d16, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2d16, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2d16wb_register, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2d16wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2d32, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2d32, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2d32wb_register, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2d32wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2d8, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2d8, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2d8wb_register, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2d8wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2q16, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2q16, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2q16wb_register, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2q16wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2q32, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2q32, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2q32wb_register, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2q32wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2q8, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2q8, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST2q8wb_register, ARM_INS_VST2: vst2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST2q8wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] + $src3[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3d16, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3d16, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3d16_UPD, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3d16_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3d32, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3d32, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3d32_UPD, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3d32_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3d8, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3d8, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3d8_UPD, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3d8_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3q16, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3q16, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3q16_UPD, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3q16_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3q32, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3q32, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3q32_UPD, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3q32_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3q8, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3q8, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST3q8_UPD, ARM_INS_VST3: vst3 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST3q8_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] + $src3[$lane] $src4[$lane]\} $rn$rm */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4d16, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4d16, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4d16_UPD, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4d16_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4d32, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4d32, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4d32_UPD, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4d32_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4d8, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4d8, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4d8_UPD, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4d8_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4q16, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4q16, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4q16_UPD, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4q16_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4q32, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4q32, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4q32_UPD, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4q32_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4q8, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4q8, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VST4q8_UPD, ARM_INS_VST4: vst4 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VST4q8_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSTMDDB_UPD, ARM_INS_VPUSH: vpush */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VSTMDDB_UPD, ARM_INS_VPUSH: vpush */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia */ + {CS_AC_READ, 0}}, -{ /* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia */ - { CS_AC_READ, 0 } -}, + {/* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VSTMSDB_UPD, ARM_INS_VPUSH: vpush */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VSTMSDB_UPD, ARM_INS_VPUSH: vpush */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia */ + {CS_AC_READ, 0}}, -{ /* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia */ - { CS_AC_READ, 0 } -}, + {/* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VSTRD, ARM_INS_VSTR: vstr */ + {CS_AC_READ, 0}}, -{ /* ARM_VSTRD, ARM_INS_VSTR: vstr */ - { CS_AC_READ, 0 } -}, + {/* ARM_VSTRH, ARM_INS_VSTR: vstr */ + {0}}, -{ /* ARM_VSTRH, ARM_INS_VSTR: vstr */ - { 0 } -}, + {/* ARM_VSTRS, ARM_INS_VSTR: vstr */ + {CS_AC_READ, 0}}, -{ /* ARM_VSTRS, ARM_INS_VSTR: vstr */ - { CS_AC_READ, 0 } -}, + {/* ARM_VSUBD, ARM_INS_FSUBD: fsubd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBD, ARM_INS_FSUBD: fsubd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBH, ARM_INS_VSUB: vsub */ + {0}}, -{ /* ARM_VSUBH, ARM_INS_VSUB: vsub */ - { 0 } -}, + {/* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBS, ARM_INS_FSUBS: fsubs */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBS, ARM_INS_FSUBS: fsubs */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBfd, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBfd, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBfq, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBfq, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBhd, ARM_INS_VSUB: vsub */ + {0}}, -{ /* ARM_VSUBhd, ARM_INS_VSUB: vsub */ - { 0 } -}, + {/* ARM_VSUBhq, ARM_INS_VSUB: vsub */ + {0}}, -{ /* ARM_VSUBhq, ARM_INS_VSUB: vsub */ - { 0 } -}, + {/* ARM_VSUBv16i8, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBv16i8, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBv1i64, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBv1i64, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBv2i32, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBv2i32, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBv2i64, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBv2i64, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBv4i16, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBv4i16, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBv4i32, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBv4i32, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBv8i16, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBv8i16, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSUBv8i8, ARM_INS_VSUB: vsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VSUBv8i8, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VSWPd, ARM_INS_VSWP: vswp */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VSWPd, ARM_INS_VSWP: vswp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VSWPq, ARM_INS_VSWP: vswp */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VSWPq, ARM_INS_VSWP: vswp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VTBL1, ARM_INS_VTBL: vtbl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTBL1, ARM_INS_VTBL: vtbl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTBL2, ARM_INS_VTBL: vtbl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTBL2, ARM_INS_VTBL: vtbl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTBL3, ARM_INS_VTBL: vtbl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTBL3, ARM_INS_VTBL: vtbl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTBL4, ARM_INS_VTBL: vtbl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTBL4, ARM_INS_VTBL: vtbl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTBX1, ARM_INS_VTBX: vtbx */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTBX1, ARM_INS_VTBX: vtbx */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTBX2, ARM_INS_VTBX: vtbx */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTBX2, ARM_INS_VTBX: vtbx */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTBX3, ARM_INS_VTBX: vtbx */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTBX3, ARM_INS_VTBX: vtbx */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTBX4, ARM_INS_VTBX: vtbx */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTBX4, ARM_INS_VTBX: vtbx */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTOSHD, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VTOSHD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VTOSHH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VTOSHH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VTOSHS, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VTOSHS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VTOSIRH, ARM_INS_VCVTR: vcvtr */ + {0}}, -{ /* ARM_VTOSIRH, ARM_INS_VCVTR: vcvtr */ - { 0 } -}, + {/* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VTOSIZD, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VTOSIZD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VTOSIZH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VTOSIZH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VTOSIZS, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VTOSIZS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VTOSLD, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VTOSLD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VTOSLH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VTOSLH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VTOSLS, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VTOSLS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VTOUHD, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VTOUHD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VTOUHH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VTOUHH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VTOUHS, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VTOUHS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VTOUIRH, ARM_INS_VCVTR: vcvtr */ + {0}}, -{ /* ARM_VTOUIRH, ARM_INS_VCVTR: vcvtr */ - { 0 } -}, + {/* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VTOUIZD, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VTOUIZD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VTOUIZH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VTOUIZH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VTOUIZS, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VTOUIZS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VTOULD, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VTOULD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VTOULH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VTOULH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VTOULS, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VTOULS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VTRNd16, ARM_INS_VTRN: vtrn */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VTRNd16, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VTRNd32, ARM_INS_VTRN: vtrn */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VTRNd32, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VTRNd8, ARM_INS_VTRN: vtrn */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VTRNd8, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VTRNq16, ARM_INS_VTRN: vtrn */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VTRNq16, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VTRNq32, ARM_INS_VTRN: vtrn */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VTRNq32, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VTRNq8, ARM_INS_VTRN: vtrn */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VTRNq8, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VTSTv16i8, ARM_INS_VTST: vtst */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTSTv16i8, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTSTv2i32, ARM_INS_VTST: vtst */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTSTv2i32, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTSTv4i16, ARM_INS_VTST: vtst */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTSTv4i16, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTSTv4i32, ARM_INS_VTST: vtst */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTSTv4i32, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTSTv8i16, ARM_INS_VTST: vtst */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTSTv8i16, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VTSTv8i8, ARM_INS_VTST: vtst */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_VTSTv8i8, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_VUDOTD, ARM_INS_VUDOT: vudot */ + {0}}, -{ /* ARM_VUDOTD, ARM_INS_VUDOT: vudot */ - { 0 } -}, + {/* ARM_VUDOTDI, ARM_INS_VUDOT: vudot */ + {0}}, -{ /* ARM_VUDOTDI, ARM_INS_VUDOT: vudot */ - { 0 } -}, + {/* ARM_VUDOTQ, ARM_INS_VUDOT: vudot */ + {0}}, -{ /* ARM_VUDOTQ, ARM_INS_VUDOT: vudot */ - { 0 } -}, + {/* ARM_VUDOTQI, ARM_INS_VUDOT: vudot */ + {0}}, -{ /* ARM_VUDOTQI, ARM_INS_VUDOT: vudot */ - { 0 } -}, + {/* ARM_VUHTOD, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VUHTOD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VUHTOH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VUHTOH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VUHTOS, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VUHTOS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VUITOD, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VUITOD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VUITOH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VUITOH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VUITOS, ARM_INS_VCVT: vcvt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_VUITOS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_VULTOD, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VULTOD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VULTOH, ARM_INS_VCVT: vcvt */ + {0}}, -{ /* ARM_VULTOH, ARM_INS_VCVT: vcvt */ - { 0 } -}, + {/* ARM_VULTOS, ARM_INS_VCVT: vcvt */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_VULTOS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_VUZPd16, ARM_INS_VUZP: vuzp */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VUZPd16, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VUZPd8, ARM_INS_VUZP: vuzp */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VUZPd8, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VUZPq16, ARM_INS_VUZP: vuzp */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VUZPq16, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VUZPq32, ARM_INS_VUZP: vuzp */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VUZPq32, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VUZPq8, ARM_INS_VUZP: vuzp */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VUZPq8, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VZIPd16, ARM_INS_VZIP: vzip */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VZIPd16, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VZIPd8, ARM_INS_VZIP: vzip */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VZIPd8, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VZIPq16, ARM_INS_VZIP: vzip */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VZIPq16, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VZIPq32, ARM_INS_VZIP: vzip */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VZIPq32, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_VZIPq8, ARM_INS_VZIP: vzip */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_VZIPq8, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_sysLDMIA, ARM_INS_LDM: ldm */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_sysLDMIA, ARM_INS_LDM: ldm */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_sysSTMDA, ARM_INS_STMDA: stmda */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_sysSTMDA, ARM_INS_STMDA: stmda */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_sysSTMDB, ARM_INS_STMDB: stmdb */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_sysSTMDB, ARM_INS_STMDB: stmdb */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_sysSTMIA, ARM_INS_STM: stm */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_sysSTMIA, ARM_INS_STM: stm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_sysSTMIA_UPD, ARM_INS_STM: stm */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_sysSTMIA_UPD, ARM_INS_STM: stm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_sysSTMIB, ARM_INS_STMIB: stmib */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_sysSTMIB, ARM_INS_STMIB: stmib */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ADCri, ARM_INS_ADC: adc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ADCri, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ADCrr, ARM_INS_ADC: adc */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2ADCrr, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2ADCrs, ARM_INS_ADC: adc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ADCrs, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ADDri, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ADDri, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ADDri12, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ADDri12, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ADDrr, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2ADDrr, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2ADDrs, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ADDrs, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ADR, ARM_INS_ADD: add */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2ADR, ARM_INS_ADD: add */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2ANDri, ARM_INS_AND: and */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ANDri, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ANDrr, ARM_INS_AND: and */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2ANDrr, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2ANDrs, ARM_INS_AND: and */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ANDrs, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ASRri, ARM_INS_ASR: asr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ASRri, ARM_INS_ASR: asr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ASRrr, ARM_INS_ASR: asr */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2ASRrr, ARM_INS_ASR: asr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2B, ARM_INS_B: b */ + {0}}, -{ /* ARM_t2B, ARM_INS_B: b */ - { 0 } -}, + {/* ARM_t2BFC, ARM_INS_BFC: bfc */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_t2BFC, ARM_INS_BFC: bfc */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_t2BFI, ARM_INS_BFI: bfi */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2BFI, ARM_INS_BFI: bfi */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2BICri, ARM_INS_AND: and */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2BICri, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2BICrr, ARM_INS_BIC: bic */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2BICrr, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2BICrs, ARM_INS_BIC: bic */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2BICrs, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2BXJ, ARM_INS_BXJ: bxj */ + {CS_AC_READ, 0}}, -{ /* ARM_t2BXJ, ARM_INS_BXJ: bxj */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2Bcc, ARM_INS_B: b */ + {0}}, -{ /* ARM_t2Bcc, ARM_INS_B: b */ - { 0 } -}, + {/* ARM_t2CDP, ARM_INS_CDP: cdp */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_t2CDP, ARM_INS_CDP: cdp */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_t2CDP2, ARM_INS_CDP2: cdp2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_t2CDP2, ARM_INS_CDP2: cdp2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_t2CLREX, ARM_INS_CLREX: clrex */ + {0}}, -{ /* ARM_t2CLREX, ARM_INS_CLREX: clrex */ - { 0 } -}, + {/* ARM_t2CLZ, ARM_INS_CLZ: clz */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2CLZ, ARM_INS_CLZ: clz */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2CMNri, ARM_INS_CMN: cmn */ + {CS_AC_READ, 0}}, -{ /* ARM_t2CMNri, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2CMNzrr, ARM_INS_CMN: cmn */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2CMNzrr, ARM_INS_CMN: cmn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2CMNzrs, ARM_INS_CMN: cmn */ + {CS_AC_READ, 0}}, -{ /* ARM_t2CMNzrs, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2CMPri, ARM_INS_CMN: cmn */ + {CS_AC_READ, 0}}, -{ /* ARM_t2CMPri, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2CMPrr, ARM_INS_CMP: cmp */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2CMPrr, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2CMPrs, ARM_INS_CMP: cmp */ + {CS_AC_READ, 0}}, -{ /* ARM_t2CMPrs, ARM_INS_CMP: cmp */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2CPS1p, ARM_INS_CPS: cps */ + {0}}, -{ /* ARM_t2CPS1p, ARM_INS_CPS: cps */ - { 0 } -}, + {/* ARM_t2CPS2p, ARM_INS_CPS: cps */ + {0}}, -{ /* ARM_t2CPS2p, ARM_INS_CPS: cps */ - { 0 } -}, + {/* ARM_t2CPS3p, ARM_INS_CPS: cps */ + {0}}, -{ /* ARM_t2CPS3p, ARM_INS_CPS: cps */ - { 0 } -}, + {/* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2DBG, ARM_INS_DBG: dbg */ + {0}}, -{ /* ARM_t2DBG, ARM_INS_DBG: dbg */ - { 0 } -}, + {/* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1 */ + {0}}, -{ /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1 */ - { 0 } -}, + {/* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2 */ + {0}}, -{ /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2 */ - { 0 } -}, + {/* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3 */ + {0}}, -{ /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3 */ - { 0 } -}, + {/* ARM_t2DMB, ARM_INS_DMB: dmb */ + {0}}, -{ /* ARM_t2DMB, ARM_INS_DMB: dmb */ - { 0 } -}, + {/* ARM_t2DSB, ARM_INS_DFB: dfb */ + {0}}, -{ /* ARM_t2DSB, ARM_INS_DFB: dfb */ - { 0 } -}, + {/* ARM_t2EORri, ARM_INS_EOR: eor */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2EORri, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2EORrr, ARM_INS_EOR: eor */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2EORrr, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2EORrs, ARM_INS_EOR: eor */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2EORrs, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2HINT, ARM_INS_CSDB: csdb */ + {0}}, -{ /* ARM_t2HINT, ARM_INS_CSDB: csdb */ - { 0 } -}, + {/* ARM_t2HVC, ARM_INS_HVC: hvc */ + {0}}, -{ /* ARM_t2HVC, ARM_INS_HVC: hvc */ - { 0 } -}, + {/* ARM_t2ISB, ARM_INS_ISB: isb */ + {0}}, -{ /* ARM_t2ISB, ARM_INS_ISB: isb */ - { 0 } -}, + {/* ARM_t2IT, ARM_INS_IT: it */ + {0}}, -{ /* ARM_t2IT, ARM_INS_IT: it */ - { 0 } -}, + {/* ARM_t2LDA, ARM_INS_LDA: lda */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDA, ARM_INS_LDA: lda */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDAB, ARM_INS_LDAB: ldab */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDAB, ARM_INS_LDAB: ldab */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDAH, ARM_INS_LDAH: ldah */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDAH, ARM_INS_LDAH: ldah */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC_POST, ARM_INS_LDC: ldc */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC_POST, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDC_PRE, ARM_INS_LDC: ldc */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDMIA, ARM_INS_LDM: ldm */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2LDMIA, ARM_INS_LDM: ldm */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRBs, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRBs, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd */ + {CS_AC_WRITE, CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDREX, ARM_INS_LDREX: ldrex */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDREX, ARM_INS_LDREX: ldrex */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRHs, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRHs, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LDRT, ARM_INS_LDRT: ldrt */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRT, ARM_INS_LDRT: ldrt */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDR_POST, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDR_POST, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDR_PRE, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDR_PRE, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRi12, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRi12, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRi8, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRi8, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRpci, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2LDRpci, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2LDRs, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LDRs, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LSLri, ARM_INS_LSL: lsl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LSLri, ARM_INS_LSL: lsl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LSLrr, ARM_INS_LSL: lsl */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LSLrr, ARM_INS_LSL: lsl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2LSRri, ARM_INS_LSR: lsr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2LSRri, ARM_INS_LSR: lsr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2LSRrr, ARM_INS_LSR: lsr */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2LSRrr, ARM_INS_LSR: lsr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2MCR, ARM_INS_MCR: mcr */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_t2MCR, ARM_INS_MCR: mcr */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_t2MCR2, ARM_INS_MCR2: mcr2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_t2MCR2, ARM_INS_MCR2: mcr2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_t2MCRR, ARM_INS_MCRR: mcrr */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2MCRR, ARM_INS_MCRR: mcrr */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2MLA, ARM_INS_MLA: mla */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2MLA, ARM_INS_MLA: mla */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2MLS, ARM_INS_MLS: mls */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2MLS, ARM_INS_MLS: mls */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2MOVTi16, ARM_INS_MOVT: movt */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_t2MOVTi16, ARM_INS_MOVT: movt */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_t2MOVi, ARM_INS_MOV: mov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2MOVi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2MOVi16, ARM_INS_MOV: mov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2MOVi16, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2MOVr, ARM_INS_LSL: lsl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2MOVr, ARM_INS_LSL: lsl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd $rm #1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd $rm #1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd $rm #1 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd $rm #1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2MRC, ARM_INS_MRC: mrc */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_t2MRC, ARM_INS_MRC: mrc */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_t2MRC2, ARM_INS_MRC2: mrc2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, + CS_AC_IGNORE, 0}}, -{ /* ARM_t2MRC2, ARM_INS_MRC2: mrc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, + {/* ARM_t2MRRC, ARM_INS_MRRC: mrrc */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2MRRC, ARM_INS_MRRC: mrrc */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2 */ + {CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2MRS_AR, ARM_INS_MRS: mrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2MRS_AR, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2MRS_M, ARM_INS_MRS: mrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2MRS_M, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2MRSbanked, ARM_INS_MRS: mrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2MRSbanked, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2MSR_AR, ARM_INS_MSR: msr */ + {CS_AC_READ, 0}}, -{ /* ARM_t2MSR_AR, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2MSR_M, ARM_INS_MSR: msr */ + {CS_AC_READ, 0}}, -{ /* ARM_t2MSR_M, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2MSRbanked, ARM_INS_MSR: msr */ + {CS_AC_READ, 0}}, -{ /* ARM_t2MSRbanked, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2MUL, ARM_INS_MUL: mul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2MUL, ARM_INS_MUL: mul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2MVNi, ARM_INS_MOV: mov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2MVNi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2MVNr, ARM_INS_MVN: mvn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2MVNr, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2MVNs, ARM_INS_MVN: mvn */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2MVNs, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2ORNri, ARM_INS_ORN: orn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ORNri, ARM_INS_ORN: orn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ORNrr, ARM_INS_ORN: orn */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2ORNrr, ARM_INS_ORN: orn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2ORNrs, ARM_INS_ORN: orn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ORNrs, ARM_INS_ORN: orn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ORRri, ARM_INS_ORN: orn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ORRri, ARM_INS_ORN: orn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2ORRrr, ARM_INS_ORR: orr */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2ORRrr, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2ORRrs, ARM_INS_ORR: orr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2ORRrs, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2PLDWi12, ARM_INS_PLDW: pldw */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLDWi12, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLDWi8, ARM_INS_PLDW: pldw */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLDWi8, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLDWs, ARM_INS_PLDW: pldw */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLDWs, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLDi12, ARM_INS_PLD: pld */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLDi12, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLDi8, ARM_INS_PLD: pld */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLDi8, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLDpci, ARM_INS_PLD: pld */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLDpci, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLDs, ARM_INS_PLD: pld */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLDs, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLIi12, ARM_INS_PLI: pli */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLIi12, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLIi8, ARM_INS_PLI: pli */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLIi8, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLIpci, ARM_INS_PLI: pli */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLIpci, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2PLIs, ARM_INS_PLI: pli */ + {CS_AC_READ, 0}}, -{ /* ARM_t2PLIs, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2QADD, ARM_INS_QADD: qadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QADD, ARM_INS_QADD: qadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2QADD16, ARM_INS_QADD16: qadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QADD16, ARM_INS_QADD16: qadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2QADD8, ARM_INS_QADD8: qadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QADD8, ARM_INS_QADD8: qadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2QASX, ARM_INS_QASX: qasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QASX, ARM_INS_QASX: qasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2QDADD, ARM_INS_QDADD: qdadd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QDADD, ARM_INS_QDADD: qdadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2QSAX, ARM_INS_QSAX: qsax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QSAX, ARM_INS_QSAX: qsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2QSUB, ARM_INS_QSUB: qsub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QSUB, ARM_INS_QSUB: qsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2RBIT, ARM_INS_RBIT: rbit */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2RBIT, ARM_INS_RBIT: rbit */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2REV, ARM_INS_REV: rev */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2REV, ARM_INS_REV: rev */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2REV16, ARM_INS_REV16: rev16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2REV16, ARM_INS_REV16: rev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2REVSH, ARM_INS_REVSH: revsh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2REVSH, ARM_INS_REVSH: revsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb */ + {CS_AC_READ, 0}}, -{ /* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb */ + {CS_AC_READ, 0}}, -{ /* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia */ + {CS_AC_READ, 0}}, -{ /* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia */ + {CS_AC_READ, 0}}, -{ /* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2RORri, ARM_INS_ROR: ror */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2RORri, ARM_INS_ROR: ror */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2RORrr, ARM_INS_ROR: ror */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2RORrr, ARM_INS_ROR: ror */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2RRX, ARM_INS_RRX: rrx */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2RRX, ARM_INS_RRX: rrx */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2RSBri, ARM_INS_NEG: neg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2RSBri, ARM_INS_NEG: neg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2RSBrr, ARM_INS_RSB: rsb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2RSBrr, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2RSBrs, ARM_INS_RSB: rsb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2RSBrs, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SADD16, ARM_INS_SADD16: sadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SADD16, ARM_INS_SADD16: sadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SADD8, ARM_INS_SADD8: sadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SADD8, ARM_INS_SADD8: sadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SASX, ARM_INS_SASX: sasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SASX, ARM_INS_SASX: sasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SBCri, ARM_INS_ADC: adc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SBCri, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SBCrr, ARM_INS_SBC: sbc */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SBCrr, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SBCrs, ARM_INS_SBC: sbc */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SBCrs, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SBFX, ARM_INS_SBFX: sbfx */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SBFX, ARM_INS_SBFX: sbfx */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SDIV, ARM_INS_SDIV: sdiv */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SDIV, ARM_INS_SDIV: sdiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SEL, ARM_INS_SEL: sel */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SEL, ARM_INS_SEL: sel */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SETPAN, ARM_INS_SETPAN: setpan */ + {0}}, -{ /* ARM_t2SETPAN, ARM_INS_SETPAN: setpan */ - { 0 } -}, + {/* ARM_t2SG, ARM_INS_SG: sg */ + {0}}, -{ /* ARM_t2SG, ARM_INS_SG: sg */ - { 0 } -}, + {/* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SHASX, ARM_INS_SHASX: shasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SHASX, ARM_INS_SHASX: shasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SHSAX, ARM_INS_SHSAX: shsax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SHSAX, ARM_INS_SHSAX: shsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMC, ARM_INS_SMC: smc */ + {0}}, -{ /* ARM_t2SMC, ARM_INS_SMC: smc */ - { 0 } -}, + {/* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLAD, ARM_INS_SMLAD: smlad */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLAD, ARM_INS_SMLAD: smlad */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLADX, ARM_INS_SMLADX: smladx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLADX, ARM_INS_SMLADX: smladx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLAL, ARM_INS_SMLAL: smlal */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLAL, ARM_INS_SMLAL: smlal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLALD, ARM_INS_SMLALD: smlald */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLALD, ARM_INS_SMLALD: smlald */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMMLA, ARM_INS_SMMLA: smmla */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMMLA, ARM_INS_SMMLA: smmla */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMMLS, ARM_INS_SMMLS: smmls */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMMLS, ARM_INS_SMMLS: smmls */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMMUL, ARM_INS_SMMUL: smmul */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMMUL, ARM_INS_SMMUL: smmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMUAD, ARM_INS_SMUAD: smuad */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMULL, ARM_INS_SMULL: smull */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMULL, ARM_INS_SMULL: smull */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMULTB, ARM_INS_SMULTB: smultb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMULTB, ARM_INS_SMULTB: smultb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMULTT, ARM_INS_SMULTT: smultt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMULTT, ARM_INS_SMULTT: smultt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMUSD, ARM_INS_SMUSD: smusd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMUSD, ARM_INS_SMUSD: smusd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb */ + {0}}, -{ /* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb */ - { 0 } -}, + {/* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb */ + {0}}, -{ /* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb */ - { 0 } -}, + {/* ARM_t2SRSIA, ARM_INS_SRSIA: srsia */ + {0}}, -{ /* ARM_t2SRSIA, ARM_INS_SRSIA: srsia */ - { 0 } -}, + {/* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia */ + {0}}, -{ /* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia */ - { 0 } -}, + {/* ARM_t2SSAT, ARM_INS_SSAT: ssat */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2SSAT, ARM_INS_SSAT: ssat */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16 */ + {CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0}}, -{ /* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16 */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } -}, + {/* ARM_t2SSAX, ARM_INS_SSAX: ssax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SSAX, ARM_INS_SSAX: ssax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC2_POST, ARM_INS_STC2: stc2 */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC2_POST, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC2_PRE, ARM_INS_STC2: stc2 */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STCL_POST, ARM_INS_STCL: stcl */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STCL_POST, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STCL_PRE, ARM_INS_STCL: stcl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC_OFFSET, ARM_INS_STC: stc */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC_OFFSET, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC_OPTION, ARM_INS_STC: stc */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC_OPTION, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC_POST, ARM_INS_STC: stc */ + {CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC_POST, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STC_PRE, ARM_INS_STC: stc */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STC_PRE, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STL, ARM_INS_STL: stl */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STL, ARM_INS_STL: stl */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STLB, ARM_INS_STLB: stlb */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STLB, ARM_INS_STLB: stlb */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STLEX, ARM_INS_STLEX: stlex */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STLEX, ARM_INS_STLEX: stlex */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STLH, ARM_INS_STLH: stlh */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STLH, ARM_INS_STLH: stlh */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STMDB, ARM_INS_STMDB: stmdb */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STMDB, ARM_INS_STMDB: stmdb */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STMDB_UPD, ARM_INS_PUSH: push */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STMDB_UPD, ARM_INS_PUSH: push */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STMIA, ARM_INS_STM: stm */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STMIA, ARM_INS_STM: stm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STMIA_UPD, ARM_INS_STM: stm */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2STMIA_UPD, ARM_INS_STM: stm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2STRBT, ARM_INS_STRBT: strbt */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2STRBT, ARM_INS_STRBT: strbt */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRB_POST, ARM_INS_STRB: strb */ + {CS_AC_READ, 0}}, -{ /* ARM_t2STRB_POST, ARM_INS_STRB: strb */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2STRB_PRE, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRB_PRE, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRBi12, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRBi12, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRBi8, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRBi8, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRBs, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRBs, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRD_POST, ARM_INS_STRD: strd */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STRD_POST, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STRD_PRE, ARM_INS_STRD: strd */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STRD_PRE, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STRDi8, ARM_INS_STRD: strd */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STRDi8, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STREX, ARM_INS_STREX: strex */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2STREX, ARM_INS_STREX: strex */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2STREXB, ARM_INS_STREXB: strexb */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STREXB, ARM_INS_STREXB: strexb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STREXD, ARM_INS_STREXD: strexd */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STREXD, ARM_INS_STREXD: strexd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STREXH, ARM_INS_STREXH: strexh */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2STREXH, ARM_INS_STREXH: strexh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2STRHT, ARM_INS_STRHT: strht */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2STRHT, ARM_INS_STRHT: strht */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRH_POST, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRH_POST, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRH_PRE, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRH_PRE, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRHi12, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRHi12, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRHi8, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRHi8, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRHs, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRHs, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRT, ARM_INS_STRT: strt */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRT, ARM_INS_STRT: strt */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STR_POST, ARM_INS_STR: str */ + {CS_AC_READ, 0}}, -{ /* ARM_t2STR_POST, ARM_INS_STR: str */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2STR_PRE, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STR_PRE, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRi12, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRi12, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRi8, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRi8, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2STRs, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_t2STRs, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_t2SUBS_PC_LR, ARM_INS_ERET: eret */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SUBS_PC_LR, ARM_INS_ERET: eret */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SUBri, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SUBri, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SUBri12, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SUBri12, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SUBrr, ARM_INS_SUB: sub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2SUBrr, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2SUBrs, ARM_INS_SUB: sub */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SUBrs, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SXTB, ARM_INS_SXTB: sxtb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SXTB, ARM_INS_SXTB: sxtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2SXTH, ARM_INS_SXTH: sxth */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2SXTH, ARM_INS_SXTH: sxth */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2TBB, ARM_INS_TBB: tbb */ + {CS_AC_READ, 0}}, -{ /* ARM_t2TBB, ARM_INS_TBB: tbb */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2TBH, ARM_INS_TBH: tbh */ + {CS_AC_READ, 0}}, -{ /* ARM_t2TBH, ARM_INS_TBH: tbh */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2TEQri, ARM_INS_TEQ: teq */ + {CS_AC_READ, 0}}, -{ /* ARM_t2TEQri, ARM_INS_TEQ: teq */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2TEQrr, ARM_INS_TEQ: teq */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2TEQrr, ARM_INS_TEQ: teq */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2TEQrs, ARM_INS_TEQ: teq */ + {CS_AC_READ, 0}}, -{ /* ARM_t2TEQrs, ARM_INS_TEQ: teq */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2TSB, ARM_INS_TSB: tsb */ + {0}}, -{ /* ARM_t2TSB, ARM_INS_TSB: tsb */ - { 0 } -}, + {/* ARM_t2TSTri, ARM_INS_TST: tst */ + {CS_AC_READ, 0}}, -{ /* ARM_t2TSTri, ARM_INS_TST: tst */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2TSTrr, ARM_INS_TST: tst */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2TSTrr, ARM_INS_TST: tst */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2TSTrs, ARM_INS_TST: tst */ + {CS_AC_READ, 0}}, -{ /* ARM_t2TSTrs, ARM_INS_TST: tst */ - { CS_AC_READ, 0 } -}, + {/* ARM_t2TT, ARM_INS_TT: tt */ + {0}}, -{ /* ARM_t2TT, ARM_INS_TT: tt */ - { 0 } -}, + {/* ARM_t2TTA, ARM_INS_TTA: tta */ + {0}}, -{ /* ARM_t2TTA, ARM_INS_TTA: tta */ - { 0 } -}, + {/* ARM_t2TTAT, ARM_INS_TTAT: ttat */ + {0}}, -{ /* ARM_t2TTAT, ARM_INS_TTAT: ttat */ - { 0 } -}, + {/* ARM_t2TTT, ARM_INS_TTT: ttt */ + {0}}, -{ /* ARM_t2TTT, ARM_INS_TTT: ttt */ - { 0 } -}, + {/* ARM_t2UADD16, ARM_INS_UADD16: uadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UADD16, ARM_INS_UADD16: uadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UADD8, ARM_INS_UADD8: uadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UADD8, ARM_INS_UADD8: uadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UASX, ARM_INS_UASX: uasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UASX, ARM_INS_UASX: uasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UBFX, ARM_INS_UBFX: ubfx */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2UBFX, ARM_INS_UBFX: ubfx */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2UDF, ARM_INS_UDF: udf */ + {0}}, -{ /* ARM_t2UDF, ARM_INS_UDF: udf */ - { 0 } -}, + {/* ARM_t2UDIV, ARM_INS_UDIV: udiv */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UDIV, ARM_INS_UDIV: udiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UHASX, ARM_INS_UHASX: uhasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UHASX, ARM_INS_UHASX: uhasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UMAAL, ARM_INS_UMAAL: umaal */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UMAAL, ARM_INS_UMAAL: umaal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UMLAL, ARM_INS_UMLAL: umlal */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UMLAL, ARM_INS_UMLAL: umlal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UMULL, ARM_INS_UMULL: umull */ + {CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UMULL, ARM_INS_UMULL: umull */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UQASX, ARM_INS_UQASX: uqasx */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UQASX, ARM_INS_UQASX: uqasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2USAD8, ARM_INS_USAD8: usad8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2USAD8, ARM_INS_USAD8: usad8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2USADA8, ARM_INS_USADA8: usada8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2USADA8, ARM_INS_USADA8: usada8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2USAT, ARM_INS_USAT: usat */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2USAT, ARM_INS_USAT: usat */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2USAT16, ARM_INS_USAT16: usat16 */ + {CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0}}, -{ /* ARM_t2USAT16, ARM_INS_USAT16: usat16 */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } -}, + {/* ARM_t2USAX, ARM_INS_USAX: usax */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2USAX, ARM_INS_USAX: usax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2USUB16, ARM_INS_USUB16: usub16 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2USUB16, ARM_INS_USUB16: usub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2USUB8, ARM_INS_USUB8: usub8 */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_t2USUB8, ARM_INS_USUB8: usub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_t2UXTB, ARM_INS_UXTB: uxtb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2UXTB, ARM_INS_UXTB: uxtb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16 */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16 */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_t2UXTH, ARM_INS_UXTH: uxth */ + {CS_AC_WRITE, 0}}, -{ /* ARM_t2UXTH, ARM_INS_UXTH: uxth */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tADC, ARM_INS_ADC: adc */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tADC, ARM_INS_ADC: adc */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tADDhirr, ARM_INS_ADD: add */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tADDhirr, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tADDi3, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tADDi3, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tADDi8, ARM_INS_ADD: add */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_tADDi8, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_tADDrSP, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_tADDrSP, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_tADDrSPi, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tADDrSPi, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tADDrr, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_tADDrr, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_tADDspi, ARM_INS_ADD: add */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_tADDspi, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_tADDspr, ARM_INS_ADD: add */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tADDspr, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tADR, ARM_INS_ADR: adr */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tADR, ARM_INS_ADR: adr */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tAND, ARM_INS_AND: and */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tAND, ARM_INS_AND: and */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tASRri, ARM_INS_ASR: asr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tASRri, ARM_INS_ASR: asr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tASRrr, ARM_INS_ASR: asr */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tASRrr, ARM_INS_ASR: asr */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tB, ARM_INS_B: b */ + {0}}, -{ /* ARM_tB, ARM_INS_B: b */ - { 0 } -}, + {/* ARM_tBIC, ARM_INS_BIC: bic */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tBIC, ARM_INS_BIC: bic */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tBKPT, ARM_INS_BKPT: bkpt */ + {0}}, -{ /* ARM_tBKPT, ARM_INS_BKPT: bkpt */ - { 0 } -}, + {/* ARM_tBL, ARM_INS_BL: bl */ + {0}}, -{ /* ARM_tBL, ARM_INS_BL: bl */ - { 0 } -}, + {/* ARM_tBLXNSr, ARM_INS_BLXNS: blxns */ + {0}}, -{ /* ARM_tBLXNSr, ARM_INS_BLXNS: blxns */ - { 0 } -}, + {/* ARM_tBLXi, ARM_INS_BLX: blx */ + {0}}, -{ /* ARM_tBLXi, ARM_INS_BLX: blx */ - { 0 } -}, + {/* ARM_tBLXr, ARM_INS_BLX: blx */ + {CS_AC_READ, 0}}, -{ /* ARM_tBLXr, ARM_INS_BLX: blx */ - { CS_AC_READ, 0 } -}, + {/* ARM_tBX, ARM_INS_BX: bx */ + {CS_AC_READ, 0}}, -{ /* ARM_tBX, ARM_INS_BX: bx */ - { CS_AC_READ, 0 } -}, + {/* ARM_tBXNS, ARM_INS_BXNS: bxns */ + {0}}, -{ /* ARM_tBXNS, ARM_INS_BXNS: bxns */ - { 0 } -}, + {/* ARM_tBcc, ARM_INS_B: b */ + {0}}, -{ /* ARM_tBcc, ARM_INS_B: b */ - { 0 } -}, + {/* ARM_tCBNZ, ARM_INS_CBNZ: cbnz */ + {CS_AC_READ, 0}}, -{ /* ARM_tCBNZ, ARM_INS_CBNZ: cbnz */ - { CS_AC_READ, 0 } -}, + {/* ARM_tCBZ, ARM_INS_CBZ: cbz */ + {CS_AC_READ, 0}}, -{ /* ARM_tCBZ, ARM_INS_CBZ: cbz */ - { CS_AC_READ, 0 } -}, + {/* ARM_tCMNz, ARM_INS_CMN: cmn */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_tCMNz, ARM_INS_CMN: cmn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_tCMPhir, ARM_INS_CMP: cmp */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_tCMPhir, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_tCMPi8, ARM_INS_CMP: cmp */ + {CS_AC_READ, 0}}, -{ /* ARM_tCMPi8, ARM_INS_CMP: cmp */ - { CS_AC_READ, 0 } -}, + {/* ARM_tCMPr, ARM_INS_CMP: cmp */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_tCMPr, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_tCPS, ARM_INS_CPS: cps */ + {0}}, -{ /* ARM_tCPS, ARM_INS_CPS: cps */ - { 0 } -}, + {/* ARM_tEOR, ARM_INS_EOR: eor */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tEOR, ARM_INS_EOR: eor */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tHINT, ARM_INS_HINT: hint */ + {0}}, -{ /* ARM_tHINT, ARM_INS_HINT: hint */ - { 0 } -}, + {/* ARM_tHLT, ARM_INS_HLT: hlt */ + {0}}, -{ /* ARM_tHLT, ARM_INS_HLT: hlt */ - { 0 } -}, + {/* ARM_tLDMIA, ARM_INS_LDM: ldm */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tLDMIA, ARM_INS_LDM: ldm */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tLDRBi, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tLDRBi, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tLDRBr, ARM_INS_LDRB: ldrb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tLDRBr, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tLDRHi, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tLDRHi, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tLDRHr, ARM_INS_LDRH: ldrh */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tLDRHr, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tLDRi, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tLDRi, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tLDRpci, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tLDRpci, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tLDRr, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tLDRr, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tLDRspi, ARM_INS_LDR: ldr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tLDRspi, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tLSLri, ARM_INS_LSL: lsl */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tLSLri, ARM_INS_LSL: lsl */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tLSLrr, ARM_INS_LSL: lsl */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tLSLrr, ARM_INS_LSL: lsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tLSRri, ARM_INS_LSR: lsr */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tLSRri, ARM_INS_LSR: lsr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tLSRrr, ARM_INS_LSR: lsr */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tLSRrr, ARM_INS_LSR: lsr */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tMOVSr, ARM_INS_MOVS: movs */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tMOVSr, ARM_INS_MOVS: movs */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tMOVi8, ARM_INS_MOV: mov */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tMOVi8, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tMOVr, ARM_INS_MOV: mov */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tMOVr, ARM_INS_MOV: mov */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tMUL, ARM_INS_MUL: mul */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_tMUL, ARM_INS_MUL: mul */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_tMVN, ARM_INS_MVN: mvn */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tMVN, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tORR, ARM_INS_ORR: orr */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tORR, ARM_INS_ORR: orr */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tPOP, ARM_INS_POP: pop */ + {CS_AC_WRITE, 0}}, -{ /* ARM_tPOP, ARM_INS_POP: pop */ - { CS_AC_WRITE, 0 } -}, + {/* ARM_tPUSH, ARM_INS_PUSH: push */ + {CS_AC_READ, 0}}, -{ /* ARM_tPUSH, ARM_INS_PUSH: push */ - { CS_AC_READ, 0 } -}, + {/* ARM_tREV, ARM_INS_REV: rev */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tREV, ARM_INS_REV: rev */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tREV16, ARM_INS_REV16: rev16 */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tREV16, ARM_INS_REV16: rev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tREVSH, ARM_INS_REVSH: revsh */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tREVSH, ARM_INS_REVSH: revsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tROR, ARM_INS_ROR: ror */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tROR, ARM_INS_ROR: ror */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tRSB, ARM_INS_NEG: neg */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tRSB, ARM_INS_NEG: neg */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tSBC, ARM_INS_SBC: sbc */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tSBC, ARM_INS_SBC: sbc */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tSETEND, ARM_INS_SETEND: setend */ + {0}}, -{ /* ARM_tSETEND, ARM_INS_SETEND: setend */ - { 0 } -}, + {/* ARM_tSTMIA_UPD, ARM_INS_STM: stm */ + {CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tSTMIA_UPD, ARM_INS_STM: stm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tSTRBi, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_tSTRBi, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_tSTRBr, ARM_INS_STRB: strb */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_tSTRBr, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_tSTRHi, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_tSTRHi, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_tSTRHr, ARM_INS_STRH: strh */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_tSTRHr, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_tSTRi, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_tSTRi, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_tSTRr, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_tSTRr, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_tSTRspi, ARM_INS_STR: str */ + {CS_AC_READ, CS_AC_WRITE, 0}}, -{ /* ARM_tSTRspi, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, + {/* ARM_tSUBi3, ARM_INS_ADD: add */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tSUBi3, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tSUBi8, ARM_INS_ADD: add */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_tSUBi8, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_tSUBrr, ARM_INS_SUB: sub */ + {CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_tSUBrr, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_tSUBspi, ARM_INS_ADD: add */ + {CS_AC_READ | CS_AC_WRITE, 0}}, -{ /* ARM_tSUBspi, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, + {/* ARM_tSVC, ARM_INS_SVC: svc */ + {0}}, -{ /* ARM_tSVC, ARM_INS_SVC: svc */ - { 0 } -}, + {/* ARM_tSXTB, ARM_INS_SXTB: sxtb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tSXTB, ARM_INS_SXTB: sxtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tSXTH, ARM_INS_SXTH: sxth */ + {CS_AC_WRITE, CS_AC_READ, 0}}, -{ /* ARM_tSXTH, ARM_INS_SXTH: sxth */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tTRAP, ARM_INS_TRAP: trap */ + {0}}, -{ /* ARM_tTRAP, ARM_INS_TRAP: trap */ - { 0 } -}, + {/* ARM_tTST, ARM_INS_TST: tst */ + {CS_AC_READ, CS_AC_READ, 0}}, -{ /* ARM_tTST, ARM_INS_TST: tst */ - { CS_AC_READ, CS_AC_READ, 0 } -}, + {/* ARM_tUDF, ARM_INS_UDF: udf */ + {0}}, -{ /* ARM_tUDF, ARM_INS_UDF: udf */ - { 0 } -}, - -{ /* ARM_tUXTB, ARM_INS_UXTB: uxtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, - -{ /* ARM_tUXTH, ARM_INS_UXTH: uxth */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, + {/* ARM_tUXTB, ARM_INS_UXTB: uxtb */ + {CS_AC_WRITE, CS_AC_READ, 0}}, + {/* ARM_tUXTH, ARM_INS_UXTH: uxth */ + {CS_AC_WRITE, CS_AC_READ, 0}}, diff --git a/arch/ARM/ARMModule.c b/arch/ARM/ARMModule.c index 0ecadd8025..335133bc69 100644 --- a/arch/ARM/ARMModule.c +++ b/arch/ARM/ARMModule.c @@ -3,61 +3,59 @@ #ifdef CAPSTONE_HAS_ARM -#include "../../cs_priv.h" +#include "ARMModule.h" #include "../../MCRegisterInfo.h" +#include "../../cs_priv.h" #include "ARMDisassembler.h" #include "ARMInstPrinter.h" #include "ARMMapping.h" -#include "ARMModule.h" -cs_err ARM_global_init(cs_struct *ud) -{ - MCRegisterInfo *mri; - mri = cs_mem_malloc(sizeof(*mri)); - - ARM_init(mri); - ARM_getRegName(ud, 0); // use default get_regname - - ud->printer = ARM_printInst; - ud->printer_info = mri; - ud->reg_name = ARM_reg_name; - ud->insn_id = ARM_get_insn_id; - ud->insn_name = ARM_insn_name; - ud->group_name = ARM_group_name; - ud->post_printer = ARM_post_printer; +cs_err ARM_global_init(cs_struct *ud) { + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + ARM_init(mri); + ARM_getRegName(ud, 0); // use default get_regname + + ud->printer = ARM_printInst; + ud->printer_info = mri; + ud->reg_name = ARM_reg_name; + ud->insn_id = ARM_get_insn_id; + ud->insn_name = ARM_insn_name; + ud->group_name = ARM_group_name; + ud->post_printer = ARM_post_printer; #ifndef CAPSTONE_DIET - ud->reg_access = ARM_reg_access; + ud->reg_access = ARM_reg_access; #endif - if (ud->mode & CS_MODE_THUMB) - ud->disasm = Thumb_getInstruction; - else - ud->disasm = ARM_getInstruction; + if (ud->mode & CS_MODE_THUMB) + ud->disasm = Thumb_getInstruction; + else + ud->disasm = ARM_getInstruction; - return CS_ERR_OK; + return CS_ERR_OK; } -cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value) -{ - switch(type) { - case CS_OPT_MODE: - if (value & CS_MODE_THUMB) - handle->disasm = Thumb_getInstruction; - else - handle->disasm = ARM_getInstruction; - - handle->mode = (cs_mode)value; - - break; - case CS_OPT_SYNTAX: - ARM_getRegName(handle, (int)value); - handle->syntax = (int)value; - break; - default: - break; - } - - return CS_ERR_OK; +cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value) { + switch (type) { + case CS_OPT_MODE: + if (value & CS_MODE_THUMB) + handle->disasm = Thumb_getInstruction; + else + handle->disasm = ARM_getInstruction; + + handle->mode = (cs_mode)value; + + break; + case CS_OPT_SYNTAX: + ARM_getRegName(handle, (int)value); + handle->syntax = (int)value; + break; + default: + break; + } + + return CS_ERR_OK; } #endif diff --git a/arch/ARM/CapstoneARMModule.h b/arch/ARM/CapstoneARMModule.h new file mode 100644 index 0000000000..7e33461ec9 --- /dev/null +++ b/arch/ARM/CapstoneARMModule.h @@ -0,0 +1,6161 @@ +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +static unsigned std_max(unsigned a, unsigned b) { return (a > b) ? a : b; } +static unsigned std_min(unsigned a, unsigned b) { return (a < b) ? a : b; } +static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodetGPROddRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodetGPREvenRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRspRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMQQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, + unsigned Insn, + uint64_t Adddress, + void *Decoder); + +static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVMOVModImmInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMVEModImmInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMVEVADCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMveAddrModeQ(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder, + int shift); + +static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVCVTImmOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, + unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeT2Imm7S4(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2AddrModeImm7s4(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeT2Imm7(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder, unsigned shift); + +static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeTAddrModeImm7(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + unsigned shift); + +static DecodeStatus DecodeT2AddrModeImm7(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + int shift, int WriteBack); + +static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2Adr(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder); + +static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBFLabelOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + bool isSigned, bool isNeg, + bool zeroPermitted, int size); + +static DecodeStatus DecodeBFAfterTargetOperand(MCInst *Inst, unsigned val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePredNoALOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeLOLoop(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLongShiftOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVSCCLRM(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVPTMaskOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeVpredROperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + bool Writeback); + +static DecodeStatus DecodeMVE_MEM_1_pre(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + int shift); + +static DecodeStatus DecodeMVE_MEM_2_pre(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + int shift); + +static DecodeStatus DecodeMVE_MEM_3_pre(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + int shift); + +static DecodeStatus DecodePowerTwoOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + unsigned MinLog, unsigned MaxLog); + +static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder, + unsigned start); + +static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMVEVCMP(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder, unsigned scalar, + void *omitted); + +static DecodeStatus DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMVEVPNOT(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMVEOverlappingLongShift(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeT2AddSubSPImm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +#define GET_INSTRINFO_ENUM +#define GET_REGINFO_ENUM +#define MIPS_GET_DISASSEMBLER +#include "../../sync/logger.h" +#include "ARMGenDisassemblerTables.inc" + +FieldFromInstruction(fieldFromInstruction_2, uint16_t) + DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, + uint16_t) DecodeInstruction(decodeInstruction_2, + fieldFromInstruction_2, + decodeToMCInst_2, uint16_t) + + FieldFromInstruction(fieldFromInstruction_4, uint32_t) + DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) + DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, + decodeToMCInst_4, uint32_t) + + static const uint16_t GPRDecoderTable[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, + ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, + ARM_R12, ARM_SP, ARM_LR, ARM_PC}; + +static const uint16_t CLRMGPRDecoderTable[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, 0, ARM_LR, ARM_APSR}; + +static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 15) + return MCDisassembler_Fail; + + unsigned Register = GPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 15) + return MCDisassembler_Fail; + + unsigned Register = CLRMGPRDecoderTable[RegNo]; + if (Register == 0) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + if (RegNo == 15) + S = MCDisassembler_SoftFail; + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + + return S; +} + +static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + if (RegNo == 15) { + MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); + return MCDisassembler_Success; + } + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + +static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + if (RegNo == 15) { + MCOperand_CreateReg0(Inst, ARM_ZR); + return MCDisassembler_Success; + } + + if (RegNo == 13) + Check(&S, MCDisassembler_SoftFail); + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + +static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + if (RegNo == 13) + return MCDisassembler_Fail; + Check(&S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + +static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const uint16_t GPRPairDecoderTable[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, + ARM_R8_R9, ARM_R10_R11, ARM_R12_SP}; + +static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + // According to the Arm ARM RegNo = 14 is undefined, but we return fail + // rather than SoftFail as there is no GPRPair table entry for index 7. + if (RegNo > 13) + return MCDisassembler_Fail; + + if (RegNo & 1) + S = MCDisassembler_SoftFail; + + unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2]; + MCOperand_CreateReg0(Inst, RegisterPair); + return S; +} + +static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 13) + return MCDisassembler_Fail; + + unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2]; + MCOperand_CreateReg0(Inst, RegisterPair); + + if ((RegNo & 1) || RegNo > 10) + return MCDisassembler_SoftFail; + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRspRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo != 13) + return MCDisassembler_Fail; + + unsigned Register = GPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + unsigned Register = 0; + switch (RegNo) { + case 0: + Register = ARM_R0; + break; + case 1: + Register = ARM_R1; + break; + case 2: + Register = ARM_R2; + break; + case 3: + Register = ARM_R3; + break; + case 9: + Register = ARM_R9; + break; + case 12: + Register = ARM_R12; + break; + default: + return MCDisassembler_Fail; + } + + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + /* Ignored bit flags */ + + if ((RegNo == 13 && !(Inst->csh->mode & CS_MODE_V8)) || RegNo == 15) + S = MCDisassembler_SoftFail; + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + +static const uint16_t SPRDecoderTable[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, + ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, + ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31}; + +static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Register = SPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const uint16_t DPRDecoderTable[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, + ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, + ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31}; + +static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + /* Ignored bit flags */ + + bool hasD32 = true; + + if (RegNo > 31 || (!hasD32 && RegNo > 15)) + return MCDisassembler_Fail; + + unsigned Register = DPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeSPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 15) + return MCDisassembler_Fail; + return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 15) + return MCDisassembler_Fail; + return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const uint16_t QPRDecoderTable[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, + ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15}; + +static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31 || (RegNo & 1) != 0) + return MCDisassembler_Fail; + RegNo >>= 1; + + unsigned Register = QPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static const uint16_t DPairDecoderTable[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, + ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, + ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, + ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, + ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, + ARM_Q15}; + +static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 30) + return MCDisassembler_Fail; + + unsigned Register = DPairDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static const uint16_t DPairSpacedDecoderTable[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, + ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, + ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, + ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, + ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, + ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31}; + +static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 29) + return MCDisassembler_Fail; + + unsigned Register = DPairSpacedDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + if (Val) + MCOperand_CreateReg0(Inst, ARM_CPSR); + else + MCOperand_CreateReg0(Inst, 0); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned type = fieldFromInstruction_4(Val, 5, 2); + unsigned imm = fieldFromInstruction_4(Val, 7, 5); + + // Register-immediate + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + ARM_AM_ShiftOpc Shift = ARM_AM_lsl; + switch (type) { + case 0: + Shift = ARM_AM_lsl; + break; + case 1: + Shift = ARM_AM_lsr; + break; + case 2: + Shift = ARM_AM_asr; + break; + case 3: + Shift = ARM_AM_ror; + break; + } + + if (Shift == ARM_AM_ror && imm == 0) + Shift = ARM_AM_rrx; + + unsigned Op = Shift | (imm << 3); + MCOperand_CreateImm0(Inst, Op); + + return S; +} + +static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned type = fieldFromInstruction_4(Val, 5, 2); + unsigned Rs = fieldFromInstruction_4(Val, 8, 4); + + // Register-register + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) + return MCDisassembler_Fail; + + ARM_AM_ShiftOpc Shift = ARM_AM_lsl; + switch (type) { + case 0: + Shift = ARM_AM_lsl; + break; + case 1: + Shift = ARM_AM_lsr; + break; + case 2: + Shift = ARM_AM_asr; + break; + case 3: + Shift = ARM_AM_ror; + break; + } + + MCOperand_CreateImm0(Inst, Shift); + + return S; +} + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + unsigned i; + DecodeStatus S = MCDisassembler_Success; + unsigned opcode; + bool NeedDisjointWriteback = false; + unsigned WritebackReg = 0; + + opcode = MCInst_getOpcode(Inst); + switch (opcode) { + default: + break; + + case ARM_LDMIA_UPD: + case ARM_LDMDB_UPD: + case ARM_LDMIB_UPD: + case ARM_LDMDA_UPD: + case ARM_t2LDMIA_UPD: + case ARM_t2LDMDB_UPD: + case ARM_t2STMIA_UPD: + case ARM_t2STMDB_UPD: + NeedDisjointWriteback = true; + WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0)); + break; + } + + // Empty register lists are not allowed. + if (Val == 0) + return MCDisassembler_Fail; + + for (i = 0; i < 16; ++i) { + if (Val & (1 << i)) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) + return MCDisassembler_Fail; + + // Writeback not allowed if Rn is in the target list. + if (NeedDisjointWriteback && + WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size - 1]))) + Check(&S, MCDisassembler_SoftFail); + } + } + + return S; +} + +static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Vd = fieldFromInstruction_4(Val, 8, 5); + unsigned regs = fieldFromInstruction_4(Val, 0, 8); + + // In case of unpredictable encoding, tweak the operands. + if (regs == 0 || (Vd + regs) > 32) { + regs = Vd + regs > 32 ? 32 - Vd : regs; + regs = std_max(1u, regs); + S = MCDisassembler_SoftFail; + } + + if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + for (unsigned i = 0; i < (regs - 1); ++i) { + if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Vd = fieldFromInstruction_4(Val, 8, 5); + unsigned regs = fieldFromInstruction_4(Val, 1, 7); + + // In case of unpredictable encoding, tweak the operands. + if (regs == 0 || regs > 16 || (Vd + regs) > 32) { + regs = Vd + regs > 32 ? 32 - Vd : regs; + regs = std_max(1u, regs); + regs = std_min(16u, regs); + S = MCDisassembler_SoftFail; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + for (unsigned i = 0; i < (regs - 1); ++i) { + if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + // This operand encodes a mask of contiguous zeros between a specified MSB + // and LSB. To decode it, we create the mask of all bits MSB-and-lower, + // the mask of all bits LSB-and-lower, and then xor them to create + // the mask of that's all ones on [msb, lsb]. Finally we not it to + // create the final mask. + unsigned msb = fieldFromInstruction_4(Val, 5, 5); + unsigned lsb = fieldFromInstruction_4(Val, 0, 5); + + DecodeStatus S = MCDisassembler_Success; + if (lsb > msb) { + Check(&S, MCDisassembler_SoftFail); + // The check above will cause the warning for the "potentially undefined + // instruction encoding" but we can't build a bad MCOperand value here + // with a lsb > msb or else printing the MCInst will cause a crash. + lsb = msb; + } + + uint32_t msb_mask = 0xFFFFFFFF; + if (msb != 31) + msb_mask = (1U << (msb + 1)) - 1; + uint32_t lsb_mask = (1U << lsb) - 1; + + MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask)); + return S; +} + +static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); + unsigned coproc = fieldFromInstruction_4(Insn, 8, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + /* Ignored bit flags */ + + switch (MCInst_getOpcode(Inst)) { + case ARM_LDC_OFFSET: + case ARM_LDC_PRE: + case ARM_LDC_POST: + case ARM_LDC_OPTION: + case ARM_LDCL_OFFSET: + case ARM_LDCL_PRE: + case ARM_LDCL_POST: + case ARM_LDCL_OPTION: + case ARM_STC_OFFSET: + case ARM_STC_PRE: + case ARM_STC_POST: + case ARM_STC_OPTION: + case ARM_STCL_OFFSET: + case ARM_STCL_PRE: + case ARM_STCL_POST: + case ARM_STCL_OPTION: + case ARM_t2LDC_OFFSET: + case ARM_t2LDC_PRE: + case ARM_t2LDC_POST: + case ARM_t2LDC_OPTION: + case ARM_t2LDCL_OFFSET: + case ARM_t2LDCL_PRE: + case ARM_t2LDCL_POST: + case ARM_t2LDCL_OPTION: + case ARM_t2STC_OFFSET: + case ARM_t2STC_PRE: + case ARM_t2STC_POST: + case ARM_t2STC_OPTION: + case ARM_t2STCL_OFFSET: + case ARM_t2STCL_PRE: + case ARM_t2STCL_POST: + case ARM_t2STCL_OPTION: + case ARM_t2LDC2_OFFSET: + case ARM_t2LDC2L_OFFSET: + case ARM_t2LDC2_PRE: + case ARM_t2LDC2L_PRE: + case ARM_t2STC2_OFFSET: + case ARM_t2STC2L_OFFSET: + case ARM_t2STC2_PRE: + case ARM_t2STC2L_PRE: + case ARM_LDC2_OFFSET: + case ARM_LDC2L_OFFSET: + case ARM_LDC2_PRE: + case ARM_LDC2L_PRE: + case ARM_STC2_OFFSET: + case ARM_STC2L_OFFSET: + case ARM_STC2_PRE: + case ARM_STC2L_PRE: + case ARM_t2LDC2_OPTION: + case ARM_t2STC2_OPTION: + case ARM_t2LDC2_POST: + case ARM_t2LDC2L_POST: + case ARM_t2STC2_POST: + case ARM_t2STC2L_POST: + case ARM_LDC2_POST: + case ARM_LDC2L_POST: + case ARM_STC2_POST: + case ARM_STC2L_POST: + if (coproc == 0xA || coproc == 0xB) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (Inst->csh->mode & CS_MODE_V8 && coproc != 14) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, coproc); + MCOperand_CreateImm0(Inst, CRd); + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDC2_OFFSET: + case ARM_t2LDC2L_OFFSET: + case ARM_t2LDC2_PRE: + case ARM_t2LDC2L_PRE: + case ARM_t2STC2_OFFSET: + case ARM_t2STC2L_OFFSET: + case ARM_t2STC2_PRE: + case ARM_t2STC2L_PRE: + case ARM_LDC2_OFFSET: + case ARM_LDC2L_OFFSET: + case ARM_LDC2_PRE: + case ARM_LDC2L_PRE: + case ARM_STC2_OFFSET: + case ARM_STC2L_OFFSET: + case ARM_STC2_PRE: + case ARM_STC2L_PRE: + case ARM_t2LDC_OFFSET: + case ARM_t2LDCL_OFFSET: + case ARM_t2LDC_PRE: + case ARM_t2LDCL_PRE: + case ARM_t2STC_OFFSET: + case ARM_t2STCL_OFFSET: + case ARM_t2STC_PRE: + case ARM_t2STCL_PRE: + case ARM_LDC_OFFSET: + case ARM_LDCL_OFFSET: + case ARM_LDC_PRE: + case ARM_LDCL_PRE: + case ARM_STC_OFFSET: + case ARM_STCL_OFFSET: + case ARM_STC_PRE: + case ARM_STCL_PRE: + imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, imm); + MCOperand_CreateImm0(Inst, imm); + break; + case ARM_t2LDC2_POST: + case ARM_t2LDC2L_POST: + case ARM_t2STC2_POST: + case ARM_t2STC2L_POST: + case ARM_LDC2_POST: + case ARM_LDC2L_POST: + case ARM_STC2_POST: + case ARM_STC2L_POST: + case ARM_t2LDC_POST: + case ARM_t2LDCL_POST: + case ARM_t2STC_POST: + case ARM_t2STCL_POST: + case ARM_LDC_POST: + case ARM_LDCL_POST: + case ARM_STC_POST: + case ARM_STCL_POST: + imm |= U << 8; + 0x0; + default: + // The 'option' variant doesn't encode 'U' in the immediate since + // the immediate is unsigned [0,255]. + MCOperand_CreateImm0(Inst, imm); + break; + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_LDC_OFFSET: + case ARM_LDC_PRE: + case ARM_LDC_POST: + case ARM_LDC_OPTION: + case ARM_LDCL_OFFSET: + case ARM_LDCL_PRE: + case ARM_LDCL_POST: + case ARM_LDCL_OPTION: + case ARM_STC_OFFSET: + case ARM_STC_PRE: + case ARM_STC_POST: + case ARM_STC_OPTION: + case ARM_STCL_OFFSET: + case ARM_STCL_PRE: + case ARM_STCL_POST: + case ARM_STCL_OPTION: + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + return S; +} + +static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned reg = fieldFromInstruction_4(Insn, 25, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + + // On stores, the writeback operand precedes Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_STR_POST_IMM: + case ARM_STR_POST_REG: + case ARM_STRB_POST_IMM: + case ARM_STRB_POST_REG: + case ARM_STRT_POST_REG: + case ARM_STRT_POST_IMM: + case ARM_STRBT_POST_REG: + case ARM_STRBT_POST_IMM: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + // On loads, the writeback operand comes after Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_LDR_POST_IMM: + case ARM_LDR_POST_REG: + case ARM_LDRB_POST_IMM: + case ARM_LDRB_POST_REG: + case ARM_LDRBT_POST_REG: + case ARM_LDRBT_POST_IMM: + case ARM_LDRT_POST_REG: + case ARM_LDRT_POST_IMM: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + ARM_AM_AddrOpc Op = ARM_AM_add; + if (!fieldFromInstruction_4(Insn, 23, 1)) + Op = ARM_AM_sub; + + bool writeback = (P == 0) || (W == 1); + unsigned idx_mode = 0; + if (P && writeback) + idx_mode = ARMII_IndexModePre; + else if (!P && writeback) + idx_mode = ARMII_IndexModePost; + + if (writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; // UNPREDICTABLE + + if (reg) { + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + ARM_AM_ShiftOpc Opc = ARM_AM_lsl; + switch (fieldFromInstruction_4(Insn, 5, 2)) { + case 0: + Opc = ARM_AM_lsl; + break; + case 1: + Opc = ARM_AM_lsr; + break; + case 2: + Opc = ARM_AM_asr; + break; + case 3: + Opc = ARM_AM_ror; + break; + default: + return MCDisassembler_Fail; + } + unsigned amt = fieldFromInstruction_4(Insn, 7, 5); + if (Opc == ARM_AM_ror && amt == 0) + Opc = ARM_AM_rrx; + unsigned imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); + + MCOperand_CreateImm0(Inst, imm); + } else { + MCOperand_CreateReg0(Inst, 0); + unsigned tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); + MCOperand_CreateImm0(Inst, tmp); + } + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 13, 4); + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned type = fieldFromInstruction_4(Val, 5, 2); + unsigned imm = fieldFromInstruction_4(Val, 7, 5); + unsigned U = fieldFromInstruction_4(Val, 12, 1); + + ARM_AM_ShiftOpc ShOp = ARM_AM_lsl; + switch (type) { + case 0: + ShOp = ARM_AM_lsl; + break; + case 1: + ShOp = ARM_AM_lsr; + break; + case 2: + ShOp = ARM_AM_asr; + break; + case 3: + ShOp = ARM_AM_ror; + break; + } + + if (ShOp == ARM_AM_ror && imm == 0) + ShOp = ARM_AM_rrx; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + unsigned shift; + if (U) + shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); + else + shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); + MCOperand_CreateImm0(Inst, shift); + + return S; +} + +static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned type = fieldFromInstruction_4(Insn, 22, 1); + unsigned imm = fieldFromInstruction_4(Insn, 8, 4); + unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + unsigned Rt2 = Rt + 1; + + bool writeback = (W == 1) | (P == 0); + + // For {LD,ST}RD, Rt must be even, else undefined. + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + if (Rt & 0x1) + S = MCDisassembler_SoftFail; + break; + default: + break; + } + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + if (P == 0 && W == 1) + S = MCDisassembler_SoftFail; + + if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) + S = MCDisassembler_SoftFail; + if (type && Rm == 15) + S = MCDisassembler_SoftFail; + if (Rt2 == 15) + S = MCDisassembler_SoftFail; + if (!type && fieldFromInstruction_4(Insn, 8, 4)) + S = MCDisassembler_SoftFail; + break; + case ARM_STRH: + case ARM_STRH_PRE: + case ARM_STRH_POST: + if (Rt == 15) + S = MCDisassembler_SoftFail; + if (writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; + if (!type && Rm == 15) + S = MCDisassembler_SoftFail; + break; + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + if (type && Rn == 15) { + if (Rt2 == 15) + S = MCDisassembler_SoftFail; + break; + } + if (P == 0 && W == 1) + S = MCDisassembler_SoftFail; + if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) + S = MCDisassembler_SoftFail; + if (!type && writeback && Rn == 15) + S = MCDisassembler_SoftFail; + if (writeback && (Rn == Rt || Rn == Rt2)) + S = MCDisassembler_SoftFail; + break; + case ARM_LDRH: + case ARM_LDRH_PRE: + case ARM_LDRH_POST: + if (type && Rn == 15) { + if (Rt == 15) + S = MCDisassembler_SoftFail; + break; + } + if (Rt == 15) + S = MCDisassembler_SoftFail; + if (!type && Rm == 15) + S = MCDisassembler_SoftFail; + if (!type && writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; + break; + case ARM_LDRSH: + case ARM_LDRSH_PRE: + case ARM_LDRSH_POST: + case ARM_LDRSB: + case ARM_LDRSB_PRE: + case ARM_LDRSB_POST: + if (type && Rn == 15) { + if (Rt == 15) + S = MCDisassembler_SoftFail; + break; + } + if (type && (Rt == 15 || (writeback && Rn == Rt))) + S = MCDisassembler_SoftFail; + if (!type && (Rt == 15 || Rm == 15)) + S = MCDisassembler_SoftFail; + if (!type && writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; + break; + default: + break; + } + + if (writeback) { // Writeback + if (P) + U |= ARMII_IndexModePre << 9; + else + U |= ARMII_IndexModePost << 9; + + // On stores, the writeback operand precedes Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + case ARM_STRH: + case ARM_STRH_PRE: + case ARM_STRH_POST: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt + 1, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (writeback) { + // On loads, the writeback operand comes after Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + case ARM_LDRH: + case ARM_LDRH_PRE: + case ARM_LDRH_POST: + case ARM_LDRSH: + case ARM_LDRSH_PRE: + case ARM_LDRSH_POST: + case ARM_LDRSB: + case ARM_LDRSB_PRE: + case ARM_LDRSB_POST: + case ARM_LDRHTr: + case ARM_LDRSBTr: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (type) { + MCOperand_CreateReg0(Inst, 0); + MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm); + } else { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, U); + } + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned mode = fieldFromInstruction_4(Insn, 23, 2); + + switch (mode) { + case 0: + mode = ARM_AM_da; + break; + case 1: + mode = ARM_AM_ia; + break; + case 2: + mode = ARM_AM_db; + break; + case 3: + mode = ARM_AM_ib; + break; + } + + MCOperand_CreateImm0(Inst, mode); + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (pred == 0xF) + return DecodeCPSInstruction(Inst, Insn, Address, Decoder); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, + unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); + + if (pred == 0xF) { + // Ambiguous with RFE and SRS + switch (MCInst_getOpcode(Inst)) { + case ARM_LDMDA: + MCInst_setOpcode(Inst, ARM_RFEDA); + break; + case ARM_LDMDA_UPD: + MCInst_setOpcode(Inst, ARM_RFEDA_UPD); + break; + case ARM_LDMDB: + MCInst_setOpcode(Inst, ARM_RFEDB); + break; + case ARM_LDMDB_UPD: + MCInst_setOpcode(Inst, ARM_RFEDB_UPD); + break; + case ARM_LDMIA: + MCInst_setOpcode(Inst, ARM_RFEIA); + break; + case ARM_LDMIA_UPD: + MCInst_setOpcode(Inst, ARM_RFEIA_UPD); + break; + case ARM_LDMIB: + MCInst_setOpcode(Inst, ARM_RFEIB); + break; + case ARM_LDMIB_UPD: + MCInst_setOpcode(Inst, ARM_RFEIB_UPD); + break; + case ARM_STMDA: + MCInst_setOpcode(Inst, ARM_SRSDA); + break; + case ARM_STMDA_UPD: + MCInst_setOpcode(Inst, ARM_SRSDA_UPD); + break; + case ARM_STMDB: + MCInst_setOpcode(Inst, ARM_SRSDB); + break; + case ARM_STMDB_UPD: + MCInst_setOpcode(Inst, ARM_SRSDB_UPD); + break; + case ARM_STMIA: + MCInst_setOpcode(Inst, ARM_SRSIA); + break; + case ARM_STMIA_UPD: + MCInst_setOpcode(Inst, ARM_SRSIA_UPD); + break; + case ARM_STMIB: + MCInst_setOpcode(Inst, ARM_SRSIB); + break; + case ARM_STMIB_UPD: + MCInst_setOpcode(Inst, ARM_SRSIB_UPD); + break; + default: + return MCDisassembler_Fail; + } + + // For stores (which become SRS's, the only operand is the mode. + if (fieldFromInstruction_4(Insn, 20, 1) == 0) { + // Check SRS encoding constraints + if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 && + fieldFromInstruction_4(Insn, 20, 1) == 0)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4)); + return S; + } + + return DecodeRFEInstruction(Inst, Insn, Address, Decoder); + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; // Tied + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned imm8 = fieldFromInstruction_4(Insn, 0, 8); + /* Ignored bit flags */ + + DecodeStatus S = MCDisassembler_Success; + + MCOperand_CreateImm0(Inst, imm8); + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, + // so all predicates should be allowed. + if (imm8 == 0x10 && pred != 0xe && ((true) != 0)) + S = MCDisassembler_SoftFail; + + return S; +} + +static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned imod = fieldFromInstruction_4(Insn, 18, 2); + unsigned M = fieldFromInstruction_4(Insn, 17, 1); + unsigned iflags = fieldFromInstruction_4(Insn, 6, 3); + unsigned mode = fieldFromInstruction_4(Insn, 0, 5); + + DecodeStatus S = MCDisassembler_Success; + + // This decoder is called from multiple location that do not check + // the full encoding is valid before they do. + if (fieldFromInstruction_4(Insn, 5, 1) != 0 || + fieldFromInstruction_4(Insn, 16, 1) != 0 || + fieldFromInstruction_4(Insn, 20, 8) != 0x10) + return MCDisassembler_Fail; + + // imod == '01' --> UNPREDICTABLE + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) + return MCDisassembler_Fail; + + if (imod && M) { + MCInst_setOpcode(Inst, ARM_CPS3p); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + MCOperand_CreateImm0(Inst, mode); + } else if (imod && !M) { + MCInst_setOpcode(Inst, ARM_CPS2p); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + if (mode) + S = MCDisassembler_SoftFail; + } else if (!imod && M) { + MCInst_setOpcode(Inst, ARM_CPS1p); + MCOperand_CreateImm0(Inst, mode); + if (iflags) + S = MCDisassembler_SoftFail; + } else { + // imod == '00' && M == '0' --> UNPREDICTABLE + MCInst_setOpcode(Inst, ARM_CPS1p); + MCOperand_CreateImm0(Inst, mode); + S = MCDisassembler_SoftFail; + } + + return S; +} + +static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned imod = fieldFromInstruction_4(Insn, 9, 2); + unsigned M = fieldFromInstruction_4(Insn, 8, 1); + unsigned iflags = fieldFromInstruction_4(Insn, 5, 3); + unsigned mode = fieldFromInstruction_4(Insn, 0, 5); + + DecodeStatus S = MCDisassembler_Success; + + // imod == '01' --> UNPREDICTABLE + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) + return MCDisassembler_Fail; + + if (imod && M) { + MCInst_setOpcode(Inst, ARM_t2CPS3p); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + MCOperand_CreateImm0(Inst, mode); + } else if (imod && !M) { + MCInst_setOpcode(Inst, ARM_t2CPS2p); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + if (mode) + S = MCDisassembler_SoftFail; + } else if (!imod && M) { + MCInst_setOpcode(Inst, ARM_t2CPS1p); + MCOperand_CreateImm0(Inst, mode); + if (iflags) + S = MCDisassembler_SoftFail; + } else { + // imod == '00' && M == '0' --> this is a HINT instruction + int imm = fieldFromInstruction_4(Insn, 0, 8); + // HINT are defined only for immediate in [0..4] + if (imm > 4) + return MCDisassembler_Fail; + MCInst_setOpcode(Inst, ARM_t2HINT); + MCOperand_CreateImm0(Inst, imm); + } + + return S; +} + +static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); + unsigned imm = 0; + + imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0); + imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8); + imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); + imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11); + + if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16) + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + // if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned imm = 0; + + imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0); + imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); + + if (MCInst_getOpcode(Inst) == ARM_MOVTi16) + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + // if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, imm); + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); + unsigned Ra = fieldFromInstruction_4(Insn, 12, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (pred == 0xF) + return DecodeCPSInstruction(Inst, Insn, Address, Decoder); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + if (Pred == 0xF) + return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Imm = fieldFromInstruction_4(Insn, 9, 1); + + /* Ignored bit flags */ + + // Decoder can be called from DecodeTST, which does not check the full + // encoding is valid. + if (fieldFromInstruction_4(Insn, 20, 12) != 0xf11 || + fieldFromInstruction_4(Insn, 4, 4) != 0) + return MCDisassembler_Fail; + if (fieldFromInstruction_4(Insn, 10, 10) != 0 || + fieldFromInstruction_4(Insn, 0, 4) != 0) + S = MCDisassembler_SoftFail; + + MCInst_setOpcode(Inst, ARM_SETPAN); + MCOperand_CreateImm0(Inst, Imm); + + return S; +} + +static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned add = fieldFromInstruction_4(Val, 12, 1); + unsigned imm = fieldFromInstruction_4(Val, 0, 12); + unsigned Rn = fieldFromInstruction_4(Val, 13, 4); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!add) + imm *= -1; + if (imm == 0 && !add) + imm = INT32_MIN; + MCOperand_CreateImm0(Inst, imm); + // if (Rn == 15) + // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); + + return S; +} + +static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + // U == 1 to add imm, 0 to subtract it. + unsigned U = fieldFromInstruction_4(Val, 8, 1); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (U) + MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, imm)); + else + MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, imm)); + + return S; +} + +static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + // U == 1 to add imm, 0 to subtract it. + unsigned U = fieldFromInstruction_4(Val, 8, 1); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (U) + MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_add, imm)); + else + MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_sub, imm)); + + return S; +} + +static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); +} + +static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus Status = MCDisassembler_Success; + + // Note the J1 and J2 values are from the encoded instruction. So here + // change them to I1 and I2 values via as documented: + // I1 = NOT(J1 EOR S); + // I2 = NOT(J2 EOR S); + // and build the imm32 with one trailing zero as documented: + // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); + unsigned S = fieldFromInstruction_4(Insn, 26, 1); + unsigned J1 = fieldFromInstruction_4(Insn, 13, 1); + unsigned J2 = fieldFromInstruction_4(Insn, 11, 1); + unsigned I1 = !(J1 ^ S); + unsigned I2 = !(J2 ^ S); + unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); + unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); + unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; + int imm32 = SignExtend32(tmp << 1, 25); + // if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, + // true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, imm32); + + return Status; +} + +static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2; + + if (pred == 0xF) { + MCInst_setOpcode(Inst, ARM_BLXi); + imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; + // if (!tryAddingSymbolicOperand(Address, Address + SignExtend32(imm, 26) + // + 8, + // true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); + return S; + } + + // if (!tryAddingSymbolicOperand(Address, Address + SignExtend32(imm, 26) + + // 8, + // true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned align = fieldFromInstruction_4(Val, 4, 2); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!align) + MCOperand_CreateImm0(Inst, 0); + else + MCOperand_CreateImm0(Inst, 4 << align); + + return S; +} + +static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned wb = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + // First output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD1q16: + case ARM_VLD1q32: + case ARM_VLD1q64: + case ARM_VLD1q8: + case ARM_VLD1q16wb_fixed: + case ARM_VLD1q16wb_register: + case ARM_VLD1q32wb_fixed: + case ARM_VLD1q32wb_register: + case ARM_VLD1q64wb_fixed: + case ARM_VLD1q64wb_register: + case ARM_VLD1q8wb_fixed: + case ARM_VLD1q8wb_register: + case ARM_VLD2d16: + case ARM_VLD2d32: + case ARM_VLD2d8: + case ARM_VLD2d16wb_fixed: + case ARM_VLD2d16wb_register: + case ARM_VLD2d32wb_fixed: + case ARM_VLD2d32wb_register: + case ARM_VLD2d8wb_fixed: + case ARM_VLD2d8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD2b16: + case ARM_VLD2b32: + case ARM_VLD2b8: + case ARM_VLD2b16wb_fixed: + case ARM_VLD2b16wb_register: + case ARM_VLD2b32wb_fixed: + case ARM_VLD2b32wb_register: + case ARM_VLD2b8wb_fixed: + case ARM_VLD2b8wb_register: + if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } + + // Second output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD3d8: + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8_UPD: + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD4d8: + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD3q8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD4q8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Third output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD3d8: + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8_UPD: + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD4d8: + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD3q8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD4q8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Fourth output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD4d8: + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD4q8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Writeback operand + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD1d8wb_fixed: + case ARM_VLD1d16wb_fixed: + case ARM_VLD1d32wb_fixed: + case ARM_VLD1d64wb_fixed: + case ARM_VLD1d8wb_register: + case ARM_VLD1d16wb_register: + case ARM_VLD1d32wb_register: + case ARM_VLD1d64wb_register: + case ARM_VLD1q8wb_fixed: + case ARM_VLD1q16wb_fixed: + case ARM_VLD1q32wb_fixed: + case ARM_VLD1q64wb_fixed: + case ARM_VLD1q8wb_register: + case ARM_VLD1q16wb_register: + case ARM_VLD1q32wb_register: + case ARM_VLD1q64wb_register: + case ARM_VLD1d8Twb_fixed: + case ARM_VLD1d8Twb_register: + case ARM_VLD1d16Twb_fixed: + case ARM_VLD1d16Twb_register: + case ARM_VLD1d32Twb_fixed: + case ARM_VLD1d32Twb_register: + case ARM_VLD1d64Twb_fixed: + case ARM_VLD1d64Twb_register: + case ARM_VLD1d8Qwb_fixed: + case ARM_VLD1d8Qwb_register: + case ARM_VLD1d16Qwb_fixed: + case ARM_VLD1d16Qwb_register: + case ARM_VLD1d32Qwb_fixed: + case ARM_VLD1d32Qwb_register: + case ARM_VLD1d64Qwb_fixed: + case ARM_VLD1d64Qwb_register: + case ARM_VLD2d8wb_fixed: + case ARM_VLD2d16wb_fixed: + case ARM_VLD2d32wb_fixed: + case ARM_VLD2q8wb_fixed: + case ARM_VLD2q16wb_fixed: + case ARM_VLD2q32wb_fixed: + case ARM_VLD2d8wb_register: + case ARM_VLD2d16wb_register: + case ARM_VLD2d32wb_register: + case ARM_VLD2q8wb_register: + case ARM_VLD2q16wb_register: + case ARM_VLD2q32wb_register: + case ARM_VLD2b8wb_fixed: + case ARM_VLD2b16wb_fixed: + case ARM_VLD2b32wb_fixed: + case ARM_VLD2b8wb_register: + case ARM_VLD2b16wb_register: + case ARM_VLD2b32wb_register: + MCOperand_CreateImm0(Inst, 0); + break; + case ARM_VLD3d8_UPD: + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD3q8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // AddrMode6 Base (register+alignment) + if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + // AddrMode6 Offset (register) + switch (MCInst_getOpcode(Inst)) { + default: + // The below have been updated to have explicit am6offset split + // between fixed and register offset. For those instructions not + // yet updated, we need to add an additional reg0 operand for the + // fixed variant. + // + // The fixed offset encodes as Rm == 0xd, so we check for that. + if (Rm == 0xd) { + MCOperand_CreateReg0(Inst, 0); + break; + } + // Fall through to handle the register offset variant. + 0x0; + case ARM_VLD1d8wb_fixed: + case ARM_VLD1d16wb_fixed: + case ARM_VLD1d32wb_fixed: + case ARM_VLD1d64wb_fixed: + case ARM_VLD1d8Twb_fixed: + case ARM_VLD1d16Twb_fixed: + case ARM_VLD1d32Twb_fixed: + case ARM_VLD1d64Twb_fixed: + case ARM_VLD1d8Qwb_fixed: + case ARM_VLD1d16Qwb_fixed: + case ARM_VLD1d32Qwb_fixed: + case ARM_VLD1d64Qwb_fixed: + case ARM_VLD1d8wb_register: + case ARM_VLD1d16wb_register: + case ARM_VLD1d32wb_register: + case ARM_VLD1d64wb_register: + case ARM_VLD1q8wb_fixed: + case ARM_VLD1q16wb_fixed: + case ARM_VLD1q32wb_fixed: + case ARM_VLD1q64wb_fixed: + case ARM_VLD1q8wb_register: + case ARM_VLD1q16wb_register: + case ARM_VLD1q32wb_register: + case ARM_VLD1q64wb_register: + // The fixed offset post-increment encodes Rm == 0xd. The no-writeback + // variant encodes Rm == 0xf. Anything else is a register offset post- + // increment and we need to add the register operand to the instruction. + if (Rm != 0xD && Rm != 0xF && + !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD2d8wb_fixed: + case ARM_VLD2d16wb_fixed: + case ARM_VLD2d32wb_fixed: + case ARM_VLD2b8wb_fixed: + case ARM_VLD2b16wb_fixed: + case ARM_VLD2b32wb_fixed: + case ARM_VLD2q8wb_fixed: + case ARM_VLD2q16wb_fixed: + case ARM_VLD2q32wb_fixed: + break; + } + + return S; +} + +static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned type = fieldFromInstruction_4(Insn, 8, 4); + unsigned align = fieldFromInstruction_4(Insn, 4, 2); + if (type == 6 && (align & 2)) + return MCDisassembler_Fail; + if (type == 7 && (align & 2)) + return MCDisassembler_Fail; + if (type == 10 && align == 3) + return MCDisassembler_Fail; + + unsigned load = fieldFromInstruction_4(Insn, 21, 1); + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) + : DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + if (size == 3) + return MCDisassembler_Fail; + + unsigned type = fieldFromInstruction_4(Insn, 8, 4); + unsigned align = fieldFromInstruction_4(Insn, 4, 2); + if (type == 8 && align == 3) + return MCDisassembler_Fail; + if (type == 9 && align == 3) + return MCDisassembler_Fail; + + unsigned load = fieldFromInstruction_4(Insn, 21, 1); + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) + : DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + if (size == 3) + return MCDisassembler_Fail; + + unsigned align = fieldFromInstruction_4(Insn, 4, 2); + if (align & 2) + return MCDisassembler_Fail; + + unsigned load = fieldFromInstruction_4(Insn, 21, 1); + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) + : DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + if (size == 3) + return MCDisassembler_Fail; + + unsigned load = fieldFromInstruction_4(Insn, 21, 1); + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) + : DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned wb = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + // Writeback Operand + switch (MCInst_getOpcode(Inst)) { + case ARM_VST1d8wb_fixed: + case ARM_VST1d16wb_fixed: + case ARM_VST1d32wb_fixed: + case ARM_VST1d64wb_fixed: + case ARM_VST1d8wb_register: + case ARM_VST1d16wb_register: + case ARM_VST1d32wb_register: + case ARM_VST1d64wb_register: + case ARM_VST1q8wb_fixed: + case ARM_VST1q16wb_fixed: + case ARM_VST1q32wb_fixed: + case ARM_VST1q64wb_fixed: + case ARM_VST1q8wb_register: + case ARM_VST1q16wb_register: + case ARM_VST1q32wb_register: + case ARM_VST1q64wb_register: + case ARM_VST1d8Twb_fixed: + case ARM_VST1d16Twb_fixed: + case ARM_VST1d32Twb_fixed: + case ARM_VST1d64Twb_fixed: + case ARM_VST1d8Twb_register: + case ARM_VST1d16Twb_register: + case ARM_VST1d32Twb_register: + case ARM_VST1d64Twb_register: + case ARM_VST1d8Qwb_fixed: + case ARM_VST1d16Qwb_fixed: + case ARM_VST1d32Qwb_fixed: + case ARM_VST1d64Qwb_fixed: + case ARM_VST1d8Qwb_register: + case ARM_VST1d16Qwb_register: + case ARM_VST1d32Qwb_register: + case ARM_VST1d64Qwb_register: + case ARM_VST2d8wb_fixed: + case ARM_VST2d16wb_fixed: + case ARM_VST2d32wb_fixed: + case ARM_VST2d8wb_register: + case ARM_VST2d16wb_register: + case ARM_VST2d32wb_register: + case ARM_VST2q8wb_fixed: + case ARM_VST2q16wb_fixed: + case ARM_VST2q32wb_fixed: + case ARM_VST2q8wb_register: + case ARM_VST2q16wb_register: + case ARM_VST2q32wb_register: + case ARM_VST2b8wb_fixed: + case ARM_VST2b16wb_fixed: + case ARM_VST2b32wb_fixed: + case ARM_VST2b8wb_register: + case ARM_VST2b16wb_register: + case ARM_VST2b32wb_register: + if (Rm == 0xF) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, 0); + break; + case ARM_VST3d8_UPD: + case ARM_VST3d16_UPD: + case ARM_VST3d32_UPD: + case ARM_VST3q8_UPD: + case ARM_VST3q16_UPD: + case ARM_VST3q32_UPD: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // AddrMode6 Base (register+alignment) + if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + // AddrMode6 Offset (register) + switch (MCInst_getOpcode(Inst)) { + default: + if (Rm == 0xD) + MCOperand_CreateReg0(Inst, 0); + else if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + break; + case ARM_VST1d8wb_fixed: + case ARM_VST1d16wb_fixed: + case ARM_VST1d32wb_fixed: + case ARM_VST1d64wb_fixed: + case ARM_VST1q8wb_fixed: + case ARM_VST1q16wb_fixed: + case ARM_VST1q32wb_fixed: + case ARM_VST1q64wb_fixed: + case ARM_VST1d8Twb_fixed: + case ARM_VST1d16Twb_fixed: + case ARM_VST1d32Twb_fixed: + case ARM_VST1d64Twb_fixed: + case ARM_VST1d8Qwb_fixed: + case ARM_VST1d16Qwb_fixed: + case ARM_VST1d32Qwb_fixed: + case ARM_VST1d64Qwb_fixed: + case ARM_VST2d8wb_fixed: + case ARM_VST2d16wb_fixed: + case ARM_VST2d32wb_fixed: + case ARM_VST2q8wb_fixed: + case ARM_VST2q16wb_fixed: + case ARM_VST2q32wb_fixed: + case ARM_VST2b8wb_fixed: + case ARM_VST2b16wb_fixed: + case ARM_VST2b32wb_fixed: + break; + } + + // First input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST1q16: + case ARM_VST1q32: + case ARM_VST1q64: + case ARM_VST1q8: + case ARM_VST1q16wb_fixed: + case ARM_VST1q16wb_register: + case ARM_VST1q32wb_fixed: + case ARM_VST1q32wb_register: + case ARM_VST1q64wb_fixed: + case ARM_VST1q64wb_register: + case ARM_VST1q8wb_fixed: + case ARM_VST1q8wb_register: + case ARM_VST2d16: + case ARM_VST2d32: + case ARM_VST2d8: + case ARM_VST2d16wb_fixed: + case ARM_VST2d16wb_register: + case ARM_VST2d32wb_fixed: + case ARM_VST2d32wb_register: + case ARM_VST2d8wb_fixed: + case ARM_VST2d8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VST2b16: + case ARM_VST2b32: + case ARM_VST2b8: + case ARM_VST2b16wb_fixed: + case ARM_VST2b16wb_register: + case ARM_VST2b32wb_fixed: + case ARM_VST2b32wb_register: + case ARM_VST2b8wb_fixed: + case ARM_VST2b8wb_register: + if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } + + // Second input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST3d8: + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8_UPD: + case ARM_VST3d16_UPD: + case ARM_VST3d32_UPD: + case ARM_VST4d8: + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VST3q8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8_UPD: + case ARM_VST3q16_UPD: + case ARM_VST3q32_UPD: + case ARM_VST4q8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Third input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST3d8: + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8_UPD: + case ARM_VST3d16_UPD: + case ARM_VST3d32_UPD: + case ARM_VST4d8: + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VST3q8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8_UPD: + case ARM_VST3q16_UPD: + case ARM_VST3q32_UPD: + case ARM_VST4q8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Fourth input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST4d8: + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VST4q8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + return S; +} + +static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned align = fieldFromInstruction_4(Insn, 4, 1); + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + + if (size == 0 && align == 1) + return MCDisassembler_Fail; + align *= (1 << size); + + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD1DUPq16: + case ARM_VLD1DUPq32: + case ARM_VLD1DUPq8: + case ARM_VLD1DUPq16wb_fixed: + case ARM_VLD1DUPq16wb_register: + case ARM_VLD1DUPq32wb_fixed: + case ARM_VLD1DUPq32wb_register: + case ARM_VLD1DUPq8wb_fixed: + case ARM_VLD1DUPq8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + } + if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + + // The fixed offset post-increment encodes Rm == 0xd. The no-writeback + // variant encodes Rm == 0xf. Anything else is a register offset post- + // increment and we need to add the register operand to the instruction. + if (Rm != 0xD && Rm != 0xF && + !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned align = fieldFromInstruction_4(Insn, 4, 1); + unsigned size = 1 << fieldFromInstruction_4(Insn, 6, 2); + align *= 2 * size; + + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD2DUPd16: + case ARM_VLD2DUPd32: + case ARM_VLD2DUPd8: + case ARM_VLD2DUPd16wb_fixed: + case ARM_VLD2DUPd16wb_register: + case ARM_VLD2DUPd32wb_fixed: + case ARM_VLD2DUPd32wb_register: + case ARM_VLD2DUPd8wb_fixed: + case ARM_VLD2DUPd8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD2DUPd16x2: + case ARM_VLD2DUPd32x2: + case ARM_VLD2DUPd8x2: + case ARM_VLD2DUPd16x2wb_fixed: + case ARM_VLD2DUPd16x2wb_register: + case ARM_VLD2DUPd32x2wb_fixed: + case ARM_VLD2DUPd32x2wb_register: + case ARM_VLD2DUPd8x2wb_fixed: + case ARM_VLD2DUPd8x2wb_register: + if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + } + + if (Rm != 0xF) + MCOperand_CreateImm0(Inst, 0); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xD && Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction(Insn, 12, 4); + Rd |= fieldFromInstruction(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction(Insn, 16, 4); + unsigned Rm = fieldFromInstruction(Insn, 0, 4); + unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, Address, + Decoder))) + return MCDisassembler_Fail; + if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, 0); + + if (Rm == 0xD) + MCOperand_CreateImm0(Inst, 0); + else if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + unsigned inc = fieldFromInstruction_4(Insn, 5, 1) + 1; + unsigned align = fieldFromInstruction_4(Insn, 4, 1); + + if (size == 0x3) { + if (align == 0) + return MCDisassembler_Fail; + align = 16; + } else { + if (size == 2) { + align *= 8; + } else { + size = 1 << size; + align *= 4 * size; + } + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, Address, + Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3 * inc) % 32, Address, + Decoder))) + return MCDisassembler_Fail; + if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + + if (Rm == 0xD) + MCOperand_CreateReg0(Inst, 0); + else if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeVMOVModImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned imm = fieldFromInstruction_4(Insn, 0, 4); + imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; + imm |= fieldFromInstruction_4(Insn, 24, 1) << 7; + imm |= fieldFromInstruction_4(Insn, 8, 4) << 8; + imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; + unsigned Q = fieldFromInstruction_4(Insn, 6, 1); + + if (Q) { + if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } else { + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } + + MCOperand_CreateImm0(Inst, imm); + + switch (MCInst_getOpcode(Inst)) { + case ARM_VORRiv4i16: + case ARM_VORRiv2i32: + case ARM_VBICiv4i16: + case ARM_VBICiv2i32: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VORRiv8i16: + case ARM_VORRiv4i32: + case ARM_VBICiv8i16: + case ARM_VBICiv4i32: + if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + return S; +} + +static DecodeStatus DecodeMVEModImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) | + fieldFromInstruction_4(Insn, 13, 3)); + unsigned cmode = fieldFromInstruction_4(Insn, 8, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 4); + imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; + imm |= fieldFromInstruction_4(Insn, 28, 1) << 7; + imm |= cmode << 8; + imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; + + if (cmode == 0xF && MCInst_getOpcode(Inst) == ARM_MVE_VMVNimmi32) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, imm); + + MCOperand_CreateImm0(Inst, /*ARMVCC_None*/ 0); + MCOperand_CreateReg0(Inst, 0); + MCOperand_CreateImm0(Inst, 0); + + return S; +} + +static DecodeStatus DecodeMVEVADCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Qd = fieldFromInstruction_4(Insn, 13, 3); + Qd |= fieldFromInstruction_4(Insn, 22, 1) << 3; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, ARM_FPSCR_NZCV); + + unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); + Qn |= fieldFromInstruction_4(Insn, 7, 1) << 3; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) + return MCDisassembler_Fail; + unsigned Qm = fieldFromInstruction_4(Insn, 1, 3); + Qm |= fieldFromInstruction_4(Insn, 5, 1) << 3; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler_Fail; + if (!fieldFromInstruction_4(Insn, 12, 1)) // I bit clear => need input FPSCR + MCOperand_CreateReg0(Inst, ARM_FPSCR_NZCV); + MCOperand_CreateImm0(Inst, Qd); + + return S; +} + +static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 18, 2); + + if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, 8 << size); + + return S; +} + +static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, 8 - Val); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, 16 - Val); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, 32 - Val); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, 64 - Val); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; + unsigned op = fieldFromInstruction_4(Insn, 6, 1); + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (op) { + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; // Writeback + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_VTBL2: + case ARM_VTBX2: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned dst = fieldFromInstruction_4(Insn, 8, 3); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + default: + return MCDisassembler_Fail; + case ARM_tADR: + break; // tADR does not explicitly represent the PC as an operand. + case ARM_tADDrSPi: + MCOperand_CreateReg0(Inst, ARM_SP); + break; + } + + MCOperand_CreateImm0(Inst, imm); + return S; +} + +static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + // if (!tryAddingSymbolicOperand(Address, Address + SignExtend32(Val<<1, 12) + // + 4, + // true, 2, Inst, Decoder)) + MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + // if (!tryAddingSymbolicOperand(Address, Address + SignExtend32(Val, 21) + + // 4, + // true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, SignExtend32(Val, 21)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + // if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, + // true, 2, Inst, Decoder)) + MCOperand_CreateImm0(Inst, Val << 1); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 0, 3); + unsigned Rm = fieldFromInstruction_4(Val, 3, 3); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 0, 3); + unsigned imm = fieldFromInstruction_4(Val, 3, 5); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + unsigned imm = Val << 2; + + MCOperand_CreateImm0(Inst, imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateImm0(Inst, Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 6, 4); + unsigned Rm = fieldFromInstruction_4(Val, 2, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 2); + + // Thumb stores cannot use PC as dest register. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2STRHs: + case ARM_t2STRBs: + case ARM_t2STRs: + if (Rn == 15) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + + /* Ignored bit flags */ + + bool hasMP = true; + bool hasV7Ops = true; + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRBs: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRHs: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSHs: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + case ARM_t2LDRSBs: + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2LDRs: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2PLDs: + MCInst_setOpcode(Inst, ARM_t2PLDpci); + break; + case ARM_t2PLIs: + MCInst_setOpcode(Inst, ARM_t2PLIpci); + break; + default: + return MCDisassembler_Fail; + } + + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRSHs: + return MCDisassembler_Fail; + case ARM_t2LDRHs: + MCInst_setOpcode(Inst, ARM_t2PLDWs); + break; + case ARM_t2LDRSBs: + MCInst_setOpcode(Inst, ARM_t2PLIs); + break; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDs: + break; + case ARM_t2PLIs: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + case ARM_t2PLDWs: + if (!hasV7Ops || !hasMP) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + unsigned addrmode = fieldFromInstruction_4(Insn, 4, 2); + addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2; + addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6; + if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned U = fieldFromInstruction_4(Insn, 9, 1); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + imm |= (U << 8); + imm |= (Rn << 9); + unsigned add = fieldFromInstruction_4(Insn, 9, 1); + + /* Ignored bit flags */ + + bool hasMP = true; + bool hasV7Ops = true; + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRi8: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2LDRBi8: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRSBi8: + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2LDRHi8: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSHi8: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + case ARM_t2PLDi8: + MCInst_setOpcode(Inst, ARM_t2PLDpci); + break; + case ARM_t2PLIi8: + MCInst_setOpcode(Inst, ARM_t2PLIpci); + break; + default: + return MCDisassembler_Fail; + } + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRSHi8: + return MCDisassembler_Fail; + case ARM_t2LDRHi8: + if (!add) + MCInst_setOpcode(Inst, ARM_t2PLDWi8); + break; + case ARM_t2LDRSBi8: + MCInst_setOpcode(Inst, ARM_t2PLIi8); + break; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDi8: + break; + case ARM_t2PLIi8: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + case ARM_t2PLDWi8: + if (!hasV7Ops || !hasMP) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= (Rn << 13); + + /* Ignored bit flags */ + + bool hasMP = true; + bool hasV7Ops = true; + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRi12: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2LDRHi12: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSHi12: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + case ARM_t2LDRBi12: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRSBi12: + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2PLDi12: + MCInst_setOpcode(Inst, ARM_t2PLDpci); + break; + case ARM_t2PLIi12: + MCInst_setOpcode(Inst, ARM_t2PLIpci); + break; + default: + return MCDisassembler_Fail; + } + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRSHi12: + return MCDisassembler_Fail; + case ARM_t2LDRHi12: + MCInst_setOpcode(Inst, ARM_t2PLDWi12); + break; + case ARM_t2LDRSBi12: + MCInst_setOpcode(Inst, ARM_t2PLIi12); + break; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDi12: + break; + case ARM_t2PLIi12: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + case ARM_t2PLDWi12: + if (!hasV7Ops || !hasMP) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + imm |= (Rn << 9); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRT: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2LDRBT: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRHT: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSBT: + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2LDRSHT: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + default: + return MCDisassembler_Fail; + } + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + int imm = fieldFromInstruction_4(Insn, 0, 12); + + /* Ignored bit flags */ + + bool hasV7Ops = true; + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRBpci: + case ARM_t2LDRHpci: + MCInst_setOpcode(Inst, ARM_t2PLDpci); + break; + case ARM_t2LDRSBpci: + MCInst_setOpcode(Inst, ARM_t2PLIpci); + break; + case ARM_t2LDRSHpci: + return MCDisassembler_Fail; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDpci: + break; + case ARM_t2PLIpci: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!U) { + // Special case for #-0. + if (imm == 0) + imm = INT32_MIN; + else + imm = -imm; + } + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder) { + if (Val == 0) + MCOperand_CreateImm0(Inst, INT32_MIN); + else { + int imm = Val & 0xFF; + + if (!(Val & 0x100)) + imm *= -1; + MCOperand_CreateImm0(Inst, imm * 4); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2Imm7S4(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder) { + if (Val == 0) + MCOperand_CreateImm0(Inst, INT32_MIN); + else { + int imm = Val & 0x7F; + + if (!(Val & 0x80)) + imm *= -1; + MCOperand_CreateImm0(Inst, imm * 4); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 9); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm7s4(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 8, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 8, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder) { + int imm = Val & 0xFF; + if (Val == 0) + imm = INT32_MIN; + else if (!(Val & 0x100)) + imm *= -1; + MCOperand_CreateImm0(Inst, imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2Imm7(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder, unsigned shift) { + int imm = Val & 0x7F; + if (Val == 0) + imm = INT32_MIN; + else if (!(Val & 0x80)) + imm *= -1; + if (imm != INT32_MIN) + imm *= (1U << shift); + MCOperand_CreateImm0(Inst, imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 9); + + // Thumb stores cannot use PC as dest register. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2STRT: + case ARM_t2STRBT: + case ARM_t2STRHT: + case ARM_t2STRi8: + case ARM_t2STRHi8: + case ARM_t2STRBi8: + if (Rn == 15) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Some instructions always use an additive offset. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRT: + case ARM_t2LDRBT: + case ARM_t2LDRHT: + case ARM_t2LDRSBT: + case ARM_t2LDRSHT: + case ARM_t2STRT: + case ARM_t2STRBT: + case ARM_t2STRHT: + imm |= 0x100; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeTAddrModeImm7(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + unsigned shift) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 8, 3); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2Imm7(Inst, imm, Address, Decoder, shift))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm7(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + int shift, int WriteBack) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 8, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + if (WriteBack) { + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } else if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2Imm7(Inst, imm, Address, Decoder, shift))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned addr = fieldFromInstruction_4(Insn, 0, 8); + addr |= fieldFromInstruction_4(Insn, 9, 1) << 8; + addr |= Rn << 9; + unsigned load = fieldFromInstruction_4(Insn, 20, 1); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDR_PRE: + case ARM_t2LDR_POST: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2LDRB_PRE: + case ARM_t2LDRB_POST: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRH_PRE: + case ARM_t2LDRH_POST: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSB_PRE: + case ARM_t2LDRSB_POST: + if (Rt == 15) + MCInst_setOpcode(Inst, ARM_t2PLIpci); + else + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2LDRSH_PRE: + case ARM_t2LDRSH_POST: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + default: + return MCDisassembler_Fail; + } + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (!load) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (load) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 13, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 12); + + // Thumb stores cannot use PC as dest register. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2STRi12: + case ARM_t2STRBi12: + case ARM_t2STRHi12: + if (Rn == 15) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, + uint64_t Address, void *Decoder) { + unsigned imm = fieldFromInstruction_4(Insn, 0, 7); + + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateImm0(Inst, imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + if (MCInst_getOpcode(Inst) == ARM_tADDrSP) { + unsigned Rdm = fieldFromInstruction_4(Insn, 0, 3); + Rdm |= fieldFromInstruction_4(Insn, 7, 1) << 3; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, ARM_SP); + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler_Fail; + } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { + unsigned Rm = fieldFromInstruction_4(Insn, 3, 4); + + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateReg0(Inst, ARM_SP); + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, + uint64_t Address, void *Decoder) { + unsigned imod = fieldFromInstruction_4(Insn, 4, 1) | 0x2; + unsigned flags = fieldFromInstruction_4(Insn, 0, 3); + + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, flags); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned add = fieldFromInstruction_4(Insn, 4, 1); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, add); + + return S; +} + +static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Insn, 3, 4); + unsigned Qm = fieldFromInstruction_4(Insn, 0, 3); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeMveAddrModeQ(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder, + int shift) { + DecodeStatus S = MCDisassembler_Success; + unsigned Qm = fieldFromInstruction_4(Insn, 8, 3); + int imm = fieldFromInstruction_4(Insn, 0, 7); + + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!fieldFromInstruction_4(Insn, 7, 1)) { + if (imm == 0) + imm = INT32_MIN; // indicate -0 + else + imm *= -1; + } + if (imm != INT32_MIN) + imm *= (1U << shift); + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + // Val is passed in as S:J1:J2:imm10H:imm10L:'0' + // Note only one trailing zero not two. Also the J1 and J2 values are from + // the encoded instruction. So here change to I1 and I2 values via: + // I1 = NOT(J1 EOR S); + // I2 = NOT(J2 EOR S); + // and build the imm32 with two trailing zeros as documented: + // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); + unsigned S = (Val >> 23) & 1; + unsigned J1 = (Val >> 22) & 1; + unsigned J2 = (Val >> 21) & 1; + unsigned I1 = !(J1 ^ S); + unsigned I2 = !(J2 ^ S); + unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); + int imm32 = SignExtend32(tmp << 1, 25); + + // if (!tryAddingSymbolicOperand(Address, + // (Address & ~2u) + imm32 + 4, + // true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, imm32); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + if (Val == 0xA || Val == 0xB) + return MCDisassembler_Fail; + + /* Ignored bit flags */ + + if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && + !(Val == 14 || Val == 15)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + /* Ignored bit flags */ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + if (Rn == 13) + S = MCDisassembler_SoftFail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned pred = fieldFromInstruction_4(Insn, 22, 4); + if (pred == 0xE || pred == 0xF) { + unsigned opc = fieldFromInstruction_4(Insn, 4, 28); + switch (opc) { + default: + return MCDisassembler_Fail; + case 0xf3bf8f4: + MCInst_setOpcode(Inst, ARM_t2DSB); + break; + case 0xf3bf8f5: + MCInst_setOpcode(Inst, ARM_t2DMB); + break; + case 0xf3bf8f6: + MCInst_setOpcode(Inst, ARM_t2ISB); + break; + } + + unsigned imm = fieldFromInstruction_4(Insn, 0, 4); + return DecodeMemBarrierOption(Inst, imm, Address, Decoder); + } + + unsigned brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1; + brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19; + brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18; + brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12; + brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20; + + if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder) { + unsigned ctrl = fieldFromInstruction_4(Val, 10, 2); + if (ctrl == 0) { + unsigned byte = fieldFromInstruction_4(Val, 8, 2); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + switch (byte) { + case 0: + MCOperand_CreateImm0(Inst, imm); + break; + case 1: + MCOperand_CreateImm0(Inst, (imm << 16) | imm); + break; + case 2: + MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8)); + break; + case 3: + MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm); + break; + } + } else { + unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; + unsigned rot = fieldFromInstruction_4(Val, 7, 5); + unsigned imm = (unrot >> rot) | (unrot << ((32 - rot) & 31)); + MCOperand_CreateImm0(Inst, imm); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder) { + // if (!tryAddingSymbolicOperand(Address, Address + SignExtend32(Val<<1, 9) + + // 4, + // true, 2, Inst, Decoder)) + MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder) { + // Val is passed in as S:J1:J2:imm10:imm11 + // Note no trailing zero after imm11. Also the J1 and J2 values are from + // the encoded instruction. So here change to I1 and I2 values via: + // I1 = NOT(J1 EOR S); + // I2 = NOT(J2 EOR S); + // and build the imm32 with one trailing zero as documented: + // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); + unsigned S = (Val >> 23) & 1; + unsigned J1 = (Val >> 22) & 1; + unsigned J2 = (Val >> 21) & 1; + unsigned I1 = !(J1 ^ S); + unsigned I2 = !(J2 ^ S); + unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); + int imm32 = SignExtend32(tmp << 1, 25); + + // if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, + // true, 4, Inst, Decoder)) + MCOperand_CreateImm0(Inst, imm32); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + if (Val & ~0xf) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder) { + if (Val & ~0xf) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + /* Ignored bit flags */ + + if (Inst->csh->mode & CS_MODE_MCLASS) { + unsigned ValLow = Val & 0xff; + + // Validate the SYSm value first. + switch (ValLow) { + case 0: // apsr + case 1: // iapsr + case 2: // eapsr + case 3: // xpsr + case 5: // ipsr + case 6: // epsr + case 7: // iepsr + case 8: // msp + case 9: // psp + case 16: // primask + case 20: // control + break; + case 17: // basepri + case 18: // basepri_max + case 19: // faultmask + if (!(true)) + // Values basepri, basepri_max and faultmask are only valid for v7m. + return MCDisassembler_Fail; + break; + case 0x8a: // msplim_ns + case 0x8b: // psplim_ns + case 0x91: // basepri_ns + case 0x93: // faultmask_ns + if (!(true)) + return MCDisassembler_Fail; + 0x0; + case 10: // msplim + case 11: // psplim + case 0x88: // msp_ns + case 0x89: // psp_ns + case 0x90: // primask_ns + case 0x94: // control_ns + case 0x98: // sp_ns + if (!(true)) + return MCDisassembler_Fail; + break; + default: + // Architecturally defined as unpredictable + S = MCDisassembler_SoftFail; + break; + } + + if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) { + unsigned Mask = fieldFromInstruction_4(Val, 10, 2); + // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are + // unpredictable. + if (Mask != 2) + S = MCDisassembler_SoftFail; + else + // The ARMv7-M architecture stores an additional 2-bit mask value in + // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and + // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if + // the NZCVQ bits should be moved by the instruction. Bit mask{0} + // indicates the move for the GE{3:0} bits, the mask{0} bit can be set + // only if the processor includes the DSP extension. + if (Mask == 0 || (Mask != 2 && ValLow > 3) || (!(true) && (Mask & 1))) + S = MCDisassembler_SoftFail; + } + } else { + // A/R class + if (Val == 0) + return MCDisassembler_Fail; + } + MCOperand_CreateImm0(Inst, Val); + return S; +} + +static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + unsigned R = fieldFromInstruction_4(Val, 5, 1); + unsigned SysM = fieldFromInstruction_4(Val, 0, 5); + + // The table of encodings for these banked registers comes from B9.2.3 of the + // ARM ARM. There are patterns, but nothing regular enough to make this logic + // neater. So by fiat, these values are UNPREDICTABLE: + if (!lookupBankedRegByEncoding((R << 5) | SysM)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt + 1) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + if (Rn == 0xF || Rn == Rt) + S = MCDisassembler_SoftFail; + if (Rm == 0xF) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 6, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; + break; + case 3: + align = 4; + break; + default: + return MCDisassembler_Fail; + } + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 6, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; + break; + case 3: + align = 4; + break; + default: + return MCDisassembler_Fail; + } + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + index = fieldFromInstruction_4(Insn, 5, 3); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 1: + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 4, 1) != 0) + align = 8; + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + index = fieldFromInstruction_4(Insn, 5, 3); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 1: + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 4, 1) != 0) + align = 8; + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 4, 2)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 4, 2)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 8; + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; + break; + case 3: + return MCDisassembler_Fail; + default: + align = 4 << fieldFromInstruction_4(Insn, 4, 2); + break; + } + + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + unsigned size = fieldFromInstruction_4(Insn, 10, 2); + + unsigned align = 0; + unsigned index = 0; + unsigned inc = 1; + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 8; + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; + break; + case 3: + return MCDisassembler_Fail; + default: + align = 4 << fieldFromInstruction_4(Insn, 4, 2); + break; + } + + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, align); + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + unsigned pred = fieldFromInstruction_4(Insn, 4, 4); + unsigned mask = fieldFromInstruction_4(Insn, 0, 4); + + if (pred == 0xF) { + pred = 0xE; + S = MCDisassembler_SoftFail; + } + + if (mask == 0x0) + return MCDisassembler_Fail; + + // IT masks are encoded as a sequence of replacement low-order bits + // for the condition code. So if the low bit of the starting + // condition code is 1, then we have to flip all the bits above the + // terminating bit (which is the lowest 1 bit). + if (pred & 1) { + unsigned LowBit = mask & -mask; + unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); + mask ^= BitsAboveLowBit; + } + + MCOperand_CreateImm0(Inst, pred); + MCOperand_CreateImm0(Inst, mask); + return S; +} + +static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned addr = fieldFromInstruction_4(Insn, 0, 8); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + bool writeback = (W == 1) | (P == 0); + + addr |= (U << 8) | (Rn << 9); + + if (writeback && (Rn == Rt || Rn == Rt2)) + Check(&S, MCDisassembler_SoftFail); + if (Rt == Rt2) + Check(&S, MCDisassembler_SoftFail); + + // Rt + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + // Rt2 + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + // Writeback operand + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + // addr + if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned addr = fieldFromInstruction_4(Insn, 0, 8); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + bool writeback = (W == 1) | (P == 0); + + addr |= (U << 8) | (Rn << 9); + + if (writeback && (Rn == Rt || Rn == Rt2)) + Check(&S, MCDisassembler_SoftFail); + + // Writeback operand + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + // Rt + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + // Rt2 + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + // addr + if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, uint64_t Address, + void *Decoder) { + unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); + unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); + if (sign1 != sign2) + return MCDisassembler_Fail; + const unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); + // assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); + DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); + + unsigned Val = fieldFromInstruction_4(Insn, 0, 8); + Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; + Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; + // If sign, then it is decreasing the address. + if (sign1) { + // Following ARMv7 Architecture Manual, when the offset + // is zero, it is decoded as a subw, not as a adr.w + if (!Val) { + MCInst_setOpcode(Inst, ARM_t2SUBri12); + MCOperand_CreateReg0(Inst, ARM_PC); + } else + Val = -Val; + } + MCOperand_CreateImm0(Inst, Val); + return S; +} + +static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + // Shift of "asr #32" is not allowed in Thumb2 mode. + if (Val == 0x20) + S = MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, Val); + return S; +} + +static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (pred == 0xF) + return DecodeCPSInstruction(Inst, Insn, Address, Decoder); + + DecodeStatus S = MCDisassembler_Success; + + if (Rt == Rn || Rn == Rt2) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + /* Ignored bit flags */ + bool hasFullFP16 = true; + + unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); + Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); + unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); + Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); + unsigned imm = fieldFromInstruction_4(Insn, 16, 6); + unsigned cmode = fieldFromInstruction_4(Insn, 8, 4); + unsigned op = fieldFromInstruction_4(Insn, 5, 1); + + DecodeStatus S = MCDisassembler_Success; + + // If the top 3 bits of imm are clear, this is a VMOV (immediate) + if (!(imm & 0x38)) { + if (cmode == 0xF) { + if (op == 1) + return MCDisassembler_Fail; + MCInst_setOpcode(Inst, ARM_VMOVv2f32); + } + if (hasFullFP16) { + if (cmode == 0xE) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMOVv1i64); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv8i8); + } + } + if (cmode == 0xD) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMVNv2i32); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv2i32); + } + } + if (cmode == 0xC) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMVNv2i32); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv2i32); + } + } + } + return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); + } + + if (!(imm & 0x20)) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, 64 - imm); + + return S; +} + +static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + /* Ignored bit flags */ + bool hasFullFP16 = true; + + unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); + Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); + unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); + Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); + unsigned imm = fieldFromInstruction_4(Insn, 16, 6); + unsigned cmode = fieldFromInstruction_4(Insn, 8, 4); + unsigned op = fieldFromInstruction_4(Insn, 5, 1); + + DecodeStatus S = MCDisassembler_Success; + + // If the top 3 bits of imm are clear, this is a VMOV (immediate) + if (!(imm & 0x38)) { + if (cmode == 0xF) { + if (op == 1) + return MCDisassembler_Fail; + MCInst_setOpcode(Inst, ARM_VMOVv4f32); + } + if (hasFullFP16) { + if (cmode == 0xE) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMOVv2i64); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv16i8); + } + } + if (cmode == 0xD) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMVNv4i32); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv4i32); + } + } + if (cmode == 0xC) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMVNv4i32); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv4i32); + } + } + } + return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); + } + + if (!(imm & 0x20)) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, 64 - imm); + + return S; +} + +static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, + unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); + Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); + unsigned Vn = (fieldFromInstruction_4(Insn, 16, 4) << 0); + Vn |= (fieldFromInstruction_4(Insn, 7, 1) << 4); + unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); + Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); + unsigned q = (fieldFromInstruction_4(Insn, 6, 1) << 0); + unsigned rotate = (fieldFromInstruction_4(Insn, 20, 2) << 0); + + DecodeStatus S = MCDisassembler_Success; +#define DestRegDecoder(Inst, Vd, Address, Decoder) \ + q ? DecodeQPRRegisterClass(Inst, Vd, Address, Decoder) \ + : DecodeDPRRegisterClass(Inst, Vd, Address, Decoder) + + if (!Check(&S, DestRegDecoder(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DestRegDecoder(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DestRegDecoder(Inst, Vn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) + return MCDisassembler_Fail; + // The lane index does not have any bits in the encoding, because it can only + // be 0. + MCOperand_CreateImm0(Inst, 0); + MCOperand_CreateImm0(Inst, rotate); + + return S; +} + +static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 16, 4); + unsigned Rt = fieldFromInstruction_4(Val, 12, 4); + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4); + unsigned Cond = fieldFromInstruction_4(Val, 28, 4); + + if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned CRm = fieldFromInstruction_4(Val, 0, 4); + unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); + unsigned cop = fieldFromInstruction_4(Val, 8, 4); + unsigned Rt = fieldFromInstruction_4(Val, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); + + if ((cop & ~0x1) == 0xa) + return MCDisassembler_Fail; + + if (Rt == Rt2) + S = MCDisassembler_SoftFail; + + // We have to check if the instruction is MRRC2 + // or MCRR2 when constructing the operands for + // Inst. Reason is because MRRC2 stores to two + // registers so it's tablegen desc has has two + // outputs whereas MCRR doesn't store to any + // registers so all of it's operands are listed + // as inputs, therefore the operand order for + // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] + // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] + + if (MCInst_getOpcode(Inst) == ARM_MRRC2) { + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + } + MCOperand_CreateImm0(Inst, cop); + MCOperand_CreateImm0(Inst, opc1); + if (MCInst_getOpcode(Inst) == ARM_MCRR2) { + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + } + MCOperand_CreateImm0(Inst, CRm); + + return S; +} + +static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + /* Ignored bit flags */ + DecodeStatus S = MCDisassembler_Success; + + // Add explicit operand for the destination sysreg, for cases where + // we have to model it for code generation purposes. + switch (MCInst_getOpcode(Inst)) { + case ARM_VMSR_FPSCR_NZCVQC: + MCOperand_CreateReg0(Inst, ARM_FPSCR_NZCV); + break; + case ARM_VMSR_P0: + MCOperand_CreateReg0(Inst, ARM_VPR); + break; + } + + if (MCInst_getOpcode(Inst) != ARM_FMSTAT) { + unsigned Rt = fieldFromInstruction_4(Val, 12, 4); + if (Inst->csh->mode & CS_MODE_THUMB && !Inst->csh->mode & CS_MODE_V8) { + if (Rt == 13 || Rt == 15) + S = MCDisassembler_SoftFail; + Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); + } else + Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); + } + + // Add explicit operand for the source sysreg, similarly to above. + switch (MCInst_getOpcode(Inst)) { + case ARM_VMRS_FPSCR_NZCVQC: + MCOperand_CreateReg0(Inst, ARM_FPSCR_NZCV); + break; + case ARM_VMRS_P0: + MCOperand_CreateReg0(Inst, ARM_VPR); + break; + } + + if (Inst->csh->mode & CS_MODE_THUMB) { + MCOperand_CreateImm0(Inst, ARMCC_AL); + MCOperand_CreateReg0(Inst, 0); + } else { + unsigned pred = fieldFromInstruction_4(Val, 28, 4); + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeBFLabelOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + bool isSigned, bool isNeg, + bool zeroPermitted, int size) { + DecodeStatus S = MCDisassembler_Success; + if (Val == 0 && !zeroPermitted) + S = MCDisassembler_Fail; + + uint64_t DecVal; + if (isSigned) + DecVal = SignExtend32(Val << 1, size + 1); + else + DecVal = (Val << 1); + + // if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, + // Inst, + // Decoder)) + MCOperand_CreateImm0(Inst, isNeg ? -DecVal : DecVal); + return S; +} + +static DecodeStatus DecodeBFAfterTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder) { + + uint64_t LocImm = MCOperand_getImm(MCInst_getOperand(Inst, 0)); + Val = LocImm + (2 << Val); + // if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, + // Decoder)) + MCOperand_CreateImm0(Inst, Val); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePredNoALOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + if (Val >= ARMCC_AL) // also exclude the non-condition NV + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, Val); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLOLoop(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + unsigned Rn; + + if (MCInst_getOpcode(Inst) == ARM_MVE_LCTP) + return S; + + unsigned Imm = fieldFromInstruction_4(Insn, 11, 1) | + fieldFromInstruction_4(Insn, 1, 10) << 1; + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LEUpdate: + case ARM_MVE_LETP: + MCOperand_CreateReg0(Inst, ARM_LR); + MCOperand_CreateReg0(Inst, ARM_LR); + 0x0; + case ARM_t2LE: + if (!Check(&S, DecodeBFLabelOperand(Inst, Imm, Address, Decoder, false, + true, true, 11))) + return MCDisassembler_Fail; + break; + case ARM_t2WLS: + case ARM_MVE_WLSTP_8: + case ARM_MVE_WLSTP_16: + case ARM_MVE_WLSTP_32: + case ARM_MVE_WLSTP_64: + MCOperand_CreateReg0(Inst, ARM_LR); + if (!Check(&S, DecoderGPRRegisterClass(Inst, + fieldFromInstruction_4(Insn, 16, 4), + Address, Decoder)) || + !Check(&S, DecodeBFLabelOperand(Inst, Imm, Address, Decoder, false, + false, true, 11))) + return MCDisassembler_Fail; + break; + case ARM_t2DLS: + case ARM_MVE_DLSTP_8: + case ARM_MVE_DLSTP_16: + case ARM_MVE_DLSTP_32: + case ARM_MVE_DLSTP_64: + Rn = fieldFromInstruction_4(Insn, 16, 4); + if (Rn == 0xF) { + // Enforce all the rest of the instruction bits in LCTP, which + // won't have been reliably checked based on LCTP's own tablegen + // record, because we came to this decode by a roundabout route. + uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; + if ((Insn & ~SBZMask) != CanonicalLCTP) + return MCDisassembler_Fail; // a mandatory bit is wrong: hard fail + if (Insn != CanonicalLCTP) + Check(&S, MCDisassembler_SoftFail); // an SBZ bit is wrong: soft fail + + MCInst_setOpcode(Inst, ARM_MVE_LCTP); + } else { + MCOperand_CreateReg0(Inst, ARM_LR); + if (!Check(&S, DecoderGPRRegisterClass( + Inst, fieldFromInstruction_4(Insn, 16, 4), Address, + Decoder))) + return MCDisassembler_Fail; + } + break; + } + return S; +} + +static DecodeStatus DecodeLongShiftOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + if (Val == 0) + Val = 32; + + MCOperand_CreateImm0(Inst, Val); + + return S; +} + +static DecodeStatus DecodetGPROddRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if ((RegNo) + 1 > 11) + return MCDisassembler_Fail; + + unsigned Register = GPRDecoderTable[(RegNo) + 1]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecodetGPREvenRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if ((RegNo) > 14) + return MCDisassembler_Fail; + + unsigned Register = GPRDecoderTable[(RegNo)]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo == 15) { + MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); + return MCDisassembler_Success; + } + + unsigned Register = GPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + + if (RegNo == 13) + return MCDisassembler_SoftFail; + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeVSCCLRM(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + MCOperand_CreateImm0(Inst, ARMCC_AL); + MCOperand_CreateReg0(Inst, 0); + if (MCInst_getOpcode(Inst) == ARM_VSCCLRMD) { + unsigned reglist = (fieldFromInstruction_4(Insn, 1, 7) << 1) | + (fieldFromInstruction_4(Insn, 12, 4) << 8) | + (fieldFromInstruction_4(Insn, 22, 1) << 12); + if (!Check(&S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { + return MCDisassembler_Fail; + } + } else { + unsigned reglist = fieldFromInstruction_4(Insn, 0, 8) | + (fieldFromInstruction_4(Insn, 22, 1) << 8) | + (fieldFromInstruction_4(Insn, 12, 4) << 9); + if (!Check(&S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { + return MCDisassembler_Fail; + } + } + MCOperand_CreateReg0(Inst, ARM_VPR); + + return S; +} + +static DecodeStatus DecodeMQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + + unsigned Register = QPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static const uint16_t QQPRDecoderTable[] = {ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, + ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, + ARM_Q6_Q7}; + +static DecodeStatus DecodeMQQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 6) + return MCDisassembler_Fail; + + unsigned Register = QQPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static const uint16_t QQQQPRDecoderTable[] = {ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, + ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, + ARM_Q4_Q5_Q6_Q7}; + +static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 4) + return MCDisassembler_Fail; + + unsigned Register = QQQQPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeVPTMaskOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + // Parse VPT mask and encode it in the MCInst as an immediate with the same + // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and + // 't' as 0 and finish with a 1. + unsigned Imm = 0; + // We always start with a 't'. + unsigned CurBit = 0; + for (int i = 3; i >= 0; --i) { + // If the bit we are looking at is not the same as last one, invert the + // CurBit, if it is the same leave it as is. + CurBit ^= (Val >> i) & 1U; + + // Encode the CurBit at the right place in the immediate. + Imm |= (CurBit << i); + + // If we are done, finish the encoding with a 1. + if ((Val & ~(~0U << i)) == 0) { + Imm |= 1U << i; + break; + } + } + + MCOperand_CreateImm0(Inst, Imm); + + return S; +} + +static DecodeStatus DecodeVpredROperand(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + // The vpred_r operand type includes an MQPR register field derived + // from the encoding. But we don't actually want to add an operand + // to the MCInst at this stage, because AddThumbPredicate will do it + // later, and will infer the register number from the TIED_TO + // constraint. So this is a deliberately empty decoder method that + // will inhibit the auto-generated disassembly code from adding an + // operand at all. + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + void *Decoder) { + MCOperand_CreateImm0(Inst, (Val & 0x1) == 0 ? ARMCC_EQ : ARMCC_NE); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + void *Decoder) { + unsigned Code; + switch (Val & 0x3) { + case 0: + Code = ARMCC_GE; + break; + case 1: + Code = ARMCC_LT; + break; + case 2: + Code = ARMCC_GT; + break; + case 3: + Code = ARMCC_LE; + break; + } + MCOperand_CreateImm0(Inst, Code); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + void *Decoder) { + MCOperand_CreateImm0(Inst, (Val & 0x1) == 0 ? ARMCC_HS : ARMCC_HI); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst *Inst, + unsigned Val, + uint64_t Address, + void *Decoder) { + unsigned Code; + switch (Val) { + default: + return MCDisassembler_Fail; + case 0: + Code = ARMCC_EQ; + break; + case 1: + Code = ARMCC_NE; + break; + case 4: + Code = ARMCC_GE; + break; + case 5: + Code = ARMCC_LT; + break; + case 6: + Code = ARMCC_GT; + break; + case 7: + Code = ARMCC_LE; + break; + } + + MCOperand_CreateImm0(Inst, Code); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeVCVTImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned DecodedVal = 64 - Val; + + switch (MCInst_getOpcode(Inst)) { + case ARM_MVE_VCVTf16s16_fix: + case ARM_MVE_VCVTs16f16_fix: + case ARM_MVE_VCVTf16u16_fix: + case ARM_MVE_VCVTu16f16_fix: + if (DecodedVal > 16) + return MCDisassembler_Fail; + break; + case ARM_MVE_VCVTf32s32_fix: + case ARM_MVE_VCVTs32f32_fix: + case ARM_MVE_VCVTf32u32_fix: + case ARM_MVE_VCVTu32f32_fix: + if (DecodedVal > 32) + return MCDisassembler_Fail; + break; + } + + MCOperand_CreateImm0(Inst, 64 - Val); + + return S; +} + +static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + bool Writeback) { + switch (MCInst_getOpcode(Inst)) { + case ARM_VSTR_FPSCR_pre: + case ARM_VSTR_FPSCR_NZCVQC_pre: + case ARM_VLDR_FPSCR_pre: + case ARM_VLDR_FPSCR_NZCVQC_pre: + case ARM_VSTR_FPSCR_off: + case ARM_VSTR_FPSCR_NZCVQC_off: + case ARM_VLDR_FPSCR_off: + case ARM_VLDR_FPSCR_NZCVQC_off: + case ARM_VSTR_FPSCR_post: + case ARM_VSTR_FPSCR_NZCVQC_post: + case ARM_VLDR_FPSCR_post: + case ARM_VLDR_FPSCR_NZCVQC_post: + /* Ignored bit flags */ {} + } + + DecodeStatus S = MCDisassembler_Success; + // FIXME if (unsigned Sysreg = + // FixedRegForVSTRVLDR_SYSREG(MCInst_getOpcode(Inst))) + // MCOperand_CreateReg0(Inst, Sysreg); + unsigned Rn = fieldFromInstruction_4(Val, 16, 4); + unsigned addr = fieldFromInstruction_4(Val, 0, 7) | + (fieldFromInstruction_4(Val, 23, 1) << 7) | (Rn << 8); + + if (Writeback) { + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + if (!Check(&S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, ARMCC_AL); + MCOperand_CreateReg0(Inst, 0); + + return S; +} + +static DecodeStatus DecodeMVE_MEM_1_pre(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + int shift) { + unsigned Rn = fieldFromInstruction_4(Val, 16, 3); + DecodeStatus S = MCDisassembler_Success; + + unsigned Qd = fieldFromInstruction(Val, 13, 3); + unsigned addr = fieldFromInstruction(Val, 0, 7) | + (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeTAddrModeImm7(Inst, addr, Address, Decoder, shift))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeMVE_MEM_2_pre(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + int shift) { + unsigned Rn = fieldFromInstruction_4(Val, 16, 4); + DecodeStatus S = MCDisassembler_Success; + + unsigned Qd = fieldFromInstruction(Val, 13, 3); + unsigned addr = fieldFromInstruction(Val, 0, 7) | + (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); + + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeT2AddrModeImm7(Inst, addr, Address, Decoder, shift, 1))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeMVE_MEM_3_pre(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + int shift) { + unsigned Rn = fieldFromInstruction_4(Val, 17, 3); + DecodeStatus S = MCDisassembler_Success; + + unsigned Qd = fieldFromInstruction(Val, 13, 3); + unsigned addr = fieldFromInstruction(Val, 0, 7) | + (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); + + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMveAddrModeQ(Inst, addr, Address, Decoder, shift))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodePowerTwoOperand(MCInst *Inst, unsigned Val, + uint64_t Address, void *Decoder, + unsigned MinLog, unsigned MaxLog) { + DecodeStatus S = MCDisassembler_Success; + + if (Val < MinLog || Val > MaxLog) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, 1LL << Val); + return S; +} + +static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder, + unsigned start) { + DecodeStatus S = MCDisassembler_Success; + + MCOperand_CreateImm0(Inst, start + Val); + + return S; +} + +static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) | + fieldFromInstruction_4(Insn, 13, 3)); + unsigned index = fieldFromInstruction_4(Insn, 4, 1); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeMVEPairVectorIndexOperand(Inst, index, Address, Decoder, 2))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeMVEPairVectorIndexOperand(Inst, index, Address, Decoder, 0))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) | + fieldFromInstruction_4(Insn, 13, 3)); + unsigned index = fieldFromInstruction_4(Insn, 4, 1); + + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeMVEPairVectorIndexOperand(Inst, index, Address, Decoder, 2))) + return MCDisassembler_Fail; + if (!Check(&S, + DecodeMVEPairVectorIndexOperand(Inst, index, Address, Decoder, 0))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeMVEOverlappingLongShift(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + unsigned RdaLo = fieldFromInstruction_4(Insn, 17, 3) << 1; + unsigned RdaHi = fieldFromInstruction_4(Insn, 9, 3) << 1; + unsigned Rm = fieldFromInstruction_4(Insn, 12, 4); + + if (RdaHi == 14) { + // This value of RdaHi (really indicating pc, because RdaHi has to + // be an odd-numbered register, so the low bit will be set by the + // decode function below) indicates that we must decode as SQRSHR + // or UQRSHL, which both have a single Rda register field with all + // four bits. + unsigned Rda = fieldFromInstruction_4(Insn, 16, 4); + + switch (MCInst_getOpcode(Inst)) { + case ARM_MVE_ASRLr: + case ARM_MVE_SQRSHRL: + MCInst_setOpcode(Inst, ARM_MVE_SQRSHR); + break; + case ARM_MVE_LSLLr: + case ARM_MVE_UQRSHLL: + MCInst_setOpcode(Inst, ARM_MVE_UQRSHL); + break; + default: + llvm_unreachable("Unexpected starting opcode!"); + } + + // Rda as output parameter + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) + return MCDisassembler_Fail; + + // Rda again as input parameter + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) + return MCDisassembler_Fail; + + // Rm, the amount to shift by + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (fieldFromInstruction_4(Insn, 6, 3) != 4) + return MCDisassembler_SoftFail; + + if (Rda == Rm) + return MCDisassembler_SoftFail; + + return S; + } + + // Otherwise, we decode as whichever opcode our caller has already + // put into Inst. Those all look the same: + + // RdaLo,RdaHi as output parameters + if (!Check(&S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) + return MCDisassembler_Fail; + + // RdaLo,RdaHi again as input parameters + if (!Check(&S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) + return MCDisassembler_Fail; + + // Rm, the amount to shift by + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (MCInst_getOpcode(Inst) == ARM_MVE_SQRSHRL || + MCInst_getOpcode(Inst) == ARM_MVE_UQRSHLL) { + unsigned Saturate = fieldFromInstruction_4(Insn, 7, 1); + // Saturate, the bit position for saturation + MCOperand_CreateImm0(Inst, Saturate); + } + + return S; +} + +static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) | + fieldFromInstruction_4(Insn, 13, 3)); + unsigned Qm = ((fieldFromInstruction_4(Insn, 5, 1) << 3) | + fieldFromInstruction_4(Insn, 1, 3)); + unsigned imm6 = fieldFromInstruction_4(Insn, 16, 6); + + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeMVEVCMP(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder, unsigned scalar, + void *omitted) { + DecodeStatus S = MCDisassembler_Success; + MCOperand_CreateReg0(Inst, ARM_VPR); + unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) + return MCDisassembler_Fail; + + unsigned fc; + + if (scalar) { + fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | + fieldFromInstruction_4(Insn, 7, 1) | + fieldFromInstruction_4(Insn, 5, 1) << 1; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + if (!Check(&S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else { + fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | + fieldFromInstruction_4(Insn, 7, 1) | + fieldFromInstruction_4(Insn, 0, 1) << 1; + unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) << 4 | + fieldFromInstruction_4(Insn, 1, 3); + if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) + return MCDisassembler_Fail; + } + + // if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) + // return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, /*ARMVCC_None*/ 0); + MCOperand_CreateReg0(Inst, 0); + MCOperand_CreateImm0(Inst, 0); + + return S; +} + +static DecodeStatus DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + MCOperand_CreateReg0(Inst, ARM_VPR); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + return S; +} + +static DecodeStatus DecodeMVEVPNOT(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + MCOperand_CreateReg0(Inst, ARM_VPR); + MCOperand_CreateReg0(Inst, ARM_VPR); + return S; +} + +static DecodeStatus DecodeT2AddSubSPImm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + const unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); + const unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + const unsigned Imm12 = fieldFromInstruction_4(Insn, 26, 1) << 11 | + fieldFromInstruction_4(Insn, 12, 3) << 8 | + fieldFromInstruction_4(Insn, 0, 8); + const unsigned TypeT3 = fieldFromInstruction_4(Insn, 25, 1); + unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); + unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); + unsigned S = fieldFromInstruction_4(Insn, 20, 1); + if (sign1 != sign2) + return MCDisassembler_Fail; + + // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) + DecodeStatus DS = MCDisassembler_Success; + if ((!Check(&DS, + DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst + (!Check(&DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) + return MCDisassembler_Fail; + if (TypeT3) { + MCInst_setOpcode(Inst, sign1 ? ARM_t2SUBspImm12 : ARM_t2ADDspImm12); + S = 0; + MCOperand_CreateImm0(Inst, Imm12); // zext imm12 + } else { + MCInst_setOpcode(Inst, sign1 ? ARM_t2SUBspImm : ARM_t2ADDspImm); + if (!Check(&DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 + return MCDisassembler_Fail; + } + if (!Check(&DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, 0); // pred + + return DS; +} \ No newline at end of file diff --git a/arch/Mips/CapstoneMipsModule.h b/arch/Mips/CapstoneMipsModule.h new file mode 100644 index 0000000000..e0fbaf7ae2 --- /dev/null +++ b/arch/Mips/CapstoneMipsModule.h @@ -0,0 +1,1922 @@ +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeJumpTarget(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMem(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMemEVA(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLoadByte15(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCacheOp(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePrefeOpMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSyncI(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSyncI_MM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSynciR6(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMImm9(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFMemMMR2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst *Inst, unsigned Value, + uint64_t Address, + void *Decoder, unsigned, + unsigned, unsigned); + +static DecodeStatus DecodeUImmWithOffset(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder, + unsigned Bits, unsigned Offset) { + return DecodeUImmWithOffsetAndScale(Inst, Value, Address, Decoder, Bits, + Offset, 1); +} +static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst *Inst, unsigned Value, + uint64_t Address, + void *Decoder, unsigned); + +static DecodeStatus DecodeInsSize(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeINSVE_DF(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDAHIDATI(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDAHIDATI(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeDINS(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDEXT(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeCRC(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeMovePOperands(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); + +#include "MipsGenDisassemblerTables.inc" + +static DecodeStatus DecodeINSVE_DF(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + DecodeStatus (*RegDecoder)(MCInst *, unsigned, uint64_t, MCRegisterInfo *); + + // The size of the n field depends on the element size + // The register class also depends on this. + unsigned tmp = fieldFromInstruction(insn, 17, 5); + unsigned NSize = 0; + RegDecoder = 0x0; + if ((tmp & 0x18) == 0x00) { // INSVE_B + NSize = 4; + RegDecoder = DecodeMSA128BRegisterClass; + } else if ((tmp & 0x1c) == 0x10) { // INSVE_H + NSize = 3; + RegDecoder = DecodeMSA128HRegisterClass; + } else if ((tmp & 0x1e) == 0x18) { // INSVE_W + NSize = 2; + RegDecoder = DecodeMSA128WRegisterClass; + } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D + NSize = 1; + RegDecoder = DecodeMSA128DRegisterClass; + } else + llvm_unreachable("Invalid encoding"); + + assert(NSize != 0 && RegDecoder != 0x0); + + // $wd + tmp = fieldFromInstruction(insn, 6, 5); + if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + // $wd_in + if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + // $n + tmp = fieldFromInstruction(insn, 16, NSize); + MCOperand_CreateImm0(MI, tmp); + // $ws + tmp = fieldFromInstruction(insn, 11, 5); + if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) + return MCDisassembler_Fail; + // $n2 + MCOperand_CreateImm0(MI, 0); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + unsigned Rs = fieldFromInstruction(insn, 16, 5); + unsigned Imm = fieldFromInstruction(insn, 0, 16); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDAHIDATI(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Imm = fieldFromInstruction(insn, 0, 16); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the ADDI instruction from the earlier + // ISA's instead). + // + // We have: + // 0b001000 sssss ttttt iiiiiiiiiiiiiiii + // BOVC if rs >= rt + // BEQZALC if rs == 0 && rt != 0 + // BEQC if rs < rt && rs != 0 + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BOVC); + HasRs = true; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BEQC); + HasRs = true; + } else + MCInst_setOpcode(MI, Mips_BEQZALC); + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, + void *Decoder) { + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = 0; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BOVC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BEQC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + } else { + MCInst_setOpcode(MI, Mips_BEQZALC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the ADDI instruction from the earlier + // ISA's instead). + // + // We have: + // 0b011000 sssss ttttt iiiiiiiiiiiiiiii + // BNVC if rs >= rt + // BNEZALC if rs == 0 && rt != 0 + // BNEC if rs < rt && rs != 0 + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BNVC); + HasRs = true; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BNEC); + HasRs = true; + } else + MCInst_setOpcode(MI, Mips_BNEZALC); + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, + void *Decoder) { + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = 0; + + if (Rs >= Rt) { + MCInst_setOpcode(MI, Mips_BNVC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else if (Rs != 0 && Rs < Rt) { + MCInst_setOpcode(MI, Mips_BNEC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + } else { + MCInst_setOpcode(MI, Mips_BNEZALC_MMR6); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, + void *Decoder) { + // We have: + // 0b110101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZC_MMR6 if rs == 0 && rt != 0 + // BLTZC_MMR6 if rs == rt && rt != 0 + // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 + + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BGTZC_MMR6); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BLTZC_MMR6); + else { + MCInst_setOpcode(MI, Mips_BLTC_MMR6); + HasRs = true; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, + void *Decoder) { + // We have: + // 0b111101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZC_MMR6 if rs == 0 && rt != 0 + // BGEZC_MMR6 if rs == rt && rt != 0 + // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 + + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BLEZC_MMR6); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BGEZC_MMR6); + else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEC_MMR6); + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BLEZL instruction from the earlier + // ISA's instead). + // + // We have: + // 0b010110 sssss ttttt iiiiiiiiiiiiiiii + // Invalid if rs == 0 + // BLEZC if rs == 0 && rt != 0 + // BGEZC if rs == rt && rt != 0 + // BGEC if rs != rt && rs != 0 && rt != 0 + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BLEZC); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BGEZC); + else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEC); + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BGTZL instruction from the earlier + // ISA's instead). + // + // We have: + // 0b010111 sssss ttttt iiiiiiiiiiiiiiii + // Invalid if rs == 0 + // BGTZC if rs == 0 && rt != 0 + // BLTZC if rs == rt && rt != 0 + // BLTC if rs != rt && rs != 0 && rt != 0 + + bool HasRs = false; + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BGTZC); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BLTZC); + else { + MCInst_setOpcode(MI, Mips_BLTC); + HasRs = true; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BGTZ instruction from the earlier + // ISA's instead). + // + // We have: + // 0b000111 sssss ttttt iiiiiiiiiiiiiiii + // BGTZ if rt == 0 + // BGTZALC if rs == 0 && rt != 0 + // BLTZALC if rs != 0 && rs == rt + // BLTUC if rs != 0 && rs != rt + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + bool HasRt = false; + + if (Rt == 0) { + MCInst_setOpcode(MI, Mips_BGTZ); + HasRs = true; + } else if (Rs == 0) { + MCInst_setOpcode(MI, Mips_BGTZALC); + HasRt = true; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, Mips_BLTZALC); + HasRs = true; + } else { + MCInst_setOpcode(MI, Mips_BLTUC); + HasRs = true; + HasRt = true; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + if (HasRt) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled + // (otherwise we would have matched the BLEZL instruction from the earlier + // ISA's instead). + // + // We have: + // 0b000110 sssss ttttt iiiiiiiiiiiiiiii + // Invalid if rs == 0 + // BLEZALC if rs == 0 && rt != 0 + // BGEZALC if rs == rt && rt != 0 + // BGEUC if rs != rt && rs != 0 && rt != 0 + + unsigned Rs = fieldFromInstruction(insn, 21, 5); + unsigned Rt = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) + MCInst_setOpcode(MI, Mips_BLEZALC); + else if (Rs == Rt) + MCInst_setOpcode(MI, Mips_BGEZALC); + else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEUC); + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDEXT(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder) { + unsigned Msbd = fieldFromInstruction(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + + switch (MCInst_getOpcode(MI)) { + case Mips_DEXT: + Pos = Lsb; + Size = Msbd + 1; + break; + case Mips_DEXTM: + Pos = Lsb; + Size = Msbd + 1 + 32; + break; + case Mips_DEXTU: + Pos = Lsb + 32; + Size = Msbd + 1; + break; + default: + llvm_unreachable("Unknown DEXT instruction!"); + } + + MCInst_setOpcode(MI, Mips_DEXT); + + unsigned Rs = fieldFromInstruction(Insn, 21, 5); + unsigned Rt = fieldFromInstruction(Insn, 16, 5); + + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateImm0(MI, Pos); + MCOperand_CreateImm0(MI, Size); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDINS(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder) { + unsigned Msbd = fieldFromInstruction(Insn, 11, 5); + unsigned Lsb = fieldFromInstruction(Insn, 6, 5); + unsigned Size = 0; + unsigned Pos = 0; + + switch (MCInst_getOpcode(MI)) { + case Mips_DINS: + Pos = Lsb; + Size = Msbd + 1 - Pos; + break; + case Mips_DINSM: + Pos = Lsb; + Size = Msbd + 33 - Pos; + break; + case Mips_DINSU: + Pos = Lsb + 32; + // mbsd = pos + size - 33 + // mbsd - pos + 33 = size + Size = Msbd + 33 - Pos; + break; + default: + llvm_unreachable("Unknown DINS instruction!"); + } + + unsigned Rs = fieldFromInstruction(Insn, 21, 5); + unsigned Rt = fieldFromInstruction(Insn, 16, 5); + + MCInst_setOpcode(MI, Mips_DINS); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR64RegClassID, Rs)); + MCOperand_CreateImm0(MI, Pos); + MCOperand_CreateImm0(MI, Size); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCRC(MCInst *MI, unsigned Insn, uint64_t Address, + void *Decoder) { + unsigned Rs = fieldFromInstruction(Insn, 21, 5); + unsigned Rt = fieldFromInstruction(Insn, 16, 5); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + return MCDisassembler_Fail; +} + +static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_GPR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_GPRMM16RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_GPRMM16ZeroRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, + unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_GPRMM16MovePRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (Inst->csh->mode & CS_MODE_MIPS64) + return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); + + return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); +} +static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_FGR64RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_FGR32RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_CCRRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, Mips_FCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_FGRCCRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMem(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SC || MCInst_getOpcode(Inst) == Mips_SCD) + MCOperand_CreateReg0(Inst, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemEVA(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn >> 7, 9); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SCE) + MCOperand_CreateReg0(Inst, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeLoadByte15(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeCacheOp(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Hint = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeCacheOpMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0xfff, 12); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Hint = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} +static DecodeStatus DecodePrefeOpMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x1ff, 9); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Hint = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn >> 7, 9); + unsigned Hint = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + MCOperand_CreateImm0(Inst, Hint); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeSyncI(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeSyncI_MM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeSynciR6(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Immediate = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Immediate); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); + unsigned Reg = fieldFromInstruction(Insn, 6, 5); + unsigned Base = fieldFromInstruction(Insn, 11, 5); + + Reg = getReg(Inst->MRI, Mips_MSA128BRegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + + // The immediate field of an LD/ST instruction is scaled which means it must + // be multiplied (when decoding) by the size (in bytes) of the instructions' + // data format. + // .b - 1 byte + // .h - 2 bytes + // .w - 4 bytes + // .d - 8 bytes + switch (MCInst_getOpcode(Inst)) { + default: + assert(false && "Unexpected instruction"); + return MCDisassembler_Fail; + break; + case Mips_LD_B: + case Mips_ST_B: + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_LD_H: + case Mips_ST_H: + MCOperand_CreateImm0(Inst, Offset * 2); + break; + case Mips_LD_W: + case Mips_ST_W: + MCOperand_CreateImm0(Inst, Offset * 4); + break; + case Mips_LD_D: + case Mips_ST_D: + MCOperand_CreateImm0(Inst, Offset * 8); + break; + } + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemMMImm4(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Offset = Insn & 0xf; + unsigned Reg = fieldFromInstruction(Insn, 7, 3); + unsigned Base = fieldFromInstruction(Insn, 4, 3); + + switch (MCInst_getOpcode(Inst)) { + case Mips_LBU16_MM: + case Mips_LHU16_MM: + case Mips_LW16_MM: + if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + break; + case Mips_SB16_MM: + case Mips_SB16_MMR6: + case Mips_SH16_MM: + case Mips_SH16_MMR6: + case Mips_SW16_MM: + case Mips_SW16_MMR6: + if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + break; + } + + if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + case Mips_LBU16_MM: + if (Offset == 0xf) + MCOperand_CreateImm0(Inst, -1); + else + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_SB16_MM: + case Mips_SB16_MMR6: + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_LHU16_MM: + case Mips_SH16_MM: + case Mips_SH16_MMR6: + MCOperand_CreateImm0(Inst, Offset << 1); + break; + case Mips_LW16_MM: + case Mips_SW16_MM: + case Mips_SW16_MMR6: + MCOperand_CreateImm0(Inst, Offset << 2); + break; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Offset = Insn & 0x1F; + unsigned Reg = fieldFromInstruction(Insn, 5, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Mips_SP); + MCOperand_CreateImm0(Inst, Offset << 2); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Offset = Insn & 0x7F; + unsigned Reg = fieldFromInstruction(Insn, 7, 3); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Mips_GP); + MCOperand_CreateImm0(Inst, Offset << 2); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + int Offset; + switch (MCInst_getOpcode(Inst)) { + case Mips_LWM16_MMR6: + case Mips_SWM16_MMR6: + Offset = fieldFromInstruction(Insn, 4, 4); + break; + default: + Offset = SignExtend32(Insn & 0xf, 4); + break; + } + + if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, Mips_SP); + MCOperand_CreateImm0(Inst, Offset << 2); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemMMImm9(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x1ff, 9); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SCE_MM || + MCInst_getOpcode(Inst) == Mips_SC_MMR6) + MCOperand_CreateReg0(Inst, Reg); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemMMImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x0fff, 12); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + switch (MCInst_getOpcode(Inst)) { + case Mips_SWM32_MM: + case Mips_LWM32_MM: + if (DecodeRegListOperand(Inst, Insn, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + break; + case Mips_SC_MM: + MCOperand_CreateReg0(Inst, Reg); + 0x0; + default: + MCOperand_CreateReg0(Inst, Reg); + if (MCInst_getOpcode(Inst) == Mips_LWP_MM || + MCInst_getOpcode(Inst) == Mips_SWP_MM) + MCOperand_CreateReg0(Inst, Reg + 1); + + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + } + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMemMMImm16(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Inst->MRI, Mips_GPR32RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMemMMR2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + // This function is the same as DecodeFMem but with the Reg and Base fields + // swapped according to microMIPS spec. + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_FGR64RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_COP2RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int Offset = SignExtend32(Insn & 0xffff, 16); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Inst->MRI, Mips_COP3RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x07ff, 11); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 11, 5); + + Reg = getReg(Inst->MRI, Mips_COP2RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int Offset = SignExtend32(Insn & 0x07ff, 11); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Inst->MRI, Mips_COP2RegClassID, Reg); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + MCOperand_CreateReg0(Inst, Reg); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + int64_t Offset = SignExtend64(Insn >> 7, 9) & 0x1ff; + unsigned Rt = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Rt = getReg(Inst->MRI, Mips_GPR32RegClassID, Rt); + Base = getReg(Inst->MRI, Mips_GPR32RegClassID, Base); + + if (MCInst_getOpcode(Inst) == Mips_SC_R6 || + MCInst_getOpcode(Inst) == Mips_SCD_R6) { + MCOperand_CreateReg0(Inst, Rt); + } + + MCOperand_CreateReg0(Inst, Rt); + MCOperand_CreateReg0(Inst, Base); + MCOperand_CreateImm0(Inst, Offset); + + return MCDisassembler_Success; +} +static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + // Currently only hardware register 29 is supported. + if (RegNo != 29) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, Mips_HWR29); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 30 || RegNo % 2) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_AFGR64RegClassID, RegNo / 2); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= 4) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_ACC64DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= 4) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_HI32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= 4) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_LO32DSPRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSA128BRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSA128HRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSA128WRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSA128DRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 7) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_MSACtrlRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_COP0RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = getReg(Inst->MRI, Mips_COP2RegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = (SignExtend32(Offset, 16) * 4) + 4; + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = (SignExtend32(Offset, 16) * 2); + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeJumpTarget(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + debugln("jump target decode"); + unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; + MCOperand_CreateImm0(Inst, JumpOffset); + debugln("with exit"); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset, 21) * 4 + 4; + + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset, 21) * 4 + 4; + + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset, 26) * 4 + 4; + + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset << 1, 8); + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset << 1, 11); + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + // llvm has a plus 4 out here - which turns out to be inconsitent with our + // test suite + int32_t BranchOffset = SignExtend32(Offset, 16) * 2 /* + 4 */; + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, + uint64_t Address, void *Decoder) { + int32_t BranchOffset = SignExtend32(Offset << 1, 27); + + MCOperand_CreateImm0(Inst, BranchOffset + Address); + return MCDisassembler_Success; +} +static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; + MCOperand_CreateImm0(Inst, JumpOffset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; + MCOperand_CreateImm0(Inst, JumpOffset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder) { + if (Value == 0) + MCOperand_CreateImm0(Inst, 1); + else if (Value == 0x7) + MCOperand_CreateImm0(Inst, -1); + else + MCOperand_CreateImm0(Inst, Value << 2); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder) { + if (Value == 0x7F) + MCOperand_CreateImm0(Inst, -1); + else + MCOperand_CreateImm0(Inst, Value); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, Value == 0x0 ? 8 : Value); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst *Inst, unsigned Value, + uint64_t Address, + void *Decoder, unsigned Bits, + unsigned Offset, + unsigned Scale) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + MCOperand_CreateImm0(Inst, Value + Offset); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst *Inst, unsigned Value, + uint64_t Address, + void *Decoder, unsigned Bits) { + unsigned Offset = 0; // we don't have default values in C, so here it goes + unsigned ScaleBy = 1; + int32_t Imm = SignExtend32(Value, Bits) * ScaleBy; + debug("after extend %d\n", Imm); + MCOperand_CreateImm0(Inst, (int64_t)Imm + Offset); + debug("created Imm0 %ld\n", (int64_t)Imm + Offset); + return MCDisassembler_Success; +} +static DecodeStatus DecodeInsSize(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + // First we need to grab the pos(lsb) from MCInst. + // This function only handles the 32 bit variants of ins, as dins + // variants are handled differently. + int Pos = MCOperand_getImm(MCInst_getOperand(Inst, 2)); + int Size = (int)Insn - Pos + 1; + MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); + return MCDisassembler_Success; +} +static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); + return MCDisassembler_Success; +} +static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, uint64_t Address, + void *Decoder) { + int32_t DecodedValue; + switch (Insn) { + case 0: + DecodedValue = 256; + break; + case 1: + DecodedValue = 257; + break; + case 510: + DecodedValue = -258; + break; + case 511: + DecodedValue = -257; + break; + default: + DecodedValue = SignExtend32(Insn, 9); + break; + } + MCOperand_CreateImm0(Inst, DecodedValue * 4); + return MCDisassembler_Success; +} +static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + // Insn must be >= 0, since it is unsigned that condition is always true. + assert(Insn < 16); + int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, + 16, 31, 32, 63, 64, 255, 32768, 65535}; + MCOperand_CreateImm0(Inst, DecodedValues[Insn]); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, + Mips_S5, Mips_S6, Mips_S7, Mips_FP}; + unsigned RegNum; + + unsigned RegLst = fieldFromInstruction(Insn, 21, 5); + + // Empty register lists are not allowed. + if (RegLst == 0) + return MCDisassembler_Fail; + + RegNum = RegLst & 0xf; + + // RegLst values 10-15, and 26-31 are reserved. + if (RegNum > 9) + return MCDisassembler_Fail; + + for (unsigned i = 0; i < RegNum; i++) + MCOperand_CreateReg0(Inst, Regs[i]); + + if (RegLst & 0x10) + MCOperand_CreateReg0(Inst, Mips_RA); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; + unsigned RegLst; + switch (MCInst_getOpcode(Inst)) { + default: + RegLst = fieldFromInstruction(Insn, 4, 2); + break; + case Mips_LWM16_MMR6: + case Mips_SWM16_MMR6: + RegLst = fieldFromInstruction(Insn, 8, 2); + break; + } + unsigned RegNum = RegLst & 0x3; + + for (unsigned i = 0; i <= RegNum; i++) + MCOperand_CreateReg0(Inst, Regs[i]); + + MCOperand_CreateReg0(Inst, Mips_RA); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMovePOperands(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + unsigned RegPair = fieldFromInstruction(Insn, 7, 3); + if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + unsigned RegRs; + if (Inst->csh->mode & CS_MODE_MIPS32R6) + RegRs = fieldFromInstruction(Insn, 0, 2) | + (fieldFromInstruction(Insn, 3, 1) << 2); + else + RegRs = fieldFromInstruction(Insn, 1, 3); + if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + unsigned RegRt = fieldFromInstruction(Insn, 4, 3); + if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == + MCDisassembler_Fail) + return MCDisassembler_Fail; + + return MCDisassembler_Success; +} +static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, + uint64_t Address, void *Decoder) { + switch (RegPair) { + default: + return MCDisassembler_Fail; + case 0: + MCOperand_CreateReg0(Inst, Mips_A1); + MCOperand_CreateReg0(Inst, Mips_A2); + break; + case 1: + MCOperand_CreateReg0(Inst, Mips_A1); + MCOperand_CreateReg0(Inst, Mips_A3); + break; + case 2: + MCOperand_CreateReg0(Inst, Mips_A2); + MCOperand_CreateReg0(Inst, Mips_A3); + break; + case 3: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_S5); + break; + case 4: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_S6); + break; + case 5: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_A1); + break; + case 6: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_A2); + break; + case 7: + MCOperand_CreateReg0(Inst, Mips_A0); + MCOperand_CreateReg0(Inst, Mips_A3); + break; + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) { + MCOperand_CreateImm0(Inst, SignExtend32(Insn << 2, 25)); + return MCDisassembler_Success; +} +static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // We have: + // 0b000111 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZALC_MMR6 if rs == 0 && rt != 0 + // BLTZALC_MMR6 if rs != 0 && rs == rt + // BLTUC_MMR6 if rs != 0 && rs != rt + + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + unsigned Imm = 0; + bool HasRs = false; + bool HasRt = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) { + MCInst_setOpcode(MI, Mips_BGTZALC_MMR6); + HasRt = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, Mips_BLTZALC_MMR6); + HasRs = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else { + MCInst_setOpcode(MI, Mips_BLTUC_MMR6); + HasRs = true; + HasRt = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + + if (HasRt) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, unsigned insn, + uint64_t Address, void *Decoder) { + // We have: + // 0b000110 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZALC_MMR6 if rs == 0 && rt != 0 + // BGEZALC_MMR6 if rs == rt && rt != 0 + // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 + + unsigned Rt = fieldFromInstruction(insn, 21, 5); + unsigned Rs = fieldFromInstruction(insn, 16, 5); + unsigned Imm = 0; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler_Fail; + else if (Rs == 0) { + MCInst_setOpcode(MI, Mips_BLEZALC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else if (Rs == Rt) { + MCInst_setOpcode(MI, Mips_BGEZALC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else { + HasRs = true; + MCInst_setOpcode(MI, Mips_BGEUC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + } + + if (HasRs) + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rs)); + MCOperand_CreateReg0(MI, getReg(MI->MRI, Mips_GPR32RegClassID, Rt)); + + MCOperand_CreateImm0(MI, Imm); + + return MCDisassembler_Success; +} \ No newline at end of file diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c index 294082394a..12e83eb194 100644 --- a/arch/Mips/MipsDisassembler.c +++ b/arch/Mips/MipsDisassembler.c @@ -36,1759 +36,306 @@ #include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" //#include "llvm/MC/MCSubtargetInfo.h" -#include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" +#include "../../MCRegisterInfo.h" // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeJumpTarget(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget21(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBranchTarget26(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); - -// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); - -// DecodeBranchTargetMM - Decode microMIPS branch offset, which is -// shifted left by 1 bit. -static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); - -// DecodeJumpTargetMM - Decode microMIPS jump target, which is -// shifted left by 1 bit. -static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCacheOp(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCacheOpR6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeCacheOpMM(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSyncI(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMSA128Mem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm4(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm12(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMemMMImm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeLiSimm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm4(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -// Decode the immediate field of an LSA instruction which -// is off by one. -static DecodeStatus DecodeLSAImm(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeInsSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeExtSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm9SP(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeANDI16Imm(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); - -/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't -/// handle. -static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeRegListOperand(MCInst *Inst, - uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); - -static DecodeStatus DecodeRegListOperand16(MCInst *Inst, - uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); - -static DecodeStatus DecodeMovePRegPair(MCInst *Inst, - uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); - #define GET_SUBTARGETINFO_ENUM -#include "MipsGenSubtargetInfo.inc" - -// Hacky: enable all features for disassembler -static uint64_t getFeatureBits(int mode) -{ - uint64_t Bits = (uint64_t)-1; // include every features at first - - // By default we do not support Mips1 - Bits &= ~Mips_FeatureMips1; - - // No MicroMips - Bits &= ~Mips_FeatureMicroMips; +//#include "MipsGenSubtargetInfo.inc" - // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() - // some features are mutually execlusive - if (mode & CS_MODE_16) { - //Bits &= ~Mips_FeatureMips32r2; - //Bits &= ~Mips_FeatureMips32; - //Bits &= ~Mips_FeatureFPIdx; - //Bits &= ~Mips_FeatureBitCount; - //Bits &= ~Mips_FeatureSwap; - //Bits &= ~Mips_FeatureSEInReg; - //Bits &= ~Mips_FeatureMips64r2; - //Bits &= ~Mips_FeatureFP64Bit; - } else if (mode & CS_MODE_32) { - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureFP64Bit; - Bits &= ~Mips_FeatureMips64r2; - Bits &= ~Mips_FeatureMips32r6; - Bits &= ~Mips_FeatureMips64r6; - } else if (mode & CS_MODE_64) { - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureMips64r6; - Bits &= ~Mips_FeatureMips32r6; - } else if (mode & CS_MODE_MIPS32R6) { - Bits |= Mips_FeatureMips32r6; - Bits &= ~Mips_FeatureMips16; - Bits &= ~Mips_FeatureFP64Bit; - Bits &= ~Mips_FeatureMips64r6; - Bits &= ~Mips_FeatureMips64r2; - } +#include "../../sync/logger.h" - if (mode & CS_MODE_MICRO) { - Bits |= Mips_FeatureMicroMips; - Bits &= ~Mips_FeatureMips4_32r2; - Bits &= ~Mips_FeatureMips2; - } - - return Bits; -} - -#include "MipsGenDisassemblerTables.inc" +#define UNIT ((uint64_t)1) +static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo); +// static uint64_t getFeatureBits(int mode); +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require); #define GET_REGINFO_ENUM -#include "MipsGenRegisterInfo.inc" - #define GET_REGINFO_MC_DESC -#include "MipsGenRegisterInfo.inc" - #define GET_INSTRINFO_ENUM -#include "MipsGenInstrInfo.inc" - -void Mips_init(MCRegisterInfo *MRI) -{ - // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC, - // MipsMCRegisterClasses, 62, - // MipsRegUnitRoots, - // 273, - // MipsRegDiffLists, - // MipsLaneMaskLists, - // MipsRegStrings, - // MipsRegClassStrings, - // MipsSubRegIdxLists, - // 12, - // MipsSubRegIdxRanges, - // MipsRegEncodingTable); - +#define MIPS_GET_DISASSEMBLER +#include "CapstoneMipsModule.h" + +/// Extract 'not' into Require, Require being '0' or 'false' means returns true +/// when the feature is not available Also we're not using bits to represent +/// feature anymore (for obvious reason) +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require) { + debugln("checking feature %d against %d %d", Feature, Bits, Require); + // if(Feature == Mips_FeatureFP64Bit) return true; // enables all fp + // instructions (32/64) + switch (Feature) { + default: + return true; // For arbitrary checks we always declare it true - enables all + // checks + case Mips_FeatureMips1: // Disabled features + case Mips_FeatureMicroMips: + return getbool(Bits & CS_MODE_MICRO) == Require; + case Mips_FeatureMips4_32r2: + case Mips_FeatureMips2: + return getbool(Bits & CS_MODE_MICRO) != Require; // these two are disabled + case Mips_FeatureSoftFloat: // Soft float represents no instruction + return !Require; + case Mips_FeatureMips16: + return getbool(Bits & CS_MODE_16) == Require; + case Mips_FeatureMips32r6: + return getbool(Bits & CS_MODE_MIPS32R6) == Require; + case Mips_FeatureMips64r6: + return getbool(Bits & (CS_MODE_16 | CS_MODE_32 | CS_MODE_MIPS32R6 | + CS_MODE_64)) != Require; + case Mips_FeatureFP64Bit: + return true; // enable this feature if required + case Mips_FeatureMips64r2: + return getbool(Bits & CS_MODE_64) == Require; + } + return false; // unreachable +} +// +//// Hacky: enable all features for disassembler +// static uint64_t getFeatureBits(int mode) +//{ +// uint64_t Bits = (uint64_t)-1; // include every features at first +// +// // By default we do not support Mips1 +// Bits &= ~(UNIT << Mips_FeatureMips1); +// +// // No MicroMips +// Bits &= ~(UNIT << Mips_FeatureMicroMips); +// +// +// // Disable soft float +// Bits &= ~(UNIT << Mips_FeatureSoftFloat); +// +// // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() +// // some features are mutually execlusive +// if (mode & CS_MODE_16) { +// // Bits &= ~Mips_FeatureMips32r2; +// // Bits &= ~Mips_FeatureMips32; +// // Bits &= ~Mips_FeatureFPIdx; +// // Bits &= ~Mips_FeatureBitCount; +// // Bits &= ~Mips_FeatureSwap; +// // Bits &= ~Mips_FeatureSEInReg; +// // Bits &= ~Mips_FeatureMips64r2; +// // Bits &= ~Mips_FeatureFP64Bit; +// } else if (mode & CS_MODE_32) { +// Bits &= ~(UNIT << Mips_FeatureMips16); +// Bits &= ~(UNIT << Mips_FeatureFP64Bit); +// Bits &= ~(UNIT << Mips_FeatureMips64r2); +// Bits &= ~(UNIT << Mips_FeatureMips32r6); +// Bits &= ~(UNIT << Mips_FeatureMips64r6); +// } else if (mode & CS_MODE_64) { +// Bits &= ~(UNIT << Mips_FeatureMips16); +// Bits &= ~(UNIT << Mips_FeatureMips64r6); +// Bits &= ~(UNIT << Mips_FeatureMips32r6); +// } else if (mode & CS_MODE_MIPS32R6) { +// Bits |= (UNIT << Mips_FeatureMips32r6); +// Bits &= ~(UNIT << Mips_FeatureMips16); +// Bits &= ~(UNIT << Mips_FeatureFP64Bit); +// Bits &= ~(UNIT << Mips_FeatureMips64r6); +// Bits &= ~(UNIT << Mips_FeatureMips64r2); +// } +// +// if (mode & CS_MODE_MICRO) { +// Bits |= (UNIT << Mips_FeatureMicroMips); +// Bits &= ~(UNIT << Mips_FeatureMips4_32r2); +// Bits &= ~(UNIT << Mips_FeatureMips2); +// } +// +// return Bits; +//} - MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394, - 0, 0, - MipsMCRegisterClasses, 62, - 0, 0, - MipsRegDiffLists, - 0, - MipsSubRegIdxLists, 12, - 0); +//#define GET_REGINFO_ENUM +//#include "MipsGenRegisterInfo.inc" +// +//#define GET_REGINFO_MC_DESC +//#include "MipsGenRegisterInfo.inc" +// +//#define GET_INSTRINFO_ENUM +//#include "MipsGenInstrInfo.inc" + +void Mips_init(MCRegisterInfo *MRI) { + // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC, + // MipsMCRegisterClasses, 62, + // MipsRegUnitRoots, + // 273, + // MipsRegDiffLists, + // MipsLaneMaskLists, + // MipsRegStrings, + // MipsRegClassStrings, + // MipsSubRegIdxLists, + // 12, + // MipsSubRegIdxRanges, + // MipsRegEncodingTable); + + MCRegisterInfo_InitMCRegisterInfo( + MRI, MipsRegDesc, ARR_SIZE(MipsRegDesc), 0, 0, MipsMCRegisterClasses, + ARR_SIZE(MipsMCRegisterClasses), 0, 0, MipsRegDiffLists, 0, + MipsSubRegIdxLists, ARR_SIZE(MipsSubRegIdxLists), 0); } /// Read two bytes from the ArrayRef and return 16 bit halfword sorted /// according to the given endianess. static void readInstruction16(unsigned char *code, uint32_t *insn, - bool isBigEndian) -{ - // We want to read exactly 2 Bytes of data. - if (isBigEndian) - *insn = (code[0] << 8) | code[1]; - else - *insn = (code[1] << 8) | code[0]; + bool isBigEndian) { + // We want to read exactly 2 Bytes of data. + if (isBigEndian) + *insn = (code[0] << 8) | code[1]; + else + *insn = (code[1] << 8) | code[0]; } /// readInstruction - read four bytes from the MemoryObject /// and return 32 bit word sorted according to the given endianess -static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) -{ - // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) - // always precede the low 16 bits in the instruction stream (that is, they - // are placed at lower addresses in the instruction stream). - // - // microMIPS byte ordering: - // Big-endian: 0 | 1 | 2 | 3 - // Little-endian: 1 | 0 | 3 | 2 - - // We want to read exactly 4 Bytes of data. - if (isBigEndian) { - // Encoded as a big-endian 32-bit word in the stream. - *insn = - (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); - } else { - if (isMicroMips) { - *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) | - ((uint32_t) code[1] << 24); - } else { - *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | - ((uint32_t) code[3] << 24); - } - } -} - -static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, - const uint8_t *code, size_t code_len, - uint16_t *Size, - uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) -{ - uint32_t Insn; - DecodeStatus Result; - - if (instr->flat_insn->detail) { - memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips)); - } - - if (mode & CS_MODE_MICRO) { - if (code_len < 2) - // not enough data - return MCDisassembler_Fail; - - readInstruction16((unsigned char*)code, &Insn, isBigEndian); - - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 2; - return Result; - } - - if (code_len < 4) - // not enough data - return MCDisassembler_Fail; - - readInstruction32((unsigned char*)code, &Insn, isBigEndian, true); - - //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - return MCDisassembler_Fail; - } - - if (code_len < 4) - // not enough data - return MCDisassembler_Fail; - - readInstruction32((unsigned char*)code, &Insn, isBigEndian, false); - - if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) { - // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } - - if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) { - // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, - Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } - - if (mode & CS_MODE_MIPS32R6) { - // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, - Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } - - if (mode & CS_MODE_MIPS64) { - // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips6432, instr, Insn, - Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - } - - // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 4; - return Result; - } - - return MCDisassembler_Fail; -} - -bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, - uint16_t *size, uint64_t address, void *info) -{ - cs_struct *handle = (cs_struct *)(uintptr_t)ud; - - DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr, - code, code_len, - size, - address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info); - - return status == MCDisassembler_Success; -} - -static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) -{ - const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); - return rc->RegsBegin[RegNo]; -} - -static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *); - // The size of the n field depends on the element size - // The register class also depends on this. - uint32_t tmp = fieldFromInstruction(insn, 17, 5); - unsigned NSize = 0; - DecodeFN RegDecoder = NULL; - - if ((tmp & 0x18) == 0x00) { // INSVE_B - NSize = 4; - RegDecoder = DecodeMSA128BRegisterClass; - } else if ((tmp & 0x1c) == 0x10) { // INSVE_H - NSize = 3; - RegDecoder = DecodeMSA128HRegisterClass; - } else if ((tmp & 0x1e) == 0x18) { // INSVE_W - NSize = 2; - RegDecoder = DecodeMSA128WRegisterClass; - } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D - NSize = 1; - RegDecoder = DecodeMSA128DRegisterClass; - } //else llvm_unreachable("Invalid encoding"); - - //assert(NSize != 0 && RegDecoder != nullptr); - if (NSize == 0 || RegDecoder == NULL) - return MCDisassembler_Fail; - - // $wd - tmp = fieldFromInstruction(insn, 6, 5); - if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) - return MCDisassembler_Fail; - - // $wd_in - if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) - return MCDisassembler_Fail; - - // $n - tmp = fieldFromInstruction(insn, 16, NSize); - MCOperand_CreateImm0(MI, tmp); - - // $ws - tmp = fieldFromInstruction(insn, 11, 5); - if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) - return MCDisassembler_Fail; - - // $n2 - MCOperand_CreateImm0(MI, 0); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the ADDI instruction from the earlier - // ISA's instead). - // - // We have: - // 0b001000 sssss ttttt iiiiiiiiiiiiiiii - // BOVC if rs >= rt - // BEQZALC if rs == 0 && rt != 0 - // BEQC if rs < rt && rs != 0 - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - - if (Rs >= Rt) { - MCInst_setOpcode(MI, Mips_BOVC); - HasRs = true; - } else if (Rs != 0 && Rs < Rt) { - MCInst_setOpcode(MI, Mips_BEQC); - HasRs = true; - } else - MCInst_setOpcode(MI, Mips_BEQZALC); - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the ADDI instruction from the earlier - // ISA's instead). - // - // We have: - // 0b011000 sssss ttttt iiiiiiiiiiiiiiii - // BNVC if rs >= rt - // BNEZALC if rs == 0 && rt != 0 - // BNEC if rs < rt && rs != 0 - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - - if (Rs >= Rt) { - MCInst_setOpcode(MI, Mips_BNVC); - HasRs = true; - } else if (Rs != 0 && Rs < Rt) { - MCInst_setOpcode(MI, Mips_BNEC); - HasRs = true; - } else - MCInst_setOpcode(MI, Mips_BNEZALC); - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the BLEZL instruction from the earlier - // ISA's instead). - // - // We have: - // 0b010110 sssss ttttt iiiiiiiiiiiiiiii - // Invalid if rs == 0 - // BLEZC if rs == 0 && rt != 0 - // BGEZC if rs == rt && rt != 0 - // BGEC if rs != rt && rs != 0 && rt != 0 - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - - if (Rt == 0) - return MCDisassembler_Fail; - else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BLEZC); - else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BGEZC); - else { - HasRs = true; - MCInst_setOpcode(MI, Mips_BGEC); - } - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the BGTZL instruction from the earlier - // ISA's instead). - // - // We have: - // 0b010111 sssss ttttt iiiiiiiiiiiiiiii - // Invalid if rs == 0 - // BGTZC if rs == 0 && rt != 0 - // BLTZC if rs == rt && rt != 0 - // BLTC if rs != rt && rs != 0 && rt != 0 - - bool HasRs = false; - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - - if (Rt == 0) - return MCDisassembler_Fail; - else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BGTZC); - else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BLTZC); - else { - MCInst_setOpcode(MI, Mips_BLTC); - HasRs = true; - } - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the BGTZ instruction from the earlier - // ISA's instead). - // - // We have: - // 0b000111 sssss ttttt iiiiiiiiiiiiiiii - // BGTZ if rt == 0 - // BGTZALC if rs == 0 && rt != 0 - // BLTZALC if rs != 0 && rs == rt - // BLTUC if rs != 0 && rs != rt - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - bool HasRt = false; - - if (Rt == 0) { - MCInst_setOpcode(MI, Mips_BGTZ); - HasRs = true; - } else if (Rs == 0) { - MCInst_setOpcode(MI, Mips_BGTZALC); - HasRt = true; - } else if (Rs == Rt) { - MCInst_setOpcode(MI, Mips_BLTZALC); - HasRs = true; - } else { - MCInst_setOpcode(MI, Mips_BLTUC); - HasRs = true; - HasRt = true; - } - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - if (HasRt) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled - // (otherwise we would have matched the BLEZL instruction from the earlier - // ISA's instead). - // - // We have: - // 0b000110 sssss ttttt iiiiiiiiiiiiiiii - // Invalid if rs == 0 - // BLEZALC if rs == 0 && rt != 0 - // BGEZALC if rs == rt && rt != 0 - // BGEUC if rs != rt && rs != 0 && rt != 0 - - uint32_t Rs = fieldFromInstruction(insn, 21, 5); - uint32_t Rt = fieldFromInstruction(insn, 16, 5); - uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; - bool HasRs = false; - - if (Rt == 0) - return MCDisassembler_Fail; - else if (Rs == 0) - MCInst_setOpcode(MI, Mips_BLEZALC); - else if (Rs == Rt) - MCInst_setOpcode(MI, Mips_BGEZALC); - else { - HasRs = true; - MCInst_setOpcode(MI, Mips_BGEUC); - } - - if (HasRs) - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); - - MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); - - MCOperand_CreateImm0(MI, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - return MCDisassembler_Fail; -} - -static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // if (static_cast(Decoder)->isGP64()) - if (Inst->csh->mode & CS_MODE_MIPS64) - return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); - - return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - int opcode = MCInst_getOpcode(Inst); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - if (opcode == Mips_SC || opcode == Mips_SCD) { - MCOperand_CreateReg0(Inst, Reg); - } - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCacheOp(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCacheOpMM(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xfff, 12); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - unsigned Hint = fieldFromInstruction(Insn, 21, 5); - - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCacheOpR6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = fieldFromInstruction(Insn, 7, 9); - unsigned Hint = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - MCOperand_CreateImm0(Inst, Hint); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSyncI(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); - unsigned Reg = fieldFromInstruction(Insn, 6, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); - - Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - // MCOperand_CreateImm0(Inst, Offset); - - // The immediate field of an LD/ST instruction is scaled which means it must - // be multiplied (when decoding) by the size (in bytes) of the instructions' - // data format. - // .b - 1 byte - // .h - 2 bytes - // .w - 4 bytes - // .d - 8 bytes - switch(MCInst_getOpcode(Inst)) { - default: - //assert (0 && "Unexpected instruction"); - return MCDisassembler_Fail; - break; - case Mips_LD_B: - case Mips_ST_B: - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_LD_H: - case Mips_ST_H: - MCOperand_CreateImm0(Inst, Offset * 2); - break; - case Mips_LD_W: - case Mips_ST_W: - MCOperand_CreateImm0(Inst, Offset * 4); - break; - case Mips_LD_D: - case Mips_ST_D: - MCOperand_CreateImm0(Inst, Offset * 8); - break; - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMImm4(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Offset = Insn & 0xf; - unsigned Reg = fieldFromInstruction(Insn, 7, 3); - unsigned Base = fieldFromInstruction(Insn, 4, 3); - - switch (MCInst_getOpcode(Inst)) { - case Mips_LBU16_MM: - case Mips_LHU16_MM: - case Mips_LW16_MM: - if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - break; - case Mips_SB16_MM: - case Mips_SH16_MM: - case Mips_SW16_MM: - if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - break; - } - - if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - - switch (MCInst_getOpcode(Inst)) { - case Mips_LBU16_MM: - if (Offset == 0xf) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_SB16_MM: - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_LHU16_MM: - case Mips_SH16_MM: - MCOperand_CreateImm0(Inst, Offset << 1); - break; - case Mips_LW16_MM: - case Mips_SW16_MM: - MCOperand_CreateImm0(Inst, Offset << 2); - break; - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Offset = Insn & 0x1F; - unsigned Reg = fieldFromInstruction(Insn, 5, 5); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Mips_SP); - MCOperand_CreateImm0(Inst, Offset << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Offset = Insn & 0x7F; - unsigned Reg = fieldFromInstruction(Insn, 7, 3); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Mips_GP); - MCOperand_CreateImm0(Inst, Offset << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xf, 4); - - if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, Mips_SP); - MCOperand_CreateImm0(Inst, Offset * 4); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMImm12(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0x0fff, 12); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - switch (MCInst_getOpcode(Inst)) { - case Mips_SWM32_MM: - case Mips_LWM32_MM: - if (DecodeRegListOperand(Inst, Insn, Address, Decoder) - == MCDisassembler_Fail) - return MCDisassembler_Fail; - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - break; - case Mips_SC_MM: - MCOperand_CreateReg0(Inst, Reg); - // fallthrough - default: - MCOperand_CreateReg0(Inst, Reg); - if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM) - MCOperand_CreateReg0(Inst, Reg + 1); - - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMemMMImm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 21, 5); - unsigned Base = fieldFromInstruction(Insn, 16, 5); - - Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFMem(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFMem2(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFMem3(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0xffff, 16); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, - unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) -{ - int Offset = SignExtend32(Insn & 0x07ff, 11); - unsigned Reg = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 11, 5); - - Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - MCOperand_CreateReg0(Inst, Reg); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9); - unsigned Rt = fieldFromInstruction(Insn, 16, 5); - unsigned Base = fieldFromInstruction(Insn, 21, 5); - - Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); - Base = getReg(Decoder, Mips_GPR32RegClassID, Base); - - if (MCInst_getOpcode(Inst) == Mips_SC_R6 || - MCInst_getOpcode(Inst) == Mips_SCD_R6) { - MCOperand_CreateReg0(Inst, Rt); - } - - MCOperand_CreateReg0(Inst, Rt); - MCOperand_CreateReg0(Inst, Base); - MCOperand_CreateImm0(Inst, Offset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // Currently only hardware register 29 is supported. - if (RegNo != 29) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, Mips_HWR29); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 30 || RegNo % 2) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo >= 4) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo >= 4) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo >= 4) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 7) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4; - MCOperand_CreateImm0(Inst, TargetAddress); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeJumpTarget(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF); - MCOperand_CreateImm0(Inst, TargetAddress); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget21(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 21) * 4; - - MCOperand_CreateImm0(Inst, BranchOffset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget26(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 26) * 4; - - MCOperand_CreateImm0(Inst, BranchOffset); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 7) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, - unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 10) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, - unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int32_t BranchOffset = SignExtend32(Offset, 16) * 2; - MCOperand_CreateImm0(Inst, BranchOffset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; - MCOperand_CreateImm0(Inst, JumpOffset); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - if (Value == 0) - MCOperand_CreateImm0(Inst, 1); - else if (Value == 0x7) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Value << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, Value << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeLiSimm7(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - if (Value == 0x7F) - MCOperand_CreateImm0(Inst, -1); - else - MCOperand_CreateImm0(Inst, Value); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm4(MCInst *Inst, - unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Value, 4)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm16(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeLSAImm(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // We add one to the immediate field as it was encoded as 'imm - 1'. - MCOperand_CreateImm0(Inst, Insn + 1); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeInsSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - // First we need to grab the pos(lsb) from MCInst. - int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2)); - int Size = (int) Insn - Pos + 1; - MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeExtSize(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - int Size = (int)Insn + 1; - - MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, - unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - int32_t DecodedValue; - - switch (Insn) { - case 0: DecodedValue = 256; break; - case 1: DecodedValue = 257; break; - case 510: DecodedValue = -258; break; - case 511: DecodedValue = -257; break; - default: DecodedValue = SignExtend32(Insn, 9); break; - } - MCOperand_CreateImm0(Inst, DecodedValue * 4); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - // Insn must be >= 0, since it is unsigned that condition is always true. - // assert(Insn < 16); - int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, - 255, 32768, 65535}; - - if (Insn >= 16) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, DecodedValues[Insn]); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, Insn << 2); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, - uint64_t Address, const MCRegisterInfo *Decoder) -{ - unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, - Mips_S6, Mips_FP}; - unsigned RegNum; - unsigned int i; - - unsigned RegLst = fieldFromInstruction(Insn, 21, 5); - // Empty register lists are not allowed. - if (RegLst == 0) - return MCDisassembler_Fail; - - RegNum = RegLst & 0xf; - for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++) - MCOperand_CreateReg0(Inst, Regs[i]); - - if (RegLst & 0x10) - MCOperand_CreateReg0(Inst, Mips_RA); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; - unsigned RegLst = fieldFromInstruction(Insn, 4, 2); - unsigned RegNum = RegLst & 0x3; - unsigned int i; - - for (i = 0; i <= RegNum; i++) - MCOperand_CreateReg0(Inst, Regs[i]); - - MCOperand_CreateReg0(Inst, Mips_RA); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - unsigned RegPair = fieldFromInstruction(Insn, 7, 3); - - switch (RegPair) { - default: - return MCDisassembler_Fail; - case 0: - MCOperand_CreateReg0(Inst, Mips_A1); - MCOperand_CreateReg0(Inst, Mips_A2); - break; - case 1: - MCOperand_CreateReg0(Inst, Mips_A1); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - case 2: - MCOperand_CreateReg0(Inst, Mips_A2); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - case 3: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_S5); - break; - case 4: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_S6); - break; - case 5: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A1); - break; - case 6: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A2); - break; - case 7: - MCOperand_CreateReg0(Inst, Mips_A0); - MCOperand_CreateReg0(Inst, Mips_A3); - break; - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, - uint64_t Address, MCRegisterInfo *Decoder) -{ - MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4); - return MCDisassembler_Success; +static void readInstruction32(unsigned char *code, uint32_t *insn, + bool isBigEndian, bool isMicroMips) { + // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) + // always precede the low 16 bits in the instruction stream (that is, they + // are placed at lower addresses in the instruction stream). + // + // microMIPS byte ordering: + // Big-endian: 0 | 1 | 2 | 3 + // Little-endian: 1 | 0 | 3 | 2 + + // We want to read exactly 4 Bytes of data. + if (isBigEndian) { + // Encoded as a big-endian 32-bit word in the stream. + *insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | + ((uint32_t)code[0] << 24); + } else { + if (isMicroMips) { + *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) | + ((uint32_t)code[1] << 24); + } else { + *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | + ((uint32_t)code[3] << 24); + } + } +} + +static DecodeStatus MipsDisassembler_getInstruction( + int mode, MCInst *instr, const uint8_t *code, size_t code_len, + uint16_t *Size, uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) { + uint32_t Insn; + DecodeStatus Result; + + instr->MRI = MRI; + + if (instr->flat_insn->detail) { + memset(instr->flat_insn->detail, 0, + offsetof(cs_detail, mips) + sizeof(cs_mips)); + } + + if (mode & CS_MODE_MICRO) { + if (code_len < 2) + // not enough data + return MCDisassembler_Fail; + + readInstruction16((unsigned char *)code, &Insn, isBigEndian); + + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, + MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + + if (code_len < 4) + // not enough data + return MCDisassembler_Fail; + + readInstruction32((unsigned char *)code, &Insn, isBigEndian, true); + + // DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, + MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + return MCDisassembler_Fail; + } + + if (code_len < 4) + // not enough data + return MCDisassembler_Fail; + + readInstruction32((unsigned char *)code, &Insn, isBigEndian, false); + + if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) { + // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); + debugln("entering mips cop3"); + Result = + decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) { + // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit + // opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, + Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + if (mode & CS_MODE_MIPS32R6) { + fflush(stdout); + // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, + Address, MRI, mode); + fflush(stdout); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + if (mode & CS_MODE_MIPS64) { + // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, MRI, + mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + } + + // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); + // Calling the auto-generated decoder function. + Result = + decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 4; + return Result; + } + + return MCDisassembler_Fail; +} + +bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info) { + cs_struct *handle = (cs_struct *)(uintptr_t)ud; + + DecodeStatus status = MipsDisassembler_getInstruction( + handle->mode, instr, code, code_len, size, address, + MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info); + + return status == MCDisassembler_Success; +} + +static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) { + const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); + return rc->RegsBegin[RegNo]; } #endif diff --git a/arch/Mips/MipsDisassembler.h b/arch/Mips/MipsDisassembler.h index 961c5f1ae8..0bc3a6264d 100644 --- a/arch/Mips/MipsDisassembler.h +++ b/arch/Mips/MipsDisassembler.h @@ -4,13 +4,14 @@ #ifndef CS_MIPSDISASSEMBLER_H #define CS_MIPSDISASSEMBLER_H -#include "capstone/capstone.h" #include "../../MCInst.h" #include "../../MCRegisterInfo.h" +#include "capstone/capstone.h" void Mips_init(MCRegisterInfo *MRI); bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); + MCInst *instr, uint16_t *size, uint64_t address, + void *info); #endif diff --git a/arch/Mips/MipsGenAsmWriter.inc b/arch/Mips/MipsGenAsmWriter.inc index cd252131f9..a51b9f3c9a 100644 --- a/arch/Mips/MipsGenAsmWriter.inc +++ b/arch/Mips/MipsGenAsmWriter.inc @@ -11,4683 +11,13074 @@ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) -{ - static const uint32_t OpInfo[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 9396U, // DBG_VALUE - 0U, // REG_SEQUENCE - 0U, // COPY - 9389U, // BUNDLE - 9406U, // LIFETIME_START - 9376U, // LIFETIME_END - 0U, // STACKMAP - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 21660U, // ABSQ_S_PH - 18025U, // ABSQ_S_QB - 24850U, // ABSQ_S_W - 134237992U, // ADD - 18294U, // ADDIUPC - 18294U, // ADDIUPC_MM - 22527U, // ADDIUR1SP_MM - 134234410U, // ADDIUR2_MM - 8683851U, // ADDIUS5_MM - 546875U, // ADDIUSP_MM - 134239193U, // ADDQH_PH - 134239310U, // ADDQH_R_PH - 134242253U, // ADDQH_R_W - 134241856U, // ADDQH_W - 134239267U, // ADDQ_PH - 134239366U, // ADDQ_S_PH - 134242558U, // ADDQ_S_W - 134236055U, // ADDSC - 134234730U, // ADDS_A_B - 134236180U, // ADDS_A_D - 134238138U, // ADDS_A_H - 134241564U, // ADDS_A_W - 134235198U, // ADDS_S_B - 134237269U, // ADDS_S_D - 134238695U, // ADDS_S_H - 134242608U, // ADDS_S_W - 134235413U, // ADDS_U_B - 134237736U, // ADDS_U_D - 134238973U, // ADDS_U_H - 134243026U, // ADDS_U_W - 134234575U, // ADDU16_MM - 134235621U, // ADDUH_QB - 134235729U, // ADDUH_R_QB - 134239465U, // ADDU_PH - 134235834U, // ADDU_QB - 134239410U, // ADDU_S_PH - 134235775U, // ADDU_S_QB - 2281718627U, // ADDVI_B - 2281720348U, // ADDVI_D - 2281722002U, // ADDVI_H - 2281725637U, // ADDVI_W - 134235491U, // ADDV_B - 134237836U, // ADDV_D - 134239051U, // ADDV_H - 134243126U, // ADDV_W - 134236094U, // ADDWC - 134234712U, // ADD_A_B - 134236161U, // ADD_A_D - 134238120U, // ADD_A_H - 134241545U, // ADD_A_W - 134237992U, // ADD_MM - 134239685U, // ADDi - 134239685U, // ADDi_MM - 134241307U, // ADDiu - 134241307U, // ADDiu_MM - 134241261U, // ADDu - 134241261U, // ADDu_MM - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 134240158U, // ALIGN - 18286U, // ALUIPC - 134238014U, // AND - 835930U, // AND16_MM - 134238014U, // AND64 - 134234471U, // ANDI16_MM - 2281718486U, // ANDI_B - 134238014U, // AND_MM - 134241389U, // AND_V - 0U, // AND_V_D_PSEUDO - 0U, // AND_V_H_PSEUDO - 0U, // AND_V_W_PSEUDO - 134239691U, // ANDi - 134239691U, // ANDi64 - 134239691U, // ANDi_MM - 134238028U, // APPEND - 134235092U, // ASUB_S_B - 134237099U, // ASUB_S_D - 134238527U, // ASUB_S_H - 134242388U, // ASUB_S_W - 134235307U, // ASUB_U_B - 134237566U, // ASUB_U_D - 134238815U, // ASUB_U_H - 134242856U, // ASUB_U_W - 0U, // ATOMIC_CMP_SWAP_I16 - 0U, // ATOMIC_CMP_SWAP_I32 - 0U, // ATOMIC_CMP_SWAP_I64 - 0U, // ATOMIC_CMP_SWAP_I8 - 0U, // ATOMIC_LOAD_ADD_I16 - 0U, // ATOMIC_LOAD_ADD_I32 - 0U, // ATOMIC_LOAD_ADD_I64 - 0U, // ATOMIC_LOAD_ADD_I8 - 0U, // ATOMIC_LOAD_AND_I16 - 0U, // ATOMIC_LOAD_AND_I32 - 0U, // ATOMIC_LOAD_AND_I64 - 0U, // ATOMIC_LOAD_AND_I8 - 0U, // ATOMIC_LOAD_NAND_I16 - 0U, // ATOMIC_LOAD_NAND_I32 - 0U, // ATOMIC_LOAD_NAND_I64 - 0U, // ATOMIC_LOAD_NAND_I8 - 0U, // ATOMIC_LOAD_OR_I16 - 0U, // ATOMIC_LOAD_OR_I32 - 0U, // ATOMIC_LOAD_OR_I64 - 0U, // ATOMIC_LOAD_OR_I8 - 0U, // ATOMIC_LOAD_SUB_I16 - 0U, // ATOMIC_LOAD_SUB_I32 - 0U, // ATOMIC_LOAD_SUB_I64 - 0U, // ATOMIC_LOAD_SUB_I8 - 0U, // ATOMIC_LOAD_XOR_I16 - 0U, // ATOMIC_LOAD_XOR_I32 - 0U, // ATOMIC_LOAD_XOR_I64 - 0U, // ATOMIC_LOAD_XOR_I8 - 0U, // ATOMIC_SWAP_I16 - 0U, // ATOMIC_SWAP_I32 - 0U, // ATOMIC_SWAP_I64 - 0U, // ATOMIC_SWAP_I8 - 134239795U, // AUI - 18279U, // AUIPC - 134235178U, // AVER_S_B - 134237249U, // AVER_S_D - 134238665U, // AVER_S_H - 134242588U, // AVER_S_W - 134235393U, // AVER_U_B - 134237716U, // AVER_U_D - 134238953U, // AVER_U_H - 134243006U, // AVER_U_W - 134235120U, // AVE_S_B - 134237181U, // AVE_S_D - 134238597U, // AVE_S_H - 134242470U, // AVE_S_W - 134235335U, // AVE_U_B - 134237648U, // AVE_U_D - 134238885U, // AVE_U_H - 134242938U, // AVE_U_W - 23579U, // AddiuRxImmX16 - 1072155U, // AddiuRxPcImmX16 - 285236251U, // AddiuRxRxImm16 - 16800795U, // AddiuRxRxImmX16 - 25189403U, // AddiuRxRyOffMemX16 - 1336343U, // AddiuSpImm16 - 549911U, // AddiuSpImmX16 - 134241261U, // AdduRxRyRz16 - 16797502U, // AndRxRxRy16 - 0U, // B - 541013U, // B16_MM - 134241260U, // BADDu - 546393U, // BAL - 542494U, // BALC - 134240157U, // BALIGN - 0U, // BAL_BR - 167788585U, // BBIT0 - 167788717U, // BBIT032 - 167788710U, // BBIT1 - 167788726U, // BBIT132 - 542473U, // BC - 20351U, // BC0F - 22218U, // BC0FL - 23455U, // BC0T - 22347U, // BC0TL - 25733U, // BC1EQZ - 20357U, // BC1F - 22225U, // BC1FL - 20357U, // BC1F_MM - 25717U, // BC1NEZ - 23461U, // BC1T - 22354U, // BC1TL - 23461U, // BC1T_MM - 25741U, // BC2EQZ - 20363U, // BC2F - 22232U, // BC2FL - 25725U, // BC2NEZ - 23467U, // BC2T - 22361U, // BC2TL - 20369U, // BC3F - 22239U, // BC3FL - 23473U, // BC3T - 22368U, // BC3TL - 2281718555U, // BCLRI_B - 2281720292U, // BCLRI_D - 2281721946U, // BCLRI_H - 2281725581U, // BCLRI_W - 134235059U, // BCLR_B - 134237023U, // BCLR_D - 134238494U, // BCLR_H - 134242304U, // BCLR_W - 134240340U, // BEQ - 134240340U, // BEQ64 - 134236044U, // BEQC - 134240063U, // BEQL - 16882U, // BEQZ16_MM - 18246U, // BEQZALC - 18394U, // BEQZC - 18394U, // BEQZC_MM - 134240340U, // BEQ_MM - 134235917U, // BGEC - 134236068U, // BGEUC - 25500U, // BGEZ - 25500U, // BGEZ64 - 22115U, // BGEZAL - 18219U, // BGEZALC - 22311U, // BGEZALL - 23424U, // BGEZALS_MM - 22115U, // BGEZAL_MM - 18373U, // BGEZC - 22391U, // BGEZL - 25500U, // BGEZ_MM - 25560U, // BGTZ - 25560U, // BGTZ64 - 18255U, // BGTZALC - 18401U, // BGTZC - 22405U, // BGTZL - 25560U, // BGTZ_MM - 2298495744U, // BINSLI_B - 2298497481U, // BINSLI_D - 2298499135U, // BINSLI_H - 2298502770U, // BINSLI_W - 151012243U, // BINSL_B - 151014033U, // BINSL_D - 151015601U, // BINSL_H - 151019280U, // BINSL_W - 2298495805U, // BINSRI_B - 2298497526U, // BINSRI_D - 2298499180U, // BINSRI_H - 2298502815U, // BINSRI_W - 151012291U, // BINSR_B - 151014289U, // BINSR_D - 151015726U, // BINSR_H - 151019570U, // BINSR_W - 23733U, // BITREV - 22477U, // BITSWAP - 25506U, // BLEZ - 25506U, // BLEZ64 - 18228U, // BLEZALC - 18380U, // BLEZC - 22398U, // BLEZL - 25506U, // BLEZ_MM - 134236062U, // BLTC - 134236075U, // BLTUC - 25566U, // BLTZ - 25566U, // BLTZ64 - 22123U, // BLTZAL - 18264U, // BLTZALC - 22320U, // BLTZALL - 23433U, // BLTZALS_MM - 22123U, // BLTZAL_MM - 18408U, // BLTZC - 22412U, // BLTZL - 25566U, // BLTZ_MM - 2298495860U, // BMNZI_B - 151018662U, // BMNZ_V - 2298495852U, // BMZI_B - 151018648U, // BMZ_V - 134238058U, // BNE - 134238058U, // BNE64 - 134235923U, // BNEC - 2281718494U, // BNEGI_B - 2281720240U, // BNEGI_D - 2281721894U, // BNEGI_H - 2281725529U, // BNEGI_W - 134234814U, // BNEG_B - 134236568U, // BNEG_D - 134238222U, // BNEG_H - 134241776U, // BNEG_W - 134239940U, // BNEL - 16874U, // BNEZ16_MM - 18237U, // BNEZALC - 18387U, // BNEZC - 18387U, // BNEZC_MM - 134238058U, // BNE_MM - 134236082U, // BNVC - 17803U, // BNZ_B - 20233U, // BNZ_D - 21363U, // BNZ_H - 23711U, // BNZ_V - 25463U, // BNZ_W - 134236088U, // BOVC - 540871U, // BPOSGE32 - 0U, // BPOSGE32_PSEUDO - 22080U, // BREAK - 65909U, // BREAK16_MM - 22080U, // BREAK_MM - 2298495719U, // BSELI_B - 0U, // BSEL_D_PSEUDO - 0U, // BSEL_FD_PSEUDO - 0U, // BSEL_FW_PSEUDO - 0U, // BSEL_H_PSEUDO - 151018620U, // BSEL_V - 0U, // BSEL_W_PSEUDO - 2281718609U, // BSETI_B - 2281720330U, // BSETI_D - 2281721984U, // BSETI_H - 2281725619U, // BSETI_W - 134235275U, // BSET_B - 134237385U, // BSET_D - 134238783U, // BSET_H - 134242762U, // BSET_W - 17797U, // BZ_B - 20217U, // BZ_D - 21357U, // BZ_H - 23698U, // BZ_V - 25457U, // BZ_W - 541278U, // B_MM_Pseudo - 402678723U, // BeqzRxImm16 - 25539U, // BeqzRxImmX16 - 1327710U, // Bimm16 - 541278U, // BimmX16 - 402678696U, // BnezRxImm16 - 25512U, // BnezRxImmX16 - 9368U, // Break16 - 1598417U, // Bteqz16 - 536893428U, // BteqzT8CmpX16 - 536892936U, // BteqzT8CmpiX16 - 536894397U, // BteqzT8SltX16 - 536892966U, // BteqzT8SltiX16 - 536894505U, // BteqzT8SltiuX16 - 536894541U, // BteqzT8SltuX16 - 549841U, // BteqzX16 - 1598390U, // Btnez16 - 671111156U, // BtnezT8CmpX16 - 671110664U, // BtnezT8CmpiX16 - 671112125U, // BtnezT8SltX16 - 671110694U, // BtnezT8SltiX16 - 671112233U, // BtnezT8SltiuX16 - 671112269U, // BtnezT8SltuX16 - 549814U, // BtnezX16 - 0U, // BuildPairF64 - 0U, // BuildPairF64_64 - 85859U, // CACHE - 85859U, // CACHE_MM - 85859U, // CACHE_R6 - 19003U, // CEIL_L_D64 - 23031U, // CEIL_L_S - 20179U, // CEIL_W_D32 - 20179U, // CEIL_W_D64 - 20179U, // CEIL_W_MM - 23353U, // CEIL_W_S - 23353U, // CEIL_W_S_MM - 134234890U, // CEQI_B - 134236627U, // CEQI_D - 134238281U, // CEQI_H - 134241916U, // CEQI_W - 134235044U, // CEQ_B - 134236930U, // CEQ_D - 134238472U, // CEQ_H - 134242192U, // CEQ_W - 16444U, // CFC1 - 16444U, // CFC1_MM - 16968U, // CFCMSA - 134243407U, // CINS - 134243363U, // CINS32 - 19639U, // CLASS_D - 23205U, // CLASS_S - 134235129U, // CLEI_S_B - 134237190U, // CLEI_S_D - 134238606U, // CLEI_S_H - 134242479U, // CLEI_S_W - 2281718992U, // CLEI_U_B - 2281721305U, // CLEI_U_D - 2281722542U, // CLEI_U_H - 2281726595U, // CLEI_U_W - 134235111U, // CLE_S_B - 134237172U, // CLE_S_D - 134238588U, // CLE_S_H - 134242461U, // CLE_S_W - 134235326U, // CLE_U_B - 134237639U, // CLE_U_D - 134238876U, // CLE_U_H - 134242929U, // CLE_U_W - 22452U, // CLO - 22452U, // CLO_MM - 22452U, // CLO_R6 - 134235149U, // CLTI_S_B - 134237210U, // CLTI_S_D - 134238626U, // CLTI_S_H - 134242499U, // CLTI_S_W - 2281719012U, // CLTI_U_B - 2281721325U, // CLTI_U_D - 2281722562U, // CLTI_U_H - 2281726615U, // CLTI_U_W - 134235217U, // CLT_S_B - 134237288U, // CLT_S_D - 134238714U, // CLT_S_H - 134242627U, // CLT_S_W - 134235444U, // CLT_U_B - 134237767U, // CLT_U_D - 134239004U, // CLT_U_H - 134243057U, // CLT_U_W - 25534U, // CLZ - 25534U, // CLZ_MM - 25534U, // CLZ_R6 - 134235667U, // CMPGDU_EQ_QB - 134235572U, // CMPGDU_LE_QB - 134235786U, // CMPGDU_LT_QB - 134235681U, // CMPGU_EQ_QB - 134235586U, // CMPGU_LE_QB - 134235800U, // CMPGU_LT_QB - 17966U, // CMPU_EQ_QB - 17871U, // CMPU_LE_QB - 18085U, // CMPU_LT_QB - 134236919U, // CMP_EQ_D - 21548U, // CMP_EQ_PH - 134240864U, // CMP_EQ_S - 134236489U, // CMP_F_D - 134240675U, // CMP_F_S - 134236333U, // CMP_LE_D - 21444U, // CMP_LE_PH - 134240596U, // CMP_LE_S - 134237410U, // CMP_LT_D - 21717U, // CMP_LT_PH - 134240959U, // CMP_LT_S - 134236507U, // CMP_SAF_D - 134240685U, // CMP_SAF_S - 134236946U, // CMP_SEQ_D - 134240883U, // CMP_SEQ_S - 134236370U, // CMP_SLE_D - 134240625U, // CMP_SLE_S - 134237437U, // CMP_SLT_D - 134240978U, // CMP_SLT_S - 134236994U, // CMP_SUEQ_D - 134240914U, // CMP_SUEQ_S - 134236418U, // CMP_SULE_D - 134240656U, // CMP_SULE_S - 134237485U, // CMP_SULT_D - 134241009U, // CMP_SULT_S - 134236876U, // CMP_SUN_D - 134240837U, // CMP_SUN_S - 134236974U, // CMP_UEQ_D - 134240903U, // CMP_UEQ_S - 134236398U, // CMP_ULE_D - 134240645U, // CMP_ULE_S - 134237465U, // CMP_ULT_D - 134240998U, // CMP_ULT_S - 134236858U, // CMP_UN_D - 134240827U, // CMP_UN_S - 9454U, // CONSTPOOL_ENTRY - 0U, // COPY_FD_PSEUDO - 0U, // COPY_FW_PSEUDO - 2952807544U, // COPY_S_B - 2952809637U, // COPY_S_D - 2952811052U, // COPY_S_H - 2952814987U, // COPY_S_W - 2952807759U, // COPY_U_B - 2952810104U, // COPY_U_D - 2952811319U, // COPY_U_H - 2952815394U, // COPY_U_W - 1867863U, // CTC1 - 1867863U, // CTC1_MM - 16976U, // CTCMSA - 22833U, // CVT_D32_S - 23896U, // CVT_D32_W - 23896U, // CVT_D32_W_MM - 22087U, // CVT_D64_L - 22833U, // CVT_D64_S - 23896U, // CVT_D64_W - 22833U, // CVT_D_S_MM - 19024U, // CVT_L_D64 - 19024U, // CVT_L_D64_MM - 23052U, // CVT_L_S - 23052U, // CVT_L_S_MM - 19362U, // CVT_S_D32 - 19362U, // CVT_S_D32_MM - 19362U, // CVT_S_D64 - 22096U, // CVT_S_L - 24651U, // CVT_S_W - 24651U, // CVT_S_W_MM - 20200U, // CVT_W_D32 - 20200U, // CVT_W_D64 - 20200U, // CVT_W_MM - 23374U, // CVT_W_S - 23374U, // CVT_W_S_MM - 19183U, // C_EQ_D32 - 19183U, // C_EQ_D64 - 23128U, // C_EQ_S - 18754U, // C_F_D32 - 18754U, // C_F_D64 - 22940U, // C_F_S - 18597U, // C_LE_D32 - 18597U, // C_LE_D64 - 22860U, // C_LE_S - 19674U, // C_LT_D32 - 19674U, // C_LT_D64 - 23223U, // C_LT_S - 18588U, // C_NGE_D32 - 18588U, // C_NGE_D64 - 22851U, // C_NGE_S - 18623U, // C_NGLE_D32 - 18623U, // C_NGLE_D64 - 22878U, // C_NGLE_S - 19040U, // C_NGL_D32 - 19040U, // C_NGL_D64 - 23068U, // C_NGL_S - 19665U, // C_NGT_D32 - 19665U, // C_NGT_D64 - 23214U, // C_NGT_S - 18633U, // C_OLE_D32 - 18633U, // C_OLE_D64 - 22888U, // C_OLE_S - 19700U, // C_OLT_D32 - 19700U, // C_OLT_D64 - 23241U, // C_OLT_S - 19209U, // C_SEQ_D32 - 19209U, // C_SEQ_D64 - 23146U, // C_SEQ_S - 18824U, // C_SF_D32 - 18824U, // C_SF_D64 - 22986U, // C_SF_S - 19237U, // C_UEQ_D32 - 19237U, // C_UEQ_D64 - 23166U, // C_UEQ_S - 18661U, // C_ULE_D32 - 18661U, // C_ULE_D64 - 22908U, // C_ULE_S - 19728U, // C_ULT_D32 - 19728U, // C_ULT_D64 - 23261U, // C_ULT_S - 19122U, // C_UN_D32 - 19122U, // C_UN_D64 - 23091U, // C_UN_S - 22516U, // CmpRxRy16 - 939546120U, // CmpiRxImm16 - 22024U, // CmpiRxImmX16 - 549945U, // Constant32 - 134237991U, // DADD - 134239684U, // DADDi - 134241306U, // DADDiu - 134241267U, // DADDu - 8689123U, // DAHI - 134240165U, // DALIGN - 8689184U, // DATI - 134239794U, // DAUI - 22476U, // DBITSWAP - 22451U, // DCLO - 22451U, // DCLO_R6 - 25533U, // DCLZ - 25533U, // DCLZ_R6 - 134241469U, // DDIV - 134241377U, // DDIVU - 9480U, // DERET - 9480U, // DERET_MM - 134243425U, // DEXT - 134243400U, // DEXTM - 134243438U, // DEXTU - 546247U, // DI - 134243413U, // DINS - 134243393U, // DINSM - 134243431U, // DINSU - 134241470U, // DIV - 134241378U, // DIVU - 134235238U, // DIV_S_B - 134237331U, // DIV_S_D - 134238735U, // DIV_S_H - 134242670U, // DIV_S_W - 134235453U, // DIV_U_B - 134237798U, // DIV_U_D - 134239013U, // DIV_U_H - 134243088U, // DIV_U_W - 546247U, // DI_MM - 134234690U, // DLSA - 134234690U, // DLSA_R6 - 134234121U, // DMFC0 - 16450U, // DMFC1 - 134234372U, // DMFC2 - 134238036U, // DMOD - 134241281U, // DMODU - 134234128U, // DMTC0 - 1867869U, // DMTC1 - 134234379U, // DMTC2 - 134239671U, // DMUH - 134241299U, // DMUHU - 134240103U, // DMUL - 23495U, // DMULT - 23641U, // DMULTu - 134241343U, // DMULU - 134240103U, // DMUL_R6 - 134237239U, // DOTP_S_D - 134238655U, // DOTP_S_H - 134242538U, // DOTP_S_W - 134237706U, // DOTP_U_D - 134238943U, // DOTP_U_H - 134242996U, // DOTP_U_W - 151014368U, // DPADD_S_D - 151015784U, // DPADD_S_H - 151019657U, // DPADD_S_W - 151014835U, // DPADD_U_D - 151016072U, // DPADD_U_H - 151020125U, // DPADD_U_W - 134239524U, // DPAQX_SA_W_PH - 134239607U, // DPAQX_S_W_PH - 134241998U, // DPAQ_SA_L_W - 134239566U, // DPAQ_S_W_PH - 134239859U, // DPAU_H_QBL - 134240355U, // DPAU_H_QBR - 134239645U, // DPAX_W_PH - 134239514U, // DPA_W_PH - 22521U, // DPOP - 134239539U, // DPSQX_SA_W_PH - 134239621U, // DPSQX_S_W_PH - 134242011U, // DPSQ_SA_L_W - 134239594U, // DPSQ_S_W_PH - 151014335U, // DPSUB_S_D - 151015763U, // DPSUB_S_H - 151019624U, // DPSUB_S_W - 151014802U, // DPSUB_U_D - 151016051U, // DPSUB_U_H - 151020092U, // DPSUB_U_W - 134239871U, // DPSU_H_QBL - 134240367U, // DPSU_H_QBR - 134239656U, // DPSX_W_PH - 134239635U, // DPS_W_PH - 134240512U, // DROTR - 134234351U, // DROTR32 - 134241513U, // DROTRV - 21370U, // DSBH - 25610U, // DSDIV - 20275U, // DSHD - 134240057U, // DSLL - 134234321U, // DSLL32 - 1073764153U, // DSLL64_32 - 134241475U, // DSLLV - 134234684U, // DSRA - 134234303U, // DSRA32 - 134241454U, // DSRAV - 134240069U, // DSRL - 134234329U, // DSRL32 - 134241482U, // DSRLV - 134235901U, // DSUB - 134241246U, // DSUBu - 25596U, // DUDIV - 25611U, // DivRxRy16 - 25597U, // DivuRxRy16 - 9438U, // EHB - 9438U, // EHB_MM - 546259U, // EI - 546259U, // EI_MM - 9481U, // ERET - 9481U, // ERET_MM - 134243426U, // EXT - 134240324U, // EXTP - 134240221U, // EXTPDP - 134241497U, // EXTPDPV - 134241506U, // EXTPV - 134242731U, // EXTRV_RS_W - 134242285U, // EXTRV_R_W - 134238744U, // EXTRV_S_H - 134243168U, // EXTRV_W - 134242720U, // EXTR_RS_W - 134242264U, // EXTR_R_W - 134238675U, // EXTR_S_H - 134242363U, // EXTR_W - 134243419U, // EXTS - 134243371U, // EXTS32 - 134243426U, // EXT_MM - 0U, // ExtractElementF64 - 0U, // ExtractElementF64_64 - 0U, // FABS_D - 19631U, // FABS_D32 - 19631U, // FABS_D64 - 19631U, // FABS_MM - 23198U, // FABS_S - 23198U, // FABS_S_MM - 0U, // FABS_W - 134236265U, // FADD_D - 134236266U, // FADD_D32 - 134236266U, // FADD_D64 - 134236266U, // FADD_MM - 134240572U, // FADD_S - 134240572U, // FADD_S_MM - 134241633U, // FADD_W - 134236499U, // FCAF_D - 134241752U, // FCAF_W - 134236929U, // FCEQ_D - 134242191U, // FCEQ_W - 19638U, // FCLASS_D - 25015U, // FCLASS_W - 134236343U, // FCLE_D - 134241675U, // FCLE_W - 134237420U, // FCLT_D - 134242770U, // FCLT_W - 2204821U, // FCMP_D32 - 2204821U, // FCMP_D32_MM - 2204821U, // FCMP_D64 - 2466965U, // FCMP_S32 - 2466965U, // FCMP_S32_MM - 134236439U, // FCNE_D - 134241709U, // FCNE_W - 134237039U, // FCOR_D - 134242320U, // FCOR_W - 134236985U, // FCUEQ_D - 134242207U, // FCUEQ_W - 134236409U, // FCULE_D - 134241691U, // FCULE_W - 134237476U, // FCULT_D - 134242786U, // FCULT_W - 134236455U, // FCUNE_D - 134241725U, // FCUNE_W - 134236868U, // FCUN_D - 134242097U, // FCUN_W - 134237862U, // FDIV_D - 134237863U, // FDIV_D32 - 134237863U, // FDIV_D64 - 134237863U, // FDIV_MM - 134241045U, // FDIV_S - 134241045U, // FDIV_S_MM - 134243152U, // FDIV_W - 134238402U, // FEXDO_H - 134242113U, // FEXDO_W - 134236152U, // FEXP2_D - 0U, // FEXP2_D_1_PSEUDO - 134241536U, // FEXP2_W - 0U, // FEXP2_W_1_PSEUDO - 19064U, // FEXUPL_D - 24311U, // FEXUPL_W - 19327U, // FEXUPR_D - 24608U, // FEXUPR_W - 19569U, // FFINT_S_D - 24908U, // FFINT_S_W - 20048U, // FFINT_U_D - 25338U, // FFINT_U_W - 19074U, // FFQL_D - 24321U, // FFQL_W - 19337U, // FFQR_D - 24618U, // FFQR_W - 17277U, // FILL_B - 19049U, // FILL_D - 0U, // FILL_FD_PSEUDO - 0U, // FILL_FW_PSEUDO - 20635U, // FILL_H - 24296U, // FILL_W - 18415U, // FLOG2_D - 23799U, // FLOG2_W - 19013U, // FLOOR_L_D64 - 23041U, // FLOOR_L_S - 20189U, // FLOOR_W_D32 - 20189U, // FLOOR_W_D64 - 20189U, // FLOOR_W_MM - 23363U, // FLOOR_W_S - 23363U, // FLOOR_W_S_MM - 151013489U, // FMADD_D - 151018857U, // FMADD_W - 134236190U, // FMAX_A_D - 134241574U, // FMAX_A_W - 134237937U, // FMAX_D - 134243177U, // FMAX_W - 134236170U, // FMIN_A_D - 134241554U, // FMIN_A_W - 134236842U, // FMIN_D - 134242089U, // FMIN_W - 20150U, // FMOV_D32 - 20150U, // FMOV_D32_MM - 20150U, // FMOV_D64 - 23324U, // FMOV_S - 23324U, // FMOV_S_MM - 151013447U, // FMSUB_D - 151018815U, // FMSUB_W - 134236826U, // FMUL_D - 134236827U, // FMUL_D32 - 134236827U, // FMUL_D64 - 134236827U, // FMUL_MM - 134240805U, // FMUL_S - 134240805U, // FMUL_S_MM - 134242073U, // FMUL_W - 18841U, // FNEG_D32 - 18841U, // FNEG_D64 - 18841U, // FNEG_MM - 23002U, // FNEG_S - 23002U, // FNEG_S_MM - 19175U, // FRCP_D - 24394U, // FRCP_W - 19786U, // FRINT_D - 25084U, // FRINT_W - 19814U, // FRSQRT_D - 25112U, // FRSQRT_W - 134236518U, // FSAF_D - 134241760U, // FSAF_W - 134236957U, // FSEQ_D - 134242199U, // FSEQ_W - 134236381U, // FSLE_D - 134241683U, // FSLE_W - 134237448U, // FSLT_D - 134242778U, // FSLT_W - 134236447U, // FSNE_D - 134241717U, // FSNE_W - 134237047U, // FSOR_D - 134242328U, // FSOR_W - 19805U, // FSQRT_D - 19806U, // FSQRT_D32 - 19806U, // FSQRT_D64 - 19806U, // FSQRT_MM - 23301U, // FSQRT_S - 23301U, // FSQRT_S_MM - 25103U, // FSQRT_W - 134236223U, // FSUB_D - 134236224U, // FSUB_D32 - 134236224U, // FSUB_D64 - 134236224U, // FSUB_MM - 134240554U, // FSUB_S - 134240554U, // FSUB_S_MM - 134241591U, // FSUB_W - 134237006U, // FSUEQ_D - 134242216U, // FSUEQ_W - 134236430U, // FSULE_D - 134241700U, // FSULE_W - 134237497U, // FSULT_D - 134242795U, // FSULT_W - 134236464U, // FSUNE_D - 134241734U, // FSUNE_W - 134236887U, // FSUN_D - 134242105U, // FSUN_W - 19580U, // FTINT_S_D - 24919U, // FTINT_S_W - 20059U, // FTINT_U_D - 25349U, // FTINT_U_W - 134238479U, // FTQ_H - 134242225U, // FTQ_W - 19402U, // FTRUNC_S_D - 24691U, // FTRUNC_S_W - 19869U, // FTRUNC_U_D - 25159U, // FTRUNC_U_W - 1224758783U, // GotPrologue16 - 134237142U, // HADD_S_D - 134238558U, // HADD_S_H - 134242431U, // HADD_S_W - 134237609U, // HADD_U_D - 134238846U, // HADD_U_H - 134242899U, // HADD_U_W - 134237109U, // HSUB_S_D - 134238537U, // HSUB_S_H - 134242398U, // HSUB_S_W - 134237576U, // HSUB_U_D - 134238825U, // HSUB_U_H - 134242866U, // HSUB_U_W - 134235508U, // ILVEV_B - 134237853U, // ILVEV_D - 134239068U, // ILVEV_H - 134243143U, // ILVEV_W - 134235036U, // ILVL_B - 134236834U, // ILVL_D - 134238394U, // ILVL_H - 134242081U, // ILVL_W - 134234788U, // ILVOD_B - 134236307U, // ILVOD_D - 134238196U, // ILVOD_H - 134241666U, // ILVOD_W - 134235084U, // ILVR_B - 134237082U, // ILVR_D - 134238519U, // ILVR_H - 134242371U, // ILVR_W - 134243408U, // INS - 44582043U, // INSERT_B - 0U, // INSERT_B_VIDX_PSEUDO - 44584275U, // INSERT_D - 0U, // INSERT_D_VIDX_PSEUDO - 0U, // INSERT_FD_PSEUDO - 0U, // INSERT_FD_VIDX_PSEUDO - 0U, // INSERT_FW_PSEUDO - 0U, // INSERT_FW_VIDX_PSEUDO - 44585551U, // INSERT_H - 0U, // INSERT_H_VIDX_PSEUDO - 44589573U, // INSERT_W - 0U, // INSERT_W_VIDX_PSEUDO - 16801009U, // INSV - 52970157U, // INSVE_B - 52971833U, // INSVE_D - 52973565U, // INSVE_H - 52977103U, // INSVE_W - 134243408U, // INS_MM - 546365U, // J - 546398U, // JAL - 22768U, // JALR - 547056U, // JALR16_MM - 22768U, // JALR64 - 0U, // JALR64Pseudo - 0U, // JALRPseudo - 541104U, // JALRS16_MM - 23442U, // JALRS_MM - 17822U, // JALR_HB - 22768U, // JALR_MM - 547706U, // JALS_MM - 549771U, // JALX - 549771U, // JALX_MM - 546398U, // JAL_MM - 18212U, // JIALC - 18201U, // JIC - 547052U, // JR - 541091U, // JR16_MM - 547052U, // JR64 - 546873U, // JRADDIUSP - 542610U, // JRC16_MM - 542103U, // JR_HB - 542103U, // JR_HB_R6 - 547052U, // JR_MM - 546365U, // J_MM - 2905694U, // Jal16 - 3167838U, // JalB16 - 546398U, // JalOneReg - 22110U, // JalTwoReg - 9430U, // JrRa16 - 9421U, // JrcRa16 - 549872U, // JrcRx16 - 540673U, // JumpLinkReg16 - 58738087U, // LB - 58738087U, // LB64 - 58737088U, // LBU16_MM - 1358979985U, // LBUX - 58738087U, // LB_MM - 58743769U, // LBu - 58743769U, // LBu64 - 58743769U, // LBu_MM - 58740538U, // LD - 58736688U, // LDC1 - 58736688U, // LDC164 - 58736688U, // LDC1_MM - 58736888U, // LDC2 - 58736888U, // LDC2_R6 - 58736947U, // LDC3 - 17103U, // LDI_B - 18857U, // LDI_D - 20511U, // LDI_H - 24146U, // LDI_W - 58742458U, // LDL - 18273U, // LDPC - 58742954U, // LDR - 1358970992U, // LDXC1 - 1358970992U, // LDXC164 - 58737301U, // LD_B - 58738820U, // LD_D - 58740709U, // LD_H - 58744179U, // LD_W - 25189403U, // LEA_ADDiu - 25189402U, // LEA_ADDiu64 - 25189403U, // LEA_ADDiu_MM - 58741643U, // LH - 58741643U, // LH64 - 58737111U, // LHU16_MM - 1358979974U, // LHX - 58741643U, // LH_MM - 58743822U, // LHu - 58743822U, // LHu64 - 58743822U, // LHu_MM - 16751U, // LI16_MM - 58742563U, // LL - 58740537U, // LLD - 58740537U, // LLD_R6 - 58742563U, // LL_MM - 58742563U, // LL_R6 - 58736647U, // LOAD_ACC128 - 58736647U, // LOAD_ACC64 - 58736647U, // LOAD_ACC64DSP - 58742794U, // LOAD_CCOND_DSP - 0U, // LONG_BRANCH_ADDiu - 0U, // LONG_BRANCH_DADDiu - 0U, // LONG_BRANCH_LUi - 134234691U, // LSA - 134234691U, // LSA_R6 - 1358971006U, // LUXC1 - 1358971006U, // LUXC164 - 1358971006U, // LUXC1_MM - 33576504U, // LUi - 33576504U, // LUi64 - 33576504U, // LUi_MM - 58745726U, // LW - 58737118U, // LW16_MM - 58745726U, // LW64 - 58736740U, // LWC1 - 58736740U, // LWC1_MM - 58736914U, // LWC2 - 58736914U, // LWC2_R6 - 58736959U, // LWC3 - 58745726U, // LWGP_MM - 58742637U, // LWL - 58742637U, // LWL64 - 58742637U, // LWL_MM - 3522956U, // LWM16_MM - 3522785U, // LWM32_MM - 3528595U, // LWM_MM - 18310U, // LWPC - 137290U, // LWP_MM - 58743054U, // LWR - 58743054U, // LWR64 - 58743054U, // LWR_MM - 58745726U, // LWSP_MM - 18303U, // LWUPC - 58743912U, // LWU_MM - 1358979991U, // LWX - 1358971020U, // LWXC1 - 1358971020U, // LWXC1_MM - 1358977945U, // LWXS_MM - 58745726U, // LW_MM - 58743912U, // LWu - 58738087U, // LbRxRyOffMemX16 - 58743769U, // LbuRxRyOffMemX16 - 58741643U, // LhRxRyOffMemX16 - 58743822U, // LhuRxRyOffMemX16 - 939546111U, // LiRxImm16 - 22005U, // LiRxImmAlignX16 - 22015U, // LiRxImmX16 - 33571334U, // LoadAddr32Imm - 58737158U, // LoadAddr32Reg - 33576447U, // LoadImm32Reg - 22019U, // LoadImm64Reg - 3695486U, // LwConstant32 - 268460926U, // LwRxPcTcp16 - 25470U, // LwRxPcTcpX16 - 58745726U, // LwRxRyOffMemX16 - 1493197694U, // LwRxSpImmX16 - 20269U, // MADD - 151013751U, // MADDF_D - 151017921U, // MADDF_S - 151015667U, // MADDR_Q_H - 151019386U, // MADDR_Q_W - 23546U, // MADDU - 134241274U, // MADDU_DSP - 23546U, // MADDU_MM - 151012706U, // MADDV_B - 151015051U, // MADDV_D - 151016266U, // MADDV_H - 151020341U, // MADDV_W - 134236274U, // MADD_D32 - 134236274U, // MADD_D32_MM - 134236274U, // MADD_D64 - 134237997U, // MADD_DSP - 20269U, // MADD_MM - 151015637U, // MADD_Q_H - 151019356U, // MADD_Q_W - 134240571U, // MADD_S - 134240571U, // MADD_S_MM - 134239974U, // MAQ_SA_W_PHL - 134240436U, // MAQ_SA_W_PHR - 134240002U, // MAQ_S_W_PHL - 134240464U, // MAQ_S_W_PHR - 134236215U, // MAXA_D - 134240544U, // MAXA_S - 134235159U, // MAXI_S_B - 134237220U, // MAXI_S_D - 134238636U, // MAXI_S_H - 134242509U, // MAXI_S_W - 2281719022U, // MAXI_U_B - 2281721335U, // MAXI_U_D - 2281722572U, // MAXI_U_H - 2281726625U, // MAXI_U_W - 134234740U, // MAX_A_B - 134236191U, // MAX_A_D - 134238148U, // MAX_A_H - 134241575U, // MAX_A_W - 134237938U, // MAX_D - 134241111U, // MAX_S - 134235247U, // MAX_S_B - 134237340U, // MAX_S_D - 134238755U, // MAX_S_H - 134242690U, // MAX_S_W - 134235462U, // MAX_U_B - 134237807U, // MAX_U_D - 134239022U, // MAX_U_H - 134243097U, // MAX_U_W - 134234122U, // MFC0 - 16451U, // MFC1 - 16451U, // MFC1_MM - 134234373U, // MFC2 - 16457U, // MFHC1_D32 - 16457U, // MFHC1_D64 - 16457U, // MFHC1_MM - 546281U, // MFHI - 546281U, // MFHI16_MM - 546281U, // MFHI64 - 21993U, // MFHI_DSP - 546281U, // MFHI_MM - 546745U, // MFLO - 546745U, // MFLO16_MM - 546745U, // MFLO64 - 22457U, // MFLO_DSP - 546745U, // MFLO_MM - 134236200U, // MINA_D - 134240536U, // MINA_S - 134235139U, // MINI_S_B - 134237200U, // MINI_S_D - 134238616U, // MINI_S_H - 134242489U, // MINI_S_W - 2281719002U, // MINI_U_B - 2281721315U, // MINI_U_D - 2281722552U, // MINI_U_H - 2281726605U, // MINI_U_W - 134234721U, // MIN_A_B - 134236171U, // MIN_A_D - 134238129U, // MIN_A_H - 134241555U, // MIN_A_W - 134236843U, // MIN_D - 134240812U, // MIN_S - 134235169U, // MIN_S_B - 134237230U, // MIN_S_D - 134238646U, // MIN_S_H - 134242529U, // MIN_S_W - 134235384U, // MIN_U_B - 134237697U, // MIN_U_D - 134238934U, // MIN_U_H - 134242987U, // MIN_U_W - 0U, // MIPSeh_return32 - 0U, // MIPSeh_return64 - 134238037U, // MOD - 134235899U, // MODSUB - 134241282U, // MODU - 134235102U, // MOD_S_B - 134237163U, // MOD_S_D - 134238579U, // MOD_S_H - 134242452U, // MOD_S_W - 134235317U, // MOD_U_B - 134237630U, // MOD_U_D - 134238867U, // MOD_U_H - 134242920U, // MOD_U_W - 20345U, // MOVE16_MM - 67491813U, // MOVEP_MM - 23668U, // MOVE_V - 134236560U, // MOVF_D32 - 134236560U, // MOVF_D32_MM - 134236560U, // MOVF_D64 - 134238109U, // MOVF_I - 134238109U, // MOVF_I64 - 134238109U, // MOVF_I_MM - 134240722U, // MOVF_S - 134240722U, // MOVF_S_MM - 134236895U, // MOVN_I64_D64 - 134240173U, // MOVN_I64_I - 134240173U, // MOVN_I64_I64 - 134240848U, // MOVN_I64_S - 134236895U, // MOVN_I_D32 - 134236895U, // MOVN_I_D32_MM - 134236895U, // MOVN_I_D64 - 134240173U, // MOVN_I_I - 134240173U, // MOVN_I_I64 - 134240173U, // MOVN_I_MM - 134240848U, // MOVN_I_S - 134240848U, // MOVN_I_S_MM - 134237558U, // MOVT_D32 - 134237558U, // MOVT_D32_MM - 134237558U, // MOVT_D64 - 134241235U, // MOVT_I - 134241235U, // MOVT_I64 - 134241235U, // MOVT_I_MM - 134241037U, // MOVT_S - 134241037U, // MOVT_S_MM - 134237978U, // MOVZ_I64_D64 - 134243300U, // MOVZ_I64_I - 134243300U, // MOVZ_I64_I64 - 134241138U, // MOVZ_I64_S - 134237978U, // MOVZ_I_D32 - 134237978U, // MOVZ_I_D32_MM - 134237978U, // MOVZ_I_D64 - 134243300U, // MOVZ_I_I - 134243300U, // MOVZ_I_I64 - 134243300U, // MOVZ_I_MM - 134241138U, // MOVZ_I_S - 134241138U, // MOVZ_I_S_MM - 18179U, // MSUB - 151013742U, // MSUBF_D - 151017912U, // MSUBF_S - 151015656U, // MSUBR_Q_H - 151019375U, // MSUBR_Q_W - 23525U, // MSUBU - 134241253U, // MSUBU_DSP - 23525U, // MSUBU_MM - 151012697U, // MSUBV_B - 151015042U, // MSUBV_D - 151016257U, // MSUBV_H - 151020332U, // MSUBV_W - 134236232U, // MSUB_D32 - 134236232U, // MSUB_D32_MM - 134236232U, // MSUB_D64 - 134235907U, // MSUB_DSP - 18179U, // MSUB_MM - 151015627U, // MSUB_Q_H - 151019346U, // MSUB_Q_W - 134240553U, // MSUB_S - 134240553U, // MSUB_S_MM - 134234129U, // MTC0 - 1867870U, // MTC1 - 1867870U, // MTC1_MM - 134234380U, // MTC2 - 1884240U, // MTHC1_D32 - 1884240U, // MTHC1_D64 - 1884240U, // MTHC1_MM - 546287U, // MTHI - 546287U, // MTHI64 - 1873391U, // MTHI_DSP - 546287U, // MTHI_MM - 1873900U, // MTHLIP - 546758U, // MTLO - 546758U, // MTLO64 - 1873862U, // MTLO_DSP - 546758U, // MTLO_MM - 540701U, // MTM0 - 540826U, // MTM1 - 540958U, // MTM2 - 540707U, // MTP0 - 540832U, // MTP1 - 540964U, // MTP2 - 134239672U, // MUH - 134241300U, // MUHU - 134240104U, // MUL - 134240015U, // MULEQ_S_W_PHL - 134240477U, // MULEQ_S_W_PHR - 134239883U, // MULEU_S_PH_QBL - 134240379U, // MULEU_S_PH_QBR - 134239433U, // MULQ_RS_PH - 134242709U, // MULQ_RS_W - 134239377U, // MULQ_S_PH - 134242568U, // MULQ_S_W - 134238462U, // MULR_Q_H - 134242181U, // MULR_Q_W - 134239579U, // MULSAQ_S_W_PH - 134239554U, // MULSA_W_PH - 23496U, // MULT - 134241370U, // MULTU_DSP - 134241224U, // MULT_DSP - 23496U, // MULT_MM - 23642U, // MULTu - 23642U, // MULTu_MM - 134241337U, // MULU - 134235517U, // MULV_B - 134237870U, // MULV_D - 134239077U, // MULV_H - 134243160U, // MULV_W - 134240104U, // MUL_MM - 134239250U, // MUL_PH - 134238431U, // MUL_Q_H - 134242150U, // MUL_Q_W - 134240104U, // MUL_R6 - 134239345U, // MUL_S_PH - 546281U, // Mfhi16 - 546745U, // Mflo16 - 20345U, // Move32R16 - 20345U, // MoveR3216 - 23496U, // MultRxRy16 - 75799496U, // MultRxRyRz16 - 23642U, // MultuRxRy16 - 75799642U, // MultuRxRyRz16 - 17028U, // NLOC_B - 18521U, // NLOC_D - 20436U, // NLOC_H - 23880U, // NLOC_W - 17036U, // NLZC_B - 18529U, // NLZC_D - 20444U, // NLZC_H - 23888U, // NLZC_W - 134236282U, // NMADD_D32 - 134236282U, // NMADD_D32_MM - 134236282U, // NMADD_D64 - 134240570U, // NMADD_S - 134240570U, // NMADD_S_MM - 134236240U, // NMSUB_D32 - 134236240U, // NMSUB_D32_MM - 134236240U, // NMSUB_D64 - 134240552U, // NMSUB_S - 134240552U, // NMSUB_S_MM - 0U, // NOP - 134240502U, // NOR - 134240502U, // NOR64 - 2281718573U, // NORI_B - 134240502U, // NOR_MM - 134241412U, // NOR_V - 0U, // NOR_V_D_PSEUDO - 0U, // NOR_V_H_PSEUDO - 0U, // NOR_V_W_PSEUDO - 16825U, // NOT16_MM - 20387U, // NegRxRy16 - 23502U, // NotRxRy16 - 134240503U, // OR - 836010U, // OR16_MM - 134240503U, // OR64 - 2281718574U, // ORI_B - 134240503U, // OR_MM - 134241413U, // OR_V - 0U, // OR_V_D_PSEUDO - 0U, // OR_V_H_PSEUDO - 0U, // OR_V_W_PSEUDO - 134239771U, // ORi - 134239771U, // ORi64 - 134239771U, // ORi_MM - 16799991U, // OrRxRxRy16 - 134239239U, // PACKRL_PH - 9442U, // PAUSE - 9442U, // PAUSE_MM - 134235499U, // PCKEV_B - 134237844U, // PCKEV_D - 134239059U, // PCKEV_H - 134243134U, // PCKEV_W - 134234779U, // PCKOD_B - 134236298U, // PCKOD_D - 134238187U, // PCKOD_H - 134241657U, // PCKOD_W - 17555U, // PCNT_B - 19778U, // PCNT_D - 21063U, // PCNT_H - 25076U, // PCNT_W - 134239203U, // PICK_PH - 134235631U, // PICK_QB - 22522U, // POP - 22186U, // PRECEQU_PH_QBL - 16906U, // PRECEQU_PH_QBLA - 22682U, // PRECEQU_PH_QBR - 16939U, // PRECEQU_PH_QBRA - 22260U, // PRECEQ_W_PHL - 22722U, // PRECEQ_W_PHR - 22171U, // PRECEU_PH_QBL - 16890U, // PRECEU_PH_QBLA - 22667U, // PRECEU_PH_QBR - 16923U, // PRECEU_PH_QBRA - 134239155U, // PRECRQU_S_QB_PH - 134241800U, // PRECRQ_PH_W - 134239128U, // PRECRQ_QB_PH - 134241831U, // PRECRQ_RS_PH_W - 134239142U, // PRECR_QB_PH - 134241784U, // PRECR_SRA_PH_W - 134241813U, // PRECR_SRA_R_PH_W - 85911U, // PREF - 85911U, // PREF_MM - 85911U, // PREF_R6 - 134238019U, // PREPEND - 0U, // PseudoCMPU_EQ_QB - 0U, // PseudoCMPU_LE_QB - 0U, // PseudoCMPU_LT_QB - 0U, // PseudoCMP_EQ_PH - 0U, // PseudoCMP_LE_PH - 0U, // PseudoCMP_LT_PH - 16391U, // PseudoCVT_D32_W - 16391U, // PseudoCVT_D64_L - 16391U, // PseudoCVT_D64_W - 16391U, // PseudoCVT_S_L - 16391U, // PseudoCVT_S_W - 0U, // PseudoDMULT - 0U, // PseudoDMULTu - 0U, // PseudoDSDIV - 0U, // PseudoDUDIV - 0U, // PseudoIndirectBranch - 0U, // PseudoIndirectBranch64 - 0U, // PseudoMADD - 0U, // PseudoMADDU - 0U, // PseudoMFHI - 0U, // PseudoMFHI64 - 0U, // PseudoMFLO - 0U, // PseudoMFLO64 - 0U, // PseudoMSUB - 0U, // PseudoMSUBU - 0U, // PseudoMTLOHI - 0U, // PseudoMTLOHI64 - 0U, // PseudoMTLOHI_DSP - 0U, // PseudoMULT - 0U, // PseudoMULTu - 0U, // PseudoPICK_PH - 0U, // PseudoPICK_QB - 0U, // PseudoReturn - 0U, // PseudoReturn64 - 0U, // PseudoSDIV - 0U, // PseudoSELECTFP_F_D32 - 0U, // PseudoSELECTFP_F_D64 - 0U, // PseudoSELECTFP_F_I - 0U, // PseudoSELECTFP_F_I64 - 0U, // PseudoSELECTFP_F_S - 0U, // PseudoSELECTFP_T_D32 - 0U, // PseudoSELECTFP_T_D64 - 0U, // PseudoSELECTFP_T_I - 0U, // PseudoSELECTFP_T_I64 - 0U, // PseudoSELECTFP_T_S - 0U, // PseudoSELECT_D32 - 0U, // PseudoSELECT_D64 - 0U, // PseudoSELECT_I - 0U, // PseudoSELECT_I64 - 0U, // PseudoSELECT_S - 0U, // PseudoUDIV - 18155U, // RADDU_W_QB - 33577003U, // RDDSP - 22791U, // RDHWR - 22791U, // RDHWR64 - 22791U, // RDHWR_MM - 21766U, // REPLV_PH - 18135U, // REPLV_QB - 33575925U, // REPL_PH - 33572353U, // REPL_QB - 19787U, // RINT_D - 23293U, // RINT_S - 134240513U, // ROTR - 134241514U, // ROTRV - 134241514U, // ROTRV_MM - 134240513U, // ROTR_MM - 18992U, // ROUND_L_D64 - 23020U, // ROUND_L_S - 20168U, // ROUND_W_D32 - 20168U, // ROUND_W_D64 - 20168U, // ROUND_W_MM - 23342U, // ROUND_W_S - 23342U, // ROUND_W_S_MM - 0U, // Restore16 - 0U, // RestoreX16 - 0U, // RetRA - 0U, // RetRA16 - 134235208U, // SAT_S_B - 134237279U, // SAT_S_D - 2281722353U, // SAT_S_H - 134242618U, // SAT_S_W - 134235435U, // SAT_U_B - 134237758U, // SAT_U_D - 2281722643U, // SAT_U_H - 134243048U, // SAT_U_W - 58738423U, // SB - 58736980U, // SB16_MM - 58738423U, // SB64 - 58738423U, // SB_MM - 3966874U, // SC - 3968802U, // SCD - 3968802U, // SCD_R6 - 3966874U, // SC_MM - 3966874U, // SC_R6 - 58740570U, // SD - 546774U, // SDBBP - 65946U, // SDBBP16_MM - 546774U, // SDBBP_MM - 546774U, // SDBBP_R6 - 58736694U, // SDC1 - 58736694U, // SDC164 - 58736694U, // SDC1_MM - 58736894U, // SDC2 - 58736894U, // SDC2_R6 - 58736953U, // SDC3 - 25611U, // SDIV - 25611U, // SDIV_MM - 58742463U, // SDL - 58742959U, // SDR - 1358970999U, // SDXC1 - 1358970999U, // SDXC164 - 17810U, // SEB - 17810U, // SEB64 - 17810U, // SEB_MM - 21382U, // SEH - 21382U, // SEH64 - 21382U, // SEH_MM - 134243273U, // SELEQZ - 134243273U, // SELEQZ64 - 134237968U, // SELEQZ_D - 134241128U, // SELEQZ_S - 134243246U, // SELNEZ - 134243246U, // SELNEZ64 - 134237951U, // SELNEZ_D - 134241118U, // SELNEZ_S - 151013977U, // SEL_D - 151018005U, // SEL_S - 134240345U, // SEQ - 134239758U, // SEQi - 58742195U, // SH - 58736993U, // SH16_MM - 58742195U, // SH64 - 2281718455U, // SHF_B - 2281721863U, // SHF_H - 2281725417U, // SHF_W - 22463U, // SHILO - 23761U, // SHILOV - 134239484U, // SHLLV_PH - 134235853U, // SHLLV_QB - 134239421U, // SHLLV_S_PH - 134242679U, // SHLLV_S_W - 134239212U, // SHLL_PH - 134235640U, // SHLL_QB - 134239334U, // SHLL_S_PH - 134242519U, // SHLL_S_W - 134239474U, // SHRAV_PH - 134235843U, // SHRAV_QB - 134239322U, // SHRAV_R_PH - 134235741U, // SHRAV_R_QB - 134242274U, // SHRAV_R_W - 134239119U, // SHRA_PH - 134235563U, // SHRA_QB - 134239287U, // SHRA_R_PH - 134235706U, // SHRA_R_QB - 134242232U, // SHRA_R_W - 134239504U, // SHRLV_PH - 134235873U, // SHRLV_QB - 134239230U, // SHRL_PH - 134235658U, // SHRL_QB - 58742195U, // SH_MM - 2969584334U, // SLDI_B - 2969586088U, // SLDI_D - 2969587742U, // SLDI_H - 2969591377U, // SLDI_W - 822100628U, // SLD_B - 822102147U, // SLD_D - 822104036U, // SLD_H - 822107506U, // SLD_W - 134240058U, // SLL - 134234494U, // SLL16_MM - 1610635066U, // SLL64_32 - 1610635066U, // SLL64_64 - 2281718512U, // SLLI_B - 2281720249U, // SLLI_D - 2281721903U, // SLLI_H - 2281725538U, // SLLI_W - 134241476U, // SLLV - 134241476U, // SLLV_MM - 134235013U, // SLL_B - 134236785U, // SLL_D - 134238371U, // SLL_H - 134240058U, // SLL_MM - 134242032U, // SLL_W - 134241213U, // SLT - 134241213U, // SLT64 - 134241213U, // SLT_MM - 134239782U, // SLTi - 134239782U, // SLTi64 - 134239782U, // SLTi_MM - 134241321U, // SLTiu - 134241321U, // SLTiu64 - 134241321U, // SLTiu_MM - 134241357U, // SLTu - 134241357U, // SLTu64 - 134241357U, // SLTu_MM - 134238063U, // SNE - 134239703U, // SNEi - 0U, // SNZ_B_PSEUDO - 0U, // SNZ_D_PSEUDO - 0U, // SNZ_H_PSEUDO - 0U, // SNZ_V_PSEUDO - 0U, // SNZ_W_PSEUDO - 2952807239U, // SPLATI_B - 2952808960U, // SPLATI_D - 2952810614U, // SPLATI_H - 2952814249U, // SPLATI_W - 805323906U, // SPLAT_B - 805326016U, // SPLAT_D - 805327414U, // SPLAT_H - 805331393U, // SPLAT_W - 134234685U, // SRA - 2281718470U, // SRAI_B - 2281720224U, // SRAI_D - 2281721878U, // SRAI_H - 2281725513U, // SRAI_W - 134234898U, // SRARI_B - 134236635U, // SRARI_D - 2281721937U, // SRARI_H - 134241924U, // SRARI_W - 134235051U, // SRAR_B - 134237015U, // SRAR_D - 134238486U, // SRAR_H - 134242296U, // SRAR_W - 134241455U, // SRAV - 134241455U, // SRAV_MM - 134234749U, // SRA_B - 134236208U, // SRA_D - 134238157U, // SRA_H - 134234685U, // SRA_MM - 134241584U, // SRA_W - 134240070U, // SRL - 134234501U, // SRL16_MM - 2281718520U, // SRLI_B - 2281720257U, // SRLI_D - 2281721911U, // SRLI_H - 2281725546U, // SRLI_W - 134234916U, // SRLRI_B - 134236653U, // SRLRI_D - 2281721955U, // SRLRI_H - 134241942U, // SRLRI_W - 134235067U, // SRLR_B - 134237031U, // SRLR_D - 134238502U, // SRLR_H - 134242312U, // SRLR_W - 134241483U, // SRLV - 134241483U, // SRLV_MM - 134235020U, // SRL_B - 134236810U, // SRL_D - 134238378U, // SRL_H - 134240070U, // SRL_MM - 134242057U, // SRL_W - 9463U, // SSNOP - 9463U, // SSNOP_MM - 58736647U, // STORE_ACC128 - 58736647U, // STORE_ACC64 - 58736647U, // STORE_ACC64DSP - 58742810U, // STORE_CCOND_DSP - 58737829U, // ST_B - 58740080U, // ST_D - 58741337U, // ST_H - 58745378U, // ST_W - 134235902U, // SUB - 134239183U, // SUBQH_PH - 134239298U, // SUBQH_R_PH - 134242242U, // SUBQH_R_W - 134241847U, // SUBQH_W - 134239258U, // SUBQ_PH - 134239355U, // SUBQ_S_PH - 134242548U, // SUBQ_S_W - 134235423U, // SUBSUS_U_B - 134237746U, // SUBSUS_U_D - 134238983U, // SUBSUS_U_H - 134243036U, // SUBSUS_U_W - 134235226U, // SUBSUU_S_B - 134237319U, // SUBSUU_S_D - 134238723U, // SUBSUU_S_H - 134242658U, // SUBSUU_S_W - 134235188U, // SUBS_S_B - 134237259U, // SUBS_S_D - 134238685U, // SUBS_S_H - 134242598U, // SUBS_S_W - 134235403U, // SUBS_U_B - 134237726U, // SUBS_U_D - 134238963U, // SUBS_U_H - 134243016U, // SUBS_U_W - 134234567U, // SUBU16_MM - 134235611U, // SUBUH_QB - 134235717U, // SUBUH_R_QB - 134239456U, // SUBU_PH - 134235825U, // SUBU_QB - 134239399U, // SUBU_S_PH - 134235764U, // SUBU_S_QB - 2281718618U, // SUBVI_B - 2281720339U, // SUBVI_D - 2281721993U, // SUBVI_H - 2281725628U, // SUBVI_W - 134235482U, // SUBV_B - 134237827U, // SUBV_D - 134239042U, // SUBV_H - 134243117U, // SUBV_W - 134235902U, // SUB_MM - 134241247U, // SUBu - 134241247U, // SUBu_MM - 1358971013U, // SUXC1 - 1358971013U, // SUXC164 - 1358971013U, // SUXC1_MM - 58745730U, // SW - 58737124U, // SW16_MM - 58745730U, // SW64 - 58736746U, // SWC1 - 58736746U, // SWC1_MM - 58736920U, // SWC2 - 58736920U, // SWC2_R6 - 58736965U, // SWC3 - 58742642U, // SWL - 58742642U, // SWL64 - 58742642U, // SWL_MM - 3522963U, // SWM16_MM - 3522792U, // SWM32_MM - 3528600U, // SWM_MM - 137295U, // SWP_MM - 58743059U, // SWR - 58743059U, // SWR64 - 58743059U, // SWR_MM - 58745730U, // SWSP_MM - 1358971027U, // SWXC1 - 1358971027U, // SWXC1_MM - 58745730U, // SW_MM - 549939U, // SYNC - 153021U, // SYNCI - 549939U, // SYNC_MM - 546590U, // SYSCALL - 546590U, // SYSCALL_MM - 0U, // SZ_B_PSEUDO - 0U, // SZ_D_PSEUDO - 0U, // SZ_H_PSEUDO - 0U, // SZ_V_PSEUDO - 0U, // SZ_W_PSEUDO - 0U, // Save16 - 0U, // SaveX16 - 58738423U, // SbRxRyOffMemX16 - 549866U, // SebRx16 - 549878U, // SehRx16 - 4367299U, // SelBeqZ - 4367272U, // SelBneZ - 1828886516U, // SelTBteqZCmp - 1828886024U, // SelTBteqZCmpi - 1828887485U, // SelTBteqZSlt - 1828886054U, // SelTBteqZSlti - 1828887593U, // SelTBteqZSltiu - 1828887629U, // SelTBteqZSltu - 1963104244U, // SelTBtneZCmp - 1963103752U, // SelTBtneZCmpi - 1963105213U, // SelTBtneZSlt - 1963103782U, // SelTBtneZSlti - 1963105321U, // SelTBtneZSltiu - 1963105357U, // SelTBtneZSltu - 58742195U, // ShRxRyOffMemX16 - 134240058U, // SllX16 - 16800964U, // SllvRxRy16 - 92576701U, // SltCCRxRy16 - 23485U, // SltRxRy16 - 92575270U, // SltiCCRxImmX16 - 939546150U, // SltiRxImm16 - 22054U, // SltiRxImmX16 - 92576809U, // SltiuCCRxImmX16 - 939547689U, // SltiuRxImm16 - 23593U, // SltiuRxImmX16 - 92576845U, // SltuCCRxRy16 - 23629U, // SltuRxRy16 - 92576845U, // SltuRxRyRz16 - 134234685U, // SraX16 - 16800943U, // SravRxRy16 - 134240070U, // SrlX16 - 16800971U, // SrlvRxRy16 - 134241247U, // SubuRxRyRz16 - 58745730U, // SwRxRyOffMemX16 - 1493197698U, // SwRxSpImmX16 - 0U, // TAILCALL - 0U, // TAILCALL64_R - 0U, // TAILCALL_R - 134240350U, // TEQ - 33576468U, // TEQI - 33576468U, // TEQI_MM - 134240350U, // TEQ_MM - 134238046U, // TGE - 33576401U, // TGEI - 33578018U, // TGEIU - 33578018U, // TGEIU_MM - 33576401U, // TGEI_MM - 134241288U, // TGEU - 134241288U, // TGEU_MM - 134238046U, // TGE_MM - 9458U, // TLBP - 9458U, // TLBP_MM - 9469U, // TLBR - 9469U, // TLBR_MM - 9448U, // TLBWI - 9448U, // TLBWI_MM - 9474U, // TLBWR - 9474U, // TLBWR_MM - 134241218U, // TLT - 33576492U, // TLTI - 33578032U, // TLTIU_MM - 33576492U, // TLTI_MM - 134241363U, // TLTU - 134241363U, // TLTU_MM - 134241218U, // TLT_MM - 134238068U, // TNE - 33576413U, // TNEI - 33576413U, // TNEI_MM - 134238068U, // TNE_MM - 0U, // TRAP - 18981U, // TRUNC_L_D64 - 23009U, // TRUNC_L_S - 20157U, // TRUNC_W_D32 - 20157U, // TRUNC_W_D64 - 20157U, // TRUNC_W_MM - 23331U, // TRUNC_W_S - 23331U, // TRUNC_W_S_MM - 33578032U, // TTLTIU - 25597U, // UDIV - 25597U, // UDIV_MM - 134241335U, // V3MULU - 134234135U, // VMM0 - 134241350U, // VMULU - 151012022U, // VSHF_B - 151013760U, // VSHF_D - 151015430U, // VSHF_H - 151018984U, // VSHF_W - 9486U, // WAIT - 547767U, // WAIT_MM - 33577010U, // WRDSP - 21376U, // WSBH - 21376U, // WSBH_MM - 134240507U, // XOR - 836009U, // XOR16_MM - 134240507U, // XOR64 - 2281718581U, // XORI_B - 134240507U, // XOR_MM - 134241419U, // XOR_V - 0U, // XOR_V_D_PSEUDO - 0U, // XOR_V_H_PSEUDO - 0U, // XOR_V_W_PSEUDO - 134239770U, // XORi - 134239770U, // XORi64 - 134239770U, // XORi_MM - 16799995U, // XorRxRxRy16 - 0U - }; +static void printInstruction(MCInst *MI, SStream *O, + const MCRegisterInfo *MRI) { + static const uint32_t OpInfo[] = {0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 9396U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 9389U, // BUNDLE + 9406U, // LIFETIME_START + 9376U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 21660U, // ABSQ_S_PH + 18025U, // ABSQ_S_QB + 24850U, // ABSQ_S_W + 134237992U, // ADD + 18294U, // ADDIUPC + 18294U, // ADDIUPC_MM + 22527U, // ADDIUR1SP_MM + 134234410U, // ADDIUR2_MM + 8683851U, // ADDIUS5_MM + 546875U, // ADDIUSP_MM + 134239193U, // ADDQH_PH + 134239310U, // ADDQH_R_PH + 134242253U, // ADDQH_R_W + 134241856U, // ADDQH_W + 134239267U, // ADDQ_PH + 134239366U, // ADDQ_S_PH + 134242558U, // ADDQ_S_W + 134236055U, // ADDSC + 134234730U, // ADDS_A_B + 134236180U, // ADDS_A_D + 134238138U, // ADDS_A_H + 134241564U, // ADDS_A_W + 134235198U, // ADDS_S_B + 134237269U, // ADDS_S_D + 134238695U, // ADDS_S_H + 134242608U, // ADDS_S_W + 134235413U, // ADDS_U_B + 134237736U, // ADDS_U_D + 134238973U, // ADDS_U_H + 134243026U, // ADDS_U_W + 134234575U, // ADDU16_MM + 134235621U, // ADDUH_QB + 134235729U, // ADDUH_R_QB + 134239465U, // ADDU_PH + 134235834U, // ADDU_QB + 134239410U, // ADDU_S_PH + 134235775U, // ADDU_S_QB + 2281718627U, // ADDVI_B + 2281720348U, // ADDVI_D + 2281722002U, // ADDVI_H + 2281725637U, // ADDVI_W + 134235491U, // ADDV_B + 134237836U, // ADDV_D + 134239051U, // ADDV_H + 134243126U, // ADDV_W + 134236094U, // ADDWC + 134234712U, // ADD_A_B + 134236161U, // ADD_A_D + 134238120U, // ADD_A_H + 134241545U, // ADD_A_W + 134237992U, // ADD_MM + 134239685U, // ADDi + 134239685U, // ADDi_MM + 134241307U, // ADDiu + 134241307U, // ADDiu_MM + 134241261U, // ADDu + 134241261U, // ADDu_MM + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 134240158U, // ALIGN + 18286U, // ALUIPC + 134238014U, // AND + 835930U, // AND16_MM + 134238014U, // AND64 + 134234471U, // ANDI16_MM + 2281718486U, // ANDI_B + 134238014U, // AND_MM + 134241389U, // AND_V + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 134239691U, // ANDi + 134239691U, // ANDi64 + 134239691U, // ANDi_MM + 134238028U, // APPEND + 134235092U, // ASUB_S_B + 134237099U, // ASUB_S_D + 134238527U, // ASUB_S_H + 134242388U, // ASUB_S_W + 134235307U, // ASUB_U_B + 134237566U, // ASUB_U_D + 134238815U, // ASUB_U_H + 134242856U, // ASUB_U_W + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 134239795U, // AUI + 18279U, // AUIPC + 134235178U, // AVER_S_B + 134237249U, // AVER_S_D + 134238665U, // AVER_S_H + 134242588U, // AVER_S_W + 134235393U, // AVER_U_B + 134237716U, // AVER_U_D + 134238953U, // AVER_U_H + 134243006U, // AVER_U_W + 134235120U, // AVE_S_B + 134237181U, // AVE_S_D + 134238597U, // AVE_S_H + 134242470U, // AVE_S_W + 134235335U, // AVE_U_B + 134237648U, // AVE_U_D + 134238885U, // AVE_U_H + 134242938U, // AVE_U_W + 23579U, // AddiuRxImmX16 + 1072155U, // AddiuRxPcImmX16 + 285236251U, // AddiuRxRxImm16 + 16800795U, // AddiuRxRxImmX16 + 25189403U, // AddiuRxRyOffMemX16 + 1336343U, // AddiuSpImm16 + 549911U, // AddiuSpImmX16 + 134241261U, // AdduRxRyRz16 + 16797502U, // AndRxRxRy16 + 0U, // B + 541013U, // B16_MM + 134241260U, // BADDu + 546393U, // BAL + 542494U, // BALC + 134240157U, // BALIGN + 0U, // BAL_BR + 167788585U, // BBIT0 + 167788717U, // BBIT032 + 167788710U, // BBIT1 + 167788726U, // BBIT132 + 542473U, // BC + 20351U, // BC0F + 22218U, // BC0FL + 23455U, // BC0T + 22347U, // BC0TL + 25733U, // BC1EQZ + 20357U, // BC1F + 22225U, // BC1FL + 20357U, // BC1F_MM + 25717U, // BC1NEZ + 23461U, // BC1T + 22354U, // BC1TL + 23461U, // BC1T_MM + 25741U, // BC2EQZ + 20363U, // BC2F + 22232U, // BC2FL + 25725U, // BC2NEZ + 23467U, // BC2T + 22361U, // BC2TL + 20369U, // BC3F + 22239U, // BC3FL + 23473U, // BC3T + 22368U, // BC3TL + 2281718555U, // BCLRI_B + 2281720292U, // BCLRI_D + 2281721946U, // BCLRI_H + 2281725581U, // BCLRI_W + 134235059U, // BCLR_B + 134237023U, // BCLR_D + 134238494U, // BCLR_H + 134242304U, // BCLR_W + 134240340U, // BEQ + 134240340U, // BEQ64 + 134236044U, // BEQC + 134240063U, // BEQL + 16882U, // BEQZ16_MM + 18246U, // BEQZALC + 18394U, // BEQZC + 18394U, // BEQZC_MM + 134240340U, // BEQ_MM + 134235917U, // BGEC + 134236068U, // BGEUC + 25500U, // BGEZ + 25500U, // BGEZ64 + 22115U, // BGEZAL + 18219U, // BGEZALC + 22311U, // BGEZALL + 23424U, // BGEZALS_MM + 22115U, // BGEZAL_MM + 18373U, // BGEZC + 22391U, // BGEZL + 25500U, // BGEZ_MM + 25560U, // BGTZ + 25560U, // BGTZ64 + 18255U, // BGTZALC + 18401U, // BGTZC + 22405U, // BGTZL + 25560U, // BGTZ_MM + 2298495744U, // BINSLI_B + 2298497481U, // BINSLI_D + 2298499135U, // BINSLI_H + 2298502770U, // BINSLI_W + 151012243U, // BINSL_B + 151014033U, // BINSL_D + 151015601U, // BINSL_H + 151019280U, // BINSL_W + 2298495805U, // BINSRI_B + 2298497526U, // BINSRI_D + 2298499180U, // BINSRI_H + 2298502815U, // BINSRI_W + 151012291U, // BINSR_B + 151014289U, // BINSR_D + 151015726U, // BINSR_H + 151019570U, // BINSR_W + 23733U, // BITREV + 22477U, // BITSWAP + 25506U, // BLEZ + 25506U, // BLEZ64 + 18228U, // BLEZALC + 18380U, // BLEZC + 22398U, // BLEZL + 25506U, // BLEZ_MM + 134236062U, // BLTC + 134236075U, // BLTUC + 25566U, // BLTZ + 25566U, // BLTZ64 + 22123U, // BLTZAL + 18264U, // BLTZALC + 22320U, // BLTZALL + 23433U, // BLTZALS_MM + 22123U, // BLTZAL_MM + 18408U, // BLTZC + 22412U, // BLTZL + 25566U, // BLTZ_MM + 2298495860U, // BMNZI_B + 151018662U, // BMNZ_V + 2298495852U, // BMZI_B + 151018648U, // BMZ_V + 134238058U, // BNE + 134238058U, // BNE64 + 134235923U, // BNEC + 2281718494U, // BNEGI_B + 2281720240U, // BNEGI_D + 2281721894U, // BNEGI_H + 2281725529U, // BNEGI_W + 134234814U, // BNEG_B + 134236568U, // BNEG_D + 134238222U, // BNEG_H + 134241776U, // BNEG_W + 134239940U, // BNEL + 16874U, // BNEZ16_MM + 18237U, // BNEZALC + 18387U, // BNEZC + 18387U, // BNEZC_MM + 134238058U, // BNE_MM + 134236082U, // BNVC + 17803U, // BNZ_B + 20233U, // BNZ_D + 21363U, // BNZ_H + 23711U, // BNZ_V + 25463U, // BNZ_W + 134236088U, // BOVC + 540871U, // BPOSGE32 + 0U, // BPOSGE32_PSEUDO + 22080U, // BREAK + 65909U, // BREAK16_MM + 22080U, // BREAK_MM + 2298495719U, // BSELI_B + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 151018620U, // BSEL_V + 0U, // BSEL_W_PSEUDO + 2281718609U, // BSETI_B + 2281720330U, // BSETI_D + 2281721984U, // BSETI_H + 2281725619U, // BSETI_W + 134235275U, // BSET_B + 134237385U, // BSET_D + 134238783U, // BSET_H + 134242762U, // BSET_W + 17797U, // BZ_B + 20217U, // BZ_D + 21357U, // BZ_H + 23698U, // BZ_V + 25457U, // BZ_W + 541278U, // B_MM_Pseudo + 402678723U, // BeqzRxImm16 + 25539U, // BeqzRxImmX16 + 1327710U, // Bimm16 + 541278U, // BimmX16 + 402678696U, // BnezRxImm16 + 25512U, // BnezRxImmX16 + 9368U, // Break16 + 1598417U, // Bteqz16 + 536893428U, // BteqzT8CmpX16 + 536892936U, // BteqzT8CmpiX16 + 536894397U, // BteqzT8SltX16 + 536892966U, // BteqzT8SltiX16 + 536894505U, // BteqzT8SltiuX16 + 536894541U, // BteqzT8SltuX16 + 549841U, // BteqzX16 + 1598390U, // Btnez16 + 671111156U, // BtnezT8CmpX16 + 671110664U, // BtnezT8CmpiX16 + 671112125U, // BtnezT8SltX16 + 671110694U, // BtnezT8SltiX16 + 671112233U, // BtnezT8SltiuX16 + 671112269U, // BtnezT8SltuX16 + 549814U, // BtnezX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 85859U, // CACHE + 85859U, // CACHE_MM + 85859U, // CACHE_R6 + 19003U, // CEIL_L_D64 + 23031U, // CEIL_L_S + 20179U, // CEIL_W_D32 + 20179U, // CEIL_W_D64 + 20179U, // CEIL_W_MM + 23353U, // CEIL_W_S + 23353U, // CEIL_W_S_MM + 134234890U, // CEQI_B + 134236627U, // CEQI_D + 134238281U, // CEQI_H + 134241916U, // CEQI_W + 134235044U, // CEQ_B + 134236930U, // CEQ_D + 134238472U, // CEQ_H + 134242192U, // CEQ_W + 16444U, // CFC1 + 16444U, // CFC1_MM + 16968U, // CFCMSA + 134243407U, // CINS + 134243363U, // CINS32 + 19639U, // CLASS_D + 23205U, // CLASS_S + 134235129U, // CLEI_S_B + 134237190U, // CLEI_S_D + 134238606U, // CLEI_S_H + 134242479U, // CLEI_S_W + 2281718992U, // CLEI_U_B + 2281721305U, // CLEI_U_D + 2281722542U, // CLEI_U_H + 2281726595U, // CLEI_U_W + 134235111U, // CLE_S_B + 134237172U, // CLE_S_D + 134238588U, // CLE_S_H + 134242461U, // CLE_S_W + 134235326U, // CLE_U_B + 134237639U, // CLE_U_D + 134238876U, // CLE_U_H + 134242929U, // CLE_U_W + 22452U, // CLO + 22452U, // CLO_MM + 22452U, // CLO_R6 + 134235149U, // CLTI_S_B + 134237210U, // CLTI_S_D + 134238626U, // CLTI_S_H + 134242499U, // CLTI_S_W + 2281719012U, // CLTI_U_B + 2281721325U, // CLTI_U_D + 2281722562U, // CLTI_U_H + 2281726615U, // CLTI_U_W + 134235217U, // CLT_S_B + 134237288U, // CLT_S_D + 134238714U, // CLT_S_H + 134242627U, // CLT_S_W + 134235444U, // CLT_U_B + 134237767U, // CLT_U_D + 134239004U, // CLT_U_H + 134243057U, // CLT_U_W + 25534U, // CLZ + 25534U, // CLZ_MM + 25534U, // CLZ_R6 + 134235667U, // CMPGDU_EQ_QB + 134235572U, // CMPGDU_LE_QB + 134235786U, // CMPGDU_LT_QB + 134235681U, // CMPGU_EQ_QB + 134235586U, // CMPGU_LE_QB + 134235800U, // CMPGU_LT_QB + 17966U, // CMPU_EQ_QB + 17871U, // CMPU_LE_QB + 18085U, // CMPU_LT_QB + 134236919U, // CMP_EQ_D + 21548U, // CMP_EQ_PH + 134240864U, // CMP_EQ_S + 134236489U, // CMP_F_D + 134240675U, // CMP_F_S + 134236333U, // CMP_LE_D + 21444U, // CMP_LE_PH + 134240596U, // CMP_LE_S + 134237410U, // CMP_LT_D + 21717U, // CMP_LT_PH + 134240959U, // CMP_LT_S + 134236507U, // CMP_SAF_D + 134240685U, // CMP_SAF_S + 134236946U, // CMP_SEQ_D + 134240883U, // CMP_SEQ_S + 134236370U, // CMP_SLE_D + 134240625U, // CMP_SLE_S + 134237437U, // CMP_SLT_D + 134240978U, // CMP_SLT_S + 134236994U, // CMP_SUEQ_D + 134240914U, // CMP_SUEQ_S + 134236418U, // CMP_SULE_D + 134240656U, // CMP_SULE_S + 134237485U, // CMP_SULT_D + 134241009U, // CMP_SULT_S + 134236876U, // CMP_SUN_D + 134240837U, // CMP_SUN_S + 134236974U, // CMP_UEQ_D + 134240903U, // CMP_UEQ_S + 134236398U, // CMP_ULE_D + 134240645U, // CMP_ULE_S + 134237465U, // CMP_ULT_D + 134240998U, // CMP_ULT_S + 134236858U, // CMP_UN_D + 134240827U, // CMP_UN_S + 9454U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 2952807544U, // COPY_S_B + 2952809637U, // COPY_S_D + 2952811052U, // COPY_S_H + 2952814987U, // COPY_S_W + 2952807759U, // COPY_U_B + 2952810104U, // COPY_U_D + 2952811319U, // COPY_U_H + 2952815394U, // COPY_U_W + 1867863U, // CTC1 + 1867863U, // CTC1_MM + 16976U, // CTCMSA + 22833U, // CVT_D32_S + 23896U, // CVT_D32_W + 23896U, // CVT_D32_W_MM + 22087U, // CVT_D64_L + 22833U, // CVT_D64_S + 23896U, // CVT_D64_W + 22833U, // CVT_D_S_MM + 19024U, // CVT_L_D64 + 19024U, // CVT_L_D64_MM + 23052U, // CVT_L_S + 23052U, // CVT_L_S_MM + 19362U, // CVT_S_D32 + 19362U, // CVT_S_D32_MM + 19362U, // CVT_S_D64 + 22096U, // CVT_S_L + 24651U, // CVT_S_W + 24651U, // CVT_S_W_MM + 20200U, // CVT_W_D32 + 20200U, // CVT_W_D64 + 20200U, // CVT_W_MM + 23374U, // CVT_W_S + 23374U, // CVT_W_S_MM + 19183U, // C_EQ_D32 + 19183U, // C_EQ_D64 + 23128U, // C_EQ_S + 18754U, // C_F_D32 + 18754U, // C_F_D64 + 22940U, // C_F_S + 18597U, // C_LE_D32 + 18597U, // C_LE_D64 + 22860U, // C_LE_S + 19674U, // C_LT_D32 + 19674U, // C_LT_D64 + 23223U, // C_LT_S + 18588U, // C_NGE_D32 + 18588U, // C_NGE_D64 + 22851U, // C_NGE_S + 18623U, // C_NGLE_D32 + 18623U, // C_NGLE_D64 + 22878U, // C_NGLE_S + 19040U, // C_NGL_D32 + 19040U, // C_NGL_D64 + 23068U, // C_NGL_S + 19665U, // C_NGT_D32 + 19665U, // C_NGT_D64 + 23214U, // C_NGT_S + 18633U, // C_OLE_D32 + 18633U, // C_OLE_D64 + 22888U, // C_OLE_S + 19700U, // C_OLT_D32 + 19700U, // C_OLT_D64 + 23241U, // C_OLT_S + 19209U, // C_SEQ_D32 + 19209U, // C_SEQ_D64 + 23146U, // C_SEQ_S + 18824U, // C_SF_D32 + 18824U, // C_SF_D64 + 22986U, // C_SF_S + 19237U, // C_UEQ_D32 + 19237U, // C_UEQ_D64 + 23166U, // C_UEQ_S + 18661U, // C_ULE_D32 + 18661U, // C_ULE_D64 + 22908U, // C_ULE_S + 19728U, // C_ULT_D32 + 19728U, // C_ULT_D64 + 23261U, // C_ULT_S + 19122U, // C_UN_D32 + 19122U, // C_UN_D64 + 23091U, // C_UN_S + 22516U, // CmpRxRy16 + 939546120U, // CmpiRxImm16 + 22024U, // CmpiRxImmX16 + 549945U, // Constant32 + 134237991U, // DADD + 134239684U, // DADDi + 134241306U, // DADDiu + 134241267U, // DADDu + 8689123U, // DAHI + 134240165U, // DALIGN + 8689184U, // DATI + 134239794U, // DAUI + 22476U, // DBITSWAP + 22451U, // DCLO + 22451U, // DCLO_R6 + 25533U, // DCLZ + 25533U, // DCLZ_R6 + 134241469U, // DDIV + 134241377U, // DDIVU + 9480U, // DERET + 9480U, // DERET_MM + 134243425U, // DEXT + 134243400U, // DEXTM + 134243438U, // DEXTU + 546247U, // DI + 134243413U, // DINS + 134243393U, // DINSM + 134243431U, // DINSU + 134241470U, // DIV + 134241378U, // DIVU + 134235238U, // DIV_S_B + 134237331U, // DIV_S_D + 134238735U, // DIV_S_H + 134242670U, // DIV_S_W + 134235453U, // DIV_U_B + 134237798U, // DIV_U_D + 134239013U, // DIV_U_H + 134243088U, // DIV_U_W + 546247U, // DI_MM + 134234690U, // DLSA + 134234690U, // DLSA_R6 + 134234121U, // DMFC0 + 16450U, // DMFC1 + 134234372U, // DMFC2 + 134238036U, // DMOD + 134241281U, // DMODU + 134234128U, // DMTC0 + 1867869U, // DMTC1 + 134234379U, // DMTC2 + 134239671U, // DMUH + 134241299U, // DMUHU + 134240103U, // DMUL + 23495U, // DMULT + 23641U, // DMULTu + 134241343U, // DMULU + 134240103U, // DMUL_R6 + 134237239U, // DOTP_S_D + 134238655U, // DOTP_S_H + 134242538U, // DOTP_S_W + 134237706U, // DOTP_U_D + 134238943U, // DOTP_U_H + 134242996U, // DOTP_U_W + 151014368U, // DPADD_S_D + 151015784U, // DPADD_S_H + 151019657U, // DPADD_S_W + 151014835U, // DPADD_U_D + 151016072U, // DPADD_U_H + 151020125U, // DPADD_U_W + 134239524U, // DPAQX_SA_W_PH + 134239607U, // DPAQX_S_W_PH + 134241998U, // DPAQ_SA_L_W + 134239566U, // DPAQ_S_W_PH + 134239859U, // DPAU_H_QBL + 134240355U, // DPAU_H_QBR + 134239645U, // DPAX_W_PH + 134239514U, // DPA_W_PH + 22521U, // DPOP + 134239539U, // DPSQX_SA_W_PH + 134239621U, // DPSQX_S_W_PH + 134242011U, // DPSQ_SA_L_W + 134239594U, // DPSQ_S_W_PH + 151014335U, // DPSUB_S_D + 151015763U, // DPSUB_S_H + 151019624U, // DPSUB_S_W + 151014802U, // DPSUB_U_D + 151016051U, // DPSUB_U_H + 151020092U, // DPSUB_U_W + 134239871U, // DPSU_H_QBL + 134240367U, // DPSU_H_QBR + 134239656U, // DPSX_W_PH + 134239635U, // DPS_W_PH + 134240512U, // DROTR + 134234351U, // DROTR32 + 134241513U, // DROTRV + 21370U, // DSBH + 25610U, // DSDIV + 20275U, // DSHD + 134240057U, // DSLL + 134234321U, // DSLL32 + 1073764153U, // DSLL64_32 + 134241475U, // DSLLV + 134234684U, // DSRA + 134234303U, // DSRA32 + 134241454U, // DSRAV + 134240069U, // DSRL + 134234329U, // DSRL32 + 134241482U, // DSRLV + 134235901U, // DSUB + 134241246U, // DSUBu + 25596U, // DUDIV + 25611U, // DivRxRy16 + 25597U, // DivuRxRy16 + 9438U, // EHB + 9438U, // EHB_MM + 546259U, // EI + 546259U, // EI_MM + 9481U, // ERET + 9481U, // ERET_MM + 134243426U, // EXT + 134240324U, // EXTP + 134240221U, // EXTPDP + 134241497U, // EXTPDPV + 134241506U, // EXTPV + 134242731U, // EXTRV_RS_W + 134242285U, // EXTRV_R_W + 134238744U, // EXTRV_S_H + 134243168U, // EXTRV_W + 134242720U, // EXTR_RS_W + 134242264U, // EXTR_R_W + 134238675U, // EXTR_S_H + 134242363U, // EXTR_W + 134243419U, // EXTS + 134243371U, // EXTS32 + 134243426U, // EXT_MM + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 19631U, // FABS_D32 + 19631U, // FABS_D64 + 19631U, // FABS_MM + 23198U, // FABS_S + 23198U, // FABS_S_MM + 0U, // FABS_W + 134236265U, // FADD_D + 134236266U, // FADD_D32 + 134236266U, // FADD_D64 + 134236266U, // FADD_MM + 134240572U, // FADD_S + 134240572U, // FADD_S_MM + 134241633U, // FADD_W + 134236499U, // FCAF_D + 134241752U, // FCAF_W + 134236929U, // FCEQ_D + 134242191U, // FCEQ_W + 19638U, // FCLASS_D + 25015U, // FCLASS_W + 134236343U, // FCLE_D + 134241675U, // FCLE_W + 134237420U, // FCLT_D + 134242770U, // FCLT_W + 2204821U, // FCMP_D32 + 2204821U, // FCMP_D32_MM + 2204821U, // FCMP_D64 + 2466965U, // FCMP_S32 + 2466965U, // FCMP_S32_MM + 134236439U, // FCNE_D + 134241709U, // FCNE_W + 134237039U, // FCOR_D + 134242320U, // FCOR_W + 134236985U, // FCUEQ_D + 134242207U, // FCUEQ_W + 134236409U, // FCULE_D + 134241691U, // FCULE_W + 134237476U, // FCULT_D + 134242786U, // FCULT_W + 134236455U, // FCUNE_D + 134241725U, // FCUNE_W + 134236868U, // FCUN_D + 134242097U, // FCUN_W + 134237862U, // FDIV_D + 134237863U, // FDIV_D32 + 134237863U, // FDIV_D64 + 134237863U, // FDIV_MM + 134241045U, // FDIV_S + 134241045U, // FDIV_S_MM + 134243152U, // FDIV_W + 134238402U, // FEXDO_H + 134242113U, // FEXDO_W + 134236152U, // FEXP2_D + 0U, // FEXP2_D_1_PSEUDO + 134241536U, // FEXP2_W + 0U, // FEXP2_W_1_PSEUDO + 19064U, // FEXUPL_D + 24311U, // FEXUPL_W + 19327U, // FEXUPR_D + 24608U, // FEXUPR_W + 19569U, // FFINT_S_D + 24908U, // FFINT_S_W + 20048U, // FFINT_U_D + 25338U, // FFINT_U_W + 19074U, // FFQL_D + 24321U, // FFQL_W + 19337U, // FFQR_D + 24618U, // FFQR_W + 17277U, // FILL_B + 19049U, // FILL_D + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 20635U, // FILL_H + 24296U, // FILL_W + 18415U, // FLOG2_D + 23799U, // FLOG2_W + 19013U, // FLOOR_L_D64 + 23041U, // FLOOR_L_S + 20189U, // FLOOR_W_D32 + 20189U, // FLOOR_W_D64 + 20189U, // FLOOR_W_MM + 23363U, // FLOOR_W_S + 23363U, // FLOOR_W_S_MM + 151013489U, // FMADD_D + 151018857U, // FMADD_W + 134236190U, // FMAX_A_D + 134241574U, // FMAX_A_W + 134237937U, // FMAX_D + 134243177U, // FMAX_W + 134236170U, // FMIN_A_D + 134241554U, // FMIN_A_W + 134236842U, // FMIN_D + 134242089U, // FMIN_W + 20150U, // FMOV_D32 + 20150U, // FMOV_D32_MM + 20150U, // FMOV_D64 + 23324U, // FMOV_S + 23324U, // FMOV_S_MM + 151013447U, // FMSUB_D + 151018815U, // FMSUB_W + 134236826U, // FMUL_D + 134236827U, // FMUL_D32 + 134236827U, // FMUL_D64 + 134236827U, // FMUL_MM + 134240805U, // FMUL_S + 134240805U, // FMUL_S_MM + 134242073U, // FMUL_W + 18841U, // FNEG_D32 + 18841U, // FNEG_D64 + 18841U, // FNEG_MM + 23002U, // FNEG_S + 23002U, // FNEG_S_MM + 19175U, // FRCP_D + 24394U, // FRCP_W + 19786U, // FRINT_D + 25084U, // FRINT_W + 19814U, // FRSQRT_D + 25112U, // FRSQRT_W + 134236518U, // FSAF_D + 134241760U, // FSAF_W + 134236957U, // FSEQ_D + 134242199U, // FSEQ_W + 134236381U, // FSLE_D + 134241683U, // FSLE_W + 134237448U, // FSLT_D + 134242778U, // FSLT_W + 134236447U, // FSNE_D + 134241717U, // FSNE_W + 134237047U, // FSOR_D + 134242328U, // FSOR_W + 19805U, // FSQRT_D + 19806U, // FSQRT_D32 + 19806U, // FSQRT_D64 + 19806U, // FSQRT_MM + 23301U, // FSQRT_S + 23301U, // FSQRT_S_MM + 25103U, // FSQRT_W + 134236223U, // FSUB_D + 134236224U, // FSUB_D32 + 134236224U, // FSUB_D64 + 134236224U, // FSUB_MM + 134240554U, // FSUB_S + 134240554U, // FSUB_S_MM + 134241591U, // FSUB_W + 134237006U, // FSUEQ_D + 134242216U, // FSUEQ_W + 134236430U, // FSULE_D + 134241700U, // FSULE_W + 134237497U, // FSULT_D + 134242795U, // FSULT_W + 134236464U, // FSUNE_D + 134241734U, // FSUNE_W + 134236887U, // FSUN_D + 134242105U, // FSUN_W + 19580U, // FTINT_S_D + 24919U, // FTINT_S_W + 20059U, // FTINT_U_D + 25349U, // FTINT_U_W + 134238479U, // FTQ_H + 134242225U, // FTQ_W + 19402U, // FTRUNC_S_D + 24691U, // FTRUNC_S_W + 19869U, // FTRUNC_U_D + 25159U, // FTRUNC_U_W + 1224758783U, // GotPrologue16 + 134237142U, // HADD_S_D + 134238558U, // HADD_S_H + 134242431U, // HADD_S_W + 134237609U, // HADD_U_D + 134238846U, // HADD_U_H + 134242899U, // HADD_U_W + 134237109U, // HSUB_S_D + 134238537U, // HSUB_S_H + 134242398U, // HSUB_S_W + 134237576U, // HSUB_U_D + 134238825U, // HSUB_U_H + 134242866U, // HSUB_U_W + 134235508U, // ILVEV_B + 134237853U, // ILVEV_D + 134239068U, // ILVEV_H + 134243143U, // ILVEV_W + 134235036U, // ILVL_B + 134236834U, // ILVL_D + 134238394U, // ILVL_H + 134242081U, // ILVL_W + 134234788U, // ILVOD_B + 134236307U, // ILVOD_D + 134238196U, // ILVOD_H + 134241666U, // ILVOD_W + 134235084U, // ILVR_B + 134237082U, // ILVR_D + 134238519U, // ILVR_H + 134242371U, // ILVR_W + 134243408U, // INS + 44582043U, // INSERT_B + 0U, // INSERT_B_VIDX_PSEUDO + 44584275U, // INSERT_D + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 44585551U, // INSERT_H + 0U, // INSERT_H_VIDX_PSEUDO + 44589573U, // INSERT_W + 0U, // INSERT_W_VIDX_PSEUDO + 16801009U, // INSV + 52970157U, // INSVE_B + 52971833U, // INSVE_D + 52973565U, // INSVE_H + 52977103U, // INSVE_W + 134243408U, // INS_MM + 546365U, // J + 546398U, // JAL + 22768U, // JALR + 547056U, // JALR16_MM + 22768U, // JALR64 + 0U, // JALR64Pseudo + 0U, // JALRPseudo + 541104U, // JALRS16_MM + 23442U, // JALRS_MM + 17822U, // JALR_HB + 22768U, // JALR_MM + 547706U, // JALS_MM + 549771U, // JALX + 549771U, // JALX_MM + 546398U, // JAL_MM + 18212U, // JIALC + 18201U, // JIC + 547052U, // JR + 541091U, // JR16_MM + 547052U, // JR64 + 546873U, // JRADDIUSP + 542610U, // JRC16_MM + 542103U, // JR_HB + 542103U, // JR_HB_R6 + 547052U, // JR_MM + 546365U, // J_MM + 2905694U, // Jal16 + 3167838U, // JalB16 + 546398U, // JalOneReg + 22110U, // JalTwoReg + 9430U, // JrRa16 + 9421U, // JrcRa16 + 549872U, // JrcRx16 + 540673U, // JumpLinkReg16 + 58738087U, // LB + 58738087U, // LB64 + 58737088U, // LBU16_MM + 1358979985U, // LBUX + 58738087U, // LB_MM + 58743769U, // LBu + 58743769U, // LBu64 + 58743769U, // LBu_MM + 58740538U, // LD + 58736688U, // LDC1 + 58736688U, // LDC164 + 58736688U, // LDC1_MM + 58736888U, // LDC2 + 58736888U, // LDC2_R6 + 58736947U, // LDC3 + 17103U, // LDI_B + 18857U, // LDI_D + 20511U, // LDI_H + 24146U, // LDI_W + 58742458U, // LDL + 18273U, // LDPC + 58742954U, // LDR + 1358970992U, // LDXC1 + 1358970992U, // LDXC164 + 58737301U, // LD_B + 58738820U, // LD_D + 58740709U, // LD_H + 58744179U, // LD_W + 25189403U, // LEA_ADDiu + 25189402U, // LEA_ADDiu64 + 25189403U, // LEA_ADDiu_MM + 58741643U, // LH + 58741643U, // LH64 + 58737111U, // LHU16_MM + 1358979974U, // LHX + 58741643U, // LH_MM + 58743822U, // LHu + 58743822U, // LHu64 + 58743822U, // LHu_MM + 16751U, // LI16_MM + 58742563U, // LL + 58740537U, // LLD + 58740537U, // LLD_R6 + 58742563U, // LL_MM + 58742563U, // LL_R6 + 58736647U, // LOAD_ACC128 + 58736647U, // LOAD_ACC64 + 58736647U, // LOAD_ACC64DSP + 58742794U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_LUi + 134234691U, // LSA + 134234691U, // LSA_R6 + 1358971006U, // LUXC1 + 1358971006U, // LUXC164 + 1358971006U, // LUXC1_MM + 33576504U, // LUi + 33576504U, // LUi64 + 33576504U, // LUi_MM + 58745726U, // LW + 58737118U, // LW16_MM + 58745726U, // LW64 + 58736740U, // LWC1 + 58736740U, // LWC1_MM + 58736914U, // LWC2 + 58736914U, // LWC2_R6 + 58736959U, // LWC3 + 58745726U, // LWGP_MM + 58742637U, // LWL + 58742637U, // LWL64 + 58742637U, // LWL_MM + 3522956U, // LWM16_MM + 3522785U, // LWM32_MM + 3528595U, // LWM_MM + 18310U, // LWPC + 137290U, // LWP_MM + 58743054U, // LWR + 58743054U, // LWR64 + 58743054U, // LWR_MM + 58745726U, // LWSP_MM + 18303U, // LWUPC + 58743912U, // LWU_MM + 1358979991U, // LWX + 1358971020U, // LWXC1 + 1358971020U, // LWXC1_MM + 1358977945U, // LWXS_MM + 58745726U, // LW_MM + 58743912U, // LWu + 58738087U, // LbRxRyOffMemX16 + 58743769U, // LbuRxRyOffMemX16 + 58741643U, // LhRxRyOffMemX16 + 58743822U, // LhuRxRyOffMemX16 + 939546111U, // LiRxImm16 + 22005U, // LiRxImmAlignX16 + 22015U, // LiRxImmX16 + 33571334U, // LoadAddr32Imm + 58737158U, // LoadAddr32Reg + 33576447U, // LoadImm32Reg + 22019U, // LoadImm64Reg + 3695486U, // LwConstant32 + 268460926U, // LwRxPcTcp16 + 25470U, // LwRxPcTcpX16 + 58745726U, // LwRxRyOffMemX16 + 1493197694U, // LwRxSpImmX16 + 20269U, // MADD + 151013751U, // MADDF_D + 151017921U, // MADDF_S + 151015667U, // MADDR_Q_H + 151019386U, // MADDR_Q_W + 23546U, // MADDU + 134241274U, // MADDU_DSP + 23546U, // MADDU_MM + 151012706U, // MADDV_B + 151015051U, // MADDV_D + 151016266U, // MADDV_H + 151020341U, // MADDV_W + 134236274U, // MADD_D32 + 134236274U, // MADD_D32_MM + 134236274U, // MADD_D64 + 134237997U, // MADD_DSP + 20269U, // MADD_MM + 151015637U, // MADD_Q_H + 151019356U, // MADD_Q_W + 134240571U, // MADD_S + 134240571U, // MADD_S_MM + 134239974U, // MAQ_SA_W_PHL + 134240436U, // MAQ_SA_W_PHR + 134240002U, // MAQ_S_W_PHL + 134240464U, // MAQ_S_W_PHR + 134236215U, // MAXA_D + 134240544U, // MAXA_S + 134235159U, // MAXI_S_B + 134237220U, // MAXI_S_D + 134238636U, // MAXI_S_H + 134242509U, // MAXI_S_W + 2281719022U, // MAXI_U_B + 2281721335U, // MAXI_U_D + 2281722572U, // MAXI_U_H + 2281726625U, // MAXI_U_W + 134234740U, // MAX_A_B + 134236191U, // MAX_A_D + 134238148U, // MAX_A_H + 134241575U, // MAX_A_W + 134237938U, // MAX_D + 134241111U, // MAX_S + 134235247U, // MAX_S_B + 134237340U, // MAX_S_D + 134238755U, // MAX_S_H + 134242690U, // MAX_S_W + 134235462U, // MAX_U_B + 134237807U, // MAX_U_D + 134239022U, // MAX_U_H + 134243097U, // MAX_U_W + 134234122U, // MFC0 + 16451U, // MFC1 + 16451U, // MFC1_MM + 134234373U, // MFC2 + 16457U, // MFHC1_D32 + 16457U, // MFHC1_D64 + 16457U, // MFHC1_MM + 546281U, // MFHI + 546281U, // MFHI16_MM + 546281U, // MFHI64 + 21993U, // MFHI_DSP + 546281U, // MFHI_MM + 546745U, // MFLO + 546745U, // MFLO16_MM + 546745U, // MFLO64 + 22457U, // MFLO_DSP + 546745U, // MFLO_MM + 134236200U, // MINA_D + 134240536U, // MINA_S + 134235139U, // MINI_S_B + 134237200U, // MINI_S_D + 134238616U, // MINI_S_H + 134242489U, // MINI_S_W + 2281719002U, // MINI_U_B + 2281721315U, // MINI_U_D + 2281722552U, // MINI_U_H + 2281726605U, // MINI_U_W + 134234721U, // MIN_A_B + 134236171U, // MIN_A_D + 134238129U, // MIN_A_H + 134241555U, // MIN_A_W + 134236843U, // MIN_D + 134240812U, // MIN_S + 134235169U, // MIN_S_B + 134237230U, // MIN_S_D + 134238646U, // MIN_S_H + 134242529U, // MIN_S_W + 134235384U, // MIN_U_B + 134237697U, // MIN_U_D + 134238934U, // MIN_U_H + 134242987U, // MIN_U_W + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 134238037U, // MOD + 134235899U, // MODSUB + 134241282U, // MODU + 134235102U, // MOD_S_B + 134237163U, // MOD_S_D + 134238579U, // MOD_S_H + 134242452U, // MOD_S_W + 134235317U, // MOD_U_B + 134237630U, // MOD_U_D + 134238867U, // MOD_U_H + 134242920U, // MOD_U_W + 20345U, // MOVE16_MM + 67491813U, // MOVEP_MM + 23668U, // MOVE_V + 134236560U, // MOVF_D32 + 134236560U, // MOVF_D32_MM + 134236560U, // MOVF_D64 + 134238109U, // MOVF_I + 134238109U, // MOVF_I64 + 134238109U, // MOVF_I_MM + 134240722U, // MOVF_S + 134240722U, // MOVF_S_MM + 134236895U, // MOVN_I64_D64 + 134240173U, // MOVN_I64_I + 134240173U, // MOVN_I64_I64 + 134240848U, // MOVN_I64_S + 134236895U, // MOVN_I_D32 + 134236895U, // MOVN_I_D32_MM + 134236895U, // MOVN_I_D64 + 134240173U, // MOVN_I_I + 134240173U, // MOVN_I_I64 + 134240173U, // MOVN_I_MM + 134240848U, // MOVN_I_S + 134240848U, // MOVN_I_S_MM + 134237558U, // MOVT_D32 + 134237558U, // MOVT_D32_MM + 134237558U, // MOVT_D64 + 134241235U, // MOVT_I + 134241235U, // MOVT_I64 + 134241235U, // MOVT_I_MM + 134241037U, // MOVT_S + 134241037U, // MOVT_S_MM + 134237978U, // MOVZ_I64_D64 + 134243300U, // MOVZ_I64_I + 134243300U, // MOVZ_I64_I64 + 134241138U, // MOVZ_I64_S + 134237978U, // MOVZ_I_D32 + 134237978U, // MOVZ_I_D32_MM + 134237978U, // MOVZ_I_D64 + 134243300U, // MOVZ_I_I + 134243300U, // MOVZ_I_I64 + 134243300U, // MOVZ_I_MM + 134241138U, // MOVZ_I_S + 134241138U, // MOVZ_I_S_MM + 18179U, // MSUB + 151013742U, // MSUBF_D + 151017912U, // MSUBF_S + 151015656U, // MSUBR_Q_H + 151019375U, // MSUBR_Q_W + 23525U, // MSUBU + 134241253U, // MSUBU_DSP + 23525U, // MSUBU_MM + 151012697U, // MSUBV_B + 151015042U, // MSUBV_D + 151016257U, // MSUBV_H + 151020332U, // MSUBV_W + 134236232U, // MSUB_D32 + 134236232U, // MSUB_D32_MM + 134236232U, // MSUB_D64 + 134235907U, // MSUB_DSP + 18179U, // MSUB_MM + 151015627U, // MSUB_Q_H + 151019346U, // MSUB_Q_W + 134240553U, // MSUB_S + 134240553U, // MSUB_S_MM + 134234129U, // MTC0 + 1867870U, // MTC1 + 1867870U, // MTC1_MM + 134234380U, // MTC2 + 1884240U, // MTHC1_D32 + 1884240U, // MTHC1_D64 + 1884240U, // MTHC1_MM + 546287U, // MTHI + 546287U, // MTHI64 + 1873391U, // MTHI_DSP + 546287U, // MTHI_MM + 1873900U, // MTHLIP + 546758U, // MTLO + 546758U, // MTLO64 + 1873862U, // MTLO_DSP + 546758U, // MTLO_MM + 540701U, // MTM0 + 540826U, // MTM1 + 540958U, // MTM2 + 540707U, // MTP0 + 540832U, // MTP1 + 540964U, // MTP2 + 134239672U, // MUH + 134241300U, // MUHU + 134240104U, // MUL + 134240015U, // MULEQ_S_W_PHL + 134240477U, // MULEQ_S_W_PHR + 134239883U, // MULEU_S_PH_QBL + 134240379U, // MULEU_S_PH_QBR + 134239433U, // MULQ_RS_PH + 134242709U, // MULQ_RS_W + 134239377U, // MULQ_S_PH + 134242568U, // MULQ_S_W + 134238462U, // MULR_Q_H + 134242181U, // MULR_Q_W + 134239579U, // MULSAQ_S_W_PH + 134239554U, // MULSA_W_PH + 23496U, // MULT + 134241370U, // MULTU_DSP + 134241224U, // MULT_DSP + 23496U, // MULT_MM + 23642U, // MULTu + 23642U, // MULTu_MM + 134241337U, // MULU + 134235517U, // MULV_B + 134237870U, // MULV_D + 134239077U, // MULV_H + 134243160U, // MULV_W + 134240104U, // MUL_MM + 134239250U, // MUL_PH + 134238431U, // MUL_Q_H + 134242150U, // MUL_Q_W + 134240104U, // MUL_R6 + 134239345U, // MUL_S_PH + 546281U, // Mfhi16 + 546745U, // Mflo16 + 20345U, // Move32R16 + 20345U, // MoveR3216 + 23496U, // MultRxRy16 + 75799496U, // MultRxRyRz16 + 23642U, // MultuRxRy16 + 75799642U, // MultuRxRyRz16 + 17028U, // NLOC_B + 18521U, // NLOC_D + 20436U, // NLOC_H + 23880U, // NLOC_W + 17036U, // NLZC_B + 18529U, // NLZC_D + 20444U, // NLZC_H + 23888U, // NLZC_W + 134236282U, // NMADD_D32 + 134236282U, // NMADD_D32_MM + 134236282U, // NMADD_D64 + 134240570U, // NMADD_S + 134240570U, // NMADD_S_MM + 134236240U, // NMSUB_D32 + 134236240U, // NMSUB_D32_MM + 134236240U, // NMSUB_D64 + 134240552U, // NMSUB_S + 134240552U, // NMSUB_S_MM + 0U, // NOP + 134240502U, // NOR + 134240502U, // NOR64 + 2281718573U, // NORI_B + 134240502U, // NOR_MM + 134241412U, // NOR_V + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 16825U, // NOT16_MM + 20387U, // NegRxRy16 + 23502U, // NotRxRy16 + 134240503U, // OR + 836010U, // OR16_MM + 134240503U, // OR64 + 2281718574U, // ORI_B + 134240503U, // OR_MM + 134241413U, // OR_V + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 134239771U, // ORi + 134239771U, // ORi64 + 134239771U, // ORi_MM + 16799991U, // OrRxRxRy16 + 134239239U, // PACKRL_PH + 9442U, // PAUSE + 9442U, // PAUSE_MM + 134235499U, // PCKEV_B + 134237844U, // PCKEV_D + 134239059U, // PCKEV_H + 134243134U, // PCKEV_W + 134234779U, // PCKOD_B + 134236298U, // PCKOD_D + 134238187U, // PCKOD_H + 134241657U, // PCKOD_W + 17555U, // PCNT_B + 19778U, // PCNT_D + 21063U, // PCNT_H + 25076U, // PCNT_W + 134239203U, // PICK_PH + 134235631U, // PICK_QB + 22522U, // POP + 22186U, // PRECEQU_PH_QBL + 16906U, // PRECEQU_PH_QBLA + 22682U, // PRECEQU_PH_QBR + 16939U, // PRECEQU_PH_QBRA + 22260U, // PRECEQ_W_PHL + 22722U, // PRECEQ_W_PHR + 22171U, // PRECEU_PH_QBL + 16890U, // PRECEU_PH_QBLA + 22667U, // PRECEU_PH_QBR + 16923U, // PRECEU_PH_QBRA + 134239155U, // PRECRQU_S_QB_PH + 134241800U, // PRECRQ_PH_W + 134239128U, // PRECRQ_QB_PH + 134241831U, // PRECRQ_RS_PH_W + 134239142U, // PRECR_QB_PH + 134241784U, // PRECR_SRA_PH_W + 134241813U, // PRECR_SRA_R_PH_W + 85911U, // PREF + 85911U, // PREF_MM + 85911U, // PREF_R6 + 134238019U, // PREPEND + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 16391U, // PseudoCVT_D32_W + 16391U, // PseudoCVT_D64_L + 16391U, // PseudoCVT_D64_W + 16391U, // PseudoCVT_S_L + 16391U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMULT + 0U, // PseudoMULTu + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 0U, // PseudoUDIV + 18155U, // RADDU_W_QB + 33577003U, // RDDSP + 22791U, // RDHWR + 22791U, // RDHWR64 + 22791U, // RDHWR_MM + 21766U, // REPLV_PH + 18135U, // REPLV_QB + 33575925U, // REPL_PH + 33572353U, // REPL_QB + 19787U, // RINT_D + 23293U, // RINT_S + 134240513U, // ROTR + 134241514U, // ROTRV + 134241514U, // ROTRV_MM + 134240513U, // ROTR_MM + 18992U, // ROUND_L_D64 + 23020U, // ROUND_L_S + 20168U, // ROUND_W_D32 + 20168U, // ROUND_W_D64 + 20168U, // ROUND_W_MM + 23342U, // ROUND_W_S + 23342U, // ROUND_W_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 0U, // RetRA + 0U, // RetRA16 + 134235208U, // SAT_S_B + 134237279U, // SAT_S_D + 2281722353U, // SAT_S_H + 134242618U, // SAT_S_W + 134235435U, // SAT_U_B + 134237758U, // SAT_U_D + 2281722643U, // SAT_U_H + 134243048U, // SAT_U_W + 58738423U, // SB + 58736980U, // SB16_MM + 58738423U, // SB64 + 58738423U, // SB_MM + 3966874U, // SC + 3968802U, // SCD + 3968802U, // SCD_R6 + 3966874U, // SC_MM + 3966874U, // SC_R6 + 58740570U, // SD + 546774U, // SDBBP + 65946U, // SDBBP16_MM + 546774U, // SDBBP_MM + 546774U, // SDBBP_R6 + 58736694U, // SDC1 + 58736694U, // SDC164 + 58736694U, // SDC1_MM + 58736894U, // SDC2 + 58736894U, // SDC2_R6 + 58736953U, // SDC3 + 25611U, // SDIV + 25611U, // SDIV_MM + 58742463U, // SDL + 58742959U, // SDR + 1358970999U, // SDXC1 + 1358970999U, // SDXC164 + 17810U, // SEB + 17810U, // SEB64 + 17810U, // SEB_MM + 21382U, // SEH + 21382U, // SEH64 + 21382U, // SEH_MM + 134243273U, // SELEQZ + 134243273U, // SELEQZ64 + 134237968U, // SELEQZ_D + 134241128U, // SELEQZ_S + 134243246U, // SELNEZ + 134243246U, // SELNEZ64 + 134237951U, // SELNEZ_D + 134241118U, // SELNEZ_S + 151013977U, // SEL_D + 151018005U, // SEL_S + 134240345U, // SEQ + 134239758U, // SEQi + 58742195U, // SH + 58736993U, // SH16_MM + 58742195U, // SH64 + 2281718455U, // SHF_B + 2281721863U, // SHF_H + 2281725417U, // SHF_W + 22463U, // SHILO + 23761U, // SHILOV + 134239484U, // SHLLV_PH + 134235853U, // SHLLV_QB + 134239421U, // SHLLV_S_PH + 134242679U, // SHLLV_S_W + 134239212U, // SHLL_PH + 134235640U, // SHLL_QB + 134239334U, // SHLL_S_PH + 134242519U, // SHLL_S_W + 134239474U, // SHRAV_PH + 134235843U, // SHRAV_QB + 134239322U, // SHRAV_R_PH + 134235741U, // SHRAV_R_QB + 134242274U, // SHRAV_R_W + 134239119U, // SHRA_PH + 134235563U, // SHRA_QB + 134239287U, // SHRA_R_PH + 134235706U, // SHRA_R_QB + 134242232U, // SHRA_R_W + 134239504U, // SHRLV_PH + 134235873U, // SHRLV_QB + 134239230U, // SHRL_PH + 134235658U, // SHRL_QB + 58742195U, // SH_MM + 2969584334U, // SLDI_B + 2969586088U, // SLDI_D + 2969587742U, // SLDI_H + 2969591377U, // SLDI_W + 822100628U, // SLD_B + 822102147U, // SLD_D + 822104036U, // SLD_H + 822107506U, // SLD_W + 134240058U, // SLL + 134234494U, // SLL16_MM + 1610635066U, // SLL64_32 + 1610635066U, // SLL64_64 + 2281718512U, // SLLI_B + 2281720249U, // SLLI_D + 2281721903U, // SLLI_H + 2281725538U, // SLLI_W + 134241476U, // SLLV + 134241476U, // SLLV_MM + 134235013U, // SLL_B + 134236785U, // SLL_D + 134238371U, // SLL_H + 134240058U, // SLL_MM + 134242032U, // SLL_W + 134241213U, // SLT + 134241213U, // SLT64 + 134241213U, // SLT_MM + 134239782U, // SLTi + 134239782U, // SLTi64 + 134239782U, // SLTi_MM + 134241321U, // SLTiu + 134241321U, // SLTiu64 + 134241321U, // SLTiu_MM + 134241357U, // SLTu + 134241357U, // SLTu64 + 134241357U, // SLTu_MM + 134238063U, // SNE + 134239703U, // SNEi + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 2952807239U, // SPLATI_B + 2952808960U, // SPLATI_D + 2952810614U, // SPLATI_H + 2952814249U, // SPLATI_W + 805323906U, // SPLAT_B + 805326016U, // SPLAT_D + 805327414U, // SPLAT_H + 805331393U, // SPLAT_W + 134234685U, // SRA + 2281718470U, // SRAI_B + 2281720224U, // SRAI_D + 2281721878U, // SRAI_H + 2281725513U, // SRAI_W + 134234898U, // SRARI_B + 134236635U, // SRARI_D + 2281721937U, // SRARI_H + 134241924U, // SRARI_W + 134235051U, // SRAR_B + 134237015U, // SRAR_D + 134238486U, // SRAR_H + 134242296U, // SRAR_W + 134241455U, // SRAV + 134241455U, // SRAV_MM + 134234749U, // SRA_B + 134236208U, // SRA_D + 134238157U, // SRA_H + 134234685U, // SRA_MM + 134241584U, // SRA_W + 134240070U, // SRL + 134234501U, // SRL16_MM + 2281718520U, // SRLI_B + 2281720257U, // SRLI_D + 2281721911U, // SRLI_H + 2281725546U, // SRLI_W + 134234916U, // SRLRI_B + 134236653U, // SRLRI_D + 2281721955U, // SRLRI_H + 134241942U, // SRLRI_W + 134235067U, // SRLR_B + 134237031U, // SRLR_D + 134238502U, // SRLR_H + 134242312U, // SRLR_W + 134241483U, // SRLV + 134241483U, // SRLV_MM + 134235020U, // SRL_B + 134236810U, // SRL_D + 134238378U, // SRL_H + 134240070U, // SRL_MM + 134242057U, // SRL_W + 9463U, // SSNOP + 9463U, // SSNOP_MM + 58736647U, // STORE_ACC128 + 58736647U, // STORE_ACC64 + 58736647U, // STORE_ACC64DSP + 58742810U, // STORE_CCOND_DSP + 58737829U, // ST_B + 58740080U, // ST_D + 58741337U, // ST_H + 58745378U, // ST_W + 134235902U, // SUB + 134239183U, // SUBQH_PH + 134239298U, // SUBQH_R_PH + 134242242U, // SUBQH_R_W + 134241847U, // SUBQH_W + 134239258U, // SUBQ_PH + 134239355U, // SUBQ_S_PH + 134242548U, // SUBQ_S_W + 134235423U, // SUBSUS_U_B + 134237746U, // SUBSUS_U_D + 134238983U, // SUBSUS_U_H + 134243036U, // SUBSUS_U_W + 134235226U, // SUBSUU_S_B + 134237319U, // SUBSUU_S_D + 134238723U, // SUBSUU_S_H + 134242658U, // SUBSUU_S_W + 134235188U, // SUBS_S_B + 134237259U, // SUBS_S_D + 134238685U, // SUBS_S_H + 134242598U, // SUBS_S_W + 134235403U, // SUBS_U_B + 134237726U, // SUBS_U_D + 134238963U, // SUBS_U_H + 134243016U, // SUBS_U_W + 134234567U, // SUBU16_MM + 134235611U, // SUBUH_QB + 134235717U, // SUBUH_R_QB + 134239456U, // SUBU_PH + 134235825U, // SUBU_QB + 134239399U, // SUBU_S_PH + 134235764U, // SUBU_S_QB + 2281718618U, // SUBVI_B + 2281720339U, // SUBVI_D + 2281721993U, // SUBVI_H + 2281725628U, // SUBVI_W + 134235482U, // SUBV_B + 134237827U, // SUBV_D + 134239042U, // SUBV_H + 134243117U, // SUBV_W + 134235902U, // SUB_MM + 134241247U, // SUBu + 134241247U, // SUBu_MM + 1358971013U, // SUXC1 + 1358971013U, // SUXC164 + 1358971013U, // SUXC1_MM + 58745730U, // SW + 58737124U, // SW16_MM + 58745730U, // SW64 + 58736746U, // SWC1 + 58736746U, // SWC1_MM + 58736920U, // SWC2 + 58736920U, // SWC2_R6 + 58736965U, // SWC3 + 58742642U, // SWL + 58742642U, // SWL64 + 58742642U, // SWL_MM + 3522963U, // SWM16_MM + 3522792U, // SWM32_MM + 3528600U, // SWM_MM + 137295U, // SWP_MM + 58743059U, // SWR + 58743059U, // SWR64 + 58743059U, // SWR_MM + 58745730U, // SWSP_MM + 1358971027U, // SWXC1 + 1358971027U, // SWXC1_MM + 58745730U, // SW_MM + 549939U, // SYNC + 153021U, // SYNCI + 549939U, // SYNC_MM + 546590U, // SYSCALL + 546590U, // SYSCALL_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 0U, // Save16 + 0U, // SaveX16 + 58738423U, // SbRxRyOffMemX16 + 549866U, // SebRx16 + 549878U, // SehRx16 + 4367299U, // SelBeqZ + 4367272U, // SelBneZ + 1828886516U, // SelTBteqZCmp + 1828886024U, // SelTBteqZCmpi + 1828887485U, // SelTBteqZSlt + 1828886054U, // SelTBteqZSlti + 1828887593U, // SelTBteqZSltiu + 1828887629U, // SelTBteqZSltu + 1963104244U, // SelTBtneZCmp + 1963103752U, // SelTBtneZCmpi + 1963105213U, // SelTBtneZSlt + 1963103782U, // SelTBtneZSlti + 1963105321U, // SelTBtneZSltiu + 1963105357U, // SelTBtneZSltu + 58742195U, // ShRxRyOffMemX16 + 134240058U, // SllX16 + 16800964U, // SllvRxRy16 + 92576701U, // SltCCRxRy16 + 23485U, // SltRxRy16 + 92575270U, // SltiCCRxImmX16 + 939546150U, // SltiRxImm16 + 22054U, // SltiRxImmX16 + 92576809U, // SltiuCCRxImmX16 + 939547689U, // SltiuRxImm16 + 23593U, // SltiuRxImmX16 + 92576845U, // SltuCCRxRy16 + 23629U, // SltuRxRy16 + 92576845U, // SltuRxRyRz16 + 134234685U, // SraX16 + 16800943U, // SravRxRy16 + 134240070U, // SrlX16 + 16800971U, // SrlvRxRy16 + 134241247U, // SubuRxRyRz16 + 58745730U, // SwRxRyOffMemX16 + 1493197698U, // SwRxSpImmX16 + 0U, // TAILCALL + 0U, // TAILCALL64_R + 0U, // TAILCALL_R + 134240350U, // TEQ + 33576468U, // TEQI + 33576468U, // TEQI_MM + 134240350U, // TEQ_MM + 134238046U, // TGE + 33576401U, // TGEI + 33578018U, // TGEIU + 33578018U, // TGEIU_MM + 33576401U, // TGEI_MM + 134241288U, // TGEU + 134241288U, // TGEU_MM + 134238046U, // TGE_MM + 9458U, // TLBP + 9458U, // TLBP_MM + 9469U, // TLBR + 9469U, // TLBR_MM + 9448U, // TLBWI + 9448U, // TLBWI_MM + 9474U, // TLBWR + 9474U, // TLBWR_MM + 134241218U, // TLT + 33576492U, // TLTI + 33578032U, // TLTIU_MM + 33576492U, // TLTI_MM + 134241363U, // TLTU + 134241363U, // TLTU_MM + 134241218U, // TLT_MM + 134238068U, // TNE + 33576413U, // TNEI + 33576413U, // TNEI_MM + 134238068U, // TNE_MM + 0U, // TRAP + 18981U, // TRUNC_L_D64 + 23009U, // TRUNC_L_S + 20157U, // TRUNC_W_D32 + 20157U, // TRUNC_W_D64 + 20157U, // TRUNC_W_MM + 23331U, // TRUNC_W_S + 23331U, // TRUNC_W_S_MM + 33578032U, // TTLTIU + 25597U, // UDIV + 25597U, // UDIV_MM + 134241335U, // V3MULU + 134234135U, // VMM0 + 134241350U, // VMULU + 151012022U, // VSHF_B + 151013760U, // VSHF_D + 151015430U, // VSHF_H + 151018984U, // VSHF_W + 9486U, // WAIT + 547767U, // WAIT_MM + 33577010U, // WRDSP + 21376U, // WSBH + 21376U, // WSBH_MM + 134240507U, // XOR + 836009U, // XOR16_MM + 134240507U, // XOR64 + 2281718581U, // XORI_B + 134240507U, // XOR_MM + 134241419U, // XOR_V + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 134239770U, // XORi + 134239770U, // XORi64 + 134239770U, // XORi_MM + 16799995U, // XorRxRxRy16 + 0U}; - static const uint8_t OpInfo2[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 0U, // DBG_VALUE - 0U, // REG_SEQUENCE - 0U, // COPY - 0U, // BUNDLE - 0U, // LIFETIME_START - 0U, // LIFETIME_END - 0U, // STACKMAP - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 0U, // ABSQ_S_PH - 0U, // ABSQ_S_QB - 0U, // ABSQ_S_W - 0U, // ADD - 0U, // ADDIUPC - 0U, // ADDIUPC_MM - 0U, // ADDIUR1SP_MM - 0U, // ADDIUR2_MM - 0U, // ADDIUS5_MM - 0U, // ADDIUSP_MM - 0U, // ADDQH_PH - 0U, // ADDQH_R_PH - 0U, // ADDQH_R_W - 0U, // ADDQH_W - 0U, // ADDQ_PH - 0U, // ADDQ_S_PH - 0U, // ADDQ_S_W - 0U, // ADDSC - 0U, // ADDS_A_B - 0U, // ADDS_A_D - 0U, // ADDS_A_H - 0U, // ADDS_A_W - 0U, // ADDS_S_B - 0U, // ADDS_S_D - 0U, // ADDS_S_H - 0U, // ADDS_S_W - 0U, // ADDS_U_B - 0U, // ADDS_U_D - 0U, // ADDS_U_H - 0U, // ADDS_U_W - 0U, // ADDU16_MM - 0U, // ADDUH_QB - 0U, // ADDUH_R_QB - 0U, // ADDU_PH - 0U, // ADDU_QB - 0U, // ADDU_S_PH - 0U, // ADDU_S_QB - 0U, // ADDVI_B - 0U, // ADDVI_D - 0U, // ADDVI_H - 0U, // ADDVI_W - 0U, // ADDV_B - 0U, // ADDV_D - 0U, // ADDV_H - 0U, // ADDV_W - 0U, // ADDWC - 0U, // ADD_A_B - 0U, // ADD_A_D - 0U, // ADD_A_H - 0U, // ADD_A_W - 0U, // ADD_MM - 0U, // ADDi - 0U, // ADDi_MM - 0U, // ADDiu - 0U, // ADDiu_MM - 0U, // ADDu - 0U, // ADDu_MM - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 4U, // ALIGN - 0U, // ALUIPC - 0U, // AND - 0U, // AND16_MM - 0U, // AND64 - 0U, // ANDI16_MM - 0U, // ANDI_B - 0U, // AND_MM - 0U, // AND_V - 0U, // AND_V_D_PSEUDO - 0U, // AND_V_H_PSEUDO - 0U, // AND_V_W_PSEUDO - 1U, // ANDi - 1U, // ANDi64 - 1U, // ANDi_MM - 1U, // APPEND - 0U, // ASUB_S_B - 0U, // ASUB_S_D - 0U, // ASUB_S_H - 0U, // ASUB_S_W - 0U, // ASUB_U_B - 0U, // ASUB_U_D - 0U, // ASUB_U_H - 0U, // ASUB_U_W - 0U, // ATOMIC_CMP_SWAP_I16 - 0U, // ATOMIC_CMP_SWAP_I32 - 0U, // ATOMIC_CMP_SWAP_I64 - 0U, // ATOMIC_CMP_SWAP_I8 - 0U, // ATOMIC_LOAD_ADD_I16 - 0U, // ATOMIC_LOAD_ADD_I32 - 0U, // ATOMIC_LOAD_ADD_I64 - 0U, // ATOMIC_LOAD_ADD_I8 - 0U, // ATOMIC_LOAD_AND_I16 - 0U, // ATOMIC_LOAD_AND_I32 - 0U, // ATOMIC_LOAD_AND_I64 - 0U, // ATOMIC_LOAD_AND_I8 - 0U, // ATOMIC_LOAD_NAND_I16 - 0U, // ATOMIC_LOAD_NAND_I32 - 0U, // ATOMIC_LOAD_NAND_I64 - 0U, // ATOMIC_LOAD_NAND_I8 - 0U, // ATOMIC_LOAD_OR_I16 - 0U, // ATOMIC_LOAD_OR_I32 - 0U, // ATOMIC_LOAD_OR_I64 - 0U, // ATOMIC_LOAD_OR_I8 - 0U, // ATOMIC_LOAD_SUB_I16 - 0U, // ATOMIC_LOAD_SUB_I32 - 0U, // ATOMIC_LOAD_SUB_I64 - 0U, // ATOMIC_LOAD_SUB_I8 - 0U, // ATOMIC_LOAD_XOR_I16 - 0U, // ATOMIC_LOAD_XOR_I32 - 0U, // ATOMIC_LOAD_XOR_I64 - 0U, // ATOMIC_LOAD_XOR_I8 - 0U, // ATOMIC_SWAP_I16 - 0U, // ATOMIC_SWAP_I32 - 0U, // ATOMIC_SWAP_I64 - 0U, // ATOMIC_SWAP_I8 - 0U, // AUI - 0U, // AUIPC - 0U, // AVER_S_B - 0U, // AVER_S_D - 0U, // AVER_S_H - 0U, // AVER_S_W - 0U, // AVER_U_B - 0U, // AVER_U_D - 0U, // AVER_U_H - 0U, // AVER_U_W - 0U, // AVE_S_B - 0U, // AVE_S_D - 0U, // AVE_S_H - 0U, // AVE_S_W - 0U, // AVE_U_B - 0U, // AVE_U_D - 0U, // AVE_U_H - 0U, // AVE_U_W - 0U, // AddiuRxImmX16 - 0U, // AddiuRxPcImmX16 - 0U, // AddiuRxRxImm16 - 0U, // AddiuRxRxImmX16 - 0U, // AddiuRxRyOffMemX16 - 0U, // AddiuSpImm16 - 0U, // AddiuSpImmX16 - 0U, // AdduRxRyRz16 - 0U, // AndRxRxRy16 - 0U, // B - 0U, // B16_MM - 0U, // BADDu - 0U, // BAL - 0U, // BALC - 1U, // BALIGN - 0U, // BAL_BR - 0U, // BBIT0 - 0U, // BBIT032 - 0U, // BBIT1 - 0U, // BBIT132 - 0U, // BC - 0U, // BC0F - 0U, // BC0FL - 0U, // BC0T - 0U, // BC0TL - 0U, // BC1EQZ - 0U, // BC1F - 0U, // BC1FL - 0U, // BC1F_MM - 0U, // BC1NEZ - 0U, // BC1T - 0U, // BC1TL - 0U, // BC1T_MM - 0U, // BC2EQZ - 0U, // BC2F - 0U, // BC2FL - 0U, // BC2NEZ - 0U, // BC2T - 0U, // BC2TL - 0U, // BC3F - 0U, // BC3FL - 0U, // BC3T - 0U, // BC3TL - 0U, // BCLRI_B - 0U, // BCLRI_D - 0U, // BCLRI_H - 0U, // BCLRI_W - 0U, // BCLR_B - 0U, // BCLR_D - 0U, // BCLR_H - 0U, // BCLR_W - 0U, // BEQ - 0U, // BEQ64 - 0U, // BEQC - 0U, // BEQL - 0U, // BEQZ16_MM - 0U, // BEQZALC - 0U, // BEQZC - 0U, // BEQZC_MM - 0U, // BEQ_MM - 0U, // BGEC - 0U, // BGEUC - 0U, // BGEZ - 0U, // BGEZ64 - 0U, // BGEZAL - 0U, // BGEZALC - 0U, // BGEZALL - 0U, // BGEZALS_MM - 0U, // BGEZAL_MM - 0U, // BGEZC - 0U, // BGEZL - 0U, // BGEZ_MM - 0U, // BGTZ - 0U, // BGTZ64 - 0U, // BGTZALC - 0U, // BGTZC - 0U, // BGTZL - 0U, // BGTZ_MM - 1U, // BINSLI_B - 1U, // BINSLI_D - 1U, // BINSLI_H - 1U, // BINSLI_W - 2U, // BINSL_B - 2U, // BINSL_D - 2U, // BINSL_H - 2U, // BINSL_W - 1U, // BINSRI_B - 1U, // BINSRI_D - 1U, // BINSRI_H - 1U, // BINSRI_W - 2U, // BINSR_B - 2U, // BINSR_D - 2U, // BINSR_H - 2U, // BINSR_W - 0U, // BITREV - 0U, // BITSWAP - 0U, // BLEZ - 0U, // BLEZ64 - 0U, // BLEZALC - 0U, // BLEZC - 0U, // BLEZL - 0U, // BLEZ_MM - 0U, // BLTC - 0U, // BLTUC - 0U, // BLTZ - 0U, // BLTZ64 - 0U, // BLTZAL - 0U, // BLTZALC - 0U, // BLTZALL - 0U, // BLTZALS_MM - 0U, // BLTZAL_MM - 0U, // BLTZC - 0U, // BLTZL - 0U, // BLTZ_MM - 1U, // BMNZI_B - 2U, // BMNZ_V - 1U, // BMZI_B - 2U, // BMZ_V - 0U, // BNE - 0U, // BNE64 - 0U, // BNEC - 0U, // BNEGI_B - 0U, // BNEGI_D - 0U, // BNEGI_H - 0U, // BNEGI_W - 0U, // BNEG_B - 0U, // BNEG_D - 0U, // BNEG_H - 0U, // BNEG_W - 0U, // BNEL - 0U, // BNEZ16_MM - 0U, // BNEZALC - 0U, // BNEZC - 0U, // BNEZC_MM - 0U, // BNE_MM - 0U, // BNVC - 0U, // BNZ_B - 0U, // BNZ_D - 0U, // BNZ_H - 0U, // BNZ_V - 0U, // BNZ_W - 0U, // BOVC - 0U, // BPOSGE32 - 0U, // BPOSGE32_PSEUDO - 0U, // BREAK - 0U, // BREAK16_MM - 0U, // BREAK_MM - 1U, // BSELI_B - 0U, // BSEL_D_PSEUDO - 0U, // BSEL_FD_PSEUDO - 0U, // BSEL_FW_PSEUDO - 0U, // BSEL_H_PSEUDO - 2U, // BSEL_V - 0U, // BSEL_W_PSEUDO - 0U, // BSETI_B - 0U, // BSETI_D - 0U, // BSETI_H - 0U, // BSETI_W - 0U, // BSET_B - 0U, // BSET_D - 0U, // BSET_H - 0U, // BSET_W - 0U, // BZ_B - 0U, // BZ_D - 0U, // BZ_H - 0U, // BZ_V - 0U, // BZ_W - 0U, // B_MM_Pseudo - 0U, // BeqzRxImm16 - 0U, // BeqzRxImmX16 - 0U, // Bimm16 - 0U, // BimmX16 - 0U, // BnezRxImm16 - 0U, // BnezRxImmX16 - 0U, // Break16 - 0U, // Bteqz16 - 0U, // BteqzT8CmpX16 - 0U, // BteqzT8CmpiX16 - 0U, // BteqzT8SltX16 - 0U, // BteqzT8SltiX16 - 0U, // BteqzT8SltiuX16 - 0U, // BteqzT8SltuX16 - 0U, // BteqzX16 - 0U, // Btnez16 - 0U, // BtnezT8CmpX16 - 0U, // BtnezT8CmpiX16 - 0U, // BtnezT8SltX16 - 0U, // BtnezT8SltiX16 - 0U, // BtnezT8SltiuX16 - 0U, // BtnezT8SltuX16 - 0U, // BtnezX16 - 0U, // BuildPairF64 - 0U, // BuildPairF64_64 - 0U, // CACHE - 0U, // CACHE_MM - 0U, // CACHE_R6 - 0U, // CEIL_L_D64 - 0U, // CEIL_L_S - 0U, // CEIL_W_D32 - 0U, // CEIL_W_D64 - 0U, // CEIL_W_MM - 0U, // CEIL_W_S - 0U, // CEIL_W_S_MM - 0U, // CEQI_B - 0U, // CEQI_D - 0U, // CEQI_H - 0U, // CEQI_W - 0U, // CEQ_B - 0U, // CEQ_D - 0U, // CEQ_H - 0U, // CEQ_W - 0U, // CFC1 - 0U, // CFC1_MM - 0U, // CFCMSA - 5U, // CINS - 5U, // CINS32 - 0U, // CLASS_D - 0U, // CLASS_S - 0U, // CLEI_S_B - 0U, // CLEI_S_D - 0U, // CLEI_S_H - 0U, // CLEI_S_W - 0U, // CLEI_U_B - 0U, // CLEI_U_D - 0U, // CLEI_U_H - 0U, // CLEI_U_W - 0U, // CLE_S_B - 0U, // CLE_S_D - 0U, // CLE_S_H - 0U, // CLE_S_W - 0U, // CLE_U_B - 0U, // CLE_U_D - 0U, // CLE_U_H - 0U, // CLE_U_W - 0U, // CLO - 0U, // CLO_MM - 0U, // CLO_R6 - 0U, // CLTI_S_B - 0U, // CLTI_S_D - 0U, // CLTI_S_H - 0U, // CLTI_S_W - 0U, // CLTI_U_B - 0U, // CLTI_U_D - 0U, // CLTI_U_H - 0U, // CLTI_U_W - 0U, // CLT_S_B - 0U, // CLT_S_D - 0U, // CLT_S_H - 0U, // CLT_S_W - 0U, // CLT_U_B - 0U, // CLT_U_D - 0U, // CLT_U_H - 0U, // CLT_U_W - 0U, // CLZ - 0U, // CLZ_MM - 0U, // CLZ_R6 - 0U, // CMPGDU_EQ_QB - 0U, // CMPGDU_LE_QB - 0U, // CMPGDU_LT_QB - 0U, // CMPGU_EQ_QB - 0U, // CMPGU_LE_QB - 0U, // CMPGU_LT_QB - 0U, // CMPU_EQ_QB - 0U, // CMPU_LE_QB - 0U, // CMPU_LT_QB - 0U, // CMP_EQ_D - 0U, // CMP_EQ_PH - 0U, // CMP_EQ_S - 0U, // CMP_F_D - 0U, // CMP_F_S - 0U, // CMP_LE_D - 0U, // CMP_LE_PH - 0U, // CMP_LE_S - 0U, // CMP_LT_D - 0U, // CMP_LT_PH - 0U, // CMP_LT_S - 0U, // CMP_SAF_D - 0U, // CMP_SAF_S - 0U, // CMP_SEQ_D - 0U, // CMP_SEQ_S - 0U, // CMP_SLE_D - 0U, // CMP_SLE_S - 0U, // CMP_SLT_D - 0U, // CMP_SLT_S - 0U, // CMP_SUEQ_D - 0U, // CMP_SUEQ_S - 0U, // CMP_SULE_D - 0U, // CMP_SULE_S - 0U, // CMP_SULT_D - 0U, // CMP_SULT_S - 0U, // CMP_SUN_D - 0U, // CMP_SUN_S - 0U, // CMP_UEQ_D - 0U, // CMP_UEQ_S - 0U, // CMP_ULE_D - 0U, // CMP_ULE_S - 0U, // CMP_ULT_D - 0U, // CMP_ULT_S - 0U, // CMP_UN_D - 0U, // CMP_UN_S - 0U, // CONSTPOOL_ENTRY - 0U, // COPY_FD_PSEUDO - 0U, // COPY_FW_PSEUDO - 8U, // COPY_S_B - 8U, // COPY_S_D - 8U, // COPY_S_H - 8U, // COPY_S_W - 8U, // COPY_U_B - 8U, // COPY_U_D - 8U, // COPY_U_H - 8U, // COPY_U_W - 0U, // CTC1 - 0U, // CTC1_MM - 0U, // CTCMSA - 0U, // CVT_D32_S - 0U, // CVT_D32_W - 0U, // CVT_D32_W_MM - 0U, // CVT_D64_L - 0U, // CVT_D64_S - 0U, // CVT_D64_W - 0U, // CVT_D_S_MM - 0U, // CVT_L_D64 - 0U, // CVT_L_D64_MM - 0U, // CVT_L_S - 0U, // CVT_L_S_MM - 0U, // CVT_S_D32 - 0U, // CVT_S_D32_MM - 0U, // CVT_S_D64 - 0U, // CVT_S_L - 0U, // CVT_S_W - 0U, // CVT_S_W_MM - 0U, // CVT_W_D32 - 0U, // CVT_W_D64 - 0U, // CVT_W_MM - 0U, // CVT_W_S - 0U, // CVT_W_S_MM - 0U, // C_EQ_D32 - 0U, // C_EQ_D64 - 0U, // C_EQ_S - 0U, // C_F_D32 - 0U, // C_F_D64 - 0U, // C_F_S - 0U, // C_LE_D32 - 0U, // C_LE_D64 - 0U, // C_LE_S - 0U, // C_LT_D32 - 0U, // C_LT_D64 - 0U, // C_LT_S - 0U, // C_NGE_D32 - 0U, // C_NGE_D64 - 0U, // C_NGE_S - 0U, // C_NGLE_D32 - 0U, // C_NGLE_D64 - 0U, // C_NGLE_S - 0U, // C_NGL_D32 - 0U, // C_NGL_D64 - 0U, // C_NGL_S - 0U, // C_NGT_D32 - 0U, // C_NGT_D64 - 0U, // C_NGT_S - 0U, // C_OLE_D32 - 0U, // C_OLE_D64 - 0U, // C_OLE_S - 0U, // C_OLT_D32 - 0U, // C_OLT_D64 - 0U, // C_OLT_S - 0U, // C_SEQ_D32 - 0U, // C_SEQ_D64 - 0U, // C_SEQ_S - 0U, // C_SF_D32 - 0U, // C_SF_D64 - 0U, // C_SF_S - 0U, // C_UEQ_D32 - 0U, // C_UEQ_D64 - 0U, // C_UEQ_S - 0U, // C_ULE_D32 - 0U, // C_ULE_D64 - 0U, // C_ULE_S - 0U, // C_ULT_D32 - 0U, // C_ULT_D64 - 0U, // C_ULT_S - 0U, // C_UN_D32 - 0U, // C_UN_D64 - 0U, // C_UN_S - 0U, // CmpRxRy16 - 0U, // CmpiRxImm16 - 0U, // CmpiRxImmX16 - 0U, // Constant32 - 0U, // DADD - 0U, // DADDi - 0U, // DADDiu - 0U, // DADDu - 0U, // DAHI - 4U, // DALIGN - 0U, // DATI - 0U, // DAUI - 0U, // DBITSWAP - 0U, // DCLO - 0U, // DCLO_R6 - 0U, // DCLZ - 0U, // DCLZ_R6 - 0U, // DDIV - 0U, // DDIVU - 0U, // DERET - 0U, // DERET_MM - 21U, // DEXT - 21U, // DEXTM - 21U, // DEXTU - 0U, // DI - 21U, // DINS - 21U, // DINSM - 21U, // DINSU - 0U, // DIV - 0U, // DIVU - 0U, // DIV_S_B - 0U, // DIV_S_D - 0U, // DIV_S_H - 0U, // DIV_S_W - 0U, // DIV_U_B - 0U, // DIV_U_D - 0U, // DIV_U_H - 0U, // DIV_U_W - 0U, // DI_MM - 4U, // DLSA - 4U, // DLSA_R6 - 1U, // DMFC0 - 0U, // DMFC1 - 1U, // DMFC2 - 0U, // DMOD - 0U, // DMODU - 1U, // DMTC0 - 0U, // DMTC1 - 1U, // DMTC2 - 0U, // DMUH - 0U, // DMUHU - 0U, // DMUL - 0U, // DMULT - 0U, // DMULTu - 0U, // DMULU - 0U, // DMUL_R6 - 0U, // DOTP_S_D - 0U, // DOTP_S_H - 0U, // DOTP_S_W - 0U, // DOTP_U_D - 0U, // DOTP_U_H - 0U, // DOTP_U_W - 2U, // DPADD_S_D - 2U, // DPADD_S_H - 2U, // DPADD_S_W - 2U, // DPADD_U_D - 2U, // DPADD_U_H - 2U, // DPADD_U_W - 0U, // DPAQX_SA_W_PH - 0U, // DPAQX_S_W_PH - 0U, // DPAQ_SA_L_W - 0U, // DPAQ_S_W_PH - 0U, // DPAU_H_QBL - 0U, // DPAU_H_QBR - 0U, // DPAX_W_PH - 0U, // DPA_W_PH - 0U, // DPOP - 0U, // DPSQX_SA_W_PH - 0U, // DPSQX_S_W_PH - 0U, // DPSQ_SA_L_W - 0U, // DPSQ_S_W_PH - 2U, // DPSUB_S_D - 2U, // DPSUB_S_H - 2U, // DPSUB_S_W - 2U, // DPSUB_U_D - 2U, // DPSUB_U_H - 2U, // DPSUB_U_W - 0U, // DPSU_H_QBL - 0U, // DPSU_H_QBR - 0U, // DPSX_W_PH - 0U, // DPS_W_PH - 1U, // DROTR - 1U, // DROTR32 - 0U, // DROTRV - 0U, // DSBH - 0U, // DSDIV - 0U, // DSHD - 1U, // DSLL - 1U, // DSLL32 - 0U, // DSLL64_32 - 0U, // DSLLV - 1U, // DSRA - 1U, // DSRA32 - 0U, // DSRAV - 1U, // DSRL - 1U, // DSRL32 - 0U, // DSRLV - 0U, // DSUB - 0U, // DSUBu - 0U, // DUDIV - 0U, // DivRxRy16 - 0U, // DivuRxRy16 - 0U, // EHB - 0U, // EHB_MM - 0U, // EI - 0U, // EI_MM - 0U, // ERET - 0U, // ERET_MM - 21U, // EXT - 1U, // EXTP - 1U, // EXTPDP - 0U, // EXTPDPV - 0U, // EXTPV - 0U, // EXTRV_RS_W - 0U, // EXTRV_R_W - 0U, // EXTRV_S_H - 0U, // EXTRV_W - 1U, // EXTR_RS_W - 1U, // EXTR_R_W - 1U, // EXTR_S_H - 1U, // EXTR_W - 5U, // EXTS - 5U, // EXTS32 - 21U, // EXT_MM - 0U, // ExtractElementF64 - 0U, // ExtractElementF64_64 - 0U, // FABS_D - 0U, // FABS_D32 - 0U, // FABS_D64 - 0U, // FABS_MM - 0U, // FABS_S - 0U, // FABS_S_MM - 0U, // FABS_W - 0U, // FADD_D - 0U, // FADD_D32 - 0U, // FADD_D64 - 0U, // FADD_MM - 0U, // FADD_S - 0U, // FADD_S_MM - 0U, // FADD_W - 0U, // FCAF_D - 0U, // FCAF_W - 0U, // FCEQ_D - 0U, // FCEQ_W - 0U, // FCLASS_D - 0U, // FCLASS_W - 0U, // FCLE_D - 0U, // FCLE_W - 0U, // FCLT_D - 0U, // FCLT_W - 0U, // FCMP_D32 - 0U, // FCMP_D32_MM - 0U, // FCMP_D64 - 0U, // FCMP_S32 - 0U, // FCMP_S32_MM - 0U, // FCNE_D - 0U, // FCNE_W - 0U, // FCOR_D - 0U, // FCOR_W - 0U, // FCUEQ_D - 0U, // FCUEQ_W - 0U, // FCULE_D - 0U, // FCULE_W - 0U, // FCULT_D - 0U, // FCULT_W - 0U, // FCUNE_D - 0U, // FCUNE_W - 0U, // FCUN_D - 0U, // FCUN_W - 0U, // FDIV_D - 0U, // FDIV_D32 - 0U, // FDIV_D64 - 0U, // FDIV_MM - 0U, // FDIV_S - 0U, // FDIV_S_MM - 0U, // FDIV_W - 0U, // FEXDO_H - 0U, // FEXDO_W - 0U, // FEXP2_D - 0U, // FEXP2_D_1_PSEUDO - 0U, // FEXP2_W - 0U, // FEXP2_W_1_PSEUDO - 0U, // FEXUPL_D - 0U, // FEXUPL_W - 0U, // FEXUPR_D - 0U, // FEXUPR_W - 0U, // FFINT_S_D - 0U, // FFINT_S_W - 0U, // FFINT_U_D - 0U, // FFINT_U_W - 0U, // FFQL_D - 0U, // FFQL_W - 0U, // FFQR_D - 0U, // FFQR_W - 0U, // FILL_B - 0U, // FILL_D - 0U, // FILL_FD_PSEUDO - 0U, // FILL_FW_PSEUDO - 0U, // FILL_H - 0U, // FILL_W - 0U, // FLOG2_D - 0U, // FLOG2_W - 0U, // FLOOR_L_D64 - 0U, // FLOOR_L_S - 0U, // FLOOR_W_D32 - 0U, // FLOOR_W_D64 - 0U, // FLOOR_W_MM - 0U, // FLOOR_W_S - 0U, // FLOOR_W_S_MM - 2U, // FMADD_D - 2U, // FMADD_W - 0U, // FMAX_A_D - 0U, // FMAX_A_W - 0U, // FMAX_D - 0U, // FMAX_W - 0U, // FMIN_A_D - 0U, // FMIN_A_W - 0U, // FMIN_D - 0U, // FMIN_W - 0U, // FMOV_D32 - 0U, // FMOV_D32_MM - 0U, // FMOV_D64 - 0U, // FMOV_S - 0U, // FMOV_S_MM - 2U, // FMSUB_D - 2U, // FMSUB_W - 0U, // FMUL_D - 0U, // FMUL_D32 - 0U, // FMUL_D64 - 0U, // FMUL_MM - 0U, // FMUL_S - 0U, // FMUL_S_MM - 0U, // FMUL_W - 0U, // FNEG_D32 - 0U, // FNEG_D64 - 0U, // FNEG_MM - 0U, // FNEG_S - 0U, // FNEG_S_MM - 0U, // FRCP_D - 0U, // FRCP_W - 0U, // FRINT_D - 0U, // FRINT_W - 0U, // FRSQRT_D - 0U, // FRSQRT_W - 0U, // FSAF_D - 0U, // FSAF_W - 0U, // FSEQ_D - 0U, // FSEQ_W - 0U, // FSLE_D - 0U, // FSLE_W - 0U, // FSLT_D - 0U, // FSLT_W - 0U, // FSNE_D - 0U, // FSNE_W - 0U, // FSOR_D - 0U, // FSOR_W - 0U, // FSQRT_D - 0U, // FSQRT_D32 - 0U, // FSQRT_D64 - 0U, // FSQRT_MM - 0U, // FSQRT_S - 0U, // FSQRT_S_MM - 0U, // FSQRT_W - 0U, // FSUB_D - 0U, // FSUB_D32 - 0U, // FSUB_D64 - 0U, // FSUB_MM - 0U, // FSUB_S - 0U, // FSUB_S_MM - 0U, // FSUB_W - 0U, // FSUEQ_D - 0U, // FSUEQ_W - 0U, // FSULE_D - 0U, // FSULE_W - 0U, // FSULT_D - 0U, // FSULT_W - 0U, // FSUNE_D - 0U, // FSUNE_W - 0U, // FSUN_D - 0U, // FSUN_W - 0U, // FTINT_S_D - 0U, // FTINT_S_W - 0U, // FTINT_U_D - 0U, // FTINT_U_W - 0U, // FTQ_H - 0U, // FTQ_W - 0U, // FTRUNC_S_D - 0U, // FTRUNC_S_W - 0U, // FTRUNC_U_D - 0U, // FTRUNC_U_W - 0U, // GotPrologue16 - 0U, // HADD_S_D - 0U, // HADD_S_H - 0U, // HADD_S_W - 0U, // HADD_U_D - 0U, // HADD_U_H - 0U, // HADD_U_W - 0U, // HSUB_S_D - 0U, // HSUB_S_H - 0U, // HSUB_S_W - 0U, // HSUB_U_D - 0U, // HSUB_U_H - 0U, // HSUB_U_W - 0U, // ILVEV_B - 0U, // ILVEV_D - 0U, // ILVEV_H - 0U, // ILVEV_W - 0U, // ILVL_B - 0U, // ILVL_D - 0U, // ILVL_H - 0U, // ILVL_W - 0U, // ILVOD_B - 0U, // ILVOD_D - 0U, // ILVOD_H - 0U, // ILVOD_W - 0U, // ILVR_B - 0U, // ILVR_D - 0U, // ILVR_H - 0U, // ILVR_W - 21U, // INS - 0U, // INSERT_B - 0U, // INSERT_B_VIDX_PSEUDO - 0U, // INSERT_D - 0U, // INSERT_D_VIDX_PSEUDO - 0U, // INSERT_FD_PSEUDO - 0U, // INSERT_FD_VIDX_PSEUDO - 0U, // INSERT_FW_PSEUDO - 0U, // INSERT_FW_VIDX_PSEUDO - 0U, // INSERT_H - 0U, // INSERT_H_VIDX_PSEUDO - 0U, // INSERT_W - 0U, // INSERT_W_VIDX_PSEUDO - 0U, // INSV - 0U, // INSVE_B - 0U, // INSVE_D - 0U, // INSVE_H - 0U, // INSVE_W - 21U, // INS_MM - 0U, // J - 0U, // JAL - 0U, // JALR - 0U, // JALR16_MM - 0U, // JALR64 - 0U, // JALR64Pseudo - 0U, // JALRPseudo - 0U, // JALRS16_MM - 0U, // JALRS_MM - 0U, // JALR_HB - 0U, // JALR_MM - 0U, // JALS_MM - 0U, // JALX - 0U, // JALX_MM - 0U, // JAL_MM - 0U, // JIALC - 0U, // JIC - 0U, // JR - 0U, // JR16_MM - 0U, // JR64 - 0U, // JRADDIUSP - 0U, // JRC16_MM - 0U, // JR_HB - 0U, // JR_HB_R6 - 0U, // JR_MM - 0U, // J_MM - 0U, // Jal16 - 0U, // JalB16 - 0U, // JalOneReg - 0U, // JalTwoReg - 0U, // JrRa16 - 0U, // JrcRa16 - 0U, // JrcRx16 - 0U, // JumpLinkReg16 - 0U, // LB - 0U, // LB64 - 0U, // LBU16_MM - 0U, // LBUX - 0U, // LB_MM - 0U, // LBu - 0U, // LBu64 - 0U, // LBu_MM - 0U, // LD - 0U, // LDC1 - 0U, // LDC164 - 0U, // LDC1_MM - 0U, // LDC2 - 0U, // LDC2_R6 - 0U, // LDC3 - 0U, // LDI_B - 0U, // LDI_D - 0U, // LDI_H - 0U, // LDI_W - 0U, // LDL - 0U, // LDPC - 0U, // LDR - 0U, // LDXC1 - 0U, // LDXC164 - 0U, // LD_B - 0U, // LD_D - 0U, // LD_H - 0U, // LD_W - 0U, // LEA_ADDiu - 0U, // LEA_ADDiu64 - 0U, // LEA_ADDiu_MM - 0U, // LH - 0U, // LH64 - 0U, // LHU16_MM - 0U, // LHX - 0U, // LH_MM - 0U, // LHu - 0U, // LHu64 - 0U, // LHu_MM - 0U, // LI16_MM - 0U, // LL - 0U, // LLD - 0U, // LLD_R6 - 0U, // LL_MM - 0U, // LL_R6 - 0U, // LOAD_ACC128 - 0U, // LOAD_ACC64 - 0U, // LOAD_ACC64DSP - 0U, // LOAD_CCOND_DSP - 0U, // LONG_BRANCH_ADDiu - 0U, // LONG_BRANCH_DADDiu - 0U, // LONG_BRANCH_LUi - 4U, // LSA - 4U, // LSA_R6 - 0U, // LUXC1 - 0U, // LUXC164 - 0U, // LUXC1_MM - 0U, // LUi - 0U, // LUi64 - 0U, // LUi_MM - 0U, // LW - 0U, // LW16_MM - 0U, // LW64 - 0U, // LWC1 - 0U, // LWC1_MM - 0U, // LWC2 - 0U, // LWC2_R6 - 0U, // LWC3 - 0U, // LWGP_MM - 0U, // LWL - 0U, // LWL64 - 0U, // LWL_MM - 0U, // LWM16_MM - 0U, // LWM32_MM - 0U, // LWM_MM - 0U, // LWPC - 0U, // LWP_MM - 0U, // LWR - 0U, // LWR64 - 0U, // LWR_MM - 0U, // LWSP_MM - 0U, // LWUPC - 0U, // LWU_MM - 0U, // LWX - 0U, // LWXC1 - 0U, // LWXC1_MM - 0U, // LWXS_MM - 0U, // LW_MM - 0U, // LWu - 0U, // LbRxRyOffMemX16 - 0U, // LbuRxRyOffMemX16 - 0U, // LhRxRyOffMemX16 - 0U, // LhuRxRyOffMemX16 - 0U, // LiRxImm16 - 0U, // LiRxImmAlignX16 - 0U, // LiRxImmX16 - 0U, // LoadAddr32Imm - 0U, // LoadAddr32Reg - 0U, // LoadImm32Reg - 0U, // LoadImm64Reg - 0U, // LwConstant32 - 0U, // LwRxPcTcp16 - 0U, // LwRxPcTcpX16 - 0U, // LwRxRyOffMemX16 - 0U, // LwRxSpImmX16 - 0U, // MADD - 2U, // MADDF_D - 2U, // MADDF_S - 2U, // MADDR_Q_H - 2U, // MADDR_Q_W - 0U, // MADDU - 0U, // MADDU_DSP - 0U, // MADDU_MM - 2U, // MADDV_B - 2U, // MADDV_D - 2U, // MADDV_H - 2U, // MADDV_W - 20U, // MADD_D32 - 20U, // MADD_D32_MM - 20U, // MADD_D64 - 0U, // MADD_DSP - 0U, // MADD_MM - 2U, // MADD_Q_H - 2U, // MADD_Q_W - 20U, // MADD_S - 20U, // MADD_S_MM - 0U, // MAQ_SA_W_PHL - 0U, // MAQ_SA_W_PHR - 0U, // MAQ_S_W_PHL - 0U, // MAQ_S_W_PHR - 0U, // MAXA_D - 0U, // MAXA_S - 0U, // MAXI_S_B - 0U, // MAXI_S_D - 0U, // MAXI_S_H - 0U, // MAXI_S_W - 0U, // MAXI_U_B - 0U, // MAXI_U_D - 0U, // MAXI_U_H - 0U, // MAXI_U_W - 0U, // MAX_A_B - 0U, // MAX_A_D - 0U, // MAX_A_H - 0U, // MAX_A_W - 0U, // MAX_D - 0U, // MAX_S - 0U, // MAX_S_B - 0U, // MAX_S_D - 0U, // MAX_S_H - 0U, // MAX_S_W - 0U, // MAX_U_B - 0U, // MAX_U_D - 0U, // MAX_U_H - 0U, // MAX_U_W - 1U, // MFC0 - 0U, // MFC1 - 0U, // MFC1_MM - 1U, // MFC2 - 0U, // MFHC1_D32 - 0U, // MFHC1_D64 - 0U, // MFHC1_MM - 0U, // MFHI - 0U, // MFHI16_MM - 0U, // MFHI64 - 0U, // MFHI_DSP - 0U, // MFHI_MM - 0U, // MFLO - 0U, // MFLO16_MM - 0U, // MFLO64 - 0U, // MFLO_DSP - 0U, // MFLO_MM - 0U, // MINA_D - 0U, // MINA_S - 0U, // MINI_S_B - 0U, // MINI_S_D - 0U, // MINI_S_H - 0U, // MINI_S_W - 0U, // MINI_U_B - 0U, // MINI_U_D - 0U, // MINI_U_H - 0U, // MINI_U_W - 0U, // MIN_A_B - 0U, // MIN_A_D - 0U, // MIN_A_H - 0U, // MIN_A_W - 0U, // MIN_D - 0U, // MIN_S - 0U, // MIN_S_B - 0U, // MIN_S_D - 0U, // MIN_S_H - 0U, // MIN_S_W - 0U, // MIN_U_B - 0U, // MIN_U_D - 0U, // MIN_U_H - 0U, // MIN_U_W - 0U, // MIPSeh_return32 - 0U, // MIPSeh_return64 - 0U, // MOD - 0U, // MODSUB - 0U, // MODU - 0U, // MOD_S_B - 0U, // MOD_S_D - 0U, // MOD_S_H - 0U, // MOD_S_W - 0U, // MOD_U_B - 0U, // MOD_U_D - 0U, // MOD_U_H - 0U, // MOD_U_W - 0U, // MOVE16_MM - 0U, // MOVEP_MM - 0U, // MOVE_V - 0U, // MOVF_D32 - 0U, // MOVF_D32_MM - 0U, // MOVF_D64 - 0U, // MOVF_I - 0U, // MOVF_I64 - 0U, // MOVF_I_MM - 0U, // MOVF_S - 0U, // MOVF_S_MM - 0U, // MOVN_I64_D64 - 0U, // MOVN_I64_I - 0U, // MOVN_I64_I64 - 0U, // MOVN_I64_S - 0U, // MOVN_I_D32 - 0U, // MOVN_I_D32_MM - 0U, // MOVN_I_D64 - 0U, // MOVN_I_I - 0U, // MOVN_I_I64 - 0U, // MOVN_I_MM - 0U, // MOVN_I_S - 0U, // MOVN_I_S_MM - 0U, // MOVT_D32 - 0U, // MOVT_D32_MM - 0U, // MOVT_D64 - 0U, // MOVT_I - 0U, // MOVT_I64 - 0U, // MOVT_I_MM - 0U, // MOVT_S - 0U, // MOVT_S_MM - 0U, // MOVZ_I64_D64 - 0U, // MOVZ_I64_I - 0U, // MOVZ_I64_I64 - 0U, // MOVZ_I64_S - 0U, // MOVZ_I_D32 - 0U, // MOVZ_I_D32_MM - 0U, // MOVZ_I_D64 - 0U, // MOVZ_I_I - 0U, // MOVZ_I_I64 - 0U, // MOVZ_I_MM - 0U, // MOVZ_I_S - 0U, // MOVZ_I_S_MM - 0U, // MSUB - 2U, // MSUBF_D - 2U, // MSUBF_S - 2U, // MSUBR_Q_H - 2U, // MSUBR_Q_W - 0U, // MSUBU - 0U, // MSUBU_DSP - 0U, // MSUBU_MM - 2U, // MSUBV_B - 2U, // MSUBV_D - 2U, // MSUBV_H - 2U, // MSUBV_W - 20U, // MSUB_D32 - 20U, // MSUB_D32_MM - 20U, // MSUB_D64 - 0U, // MSUB_DSP - 0U, // MSUB_MM - 2U, // MSUB_Q_H - 2U, // MSUB_Q_W - 20U, // MSUB_S - 20U, // MSUB_S_MM - 1U, // MTC0 - 0U, // MTC1 - 0U, // MTC1_MM - 1U, // MTC2 - 0U, // MTHC1_D32 - 0U, // MTHC1_D64 - 0U, // MTHC1_MM - 0U, // MTHI - 0U, // MTHI64 - 0U, // MTHI_DSP - 0U, // MTHI_MM - 0U, // MTHLIP - 0U, // MTLO - 0U, // MTLO64 - 0U, // MTLO_DSP - 0U, // MTLO_MM - 0U, // MTM0 - 0U, // MTM1 - 0U, // MTM2 - 0U, // MTP0 - 0U, // MTP1 - 0U, // MTP2 - 0U, // MUH - 0U, // MUHU - 0U, // MUL - 0U, // MULEQ_S_W_PHL - 0U, // MULEQ_S_W_PHR - 0U, // MULEU_S_PH_QBL - 0U, // MULEU_S_PH_QBR - 0U, // MULQ_RS_PH - 0U, // MULQ_RS_W - 0U, // MULQ_S_PH - 0U, // MULQ_S_W - 0U, // MULR_Q_H - 0U, // MULR_Q_W - 0U, // MULSAQ_S_W_PH - 0U, // MULSA_W_PH - 0U, // MULT - 0U, // MULTU_DSP - 0U, // MULT_DSP - 0U, // MULT_MM - 0U, // MULTu - 0U, // MULTu_MM - 0U, // MULU - 0U, // MULV_B - 0U, // MULV_D - 0U, // MULV_H - 0U, // MULV_W - 0U, // MUL_MM - 0U, // MUL_PH - 0U, // MUL_Q_H - 0U, // MUL_Q_W - 0U, // MUL_R6 - 0U, // MUL_S_PH - 0U, // Mfhi16 - 0U, // Mflo16 - 0U, // Move32R16 - 0U, // MoveR3216 - 0U, // MultRxRy16 - 0U, // MultRxRyRz16 - 0U, // MultuRxRy16 - 0U, // MultuRxRyRz16 - 0U, // NLOC_B - 0U, // NLOC_D - 0U, // NLOC_H - 0U, // NLOC_W - 0U, // NLZC_B - 0U, // NLZC_D - 0U, // NLZC_H - 0U, // NLZC_W - 20U, // NMADD_D32 - 20U, // NMADD_D32_MM - 20U, // NMADD_D64 - 20U, // NMADD_S - 20U, // NMADD_S_MM - 20U, // NMSUB_D32 - 20U, // NMSUB_D32_MM - 20U, // NMSUB_D64 - 20U, // NMSUB_S - 20U, // NMSUB_S_MM - 0U, // NOP - 0U, // NOR - 0U, // NOR64 - 0U, // NORI_B - 0U, // NOR_MM - 0U, // NOR_V - 0U, // NOR_V_D_PSEUDO - 0U, // NOR_V_H_PSEUDO - 0U, // NOR_V_W_PSEUDO - 0U, // NOT16_MM - 0U, // NegRxRy16 - 0U, // NotRxRy16 - 0U, // OR - 0U, // OR16_MM - 0U, // OR64 - 0U, // ORI_B - 0U, // OR_MM - 0U, // OR_V - 0U, // OR_V_D_PSEUDO - 0U, // OR_V_H_PSEUDO - 0U, // OR_V_W_PSEUDO - 1U, // ORi - 1U, // ORi64 - 1U, // ORi_MM - 0U, // OrRxRxRy16 - 0U, // PACKRL_PH - 0U, // PAUSE - 0U, // PAUSE_MM - 0U, // PCKEV_B - 0U, // PCKEV_D - 0U, // PCKEV_H - 0U, // PCKEV_W - 0U, // PCKOD_B - 0U, // PCKOD_D - 0U, // PCKOD_H - 0U, // PCKOD_W - 0U, // PCNT_B - 0U, // PCNT_D - 0U, // PCNT_H - 0U, // PCNT_W - 0U, // PICK_PH - 0U, // PICK_QB - 0U, // POP - 0U, // PRECEQU_PH_QBL - 0U, // PRECEQU_PH_QBLA - 0U, // PRECEQU_PH_QBR - 0U, // PRECEQU_PH_QBRA - 0U, // PRECEQ_W_PHL - 0U, // PRECEQ_W_PHR - 0U, // PRECEU_PH_QBL - 0U, // PRECEU_PH_QBLA - 0U, // PRECEU_PH_QBR - 0U, // PRECEU_PH_QBRA - 0U, // PRECRQU_S_QB_PH - 0U, // PRECRQ_PH_W - 0U, // PRECRQ_QB_PH - 0U, // PRECRQ_RS_PH_W - 0U, // PRECR_QB_PH - 1U, // PRECR_SRA_PH_W - 1U, // PRECR_SRA_R_PH_W - 0U, // PREF - 0U, // PREF_MM - 0U, // PREF_R6 - 1U, // PREPEND - 0U, // PseudoCMPU_EQ_QB - 0U, // PseudoCMPU_LE_QB - 0U, // PseudoCMPU_LT_QB - 0U, // PseudoCMP_EQ_PH - 0U, // PseudoCMP_LE_PH - 0U, // PseudoCMP_LT_PH - 0U, // PseudoCVT_D32_W - 0U, // PseudoCVT_D64_L - 0U, // PseudoCVT_D64_W - 0U, // PseudoCVT_S_L - 0U, // PseudoCVT_S_W - 0U, // PseudoDMULT - 0U, // PseudoDMULTu - 0U, // PseudoDSDIV - 0U, // PseudoDUDIV - 0U, // PseudoIndirectBranch - 0U, // PseudoIndirectBranch64 - 0U, // PseudoMADD - 0U, // PseudoMADDU - 0U, // PseudoMFHI - 0U, // PseudoMFHI64 - 0U, // PseudoMFLO - 0U, // PseudoMFLO64 - 0U, // PseudoMSUB - 0U, // PseudoMSUBU - 0U, // PseudoMTLOHI - 0U, // PseudoMTLOHI64 - 0U, // PseudoMTLOHI_DSP - 0U, // PseudoMULT - 0U, // PseudoMULTu - 0U, // PseudoPICK_PH - 0U, // PseudoPICK_QB - 0U, // PseudoReturn - 0U, // PseudoReturn64 - 0U, // PseudoSDIV - 0U, // PseudoSELECTFP_F_D32 - 0U, // PseudoSELECTFP_F_D64 - 0U, // PseudoSELECTFP_F_I - 0U, // PseudoSELECTFP_F_I64 - 0U, // PseudoSELECTFP_F_S - 0U, // PseudoSELECTFP_T_D32 - 0U, // PseudoSELECTFP_T_D64 - 0U, // PseudoSELECTFP_T_I - 0U, // PseudoSELECTFP_T_I64 - 0U, // PseudoSELECTFP_T_S - 0U, // PseudoSELECT_D32 - 0U, // PseudoSELECT_D64 - 0U, // PseudoSELECT_I - 0U, // PseudoSELECT_I64 - 0U, // PseudoSELECT_S - 0U, // PseudoUDIV - 0U, // RADDU_W_QB - 0U, // RDDSP - 0U, // RDHWR - 0U, // RDHWR64 - 0U, // RDHWR_MM - 0U, // REPLV_PH - 0U, // REPLV_QB - 0U, // REPL_PH - 0U, // REPL_QB - 0U, // RINT_D - 0U, // RINT_S - 1U, // ROTR - 0U, // ROTRV - 0U, // ROTRV_MM - 1U, // ROTR_MM - 0U, // ROUND_L_D64 - 0U, // ROUND_L_S - 0U, // ROUND_W_D32 - 0U, // ROUND_W_D64 - 0U, // ROUND_W_MM - 0U, // ROUND_W_S - 0U, // ROUND_W_S_MM - 0U, // Restore16 - 0U, // RestoreX16 - 0U, // RetRA - 0U, // RetRA16 - 1U, // SAT_S_B - 1U, // SAT_S_D - 0U, // SAT_S_H - 1U, // SAT_S_W - 1U, // SAT_U_B - 1U, // SAT_U_D - 0U, // SAT_U_H - 1U, // SAT_U_W - 0U, // SB - 0U, // SB16_MM - 0U, // SB64 - 0U, // SB_MM - 0U, // SC - 0U, // SCD - 0U, // SCD_R6 - 0U, // SC_MM - 0U, // SC_R6 - 0U, // SD - 0U, // SDBBP - 0U, // SDBBP16_MM - 0U, // SDBBP_MM - 0U, // SDBBP_R6 - 0U, // SDC1 - 0U, // SDC164 - 0U, // SDC1_MM - 0U, // SDC2 - 0U, // SDC2_R6 - 0U, // SDC3 - 0U, // SDIV - 0U, // SDIV_MM - 0U, // SDL - 0U, // SDR - 0U, // SDXC1 - 0U, // SDXC164 - 0U, // SEB - 0U, // SEB64 - 0U, // SEB_MM - 0U, // SEH - 0U, // SEH64 - 0U, // SEH_MM - 0U, // SELEQZ - 0U, // SELEQZ64 - 0U, // SELEQZ_D - 0U, // SELEQZ_S - 0U, // SELNEZ - 0U, // SELNEZ64 - 0U, // SELNEZ_D - 0U, // SELNEZ_S - 2U, // SEL_D - 2U, // SEL_S - 0U, // SEQ - 0U, // SEQi - 0U, // SH - 0U, // SH16_MM - 0U, // SH64 - 0U, // SHF_B - 0U, // SHF_H - 0U, // SHF_W - 0U, // SHILO - 0U, // SHILOV - 0U, // SHLLV_PH - 0U, // SHLLV_QB - 0U, // SHLLV_S_PH - 0U, // SHLLV_S_W - 1U, // SHLL_PH - 1U, // SHLL_QB - 1U, // SHLL_S_PH - 1U, // SHLL_S_W - 0U, // SHRAV_PH - 0U, // SHRAV_QB - 0U, // SHRAV_R_PH - 0U, // SHRAV_R_QB - 0U, // SHRAV_R_W - 1U, // SHRA_PH - 1U, // SHRA_QB - 1U, // SHRA_R_PH - 1U, // SHRA_R_QB - 1U, // SHRA_R_W - 0U, // SHRLV_PH - 0U, // SHRLV_QB - 1U, // SHRL_PH - 1U, // SHRL_QB - 0U, // SH_MM - 9U, // SLDI_B - 9U, // SLDI_D - 9U, // SLDI_H - 9U, // SLDI_W - 10U, // SLD_B - 10U, // SLD_D - 10U, // SLD_H - 10U, // SLD_W - 1U, // SLL - 0U, // SLL16_MM - 0U, // SLL64_32 - 0U, // SLL64_64 - 0U, // SLLI_B - 0U, // SLLI_D - 0U, // SLLI_H - 0U, // SLLI_W - 0U, // SLLV - 0U, // SLLV_MM - 0U, // SLL_B - 0U, // SLL_D - 0U, // SLL_H - 1U, // SLL_MM - 0U, // SLL_W - 0U, // SLT - 0U, // SLT64 - 0U, // SLT_MM - 0U, // SLTi - 0U, // SLTi64 - 0U, // SLTi_MM - 0U, // SLTiu - 0U, // SLTiu64 - 0U, // SLTiu_MM - 0U, // SLTu - 0U, // SLTu64 - 0U, // SLTu_MM - 0U, // SNE - 0U, // SNEi - 0U, // SNZ_B_PSEUDO - 0U, // SNZ_D_PSEUDO - 0U, // SNZ_H_PSEUDO - 0U, // SNZ_V_PSEUDO - 0U, // SNZ_W_PSEUDO - 8U, // SPLATI_B - 8U, // SPLATI_D - 8U, // SPLATI_H - 8U, // SPLATI_W - 8U, // SPLAT_B - 8U, // SPLAT_D - 8U, // SPLAT_H - 8U, // SPLAT_W - 1U, // SRA - 0U, // SRAI_B - 0U, // SRAI_D - 0U, // SRAI_H - 0U, // SRAI_W - 1U, // SRARI_B - 1U, // SRARI_D - 0U, // SRARI_H - 1U, // SRARI_W - 0U, // SRAR_B - 0U, // SRAR_D - 0U, // SRAR_H - 0U, // SRAR_W - 0U, // SRAV - 0U, // SRAV_MM - 0U, // SRA_B - 0U, // SRA_D - 0U, // SRA_H - 1U, // SRA_MM - 0U, // SRA_W - 1U, // SRL - 0U, // SRL16_MM - 0U, // SRLI_B - 0U, // SRLI_D - 0U, // SRLI_H - 0U, // SRLI_W - 1U, // SRLRI_B - 1U, // SRLRI_D - 0U, // SRLRI_H - 1U, // SRLRI_W - 0U, // SRLR_B - 0U, // SRLR_D - 0U, // SRLR_H - 0U, // SRLR_W - 0U, // SRLV - 0U, // SRLV_MM - 0U, // SRL_B - 0U, // SRL_D - 0U, // SRL_H - 1U, // SRL_MM - 0U, // SRL_W - 0U, // SSNOP - 0U, // SSNOP_MM - 0U, // STORE_ACC128 - 0U, // STORE_ACC64 - 0U, // STORE_ACC64DSP - 0U, // STORE_CCOND_DSP - 0U, // ST_B - 0U, // ST_D - 0U, // ST_H - 0U, // ST_W - 0U, // SUB - 0U, // SUBQH_PH - 0U, // SUBQH_R_PH - 0U, // SUBQH_R_W - 0U, // SUBQH_W - 0U, // SUBQ_PH - 0U, // SUBQ_S_PH - 0U, // SUBQ_S_W - 0U, // SUBSUS_U_B - 0U, // SUBSUS_U_D - 0U, // SUBSUS_U_H - 0U, // SUBSUS_U_W - 0U, // SUBSUU_S_B - 0U, // SUBSUU_S_D - 0U, // SUBSUU_S_H - 0U, // SUBSUU_S_W - 0U, // SUBS_S_B - 0U, // SUBS_S_D - 0U, // SUBS_S_H - 0U, // SUBS_S_W - 0U, // SUBS_U_B - 0U, // SUBS_U_D - 0U, // SUBS_U_H - 0U, // SUBS_U_W - 0U, // SUBU16_MM - 0U, // SUBUH_QB - 0U, // SUBUH_R_QB - 0U, // SUBU_PH - 0U, // SUBU_QB - 0U, // SUBU_S_PH - 0U, // SUBU_S_QB - 0U, // SUBVI_B - 0U, // SUBVI_D - 0U, // SUBVI_H - 0U, // SUBVI_W - 0U, // SUBV_B - 0U, // SUBV_D - 0U, // SUBV_H - 0U, // SUBV_W - 0U, // SUB_MM - 0U, // SUBu - 0U, // SUBu_MM - 0U, // SUXC1 - 0U, // SUXC164 - 0U, // SUXC1_MM - 0U, // SW - 0U, // SW16_MM - 0U, // SW64 - 0U, // SWC1 - 0U, // SWC1_MM - 0U, // SWC2 - 0U, // SWC2_R6 - 0U, // SWC3 - 0U, // SWL - 0U, // SWL64 - 0U, // SWL_MM - 0U, // SWM16_MM - 0U, // SWM32_MM - 0U, // SWM_MM - 0U, // SWP_MM - 0U, // SWR - 0U, // SWR64 - 0U, // SWR_MM - 0U, // SWSP_MM - 0U, // SWXC1 - 0U, // SWXC1_MM - 0U, // SW_MM - 0U, // SYNC - 0U, // SYNCI - 0U, // SYNC_MM - 0U, // SYSCALL - 0U, // SYSCALL_MM - 0U, // SZ_B_PSEUDO - 0U, // SZ_D_PSEUDO - 0U, // SZ_H_PSEUDO - 0U, // SZ_V_PSEUDO - 0U, // SZ_W_PSEUDO - 0U, // Save16 - 0U, // SaveX16 - 0U, // SbRxRyOffMemX16 - 0U, // SebRx16 - 0U, // SehRx16 - 0U, // SelBeqZ - 0U, // SelBneZ - 0U, // SelTBteqZCmp - 0U, // SelTBteqZCmpi - 0U, // SelTBteqZSlt - 0U, // SelTBteqZSlti - 0U, // SelTBteqZSltiu - 0U, // SelTBteqZSltu - 0U, // SelTBtneZCmp - 0U, // SelTBtneZCmpi - 0U, // SelTBtneZSlt - 0U, // SelTBtneZSlti - 0U, // SelTBtneZSltiu - 0U, // SelTBtneZSltu - 0U, // ShRxRyOffMemX16 - 1U, // SllX16 - 0U, // SllvRxRy16 - 0U, // SltCCRxRy16 - 0U, // SltRxRy16 - 0U, // SltiCCRxImmX16 - 0U, // SltiRxImm16 - 0U, // SltiRxImmX16 - 0U, // SltiuCCRxImmX16 - 0U, // SltiuRxImm16 - 0U, // SltiuRxImmX16 - 0U, // SltuCCRxRy16 - 0U, // SltuRxRy16 - 0U, // SltuRxRyRz16 - 1U, // SraX16 - 0U, // SravRxRy16 - 1U, // SrlX16 - 0U, // SrlvRxRy16 - 0U, // SubuRxRyRz16 - 0U, // SwRxRyOffMemX16 - 0U, // SwRxSpImmX16 - 0U, // TAILCALL - 0U, // TAILCALL64_R - 0U, // TAILCALL_R - 1U, // TEQ - 0U, // TEQI - 0U, // TEQI_MM - 1U, // TEQ_MM - 1U, // TGE - 0U, // TGEI - 0U, // TGEIU - 0U, // TGEIU_MM - 0U, // TGEI_MM - 1U, // TGEU - 1U, // TGEU_MM - 1U, // TGE_MM - 0U, // TLBP - 0U, // TLBP_MM - 0U, // TLBR - 0U, // TLBR_MM - 0U, // TLBWI - 0U, // TLBWI_MM - 0U, // TLBWR - 0U, // TLBWR_MM - 1U, // TLT - 0U, // TLTI - 0U, // TLTIU_MM - 0U, // TLTI_MM - 1U, // TLTU - 1U, // TLTU_MM - 1U, // TLT_MM - 1U, // TNE - 0U, // TNEI - 0U, // TNEI_MM - 1U, // TNE_MM - 0U, // TRAP - 0U, // TRUNC_L_D64 - 0U, // TRUNC_L_S - 0U, // TRUNC_W_D32 - 0U, // TRUNC_W_D64 - 0U, // TRUNC_W_MM - 0U, // TRUNC_W_S - 0U, // TRUNC_W_S_MM - 0U, // TTLTIU - 0U, // UDIV - 0U, // UDIV_MM - 0U, // V3MULU - 0U, // VMM0 - 0U, // VMULU - 2U, // VSHF_B - 2U, // VSHF_D - 2U, // VSHF_H - 2U, // VSHF_W - 0U, // WAIT - 0U, // WAIT_MM - 0U, // WRDSP - 0U, // WSBH - 0U, // WSBH_MM - 0U, // XOR - 0U, // XOR16_MM - 0U, // XOR64 - 0U, // XORI_B - 0U, // XOR_MM - 0U, // XOR_V - 0U, // XOR_V_D_PSEUDO - 0U, // XOR_V_H_PSEUDO - 0U, // XOR_V_W_PSEUDO - 1U, // XORi - 1U, // XORi64 - 1U, // XORi_MM - 0U, // XorRxRxRy16 - 0U - }; + static const uint8_t OpInfo2[] = {0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 0U, // ABSQ_S_PH + 0U, // ABSQ_S_QB + 0U, // ABSQ_S_W + 0U, // ADD + 0U, // ADDIUPC + 0U, // ADDIUPC_MM + 0U, // ADDIUR1SP_MM + 0U, // ADDIUR2_MM + 0U, // ADDIUS5_MM + 0U, // ADDIUSP_MM + 0U, // ADDQH_PH + 0U, // ADDQH_R_PH + 0U, // ADDQH_R_W + 0U, // ADDQH_W + 0U, // ADDQ_PH + 0U, // ADDQ_S_PH + 0U, // ADDQ_S_W + 0U, // ADDSC + 0U, // ADDS_A_B + 0U, // ADDS_A_D + 0U, // ADDS_A_H + 0U, // ADDS_A_W + 0U, // ADDS_S_B + 0U, // ADDS_S_D + 0U, // ADDS_S_H + 0U, // ADDS_S_W + 0U, // ADDS_U_B + 0U, // ADDS_U_D + 0U, // ADDS_U_H + 0U, // ADDS_U_W + 0U, // ADDU16_MM + 0U, // ADDUH_QB + 0U, // ADDUH_R_QB + 0U, // ADDU_PH + 0U, // ADDU_QB + 0U, // ADDU_S_PH + 0U, // ADDU_S_QB + 0U, // ADDVI_B + 0U, // ADDVI_D + 0U, // ADDVI_H + 0U, // ADDVI_W + 0U, // ADDV_B + 0U, // ADDV_D + 0U, // ADDV_H + 0U, // ADDV_W + 0U, // ADDWC + 0U, // ADD_A_B + 0U, // ADD_A_D + 0U, // ADD_A_H + 0U, // ADD_A_W + 0U, // ADD_MM + 0U, // ADDi + 0U, // ADDi_MM + 0U, // ADDiu + 0U, // ADDiu_MM + 0U, // ADDu + 0U, // ADDu_MM + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 4U, // ALIGN + 0U, // ALUIPC + 0U, // AND + 0U, // AND16_MM + 0U, // AND64 + 0U, // ANDI16_MM + 0U, // ANDI_B + 0U, // AND_MM + 0U, // AND_V + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 1U, // ANDi + 1U, // ANDi64 + 1U, // ANDi_MM + 1U, // APPEND + 0U, // ASUB_S_B + 0U, // ASUB_S_D + 0U, // ASUB_S_H + 0U, // ASUB_S_W + 0U, // ASUB_U_B + 0U, // ASUB_U_D + 0U, // ASUB_U_H + 0U, // ASUB_U_W + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 0U, // AUI + 0U, // AUIPC + 0U, // AVER_S_B + 0U, // AVER_S_D + 0U, // AVER_S_H + 0U, // AVER_S_W + 0U, // AVER_U_B + 0U, // AVER_U_D + 0U, // AVER_U_H + 0U, // AVER_U_W + 0U, // AVE_S_B + 0U, // AVE_S_D + 0U, // AVE_S_H + 0U, // AVE_S_W + 0U, // AVE_U_B + 0U, // AVE_U_D + 0U, // AVE_U_H + 0U, // AVE_U_W + 0U, // AddiuRxImmX16 + 0U, // AddiuRxPcImmX16 + 0U, // AddiuRxRxImm16 + 0U, // AddiuRxRxImmX16 + 0U, // AddiuRxRyOffMemX16 + 0U, // AddiuSpImm16 + 0U, // AddiuSpImmX16 + 0U, // AdduRxRyRz16 + 0U, // AndRxRxRy16 + 0U, // B + 0U, // B16_MM + 0U, // BADDu + 0U, // BAL + 0U, // BALC + 1U, // BALIGN + 0U, // BAL_BR + 0U, // BBIT0 + 0U, // BBIT032 + 0U, // BBIT1 + 0U, // BBIT132 + 0U, // BC + 0U, // BC0F + 0U, // BC0FL + 0U, // BC0T + 0U, // BC0TL + 0U, // BC1EQZ + 0U, // BC1F + 0U, // BC1FL + 0U, // BC1F_MM + 0U, // BC1NEZ + 0U, // BC1T + 0U, // BC1TL + 0U, // BC1T_MM + 0U, // BC2EQZ + 0U, // BC2F + 0U, // BC2FL + 0U, // BC2NEZ + 0U, // BC2T + 0U, // BC2TL + 0U, // BC3F + 0U, // BC3FL + 0U, // BC3T + 0U, // BC3TL + 0U, // BCLRI_B + 0U, // BCLRI_D + 0U, // BCLRI_H + 0U, // BCLRI_W + 0U, // BCLR_B + 0U, // BCLR_D + 0U, // BCLR_H + 0U, // BCLR_W + 0U, // BEQ + 0U, // BEQ64 + 0U, // BEQC + 0U, // BEQL + 0U, // BEQZ16_MM + 0U, // BEQZALC + 0U, // BEQZC + 0U, // BEQZC_MM + 0U, // BEQ_MM + 0U, // BGEC + 0U, // BGEUC + 0U, // BGEZ + 0U, // BGEZ64 + 0U, // BGEZAL + 0U, // BGEZALC + 0U, // BGEZALL + 0U, // BGEZALS_MM + 0U, // BGEZAL_MM + 0U, // BGEZC + 0U, // BGEZL + 0U, // BGEZ_MM + 0U, // BGTZ + 0U, // BGTZ64 + 0U, // BGTZALC + 0U, // BGTZC + 0U, // BGTZL + 0U, // BGTZ_MM + 1U, // BINSLI_B + 1U, // BINSLI_D + 1U, // BINSLI_H + 1U, // BINSLI_W + 2U, // BINSL_B + 2U, // BINSL_D + 2U, // BINSL_H + 2U, // BINSL_W + 1U, // BINSRI_B + 1U, // BINSRI_D + 1U, // BINSRI_H + 1U, // BINSRI_W + 2U, // BINSR_B + 2U, // BINSR_D + 2U, // BINSR_H + 2U, // BINSR_W + 0U, // BITREV + 0U, // BITSWAP + 0U, // BLEZ + 0U, // BLEZ64 + 0U, // BLEZALC + 0U, // BLEZC + 0U, // BLEZL + 0U, // BLEZ_MM + 0U, // BLTC + 0U, // BLTUC + 0U, // BLTZ + 0U, // BLTZ64 + 0U, // BLTZAL + 0U, // BLTZALC + 0U, // BLTZALL + 0U, // BLTZALS_MM + 0U, // BLTZAL_MM + 0U, // BLTZC + 0U, // BLTZL + 0U, // BLTZ_MM + 1U, // BMNZI_B + 2U, // BMNZ_V + 1U, // BMZI_B + 2U, // BMZ_V + 0U, // BNE + 0U, // BNE64 + 0U, // BNEC + 0U, // BNEGI_B + 0U, // BNEGI_D + 0U, // BNEGI_H + 0U, // BNEGI_W + 0U, // BNEG_B + 0U, // BNEG_D + 0U, // BNEG_H + 0U, // BNEG_W + 0U, // BNEL + 0U, // BNEZ16_MM + 0U, // BNEZALC + 0U, // BNEZC + 0U, // BNEZC_MM + 0U, // BNE_MM + 0U, // BNVC + 0U, // BNZ_B + 0U, // BNZ_D + 0U, // BNZ_H + 0U, // BNZ_V + 0U, // BNZ_W + 0U, // BOVC + 0U, // BPOSGE32 + 0U, // BPOSGE32_PSEUDO + 0U, // BREAK + 0U, // BREAK16_MM + 0U, // BREAK_MM + 1U, // BSELI_B + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 2U, // BSEL_V + 0U, // BSEL_W_PSEUDO + 0U, // BSETI_B + 0U, // BSETI_D + 0U, // BSETI_H + 0U, // BSETI_W + 0U, // BSET_B + 0U, // BSET_D + 0U, // BSET_H + 0U, // BSET_W + 0U, // BZ_B + 0U, // BZ_D + 0U, // BZ_H + 0U, // BZ_V + 0U, // BZ_W + 0U, // B_MM_Pseudo + 0U, // BeqzRxImm16 + 0U, // BeqzRxImmX16 + 0U, // Bimm16 + 0U, // BimmX16 + 0U, // BnezRxImm16 + 0U, // BnezRxImmX16 + 0U, // Break16 + 0U, // Bteqz16 + 0U, // BteqzT8CmpX16 + 0U, // BteqzT8CmpiX16 + 0U, // BteqzT8SltX16 + 0U, // BteqzT8SltiX16 + 0U, // BteqzT8SltiuX16 + 0U, // BteqzT8SltuX16 + 0U, // BteqzX16 + 0U, // Btnez16 + 0U, // BtnezT8CmpX16 + 0U, // BtnezT8CmpiX16 + 0U, // BtnezT8SltX16 + 0U, // BtnezT8SltiX16 + 0U, // BtnezT8SltiuX16 + 0U, // BtnezT8SltuX16 + 0U, // BtnezX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 0U, // CACHE + 0U, // CACHE_MM + 0U, // CACHE_R6 + 0U, // CEIL_L_D64 + 0U, // CEIL_L_S + 0U, // CEIL_W_D32 + 0U, // CEIL_W_D64 + 0U, // CEIL_W_MM + 0U, // CEIL_W_S + 0U, // CEIL_W_S_MM + 0U, // CEQI_B + 0U, // CEQI_D + 0U, // CEQI_H + 0U, // CEQI_W + 0U, // CEQ_B + 0U, // CEQ_D + 0U, // CEQ_H + 0U, // CEQ_W + 0U, // CFC1 + 0U, // CFC1_MM + 0U, // CFCMSA + 5U, // CINS + 5U, // CINS32 + 0U, // CLASS_D + 0U, // CLASS_S + 0U, // CLEI_S_B + 0U, // CLEI_S_D + 0U, // CLEI_S_H + 0U, // CLEI_S_W + 0U, // CLEI_U_B + 0U, // CLEI_U_D + 0U, // CLEI_U_H + 0U, // CLEI_U_W + 0U, // CLE_S_B + 0U, // CLE_S_D + 0U, // CLE_S_H + 0U, // CLE_S_W + 0U, // CLE_U_B + 0U, // CLE_U_D + 0U, // CLE_U_H + 0U, // CLE_U_W + 0U, // CLO + 0U, // CLO_MM + 0U, // CLO_R6 + 0U, // CLTI_S_B + 0U, // CLTI_S_D + 0U, // CLTI_S_H + 0U, // CLTI_S_W + 0U, // CLTI_U_B + 0U, // CLTI_U_D + 0U, // CLTI_U_H + 0U, // CLTI_U_W + 0U, // CLT_S_B + 0U, // CLT_S_D + 0U, // CLT_S_H + 0U, // CLT_S_W + 0U, // CLT_U_B + 0U, // CLT_U_D + 0U, // CLT_U_H + 0U, // CLT_U_W + 0U, // CLZ + 0U, // CLZ_MM + 0U, // CLZ_R6 + 0U, // CMPGDU_EQ_QB + 0U, // CMPGDU_LE_QB + 0U, // CMPGDU_LT_QB + 0U, // CMPGU_EQ_QB + 0U, // CMPGU_LE_QB + 0U, // CMPGU_LT_QB + 0U, // CMPU_EQ_QB + 0U, // CMPU_LE_QB + 0U, // CMPU_LT_QB + 0U, // CMP_EQ_D + 0U, // CMP_EQ_PH + 0U, // CMP_EQ_S + 0U, // CMP_F_D + 0U, // CMP_F_S + 0U, // CMP_LE_D + 0U, // CMP_LE_PH + 0U, // CMP_LE_S + 0U, // CMP_LT_D + 0U, // CMP_LT_PH + 0U, // CMP_LT_S + 0U, // CMP_SAF_D + 0U, // CMP_SAF_S + 0U, // CMP_SEQ_D + 0U, // CMP_SEQ_S + 0U, // CMP_SLE_D + 0U, // CMP_SLE_S + 0U, // CMP_SLT_D + 0U, // CMP_SLT_S + 0U, // CMP_SUEQ_D + 0U, // CMP_SUEQ_S + 0U, // CMP_SULE_D + 0U, // CMP_SULE_S + 0U, // CMP_SULT_D + 0U, // CMP_SULT_S + 0U, // CMP_SUN_D + 0U, // CMP_SUN_S + 0U, // CMP_UEQ_D + 0U, // CMP_UEQ_S + 0U, // CMP_ULE_D + 0U, // CMP_ULE_S + 0U, // CMP_ULT_D + 0U, // CMP_ULT_S + 0U, // CMP_UN_D + 0U, // CMP_UN_S + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 8U, // COPY_S_B + 8U, // COPY_S_D + 8U, // COPY_S_H + 8U, // COPY_S_W + 8U, // COPY_U_B + 8U, // COPY_U_D + 8U, // COPY_U_H + 8U, // COPY_U_W + 0U, // CTC1 + 0U, // CTC1_MM + 0U, // CTCMSA + 0U, // CVT_D32_S + 0U, // CVT_D32_W + 0U, // CVT_D32_W_MM + 0U, // CVT_D64_L + 0U, // CVT_D64_S + 0U, // CVT_D64_W + 0U, // CVT_D_S_MM + 0U, // CVT_L_D64 + 0U, // CVT_L_D64_MM + 0U, // CVT_L_S + 0U, // CVT_L_S_MM + 0U, // CVT_S_D32 + 0U, // CVT_S_D32_MM + 0U, // CVT_S_D64 + 0U, // CVT_S_L + 0U, // CVT_S_W + 0U, // CVT_S_W_MM + 0U, // CVT_W_D32 + 0U, // CVT_W_D64 + 0U, // CVT_W_MM + 0U, // CVT_W_S + 0U, // CVT_W_S_MM + 0U, // C_EQ_D32 + 0U, // C_EQ_D64 + 0U, // C_EQ_S + 0U, // C_F_D32 + 0U, // C_F_D64 + 0U, // C_F_S + 0U, // C_LE_D32 + 0U, // C_LE_D64 + 0U, // C_LE_S + 0U, // C_LT_D32 + 0U, // C_LT_D64 + 0U, // C_LT_S + 0U, // C_NGE_D32 + 0U, // C_NGE_D64 + 0U, // C_NGE_S + 0U, // C_NGLE_D32 + 0U, // C_NGLE_D64 + 0U, // C_NGLE_S + 0U, // C_NGL_D32 + 0U, // C_NGL_D64 + 0U, // C_NGL_S + 0U, // C_NGT_D32 + 0U, // C_NGT_D64 + 0U, // C_NGT_S + 0U, // C_OLE_D32 + 0U, // C_OLE_D64 + 0U, // C_OLE_S + 0U, // C_OLT_D32 + 0U, // C_OLT_D64 + 0U, // C_OLT_S + 0U, // C_SEQ_D32 + 0U, // C_SEQ_D64 + 0U, // C_SEQ_S + 0U, // C_SF_D32 + 0U, // C_SF_D64 + 0U, // C_SF_S + 0U, // C_UEQ_D32 + 0U, // C_UEQ_D64 + 0U, // C_UEQ_S + 0U, // C_ULE_D32 + 0U, // C_ULE_D64 + 0U, // C_ULE_S + 0U, // C_ULT_D32 + 0U, // C_ULT_D64 + 0U, // C_ULT_S + 0U, // C_UN_D32 + 0U, // C_UN_D64 + 0U, // C_UN_S + 0U, // CmpRxRy16 + 0U, // CmpiRxImm16 + 0U, // CmpiRxImmX16 + 0U, // Constant32 + 0U, // DADD + 0U, // DADDi + 0U, // DADDiu + 0U, // DADDu + 0U, // DAHI + 4U, // DALIGN + 0U, // DATI + 0U, // DAUI + 0U, // DBITSWAP + 0U, // DCLO + 0U, // DCLO_R6 + 0U, // DCLZ + 0U, // DCLZ_R6 + 0U, // DDIV + 0U, // DDIVU + 0U, // DERET + 0U, // DERET_MM + 21U, // DEXT + 21U, // DEXTM + 21U, // DEXTU + 0U, // DI + 21U, // DINS + 21U, // DINSM + 21U, // DINSU + 0U, // DIV + 0U, // DIVU + 0U, // DIV_S_B + 0U, // DIV_S_D + 0U, // DIV_S_H + 0U, // DIV_S_W + 0U, // DIV_U_B + 0U, // DIV_U_D + 0U, // DIV_U_H + 0U, // DIV_U_W + 0U, // DI_MM + 4U, // DLSA + 4U, // DLSA_R6 + 1U, // DMFC0 + 0U, // DMFC1 + 1U, // DMFC2 + 0U, // DMOD + 0U, // DMODU + 1U, // DMTC0 + 0U, // DMTC1 + 1U, // DMTC2 + 0U, // DMUH + 0U, // DMUHU + 0U, // DMUL + 0U, // DMULT + 0U, // DMULTu + 0U, // DMULU + 0U, // DMUL_R6 + 0U, // DOTP_S_D + 0U, // DOTP_S_H + 0U, // DOTP_S_W + 0U, // DOTP_U_D + 0U, // DOTP_U_H + 0U, // DOTP_U_W + 2U, // DPADD_S_D + 2U, // DPADD_S_H + 2U, // DPADD_S_W + 2U, // DPADD_U_D + 2U, // DPADD_U_H + 2U, // DPADD_U_W + 0U, // DPAQX_SA_W_PH + 0U, // DPAQX_S_W_PH + 0U, // DPAQ_SA_L_W + 0U, // DPAQ_S_W_PH + 0U, // DPAU_H_QBL + 0U, // DPAU_H_QBR + 0U, // DPAX_W_PH + 0U, // DPA_W_PH + 0U, // DPOP + 0U, // DPSQX_SA_W_PH + 0U, // DPSQX_S_W_PH + 0U, // DPSQ_SA_L_W + 0U, // DPSQ_S_W_PH + 2U, // DPSUB_S_D + 2U, // DPSUB_S_H + 2U, // DPSUB_S_W + 2U, // DPSUB_U_D + 2U, // DPSUB_U_H + 2U, // DPSUB_U_W + 0U, // DPSU_H_QBL + 0U, // DPSU_H_QBR + 0U, // DPSX_W_PH + 0U, // DPS_W_PH + 1U, // DROTR + 1U, // DROTR32 + 0U, // DROTRV + 0U, // DSBH + 0U, // DSDIV + 0U, // DSHD + 1U, // DSLL + 1U, // DSLL32 + 0U, // DSLL64_32 + 0U, // DSLLV + 1U, // DSRA + 1U, // DSRA32 + 0U, // DSRAV + 1U, // DSRL + 1U, // DSRL32 + 0U, // DSRLV + 0U, // DSUB + 0U, // DSUBu + 0U, // DUDIV + 0U, // DivRxRy16 + 0U, // DivuRxRy16 + 0U, // EHB + 0U, // EHB_MM + 0U, // EI + 0U, // EI_MM + 0U, // ERET + 0U, // ERET_MM + 21U, // EXT + 1U, // EXTP + 1U, // EXTPDP + 0U, // EXTPDPV + 0U, // EXTPV + 0U, // EXTRV_RS_W + 0U, // EXTRV_R_W + 0U, // EXTRV_S_H + 0U, // EXTRV_W + 1U, // EXTR_RS_W + 1U, // EXTR_R_W + 1U, // EXTR_S_H + 1U, // EXTR_W + 5U, // EXTS + 5U, // EXTS32 + 21U, // EXT_MM + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 0U, // FABS_D32 + 0U, // FABS_D64 + 0U, // FABS_MM + 0U, // FABS_S + 0U, // FABS_S_MM + 0U, // FABS_W + 0U, // FADD_D + 0U, // FADD_D32 + 0U, // FADD_D64 + 0U, // FADD_MM + 0U, // FADD_S + 0U, // FADD_S_MM + 0U, // FADD_W + 0U, // FCAF_D + 0U, // FCAF_W + 0U, // FCEQ_D + 0U, // FCEQ_W + 0U, // FCLASS_D + 0U, // FCLASS_W + 0U, // FCLE_D + 0U, // FCLE_W + 0U, // FCLT_D + 0U, // FCLT_W + 0U, // FCMP_D32 + 0U, // FCMP_D32_MM + 0U, // FCMP_D64 + 0U, // FCMP_S32 + 0U, // FCMP_S32_MM + 0U, // FCNE_D + 0U, // FCNE_W + 0U, // FCOR_D + 0U, // FCOR_W + 0U, // FCUEQ_D + 0U, // FCUEQ_W + 0U, // FCULE_D + 0U, // FCULE_W + 0U, // FCULT_D + 0U, // FCULT_W + 0U, // FCUNE_D + 0U, // FCUNE_W + 0U, // FCUN_D + 0U, // FCUN_W + 0U, // FDIV_D + 0U, // FDIV_D32 + 0U, // FDIV_D64 + 0U, // FDIV_MM + 0U, // FDIV_S + 0U, // FDIV_S_MM + 0U, // FDIV_W + 0U, // FEXDO_H + 0U, // FEXDO_W + 0U, // FEXP2_D + 0U, // FEXP2_D_1_PSEUDO + 0U, // FEXP2_W + 0U, // FEXP2_W_1_PSEUDO + 0U, // FEXUPL_D + 0U, // FEXUPL_W + 0U, // FEXUPR_D + 0U, // FEXUPR_W + 0U, // FFINT_S_D + 0U, // FFINT_S_W + 0U, // FFINT_U_D + 0U, // FFINT_U_W + 0U, // FFQL_D + 0U, // FFQL_W + 0U, // FFQR_D + 0U, // FFQR_W + 0U, // FILL_B + 0U, // FILL_D + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 0U, // FILL_H + 0U, // FILL_W + 0U, // FLOG2_D + 0U, // FLOG2_W + 0U, // FLOOR_L_D64 + 0U, // FLOOR_L_S + 0U, // FLOOR_W_D32 + 0U, // FLOOR_W_D64 + 0U, // FLOOR_W_MM + 0U, // FLOOR_W_S + 0U, // FLOOR_W_S_MM + 2U, // FMADD_D + 2U, // FMADD_W + 0U, // FMAX_A_D + 0U, // FMAX_A_W + 0U, // FMAX_D + 0U, // FMAX_W + 0U, // FMIN_A_D + 0U, // FMIN_A_W + 0U, // FMIN_D + 0U, // FMIN_W + 0U, // FMOV_D32 + 0U, // FMOV_D32_MM + 0U, // FMOV_D64 + 0U, // FMOV_S + 0U, // FMOV_S_MM + 2U, // FMSUB_D + 2U, // FMSUB_W + 0U, // FMUL_D + 0U, // FMUL_D32 + 0U, // FMUL_D64 + 0U, // FMUL_MM + 0U, // FMUL_S + 0U, // FMUL_S_MM + 0U, // FMUL_W + 0U, // FNEG_D32 + 0U, // FNEG_D64 + 0U, // FNEG_MM + 0U, // FNEG_S + 0U, // FNEG_S_MM + 0U, // FRCP_D + 0U, // FRCP_W + 0U, // FRINT_D + 0U, // FRINT_W + 0U, // FRSQRT_D + 0U, // FRSQRT_W + 0U, // FSAF_D + 0U, // FSAF_W + 0U, // FSEQ_D + 0U, // FSEQ_W + 0U, // FSLE_D + 0U, // FSLE_W + 0U, // FSLT_D + 0U, // FSLT_W + 0U, // FSNE_D + 0U, // FSNE_W + 0U, // FSOR_D + 0U, // FSOR_W + 0U, // FSQRT_D + 0U, // FSQRT_D32 + 0U, // FSQRT_D64 + 0U, // FSQRT_MM + 0U, // FSQRT_S + 0U, // FSQRT_S_MM + 0U, // FSQRT_W + 0U, // FSUB_D + 0U, // FSUB_D32 + 0U, // FSUB_D64 + 0U, // FSUB_MM + 0U, // FSUB_S + 0U, // FSUB_S_MM + 0U, // FSUB_W + 0U, // FSUEQ_D + 0U, // FSUEQ_W + 0U, // FSULE_D + 0U, // FSULE_W + 0U, // FSULT_D + 0U, // FSULT_W + 0U, // FSUNE_D + 0U, // FSUNE_W + 0U, // FSUN_D + 0U, // FSUN_W + 0U, // FTINT_S_D + 0U, // FTINT_S_W + 0U, // FTINT_U_D + 0U, // FTINT_U_W + 0U, // FTQ_H + 0U, // FTQ_W + 0U, // FTRUNC_S_D + 0U, // FTRUNC_S_W + 0U, // FTRUNC_U_D + 0U, // FTRUNC_U_W + 0U, // GotPrologue16 + 0U, // HADD_S_D + 0U, // HADD_S_H + 0U, // HADD_S_W + 0U, // HADD_U_D + 0U, // HADD_U_H + 0U, // HADD_U_W + 0U, // HSUB_S_D + 0U, // HSUB_S_H + 0U, // HSUB_S_W + 0U, // HSUB_U_D + 0U, // HSUB_U_H + 0U, // HSUB_U_W + 0U, // ILVEV_B + 0U, // ILVEV_D + 0U, // ILVEV_H + 0U, // ILVEV_W + 0U, // ILVL_B + 0U, // ILVL_D + 0U, // ILVL_H + 0U, // ILVL_W + 0U, // ILVOD_B + 0U, // ILVOD_D + 0U, // ILVOD_H + 0U, // ILVOD_W + 0U, // ILVR_B + 0U, // ILVR_D + 0U, // ILVR_H + 0U, // ILVR_W + 21U, // INS + 0U, // INSERT_B + 0U, // INSERT_B_VIDX_PSEUDO + 0U, // INSERT_D + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 0U, // INSERT_H + 0U, // INSERT_H_VIDX_PSEUDO + 0U, // INSERT_W + 0U, // INSERT_W_VIDX_PSEUDO + 0U, // INSV + 0U, // INSVE_B + 0U, // INSVE_D + 0U, // INSVE_H + 0U, // INSVE_W + 21U, // INS_MM + 0U, // J + 0U, // JAL + 0U, // JALR + 0U, // JALR16_MM + 0U, // JALR64 + 0U, // JALR64Pseudo + 0U, // JALRPseudo + 0U, // JALRS16_MM + 0U, // JALRS_MM + 0U, // JALR_HB + 0U, // JALR_MM + 0U, // JALS_MM + 0U, // JALX + 0U, // JALX_MM + 0U, // JAL_MM + 0U, // JIALC + 0U, // JIC + 0U, // JR + 0U, // JR16_MM + 0U, // JR64 + 0U, // JRADDIUSP + 0U, // JRC16_MM + 0U, // JR_HB + 0U, // JR_HB_R6 + 0U, // JR_MM + 0U, // J_MM + 0U, // Jal16 + 0U, // JalB16 + 0U, // JalOneReg + 0U, // JalTwoReg + 0U, // JrRa16 + 0U, // JrcRa16 + 0U, // JrcRx16 + 0U, // JumpLinkReg16 + 0U, // LB + 0U, // LB64 + 0U, // LBU16_MM + 0U, // LBUX + 0U, // LB_MM + 0U, // LBu + 0U, // LBu64 + 0U, // LBu_MM + 0U, // LD + 0U, // LDC1 + 0U, // LDC164 + 0U, // LDC1_MM + 0U, // LDC2 + 0U, // LDC2_R6 + 0U, // LDC3 + 0U, // LDI_B + 0U, // LDI_D + 0U, // LDI_H + 0U, // LDI_W + 0U, // LDL + 0U, // LDPC + 0U, // LDR + 0U, // LDXC1 + 0U, // LDXC164 + 0U, // LD_B + 0U, // LD_D + 0U, // LD_H + 0U, // LD_W + 0U, // LEA_ADDiu + 0U, // LEA_ADDiu64 + 0U, // LEA_ADDiu_MM + 0U, // LH + 0U, // LH64 + 0U, // LHU16_MM + 0U, // LHX + 0U, // LH_MM + 0U, // LHu + 0U, // LHu64 + 0U, // LHu_MM + 0U, // LI16_MM + 0U, // LL + 0U, // LLD + 0U, // LLD_R6 + 0U, // LL_MM + 0U, // LL_R6 + 0U, // LOAD_ACC128 + 0U, // LOAD_ACC64 + 0U, // LOAD_ACC64DSP + 0U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_LUi + 4U, // LSA + 4U, // LSA_R6 + 0U, // LUXC1 + 0U, // LUXC164 + 0U, // LUXC1_MM + 0U, // LUi + 0U, // LUi64 + 0U, // LUi_MM + 0U, // LW + 0U, // LW16_MM + 0U, // LW64 + 0U, // LWC1 + 0U, // LWC1_MM + 0U, // LWC2 + 0U, // LWC2_R6 + 0U, // LWC3 + 0U, // LWGP_MM + 0U, // LWL + 0U, // LWL64 + 0U, // LWL_MM + 0U, // LWM16_MM + 0U, // LWM32_MM + 0U, // LWM_MM + 0U, // LWPC + 0U, // LWP_MM + 0U, // LWR + 0U, // LWR64 + 0U, // LWR_MM + 0U, // LWSP_MM + 0U, // LWUPC + 0U, // LWU_MM + 0U, // LWX + 0U, // LWXC1 + 0U, // LWXC1_MM + 0U, // LWXS_MM + 0U, // LW_MM + 0U, // LWu + 0U, // LbRxRyOffMemX16 + 0U, // LbuRxRyOffMemX16 + 0U, // LhRxRyOffMemX16 + 0U, // LhuRxRyOffMemX16 + 0U, // LiRxImm16 + 0U, // LiRxImmAlignX16 + 0U, // LiRxImmX16 + 0U, // LoadAddr32Imm + 0U, // LoadAddr32Reg + 0U, // LoadImm32Reg + 0U, // LoadImm64Reg + 0U, // LwConstant32 + 0U, // LwRxPcTcp16 + 0U, // LwRxPcTcpX16 + 0U, // LwRxRyOffMemX16 + 0U, // LwRxSpImmX16 + 0U, // MADD + 2U, // MADDF_D + 2U, // MADDF_S + 2U, // MADDR_Q_H + 2U, // MADDR_Q_W + 0U, // MADDU + 0U, // MADDU_DSP + 0U, // MADDU_MM + 2U, // MADDV_B + 2U, // MADDV_D + 2U, // MADDV_H + 2U, // MADDV_W + 20U, // MADD_D32 + 20U, // MADD_D32_MM + 20U, // MADD_D64 + 0U, // MADD_DSP + 0U, // MADD_MM + 2U, // MADD_Q_H + 2U, // MADD_Q_W + 20U, // MADD_S + 20U, // MADD_S_MM + 0U, // MAQ_SA_W_PHL + 0U, // MAQ_SA_W_PHR + 0U, // MAQ_S_W_PHL + 0U, // MAQ_S_W_PHR + 0U, // MAXA_D + 0U, // MAXA_S + 0U, // MAXI_S_B + 0U, // MAXI_S_D + 0U, // MAXI_S_H + 0U, // MAXI_S_W + 0U, // MAXI_U_B + 0U, // MAXI_U_D + 0U, // MAXI_U_H + 0U, // MAXI_U_W + 0U, // MAX_A_B + 0U, // MAX_A_D + 0U, // MAX_A_H + 0U, // MAX_A_W + 0U, // MAX_D + 0U, // MAX_S + 0U, // MAX_S_B + 0U, // MAX_S_D + 0U, // MAX_S_H + 0U, // MAX_S_W + 0U, // MAX_U_B + 0U, // MAX_U_D + 0U, // MAX_U_H + 0U, // MAX_U_W + 1U, // MFC0 + 0U, // MFC1 + 0U, // MFC1_MM + 1U, // MFC2 + 0U, // MFHC1_D32 + 0U, // MFHC1_D64 + 0U, // MFHC1_MM + 0U, // MFHI + 0U, // MFHI16_MM + 0U, // MFHI64 + 0U, // MFHI_DSP + 0U, // MFHI_MM + 0U, // MFLO + 0U, // MFLO16_MM + 0U, // MFLO64 + 0U, // MFLO_DSP + 0U, // MFLO_MM + 0U, // MINA_D + 0U, // MINA_S + 0U, // MINI_S_B + 0U, // MINI_S_D + 0U, // MINI_S_H + 0U, // MINI_S_W + 0U, // MINI_U_B + 0U, // MINI_U_D + 0U, // MINI_U_H + 0U, // MINI_U_W + 0U, // MIN_A_B + 0U, // MIN_A_D + 0U, // MIN_A_H + 0U, // MIN_A_W + 0U, // MIN_D + 0U, // MIN_S + 0U, // MIN_S_B + 0U, // MIN_S_D + 0U, // MIN_S_H + 0U, // MIN_S_W + 0U, // MIN_U_B + 0U, // MIN_U_D + 0U, // MIN_U_H + 0U, // MIN_U_W + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 0U, // MOD + 0U, // MODSUB + 0U, // MODU + 0U, // MOD_S_B + 0U, // MOD_S_D + 0U, // MOD_S_H + 0U, // MOD_S_W + 0U, // MOD_U_B + 0U, // MOD_U_D + 0U, // MOD_U_H + 0U, // MOD_U_W + 0U, // MOVE16_MM + 0U, // MOVEP_MM + 0U, // MOVE_V + 0U, // MOVF_D32 + 0U, // MOVF_D32_MM + 0U, // MOVF_D64 + 0U, // MOVF_I + 0U, // MOVF_I64 + 0U, // MOVF_I_MM + 0U, // MOVF_S + 0U, // MOVF_S_MM + 0U, // MOVN_I64_D64 + 0U, // MOVN_I64_I + 0U, // MOVN_I64_I64 + 0U, // MOVN_I64_S + 0U, // MOVN_I_D32 + 0U, // MOVN_I_D32_MM + 0U, // MOVN_I_D64 + 0U, // MOVN_I_I + 0U, // MOVN_I_I64 + 0U, // MOVN_I_MM + 0U, // MOVN_I_S + 0U, // MOVN_I_S_MM + 0U, // MOVT_D32 + 0U, // MOVT_D32_MM + 0U, // MOVT_D64 + 0U, // MOVT_I + 0U, // MOVT_I64 + 0U, // MOVT_I_MM + 0U, // MOVT_S + 0U, // MOVT_S_MM + 0U, // MOVZ_I64_D64 + 0U, // MOVZ_I64_I + 0U, // MOVZ_I64_I64 + 0U, // MOVZ_I64_S + 0U, // MOVZ_I_D32 + 0U, // MOVZ_I_D32_MM + 0U, // MOVZ_I_D64 + 0U, // MOVZ_I_I + 0U, // MOVZ_I_I64 + 0U, // MOVZ_I_MM + 0U, // MOVZ_I_S + 0U, // MOVZ_I_S_MM + 0U, // MSUB + 2U, // MSUBF_D + 2U, // MSUBF_S + 2U, // MSUBR_Q_H + 2U, // MSUBR_Q_W + 0U, // MSUBU + 0U, // MSUBU_DSP + 0U, // MSUBU_MM + 2U, // MSUBV_B + 2U, // MSUBV_D + 2U, // MSUBV_H + 2U, // MSUBV_W + 20U, // MSUB_D32 + 20U, // MSUB_D32_MM + 20U, // MSUB_D64 + 0U, // MSUB_DSP + 0U, // MSUB_MM + 2U, // MSUB_Q_H + 2U, // MSUB_Q_W + 20U, // MSUB_S + 20U, // MSUB_S_MM + 1U, // MTC0 + 0U, // MTC1 + 0U, // MTC1_MM + 1U, // MTC2 + 0U, // MTHC1_D32 + 0U, // MTHC1_D64 + 0U, // MTHC1_MM + 0U, // MTHI + 0U, // MTHI64 + 0U, // MTHI_DSP + 0U, // MTHI_MM + 0U, // MTHLIP + 0U, // MTLO + 0U, // MTLO64 + 0U, // MTLO_DSP + 0U, // MTLO_MM + 0U, // MTM0 + 0U, // MTM1 + 0U, // MTM2 + 0U, // MTP0 + 0U, // MTP1 + 0U, // MTP2 + 0U, // MUH + 0U, // MUHU + 0U, // MUL + 0U, // MULEQ_S_W_PHL + 0U, // MULEQ_S_W_PHR + 0U, // MULEU_S_PH_QBL + 0U, // MULEU_S_PH_QBR + 0U, // MULQ_RS_PH + 0U, // MULQ_RS_W + 0U, // MULQ_S_PH + 0U, // MULQ_S_W + 0U, // MULR_Q_H + 0U, // MULR_Q_W + 0U, // MULSAQ_S_W_PH + 0U, // MULSA_W_PH + 0U, // MULT + 0U, // MULTU_DSP + 0U, // MULT_DSP + 0U, // MULT_MM + 0U, // MULTu + 0U, // MULTu_MM + 0U, // MULU + 0U, // MULV_B + 0U, // MULV_D + 0U, // MULV_H + 0U, // MULV_W + 0U, // MUL_MM + 0U, // MUL_PH + 0U, // MUL_Q_H + 0U, // MUL_Q_W + 0U, // MUL_R6 + 0U, // MUL_S_PH + 0U, // Mfhi16 + 0U, // Mflo16 + 0U, // Move32R16 + 0U, // MoveR3216 + 0U, // MultRxRy16 + 0U, // MultRxRyRz16 + 0U, // MultuRxRy16 + 0U, // MultuRxRyRz16 + 0U, // NLOC_B + 0U, // NLOC_D + 0U, // NLOC_H + 0U, // NLOC_W + 0U, // NLZC_B + 0U, // NLZC_D + 0U, // NLZC_H + 0U, // NLZC_W + 20U, // NMADD_D32 + 20U, // NMADD_D32_MM + 20U, // NMADD_D64 + 20U, // NMADD_S + 20U, // NMADD_S_MM + 20U, // NMSUB_D32 + 20U, // NMSUB_D32_MM + 20U, // NMSUB_D64 + 20U, // NMSUB_S + 20U, // NMSUB_S_MM + 0U, // NOP + 0U, // NOR + 0U, // NOR64 + 0U, // NORI_B + 0U, // NOR_MM + 0U, // NOR_V + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 0U, // NOT16_MM + 0U, // NegRxRy16 + 0U, // NotRxRy16 + 0U, // OR + 0U, // OR16_MM + 0U, // OR64 + 0U, // ORI_B + 0U, // OR_MM + 0U, // OR_V + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 1U, // ORi + 1U, // ORi64 + 1U, // ORi_MM + 0U, // OrRxRxRy16 + 0U, // PACKRL_PH + 0U, // PAUSE + 0U, // PAUSE_MM + 0U, // PCKEV_B + 0U, // PCKEV_D + 0U, // PCKEV_H + 0U, // PCKEV_W + 0U, // PCKOD_B + 0U, // PCKOD_D + 0U, // PCKOD_H + 0U, // PCKOD_W + 0U, // PCNT_B + 0U, // PCNT_D + 0U, // PCNT_H + 0U, // PCNT_W + 0U, // PICK_PH + 0U, // PICK_QB + 0U, // POP + 0U, // PRECEQU_PH_QBL + 0U, // PRECEQU_PH_QBLA + 0U, // PRECEQU_PH_QBR + 0U, // PRECEQU_PH_QBRA + 0U, // PRECEQ_W_PHL + 0U, // PRECEQ_W_PHR + 0U, // PRECEU_PH_QBL + 0U, // PRECEU_PH_QBLA + 0U, // PRECEU_PH_QBR + 0U, // PRECEU_PH_QBRA + 0U, // PRECRQU_S_QB_PH + 0U, // PRECRQ_PH_W + 0U, // PRECRQ_QB_PH + 0U, // PRECRQ_RS_PH_W + 0U, // PRECR_QB_PH + 1U, // PRECR_SRA_PH_W + 1U, // PRECR_SRA_R_PH_W + 0U, // PREF + 0U, // PREF_MM + 0U, // PREF_R6 + 1U, // PREPEND + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 0U, // PseudoCVT_D32_W + 0U, // PseudoCVT_D64_L + 0U, // PseudoCVT_D64_W + 0U, // PseudoCVT_S_L + 0U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMULT + 0U, // PseudoMULTu + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 0U, // PseudoUDIV + 0U, // RADDU_W_QB + 0U, // RDDSP + 0U, // RDHWR + 0U, // RDHWR64 + 0U, // RDHWR_MM + 0U, // REPLV_PH + 0U, // REPLV_QB + 0U, // REPL_PH + 0U, // REPL_QB + 0U, // RINT_D + 0U, // RINT_S + 1U, // ROTR + 0U, // ROTRV + 0U, // ROTRV_MM + 1U, // ROTR_MM + 0U, // ROUND_L_D64 + 0U, // ROUND_L_S + 0U, // ROUND_W_D32 + 0U, // ROUND_W_D64 + 0U, // ROUND_W_MM + 0U, // ROUND_W_S + 0U, // ROUND_W_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 0U, // RetRA + 0U, // RetRA16 + 1U, // SAT_S_B + 1U, // SAT_S_D + 0U, // SAT_S_H + 1U, // SAT_S_W + 1U, // SAT_U_B + 1U, // SAT_U_D + 0U, // SAT_U_H + 1U, // SAT_U_W + 0U, // SB + 0U, // SB16_MM + 0U, // SB64 + 0U, // SB_MM + 0U, // SC + 0U, // SCD + 0U, // SCD_R6 + 0U, // SC_MM + 0U, // SC_R6 + 0U, // SD + 0U, // SDBBP + 0U, // SDBBP16_MM + 0U, // SDBBP_MM + 0U, // SDBBP_R6 + 0U, // SDC1 + 0U, // SDC164 + 0U, // SDC1_MM + 0U, // SDC2 + 0U, // SDC2_R6 + 0U, // SDC3 + 0U, // SDIV + 0U, // SDIV_MM + 0U, // SDL + 0U, // SDR + 0U, // SDXC1 + 0U, // SDXC164 + 0U, // SEB + 0U, // SEB64 + 0U, // SEB_MM + 0U, // SEH + 0U, // SEH64 + 0U, // SEH_MM + 0U, // SELEQZ + 0U, // SELEQZ64 + 0U, // SELEQZ_D + 0U, // SELEQZ_S + 0U, // SELNEZ + 0U, // SELNEZ64 + 0U, // SELNEZ_D + 0U, // SELNEZ_S + 2U, // SEL_D + 2U, // SEL_S + 0U, // SEQ + 0U, // SEQi + 0U, // SH + 0U, // SH16_MM + 0U, // SH64 + 0U, // SHF_B + 0U, // SHF_H + 0U, // SHF_W + 0U, // SHILO + 0U, // SHILOV + 0U, // SHLLV_PH + 0U, // SHLLV_QB + 0U, // SHLLV_S_PH + 0U, // SHLLV_S_W + 1U, // SHLL_PH + 1U, // SHLL_QB + 1U, // SHLL_S_PH + 1U, // SHLL_S_W + 0U, // SHRAV_PH + 0U, // SHRAV_QB + 0U, // SHRAV_R_PH + 0U, // SHRAV_R_QB + 0U, // SHRAV_R_W + 1U, // SHRA_PH + 1U, // SHRA_QB + 1U, // SHRA_R_PH + 1U, // SHRA_R_QB + 1U, // SHRA_R_W + 0U, // SHRLV_PH + 0U, // SHRLV_QB + 1U, // SHRL_PH + 1U, // SHRL_QB + 0U, // SH_MM + 9U, // SLDI_B + 9U, // SLDI_D + 9U, // SLDI_H + 9U, // SLDI_W + 10U, // SLD_B + 10U, // SLD_D + 10U, // SLD_H + 10U, // SLD_W + 1U, // SLL + 0U, // SLL16_MM + 0U, // SLL64_32 + 0U, // SLL64_64 + 0U, // SLLI_B + 0U, // SLLI_D + 0U, // SLLI_H + 0U, // SLLI_W + 0U, // SLLV + 0U, // SLLV_MM + 0U, // SLL_B + 0U, // SLL_D + 0U, // SLL_H + 1U, // SLL_MM + 0U, // SLL_W + 0U, // SLT + 0U, // SLT64 + 0U, // SLT_MM + 0U, // SLTi + 0U, // SLTi64 + 0U, // SLTi_MM + 0U, // SLTiu + 0U, // SLTiu64 + 0U, // SLTiu_MM + 0U, // SLTu + 0U, // SLTu64 + 0U, // SLTu_MM + 0U, // SNE + 0U, // SNEi + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 8U, // SPLATI_B + 8U, // SPLATI_D + 8U, // SPLATI_H + 8U, // SPLATI_W + 8U, // SPLAT_B + 8U, // SPLAT_D + 8U, // SPLAT_H + 8U, // SPLAT_W + 1U, // SRA + 0U, // SRAI_B + 0U, // SRAI_D + 0U, // SRAI_H + 0U, // SRAI_W + 1U, // SRARI_B + 1U, // SRARI_D + 0U, // SRARI_H + 1U, // SRARI_W + 0U, // SRAR_B + 0U, // SRAR_D + 0U, // SRAR_H + 0U, // SRAR_W + 0U, // SRAV + 0U, // SRAV_MM + 0U, // SRA_B + 0U, // SRA_D + 0U, // SRA_H + 1U, // SRA_MM + 0U, // SRA_W + 1U, // SRL + 0U, // SRL16_MM + 0U, // SRLI_B + 0U, // SRLI_D + 0U, // SRLI_H + 0U, // SRLI_W + 1U, // SRLRI_B + 1U, // SRLRI_D + 0U, // SRLRI_H + 1U, // SRLRI_W + 0U, // SRLR_B + 0U, // SRLR_D + 0U, // SRLR_H + 0U, // SRLR_W + 0U, // SRLV + 0U, // SRLV_MM + 0U, // SRL_B + 0U, // SRL_D + 0U, // SRL_H + 1U, // SRL_MM + 0U, // SRL_W + 0U, // SSNOP + 0U, // SSNOP_MM + 0U, // STORE_ACC128 + 0U, // STORE_ACC64 + 0U, // STORE_ACC64DSP + 0U, // STORE_CCOND_DSP + 0U, // ST_B + 0U, // ST_D + 0U, // ST_H + 0U, // ST_W + 0U, // SUB + 0U, // SUBQH_PH + 0U, // SUBQH_R_PH + 0U, // SUBQH_R_W + 0U, // SUBQH_W + 0U, // SUBQ_PH + 0U, // SUBQ_S_PH + 0U, // SUBQ_S_W + 0U, // SUBSUS_U_B + 0U, // SUBSUS_U_D + 0U, // SUBSUS_U_H + 0U, // SUBSUS_U_W + 0U, // SUBSUU_S_B + 0U, // SUBSUU_S_D + 0U, // SUBSUU_S_H + 0U, // SUBSUU_S_W + 0U, // SUBS_S_B + 0U, // SUBS_S_D + 0U, // SUBS_S_H + 0U, // SUBS_S_W + 0U, // SUBS_U_B + 0U, // SUBS_U_D + 0U, // SUBS_U_H + 0U, // SUBS_U_W + 0U, // SUBU16_MM + 0U, // SUBUH_QB + 0U, // SUBUH_R_QB + 0U, // SUBU_PH + 0U, // SUBU_QB + 0U, // SUBU_S_PH + 0U, // SUBU_S_QB + 0U, // SUBVI_B + 0U, // SUBVI_D + 0U, // SUBVI_H + 0U, // SUBVI_W + 0U, // SUBV_B + 0U, // SUBV_D + 0U, // SUBV_H + 0U, // SUBV_W + 0U, // SUB_MM + 0U, // SUBu + 0U, // SUBu_MM + 0U, // SUXC1 + 0U, // SUXC164 + 0U, // SUXC1_MM + 0U, // SW + 0U, // SW16_MM + 0U, // SW64 + 0U, // SWC1 + 0U, // SWC1_MM + 0U, // SWC2 + 0U, // SWC2_R6 + 0U, // SWC3 + 0U, // SWL + 0U, // SWL64 + 0U, // SWL_MM + 0U, // SWM16_MM + 0U, // SWM32_MM + 0U, // SWM_MM + 0U, // SWP_MM + 0U, // SWR + 0U, // SWR64 + 0U, // SWR_MM + 0U, // SWSP_MM + 0U, // SWXC1 + 0U, // SWXC1_MM + 0U, // SW_MM + 0U, // SYNC + 0U, // SYNCI + 0U, // SYNC_MM + 0U, // SYSCALL + 0U, // SYSCALL_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 0U, // Save16 + 0U, // SaveX16 + 0U, // SbRxRyOffMemX16 + 0U, // SebRx16 + 0U, // SehRx16 + 0U, // SelBeqZ + 0U, // SelBneZ + 0U, // SelTBteqZCmp + 0U, // SelTBteqZCmpi + 0U, // SelTBteqZSlt + 0U, // SelTBteqZSlti + 0U, // SelTBteqZSltiu + 0U, // SelTBteqZSltu + 0U, // SelTBtneZCmp + 0U, // SelTBtneZCmpi + 0U, // SelTBtneZSlt + 0U, // SelTBtneZSlti + 0U, // SelTBtneZSltiu + 0U, // SelTBtneZSltu + 0U, // ShRxRyOffMemX16 + 1U, // SllX16 + 0U, // SllvRxRy16 + 0U, // SltCCRxRy16 + 0U, // SltRxRy16 + 0U, // SltiCCRxImmX16 + 0U, // SltiRxImm16 + 0U, // SltiRxImmX16 + 0U, // SltiuCCRxImmX16 + 0U, // SltiuRxImm16 + 0U, // SltiuRxImmX16 + 0U, // SltuCCRxRy16 + 0U, // SltuRxRy16 + 0U, // SltuRxRyRz16 + 1U, // SraX16 + 0U, // SravRxRy16 + 1U, // SrlX16 + 0U, // SrlvRxRy16 + 0U, // SubuRxRyRz16 + 0U, // SwRxRyOffMemX16 + 0U, // SwRxSpImmX16 + 0U, // TAILCALL + 0U, // TAILCALL64_R + 0U, // TAILCALL_R + 1U, // TEQ + 0U, // TEQI + 0U, // TEQI_MM + 1U, // TEQ_MM + 1U, // TGE + 0U, // TGEI + 0U, // TGEIU + 0U, // TGEIU_MM + 0U, // TGEI_MM + 1U, // TGEU + 1U, // TGEU_MM + 1U, // TGE_MM + 0U, // TLBP + 0U, // TLBP_MM + 0U, // TLBR + 0U, // TLBR_MM + 0U, // TLBWI + 0U, // TLBWI_MM + 0U, // TLBWR + 0U, // TLBWR_MM + 1U, // TLT + 0U, // TLTI + 0U, // TLTIU_MM + 0U, // TLTI_MM + 1U, // TLTU + 1U, // TLTU_MM + 1U, // TLT_MM + 1U, // TNE + 0U, // TNEI + 0U, // TNEI_MM + 1U, // TNE_MM + 0U, // TRAP + 0U, // TRUNC_L_D64 + 0U, // TRUNC_L_S + 0U, // TRUNC_W_D32 + 0U, // TRUNC_W_D64 + 0U, // TRUNC_W_MM + 0U, // TRUNC_W_S + 0U, // TRUNC_W_S_MM + 0U, // TTLTIU + 0U, // UDIV + 0U, // UDIV_MM + 0U, // V3MULU + 0U, // VMM0 + 0U, // VMULU + 2U, // VSHF_B + 2U, // VSHF_D + 2U, // VSHF_H + 2U, // VSHF_W + 0U, // WAIT + 0U, // WAIT_MM + 0U, // WRDSP + 0U, // WSBH + 0U, // WSBH_MM + 0U, // XOR + 0U, // XOR16_MM + 0U, // XOR64 + 0U, // XORI_B + 0U, // XOR_MM + 0U, // XOR_V + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 1U, // XORi + 1U, // XORi64 + 1U, // XORi_MM + 0U, // XorRxRxRy16 + 0U}; #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0, - /* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0, - /* 15 */ 'd', 'm', 't', 'c', '0', 9, 0, - /* 22 */ 'v', 'm', 'm', '0', 9, 0, - /* 28 */ 'm', 't', 'm', '0', 9, 0, - /* 34 */ 'm', 't', 'p', '0', 9, 0, - /* 40 */ 'b', 'b', 'i', 't', '0', 9, 0, - /* 47 */ 'l', 'd', 'c', '1', 9, 0, - /* 53 */ 's', 'd', 'c', '1', 9, 0, - /* 59 */ 'c', 'f', 'c', '1', 9, 0, - /* 65 */ 'd', 'm', 'f', 'c', '1', 9, 0, - /* 72 */ 'm', 'f', 'h', 'c', '1', 9, 0, - /* 79 */ 'm', 't', 'h', 'c', '1', 9, 0, - /* 86 */ 'c', 't', 'c', '1', 9, 0, - /* 92 */ 'd', 'm', 't', 'c', '1', 9, 0, - /* 99 */ 'l', 'w', 'c', '1', 9, 0, - /* 105 */ 's', 'w', 'c', '1', 9, 0, - /* 111 */ 'l', 'd', 'x', 'c', '1', 9, 0, - /* 118 */ 's', 'd', 'x', 'c', '1', 9, 0, - /* 125 */ 'l', 'u', 'x', 'c', '1', 9, 0, - /* 132 */ 's', 'u', 'x', 'c', '1', 9, 0, - /* 139 */ 'l', 'w', 'x', 'c', '1', 9, 0, - /* 146 */ 's', 'w', 'x', 'c', '1', 9, 0, - /* 153 */ 'm', 't', 'm', '1', 9, 0, - /* 159 */ 'm', 't', 'p', '1', 9, 0, - /* 165 */ 'b', 'b', 'i', 't', '1', 9, 0, - /* 172 */ 'b', 'b', 'i', 't', '0', '3', '2', 9, 0, - /* 181 */ 'b', 'b', 'i', 't', '1', '3', '2', 9, 0, - /* 190 */ 'd', 's', 'r', 'a', '3', '2', 9, 0, - /* 198 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0, - /* 208 */ 'd', 's', 'l', 'l', '3', '2', 9, 0, - /* 216 */ 'd', 's', 'r', 'l', '3', '2', 9, 0, - /* 224 */ 'l', 'w', 'm', '3', '2', 9, 0, - /* 231 */ 's', 'w', 'm', '3', '2', 9, 0, - /* 238 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0, - /* 247 */ 'l', 'd', 'c', '2', 9, 0, - /* 253 */ 's', 'd', 'c', '2', 9, 0, - /* 259 */ 'd', 'm', 'f', 'c', '2', 9, 0, - /* 266 */ 'd', 'm', 't', 'c', '2', 9, 0, - /* 273 */ 'l', 'w', 'c', '2', 9, 0, - /* 279 */ 's', 'w', 'c', '2', 9, 0, - /* 285 */ 'm', 't', 'm', '2', 9, 0, - /* 291 */ 'm', 't', 'p', '2', 9, 0, - /* 297 */ 'a', 'd', 'd', 'i', 'u', 'r', '2', 9, 0, - /* 306 */ 'l', 'd', 'c', '3', 9, 0, - /* 312 */ 's', 'd', 'c', '3', 9, 0, - /* 318 */ 'l', 'w', 'c', '3', 9, 0, - /* 324 */ 's', 'w', 'c', '3', 9, 0, - /* 330 */ 'a', 'd', 'd', 'i', 'u', 's', '5', 9, 0, - /* 339 */ 's', 'b', '1', '6', 9, 0, - /* 345 */ 'a', 'n', 'd', '1', '6', 9, 0, - /* 352 */ 's', 'h', '1', '6', 9, 0, - /* 358 */ 'a', 'n', 'd', 'i', '1', '6', 9, 0, - /* 366 */ 'l', 'i', '1', '6', 9, 0, - /* 372 */ 'b', 'r', 'e', 'a', 'k', '1', '6', 9, 0, - /* 381 */ 's', 'l', 'l', '1', '6', 9, 0, - /* 388 */ 's', 'r', 'l', '1', '6', 9, 0, - /* 395 */ 'l', 'w', 'm', '1', '6', 9, 0, - /* 402 */ 's', 'w', 'm', '1', '6', 9, 0, - /* 409 */ 's', 'd', 'b', 'b', 'p', '1', '6', 9, 0, - /* 418 */ 'j', 'r', '1', '6', 9, 0, - /* 424 */ 'x', 'o', 'r', '1', '6', 9, 0, - /* 431 */ 'j', 'a', 'l', 'r', 's', '1', '6', 9, 0, - /* 440 */ 'n', 'o', 't', '1', '6', 9, 0, - /* 447 */ 'l', 'b', 'u', '1', '6', 9, 0, - /* 454 */ 's', 'u', 'b', 'u', '1', '6', 9, 0, - /* 462 */ 'a', 'd', 'd', 'u', '1', '6', 9, 0, - /* 470 */ 'l', 'h', 'u', '1', '6', 9, 0, - /* 477 */ 'l', 'w', '1', '6', 9, 0, - /* 483 */ 's', 'w', '1', '6', 9, 0, - /* 489 */ 'b', 'n', 'e', 'z', '1', '6', 9, 0, - /* 497 */ 'b', 'e', 'q', 'z', '1', '6', 9, 0, - /* 505 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, - /* 521 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, - /* 538 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, - /* 554 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, - /* 571 */ 'd', 's', 'r', 'a', 9, 0, - /* 577 */ 'd', 'l', 's', 'a', 9, 0, - /* 583 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0, - /* 591 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0, - /* 599 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0, - /* 608 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0, - /* 617 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0, - /* 627 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0, - /* 636 */ 's', 'r', 'a', '.', 'b', 9, 0, - /* 643 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0, - /* 651 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0, - /* 659 */ 's', 'l', 'd', '.', 'b', 9, 0, - /* 666 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0, - /* 675 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0, - /* 684 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0, - /* 693 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0, - /* 701 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0, - /* 709 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0, - /* 717 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0, - /* 725 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0, - /* 733 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0, - /* 742 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0, - /* 751 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0, - /* 759 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0, - /* 767 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0, - /* 777 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0, - /* 785 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0, - /* 794 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0, - /* 803 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0, - /* 812 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0, - /* 820 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0, - /* 828 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0, - /* 838 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0, - /* 848 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0, - /* 857 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0, - /* 866 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0, - /* 875 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0, - /* 883 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0, - /* 892 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0, - /* 900 */ 's', 'l', 'l', '.', 'b', 9, 0, - /* 907 */ 's', 'r', 'l', '.', 'b', 9, 0, - /* 914 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0, - /* 923 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0, - /* 931 */ 'c', 'e', 'q', '.', 'b', 9, 0, - /* 938 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0, - /* 946 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0, - /* 954 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0, - /* 962 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0, - /* 971 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0, - /* 979 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0, - /* 989 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0, - /* 998 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0, - /* 1007 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0, - /* 1016 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0, - /* 1026 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0, - /* 1036 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0, - /* 1046 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0, - /* 1056 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0, - /* 1065 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0, - /* 1075 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0, - /* 1085 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 0, - /* 1095 */ 's', 'a', 't', '_', 's', '.', 'b', 9, 0, - /* 1104 */ 'c', 'l', 't', '_', 's', '.', 'b', 9, 0, - /* 1113 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'b', 9, 0, - /* 1125 */ 'd', 'i', 'v', '_', 's', '.', 'b', 9, 0, - /* 1134 */ 'm', 'a', 'x', '_', 's', '.', 'b', 9, 0, - /* 1143 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'b', 9, 0, - /* 1153 */ 's', 'p', 'l', 'a', 't', '.', 'b', 9, 0, - /* 1162 */ 'b', 's', 'e', 't', '.', 'b', 9, 0, - /* 1170 */ 'p', 'c', 'n', 't', '.', 'b', 9, 0, - /* 1178 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'b', 9, 0, - /* 1188 */ 's', 't', '.', 'b', 9, 0, - /* 1194 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'b', 9, 0, - /* 1204 */ 'm', 'o', 'd', '_', 'u', '.', 'b', 9, 0, - /* 1213 */ 'c', 'l', 'e', '_', 'u', '.', 'b', 9, 0, - /* 1222 */ 'a', 'v', 'e', '_', 'u', '.', 'b', 9, 0, - /* 1231 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1241 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1251 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1261 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'b', 9, 0, - /* 1271 */ 'm', 'i', 'n', '_', 'u', '.', 'b', 9, 0, - /* 1280 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'b', 9, 0, - /* 1290 */ 's', 'u', 'b', 's', '_', 'u', '.', 'b', 9, 0, - /* 1300 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'b', 9, 0, - /* 1310 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'b', 9, 0, - /* 1322 */ 's', 'a', 't', '_', 'u', '.', 'b', 9, 0, - /* 1331 */ 'c', 'l', 't', '_', 'u', '.', 'b', 9, 0, - /* 1340 */ 'd', 'i', 'v', '_', 'u', '.', 'b', 9, 0, - /* 1349 */ 'm', 'a', 'x', '_', 'u', '.', 'b', 9, 0, - /* 1358 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'b', 9, 0, - /* 1368 */ 'm', 's', 'u', 'b', 'v', '.', 'b', 9, 0, - /* 1377 */ 'm', 'a', 'd', 'd', 'v', '.', 'b', 9, 0, - /* 1386 */ 'p', 'c', 'k', 'e', 'v', '.', 'b', 9, 0, - /* 1395 */ 'i', 'l', 'v', 'e', 'v', '.', 'b', 9, 0, - /* 1404 */ 'm', 'u', 'l', 'v', '.', 'b', 9, 0, - /* 1412 */ 'b', 'z', '.', 'b', 9, 0, - /* 1418 */ 'b', 'n', 'z', '.', 'b', 9, 0, - /* 1425 */ 's', 'e', 'b', 9, 0, - /* 1430 */ 'j', 'r', '.', 'h', 'b', 9, 0, - /* 1437 */ 'j', 'a', 'l', 'r', '.', 'h', 'b', 9, 0, - /* 1446 */ 'l', 'b', 9, 0, - /* 1450 */ 's', 'h', 'r', 'a', '.', 'q', 'b', 9, 0, - /* 1459 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, - /* 1473 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, - /* 1486 */ 'c', 'm', 'p', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, - /* 1498 */ 's', 'u', 'b', 'u', 'h', '.', 'q', 'b', 9, 0, - /* 1508 */ 'a', 'd', 'd', 'u', 'h', '.', 'q', 'b', 9, 0, - /* 1518 */ 'p', 'i', 'c', 'k', '.', 'q', 'b', 9, 0, - /* 1527 */ 's', 'h', 'l', 'l', '.', 'q', 'b', 9, 0, - /* 1536 */ 'r', 'e', 'p', 'l', '.', 'q', 'b', 9, 0, - /* 1545 */ 's', 'h', 'r', 'l', '.', 'q', 'b', 9, 0, - /* 1554 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, - /* 1568 */ 'c', 'm', 'p', 'g', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, - /* 1581 */ 'c', 'm', 'p', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, - /* 1593 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1604 */ 's', 'u', 'b', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1616 */ 'a', 'd', 'd', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1628 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'q', 'b', 9, 0, - /* 1640 */ 'a', 'b', 's', 'q', '_', 's', '.', 'q', 'b', 9, 0, - /* 1651 */ 's', 'u', 'b', 'u', '_', 's', '.', 'q', 'b', 9, 0, - /* 1662 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'q', 'b', 9, 0, - /* 1673 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, - /* 1687 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, - /* 1700 */ 'c', 'm', 'p', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, - /* 1712 */ 's', 'u', 'b', 'u', '.', 'q', 'b', 9, 0, - /* 1721 */ 'a', 'd', 'd', 'u', '.', 'q', 'b', 9, 0, - /* 1730 */ 's', 'h', 'r', 'a', 'v', '.', 'q', 'b', 9, 0, - /* 1740 */ 's', 'h', 'l', 'l', 'v', '.', 'q', 'b', 9, 0, - /* 1750 */ 'r', 'e', 'p', 'l', 'v', '.', 'q', 'b', 9, 0, - /* 1760 */ 's', 'h', 'r', 'l', 'v', '.', 'q', 'b', 9, 0, - /* 1770 */ 'r', 'a', 'd', 'd', 'u', '.', 'w', '.', 'q', 'b', 9, 0, - /* 1782 */ 's', 'b', 9, 0, - /* 1786 */ 'm', 'o', 'd', 's', 'u', 'b', 9, 0, - /* 1794 */ 'm', 's', 'u', 'b', 9, 0, - /* 1800 */ 'b', 'c', 9, 0, - /* 1804 */ 'b', 'g', 'e', 'c', 9, 0, - /* 1810 */ 'b', 'n', 'e', 'c', 9, 0, - /* 1816 */ 'j', 'i', 'c', 9, 0, - /* 1821 */ 'b', 'a', 'l', 'c', 9, 0, - /* 1827 */ 'j', 'i', 'a', 'l', 'c', 9, 0, - /* 1834 */ 'b', 'g', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1843 */ 'b', 'l', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1852 */ 'b', 'n', 'e', 'z', 'a', 'l', 'c', 9, 0, - /* 1861 */ 'b', 'e', 'q', 'z', 'a', 'l', 'c', 9, 0, - /* 1870 */ 'b', 'g', 't', 'z', 'a', 'l', 'c', 9, 0, - /* 1879 */ 'b', 'l', 't', 'z', 'a', 'l', 'c', 9, 0, - /* 1888 */ 'l', 'd', 'p', 'c', 9, 0, - /* 1894 */ 'a', 'u', 'i', 'p', 'c', 9, 0, - /* 1901 */ 'a', 'l', 'u', 'i', 'p', 'c', 9, 0, - /* 1909 */ 'a', 'd', 'd', 'i', 'u', 'p', 'c', 9, 0, - /* 1918 */ 'l', 'w', 'u', 'p', 'c', 9, 0, - /* 1925 */ 'l', 'w', 'p', 'c', 9, 0, - /* 1931 */ 'b', 'e', 'q', 'c', 9, 0, - /* 1937 */ 'j', 'r', 'c', 9, 0, - /* 1942 */ 'a', 'd', 'd', 's', 'c', 9, 0, - /* 1949 */ 'b', 'l', 't', 'c', 9, 0, - /* 1955 */ 'b', 'g', 'e', 'u', 'c', 9, 0, - /* 1962 */ 'b', 'l', 't', 'u', 'c', 9, 0, - /* 1969 */ 'b', 'n', 'v', 'c', 9, 0, - /* 1975 */ 'b', 'o', 'v', 'c', 9, 0, - /* 1981 */ 'a', 'd', 'd', 'w', 'c', 9, 0, - /* 1988 */ 'b', 'g', 'e', 'z', 'c', 9, 0, - /* 1995 */ 'b', 'l', 'e', 'z', 'c', 9, 0, - /* 2002 */ 'b', 'n', 'e', 'z', 'c', 9, 0, - /* 2009 */ 'b', 'e', 'q', 'z', 'c', 9, 0, - /* 2016 */ 'b', 'g', 't', 'z', 'c', 9, 0, - /* 2023 */ 'b', 'l', 't', 'z', 'c', 9, 0, - /* 2030 */ 'f', 'l', 'o', 'g', '2', '.', 'd', 9, 0, - /* 2039 */ 'f', 'e', 'x', 'p', '2', '.', 'd', 9, 0, - /* 2048 */ 'a', 'd', 'd', '_', 'a', '.', 'd', 9, 0, - /* 2057 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'd', 9, 0, - /* 2067 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'd', 9, 0, - /* 2077 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'd', 9, 0, - /* 2087 */ 'm', 'i', 'n', 'a', '.', 'd', 9, 0, - /* 2095 */ 's', 'r', 'a', '.', 'd', 9, 0, - /* 2102 */ 'm', 'a', 'x', 'a', '.', 'd', 9, 0, - /* 2110 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, - /* 2118 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 2127 */ 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 2136 */ 'n', 'l', 'o', 'c', '.', 'd', 9, 0, - /* 2144 */ 'n', 'l', 'z', 'c', '.', 'd', 9, 0, - /* 2152 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 2160 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 2169 */ 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 2178 */ 's', 'l', 'd', '.', 'd', 9, 0, - /* 2185 */ 'p', 'c', 'k', 'o', 'd', '.', 'd', 9, 0, - /* 2194 */ 'i', 'l', 'v', 'o', 'd', '.', 'd', 9, 0, - /* 2203 */ 'c', '.', 'n', 'g', 'e', '.', 'd', 9, 0, - /* 2212 */ 'c', '.', 'l', 'e', '.', 'd', 9, 0, - /* 2220 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'd', 9, 0, - /* 2230 */ 'f', 'c', 'l', 'e', '.', 'd', 9, 0, - /* 2238 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 'd', 9, 0, - /* 2248 */ 'c', '.', 'o', 'l', 'e', '.', 'd', 9, 0, - /* 2257 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 'd', 9, 0, - /* 2268 */ 'f', 's', 'l', 'e', '.', 'd', 9, 0, - /* 2276 */ 'c', '.', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2285 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2296 */ 'f', 'c', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2305 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2317 */ 'f', 's', 'u', 'l', 'e', '.', 'd', 9, 0, - /* 2326 */ 'f', 'c', 'n', 'e', '.', 'd', 9, 0, - /* 2334 */ 'f', 's', 'n', 'e', '.', 'd', 9, 0, - /* 2342 */ 'f', 'c', 'u', 'n', 'e', '.', 'd', 9, 0, - /* 2351 */ 'f', 's', 'u', 'n', 'e', '.', 'd', 9, 0, - /* 2360 */ 'i', 'n', 's', 'v', 'e', '.', 'd', 9, 0, - /* 2369 */ 'c', '.', 'f', '.', 'd', 9, 0, - /* 2376 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 'd', 9, 0, - /* 2386 */ 'f', 'c', 'a', 'f', '.', 'd', 9, 0, - /* 2394 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 'd', 9, 0, - /* 2405 */ 'f', 's', 'a', 'f', '.', 'd', 9, 0, - /* 2413 */ 'm', 's', 'u', 'b', 'f', '.', 'd', 9, 0, - /* 2422 */ 'm', 'a', 'd', 'd', 'f', '.', 'd', 9, 0, - /* 2431 */ 'v', 's', 'h', 'f', '.', 'd', 9, 0, - /* 2439 */ 'c', '.', 's', 'f', '.', 'd', 9, 0, - /* 2447 */ 'm', 'o', 'v', 'f', '.', 'd', 9, 0, - /* 2455 */ 'b', 'n', 'e', 'g', '.', 'd', 9, 0, - /* 2463 */ 's', 'r', 'a', 'i', '.', 'd', 9, 0, - /* 2471 */ 's', 'l', 'd', 'i', '.', 'd', 9, 0, - /* 2479 */ 'b', 'n', 'e', 'g', 'i', '.', 'd', 9, 0, - /* 2488 */ 's', 'l', 'l', 'i', '.', 'd', 9, 0, - /* 2496 */ 's', 'r', 'l', 'i', '.', 'd', 9, 0, - /* 2504 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'd', 9, 0, - /* 2514 */ 'c', 'e', 'q', 'i', '.', 'd', 9, 0, - /* 2522 */ 's', 'r', 'a', 'r', 'i', '.', 'd', 9, 0, - /* 2531 */ 'b', 'c', 'l', 'r', 'i', '.', 'd', 9, 0, - /* 2540 */ 's', 'r', 'l', 'r', 'i', '.', 'd', 9, 0, - /* 2549 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'd', 9, 0, - /* 2559 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'd', 9, 0, - /* 2569 */ 'b', 's', 'e', 't', 'i', '.', 'd', 9, 0, - /* 2578 */ 's', 'u', 'b', 'v', 'i', '.', 'd', 9, 0, - /* 2587 */ 'a', 'd', 'd', 'v', 'i', '.', 'd', 9, 0, - /* 2596 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 'd', 9, 0, - /* 2607 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 'd', 9, 0, - /* 2618 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 'd', 9, 0, - /* 2628 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 'd', 9, 0, - /* 2639 */ 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, - /* 2648 */ 's', 'e', 'l', '.', 'd', 9, 0, - /* 2655 */ 'c', '.', 'n', 'g', 'l', '.', 'd', 9, 0, - /* 2664 */ 'f', 'i', 'l', 'l', '.', 'd', 9, 0, - /* 2672 */ 's', 'l', 'l', '.', 'd', 9, 0, - /* 2679 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'd', 9, 0, - /* 2689 */ 'f', 'f', 'q', 'l', '.', 'd', 9, 0, - /* 2697 */ 's', 'r', 'l', '.', 'd', 9, 0, - /* 2704 */ 'b', 'i', 'n', 's', 'l', '.', 'd', 9, 0, - /* 2713 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, - /* 2721 */ 'i', 'l', 'v', 'l', '.', 'd', 9, 0, - /* 2729 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, - /* 2737 */ 'c', '.', 'u', 'n', '.', 'd', 9, 0, - /* 2745 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 'd', 9, 0, - /* 2755 */ 'f', 'c', 'u', 'n', '.', 'd', 9, 0, - /* 2763 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 'd', 9, 0, - /* 2774 */ 'f', 's', 'u', 'n', '.', 'd', 9, 0, - /* 2782 */ 'm', 'o', 'v', 'n', '.', 'd', 9, 0, - /* 2790 */ 'f', 'r', 'c', 'p', '.', 'd', 9, 0, - /* 2798 */ 'c', '.', 'e', 'q', '.', 'd', 9, 0, - /* 2806 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'd', 9, 0, - /* 2816 */ 'f', 'c', 'e', 'q', '.', 'd', 9, 0, - /* 2824 */ 'c', '.', 's', 'e', 'q', '.', 'd', 9, 0, - /* 2833 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 'd', 9, 0, - /* 2844 */ 'f', 's', 'e', 'q', '.', 'd', 9, 0, - /* 2852 */ 'c', '.', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2861 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2872 */ 'f', 'c', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2881 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2893 */ 'f', 's', 'u', 'e', 'q', '.', 'd', 9, 0, - /* 2902 */ 's', 'r', 'a', 'r', '.', 'd', 9, 0, - /* 2910 */ 'b', 'c', 'l', 'r', '.', 'd', 9, 0, - /* 2918 */ 's', 'r', 'l', 'r', '.', 'd', 9, 0, - /* 2926 */ 'f', 'c', 'o', 'r', '.', 'd', 9, 0, - /* 2934 */ 'f', 's', 'o', 'r', '.', 'd', 9, 0, - /* 2942 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'd', 9, 0, - /* 2952 */ 'f', 'f', 'q', 'r', '.', 'd', 9, 0, - /* 2960 */ 'b', 'i', 'n', 's', 'r', '.', 'd', 9, 0, - /* 2969 */ 'i', 'l', 'v', 'r', '.', 'd', 9, 0, - /* 2977 */ 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, - /* 2986 */ 'a', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, - /* 2996 */ 'h', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, - /* 3006 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, - /* 3017 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'd', 9, 0, - /* 3029 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0, - /* 3039 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0, - /* 3050 */ 'm', 'o', 'd', '_', 's', '.', 'd', 9, 0, - /* 3059 */ 'c', 'l', 'e', '_', 's', '.', 'd', 9, 0, - /* 3068 */ 'a', 'v', 'e', '_', 's', '.', 'd', 9, 0, - /* 3077 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'd', 9, 0, - /* 3087 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'd', 9, 0, - /* 3097 */ 'c', 'l', 't', 'i', '_', 's', '.', 'd', 9, 0, - /* 3107 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'd', 9, 0, - /* 3117 */ 'm', 'i', 'n', '_', 's', '.', 'd', 9, 0, - /* 3126 */ 'd', 'o', 't', 'p', '_', 's', '.', 'd', 9, 0, - /* 3136 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'd', 9, 0, - /* 3146 */ 's', 'u', 'b', 's', '_', 's', '.', 'd', 9, 0, - /* 3156 */ 'a', 'd', 'd', 's', '_', 's', '.', 'd', 9, 0, - /* 3166 */ 's', 'a', 't', '_', 's', '.', 'd', 9, 0, - /* 3175 */ 'c', 'l', 't', '_', 's', '.', 'd', 9, 0, - /* 3184 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0, - /* 3195 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0, - /* 3206 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'd', 9, 0, - /* 3218 */ 'd', 'i', 'v', '_', 's', '.', 'd', 9, 0, - /* 3227 */ 'm', 'a', 'x', '_', 's', '.', 'd', 9, 0, - /* 3236 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'd', 9, 0, - /* 3246 */ 'a', 'b', 's', '.', 'd', 9, 0, - /* 3253 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, - /* 3263 */ 's', 'p', 'l', 'a', 't', '.', 'd', 9, 0, - /* 3272 */ 'b', 's', 'e', 't', '.', 'd', 9, 0, - /* 3280 */ 'c', '.', 'n', 'g', 't', '.', 'd', 9, 0, - /* 3289 */ 'c', '.', 'l', 't', '.', 'd', 9, 0, - /* 3297 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'd', 9, 0, - /* 3307 */ 'f', 'c', 'l', 't', '.', 'd', 9, 0, - /* 3315 */ 'c', '.', 'o', 'l', 't', '.', 'd', 9, 0, - /* 3324 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 'd', 9, 0, - /* 3335 */ 'f', 's', 'l', 't', '.', 'd', 9, 0, - /* 3343 */ 'c', '.', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3352 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3363 */ 'f', 'c', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3372 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3384 */ 'f', 's', 'u', 'l', 't', '.', 'd', 9, 0, - /* 3393 */ 'p', 'c', 'n', 't', '.', 'd', 9, 0, - /* 3401 */ 'f', 'r', 'i', 'n', 't', '.', 'd', 9, 0, - /* 3410 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'd', 9, 0, - /* 3420 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, - /* 3429 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'd', 9, 0, - /* 3439 */ 's', 't', '.', 'd', 9, 0, - /* 3445 */ 'm', 'o', 'v', 't', '.', 'd', 9, 0, - /* 3453 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, - /* 3463 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, - /* 3473 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, - /* 3484 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'd', 9, 0, - /* 3496 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0, - /* 3506 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0, - /* 3517 */ 'm', 'o', 'd', '_', 'u', '.', 'd', 9, 0, - /* 3526 */ 'c', 'l', 'e', '_', 'u', '.', 'd', 9, 0, - /* 3535 */ 'a', 'v', 'e', '_', 'u', '.', 'd', 9, 0, - /* 3544 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'd', 9, 0, - /* 3554 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'd', 9, 0, - /* 3564 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'd', 9, 0, - /* 3574 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'd', 9, 0, - /* 3584 */ 'm', 'i', 'n', '_', 'u', '.', 'd', 9, 0, - /* 3593 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'd', 9, 0, - /* 3603 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'd', 9, 0, - /* 3613 */ 's', 'u', 'b', 's', '_', 'u', '.', 'd', 9, 0, - /* 3623 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'd', 9, 0, - /* 3633 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'd', 9, 0, - /* 3645 */ 's', 'a', 't', '_', 'u', '.', 'd', 9, 0, - /* 3654 */ 'c', 'l', 't', '_', 'u', '.', 'd', 9, 0, - /* 3663 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0, - /* 3674 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0, - /* 3685 */ 'd', 'i', 'v', '_', 'u', '.', 'd', 9, 0, - /* 3694 */ 'm', 'a', 'x', '_', 'u', '.', 'd', 9, 0, - /* 3703 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'd', 9, 0, - /* 3713 */ 'm', 's', 'u', 'b', 'v', '.', 'd', 9, 0, - /* 3722 */ 'm', 'a', 'd', 'd', 'v', '.', 'd', 9, 0, - /* 3731 */ 'p', 'c', 'k', 'e', 'v', '.', 'd', 9, 0, - /* 3740 */ 'i', 'l', 'v', 'e', 'v', '.', 'd', 9, 0, - /* 3749 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, - /* 3757 */ 'm', 'u', 'l', 'v', '.', 'd', 9, 0, - /* 3765 */ 'm', 'o', 'v', '.', 'd', 9, 0, - /* 3772 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 'd', 9, 0, - /* 3783 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 'd', 9, 0, - /* 3794 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 'd', 9, 0, - /* 3804 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 'd', 9, 0, - /* 3815 */ 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, - /* 3824 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, - /* 3832 */ 'b', 'z', '.', 'd', 9, 0, - /* 3838 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 'd', 9, 0, - /* 3848 */ 'b', 'n', 'z', '.', 'd', 9, 0, - /* 3855 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 'd', 9, 0, - /* 3865 */ 'm', 'o', 'v', 'z', '.', 'd', 9, 0, - /* 3873 */ 's', 'c', 'd', 9, 0, - /* 3878 */ 'd', 'a', 'd', 'd', 9, 0, - /* 3884 */ 'm', 'a', 'd', 'd', 9, 0, - /* 3890 */ 'd', 's', 'h', 'd', 9, 0, - /* 3896 */ 'l', 'l', 'd', 9, 0, - /* 3901 */ 'a', 'n', 'd', 9, 0, - /* 3906 */ 'p', 'r', 'e', 'p', 'e', 'n', 'd', 9, 0, - /* 3915 */ 'a', 'p', 'p', 'e', 'n', 'd', 9, 0, - /* 3923 */ 'd', 'm', 'o', 'd', 9, 0, - /* 3929 */ 's', 'd', 9, 0, - /* 3933 */ 't', 'g', 'e', 9, 0, - /* 3938 */ 'c', 'a', 'c', 'h', 'e', 9, 0, - /* 3945 */ 'b', 'n', 'e', 9, 0, - /* 3950 */ 's', 'n', 'e', 9, 0, - /* 3955 */ 't', 'n', 'e', 9, 0, - /* 3960 */ 'm', 'o', 'v', 'e', 9, 0, - /* 3966 */ 'b', 'c', '0', 'f', 9, 0, - /* 3972 */ 'b', 'c', '1', 'f', 9, 0, - /* 3978 */ 'b', 'c', '2', 'f', 9, 0, - /* 3984 */ 'b', 'c', '3', 'f', 9, 0, - /* 3990 */ 'p', 'r', 'e', 'f', 9, 0, - /* 3996 */ 'm', 'o', 'v', 'f', 9, 0, - /* 4002 */ 'n', 'e', 'g', 9, 0, - /* 4007 */ 'a', 'd', 'd', '_', 'a', '.', 'h', 9, 0, - /* 4016 */ 'm', 'i', 'n', '_', 'a', '.', 'h', 9, 0, - /* 4025 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'h', 9, 0, - /* 4035 */ 'm', 'a', 'x', '_', 'a', '.', 'h', 9, 0, - /* 4044 */ 's', 'r', 'a', '.', 'h', 9, 0, - /* 4051 */ 'n', 'l', 'o', 'c', '.', 'h', 9, 0, - /* 4059 */ 'n', 'l', 'z', 'c', '.', 'h', 9, 0, - /* 4067 */ 's', 'l', 'd', '.', 'h', 9, 0, - /* 4074 */ 'p', 'c', 'k', 'o', 'd', '.', 'h', 9, 0, - /* 4083 */ 'i', 'l', 'v', 'o', 'd', '.', 'h', 9, 0, - /* 4092 */ 'i', 'n', 's', 'v', 'e', '.', 'h', 9, 0, - /* 4101 */ 'v', 's', 'h', 'f', '.', 'h', 9, 0, - /* 4109 */ 'b', 'n', 'e', 'g', '.', 'h', 9, 0, - /* 4117 */ 's', 'r', 'a', 'i', '.', 'h', 9, 0, - /* 4125 */ 's', 'l', 'd', 'i', '.', 'h', 9, 0, - /* 4133 */ 'b', 'n', 'e', 'g', 'i', '.', 'h', 9, 0, - /* 4142 */ 's', 'l', 'l', 'i', '.', 'h', 9, 0, - /* 4150 */ 's', 'r', 'l', 'i', '.', 'h', 9, 0, - /* 4158 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'h', 9, 0, - /* 4168 */ 'c', 'e', 'q', 'i', '.', 'h', 9, 0, - /* 4176 */ 's', 'r', 'a', 'r', 'i', '.', 'h', 9, 0, - /* 4185 */ 'b', 'c', 'l', 'r', 'i', '.', 'h', 9, 0, - /* 4194 */ 's', 'r', 'l', 'r', 'i', '.', 'h', 9, 0, - /* 4203 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'h', 9, 0, - /* 4213 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'h', 9, 0, - /* 4223 */ 'b', 's', 'e', 't', 'i', '.', 'h', 9, 0, - /* 4232 */ 's', 'u', 'b', 'v', 'i', '.', 'h', 9, 0, - /* 4241 */ 'a', 'd', 'd', 'v', 'i', '.', 'h', 9, 0, - /* 4250 */ 'f', 'i', 'l', 'l', '.', 'h', 9, 0, - /* 4258 */ 's', 'l', 'l', '.', 'h', 9, 0, - /* 4265 */ 's', 'r', 'l', '.', 'h', 9, 0, - /* 4272 */ 'b', 'i', 'n', 's', 'l', '.', 'h', 9, 0, - /* 4281 */ 'i', 'l', 'v', 'l', '.', 'h', 9, 0, - /* 4289 */ 'f', 'e', 'x', 'd', 'o', '.', 'h', 9, 0, - /* 4298 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'h', 9, 0, - /* 4308 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'h', 9, 0, - /* 4318 */ 'm', 'u', 'l', '_', 'q', '.', 'h', 9, 0, - /* 4327 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'h', 9, 0, - /* 4338 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'h', 9, 0, - /* 4349 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'h', 9, 0, - /* 4359 */ 'c', 'e', 'q', '.', 'h', 9, 0, - /* 4366 */ 'f', 't', 'q', '.', 'h', 9, 0, - /* 4373 */ 's', 'r', 'a', 'r', '.', 'h', 9, 0, - /* 4381 */ 'b', 'c', 'l', 'r', '.', 'h', 9, 0, - /* 4389 */ 's', 'r', 'l', 'r', '.', 'h', 9, 0, - /* 4397 */ 'b', 'i', 'n', 's', 'r', '.', 'h', 9, 0, - /* 4406 */ 'i', 'l', 'v', 'r', '.', 'h', 9, 0, - /* 4414 */ 'a', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, - /* 4424 */ 'h', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, - /* 4434 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, - /* 4445 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0, - /* 4455 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0, - /* 4466 */ 'm', 'o', 'd', '_', 's', '.', 'h', 9, 0, - /* 4475 */ 'c', 'l', 'e', '_', 's', '.', 'h', 9, 0, - /* 4484 */ 'a', 'v', 'e', '_', 's', '.', 'h', 9, 0, - /* 4493 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'h', 9, 0, - /* 4503 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'h', 9, 0, - /* 4513 */ 'c', 'l', 't', 'i', '_', 's', '.', 'h', 9, 0, - /* 4523 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'h', 9, 0, - /* 4533 */ 'm', 'i', 'n', '_', 's', '.', 'h', 9, 0, - /* 4542 */ 'd', 'o', 't', 'p', '_', 's', '.', 'h', 9, 0, - /* 4552 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'h', 9, 0, - /* 4562 */ 'e', 'x', 't', 'r', '_', 's', '.', 'h', 9, 0, - /* 4572 */ 's', 'u', 'b', 's', '_', 's', '.', 'h', 9, 0, - /* 4582 */ 'a', 'd', 'd', 's', '_', 's', '.', 'h', 9, 0, - /* 4592 */ 's', 'a', 't', '_', 's', '.', 'h', 9, 0, - /* 4601 */ 'c', 'l', 't', '_', 's', '.', 'h', 9, 0, - /* 4610 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'h', 9, 0, - /* 4622 */ 'd', 'i', 'v', '_', 's', '.', 'h', 9, 0, - /* 4631 */ 'e', 'x', 't', 'r', 'v', '_', 's', '.', 'h', 9, 0, - /* 4642 */ 'm', 'a', 'x', '_', 's', '.', 'h', 9, 0, - /* 4651 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'h', 9, 0, - /* 4661 */ 's', 'p', 'l', 'a', 't', '.', 'h', 9, 0, - /* 4670 */ 'b', 's', 'e', 't', '.', 'h', 9, 0, - /* 4678 */ 'p', 'c', 'n', 't', '.', 'h', 9, 0, - /* 4686 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'h', 9, 0, - /* 4696 */ 's', 't', '.', 'h', 9, 0, - /* 4702 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0, - /* 4712 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0, - /* 4722 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0, - /* 4733 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0, - /* 4743 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0, - /* 4754 */ 'm', 'o', 'd', '_', 'u', '.', 'h', 9, 0, - /* 4763 */ 'c', 'l', 'e', '_', 'u', '.', 'h', 9, 0, - /* 4772 */ 'a', 'v', 'e', '_', 'u', '.', 'h', 9, 0, - /* 4781 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'h', 9, 0, - /* 4791 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'h', 9, 0, - /* 4801 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'h', 9, 0, - /* 4811 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'h', 9, 0, - /* 4821 */ 'm', 'i', 'n', '_', 'u', '.', 'h', 9, 0, - /* 4830 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'h', 9, 0, - /* 4840 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'h', 9, 0, - /* 4850 */ 's', 'u', 'b', 's', '_', 'u', '.', 'h', 9, 0, - /* 4860 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'h', 9, 0, - /* 4870 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'h', 9, 0, - /* 4882 */ 's', 'a', 't', '_', 'u', '.', 'h', 9, 0, - /* 4891 */ 'c', 'l', 't', '_', 'u', '.', 'h', 9, 0, - /* 4900 */ 'd', 'i', 'v', '_', 'u', '.', 'h', 9, 0, - /* 4909 */ 'm', 'a', 'x', '_', 'u', '.', 'h', 9, 0, - /* 4918 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'h', 9, 0, - /* 4928 */ 'm', 's', 'u', 'b', 'v', '.', 'h', 9, 0, - /* 4937 */ 'm', 'a', 'd', 'd', 'v', '.', 'h', 9, 0, - /* 4946 */ 'p', 'c', 'k', 'e', 'v', '.', 'h', 9, 0, - /* 4955 */ 'i', 'l', 'v', 'e', 'v', '.', 'h', 9, 0, - /* 4964 */ 'm', 'u', 'l', 'v', '.', 'h', 9, 0, - /* 4972 */ 'b', 'z', '.', 'h', 9, 0, - /* 4978 */ 'b', 'n', 'z', '.', 'h', 9, 0, - /* 4985 */ 'd', 's', 'b', 'h', 9, 0, - /* 4991 */ 'w', 's', 'b', 'h', 9, 0, - /* 4997 */ 's', 'e', 'h', 9, 0, - /* 5002 */ 'l', 'h', 9, 0, - /* 5006 */ 's', 'h', 'r', 'a', '.', 'p', 'h', 9, 0, - /* 5015 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'q', 'b', '.', 'p', 'h', 9, 0, - /* 5029 */ 'p', 'r', 'e', 'c', 'r', '.', 'q', 'b', '.', 'p', 'h', 9, 0, - /* 5042 */ 'p', 'r', 'e', 'c', 'r', 'q', 'u', '_', 's', '.', 'q', 'b', '.', 'p', 'h', 9, 0, - /* 5059 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'p', 'h', 9, 0, - /* 5070 */ 's', 'u', 'b', 'q', 'h', '.', 'p', 'h', 9, 0, - /* 5080 */ 'a', 'd', 'd', 'q', 'h', '.', 'p', 'h', 9, 0, - /* 5090 */ 'p', 'i', 'c', 'k', '.', 'p', 'h', 9, 0, - /* 5099 */ 's', 'h', 'l', 'l', '.', 'p', 'h', 9, 0, - /* 5108 */ 'r', 'e', 'p', 'l', '.', 'p', 'h', 9, 0, - /* 5117 */ 's', 'h', 'r', 'l', '.', 'p', 'h', 9, 0, - /* 5126 */ 'p', 'a', 'c', 'k', 'r', 'l', '.', 'p', 'h', 9, 0, - /* 5137 */ 'm', 'u', 'l', '.', 'p', 'h', 9, 0, - /* 5145 */ 's', 'u', 'b', 'q', '.', 'p', 'h', 9, 0, - /* 5154 */ 'a', 'd', 'd', 'q', '.', 'p', 'h', 9, 0, - /* 5163 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'p', 'h', 9, 0, - /* 5174 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'p', 'h', 9, 0, - /* 5185 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0, - /* 5197 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0, - /* 5209 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'p', 'h', 9, 0, - /* 5221 */ 's', 'h', 'l', 'l', '_', 's', '.', 'p', 'h', 9, 0, - /* 5232 */ 'm', 'u', 'l', '_', 's', '.', 'p', 'h', 9, 0, - /* 5242 */ 's', 'u', 'b', 'q', '_', 's', '.', 'p', 'h', 9, 0, - /* 5253 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'p', 'h', 9, 0, - /* 5264 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'p', 'h', 9, 0, - /* 5275 */ 'a', 'b', 's', 'q', '_', 's', '.', 'p', 'h', 9, 0, - /* 5286 */ 's', 'u', 'b', 'u', '_', 's', '.', 'p', 'h', 9, 0, - /* 5297 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'p', 'h', 9, 0, - /* 5308 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'p', 'h', 9, 0, - /* 5320 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'p', 'h', 9, 0, - /* 5332 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'p', 'h', 9, 0, - /* 5343 */ 's', 'u', 'b', 'u', '.', 'p', 'h', 9, 0, - /* 5352 */ 'a', 'd', 'd', 'u', '.', 'p', 'h', 9, 0, - /* 5361 */ 's', 'h', 'r', 'a', 'v', '.', 'p', 'h', 9, 0, - /* 5371 */ 's', 'h', 'l', 'l', 'v', '.', 'p', 'h', 9, 0, - /* 5381 */ 'r', 'e', 'p', 'l', 'v', '.', 'p', 'h', 9, 0, - /* 5391 */ 's', 'h', 'r', 'l', 'v', '.', 'p', 'h', 9, 0, - /* 5401 */ 'd', 'p', 'a', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5411 */ 'd', 'p', 'a', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5426 */ 'd', 'p', 's', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5441 */ 'm', 'u', 'l', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5453 */ 'd', 'p', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5466 */ 'm', 'u', 'l', 's', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5481 */ 'd', 'p', 's', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5494 */ 'd', 'p', 'a', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5508 */ 'd', 'p', 's', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5522 */ 'd', 'p', 's', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5532 */ 'd', 'p', 'a', 'x', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5543 */ 'd', 'p', 's', 'x', '.', 'w', '.', 'p', 'h', 9, 0, - /* 5554 */ 's', 'h', 9, 0, - /* 5558 */ 'd', 'm', 'u', 'h', 9, 0, - /* 5564 */ 's', 'y', 'n', 'c', 'i', 9, 0, - /* 5571 */ 'd', 'a', 'd', 'd', 'i', 9, 0, - /* 5578 */ 'a', 'n', 'd', 'i', 9, 0, - /* 5584 */ 't', 'g', 'e', 'i', 9, 0, - /* 5590 */ 's', 'n', 'e', 'i', 9, 0, - /* 5596 */ 't', 'n', 'e', 'i', 9, 0, - /* 5602 */ 'd', 'a', 'h', 'i', 9, 0, - /* 5608 */ 'm', 'f', 'h', 'i', 9, 0, - /* 5614 */ 'm', 't', 'h', 'i', 9, 0, - /* 5620 */ '.', 'a', 'l', 'i', 'g', 'n', 32, '2', 10, 9, 'l', 'i', 9, 0, - /* 5634 */ 'd', 'l', 'i', 9, 0, - /* 5639 */ 'c', 'm', 'p', 'i', 9, 0, - /* 5645 */ 's', 'e', 'q', 'i', 9, 0, - /* 5651 */ 't', 'e', 'q', 'i', 9, 0, - /* 5657 */ 'x', 'o', 'r', 'i', 9, 0, - /* 5663 */ 'd', 'a', 't', 'i', 9, 0, - /* 5669 */ 's', 'l', 't', 'i', 9, 0, - /* 5675 */ 't', 'l', 't', 'i', 9, 0, - /* 5681 */ 'd', 'a', 'u', 'i', 9, 0, - /* 5687 */ 'l', 'u', 'i', 9, 0, - /* 5692 */ 'j', 9, 0, - /* 5695 */ 'b', 'r', 'e', 'a', 'k', 9, 0, - /* 5702 */ 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, - /* 5711 */ 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, - /* 5720 */ 'b', 'a', 'l', 9, 0, - /* 5725 */ 'j', 'a', 'l', 9, 0, - /* 5730 */ 'b', 'g', 'e', 'z', 'a', 'l', 9, 0, - /* 5738 */ 'b', 'l', 't', 'z', 'a', 'l', 9, 0, - /* 5746 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0, - /* 5758 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0, - /* 5770 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, - /* 5786 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, - /* 5801 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, - /* 5817 */ 'l', 'd', 'l', 9, 0, - /* 5822 */ 's', 'd', 'l', 9, 0, - /* 5827 */ 'b', 'n', 'e', 'l', 9, 0, - /* 5833 */ 'b', 'c', '0', 'f', 'l', 9, 0, - /* 5840 */ 'b', 'c', '1', 'f', 'l', 9, 0, - /* 5847 */ 'b', 'c', '2', 'f', 'l', 9, 0, - /* 5854 */ 'b', 'c', '3', 'f', 'l', 9, 0, - /* 5861 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'l', 9, 0, - /* 5875 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'l', 9, 0, - /* 5889 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0, - /* 5902 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0, - /* 5917 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 9, 0, - /* 5926 */ 'b', 'g', 'e', 'z', 'a', 'l', 'l', 9, 0, - /* 5935 */ 'b', 'l', 't', 'z', 'a', 'l', 'l', 9, 0, - /* 5944 */ 'd', 's', 'l', 'l', 9, 0, - /* 5950 */ 'b', 'e', 'q', 'l', 9, 0, - /* 5956 */ 'd', 's', 'r', 'l', 9, 0, - /* 5962 */ 'b', 'c', '0', 't', 'l', 9, 0, - /* 5969 */ 'b', 'c', '1', 't', 'l', 9, 0, - /* 5976 */ 'b', 'c', '2', 't', 'l', 9, 0, - /* 5983 */ 'b', 'c', '3', 't', 'l', 9, 0, - /* 5990 */ 'd', 'm', 'u', 'l', 9, 0, - /* 5996 */ 'l', 'w', 'l', 9, 0, - /* 6001 */ 's', 'w', 'l', 9, 0, - /* 6006 */ 'b', 'g', 'e', 'z', 'l', 9, 0, - /* 6013 */ 'b', 'l', 'e', 'z', 'l', 9, 0, - /* 6020 */ 'b', 'g', 't', 'z', 'l', 9, 0, - /* 6027 */ 'b', 'l', 't', 'z', 'l', 9, 0, - /* 6034 */ 'l', 'w', 'm', 9, 0, - /* 6039 */ 's', 'w', 'm', 9, 0, - /* 6044 */ 'b', 'a', 'l', 'i', 'g', 'n', 9, 0, - /* 6052 */ 'd', 'a', 'l', 'i', 'g', 'n', 9, 0, - /* 6060 */ 'm', 'o', 'v', 'n', 9, 0, - /* 6066 */ 'd', 'c', 'l', 'o', 9, 0, - /* 6072 */ 'm', 'f', 'l', 'o', 9, 0, - /* 6078 */ 's', 'h', 'i', 'l', 'o', 9, 0, - /* 6085 */ 'm', 't', 'l', 'o', 9, 0, - /* 6091 */ 'd', 'b', 'i', 't', 's', 'w', 'a', 'p', 9, 0, - /* 6101 */ 's', 'd', 'b', 'b', 'p', 9, 0, - /* 6108 */ 'e', 'x', 't', 'p', 'd', 'p', 9, 0, - /* 6116 */ 'm', 'o', 'v', 'e', 'p', 9, 0, - /* 6123 */ 'm', 't', 'h', 'l', 'i', 'p', 9, 0, - /* 6131 */ 'c', 'm', 'p', 9, 0, - /* 6136 */ 'd', 'p', 'o', 'p', 9, 0, - /* 6142 */ 'a', 'd', 'd', 'i', 'u', 'r', '1', 's', 'p', 9, 0, - /* 6153 */ 'l', 'o', 'a', 'd', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, - /* 6169 */ 's', 't', 'o', 'r', 'e', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, - /* 6186 */ 'r', 'd', 'd', 's', 'p', 9, 0, - /* 6193 */ 'w', 'r', 'd', 's', 'p', 9, 0, - /* 6200 */ 'j', 'r', 'a', 'd', 'd', 'i', 'u', 's', 'p', 9, 0, - /* 6211 */ 'e', 'x', 't', 'p', 9, 0, - /* 6217 */ 'l', 'w', 'p', 9, 0, - /* 6222 */ 's', 'w', 'p', 9, 0, - /* 6227 */ 'b', 'e', 'q', 9, 0, - /* 6232 */ 's', 'e', 'q', 9, 0, - /* 6237 */ 't', 'e', 'q', 9, 0, - /* 6242 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0, - /* 6254 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0, - /* 6266 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, - /* 6282 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, - /* 6297 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, - /* 6313 */ 'l', 'd', 'r', 9, 0, - /* 6318 */ 's', 'd', 'r', 9, 0, - /* 6323 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'r', 9, 0, - /* 6337 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'r', 9, 0, - /* 6351 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0, - /* 6364 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0, - /* 6379 */ 'j', 'r', 9, 0, - /* 6383 */ 'j', 'a', 'l', 'r', 9, 0, - /* 6389 */ 'n', 'o', 'r', 9, 0, - /* 6394 */ 'x', 'o', 'r', 9, 0, - /* 6399 */ 'd', 'r', 'o', 't', 'r', 9, 0, - /* 6406 */ 'r', 'd', 'h', 'w', 'r', 9, 0, - /* 6413 */ 'l', 'w', 'r', 9, 0, - /* 6418 */ 's', 'w', 'r', 9, 0, - /* 6423 */ 'm', 'i', 'n', 'a', '.', 's', 9, 0, - /* 6431 */ 'm', 'a', 'x', 'a', '.', 's', 9, 0, - /* 6439 */ 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, - /* 6448 */ 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, - /* 6457 */ 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, - /* 6466 */ 'c', '.', 'n', 'g', 'e', '.', 's', 9, 0, - /* 6475 */ 'c', '.', 'l', 'e', '.', 's', 9, 0, - /* 6483 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 's', 9, 0, - /* 6493 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 's', 9, 0, - /* 6503 */ 'c', '.', 'o', 'l', 'e', '.', 's', 9, 0, - /* 6512 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 's', 9, 0, - /* 6523 */ 'c', '.', 'u', 'l', 'e', '.', 's', 9, 0, - /* 6532 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 's', 9, 0, - /* 6543 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 's', 9, 0, - /* 6555 */ 'c', '.', 'f', '.', 's', 9, 0, - /* 6562 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 's', 9, 0, - /* 6572 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 's', 9, 0, - /* 6583 */ 'm', 's', 'u', 'b', 'f', '.', 's', 9, 0, - /* 6592 */ 'm', 'a', 'd', 'd', 'f', '.', 's', 9, 0, - /* 6601 */ 'c', '.', 's', 'f', '.', 's', 9, 0, - /* 6609 */ 'm', 'o', 'v', 'f', '.', 's', 9, 0, - /* 6617 */ 'n', 'e', 'g', '.', 's', 9, 0, - /* 6624 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 's', 9, 0, - /* 6635 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 's', 9, 0, - /* 6646 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 's', 9, 0, - /* 6656 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 's', 9, 0, - /* 6667 */ 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, - /* 6676 */ 's', 'e', 'l', '.', 's', 9, 0, - /* 6683 */ 'c', '.', 'n', 'g', 'l', '.', 's', 9, 0, - /* 6692 */ 'm', 'u', 'l', '.', 's', 9, 0, - /* 6699 */ 'm', 'i', 'n', '.', 's', 9, 0, - /* 6706 */ 'c', '.', 'u', 'n', '.', 's', 9, 0, - /* 6714 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 's', 9, 0, - /* 6724 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 's', 9, 0, - /* 6735 */ 'm', 'o', 'v', 'n', '.', 's', 9, 0, - /* 6743 */ 'c', '.', 'e', 'q', '.', 's', 9, 0, - /* 6751 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 's', 9, 0, - /* 6761 */ 'c', '.', 's', 'e', 'q', '.', 's', 9, 0, - /* 6770 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 's', 9, 0, - /* 6781 */ 'c', '.', 'u', 'e', 'q', '.', 's', 9, 0, - /* 6790 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 's', 9, 0, - /* 6801 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 's', 9, 0, - /* 6813 */ 'a', 'b', 's', '.', 's', 9, 0, - /* 6820 */ 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, - /* 6829 */ 'c', '.', 'n', 'g', 't', '.', 's', 9, 0, - /* 6838 */ 'c', '.', 'l', 't', '.', 's', 9, 0, - /* 6846 */ 'c', 'm', 'p', '.', 'l', 't', '.', 's', 9, 0, - /* 6856 */ 'c', '.', 'o', 'l', 't', '.', 's', 9, 0, - /* 6865 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 's', 9, 0, - /* 6876 */ 'c', '.', 'u', 'l', 't', '.', 's', 9, 0, - /* 6885 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 's', 9, 0, - /* 6896 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 's', 9, 0, - /* 6908 */ 'r', 'i', 'n', 't', '.', 's', 9, 0, - /* 6916 */ 's', 'q', 'r', 't', '.', 's', 9, 0, - /* 6924 */ 'm', 'o', 'v', 't', '.', 's', 9, 0, - /* 6932 */ 'd', 'i', 'v', '.', 's', 9, 0, - /* 6939 */ 'm', 'o', 'v', '.', 's', 9, 0, - /* 6946 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 's', 9, 0, - /* 6957 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 's', 9, 0, - /* 6968 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 's', 9, 0, - /* 6978 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 's', 9, 0, - /* 6989 */ 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, - /* 6998 */ 'm', 'a', 'x', '.', 's', 9, 0, - /* 7005 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 's', 9, 0, - /* 7015 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 's', 9, 0, - /* 7025 */ 'm', 'o', 'v', 'z', '.', 's', 9, 0, - /* 7033 */ 'j', 'a', 'l', 's', 9, 0, - /* 7039 */ 'b', 'g', 'e', 'z', 'a', 'l', 's', 9, 0, - /* 7048 */ 'b', 'l', 't', 'z', 'a', 'l', 's', 9, 0, - /* 7057 */ 'j', 'a', 'l', 'r', 's', 9, 0, - /* 7064 */ 'l', 'w', 'x', 's', 9, 0, - /* 7070 */ 'b', 'c', '0', 't', 9, 0, - /* 7076 */ 'b', 'c', '1', 't', 9, 0, - /* 7082 */ 'b', 'c', '2', 't', 9, 0, - /* 7088 */ 'b', 'c', '3', 't', 9, 0, - /* 7094 */ 'w', 'a', 'i', 't', 9, 0, - /* 7100 */ 's', 'l', 't', 9, 0, - /* 7105 */ 't', 'l', 't', 9, 0, - /* 7110 */ 'd', 'm', 'u', 'l', 't', 9, 0, - /* 7117 */ 'n', 'o', 't', 9, 0, - /* 7122 */ 'm', 'o', 'v', 't', 9, 0, - /* 7128 */ 'l', 'b', 'u', 9, 0, - /* 7133 */ 'd', 's', 'u', 'b', 'u', 9, 0, - /* 7140 */ 'm', 's', 'u', 'b', 'u', 9, 0, - /* 7147 */ 'b', 'a', 'd', 'd', 'u', 9, 0, - /* 7154 */ 'd', 'a', 'd', 'd', 'u', 9, 0, - /* 7161 */ 'm', 'a', 'd', 'd', 'u', 9, 0, - /* 7168 */ 'd', 'm', 'o', 'd', 'u', 9, 0, - /* 7175 */ 't', 'g', 'e', 'u', 9, 0, - /* 7181 */ 'l', 'h', 'u', 9, 0, - /* 7186 */ 'd', 'm', 'u', 'h', 'u', 9, 0, - /* 7193 */ 'd', 'a', 'd', 'd', 'i', 'u', 9, 0, - /* 7201 */ 't', 'g', 'e', 'i', 'u', 9, 0, - /* 7208 */ 's', 'l', 't', 'i', 'u', 9, 0, - /* 7215 */ 't', 'l', 't', 'i', 'u', 9, 0, - /* 7222 */ 'v', '3', 'm', 'u', 'l', 'u', 9, 0, - /* 7230 */ 'd', 'm', 'u', 'l', 'u', 9, 0, - /* 7237 */ 'v', 'm', 'u', 'l', 'u', 9, 0, - /* 7244 */ 's', 'l', 't', 'u', 9, 0, - /* 7250 */ 't', 'l', 't', 'u', 9, 0, - /* 7256 */ 'd', 'm', 'u', 'l', 't', 'u', 9, 0, - /* 7264 */ 'd', 'd', 'i', 'v', 'u', 9, 0, - /* 7271 */ 'l', 'w', 'u', 9, 0, - /* 7276 */ 'a', 'n', 'd', '.', 'v', 9, 0, - /* 7283 */ 'm', 'o', 'v', 'e', '.', 'v', 9, 0, - /* 7291 */ 'b', 's', 'e', 'l', '.', 'v', 9, 0, - /* 7299 */ 'n', 'o', 'r', '.', 'v', 9, 0, - /* 7306 */ 'x', 'o', 'r', '.', 'v', 9, 0, - /* 7313 */ 'b', 'z', '.', 'v', 9, 0, - /* 7319 */ 'b', 'm', 'z', '.', 'v', 9, 0, - /* 7326 */ 'b', 'n', 'z', '.', 'v', 9, 0, - /* 7333 */ 'b', 'm', 'n', 'z', '.', 'v', 9, 0, - /* 7341 */ 'd', 's', 'r', 'a', 'v', 9, 0, - /* 7348 */ 'b', 'i', 't', 'r', 'e', 'v', 9, 0, - /* 7356 */ 'd', 'd', 'i', 'v', 9, 0, - /* 7362 */ 'd', 's', 'l', 'l', 'v', 9, 0, - /* 7369 */ 'd', 's', 'r', 'l', 'v', 9, 0, - /* 7376 */ 's', 'h', 'i', 'l', 'o', 'v', 9, 0, - /* 7384 */ 'e', 'x', 't', 'p', 'd', 'p', 'v', 9, 0, - /* 7393 */ 'e', 'x', 't', 'p', 'v', 9, 0, - /* 7400 */ 'd', 'r', 'o', 't', 'r', 'v', 9, 0, - /* 7408 */ 'i', 'n', 's', 'v', 9, 0, - /* 7414 */ 'f', 'l', 'o', 'g', '2', '.', 'w', 9, 0, - /* 7423 */ 'f', 'e', 'x', 'p', '2', '.', 'w', 9, 0, - /* 7432 */ 'a', 'd', 'd', '_', 'a', '.', 'w', 9, 0, - /* 7441 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'w', 9, 0, - /* 7451 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'w', 9, 0, - /* 7461 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'w', 9, 0, - /* 7471 */ 's', 'r', 'a', '.', 'w', 9, 0, - /* 7478 */ 'f', 's', 'u', 'b', '.', 'w', 9, 0, - /* 7486 */ 'f', 'm', 's', 'u', 'b', '.', 'w', 9, 0, - /* 7495 */ 'n', 'l', 'o', 'c', '.', 'w', 9, 0, - /* 7503 */ 'n', 'l', 'z', 'c', '.', 'w', 9, 0, - /* 7511 */ 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, - /* 7520 */ 'f', 'a', 'd', 'd', '.', 'w', 9, 0, - /* 7528 */ 'f', 'm', 'a', 'd', 'd', '.', 'w', 9, 0, - /* 7537 */ 's', 'l', 'd', '.', 'w', 9, 0, - /* 7544 */ 'p', 'c', 'k', 'o', 'd', '.', 'w', 9, 0, - /* 7553 */ 'i', 'l', 'v', 'o', 'd', '.', 'w', 9, 0, - /* 7562 */ 'f', 'c', 'l', 'e', '.', 'w', 9, 0, - /* 7570 */ 'f', 's', 'l', 'e', '.', 'w', 9, 0, - /* 7578 */ 'f', 'c', 'u', 'l', 'e', '.', 'w', 9, 0, - /* 7587 */ 'f', 's', 'u', 'l', 'e', '.', 'w', 9, 0, - /* 7596 */ 'f', 'c', 'n', 'e', '.', 'w', 9, 0, - /* 7604 */ 'f', 's', 'n', 'e', '.', 'w', 9, 0, - /* 7612 */ 'f', 'c', 'u', 'n', 'e', '.', 'w', 9, 0, - /* 7621 */ 'f', 's', 'u', 'n', 'e', '.', 'w', 9, 0, - /* 7630 */ 'i', 'n', 's', 'v', 'e', '.', 'w', 9, 0, - /* 7639 */ 'f', 'c', 'a', 'f', '.', 'w', 9, 0, - /* 7647 */ 'f', 's', 'a', 'f', '.', 'w', 9, 0, - /* 7655 */ 'v', 's', 'h', 'f', '.', 'w', 9, 0, - /* 7663 */ 'b', 'n', 'e', 'g', '.', 'w', 9, 0, - /* 7671 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '.', 'p', 'h', '.', 'w', 9, 0, - /* 7687 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'p', 'h', '.', 'w', 9, 0, - /* 7700 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '_', 'r', '.', 'p', 'h', '.', 'w', 9, 0, - /* 7718 */ 'p', 'r', 'e', 'c', 'r', 'q', '_', 'r', 's', '.', 'p', 'h', '.', 'w', 9, 0, - /* 7734 */ 's', 'u', 'b', 'q', 'h', '.', 'w', 9, 0, - /* 7743 */ 'a', 'd', 'd', 'q', 'h', '.', 'w', 9, 0, - /* 7752 */ 's', 'r', 'a', 'i', '.', 'w', 9, 0, - /* 7760 */ 's', 'l', 'd', 'i', '.', 'w', 9, 0, - /* 7768 */ 'b', 'n', 'e', 'g', 'i', '.', 'w', 9, 0, - /* 7777 */ 's', 'l', 'l', 'i', '.', 'w', 9, 0, - /* 7785 */ 's', 'r', 'l', 'i', '.', 'w', 9, 0, - /* 7793 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'w', 9, 0, - /* 7803 */ 'c', 'e', 'q', 'i', '.', 'w', 9, 0, - /* 7811 */ 's', 'r', 'a', 'r', 'i', '.', 'w', 9, 0, - /* 7820 */ 'b', 'c', 'l', 'r', 'i', '.', 'w', 9, 0, - /* 7829 */ 's', 'r', 'l', 'r', 'i', '.', 'w', 9, 0, - /* 7838 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'w', 9, 0, - /* 7848 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'w', 9, 0, - /* 7858 */ 'b', 's', 'e', 't', 'i', '.', 'w', 9, 0, - /* 7867 */ 's', 'u', 'b', 'v', 'i', '.', 'w', 9, 0, - /* 7876 */ 'a', 'd', 'd', 'v', 'i', '.', 'w', 9, 0, - /* 7885 */ 'd', 'p', 'a', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, - /* 7898 */ 'd', 'p', 's', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, - /* 7911 */ 'f', 'i', 'l', 'l', '.', 'w', 9, 0, - /* 7919 */ 's', 'l', 'l', '.', 'w', 9, 0, - /* 7926 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'w', 9, 0, - /* 7936 */ 'f', 'f', 'q', 'l', '.', 'w', 9, 0, - /* 7944 */ 's', 'r', 'l', '.', 'w', 9, 0, - /* 7951 */ 'b', 'i', 'n', 's', 'l', '.', 'w', 9, 0, - /* 7960 */ 'f', 'm', 'u', 'l', '.', 'w', 9, 0, - /* 7968 */ 'i', 'l', 'v', 'l', '.', 'w', 9, 0, - /* 7976 */ 'f', 'm', 'i', 'n', '.', 'w', 9, 0, - /* 7984 */ 'f', 'c', 'u', 'n', '.', 'w', 9, 0, - /* 7992 */ 'f', 's', 'u', 'n', '.', 'w', 9, 0, - /* 8000 */ 'f', 'e', 'x', 'd', 'o', '.', 'w', 9, 0, - /* 8009 */ 'f', 'r', 'c', 'p', '.', 'w', 9, 0, - /* 8017 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'w', 9, 0, - /* 8027 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'w', 9, 0, - /* 8037 */ 'm', 'u', 'l', '_', 'q', '.', 'w', 9, 0, - /* 8046 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'w', 9, 0, - /* 8057 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'w', 9, 0, - /* 8068 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'w', 9, 0, - /* 8078 */ 'f', 'c', 'e', 'q', '.', 'w', 9, 0, - /* 8086 */ 'f', 's', 'e', 'q', '.', 'w', 9, 0, - /* 8094 */ 'f', 'c', 'u', 'e', 'q', '.', 'w', 9, 0, - /* 8103 */ 'f', 's', 'u', 'e', 'q', '.', 'w', 9, 0, - /* 8112 */ 'f', 't', 'q', '.', 'w', 9, 0, - /* 8119 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'w', 9, 0, - /* 8129 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'w', 9, 0, - /* 8140 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'w', 9, 0, - /* 8151 */ 'e', 'x', 't', 'r', '_', 'r', '.', 'w', 9, 0, - /* 8161 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'w', 9, 0, - /* 8172 */ 'e', 'x', 't', 'r', 'v', '_', 'r', '.', 'w', 9, 0, - /* 8183 */ 's', 'r', 'a', 'r', '.', 'w', 9, 0, - /* 8191 */ 'b', 'c', 'l', 'r', '.', 'w', 9, 0, - /* 8199 */ 's', 'r', 'l', 'r', '.', 'w', 9, 0, - /* 8207 */ 'f', 'c', 'o', 'r', '.', 'w', 9, 0, - /* 8215 */ 'f', 's', 'o', 'r', '.', 'w', 9, 0, - /* 8223 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'w', 9, 0, - /* 8233 */ 'f', 'f', 'q', 'r', '.', 'w', 9, 0, - /* 8241 */ 'b', 'i', 'n', 's', 'r', '.', 'w', 9, 0, - /* 8250 */ 'e', 'x', 't', 'r', '.', 'w', 9, 0, - /* 8258 */ 'i', 'l', 'v', 'r', '.', 'w', 9, 0, - /* 8266 */ 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, - /* 8275 */ 'a', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, - /* 8285 */ 'h', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, - /* 8295 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, - /* 8306 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'w', 9, 0, - /* 8318 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, - /* 8328 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, - /* 8339 */ 'm', 'o', 'd', '_', 's', '.', 'w', 9, 0, - /* 8348 */ 'c', 'l', 'e', '_', 's', '.', 'w', 9, 0, - /* 8357 */ 'a', 'v', 'e', '_', 's', '.', 'w', 9, 0, - /* 8366 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'w', 9, 0, - /* 8376 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'w', 9, 0, - /* 8386 */ 'c', 'l', 't', 'i', '_', 's', '.', 'w', 9, 0, - /* 8396 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'w', 9, 0, - /* 8406 */ 's', 'h', 'l', 'l', '_', 's', '.', 'w', 9, 0, - /* 8416 */ 'm', 'i', 'n', '_', 's', '.', 'w', 9, 0, - /* 8425 */ 'd', 'o', 't', 'p', '_', 's', '.', 'w', 9, 0, - /* 8435 */ 's', 'u', 'b', 'q', '_', 's', '.', 'w', 9, 0, - /* 8445 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'w', 9, 0, - /* 8455 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'w', 9, 0, - /* 8465 */ 'a', 'b', 's', 'q', '_', 's', '.', 'w', 9, 0, - /* 8475 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'w', 9, 0, - /* 8485 */ 's', 'u', 'b', 's', '_', 's', '.', 'w', 9, 0, - /* 8495 */ 'a', 'd', 'd', 's', '_', 's', '.', 'w', 9, 0, - /* 8505 */ 's', 'a', 't', '_', 's', '.', 'w', 9, 0, - /* 8514 */ 'c', 'l', 't', '_', 's', '.', 'w', 9, 0, - /* 8523 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, - /* 8534 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, - /* 8545 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0, - /* 8557 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0, - /* 8566 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0, - /* 8577 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0, - /* 8586 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0, - /* 8596 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0, - /* 8607 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0, - /* 8618 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0, - /* 8630 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0, - /* 8640 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0, - /* 8649 */ 'b', 's', 'e', 't', '.', 'w', 9, 0, - /* 8657 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0, - /* 8665 */ 'f', 's', 'l', 't', '.', 'w', 9, 0, - /* 8673 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0, - /* 8682 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0, - /* 8691 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0, - /* 8699 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0, - /* 8708 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0, - /* 8718 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0, - /* 8727 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0, - /* 8737 */ 's', 't', '.', 'w', 9, 0, - /* 8743 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8753 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8763 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, - /* 8774 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0, - /* 8786 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8796 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8807 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0, - /* 8816 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0, - /* 8825 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0, - /* 8834 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8844 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8854 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8864 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0, - /* 8874 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0, - /* 8883 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0, - /* 8893 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0, - /* 8903 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0, - /* 8913 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0, - /* 8923 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0, - /* 8935 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0, - /* 8944 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0, - /* 8953 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, - /* 8964 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, - /* 8975 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0, - /* 8984 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0, - /* 8993 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0, - /* 9003 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0, - /* 9012 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0, - /* 9021 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0, - /* 9030 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0, - /* 9039 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0, - /* 9047 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0, - /* 9055 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0, - /* 9064 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0, - /* 9072 */ 'b', 'z', '.', 'w', 9, 0, - /* 9078 */ 'b', 'n', 'z', '.', 'w', 9, 0, - /* 9085 */ 'l', 'w', 9, 0, - /* 9089 */ 's', 'w', 9, 0, - /* 9093 */ 'l', 'h', 'x', 9, 0, - /* 9098 */ 'j', 'a', 'l', 'x', 9, 0, - /* 9104 */ 'l', 'b', 'u', 'x', 9, 0, - /* 9110 */ 'l', 'w', 'x', 9, 0, - /* 9115 */ 'b', 'g', 'e', 'z', 9, 0, - /* 9121 */ 'b', 'l', 'e', 'z', 9, 0, - /* 9127 */ 'b', 'n', 'e', 'z', 9, 0, - /* 9133 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0, - /* 9141 */ 'b', 't', 'n', 'e', 'z', 9, 0, - /* 9148 */ 'd', 'c', 'l', 'z', 9, 0, - /* 9154 */ 'b', 'e', 'q', 'z', 9, 0, - /* 9160 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0, - /* 9168 */ 'b', 't', 'e', 'q', 'z', 9, 0, - /* 9175 */ 'b', 'g', 't', 'z', 9, 0, - /* 9181 */ 'b', 'l', 't', 'z', 9, 0, - /* 9187 */ 'm', 'o', 'v', 'z', 9, 0, - /* 9193 */ 's', 'e', 'b', 9, 32, 0, - /* 9199 */ 'j', 'r', 'c', 9, 32, 0, - /* 9205 */ 's', 'e', 'h', 9, 32, 0, - /* 9211 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, - /* 9225 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, - /* 9238 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0, - /* 9250 */ 'c', 'i', 'n', 's', '3', '2', 32, 0, - /* 9258 */ 'e', 'x', 't', 's', '3', '2', 32, 0, - /* 9266 */ 's', 'y', 'n', 'c', 32, 0, - /* 9272 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0, - /* 9280 */ 'd', 'i', 'n', 's', 'm', 32, 0, - /* 9287 */ 'd', 'e', 'x', 't', 'm', 32, 0, - /* 9294 */ 'c', 'i', 'n', 's', 32, 0, - /* 9300 */ 'd', 'i', 'n', 's', 32, 0, - /* 9306 */ 'e', 'x', 't', 's', 32, 0, - /* 9312 */ 'd', 'e', 'x', 't', 32, 0, - /* 9318 */ 'd', 'i', 'n', 's', 'u', 32, 0, - /* 9325 */ 'd', 'e', 'x', 't', 'u', 32, 0, - /* 9332 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0, - /* 9340 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0, - /* 9348 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0, - /* 9356 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0, - /* 9364 */ 'c', '.', 0, - /* 9367 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0, - /* 9375 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 9388 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 9395 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 9405 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 9420 */ 'j', 'r', 'c', 9, 32, '$', 'r', 'a', 0, - /* 9429 */ 'j', 'r', 9, 32, '$', 'r', 'a', 0, - /* 9437 */ 'e', 'h', 'b', 0, - /* 9441 */ 'p', 'a', 'u', 's', 'e', 0, - /* 9447 */ 't', 'l', 'b', 'w', 'i', 0, - /* 9453 */ 'f', 'o', 'o', 0, - /* 9457 */ 't', 'l', 'b', 'p', 0, - /* 9462 */ 's', 's', 'n', 'o', 'p', 0, - /* 9468 */ 't', 'l', 'b', 'r', 0, - /* 9473 */ 't', 'l', 'b', 'w', 'r', 0, - /* 9479 */ 'd', 'e', 'r', 'e', 't', 0, - /* 9485 */ 'w', 'a', 'i', 't', 0, + /* 0 */ 'j', + 'a', + 'l', + 'r', + 'c', + 32, + 9, + 0, + /* 8 */ 'd', + 'm', + 'f', + 'c', + '0', + 9, + 0, + /* 15 */ 'd', + 'm', + 't', + 'c', + '0', + 9, + 0, + /* 22 */ 'v', + 'm', + 'm', + '0', + 9, + 0, + /* 28 */ 'm', + 't', + 'm', + '0', + 9, + 0, + /* 34 */ 'm', + 't', + 'p', + '0', + 9, + 0, + /* 40 */ 'b', + 'b', + 'i', + 't', + '0', + 9, + 0, + /* 47 */ 'l', + 'd', + 'c', + '1', + 9, + 0, + /* 53 */ 's', + 'd', + 'c', + '1', + 9, + 0, + /* 59 */ 'c', + 'f', + 'c', + '1', + 9, + 0, + /* 65 */ 'd', + 'm', + 'f', + 'c', + '1', + 9, + 0, + /* 72 */ 'm', + 'f', + 'h', + 'c', + '1', + 9, + 0, + /* 79 */ 'm', + 't', + 'h', + 'c', + '1', + 9, + 0, + /* 86 */ 'c', + 't', + 'c', + '1', + 9, + 0, + /* 92 */ 'd', + 'm', + 't', + 'c', + '1', + 9, + 0, + /* 99 */ 'l', + 'w', + 'c', + '1', + 9, + 0, + /* 105 */ 's', + 'w', + 'c', + '1', + 9, + 0, + /* 111 */ 'l', + 'd', + 'x', + 'c', + '1', + 9, + 0, + /* 118 */ 's', + 'd', + 'x', + 'c', + '1', + 9, + 0, + /* 125 */ 'l', + 'u', + 'x', + 'c', + '1', + 9, + 0, + /* 132 */ 's', + 'u', + 'x', + 'c', + '1', + 9, + 0, + /* 139 */ 'l', + 'w', + 'x', + 'c', + '1', + 9, + 0, + /* 146 */ 's', + 'w', + 'x', + 'c', + '1', + 9, + 0, + /* 153 */ 'm', + 't', + 'm', + '1', + 9, + 0, + /* 159 */ 'm', + 't', + 'p', + '1', + 9, + 0, + /* 165 */ 'b', + 'b', + 'i', + 't', + '1', + 9, + 0, + /* 172 */ 'b', + 'b', + 'i', + 't', + '0', + '3', + '2', + 9, + 0, + /* 181 */ 'b', + 'b', + 'i', + 't', + '1', + '3', + '2', + 9, + 0, + /* 190 */ 'd', + 's', + 'r', + 'a', + '3', + '2', + 9, + 0, + /* 198 */ 'b', + 'p', + 'o', + 's', + 'g', + 'e', + '3', + '2', + 9, + 0, + /* 208 */ 'd', + 's', + 'l', + 'l', + '3', + '2', + 9, + 0, + /* 216 */ 'd', + 's', + 'r', + 'l', + '3', + '2', + 9, + 0, + /* 224 */ 'l', + 'w', + 'm', + '3', + '2', + 9, + 0, + /* 231 */ 's', + 'w', + 'm', + '3', + '2', + 9, + 0, + /* 238 */ 'd', + 'r', + 'o', + 't', + 'r', + '3', + '2', + 9, + 0, + /* 247 */ 'l', + 'd', + 'c', + '2', + 9, + 0, + /* 253 */ 's', + 'd', + 'c', + '2', + 9, + 0, + /* 259 */ 'd', + 'm', + 'f', + 'c', + '2', + 9, + 0, + /* 266 */ 'd', + 'm', + 't', + 'c', + '2', + 9, + 0, + /* 273 */ 'l', + 'w', + 'c', + '2', + 9, + 0, + /* 279 */ 's', + 'w', + 'c', + '2', + 9, + 0, + /* 285 */ 'm', + 't', + 'm', + '2', + 9, + 0, + /* 291 */ 'm', + 't', + 'p', + '2', + 9, + 0, + /* 297 */ 'a', + 'd', + 'd', + 'i', + 'u', + 'r', + '2', + 9, + 0, + /* 306 */ 'l', + 'd', + 'c', + '3', + 9, + 0, + /* 312 */ 's', + 'd', + 'c', + '3', + 9, + 0, + /* 318 */ 'l', + 'w', + 'c', + '3', + 9, + 0, + /* 324 */ 's', + 'w', + 'c', + '3', + 9, + 0, + /* 330 */ 'a', + 'd', + 'd', + 'i', + 'u', + 's', + '5', + 9, + 0, + /* 339 */ 's', + 'b', + '1', + '6', + 9, + 0, + /* 345 */ 'a', + 'n', + 'd', + '1', + '6', + 9, + 0, + /* 352 */ 's', + 'h', + '1', + '6', + 9, + 0, + /* 358 */ 'a', + 'n', + 'd', + 'i', + '1', + '6', + 9, + 0, + /* 366 */ 'l', + 'i', + '1', + '6', + 9, + 0, + /* 372 */ 'b', + 'r', + 'e', + 'a', + 'k', + '1', + '6', + 9, + 0, + /* 381 */ 's', + 'l', + 'l', + '1', + '6', + 9, + 0, + /* 388 */ 's', + 'r', + 'l', + '1', + '6', + 9, + 0, + /* 395 */ 'l', + 'w', + 'm', + '1', + '6', + 9, + 0, + /* 402 */ 's', + 'w', + 'm', + '1', + '6', + 9, + 0, + /* 409 */ 's', + 'd', + 'b', + 'b', + 'p', + '1', + '6', + 9, + 0, + /* 418 */ 'j', + 'r', + '1', + '6', + 9, + 0, + /* 424 */ 'x', + 'o', + 'r', + '1', + '6', + 9, + 0, + /* 431 */ 'j', + 'a', + 'l', + 'r', + 's', + '1', + '6', + 9, + 0, + /* 440 */ 'n', + 'o', + 't', + '1', + '6', + 9, + 0, + /* 447 */ 'l', + 'b', + 'u', + '1', + '6', + 9, + 0, + /* 454 */ 's', + 'u', + 'b', + 'u', + '1', + '6', + 9, + 0, + /* 462 */ 'a', + 'd', + 'd', + 'u', + '1', + '6', + 9, + 0, + /* 470 */ 'l', + 'h', + 'u', + '1', + '6', + 9, + 0, + /* 477 */ 'l', + 'w', + '1', + '6', + 9, + 0, + /* 483 */ 's', + 'w', + '1', + '6', + 9, + 0, + /* 489 */ 'b', + 'n', + 'e', + 'z', + '1', + '6', + 9, + 0, + /* 497 */ 'b', + 'e', + 'q', + 'z', + '1', + '6', + 9, + 0, + /* 505 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'u', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'l', + 'a', + 9, + 0, + /* 521 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'q', + 'u', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'l', + 'a', + 9, + 0, + /* 538 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'u', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'r', + 'a', + 9, + 0, + /* 554 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'q', + 'u', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'r', + 'a', + 9, + 0, + /* 571 */ 'd', + 's', + 'r', + 'a', + 9, + 0, + /* 577 */ 'd', + 'l', + 's', + 'a', + 9, + 0, + /* 583 */ 'c', + 'f', + 'c', + 'm', + 's', + 'a', + 9, + 0, + /* 591 */ 'c', + 't', + 'c', + 'm', + 's', + 'a', + 9, + 0, + /* 599 */ 'a', + 'd', + 'd', + '_', + 'a', + '.', + 'b', + 9, + 0, + /* 608 */ 'm', + 'i', + 'n', + '_', + 'a', + '.', + 'b', + 9, + 0, + /* 617 */ 'a', + 'd', + 'd', + 's', + '_', + 'a', + '.', + 'b', + 9, + 0, + /* 627 */ 'm', + 'a', + 'x', + '_', + 'a', + '.', + 'b', + 9, + 0, + /* 636 */ 's', + 'r', + 'a', + '.', + 'b', + 9, + 0, + /* 643 */ 'n', + 'l', + 'o', + 'c', + '.', + 'b', + 9, + 0, + /* 651 */ 'n', + 'l', + 'z', + 'c', + '.', + 'b', + 9, + 0, + /* 659 */ 's', + 'l', + 'd', + '.', + 'b', + 9, + 0, + /* 666 */ 'p', + 'c', + 'k', + 'o', + 'd', + '.', + 'b', + 9, + 0, + /* 675 */ 'i', + 'l', + 'v', + 'o', + 'd', + '.', + 'b', + 9, + 0, + /* 684 */ 'i', + 'n', + 's', + 'v', + 'e', + '.', + 'b', + 9, + 0, + /* 693 */ 'v', + 's', + 'h', + 'f', + '.', + 'b', + 9, + 0, + /* 701 */ 'b', + 'n', + 'e', + 'g', + '.', + 'b', + 9, + 0, + /* 709 */ 's', + 'r', + 'a', + 'i', + '.', + 'b', + 9, + 0, + /* 717 */ 's', + 'l', + 'd', + 'i', + '.', + 'b', + 9, + 0, + /* 725 */ 'a', + 'n', + 'd', + 'i', + '.', + 'b', + 9, + 0, + /* 733 */ 'b', + 'n', + 'e', + 'g', + 'i', + '.', + 'b', + 9, + 0, + /* 742 */ 'b', + 's', + 'e', + 'l', + 'i', + '.', + 'b', + 9, + 0, + /* 751 */ 's', + 'l', + 'l', + 'i', + '.', + 'b', + 9, + 0, + /* 759 */ 's', + 'r', + 'l', + 'i', + '.', + 'b', + 9, + 0, + /* 767 */ 'b', + 'i', + 'n', + 's', + 'l', + 'i', + '.', + 'b', + 9, + 0, + /* 777 */ 'c', + 'e', + 'q', + 'i', + '.', + 'b', + 9, + 0, + /* 785 */ 's', + 'r', + 'a', + 'r', + 'i', + '.', + 'b', + 9, + 0, + /* 794 */ 'b', + 'c', + 'l', + 'r', + 'i', + '.', + 'b', + 9, + 0, + /* 803 */ 's', + 'r', + 'l', + 'r', + 'i', + '.', + 'b', + 9, + 0, + /* 812 */ 'n', + 'o', + 'r', + 'i', + '.', + 'b', + 9, + 0, + /* 820 */ 'x', + 'o', + 'r', + 'i', + '.', + 'b', + 9, + 0, + /* 828 */ 'b', + 'i', + 'n', + 's', + 'r', + 'i', + '.', + 'b', + 9, + 0, + /* 838 */ 's', + 'p', + 'l', + 'a', + 't', + 'i', + '.', + 'b', + 9, + 0, + /* 848 */ 'b', + 's', + 'e', + 't', + 'i', + '.', + 'b', + 9, + 0, + /* 857 */ 's', + 'u', + 'b', + 'v', + 'i', + '.', + 'b', + 9, + 0, + /* 866 */ 'a', + 'd', + 'd', + 'v', + 'i', + '.', + 'b', + 9, + 0, + /* 875 */ 'b', + 'm', + 'z', + 'i', + '.', + 'b', + 9, + 0, + /* 883 */ 'b', + 'm', + 'n', + 'z', + 'i', + '.', + 'b', + 9, + 0, + /* 892 */ 'f', + 'i', + 'l', + 'l', + '.', + 'b', + 9, + 0, + /* 900 */ 's', + 'l', + 'l', + '.', + 'b', + 9, + 0, + /* 907 */ 's', + 'r', + 'l', + '.', + 'b', + 9, + 0, + /* 914 */ 'b', + 'i', + 'n', + 's', + 'l', + '.', + 'b', + 9, + 0, + /* 923 */ 'i', + 'l', + 'v', + 'l', + '.', + 'b', + 9, + 0, + /* 931 */ 'c', + 'e', + 'q', + '.', + 'b', + 9, + 0, + /* 938 */ 's', + 'r', + 'a', + 'r', + '.', + 'b', + 9, + 0, + /* 946 */ 'b', + 'c', + 'l', + 'r', + '.', + 'b', + 9, + 0, + /* 954 */ 's', + 'r', + 'l', + 'r', + '.', + 'b', + 9, + 0, + /* 962 */ 'b', + 'i', + 'n', + 's', + 'r', + '.', + 'b', + 9, + 0, + /* 971 */ 'i', + 'l', + 'v', + 'r', + '.', + 'b', + 9, + 0, + /* 979 */ 'a', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 989 */ 'm', + 'o', + 'd', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 998 */ 'c', + 'l', + 'e', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1007 */ 'a', + 'v', + 'e', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1016 */ 'c', + 'l', + 'e', + 'i', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1026 */ 'm', + 'i', + 'n', + 'i', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1036 */ 'c', + 'l', + 't', + 'i', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1046 */ 'm', + 'a', + 'x', + 'i', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1056 */ 'm', + 'i', + 'n', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1065 */ 'a', + 'v', + 'e', + 'r', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1075 */ 's', + 'u', + 'b', + 's', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1085 */ 'a', + 'd', + 'd', + 's', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1095 */ 's', + 'a', + 't', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1104 */ 'c', + 'l', + 't', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1113 */ 's', + 'u', + 'b', + 's', + 'u', + 'u', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1125 */ 'd', + 'i', + 'v', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1134 */ 'm', + 'a', + 'x', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1143 */ 'c', + 'o', + 'p', + 'y', + '_', + 's', + '.', + 'b', + 9, + 0, + /* 1153 */ 's', + 'p', + 'l', + 'a', + 't', + '.', + 'b', + 9, + 0, + /* 1162 */ 'b', + 's', + 'e', + 't', + '.', + 'b', + 9, + 0, + /* 1170 */ 'p', + 'c', + 'n', + 't', + '.', + 'b', + 9, + 0, + /* 1178 */ 'i', + 'n', + 's', + 'e', + 'r', + 't', + '.', + 'b', + 9, + 0, + /* 1188 */ 's', + 't', + '.', + 'b', + 9, + 0, + /* 1194 */ 'a', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1204 */ 'm', + 'o', + 'd', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1213 */ 'c', + 'l', + 'e', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1222 */ 'a', + 'v', + 'e', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1231 */ 'c', + 'l', + 'e', + 'i', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1241 */ 'm', + 'i', + 'n', + 'i', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1251 */ 'c', + 'l', + 't', + 'i', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1261 */ 'm', + 'a', + 'x', + 'i', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1271 */ 'm', + 'i', + 'n', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1280 */ 'a', + 'v', + 'e', + 'r', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1290 */ 's', + 'u', + 'b', + 's', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1300 */ 'a', + 'd', + 'd', + 's', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1310 */ 's', + 'u', + 'b', + 's', + 'u', + 's', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1322 */ 's', + 'a', + 't', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1331 */ 'c', + 'l', + 't', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1340 */ 'd', + 'i', + 'v', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1349 */ 'm', + 'a', + 'x', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1358 */ 'c', + 'o', + 'p', + 'y', + '_', + 'u', + '.', + 'b', + 9, + 0, + /* 1368 */ 'm', + 's', + 'u', + 'b', + 'v', + '.', + 'b', + 9, + 0, + /* 1377 */ 'm', + 'a', + 'd', + 'd', + 'v', + '.', + 'b', + 9, + 0, + /* 1386 */ 'p', + 'c', + 'k', + 'e', + 'v', + '.', + 'b', + 9, + 0, + /* 1395 */ 'i', + 'l', + 'v', + 'e', + 'v', + '.', + 'b', + 9, + 0, + /* 1404 */ 'm', + 'u', + 'l', + 'v', + '.', + 'b', + 9, + 0, + /* 1412 */ 'b', + 'z', + '.', + 'b', + 9, + 0, + /* 1418 */ 'b', + 'n', + 'z', + '.', + 'b', + 9, + 0, + /* 1425 */ 's', + 'e', + 'b', + 9, + 0, + /* 1430 */ 'j', + 'r', + '.', + 'h', + 'b', + 9, + 0, + /* 1437 */ 'j', + 'a', + 'l', + 'r', + '.', + 'h', + 'b', + 9, + 0, + /* 1446 */ 'l', + 'b', + 9, + 0, + /* 1450 */ 's', + 'h', + 'r', + 'a', + '.', + 'q', + 'b', + 9, + 0, + /* 1459 */ 'c', + 'm', + 'p', + 'g', + 'd', + 'u', + '.', + 'l', + 'e', + '.', + 'q', + 'b', + 9, + 0, + /* 1473 */ 'c', + 'm', + 'p', + 'g', + 'u', + '.', + 'l', + 'e', + '.', + 'q', + 'b', + 9, + 0, + /* 1486 */ 'c', + 'm', + 'p', + 'u', + '.', + 'l', + 'e', + '.', + 'q', + 'b', + 9, + 0, + /* 1498 */ 's', + 'u', + 'b', + 'u', + 'h', + '.', + 'q', + 'b', + 9, + 0, + /* 1508 */ 'a', + 'd', + 'd', + 'u', + 'h', + '.', + 'q', + 'b', + 9, + 0, + /* 1518 */ 'p', + 'i', + 'c', + 'k', + '.', + 'q', + 'b', + 9, + 0, + /* 1527 */ 's', + 'h', + 'l', + 'l', + '.', + 'q', + 'b', + 9, + 0, + /* 1536 */ 'r', + 'e', + 'p', + 'l', + '.', + 'q', + 'b', + 9, + 0, + /* 1545 */ 's', + 'h', + 'r', + 'l', + '.', + 'q', + 'b', + 9, + 0, + /* 1554 */ 'c', + 'm', + 'p', + 'g', + 'd', + 'u', + '.', + 'e', + 'q', + '.', + 'q', + 'b', + 9, + 0, + /* 1568 */ 'c', + 'm', + 'p', + 'g', + 'u', + '.', + 'e', + 'q', + '.', + 'q', + 'b', + 9, + 0, + /* 1581 */ 'c', + 'm', + 'p', + 'u', + '.', + 'e', + 'q', + '.', + 'q', + 'b', + 9, + 0, + /* 1593 */ 's', + 'h', + 'r', + 'a', + '_', + 'r', + '.', + 'q', + 'b', + 9, + 0, + /* 1604 */ 's', + 'u', + 'b', + 'u', + 'h', + '_', + 'r', + '.', + 'q', + 'b', + 9, + 0, + /* 1616 */ 'a', + 'd', + 'd', + 'u', + 'h', + '_', + 'r', + '.', + 'q', + 'b', + 9, + 0, + /* 1628 */ 's', + 'h', + 'r', + 'a', + 'v', + '_', + 'r', + '.', + 'q', + 'b', + 9, + 0, + /* 1640 */ 'a', + 'b', + 's', + 'q', + '_', + 's', + '.', + 'q', + 'b', + 9, + 0, + /* 1651 */ 's', + 'u', + 'b', + 'u', + '_', + 's', + '.', + 'q', + 'b', + 9, + 0, + /* 1662 */ 'a', + 'd', + 'd', + 'u', + '_', + 's', + '.', + 'q', + 'b', + 9, + 0, + /* 1673 */ 'c', + 'm', + 'p', + 'g', + 'd', + 'u', + '.', + 'l', + 't', + '.', + 'q', + 'b', + 9, + 0, + /* 1687 */ 'c', + 'm', + 'p', + 'g', + 'u', + '.', + 'l', + 't', + '.', + 'q', + 'b', + 9, + 0, + /* 1700 */ 'c', + 'm', + 'p', + 'u', + '.', + 'l', + 't', + '.', + 'q', + 'b', + 9, + 0, + /* 1712 */ 's', + 'u', + 'b', + 'u', + '.', + 'q', + 'b', + 9, + 0, + /* 1721 */ 'a', + 'd', + 'd', + 'u', + '.', + 'q', + 'b', + 9, + 0, + /* 1730 */ 's', + 'h', + 'r', + 'a', + 'v', + '.', + 'q', + 'b', + 9, + 0, + /* 1740 */ 's', + 'h', + 'l', + 'l', + 'v', + '.', + 'q', + 'b', + 9, + 0, + /* 1750 */ 'r', + 'e', + 'p', + 'l', + 'v', + '.', + 'q', + 'b', + 9, + 0, + /* 1760 */ 's', + 'h', + 'r', + 'l', + 'v', + '.', + 'q', + 'b', + 9, + 0, + /* 1770 */ 'r', + 'a', + 'd', + 'd', + 'u', + '.', + 'w', + '.', + 'q', + 'b', + 9, + 0, + /* 1782 */ 's', + 'b', + 9, + 0, + /* 1786 */ 'm', + 'o', + 'd', + 's', + 'u', + 'b', + 9, + 0, + /* 1794 */ 'm', + 's', + 'u', + 'b', + 9, + 0, + /* 1800 */ 'b', + 'c', + 9, + 0, + /* 1804 */ 'b', + 'g', + 'e', + 'c', + 9, + 0, + /* 1810 */ 'b', + 'n', + 'e', + 'c', + 9, + 0, + /* 1816 */ 'j', + 'i', + 'c', + 9, + 0, + /* 1821 */ 'b', + 'a', + 'l', + 'c', + 9, + 0, + /* 1827 */ 'j', + 'i', + 'a', + 'l', + 'c', + 9, + 0, + /* 1834 */ 'b', + 'g', + 'e', + 'z', + 'a', + 'l', + 'c', + 9, + 0, + /* 1843 */ 'b', + 'l', + 'e', + 'z', + 'a', + 'l', + 'c', + 9, + 0, + /* 1852 */ 'b', + 'n', + 'e', + 'z', + 'a', + 'l', + 'c', + 9, + 0, + /* 1861 */ 'b', + 'e', + 'q', + 'z', + 'a', + 'l', + 'c', + 9, + 0, + /* 1870 */ 'b', + 'g', + 't', + 'z', + 'a', + 'l', + 'c', + 9, + 0, + /* 1879 */ 'b', + 'l', + 't', + 'z', + 'a', + 'l', + 'c', + 9, + 0, + /* 1888 */ 'l', + 'd', + 'p', + 'c', + 9, + 0, + /* 1894 */ 'a', + 'u', + 'i', + 'p', + 'c', + 9, + 0, + /* 1901 */ 'a', + 'l', + 'u', + 'i', + 'p', + 'c', + 9, + 0, + /* 1909 */ 'a', + 'd', + 'd', + 'i', + 'u', + 'p', + 'c', + 9, + 0, + /* 1918 */ 'l', + 'w', + 'u', + 'p', + 'c', + 9, + 0, + /* 1925 */ 'l', + 'w', + 'p', + 'c', + 9, + 0, + /* 1931 */ 'b', + 'e', + 'q', + 'c', + 9, + 0, + /* 1937 */ 'j', + 'r', + 'c', + 9, + 0, + /* 1942 */ 'a', + 'd', + 'd', + 's', + 'c', + 9, + 0, + /* 1949 */ 'b', + 'l', + 't', + 'c', + 9, + 0, + /* 1955 */ 'b', + 'g', + 'e', + 'u', + 'c', + 9, + 0, + /* 1962 */ 'b', + 'l', + 't', + 'u', + 'c', + 9, + 0, + /* 1969 */ 'b', + 'n', + 'v', + 'c', + 9, + 0, + /* 1975 */ 'b', + 'o', + 'v', + 'c', + 9, + 0, + /* 1981 */ 'a', + 'd', + 'd', + 'w', + 'c', + 9, + 0, + /* 1988 */ 'b', + 'g', + 'e', + 'z', + 'c', + 9, + 0, + /* 1995 */ 'b', + 'l', + 'e', + 'z', + 'c', + 9, + 0, + /* 2002 */ 'b', + 'n', + 'e', + 'z', + 'c', + 9, + 0, + /* 2009 */ 'b', + 'e', + 'q', + 'z', + 'c', + 9, + 0, + /* 2016 */ 'b', + 'g', + 't', + 'z', + 'c', + 9, + 0, + /* 2023 */ 'b', + 'l', + 't', + 'z', + 'c', + 9, + 0, + /* 2030 */ 'f', + 'l', + 'o', + 'g', + '2', + '.', + 'd', + 9, + 0, + /* 2039 */ 'f', + 'e', + 'x', + 'p', + '2', + '.', + 'd', + 9, + 0, + /* 2048 */ 'a', + 'd', + 'd', + '_', + 'a', + '.', + 'd', + 9, + 0, + /* 2057 */ 'f', + 'm', + 'i', + 'n', + '_', + 'a', + '.', + 'd', + 9, + 0, + /* 2067 */ 'a', + 'd', + 'd', + 's', + '_', + 'a', + '.', + 'd', + 9, + 0, + /* 2077 */ 'f', + 'm', + 'a', + 'x', + '_', + 'a', + '.', + 'd', + 9, + 0, + /* 2087 */ 'm', + 'i', + 'n', + 'a', + '.', + 'd', + 9, + 0, + /* 2095 */ 's', + 'r', + 'a', + '.', + 'd', + 9, + 0, + /* 2102 */ 'm', + 'a', + 'x', + 'a', + '.', + 'd', + 9, + 0, + /* 2110 */ 'f', + 's', + 'u', + 'b', + '.', + 'd', + 9, + 0, + /* 2118 */ 'f', + 'm', + 's', + 'u', + 'b', + '.', + 'd', + 9, + 0, + /* 2127 */ 'n', + 'm', + 's', + 'u', + 'b', + '.', + 'd', + 9, + 0, + /* 2136 */ 'n', + 'l', + 'o', + 'c', + '.', + 'd', + 9, + 0, + /* 2144 */ 'n', + 'l', + 'z', + 'c', + '.', + 'd', + 9, + 0, + /* 2152 */ 'f', + 'a', + 'd', + 'd', + '.', + 'd', + 9, + 0, + /* 2160 */ 'f', + 'm', + 'a', + 'd', + 'd', + '.', + 'd', + 9, + 0, + /* 2169 */ 'n', + 'm', + 'a', + 'd', + 'd', + '.', + 'd', + 9, + 0, + /* 2178 */ 's', + 'l', + 'd', + '.', + 'd', + 9, + 0, + /* 2185 */ 'p', + 'c', + 'k', + 'o', + 'd', + '.', + 'd', + 9, + 0, + /* 2194 */ 'i', + 'l', + 'v', + 'o', + 'd', + '.', + 'd', + 9, + 0, + /* 2203 */ 'c', + '.', + 'n', + 'g', + 'e', + '.', + 'd', + 9, + 0, + /* 2212 */ 'c', + '.', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2220 */ 'c', + 'm', + 'p', + '.', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2230 */ 'f', + 'c', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2238 */ 'c', + '.', + 'n', + 'g', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2248 */ 'c', + '.', + 'o', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2257 */ 'c', + 'm', + 'p', + '.', + 's', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2268 */ 'f', + 's', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2276 */ 'c', + '.', + 'u', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2285 */ 'c', + 'm', + 'p', + '.', + 'u', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2296 */ 'f', + 'c', + 'u', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2305 */ 'c', + 'm', + 'p', + '.', + 's', + 'u', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2317 */ 'f', + 's', + 'u', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 2326 */ 'f', + 'c', + 'n', + 'e', + '.', + 'd', + 9, + 0, + /* 2334 */ 'f', + 's', + 'n', + 'e', + '.', + 'd', + 9, + 0, + /* 2342 */ 'f', + 'c', + 'u', + 'n', + 'e', + '.', + 'd', + 9, + 0, + /* 2351 */ 'f', + 's', + 'u', + 'n', + 'e', + '.', + 'd', + 9, + 0, + /* 2360 */ 'i', + 'n', + 's', + 'v', + 'e', + '.', + 'd', + 9, + 0, + /* 2369 */ 'c', + '.', + 'f', + '.', + 'd', + 9, + 0, + /* 2376 */ 'c', + 'm', + 'p', + '.', + 'a', + 'f', + '.', + 'd', + 9, + 0, + /* 2386 */ 'f', + 'c', + 'a', + 'f', + '.', + 'd', + 9, + 0, + /* 2394 */ 'c', + 'm', + 'p', + '.', + 's', + 'a', + 'f', + '.', + 'd', + 9, + 0, + /* 2405 */ 'f', + 's', + 'a', + 'f', + '.', + 'd', + 9, + 0, + /* 2413 */ 'm', + 's', + 'u', + 'b', + 'f', + '.', + 'd', + 9, + 0, + /* 2422 */ 'm', + 'a', + 'd', + 'd', + 'f', + '.', + 'd', + 9, + 0, + /* 2431 */ 'v', + 's', + 'h', + 'f', + '.', + 'd', + 9, + 0, + /* 2439 */ 'c', + '.', + 's', + 'f', + '.', + 'd', + 9, + 0, + /* 2447 */ 'm', + 'o', + 'v', + 'f', + '.', + 'd', + 9, + 0, + /* 2455 */ 'b', + 'n', + 'e', + 'g', + '.', + 'd', + 9, + 0, + /* 2463 */ 's', + 'r', + 'a', + 'i', + '.', + 'd', + 9, + 0, + /* 2471 */ 's', + 'l', + 'd', + 'i', + '.', + 'd', + 9, + 0, + /* 2479 */ 'b', + 'n', + 'e', + 'g', + 'i', + '.', + 'd', + 9, + 0, + /* 2488 */ 's', + 'l', + 'l', + 'i', + '.', + 'd', + 9, + 0, + /* 2496 */ 's', + 'r', + 'l', + 'i', + '.', + 'd', + 9, + 0, + /* 2504 */ 'b', + 'i', + 'n', + 's', + 'l', + 'i', + '.', + 'd', + 9, + 0, + /* 2514 */ 'c', + 'e', + 'q', + 'i', + '.', + 'd', + 9, + 0, + /* 2522 */ 's', + 'r', + 'a', + 'r', + 'i', + '.', + 'd', + 9, + 0, + /* 2531 */ 'b', + 'c', + 'l', + 'r', + 'i', + '.', + 'd', + 9, + 0, + /* 2540 */ 's', + 'r', + 'l', + 'r', + 'i', + '.', + 'd', + 9, + 0, + /* 2549 */ 'b', + 'i', + 'n', + 's', + 'r', + 'i', + '.', + 'd', + 9, + 0, + /* 2559 */ 's', + 'p', + 'l', + 'a', + 't', + 'i', + '.', + 'd', + 9, + 0, + /* 2569 */ 'b', + 's', + 'e', + 't', + 'i', + '.', + 'd', + 9, + 0, + /* 2578 */ 's', + 'u', + 'b', + 'v', + 'i', + '.', + 'd', + 9, + 0, + /* 2587 */ 'a', + 'd', + 'd', + 'v', + 'i', + '.', + 'd', + 9, + 0, + /* 2596 */ 't', + 'r', + 'u', + 'n', + 'c', + '.', + 'l', + '.', + 'd', + 9, + 0, + /* 2607 */ 'r', + 'o', + 'u', + 'n', + 'd', + '.', + 'l', + '.', + 'd', + 9, + 0, + /* 2618 */ 'c', + 'e', + 'i', + 'l', + '.', + 'l', + '.', + 'd', + 9, + 0, + /* 2628 */ 'f', + 'l', + 'o', + 'o', + 'r', + '.', + 'l', + '.', + 'd', + 9, + 0, + /* 2639 */ 'c', + 'v', + 't', + '.', + 'l', + '.', + 'd', + 9, + 0, + /* 2648 */ 's', + 'e', + 'l', + '.', + 'd', + 9, + 0, + /* 2655 */ 'c', + '.', + 'n', + 'g', + 'l', + '.', + 'd', + 9, + 0, + /* 2664 */ 'f', + 'i', + 'l', + 'l', + '.', + 'd', + 9, + 0, + /* 2672 */ 's', + 'l', + 'l', + '.', + 'd', + 9, + 0, + /* 2679 */ 'f', + 'e', + 'x', + 'u', + 'p', + 'l', + '.', + 'd', + 9, + 0, + /* 2689 */ 'f', + 'f', + 'q', + 'l', + '.', + 'd', + 9, + 0, + /* 2697 */ 's', + 'r', + 'l', + '.', + 'd', + 9, + 0, + /* 2704 */ 'b', + 'i', + 'n', + 's', + 'l', + '.', + 'd', + 9, + 0, + /* 2713 */ 'f', + 'm', + 'u', + 'l', + '.', + 'd', + 9, + 0, + /* 2721 */ 'i', + 'l', + 'v', + 'l', + '.', + 'd', + 9, + 0, + /* 2729 */ 'f', + 'm', + 'i', + 'n', + '.', + 'd', + 9, + 0, + /* 2737 */ 'c', + '.', + 'u', + 'n', + '.', + 'd', + 9, + 0, + /* 2745 */ 'c', + 'm', + 'p', + '.', + 'u', + 'n', + '.', + 'd', + 9, + 0, + /* 2755 */ 'f', + 'c', + 'u', + 'n', + '.', + 'd', + 9, + 0, + /* 2763 */ 'c', + 'm', + 'p', + '.', + 's', + 'u', + 'n', + '.', + 'd', + 9, + 0, + /* 2774 */ 'f', + 's', + 'u', + 'n', + '.', + 'd', + 9, + 0, + /* 2782 */ 'm', + 'o', + 'v', + 'n', + '.', + 'd', + 9, + 0, + /* 2790 */ 'f', + 'r', + 'c', + 'p', + '.', + 'd', + 9, + 0, + /* 2798 */ 'c', + '.', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2806 */ 'c', + 'm', + 'p', + '.', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2816 */ 'f', + 'c', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2824 */ 'c', + '.', + 's', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2833 */ 'c', + 'm', + 'p', + '.', + 's', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2844 */ 'f', + 's', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2852 */ 'c', + '.', + 'u', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2861 */ 'c', + 'm', + 'p', + '.', + 'u', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2872 */ 'f', + 'c', + 'u', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2881 */ 'c', + 'm', + 'p', + '.', + 's', + 'u', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2893 */ 'f', + 's', + 'u', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 2902 */ 's', + 'r', + 'a', + 'r', + '.', + 'd', + 9, + 0, + /* 2910 */ 'b', + 'c', + 'l', + 'r', + '.', + 'd', + 9, + 0, + /* 2918 */ 's', + 'r', + 'l', + 'r', + '.', + 'd', + 9, + 0, + /* 2926 */ 'f', + 'c', + 'o', + 'r', + '.', + 'd', + 9, + 0, + /* 2934 */ 'f', + 's', + 'o', + 'r', + '.', + 'd', + 9, + 0, + /* 2942 */ 'f', + 'e', + 'x', + 'u', + 'p', + 'r', + '.', + 'd', + 9, + 0, + /* 2952 */ 'f', + 'f', + 'q', + 'r', + '.', + 'd', + 9, + 0, + /* 2960 */ 'b', + 'i', + 'n', + 's', + 'r', + '.', + 'd', + 9, + 0, + /* 2969 */ 'i', + 'l', + 'v', + 'r', + '.', + 'd', + 9, + 0, + /* 2977 */ 'c', + 'v', + 't', + '.', + 's', + '.', + 'd', + 9, + 0, + /* 2986 */ 'a', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 2996 */ 'h', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3006 */ 'd', + 'p', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3017 */ 'f', + 't', + 'r', + 'u', + 'n', + 'c', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3029 */ 'h', + 'a', + 'd', + 'd', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3039 */ 'd', + 'p', + 'a', + 'd', + 'd', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3050 */ 'm', + 'o', + 'd', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3059 */ 'c', + 'l', + 'e', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3068 */ 'a', + 'v', + 'e', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3077 */ 'c', + 'l', + 'e', + 'i', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3087 */ 'm', + 'i', + 'n', + 'i', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3097 */ 'c', + 'l', + 't', + 'i', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3107 */ 'm', + 'a', + 'x', + 'i', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3117 */ 'm', + 'i', + 'n', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3126 */ 'd', + 'o', + 't', + 'p', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3136 */ 'a', + 'v', + 'e', + 'r', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3146 */ 's', + 'u', + 'b', + 's', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3156 */ 'a', + 'd', + 'd', + 's', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3166 */ 's', + 'a', + 't', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3175 */ 'c', + 'l', + 't', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3184 */ 'f', + 'f', + 'i', + 'n', + 't', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3195 */ 'f', + 't', + 'i', + 'n', + 't', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3206 */ 's', + 'u', + 'b', + 's', + 'u', + 'u', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3218 */ 'd', + 'i', + 'v', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3227 */ 'm', + 'a', + 'x', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3236 */ 'c', + 'o', + 'p', + 'y', + '_', + 's', + '.', + 'd', + 9, + 0, + /* 3246 */ 'a', + 'b', + 's', + '.', + 'd', + 9, + 0, + /* 3253 */ 'f', + 'c', + 'l', + 'a', + 's', + 's', + '.', + 'd', + 9, + 0, + /* 3263 */ 's', + 'p', + 'l', + 'a', + 't', + '.', + 'd', + 9, + 0, + /* 3272 */ 'b', + 's', + 'e', + 't', + '.', + 'd', + 9, + 0, + /* 3280 */ 'c', + '.', + 'n', + 'g', + 't', + '.', + 'd', + 9, + 0, + /* 3289 */ 'c', + '.', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3297 */ 'c', + 'm', + 'p', + '.', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3307 */ 'f', + 'c', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3315 */ 'c', + '.', + 'o', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3324 */ 'c', + 'm', + 'p', + '.', + 's', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3335 */ 'f', + 's', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3343 */ 'c', + '.', + 'u', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3352 */ 'c', + 'm', + 'p', + '.', + 'u', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3363 */ 'f', + 'c', + 'u', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3372 */ 'c', + 'm', + 'p', + '.', + 's', + 'u', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3384 */ 'f', + 's', + 'u', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 3393 */ 'p', + 'c', + 'n', + 't', + '.', + 'd', + 9, + 0, + /* 3401 */ 'f', + 'r', + 'i', + 'n', + 't', + '.', + 'd', + 9, + 0, + /* 3410 */ 'i', + 'n', + 's', + 'e', + 'r', + 't', + '.', + 'd', + 9, + 0, + /* 3420 */ 'f', + 's', + 'q', + 'r', + 't', + '.', + 'd', + 9, + 0, + /* 3429 */ 'f', + 'r', + 's', + 'q', + 'r', + 't', + '.', + 'd', + 9, + 0, + /* 3439 */ 's', + 't', + '.', + 'd', + 9, + 0, + /* 3445 */ 'm', + 'o', + 'v', + 't', + '.', + 'd', + 9, + 0, + /* 3453 */ 'a', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3463 */ 'h', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3473 */ 'd', + 'p', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3484 */ 'f', + 't', + 'r', + 'u', + 'n', + 'c', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3496 */ 'h', + 'a', + 'd', + 'd', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3506 */ 'd', + 'p', + 'a', + 'd', + 'd', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3517 */ 'm', + 'o', + 'd', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3526 */ 'c', + 'l', + 'e', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3535 */ 'a', + 'v', + 'e', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3544 */ 'c', + 'l', + 'e', + 'i', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3554 */ 'm', + 'i', + 'n', + 'i', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3564 */ 'c', + 'l', + 't', + 'i', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3574 */ 'm', + 'a', + 'x', + 'i', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3584 */ 'm', + 'i', + 'n', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3593 */ 'd', + 'o', + 't', + 'p', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3603 */ 'a', + 'v', + 'e', + 'r', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3613 */ 's', + 'u', + 'b', + 's', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3623 */ 'a', + 'd', + 'd', + 's', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3633 */ 's', + 'u', + 'b', + 's', + 'u', + 's', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3645 */ 's', + 'a', + 't', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3654 */ 'c', + 'l', + 't', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3663 */ 'f', + 'f', + 'i', + 'n', + 't', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3674 */ 'f', + 't', + 'i', + 'n', + 't', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3685 */ 'd', + 'i', + 'v', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3694 */ 'm', + 'a', + 'x', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3703 */ 'c', + 'o', + 'p', + 'y', + '_', + 'u', + '.', + 'd', + 9, + 0, + /* 3713 */ 'm', + 's', + 'u', + 'b', + 'v', + '.', + 'd', + 9, + 0, + /* 3722 */ 'm', + 'a', + 'd', + 'd', + 'v', + '.', + 'd', + 9, + 0, + /* 3731 */ 'p', + 'c', + 'k', + 'e', + 'v', + '.', + 'd', + 9, + 0, + /* 3740 */ 'i', + 'l', + 'v', + 'e', + 'v', + '.', + 'd', + 9, + 0, + /* 3749 */ 'f', + 'd', + 'i', + 'v', + '.', + 'd', + 9, + 0, + /* 3757 */ 'm', + 'u', + 'l', + 'v', + '.', + 'd', + 9, + 0, + /* 3765 */ 'm', + 'o', + 'v', + '.', + 'd', + 9, + 0, + /* 3772 */ 't', + 'r', + 'u', + 'n', + 'c', + '.', + 'w', + '.', + 'd', + 9, + 0, + /* 3783 */ 'r', + 'o', + 'u', + 'n', + 'd', + '.', + 'w', + '.', + 'd', + 9, + 0, + /* 3794 */ 'c', + 'e', + 'i', + 'l', + '.', + 'w', + '.', + 'd', + 9, + 0, + /* 3804 */ 'f', + 'l', + 'o', + 'o', + 'r', + '.', + 'w', + '.', + 'd', + 9, + 0, + /* 3815 */ 'c', + 'v', + 't', + '.', + 'w', + '.', + 'd', + 9, + 0, + /* 3824 */ 'f', + 'm', + 'a', + 'x', + '.', + 'd', + 9, + 0, + /* 3832 */ 'b', + 'z', + '.', + 'd', + 9, + 0, + /* 3838 */ 's', + 'e', + 'l', + 'n', + 'e', + 'z', + '.', + 'd', + 9, + 0, + /* 3848 */ 'b', + 'n', + 'z', + '.', + 'd', + 9, + 0, + /* 3855 */ 's', + 'e', + 'l', + 'e', + 'q', + 'z', + '.', + 'd', + 9, + 0, + /* 3865 */ 'm', + 'o', + 'v', + 'z', + '.', + 'd', + 9, + 0, + /* 3873 */ 's', + 'c', + 'd', + 9, + 0, + /* 3878 */ 'd', + 'a', + 'd', + 'd', + 9, + 0, + /* 3884 */ 'm', + 'a', + 'd', + 'd', + 9, + 0, + /* 3890 */ 'd', + 's', + 'h', + 'd', + 9, + 0, + /* 3896 */ 'l', + 'l', + 'd', + 9, + 0, + /* 3901 */ 'a', + 'n', + 'd', + 9, + 0, + /* 3906 */ 'p', + 'r', + 'e', + 'p', + 'e', + 'n', + 'd', + 9, + 0, + /* 3915 */ 'a', + 'p', + 'p', + 'e', + 'n', + 'd', + 9, + 0, + /* 3923 */ 'd', + 'm', + 'o', + 'd', + 9, + 0, + /* 3929 */ 's', + 'd', + 9, + 0, + /* 3933 */ 't', + 'g', + 'e', + 9, + 0, + /* 3938 */ 'c', + 'a', + 'c', + 'h', + 'e', + 9, + 0, + /* 3945 */ 'b', + 'n', + 'e', + 9, + 0, + /* 3950 */ 's', + 'n', + 'e', + 9, + 0, + /* 3955 */ 't', + 'n', + 'e', + 9, + 0, + /* 3960 */ 'm', + 'o', + 'v', + 'e', + 9, + 0, + /* 3966 */ 'b', + 'c', + '0', + 'f', + 9, + 0, + /* 3972 */ 'b', + 'c', + '1', + 'f', + 9, + 0, + /* 3978 */ 'b', + 'c', + '2', + 'f', + 9, + 0, + /* 3984 */ 'b', + 'c', + '3', + 'f', + 9, + 0, + /* 3990 */ 'p', + 'r', + 'e', + 'f', + 9, + 0, + /* 3996 */ 'm', + 'o', + 'v', + 'f', + 9, + 0, + /* 4002 */ 'n', + 'e', + 'g', + 9, + 0, + /* 4007 */ 'a', + 'd', + 'd', + '_', + 'a', + '.', + 'h', + 9, + 0, + /* 4016 */ 'm', + 'i', + 'n', + '_', + 'a', + '.', + 'h', + 9, + 0, + /* 4025 */ 'a', + 'd', + 'd', + 's', + '_', + 'a', + '.', + 'h', + 9, + 0, + /* 4035 */ 'm', + 'a', + 'x', + '_', + 'a', + '.', + 'h', + 9, + 0, + /* 4044 */ 's', + 'r', + 'a', + '.', + 'h', + 9, + 0, + /* 4051 */ 'n', + 'l', + 'o', + 'c', + '.', + 'h', + 9, + 0, + /* 4059 */ 'n', + 'l', + 'z', + 'c', + '.', + 'h', + 9, + 0, + /* 4067 */ 's', + 'l', + 'd', + '.', + 'h', + 9, + 0, + /* 4074 */ 'p', + 'c', + 'k', + 'o', + 'd', + '.', + 'h', + 9, + 0, + /* 4083 */ 'i', + 'l', + 'v', + 'o', + 'd', + '.', + 'h', + 9, + 0, + /* 4092 */ 'i', + 'n', + 's', + 'v', + 'e', + '.', + 'h', + 9, + 0, + /* 4101 */ 'v', + 's', + 'h', + 'f', + '.', + 'h', + 9, + 0, + /* 4109 */ 'b', + 'n', + 'e', + 'g', + '.', + 'h', + 9, + 0, + /* 4117 */ 's', + 'r', + 'a', + 'i', + '.', + 'h', + 9, + 0, + /* 4125 */ 's', + 'l', + 'd', + 'i', + '.', + 'h', + 9, + 0, + /* 4133 */ 'b', + 'n', + 'e', + 'g', + 'i', + '.', + 'h', + 9, + 0, + /* 4142 */ 's', + 'l', + 'l', + 'i', + '.', + 'h', + 9, + 0, + /* 4150 */ 's', + 'r', + 'l', + 'i', + '.', + 'h', + 9, + 0, + /* 4158 */ 'b', + 'i', + 'n', + 's', + 'l', + 'i', + '.', + 'h', + 9, + 0, + /* 4168 */ 'c', + 'e', + 'q', + 'i', + '.', + 'h', + 9, + 0, + /* 4176 */ 's', + 'r', + 'a', + 'r', + 'i', + '.', + 'h', + 9, + 0, + /* 4185 */ 'b', + 'c', + 'l', + 'r', + 'i', + '.', + 'h', + 9, + 0, + /* 4194 */ 's', + 'r', + 'l', + 'r', + 'i', + '.', + 'h', + 9, + 0, + /* 4203 */ 'b', + 'i', + 'n', + 's', + 'r', + 'i', + '.', + 'h', + 9, + 0, + /* 4213 */ 's', + 'p', + 'l', + 'a', + 't', + 'i', + '.', + 'h', + 9, + 0, + /* 4223 */ 'b', + 's', + 'e', + 't', + 'i', + '.', + 'h', + 9, + 0, + /* 4232 */ 's', + 'u', + 'b', + 'v', + 'i', + '.', + 'h', + 9, + 0, + /* 4241 */ 'a', + 'd', + 'd', + 'v', + 'i', + '.', + 'h', + 9, + 0, + /* 4250 */ 'f', + 'i', + 'l', + 'l', + '.', + 'h', + 9, + 0, + /* 4258 */ 's', + 'l', + 'l', + '.', + 'h', + 9, + 0, + /* 4265 */ 's', + 'r', + 'l', + '.', + 'h', + 9, + 0, + /* 4272 */ 'b', + 'i', + 'n', + 's', + 'l', + '.', + 'h', + 9, + 0, + /* 4281 */ 'i', + 'l', + 'v', + 'l', + '.', + 'h', + 9, + 0, + /* 4289 */ 'f', + 'e', + 'x', + 'd', + 'o', + '.', + 'h', + 9, + 0, + /* 4298 */ 'm', + 's', + 'u', + 'b', + '_', + 'q', + '.', + 'h', + 9, + 0, + /* 4308 */ 'm', + 'a', + 'd', + 'd', + '_', + 'q', + '.', + 'h', + 9, + 0, + /* 4318 */ 'm', + 'u', + 'l', + '_', + 'q', + '.', + 'h', + 9, + 0, + /* 4327 */ 'm', + 's', + 'u', + 'b', + 'r', + '_', + 'q', + '.', + 'h', + 9, + 0, + /* 4338 */ 'm', + 'a', + 'd', + 'd', + 'r', + '_', + 'q', + '.', + 'h', + 9, + 0, + /* 4349 */ 'm', + 'u', + 'l', + 'r', + '_', + 'q', + '.', + 'h', + 9, + 0, + /* 4359 */ 'c', + 'e', + 'q', + '.', + 'h', + 9, + 0, + /* 4366 */ 'f', + 't', + 'q', + '.', + 'h', + 9, + 0, + /* 4373 */ 's', + 'r', + 'a', + 'r', + '.', + 'h', + 9, + 0, + /* 4381 */ 'b', + 'c', + 'l', + 'r', + '.', + 'h', + 9, + 0, + /* 4389 */ 's', + 'r', + 'l', + 'r', + '.', + 'h', + 9, + 0, + /* 4397 */ 'b', + 'i', + 'n', + 's', + 'r', + '.', + 'h', + 9, + 0, + /* 4406 */ 'i', + 'l', + 'v', + 'r', + '.', + 'h', + 9, + 0, + /* 4414 */ 'a', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4424 */ 'h', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4434 */ 'd', + 'p', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4445 */ 'h', + 'a', + 'd', + 'd', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4455 */ 'd', + 'p', + 'a', + 'd', + 'd', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4466 */ 'm', + 'o', + 'd', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4475 */ 'c', + 'l', + 'e', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4484 */ 'a', + 'v', + 'e', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4493 */ 'c', + 'l', + 'e', + 'i', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4503 */ 'm', + 'i', + 'n', + 'i', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4513 */ 'c', + 'l', + 't', + 'i', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4523 */ 'm', + 'a', + 'x', + 'i', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4533 */ 'm', + 'i', + 'n', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4542 */ 'd', + 'o', + 't', + 'p', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4552 */ 'a', + 'v', + 'e', + 'r', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4562 */ 'e', + 'x', + 't', + 'r', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4572 */ 's', + 'u', + 'b', + 's', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4582 */ 'a', + 'd', + 'd', + 's', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4592 */ 's', + 'a', + 't', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4601 */ 'c', + 'l', + 't', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4610 */ 's', + 'u', + 'b', + 's', + 'u', + 'u', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4622 */ 'd', + 'i', + 'v', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4631 */ 'e', + 'x', + 't', + 'r', + 'v', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4642 */ 'm', + 'a', + 'x', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4651 */ 'c', + 'o', + 'p', + 'y', + '_', + 's', + '.', + 'h', + 9, + 0, + /* 4661 */ 's', + 'p', + 'l', + 'a', + 't', + '.', + 'h', + 9, + 0, + /* 4670 */ 'b', + 's', + 'e', + 't', + '.', + 'h', + 9, + 0, + /* 4678 */ 'p', + 'c', + 'n', + 't', + '.', + 'h', + 9, + 0, + /* 4686 */ 'i', + 'n', + 's', + 'e', + 'r', + 't', + '.', + 'h', + 9, + 0, + /* 4696 */ 's', + 't', + '.', + 'h', + 9, + 0, + /* 4702 */ 'a', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4712 */ 'h', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4722 */ 'd', + 'p', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4733 */ 'h', + 'a', + 'd', + 'd', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4743 */ 'd', + 'p', + 'a', + 'd', + 'd', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4754 */ 'm', + 'o', + 'd', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4763 */ 'c', + 'l', + 'e', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4772 */ 'a', + 'v', + 'e', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4781 */ 'c', + 'l', + 'e', + 'i', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4791 */ 'm', + 'i', + 'n', + 'i', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4801 */ 'c', + 'l', + 't', + 'i', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4811 */ 'm', + 'a', + 'x', + 'i', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4821 */ 'm', + 'i', + 'n', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4830 */ 'd', + 'o', + 't', + 'p', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4840 */ 'a', + 'v', + 'e', + 'r', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4850 */ 's', + 'u', + 'b', + 's', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4860 */ 'a', + 'd', + 'd', + 's', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4870 */ 's', + 'u', + 'b', + 's', + 'u', + 's', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4882 */ 's', + 'a', + 't', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4891 */ 'c', + 'l', + 't', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4900 */ 'd', + 'i', + 'v', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4909 */ 'm', + 'a', + 'x', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4918 */ 'c', + 'o', + 'p', + 'y', + '_', + 'u', + '.', + 'h', + 9, + 0, + /* 4928 */ 'm', + 's', + 'u', + 'b', + 'v', + '.', + 'h', + 9, + 0, + /* 4937 */ 'm', + 'a', + 'd', + 'd', + 'v', + '.', + 'h', + 9, + 0, + /* 4946 */ 'p', + 'c', + 'k', + 'e', + 'v', + '.', + 'h', + 9, + 0, + /* 4955 */ 'i', + 'l', + 'v', + 'e', + 'v', + '.', + 'h', + 9, + 0, + /* 4964 */ 'm', + 'u', + 'l', + 'v', + '.', + 'h', + 9, + 0, + /* 4972 */ 'b', + 'z', + '.', + 'h', + 9, + 0, + /* 4978 */ 'b', + 'n', + 'z', + '.', + 'h', + 9, + 0, + /* 4985 */ 'd', + 's', + 'b', + 'h', + 9, + 0, + /* 4991 */ 'w', + 's', + 'b', + 'h', + 9, + 0, + /* 4997 */ 's', + 'e', + 'h', + 9, + 0, + /* 5002 */ 'l', + 'h', + 9, + 0, + /* 5006 */ 's', + 'h', + 'r', + 'a', + '.', + 'p', + 'h', + 9, + 0, + /* 5015 */ 'p', + 'r', + 'e', + 'c', + 'r', + 'q', + '.', + 'q', + 'b', + '.', + 'p', + 'h', + 9, + 0, + /* 5029 */ 'p', + 'r', + 'e', + 'c', + 'r', + '.', + 'q', + 'b', + '.', + 'p', + 'h', + 9, + 0, + /* 5042 */ 'p', + 'r', + 'e', + 'c', + 'r', + 'q', + 'u', + '_', + 's', + '.', + 'q', + 'b', + '.', + 'p', + 'h', + 9, + 0, + /* 5059 */ 'c', + 'm', + 'p', + '.', + 'l', + 'e', + '.', + 'p', + 'h', + 9, + 0, + /* 5070 */ 's', + 'u', + 'b', + 'q', + 'h', + '.', + 'p', + 'h', + 9, + 0, + /* 5080 */ 'a', + 'd', + 'd', + 'q', + 'h', + '.', + 'p', + 'h', + 9, + 0, + /* 5090 */ 'p', + 'i', + 'c', + 'k', + '.', + 'p', + 'h', + 9, + 0, + /* 5099 */ 's', + 'h', + 'l', + 'l', + '.', + 'p', + 'h', + 9, + 0, + /* 5108 */ 'r', + 'e', + 'p', + 'l', + '.', + 'p', + 'h', + 9, + 0, + /* 5117 */ 's', + 'h', + 'r', + 'l', + '.', + 'p', + 'h', + 9, + 0, + /* 5126 */ 'p', + 'a', + 'c', + 'k', + 'r', + 'l', + '.', + 'p', + 'h', + 9, + 0, + /* 5137 */ 'm', + 'u', + 'l', + '.', + 'p', + 'h', + 9, + 0, + /* 5145 */ 's', + 'u', + 'b', + 'q', + '.', + 'p', + 'h', + 9, + 0, + /* 5154 */ 'a', + 'd', + 'd', + 'q', + '.', + 'p', + 'h', + 9, + 0, + /* 5163 */ 'c', + 'm', + 'p', + '.', + 'e', + 'q', + '.', + 'p', + 'h', + 9, + 0, + /* 5174 */ 's', + 'h', + 'r', + 'a', + '_', + 'r', + '.', + 'p', + 'h', + 9, + 0, + /* 5185 */ 's', + 'u', + 'b', + 'q', + 'h', + '_', + 'r', + '.', + 'p', + 'h', + 9, + 0, + /* 5197 */ 'a', + 'd', + 'd', + 'q', + 'h', + '_', + 'r', + '.', + 'p', + 'h', + 9, + 0, + /* 5209 */ 's', + 'h', + 'r', + 'a', + 'v', + '_', + 'r', + '.', + 'p', + 'h', + 9, + 0, + /* 5221 */ 's', + 'h', + 'l', + 'l', + '_', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5232 */ 'm', + 'u', + 'l', + '_', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5242 */ 's', + 'u', + 'b', + 'q', + '_', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5253 */ 'a', + 'd', + 'd', + 'q', + '_', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5264 */ 'm', + 'u', + 'l', + 'q', + '_', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5275 */ 'a', + 'b', + 's', + 'q', + '_', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5286 */ 's', + 'u', + 'b', + 'u', + '_', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5297 */ 'a', + 'd', + 'd', + 'u', + '_', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5308 */ 's', + 'h', + 'l', + 'l', + 'v', + '_', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5320 */ 'm', + 'u', + 'l', + 'q', + '_', + 'r', + 's', + '.', + 'p', + 'h', + 9, + 0, + /* 5332 */ 'c', + 'm', + 'p', + '.', + 'l', + 't', + '.', + 'p', + 'h', + 9, + 0, + /* 5343 */ 's', + 'u', + 'b', + 'u', + '.', + 'p', + 'h', + 9, + 0, + /* 5352 */ 'a', + 'd', + 'd', + 'u', + '.', + 'p', + 'h', + 9, + 0, + /* 5361 */ 's', + 'h', + 'r', + 'a', + 'v', + '.', + 'p', + 'h', + 9, + 0, + /* 5371 */ 's', + 'h', + 'l', + 'l', + 'v', + '.', + 'p', + 'h', + 9, + 0, + /* 5381 */ 'r', + 'e', + 'p', + 'l', + 'v', + '.', + 'p', + 'h', + 9, + 0, + /* 5391 */ 's', + 'h', + 'r', + 'l', + 'v', + '.', + 'p', + 'h', + 9, + 0, + /* 5401 */ 'd', + 'p', + 'a', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5411 */ 'd', + 'p', + 'a', + 'q', + 'x', + '_', + 's', + 'a', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5426 */ 'd', + 'p', + 's', + 'q', + 'x', + '_', + 's', + 'a', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5441 */ 'm', + 'u', + 'l', + 's', + 'a', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5453 */ 'd', + 'p', + 'a', + 'q', + '_', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5466 */ 'm', + 'u', + 'l', + 's', + 'a', + 'q', + '_', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5481 */ 'd', + 'p', + 's', + 'q', + '_', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5494 */ 'd', + 'p', + 'a', + 'q', + 'x', + '_', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5508 */ 'd', + 'p', + 's', + 'q', + 'x', + '_', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5522 */ 'd', + 'p', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5532 */ 'd', + 'p', + 'a', + 'x', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5543 */ 'd', + 'p', + 's', + 'x', + '.', + 'w', + '.', + 'p', + 'h', + 9, + 0, + /* 5554 */ 's', + 'h', + 9, + 0, + /* 5558 */ 'd', + 'm', + 'u', + 'h', + 9, + 0, + /* 5564 */ 's', + 'y', + 'n', + 'c', + 'i', + 9, + 0, + /* 5571 */ 'd', + 'a', + 'd', + 'd', + 'i', + 9, + 0, + /* 5578 */ 'a', + 'n', + 'd', + 'i', + 9, + 0, + /* 5584 */ 't', + 'g', + 'e', + 'i', + 9, + 0, + /* 5590 */ 's', + 'n', + 'e', + 'i', + 9, + 0, + /* 5596 */ 't', + 'n', + 'e', + 'i', + 9, + 0, + /* 5602 */ 'd', + 'a', + 'h', + 'i', + 9, + 0, + /* 5608 */ 'm', + 'f', + 'h', + 'i', + 9, + 0, + /* 5614 */ 'm', + 't', + 'h', + 'i', + 9, + 0, + /* 5620 */ '.', + 'a', + 'l', + 'i', + 'g', + 'n', + 32, + '2', + 10, + 9, + 'l', + 'i', + 9, + 0, + /* 5634 */ 'd', + 'l', + 'i', + 9, + 0, + /* 5639 */ 'c', + 'm', + 'p', + 'i', + 9, + 0, + /* 5645 */ 's', + 'e', + 'q', + 'i', + 9, + 0, + /* 5651 */ 't', + 'e', + 'q', + 'i', + 9, + 0, + /* 5657 */ 'x', + 'o', + 'r', + 'i', + 9, + 0, + /* 5663 */ 'd', + 'a', + 't', + 'i', + 9, + 0, + /* 5669 */ 's', + 'l', + 't', + 'i', + 9, + 0, + /* 5675 */ 't', + 'l', + 't', + 'i', + 9, + 0, + /* 5681 */ 'd', + 'a', + 'u', + 'i', + 9, + 0, + /* 5687 */ 'l', + 'u', + 'i', + 9, + 0, + /* 5692 */ 'j', + 9, + 0, + /* 5695 */ 'b', + 'r', + 'e', + 'a', + 'k', + 9, + 0, + /* 5702 */ 'c', + 'v', + 't', + '.', + 'd', + '.', + 'l', + 9, + 0, + /* 5711 */ 'c', + 'v', + 't', + '.', + 's', + '.', + 'l', + 9, + 0, + /* 5720 */ 'b', + 'a', + 'l', + 9, + 0, + /* 5725 */ 'j', + 'a', + 'l', + 9, + 0, + /* 5730 */ 'b', + 'g', + 'e', + 'z', + 'a', + 'l', + 9, + 0, + /* 5738 */ 'b', + 'l', + 't', + 'z', + 'a', + 'l', + 9, + 0, + /* 5746 */ 'd', + 'p', + 'a', + 'u', + '.', + 'h', + '.', + 'q', + 'b', + 'l', + 9, + 0, + /* 5758 */ 'd', + 'p', + 's', + 'u', + '.', + 'h', + '.', + 'q', + 'b', + 'l', + 9, + 0, + /* 5770 */ 'm', + 'u', + 'l', + 'e', + 'u', + '_', + 's', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'l', + 9, + 0, + /* 5786 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'u', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'l', + 9, + 0, + /* 5801 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'q', + 'u', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'l', + 9, + 0, + /* 5817 */ 'l', + 'd', + 'l', + 9, + 0, + /* 5822 */ 's', + 'd', + 'l', + 9, + 0, + /* 5827 */ 'b', + 'n', + 'e', + 'l', + 9, + 0, + /* 5833 */ 'b', + 'c', + '0', + 'f', + 'l', + 9, + 0, + /* 5840 */ 'b', + 'c', + '1', + 'f', + 'l', + 9, + 0, + /* 5847 */ 'b', + 'c', + '2', + 'f', + 'l', + 9, + 0, + /* 5854 */ 'b', + 'c', + '3', + 'f', + 'l', + 9, + 0, + /* 5861 */ 'm', + 'a', + 'q', + '_', + 's', + 'a', + '.', + 'w', + '.', + 'p', + 'h', + 'l', + 9, + 0, + /* 5875 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'q', + '.', + 'w', + '.', + 'p', + 'h', + 'l', + 9, + 0, + /* 5889 */ 'm', + 'a', + 'q', + '_', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 'l', + 9, + 0, + /* 5902 */ 'm', + 'u', + 'l', + 'e', + 'q', + '_', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 'l', + 9, + 0, + /* 5917 */ 's', + 'y', + 's', + 'c', + 'a', + 'l', + 'l', + 9, + 0, + /* 5926 */ 'b', + 'g', + 'e', + 'z', + 'a', + 'l', + 'l', + 9, + 0, + /* 5935 */ 'b', + 'l', + 't', + 'z', + 'a', + 'l', + 'l', + 9, + 0, + /* 5944 */ 'd', + 's', + 'l', + 'l', + 9, + 0, + /* 5950 */ 'b', + 'e', + 'q', + 'l', + 9, + 0, + /* 5956 */ 'd', + 's', + 'r', + 'l', + 9, + 0, + /* 5962 */ 'b', + 'c', + '0', + 't', + 'l', + 9, + 0, + /* 5969 */ 'b', + 'c', + '1', + 't', + 'l', + 9, + 0, + /* 5976 */ 'b', + 'c', + '2', + 't', + 'l', + 9, + 0, + /* 5983 */ 'b', + 'c', + '3', + 't', + 'l', + 9, + 0, + /* 5990 */ 'd', + 'm', + 'u', + 'l', + 9, + 0, + /* 5996 */ 'l', + 'w', + 'l', + 9, + 0, + /* 6001 */ 's', + 'w', + 'l', + 9, + 0, + /* 6006 */ 'b', + 'g', + 'e', + 'z', + 'l', + 9, + 0, + /* 6013 */ 'b', + 'l', + 'e', + 'z', + 'l', + 9, + 0, + /* 6020 */ 'b', + 'g', + 't', + 'z', + 'l', + 9, + 0, + /* 6027 */ 'b', + 'l', + 't', + 'z', + 'l', + 9, + 0, + /* 6034 */ 'l', + 'w', + 'm', + 9, + 0, + /* 6039 */ 's', + 'w', + 'm', + 9, + 0, + /* 6044 */ 'b', + 'a', + 'l', + 'i', + 'g', + 'n', + 9, + 0, + /* 6052 */ 'd', + 'a', + 'l', + 'i', + 'g', + 'n', + 9, + 0, + /* 6060 */ 'm', + 'o', + 'v', + 'n', + 9, + 0, + /* 6066 */ 'd', + 'c', + 'l', + 'o', + 9, + 0, + /* 6072 */ 'm', + 'f', + 'l', + 'o', + 9, + 0, + /* 6078 */ 's', + 'h', + 'i', + 'l', + 'o', + 9, + 0, + /* 6085 */ 'm', + 't', + 'l', + 'o', + 9, + 0, + /* 6091 */ 'd', + 'b', + 'i', + 't', + 's', + 'w', + 'a', + 'p', + 9, + 0, + /* 6101 */ 's', + 'd', + 'b', + 'b', + 'p', + 9, + 0, + /* 6108 */ 'e', + 'x', + 't', + 'p', + 'd', + 'p', + 9, + 0, + /* 6116 */ 'm', + 'o', + 'v', + 'e', + 'p', + 9, + 0, + /* 6123 */ 'm', + 't', + 'h', + 'l', + 'i', + 'p', + 9, + 0, + /* 6131 */ 'c', + 'm', + 'p', + 9, + 0, + /* 6136 */ 'd', + 'p', + 'o', + 'p', + 9, + 0, + /* 6142 */ 'a', + 'd', + 'd', + 'i', + 'u', + 'r', + '1', + 's', + 'p', + 9, + 0, + /* 6153 */ 'l', + 'o', + 'a', + 'd', + '_', + 'c', + 'c', + 'o', + 'n', + 'd', + '_', + 'd', + 's', + 'p', + 9, + 0, + /* 6169 */ 's', + 't', + 'o', + 'r', + 'e', + '_', + 'c', + 'c', + 'o', + 'n', + 'd', + '_', + 'd', + 's', + 'p', + 9, + 0, + /* 6186 */ 'r', + 'd', + 'd', + 's', + 'p', + 9, + 0, + /* 6193 */ 'w', + 'r', + 'd', + 's', + 'p', + 9, + 0, + /* 6200 */ 'j', + 'r', + 'a', + 'd', + 'd', + 'i', + 'u', + 's', + 'p', + 9, + 0, + /* 6211 */ 'e', + 'x', + 't', + 'p', + 9, + 0, + /* 6217 */ 'l', + 'w', + 'p', + 9, + 0, + /* 6222 */ 's', + 'w', + 'p', + 9, + 0, + /* 6227 */ 'b', + 'e', + 'q', + 9, + 0, + /* 6232 */ 's', + 'e', + 'q', + 9, + 0, + /* 6237 */ 't', + 'e', + 'q', + 9, + 0, + /* 6242 */ 'd', + 'p', + 'a', + 'u', + '.', + 'h', + '.', + 'q', + 'b', + 'r', + 9, + 0, + /* 6254 */ 'd', + 'p', + 's', + 'u', + '.', + 'h', + '.', + 'q', + 'b', + 'r', + 9, + 0, + /* 6266 */ 'm', + 'u', + 'l', + 'e', + 'u', + '_', + 's', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'r', + 9, + 0, + /* 6282 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'u', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'r', + 9, + 0, + /* 6297 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'q', + 'u', + '.', + 'p', + 'h', + '.', + 'q', + 'b', + 'r', + 9, + 0, + /* 6313 */ 'l', + 'd', + 'r', + 9, + 0, + /* 6318 */ 's', + 'd', + 'r', + 9, + 0, + /* 6323 */ 'm', + 'a', + 'q', + '_', + 's', + 'a', + '.', + 'w', + '.', + 'p', + 'h', + 'r', + 9, + 0, + /* 6337 */ 'p', + 'r', + 'e', + 'c', + 'e', + 'q', + '.', + 'w', + '.', + 'p', + 'h', + 'r', + 9, + 0, + /* 6351 */ 'm', + 'a', + 'q', + '_', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 'r', + 9, + 0, + /* 6364 */ 'm', + 'u', + 'l', + 'e', + 'q', + '_', + 's', + '.', + 'w', + '.', + 'p', + 'h', + 'r', + 9, + 0, + /* 6379 */ 'j', + 'r', + 9, + 0, + /* 6383 */ 'j', + 'a', + 'l', + 'r', + 9, + 0, + /* 6389 */ 'n', + 'o', + 'r', + 9, + 0, + /* 6394 */ 'x', + 'o', + 'r', + 9, + 0, + /* 6399 */ 'd', + 'r', + 'o', + 't', + 'r', + 9, + 0, + /* 6406 */ 'r', + 'd', + 'h', + 'w', + 'r', + 9, + 0, + /* 6413 */ 'l', + 'w', + 'r', + 9, + 0, + /* 6418 */ 's', + 'w', + 'r', + 9, + 0, + /* 6423 */ 'm', + 'i', + 'n', + 'a', + '.', + 's', + 9, + 0, + /* 6431 */ 'm', + 'a', + 'x', + 'a', + '.', + 's', + 9, + 0, + /* 6439 */ 'n', + 'm', + 's', + 'u', + 'b', + '.', + 's', + 9, + 0, + /* 6448 */ 'c', + 'v', + 't', + '.', + 'd', + '.', + 's', + 9, + 0, + /* 6457 */ 'n', + 'm', + 'a', + 'd', + 'd', + '.', + 's', + 9, + 0, + /* 6466 */ 'c', + '.', + 'n', + 'g', + 'e', + '.', + 's', + 9, + 0, + /* 6475 */ 'c', + '.', + 'l', + 'e', + '.', + 's', + 9, + 0, + /* 6483 */ 'c', + 'm', + 'p', + '.', + 'l', + 'e', + '.', + 's', + 9, + 0, + /* 6493 */ 'c', + '.', + 'n', + 'g', + 'l', + 'e', + '.', + 's', + 9, + 0, + /* 6503 */ 'c', + '.', + 'o', + 'l', + 'e', + '.', + 's', + 9, + 0, + /* 6512 */ 'c', + 'm', + 'p', + '.', + 's', + 'l', + 'e', + '.', + 's', + 9, + 0, + /* 6523 */ 'c', + '.', + 'u', + 'l', + 'e', + '.', + 's', + 9, + 0, + /* 6532 */ 'c', + 'm', + 'p', + '.', + 'u', + 'l', + 'e', + '.', + 's', + 9, + 0, + /* 6543 */ 'c', + 'm', + 'p', + '.', + 's', + 'u', + 'l', + 'e', + '.', + 's', + 9, + 0, + /* 6555 */ 'c', + '.', + 'f', + '.', + 's', + 9, + 0, + /* 6562 */ 'c', + 'm', + 'p', + '.', + 'a', + 'f', + '.', + 's', + 9, + 0, + /* 6572 */ 'c', + 'm', + 'p', + '.', + 's', + 'a', + 'f', + '.', + 's', + 9, + 0, + /* 6583 */ 'm', + 's', + 'u', + 'b', + 'f', + '.', + 's', + 9, + 0, + /* 6592 */ 'm', + 'a', + 'd', + 'd', + 'f', + '.', + 's', + 9, + 0, + /* 6601 */ 'c', + '.', + 's', + 'f', + '.', + 's', + 9, + 0, + /* 6609 */ 'm', + 'o', + 'v', + 'f', + '.', + 's', + 9, + 0, + /* 6617 */ 'n', + 'e', + 'g', + '.', + 's', + 9, + 0, + /* 6624 */ 't', + 'r', + 'u', + 'n', + 'c', + '.', + 'l', + '.', + 's', + 9, + 0, + /* 6635 */ 'r', + 'o', + 'u', + 'n', + 'd', + '.', + 'l', + '.', + 's', + 9, + 0, + /* 6646 */ 'c', + 'e', + 'i', + 'l', + '.', + 'l', + '.', + 's', + 9, + 0, + /* 6656 */ 'f', + 'l', + 'o', + 'o', + 'r', + '.', + 'l', + '.', + 's', + 9, + 0, + /* 6667 */ 'c', + 'v', + 't', + '.', + 'l', + '.', + 's', + 9, + 0, + /* 6676 */ 's', + 'e', + 'l', + '.', + 's', + 9, + 0, + /* 6683 */ 'c', + '.', + 'n', + 'g', + 'l', + '.', + 's', + 9, + 0, + /* 6692 */ 'm', + 'u', + 'l', + '.', + 's', + 9, + 0, + /* 6699 */ 'm', + 'i', + 'n', + '.', + 's', + 9, + 0, + /* 6706 */ 'c', + '.', + 'u', + 'n', + '.', + 's', + 9, + 0, + /* 6714 */ 'c', + 'm', + 'p', + '.', + 'u', + 'n', + '.', + 's', + 9, + 0, + /* 6724 */ 'c', + 'm', + 'p', + '.', + 's', + 'u', + 'n', + '.', + 's', + 9, + 0, + /* 6735 */ 'm', + 'o', + 'v', + 'n', + '.', + 's', + 9, + 0, + /* 6743 */ 'c', + '.', + 'e', + 'q', + '.', + 's', + 9, + 0, + /* 6751 */ 'c', + 'm', + 'p', + '.', + 'e', + 'q', + '.', + 's', + 9, + 0, + /* 6761 */ 'c', + '.', + 's', + 'e', + 'q', + '.', + 's', + 9, + 0, + /* 6770 */ 'c', + 'm', + 'p', + '.', + 's', + 'e', + 'q', + '.', + 's', + 9, + 0, + /* 6781 */ 'c', + '.', + 'u', + 'e', + 'q', + '.', + 's', + 9, + 0, + /* 6790 */ 'c', + 'm', + 'p', + '.', + 'u', + 'e', + 'q', + '.', + 's', + 9, + 0, + /* 6801 */ 'c', + 'm', + 'p', + '.', + 's', + 'u', + 'e', + 'q', + '.', + 's', + 9, + 0, + /* 6813 */ 'a', + 'b', + 's', + '.', + 's', + 9, + 0, + /* 6820 */ 'c', + 'l', + 'a', + 's', + 's', + '.', + 's', + 9, + 0, + /* 6829 */ 'c', + '.', + 'n', + 'g', + 't', + '.', + 's', + 9, + 0, + /* 6838 */ 'c', + '.', + 'l', + 't', + '.', + 's', + 9, + 0, + /* 6846 */ 'c', + 'm', + 'p', + '.', + 'l', + 't', + '.', + 's', + 9, + 0, + /* 6856 */ 'c', + '.', + 'o', + 'l', + 't', + '.', + 's', + 9, + 0, + /* 6865 */ 'c', + 'm', + 'p', + '.', + 's', + 'l', + 't', + '.', + 's', + 9, + 0, + /* 6876 */ 'c', + '.', + 'u', + 'l', + 't', + '.', + 's', + 9, + 0, + /* 6885 */ 'c', + 'm', + 'p', + '.', + 'u', + 'l', + 't', + '.', + 's', + 9, + 0, + /* 6896 */ 'c', + 'm', + 'p', + '.', + 's', + 'u', + 'l', + 't', + '.', + 's', + 9, + 0, + /* 6908 */ 'r', + 'i', + 'n', + 't', + '.', + 's', + 9, + 0, + /* 6916 */ 's', + 'q', + 'r', + 't', + '.', + 's', + 9, + 0, + /* 6924 */ 'm', + 'o', + 'v', + 't', + '.', + 's', + 9, + 0, + /* 6932 */ 'd', + 'i', + 'v', + '.', + 's', + 9, + 0, + /* 6939 */ 'm', + 'o', + 'v', + '.', + 's', + 9, + 0, + /* 6946 */ 't', + 'r', + 'u', + 'n', + 'c', + '.', + 'w', + '.', + 's', + 9, + 0, + /* 6957 */ 'r', + 'o', + 'u', + 'n', + 'd', + '.', + 'w', + '.', + 's', + 9, + 0, + /* 6968 */ 'c', + 'e', + 'i', + 'l', + '.', + 'w', + '.', + 's', + 9, + 0, + /* 6978 */ 'f', + 'l', + 'o', + 'o', + 'r', + '.', + 'w', + '.', + 's', + 9, + 0, + /* 6989 */ 'c', + 'v', + 't', + '.', + 'w', + '.', + 's', + 9, + 0, + /* 6998 */ 'm', + 'a', + 'x', + '.', + 's', + 9, + 0, + /* 7005 */ 's', + 'e', + 'l', + 'n', + 'e', + 'z', + '.', + 's', + 9, + 0, + /* 7015 */ 's', + 'e', + 'l', + 'e', + 'q', + 'z', + '.', + 's', + 9, + 0, + /* 7025 */ 'm', + 'o', + 'v', + 'z', + '.', + 's', + 9, + 0, + /* 7033 */ 'j', + 'a', + 'l', + 's', + 9, + 0, + /* 7039 */ 'b', + 'g', + 'e', + 'z', + 'a', + 'l', + 's', + 9, + 0, + /* 7048 */ 'b', + 'l', + 't', + 'z', + 'a', + 'l', + 's', + 9, + 0, + /* 7057 */ 'j', + 'a', + 'l', + 'r', + 's', + 9, + 0, + /* 7064 */ 'l', + 'w', + 'x', + 's', + 9, + 0, + /* 7070 */ 'b', + 'c', + '0', + 't', + 9, + 0, + /* 7076 */ 'b', + 'c', + '1', + 't', + 9, + 0, + /* 7082 */ 'b', + 'c', + '2', + 't', + 9, + 0, + /* 7088 */ 'b', + 'c', + '3', + 't', + 9, + 0, + /* 7094 */ 'w', + 'a', + 'i', + 't', + 9, + 0, + /* 7100 */ 's', + 'l', + 't', + 9, + 0, + /* 7105 */ 't', + 'l', + 't', + 9, + 0, + /* 7110 */ 'd', + 'm', + 'u', + 'l', + 't', + 9, + 0, + /* 7117 */ 'n', + 'o', + 't', + 9, + 0, + /* 7122 */ 'm', + 'o', + 'v', + 't', + 9, + 0, + /* 7128 */ 'l', + 'b', + 'u', + 9, + 0, + /* 7133 */ 'd', + 's', + 'u', + 'b', + 'u', + 9, + 0, + /* 7140 */ 'm', + 's', + 'u', + 'b', + 'u', + 9, + 0, + /* 7147 */ 'b', + 'a', + 'd', + 'd', + 'u', + 9, + 0, + /* 7154 */ 'd', + 'a', + 'd', + 'd', + 'u', + 9, + 0, + /* 7161 */ 'm', + 'a', + 'd', + 'd', + 'u', + 9, + 0, + /* 7168 */ 'd', + 'm', + 'o', + 'd', + 'u', + 9, + 0, + /* 7175 */ 't', + 'g', + 'e', + 'u', + 9, + 0, + /* 7181 */ 'l', + 'h', + 'u', + 9, + 0, + /* 7186 */ 'd', + 'm', + 'u', + 'h', + 'u', + 9, + 0, + /* 7193 */ 'd', + 'a', + 'd', + 'd', + 'i', + 'u', + 9, + 0, + /* 7201 */ 't', + 'g', + 'e', + 'i', + 'u', + 9, + 0, + /* 7208 */ 's', + 'l', + 't', + 'i', + 'u', + 9, + 0, + /* 7215 */ 't', + 'l', + 't', + 'i', + 'u', + 9, + 0, + /* 7222 */ 'v', + '3', + 'm', + 'u', + 'l', + 'u', + 9, + 0, + /* 7230 */ 'd', + 'm', + 'u', + 'l', + 'u', + 9, + 0, + /* 7237 */ 'v', + 'm', + 'u', + 'l', + 'u', + 9, + 0, + /* 7244 */ 's', + 'l', + 't', + 'u', + 9, + 0, + /* 7250 */ 't', + 'l', + 't', + 'u', + 9, + 0, + /* 7256 */ 'd', + 'm', + 'u', + 'l', + 't', + 'u', + 9, + 0, + /* 7264 */ 'd', + 'd', + 'i', + 'v', + 'u', + 9, + 0, + /* 7271 */ 'l', + 'w', + 'u', + 9, + 0, + /* 7276 */ 'a', + 'n', + 'd', + '.', + 'v', + 9, + 0, + /* 7283 */ 'm', + 'o', + 'v', + 'e', + '.', + 'v', + 9, + 0, + /* 7291 */ 'b', + 's', + 'e', + 'l', + '.', + 'v', + 9, + 0, + /* 7299 */ 'n', + 'o', + 'r', + '.', + 'v', + 9, + 0, + /* 7306 */ 'x', + 'o', + 'r', + '.', + 'v', + 9, + 0, + /* 7313 */ 'b', + 'z', + '.', + 'v', + 9, + 0, + /* 7319 */ 'b', + 'm', + 'z', + '.', + 'v', + 9, + 0, + /* 7326 */ 'b', + 'n', + 'z', + '.', + 'v', + 9, + 0, + /* 7333 */ 'b', + 'm', + 'n', + 'z', + '.', + 'v', + 9, + 0, + /* 7341 */ 'd', + 's', + 'r', + 'a', + 'v', + 9, + 0, + /* 7348 */ 'b', + 'i', + 't', + 'r', + 'e', + 'v', + 9, + 0, + /* 7356 */ 'd', + 'd', + 'i', + 'v', + 9, + 0, + /* 7362 */ 'd', + 's', + 'l', + 'l', + 'v', + 9, + 0, + /* 7369 */ 'd', + 's', + 'r', + 'l', + 'v', + 9, + 0, + /* 7376 */ 's', + 'h', + 'i', + 'l', + 'o', + 'v', + 9, + 0, + /* 7384 */ 'e', + 'x', + 't', + 'p', + 'd', + 'p', + 'v', + 9, + 0, + /* 7393 */ 'e', + 'x', + 't', + 'p', + 'v', + 9, + 0, + /* 7400 */ 'd', + 'r', + 'o', + 't', + 'r', + 'v', + 9, + 0, + /* 7408 */ 'i', + 'n', + 's', + 'v', + 9, + 0, + /* 7414 */ 'f', + 'l', + 'o', + 'g', + '2', + '.', + 'w', + 9, + 0, + /* 7423 */ 'f', + 'e', + 'x', + 'p', + '2', + '.', + 'w', + 9, + 0, + /* 7432 */ 'a', + 'd', + 'd', + '_', + 'a', + '.', + 'w', + 9, + 0, + /* 7441 */ 'f', + 'm', + 'i', + 'n', + '_', + 'a', + '.', + 'w', + 9, + 0, + /* 7451 */ 'a', + 'd', + 'd', + 's', + '_', + 'a', + '.', + 'w', + 9, + 0, + /* 7461 */ 'f', + 'm', + 'a', + 'x', + '_', + 'a', + '.', + 'w', + 9, + 0, + /* 7471 */ 's', + 'r', + 'a', + '.', + 'w', + 9, + 0, + /* 7478 */ 'f', + 's', + 'u', + 'b', + '.', + 'w', + 9, + 0, + /* 7486 */ 'f', + 'm', + 's', + 'u', + 'b', + '.', + 'w', + 9, + 0, + /* 7495 */ 'n', + 'l', + 'o', + 'c', + '.', + 'w', + 9, + 0, + /* 7503 */ 'n', + 'l', + 'z', + 'c', + '.', + 'w', + 9, + 0, + /* 7511 */ 'c', + 'v', + 't', + '.', + 'd', + '.', + 'w', + 9, + 0, + /* 7520 */ 'f', + 'a', + 'd', + 'd', + '.', + 'w', + 9, + 0, + /* 7528 */ 'f', + 'm', + 'a', + 'd', + 'd', + '.', + 'w', + 9, + 0, + /* 7537 */ 's', + 'l', + 'd', + '.', + 'w', + 9, + 0, + /* 7544 */ 'p', + 'c', + 'k', + 'o', + 'd', + '.', + 'w', + 9, + 0, + /* 7553 */ 'i', + 'l', + 'v', + 'o', + 'd', + '.', + 'w', + 9, + 0, + /* 7562 */ 'f', + 'c', + 'l', + 'e', + '.', + 'w', + 9, + 0, + /* 7570 */ 'f', + 's', + 'l', + 'e', + '.', + 'w', + 9, + 0, + /* 7578 */ 'f', + 'c', + 'u', + 'l', + 'e', + '.', + 'w', + 9, + 0, + /* 7587 */ 'f', + 's', + 'u', + 'l', + 'e', + '.', + 'w', + 9, + 0, + /* 7596 */ 'f', + 'c', + 'n', + 'e', + '.', + 'w', + 9, + 0, + /* 7604 */ 'f', + 's', + 'n', + 'e', + '.', + 'w', + 9, + 0, + /* 7612 */ 'f', + 'c', + 'u', + 'n', + 'e', + '.', + 'w', + 9, + 0, + /* 7621 */ 'f', + 's', + 'u', + 'n', + 'e', + '.', + 'w', + 9, + 0, + /* 7630 */ 'i', + 'n', + 's', + 'v', + 'e', + '.', + 'w', + 9, + 0, + /* 7639 */ 'f', + 'c', + 'a', + 'f', + '.', + 'w', + 9, + 0, + /* 7647 */ 'f', + 's', + 'a', + 'f', + '.', + 'w', + 9, + 0, + /* 7655 */ 'v', + 's', + 'h', + 'f', + '.', + 'w', + 9, + 0, + /* 7663 */ 'b', + 'n', + 'e', + 'g', + '.', + 'w', + 9, + 0, + /* 7671 */ 'p', + 'r', + 'e', + 'c', + 'r', + '_', + 's', + 'r', + 'a', + '.', + 'p', + 'h', + '.', + 'w', + 9, + 0, + /* 7687 */ 'p', + 'r', + 'e', + 'c', + 'r', + 'q', + '.', + 'p', + 'h', + '.', + 'w', + 9, + 0, + /* 7700 */ 'p', + 'r', + 'e', + 'c', + 'r', + '_', + 's', + 'r', + 'a', + '_', + 'r', + '.', + 'p', + 'h', + '.', + 'w', + 9, + 0, + /* 7718 */ 'p', + 'r', + 'e', + 'c', + 'r', + 'q', + '_', + 'r', + 's', + '.', + 'p', + 'h', + '.', + 'w', + 9, + 0, + /* 7734 */ 's', + 'u', + 'b', + 'q', + 'h', + '.', + 'w', + 9, + 0, + /* 7743 */ 'a', + 'd', + 'd', + 'q', + 'h', + '.', + 'w', + 9, + 0, + /* 7752 */ 's', + 'r', + 'a', + 'i', + '.', + 'w', + 9, + 0, + /* 7760 */ 's', + 'l', + 'd', + 'i', + '.', + 'w', + 9, + 0, + /* 7768 */ 'b', + 'n', + 'e', + 'g', + 'i', + '.', + 'w', + 9, + 0, + /* 7777 */ 's', + 'l', + 'l', + 'i', + '.', + 'w', + 9, + 0, + /* 7785 */ 's', + 'r', + 'l', + 'i', + '.', + 'w', + 9, + 0, + /* 7793 */ 'b', + 'i', + 'n', + 's', + 'l', + 'i', + '.', + 'w', + 9, + 0, + /* 7803 */ 'c', + 'e', + 'q', + 'i', + '.', + 'w', + 9, + 0, + /* 7811 */ 's', + 'r', + 'a', + 'r', + 'i', + '.', + 'w', + 9, + 0, + /* 7820 */ 'b', + 'c', + 'l', + 'r', + 'i', + '.', + 'w', + 9, + 0, + /* 7829 */ 's', + 'r', + 'l', + 'r', + 'i', + '.', + 'w', + 9, + 0, + /* 7838 */ 'b', + 'i', + 'n', + 's', + 'r', + 'i', + '.', + 'w', + 9, + 0, + /* 7848 */ 's', + 'p', + 'l', + 'a', + 't', + 'i', + '.', + 'w', + 9, + 0, + /* 7858 */ 'b', + 's', + 'e', + 't', + 'i', + '.', + 'w', + 9, + 0, + /* 7867 */ 's', + 'u', + 'b', + 'v', + 'i', + '.', + 'w', + 9, + 0, + /* 7876 */ 'a', + 'd', + 'd', + 'v', + 'i', + '.', + 'w', + 9, + 0, + /* 7885 */ 'd', + 'p', + 'a', + 'q', + '_', + 's', + 'a', + '.', + 'l', + '.', + 'w', + 9, + 0, + /* 7898 */ 'd', + 'p', + 's', + 'q', + '_', + 's', + 'a', + '.', + 'l', + '.', + 'w', + 9, + 0, + /* 7911 */ 'f', + 'i', + 'l', + 'l', + '.', + 'w', + 9, + 0, + /* 7919 */ 's', + 'l', + 'l', + '.', + 'w', + 9, + 0, + /* 7926 */ 'f', + 'e', + 'x', + 'u', + 'p', + 'l', + '.', + 'w', + 9, + 0, + /* 7936 */ 'f', + 'f', + 'q', + 'l', + '.', + 'w', + 9, + 0, + /* 7944 */ 's', + 'r', + 'l', + '.', + 'w', + 9, + 0, + /* 7951 */ 'b', + 'i', + 'n', + 's', + 'l', + '.', + 'w', + 9, + 0, + /* 7960 */ 'f', + 'm', + 'u', + 'l', + '.', + 'w', + 9, + 0, + /* 7968 */ 'i', + 'l', + 'v', + 'l', + '.', + 'w', + 9, + 0, + /* 7976 */ 'f', + 'm', + 'i', + 'n', + '.', + 'w', + 9, + 0, + /* 7984 */ 'f', + 'c', + 'u', + 'n', + '.', + 'w', + 9, + 0, + /* 7992 */ 'f', + 's', + 'u', + 'n', + '.', + 'w', + 9, + 0, + /* 8000 */ 'f', + 'e', + 'x', + 'd', + 'o', + '.', + 'w', + 9, + 0, + /* 8009 */ 'f', + 'r', + 'c', + 'p', + '.', + 'w', + 9, + 0, + /* 8017 */ 'm', + 's', + 'u', + 'b', + '_', + 'q', + '.', + 'w', + 9, + 0, + /* 8027 */ 'm', + 'a', + 'd', + 'd', + '_', + 'q', + '.', + 'w', + 9, + 0, + /* 8037 */ 'm', + 'u', + 'l', + '_', + 'q', + '.', + 'w', + 9, + 0, + /* 8046 */ 'm', + 's', + 'u', + 'b', + 'r', + '_', + 'q', + '.', + 'w', + 9, + 0, + /* 8057 */ 'm', + 'a', + 'd', + 'd', + 'r', + '_', + 'q', + '.', + 'w', + 9, + 0, + /* 8068 */ 'm', + 'u', + 'l', + 'r', + '_', + 'q', + '.', + 'w', + 9, + 0, + /* 8078 */ 'f', + 'c', + 'e', + 'q', + '.', + 'w', + 9, + 0, + /* 8086 */ 'f', + 's', + 'e', + 'q', + '.', + 'w', + 9, + 0, + /* 8094 */ 'f', + 'c', + 'u', + 'e', + 'q', + '.', + 'w', + 9, + 0, + /* 8103 */ 'f', + 's', + 'u', + 'e', + 'q', + '.', + 'w', + 9, + 0, + /* 8112 */ 'f', + 't', + 'q', + '.', + 'w', + 9, + 0, + /* 8119 */ 's', + 'h', + 'r', + 'a', + '_', + 'r', + '.', + 'w', + 9, + 0, + /* 8129 */ 's', + 'u', + 'b', + 'q', + 'h', + '_', + 'r', + '.', + 'w', + 9, + 0, + /* 8140 */ 'a', + 'd', + 'd', + 'q', + 'h', + '_', + 'r', + '.', + 'w', + 9, + 0, + /* 8151 */ 'e', + 'x', + 't', + 'r', + '_', + 'r', + '.', + 'w', + 9, + 0, + /* 8161 */ 's', + 'h', + 'r', + 'a', + 'v', + '_', + 'r', + '.', + 'w', + 9, + 0, + /* 8172 */ 'e', + 'x', + 't', + 'r', + 'v', + '_', + 'r', + '.', + 'w', + 9, + 0, + /* 8183 */ 's', + 'r', + 'a', + 'r', + '.', + 'w', + 9, + 0, + /* 8191 */ 'b', + 'c', + 'l', + 'r', + '.', + 'w', + 9, + 0, + /* 8199 */ 's', + 'r', + 'l', + 'r', + '.', + 'w', + 9, + 0, + /* 8207 */ 'f', + 'c', + 'o', + 'r', + '.', + 'w', + 9, + 0, + /* 8215 */ 'f', + 's', + 'o', + 'r', + '.', + 'w', + 9, + 0, + /* 8223 */ 'f', + 'e', + 'x', + 'u', + 'p', + 'r', + '.', + 'w', + 9, + 0, + /* 8233 */ 'f', + 'f', + 'q', + 'r', + '.', + 'w', + 9, + 0, + /* 8241 */ 'b', + 'i', + 'n', + 's', + 'r', + '.', + 'w', + 9, + 0, + /* 8250 */ 'e', + 'x', + 't', + 'r', + '.', + 'w', + 9, + 0, + /* 8258 */ 'i', + 'l', + 'v', + 'r', + '.', + 'w', + 9, + 0, + /* 8266 */ 'c', + 'v', + 't', + '.', + 's', + '.', + 'w', + 9, + 0, + /* 8275 */ 'a', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8285 */ 'h', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8295 */ 'd', + 'p', + 's', + 'u', + 'b', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8306 */ 'f', + 't', + 'r', + 'u', + 'n', + 'c', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8318 */ 'h', + 'a', + 'd', + 'd', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8328 */ 'd', + 'p', + 'a', + 'd', + 'd', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8339 */ 'm', + 'o', + 'd', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8348 */ 'c', + 'l', + 'e', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8357 */ 'a', + 'v', + 'e', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8366 */ 'c', + 'l', + 'e', + 'i', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8376 */ 'm', + 'i', + 'n', + 'i', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8386 */ 'c', + 'l', + 't', + 'i', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8396 */ 'm', + 'a', + 'x', + 'i', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8406 */ 's', + 'h', + 'l', + 'l', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8416 */ 'm', + 'i', + 'n', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8425 */ 'd', + 'o', + 't', + 'p', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8435 */ 's', + 'u', + 'b', + 'q', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8445 */ 'a', + 'd', + 'd', + 'q', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8455 */ 'm', + 'u', + 'l', + 'q', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8465 */ 'a', + 'b', + 's', + 'q', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8475 */ 'a', + 'v', + 'e', + 'r', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8485 */ 's', + 'u', + 'b', + 's', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8495 */ 'a', + 'd', + 'd', + 's', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8505 */ 's', + 'a', + 't', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8514 */ 'c', + 'l', + 't', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8523 */ 'f', + 'f', + 'i', + 'n', + 't', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8534 */ 'f', + 't', + 'i', + 'n', + 't', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8545 */ 's', + 'u', + 'b', + 's', + 'u', + 'u', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8557 */ 'd', + 'i', + 'v', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8566 */ 's', + 'h', + 'l', + 'l', + 'v', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8577 */ 'm', + 'a', + 'x', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8586 */ 'c', + 'o', + 'p', + 'y', + '_', + 's', + '.', + 'w', + 9, + 0, + /* 8596 */ 'm', + 'u', + 'l', + 'q', + '_', + 'r', + 's', + '.', + 'w', + 9, + 0, + /* 8607 */ 'e', + 'x', + 't', + 'r', + '_', + 'r', + 's', + '.', + 'w', + 9, + 0, + /* 8618 */ 'e', + 'x', + 't', + 'r', + 'v', + '_', + 'r', + 's', + '.', + 'w', + 9, + 0, + /* 8630 */ 'f', + 'c', + 'l', + 'a', + 's', + 's', + '.', + 'w', + 9, + 0, + /* 8640 */ 's', + 'p', + 'l', + 'a', + 't', + '.', + 'w', + 9, + 0, + /* 8649 */ 'b', + 's', + 'e', + 't', + '.', + 'w', + 9, + 0, + /* 8657 */ 'f', + 'c', + 'l', + 't', + '.', + 'w', + 9, + 0, + /* 8665 */ 'f', + 's', + 'l', + 't', + '.', + 'w', + 9, + 0, + /* 8673 */ 'f', + 'c', + 'u', + 'l', + 't', + '.', + 'w', + 9, + 0, + /* 8682 */ 'f', + 's', + 'u', + 'l', + 't', + '.', + 'w', + 9, + 0, + /* 8691 */ 'p', + 'c', + 'n', + 't', + '.', + 'w', + 9, + 0, + /* 8699 */ 'f', + 'r', + 'i', + 'n', + 't', + '.', + 'w', + 9, + 0, + /* 8708 */ 'i', + 'n', + 's', + 'e', + 'r', + 't', + '.', + 'w', + 9, + 0, + /* 8718 */ 'f', + 's', + 'q', + 'r', + 't', + '.', + 'w', + 9, + 0, + /* 8727 */ 'f', + 'r', + 's', + 'q', + 'r', + 't', + '.', + 'w', + 9, + 0, + /* 8737 */ 's', + 't', + '.', + 'w', + 9, + 0, + /* 8743 */ 'a', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8753 */ 'h', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8763 */ 'd', + 'p', + 's', + 'u', + 'b', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8774 */ 'f', + 't', + 'r', + 'u', + 'n', + 'c', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8786 */ 'h', + 'a', + 'd', + 'd', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8796 */ 'd', + 'p', + 'a', + 'd', + 'd', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8807 */ 'm', + 'o', + 'd', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8816 */ 'c', + 'l', + 'e', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8825 */ 'a', + 'v', + 'e', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8834 */ 'c', + 'l', + 'e', + 'i', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8844 */ 'm', + 'i', + 'n', + 'i', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8854 */ 'c', + 'l', + 't', + 'i', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8864 */ 'm', + 'a', + 'x', + 'i', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8874 */ 'm', + 'i', + 'n', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8883 */ 'd', + 'o', + 't', + 'p', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8893 */ 'a', + 'v', + 'e', + 'r', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8903 */ 's', + 'u', + 'b', + 's', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8913 */ 'a', + 'd', + 'd', + 's', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8923 */ 's', + 'u', + 'b', + 's', + 'u', + 's', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8935 */ 's', + 'a', + 't', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8944 */ 'c', + 'l', + 't', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8953 */ 'f', + 'f', + 'i', + 'n', + 't', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8964 */ 'f', + 't', + 'i', + 'n', + 't', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8975 */ 'd', + 'i', + 'v', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8984 */ 'm', + 'a', + 'x', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 8993 */ 'c', + 'o', + 'p', + 'y', + '_', + 'u', + '.', + 'w', + 9, + 0, + /* 9003 */ 'm', + 's', + 'u', + 'b', + 'v', + '.', + 'w', + 9, + 0, + /* 9012 */ 'm', + 'a', + 'd', + 'd', + 'v', + '.', + 'w', + 9, + 0, + /* 9021 */ 'p', + 'c', + 'k', + 'e', + 'v', + '.', + 'w', + 9, + 0, + /* 9030 */ 'i', + 'l', + 'v', + 'e', + 'v', + '.', + 'w', + 9, + 0, + /* 9039 */ 'f', + 'd', + 'i', + 'v', + '.', + 'w', + 9, + 0, + /* 9047 */ 'm', + 'u', + 'l', + 'v', + '.', + 'w', + 9, + 0, + /* 9055 */ 'e', + 'x', + 't', + 'r', + 'v', + '.', + 'w', + 9, + 0, + /* 9064 */ 'f', + 'm', + 'a', + 'x', + '.', + 'w', + 9, + 0, + /* 9072 */ 'b', + 'z', + '.', + 'w', + 9, + 0, + /* 9078 */ 'b', + 'n', + 'z', + '.', + 'w', + 9, + 0, + /* 9085 */ 'l', + 'w', + 9, + 0, + /* 9089 */ 's', + 'w', + 9, + 0, + /* 9093 */ 'l', + 'h', + 'x', + 9, + 0, + /* 9098 */ 'j', + 'a', + 'l', + 'x', + 9, + 0, + /* 9104 */ 'l', + 'b', + 'u', + 'x', + 9, + 0, + /* 9110 */ 'l', + 'w', + 'x', + 9, + 0, + /* 9115 */ 'b', + 'g', + 'e', + 'z', + 9, + 0, + /* 9121 */ 'b', + 'l', + 'e', + 'z', + 9, + 0, + /* 9127 */ 'b', + 'n', + 'e', + 'z', + 9, + 0, + /* 9133 */ 's', + 'e', + 'l', + 'n', + 'e', + 'z', + 9, + 0, + /* 9141 */ 'b', + 't', + 'n', + 'e', + 'z', + 9, + 0, + /* 9148 */ 'd', + 'c', + 'l', + 'z', + 9, + 0, + /* 9154 */ 'b', + 'e', + 'q', + 'z', + 9, + 0, + /* 9160 */ 's', + 'e', + 'l', + 'e', + 'q', + 'z', + 9, + 0, + /* 9168 */ 'b', + 't', + 'e', + 'q', + 'z', + 9, + 0, + /* 9175 */ 'b', + 'g', + 't', + 'z', + 9, + 0, + /* 9181 */ 'b', + 'l', + 't', + 'z', + 9, + 0, + /* 9187 */ 'm', + 'o', + 'v', + 'z', + 9, + 0, + /* 9193 */ 's', + 'e', + 'b', + 9, + 32, + 0, + /* 9199 */ 'j', + 'r', + 'c', + 9, + 32, + 0, + /* 9205 */ 's', + 'e', + 'h', + 9, + 32, + 0, + /* 9211 */ 'd', + 'd', + 'i', + 'v', + 'u', + 9, + '$', + 'z', + 'e', + 'r', + 'o', + ',', + 32, + 0, + /* 9225 */ 'd', + 'd', + 'i', + 'v', + 9, + '$', + 'z', + 'e', + 'r', + 'o', + ',', + 32, + 0, + /* 9238 */ 'a', + 'd', + 'd', + 'i', + 'u', + 9, + '$', + 's', + 'p', + ',', + 32, + 0, + /* 9250 */ 'c', + 'i', + 'n', + 's', + '3', + '2', + 32, + 0, + /* 9258 */ 'e', + 'x', + 't', + 's', + '3', + '2', + 32, + 0, + /* 9266 */ 's', + 'y', + 'n', + 'c', + 32, + 0, + /* 9272 */ 9, + '.', + 'w', + 'o', + 'r', + 'd', + 32, + 0, + /* 9280 */ 'd', + 'i', + 'n', + 's', + 'm', + 32, + 0, + /* 9287 */ 'd', + 'e', + 'x', + 't', + 'm', + 32, + 0, + /* 9294 */ 'c', + 'i', + 'n', + 's', + 32, + 0, + /* 9300 */ 'd', + 'i', + 'n', + 's', + 32, + 0, + /* 9306 */ 'e', + 'x', + 't', + 's', + 32, + 0, + /* 9312 */ 'd', + 'e', + 'x', + 't', + 32, + 0, + /* 9318 */ 'd', + 'i', + 'n', + 's', + 'u', + 32, + 0, + /* 9325 */ 'd', + 'e', + 'x', + 't', + 'u', + 32, + 0, + /* 9332 */ 'b', + 'c', + '1', + 'n', + 'e', + 'z', + 32, + 0, + /* 9340 */ 'b', + 'c', + '2', + 'n', + 'e', + 'z', + 32, + 0, + /* 9348 */ 'b', + 'c', + '1', + 'e', + 'q', + 'z', + 32, + 0, + /* 9356 */ 'b', + 'c', + '2', + 'e', + 'q', + 'z', + 32, + 0, + /* 9364 */ 'c', + '.', + 0, + /* 9367 */ 'b', + 'r', + 'e', + 'a', + 'k', + 32, + '0', + 0, + /* 9375 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'E', + 'N', + 'D', + 0, + /* 9388 */ 'B', + 'U', + 'N', + 'D', + 'L', + 'E', + 0, + /* 9395 */ 'D', + 'B', + 'G', + '_', + 'V', + 'A', + 'L', + 'U', + 'E', + 0, + /* 9405 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'S', + 'T', + 'A', + 'R', + 'T', + 0, + /* 9420 */ 'j', + 'r', + 'c', + 9, + 32, + '$', + 'r', + 'a', + 0, + /* 9429 */ 'j', + 'r', + 9, + 32, + '$', + 'r', + 'a', + 0, + /* 9437 */ 'e', + 'h', + 'b', + 0, + /* 9441 */ 'p', + 'a', + 'u', + 's', + 'e', + 0, + /* 9447 */ 't', + 'l', + 'b', + 'w', + 'i', + 0, + /* 9453 */ 'f', + 'o', + 'o', + 0, + /* 9457 */ 't', + 'l', + 'b', + 'p', + 0, + /* 9462 */ 's', + 's', + 'n', + 'o', + 'p', + 0, + /* 9468 */ 't', + 'l', + 'b', + 'r', + 0, + /* 9473 */ 't', + 'l', + 'b', + 'w', + 'r', + 0, + /* 9479 */ 'd', + 'e', + 'r', + 'e', + 't', + 0, + /* 9485 */ 'w', + 'a', + 'i', + 't', + 0, }; #endif @@ -4697,12 +13088,11 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) uint64_t Bits = (Bits2 << 32) | Bits1; // assert(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 16383)-1); + SStream_concat0(O, AsmStrs + (Bits & 16383) - 1); #endif - // Fragment 0 encoded into 4 bits for 11 unique commands. - //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); + // printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); switch ((Bits >> 14) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: @@ -4711,69 +13101,68 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 1: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - printOperand(MI, 0, O); + printOperand(MI, 0, O); break; case 2: // ADDIUS5_MM, CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHI_DSP,... - printOperand(MI, 1, O); - SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); break; case 3: // AND16_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, OR16_MM, XOR16_MM - printOperand(MI, 2, O); - SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); break; case 4: // BREAK16_MM, SDBBP16_MM - printUnsignedImm8(MI, 0, O); + printUnsignedImm8(MI, 0, O); return; break; case 5: // CACHE, CACHE_MM, CACHE_R6, PREF, PREF_MM, PREF_R6 - printUnsignedImm(MI, 2, O); - SStream_concat0(O, ", "); - printMemOperand(MI, 0, O); + printUnsignedImm(MI, 2, O); + SStream_concat0(O, ", "); + printMemOperand(MI, 0, O); return; break; case 6: // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM - printFCCOperand(MI, 2, O); + printFCCOperand(MI, 2, O); break; case 7: // LWM16_MM, LWM32_MM, LWM_MM, MOVEP_MM, SWM16_MM, SWM32_MM, SWM_MM - printRegisterList(MI, 0, O); - SStream_concat0(O, ", "); + printRegisterList(MI, 0, O); + SStream_concat0(O, ", "); break; case 8: // LWP_MM, SWP_MM - printRegisterPair(MI, 0, O); - SStream_concat0(O, ", "); - printMemOperand(MI, 2, O); + printRegisterPair(MI, 0, O); + SStream_concat0(O, ", "); + printMemOperand(MI, 2, O); return; break; case 9: // SYNCI - printMemOperand(MI, 0, O); + printMemOperand(MI, 0, O); return; break; case 10: // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... - printOperand(MI, 3, O); + printOperand(MI, 3, O); break; } - // Fragment 1 encoded into 5 bits for 17 unique commands. - //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); + // printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); switch ((Bits >> 18) & 31) { default: // llvm_unreachable("Invalid command number."); case 0: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 1: // ADDIUS5_MM, DAHI, DATI, MOVEP_MM, MultRxRyRz16, MultuRxRyRz16, SltCCRx... - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; case 2: // ADDIUSP_MM, AddiuSpImmX16, B16_MM, BAL, BALC, BC, BPOSGE32, B_MM_Pseud... @@ -4781,95 +13170,94 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 3: // AND16_MM, OR16_MM, XOR16_MM - printOperand(MI, 1, O); + printOperand(MI, 1, O); return; break; case 4: // AddiuRxPcImmX16 - SStream_concat0(O, ", $pc, "); - printOperand(MI, 1, O); + SStream_concat0(O, ", $pc, "); + printOperand(MI, 1, O); return; break; case 5: // AddiuSpImm16, Bimm16 - SStream_concat0(O, " # 16 bit inst"); + SStream_concat0(O, " # 16 bit inst"); return; break; case 6: // Bteqz16, Btnez16 - SStream_concat0(O, " # 16 bit inst"); + SStream_concat0(O, " # 16 bit inst"); return; break; case 7: // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, M... - printOperand(MI, 0, O); + printOperand(MI, 0, O); return; break; case 8: // FCMP_D32, FCMP_D32_MM, FCMP_D64 - SStream_concat0(O, ".d\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); + SStream_concat0(O, ".d\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); return; break; case 9: // FCMP_S32, FCMP_S32_MM - SStream_concat0(O, ".s\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); + SStream_concat0(O, ".s\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); return; break; case 10: // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... - SStream_concat0(O, "["); + SStream_concat0(O, "["); break; case 11: // Jal16 - SStream_concat0(O, "\n\tnop"); + SStream_concat0(O, "\n\tnop"); return; break; case 12: // JalB16 - SStream_concat0(O, "\t# branch\n\tnop"); + SStream_concat0(O, "\t# branch\n\tnop"); return; break; case 13: // LWM16_MM, LWM32_MM, LWM_MM, SWM16_MM, SWM32_MM, SWM_MM - printMemOperand(MI, 1, O); + printMemOperand(MI, 1, O); return; break; case 14: // LwConstant32 - SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); - printOperand(MI, 1, O); - SStream_concat0(O, "\n2:"); + SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); + printOperand(MI, 1, O); + SStream_concat0(O, "\n2:"); return; break; case 15: // SC, SCD, SCD_R6, SC_MM, SC_R6 - printMemOperand(MI, 2, O); + printMemOperand(MI, 2, O); return; break; case 16: // SelBeqZ, SelBneZ - SStream_concat0(O, ", .+4\n\t\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + SStream_concat0(O, ", .+4\n\t\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); return; break; } - // Fragment 2 encoded into 4 bits for 12 unique commands. - //printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15); + // printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15); switch ((Bits >> 23) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... - printOperand(MI, 1, O); + printOperand(MI, 1, O); break; case 1: // ADDIUS5_MM, DAHI, DATI @@ -4877,67 +13265,66 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 2: // AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B, BINSLI_D, BINS... - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; case 3: // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM - printMemOperandEA(MI, 1, O); + printMemOperandEA(MI, 1, O); return; break; case 4: // BBIT0, BBIT032, BBIT1, BBIT132, LUi, LUi64, LUi_MM, LoadAddr32Imm, Loa... - printUnsignedImm(MI, 1, O); + printUnsignedImm(MI, 1, O); break; case 5: // INSERT_B, INSERT_D, INSERT_H, INSERT_W - printUnsignedImm(MI, 3, O); - SStream_concat0(O, "], "); - printOperand(MI, 2, O); + printUnsignedImm(MI, 3, O); + SStream_concat0(O, "], "); + printOperand(MI, 2, O); return; break; case 6: // INSVE_B, INSVE_D, INSVE_H, INSVE_W - printUnsignedImm(MI, 2, O); - SStream_concat0(O, "], "); - printOperand(MI, 3, O); - SStream_concat0(O, "["); - printUnsignedImm(MI, 4, O); - SStream_concat0(O, "]"); + printUnsignedImm(MI, 2, O); + SStream_concat0(O, "], "); + printOperand(MI, 3, O); + SStream_concat0(O, "["); + printUnsignedImm(MI, 4, O); + SStream_concat0(O, "]"); return; break; case 7: // LB, LB64, LBU16_MM, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_... - printMemOperand(MI, 1, O); + printMemOperand(MI, 1, O); return; break; case 8: // MOVEP_MM - SStream_concat0(O, ", "); - printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); return; break; case 9: // MultRxRyRz16, MultuRxRyRz16 - SStream_concat0(O, "\n\tmflo\t"); - printOperand(MI, 0, O); + SStream_concat0(O, "\n\tmflo\t"); + printOperand(MI, 0, O); return; break; case 10: // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... - printOperand(MI, 4, O); + printOperand(MI, 4, O); break; case 11: // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... - SStream_concat0(O, "\n\tmove\t"); - printOperand(MI, 0, O); - SStream_concat0(O, ", $t8"); + SStream_concat0(O, "\n\tmove\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", $t8"); return; break; } - // Fragment 3 encoded into 4 bits for 15 unique commands. - //printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15); + // printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15); switch ((Bits >> 27) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: @@ -4946,120 +13333,118 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 1: // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 2: // AddiuRxRxImm16, LwRxPcTcp16 - SStream_concat0(O, "\t# 16 bit inst"); + SStream_concat0(O, "\t# 16 bit inst"); return; break; case 3: // BeqzRxImm16, BnezRxImm16 - SStream_concat0(O, " # 16 bit inst"); + SStream_concat0(O, " # 16 bit inst"); return; break; case 4: // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... - SStream_concat0(O, "\n\tbteqz\t"); - printOperand(MI, 2, O); + SStream_concat0(O, "\n\tbteqz\t"); + printOperand(MI, 2, O); return; break; case 5: // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... - SStream_concat0(O, "\n\tbtnez\t"); - printOperand(MI, 2, O); + SStream_concat0(O, "\n\tbtnez\t"); + printOperand(MI, 2, O); return; break; case 6: // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... - SStream_concat0(O, "["); + SStream_concat0(O, "["); break; case 7: // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 - SStream_concat0(O, " \t# 16 bit inst"); + SStream_concat0(O, " \t# 16 bit inst"); return; break; case 8: // DSLL64_32 - SStream_concat0(O, ", 32"); + SStream_concat0(O, ", 32"); return; break; case 9: // GotPrologue16 - SStream_concat0(O, "\n\taddiu\t"); - printOperand(MI, 1, O); - SStream_concat0(O, ", $pc, "); - printOperand(MI, 3, O); - SStream_concat0(O, "\n "); + SStream_concat0(O, "\n\taddiu\t"); + printOperand(MI, 1, O); + SStream_concat0(O, ", $pc, "); + printOperand(MI, 3, O); + SStream_concat0(O, "\n "); return; break; case 10: // LBUX, LDXC1, LDXC164, LHX, LUXC1, LUXC164, LUXC1_MM, LWX, LWXC1, LWXC1... - SStream_concat0(O, "("); - printOperand(MI, 1, O); - SStream_concat0(O, ")"); + SStream_concat0(O, "("); + printOperand(MI, 1, O); + SStream_concat0(O, ")"); return; break; case 11: // LwRxSpImmX16, SwRxSpImmX16 - SStream_concat0(O, " ( "); - printOperand(MI, 1, O); - SStream_concat0(O, " ); "); + SStream_concat0(O, " ( "); + printOperand(MI, 1, O); + SStream_concat0(O, " ); "); return; break; case 12: // SLL64_32, SLL64_64 - SStream_concat0(O, ", 0"); + SStream_concat0(O, ", 0"); return; break; case 13: // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... - SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); return; break; case 14: // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... - SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); + SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); return; break; } - // Fragment 4 encoded into 3 bits for 5 unique commands. - //printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7); + // printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7); switch ((Bits >> 31) & 7) { default: // llvm_unreachable("Invalid command number."); case 0: // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; case 1: // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,... - printUnsignedImm8(MI, 2, O); + printUnsignedImm8(MI, 2, O); break; case 2: // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT... - printUnsignedImm(MI, 2, O); + printUnsignedImm(MI, 2, O); break; case 3: // BINSLI_B, BINSLI_D, BINSLI_H, BINSLI_W, BINSRI_B, BINSRI_D, BINSRI_H, ... - printUnsignedImm8(MI, 3, O); + printUnsignedImm8(MI, 3, O); break; case 4: // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... - printOperand(MI, 3, O); + printOperand(MI, 3, O); break; } - // Fragment 5 encoded into 2 bits for 3 unique commands. - //printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3); + // printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3); switch ((Bits >> 34) & 3) { default: // llvm_unreachable("Invalid command number."); case 0: @@ -5068,211 +13453,212 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 1: // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 2: // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... - SStream_concat0(O, "]"); + SStream_concat0(O, "]"); return; break; } - // Fragment 6 encoded into 1 bits for 2 unique commands. - //printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1); + // printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1); if ((Bits >> 36) & 1) { // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD... - printOperand(MI, 3, O); + printOperand(MI, 3, O); return; } else { // ALIGN, CINS, CINS32, DALIGN, DLSA, DLSA_R6, EXTS, EXTS32, LSA, LSA_R6 - printUnsignedImm(MI, 3, O); + printUnsignedImm(MI, 3, O); return; } } - /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static const char *getRegisterName(unsigned RegNo) -{ +static const char *getRegisterName(unsigned RegNo) { // assert(RegNo && RegNo < 394 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'f', '1', '0', 0, - /* 4 */ 'w', '1', '0', 0, - /* 8 */ 'f', '2', '0', 0, - /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, - /* 25 */ 'w', '2', '0', 0, - /* 29 */ 'f', '3', '0', 0, - /* 33 */ 'w', '3', '0', 0, - /* 37 */ 'a', '0', 0, - /* 40 */ 'a', 'c', '0', 0, - /* 44 */ 'f', 'c', 'c', '0', 0, - /* 49 */ 'f', '0', 0, - /* 52 */ 'k', '0', 0, - /* 55 */ 'm', 'p', 'l', '0', 0, - /* 60 */ 'p', '0', 0, - /* 63 */ 's', '0', 0, - /* 66 */ 't', '0', 0, - /* 69 */ 'v', '0', 0, - /* 72 */ 'w', '0', 0, - /* 75 */ 'f', '1', '1', 0, - /* 79 */ 'w', '1', '1', 0, - /* 83 */ 'f', '2', '1', 0, - /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, - /* 100 */ 'w', '2', '1', 0, - /* 104 */ 'f', '3', '1', 0, - /* 108 */ 'w', '3', '1', 0, - /* 112 */ 'a', '1', 0, - /* 115 */ 'a', 'c', '1', 0, - /* 119 */ 'f', 'c', 'c', '1', 0, - /* 124 */ 'f', '1', 0, - /* 127 */ 'k', '1', 0, - /* 130 */ 'm', 'p', 'l', '1', 0, - /* 135 */ 'p', '1', 0, - /* 138 */ 's', '1', 0, - /* 141 */ 't', '1', 0, - /* 144 */ 'v', '1', 0, - /* 147 */ 'w', '1', 0, - /* 150 */ 'f', '1', '2', 0, - /* 154 */ 'w', '1', '2', 0, - /* 158 */ 'f', '2', '2', 0, - /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, - /* 175 */ 'w', '2', '2', 0, - /* 179 */ 'a', '2', 0, - /* 182 */ 'a', 'c', '2', 0, - /* 186 */ 'f', 'c', 'c', '2', 0, - /* 191 */ 'f', '2', 0, - /* 194 */ 'm', 'p', 'l', '2', 0, - /* 199 */ 'p', '2', 0, - /* 202 */ 's', '2', 0, - /* 205 */ 't', '2', 0, - /* 208 */ 'w', '2', 0, - /* 211 */ 'f', '1', '3', 0, - /* 215 */ 'w', '1', '3', 0, - /* 219 */ 'f', '2', '3', 0, - /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, - /* 236 */ 'w', '2', '3', 0, - /* 240 */ 'a', '3', 0, - /* 243 */ 'a', 'c', '3', 0, - /* 247 */ 'f', 'c', 'c', '3', 0, - /* 252 */ 'f', '3', 0, - /* 255 */ 's', '3', 0, - /* 258 */ 't', '3', 0, - /* 261 */ 'w', '3', 0, - /* 264 */ 'f', '1', '4', 0, - /* 268 */ 'w', '1', '4', 0, - /* 272 */ 'f', '2', '4', 0, - /* 276 */ 'w', '2', '4', 0, - /* 280 */ 'f', 'c', 'c', '4', 0, - /* 285 */ 'f', '4', 0, - /* 288 */ 's', '4', 0, - /* 291 */ 't', '4', 0, - /* 294 */ 'w', '4', 0, - /* 297 */ 'f', '1', '5', 0, - /* 301 */ 'w', '1', '5', 0, - /* 305 */ 'f', '2', '5', 0, - /* 309 */ 'w', '2', '5', 0, - /* 313 */ 'f', 'c', 'c', '5', 0, - /* 318 */ 'f', '5', 0, - /* 321 */ 's', '5', 0, - /* 324 */ 't', '5', 0, - /* 327 */ 'w', '5', 0, - /* 330 */ 'f', '1', '6', 0, - /* 334 */ 'w', '1', '6', 0, - /* 338 */ 'f', '2', '6', 0, - /* 342 */ 'w', '2', '6', 0, - /* 346 */ 'f', 'c', 'c', '6', 0, - /* 351 */ 'f', '6', 0, - /* 354 */ 's', '6', 0, - /* 357 */ 't', '6', 0, - /* 360 */ 'w', '6', 0, - /* 363 */ 'f', '1', '7', 0, - /* 367 */ 'w', '1', '7', 0, - /* 371 */ 'f', '2', '7', 0, - /* 375 */ 'w', '2', '7', 0, - /* 379 */ 'f', 'c', 'c', '7', 0, - /* 384 */ 'f', '7', 0, - /* 387 */ 's', '7', 0, - /* 390 */ 't', '7', 0, - /* 393 */ 'w', '7', 0, - /* 396 */ 'f', '1', '8', 0, - /* 400 */ 'w', '1', '8', 0, - /* 404 */ 'f', '2', '8', 0, - /* 408 */ 'w', '2', '8', 0, - /* 412 */ 'f', '8', 0, - /* 415 */ 't', '8', 0, - /* 418 */ 'w', '8', 0, - /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, - /* 437 */ 'f', '1', '9', 0, - /* 441 */ 'w', '1', '9', 0, - /* 445 */ 'f', '2', '9', 0, - /* 449 */ 'w', '2', '9', 0, - /* 453 */ 'f', '9', 0, - /* 456 */ 't', '9', 0, - /* 459 */ 'w', '9', 0, - /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, - /* 469 */ 'r', 'a', 0, - /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0, - /* 479 */ 'p', 'c', 0, - /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, - /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, - /* 502 */ 'h', 'i', 0, - /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0, - /* 516 */ 'l', 'o', 0, - /* 519 */ 'z', 'e', 'r', 'o', 0, - /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', 't', 'e', 'p', 0, - /* 539 */ 'f', 'p', 0, - /* 542 */ 'g', 'p', 0, - /* 545 */ 's', 'p', 0, - /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0, - /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0, - /* 565 */ 'a', 't', 0, - /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, - /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, + /* 0 */ 'f', '1', '0', 0, + /* 4 */ 'w', '1', '0', 0, + /* 8 */ 'f', '2', '0', 0, + /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', + '0', 0, + /* 25 */ 'w', '2', '0', 0, + /* 29 */ 'f', '3', '0', 0, + /* 33 */ 'w', '3', '0', 0, + /* 37 */ 'a', '0', 0, + /* 40 */ 'a', 'c', '0', 0, + /* 44 */ 'f', 'c', 'c', '0', 0, + /* 49 */ 'f', '0', 0, + /* 52 */ 'k', '0', 0, + /* 55 */ 'm', 'p', 'l', '0', 0, + /* 60 */ 'p', '0', 0, + /* 63 */ 's', '0', 0, + /* 66 */ 't', '0', 0, + /* 69 */ 'v', '0', 0, + /* 72 */ 'w', '0', 0, + /* 75 */ 'f', '1', '1', 0, + /* 79 */ 'w', '1', '1', 0, + /* 83 */ 'f', '2', '1', 0, + /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', + '1', 0, + /* 100 */ 'w', '2', '1', 0, + /* 104 */ 'f', '3', '1', 0, + /* 108 */ 'w', '3', '1', 0, + /* 112 */ 'a', '1', 0, + /* 115 */ 'a', 'c', '1', 0, + /* 119 */ 'f', 'c', 'c', '1', 0, + /* 124 */ 'f', '1', 0, + /* 127 */ 'k', '1', 0, + /* 130 */ 'm', 'p', 'l', '1', 0, + /* 135 */ 'p', '1', 0, + /* 138 */ 's', '1', 0, + /* 141 */ 't', '1', 0, + /* 144 */ 'v', '1', 0, + /* 147 */ 'w', '1', 0, + /* 150 */ 'f', '1', '2', 0, + /* 154 */ 'w', '1', '2', 0, + /* 158 */ 'f', '2', '2', 0, + /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', + '2', 0, + /* 175 */ 'w', '2', '2', 0, + /* 179 */ 'a', '2', 0, + /* 182 */ 'a', 'c', '2', 0, + /* 186 */ 'f', 'c', 'c', '2', 0, + /* 191 */ 'f', '2', 0, + /* 194 */ 'm', 'p', 'l', '2', 0, + /* 199 */ 'p', '2', 0, + /* 202 */ 's', '2', 0, + /* 205 */ 't', '2', 0, + /* 208 */ 'w', '2', 0, + /* 211 */ 'f', '1', '3', 0, + /* 215 */ 'w', '1', '3', 0, + /* 219 */ 'f', '2', '3', 0, + /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', + '3', 0, + /* 236 */ 'w', '2', '3', 0, + /* 240 */ 'a', '3', 0, + /* 243 */ 'a', 'c', '3', 0, + /* 247 */ 'f', 'c', 'c', '3', 0, + /* 252 */ 'f', '3', 0, + /* 255 */ 's', '3', 0, + /* 258 */ 't', '3', 0, + /* 261 */ 'w', '3', 0, + /* 264 */ 'f', '1', '4', 0, + /* 268 */ 'w', '1', '4', 0, + /* 272 */ 'f', '2', '4', 0, + /* 276 */ 'w', '2', '4', 0, + /* 280 */ 'f', 'c', 'c', '4', 0, + /* 285 */ 'f', '4', 0, + /* 288 */ 's', '4', 0, + /* 291 */ 't', '4', 0, + /* 294 */ 'w', '4', 0, + /* 297 */ 'f', '1', '5', 0, + /* 301 */ 'w', '1', '5', 0, + /* 305 */ 'f', '2', '5', 0, + /* 309 */ 'w', '2', '5', 0, + /* 313 */ 'f', 'c', 'c', '5', 0, + /* 318 */ 'f', '5', 0, + /* 321 */ 's', '5', 0, + /* 324 */ 't', '5', 0, + /* 327 */ 'w', '5', 0, + /* 330 */ 'f', '1', '6', 0, + /* 334 */ 'w', '1', '6', 0, + /* 338 */ 'f', '2', '6', 0, + /* 342 */ 'w', '2', '6', 0, + /* 346 */ 'f', 'c', 'c', '6', 0, + /* 351 */ 'f', '6', 0, + /* 354 */ 's', '6', 0, + /* 357 */ 't', '6', 0, + /* 360 */ 'w', '6', 0, + /* 363 */ 'f', '1', '7', 0, + /* 367 */ 'w', '1', '7', 0, + /* 371 */ 'f', '2', '7', 0, + /* 375 */ 'w', '2', '7', 0, + /* 379 */ 'f', 'c', 'c', '7', 0, + /* 384 */ 'f', '7', 0, + /* 387 */ 's', '7', 0, + /* 390 */ 't', '7', 0, + /* 393 */ 'w', '7', 0, + /* 396 */ 'f', '1', '8', 0, + /* 400 */ 'w', '1', '8', 0, + /* 404 */ 'f', '2', '8', 0, + /* 408 */ 'w', '2', '8', 0, + /* 412 */ 'f', '8', 0, + /* 415 */ 't', '8', 0, + /* 418 */ 'w', '8', 0, + /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', + '6', '_', '1', '9', 0, + /* 437 */ 'f', '1', '9', 0, + /* 441 */ 'w', '1', '9', 0, + /* 445 */ 'f', '2', '9', 0, + /* 449 */ 'w', '2', '9', 0, + /* 453 */ 'f', '9', 0, + /* 456 */ 't', '9', 0, + /* 459 */ 'w', '9', 0, + /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, + /* 469 */ 'r', 'a', 0, + /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0, + /* 479 */ 'p', 'c', 0, + /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, + /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, + /* 502 */ 'h', 'i', 0, + /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0, + /* 516 */ 'l', 'o', 0, + /* 519 */ 'z', 'e', 'r', 'o', 0, + /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', + 't', 'e', 'p', 0, + /* 539 */ 'f', 'p', 0, + /* 542 */ 'g', 'p', 0, + /* 545 */ 's', 'p', 0, + /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0, + /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0, + /* 565 */ 'a', 't', 0, + /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, + /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, }; static const uint16_t RegAsmOffset[] = { - 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266, - 299, 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182, - 243, 565, 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, - 266, 299, 332, 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, - 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, - 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 1, 76, 151, 212, - 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, - 405, 446, 30, 105, 49, 191, 285, 351, 412, 0, 150, 264, 330, 396, - 8, 158, 272, 338, 404, 29, 12, 87, 162, 223, 49, 124, 191, 252, - 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, - 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, - 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, 213, 266, 299, - 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, - 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, 49, - 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, - 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, - 445, 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299, - 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, - 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, - 40, 115, 182, 243, 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, - 255, 288, 321, 354, 387, 545, 66, 141, 205, 258, 291, 324, 357, 390, - 415, 456, 69, 144, 72, 147, 208, 261, 294, 327, 360, 393, 418, 459, - 4, 79, 154, 215, 268, 301, 334, 367, 400, 441, 25, 100, 175, 236, - 276, 309, 342, 375, 408, 449, 33, 108, 519, 37, 112, 179, 240, 40, - 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, - 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, - 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, 202, 255, 288, - 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, - 144, + 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266, 299, + 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182, 243, 565, + 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, 266, 299, 332, + 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, 398, 435, 1, 76, + 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, + 372, 405, 446, 30, 105, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, + 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 49, 191, 285, + 351, 412, 0, 150, 264, 330, 396, 8, 158, 272, 338, 404, 29, 12, 87, + 162, 223, 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, + 211, 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, + 404, 445, 29, 104, 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, + 213, 266, 299, 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, + 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, + 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, + 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, + 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299, 332, 365, + 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, 159, + 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, 40, 115, 182, 243, + 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, 255, 288, 321, 354, 387, + 545, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, 144, 72, 147, + 208, 261, 294, 327, 360, 393, 418, 459, 4, 79, 154, 215, 268, 301, 334, + 367, 400, 441, 25, 100, 175, 236, 276, 309, 342, 375, 408, 449, 33, 108, + 519, 37, 112, 179, 240, 40, 49, 124, 191, 252, 285, 318, 351, 384, 412, + 453, 0, 75, 150, 211, 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, + 272, 305, 338, 371, 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, + 202, 255, 288, 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, + 456, 69, 144, }; - //printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]); - //int i; - //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) + // printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]); + // int i; + // for (i = 0; i < sizeof(RegAsmOffset)/2; i++) // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); - //printf("-------------------------\n"); - return AsmStrs+RegAsmOffset[RegNo-1]; + // printf("-------------------------\n"); + return AsmStrs + RegAsmOffset[RegNo - 1]; #else return NULL; #endif @@ -5282,19 +13668,19 @@ static const char *getRegisterName(unsigned RegNo) #undef PRINT_ALIAS_INSTR static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, SStream *OS) -{ -} + unsigned PrintMethodIdx, SStream *OS) {} -static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) -{ - #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) { +#define GETREGCLASS_CONTAIN(_class, _reg) \ + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), \ + MCOperand_getReg(MCInst_getOperand(MI, _reg))) const char *AsmString; char *tmp, *AsmMnem, *AsmOps, *c; int OpIdx, PrintMethodIdx; MCRegisterInfo *MRI = (MCRegisterInfo *)info; switch (MCInst_getOpcode(MI)) { - default: return NULL; + default: + return NULL; case Mips_ADDu: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && @@ -5693,7 +14079,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) tmp = cs_strdup(AsmString); AsmMnem = tmp; - for(AsmOps = tmp; *AsmOps; AsmOps++) { + for (AsmOps = tmp; *AsmOps; AsmOps++) { if (*AsmOps == ' ' || *AsmOps == '\t') { *AsmOps = '\0'; AsmOps++; diff --git a/arch/Mips/MipsGenDisassemblerTables.inc b/arch/Mips/MipsGenDisassemblerTables.inc index e926f77884..5e2fa8d6c5 100644 --- a/arch/Mips/MipsGenDisassemblerTables.inc +++ b/arch/Mips/MipsGenDisassemblerTables.inc @@ -1,6942 +1,64980 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * Mips Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* By Phosphorus15 , Year 2021 */ +/* This generator is under https://github.com/rizinorg/llvm-capstone */ +/* Automatically generated file, do not edit! */ -#include "../../MCInst.h" #include "../../LEB128.h" +#include "../../MCInst.h" + +#define Mips_FeatureAbs2008 0ULL +#define Mips_FeatureCRC 1ULL +#define Mips_FeatureCnMips 2ULL +#define Mips_FeatureCnMipsP 3ULL +#define Mips_FeatureDSP 4ULL +#define Mips_FeatureDSPR2 5ULL +#define Mips_FeatureDSPR3 6ULL +#define Mips_FeatureEVA 7ULL +#define Mips_FeatureFP64Bit 8ULL +#define Mips_FeatureFPXX 9ULL +#define Mips_FeatureGINV 10ULL +#define Mips_FeatureGP64Bit 11ULL +#define Mips_FeatureLongCalls 12ULL +#define Mips_FeatureMSA 13ULL +#define Mips_FeatureMT 14ULL +#define Mips_FeatureMicroMips 15ULL +#define Mips_FeatureMips1 16ULL +#define Mips_FeatureMips2 17ULL +#define Mips_FeatureMips3 18ULL +#define Mips_FeatureMips3D 19ULL +#define Mips_FeatureMips3_32 20ULL +#define Mips_FeatureMips3_32r2 21ULL +#define Mips_FeatureMips4 22ULL +#define Mips_FeatureMips4_32 23ULL +#define Mips_FeatureMips4_32r2 24ULL +#define Mips_FeatureMips5 25ULL +#define Mips_FeatureMips5_32r2 26ULL +#define Mips_FeatureMips16 27ULL +#define Mips_FeatureMips32 28ULL +#define Mips_FeatureMips32r2 29ULL +#define Mips_FeatureMips32r3 30ULL +#define Mips_FeatureMips32r5 31ULL +#define Mips_FeatureMips32r6 32ULL +#define Mips_FeatureMips64 33ULL +#define Mips_FeatureMips64r2 34ULL +#define Mips_FeatureMips64r3 35ULL +#define Mips_FeatureMips64r5 36ULL +#define Mips_FeatureMips64r6 37ULL +#define Mips_FeatureNaN2008 38ULL +#define Mips_FeatureNoABICalls 39ULL +#define Mips_FeatureNoMadd4 40ULL +#define Mips_FeatureNoOddSPReg 41ULL +#define Mips_FeaturePTR64Bit 42ULL +#define Mips_FeatureSingleFloat 43ULL +#define Mips_FeatureSoftFloat 44ULL +#define Mips_FeatureSym32 45ULL +#define Mips_FeatureUseIndirectJumpsHazard 46ULL +#define Mips_FeatureUseTCCInDIV 47ULL +#define Mips_FeatureVFPU 48ULL +#define Mips_FeatureVirt 49ULL +#define Mips_FeatureXGOT 50ULL +#define Mips_ImplP5600 51ULL +#ifdef MIPS_GET_DISASSEMBLER +#undef MIPS_GET_DISASSEMBLER // Helper function for extracting fields from encoded instructions. -#define FieldFromInstruction(fname, InsnType) \ -static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ -{ \ - InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ - fieldMask = (InsnType)(-1LL); \ - else \ - fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ - return (insn & fieldMask) >> startBit; \ -} +#define FieldFromInstruction(fname, InsnType) \ + static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ + } + +static const uint8_t DecoderTable16[] = { + /* 0 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 17 + /* 8 */ MCD_OPC_CheckPredicate, + 0, + 71, + 2, + 0, // Skip to: 596 + /* 13 */ MCD_OPC_Decode, + 140, + 8, + 0, // Opcode: Bimm16 + /* 17 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 31 + /* 22 */ MCD_OPC_CheckPredicate, + 0, + 57, + 2, + 0, // Skip to: 596 + /* 27 */ MCD_OPC_Decode, + 138, + 8, + 1, // Opcode: BeqzRxImm16 + /* 31 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 45 + /* 36 */ MCD_OPC_CheckPredicate, + 0, + 43, + 2, + 0, // Skip to: 596 + /* 41 */ MCD_OPC_Decode, + 142, + 8, + 1, // Opcode: BnezRxImm16 + /* 45 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 59 + /* 50 */ MCD_OPC_CheckPredicate, + 0, + 29, + 2, + 0, // Skip to: 596 + /* 55 */ MCD_OPC_Decode, + 191, + 6, + 2, // Opcode: AddiuRxRxImm16 + /* 59 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 73 + /* 64 */ MCD_OPC_CheckPredicate, + 0, + 15, + 2, + 0, // Skip to: 596 + /* 69 */ MCD_OPC_Decode, + 184, + 21, + 1, // Opcode: SltiRxImm16 + /* 73 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 87 + /* 78 */ MCD_OPC_CheckPredicate, + 0, + 1, + 2, + 0, // Skip to: 596 + /* 83 */ MCD_OPC_Decode, + 186, + 21, + 1, // Opcode: SltiuRxImm16 + /* 87 */ MCD_OPC_FilterValue, + 12, + 73, + 0, + 0, // Skip to: 165 + /* 92 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 95 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 109 + /* 100 */ MCD_OPC_CheckPredicate, + 0, + 235, + 1, + 0, // Skip to: 596 + /* 105 */ MCD_OPC_Decode, + 145, + 8, + 0, // Opcode: Bteqz16 + /* 109 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 123 + /* 114 */ MCD_OPC_CheckPredicate, + 0, + 221, + 1, + 0, // Skip to: 596 + /* 119 */ MCD_OPC_Decode, + 147, + 8, + 0, // Opcode: Btnez16 + /* 123 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 137 + /* 128 */ MCD_OPC_CheckPredicate, + 0, + 207, + 1, + 0, // Skip to: 596 + /* 133 */ MCD_OPC_Decode, + 194, + 6, + 0, // Opcode: AddiuSpImm16 + /* 137 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 151 + /* 142 */ MCD_OPC_CheckPredicate, + 0, + 193, + 1, + 0, // Skip to: 596 + /* 147 */ MCD_OPC_Decode, + 190, + 17, + 3, // Opcode: Move32R16 + /* 151 */ MCD_OPC_FilterValue, + 7, + 184, + 1, + 0, // Skip to: 596 + /* 156 */ MCD_OPC_CheckPredicate, + 0, + 179, + 1, + 0, // Skip to: 596 + /* 161 */ MCD_OPC_Decode, + 191, + 17, + 4, // Opcode: MoveR3216 + /* 165 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 179 + /* 170 */ MCD_OPC_CheckPredicate, + 0, + 165, + 1, + 0, // Skip to: 596 + /* 175 */ MCD_OPC_Decode, + 144, + 15, + 1, // Opcode: LiRxImm16 + /* 179 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 193 + /* 184 */ MCD_OPC_CheckPredicate, + 0, + 151, + 1, + 0, // Skip to: 596 + /* 189 */ MCD_OPC_Decode, + 211, + 10, + 1, // Opcode: CmpiRxImm16 + /* 193 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 207 + /* 198 */ MCD_OPC_CheckPredicate, + 0, + 137, + 1, + 0, // Skip to: 596 + /* 203 */ MCD_OPC_Decode, + 147, + 15, + 1, // Opcode: LwRxPcTcp16 + /* 207 */ MCD_OPC_FilterValue, + 28, + 31, + 0, + 0, // Skip to: 243 + /* 212 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 215 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 229 + /* 220 */ MCD_OPC_CheckPredicate, + 0, + 115, + 1, + 0, // Skip to: 596 + /* 225 */ MCD_OPC_Decode, + 196, + 6, + 5, // Opcode: AdduRxRyRz16 + /* 229 */ MCD_OPC_FilterValue, + 3, + 106, + 1, + 0, // Skip to: 596 + /* 234 */ MCD_OPC_CheckPredicate, + 0, + 101, + 1, + 0, // Skip to: 596 + /* 239 */ MCD_OPC_Decode, + 193, + 21, + 5, // Opcode: SubuRxRyRz16 + /* 243 */ MCD_OPC_FilterValue, + 29, + 92, + 1, + 0, // Skip to: 596 + /* 248 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 251 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 329 + /* 256 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 259 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 273 + /* 264 */ MCD_OPC_CheckPredicate, + 0, + 71, + 1, + 0, // Skip to: 596 + /* 269 */ MCD_OPC_Decode, + 151, + 14, + 0, // Opcode: JumpLinkReg16 + /* 273 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 294 + /* 278 */ MCD_OPC_CheckPredicate, + 0, + 57, + 1, + 0, // Skip to: 596 + /* 283 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 50, + 1, + 0, // Skip to: 596 + /* 290 */ MCD_OPC_Decode, + 148, + 14, + 0, // Opcode: JrRa16 + /* 294 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 308 + /* 299 */ MCD_OPC_CheckPredicate, + 0, + 36, + 1, + 0, // Skip to: 596 + /* 304 */ MCD_OPC_Decode, + 150, + 14, + 1, // Opcode: JrcRx16 + /* 308 */ MCD_OPC_FilterValue, + 7, + 27, + 1, + 0, // Skip to: 596 + /* 313 */ MCD_OPC_CheckPredicate, + 0, + 22, + 1, + 0, // Skip to: 596 + /* 318 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 15, + 1, + 0, // Skip to: 596 + /* 325 */ MCD_OPC_Decode, + 149, + 14, + 0, // Opcode: JrcRa16 + /* 329 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 343 + /* 334 */ MCD_OPC_CheckPredicate, + 0, + 1, + 1, + 0, // Skip to: 596 + /* 339 */ MCD_OPC_Decode, + 183, + 21, + 6, // Opcode: SltRxRy16 + /* 343 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 357 + /* 348 */ MCD_OPC_CheckPredicate, + 0, + 243, + 0, + 0, // Skip to: 596 + /* 353 */ MCD_OPC_Decode, + 188, + 21, + 6, // Opcode: SltuRxRy16 + /* 357 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 371 + /* 362 */ MCD_OPC_CheckPredicate, + 0, + 229, + 0, + 0, // Skip to: 596 + /* 367 */ MCD_OPC_Decode, + 182, + 21, + 7, // Opcode: SllvRxRy16 + /* 371 */ MCD_OPC_FilterValue, + 5, + 16, + 0, + 0, // Skip to: 392 + /* 376 */ MCD_OPC_CheckPredicate, + 0, + 215, + 0, + 0, // Skip to: 596 + /* 381 */ MCD_OPC_CheckField, + 5, + 6, + 0, + 208, + 0, + 0, // Skip to: 596 + /* 388 */ MCD_OPC_Decode, + 144, + 8, + 0, // Opcode: Break16 + /* 392 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 406 + /* 397 */ MCD_OPC_CheckPredicate, + 0, + 194, + 0, + 0, // Skip to: 596 + /* 402 */ MCD_OPC_Decode, + 192, + 21, + 7, // Opcode: SrlvRxRy16 + /* 406 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 420 + /* 411 */ MCD_OPC_CheckPredicate, + 0, + 180, + 0, + 0, // Skip to: 596 + /* 416 */ MCD_OPC_Decode, + 190, + 21, + 7, // Opcode: SravRxRy16 + /* 420 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 434 + /* 425 */ MCD_OPC_CheckPredicate, + 0, + 166, + 0, + 0, // Skip to: 596 + /* 430 */ MCD_OPC_Decode, + 210, + 10, + 6, // Opcode: CmpRxRy16 + /* 434 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 448 + /* 439 */ MCD_OPC_CheckPredicate, + 0, + 152, + 0, + 0, // Skip to: 596 + /* 444 */ MCD_OPC_Decode, + 197, + 6, + 7, // Opcode: AndRxRxRy16 + /* 448 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 462 + /* 453 */ MCD_OPC_CheckPredicate, + 0, + 138, + 0, + 0, // Skip to: 596 + /* 458 */ MCD_OPC_Decode, + 232, + 17, + 7, // Opcode: OrRxRxRy16 + /* 462 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 476 + /* 467 */ MCD_OPC_CheckPredicate, + 0, + 124, + 0, + 0, // Skip to: 596 + /* 472 */ MCD_OPC_Decode, + 157, + 22, + 7, // Opcode: XorRxRxRy16 + /* 476 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 490 + /* 481 */ MCD_OPC_CheckPredicate, + 0, + 110, + 0, + 0, // Skip to: 596 + /* 486 */ MCD_OPC_Decode, + 219, + 17, + 6, // Opcode: NotRxRy16 + /* 490 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 504 + /* 495 */ MCD_OPC_CheckPredicate, + 0, + 96, + 0, + 0, // Skip to: 596 + /* 500 */ MCD_OPC_Decode, + 188, + 17, + 1, // Opcode: Mfhi16 + /* 504 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 540 + /* 509 */ MCD_OPC_ExtractField, + 5, + 3, // Inst{7-5} ... + /* 512 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 526 + /* 517 */ MCD_OPC_CheckPredicate, + 0, + 74, + 0, + 0, // Skip to: 596 + /* 522 */ MCD_OPC_Decode, + 178, + 21, + 2, // Opcode: SebRx16 + /* 526 */ MCD_OPC_FilterValue, + 5, + 65, + 0, + 0, // Skip to: 596 + /* 531 */ MCD_OPC_CheckPredicate, + 0, + 60, + 0, + 0, // Skip to: 596 + /* 536 */ MCD_OPC_Decode, + 179, + 21, + 2, // Opcode: SehRx16 + /* 540 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 554 + /* 545 */ MCD_OPC_CheckPredicate, + 0, + 46, + 0, + 0, // Skip to: 596 + /* 550 */ MCD_OPC_Decode, + 189, + 17, + 1, // Opcode: Mflo16 + /* 554 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 568 + /* 559 */ MCD_OPC_CheckPredicate, + 0, + 32, + 0, + 0, // Skip to: 596 + /* 564 */ MCD_OPC_Decode, + 220, + 11, + 6, // Opcode: DivRxRy16 + /* 568 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 582 + /* 573 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 596 + /* 578 */ MCD_OPC_Decode, + 221, + 11, + 6, // Opcode: DivuRxRy16 + /* 582 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 596 + /* 587 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 596 + /* 592 */ MCD_OPC_Decode, + 218, + 17, + 6, // Opcode: NegRxRy16 + /* 596 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTable32[] = { + /* 0 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3 */ MCD_OPC_FilterValue, + 1, + 23, + 0, + 0, // Skip to: 31 + /* 8 */ MCD_OPC_CheckPredicate, + 0, + 2, + 2, + 0, // Skip to: 527 + /* 13 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 251, + 1, + 0, // Skip to: 527 + /* 20 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 244, + 1, + 0, // Skip to: 527 + /* 27 */ MCD_OPC_Decode, + 190, + 6, + 1, // Opcode: AddiuRxPcImmX16 + /* 31 */ MCD_OPC_FilterValue, + 2, + 23, + 0, + 0, // Skip to: 59 + /* 36 */ MCD_OPC_CheckPredicate, + 0, + 230, + 1, + 0, // Skip to: 527 + /* 41 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 223, + 1, + 0, // Skip to: 527 + /* 48 */ MCD_OPC_CheckField, + 5, + 6, + 0, + 216, + 1, + 0, // Skip to: 527 + /* 55 */ MCD_OPC_Decode, + 141, + 8, + 8, // Opcode: BimmX16 + /* 59 */ MCD_OPC_FilterValue, + 4, + 23, + 0, + 0, // Skip to: 87 + /* 64 */ MCD_OPC_CheckPredicate, + 0, + 202, + 1, + 0, // Skip to: 527 + /* 69 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 195, + 1, + 0, // Skip to: 527 + /* 76 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 188, + 1, + 0, // Skip to: 527 + /* 83 */ MCD_OPC_Decode, + 139, + 8, + 1, // Opcode: BeqzRxImmX16 + /* 87 */ MCD_OPC_FilterValue, + 5, + 23, + 0, + 0, // Skip to: 115 + /* 92 */ MCD_OPC_CheckPredicate, + 0, + 174, + 1, + 0, // Skip to: 527 + /* 97 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 167, + 1, + 0, // Skip to: 527 + /* 104 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 160, + 1, + 0, // Skip to: 527 + /* 111 */ MCD_OPC_Decode, + 143, + 8, + 1, // Opcode: BnezRxImmX16 + /* 115 */ MCD_OPC_FilterValue, + 6, + 106, + 0, + 0, // Skip to: 226 + /* 120 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 123 */ MCD_OPC_FilterValue, + 30, + 143, + 1, + 0, // Skip to: 527 + /* 128 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 131 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 181 + /* 136 */ MCD_OPC_ExtractField, + 0, + 5, // Inst{4-0} ... + /* 139 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 153 + /* 144 */ MCD_OPC_CheckPredicate, + 0, + 32, + 0, + 0, // Skip to: 181 + /* 149 */ MCD_OPC_Decode, + 181, + 21, + 6, // Opcode: SllX16 + /* 153 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 167 + /* 158 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 181 + /* 163 */ MCD_OPC_Decode, + 191, + 21, + 6, // Opcode: SrlX16 + /* 167 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 181 + /* 172 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 181 + /* 177 */ MCD_OPC_Decode, + 189, + 21, + 6, // Opcode: SraX16 + /* 181 */ MCD_OPC_ExtractField, + 5, + 6, // Inst{10-5} ... + /* 184 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 198 + /* 189 */ MCD_OPC_CheckPredicate, + 0, + 77, + 1, + 0, // Skip to: 527 + /* 194 */ MCD_OPC_Decode, + 146, + 8, + 0, // Opcode: BteqzX16 + /* 198 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 212 + /* 203 */ MCD_OPC_CheckPredicate, + 0, + 63, + 1, + 0, // Skip to: 527 + /* 208 */ MCD_OPC_Decode, + 148, + 8, + 0, // Opcode: BtnezX16 + /* 212 */ MCD_OPC_FilterValue, + 24, + 54, + 1, + 0, // Skip to: 527 + /* 217 */ MCD_OPC_CheckPredicate, + 0, + 49, + 1, + 0, // Skip to: 527 + /* 222 */ MCD_OPC_Decode, + 195, + 6, + 0, // Opcode: AddiuSpImmX16 + /* 226 */ MCD_OPC_FilterValue, + 8, + 23, + 0, + 0, // Skip to: 254 + /* 231 */ MCD_OPC_CheckPredicate, + 0, + 35, + 1, + 0, // Skip to: 527 + /* 236 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 28, + 1, + 0, // Skip to: 527 + /* 243 */ MCD_OPC_CheckField, + 4, + 1, + 0, + 21, + 1, + 0, // Skip to: 527 + /* 250 */ MCD_OPC_Decode, + 193, + 6, + 9, // Opcode: AddiuRxRyOffMemX16 + /* 254 */ MCD_OPC_FilterValue, + 9, + 23, + 0, + 0, // Skip to: 282 + /* 259 */ MCD_OPC_CheckPredicate, + 0, + 7, + 1, + 0, // Skip to: 527 + /* 264 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 0, + 1, + 0, // Skip to: 527 + /* 271 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 249, + 0, + 0, // Skip to: 527 + /* 278 */ MCD_OPC_Decode, + 189, + 6, + 1, // Opcode: AddiuRxImmX16 + /* 282 */ MCD_OPC_FilterValue, + 10, + 23, + 0, + 0, // Skip to: 310 + /* 287 */ MCD_OPC_CheckPredicate, + 0, + 235, + 0, + 0, // Skip to: 527 + /* 292 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 228, + 0, + 0, // Skip to: 527 + /* 299 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 221, + 0, + 0, // Skip to: 527 + /* 306 */ MCD_OPC_Decode, + 185, + 21, + 1, // Opcode: SltiRxImmX16 + /* 310 */ MCD_OPC_FilterValue, + 11, + 23, + 0, + 0, // Skip to: 338 + /* 315 */ MCD_OPC_CheckPredicate, + 0, + 207, + 0, + 0, // Skip to: 527 + /* 320 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 200, + 0, + 0, // Skip to: 527 + /* 327 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 193, + 0, + 0, // Skip to: 527 + /* 334 */ MCD_OPC_Decode, + 187, + 21, + 1, // Opcode: SltiuRxImmX16 + /* 338 */ MCD_OPC_FilterValue, + 13, + 23, + 0, + 0, // Skip to: 366 + /* 343 */ MCD_OPC_CheckPredicate, + 0, + 179, + 0, + 0, // Skip to: 527 + /* 348 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 172, + 0, + 0, // Skip to: 527 + /* 355 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 165, + 0, + 0, // Skip to: 527 + /* 362 */ MCD_OPC_Decode, + 146, + 15, + 1, // Opcode: LiRxImmX16 + /* 366 */ MCD_OPC_FilterValue, + 14, + 23, + 0, + 0, // Skip to: 394 + /* 371 */ MCD_OPC_CheckPredicate, + 0, + 151, + 0, + 0, // Skip to: 527 + /* 376 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 144, + 0, + 0, // Skip to: 527 + /* 383 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 137, + 0, + 0, // Skip to: 527 + /* 390 */ MCD_OPC_Decode, + 212, + 10, + 1, // Opcode: CmpiRxImmX16 + /* 394 */ MCD_OPC_FilterValue, + 18, + 16, + 0, + 0, // Skip to: 415 + /* 399 */ MCD_OPC_CheckPredicate, + 0, + 123, + 0, + 0, // Skip to: 527 + /* 404 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 116, + 0, + 0, // Skip to: 527 + /* 411 */ MCD_OPC_Decode, + 150, + 15, + 9, // Opcode: LwRxSpImmX16 + /* 415 */ MCD_OPC_FilterValue, + 22, + 23, + 0, + 0, // Skip to: 443 + /* 420 */ MCD_OPC_CheckPredicate, + 0, + 102, + 0, + 0, // Skip to: 527 + /* 425 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 95, + 0, + 0, // Skip to: 527 + /* 432 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 88, + 0, + 0, // Skip to: 527 + /* 439 */ MCD_OPC_Decode, + 148, + 15, + 1, // Opcode: LwRxPcTcpX16 + /* 443 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 464 + /* 448 */ MCD_OPC_CheckPredicate, + 0, + 74, + 0, + 0, // Skip to: 527 + /* 453 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 67, + 0, + 0, // Skip to: 527 + /* 460 */ MCD_OPC_Decode, + 177, + 21, + 9, // Opcode: SbRxRyOffMemX16 + /* 464 */ MCD_OPC_FilterValue, + 25, + 16, + 0, + 0, // Skip to: 485 + /* 469 */ MCD_OPC_CheckPredicate, + 0, + 53, + 0, + 0, // Skip to: 527 + /* 474 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 46, + 0, + 0, // Skip to: 527 + /* 481 */ MCD_OPC_Decode, + 180, + 21, + 9, // Opcode: ShRxRyOffMemX16 + /* 485 */ MCD_OPC_FilterValue, + 26, + 16, + 0, + 0, // Skip to: 506 + /* 490 */ MCD_OPC_CheckPredicate, + 0, + 32, + 0, + 0, // Skip to: 527 + /* 495 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 25, + 0, + 0, // Skip to: 527 + /* 502 */ MCD_OPC_Decode, + 195, + 21, + 9, // Opcode: SwRxSpImmX16 + /* 506 */ MCD_OPC_FilterValue, + 27, + 16, + 0, + 0, // Skip to: 527 + /* 511 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 527 + /* 516 */ MCD_OPC_CheckField, + 27, + 5, + 30, + 4, + 0, + 0, // Skip to: 527 + /* 523 */ MCD_OPC_Decode, + 194, + 21, + 9, // Opcode: SwRxRyOffMemX16 + /* 527 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableCOP3_32[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15 -/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51 -/* 11 */ MCD_OPC_Decode, 220, 7, 10, // Opcode: LWC3 -/* 15 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 27 -/* 19 */ MCD_OPC_CheckPredicate, 2, 28, 0, // Skip to: 51 -/* 23 */ MCD_OPC_Decode, 167, 7, 10, // Opcode: LDC3 -/* 27 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 39 -/* 31 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 51 -/* 35 */ MCD_OPC_Decode, 242, 12, 10, // Opcode: SWC3 -/* 39 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 51 -/* 43 */ MCD_OPC_CheckPredicate, 2, 4, 0, // Skip to: 51 -/* 47 */ MCD_OPC_Decode, 161, 11, 10, // Opcode: SDC3 -/* 51 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, 51, 9, 0, 0, // Skip to: 17 + /* 8 */ MCD_OPC_CheckPredicate, 1, 46, 0, 0, // Skip to: 59 + /* 13 */ MCD_OPC_Decode, 235, 14, 10, // Opcode: LWC3 + /* 17 */ MCD_OPC_FilterValue, 55, 9, 0, 0, // Skip to: 31 + /* 22 */ MCD_OPC_CheckPredicate, 2, 32, 0, 0, // Skip to: 59 + /* 27 */ MCD_OPC_Decode, 175, 14, 10, // Opcode: LDC3 + /* 31 */ MCD_OPC_FilterValue, 59, 9, 0, 0, // Skip to: 45 + /* 36 */ MCD_OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 59 + /* 41 */ MCD_OPC_Decode, 142, 21, 10, // Opcode: SWC3 + /* 45 */ MCD_OPC_FilterValue, 63, 9, 0, 0, // Skip to: 59 + /* 50 */ MCD_OPC_CheckPredicate, 2, 4, 0, 0, // Skip to: 59 + /* 55 */ MCD_OPC_Decode, 138, 19, 10, // Opcode: SDC3 + /* 59 */ MCD_OPC_Fail, 0}; + +static const uint8_t DecoderTableCnMips32[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 18, + 31, + 0, + 0, // Skip to: 39 + /* 8 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 11 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 25 + /* 16 */ MCD_OPC_CheckPredicate, + 3, + 239, + 1, + 0, // Skip to: 516 + /* 21 */ MCD_OPC_Decode, + 130, + 11, + 11, // Opcode: DMFC2_OCTEON + /* 25 */ MCD_OPC_FilterValue, + 5, + 230, + 1, + 0, // Skip to: 516 + /* 30 */ MCD_OPC_CheckPredicate, + 3, + 225, + 1, + 0, // Skip to: 516 + /* 35 */ MCD_OPC_Decode, + 138, + 11, + 11, // Opcode: DMTC2_OCTEON + /* 39 */ MCD_OPC_FilterValue, + 28, + 160, + 1, + 0, // Skip to: 460 + /* 44 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 47 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 68 + /* 52 */ MCD_OPC_CheckPredicate, + 3, + 203, + 1, + 0, // Skip to: 516 + /* 57 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 196, + 1, + 0, // Skip to: 516 + /* 64 */ MCD_OPC_Decode, + 142, + 11, + 12, // Opcode: DMUL + /* 68 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 89 + /* 73 */ MCD_OPC_CheckPredicate, + 3, + 182, + 1, + 0, // Skip to: 516 + /* 78 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 175, + 1, + 0, // Skip to: 516 + /* 85 */ MCD_OPC_Decode, + 130, + 17, + 13, // Opcode: MTM0 + /* 89 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 110 + /* 94 */ MCD_OPC_CheckPredicate, + 3, + 161, + 1, + 0, // Skip to: 516 + /* 99 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 154, + 1, + 0, // Skip to: 516 + /* 106 */ MCD_OPC_Decode, + 133, + 17, + 13, // Opcode: MTP0 + /* 110 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 131 + /* 115 */ MCD_OPC_CheckPredicate, + 3, + 140, + 1, + 0, // Skip to: 516 + /* 120 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 133, + 1, + 0, // Skip to: 516 + /* 127 */ MCD_OPC_Decode, + 134, + 17, + 13, // Opcode: MTP1 + /* 131 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 152 + /* 136 */ MCD_OPC_CheckPredicate, + 3, + 119, + 1, + 0, // Skip to: 516 + /* 141 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 112, + 1, + 0, // Skip to: 516 + /* 148 */ MCD_OPC_Decode, + 135, + 17, + 13, // Opcode: MTP2 + /* 152 */ MCD_OPC_FilterValue, + 12, + 16, + 0, + 0, // Skip to: 173 + /* 157 */ MCD_OPC_CheckPredicate, + 3, + 98, + 1, + 0, // Skip to: 516 + /* 162 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 91, + 1, + 0, // Skip to: 516 + /* 169 */ MCD_OPC_Decode, + 131, + 17, + 13, // Opcode: MTM1 + /* 173 */ MCD_OPC_FilterValue, + 13, + 16, + 0, + 0, // Skip to: 194 + /* 178 */ MCD_OPC_CheckPredicate, + 3, + 77, + 1, + 0, // Skip to: 516 + /* 183 */ MCD_OPC_CheckField, + 6, + 15, + 0, + 70, + 1, + 0, // Skip to: 516 + /* 190 */ MCD_OPC_Decode, + 132, + 17, + 13, // Opcode: MTM2 + /* 194 */ MCD_OPC_FilterValue, + 15, + 16, + 0, + 0, // Skip to: 215 + /* 199 */ MCD_OPC_CheckPredicate, + 3, + 56, + 1, + 0, // Skip to: 516 + /* 204 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 49, + 1, + 0, // Skip to: 516 + /* 211 */ MCD_OPC_Decode, + 131, + 22, + 12, // Opcode: VMULU + /* 215 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 236 + /* 220 */ MCD_OPC_CheckPredicate, + 3, + 35, + 1, + 0, // Skip to: 516 + /* 225 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 28, + 1, + 0, // Skip to: 516 + /* 232 */ MCD_OPC_Decode, + 130, + 22, + 12, // Opcode: VMM0 + /* 236 */ MCD_OPC_FilterValue, + 17, + 16, + 0, + 0, // Skip to: 257 + /* 241 */ MCD_OPC_CheckPredicate, + 3, + 14, + 1, + 0, // Skip to: 516 + /* 246 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 7, + 1, + 0, // Skip to: 516 + /* 253 */ MCD_OPC_Decode, + 129, + 22, + 12, // Opcode: V3MULU + /* 257 */ MCD_OPC_FilterValue, + 40, + 16, + 0, + 0, // Skip to: 278 + /* 262 */ MCD_OPC_CheckPredicate, + 3, + 249, + 0, + 0, // Skip to: 516 + /* 267 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 242, + 0, + 0, // Skip to: 516 + /* 274 */ MCD_OPC_Decode, + 199, + 6, + 12, // Opcode: BADDu + /* 278 */ MCD_OPC_FilterValue, + 42, + 16, + 0, + 0, // Skip to: 299 + /* 283 */ MCD_OPC_CheckPredicate, + 3, + 228, + 0, + 0, // Skip to: 516 + /* 288 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 221, + 0, + 0, // Skip to: 516 + /* 295 */ MCD_OPC_Decode, + 169, + 19, + 12, // Opcode: SEQ + /* 299 */ MCD_OPC_FilterValue, + 43, + 16, + 0, + 0, // Skip to: 320 + /* 304 */ MCD_OPC_CheckPredicate, + 3, + 207, + 0, + 0, // Skip to: 516 + /* 309 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 200, + 0, + 0, // Skip to: 516 + /* 316 */ MCD_OPC_Decode, + 141, + 20, + 12, // Opcode: SNE + /* 320 */ MCD_OPC_FilterValue, + 44, + 23, + 0, + 0, // Skip to: 348 + /* 325 */ MCD_OPC_CheckPredicate, + 3, + 186, + 0, + 0, // Skip to: 516 + /* 330 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 179, + 0, + 0, // Skip to: 516 + /* 337 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 172, + 0, + 0, // Skip to: 516 + /* 344 */ MCD_OPC_Decode, + 128, + 18, + 14, // Opcode: POP + /* 348 */ MCD_OPC_FilterValue, + 45, + 23, + 0, + 0, // Skip to: 376 + /* 353 */ MCD_OPC_CheckPredicate, + 3, + 158, + 0, + 0, // Skip to: 516 + /* 358 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 151, + 0, + 0, // Skip to: 516 + /* 365 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 144, + 0, + 0, // Skip to: 516 + /* 372 */ MCD_OPC_Decode, + 175, + 11, + 15, // Opcode: DPOP + /* 376 */ MCD_OPC_FilterValue, + 46, + 9, + 0, + 0, // Skip to: 390 + /* 381 */ MCD_OPC_CheckPredicate, + 3, + 130, + 0, + 0, // Skip to: 516 + /* 386 */ MCD_OPC_Decode, + 170, + 19, + 16, // Opcode: SEQi + /* 390 */ MCD_OPC_FilterValue, + 47, + 9, + 0, + 0, // Skip to: 404 + /* 395 */ MCD_OPC_CheckPredicate, + 3, + 116, + 0, + 0, // Skip to: 516 + /* 400 */ MCD_OPC_Decode, + 142, + 20, + 16, // Opcode: SNEi + /* 404 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 418 + /* 409 */ MCD_OPC_CheckPredicate, + 4, + 102, + 0, + 0, // Skip to: 516 + /* 414 */ MCD_OPC_Decode, + 178, + 8, + 17, // Opcode: CINS + /* 418 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 432 + /* 423 */ MCD_OPC_CheckPredicate, + 4, + 88, + 0, + 0, // Skip to: 516 + /* 428 */ MCD_OPC_Decode, + 179, + 8, + 17, // Opcode: CINS32 + /* 432 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 446 + /* 437 */ MCD_OPC_CheckPredicate, + 4, + 74, + 0, + 0, // Skip to: 516 + /* 442 */ MCD_OPC_Decode, + 134, + 12, + 17, // Opcode: EXTS + /* 446 */ MCD_OPC_FilterValue, + 59, + 65, + 0, + 0, // Skip to: 516 + /* 451 */ MCD_OPC_CheckPredicate, + 4, + 60, + 0, + 0, // Skip to: 516 + /* 456 */ MCD_OPC_Decode, + 135, + 12, + 17, // Opcode: EXTS32 + /* 460 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 474 + /* 465 */ MCD_OPC_CheckPredicate, + 3, + 46, + 0, + 0, // Skip to: 516 + /* 470 */ MCD_OPC_Decode, + 205, + 6, + 18, // Opcode: BBIT0 + /* 474 */ MCD_OPC_FilterValue, + 54, + 9, + 0, + 0, // Skip to: 488 + /* 479 */ MCD_OPC_CheckPredicate, + 3, + 32, + 0, + 0, // Skip to: 516 + /* 484 */ MCD_OPC_Decode, + 206, + 6, + 18, // Opcode: BBIT032 + /* 488 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 502 + /* 493 */ MCD_OPC_CheckPredicate, + 3, + 18, + 0, + 0, // Skip to: 516 + /* 498 */ MCD_OPC_Decode, + 207, + 6, + 18, // Opcode: BBIT1 + /* 502 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 516 + /* 507 */ MCD_OPC_CheckPredicate, + 3, + 4, + 0, + 0, // Skip to: 516 + /* 512 */ MCD_OPC_Decode, + 208, + 6, + 18, // Opcode: BBIT132 + /* 516 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableCnMipsP32[] = { + /* 0 */ MCD_OPC_ExtractField, + 0, + 16, // Inst{15-0} ... + /* 3 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 24 + /* 8 */ MCD_OPC_CheckPredicate, + 5, + 32, + 0, + 0, // Skip to: 45 + /* 13 */ MCD_OPC_CheckField, + 26, + 6, + 28, + 25, + 0, + 0, // Skip to: 45 + /* 20 */ MCD_OPC_Decode, + 224, + 18, + 19, // Opcode: SAA + /* 24 */ MCD_OPC_FilterValue, + 25, + 16, + 0, + 0, // Skip to: 45 + /* 29 */ MCD_OPC_CheckPredicate, + 5, + 11, + 0, + 0, // Skip to: 45 + /* 34 */ MCD_OPC_CheckField, + 26, + 6, + 28, + 4, + 0, + 0, // Skip to: 45 + /* 41 */ MCD_OPC_Decode, + 225, + 18, + 19, // Opcode: SAAD + /* 45 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMicroMips16[] = { -/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33 -/* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 21 -/* 14 */ MCD_OPC_CheckPredicate, 3, 19, 2, // Skip to: 549 -/* 18 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDU16_MM -/* 21 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 549 -/* 25 */ MCD_OPC_CheckPredicate, 3, 8, 2, // Skip to: 549 -/* 29 */ MCD_OPC_Decode, 214, 12, 11, // Opcode: SUBU16_MM -/* 33 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 45 -/* 37 */ MCD_OPC_CheckPredicate, 3, 252, 1, // Skip to: 549 -/* 41 */ MCD_OPC_Decode, 155, 7, 12, // Opcode: LBU16_MM -/* 45 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 57 -/* 49 */ MCD_OPC_CheckPredicate, 3, 240, 1, // Skip to: 549 -/* 53 */ MCD_OPC_Decode, 233, 8, 13, // Opcode: MOVE16_MM -/* 57 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 88 -/* 61 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 64 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 76 -/* 68 */ MCD_OPC_CheckPredicate, 3, 221, 1, // Skip to: 549 -/* 72 */ MCD_OPC_Decode, 226, 11, 14, // Opcode: SLL16_MM -/* 76 */ MCD_OPC_FilterValue, 1, 213, 1, // Skip to: 549 -/* 80 */ MCD_OPC_CheckPredicate, 3, 209, 1, // Skip to: 549 -/* 84 */ MCD_OPC_Decode, 160, 12, 14, // Opcode: SRL16_MM -/* 88 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 100 -/* 92 */ MCD_OPC_CheckPredicate, 3, 197, 1, // Skip to: 549 -/* 96 */ MCD_OPC_Decode, 186, 7, 12, // Opcode: LHU16_MM -/* 100 */ MCD_OPC_FilterValue, 11, 7, 0, // Skip to: 111 -/* 104 */ MCD_OPC_CheckPredicate, 3, 185, 1, // Skip to: 549 -/* 108 */ MCD_OPC_Decode, 86, 15, // Opcode: ANDI16_MM -/* 111 */ MCD_OPC_FilterValue, 17, 226, 0, // Skip to: 341 -/* 115 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 -/* 122 */ MCD_OPC_CheckPredicate, 3, 167, 1, // Skip to: 549 -/* 126 */ MCD_OPC_Decode, 130, 10, 16, // Opcode: NOT16_MM -/* 130 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 142 -/* 134 */ MCD_OPC_CheckPredicate, 3, 155, 1, // Skip to: 549 -/* 138 */ MCD_OPC_Decode, 237, 13, 17, // Opcode: XOR16_MM -/* 142 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 153 -/* 146 */ MCD_OPC_CheckPredicate, 3, 143, 1, // Skip to: 549 -/* 150 */ MCD_OPC_Decode, 84, 17, // Opcode: AND16_MM -/* 153 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 165 -/* 157 */ MCD_OPC_CheckPredicate, 3, 132, 1, // Skip to: 549 -/* 161 */ MCD_OPC_Decode, 134, 10, 17, // Opcode: OR16_MM -/* 165 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 177 -/* 169 */ MCD_OPC_CheckPredicate, 3, 120, 1, // Skip to: 549 -/* 173 */ MCD_OPC_Decode, 225, 7, 18, // Opcode: LWM16_MM -/* 177 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 189 -/* 181 */ MCD_OPC_CheckPredicate, 3, 108, 1, // Skip to: 549 -/* 185 */ MCD_OPC_Decode, 246, 12, 18, // Opcode: SWM16_MM -/* 189 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 220 -/* 193 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 208 -/* 200 */ MCD_OPC_CheckPredicate, 3, 89, 1, // Skip to: 549 -/* 204 */ MCD_OPC_Decode, 137, 7, 19, // Opcode: JR16_MM -/* 208 */ MCD_OPC_FilterValue, 1, 81, 1, // Skip to: 549 -/* 212 */ MCD_OPC_CheckPredicate, 3, 77, 1, // Skip to: 549 -/* 216 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: JRC16_MM -/* 220 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 251 -/* 224 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... -/* 227 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 239 -/* 231 */ MCD_OPC_CheckPredicate, 3, 58, 1, // Skip to: 549 -/* 235 */ MCD_OPC_Decode, 250, 6, 19, // Opcode: JALR16_MM -/* 239 */ MCD_OPC_FilterValue, 1, 50, 1, // Skip to: 549 -/* 243 */ MCD_OPC_CheckPredicate, 3, 46, 1, // Skip to: 549 -/* 247 */ MCD_OPC_Decode, 254, 6, 19, // Opcode: JALRS16_MM -/* 251 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 269 -/* 255 */ MCD_OPC_CheckPredicate, 3, 34, 1, // Skip to: 549 -/* 259 */ MCD_OPC_CheckField, 5, 1, 0, 28, 1, // Skip to: 549 -/* 265 */ MCD_OPC_Decode, 187, 8, 19, // Opcode: MFHI16_MM -/* 269 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 287 -/* 273 */ MCD_OPC_CheckPredicate, 3, 16, 1, // Skip to: 549 -/* 277 */ MCD_OPC_CheckField, 5, 1, 0, 10, 1, // Skip to: 549 -/* 283 */ MCD_OPC_Decode, 192, 8, 19, // Opcode: MFLO16_MM -/* 287 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 305 -/* 291 */ MCD_OPC_CheckPredicate, 3, 254, 0, // Skip to: 549 -/* 295 */ MCD_OPC_CheckField, 4, 2, 0, 248, 0, // Skip to: 549 -/* 301 */ MCD_OPC_Decode, 172, 2, 20, // Opcode: BREAK16_MM -/* 305 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 323 -/* 309 */ MCD_OPC_CheckPredicate, 3, 236, 0, // Skip to: 549 -/* 313 */ MCD_OPC_CheckField, 4, 2, 0, 230, 0, // Skip to: 549 -/* 319 */ MCD_OPC_Decode, 153, 11, 20, // Opcode: SDBBP16_MM -/* 323 */ MCD_OPC_FilterValue, 12, 222, 0, // Skip to: 549 -/* 327 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 549 -/* 331 */ MCD_OPC_CheckField, 5, 1, 0, 212, 0, // Skip to: 549 -/* 337 */ MCD_OPC_Decode, 139, 7, 21, // Opcode: JRADDIUSP -/* 341 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 353 -/* 345 */ MCD_OPC_CheckPredicate, 3, 200, 0, // Skip to: 549 -/* 349 */ MCD_OPC_Decode, 233, 7, 22, // Opcode: LWSP_MM -/* 353 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 382 -/* 357 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 360 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 371 -/* 364 */ MCD_OPC_CheckPredicate, 3, 181, 0, // Skip to: 549 -/* 368 */ MCD_OPC_Decode, 30, 23, // Opcode: ADDIUS5_MM -/* 371 */ MCD_OPC_FilterValue, 1, 174, 0, // Skip to: 549 -/* 375 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 549 -/* 379 */ MCD_OPC_Decode, 31, 24, // Opcode: ADDIUSP_MM -/* 382 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 394 -/* 386 */ MCD_OPC_CheckPredicate, 3, 159, 0, // Skip to: 549 -/* 390 */ MCD_OPC_Decode, 221, 7, 25, // Opcode: LWGP_MM -/* 394 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 406 -/* 398 */ MCD_OPC_CheckPredicate, 3, 147, 0, // Skip to: 549 -/* 402 */ MCD_OPC_Decode, 214, 7, 12, // Opcode: LW16_MM -/* 406 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 435 -/* 410 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 413 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 424 -/* 417 */ MCD_OPC_CheckPredicate, 3, 128, 0, // Skip to: 549 -/* 421 */ MCD_OPC_Decode, 29, 26, // Opcode: ADDIUR2_MM -/* 424 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 549 -/* 428 */ MCD_OPC_CheckPredicate, 3, 117, 0, // Skip to: 549 -/* 432 */ MCD_OPC_Decode, 28, 27, // Opcode: ADDIUR1SP_MM -/* 435 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 453 -/* 439 */ MCD_OPC_CheckPredicate, 3, 106, 0, // Skip to: 549 -/* 443 */ MCD_OPC_CheckField, 0, 1, 0, 100, 0, // Skip to: 549 -/* 449 */ MCD_OPC_Decode, 234, 8, 28, // Opcode: MOVEP_MM -/* 453 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 465 -/* 457 */ MCD_OPC_CheckPredicate, 3, 88, 0, // Skip to: 549 -/* 461 */ MCD_OPC_Decode, 143, 11, 12, // Opcode: SB16_MM -/* 465 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 477 -/* 469 */ MCD_OPC_CheckPredicate, 3, 76, 0, // Skip to: 549 -/* 473 */ MCD_OPC_Decode, 210, 1, 29, // Opcode: BEQZ16_MM -/* 477 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 489 -/* 481 */ MCD_OPC_CheckPredicate, 3, 64, 0, // Skip to: 549 -/* 485 */ MCD_OPC_Decode, 187, 11, 12, // Opcode: SH16_MM -/* 489 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 501 -/* 493 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 549 -/* 497 */ MCD_OPC_Decode, 157, 2, 29, // Opcode: BNEZ16_MM -/* 501 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 513 -/* 505 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 549 -/* 509 */ MCD_OPC_Decode, 253, 12, 22, // Opcode: SWSP_MM -/* 513 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 525 -/* 517 */ MCD_OPC_CheckPredicate, 4, 28, 0, // Skip to: 549 -/* 521 */ MCD_OPC_Decode, 165, 1, 30, // Opcode: B16_MM -/* 525 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 537 -/* 529 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 549 -/* 533 */ MCD_OPC_Decode, 236, 12, 12, // Opcode: SW16_MM -/* 537 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 549 -/* 541 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 549 -/* 545 */ MCD_OPC_Decode, 192, 7, 31, // Opcode: LI16_MM -/* 549 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 3 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 39 + /* 8 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 25 + /* 16 */ MCD_OPC_CheckPredicate, + 6, + 114, + 2, + 0, // Skip to: 647 + /* 21 */ MCD_OPC_Decode, + 232, + 5, + 20, // Opcode: ADDU16_MM + /* 25 */ MCD_OPC_FilterValue, + 1, + 105, + 2, + 0, // Skip to: 647 + /* 30 */ MCD_OPC_CheckPredicate, + 6, + 100, + 2, + 0, // Skip to: 647 + /* 35 */ MCD_OPC_Decode, + 231, + 20, + 20, // Opcode: SUBU16_MM + /* 39 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 53 + /* 44 */ MCD_OPC_CheckPredicate, + 7, + 86, + 2, + 0, // Skip to: 647 + /* 49 */ MCD_OPC_Decode, + 156, + 14, + 21, // Opcode: LBU16_MM + /* 53 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 67 + /* 58 */ MCD_OPC_CheckPredicate, + 6, + 72, + 2, + 0, // Skip to: 647 + /* 63 */ MCD_OPC_Decode, + 157, + 16, + 22, // Opcode: MOVE16_MM + /* 67 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 103 + /* 72 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 75 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 89 + /* 80 */ MCD_OPC_CheckPredicate, + 6, + 50, + 2, + 0, // Skip to: 647 + /* 85 */ MCD_OPC_Decode, + 241, + 19, + 23, // Opcode: SLL16_MM + /* 89 */ MCD_OPC_FilterValue, + 1, + 41, + 2, + 0, // Skip to: 647 + /* 94 */ MCD_OPC_CheckPredicate, + 6, + 36, + 2, + 0, // Skip to: 647 + /* 99 */ MCD_OPC_Decode, + 172, + 20, + 23, // Opcode: SRL16_MM + /* 103 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 117 + /* 108 */ MCD_OPC_CheckPredicate, + 7, + 22, + 2, + 0, // Skip to: 647 + /* 113 */ MCD_OPC_Decode, + 196, + 14, + 21, // Opcode: LHU16_MM + /* 117 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 131 + /* 122 */ MCD_OPC_CheckPredicate, + 6, + 8, + 2, + 0, // Skip to: 647 + /* 127 */ MCD_OPC_Decode, + 149, + 6, + 24, // Opcode: ANDI16_MM + /* 131 */ MCD_OPC_FilterValue, + 17, + 8, + 1, + 0, // Skip to: 400 + /* 136 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 139 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 153 + /* 144 */ MCD_OPC_CheckPredicate, + 6, + 242, + 1, + 0, // Skip to: 647 + /* 149 */ MCD_OPC_Decode, + 216, + 17, + 25, // Opcode: NOT16_MM + /* 153 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 167 + /* 158 */ MCD_OPC_CheckPredicate, + 6, + 228, + 1, + 0, // Skip to: 647 + /* 163 */ MCD_OPC_Decode, + 146, + 22, + 26, // Opcode: XOR16_MM + /* 167 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 181 + /* 172 */ MCD_OPC_CheckPredicate, + 6, + 214, + 1, + 0, // Skip to: 647 + /* 177 */ MCD_OPC_Decode, + 146, + 6, + 26, // Opcode: AND16_MM + /* 181 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 195 + /* 186 */ MCD_OPC_CheckPredicate, + 6, + 200, + 1, + 0, // Skip to: 647 + /* 191 */ MCD_OPC_Decode, + 221, + 17, + 26, // Opcode: OR16_MM + /* 195 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 209 + /* 200 */ MCD_OPC_CheckPredicate, + 6, + 186, + 1, + 0, // Skip to: 647 + /* 205 */ MCD_OPC_Decode, + 246, + 14, + 27, // Opcode: LWM16_MM + /* 209 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 223 + /* 214 */ MCD_OPC_CheckPredicate, + 6, + 172, + 1, + 0, // Skip to: 647 + /* 219 */ MCD_OPC_Decode, + 152, + 21, + 27, // Opcode: SWM16_MM + /* 223 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 259 + /* 228 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 231 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 245 + /* 236 */ MCD_OPC_CheckPredicate, + 6, + 150, + 1, + 0, // Skip to: 647 + /* 241 */ MCD_OPC_Decode, + 134, + 14, + 28, // Opcode: JR16_MM + /* 245 */ MCD_OPC_FilterValue, + 1, + 141, + 1, + 0, // Skip to: 647 + /* 250 */ MCD_OPC_CheckPredicate, + 6, + 136, + 1, + 0, // Skip to: 647 + /* 255 */ MCD_OPC_Decode, + 137, + 14, + 28, // Opcode: JRC16_MM + /* 259 */ MCD_OPC_FilterValue, + 7, + 31, + 0, + 0, // Skip to: 295 + /* 264 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 267 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 281 + /* 272 */ MCD_OPC_CheckPredicate, + 6, + 114, + 1, + 0, // Skip to: 647 + /* 277 */ MCD_OPC_Decode, + 241, + 13, + 28, // Opcode: JALR16_MM + /* 281 */ MCD_OPC_FilterValue, + 1, + 105, + 1, + 0, // Skip to: 647 + /* 286 */ MCD_OPC_CheckPredicate, + 6, + 100, + 1, + 0, // Skip to: 647 + /* 291 */ MCD_OPC_Decode, + 246, + 13, + 28, // Opcode: JALRS16_MM + /* 295 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 316 + /* 300 */ MCD_OPC_CheckPredicate, + 6, + 86, + 1, + 0, // Skip to: 647 + /* 305 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 79, + 1, + 0, // Skip to: 647 + /* 312 */ MCD_OPC_Decode, + 231, + 15, + 28, // Opcode: MFHI16_MM + /* 316 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 337 + /* 321 */ MCD_OPC_CheckPredicate, + 6, + 65, + 1, + 0, // Skip to: 647 + /* 326 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 58, + 1, + 0, // Skip to: 647 + /* 333 */ MCD_OPC_Decode, + 237, + 15, + 28, // Opcode: MFLO16_MM + /* 337 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 358 + /* 342 */ MCD_OPC_CheckPredicate, + 6, + 44, + 1, + 0, // Skip to: 647 + /* 347 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 37, + 1, + 0, // Skip to: 647 + /* 354 */ MCD_OPC_Decode, + 247, + 7, + 29, // Opcode: BREAK16_MM + /* 358 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 379 + /* 363 */ MCD_OPC_CheckPredicate, + 6, + 23, + 1, + 0, // Skip to: 647 + /* 368 */ MCD_OPC_CheckField, + 4, + 2, + 0, + 16, + 1, + 0, // Skip to: 647 + /* 375 */ MCD_OPC_Decode, + 254, + 18, + 29, // Opcode: SDBBP16_MM + /* 379 */ MCD_OPC_FilterValue, + 12, + 7, + 1, + 0, // Skip to: 647 + /* 384 */ MCD_OPC_CheckPredicate, + 6, + 2, + 1, + 0, // Skip to: 647 + /* 389 */ MCD_OPC_CheckField, + 5, + 1, + 0, + 251, + 0, + 0, // Skip to: 647 + /* 396 */ MCD_OPC_Decode, + 136, + 14, + 30, // Opcode: JRADDIUSP + /* 400 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 414 + /* 405 */ MCD_OPC_CheckPredicate, + 7, + 237, + 0, + 0, // Skip to: 647 + /* 410 */ MCD_OPC_Decode, + 129, + 15, + 31, // Opcode: LWSP_MM + /* 414 */ MCD_OPC_FilterValue, + 19, + 31, + 0, + 0, // Skip to: 450 + /* 419 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 422 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 436 + /* 427 */ MCD_OPC_CheckPredicate, + 7, + 215, + 0, + 0, // Skip to: 647 + /* 432 */ MCD_OPC_Decode, + 200, + 5, + 32, // Opcode: ADDIUS5_MM + /* 436 */ MCD_OPC_FilterValue, + 1, + 206, + 0, + 0, // Skip to: 647 + /* 441 */ MCD_OPC_CheckPredicate, + 7, + 201, + 0, + 0, // Skip to: 647 + /* 446 */ MCD_OPC_Decode, + 201, + 5, + 33, // Opcode: ADDIUSP_MM + /* 450 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 464 + /* 455 */ MCD_OPC_CheckPredicate, + 7, + 187, + 0, + 0, // Skip to: 647 + /* 460 */ MCD_OPC_Decode, + 240, + 14, + 34, // Opcode: LWGP_MM + /* 464 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 478 + /* 469 */ MCD_OPC_CheckPredicate, + 7, + 173, + 0, + 0, // Skip to: 647 + /* 474 */ MCD_OPC_Decode, + 228, + 14, + 21, // Opcode: LW16_MM + /* 478 */ MCD_OPC_FilterValue, + 27, + 31, + 0, + 0, // Skip to: 514 + /* 483 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 486 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 500 + /* 491 */ MCD_OPC_CheckPredicate, + 7, + 151, + 0, + 0, // Skip to: 647 + /* 496 */ MCD_OPC_Decode, + 199, + 5, + 35, // Opcode: ADDIUR2_MM + /* 500 */ MCD_OPC_FilterValue, + 1, + 142, + 0, + 0, // Skip to: 647 + /* 505 */ MCD_OPC_CheckPredicate, + 7, + 137, + 0, + 0, // Skip to: 647 + /* 510 */ MCD_OPC_Decode, + 198, + 5, + 36, // Opcode: ADDIUR1SP_MM + /* 514 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 535 + /* 519 */ MCD_OPC_CheckPredicate, + 6, + 123, + 0, + 0, // Skip to: 647 + /* 524 */ MCD_OPC_CheckField, + 0, + 1, + 0, + 116, + 0, + 0, // Skip to: 647 + /* 531 */ MCD_OPC_Decode, + 159, + 16, + 37, // Opcode: MOVEP_MM + /* 535 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 549 + /* 540 */ MCD_OPC_CheckPredicate, + 6, + 102, + 0, + 0, // Skip to: 647 + /* 545 */ MCD_OPC_Decode, + 235, + 18, + 21, // Opcode: SB16_MM + /* 549 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 563 + /* 554 */ MCD_OPC_CheckPredicate, + 6, + 88, + 0, + 0, // Skip to: 647 + /* 559 */ MCD_OPC_Decode, + 250, + 6, + 38, // Opcode: BEQZ16_MM + /* 563 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 577 + /* 568 */ MCD_OPC_CheckPredicate, + 6, + 74, + 0, + 0, // Skip to: 647 + /* 573 */ MCD_OPC_Decode, + 172, + 19, + 21, // Opcode: SH16_MM + /* 577 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 591 + /* 582 */ MCD_OPC_CheckPredicate, + 6, + 60, + 0, + 0, // Skip to: 647 + /* 587 */ MCD_OPC_Decode, + 225, + 7, + 38, // Opcode: BNEZ16_MM + /* 591 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 605 + /* 596 */ MCD_OPC_CheckPredicate, + 6, + 46, + 0, + 0, // Skip to: 647 + /* 601 */ MCD_OPC_Decode, + 161, + 21, + 31, // Opcode: SWSP_MM + /* 605 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 619 + /* 610 */ MCD_OPC_CheckPredicate, + 7, + 32, + 0, + 0, // Skip to: 647 + /* 615 */ MCD_OPC_Decode, + 198, + 6, + 39, // Opcode: B16_MM + /* 619 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 633 + /* 624 */ MCD_OPC_CheckPredicate, + 6, + 18, + 0, + 0, // Skip to: 647 + /* 629 */ MCD_OPC_Decode, + 134, + 21, + 21, // Opcode: SW16_MM + /* 633 */ MCD_OPC_FilterValue, + 59, + 9, + 0, + 0, // Skip to: 647 + /* 638 */ MCD_OPC_CheckPredicate, + 6, + 4, + 0, + 0, // Skip to: 647 + /* 643 */ MCD_OPC_Decode, + 205, + 14, + 40, // Opcode: LI16_MM + /* 647 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMicroMips32[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 189, 3, // Skip to: 964 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 90, 0, // Skip to: 104 -/* 14 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 17 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 68 -/* 21 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... -/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 -/* 28 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 60 -/* 32 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: SSNOP_MM -/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 -/* 40 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 60 -/* 44 */ MCD_OPC_Decode, 140, 5, 0, // Opcode: EHB_MM -/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 -/* 52 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 60 -/* 56 */ MCD_OPC_Decode, 148, 10, 0, // Opcode: PAUSE_MM -/* 60 */ MCD_OPC_CheckPredicate, 3, 38, 6, // Skip to: 1638 -/* 64 */ MCD_OPC_Decode, 238, 11, 32, // Opcode: SLL_MM -/* 68 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 80 -/* 72 */ MCD_OPC_CheckPredicate, 3, 26, 6, // Skip to: 1638 -/* 76 */ MCD_OPC_Decode, 178, 12, 32, // Opcode: SRL_MM -/* 80 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 92 -/* 84 */ MCD_OPC_CheckPredicate, 3, 14, 6, // Skip to: 1638 -/* 88 */ MCD_OPC_Decode, 157, 12, 32, // Opcode: SRA_MM -/* 92 */ MCD_OPC_FilterValue, 3, 6, 6, // Skip to: 1638 -/* 96 */ MCD_OPC_CheckPredicate, 3, 2, 6, // Skip to: 1638 -/* 100 */ MCD_OPC_Decode, 250, 10, 32, // Opcode: ROTR_MM -/* 104 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 116 -/* 108 */ MCD_OPC_CheckPredicate, 3, 246, 5, // Skip to: 1638 -/* 112 */ MCD_OPC_Decode, 173, 2, 33, // Opcode: BREAK_MM -/* 116 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 128 -/* 120 */ MCD_OPC_CheckPredicate, 3, 234, 5, // Skip to: 1638 -/* 124 */ MCD_OPC_Decode, 246, 6, 34, // Opcode: INS_MM -/* 128 */ MCD_OPC_FilterValue, 16, 180, 0, // Skip to: 312 -/* 132 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 135 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 147 -/* 139 */ MCD_OPC_CheckPredicate, 3, 215, 5, // Skip to: 1638 -/* 143 */ MCD_OPC_Decode, 234, 11, 35, // Opcode: SLLV_MM -/* 147 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 159 -/* 151 */ MCD_OPC_CheckPredicate, 3, 203, 5, // Skip to: 1638 -/* 155 */ MCD_OPC_Decode, 174, 12, 35, // Opcode: SRLV_MM -/* 159 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 171 -/* 163 */ MCD_OPC_CheckPredicate, 3, 191, 5, // Skip to: 1638 -/* 167 */ MCD_OPC_Decode, 153, 12, 35, // Opcode: SRAV_MM -/* 171 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 183 -/* 175 */ MCD_OPC_CheckPredicate, 3, 179, 5, // Skip to: 1638 -/* 179 */ MCD_OPC_Decode, 249, 10, 35, // Opcode: ROTRV_MM -/* 183 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 194 -/* 187 */ MCD_OPC_CheckPredicate, 3, 167, 5, // Skip to: 1638 -/* 191 */ MCD_OPC_Decode, 72, 36, // Opcode: ADD_MM -/* 194 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 205 -/* 198 */ MCD_OPC_CheckPredicate, 3, 156, 5, // Skip to: 1638 -/* 202 */ MCD_OPC_Decode, 78, 36, // Opcode: ADDu_MM -/* 205 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 217 -/* 209 */ MCD_OPC_CheckPredicate, 3, 145, 5, // Skip to: 1638 -/* 213 */ MCD_OPC_Decode, 229, 12, 36, // Opcode: SUB_MM -/* 217 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 229 -/* 221 */ MCD_OPC_CheckPredicate, 3, 133, 5, // Skip to: 1638 -/* 225 */ MCD_OPC_Decode, 231, 12, 36, // Opcode: SUBu_MM -/* 229 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 241 -/* 233 */ MCD_OPC_CheckPredicate, 3, 121, 5, // Skip to: 1638 -/* 237 */ MCD_OPC_Decode, 217, 9, 36, // Opcode: MUL_MM -/* 241 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 252 -/* 245 */ MCD_OPC_CheckPredicate, 3, 109, 5, // Skip to: 1638 -/* 249 */ MCD_OPC_Decode, 88, 36, // Opcode: AND_MM -/* 252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 264 -/* 256 */ MCD_OPC_CheckPredicate, 3, 98, 5, // Skip to: 1638 -/* 260 */ MCD_OPC_Decode, 137, 10, 36, // Opcode: OR_MM -/* 264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 276 -/* 268 */ MCD_OPC_CheckPredicate, 3, 86, 5, // Skip to: 1638 -/* 272 */ MCD_OPC_Decode, 253, 9, 36, // Opcode: NOR_MM -/* 276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 288 -/* 280 */ MCD_OPC_CheckPredicate, 3, 74, 5, // Skip to: 1638 -/* 284 */ MCD_OPC_Decode, 240, 13, 36, // Opcode: XOR_MM -/* 288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 300 -/* 292 */ MCD_OPC_CheckPredicate, 3, 62, 5, // Skip to: 1638 -/* 296 */ MCD_OPC_Decode, 242, 11, 36, // Opcode: SLT_MM -/* 300 */ MCD_OPC_FilterValue, 14, 54, 5, // Skip to: 1638 -/* 304 */ MCD_OPC_CheckPredicate, 3, 50, 5, // Skip to: 1638 -/* 308 */ MCD_OPC_Decode, 251, 11, 36, // Opcode: SLTu_MM -/* 312 */ MCD_OPC_FilterValue, 24, 39, 0, // Skip to: 355 -/* 316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 319 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 331 -/* 323 */ MCD_OPC_CheckPredicate, 3, 31, 5, // Skip to: 1638 -/* 327 */ MCD_OPC_Decode, 253, 8, 37, // Opcode: MOVN_I_MM -/* 331 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 343 -/* 335 */ MCD_OPC_CheckPredicate, 3, 19, 5, // Skip to: 1638 -/* 339 */ MCD_OPC_Decode, 145, 9, 37, // Opcode: MOVZ_I_MM -/* 343 */ MCD_OPC_FilterValue, 4, 11, 5, // Skip to: 1638 -/* 347 */ MCD_OPC_CheckPredicate, 3, 7, 5, // Skip to: 1638 -/* 351 */ MCD_OPC_Decode, 239, 7, 38, // Opcode: LWXS_MM -/* 355 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 367 -/* 359 */ MCD_OPC_CheckPredicate, 3, 251, 4, // Skip to: 1638 -/* 363 */ MCD_OPC_Decode, 160, 5, 39, // Opcode: EXT_MM -/* 367 */ MCD_OPC_FilterValue, 60, 243, 4, // Skip to: 1638 -/* 371 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... -/* 374 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 386 -/* 378 */ MCD_OPC_CheckPredicate, 3, 232, 4, // Skip to: 1638 -/* 382 */ MCD_OPC_Decode, 185, 13, 40, // Opcode: TEQ_MM -/* 386 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 398 -/* 390 */ MCD_OPC_CheckPredicate, 3, 220, 4, // Skip to: 1638 -/* 394 */ MCD_OPC_Decode, 193, 13, 40, // Opcode: TGE_MM -/* 398 */ MCD_OPC_FilterValue, 13, 123, 0, // Skip to: 525 -/* 402 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 405 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 423 -/* 409 */ MCD_OPC_CheckPredicate, 3, 201, 4, // Skip to: 1638 -/* 413 */ MCD_OPC_CheckField, 16, 10, 0, 195, 4, // Skip to: 1638 -/* 419 */ MCD_OPC_Decode, 195, 13, 0, // Opcode: TLBP_MM -/* 423 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 441 -/* 427 */ MCD_OPC_CheckPredicate, 3, 183, 4, // Skip to: 1638 -/* 431 */ MCD_OPC_CheckField, 16, 10, 0, 177, 4, // Skip to: 1638 -/* 437 */ MCD_OPC_Decode, 197, 13, 0, // Opcode: TLBR_MM -/* 441 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 459 -/* 445 */ MCD_OPC_CheckPredicate, 3, 165, 4, // Skip to: 1638 -/* 449 */ MCD_OPC_CheckField, 16, 10, 0, 159, 4, // Skip to: 1638 -/* 455 */ MCD_OPC_Decode, 199, 13, 0, // Opcode: TLBWI_MM -/* 459 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 477 -/* 463 */ MCD_OPC_CheckPredicate, 3, 147, 4, // Skip to: 1638 -/* 467 */ MCD_OPC_CheckField, 16, 10, 0, 141, 4, // Skip to: 1638 -/* 473 */ MCD_OPC_Decode, 201, 13, 0, // Opcode: TLBWR_MM -/* 477 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 489 -/* 481 */ MCD_OPC_CheckPredicate, 3, 129, 4, // Skip to: 1638 -/* 485 */ MCD_OPC_Decode, 232, 13, 41, // Opcode: WAIT_MM -/* 489 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 507 -/* 493 */ MCD_OPC_CheckPredicate, 3, 117, 4, // Skip to: 1638 -/* 497 */ MCD_OPC_CheckField, 16, 10, 0, 111, 4, // Skip to: 1638 -/* 503 */ MCD_OPC_Decode, 175, 4, 0, // Opcode: DERET_MM -/* 507 */ MCD_OPC_FilterValue, 15, 103, 4, // Skip to: 1638 -/* 511 */ MCD_OPC_CheckPredicate, 3, 99, 4, // Skip to: 1638 -/* 515 */ MCD_OPC_CheckField, 16, 10, 0, 93, 4, // Skip to: 1638 -/* 521 */ MCD_OPC_Decode, 144, 5, 0, // Opcode: ERET_MM -/* 525 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 537 -/* 529 */ MCD_OPC_CheckPredicate, 3, 81, 4, // Skip to: 1638 -/* 533 */ MCD_OPC_Decode, 192, 13, 40, // Opcode: TGEU_MM -/* 537 */ MCD_OPC_FilterValue, 29, 39, 0, // Skip to: 580 -/* 541 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 544 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 562 -/* 548 */ MCD_OPC_CheckPredicate, 3, 62, 4, // Skip to: 1638 -/* 552 */ MCD_OPC_CheckField, 21, 5, 0, 56, 4, // Skip to: 1638 -/* 558 */ MCD_OPC_Decode, 193, 4, 42, // Opcode: DI_MM -/* 562 */ MCD_OPC_FilterValue, 5, 48, 4, // Skip to: 1638 -/* 566 */ MCD_OPC_CheckPredicate, 3, 44, 4, // Skip to: 1638 -/* 570 */ MCD_OPC_CheckField, 21, 5, 0, 38, 4, // Skip to: 1638 -/* 576 */ MCD_OPC_Decode, 142, 5, 42, // Opcode: EI_MM -/* 580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 592 -/* 584 */ MCD_OPC_CheckPredicate, 3, 26, 4, // Skip to: 1638 -/* 588 */ MCD_OPC_Decode, 208, 13, 40, // Opcode: TLT_MM -/* 592 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 604 -/* 596 */ MCD_OPC_CheckPredicate, 3, 14, 4, // Skip to: 1638 -/* 600 */ MCD_OPC_Decode, 207, 13, 40, // Opcode: TLTU_MM -/* 604 */ MCD_OPC_FilterValue, 44, 171, 0, // Skip to: 779 -/* 608 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 611 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 623 -/* 615 */ MCD_OPC_CheckPredicate, 3, 251, 3, // Skip to: 1638 -/* 619 */ MCD_OPC_Decode, 170, 11, 43, // Opcode: SEB_MM -/* 623 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 635 -/* 627 */ MCD_OPC_CheckPredicate, 3, 239, 3, // Skip to: 1638 -/* 631 */ MCD_OPC_Decode, 173, 11, 43, // Opcode: SEH_MM -/* 635 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 647 -/* 639 */ MCD_OPC_CheckPredicate, 3, 227, 3, // Skip to: 1638 -/* 643 */ MCD_OPC_Decode, 134, 3, 43, // Opcode: CLO_MM -/* 647 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 659 -/* 651 */ MCD_OPC_CheckPredicate, 3, 215, 3, // Skip to: 1638 -/* 655 */ MCD_OPC_Decode, 153, 3, 43, // Opcode: CLZ_MM -/* 659 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 671 -/* 663 */ MCD_OPC_CheckPredicate, 3, 203, 3, // Skip to: 1638 -/* 667 */ MCD_OPC_Decode, 240, 10, 44, // Opcode: RDHWR_MM -/* 671 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 683 -/* 675 */ MCD_OPC_CheckPredicate, 3, 191, 3, // Skip to: 1638 -/* 679 */ MCD_OPC_Decode, 235, 13, 43, // Opcode: WSBH_MM -/* 683 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 695 -/* 687 */ MCD_OPC_CheckPredicate, 3, 179, 3, // Skip to: 1638 -/* 691 */ MCD_OPC_Decode, 209, 9, 45, // Opcode: MULT_MM -/* 695 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 707 -/* 699 */ MCD_OPC_CheckPredicate, 3, 167, 3, // Skip to: 1638 -/* 703 */ MCD_OPC_Decode, 211, 9, 45, // Opcode: MULTu_MM -/* 707 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 719 -/* 711 */ MCD_OPC_CheckPredicate, 3, 155, 3, // Skip to: 1638 -/* 715 */ MCD_OPC_Decode, 163, 11, 45, // Opcode: SDIV_MM -/* 719 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 731 -/* 723 */ MCD_OPC_CheckPredicate, 3, 143, 3, // Skip to: 1638 -/* 727 */ MCD_OPC_Decode, 223, 13, 45, // Opcode: UDIV_MM -/* 731 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 743 -/* 735 */ MCD_OPC_CheckPredicate, 3, 131, 3, // Skip to: 1638 -/* 739 */ MCD_OPC_Decode, 146, 8, 45, // Opcode: MADD_MM -/* 743 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 755 -/* 747 */ MCD_OPC_CheckPredicate, 3, 119, 3, // Skip to: 1638 -/* 751 */ MCD_OPC_Decode, 137, 8, 45, // Opcode: MADDU_MM -/* 755 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 767 -/* 759 */ MCD_OPC_CheckPredicate, 3, 107, 3, // Skip to: 1638 -/* 763 */ MCD_OPC_Decode, 164, 9, 45, // Opcode: MSUB_MM -/* 767 */ MCD_OPC_FilterValue, 15, 99, 3, // Skip to: 1638 -/* 771 */ MCD_OPC_CheckPredicate, 3, 95, 3, // Skip to: 1638 -/* 775 */ MCD_OPC_Decode, 155, 9, 45, // Opcode: MSUBU_MM -/* 779 */ MCD_OPC_FilterValue, 45, 45, 0, // Skip to: 828 -/* 783 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 786 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 804 -/* 790 */ MCD_OPC_CheckPredicate, 3, 76, 3, // Skip to: 1638 -/* 794 */ MCD_OPC_CheckField, 21, 5, 0, 70, 3, // Skip to: 1638 -/* 800 */ MCD_OPC_Decode, 131, 13, 46, // Opcode: SYNC_MM -/* 804 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 816 -/* 808 */ MCD_OPC_CheckPredicate, 3, 58, 3, // Skip to: 1638 -/* 812 */ MCD_OPC_Decode, 133, 13, 41, // Opcode: SYSCALL_MM -/* 816 */ MCD_OPC_FilterValue, 13, 50, 3, // Skip to: 1638 -/* 820 */ MCD_OPC_CheckPredicate, 3, 46, 3, // Skip to: 1638 -/* 824 */ MCD_OPC_Decode, 154, 11, 41, // Opcode: SDBBP_MM -/* 828 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 840 -/* 832 */ MCD_OPC_CheckPredicate, 3, 34, 3, // Skip to: 1638 -/* 836 */ MCD_OPC_Decode, 212, 13, 40, // Opcode: TNE_MM -/* 840 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 919 -/* 844 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 847 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 865 -/* 851 */ MCD_OPC_CheckPredicate, 3, 15, 3, // Skip to: 1638 -/* 855 */ MCD_OPC_CheckField, 21, 5, 0, 9, 3, // Skip to: 1638 -/* 861 */ MCD_OPC_Decode, 190, 8, 42, // Opcode: MFHI_MM -/* 865 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 883 -/* 869 */ MCD_OPC_CheckPredicate, 3, 253, 2, // Skip to: 1638 -/* 873 */ MCD_OPC_CheckField, 21, 5, 0, 247, 2, // Skip to: 1638 -/* 879 */ MCD_OPC_Decode, 195, 8, 42, // Opcode: MFLO_MM -/* 883 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 901 -/* 887 */ MCD_OPC_CheckPredicate, 3, 235, 2, // Skip to: 1638 -/* 891 */ MCD_OPC_CheckField, 21, 5, 0, 229, 2, // Skip to: 1638 -/* 897 */ MCD_OPC_Decode, 179, 9, 42, // Opcode: MTHI_MM -/* 901 */ MCD_OPC_FilterValue, 3, 221, 2, // Skip to: 1638 -/* 905 */ MCD_OPC_CheckPredicate, 3, 217, 2, // Skip to: 1638 -/* 909 */ MCD_OPC_CheckField, 21, 5, 0, 211, 2, // Skip to: 1638 -/* 915 */ MCD_OPC_Decode, 184, 9, 42, // Opcode: MTLO_MM -/* 919 */ MCD_OPC_FilterValue, 60, 203, 2, // Skip to: 1638 -/* 923 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 926 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 952 -/* 930 */ MCD_OPC_CheckPredicate, 3, 10, 0, // Skip to: 944 -/* 934 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 944 -/* 940 */ MCD_OPC_Decode, 143, 7, 42, // Opcode: JR_MM -/* 944 */ MCD_OPC_CheckPredicate, 3, 178, 2, // Skip to: 1638 -/* 948 */ MCD_OPC_Decode, 129, 7, 43, // Opcode: JALR_MM -/* 952 */ MCD_OPC_FilterValue, 4, 170, 2, // Skip to: 1638 -/* 956 */ MCD_OPC_CheckPredicate, 3, 166, 2, // Skip to: 1638 -/* 960 */ MCD_OPC_Decode, 255, 6, 43, // Opcode: JALRS_MM -/* 964 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 975 -/* 968 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 1638 -/* 972 */ MCD_OPC_Decode, 74, 47, // Opcode: ADDi_MM -/* 975 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 987 -/* 979 */ MCD_OPC_CheckPredicate, 3, 143, 2, // Skip to: 1638 -/* 983 */ MCD_OPC_Decode, 160, 7, 48, // Opcode: LBu_MM -/* 987 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 999 -/* 991 */ MCD_OPC_CheckPredicate, 3, 131, 2, // Skip to: 1638 -/* 995 */ MCD_OPC_Decode, 145, 11, 48, // Opcode: SB_MM -/* 999 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1011 -/* 1003 */ MCD_OPC_CheckPredicate, 3, 119, 2, // Skip to: 1638 -/* 1007 */ MCD_OPC_Decode, 157, 7, 48, // Opcode: LB_MM -/* 1011 */ MCD_OPC_FilterValue, 8, 63, 0, // Skip to: 1078 -/* 1015 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 1018 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1030 -/* 1022 */ MCD_OPC_CheckPredicate, 3, 100, 2, // Skip to: 1638 -/* 1026 */ MCD_OPC_Decode, 229, 7, 49, // Opcode: LWP_MM -/* 1030 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1042 -/* 1034 */ MCD_OPC_CheckPredicate, 3, 88, 2, // Skip to: 1638 -/* 1038 */ MCD_OPC_Decode, 226, 7, 49, // Opcode: LWM32_MM -/* 1042 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1054 -/* 1046 */ MCD_OPC_CheckPredicate, 3, 76, 2, // Skip to: 1638 -/* 1050 */ MCD_OPC_Decode, 221, 2, 50, // Opcode: CACHE_MM -/* 1054 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1066 -/* 1058 */ MCD_OPC_CheckPredicate, 3, 64, 2, // Skip to: 1638 -/* 1062 */ MCD_OPC_Decode, 249, 12, 49, // Opcode: SWP_MM -/* 1066 */ MCD_OPC_FilterValue, 13, 56, 2, // Skip to: 1638 -/* 1070 */ MCD_OPC_CheckPredicate, 3, 52, 2, // Skip to: 1638 -/* 1074 */ MCD_OPC_Decode, 247, 12, 49, // Opcode: SWM32_MM -/* 1078 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1089 -/* 1082 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 1638 -/* 1086 */ MCD_OPC_Decode, 76, 47, // Opcode: ADDiu_MM -/* 1089 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1101 -/* 1093 */ MCD_OPC_CheckPredicate, 3, 29, 2, // Skip to: 1638 -/* 1097 */ MCD_OPC_Decode, 191, 7, 48, // Opcode: LHu_MM -/* 1101 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1113 -/* 1105 */ MCD_OPC_CheckPredicate, 3, 17, 2, // Skip to: 1638 -/* 1109 */ MCD_OPC_Decode, 216, 11, 48, // Opcode: SH_MM -/* 1113 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1125 -/* 1117 */ MCD_OPC_CheckPredicate, 3, 5, 2, // Skip to: 1638 -/* 1121 */ MCD_OPC_Decode, 188, 7, 48, // Opcode: LH_MM -/* 1125 */ MCD_OPC_FilterValue, 16, 207, 0, // Skip to: 1336 -/* 1129 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1144 -/* 1136 */ MCD_OPC_CheckPredicate, 3, 242, 1, // Skip to: 1638 -/* 1140 */ MCD_OPC_Decode, 140, 2, 51, // Opcode: BLTZ_MM -/* 1144 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1156 -/* 1148 */ MCD_OPC_CheckPredicate, 3, 230, 1, // Skip to: 1638 -/* 1152 */ MCD_OPC_Decode, 137, 2, 51, // Opcode: BLTZAL_MM -/* 1156 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1168 -/* 1160 */ MCD_OPC_CheckPredicate, 3, 218, 1, // Skip to: 1638 -/* 1164 */ MCD_OPC_Decode, 226, 1, 51, // Opcode: BGEZ_MM -/* 1168 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1180 -/* 1172 */ MCD_OPC_CheckPredicate, 3, 206, 1, // Skip to: 1638 -/* 1176 */ MCD_OPC_Decode, 223, 1, 51, // Opcode: BGEZAL_MM -/* 1180 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1192 -/* 1184 */ MCD_OPC_CheckPredicate, 3, 194, 1, // Skip to: 1638 -/* 1188 */ MCD_OPC_Decode, 128, 2, 51, // Opcode: BLEZ_MM -/* 1192 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1204 -/* 1196 */ MCD_OPC_CheckPredicate, 3, 182, 1, // Skip to: 1638 -/* 1200 */ MCD_OPC_Decode, 160, 2, 51, // Opcode: BNEZC_MM -/* 1204 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1216 -/* 1208 */ MCD_OPC_CheckPredicate, 3, 170, 1, // Skip to: 1638 -/* 1212 */ MCD_OPC_Decode, 232, 1, 51, // Opcode: BGTZ_MM -/* 1216 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1228 -/* 1220 */ MCD_OPC_CheckPredicate, 3, 158, 1, // Skip to: 1638 -/* 1224 */ MCD_OPC_Decode, 213, 1, 51, // Opcode: BEQZC_MM -/* 1228 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1240 -/* 1232 */ MCD_OPC_CheckPredicate, 3, 146, 1, // Skip to: 1638 -/* 1236 */ MCD_OPC_Decode, 205, 13, 52, // Opcode: TLTI_MM -/* 1240 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1252 -/* 1244 */ MCD_OPC_CheckPredicate, 3, 134, 1, // Skip to: 1638 -/* 1248 */ MCD_OPC_Decode, 190, 13, 52, // Opcode: TGEI_MM -/* 1252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1264 -/* 1256 */ MCD_OPC_CheckPredicate, 3, 122, 1, // Skip to: 1638 -/* 1260 */ MCD_OPC_Decode, 204, 13, 52, // Opcode: TLTIU_MM -/* 1264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1276 -/* 1268 */ MCD_OPC_CheckPredicate, 3, 110, 1, // Skip to: 1638 -/* 1272 */ MCD_OPC_Decode, 189, 13, 52, // Opcode: TGEIU_MM -/* 1276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1288 -/* 1280 */ MCD_OPC_CheckPredicate, 3, 98, 1, // Skip to: 1638 -/* 1284 */ MCD_OPC_Decode, 211, 13, 52, // Opcode: TNEI_MM -/* 1288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1300 -/* 1292 */ MCD_OPC_CheckPredicate, 3, 86, 1, // Skip to: 1638 -/* 1296 */ MCD_OPC_Decode, 212, 7, 52, // Opcode: LUi_MM -/* 1300 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1312 -/* 1304 */ MCD_OPC_CheckPredicate, 3, 74, 1, // Skip to: 1638 -/* 1308 */ MCD_OPC_Decode, 184, 13, 52, // Opcode: TEQI_MM -/* 1312 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1324 -/* 1316 */ MCD_OPC_CheckPredicate, 3, 62, 1, // Skip to: 1638 -/* 1320 */ MCD_OPC_Decode, 136, 2, 51, // Opcode: BLTZALS_MM -/* 1324 */ MCD_OPC_FilterValue, 19, 54, 1, // Skip to: 1638 -/* 1328 */ MCD_OPC_CheckPredicate, 3, 50, 1, // Skip to: 1638 -/* 1332 */ MCD_OPC_Decode, 222, 1, 51, // Opcode: BGEZALS_MM -/* 1336 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 1348 -/* 1340 */ MCD_OPC_CheckPredicate, 3, 38, 1, // Skip to: 1638 -/* 1344 */ MCD_OPC_Decode, 144, 10, 53, // Opcode: ORi_MM -/* 1348 */ MCD_OPC_FilterValue, 21, 29, 0, // Skip to: 1381 -/* 1352 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... -/* 1355 */ MCD_OPC_FilterValue, 251, 2, 8, 0, // Skip to: 1368 -/* 1360 */ MCD_OPC_CheckPredicate, 3, 18, 1, // Skip to: 1638 -/* 1364 */ MCD_OPC_Decode, 241, 8, 54, // Opcode: MOVF_I_MM -/* 1368 */ MCD_OPC_FilterValue, 251, 18, 9, 1, // Skip to: 1638 -/* 1373 */ MCD_OPC_CheckPredicate, 3, 5, 1, // Skip to: 1638 -/* 1377 */ MCD_OPC_Decode, 133, 9, 54, // Opcode: MOVT_I_MM -/* 1381 */ MCD_OPC_FilterValue, 24, 99, 0, // Skip to: 1484 -/* 1385 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 1388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1400 -/* 1392 */ MCD_OPC_CheckPredicate, 3, 242, 0, // Skip to: 1638 -/* 1396 */ MCD_OPC_Decode, 224, 7, 49, // Opcode: LWL_MM -/* 1400 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1412 -/* 1404 */ MCD_OPC_CheckPredicate, 3, 230, 0, // Skip to: 1638 -/* 1408 */ MCD_OPC_Decode, 232, 7, 49, // Opcode: LWR_MM -/* 1412 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1424 -/* 1416 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 1638 -/* 1420 */ MCD_OPC_Decode, 182, 10, 50, // Opcode: PREF_MM -/* 1424 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1436 -/* 1428 */ MCD_OPC_CheckPredicate, 3, 206, 0, // Skip to: 1638 -/* 1432 */ MCD_OPC_Decode, 196, 7, 49, // Opcode: LL_MM -/* 1436 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1448 -/* 1440 */ MCD_OPC_CheckPredicate, 3, 194, 0, // Skip to: 1638 -/* 1444 */ MCD_OPC_Decode, 245, 12, 49, // Opcode: SWL_MM -/* 1448 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1460 -/* 1452 */ MCD_OPC_CheckPredicate, 3, 182, 0, // Skip to: 1638 -/* 1456 */ MCD_OPC_Decode, 252, 12, 49, // Opcode: SWR_MM -/* 1460 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1472 -/* 1464 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 1638 -/* 1468 */ MCD_OPC_Decode, 149, 11, 49, // Opcode: SC_MM -/* 1472 */ MCD_OPC_FilterValue, 14, 162, 0, // Skip to: 1638 -/* 1476 */ MCD_OPC_CheckPredicate, 3, 158, 0, // Skip to: 1638 -/* 1480 */ MCD_OPC_Decode, 235, 7, 49, // Opcode: LWU_MM -/* 1484 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1496 -/* 1488 */ MCD_OPC_CheckPredicate, 3, 146, 0, // Skip to: 1638 -/* 1492 */ MCD_OPC_Decode, 247, 13, 53, // Opcode: XORi_MM -/* 1496 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1508 -/* 1500 */ MCD_OPC_CheckPredicate, 3, 134, 0, // Skip to: 1638 -/* 1504 */ MCD_OPC_Decode, 130, 7, 55, // Opcode: JALS_MM -/* 1508 */ MCD_OPC_FilterValue, 30, 7, 0, // Skip to: 1519 -/* 1512 */ MCD_OPC_CheckPredicate, 3, 122, 0, // Skip to: 1638 -/* 1516 */ MCD_OPC_Decode, 27, 56, // Opcode: ADDIUPC_MM -/* 1519 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 1531 -/* 1523 */ MCD_OPC_CheckPredicate, 3, 111, 0, // Skip to: 1638 -/* 1527 */ MCD_OPC_Decode, 245, 11, 47, // Opcode: SLTi_MM -/* 1531 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 1543 -/* 1535 */ MCD_OPC_CheckPredicate, 3, 99, 0, // Skip to: 1638 -/* 1539 */ MCD_OPC_Decode, 214, 1, 57, // Opcode: BEQ_MM -/* 1543 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 1555 -/* 1547 */ MCD_OPC_CheckPredicate, 3, 87, 0, // Skip to: 1638 -/* 1551 */ MCD_OPC_Decode, 248, 11, 47, // Opcode: SLTiu_MM -/* 1555 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 1567 -/* 1559 */ MCD_OPC_CheckPredicate, 3, 75, 0, // Skip to: 1638 -/* 1563 */ MCD_OPC_Decode, 161, 2, 57, // Opcode: BNE_MM -/* 1567 */ MCD_OPC_FilterValue, 52, 7, 0, // Skip to: 1578 -/* 1571 */ MCD_OPC_CheckPredicate, 3, 63, 0, // Skip to: 1638 -/* 1575 */ MCD_OPC_Decode, 95, 53, // Opcode: ANDi_MM -/* 1578 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 1590 -/* 1582 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 1638 -/* 1586 */ MCD_OPC_Decode, 144, 7, 55, // Opcode: J_MM -/* 1590 */ MCD_OPC_FilterValue, 60, 8, 0, // Skip to: 1602 -/* 1594 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 1638 -/* 1598 */ MCD_OPC_Decode, 132, 7, 55, // Opcode: JALX_MM -/* 1602 */ MCD_OPC_FilterValue, 61, 8, 0, // Skip to: 1614 -/* 1606 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 1638 -/* 1610 */ MCD_OPC_Decode, 133, 7, 55, // Opcode: JAL_MM -/* 1614 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 1626 -/* 1618 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 1638 -/* 1622 */ MCD_OPC_Decode, 128, 13, 48, // Opcode: SW_MM -/* 1626 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 1638 -/* 1630 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 1638 -/* 1634 */ MCD_OPC_Decode, 240, 7, 48, // Opcode: LW_MM -/* 1638 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 238, + 14, + 0, // Skip to: 3830 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 104, + 0, + 0, // Skip to: 120 + /* 16 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 78 + /* 24 */ MCD_OPC_ExtractField, + 11, + 15, // Inst{25-11} ... + /* 27 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 41 + /* 32 */ MCD_OPC_CheckPredicate, + 7, + 32, + 0, + 0, // Skip to: 69 + /* 37 */ MCD_OPC_Decode, + 194, + 20, + 0, // Opcode: SSNOP_MM + /* 41 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 55 + /* 46 */ MCD_OPC_CheckPredicate, + 7, + 18, + 0, + 0, // Skip to: 69 + /* 51 */ MCD_OPC_Decode, + 223, + 11, + 0, // Opcode: EHB_MM + /* 55 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 69 + /* 60 */ MCD_OPC_CheckPredicate, + 7, + 4, + 0, + 0, // Skip to: 69 + /* 65 */ MCD_OPC_Decode, + 236, + 17, + 0, // Opcode: PAUSE_MM + /* 69 */ MCD_OPC_CheckPredicate, + 7, + 42, + 25, + 0, // Skip to: 6516 + /* 74 */ MCD_OPC_Decode, + 254, + 19, + 41, // Opcode: SLL_MM + /* 78 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 92 + /* 83 */ MCD_OPC_CheckPredicate, + 7, + 28, + 25, + 0, // Skip to: 6516 + /* 88 */ MCD_OPC_Decode, + 191, + 20, + 41, // Opcode: SRL_MM + /* 92 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 106 + /* 97 */ MCD_OPC_CheckPredicate, + 7, + 14, + 25, + 0, // Skip to: 6516 + /* 102 */ MCD_OPC_Decode, + 169, + 20, + 41, // Opcode: SRA_MM + /* 106 */ MCD_OPC_FilterValue, + 3, + 5, + 25, + 0, // Skip to: 6516 + /* 111 */ MCD_OPC_CheckPredicate, + 7, + 0, + 25, + 0, // Skip to: 6516 + /* 116 */ MCD_OPC_Decode, + 204, + 18, + 41, // Opcode: ROTR_MM + /* 120 */ MCD_OPC_FilterValue, + 5, + 227, + 0, + 0, // Skip to: 352 + /* 125 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 128 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 149 + /* 133 */ MCD_OPC_CheckPredicate, + 8, + 234, + 24, + 0, // Skip to: 6516 + /* 138 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 227, + 24, + 0, // Skip to: 6516 + /* 145 */ MCD_OPC_Decode, + 249, + 8, + 42, // Opcode: CMP_EQ_PH_MM + /* 149 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 170 + /* 154 */ MCD_OPC_CheckPredicate, + 8, + 213, + 24, + 0, // Skip to: 6516 + /* 159 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 206, + 24, + 0, // Skip to: 6516 + /* 166 */ MCD_OPC_Decode, + 135, + 9, + 42, // Opcode: CMP_LT_PH_MM + /* 170 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 191 + /* 175 */ MCD_OPC_CheckPredicate, + 8, + 192, + 24, + 0, // Skip to: 6516 + /* 180 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 185, + 24, + 0, // Skip to: 6516 + /* 187 */ MCD_OPC_Decode, + 129, + 9, + 42, // Opcode: CMP_LE_PH_MM + /* 191 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 205 + /* 196 */ MCD_OPC_CheckPredicate, + 9, + 171, + 24, + 0, // Skip to: 6516 + /* 201 */ MCD_OPC_Decode, + 227, + 8, + 43, // Opcode: CMPGDU_EQ_QB_MMR2 + /* 205 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 219 + /* 210 */ MCD_OPC_CheckPredicate, + 9, + 157, + 24, + 0, // Skip to: 6516 + /* 215 */ MCD_OPC_Decode, + 231, + 8, + 43, // Opcode: CMPGDU_LT_QB_MMR2 + /* 219 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 233 + /* 224 */ MCD_OPC_CheckPredicate, + 9, + 143, + 24, + 0, // Skip to: 6516 + /* 229 */ MCD_OPC_Decode, + 229, + 8, + 43, // Opcode: CMPGDU_LE_QB_MMR2 + /* 233 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 254 + /* 238 */ MCD_OPC_CheckPredicate, + 8, + 129, + 24, + 0, // Skip to: 6516 + /* 243 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 122, + 24, + 0, // Skip to: 6516 + /* 250 */ MCD_OPC_Decode, + 239, + 8, + 42, // Opcode: CMPU_EQ_QB_MM + /* 254 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 275 + /* 259 */ MCD_OPC_CheckPredicate, + 8, + 108, + 24, + 0, // Skip to: 6516 + /* 264 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 101, + 24, + 0, // Skip to: 6516 + /* 271 */ MCD_OPC_Decode, + 243, + 8, + 42, // Opcode: CMPU_LT_QB_MM + /* 275 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 296 + /* 280 */ MCD_OPC_CheckPredicate, + 8, + 87, + 24, + 0, // Skip to: 6516 + /* 285 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 80, + 24, + 0, // Skip to: 6516 + /* 292 */ MCD_OPC_Decode, + 241, + 8, + 42, // Opcode: CMPU_LE_QB_MM + /* 296 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 310 + /* 301 */ MCD_OPC_CheckPredicate, + 8, + 66, + 24, + 0, // Skip to: 6516 + /* 306 */ MCD_OPC_Decode, + 216, + 5, + 44, // Opcode: ADDQ_S_W_MM + /* 310 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 324 + /* 315 */ MCD_OPC_CheckPredicate, + 8, + 52, + 24, + 0, // Skip to: 6516 + /* 320 */ MCD_OPC_Decode, + 214, + 20, + 44, // Opcode: SUBQ_S_W_MM + /* 324 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 338 + /* 329 */ MCD_OPC_CheckPredicate, + 8, + 38, + 24, + 0, // Skip to: 6516 + /* 334 */ MCD_OPC_Decode, + 219, + 5, + 44, // Opcode: ADDSC_MM + /* 338 */ MCD_OPC_FilterValue, + 15, + 29, + 24, + 0, // Skip to: 6516 + /* 343 */ MCD_OPC_CheckPredicate, + 8, + 24, + 24, + 0, // Skip to: 6516 + /* 348 */ MCD_OPC_Decode, + 128, + 6, + 44, // Opcode: ADDWC_MM + /* 352 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 366 + /* 357 */ MCD_OPC_CheckPredicate, + 7, + 10, + 24, + 0, // Skip to: 6516 + /* 362 */ MCD_OPC_Decode, + 249, + 7, + 45, // Opcode: BREAK_MM + /* 366 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 380 + /* 371 */ MCD_OPC_CheckPredicate, + 6, + 252, + 23, + 0, // Skip to: 6516 + /* 376 */ MCD_OPC_Decode, + 236, + 13, + 46, // Opcode: INS_MM + /* 380 */ MCD_OPC_FilterValue, + 13, + 167, + 1, + 0, // Skip to: 808 + /* 385 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 388 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 402 + /* 393 */ MCD_OPC_CheckPredicate, + 8, + 230, + 23, + 0, // Skip to: 6516 + /* 398 */ MCD_OPC_Decode, + 212, + 5, + 47, // Opcode: ADDQ_PH_MM + /* 402 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 416 + /* 407 */ MCD_OPC_CheckPredicate, + 9, + 216, + 23, + 0, // Skip to: 6516 + /* 412 */ MCD_OPC_Decode, + 204, + 5, + 47, // Opcode: ADDQH_PH_MMR2 + /* 416 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 430 + /* 421 */ MCD_OPC_CheckPredicate, + 9, + 202, + 23, + 0, // Skip to: 6516 + /* 426 */ MCD_OPC_Decode, + 210, + 5, + 44, // Opcode: ADDQH_W_MMR2 + /* 430 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 444 + /* 435 */ MCD_OPC_CheckPredicate, + 8, + 188, + 23, + 0, // Skip to: 6516 + /* 440 */ MCD_OPC_Decode, + 242, + 5, + 47, // Opcode: ADDU_QB_MM + /* 444 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 458 + /* 449 */ MCD_OPC_CheckPredicate, + 9, + 174, + 23, + 0, // Skip to: 6516 + /* 454 */ MCD_OPC_Decode, + 240, + 5, + 47, // Opcode: ADDU_PH_MMR2 + /* 458 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 472 + /* 463 */ MCD_OPC_CheckPredicate, + 9, + 160, + 23, + 0, // Skip to: 6516 + /* 468 */ MCD_OPC_Decode, + 235, + 5, + 47, // Opcode: ADDUH_QB_MMR2 + /* 472 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 486 + /* 477 */ MCD_OPC_CheckPredicate, + 8, + 146, + 23, + 0, // Skip to: 6516 + /* 482 */ MCD_OPC_Decode, + 201, + 19, + 48, // Opcode: SHRAV_PH_MM + /* 486 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 500 + /* 491 */ MCD_OPC_CheckPredicate, + 9, + 132, + 23, + 0, // Skip to: 6516 + /* 496 */ MCD_OPC_Decode, + 203, + 19, + 48, // Opcode: SHRAV_QB_MMR2 + /* 500 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 514 + /* 505 */ MCD_OPC_CheckPredicate, + 8, + 118, + 23, + 0, // Skip to: 6516 + /* 510 */ MCD_OPC_Decode, + 210, + 20, + 47, // Opcode: SUBQ_PH_MM + /* 514 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 528 + /* 519 */ MCD_OPC_CheckPredicate, + 9, + 104, + 23, + 0, // Skip to: 6516 + /* 524 */ MCD_OPC_Decode, + 202, + 20, + 47, // Opcode: SUBQH_PH_MMR2 + /* 528 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 542 + /* 533 */ MCD_OPC_CheckPredicate, + 9, + 90, + 23, + 0, // Skip to: 6516 + /* 538 */ MCD_OPC_Decode, + 208, + 20, + 44, // Opcode: SUBQH_W_MMR2 + /* 542 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 556 + /* 547 */ MCD_OPC_CheckPredicate, + 8, + 76, + 23, + 0, // Skip to: 6516 + /* 552 */ MCD_OPC_Decode, + 241, + 20, + 47, // Opcode: SUBU_QB_MM + /* 556 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 570 + /* 561 */ MCD_OPC_CheckPredicate, + 9, + 62, + 23, + 0, // Skip to: 6516 + /* 566 */ MCD_OPC_Decode, + 239, + 20, + 47, // Opcode: SUBU_PH_MMR2 + /* 570 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 584 + /* 575 */ MCD_OPC_CheckPredicate, + 9, + 48, + 23, + 0, // Skip to: 6516 + /* 580 */ MCD_OPC_Decode, + 234, + 20, + 47, // Opcode: SUBUH_QB_MMR2 + /* 584 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 598 + /* 589 */ MCD_OPC_CheckPredicate, + 9, + 34, + 23, + 0, // Skip to: 6516 + /* 594 */ MCD_OPC_Decode, + 160, + 18, + 49, // Opcode: PRECR_SRA_PH_W_MMR2 + /* 598 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 612 + /* 603 */ MCD_OPC_CheckPredicate, + 8, + 20, + 23, + 0, // Skip to: 6516 + /* 608 */ MCD_OPC_Decode, + 214, + 5, + 47, // Opcode: ADDQ_S_PH_MM + /* 612 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 626 + /* 617 */ MCD_OPC_CheckPredicate, + 9, + 6, + 23, + 0, // Skip to: 6516 + /* 622 */ MCD_OPC_Decode, + 206, + 5, + 47, // Opcode: ADDQH_R_PH_MMR2 + /* 626 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 640 + /* 631 */ MCD_OPC_CheckPredicate, + 9, + 248, + 22, + 0, // Skip to: 6516 + /* 636 */ MCD_OPC_Decode, + 208, + 5, + 44, // Opcode: ADDQH_R_W_MMR2 + /* 640 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 654 + /* 645 */ MCD_OPC_CheckPredicate, + 8, + 234, + 22, + 0, // Skip to: 6516 + /* 650 */ MCD_OPC_Decode, + 246, + 5, + 47, // Opcode: ADDU_S_QB_MM + /* 654 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 668 + /* 659 */ MCD_OPC_CheckPredicate, + 9, + 220, + 22, + 0, // Skip to: 6516 + /* 664 */ MCD_OPC_Decode, + 244, + 5, + 47, // Opcode: ADDU_S_PH_MMR2 + /* 668 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 682 + /* 673 */ MCD_OPC_CheckPredicate, + 9, + 206, + 22, + 0, // Skip to: 6516 + /* 678 */ MCD_OPC_Decode, + 237, + 5, + 47, // Opcode: ADDUH_R_QB_MMR2 + /* 682 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 696 + /* 687 */ MCD_OPC_CheckPredicate, + 8, + 192, + 22, + 0, // Skip to: 6516 + /* 692 */ MCD_OPC_Decode, + 205, + 19, + 48, // Opcode: SHRAV_R_PH_MM + /* 696 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 710 + /* 701 */ MCD_OPC_CheckPredicate, + 9, + 178, + 22, + 0, // Skip to: 6516 + /* 706 */ MCD_OPC_Decode, + 207, + 19, + 48, // Opcode: SHRAV_R_QB_MMR2 + /* 710 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 724 + /* 715 */ MCD_OPC_CheckPredicate, + 8, + 164, + 22, + 0, // Skip to: 6516 + /* 720 */ MCD_OPC_Decode, + 212, + 20, + 47, // Opcode: SUBQ_S_PH_MM + /* 724 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 738 + /* 729 */ MCD_OPC_CheckPredicate, + 9, + 150, + 22, + 0, // Skip to: 6516 + /* 734 */ MCD_OPC_Decode, + 204, + 20, + 47, // Opcode: SUBQH_R_PH_MMR2 + /* 738 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 752 + /* 743 */ MCD_OPC_CheckPredicate, + 9, + 136, + 22, + 0, // Skip to: 6516 + /* 748 */ MCD_OPC_Decode, + 206, + 20, + 44, // Opcode: SUBQH_R_W_MMR2 + /* 752 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 766 + /* 757 */ MCD_OPC_CheckPredicate, + 8, + 122, + 22, + 0, // Skip to: 6516 + /* 762 */ MCD_OPC_Decode, + 245, + 20, + 47, // Opcode: SUBU_S_QB_MM + /* 766 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 780 + /* 771 */ MCD_OPC_CheckPredicate, + 9, + 108, + 22, + 0, // Skip to: 6516 + /* 776 */ MCD_OPC_Decode, + 243, + 20, + 47, // Opcode: SUBU_S_PH_MMR2 + /* 780 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 794 + /* 785 */ MCD_OPC_CheckPredicate, + 9, + 94, + 22, + 0, // Skip to: 6516 + /* 790 */ MCD_OPC_Decode, + 236, + 20, + 47, // Opcode: SUBUH_R_QB_MMR2 + /* 794 */ MCD_OPC_FilterValue, + 31, + 85, + 22, + 0, // Skip to: 6516 + /* 799 */ MCD_OPC_CheckPredicate, + 9, + 80, + 22, + 0, // Skip to: 6516 + /* 804 */ MCD_OPC_Decode, + 162, + 18, + 49, // Opcode: PRECR_SRA_R_PH_W_MMR2 + /* 808 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 844 + /* 813 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 816 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 830 + /* 821 */ MCD_OPC_CheckPredicate, + 8, + 58, + 22, + 0, // Skip to: 6516 + /* 826 */ MCD_OPC_Decode, + 185, + 19, + 48, // Opcode: SHLLV_PH_MM + /* 830 */ MCD_OPC_FilterValue, + 16, + 49, + 22, + 0, // Skip to: 6516 + /* 835 */ MCD_OPC_CheckPredicate, + 8, + 44, + 22, + 0, // Skip to: 6516 + /* 840 */ MCD_OPC_Decode, + 189, + 19, + 48, // Opcode: SHLLV_S_PH_MM + /* 844 */ MCD_OPC_FilterValue, + 16, + 213, + 0, + 0, // Skip to: 1062 + /* 849 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 852 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 866 + /* 857 */ MCD_OPC_CheckPredicate, + 7, + 22, + 22, + 0, // Skip to: 6516 + /* 862 */ MCD_OPC_Decode, + 250, + 19, + 50, // Opcode: SLLV_MM + /* 866 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 880 + /* 871 */ MCD_OPC_CheckPredicate, + 7, + 8, + 22, + 0, // Skip to: 6516 + /* 876 */ MCD_OPC_Decode, + 187, + 20, + 50, // Opcode: SRLV_MM + /* 880 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 894 + /* 885 */ MCD_OPC_CheckPredicate, + 7, + 250, + 21, + 0, // Skip to: 6516 + /* 890 */ MCD_OPC_Decode, + 165, + 20, + 50, // Opcode: SRAV_MM + /* 894 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 908 + /* 899 */ MCD_OPC_CheckPredicate, + 7, + 236, + 21, + 0, // Skip to: 6516 + /* 904 */ MCD_OPC_Decode, + 203, + 18, + 50, // Opcode: ROTRV_MM + /* 908 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 922 + /* 913 */ MCD_OPC_CheckPredicate, + 6, + 222, + 21, + 0, // Skip to: 6516 + /* 918 */ MCD_OPC_Decode, + 133, + 6, + 44, // Opcode: ADD_MM + /* 922 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 936 + /* 927 */ MCD_OPC_CheckPredicate, + 6, + 208, + 21, + 0, // Skip to: 6516 + /* 932 */ MCD_OPC_Decode, + 140, + 6, + 44, // Opcode: ADDu_MM + /* 936 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 950 + /* 941 */ MCD_OPC_CheckPredicate, + 6, + 194, + 21, + 0, // Skip to: 6516 + /* 946 */ MCD_OPC_Decode, + 254, + 20, + 44, // Opcode: SUB_MM + /* 950 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 964 + /* 955 */ MCD_OPC_CheckPredicate, + 6, + 180, + 21, + 0, // Skip to: 6516 + /* 960 */ MCD_OPC_Decode, + 129, + 21, + 44, // Opcode: SUBu_MM + /* 964 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 978 + /* 969 */ MCD_OPC_CheckPredicate, + 6, + 166, + 21, + 0, // Skip to: 6516 + /* 974 */ MCD_OPC_Decode, + 179, + 17, + 44, // Opcode: MUL_MM + /* 978 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 992 + /* 983 */ MCD_OPC_CheckPredicate, + 6, + 152, + 21, + 0, // Skip to: 6516 + /* 988 */ MCD_OPC_Decode, + 153, + 6, + 44, // Opcode: AND_MM + /* 992 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 1006 + /* 997 */ MCD_OPC_CheckPredicate, + 6, + 138, + 21, + 0, // Skip to: 6516 + /* 1002 */ MCD_OPC_Decode, + 226, + 17, + 44, // Opcode: OR_MM + /* 1006 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 1020 + /* 1011 */ MCD_OPC_CheckPredicate, + 6, + 124, + 21, + 0, // Skip to: 6516 + /* 1016 */ MCD_OPC_Decode, + 213, + 17, + 44, // Opcode: NOR_MM + /* 1020 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 1034 + /* 1025 */ MCD_OPC_CheckPredicate, + 6, + 110, + 21, + 0, // Skip to: 6516 + /* 1030 */ MCD_OPC_Decode, + 151, + 22, + 44, // Opcode: XOR_MM + /* 1034 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 1048 + /* 1039 */ MCD_OPC_CheckPredicate, + 7, + 96, + 21, + 0, // Skip to: 6516 + /* 1044 */ MCD_OPC_Decode, + 131, + 20, + 44, // Opcode: SLT_MM + /* 1048 */ MCD_OPC_FilterValue, + 14, + 87, + 21, + 0, // Skip to: 6516 + /* 1053 */ MCD_OPC_CheckPredicate, + 7, + 82, + 21, + 0, // Skip to: 6516 + /* 1058 */ MCD_OPC_Decode, + 140, + 20, + 44, // Opcode: SLTu_MM + /* 1062 */ MCD_OPC_FilterValue, + 21, + 199, + 0, + 0, // Skip to: 1266 + /* 1067 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1070 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 1084 + /* 1075 */ MCD_OPC_CheckPredicate, + 8, + 60, + 21, + 0, // Skip to: 6516 + /* 1080 */ MCD_OPC_Decode, + 147, + 17, + 47, // Opcode: MULEU_S_PH_QBL_MM + /* 1084 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 1098 + /* 1089 */ MCD_OPC_CheckPredicate, + 8, + 46, + 21, + 0, // Skip to: 6516 + /* 1094 */ MCD_OPC_Decode, + 149, + 17, + 47, // Opcode: MULEU_S_PH_QBR_MM + /* 1098 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1112 + /* 1103 */ MCD_OPC_CheckPredicate, + 8, + 32, + 21, + 0, // Skip to: 6516 + /* 1108 */ MCD_OPC_Decode, + 151, + 17, + 47, // Opcode: MULQ_RS_PH_MM + /* 1112 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 1126 + /* 1117 */ MCD_OPC_CheckPredicate, + 9, + 18, + 21, + 0, // Skip to: 6516 + /* 1122 */ MCD_OPC_Decode, + 155, + 17, + 47, // Opcode: MULQ_S_PH_MMR2 + /* 1126 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1140 + /* 1131 */ MCD_OPC_CheckPredicate, + 9, + 4, + 21, + 0, // Skip to: 6516 + /* 1136 */ MCD_OPC_Decode, + 153, + 17, + 44, // Opcode: MULQ_RS_W_MMR2 + /* 1140 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 1154 + /* 1145 */ MCD_OPC_CheckPredicate, + 9, + 246, + 20, + 0, // Skip to: 6516 + /* 1150 */ MCD_OPC_Decode, + 157, + 17, + 44, // Opcode: MULQ_S_W_MMR2 + /* 1154 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 1168 + /* 1159 */ MCD_OPC_CheckPredicate, + 9, + 232, + 20, + 0, // Skip to: 6516 + /* 1164 */ MCD_OPC_Decode, + 160, + 6, + 51, // Opcode: APPEND_MMR2 + /* 1168 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 1182 + /* 1173 */ MCD_OPC_CheckPredicate, + 9, + 218, + 20, + 0, // Skip to: 6516 + /* 1178 */ MCD_OPC_Decode, + 171, + 18, + 51, // Opcode: PREPEND_MMR2 + /* 1182 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 1196 + /* 1187 */ MCD_OPC_CheckPredicate, + 8, + 204, + 20, + 0, // Skip to: 6516 + /* 1192 */ MCD_OPC_Decode, + 145, + 16, + 44, // Opcode: MODSUB_MM + /* 1196 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 1210 + /* 1201 */ MCD_OPC_CheckPredicate, + 8, + 190, + 20, + 0, // Skip to: 6516 + /* 1206 */ MCD_OPC_Decode, + 209, + 19, + 50, // Opcode: SHRAV_R_W_MM + /* 1210 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 1224 + /* 1215 */ MCD_OPC_CheckPredicate, + 9, + 176, + 20, + 0, // Skip to: 6516 + /* 1220 */ MCD_OPC_Decode, + 221, + 19, + 48, // Opcode: SHRLV_PH_MMR2 + /* 1224 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 1238 + /* 1229 */ MCD_OPC_CheckPredicate, + 8, + 162, + 20, + 0, // Skip to: 6516 + /* 1234 */ MCD_OPC_Decode, + 223, + 19, + 48, // Opcode: SHRLV_QB_MM + /* 1238 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 1252 + /* 1243 */ MCD_OPC_CheckPredicate, + 8, + 148, + 20, + 0, // Skip to: 6516 + /* 1248 */ MCD_OPC_Decode, + 187, + 19, + 48, // Opcode: SHLLV_QB_MM + /* 1252 */ MCD_OPC_FilterValue, + 15, + 139, + 20, + 0, // Skip to: 6516 + /* 1257 */ MCD_OPC_CheckPredicate, + 8, + 134, + 20, + 0, // Skip to: 6516 + /* 1262 */ MCD_OPC_Decode, + 191, + 19, + 50, // Opcode: SHLLV_S_W_MM + /* 1266 */ MCD_OPC_FilterValue, + 24, + 45, + 0, + 0, // Skip to: 1316 + /* 1271 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1274 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1288 + /* 1279 */ MCD_OPC_CheckPredicate, + 6, + 112, + 20, + 0, // Skip to: 6516 + /* 1284 */ MCD_OPC_Decode, + 179, + 16, + 52, // Opcode: MOVN_I_MM + /* 1288 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1302 + /* 1293 */ MCD_OPC_CheckPredicate, + 6, + 98, + 20, + 0, // Skip to: 6516 + /* 1298 */ MCD_OPC_Decode, + 199, + 16, + 52, // Opcode: MOVZ_I_MM + /* 1302 */ MCD_OPC_FilterValue, + 4, + 89, + 20, + 0, // Skip to: 6516 + /* 1307 */ MCD_OPC_CheckPredicate, + 7, + 84, + 20, + 0, // Skip to: 6516 + /* 1312 */ MCD_OPC_Decode, + 135, + 15, + 53, // Opcode: LWXS_MM + /* 1316 */ MCD_OPC_FilterValue, + 29, + 23, + 0, + 0, // Skip to: 1344 + /* 1321 */ MCD_OPC_CheckPredicate, + 8, + 70, + 20, + 0, // Skip to: 6516 + /* 1326 */ MCD_OPC_CheckField, + 22, + 4, + 0, + 63, + 20, + 0, // Skip to: 6516 + /* 1333 */ MCD_OPC_CheckField, + 6, + 8, + 0, + 56, + 20, + 0, // Skip to: 6516 + /* 1340 */ MCD_OPC_Decode, + 183, + 19, + 54, // Opcode: SHILO_MM + /* 1344 */ MCD_OPC_FilterValue, + 37, + 73, + 0, + 0, // Skip to: 1422 + /* 1349 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1352 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1366 + /* 1357 */ MCD_OPC_CheckPredicate, + 8, + 34, + 20, + 0, // Skip to: 6516 + /* 1362 */ MCD_OPC_Decode, + 143, + 17, + 43, // Opcode: MULEQ_S_W_PHL_MM + /* 1366 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1380 + /* 1371 */ MCD_OPC_CheckPredicate, + 8, + 20, + 20, + 0, // Skip to: 6516 + /* 1376 */ MCD_OPC_Decode, + 145, + 17, + 43, // Opcode: MULEQ_S_W_PHR_MM + /* 1380 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 1394 + /* 1385 */ MCD_OPC_CheckPredicate, + 8, + 6, + 20, + 0, // Skip to: 6516 + /* 1390 */ MCD_OPC_Decode, + 198, + 14, + 53, // Opcode: LHX_MM + /* 1394 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1408 + /* 1399 */ MCD_OPC_CheckPredicate, + 8, + 248, + 19, + 0, // Skip to: 6516 + /* 1404 */ MCD_OPC_Decode, + 136, + 15, + 53, // Opcode: LWX_MM + /* 1408 */ MCD_OPC_FilterValue, + 8, + 239, + 19, + 0, // Skip to: 6516 + /* 1413 */ MCD_OPC_CheckPredicate, + 8, + 234, + 19, + 0, // Skip to: 6516 + /* 1418 */ MCD_OPC_Decode, + 158, + 14, + 53, // Opcode: LBUX_MM + /* 1422 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 1436 + /* 1427 */ MCD_OPC_CheckPredicate, + 6, + 220, + 19, + 0, // Skip to: 6516 + /* 1432 */ MCD_OPC_Decode, + 136, + 12, + 55, // Opcode: EXT_MM + /* 1436 */ MCD_OPC_FilterValue, + 45, + 143, + 0, + 0, // Skip to: 1584 + /* 1441 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1444 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1458 + /* 1449 */ MCD_OPC_CheckPredicate, + 9, + 198, + 19, + 0, // Skip to: 6516 + /* 1454 */ MCD_OPC_Decode, + 182, + 17, + 47, // Opcode: MUL_PH_MMR2 + /* 1458 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1472 + /* 1463 */ MCD_OPC_CheckPredicate, + 9, + 184, + 19, + 0, // Skip to: 6516 + /* 1468 */ MCD_OPC_Decode, + 158, + 18, + 47, // Opcode: PRECR_QB_PH_MMR2 + /* 1472 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 1486 + /* 1477 */ MCD_OPC_CheckPredicate, + 8, + 170, + 19, + 0, // Skip to: 6516 + /* 1482 */ MCD_OPC_Decode, + 154, + 18, + 47, // Opcode: PRECRQ_QB_PH_MM + /* 1486 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 1500 + /* 1491 */ MCD_OPC_CheckPredicate, + 8, + 156, + 19, + 0, // Skip to: 6516 + /* 1496 */ MCD_OPC_Decode, + 152, + 18, + 56, // Opcode: PRECRQ_PH_W_MM + /* 1500 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1514 + /* 1505 */ MCD_OPC_CheckPredicate, + 8, + 142, + 19, + 0, // Skip to: 6516 + /* 1510 */ MCD_OPC_Decode, + 156, + 18, + 56, // Opcode: PRECRQ_RS_PH_W_MM + /* 1514 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 1528 + /* 1519 */ MCD_OPC_CheckPredicate, + 8, + 128, + 19, + 0, // Skip to: 6516 + /* 1524 */ MCD_OPC_Decode, + 150, + 18, + 47, // Opcode: PRECRQU_S_QB_PH_MM + /* 1528 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1542 + /* 1533 */ MCD_OPC_CheckPredicate, + 8, + 114, + 19, + 0, // Skip to: 6516 + /* 1538 */ MCD_OPC_Decode, + 234, + 17, + 47, // Opcode: PACKRL_PH_MM + /* 1542 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 1556 + /* 1547 */ MCD_OPC_CheckPredicate, + 8, + 100, + 19, + 0, // Skip to: 6516 + /* 1552 */ MCD_OPC_Decode, + 253, + 17, + 47, // Opcode: PICK_QB_MM + /* 1556 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 1570 + /* 1561 */ MCD_OPC_CheckPredicate, + 8, + 86, + 19, + 0, // Skip to: 6516 + /* 1566 */ MCD_OPC_Decode, + 251, + 17, + 47, // Opcode: PICK_PH_MM + /* 1570 */ MCD_OPC_FilterValue, + 16, + 77, + 19, + 0, // Skip to: 6516 + /* 1575 */ MCD_OPC_CheckPredicate, + 9, + 72, + 19, + 0, // Skip to: 6516 + /* 1580 */ MCD_OPC_Decode, + 187, + 17, + 47, // Opcode: MUL_S_PH_MMR2 + /* 1584 */ MCD_OPC_FilterValue, + 52, + 45, + 0, + 0, // Skip to: 1634 + /* 1589 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1592 */ MCD_OPC_FilterValue, + 19, + 16, + 0, + 0, // Skip to: 1613 + /* 1597 */ MCD_OPC_CheckPredicate, + 10, + 50, + 19, + 0, // Skip to: 6516 + /* 1602 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 43, + 19, + 0, // Skip to: 6516 + /* 1609 */ MCD_OPC_Decode, + 229, + 15, + 57, // Opcode: MFHGC0_MM + /* 1613 */ MCD_OPC_FilterValue, + 27, + 34, + 19, + 0, // Skip to: 6516 + /* 1618 */ MCD_OPC_CheckPredicate, + 10, + 29, + 19, + 0, // Skip to: 6516 + /* 1623 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 22, + 19, + 0, // Skip to: 6516 + /* 1630 */ MCD_OPC_Decode, + 245, + 16, + 58, // Opcode: MTHGC0_MM + /* 1634 */ MCD_OPC_FilterValue, + 53, + 109, + 0, + 0, // Skip to: 1748 + /* 1639 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1642 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 1656 + /* 1647 */ MCD_OPC_CheckPredicate, + 8, + 0, + 19, + 0, // Skip to: 6516 + /* 1652 */ MCD_OPC_Decode, + 219, + 19, + 41, // Opcode: SHRA_R_W_MM + /* 1656 */ MCD_OPC_FilterValue, + 12, + 16, + 0, + 0, // Skip to: 1677 + /* 1661 */ MCD_OPC_CheckPredicate, + 8, + 242, + 18, + 0, // Skip to: 6516 + /* 1666 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 235, + 18, + 0, // Skip to: 6516 + /* 1673 */ MCD_OPC_Decode, + 211, + 19, + 59, // Opcode: SHRA_PH_MM + /* 1677 */ MCD_OPC_FilterValue, + 14, + 31, + 0, + 0, // Skip to: 1713 + /* 1682 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 1685 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1699 + /* 1690 */ MCD_OPC_CheckPredicate, + 8, + 213, + 18, + 0, // Skip to: 6516 + /* 1695 */ MCD_OPC_Decode, + 193, + 19, + 59, // Opcode: SHLL_PH_MM + /* 1699 */ MCD_OPC_FilterValue, + 1, + 204, + 18, + 0, // Skip to: 6516 + /* 1704 */ MCD_OPC_CheckPredicate, + 8, + 199, + 18, + 0, // Skip to: 6516 + /* 1709 */ MCD_OPC_Decode, + 197, + 19, + 59, // Opcode: SHLL_S_PH_MM + /* 1713 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 1727 + /* 1718 */ MCD_OPC_CheckPredicate, + 8, + 185, + 18, + 0, // Skip to: 6516 + /* 1723 */ MCD_OPC_Decode, + 199, + 19, + 41, // Opcode: SHLL_S_W_MM + /* 1727 */ MCD_OPC_FilterValue, + 28, + 176, + 18, + 0, // Skip to: 6516 + /* 1732 */ MCD_OPC_CheckPredicate, + 8, + 171, + 18, + 0, // Skip to: 6516 + /* 1737 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 164, + 18, + 0, // Skip to: 6516 + /* 1744 */ MCD_OPC_Decode, + 215, + 19, + 59, // Opcode: SHRA_R_PH_MM + /* 1748 */ MCD_OPC_FilterValue, + 60, + 8, + 8, + 0, // Skip to: 3809 + /* 1753 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1756 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 1792 + /* 1761 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 1764 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1778 + /* 1769 */ MCD_OPC_CheckPredicate, + 7, + 134, + 18, + 0, // Skip to: 6516 + /* 1774 */ MCD_OPC_Decode, + 199, + 21, + 60, // Opcode: TEQ_MM + /* 1778 */ MCD_OPC_FilterValue, + 1, + 125, + 18, + 0, // Skip to: 6516 + /* 1783 */ MCD_OPC_CheckPredicate, + 7, + 120, + 18, + 0, // Skip to: 6516 + /* 1788 */ MCD_OPC_Decode, + 238, + 21, + 60, // Opcode: TLT_MM + /* 1792 */ MCD_OPC_FilterValue, + 1, + 131, + 0, + 0, // Skip to: 1928 + /* 1797 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 1800 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 1850 + /* 1805 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1808 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1829 + /* 1813 */ MCD_OPC_CheckPredicate, + 8, + 90, + 18, + 0, // Skip to: 6516 + /* 1818 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 83, + 18, + 0, // Skip to: 6516 + /* 1825 */ MCD_OPC_Decode, + 234, + 15, + 61, // Opcode: MFHI_DSP_MM + /* 1829 */ MCD_OPC_FilterValue, + 1, + 74, + 18, + 0, // Skip to: 6516 + /* 1834 */ MCD_OPC_CheckPredicate, + 8, + 69, + 18, + 0, // Skip to: 6516 + /* 1839 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 62, + 18, + 0, // Skip to: 6516 + /* 1846 */ MCD_OPC_Decode, + 249, + 16, + 62, // Opcode: MTHI_DSP_MM + /* 1850 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1864 + /* 1855 */ MCD_OPC_CheckPredicate, + 8, + 48, + 18, + 0, // Skip to: 6516 + /* 1860 */ MCD_OPC_Decode, + 195, + 19, + 63, // Opcode: SHLL_QB_MM + /* 1864 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 1914 + /* 1869 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1872 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 1893 + /* 1877 */ MCD_OPC_CheckPredicate, + 8, + 26, + 18, + 0, // Skip to: 6516 + /* 1882 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 19, + 18, + 0, // Skip to: 6516 + /* 1889 */ MCD_OPC_Decode, + 240, + 15, + 61, // Opcode: MFLO_DSP_MM + /* 1893 */ MCD_OPC_FilterValue, + 1, + 10, + 18, + 0, // Skip to: 6516 + /* 1898 */ MCD_OPC_CheckPredicate, + 8, + 5, + 18, + 0, // Skip to: 6516 + /* 1903 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 254, + 17, + 0, // Skip to: 6516 + /* 1910 */ MCD_OPC_Decode, + 128, + 17, + 64, // Opcode: MTLO_DSP_MM + /* 1914 */ MCD_OPC_FilterValue, + 3, + 245, + 17, + 0, // Skip to: 6516 + /* 1919 */ MCD_OPC_CheckPredicate, + 8, + 240, + 17, + 0, // Skip to: 6516 + /* 1924 */ MCD_OPC_Decode, + 227, + 19, + 63, // Opcode: SHRL_QB_MM + /* 1928 */ MCD_OPC_FilterValue, + 2, + 101, + 0, + 0, // Skip to: 2034 + /* 1933 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 1936 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1950 + /* 1941 */ MCD_OPC_CheckPredicate, + 9, + 218, + 17, + 0, // Skip to: 6516 + /* 1946 */ MCD_OPC_Decode, + 174, + 11, + 65, // Opcode: DPA_W_PH_MMR2 + /* 1950 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1964 + /* 1955 */ MCD_OPC_CheckPredicate, + 9, + 204, + 17, + 0, // Skip to: 6516 + /* 1960 */ MCD_OPC_Decode, + 204, + 6, + 66, // Opcode: BALIGN_MMR2 + /* 1964 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 1978 + /* 1969 */ MCD_OPC_CheckPredicate, + 9, + 190, + 17, + 0, // Skip to: 6516 + /* 1974 */ MCD_OPC_Decode, + 172, + 11, + 65, // Opcode: DPAX_W_PH_MMR2 + /* 1978 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1992 + /* 1983 */ MCD_OPC_CheckPredicate, + 8, + 176, + 17, + 0, // Skip to: 6516 + /* 1988 */ MCD_OPC_Decode, + 168, + 11, + 65, // Opcode: DPAU_H_QBL_MM + /* 1992 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2006 + /* 1997 */ MCD_OPC_CheckPredicate, + 8, + 162, + 17, + 0, // Skip to: 6516 + /* 2002 */ MCD_OPC_Decode, + 244, + 11, + 67, // Opcode: EXTPV_MM + /* 2006 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2020 + /* 2011 */ MCD_OPC_CheckPredicate, + 8, + 148, + 17, + 0, // Skip to: 6516 + /* 2016 */ MCD_OPC_Decode, + 170, + 11, + 65, // Opcode: DPAU_H_QBR_MM + /* 2020 */ MCD_OPC_FilterValue, + 7, + 139, + 17, + 0, // Skip to: 6516 + /* 2025 */ MCD_OPC_CheckPredicate, + 8, + 134, + 17, + 0, // Skip to: 6516 + /* 2030 */ MCD_OPC_Decode, + 241, + 11, + 67, // Opcode: EXTPDPV_MM + /* 2034 */ MCD_OPC_FilterValue, + 4, + 171, + 0, + 0, // Skip to: 2210 + /* 2039 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2042 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2056 + /* 2047 */ MCD_OPC_CheckPredicate, + 9, + 112, + 17, + 0, // Skip to: 6516 + /* 2052 */ MCD_OPC_Decode, + 191, + 5, + 68, // Opcode: ABSQ_S_QB_MMR2 + /* 2056 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2070 + /* 2061 */ MCD_OPC_CheckPredicate, + 8, + 98, + 17, + 0, // Skip to: 6516 + /* 2066 */ MCD_OPC_Decode, + 189, + 5, + 68, // Opcode: ABSQ_S_PH_MM + /* 2070 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 2084 + /* 2075 */ MCD_OPC_CheckPredicate, + 8, + 84, + 17, + 0, // Skip to: 6516 + /* 2080 */ MCD_OPC_Decode, + 193, + 5, + 69, // Opcode: ABSQ_S_W_MM + /* 2084 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2098 + /* 2089 */ MCD_OPC_CheckPredicate, + 8, + 70, + 17, + 0, // Skip to: 6516 + /* 2094 */ MCD_OPC_Decode, + 176, + 7, + 69, // Opcode: BITREV_MM + /* 2098 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 2112 + /* 2103 */ MCD_OPC_CheckPredicate, + 8, + 56, + 17, + 0, // Skip to: 6516 + /* 2108 */ MCD_OPC_Decode, + 235, + 13, + 70, // Opcode: INSV_MM + /* 2112 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 2126 + /* 2117 */ MCD_OPC_CheckPredicate, + 8, + 42, + 17, + 0, // Skip to: 6516 + /* 2122 */ MCD_OPC_Decode, + 138, + 18, + 71, // Opcode: PRECEQ_W_PHL_MM + /* 2126 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 2140 + /* 2131 */ MCD_OPC_CheckPredicate, + 8, + 28, + 17, + 0, // Skip to: 6516 + /* 2136 */ MCD_OPC_Decode, + 140, + 18, + 71, // Opcode: PRECEQ_W_PHR_MM + /* 2140 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 2154 + /* 2145 */ MCD_OPC_CheckPredicate, + 8, + 14, + 17, + 0, // Skip to: 6516 + /* 2150 */ MCD_OPC_Decode, + 132, + 18, + 68, // Opcode: PRECEQU_PH_QBL_MM + /* 2154 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 2168 + /* 2159 */ MCD_OPC_CheckPredicate, + 8, + 0, + 17, + 0, // Skip to: 6516 + /* 2164 */ MCD_OPC_Decode, + 136, + 18, + 68, // Opcode: PRECEQU_PH_QBR_MM + /* 2168 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 2182 + /* 2173 */ MCD_OPC_CheckPredicate, + 8, + 242, + 16, + 0, // Skip to: 6516 + /* 2178 */ MCD_OPC_Decode, + 144, + 18, + 68, // Opcode: PRECEU_PH_QBL_MM + /* 2182 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 2196 + /* 2187 */ MCD_OPC_CheckPredicate, + 8, + 228, + 16, + 0, // Skip to: 6516 + /* 2192 */ MCD_OPC_Decode, + 148, + 18, + 68, // Opcode: PRECEU_PH_QBR_MM + /* 2196 */ MCD_OPC_FilterValue, + 30, + 219, + 16, + 0, // Skip to: 6516 + /* 2201 */ MCD_OPC_CheckPredicate, + 8, + 214, + 16, + 0, // Skip to: 6516 + /* 2206 */ MCD_OPC_Decode, + 175, + 18, + 71, // Opcode: RADDU_W_QB_MM + /* 2210 */ MCD_OPC_FilterValue, + 5, + 87, + 0, + 0, // Skip to: 2302 + /* 2215 */ MCD_OPC_ExtractField, + 11, + 15, // Inst{25-11} ... + /* 2218 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2232 + /* 2223 */ MCD_OPC_CheckPredicate, + 10, + 192, + 16, + 0, // Skip to: 6516 + /* 2228 */ MCD_OPC_Decode, + 213, + 21, + 0, // Opcode: TLBGP_MM + /* 2232 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2246 + /* 2237 */ MCD_OPC_CheckPredicate, + 10, + 178, + 16, + 0, // Skip to: 6516 + /* 2242 */ MCD_OPC_Decode, + 215, + 21, + 0, // Opcode: TLBGR_MM + /* 2246 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 2260 + /* 2251 */ MCD_OPC_CheckPredicate, + 10, + 164, + 16, + 0, // Skip to: 6516 + /* 2256 */ MCD_OPC_Decode, + 217, + 21, + 0, // Opcode: TLBGWI_MM + /* 2260 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2274 + /* 2265 */ MCD_OPC_CheckPredicate, + 10, + 150, + 16, + 0, // Skip to: 6516 + /* 2270 */ MCD_OPC_Decode, + 219, + 21, + 0, // Opcode: TLBGWR_MM + /* 2274 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 2288 + /* 2279 */ MCD_OPC_CheckPredicate, + 10, + 136, + 16, + 0, // Skip to: 6516 + /* 2284 */ MCD_OPC_Decode, + 211, + 21, + 0, // Opcode: TLBGINV_MM + /* 2288 */ MCD_OPC_FilterValue, + 10, + 127, + 16, + 0, // Skip to: 6516 + /* 2293 */ MCD_OPC_CheckPredicate, + 10, + 122, + 16, + 0, // Skip to: 6516 + /* 2298 */ MCD_OPC_Decode, + 210, + 21, + 0, // Opcode: TLBGINVF_MM + /* 2302 */ MCD_OPC_FilterValue, + 7, + 31, + 0, + 0, // Skip to: 2338 + /* 2307 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 2310 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2324 + /* 2315 */ MCD_OPC_CheckPredicate, + 9, + 100, + 16, + 0, // Skip to: 6516 + /* 2320 */ MCD_OPC_Decode, + 213, + 19, + 63, // Opcode: SHRA_QB_MMR2 + /* 2324 */ MCD_OPC_FilterValue, + 2, + 91, + 16, + 0, // Skip to: 6516 + /* 2329 */ MCD_OPC_CheckPredicate, + 9, + 86, + 16, + 0, // Skip to: 6516 + /* 2334 */ MCD_OPC_Decode, + 217, + 19, + 63, // Opcode: SHRA_R_QB_MMR2 + /* 2338 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 2374 + /* 2343 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 2346 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2360 + /* 2351 */ MCD_OPC_CheckPredicate, + 7, + 64, + 16, + 0, // Skip to: 6516 + /* 2356 */ MCD_OPC_Decode, + 207, + 21, + 60, // Opcode: TGE_MM + /* 2360 */ MCD_OPC_FilterValue, + 1, + 55, + 16, + 0, // Skip to: 6516 + /* 2365 */ MCD_OPC_CheckPredicate, + 7, + 50, + 16, + 0, // Skip to: 6516 + /* 2370 */ MCD_OPC_Decode, + 237, + 21, + 60, // Opcode: TLTU_MM + /* 2374 */ MCD_OPC_FilterValue, + 9, + 101, + 0, + 0, // Skip to: 2480 + /* 2379 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 2382 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 2403 + /* 2387 */ MCD_OPC_CheckPredicate, + 8, + 28, + 16, + 0, // Skip to: 6516 + /* 2392 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 21, + 16, + 0, // Skip to: 6516 + /* 2399 */ MCD_OPC_Decode, + 252, + 16, + 72, // Opcode: MTHLIP_MM + /* 2403 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2417 + /* 2408 */ MCD_OPC_CheckPredicate, + 8, + 7, + 16, + 0, // Skip to: 6516 + /* 2413 */ MCD_OPC_Decode, + 183, + 15, + 65, // Opcode: MAQ_S_W_PHR_MM + /* 2417 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 2438 + /* 2422 */ MCD_OPC_CheckPredicate, + 8, + 249, + 15, + 0, // Skip to: 6516 + /* 2427 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 242, + 15, + 0, // Skip to: 6516 + /* 2434 */ MCD_OPC_Decode, + 182, + 19, + 72, // Opcode: SHILOV_MM + /* 2438 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 2452 + /* 2443 */ MCD_OPC_CheckPredicate, + 8, + 228, + 15, + 0, // Skip to: 6516 + /* 2448 */ MCD_OPC_Decode, + 181, + 15, + 65, // Opcode: MAQ_S_W_PHL_MM + /* 2452 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2466 + /* 2457 */ MCD_OPC_CheckPredicate, + 8, + 214, + 15, + 0, // Skip to: 6516 + /* 2462 */ MCD_OPC_Decode, + 179, + 15, + 65, // Opcode: MAQ_SA_W_PHR_MM + /* 2466 */ MCD_OPC_FilterValue, + 7, + 205, + 15, + 0, // Skip to: 6516 + /* 2471 */ MCD_OPC_CheckPredicate, + 8, + 200, + 15, + 0, // Skip to: 6516 + /* 2476 */ MCD_OPC_Decode, + 177, + 15, + 65, // Opcode: MAQ_SA_W_PHL_MM + /* 2480 */ MCD_OPC_FilterValue, + 10, + 115, + 0, + 0, // Skip to: 2600 + /* 2485 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 2488 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2502 + /* 2493 */ MCD_OPC_CheckPredicate, + 8, + 178, + 15, + 0, // Skip to: 6516 + /* 2498 */ MCD_OPC_Decode, + 166, + 11, + 65, // Opcode: DPAQ_S_W_PH_MM + /* 2502 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2516 + /* 2507 */ MCD_OPC_CheckPredicate, + 8, + 164, + 15, + 0, // Skip to: 6516 + /* 2512 */ MCD_OPC_Decode, + 170, + 15, + 65, // Opcode: MADD_DSP_MM + /* 2516 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2530 + /* 2521 */ MCD_OPC_CheckPredicate, + 8, + 150, + 15, + 0, // Skip to: 6516 + /* 2526 */ MCD_OPC_Decode, + 164, + 11, + 65, // Opcode: DPAQ_SA_L_W_MM + /* 2530 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 2544 + /* 2535 */ MCD_OPC_CheckPredicate, + 8, + 136, + 15, + 0, // Skip to: 6516 + /* 2540 */ MCD_OPC_Decode, + 160, + 15, + 65, // Opcode: MADDU_DSP_MM + /* 2544 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 2558 + /* 2549 */ MCD_OPC_CheckPredicate, + 9, + 122, + 15, + 0, // Skip to: 6516 + /* 2554 */ MCD_OPC_Decode, + 162, + 11, + 65, // Opcode: DPAQX_S_W_PH_MMR2 + /* 2558 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2572 + /* 2563 */ MCD_OPC_CheckPredicate, + 8, + 108, + 15, + 0, // Skip to: 6516 + /* 2568 */ MCD_OPC_Decode, + 221, + 16, + 65, // Opcode: MSUB_DSP_MM + /* 2572 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2586 + /* 2577 */ MCD_OPC_CheckPredicate, + 9, + 94, + 15, + 0, // Skip to: 6516 + /* 2582 */ MCD_OPC_Decode, + 160, + 11, + 65, // Opcode: DPAQX_SA_W_PH_MMR2 + /* 2586 */ MCD_OPC_FilterValue, + 7, + 85, + 15, + 0, // Skip to: 6516 + /* 2591 */ MCD_OPC_CheckPredicate, + 8, + 80, + 15, + 0, // Skip to: 6516 + /* 2596 */ MCD_OPC_Decode, + 211, + 16, + 65, // Opcode: MSUBU_DSP_MM + /* 2600 */ MCD_OPC_FilterValue, + 12, + 27, + 1, + 0, // Skip to: 2888 + /* 2605 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2608 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2622 + /* 2613 */ MCD_OPC_CheckPredicate, + 8, + 58, + 15, + 0, // Skip to: 6516 + /* 2618 */ MCD_OPC_Decode, + 190, + 18, + 73, // Opcode: REPLV_PH_MM + /* 2622 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2636 + /* 2627 */ MCD_OPC_CheckPredicate, + 8, + 44, + 15, + 0, // Skip to: 6516 + /* 2632 */ MCD_OPC_Decode, + 192, + 18, + 73, // Opcode: REPLV_QB_MM + /* 2636 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2650 + /* 2641 */ MCD_OPC_CheckPredicate, + 7, + 30, + 15, + 0, // Skip to: 6516 + /* 2646 */ MCD_OPC_Decode, + 147, + 19, + 69, // Opcode: SEB_MM + /* 2650 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 2664 + /* 2655 */ MCD_OPC_CheckPredicate, + 7, + 16, + 15, + 0, // Skip to: 6516 + /* 2660 */ MCD_OPC_Decode, + 150, + 19, + 69, // Opcode: SEH_MM + /* 2664 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 2678 + /* 2669 */ MCD_OPC_CheckPredicate, + 7, + 2, + 15, + 0, // Skip to: 6516 + /* 2674 */ MCD_OPC_Decode, + 203, + 8, + 69, // Opcode: CLO_MM + /* 2678 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 2692 + /* 2683 */ MCD_OPC_CheckPredicate, + 7, + 244, + 14, + 0, // Skip to: 6516 + /* 2688 */ MCD_OPC_Decode, + 223, + 8, + 69, // Opcode: CLZ_MM + /* 2692 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 2706 + /* 2697 */ MCD_OPC_CheckPredicate, + 6, + 230, + 14, + 0, // Skip to: 6516 + /* 2702 */ MCD_OPC_Decode, + 180, + 18, + 74, // Opcode: RDHWR_MM + /* 2706 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 2720 + /* 2711 */ MCD_OPC_CheckPredicate, + 8, + 216, + 14, + 0, // Skip to: 6516 + /* 2716 */ MCD_OPC_Decode, + 131, + 18, + 68, // Opcode: PRECEQU_PH_QBLA_MM + /* 2720 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 2734 + /* 2725 */ MCD_OPC_CheckPredicate, + 7, + 202, + 14, + 0, // Skip to: 6516 + /* 2730 */ MCD_OPC_Decode, + 143, + 22, + 69, // Opcode: WSBH_MM + /* 2734 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 2748 + /* 2739 */ MCD_OPC_CheckPredicate, + 6, + 188, + 14, + 0, // Skip to: 6516 + /* 2744 */ MCD_OPC_Decode, + 170, + 17, + 75, // Opcode: MULT_MM + /* 2748 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 2762 + /* 2753 */ MCD_OPC_CheckPredicate, + 8, + 174, + 14, + 0, // Skip to: 6516 + /* 2758 */ MCD_OPC_Decode, + 135, + 18, + 68, // Opcode: PRECEQU_PH_QBRA_MM + /* 2762 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 2776 + /* 2767 */ MCD_OPC_CheckPredicate, + 6, + 160, + 14, + 0, // Skip to: 6516 + /* 2772 */ MCD_OPC_Decode, + 172, + 17, + 75, // Opcode: MULTu_MM + /* 2776 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 2790 + /* 2781 */ MCD_OPC_CheckPredicate, + 6, + 146, + 14, + 0, // Skip to: 6516 + /* 2786 */ MCD_OPC_Decode, + 140, + 19, + 75, // Opcode: SDIV_MM + /* 2790 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 2804 + /* 2795 */ MCD_OPC_CheckPredicate, + 8, + 132, + 14, + 0, // Skip to: 6516 + /* 2800 */ MCD_OPC_Decode, + 143, + 18, + 68, // Opcode: PRECEU_PH_QBLA_MM + /* 2804 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 2818 + /* 2809 */ MCD_OPC_CheckPredicate, + 6, + 118, + 14, + 0, // Skip to: 6516 + /* 2814 */ MCD_OPC_Decode, + 128, + 22, + 75, // Opcode: UDIV_MM + /* 2818 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 2832 + /* 2823 */ MCD_OPC_CheckPredicate, + 6, + 104, + 14, + 0, // Skip to: 6516 + /* 2828 */ MCD_OPC_Decode, + 171, + 15, + 75, // Opcode: MADD_MM + /* 2832 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 2846 + /* 2837 */ MCD_OPC_CheckPredicate, + 8, + 90, + 14, + 0, // Skip to: 6516 + /* 2842 */ MCD_OPC_Decode, + 147, + 18, + 68, // Opcode: PRECEU_PH_QBRA_MM + /* 2846 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 2860 + /* 2851 */ MCD_OPC_CheckPredicate, + 6, + 76, + 14, + 0, // Skip to: 6516 + /* 2856 */ MCD_OPC_Decode, + 161, + 15, + 75, // Opcode: MADDU_MM + /* 2860 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 2874 + /* 2865 */ MCD_OPC_CheckPredicate, + 6, + 62, + 14, + 0, // Skip to: 6516 + /* 2870 */ MCD_OPC_Decode, + 222, + 16, + 75, // Opcode: MSUB_MM + /* 2874 */ MCD_OPC_FilterValue, + 31, + 53, + 14, + 0, // Skip to: 6516 + /* 2879 */ MCD_OPC_CheckPredicate, + 6, + 48, + 14, + 0, // Skip to: 6516 + /* 2884 */ MCD_OPC_Decode, + 212, + 16, + 75, // Opcode: MSUBU_MM + /* 2888 */ MCD_OPC_FilterValue, + 13, + 206, + 0, + 0, // Skip to: 3099 + /* 2893 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2896 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 2917 + /* 2901 */ MCD_OPC_CheckPredicate, + 7, + 26, + 14, + 0, // Skip to: 6516 + /* 2906 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 19, + 14, + 0, // Skip to: 6516 + /* 2913 */ MCD_OPC_Decode, + 225, + 21, + 0, // Opcode: TLBP_MM + /* 2917 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 2938 + /* 2922 */ MCD_OPC_CheckPredicate, + 7, + 5, + 14, + 0, // Skip to: 6516 + /* 2927 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 254, + 13, + 0, // Skip to: 6516 + /* 2934 */ MCD_OPC_Decode, + 227, + 21, + 0, // Opcode: TLBR_MM + /* 2938 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 2959 + /* 2943 */ MCD_OPC_CheckPredicate, + 7, + 240, + 13, + 0, // Skip to: 6516 + /* 2948 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 233, + 13, + 0, // Skip to: 6516 + /* 2955 */ MCD_OPC_Decode, + 229, + 21, + 0, // Opcode: TLBWI_MM + /* 2959 */ MCD_OPC_FilterValue, + 6, + 16, + 0, + 0, // Skip to: 2980 + /* 2964 */ MCD_OPC_CheckPredicate, + 7, + 219, + 13, + 0, // Skip to: 6516 + /* 2969 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 212, + 13, + 0, // Skip to: 6516 + /* 2976 */ MCD_OPC_Decode, + 231, + 21, + 0, // Opcode: TLBWR_MM + /* 2980 */ MCD_OPC_FilterValue, + 13, + 16, + 0, + 0, // Skip to: 3001 + /* 2985 */ MCD_OPC_CheckPredicate, + 7, + 198, + 13, + 0, // Skip to: 6516 + /* 2990 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 191, + 13, + 0, // Skip to: 6516 + /* 2997 */ MCD_OPC_Decode, + 171, + 21, + 76, // Opcode: SYNC_MM + /* 3001 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 3015 + /* 3006 */ MCD_OPC_CheckPredicate, + 7, + 177, + 13, + 0, // Skip to: 6516 + /* 3011 */ MCD_OPC_Decode, + 174, + 21, + 77, // Opcode: SYSCALL_MM + /* 3015 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 3029 + /* 3020 */ MCD_OPC_CheckPredicate, + 7, + 163, + 13, + 0, // Skip to: 6516 + /* 3025 */ MCD_OPC_Decode, + 137, + 22, + 77, // Opcode: WAIT_MM + /* 3029 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 3043 + /* 3034 */ MCD_OPC_CheckPredicate, + 10, + 149, + 13, + 0, // Skip to: 6516 + /* 3039 */ MCD_OPC_Decode, + 208, + 13, + 77, // Opcode: HYPCALL_MM + /* 3043 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 3057 + /* 3048 */ MCD_OPC_CheckPredicate, + 7, + 135, + 13, + 0, // Skip to: 6516 + /* 3053 */ MCD_OPC_Decode, + 128, + 19, + 77, // Opcode: SDBBP_MM + /* 3057 */ MCD_OPC_FilterValue, + 28, + 16, + 0, + 0, // Skip to: 3078 + /* 3062 */ MCD_OPC_CheckPredicate, + 7, + 121, + 13, + 0, // Skip to: 6516 + /* 3067 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 114, + 13, + 0, // Skip to: 6516 + /* 3074 */ MCD_OPC_Decode, + 229, + 10, + 0, // Opcode: DERET_MM + /* 3078 */ MCD_OPC_FilterValue, + 30, + 105, + 13, + 0, // Skip to: 6516 + /* 3083 */ MCD_OPC_CheckPredicate, + 7, + 100, + 13, + 0, // Skip to: 6516 + /* 3088 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 93, + 13, + 0, // Skip to: 6516 + /* 3095 */ MCD_OPC_Decode, + 232, + 11, + 0, // Opcode: ERET_MM + /* 3099 */ MCD_OPC_FilterValue, + 15, + 16, + 0, + 0, // Skip to: 3120 + /* 3104 */ MCD_OPC_CheckPredicate, + 9, + 79, + 13, + 0, // Skip to: 6516 + /* 3109 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 72, + 13, + 0, // Skip to: 6516 + /* 3116 */ MCD_OPC_Decode, + 225, + 19, + 59, // Opcode: SHRL_PH_MMR2 + /* 3120 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 3156 + /* 3125 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 3128 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3142 + /* 3133 */ MCD_OPC_CheckPredicate, + 7, + 50, + 13, + 0, // Skip to: 6516 + /* 3138 */ MCD_OPC_Decode, + 206, + 21, + 60, // Opcode: TGEU_MM + /* 3142 */ MCD_OPC_FilterValue, + 1, + 41, + 13, + 0, // Skip to: 6516 + /* 3147 */ MCD_OPC_CheckPredicate, + 7, + 36, + 13, + 0, // Skip to: 6516 + /* 3152 */ MCD_OPC_Decode, + 242, + 21, + 60, // Opcode: TNE_MM + /* 3156 */ MCD_OPC_FilterValue, + 18, + 115, + 0, + 0, // Skip to: 3276 + /* 3161 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 3164 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3178 + /* 3169 */ MCD_OPC_CheckPredicate, + 9, + 14, + 13, + 0, // Skip to: 6516 + /* 3174 */ MCD_OPC_Decode, + 197, + 11, + 65, // Opcode: DPS_W_PH_MMR2 + /* 3178 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3192 + /* 3183 */ MCD_OPC_CheckPredicate, + 8, + 0, + 13, + 0, // Skip to: 6516 + /* 3188 */ MCD_OPC_Decode, + 169, + 17, + 78, // Opcode: MULT_DSP_MM + /* 3192 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3206 + /* 3197 */ MCD_OPC_CheckPredicate, + 9, + 242, + 12, + 0, // Skip to: 6516 + /* 3202 */ MCD_OPC_Decode, + 195, + 11, + 65, // Opcode: DPSX_W_PH_MMR2 + /* 3206 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3220 + /* 3211 */ MCD_OPC_CheckPredicate, + 8, + 228, + 12, + 0, // Skip to: 6516 + /* 3216 */ MCD_OPC_Decode, + 167, + 17, + 78, // Opcode: MULTU_DSP_MM + /* 3220 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 3234 + /* 3225 */ MCD_OPC_CheckPredicate, + 8, + 214, + 12, + 0, // Skip to: 6516 + /* 3230 */ MCD_OPC_Decode, + 191, + 11, + 65, // Opcode: DPSU_H_QBL_MM + /* 3234 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3248 + /* 3239 */ MCD_OPC_CheckPredicate, + 9, + 200, + 12, + 0, // Skip to: 6516 + /* 3244 */ MCD_OPC_Decode, + 164, + 17, + 65, // Opcode: MULSA_W_PH_MMR2 + /* 3248 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3262 + /* 3253 */ MCD_OPC_CheckPredicate, + 8, + 186, + 12, + 0, // Skip to: 6516 + /* 3258 */ MCD_OPC_Decode, + 193, + 11, + 65, // Opcode: DPSU_H_QBR_MM + /* 3262 */ MCD_OPC_FilterValue, + 7, + 177, + 12, + 0, // Skip to: 6516 + /* 3267 */ MCD_OPC_CheckPredicate, + 8, + 172, + 12, + 0, // Skip to: 6516 + /* 3272 */ MCD_OPC_Decode, + 162, + 17, + 65, // Opcode: MULSAQ_S_W_PH_MM + /* 3276 */ MCD_OPC_FilterValue, + 19, + 16, + 0, + 0, // Skip to: 3297 + /* 3281 */ MCD_OPC_CheckPredicate, + 10, + 158, + 12, + 0, // Skip to: 6516 + /* 3286 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 151, + 12, + 0, // Skip to: 6516 + /* 3293 */ MCD_OPC_Decode, + 221, + 15, + 57, // Opcode: MFGC0_MM + /* 3297 */ MCD_OPC_FilterValue, + 20, + 31, + 0, + 0, // Skip to: 3333 + /* 3302 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3305 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 3319 + /* 3310 */ MCD_OPC_CheckPredicate, + 7, + 129, + 12, + 0, // Skip to: 6516 + /* 3315 */ MCD_OPC_Decode, + 176, + 8, + 79, // Opcode: CFC2_MM + /* 3319 */ MCD_OPC_FilterValue, + 27, + 120, + 12, + 0, // Skip to: 6516 + /* 3324 */ MCD_OPC_CheckPredicate, + 7, + 115, + 12, + 0, // Skip to: 6516 + /* 3329 */ MCD_OPC_Decode, + 203, + 9, + 80, // Opcode: CTC2_MM + /* 3333 */ MCD_OPC_FilterValue, + 21, + 87, + 0, + 0, // Skip to: 3425 + /* 3338 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3341 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 3362 + /* 3346 */ MCD_OPC_CheckPredicate, + 6, + 93, + 12, + 0, // Skip to: 6516 + /* 3351 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 86, + 12, + 0, // Skip to: 6516 + /* 3358 */ MCD_OPC_Decode, + 235, + 15, + 81, // Opcode: MFHI_MM + /* 3362 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 3383 + /* 3367 */ MCD_OPC_CheckPredicate, + 6, + 72, + 12, + 0, // Skip to: 6516 + /* 3372 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 65, + 12, + 0, // Skip to: 6516 + /* 3379 */ MCD_OPC_Decode, + 241, + 15, + 81, // Opcode: MFLO_MM + /* 3383 */ MCD_OPC_FilterValue, + 5, + 16, + 0, + 0, // Skip to: 3404 + /* 3388 */ MCD_OPC_CheckPredicate, + 6, + 51, + 12, + 0, // Skip to: 6516 + /* 3393 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 44, + 12, + 0, // Skip to: 6516 + /* 3400 */ MCD_OPC_Decode, + 250, + 16, + 81, // Opcode: MTHI_MM + /* 3404 */ MCD_OPC_FilterValue, + 7, + 35, + 12, + 0, // Skip to: 6516 + /* 3409 */ MCD_OPC_CheckPredicate, + 6, + 30, + 12, + 0, // Skip to: 6516 + /* 3414 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 23, + 12, + 0, // Skip to: 6516 + /* 3421 */ MCD_OPC_Decode, + 129, + 17, + 81, // Opcode: MTLO_MM + /* 3425 */ MCD_OPC_FilterValue, + 23, + 16, + 0, + 0, // Skip to: 3446 + /* 3430 */ MCD_OPC_CheckPredicate, + 8, + 9, + 12, + 0, // Skip to: 6516 + /* 3435 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 2, + 12, + 0, // Skip to: 6516 + /* 3442 */ MCD_OPC_Decode, + 196, + 18, + 82, // Opcode: REPL_QB_MM + /* 3446 */ MCD_OPC_FilterValue, + 25, + 115, + 0, + 0, // Skip to: 3566 + /* 3451 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 3454 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3468 + /* 3459 */ MCD_OPC_CheckPredicate, + 8, + 236, + 11, + 0, // Skip to: 6516 + /* 3464 */ MCD_OPC_Decode, + 177, + 18, + 83, // Opcode: RDDSP_MM + /* 3468 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3482 + /* 3473 */ MCD_OPC_CheckPredicate, + 8, + 222, + 11, + 0, // Skip to: 6516 + /* 3478 */ MCD_OPC_Decode, + 133, + 12, + 84, // Opcode: EXTR_W_MM + /* 3482 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3496 + /* 3487 */ MCD_OPC_CheckPredicate, + 8, + 208, + 11, + 0, // Skip to: 6516 + /* 3492 */ MCD_OPC_Decode, + 140, + 22, + 83, // Opcode: WRDSP_MM + /* 3496 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3510 + /* 3501 */ MCD_OPC_CheckPredicate, + 8, + 194, + 11, + 0, // Skip to: 6516 + /* 3506 */ MCD_OPC_Decode, + 129, + 12, + 84, // Opcode: EXTR_R_W_MM + /* 3510 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 3524 + /* 3515 */ MCD_OPC_CheckPredicate, + 8, + 180, + 11, + 0, // Skip to: 6516 + /* 3520 */ MCD_OPC_Decode, + 245, + 11, + 84, // Opcode: EXTP_MM + /* 3524 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3538 + /* 3529 */ MCD_OPC_CheckPredicate, + 8, + 166, + 11, + 0, // Skip to: 6516 + /* 3534 */ MCD_OPC_Decode, + 255, + 11, + 84, // Opcode: EXTR_RS_W_MM + /* 3538 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3552 + /* 3543 */ MCD_OPC_CheckPredicate, + 8, + 152, + 11, + 0, // Skip to: 6516 + /* 3548 */ MCD_OPC_Decode, + 242, + 11, + 84, // Opcode: EXTPDP_MM + /* 3552 */ MCD_OPC_FilterValue, + 7, + 143, + 11, + 0, // Skip to: 6516 + /* 3557 */ MCD_OPC_CheckPredicate, + 8, + 138, + 11, + 0, // Skip to: 6516 + /* 3562 */ MCD_OPC_Decode, + 131, + 12, + 84, // Opcode: EXTR_S_H_MM + /* 3566 */ MCD_OPC_FilterValue, + 26, + 115, + 0, + 0, // Skip to: 3686 + /* 3571 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 3574 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3588 + /* 3579 */ MCD_OPC_CheckPredicate, + 8, + 116, + 11, + 0, // Skip to: 6516 + /* 3584 */ MCD_OPC_Decode, + 183, + 11, + 65, // Opcode: DPSQ_S_W_PH_MM + /* 3588 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3602 + /* 3593 */ MCD_OPC_CheckPredicate, + 8, + 102, + 11, + 0, // Skip to: 6516 + /* 3598 */ MCD_OPC_Decode, + 253, + 11, + 67, // Opcode: EXTRV_W_MM + /* 3602 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3616 + /* 3607 */ MCD_OPC_CheckPredicate, + 8, + 88, + 11, + 0, // Skip to: 6516 + /* 3612 */ MCD_OPC_Decode, + 181, + 11, + 65, // Opcode: DPSQ_SA_L_W_MM + /* 3616 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3630 + /* 3621 */ MCD_OPC_CheckPredicate, + 8, + 74, + 11, + 0, // Skip to: 6516 + /* 3626 */ MCD_OPC_Decode, + 249, + 11, + 67, // Opcode: EXTRV_R_W_MM + /* 3630 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 3644 + /* 3635 */ MCD_OPC_CheckPredicate, + 9, + 60, + 11, + 0, // Skip to: 6516 + /* 3640 */ MCD_OPC_Decode, + 179, + 11, + 65, // Opcode: DPSQX_S_W_PH_MMR2 + /* 3644 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3658 + /* 3649 */ MCD_OPC_CheckPredicate, + 8, + 46, + 11, + 0, // Skip to: 6516 + /* 3654 */ MCD_OPC_Decode, + 247, + 11, + 67, // Opcode: EXTRV_RS_W_MM + /* 3658 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3672 + /* 3663 */ MCD_OPC_CheckPredicate, + 9, + 32, + 11, + 0, // Skip to: 6516 + /* 3668 */ MCD_OPC_Decode, + 177, + 11, + 65, // Opcode: DPSQX_SA_W_PH_MMR2 + /* 3672 */ MCD_OPC_FilterValue, + 7, + 23, + 11, + 0, // Skip to: 6516 + /* 3677 */ MCD_OPC_CheckPredicate, + 8, + 18, + 11, + 0, // Skip to: 6516 + /* 3682 */ MCD_OPC_Decode, + 251, + 11, + 67, // Opcode: EXTRV_S_H_MM + /* 3686 */ MCD_OPC_FilterValue, + 27, + 16, + 0, + 0, // Skip to: 3707 + /* 3691 */ MCD_OPC_CheckPredicate, + 10, + 4, + 11, + 0, // Skip to: 6516 + /* 3696 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 253, + 10, + 0, // Skip to: 6516 + /* 3703 */ MCD_OPC_Decode, + 237, + 16, + 58, // Opcode: MTGC0_MM + /* 3707 */ MCD_OPC_FilterValue, + 28, + 47, + 0, + 0, // Skip to: 3759 + /* 3712 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3715 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 3745 + /* 3720 */ MCD_OPC_CheckPredicate, + 6, + 11, + 0, + 0, // Skip to: 3736 + /* 3725 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 3736 + /* 3732 */ MCD_OPC_Decode, + 144, + 14, + 81, // Opcode: JR_MM + /* 3736 */ MCD_OPC_CheckPredicate, + 6, + 215, + 10, + 0, // Skip to: 6516 + /* 3741 */ MCD_OPC_Decode, + 250, + 13, + 69, // Opcode: JALR_MM + /* 3745 */ MCD_OPC_FilterValue, + 9, + 206, + 10, + 0, // Skip to: 6516 + /* 3750 */ MCD_OPC_CheckPredicate, + 6, + 201, + 10, + 0, // Skip to: 6516 + /* 3755 */ MCD_OPC_Decode, + 247, + 13, + 69, // Opcode: JALRS_MM + /* 3759 */ MCD_OPC_FilterValue, + 29, + 192, + 10, + 0, // Skip to: 6516 + /* 3764 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3767 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 3788 + /* 3772 */ MCD_OPC_CheckPredicate, + 7, + 179, + 10, + 0, // Skip to: 6516 + /* 3777 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 172, + 10, + 0, // Skip to: 6516 + /* 3784 */ MCD_OPC_Decode, + 251, + 10, + 81, // Opcode: DI_MM + /* 3788 */ MCD_OPC_FilterValue, + 10, + 163, + 10, + 0, // Skip to: 6516 + /* 3793 */ MCD_OPC_CheckPredicate, + 7, + 158, + 10, + 0, // Skip to: 6516 + /* 3798 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 151, + 10, + 0, // Skip to: 6516 + /* 3805 */ MCD_OPC_Decode, + 226, + 11, + 81, // Opcode: EI_MM + /* 3809 */ MCD_OPC_FilterValue, + 61, + 142, + 10, + 0, // Skip to: 6516 + /* 3814 */ MCD_OPC_CheckPredicate, + 8, + 137, + 10, + 0, // Skip to: 6516 + /* 3819 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 130, + 10, + 0, // Skip to: 6516 + /* 3826 */ MCD_OPC_Decode, + 194, + 18, + 85, // Opcode: REPL_PH_MM + /* 3830 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 3844 + /* 3835 */ MCD_OPC_CheckPredicate, + 6, + 116, + 10, + 0, // Skip to: 6516 + /* 3840 */ MCD_OPC_Decode, + 136, + 6, + 86, // Opcode: ADDi_MM + /* 3844 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3858 + /* 3849 */ MCD_OPC_CheckPredicate, + 7, + 102, + 10, + 0, // Skip to: 6516 + /* 3854 */ MCD_OPC_Decode, + 166, + 14, + 87, // Opcode: LBu_MM + /* 3858 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3872 + /* 3863 */ MCD_OPC_CheckPredicate, + 7, + 88, + 10, + 0, // Skip to: 6516 + /* 3868 */ MCD_OPC_Decode, + 240, + 18, + 87, // Opcode: SB_MM + /* 3872 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 3886 + /* 3877 */ MCD_OPC_CheckPredicate, + 7, + 74, + 10, + 0, // Skip to: 6516 + /* 3882 */ MCD_OPC_Decode, + 160, + 14, + 87, // Opcode: LB_MM + /* 3886 */ MCD_OPC_FilterValue, + 8, + 73, + 0, + 0, // Skip to: 3964 + /* 3891 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3894 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3908 + /* 3899 */ MCD_OPC_CheckPredicate, + 7, + 52, + 10, + 0, // Skip to: 6516 + /* 3904 */ MCD_OPC_Decode, + 251, + 14, + 88, // Opcode: LWP_MM + /* 3908 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3922 + /* 3913 */ MCD_OPC_CheckPredicate, + 7, + 38, + 10, + 0, // Skip to: 6516 + /* 3918 */ MCD_OPC_Decode, + 248, + 14, + 88, // Opcode: LWM32_MM + /* 3922 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 3936 + /* 3927 */ MCD_OPC_CheckPredicate, + 6, + 24, + 10, + 0, // Skip to: 6516 + /* 3932 */ MCD_OPC_Decode, + 152, + 8, + 89, // Opcode: CACHE_MM + /* 3936 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 3950 + /* 3941 */ MCD_OPC_CheckPredicate, + 7, + 10, + 10, + 0, // Skip to: 6516 + /* 3946 */ MCD_OPC_Decode, + 155, + 21, + 88, // Opcode: SWP_MM + /* 3950 */ MCD_OPC_FilterValue, + 13, + 1, + 10, + 0, // Skip to: 6516 + /* 3955 */ MCD_OPC_CheckPredicate, + 7, + 252, + 9, + 0, // Skip to: 6516 + /* 3960 */ MCD_OPC_Decode, + 154, + 21, + 88, // Opcode: SWM32_MM + /* 3964 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 3978 + /* 3969 */ MCD_OPC_CheckPredicate, + 6, + 238, + 9, + 0, // Skip to: 6516 + /* 3974 */ MCD_OPC_Decode, + 138, + 6, + 86, // Opcode: ADDiu_MM + /* 3978 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 3992 + /* 3983 */ MCD_OPC_CheckPredicate, + 7, + 224, + 9, + 0, // Skip to: 6516 + /* 3988 */ MCD_OPC_Decode, + 204, + 14, + 87, // Opcode: LHu_MM + /* 3992 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4006 + /* 3997 */ MCD_OPC_CheckPredicate, + 7, + 210, + 9, + 0, // Skip to: 6516 + /* 4002 */ MCD_OPC_Decode, + 228, + 19, + 87, // Opcode: SH_MM + /* 4006 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 4020 + /* 4011 */ MCD_OPC_CheckPredicate, + 7, + 196, + 9, + 0, // Skip to: 6516 + /* 4016 */ MCD_OPC_Decode, + 199, + 14, + 87, // Opcode: LH_MM + /* 4020 */ MCD_OPC_FilterValue, + 16, + 83, + 1, + 0, // Skip to: 4364 + /* 4025 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 4028 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4042 + /* 4033 */ MCD_OPC_CheckPredicate, + 6, + 174, + 9, + 0, // Skip to: 6516 + /* 4038 */ MCD_OPC_Decode, + 206, + 7, + 90, // Opcode: BLTZ_MM + /* 4042 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4056 + /* 4047 */ MCD_OPC_CheckPredicate, + 6, + 160, + 9, + 0, // Skip to: 6516 + /* 4052 */ MCD_OPC_Decode, + 201, + 7, + 90, // Opcode: BLTZAL_MM + /* 4056 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4070 + /* 4061 */ MCD_OPC_CheckPredicate, + 6, + 146, + 9, + 0, // Skip to: 6516 + /* 4066 */ MCD_OPC_Decode, + 149, + 7, + 90, // Opcode: BGEZ_MM + /* 4070 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 4084 + /* 4075 */ MCD_OPC_CheckPredicate, + 6, + 132, + 9, + 0, // Skip to: 6516 + /* 4080 */ MCD_OPC_Decode, + 144, + 7, + 90, // Opcode: BGEZAL_MM + /* 4084 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 4098 + /* 4089 */ MCD_OPC_CheckPredicate, + 6, + 118, + 9, + 0, // Skip to: 6516 + /* 4094 */ MCD_OPC_Decode, + 187, + 7, + 90, // Opcode: BLEZ_MM + /* 4098 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 4112 + /* 4103 */ MCD_OPC_CheckPredicate, + 6, + 104, + 9, + 0, // Skip to: 6516 + /* 4108 */ MCD_OPC_Decode, + 231, + 7, + 90, // Opcode: BNEZC_MM + /* 4112 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 4126 + /* 4117 */ MCD_OPC_CheckPredicate, + 6, + 90, + 9, + 0, // Skip to: 6516 + /* 4122 */ MCD_OPC_Decode, + 158, + 7, + 90, // Opcode: BGTZ_MM + /* 4126 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 4140 + /* 4131 */ MCD_OPC_CheckPredicate, + 6, + 76, + 9, + 0, // Skip to: 6516 + /* 4136 */ MCD_OPC_Decode, + 128, + 7, + 90, // Opcode: BEQZC_MM + /* 4140 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 4154 + /* 4145 */ MCD_OPC_CheckPredicate, + 6, + 62, + 9, + 0, // Skip to: 6516 + /* 4150 */ MCD_OPC_Decode, + 235, + 21, + 91, // Opcode: TLTI_MM + /* 4154 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 4168 + /* 4159 */ MCD_OPC_CheckPredicate, + 6, + 48, + 9, + 0, // Skip to: 6516 + /* 4164 */ MCD_OPC_Decode, + 204, + 21, + 91, // Opcode: TGEI_MM + /* 4168 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 4182 + /* 4173 */ MCD_OPC_CheckPredicate, + 6, + 34, + 9, + 0, // Skip to: 6516 + /* 4178 */ MCD_OPC_Decode, + 234, + 21, + 91, // Opcode: TLTIU_MM + /* 4182 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 4196 + /* 4187 */ MCD_OPC_CheckPredicate, + 6, + 20, + 9, + 0, // Skip to: 6516 + /* 4192 */ MCD_OPC_Decode, + 203, + 21, + 91, // Opcode: TGEIU_MM + /* 4196 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 4210 + /* 4201 */ MCD_OPC_CheckPredicate, + 6, + 6, + 9, + 0, // Skip to: 6516 + /* 4206 */ MCD_OPC_Decode, + 241, + 21, + 91, // Opcode: TNEI_MM + /* 4210 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 4224 + /* 4215 */ MCD_OPC_CheckPredicate, + 6, + 248, + 8, + 0, // Skip to: 6516 + /* 4220 */ MCD_OPC_Decode, + 226, + 14, + 92, // Opcode: LUi_MM + /* 4224 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 4238 + /* 4229 */ MCD_OPC_CheckPredicate, + 6, + 234, + 8, + 0, // Skip to: 6516 + /* 4234 */ MCD_OPC_Decode, + 198, + 21, + 91, // Opcode: TEQI_MM + /* 4238 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 4252 + /* 4243 */ MCD_OPC_CheckPredicate, + 6, + 220, + 8, + 0, // Skip to: 6516 + /* 4248 */ MCD_OPC_Decode, + 169, + 21, + 93, // Opcode: SYNCI_MM + /* 4252 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 4266 + /* 4257 */ MCD_OPC_CheckPredicate, + 6, + 206, + 8, + 0, // Skip to: 6516 + /* 4262 */ MCD_OPC_Decode, + 200, + 7, + 90, // Opcode: BLTZALS_MM + /* 4266 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 4280 + /* 4271 */ MCD_OPC_CheckPredicate, + 6, + 192, + 8, + 0, // Skip to: 6516 + /* 4276 */ MCD_OPC_Decode, + 143, + 7, + 90, // Opcode: BGEZALS_MM + /* 4280 */ MCD_OPC_FilterValue, + 25, + 16, + 0, + 0, // Skip to: 4301 + /* 4285 */ MCD_OPC_CheckPredicate, + 11, + 178, + 8, + 0, // Skip to: 6516 + /* 4290 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 171, + 8, + 0, // Skip to: 6516 + /* 4297 */ MCD_OPC_Decode, + 244, + 7, + 94, // Opcode: BPOSGE32C_MMR3 + /* 4301 */ MCD_OPC_FilterValue, + 27, + 16, + 0, + 0, // Skip to: 4322 + /* 4306 */ MCD_OPC_CheckPredicate, + 12, + 157, + 8, + 0, // Skip to: 6516 + /* 4311 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 150, + 8, + 0, // Skip to: 6516 + /* 4318 */ MCD_OPC_Decode, + 245, + 7, + 95, // Opcode: BPOSGE32_MM + /* 4322 */ MCD_OPC_FilterValue, + 28, + 16, + 0, + 0, // Skip to: 4343 + /* 4327 */ MCD_OPC_CheckPredicate, + 13, + 136, + 8, + 0, // Skip to: 6516 + /* 4332 */ MCD_OPC_CheckField, + 16, + 2, + 0, + 129, + 8, + 0, // Skip to: 6516 + /* 4339 */ MCD_OPC_Decode, + 217, + 6, + 96, // Opcode: BC1F_MM + /* 4343 */ MCD_OPC_FilterValue, + 29, + 120, + 8, + 0, // Skip to: 6516 + /* 4348 */ MCD_OPC_CheckPredicate, + 13, + 115, + 8, + 0, // Skip to: 6516 + /* 4353 */ MCD_OPC_CheckField, + 16, + 2, + 0, + 108, + 8, + 0, // Skip to: 6516 + /* 4360 */ MCD_OPC_Decode, + 222, + 6, + 96, // Opcode: BC1T_MM + /* 4364 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 4378 + /* 4369 */ MCD_OPC_CheckPredicate, + 6, + 94, + 8, + 0, // Skip to: 6516 + /* 4374 */ MCD_OPC_Decode, + 231, + 17, + 97, // Opcode: ORi_MM + /* 4378 */ MCD_OPC_FilterValue, + 21, + 197, + 5, + 0, // Skip to: 5860 + /* 4383 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 4386 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4400 + /* 4391 */ MCD_OPC_CheckPredicate, + 14, + 72, + 8, + 0, // Skip to: 6516 + /* 4396 */ MCD_OPC_Decode, + 175, + 15, + 98, // Opcode: MADD_S_MM + /* 4400 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4414 + /* 4405 */ MCD_OPC_CheckPredicate, + 14, + 58, + 8, + 0, // Skip to: 6516 + /* 4410 */ MCD_OPC_Decode, + 204, + 17, + 98, // Opcode: NMADD_S_MM + /* 4414 */ MCD_OPC_FilterValue, + 8, + 59, + 0, + 0, // Skip to: 4478 + /* 4419 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4422 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4436 + /* 4427 */ MCD_OPC_CheckPredicate, + 13, + 36, + 8, + 0, // Skip to: 6516 + /* 4432 */ MCD_OPC_Decode, + 134, + 15, + 99, // Opcode: LWXC1_MM + /* 4436 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4450 + /* 4441 */ MCD_OPC_CheckPredicate, + 13, + 22, + 8, + 0, // Skip to: 6516 + /* 4446 */ MCD_OPC_Decode, + 164, + 21, + 99, // Opcode: SWXC1_MM + /* 4450 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 4464 + /* 4455 */ MCD_OPC_CheckPredicate, + 15, + 8, + 8, + 0, // Skip to: 6516 + /* 4460 */ MCD_OPC_Decode, + 223, + 14, + 100, // Opcode: LUXC1_MM + /* 4464 */ MCD_OPC_FilterValue, + 6, + 255, + 7, + 0, // Skip to: 6516 + /* 4469 */ MCD_OPC_CheckPredicate, + 15, + 250, + 7, + 0, // Skip to: 6516 + /* 4474 */ MCD_OPC_Decode, + 132, + 21, + 100, // Opcode: SUXC1_MM + /* 4478 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 4492 + /* 4483 */ MCD_OPC_CheckPredicate, + 16, + 236, + 7, + 0, // Skip to: 6516 + /* 4488 */ MCD_OPC_Decode, + 167, + 15, + 101, // Opcode: MADD_D32_MM + /* 4492 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 4506 + /* 4497 */ MCD_OPC_CheckPredicate, + 16, + 222, + 7, + 0, // Skip to: 6516 + /* 4502 */ MCD_OPC_Decode, + 201, + 17, + 101, // Opcode: NMADD_D32_MM + /* 4506 */ MCD_OPC_FilterValue, + 32, + 101, + 0, + 0, // Skip to: 4612 + /* 4511 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4514 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4535 + /* 4519 */ MCD_OPC_CheckPredicate, + 13, + 200, + 7, + 0, // Skip to: 6516 + /* 4524 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 193, + 7, + 0, // Skip to: 6516 + /* 4531 */ MCD_OPC_Decode, + 169, + 16, + 102, // Opcode: MOVF_S_MM + /* 4535 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 4556 + /* 4540 */ MCD_OPC_CheckPredicate, + 13, + 179, + 7, + 0, // Skip to: 6516 + /* 4545 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 172, + 7, + 0, // Skip to: 6516 + /* 4552 */ MCD_OPC_Decode, + 189, + 16, + 102, // Opcode: MOVT_S_MM + /* 4556 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 4570 + /* 4561 */ MCD_OPC_CheckPredicate, + 6, + 158, + 7, + 0, // Skip to: 6516 + /* 4566 */ MCD_OPC_Decode, + 166, + 18, + 103, // Opcode: PREFX_MM + /* 4570 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 4591 + /* 4575 */ MCD_OPC_CheckPredicate, + 17, + 144, + 7, + 0, // Skip to: 6516 + /* 4580 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 137, + 7, + 0, // Skip to: 6516 + /* 4587 */ MCD_OPC_Decode, + 163, + 16, + 104, // Opcode: MOVF_D32_MM + /* 4591 */ MCD_OPC_FilterValue, + 9, + 128, + 7, + 0, // Skip to: 6516 + /* 4596 */ MCD_OPC_CheckPredicate, + 17, + 123, + 7, + 0, // Skip to: 6516 + /* 4601 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 116, + 7, + 0, // Skip to: 6516 + /* 4608 */ MCD_OPC_Decode, + 183, + 16, + 104, // Opcode: MOVT_D32_MM + /* 4612 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 4626 + /* 4617 */ MCD_OPC_CheckPredicate, + 14, + 102, + 7, + 0, // Skip to: 6516 + /* 4622 */ MCD_OPC_Decode, + 226, + 16, + 98, // Opcode: MSUB_S_MM + /* 4626 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 4640 + /* 4631 */ MCD_OPC_CheckPredicate, + 14, + 88, + 7, + 0, // Skip to: 6516 + /* 4636 */ MCD_OPC_Decode, + 209, + 17, + 98, // Opcode: NMSUB_S_MM + /* 4640 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 4654 + /* 4645 */ MCD_OPC_CheckPredicate, + 16, + 74, + 7, + 0, // Skip to: 6516 + /* 4650 */ MCD_OPC_Decode, + 218, + 16, + 101, // Opcode: MSUB_D32_MM + /* 4654 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 4668 + /* 4659 */ MCD_OPC_CheckPredicate, + 16, + 60, + 7, + 0, // Skip to: 6516 + /* 4664 */ MCD_OPC_Decode, + 206, + 17, + 101, // Opcode: NMSUB_D32_MM + /* 4668 */ MCD_OPC_FilterValue, + 48, + 59, + 0, + 0, // Skip to: 4732 + /* 4673 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4676 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 4690 + /* 4681 */ MCD_OPC_CheckPredicate, + 18, + 38, + 7, + 0, // Skip to: 6516 + /* 4686 */ MCD_OPC_Decode, + 146, + 12, + 105, // Opcode: FADD_D32_MM + /* 4690 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 4704 + /* 4695 */ MCD_OPC_CheckPredicate, + 18, + 24, + 7, + 0, // Skip to: 6516 + /* 4700 */ MCD_OPC_Decode, + 163, + 13, + 105, // Opcode: FSUB_D32_MM + /* 4704 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 4718 + /* 4709 */ MCD_OPC_CheckPredicate, + 18, + 10, + 7, + 0, // Skip to: 6516 + /* 4714 */ MCD_OPC_Decode, + 247, + 12, + 105, // Opcode: FMUL_D32_MM + /* 4718 */ MCD_OPC_FilterValue, + 7, + 1, + 7, + 0, // Skip to: 6516 + /* 4723 */ MCD_OPC_CheckPredicate, + 18, + 252, + 6, + 0, // Skip to: 6516 + /* 4728 */ MCD_OPC_Decode, + 185, + 12, + 105, // Opcode: FDIV_D32_MM + /* 4732 */ MCD_OPC_FilterValue, + 56, + 59, + 0, + 0, // Skip to: 4796 + /* 4737 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 4740 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4754 + /* 4745 */ MCD_OPC_CheckPredicate, + 13, + 230, + 6, + 0, // Skip to: 6516 + /* 4750 */ MCD_OPC_Decode, + 181, + 16, + 106, // Opcode: MOVN_I_S_MM + /* 4754 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4768 + /* 4759 */ MCD_OPC_CheckPredicate, + 13, + 216, + 6, + 0, // Skip to: 6516 + /* 4764 */ MCD_OPC_Decode, + 201, + 16, + 106, // Opcode: MOVZ_I_S_MM + /* 4768 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 4782 + /* 4773 */ MCD_OPC_CheckPredicate, + 17, + 202, + 6, + 0, // Skip to: 6516 + /* 4778 */ MCD_OPC_Decode, + 175, + 16, + 107, // Opcode: MOVN_I_D32_MM + /* 4782 */ MCD_OPC_FilterValue, + 5, + 193, + 6, + 0, // Skip to: 6516 + /* 4787 */ MCD_OPC_CheckPredicate, + 17, + 188, + 6, + 0, // Skip to: 6516 + /* 4792 */ MCD_OPC_Decode, + 195, + 16, + 107, // Opcode: MOVZ_I_D32_MM + /* 4796 */ MCD_OPC_FilterValue, + 59, + 91, + 2, + 0, // Skip to: 5404 + /* 4801 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 4804 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4825 + /* 4809 */ MCD_OPC_CheckPredicate, + 19, + 166, + 6, + 0, // Skip to: 6516 + /* 4814 */ MCD_OPC_CheckField, + 13, + 3, + 1, + 159, + 6, + 0, // Skip to: 6516 + /* 4821 */ MCD_OPC_Decode, + 216, + 15, + 108, // Opcode: MFC1_MM + /* 4825 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 4846 + /* 4830 */ MCD_OPC_CheckPredicate, + 18, + 145, + 6, + 0, // Skip to: 6516 + /* 4835 */ MCD_OPC_CheckField, + 13, + 3, + 1, + 138, + 6, + 0, // Skip to: 6516 + /* 4842 */ MCD_OPC_Decode, + 236, + 12, + 109, // Opcode: FMOV_D32_MM + /* 4846 */ MCD_OPC_FilterValue, + 4, + 31, + 0, + 0, // Skip to: 4882 + /* 4851 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4854 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4868 + /* 4859 */ MCD_OPC_CheckPredicate, + 20, + 116, + 6, + 0, // Skip to: 6516 + /* 4864 */ MCD_OPC_Decode, + 219, + 9, + 110, // Opcode: CVT_L_S_MM + /* 4868 */ MCD_OPC_FilterValue, + 2, + 107, + 6, + 0, // Skip to: 6516 + /* 4873 */ MCD_OPC_CheckPredicate, + 20, + 102, + 6, + 0, // Skip to: 6516 + /* 4878 */ MCD_OPC_Decode, + 216, + 9, + 111, // Opcode: CVT_L_D64_MM + /* 4882 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 4896 + /* 4887 */ MCD_OPC_CheckPredicate, + 13, + 88, + 6, + 0, // Skip to: 6516 + /* 4892 */ MCD_OPC_Decode, + 167, + 16, + 112, // Opcode: MOVF_I_MM + /* 4896 */ MCD_OPC_FilterValue, + 8, + 31, + 0, + 0, // Skip to: 4932 + /* 4901 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4904 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4918 + /* 4909 */ MCD_OPC_CheckPredicate, + 19, + 66, + 6, + 0, // Skip to: 6516 + /* 4914 */ MCD_OPC_Decode, + 221, + 18, + 113, // Opcode: RSQRT_S_MM + /* 4918 */ MCD_OPC_FilterValue, + 2, + 57, + 6, + 0, // Skip to: 6516 + /* 4923 */ MCD_OPC_CheckPredicate, + 18, + 52, + 6, + 0, // Skip to: 6516 + /* 4928 */ MCD_OPC_Decode, + 217, + 18, + 109, // Opcode: RSQRT_D32_MM + /* 4932 */ MCD_OPC_FilterValue, + 13, + 31, + 0, + 0, // Skip to: 4968 + /* 4937 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4940 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4954 + /* 4945 */ MCD_OPC_CheckPredicate, + 19, + 30, + 6, + 0, // Skip to: 6516 + /* 4950 */ MCD_OPC_Decode, + 143, + 12, + 113, // Opcode: FABS_S_MM + /* 4954 */ MCD_OPC_FilterValue, + 1, + 21, + 6, + 0, // Skip to: 6516 + /* 4959 */ MCD_OPC_CheckPredicate, + 18, + 16, + 6, + 0, // Skip to: 6516 + /* 4964 */ MCD_OPC_Decode, + 139, + 12, + 109, // Opcode: FABS_D32_MM + /* 4968 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 4989 + /* 4973 */ MCD_OPC_CheckPredicate, + 19, + 2, + 6, + 0, // Skip to: 6516 + /* 4978 */ MCD_OPC_CheckField, + 13, + 3, + 1, + 251, + 5, + 0, // Skip to: 6516 + /* 4985 */ MCD_OPC_Decode, + 232, + 16, + 114, // Opcode: MTC1_MM + /* 4989 */ MCD_OPC_FilterValue, + 36, + 31, + 0, + 0, // Skip to: 5025 + /* 4994 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4997 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5011 + /* 5002 */ MCD_OPC_CheckPredicate, + 19, + 229, + 5, + 0, // Skip to: 6516 + /* 5007 */ MCD_OPC_Decode, + 240, + 9, + 113, // Opcode: CVT_W_S_MM + /* 5011 */ MCD_OPC_FilterValue, + 2, + 220, + 5, + 0, // Skip to: 6516 + /* 5016 */ MCD_OPC_CheckPredicate, + 18, + 215, + 5, + 0, // Skip to: 6516 + /* 5021 */ MCD_OPC_Decode, + 236, + 9, + 115, // Opcode: CVT_W_D32_MM + /* 5025 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 5039 + /* 5030 */ MCD_OPC_CheckPredicate, + 13, + 201, + 5, + 0, // Skip to: 6516 + /* 5035 */ MCD_OPC_Decode, + 187, + 16, + 112, // Opcode: MOVT_I_MM + /* 5039 */ MCD_OPC_FilterValue, + 40, + 31, + 0, + 0, // Skip to: 5075 + /* 5044 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5047 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5061 + /* 5052 */ MCD_OPC_CheckPredicate, + 19, + 179, + 5, + 0, // Skip to: 6516 + /* 5057 */ MCD_OPC_Decode, + 159, + 13, + 113, // Opcode: FSQRT_S_MM + /* 5061 */ MCD_OPC_FilterValue, + 2, + 170, + 5, + 0, // Skip to: 6516 + /* 5066 */ MCD_OPC_CheckPredicate, + 18, + 165, + 5, + 0, // Skip to: 6516 + /* 5071 */ MCD_OPC_Decode, + 155, + 13, + 109, // Opcode: FSQRT_D32_MM + /* 5075 */ MCD_OPC_FilterValue, + 44, + 59, + 0, + 0, // Skip to: 5139 + /* 5080 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5083 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5097 + /* 5088 */ MCD_OPC_CheckPredicate, + 19, + 143, + 5, + 0, // Skip to: 6516 + /* 5093 */ MCD_OPC_Decode, + 223, + 12, + 113, // Opcode: FLOOR_W_S_MM + /* 5097 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5111 + /* 5102 */ MCD_OPC_CheckPredicate, + 19, + 129, + 5, + 0, // Skip to: 6516 + /* 5107 */ MCD_OPC_Decode, + 252, + 21, + 113, // Opcode: TRUNC_W_S_MM + /* 5111 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5125 + /* 5116 */ MCD_OPC_CheckPredicate, + 18, + 115, + 5, + 0, // Skip to: 6516 + /* 5121 */ MCD_OPC_Decode, + 221, + 12, + 115, // Opcode: FLOOR_W_MM + /* 5125 */ MCD_OPC_FilterValue, + 3, + 106, + 5, + 0, // Skip to: 6516 + /* 5130 */ MCD_OPC_CheckPredicate, + 18, + 101, + 5, + 0, // Skip to: 6516 + /* 5135 */ MCD_OPC_Decode, + 250, + 21, + 115, // Opcode: TRUNC_W_MM + /* 5139 */ MCD_OPC_FilterValue, + 45, + 16, + 0, + 0, // Skip to: 5160 + /* 5144 */ MCD_OPC_CheckPredicate, + 18, + 87, + 5, + 0, // Skip to: 6516 + /* 5149 */ MCD_OPC_CheckField, + 13, + 3, + 1, + 80, + 5, + 0, // Skip to: 6516 + /* 5156 */ MCD_OPC_Decode, + 128, + 13, + 109, // Opcode: FNEG_D32_MM + /* 5160 */ MCD_OPC_FilterValue, + 64, + 31, + 0, + 0, // Skip to: 5196 + /* 5165 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5168 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5182 + /* 5173 */ MCD_OPC_CheckPredicate, + 19, + 58, + 5, + 0, // Skip to: 6516 + /* 5178 */ MCD_OPC_Decode, + 175, + 8, + 116, // Opcode: CFC1_MM + /* 5182 */ MCD_OPC_FilterValue, + 1, + 49, + 5, + 0, // Skip to: 6516 + /* 5187 */ MCD_OPC_CheckPredicate, + 18, + 44, + 5, + 0, // Skip to: 6516 + /* 5192 */ MCD_OPC_Decode, + 224, + 15, + 117, // Opcode: MFHC1_D32_MM + /* 5196 */ MCD_OPC_FilterValue, + 72, + 31, + 0, + 0, // Skip to: 5232 + /* 5201 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5204 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5218 + /* 5209 */ MCD_OPC_CheckPredicate, + 19, + 22, + 5, + 0, // Skip to: 6516 + /* 5214 */ MCD_OPC_Decode, + 188, + 18, + 113, // Opcode: RECIP_S_MM + /* 5218 */ MCD_OPC_FilterValue, + 2, + 13, + 5, + 0, // Skip to: 6516 + /* 5223 */ MCD_OPC_CheckPredicate, + 18, + 8, + 5, + 0, // Skip to: 6516 + /* 5228 */ MCD_OPC_Decode, + 184, + 18, + 109, // Opcode: RECIP_D32_MM + /* 5232 */ MCD_OPC_FilterValue, + 77, + 31, + 0, + 0, // Skip to: 5268 + /* 5237 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5240 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5254 + /* 5245 */ MCD_OPC_CheckPredicate, + 18, + 242, + 4, + 0, // Skip to: 6516 + /* 5250 */ MCD_OPC_Decode, + 206, + 9, + 118, // Opcode: CVT_D32_S_MM + /* 5254 */ MCD_OPC_FilterValue, + 1, + 233, + 4, + 0, // Skip to: 6516 + /* 5259 */ MCD_OPC_CheckPredicate, + 18, + 228, + 4, + 0, // Skip to: 6516 + /* 5264 */ MCD_OPC_Decode, + 208, + 9, + 118, // Opcode: CVT_D32_W_MM + /* 5268 */ MCD_OPC_FilterValue, + 96, + 31, + 0, + 0, // Skip to: 5304 + /* 5273 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5276 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5290 + /* 5281 */ MCD_OPC_CheckPredicate, + 19, + 206, + 4, + 0, // Skip to: 6516 + /* 5286 */ MCD_OPC_Decode, + 202, + 9, + 119, // Opcode: CTC1_MM + /* 5290 */ MCD_OPC_FilterValue, + 1, + 197, + 4, + 0, // Skip to: 6516 + /* 5295 */ MCD_OPC_CheckPredicate, + 18, + 192, + 4, + 0, // Skip to: 6516 + /* 5300 */ MCD_OPC_Decode, + 240, + 16, + 120, // Opcode: MTHC1_D32_MM + /* 5304 */ MCD_OPC_FilterValue, + 108, + 59, + 0, + 0, // Skip to: 5368 + /* 5309 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5312 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5326 + /* 5317 */ MCD_OPC_CheckPredicate, + 19, + 170, + 4, + 0, // Skip to: 6516 + /* 5322 */ MCD_OPC_Decode, + 164, + 8, + 113, // Opcode: CEIL_W_S_MM + /* 5326 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5340 + /* 5331 */ MCD_OPC_CheckPredicate, + 19, + 156, + 4, + 0, // Skip to: 6516 + /* 5336 */ MCD_OPC_Decode, + 214, + 18, + 113, // Opcode: ROUND_W_S_MM + /* 5340 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5354 + /* 5345 */ MCD_OPC_CheckPredicate, + 18, + 142, + 4, + 0, // Skip to: 6516 + /* 5350 */ MCD_OPC_Decode, + 162, + 8, + 115, // Opcode: CEIL_W_MM + /* 5354 */ MCD_OPC_FilterValue, + 3, + 133, + 4, + 0, // Skip to: 6516 + /* 5359 */ MCD_OPC_CheckPredicate, + 18, + 128, + 4, + 0, // Skip to: 6516 + /* 5364 */ MCD_OPC_Decode, + 212, + 18, + 115, // Opcode: ROUND_W_MM + /* 5368 */ MCD_OPC_FilterValue, + 109, + 119, + 4, + 0, // Skip to: 6516 + /* 5373 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5376 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5390 + /* 5381 */ MCD_OPC_CheckPredicate, + 18, + 106, + 4, + 0, // Skip to: 6516 + /* 5386 */ MCD_OPC_Decode, + 225, + 9, + 115, // Opcode: CVT_S_D32_MM + /* 5390 */ MCD_OPC_FilterValue, + 1, + 97, + 4, + 0, // Skip to: 6516 + /* 5395 */ MCD_OPC_CheckPredicate, + 19, + 92, + 4, + 0, // Skip to: 6516 + /* 5400 */ MCD_OPC_Decode, + 233, + 9, + 113, // Opcode: CVT_S_W_MM + /* 5404 */ MCD_OPC_FilterValue, + 60, + 83, + 4, + 0, // Skip to: 6516 + /* 5409 */ MCD_OPC_ExtractField, + 6, + 7, // Inst{12-6} ... + /* 5412 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5426 + /* 5417 */ MCD_OPC_CheckPredicate, + 13, + 70, + 4, + 0, // Skip to: 6516 + /* 5422 */ MCD_OPC_Decode, + 253, + 9, + 121, // Opcode: C_F_S_MM + /* 5426 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5440 + /* 5431 */ MCD_OPC_CheckPredicate, + 13, + 56, + 4, + 0, // Skip to: 6516 + /* 5436 */ MCD_OPC_Decode, + 209, + 10, + 121, // Opcode: C_UN_S_MM + /* 5440 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5454 + /* 5445 */ MCD_OPC_CheckPredicate, + 13, + 42, + 4, + 0, // Skip to: 6516 + /* 5450 */ MCD_OPC_Decode, + 247, + 9, + 121, // Opcode: C_EQ_S_MM + /* 5454 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 5468 + /* 5459 */ MCD_OPC_CheckPredicate, + 13, + 28, + 4, + 0, // Skip to: 6516 + /* 5464 */ MCD_OPC_Decode, + 191, + 10, + 121, // Opcode: C_UEQ_S_MM + /* 5468 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 5482 + /* 5473 */ MCD_OPC_CheckPredicate, + 13, + 14, + 4, + 0, // Skip to: 6516 + /* 5478 */ MCD_OPC_Decode, + 173, + 10, + 121, // Opcode: C_OLT_S_MM + /* 5482 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 5496 + /* 5487 */ MCD_OPC_CheckPredicate, + 13, + 0, + 4, + 0, // Skip to: 6516 + /* 5492 */ MCD_OPC_Decode, + 203, + 10, + 121, // Opcode: C_ULT_S_MM + /* 5496 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 5510 + /* 5501 */ MCD_OPC_CheckPredicate, + 13, + 242, + 3, + 0, // Skip to: 6516 + /* 5506 */ MCD_OPC_Decode, + 167, + 10, + 121, // Opcode: C_OLE_S_MM + /* 5510 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 5524 + /* 5515 */ MCD_OPC_CheckPredicate, + 13, + 228, + 3, + 0, // Skip to: 6516 + /* 5520 */ MCD_OPC_Decode, + 197, + 10, + 121, // Opcode: C_ULE_S_MM + /* 5524 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 5538 + /* 5529 */ MCD_OPC_CheckPredicate, + 13, + 214, + 3, + 0, // Skip to: 6516 + /* 5534 */ MCD_OPC_Decode, + 185, + 10, + 121, // Opcode: C_SF_S_MM + /* 5538 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 5552 + /* 5543 */ MCD_OPC_CheckPredicate, + 13, + 200, + 3, + 0, // Skip to: 6516 + /* 5548 */ MCD_OPC_Decode, + 149, + 10, + 121, // Opcode: C_NGLE_S_MM + /* 5552 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 5566 + /* 5557 */ MCD_OPC_CheckPredicate, + 13, + 186, + 3, + 0, // Skip to: 6516 + /* 5562 */ MCD_OPC_Decode, + 179, + 10, + 121, // Opcode: C_SEQ_S_MM + /* 5566 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 5580 + /* 5571 */ MCD_OPC_CheckPredicate, + 13, + 172, + 3, + 0, // Skip to: 6516 + /* 5576 */ MCD_OPC_Decode, + 155, + 10, + 121, // Opcode: C_NGL_S_MM + /* 5580 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 5594 + /* 5585 */ MCD_OPC_CheckPredicate, + 13, + 158, + 3, + 0, // Skip to: 6516 + /* 5590 */ MCD_OPC_Decode, + 137, + 10, + 121, // Opcode: C_LT_S_MM + /* 5594 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 5608 + /* 5599 */ MCD_OPC_CheckPredicate, + 13, + 144, + 3, + 0, // Skip to: 6516 + /* 5604 */ MCD_OPC_Decode, + 143, + 10, + 121, // Opcode: C_NGE_S_MM + /* 5608 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 5622 + /* 5613 */ MCD_OPC_CheckPredicate, + 13, + 130, + 3, + 0, // Skip to: 6516 + /* 5618 */ MCD_OPC_Decode, + 131, + 10, + 121, // Opcode: C_LE_S_MM + /* 5622 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 5636 + /* 5627 */ MCD_OPC_CheckPredicate, + 13, + 116, + 3, + 0, // Skip to: 6516 + /* 5632 */ MCD_OPC_Decode, + 161, + 10, + 121, // Opcode: C_NGT_S_MM + /* 5636 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 5650 + /* 5641 */ MCD_OPC_CheckPredicate, + 17, + 102, + 3, + 0, // Skip to: 6516 + /* 5646 */ MCD_OPC_Decode, + 249, + 9, + 122, // Opcode: C_F_D32_MM + /* 5650 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 5664 + /* 5655 */ MCD_OPC_CheckPredicate, + 17, + 88, + 3, + 0, // Skip to: 6516 + /* 5660 */ MCD_OPC_Decode, + 205, + 10, + 122, // Opcode: C_UN_D32_MM + /* 5664 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 5678 + /* 5669 */ MCD_OPC_CheckPredicate, + 17, + 74, + 3, + 0, // Skip to: 6516 + /* 5674 */ MCD_OPC_Decode, + 243, + 9, + 122, // Opcode: C_EQ_D32_MM + /* 5678 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 5692 + /* 5683 */ MCD_OPC_CheckPredicate, + 17, + 60, + 3, + 0, // Skip to: 6516 + /* 5688 */ MCD_OPC_Decode, + 187, + 10, + 122, // Opcode: C_UEQ_D32_MM + /* 5692 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 5706 + /* 5697 */ MCD_OPC_CheckPredicate, + 17, + 46, + 3, + 0, // Skip to: 6516 + /* 5702 */ MCD_OPC_Decode, + 169, + 10, + 122, // Opcode: C_OLT_D32_MM + /* 5706 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 5720 + /* 5711 */ MCD_OPC_CheckPredicate, + 17, + 32, + 3, + 0, // Skip to: 6516 + /* 5716 */ MCD_OPC_Decode, + 199, + 10, + 122, // Opcode: C_ULT_D32_MM + /* 5720 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 5734 + /* 5725 */ MCD_OPC_CheckPredicate, + 17, + 18, + 3, + 0, // Skip to: 6516 + /* 5730 */ MCD_OPC_Decode, + 163, + 10, + 122, // Opcode: C_OLE_D32_MM + /* 5734 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 5748 + /* 5739 */ MCD_OPC_CheckPredicate, + 17, + 4, + 3, + 0, // Skip to: 6516 + /* 5744 */ MCD_OPC_Decode, + 193, + 10, + 122, // Opcode: C_ULE_D32_MM + /* 5748 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 5762 + /* 5753 */ MCD_OPC_CheckPredicate, + 17, + 246, + 2, + 0, // Skip to: 6516 + /* 5758 */ MCD_OPC_Decode, + 181, + 10, + 122, // Opcode: C_SF_D32_MM + /* 5762 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 5776 + /* 5767 */ MCD_OPC_CheckPredicate, + 17, + 232, + 2, + 0, // Skip to: 6516 + /* 5772 */ MCD_OPC_Decode, + 145, + 10, + 122, // Opcode: C_NGLE_D32_MM + /* 5776 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 5790 + /* 5781 */ MCD_OPC_CheckPredicate, + 17, + 218, + 2, + 0, // Skip to: 6516 + /* 5786 */ MCD_OPC_Decode, + 175, + 10, + 122, // Opcode: C_SEQ_D32_MM + /* 5790 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 5804 + /* 5795 */ MCD_OPC_CheckPredicate, + 17, + 204, + 2, + 0, // Skip to: 6516 + /* 5800 */ MCD_OPC_Decode, + 151, + 10, + 122, // Opcode: C_NGL_D32_MM + /* 5804 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 5818 + /* 5809 */ MCD_OPC_CheckPredicate, + 17, + 190, + 2, + 0, // Skip to: 6516 + /* 5814 */ MCD_OPC_Decode, + 133, + 10, + 122, // Opcode: C_LT_D32_MM + /* 5818 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 5832 + /* 5823 */ MCD_OPC_CheckPredicate, + 17, + 176, + 2, + 0, // Skip to: 6516 + /* 5828 */ MCD_OPC_Decode, + 139, + 10, + 122, // Opcode: C_NGE_D32_MM + /* 5832 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 5846 + /* 5837 */ MCD_OPC_CheckPredicate, + 17, + 162, + 2, + 0, // Skip to: 6516 + /* 5842 */ MCD_OPC_Decode, + 255, + 9, + 122, // Opcode: C_LE_D32_MM + /* 5846 */ MCD_OPC_FilterValue, + 31, + 153, + 2, + 0, // Skip to: 6516 + /* 5851 */ MCD_OPC_CheckPredicate, + 17, + 148, + 2, + 0, // Skip to: 6516 + /* 5856 */ MCD_OPC_Decode, + 157, + 10, + 122, // Opcode: C_NGT_D32_MM + /* 5860 */ MCD_OPC_FilterValue, + 22, + 48, + 0, + 0, // Skip to: 5913 + /* 5865 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 5868 */ MCD_OPC_FilterValue, + 197, + 1, + 9, + 0, + 0, // Skip to: 5883 + /* 5874 */ MCD_OPC_CheckPredicate, + 8, + 125, + 2, + 0, // Skip to: 6516 + /* 5879 */ MCD_OPC_Decode, + 233, + 8, + 43, // Opcode: CMPGU_EQ_QB_MM + /* 5883 */ MCD_OPC_FilterValue, + 133, + 2, + 9, + 0, + 0, // Skip to: 5898 + /* 5889 */ MCD_OPC_CheckPredicate, + 8, + 110, + 2, + 0, // Skip to: 6516 + /* 5894 */ MCD_OPC_Decode, + 237, + 8, + 43, // Opcode: CMPGU_LT_QB_MM + /* 5898 */ MCD_OPC_FilterValue, + 197, + 2, + 100, + 2, + 0, // Skip to: 6516 + /* 5904 */ MCD_OPC_CheckPredicate, + 8, + 95, + 2, + 0, // Skip to: 6516 + /* 5909 */ MCD_OPC_Decode, + 235, + 8, + 43, // Opcode: CMPGU_LE_QB_MM + /* 5913 */ MCD_OPC_FilterValue, + 24, + 99, + 1, + 0, // Skip to: 6273 + /* 5918 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5921 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5935 + /* 5926 */ MCD_OPC_CheckPredicate, + 6, + 73, + 2, + 0, // Skip to: 6516 + /* 5931 */ MCD_OPC_Decode, + 245, + 14, + 88, // Opcode: LWL_MM + /* 5935 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5949 + /* 5940 */ MCD_OPC_CheckPredicate, + 6, + 59, + 2, + 0, // Skip to: 6516 + /* 5945 */ MCD_OPC_Decode, + 128, + 15, + 88, // Opcode: LWR_MM + /* 5949 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5963 + /* 5954 */ MCD_OPC_CheckPredicate, + 6, + 45, + 2, + 0, // Skip to: 6516 + /* 5959 */ MCD_OPC_Decode, + 167, + 18, + 89, // Opcode: PREF_MM + /* 5963 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 5977 + /* 5968 */ MCD_OPC_CheckPredicate, + 6, + 31, + 2, + 0, // Skip to: 6516 + /* 5973 */ MCD_OPC_Decode, + 214, + 14, + 88, // Opcode: LL_MM + /* 5977 */ MCD_OPC_FilterValue, + 6, + 115, + 0, + 0, // Skip to: 6097 + /* 5982 */ MCD_OPC_ExtractField, + 9, + 3, // Inst{11-9} ... + /* 5985 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 5999 + /* 5990 */ MCD_OPC_CheckPredicate, + 21, + 9, + 2, + 0, // Skip to: 6516 + /* 5995 */ MCD_OPC_Decode, + 165, + 14, + 123, // Opcode: LBuE_MM + /* 5999 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6013 + /* 6004 */ MCD_OPC_CheckPredicate, + 21, + 251, + 1, + 0, // Skip to: 6516 + /* 6009 */ MCD_OPC_Decode, + 203, + 14, + 123, // Opcode: LHuE_MM + /* 6013 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6027 + /* 6018 */ MCD_OPC_CheckPredicate, + 22, + 237, + 1, + 0, // Skip to: 6516 + /* 6023 */ MCD_OPC_Decode, + 244, + 14, + 123, // Opcode: LWLE_MM + /* 6027 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 6041 + /* 6032 */ MCD_OPC_CheckPredicate, + 22, + 223, + 1, + 0, // Skip to: 6516 + /* 6037 */ MCD_OPC_Decode, + 255, + 14, + 123, // Opcode: LWRE_MM + /* 6041 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 6055 + /* 6046 */ MCD_OPC_CheckPredicate, + 21, + 209, + 1, + 0, // Skip to: 6516 + /* 6051 */ MCD_OPC_Decode, + 155, + 14, + 123, // Opcode: LBE_MM + /* 6055 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 6069 + /* 6060 */ MCD_OPC_CheckPredicate, + 21, + 195, + 1, + 0, // Skip to: 6516 + /* 6065 */ MCD_OPC_Decode, + 195, + 14, + 123, // Opcode: LHE_MM + /* 6069 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 6083 + /* 6074 */ MCD_OPC_CheckPredicate, + 21, + 181, + 1, + 0, // Skip to: 6516 + /* 6079 */ MCD_OPC_Decode, + 213, + 14, + 123, // Opcode: LLE_MM + /* 6083 */ MCD_OPC_FilterValue, + 7, + 172, + 1, + 0, // Skip to: 6516 + /* 6088 */ MCD_OPC_CheckPredicate, + 21, + 167, + 1, + 0, // Skip to: 6516 + /* 6093 */ MCD_OPC_Decode, + 239, + 14, + 123, // Opcode: LWE_MM + /* 6097 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 6111 + /* 6102 */ MCD_OPC_CheckPredicate, + 6, + 153, + 1, + 0, // Skip to: 6516 + /* 6107 */ MCD_OPC_Decode, + 151, + 21, + 88, // Opcode: SWL_MM + /* 6111 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 6125 + /* 6116 */ MCD_OPC_CheckPredicate, + 6, + 139, + 1, + 0, // Skip to: 6516 + /* 6121 */ MCD_OPC_Decode, + 160, + 21, + 88, // Opcode: SWR_MM + /* 6125 */ MCD_OPC_FilterValue, + 10, + 115, + 0, + 0, // Skip to: 6245 + /* 6130 */ MCD_OPC_ExtractField, + 9, + 3, // Inst{11-9} ... + /* 6133 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6147 + /* 6138 */ MCD_OPC_CheckPredicate, + 22, + 117, + 1, + 0, // Skip to: 6516 + /* 6143 */ MCD_OPC_Decode, + 150, + 21, + 123, // Opcode: SWLE_MM + /* 6147 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6161 + /* 6152 */ MCD_OPC_CheckPredicate, + 22, + 103, + 1, + 0, // Skip to: 6516 + /* 6157 */ MCD_OPC_Decode, + 159, + 21, + 123, // Opcode: SWRE_MM + /* 6161 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6175 + /* 6166 */ MCD_OPC_CheckPredicate, + 21, + 89, + 1, + 0, // Skip to: 6516 + /* 6171 */ MCD_OPC_Decode, + 165, + 18, + 124, // Opcode: PREFE_MM + /* 6175 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 6189 + /* 6180 */ MCD_OPC_CheckPredicate, + 21, + 75, + 1, + 0, // Skip to: 6516 + /* 6185 */ MCD_OPC_Decode, + 151, + 8, + 124, // Opcode: CACHEE_MM + /* 6189 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 6203 + /* 6194 */ MCD_OPC_CheckPredicate, + 21, + 61, + 1, + 0, // Skip to: 6516 + /* 6199 */ MCD_OPC_Decode, + 239, + 18, + 123, // Opcode: SBE_MM + /* 6203 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 6217 + /* 6208 */ MCD_OPC_CheckPredicate, + 21, + 47, + 1, + 0, // Skip to: 6516 + /* 6213 */ MCD_OPC_Decode, + 176, + 19, + 123, // Opcode: SHE_MM + /* 6217 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 6231 + /* 6222 */ MCD_OPC_CheckPredicate, + 21, + 33, + 1, + 0, // Skip to: 6516 + /* 6227 */ MCD_OPC_Decode, + 248, + 18, + 123, // Opcode: SCE_MM + /* 6231 */ MCD_OPC_FilterValue, + 7, + 24, + 1, + 0, // Skip to: 6516 + /* 6236 */ MCD_OPC_CheckPredicate, + 21, + 19, + 1, + 0, // Skip to: 6516 + /* 6241 */ MCD_OPC_Decode, + 146, + 21, + 123, // Opcode: SWE_MM + /* 6245 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 6259 + /* 6250 */ MCD_OPC_CheckPredicate, + 6, + 5, + 1, + 0, // Skip to: 6516 + /* 6255 */ MCD_OPC_Decode, + 249, + 18, + 88, // Opcode: SC_MM + /* 6259 */ MCD_OPC_FilterValue, + 14, + 252, + 0, + 0, // Skip to: 6516 + /* 6264 */ MCD_OPC_CheckPredicate, + 6, + 247, + 0, + 0, // Skip to: 6516 + /* 6269 */ MCD_OPC_Decode, + 131, + 15, + 88, // Opcode: LWU_MM + /* 6273 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 6287 + /* 6278 */ MCD_OPC_CheckPredicate, + 6, + 233, + 0, + 0, // Skip to: 6516 + /* 6283 */ MCD_OPC_Decode, + 156, + 22, + 97, // Opcode: XORi_MM + /* 6287 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 6301 + /* 6292 */ MCD_OPC_CheckPredicate, + 6, + 219, + 0, + 0, // Skip to: 6516 + /* 6297 */ MCD_OPC_Decode, + 251, + 13, + 125, // Opcode: JALS_MM + /* 6301 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 6315 + /* 6306 */ MCD_OPC_CheckPredicate, + 6, + 205, + 0, + 0, // Skip to: 6516 + /* 6311 */ MCD_OPC_Decode, + 196, + 5, + 126, // Opcode: ADDIUPC_MM + /* 6315 */ MCD_OPC_FilterValue, + 36, + 9, + 0, + 0, // Skip to: 6329 + /* 6320 */ MCD_OPC_CheckPredicate, + 7, + 191, + 0, + 0, // Skip to: 6516 + /* 6325 */ MCD_OPC_Decode, + 134, + 20, + 86, // Opcode: SLTi_MM + /* 6329 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 6343 + /* 6334 */ MCD_OPC_CheckPredicate, + 6, + 177, + 0, + 0, // Skip to: 6516 + /* 6339 */ MCD_OPC_Decode, + 130, + 7, + 127, // Opcode: BEQ_MM + /* 6343 */ MCD_OPC_FilterValue, + 38, + 10, + 0, + 0, // Skip to: 6358 + /* 6348 */ MCD_OPC_CheckPredicate, + 19, + 163, + 0, + 0, // Skip to: 6516 + /* 6353 */ MCD_OPC_Decode, + 138, + 21, + 128, + 1, // Opcode: SWC1_MM + /* 6358 */ MCD_OPC_FilterValue, + 39, + 10, + 0, + 0, // Skip to: 6373 + /* 6363 */ MCD_OPC_CheckPredicate, + 19, + 148, + 0, + 0, // Skip to: 6516 + /* 6368 */ MCD_OPC_Decode, + 231, + 14, + 128, + 1, // Opcode: LWC1_MM + /* 6373 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 6387 + /* 6378 */ MCD_OPC_CheckPredicate, + 7, + 133, + 0, + 0, // Skip to: 6516 + /* 6383 */ MCD_OPC_Decode, + 137, + 20, + 86, // Opcode: SLTiu_MM + /* 6387 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 6401 + /* 6392 */ MCD_OPC_CheckPredicate, + 6, + 119, + 0, + 0, // Skip to: 6516 + /* 6397 */ MCD_OPC_Decode, + 233, + 7, + 127, // Opcode: BNE_MM + /* 6401 */ MCD_OPC_FilterValue, + 46, + 10, + 0, + 0, // Skip to: 6416 + /* 6406 */ MCD_OPC_CheckPredicate, + 18, + 105, + 0, + 0, // Skip to: 6516 + /* 6411 */ MCD_OPC_Decode, + 134, + 19, + 128, + 1, // Opcode: SDC1_MM + /* 6416 */ MCD_OPC_FilterValue, + 47, + 10, + 0, + 0, // Skip to: 6431 + /* 6421 */ MCD_OPC_CheckPredicate, + 18, + 90, + 0, + 0, // Skip to: 6516 + /* 6426 */ MCD_OPC_Decode, + 171, + 14, + 128, + 1, // Opcode: LDC1_MM + /* 6431 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 6445 + /* 6436 */ MCD_OPC_CheckPredicate, + 6, + 75, + 0, + 0, // Skip to: 6516 + /* 6441 */ MCD_OPC_Decode, + 158, + 6, + 97, // Opcode: ANDi_MM + /* 6445 */ MCD_OPC_FilterValue, + 53, + 9, + 0, + 0, // Skip to: 6459 + /* 6450 */ MCD_OPC_CheckPredicate, + 6, + 61, + 0, + 0, // Skip to: 6516 + /* 6455 */ MCD_OPC_Decode, + 145, + 14, + 125, // Opcode: J_MM + /* 6459 */ MCD_OPC_FilterValue, + 60, + 10, + 0, + 0, // Skip to: 6474 + /* 6464 */ MCD_OPC_CheckPredicate, + 6, + 47, + 0, + 0, // Skip to: 6516 + /* 6469 */ MCD_OPC_Decode, + 253, + 13, + 129, + 1, // Opcode: JALX_MM + /* 6474 */ MCD_OPC_FilterValue, + 61, + 9, + 0, + 0, // Skip to: 6488 + /* 6479 */ MCD_OPC_CheckPredicate, + 6, + 32, + 0, + 0, // Skip to: 6516 + /* 6484 */ MCD_OPC_Decode, + 254, + 13, + 125, // Opcode: JAL_MM + /* 6488 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 6502 + /* 6493 */ MCD_OPC_CheckPredicate, + 7, + 18, + 0, + 0, // Skip to: 6516 + /* 6498 */ MCD_OPC_Decode, + 165, + 21, + 87, // Opcode: SW_MM + /* 6502 */ MCD_OPC_FilterValue, + 63, + 9, + 0, + 0, // Skip to: 6516 + /* 6507 */ MCD_OPC_CheckPredicate, + 7, + 4, + 0, + 0, // Skip to: 6516 + /* 6512 */ MCD_OPC_Decode, + 137, + 15, + 87, // Opcode: LW_MM + /* 6516 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsDSP32[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 62, + 10, + 0, + 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, + 8, + 20, + 0, + 0, // Skip to: 33 + /* 13 */ MCD_OPC_Decode, + 144, + 21, + 130, + 1, // Opcode: SWDSP_MM + /* 18 */ MCD_OPC_FilterValue, + 63, + 10, + 0, + 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, + 8, + 5, + 0, + 0, // Skip to: 33 + /* 28 */ MCD_OPC_Decode, + 237, + 14, + 130, + 1, // Opcode: LWDSP_MM + /* 33 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsFP6432[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 21, + 39, + 1, + 0, // Skip to: 303 + /* 8 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 11 */ MCD_OPC_FilterValue, + 59, + 48, + 0, + 0, // Skip to: 64 + /* 16 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 19 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 34 + /* 24 */ MCD_OPC_CheckPredicate, + 20, + 48, + 1, + 0, // Skip to: 333 + /* 29 */ MCD_OPC_Decode, + 231, + 16, + 131, + 1, // Opcode: MTC1_D64_MM + /* 34 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 49 + /* 39 */ MCD_OPC_CheckPredicate, + 20, + 33, + 1, + 0, // Skip to: 333 + /* 44 */ MCD_OPC_Decode, + 226, + 15, + 132, + 1, // Opcode: MFHC1_D64_MM + /* 49 */ MCD_OPC_FilterValue, + 7, + 23, + 1, + 0, // Skip to: 333 + /* 54 */ MCD_OPC_CheckPredicate, + 20, + 18, + 1, + 0, // Skip to: 333 + /* 59 */ MCD_OPC_Decode, + 242, + 16, + 133, + 1, // Opcode: MTHC1_D64_MM + /* 64 */ MCD_OPC_FilterValue, + 123, + 16, + 0, + 0, // Skip to: 85 + /* 69 */ MCD_OPC_CheckPredicate, + 20, + 3, + 1, + 0, // Skip to: 333 + /* 74 */ MCD_OPC_CheckField, + 11, + 5, + 4, + 252, + 0, + 0, // Skip to: 333 + /* 81 */ MCD_OPC_Decode, + 238, + 12, + 111, // Opcode: FMOV_D64_MM + /* 85 */ MCD_OPC_FilterValue, + 176, + 2, + 10, + 0, + 0, // Skip to: 101 + /* 91 */ MCD_OPC_CheckPredicate, + 20, + 237, + 0, + 0, // Skip to: 333 + /* 96 */ MCD_OPC_Decode, + 148, + 12, + 134, + 1, // Opcode: FADD_D64_MM + /* 101 */ MCD_OPC_FilterValue, + 187, + 2, + 17, + 0, + 0, // Skip to: 124 + /* 107 */ MCD_OPC_CheckPredicate, + 20, + 221, + 0, + 0, // Skip to: 333 + /* 112 */ MCD_OPC_CheckField, + 11, + 5, + 9, + 214, + 0, + 0, // Skip to: 333 + /* 119 */ MCD_OPC_Decode, + 238, + 9, + 135, + 1, // Opcode: CVT_W_D64_MM + /* 124 */ MCD_OPC_FilterValue, + 240, + 2, + 10, + 0, + 0, // Skip to: 140 + /* 130 */ MCD_OPC_CheckPredicate, + 20, + 198, + 0, + 0, // Skip to: 333 + /* 135 */ MCD_OPC_Decode, + 165, + 13, + 134, + 1, // Opcode: FSUB_D64_MM + /* 140 */ MCD_OPC_FilterValue, + 176, + 3, + 10, + 0, + 0, // Skip to: 156 + /* 146 */ MCD_OPC_CheckPredicate, + 20, + 182, + 0, + 0, // Skip to: 333 + /* 151 */ MCD_OPC_Decode, + 249, + 12, + 134, + 1, // Opcode: FMUL_D64_MM + /* 156 */ MCD_OPC_FilterValue, + 240, + 3, + 10, + 0, + 0, // Skip to: 172 + /* 162 */ MCD_OPC_CheckPredicate, + 20, + 166, + 0, + 0, // Skip to: 333 + /* 167 */ MCD_OPC_Decode, + 187, + 12, + 134, + 1, // Opcode: FDIV_D64_MM + /* 172 */ MCD_OPC_FilterValue, + 187, + 4, + 45, + 0, + 0, // Skip to: 223 + /* 178 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 181 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 195 + /* 186 */ MCD_OPC_CheckPredicate, + 20, + 142, + 0, + 0, // Skip to: 333 + /* 191 */ MCD_OPC_Decode, + 219, + 18, + 111, // Opcode: RSQRT_D64_MM + /* 195 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 209 + /* 200 */ MCD_OPC_CheckPredicate, + 20, + 128, + 0, + 0, // Skip to: 333 + /* 205 */ MCD_OPC_Decode, + 157, + 13, + 111, // Opcode: FSQRT_D64_MM + /* 209 */ MCD_OPC_FilterValue, + 10, + 119, + 0, + 0, // Skip to: 333 + /* 214 */ MCD_OPC_CheckPredicate, + 20, + 114, + 0, + 0, // Skip to: 333 + /* 219 */ MCD_OPC_Decode, + 186, + 18, + 111, // Opcode: RECIP_D64_MM + /* 223 */ MCD_OPC_FilterValue, + 251, + 6, + 104, + 0, + 0, // Skip to: 333 + /* 229 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 232 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 246 + /* 237 */ MCD_OPC_CheckPredicate, + 20, + 91, + 0, + 0, // Skip to: 333 + /* 242 */ MCD_OPC_Decode, + 211, + 9, + 110, // Opcode: CVT_D64_S_MM + /* 246 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 261 + /* 251 */ MCD_OPC_CheckPredicate, + 20, + 77, + 0, + 0, // Skip to: 333 + /* 256 */ MCD_OPC_Decode, + 227, + 9, + 135, + 1, // Opcode: CVT_S_D64_MM + /* 261 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 275 + /* 266 */ MCD_OPC_CheckPredicate, + 20, + 62, + 0, + 0, // Skip to: 333 + /* 271 */ MCD_OPC_Decode, + 141, + 12, + 111, // Opcode: FABS_D64_MM + /* 275 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 289 + /* 280 */ MCD_OPC_CheckPredicate, + 20, + 48, + 0, + 0, // Skip to: 333 + /* 285 */ MCD_OPC_Decode, + 130, + 13, + 111, // Opcode: FNEG_D64_MM + /* 289 */ MCD_OPC_FilterValue, + 6, + 39, + 0, + 0, // Skip to: 333 + /* 294 */ MCD_OPC_CheckPredicate, + 20, + 34, + 0, + 0, // Skip to: 333 + /* 299 */ MCD_OPC_Decode, + 213, + 9, + 110, // Opcode: CVT_D64_W_MM + /* 303 */ MCD_OPC_FilterValue, + 46, + 10, + 0, + 0, // Skip to: 318 + /* 308 */ MCD_OPC_CheckPredicate, + 23, + 20, + 0, + 0, // Skip to: 333 + /* 313 */ MCD_OPC_Decode, + 133, + 19, + 128, + 1, // Opcode: SDC1_D64_MMR6 + /* 318 */ MCD_OPC_FilterValue, + 47, + 10, + 0, + 0, // Skip to: 333 + /* 323 */ MCD_OPC_CheckPredicate, + 23, + 5, + 0, + 0, // Skip to: 333 + /* 328 */ MCD_OPC_Decode, + 170, + 14, + 128, + 1, // Opcode: LDC1_D64_MMR6 + /* 333 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsR616[] = { + /* 0 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 3 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 41 + /* 8 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 26 + /* 16 */ MCD_OPC_CheckPredicate, + 24, + 173, + 1, + 0, // Skip to: 450 + /* 21 */ MCD_OPC_Decode, + 233, + 5, + 136, + 1, // Opcode: ADDU16_MMR6 + /* 26 */ MCD_OPC_FilterValue, + 1, + 163, + 1, + 0, // Skip to: 450 + /* 31 */ MCD_OPC_CheckPredicate, + 24, + 158, + 1, + 0, // Skip to: 450 + /* 36 */ MCD_OPC_Decode, + 232, + 20, + 136, + 1, // Opcode: SUBU16_MMR6 + /* 41 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 55 + /* 46 */ MCD_OPC_CheckPredicate, + 24, + 143, + 1, + 0, // Skip to: 450 + /* 51 */ MCD_OPC_Decode, + 158, + 16, + 22, // Opcode: MOVE16_MMR6 + /* 55 */ MCD_OPC_FilterValue, + 9, + 31, + 0, + 0, // Skip to: 91 + /* 60 */ MCD_OPC_ExtractField, + 0, + 1, // Inst{0} ... + /* 63 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 77 + /* 68 */ MCD_OPC_CheckPredicate, + 24, + 121, + 1, + 0, // Skip to: 450 + /* 73 */ MCD_OPC_Decode, + 242, + 19, + 23, // Opcode: SLL16_MMR6 + /* 77 */ MCD_OPC_FilterValue, + 1, + 112, + 1, + 0, // Skip to: 450 + /* 82 */ MCD_OPC_CheckPredicate, + 24, + 107, + 1, + 0, // Skip to: 450 + /* 87 */ MCD_OPC_Decode, + 173, + 20, + 23, // Opcode: SRL16_MMR6 + /* 91 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 105 + /* 96 */ MCD_OPC_CheckPredicate, + 24, + 93, + 1, + 0, // Skip to: 450 + /* 101 */ MCD_OPC_Decode, + 150, + 6, + 24, // Opcode: ANDI16_MMR6 + /* 105 */ MCD_OPC_FilterValue, + 17, + 228, + 0, + 0, // Skip to: 338 + /* 110 */ MCD_OPC_ExtractField, + 2, + 1, // Inst{2} ... + /* 113 */ MCD_OPC_FilterValue, + 0, + 206, + 0, + 0, // Skip to: 324 + /* 118 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 121 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 159 + /* 126 */ MCD_OPC_ExtractField, + 3, + 1, // Inst{3} ... + /* 129 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 144 + /* 134 */ MCD_OPC_CheckPredicate, + 24, + 55, + 1, + 0, // Skip to: 450 + /* 139 */ MCD_OPC_Decode, + 217, + 17, + 137, + 1, // Opcode: NOT16_MMR6 + /* 144 */ MCD_OPC_FilterValue, + 1, + 45, + 1, + 0, // Skip to: 450 + /* 149 */ MCD_OPC_CheckPredicate, + 24, + 40, + 1, + 0, // Skip to: 450 + /* 154 */ MCD_OPC_Decode, + 147, + 22, + 138, + 1, // Opcode: XOR16_MMR6 + /* 159 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 197 + /* 164 */ MCD_OPC_ExtractField, + 3, + 1, // Inst{3} ... + /* 167 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 182 + /* 172 */ MCD_OPC_CheckPredicate, + 24, + 17, + 1, + 0, // Skip to: 450 + /* 177 */ MCD_OPC_Decode, + 147, + 6, + 138, + 1, // Opcode: AND16_MMR6 + /* 182 */ MCD_OPC_FilterValue, + 1, + 7, + 1, + 0, // Skip to: 450 + /* 187 */ MCD_OPC_CheckPredicate, + 24, + 2, + 1, + 0, // Skip to: 450 + /* 192 */ MCD_OPC_Decode, + 222, + 17, + 138, + 1, // Opcode: OR16_MMR6 + /* 197 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 233 + /* 202 */ MCD_OPC_ExtractField, + 3, + 1, // Inst{3} ... + /* 205 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 219 + /* 210 */ MCD_OPC_CheckPredicate, + 24, + 235, + 0, + 0, // Skip to: 450 + /* 215 */ MCD_OPC_Decode, + 247, + 14, + 27, // Opcode: LWM16_MMR6 + /* 219 */ MCD_OPC_FilterValue, + 1, + 226, + 0, + 0, // Skip to: 450 + /* 224 */ MCD_OPC_CheckPredicate, + 24, + 221, + 0, + 0, // Skip to: 450 + /* 229 */ MCD_OPC_Decode, + 153, + 21, + 27, // Opcode: SWM16_MMR6 + /* 233 */ MCD_OPC_FilterValue, + 3, + 212, + 0, + 0, // Skip to: 450 + /* 238 */ MCD_OPC_ExtractField, + 3, + 2, // Inst{4-3} ... + /* 241 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 256 + /* 246 */ MCD_OPC_CheckPredicate, + 24, + 199, + 0, + 0, // Skip to: 450 + /* 251 */ MCD_OPC_Decode, + 138, + 14, + 139, + 1, // Opcode: JRC16_MMR6 + /* 256 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 271 + /* 261 */ MCD_OPC_CheckPredicate, + 24, + 184, + 0, + 0, // Skip to: 450 + /* 266 */ MCD_OPC_Decode, + 243, + 13, + 139, + 1, // Opcode: JALRC16_MMR6 + /* 271 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 286 + /* 276 */ MCD_OPC_CheckPredicate, + 24, + 169, + 0, + 0, // Skip to: 450 + /* 281 */ MCD_OPC_Decode, + 139, + 14, + 140, + 1, // Opcode: JRCADDIUSP_MMR6 + /* 286 */ MCD_OPC_FilterValue, + 3, + 159, + 0, + 0, // Skip to: 450 + /* 291 */ MCD_OPC_ExtractField, + 5, + 1, // Inst{5} ... + /* 294 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 309 + /* 299 */ MCD_OPC_CheckPredicate, + 24, + 146, + 0, + 0, // Skip to: 450 + /* 304 */ MCD_OPC_Decode, + 248, + 7, + 141, + 1, // Opcode: BREAK16_MMR6 + /* 309 */ MCD_OPC_FilterValue, + 1, + 136, + 0, + 0, // Skip to: 450 + /* 314 */ MCD_OPC_CheckPredicate, + 24, + 131, + 0, + 0, // Skip to: 450 + /* 319 */ MCD_OPC_Decode, + 255, + 18, + 141, + 1, // Opcode: SDBBP16_MMR6 + /* 324 */ MCD_OPC_FilterValue, + 1, + 121, + 0, + 0, // Skip to: 450 + /* 329 */ MCD_OPC_CheckPredicate, + 24, + 116, + 0, + 0, // Skip to: 450 + /* 334 */ MCD_OPC_Decode, + 160, + 16, + 37, // Opcode: MOVEP_MMR6 + /* 338 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 352 + /* 343 */ MCD_OPC_CheckPredicate, + 24, + 102, + 0, + 0, // Skip to: 450 + /* 348 */ MCD_OPC_Decode, + 236, + 18, + 21, // Opcode: SB16_MMR6 + /* 352 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 366 + /* 357 */ MCD_OPC_CheckPredicate, + 24, + 88, + 0, + 0, // Skip to: 450 + /* 362 */ MCD_OPC_Decode, + 254, + 6, + 38, // Opcode: BEQZC16_MMR6 + /* 366 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 380 + /* 371 */ MCD_OPC_CheckPredicate, + 24, + 74, + 0, + 0, // Skip to: 450 + /* 376 */ MCD_OPC_Decode, + 173, + 19, + 21, // Opcode: SH16_MMR6 + /* 380 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 394 + /* 385 */ MCD_OPC_CheckPredicate, + 24, + 60, + 0, + 0, // Skip to: 450 + /* 390 */ MCD_OPC_Decode, + 229, + 7, + 38, // Opcode: BNEZC16_MMR6 + /* 394 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 408 + /* 399 */ MCD_OPC_CheckPredicate, + 24, + 46, + 0, + 0, // Skip to: 450 + /* 404 */ MCD_OPC_Decode, + 162, + 21, + 31, // Opcode: SWSP_MMR6 + /* 408 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 422 + /* 413 */ MCD_OPC_CheckPredicate, + 24, + 32, + 0, + 0, // Skip to: 450 + /* 418 */ MCD_OPC_Decode, + 212, + 6, + 39, // Opcode: BC16_MMR6 + /* 422 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 436 + /* 427 */ MCD_OPC_CheckPredicate, + 24, + 18, + 0, + 0, // Skip to: 450 + /* 432 */ MCD_OPC_Decode, + 135, + 21, + 21, // Opcode: SW16_MMR6 + /* 436 */ MCD_OPC_FilterValue, + 59, + 9, + 0, + 0, // Skip to: 450 + /* 441 */ MCD_OPC_CheckPredicate, + 24, + 4, + 0, + 0, // Skip to: 450 + /* 446 */ MCD_OPC_Decode, + 206, + 14, + 40, // Opcode: LI16_MMR6 + /* 450 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsR632[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 98, + 4, + 0, // Skip to: 1130 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 112, + 0, + 0, // Skip to: 128 + /* 16 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 54, + 0, + 0, // Skip to: 78 + /* 24 */ MCD_OPC_ExtractField, + 11, + 15, // Inst{25-11} ... + /* 27 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 41 + /* 32 */ MCD_OPC_CheckPredicate, + 24, + 32, + 0, + 0, // Skip to: 69 + /* 37 */ MCD_OPC_Decode, + 195, + 20, + 0, // Opcode: SSNOP_MMR6 + /* 41 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 55 + /* 46 */ MCD_OPC_CheckPredicate, + 24, + 18, + 0, + 0, // Skip to: 69 + /* 51 */ MCD_OPC_Decode, + 224, + 11, + 0, // Opcode: EHB_MMR6 + /* 55 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 69 + /* 60 */ MCD_OPC_CheckPredicate, + 24, + 4, + 0, + 0, // Skip to: 69 + /* 65 */ MCD_OPC_Decode, + 237, + 17, + 0, // Opcode: PAUSE_MMR6 + /* 69 */ MCD_OPC_CheckPredicate, + 24, + 78, + 12, + 0, // Skip to: 3224 + /* 74 */ MCD_OPC_Decode, + 255, + 19, + 41, // Opcode: SLL_MMR6 + /* 78 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 92 + /* 83 */ MCD_OPC_CheckPredicate, + 24, + 64, + 12, + 0, // Skip to: 3224 + /* 88 */ MCD_OPC_Decode, + 155, + 19, + 44, // Opcode: SELEQZ_MMR6 + /* 92 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 106 + /* 97 */ MCD_OPC_CheckPredicate, + 24, + 50, + 12, + 0, // Skip to: 3224 + /* 102 */ MCD_OPC_Decode, + 162, + 19, + 44, // Opcode: SELNEZ_MMR6 + /* 106 */ MCD_OPC_FilterValue, + 7, + 41, + 12, + 0, // Skip to: 3224 + /* 111 */ MCD_OPC_CheckPredicate, + 24, + 36, + 12, + 0, // Skip to: 3224 + /* 116 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 29, + 12, + 0, // Skip to: 3224 + /* 123 */ MCD_OPC_Decode, + 181, + 18, + 142, + 1, // Opcode: RDHWR_MMR6 + /* 128 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 142 + /* 133 */ MCD_OPC_CheckPredicate, + 24, + 14, + 12, + 0, // Skip to: 3224 + /* 138 */ MCD_OPC_Decode, + 250, + 7, + 45, // Opcode: BREAK_MMR6 + /* 142 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 156 + /* 147 */ MCD_OPC_CheckPredicate, + 24, + 0, + 12, + 0, // Skip to: 3224 + /* 152 */ MCD_OPC_Decode, + 237, + 13, + 46, // Opcode: INS_MMR6 + /* 156 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 178 + /* 161 */ MCD_OPC_CheckPredicate, + 24, + 242, + 11, + 0, // Skip to: 3224 + /* 166 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 235, + 11, + 0, // Skip to: 3224 + /* 173 */ MCD_OPC_Decode, + 218, + 14, + 143, + 1, // Opcode: LSA_MMR6 + /* 178 */ MCD_OPC_FilterValue, + 16, + 136, + 0, + 0, // Skip to: 319 + /* 183 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 186 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 207 + /* 191 */ MCD_OPC_CheckPredicate, + 24, + 212, + 11, + 0, // Skip to: 3224 + /* 196 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 205, + 11, + 0, // Skip to: 3224 + /* 203 */ MCD_OPC_Decode, + 224, + 8, + 14, // Opcode: CLZ_MMR6 + /* 207 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 221 + /* 212 */ MCD_OPC_CheckPredicate, + 24, + 191, + 11, + 0, // Skip to: 3224 + /* 217 */ MCD_OPC_Decode, + 134, + 6, + 44, // Opcode: ADD_MMR6 + /* 221 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 235 + /* 226 */ MCD_OPC_CheckPredicate, + 24, + 177, + 11, + 0, // Skip to: 3224 + /* 231 */ MCD_OPC_Decode, + 238, + 5, + 44, // Opcode: ADDU_MMR6 + /* 235 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 249 + /* 240 */ MCD_OPC_CheckPredicate, + 24, + 163, + 11, + 0, // Skip to: 3224 + /* 245 */ MCD_OPC_Decode, + 255, + 20, + 44, // Opcode: SUB_MMR6 + /* 249 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 263 + /* 254 */ MCD_OPC_CheckPredicate, + 24, + 149, + 11, + 0, // Skip to: 3224 + /* 259 */ MCD_OPC_Decode, + 237, + 20, + 44, // Opcode: SUBU_MMR6 + /* 263 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 277 + /* 268 */ MCD_OPC_CheckPredicate, + 24, + 135, + 11, + 0, // Skip to: 3224 + /* 273 */ MCD_OPC_Decode, + 154, + 6, + 44, // Opcode: AND_MMR6 + /* 277 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 291 + /* 282 */ MCD_OPC_CheckPredicate, + 24, + 121, + 11, + 0, // Skip to: 3224 + /* 287 */ MCD_OPC_Decode, + 227, + 17, + 44, // Opcode: OR_MMR6 + /* 291 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 305 + /* 296 */ MCD_OPC_CheckPredicate, + 24, + 107, + 11, + 0, // Skip to: 3224 + /* 301 */ MCD_OPC_Decode, + 214, + 17, + 44, // Opcode: NOR_MMR6 + /* 305 */ MCD_OPC_FilterValue, + 12, + 98, + 11, + 0, // Skip to: 3224 + /* 310 */ MCD_OPC_CheckPredicate, + 24, + 93, + 11, + 0, // Skip to: 3224 + /* 315 */ MCD_OPC_Decode, + 152, + 22, + 44, // Opcode: XOR_MMR6 + /* 319 */ MCD_OPC_FilterValue, + 24, + 115, + 0, + 0, // Skip to: 439 + /* 324 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 327 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 341 + /* 332 */ MCD_OPC_CheckPredicate, + 24, + 71, + 11, + 0, // Skip to: 3224 + /* 337 */ MCD_OPC_Decode, + 180, + 17, + 44, // Opcode: MUL_MMR6 + /* 341 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 355 + /* 346 */ MCD_OPC_CheckPredicate, + 24, + 57, + 11, + 0, // Skip to: 3224 + /* 351 */ MCD_OPC_Decode, + 140, + 17, + 44, // Opcode: MUH_MMR6 + /* 355 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 369 + /* 360 */ MCD_OPC_CheckPredicate, + 24, + 43, + 11, + 0, // Skip to: 3224 + /* 365 */ MCD_OPC_Decode, + 174, + 17, + 44, // Opcode: MULU_MMR6 + /* 369 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 383 + /* 374 */ MCD_OPC_CheckPredicate, + 24, + 29, + 11, + 0, // Skip to: 3224 + /* 379 */ MCD_OPC_Decode, + 139, + 17, + 44, // Opcode: MUHU_MMR6 + /* 383 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 397 + /* 388 */ MCD_OPC_CheckPredicate, + 24, + 15, + 11, + 0, // Skip to: 3224 + /* 393 */ MCD_OPC_Decode, + 242, + 10, + 44, // Opcode: DIV_MMR6 + /* 397 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 411 + /* 402 */ MCD_OPC_CheckPredicate, + 24, + 1, + 11, + 0, // Skip to: 3224 + /* 407 */ MCD_OPC_Decode, + 148, + 16, + 44, // Opcode: MOD_MMR6 + /* 411 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 425 + /* 416 */ MCD_OPC_CheckPredicate, + 24, + 243, + 10, + 0, // Skip to: 3224 + /* 421 */ MCD_OPC_Decode, + 241, + 10, + 44, // Opcode: DIVU_MMR6 + /* 425 */ MCD_OPC_FilterValue, + 7, + 234, + 10, + 0, // Skip to: 3224 + /* 430 */ MCD_OPC_CheckPredicate, + 24, + 229, + 10, + 0, // Skip to: 3224 + /* 435 */ MCD_OPC_Decode, + 147, + 16, + 44, // Opcode: MODU_MMR6 + /* 439 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 461 + /* 444 */ MCD_OPC_CheckPredicate, + 24, + 215, + 10, + 0, // Skip to: 3224 + /* 449 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 208, + 10, + 0, // Skip to: 3224 + /* 456 */ MCD_OPC_Decode, + 142, + 6, + 144, + 1, // Opcode: ALIGN_MMR6 + /* 461 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 475 + /* 466 */ MCD_OPC_CheckPredicate, + 24, + 193, + 10, + 0, // Skip to: 3224 + /* 471 */ MCD_OPC_Decode, + 137, + 12, + 55, // Opcode: EXT_MMR6 + /* 475 */ MCD_OPC_FilterValue, + 52, + 45, + 0, + 0, // Skip to: 525 + /* 480 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 483 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 504 + /* 488 */ MCD_OPC_CheckPredicate, + 24, + 171, + 10, + 0, // Skip to: 3224 + /* 493 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 164, + 10, + 0, // Skip to: 3224 + /* 500 */ MCD_OPC_Decode, + 222, + 15, + 57, // Opcode: MFHC0_MMR6 + /* 504 */ MCD_OPC_FilterValue, + 11, + 155, + 10, + 0, // Skip to: 3224 + /* 509 */ MCD_OPC_CheckPredicate, + 24, + 150, + 10, + 0, // Skip to: 3224 + /* 514 */ MCD_OPC_CheckField, + 14, + 2, + 0, + 143, + 10, + 0, // Skip to: 3224 + /* 521 */ MCD_OPC_Decode, + 238, + 16, + 58, // Opcode: MTHC0_MMR6 + /* 525 */ MCD_OPC_FilterValue, + 60, + 66, + 2, + 0, // Skip to: 1108 + /* 530 */ MCD_OPC_ExtractField, + 14, + 2, // Inst{15-14} ... + /* 533 */ MCD_OPC_FilterValue, + 0, + 138, + 0, + 0, // Skip to: 676 + /* 538 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 541 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 555 + /* 546 */ MCD_OPC_CheckPredicate, + 24, + 113, + 10, + 0, // Skip to: 3224 + /* 551 */ MCD_OPC_Decode, + 213, + 15, + 57, // Opcode: MFC0_MMR6 + /* 555 */ MCD_OPC_FilterValue, + 5, + 45, + 0, + 0, // Skip to: 605 + /* 560 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 563 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 584 + /* 568 */ MCD_OPC_CheckPredicate, + 24, + 91, + 10, + 0, // Skip to: 3224 + /* 573 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 84, + 10, + 0, // Skip to: 3224 + /* 580 */ MCD_OPC_Decode, + 219, + 11, + 81, // Opcode: DVP_MMR6 + /* 584 */ MCD_OPC_FilterValue, + 7, + 75, + 10, + 0, // Skip to: 3224 + /* 589 */ MCD_OPC_CheckPredicate, + 24, + 70, + 10, + 0, // Skip to: 3224 + /* 594 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 63, + 10, + 0, // Skip to: 3224 + /* 601 */ MCD_OPC_Decode, + 236, + 11, + 81, // Opcode: EVP_MMR6 + /* 605 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 619 + /* 610 */ MCD_OPC_CheckPredicate, + 24, + 49, + 10, + 0, // Skip to: 3224 + /* 615 */ MCD_OPC_Decode, + 228, + 16, + 58, // Opcode: MTC0_MMR6 + /* 619 */ MCD_OPC_FilterValue, + 12, + 16, + 0, + 0, // Skip to: 640 + /* 624 */ MCD_OPC_CheckPredicate, + 24, + 35, + 10, + 0, // Skip to: 3224 + /* 629 */ MCD_OPC_CheckField, + 11, + 3, + 1, + 28, + 10, + 0, // Skip to: 3224 + /* 636 */ MCD_OPC_Decode, + 178, + 7, + 75, // Opcode: BITSWAP_MMR6 + /* 640 */ MCD_OPC_FilterValue, + 28, + 19, + 10, + 0, // Skip to: 3224 + /* 645 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 648 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 662 + /* 653 */ MCD_OPC_CheckPredicate, + 24, + 6, + 10, + 0, // Skip to: 3224 + /* 658 */ MCD_OPC_Decode, + 245, + 13, + 69, // Opcode: JALRC_MMR6 + /* 662 */ MCD_OPC_FilterValue, + 3, + 253, + 9, + 0, // Skip to: 3224 + /* 667 */ MCD_OPC_CheckPredicate, + 24, + 248, + 9, + 0, // Skip to: 3224 + /* 672 */ MCD_OPC_Decode, + 244, + 13, + 69, // Opcode: JALRC_HB_MMR6 + /* 676 */ MCD_OPC_FilterValue, + 1, + 10, + 1, + 0, // Skip to: 947 + /* 681 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 684 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 734 + /* 689 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 692 */ MCD_OPC_FilterValue, + 13, + 16, + 0, + 0, // Skip to: 713 + /* 697 */ MCD_OPC_CheckPredicate, + 24, + 218, + 9, + 0, // Skip to: 3224 + /* 702 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 211, + 9, + 0, // Skip to: 3224 + /* 709 */ MCD_OPC_Decode, + 223, + 21, + 0, // Opcode: TLBINV_MMR6 + /* 713 */ MCD_OPC_FilterValue, + 29, + 202, + 9, + 0, // Skip to: 3224 + /* 718 */ MCD_OPC_CheckPredicate, + 24, + 197, + 9, + 0, // Skip to: 3224 + /* 723 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 190, + 9, + 0, // Skip to: 3224 + /* 730 */ MCD_OPC_Decode, + 252, + 10, + 81, // Opcode: DI_MMR6 + /* 734 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 770 + /* 739 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 742 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 756 + /* 747 */ MCD_OPC_CheckPredicate, + 24, + 168, + 9, + 0, // Skip to: 3224 + /* 752 */ MCD_OPC_Decode, + 204, + 8, + 69, // Opcode: CLO_MMR6 + /* 756 */ MCD_OPC_FilterValue, + 20, + 159, + 9, + 0, // Skip to: 3224 + /* 761 */ MCD_OPC_CheckPredicate, + 24, + 154, + 9, + 0, // Skip to: 3224 + /* 766 */ MCD_OPC_Decode, + 219, + 15, + 79, // Opcode: MFC2_MMR6 + /* 770 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 820 + /* 775 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 778 */ MCD_OPC_FilterValue, + 13, + 16, + 0, + 0, // Skip to: 799 + /* 783 */ MCD_OPC_CheckPredicate, + 24, + 132, + 9, + 0, // Skip to: 3224 + /* 788 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 125, + 9, + 0, // Skip to: 3224 + /* 795 */ MCD_OPC_Decode, + 222, + 21, + 0, // Opcode: TLBINVF_MMR6 + /* 799 */ MCD_OPC_FilterValue, + 29, + 116, + 9, + 0, // Skip to: 3224 + /* 804 */ MCD_OPC_CheckPredicate, + 24, + 111, + 9, + 0, // Skip to: 3224 + /* 809 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 104, + 9, + 0, // Skip to: 3224 + /* 816 */ MCD_OPC_Decode, + 227, + 11, + 81, // Opcode: EI_MMR6 + /* 820 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 841 + /* 825 */ MCD_OPC_CheckPredicate, + 24, + 90, + 9, + 0, // Skip to: 3224 + /* 830 */ MCD_OPC_CheckField, + 6, + 5, + 20, + 83, + 9, + 0, // Skip to: 3224 + /* 837 */ MCD_OPC_Decode, + 235, + 16, + 80, // Opcode: MTC2_MMR6 + /* 841 */ MCD_OPC_FilterValue, + 4, + 23, + 0, + 0, // Skip to: 869 + /* 846 */ MCD_OPC_CheckPredicate, + 25, + 69, + 9, + 0, // Skip to: 3224 + /* 851 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 62, + 9, + 0, // Skip to: 3224 + /* 858 */ MCD_OPC_CheckField, + 6, + 3, + 5, + 55, + 9, + 0, // Skip to: 3224 + /* 865 */ MCD_OPC_Decode, + 192, + 13, + 81, // Opcode: GINVI_MMR6 + /* 869 */ MCD_OPC_FilterValue, + 5, + 23, + 0, + 0, // Skip to: 897 + /* 874 */ MCD_OPC_CheckPredicate, + 24, + 41, + 9, + 0, // Skip to: 3224 + /* 879 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 34, + 9, + 0, // Skip to: 3224 + /* 886 */ MCD_OPC_CheckField, + 6, + 5, + 13, + 27, + 9, + 0, // Skip to: 3224 + /* 893 */ MCD_OPC_Decode, + 172, + 21, + 76, // Opcode: SYNC_MMR6 + /* 897 */ MCD_OPC_FilterValue, + 6, + 24, + 0, + 0, // Skip to: 926 + /* 902 */ MCD_OPC_CheckPredicate, + 25, + 13, + 9, + 0, // Skip to: 3224 + /* 907 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 6, + 9, + 0, // Skip to: 3224 + /* 914 */ MCD_OPC_CheckField, + 6, + 3, + 5, + 255, + 8, + 0, // Skip to: 3224 + /* 921 */ MCD_OPC_Decode, + 194, + 13, + 145, + 1, // Opcode: GINVT_MMR6 + /* 926 */ MCD_OPC_FilterValue, + 7, + 245, + 8, + 0, // Skip to: 3224 + /* 931 */ MCD_OPC_CheckPredicate, + 24, + 240, + 8, + 0, // Skip to: 3224 + /* 936 */ MCD_OPC_CheckField, + 6, + 5, + 12, + 233, + 8, + 0, // Skip to: 3224 + /* 943 */ MCD_OPC_Decode, + 144, + 22, + 69, // Opcode: WSBH_MMR6 + /* 947 */ MCD_OPC_FilterValue, + 2, + 45, + 0, + 0, // Skip to: 997 + /* 952 */ MCD_OPC_ExtractField, + 6, + 8, // Inst{13-6} ... + /* 955 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 969 + /* 960 */ MCD_OPC_CheckPredicate, + 24, + 211, + 8, + 0, // Skip to: 3224 + /* 965 */ MCD_OPC_Decode, + 227, + 15, + 79, // Opcode: MFHC2_MMR6 + /* 969 */ MCD_OPC_FilterValue, + 77, + 9, + 0, + 0, // Skip to: 983 + /* 974 */ MCD_OPC_CheckPredicate, + 24, + 197, + 8, + 0, // Skip to: 3224 + /* 979 */ MCD_OPC_Decode, + 138, + 22, + 77, // Opcode: WAIT_MMR6 + /* 983 */ MCD_OPC_FilterValue, + 116, + 188, + 8, + 0, // Skip to: 3224 + /* 988 */ MCD_OPC_CheckPredicate, + 24, + 183, + 8, + 0, // Skip to: 3224 + /* 993 */ MCD_OPC_Decode, + 243, + 16, + 80, // Opcode: MTHC2_MMR6 + /* 997 */ MCD_OPC_FilterValue, + 3, + 174, + 8, + 0, // Skip to: 3224 + /* 1002 */ MCD_OPC_ExtractField, + 6, + 8, // Inst{13-6} ... + /* 1005 */ MCD_OPC_FilterValue, + 109, + 9, + 0, + 0, // Skip to: 1019 + /* 1010 */ MCD_OPC_CheckPredicate, + 24, + 161, + 8, + 0, // Skip to: 3224 + /* 1015 */ MCD_OPC_Decode, + 129, + 19, + 77, // Opcode: SDBBP_MMR6 + /* 1019 */ MCD_OPC_FilterValue, + 133, + 1, + 9, + 0, + 0, // Skip to: 1034 + /* 1025 */ MCD_OPC_CheckPredicate, + 24, + 146, + 8, + 0, // Skip to: 3224 + /* 1030 */ MCD_OPC_Decode, + 182, + 18, + 69, // Opcode: RDPGPR_MMR6 + /* 1034 */ MCD_OPC_FilterValue, + 141, + 1, + 16, + 0, + 0, // Skip to: 1056 + /* 1040 */ MCD_OPC_CheckPredicate, + 24, + 131, + 8, + 0, // Skip to: 3224 + /* 1045 */ MCD_OPC_CheckField, + 16, + 10, + 0, + 124, + 8, + 0, // Skip to: 3224 + /* 1052 */ MCD_OPC_Decode, + 230, + 10, + 0, // Opcode: DERET_MMR6 + /* 1056 */ MCD_OPC_FilterValue, + 197, + 1, + 9, + 0, + 0, // Skip to: 1071 + /* 1062 */ MCD_OPC_CheckPredicate, + 24, + 109, + 8, + 0, // Skip to: 3224 + /* 1067 */ MCD_OPC_Decode, + 141, + 22, + 69, // Opcode: WRPGPR_MMR6 + /* 1071 */ MCD_OPC_FilterValue, + 205, + 1, + 99, + 8, + 0, // Skip to: 3224 + /* 1077 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 1080 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1094 + /* 1085 */ MCD_OPC_CheckPredicate, + 24, + 86, + 8, + 0, // Skip to: 3224 + /* 1090 */ MCD_OPC_Decode, + 233, + 11, + 0, // Opcode: ERET_MMR6 + /* 1094 */ MCD_OPC_FilterValue, + 1, + 77, + 8, + 0, // Skip to: 3224 + /* 1099 */ MCD_OPC_CheckPredicate, + 24, + 72, + 8, + 0, // Skip to: 3224 + /* 1104 */ MCD_OPC_Decode, + 231, + 11, + 0, // Opcode: ERETNC_MMR6 + /* 1108 */ MCD_OPC_FilterValue, + 63, + 63, + 8, + 0, // Skip to: 3224 + /* 1113 */ MCD_OPC_CheckPredicate, + 24, + 58, + 8, + 0, // Skip to: 3224 + /* 1118 */ MCD_OPC_CheckField, + 22, + 4, + 0, + 51, + 8, + 0, // Skip to: 3224 + /* 1125 */ MCD_OPC_Decode, + 231, + 19, + 146, + 1, // Opcode: SIGRIE_MMR6 + /* 1130 */ MCD_OPC_FilterValue, + 4, + 26, + 0, + 0, // Skip to: 1161 + /* 1135 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 1152 + /* 1140 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 1152 + /* 1147 */ MCD_OPC_Decode, + 220, + 14, + 147, + 1, // Opcode: LUI_MMR6 + /* 1152 */ MCD_OPC_CheckPredicate, + 24, + 19, + 8, + 0, // Skip to: 3224 + /* 1157 */ MCD_OPC_Decode, + 172, + 6, + 97, // Opcode: AUI_MMR6 + /* 1161 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1176 + /* 1166 */ MCD_OPC_CheckPredicate, + 24, + 5, + 8, + 0, // Skip to: 3224 + /* 1171 */ MCD_OPC_Decode, + 159, + 14, + 148, + 1, // Opcode: LBU_MMR6 + /* 1176 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1190 + /* 1181 */ MCD_OPC_CheckPredicate, + 24, + 246, + 7, + 0, // Skip to: 3224 + /* 1186 */ MCD_OPC_Decode, + 241, + 18, + 87, // Opcode: SB_MMR6 + /* 1190 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1205 + /* 1195 */ MCD_OPC_CheckPredicate, + 24, + 232, + 7, + 0, // Skip to: 3224 + /* 1200 */ MCD_OPC_Decode, + 161, + 14, + 148, + 1, // Opcode: LB_MMR6 + /* 1205 */ MCD_OPC_FilterValue, + 8, + 105, + 0, + 0, // Skip to: 1315 + /* 1210 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 1213 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1235 + /* 1218 */ MCD_OPC_CheckPredicate, + 24, + 209, + 7, + 0, // Skip to: 3224 + /* 1223 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 202, + 7, + 0, // Skip to: 3224 + /* 1230 */ MCD_OPC_Decode, + 233, + 14, + 149, + 1, // Opcode: LWC2_MMR6 + /* 1235 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 1257 + /* 1240 */ MCD_OPC_CheckPredicate, + 24, + 187, + 7, + 0, // Skip to: 3224 + /* 1245 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 180, + 7, + 0, // Skip to: 3224 + /* 1252 */ MCD_OPC_Decode, + 173, + 14, + 149, + 1, // Opcode: LDC2_MMR6 + /* 1257 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 1271 + /* 1262 */ MCD_OPC_CheckPredicate, + 24, + 165, + 7, + 0, // Skip to: 3224 + /* 1267 */ MCD_OPC_Decode, + 153, + 8, + 89, // Opcode: CACHE_MMR6 + /* 1271 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 1293 + /* 1276 */ MCD_OPC_CheckPredicate, + 24, + 151, + 7, + 0, // Skip to: 3224 + /* 1281 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 144, + 7, + 0, // Skip to: 3224 + /* 1288 */ MCD_OPC_Decode, + 140, + 21, + 149, + 1, // Opcode: SWC2_MMR6 + /* 1293 */ MCD_OPC_FilterValue, + 10, + 134, + 7, + 0, // Skip to: 3224 + /* 1298 */ MCD_OPC_CheckPredicate, + 24, + 129, + 7, + 0, // Skip to: 3224 + /* 1303 */ MCD_OPC_CheckField, + 11, + 1, + 0, + 122, + 7, + 0, // Skip to: 3224 + /* 1310 */ MCD_OPC_Decode, + 136, + 19, + 149, + 1, // Opcode: SDC2_MMR6 + /* 1315 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 1329 + /* 1320 */ MCD_OPC_CheckPredicate, + 24, + 107, + 7, + 0, // Skip to: 3224 + /* 1325 */ MCD_OPC_Decode, + 202, + 5, + 86, // Opcode: ADDIU_MMR6 + /* 1329 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 1343 + /* 1334 */ MCD_OPC_CheckPredicate, + 24, + 93, + 7, + 0, // Skip to: 3224 + /* 1339 */ MCD_OPC_Decode, + 229, + 19, + 87, // Opcode: SH_MMR6 + /* 1343 */ MCD_OPC_FilterValue, + 16, + 78, + 0, + 0, // Skip to: 1426 + /* 1348 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 1351 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1366 + /* 1356 */ MCD_OPC_CheckPredicate, + 26, + 71, + 7, + 0, // Skip to: 3224 + /* 1361 */ MCD_OPC_Decode, + 214, + 6, + 150, + 1, // Opcode: BC1EQZC_MMR6 + /* 1366 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1381 + /* 1371 */ MCD_OPC_CheckPredicate, + 26, + 56, + 7, + 0, // Skip to: 3224 + /* 1376 */ MCD_OPC_Decode, + 219, + 6, + 150, + 1, // Opcode: BC1NEZC_MMR6 + /* 1381 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1396 + /* 1386 */ MCD_OPC_CheckPredicate, + 24, + 41, + 7, + 0, // Skip to: 3224 + /* 1391 */ MCD_OPC_Decode, + 224, + 6, + 151, + 1, // Opcode: BC2EQZC_MMR6 + /* 1396 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1411 + /* 1401 */ MCD_OPC_CheckPredicate, + 24, + 26, + 7, + 0, // Skip to: 3224 + /* 1406 */ MCD_OPC_Decode, + 228, + 6, + 151, + 1, // Opcode: BC2NEZC_MMR6 + /* 1411 */ MCD_OPC_FilterValue, + 12, + 16, + 7, + 0, // Skip to: 3224 + /* 1416 */ MCD_OPC_CheckPredicate, + 24, + 11, + 7, + 0, // Skip to: 3224 + /* 1421 */ MCD_OPC_Decode, + 170, + 21, + 152, + 1, // Opcode: SYNCI_MMR6 + /* 1426 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 1440 + /* 1431 */ MCD_OPC_CheckPredicate, + 24, + 252, + 6, + 0, // Skip to: 3224 + /* 1436 */ MCD_OPC_Decode, + 225, + 17, + 97, // Opcode: ORI_MMR6 + /* 1440 */ MCD_OPC_FilterValue, + 21, + 87, + 5, + 0, // Skip to: 2812 + /* 1445 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 1448 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1463 + /* 1453 */ MCD_OPC_CheckPredicate, + 26, + 230, + 6, + 0, // Skip to: 3224 + /* 1458 */ MCD_OPC_Decode, + 137, + 16, + 153, + 1, // Opcode: MIN_S_MMR6 + /* 1463 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1478 + /* 1468 */ MCD_OPC_CheckPredicate, + 26, + 215, + 6, + 0, // Skip to: 3224 + /* 1473 */ MCD_OPC_Decode, + 245, + 8, + 154, + 1, // Opcode: CMP_AF_S_MMR6 + /* 1478 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1493 + /* 1483 */ MCD_OPC_CheckPredicate, + 26, + 200, + 6, + 0, // Skip to: 3224 + /* 1488 */ MCD_OPC_Decode, + 206, + 15, + 153, + 1, // Opcode: MAX_S_MMR6 + /* 1493 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 1508 + /* 1498 */ MCD_OPC_CheckPredicate, + 26, + 185, + 6, + 0, // Skip to: 3224 + /* 1503 */ MCD_OPC_Decode, + 244, + 8, + 155, + 1, // Opcode: CMP_AF_D_MMR6 + /* 1508 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 1530 + /* 1513 */ MCD_OPC_CheckPredicate, + 24, + 170, + 6, + 0, // Skip to: 3224 + /* 1518 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 163, + 6, + 0, // Skip to: 3224 + /* 1525 */ MCD_OPC_Decode, + 200, + 18, + 156, + 1, // Opcode: RINT_S_MMR6 + /* 1530 */ MCD_OPC_FilterValue, + 35, + 10, + 0, + 0, // Skip to: 1545 + /* 1535 */ MCD_OPC_CheckPredicate, + 26, + 148, + 6, + 0, // Skip to: 3224 + /* 1540 */ MCD_OPC_Decode, + 246, + 15, + 153, + 1, // Opcode: MINA_S_MMR6 + /* 1545 */ MCD_OPC_FilterValue, + 43, + 10, + 0, + 0, // Skip to: 1560 + /* 1550 */ MCD_OPC_CheckPredicate, + 26, + 133, + 6, + 0, // Skip to: 3224 + /* 1555 */ MCD_OPC_Decode, + 187, + 15, + 153, + 1, // Opcode: MAXA_S_MMR6 + /* 1560 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 1575 + /* 1565 */ MCD_OPC_CheckPredicate, + 26, + 118, + 6, + 0, // Skip to: 3224 + /* 1570 */ MCD_OPC_Decode, + 152, + 12, + 157, + 1, // Opcode: FADD_S_MMR6 + /* 1575 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 1590 + /* 1580 */ MCD_OPC_CheckPredicate, + 24, + 103, + 6, + 0, // Skip to: 3224 + /* 1585 */ MCD_OPC_Decode, + 157, + 19, + 153, + 1, // Opcode: SELEQZ_S_MMR6 + /* 1590 */ MCD_OPC_FilterValue, + 59, + 31, + 0, + 0, // Skip to: 1626 + /* 1595 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 1598 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 1612 + /* 1603 */ MCD_OPC_CheckPredicate, + 26, + 80, + 6, + 0, // Skip to: 3224 + /* 1608 */ MCD_OPC_Decode, + 217, + 15, + 108, // Opcode: MFC1_MMR6 + /* 1612 */ MCD_OPC_FilterValue, + 5, + 71, + 6, + 0, // Skip to: 3224 + /* 1617 */ MCD_OPC_CheckPredicate, + 26, + 66, + 6, + 0, // Skip to: 3224 + /* 1622 */ MCD_OPC_Decode, + 233, + 16, + 114, // Opcode: MTC1_MMR6 + /* 1626 */ MCD_OPC_FilterValue, + 69, + 10, + 0, + 0, // Skip to: 1641 + /* 1631 */ MCD_OPC_CheckPredicate, + 26, + 52, + 6, + 0, // Skip to: 3224 + /* 1636 */ MCD_OPC_Decode, + 185, + 9, + 154, + 1, // Opcode: CMP_UN_S_MMR6 + /* 1641 */ MCD_OPC_FilterValue, + 85, + 10, + 0, + 0, // Skip to: 1656 + /* 1646 */ MCD_OPC_CheckPredicate, + 26, + 37, + 6, + 0, // Skip to: 3224 + /* 1651 */ MCD_OPC_Decode, + 183, + 9, + 155, + 1, // Opcode: CMP_UN_D_MMR6 + /* 1656 */ MCD_OPC_FilterValue, + 96, + 17, + 0, + 0, // Skip to: 1678 + /* 1661 */ MCD_OPC_CheckPredicate, + 24, + 22, + 6, + 0, // Skip to: 3224 + /* 1666 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 15, + 6, + 0, // Skip to: 3224 + /* 1673 */ MCD_OPC_Decode, + 185, + 8, + 156, + 1, // Opcode: CLASS_S_MMR6 + /* 1678 */ MCD_OPC_FilterValue, + 112, + 10, + 0, + 0, // Skip to: 1693 + /* 1683 */ MCD_OPC_CheckPredicate, + 26, + 0, + 6, + 0, // Skip to: 3224 + /* 1688 */ MCD_OPC_Decode, + 169, + 13, + 157, + 1, // Opcode: FSUB_S_MMR6 + /* 1693 */ MCD_OPC_FilterValue, + 120, + 10, + 0, + 0, // Skip to: 1708 + /* 1698 */ MCD_OPC_CheckPredicate, + 24, + 241, + 5, + 0, // Skip to: 3224 + /* 1703 */ MCD_OPC_Decode, + 164, + 19, + 153, + 1, // Opcode: SELNEZ_S_MMR6 + /* 1708 */ MCD_OPC_FilterValue, + 123, + 31, + 0, + 0, // Skip to: 1744 + /* 1713 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 1716 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1730 + /* 1721 */ MCD_OPC_CheckPredicate, + 26, + 218, + 5, + 0, // Skip to: 3224 + /* 1726 */ MCD_OPC_Decode, + 242, + 12, + 113, // Opcode: FMOV_S_MMR6 + /* 1730 */ MCD_OPC_FilterValue, + 4, + 209, + 5, + 0, // Skip to: 3224 + /* 1735 */ MCD_OPC_CheckPredicate, + 26, + 204, + 5, + 0, // Skip to: 3224 + /* 1740 */ MCD_OPC_Decode, + 239, + 12, + 111, // Opcode: FMOV_D_MMR6 + /* 1744 */ MCD_OPC_FilterValue, + 133, + 1, + 10, + 0, + 0, // Skip to: 1760 + /* 1750 */ MCD_OPC_CheckPredicate, + 26, + 189, + 5, + 0, // Skip to: 3224 + /* 1755 */ MCD_OPC_Decode, + 251, + 8, + 154, + 1, // Opcode: CMP_EQ_S_MMR6 + /* 1760 */ MCD_OPC_FilterValue, + 149, + 1, + 10, + 0, + 0, // Skip to: 1776 + /* 1766 */ MCD_OPC_CheckPredicate, + 26, + 173, + 5, + 0, // Skip to: 3224 + /* 1771 */ MCD_OPC_Decode, + 247, + 8, + 155, + 1, // Opcode: CMP_EQ_D_MMR6 + /* 1776 */ MCD_OPC_FilterValue, + 176, + 1, + 10, + 0, + 0, // Skip to: 1792 + /* 1782 */ MCD_OPC_CheckPredicate, + 26, + 157, + 5, + 0, // Skip to: 3224 + /* 1787 */ MCD_OPC_Decode, + 253, + 12, + 157, + 1, // Opcode: FMUL_S_MMR6 + /* 1792 */ MCD_OPC_FilterValue, + 184, + 1, + 10, + 0, + 0, // Skip to: 1808 + /* 1798 */ MCD_OPC_CheckPredicate, + 24, + 141, + 5, + 0, // Skip to: 3224 + /* 1803 */ MCD_OPC_Decode, + 168, + 19, + 158, + 1, // Opcode: SEL_S_MMR6 + /* 1808 */ MCD_OPC_FilterValue, + 197, + 1, + 10, + 0, + 0, // Skip to: 1824 + /* 1814 */ MCD_OPC_CheckPredicate, + 26, + 125, + 5, + 0, // Skip to: 3224 + /* 1819 */ MCD_OPC_Decode, + 173, + 9, + 154, + 1, // Opcode: CMP_UEQ_S_MMR6 + /* 1824 */ MCD_OPC_FilterValue, + 213, + 1, + 10, + 0, + 0, // Skip to: 1840 + /* 1830 */ MCD_OPC_CheckPredicate, + 26, + 109, + 5, + 0, // Skip to: 3224 + /* 1835 */ MCD_OPC_Decode, + 171, + 9, + 155, + 1, // Opcode: CMP_UEQ_D_MMR6 + /* 1840 */ MCD_OPC_FilterValue, + 240, + 1, + 10, + 0, + 0, // Skip to: 1856 + /* 1846 */ MCD_OPC_CheckPredicate, + 26, + 93, + 5, + 0, // Skip to: 3224 + /* 1851 */ MCD_OPC_Decode, + 190, + 12, + 157, + 1, // Opcode: FDIV_S_MMR6 + /* 1856 */ MCD_OPC_FilterValue, + 133, + 2, + 10, + 0, + 0, // Skip to: 1872 + /* 1862 */ MCD_OPC_CheckPredicate, + 26, + 77, + 5, + 0, // Skip to: 3224 + /* 1867 */ MCD_OPC_Decode, + 137, + 9, + 154, + 1, // Opcode: CMP_LT_S_MMR6 + /* 1872 */ MCD_OPC_FilterValue, + 149, + 2, + 10, + 0, + 0, // Skip to: 1888 + /* 1878 */ MCD_OPC_CheckPredicate, + 26, + 61, + 5, + 0, // Skip to: 3224 + /* 1883 */ MCD_OPC_Decode, + 133, + 9, + 155, + 1, // Opcode: CMP_LT_D_MMR6 + /* 1888 */ MCD_OPC_FilterValue, + 187, + 2, + 45, + 0, + 0, // Skip to: 1939 + /* 1894 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 1897 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1911 + /* 1902 */ MCD_OPC_CheckPredicate, + 26, + 37, + 5, + 0, // Skip to: 3224 + /* 1907 */ MCD_OPC_Decode, + 220, + 9, + 110, // Opcode: CVT_L_S_MMR6 + /* 1911 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1925 + /* 1916 */ MCD_OPC_CheckPredicate, + 26, + 23, + 5, + 0, // Skip to: 3224 + /* 1921 */ MCD_OPC_Decode, + 241, + 9, + 113, // Opcode: CVT_W_S_MMR6 + /* 1925 */ MCD_OPC_FilterValue, + 8, + 14, + 5, + 0, // Skip to: 3224 + /* 1930 */ MCD_OPC_CheckPredicate, + 26, + 9, + 5, + 0, // Skip to: 3224 + /* 1935 */ MCD_OPC_Decode, + 217, + 9, + 111, // Opcode: CVT_L_D_MMR6 + /* 1939 */ MCD_OPC_FilterValue, + 197, + 2, + 10, + 0, + 0, // Skip to: 1955 + /* 1945 */ MCD_OPC_CheckPredicate, + 26, + 250, + 4, + 0, // Skip to: 3224 + /* 1950 */ MCD_OPC_Decode, + 181, + 9, + 154, + 1, // Opcode: CMP_ULT_S_MMR6 + /* 1955 */ MCD_OPC_FilterValue, + 213, + 2, + 10, + 0, + 0, // Skip to: 1971 + /* 1961 */ MCD_OPC_CheckPredicate, + 26, + 234, + 4, + 0, // Skip to: 3224 + /* 1966 */ MCD_OPC_Decode, + 179, + 9, + 155, + 1, // Opcode: CMP_ULT_D_MMR6 + /* 1971 */ MCD_OPC_FilterValue, + 133, + 3, + 10, + 0, + 0, // Skip to: 1987 + /* 1977 */ MCD_OPC_CheckPredicate, + 26, + 218, + 4, + 0, // Skip to: 3224 + /* 1982 */ MCD_OPC_Decode, + 131, + 9, + 154, + 1, // Opcode: CMP_LE_S_MMR6 + /* 1987 */ MCD_OPC_FilterValue, + 149, + 3, + 10, + 0, + 0, // Skip to: 2003 + /* 1993 */ MCD_OPC_CheckPredicate, + 26, + 202, + 4, + 0, // Skip to: 3224 + /* 1998 */ MCD_OPC_Decode, + 255, + 8, + 155, + 1, // Opcode: CMP_LE_D_MMR6 + /* 2003 */ MCD_OPC_FilterValue, + 184, + 3, + 10, + 0, + 0, // Skip to: 2019 + /* 2009 */ MCD_OPC_CheckPredicate, + 26, + 186, + 4, + 0, // Skip to: 3224 + /* 2014 */ MCD_OPC_Decode, + 155, + 15, + 159, + 1, // Opcode: MADDF_S_MMR6 + /* 2019 */ MCD_OPC_FilterValue, + 197, + 3, + 10, + 0, + 0, // Skip to: 2035 + /* 2025 */ MCD_OPC_CheckPredicate, + 26, + 170, + 4, + 0, // Skip to: 3224 + /* 2030 */ MCD_OPC_Decode, + 177, + 9, + 154, + 1, // Opcode: CMP_ULE_S_MMR6 + /* 2035 */ MCD_OPC_FilterValue, + 213, + 3, + 10, + 0, + 0, // Skip to: 2051 + /* 2041 */ MCD_OPC_CheckPredicate, + 26, + 154, + 4, + 0, // Skip to: 3224 + /* 2046 */ MCD_OPC_Decode, + 175, + 9, + 155, + 1, // Opcode: CMP_ULE_D_MMR6 + /* 2051 */ MCD_OPC_FilterValue, + 248, + 3, + 10, + 0, + 0, // Skip to: 2067 + /* 2057 */ MCD_OPC_CheckPredicate, + 26, + 138, + 4, + 0, // Skip to: 3224 + /* 2062 */ MCD_OPC_Decode, + 206, + 16, + 159, + 1, // Opcode: MSUBF_S_MMR6 + /* 2067 */ MCD_OPC_FilterValue, + 131, + 4, + 10, + 0, + 0, // Skip to: 2083 + /* 2073 */ MCD_OPC_CheckPredicate, + 26, + 122, + 4, + 0, // Skip to: 3224 + /* 2078 */ MCD_OPC_Decode, + 132, + 16, + 134, + 1, // Opcode: MIN_D_MMR6 + /* 2083 */ MCD_OPC_FilterValue, + 133, + 4, + 10, + 0, + 0, // Skip to: 2099 + /* 2089 */ MCD_OPC_CheckPredicate, + 26, + 106, + 4, + 0, // Skip to: 3224 + /* 2094 */ MCD_OPC_Decode, + 141, + 9, + 154, + 1, // Opcode: CMP_SAF_S_MMR6 + /* 2099 */ MCD_OPC_FilterValue, + 139, + 4, + 10, + 0, + 0, // Skip to: 2115 + /* 2105 */ MCD_OPC_CheckPredicate, + 26, + 90, + 4, + 0, // Skip to: 3224 + /* 2110 */ MCD_OPC_Decode, + 201, + 15, + 134, + 1, // Opcode: MAX_D_MMR6 + /* 2115 */ MCD_OPC_FilterValue, + 149, + 4, + 10, + 0, + 0, // Skip to: 2131 + /* 2121 */ MCD_OPC_CheckPredicate, + 26, + 74, + 4, + 0, // Skip to: 3224 + /* 2126 */ MCD_OPC_Decode, + 139, + 9, + 155, + 1, // Opcode: CMP_SAF_D_MMR6 + /* 2131 */ MCD_OPC_FilterValue, + 160, + 4, + 17, + 0, + 0, // Skip to: 2154 + /* 2137 */ MCD_OPC_CheckPredicate, + 24, + 58, + 4, + 0, // Skip to: 3224 + /* 2142 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 51, + 4, + 0, // Skip to: 3224 + /* 2149 */ MCD_OPC_Decode, + 198, + 18, + 160, + 1, // Opcode: RINT_D_MMR6 + /* 2154 */ MCD_OPC_FilterValue, + 163, + 4, + 10, + 0, + 0, // Skip to: 2170 + /* 2160 */ MCD_OPC_CheckPredicate, + 26, + 35, + 4, + 0, // Skip to: 3224 + /* 2165 */ MCD_OPC_Decode, + 244, + 15, + 134, + 1, // Opcode: MINA_D_MMR6 + /* 2170 */ MCD_OPC_FilterValue, + 171, + 4, + 10, + 0, + 0, // Skip to: 2186 + /* 2176 */ MCD_OPC_CheckPredicate, + 26, + 19, + 4, + 0, // Skip to: 3224 + /* 2181 */ MCD_OPC_Decode, + 185, + 15, + 134, + 1, // Opcode: MAXA_D_MMR6 + /* 2186 */ MCD_OPC_FilterValue, + 184, + 4, + 10, + 0, + 0, // Skip to: 2202 + /* 2192 */ MCD_OPC_CheckPredicate, + 24, + 3, + 4, + 0, // Skip to: 3224 + /* 2197 */ MCD_OPC_Decode, + 154, + 19, + 134, + 1, // Opcode: SELEQZ_D_MMR6 + /* 2202 */ MCD_OPC_FilterValue, + 197, + 4, + 10, + 0, + 0, // Skip to: 2218 + /* 2208 */ MCD_OPC_CheckPredicate, + 26, + 243, + 3, + 0, // Skip to: 3224 + /* 2213 */ MCD_OPC_Decode, + 169, + 9, + 154, + 1, // Opcode: CMP_SUN_S_MMR6 + /* 2218 */ MCD_OPC_FilterValue, + 213, + 4, + 10, + 0, + 0, // Skip to: 2234 + /* 2224 */ MCD_OPC_CheckPredicate, + 26, + 227, + 3, + 0, // Skip to: 3224 + /* 2229 */ MCD_OPC_Decode, + 167, + 9, + 155, + 1, // Opcode: CMP_SUN_D_MMR6 + /* 2234 */ MCD_OPC_FilterValue, + 224, + 4, + 17, + 0, + 0, // Skip to: 2257 + /* 2240 */ MCD_OPC_CheckPredicate, + 24, + 211, + 3, + 0, // Skip to: 3224 + /* 2245 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 204, + 3, + 0, // Skip to: 3224 + /* 2252 */ MCD_OPC_Decode, + 183, + 8, + 160, + 1, // Opcode: CLASS_D_MMR6 + /* 2257 */ MCD_OPC_FilterValue, + 248, + 4, + 10, + 0, + 0, // Skip to: 2273 + /* 2263 */ MCD_OPC_CheckPredicate, + 24, + 188, + 3, + 0, // Skip to: 3224 + /* 2268 */ MCD_OPC_Decode, + 161, + 19, + 134, + 1, // Opcode: SELNEZ_D_MMR6 + /* 2273 */ MCD_OPC_FilterValue, + 133, + 5, + 10, + 0, + 0, // Skip to: 2289 + /* 2279 */ MCD_OPC_CheckPredicate, + 26, + 172, + 3, + 0, // Skip to: 3224 + /* 2284 */ MCD_OPC_Decode, + 145, + 9, + 154, + 1, // Opcode: CMP_SEQ_S_MMR6 + /* 2289 */ MCD_OPC_FilterValue, + 149, + 5, + 10, + 0, + 0, // Skip to: 2305 + /* 2295 */ MCD_OPC_CheckPredicate, + 26, + 156, + 3, + 0, // Skip to: 3224 + /* 2300 */ MCD_OPC_Decode, + 143, + 9, + 155, + 1, // Opcode: CMP_SEQ_D_MMR6 + /* 2305 */ MCD_OPC_FilterValue, + 184, + 5, + 10, + 0, + 0, // Skip to: 2321 + /* 2311 */ MCD_OPC_CheckPredicate, + 24, + 140, + 3, + 0, // Skip to: 3224 + /* 2316 */ MCD_OPC_Decode, + 166, + 19, + 161, + 1, // Opcode: SEL_D_MMR6 + /* 2321 */ MCD_OPC_FilterValue, + 197, + 5, + 10, + 0, + 0, // Skip to: 2337 + /* 2327 */ MCD_OPC_CheckPredicate, + 26, + 124, + 3, + 0, // Skip to: 3224 + /* 2332 */ MCD_OPC_Decode, + 157, + 9, + 154, + 1, // Opcode: CMP_SUEQ_S_MMR6 + /* 2337 */ MCD_OPC_FilterValue, + 213, + 5, + 10, + 0, + 0, // Skip to: 2353 + /* 2343 */ MCD_OPC_CheckPredicate, + 26, + 108, + 3, + 0, // Skip to: 3224 + /* 2348 */ MCD_OPC_Decode, + 155, + 9, + 155, + 1, // Opcode: CMP_SUEQ_D_MMR6 + /* 2353 */ MCD_OPC_FilterValue, + 133, + 6, + 10, + 0, + 0, // Skip to: 2369 + /* 2359 */ MCD_OPC_CheckPredicate, + 26, + 92, + 3, + 0, // Skip to: 3224 + /* 2364 */ MCD_OPC_Decode, + 153, + 9, + 154, + 1, // Opcode: CMP_SLT_S_MMR6 + /* 2369 */ MCD_OPC_FilterValue, + 149, + 6, + 10, + 0, + 0, // Skip to: 2385 + /* 2375 */ MCD_OPC_CheckPredicate, + 26, + 76, + 3, + 0, // Skip to: 3224 + /* 2380 */ MCD_OPC_Decode, + 151, + 9, + 155, + 1, // Opcode: CMP_SLT_D_MMR6 + /* 2385 */ MCD_OPC_FilterValue, + 187, + 6, + 228, + 0, + 0, // Skip to: 2619 + /* 2391 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2394 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2408 + /* 2399 */ MCD_OPC_CheckPredicate, + 26, + 52, + 3, + 0, // Skip to: 3224 + /* 2404 */ MCD_OPC_Decode, + 217, + 12, + 110, // Opcode: FLOOR_L_S_MMR6 + /* 2408 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2422 + /* 2413 */ MCD_OPC_CheckPredicate, + 26, + 38, + 3, + 0, // Skip to: 3224 + /* 2418 */ MCD_OPC_Decode, + 224, + 12, + 113, // Opcode: FLOOR_W_S_MMR6 + /* 2422 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2436 + /* 2427 */ MCD_OPC_CheckPredicate, + 26, + 24, + 3, + 0, // Skip to: 3224 + /* 2432 */ MCD_OPC_Decode, + 158, + 8, + 110, // Opcode: CEIL_L_S_MMR6 + /* 2436 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 2450 + /* 2441 */ MCD_OPC_CheckPredicate, + 26, + 10, + 3, + 0, // Skip to: 3224 + /* 2446 */ MCD_OPC_Decode, + 165, + 8, + 113, // Opcode: CEIL_W_S_MMR6 + /* 2450 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 2464 + /* 2455 */ MCD_OPC_CheckPredicate, + 26, + 252, + 2, + 0, // Skip to: 3224 + /* 2460 */ MCD_OPC_Decode, + 246, + 21, + 110, // Opcode: TRUNC_L_S_MMR6 + /* 2464 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2478 + /* 2469 */ MCD_OPC_CheckPredicate, + 26, + 238, + 2, + 0, // Skip to: 3224 + /* 2474 */ MCD_OPC_Decode, + 253, + 21, + 113, // Opcode: TRUNC_W_S_MMR6 + /* 2478 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 2492 + /* 2483 */ MCD_OPC_CheckPredicate, + 26, + 224, + 2, + 0, // Skip to: 3224 + /* 2488 */ MCD_OPC_Decode, + 208, + 18, + 110, // Opcode: ROUND_L_S_MMR6 + /* 2492 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 2506 + /* 2497 */ MCD_OPC_CheckPredicate, + 26, + 210, + 2, + 0, // Skip to: 3224 + /* 2502 */ MCD_OPC_Decode, + 215, + 18, + 113, // Opcode: ROUND_W_S_MMR6 + /* 2506 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 2520 + /* 2511 */ MCD_OPC_CheckPredicate, + 26, + 196, + 2, + 0, // Skip to: 3224 + /* 2516 */ MCD_OPC_Decode, + 215, + 12, + 111, // Opcode: FLOOR_L_D_MMR6 + /* 2520 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 2534 + /* 2525 */ MCD_OPC_CheckPredicate, + 26, + 182, + 2, + 0, // Skip to: 3224 + /* 2530 */ MCD_OPC_Decode, + 220, + 12, + 115, // Opcode: FLOOR_W_D_MMR6 + /* 2534 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 2548 + /* 2539 */ MCD_OPC_CheckPredicate, + 26, + 168, + 2, + 0, // Skip to: 3224 + /* 2544 */ MCD_OPC_Decode, + 156, + 8, + 111, // Opcode: CEIL_L_D_MMR6 + /* 2548 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 2562 + /* 2553 */ MCD_OPC_CheckPredicate, + 26, + 154, + 2, + 0, // Skip to: 3224 + /* 2558 */ MCD_OPC_Decode, + 161, + 8, + 115, // Opcode: CEIL_W_D_MMR6 + /* 2562 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 2576 + /* 2567 */ MCD_OPC_CheckPredicate, + 26, + 140, + 2, + 0, // Skip to: 3224 + /* 2572 */ MCD_OPC_Decode, + 244, + 21, + 111, // Opcode: TRUNC_L_D_MMR6 + /* 2576 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 2591 + /* 2581 */ MCD_OPC_CheckPredicate, + 26, + 126, + 2, + 0, // Skip to: 3224 + /* 2586 */ MCD_OPC_Decode, + 249, + 21, + 135, + 1, // Opcode: TRUNC_W_D_MMR6 + /* 2591 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 2605 + /* 2596 */ MCD_OPC_CheckPredicate, + 26, + 111, + 2, + 0, // Skip to: 3224 + /* 2601 */ MCD_OPC_Decode, + 206, + 18, + 111, // Opcode: ROUND_L_D_MMR6 + /* 2605 */ MCD_OPC_FilterValue, + 15, + 102, + 2, + 0, // Skip to: 3224 + /* 2610 */ MCD_OPC_CheckPredicate, + 26, + 97, + 2, + 0, // Skip to: 3224 + /* 2615 */ MCD_OPC_Decode, + 211, + 18, + 111, // Opcode: ROUND_W_D_MMR6 + /* 2619 */ MCD_OPC_FilterValue, + 197, + 6, + 10, + 0, + 0, // Skip to: 2635 + /* 2625 */ MCD_OPC_CheckPredicate, + 26, + 82, + 2, + 0, // Skip to: 3224 + /* 2630 */ MCD_OPC_Decode, + 165, + 9, + 154, + 1, // Opcode: CMP_SULT_S_MMR6 + /* 2635 */ MCD_OPC_FilterValue, + 213, + 6, + 10, + 0, + 0, // Skip to: 2651 + /* 2641 */ MCD_OPC_CheckPredicate, + 26, + 66, + 2, + 0, // Skip to: 3224 + /* 2646 */ MCD_OPC_Decode, + 163, + 9, + 155, + 1, // Opcode: CMP_SULT_D_MMR6 + /* 2651 */ MCD_OPC_FilterValue, + 251, + 6, + 59, + 0, + 0, // Skip to: 2716 + /* 2657 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 2660 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2674 + /* 2665 */ MCD_OPC_CheckPredicate, + 26, + 42, + 2, + 0, // Skip to: 3224 + /* 2670 */ MCD_OPC_Decode, + 133, + 13, + 113, // Opcode: FNEG_S_MMR6 + /* 2674 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 2688 + /* 2679 */ MCD_OPC_CheckPredicate, + 26, + 28, + 2, + 0, // Skip to: 3224 + /* 2684 */ MCD_OPC_Decode, + 234, + 9, + 113, // Opcode: CVT_S_W_MMR6 + /* 2688 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 2702 + /* 2693 */ MCD_OPC_CheckPredicate, + 23, + 14, + 2, + 0, // Skip to: 3224 + /* 2698 */ MCD_OPC_Decode, + 214, + 9, + 111, // Opcode: CVT_D_L_MMR6 + /* 2702 */ MCD_OPC_FilterValue, + 11, + 5, + 2, + 0, // Skip to: 3224 + /* 2707 */ MCD_OPC_CheckPredicate, + 23, + 0, + 2, + 0, // Skip to: 3224 + /* 2712 */ MCD_OPC_Decode, + 229, + 9, + 110, // Opcode: CVT_S_L_MMR6 + /* 2716 */ MCD_OPC_FilterValue, + 133, + 7, + 10, + 0, + 0, // Skip to: 2732 + /* 2722 */ MCD_OPC_CheckPredicate, + 26, + 241, + 1, + 0, // Skip to: 3224 + /* 2727 */ MCD_OPC_Decode, + 149, + 9, + 154, + 1, // Opcode: CMP_SLE_S_MMR6 + /* 2732 */ MCD_OPC_FilterValue, + 149, + 7, + 10, + 0, + 0, // Skip to: 2748 + /* 2738 */ MCD_OPC_CheckPredicate, + 26, + 225, + 1, + 0, // Skip to: 3224 + /* 2743 */ MCD_OPC_Decode, + 147, + 9, + 155, + 1, // Opcode: CMP_SLE_D_MMR6 + /* 2748 */ MCD_OPC_FilterValue, + 184, + 7, + 10, + 0, + 0, // Skip to: 2764 + /* 2754 */ MCD_OPC_CheckPredicate, + 26, + 209, + 1, + 0, // Skip to: 3224 + /* 2759 */ MCD_OPC_Decode, + 153, + 15, + 161, + 1, // Opcode: MADDF_D_MMR6 + /* 2764 */ MCD_OPC_FilterValue, + 197, + 7, + 10, + 0, + 0, // Skip to: 2780 + /* 2770 */ MCD_OPC_CheckPredicate, + 26, + 193, + 1, + 0, // Skip to: 3224 + /* 2775 */ MCD_OPC_Decode, + 161, + 9, + 154, + 1, // Opcode: CMP_SULE_S_MMR6 + /* 2780 */ MCD_OPC_FilterValue, + 213, + 7, + 10, + 0, + 0, // Skip to: 2796 + /* 2786 */ MCD_OPC_CheckPredicate, + 26, + 177, + 1, + 0, // Skip to: 3224 + /* 2791 */ MCD_OPC_Decode, + 159, + 9, + 155, + 1, // Opcode: CMP_SULE_D_MMR6 + /* 2796 */ MCD_OPC_FilterValue, + 248, + 7, + 166, + 1, + 0, // Skip to: 3224 + /* 2802 */ MCD_OPC_CheckPredicate, + 26, + 161, + 1, + 0, // Skip to: 3224 + /* 2807 */ MCD_OPC_Decode, + 204, + 16, + 161, + 1, // Opcode: MSUBF_D_MMR6 + /* 2812 */ MCD_OPC_FilterValue, + 24, + 59, + 0, + 0, // Skip to: 2876 + /* 2817 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 2820 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2834 + /* 2825 */ MCD_OPC_CheckPredicate, + 24, + 138, + 1, + 0, // Skip to: 3224 + /* 2830 */ MCD_OPC_Decode, + 168, + 18, + 89, // Opcode: PREF_MMR6 + /* 2834 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 2855 + /* 2839 */ MCD_OPC_CheckPredicate, + 24, + 124, + 1, + 0, // Skip to: 3224 + /* 2844 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 117, + 1, + 0, // Skip to: 3224 + /* 2851 */ MCD_OPC_Decode, + 215, + 14, + 123, // Opcode: LL_MMR6 + /* 2855 */ MCD_OPC_FilterValue, + 11, + 108, + 1, + 0, // Skip to: 3224 + /* 2860 */ MCD_OPC_CheckPredicate, + 24, + 103, + 1, + 0, // Skip to: 3224 + /* 2865 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 96, + 1, + 0, // Skip to: 3224 + /* 2872 */ MCD_OPC_Decode, + 250, + 18, + 123, // Opcode: SC_MMR6 + /* 2876 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 2890 + /* 2881 */ MCD_OPC_CheckPredicate, + 24, + 82, + 1, + 0, // Skip to: 3224 + /* 2886 */ MCD_OPC_Decode, + 150, + 22, + 97, // Opcode: XORI_MMR6 + /* 2890 */ MCD_OPC_FilterValue, + 29, + 27, + 0, + 0, // Skip to: 2922 + /* 2895 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 2912 + /* 2900 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 2912 + /* 2907 */ MCD_OPC_Decode, + 252, + 6, + 162, + 1, // Opcode: BEQZALC_MMR6 + /* 2912 */ MCD_OPC_CheckPredicate, + 24, + 51, + 1, + 0, // Skip to: 3224 + /* 2917 */ MCD_OPC_Decode, + 248, + 6, + 162, + 1, // Opcode: BEQC_MMR6 + /* 2922 */ MCD_OPC_FilterValue, + 30, + 71, + 0, + 0, // Skip to: 2998 + /* 2927 */ MCD_OPC_ExtractField, + 19, + 2, // Inst{20-19} ... + /* 2930 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2945 + /* 2935 */ MCD_OPC_CheckPredicate, + 24, + 28, + 1, + 0, // Skip to: 3224 + /* 2940 */ MCD_OPC_Decode, + 197, + 5, + 163, + 1, // Opcode: ADDIUPC_MMR6 + /* 2945 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2960 + /* 2950 */ MCD_OPC_CheckPredicate, + 24, + 13, + 1, + 0, // Skip to: 3224 + /* 2955 */ MCD_OPC_Decode, + 250, + 14, + 163, + 1, // Opcode: LWPC_MMR6 + /* 2960 */ MCD_OPC_FilterValue, + 3, + 3, + 1, + 0, // Skip to: 3224 + /* 2965 */ MCD_OPC_ExtractField, + 16, + 3, // Inst{18-16} ... + /* 2968 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 2983 + /* 2973 */ MCD_OPC_CheckPredicate, + 24, + 246, + 0, + 0, // Skip to: 3224 + /* 2978 */ MCD_OPC_Decode, + 171, + 6, + 164, + 1, // Opcode: AUIPC_MMR6 + /* 2983 */ MCD_OPC_FilterValue, + 7, + 236, + 0, + 0, // Skip to: 3224 + /* 2988 */ MCD_OPC_CheckPredicate, + 24, + 231, + 0, + 0, // Skip to: 3224 + /* 2993 */ MCD_OPC_Decode, + 144, + 6, + 164, + 1, // Opcode: ALUIPC_MMR6 + /* 2998 */ MCD_OPC_FilterValue, + 31, + 27, + 0, + 0, // Skip to: 3030 + /* 3003 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 3020 + /* 3008 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 3020 + /* 3015 */ MCD_OPC_Decode, + 227, + 7, + 165, + 1, // Opcode: BNEZALC_MMR6 + /* 3020 */ MCD_OPC_CheckPredicate, + 24, + 199, + 0, + 0, // Skip to: 3224 + /* 3025 */ MCD_OPC_Decode, + 215, + 7, + 165, + 1, // Opcode: BNEC_MMR6 + /* 3030 */ MCD_OPC_FilterValue, + 32, + 26, + 0, + 0, // Skip to: 3061 + /* 3035 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 3051 + /* 3040 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 3051 + /* 3047 */ MCD_OPC_Decode, + 129, + 14, + 92, // Opcode: JIALC_MMR6 + /* 3051 */ MCD_OPC_CheckPredicate, + 24, + 168, + 0, + 0, // Skip to: 3224 + /* 3056 */ MCD_OPC_Decode, + 129, + 7, + 166, + 1, // Opcode: BEQZC_MMR6 + /* 3061 */ MCD_OPC_FilterValue, + 37, + 10, + 0, + 0, // Skip to: 3076 + /* 3066 */ MCD_OPC_CheckPredicate, + 24, + 153, + 0, + 0, // Skip to: 3224 + /* 3071 */ MCD_OPC_Decode, + 243, + 6, + 167, + 1, // Opcode: BC_MMR6 + /* 3076 */ MCD_OPC_FilterValue, + 40, + 26, + 0, + 0, // Skip to: 3107 + /* 3081 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 3097 + /* 3086 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 3097 + /* 3093 */ MCD_OPC_Decode, + 132, + 14, + 92, // Opcode: JIC_MMR6 + /* 3097 */ MCD_OPC_CheckPredicate, + 24, + 122, + 0, + 0, // Skip to: 3224 + /* 3102 */ MCD_OPC_Decode, + 232, + 7, + 166, + 1, // Opcode: BNEZC_MMR6 + /* 3107 */ MCD_OPC_FilterValue, + 45, + 10, + 0, + 0, // Skip to: 3122 + /* 3112 */ MCD_OPC_CheckPredicate, + 24, + 107, + 0, + 0, // Skip to: 3224 + /* 3117 */ MCD_OPC_Decode, + 202, + 6, + 167, + 1, // Opcode: BALC_MMR6 + /* 3122 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 3137 + /* 3127 */ MCD_OPC_CheckPredicate, + 24, + 92, + 0, + 0, // Skip to: 3224 + /* 3132 */ MCD_OPC_Decode, + 136, + 7, + 168, + 1, // Opcode: BGEUC_MMR6 + /* 3137 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 3151 + /* 3142 */ MCD_OPC_CheckPredicate, + 24, + 77, + 0, + 0, // Skip to: 3224 + /* 3147 */ MCD_OPC_Decode, + 152, + 6, + 97, // Opcode: ANDI_MMR6 + /* 3151 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 3166 + /* 3156 */ MCD_OPC_CheckPredicate, + 24, + 63, + 0, + 0, // Skip to: 3224 + /* 3161 */ MCD_OPC_Decode, + 190, + 7, + 169, + 1, // Opcode: BLTC_MMR6 + /* 3166 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 3181 + /* 3171 */ MCD_OPC_CheckPredicate, + 24, + 48, + 0, + 0, // Skip to: 3224 + /* 3176 */ MCD_OPC_Decode, + 193, + 7, + 170, + 1, // Opcode: BLTUC_MMR6 + /* 3181 */ MCD_OPC_FilterValue, + 61, + 10, + 0, + 0, // Skip to: 3196 + /* 3186 */ MCD_OPC_CheckPredicate, + 24, + 33, + 0, + 0, // Skip to: 3224 + /* 3191 */ MCD_OPC_Decode, + 133, + 7, + 171, + 1, // Opcode: BGEC_MMR6 + /* 3196 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 3210 + /* 3201 */ MCD_OPC_CheckPredicate, + 24, + 18, + 0, + 0, // Skip to: 3224 + /* 3206 */ MCD_OPC_Decode, + 166, + 21, + 87, // Opcode: SW_MMR6 + /* 3210 */ MCD_OPC_FilterValue, + 63, + 9, + 0, + 0, // Skip to: 3224 + /* 3215 */ MCD_OPC_CheckPredicate, + 24, + 4, + 0, + 0, // Skip to: 3224 + /* 3220 */ MCD_OPC_Decode, + 138, + 15, + 87, // Opcode: LW_MMR6 + /* 3224 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMicroMipsR6_Ambiguous32[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, + 24, + 84, + 0, + 0, // Skip to: 97 + /* 13 */ MCD_OPC_Decode, + 242, + 7, + 162, + 1, // Opcode: BOVC_MMR6 + /* 18 */ MCD_OPC_FilterValue, + 31, + 10, + 0, + 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, + 24, + 69, + 0, + 0, // Skip to: 97 + /* 28 */ MCD_OPC_Decode, + 235, + 7, + 165, + 1, // Opcode: BNVC_MMR6 + /* 33 */ MCD_OPC_FilterValue, + 48, + 27, + 0, + 0, // Skip to: 65 + /* 38 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 55 + /* 43 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 55 + /* 50 */ MCD_OPC_Decode, + 182, + 7, + 168, + 1, // Opcode: BLEZALC_MMR6 + /* 55 */ MCD_OPC_CheckPredicate, + 24, + 37, + 0, + 0, // Skip to: 97 + /* 60 */ MCD_OPC_Decode, + 141, + 7, + 168, + 1, // Opcode: BGEZALC_MMR6 + /* 65 */ MCD_OPC_FilterValue, + 56, + 27, + 0, + 0, // Skip to: 97 + /* 70 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 87 + /* 75 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 87 + /* 82 */ MCD_OPC_Decode, + 153, + 7, + 170, + 1, // Opcode: BGTZALC_MMR6 + /* 87 */ MCD_OPC_CheckPredicate, + 24, + 5, + 0, + 0, // Skip to: 97 + /* 92 */ MCD_OPC_Decode, + 198, + 7, + 170, + 1, // Opcode: BLTZALC_MMR6 + /* 97 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMips32[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 68 -/* 14 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 17 */ MCD_OPC_FilterValue, 0, 137, 53, // Skip to: 13726 -/* 21 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... -/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 -/* 28 */ MCD_OPC_CheckPredicate, 5, 28, 0, // Skip to: 60 -/* 32 */ MCD_OPC_Decode, 180, 12, 0, // Opcode: SSNOP -/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 -/* 40 */ MCD_OPC_CheckPredicate, 5, 16, 0, // Skip to: 60 -/* 44 */ MCD_OPC_Decode, 139, 5, 0, // Opcode: EHB -/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 -/* 52 */ MCD_OPC_CheckPredicate, 6, 4, 0, // Skip to: 60 -/* 56 */ MCD_OPC_Decode, 147, 10, 0, // Opcode: PAUSE -/* 60 */ MCD_OPC_CheckPredicate, 1, 94, 53, // Skip to: 13726 -/* 64 */ MCD_OPC_Decode, 225, 11, 58, // Opcode: SLL -/* 68 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 111 -/* 72 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 75 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 93 -/* 79 */ MCD_OPC_CheckPredicate, 7, 75, 53, // Skip to: 13726 -/* 83 */ MCD_OPC_CheckField, 6, 5, 0, 69, 53, // Skip to: 13726 -/* 89 */ MCD_OPC_Decode, 239, 8, 59, // Opcode: MOVF_I -/* 93 */ MCD_OPC_FilterValue, 1, 61, 53, // Skip to: 13726 -/* 97 */ MCD_OPC_CheckPredicate, 7, 57, 53, // Skip to: 13726 -/* 101 */ MCD_OPC_CheckField, 6, 5, 0, 51, 53, // Skip to: 13726 -/* 107 */ MCD_OPC_Decode, 131, 9, 59, // Opcode: MOVT_I -/* 111 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 142 -/* 115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 -/* 122 */ MCD_OPC_CheckPredicate, 1, 32, 53, // Skip to: 13726 -/* 126 */ MCD_OPC_Decode, 159, 12, 58, // Opcode: SRL -/* 130 */ MCD_OPC_FilterValue, 1, 24, 53, // Skip to: 13726 -/* 134 */ MCD_OPC_CheckPredicate, 6, 20, 53, // Skip to: 13726 -/* 138 */ MCD_OPC_Decode, 247, 10, 58, // Opcode: ROTR -/* 142 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 160 -/* 146 */ MCD_OPC_CheckPredicate, 5, 8, 53, // Skip to: 13726 -/* 150 */ MCD_OPC_CheckField, 21, 5, 0, 2, 53, // Skip to: 13726 -/* 156 */ MCD_OPC_Decode, 139, 12, 58, // Opcode: SRA -/* 160 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 178 -/* 164 */ MCD_OPC_CheckPredicate, 5, 246, 52, // Skip to: 13726 -/* 168 */ MCD_OPC_CheckField, 6, 5, 0, 240, 52, // Skip to: 13726 -/* 174 */ MCD_OPC_Decode, 233, 11, 36, // Opcode: SLLV -/* 178 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 196 -/* 182 */ MCD_OPC_CheckPredicate, 8, 228, 52, // Skip to: 13726 -/* 186 */ MCD_OPC_CheckField, 8, 3, 0, 222, 52, // Skip to: 13726 -/* 192 */ MCD_OPC_Decode, 205, 7, 60, // Opcode: LSA -/* 196 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 227 -/* 200 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 215 -/* 207 */ MCD_OPC_CheckPredicate, 5, 203, 52, // Skip to: 13726 -/* 211 */ MCD_OPC_Decode, 173, 12, 36, // Opcode: SRLV -/* 215 */ MCD_OPC_FilterValue, 1, 195, 52, // Skip to: 13726 -/* 219 */ MCD_OPC_CheckPredicate, 6, 191, 52, // Skip to: 13726 -/* 223 */ MCD_OPC_Decode, 248, 10, 36, // Opcode: ROTRV -/* 227 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 245 -/* 231 */ MCD_OPC_CheckPredicate, 5, 179, 52, // Skip to: 13726 -/* 235 */ MCD_OPC_CheckField, 6, 5, 0, 173, 52, // Skip to: 13726 -/* 241 */ MCD_OPC_Decode, 152, 12, 36, // Opcode: SRAV -/* 245 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 276 -/* 249 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... -/* 252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 264 -/* 256 */ MCD_OPC_CheckPredicate, 5, 154, 52, // Skip to: 13726 -/* 260 */ MCD_OPC_Decode, 136, 7, 61, // Opcode: JR -/* 264 */ MCD_OPC_FilterValue, 16, 146, 52, // Skip to: 13726 -/* 268 */ MCD_OPC_CheckPredicate, 9, 142, 52, // Skip to: 13726 -/* 272 */ MCD_OPC_Decode, 141, 7, 61, // Opcode: JR_HB -/* 276 */ MCD_OPC_FilterValue, 9, 39, 0, // Skip to: 319 -/* 280 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 283 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 301 -/* 287 */ MCD_OPC_CheckPredicate, 1, 123, 52, // Skip to: 13726 -/* 291 */ MCD_OPC_CheckField, 16, 5, 0, 117, 52, // Skip to: 13726 -/* 297 */ MCD_OPC_Decode, 249, 6, 62, // Opcode: JALR -/* 301 */ MCD_OPC_FilterValue, 16, 109, 52, // Skip to: 13726 -/* 305 */ MCD_OPC_CheckPredicate, 10, 105, 52, // Skip to: 13726 -/* 309 */ MCD_OPC_CheckField, 16, 5, 0, 99, 52, // Skip to: 13726 -/* 315 */ MCD_OPC_Decode, 128, 7, 62, // Opcode: JALR_HB -/* 319 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 337 -/* 323 */ MCD_OPC_CheckPredicate, 7, 87, 52, // Skip to: 13726 -/* 327 */ MCD_OPC_CheckField, 6, 5, 0, 81, 52, // Skip to: 13726 -/* 333 */ MCD_OPC_Decode, 143, 9, 63, // Opcode: MOVZ_I_I -/* 337 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 355 -/* 341 */ MCD_OPC_CheckPredicate, 7, 69, 52, // Skip to: 13726 -/* 345 */ MCD_OPC_CheckField, 6, 5, 0, 63, 52, // Skip to: 13726 -/* 351 */ MCD_OPC_Decode, 251, 8, 63, // Opcode: MOVN_I_I -/* 355 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 367 -/* 359 */ MCD_OPC_CheckPredicate, 5, 51, 52, // Skip to: 13726 -/* 363 */ MCD_OPC_Decode, 132, 13, 64, // Opcode: SYSCALL -/* 367 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 379 -/* 371 */ MCD_OPC_CheckPredicate, 5, 39, 52, // Skip to: 13726 -/* 375 */ MCD_OPC_Decode, 171, 2, 33, // Opcode: BREAK -/* 379 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 391 -/* 383 */ MCD_OPC_CheckPredicate, 10, 27, 52, // Skip to: 13726 -/* 387 */ MCD_OPC_Decode, 129, 13, 65, // Opcode: SYNC -/* 391 */ MCD_OPC_FilterValue, 16, 43, 0, // Skip to: 438 -/* 395 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 398 */ MCD_OPC_FilterValue, 0, 12, 52, // Skip to: 13726 -/* 402 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 405 */ MCD_OPC_FilterValue, 0, 5, 52, // Skip to: 13726 -/* 409 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 412 */ MCD_OPC_FilterValue, 0, 254, 51, // Skip to: 13726 -/* 416 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 430 -/* 420 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 430 -/* 426 */ MCD_OPC_Decode, 186, 8, 66, // Opcode: MFHI -/* 430 */ MCD_OPC_CheckPredicate, 12, 236, 51, // Skip to: 13726 -/* 434 */ MCD_OPC_Decode, 189, 8, 67, // Opcode: MFHI_DSP -/* 438 */ MCD_OPC_FilterValue, 17, 36, 0, // Skip to: 478 -/* 442 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 445 */ MCD_OPC_FilterValue, 0, 221, 51, // Skip to: 13726 -/* 449 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... -/* 452 */ MCD_OPC_FilterValue, 0, 214, 51, // Skip to: 13726 -/* 456 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 470 -/* 460 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 470 -/* 466 */ MCD_OPC_Decode, 176, 9, 61, // Opcode: MTHI -/* 470 */ MCD_OPC_CheckPredicate, 12, 196, 51, // Skip to: 13726 -/* 474 */ MCD_OPC_Decode, 178, 9, 68, // Opcode: MTHI_DSP -/* 478 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 525 -/* 482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 485 */ MCD_OPC_FilterValue, 0, 181, 51, // Skip to: 13726 -/* 489 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 492 */ MCD_OPC_FilterValue, 0, 174, 51, // Skip to: 13726 -/* 496 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 499 */ MCD_OPC_FilterValue, 0, 167, 51, // Skip to: 13726 -/* 503 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 517 -/* 507 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 517 -/* 513 */ MCD_OPC_Decode, 191, 8, 66, // Opcode: MFLO -/* 517 */ MCD_OPC_CheckPredicate, 12, 149, 51, // Skip to: 13726 -/* 521 */ MCD_OPC_Decode, 194, 8, 67, // Opcode: MFLO_DSP -/* 525 */ MCD_OPC_FilterValue, 19, 36, 0, // Skip to: 565 -/* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 532 */ MCD_OPC_FilterValue, 0, 134, 51, // Skip to: 13726 -/* 536 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... -/* 539 */ MCD_OPC_FilterValue, 0, 127, 51, // Skip to: 13726 -/* 543 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 557 -/* 547 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 557 -/* 553 */ MCD_OPC_Decode, 181, 9, 61, // Opcode: MTLO -/* 557 */ MCD_OPC_CheckPredicate, 12, 109, 51, // Skip to: 13726 -/* 561 */ MCD_OPC_Decode, 183, 9, 69, // Opcode: MTLO_DSP -/* 565 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 583 -/* 569 */ MCD_OPC_CheckPredicate, 14, 97, 51, // Skip to: 13726 -/* 573 */ MCD_OPC_CheckField, 8, 3, 0, 91, 51, // Skip to: 13726 -/* 579 */ MCD_OPC_Decode, 194, 4, 70, // Opcode: DLSA -/* 583 */ MCD_OPC_FilterValue, 24, 36, 0, // Skip to: 623 -/* 587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 590 */ MCD_OPC_FilterValue, 0, 76, 51, // Skip to: 13726 -/* 594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 597 */ MCD_OPC_FilterValue, 0, 69, 51, // Skip to: 13726 -/* 601 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 615 -/* 605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 615 -/* 611 */ MCD_OPC_Decode, 206, 9, 43, // Opcode: MULT -/* 615 */ MCD_OPC_CheckPredicate, 12, 51, 51, // Skip to: 13726 -/* 619 */ MCD_OPC_Decode, 208, 9, 71, // Opcode: MULT_DSP -/* 623 */ MCD_OPC_FilterValue, 25, 36, 0, // Skip to: 663 -/* 627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 630 */ MCD_OPC_FilterValue, 0, 36, 51, // Skip to: 13726 -/* 634 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 637 */ MCD_OPC_FilterValue, 0, 29, 51, // Skip to: 13726 -/* 641 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 655 -/* 645 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 655 -/* 651 */ MCD_OPC_Decode, 210, 9, 43, // Opcode: MULTu -/* 655 */ MCD_OPC_CheckPredicate, 12, 11, 51, // Skip to: 13726 -/* 659 */ MCD_OPC_Decode, 207, 9, 71, // Opcode: MULTU_DSP -/* 663 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 681 -/* 667 */ MCD_OPC_CheckPredicate, 13, 255, 50, // Skip to: 13726 -/* 671 */ MCD_OPC_CheckField, 6, 10, 0, 249, 50, // Skip to: 13726 -/* 677 */ MCD_OPC_Decode, 162, 11, 43, // Opcode: SDIV -/* 681 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 699 -/* 685 */ MCD_OPC_CheckPredicate, 13, 237, 50, // Skip to: 13726 -/* 689 */ MCD_OPC_CheckField, 6, 10, 0, 231, 50, // Skip to: 13726 -/* 695 */ MCD_OPC_Decode, 222, 13, 43, // Opcode: UDIV -/* 699 */ MCD_OPC_FilterValue, 32, 13, 0, // Skip to: 716 -/* 703 */ MCD_OPC_CheckPredicate, 5, 219, 50, // Skip to: 13726 -/* 707 */ MCD_OPC_CheckField, 6, 5, 0, 213, 50, // Skip to: 13726 -/* 713 */ MCD_OPC_Decode, 25, 35, // Opcode: ADD -/* 716 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 733 -/* 720 */ MCD_OPC_CheckPredicate, 5, 202, 50, // Skip to: 13726 -/* 724 */ MCD_OPC_CheckField, 6, 5, 0, 196, 50, // Skip to: 13726 -/* 730 */ MCD_OPC_Decode, 77, 35, // Opcode: ADDu -/* 733 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 751 -/* 737 */ MCD_OPC_CheckPredicate, 5, 185, 50, // Skip to: 13726 -/* 741 */ MCD_OPC_CheckField, 6, 5, 0, 179, 50, // Skip to: 13726 -/* 747 */ MCD_OPC_Decode, 190, 12, 35, // Opcode: SUB -/* 751 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 769 -/* 755 */ MCD_OPC_CheckPredicate, 5, 167, 50, // Skip to: 13726 -/* 759 */ MCD_OPC_CheckField, 6, 5, 0, 161, 50, // Skip to: 13726 -/* 765 */ MCD_OPC_Decode, 230, 12, 35, // Opcode: SUBu -/* 769 */ MCD_OPC_FilterValue, 36, 13, 0, // Skip to: 786 -/* 773 */ MCD_OPC_CheckPredicate, 1, 149, 50, // Skip to: 13726 -/* 777 */ MCD_OPC_CheckField, 6, 5, 0, 143, 50, // Skip to: 13726 -/* 783 */ MCD_OPC_Decode, 83, 35, // Opcode: AND -/* 786 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 804 -/* 790 */ MCD_OPC_CheckPredicate, 1, 132, 50, // Skip to: 13726 -/* 794 */ MCD_OPC_CheckField, 6, 5, 0, 126, 50, // Skip to: 13726 -/* 800 */ MCD_OPC_Decode, 133, 10, 35, // Opcode: OR -/* 804 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 822 -/* 808 */ MCD_OPC_CheckPredicate, 1, 114, 50, // Skip to: 13726 -/* 812 */ MCD_OPC_CheckField, 6, 5, 0, 108, 50, // Skip to: 13726 -/* 818 */ MCD_OPC_Decode, 236, 13, 35, // Opcode: XOR -/* 822 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 840 -/* 826 */ MCD_OPC_CheckPredicate, 5, 96, 50, // Skip to: 13726 -/* 830 */ MCD_OPC_CheckField, 6, 5, 0, 90, 50, // Skip to: 13726 -/* 836 */ MCD_OPC_Decode, 250, 9, 35, // Opcode: NOR -/* 840 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 858 -/* 844 */ MCD_OPC_CheckPredicate, 5, 78, 50, // Skip to: 13726 -/* 848 */ MCD_OPC_CheckField, 6, 5, 0, 72, 50, // Skip to: 13726 -/* 854 */ MCD_OPC_Decode, 240, 11, 35, // Opcode: SLT -/* 858 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 876 -/* 862 */ MCD_OPC_CheckPredicate, 5, 60, 50, // Skip to: 13726 -/* 866 */ MCD_OPC_CheckField, 6, 5, 0, 54, 50, // Skip to: 13726 -/* 872 */ MCD_OPC_Decode, 249, 11, 35, // Opcode: SLTu -/* 876 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 888 -/* 880 */ MCD_OPC_CheckPredicate, 15, 42, 50, // Skip to: 13726 -/* 884 */ MCD_OPC_Decode, 186, 13, 72, // Opcode: TGE -/* 888 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 900 -/* 892 */ MCD_OPC_CheckPredicate, 15, 30, 50, // Skip to: 13726 -/* 896 */ MCD_OPC_Decode, 191, 13, 72, // Opcode: TGEU -/* 900 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 912 -/* 904 */ MCD_OPC_CheckPredicate, 15, 18, 50, // Skip to: 13726 -/* 908 */ MCD_OPC_Decode, 202, 13, 72, // Opcode: TLT -/* 912 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 924 -/* 916 */ MCD_OPC_CheckPredicate, 15, 6, 50, // Skip to: 13726 -/* 920 */ MCD_OPC_Decode, 206, 13, 72, // Opcode: TLTU -/* 924 */ MCD_OPC_FilterValue, 52, 8, 0, // Skip to: 936 -/* 928 */ MCD_OPC_CheckPredicate, 15, 250, 49, // Skip to: 13726 -/* 932 */ MCD_OPC_Decode, 182, 13, 72, // Opcode: TEQ -/* 936 */ MCD_OPC_FilterValue, 54, 242, 49, // Skip to: 13726 -/* 940 */ MCD_OPC_CheckPredicate, 15, 238, 49, // Skip to: 13726 -/* 944 */ MCD_OPC_Decode, 209, 13, 72, // Opcode: TNE -/* 948 */ MCD_OPC_FilterValue, 1, 201, 0, // Skip to: 1153 -/* 952 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 -/* 959 */ MCD_OPC_CheckPredicate, 5, 219, 49, // Skip to: 13726 -/* 963 */ MCD_OPC_Decode, 131, 2, 73, // Opcode: BLTZ -/* 967 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 979 -/* 971 */ MCD_OPC_CheckPredicate, 5, 207, 49, // Skip to: 13726 -/* 975 */ MCD_OPC_Decode, 217, 1, 73, // Opcode: BGEZ -/* 979 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 991 -/* 983 */ MCD_OPC_CheckPredicate, 16, 195, 49, // Skip to: 13726 -/* 987 */ MCD_OPC_Decode, 139, 2, 73, // Opcode: BLTZL -/* 991 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1003 -/* 995 */ MCD_OPC_CheckPredicate, 16, 183, 49, // Skip to: 13726 -/* 999 */ MCD_OPC_Decode, 225, 1, 73, // Opcode: BGEZL -/* 1003 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1015 -/* 1007 */ MCD_OPC_CheckPredicate, 16, 171, 49, // Skip to: 13726 -/* 1011 */ MCD_OPC_Decode, 187, 13, 74, // Opcode: TGEI -/* 1015 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1027 -/* 1019 */ MCD_OPC_CheckPredicate, 16, 159, 49, // Skip to: 13726 -/* 1023 */ MCD_OPC_Decode, 188, 13, 74, // Opcode: TGEIU -/* 1027 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1039 -/* 1031 */ MCD_OPC_CheckPredicate, 16, 147, 49, // Skip to: 13726 -/* 1035 */ MCD_OPC_Decode, 203, 13, 74, // Opcode: TLTI -/* 1039 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1051 -/* 1043 */ MCD_OPC_CheckPredicate, 16, 135, 49, // Skip to: 13726 -/* 1047 */ MCD_OPC_Decode, 221, 13, 74, // Opcode: TTLTIU -/* 1051 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1063 -/* 1055 */ MCD_OPC_CheckPredicate, 16, 123, 49, // Skip to: 13726 -/* 1059 */ MCD_OPC_Decode, 183, 13, 74, // Opcode: TEQI -/* 1063 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1075 -/* 1067 */ MCD_OPC_CheckPredicate, 16, 111, 49, // Skip to: 13726 -/* 1071 */ MCD_OPC_Decode, 210, 13, 74, // Opcode: TNEI -/* 1075 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1087 -/* 1079 */ MCD_OPC_CheckPredicate, 13, 99, 49, // Skip to: 13726 -/* 1083 */ MCD_OPC_Decode, 133, 2, 73, // Opcode: BLTZAL -/* 1087 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1099 -/* 1091 */ MCD_OPC_CheckPredicate, 13, 87, 49, // Skip to: 13726 -/* 1095 */ MCD_OPC_Decode, 219, 1, 73, // Opcode: BGEZAL -/* 1099 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1111 -/* 1103 */ MCD_OPC_CheckPredicate, 16, 75, 49, // Skip to: 13726 -/* 1107 */ MCD_OPC_Decode, 135, 2, 73, // Opcode: BLTZALL -/* 1111 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1123 -/* 1115 */ MCD_OPC_CheckPredicate, 16, 63, 49, // Skip to: 13726 -/* 1119 */ MCD_OPC_Decode, 221, 1, 73, // Opcode: BGEZALL -/* 1123 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 1141 -/* 1127 */ MCD_OPC_CheckPredicate, 12, 51, 49, // Skip to: 13726 -/* 1131 */ MCD_OPC_CheckField, 21, 5, 0, 45, 49, // Skip to: 13726 -/* 1137 */ MCD_OPC_Decode, 169, 2, 75, // Opcode: BPOSGE32 -/* 1141 */ MCD_OPC_FilterValue, 31, 37, 49, // Skip to: 13726 -/* 1145 */ MCD_OPC_CheckPredicate, 6, 33, 49, // Skip to: 13726 -/* 1149 */ MCD_OPC_Decode, 130, 13, 76, // Opcode: SYNCI -/* 1153 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1165 -/* 1157 */ MCD_OPC_CheckPredicate, 10, 21, 49, // Skip to: 13726 -/* 1161 */ MCD_OPC_Decode, 247, 6, 77, // Opcode: J -/* 1165 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1177 -/* 1169 */ MCD_OPC_CheckPredicate, 5, 9, 49, // Skip to: 13726 -/* 1173 */ MCD_OPC_Decode, 248, 6, 77, // Opcode: JAL -/* 1177 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1189 -/* 1181 */ MCD_OPC_CheckPredicate, 5, 253, 48, // Skip to: 13726 -/* 1185 */ MCD_OPC_Decode, 206, 1, 78, // Opcode: BEQ -/* 1189 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1201 -/* 1193 */ MCD_OPC_CheckPredicate, 5, 241, 48, // Skip to: 13726 -/* 1197 */ MCD_OPC_Decode, 145, 2, 78, // Opcode: BNE -/* 1201 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1219 -/* 1205 */ MCD_OPC_CheckPredicate, 5, 229, 48, // Skip to: 13726 -/* 1209 */ MCD_OPC_CheckField, 16, 5, 0, 223, 48, // Skip to: 13726 -/* 1215 */ MCD_OPC_Decode, 251, 1, 73, // Opcode: BLEZ -/* 1219 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1237 -/* 1223 */ MCD_OPC_CheckPredicate, 5, 211, 48, // Skip to: 13726 -/* 1227 */ MCD_OPC_CheckField, 16, 5, 0, 205, 48, // Skip to: 13726 -/* 1233 */ MCD_OPC_Decode, 227, 1, 73, // Opcode: BGTZ -/* 1237 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 1248 -/* 1241 */ MCD_OPC_CheckPredicate, 13, 193, 48, // Skip to: 13726 -/* 1245 */ MCD_OPC_Decode, 73, 79, // Opcode: ADDi -/* 1248 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 1259 -/* 1252 */ MCD_OPC_CheckPredicate, 1, 182, 48, // Skip to: 13726 -/* 1256 */ MCD_OPC_Decode, 75, 79, // Opcode: ADDiu -/* 1259 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1271 -/* 1263 */ MCD_OPC_CheckPredicate, 5, 171, 48, // Skip to: 13726 -/* 1267 */ MCD_OPC_Decode, 243, 11, 79, // Opcode: SLTi -/* 1271 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1283 -/* 1275 */ MCD_OPC_CheckPredicate, 5, 159, 48, // Skip to: 13726 -/* 1279 */ MCD_OPC_Decode, 246, 11, 79, // Opcode: SLTiu -/* 1283 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1294 -/* 1287 */ MCD_OPC_CheckPredicate, 1, 147, 48, // Skip to: 13726 -/* 1291 */ MCD_OPC_Decode, 93, 80, // Opcode: ANDi -/* 1294 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1306 -/* 1298 */ MCD_OPC_CheckPredicate, 5, 136, 48, // Skip to: 13726 -/* 1302 */ MCD_OPC_Decode, 142, 10, 80, // Opcode: ORi -/* 1306 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1318 -/* 1310 */ MCD_OPC_CheckPredicate, 5, 124, 48, // Skip to: 13726 -/* 1314 */ MCD_OPC_Decode, 245, 13, 80, // Opcode: XORi -/* 1318 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1336 -/* 1322 */ MCD_OPC_CheckPredicate, 5, 112, 48, // Skip to: 13726 -/* 1326 */ MCD_OPC_CheckField, 21, 5, 0, 106, 48, // Skip to: 13726 -/* 1332 */ MCD_OPC_Decode, 210, 7, 52, // Opcode: LUi -/* 1336 */ MCD_OPC_FilterValue, 16, 220, 0, // Skip to: 1560 -/* 1340 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1343 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1361 -/* 1347 */ MCD_OPC_CheckPredicate, 10, 87, 48, // Skip to: 13726 -/* 1351 */ MCD_OPC_CheckField, 3, 8, 0, 81, 48, // Skip to: 13726 -/* 1357 */ MCD_OPC_Decode, 179, 8, 81, // Opcode: MFC0 -/* 1361 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1379 -/* 1365 */ MCD_OPC_CheckPredicate, 10, 69, 48, // Skip to: 13726 -/* 1369 */ MCD_OPC_CheckField, 3, 8, 0, 63, 48, // Skip to: 13726 -/* 1375 */ MCD_OPC_Decode, 169, 9, 81, // Opcode: MTC0 -/* 1379 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1434 -/* 1383 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1386 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1398 -/* 1390 */ MCD_OPC_CheckPredicate, 13, 44, 48, // Skip to: 13726 -/* 1394 */ MCD_OPC_Decode, 176, 1, 82, // Opcode: BC0F -/* 1398 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1410 -/* 1402 */ MCD_OPC_CheckPredicate, 13, 32, 48, // Skip to: 13726 -/* 1406 */ MCD_OPC_Decode, 178, 1, 82, // Opcode: BC0T -/* 1410 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1422 -/* 1414 */ MCD_OPC_CheckPredicate, 13, 20, 48, // Skip to: 13726 -/* 1418 */ MCD_OPC_Decode, 177, 1, 82, // Opcode: BC0FL -/* 1422 */ MCD_OPC_FilterValue, 3, 12, 48, // Skip to: 13726 -/* 1426 */ MCD_OPC_CheckPredicate, 13, 8, 48, // Skip to: 13726 -/* 1430 */ MCD_OPC_Decode, 179, 1, 82, // Opcode: BC0TL -/* 1434 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 1469 -/* 1438 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... -/* 1441 */ MCD_OPC_FilterValue, 128, 192, 1, 8, 0, // Skip to: 1455 -/* 1447 */ MCD_OPC_CheckPredicate, 6, 243, 47, // Skip to: 13726 -/* 1451 */ MCD_OPC_Decode, 179, 4, 42, // Opcode: DI -/* 1455 */ MCD_OPC_FilterValue, 160, 192, 1, 233, 47, // Skip to: 13726 -/* 1461 */ MCD_OPC_CheckPredicate, 6, 229, 47, // Skip to: 13726 -/* 1465 */ MCD_OPC_Decode, 141, 5, 42, // Opcode: EI -/* 1469 */ MCD_OPC_FilterValue, 16, 221, 47, // Skip to: 13726 -/* 1473 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... -/* 1476 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1488 -/* 1480 */ MCD_OPC_CheckPredicate, 5, 210, 47, // Skip to: 13726 -/* 1484 */ MCD_OPC_Decode, 196, 13, 0, // Opcode: TLBR -/* 1488 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1500 -/* 1492 */ MCD_OPC_CheckPredicate, 5, 198, 47, // Skip to: 13726 -/* 1496 */ MCD_OPC_Decode, 198, 13, 0, // Opcode: TLBWI -/* 1500 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1512 -/* 1504 */ MCD_OPC_CheckPredicate, 5, 186, 47, // Skip to: 13726 -/* 1508 */ MCD_OPC_Decode, 200, 13, 0, // Opcode: TLBWR -/* 1512 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1524 -/* 1516 */ MCD_OPC_CheckPredicate, 5, 174, 47, // Skip to: 13726 -/* 1520 */ MCD_OPC_Decode, 194, 13, 0, // Opcode: TLBP -/* 1524 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1536 -/* 1528 */ MCD_OPC_CheckPredicate, 17, 162, 47, // Skip to: 13726 -/* 1532 */ MCD_OPC_Decode, 143, 5, 0, // Opcode: ERET -/* 1536 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1548 -/* 1540 */ MCD_OPC_CheckPredicate, 10, 150, 47, // Skip to: 13726 -/* 1544 */ MCD_OPC_Decode, 174, 4, 0, // Opcode: DERET -/* 1548 */ MCD_OPC_FilterValue, 32, 142, 47, // Skip to: 13726 -/* 1552 */ MCD_OPC_CheckPredicate, 18, 138, 47, // Skip to: 13726 -/* 1556 */ MCD_OPC_Decode, 231, 13, 0, // Opcode: WAIT -/* 1560 */ MCD_OPC_FilterValue, 17, 21, 6, // Skip to: 3121 -/* 1564 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1567 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1585 -/* 1571 */ MCD_OPC_CheckPredicate, 5, 119, 47, // Skip to: 13726 -/* 1575 */ MCD_OPC_CheckField, 0, 11, 0, 113, 47, // Skip to: 13726 -/* 1581 */ MCD_OPC_Decode, 180, 8, 83, // Opcode: MFC1 -/* 1585 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1603 -/* 1589 */ MCD_OPC_CheckPredicate, 19, 101, 47, // Skip to: 13726 -/* 1593 */ MCD_OPC_CheckField, 0, 11, 0, 95, 47, // Skip to: 13726 -/* 1599 */ MCD_OPC_Decode, 197, 4, 84, // Opcode: DMFC1 -/* 1603 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 1621 -/* 1607 */ MCD_OPC_CheckPredicate, 5, 83, 47, // Skip to: 13726 -/* 1611 */ MCD_OPC_CheckField, 0, 11, 0, 77, 47, // Skip to: 13726 -/* 1617 */ MCD_OPC_Decode, 238, 2, 85, // Opcode: CFC1 -/* 1621 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 1639 -/* 1625 */ MCD_OPC_CheckPredicate, 20, 65, 47, // Skip to: 13726 -/* 1629 */ MCD_OPC_CheckField, 0, 11, 0, 59, 47, // Skip to: 13726 -/* 1635 */ MCD_OPC_Decode, 183, 8, 86, // Opcode: MFHC1_D32 -/* 1639 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1657 -/* 1643 */ MCD_OPC_CheckPredicate, 5, 47, 47, // Skip to: 13726 -/* 1647 */ MCD_OPC_CheckField, 0, 11, 0, 41, 47, // Skip to: 13726 -/* 1653 */ MCD_OPC_Decode, 170, 9, 87, // Opcode: MTC1 -/* 1657 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1675 -/* 1661 */ MCD_OPC_CheckPredicate, 19, 29, 47, // Skip to: 13726 -/* 1665 */ MCD_OPC_CheckField, 0, 11, 0, 23, 47, // Skip to: 13726 -/* 1671 */ MCD_OPC_Decode, 202, 4, 88, // Opcode: DMTC1 -/* 1675 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1693 -/* 1679 */ MCD_OPC_CheckPredicate, 5, 11, 47, // Skip to: 13726 -/* 1683 */ MCD_OPC_CheckField, 0, 11, 0, 5, 47, // Skip to: 13726 -/* 1689 */ MCD_OPC_Decode, 210, 3, 89, // Opcode: CTC1 -/* 1693 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1711 -/* 1697 */ MCD_OPC_CheckPredicate, 20, 249, 46, // Skip to: 13726 -/* 1701 */ MCD_OPC_CheckField, 0, 11, 0, 243, 46, // Skip to: 13726 -/* 1707 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: MTHC1_D32 -/* 1711 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1766 -/* 1715 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1718 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1730 -/* 1722 */ MCD_OPC_CheckPredicate, 13, 224, 46, // Skip to: 13726 -/* 1726 */ MCD_OPC_Decode, 181, 1, 91, // Opcode: BC1F -/* 1730 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1742 -/* 1734 */ MCD_OPC_CheckPredicate, 13, 212, 46, // Skip to: 13726 -/* 1738 */ MCD_OPC_Decode, 185, 1, 91, // Opcode: BC1T -/* 1742 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1754 -/* 1746 */ MCD_OPC_CheckPredicate, 16, 200, 46, // Skip to: 13726 -/* 1750 */ MCD_OPC_Decode, 182, 1, 91, // Opcode: BC1FL -/* 1754 */ MCD_OPC_FilterValue, 3, 192, 46, // Skip to: 13726 -/* 1758 */ MCD_OPC_CheckPredicate, 16, 188, 46, // Skip to: 13726 -/* 1762 */ MCD_OPC_Decode, 186, 1, 91, // Opcode: BC1TL -/* 1766 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1778 -/* 1770 */ MCD_OPC_CheckPredicate, 8, 176, 46, // Skip to: 13726 -/* 1774 */ MCD_OPC_Decode, 192, 2, 92, // Opcode: BZ_V -/* 1778 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1790 -/* 1782 */ MCD_OPC_CheckPredicate, 8, 164, 46, // Skip to: 13726 -/* 1786 */ MCD_OPC_Decode, 166, 2, 92, // Opcode: BNZ_V -/* 1790 */ MCD_OPC_FilterValue, 16, 80, 2, // Skip to: 2386 -/* 1794 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1809 -/* 1801 */ MCD_OPC_CheckPredicate, 5, 145, 46, // Skip to: 13726 -/* 1805 */ MCD_OPC_Decode, 174, 5, 93, // Opcode: FADD_S -/* 1809 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1821 -/* 1813 */ MCD_OPC_CheckPredicate, 5, 133, 46, // Skip to: 13726 -/* 1817 */ MCD_OPC_Decode, 176, 6, 93, // Opcode: FSUB_S -/* 1821 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1833 -/* 1825 */ MCD_OPC_CheckPredicate, 5, 121, 46, // Skip to: 13726 -/* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S -/* 1833 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1845 -/* 1837 */ MCD_OPC_CheckPredicate, 5, 109, 46, // Skip to: 13726 -/* 1841 */ MCD_OPC_Decode, 210, 5, 93, // Opcode: FDIV_S -/* 1845 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1863 -/* 1849 */ MCD_OPC_CheckPredicate, 15, 97, 46, // Skip to: 13726 -/* 1853 */ MCD_OPC_CheckField, 16, 5, 0, 91, 46, // Skip to: 13726 -/* 1859 */ MCD_OPC_Decode, 169, 6, 94, // Opcode: FSQRT_S -/* 1863 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1881 -/* 1867 */ MCD_OPC_CheckPredicate, 5, 79, 46, // Skip to: 13726 -/* 1871 */ MCD_OPC_CheckField, 16, 5, 0, 73, 46, // Skip to: 13726 -/* 1877 */ MCD_OPC_Decode, 167, 5, 94, // Opcode: FABS_S -/* 1881 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1899 -/* 1885 */ MCD_OPC_CheckPredicate, 5, 61, 46, // Skip to: 13726 -/* 1889 */ MCD_OPC_CheckField, 16, 5, 0, 55, 46, // Skip to: 13726 -/* 1895 */ MCD_OPC_Decode, 131, 6, 94, // Opcode: FMOV_S -/* 1899 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1917 -/* 1903 */ MCD_OPC_CheckPredicate, 5, 43, 46, // Skip to: 13726 -/* 1907 */ MCD_OPC_CheckField, 16, 5, 0, 37, 46, // Skip to: 13726 -/* 1913 */ MCD_OPC_Decode, 145, 6, 94, // Opcode: FNEG_S -/* 1917 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 1935 -/* 1921 */ MCD_OPC_CheckPredicate, 15, 25, 46, // Skip to: 13726 -/* 1925 */ MCD_OPC_CheckField, 16, 5, 0, 19, 46, // Skip to: 13726 -/* 1931 */ MCD_OPC_Decode, 128, 11, 94, // Opcode: ROUND_W_S -/* 1935 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 1953 -/* 1939 */ MCD_OPC_CheckPredicate, 15, 7, 46, // Skip to: 13726 -/* 1943 */ MCD_OPC_CheckField, 16, 5, 0, 1, 46, // Skip to: 13726 -/* 1949 */ MCD_OPC_Decode, 219, 13, 94, // Opcode: TRUNC_W_S -/* 1953 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 1971 -/* 1957 */ MCD_OPC_CheckPredicate, 15, 245, 45, // Skip to: 13726 -/* 1961 */ MCD_OPC_CheckField, 16, 5, 0, 239, 45, // Skip to: 13726 -/* 1967 */ MCD_OPC_Decode, 228, 2, 94, // Opcode: CEIL_W_S -/* 1971 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1989 -/* 1975 */ MCD_OPC_CheckPredicate, 15, 227, 45, // Skip to: 13726 -/* 1979 */ MCD_OPC_CheckField, 16, 5, 0, 221, 45, // Skip to: 13726 -/* 1985 */ MCD_OPC_Decode, 244, 5, 94, // Opcode: FLOOR_W_S -/* 1989 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2020 -/* 1993 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1996 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2008 -/* 2000 */ MCD_OPC_CheckPredicate, 7, 202, 45, // Skip to: 13726 -/* 2004 */ MCD_OPC_Decode, 242, 8, 95, // Opcode: MOVF_S -/* 2008 */ MCD_OPC_FilterValue, 1, 194, 45, // Skip to: 13726 -/* 2012 */ MCD_OPC_CheckPredicate, 7, 190, 45, // Skip to: 13726 -/* 2016 */ MCD_OPC_Decode, 134, 9, 95, // Opcode: MOVT_S -/* 2020 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2032 -/* 2024 */ MCD_OPC_CheckPredicate, 7, 178, 45, // Skip to: 13726 -/* 2028 */ MCD_OPC_Decode, 146, 9, 96, // Opcode: MOVZ_I_S -/* 2032 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2044 -/* 2036 */ MCD_OPC_CheckPredicate, 7, 166, 45, // Skip to: 13726 -/* 2040 */ MCD_OPC_Decode, 254, 8, 96, // Opcode: MOVN_I_S -/* 2044 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2062 -/* 2048 */ MCD_OPC_CheckPredicate, 21, 154, 45, // Skip to: 13726 -/* 2052 */ MCD_OPC_CheckField, 16, 5, 0, 148, 45, // Skip to: 13726 -/* 2058 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: CVT_D32_S -/* 2062 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2080 -/* 2066 */ MCD_OPC_CheckPredicate, 5, 136, 45, // Skip to: 13726 -/* 2070 */ MCD_OPC_CheckField, 16, 5, 0, 130, 45, // Skip to: 13726 -/* 2076 */ MCD_OPC_Decode, 233, 3, 94, // Opcode: CVT_W_S -/* 2080 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2098 -/* 2084 */ MCD_OPC_CheckPredicate, 22, 118, 45, // Skip to: 13726 -/* 2088 */ MCD_OPC_CheckField, 16, 5, 0, 112, 45, // Skip to: 13726 -/* 2094 */ MCD_OPC_Decode, 222, 3, 98, // Opcode: CVT_L_S -/* 2098 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2116 -/* 2102 */ MCD_OPC_CheckPredicate, 13, 100, 45, // Skip to: 13726 -/* 2106 */ MCD_OPC_CheckField, 6, 5, 0, 94, 45, // Skip to: 13726 -/* 2112 */ MCD_OPC_Decode, 240, 3, 99, // Opcode: C_F_S -/* 2116 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2134 -/* 2120 */ MCD_OPC_CheckPredicate, 13, 82, 45, // Skip to: 13726 -/* 2124 */ MCD_OPC_CheckField, 6, 5, 0, 76, 45, // Skip to: 13726 -/* 2130 */ MCD_OPC_Decode, 154, 4, 99, // Opcode: C_UN_S -/* 2134 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2152 -/* 2138 */ MCD_OPC_CheckPredicate, 13, 64, 45, // Skip to: 13726 -/* 2142 */ MCD_OPC_CheckField, 6, 5, 0, 58, 45, // Skip to: 13726 -/* 2148 */ MCD_OPC_Decode, 237, 3, 99, // Opcode: C_EQ_S -/* 2152 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2170 -/* 2156 */ MCD_OPC_CheckPredicate, 13, 46, 45, // Skip to: 13726 -/* 2160 */ MCD_OPC_CheckField, 6, 5, 0, 40, 45, // Skip to: 13726 -/* 2166 */ MCD_OPC_Decode, 145, 4, 99, // Opcode: C_UEQ_S -/* 2170 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2188 -/* 2174 */ MCD_OPC_CheckPredicate, 13, 28, 45, // Skip to: 13726 -/* 2178 */ MCD_OPC_CheckField, 6, 5, 0, 22, 45, // Skip to: 13726 -/* 2184 */ MCD_OPC_Decode, 136, 4, 99, // Opcode: C_OLT_S -/* 2188 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2206 -/* 2192 */ MCD_OPC_CheckPredicate, 13, 10, 45, // Skip to: 13726 -/* 2196 */ MCD_OPC_CheckField, 6, 5, 0, 4, 45, // Skip to: 13726 -/* 2202 */ MCD_OPC_Decode, 151, 4, 99, // Opcode: C_ULT_S -/* 2206 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2224 -/* 2210 */ MCD_OPC_CheckPredicate, 13, 248, 44, // Skip to: 13726 -/* 2214 */ MCD_OPC_CheckField, 6, 5, 0, 242, 44, // Skip to: 13726 -/* 2220 */ MCD_OPC_Decode, 133, 4, 99, // Opcode: C_OLE_S -/* 2224 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2242 -/* 2228 */ MCD_OPC_CheckPredicate, 13, 230, 44, // Skip to: 13726 -/* 2232 */ MCD_OPC_CheckField, 6, 5, 0, 224, 44, // Skip to: 13726 -/* 2238 */ MCD_OPC_Decode, 148, 4, 99, // Opcode: C_ULE_S -/* 2242 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2260 -/* 2246 */ MCD_OPC_CheckPredicate, 13, 212, 44, // Skip to: 13726 -/* 2250 */ MCD_OPC_CheckField, 6, 5, 0, 206, 44, // Skip to: 13726 -/* 2256 */ MCD_OPC_Decode, 142, 4, 99, // Opcode: C_SF_S -/* 2260 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2278 -/* 2264 */ MCD_OPC_CheckPredicate, 13, 194, 44, // Skip to: 13726 -/* 2268 */ MCD_OPC_CheckField, 6, 5, 0, 188, 44, // Skip to: 13726 -/* 2274 */ MCD_OPC_Decode, 252, 3, 99, // Opcode: C_NGLE_S -/* 2278 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2296 -/* 2282 */ MCD_OPC_CheckPredicate, 13, 176, 44, // Skip to: 13726 -/* 2286 */ MCD_OPC_CheckField, 6, 5, 0, 170, 44, // Skip to: 13726 -/* 2292 */ MCD_OPC_Decode, 139, 4, 99, // Opcode: C_SEQ_S -/* 2296 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2314 -/* 2300 */ MCD_OPC_CheckPredicate, 13, 158, 44, // Skip to: 13726 -/* 2304 */ MCD_OPC_CheckField, 6, 5, 0, 152, 44, // Skip to: 13726 -/* 2310 */ MCD_OPC_Decode, 255, 3, 99, // Opcode: C_NGL_S -/* 2314 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2332 -/* 2318 */ MCD_OPC_CheckPredicate, 13, 140, 44, // Skip to: 13726 -/* 2322 */ MCD_OPC_CheckField, 6, 5, 0, 134, 44, // Skip to: 13726 -/* 2328 */ MCD_OPC_Decode, 246, 3, 99, // Opcode: C_LT_S -/* 2332 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2350 -/* 2336 */ MCD_OPC_CheckPredicate, 13, 122, 44, // Skip to: 13726 -/* 2340 */ MCD_OPC_CheckField, 6, 5, 0, 116, 44, // Skip to: 13726 -/* 2346 */ MCD_OPC_Decode, 249, 3, 99, // Opcode: C_NGE_S -/* 2350 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2368 -/* 2354 */ MCD_OPC_CheckPredicate, 13, 104, 44, // Skip to: 13726 -/* 2358 */ MCD_OPC_CheckField, 6, 5, 0, 98, 44, // Skip to: 13726 -/* 2364 */ MCD_OPC_Decode, 243, 3, 99, // Opcode: C_LE_S -/* 2368 */ MCD_OPC_FilterValue, 63, 90, 44, // Skip to: 13726 -/* 2372 */ MCD_OPC_CheckPredicate, 13, 86, 44, // Skip to: 13726 -/* 2376 */ MCD_OPC_CheckField, 6, 5, 0, 80, 44, // Skip to: 13726 -/* 2382 */ MCD_OPC_Decode, 130, 4, 99, // Opcode: C_NGT_S -/* 2386 */ MCD_OPC_FilterValue, 17, 80, 2, // Skip to: 2982 -/* 2390 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2393 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2405 -/* 2397 */ MCD_OPC_CheckPredicate, 21, 61, 44, // Skip to: 13726 -/* 2401 */ MCD_OPC_Decode, 171, 5, 100, // Opcode: FADD_D32 -/* 2405 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2417 -/* 2409 */ MCD_OPC_CheckPredicate, 21, 49, 44, // Skip to: 13726 -/* 2413 */ MCD_OPC_Decode, 173, 6, 100, // Opcode: FSUB_D32 -/* 2417 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2429 -/* 2421 */ MCD_OPC_CheckPredicate, 21, 37, 44, // Skip to: 13726 -/* 2425 */ MCD_OPC_Decode, 136, 6, 100, // Opcode: FMUL_D32 -/* 2429 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2441 -/* 2433 */ MCD_OPC_CheckPredicate, 21, 25, 44, // Skip to: 13726 -/* 2437 */ MCD_OPC_Decode, 207, 5, 100, // Opcode: FDIV_D32 -/* 2441 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2459 -/* 2445 */ MCD_OPC_CheckPredicate, 23, 13, 44, // Skip to: 13726 -/* 2449 */ MCD_OPC_CheckField, 16, 5, 0, 7, 44, // Skip to: 13726 -/* 2455 */ MCD_OPC_Decode, 166, 6, 101, // Opcode: FSQRT_D32 -/* 2459 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2477 -/* 2463 */ MCD_OPC_CheckPredicate, 21, 251, 43, // Skip to: 13726 -/* 2467 */ MCD_OPC_CheckField, 16, 5, 0, 245, 43, // Skip to: 13726 -/* 2473 */ MCD_OPC_Decode, 164, 5, 101, // Opcode: FABS_D32 -/* 2477 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2495 -/* 2481 */ MCD_OPC_CheckPredicate, 21, 233, 43, // Skip to: 13726 -/* 2485 */ MCD_OPC_CheckField, 16, 5, 0, 227, 43, // Skip to: 13726 -/* 2491 */ MCD_OPC_Decode, 128, 6, 101, // Opcode: FMOV_D32 -/* 2495 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2513 -/* 2499 */ MCD_OPC_CheckPredicate, 21, 215, 43, // Skip to: 13726 -/* 2503 */ MCD_OPC_CheckField, 16, 5, 0, 209, 43, // Skip to: 13726 -/* 2509 */ MCD_OPC_Decode, 142, 6, 101, // Opcode: FNEG_D32 -/* 2513 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 2531 -/* 2517 */ MCD_OPC_CheckPredicate, 23, 197, 43, // Skip to: 13726 -/* 2521 */ MCD_OPC_CheckField, 16, 5, 0, 191, 43, // Skip to: 13726 -/* 2527 */ MCD_OPC_Decode, 253, 10, 102, // Opcode: ROUND_W_D32 -/* 2531 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 2549 -/* 2535 */ MCD_OPC_CheckPredicate, 23, 179, 43, // Skip to: 13726 -/* 2539 */ MCD_OPC_CheckField, 16, 5, 0, 173, 43, // Skip to: 13726 -/* 2545 */ MCD_OPC_Decode, 216, 13, 102, // Opcode: TRUNC_W_D32 -/* 2549 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 2567 -/* 2553 */ MCD_OPC_CheckPredicate, 23, 161, 43, // Skip to: 13726 -/* 2557 */ MCD_OPC_CheckField, 16, 5, 0, 155, 43, // Skip to: 13726 -/* 2563 */ MCD_OPC_Decode, 225, 2, 102, // Opcode: CEIL_W_D32 -/* 2567 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 2585 -/* 2571 */ MCD_OPC_CheckPredicate, 23, 143, 43, // Skip to: 13726 -/* 2575 */ MCD_OPC_CheckField, 16, 5, 0, 137, 43, // Skip to: 13726 -/* 2581 */ MCD_OPC_Decode, 241, 5, 102, // Opcode: FLOOR_W_D32 -/* 2585 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2616 -/* 2589 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 2592 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2604 -/* 2596 */ MCD_OPC_CheckPredicate, 24, 118, 43, // Skip to: 13726 -/* 2600 */ MCD_OPC_Decode, 236, 8, 103, // Opcode: MOVF_D32 -/* 2604 */ MCD_OPC_FilterValue, 1, 110, 43, // Skip to: 13726 -/* 2608 */ MCD_OPC_CheckPredicate, 24, 106, 43, // Skip to: 13726 -/* 2612 */ MCD_OPC_Decode, 128, 9, 103, // Opcode: MOVT_D32 -/* 2616 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2628 -/* 2620 */ MCD_OPC_CheckPredicate, 24, 94, 43, // Skip to: 13726 -/* 2624 */ MCD_OPC_Decode, 140, 9, 104, // Opcode: MOVZ_I_D32 -/* 2628 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2640 -/* 2632 */ MCD_OPC_CheckPredicate, 24, 82, 43, // Skip to: 13726 -/* 2636 */ MCD_OPC_Decode, 248, 8, 104, // Opcode: MOVN_I_D32 -/* 2640 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2658 -/* 2644 */ MCD_OPC_CheckPredicate, 21, 70, 43, // Skip to: 13726 -/* 2648 */ MCD_OPC_CheckField, 16, 5, 0, 64, 43, // Skip to: 13726 -/* 2654 */ MCD_OPC_Decode, 224, 3, 102, // Opcode: CVT_S_D32 -/* 2658 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2676 -/* 2662 */ MCD_OPC_CheckPredicate, 21, 52, 43, // Skip to: 13726 -/* 2666 */ MCD_OPC_CheckField, 16, 5, 0, 46, 43, // Skip to: 13726 -/* 2672 */ MCD_OPC_Decode, 230, 3, 102, // Opcode: CVT_W_D32 -/* 2676 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2694 -/* 2680 */ MCD_OPC_CheckPredicate, 22, 34, 43, // Skip to: 13726 -/* 2684 */ MCD_OPC_CheckField, 16, 5, 0, 28, 43, // Skip to: 13726 -/* 2690 */ MCD_OPC_Decode, 220, 3, 105, // Opcode: CVT_L_D64 -/* 2694 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2712 -/* 2698 */ MCD_OPC_CheckPredicate, 25, 16, 43, // Skip to: 13726 -/* 2702 */ MCD_OPC_CheckField, 6, 5, 0, 10, 43, // Skip to: 13726 -/* 2708 */ MCD_OPC_Decode, 238, 3, 106, // Opcode: C_F_D32 -/* 2712 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2730 -/* 2716 */ MCD_OPC_CheckPredicate, 25, 254, 42, // Skip to: 13726 -/* 2720 */ MCD_OPC_CheckField, 6, 5, 0, 248, 42, // Skip to: 13726 -/* 2726 */ MCD_OPC_Decode, 152, 4, 106, // Opcode: C_UN_D32 -/* 2730 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2748 -/* 2734 */ MCD_OPC_CheckPredicate, 25, 236, 42, // Skip to: 13726 -/* 2738 */ MCD_OPC_CheckField, 6, 5, 0, 230, 42, // Skip to: 13726 -/* 2744 */ MCD_OPC_Decode, 235, 3, 106, // Opcode: C_EQ_D32 -/* 2748 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2766 -/* 2752 */ MCD_OPC_CheckPredicate, 25, 218, 42, // Skip to: 13726 -/* 2756 */ MCD_OPC_CheckField, 6, 5, 0, 212, 42, // Skip to: 13726 -/* 2762 */ MCD_OPC_Decode, 143, 4, 106, // Opcode: C_UEQ_D32 -/* 2766 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2784 -/* 2770 */ MCD_OPC_CheckPredicate, 25, 200, 42, // Skip to: 13726 -/* 2774 */ MCD_OPC_CheckField, 6, 5, 0, 194, 42, // Skip to: 13726 -/* 2780 */ MCD_OPC_Decode, 134, 4, 106, // Opcode: C_OLT_D32 -/* 2784 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2802 -/* 2788 */ MCD_OPC_CheckPredicate, 25, 182, 42, // Skip to: 13726 -/* 2792 */ MCD_OPC_CheckField, 6, 5, 0, 176, 42, // Skip to: 13726 -/* 2798 */ MCD_OPC_Decode, 149, 4, 106, // Opcode: C_ULT_D32 -/* 2802 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2820 -/* 2806 */ MCD_OPC_CheckPredicate, 25, 164, 42, // Skip to: 13726 -/* 2810 */ MCD_OPC_CheckField, 6, 5, 0, 158, 42, // Skip to: 13726 -/* 2816 */ MCD_OPC_Decode, 131, 4, 106, // Opcode: C_OLE_D32 -/* 2820 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2838 -/* 2824 */ MCD_OPC_CheckPredicate, 25, 146, 42, // Skip to: 13726 -/* 2828 */ MCD_OPC_CheckField, 6, 5, 0, 140, 42, // Skip to: 13726 -/* 2834 */ MCD_OPC_Decode, 146, 4, 106, // Opcode: C_ULE_D32 -/* 2838 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2856 -/* 2842 */ MCD_OPC_CheckPredicate, 25, 128, 42, // Skip to: 13726 -/* 2846 */ MCD_OPC_CheckField, 6, 5, 0, 122, 42, // Skip to: 13726 -/* 2852 */ MCD_OPC_Decode, 140, 4, 106, // Opcode: C_SF_D32 -/* 2856 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2874 -/* 2860 */ MCD_OPC_CheckPredicate, 25, 110, 42, // Skip to: 13726 -/* 2864 */ MCD_OPC_CheckField, 6, 5, 0, 104, 42, // Skip to: 13726 -/* 2870 */ MCD_OPC_Decode, 250, 3, 106, // Opcode: C_NGLE_D32 -/* 2874 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2892 -/* 2878 */ MCD_OPC_CheckPredicate, 25, 92, 42, // Skip to: 13726 -/* 2882 */ MCD_OPC_CheckField, 6, 5, 0, 86, 42, // Skip to: 13726 -/* 2888 */ MCD_OPC_Decode, 137, 4, 106, // Opcode: C_SEQ_D32 -/* 2892 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2910 -/* 2896 */ MCD_OPC_CheckPredicate, 25, 74, 42, // Skip to: 13726 -/* 2900 */ MCD_OPC_CheckField, 6, 5, 0, 68, 42, // Skip to: 13726 -/* 2906 */ MCD_OPC_Decode, 253, 3, 106, // Opcode: C_NGL_D32 -/* 2910 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2928 -/* 2914 */ MCD_OPC_CheckPredicate, 25, 56, 42, // Skip to: 13726 -/* 2918 */ MCD_OPC_CheckField, 6, 5, 0, 50, 42, // Skip to: 13726 -/* 2924 */ MCD_OPC_Decode, 244, 3, 106, // Opcode: C_LT_D32 -/* 2928 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2946 -/* 2932 */ MCD_OPC_CheckPredicate, 25, 38, 42, // Skip to: 13726 -/* 2936 */ MCD_OPC_CheckField, 6, 5, 0, 32, 42, // Skip to: 13726 -/* 2942 */ MCD_OPC_Decode, 247, 3, 106, // Opcode: C_NGE_D32 -/* 2946 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2964 -/* 2950 */ MCD_OPC_CheckPredicate, 25, 20, 42, // Skip to: 13726 -/* 2954 */ MCD_OPC_CheckField, 6, 5, 0, 14, 42, // Skip to: 13726 -/* 2960 */ MCD_OPC_Decode, 241, 3, 106, // Opcode: C_LE_D32 -/* 2964 */ MCD_OPC_FilterValue, 63, 6, 42, // Skip to: 13726 -/* 2968 */ MCD_OPC_CheckPredicate, 25, 2, 42, // Skip to: 13726 -/* 2972 */ MCD_OPC_CheckField, 6, 5, 0, 252, 41, // Skip to: 13726 -/* 2978 */ MCD_OPC_Decode, 128, 4, 106, // Opcode: C_NGT_D32 -/* 2982 */ MCD_OPC_FilterValue, 20, 39, 0, // Skip to: 3025 -/* 2986 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2989 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3007 -/* 2993 */ MCD_OPC_CheckPredicate, 5, 233, 41, // Skip to: 13726 -/* 2997 */ MCD_OPC_CheckField, 16, 5, 0, 227, 41, // Skip to: 13726 -/* 3003 */ MCD_OPC_Decode, 228, 3, 94, // Opcode: CVT_S_W -/* 3007 */ MCD_OPC_FilterValue, 33, 219, 41, // Skip to: 13726 -/* 3011 */ MCD_OPC_CheckPredicate, 21, 215, 41, // Skip to: 13726 -/* 3015 */ MCD_OPC_CheckField, 16, 5, 0, 209, 41, // Skip to: 13726 -/* 3021 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: CVT_D32_W -/* 3025 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 3037 -/* 3029 */ MCD_OPC_CheckPredicate, 8, 197, 41, // Skip to: 13726 -/* 3033 */ MCD_OPC_Decode, 189, 2, 92, // Opcode: BZ_B -/* 3037 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 3049 -/* 3041 */ MCD_OPC_CheckPredicate, 8, 185, 41, // Skip to: 13726 -/* 3045 */ MCD_OPC_Decode, 191, 2, 107, // Opcode: BZ_H -/* 3049 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 3061 -/* 3053 */ MCD_OPC_CheckPredicate, 8, 173, 41, // Skip to: 13726 -/* 3057 */ MCD_OPC_Decode, 193, 2, 108, // Opcode: BZ_W -/* 3061 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 3073 -/* 3065 */ MCD_OPC_CheckPredicate, 8, 161, 41, // Skip to: 13726 -/* 3069 */ MCD_OPC_Decode, 190, 2, 109, // Opcode: BZ_D -/* 3073 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 3085 -/* 3077 */ MCD_OPC_CheckPredicate, 8, 149, 41, // Skip to: 13726 -/* 3081 */ MCD_OPC_Decode, 163, 2, 92, // Opcode: BNZ_B -/* 3085 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3097 -/* 3089 */ MCD_OPC_CheckPredicate, 8, 137, 41, // Skip to: 13726 -/* 3093 */ MCD_OPC_Decode, 165, 2, 107, // Opcode: BNZ_H -/* 3097 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 3109 -/* 3101 */ MCD_OPC_CheckPredicate, 8, 125, 41, // Skip to: 13726 -/* 3105 */ MCD_OPC_Decode, 167, 2, 108, // Opcode: BNZ_W -/* 3109 */ MCD_OPC_FilterValue, 31, 117, 41, // Skip to: 13726 -/* 3113 */ MCD_OPC_CheckPredicate, 8, 113, 41, // Skip to: 13726 -/* 3117 */ MCD_OPC_Decode, 164, 2, 109, // Opcode: BNZ_D -/* 3121 */ MCD_OPC_FilterValue, 18, 94, 0, // Skip to: 3219 -/* 3125 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3128 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3146 -/* 3132 */ MCD_OPC_CheckPredicate, 5, 94, 41, // Skip to: 13726 -/* 3136 */ MCD_OPC_CheckField, 3, 8, 0, 88, 41, // Skip to: 13726 -/* 3142 */ MCD_OPC_Decode, 182, 8, 81, // Opcode: MFC2 -/* 3146 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3164 -/* 3150 */ MCD_OPC_CheckPredicate, 5, 76, 41, // Skip to: 13726 -/* 3154 */ MCD_OPC_CheckField, 3, 8, 0, 70, 41, // Skip to: 13726 -/* 3160 */ MCD_OPC_Decode, 172, 9, 81, // Opcode: MTC2 -/* 3164 */ MCD_OPC_FilterValue, 8, 62, 41, // Skip to: 13726 -/* 3168 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 3171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3183 -/* 3175 */ MCD_OPC_CheckPredicate, 13, 51, 41, // Skip to: 13726 -/* 3179 */ MCD_OPC_Decode, 189, 1, 82, // Opcode: BC2F -/* 3183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3195 -/* 3187 */ MCD_OPC_CheckPredicate, 13, 39, 41, // Skip to: 13726 -/* 3191 */ MCD_OPC_Decode, 192, 1, 82, // Opcode: BC2T -/* 3195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3207 -/* 3199 */ MCD_OPC_CheckPredicate, 13, 27, 41, // Skip to: 13726 -/* 3203 */ MCD_OPC_Decode, 190, 1, 82, // Opcode: BC2FL -/* 3207 */ MCD_OPC_FilterValue, 3, 19, 41, // Skip to: 13726 -/* 3211 */ MCD_OPC_CheckPredicate, 13, 15, 41, // Skip to: 13726 -/* 3215 */ MCD_OPC_Decode, 193, 1, 82, // Opcode: BC2TL -/* 3219 */ MCD_OPC_FilterValue, 19, 9, 1, // Skip to: 3488 -/* 3223 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3226 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 3281 -/* 3230 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 3233 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3245 -/* 3237 */ MCD_OPC_CheckPredicate, 13, 40, 0, // Skip to: 3281 -/* 3241 */ MCD_OPC_Decode, 194, 1, 82, // Opcode: BC3F -/* 3245 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3257 -/* 3249 */ MCD_OPC_CheckPredicate, 13, 28, 0, // Skip to: 3281 -/* 3253 */ MCD_OPC_Decode, 196, 1, 82, // Opcode: BC3T -/* 3257 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3269 -/* 3261 */ MCD_OPC_CheckPredicate, 13, 16, 0, // Skip to: 3281 -/* 3265 */ MCD_OPC_Decode, 195, 1, 82, // Opcode: BC3FL -/* 3269 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3281 -/* 3273 */ MCD_OPC_CheckPredicate, 13, 4, 0, // Skip to: 3281 -/* 3277 */ MCD_OPC_Decode, 197, 1, 82, // Opcode: BC3TL -/* 3281 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3302 -/* 3288 */ MCD_OPC_CheckPredicate, 26, 194, 40, // Skip to: 13726 -/* 3292 */ MCD_OPC_CheckField, 11, 5, 0, 188, 40, // Skip to: 13726 -/* 3298 */ MCD_OPC_Decode, 237, 7, 110, // Opcode: LWXC1 -/* 3302 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3320 -/* 3306 */ MCD_OPC_CheckPredicate, 27, 176, 40, // Skip to: 13726 -/* 3310 */ MCD_OPC_CheckField, 11, 5, 0, 170, 40, // Skip to: 13726 -/* 3316 */ MCD_OPC_Decode, 175, 7, 111, // Opcode: LDXC1 -/* 3320 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3338 -/* 3324 */ MCD_OPC_CheckPredicate, 28, 158, 40, // Skip to: 13726 -/* 3328 */ MCD_OPC_CheckField, 11, 5, 0, 152, 40, // Skip to: 13726 -/* 3334 */ MCD_OPC_Decode, 207, 7, 111, // Opcode: LUXC1 -/* 3338 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3356 -/* 3342 */ MCD_OPC_CheckPredicate, 26, 140, 40, // Skip to: 13726 -/* 3346 */ MCD_OPC_CheckField, 6, 5, 0, 134, 40, // Skip to: 13726 -/* 3352 */ MCD_OPC_Decode, 254, 12, 112, // Opcode: SWXC1 -/* 3356 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3374 -/* 3360 */ MCD_OPC_CheckPredicate, 27, 122, 40, // Skip to: 13726 -/* 3364 */ MCD_OPC_CheckField, 6, 5, 0, 116, 40, // Skip to: 13726 -/* 3370 */ MCD_OPC_Decode, 166, 11, 113, // Opcode: SDXC1 -/* 3374 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3392 -/* 3378 */ MCD_OPC_CheckPredicate, 28, 104, 40, // Skip to: 13726 -/* 3382 */ MCD_OPC_CheckField, 6, 5, 0, 98, 40, // Skip to: 13726 -/* 3388 */ MCD_OPC_Decode, 232, 12, 113, // Opcode: SUXC1 -/* 3392 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3404 -/* 3396 */ MCD_OPC_CheckPredicate, 26, 86, 40, // Skip to: 13726 -/* 3400 */ MCD_OPC_Decode, 149, 8, 114, // Opcode: MADD_S -/* 3404 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3416 -/* 3408 */ MCD_OPC_CheckPredicate, 29, 74, 40, // Skip to: 13726 -/* 3412 */ MCD_OPC_Decode, 142, 8, 115, // Opcode: MADD_D32 -/* 3416 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3428 -/* 3420 */ MCD_OPC_CheckPredicate, 26, 62, 40, // Skip to: 13726 -/* 3424 */ MCD_OPC_Decode, 167, 9, 114, // Opcode: MSUB_S -/* 3428 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3440 -/* 3432 */ MCD_OPC_CheckPredicate, 29, 50, 40, // Skip to: 13726 -/* 3436 */ MCD_OPC_Decode, 160, 9, 115, // Opcode: MSUB_D32 -/* 3440 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 3452 -/* 3444 */ MCD_OPC_CheckPredicate, 26, 38, 40, // Skip to: 13726 -/* 3448 */ MCD_OPC_Decode, 242, 9, 114, // Opcode: NMADD_S -/* 3452 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3464 -/* 3456 */ MCD_OPC_CheckPredicate, 29, 26, 40, // Skip to: 13726 -/* 3460 */ MCD_OPC_Decode, 239, 9, 115, // Opcode: NMADD_D32 -/* 3464 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 3476 -/* 3468 */ MCD_OPC_CheckPredicate, 26, 14, 40, // Skip to: 13726 -/* 3472 */ MCD_OPC_Decode, 247, 9, 114, // Opcode: NMSUB_S -/* 3476 */ MCD_OPC_FilterValue, 57, 6, 40, // Skip to: 13726 -/* 3480 */ MCD_OPC_CheckPredicate, 29, 2, 40, // Skip to: 13726 -/* 3484 */ MCD_OPC_Decode, 244, 9, 115, // Opcode: NMSUB_D32 -/* 3488 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 3500 -/* 3492 */ MCD_OPC_CheckPredicate, 16, 246, 39, // Skip to: 13726 -/* 3496 */ MCD_OPC_Decode, 209, 1, 78, // Opcode: BEQL -/* 3500 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 3512 -/* 3504 */ MCD_OPC_CheckPredicate, 16, 234, 39, // Skip to: 13726 -/* 3508 */ MCD_OPC_Decode, 156, 2, 78, // Opcode: BNEL -/* 3512 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 3530 -/* 3516 */ MCD_OPC_CheckPredicate, 16, 222, 39, // Skip to: 13726 -/* 3520 */ MCD_OPC_CheckField, 16, 5, 0, 216, 39, // Skip to: 13726 -/* 3526 */ MCD_OPC_Decode, 255, 1, 73, // Opcode: BLEZL -/* 3530 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3548 -/* 3534 */ MCD_OPC_CheckPredicate, 16, 204, 39, // Skip to: 13726 -/* 3538 */ MCD_OPC_CheckField, 16, 5, 0, 198, 39, // Skip to: 13726 -/* 3544 */ MCD_OPC_Decode, 231, 1, 73, // Opcode: BGTZL -/* 3548 */ MCD_OPC_FilterValue, 28, 229, 0, // Skip to: 3781 -/* 3552 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3555 */ MCD_OPC_FilterValue, 0, 36, 0, // Skip to: 3595 -/* 3559 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3562 */ MCD_OPC_FilterValue, 0, 176, 39, // Skip to: 13726 -/* 3566 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3569 */ MCD_OPC_FilterValue, 0, 169, 39, // Skip to: 13726 -/* 3573 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3587 -/* 3577 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3587 -/* 3583 */ MCD_OPC_Decode, 130, 8, 43, // Opcode: MADD -/* 3587 */ MCD_OPC_CheckPredicate, 12, 151, 39, // Skip to: 13726 -/* 3591 */ MCD_OPC_Decode, 145, 8, 116, // Opcode: MADD_DSP -/* 3595 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 3635 -/* 3599 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3602 */ MCD_OPC_FilterValue, 0, 136, 39, // Skip to: 13726 -/* 3606 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3609 */ MCD_OPC_FilterValue, 0, 129, 39, // Skip to: 13726 -/* 3613 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3627 -/* 3617 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3627 -/* 3623 */ MCD_OPC_Decode, 135, 8, 43, // Opcode: MADDU -/* 3627 */ MCD_OPC_CheckPredicate, 12, 111, 39, // Skip to: 13726 -/* 3631 */ MCD_OPC_Decode, 136, 8, 116, // Opcode: MADDU_DSP -/* 3635 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3653 -/* 3639 */ MCD_OPC_CheckPredicate, 9, 99, 39, // Skip to: 13726 -/* 3643 */ MCD_OPC_CheckField, 6, 5, 0, 93, 39, // Skip to: 13726 -/* 3649 */ MCD_OPC_Decode, 193, 9, 35, // Opcode: MUL -/* 3653 */ MCD_OPC_FilterValue, 4, 36, 0, // Skip to: 3693 -/* 3657 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3660 */ MCD_OPC_FilterValue, 0, 78, 39, // Skip to: 13726 -/* 3664 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3667 */ MCD_OPC_FilterValue, 0, 71, 39, // Skip to: 13726 -/* 3671 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3685 -/* 3675 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3685 -/* 3681 */ MCD_OPC_Decode, 148, 9, 43, // Opcode: MSUB -/* 3685 */ MCD_OPC_CheckPredicate, 12, 53, 39, // Skip to: 13726 -/* 3689 */ MCD_OPC_Decode, 163, 9, 116, // Opcode: MSUB_DSP -/* 3693 */ MCD_OPC_FilterValue, 5, 36, 0, // Skip to: 3733 -/* 3697 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3700 */ MCD_OPC_FilterValue, 0, 38, 39, // Skip to: 13726 -/* 3704 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3707 */ MCD_OPC_FilterValue, 0, 31, 39, // Skip to: 13726 -/* 3711 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3725 -/* 3715 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3725 -/* 3721 */ MCD_OPC_Decode, 153, 9, 43, // Opcode: MSUBU -/* 3725 */ MCD_OPC_CheckPredicate, 12, 13, 39, // Skip to: 13726 -/* 3729 */ MCD_OPC_Decode, 154, 9, 116, // Opcode: MSUBU_DSP -/* 3733 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3751 -/* 3737 */ MCD_OPC_CheckPredicate, 9, 1, 39, // Skip to: 13726 -/* 3741 */ MCD_OPC_CheckField, 6, 5, 0, 251, 38, // Skip to: 13726 -/* 3747 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: CLZ -/* 3751 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3769 -/* 3755 */ MCD_OPC_CheckPredicate, 9, 239, 38, // Skip to: 13726 -/* 3759 */ MCD_OPC_CheckField, 6, 5, 0, 233, 38, // Skip to: 13726 -/* 3765 */ MCD_OPC_Decode, 133, 3, 117, // Opcode: CLO -/* 3769 */ MCD_OPC_FilterValue, 63, 225, 38, // Skip to: 13726 -/* 3773 */ MCD_OPC_CheckPredicate, 9, 221, 38, // Skip to: 13726 -/* 3777 */ MCD_OPC_Decode, 152, 11, 64, // Opcode: SDBBP -/* 3781 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3793 -/* 3785 */ MCD_OPC_CheckPredicate, 9, 209, 38, // Skip to: 13726 -/* 3789 */ MCD_OPC_Decode, 131, 7, 77, // Opcode: JALX -/* 3793 */ MCD_OPC_FilterValue, 30, 28, 28, // Skip to: 10993 -/* 3797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3800 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 3854 -/* 3804 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3807 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3818 -/* 3811 */ MCD_OPC_CheckPredicate, 8, 183, 38, // Skip to: 13726 -/* 3815 */ MCD_OPC_Decode, 87, 118, // Opcode: ANDI_B -/* 3818 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3830 -/* 3822 */ MCD_OPC_CheckPredicate, 8, 172, 38, // Skip to: 13726 -/* 3826 */ MCD_OPC_Decode, 136, 10, 118, // Opcode: ORI_B -/* 3830 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3842 -/* 3834 */ MCD_OPC_CheckPredicate, 8, 160, 38, // Skip to: 13726 -/* 3838 */ MCD_OPC_Decode, 252, 9, 118, // Opcode: NORI_B -/* 3842 */ MCD_OPC_FilterValue, 3, 152, 38, // Skip to: 13726 -/* 3846 */ MCD_OPC_CheckPredicate, 8, 148, 38, // Skip to: 13726 -/* 3850 */ MCD_OPC_Decode, 239, 13, 118, // Opcode: XORI_B -/* 3854 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 3897 -/* 3858 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3861 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3873 -/* 3865 */ MCD_OPC_CheckPredicate, 8, 129, 38, // Skip to: 13726 -/* 3869 */ MCD_OPC_Decode, 141, 2, 119, // Opcode: BMNZI_B -/* 3873 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3885 -/* 3877 */ MCD_OPC_CheckPredicate, 8, 117, 38, // Skip to: 13726 -/* 3881 */ MCD_OPC_Decode, 143, 2, 119, // Opcode: BMZI_B -/* 3885 */ MCD_OPC_FilterValue, 2, 109, 38, // Skip to: 13726 -/* 3889 */ MCD_OPC_CheckPredicate, 8, 105, 38, // Skip to: 13726 -/* 3893 */ MCD_OPC_Decode, 174, 2, 119, // Opcode: BSELI_B -/* 3897 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 3940 -/* 3901 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 3904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3916 -/* 3908 */ MCD_OPC_CheckPredicate, 8, 86, 38, // Skip to: 13726 -/* 3912 */ MCD_OPC_Decode, 189, 11, 118, // Opcode: SHF_B -/* 3916 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3928 -/* 3920 */ MCD_OPC_CheckPredicate, 8, 74, 38, // Skip to: 13726 -/* 3924 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: SHF_H -/* 3928 */ MCD_OPC_FilterValue, 2, 66, 38, // Skip to: 13726 -/* 3932 */ MCD_OPC_CheckPredicate, 8, 62, 38, // Skip to: 13726 -/* 3936 */ MCD_OPC_Decode, 191, 11, 121, // Opcode: SHF_W -/* 3940 */ MCD_OPC_FilterValue, 6, 31, 1, // Skip to: 4231 -/* 3944 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 3947 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3958 -/* 3951 */ MCD_OPC_CheckPredicate, 8, 43, 38, // Skip to: 13726 -/* 3955 */ MCD_OPC_Decode, 59, 122, // Opcode: ADDVI_B -/* 3958 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 3969 -/* 3962 */ MCD_OPC_CheckPredicate, 8, 32, 38, // Skip to: 13726 -/* 3966 */ MCD_OPC_Decode, 61, 123, // Opcode: ADDVI_H -/* 3969 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3980 -/* 3973 */ MCD_OPC_CheckPredicate, 8, 21, 38, // Skip to: 13726 -/* 3977 */ MCD_OPC_Decode, 62, 124, // Opcode: ADDVI_W -/* 3980 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 3991 -/* 3984 */ MCD_OPC_CheckPredicate, 8, 10, 38, // Skip to: 13726 -/* 3988 */ MCD_OPC_Decode, 60, 125, // Opcode: ADDVI_D -/* 3991 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 4003 -/* 3995 */ MCD_OPC_CheckPredicate, 8, 255, 37, // Skip to: 13726 -/* 3999 */ MCD_OPC_Decode, 221, 12, 122, // Opcode: SUBVI_B -/* 4003 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 4015 -/* 4007 */ MCD_OPC_CheckPredicate, 8, 243, 37, // Skip to: 13726 -/* 4011 */ MCD_OPC_Decode, 223, 12, 123, // Opcode: SUBVI_H -/* 4015 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4027 -/* 4019 */ MCD_OPC_CheckPredicate, 8, 231, 37, // Skip to: 13726 -/* 4023 */ MCD_OPC_Decode, 224, 12, 124, // Opcode: SUBVI_W -/* 4027 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 4039 -/* 4031 */ MCD_OPC_CheckPredicate, 8, 219, 37, // Skip to: 13726 -/* 4035 */ MCD_OPC_Decode, 222, 12, 125, // Opcode: SUBVI_D -/* 4039 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4051 -/* 4043 */ MCD_OPC_CheckPredicate, 8, 207, 37, // Skip to: 13726 -/* 4047 */ MCD_OPC_Decode, 157, 8, 122, // Opcode: MAXI_S_B -/* 4051 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4063 -/* 4055 */ MCD_OPC_CheckPredicate, 8, 195, 37, // Skip to: 13726 -/* 4059 */ MCD_OPC_Decode, 159, 8, 123, // Opcode: MAXI_S_H -/* 4063 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4075 -/* 4067 */ MCD_OPC_CheckPredicate, 8, 183, 37, // Skip to: 13726 -/* 4071 */ MCD_OPC_Decode, 160, 8, 124, // Opcode: MAXI_S_W -/* 4075 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4087 -/* 4079 */ MCD_OPC_CheckPredicate, 8, 171, 37, // Skip to: 13726 -/* 4083 */ MCD_OPC_Decode, 158, 8, 125, // Opcode: MAXI_S_D -/* 4087 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4099 -/* 4091 */ MCD_OPC_CheckPredicate, 8, 159, 37, // Skip to: 13726 -/* 4095 */ MCD_OPC_Decode, 161, 8, 122, // Opcode: MAXI_U_B -/* 4099 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4111 -/* 4103 */ MCD_OPC_CheckPredicate, 8, 147, 37, // Skip to: 13726 -/* 4107 */ MCD_OPC_Decode, 163, 8, 123, // Opcode: MAXI_U_H -/* 4111 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4123 -/* 4115 */ MCD_OPC_CheckPredicate, 8, 135, 37, // Skip to: 13726 -/* 4119 */ MCD_OPC_Decode, 164, 8, 124, // Opcode: MAXI_U_W -/* 4123 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4135 -/* 4127 */ MCD_OPC_CheckPredicate, 8, 123, 37, // Skip to: 13726 -/* 4131 */ MCD_OPC_Decode, 162, 8, 125, // Opcode: MAXI_U_D -/* 4135 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4147 -/* 4139 */ MCD_OPC_CheckPredicate, 8, 111, 37, // Skip to: 13726 -/* 4143 */ MCD_OPC_Decode, 198, 8, 122, // Opcode: MINI_S_B -/* 4147 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4159 -/* 4151 */ MCD_OPC_CheckPredicate, 8, 99, 37, // Skip to: 13726 -/* 4155 */ MCD_OPC_Decode, 200, 8, 123, // Opcode: MINI_S_H -/* 4159 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4171 -/* 4163 */ MCD_OPC_CheckPredicate, 8, 87, 37, // Skip to: 13726 -/* 4167 */ MCD_OPC_Decode, 201, 8, 124, // Opcode: MINI_S_W -/* 4171 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4183 -/* 4175 */ MCD_OPC_CheckPredicate, 8, 75, 37, // Skip to: 13726 -/* 4179 */ MCD_OPC_Decode, 199, 8, 125, // Opcode: MINI_S_D -/* 4183 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4195 -/* 4187 */ MCD_OPC_CheckPredicate, 8, 63, 37, // Skip to: 13726 -/* 4191 */ MCD_OPC_Decode, 202, 8, 122, // Opcode: MINI_U_B -/* 4195 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4207 -/* 4199 */ MCD_OPC_CheckPredicate, 8, 51, 37, // Skip to: 13726 -/* 4203 */ MCD_OPC_Decode, 204, 8, 123, // Opcode: MINI_U_H -/* 4207 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4219 -/* 4211 */ MCD_OPC_CheckPredicate, 8, 39, 37, // Skip to: 13726 -/* 4215 */ MCD_OPC_Decode, 205, 8, 124, // Opcode: MINI_U_W -/* 4219 */ MCD_OPC_FilterValue, 23, 31, 37, // Skip to: 13726 -/* 4223 */ MCD_OPC_CheckPredicate, 8, 27, 37, // Skip to: 13726 -/* 4227 */ MCD_OPC_Decode, 203, 8, 125, // Opcode: MINI_U_D -/* 4231 */ MCD_OPC_FilterValue, 7, 37, 1, // Skip to: 4528 -/* 4235 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 4238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4250 -/* 4242 */ MCD_OPC_CheckPredicate, 8, 8, 37, // Skip to: 13726 -/* 4246 */ MCD_OPC_Decode, 230, 2, 122, // Opcode: CEQI_B -/* 4250 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 4262 -/* 4254 */ MCD_OPC_CheckPredicate, 8, 252, 36, // Skip to: 13726 -/* 4258 */ MCD_OPC_Decode, 232, 2, 123, // Opcode: CEQI_H -/* 4262 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4274 -/* 4266 */ MCD_OPC_CheckPredicate, 8, 240, 36, // Skip to: 13726 -/* 4270 */ MCD_OPC_Decode, 233, 2, 124, // Opcode: CEQI_W -/* 4274 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 4286 -/* 4278 */ MCD_OPC_CheckPredicate, 8, 228, 36, // Skip to: 13726 -/* 4282 */ MCD_OPC_Decode, 231, 2, 125, // Opcode: CEQI_D -/* 4286 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4298 -/* 4290 */ MCD_OPC_CheckPredicate, 8, 216, 36, // Skip to: 13726 -/* 4294 */ MCD_OPC_Decode, 136, 3, 122, // Opcode: CLTI_S_B -/* 4298 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4310 -/* 4302 */ MCD_OPC_CheckPredicate, 8, 204, 36, // Skip to: 13726 -/* 4306 */ MCD_OPC_Decode, 138, 3, 123, // Opcode: CLTI_S_H -/* 4310 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4322 -/* 4314 */ MCD_OPC_CheckPredicate, 8, 192, 36, // Skip to: 13726 -/* 4318 */ MCD_OPC_Decode, 139, 3, 124, // Opcode: CLTI_S_W -/* 4322 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4334 -/* 4326 */ MCD_OPC_CheckPredicate, 8, 180, 36, // Skip to: 13726 -/* 4330 */ MCD_OPC_Decode, 137, 3, 125, // Opcode: CLTI_S_D -/* 4334 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4346 -/* 4338 */ MCD_OPC_CheckPredicate, 8, 168, 36, // Skip to: 13726 -/* 4342 */ MCD_OPC_Decode, 140, 3, 122, // Opcode: CLTI_U_B -/* 4346 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4358 -/* 4350 */ MCD_OPC_CheckPredicate, 8, 156, 36, // Skip to: 13726 -/* 4354 */ MCD_OPC_Decode, 142, 3, 123, // Opcode: CLTI_U_H -/* 4358 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4370 -/* 4362 */ MCD_OPC_CheckPredicate, 8, 144, 36, // Skip to: 13726 -/* 4366 */ MCD_OPC_Decode, 143, 3, 124, // Opcode: CLTI_U_W -/* 4370 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4382 -/* 4374 */ MCD_OPC_CheckPredicate, 8, 132, 36, // Skip to: 13726 -/* 4378 */ MCD_OPC_Decode, 141, 3, 125, // Opcode: CLTI_U_D -/* 4382 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4394 -/* 4386 */ MCD_OPC_CheckPredicate, 8, 120, 36, // Skip to: 13726 -/* 4390 */ MCD_OPC_Decode, 245, 2, 122, // Opcode: CLEI_S_B -/* 4394 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4406 -/* 4398 */ MCD_OPC_CheckPredicate, 8, 108, 36, // Skip to: 13726 -/* 4402 */ MCD_OPC_Decode, 247, 2, 123, // Opcode: CLEI_S_H -/* 4406 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4418 -/* 4410 */ MCD_OPC_CheckPredicate, 8, 96, 36, // Skip to: 13726 -/* 4414 */ MCD_OPC_Decode, 248, 2, 124, // Opcode: CLEI_S_W -/* 4418 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4430 -/* 4422 */ MCD_OPC_CheckPredicate, 8, 84, 36, // Skip to: 13726 -/* 4426 */ MCD_OPC_Decode, 246, 2, 125, // Opcode: CLEI_S_D -/* 4430 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4442 -/* 4434 */ MCD_OPC_CheckPredicate, 8, 72, 36, // Skip to: 13726 -/* 4438 */ MCD_OPC_Decode, 249, 2, 122, // Opcode: CLEI_U_B -/* 4442 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4454 -/* 4446 */ MCD_OPC_CheckPredicate, 8, 60, 36, // Skip to: 13726 -/* 4450 */ MCD_OPC_Decode, 251, 2, 123, // Opcode: CLEI_U_H -/* 4454 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4466 -/* 4458 */ MCD_OPC_CheckPredicate, 8, 48, 36, // Skip to: 13726 -/* 4462 */ MCD_OPC_Decode, 252, 2, 124, // Opcode: CLEI_U_W -/* 4466 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 4478 -/* 4470 */ MCD_OPC_CheckPredicate, 8, 36, 36, // Skip to: 13726 -/* 4474 */ MCD_OPC_Decode, 250, 2, 125, // Opcode: CLEI_U_D -/* 4478 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 4490 -/* 4482 */ MCD_OPC_CheckPredicate, 8, 24, 36, // Skip to: 13726 -/* 4486 */ MCD_OPC_Decode, 168, 7, 126, // Opcode: LDI_B -/* 4490 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 4502 -/* 4494 */ MCD_OPC_CheckPredicate, 8, 12, 36, // Skip to: 13726 -/* 4498 */ MCD_OPC_Decode, 170, 7, 127, // Opcode: LDI_H -/* 4502 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 4515 -/* 4506 */ MCD_OPC_CheckPredicate, 8, 0, 36, // Skip to: 13726 -/* 4510 */ MCD_OPC_Decode, 171, 7, 128, 1, // Opcode: LDI_W -/* 4515 */ MCD_OPC_FilterValue, 27, 247, 35, // Skip to: 13726 -/* 4519 */ MCD_OPC_CheckPredicate, 8, 243, 35, // Skip to: 13726 -/* 4523 */ MCD_OPC_Decode, 169, 7, 129, 1, // Opcode: LDI_D -/* 4528 */ MCD_OPC_FilterValue, 9, 61, 2, // Skip to: 5105 -/* 4532 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 4535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4548 -/* 4539 */ MCD_OPC_CheckPredicate, 8, 223, 35, // Skip to: 13726 -/* 4543 */ MCD_OPC_Decode, 230, 11, 130, 1, // Opcode: SLLI_D -/* 4548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 4606 -/* 4552 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4555 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4567 -/* 4559 */ MCD_OPC_CheckPredicate, 8, 203, 35, // Skip to: 13726 -/* 4563 */ MCD_OPC_Decode, 232, 11, 124, // Opcode: SLLI_W -/* 4567 */ MCD_OPC_FilterValue, 1, 195, 35, // Skip to: 13726 -/* 4571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4574 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4587 -/* 4578 */ MCD_OPC_CheckPredicate, 8, 184, 35, // Skip to: 13726 -/* 4582 */ MCD_OPC_Decode, 231, 11, 131, 1, // Opcode: SLLI_H -/* 4587 */ MCD_OPC_FilterValue, 1, 175, 35, // Skip to: 13726 -/* 4591 */ MCD_OPC_CheckPredicate, 8, 171, 35, // Skip to: 13726 -/* 4595 */ MCD_OPC_CheckField, 19, 1, 0, 165, 35, // Skip to: 13726 -/* 4601 */ MCD_OPC_Decode, 229, 11, 132, 1, // Opcode: SLLI_B -/* 4606 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4619 -/* 4610 */ MCD_OPC_CheckPredicate, 8, 152, 35, // Skip to: 13726 -/* 4614 */ MCD_OPC_Decode, 141, 12, 130, 1, // Opcode: SRAI_D -/* 4619 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 4677 -/* 4623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4638 -/* 4630 */ MCD_OPC_CheckPredicate, 8, 132, 35, // Skip to: 13726 -/* 4634 */ MCD_OPC_Decode, 143, 12, 124, // Opcode: SRAI_W -/* 4638 */ MCD_OPC_FilterValue, 1, 124, 35, // Skip to: 13726 -/* 4642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4645 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4658 -/* 4649 */ MCD_OPC_CheckPredicate, 8, 113, 35, // Skip to: 13726 -/* 4653 */ MCD_OPC_Decode, 142, 12, 131, 1, // Opcode: SRAI_H -/* 4658 */ MCD_OPC_FilterValue, 1, 104, 35, // Skip to: 13726 -/* 4662 */ MCD_OPC_CheckPredicate, 8, 100, 35, // Skip to: 13726 -/* 4666 */ MCD_OPC_CheckField, 19, 1, 0, 94, 35, // Skip to: 13726 -/* 4672 */ MCD_OPC_Decode, 140, 12, 132, 1, // Opcode: SRAI_B -/* 4677 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 4690 -/* 4681 */ MCD_OPC_CheckPredicate, 8, 81, 35, // Skip to: 13726 -/* 4685 */ MCD_OPC_Decode, 162, 12, 130, 1, // Opcode: SRLI_D -/* 4690 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 4748 -/* 4694 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4697 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4709 -/* 4701 */ MCD_OPC_CheckPredicate, 8, 61, 35, // Skip to: 13726 -/* 4705 */ MCD_OPC_Decode, 164, 12, 124, // Opcode: SRLI_W -/* 4709 */ MCD_OPC_FilterValue, 1, 53, 35, // Skip to: 13726 -/* 4713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4716 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4729 -/* 4720 */ MCD_OPC_CheckPredicate, 8, 42, 35, // Skip to: 13726 -/* 4724 */ MCD_OPC_Decode, 163, 12, 131, 1, // Opcode: SRLI_H -/* 4729 */ MCD_OPC_FilterValue, 1, 33, 35, // Skip to: 13726 -/* 4733 */ MCD_OPC_CheckPredicate, 8, 29, 35, // Skip to: 13726 -/* 4737 */ MCD_OPC_CheckField, 19, 1, 0, 23, 35, // Skip to: 13726 -/* 4743 */ MCD_OPC_Decode, 161, 12, 132, 1, // Opcode: SRLI_B -/* 4748 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 4761 -/* 4752 */ MCD_OPC_CheckPredicate, 8, 10, 35, // Skip to: 13726 -/* 4756 */ MCD_OPC_Decode, 199, 1, 130, 1, // Opcode: BCLRI_D -/* 4761 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 4819 -/* 4765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4768 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4780 -/* 4772 */ MCD_OPC_CheckPredicate, 8, 246, 34, // Skip to: 13726 -/* 4776 */ MCD_OPC_Decode, 201, 1, 124, // Opcode: BCLRI_W -/* 4780 */ MCD_OPC_FilterValue, 1, 238, 34, // Skip to: 13726 -/* 4784 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4787 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4800 -/* 4791 */ MCD_OPC_CheckPredicate, 8, 227, 34, // Skip to: 13726 -/* 4795 */ MCD_OPC_Decode, 200, 1, 131, 1, // Opcode: BCLRI_H -/* 4800 */ MCD_OPC_FilterValue, 1, 218, 34, // Skip to: 13726 -/* 4804 */ MCD_OPC_CheckPredicate, 8, 214, 34, // Skip to: 13726 -/* 4808 */ MCD_OPC_CheckField, 19, 1, 0, 208, 34, // Skip to: 13726 -/* 4814 */ MCD_OPC_Decode, 198, 1, 132, 1, // Opcode: BCLRI_B -/* 4819 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 4832 -/* 4823 */ MCD_OPC_CheckPredicate, 8, 195, 34, // Skip to: 13726 -/* 4827 */ MCD_OPC_Decode, 182, 2, 130, 1, // Opcode: BSETI_D -/* 4832 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 4890 -/* 4836 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4839 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4851 -/* 4843 */ MCD_OPC_CheckPredicate, 8, 175, 34, // Skip to: 13726 -/* 4847 */ MCD_OPC_Decode, 184, 2, 124, // Opcode: BSETI_W -/* 4851 */ MCD_OPC_FilterValue, 1, 167, 34, // Skip to: 13726 -/* 4855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4858 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4871 -/* 4862 */ MCD_OPC_CheckPredicate, 8, 156, 34, // Skip to: 13726 -/* 4866 */ MCD_OPC_Decode, 183, 2, 131, 1, // Opcode: BSETI_H -/* 4871 */ MCD_OPC_FilterValue, 1, 147, 34, // Skip to: 13726 -/* 4875 */ MCD_OPC_CheckPredicate, 8, 143, 34, // Skip to: 13726 -/* 4879 */ MCD_OPC_CheckField, 19, 1, 0, 137, 34, // Skip to: 13726 -/* 4885 */ MCD_OPC_Decode, 181, 2, 132, 1, // Opcode: BSETI_B -/* 4890 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 4903 -/* 4894 */ MCD_OPC_CheckPredicate, 8, 124, 34, // Skip to: 13726 -/* 4898 */ MCD_OPC_Decode, 149, 2, 130, 1, // Opcode: BNEGI_D -/* 4903 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 4961 -/* 4907 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4910 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4922 -/* 4914 */ MCD_OPC_CheckPredicate, 8, 104, 34, // Skip to: 13726 -/* 4918 */ MCD_OPC_Decode, 151, 2, 124, // Opcode: BNEGI_W -/* 4922 */ MCD_OPC_FilterValue, 1, 96, 34, // Skip to: 13726 -/* 4926 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 4929 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4942 -/* 4933 */ MCD_OPC_CheckPredicate, 8, 85, 34, // Skip to: 13726 -/* 4937 */ MCD_OPC_Decode, 150, 2, 131, 1, // Opcode: BNEGI_H -/* 4942 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 13726 -/* 4946 */ MCD_OPC_CheckPredicate, 8, 72, 34, // Skip to: 13726 -/* 4950 */ MCD_OPC_CheckField, 19, 1, 0, 66, 34, // Skip to: 13726 -/* 4956 */ MCD_OPC_Decode, 148, 2, 132, 1, // Opcode: BNEGI_B -/* 4961 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 4974 -/* 4965 */ MCD_OPC_CheckPredicate, 8, 53, 34, // Skip to: 13726 -/* 4969 */ MCD_OPC_Decode, 234, 1, 133, 1, // Opcode: BINSLI_D -/* 4974 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 5033 -/* 4978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 4981 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4994 -/* 4985 */ MCD_OPC_CheckPredicate, 8, 33, 34, // Skip to: 13726 -/* 4989 */ MCD_OPC_Decode, 236, 1, 134, 1, // Opcode: BINSLI_W -/* 4994 */ MCD_OPC_FilterValue, 1, 24, 34, // Skip to: 13726 -/* 4998 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5001 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5014 -/* 5005 */ MCD_OPC_CheckPredicate, 8, 13, 34, // Skip to: 13726 -/* 5009 */ MCD_OPC_Decode, 235, 1, 135, 1, // Opcode: BINSLI_H -/* 5014 */ MCD_OPC_FilterValue, 1, 4, 34, // Skip to: 13726 -/* 5018 */ MCD_OPC_CheckPredicate, 8, 0, 34, // Skip to: 13726 -/* 5022 */ MCD_OPC_CheckField, 19, 1, 0, 250, 33, // Skip to: 13726 -/* 5028 */ MCD_OPC_Decode, 233, 1, 136, 1, // Opcode: BINSLI_B -/* 5033 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5046 -/* 5037 */ MCD_OPC_CheckPredicate, 8, 237, 33, // Skip to: 13726 -/* 5041 */ MCD_OPC_Decode, 242, 1, 133, 1, // Opcode: BINSRI_D -/* 5046 */ MCD_OPC_FilterValue, 15, 228, 33, // Skip to: 13726 -/* 5050 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5053 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5066 -/* 5057 */ MCD_OPC_CheckPredicate, 8, 217, 33, // Skip to: 13726 -/* 5061 */ MCD_OPC_Decode, 244, 1, 134, 1, // Opcode: BINSRI_W -/* 5066 */ MCD_OPC_FilterValue, 1, 208, 33, // Skip to: 13726 -/* 5070 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5073 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5086 -/* 5077 */ MCD_OPC_CheckPredicate, 8, 197, 33, // Skip to: 13726 -/* 5081 */ MCD_OPC_Decode, 243, 1, 135, 1, // Opcode: BINSRI_H -/* 5086 */ MCD_OPC_FilterValue, 1, 188, 33, // Skip to: 13726 -/* 5090 */ MCD_OPC_CheckPredicate, 8, 184, 33, // Skip to: 13726 -/* 5094 */ MCD_OPC_CheckField, 19, 1, 0, 178, 33, // Skip to: 13726 -/* 5100 */ MCD_OPC_Decode, 241, 1, 136, 1, // Opcode: BINSRI_B -/* 5105 */ MCD_OPC_FilterValue, 10, 31, 1, // Skip to: 5396 -/* 5109 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 5112 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5125 -/* 5116 */ MCD_OPC_CheckPredicate, 8, 158, 33, // Skip to: 13726 -/* 5120 */ MCD_OPC_Decode, 135, 11, 130, 1, // Opcode: SAT_S_D -/* 5125 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 5183 -/* 5129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5144 -/* 5136 */ MCD_OPC_CheckPredicate, 8, 138, 33, // Skip to: 13726 -/* 5140 */ MCD_OPC_Decode, 137, 11, 124, // Opcode: SAT_S_W -/* 5144 */ MCD_OPC_FilterValue, 1, 130, 33, // Skip to: 13726 -/* 5148 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5164 -/* 5155 */ MCD_OPC_CheckPredicate, 8, 119, 33, // Skip to: 13726 -/* 5159 */ MCD_OPC_Decode, 136, 11, 131, 1, // Opcode: SAT_S_H -/* 5164 */ MCD_OPC_FilterValue, 1, 110, 33, // Skip to: 13726 -/* 5168 */ MCD_OPC_CheckPredicate, 8, 106, 33, // Skip to: 13726 -/* 5172 */ MCD_OPC_CheckField, 19, 1, 0, 100, 33, // Skip to: 13726 -/* 5178 */ MCD_OPC_Decode, 134, 11, 132, 1, // Opcode: SAT_S_B -/* 5183 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5196 -/* 5187 */ MCD_OPC_CheckPredicate, 8, 87, 33, // Skip to: 13726 -/* 5191 */ MCD_OPC_Decode, 139, 11, 130, 1, // Opcode: SAT_U_D -/* 5196 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 5254 -/* 5200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5215 -/* 5207 */ MCD_OPC_CheckPredicate, 8, 67, 33, // Skip to: 13726 -/* 5211 */ MCD_OPC_Decode, 141, 11, 124, // Opcode: SAT_U_W -/* 5215 */ MCD_OPC_FilterValue, 1, 59, 33, // Skip to: 13726 -/* 5219 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5222 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5235 -/* 5226 */ MCD_OPC_CheckPredicate, 8, 48, 33, // Skip to: 13726 -/* 5230 */ MCD_OPC_Decode, 140, 11, 131, 1, // Opcode: SAT_U_H -/* 5235 */ MCD_OPC_FilterValue, 1, 39, 33, // Skip to: 13726 -/* 5239 */ MCD_OPC_CheckPredicate, 8, 35, 33, // Skip to: 13726 -/* 5243 */ MCD_OPC_CheckField, 19, 1, 0, 29, 33, // Skip to: 13726 -/* 5249 */ MCD_OPC_Decode, 138, 11, 132, 1, // Opcode: SAT_U_B -/* 5254 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5267 -/* 5258 */ MCD_OPC_CheckPredicate, 8, 16, 33, // Skip to: 13726 -/* 5262 */ MCD_OPC_Decode, 145, 12, 130, 1, // Opcode: SRARI_D -/* 5267 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 5325 -/* 5271 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5274 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5286 -/* 5278 */ MCD_OPC_CheckPredicate, 8, 252, 32, // Skip to: 13726 -/* 5282 */ MCD_OPC_Decode, 147, 12, 124, // Opcode: SRARI_W -/* 5286 */ MCD_OPC_FilterValue, 1, 244, 32, // Skip to: 13726 -/* 5290 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5293 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5306 -/* 5297 */ MCD_OPC_CheckPredicate, 8, 233, 32, // Skip to: 13726 -/* 5301 */ MCD_OPC_Decode, 146, 12, 131, 1, // Opcode: SRARI_H -/* 5306 */ MCD_OPC_FilterValue, 1, 224, 32, // Skip to: 13726 -/* 5310 */ MCD_OPC_CheckPredicate, 8, 220, 32, // Skip to: 13726 -/* 5314 */ MCD_OPC_CheckField, 19, 1, 0, 214, 32, // Skip to: 13726 -/* 5320 */ MCD_OPC_Decode, 144, 12, 132, 1, // Opcode: SRARI_B -/* 5325 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5338 -/* 5329 */ MCD_OPC_CheckPredicate, 8, 201, 32, // Skip to: 13726 -/* 5333 */ MCD_OPC_Decode, 166, 12, 130, 1, // Opcode: SRLRI_D -/* 5338 */ MCD_OPC_FilterValue, 7, 192, 32, // Skip to: 13726 -/* 5342 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5345 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5357 -/* 5349 */ MCD_OPC_CheckPredicate, 8, 181, 32, // Skip to: 13726 -/* 5353 */ MCD_OPC_Decode, 168, 12, 124, // Opcode: SRLRI_W -/* 5357 */ MCD_OPC_FilterValue, 1, 173, 32, // Skip to: 13726 -/* 5361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 5364 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5377 -/* 5368 */ MCD_OPC_CheckPredicate, 8, 162, 32, // Skip to: 13726 -/* 5372 */ MCD_OPC_Decode, 167, 12, 131, 1, // Opcode: SRLRI_H -/* 5377 */ MCD_OPC_FilterValue, 1, 153, 32, // Skip to: 13726 -/* 5381 */ MCD_OPC_CheckPredicate, 8, 149, 32, // Skip to: 13726 -/* 5385 */ MCD_OPC_CheckField, 19, 1, 0, 143, 32, // Skip to: 13726 -/* 5391 */ MCD_OPC_Decode, 165, 12, 132, 1, // Opcode: SRLRI_B -/* 5396 */ MCD_OPC_FilterValue, 13, 163, 1, // Skip to: 5819 -/* 5400 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 5403 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5416 -/* 5407 */ MCD_OPC_CheckPredicate, 8, 123, 32, // Skip to: 13726 -/* 5411 */ MCD_OPC_Decode, 235, 11, 137, 1, // Opcode: SLL_B -/* 5416 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5429 -/* 5420 */ MCD_OPC_CheckPredicate, 8, 110, 32, // Skip to: 13726 -/* 5424 */ MCD_OPC_Decode, 237, 11, 138, 1, // Opcode: SLL_H -/* 5429 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5442 -/* 5433 */ MCD_OPC_CheckPredicate, 8, 97, 32, // Skip to: 13726 -/* 5437 */ MCD_OPC_Decode, 239, 11, 139, 1, // Opcode: SLL_W -/* 5442 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5455 -/* 5446 */ MCD_OPC_CheckPredicate, 8, 84, 32, // Skip to: 13726 -/* 5450 */ MCD_OPC_Decode, 236, 11, 140, 1, // Opcode: SLL_D -/* 5455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5468 -/* 5459 */ MCD_OPC_CheckPredicate, 8, 71, 32, // Skip to: 13726 -/* 5463 */ MCD_OPC_Decode, 154, 12, 137, 1, // Opcode: SRA_B -/* 5468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5481 -/* 5472 */ MCD_OPC_CheckPredicate, 8, 58, 32, // Skip to: 13726 -/* 5476 */ MCD_OPC_Decode, 156, 12, 138, 1, // Opcode: SRA_H -/* 5481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5494 -/* 5485 */ MCD_OPC_CheckPredicate, 8, 45, 32, // Skip to: 13726 -/* 5489 */ MCD_OPC_Decode, 158, 12, 139, 1, // Opcode: SRA_W -/* 5494 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5507 -/* 5498 */ MCD_OPC_CheckPredicate, 8, 32, 32, // Skip to: 13726 -/* 5502 */ MCD_OPC_Decode, 155, 12, 140, 1, // Opcode: SRA_D -/* 5507 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5520 -/* 5511 */ MCD_OPC_CheckPredicate, 8, 19, 32, // Skip to: 13726 -/* 5515 */ MCD_OPC_Decode, 175, 12, 137, 1, // Opcode: SRL_B -/* 5520 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5533 -/* 5524 */ MCD_OPC_CheckPredicate, 8, 6, 32, // Skip to: 13726 -/* 5528 */ MCD_OPC_Decode, 177, 12, 138, 1, // Opcode: SRL_H -/* 5533 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5546 -/* 5537 */ MCD_OPC_CheckPredicate, 8, 249, 31, // Skip to: 13726 -/* 5541 */ MCD_OPC_Decode, 179, 12, 139, 1, // Opcode: SRL_W -/* 5546 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5559 -/* 5550 */ MCD_OPC_CheckPredicate, 8, 236, 31, // Skip to: 13726 -/* 5554 */ MCD_OPC_Decode, 176, 12, 140, 1, // Opcode: SRL_D -/* 5559 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5572 -/* 5563 */ MCD_OPC_CheckPredicate, 8, 223, 31, // Skip to: 13726 -/* 5567 */ MCD_OPC_Decode, 202, 1, 137, 1, // Opcode: BCLR_B -/* 5572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5585 -/* 5576 */ MCD_OPC_CheckPredicate, 8, 210, 31, // Skip to: 13726 -/* 5580 */ MCD_OPC_Decode, 204, 1, 138, 1, // Opcode: BCLR_H -/* 5585 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5598 -/* 5589 */ MCD_OPC_CheckPredicate, 8, 197, 31, // Skip to: 13726 -/* 5593 */ MCD_OPC_Decode, 205, 1, 139, 1, // Opcode: BCLR_W -/* 5598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5611 -/* 5602 */ MCD_OPC_CheckPredicate, 8, 184, 31, // Skip to: 13726 -/* 5606 */ MCD_OPC_Decode, 203, 1, 140, 1, // Opcode: BCLR_D -/* 5611 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 5624 -/* 5615 */ MCD_OPC_CheckPredicate, 8, 171, 31, // Skip to: 13726 -/* 5619 */ MCD_OPC_Decode, 185, 2, 137, 1, // Opcode: BSET_B -/* 5624 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 5637 -/* 5628 */ MCD_OPC_CheckPredicate, 8, 158, 31, // Skip to: 13726 -/* 5632 */ MCD_OPC_Decode, 187, 2, 138, 1, // Opcode: BSET_H -/* 5637 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 5650 -/* 5641 */ MCD_OPC_CheckPredicate, 8, 145, 31, // Skip to: 13726 -/* 5645 */ MCD_OPC_Decode, 188, 2, 139, 1, // Opcode: BSET_W -/* 5650 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 5663 -/* 5654 */ MCD_OPC_CheckPredicate, 8, 132, 31, // Skip to: 13726 -/* 5658 */ MCD_OPC_Decode, 186, 2, 140, 1, // Opcode: BSET_D -/* 5663 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 5676 -/* 5667 */ MCD_OPC_CheckPredicate, 8, 119, 31, // Skip to: 13726 -/* 5671 */ MCD_OPC_Decode, 152, 2, 137, 1, // Opcode: BNEG_B -/* 5676 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 5689 -/* 5680 */ MCD_OPC_CheckPredicate, 8, 106, 31, // Skip to: 13726 -/* 5684 */ MCD_OPC_Decode, 154, 2, 138, 1, // Opcode: BNEG_H -/* 5689 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 5702 -/* 5693 */ MCD_OPC_CheckPredicate, 8, 93, 31, // Skip to: 13726 -/* 5697 */ MCD_OPC_Decode, 155, 2, 139, 1, // Opcode: BNEG_W -/* 5702 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 5715 -/* 5706 */ MCD_OPC_CheckPredicate, 8, 80, 31, // Skip to: 13726 -/* 5710 */ MCD_OPC_Decode, 153, 2, 140, 1, // Opcode: BNEG_D -/* 5715 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 5728 -/* 5719 */ MCD_OPC_CheckPredicate, 8, 67, 31, // Skip to: 13726 -/* 5723 */ MCD_OPC_Decode, 237, 1, 141, 1, // Opcode: BINSL_B -/* 5728 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 5741 -/* 5732 */ MCD_OPC_CheckPredicate, 8, 54, 31, // Skip to: 13726 -/* 5736 */ MCD_OPC_Decode, 239, 1, 142, 1, // Opcode: BINSL_H -/* 5741 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 5754 -/* 5745 */ MCD_OPC_CheckPredicate, 8, 41, 31, // Skip to: 13726 -/* 5749 */ MCD_OPC_Decode, 240, 1, 143, 1, // Opcode: BINSL_W -/* 5754 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 5767 -/* 5758 */ MCD_OPC_CheckPredicate, 8, 28, 31, // Skip to: 13726 -/* 5762 */ MCD_OPC_Decode, 238, 1, 144, 1, // Opcode: BINSL_D -/* 5767 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 5780 -/* 5771 */ MCD_OPC_CheckPredicate, 8, 15, 31, // Skip to: 13726 -/* 5775 */ MCD_OPC_Decode, 245, 1, 141, 1, // Opcode: BINSR_B -/* 5780 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 5793 -/* 5784 */ MCD_OPC_CheckPredicate, 8, 2, 31, // Skip to: 13726 -/* 5788 */ MCD_OPC_Decode, 247, 1, 142, 1, // Opcode: BINSR_H -/* 5793 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 5806 -/* 5797 */ MCD_OPC_CheckPredicate, 8, 245, 30, // Skip to: 13726 -/* 5801 */ MCD_OPC_Decode, 248, 1, 143, 1, // Opcode: BINSR_W -/* 5806 */ MCD_OPC_FilterValue, 31, 236, 30, // Skip to: 13726 -/* 5810 */ MCD_OPC_CheckPredicate, 8, 232, 30, // Skip to: 13726 -/* 5814 */ MCD_OPC_Decode, 246, 1, 144, 1, // Opcode: BINSR_D -/* 5819 */ MCD_OPC_FilterValue, 14, 159, 1, // Skip to: 6238 -/* 5823 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 5826 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5838 -/* 5830 */ MCD_OPC_CheckPredicate, 8, 212, 30, // Skip to: 13726 -/* 5834 */ MCD_OPC_Decode, 63, 137, 1, // Opcode: ADDV_B -/* 5838 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5850 -/* 5842 */ MCD_OPC_CheckPredicate, 8, 200, 30, // Skip to: 13726 -/* 5846 */ MCD_OPC_Decode, 65, 138, 1, // Opcode: ADDV_H -/* 5850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5862 -/* 5854 */ MCD_OPC_CheckPredicate, 8, 188, 30, // Skip to: 13726 -/* 5858 */ MCD_OPC_Decode, 66, 139, 1, // Opcode: ADDV_W -/* 5862 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 5874 -/* 5866 */ MCD_OPC_CheckPredicate, 8, 176, 30, // Skip to: 13726 -/* 5870 */ MCD_OPC_Decode, 64, 140, 1, // Opcode: ADDV_D -/* 5874 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5887 -/* 5878 */ MCD_OPC_CheckPredicate, 8, 164, 30, // Skip to: 13726 -/* 5882 */ MCD_OPC_Decode, 225, 12, 137, 1, // Opcode: SUBV_B -/* 5887 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5900 -/* 5891 */ MCD_OPC_CheckPredicate, 8, 151, 30, // Skip to: 13726 -/* 5895 */ MCD_OPC_Decode, 227, 12, 138, 1, // Opcode: SUBV_H -/* 5900 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5913 -/* 5904 */ MCD_OPC_CheckPredicate, 8, 138, 30, // Skip to: 13726 -/* 5908 */ MCD_OPC_Decode, 228, 12, 139, 1, // Opcode: SUBV_W -/* 5913 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5926 -/* 5917 */ MCD_OPC_CheckPredicate, 8, 125, 30, // Skip to: 13726 -/* 5921 */ MCD_OPC_Decode, 226, 12, 140, 1, // Opcode: SUBV_D -/* 5926 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5939 -/* 5930 */ MCD_OPC_CheckPredicate, 8, 112, 30, // Skip to: 13726 -/* 5934 */ MCD_OPC_Decode, 171, 8, 137, 1, // Opcode: MAX_S_B -/* 5939 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5952 -/* 5943 */ MCD_OPC_CheckPredicate, 8, 99, 30, // Skip to: 13726 -/* 5947 */ MCD_OPC_Decode, 173, 8, 138, 1, // Opcode: MAX_S_H -/* 5952 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5965 -/* 5956 */ MCD_OPC_CheckPredicate, 8, 86, 30, // Skip to: 13726 -/* 5960 */ MCD_OPC_Decode, 174, 8, 139, 1, // Opcode: MAX_S_W -/* 5965 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5978 -/* 5969 */ MCD_OPC_CheckPredicate, 8, 73, 30, // Skip to: 13726 -/* 5973 */ MCD_OPC_Decode, 172, 8, 140, 1, // Opcode: MAX_S_D -/* 5978 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5991 -/* 5982 */ MCD_OPC_CheckPredicate, 8, 60, 30, // Skip to: 13726 -/* 5986 */ MCD_OPC_Decode, 175, 8, 137, 1, // Opcode: MAX_U_B -/* 5991 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6004 -/* 5995 */ MCD_OPC_CheckPredicate, 8, 47, 30, // Skip to: 13726 -/* 5999 */ MCD_OPC_Decode, 177, 8, 138, 1, // Opcode: MAX_U_H -/* 6004 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6017 -/* 6008 */ MCD_OPC_CheckPredicate, 8, 34, 30, // Skip to: 13726 -/* 6012 */ MCD_OPC_Decode, 178, 8, 139, 1, // Opcode: MAX_U_W -/* 6017 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6030 -/* 6021 */ MCD_OPC_CheckPredicate, 8, 21, 30, // Skip to: 13726 -/* 6025 */ MCD_OPC_Decode, 176, 8, 140, 1, // Opcode: MAX_U_D -/* 6030 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6043 -/* 6034 */ MCD_OPC_CheckPredicate, 8, 8, 30, // Skip to: 13726 -/* 6038 */ MCD_OPC_Decode, 212, 8, 137, 1, // Opcode: MIN_S_B -/* 6043 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6056 -/* 6047 */ MCD_OPC_CheckPredicate, 8, 251, 29, // Skip to: 13726 -/* 6051 */ MCD_OPC_Decode, 214, 8, 138, 1, // Opcode: MIN_S_H -/* 6056 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6069 -/* 6060 */ MCD_OPC_CheckPredicate, 8, 238, 29, // Skip to: 13726 -/* 6064 */ MCD_OPC_Decode, 215, 8, 139, 1, // Opcode: MIN_S_W -/* 6069 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6082 -/* 6073 */ MCD_OPC_CheckPredicate, 8, 225, 29, // Skip to: 13726 -/* 6077 */ MCD_OPC_Decode, 213, 8, 140, 1, // Opcode: MIN_S_D -/* 6082 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6095 -/* 6086 */ MCD_OPC_CheckPredicate, 8, 212, 29, // Skip to: 13726 -/* 6090 */ MCD_OPC_Decode, 216, 8, 137, 1, // Opcode: MIN_U_B -/* 6095 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6108 -/* 6099 */ MCD_OPC_CheckPredicate, 8, 199, 29, // Skip to: 13726 -/* 6103 */ MCD_OPC_Decode, 218, 8, 138, 1, // Opcode: MIN_U_H -/* 6108 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6121 -/* 6112 */ MCD_OPC_CheckPredicate, 8, 186, 29, // Skip to: 13726 -/* 6116 */ MCD_OPC_Decode, 219, 8, 139, 1, // Opcode: MIN_U_W -/* 6121 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6134 -/* 6125 */ MCD_OPC_CheckPredicate, 8, 173, 29, // Skip to: 13726 -/* 6129 */ MCD_OPC_Decode, 217, 8, 140, 1, // Opcode: MIN_U_D -/* 6134 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6147 -/* 6138 */ MCD_OPC_CheckPredicate, 8, 160, 29, // Skip to: 13726 -/* 6142 */ MCD_OPC_Decode, 165, 8, 137, 1, // Opcode: MAX_A_B -/* 6147 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6160 -/* 6151 */ MCD_OPC_CheckPredicate, 8, 147, 29, // Skip to: 13726 -/* 6155 */ MCD_OPC_Decode, 167, 8, 138, 1, // Opcode: MAX_A_H -/* 6160 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6173 -/* 6164 */ MCD_OPC_CheckPredicate, 8, 134, 29, // Skip to: 13726 -/* 6168 */ MCD_OPC_Decode, 168, 8, 139, 1, // Opcode: MAX_A_W -/* 6173 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6186 -/* 6177 */ MCD_OPC_CheckPredicate, 8, 121, 29, // Skip to: 13726 -/* 6181 */ MCD_OPC_Decode, 166, 8, 140, 1, // Opcode: MAX_A_D -/* 6186 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6199 -/* 6190 */ MCD_OPC_CheckPredicate, 8, 108, 29, // Skip to: 13726 -/* 6194 */ MCD_OPC_Decode, 206, 8, 137, 1, // Opcode: MIN_A_B -/* 6199 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6212 -/* 6203 */ MCD_OPC_CheckPredicate, 8, 95, 29, // Skip to: 13726 -/* 6207 */ MCD_OPC_Decode, 208, 8, 138, 1, // Opcode: MIN_A_H -/* 6212 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6225 -/* 6216 */ MCD_OPC_CheckPredicate, 8, 82, 29, // Skip to: 13726 -/* 6220 */ MCD_OPC_Decode, 209, 8, 139, 1, // Opcode: MIN_A_W -/* 6225 */ MCD_OPC_FilterValue, 31, 73, 29, // Skip to: 13726 -/* 6229 */ MCD_OPC_CheckPredicate, 8, 69, 29, // Skip to: 13726 -/* 6233 */ MCD_OPC_Decode, 207, 8, 140, 1, // Opcode: MIN_A_D -/* 6238 */ MCD_OPC_FilterValue, 15, 7, 1, // Skip to: 6505 -/* 6242 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6245 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6258 -/* 6249 */ MCD_OPC_CheckPredicate, 8, 49, 29, // Skip to: 13726 -/* 6253 */ MCD_OPC_Decode, 234, 2, 137, 1, // Opcode: CEQ_B -/* 6258 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6271 -/* 6262 */ MCD_OPC_CheckPredicate, 8, 36, 29, // Skip to: 13726 -/* 6266 */ MCD_OPC_Decode, 236, 2, 138, 1, // Opcode: CEQ_H -/* 6271 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6284 -/* 6275 */ MCD_OPC_CheckPredicate, 8, 23, 29, // Skip to: 13726 -/* 6279 */ MCD_OPC_Decode, 237, 2, 139, 1, // Opcode: CEQ_W -/* 6284 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6297 -/* 6288 */ MCD_OPC_CheckPredicate, 8, 10, 29, // Skip to: 13726 -/* 6292 */ MCD_OPC_Decode, 235, 2, 140, 1, // Opcode: CEQ_D -/* 6297 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6310 -/* 6301 */ MCD_OPC_CheckPredicate, 8, 253, 28, // Skip to: 13726 -/* 6305 */ MCD_OPC_Decode, 144, 3, 137, 1, // Opcode: CLT_S_B -/* 6310 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6323 -/* 6314 */ MCD_OPC_CheckPredicate, 8, 240, 28, // Skip to: 13726 -/* 6318 */ MCD_OPC_Decode, 146, 3, 138, 1, // Opcode: CLT_S_H -/* 6323 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6336 -/* 6327 */ MCD_OPC_CheckPredicate, 8, 227, 28, // Skip to: 13726 -/* 6331 */ MCD_OPC_Decode, 147, 3, 139, 1, // Opcode: CLT_S_W -/* 6336 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6349 -/* 6340 */ MCD_OPC_CheckPredicate, 8, 214, 28, // Skip to: 13726 -/* 6344 */ MCD_OPC_Decode, 145, 3, 140, 1, // Opcode: CLT_S_D -/* 6349 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6362 -/* 6353 */ MCD_OPC_CheckPredicate, 8, 201, 28, // Skip to: 13726 -/* 6357 */ MCD_OPC_Decode, 148, 3, 137, 1, // Opcode: CLT_U_B -/* 6362 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6375 -/* 6366 */ MCD_OPC_CheckPredicate, 8, 188, 28, // Skip to: 13726 -/* 6370 */ MCD_OPC_Decode, 150, 3, 138, 1, // Opcode: CLT_U_H -/* 6375 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6388 -/* 6379 */ MCD_OPC_CheckPredicate, 8, 175, 28, // Skip to: 13726 -/* 6383 */ MCD_OPC_Decode, 151, 3, 139, 1, // Opcode: CLT_U_W -/* 6388 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6401 -/* 6392 */ MCD_OPC_CheckPredicate, 8, 162, 28, // Skip to: 13726 -/* 6396 */ MCD_OPC_Decode, 149, 3, 140, 1, // Opcode: CLT_U_D -/* 6401 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6414 -/* 6405 */ MCD_OPC_CheckPredicate, 8, 149, 28, // Skip to: 13726 -/* 6409 */ MCD_OPC_Decode, 253, 2, 137, 1, // Opcode: CLE_S_B -/* 6414 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6427 -/* 6418 */ MCD_OPC_CheckPredicate, 8, 136, 28, // Skip to: 13726 -/* 6422 */ MCD_OPC_Decode, 255, 2, 138, 1, // Opcode: CLE_S_H -/* 6427 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6440 -/* 6431 */ MCD_OPC_CheckPredicate, 8, 123, 28, // Skip to: 13726 -/* 6435 */ MCD_OPC_Decode, 128, 3, 139, 1, // Opcode: CLE_S_W -/* 6440 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6453 -/* 6444 */ MCD_OPC_CheckPredicate, 8, 110, 28, // Skip to: 13726 -/* 6448 */ MCD_OPC_Decode, 254, 2, 140, 1, // Opcode: CLE_S_D -/* 6453 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6466 -/* 6457 */ MCD_OPC_CheckPredicate, 8, 97, 28, // Skip to: 13726 -/* 6461 */ MCD_OPC_Decode, 129, 3, 137, 1, // Opcode: CLE_U_B -/* 6466 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6479 -/* 6470 */ MCD_OPC_CheckPredicate, 8, 84, 28, // Skip to: 13726 -/* 6474 */ MCD_OPC_Decode, 131, 3, 138, 1, // Opcode: CLE_U_H -/* 6479 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6492 -/* 6483 */ MCD_OPC_CheckPredicate, 8, 71, 28, // Skip to: 13726 -/* 6487 */ MCD_OPC_Decode, 132, 3, 139, 1, // Opcode: CLE_U_W -/* 6492 */ MCD_OPC_FilterValue, 23, 62, 28, // Skip to: 13726 -/* 6496 */ MCD_OPC_CheckPredicate, 8, 58, 28, // Skip to: 13726 -/* 6500 */ MCD_OPC_Decode, 130, 3, 140, 1, // Opcode: CLE_U_D -/* 6505 */ MCD_OPC_FilterValue, 16, 147, 1, // Skip to: 6912 -/* 6509 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6512 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6524 -/* 6516 */ MCD_OPC_CheckPredicate, 8, 38, 28, // Skip to: 13726 -/* 6520 */ MCD_OPC_Decode, 68, 137, 1, // Opcode: ADD_A_B -/* 6524 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6536 -/* 6528 */ MCD_OPC_CheckPredicate, 8, 26, 28, // Skip to: 13726 -/* 6532 */ MCD_OPC_Decode, 70, 138, 1, // Opcode: ADD_A_H -/* 6536 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6548 -/* 6540 */ MCD_OPC_CheckPredicate, 8, 14, 28, // Skip to: 13726 -/* 6544 */ MCD_OPC_Decode, 71, 139, 1, // Opcode: ADD_A_W -/* 6548 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6560 -/* 6552 */ MCD_OPC_CheckPredicate, 8, 2, 28, // Skip to: 13726 -/* 6556 */ MCD_OPC_Decode, 69, 140, 1, // Opcode: ADD_A_D -/* 6560 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6572 -/* 6564 */ MCD_OPC_CheckPredicate, 8, 246, 27, // Skip to: 13726 -/* 6568 */ MCD_OPC_Decode, 40, 137, 1, // Opcode: ADDS_A_B -/* 6572 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6584 -/* 6576 */ MCD_OPC_CheckPredicate, 8, 234, 27, // Skip to: 13726 -/* 6580 */ MCD_OPC_Decode, 42, 138, 1, // Opcode: ADDS_A_H -/* 6584 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6596 -/* 6588 */ MCD_OPC_CheckPredicate, 8, 222, 27, // Skip to: 13726 -/* 6592 */ MCD_OPC_Decode, 43, 139, 1, // Opcode: ADDS_A_W -/* 6596 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6608 -/* 6600 */ MCD_OPC_CheckPredicate, 8, 210, 27, // Skip to: 13726 -/* 6604 */ MCD_OPC_Decode, 41, 140, 1, // Opcode: ADDS_A_D -/* 6608 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6620 -/* 6612 */ MCD_OPC_CheckPredicate, 8, 198, 27, // Skip to: 13726 -/* 6616 */ MCD_OPC_Decode, 44, 137, 1, // Opcode: ADDS_S_B -/* 6620 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6632 -/* 6624 */ MCD_OPC_CheckPredicate, 8, 186, 27, // Skip to: 13726 -/* 6628 */ MCD_OPC_Decode, 46, 138, 1, // Opcode: ADDS_S_H -/* 6632 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6644 -/* 6636 */ MCD_OPC_CheckPredicate, 8, 174, 27, // Skip to: 13726 -/* 6640 */ MCD_OPC_Decode, 47, 139, 1, // Opcode: ADDS_S_W -/* 6644 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6656 -/* 6648 */ MCD_OPC_CheckPredicate, 8, 162, 27, // Skip to: 13726 -/* 6652 */ MCD_OPC_Decode, 45, 140, 1, // Opcode: ADDS_S_D -/* 6656 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6668 -/* 6660 */ MCD_OPC_CheckPredicate, 8, 150, 27, // Skip to: 13726 -/* 6664 */ MCD_OPC_Decode, 48, 137, 1, // Opcode: ADDS_U_B -/* 6668 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6680 -/* 6672 */ MCD_OPC_CheckPredicate, 8, 138, 27, // Skip to: 13726 -/* 6676 */ MCD_OPC_Decode, 50, 138, 1, // Opcode: ADDS_U_H -/* 6680 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6692 -/* 6684 */ MCD_OPC_CheckPredicate, 8, 126, 27, // Skip to: 13726 -/* 6688 */ MCD_OPC_Decode, 51, 139, 1, // Opcode: ADDS_U_W -/* 6692 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6704 -/* 6696 */ MCD_OPC_CheckPredicate, 8, 114, 27, // Skip to: 13726 -/* 6700 */ MCD_OPC_Decode, 49, 140, 1, // Opcode: ADDS_U_D -/* 6704 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6717 -/* 6708 */ MCD_OPC_CheckPredicate, 8, 102, 27, // Skip to: 13726 -/* 6712 */ MCD_OPC_Decode, 147, 1, 137, 1, // Opcode: AVE_S_B -/* 6717 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6730 -/* 6721 */ MCD_OPC_CheckPredicate, 8, 89, 27, // Skip to: 13726 -/* 6725 */ MCD_OPC_Decode, 149, 1, 138, 1, // Opcode: AVE_S_H -/* 6730 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6743 -/* 6734 */ MCD_OPC_CheckPredicate, 8, 76, 27, // Skip to: 13726 -/* 6738 */ MCD_OPC_Decode, 150, 1, 139, 1, // Opcode: AVE_S_W -/* 6743 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6756 -/* 6747 */ MCD_OPC_CheckPredicate, 8, 63, 27, // Skip to: 13726 -/* 6751 */ MCD_OPC_Decode, 148, 1, 140, 1, // Opcode: AVE_S_D -/* 6756 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6769 -/* 6760 */ MCD_OPC_CheckPredicate, 8, 50, 27, // Skip to: 13726 -/* 6764 */ MCD_OPC_Decode, 151, 1, 137, 1, // Opcode: AVE_U_B -/* 6769 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6782 -/* 6773 */ MCD_OPC_CheckPredicate, 8, 37, 27, // Skip to: 13726 -/* 6777 */ MCD_OPC_Decode, 153, 1, 138, 1, // Opcode: AVE_U_H -/* 6782 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6795 -/* 6786 */ MCD_OPC_CheckPredicate, 8, 24, 27, // Skip to: 13726 -/* 6790 */ MCD_OPC_Decode, 154, 1, 139, 1, // Opcode: AVE_U_W -/* 6795 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6808 -/* 6799 */ MCD_OPC_CheckPredicate, 8, 11, 27, // Skip to: 13726 -/* 6803 */ MCD_OPC_Decode, 152, 1, 140, 1, // Opcode: AVE_U_D -/* 6808 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6821 -/* 6812 */ MCD_OPC_CheckPredicate, 8, 254, 26, // Skip to: 13726 -/* 6816 */ MCD_OPC_Decode, 139, 1, 137, 1, // Opcode: AVER_S_B -/* 6821 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6834 -/* 6825 */ MCD_OPC_CheckPredicate, 8, 241, 26, // Skip to: 13726 -/* 6829 */ MCD_OPC_Decode, 141, 1, 138, 1, // Opcode: AVER_S_H -/* 6834 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6847 -/* 6838 */ MCD_OPC_CheckPredicate, 8, 228, 26, // Skip to: 13726 -/* 6842 */ MCD_OPC_Decode, 142, 1, 139, 1, // Opcode: AVER_S_W -/* 6847 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6860 -/* 6851 */ MCD_OPC_CheckPredicate, 8, 215, 26, // Skip to: 13726 -/* 6855 */ MCD_OPC_Decode, 140, 1, 140, 1, // Opcode: AVER_S_D -/* 6860 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6873 -/* 6864 */ MCD_OPC_CheckPredicate, 8, 202, 26, // Skip to: 13726 -/* 6868 */ MCD_OPC_Decode, 143, 1, 137, 1, // Opcode: AVER_U_B -/* 6873 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6886 -/* 6877 */ MCD_OPC_CheckPredicate, 8, 189, 26, // Skip to: 13726 -/* 6881 */ MCD_OPC_Decode, 145, 1, 138, 1, // Opcode: AVER_U_H -/* 6886 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6899 -/* 6890 */ MCD_OPC_CheckPredicate, 8, 176, 26, // Skip to: 13726 -/* 6894 */ MCD_OPC_Decode, 146, 1, 139, 1, // Opcode: AVER_U_W -/* 6899 */ MCD_OPC_FilterValue, 31, 167, 26, // Skip to: 13726 -/* 6903 */ MCD_OPC_CheckPredicate, 8, 163, 26, // Skip to: 13726 -/* 6907 */ MCD_OPC_Decode, 144, 1, 140, 1, // Opcode: AVER_U_D -/* 6912 */ MCD_OPC_FilterValue, 17, 51, 1, // Skip to: 7223 -/* 6916 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 6919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6932 -/* 6923 */ MCD_OPC_CheckPredicate, 8, 143, 26, // Skip to: 13726 -/* 6927 */ MCD_OPC_Decode, 206, 12, 137, 1, // Opcode: SUBS_S_B -/* 6932 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6945 -/* 6936 */ MCD_OPC_CheckPredicate, 8, 130, 26, // Skip to: 13726 -/* 6940 */ MCD_OPC_Decode, 208, 12, 138, 1, // Opcode: SUBS_S_H -/* 6945 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6958 -/* 6949 */ MCD_OPC_CheckPredicate, 8, 117, 26, // Skip to: 13726 -/* 6953 */ MCD_OPC_Decode, 209, 12, 139, 1, // Opcode: SUBS_S_W -/* 6958 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6971 -/* 6962 */ MCD_OPC_CheckPredicate, 8, 104, 26, // Skip to: 13726 -/* 6966 */ MCD_OPC_Decode, 207, 12, 140, 1, // Opcode: SUBS_S_D -/* 6971 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 6984 -/* 6975 */ MCD_OPC_CheckPredicate, 8, 91, 26, // Skip to: 13726 -/* 6979 */ MCD_OPC_Decode, 210, 12, 137, 1, // Opcode: SUBS_U_B -/* 6984 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 6997 -/* 6988 */ MCD_OPC_CheckPredicate, 8, 78, 26, // Skip to: 13726 -/* 6992 */ MCD_OPC_Decode, 212, 12, 138, 1, // Opcode: SUBS_U_H -/* 6997 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7010 -/* 7001 */ MCD_OPC_CheckPredicate, 8, 65, 26, // Skip to: 13726 -/* 7005 */ MCD_OPC_Decode, 213, 12, 139, 1, // Opcode: SUBS_U_W -/* 7010 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7023 -/* 7014 */ MCD_OPC_CheckPredicate, 8, 52, 26, // Skip to: 13726 -/* 7018 */ MCD_OPC_Decode, 211, 12, 140, 1, // Opcode: SUBS_U_D -/* 7023 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7036 -/* 7027 */ MCD_OPC_CheckPredicate, 8, 39, 26, // Skip to: 13726 -/* 7031 */ MCD_OPC_Decode, 198, 12, 137, 1, // Opcode: SUBSUS_U_B -/* 7036 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7049 -/* 7040 */ MCD_OPC_CheckPredicate, 8, 26, 26, // Skip to: 13726 -/* 7044 */ MCD_OPC_Decode, 200, 12, 138, 1, // Opcode: SUBSUS_U_H -/* 7049 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7062 -/* 7053 */ MCD_OPC_CheckPredicate, 8, 13, 26, // Skip to: 13726 -/* 7057 */ MCD_OPC_Decode, 201, 12, 139, 1, // Opcode: SUBSUS_U_W -/* 7062 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7075 -/* 7066 */ MCD_OPC_CheckPredicate, 8, 0, 26, // Skip to: 13726 -/* 7070 */ MCD_OPC_Decode, 199, 12, 140, 1, // Opcode: SUBSUS_U_D -/* 7075 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7088 -/* 7079 */ MCD_OPC_CheckPredicate, 8, 243, 25, // Skip to: 13726 -/* 7083 */ MCD_OPC_Decode, 202, 12, 137, 1, // Opcode: SUBSUU_S_B -/* 7088 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7101 -/* 7092 */ MCD_OPC_CheckPredicate, 8, 230, 25, // Skip to: 13726 -/* 7096 */ MCD_OPC_Decode, 204, 12, 138, 1, // Opcode: SUBSUU_S_H -/* 7101 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7114 -/* 7105 */ MCD_OPC_CheckPredicate, 8, 217, 25, // Skip to: 13726 -/* 7109 */ MCD_OPC_Decode, 205, 12, 139, 1, // Opcode: SUBSUU_S_W -/* 7114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7127 -/* 7118 */ MCD_OPC_CheckPredicate, 8, 204, 25, // Skip to: 13726 -/* 7122 */ MCD_OPC_Decode, 203, 12, 140, 1, // Opcode: SUBSUU_S_D -/* 7127 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7139 -/* 7131 */ MCD_OPC_CheckPredicate, 8, 191, 25, // Skip to: 13726 -/* 7135 */ MCD_OPC_Decode, 97, 137, 1, // Opcode: ASUB_S_B -/* 7139 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7151 -/* 7143 */ MCD_OPC_CheckPredicate, 8, 179, 25, // Skip to: 13726 -/* 7147 */ MCD_OPC_Decode, 99, 138, 1, // Opcode: ASUB_S_H -/* 7151 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7163 -/* 7155 */ MCD_OPC_CheckPredicate, 8, 167, 25, // Skip to: 13726 -/* 7159 */ MCD_OPC_Decode, 100, 139, 1, // Opcode: ASUB_S_W -/* 7163 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7175 -/* 7167 */ MCD_OPC_CheckPredicate, 8, 155, 25, // Skip to: 13726 -/* 7171 */ MCD_OPC_Decode, 98, 140, 1, // Opcode: ASUB_S_D -/* 7175 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7187 -/* 7179 */ MCD_OPC_CheckPredicate, 8, 143, 25, // Skip to: 13726 -/* 7183 */ MCD_OPC_Decode, 101, 137, 1, // Opcode: ASUB_U_B -/* 7187 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7199 -/* 7191 */ MCD_OPC_CheckPredicate, 8, 131, 25, // Skip to: 13726 -/* 7195 */ MCD_OPC_Decode, 103, 138, 1, // Opcode: ASUB_U_H -/* 7199 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7211 -/* 7203 */ MCD_OPC_CheckPredicate, 8, 119, 25, // Skip to: 13726 -/* 7207 */ MCD_OPC_Decode, 104, 139, 1, // Opcode: ASUB_U_W -/* 7211 */ MCD_OPC_FilterValue, 23, 111, 25, // Skip to: 13726 -/* 7215 */ MCD_OPC_CheckPredicate, 8, 107, 25, // Skip to: 13726 -/* 7219 */ MCD_OPC_Decode, 102, 140, 1, // Opcode: ASUB_U_D -/* 7223 */ MCD_OPC_FilterValue, 18, 111, 1, // Skip to: 7594 -/* 7227 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7243 -/* 7234 */ MCD_OPC_CheckPredicate, 8, 88, 25, // Skip to: 13726 -/* 7238 */ MCD_OPC_Decode, 213, 9, 137, 1, // Opcode: MULV_B -/* 7243 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7256 -/* 7247 */ MCD_OPC_CheckPredicate, 8, 75, 25, // Skip to: 13726 -/* 7251 */ MCD_OPC_Decode, 215, 9, 138, 1, // Opcode: MULV_H -/* 7256 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7269 -/* 7260 */ MCD_OPC_CheckPredicate, 8, 62, 25, // Skip to: 13726 -/* 7264 */ MCD_OPC_Decode, 216, 9, 139, 1, // Opcode: MULV_W -/* 7269 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7282 -/* 7273 */ MCD_OPC_CheckPredicate, 8, 49, 25, // Skip to: 13726 -/* 7277 */ MCD_OPC_Decode, 214, 9, 140, 1, // Opcode: MULV_D -/* 7282 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7295 -/* 7286 */ MCD_OPC_CheckPredicate, 8, 36, 25, // Skip to: 13726 -/* 7290 */ MCD_OPC_Decode, 138, 8, 141, 1, // Opcode: MADDV_B -/* 7295 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7308 -/* 7299 */ MCD_OPC_CheckPredicate, 8, 23, 25, // Skip to: 13726 -/* 7303 */ MCD_OPC_Decode, 140, 8, 142, 1, // Opcode: MADDV_H -/* 7308 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7321 -/* 7312 */ MCD_OPC_CheckPredicate, 8, 10, 25, // Skip to: 13726 -/* 7316 */ MCD_OPC_Decode, 141, 8, 143, 1, // Opcode: MADDV_W -/* 7321 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7334 -/* 7325 */ MCD_OPC_CheckPredicate, 8, 253, 24, // Skip to: 13726 -/* 7329 */ MCD_OPC_Decode, 139, 8, 144, 1, // Opcode: MADDV_D -/* 7334 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7347 -/* 7338 */ MCD_OPC_CheckPredicate, 8, 240, 24, // Skip to: 13726 -/* 7342 */ MCD_OPC_Decode, 156, 9, 141, 1, // Opcode: MSUBV_B -/* 7347 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7360 -/* 7351 */ MCD_OPC_CheckPredicate, 8, 227, 24, // Skip to: 13726 -/* 7355 */ MCD_OPC_Decode, 158, 9, 142, 1, // Opcode: MSUBV_H -/* 7360 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7373 -/* 7364 */ MCD_OPC_CheckPredicate, 8, 214, 24, // Skip to: 13726 -/* 7368 */ MCD_OPC_Decode, 159, 9, 143, 1, // Opcode: MSUBV_W -/* 7373 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7386 -/* 7377 */ MCD_OPC_CheckPredicate, 8, 201, 24, // Skip to: 13726 -/* 7381 */ MCD_OPC_Decode, 157, 9, 144, 1, // Opcode: MSUBV_D -/* 7386 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 7399 -/* 7390 */ MCD_OPC_CheckPredicate, 8, 188, 24, // Skip to: 13726 -/* 7394 */ MCD_OPC_Decode, 185, 4, 137, 1, // Opcode: DIV_S_B -/* 7399 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7412 -/* 7403 */ MCD_OPC_CheckPredicate, 8, 175, 24, // Skip to: 13726 -/* 7407 */ MCD_OPC_Decode, 187, 4, 138, 1, // Opcode: DIV_S_H -/* 7412 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7425 -/* 7416 */ MCD_OPC_CheckPredicate, 8, 162, 24, // Skip to: 13726 -/* 7420 */ MCD_OPC_Decode, 188, 4, 139, 1, // Opcode: DIV_S_W -/* 7425 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7438 -/* 7429 */ MCD_OPC_CheckPredicate, 8, 149, 24, // Skip to: 13726 -/* 7433 */ MCD_OPC_Decode, 186, 4, 140, 1, // Opcode: DIV_S_D -/* 7438 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 7451 -/* 7442 */ MCD_OPC_CheckPredicate, 8, 136, 24, // Skip to: 13726 -/* 7446 */ MCD_OPC_Decode, 189, 4, 137, 1, // Opcode: DIV_U_B -/* 7451 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7464 -/* 7455 */ MCD_OPC_CheckPredicate, 8, 123, 24, // Skip to: 13726 -/* 7459 */ MCD_OPC_Decode, 191, 4, 138, 1, // Opcode: DIV_U_H -/* 7464 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7477 -/* 7468 */ MCD_OPC_CheckPredicate, 8, 110, 24, // Skip to: 13726 -/* 7472 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: DIV_U_W -/* 7477 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 7490 -/* 7481 */ MCD_OPC_CheckPredicate, 8, 97, 24, // Skip to: 13726 -/* 7485 */ MCD_OPC_Decode, 190, 4, 140, 1, // Opcode: DIV_U_D -/* 7490 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 7503 -/* 7494 */ MCD_OPC_CheckPredicate, 8, 84, 24, // Skip to: 13726 -/* 7498 */ MCD_OPC_Decode, 225, 8, 137, 1, // Opcode: MOD_S_B -/* 7503 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 7516 -/* 7507 */ MCD_OPC_CheckPredicate, 8, 71, 24, // Skip to: 13726 -/* 7511 */ MCD_OPC_Decode, 227, 8, 138, 1, // Opcode: MOD_S_H -/* 7516 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 7529 -/* 7520 */ MCD_OPC_CheckPredicate, 8, 58, 24, // Skip to: 13726 -/* 7524 */ MCD_OPC_Decode, 228, 8, 139, 1, // Opcode: MOD_S_W -/* 7529 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 7542 -/* 7533 */ MCD_OPC_CheckPredicate, 8, 45, 24, // Skip to: 13726 -/* 7537 */ MCD_OPC_Decode, 226, 8, 140, 1, // Opcode: MOD_S_D -/* 7542 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 7555 -/* 7546 */ MCD_OPC_CheckPredicate, 8, 32, 24, // Skip to: 13726 -/* 7550 */ MCD_OPC_Decode, 229, 8, 137, 1, // Opcode: MOD_U_B -/* 7555 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 7568 -/* 7559 */ MCD_OPC_CheckPredicate, 8, 19, 24, // Skip to: 13726 -/* 7563 */ MCD_OPC_Decode, 231, 8, 138, 1, // Opcode: MOD_U_H -/* 7568 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 7581 -/* 7572 */ MCD_OPC_CheckPredicate, 8, 6, 24, // Skip to: 13726 -/* 7576 */ MCD_OPC_Decode, 232, 8, 139, 1, // Opcode: MOD_U_W -/* 7581 */ MCD_OPC_FilterValue, 31, 253, 23, // Skip to: 13726 -/* 7585 */ MCD_OPC_CheckPredicate, 8, 249, 23, // Skip to: 13726 -/* 7589 */ MCD_OPC_Decode, 230, 8, 140, 1, // Opcode: MOD_U_D -/* 7594 */ MCD_OPC_FilterValue, 19, 237, 0, // Skip to: 7835 -/* 7598 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7601 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7614 -/* 7605 */ MCD_OPC_CheckPredicate, 8, 229, 23, // Skip to: 13726 -/* 7609 */ MCD_OPC_Decode, 212, 4, 145, 1, // Opcode: DOTP_S_H -/* 7614 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7627 -/* 7618 */ MCD_OPC_CheckPredicate, 8, 216, 23, // Skip to: 13726 -/* 7622 */ MCD_OPC_Decode, 213, 4, 146, 1, // Opcode: DOTP_S_W -/* 7627 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7640 -/* 7631 */ MCD_OPC_CheckPredicate, 8, 203, 23, // Skip to: 13726 -/* 7635 */ MCD_OPC_Decode, 211, 4, 147, 1, // Opcode: DOTP_S_D -/* 7640 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7653 -/* 7644 */ MCD_OPC_CheckPredicate, 8, 190, 23, // Skip to: 13726 -/* 7648 */ MCD_OPC_Decode, 215, 4, 145, 1, // Opcode: DOTP_U_H -/* 7653 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7666 -/* 7657 */ MCD_OPC_CheckPredicate, 8, 177, 23, // Skip to: 13726 -/* 7661 */ MCD_OPC_Decode, 216, 4, 146, 1, // Opcode: DOTP_U_W -/* 7666 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7679 -/* 7670 */ MCD_OPC_CheckPredicate, 8, 164, 23, // Skip to: 13726 -/* 7674 */ MCD_OPC_Decode, 214, 4, 147, 1, // Opcode: DOTP_U_D -/* 7679 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7692 -/* 7683 */ MCD_OPC_CheckPredicate, 8, 151, 23, // Skip to: 13726 -/* 7687 */ MCD_OPC_Decode, 218, 4, 148, 1, // Opcode: DPADD_S_H -/* 7692 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7705 -/* 7696 */ MCD_OPC_CheckPredicate, 8, 138, 23, // Skip to: 13726 -/* 7700 */ MCD_OPC_Decode, 219, 4, 149, 1, // Opcode: DPADD_S_W -/* 7705 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7718 -/* 7709 */ MCD_OPC_CheckPredicate, 8, 125, 23, // Skip to: 13726 -/* 7713 */ MCD_OPC_Decode, 217, 4, 150, 1, // Opcode: DPADD_S_D -/* 7718 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7731 -/* 7722 */ MCD_OPC_CheckPredicate, 8, 112, 23, // Skip to: 13726 -/* 7726 */ MCD_OPC_Decode, 221, 4, 148, 1, // Opcode: DPADD_U_H -/* 7731 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7744 -/* 7735 */ MCD_OPC_CheckPredicate, 8, 99, 23, // Skip to: 13726 -/* 7739 */ MCD_OPC_Decode, 222, 4, 149, 1, // Opcode: DPADD_U_W -/* 7744 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7757 -/* 7748 */ MCD_OPC_CheckPredicate, 8, 86, 23, // Skip to: 13726 -/* 7752 */ MCD_OPC_Decode, 220, 4, 150, 1, // Opcode: DPADD_U_D -/* 7757 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7770 -/* 7761 */ MCD_OPC_CheckPredicate, 8, 73, 23, // Skip to: 13726 -/* 7765 */ MCD_OPC_Decode, 237, 4, 148, 1, // Opcode: DPSUB_S_H -/* 7770 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7783 -/* 7774 */ MCD_OPC_CheckPredicate, 8, 60, 23, // Skip to: 13726 -/* 7778 */ MCD_OPC_Decode, 238, 4, 149, 1, // Opcode: DPSUB_S_W -/* 7783 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7796 -/* 7787 */ MCD_OPC_CheckPredicate, 8, 47, 23, // Skip to: 13726 -/* 7791 */ MCD_OPC_Decode, 236, 4, 150, 1, // Opcode: DPSUB_S_D -/* 7796 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7809 -/* 7800 */ MCD_OPC_CheckPredicate, 8, 34, 23, // Skip to: 13726 -/* 7804 */ MCD_OPC_Decode, 240, 4, 148, 1, // Opcode: DPSUB_U_H -/* 7809 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7822 -/* 7813 */ MCD_OPC_CheckPredicate, 8, 21, 23, // Skip to: 13726 -/* 7817 */ MCD_OPC_Decode, 241, 4, 149, 1, // Opcode: DPSUB_U_W -/* 7822 */ MCD_OPC_FilterValue, 23, 12, 23, // Skip to: 13726 -/* 7826 */ MCD_OPC_CheckPredicate, 8, 8, 23, // Skip to: 13726 -/* 7830 */ MCD_OPC_Decode, 239, 4, 150, 1, // Opcode: DPSUB_U_D -/* 7835 */ MCD_OPC_FilterValue, 20, 163, 1, // Skip to: 8258 -/* 7839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 7842 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7855 -/* 7846 */ MCD_OPC_CheckPredicate, 8, 244, 22, // Skip to: 13726 -/* 7850 */ MCD_OPC_Decode, 221, 11, 151, 1, // Opcode: SLD_B -/* 7855 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7868 -/* 7859 */ MCD_OPC_CheckPredicate, 8, 231, 22, // Skip to: 13726 -/* 7863 */ MCD_OPC_Decode, 223, 11, 152, 1, // Opcode: SLD_H -/* 7868 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7881 -/* 7872 */ MCD_OPC_CheckPredicate, 8, 218, 22, // Skip to: 13726 -/* 7876 */ MCD_OPC_Decode, 224, 11, 153, 1, // Opcode: SLD_W -/* 7881 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7894 -/* 7885 */ MCD_OPC_CheckPredicate, 8, 205, 22, // Skip to: 13726 -/* 7889 */ MCD_OPC_Decode, 222, 11, 154, 1, // Opcode: SLD_D -/* 7894 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7907 -/* 7898 */ MCD_OPC_CheckPredicate, 8, 192, 22, // Skip to: 13726 -/* 7902 */ MCD_OPC_Decode, 135, 12, 155, 1, // Opcode: SPLAT_B -/* 7907 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7920 -/* 7911 */ MCD_OPC_CheckPredicate, 8, 179, 22, // Skip to: 13726 -/* 7915 */ MCD_OPC_Decode, 137, 12, 156, 1, // Opcode: SPLAT_H -/* 7920 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7933 -/* 7924 */ MCD_OPC_CheckPredicate, 8, 166, 22, // Skip to: 13726 -/* 7928 */ MCD_OPC_Decode, 138, 12, 157, 1, // Opcode: SPLAT_W -/* 7933 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7946 -/* 7937 */ MCD_OPC_CheckPredicate, 8, 153, 22, // Skip to: 13726 -/* 7941 */ MCD_OPC_Decode, 136, 12, 158, 1, // Opcode: SPLAT_D -/* 7946 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7959 -/* 7950 */ MCD_OPC_CheckPredicate, 8, 140, 22, // Skip to: 13726 -/* 7954 */ MCD_OPC_Decode, 149, 10, 137, 1, // Opcode: PCKEV_B -/* 7959 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7972 -/* 7963 */ MCD_OPC_CheckPredicate, 8, 127, 22, // Skip to: 13726 -/* 7967 */ MCD_OPC_Decode, 151, 10, 138, 1, // Opcode: PCKEV_H -/* 7972 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7985 -/* 7976 */ MCD_OPC_CheckPredicate, 8, 114, 22, // Skip to: 13726 -/* 7980 */ MCD_OPC_Decode, 152, 10, 139, 1, // Opcode: PCKEV_W -/* 7985 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7998 -/* 7989 */ MCD_OPC_CheckPredicate, 8, 101, 22, // Skip to: 13726 -/* 7993 */ MCD_OPC_Decode, 150, 10, 140, 1, // Opcode: PCKEV_D -/* 7998 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8011 -/* 8002 */ MCD_OPC_CheckPredicate, 8, 88, 22, // Skip to: 13726 -/* 8006 */ MCD_OPC_Decode, 153, 10, 137, 1, // Opcode: PCKOD_B -/* 8011 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 8024 -/* 8015 */ MCD_OPC_CheckPredicate, 8, 75, 22, // Skip to: 13726 -/* 8019 */ MCD_OPC_Decode, 155, 10, 138, 1, // Opcode: PCKOD_H -/* 8024 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 8037 -/* 8028 */ MCD_OPC_CheckPredicate, 8, 62, 22, // Skip to: 13726 -/* 8032 */ MCD_OPC_Decode, 156, 10, 139, 1, // Opcode: PCKOD_W -/* 8037 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 8050 -/* 8041 */ MCD_OPC_CheckPredicate, 8, 49, 22, // Skip to: 13726 -/* 8045 */ MCD_OPC_Decode, 154, 10, 140, 1, // Opcode: PCKOD_D -/* 8050 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8063 -/* 8054 */ MCD_OPC_CheckPredicate, 8, 36, 22, // Skip to: 13726 -/* 8058 */ MCD_OPC_Decode, 216, 6, 137, 1, // Opcode: ILVL_B -/* 8063 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8076 -/* 8067 */ MCD_OPC_CheckPredicate, 8, 23, 22, // Skip to: 13726 -/* 8071 */ MCD_OPC_Decode, 218, 6, 138, 1, // Opcode: ILVL_H -/* 8076 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8089 -/* 8080 */ MCD_OPC_CheckPredicate, 8, 10, 22, // Skip to: 13726 -/* 8084 */ MCD_OPC_Decode, 219, 6, 139, 1, // Opcode: ILVL_W -/* 8089 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8102 -/* 8093 */ MCD_OPC_CheckPredicate, 8, 253, 21, // Skip to: 13726 -/* 8097 */ MCD_OPC_Decode, 217, 6, 140, 1, // Opcode: ILVL_D -/* 8102 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 8115 -/* 8106 */ MCD_OPC_CheckPredicate, 8, 240, 21, // Skip to: 13726 -/* 8110 */ MCD_OPC_Decode, 224, 6, 137, 1, // Opcode: ILVR_B -/* 8115 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8128 -/* 8119 */ MCD_OPC_CheckPredicate, 8, 227, 21, // Skip to: 13726 -/* 8123 */ MCD_OPC_Decode, 226, 6, 138, 1, // Opcode: ILVR_H -/* 8128 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8141 -/* 8132 */ MCD_OPC_CheckPredicate, 8, 214, 21, // Skip to: 13726 -/* 8136 */ MCD_OPC_Decode, 227, 6, 139, 1, // Opcode: ILVR_W -/* 8141 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8154 -/* 8145 */ MCD_OPC_CheckPredicate, 8, 201, 21, // Skip to: 13726 -/* 8149 */ MCD_OPC_Decode, 225, 6, 140, 1, // Opcode: ILVR_D -/* 8154 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 8167 -/* 8158 */ MCD_OPC_CheckPredicate, 8, 188, 21, // Skip to: 13726 -/* 8162 */ MCD_OPC_Decode, 212, 6, 137, 1, // Opcode: ILVEV_B -/* 8167 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8180 -/* 8171 */ MCD_OPC_CheckPredicate, 8, 175, 21, // Skip to: 13726 -/* 8175 */ MCD_OPC_Decode, 214, 6, 138, 1, // Opcode: ILVEV_H -/* 8180 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8193 -/* 8184 */ MCD_OPC_CheckPredicate, 8, 162, 21, // Skip to: 13726 -/* 8188 */ MCD_OPC_Decode, 215, 6, 139, 1, // Opcode: ILVEV_W -/* 8193 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8206 -/* 8197 */ MCD_OPC_CheckPredicate, 8, 149, 21, // Skip to: 13726 -/* 8201 */ MCD_OPC_Decode, 213, 6, 140, 1, // Opcode: ILVEV_D -/* 8206 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 8219 -/* 8210 */ MCD_OPC_CheckPredicate, 8, 136, 21, // Skip to: 13726 -/* 8214 */ MCD_OPC_Decode, 220, 6, 137, 1, // Opcode: ILVOD_B -/* 8219 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8232 -/* 8223 */ MCD_OPC_CheckPredicate, 8, 123, 21, // Skip to: 13726 -/* 8227 */ MCD_OPC_Decode, 222, 6, 138, 1, // Opcode: ILVOD_H -/* 8232 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8245 -/* 8236 */ MCD_OPC_CheckPredicate, 8, 110, 21, // Skip to: 13726 -/* 8240 */ MCD_OPC_Decode, 223, 6, 139, 1, // Opcode: ILVOD_W -/* 8245 */ MCD_OPC_FilterValue, 31, 101, 21, // Skip to: 13726 -/* 8249 */ MCD_OPC_CheckPredicate, 8, 97, 21, // Skip to: 13726 -/* 8253 */ MCD_OPC_Decode, 221, 6, 140, 1, // Opcode: ILVOD_D -/* 8258 */ MCD_OPC_FilterValue, 21, 59, 1, // Skip to: 8577 -/* 8262 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 8265 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8278 -/* 8269 */ MCD_OPC_CheckPredicate, 8, 77, 21, // Skip to: 13726 -/* 8273 */ MCD_OPC_Decode, 227, 13, 141, 1, // Opcode: VSHF_B -/* 8278 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8291 -/* 8282 */ MCD_OPC_CheckPredicate, 8, 64, 21, // Skip to: 13726 -/* 8286 */ MCD_OPC_Decode, 229, 13, 142, 1, // Opcode: VSHF_H -/* 8291 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8304 -/* 8295 */ MCD_OPC_CheckPredicate, 8, 51, 21, // Skip to: 13726 -/* 8299 */ MCD_OPC_Decode, 230, 13, 143, 1, // Opcode: VSHF_W -/* 8304 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8317 -/* 8308 */ MCD_OPC_CheckPredicate, 8, 38, 21, // Skip to: 13726 -/* 8312 */ MCD_OPC_Decode, 228, 13, 144, 1, // Opcode: VSHF_D -/* 8317 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8330 -/* 8321 */ MCD_OPC_CheckPredicate, 8, 25, 21, // Skip to: 13726 -/* 8325 */ MCD_OPC_Decode, 148, 12, 137, 1, // Opcode: SRAR_B -/* 8330 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 8343 -/* 8334 */ MCD_OPC_CheckPredicate, 8, 12, 21, // Skip to: 13726 -/* 8338 */ MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: SRAR_H -/* 8343 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 8356 -/* 8347 */ MCD_OPC_CheckPredicate, 8, 255, 20, // Skip to: 13726 -/* 8351 */ MCD_OPC_Decode, 151, 12, 139, 1, // Opcode: SRAR_W -/* 8356 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 8369 -/* 8360 */ MCD_OPC_CheckPredicate, 8, 242, 20, // Skip to: 13726 -/* 8364 */ MCD_OPC_Decode, 149, 12, 140, 1, // Opcode: SRAR_D -/* 8369 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8382 -/* 8373 */ MCD_OPC_CheckPredicate, 8, 229, 20, // Skip to: 13726 -/* 8377 */ MCD_OPC_Decode, 169, 12, 137, 1, // Opcode: SRLR_B -/* 8382 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 8395 -/* 8386 */ MCD_OPC_CheckPredicate, 8, 216, 20, // Skip to: 13726 -/* 8390 */ MCD_OPC_Decode, 171, 12, 138, 1, // Opcode: SRLR_H -/* 8395 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 8408 -/* 8399 */ MCD_OPC_CheckPredicate, 8, 203, 20, // Skip to: 13726 -/* 8403 */ MCD_OPC_Decode, 172, 12, 139, 1, // Opcode: SRLR_W -/* 8408 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 8421 -/* 8412 */ MCD_OPC_CheckPredicate, 8, 190, 20, // Skip to: 13726 -/* 8416 */ MCD_OPC_Decode, 170, 12, 140, 1, // Opcode: SRLR_D -/* 8421 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8434 -/* 8425 */ MCD_OPC_CheckPredicate, 8, 177, 20, // Skip to: 13726 -/* 8429 */ MCD_OPC_Decode, 201, 6, 145, 1, // Opcode: HADD_S_H -/* 8434 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8447 -/* 8438 */ MCD_OPC_CheckPredicate, 8, 164, 20, // Skip to: 13726 -/* 8442 */ MCD_OPC_Decode, 202, 6, 146, 1, // Opcode: HADD_S_W -/* 8447 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8460 -/* 8451 */ MCD_OPC_CheckPredicate, 8, 151, 20, // Skip to: 13726 -/* 8455 */ MCD_OPC_Decode, 200, 6, 147, 1, // Opcode: HADD_S_D -/* 8460 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8473 -/* 8464 */ MCD_OPC_CheckPredicate, 8, 138, 20, // Skip to: 13726 -/* 8468 */ MCD_OPC_Decode, 204, 6, 145, 1, // Opcode: HADD_U_H -/* 8473 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8486 -/* 8477 */ MCD_OPC_CheckPredicate, 8, 125, 20, // Skip to: 13726 -/* 8481 */ MCD_OPC_Decode, 205, 6, 146, 1, // Opcode: HADD_U_W -/* 8486 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8499 -/* 8490 */ MCD_OPC_CheckPredicate, 8, 112, 20, // Skip to: 13726 -/* 8494 */ MCD_OPC_Decode, 203, 6, 147, 1, // Opcode: HADD_U_D -/* 8499 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8512 -/* 8503 */ MCD_OPC_CheckPredicate, 8, 99, 20, // Skip to: 13726 -/* 8507 */ MCD_OPC_Decode, 207, 6, 145, 1, // Opcode: HSUB_S_H -/* 8512 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8525 -/* 8516 */ MCD_OPC_CheckPredicate, 8, 86, 20, // Skip to: 13726 -/* 8520 */ MCD_OPC_Decode, 208, 6, 146, 1, // Opcode: HSUB_S_W -/* 8525 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8538 -/* 8529 */ MCD_OPC_CheckPredicate, 8, 73, 20, // Skip to: 13726 -/* 8533 */ MCD_OPC_Decode, 206, 6, 147, 1, // Opcode: HSUB_S_D -/* 8538 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8551 -/* 8542 */ MCD_OPC_CheckPredicate, 8, 60, 20, // Skip to: 13726 -/* 8546 */ MCD_OPC_Decode, 210, 6, 145, 1, // Opcode: HSUB_U_H -/* 8551 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8564 -/* 8555 */ MCD_OPC_CheckPredicate, 8, 47, 20, // Skip to: 13726 -/* 8559 */ MCD_OPC_Decode, 211, 6, 146, 1, // Opcode: HSUB_U_W -/* 8564 */ MCD_OPC_FilterValue, 31, 38, 20, // Skip to: 13726 -/* 8568 */ MCD_OPC_CheckPredicate, 8, 34, 20, // Skip to: 13726 -/* 8572 */ MCD_OPC_Decode, 209, 6, 147, 1, // Opcode: HSUB_U_D -/* 8577 */ MCD_OPC_FilterValue, 25, 230, 1, // Skip to: 9067 -/* 8581 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... -/* 8584 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8597 -/* 8588 */ MCD_OPC_CheckPredicate, 8, 14, 20, // Skip to: 13726 -/* 8592 */ MCD_OPC_Decode, 217, 11, 159, 1, // Opcode: SLDI_B -/* 8597 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8616 -/* 8601 */ MCD_OPC_CheckPredicate, 8, 1, 20, // Skip to: 13726 -/* 8605 */ MCD_OPC_CheckField, 19, 1, 0, 251, 19, // Skip to: 13726 -/* 8611 */ MCD_OPC_Decode, 219, 11, 160, 1, // Opcode: SLDI_H -/* 8616 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 8674 -/* 8620 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8623 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8636 -/* 8627 */ MCD_OPC_CheckPredicate, 8, 231, 19, // Skip to: 13726 -/* 8631 */ MCD_OPC_Decode, 220, 11, 161, 1, // Opcode: SLDI_W -/* 8636 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8655 -/* 8640 */ MCD_OPC_CheckPredicate, 8, 218, 19, // Skip to: 13726 -/* 8644 */ MCD_OPC_CheckField, 17, 1, 0, 212, 19, // Skip to: 13726 -/* 8650 */ MCD_OPC_Decode, 218, 11, 162, 1, // Opcode: SLDI_D -/* 8655 */ MCD_OPC_FilterValue, 3, 203, 19, // Skip to: 13726 -/* 8659 */ MCD_OPC_CheckPredicate, 8, 199, 19, // Skip to: 13726 -/* 8663 */ MCD_OPC_CheckField, 16, 2, 2, 193, 19, // Skip to: 13726 -/* 8669 */ MCD_OPC_Decode, 212, 3, 163, 1, // Opcode: CTCMSA -/* 8674 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8687 -/* 8678 */ MCD_OPC_CheckPredicate, 8, 180, 19, // Skip to: 13726 -/* 8682 */ MCD_OPC_Decode, 131, 12, 164, 1, // Opcode: SPLATI_B -/* 8687 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 8706 -/* 8691 */ MCD_OPC_CheckPredicate, 8, 167, 19, // Skip to: 13726 -/* 8695 */ MCD_OPC_CheckField, 19, 1, 0, 161, 19, // Skip to: 13726 -/* 8701 */ MCD_OPC_Decode, 133, 12, 165, 1, // Opcode: SPLATI_H -/* 8706 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 8764 -/* 8710 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8713 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8726 -/* 8717 */ MCD_OPC_CheckPredicate, 8, 141, 19, // Skip to: 13726 -/* 8721 */ MCD_OPC_Decode, 134, 12, 166, 1, // Opcode: SPLATI_W -/* 8726 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8745 -/* 8730 */ MCD_OPC_CheckPredicate, 8, 128, 19, // Skip to: 13726 -/* 8734 */ MCD_OPC_CheckField, 17, 1, 0, 122, 19, // Skip to: 13726 -/* 8740 */ MCD_OPC_Decode, 132, 12, 167, 1, // Opcode: SPLATI_D -/* 8745 */ MCD_OPC_FilterValue, 3, 113, 19, // Skip to: 13726 -/* 8749 */ MCD_OPC_CheckPredicate, 8, 109, 19, // Skip to: 13726 -/* 8753 */ MCD_OPC_CheckField, 16, 2, 2, 103, 19, // Skip to: 13726 -/* 8759 */ MCD_OPC_Decode, 240, 2, 168, 1, // Opcode: CFCMSA -/* 8764 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8777 -/* 8768 */ MCD_OPC_CheckPredicate, 8, 90, 19, // Skip to: 13726 -/* 8772 */ MCD_OPC_Decode, 202, 3, 169, 1, // Opcode: COPY_S_B -/* 8777 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 8796 -/* 8781 */ MCD_OPC_CheckPredicate, 8, 77, 19, // Skip to: 13726 -/* 8785 */ MCD_OPC_CheckField, 19, 1, 0, 71, 19, // Skip to: 13726 -/* 8791 */ MCD_OPC_Decode, 204, 3, 170, 1, // Opcode: COPY_S_H -/* 8796 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 8854 -/* 8800 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8803 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8816 -/* 8807 */ MCD_OPC_CheckPredicate, 8, 51, 19, // Skip to: 13726 -/* 8811 */ MCD_OPC_Decode, 205, 3, 171, 1, // Opcode: COPY_S_W -/* 8816 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8835 -/* 8820 */ MCD_OPC_CheckPredicate, 14, 38, 19, // Skip to: 13726 -/* 8824 */ MCD_OPC_CheckField, 17, 1, 0, 32, 19, // Skip to: 13726 -/* 8830 */ MCD_OPC_Decode, 203, 3, 172, 1, // Opcode: COPY_S_D -/* 8835 */ MCD_OPC_FilterValue, 3, 23, 19, // Skip to: 13726 -/* 8839 */ MCD_OPC_CheckPredicate, 8, 19, 19, // Skip to: 13726 -/* 8843 */ MCD_OPC_CheckField, 16, 2, 2, 13, 19, // Skip to: 13726 -/* 8849 */ MCD_OPC_Decode, 235, 8, 173, 1, // Opcode: MOVE_V -/* 8854 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8867 -/* 8858 */ MCD_OPC_CheckPredicate, 8, 0, 19, // Skip to: 13726 -/* 8862 */ MCD_OPC_Decode, 206, 3, 169, 1, // Opcode: COPY_U_B -/* 8867 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 8886 -/* 8871 */ MCD_OPC_CheckPredicate, 8, 243, 18, // Skip to: 13726 -/* 8875 */ MCD_OPC_CheckField, 19, 1, 0, 237, 18, // Skip to: 13726 -/* 8881 */ MCD_OPC_Decode, 208, 3, 170, 1, // Opcode: COPY_U_H -/* 8886 */ MCD_OPC_FilterValue, 15, 35, 0, // Skip to: 8925 -/* 8890 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8893 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8906 -/* 8897 */ MCD_OPC_CheckPredicate, 8, 217, 18, // Skip to: 13726 -/* 8901 */ MCD_OPC_Decode, 209, 3, 171, 1, // Opcode: COPY_U_W -/* 8906 */ MCD_OPC_FilterValue, 2, 208, 18, // Skip to: 13726 -/* 8910 */ MCD_OPC_CheckPredicate, 14, 204, 18, // Skip to: 13726 -/* 8914 */ MCD_OPC_CheckField, 17, 1, 0, 198, 18, // Skip to: 13726 -/* 8920 */ MCD_OPC_Decode, 207, 3, 172, 1, // Opcode: COPY_U_D -/* 8925 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8938 -/* 8929 */ MCD_OPC_CheckPredicate, 8, 185, 18, // Skip to: 13726 -/* 8933 */ MCD_OPC_Decode, 229, 6, 174, 1, // Opcode: INSERT_B -/* 8938 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 8957 -/* 8942 */ MCD_OPC_CheckPredicate, 8, 172, 18, // Skip to: 13726 -/* 8946 */ MCD_OPC_CheckField, 19, 1, 0, 166, 18, // Skip to: 13726 -/* 8952 */ MCD_OPC_Decode, 237, 6, 175, 1, // Opcode: INSERT_H -/* 8957 */ MCD_OPC_FilterValue, 19, 35, 0, // Skip to: 8996 -/* 8961 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 8964 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8977 -/* 8968 */ MCD_OPC_CheckPredicate, 8, 146, 18, // Skip to: 13726 -/* 8972 */ MCD_OPC_Decode, 239, 6, 176, 1, // Opcode: INSERT_W -/* 8977 */ MCD_OPC_FilterValue, 2, 137, 18, // Skip to: 13726 -/* 8981 */ MCD_OPC_CheckPredicate, 14, 133, 18, // Skip to: 13726 -/* 8985 */ MCD_OPC_CheckField, 17, 1, 0, 127, 18, // Skip to: 13726 -/* 8991 */ MCD_OPC_Decode, 231, 6, 177, 1, // Opcode: INSERT_D -/* 8996 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9009 -/* 9000 */ MCD_OPC_CheckPredicate, 8, 114, 18, // Skip to: 13726 -/* 9004 */ MCD_OPC_Decode, 242, 6, 178, 1, // Opcode: INSVE_B -/* 9009 */ MCD_OPC_FilterValue, 22, 15, 0, // Skip to: 9028 -/* 9013 */ MCD_OPC_CheckPredicate, 8, 101, 18, // Skip to: 13726 -/* 9017 */ MCD_OPC_CheckField, 19, 1, 0, 95, 18, // Skip to: 13726 -/* 9023 */ MCD_OPC_Decode, 244, 6, 178, 1, // Opcode: INSVE_H -/* 9028 */ MCD_OPC_FilterValue, 23, 86, 18, // Skip to: 13726 -/* 9032 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... -/* 9035 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9048 -/* 9039 */ MCD_OPC_CheckPredicate, 8, 75, 18, // Skip to: 13726 -/* 9043 */ MCD_OPC_Decode, 245, 6, 178, 1, // Opcode: INSVE_W -/* 9048 */ MCD_OPC_FilterValue, 2, 66, 18, // Skip to: 13726 -/* 9052 */ MCD_OPC_CheckPredicate, 8, 62, 18, // Skip to: 13726 -/* 9056 */ MCD_OPC_CheckField, 17, 1, 0, 56, 18, // Skip to: 13726 -/* 9062 */ MCD_OPC_Decode, 243, 6, 178, 1, // Opcode: INSVE_D -/* 9067 */ MCD_OPC_FilterValue, 26, 163, 1, // Skip to: 9490 -/* 9071 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9074 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9087 -/* 9078 */ MCD_OPC_CheckPredicate, 8, 36, 18, // Skip to: 13726 -/* 9082 */ MCD_OPC_Decode, 178, 5, 139, 1, // Opcode: FCAF_W -/* 9087 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9100 -/* 9091 */ MCD_OPC_CheckPredicate, 8, 23, 18, // Skip to: 13726 -/* 9095 */ MCD_OPC_Decode, 177, 5, 140, 1, // Opcode: FCAF_D -/* 9100 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9113 -/* 9104 */ MCD_OPC_CheckPredicate, 8, 10, 18, // Skip to: 13726 -/* 9108 */ MCD_OPC_Decode, 205, 5, 139, 1, // Opcode: FCUN_W -/* 9113 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9126 -/* 9117 */ MCD_OPC_CheckPredicate, 8, 253, 17, // Skip to: 13726 -/* 9121 */ MCD_OPC_Decode, 204, 5, 140, 1, // Opcode: FCUN_D -/* 9126 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9139 -/* 9130 */ MCD_OPC_CheckPredicate, 8, 240, 17, // Skip to: 13726 -/* 9134 */ MCD_OPC_Decode, 180, 5, 139, 1, // Opcode: FCEQ_W -/* 9139 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9152 -/* 9143 */ MCD_OPC_CheckPredicate, 8, 227, 17, // Skip to: 13726 -/* 9147 */ MCD_OPC_Decode, 179, 5, 140, 1, // Opcode: FCEQ_D -/* 9152 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9165 -/* 9156 */ MCD_OPC_CheckPredicate, 8, 214, 17, // Skip to: 13726 -/* 9160 */ MCD_OPC_Decode, 197, 5, 139, 1, // Opcode: FCUEQ_W -/* 9165 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9178 -/* 9169 */ MCD_OPC_CheckPredicate, 8, 201, 17, // Skip to: 13726 -/* 9173 */ MCD_OPC_Decode, 196, 5, 140, 1, // Opcode: FCUEQ_D -/* 9178 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9191 -/* 9182 */ MCD_OPC_CheckPredicate, 8, 188, 17, // Skip to: 13726 -/* 9186 */ MCD_OPC_Decode, 186, 5, 139, 1, // Opcode: FCLT_W -/* 9191 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9204 -/* 9195 */ MCD_OPC_CheckPredicate, 8, 175, 17, // Skip to: 13726 -/* 9199 */ MCD_OPC_Decode, 185, 5, 140, 1, // Opcode: FCLT_D -/* 9204 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9217 -/* 9208 */ MCD_OPC_CheckPredicate, 8, 162, 17, // Skip to: 13726 -/* 9212 */ MCD_OPC_Decode, 201, 5, 139, 1, // Opcode: FCULT_W -/* 9217 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9230 -/* 9221 */ MCD_OPC_CheckPredicate, 8, 149, 17, // Skip to: 13726 -/* 9225 */ MCD_OPC_Decode, 200, 5, 140, 1, // Opcode: FCULT_D -/* 9230 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9243 -/* 9234 */ MCD_OPC_CheckPredicate, 8, 136, 17, // Skip to: 13726 -/* 9238 */ MCD_OPC_Decode, 184, 5, 139, 1, // Opcode: FCLE_W -/* 9243 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9256 -/* 9247 */ MCD_OPC_CheckPredicate, 8, 123, 17, // Skip to: 13726 -/* 9251 */ MCD_OPC_Decode, 183, 5, 140, 1, // Opcode: FCLE_D -/* 9256 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9269 -/* 9260 */ MCD_OPC_CheckPredicate, 8, 110, 17, // Skip to: 13726 -/* 9264 */ MCD_OPC_Decode, 199, 5, 139, 1, // Opcode: FCULE_W -/* 9269 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9282 -/* 9273 */ MCD_OPC_CheckPredicate, 8, 97, 17, // Skip to: 13726 -/* 9277 */ MCD_OPC_Decode, 198, 5, 140, 1, // Opcode: FCULE_D -/* 9282 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9295 -/* 9286 */ MCD_OPC_CheckPredicate, 8, 84, 17, // Skip to: 13726 -/* 9290 */ MCD_OPC_Decode, 154, 6, 139, 1, // Opcode: FSAF_W -/* 9295 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9308 -/* 9299 */ MCD_OPC_CheckPredicate, 8, 71, 17, // Skip to: 13726 -/* 9303 */ MCD_OPC_Decode, 153, 6, 140, 1, // Opcode: FSAF_D -/* 9308 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 9321 -/* 9312 */ MCD_OPC_CheckPredicate, 8, 58, 17, // Skip to: 13726 -/* 9316 */ MCD_OPC_Decode, 188, 6, 139, 1, // Opcode: FSUN_W -/* 9321 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 9334 -/* 9325 */ MCD_OPC_CheckPredicate, 8, 45, 17, // Skip to: 13726 -/* 9329 */ MCD_OPC_Decode, 187, 6, 140, 1, // Opcode: FSUN_D -/* 9334 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9347 -/* 9338 */ MCD_OPC_CheckPredicate, 8, 32, 17, // Skip to: 13726 -/* 9342 */ MCD_OPC_Decode, 156, 6, 139, 1, // Opcode: FSEQ_W -/* 9347 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9360 -/* 9351 */ MCD_OPC_CheckPredicate, 8, 19, 17, // Skip to: 13726 -/* 9355 */ MCD_OPC_Decode, 155, 6, 140, 1, // Opcode: FSEQ_D -/* 9360 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 9373 -/* 9364 */ MCD_OPC_CheckPredicate, 8, 6, 17, // Skip to: 13726 -/* 9368 */ MCD_OPC_Decode, 180, 6, 139, 1, // Opcode: FSUEQ_W -/* 9373 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 9386 -/* 9377 */ MCD_OPC_CheckPredicate, 8, 249, 16, // Skip to: 13726 -/* 9381 */ MCD_OPC_Decode, 179, 6, 140, 1, // Opcode: FSUEQ_D -/* 9386 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9399 -/* 9390 */ MCD_OPC_CheckPredicate, 8, 236, 16, // Skip to: 13726 -/* 9394 */ MCD_OPC_Decode, 160, 6, 139, 1, // Opcode: FSLT_W -/* 9399 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9412 -/* 9403 */ MCD_OPC_CheckPredicate, 8, 223, 16, // Skip to: 13726 -/* 9407 */ MCD_OPC_Decode, 159, 6, 140, 1, // Opcode: FSLT_D -/* 9412 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9425 -/* 9416 */ MCD_OPC_CheckPredicate, 8, 210, 16, // Skip to: 13726 -/* 9420 */ MCD_OPC_Decode, 184, 6, 139, 1, // Opcode: FSULT_W -/* 9425 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9438 -/* 9429 */ MCD_OPC_CheckPredicate, 8, 197, 16, // Skip to: 13726 -/* 9433 */ MCD_OPC_Decode, 183, 6, 140, 1, // Opcode: FSULT_D -/* 9438 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9451 -/* 9442 */ MCD_OPC_CheckPredicate, 8, 184, 16, // Skip to: 13726 -/* 9446 */ MCD_OPC_Decode, 158, 6, 139, 1, // Opcode: FSLE_W -/* 9451 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9464 -/* 9455 */ MCD_OPC_CheckPredicate, 8, 171, 16, // Skip to: 13726 -/* 9459 */ MCD_OPC_Decode, 157, 6, 140, 1, // Opcode: FSLE_D -/* 9464 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9477 -/* 9468 */ MCD_OPC_CheckPredicate, 8, 158, 16, // Skip to: 13726 -/* 9472 */ MCD_OPC_Decode, 182, 6, 139, 1, // Opcode: FSULE_W -/* 9477 */ MCD_OPC_FilterValue, 31, 149, 16, // Skip to: 13726 -/* 9481 */ MCD_OPC_CheckPredicate, 8, 145, 16, // Skip to: 13726 -/* 9485 */ MCD_OPC_Decode, 181, 6, 140, 1, // Opcode: FSULE_D -/* 9490 */ MCD_OPC_FilterValue, 27, 85, 1, // Skip to: 9835 -/* 9494 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9497 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9510 -/* 9501 */ MCD_OPC_CheckPredicate, 8, 125, 16, // Skip to: 13726 -/* 9505 */ MCD_OPC_Decode, 176, 5, 139, 1, // Opcode: FADD_W -/* 9510 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9523 -/* 9514 */ MCD_OPC_CheckPredicate, 8, 112, 16, // Skip to: 13726 -/* 9518 */ MCD_OPC_Decode, 170, 5, 140, 1, // Opcode: FADD_D -/* 9523 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9536 -/* 9527 */ MCD_OPC_CheckPredicate, 8, 99, 16, // Skip to: 13726 -/* 9531 */ MCD_OPC_Decode, 178, 6, 139, 1, // Opcode: FSUB_W -/* 9536 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9549 -/* 9540 */ MCD_OPC_CheckPredicate, 8, 86, 16, // Skip to: 13726 -/* 9544 */ MCD_OPC_Decode, 172, 6, 140, 1, // Opcode: FSUB_D -/* 9549 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9562 -/* 9553 */ MCD_OPC_CheckPredicate, 8, 73, 16, // Skip to: 13726 -/* 9557 */ MCD_OPC_Decode, 141, 6, 139, 1, // Opcode: FMUL_W -/* 9562 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9575 -/* 9566 */ MCD_OPC_CheckPredicate, 8, 60, 16, // Skip to: 13726 -/* 9570 */ MCD_OPC_Decode, 135, 6, 140, 1, // Opcode: FMUL_D -/* 9575 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9588 -/* 9579 */ MCD_OPC_CheckPredicate, 8, 47, 16, // Skip to: 13726 -/* 9583 */ MCD_OPC_Decode, 212, 5, 139, 1, // Opcode: FDIV_W -/* 9588 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9601 -/* 9592 */ MCD_OPC_CheckPredicate, 8, 34, 16, // Skip to: 13726 -/* 9596 */ MCD_OPC_Decode, 206, 5, 140, 1, // Opcode: FDIV_D -/* 9601 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9614 -/* 9605 */ MCD_OPC_CheckPredicate, 8, 21, 16, // Skip to: 13726 -/* 9609 */ MCD_OPC_Decode, 247, 5, 143, 1, // Opcode: FMADD_W -/* 9614 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9627 -/* 9618 */ MCD_OPC_CheckPredicate, 8, 8, 16, // Skip to: 13726 -/* 9622 */ MCD_OPC_Decode, 246, 5, 144, 1, // Opcode: FMADD_D -/* 9627 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9640 -/* 9631 */ MCD_OPC_CheckPredicate, 8, 251, 15, // Skip to: 13726 -/* 9635 */ MCD_OPC_Decode, 134, 6, 143, 1, // Opcode: FMSUB_W -/* 9640 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9653 -/* 9644 */ MCD_OPC_CheckPredicate, 8, 238, 15, // Skip to: 13726 -/* 9648 */ MCD_OPC_Decode, 133, 6, 144, 1, // Opcode: FMSUB_D -/* 9653 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9666 -/* 9657 */ MCD_OPC_CheckPredicate, 8, 225, 15, // Skip to: 13726 -/* 9661 */ MCD_OPC_Decode, 217, 5, 139, 1, // Opcode: FEXP2_W -/* 9666 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9679 -/* 9670 */ MCD_OPC_CheckPredicate, 8, 212, 15, // Skip to: 13726 -/* 9674 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: FEXP2_D -/* 9679 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9692 -/* 9683 */ MCD_OPC_CheckPredicate, 8, 199, 15, // Skip to: 13726 -/* 9687 */ MCD_OPC_Decode, 213, 5, 179, 1, // Opcode: FEXDO_H -/* 9692 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9705 -/* 9696 */ MCD_OPC_CheckPredicate, 8, 186, 15, // Skip to: 13726 -/* 9700 */ MCD_OPC_Decode, 214, 5, 180, 1, // Opcode: FEXDO_W -/* 9705 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9718 -/* 9709 */ MCD_OPC_CheckPredicate, 8, 173, 15, // Skip to: 13726 -/* 9713 */ MCD_OPC_Decode, 193, 6, 179, 1, // Opcode: FTQ_H -/* 9718 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9731 -/* 9722 */ MCD_OPC_CheckPredicate, 8, 160, 15, // Skip to: 13726 -/* 9726 */ MCD_OPC_Decode, 194, 6, 180, 1, // Opcode: FTQ_W -/* 9731 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9744 -/* 9735 */ MCD_OPC_CheckPredicate, 8, 147, 15, // Skip to: 13726 -/* 9739 */ MCD_OPC_Decode, 255, 5, 139, 1, // Opcode: FMIN_W -/* 9744 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9757 -/* 9748 */ MCD_OPC_CheckPredicate, 8, 134, 15, // Skip to: 13726 -/* 9752 */ MCD_OPC_Decode, 254, 5, 140, 1, // Opcode: FMIN_D -/* 9757 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9770 -/* 9761 */ MCD_OPC_CheckPredicate, 8, 121, 15, // Skip to: 13726 -/* 9765 */ MCD_OPC_Decode, 253, 5, 139, 1, // Opcode: FMIN_A_W -/* 9770 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9783 -/* 9774 */ MCD_OPC_CheckPredicate, 8, 108, 15, // Skip to: 13726 -/* 9778 */ MCD_OPC_Decode, 252, 5, 140, 1, // Opcode: FMIN_A_D -/* 9783 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9796 -/* 9787 */ MCD_OPC_CheckPredicate, 8, 95, 15, // Skip to: 13726 -/* 9791 */ MCD_OPC_Decode, 251, 5, 139, 1, // Opcode: FMAX_W -/* 9796 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9809 -/* 9800 */ MCD_OPC_CheckPredicate, 8, 82, 15, // Skip to: 13726 -/* 9804 */ MCD_OPC_Decode, 250, 5, 140, 1, // Opcode: FMAX_D -/* 9809 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9822 -/* 9813 */ MCD_OPC_CheckPredicate, 8, 69, 15, // Skip to: 13726 -/* 9817 */ MCD_OPC_Decode, 249, 5, 139, 1, // Opcode: FMAX_A_W -/* 9822 */ MCD_OPC_FilterValue, 31, 60, 15, // Skip to: 13726 -/* 9826 */ MCD_OPC_CheckPredicate, 8, 56, 15, // Skip to: 13726 -/* 9830 */ MCD_OPC_Decode, 248, 5, 140, 1, // Opcode: FMAX_A_D -/* 9835 */ MCD_OPC_FilterValue, 28, 59, 1, // Skip to: 10154 -/* 9839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 9842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9855 -/* 9846 */ MCD_OPC_CheckPredicate, 8, 36, 15, // Skip to: 13726 -/* 9850 */ MCD_OPC_Decode, 195, 5, 139, 1, // Opcode: FCOR_W -/* 9855 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9868 -/* 9859 */ MCD_OPC_CheckPredicate, 8, 23, 15, // Skip to: 13726 -/* 9863 */ MCD_OPC_Decode, 194, 5, 140, 1, // Opcode: FCOR_D -/* 9868 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9881 -/* 9872 */ MCD_OPC_CheckPredicate, 8, 10, 15, // Skip to: 13726 -/* 9876 */ MCD_OPC_Decode, 203, 5, 139, 1, // Opcode: FCUNE_W -/* 9881 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9894 -/* 9885 */ MCD_OPC_CheckPredicate, 8, 253, 14, // Skip to: 13726 -/* 9889 */ MCD_OPC_Decode, 202, 5, 140, 1, // Opcode: FCUNE_D -/* 9894 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9907 -/* 9898 */ MCD_OPC_CheckPredicate, 8, 240, 14, // Skip to: 13726 -/* 9902 */ MCD_OPC_Decode, 193, 5, 139, 1, // Opcode: FCNE_W -/* 9907 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9920 -/* 9911 */ MCD_OPC_CheckPredicate, 8, 227, 14, // Skip to: 13726 -/* 9915 */ MCD_OPC_Decode, 192, 5, 140, 1, // Opcode: FCNE_D -/* 9920 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9933 -/* 9924 */ MCD_OPC_CheckPredicate, 8, 214, 14, // Skip to: 13726 -/* 9928 */ MCD_OPC_Decode, 219, 9, 138, 1, // Opcode: MUL_Q_H -/* 9933 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9946 -/* 9937 */ MCD_OPC_CheckPredicate, 8, 201, 14, // Skip to: 13726 -/* 9941 */ MCD_OPC_Decode, 220, 9, 139, 1, // Opcode: MUL_Q_W -/* 9946 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9959 -/* 9950 */ MCD_OPC_CheckPredicate, 8, 188, 14, // Skip to: 13726 -/* 9954 */ MCD_OPC_Decode, 147, 8, 142, 1, // Opcode: MADD_Q_H -/* 9959 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9972 -/* 9963 */ MCD_OPC_CheckPredicate, 8, 175, 14, // Skip to: 13726 -/* 9967 */ MCD_OPC_Decode, 148, 8, 143, 1, // Opcode: MADD_Q_W -/* 9972 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9985 -/* 9976 */ MCD_OPC_CheckPredicate, 8, 162, 14, // Skip to: 13726 -/* 9980 */ MCD_OPC_Decode, 165, 9, 142, 1, // Opcode: MSUB_Q_H -/* 9985 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9998 -/* 9989 */ MCD_OPC_CheckPredicate, 8, 149, 14, // Skip to: 13726 -/* 9993 */ MCD_OPC_Decode, 166, 9, 143, 1, // Opcode: MSUB_Q_W -/* 9998 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10011 -/* 10002 */ MCD_OPC_CheckPredicate, 8, 136, 14, // Skip to: 13726 -/* 10006 */ MCD_OPC_Decode, 164, 6, 139, 1, // Opcode: FSOR_W -/* 10011 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10024 -/* 10015 */ MCD_OPC_CheckPredicate, 8, 123, 14, // Skip to: 13726 -/* 10019 */ MCD_OPC_Decode, 163, 6, 140, 1, // Opcode: FSOR_D -/* 10024 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10037 -/* 10028 */ MCD_OPC_CheckPredicate, 8, 110, 14, // Skip to: 13726 -/* 10032 */ MCD_OPC_Decode, 186, 6, 139, 1, // Opcode: FSUNE_W -/* 10037 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10050 -/* 10041 */ MCD_OPC_CheckPredicate, 8, 97, 14, // Skip to: 13726 -/* 10045 */ MCD_OPC_Decode, 185, 6, 140, 1, // Opcode: FSUNE_D -/* 10050 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10063 -/* 10054 */ MCD_OPC_CheckPredicate, 8, 84, 14, // Skip to: 13726 -/* 10058 */ MCD_OPC_Decode, 162, 6, 139, 1, // Opcode: FSNE_W -/* 10063 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10076 -/* 10067 */ MCD_OPC_CheckPredicate, 8, 71, 14, // Skip to: 13726 -/* 10071 */ MCD_OPC_Decode, 161, 6, 140, 1, // Opcode: FSNE_D -/* 10076 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10089 -/* 10080 */ MCD_OPC_CheckPredicate, 8, 58, 14, // Skip to: 13726 -/* 10084 */ MCD_OPC_Decode, 202, 9, 138, 1, // Opcode: MULR_Q_H -/* 10089 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10102 -/* 10093 */ MCD_OPC_CheckPredicate, 8, 45, 14, // Skip to: 13726 -/* 10097 */ MCD_OPC_Decode, 203, 9, 139, 1, // Opcode: MULR_Q_W -/* 10102 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10115 -/* 10106 */ MCD_OPC_CheckPredicate, 8, 32, 14, // Skip to: 13726 -/* 10110 */ MCD_OPC_Decode, 133, 8, 142, 1, // Opcode: MADDR_Q_H -/* 10115 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10128 -/* 10119 */ MCD_OPC_CheckPredicate, 8, 19, 14, // Skip to: 13726 -/* 10123 */ MCD_OPC_Decode, 134, 8, 143, 1, // Opcode: MADDR_Q_W -/* 10128 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10141 -/* 10132 */ MCD_OPC_CheckPredicate, 8, 6, 14, // Skip to: 13726 -/* 10136 */ MCD_OPC_Decode, 151, 9, 142, 1, // Opcode: MSUBR_Q_H -/* 10141 */ MCD_OPC_FilterValue, 29, 253, 13, // Skip to: 13726 -/* 10145 */ MCD_OPC_CheckPredicate, 8, 249, 13, // Skip to: 13726 -/* 10149 */ MCD_OPC_Decode, 152, 9, 143, 1, // Opcode: MSUBR_Q_W -/* 10154 */ MCD_OPC_FilterValue, 30, 219, 2, // Skip to: 10889 -/* 10158 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 10161 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10173 -/* 10165 */ MCD_OPC_CheckPredicate, 8, 229, 13, // Skip to: 13726 -/* 10169 */ MCD_OPC_Decode, 89, 137, 1, // Opcode: AND_V -/* 10173 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10186 -/* 10177 */ MCD_OPC_CheckPredicate, 8, 217, 13, // Skip to: 13726 -/* 10181 */ MCD_OPC_Decode, 138, 10, 137, 1, // Opcode: OR_V -/* 10186 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10199 -/* 10190 */ MCD_OPC_CheckPredicate, 8, 204, 13, // Skip to: 13726 -/* 10194 */ MCD_OPC_Decode, 254, 9, 137, 1, // Opcode: NOR_V -/* 10199 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10212 -/* 10203 */ MCD_OPC_CheckPredicate, 8, 191, 13, // Skip to: 13726 -/* 10207 */ MCD_OPC_Decode, 241, 13, 137, 1, // Opcode: XOR_V -/* 10212 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10225 -/* 10216 */ MCD_OPC_CheckPredicate, 8, 178, 13, // Skip to: 13726 -/* 10220 */ MCD_OPC_Decode, 142, 2, 141, 1, // Opcode: BMNZ_V -/* 10225 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10238 -/* 10229 */ MCD_OPC_CheckPredicate, 8, 165, 13, // Skip to: 13726 -/* 10233 */ MCD_OPC_Decode, 144, 2, 141, 1, // Opcode: BMZ_V -/* 10238 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10251 -/* 10242 */ MCD_OPC_CheckPredicate, 8, 152, 13, // Skip to: 13726 -/* 10246 */ MCD_OPC_Decode, 179, 2, 141, 1, // Opcode: BSEL_V -/* 10251 */ MCD_OPC_FilterValue, 24, 211, 0, // Skip to: 10466 -/* 10255 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10271 -/* 10262 */ MCD_OPC_CheckPredicate, 8, 132, 13, // Skip to: 13726 -/* 10266 */ MCD_OPC_Decode, 231, 5, 181, 1, // Opcode: FILL_B -/* 10271 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10284 -/* 10275 */ MCD_OPC_CheckPredicate, 8, 119, 13, // Skip to: 13726 -/* 10279 */ MCD_OPC_Decode, 235, 5, 182, 1, // Opcode: FILL_H -/* 10284 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10297 -/* 10288 */ MCD_OPC_CheckPredicate, 8, 106, 13, // Skip to: 13726 -/* 10292 */ MCD_OPC_Decode, 236, 5, 183, 1, // Opcode: FILL_W -/* 10297 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10310 -/* 10301 */ MCD_OPC_CheckPredicate, 14, 93, 13, // Skip to: 13726 -/* 10305 */ MCD_OPC_Decode, 232, 5, 184, 1, // Opcode: FILL_D -/* 10310 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10323 -/* 10314 */ MCD_OPC_CheckPredicate, 8, 80, 13, // Skip to: 13726 -/* 10318 */ MCD_OPC_Decode, 157, 10, 173, 1, // Opcode: PCNT_B -/* 10323 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10336 -/* 10327 */ MCD_OPC_CheckPredicate, 8, 67, 13, // Skip to: 13726 -/* 10331 */ MCD_OPC_Decode, 159, 10, 185, 1, // Opcode: PCNT_H -/* 10336 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10349 -/* 10340 */ MCD_OPC_CheckPredicate, 8, 54, 13, // Skip to: 13726 -/* 10344 */ MCD_OPC_Decode, 160, 10, 186, 1, // Opcode: PCNT_W -/* 10349 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10362 -/* 10353 */ MCD_OPC_CheckPredicate, 8, 41, 13, // Skip to: 13726 -/* 10357 */ MCD_OPC_Decode, 158, 10, 187, 1, // Opcode: PCNT_D -/* 10362 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10375 -/* 10366 */ MCD_OPC_CheckPredicate, 8, 28, 13, // Skip to: 13726 -/* 10370 */ MCD_OPC_Decode, 231, 9, 173, 1, // Opcode: NLOC_B -/* 10375 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10388 -/* 10379 */ MCD_OPC_CheckPredicate, 8, 15, 13, // Skip to: 13726 -/* 10383 */ MCD_OPC_Decode, 233, 9, 185, 1, // Opcode: NLOC_H -/* 10388 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10401 -/* 10392 */ MCD_OPC_CheckPredicate, 8, 2, 13, // Skip to: 13726 -/* 10396 */ MCD_OPC_Decode, 234, 9, 186, 1, // Opcode: NLOC_W -/* 10401 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10414 -/* 10405 */ MCD_OPC_CheckPredicate, 8, 245, 12, // Skip to: 13726 -/* 10409 */ MCD_OPC_Decode, 232, 9, 187, 1, // Opcode: NLOC_D -/* 10414 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10427 -/* 10418 */ MCD_OPC_CheckPredicate, 8, 232, 12, // Skip to: 13726 -/* 10422 */ MCD_OPC_Decode, 235, 9, 173, 1, // Opcode: NLZC_B -/* 10427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10440 -/* 10431 */ MCD_OPC_CheckPredicate, 8, 219, 12, // Skip to: 13726 -/* 10435 */ MCD_OPC_Decode, 237, 9, 185, 1, // Opcode: NLZC_H -/* 10440 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10453 -/* 10444 */ MCD_OPC_CheckPredicate, 8, 206, 12, // Skip to: 13726 -/* 10448 */ MCD_OPC_Decode, 238, 9, 186, 1, // Opcode: NLZC_W -/* 10453 */ MCD_OPC_FilterValue, 15, 197, 12, // Skip to: 13726 -/* 10457 */ MCD_OPC_CheckPredicate, 8, 193, 12, // Skip to: 13726 -/* 10461 */ MCD_OPC_Decode, 236, 9, 187, 1, // Opcode: NLZC_D -/* 10466 */ MCD_OPC_FilterValue, 25, 184, 12, // Skip to: 13726 -/* 10470 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10473 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10486 -/* 10477 */ MCD_OPC_CheckPredicate, 8, 173, 12, // Skip to: 13726 -/* 10481 */ MCD_OPC_Decode, 182, 5, 186, 1, // Opcode: FCLASS_W -/* 10486 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10499 -/* 10490 */ MCD_OPC_CheckPredicate, 8, 160, 12, // Skip to: 13726 -/* 10494 */ MCD_OPC_Decode, 181, 5, 187, 1, // Opcode: FCLASS_D -/* 10499 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10512 -/* 10503 */ MCD_OPC_CheckPredicate, 8, 147, 12, // Skip to: 13726 -/* 10507 */ MCD_OPC_Decode, 196, 6, 186, 1, // Opcode: FTRUNC_S_W -/* 10512 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10525 -/* 10516 */ MCD_OPC_CheckPredicate, 8, 134, 12, // Skip to: 13726 -/* 10520 */ MCD_OPC_Decode, 195, 6, 187, 1, // Opcode: FTRUNC_S_D -/* 10525 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10538 -/* 10529 */ MCD_OPC_CheckPredicate, 8, 121, 12, // Skip to: 13726 -/* 10533 */ MCD_OPC_Decode, 198, 6, 186, 1, // Opcode: FTRUNC_U_W -/* 10538 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10551 -/* 10542 */ MCD_OPC_CheckPredicate, 8, 108, 12, // Skip to: 13726 -/* 10546 */ MCD_OPC_Decode, 197, 6, 187, 1, // Opcode: FTRUNC_U_D -/* 10551 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10564 -/* 10555 */ MCD_OPC_CheckPredicate, 8, 95, 12, // Skip to: 13726 -/* 10559 */ MCD_OPC_Decode, 171, 6, 186, 1, // Opcode: FSQRT_W -/* 10564 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10577 -/* 10568 */ MCD_OPC_CheckPredicate, 8, 82, 12, // Skip to: 13726 -/* 10572 */ MCD_OPC_Decode, 165, 6, 187, 1, // Opcode: FSQRT_D -/* 10577 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10590 -/* 10581 */ MCD_OPC_CheckPredicate, 8, 69, 12, // Skip to: 13726 -/* 10585 */ MCD_OPC_Decode, 152, 6, 186, 1, // Opcode: FRSQRT_W -/* 10590 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10603 -/* 10594 */ MCD_OPC_CheckPredicate, 8, 56, 12, // Skip to: 13726 -/* 10598 */ MCD_OPC_Decode, 151, 6, 187, 1, // Opcode: FRSQRT_D -/* 10603 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10616 -/* 10607 */ MCD_OPC_CheckPredicate, 8, 43, 12, // Skip to: 13726 -/* 10611 */ MCD_OPC_Decode, 148, 6, 186, 1, // Opcode: FRCP_W -/* 10616 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10629 -/* 10620 */ MCD_OPC_CheckPredicate, 8, 30, 12, // Skip to: 13726 -/* 10624 */ MCD_OPC_Decode, 147, 6, 187, 1, // Opcode: FRCP_D -/* 10629 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10642 -/* 10633 */ MCD_OPC_CheckPredicate, 8, 17, 12, // Skip to: 13726 -/* 10637 */ MCD_OPC_Decode, 150, 6, 186, 1, // Opcode: FRINT_W -/* 10642 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10655 -/* 10646 */ MCD_OPC_CheckPredicate, 8, 4, 12, // Skip to: 13726 -/* 10650 */ MCD_OPC_Decode, 149, 6, 187, 1, // Opcode: FRINT_D -/* 10655 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10668 -/* 10659 */ MCD_OPC_CheckPredicate, 8, 247, 11, // Skip to: 13726 -/* 10663 */ MCD_OPC_Decode, 238, 5, 186, 1, // Opcode: FLOG2_W -/* 10668 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10681 -/* 10672 */ MCD_OPC_CheckPredicate, 8, 234, 11, // Skip to: 13726 -/* 10676 */ MCD_OPC_Decode, 237, 5, 187, 1, // Opcode: FLOG2_D -/* 10681 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 10694 -/* 10685 */ MCD_OPC_CheckPredicate, 8, 221, 11, // Skip to: 13726 -/* 10689 */ MCD_OPC_Decode, 220, 5, 188, 1, // Opcode: FEXUPL_W -/* 10694 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 10707 -/* 10698 */ MCD_OPC_CheckPredicate, 8, 208, 11, // Skip to: 13726 -/* 10702 */ MCD_OPC_Decode, 219, 5, 189, 1, // Opcode: FEXUPL_D -/* 10707 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10720 -/* 10711 */ MCD_OPC_CheckPredicate, 8, 195, 11, // Skip to: 13726 -/* 10715 */ MCD_OPC_Decode, 222, 5, 188, 1, // Opcode: FEXUPR_W -/* 10720 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10733 -/* 10724 */ MCD_OPC_CheckPredicate, 8, 182, 11, // Skip to: 13726 -/* 10728 */ MCD_OPC_Decode, 221, 5, 189, 1, // Opcode: FEXUPR_D -/* 10733 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10746 -/* 10737 */ MCD_OPC_CheckPredicate, 8, 169, 11, // Skip to: 13726 -/* 10741 */ MCD_OPC_Decode, 228, 5, 188, 1, // Opcode: FFQL_W -/* 10746 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10759 -/* 10750 */ MCD_OPC_CheckPredicate, 8, 156, 11, // Skip to: 13726 -/* 10754 */ MCD_OPC_Decode, 227, 5, 189, 1, // Opcode: FFQL_D -/* 10759 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10772 -/* 10763 */ MCD_OPC_CheckPredicate, 8, 143, 11, // Skip to: 13726 -/* 10767 */ MCD_OPC_Decode, 230, 5, 188, 1, // Opcode: FFQR_W -/* 10772 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10785 -/* 10776 */ MCD_OPC_CheckPredicate, 8, 130, 11, // Skip to: 13726 -/* 10780 */ MCD_OPC_Decode, 229, 5, 189, 1, // Opcode: FFQR_D -/* 10785 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10798 -/* 10789 */ MCD_OPC_CheckPredicate, 8, 117, 11, // Skip to: 13726 -/* 10793 */ MCD_OPC_Decode, 190, 6, 186, 1, // Opcode: FTINT_S_W -/* 10798 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10811 -/* 10802 */ MCD_OPC_CheckPredicate, 8, 104, 11, // Skip to: 13726 -/* 10806 */ MCD_OPC_Decode, 189, 6, 187, 1, // Opcode: FTINT_S_D -/* 10811 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10824 -/* 10815 */ MCD_OPC_CheckPredicate, 8, 91, 11, // Skip to: 13726 -/* 10819 */ MCD_OPC_Decode, 192, 6, 186, 1, // Opcode: FTINT_U_W -/* 10824 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10837 -/* 10828 */ MCD_OPC_CheckPredicate, 8, 78, 11, // Skip to: 13726 -/* 10832 */ MCD_OPC_Decode, 191, 6, 187, 1, // Opcode: FTINT_U_D -/* 10837 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10850 -/* 10841 */ MCD_OPC_CheckPredicate, 8, 65, 11, // Skip to: 13726 -/* 10845 */ MCD_OPC_Decode, 224, 5, 186, 1, // Opcode: FFINT_S_W -/* 10850 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 10863 -/* 10854 */ MCD_OPC_CheckPredicate, 8, 52, 11, // Skip to: 13726 -/* 10858 */ MCD_OPC_Decode, 223, 5, 187, 1, // Opcode: FFINT_S_D -/* 10863 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 10876 -/* 10867 */ MCD_OPC_CheckPredicate, 8, 39, 11, // Skip to: 13726 -/* 10871 */ MCD_OPC_Decode, 226, 5, 186, 1, // Opcode: FFINT_U_W -/* 10876 */ MCD_OPC_FilterValue, 31, 30, 11, // Skip to: 13726 -/* 10880 */ MCD_OPC_CheckPredicate, 8, 26, 11, // Skip to: 13726 -/* 10884 */ MCD_OPC_Decode, 225, 5, 187, 1, // Opcode: FFINT_U_D -/* 10889 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 10902 -/* 10893 */ MCD_OPC_CheckPredicate, 8, 13, 11, // Skip to: 13726 -/* 10897 */ MCD_OPC_Decode, 177, 7, 190, 1, // Opcode: LD_B -/* 10902 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 10915 -/* 10906 */ MCD_OPC_CheckPredicate, 8, 0, 11, // Skip to: 13726 -/* 10910 */ MCD_OPC_Decode, 179, 7, 190, 1, // Opcode: LD_H -/* 10915 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 10928 -/* 10919 */ MCD_OPC_CheckPredicate, 8, 243, 10, // Skip to: 13726 -/* 10923 */ MCD_OPC_Decode, 180, 7, 190, 1, // Opcode: LD_W -/* 10928 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 10941 -/* 10932 */ MCD_OPC_CheckPredicate, 8, 230, 10, // Skip to: 13726 -/* 10936 */ MCD_OPC_Decode, 178, 7, 190, 1, // Opcode: LD_D -/* 10941 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 10954 -/* 10945 */ MCD_OPC_CheckPredicate, 8, 217, 10, // Skip to: 13726 -/* 10949 */ MCD_OPC_Decode, 186, 12, 190, 1, // Opcode: ST_B -/* 10954 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 10967 -/* 10958 */ MCD_OPC_CheckPredicate, 8, 204, 10, // Skip to: 13726 -/* 10962 */ MCD_OPC_Decode, 188, 12, 190, 1, // Opcode: ST_H -/* 10967 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 10980 -/* 10971 */ MCD_OPC_CheckPredicate, 8, 191, 10, // Skip to: 13726 -/* 10975 */ MCD_OPC_Decode, 189, 12, 190, 1, // Opcode: ST_W -/* 10980 */ MCD_OPC_FilterValue, 39, 182, 10, // Skip to: 13726 -/* 10984 */ MCD_OPC_CheckPredicate, 8, 178, 10, // Skip to: 13726 -/* 10988 */ MCD_OPC_Decode, 187, 12, 190, 1, // Opcode: ST_D -/* 10993 */ MCD_OPC_FilterValue, 31, 113, 9, // Skip to: 13414 -/* 10997 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 11000 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11013 -/* 11004 */ MCD_OPC_CheckPredicate, 6, 158, 10, // Skip to: 13726 -/* 11008 */ MCD_OPC_Decode, 145, 5, 191, 1, // Opcode: EXT -/* 11013 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11026 -/* 11017 */ MCD_OPC_CheckPredicate, 6, 145, 10, // Skip to: 13726 -/* 11021 */ MCD_OPC_Decode, 228, 6, 192, 1, // Opcode: INS -/* 11026 */ MCD_OPC_FilterValue, 10, 42, 0, // Skip to: 11072 -/* 11030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11033 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11046 -/* 11037 */ MCD_OPC_CheckPredicate, 12, 125, 10, // Skip to: 13726 -/* 11041 */ MCD_OPC_Decode, 236, 7, 193, 1, // Opcode: LWX -/* 11046 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11059 -/* 11050 */ MCD_OPC_CheckPredicate, 12, 112, 10, // Skip to: 13726 -/* 11054 */ MCD_OPC_Decode, 187, 7, 193, 1, // Opcode: LHX -/* 11059 */ MCD_OPC_FilterValue, 6, 103, 10, // Skip to: 13726 -/* 11063 */ MCD_OPC_CheckPredicate, 12, 99, 10, // Skip to: 13726 -/* 11067 */ MCD_OPC_Decode, 156, 7, 193, 1, // Opcode: LBUX -/* 11072 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11091 -/* 11076 */ MCD_OPC_CheckPredicate, 12, 86, 10, // Skip to: 13726 -/* 11080 */ MCD_OPC_CheckField, 6, 10, 0, 80, 10, // Skip to: 13726 -/* 11086 */ MCD_OPC_Decode, 241, 6, 194, 1, // Opcode: INSV -/* 11091 */ MCD_OPC_FilterValue, 16, 51, 1, // Skip to: 11402 -/* 11095 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11098 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11110 -/* 11102 */ MCD_OPC_CheckPredicate, 12, 60, 10, // Skip to: 13726 -/* 11106 */ MCD_OPC_Decode, 56, 195, 1, // Opcode: ADDU_QB -/* 11110 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 11123 -/* 11114 */ MCD_OPC_CheckPredicate, 12, 48, 10, // Skip to: 13726 -/* 11118 */ MCD_OPC_Decode, 218, 12, 195, 1, // Opcode: SUBU_QB -/* 11123 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11135 -/* 11127 */ MCD_OPC_CheckPredicate, 12, 35, 10, // Skip to: 13726 -/* 11131 */ MCD_OPC_Decode, 58, 195, 1, // Opcode: ADDU_S_QB -/* 11135 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11148 -/* 11139 */ MCD_OPC_CheckPredicate, 12, 23, 10, // Skip to: 13726 -/* 11143 */ MCD_OPC_Decode, 220, 12, 195, 1, // Opcode: SUBU_S_QB -/* 11148 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11161 -/* 11152 */ MCD_OPC_CheckPredicate, 12, 10, 10, // Skip to: 13726 -/* 11156 */ MCD_OPC_Decode, 196, 9, 195, 1, // Opcode: MULEU_S_PH_QBL -/* 11161 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 11174 -/* 11165 */ MCD_OPC_CheckPredicate, 12, 253, 9, // Skip to: 13726 -/* 11169 */ MCD_OPC_Decode, 197, 9, 195, 1, // Opcode: MULEU_S_PH_QBR -/* 11174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11186 -/* 11178 */ MCD_OPC_CheckPredicate, 30, 240, 9, // Skip to: 13726 -/* 11182 */ MCD_OPC_Decode, 55, 195, 1, // Opcode: ADDU_PH -/* 11186 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 11199 -/* 11190 */ MCD_OPC_CheckPredicate, 30, 228, 9, // Skip to: 13726 -/* 11194 */ MCD_OPC_Decode, 217, 12, 195, 1, // Opcode: SUBU_PH -/* 11199 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11211 -/* 11203 */ MCD_OPC_CheckPredicate, 12, 215, 9, // Skip to: 13726 -/* 11207 */ MCD_OPC_Decode, 36, 195, 1, // Opcode: ADDQ_PH -/* 11211 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11224 -/* 11215 */ MCD_OPC_CheckPredicate, 12, 203, 9, // Skip to: 13726 -/* 11219 */ MCD_OPC_Decode, 195, 12, 195, 1, // Opcode: SUBQ_PH -/* 11224 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11236 -/* 11228 */ MCD_OPC_CheckPredicate, 30, 190, 9, // Skip to: 13726 -/* 11232 */ MCD_OPC_Decode, 57, 195, 1, // Opcode: ADDU_S_PH -/* 11236 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11249 -/* 11240 */ MCD_OPC_CheckPredicate, 30, 178, 9, // Skip to: 13726 -/* 11244 */ MCD_OPC_Decode, 219, 12, 195, 1, // Opcode: SUBU_S_PH -/* 11249 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 11261 -/* 11253 */ MCD_OPC_CheckPredicate, 12, 165, 9, // Skip to: 13726 -/* 11257 */ MCD_OPC_Decode, 37, 195, 1, // Opcode: ADDQ_S_PH -/* 11261 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11274 -/* 11265 */ MCD_OPC_CheckPredicate, 12, 153, 9, // Skip to: 13726 -/* 11269 */ MCD_OPC_Decode, 196, 12, 195, 1, // Opcode: SUBQ_S_PH -/* 11274 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 11285 -/* 11278 */ MCD_OPC_CheckPredicate, 12, 140, 9, // Skip to: 13726 -/* 11282 */ MCD_OPC_Decode, 39, 35, // Opcode: ADDSC -/* 11285 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 11296 -/* 11289 */ MCD_OPC_CheckPredicate, 12, 129, 9, // Skip to: 13726 -/* 11293 */ MCD_OPC_Decode, 67, 35, // Opcode: ADDWC -/* 11296 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 11308 -/* 11300 */ MCD_OPC_CheckPredicate, 12, 118, 9, // Skip to: 13726 -/* 11304 */ MCD_OPC_Decode, 223, 8, 35, // Opcode: MODSUB -/* 11308 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 11327 -/* 11312 */ MCD_OPC_CheckPredicate, 12, 106, 9, // Skip to: 13726 -/* 11316 */ MCD_OPC_CheckField, 16, 5, 0, 100, 9, // Skip to: 13726 -/* 11322 */ MCD_OPC_Decode, 236, 10, 196, 1, // Opcode: RADDU_W_QB -/* 11327 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 11338 -/* 11331 */ MCD_OPC_CheckPredicate, 12, 87, 9, // Skip to: 13726 -/* 11335 */ MCD_OPC_Decode, 38, 35, // Opcode: ADDQ_S_W -/* 11338 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 11350 -/* 11342 */ MCD_OPC_CheckPredicate, 12, 76, 9, // Skip to: 13726 -/* 11346 */ MCD_OPC_Decode, 197, 12, 35, // Opcode: SUBQ_S_W -/* 11350 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 11363 -/* 11354 */ MCD_OPC_CheckPredicate, 12, 64, 9, // Skip to: 13726 -/* 11358 */ MCD_OPC_Decode, 194, 9, 197, 1, // Opcode: MULEQ_S_W_PHL -/* 11363 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 11376 -/* 11367 */ MCD_OPC_CheckPredicate, 12, 51, 9, // Skip to: 13726 -/* 11371 */ MCD_OPC_Decode, 195, 9, 197, 1, // Opcode: MULEQ_S_W_PHR -/* 11376 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11389 -/* 11380 */ MCD_OPC_CheckPredicate, 30, 38, 9, // Skip to: 13726 -/* 11384 */ MCD_OPC_Decode, 200, 9, 195, 1, // Opcode: MULQ_S_PH -/* 11389 */ MCD_OPC_FilterValue, 31, 29, 9, // Skip to: 13726 -/* 11393 */ MCD_OPC_CheckPredicate, 12, 25, 9, // Skip to: 13726 -/* 11397 */ MCD_OPC_Decode, 198, 9, 195, 1, // Opcode: MULQ_RS_PH -/* 11402 */ MCD_OPC_FilterValue, 17, 69, 1, // Skip to: 11731 -/* 11406 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11409 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11428 -/* 11413 */ MCD_OPC_CheckPredicate, 12, 5, 9, // Skip to: 13726 -/* 11417 */ MCD_OPC_CheckField, 11, 5, 0, 255, 8, // Skip to: 13726 -/* 11423 */ MCD_OPC_Decode, 161, 3, 198, 1, // Opcode: CMPU_EQ_QB -/* 11428 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11447 -/* 11432 */ MCD_OPC_CheckPredicate, 12, 242, 8, // Skip to: 13726 -/* 11436 */ MCD_OPC_CheckField, 11, 5, 0, 236, 8, // Skip to: 13726 -/* 11442 */ MCD_OPC_Decode, 163, 3, 198, 1, // Opcode: CMPU_LT_QB -/* 11447 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 11466 -/* 11451 */ MCD_OPC_CheckPredicate, 12, 223, 8, // Skip to: 13726 -/* 11455 */ MCD_OPC_CheckField, 11, 5, 0, 217, 8, // Skip to: 13726 -/* 11461 */ MCD_OPC_Decode, 162, 3, 198, 1, // Opcode: CMPU_LE_QB -/* 11466 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11479 -/* 11470 */ MCD_OPC_CheckPredicate, 12, 204, 8, // Skip to: 13726 -/* 11474 */ MCD_OPC_Decode, 162, 10, 195, 1, // Opcode: PICK_QB -/* 11479 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11492 -/* 11483 */ MCD_OPC_CheckPredicate, 12, 191, 8, // Skip to: 13726 -/* 11487 */ MCD_OPC_Decode, 158, 3, 197, 1, // Opcode: CMPGU_EQ_QB -/* 11492 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11505 -/* 11496 */ MCD_OPC_CheckPredicate, 12, 178, 8, // Skip to: 13726 -/* 11500 */ MCD_OPC_Decode, 160, 3, 197, 1, // Opcode: CMPGU_LT_QB -/* 11505 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11518 -/* 11509 */ MCD_OPC_CheckPredicate, 12, 165, 8, // Skip to: 13726 -/* 11513 */ MCD_OPC_Decode, 159, 3, 197, 1, // Opcode: CMPGU_LE_QB -/* 11518 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 11537 -/* 11522 */ MCD_OPC_CheckPredicate, 12, 152, 8, // Skip to: 13726 -/* 11526 */ MCD_OPC_CheckField, 11, 5, 0, 146, 8, // Skip to: 13726 -/* 11532 */ MCD_OPC_Decode, 165, 3, 198, 1, // Opcode: CMP_EQ_PH -/* 11537 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 11556 -/* 11541 */ MCD_OPC_CheckPredicate, 12, 133, 8, // Skip to: 13726 -/* 11545 */ MCD_OPC_CheckField, 11, 5, 0, 127, 8, // Skip to: 13726 -/* 11551 */ MCD_OPC_Decode, 173, 3, 198, 1, // Opcode: CMP_LT_PH -/* 11556 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 11575 -/* 11560 */ MCD_OPC_CheckPredicate, 12, 114, 8, // Skip to: 13726 -/* 11564 */ MCD_OPC_CheckField, 11, 5, 0, 108, 8, // Skip to: 13726 -/* 11570 */ MCD_OPC_Decode, 170, 3, 198, 1, // Opcode: CMP_LE_PH -/* 11575 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11588 -/* 11579 */ MCD_OPC_CheckPredicate, 12, 95, 8, // Skip to: 13726 -/* 11583 */ MCD_OPC_Decode, 161, 10, 195, 1, // Opcode: PICK_PH -/* 11588 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11601 -/* 11592 */ MCD_OPC_CheckPredicate, 12, 82, 8, // Skip to: 13726 -/* 11596 */ MCD_OPC_Decode, 176, 10, 195, 1, // Opcode: PRECRQ_QB_PH -/* 11601 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11614 -/* 11605 */ MCD_OPC_CheckPredicate, 30, 69, 8, // Skip to: 13726 -/* 11609 */ MCD_OPC_Decode, 178, 10, 195, 1, // Opcode: PRECR_QB_PH -/* 11614 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11627 -/* 11618 */ MCD_OPC_CheckPredicate, 12, 56, 8, // Skip to: 13726 -/* 11622 */ MCD_OPC_Decode, 146, 10, 195, 1, // Opcode: PACKRL_PH -/* 11627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11640 -/* 11631 */ MCD_OPC_CheckPredicate, 12, 43, 8, // Skip to: 13726 -/* 11635 */ MCD_OPC_Decode, 174, 10, 195, 1, // Opcode: PRECRQU_S_QB_PH -/* 11640 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11653 -/* 11644 */ MCD_OPC_CheckPredicate, 12, 30, 8, // Skip to: 13726 -/* 11648 */ MCD_OPC_Decode, 175, 10, 199, 1, // Opcode: PRECRQ_PH_W -/* 11653 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11666 -/* 11657 */ MCD_OPC_CheckPredicate, 12, 17, 8, // Skip to: 13726 -/* 11661 */ MCD_OPC_Decode, 177, 10, 199, 1, // Opcode: PRECRQ_RS_PH_W -/* 11666 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 11679 -/* 11670 */ MCD_OPC_CheckPredicate, 30, 4, 8, // Skip to: 13726 -/* 11674 */ MCD_OPC_Decode, 155, 3, 197, 1, // Opcode: CMPGDU_EQ_QB -/* 11679 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11692 -/* 11683 */ MCD_OPC_CheckPredicate, 30, 247, 7, // Skip to: 13726 -/* 11687 */ MCD_OPC_Decode, 157, 3, 197, 1, // Opcode: CMPGDU_LT_QB -/* 11692 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 11705 -/* 11696 */ MCD_OPC_CheckPredicate, 30, 234, 7, // Skip to: 13726 -/* 11700 */ MCD_OPC_Decode, 156, 3, 197, 1, // Opcode: CMPGDU_LE_QB -/* 11705 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11718 -/* 11709 */ MCD_OPC_CheckPredicate, 30, 221, 7, // Skip to: 13726 -/* 11713 */ MCD_OPC_Decode, 179, 10, 200, 1, // Opcode: PRECR_SRA_PH_W -/* 11718 */ MCD_OPC_FilterValue, 31, 212, 7, // Skip to: 13726 -/* 11722 */ MCD_OPC_CheckPredicate, 30, 208, 7, // Skip to: 13726 -/* 11726 */ MCD_OPC_Decode, 180, 10, 200, 1, // Opcode: PRECR_SRA_R_PH_W -/* 11731 */ MCD_OPC_FilterValue, 18, 74, 1, // Skip to: 12065 -/* 11735 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11738 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11756 -/* 11742 */ MCD_OPC_CheckPredicate, 30, 188, 7, // Skip to: 13726 -/* 11746 */ MCD_OPC_CheckField, 21, 5, 0, 182, 7, // Skip to: 13726 -/* 11752 */ MCD_OPC_Decode, 23, 201, 1, // Opcode: ABSQ_S_QB -/* 11756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11769 -/* 11760 */ MCD_OPC_CheckPredicate, 12, 170, 7, // Skip to: 13726 -/* 11764 */ MCD_OPC_Decode, 244, 10, 202, 1, // Opcode: REPL_QB -/* 11769 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 11788 -/* 11773 */ MCD_OPC_CheckPredicate, 12, 157, 7, // Skip to: 13726 -/* 11777 */ MCD_OPC_CheckField, 21, 5, 0, 151, 7, // Skip to: 13726 -/* 11783 */ MCD_OPC_Decode, 242, 10, 203, 1, // Opcode: REPLV_QB -/* 11788 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 11807 -/* 11792 */ MCD_OPC_CheckPredicate, 12, 138, 7, // Skip to: 13726 -/* 11796 */ MCD_OPC_CheckField, 21, 5, 0, 132, 7, // Skip to: 13726 -/* 11802 */ MCD_OPC_Decode, 164, 10, 201, 1, // Opcode: PRECEQU_PH_QBL -/* 11807 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 11826 -/* 11811 */ MCD_OPC_CheckPredicate, 12, 119, 7, // Skip to: 13726 -/* 11815 */ MCD_OPC_CheckField, 21, 5, 0, 113, 7, // Skip to: 13726 -/* 11821 */ MCD_OPC_Decode, 166, 10, 201, 1, // Opcode: PRECEQU_PH_QBR -/* 11826 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 11845 -/* 11830 */ MCD_OPC_CheckPredicate, 12, 100, 7, // Skip to: 13726 -/* 11834 */ MCD_OPC_CheckField, 21, 5, 0, 94, 7, // Skip to: 13726 -/* 11840 */ MCD_OPC_Decode, 165, 10, 201, 1, // Opcode: PRECEQU_PH_QBLA -/* 11845 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 11864 -/* 11849 */ MCD_OPC_CheckPredicate, 12, 81, 7, // Skip to: 13726 -/* 11853 */ MCD_OPC_CheckField, 21, 5, 0, 75, 7, // Skip to: 13726 -/* 11859 */ MCD_OPC_Decode, 167, 10, 201, 1, // Opcode: PRECEQU_PH_QBRA -/* 11864 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 11882 -/* 11868 */ MCD_OPC_CheckPredicate, 12, 62, 7, // Skip to: 13726 -/* 11872 */ MCD_OPC_CheckField, 21, 5, 0, 56, 7, // Skip to: 13726 -/* 11878 */ MCD_OPC_Decode, 22, 201, 1, // Opcode: ABSQ_S_PH -/* 11882 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11895 -/* 11886 */ MCD_OPC_CheckPredicate, 12, 44, 7, // Skip to: 13726 -/* 11890 */ MCD_OPC_Decode, 243, 10, 202, 1, // Opcode: REPL_PH -/* 11895 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 11914 -/* 11899 */ MCD_OPC_CheckPredicate, 12, 31, 7, // Skip to: 13726 -/* 11903 */ MCD_OPC_CheckField, 21, 5, 0, 25, 7, // Skip to: 13726 -/* 11909 */ MCD_OPC_Decode, 241, 10, 203, 1, // Opcode: REPLV_PH -/* 11914 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11933 -/* 11918 */ MCD_OPC_CheckPredicate, 12, 12, 7, // Skip to: 13726 -/* 11922 */ MCD_OPC_CheckField, 21, 5, 0, 6, 7, // Skip to: 13726 -/* 11928 */ MCD_OPC_Decode, 168, 10, 204, 1, // Opcode: PRECEQ_W_PHL -/* 11933 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 11952 -/* 11937 */ MCD_OPC_CheckPredicate, 12, 249, 6, // Skip to: 13726 -/* 11941 */ MCD_OPC_CheckField, 21, 5, 0, 243, 6, // Skip to: 13726 -/* 11947 */ MCD_OPC_Decode, 169, 10, 204, 1, // Opcode: PRECEQ_W_PHR -/* 11952 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 11970 -/* 11956 */ MCD_OPC_CheckPredicate, 12, 230, 6, // Skip to: 13726 -/* 11960 */ MCD_OPC_CheckField, 21, 5, 0, 224, 6, // Skip to: 13726 -/* 11966 */ MCD_OPC_Decode, 24, 205, 1, // Opcode: ABSQ_S_W -/* 11970 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 11989 -/* 11974 */ MCD_OPC_CheckPredicate, 12, 212, 6, // Skip to: 13726 -/* 11978 */ MCD_OPC_CheckField, 21, 5, 0, 206, 6, // Skip to: 13726 -/* 11984 */ MCD_OPC_Decode, 249, 1, 205, 1, // Opcode: BITREV -/* 11989 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 12008 -/* 11993 */ MCD_OPC_CheckPredicate, 12, 193, 6, // Skip to: 13726 -/* 11997 */ MCD_OPC_CheckField, 21, 5, 0, 187, 6, // Skip to: 13726 -/* 12003 */ MCD_OPC_Decode, 170, 10, 201, 1, // Opcode: PRECEU_PH_QBL -/* 12008 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 12027 -/* 12012 */ MCD_OPC_CheckPredicate, 12, 174, 6, // Skip to: 13726 -/* 12016 */ MCD_OPC_CheckField, 21, 5, 0, 168, 6, // Skip to: 13726 -/* 12022 */ MCD_OPC_Decode, 172, 10, 201, 1, // Opcode: PRECEU_PH_QBR -/* 12027 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 12046 -/* 12031 */ MCD_OPC_CheckPredicate, 12, 155, 6, // Skip to: 13726 -/* 12035 */ MCD_OPC_CheckField, 21, 5, 0, 149, 6, // Skip to: 13726 -/* 12041 */ MCD_OPC_Decode, 171, 10, 201, 1, // Opcode: PRECEU_PH_QBLA -/* 12046 */ MCD_OPC_FilterValue, 31, 140, 6, // Skip to: 13726 -/* 12050 */ MCD_OPC_CheckPredicate, 12, 136, 6, // Skip to: 13726 -/* 12054 */ MCD_OPC_CheckField, 21, 5, 0, 130, 6, // Skip to: 13726 -/* 12060 */ MCD_OPC_Decode, 173, 10, 201, 1, // Opcode: PRECEU_PH_QBRA -/* 12065 */ MCD_OPC_FilterValue, 19, 31, 1, // Skip to: 12356 -/* 12069 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12072 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12085 -/* 12076 */ MCD_OPC_CheckPredicate, 12, 110, 6, // Skip to: 13726 -/* 12080 */ MCD_OPC_Decode, 199, 11, 206, 1, // Opcode: SHLL_QB -/* 12085 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12098 -/* 12089 */ MCD_OPC_CheckPredicate, 12, 97, 6, // Skip to: 13726 -/* 12093 */ MCD_OPC_Decode, 215, 11, 206, 1, // Opcode: SHRL_QB -/* 12098 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12111 -/* 12102 */ MCD_OPC_CheckPredicate, 12, 84, 6, // Skip to: 13726 -/* 12106 */ MCD_OPC_Decode, 195, 11, 207, 1, // Opcode: SHLLV_QB -/* 12111 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12124 -/* 12115 */ MCD_OPC_CheckPredicate, 12, 71, 6, // Skip to: 13726 -/* 12119 */ MCD_OPC_Decode, 213, 11, 207, 1, // Opcode: SHRLV_QB -/* 12124 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12137 -/* 12128 */ MCD_OPC_CheckPredicate, 30, 58, 6, // Skip to: 13726 -/* 12132 */ MCD_OPC_Decode, 208, 11, 206, 1, // Opcode: SHRA_QB -/* 12137 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 12150 -/* 12141 */ MCD_OPC_CheckPredicate, 30, 45, 6, // Skip to: 13726 -/* 12145 */ MCD_OPC_Decode, 210, 11, 206, 1, // Opcode: SHRA_R_QB -/* 12150 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 12163 -/* 12154 */ MCD_OPC_CheckPredicate, 30, 32, 6, // Skip to: 13726 -/* 12158 */ MCD_OPC_Decode, 203, 11, 207, 1, // Opcode: SHRAV_QB -/* 12163 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 12176 -/* 12167 */ MCD_OPC_CheckPredicate, 30, 19, 6, // Skip to: 13726 -/* 12171 */ MCD_OPC_Decode, 205, 11, 207, 1, // Opcode: SHRAV_R_QB -/* 12176 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 12189 -/* 12180 */ MCD_OPC_CheckPredicate, 12, 6, 6, // Skip to: 13726 -/* 12184 */ MCD_OPC_Decode, 198, 11, 206, 1, // Opcode: SHLL_PH -/* 12189 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12202 -/* 12193 */ MCD_OPC_CheckPredicate, 12, 249, 5, // Skip to: 13726 -/* 12197 */ MCD_OPC_Decode, 207, 11, 206, 1, // Opcode: SHRA_PH -/* 12202 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 12215 -/* 12206 */ MCD_OPC_CheckPredicate, 12, 236, 5, // Skip to: 13726 -/* 12210 */ MCD_OPC_Decode, 194, 11, 207, 1, // Opcode: SHLLV_PH -/* 12215 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12228 -/* 12219 */ MCD_OPC_CheckPredicate, 12, 223, 5, // Skip to: 13726 -/* 12223 */ MCD_OPC_Decode, 202, 11, 207, 1, // Opcode: SHRAV_PH -/* 12228 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12241 -/* 12232 */ MCD_OPC_CheckPredicate, 12, 210, 5, // Skip to: 13726 -/* 12236 */ MCD_OPC_Decode, 200, 11, 206, 1, // Opcode: SHLL_S_PH -/* 12241 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 12254 -/* 12245 */ MCD_OPC_CheckPredicate, 12, 197, 5, // Skip to: 13726 -/* 12249 */ MCD_OPC_Decode, 209, 11, 206, 1, // Opcode: SHRA_R_PH -/* 12254 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12267 -/* 12258 */ MCD_OPC_CheckPredicate, 12, 184, 5, // Skip to: 13726 -/* 12262 */ MCD_OPC_Decode, 196, 11, 207, 1, // Opcode: SHLLV_S_PH -/* 12267 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 12280 -/* 12271 */ MCD_OPC_CheckPredicate, 12, 171, 5, // Skip to: 13726 -/* 12275 */ MCD_OPC_Decode, 204, 11, 207, 1, // Opcode: SHRAV_R_PH -/* 12280 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 12293 -/* 12284 */ MCD_OPC_CheckPredicate, 12, 158, 5, // Skip to: 13726 -/* 12288 */ MCD_OPC_Decode, 201, 11, 208, 1, // Opcode: SHLL_S_W -/* 12293 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 12306 -/* 12297 */ MCD_OPC_CheckPredicate, 12, 145, 5, // Skip to: 13726 -/* 12301 */ MCD_OPC_Decode, 211, 11, 208, 1, // Opcode: SHRA_R_W -/* 12306 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12318 -/* 12310 */ MCD_OPC_CheckPredicate, 12, 132, 5, // Skip to: 13726 -/* 12314 */ MCD_OPC_Decode, 197, 11, 36, // Opcode: SHLLV_S_W -/* 12318 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 12330 -/* 12322 */ MCD_OPC_CheckPredicate, 12, 120, 5, // Skip to: 13726 -/* 12326 */ MCD_OPC_Decode, 206, 11, 36, // Opcode: SHRAV_R_W -/* 12330 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 12343 -/* 12334 */ MCD_OPC_CheckPredicate, 30, 108, 5, // Skip to: 13726 -/* 12338 */ MCD_OPC_Decode, 214, 11, 206, 1, // Opcode: SHRL_PH -/* 12343 */ MCD_OPC_FilterValue, 27, 99, 5, // Skip to: 13726 -/* 12347 */ MCD_OPC_CheckPredicate, 30, 95, 5, // Skip to: 13726 -/* 12351 */ MCD_OPC_Decode, 212, 11, 207, 1, // Opcode: SHRLV_PH -/* 12356 */ MCD_OPC_FilterValue, 24, 199, 0, // Skip to: 12559 -/* 12360 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12363 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12375 -/* 12367 */ MCD_OPC_CheckPredicate, 30, 75, 5, // Skip to: 13726 -/* 12371 */ MCD_OPC_Decode, 53, 195, 1, // Opcode: ADDUH_QB -/* 12375 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12388 -/* 12379 */ MCD_OPC_CheckPredicate, 30, 63, 5, // Skip to: 13726 -/* 12383 */ MCD_OPC_Decode, 215, 12, 195, 1, // Opcode: SUBUH_QB -/* 12388 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12400 -/* 12392 */ MCD_OPC_CheckPredicate, 30, 50, 5, // Skip to: 13726 -/* 12396 */ MCD_OPC_Decode, 54, 195, 1, // Opcode: ADDUH_R_QB -/* 12400 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12413 -/* 12404 */ MCD_OPC_CheckPredicate, 30, 38, 5, // Skip to: 13726 -/* 12408 */ MCD_OPC_Decode, 216, 12, 195, 1, // Opcode: SUBUH_R_QB -/* 12413 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12425 -/* 12417 */ MCD_OPC_CheckPredicate, 30, 25, 5, // Skip to: 13726 -/* 12421 */ MCD_OPC_Decode, 32, 195, 1, // Opcode: ADDQH_PH -/* 12425 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12438 -/* 12429 */ MCD_OPC_CheckPredicate, 30, 13, 5, // Skip to: 13726 -/* 12433 */ MCD_OPC_Decode, 191, 12, 195, 1, // Opcode: SUBQH_PH -/* 12438 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12450 -/* 12442 */ MCD_OPC_CheckPredicate, 30, 0, 5, // Skip to: 13726 -/* 12446 */ MCD_OPC_Decode, 33, 195, 1, // Opcode: ADDQH_R_PH -/* 12450 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12463 -/* 12454 */ MCD_OPC_CheckPredicate, 30, 244, 4, // Skip to: 13726 -/* 12458 */ MCD_OPC_Decode, 192, 12, 195, 1, // Opcode: SUBQH_R_PH -/* 12463 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12476 -/* 12467 */ MCD_OPC_CheckPredicate, 30, 231, 4, // Skip to: 13726 -/* 12471 */ MCD_OPC_Decode, 218, 9, 195, 1, // Opcode: MUL_PH -/* 12476 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12489 -/* 12480 */ MCD_OPC_CheckPredicate, 30, 218, 4, // Skip to: 13726 -/* 12484 */ MCD_OPC_Decode, 222, 9, 195, 1, // Opcode: MUL_S_PH -/* 12489 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 12500 -/* 12493 */ MCD_OPC_CheckPredicate, 30, 205, 4, // Skip to: 13726 -/* 12497 */ MCD_OPC_Decode, 35, 35, // Opcode: ADDQH_W -/* 12500 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 12512 -/* 12504 */ MCD_OPC_CheckPredicate, 30, 194, 4, // Skip to: 13726 -/* 12508 */ MCD_OPC_Decode, 194, 12, 35, // Opcode: SUBQH_W -/* 12512 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 12523 -/* 12516 */ MCD_OPC_CheckPredicate, 30, 182, 4, // Skip to: 13726 -/* 12520 */ MCD_OPC_Decode, 34, 35, // Opcode: ADDQH_R_W -/* 12523 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 12535 -/* 12527 */ MCD_OPC_CheckPredicate, 30, 171, 4, // Skip to: 13726 -/* 12531 */ MCD_OPC_Decode, 193, 12, 35, // Opcode: SUBQH_R_W -/* 12535 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12547 -/* 12539 */ MCD_OPC_CheckPredicate, 30, 159, 4, // Skip to: 13726 -/* 12543 */ MCD_OPC_Decode, 201, 9, 35, // Opcode: MULQ_S_W -/* 12547 */ MCD_OPC_FilterValue, 23, 151, 4, // Skip to: 13726 -/* 12551 */ MCD_OPC_CheckPredicate, 30, 147, 4, // Skip to: 13726 -/* 12555 */ MCD_OPC_Decode, 199, 9, 35, // Opcode: MULQ_RS_W -/* 12559 */ MCD_OPC_FilterValue, 32, 60, 0, // Skip to: 12623 -/* 12563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12566 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12585 -/* 12570 */ MCD_OPC_CheckPredicate, 6, 128, 4, // Skip to: 13726 -/* 12574 */ MCD_OPC_CheckField, 21, 5, 0, 122, 4, // Skip to: 13726 -/* 12580 */ MCD_OPC_Decode, 234, 13, 205, 1, // Opcode: WSBH -/* 12585 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 12604 -/* 12589 */ MCD_OPC_CheckPredicate, 6, 109, 4, // Skip to: 13726 -/* 12593 */ MCD_OPC_CheckField, 21, 5, 0, 103, 4, // Skip to: 13726 -/* 12599 */ MCD_OPC_Decode, 168, 11, 205, 1, // Opcode: SEB -/* 12604 */ MCD_OPC_FilterValue, 24, 94, 4, // Skip to: 13726 -/* 12608 */ MCD_OPC_CheckPredicate, 6, 90, 4, // Skip to: 13726 -/* 12612 */ MCD_OPC_CheckField, 21, 5, 0, 84, 4, // Skip to: 13726 -/* 12618 */ MCD_OPC_Decode, 171, 11, 205, 1, // Opcode: SEH -/* 12623 */ MCD_OPC_FilterValue, 48, 143, 1, // Skip to: 13026 -/* 12627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 12630 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12648 -/* 12634 */ MCD_OPC_CheckPredicate, 30, 64, 4, // Skip to: 13726 -/* 12638 */ MCD_OPC_CheckField, 13, 3, 0, 58, 4, // Skip to: 13726 -/* 12644 */ MCD_OPC_Decode, 230, 4, 116, // Opcode: DPA_W_PH -/* 12648 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12666 -/* 12652 */ MCD_OPC_CheckPredicate, 30, 46, 4, // Skip to: 13726 -/* 12656 */ MCD_OPC_CheckField, 13, 3, 0, 40, 4, // Skip to: 13726 -/* 12662 */ MCD_OPC_Decode, 245, 4, 116, // Opcode: DPS_W_PH -/* 12666 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12684 -/* 12670 */ MCD_OPC_CheckPredicate, 30, 28, 4, // Skip to: 13726 -/* 12674 */ MCD_OPC_CheckField, 13, 3, 0, 22, 4, // Skip to: 13726 -/* 12680 */ MCD_OPC_Decode, 205, 9, 116, // Opcode: MULSA_W_PH -/* 12684 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12702 -/* 12688 */ MCD_OPC_CheckPredicate, 12, 10, 4, // Skip to: 13726 -/* 12692 */ MCD_OPC_CheckField, 13, 3, 0, 4, 4, // Skip to: 13726 -/* 12698 */ MCD_OPC_Decode, 227, 4, 116, // Opcode: DPAU_H_QBL -/* 12702 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12720 -/* 12706 */ MCD_OPC_CheckPredicate, 12, 248, 3, // Skip to: 13726 -/* 12710 */ MCD_OPC_CheckField, 13, 3, 0, 242, 3, // Skip to: 13726 -/* 12716 */ MCD_OPC_Decode, 226, 4, 116, // Opcode: DPAQ_S_W_PH -/* 12720 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12738 -/* 12724 */ MCD_OPC_CheckPredicate, 12, 230, 3, // Skip to: 13726 -/* 12728 */ MCD_OPC_CheckField, 13, 3, 0, 224, 3, // Skip to: 13726 -/* 12734 */ MCD_OPC_Decode, 235, 4, 116, // Opcode: DPSQ_S_W_PH -/* 12738 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 12756 -/* 12742 */ MCD_OPC_CheckPredicate, 12, 212, 3, // Skip to: 13726 -/* 12746 */ MCD_OPC_CheckField, 13, 3, 0, 206, 3, // Skip to: 13726 -/* 12752 */ MCD_OPC_Decode, 204, 9, 116, // Opcode: MULSAQ_S_W_PH -/* 12756 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 12774 -/* 12760 */ MCD_OPC_CheckPredicate, 12, 194, 3, // Skip to: 13726 -/* 12764 */ MCD_OPC_CheckField, 13, 3, 0, 188, 3, // Skip to: 13726 -/* 12770 */ MCD_OPC_Decode, 228, 4, 116, // Opcode: DPAU_H_QBR -/* 12774 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12792 -/* 12778 */ MCD_OPC_CheckPredicate, 30, 176, 3, // Skip to: 13726 -/* 12782 */ MCD_OPC_CheckField, 13, 3, 0, 170, 3, // Skip to: 13726 -/* 12788 */ MCD_OPC_Decode, 229, 4, 116, // Opcode: DPAX_W_PH -/* 12792 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 12810 -/* 12796 */ MCD_OPC_CheckPredicate, 30, 158, 3, // Skip to: 13726 -/* 12800 */ MCD_OPC_CheckField, 13, 3, 0, 152, 3, // Skip to: 13726 -/* 12806 */ MCD_OPC_Decode, 244, 4, 116, // Opcode: DPSX_W_PH -/* 12810 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12828 -/* 12814 */ MCD_OPC_CheckPredicate, 12, 140, 3, // Skip to: 13726 -/* 12818 */ MCD_OPC_CheckField, 13, 3, 0, 134, 3, // Skip to: 13726 -/* 12824 */ MCD_OPC_Decode, 242, 4, 116, // Opcode: DPSU_H_QBL -/* 12828 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12846 -/* 12832 */ MCD_OPC_CheckPredicate, 12, 122, 3, // Skip to: 13726 -/* 12836 */ MCD_OPC_CheckField, 13, 3, 0, 116, 3, // Skip to: 13726 -/* 12842 */ MCD_OPC_Decode, 225, 4, 116, // Opcode: DPAQ_SA_L_W -/* 12846 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12864 -/* 12850 */ MCD_OPC_CheckPredicate, 12, 104, 3, // Skip to: 13726 -/* 12854 */ MCD_OPC_CheckField, 13, 3, 0, 98, 3, // Skip to: 13726 -/* 12860 */ MCD_OPC_Decode, 234, 4, 116, // Opcode: DPSQ_SA_L_W -/* 12864 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 12882 -/* 12868 */ MCD_OPC_CheckPredicate, 12, 86, 3, // Skip to: 13726 -/* 12872 */ MCD_OPC_CheckField, 13, 3, 0, 80, 3, // Skip to: 13726 -/* 12878 */ MCD_OPC_Decode, 243, 4, 116, // Opcode: DPSU_H_QBR -/* 12882 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 12900 -/* 12886 */ MCD_OPC_CheckPredicate, 12, 68, 3, // Skip to: 13726 -/* 12890 */ MCD_OPC_CheckField, 13, 3, 0, 62, 3, // Skip to: 13726 -/* 12896 */ MCD_OPC_Decode, 151, 8, 116, // Opcode: MAQ_SA_W_PHL -/* 12900 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 12918 -/* 12904 */ MCD_OPC_CheckPredicate, 12, 50, 3, // Skip to: 13726 -/* 12908 */ MCD_OPC_CheckField, 13, 3, 0, 44, 3, // Skip to: 13726 -/* 12914 */ MCD_OPC_Decode, 152, 8, 116, // Opcode: MAQ_SA_W_PHR -/* 12918 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 12936 -/* 12922 */ MCD_OPC_CheckPredicate, 12, 32, 3, // Skip to: 13726 -/* 12926 */ MCD_OPC_CheckField, 13, 3, 0, 26, 3, // Skip to: 13726 -/* 12932 */ MCD_OPC_Decode, 153, 8, 116, // Opcode: MAQ_S_W_PHL -/* 12936 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 12954 -/* 12940 */ MCD_OPC_CheckPredicate, 12, 14, 3, // Skip to: 13726 -/* 12944 */ MCD_OPC_CheckField, 13, 3, 0, 8, 3, // Skip to: 13726 -/* 12950 */ MCD_OPC_Decode, 154, 8, 116, // Opcode: MAQ_S_W_PHR -/* 12954 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 12972 -/* 12958 */ MCD_OPC_CheckPredicate, 30, 252, 2, // Skip to: 13726 -/* 12962 */ MCD_OPC_CheckField, 13, 3, 0, 246, 2, // Skip to: 13726 -/* 12968 */ MCD_OPC_Decode, 224, 4, 116, // Opcode: DPAQX_S_W_PH -/* 12972 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 12990 -/* 12976 */ MCD_OPC_CheckPredicate, 30, 234, 2, // Skip to: 13726 -/* 12980 */ MCD_OPC_CheckField, 13, 3, 0, 228, 2, // Skip to: 13726 -/* 12986 */ MCD_OPC_Decode, 233, 4, 116, // Opcode: DPSQX_S_W_PH -/* 12990 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 13008 -/* 12994 */ MCD_OPC_CheckPredicate, 30, 216, 2, // Skip to: 13726 -/* 12998 */ MCD_OPC_CheckField, 13, 3, 0, 210, 2, // Skip to: 13726 -/* 13004 */ MCD_OPC_Decode, 223, 4, 116, // Opcode: DPAQX_SA_W_PH -/* 13008 */ MCD_OPC_FilterValue, 27, 202, 2, // Skip to: 13726 -/* 13012 */ MCD_OPC_CheckPredicate, 30, 198, 2, // Skip to: 13726 -/* 13016 */ MCD_OPC_CheckField, 13, 3, 0, 192, 2, // Skip to: 13726 -/* 13022 */ MCD_OPC_Decode, 232, 4, 116, // Opcode: DPSQX_SA_W_PH -/* 13026 */ MCD_OPC_FilterValue, 49, 41, 0, // Skip to: 13071 -/* 13030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 13033 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13045 -/* 13037 */ MCD_OPC_CheckPredicate, 30, 173, 2, // Skip to: 13726 -/* 13041 */ MCD_OPC_Decode, 96, 209, 1, // Opcode: APPEND -/* 13045 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13058 -/* 13049 */ MCD_OPC_CheckPredicate, 30, 161, 2, // Skip to: 13726 -/* 13053 */ MCD_OPC_Decode, 184, 10, 209, 1, // Opcode: PREPEND -/* 13058 */ MCD_OPC_FilterValue, 16, 152, 2, // Skip to: 13726 -/* 13062 */ MCD_OPC_CheckPredicate, 30, 148, 2, // Skip to: 13726 -/* 13066 */ MCD_OPC_Decode, 169, 1, 209, 1, // Opcode: BALIGN -/* 13071 */ MCD_OPC_FilterValue, 56, 58, 1, // Skip to: 13389 -/* 13075 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 13078 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13097 -/* 13082 */ MCD_OPC_CheckPredicate, 12, 128, 2, // Skip to: 13726 -/* 13086 */ MCD_OPC_CheckField, 13, 3, 0, 122, 2, // Skip to: 13726 -/* 13092 */ MCD_OPC_Decode, 157, 5, 210, 1, // Opcode: EXTR_W -/* 13097 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 13116 -/* 13101 */ MCD_OPC_CheckPredicate, 12, 109, 2, // Skip to: 13726 -/* 13105 */ MCD_OPC_CheckField, 13, 3, 0, 103, 2, // Skip to: 13726 -/* 13111 */ MCD_OPC_Decode, 153, 5, 211, 1, // Opcode: EXTRV_W -/* 13116 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 13135 -/* 13120 */ MCD_OPC_CheckPredicate, 12, 90, 2, // Skip to: 13726 -/* 13124 */ MCD_OPC_CheckField, 13, 3, 0, 84, 2, // Skip to: 13726 -/* 13130 */ MCD_OPC_Decode, 146, 5, 210, 1, // Opcode: EXTP -/* 13135 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 13154 -/* 13139 */ MCD_OPC_CheckPredicate, 12, 71, 2, // Skip to: 13726 -/* 13143 */ MCD_OPC_CheckField, 13, 3, 0, 65, 2, // Skip to: 13726 -/* 13149 */ MCD_OPC_Decode, 149, 5, 211, 1, // Opcode: EXTPV -/* 13154 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 13173 -/* 13158 */ MCD_OPC_CheckPredicate, 12, 52, 2, // Skip to: 13726 -/* 13162 */ MCD_OPC_CheckField, 13, 3, 0, 46, 2, // Skip to: 13726 -/* 13168 */ MCD_OPC_Decode, 155, 5, 210, 1, // Opcode: EXTR_R_W -/* 13173 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 13192 -/* 13177 */ MCD_OPC_CheckPredicate, 12, 33, 2, // Skip to: 13726 -/* 13181 */ MCD_OPC_CheckField, 13, 3, 0, 27, 2, // Skip to: 13726 -/* 13187 */ MCD_OPC_Decode, 151, 5, 211, 1, // Opcode: EXTRV_R_W -/* 13192 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 13211 -/* 13196 */ MCD_OPC_CheckPredicate, 12, 14, 2, // Skip to: 13726 -/* 13200 */ MCD_OPC_CheckField, 13, 3, 0, 8, 2, // Skip to: 13726 -/* 13206 */ MCD_OPC_Decode, 154, 5, 210, 1, // Opcode: EXTR_RS_W -/* 13211 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 13230 -/* 13215 */ MCD_OPC_CheckPredicate, 12, 251, 1, // Skip to: 13726 -/* 13219 */ MCD_OPC_CheckField, 13, 3, 0, 245, 1, // Skip to: 13726 -/* 13225 */ MCD_OPC_Decode, 150, 5, 211, 1, // Opcode: EXTRV_RS_W -/* 13230 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 13249 -/* 13234 */ MCD_OPC_CheckPredicate, 12, 232, 1, // Skip to: 13726 -/* 13238 */ MCD_OPC_CheckField, 13, 3, 0, 226, 1, // Skip to: 13726 -/* 13244 */ MCD_OPC_Decode, 147, 5, 210, 1, // Opcode: EXTPDP -/* 13249 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 13268 -/* 13253 */ MCD_OPC_CheckPredicate, 12, 213, 1, // Skip to: 13726 -/* 13257 */ MCD_OPC_CheckField, 13, 3, 0, 207, 1, // Skip to: 13726 -/* 13263 */ MCD_OPC_Decode, 148, 5, 211, 1, // Opcode: EXTPDPV -/* 13268 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 13287 -/* 13272 */ MCD_OPC_CheckPredicate, 12, 194, 1, // Skip to: 13726 -/* 13276 */ MCD_OPC_CheckField, 13, 3, 0, 188, 1, // Skip to: 13726 -/* 13282 */ MCD_OPC_Decode, 156, 5, 210, 1, // Opcode: EXTR_S_H -/* 13287 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 13306 -/* 13291 */ MCD_OPC_CheckPredicate, 12, 175, 1, // Skip to: 13726 -/* 13295 */ MCD_OPC_CheckField, 13, 3, 0, 169, 1, // Skip to: 13726 -/* 13301 */ MCD_OPC_Decode, 152, 5, 211, 1, // Opcode: EXTRV_S_H -/* 13306 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 13319 -/* 13310 */ MCD_OPC_CheckPredicate, 12, 156, 1, // Skip to: 13726 -/* 13314 */ MCD_OPC_Decode, 237, 10, 212, 1, // Opcode: RDDSP -/* 13319 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 13332 -/* 13323 */ MCD_OPC_CheckPredicate, 12, 143, 1, // Skip to: 13726 -/* 13327 */ MCD_OPC_Decode, 233, 13, 213, 1, // Opcode: WRDSP -/* 13332 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 13351 -/* 13336 */ MCD_OPC_CheckPredicate, 12, 130, 1, // Skip to: 13726 -/* 13340 */ MCD_OPC_CheckField, 13, 7, 0, 124, 1, // Skip to: 13726 -/* 13346 */ MCD_OPC_Decode, 192, 11, 214, 1, // Opcode: SHILO -/* 13351 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 13370 -/* 13355 */ MCD_OPC_CheckPredicate, 12, 111, 1, // Skip to: 13726 -/* 13359 */ MCD_OPC_CheckField, 13, 8, 0, 105, 1, // Skip to: 13726 -/* 13365 */ MCD_OPC_Decode, 193, 11, 215, 1, // Opcode: SHILOV -/* 13370 */ MCD_OPC_FilterValue, 31, 96, 1, // Skip to: 13726 -/* 13374 */ MCD_OPC_CheckPredicate, 12, 92, 1, // Skip to: 13726 -/* 13378 */ MCD_OPC_CheckField, 13, 8, 0, 86, 1, // Skip to: 13726 -/* 13384 */ MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: MTHLIP -/* 13389 */ MCD_OPC_FilterValue, 59, 77, 1, // Skip to: 13726 -/* 13393 */ MCD_OPC_CheckPredicate, 5, 73, 1, // Skip to: 13726 -/* 13397 */ MCD_OPC_CheckField, 21, 5, 0, 67, 1, // Skip to: 13726 -/* 13403 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, // Skip to: 13726 -/* 13409 */ MCD_OPC_Decode, 238, 10, 216, 1, // Opcode: RDHWR -/* 13414 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 13427 -/* 13418 */ MCD_OPC_CheckPredicate, 5, 48, 1, // Skip to: 13726 -/* 13422 */ MCD_OPC_Decode, 153, 7, 217, 1, // Opcode: LB -/* 13427 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 13440 -/* 13431 */ MCD_OPC_CheckPredicate, 5, 35, 1, // Skip to: 13726 -/* 13435 */ MCD_OPC_Decode, 184, 7, 217, 1, // Opcode: LH -/* 13440 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 13453 -/* 13444 */ MCD_OPC_CheckPredicate, 11, 22, 1, // Skip to: 13726 -/* 13448 */ MCD_OPC_Decode, 222, 7, 217, 1, // Opcode: LWL -/* 13453 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 13466 -/* 13457 */ MCD_OPC_CheckPredicate, 1, 9, 1, // Skip to: 13726 -/* 13461 */ MCD_OPC_Decode, 213, 7, 217, 1, // Opcode: LW -/* 13466 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 13479 -/* 13470 */ MCD_OPC_CheckPredicate, 5, 252, 0, // Skip to: 13726 -/* 13474 */ MCD_OPC_Decode, 158, 7, 217, 1, // Opcode: LBu -/* 13479 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 13492 -/* 13483 */ MCD_OPC_CheckPredicate, 5, 239, 0, // Skip to: 13726 -/* 13487 */ MCD_OPC_Decode, 189, 7, 217, 1, // Opcode: LHu -/* 13492 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 13505 -/* 13496 */ MCD_OPC_CheckPredicate, 11, 226, 0, // Skip to: 13726 -/* 13500 */ MCD_OPC_Decode, 230, 7, 217, 1, // Opcode: LWR -/* 13505 */ MCD_OPC_FilterValue, 40, 9, 0, // Skip to: 13518 -/* 13509 */ MCD_OPC_CheckPredicate, 5, 213, 0, // Skip to: 13726 -/* 13513 */ MCD_OPC_Decode, 142, 11, 217, 1, // Opcode: SB -/* 13518 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 13531 -/* 13522 */ MCD_OPC_CheckPredicate, 5, 200, 0, // Skip to: 13726 -/* 13526 */ MCD_OPC_Decode, 186, 11, 217, 1, // Opcode: SH -/* 13531 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 13544 -/* 13535 */ MCD_OPC_CheckPredicate, 11, 187, 0, // Skip to: 13726 -/* 13539 */ MCD_OPC_Decode, 243, 12, 217, 1, // Opcode: SWL -/* 13544 */ MCD_OPC_FilterValue, 43, 9, 0, // Skip to: 13557 -/* 13548 */ MCD_OPC_CheckPredicate, 1, 174, 0, // Skip to: 13726 -/* 13552 */ MCD_OPC_Decode, 235, 12, 217, 1, // Opcode: SW -/* 13557 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 13570 -/* 13561 */ MCD_OPC_CheckPredicate, 11, 161, 0, // Skip to: 13726 -/* 13565 */ MCD_OPC_Decode, 250, 12, 217, 1, // Opcode: SWR -/* 13570 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 13583 -/* 13574 */ MCD_OPC_CheckPredicate, 31, 148, 0, // Skip to: 13726 -/* 13578 */ MCD_OPC_Decode, 220, 2, 218, 1, // Opcode: CACHE -/* 13583 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 13596 -/* 13587 */ MCD_OPC_CheckPredicate, 32, 135, 0, // Skip to: 13726 -/* 13591 */ MCD_OPC_Decode, 193, 7, 217, 1, // Opcode: LL -/* 13596 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 13609 -/* 13600 */ MCD_OPC_CheckPredicate, 5, 122, 0, // Skip to: 13726 -/* 13604 */ MCD_OPC_Decode, 216, 7, 219, 1, // Opcode: LWC1 -/* 13609 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 13622 -/* 13613 */ MCD_OPC_CheckPredicate, 33, 109, 0, // Skip to: 13726 -/* 13617 */ MCD_OPC_Decode, 218, 7, 220, 1, // Opcode: LWC2 -/* 13622 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 13635 -/* 13626 */ MCD_OPC_CheckPredicate, 31, 96, 0, // Skip to: 13726 -/* 13630 */ MCD_OPC_Decode, 181, 10, 218, 1, // Opcode: PREF -/* 13635 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 13648 -/* 13639 */ MCD_OPC_CheckPredicate, 34, 83, 0, // Skip to: 13726 -/* 13643 */ MCD_OPC_Decode, 162, 7, 219, 1, // Opcode: LDC1 -/* 13648 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 13661 -/* 13652 */ MCD_OPC_CheckPredicate, 35, 70, 0, // Skip to: 13726 -/* 13656 */ MCD_OPC_Decode, 165, 7, 220, 1, // Opcode: LDC2 -/* 13661 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 13674 -/* 13665 */ MCD_OPC_CheckPredicate, 32, 57, 0, // Skip to: 13726 -/* 13669 */ MCD_OPC_Decode, 146, 11, 217, 1, // Opcode: SC -/* 13674 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 13687 -/* 13678 */ MCD_OPC_CheckPredicate, 5, 44, 0, // Skip to: 13726 -/* 13682 */ MCD_OPC_Decode, 238, 12, 219, 1, // Opcode: SWC1 -/* 13687 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 13700 -/* 13691 */ MCD_OPC_CheckPredicate, 33, 31, 0, // Skip to: 13726 -/* 13695 */ MCD_OPC_Decode, 240, 12, 220, 1, // Opcode: SWC2 -/* 13700 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 13713 -/* 13704 */ MCD_OPC_CheckPredicate, 34, 18, 0, // Skip to: 13726 -/* 13708 */ MCD_OPC_Decode, 156, 11, 219, 1, // Opcode: SDC1 -/* 13713 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 13726 -/* 13717 */ MCD_OPC_CheckPredicate, 35, 5, 0, // Skip to: 13726 -/* 13721 */ MCD_OPC_Decode, 159, 11, 220, 1, // Opcode: SDC2 -/* 13726 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 101, + 4, + 0, // Skip to: 1133 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 79 + /* 16 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 29, + 67, + 0, // Skip to: 17205 + /* 24 */ MCD_OPC_ExtractField, + 6, + 15, // Inst{20-6} ... + /* 27 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 41 + /* 32 */ MCD_OPC_CheckPredicate, + 27, + 32, + 0, + 0, // Skip to: 69 + /* 37 */ MCD_OPC_Decode, + 193, + 20, + 0, // Opcode: SSNOP + /* 41 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 55 + /* 46 */ MCD_OPC_CheckPredicate, + 27, + 18, + 0, + 0, // Skip to: 69 + /* 51 */ MCD_OPC_Decode, + 222, + 11, + 0, // Opcode: EHB + /* 55 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 69 + /* 60 */ MCD_OPC_CheckPredicate, + 28, + 4, + 0, + 0, // Skip to: 69 + /* 65 */ MCD_OPC_Decode, + 235, + 17, + 0, // Opcode: PAUSE + /* 69 */ MCD_OPC_CheckPredicate, + 27, + 235, + 66, + 0, // Skip to: 17205 + /* 74 */ MCD_OPC_Decode, + 240, + 19, + 172, + 1, // Opcode: SLL + /* 79 */ MCD_OPC_FilterValue, + 1, + 47, + 0, + 0, // Skip to: 131 + /* 84 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 87 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 109 + /* 92 */ MCD_OPC_CheckPredicate, + 29, + 212, + 66, + 0, // Skip to: 17205 + /* 97 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 205, + 66, + 0, // Skip to: 17205 + /* 104 */ MCD_OPC_Decode, + 165, + 16, + 173, + 1, // Opcode: MOVF_I + /* 109 */ MCD_OPC_FilterValue, + 1, + 195, + 66, + 0, // Skip to: 17205 + /* 114 */ MCD_OPC_CheckPredicate, + 29, + 190, + 66, + 0, // Skip to: 17205 + /* 119 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 183, + 66, + 0, // Skip to: 17205 + /* 126 */ MCD_OPC_Decode, + 185, + 16, + 173, + 1, // Opcode: MOVT_I + /* 131 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 169 + /* 136 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 139 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 154 + /* 144 */ MCD_OPC_CheckPredicate, + 27, + 160, + 66, + 0, // Skip to: 17205 + /* 149 */ MCD_OPC_Decode, + 171, + 20, + 172, + 1, // Opcode: SRL + /* 154 */ MCD_OPC_FilterValue, + 1, + 150, + 66, + 0, // Skip to: 17205 + /* 159 */ MCD_OPC_CheckPredicate, + 28, + 145, + 66, + 0, // Skip to: 17205 + /* 164 */ MCD_OPC_Decode, + 201, + 18, + 172, + 1, // Opcode: ROTR + /* 169 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 191 + /* 174 */ MCD_OPC_CheckPredicate, + 27, + 130, + 66, + 0, // Skip to: 17205 + /* 179 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 123, + 66, + 0, // Skip to: 17205 + /* 186 */ MCD_OPC_Decode, + 151, + 20, + 172, + 1, // Opcode: SRA + /* 191 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 212 + /* 196 */ MCD_OPC_CheckPredicate, + 27, + 108, + 66, + 0, // Skip to: 17205 + /* 201 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 101, + 66, + 0, // Skip to: 17205 + /* 208 */ MCD_OPC_Decode, + 249, + 19, + 44, // Opcode: SLLV + /* 212 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 234 + /* 217 */ MCD_OPC_CheckPredicate, + 30, + 87, + 66, + 0, // Skip to: 17205 + /* 222 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 80, + 66, + 0, // Skip to: 17205 + /* 229 */ MCD_OPC_Decode, + 217, + 14, + 174, + 1, // Opcode: LSA + /* 234 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 270 + /* 239 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 242 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 256 + /* 247 */ MCD_OPC_CheckPredicate, + 27, + 57, + 66, + 0, // Skip to: 17205 + /* 252 */ MCD_OPC_Decode, + 186, + 20, + 44, // Opcode: SRLV + /* 256 */ MCD_OPC_FilterValue, + 1, + 48, + 66, + 0, // Skip to: 17205 + /* 261 */ MCD_OPC_CheckPredicate, + 28, + 43, + 66, + 0, // Skip to: 17205 + /* 266 */ MCD_OPC_Decode, + 202, + 18, + 44, // Opcode: ROTRV + /* 270 */ MCD_OPC_FilterValue, + 7, + 16, + 0, + 0, // Skip to: 291 + /* 275 */ MCD_OPC_CheckPredicate, + 27, + 29, + 66, + 0, // Skip to: 17205 + /* 280 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 22, + 66, + 0, // Skip to: 17205 + /* 287 */ MCD_OPC_Decode, + 164, + 20, + 44, // Opcode: SRAV + /* 291 */ MCD_OPC_FilterValue, + 8, + 33, + 0, + 0, // Skip to: 329 + /* 296 */ MCD_OPC_ExtractField, + 6, + 15, // Inst{20-6} ... + /* 299 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 314 + /* 304 */ MCD_OPC_CheckPredicate, + 31, + 0, + 66, + 0, // Skip to: 17205 + /* 309 */ MCD_OPC_Decode, + 133, + 14, + 175, + 1, // Opcode: JR + /* 314 */ MCD_OPC_FilterValue, + 16, + 246, + 65, + 0, // Skip to: 17205 + /* 319 */ MCD_OPC_CheckPredicate, + 32, + 241, + 65, + 0, // Skip to: 17205 + /* 324 */ MCD_OPC_Decode, + 140, + 14, + 175, + 1, // Opcode: JR_HB + /* 329 */ MCD_OPC_FilterValue, + 9, + 45, + 0, + 0, // Skip to: 379 + /* 334 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 337 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 358 + /* 342 */ MCD_OPC_CheckPredicate, + 33, + 218, + 65, + 0, // Skip to: 17205 + /* 347 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 211, + 65, + 0, // Skip to: 17205 + /* 354 */ MCD_OPC_Decode, + 240, + 13, + 14, // Opcode: JALR + /* 358 */ MCD_OPC_FilterValue, + 16, + 202, + 65, + 0, // Skip to: 17205 + /* 363 */ MCD_OPC_CheckPredicate, + 34, + 197, + 65, + 0, // Skip to: 17205 + /* 368 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 190, + 65, + 0, // Skip to: 17205 + /* 375 */ MCD_OPC_Decode, + 248, + 13, + 14, // Opcode: JALR_HB + /* 379 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 401 + /* 384 */ MCD_OPC_CheckPredicate, + 35, + 176, + 65, + 0, // Skip to: 17205 + /* 389 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 169, + 65, + 0, // Skip to: 17205 + /* 396 */ MCD_OPC_Decode, + 197, + 16, + 176, + 1, // Opcode: MOVZ_I_I + /* 401 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 423 + /* 406 */ MCD_OPC_CheckPredicate, + 35, + 154, + 65, + 0, // Skip to: 17205 + /* 411 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 147, + 65, + 0, // Skip to: 17205 + /* 418 */ MCD_OPC_Decode, + 177, + 16, + 176, + 1, // Opcode: MOVN_I_I + /* 423 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 438 + /* 428 */ MCD_OPC_CheckPredicate, + 27, + 132, + 65, + 0, // Skip to: 17205 + /* 433 */ MCD_OPC_Decode, + 173, + 21, + 177, + 1, // Opcode: SYSCALL + /* 438 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 452 + /* 443 */ MCD_OPC_CheckPredicate, + 27, + 117, + 65, + 0, // Skip to: 17205 + /* 448 */ MCD_OPC_Decode, + 246, + 7, + 45, // Opcode: BREAK + /* 452 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 467 + /* 457 */ MCD_OPC_CheckPredicate, + 36, + 103, + 65, + 0, // Skip to: 17205 + /* 462 */ MCD_OPC_Decode, + 167, + 21, + 178, + 1, // Opcode: SYNC + /* 467 */ MCD_OPC_FilterValue, + 16, + 51, + 0, + 0, // Skip to: 523 + /* 472 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 475 */ MCD_OPC_FilterValue, + 0, + 85, + 65, + 0, // Skip to: 17205 + /* 480 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 483 */ MCD_OPC_FilterValue, + 0, + 77, + 65, + 0, // Skip to: 17205 + /* 488 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 491 */ MCD_OPC_FilterValue, + 0, + 69, + 65, + 0, // Skip to: 17205 + /* 496 */ MCD_OPC_CheckPredicate, + 31, + 12, + 0, + 0, // Skip to: 513 + /* 501 */ MCD_OPC_CheckField, + 21, + 2, + 0, + 5, + 0, + 0, // Skip to: 513 + /* 508 */ MCD_OPC_Decode, + 230, + 15, + 179, + 1, // Opcode: MFHI + /* 513 */ MCD_OPC_CheckPredicate, + 37, + 47, + 65, + 0, // Skip to: 17205 + /* 518 */ MCD_OPC_Decode, + 233, + 15, + 180, + 1, // Opcode: MFHI_DSP + /* 523 */ MCD_OPC_FilterValue, + 17, + 43, + 0, + 0, // Skip to: 571 + /* 528 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 531 */ MCD_OPC_FilterValue, + 0, + 29, + 65, + 0, // Skip to: 17205 + /* 536 */ MCD_OPC_ExtractField, + 13, + 8, // Inst{20-13} ... + /* 539 */ MCD_OPC_FilterValue, + 0, + 21, + 65, + 0, // Skip to: 17205 + /* 544 */ MCD_OPC_CheckPredicate, + 31, + 12, + 0, + 0, // Skip to: 561 + /* 549 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 5, + 0, + 0, // Skip to: 561 + /* 556 */ MCD_OPC_Decode, + 246, + 16, + 175, + 1, // Opcode: MTHI + /* 561 */ MCD_OPC_CheckPredicate, + 37, + 255, + 64, + 0, // Skip to: 17205 + /* 566 */ MCD_OPC_Decode, + 248, + 16, + 181, + 1, // Opcode: MTHI_DSP + /* 571 */ MCD_OPC_FilterValue, + 18, + 51, + 0, + 0, // Skip to: 627 + /* 576 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 579 */ MCD_OPC_FilterValue, + 0, + 237, + 64, + 0, // Skip to: 17205 + /* 584 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 587 */ MCD_OPC_FilterValue, + 0, + 229, + 64, + 0, // Skip to: 17205 + /* 592 */ MCD_OPC_ExtractField, + 23, + 3, // Inst{25-23} ... + /* 595 */ MCD_OPC_FilterValue, + 0, + 221, + 64, + 0, // Skip to: 17205 + /* 600 */ MCD_OPC_CheckPredicate, + 31, + 12, + 0, + 0, // Skip to: 617 + /* 605 */ MCD_OPC_CheckField, + 21, + 2, + 0, + 5, + 0, + 0, // Skip to: 617 + /* 612 */ MCD_OPC_Decode, + 236, + 15, + 179, + 1, // Opcode: MFLO + /* 617 */ MCD_OPC_CheckPredicate, + 37, + 199, + 64, + 0, // Skip to: 17205 + /* 622 */ MCD_OPC_Decode, + 239, + 15, + 180, + 1, // Opcode: MFLO_DSP + /* 627 */ MCD_OPC_FilterValue, + 19, + 43, + 0, + 0, // Skip to: 675 + /* 632 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 635 */ MCD_OPC_FilterValue, + 0, + 181, + 64, + 0, // Skip to: 17205 + /* 640 */ MCD_OPC_ExtractField, + 13, + 8, // Inst{20-13} ... + /* 643 */ MCD_OPC_FilterValue, + 0, + 173, + 64, + 0, // Skip to: 17205 + /* 648 */ MCD_OPC_CheckPredicate, + 31, + 12, + 0, + 0, // Skip to: 665 + /* 653 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 5, + 0, + 0, // Skip to: 665 + /* 660 */ MCD_OPC_Decode, + 253, + 16, + 175, + 1, // Opcode: MTLO + /* 665 */ MCD_OPC_CheckPredicate, + 37, + 151, + 64, + 0, // Skip to: 17205 + /* 670 */ MCD_OPC_Decode, + 255, + 16, + 182, + 1, // Opcode: MTLO_DSP + /* 675 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 697 + /* 680 */ MCD_OPC_CheckPredicate, + 38, + 136, + 64, + 0, // Skip to: 17205 + /* 685 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 129, + 64, + 0, // Skip to: 17205 + /* 692 */ MCD_OPC_Decode, + 253, + 10, + 183, + 1, // Opcode: DLSA + /* 697 */ MCD_OPC_FilterValue, + 24, + 42, + 0, + 0, // Skip to: 744 + /* 702 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 705 */ MCD_OPC_FilterValue, + 0, + 111, + 64, + 0, // Skip to: 17205 + /* 710 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 713 */ MCD_OPC_FilterValue, + 0, + 103, + 64, + 0, // Skip to: 17205 + /* 718 */ MCD_OPC_CheckPredicate, + 31, + 11, + 0, + 0, // Skip to: 734 + /* 723 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 734 + /* 730 */ MCD_OPC_Decode, + 165, + 17, + 69, // Opcode: MULT + /* 734 */ MCD_OPC_CheckPredicate, + 37, + 82, + 64, + 0, // Skip to: 17205 + /* 739 */ MCD_OPC_Decode, + 168, + 17, + 184, + 1, // Opcode: MULT_DSP + /* 744 */ MCD_OPC_FilterValue, + 25, + 42, + 0, + 0, // Skip to: 791 + /* 749 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 752 */ MCD_OPC_FilterValue, + 0, + 64, + 64, + 0, // Skip to: 17205 + /* 757 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 760 */ MCD_OPC_FilterValue, + 0, + 56, + 64, + 0, // Skip to: 17205 + /* 765 */ MCD_OPC_CheckPredicate, + 31, + 11, + 0, + 0, // Skip to: 781 + /* 770 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 781 + /* 777 */ MCD_OPC_Decode, + 171, + 17, + 69, // Opcode: MULTu + /* 781 */ MCD_OPC_CheckPredicate, + 37, + 35, + 64, + 0, // Skip to: 17205 + /* 786 */ MCD_OPC_Decode, + 166, + 17, + 184, + 1, // Opcode: MULTU_DSP + /* 791 */ MCD_OPC_FilterValue, + 26, + 16, + 0, + 0, // Skip to: 812 + /* 796 */ MCD_OPC_CheckPredicate, + 31, + 20, + 64, + 0, // Skip to: 17205 + /* 801 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 13, + 64, + 0, // Skip to: 17205 + /* 808 */ MCD_OPC_Decode, + 139, + 19, + 69, // Opcode: SDIV + /* 812 */ MCD_OPC_FilterValue, + 27, + 16, + 0, + 0, // Skip to: 833 + /* 817 */ MCD_OPC_CheckPredicate, + 31, + 255, + 63, + 0, // Skip to: 17205 + /* 822 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 248, + 63, + 0, // Skip to: 17205 + /* 829 */ MCD_OPC_Decode, + 255, + 21, + 69, // Opcode: UDIV + /* 833 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 854 + /* 838 */ MCD_OPC_CheckPredicate, + 27, + 234, + 63, + 0, // Skip to: 17205 + /* 843 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 227, + 63, + 0, // Skip to: 17205 + /* 850 */ MCD_OPC_Decode, + 194, + 5, + 50, // Opcode: ADD + /* 854 */ MCD_OPC_FilterValue, + 33, + 16, + 0, + 0, // Skip to: 875 + /* 859 */ MCD_OPC_CheckPredicate, + 27, + 213, + 63, + 0, // Skip to: 17205 + /* 864 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 206, + 63, + 0, // Skip to: 17205 + /* 871 */ MCD_OPC_Decode, + 139, + 6, + 50, // Opcode: ADDu + /* 875 */ MCD_OPC_FilterValue, + 34, + 16, + 0, + 0, // Skip to: 896 + /* 880 */ MCD_OPC_CheckPredicate, + 27, + 192, + 63, + 0, // Skip to: 17205 + /* 885 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 185, + 63, + 0, // Skip to: 17205 + /* 892 */ MCD_OPC_Decode, + 200, + 20, + 50, // Opcode: SUB + /* 896 */ MCD_OPC_FilterValue, + 35, + 16, + 0, + 0, // Skip to: 917 + /* 901 */ MCD_OPC_CheckPredicate, + 27, + 171, + 63, + 0, // Skip to: 17205 + /* 906 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 164, + 63, + 0, // Skip to: 17205 + /* 913 */ MCD_OPC_Decode, + 128, + 21, + 50, // Opcode: SUBu + /* 917 */ MCD_OPC_FilterValue, + 36, + 16, + 0, + 0, // Skip to: 938 + /* 922 */ MCD_OPC_CheckPredicate, + 27, + 150, + 63, + 0, // Skip to: 17205 + /* 927 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 143, + 63, + 0, // Skip to: 17205 + /* 934 */ MCD_OPC_Decode, + 145, + 6, + 50, // Opcode: AND + /* 938 */ MCD_OPC_FilterValue, + 37, + 16, + 0, + 0, // Skip to: 959 + /* 943 */ MCD_OPC_CheckPredicate, + 27, + 129, + 63, + 0, // Skip to: 17205 + /* 948 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 122, + 63, + 0, // Skip to: 17205 + /* 955 */ MCD_OPC_Decode, + 220, + 17, + 50, // Opcode: OR + /* 959 */ MCD_OPC_FilterValue, + 38, + 16, + 0, + 0, // Skip to: 980 + /* 964 */ MCD_OPC_CheckPredicate, + 27, + 108, + 63, + 0, // Skip to: 17205 + /* 969 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 101, + 63, + 0, // Skip to: 17205 + /* 976 */ MCD_OPC_Decode, + 145, + 22, + 50, // Opcode: XOR + /* 980 */ MCD_OPC_FilterValue, + 39, + 16, + 0, + 0, // Skip to: 1001 + /* 985 */ MCD_OPC_CheckPredicate, + 27, + 87, + 63, + 0, // Skip to: 17205 + /* 990 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 80, + 63, + 0, // Skip to: 17205 + /* 997 */ MCD_OPC_Decode, + 210, + 17, + 50, // Opcode: NOR + /* 1001 */ MCD_OPC_FilterValue, + 42, + 16, + 0, + 0, // Skip to: 1022 + /* 1006 */ MCD_OPC_CheckPredicate, + 27, + 66, + 63, + 0, // Skip to: 17205 + /* 1011 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 59, + 63, + 0, // Skip to: 17205 + /* 1018 */ MCD_OPC_Decode, + 129, + 20, + 50, // Opcode: SLT + /* 1022 */ MCD_OPC_FilterValue, + 43, + 16, + 0, + 0, // Skip to: 1043 + /* 1027 */ MCD_OPC_CheckPredicate, + 27, + 45, + 63, + 0, // Skip to: 17205 + /* 1032 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 38, + 63, + 0, // Skip to: 17205 + /* 1039 */ MCD_OPC_Decode, + 138, + 20, + 50, // Opcode: SLTu + /* 1043 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 1058 + /* 1048 */ MCD_OPC_CheckPredicate, + 36, + 24, + 63, + 0, // Skip to: 17205 + /* 1053 */ MCD_OPC_Decode, + 200, + 21, + 185, + 1, // Opcode: TGE + /* 1058 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 1073 + /* 1063 */ MCD_OPC_CheckPredicate, + 36, + 9, + 63, + 0, // Skip to: 17205 + /* 1068 */ MCD_OPC_Decode, + 205, + 21, + 185, + 1, // Opcode: TGEU + /* 1073 */ MCD_OPC_FilterValue, + 50, + 10, + 0, + 0, // Skip to: 1088 + /* 1078 */ MCD_OPC_CheckPredicate, + 36, + 250, + 62, + 0, // Skip to: 17205 + /* 1083 */ MCD_OPC_Decode, + 232, + 21, + 185, + 1, // Opcode: TLT + /* 1088 */ MCD_OPC_FilterValue, + 51, + 10, + 0, + 0, // Skip to: 1103 + /* 1093 */ MCD_OPC_CheckPredicate, + 36, + 235, + 62, + 0, // Skip to: 17205 + /* 1098 */ MCD_OPC_Decode, + 236, + 21, + 185, + 1, // Opcode: TLTU + /* 1103 */ MCD_OPC_FilterValue, + 52, + 10, + 0, + 0, // Skip to: 1118 + /* 1108 */ MCD_OPC_CheckPredicate, + 36, + 220, + 62, + 0, // Skip to: 17205 + /* 1113 */ MCD_OPC_Decode, + 196, + 21, + 185, + 1, // Opcode: TEQ + /* 1118 */ MCD_OPC_FilterValue, + 54, + 210, + 62, + 0, // Skip to: 17205 + /* 1123 */ MCD_OPC_CheckPredicate, + 36, + 205, + 62, + 0, // Skip to: 17205 + /* 1128 */ MCD_OPC_Decode, + 239, + 21, + 185, + 1, // Opcode: TNE + /* 1133 */ MCD_OPC_FilterValue, + 1, + 250, + 0, + 0, // Skip to: 1388 + /* 1138 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 1141 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1156 + /* 1146 */ MCD_OPC_CheckPredicate, + 27, + 182, + 62, + 0, // Skip to: 17205 + /* 1151 */ MCD_OPC_Decode, + 194, + 7, + 186, + 1, // Opcode: BLTZ + /* 1156 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1171 + /* 1161 */ MCD_OPC_CheckPredicate, + 27, + 167, + 62, + 0, // Skip to: 17205 + /* 1166 */ MCD_OPC_Decode, + 137, + 7, + 186, + 1, // Opcode: BGEZ + /* 1171 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1186 + /* 1176 */ MCD_OPC_CheckPredicate, + 39, + 152, + 62, + 0, // Skip to: 17205 + /* 1181 */ MCD_OPC_Decode, + 205, + 7, + 186, + 1, // Opcode: BLTZL + /* 1186 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1201 + /* 1191 */ MCD_OPC_CheckPredicate, + 39, + 137, + 62, + 0, // Skip to: 17205 + /* 1196 */ MCD_OPC_Decode, + 148, + 7, + 186, + 1, // Opcode: BGEZL + /* 1201 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1216 + /* 1206 */ MCD_OPC_CheckPredicate, + 39, + 122, + 62, + 0, // Skip to: 17205 + /* 1211 */ MCD_OPC_Decode, + 201, + 21, + 164, + 1, // Opcode: TGEI + /* 1216 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1231 + /* 1221 */ MCD_OPC_CheckPredicate, + 39, + 107, + 62, + 0, // Skip to: 17205 + /* 1226 */ MCD_OPC_Decode, + 202, + 21, + 164, + 1, // Opcode: TGEIU + /* 1231 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1246 + /* 1236 */ MCD_OPC_CheckPredicate, + 39, + 92, + 62, + 0, // Skip to: 17205 + /* 1241 */ MCD_OPC_Decode, + 233, + 21, + 164, + 1, // Opcode: TLTI + /* 1246 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1261 + /* 1251 */ MCD_OPC_CheckPredicate, + 39, + 77, + 62, + 0, // Skip to: 17205 + /* 1256 */ MCD_OPC_Decode, + 254, + 21, + 164, + 1, // Opcode: TTLTIU + /* 1261 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 1276 + /* 1266 */ MCD_OPC_CheckPredicate, + 39, + 62, + 62, + 0, // Skip to: 17205 + /* 1271 */ MCD_OPC_Decode, + 197, + 21, + 164, + 1, // Opcode: TEQI + /* 1276 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1291 + /* 1281 */ MCD_OPC_CheckPredicate, + 39, + 47, + 62, + 0, // Skip to: 17205 + /* 1286 */ MCD_OPC_Decode, + 240, + 21, + 164, + 1, // Opcode: TNEI + /* 1291 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 1306 + /* 1296 */ MCD_OPC_CheckPredicate, + 31, + 32, + 62, + 0, // Skip to: 17205 + /* 1301 */ MCD_OPC_Decode, + 196, + 7, + 186, + 1, // Opcode: BLTZAL + /* 1306 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 1321 + /* 1311 */ MCD_OPC_CheckPredicate, + 31, + 17, + 62, + 0, // Skip to: 17205 + /* 1316 */ MCD_OPC_Decode, + 139, + 7, + 186, + 1, // Opcode: BGEZAL + /* 1321 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 1336 + /* 1326 */ MCD_OPC_CheckPredicate, + 39, + 2, + 62, + 0, // Skip to: 17205 + /* 1331 */ MCD_OPC_Decode, + 199, + 7, + 186, + 1, // Opcode: BLTZALL + /* 1336 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 1351 + /* 1341 */ MCD_OPC_CheckPredicate, + 39, + 243, + 61, + 0, // Skip to: 17205 + /* 1346 */ MCD_OPC_Decode, + 142, + 7, + 186, + 1, // Opcode: BGEZALL + /* 1351 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 1373 + /* 1356 */ MCD_OPC_CheckPredicate, + 40, + 228, + 61, + 0, // Skip to: 17205 + /* 1361 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 221, + 61, + 0, // Skip to: 17205 + /* 1368 */ MCD_OPC_Decode, + 243, + 7, + 187, + 1, // Opcode: BPOSGE32 + /* 1373 */ MCD_OPC_FilterValue, + 31, + 211, + 61, + 0, // Skip to: 17205 + /* 1378 */ MCD_OPC_CheckPredicate, + 28, + 206, + 61, + 0, // Skip to: 17205 + /* 1383 */ MCD_OPC_Decode, + 168, + 21, + 188, + 1, // Opcode: SYNCI + /* 1388 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1403 + /* 1393 */ MCD_OPC_CheckPredicate, + 27, + 191, + 61, + 0, // Skip to: 17205 + /* 1398 */ MCD_OPC_Decode, + 238, + 13, + 189, + 1, // Opcode: J + /* 1403 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1418 + /* 1408 */ MCD_OPC_CheckPredicate, + 27, + 176, + 61, + 0, // Skip to: 17205 + /* 1413 */ MCD_OPC_Decode, + 239, + 13, + 189, + 1, // Opcode: JAL + /* 1418 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 1433 + /* 1423 */ MCD_OPC_CheckPredicate, + 27, + 161, + 61, + 0, // Skip to: 17205 + /* 1428 */ MCD_OPC_Decode, + 244, + 6, + 190, + 1, // Opcode: BEQ + /* 1433 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1448 + /* 1438 */ MCD_OPC_CheckPredicate, + 27, + 146, + 61, + 0, // Skip to: 17205 + /* 1443 */ MCD_OPC_Decode, + 211, + 7, + 190, + 1, // Opcode: BNE + /* 1448 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 1470 + /* 1453 */ MCD_OPC_CheckPredicate, + 27, + 131, + 61, + 0, // Skip to: 17205 + /* 1458 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 124, + 61, + 0, // Skip to: 17205 + /* 1465 */ MCD_OPC_Decode, + 179, + 7, + 186, + 1, // Opcode: BLEZ + /* 1470 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 1492 + /* 1475 */ MCD_OPC_CheckPredicate, + 27, + 109, + 61, + 0, // Skip to: 17205 + /* 1480 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 102, + 61, + 0, // Skip to: 17205 + /* 1487 */ MCD_OPC_Decode, + 150, + 7, + 186, + 1, // Opcode: BGTZ + /* 1492 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1507 + /* 1497 */ MCD_OPC_CheckPredicate, + 31, + 87, + 61, + 0, // Skip to: 17205 + /* 1502 */ MCD_OPC_Decode, + 135, + 6, + 191, + 1, // Opcode: ADDi + /* 1507 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1522 + /* 1512 */ MCD_OPC_CheckPredicate, + 27, + 72, + 61, + 0, // Skip to: 17205 + /* 1517 */ MCD_OPC_Decode, + 137, + 6, + 191, + 1, // Opcode: ADDiu + /* 1522 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1537 + /* 1527 */ MCD_OPC_CheckPredicate, + 27, + 57, + 61, + 0, // Skip to: 17205 + /* 1532 */ MCD_OPC_Decode, + 132, + 20, + 191, + 1, // Opcode: SLTi + /* 1537 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1552 + /* 1542 */ MCD_OPC_CheckPredicate, + 27, + 42, + 61, + 0, // Skip to: 17205 + /* 1547 */ MCD_OPC_Decode, + 135, + 20, + 191, + 1, // Opcode: SLTiu + /* 1552 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 1567 + /* 1557 */ MCD_OPC_CheckPredicate, + 27, + 27, + 61, + 0, // Skip to: 17205 + /* 1562 */ MCD_OPC_Decode, + 156, + 6, + 192, + 1, // Opcode: ANDi + /* 1567 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1582 + /* 1572 */ MCD_OPC_CheckPredicate, + 27, + 12, + 61, + 0, // Skip to: 17205 + /* 1577 */ MCD_OPC_Decode, + 229, + 17, + 192, + 1, // Opcode: ORi + /* 1582 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1597 + /* 1587 */ MCD_OPC_CheckPredicate, + 27, + 253, + 60, + 0, // Skip to: 17205 + /* 1592 */ MCD_OPC_Decode, + 154, + 22, + 192, + 1, // Opcode: XORi + /* 1597 */ MCD_OPC_FilterValue, + 15, + 16, + 0, + 0, // Skip to: 1618 + /* 1602 */ MCD_OPC_CheckPredicate, + 27, + 238, + 60, + 0, // Skip to: 17205 + /* 1607 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 231, + 60, + 0, // Skip to: 17205 + /* 1614 */ MCD_OPC_Decode, + 224, + 14, + 92, // Opcode: LUi + /* 1618 */ MCD_OPC_FilterValue, + 16, + 155, + 2, + 0, // Skip to: 2290 + /* 1623 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 1626 */ MCD_OPC_FilterValue, + 0, + 50, + 1, + 0, // Skip to: 1937 + /* 1631 */ MCD_OPC_ExtractField, + 21, + 4, // Inst{24-21} ... + /* 1634 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 1656 + /* 1639 */ MCD_OPC_CheckPredicate, + 27, + 201, + 60, + 0, // Skip to: 17205 + /* 1644 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 194, + 60, + 0, // Skip to: 17205 + /* 1651 */ MCD_OPC_Decode, + 212, + 15, + 193, + 1, // Opcode: MFC0 + /* 1656 */ MCD_OPC_FilterValue, + 3, + 65, + 0, + 0, // Skip to: 1726 + /* 1661 */ MCD_OPC_ExtractField, + 3, + 8, // Inst{10-3} ... + /* 1664 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1679 + /* 1669 */ MCD_OPC_CheckPredicate, + 41, + 171, + 60, + 0, // Skip to: 17205 + /* 1674 */ MCD_OPC_Decode, + 220, + 15, + 193, + 1, // Opcode: MFGC0 + /* 1679 */ MCD_OPC_FilterValue, + 64, + 10, + 0, + 0, // Skip to: 1694 + /* 1684 */ MCD_OPC_CheckPredicate, + 41, + 156, + 60, + 0, // Skip to: 17205 + /* 1689 */ MCD_OPC_Decode, + 236, + 16, + 194, + 1, // Opcode: MTGC0 + /* 1694 */ MCD_OPC_FilterValue, + 128, + 1, + 10, + 0, + 0, // Skip to: 1710 + /* 1700 */ MCD_OPC_CheckPredicate, + 41, + 140, + 60, + 0, // Skip to: 17205 + /* 1705 */ MCD_OPC_Decode, + 228, + 15, + 193, + 1, // Opcode: MFHGC0 + /* 1710 */ MCD_OPC_FilterValue, + 192, + 1, + 129, + 60, + 0, // Skip to: 17205 + /* 1716 */ MCD_OPC_CheckPredicate, + 41, + 124, + 60, + 0, // Skip to: 17205 + /* 1721 */ MCD_OPC_Decode, + 244, + 16, + 194, + 1, // Opcode: MTHGC0 + /* 1726 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 1748 + /* 1731 */ MCD_OPC_CheckPredicate, + 27, + 109, + 60, + 0, // Skip to: 17205 + /* 1736 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 102, + 60, + 0, // Skip to: 17205 + /* 1743 */ MCD_OPC_Decode, + 227, + 16, + 194, + 1, // Opcode: MTC0 + /* 1748 */ MCD_OPC_FilterValue, + 8, + 57, + 0, + 0, // Skip to: 1810 + /* 1753 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 1756 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1771 + /* 1761 */ MCD_OPC_CheckPredicate, + 31, + 20, + 0, + 0, // Skip to: 1786 + /* 1766 */ MCD_OPC_Decode, + 210, + 6, + 187, + 1, // Opcode: BC0F + /* 1771 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1786 + /* 1776 */ MCD_OPC_CheckPredicate, + 31, + 5, + 0, + 0, // Skip to: 1786 + /* 1781 */ MCD_OPC_Decode, + 211, + 6, + 187, + 1, // Opcode: BC0T + /* 1786 */ MCD_OPC_CheckPredicate, + 42, + 54, + 60, + 0, // Skip to: 17205 + /* 1791 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 47, + 60, + 0, // Skip to: 17205 + /* 1798 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 40, + 60, + 0, // Skip to: 17205 + /* 1805 */ MCD_OPC_Decode, + 242, + 15, + 195, + 1, // Opcode: MFTR + /* 1810 */ MCD_OPC_FilterValue, + 11, + 93, + 0, + 0, // Skip to: 1908 + /* 1815 */ MCD_OPC_ExtractField, + 0, + 16, // Inst{15-0} ... + /* 1818 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1832 + /* 1823 */ MCD_OPC_CheckPredicate, + 42, + 17, + 60, + 0, // Skip to: 17205 + /* 1828 */ MCD_OPC_Decode, + 218, + 11, + 81, // Opcode: DVPE + /* 1832 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 1846 + /* 1837 */ MCD_OPC_CheckPredicate, + 42, + 3, + 60, + 0, // Skip to: 17205 + /* 1842 */ MCD_OPC_Decode, + 235, + 11, + 81, // Opcode: EVPE + /* 1846 */ MCD_OPC_FilterValue, + 193, + 23, + 9, + 0, + 0, // Skip to: 1861 + /* 1852 */ MCD_OPC_CheckPredicate, + 42, + 244, + 59, + 0, // Skip to: 17205 + /* 1857 */ MCD_OPC_Decode, + 134, + 11, + 81, // Opcode: DMT + /* 1861 */ MCD_OPC_FilterValue, + 225, + 23, + 9, + 0, + 0, // Skip to: 1876 + /* 1867 */ MCD_OPC_CheckPredicate, + 42, + 229, + 59, + 0, // Skip to: 17205 + /* 1872 */ MCD_OPC_Decode, + 228, + 11, + 81, // Opcode: EMT + /* 1876 */ MCD_OPC_FilterValue, + 128, + 192, + 1, + 9, + 0, + 0, // Skip to: 1892 + /* 1883 */ MCD_OPC_CheckPredicate, + 28, + 213, + 59, + 0, // Skip to: 17205 + /* 1888 */ MCD_OPC_Decode, + 235, + 10, + 81, // Opcode: DI + /* 1892 */ MCD_OPC_FilterValue, + 160, + 192, + 1, + 202, + 59, + 0, // Skip to: 17205 + /* 1899 */ MCD_OPC_CheckPredicate, + 28, + 197, + 59, + 0, // Skip to: 17205 + /* 1904 */ MCD_OPC_Decode, + 225, + 11, + 81, // Opcode: EI + /* 1908 */ MCD_OPC_FilterValue, + 12, + 188, + 59, + 0, // Skip to: 17205 + /* 1913 */ MCD_OPC_CheckPredicate, + 42, + 183, + 59, + 0, // Skip to: 17205 + /* 1918 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 176, + 59, + 0, // Skip to: 17205 + /* 1925 */ MCD_OPC_CheckField, + 3, + 1, + 0, + 169, + 59, + 0, // Skip to: 17205 + /* 1932 */ MCD_OPC_Decode, + 136, + 17, + 195, + 1, // Opcode: MTTR + /* 1937 */ MCD_OPC_FilterValue, + 1, + 159, + 59, + 0, // Skip to: 17205 + /* 1942 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1945 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 1966 + /* 1950 */ MCD_OPC_CheckPredicate, + 27, + 146, + 59, + 0, // Skip to: 17205 + /* 1955 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 139, + 59, + 0, // Skip to: 17205 + /* 1962 */ MCD_OPC_Decode, + 226, + 21, + 0, // Opcode: TLBR + /* 1966 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 1987 + /* 1971 */ MCD_OPC_CheckPredicate, + 27, + 125, + 59, + 0, // Skip to: 17205 + /* 1976 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 118, + 59, + 0, // Skip to: 17205 + /* 1983 */ MCD_OPC_Decode, + 228, + 21, + 0, // Opcode: TLBWI + /* 1987 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 2008 + /* 1992 */ MCD_OPC_CheckPredicate, + 43, + 104, + 59, + 0, // Skip to: 17205 + /* 1997 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 97, + 59, + 0, // Skip to: 17205 + /* 2004 */ MCD_OPC_Decode, + 220, + 21, + 0, // Opcode: TLBINV + /* 2008 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 2029 + /* 2013 */ MCD_OPC_CheckPredicate, + 43, + 83, + 59, + 0, // Skip to: 17205 + /* 2018 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 76, + 59, + 0, // Skip to: 17205 + /* 2025 */ MCD_OPC_Decode, + 221, + 21, + 0, // Opcode: TLBINVF + /* 2029 */ MCD_OPC_FilterValue, + 6, + 16, + 0, + 0, // Skip to: 2050 + /* 2034 */ MCD_OPC_CheckPredicate, + 27, + 62, + 59, + 0, // Skip to: 17205 + /* 2039 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 55, + 59, + 0, // Skip to: 17205 + /* 2046 */ MCD_OPC_Decode, + 230, + 21, + 0, // Opcode: TLBWR + /* 2050 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 2071 + /* 2055 */ MCD_OPC_CheckPredicate, + 27, + 41, + 59, + 0, // Skip to: 17205 + /* 2060 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 34, + 59, + 0, // Skip to: 17205 + /* 2067 */ MCD_OPC_Decode, + 224, + 21, + 0, // Opcode: TLBP + /* 2071 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 2092 + /* 2076 */ MCD_OPC_CheckPredicate, + 41, + 20, + 59, + 0, // Skip to: 17205 + /* 2081 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 13, + 59, + 0, // Skip to: 17205 + /* 2088 */ MCD_OPC_Decode, + 214, + 21, + 0, // Opcode: TLBGR + /* 2092 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 2113 + /* 2097 */ MCD_OPC_CheckPredicate, + 41, + 255, + 58, + 0, // Skip to: 17205 + /* 2102 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 248, + 58, + 0, // Skip to: 17205 + /* 2109 */ MCD_OPC_Decode, + 216, + 21, + 0, // Opcode: TLBGWI + /* 2113 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 2134 + /* 2118 */ MCD_OPC_CheckPredicate, + 41, + 234, + 58, + 0, // Skip to: 17205 + /* 2123 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 227, + 58, + 0, // Skip to: 17205 + /* 2130 */ MCD_OPC_Decode, + 208, + 21, + 0, // Opcode: TLBGINV + /* 2134 */ MCD_OPC_FilterValue, + 12, + 16, + 0, + 0, // Skip to: 2155 + /* 2139 */ MCD_OPC_CheckPredicate, + 41, + 213, + 58, + 0, // Skip to: 17205 + /* 2144 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 206, + 58, + 0, // Skip to: 17205 + /* 2151 */ MCD_OPC_Decode, + 209, + 21, + 0, // Opcode: TLBGINVF + /* 2155 */ MCD_OPC_FilterValue, + 14, + 16, + 0, + 0, // Skip to: 2176 + /* 2160 */ MCD_OPC_CheckPredicate, + 41, + 192, + 58, + 0, // Skip to: 17205 + /* 2165 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 185, + 58, + 0, // Skip to: 17205 + /* 2172 */ MCD_OPC_Decode, + 218, + 21, + 0, // Opcode: TLBGWR + /* 2176 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 2197 + /* 2181 */ MCD_OPC_CheckPredicate, + 41, + 171, + 58, + 0, // Skip to: 17205 + /* 2186 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 164, + 58, + 0, // Skip to: 17205 + /* 2193 */ MCD_OPC_Decode, + 212, + 21, + 0, // Opcode: TLBGP + /* 2197 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 2233 + /* 2202 */ MCD_OPC_ExtractField, + 6, + 19, // Inst{24-6} ... + /* 2205 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2219 + /* 2210 */ MCD_OPC_CheckPredicate, + 44, + 142, + 58, + 0, // Skip to: 17205 + /* 2215 */ MCD_OPC_Decode, + 229, + 11, + 0, // Opcode: ERET + /* 2219 */ MCD_OPC_FilterValue, + 1, + 133, + 58, + 0, // Skip to: 17205 + /* 2224 */ MCD_OPC_CheckPredicate, + 45, + 128, + 58, + 0, // Skip to: 17205 + /* 2229 */ MCD_OPC_Decode, + 230, + 11, + 0, // Opcode: ERETNC + /* 2233 */ MCD_OPC_FilterValue, + 31, + 16, + 0, + 0, // Skip to: 2254 + /* 2238 */ MCD_OPC_CheckPredicate, + 46, + 114, + 58, + 0, // Skip to: 17205 + /* 2243 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 107, + 58, + 0, // Skip to: 17205 + /* 2250 */ MCD_OPC_Decode, + 228, + 10, + 0, // Opcode: DERET + /* 2254 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 2275 + /* 2259 */ MCD_OPC_CheckPredicate, + 44, + 93, + 58, + 0, // Skip to: 17205 + /* 2264 */ MCD_OPC_CheckField, + 6, + 19, + 0, + 86, + 58, + 0, // Skip to: 17205 + /* 2271 */ MCD_OPC_Decode, + 136, + 22, + 0, // Opcode: WAIT + /* 2275 */ MCD_OPC_FilterValue, + 40, + 77, + 58, + 0, // Skip to: 17205 + /* 2280 */ MCD_OPC_CheckPredicate, + 41, + 72, + 58, + 0, // Skip to: 17205 + /* 2285 */ MCD_OPC_Decode, + 207, + 13, + 196, + 1, // Opcode: HYPCALL + /* 2290 */ MCD_OPC_FilterValue, + 17, + 205, + 7, + 0, // Skip to: 4292 + /* 2295 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 2298 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2320 + /* 2303 */ MCD_OPC_CheckPredicate, + 47, + 49, + 58, + 0, // Skip to: 17205 + /* 2308 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 42, + 58, + 0, // Skip to: 17205 + /* 2315 */ MCD_OPC_Decode, + 214, + 15, + 197, + 1, // Opcode: MFC1 + /* 2320 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 2342 + /* 2325 */ MCD_OPC_CheckPredicate, + 48, + 27, + 58, + 0, // Skip to: 17205 + /* 2330 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 20, + 58, + 0, // Skip to: 17205 + /* 2337 */ MCD_OPC_Decode, + 128, + 11, + 198, + 1, // Opcode: DMFC1 + /* 2342 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 2364 + /* 2347 */ MCD_OPC_CheckPredicate, + 47, + 5, + 58, + 0, // Skip to: 17205 + /* 2352 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 254, + 57, + 0, // Skip to: 17205 + /* 2359 */ MCD_OPC_Decode, + 174, + 8, + 199, + 1, // Opcode: CFC1 + /* 2364 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 2386 + /* 2369 */ MCD_OPC_CheckPredicate, + 49, + 239, + 57, + 0, // Skip to: 17205 + /* 2374 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 232, + 57, + 0, // Skip to: 17205 + /* 2381 */ MCD_OPC_Decode, + 223, + 15, + 200, + 1, // Opcode: MFHC1_D32 + /* 2386 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 2408 + /* 2391 */ MCD_OPC_CheckPredicate, + 47, + 217, + 57, + 0, // Skip to: 17205 + /* 2396 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 210, + 57, + 0, // Skip to: 17205 + /* 2403 */ MCD_OPC_Decode, + 229, + 16, + 201, + 1, // Opcode: MTC1 + /* 2408 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 2430 + /* 2413 */ MCD_OPC_CheckPredicate, + 48, + 195, + 57, + 0, // Skip to: 17205 + /* 2418 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 188, + 57, + 0, // Skip to: 17205 + /* 2425 */ MCD_OPC_Decode, + 136, + 11, + 202, + 1, // Opcode: DMTC1 + /* 2430 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 2452 + /* 2435 */ MCD_OPC_CheckPredicate, + 47, + 173, + 57, + 0, // Skip to: 17205 + /* 2440 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 166, + 57, + 0, // Skip to: 17205 + /* 2447 */ MCD_OPC_Decode, + 201, + 9, + 203, + 1, // Opcode: CTC1 + /* 2452 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 2474 + /* 2457 */ MCD_OPC_CheckPredicate, + 49, + 151, + 57, + 0, // Skip to: 17205 + /* 2462 */ MCD_OPC_CheckField, + 0, + 11, + 0, + 144, + 57, + 0, // Skip to: 17205 + /* 2469 */ MCD_OPC_Decode, + 239, + 16, + 204, + 1, // Opcode: MTHC1_D32 + /* 2474 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 2542 + /* 2479 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 2482 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2497 + /* 2487 */ MCD_OPC_CheckPredicate, + 50, + 121, + 57, + 0, // Skip to: 17205 + /* 2492 */ MCD_OPC_Decode, + 215, + 6, + 205, + 1, // Opcode: BC1F + /* 2497 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2512 + /* 2502 */ MCD_OPC_CheckPredicate, + 50, + 106, + 57, + 0, // Skip to: 17205 + /* 2507 */ MCD_OPC_Decode, + 220, + 6, + 205, + 1, // Opcode: BC1T + /* 2512 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2527 + /* 2517 */ MCD_OPC_CheckPredicate, + 51, + 91, + 57, + 0, // Skip to: 17205 + /* 2522 */ MCD_OPC_Decode, + 216, + 6, + 205, + 1, // Opcode: BC1FL + /* 2527 */ MCD_OPC_FilterValue, + 3, + 81, + 57, + 0, // Skip to: 17205 + /* 2532 */ MCD_OPC_CheckPredicate, + 51, + 76, + 57, + 0, // Skip to: 17205 + /* 2537 */ MCD_OPC_Decode, + 221, + 6, + 205, + 1, // Opcode: BC1TL + /* 2542 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 2557 + /* 2547 */ MCD_OPC_CheckPredicate, + 30, + 61, + 57, + 0, // Skip to: 17205 + /* 2552 */ MCD_OPC_Decode, + 136, + 8, + 206, + 1, // Opcode: BZ_V + /* 2557 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 2572 + /* 2562 */ MCD_OPC_CheckPredicate, + 30, + 46, + 57, + 0, // Skip to: 17205 + /* 2567 */ MCD_OPC_Decode, + 239, + 7, + 206, + 1, // Opcode: BNZ_V + /* 2572 */ MCD_OPC_FilterValue, + 16, + 1, + 3, + 0, // Skip to: 3346 + /* 2577 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 2580 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2595 + /* 2585 */ MCD_OPC_CheckPredicate, + 47, + 23, + 57, + 0, // Skip to: 17205 + /* 2590 */ MCD_OPC_Decode, + 150, + 12, + 207, + 1, // Opcode: FADD_S + /* 2595 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2610 + /* 2600 */ MCD_OPC_CheckPredicate, + 47, + 8, + 57, + 0, // Skip to: 17205 + /* 2605 */ MCD_OPC_Decode, + 167, + 13, + 207, + 1, // Opcode: FSUB_S + /* 2610 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2625 + /* 2615 */ MCD_OPC_CheckPredicate, + 47, + 249, + 56, + 0, // Skip to: 17205 + /* 2620 */ MCD_OPC_Decode, + 251, + 12, + 207, + 1, // Opcode: FMUL_S + /* 2625 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 2640 + /* 2630 */ MCD_OPC_CheckPredicate, + 47, + 234, + 56, + 0, // Skip to: 17205 + /* 2635 */ MCD_OPC_Decode, + 188, + 12, + 207, + 1, // Opcode: FDIV_S + /* 2640 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 2662 + /* 2645 */ MCD_OPC_CheckPredicate, + 52, + 219, + 56, + 0, // Skip to: 17205 + /* 2650 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 212, + 56, + 0, // Skip to: 17205 + /* 2657 */ MCD_OPC_Decode, + 158, + 13, + 208, + 1, // Opcode: FSQRT_S + /* 2662 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 2684 + /* 2667 */ MCD_OPC_CheckPredicate, + 47, + 197, + 56, + 0, // Skip to: 17205 + /* 2672 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 190, + 56, + 0, // Skip to: 17205 + /* 2679 */ MCD_OPC_Decode, + 142, + 12, + 208, + 1, // Opcode: FABS_S + /* 2684 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 2706 + /* 2689 */ MCD_OPC_CheckPredicate, + 47, + 175, + 56, + 0, // Skip to: 17205 + /* 2694 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 168, + 56, + 0, // Skip to: 17205 + /* 2701 */ MCD_OPC_Decode, + 240, + 12, + 208, + 1, // Opcode: FMOV_S + /* 2706 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 2728 + /* 2711 */ MCD_OPC_CheckPredicate, + 53, + 153, + 56, + 0, // Skip to: 17205 + /* 2716 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 146, + 56, + 0, // Skip to: 17205 + /* 2723 */ MCD_OPC_Decode, + 131, + 13, + 208, + 1, // Opcode: FNEG_S + /* 2728 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 2750 + /* 2733 */ MCD_OPC_CheckPredicate, + 52, + 131, + 56, + 0, // Skip to: 17205 + /* 2738 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 124, + 56, + 0, // Skip to: 17205 + /* 2745 */ MCD_OPC_Decode, + 213, + 18, + 208, + 1, // Opcode: ROUND_W_S + /* 2750 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 2772 + /* 2755 */ MCD_OPC_CheckPredicate, + 52, + 109, + 56, + 0, // Skip to: 17205 + /* 2760 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 102, + 56, + 0, // Skip to: 17205 + /* 2767 */ MCD_OPC_Decode, + 251, + 21, + 208, + 1, // Opcode: TRUNC_W_S + /* 2772 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 2794 + /* 2777 */ MCD_OPC_CheckPredicate, + 52, + 87, + 56, + 0, // Skip to: 17205 + /* 2782 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 80, + 56, + 0, // Skip to: 17205 + /* 2789 */ MCD_OPC_Decode, + 163, + 8, + 208, + 1, // Opcode: CEIL_W_S + /* 2794 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 2816 + /* 2799 */ MCD_OPC_CheckPredicate, + 52, + 65, + 56, + 0, // Skip to: 17205 + /* 2804 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 58, + 56, + 0, // Skip to: 17205 + /* 2811 */ MCD_OPC_Decode, + 222, + 12, + 208, + 1, // Opcode: FLOOR_W_S + /* 2816 */ MCD_OPC_FilterValue, + 17, + 33, + 0, + 0, // Skip to: 2854 + /* 2821 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 2824 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2839 + /* 2829 */ MCD_OPC_CheckPredicate, + 29, + 35, + 56, + 0, // Skip to: 17205 + /* 2834 */ MCD_OPC_Decode, + 168, + 16, + 209, + 1, // Opcode: MOVF_S + /* 2839 */ MCD_OPC_FilterValue, + 1, + 25, + 56, + 0, // Skip to: 17205 + /* 2844 */ MCD_OPC_CheckPredicate, + 29, + 20, + 56, + 0, // Skip to: 17205 + /* 2849 */ MCD_OPC_Decode, + 188, + 16, + 209, + 1, // Opcode: MOVT_S + /* 2854 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 2869 + /* 2859 */ MCD_OPC_CheckPredicate, + 29, + 5, + 56, + 0, // Skip to: 17205 + /* 2864 */ MCD_OPC_Decode, + 200, + 16, + 210, + 1, // Opcode: MOVZ_I_S + /* 2869 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 2884 + /* 2874 */ MCD_OPC_CheckPredicate, + 29, + 246, + 55, + 0, // Skip to: 17205 + /* 2879 */ MCD_OPC_Decode, + 180, + 16, + 210, + 1, // Opcode: MOVN_I_S + /* 2884 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 2906 + /* 2889 */ MCD_OPC_CheckPredicate, + 54, + 231, + 55, + 0, // Skip to: 17205 + /* 2894 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 224, + 55, + 0, // Skip to: 17205 + /* 2901 */ MCD_OPC_Decode, + 187, + 18, + 208, + 1, // Opcode: RECIP_S + /* 2906 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 2928 + /* 2911 */ MCD_OPC_CheckPredicate, + 54, + 209, + 55, + 0, // Skip to: 17205 + /* 2916 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 202, + 55, + 0, // Skip to: 17205 + /* 2923 */ MCD_OPC_Decode, + 220, + 18, + 208, + 1, // Opcode: RSQRT_S + /* 2928 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 2950 + /* 2933 */ MCD_OPC_CheckPredicate, + 55, + 187, + 55, + 0, // Skip to: 17205 + /* 2938 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 180, + 55, + 0, // Skip to: 17205 + /* 2945 */ MCD_OPC_Decode, + 205, + 9, + 211, + 1, // Opcode: CVT_D32_S + /* 2950 */ MCD_OPC_FilterValue, + 36, + 17, + 0, + 0, // Skip to: 2972 + /* 2955 */ MCD_OPC_CheckPredicate, + 47, + 165, + 55, + 0, // Skip to: 17205 + /* 2960 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 158, + 55, + 0, // Skip to: 17205 + /* 2967 */ MCD_OPC_Decode, + 239, + 9, + 208, + 1, // Opcode: CVT_W_S + /* 2972 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 2994 + /* 2977 */ MCD_OPC_CheckPredicate, + 56, + 143, + 55, + 0, // Skip to: 17205 + /* 2982 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 136, + 55, + 0, // Skip to: 17205 + /* 2989 */ MCD_OPC_Decode, + 218, + 9, + 212, + 1, // Opcode: CVT_L_S + /* 2994 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 3016 + /* 2999 */ MCD_OPC_CheckPredicate, + 50, + 121, + 55, + 0, // Skip to: 17205 + /* 3004 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 114, + 55, + 0, // Skip to: 17205 + /* 3011 */ MCD_OPC_Decode, + 252, + 9, + 213, + 1, // Opcode: C_F_S + /* 3016 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 3038 + /* 3021 */ MCD_OPC_CheckPredicate, + 50, + 99, + 55, + 0, // Skip to: 17205 + /* 3026 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 92, + 55, + 0, // Skip to: 17205 + /* 3033 */ MCD_OPC_Decode, + 208, + 10, + 213, + 1, // Opcode: C_UN_S + /* 3038 */ MCD_OPC_FilterValue, + 50, + 17, + 0, + 0, // Skip to: 3060 + /* 3043 */ MCD_OPC_CheckPredicate, + 50, + 77, + 55, + 0, // Skip to: 17205 + /* 3048 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 70, + 55, + 0, // Skip to: 17205 + /* 3055 */ MCD_OPC_Decode, + 246, + 9, + 213, + 1, // Opcode: C_EQ_S + /* 3060 */ MCD_OPC_FilterValue, + 51, + 17, + 0, + 0, // Skip to: 3082 + /* 3065 */ MCD_OPC_CheckPredicate, + 50, + 55, + 55, + 0, // Skip to: 17205 + /* 3070 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 48, + 55, + 0, // Skip to: 17205 + /* 3077 */ MCD_OPC_Decode, + 190, + 10, + 213, + 1, // Opcode: C_UEQ_S + /* 3082 */ MCD_OPC_FilterValue, + 52, + 17, + 0, + 0, // Skip to: 3104 + /* 3087 */ MCD_OPC_CheckPredicate, + 50, + 33, + 55, + 0, // Skip to: 17205 + /* 3092 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 26, + 55, + 0, // Skip to: 17205 + /* 3099 */ MCD_OPC_Decode, + 172, + 10, + 213, + 1, // Opcode: C_OLT_S + /* 3104 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 3126 + /* 3109 */ MCD_OPC_CheckPredicate, + 50, + 11, + 55, + 0, // Skip to: 17205 + /* 3114 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 4, + 55, + 0, // Skip to: 17205 + /* 3121 */ MCD_OPC_Decode, + 202, + 10, + 213, + 1, // Opcode: C_ULT_S + /* 3126 */ MCD_OPC_FilterValue, + 54, + 17, + 0, + 0, // Skip to: 3148 + /* 3131 */ MCD_OPC_CheckPredicate, + 50, + 245, + 54, + 0, // Skip to: 17205 + /* 3136 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 238, + 54, + 0, // Skip to: 17205 + /* 3143 */ MCD_OPC_Decode, + 166, + 10, + 213, + 1, // Opcode: C_OLE_S + /* 3148 */ MCD_OPC_FilterValue, + 55, + 17, + 0, + 0, // Skip to: 3170 + /* 3153 */ MCD_OPC_CheckPredicate, + 50, + 223, + 54, + 0, // Skip to: 17205 + /* 3158 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 216, + 54, + 0, // Skip to: 17205 + /* 3165 */ MCD_OPC_Decode, + 196, + 10, + 213, + 1, // Opcode: C_ULE_S + /* 3170 */ MCD_OPC_FilterValue, + 56, + 17, + 0, + 0, // Skip to: 3192 + /* 3175 */ MCD_OPC_CheckPredicate, + 50, + 201, + 54, + 0, // Skip to: 17205 + /* 3180 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 194, + 54, + 0, // Skip to: 17205 + /* 3187 */ MCD_OPC_Decode, + 184, + 10, + 213, + 1, // Opcode: C_SF_S + /* 3192 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 3214 + /* 3197 */ MCD_OPC_CheckPredicate, + 50, + 179, + 54, + 0, // Skip to: 17205 + /* 3202 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 172, + 54, + 0, // Skip to: 17205 + /* 3209 */ MCD_OPC_Decode, + 148, + 10, + 213, + 1, // Opcode: C_NGLE_S + /* 3214 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 3236 + /* 3219 */ MCD_OPC_CheckPredicate, + 50, + 157, + 54, + 0, // Skip to: 17205 + /* 3224 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 150, + 54, + 0, // Skip to: 17205 + /* 3231 */ MCD_OPC_Decode, + 178, + 10, + 213, + 1, // Opcode: C_SEQ_S + /* 3236 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 3258 + /* 3241 */ MCD_OPC_CheckPredicate, + 50, + 135, + 54, + 0, // Skip to: 17205 + /* 3246 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 128, + 54, + 0, // Skip to: 17205 + /* 3253 */ MCD_OPC_Decode, + 154, + 10, + 213, + 1, // Opcode: C_NGL_S + /* 3258 */ MCD_OPC_FilterValue, + 60, + 17, + 0, + 0, // Skip to: 3280 + /* 3263 */ MCD_OPC_CheckPredicate, + 50, + 113, + 54, + 0, // Skip to: 17205 + /* 3268 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 106, + 54, + 0, // Skip to: 17205 + /* 3275 */ MCD_OPC_Decode, + 136, + 10, + 213, + 1, // Opcode: C_LT_S + /* 3280 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 3302 + /* 3285 */ MCD_OPC_CheckPredicate, + 50, + 91, + 54, + 0, // Skip to: 17205 + /* 3290 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 84, + 54, + 0, // Skip to: 17205 + /* 3297 */ MCD_OPC_Decode, + 142, + 10, + 213, + 1, // Opcode: C_NGE_S + /* 3302 */ MCD_OPC_FilterValue, + 62, + 17, + 0, + 0, // Skip to: 3324 + /* 3307 */ MCD_OPC_CheckPredicate, + 50, + 69, + 54, + 0, // Skip to: 17205 + /* 3312 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 62, + 54, + 0, // Skip to: 17205 + /* 3319 */ MCD_OPC_Decode, + 130, + 10, + 213, + 1, // Opcode: C_LE_S + /* 3324 */ MCD_OPC_FilterValue, + 63, + 52, + 54, + 0, // Skip to: 17205 + /* 3329 */ MCD_OPC_CheckPredicate, + 50, + 47, + 54, + 0, // Skip to: 17205 + /* 3334 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 40, + 54, + 0, // Skip to: 17205 + /* 3341 */ MCD_OPC_Decode, + 160, + 10, + 213, + 1, // Opcode: C_NGT_S + /* 3346 */ MCD_OPC_FilterValue, + 17, + 1, + 3, + 0, // Skip to: 4120 + /* 3351 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 3354 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3369 + /* 3359 */ MCD_OPC_CheckPredicate, + 55, + 17, + 54, + 0, // Skip to: 17205 + /* 3364 */ MCD_OPC_Decode, + 145, + 12, + 214, + 1, // Opcode: FADD_D32 + /* 3369 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 3384 + /* 3374 */ MCD_OPC_CheckPredicate, + 55, + 2, + 54, + 0, // Skip to: 17205 + /* 3379 */ MCD_OPC_Decode, + 162, + 13, + 214, + 1, // Opcode: FSUB_D32 + /* 3384 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 3399 + /* 3389 */ MCD_OPC_CheckPredicate, + 55, + 243, + 53, + 0, // Skip to: 17205 + /* 3394 */ MCD_OPC_Decode, + 246, + 12, + 214, + 1, // Opcode: FMUL_D32 + /* 3399 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 3414 + /* 3404 */ MCD_OPC_CheckPredicate, + 55, + 228, + 53, + 0, // Skip to: 17205 + /* 3409 */ MCD_OPC_Decode, + 184, + 12, + 214, + 1, // Opcode: FDIV_D32 + /* 3414 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 3436 + /* 3419 */ MCD_OPC_CheckPredicate, + 57, + 213, + 53, + 0, // Skip to: 17205 + /* 3424 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 206, + 53, + 0, // Skip to: 17205 + /* 3431 */ MCD_OPC_Decode, + 154, + 13, + 215, + 1, // Opcode: FSQRT_D32 + /* 3436 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 3458 + /* 3441 */ MCD_OPC_CheckPredicate, + 55, + 191, + 53, + 0, // Skip to: 17205 + /* 3446 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 184, + 53, + 0, // Skip to: 17205 + /* 3453 */ MCD_OPC_Decode, + 138, + 12, + 215, + 1, // Opcode: FABS_D32 + /* 3458 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 3480 + /* 3463 */ MCD_OPC_CheckPredicate, + 55, + 169, + 53, + 0, // Skip to: 17205 + /* 3468 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 162, + 53, + 0, // Skip to: 17205 + /* 3475 */ MCD_OPC_Decode, + 235, + 12, + 215, + 1, // Opcode: FMOV_D32 + /* 3480 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 3502 + /* 3485 */ MCD_OPC_CheckPredicate, + 55, + 147, + 53, + 0, // Skip to: 17205 + /* 3490 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 140, + 53, + 0, // Skip to: 17205 + /* 3497 */ MCD_OPC_Decode, + 255, + 12, + 215, + 1, // Opcode: FNEG_D32 + /* 3502 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 3524 + /* 3507 */ MCD_OPC_CheckPredicate, + 57, + 125, + 53, + 0, // Skip to: 17205 + /* 3512 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 118, + 53, + 0, // Skip to: 17205 + /* 3519 */ MCD_OPC_Decode, + 209, + 18, + 216, + 1, // Opcode: ROUND_W_D32 + /* 3524 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 3546 + /* 3529 */ MCD_OPC_CheckPredicate, + 57, + 103, + 53, + 0, // Skip to: 17205 + /* 3534 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 96, + 53, + 0, // Skip to: 17205 + /* 3541 */ MCD_OPC_Decode, + 247, + 21, + 216, + 1, // Opcode: TRUNC_W_D32 + /* 3546 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 3568 + /* 3551 */ MCD_OPC_CheckPredicate, + 57, + 81, + 53, + 0, // Skip to: 17205 + /* 3556 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 74, + 53, + 0, // Skip to: 17205 + /* 3563 */ MCD_OPC_Decode, + 159, + 8, + 216, + 1, // Opcode: CEIL_W_D32 + /* 3568 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 3590 + /* 3573 */ MCD_OPC_CheckPredicate, + 57, + 59, + 53, + 0, // Skip to: 17205 + /* 3578 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 52, + 53, + 0, // Skip to: 17205 + /* 3585 */ MCD_OPC_Decode, + 218, + 12, + 216, + 1, // Opcode: FLOOR_W_D32 + /* 3590 */ MCD_OPC_FilterValue, + 17, + 33, + 0, + 0, // Skip to: 3628 + /* 3595 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 3598 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 3613 + /* 3603 */ MCD_OPC_CheckPredicate, + 58, + 29, + 53, + 0, // Skip to: 17205 + /* 3608 */ MCD_OPC_Decode, + 162, + 16, + 217, + 1, // Opcode: MOVF_D32 + /* 3613 */ MCD_OPC_FilterValue, + 1, + 19, + 53, + 0, // Skip to: 17205 + /* 3618 */ MCD_OPC_CheckPredicate, + 58, + 14, + 53, + 0, // Skip to: 17205 + /* 3623 */ MCD_OPC_Decode, + 182, + 16, + 217, + 1, // Opcode: MOVT_D32 + /* 3628 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 3643 + /* 3633 */ MCD_OPC_CheckPredicate, + 58, + 255, + 52, + 0, // Skip to: 17205 + /* 3638 */ MCD_OPC_Decode, + 194, + 16, + 218, + 1, // Opcode: MOVZ_I_D32 + /* 3643 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 3658 + /* 3648 */ MCD_OPC_CheckPredicate, + 58, + 240, + 52, + 0, // Skip to: 17205 + /* 3653 */ MCD_OPC_Decode, + 174, + 16, + 218, + 1, // Opcode: MOVN_I_D32 + /* 3658 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 3680 + /* 3663 */ MCD_OPC_CheckPredicate, + 59, + 225, + 52, + 0, // Skip to: 17205 + /* 3668 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 218, + 52, + 0, // Skip to: 17205 + /* 3675 */ MCD_OPC_Decode, + 183, + 18, + 215, + 1, // Opcode: RECIP_D32 + /* 3680 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 3702 + /* 3685 */ MCD_OPC_CheckPredicate, + 59, + 203, + 52, + 0, // Skip to: 17205 + /* 3690 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 196, + 52, + 0, // Skip to: 17205 + /* 3697 */ MCD_OPC_Decode, + 216, + 18, + 215, + 1, // Opcode: RSQRT_D32 + /* 3702 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 3724 + /* 3707 */ MCD_OPC_CheckPredicate, + 55, + 181, + 52, + 0, // Skip to: 17205 + /* 3712 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 174, + 52, + 0, // Skip to: 17205 + /* 3719 */ MCD_OPC_Decode, + 224, + 9, + 216, + 1, // Opcode: CVT_S_D32 + /* 3724 */ MCD_OPC_FilterValue, + 36, + 17, + 0, + 0, // Skip to: 3746 + /* 3729 */ MCD_OPC_CheckPredicate, + 55, + 159, + 52, + 0, // Skip to: 17205 + /* 3734 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 152, + 52, + 0, // Skip to: 17205 + /* 3741 */ MCD_OPC_Decode, + 235, + 9, + 216, + 1, // Opcode: CVT_W_D32 + /* 3746 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 3768 + /* 3751 */ MCD_OPC_CheckPredicate, + 56, + 137, + 52, + 0, // Skip to: 17205 + /* 3756 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 130, + 52, + 0, // Skip to: 17205 + /* 3763 */ MCD_OPC_Decode, + 215, + 9, + 219, + 1, // Opcode: CVT_L_D64 + /* 3768 */ MCD_OPC_FilterValue, + 48, + 17, + 0, + 0, // Skip to: 3790 + /* 3773 */ MCD_OPC_CheckPredicate, + 60, + 115, + 52, + 0, // Skip to: 17205 + /* 3778 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 108, + 52, + 0, // Skip to: 17205 + /* 3785 */ MCD_OPC_Decode, + 248, + 9, + 220, + 1, // Opcode: C_F_D32 + /* 3790 */ MCD_OPC_FilterValue, + 49, + 17, + 0, + 0, // Skip to: 3812 + /* 3795 */ MCD_OPC_CheckPredicate, + 60, + 93, + 52, + 0, // Skip to: 17205 + /* 3800 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 86, + 52, + 0, // Skip to: 17205 + /* 3807 */ MCD_OPC_Decode, + 204, + 10, + 220, + 1, // Opcode: C_UN_D32 + /* 3812 */ MCD_OPC_FilterValue, + 50, + 17, + 0, + 0, // Skip to: 3834 + /* 3817 */ MCD_OPC_CheckPredicate, + 60, + 71, + 52, + 0, // Skip to: 17205 + /* 3822 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 64, + 52, + 0, // Skip to: 17205 + /* 3829 */ MCD_OPC_Decode, + 242, + 9, + 220, + 1, // Opcode: C_EQ_D32 + /* 3834 */ MCD_OPC_FilterValue, + 51, + 17, + 0, + 0, // Skip to: 3856 + /* 3839 */ MCD_OPC_CheckPredicate, + 60, + 49, + 52, + 0, // Skip to: 17205 + /* 3844 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 42, + 52, + 0, // Skip to: 17205 + /* 3851 */ MCD_OPC_Decode, + 186, + 10, + 220, + 1, // Opcode: C_UEQ_D32 + /* 3856 */ MCD_OPC_FilterValue, + 52, + 17, + 0, + 0, // Skip to: 3878 + /* 3861 */ MCD_OPC_CheckPredicate, + 60, + 27, + 52, + 0, // Skip to: 17205 + /* 3866 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 20, + 52, + 0, // Skip to: 17205 + /* 3873 */ MCD_OPC_Decode, + 168, + 10, + 220, + 1, // Opcode: C_OLT_D32 + /* 3878 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 3900 + /* 3883 */ MCD_OPC_CheckPredicate, + 60, + 5, + 52, + 0, // Skip to: 17205 + /* 3888 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 254, + 51, + 0, // Skip to: 17205 + /* 3895 */ MCD_OPC_Decode, + 198, + 10, + 220, + 1, // Opcode: C_ULT_D32 + /* 3900 */ MCD_OPC_FilterValue, + 54, + 17, + 0, + 0, // Skip to: 3922 + /* 3905 */ MCD_OPC_CheckPredicate, + 60, + 239, + 51, + 0, // Skip to: 17205 + /* 3910 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 232, + 51, + 0, // Skip to: 17205 + /* 3917 */ MCD_OPC_Decode, + 162, + 10, + 220, + 1, // Opcode: C_OLE_D32 + /* 3922 */ MCD_OPC_FilterValue, + 55, + 17, + 0, + 0, // Skip to: 3944 + /* 3927 */ MCD_OPC_CheckPredicate, + 60, + 217, + 51, + 0, // Skip to: 17205 + /* 3932 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 210, + 51, + 0, // Skip to: 17205 + /* 3939 */ MCD_OPC_Decode, + 192, + 10, + 220, + 1, // Opcode: C_ULE_D32 + /* 3944 */ MCD_OPC_FilterValue, + 56, + 17, + 0, + 0, // Skip to: 3966 + /* 3949 */ MCD_OPC_CheckPredicate, + 60, + 195, + 51, + 0, // Skip to: 17205 + /* 3954 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 188, + 51, + 0, // Skip to: 17205 + /* 3961 */ MCD_OPC_Decode, + 180, + 10, + 220, + 1, // Opcode: C_SF_D32 + /* 3966 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 3988 + /* 3971 */ MCD_OPC_CheckPredicate, + 60, + 173, + 51, + 0, // Skip to: 17205 + /* 3976 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 166, + 51, + 0, // Skip to: 17205 + /* 3983 */ MCD_OPC_Decode, + 144, + 10, + 220, + 1, // Opcode: C_NGLE_D32 + /* 3988 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 4010 + /* 3993 */ MCD_OPC_CheckPredicate, + 60, + 151, + 51, + 0, // Skip to: 17205 + /* 3998 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 144, + 51, + 0, // Skip to: 17205 + /* 4005 */ MCD_OPC_Decode, + 174, + 10, + 220, + 1, // Opcode: C_SEQ_D32 + /* 4010 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 4032 + /* 4015 */ MCD_OPC_CheckPredicate, + 60, + 129, + 51, + 0, // Skip to: 17205 + /* 4020 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 122, + 51, + 0, // Skip to: 17205 + /* 4027 */ MCD_OPC_Decode, + 150, + 10, + 220, + 1, // Opcode: C_NGL_D32 + /* 4032 */ MCD_OPC_FilterValue, + 60, + 17, + 0, + 0, // Skip to: 4054 + /* 4037 */ MCD_OPC_CheckPredicate, + 60, + 107, + 51, + 0, // Skip to: 17205 + /* 4042 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 100, + 51, + 0, // Skip to: 17205 + /* 4049 */ MCD_OPC_Decode, + 132, + 10, + 220, + 1, // Opcode: C_LT_D32 + /* 4054 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 4076 + /* 4059 */ MCD_OPC_CheckPredicate, + 60, + 85, + 51, + 0, // Skip to: 17205 + /* 4064 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 78, + 51, + 0, // Skip to: 17205 + /* 4071 */ MCD_OPC_Decode, + 138, + 10, + 220, + 1, // Opcode: C_NGE_D32 + /* 4076 */ MCD_OPC_FilterValue, + 62, + 17, + 0, + 0, // Skip to: 4098 + /* 4081 */ MCD_OPC_CheckPredicate, + 60, + 63, + 51, + 0, // Skip to: 17205 + /* 4086 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 56, + 51, + 0, // Skip to: 17205 + /* 4093 */ MCD_OPC_Decode, + 254, + 9, + 220, + 1, // Opcode: C_LE_D32 + /* 4098 */ MCD_OPC_FilterValue, + 63, + 46, + 51, + 0, // Skip to: 17205 + /* 4103 */ MCD_OPC_CheckPredicate, + 60, + 41, + 51, + 0, // Skip to: 17205 + /* 4108 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 34, + 51, + 0, // Skip to: 17205 + /* 4115 */ MCD_OPC_Decode, + 156, + 10, + 220, + 1, // Opcode: C_NGT_D32 + /* 4120 */ MCD_OPC_FilterValue, + 20, + 47, + 0, + 0, // Skip to: 4172 + /* 4125 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 4128 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 4150 + /* 4133 */ MCD_OPC_CheckPredicate, + 47, + 11, + 51, + 0, // Skip to: 17205 + /* 4138 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 4, + 51, + 0, // Skip to: 17205 + /* 4145 */ MCD_OPC_Decode, + 232, + 9, + 208, + 1, // Opcode: CVT_S_W + /* 4150 */ MCD_OPC_FilterValue, + 33, + 250, + 50, + 0, // Skip to: 17205 + /* 4155 */ MCD_OPC_CheckPredicate, + 55, + 245, + 50, + 0, // Skip to: 17205 + /* 4160 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 238, + 50, + 0, // Skip to: 17205 + /* 4167 */ MCD_OPC_Decode, + 207, + 9, + 211, + 1, // Opcode: CVT_D32_W + /* 4172 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 4187 + /* 4177 */ MCD_OPC_CheckPredicate, + 30, + 223, + 50, + 0, // Skip to: 17205 + /* 4182 */ MCD_OPC_Decode, + 133, + 8, + 206, + 1, // Opcode: BZ_B + /* 4187 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 4202 + /* 4192 */ MCD_OPC_CheckPredicate, + 30, + 208, + 50, + 0, // Skip to: 17205 + /* 4197 */ MCD_OPC_Decode, + 135, + 8, + 221, + 1, // Opcode: BZ_H + /* 4202 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 4217 + /* 4207 */ MCD_OPC_CheckPredicate, + 30, + 193, + 50, + 0, // Skip to: 17205 + /* 4212 */ MCD_OPC_Decode, + 137, + 8, + 222, + 1, // Opcode: BZ_W + /* 4217 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 4232 + /* 4222 */ MCD_OPC_CheckPredicate, + 30, + 178, + 50, + 0, // Skip to: 17205 + /* 4227 */ MCD_OPC_Decode, + 134, + 8, + 223, + 1, // Opcode: BZ_D + /* 4232 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 4247 + /* 4237 */ MCD_OPC_CheckPredicate, + 30, + 163, + 50, + 0, // Skip to: 17205 + /* 4242 */ MCD_OPC_Decode, + 236, + 7, + 206, + 1, // Opcode: BNZ_B + /* 4247 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 4262 + /* 4252 */ MCD_OPC_CheckPredicate, + 30, + 148, + 50, + 0, // Skip to: 17205 + /* 4257 */ MCD_OPC_Decode, + 238, + 7, + 221, + 1, // Opcode: BNZ_H + /* 4262 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 4277 + /* 4267 */ MCD_OPC_CheckPredicate, + 30, + 133, + 50, + 0, // Skip to: 17205 + /* 4272 */ MCD_OPC_Decode, + 240, + 7, + 222, + 1, // Opcode: BNZ_W + /* 4277 */ MCD_OPC_FilterValue, + 31, + 123, + 50, + 0, // Skip to: 17205 + /* 4282 */ MCD_OPC_CheckPredicate, + 30, + 118, + 50, + 0, // Skip to: 17205 + /* 4287 */ MCD_OPC_Decode, + 237, + 7, + 223, + 1, // Opcode: BNZ_D + /* 4292 */ MCD_OPC_FilterValue, + 18, + 115, + 0, + 0, // Skip to: 4412 + /* 4297 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 4300 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4322 + /* 4305 */ MCD_OPC_CheckPredicate, + 27, + 95, + 50, + 0, // Skip to: 17205 + /* 4310 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 88, + 50, + 0, // Skip to: 17205 + /* 4317 */ MCD_OPC_Decode, + 218, + 15, + 224, + 1, // Opcode: MFC2 + /* 4322 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 4344 + /* 4327 */ MCD_OPC_CheckPredicate, + 27, + 73, + 50, + 0, // Skip to: 17205 + /* 4332 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 66, + 50, + 0, // Skip to: 17205 + /* 4339 */ MCD_OPC_Decode, + 234, + 16, + 225, + 1, // Opcode: MTC2 + /* 4344 */ MCD_OPC_FilterValue, + 8, + 56, + 50, + 0, // Skip to: 17205 + /* 4349 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 4352 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4367 + /* 4357 */ MCD_OPC_CheckPredicate, + 50, + 43, + 50, + 0, // Skip to: 17205 + /* 4362 */ MCD_OPC_Decode, + 225, + 6, + 205, + 1, // Opcode: BC2F + /* 4367 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4382 + /* 4372 */ MCD_OPC_CheckPredicate, + 50, + 28, + 50, + 0, // Skip to: 17205 + /* 4377 */ MCD_OPC_Decode, + 229, + 6, + 205, + 1, // Opcode: BC2T + /* 4382 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 4397 + /* 4387 */ MCD_OPC_CheckPredicate, + 51, + 13, + 50, + 0, // Skip to: 17205 + /* 4392 */ MCD_OPC_Decode, + 226, + 6, + 205, + 1, // Opcode: BC2FL + /* 4397 */ MCD_OPC_FilterValue, + 3, + 3, + 50, + 0, // Skip to: 17205 + /* 4402 */ MCD_OPC_CheckPredicate, + 51, + 254, + 49, + 0, // Skip to: 17205 + /* 4407 */ MCD_OPC_Decode, + 230, + 6, + 205, + 1, // Opcode: BC2TL + /* 4412 */ MCD_OPC_FilterValue, + 19, + 70, + 1, + 0, // Skip to: 4743 + /* 4417 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 4420 */ MCD_OPC_FilterValue, + 8, + 63, + 0, + 0, // Skip to: 4488 + /* 4425 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 4428 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4443 + /* 4433 */ MCD_OPC_CheckPredicate, + 50, + 50, + 0, + 0, // Skip to: 4488 + /* 4438 */ MCD_OPC_Decode, + 231, + 6, + 205, + 1, // Opcode: BC3F + /* 4443 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4458 + /* 4448 */ MCD_OPC_CheckPredicate, + 50, + 35, + 0, + 0, // Skip to: 4488 + /* 4453 */ MCD_OPC_Decode, + 233, + 6, + 205, + 1, // Opcode: BC3T + /* 4458 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 4473 + /* 4463 */ MCD_OPC_CheckPredicate, + 51, + 20, + 0, + 0, // Skip to: 4488 + /* 4468 */ MCD_OPC_Decode, + 232, + 6, + 205, + 1, // Opcode: BC3FL + /* 4473 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 4488 + /* 4478 */ MCD_OPC_CheckPredicate, + 51, + 5, + 0, + 0, // Skip to: 4488 + /* 4483 */ MCD_OPC_Decode, + 234, + 6, + 205, + 1, // Opcode: BC3TL + /* 4488 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 4491 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4513 + /* 4496 */ MCD_OPC_CheckPredicate, + 61, + 160, + 49, + 0, // Skip to: 17205 + /* 4501 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 153, + 49, + 0, // Skip to: 17205 + /* 4508 */ MCD_OPC_Decode, + 133, + 15, + 226, + 1, // Opcode: LWXC1 + /* 4513 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 4535 + /* 4518 */ MCD_OPC_CheckPredicate, + 62, + 138, + 49, + 0, // Skip to: 17205 + /* 4523 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 131, + 49, + 0, // Skip to: 17205 + /* 4530 */ MCD_OPC_Decode, + 183, + 14, + 227, + 1, // Opcode: LDXC1 + /* 4535 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 4557 + /* 4540 */ MCD_OPC_CheckPredicate, + 63, + 116, + 49, + 0, // Skip to: 17205 + /* 4545 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 109, + 49, + 0, // Skip to: 17205 + /* 4552 */ MCD_OPC_Decode, + 221, + 14, + 227, + 1, // Opcode: LUXC1 + /* 4557 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 4579 + /* 4562 */ MCD_OPC_CheckPredicate, + 61, + 94, + 49, + 0, // Skip to: 17205 + /* 4567 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 87, + 49, + 0, // Skip to: 17205 + /* 4574 */ MCD_OPC_Decode, + 163, + 21, + 228, + 1, // Opcode: SWXC1 + /* 4579 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 4601 + /* 4584 */ MCD_OPC_CheckPredicate, + 62, + 72, + 49, + 0, // Skip to: 17205 + /* 4589 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 65, + 49, + 0, // Skip to: 17205 + /* 4596 */ MCD_OPC_Decode, + 143, + 19, + 229, + 1, // Opcode: SDXC1 + /* 4601 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 4623 + /* 4606 */ MCD_OPC_CheckPredicate, + 63, + 50, + 49, + 0, // Skip to: 17205 + /* 4611 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 43, + 49, + 0, // Skip to: 17205 + /* 4618 */ MCD_OPC_Decode, + 130, + 21, + 229, + 1, // Opcode: SUXC1 + /* 4623 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 4638 + /* 4628 */ MCD_OPC_CheckPredicate, + 64, + 28, + 49, + 0, // Skip to: 17205 + /* 4633 */ MCD_OPC_Decode, + 174, + 15, + 230, + 1, // Opcode: MADD_S + /* 4638 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 4653 + /* 4643 */ MCD_OPC_CheckPredicate, + 65, + 13, + 49, + 0, // Skip to: 17205 + /* 4648 */ MCD_OPC_Decode, + 166, + 15, + 231, + 1, // Opcode: MADD_D32 + /* 4653 */ MCD_OPC_FilterValue, + 40, + 10, + 0, + 0, // Skip to: 4668 + /* 4658 */ MCD_OPC_CheckPredicate, + 64, + 254, + 48, + 0, // Skip to: 17205 + /* 4663 */ MCD_OPC_Decode, + 225, + 16, + 230, + 1, // Opcode: MSUB_S + /* 4668 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 4683 + /* 4673 */ MCD_OPC_CheckPredicate, + 65, + 239, + 48, + 0, // Skip to: 17205 + /* 4678 */ MCD_OPC_Decode, + 217, + 16, + 231, + 1, // Opcode: MSUB_D32 + /* 4683 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 4698 + /* 4688 */ MCD_OPC_CheckPredicate, + 66, + 224, + 48, + 0, // Skip to: 17205 + /* 4693 */ MCD_OPC_Decode, + 203, + 17, + 230, + 1, // Opcode: NMADD_S + /* 4698 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 4713 + /* 4703 */ MCD_OPC_CheckPredicate, + 67, + 209, + 48, + 0, // Skip to: 17205 + /* 4708 */ MCD_OPC_Decode, + 200, + 17, + 231, + 1, // Opcode: NMADD_D32 + /* 4713 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 4728 + /* 4718 */ MCD_OPC_CheckPredicate, + 66, + 194, + 48, + 0, // Skip to: 17205 + /* 4723 */ MCD_OPC_Decode, + 208, + 17, + 230, + 1, // Opcode: NMSUB_S + /* 4728 */ MCD_OPC_FilterValue, + 57, + 184, + 48, + 0, // Skip to: 17205 + /* 4733 */ MCD_OPC_CheckPredicate, + 67, + 179, + 48, + 0, // Skip to: 17205 + /* 4738 */ MCD_OPC_Decode, + 205, + 17, + 231, + 1, // Opcode: NMSUB_D32 + /* 4743 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 4758 + /* 4748 */ MCD_OPC_CheckPredicate, + 39, + 164, + 48, + 0, // Skip to: 17205 + /* 4753 */ MCD_OPC_Decode, + 249, + 6, + 190, + 1, // Opcode: BEQL + /* 4758 */ MCD_OPC_FilterValue, + 21, + 107, + 0, + 0, // Skip to: 4870 + /* 4763 */ MCD_OPC_ExtractField, + 0, + 16, // Inst{15-0} ... + /* 4766 */ MCD_OPC_FilterValue, + 123, + 9, + 0, + 0, // Skip to: 4780 + /* 4771 */ MCD_OPC_CheckPredicate, + 19, + 19, + 0, + 0, // Skip to: 4795 + /* 4776 */ MCD_OPC_Decode, + 241, + 12, + 113, // Opcode: FMOV_S_MM + /* 4780 */ MCD_OPC_FilterValue, + 251, + 22, + 9, + 0, + 0, // Skip to: 4795 + /* 4786 */ MCD_OPC_CheckPredicate, + 19, + 4, + 0, + 0, // Skip to: 4795 + /* 4791 */ MCD_OPC_Decode, + 132, + 13, + 113, // Opcode: FNEG_S_MM + /* 4795 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 4798 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 4813 + /* 4803 */ MCD_OPC_CheckPredicate, + 19, + 52, + 0, + 0, // Skip to: 4860 + /* 4808 */ MCD_OPC_Decode, + 151, + 12, + 153, + 1, // Opcode: FADD_S_MM + /* 4813 */ MCD_OPC_FilterValue, + 112, + 10, + 0, + 0, // Skip to: 4828 + /* 4818 */ MCD_OPC_CheckPredicate, + 19, + 37, + 0, + 0, // Skip to: 4860 + /* 4823 */ MCD_OPC_Decode, + 168, + 13, + 153, + 1, // Opcode: FSUB_S_MM + /* 4828 */ MCD_OPC_FilterValue, + 176, + 1, + 10, + 0, + 0, // Skip to: 4844 + /* 4834 */ MCD_OPC_CheckPredicate, + 19, + 21, + 0, + 0, // Skip to: 4860 + /* 4839 */ MCD_OPC_Decode, + 252, + 12, + 153, + 1, // Opcode: FMUL_S_MM + /* 4844 */ MCD_OPC_FilterValue, + 240, + 1, + 10, + 0, + 0, // Skip to: 4860 + /* 4850 */ MCD_OPC_CheckPredicate, + 19, + 5, + 0, + 0, // Skip to: 4860 + /* 4855 */ MCD_OPC_Decode, + 189, + 12, + 153, + 1, // Opcode: FDIV_S_MM + /* 4860 */ MCD_OPC_CheckPredicate, + 39, + 52, + 48, + 0, // Skip to: 17205 + /* 4865 */ MCD_OPC_Decode, + 224, + 7, + 190, + 1, // Opcode: BNEL + /* 4870 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 4892 + /* 4875 */ MCD_OPC_CheckPredicate, + 39, + 37, + 48, + 0, // Skip to: 17205 + /* 4880 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 30, + 48, + 0, // Skip to: 17205 + /* 4887 */ MCD_OPC_Decode, + 186, + 7, + 186, + 1, // Opcode: BLEZL + /* 4892 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 4914 + /* 4897 */ MCD_OPC_CheckPredicate, + 39, + 15, + 48, + 0, // Skip to: 17205 + /* 4902 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 8, + 48, + 0, // Skip to: 17205 + /* 4909 */ MCD_OPC_Decode, + 157, + 7, + 186, + 1, // Opcode: BGTZL + /* 4914 */ MCD_OPC_FilterValue, + 28, + 15, + 1, + 0, // Skip to: 5190 + /* 4919 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 4922 */ MCD_OPC_FilterValue, + 0, + 42, + 0, + 0, // Skip to: 4969 + /* 4927 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4930 */ MCD_OPC_FilterValue, + 0, + 238, + 47, + 0, // Skip to: 17205 + /* 4935 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4938 */ MCD_OPC_FilterValue, + 0, + 230, + 47, + 0, // Skip to: 17205 + /* 4943 */ MCD_OPC_CheckPredicate, + 68, + 11, + 0, + 0, // Skip to: 4959 + /* 4948 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 4959 + /* 4955 */ MCD_OPC_Decode, + 151, + 15, + 69, // Opcode: MADD + /* 4959 */ MCD_OPC_CheckPredicate, + 37, + 209, + 47, + 0, // Skip to: 17205 + /* 4964 */ MCD_OPC_Decode, + 169, + 15, + 232, + 1, // Opcode: MADD_DSP + /* 4969 */ MCD_OPC_FilterValue, + 1, + 42, + 0, + 0, // Skip to: 5016 + /* 4974 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 4977 */ MCD_OPC_FilterValue, + 0, + 191, + 47, + 0, // Skip to: 17205 + /* 4982 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 4985 */ MCD_OPC_FilterValue, + 0, + 183, + 47, + 0, // Skip to: 17205 + /* 4990 */ MCD_OPC_CheckPredicate, + 68, + 11, + 0, + 0, // Skip to: 5006 + /* 4995 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 5006 + /* 5002 */ MCD_OPC_Decode, + 158, + 15, + 69, // Opcode: MADDU + /* 5006 */ MCD_OPC_CheckPredicate, + 37, + 162, + 47, + 0, // Skip to: 17205 + /* 5011 */ MCD_OPC_Decode, + 159, + 15, + 232, + 1, // Opcode: MADDU_DSP + /* 5016 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 5037 + /* 5021 */ MCD_OPC_CheckPredicate, + 68, + 147, + 47, + 0, // Skip to: 17205 + /* 5026 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 140, + 47, + 0, // Skip to: 17205 + /* 5033 */ MCD_OPC_Decode, + 141, + 17, + 50, // Opcode: MUL + /* 5037 */ MCD_OPC_FilterValue, + 4, + 42, + 0, + 0, // Skip to: 5084 + /* 5042 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 5045 */ MCD_OPC_FilterValue, + 0, + 123, + 47, + 0, // Skip to: 17205 + /* 5050 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5053 */ MCD_OPC_FilterValue, + 0, + 115, + 47, + 0, // Skip to: 17205 + /* 5058 */ MCD_OPC_CheckPredicate, + 68, + 11, + 0, + 0, // Skip to: 5074 + /* 5063 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 5074 + /* 5070 */ MCD_OPC_Decode, + 202, + 16, + 69, // Opcode: MSUB + /* 5074 */ MCD_OPC_CheckPredicate, + 37, + 94, + 47, + 0, // Skip to: 17205 + /* 5079 */ MCD_OPC_Decode, + 220, + 16, + 232, + 1, // Opcode: MSUB_DSP + /* 5084 */ MCD_OPC_FilterValue, + 5, + 42, + 0, + 0, // Skip to: 5131 + /* 5089 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 5092 */ MCD_OPC_FilterValue, + 0, + 76, + 47, + 0, // Skip to: 17205 + /* 5097 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 5100 */ MCD_OPC_FilterValue, + 0, + 68, + 47, + 0, // Skip to: 17205 + /* 5105 */ MCD_OPC_CheckPredicate, + 68, + 11, + 0, + 0, // Skip to: 5121 + /* 5110 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 5121 + /* 5117 */ MCD_OPC_Decode, + 209, + 16, + 69, // Opcode: MSUBU + /* 5121 */ MCD_OPC_CheckPredicate, + 37, + 47, + 47, + 0, // Skip to: 17205 + /* 5126 */ MCD_OPC_Decode, + 210, + 16, + 232, + 1, // Opcode: MSUBU_DSP + /* 5131 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 5153 + /* 5136 */ MCD_OPC_CheckPredicate, + 68, + 32, + 47, + 0, // Skip to: 17205 + /* 5141 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 25, + 47, + 0, // Skip to: 17205 + /* 5148 */ MCD_OPC_Decode, + 222, + 8, + 233, + 1, // Opcode: CLZ + /* 5153 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 5175 + /* 5158 */ MCD_OPC_CheckPredicate, + 68, + 10, + 47, + 0, // Skip to: 17205 + /* 5163 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 3, + 47, + 0, // Skip to: 17205 + /* 5170 */ MCD_OPC_Decode, + 202, + 8, + 233, + 1, // Opcode: CLO + /* 5175 */ MCD_OPC_FilterValue, + 63, + 249, + 46, + 0, // Skip to: 17205 + /* 5180 */ MCD_OPC_CheckPredicate, + 68, + 244, + 46, + 0, // Skip to: 17205 + /* 5185 */ MCD_OPC_Decode, + 253, + 18, + 177, + 1, // Opcode: SDBBP + /* 5190 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 5205 + /* 5195 */ MCD_OPC_CheckPredicate, + 68, + 229, + 46, + 0, // Skip to: 17205 + /* 5200 */ MCD_OPC_Decode, + 252, + 13, + 189, + 1, // Opcode: JALX + /* 5205 */ MCD_OPC_FilterValue, + 30, + 201, + 32, + 0, // Skip to: 13603 + /* 5210 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 5213 */ MCD_OPC_FilterValue, + 0, + 63, + 0, + 0, // Skip to: 5281 + /* 5218 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 5221 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5236 + /* 5226 */ MCD_OPC_CheckPredicate, + 30, + 198, + 46, + 0, // Skip to: 17205 + /* 5231 */ MCD_OPC_Decode, + 151, + 6, + 234, + 1, // Opcode: ANDI_B + /* 5236 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5251 + /* 5241 */ MCD_OPC_CheckPredicate, + 30, + 183, + 46, + 0, // Skip to: 17205 + /* 5246 */ MCD_OPC_Decode, + 224, + 17, + 234, + 1, // Opcode: ORI_B + /* 5251 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5266 + /* 5256 */ MCD_OPC_CheckPredicate, + 30, + 168, + 46, + 0, // Skip to: 17205 + /* 5261 */ MCD_OPC_Decode, + 212, + 17, + 234, + 1, // Opcode: NORI_B + /* 5266 */ MCD_OPC_FilterValue, + 3, + 158, + 46, + 0, // Skip to: 17205 + /* 5271 */ MCD_OPC_CheckPredicate, + 30, + 153, + 46, + 0, // Skip to: 17205 + /* 5276 */ MCD_OPC_Decode, + 149, + 22, + 234, + 1, // Opcode: XORI_B + /* 5281 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 5334 + /* 5286 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 5289 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5304 + /* 5294 */ MCD_OPC_CheckPredicate, + 30, + 130, + 46, + 0, // Skip to: 17205 + /* 5299 */ MCD_OPC_Decode, + 207, + 7, + 235, + 1, // Opcode: BMNZI_B + /* 5304 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5319 + /* 5309 */ MCD_OPC_CheckPredicate, + 30, + 115, + 46, + 0, // Skip to: 17205 + /* 5314 */ MCD_OPC_Decode, + 209, + 7, + 235, + 1, // Opcode: BMZI_B + /* 5319 */ MCD_OPC_FilterValue, + 2, + 105, + 46, + 0, // Skip to: 17205 + /* 5324 */ MCD_OPC_CheckPredicate, + 30, + 100, + 46, + 0, // Skip to: 17205 + /* 5329 */ MCD_OPC_Decode, + 251, + 7, + 235, + 1, // Opcode: BSELI_B + /* 5334 */ MCD_OPC_FilterValue, + 2, + 48, + 0, + 0, // Skip to: 5387 + /* 5339 */ MCD_OPC_ExtractField, + 24, + 2, // Inst{25-24} ... + /* 5342 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5357 + /* 5347 */ MCD_OPC_CheckPredicate, + 30, + 77, + 46, + 0, // Skip to: 17205 + /* 5352 */ MCD_OPC_Decode, + 177, + 19, + 234, + 1, // Opcode: SHF_B + /* 5357 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5372 + /* 5362 */ MCD_OPC_CheckPredicate, + 30, + 62, + 46, + 0, // Skip to: 17205 + /* 5367 */ MCD_OPC_Decode, + 178, + 19, + 236, + 1, // Opcode: SHF_H + /* 5372 */ MCD_OPC_FilterValue, + 2, + 52, + 46, + 0, // Skip to: 17205 + /* 5377 */ MCD_OPC_CheckPredicate, + 30, + 47, + 46, + 0, // Skip to: 17205 + /* 5382 */ MCD_OPC_Decode, + 179, + 19, + 237, + 1, // Opcode: SHF_W + /* 5387 */ MCD_OPC_FilterValue, + 6, + 107, + 1, + 0, // Skip to: 5755 + /* 5392 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 5395 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5410 + /* 5400 */ MCD_OPC_CheckPredicate, + 30, + 24, + 46, + 0, // Skip to: 17205 + /* 5405 */ MCD_OPC_Decode, + 247, + 5, + 238, + 1, // Opcode: ADDVI_B + /* 5410 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5425 + /* 5415 */ MCD_OPC_CheckPredicate, + 30, + 9, + 46, + 0, // Skip to: 17205 + /* 5420 */ MCD_OPC_Decode, + 249, + 5, + 239, + 1, // Opcode: ADDVI_H + /* 5425 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5440 + /* 5430 */ MCD_OPC_CheckPredicate, + 30, + 250, + 45, + 0, // Skip to: 17205 + /* 5435 */ MCD_OPC_Decode, + 250, + 5, + 240, + 1, // Opcode: ADDVI_W + /* 5440 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5455 + /* 5445 */ MCD_OPC_CheckPredicate, + 30, + 235, + 45, + 0, // Skip to: 17205 + /* 5450 */ MCD_OPC_Decode, + 248, + 5, + 241, + 1, // Opcode: ADDVI_D + /* 5455 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 5470 + /* 5460 */ MCD_OPC_CheckPredicate, + 30, + 220, + 45, + 0, // Skip to: 17205 + /* 5465 */ MCD_OPC_Decode, + 246, + 20, + 238, + 1, // Opcode: SUBVI_B + /* 5470 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 5485 + /* 5475 */ MCD_OPC_CheckPredicate, + 30, + 205, + 45, + 0, // Skip to: 17205 + /* 5480 */ MCD_OPC_Decode, + 248, + 20, + 239, + 1, // Opcode: SUBVI_H + /* 5485 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 5500 + /* 5490 */ MCD_OPC_CheckPredicate, + 30, + 190, + 45, + 0, // Skip to: 17205 + /* 5495 */ MCD_OPC_Decode, + 249, + 20, + 240, + 1, // Opcode: SUBVI_W + /* 5500 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 5515 + /* 5505 */ MCD_OPC_CheckPredicate, + 30, + 175, + 45, + 0, // Skip to: 17205 + /* 5510 */ MCD_OPC_Decode, + 247, + 20, + 241, + 1, // Opcode: SUBVI_D + /* 5515 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 5530 + /* 5520 */ MCD_OPC_CheckPredicate, + 30, + 160, + 45, + 0, // Skip to: 17205 + /* 5525 */ MCD_OPC_Decode, + 188, + 15, + 238, + 1, // Opcode: MAXI_S_B + /* 5530 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 5545 + /* 5535 */ MCD_OPC_CheckPredicate, + 30, + 145, + 45, + 0, // Skip to: 17205 + /* 5540 */ MCD_OPC_Decode, + 190, + 15, + 239, + 1, // Opcode: MAXI_S_H + /* 5545 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 5560 + /* 5550 */ MCD_OPC_CheckPredicate, + 30, + 130, + 45, + 0, // Skip to: 17205 + /* 5555 */ MCD_OPC_Decode, + 191, + 15, + 240, + 1, // Opcode: MAXI_S_W + /* 5560 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 5575 + /* 5565 */ MCD_OPC_CheckPredicate, + 30, + 115, + 45, + 0, // Skip to: 17205 + /* 5570 */ MCD_OPC_Decode, + 189, + 15, + 241, + 1, // Opcode: MAXI_S_D + /* 5575 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 5590 + /* 5580 */ MCD_OPC_CheckPredicate, + 30, + 100, + 45, + 0, // Skip to: 17205 + /* 5585 */ MCD_OPC_Decode, + 192, + 15, + 238, + 1, // Opcode: MAXI_U_B + /* 5590 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5605 + /* 5595 */ MCD_OPC_CheckPredicate, + 30, + 85, + 45, + 0, // Skip to: 17205 + /* 5600 */ MCD_OPC_Decode, + 194, + 15, + 239, + 1, // Opcode: MAXI_U_H + /* 5605 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 5620 + /* 5610 */ MCD_OPC_CheckPredicate, + 30, + 70, + 45, + 0, // Skip to: 17205 + /* 5615 */ MCD_OPC_Decode, + 195, + 15, + 240, + 1, // Opcode: MAXI_U_W + /* 5620 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5635 + /* 5625 */ MCD_OPC_CheckPredicate, + 30, + 55, + 45, + 0, // Skip to: 17205 + /* 5630 */ MCD_OPC_Decode, + 193, + 15, + 241, + 1, // Opcode: MAXI_U_D + /* 5635 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 5650 + /* 5640 */ MCD_OPC_CheckPredicate, + 30, + 40, + 45, + 0, // Skip to: 17205 + /* 5645 */ MCD_OPC_Decode, + 247, + 15, + 238, + 1, // Opcode: MINI_S_B + /* 5650 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 5665 + /* 5655 */ MCD_OPC_CheckPredicate, + 30, + 25, + 45, + 0, // Skip to: 17205 + /* 5660 */ MCD_OPC_Decode, + 249, + 15, + 239, + 1, // Opcode: MINI_S_H + /* 5665 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 5680 + /* 5670 */ MCD_OPC_CheckPredicate, + 30, + 10, + 45, + 0, // Skip to: 17205 + /* 5675 */ MCD_OPC_Decode, + 250, + 15, + 240, + 1, // Opcode: MINI_S_W + /* 5680 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 5695 + /* 5685 */ MCD_OPC_CheckPredicate, + 30, + 251, + 44, + 0, // Skip to: 17205 + /* 5690 */ MCD_OPC_Decode, + 248, + 15, + 241, + 1, // Opcode: MINI_S_D + /* 5695 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 5710 + /* 5700 */ MCD_OPC_CheckPredicate, + 30, + 236, + 44, + 0, // Skip to: 17205 + /* 5705 */ MCD_OPC_Decode, + 251, + 15, + 238, + 1, // Opcode: MINI_U_B + /* 5710 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 5725 + /* 5715 */ MCD_OPC_CheckPredicate, + 30, + 221, + 44, + 0, // Skip to: 17205 + /* 5720 */ MCD_OPC_Decode, + 253, + 15, + 239, + 1, // Opcode: MINI_U_H + /* 5725 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 5740 + /* 5730 */ MCD_OPC_CheckPredicate, + 30, + 206, + 44, + 0, // Skip to: 17205 + /* 5735 */ MCD_OPC_Decode, + 254, + 15, + 240, + 1, // Opcode: MINI_U_W + /* 5740 */ MCD_OPC_FilterValue, + 23, + 196, + 44, + 0, // Skip to: 17205 + /* 5745 */ MCD_OPC_CheckPredicate, + 30, + 191, + 44, + 0, // Skip to: 17205 + /* 5750 */ MCD_OPC_Decode, + 252, + 15, + 241, + 1, // Opcode: MINI_U_D + /* 5755 */ MCD_OPC_FilterValue, + 7, + 107, + 1, + 0, // Skip to: 6123 + /* 5760 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 5763 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5778 + /* 5768 */ MCD_OPC_CheckPredicate, + 30, + 168, + 44, + 0, // Skip to: 17205 + /* 5773 */ MCD_OPC_Decode, + 166, + 8, + 238, + 1, // Opcode: CEQI_B + /* 5778 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5793 + /* 5783 */ MCD_OPC_CheckPredicate, + 30, + 153, + 44, + 0, // Skip to: 17205 + /* 5788 */ MCD_OPC_Decode, + 168, + 8, + 239, + 1, // Opcode: CEQI_H + /* 5793 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5808 + /* 5798 */ MCD_OPC_CheckPredicate, + 30, + 138, + 44, + 0, // Skip to: 17205 + /* 5803 */ MCD_OPC_Decode, + 169, + 8, + 240, + 1, // Opcode: CEQI_W + /* 5808 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5823 + /* 5813 */ MCD_OPC_CheckPredicate, + 30, + 123, + 44, + 0, // Skip to: 17205 + /* 5818 */ MCD_OPC_Decode, + 167, + 8, + 241, + 1, // Opcode: CEQI_D + /* 5823 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 5838 + /* 5828 */ MCD_OPC_CheckPredicate, + 30, + 108, + 44, + 0, // Skip to: 17205 + /* 5833 */ MCD_OPC_Decode, + 206, + 8, + 238, + 1, // Opcode: CLTI_S_B + /* 5838 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 5853 + /* 5843 */ MCD_OPC_CheckPredicate, + 30, + 93, + 44, + 0, // Skip to: 17205 + /* 5848 */ MCD_OPC_Decode, + 208, + 8, + 239, + 1, // Opcode: CLTI_S_H + /* 5853 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 5868 + /* 5858 */ MCD_OPC_CheckPredicate, + 30, + 78, + 44, + 0, // Skip to: 17205 + /* 5863 */ MCD_OPC_Decode, + 209, + 8, + 240, + 1, // Opcode: CLTI_S_W + /* 5868 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 5883 + /* 5873 */ MCD_OPC_CheckPredicate, + 30, + 63, + 44, + 0, // Skip to: 17205 + /* 5878 */ MCD_OPC_Decode, + 207, + 8, + 241, + 1, // Opcode: CLTI_S_D + /* 5883 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 5898 + /* 5888 */ MCD_OPC_CheckPredicate, + 30, + 48, + 44, + 0, // Skip to: 17205 + /* 5893 */ MCD_OPC_Decode, + 210, + 8, + 238, + 1, // Opcode: CLTI_U_B + /* 5898 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 5913 + /* 5903 */ MCD_OPC_CheckPredicate, + 30, + 33, + 44, + 0, // Skip to: 17205 + /* 5908 */ MCD_OPC_Decode, + 212, + 8, + 239, + 1, // Opcode: CLTI_U_H + /* 5913 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 5928 + /* 5918 */ MCD_OPC_CheckPredicate, + 30, + 18, + 44, + 0, // Skip to: 17205 + /* 5923 */ MCD_OPC_Decode, + 213, + 8, + 240, + 1, // Opcode: CLTI_U_W + /* 5928 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 5943 + /* 5933 */ MCD_OPC_CheckPredicate, + 30, + 3, + 44, + 0, // Skip to: 17205 + /* 5938 */ MCD_OPC_Decode, + 211, + 8, + 241, + 1, // Opcode: CLTI_U_D + /* 5943 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 5958 + /* 5948 */ MCD_OPC_CheckPredicate, + 30, + 244, + 43, + 0, // Skip to: 17205 + /* 5953 */ MCD_OPC_Decode, + 186, + 8, + 238, + 1, // Opcode: CLEI_S_B + /* 5958 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 5973 + /* 5963 */ MCD_OPC_CheckPredicate, + 30, + 229, + 43, + 0, // Skip to: 17205 + /* 5968 */ MCD_OPC_Decode, + 188, + 8, + 239, + 1, // Opcode: CLEI_S_H + /* 5973 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 5988 + /* 5978 */ MCD_OPC_CheckPredicate, + 30, + 214, + 43, + 0, // Skip to: 17205 + /* 5983 */ MCD_OPC_Decode, + 189, + 8, + 240, + 1, // Opcode: CLEI_S_W + /* 5988 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 6003 + /* 5993 */ MCD_OPC_CheckPredicate, + 30, + 199, + 43, + 0, // Skip to: 17205 + /* 5998 */ MCD_OPC_Decode, + 187, + 8, + 241, + 1, // Opcode: CLEI_S_D + /* 6003 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 6018 + /* 6008 */ MCD_OPC_CheckPredicate, + 30, + 184, + 43, + 0, // Skip to: 17205 + /* 6013 */ MCD_OPC_Decode, + 190, + 8, + 238, + 1, // Opcode: CLEI_U_B + /* 6018 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 6033 + /* 6023 */ MCD_OPC_CheckPredicate, + 30, + 169, + 43, + 0, // Skip to: 17205 + /* 6028 */ MCD_OPC_Decode, + 192, + 8, + 239, + 1, // Opcode: CLEI_U_H + /* 6033 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 6048 + /* 6038 */ MCD_OPC_CheckPredicate, + 30, + 154, + 43, + 0, // Skip to: 17205 + /* 6043 */ MCD_OPC_Decode, + 193, + 8, + 240, + 1, // Opcode: CLEI_U_W + /* 6048 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 6063 + /* 6053 */ MCD_OPC_CheckPredicate, + 30, + 139, + 43, + 0, // Skip to: 17205 + /* 6058 */ MCD_OPC_Decode, + 191, + 8, + 241, + 1, // Opcode: CLEI_U_D + /* 6063 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 6078 + /* 6068 */ MCD_OPC_CheckPredicate, + 30, + 124, + 43, + 0, // Skip to: 17205 + /* 6073 */ MCD_OPC_Decode, + 176, + 14, + 242, + 1, // Opcode: LDI_B + /* 6078 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 6093 + /* 6083 */ MCD_OPC_CheckPredicate, + 30, + 109, + 43, + 0, // Skip to: 17205 + /* 6088 */ MCD_OPC_Decode, + 178, + 14, + 243, + 1, // Opcode: LDI_H + /* 6093 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 6108 + /* 6098 */ MCD_OPC_CheckPredicate, + 30, + 94, + 43, + 0, // Skip to: 17205 + /* 6103 */ MCD_OPC_Decode, + 179, + 14, + 244, + 1, // Opcode: LDI_W + /* 6108 */ MCD_OPC_FilterValue, + 27, + 84, + 43, + 0, // Skip to: 17205 + /* 6113 */ MCD_OPC_CheckPredicate, + 30, + 79, + 43, + 0, // Skip to: 17205 + /* 6118 */ MCD_OPC_Decode, + 177, + 14, + 245, + 1, // Opcode: LDI_D + /* 6123 */ MCD_OPC_FilterValue, + 9, + 155, + 2, + 0, // Skip to: 6795 + /* 6128 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 6131 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6146 + /* 6136 */ MCD_OPC_CheckPredicate, + 30, + 56, + 43, + 0, // Skip to: 17205 + /* 6141 */ MCD_OPC_Decode, + 246, + 19, + 246, + 1, // Opcode: SLLI_D + /* 6146 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 6214 + /* 6151 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6154 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6169 + /* 6159 */ MCD_OPC_CheckPredicate, + 30, + 33, + 43, + 0, // Skip to: 17205 + /* 6164 */ MCD_OPC_Decode, + 248, + 19, + 240, + 1, // Opcode: SLLI_W + /* 6169 */ MCD_OPC_FilterValue, + 1, + 23, + 43, + 0, // Skip to: 17205 + /* 6174 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6177 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6192 + /* 6182 */ MCD_OPC_CheckPredicate, + 30, + 10, + 43, + 0, // Skip to: 17205 + /* 6187 */ MCD_OPC_Decode, + 247, + 19, + 247, + 1, // Opcode: SLLI_H + /* 6192 */ MCD_OPC_FilterValue, + 1, + 0, + 43, + 0, // Skip to: 17205 + /* 6197 */ MCD_OPC_CheckPredicate, + 30, + 251, + 42, + 0, // Skip to: 17205 + /* 6202 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 244, + 42, + 0, // Skip to: 17205 + /* 6209 */ MCD_OPC_Decode, + 245, + 19, + 248, + 1, // Opcode: SLLI_B + /* 6214 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6229 + /* 6219 */ MCD_OPC_CheckPredicate, + 30, + 229, + 42, + 0, // Skip to: 17205 + /* 6224 */ MCD_OPC_Decode, + 153, + 20, + 246, + 1, // Opcode: SRAI_D + /* 6229 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 6297 + /* 6234 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6237 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6252 + /* 6242 */ MCD_OPC_CheckPredicate, + 30, + 206, + 42, + 0, // Skip to: 17205 + /* 6247 */ MCD_OPC_Decode, + 155, + 20, + 240, + 1, // Opcode: SRAI_W + /* 6252 */ MCD_OPC_FilterValue, + 1, + 196, + 42, + 0, // Skip to: 17205 + /* 6257 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6260 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6275 + /* 6265 */ MCD_OPC_CheckPredicate, + 30, + 183, + 42, + 0, // Skip to: 17205 + /* 6270 */ MCD_OPC_Decode, + 154, + 20, + 247, + 1, // Opcode: SRAI_H + /* 6275 */ MCD_OPC_FilterValue, + 1, + 173, + 42, + 0, // Skip to: 17205 + /* 6280 */ MCD_OPC_CheckPredicate, + 30, + 168, + 42, + 0, // Skip to: 17205 + /* 6285 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 161, + 42, + 0, // Skip to: 17205 + /* 6292 */ MCD_OPC_Decode, + 152, + 20, + 248, + 1, // Opcode: SRAI_B + /* 6297 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 6312 + /* 6302 */ MCD_OPC_CheckPredicate, + 30, + 146, + 42, + 0, // Skip to: 17205 + /* 6307 */ MCD_OPC_Decode, + 175, + 20, + 246, + 1, // Opcode: SRLI_D + /* 6312 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 6380 + /* 6317 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6320 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6335 + /* 6325 */ MCD_OPC_CheckPredicate, + 30, + 123, + 42, + 0, // Skip to: 17205 + /* 6330 */ MCD_OPC_Decode, + 177, + 20, + 240, + 1, // Opcode: SRLI_W + /* 6335 */ MCD_OPC_FilterValue, + 1, + 113, + 42, + 0, // Skip to: 17205 + /* 6340 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6343 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6358 + /* 6348 */ MCD_OPC_CheckPredicate, + 30, + 100, + 42, + 0, // Skip to: 17205 + /* 6353 */ MCD_OPC_Decode, + 176, + 20, + 247, + 1, // Opcode: SRLI_H + /* 6358 */ MCD_OPC_FilterValue, + 1, + 90, + 42, + 0, // Skip to: 17205 + /* 6363 */ MCD_OPC_CheckPredicate, + 30, + 85, + 42, + 0, // Skip to: 17205 + /* 6368 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 78, + 42, + 0, // Skip to: 17205 + /* 6375 */ MCD_OPC_Decode, + 174, + 20, + 248, + 1, // Opcode: SRLI_B + /* 6380 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 6395 + /* 6385 */ MCD_OPC_CheckPredicate, + 30, + 63, + 42, + 0, // Skip to: 17205 + /* 6390 */ MCD_OPC_Decode, + 236, + 6, + 246, + 1, // Opcode: BCLRI_D + /* 6395 */ MCD_OPC_FilterValue, + 7, + 63, + 0, + 0, // Skip to: 6463 + /* 6400 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6403 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6418 + /* 6408 */ MCD_OPC_CheckPredicate, + 30, + 40, + 42, + 0, // Skip to: 17205 + /* 6413 */ MCD_OPC_Decode, + 238, + 6, + 240, + 1, // Opcode: BCLRI_W + /* 6418 */ MCD_OPC_FilterValue, + 1, + 30, + 42, + 0, // Skip to: 17205 + /* 6423 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6426 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6441 + /* 6431 */ MCD_OPC_CheckPredicate, + 30, + 17, + 42, + 0, // Skip to: 17205 + /* 6436 */ MCD_OPC_Decode, + 237, + 6, + 247, + 1, // Opcode: BCLRI_H + /* 6441 */ MCD_OPC_FilterValue, + 1, + 7, + 42, + 0, // Skip to: 17205 + /* 6446 */ MCD_OPC_CheckPredicate, + 30, + 2, + 42, + 0, // Skip to: 17205 + /* 6451 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 251, + 41, + 0, // Skip to: 17205 + /* 6458 */ MCD_OPC_Decode, + 235, + 6, + 248, + 1, // Opcode: BCLRI_B + /* 6463 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 6478 + /* 6468 */ MCD_OPC_CheckPredicate, + 30, + 236, + 41, + 0, // Skip to: 17205 + /* 6473 */ MCD_OPC_Decode, + 254, + 7, + 246, + 1, // Opcode: BSETI_D + /* 6478 */ MCD_OPC_FilterValue, + 9, + 63, + 0, + 0, // Skip to: 6546 + /* 6483 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6486 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6501 + /* 6491 */ MCD_OPC_CheckPredicate, + 30, + 213, + 41, + 0, // Skip to: 17205 + /* 6496 */ MCD_OPC_Decode, + 128, + 8, + 240, + 1, // Opcode: BSETI_W + /* 6501 */ MCD_OPC_FilterValue, + 1, + 203, + 41, + 0, // Skip to: 17205 + /* 6506 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6509 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6524 + /* 6514 */ MCD_OPC_CheckPredicate, + 30, + 190, + 41, + 0, // Skip to: 17205 + /* 6519 */ MCD_OPC_Decode, + 255, + 7, + 247, + 1, // Opcode: BSETI_H + /* 6524 */ MCD_OPC_FilterValue, + 1, + 180, + 41, + 0, // Skip to: 17205 + /* 6529 */ MCD_OPC_CheckPredicate, + 30, + 175, + 41, + 0, // Skip to: 17205 + /* 6534 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 168, + 41, + 0, // Skip to: 17205 + /* 6541 */ MCD_OPC_Decode, + 253, + 7, + 248, + 1, // Opcode: BSETI_B + /* 6546 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 6561 + /* 6551 */ MCD_OPC_CheckPredicate, + 30, + 153, + 41, + 0, // Skip to: 17205 + /* 6556 */ MCD_OPC_Decode, + 217, + 7, + 246, + 1, // Opcode: BNEGI_D + /* 6561 */ MCD_OPC_FilterValue, + 11, + 63, + 0, + 0, // Skip to: 6629 + /* 6566 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6569 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6584 + /* 6574 */ MCD_OPC_CheckPredicate, + 30, + 130, + 41, + 0, // Skip to: 17205 + /* 6579 */ MCD_OPC_Decode, + 219, + 7, + 240, + 1, // Opcode: BNEGI_W + /* 6584 */ MCD_OPC_FilterValue, + 1, + 120, + 41, + 0, // Skip to: 17205 + /* 6589 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6592 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6607 + /* 6597 */ MCD_OPC_CheckPredicate, + 30, + 107, + 41, + 0, // Skip to: 17205 + /* 6602 */ MCD_OPC_Decode, + 218, + 7, + 247, + 1, // Opcode: BNEGI_H + /* 6607 */ MCD_OPC_FilterValue, + 1, + 97, + 41, + 0, // Skip to: 17205 + /* 6612 */ MCD_OPC_CheckPredicate, + 30, + 92, + 41, + 0, // Skip to: 17205 + /* 6617 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 85, + 41, + 0, // Skip to: 17205 + /* 6624 */ MCD_OPC_Decode, + 216, + 7, + 248, + 1, // Opcode: BNEGI_B + /* 6629 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 6644 + /* 6634 */ MCD_OPC_CheckPredicate, + 30, + 70, + 41, + 0, // Skip to: 17205 + /* 6639 */ MCD_OPC_Decode, + 160, + 7, + 249, + 1, // Opcode: BINSLI_D + /* 6644 */ MCD_OPC_FilterValue, + 13, + 63, + 0, + 0, // Skip to: 6712 + /* 6649 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6652 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6667 + /* 6657 */ MCD_OPC_CheckPredicate, + 30, + 47, + 41, + 0, // Skip to: 17205 + /* 6662 */ MCD_OPC_Decode, + 162, + 7, + 250, + 1, // Opcode: BINSLI_W + /* 6667 */ MCD_OPC_FilterValue, + 1, + 37, + 41, + 0, // Skip to: 17205 + /* 6672 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6675 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6690 + /* 6680 */ MCD_OPC_CheckPredicate, + 30, + 24, + 41, + 0, // Skip to: 17205 + /* 6685 */ MCD_OPC_Decode, + 161, + 7, + 251, + 1, // Opcode: BINSLI_H + /* 6690 */ MCD_OPC_FilterValue, + 1, + 14, + 41, + 0, // Skip to: 17205 + /* 6695 */ MCD_OPC_CheckPredicate, + 30, + 9, + 41, + 0, // Skip to: 17205 + /* 6700 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 2, + 41, + 0, // Skip to: 17205 + /* 6707 */ MCD_OPC_Decode, + 159, + 7, + 252, + 1, // Opcode: BINSLI_B + /* 6712 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 6727 + /* 6717 */ MCD_OPC_CheckPredicate, + 30, + 243, + 40, + 0, // Skip to: 17205 + /* 6722 */ MCD_OPC_Decode, + 168, + 7, + 249, + 1, // Opcode: BINSRI_D + /* 6727 */ MCD_OPC_FilterValue, + 15, + 233, + 40, + 0, // Skip to: 17205 + /* 6732 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6735 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6750 + /* 6740 */ MCD_OPC_CheckPredicate, + 30, + 220, + 40, + 0, // Skip to: 17205 + /* 6745 */ MCD_OPC_Decode, + 170, + 7, + 250, + 1, // Opcode: BINSRI_W + /* 6750 */ MCD_OPC_FilterValue, + 1, + 210, + 40, + 0, // Skip to: 17205 + /* 6755 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6758 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6773 + /* 6763 */ MCD_OPC_CheckPredicate, + 30, + 197, + 40, + 0, // Skip to: 17205 + /* 6768 */ MCD_OPC_Decode, + 169, + 7, + 251, + 1, // Opcode: BINSRI_H + /* 6773 */ MCD_OPC_FilterValue, + 1, + 187, + 40, + 0, // Skip to: 17205 + /* 6778 */ MCD_OPC_CheckPredicate, + 30, + 182, + 40, + 0, // Skip to: 17205 + /* 6783 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 175, + 40, + 0, // Skip to: 17205 + /* 6790 */ MCD_OPC_Decode, + 167, + 7, + 252, + 1, // Opcode: BINSRI_B + /* 6795 */ MCD_OPC_FilterValue, + 10, + 79, + 1, + 0, // Skip to: 7135 + /* 6800 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 6803 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6818 + /* 6808 */ MCD_OPC_CheckPredicate, + 30, + 152, + 40, + 0, // Skip to: 17205 + /* 6813 */ MCD_OPC_Decode, + 227, + 18, + 246, + 1, // Opcode: SAT_S_D + /* 6818 */ MCD_OPC_FilterValue, + 1, + 63, + 0, + 0, // Skip to: 6886 + /* 6823 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6826 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6841 + /* 6831 */ MCD_OPC_CheckPredicate, + 30, + 129, + 40, + 0, // Skip to: 17205 + /* 6836 */ MCD_OPC_Decode, + 229, + 18, + 240, + 1, // Opcode: SAT_S_W + /* 6841 */ MCD_OPC_FilterValue, + 1, + 119, + 40, + 0, // Skip to: 17205 + /* 6846 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6849 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6864 + /* 6854 */ MCD_OPC_CheckPredicate, + 30, + 106, + 40, + 0, // Skip to: 17205 + /* 6859 */ MCD_OPC_Decode, + 228, + 18, + 247, + 1, // Opcode: SAT_S_H + /* 6864 */ MCD_OPC_FilterValue, + 1, + 96, + 40, + 0, // Skip to: 17205 + /* 6869 */ MCD_OPC_CheckPredicate, + 30, + 91, + 40, + 0, // Skip to: 17205 + /* 6874 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 84, + 40, + 0, // Skip to: 17205 + /* 6881 */ MCD_OPC_Decode, + 226, + 18, + 248, + 1, // Opcode: SAT_S_B + /* 6886 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6901 + /* 6891 */ MCD_OPC_CheckPredicate, + 30, + 69, + 40, + 0, // Skip to: 17205 + /* 6896 */ MCD_OPC_Decode, + 231, + 18, + 246, + 1, // Opcode: SAT_U_D + /* 6901 */ MCD_OPC_FilterValue, + 3, + 63, + 0, + 0, // Skip to: 6969 + /* 6906 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6909 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6924 + /* 6914 */ MCD_OPC_CheckPredicate, + 30, + 46, + 40, + 0, // Skip to: 17205 + /* 6919 */ MCD_OPC_Decode, + 233, + 18, + 240, + 1, // Opcode: SAT_U_W + /* 6924 */ MCD_OPC_FilterValue, + 1, + 36, + 40, + 0, // Skip to: 17205 + /* 6929 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 6932 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6947 + /* 6937 */ MCD_OPC_CheckPredicate, + 30, + 23, + 40, + 0, // Skip to: 17205 + /* 6942 */ MCD_OPC_Decode, + 232, + 18, + 247, + 1, // Opcode: SAT_U_H + /* 6947 */ MCD_OPC_FilterValue, + 1, + 13, + 40, + 0, // Skip to: 17205 + /* 6952 */ MCD_OPC_CheckPredicate, + 30, + 8, + 40, + 0, // Skip to: 17205 + /* 6957 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 1, + 40, + 0, // Skip to: 17205 + /* 6964 */ MCD_OPC_Decode, + 230, + 18, + 248, + 1, // Opcode: SAT_U_B + /* 6969 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 6984 + /* 6974 */ MCD_OPC_CheckPredicate, + 30, + 242, + 39, + 0, // Skip to: 17205 + /* 6979 */ MCD_OPC_Decode, + 157, + 20, + 246, + 1, // Opcode: SRARI_D + /* 6984 */ MCD_OPC_FilterValue, + 5, + 63, + 0, + 0, // Skip to: 7052 + /* 6989 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 6992 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7007 + /* 6997 */ MCD_OPC_CheckPredicate, + 30, + 219, + 39, + 0, // Skip to: 17205 + /* 7002 */ MCD_OPC_Decode, + 159, + 20, + 240, + 1, // Opcode: SRARI_W + /* 7007 */ MCD_OPC_FilterValue, + 1, + 209, + 39, + 0, // Skip to: 17205 + /* 7012 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7015 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7030 + /* 7020 */ MCD_OPC_CheckPredicate, + 30, + 196, + 39, + 0, // Skip to: 17205 + /* 7025 */ MCD_OPC_Decode, + 158, + 20, + 247, + 1, // Opcode: SRARI_H + /* 7030 */ MCD_OPC_FilterValue, + 1, + 186, + 39, + 0, // Skip to: 17205 + /* 7035 */ MCD_OPC_CheckPredicate, + 30, + 181, + 39, + 0, // Skip to: 17205 + /* 7040 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 174, + 39, + 0, // Skip to: 17205 + /* 7047 */ MCD_OPC_Decode, + 156, + 20, + 248, + 1, // Opcode: SRARI_B + /* 7052 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 7067 + /* 7057 */ MCD_OPC_CheckPredicate, + 30, + 159, + 39, + 0, // Skip to: 17205 + /* 7062 */ MCD_OPC_Decode, + 179, + 20, + 246, + 1, // Opcode: SRLRI_D + /* 7067 */ MCD_OPC_FilterValue, + 7, + 149, + 39, + 0, // Skip to: 17205 + /* 7072 */ MCD_OPC_ExtractField, + 21, + 1, // Inst{21} ... + /* 7075 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7090 + /* 7080 */ MCD_OPC_CheckPredicate, + 30, + 136, + 39, + 0, // Skip to: 17205 + /* 7085 */ MCD_OPC_Decode, + 181, + 20, + 240, + 1, // Opcode: SRLRI_W + /* 7090 */ MCD_OPC_FilterValue, + 1, + 126, + 39, + 0, // Skip to: 17205 + /* 7095 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 7098 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7113 + /* 7103 */ MCD_OPC_CheckPredicate, + 30, + 113, + 39, + 0, // Skip to: 17205 + /* 7108 */ MCD_OPC_Decode, + 180, + 20, + 247, + 1, // Opcode: SRLRI_H + /* 7113 */ MCD_OPC_FilterValue, + 1, + 103, + 39, + 0, // Skip to: 17205 + /* 7118 */ MCD_OPC_CheckPredicate, + 30, + 98, + 39, + 0, // Skip to: 17205 + /* 7123 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 91, + 39, + 0, // Skip to: 17205 + /* 7130 */ MCD_OPC_Decode, + 178, + 20, + 248, + 1, // Opcode: SRLRI_B + /* 7135 */ MCD_OPC_FilterValue, + 13, + 227, + 1, + 0, // Skip to: 7623 + /* 7140 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 7143 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7158 + /* 7148 */ MCD_OPC_CheckPredicate, + 30, + 68, + 39, + 0, // Skip to: 17205 + /* 7153 */ MCD_OPC_Decode, + 251, + 19, + 253, + 1, // Opcode: SLL_B + /* 7158 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7173 + /* 7163 */ MCD_OPC_CheckPredicate, + 30, + 53, + 39, + 0, // Skip to: 17205 + /* 7168 */ MCD_OPC_Decode, + 253, + 19, + 254, + 1, // Opcode: SLL_H + /* 7173 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7188 + /* 7178 */ MCD_OPC_CheckPredicate, + 30, + 38, + 39, + 0, // Skip to: 17205 + /* 7183 */ MCD_OPC_Decode, + 128, + 20, + 255, + 1, // Opcode: SLL_W + /* 7188 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 7203 + /* 7193 */ MCD_OPC_CheckPredicate, + 30, + 23, + 39, + 0, // Skip to: 17205 + /* 7198 */ MCD_OPC_Decode, + 252, + 19, + 128, + 2, // Opcode: SLL_D + /* 7203 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 7218 + /* 7208 */ MCD_OPC_CheckPredicate, + 30, + 8, + 39, + 0, // Skip to: 17205 + /* 7213 */ MCD_OPC_Decode, + 166, + 20, + 253, + 1, // Opcode: SRA_B + /* 7218 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 7233 + /* 7223 */ MCD_OPC_CheckPredicate, + 30, + 249, + 38, + 0, // Skip to: 17205 + /* 7228 */ MCD_OPC_Decode, + 168, + 20, + 254, + 1, // Opcode: SRA_H + /* 7233 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 7248 + /* 7238 */ MCD_OPC_CheckPredicate, + 30, + 234, + 38, + 0, // Skip to: 17205 + /* 7243 */ MCD_OPC_Decode, + 170, + 20, + 255, + 1, // Opcode: SRA_W + /* 7248 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 7263 + /* 7253 */ MCD_OPC_CheckPredicate, + 30, + 219, + 38, + 0, // Skip to: 17205 + /* 7258 */ MCD_OPC_Decode, + 167, + 20, + 128, + 2, // Opcode: SRA_D + /* 7263 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 7278 + /* 7268 */ MCD_OPC_CheckPredicate, + 30, + 204, + 38, + 0, // Skip to: 17205 + /* 7273 */ MCD_OPC_Decode, + 188, + 20, + 253, + 1, // Opcode: SRL_B + /* 7278 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 7293 + /* 7283 */ MCD_OPC_CheckPredicate, + 30, + 189, + 38, + 0, // Skip to: 17205 + /* 7288 */ MCD_OPC_Decode, + 190, + 20, + 254, + 1, // Opcode: SRL_H + /* 7293 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 7308 + /* 7298 */ MCD_OPC_CheckPredicate, + 30, + 174, + 38, + 0, // Skip to: 17205 + /* 7303 */ MCD_OPC_Decode, + 192, + 20, + 255, + 1, // Opcode: SRL_W + /* 7308 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 7323 + /* 7313 */ MCD_OPC_CheckPredicate, + 30, + 159, + 38, + 0, // Skip to: 17205 + /* 7318 */ MCD_OPC_Decode, + 189, + 20, + 128, + 2, // Opcode: SRL_D + /* 7323 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 7338 + /* 7328 */ MCD_OPC_CheckPredicate, + 30, + 144, + 38, + 0, // Skip to: 17205 + /* 7333 */ MCD_OPC_Decode, + 239, + 6, + 253, + 1, // Opcode: BCLR_B + /* 7338 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 7353 + /* 7343 */ MCD_OPC_CheckPredicate, + 30, + 129, + 38, + 0, // Skip to: 17205 + /* 7348 */ MCD_OPC_Decode, + 241, + 6, + 254, + 1, // Opcode: BCLR_H + /* 7353 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7368 + /* 7358 */ MCD_OPC_CheckPredicate, + 30, + 114, + 38, + 0, // Skip to: 17205 + /* 7363 */ MCD_OPC_Decode, + 242, + 6, + 255, + 1, // Opcode: BCLR_W + /* 7368 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 7383 + /* 7373 */ MCD_OPC_CheckPredicate, + 30, + 99, + 38, + 0, // Skip to: 17205 + /* 7378 */ MCD_OPC_Decode, + 240, + 6, + 128, + 2, // Opcode: BCLR_D + /* 7383 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 7398 + /* 7388 */ MCD_OPC_CheckPredicate, + 30, + 84, + 38, + 0, // Skip to: 17205 + /* 7393 */ MCD_OPC_Decode, + 129, + 8, + 253, + 1, // Opcode: BSET_B + /* 7398 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 7413 + /* 7403 */ MCD_OPC_CheckPredicate, + 30, + 69, + 38, + 0, // Skip to: 17205 + /* 7408 */ MCD_OPC_Decode, + 131, + 8, + 254, + 1, // Opcode: BSET_H + /* 7413 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 7428 + /* 7418 */ MCD_OPC_CheckPredicate, + 30, + 54, + 38, + 0, // Skip to: 17205 + /* 7423 */ MCD_OPC_Decode, + 132, + 8, + 255, + 1, // Opcode: BSET_W + /* 7428 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 7443 + /* 7433 */ MCD_OPC_CheckPredicate, + 30, + 39, + 38, + 0, // Skip to: 17205 + /* 7438 */ MCD_OPC_Decode, + 130, + 8, + 128, + 2, // Opcode: BSET_D + /* 7443 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 7458 + /* 7448 */ MCD_OPC_CheckPredicate, + 30, + 24, + 38, + 0, // Skip to: 17205 + /* 7453 */ MCD_OPC_Decode, + 220, + 7, + 253, + 1, // Opcode: BNEG_B + /* 7458 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 7473 + /* 7463 */ MCD_OPC_CheckPredicate, + 30, + 9, + 38, + 0, // Skip to: 17205 + /* 7468 */ MCD_OPC_Decode, + 222, + 7, + 254, + 1, // Opcode: BNEG_H + /* 7473 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 7488 + /* 7478 */ MCD_OPC_CheckPredicate, + 30, + 250, + 37, + 0, // Skip to: 17205 + /* 7483 */ MCD_OPC_Decode, + 223, + 7, + 255, + 1, // Opcode: BNEG_W + /* 7488 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 7503 + /* 7493 */ MCD_OPC_CheckPredicate, + 30, + 235, + 37, + 0, // Skip to: 17205 + /* 7498 */ MCD_OPC_Decode, + 221, + 7, + 128, + 2, // Opcode: BNEG_D + /* 7503 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 7518 + /* 7508 */ MCD_OPC_CheckPredicate, + 30, + 220, + 37, + 0, // Skip to: 17205 + /* 7513 */ MCD_OPC_Decode, + 163, + 7, + 129, + 2, // Opcode: BINSL_B + /* 7518 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 7533 + /* 7523 */ MCD_OPC_CheckPredicate, + 30, + 205, + 37, + 0, // Skip to: 17205 + /* 7528 */ MCD_OPC_Decode, + 165, + 7, + 130, + 2, // Opcode: BINSL_H + /* 7533 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 7548 + /* 7538 */ MCD_OPC_CheckPredicate, + 30, + 190, + 37, + 0, // Skip to: 17205 + /* 7543 */ MCD_OPC_Decode, + 166, + 7, + 131, + 2, // Opcode: BINSL_W + /* 7548 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 7563 + /* 7553 */ MCD_OPC_CheckPredicate, + 30, + 175, + 37, + 0, // Skip to: 17205 + /* 7558 */ MCD_OPC_Decode, + 164, + 7, + 132, + 2, // Opcode: BINSL_D + /* 7563 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 7578 + /* 7568 */ MCD_OPC_CheckPredicate, + 30, + 160, + 37, + 0, // Skip to: 17205 + /* 7573 */ MCD_OPC_Decode, + 171, + 7, + 129, + 2, // Opcode: BINSR_B + /* 7578 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 7593 + /* 7583 */ MCD_OPC_CheckPredicate, + 30, + 145, + 37, + 0, // Skip to: 17205 + /* 7588 */ MCD_OPC_Decode, + 173, + 7, + 130, + 2, // Opcode: BINSR_H + /* 7593 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 7608 + /* 7598 */ MCD_OPC_CheckPredicate, + 30, + 130, + 37, + 0, // Skip to: 17205 + /* 7603 */ MCD_OPC_Decode, + 174, + 7, + 131, + 2, // Opcode: BINSR_W + /* 7608 */ MCD_OPC_FilterValue, + 31, + 120, + 37, + 0, // Skip to: 17205 + /* 7613 */ MCD_OPC_CheckPredicate, + 30, + 115, + 37, + 0, // Skip to: 17205 + /* 7618 */ MCD_OPC_Decode, + 172, + 7, + 132, + 2, // Opcode: BINSR_D + /* 7623 */ MCD_OPC_FilterValue, + 14, + 227, + 1, + 0, // Skip to: 8111 + /* 7628 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 7631 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7646 + /* 7636 */ MCD_OPC_CheckPredicate, + 30, + 92, + 37, + 0, // Skip to: 17205 + /* 7641 */ MCD_OPC_Decode, + 251, + 5, + 253, + 1, // Opcode: ADDV_B + /* 7646 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7661 + /* 7651 */ MCD_OPC_CheckPredicate, + 30, + 77, + 37, + 0, // Skip to: 17205 + /* 7656 */ MCD_OPC_Decode, + 253, + 5, + 254, + 1, // Opcode: ADDV_H + /* 7661 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7676 + /* 7666 */ MCD_OPC_CheckPredicate, + 30, + 62, + 37, + 0, // Skip to: 17205 + /* 7671 */ MCD_OPC_Decode, + 254, + 5, + 255, + 1, // Opcode: ADDV_W + /* 7676 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 7691 + /* 7681 */ MCD_OPC_CheckPredicate, + 30, + 47, + 37, + 0, // Skip to: 17205 + /* 7686 */ MCD_OPC_Decode, + 252, + 5, + 128, + 2, // Opcode: ADDV_D + /* 7691 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 7706 + /* 7696 */ MCD_OPC_CheckPredicate, + 30, + 32, + 37, + 0, // Skip to: 17205 + /* 7701 */ MCD_OPC_Decode, + 250, + 20, + 253, + 1, // Opcode: SUBV_B + /* 7706 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 7721 + /* 7711 */ MCD_OPC_CheckPredicate, + 30, + 17, + 37, + 0, // Skip to: 17205 + /* 7716 */ MCD_OPC_Decode, + 252, + 20, + 254, + 1, // Opcode: SUBV_H + /* 7721 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 7736 + /* 7726 */ MCD_OPC_CheckPredicate, + 30, + 2, + 37, + 0, // Skip to: 17205 + /* 7731 */ MCD_OPC_Decode, + 253, + 20, + 255, + 1, // Opcode: SUBV_W + /* 7736 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 7751 + /* 7741 */ MCD_OPC_CheckPredicate, + 30, + 243, + 36, + 0, // Skip to: 17205 + /* 7746 */ MCD_OPC_Decode, + 251, + 20, + 128, + 2, // Opcode: SUBV_D + /* 7751 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 7766 + /* 7756 */ MCD_OPC_CheckPredicate, + 30, + 228, + 36, + 0, // Skip to: 17205 + /* 7761 */ MCD_OPC_Decode, + 203, + 15, + 253, + 1, // Opcode: MAX_S_B + /* 7766 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 7781 + /* 7771 */ MCD_OPC_CheckPredicate, + 30, + 213, + 36, + 0, // Skip to: 17205 + /* 7776 */ MCD_OPC_Decode, + 205, + 15, + 254, + 1, // Opcode: MAX_S_H + /* 7781 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 7796 + /* 7786 */ MCD_OPC_CheckPredicate, + 30, + 198, + 36, + 0, // Skip to: 17205 + /* 7791 */ MCD_OPC_Decode, + 207, + 15, + 255, + 1, // Opcode: MAX_S_W + /* 7796 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 7811 + /* 7801 */ MCD_OPC_CheckPredicate, + 30, + 183, + 36, + 0, // Skip to: 17205 + /* 7806 */ MCD_OPC_Decode, + 204, + 15, + 128, + 2, // Opcode: MAX_S_D + /* 7811 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 7826 + /* 7816 */ MCD_OPC_CheckPredicate, + 30, + 168, + 36, + 0, // Skip to: 17205 + /* 7821 */ MCD_OPC_Decode, + 208, + 15, + 253, + 1, // Opcode: MAX_U_B + /* 7826 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 7841 + /* 7831 */ MCD_OPC_CheckPredicate, + 30, + 153, + 36, + 0, // Skip to: 17205 + /* 7836 */ MCD_OPC_Decode, + 210, + 15, + 254, + 1, // Opcode: MAX_U_H + /* 7841 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 7856 + /* 7846 */ MCD_OPC_CheckPredicate, + 30, + 138, + 36, + 0, // Skip to: 17205 + /* 7851 */ MCD_OPC_Decode, + 211, + 15, + 255, + 1, // Opcode: MAX_U_W + /* 7856 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 7871 + /* 7861 */ MCD_OPC_CheckPredicate, + 30, + 123, + 36, + 0, // Skip to: 17205 + /* 7866 */ MCD_OPC_Decode, + 209, + 15, + 128, + 2, // Opcode: MAX_U_D + /* 7871 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 7886 + /* 7876 */ MCD_OPC_CheckPredicate, + 30, + 108, + 36, + 0, // Skip to: 17205 + /* 7881 */ MCD_OPC_Decode, + 134, + 16, + 253, + 1, // Opcode: MIN_S_B + /* 7886 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 7901 + /* 7891 */ MCD_OPC_CheckPredicate, + 30, + 93, + 36, + 0, // Skip to: 17205 + /* 7896 */ MCD_OPC_Decode, + 136, + 16, + 254, + 1, // Opcode: MIN_S_H + /* 7901 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 7916 + /* 7906 */ MCD_OPC_CheckPredicate, + 30, + 78, + 36, + 0, // Skip to: 17205 + /* 7911 */ MCD_OPC_Decode, + 138, + 16, + 255, + 1, // Opcode: MIN_S_W + /* 7916 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 7931 + /* 7921 */ MCD_OPC_CheckPredicate, + 30, + 63, + 36, + 0, // Skip to: 17205 + /* 7926 */ MCD_OPC_Decode, + 135, + 16, + 128, + 2, // Opcode: MIN_S_D + /* 7931 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 7946 + /* 7936 */ MCD_OPC_CheckPredicate, + 30, + 48, + 36, + 0, // Skip to: 17205 + /* 7941 */ MCD_OPC_Decode, + 139, + 16, + 253, + 1, // Opcode: MIN_U_B + /* 7946 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 7961 + /* 7951 */ MCD_OPC_CheckPredicate, + 30, + 33, + 36, + 0, // Skip to: 17205 + /* 7956 */ MCD_OPC_Decode, + 141, + 16, + 254, + 1, // Opcode: MIN_U_H + /* 7961 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 7976 + /* 7966 */ MCD_OPC_CheckPredicate, + 30, + 18, + 36, + 0, // Skip to: 17205 + /* 7971 */ MCD_OPC_Decode, + 142, + 16, + 255, + 1, // Opcode: MIN_U_W + /* 7976 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 7991 + /* 7981 */ MCD_OPC_CheckPredicate, + 30, + 3, + 36, + 0, // Skip to: 17205 + /* 7986 */ MCD_OPC_Decode, + 140, + 16, + 128, + 2, // Opcode: MIN_U_D + /* 7991 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 8006 + /* 7996 */ MCD_OPC_CheckPredicate, + 30, + 244, + 35, + 0, // Skip to: 17205 + /* 8001 */ MCD_OPC_Decode, + 196, + 15, + 253, + 1, // Opcode: MAX_A_B + /* 8006 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 8021 + /* 8011 */ MCD_OPC_CheckPredicate, + 30, + 229, + 35, + 0, // Skip to: 17205 + /* 8016 */ MCD_OPC_Decode, + 198, + 15, + 254, + 1, // Opcode: MAX_A_H + /* 8021 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 8036 + /* 8026 */ MCD_OPC_CheckPredicate, + 30, + 214, + 35, + 0, // Skip to: 17205 + /* 8031 */ MCD_OPC_Decode, + 199, + 15, + 255, + 1, // Opcode: MAX_A_W + /* 8036 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 8051 + /* 8041 */ MCD_OPC_CheckPredicate, + 30, + 199, + 35, + 0, // Skip to: 17205 + /* 8046 */ MCD_OPC_Decode, + 197, + 15, + 128, + 2, // Opcode: MAX_A_D + /* 8051 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 8066 + /* 8056 */ MCD_OPC_CheckPredicate, + 30, + 184, + 35, + 0, // Skip to: 17205 + /* 8061 */ MCD_OPC_Decode, + 255, + 15, + 253, + 1, // Opcode: MIN_A_B + /* 8066 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 8081 + /* 8071 */ MCD_OPC_CheckPredicate, + 30, + 169, + 35, + 0, // Skip to: 17205 + /* 8076 */ MCD_OPC_Decode, + 129, + 16, + 254, + 1, // Opcode: MIN_A_H + /* 8081 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 8096 + /* 8086 */ MCD_OPC_CheckPredicate, + 30, + 154, + 35, + 0, // Skip to: 17205 + /* 8091 */ MCD_OPC_Decode, + 130, + 16, + 255, + 1, // Opcode: MIN_A_W + /* 8096 */ MCD_OPC_FilterValue, + 31, + 144, + 35, + 0, // Skip to: 17205 + /* 8101 */ MCD_OPC_CheckPredicate, + 30, + 139, + 35, + 0, // Skip to: 17205 + /* 8106 */ MCD_OPC_Decode, + 128, + 16, + 128, + 2, // Opcode: MIN_A_D + /* 8111 */ MCD_OPC_FilterValue, + 15, + 47, + 1, + 0, // Skip to: 8419 + /* 8116 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 8119 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8134 + /* 8124 */ MCD_OPC_CheckPredicate, + 30, + 116, + 35, + 0, // Skip to: 17205 + /* 8129 */ MCD_OPC_Decode, + 170, + 8, + 253, + 1, // Opcode: CEQ_B + /* 8134 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8149 + /* 8139 */ MCD_OPC_CheckPredicate, + 30, + 101, + 35, + 0, // Skip to: 17205 + /* 8144 */ MCD_OPC_Decode, + 172, + 8, + 254, + 1, // Opcode: CEQ_H + /* 8149 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8164 + /* 8154 */ MCD_OPC_CheckPredicate, + 30, + 86, + 35, + 0, // Skip to: 17205 + /* 8159 */ MCD_OPC_Decode, + 173, + 8, + 255, + 1, // Opcode: CEQ_W + /* 8164 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8179 + /* 8169 */ MCD_OPC_CheckPredicate, + 30, + 71, + 35, + 0, // Skip to: 17205 + /* 8174 */ MCD_OPC_Decode, + 171, + 8, + 128, + 2, // Opcode: CEQ_D + /* 8179 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 8194 + /* 8184 */ MCD_OPC_CheckPredicate, + 30, + 56, + 35, + 0, // Skip to: 17205 + /* 8189 */ MCD_OPC_Decode, + 214, + 8, + 253, + 1, // Opcode: CLT_S_B + /* 8194 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 8209 + /* 8199 */ MCD_OPC_CheckPredicate, + 30, + 41, + 35, + 0, // Skip to: 17205 + /* 8204 */ MCD_OPC_Decode, + 216, + 8, + 254, + 1, // Opcode: CLT_S_H + /* 8209 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 8224 + /* 8214 */ MCD_OPC_CheckPredicate, + 30, + 26, + 35, + 0, // Skip to: 17205 + /* 8219 */ MCD_OPC_Decode, + 217, + 8, + 255, + 1, // Opcode: CLT_S_W + /* 8224 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 8239 + /* 8229 */ MCD_OPC_CheckPredicate, + 30, + 11, + 35, + 0, // Skip to: 17205 + /* 8234 */ MCD_OPC_Decode, + 215, + 8, + 128, + 2, // Opcode: CLT_S_D + /* 8239 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 8254 + /* 8244 */ MCD_OPC_CheckPredicate, + 30, + 252, + 34, + 0, // Skip to: 17205 + /* 8249 */ MCD_OPC_Decode, + 218, + 8, + 253, + 1, // Opcode: CLT_U_B + /* 8254 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 8269 + /* 8259 */ MCD_OPC_CheckPredicate, + 30, + 237, + 34, + 0, // Skip to: 17205 + /* 8264 */ MCD_OPC_Decode, + 220, + 8, + 254, + 1, // Opcode: CLT_U_H + /* 8269 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 8284 + /* 8274 */ MCD_OPC_CheckPredicate, + 30, + 222, + 34, + 0, // Skip to: 17205 + /* 8279 */ MCD_OPC_Decode, + 221, + 8, + 255, + 1, // Opcode: CLT_U_W + /* 8284 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 8299 + /* 8289 */ MCD_OPC_CheckPredicate, + 30, + 207, + 34, + 0, // Skip to: 17205 + /* 8294 */ MCD_OPC_Decode, + 219, + 8, + 128, + 2, // Opcode: CLT_U_D + /* 8299 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 8314 + /* 8304 */ MCD_OPC_CheckPredicate, + 30, + 192, + 34, + 0, // Skip to: 17205 + /* 8309 */ MCD_OPC_Decode, + 194, + 8, + 253, + 1, // Opcode: CLE_S_B + /* 8314 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 8329 + /* 8319 */ MCD_OPC_CheckPredicate, + 30, + 177, + 34, + 0, // Skip to: 17205 + /* 8324 */ MCD_OPC_Decode, + 196, + 8, + 254, + 1, // Opcode: CLE_S_H + /* 8329 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 8344 + /* 8334 */ MCD_OPC_CheckPredicate, + 30, + 162, + 34, + 0, // Skip to: 17205 + /* 8339 */ MCD_OPC_Decode, + 197, + 8, + 255, + 1, // Opcode: CLE_S_W + /* 8344 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 8359 + /* 8349 */ MCD_OPC_CheckPredicate, + 30, + 147, + 34, + 0, // Skip to: 17205 + /* 8354 */ MCD_OPC_Decode, + 195, + 8, + 128, + 2, // Opcode: CLE_S_D + /* 8359 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 8374 + /* 8364 */ MCD_OPC_CheckPredicate, + 30, + 132, + 34, + 0, // Skip to: 17205 + /* 8369 */ MCD_OPC_Decode, + 198, + 8, + 253, + 1, // Opcode: CLE_U_B + /* 8374 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 8389 + /* 8379 */ MCD_OPC_CheckPredicate, + 30, + 117, + 34, + 0, // Skip to: 17205 + /* 8384 */ MCD_OPC_Decode, + 200, + 8, + 254, + 1, // Opcode: CLE_U_H + /* 8389 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 8404 + /* 8394 */ MCD_OPC_CheckPredicate, + 30, + 102, + 34, + 0, // Skip to: 17205 + /* 8399 */ MCD_OPC_Decode, + 201, + 8, + 255, + 1, // Opcode: CLE_U_W + /* 8404 */ MCD_OPC_FilterValue, + 23, + 92, + 34, + 0, // Skip to: 17205 + /* 8409 */ MCD_OPC_CheckPredicate, + 30, + 87, + 34, + 0, // Skip to: 17205 + /* 8414 */ MCD_OPC_Decode, + 199, + 8, + 128, + 2, // Opcode: CLE_U_D + /* 8419 */ MCD_OPC_FilterValue, + 16, + 227, + 1, + 0, // Skip to: 8907 + /* 8424 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 8427 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8442 + /* 8432 */ MCD_OPC_CheckPredicate, + 30, + 64, + 34, + 0, // Skip to: 17205 + /* 8437 */ MCD_OPC_Decode, + 129, + 6, + 253, + 1, // Opcode: ADD_A_B + /* 8442 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8457 + /* 8447 */ MCD_OPC_CheckPredicate, + 30, + 49, + 34, + 0, // Skip to: 17205 + /* 8452 */ MCD_OPC_Decode, + 131, + 6, + 254, + 1, // Opcode: ADD_A_H + /* 8457 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8472 + /* 8462 */ MCD_OPC_CheckPredicate, + 30, + 34, + 34, + 0, // Skip to: 17205 + /* 8467 */ MCD_OPC_Decode, + 132, + 6, + 255, + 1, // Opcode: ADD_A_W + /* 8472 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8487 + /* 8477 */ MCD_OPC_CheckPredicate, + 30, + 19, + 34, + 0, // Skip to: 17205 + /* 8482 */ MCD_OPC_Decode, + 130, + 6, + 128, + 2, // Opcode: ADD_A_D + /* 8487 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 8502 + /* 8492 */ MCD_OPC_CheckPredicate, + 30, + 4, + 34, + 0, // Skip to: 17205 + /* 8497 */ MCD_OPC_Decode, + 220, + 5, + 253, + 1, // Opcode: ADDS_A_B + /* 8502 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 8517 + /* 8507 */ MCD_OPC_CheckPredicate, + 30, + 245, + 33, + 0, // Skip to: 17205 + /* 8512 */ MCD_OPC_Decode, + 222, + 5, + 254, + 1, // Opcode: ADDS_A_H + /* 8517 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 8532 + /* 8522 */ MCD_OPC_CheckPredicate, + 30, + 230, + 33, + 0, // Skip to: 17205 + /* 8527 */ MCD_OPC_Decode, + 223, + 5, + 255, + 1, // Opcode: ADDS_A_W + /* 8532 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 8547 + /* 8537 */ MCD_OPC_CheckPredicate, + 30, + 215, + 33, + 0, // Skip to: 17205 + /* 8542 */ MCD_OPC_Decode, + 221, + 5, + 128, + 2, // Opcode: ADDS_A_D + /* 8547 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 8562 + /* 8552 */ MCD_OPC_CheckPredicate, + 30, + 200, + 33, + 0, // Skip to: 17205 + /* 8557 */ MCD_OPC_Decode, + 224, + 5, + 253, + 1, // Opcode: ADDS_S_B + /* 8562 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 8577 + /* 8567 */ MCD_OPC_CheckPredicate, + 30, + 185, + 33, + 0, // Skip to: 17205 + /* 8572 */ MCD_OPC_Decode, + 226, + 5, + 254, + 1, // Opcode: ADDS_S_H + /* 8577 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 8592 + /* 8582 */ MCD_OPC_CheckPredicate, + 30, + 170, + 33, + 0, // Skip to: 17205 + /* 8587 */ MCD_OPC_Decode, + 227, + 5, + 255, + 1, // Opcode: ADDS_S_W + /* 8592 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 8607 + /* 8597 */ MCD_OPC_CheckPredicate, + 30, + 155, + 33, + 0, // Skip to: 17205 + /* 8602 */ MCD_OPC_Decode, + 225, + 5, + 128, + 2, // Opcode: ADDS_S_D + /* 8607 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 8622 + /* 8612 */ MCD_OPC_CheckPredicate, + 30, + 140, + 33, + 0, // Skip to: 17205 + /* 8617 */ MCD_OPC_Decode, + 228, + 5, + 253, + 1, // Opcode: ADDS_U_B + /* 8622 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 8637 + /* 8627 */ MCD_OPC_CheckPredicate, + 30, + 125, + 33, + 0, // Skip to: 17205 + /* 8632 */ MCD_OPC_Decode, + 230, + 5, + 254, + 1, // Opcode: ADDS_U_H + /* 8637 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 8652 + /* 8642 */ MCD_OPC_CheckPredicate, + 30, + 110, + 33, + 0, // Skip to: 17205 + /* 8647 */ MCD_OPC_Decode, + 231, + 5, + 255, + 1, // Opcode: ADDS_U_W + /* 8652 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 8667 + /* 8657 */ MCD_OPC_CheckPredicate, + 30, + 95, + 33, + 0, // Skip to: 17205 + /* 8662 */ MCD_OPC_Decode, + 229, + 5, + 128, + 2, // Opcode: ADDS_U_D + /* 8667 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 8682 + /* 8672 */ MCD_OPC_CheckPredicate, + 30, + 80, + 33, + 0, // Skip to: 17205 + /* 8677 */ MCD_OPC_Decode, + 181, + 6, + 253, + 1, // Opcode: AVE_S_B + /* 8682 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 8697 + /* 8687 */ MCD_OPC_CheckPredicate, + 30, + 65, + 33, + 0, // Skip to: 17205 + /* 8692 */ MCD_OPC_Decode, + 183, + 6, + 254, + 1, // Opcode: AVE_S_H + /* 8697 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 8712 + /* 8702 */ MCD_OPC_CheckPredicate, + 30, + 50, + 33, + 0, // Skip to: 17205 + /* 8707 */ MCD_OPC_Decode, + 184, + 6, + 255, + 1, // Opcode: AVE_S_W + /* 8712 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 8727 + /* 8717 */ MCD_OPC_CheckPredicate, + 30, + 35, + 33, + 0, // Skip to: 17205 + /* 8722 */ MCD_OPC_Decode, + 182, + 6, + 128, + 2, // Opcode: AVE_S_D + /* 8727 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 8742 + /* 8732 */ MCD_OPC_CheckPredicate, + 30, + 20, + 33, + 0, // Skip to: 17205 + /* 8737 */ MCD_OPC_Decode, + 185, + 6, + 253, + 1, // Opcode: AVE_U_B + /* 8742 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 8757 + /* 8747 */ MCD_OPC_CheckPredicate, + 30, + 5, + 33, + 0, // Skip to: 17205 + /* 8752 */ MCD_OPC_Decode, + 187, + 6, + 254, + 1, // Opcode: AVE_U_H + /* 8757 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 8772 + /* 8762 */ MCD_OPC_CheckPredicate, + 30, + 246, + 32, + 0, // Skip to: 17205 + /* 8767 */ MCD_OPC_Decode, + 188, + 6, + 255, + 1, // Opcode: AVE_U_W + /* 8772 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 8787 + /* 8777 */ MCD_OPC_CheckPredicate, + 30, + 231, + 32, + 0, // Skip to: 17205 + /* 8782 */ MCD_OPC_Decode, + 186, + 6, + 128, + 2, // Opcode: AVE_U_D + /* 8787 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 8802 + /* 8792 */ MCD_OPC_CheckPredicate, + 30, + 216, + 32, + 0, // Skip to: 17205 + /* 8797 */ MCD_OPC_Decode, + 173, + 6, + 253, + 1, // Opcode: AVER_S_B + /* 8802 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 8817 + /* 8807 */ MCD_OPC_CheckPredicate, + 30, + 201, + 32, + 0, // Skip to: 17205 + /* 8812 */ MCD_OPC_Decode, + 175, + 6, + 254, + 1, // Opcode: AVER_S_H + /* 8817 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 8832 + /* 8822 */ MCD_OPC_CheckPredicate, + 30, + 186, + 32, + 0, // Skip to: 17205 + /* 8827 */ MCD_OPC_Decode, + 176, + 6, + 255, + 1, // Opcode: AVER_S_W + /* 8832 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 8847 + /* 8837 */ MCD_OPC_CheckPredicate, + 30, + 171, + 32, + 0, // Skip to: 17205 + /* 8842 */ MCD_OPC_Decode, + 174, + 6, + 128, + 2, // Opcode: AVER_S_D + /* 8847 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 8862 + /* 8852 */ MCD_OPC_CheckPredicate, + 30, + 156, + 32, + 0, // Skip to: 17205 + /* 8857 */ MCD_OPC_Decode, + 177, + 6, + 253, + 1, // Opcode: AVER_U_B + /* 8862 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 8877 + /* 8867 */ MCD_OPC_CheckPredicate, + 30, + 141, + 32, + 0, // Skip to: 17205 + /* 8872 */ MCD_OPC_Decode, + 179, + 6, + 254, + 1, // Opcode: AVER_U_H + /* 8877 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 8892 + /* 8882 */ MCD_OPC_CheckPredicate, + 30, + 126, + 32, + 0, // Skip to: 17205 + /* 8887 */ MCD_OPC_Decode, + 180, + 6, + 255, + 1, // Opcode: AVER_U_W + /* 8892 */ MCD_OPC_FilterValue, + 31, + 116, + 32, + 0, // Skip to: 17205 + /* 8897 */ MCD_OPC_CheckPredicate, + 30, + 111, + 32, + 0, // Skip to: 17205 + /* 8902 */ MCD_OPC_Decode, + 178, + 6, + 128, + 2, // Opcode: AVER_U_D + /* 8907 */ MCD_OPC_FilterValue, + 17, + 107, + 1, + 0, // Skip to: 9275 + /* 8912 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 8915 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8930 + /* 8920 */ MCD_OPC_CheckPredicate, + 30, + 88, + 32, + 0, // Skip to: 17205 + /* 8925 */ MCD_OPC_Decode, + 223, + 20, + 253, + 1, // Opcode: SUBS_S_B + /* 8930 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8945 + /* 8935 */ MCD_OPC_CheckPredicate, + 30, + 73, + 32, + 0, // Skip to: 17205 + /* 8940 */ MCD_OPC_Decode, + 225, + 20, + 254, + 1, // Opcode: SUBS_S_H + /* 8945 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8960 + /* 8950 */ MCD_OPC_CheckPredicate, + 30, + 58, + 32, + 0, // Skip to: 17205 + /* 8955 */ MCD_OPC_Decode, + 226, + 20, + 255, + 1, // Opcode: SUBS_S_W + /* 8960 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8975 + /* 8965 */ MCD_OPC_CheckPredicate, + 30, + 43, + 32, + 0, // Skip to: 17205 + /* 8970 */ MCD_OPC_Decode, + 224, + 20, + 128, + 2, // Opcode: SUBS_S_D + /* 8975 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 8990 + /* 8980 */ MCD_OPC_CheckPredicate, + 30, + 28, + 32, + 0, // Skip to: 17205 + /* 8985 */ MCD_OPC_Decode, + 227, + 20, + 253, + 1, // Opcode: SUBS_U_B + /* 8990 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 9005 + /* 8995 */ MCD_OPC_CheckPredicate, + 30, + 13, + 32, + 0, // Skip to: 17205 + /* 9000 */ MCD_OPC_Decode, + 229, + 20, + 254, + 1, // Opcode: SUBS_U_H + /* 9005 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 9020 + /* 9010 */ MCD_OPC_CheckPredicate, + 30, + 254, + 31, + 0, // Skip to: 17205 + /* 9015 */ MCD_OPC_Decode, + 230, + 20, + 255, + 1, // Opcode: SUBS_U_W + /* 9020 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 9035 + /* 9025 */ MCD_OPC_CheckPredicate, + 30, + 239, + 31, + 0, // Skip to: 17205 + /* 9030 */ MCD_OPC_Decode, + 228, + 20, + 128, + 2, // Opcode: SUBS_U_D + /* 9035 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 9050 + /* 9040 */ MCD_OPC_CheckPredicate, + 30, + 224, + 31, + 0, // Skip to: 17205 + /* 9045 */ MCD_OPC_Decode, + 215, + 20, + 253, + 1, // Opcode: SUBSUS_U_B + /* 9050 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 9065 + /* 9055 */ MCD_OPC_CheckPredicate, + 30, + 209, + 31, + 0, // Skip to: 17205 + /* 9060 */ MCD_OPC_Decode, + 217, + 20, + 254, + 1, // Opcode: SUBSUS_U_H + /* 9065 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 9080 + /* 9070 */ MCD_OPC_CheckPredicate, + 30, + 194, + 31, + 0, // Skip to: 17205 + /* 9075 */ MCD_OPC_Decode, + 218, + 20, + 255, + 1, // Opcode: SUBSUS_U_W + /* 9080 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 9095 + /* 9085 */ MCD_OPC_CheckPredicate, + 30, + 179, + 31, + 0, // Skip to: 17205 + /* 9090 */ MCD_OPC_Decode, + 216, + 20, + 128, + 2, // Opcode: SUBSUS_U_D + /* 9095 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 9110 + /* 9100 */ MCD_OPC_CheckPredicate, + 30, + 164, + 31, + 0, // Skip to: 17205 + /* 9105 */ MCD_OPC_Decode, + 219, + 20, + 253, + 1, // Opcode: SUBSUU_S_B + /* 9110 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 9125 + /* 9115 */ MCD_OPC_CheckPredicate, + 30, + 149, + 31, + 0, // Skip to: 17205 + /* 9120 */ MCD_OPC_Decode, + 221, + 20, + 254, + 1, // Opcode: SUBSUU_S_H + /* 9125 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9140 + /* 9130 */ MCD_OPC_CheckPredicate, + 30, + 134, + 31, + 0, // Skip to: 17205 + /* 9135 */ MCD_OPC_Decode, + 222, + 20, + 255, + 1, // Opcode: SUBSUU_S_W + /* 9140 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 9155 + /* 9145 */ MCD_OPC_CheckPredicate, + 30, + 119, + 31, + 0, // Skip to: 17205 + /* 9150 */ MCD_OPC_Decode, + 220, + 20, + 128, + 2, // Opcode: SUBSUU_S_D + /* 9155 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 9170 + /* 9160 */ MCD_OPC_CheckPredicate, + 30, + 104, + 31, + 0, // Skip to: 17205 + /* 9165 */ MCD_OPC_Decode, + 161, + 6, + 253, + 1, // Opcode: ASUB_S_B + /* 9170 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 9185 + /* 9175 */ MCD_OPC_CheckPredicate, + 30, + 89, + 31, + 0, // Skip to: 17205 + /* 9180 */ MCD_OPC_Decode, + 163, + 6, + 254, + 1, // Opcode: ASUB_S_H + /* 9185 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 9200 + /* 9190 */ MCD_OPC_CheckPredicate, + 30, + 74, + 31, + 0, // Skip to: 17205 + /* 9195 */ MCD_OPC_Decode, + 164, + 6, + 255, + 1, // Opcode: ASUB_S_W + /* 9200 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 9215 + /* 9205 */ MCD_OPC_CheckPredicate, + 30, + 59, + 31, + 0, // Skip to: 17205 + /* 9210 */ MCD_OPC_Decode, + 162, + 6, + 128, + 2, // Opcode: ASUB_S_D + /* 9215 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 9230 + /* 9220 */ MCD_OPC_CheckPredicate, + 30, + 44, + 31, + 0, // Skip to: 17205 + /* 9225 */ MCD_OPC_Decode, + 165, + 6, + 253, + 1, // Opcode: ASUB_U_B + /* 9230 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 9245 + /* 9235 */ MCD_OPC_CheckPredicate, + 30, + 29, + 31, + 0, // Skip to: 17205 + /* 9240 */ MCD_OPC_Decode, + 167, + 6, + 254, + 1, // Opcode: ASUB_U_H + /* 9245 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 9260 + /* 9250 */ MCD_OPC_CheckPredicate, + 30, + 14, + 31, + 0, // Skip to: 17205 + /* 9255 */ MCD_OPC_Decode, + 168, + 6, + 255, + 1, // Opcode: ASUB_U_W + /* 9260 */ MCD_OPC_FilterValue, + 23, + 4, + 31, + 0, // Skip to: 17205 + /* 9265 */ MCD_OPC_CheckPredicate, + 30, + 255, + 30, + 0, // Skip to: 17205 + /* 9270 */ MCD_OPC_Decode, + 166, + 6, + 128, + 2, // Opcode: ASUB_U_D + /* 9275 */ MCD_OPC_FilterValue, + 18, + 167, + 1, + 0, // Skip to: 9703 + /* 9280 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 9283 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9298 + /* 9288 */ MCD_OPC_CheckPredicate, + 30, + 232, + 30, + 0, // Skip to: 17205 + /* 9293 */ MCD_OPC_Decode, + 175, + 17, + 253, + 1, // Opcode: MULV_B + /* 9298 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9313 + /* 9303 */ MCD_OPC_CheckPredicate, + 30, + 217, + 30, + 0, // Skip to: 17205 + /* 9308 */ MCD_OPC_Decode, + 177, + 17, + 254, + 1, // Opcode: MULV_H + /* 9313 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9328 + /* 9318 */ MCD_OPC_CheckPredicate, + 30, + 202, + 30, + 0, // Skip to: 17205 + /* 9323 */ MCD_OPC_Decode, + 178, + 17, + 255, + 1, // Opcode: MULV_W + /* 9328 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 9343 + /* 9333 */ MCD_OPC_CheckPredicate, + 30, + 187, + 30, + 0, // Skip to: 17205 + /* 9338 */ MCD_OPC_Decode, + 176, + 17, + 128, + 2, // Opcode: MULV_D + /* 9343 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 9358 + /* 9348 */ MCD_OPC_CheckPredicate, + 30, + 172, + 30, + 0, // Skip to: 17205 + /* 9353 */ MCD_OPC_Decode, + 162, + 15, + 129, + 2, // Opcode: MADDV_B + /* 9358 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 9373 + /* 9363 */ MCD_OPC_CheckPredicate, + 30, + 157, + 30, + 0, // Skip to: 17205 + /* 9368 */ MCD_OPC_Decode, + 164, + 15, + 130, + 2, // Opcode: MADDV_H + /* 9373 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 9388 + /* 9378 */ MCD_OPC_CheckPredicate, + 30, + 142, + 30, + 0, // Skip to: 17205 + /* 9383 */ MCD_OPC_Decode, + 165, + 15, + 131, + 2, // Opcode: MADDV_W + /* 9388 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 9403 + /* 9393 */ MCD_OPC_CheckPredicate, + 30, + 127, + 30, + 0, // Skip to: 17205 + /* 9398 */ MCD_OPC_Decode, + 163, + 15, + 132, + 2, // Opcode: MADDV_D + /* 9403 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 9418 + /* 9408 */ MCD_OPC_CheckPredicate, + 30, + 112, + 30, + 0, // Skip to: 17205 + /* 9413 */ MCD_OPC_Decode, + 213, + 16, + 129, + 2, // Opcode: MSUBV_B + /* 9418 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 9433 + /* 9423 */ MCD_OPC_CheckPredicate, + 30, + 97, + 30, + 0, // Skip to: 17205 + /* 9428 */ MCD_OPC_Decode, + 215, + 16, + 130, + 2, // Opcode: MSUBV_H + /* 9433 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 9448 + /* 9438 */ MCD_OPC_CheckPredicate, + 30, + 82, + 30, + 0, // Skip to: 17205 + /* 9443 */ MCD_OPC_Decode, + 216, + 16, + 131, + 2, // Opcode: MSUBV_W + /* 9448 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 9463 + /* 9453 */ MCD_OPC_CheckPredicate, + 30, + 67, + 30, + 0, // Skip to: 17205 + /* 9458 */ MCD_OPC_Decode, + 214, + 16, + 132, + 2, // Opcode: MSUBV_D + /* 9463 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 9478 + /* 9468 */ MCD_OPC_CheckPredicate, + 30, + 52, + 30, + 0, // Skip to: 17205 + /* 9473 */ MCD_OPC_Decode, + 243, + 10, + 253, + 1, // Opcode: DIV_S_B + /* 9478 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 9493 + /* 9483 */ MCD_OPC_CheckPredicate, + 30, + 37, + 30, + 0, // Skip to: 17205 + /* 9488 */ MCD_OPC_Decode, + 245, + 10, + 254, + 1, // Opcode: DIV_S_H + /* 9493 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 9508 + /* 9498 */ MCD_OPC_CheckPredicate, + 30, + 22, + 30, + 0, // Skip to: 17205 + /* 9503 */ MCD_OPC_Decode, + 246, + 10, + 255, + 1, // Opcode: DIV_S_W + /* 9508 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 9523 + /* 9513 */ MCD_OPC_CheckPredicate, + 30, + 7, + 30, + 0, // Skip to: 17205 + /* 9518 */ MCD_OPC_Decode, + 244, + 10, + 128, + 2, // Opcode: DIV_S_D + /* 9523 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 9538 + /* 9528 */ MCD_OPC_CheckPredicate, + 30, + 248, + 29, + 0, // Skip to: 17205 + /* 9533 */ MCD_OPC_Decode, + 247, + 10, + 253, + 1, // Opcode: DIV_U_B + /* 9538 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 9553 + /* 9543 */ MCD_OPC_CheckPredicate, + 30, + 233, + 29, + 0, // Skip to: 17205 + /* 9548 */ MCD_OPC_Decode, + 249, + 10, + 254, + 1, // Opcode: DIV_U_H + /* 9553 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 9568 + /* 9558 */ MCD_OPC_CheckPredicate, + 30, + 218, + 29, + 0, // Skip to: 17205 + /* 9563 */ MCD_OPC_Decode, + 250, + 10, + 255, + 1, // Opcode: DIV_U_W + /* 9568 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 9583 + /* 9573 */ MCD_OPC_CheckPredicate, + 30, + 203, + 29, + 0, // Skip to: 17205 + /* 9578 */ MCD_OPC_Decode, + 248, + 10, + 128, + 2, // Opcode: DIV_U_D + /* 9583 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 9598 + /* 9588 */ MCD_OPC_CheckPredicate, + 30, + 188, + 29, + 0, // Skip to: 17205 + /* 9593 */ MCD_OPC_Decode, + 149, + 16, + 253, + 1, // Opcode: MOD_S_B + /* 9598 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 9613 + /* 9603 */ MCD_OPC_CheckPredicate, + 30, + 173, + 29, + 0, // Skip to: 17205 + /* 9608 */ MCD_OPC_Decode, + 151, + 16, + 254, + 1, // Opcode: MOD_S_H + /* 9613 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 9628 + /* 9618 */ MCD_OPC_CheckPredicate, + 30, + 158, + 29, + 0, // Skip to: 17205 + /* 9623 */ MCD_OPC_Decode, + 152, + 16, + 255, + 1, // Opcode: MOD_S_W + /* 9628 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 9643 + /* 9633 */ MCD_OPC_CheckPredicate, + 30, + 143, + 29, + 0, // Skip to: 17205 + /* 9638 */ MCD_OPC_Decode, + 150, + 16, + 128, + 2, // Opcode: MOD_S_D + /* 9643 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 9658 + /* 9648 */ MCD_OPC_CheckPredicate, + 30, + 128, + 29, + 0, // Skip to: 17205 + /* 9653 */ MCD_OPC_Decode, + 153, + 16, + 253, + 1, // Opcode: MOD_U_B + /* 9658 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 9673 + /* 9663 */ MCD_OPC_CheckPredicate, + 30, + 113, + 29, + 0, // Skip to: 17205 + /* 9668 */ MCD_OPC_Decode, + 155, + 16, + 254, + 1, // Opcode: MOD_U_H + /* 9673 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 9688 + /* 9678 */ MCD_OPC_CheckPredicate, + 30, + 98, + 29, + 0, // Skip to: 17205 + /* 9683 */ MCD_OPC_Decode, + 156, + 16, + 255, + 1, // Opcode: MOD_U_W + /* 9688 */ MCD_OPC_FilterValue, + 31, + 88, + 29, + 0, // Skip to: 17205 + /* 9693 */ MCD_OPC_CheckPredicate, + 30, + 83, + 29, + 0, // Skip to: 17205 + /* 9698 */ MCD_OPC_Decode, + 154, + 16, + 128, + 2, // Opcode: MOD_U_D + /* 9703 */ MCD_OPC_FilterValue, + 19, + 17, + 1, + 0, // Skip to: 9981 + /* 9708 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 9711 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9726 + /* 9716 */ MCD_OPC_CheckPredicate, + 30, + 60, + 29, + 0, // Skip to: 17205 + /* 9721 */ MCD_OPC_Decode, + 148, + 11, + 133, + 2, // Opcode: DOTP_S_H + /* 9726 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9741 + /* 9731 */ MCD_OPC_CheckPredicate, + 30, + 45, + 29, + 0, // Skip to: 17205 + /* 9736 */ MCD_OPC_Decode, + 149, + 11, + 134, + 2, // Opcode: DOTP_S_W + /* 9741 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 9756 + /* 9746 */ MCD_OPC_CheckPredicate, + 30, + 30, + 29, + 0, // Skip to: 17205 + /* 9751 */ MCD_OPC_Decode, + 147, + 11, + 135, + 2, // Opcode: DOTP_S_D + /* 9756 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 9771 + /* 9761 */ MCD_OPC_CheckPredicate, + 30, + 15, + 29, + 0, // Skip to: 17205 + /* 9766 */ MCD_OPC_Decode, + 151, + 11, + 133, + 2, // Opcode: DOTP_U_H + /* 9771 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 9786 + /* 9776 */ MCD_OPC_CheckPredicate, + 30, + 0, + 29, + 0, // Skip to: 17205 + /* 9781 */ MCD_OPC_Decode, + 152, + 11, + 134, + 2, // Opcode: DOTP_U_W + /* 9786 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 9801 + /* 9791 */ MCD_OPC_CheckPredicate, + 30, + 241, + 28, + 0, // Skip to: 17205 + /* 9796 */ MCD_OPC_Decode, + 150, + 11, + 135, + 2, // Opcode: DOTP_U_D + /* 9801 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 9816 + /* 9806 */ MCD_OPC_CheckPredicate, + 30, + 226, + 28, + 0, // Skip to: 17205 + /* 9811 */ MCD_OPC_Decode, + 154, + 11, + 136, + 2, // Opcode: DPADD_S_H + /* 9816 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 9831 + /* 9821 */ MCD_OPC_CheckPredicate, + 30, + 211, + 28, + 0, // Skip to: 17205 + /* 9826 */ MCD_OPC_Decode, + 155, + 11, + 137, + 2, // Opcode: DPADD_S_W + /* 9831 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 9846 + /* 9836 */ MCD_OPC_CheckPredicate, + 30, + 196, + 28, + 0, // Skip to: 17205 + /* 9841 */ MCD_OPC_Decode, + 153, + 11, + 138, + 2, // Opcode: DPADD_S_D + /* 9846 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 9861 + /* 9851 */ MCD_OPC_CheckPredicate, + 30, + 181, + 28, + 0, // Skip to: 17205 + /* 9856 */ MCD_OPC_Decode, + 157, + 11, + 136, + 2, // Opcode: DPADD_U_H + /* 9861 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9876 + /* 9866 */ MCD_OPC_CheckPredicate, + 30, + 166, + 28, + 0, // Skip to: 17205 + /* 9871 */ MCD_OPC_Decode, + 158, + 11, + 137, + 2, // Opcode: DPADD_U_W + /* 9876 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 9891 + /* 9881 */ MCD_OPC_CheckPredicate, + 30, + 151, + 28, + 0, // Skip to: 17205 + /* 9886 */ MCD_OPC_Decode, + 156, + 11, + 138, + 2, // Opcode: DPADD_U_D + /* 9891 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 9906 + /* 9896 */ MCD_OPC_CheckPredicate, + 30, + 136, + 28, + 0, // Skip to: 17205 + /* 9901 */ MCD_OPC_Decode, + 185, + 11, + 136, + 2, // Opcode: DPSUB_S_H + /* 9906 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 9921 + /* 9911 */ MCD_OPC_CheckPredicate, + 30, + 121, + 28, + 0, // Skip to: 17205 + /* 9916 */ MCD_OPC_Decode, + 186, + 11, + 137, + 2, // Opcode: DPSUB_S_W + /* 9921 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 9936 + /* 9926 */ MCD_OPC_CheckPredicate, + 30, + 106, + 28, + 0, // Skip to: 17205 + /* 9931 */ MCD_OPC_Decode, + 184, + 11, + 138, + 2, // Opcode: DPSUB_S_D + /* 9936 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 9951 + /* 9941 */ MCD_OPC_CheckPredicate, + 30, + 91, + 28, + 0, // Skip to: 17205 + /* 9946 */ MCD_OPC_Decode, + 188, + 11, + 136, + 2, // Opcode: DPSUB_U_H + /* 9951 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 9966 + /* 9956 */ MCD_OPC_CheckPredicate, + 30, + 76, + 28, + 0, // Skip to: 17205 + /* 9961 */ MCD_OPC_Decode, + 189, + 11, + 137, + 2, // Opcode: DPSUB_U_W + /* 9966 */ MCD_OPC_FilterValue, + 23, + 66, + 28, + 0, // Skip to: 17205 + /* 9971 */ MCD_OPC_CheckPredicate, + 30, + 61, + 28, + 0, // Skip to: 17205 + /* 9976 */ MCD_OPC_Decode, + 187, + 11, + 138, + 2, // Opcode: DPSUB_U_D + /* 9981 */ MCD_OPC_FilterValue, + 20, + 227, + 1, + 0, // Skip to: 10469 + /* 9986 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 9989 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10004 + /* 9994 */ MCD_OPC_CheckPredicate, + 30, + 38, + 28, + 0, // Skip to: 17205 + /* 9999 */ MCD_OPC_Decode, + 236, + 19, + 139, + 2, // Opcode: SLD_B + /* 10004 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10019 + /* 10009 */ MCD_OPC_CheckPredicate, + 30, + 23, + 28, + 0, // Skip to: 17205 + /* 10014 */ MCD_OPC_Decode, + 238, + 19, + 140, + 2, // Opcode: SLD_H + /* 10019 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10034 + /* 10024 */ MCD_OPC_CheckPredicate, + 30, + 8, + 28, + 0, // Skip to: 17205 + /* 10029 */ MCD_OPC_Decode, + 239, + 19, + 141, + 2, // Opcode: SLD_W + /* 10034 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 10049 + /* 10039 */ MCD_OPC_CheckPredicate, + 30, + 249, + 27, + 0, // Skip to: 17205 + /* 10044 */ MCD_OPC_Decode, + 237, + 19, + 142, + 2, // Opcode: SLD_D + /* 10049 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 10064 + /* 10054 */ MCD_OPC_CheckPredicate, + 30, + 234, + 27, + 0, // Skip to: 17205 + /* 10059 */ MCD_OPC_Decode, + 147, + 20, + 143, + 2, // Opcode: SPLAT_B + /* 10064 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 10079 + /* 10069 */ MCD_OPC_CheckPredicate, + 30, + 219, + 27, + 0, // Skip to: 17205 + /* 10074 */ MCD_OPC_Decode, + 149, + 20, + 144, + 2, // Opcode: SPLAT_H + /* 10079 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 10094 + /* 10084 */ MCD_OPC_CheckPredicate, + 30, + 204, + 27, + 0, // Skip to: 17205 + /* 10089 */ MCD_OPC_Decode, + 150, + 20, + 145, + 2, // Opcode: SPLAT_W + /* 10094 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 10109 + /* 10099 */ MCD_OPC_CheckPredicate, + 30, + 189, + 27, + 0, // Skip to: 17205 + /* 10104 */ MCD_OPC_Decode, + 148, + 20, + 146, + 2, // Opcode: SPLAT_D + /* 10109 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 10124 + /* 10114 */ MCD_OPC_CheckPredicate, + 30, + 174, + 27, + 0, // Skip to: 17205 + /* 10119 */ MCD_OPC_Decode, + 238, + 17, + 253, + 1, // Opcode: PCKEV_B + /* 10124 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 10139 + /* 10129 */ MCD_OPC_CheckPredicate, + 30, + 159, + 27, + 0, // Skip to: 17205 + /* 10134 */ MCD_OPC_Decode, + 240, + 17, + 254, + 1, // Opcode: PCKEV_H + /* 10139 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 10154 + /* 10144 */ MCD_OPC_CheckPredicate, + 30, + 144, + 27, + 0, // Skip to: 17205 + /* 10149 */ MCD_OPC_Decode, + 241, + 17, + 255, + 1, // Opcode: PCKEV_W + /* 10154 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 10169 + /* 10159 */ MCD_OPC_CheckPredicate, + 30, + 129, + 27, + 0, // Skip to: 17205 + /* 10164 */ MCD_OPC_Decode, + 239, + 17, + 128, + 2, // Opcode: PCKEV_D + /* 10169 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 10184 + /* 10174 */ MCD_OPC_CheckPredicate, + 30, + 114, + 27, + 0, // Skip to: 17205 + /* 10179 */ MCD_OPC_Decode, + 242, + 17, + 253, + 1, // Opcode: PCKOD_B + /* 10184 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 10199 + /* 10189 */ MCD_OPC_CheckPredicate, + 30, + 99, + 27, + 0, // Skip to: 17205 + /* 10194 */ MCD_OPC_Decode, + 244, + 17, + 254, + 1, // Opcode: PCKOD_H + /* 10199 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10214 + /* 10204 */ MCD_OPC_CheckPredicate, + 30, + 84, + 27, + 0, // Skip to: 17205 + /* 10209 */ MCD_OPC_Decode, + 245, + 17, + 255, + 1, // Opcode: PCKOD_W + /* 10214 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 10229 + /* 10219 */ MCD_OPC_CheckPredicate, + 30, + 69, + 27, + 0, // Skip to: 17205 + /* 10224 */ MCD_OPC_Decode, + 243, + 17, + 128, + 2, // Opcode: PCKOD_D + /* 10229 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 10244 + /* 10234 */ MCD_OPC_CheckPredicate, + 30, + 54, + 27, + 0, // Skip to: 17205 + /* 10239 */ MCD_OPC_Decode, + 213, + 13, + 253, + 1, // Opcode: ILVL_B + /* 10244 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 10259 + /* 10249 */ MCD_OPC_CheckPredicate, + 30, + 39, + 27, + 0, // Skip to: 17205 + /* 10254 */ MCD_OPC_Decode, + 215, + 13, + 254, + 1, // Opcode: ILVL_H + /* 10259 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 10274 + /* 10264 */ MCD_OPC_CheckPredicate, + 30, + 24, + 27, + 0, // Skip to: 17205 + /* 10269 */ MCD_OPC_Decode, + 216, + 13, + 255, + 1, // Opcode: ILVL_W + /* 10274 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 10289 + /* 10279 */ MCD_OPC_CheckPredicate, + 30, + 9, + 27, + 0, // Skip to: 17205 + /* 10284 */ MCD_OPC_Decode, + 214, + 13, + 128, + 2, // Opcode: ILVL_D + /* 10289 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 10304 + /* 10294 */ MCD_OPC_CheckPredicate, + 30, + 250, + 26, + 0, // Skip to: 17205 + /* 10299 */ MCD_OPC_Decode, + 221, + 13, + 253, + 1, // Opcode: ILVR_B + /* 10304 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 10319 + /* 10309 */ MCD_OPC_CheckPredicate, + 30, + 235, + 26, + 0, // Skip to: 17205 + /* 10314 */ MCD_OPC_Decode, + 223, + 13, + 254, + 1, // Opcode: ILVR_H + /* 10319 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 10334 + /* 10324 */ MCD_OPC_CheckPredicate, + 30, + 220, + 26, + 0, // Skip to: 17205 + /* 10329 */ MCD_OPC_Decode, + 224, + 13, + 255, + 1, // Opcode: ILVR_W + /* 10334 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 10349 + /* 10339 */ MCD_OPC_CheckPredicate, + 30, + 205, + 26, + 0, // Skip to: 17205 + /* 10344 */ MCD_OPC_Decode, + 222, + 13, + 128, + 2, // Opcode: ILVR_D + /* 10349 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 10364 + /* 10354 */ MCD_OPC_CheckPredicate, + 30, + 190, + 26, + 0, // Skip to: 17205 + /* 10359 */ MCD_OPC_Decode, + 209, + 13, + 253, + 1, // Opcode: ILVEV_B + /* 10364 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 10379 + /* 10369 */ MCD_OPC_CheckPredicate, + 30, + 175, + 26, + 0, // Skip to: 17205 + /* 10374 */ MCD_OPC_Decode, + 211, + 13, + 254, + 1, // Opcode: ILVEV_H + /* 10379 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 10394 + /* 10384 */ MCD_OPC_CheckPredicate, + 30, + 160, + 26, + 0, // Skip to: 17205 + /* 10389 */ MCD_OPC_Decode, + 212, + 13, + 255, + 1, // Opcode: ILVEV_W + /* 10394 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 10409 + /* 10399 */ MCD_OPC_CheckPredicate, + 30, + 145, + 26, + 0, // Skip to: 17205 + /* 10404 */ MCD_OPC_Decode, + 210, + 13, + 128, + 2, // Opcode: ILVEV_D + /* 10409 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 10424 + /* 10414 */ MCD_OPC_CheckPredicate, + 30, + 130, + 26, + 0, // Skip to: 17205 + /* 10419 */ MCD_OPC_Decode, + 217, + 13, + 253, + 1, // Opcode: ILVOD_B + /* 10424 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 10439 + /* 10429 */ MCD_OPC_CheckPredicate, + 30, + 115, + 26, + 0, // Skip to: 17205 + /* 10434 */ MCD_OPC_Decode, + 219, + 13, + 254, + 1, // Opcode: ILVOD_H + /* 10439 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 10454 + /* 10444 */ MCD_OPC_CheckPredicate, + 30, + 100, + 26, + 0, // Skip to: 17205 + /* 10449 */ MCD_OPC_Decode, + 220, + 13, + 255, + 1, // Opcode: ILVOD_W + /* 10454 */ MCD_OPC_FilterValue, + 31, + 90, + 26, + 0, // Skip to: 17205 + /* 10459 */ MCD_OPC_CheckPredicate, + 30, + 85, + 26, + 0, // Skip to: 17205 + /* 10464 */ MCD_OPC_Decode, + 218, + 13, + 128, + 2, // Opcode: ILVOD_D + /* 10469 */ MCD_OPC_FilterValue, + 21, + 107, + 1, + 0, // Skip to: 10837 + /* 10474 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 10477 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10492 + /* 10482 */ MCD_OPC_CheckPredicate, + 30, + 62, + 26, + 0, // Skip to: 17205 + /* 10487 */ MCD_OPC_Decode, + 132, + 22, + 129, + 2, // Opcode: VSHF_B + /* 10492 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10507 + /* 10497 */ MCD_OPC_CheckPredicate, + 30, + 47, + 26, + 0, // Skip to: 17205 + /* 10502 */ MCD_OPC_Decode, + 134, + 22, + 130, + 2, // Opcode: VSHF_H + /* 10507 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10522 + /* 10512 */ MCD_OPC_CheckPredicate, + 30, + 32, + 26, + 0, // Skip to: 17205 + /* 10517 */ MCD_OPC_Decode, + 135, + 22, + 131, + 2, // Opcode: VSHF_W + /* 10522 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 10537 + /* 10527 */ MCD_OPC_CheckPredicate, + 30, + 17, + 26, + 0, // Skip to: 17205 + /* 10532 */ MCD_OPC_Decode, + 133, + 22, + 132, + 2, // Opcode: VSHF_D + /* 10537 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 10552 + /* 10542 */ MCD_OPC_CheckPredicate, + 30, + 2, + 26, + 0, // Skip to: 17205 + /* 10547 */ MCD_OPC_Decode, + 160, + 20, + 253, + 1, // Opcode: SRAR_B + /* 10552 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 10567 + /* 10557 */ MCD_OPC_CheckPredicate, + 30, + 243, + 25, + 0, // Skip to: 17205 + /* 10562 */ MCD_OPC_Decode, + 162, + 20, + 254, + 1, // Opcode: SRAR_H + /* 10567 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 10582 + /* 10572 */ MCD_OPC_CheckPredicate, + 30, + 228, + 25, + 0, // Skip to: 17205 + /* 10577 */ MCD_OPC_Decode, + 163, + 20, + 255, + 1, // Opcode: SRAR_W + /* 10582 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 10597 + /* 10587 */ MCD_OPC_CheckPredicate, + 30, + 213, + 25, + 0, // Skip to: 17205 + /* 10592 */ MCD_OPC_Decode, + 161, + 20, + 128, + 2, // Opcode: SRAR_D + /* 10597 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 10612 + /* 10602 */ MCD_OPC_CheckPredicate, + 30, + 198, + 25, + 0, // Skip to: 17205 + /* 10607 */ MCD_OPC_Decode, + 182, + 20, + 253, + 1, // Opcode: SRLR_B + /* 10612 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 10627 + /* 10617 */ MCD_OPC_CheckPredicate, + 30, + 183, + 25, + 0, // Skip to: 17205 + /* 10622 */ MCD_OPC_Decode, + 184, + 20, + 254, + 1, // Opcode: SRLR_H + /* 10627 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 10642 + /* 10632 */ MCD_OPC_CheckPredicate, + 30, + 168, + 25, + 0, // Skip to: 17205 + /* 10637 */ MCD_OPC_Decode, + 185, + 20, + 255, + 1, // Opcode: SRLR_W + /* 10642 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 10657 + /* 10647 */ MCD_OPC_CheckPredicate, + 30, + 153, + 25, + 0, // Skip to: 17205 + /* 10652 */ MCD_OPC_Decode, + 183, + 20, + 128, + 2, // Opcode: SRLR_D + /* 10657 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 10672 + /* 10662 */ MCD_OPC_CheckPredicate, + 30, + 138, + 25, + 0, // Skip to: 17205 + /* 10667 */ MCD_OPC_Decode, + 196, + 13, + 133, + 2, // Opcode: HADD_S_H + /* 10672 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 10687 + /* 10677 */ MCD_OPC_CheckPredicate, + 30, + 123, + 25, + 0, // Skip to: 17205 + /* 10682 */ MCD_OPC_Decode, + 197, + 13, + 134, + 2, // Opcode: HADD_S_W + /* 10687 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 10702 + /* 10692 */ MCD_OPC_CheckPredicate, + 30, + 108, + 25, + 0, // Skip to: 17205 + /* 10697 */ MCD_OPC_Decode, + 195, + 13, + 135, + 2, // Opcode: HADD_S_D + /* 10702 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 10717 + /* 10707 */ MCD_OPC_CheckPredicate, + 30, + 93, + 25, + 0, // Skip to: 17205 + /* 10712 */ MCD_OPC_Decode, + 199, + 13, + 133, + 2, // Opcode: HADD_U_H + /* 10717 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 10732 + /* 10722 */ MCD_OPC_CheckPredicate, + 30, + 78, + 25, + 0, // Skip to: 17205 + /* 10727 */ MCD_OPC_Decode, + 200, + 13, + 134, + 2, // Opcode: HADD_U_W + /* 10732 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 10747 + /* 10737 */ MCD_OPC_CheckPredicate, + 30, + 63, + 25, + 0, // Skip to: 17205 + /* 10742 */ MCD_OPC_Decode, + 198, + 13, + 135, + 2, // Opcode: HADD_U_D + /* 10747 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 10762 + /* 10752 */ MCD_OPC_CheckPredicate, + 30, + 48, + 25, + 0, // Skip to: 17205 + /* 10757 */ MCD_OPC_Decode, + 202, + 13, + 133, + 2, // Opcode: HSUB_S_H + /* 10762 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 10777 + /* 10767 */ MCD_OPC_CheckPredicate, + 30, + 33, + 25, + 0, // Skip to: 17205 + /* 10772 */ MCD_OPC_Decode, + 203, + 13, + 134, + 2, // Opcode: HSUB_S_W + /* 10777 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 10792 + /* 10782 */ MCD_OPC_CheckPredicate, + 30, + 18, + 25, + 0, // Skip to: 17205 + /* 10787 */ MCD_OPC_Decode, + 201, + 13, + 135, + 2, // Opcode: HSUB_S_D + /* 10792 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 10807 + /* 10797 */ MCD_OPC_CheckPredicate, + 30, + 3, + 25, + 0, // Skip to: 17205 + /* 10802 */ MCD_OPC_Decode, + 205, + 13, + 133, + 2, // Opcode: HSUB_U_H + /* 10807 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 10822 + /* 10812 */ MCD_OPC_CheckPredicate, + 30, + 244, + 24, + 0, // Skip to: 17205 + /* 10817 */ MCD_OPC_Decode, + 206, + 13, + 134, + 2, // Opcode: HSUB_U_W + /* 10822 */ MCD_OPC_FilterValue, + 31, + 234, + 24, + 0, // Skip to: 17205 + /* 10827 */ MCD_OPC_CheckPredicate, + 30, + 229, + 24, + 0, // Skip to: 17205 + /* 10832 */ MCD_OPC_Decode, + 204, + 13, + 135, + 2, // Opcode: HSUB_U_D + /* 10837 */ MCD_OPC_FilterValue, + 25, + 26, + 2, + 0, // Skip to: 11380 + /* 10842 */ MCD_OPC_ExtractField, + 20, + 6, // Inst{25-20} ... + /* 10845 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10860 + /* 10850 */ MCD_OPC_CheckPredicate, + 30, + 206, + 24, + 0, // Skip to: 17205 + /* 10855 */ MCD_OPC_Decode, + 232, + 19, + 147, + 2, // Opcode: SLDI_B + /* 10860 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 10882 + /* 10865 */ MCD_OPC_CheckPredicate, + 30, + 191, + 24, + 0, // Skip to: 17205 + /* 10870 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 184, + 24, + 0, // Skip to: 17205 + /* 10877 */ MCD_OPC_Decode, + 234, + 19, + 148, + 2, // Opcode: SLDI_H + /* 10882 */ MCD_OPC_FilterValue, + 3, + 62, + 0, + 0, // Skip to: 10949 + /* 10887 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 10890 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10905 + /* 10895 */ MCD_OPC_CheckPredicate, + 30, + 161, + 24, + 0, // Skip to: 17205 + /* 10900 */ MCD_OPC_Decode, + 235, + 19, + 149, + 2, // Opcode: SLDI_W + /* 10905 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 10927 + /* 10910 */ MCD_OPC_CheckPredicate, + 30, + 146, + 24, + 0, // Skip to: 17205 + /* 10915 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 139, + 24, + 0, // Skip to: 17205 + /* 10922 */ MCD_OPC_Decode, + 233, + 19, + 150, + 2, // Opcode: SLDI_D + /* 10927 */ MCD_OPC_FilterValue, + 3, + 129, + 24, + 0, // Skip to: 17205 + /* 10932 */ MCD_OPC_CheckPredicate, + 30, + 124, + 24, + 0, // Skip to: 17205 + /* 10937 */ MCD_OPC_CheckField, + 16, + 2, + 2, + 117, + 24, + 0, // Skip to: 17205 + /* 10944 */ MCD_OPC_Decode, + 204, + 9, + 151, + 2, // Opcode: CTCMSA + /* 10949 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 10964 + /* 10954 */ MCD_OPC_CheckPredicate, + 30, + 102, + 24, + 0, // Skip to: 17205 + /* 10959 */ MCD_OPC_Decode, + 143, + 20, + 152, + 2, // Opcode: SPLATI_B + /* 10964 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 10986 + /* 10969 */ MCD_OPC_CheckPredicate, + 30, + 87, + 24, + 0, // Skip to: 17205 + /* 10974 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 80, + 24, + 0, // Skip to: 17205 + /* 10981 */ MCD_OPC_Decode, + 145, + 20, + 153, + 2, // Opcode: SPLATI_H + /* 10986 */ MCD_OPC_FilterValue, + 7, + 62, + 0, + 0, // Skip to: 11053 + /* 10991 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 10994 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11009 + /* 10999 */ MCD_OPC_CheckPredicate, + 30, + 57, + 24, + 0, // Skip to: 17205 + /* 11004 */ MCD_OPC_Decode, + 146, + 20, + 154, + 2, // Opcode: SPLATI_W + /* 11009 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 11031 + /* 11014 */ MCD_OPC_CheckPredicate, + 30, + 42, + 24, + 0, // Skip to: 17205 + /* 11019 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 35, + 24, + 0, // Skip to: 17205 + /* 11026 */ MCD_OPC_Decode, + 144, + 20, + 155, + 2, // Opcode: SPLATI_D + /* 11031 */ MCD_OPC_FilterValue, + 3, + 25, + 24, + 0, // Skip to: 17205 + /* 11036 */ MCD_OPC_CheckPredicate, + 30, + 20, + 24, + 0, // Skip to: 17205 + /* 11041 */ MCD_OPC_CheckField, + 16, + 2, + 2, + 13, + 24, + 0, // Skip to: 17205 + /* 11048 */ MCD_OPC_Decode, + 177, + 8, + 156, + 2, // Opcode: CFCMSA + /* 11053 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 11068 + /* 11058 */ MCD_OPC_CheckPredicate, + 30, + 254, + 23, + 0, // Skip to: 17205 + /* 11063 */ MCD_OPC_Decode, + 186, + 9, + 157, + 2, // Opcode: COPY_S_B + /* 11068 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 11090 + /* 11073 */ MCD_OPC_CheckPredicate, + 30, + 239, + 23, + 0, // Skip to: 17205 + /* 11078 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 232, + 23, + 0, // Skip to: 17205 + /* 11085 */ MCD_OPC_Decode, + 188, + 9, + 158, + 2, // Opcode: COPY_S_H + /* 11090 */ MCD_OPC_FilterValue, + 11, + 62, + 0, + 0, // Skip to: 11157 + /* 11095 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 11098 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11113 + /* 11103 */ MCD_OPC_CheckPredicate, + 30, + 209, + 23, + 0, // Skip to: 17205 + /* 11108 */ MCD_OPC_Decode, + 189, + 9, + 159, + 2, // Opcode: COPY_S_W + /* 11113 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 11135 + /* 11118 */ MCD_OPC_CheckPredicate, + 38, + 194, + 23, + 0, // Skip to: 17205 + /* 11123 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 187, + 23, + 0, // Skip to: 17205 + /* 11130 */ MCD_OPC_Decode, + 187, + 9, + 160, + 2, // Opcode: COPY_S_D + /* 11135 */ MCD_OPC_FilterValue, + 3, + 177, + 23, + 0, // Skip to: 17205 + /* 11140 */ MCD_OPC_CheckPredicate, + 30, + 172, + 23, + 0, // Skip to: 17205 + /* 11145 */ MCD_OPC_CheckField, + 16, + 2, + 2, + 165, + 23, + 0, // Skip to: 17205 + /* 11152 */ MCD_OPC_Decode, + 161, + 16, + 161, + 2, // Opcode: MOVE_V + /* 11157 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 11172 + /* 11162 */ MCD_OPC_CheckPredicate, + 30, + 150, + 23, + 0, // Skip to: 17205 + /* 11167 */ MCD_OPC_Decode, + 190, + 9, + 157, + 2, // Opcode: COPY_U_B + /* 11172 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 11194 + /* 11177 */ MCD_OPC_CheckPredicate, + 30, + 135, + 23, + 0, // Skip to: 17205 + /* 11182 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 128, + 23, + 0, // Skip to: 17205 + /* 11189 */ MCD_OPC_Decode, + 191, + 9, + 158, + 2, // Opcode: COPY_U_H + /* 11194 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 11216 + /* 11199 */ MCD_OPC_CheckPredicate, + 38, + 113, + 23, + 0, // Skip to: 17205 + /* 11204 */ MCD_OPC_CheckField, + 18, + 2, + 0, + 106, + 23, + 0, // Skip to: 17205 + /* 11211 */ MCD_OPC_Decode, + 192, + 9, + 159, + 2, // Opcode: COPY_U_W + /* 11216 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 11231 + /* 11221 */ MCD_OPC_CheckPredicate, + 30, + 91, + 23, + 0, // Skip to: 17205 + /* 11226 */ MCD_OPC_Decode, + 226, + 13, + 162, + 2, // Opcode: INSERT_B + /* 11231 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 11253 + /* 11236 */ MCD_OPC_CheckPredicate, + 30, + 76, + 23, + 0, // Skip to: 17205 + /* 11241 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 69, + 23, + 0, // Skip to: 17205 + /* 11248 */ MCD_OPC_Decode, + 228, + 13, + 163, + 2, // Opcode: INSERT_H + /* 11253 */ MCD_OPC_FilterValue, + 19, + 40, + 0, + 0, // Skip to: 11298 + /* 11258 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 11261 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11276 + /* 11266 */ MCD_OPC_CheckPredicate, + 30, + 46, + 23, + 0, // Skip to: 17205 + /* 11271 */ MCD_OPC_Decode, + 229, + 13, + 164, + 2, // Opcode: INSERT_W + /* 11276 */ MCD_OPC_FilterValue, + 2, + 36, + 23, + 0, // Skip to: 17205 + /* 11281 */ MCD_OPC_CheckPredicate, + 38, + 31, + 23, + 0, // Skip to: 17205 + /* 11286 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 24, + 23, + 0, // Skip to: 17205 + /* 11293 */ MCD_OPC_Decode, + 227, + 13, + 165, + 2, // Opcode: INSERT_D + /* 11298 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 11313 + /* 11303 */ MCD_OPC_CheckPredicate, + 30, + 9, + 23, + 0, // Skip to: 17205 + /* 11308 */ MCD_OPC_Decode, + 231, + 13, + 166, + 2, // Opcode: INSVE_B + /* 11313 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 11335 + /* 11318 */ MCD_OPC_CheckPredicate, + 30, + 250, + 22, + 0, // Skip to: 17205 + /* 11323 */ MCD_OPC_CheckField, + 19, + 1, + 0, + 243, + 22, + 0, // Skip to: 17205 + /* 11330 */ MCD_OPC_Decode, + 233, + 13, + 166, + 2, // Opcode: INSVE_H + /* 11335 */ MCD_OPC_FilterValue, + 23, + 233, + 22, + 0, // Skip to: 17205 + /* 11340 */ MCD_OPC_ExtractField, + 18, + 2, // Inst{19-18} ... + /* 11343 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11358 + /* 11348 */ MCD_OPC_CheckPredicate, + 30, + 220, + 22, + 0, // Skip to: 17205 + /* 11353 */ MCD_OPC_Decode, + 234, + 13, + 166, + 2, // Opcode: INSVE_W + /* 11358 */ MCD_OPC_FilterValue, + 2, + 210, + 22, + 0, // Skip to: 17205 + /* 11363 */ MCD_OPC_CheckPredicate, + 30, + 205, + 22, + 0, // Skip to: 17205 + /* 11368 */ MCD_OPC_CheckField, + 17, + 1, + 0, + 198, + 22, + 0, // Skip to: 17205 + /* 11375 */ MCD_OPC_Decode, + 232, + 13, + 166, + 2, // Opcode: INSVE_D + /* 11380 */ MCD_OPC_FilterValue, + 26, + 227, + 1, + 0, // Skip to: 11868 + /* 11385 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 11388 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11403 + /* 11393 */ MCD_OPC_CheckPredicate, + 30, + 175, + 22, + 0, // Skip to: 17205 + /* 11398 */ MCD_OPC_Decode, + 155, + 12, + 255, + 1, // Opcode: FCAF_W + /* 11403 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11418 + /* 11408 */ MCD_OPC_CheckPredicate, + 30, + 160, + 22, + 0, // Skip to: 17205 + /* 11413 */ MCD_OPC_Decode, + 154, + 12, + 128, + 2, // Opcode: FCAF_D + /* 11418 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11433 + /* 11423 */ MCD_OPC_CheckPredicate, + 30, + 145, + 22, + 0, // Skip to: 17205 + /* 11428 */ MCD_OPC_Decode, + 182, + 12, + 255, + 1, // Opcode: FCUN_W + /* 11433 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 11448 + /* 11438 */ MCD_OPC_CheckPredicate, + 30, + 130, + 22, + 0, // Skip to: 17205 + /* 11443 */ MCD_OPC_Decode, + 181, + 12, + 128, + 2, // Opcode: FCUN_D + /* 11448 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 11463 + /* 11453 */ MCD_OPC_CheckPredicate, + 30, + 115, + 22, + 0, // Skip to: 17205 + /* 11458 */ MCD_OPC_Decode, + 157, + 12, + 255, + 1, // Opcode: FCEQ_W + /* 11463 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 11478 + /* 11468 */ MCD_OPC_CheckPredicate, + 30, + 100, + 22, + 0, // Skip to: 17205 + /* 11473 */ MCD_OPC_Decode, + 156, + 12, + 128, + 2, // Opcode: FCEQ_D + /* 11478 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 11493 + /* 11483 */ MCD_OPC_CheckPredicate, + 30, + 85, + 22, + 0, // Skip to: 17205 + /* 11488 */ MCD_OPC_Decode, + 174, + 12, + 255, + 1, // Opcode: FCUEQ_W + /* 11493 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 11508 + /* 11498 */ MCD_OPC_CheckPredicate, + 30, + 70, + 22, + 0, // Skip to: 17205 + /* 11503 */ MCD_OPC_Decode, + 173, + 12, + 128, + 2, // Opcode: FCUEQ_D + /* 11508 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 11523 + /* 11513 */ MCD_OPC_CheckPredicate, + 30, + 55, + 22, + 0, // Skip to: 17205 + /* 11518 */ MCD_OPC_Decode, + 163, + 12, + 255, + 1, // Opcode: FCLT_W + /* 11523 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 11538 + /* 11528 */ MCD_OPC_CheckPredicate, + 30, + 40, + 22, + 0, // Skip to: 17205 + /* 11533 */ MCD_OPC_Decode, + 162, + 12, + 128, + 2, // Opcode: FCLT_D + /* 11538 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 11553 + /* 11543 */ MCD_OPC_CheckPredicate, + 30, + 25, + 22, + 0, // Skip to: 17205 + /* 11548 */ MCD_OPC_Decode, + 178, + 12, + 255, + 1, // Opcode: FCULT_W + /* 11553 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 11568 + /* 11558 */ MCD_OPC_CheckPredicate, + 30, + 10, + 22, + 0, // Skip to: 17205 + /* 11563 */ MCD_OPC_Decode, + 177, + 12, + 128, + 2, // Opcode: FCULT_D + /* 11568 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 11583 + /* 11573 */ MCD_OPC_CheckPredicate, + 30, + 251, + 21, + 0, // Skip to: 17205 + /* 11578 */ MCD_OPC_Decode, + 161, + 12, + 255, + 1, // Opcode: FCLE_W + /* 11583 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 11598 + /* 11588 */ MCD_OPC_CheckPredicate, + 30, + 236, + 21, + 0, // Skip to: 17205 + /* 11593 */ MCD_OPC_Decode, + 160, + 12, + 128, + 2, // Opcode: FCLE_D + /* 11598 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 11613 + /* 11603 */ MCD_OPC_CheckPredicate, + 30, + 221, + 21, + 0, // Skip to: 17205 + /* 11608 */ MCD_OPC_Decode, + 176, + 12, + 255, + 1, // Opcode: FCULE_W + /* 11613 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 11628 + /* 11618 */ MCD_OPC_CheckPredicate, + 30, + 206, + 21, + 0, // Skip to: 17205 + /* 11623 */ MCD_OPC_Decode, + 175, + 12, + 128, + 2, // Opcode: FCULE_D + /* 11628 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 11643 + /* 11633 */ MCD_OPC_CheckPredicate, + 30, + 191, + 21, + 0, // Skip to: 17205 + /* 11638 */ MCD_OPC_Decode, + 142, + 13, + 255, + 1, // Opcode: FSAF_W + /* 11643 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 11658 + /* 11648 */ MCD_OPC_CheckPredicate, + 30, + 176, + 21, + 0, // Skip to: 17205 + /* 11653 */ MCD_OPC_Decode, + 141, + 13, + 128, + 2, // Opcode: FSAF_D + /* 11658 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 11673 + /* 11663 */ MCD_OPC_CheckPredicate, + 30, + 161, + 21, + 0, // Skip to: 17205 + /* 11668 */ MCD_OPC_Decode, + 180, + 13, + 255, + 1, // Opcode: FSUN_W + /* 11673 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 11688 + /* 11678 */ MCD_OPC_CheckPredicate, + 30, + 146, + 21, + 0, // Skip to: 17205 + /* 11683 */ MCD_OPC_Decode, + 179, + 13, + 128, + 2, // Opcode: FSUN_D + /* 11688 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 11703 + /* 11693 */ MCD_OPC_CheckPredicate, + 30, + 131, + 21, + 0, // Skip to: 17205 + /* 11698 */ MCD_OPC_Decode, + 144, + 13, + 255, + 1, // Opcode: FSEQ_W + /* 11703 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 11718 + /* 11708 */ MCD_OPC_CheckPredicate, + 30, + 116, + 21, + 0, // Skip to: 17205 + /* 11713 */ MCD_OPC_Decode, + 143, + 13, + 128, + 2, // Opcode: FSEQ_D + /* 11718 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 11733 + /* 11723 */ MCD_OPC_CheckPredicate, + 30, + 101, + 21, + 0, // Skip to: 17205 + /* 11728 */ MCD_OPC_Decode, + 172, + 13, + 255, + 1, // Opcode: FSUEQ_W + /* 11733 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 11748 + /* 11738 */ MCD_OPC_CheckPredicate, + 30, + 86, + 21, + 0, // Skip to: 17205 + /* 11743 */ MCD_OPC_Decode, + 171, + 13, + 128, + 2, // Opcode: FSUEQ_D + /* 11748 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 11763 + /* 11753 */ MCD_OPC_CheckPredicate, + 30, + 71, + 21, + 0, // Skip to: 17205 + /* 11758 */ MCD_OPC_Decode, + 148, + 13, + 255, + 1, // Opcode: FSLT_W + /* 11763 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 11778 + /* 11768 */ MCD_OPC_CheckPredicate, + 30, + 56, + 21, + 0, // Skip to: 17205 + /* 11773 */ MCD_OPC_Decode, + 147, + 13, + 128, + 2, // Opcode: FSLT_D + /* 11778 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 11793 + /* 11783 */ MCD_OPC_CheckPredicate, + 30, + 41, + 21, + 0, // Skip to: 17205 + /* 11788 */ MCD_OPC_Decode, + 176, + 13, + 255, + 1, // Opcode: FSULT_W + /* 11793 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 11808 + /* 11798 */ MCD_OPC_CheckPredicate, + 30, + 26, + 21, + 0, // Skip to: 17205 + /* 11803 */ MCD_OPC_Decode, + 175, + 13, + 128, + 2, // Opcode: FSULT_D + /* 11808 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 11823 + /* 11813 */ MCD_OPC_CheckPredicate, + 30, + 11, + 21, + 0, // Skip to: 17205 + /* 11818 */ MCD_OPC_Decode, + 146, + 13, + 255, + 1, // Opcode: FSLE_W + /* 11823 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 11838 + /* 11828 */ MCD_OPC_CheckPredicate, + 30, + 252, + 20, + 0, // Skip to: 17205 + /* 11833 */ MCD_OPC_Decode, + 145, + 13, + 128, + 2, // Opcode: FSLE_D + /* 11838 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 11853 + /* 11843 */ MCD_OPC_CheckPredicate, + 30, + 237, + 20, + 0, // Skip to: 17205 + /* 11848 */ MCD_OPC_Decode, + 174, + 13, + 255, + 1, // Opcode: FSULE_W + /* 11853 */ MCD_OPC_FilterValue, + 31, + 227, + 20, + 0, // Skip to: 17205 + /* 11858 */ MCD_OPC_CheckPredicate, + 30, + 222, + 20, + 0, // Skip to: 17205 + /* 11863 */ MCD_OPC_Decode, + 173, + 13, + 128, + 2, // Opcode: FSULE_D + /* 11868 */ MCD_OPC_FilterValue, + 27, + 137, + 1, + 0, // Skip to: 12266 + /* 11873 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 11876 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11891 + /* 11881 */ MCD_OPC_CheckPredicate, + 30, + 199, + 20, + 0, // Skip to: 17205 + /* 11886 */ MCD_OPC_Decode, + 153, + 12, + 255, + 1, // Opcode: FADD_W + /* 11891 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11906 + /* 11896 */ MCD_OPC_CheckPredicate, + 30, + 184, + 20, + 0, // Skip to: 17205 + /* 11901 */ MCD_OPC_Decode, + 144, + 12, + 128, + 2, // Opcode: FADD_D + /* 11906 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11921 + /* 11911 */ MCD_OPC_CheckPredicate, + 30, + 169, + 20, + 0, // Skip to: 17205 + /* 11916 */ MCD_OPC_Decode, + 170, + 13, + 255, + 1, // Opcode: FSUB_W + /* 11921 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 11936 + /* 11926 */ MCD_OPC_CheckPredicate, + 30, + 154, + 20, + 0, // Skip to: 17205 + /* 11931 */ MCD_OPC_Decode, + 161, + 13, + 128, + 2, // Opcode: FSUB_D + /* 11936 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 11951 + /* 11941 */ MCD_OPC_CheckPredicate, + 30, + 139, + 20, + 0, // Skip to: 17205 + /* 11946 */ MCD_OPC_Decode, + 254, + 12, + 255, + 1, // Opcode: FMUL_W + /* 11951 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 11966 + /* 11956 */ MCD_OPC_CheckPredicate, + 30, + 124, + 20, + 0, // Skip to: 17205 + /* 11961 */ MCD_OPC_Decode, + 245, + 12, + 128, + 2, // Opcode: FMUL_D + /* 11966 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 11981 + /* 11971 */ MCD_OPC_CheckPredicate, + 30, + 109, + 20, + 0, // Skip to: 17205 + /* 11976 */ MCD_OPC_Decode, + 191, + 12, + 255, + 1, // Opcode: FDIV_W + /* 11981 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 11996 + /* 11986 */ MCD_OPC_CheckPredicate, + 30, + 94, + 20, + 0, // Skip to: 17205 + /* 11991 */ MCD_OPC_Decode, + 183, + 12, + 128, + 2, // Opcode: FDIV_D + /* 11996 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 12011 + /* 12001 */ MCD_OPC_CheckPredicate, + 30, + 79, + 20, + 0, // Skip to: 17205 + /* 12006 */ MCD_OPC_Decode, + 226, + 12, + 131, + 2, // Opcode: FMADD_W + /* 12011 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 12026 + /* 12016 */ MCD_OPC_CheckPredicate, + 30, + 64, + 20, + 0, // Skip to: 17205 + /* 12021 */ MCD_OPC_Decode, + 225, + 12, + 132, + 2, // Opcode: FMADD_D + /* 12026 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 12041 + /* 12031 */ MCD_OPC_CheckPredicate, + 30, + 49, + 20, + 0, // Skip to: 17205 + /* 12036 */ MCD_OPC_Decode, + 244, + 12, + 131, + 2, // Opcode: FMSUB_W + /* 12041 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 12056 + /* 12046 */ MCD_OPC_CheckPredicate, + 30, + 34, + 20, + 0, // Skip to: 17205 + /* 12051 */ MCD_OPC_Decode, + 243, + 12, + 132, + 2, // Opcode: FMSUB_D + /* 12056 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12071 + /* 12061 */ MCD_OPC_CheckPredicate, + 30, + 19, + 20, + 0, // Skip to: 17205 + /* 12066 */ MCD_OPC_Decode, + 195, + 12, + 255, + 1, // Opcode: FEXP2_W + /* 12071 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 12086 + /* 12076 */ MCD_OPC_CheckPredicate, + 30, + 4, + 20, + 0, // Skip to: 17205 + /* 12081 */ MCD_OPC_Decode, + 194, + 12, + 128, + 2, // Opcode: FEXP2_D + /* 12086 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 12101 + /* 12091 */ MCD_OPC_CheckPredicate, + 30, + 245, + 19, + 0, // Skip to: 17205 + /* 12096 */ MCD_OPC_Decode, + 192, + 12, + 167, + 2, // Opcode: FEXDO_H + /* 12101 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 12116 + /* 12106 */ MCD_OPC_CheckPredicate, + 30, + 230, + 19, + 0, // Skip to: 17205 + /* 12111 */ MCD_OPC_Decode, + 193, + 12, + 168, + 2, // Opcode: FEXDO_W + /* 12116 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 12131 + /* 12121 */ MCD_OPC_CheckPredicate, + 30, + 215, + 19, + 0, // Skip to: 17205 + /* 12126 */ MCD_OPC_Decode, + 185, + 13, + 167, + 2, // Opcode: FTQ_H + /* 12131 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 12146 + /* 12136 */ MCD_OPC_CheckPredicate, + 30, + 200, + 19, + 0, // Skip to: 17205 + /* 12141 */ MCD_OPC_Decode, + 186, + 13, + 168, + 2, // Opcode: FTQ_W + /* 12146 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 12161 + /* 12151 */ MCD_OPC_CheckPredicate, + 30, + 185, + 19, + 0, // Skip to: 17205 + /* 12156 */ MCD_OPC_Decode, + 234, + 12, + 255, + 1, // Opcode: FMIN_W + /* 12161 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 12176 + /* 12166 */ MCD_OPC_CheckPredicate, + 30, + 170, + 19, + 0, // Skip to: 17205 + /* 12171 */ MCD_OPC_Decode, + 233, + 12, + 128, + 2, // Opcode: FMIN_D + /* 12176 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 12191 + /* 12181 */ MCD_OPC_CheckPredicate, + 30, + 155, + 19, + 0, // Skip to: 17205 + /* 12186 */ MCD_OPC_Decode, + 232, + 12, + 255, + 1, // Opcode: FMIN_A_W + /* 12191 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 12206 + /* 12196 */ MCD_OPC_CheckPredicate, + 30, + 140, + 19, + 0, // Skip to: 17205 + /* 12201 */ MCD_OPC_Decode, + 231, + 12, + 128, + 2, // Opcode: FMIN_A_D + /* 12206 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 12221 + /* 12211 */ MCD_OPC_CheckPredicate, + 30, + 125, + 19, + 0, // Skip to: 17205 + /* 12216 */ MCD_OPC_Decode, + 230, + 12, + 255, + 1, // Opcode: FMAX_W + /* 12221 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 12236 + /* 12226 */ MCD_OPC_CheckPredicate, + 30, + 110, + 19, + 0, // Skip to: 17205 + /* 12231 */ MCD_OPC_Decode, + 229, + 12, + 128, + 2, // Opcode: FMAX_D + /* 12236 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 12251 + /* 12241 */ MCD_OPC_CheckPredicate, + 30, + 95, + 19, + 0, // Skip to: 17205 + /* 12246 */ MCD_OPC_Decode, + 228, + 12, + 255, + 1, // Opcode: FMAX_A_W + /* 12251 */ MCD_OPC_FilterValue, + 31, + 85, + 19, + 0, // Skip to: 17205 + /* 12256 */ MCD_OPC_CheckPredicate, + 30, + 80, + 19, + 0, // Skip to: 17205 + /* 12261 */ MCD_OPC_Decode, + 227, + 12, + 128, + 2, // Opcode: FMAX_A_D + /* 12266 */ MCD_OPC_FilterValue, + 28, + 107, + 1, + 0, // Skip to: 12634 + /* 12271 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 12274 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12289 + /* 12279 */ MCD_OPC_CheckPredicate, + 30, + 57, + 19, + 0, // Skip to: 17205 + /* 12284 */ MCD_OPC_Decode, + 172, + 12, + 255, + 1, // Opcode: FCOR_W + /* 12289 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12304 + /* 12294 */ MCD_OPC_CheckPredicate, + 30, + 42, + 19, + 0, // Skip to: 17205 + /* 12299 */ MCD_OPC_Decode, + 171, + 12, + 128, + 2, // Opcode: FCOR_D + /* 12304 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 12319 + /* 12309 */ MCD_OPC_CheckPredicate, + 30, + 27, + 19, + 0, // Skip to: 17205 + /* 12314 */ MCD_OPC_Decode, + 180, + 12, + 255, + 1, // Opcode: FCUNE_W + /* 12319 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 12334 + /* 12324 */ MCD_OPC_CheckPredicate, + 30, + 12, + 19, + 0, // Skip to: 17205 + /* 12329 */ MCD_OPC_Decode, + 179, + 12, + 128, + 2, // Opcode: FCUNE_D + /* 12334 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 12349 + /* 12339 */ MCD_OPC_CheckPredicate, + 30, + 253, + 18, + 0, // Skip to: 17205 + /* 12344 */ MCD_OPC_Decode, + 170, + 12, + 255, + 1, // Opcode: FCNE_W + /* 12349 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 12364 + /* 12354 */ MCD_OPC_CheckPredicate, + 30, + 238, + 18, + 0, // Skip to: 17205 + /* 12359 */ MCD_OPC_Decode, + 169, + 12, + 128, + 2, // Opcode: FCNE_D + /* 12364 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 12379 + /* 12369 */ MCD_OPC_CheckPredicate, + 30, + 223, + 18, + 0, // Skip to: 17205 + /* 12374 */ MCD_OPC_Decode, + 183, + 17, + 254, + 1, // Opcode: MUL_Q_H + /* 12379 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 12394 + /* 12384 */ MCD_OPC_CheckPredicate, + 30, + 208, + 18, + 0, // Skip to: 17205 + /* 12389 */ MCD_OPC_Decode, + 184, + 17, + 255, + 1, // Opcode: MUL_Q_W + /* 12394 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 12409 + /* 12399 */ MCD_OPC_CheckPredicate, + 30, + 193, + 18, + 0, // Skip to: 17205 + /* 12404 */ MCD_OPC_Decode, + 172, + 15, + 130, + 2, // Opcode: MADD_Q_H + /* 12409 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 12424 + /* 12414 */ MCD_OPC_CheckPredicate, + 30, + 178, + 18, + 0, // Skip to: 17205 + /* 12419 */ MCD_OPC_Decode, + 173, + 15, + 131, + 2, // Opcode: MADD_Q_W + /* 12424 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 12439 + /* 12429 */ MCD_OPC_CheckPredicate, + 30, + 163, + 18, + 0, // Skip to: 17205 + /* 12434 */ MCD_OPC_Decode, + 223, + 16, + 130, + 2, // Opcode: MSUB_Q_H + /* 12439 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 12454 + /* 12444 */ MCD_OPC_CheckPredicate, + 30, + 148, + 18, + 0, // Skip to: 17205 + /* 12449 */ MCD_OPC_Decode, + 224, + 16, + 131, + 2, // Opcode: MSUB_Q_W + /* 12454 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 12469 + /* 12459 */ MCD_OPC_CheckPredicate, + 30, + 133, + 18, + 0, // Skip to: 17205 + /* 12464 */ MCD_OPC_Decode, + 152, + 13, + 255, + 1, // Opcode: FSOR_W + /* 12469 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 12484 + /* 12474 */ MCD_OPC_CheckPredicate, + 30, + 118, + 18, + 0, // Skip to: 17205 + /* 12479 */ MCD_OPC_Decode, + 151, + 13, + 128, + 2, // Opcode: FSOR_D + /* 12484 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 12499 + /* 12489 */ MCD_OPC_CheckPredicate, + 30, + 103, + 18, + 0, // Skip to: 17205 + /* 12494 */ MCD_OPC_Decode, + 178, + 13, + 255, + 1, // Opcode: FSUNE_W + /* 12499 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 12514 + /* 12504 */ MCD_OPC_CheckPredicate, + 30, + 88, + 18, + 0, // Skip to: 17205 + /* 12509 */ MCD_OPC_Decode, + 177, + 13, + 128, + 2, // Opcode: FSUNE_D + /* 12514 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 12529 + /* 12519 */ MCD_OPC_CheckPredicate, + 30, + 73, + 18, + 0, // Skip to: 17205 + /* 12524 */ MCD_OPC_Decode, + 150, + 13, + 255, + 1, // Opcode: FSNE_W + /* 12529 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 12544 + /* 12534 */ MCD_OPC_CheckPredicate, + 30, + 58, + 18, + 0, // Skip to: 17205 + /* 12539 */ MCD_OPC_Decode, + 149, + 13, + 128, + 2, // Opcode: FSNE_D + /* 12544 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 12559 + /* 12549 */ MCD_OPC_CheckPredicate, + 30, + 43, + 18, + 0, // Skip to: 17205 + /* 12554 */ MCD_OPC_Decode, + 159, + 17, + 254, + 1, // Opcode: MULR_Q_H + /* 12559 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 12574 + /* 12564 */ MCD_OPC_CheckPredicate, + 30, + 28, + 18, + 0, // Skip to: 17205 + /* 12569 */ MCD_OPC_Decode, + 160, + 17, + 255, + 1, // Opcode: MULR_Q_W + /* 12574 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 12589 + /* 12579 */ MCD_OPC_CheckPredicate, + 30, + 13, + 18, + 0, // Skip to: 17205 + /* 12584 */ MCD_OPC_Decode, + 156, + 15, + 130, + 2, // Opcode: MADDR_Q_H + /* 12589 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 12604 + /* 12594 */ MCD_OPC_CheckPredicate, + 30, + 254, + 17, + 0, // Skip to: 17205 + /* 12599 */ MCD_OPC_Decode, + 157, + 15, + 131, + 2, // Opcode: MADDR_Q_W + /* 12604 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 12619 + /* 12609 */ MCD_OPC_CheckPredicate, + 30, + 239, + 17, + 0, // Skip to: 17205 + /* 12614 */ MCD_OPC_Decode, + 207, + 16, + 130, + 2, // Opcode: MSUBR_Q_H + /* 12619 */ MCD_OPC_FilterValue, + 29, + 229, + 17, + 0, // Skip to: 17205 + /* 12624 */ MCD_OPC_CheckPredicate, + 30, + 224, + 17, + 0, // Skip to: 17205 + /* 12629 */ MCD_OPC_Decode, + 208, + 16, + 131, + 2, // Opcode: MSUBR_Q_W + /* 12634 */ MCD_OPC_FilterValue, + 30, + 76, + 3, + 0, // Skip to: 13483 + /* 12639 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 12642 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 12657 + /* 12647 */ MCD_OPC_CheckPredicate, + 30, + 201, + 17, + 0, // Skip to: 17205 + /* 12652 */ MCD_OPC_Decode, + 155, + 6, + 253, + 1, // Opcode: AND_V + /* 12657 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 12672 + /* 12662 */ MCD_OPC_CheckPredicate, + 30, + 186, + 17, + 0, // Skip to: 17205 + /* 12667 */ MCD_OPC_Decode, + 228, + 17, + 253, + 1, // Opcode: OR_V + /* 12672 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12687 + /* 12677 */ MCD_OPC_CheckPredicate, + 30, + 171, + 17, + 0, // Skip to: 17205 + /* 12682 */ MCD_OPC_Decode, + 215, + 17, + 253, + 1, // Opcode: NOR_V + /* 12687 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12702 + /* 12692 */ MCD_OPC_CheckPredicate, + 30, + 156, + 17, + 0, // Skip to: 17205 + /* 12697 */ MCD_OPC_Decode, + 153, + 22, + 253, + 1, // Opcode: XOR_V + /* 12702 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 12717 + /* 12707 */ MCD_OPC_CheckPredicate, + 30, + 141, + 17, + 0, // Skip to: 17205 + /* 12712 */ MCD_OPC_Decode, + 208, + 7, + 129, + 2, // Opcode: BMNZ_V + /* 12717 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 12732 + /* 12722 */ MCD_OPC_CheckPredicate, + 30, + 126, + 17, + 0, // Skip to: 17205 + /* 12727 */ MCD_OPC_Decode, + 210, + 7, + 129, + 2, // Opcode: BMZ_V + /* 12732 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 12747 + /* 12737 */ MCD_OPC_CheckPredicate, + 30, + 111, + 17, + 0, // Skip to: 17205 + /* 12742 */ MCD_OPC_Decode, + 252, + 7, + 129, + 2, // Opcode: BSEL_V + /* 12747 */ MCD_OPC_FilterValue, + 24, + 243, + 0, + 0, // Skip to: 12995 + /* 12752 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 12755 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 12770 + /* 12760 */ MCD_OPC_CheckPredicate, + 30, + 88, + 17, + 0, // Skip to: 17205 + /* 12765 */ MCD_OPC_Decode, + 208, + 12, + 169, + 2, // Opcode: FILL_B + /* 12770 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 12785 + /* 12775 */ MCD_OPC_CheckPredicate, + 30, + 73, + 17, + 0, // Skip to: 17205 + /* 12780 */ MCD_OPC_Decode, + 210, + 12, + 170, + 2, // Opcode: FILL_H + /* 12785 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12800 + /* 12790 */ MCD_OPC_CheckPredicate, + 30, + 58, + 17, + 0, // Skip to: 17205 + /* 12795 */ MCD_OPC_Decode, + 211, + 12, + 171, + 2, // Opcode: FILL_W + /* 12800 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12815 + /* 12805 */ MCD_OPC_CheckPredicate, + 38, + 43, + 17, + 0, // Skip to: 17205 + /* 12810 */ MCD_OPC_Decode, + 209, + 12, + 172, + 2, // Opcode: FILL_D + /* 12815 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 12830 + /* 12820 */ MCD_OPC_CheckPredicate, + 30, + 28, + 17, + 0, // Skip to: 17205 + /* 12825 */ MCD_OPC_Decode, + 246, + 17, + 161, + 2, // Opcode: PCNT_B + /* 12830 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 12845 + /* 12835 */ MCD_OPC_CheckPredicate, + 30, + 13, + 17, + 0, // Skip to: 17205 + /* 12840 */ MCD_OPC_Decode, + 248, + 17, + 173, + 2, // Opcode: PCNT_H + /* 12845 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 12860 + /* 12850 */ MCD_OPC_CheckPredicate, + 30, + 254, + 16, + 0, // Skip to: 17205 + /* 12855 */ MCD_OPC_Decode, + 249, + 17, + 174, + 2, // Opcode: PCNT_W + /* 12860 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 12875 + /* 12865 */ MCD_OPC_CheckPredicate, + 30, + 239, + 16, + 0, // Skip to: 17205 + /* 12870 */ MCD_OPC_Decode, + 247, + 17, + 175, + 2, // Opcode: PCNT_D + /* 12875 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 12890 + /* 12880 */ MCD_OPC_CheckPredicate, + 30, + 224, + 16, + 0, // Skip to: 17205 + /* 12885 */ MCD_OPC_Decode, + 192, + 17, + 161, + 2, // Opcode: NLOC_B + /* 12890 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 12905 + /* 12895 */ MCD_OPC_CheckPredicate, + 30, + 209, + 16, + 0, // Skip to: 17205 + /* 12900 */ MCD_OPC_Decode, + 194, + 17, + 173, + 2, // Opcode: NLOC_H + /* 12905 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 12920 + /* 12910 */ MCD_OPC_CheckPredicate, + 30, + 194, + 16, + 0, // Skip to: 17205 + /* 12915 */ MCD_OPC_Decode, + 195, + 17, + 174, + 2, // Opcode: NLOC_W + /* 12920 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 12935 + /* 12925 */ MCD_OPC_CheckPredicate, + 30, + 179, + 16, + 0, // Skip to: 17205 + /* 12930 */ MCD_OPC_Decode, + 193, + 17, + 175, + 2, // Opcode: NLOC_D + /* 12935 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 12950 + /* 12940 */ MCD_OPC_CheckPredicate, + 30, + 164, + 16, + 0, // Skip to: 17205 + /* 12945 */ MCD_OPC_Decode, + 196, + 17, + 161, + 2, // Opcode: NLZC_B + /* 12950 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 12965 + /* 12955 */ MCD_OPC_CheckPredicate, + 30, + 149, + 16, + 0, // Skip to: 17205 + /* 12960 */ MCD_OPC_Decode, + 198, + 17, + 173, + 2, // Opcode: NLZC_H + /* 12965 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 12980 + /* 12970 */ MCD_OPC_CheckPredicate, + 30, + 134, + 16, + 0, // Skip to: 17205 + /* 12975 */ MCD_OPC_Decode, + 199, + 17, + 174, + 2, // Opcode: NLZC_W + /* 12980 */ MCD_OPC_FilterValue, + 15, + 124, + 16, + 0, // Skip to: 17205 + /* 12985 */ MCD_OPC_CheckPredicate, + 30, + 119, + 16, + 0, // Skip to: 17205 + /* 12990 */ MCD_OPC_Decode, + 197, + 17, + 175, + 2, // Opcode: NLZC_D + /* 12995 */ MCD_OPC_FilterValue, + 25, + 109, + 16, + 0, // Skip to: 17205 + /* 13000 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 13003 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13018 + /* 13008 */ MCD_OPC_CheckPredicate, + 30, + 96, + 16, + 0, // Skip to: 17205 + /* 13013 */ MCD_OPC_Decode, + 159, + 12, + 174, + 2, // Opcode: FCLASS_W + /* 13018 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13033 + /* 13023 */ MCD_OPC_CheckPredicate, + 30, + 81, + 16, + 0, // Skip to: 17205 + /* 13028 */ MCD_OPC_Decode, + 158, + 12, + 175, + 2, // Opcode: FCLASS_D + /* 13033 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13048 + /* 13038 */ MCD_OPC_CheckPredicate, + 30, + 66, + 16, + 0, // Skip to: 17205 + /* 13043 */ MCD_OPC_Decode, + 188, + 13, + 174, + 2, // Opcode: FTRUNC_S_W + /* 13048 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 13063 + /* 13053 */ MCD_OPC_CheckPredicate, + 30, + 51, + 16, + 0, // Skip to: 17205 + /* 13058 */ MCD_OPC_Decode, + 187, + 13, + 175, + 2, // Opcode: FTRUNC_S_D + /* 13063 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 13078 + /* 13068 */ MCD_OPC_CheckPredicate, + 30, + 36, + 16, + 0, // Skip to: 17205 + /* 13073 */ MCD_OPC_Decode, + 190, + 13, + 174, + 2, // Opcode: FTRUNC_U_W + /* 13078 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 13093 + /* 13083 */ MCD_OPC_CheckPredicate, + 30, + 21, + 16, + 0, // Skip to: 17205 + /* 13088 */ MCD_OPC_Decode, + 189, + 13, + 175, + 2, // Opcode: FTRUNC_U_D + /* 13093 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 13108 + /* 13098 */ MCD_OPC_CheckPredicate, + 30, + 6, + 16, + 0, // Skip to: 17205 + /* 13103 */ MCD_OPC_Decode, + 160, + 13, + 174, + 2, // Opcode: FSQRT_W + /* 13108 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 13123 + /* 13113 */ MCD_OPC_CheckPredicate, + 30, + 247, + 15, + 0, // Skip to: 17205 + /* 13118 */ MCD_OPC_Decode, + 153, + 13, + 175, + 2, // Opcode: FSQRT_D + /* 13123 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 13138 + /* 13128 */ MCD_OPC_CheckPredicate, + 30, + 232, + 15, + 0, // Skip to: 17205 + /* 13133 */ MCD_OPC_Decode, + 140, + 13, + 174, + 2, // Opcode: FRSQRT_W + /* 13138 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 13153 + /* 13143 */ MCD_OPC_CheckPredicate, + 30, + 217, + 15, + 0, // Skip to: 17205 + /* 13148 */ MCD_OPC_Decode, + 139, + 13, + 175, + 2, // Opcode: FRSQRT_D + /* 13153 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 13168 + /* 13158 */ MCD_OPC_CheckPredicate, + 30, + 202, + 15, + 0, // Skip to: 17205 + /* 13163 */ MCD_OPC_Decode, + 136, + 13, + 174, + 2, // Opcode: FRCP_W + /* 13168 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 13183 + /* 13173 */ MCD_OPC_CheckPredicate, + 30, + 187, + 15, + 0, // Skip to: 17205 + /* 13178 */ MCD_OPC_Decode, + 135, + 13, + 175, + 2, // Opcode: FRCP_D + /* 13183 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 13198 + /* 13188 */ MCD_OPC_CheckPredicate, + 30, + 172, + 15, + 0, // Skip to: 17205 + /* 13193 */ MCD_OPC_Decode, + 138, + 13, + 174, + 2, // Opcode: FRINT_W + /* 13198 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 13213 + /* 13203 */ MCD_OPC_CheckPredicate, + 30, + 157, + 15, + 0, // Skip to: 17205 + /* 13208 */ MCD_OPC_Decode, + 137, + 13, + 175, + 2, // Opcode: FRINT_D + /* 13213 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 13228 + /* 13218 */ MCD_OPC_CheckPredicate, + 30, + 142, + 15, + 0, // Skip to: 17205 + /* 13223 */ MCD_OPC_Decode, + 213, + 12, + 174, + 2, // Opcode: FLOG2_W + /* 13228 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 13243 + /* 13233 */ MCD_OPC_CheckPredicate, + 30, + 127, + 15, + 0, // Skip to: 17205 + /* 13238 */ MCD_OPC_Decode, + 212, + 12, + 175, + 2, // Opcode: FLOG2_D + /* 13243 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 13258 + /* 13248 */ MCD_OPC_CheckPredicate, + 30, + 112, + 15, + 0, // Skip to: 17205 + /* 13253 */ MCD_OPC_Decode, + 197, + 12, + 176, + 2, // Opcode: FEXUPL_W + /* 13258 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 13273 + /* 13263 */ MCD_OPC_CheckPredicate, + 30, + 97, + 15, + 0, // Skip to: 17205 + /* 13268 */ MCD_OPC_Decode, + 196, + 12, + 177, + 2, // Opcode: FEXUPL_D + /* 13273 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 13288 + /* 13278 */ MCD_OPC_CheckPredicate, + 30, + 82, + 15, + 0, // Skip to: 17205 + /* 13283 */ MCD_OPC_Decode, + 199, + 12, + 176, + 2, // Opcode: FEXUPR_W + /* 13288 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 13303 + /* 13293 */ MCD_OPC_CheckPredicate, + 30, + 67, + 15, + 0, // Skip to: 17205 + /* 13298 */ MCD_OPC_Decode, + 198, + 12, + 177, + 2, // Opcode: FEXUPR_D + /* 13303 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 13318 + /* 13308 */ MCD_OPC_CheckPredicate, + 30, + 52, + 15, + 0, // Skip to: 17205 + /* 13313 */ MCD_OPC_Decode, + 205, + 12, + 176, + 2, // Opcode: FFQL_W + /* 13318 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 13333 + /* 13323 */ MCD_OPC_CheckPredicate, + 30, + 37, + 15, + 0, // Skip to: 17205 + /* 13328 */ MCD_OPC_Decode, + 204, + 12, + 177, + 2, // Opcode: FFQL_D + /* 13333 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 13348 + /* 13338 */ MCD_OPC_CheckPredicate, + 30, + 22, + 15, + 0, // Skip to: 17205 + /* 13343 */ MCD_OPC_Decode, + 207, + 12, + 176, + 2, // Opcode: FFQR_W + /* 13348 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 13363 + /* 13353 */ MCD_OPC_CheckPredicate, + 30, + 7, + 15, + 0, // Skip to: 17205 + /* 13358 */ MCD_OPC_Decode, + 206, + 12, + 177, + 2, // Opcode: FFQR_D + /* 13363 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 13378 + /* 13368 */ MCD_OPC_CheckPredicate, + 30, + 248, + 14, + 0, // Skip to: 17205 + /* 13373 */ MCD_OPC_Decode, + 182, + 13, + 174, + 2, // Opcode: FTINT_S_W + /* 13378 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 13393 + /* 13383 */ MCD_OPC_CheckPredicate, + 30, + 233, + 14, + 0, // Skip to: 17205 + /* 13388 */ MCD_OPC_Decode, + 181, + 13, + 175, + 2, // Opcode: FTINT_S_D + /* 13393 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 13408 + /* 13398 */ MCD_OPC_CheckPredicate, + 30, + 218, + 14, + 0, // Skip to: 17205 + /* 13403 */ MCD_OPC_Decode, + 184, + 13, + 174, + 2, // Opcode: FTINT_U_W + /* 13408 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 13423 + /* 13413 */ MCD_OPC_CheckPredicate, + 30, + 203, + 14, + 0, // Skip to: 17205 + /* 13418 */ MCD_OPC_Decode, + 183, + 13, + 175, + 2, // Opcode: FTINT_U_D + /* 13423 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 13438 + /* 13428 */ MCD_OPC_CheckPredicate, + 30, + 188, + 14, + 0, // Skip to: 17205 + /* 13433 */ MCD_OPC_Decode, + 201, + 12, + 174, + 2, // Opcode: FFINT_S_W + /* 13438 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 13453 + /* 13443 */ MCD_OPC_CheckPredicate, + 30, + 173, + 14, + 0, // Skip to: 17205 + /* 13448 */ MCD_OPC_Decode, + 200, + 12, + 175, + 2, // Opcode: FFINT_S_D + /* 13453 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 13468 + /* 13458 */ MCD_OPC_CheckPredicate, + 30, + 158, + 14, + 0, // Skip to: 17205 + /* 13463 */ MCD_OPC_Decode, + 203, + 12, + 174, + 2, // Opcode: FFINT_U_W + /* 13468 */ MCD_OPC_FilterValue, + 31, + 148, + 14, + 0, // Skip to: 17205 + /* 13473 */ MCD_OPC_CheckPredicate, + 30, + 143, + 14, + 0, // Skip to: 17205 + /* 13478 */ MCD_OPC_Decode, + 202, + 12, + 175, + 2, // Opcode: FFINT_U_D + /* 13483 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 13498 + /* 13488 */ MCD_OPC_CheckPredicate, + 30, + 128, + 14, + 0, // Skip to: 17205 + /* 13493 */ MCD_OPC_Decode, + 185, + 14, + 178, + 2, // Opcode: LD_B + /* 13498 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 13513 + /* 13503 */ MCD_OPC_CheckPredicate, + 30, + 113, + 14, + 0, // Skip to: 17205 + /* 13508 */ MCD_OPC_Decode, + 187, + 14, + 178, + 2, // Opcode: LD_H + /* 13513 */ MCD_OPC_FilterValue, + 34, + 10, + 0, + 0, // Skip to: 13528 + /* 13518 */ MCD_OPC_CheckPredicate, + 30, + 98, + 14, + 0, // Skip to: 17205 + /* 13523 */ MCD_OPC_Decode, + 188, + 14, + 178, + 2, // Opcode: LD_W + /* 13528 */ MCD_OPC_FilterValue, + 35, + 10, + 0, + 0, // Skip to: 13543 + /* 13533 */ MCD_OPC_CheckPredicate, + 30, + 83, + 14, + 0, // Skip to: 17205 + /* 13538 */ MCD_OPC_Decode, + 186, + 14, + 178, + 2, // Opcode: LD_D + /* 13543 */ MCD_OPC_FilterValue, + 36, + 10, + 0, + 0, // Skip to: 13558 + /* 13548 */ MCD_OPC_CheckPredicate, + 30, + 68, + 14, + 0, // Skip to: 17205 + /* 13553 */ MCD_OPC_Decode, + 196, + 20, + 178, + 2, // Opcode: ST_B + /* 13558 */ MCD_OPC_FilterValue, + 37, + 10, + 0, + 0, // Skip to: 13573 + /* 13563 */ MCD_OPC_CheckPredicate, + 30, + 53, + 14, + 0, // Skip to: 17205 + /* 13568 */ MCD_OPC_Decode, + 198, + 20, + 178, + 2, // Opcode: ST_H + /* 13573 */ MCD_OPC_FilterValue, + 38, + 10, + 0, + 0, // Skip to: 13588 + /* 13578 */ MCD_OPC_CheckPredicate, + 30, + 38, + 14, + 0, // Skip to: 17205 + /* 13583 */ MCD_OPC_Decode, + 199, + 20, + 178, + 2, // Opcode: ST_W + /* 13588 */ MCD_OPC_FilterValue, + 39, + 28, + 14, + 0, // Skip to: 17205 + /* 13593 */ MCD_OPC_CheckPredicate, + 30, + 23, + 14, + 0, // Skip to: 17205 + /* 13598 */ MCD_OPC_Decode, + 197, + 20, + 178, + 2, // Opcode: ST_D + /* 13603 */ MCD_OPC_FilterValue, + 31, + 165, + 12, + 0, // Skip to: 16845 + /* 13608 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 13611 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13626 + /* 13616 */ MCD_OPC_CheckPredicate, + 28, + 0, + 14, + 0, // Skip to: 17205 + /* 13621 */ MCD_OPC_Decode, + 237, + 11, + 179, + 2, // Opcode: EXT + /* 13626 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 13641 + /* 13631 */ MCD_OPC_CheckPredicate, + 28, + 241, + 13, + 0, // Skip to: 17205 + /* 13636 */ MCD_OPC_Decode, + 225, + 13, + 180, + 2, // Opcode: INS + /* 13641 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 13663 + /* 13646 */ MCD_OPC_CheckPredicate, + 42, + 226, + 13, + 0, // Skip to: 17205 + /* 13651 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 219, + 13, + 0, // Skip to: 17205 + /* 13658 */ MCD_OPC_Decode, + 134, + 13, + 181, + 2, // Opcode: FORK + /* 13663 */ MCD_OPC_FilterValue, + 9, + 23, + 0, + 0, // Skip to: 13691 + /* 13668 */ MCD_OPC_CheckPredicate, + 42, + 204, + 13, + 0, // Skip to: 17205 + /* 13673 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 197, + 13, + 0, // Skip to: 17205 + /* 13680 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 190, + 13, + 0, // Skip to: 17205 + /* 13687 */ MCD_OPC_Decode, + 158, + 22, + 14, // Opcode: YIELD + /* 13691 */ MCD_OPC_FilterValue, + 10, + 48, + 0, + 0, // Skip to: 13744 + /* 13696 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 13699 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13714 + /* 13704 */ MCD_OPC_CheckPredicate, + 37, + 168, + 13, + 0, // Skip to: 17205 + /* 13709 */ MCD_OPC_Decode, + 132, + 15, + 182, + 2, // Opcode: LWX + /* 13714 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 13729 + /* 13719 */ MCD_OPC_CheckPredicate, + 37, + 153, + 13, + 0, // Skip to: 17205 + /* 13724 */ MCD_OPC_Decode, + 197, + 14, + 182, + 2, // Opcode: LHX + /* 13729 */ MCD_OPC_FilterValue, + 6, + 143, + 13, + 0, // Skip to: 17205 + /* 13734 */ MCD_OPC_CheckPredicate, + 37, + 138, + 13, + 0, // Skip to: 17205 + /* 13739 */ MCD_OPC_Decode, + 157, + 14, + 182, + 2, // Opcode: LBUX + /* 13744 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 13766 + /* 13749 */ MCD_OPC_CheckPredicate, + 37, + 123, + 13, + 0, // Skip to: 17205 + /* 13754 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 116, + 13, + 0, // Skip to: 17205 + /* 13761 */ MCD_OPC_Decode, + 230, + 13, + 183, + 2, // Opcode: INSV + /* 13766 */ MCD_OPC_FilterValue, + 16, + 109, + 1, + 0, // Skip to: 14136 + /* 13771 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 13774 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13789 + /* 13779 */ MCD_OPC_CheckPredicate, + 37, + 93, + 13, + 0, // Skip to: 17205 + /* 13784 */ MCD_OPC_Decode, + 241, + 5, + 184, + 2, // Opcode: ADDU_QB + /* 13789 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13804 + /* 13794 */ MCD_OPC_CheckPredicate, + 37, + 78, + 13, + 0, // Skip to: 17205 + /* 13799 */ MCD_OPC_Decode, + 240, + 20, + 184, + 2, // Opcode: SUBU_QB + /* 13804 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 13819 + /* 13809 */ MCD_OPC_CheckPredicate, + 37, + 63, + 13, + 0, // Skip to: 17205 + /* 13814 */ MCD_OPC_Decode, + 245, + 5, + 184, + 2, // Opcode: ADDU_S_QB + /* 13819 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 13834 + /* 13824 */ MCD_OPC_CheckPredicate, + 37, + 48, + 13, + 0, // Skip to: 17205 + /* 13829 */ MCD_OPC_Decode, + 244, + 20, + 184, + 2, // Opcode: SUBU_S_QB + /* 13834 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 13849 + /* 13839 */ MCD_OPC_CheckPredicate, + 37, + 33, + 13, + 0, // Skip to: 17205 + /* 13844 */ MCD_OPC_Decode, + 146, + 17, + 184, + 2, // Opcode: MULEU_S_PH_QBL + /* 13849 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 13864 + /* 13854 */ MCD_OPC_CheckPredicate, + 37, + 18, + 13, + 0, // Skip to: 17205 + /* 13859 */ MCD_OPC_Decode, + 148, + 17, + 184, + 2, // Opcode: MULEU_S_PH_QBR + /* 13864 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 13879 + /* 13869 */ MCD_OPC_CheckPredicate, + 69, + 3, + 13, + 0, // Skip to: 17205 + /* 13874 */ MCD_OPC_Decode, + 239, + 5, + 184, + 2, // Opcode: ADDU_PH + /* 13879 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 13894 + /* 13884 */ MCD_OPC_CheckPredicate, + 69, + 244, + 12, + 0, // Skip to: 17205 + /* 13889 */ MCD_OPC_Decode, + 238, + 20, + 184, + 2, // Opcode: SUBU_PH + /* 13894 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 13909 + /* 13899 */ MCD_OPC_CheckPredicate, + 37, + 229, + 12, + 0, // Skip to: 17205 + /* 13904 */ MCD_OPC_Decode, + 211, + 5, + 184, + 2, // Opcode: ADDQ_PH + /* 13909 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 13924 + /* 13914 */ MCD_OPC_CheckPredicate, + 37, + 214, + 12, + 0, // Skip to: 17205 + /* 13919 */ MCD_OPC_Decode, + 209, + 20, + 184, + 2, // Opcode: SUBQ_PH + /* 13924 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 13939 + /* 13929 */ MCD_OPC_CheckPredicate, + 69, + 199, + 12, + 0, // Skip to: 17205 + /* 13934 */ MCD_OPC_Decode, + 243, + 5, + 184, + 2, // Opcode: ADDU_S_PH + /* 13939 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 13954 + /* 13944 */ MCD_OPC_CheckPredicate, + 69, + 184, + 12, + 0, // Skip to: 17205 + /* 13949 */ MCD_OPC_Decode, + 242, + 20, + 184, + 2, // Opcode: SUBU_S_PH + /* 13954 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 13969 + /* 13959 */ MCD_OPC_CheckPredicate, + 37, + 169, + 12, + 0, // Skip to: 17205 + /* 13964 */ MCD_OPC_Decode, + 213, + 5, + 184, + 2, // Opcode: ADDQ_S_PH + /* 13969 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 13984 + /* 13974 */ MCD_OPC_CheckPredicate, + 37, + 154, + 12, + 0, // Skip to: 17205 + /* 13979 */ MCD_OPC_Decode, + 211, + 20, + 184, + 2, // Opcode: SUBQ_S_PH + /* 13984 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 13998 + /* 13989 */ MCD_OPC_CheckPredicate, + 37, + 139, + 12, + 0, // Skip to: 17205 + /* 13994 */ MCD_OPC_Decode, + 218, + 5, + 50, // Opcode: ADDSC + /* 13998 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 14012 + /* 14003 */ MCD_OPC_CheckPredicate, + 37, + 125, + 12, + 0, // Skip to: 17205 + /* 14008 */ MCD_OPC_Decode, + 255, + 5, + 50, // Opcode: ADDWC + /* 14012 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 14026 + /* 14017 */ MCD_OPC_CheckPredicate, + 37, + 111, + 12, + 0, // Skip to: 17205 + /* 14022 */ MCD_OPC_Decode, + 144, + 16, + 50, // Opcode: MODSUB + /* 14026 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 14048 + /* 14031 */ MCD_OPC_CheckPredicate, + 37, + 97, + 12, + 0, // Skip to: 17205 + /* 14036 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 90, + 12, + 0, // Skip to: 17205 + /* 14043 */ MCD_OPC_Decode, + 174, + 18, + 185, + 2, // Opcode: RADDU_W_QB + /* 14048 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 14062 + /* 14053 */ MCD_OPC_CheckPredicate, + 37, + 75, + 12, + 0, // Skip to: 17205 + /* 14058 */ MCD_OPC_Decode, + 215, + 5, + 50, // Opcode: ADDQ_S_W + /* 14062 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 14076 + /* 14067 */ MCD_OPC_CheckPredicate, + 37, + 61, + 12, + 0, // Skip to: 17205 + /* 14072 */ MCD_OPC_Decode, + 213, + 20, + 50, // Opcode: SUBQ_S_W + /* 14076 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 14091 + /* 14081 */ MCD_OPC_CheckPredicate, + 37, + 47, + 12, + 0, // Skip to: 17205 + /* 14086 */ MCD_OPC_Decode, + 142, + 17, + 186, + 2, // Opcode: MULEQ_S_W_PHL + /* 14091 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 14106 + /* 14096 */ MCD_OPC_CheckPredicate, + 37, + 32, + 12, + 0, // Skip to: 17205 + /* 14101 */ MCD_OPC_Decode, + 144, + 17, + 186, + 2, // Opcode: MULEQ_S_W_PHR + /* 14106 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 14121 + /* 14111 */ MCD_OPC_CheckPredicate, + 69, + 17, + 12, + 0, // Skip to: 17205 + /* 14116 */ MCD_OPC_Decode, + 154, + 17, + 184, + 2, // Opcode: MULQ_S_PH + /* 14121 */ MCD_OPC_FilterValue, + 31, + 7, + 12, + 0, // Skip to: 17205 + /* 14126 */ MCD_OPC_CheckPredicate, + 37, + 2, + 12, + 0, // Skip to: 17205 + /* 14131 */ MCD_OPC_Decode, + 150, + 17, + 184, + 2, // Opcode: MULQ_RS_PH + /* 14136 */ MCD_OPC_FilterValue, + 17, + 113, + 1, + 0, // Skip to: 14510 + /* 14141 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 14144 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 14165 + /* 14149 */ MCD_OPC_CheckPredicate, + 37, + 235, + 11, + 0, // Skip to: 17205 + /* 14154 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 228, + 11, + 0, // Skip to: 17205 + /* 14161 */ MCD_OPC_Decode, + 238, + 8, + 68, // Opcode: CMPU_EQ_QB + /* 14165 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 14186 + /* 14170 */ MCD_OPC_CheckPredicate, + 37, + 214, + 11, + 0, // Skip to: 17205 + /* 14175 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 207, + 11, + 0, // Skip to: 17205 + /* 14182 */ MCD_OPC_Decode, + 242, + 8, + 68, // Opcode: CMPU_LT_QB + /* 14186 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 14207 + /* 14191 */ MCD_OPC_CheckPredicate, + 37, + 193, + 11, + 0, // Skip to: 17205 + /* 14196 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 186, + 11, + 0, // Skip to: 17205 + /* 14203 */ MCD_OPC_Decode, + 240, + 8, + 68, // Opcode: CMPU_LE_QB + /* 14207 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 14222 + /* 14212 */ MCD_OPC_CheckPredicate, + 37, + 172, + 11, + 0, // Skip to: 17205 + /* 14217 */ MCD_OPC_Decode, + 252, + 17, + 184, + 2, // Opcode: PICK_QB + /* 14222 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 14237 + /* 14227 */ MCD_OPC_CheckPredicate, + 37, + 157, + 11, + 0, // Skip to: 17205 + /* 14232 */ MCD_OPC_Decode, + 232, + 8, + 186, + 2, // Opcode: CMPGU_EQ_QB + /* 14237 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 14252 + /* 14242 */ MCD_OPC_CheckPredicate, + 37, + 142, + 11, + 0, // Skip to: 17205 + /* 14247 */ MCD_OPC_Decode, + 236, + 8, + 186, + 2, // Opcode: CMPGU_LT_QB + /* 14252 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 14267 + /* 14257 */ MCD_OPC_CheckPredicate, + 37, + 127, + 11, + 0, // Skip to: 17205 + /* 14262 */ MCD_OPC_Decode, + 234, + 8, + 186, + 2, // Opcode: CMPGU_LE_QB + /* 14267 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 14288 + /* 14272 */ MCD_OPC_CheckPredicate, + 37, + 112, + 11, + 0, // Skip to: 17205 + /* 14277 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 105, + 11, + 0, // Skip to: 17205 + /* 14284 */ MCD_OPC_Decode, + 248, + 8, + 68, // Opcode: CMP_EQ_PH + /* 14288 */ MCD_OPC_FilterValue, + 9, + 16, + 0, + 0, // Skip to: 14309 + /* 14293 */ MCD_OPC_CheckPredicate, + 37, + 91, + 11, + 0, // Skip to: 17205 + /* 14298 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 84, + 11, + 0, // Skip to: 17205 + /* 14305 */ MCD_OPC_Decode, + 134, + 9, + 68, // Opcode: CMP_LT_PH + /* 14309 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 14330 + /* 14314 */ MCD_OPC_CheckPredicate, + 37, + 70, + 11, + 0, // Skip to: 17205 + /* 14319 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 63, + 11, + 0, // Skip to: 17205 + /* 14326 */ MCD_OPC_Decode, + 128, + 9, + 68, // Opcode: CMP_LE_PH + /* 14330 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 14345 + /* 14335 */ MCD_OPC_CheckPredicate, + 37, + 49, + 11, + 0, // Skip to: 17205 + /* 14340 */ MCD_OPC_Decode, + 250, + 17, + 184, + 2, // Opcode: PICK_PH + /* 14345 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 14360 + /* 14350 */ MCD_OPC_CheckPredicate, + 37, + 34, + 11, + 0, // Skip to: 17205 + /* 14355 */ MCD_OPC_Decode, + 153, + 18, + 184, + 2, // Opcode: PRECRQ_QB_PH + /* 14360 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 14375 + /* 14365 */ MCD_OPC_CheckPredicate, + 69, + 19, + 11, + 0, // Skip to: 17205 + /* 14370 */ MCD_OPC_Decode, + 157, + 18, + 184, + 2, // Opcode: PRECR_QB_PH + /* 14375 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 14390 + /* 14380 */ MCD_OPC_CheckPredicate, + 37, + 4, + 11, + 0, // Skip to: 17205 + /* 14385 */ MCD_OPC_Decode, + 233, + 17, + 184, + 2, // Opcode: PACKRL_PH + /* 14390 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 14405 + /* 14395 */ MCD_OPC_CheckPredicate, + 37, + 245, + 10, + 0, // Skip to: 17205 + /* 14400 */ MCD_OPC_Decode, + 149, + 18, + 184, + 2, // Opcode: PRECRQU_S_QB_PH + /* 14405 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 14420 + /* 14410 */ MCD_OPC_CheckPredicate, + 37, + 230, + 10, + 0, // Skip to: 17205 + /* 14415 */ MCD_OPC_Decode, + 151, + 18, + 187, + 2, // Opcode: PRECRQ_PH_W + /* 14420 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 14435 + /* 14425 */ MCD_OPC_CheckPredicate, + 37, + 215, + 10, + 0, // Skip to: 17205 + /* 14430 */ MCD_OPC_Decode, + 155, + 18, + 187, + 2, // Opcode: PRECRQ_RS_PH_W + /* 14435 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 14450 + /* 14440 */ MCD_OPC_CheckPredicate, + 69, + 200, + 10, + 0, // Skip to: 17205 + /* 14445 */ MCD_OPC_Decode, + 226, + 8, + 186, + 2, // Opcode: CMPGDU_EQ_QB + /* 14450 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 14465 + /* 14455 */ MCD_OPC_CheckPredicate, + 69, + 185, + 10, + 0, // Skip to: 17205 + /* 14460 */ MCD_OPC_Decode, + 230, + 8, + 186, + 2, // Opcode: CMPGDU_LT_QB + /* 14465 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 14480 + /* 14470 */ MCD_OPC_CheckPredicate, + 69, + 170, + 10, + 0, // Skip to: 17205 + /* 14475 */ MCD_OPC_Decode, + 228, + 8, + 186, + 2, // Opcode: CMPGDU_LE_QB + /* 14480 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 14495 + /* 14485 */ MCD_OPC_CheckPredicate, + 69, + 155, + 10, + 0, // Skip to: 17205 + /* 14490 */ MCD_OPC_Decode, + 159, + 18, + 188, + 2, // Opcode: PRECR_SRA_PH_W + /* 14495 */ MCD_OPC_FilterValue, + 31, + 145, + 10, + 0, // Skip to: 17205 + /* 14500 */ MCD_OPC_CheckPredicate, + 69, + 140, + 10, + 0, // Skip to: 17205 + /* 14505 */ MCD_OPC_Decode, + 161, + 18, + 188, + 2, // Opcode: PRECR_SRA_R_PH_W + /* 14510 */ MCD_OPC_FilterValue, + 18, + 128, + 1, + 0, // Skip to: 14899 + /* 14515 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 14518 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 14540 + /* 14523 */ MCD_OPC_CheckPredicate, + 69, + 117, + 10, + 0, // Skip to: 17205 + /* 14528 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 110, + 10, + 0, // Skip to: 17205 + /* 14535 */ MCD_OPC_Decode, + 190, + 5, + 189, + 2, // Opcode: ABSQ_S_QB + /* 14540 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 14555 + /* 14545 */ MCD_OPC_CheckPredicate, + 37, + 95, + 10, + 0, // Skip to: 17205 + /* 14550 */ MCD_OPC_Decode, + 195, + 18, + 190, + 2, // Opcode: REPL_QB + /* 14555 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 14577 + /* 14560 */ MCD_OPC_CheckPredicate, + 37, + 80, + 10, + 0, // Skip to: 17205 + /* 14565 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 73, + 10, + 0, // Skip to: 17205 + /* 14572 */ MCD_OPC_Decode, + 191, + 18, + 191, + 2, // Opcode: REPLV_QB + /* 14577 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 14599 + /* 14582 */ MCD_OPC_CheckPredicate, + 37, + 58, + 10, + 0, // Skip to: 17205 + /* 14587 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 51, + 10, + 0, // Skip to: 17205 + /* 14594 */ MCD_OPC_Decode, + 129, + 18, + 189, + 2, // Opcode: PRECEQU_PH_QBL + /* 14599 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 14621 + /* 14604 */ MCD_OPC_CheckPredicate, + 37, + 36, + 10, + 0, // Skip to: 17205 + /* 14609 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 29, + 10, + 0, // Skip to: 17205 + /* 14616 */ MCD_OPC_Decode, + 133, + 18, + 189, + 2, // Opcode: PRECEQU_PH_QBR + /* 14621 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 14643 + /* 14626 */ MCD_OPC_CheckPredicate, + 37, + 14, + 10, + 0, // Skip to: 17205 + /* 14631 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 7, + 10, + 0, // Skip to: 17205 + /* 14638 */ MCD_OPC_Decode, + 130, + 18, + 189, + 2, // Opcode: PRECEQU_PH_QBLA + /* 14643 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 14665 + /* 14648 */ MCD_OPC_CheckPredicate, + 37, + 248, + 9, + 0, // Skip to: 17205 + /* 14653 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 241, + 9, + 0, // Skip to: 17205 + /* 14660 */ MCD_OPC_Decode, + 134, + 18, + 189, + 2, // Opcode: PRECEQU_PH_QBRA + /* 14665 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 14687 + /* 14670 */ MCD_OPC_CheckPredicate, + 37, + 226, + 9, + 0, // Skip to: 17205 + /* 14675 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 219, + 9, + 0, // Skip to: 17205 + /* 14682 */ MCD_OPC_Decode, + 188, + 5, + 189, + 2, // Opcode: ABSQ_S_PH + /* 14687 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 14701 + /* 14692 */ MCD_OPC_CheckPredicate, + 37, + 204, + 9, + 0, // Skip to: 17205 + /* 14697 */ MCD_OPC_Decode, + 193, + 18, + 85, // Opcode: REPL_PH + /* 14701 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 14723 + /* 14706 */ MCD_OPC_CheckPredicate, + 37, + 190, + 9, + 0, // Skip to: 17205 + /* 14711 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 183, + 9, + 0, // Skip to: 17205 + /* 14718 */ MCD_OPC_Decode, + 189, + 18, + 191, + 2, // Opcode: REPLV_PH + /* 14723 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 14745 + /* 14728 */ MCD_OPC_CheckPredicate, + 37, + 168, + 9, + 0, // Skip to: 17205 + /* 14733 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 161, + 9, + 0, // Skip to: 17205 + /* 14740 */ MCD_OPC_Decode, + 137, + 18, + 192, + 2, // Opcode: PRECEQ_W_PHL + /* 14745 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 14767 + /* 14750 */ MCD_OPC_CheckPredicate, + 37, + 146, + 9, + 0, // Skip to: 17205 + /* 14755 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 139, + 9, + 0, // Skip to: 17205 + /* 14762 */ MCD_OPC_Decode, + 139, + 18, + 192, + 2, // Opcode: PRECEQ_W_PHR + /* 14767 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 14789 + /* 14772 */ MCD_OPC_CheckPredicate, + 37, + 124, + 9, + 0, // Skip to: 17205 + /* 14777 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 117, + 9, + 0, // Skip to: 17205 + /* 14784 */ MCD_OPC_Decode, + 192, + 5, + 193, + 2, // Opcode: ABSQ_S_W + /* 14789 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 14811 + /* 14794 */ MCD_OPC_CheckPredicate, + 37, + 102, + 9, + 0, // Skip to: 17205 + /* 14799 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 95, + 9, + 0, // Skip to: 17205 + /* 14806 */ MCD_OPC_Decode, + 175, + 7, + 193, + 2, // Opcode: BITREV + /* 14811 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 14833 + /* 14816 */ MCD_OPC_CheckPredicate, + 37, + 80, + 9, + 0, // Skip to: 17205 + /* 14821 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 73, + 9, + 0, // Skip to: 17205 + /* 14828 */ MCD_OPC_Decode, + 141, + 18, + 189, + 2, // Opcode: PRECEU_PH_QBL + /* 14833 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 14855 + /* 14838 */ MCD_OPC_CheckPredicate, + 37, + 58, + 9, + 0, // Skip to: 17205 + /* 14843 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 51, + 9, + 0, // Skip to: 17205 + /* 14850 */ MCD_OPC_Decode, + 145, + 18, + 189, + 2, // Opcode: PRECEU_PH_QBR + /* 14855 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 14877 + /* 14860 */ MCD_OPC_CheckPredicate, + 37, + 36, + 9, + 0, // Skip to: 17205 + /* 14865 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 29, + 9, + 0, // Skip to: 17205 + /* 14872 */ MCD_OPC_Decode, + 142, + 18, + 189, + 2, // Opcode: PRECEU_PH_QBLA + /* 14877 */ MCD_OPC_FilterValue, + 31, + 19, + 9, + 0, // Skip to: 17205 + /* 14882 */ MCD_OPC_CheckPredicate, + 37, + 14, + 9, + 0, // Skip to: 17205 + /* 14887 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 7, + 9, + 0, // Skip to: 17205 + /* 14894 */ MCD_OPC_Decode, + 146, + 18, + 189, + 2, // Opcode: PRECEU_PH_QBRA + /* 14899 */ MCD_OPC_FilterValue, + 19, + 75, + 1, + 0, // Skip to: 15235 + /* 14904 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 14907 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 14922 + /* 14912 */ MCD_OPC_CheckPredicate, + 37, + 240, + 8, + 0, // Skip to: 17205 + /* 14917 */ MCD_OPC_Decode, + 194, + 19, + 194, + 2, // Opcode: SHLL_QB + /* 14922 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 14937 + /* 14927 */ MCD_OPC_CheckPredicate, + 37, + 225, + 8, + 0, // Skip to: 17205 + /* 14932 */ MCD_OPC_Decode, + 226, + 19, + 194, + 2, // Opcode: SHRL_QB + /* 14937 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 14952 + /* 14942 */ MCD_OPC_CheckPredicate, + 37, + 210, + 8, + 0, // Skip to: 17205 + /* 14947 */ MCD_OPC_Decode, + 186, + 19, + 195, + 2, // Opcode: SHLLV_QB + /* 14952 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 14967 + /* 14957 */ MCD_OPC_CheckPredicate, + 37, + 195, + 8, + 0, // Skip to: 17205 + /* 14962 */ MCD_OPC_Decode, + 222, + 19, + 195, + 2, // Opcode: SHRLV_QB + /* 14967 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 14982 + /* 14972 */ MCD_OPC_CheckPredicate, + 69, + 180, + 8, + 0, // Skip to: 17205 + /* 14977 */ MCD_OPC_Decode, + 212, + 19, + 194, + 2, // Opcode: SHRA_QB + /* 14982 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 14997 + /* 14987 */ MCD_OPC_CheckPredicate, + 69, + 165, + 8, + 0, // Skip to: 17205 + /* 14992 */ MCD_OPC_Decode, + 216, + 19, + 194, + 2, // Opcode: SHRA_R_QB + /* 14997 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 15012 + /* 15002 */ MCD_OPC_CheckPredicate, + 69, + 150, + 8, + 0, // Skip to: 17205 + /* 15007 */ MCD_OPC_Decode, + 202, + 19, + 195, + 2, // Opcode: SHRAV_QB + /* 15012 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 15027 + /* 15017 */ MCD_OPC_CheckPredicate, + 69, + 135, + 8, + 0, // Skip to: 17205 + /* 15022 */ MCD_OPC_Decode, + 206, + 19, + 195, + 2, // Opcode: SHRAV_R_QB + /* 15027 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 15042 + /* 15032 */ MCD_OPC_CheckPredicate, + 37, + 120, + 8, + 0, // Skip to: 17205 + /* 15037 */ MCD_OPC_Decode, + 192, + 19, + 194, + 2, // Opcode: SHLL_PH + /* 15042 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 15057 + /* 15047 */ MCD_OPC_CheckPredicate, + 37, + 105, + 8, + 0, // Skip to: 17205 + /* 15052 */ MCD_OPC_Decode, + 210, + 19, + 194, + 2, // Opcode: SHRA_PH + /* 15057 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 15072 + /* 15062 */ MCD_OPC_CheckPredicate, + 37, + 90, + 8, + 0, // Skip to: 17205 + /* 15067 */ MCD_OPC_Decode, + 184, + 19, + 195, + 2, // Opcode: SHLLV_PH + /* 15072 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 15087 + /* 15077 */ MCD_OPC_CheckPredicate, + 37, + 75, + 8, + 0, // Skip to: 17205 + /* 15082 */ MCD_OPC_Decode, + 200, + 19, + 195, + 2, // Opcode: SHRAV_PH + /* 15087 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 15102 + /* 15092 */ MCD_OPC_CheckPredicate, + 37, + 60, + 8, + 0, // Skip to: 17205 + /* 15097 */ MCD_OPC_Decode, + 196, + 19, + 194, + 2, // Opcode: SHLL_S_PH + /* 15102 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 15117 + /* 15107 */ MCD_OPC_CheckPredicate, + 37, + 45, + 8, + 0, // Skip to: 17205 + /* 15112 */ MCD_OPC_Decode, + 214, + 19, + 194, + 2, // Opcode: SHRA_R_PH + /* 15117 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 15132 + /* 15122 */ MCD_OPC_CheckPredicate, + 37, + 30, + 8, + 0, // Skip to: 17205 + /* 15127 */ MCD_OPC_Decode, + 188, + 19, + 195, + 2, // Opcode: SHLLV_S_PH + /* 15132 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 15147 + /* 15137 */ MCD_OPC_CheckPredicate, + 37, + 15, + 8, + 0, // Skip to: 17205 + /* 15142 */ MCD_OPC_Decode, + 204, + 19, + 195, + 2, // Opcode: SHRAV_R_PH + /* 15147 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 15162 + /* 15152 */ MCD_OPC_CheckPredicate, + 37, + 0, + 8, + 0, // Skip to: 17205 + /* 15157 */ MCD_OPC_Decode, + 198, + 19, + 196, + 2, // Opcode: SHLL_S_W + /* 15162 */ MCD_OPC_FilterValue, + 21, + 10, + 0, + 0, // Skip to: 15177 + /* 15167 */ MCD_OPC_CheckPredicate, + 37, + 241, + 7, + 0, // Skip to: 17205 + /* 15172 */ MCD_OPC_Decode, + 218, + 19, + 196, + 2, // Opcode: SHRA_R_W + /* 15177 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 15191 + /* 15182 */ MCD_OPC_CheckPredicate, + 37, + 226, + 7, + 0, // Skip to: 17205 + /* 15187 */ MCD_OPC_Decode, + 190, + 19, + 44, // Opcode: SHLLV_S_W + /* 15191 */ MCD_OPC_FilterValue, + 23, + 9, + 0, + 0, // Skip to: 15205 + /* 15196 */ MCD_OPC_CheckPredicate, + 37, + 212, + 7, + 0, // Skip to: 17205 + /* 15201 */ MCD_OPC_Decode, + 208, + 19, + 44, // Opcode: SHRAV_R_W + /* 15205 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 15220 + /* 15210 */ MCD_OPC_CheckPredicate, + 69, + 198, + 7, + 0, // Skip to: 17205 + /* 15215 */ MCD_OPC_Decode, + 224, + 19, + 194, + 2, // Opcode: SHRL_PH + /* 15220 */ MCD_OPC_FilterValue, + 27, + 188, + 7, + 0, // Skip to: 17205 + /* 15225 */ MCD_OPC_CheckPredicate, + 69, + 183, + 7, + 0, // Skip to: 17205 + /* 15230 */ MCD_OPC_Decode, + 220, + 19, + 195, + 2, // Opcode: SHRLV_PH + /* 15235 */ MCD_OPC_FilterValue, + 24, + 237, + 0, + 0, // Skip to: 15477 + /* 15240 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 15243 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 15258 + /* 15248 */ MCD_OPC_CheckPredicate, + 69, + 160, + 7, + 0, // Skip to: 17205 + /* 15253 */ MCD_OPC_Decode, + 234, + 5, + 184, + 2, // Opcode: ADDUH_QB + /* 15258 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 15273 + /* 15263 */ MCD_OPC_CheckPredicate, + 69, + 145, + 7, + 0, // Skip to: 17205 + /* 15268 */ MCD_OPC_Decode, + 233, + 20, + 184, + 2, // Opcode: SUBUH_QB + /* 15273 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 15288 + /* 15278 */ MCD_OPC_CheckPredicate, + 69, + 130, + 7, + 0, // Skip to: 17205 + /* 15283 */ MCD_OPC_Decode, + 236, + 5, + 184, + 2, // Opcode: ADDUH_R_QB + /* 15288 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 15303 + /* 15293 */ MCD_OPC_CheckPredicate, + 69, + 115, + 7, + 0, // Skip to: 17205 + /* 15298 */ MCD_OPC_Decode, + 235, + 20, + 184, + 2, // Opcode: SUBUH_R_QB + /* 15303 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 15318 + /* 15308 */ MCD_OPC_CheckPredicate, + 69, + 100, + 7, + 0, // Skip to: 17205 + /* 15313 */ MCD_OPC_Decode, + 203, + 5, + 184, + 2, // Opcode: ADDQH_PH + /* 15318 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 15333 + /* 15323 */ MCD_OPC_CheckPredicate, + 69, + 85, + 7, + 0, // Skip to: 17205 + /* 15328 */ MCD_OPC_Decode, + 201, + 20, + 184, + 2, // Opcode: SUBQH_PH + /* 15333 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 15348 + /* 15338 */ MCD_OPC_CheckPredicate, + 69, + 70, + 7, + 0, // Skip to: 17205 + /* 15343 */ MCD_OPC_Decode, + 205, + 5, + 184, + 2, // Opcode: ADDQH_R_PH + /* 15348 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 15363 + /* 15353 */ MCD_OPC_CheckPredicate, + 69, + 55, + 7, + 0, // Skip to: 17205 + /* 15358 */ MCD_OPC_Decode, + 203, + 20, + 184, + 2, // Opcode: SUBQH_R_PH + /* 15363 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 15378 + /* 15368 */ MCD_OPC_CheckPredicate, + 69, + 40, + 7, + 0, // Skip to: 17205 + /* 15373 */ MCD_OPC_Decode, + 181, + 17, + 184, + 2, // Opcode: MUL_PH + /* 15378 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 15393 + /* 15383 */ MCD_OPC_CheckPredicate, + 69, + 25, + 7, + 0, // Skip to: 17205 + /* 15388 */ MCD_OPC_Decode, + 186, + 17, + 184, + 2, // Opcode: MUL_S_PH + /* 15393 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 15407 + /* 15398 */ MCD_OPC_CheckPredicate, + 69, + 10, + 7, + 0, // Skip to: 17205 + /* 15403 */ MCD_OPC_Decode, + 209, + 5, + 50, // Opcode: ADDQH_W + /* 15407 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 15421 + /* 15412 */ MCD_OPC_CheckPredicate, + 69, + 252, + 6, + 0, // Skip to: 17205 + /* 15417 */ MCD_OPC_Decode, + 207, + 20, + 50, // Opcode: SUBQH_W + /* 15421 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 15435 + /* 15426 */ MCD_OPC_CheckPredicate, + 69, + 238, + 6, + 0, // Skip to: 17205 + /* 15431 */ MCD_OPC_Decode, + 207, + 5, + 50, // Opcode: ADDQH_R_W + /* 15435 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 15449 + /* 15440 */ MCD_OPC_CheckPredicate, + 69, + 224, + 6, + 0, // Skip to: 17205 + /* 15445 */ MCD_OPC_Decode, + 205, + 20, + 50, // Opcode: SUBQH_R_W + /* 15449 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 15463 + /* 15454 */ MCD_OPC_CheckPredicate, + 69, + 210, + 6, + 0, // Skip to: 17205 + /* 15459 */ MCD_OPC_Decode, + 156, + 17, + 50, // Opcode: MULQ_S_W + /* 15463 */ MCD_OPC_FilterValue, + 23, + 201, + 6, + 0, // Skip to: 17205 + /* 15468 */ MCD_OPC_CheckPredicate, + 69, + 196, + 6, + 0, // Skip to: 17205 + /* 15473 */ MCD_OPC_Decode, + 152, + 17, + 50, // Opcode: MULQ_RS_W + /* 15477 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 15499 + /* 15482 */ MCD_OPC_CheckPredicate, + 70, + 182, + 6, + 0, // Skip to: 17205 + /* 15487 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 175, + 6, + 0, // Skip to: 17205 + /* 15494 */ MCD_OPC_Decode, + 243, + 14, + 197, + 2, // Opcode: LWLE + /* 15499 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 15521 + /* 15504 */ MCD_OPC_CheckPredicate, + 70, + 160, + 6, + 0, // Skip to: 17205 + /* 15509 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 153, + 6, + 0, // Skip to: 17205 + /* 15516 */ MCD_OPC_Decode, + 254, + 14, + 197, + 2, // Opcode: LWRE + /* 15521 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 15543 + /* 15526 */ MCD_OPC_CheckPredicate, + 43, + 138, + 6, + 0, // Skip to: 17205 + /* 15531 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 131, + 6, + 0, // Skip to: 17205 + /* 15538 */ MCD_OPC_Decode, + 150, + 8, + 198, + 2, // Opcode: CACHEE + /* 15543 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 15565 + /* 15548 */ MCD_OPC_CheckPredicate, + 43, + 116, + 6, + 0, // Skip to: 17205 + /* 15553 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 109, + 6, + 0, // Skip to: 17205 + /* 15560 */ MCD_OPC_Decode, + 238, + 18, + 197, + 2, // Opcode: SBE + /* 15565 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 15587 + /* 15570 */ MCD_OPC_CheckPredicate, + 43, + 94, + 6, + 0, // Skip to: 17205 + /* 15575 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 87, + 6, + 0, // Skip to: 17205 + /* 15582 */ MCD_OPC_Decode, + 175, + 19, + 197, + 2, // Opcode: SHE + /* 15587 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 15609 + /* 15592 */ MCD_OPC_CheckPredicate, + 43, + 72, + 6, + 0, // Skip to: 17205 + /* 15597 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 65, + 6, + 0, // Skip to: 17205 + /* 15604 */ MCD_OPC_Decode, + 247, + 18, + 197, + 2, // Opcode: SCE + /* 15609 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 15631 + /* 15614 */ MCD_OPC_CheckPredicate, + 43, + 50, + 6, + 0, // Skip to: 17205 + /* 15619 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 43, + 6, + 0, // Skip to: 17205 + /* 15626 */ MCD_OPC_Decode, + 145, + 21, + 197, + 2, // Opcode: SWE + /* 15631 */ MCD_OPC_FilterValue, + 32, + 69, + 0, + 0, // Skip to: 15705 + /* 15636 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 15639 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 15661 + /* 15644 */ MCD_OPC_CheckPredicate, + 28, + 20, + 6, + 0, // Skip to: 17205 + /* 15649 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 13, + 6, + 0, // Skip to: 17205 + /* 15656 */ MCD_OPC_Decode, + 142, + 22, + 193, + 2, // Opcode: WSBH + /* 15661 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 15683 + /* 15666 */ MCD_OPC_CheckPredicate, + 28, + 254, + 5, + 0, // Skip to: 17205 + /* 15671 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 247, + 5, + 0, // Skip to: 17205 + /* 15678 */ MCD_OPC_Decode, + 145, + 19, + 193, + 2, // Opcode: SEB + /* 15683 */ MCD_OPC_FilterValue, + 24, + 237, + 5, + 0, // Skip to: 17205 + /* 15688 */ MCD_OPC_CheckPredicate, + 28, + 232, + 5, + 0, // Skip to: 17205 + /* 15693 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 225, + 5, + 0, // Skip to: 17205 + /* 15700 */ MCD_OPC_Decode, + 148, + 19, + 193, + 2, // Opcode: SEH + /* 15705 */ MCD_OPC_FilterValue, + 33, + 17, + 0, + 0, // Skip to: 15727 + /* 15710 */ MCD_OPC_CheckPredicate, + 70, + 210, + 5, + 0, // Skip to: 17205 + /* 15715 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 203, + 5, + 0, // Skip to: 17205 + /* 15722 */ MCD_OPC_Decode, + 149, + 21, + 197, + 2, // Opcode: SWLE + /* 15727 */ MCD_OPC_FilterValue, + 34, + 17, + 0, + 0, // Skip to: 15749 + /* 15732 */ MCD_OPC_CheckPredicate, + 70, + 188, + 5, + 0, // Skip to: 17205 + /* 15737 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 181, + 5, + 0, // Skip to: 17205 + /* 15744 */ MCD_OPC_Decode, + 158, + 21, + 197, + 2, // Opcode: SWRE + /* 15749 */ MCD_OPC_FilterValue, + 35, + 17, + 0, + 0, // Skip to: 15771 + /* 15754 */ MCD_OPC_CheckPredicate, + 43, + 166, + 5, + 0, // Skip to: 17205 + /* 15759 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 159, + 5, + 0, // Skip to: 17205 + /* 15766 */ MCD_OPC_Decode, + 164, + 18, + 198, + 2, // Opcode: PREFE + /* 15771 */ MCD_OPC_FilterValue, + 40, + 17, + 0, + 0, // Skip to: 15793 + /* 15776 */ MCD_OPC_CheckPredicate, + 43, + 144, + 5, + 0, // Skip to: 17205 + /* 15781 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 137, + 5, + 0, // Skip to: 17205 + /* 15788 */ MCD_OPC_Decode, + 164, + 14, + 197, + 2, // Opcode: LBuE + /* 15793 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 15815 + /* 15798 */ MCD_OPC_CheckPredicate, + 43, + 122, + 5, + 0, // Skip to: 17205 + /* 15803 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 115, + 5, + 0, // Skip to: 17205 + /* 15810 */ MCD_OPC_Decode, + 202, + 14, + 197, + 2, // Opcode: LHuE + /* 15815 */ MCD_OPC_FilterValue, + 44, + 17, + 0, + 0, // Skip to: 15837 + /* 15820 */ MCD_OPC_CheckPredicate, + 43, + 100, + 5, + 0, // Skip to: 17205 + /* 15825 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 93, + 5, + 0, // Skip to: 17205 + /* 15832 */ MCD_OPC_Decode, + 154, + 14, + 197, + 2, // Opcode: LBE + /* 15837 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 15859 + /* 15842 */ MCD_OPC_CheckPredicate, + 43, + 78, + 5, + 0, // Skip to: 17205 + /* 15847 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 71, + 5, + 0, // Skip to: 17205 + /* 15854 */ MCD_OPC_Decode, + 194, + 14, + 197, + 2, // Opcode: LHE + /* 15859 */ MCD_OPC_FilterValue, + 46, + 17, + 0, + 0, // Skip to: 15881 + /* 15864 */ MCD_OPC_CheckPredicate, + 43, + 56, + 5, + 0, // Skip to: 17205 + /* 15869 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 49, + 5, + 0, // Skip to: 17205 + /* 15876 */ MCD_OPC_Decode, + 212, + 14, + 197, + 2, // Opcode: LLE + /* 15881 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 15903 + /* 15886 */ MCD_OPC_CheckPredicate, + 43, + 34, + 5, + 0, // Skip to: 17205 + /* 15891 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 27, + 5, + 0, // Skip to: 17205 + /* 15898 */ MCD_OPC_Decode, + 238, + 14, + 197, + 2, // Opcode: LWE + /* 15903 */ MCD_OPC_FilterValue, + 48, + 231, + 1, + 0, // Skip to: 16395 + /* 15908 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 15911 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 15933 + /* 15916 */ MCD_OPC_CheckPredicate, + 69, + 4, + 5, + 0, // Skip to: 17205 + /* 15921 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 253, + 4, + 0, // Skip to: 17205 + /* 15928 */ MCD_OPC_Decode, + 173, + 11, + 232, + 1, // Opcode: DPA_W_PH + /* 15933 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 15955 + /* 15938 */ MCD_OPC_CheckPredicate, + 69, + 238, + 4, + 0, // Skip to: 17205 + /* 15943 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 231, + 4, + 0, // Skip to: 17205 + /* 15950 */ MCD_OPC_Decode, + 196, + 11, + 232, + 1, // Opcode: DPS_W_PH + /* 15955 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 15977 + /* 15960 */ MCD_OPC_CheckPredicate, + 69, + 216, + 4, + 0, // Skip to: 17205 + /* 15965 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 209, + 4, + 0, // Skip to: 17205 + /* 15972 */ MCD_OPC_Decode, + 163, + 17, + 232, + 1, // Opcode: MULSA_W_PH + /* 15977 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 15999 + /* 15982 */ MCD_OPC_CheckPredicate, + 37, + 194, + 4, + 0, // Skip to: 17205 + /* 15987 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 187, + 4, + 0, // Skip to: 17205 + /* 15994 */ MCD_OPC_Decode, + 167, + 11, + 232, + 1, // Opcode: DPAU_H_QBL + /* 15999 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 16021 + /* 16004 */ MCD_OPC_CheckPredicate, + 37, + 172, + 4, + 0, // Skip to: 17205 + /* 16009 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 165, + 4, + 0, // Skip to: 17205 + /* 16016 */ MCD_OPC_Decode, + 165, + 11, + 232, + 1, // Opcode: DPAQ_S_W_PH + /* 16021 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 16043 + /* 16026 */ MCD_OPC_CheckPredicate, + 37, + 150, + 4, + 0, // Skip to: 17205 + /* 16031 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 143, + 4, + 0, // Skip to: 17205 + /* 16038 */ MCD_OPC_Decode, + 182, + 11, + 232, + 1, // Opcode: DPSQ_S_W_PH + /* 16043 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 16065 + /* 16048 */ MCD_OPC_CheckPredicate, + 37, + 128, + 4, + 0, // Skip to: 17205 + /* 16053 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 121, + 4, + 0, // Skip to: 17205 + /* 16060 */ MCD_OPC_Decode, + 161, + 17, + 232, + 1, // Opcode: MULSAQ_S_W_PH + /* 16065 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 16087 + /* 16070 */ MCD_OPC_CheckPredicate, + 37, + 106, + 4, + 0, // Skip to: 17205 + /* 16075 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 99, + 4, + 0, // Skip to: 17205 + /* 16082 */ MCD_OPC_Decode, + 169, + 11, + 232, + 1, // Opcode: DPAU_H_QBR + /* 16087 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 16109 + /* 16092 */ MCD_OPC_CheckPredicate, + 69, + 84, + 4, + 0, // Skip to: 17205 + /* 16097 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 77, + 4, + 0, // Skip to: 17205 + /* 16104 */ MCD_OPC_Decode, + 171, + 11, + 232, + 1, // Opcode: DPAX_W_PH + /* 16109 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 16131 + /* 16114 */ MCD_OPC_CheckPredicate, + 69, + 62, + 4, + 0, // Skip to: 17205 + /* 16119 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 55, + 4, + 0, // Skip to: 17205 + /* 16126 */ MCD_OPC_Decode, + 194, + 11, + 232, + 1, // Opcode: DPSX_W_PH + /* 16131 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 16153 + /* 16136 */ MCD_OPC_CheckPredicate, + 37, + 40, + 4, + 0, // Skip to: 17205 + /* 16141 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 33, + 4, + 0, // Skip to: 17205 + /* 16148 */ MCD_OPC_Decode, + 190, + 11, + 232, + 1, // Opcode: DPSU_H_QBL + /* 16153 */ MCD_OPC_FilterValue, + 12, + 17, + 0, + 0, // Skip to: 16175 + /* 16158 */ MCD_OPC_CheckPredicate, + 37, + 18, + 4, + 0, // Skip to: 17205 + /* 16163 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 11, + 4, + 0, // Skip to: 17205 + /* 16170 */ MCD_OPC_Decode, + 163, + 11, + 232, + 1, // Opcode: DPAQ_SA_L_W + /* 16175 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 16197 + /* 16180 */ MCD_OPC_CheckPredicate, + 37, + 252, + 3, + 0, // Skip to: 17205 + /* 16185 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 245, + 3, + 0, // Skip to: 17205 + /* 16192 */ MCD_OPC_Decode, + 180, + 11, + 232, + 1, // Opcode: DPSQ_SA_L_W + /* 16197 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 16219 + /* 16202 */ MCD_OPC_CheckPredicate, + 37, + 230, + 3, + 0, // Skip to: 17205 + /* 16207 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 223, + 3, + 0, // Skip to: 17205 + /* 16214 */ MCD_OPC_Decode, + 192, + 11, + 232, + 1, // Opcode: DPSU_H_QBR + /* 16219 */ MCD_OPC_FilterValue, + 16, + 17, + 0, + 0, // Skip to: 16241 + /* 16224 */ MCD_OPC_CheckPredicate, + 37, + 208, + 3, + 0, // Skip to: 17205 + /* 16229 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 201, + 3, + 0, // Skip to: 17205 + /* 16236 */ MCD_OPC_Decode, + 176, + 15, + 232, + 1, // Opcode: MAQ_SA_W_PHL + /* 16241 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 16263 + /* 16246 */ MCD_OPC_CheckPredicate, + 37, + 186, + 3, + 0, // Skip to: 17205 + /* 16251 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 179, + 3, + 0, // Skip to: 17205 + /* 16258 */ MCD_OPC_Decode, + 178, + 15, + 232, + 1, // Opcode: MAQ_SA_W_PHR + /* 16263 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 16285 + /* 16268 */ MCD_OPC_CheckPredicate, + 37, + 164, + 3, + 0, // Skip to: 17205 + /* 16273 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 157, + 3, + 0, // Skip to: 17205 + /* 16280 */ MCD_OPC_Decode, + 180, + 15, + 232, + 1, // Opcode: MAQ_S_W_PHL + /* 16285 */ MCD_OPC_FilterValue, + 22, + 17, + 0, + 0, // Skip to: 16307 + /* 16290 */ MCD_OPC_CheckPredicate, + 37, + 142, + 3, + 0, // Skip to: 17205 + /* 16295 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 135, + 3, + 0, // Skip to: 17205 + /* 16302 */ MCD_OPC_Decode, + 182, + 15, + 232, + 1, // Opcode: MAQ_S_W_PHR + /* 16307 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 16329 + /* 16312 */ MCD_OPC_CheckPredicate, + 69, + 120, + 3, + 0, // Skip to: 17205 + /* 16317 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 113, + 3, + 0, // Skip to: 17205 + /* 16324 */ MCD_OPC_Decode, + 161, + 11, + 232, + 1, // Opcode: DPAQX_S_W_PH + /* 16329 */ MCD_OPC_FilterValue, + 25, + 17, + 0, + 0, // Skip to: 16351 + /* 16334 */ MCD_OPC_CheckPredicate, + 69, + 98, + 3, + 0, // Skip to: 17205 + /* 16339 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 91, + 3, + 0, // Skip to: 17205 + /* 16346 */ MCD_OPC_Decode, + 178, + 11, + 232, + 1, // Opcode: DPSQX_S_W_PH + /* 16351 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 16373 + /* 16356 */ MCD_OPC_CheckPredicate, + 69, + 76, + 3, + 0, // Skip to: 17205 + /* 16361 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 69, + 3, + 0, // Skip to: 17205 + /* 16368 */ MCD_OPC_Decode, + 159, + 11, + 232, + 1, // Opcode: DPAQX_SA_W_PH + /* 16373 */ MCD_OPC_FilterValue, + 27, + 59, + 3, + 0, // Skip to: 17205 + /* 16378 */ MCD_OPC_CheckPredicate, + 69, + 54, + 3, + 0, // Skip to: 17205 + /* 16383 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 47, + 3, + 0, // Skip to: 17205 + /* 16390 */ MCD_OPC_Decode, + 176, + 11, + 232, + 1, // Opcode: DPSQX_SA_W_PH + /* 16395 */ MCD_OPC_FilterValue, + 49, + 48, + 0, + 0, // Skip to: 16448 + /* 16400 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 16403 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16418 + /* 16408 */ MCD_OPC_CheckPredicate, + 69, + 24, + 3, + 0, // Skip to: 17205 + /* 16413 */ MCD_OPC_Decode, + 159, + 6, + 199, + 2, // Opcode: APPEND + /* 16418 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 16433 + /* 16423 */ MCD_OPC_CheckPredicate, + 69, + 9, + 3, + 0, // Skip to: 17205 + /* 16428 */ MCD_OPC_Decode, + 170, + 18, + 199, + 2, // Opcode: PREPEND + /* 16433 */ MCD_OPC_FilterValue, + 16, + 255, + 2, + 0, // Skip to: 17205 + /* 16438 */ MCD_OPC_CheckPredicate, + 69, + 250, + 2, + 0, // Skip to: 17205 + /* 16443 */ MCD_OPC_Decode, + 203, + 6, + 199, + 2, // Opcode: BALIGN + /* 16448 */ MCD_OPC_FilterValue, + 56, + 107, + 1, + 0, // Skip to: 16816 + /* 16453 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 16456 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 16478 + /* 16461 */ MCD_OPC_CheckPredicate, + 37, + 227, + 2, + 0, // Skip to: 17205 + /* 16466 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 220, + 2, + 0, // Skip to: 17205 + /* 16473 */ MCD_OPC_Decode, + 132, + 12, + 200, + 2, // Opcode: EXTR_W + /* 16478 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 16500 + /* 16483 */ MCD_OPC_CheckPredicate, + 37, + 205, + 2, + 0, // Skip to: 17205 + /* 16488 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 198, + 2, + 0, // Skip to: 17205 + /* 16495 */ MCD_OPC_Decode, + 252, + 11, + 201, + 2, // Opcode: EXTRV_W + /* 16500 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 16522 + /* 16505 */ MCD_OPC_CheckPredicate, + 37, + 183, + 2, + 0, // Skip to: 17205 + /* 16510 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 176, + 2, + 0, // Skip to: 17205 + /* 16517 */ MCD_OPC_Decode, + 238, + 11, + 200, + 2, // Opcode: EXTP + /* 16522 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 16544 + /* 16527 */ MCD_OPC_CheckPredicate, + 37, + 161, + 2, + 0, // Skip to: 17205 + /* 16532 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 154, + 2, + 0, // Skip to: 17205 + /* 16539 */ MCD_OPC_Decode, + 243, + 11, + 201, + 2, // Opcode: EXTPV + /* 16544 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 16566 + /* 16549 */ MCD_OPC_CheckPredicate, + 37, + 139, + 2, + 0, // Skip to: 17205 + /* 16554 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 132, + 2, + 0, // Skip to: 17205 + /* 16561 */ MCD_OPC_Decode, + 128, + 12, + 200, + 2, // Opcode: EXTR_R_W + /* 16566 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 16588 + /* 16571 */ MCD_OPC_CheckPredicate, + 37, + 117, + 2, + 0, // Skip to: 17205 + /* 16576 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 110, + 2, + 0, // Skip to: 17205 + /* 16583 */ MCD_OPC_Decode, + 248, + 11, + 201, + 2, // Opcode: EXTRV_R_W + /* 16588 */ MCD_OPC_FilterValue, + 6, + 17, + 0, + 0, // Skip to: 16610 + /* 16593 */ MCD_OPC_CheckPredicate, + 37, + 95, + 2, + 0, // Skip to: 17205 + /* 16598 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 88, + 2, + 0, // Skip to: 17205 + /* 16605 */ MCD_OPC_Decode, + 254, + 11, + 200, + 2, // Opcode: EXTR_RS_W + /* 16610 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 16632 + /* 16615 */ MCD_OPC_CheckPredicate, + 37, + 73, + 2, + 0, // Skip to: 17205 + /* 16620 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 66, + 2, + 0, // Skip to: 17205 + /* 16627 */ MCD_OPC_Decode, + 246, + 11, + 201, + 2, // Opcode: EXTRV_RS_W + /* 16632 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 16654 + /* 16637 */ MCD_OPC_CheckPredicate, + 37, + 51, + 2, + 0, // Skip to: 17205 + /* 16642 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 44, + 2, + 0, // Skip to: 17205 + /* 16649 */ MCD_OPC_Decode, + 239, + 11, + 200, + 2, // Opcode: EXTPDP + /* 16654 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 16676 + /* 16659 */ MCD_OPC_CheckPredicate, + 37, + 29, + 2, + 0, // Skip to: 17205 + /* 16664 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 22, + 2, + 0, // Skip to: 17205 + /* 16671 */ MCD_OPC_Decode, + 240, + 11, + 201, + 2, // Opcode: EXTPDPV + /* 16676 */ MCD_OPC_FilterValue, + 14, + 17, + 0, + 0, // Skip to: 16698 + /* 16681 */ MCD_OPC_CheckPredicate, + 37, + 7, + 2, + 0, // Skip to: 17205 + /* 16686 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 0, + 2, + 0, // Skip to: 17205 + /* 16693 */ MCD_OPC_Decode, + 130, + 12, + 200, + 2, // Opcode: EXTR_S_H + /* 16698 */ MCD_OPC_FilterValue, + 15, + 17, + 0, + 0, // Skip to: 16720 + /* 16703 */ MCD_OPC_CheckPredicate, + 37, + 241, + 1, + 0, // Skip to: 17205 + /* 16708 */ MCD_OPC_CheckField, + 13, + 3, + 0, + 234, + 1, + 0, // Skip to: 17205 + /* 16715 */ MCD_OPC_Decode, + 250, + 11, + 201, + 2, // Opcode: EXTRV_S_H + /* 16720 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 16735 + /* 16725 */ MCD_OPC_CheckPredicate, + 37, + 219, + 1, + 0, // Skip to: 17205 + /* 16730 */ MCD_OPC_Decode, + 176, + 18, + 202, + 2, // Opcode: RDDSP + /* 16735 */ MCD_OPC_FilterValue, + 19, + 10, + 0, + 0, // Skip to: 16750 + /* 16740 */ MCD_OPC_CheckPredicate, + 40, + 204, + 1, + 0, // Skip to: 17205 + /* 16745 */ MCD_OPC_Decode, + 139, + 22, + 203, + 2, // Opcode: WRDSP + /* 16750 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 16772 + /* 16755 */ MCD_OPC_CheckPredicate, + 37, + 189, + 1, + 0, // Skip to: 17205 + /* 16760 */ MCD_OPC_CheckField, + 13, + 7, + 0, + 182, + 1, + 0, // Skip to: 17205 + /* 16767 */ MCD_OPC_Decode, + 180, + 19, + 204, + 2, // Opcode: SHILO + /* 16772 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 16794 + /* 16777 */ MCD_OPC_CheckPredicate, + 37, + 167, + 1, + 0, // Skip to: 17205 + /* 16782 */ MCD_OPC_CheckField, + 13, + 8, + 0, + 160, + 1, + 0, // Skip to: 17205 + /* 16789 */ MCD_OPC_Decode, + 181, + 19, + 205, + 2, // Opcode: SHILOV + /* 16794 */ MCD_OPC_FilterValue, + 31, + 150, + 1, + 0, // Skip to: 17205 + /* 16799 */ MCD_OPC_CheckPredicate, + 37, + 145, + 1, + 0, // Skip to: 17205 + /* 16804 */ MCD_OPC_CheckField, + 13, + 8, + 0, + 138, + 1, + 0, // Skip to: 17205 + /* 16811 */ MCD_OPC_Decode, + 251, + 16, + 205, + 2, // Opcode: MTHLIP + /* 16816 */ MCD_OPC_FilterValue, + 59, + 128, + 1, + 0, // Skip to: 17205 + /* 16821 */ MCD_OPC_CheckPredicate, + 27, + 123, + 1, + 0, // Skip to: 17205 + /* 16826 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 116, + 1, + 0, // Skip to: 17205 + /* 16833 */ MCD_OPC_CheckField, + 9, + 2, + 0, + 109, + 1, + 0, // Skip to: 17205 + /* 16840 */ MCD_OPC_Decode, + 178, + 18, + 206, + 2, // Opcode: RDHWR + /* 16845 */ MCD_OPC_FilterValue, + 32, + 10, + 0, + 0, // Skip to: 16860 + /* 16850 */ MCD_OPC_CheckPredicate, + 27, + 94, + 1, + 0, // Skip to: 17205 + /* 16855 */ MCD_OPC_Decode, + 152, + 14, + 130, + 1, // Opcode: LB + /* 16860 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 16875 + /* 16865 */ MCD_OPC_CheckPredicate, + 27, + 79, + 1, + 0, // Skip to: 17205 + /* 16870 */ MCD_OPC_Decode, + 192, + 14, + 130, + 1, // Opcode: LH + /* 16875 */ MCD_OPC_FilterValue, + 34, + 10, + 0, + 0, // Skip to: 16890 + /* 16880 */ MCD_OPC_CheckPredicate, + 31, + 64, + 1, + 0, // Skip to: 17205 + /* 16885 */ MCD_OPC_Decode, + 241, + 14, + 130, + 1, // Opcode: LWL + /* 16890 */ MCD_OPC_FilterValue, + 35, + 10, + 0, + 0, // Skip to: 16905 + /* 16895 */ MCD_OPC_CheckPredicate, + 27, + 49, + 1, + 0, // Skip to: 17205 + /* 16900 */ MCD_OPC_Decode, + 227, + 14, + 130, + 1, // Opcode: LW + /* 16905 */ MCD_OPC_FilterValue, + 36, + 10, + 0, + 0, // Skip to: 16920 + /* 16910 */ MCD_OPC_CheckPredicate, + 27, + 34, + 1, + 0, // Skip to: 17205 + /* 16915 */ MCD_OPC_Decode, + 162, + 14, + 130, + 1, // Opcode: LBu + /* 16920 */ MCD_OPC_FilterValue, + 37, + 10, + 0, + 0, // Skip to: 16935 + /* 16925 */ MCD_OPC_CheckPredicate, + 27, + 19, + 1, + 0, // Skip to: 17205 + /* 16930 */ MCD_OPC_Decode, + 200, + 14, + 130, + 1, // Opcode: LHu + /* 16935 */ MCD_OPC_FilterValue, + 38, + 10, + 0, + 0, // Skip to: 16950 + /* 16940 */ MCD_OPC_CheckPredicate, + 31, + 4, + 1, + 0, // Skip to: 17205 + /* 16945 */ MCD_OPC_Decode, + 252, + 14, + 130, + 1, // Opcode: LWR + /* 16950 */ MCD_OPC_FilterValue, + 40, + 10, + 0, + 0, // Skip to: 16965 + /* 16955 */ MCD_OPC_CheckPredicate, + 27, + 245, + 0, + 0, // Skip to: 17205 + /* 16960 */ MCD_OPC_Decode, + 234, + 18, + 130, + 1, // Opcode: SB + /* 16965 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 16980 + /* 16970 */ MCD_OPC_CheckPredicate, + 27, + 230, + 0, + 0, // Skip to: 17205 + /* 16975 */ MCD_OPC_Decode, + 171, + 19, + 130, + 1, // Opcode: SH + /* 16980 */ MCD_OPC_FilterValue, + 42, + 10, + 0, + 0, // Skip to: 16995 + /* 16985 */ MCD_OPC_CheckPredicate, + 31, + 215, + 0, + 0, // Skip to: 17205 + /* 16990 */ MCD_OPC_Decode, + 147, + 21, + 130, + 1, // Opcode: SWL + /* 16995 */ MCD_OPC_FilterValue, + 43, + 10, + 0, + 0, // Skip to: 17010 + /* 17000 */ MCD_OPC_CheckPredicate, + 27, + 200, + 0, + 0, // Skip to: 17205 + /* 17005 */ MCD_OPC_Decode, + 133, + 21, + 130, + 1, // Opcode: SW + /* 17010 */ MCD_OPC_FilterValue, + 46, + 10, + 0, + 0, // Skip to: 17025 + /* 17015 */ MCD_OPC_CheckPredicate, + 31, + 185, + 0, + 0, // Skip to: 17205 + /* 17020 */ MCD_OPC_Decode, + 156, + 21, + 130, + 1, // Opcode: SWR + /* 17025 */ MCD_OPC_FilterValue, + 47, + 10, + 0, + 0, // Skip to: 17040 + /* 17030 */ MCD_OPC_CheckPredicate, + 71, + 170, + 0, + 0, // Skip to: 17205 + /* 17035 */ MCD_OPC_Decode, + 149, + 8, + 207, + 2, // Opcode: CACHE + /* 17040 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 17055 + /* 17045 */ MCD_OPC_CheckPredicate, + 72, + 155, + 0, + 0, // Skip to: 17205 + /* 17050 */ MCD_OPC_Decode, + 207, + 14, + 130, + 1, // Opcode: LL + /* 17055 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 17070 + /* 17060 */ MCD_OPC_CheckPredicate, + 47, + 140, + 0, + 0, // Skip to: 17205 + /* 17065 */ MCD_OPC_Decode, + 230, + 14, + 208, + 2, // Opcode: LWC1 + /* 17070 */ MCD_OPC_FilterValue, + 50, + 10, + 0, + 0, // Skip to: 17085 + /* 17075 */ MCD_OPC_CheckPredicate, + 31, + 125, + 0, + 0, // Skip to: 17205 + /* 17080 */ MCD_OPC_Decode, + 232, + 14, + 209, + 2, // Opcode: LWC2 + /* 17085 */ MCD_OPC_FilterValue, + 51, + 10, + 0, + 0, // Skip to: 17100 + /* 17090 */ MCD_OPC_CheckPredicate, + 71, + 110, + 0, + 0, // Skip to: 17205 + /* 17095 */ MCD_OPC_Decode, + 163, + 18, + 207, + 2, // Opcode: PREF + /* 17100 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 17115 + /* 17105 */ MCD_OPC_CheckPredicate, + 57, + 95, + 0, + 0, // Skip to: 17205 + /* 17110 */ MCD_OPC_Decode, + 168, + 14, + 208, + 2, // Opcode: LDC1 + /* 17115 */ MCD_OPC_FilterValue, + 54, + 10, + 0, + 0, // Skip to: 17130 + /* 17120 */ MCD_OPC_CheckPredicate, + 39, + 80, + 0, + 0, // Skip to: 17205 + /* 17125 */ MCD_OPC_Decode, + 172, + 14, + 209, + 2, // Opcode: LDC2 + /* 17130 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 17145 + /* 17135 */ MCD_OPC_CheckPredicate, + 72, + 65, + 0, + 0, // Skip to: 17205 + /* 17140 */ MCD_OPC_Decode, + 242, + 18, + 130, + 1, // Opcode: SC + /* 17145 */ MCD_OPC_FilterValue, + 57, + 10, + 0, + 0, // Skip to: 17160 + /* 17150 */ MCD_OPC_CheckPredicate, + 47, + 50, + 0, + 0, // Skip to: 17205 + /* 17155 */ MCD_OPC_Decode, + 137, + 21, + 208, + 2, // Opcode: SWC1 + /* 17160 */ MCD_OPC_FilterValue, + 58, + 10, + 0, + 0, // Skip to: 17175 + /* 17165 */ MCD_OPC_CheckPredicate, + 31, + 35, + 0, + 0, // Skip to: 17205 + /* 17170 */ MCD_OPC_Decode, + 139, + 21, + 209, + 2, // Opcode: SWC2 + /* 17175 */ MCD_OPC_FilterValue, + 61, + 10, + 0, + 0, // Skip to: 17190 + /* 17180 */ MCD_OPC_CheckPredicate, + 57, + 20, + 0, + 0, // Skip to: 17205 + /* 17185 */ MCD_OPC_Decode, + 131, + 19, + 208, + 2, // Opcode: SDC1 + /* 17190 */ MCD_OPC_FilterValue, + 62, + 10, + 0, + 0, // Skip to: 17205 + /* 17195 */ MCD_OPC_CheckPredicate, + 39, + 5, + 0, + 0, // Skip to: 17205 + /* 17200 */ MCD_OPC_Decode, + 135, + 19, + 209, + 2, // Opcode: SDC2 + /* 17205 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMips32_64_PTR6432[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 24 + /* 8 */ MCD_OPC_CheckPredicate, + 73, + 41, + 0, + 0, // Skip to: 54 + /* 13 */ MCD_OPC_CheckField, + 0, + 21, + 8, + 34, + 0, + 0, // Skip to: 54 + /* 20 */ MCD_OPC_Decode, + 135, + 14, + 13, // Opcode: JR64 + /* 24 */ MCD_OPC_FilterValue, + 48, + 10, + 0, + 0, // Skip to: 39 + /* 29 */ MCD_OPC_CheckPredicate, + 74, + 20, + 0, + 0, // Skip to: 54 + /* 34 */ MCD_OPC_Decode, + 208, + 14, + 130, + 1, // Opcode: LL64 + /* 39 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 54 + /* 44 */ MCD_OPC_CheckPredicate, + 74, + 5, + 0, + 0, // Skip to: 54 + /* 49 */ MCD_OPC_Decode, + 243, + 18, + 130, + 1, // Opcode: SC64 + /* 54 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMips32r6_64r632[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 29 -/* 14 */ MCD_OPC_CheckPredicate, 36, 37, 7, // Skip to: 1847 -/* 18 */ MCD_OPC_CheckField, 8, 3, 0, 31, 7, // Skip to: 1847 -/* 24 */ MCD_OPC_Decode, 206, 7, 221, 1, // Opcode: LSA_R6 -/* 29 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 47 -/* 33 */ MCD_OPC_CheckPredicate, 36, 18, 7, // Skip to: 1847 -/* 37 */ MCD_OPC_CheckField, 6, 15, 16, 12, 7, // Skip to: 1847 -/* 43 */ MCD_OPC_Decode, 142, 7, 61, // Opcode: JR_HB_R6 -/* 47 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 59 -/* 51 */ MCD_OPC_CheckPredicate, 36, 0, 7, // Skip to: 1847 -/* 55 */ MCD_OPC_Decode, 155, 11, 64, // Opcode: SDBBP_R6 -/* 59 */ MCD_OPC_FilterValue, 16, 20, 0, // Skip to: 83 -/* 63 */ MCD_OPC_CheckPredicate, 36, 244, 6, // Skip to: 1847 -/* 67 */ MCD_OPC_CheckField, 16, 5, 0, 238, 6, // Skip to: 1847 -/* 73 */ MCD_OPC_CheckField, 6, 5, 1, 232, 6, // Skip to: 1847 -/* 79 */ MCD_OPC_Decode, 154, 3, 62, // Opcode: CLZ_R6 -/* 83 */ MCD_OPC_FilterValue, 17, 20, 0, // Skip to: 107 -/* 87 */ MCD_OPC_CheckPredicate, 36, 220, 6, // Skip to: 1847 -/* 91 */ MCD_OPC_CheckField, 16, 5, 0, 214, 6, // Skip to: 1847 -/* 97 */ MCD_OPC_CheckField, 6, 5, 1, 208, 6, // Skip to: 1847 -/* 103 */ MCD_OPC_Decode, 135, 3, 62, // Opcode: CLO_R6 -/* 107 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 132 -/* 111 */ MCD_OPC_CheckPredicate, 37, 196, 6, // Skip to: 1847 -/* 115 */ MCD_OPC_CheckField, 16, 5, 0, 190, 6, // Skip to: 1847 -/* 121 */ MCD_OPC_CheckField, 6, 5, 1, 184, 6, // Skip to: 1847 -/* 127 */ MCD_OPC_Decode, 171, 4, 222, 1, // Opcode: DCLZ_R6 -/* 132 */ MCD_OPC_FilterValue, 19, 21, 0, // Skip to: 157 -/* 136 */ MCD_OPC_CheckPredicate, 37, 171, 6, // Skip to: 1847 -/* 140 */ MCD_OPC_CheckField, 16, 5, 0, 165, 6, // Skip to: 1847 -/* 146 */ MCD_OPC_CheckField, 6, 5, 1, 159, 6, // Skip to: 1847 -/* 152 */ MCD_OPC_Decode, 169, 4, 222, 1, // Opcode: DCLO_R6 -/* 157 */ MCD_OPC_FilterValue, 21, 15, 0, // Skip to: 176 -/* 161 */ MCD_OPC_CheckPredicate, 37, 146, 6, // Skip to: 1847 -/* 165 */ MCD_OPC_CheckField, 8, 3, 0, 140, 6, // Skip to: 1847 -/* 171 */ MCD_OPC_Decode, 195, 4, 223, 1, // Opcode: DLSA_R6 -/* 176 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 207 -/* 180 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 195 -/* 187 */ MCD_OPC_CheckPredicate, 36, 120, 6, // Skip to: 1847 -/* 191 */ MCD_OPC_Decode, 221, 9, 35, // Opcode: MUL_R6 -/* 195 */ MCD_OPC_FilterValue, 3, 112, 6, // Skip to: 1847 -/* 199 */ MCD_OPC_CheckPredicate, 36, 108, 6, // Skip to: 1847 -/* 203 */ MCD_OPC_Decode, 191, 9, 35, // Opcode: MUH -/* 207 */ MCD_OPC_FilterValue, 25, 27, 0, // Skip to: 238 -/* 211 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 226 -/* 218 */ MCD_OPC_CheckPredicate, 36, 89, 6, // Skip to: 1847 -/* 222 */ MCD_OPC_Decode, 212, 9, 35, // Opcode: MULU -/* 226 */ MCD_OPC_FilterValue, 3, 81, 6, // Skip to: 1847 -/* 230 */ MCD_OPC_CheckPredicate, 36, 77, 6, // Skip to: 1847 -/* 234 */ MCD_OPC_Decode, 192, 9, 35, // Opcode: MUHU -/* 238 */ MCD_OPC_FilterValue, 26, 27, 0, // Skip to: 269 -/* 242 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 257 -/* 249 */ MCD_OPC_CheckPredicate, 36, 58, 6, // Skip to: 1847 -/* 253 */ MCD_OPC_Decode, 183, 4, 35, // Opcode: DIV -/* 257 */ MCD_OPC_FilterValue, 3, 50, 6, // Skip to: 1847 -/* 261 */ MCD_OPC_CheckPredicate, 36, 46, 6, // Skip to: 1847 -/* 265 */ MCD_OPC_Decode, 222, 8, 35, // Opcode: MOD -/* 269 */ MCD_OPC_FilterValue, 27, 27, 0, // Skip to: 300 -/* 273 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 276 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 288 -/* 280 */ MCD_OPC_CheckPredicate, 36, 27, 6, // Skip to: 1847 -/* 284 */ MCD_OPC_Decode, 184, 4, 35, // Opcode: DIVU -/* 288 */ MCD_OPC_FilterValue, 3, 19, 6, // Skip to: 1847 -/* 292 */ MCD_OPC_CheckPredicate, 36, 15, 6, // Skip to: 1847 -/* 296 */ MCD_OPC_Decode, 224, 8, 35, // Opcode: MODU -/* 300 */ MCD_OPC_FilterValue, 28, 29, 0, // Skip to: 333 -/* 304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 307 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 320 -/* 311 */ MCD_OPC_CheckPredicate, 37, 252, 5, // Skip to: 1847 -/* 315 */ MCD_OPC_Decode, 210, 4, 224, 1, // Opcode: DMUL_R6 -/* 320 */ MCD_OPC_FilterValue, 3, 243, 5, // Skip to: 1847 -/* 324 */ MCD_OPC_CheckPredicate, 37, 239, 5, // Skip to: 1847 -/* 328 */ MCD_OPC_Decode, 204, 4, 224, 1, // Opcode: DMUH -/* 333 */ MCD_OPC_FilterValue, 29, 29, 0, // Skip to: 366 -/* 337 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 353 -/* 344 */ MCD_OPC_CheckPredicate, 37, 219, 5, // Skip to: 1847 -/* 348 */ MCD_OPC_Decode, 209, 4, 224, 1, // Opcode: DMULU -/* 353 */ MCD_OPC_FilterValue, 3, 210, 5, // Skip to: 1847 -/* 357 */ MCD_OPC_CheckPredicate, 37, 206, 5, // Skip to: 1847 -/* 361 */ MCD_OPC_Decode, 205, 4, 224, 1, // Opcode: DMUHU -/* 366 */ MCD_OPC_FilterValue, 30, 29, 0, // Skip to: 399 -/* 370 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 386 -/* 377 */ MCD_OPC_CheckPredicate, 37, 186, 5, // Skip to: 1847 -/* 381 */ MCD_OPC_Decode, 172, 4, 224, 1, // Opcode: DDIV -/* 386 */ MCD_OPC_FilterValue, 3, 177, 5, // Skip to: 1847 -/* 390 */ MCD_OPC_CheckPredicate, 37, 173, 5, // Skip to: 1847 -/* 394 */ MCD_OPC_Decode, 199, 4, 224, 1, // Opcode: DMOD -/* 399 */ MCD_OPC_FilterValue, 31, 29, 0, // Skip to: 432 -/* 403 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 406 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 419 -/* 410 */ MCD_OPC_CheckPredicate, 37, 153, 5, // Skip to: 1847 -/* 414 */ MCD_OPC_Decode, 173, 4, 224, 1, // Opcode: DDIVU -/* 419 */ MCD_OPC_FilterValue, 3, 144, 5, // Skip to: 1847 -/* 423 */ MCD_OPC_CheckPredicate, 37, 140, 5, // Skip to: 1847 -/* 427 */ MCD_OPC_Decode, 200, 4, 224, 1, // Opcode: DMODU -/* 432 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 450 -/* 436 */ MCD_OPC_CheckPredicate, 38, 127, 5, // Skip to: 1847 -/* 440 */ MCD_OPC_CheckField, 6, 5, 0, 121, 5, // Skip to: 1847 -/* 446 */ MCD_OPC_Decode, 174, 11, 35, // Opcode: SELEQZ -/* 450 */ MCD_OPC_FilterValue, 55, 113, 5, // Skip to: 1847 -/* 454 */ MCD_OPC_CheckPredicate, 38, 109, 5, // Skip to: 1847 -/* 458 */ MCD_OPC_CheckField, 6, 5, 0, 103, 5, // Skip to: 1847 -/* 464 */ MCD_OPC_Decode, 178, 11, 35, // Opcode: SELNEZ -/* 468 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 519 -/* 472 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 475 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 488 -/* 479 */ MCD_OPC_CheckPredicate, 37, 84, 5, // Skip to: 1847 -/* 483 */ MCD_OPC_Decode, 163, 4, 225, 1, // Opcode: DAHI -/* 488 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 506 -/* 492 */ MCD_OPC_CheckPredicate, 36, 71, 5, // Skip to: 1847 -/* 496 */ MCD_OPC_CheckField, 21, 5, 0, 65, 5, // Skip to: 1847 -/* 502 */ MCD_OPC_Decode, 167, 1, 75, // Opcode: BAL -/* 506 */ MCD_OPC_FilterValue, 30, 57, 5, // Skip to: 1847 -/* 510 */ MCD_OPC_CheckPredicate, 37, 53, 5, // Skip to: 1847 -/* 514 */ MCD_OPC_Decode, 165, 4, 225, 1, // Opcode: DATI -/* 519 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 532 -/* 523 */ MCD_OPC_CheckPredicate, 36, 40, 5, // Skip to: 1847 -/* 527 */ MCD_OPC_Decode, 220, 1, 226, 1, // Opcode: BGEZALC -/* 532 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 545 -/* 536 */ MCD_OPC_CheckPredicate, 36, 27, 5, // Skip to: 1847 -/* 540 */ MCD_OPC_Decode, 134, 2, 227, 1, // Opcode: BLTZALC -/* 545 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 558 -/* 549 */ MCD_OPC_CheckPredicate, 36, 14, 5, // Skip to: 1847 -/* 553 */ MCD_OPC_Decode, 208, 1, 228, 1, // Opcode: BEQC -/* 558 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 570 -/* 562 */ MCD_OPC_CheckPredicate, 36, 1, 5, // Skip to: 1847 -/* 566 */ MCD_OPC_Decode, 137, 1, 47, // Opcode: AUI -/* 570 */ MCD_OPC_FilterValue, 17, 5, 3, // Skip to: 1347 -/* 574 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 577 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 590 -/* 581 */ MCD_OPC_CheckPredicate, 36, 238, 4, // Skip to: 1847 -/* 585 */ MCD_OPC_Decode, 180, 1, 229, 1, // Opcode: BC1EQZ -/* 590 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 603 -/* 594 */ MCD_OPC_CheckPredicate, 36, 225, 4, // Skip to: 1847 -/* 598 */ MCD_OPC_Decode, 184, 1, 229, 1, // Opcode: BC1NEZ -/* 603 */ MCD_OPC_FilterValue, 16, 150, 0, // Skip to: 757 -/* 607 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 610 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 623 -/* 614 */ MCD_OPC_CheckPredicate, 36, 205, 4, // Skip to: 1847 -/* 618 */ MCD_OPC_Decode, 183, 11, 230, 1, // Opcode: SEL_S -/* 623 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 635 -/* 627 */ MCD_OPC_CheckPredicate, 36, 192, 4, // Skip to: 1847 -/* 631 */ MCD_OPC_Decode, 177, 11, 93, // Opcode: SELEQZ_S -/* 635 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 647 -/* 639 */ MCD_OPC_CheckPredicate, 36, 180, 4, // Skip to: 1847 -/* 643 */ MCD_OPC_Decode, 181, 11, 93, // Opcode: SELNEZ_S -/* 647 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 660 -/* 651 */ MCD_OPC_CheckPredicate, 36, 168, 4, // Skip to: 1847 -/* 655 */ MCD_OPC_Decode, 132, 8, 231, 1, // Opcode: MADDF_S -/* 660 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 673 -/* 664 */ MCD_OPC_CheckPredicate, 36, 155, 4, // Skip to: 1847 -/* 668 */ MCD_OPC_Decode, 150, 9, 231, 1, // Opcode: MSUBF_S -/* 673 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 691 -/* 677 */ MCD_OPC_CheckPredicate, 36, 142, 4, // Skip to: 1847 -/* 681 */ MCD_OPC_CheckField, 16, 5, 0, 136, 4, // Skip to: 1847 -/* 687 */ MCD_OPC_Decode, 246, 10, 94, // Opcode: RINT_S -/* 691 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 709 -/* 695 */ MCD_OPC_CheckPredicate, 36, 124, 4, // Skip to: 1847 -/* 699 */ MCD_OPC_CheckField, 16, 5, 0, 118, 4, // Skip to: 1847 -/* 705 */ MCD_OPC_Decode, 244, 2, 94, // Opcode: CLASS_S -/* 709 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 721 -/* 713 */ MCD_OPC_CheckPredicate, 36, 106, 4, // Skip to: 1847 -/* 717 */ MCD_OPC_Decode, 211, 8, 93, // Opcode: MIN_S -/* 721 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 733 -/* 725 */ MCD_OPC_CheckPredicate, 36, 94, 4, // Skip to: 1847 -/* 729 */ MCD_OPC_Decode, 170, 8, 93, // Opcode: MAX_S -/* 733 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 745 -/* 737 */ MCD_OPC_CheckPredicate, 36, 82, 4, // Skip to: 1847 -/* 741 */ MCD_OPC_Decode, 197, 8, 93, // Opcode: MINA_S -/* 745 */ MCD_OPC_FilterValue, 31, 74, 4, // Skip to: 1847 -/* 749 */ MCD_OPC_CheckPredicate, 36, 70, 4, // Skip to: 1847 -/* 753 */ MCD_OPC_Decode, 156, 8, 93, // Opcode: MAXA_S -/* 757 */ MCD_OPC_FilterValue, 17, 156, 0, // Skip to: 917 -/* 761 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 764 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 777 -/* 768 */ MCD_OPC_CheckPredicate, 36, 51, 4, // Skip to: 1847 -/* 772 */ MCD_OPC_Decode, 182, 11, 232, 1, // Opcode: SEL_D -/* 777 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 790 -/* 781 */ MCD_OPC_CheckPredicate, 36, 38, 4, // Skip to: 1847 -/* 785 */ MCD_OPC_Decode, 176, 11, 233, 1, // Opcode: SELEQZ_D -/* 790 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 803 -/* 794 */ MCD_OPC_CheckPredicate, 36, 25, 4, // Skip to: 1847 -/* 798 */ MCD_OPC_Decode, 180, 11, 233, 1, // Opcode: SELNEZ_D -/* 803 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 816 -/* 807 */ MCD_OPC_CheckPredicate, 36, 12, 4, // Skip to: 1847 -/* 811 */ MCD_OPC_Decode, 131, 8, 234, 1, // Opcode: MADDF_D -/* 816 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 829 -/* 820 */ MCD_OPC_CheckPredicate, 36, 255, 3, // Skip to: 1847 -/* 824 */ MCD_OPC_Decode, 149, 9, 234, 1, // Opcode: MSUBF_D -/* 829 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 847 -/* 833 */ MCD_OPC_CheckPredicate, 36, 242, 3, // Skip to: 1847 -/* 837 */ MCD_OPC_CheckField, 16, 5, 0, 236, 3, // Skip to: 1847 -/* 843 */ MCD_OPC_Decode, 245, 10, 105, // Opcode: RINT_D -/* 847 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 865 -/* 851 */ MCD_OPC_CheckPredicate, 36, 224, 3, // Skip to: 1847 -/* 855 */ MCD_OPC_CheckField, 16, 5, 0, 218, 3, // Skip to: 1847 -/* 861 */ MCD_OPC_Decode, 243, 2, 105, // Opcode: CLASS_D -/* 865 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 878 -/* 869 */ MCD_OPC_CheckPredicate, 36, 206, 3, // Skip to: 1847 -/* 873 */ MCD_OPC_Decode, 210, 8, 233, 1, // Opcode: MIN_D -/* 878 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 891 -/* 882 */ MCD_OPC_CheckPredicate, 36, 193, 3, // Skip to: 1847 -/* 886 */ MCD_OPC_Decode, 169, 8, 233, 1, // Opcode: MAX_D -/* 891 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 904 -/* 895 */ MCD_OPC_CheckPredicate, 36, 180, 3, // Skip to: 1847 -/* 899 */ MCD_OPC_Decode, 196, 8, 233, 1, // Opcode: MINA_D -/* 904 */ MCD_OPC_FilterValue, 31, 171, 3, // Skip to: 1847 -/* 908 */ MCD_OPC_CheckPredicate, 36, 167, 3, // Skip to: 1847 -/* 912 */ MCD_OPC_Decode, 155, 8, 233, 1, // Opcode: MAXA_D -/* 917 */ MCD_OPC_FilterValue, 20, 211, 0, // Skip to: 1132 -/* 921 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 924 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 937 -/* 928 */ MCD_OPC_CheckPredicate, 36, 147, 3, // Skip to: 1847 -/* 932 */ MCD_OPC_Decode, 168, 3, 235, 1, // Opcode: CMP_F_S -/* 937 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 950 -/* 941 */ MCD_OPC_CheckPredicate, 36, 134, 3, // Skip to: 1847 -/* 945 */ MCD_OPC_Decode, 198, 3, 235, 1, // Opcode: CMP_UN_S -/* 950 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 963 -/* 954 */ MCD_OPC_CheckPredicate, 36, 121, 3, // Skip to: 1847 -/* 958 */ MCD_OPC_Decode, 166, 3, 235, 1, // Opcode: CMP_EQ_S -/* 963 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 976 -/* 967 */ MCD_OPC_CheckPredicate, 36, 108, 3, // Skip to: 1847 -/* 971 */ MCD_OPC_Decode, 192, 3, 235, 1, // Opcode: CMP_UEQ_S -/* 976 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 989 -/* 980 */ MCD_OPC_CheckPredicate, 36, 95, 3, // Skip to: 1847 -/* 984 */ MCD_OPC_Decode, 174, 3, 235, 1, // Opcode: CMP_LT_S -/* 989 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1002 -/* 993 */ MCD_OPC_CheckPredicate, 36, 82, 3, // Skip to: 1847 -/* 997 */ MCD_OPC_Decode, 196, 3, 235, 1, // Opcode: CMP_ULT_S -/* 1002 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1015 -/* 1006 */ MCD_OPC_CheckPredicate, 36, 69, 3, // Skip to: 1847 -/* 1010 */ MCD_OPC_Decode, 171, 3, 235, 1, // Opcode: CMP_LE_S -/* 1015 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1028 -/* 1019 */ MCD_OPC_CheckPredicate, 36, 56, 3, // Skip to: 1847 -/* 1023 */ MCD_OPC_Decode, 194, 3, 235, 1, // Opcode: CMP_ULE_S -/* 1028 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1041 -/* 1032 */ MCD_OPC_CheckPredicate, 36, 43, 3, // Skip to: 1847 -/* 1036 */ MCD_OPC_Decode, 176, 3, 235, 1, // Opcode: CMP_SAF_S -/* 1041 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1054 -/* 1045 */ MCD_OPC_CheckPredicate, 36, 30, 3, // Skip to: 1847 -/* 1049 */ MCD_OPC_Decode, 190, 3, 235, 1, // Opcode: CMP_SUN_S -/* 1054 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1067 -/* 1058 */ MCD_OPC_CheckPredicate, 36, 17, 3, // Skip to: 1847 -/* 1062 */ MCD_OPC_Decode, 178, 3, 235, 1, // Opcode: CMP_SEQ_S -/* 1067 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1080 -/* 1071 */ MCD_OPC_CheckPredicate, 36, 4, 3, // Skip to: 1847 -/* 1075 */ MCD_OPC_Decode, 184, 3, 235, 1, // Opcode: CMP_SUEQ_S -/* 1080 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1093 -/* 1084 */ MCD_OPC_CheckPredicate, 36, 247, 2, // Skip to: 1847 -/* 1088 */ MCD_OPC_Decode, 182, 3, 235, 1, // Opcode: CMP_SLT_S -/* 1093 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1106 -/* 1097 */ MCD_OPC_CheckPredicate, 36, 234, 2, // Skip to: 1847 -/* 1101 */ MCD_OPC_Decode, 188, 3, 235, 1, // Opcode: CMP_SULT_S -/* 1106 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1119 -/* 1110 */ MCD_OPC_CheckPredicate, 36, 221, 2, // Skip to: 1847 -/* 1114 */ MCD_OPC_Decode, 180, 3, 235, 1, // Opcode: CMP_SLE_S -/* 1119 */ MCD_OPC_FilterValue, 15, 212, 2, // Skip to: 1847 -/* 1123 */ MCD_OPC_CheckPredicate, 36, 208, 2, // Skip to: 1847 -/* 1127 */ MCD_OPC_Decode, 186, 3, 235, 1, // Opcode: CMP_SULE_S -/* 1132 */ MCD_OPC_FilterValue, 21, 199, 2, // Skip to: 1847 -/* 1136 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1139 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1152 -/* 1143 */ MCD_OPC_CheckPredicate, 36, 188, 2, // Skip to: 1847 -/* 1147 */ MCD_OPC_Decode, 167, 3, 236, 1, // Opcode: CMP_F_D -/* 1152 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1165 -/* 1156 */ MCD_OPC_CheckPredicate, 36, 175, 2, // Skip to: 1847 -/* 1160 */ MCD_OPC_Decode, 197, 3, 236, 1, // Opcode: CMP_UN_D -/* 1165 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1178 -/* 1169 */ MCD_OPC_CheckPredicate, 36, 162, 2, // Skip to: 1847 -/* 1173 */ MCD_OPC_Decode, 164, 3, 236, 1, // Opcode: CMP_EQ_D -/* 1178 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1191 -/* 1182 */ MCD_OPC_CheckPredicate, 36, 149, 2, // Skip to: 1847 -/* 1186 */ MCD_OPC_Decode, 191, 3, 236, 1, // Opcode: CMP_UEQ_D -/* 1191 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1204 -/* 1195 */ MCD_OPC_CheckPredicate, 36, 136, 2, // Skip to: 1847 -/* 1199 */ MCD_OPC_Decode, 172, 3, 236, 1, // Opcode: CMP_LT_D -/* 1204 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1217 -/* 1208 */ MCD_OPC_CheckPredicate, 36, 123, 2, // Skip to: 1847 -/* 1212 */ MCD_OPC_Decode, 195, 3, 236, 1, // Opcode: CMP_ULT_D -/* 1217 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1230 -/* 1221 */ MCD_OPC_CheckPredicate, 36, 110, 2, // Skip to: 1847 -/* 1225 */ MCD_OPC_Decode, 169, 3, 236, 1, // Opcode: CMP_LE_D -/* 1230 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1243 -/* 1234 */ MCD_OPC_CheckPredicate, 36, 97, 2, // Skip to: 1847 -/* 1238 */ MCD_OPC_Decode, 193, 3, 236, 1, // Opcode: CMP_ULE_D -/* 1243 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1256 -/* 1247 */ MCD_OPC_CheckPredicate, 36, 84, 2, // Skip to: 1847 -/* 1251 */ MCD_OPC_Decode, 175, 3, 236, 1, // Opcode: CMP_SAF_D -/* 1256 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1269 -/* 1260 */ MCD_OPC_CheckPredicate, 36, 71, 2, // Skip to: 1847 -/* 1264 */ MCD_OPC_Decode, 189, 3, 236, 1, // Opcode: CMP_SUN_D -/* 1269 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1282 -/* 1273 */ MCD_OPC_CheckPredicate, 36, 58, 2, // Skip to: 1847 -/* 1277 */ MCD_OPC_Decode, 177, 3, 236, 1, // Opcode: CMP_SEQ_D -/* 1282 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1295 -/* 1286 */ MCD_OPC_CheckPredicate, 36, 45, 2, // Skip to: 1847 -/* 1290 */ MCD_OPC_Decode, 183, 3, 236, 1, // Opcode: CMP_SUEQ_D -/* 1295 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1308 -/* 1299 */ MCD_OPC_CheckPredicate, 36, 32, 2, // Skip to: 1847 -/* 1303 */ MCD_OPC_Decode, 181, 3, 236, 1, // Opcode: CMP_SLT_D -/* 1308 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1321 -/* 1312 */ MCD_OPC_CheckPredicate, 36, 19, 2, // Skip to: 1847 -/* 1316 */ MCD_OPC_Decode, 187, 3, 236, 1, // Opcode: CMP_SULT_D -/* 1321 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1334 -/* 1325 */ MCD_OPC_CheckPredicate, 36, 6, 2, // Skip to: 1847 -/* 1329 */ MCD_OPC_Decode, 179, 3, 236, 1, // Opcode: CMP_SLE_D -/* 1334 */ MCD_OPC_FilterValue, 15, 253, 1, // Skip to: 1847 -/* 1338 */ MCD_OPC_CheckPredicate, 36, 249, 1, // Skip to: 1847 -/* 1342 */ MCD_OPC_Decode, 185, 3, 236, 1, // Opcode: CMP_SULE_D -/* 1347 */ MCD_OPC_FilterValue, 18, 81, 0, // Skip to: 1432 -/* 1351 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1354 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1367 -/* 1358 */ MCD_OPC_CheckPredicate, 36, 229, 1, // Skip to: 1847 -/* 1362 */ MCD_OPC_Decode, 188, 1, 237, 1, // Opcode: BC2EQZ -/* 1367 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1380 -/* 1371 */ MCD_OPC_CheckPredicate, 36, 216, 1, // Skip to: 1847 -/* 1375 */ MCD_OPC_Decode, 219, 7, 238, 1, // Opcode: LWC2_R6 -/* 1380 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1393 -/* 1384 */ MCD_OPC_CheckPredicate, 36, 203, 1, // Skip to: 1847 -/* 1388 */ MCD_OPC_Decode, 241, 12, 238, 1, // Opcode: SWC2_R6 -/* 1393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1406 -/* 1397 */ MCD_OPC_CheckPredicate, 36, 190, 1, // Skip to: 1847 -/* 1401 */ MCD_OPC_Decode, 191, 1, 237, 1, // Opcode: BC2NEZ -/* 1406 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1419 -/* 1410 */ MCD_OPC_CheckPredicate, 36, 177, 1, // Skip to: 1847 -/* 1414 */ MCD_OPC_Decode, 166, 7, 238, 1, // Opcode: LDC2_R6 -/* 1419 */ MCD_OPC_FilterValue, 15, 168, 1, // Skip to: 1847 -/* 1423 */ MCD_OPC_CheckPredicate, 36, 164, 1, // Skip to: 1847 -/* 1427 */ MCD_OPC_Decode, 160, 11, 238, 1, // Opcode: SDC2_R6 -/* 1432 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 1445 -/* 1436 */ MCD_OPC_CheckPredicate, 36, 151, 1, // Skip to: 1847 -/* 1440 */ MCD_OPC_Decode, 224, 1, 239, 1, // Opcode: BGEZC -/* 1445 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 1458 -/* 1449 */ MCD_OPC_CheckPredicate, 36, 138, 1, // Skip to: 1847 -/* 1453 */ MCD_OPC_Decode, 138, 2, 240, 1, // Opcode: BLTZC -/* 1458 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1471 -/* 1462 */ MCD_OPC_CheckPredicate, 36, 125, 1, // Skip to: 1847 -/* 1466 */ MCD_OPC_Decode, 147, 2, 241, 1, // Opcode: BNEC -/* 1471 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 1484 -/* 1475 */ MCD_OPC_CheckPredicate, 37, 112, 1, // Skip to: 1847 -/* 1479 */ MCD_OPC_Decode, 166, 4, 242, 1, // Opcode: DAUI -/* 1484 */ MCD_OPC_FilterValue, 31, 182, 0, // Skip to: 1670 -/* 1488 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1491 */ MCD_OPC_FilterValue, 32, 40, 0, // Skip to: 1535 -/* 1495 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 1498 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1523 -/* 1502 */ MCD_OPC_CheckPredicate, 36, 85, 1, // Skip to: 1847 -/* 1506 */ MCD_OPC_CheckField, 21, 5, 0, 79, 1, // Skip to: 1847 -/* 1512 */ MCD_OPC_CheckField, 6, 2, 0, 73, 1, // Skip to: 1847 -/* 1518 */ MCD_OPC_Decode, 250, 1, 205, 1, // Opcode: BITSWAP -/* 1523 */ MCD_OPC_FilterValue, 2, 64, 1, // Skip to: 1847 -/* 1527 */ MCD_OPC_CheckPredicate, 36, 60, 1, // Skip to: 1847 -/* 1531 */ MCD_OPC_Decode, 81, 221, 1, // Opcode: ALIGN -/* 1535 */ MCD_OPC_FilterValue, 36, 41, 0, // Skip to: 1580 -/* 1539 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 1542 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1567 -/* 1546 */ MCD_OPC_CheckPredicate, 37, 41, 1, // Skip to: 1847 -/* 1550 */ MCD_OPC_CheckField, 21, 5, 0, 35, 1, // Skip to: 1847 -/* 1556 */ MCD_OPC_CheckField, 6, 3, 0, 29, 1, // Skip to: 1847 -/* 1562 */ MCD_OPC_Decode, 167, 4, 243, 1, // Opcode: DBITSWAP -/* 1567 */ MCD_OPC_FilterValue, 1, 20, 1, // Skip to: 1847 -/* 1571 */ MCD_OPC_CheckPredicate, 37, 16, 1, // Skip to: 1847 -/* 1575 */ MCD_OPC_Decode, 164, 4, 244, 1, // Opcode: DALIGN -/* 1580 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1599 -/* 1584 */ MCD_OPC_CheckPredicate, 36, 3, 1, // Skip to: 1847 -/* 1588 */ MCD_OPC_CheckField, 6, 1, 0, 253, 0, // Skip to: 1847 -/* 1594 */ MCD_OPC_Decode, 222, 2, 245, 1, // Opcode: CACHE_R6 -/* 1599 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 1612 -/* 1603 */ MCD_OPC_CheckPredicate, 36, 240, 0, // Skip to: 1847 -/* 1607 */ MCD_OPC_Decode, 150, 11, 246, 1, // Opcode: SC_R6 -/* 1612 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 1625 -/* 1616 */ MCD_OPC_CheckPredicate, 36, 227, 0, // Skip to: 1847 -/* 1620 */ MCD_OPC_Decode, 148, 11, 246, 1, // Opcode: SCD_R6 -/* 1625 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 1644 -/* 1629 */ MCD_OPC_CheckPredicate, 36, 214, 0, // Skip to: 1847 -/* 1633 */ MCD_OPC_CheckField, 6, 1, 0, 208, 0, // Skip to: 1847 -/* 1639 */ MCD_OPC_Decode, 183, 10, 245, 1, // Opcode: PREF_R6 -/* 1644 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 1657 -/* 1648 */ MCD_OPC_CheckPredicate, 36, 195, 0, // Skip to: 1847 -/* 1652 */ MCD_OPC_Decode, 197, 7, 246, 1, // Opcode: LL_R6 -/* 1657 */ MCD_OPC_FilterValue, 55, 186, 0, // Skip to: 1847 -/* 1661 */ MCD_OPC_CheckPredicate, 36, 182, 0, // Skip to: 1847 -/* 1665 */ MCD_OPC_Decode, 195, 7, 246, 1, // Opcode: LLD_R6 -/* 1670 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1683 -/* 1674 */ MCD_OPC_CheckPredicate, 36, 169, 0, // Skip to: 1847 -/* 1678 */ MCD_OPC_Decode, 175, 1, 247, 1, // Opcode: BC -/* 1683 */ MCD_OPC_FilterValue, 54, 23, 0, // Skip to: 1710 -/* 1687 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1701 -/* 1691 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1701 -/* 1697 */ MCD_OPC_Decode, 135, 7, 52, // Opcode: JIC -/* 1701 */ MCD_OPC_CheckPredicate, 36, 142, 0, // Skip to: 1847 -/* 1705 */ MCD_OPC_Decode, 212, 1, 248, 1, // Opcode: BEQZC -/* 1710 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1723 -/* 1714 */ MCD_OPC_CheckPredicate, 36, 129, 0, // Skip to: 1847 -/* 1718 */ MCD_OPC_Decode, 168, 1, 247, 1, // Opcode: BALC -/* 1723 */ MCD_OPC_FilterValue, 59, 93, 0, // Skip to: 1820 -/* 1727 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... -/* 1730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1742 -/* 1734 */ MCD_OPC_CheckPredicate, 36, 109, 0, // Skip to: 1847 -/* 1738 */ MCD_OPC_Decode, 26, 249, 1, // Opcode: ADDIUPC -/* 1742 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1755 -/* 1746 */ MCD_OPC_CheckPredicate, 36, 97, 0, // Skip to: 1847 -/* 1750 */ MCD_OPC_Decode, 228, 7, 249, 1, // Opcode: LWPC -/* 1755 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1768 -/* 1759 */ MCD_OPC_CheckPredicate, 36, 84, 0, // Skip to: 1847 -/* 1763 */ MCD_OPC_Decode, 234, 7, 249, 1, // Opcode: LWUPC -/* 1768 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 1847 -/* 1772 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 1775 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1788 -/* 1779 */ MCD_OPC_CheckPredicate, 37, 64, 0, // Skip to: 1847 -/* 1783 */ MCD_OPC_Decode, 173, 7, 250, 1, // Opcode: LDPC -/* 1788 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 1847 -/* 1792 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 1795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1808 -/* 1799 */ MCD_OPC_CheckPredicate, 36, 44, 0, // Skip to: 1847 -/* 1803 */ MCD_OPC_Decode, 138, 1, 251, 1, // Opcode: AUIPC -/* 1808 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 1847 -/* 1812 */ MCD_OPC_CheckPredicate, 36, 31, 0, // Skip to: 1847 -/* 1816 */ MCD_OPC_Decode, 82, 251, 1, // Opcode: ALUIPC -/* 1820 */ MCD_OPC_FilterValue, 62, 23, 0, // Skip to: 1847 -/* 1824 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1838 -/* 1828 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1838 -/* 1834 */ MCD_OPC_Decode, 134, 7, 52, // Opcode: JIALC -/* 1838 */ MCD_OPC_CheckPredicate, 36, 5, 0, // Skip to: 1847 -/* 1842 */ MCD_OPC_Decode, 159, 2, 248, 1, // Opcode: BNEZC -/* 1847 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 14, + 2, + 0, // Skip to: 534 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 33 + /* 16 */ MCD_OPC_CheckPredicate, + 75, + 133, + 9, + 0, // Skip to: 2458 + /* 21 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 126, + 9, + 0, // Skip to: 2458 + /* 28 */ MCD_OPC_Decode, + 219, + 14, + 174, + 1, // Opcode: LSA_R6 + /* 33 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 55 + /* 38 */ MCD_OPC_CheckPredicate, + 75, + 111, + 9, + 0, // Skip to: 2458 + /* 43 */ MCD_OPC_CheckField, + 6, + 15, + 16, + 104, + 9, + 0, // Skip to: 2458 + /* 50 */ MCD_OPC_Decode, + 143, + 14, + 175, + 1, // Opcode: JR_HB_R6 + /* 55 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 70 + /* 60 */ MCD_OPC_CheckPredicate, + 76, + 89, + 9, + 0, // Skip to: 2458 + /* 65 */ MCD_OPC_Decode, + 130, + 19, + 177, + 1, // Opcode: SDBBP_R6 + /* 70 */ MCD_OPC_FilterValue, + 16, + 23, + 0, + 0, // Skip to: 98 + /* 75 */ MCD_OPC_CheckPredicate, + 75, + 74, + 9, + 0, // Skip to: 2458 + /* 80 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 67, + 9, + 0, // Skip to: 2458 + /* 87 */ MCD_OPC_CheckField, + 6, + 5, + 1, + 60, + 9, + 0, // Skip to: 2458 + /* 94 */ MCD_OPC_Decode, + 225, + 8, + 14, // Opcode: CLZ_R6 + /* 98 */ MCD_OPC_FilterValue, + 17, + 23, + 0, + 0, // Skip to: 126 + /* 103 */ MCD_OPC_CheckPredicate, + 75, + 46, + 9, + 0, // Skip to: 2458 + /* 108 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 39, + 9, + 0, // Skip to: 2458 + /* 115 */ MCD_OPC_CheckField, + 6, + 5, + 1, + 32, + 9, + 0, // Skip to: 2458 + /* 122 */ MCD_OPC_Decode, + 205, + 8, + 14, // Opcode: CLO_R6 + /* 126 */ MCD_OPC_FilterValue, + 18, + 23, + 0, + 0, // Skip to: 154 + /* 131 */ MCD_OPC_CheckPredicate, + 77, + 18, + 9, + 0, // Skip to: 2458 + /* 136 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 11, + 9, + 0, // Skip to: 2458 + /* 143 */ MCD_OPC_CheckField, + 6, + 5, + 1, + 4, + 9, + 0, // Skip to: 2458 + /* 150 */ MCD_OPC_Decode, + 225, + 10, + 15, // Opcode: DCLZ_R6 + /* 154 */ MCD_OPC_FilterValue, + 19, + 23, + 0, + 0, // Skip to: 182 + /* 159 */ MCD_OPC_CheckPredicate, + 77, + 246, + 8, + 0, // Skip to: 2458 + /* 164 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 239, + 8, + 0, // Skip to: 2458 + /* 171 */ MCD_OPC_CheckField, + 6, + 5, + 1, + 232, + 8, + 0, // Skip to: 2458 + /* 178 */ MCD_OPC_Decode, + 223, + 10, + 15, // Opcode: DCLO_R6 + /* 182 */ MCD_OPC_FilterValue, + 21, + 17, + 0, + 0, // Skip to: 204 + /* 187 */ MCD_OPC_CheckPredicate, + 77, + 218, + 8, + 0, // Skip to: 2458 + /* 192 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 211, + 8, + 0, // Skip to: 2458 + /* 199 */ MCD_OPC_Decode, + 254, + 10, + 183, + 1, // Opcode: DLSA_R6 + /* 204 */ MCD_OPC_FilterValue, + 24, + 31, + 0, + 0, // Skip to: 240 + /* 209 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 212 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 226 + /* 217 */ MCD_OPC_CheckPredicate, + 76, + 188, + 8, + 0, // Skip to: 2458 + /* 222 */ MCD_OPC_Decode, + 185, + 17, + 50, // Opcode: MUL_R6 + /* 226 */ MCD_OPC_FilterValue, + 3, + 179, + 8, + 0, // Skip to: 2458 + /* 231 */ MCD_OPC_CheckPredicate, + 76, + 174, + 8, + 0, // Skip to: 2458 + /* 236 */ MCD_OPC_Decode, + 137, + 17, + 50, // Opcode: MUH + /* 240 */ MCD_OPC_FilterValue, + 25, + 31, + 0, + 0, // Skip to: 276 + /* 245 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 248 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 262 + /* 253 */ MCD_OPC_CheckPredicate, + 76, + 152, + 8, + 0, // Skip to: 2458 + /* 258 */ MCD_OPC_Decode, + 173, + 17, + 50, // Opcode: MULU + /* 262 */ MCD_OPC_FilterValue, + 3, + 143, + 8, + 0, // Skip to: 2458 + /* 267 */ MCD_OPC_CheckPredicate, + 76, + 138, + 8, + 0, // Skip to: 2458 + /* 272 */ MCD_OPC_Decode, + 138, + 17, + 50, // Opcode: MUHU + /* 276 */ MCD_OPC_FilterValue, + 26, + 31, + 0, + 0, // Skip to: 312 + /* 281 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 284 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 298 + /* 289 */ MCD_OPC_CheckPredicate, + 76, + 116, + 8, + 0, // Skip to: 2458 + /* 294 */ MCD_OPC_Decode, + 239, + 10, + 50, // Opcode: DIV + /* 298 */ MCD_OPC_FilterValue, + 3, + 107, + 8, + 0, // Skip to: 2458 + /* 303 */ MCD_OPC_CheckPredicate, + 76, + 102, + 8, + 0, // Skip to: 2458 + /* 308 */ MCD_OPC_Decode, + 143, + 16, + 50, // Opcode: MOD + /* 312 */ MCD_OPC_FilterValue, + 27, + 31, + 0, + 0, // Skip to: 348 + /* 317 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 320 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 334 + /* 325 */ MCD_OPC_CheckPredicate, + 76, + 80, + 8, + 0, // Skip to: 2458 + /* 330 */ MCD_OPC_Decode, + 240, + 10, + 50, // Opcode: DIVU + /* 334 */ MCD_OPC_FilterValue, + 3, + 71, + 8, + 0, // Skip to: 2458 + /* 339 */ MCD_OPC_CheckPredicate, + 76, + 66, + 8, + 0, // Skip to: 2458 + /* 344 */ MCD_OPC_Decode, + 146, + 16, + 50, // Opcode: MODU + /* 348 */ MCD_OPC_FilterValue, + 28, + 31, + 0, + 0, // Skip to: 384 + /* 353 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 356 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 370 + /* 361 */ MCD_OPC_CheckPredicate, + 77, + 44, + 8, + 0, // Skip to: 2458 + /* 366 */ MCD_OPC_Decode, + 146, + 11, + 12, // Opcode: DMUL_R6 + /* 370 */ MCD_OPC_FilterValue, + 3, + 35, + 8, + 0, // Skip to: 2458 + /* 375 */ MCD_OPC_CheckPredicate, + 77, + 30, + 8, + 0, // Skip to: 2458 + /* 380 */ MCD_OPC_Decode, + 140, + 11, + 12, // Opcode: DMUH + /* 384 */ MCD_OPC_FilterValue, + 29, + 31, + 0, + 0, // Skip to: 420 + /* 389 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 392 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 406 + /* 397 */ MCD_OPC_CheckPredicate, + 77, + 8, + 8, + 0, // Skip to: 2458 + /* 402 */ MCD_OPC_Decode, + 145, + 11, + 12, // Opcode: DMULU + /* 406 */ MCD_OPC_FilterValue, + 3, + 255, + 7, + 0, // Skip to: 2458 + /* 411 */ MCD_OPC_CheckPredicate, + 77, + 250, + 7, + 0, // Skip to: 2458 + /* 416 */ MCD_OPC_Decode, + 141, + 11, + 12, // Opcode: DMUHU + /* 420 */ MCD_OPC_FilterValue, + 30, + 31, + 0, + 0, // Skip to: 456 + /* 425 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 428 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 442 + /* 433 */ MCD_OPC_CheckPredicate, + 77, + 228, + 7, + 0, // Skip to: 2458 + /* 438 */ MCD_OPC_Decode, + 226, + 10, + 12, // Opcode: DDIV + /* 442 */ MCD_OPC_FilterValue, + 3, + 219, + 7, + 0, // Skip to: 2458 + /* 447 */ MCD_OPC_CheckPredicate, + 77, + 214, + 7, + 0, // Skip to: 2458 + /* 452 */ MCD_OPC_Decode, + 132, + 11, + 12, // Opcode: DMOD + /* 456 */ MCD_OPC_FilterValue, + 31, + 31, + 0, + 0, // Skip to: 492 + /* 461 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 464 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 478 + /* 469 */ MCD_OPC_CheckPredicate, + 77, + 192, + 7, + 0, // Skip to: 2458 + /* 474 */ MCD_OPC_Decode, + 227, + 10, + 12, // Opcode: DDIVU + /* 478 */ MCD_OPC_FilterValue, + 3, + 183, + 7, + 0, // Skip to: 2458 + /* 483 */ MCD_OPC_CheckPredicate, + 77, + 178, + 7, + 0, // Skip to: 2458 + /* 488 */ MCD_OPC_Decode, + 133, + 11, + 12, // Opcode: DMODU + /* 492 */ MCD_OPC_FilterValue, + 53, + 16, + 0, + 0, // Skip to: 513 + /* 497 */ MCD_OPC_CheckPredicate, + 78, + 164, + 7, + 0, // Skip to: 2458 + /* 502 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 157, + 7, + 0, // Skip to: 2458 + /* 509 */ MCD_OPC_Decode, + 151, + 19, + 50, // Opcode: SELEQZ + /* 513 */ MCD_OPC_FilterValue, + 55, + 148, + 7, + 0, // Skip to: 2458 + /* 518 */ MCD_OPC_CheckPredicate, + 78, + 143, + 7, + 0, // Skip to: 2458 + /* 523 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 136, + 7, + 0, // Skip to: 2458 + /* 530 */ MCD_OPC_Decode, + 158, + 19, + 50, // Opcode: SELNEZ + /* 534 */ MCD_OPC_FilterValue, + 1, + 77, + 0, + 0, // Skip to: 616 + /* 539 */ MCD_OPC_ExtractField, + 16, + 5, // Inst{20-16} ... + /* 542 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 557 + /* 547 */ MCD_OPC_CheckPredicate, + 77, + 114, + 7, + 0, // Skip to: 2458 + /* 552 */ MCD_OPC_Decode, + 217, + 10, + 210, + 2, // Opcode: DAHI + /* 557 */ MCD_OPC_FilterValue, + 17, + 17, + 0, + 0, // Skip to: 579 + /* 562 */ MCD_OPC_CheckPredicate, + 75, + 99, + 7, + 0, // Skip to: 2458 + /* 567 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 92, + 7, + 0, // Skip to: 2458 + /* 574 */ MCD_OPC_Decode, + 200, + 6, + 187, + 1, // Opcode: BAL + /* 579 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 601 + /* 584 */ MCD_OPC_CheckPredicate, + 76, + 77, + 7, + 0, // Skip to: 2458 + /* 589 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 70, + 7, + 0, // Skip to: 2458 + /* 596 */ MCD_OPC_Decode, + 230, + 19, + 211, + 2, // Opcode: SIGRIE + /* 601 */ MCD_OPC_FilterValue, + 30, + 60, + 7, + 0, // Skip to: 2458 + /* 606 */ MCD_OPC_CheckPredicate, + 77, + 55, + 7, + 0, // Skip to: 2458 + /* 611 */ MCD_OPC_Decode, + 219, + 10, + 210, + 2, // Opcode: DATI + /* 616 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 631 + /* 621 */ MCD_OPC_CheckPredicate, + 76, + 40, + 7, + 0, // Skip to: 2458 + /* 626 */ MCD_OPC_Decode, + 140, + 7, + 212, + 2, // Opcode: BGEZALC + /* 631 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 646 + /* 636 */ MCD_OPC_CheckPredicate, + 76, + 25, + 7, + 0, // Skip to: 2458 + /* 641 */ MCD_OPC_Decode, + 197, + 7, + 213, + 2, // Opcode: BLTZALC + /* 646 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 661 + /* 651 */ MCD_OPC_CheckPredicate, + 76, + 10, + 7, + 0, // Skip to: 2458 + /* 656 */ MCD_OPC_Decode, + 246, + 6, + 214, + 2, // Opcode: BEQC + /* 661 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 676 + /* 666 */ MCD_OPC_CheckPredicate, + 75, + 251, + 6, + 0, // Skip to: 2458 + /* 671 */ MCD_OPC_Decode, + 169, + 6, + 192, + 1, // Opcode: AUI + /* 676 */ MCD_OPC_FilterValue, + 16, + 45, + 0, + 0, // Skip to: 726 + /* 681 */ MCD_OPC_ExtractField, + 0, + 16, // Inst{15-0} ... + /* 684 */ MCD_OPC_FilterValue, + 4, + 16, + 0, + 0, // Skip to: 705 + /* 689 */ MCD_OPC_CheckPredicate, + 75, + 228, + 6, + 0, // Skip to: 2458 + /* 694 */ MCD_OPC_CheckField, + 21, + 5, + 11, + 221, + 6, + 0, // Skip to: 2458 + /* 701 */ MCD_OPC_Decode, + 234, + 11, + 81, // Opcode: EVP + /* 705 */ MCD_OPC_FilterValue, + 36, + 212, + 6, + 0, // Skip to: 2458 + /* 710 */ MCD_OPC_CheckPredicate, + 75, + 207, + 6, + 0, // Skip to: 2458 + /* 715 */ MCD_OPC_CheckField, + 21, + 5, + 11, + 200, + 6, + 0, // Skip to: 2458 + /* 722 */ MCD_OPC_Decode, + 217, + 11, + 81, // Opcode: DVP + /* 726 */ MCD_OPC_FilterValue, + 17, + 135, + 3, + 0, // Skip to: 1634 + /* 731 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 734 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 749 + /* 739 */ MCD_OPC_CheckPredicate, + 79, + 178, + 6, + 0, // Skip to: 2458 + /* 744 */ MCD_OPC_Decode, + 213, + 6, + 215, + 2, // Opcode: BC1EQZ + /* 749 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 764 + /* 754 */ MCD_OPC_CheckPredicate, + 79, + 163, + 6, + 0, // Skip to: 2458 + /* 759 */ MCD_OPC_Decode, + 218, + 6, + 215, + 2, // Opcode: BC1NEZ + /* 764 */ MCD_OPC_FilterValue, + 16, + 182, + 0, + 0, // Skip to: 951 + /* 769 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 772 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 787 + /* 777 */ MCD_OPC_CheckPredicate, + 79, + 140, + 6, + 0, // Skip to: 2458 + /* 782 */ MCD_OPC_Decode, + 167, + 19, + 216, + 2, // Opcode: SEL_S + /* 787 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 802 + /* 792 */ MCD_OPC_CheckPredicate, + 79, + 125, + 6, + 0, // Skip to: 2458 + /* 797 */ MCD_OPC_Decode, + 156, + 19, + 207, + 1, // Opcode: SELEQZ_S + /* 802 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 817 + /* 807 */ MCD_OPC_CheckPredicate, + 79, + 110, + 6, + 0, // Skip to: 2458 + /* 812 */ MCD_OPC_Decode, + 163, + 19, + 207, + 1, // Opcode: SELNEZ_S + /* 817 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 832 + /* 822 */ MCD_OPC_CheckPredicate, + 79, + 95, + 6, + 0, // Skip to: 2458 + /* 827 */ MCD_OPC_Decode, + 154, + 15, + 217, + 2, // Opcode: MADDF_S + /* 832 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 847 + /* 837 */ MCD_OPC_CheckPredicate, + 79, + 80, + 6, + 0, // Skip to: 2458 + /* 842 */ MCD_OPC_Decode, + 205, + 16, + 217, + 2, // Opcode: MSUBF_S + /* 847 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 869 + /* 852 */ MCD_OPC_CheckPredicate, + 79, + 65, + 6, + 0, // Skip to: 2458 + /* 857 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 58, + 6, + 0, // Skip to: 2458 + /* 864 */ MCD_OPC_Decode, + 199, + 18, + 208, + 1, // Opcode: RINT_S + /* 869 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 891 + /* 874 */ MCD_OPC_CheckPredicate, + 79, + 43, + 6, + 0, // Skip to: 2458 + /* 879 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 36, + 6, + 0, // Skip to: 2458 + /* 886 */ MCD_OPC_Decode, + 184, + 8, + 208, + 1, // Opcode: CLASS_S + /* 891 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 906 + /* 896 */ MCD_OPC_CheckPredicate, + 79, + 21, + 6, + 0, // Skip to: 2458 + /* 901 */ MCD_OPC_Decode, + 133, + 16, + 207, + 1, // Opcode: MIN_S + /* 906 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 921 + /* 911 */ MCD_OPC_CheckPredicate, + 79, + 6, + 6, + 0, // Skip to: 2458 + /* 916 */ MCD_OPC_Decode, + 202, + 15, + 207, + 1, // Opcode: MAX_S + /* 921 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 936 + /* 926 */ MCD_OPC_CheckPredicate, + 79, + 247, + 5, + 0, // Skip to: 2458 + /* 931 */ MCD_OPC_Decode, + 245, + 15, + 207, + 1, // Opcode: MINA_S + /* 936 */ MCD_OPC_FilterValue, + 31, + 237, + 5, + 0, // Skip to: 2458 + /* 941 */ MCD_OPC_CheckPredicate, + 79, + 232, + 5, + 0, // Skip to: 2458 + /* 946 */ MCD_OPC_Decode, + 186, + 15, + 207, + 1, // Opcode: MAXA_S + /* 951 */ MCD_OPC_FilterValue, + 17, + 182, + 0, + 0, // Skip to: 1138 + /* 956 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 959 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 974 + /* 964 */ MCD_OPC_CheckPredicate, + 79, + 209, + 5, + 0, // Skip to: 2458 + /* 969 */ MCD_OPC_Decode, + 165, + 19, + 218, + 2, // Opcode: SEL_D + /* 974 */ MCD_OPC_FilterValue, + 20, + 10, + 0, + 0, // Skip to: 989 + /* 979 */ MCD_OPC_CheckPredicate, + 79, + 194, + 5, + 0, // Skip to: 2458 + /* 984 */ MCD_OPC_Decode, + 153, + 19, + 219, + 2, // Opcode: SELEQZ_D + /* 989 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 1004 + /* 994 */ MCD_OPC_CheckPredicate, + 79, + 179, + 5, + 0, // Skip to: 2458 + /* 999 */ MCD_OPC_Decode, + 160, + 19, + 219, + 2, // Opcode: SELNEZ_D + /* 1004 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 1019 + /* 1009 */ MCD_OPC_CheckPredicate, + 79, + 164, + 5, + 0, // Skip to: 2458 + /* 1014 */ MCD_OPC_Decode, + 152, + 15, + 218, + 2, // Opcode: MADDF_D + /* 1019 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 1034 + /* 1024 */ MCD_OPC_CheckPredicate, + 79, + 149, + 5, + 0, // Skip to: 2458 + /* 1029 */ MCD_OPC_Decode, + 203, + 16, + 218, + 2, // Opcode: MSUBF_D + /* 1034 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 1056 + /* 1039 */ MCD_OPC_CheckPredicate, + 79, + 134, + 5, + 0, // Skip to: 2458 + /* 1044 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 127, + 5, + 0, // Skip to: 2458 + /* 1051 */ MCD_OPC_Decode, + 197, + 18, + 219, + 1, // Opcode: RINT_D + /* 1056 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 1078 + /* 1061 */ MCD_OPC_CheckPredicate, + 79, + 112, + 5, + 0, // Skip to: 2458 + /* 1066 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 105, + 5, + 0, // Skip to: 2458 + /* 1073 */ MCD_OPC_Decode, + 182, + 8, + 219, + 1, // Opcode: CLASS_D + /* 1078 */ MCD_OPC_FilterValue, + 28, + 10, + 0, + 0, // Skip to: 1093 + /* 1083 */ MCD_OPC_CheckPredicate, + 79, + 90, + 5, + 0, // Skip to: 2458 + /* 1088 */ MCD_OPC_Decode, + 131, + 16, + 219, + 2, // Opcode: MIN_D + /* 1093 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 1108 + /* 1098 */ MCD_OPC_CheckPredicate, + 79, + 75, + 5, + 0, // Skip to: 2458 + /* 1103 */ MCD_OPC_Decode, + 200, + 15, + 219, + 2, // Opcode: MAX_D + /* 1108 */ MCD_OPC_FilterValue, + 30, + 10, + 0, + 0, // Skip to: 1123 + /* 1113 */ MCD_OPC_CheckPredicate, + 79, + 60, + 5, + 0, // Skip to: 2458 + /* 1118 */ MCD_OPC_Decode, + 243, + 15, + 219, + 2, // Opcode: MINA_D + /* 1123 */ MCD_OPC_FilterValue, + 31, + 50, + 5, + 0, // Skip to: 2458 + /* 1128 */ MCD_OPC_CheckPredicate, + 79, + 45, + 5, + 0, // Skip to: 2458 + /* 1133 */ MCD_OPC_Decode, + 184, + 15, + 219, + 2, // Opcode: MAXA_D + /* 1138 */ MCD_OPC_FilterValue, + 20, + 243, + 0, + 0, // Skip to: 1386 + /* 1143 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1146 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1161 + /* 1151 */ MCD_OPC_CheckPredicate, + 79, + 22, + 5, + 0, // Skip to: 2458 + /* 1156 */ MCD_OPC_Decode, + 253, + 8, + 220, + 2, // Opcode: CMP_F_S + /* 1161 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1176 + /* 1166 */ MCD_OPC_CheckPredicate, + 79, + 7, + 5, + 0, // Skip to: 2458 + /* 1171 */ MCD_OPC_Decode, + 184, + 9, + 220, + 2, // Opcode: CMP_UN_S + /* 1176 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1191 + /* 1181 */ MCD_OPC_CheckPredicate, + 79, + 248, + 4, + 0, // Skip to: 2458 + /* 1186 */ MCD_OPC_Decode, + 250, + 8, + 220, + 2, // Opcode: CMP_EQ_S + /* 1191 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1206 + /* 1196 */ MCD_OPC_CheckPredicate, + 79, + 233, + 4, + 0, // Skip to: 2458 + /* 1201 */ MCD_OPC_Decode, + 172, + 9, + 220, + 2, // Opcode: CMP_UEQ_S + /* 1206 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 1221 + /* 1211 */ MCD_OPC_CheckPredicate, + 79, + 218, + 4, + 0, // Skip to: 2458 + /* 1216 */ MCD_OPC_Decode, + 136, + 9, + 220, + 2, // Opcode: CMP_LT_S + /* 1221 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1236 + /* 1226 */ MCD_OPC_CheckPredicate, + 79, + 203, + 4, + 0, // Skip to: 2458 + /* 1231 */ MCD_OPC_Decode, + 180, + 9, + 220, + 2, // Opcode: CMP_ULT_S + /* 1236 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 1251 + /* 1241 */ MCD_OPC_CheckPredicate, + 79, + 188, + 4, + 0, // Skip to: 2458 + /* 1246 */ MCD_OPC_Decode, + 130, + 9, + 220, + 2, // Opcode: CMP_LE_S + /* 1251 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1266 + /* 1256 */ MCD_OPC_CheckPredicate, + 79, + 173, + 4, + 0, // Skip to: 2458 + /* 1261 */ MCD_OPC_Decode, + 176, + 9, + 220, + 2, // Opcode: CMP_ULE_S + /* 1266 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1281 + /* 1271 */ MCD_OPC_CheckPredicate, + 79, + 158, + 4, + 0, // Skip to: 2458 + /* 1276 */ MCD_OPC_Decode, + 140, + 9, + 220, + 2, // Opcode: CMP_SAF_S + /* 1281 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1296 + /* 1286 */ MCD_OPC_CheckPredicate, + 79, + 143, + 4, + 0, // Skip to: 2458 + /* 1291 */ MCD_OPC_Decode, + 168, + 9, + 220, + 2, // Opcode: CMP_SUN_S + /* 1296 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1311 + /* 1301 */ MCD_OPC_CheckPredicate, + 79, + 128, + 4, + 0, // Skip to: 2458 + /* 1306 */ MCD_OPC_Decode, + 144, + 9, + 220, + 2, // Opcode: CMP_SEQ_S + /* 1311 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1326 + /* 1316 */ MCD_OPC_CheckPredicate, + 79, + 113, + 4, + 0, // Skip to: 2458 + /* 1321 */ MCD_OPC_Decode, + 156, + 9, + 220, + 2, // Opcode: CMP_SUEQ_S + /* 1326 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 1341 + /* 1331 */ MCD_OPC_CheckPredicate, + 79, + 98, + 4, + 0, // Skip to: 2458 + /* 1336 */ MCD_OPC_Decode, + 152, + 9, + 220, + 2, // Opcode: CMP_SLT_S + /* 1341 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1356 + /* 1346 */ MCD_OPC_CheckPredicate, + 79, + 83, + 4, + 0, // Skip to: 2458 + /* 1351 */ MCD_OPC_Decode, + 164, + 9, + 220, + 2, // Opcode: CMP_SULT_S + /* 1356 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1371 + /* 1361 */ MCD_OPC_CheckPredicate, + 79, + 68, + 4, + 0, // Skip to: 2458 + /* 1366 */ MCD_OPC_Decode, + 148, + 9, + 220, + 2, // Opcode: CMP_SLE_S + /* 1371 */ MCD_OPC_FilterValue, + 15, + 58, + 4, + 0, // Skip to: 2458 + /* 1376 */ MCD_OPC_CheckPredicate, + 79, + 53, + 4, + 0, // Skip to: 2458 + /* 1381 */ MCD_OPC_Decode, + 160, + 9, + 220, + 2, // Opcode: CMP_SULE_S + /* 1386 */ MCD_OPC_FilterValue, + 21, + 43, + 4, + 0, // Skip to: 2458 + /* 1391 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1394 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1409 + /* 1399 */ MCD_OPC_CheckPredicate, + 79, + 30, + 4, + 0, // Skip to: 2458 + /* 1404 */ MCD_OPC_Decode, + 252, + 8, + 221, + 2, // Opcode: CMP_F_D + /* 1409 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1424 + /* 1414 */ MCD_OPC_CheckPredicate, + 79, + 15, + 4, + 0, // Skip to: 2458 + /* 1419 */ MCD_OPC_Decode, + 182, + 9, + 221, + 2, // Opcode: CMP_UN_D + /* 1424 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1439 + /* 1429 */ MCD_OPC_CheckPredicate, + 79, + 0, + 4, + 0, // Skip to: 2458 + /* 1434 */ MCD_OPC_Decode, + 246, + 8, + 221, + 2, // Opcode: CMP_EQ_D + /* 1439 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1454 + /* 1444 */ MCD_OPC_CheckPredicate, + 79, + 241, + 3, + 0, // Skip to: 2458 + /* 1449 */ MCD_OPC_Decode, + 170, + 9, + 221, + 2, // Opcode: CMP_UEQ_D + /* 1454 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 1469 + /* 1459 */ MCD_OPC_CheckPredicate, + 79, + 226, + 3, + 0, // Skip to: 2458 + /* 1464 */ MCD_OPC_Decode, + 132, + 9, + 221, + 2, // Opcode: CMP_LT_D + /* 1469 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1484 + /* 1474 */ MCD_OPC_CheckPredicate, + 79, + 211, + 3, + 0, // Skip to: 2458 + /* 1479 */ MCD_OPC_Decode, + 178, + 9, + 221, + 2, // Opcode: CMP_ULT_D + /* 1484 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 1499 + /* 1489 */ MCD_OPC_CheckPredicate, + 79, + 196, + 3, + 0, // Skip to: 2458 + /* 1494 */ MCD_OPC_Decode, + 254, + 8, + 221, + 2, // Opcode: CMP_LE_D + /* 1499 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1514 + /* 1504 */ MCD_OPC_CheckPredicate, + 79, + 181, + 3, + 0, // Skip to: 2458 + /* 1509 */ MCD_OPC_Decode, + 174, + 9, + 221, + 2, // Opcode: CMP_ULE_D + /* 1514 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1529 + /* 1519 */ MCD_OPC_CheckPredicate, + 79, + 166, + 3, + 0, // Skip to: 2458 + /* 1524 */ MCD_OPC_Decode, + 138, + 9, + 221, + 2, // Opcode: CMP_SAF_D + /* 1529 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1544 + /* 1534 */ MCD_OPC_CheckPredicate, + 79, + 151, + 3, + 0, // Skip to: 2458 + /* 1539 */ MCD_OPC_Decode, + 166, + 9, + 221, + 2, // Opcode: CMP_SUN_D + /* 1544 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1559 + /* 1549 */ MCD_OPC_CheckPredicate, + 79, + 136, + 3, + 0, // Skip to: 2458 + /* 1554 */ MCD_OPC_Decode, + 142, + 9, + 221, + 2, // Opcode: CMP_SEQ_D + /* 1559 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1574 + /* 1564 */ MCD_OPC_CheckPredicate, + 79, + 121, + 3, + 0, // Skip to: 2458 + /* 1569 */ MCD_OPC_Decode, + 154, + 9, + 221, + 2, // Opcode: CMP_SUEQ_D + /* 1574 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 1589 + /* 1579 */ MCD_OPC_CheckPredicate, + 79, + 106, + 3, + 0, // Skip to: 2458 + /* 1584 */ MCD_OPC_Decode, + 150, + 9, + 221, + 2, // Opcode: CMP_SLT_D + /* 1589 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1604 + /* 1594 */ MCD_OPC_CheckPredicate, + 79, + 91, + 3, + 0, // Skip to: 2458 + /* 1599 */ MCD_OPC_Decode, + 162, + 9, + 221, + 2, // Opcode: CMP_SULT_D + /* 1604 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1619 + /* 1609 */ MCD_OPC_CheckPredicate, + 79, + 76, + 3, + 0, // Skip to: 2458 + /* 1614 */ MCD_OPC_Decode, + 146, + 9, + 221, + 2, // Opcode: CMP_SLE_D + /* 1619 */ MCD_OPC_FilterValue, + 15, + 66, + 3, + 0, // Skip to: 2458 + /* 1624 */ MCD_OPC_CheckPredicate, + 79, + 61, + 3, + 0, // Skip to: 2458 + /* 1629 */ MCD_OPC_Decode, + 158, + 9, + 221, + 2, // Opcode: CMP_SULE_D + /* 1634 */ MCD_OPC_FilterValue, + 18, + 93, + 0, + 0, // Skip to: 1732 + /* 1639 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 1642 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1657 + /* 1647 */ MCD_OPC_CheckPredicate, + 76, + 38, + 3, + 0, // Skip to: 2458 + /* 1652 */ MCD_OPC_Decode, + 223, + 6, + 222, + 2, // Opcode: BC2EQZ + /* 1657 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1672 + /* 1662 */ MCD_OPC_CheckPredicate, + 76, + 23, + 3, + 0, // Skip to: 2458 + /* 1667 */ MCD_OPC_Decode, + 234, + 14, + 223, + 2, // Opcode: LWC2_R6 + /* 1672 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1687 + /* 1677 */ MCD_OPC_CheckPredicate, + 76, + 8, + 3, + 0, // Skip to: 2458 + /* 1682 */ MCD_OPC_Decode, + 141, + 21, + 223, + 2, // Opcode: SWC2_R6 + /* 1687 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1702 + /* 1692 */ MCD_OPC_CheckPredicate, + 76, + 249, + 2, + 0, // Skip to: 2458 + /* 1697 */ MCD_OPC_Decode, + 227, + 6, + 222, + 2, // Opcode: BC2NEZ + /* 1702 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1717 + /* 1707 */ MCD_OPC_CheckPredicate, + 76, + 234, + 2, + 0, // Skip to: 2458 + /* 1712 */ MCD_OPC_Decode, + 174, + 14, + 223, + 2, // Opcode: LDC2_R6 + /* 1717 */ MCD_OPC_FilterValue, + 15, + 224, + 2, + 0, // Skip to: 2458 + /* 1722 */ MCD_OPC_CheckPredicate, + 76, + 219, + 2, + 0, // Skip to: 2458 + /* 1727 */ MCD_OPC_Decode, + 137, + 19, + 223, + 2, // Opcode: SDC2_R6 + /* 1732 */ MCD_OPC_FilterValue, + 22, + 10, + 0, + 0, // Skip to: 1747 + /* 1737 */ MCD_OPC_CheckPredicate, + 76, + 204, + 2, + 0, // Skip to: 2458 + /* 1742 */ MCD_OPC_Decode, + 145, + 7, + 224, + 2, // Opcode: BGEZC + /* 1747 */ MCD_OPC_FilterValue, + 23, + 10, + 0, + 0, // Skip to: 1762 + /* 1752 */ MCD_OPC_CheckPredicate, + 76, + 189, + 2, + 0, // Skip to: 2458 + /* 1757 */ MCD_OPC_Decode, + 202, + 7, + 225, + 2, // Opcode: BLTZC + /* 1762 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 1777 + /* 1767 */ MCD_OPC_CheckPredicate, + 76, + 174, + 2, + 0, // Skip to: 2458 + /* 1772 */ MCD_OPC_Decode, + 213, + 7, + 226, + 2, // Opcode: BNEC + /* 1777 */ MCD_OPC_FilterValue, + 29, + 10, + 0, + 0, // Skip to: 1792 + /* 1782 */ MCD_OPC_CheckPredicate, + 77, + 159, + 2, + 0, // Skip to: 2458 + /* 1787 */ MCD_OPC_Decode, + 220, + 10, + 227, + 2, // Opcode: DAUI + /* 1792 */ MCD_OPC_FilterValue, + 31, + 135, + 1, + 0, // Skip to: 2188 + /* 1797 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1800 */ MCD_OPC_FilterValue, + 15, + 123, + 0, + 0, // Skip to: 1928 + /* 1805 */ MCD_OPC_ExtractField, + 6, + 10, // Inst{15-6} ... + /* 1808 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 1823 + /* 1813 */ MCD_OPC_CheckPredicate, + 80, + 128, + 2, + 0, // Skip to: 2458 + /* 1818 */ MCD_OPC_Decode, + 193, + 9, + 228, + 2, // Opcode: CRC32B + /* 1823 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1838 + /* 1828 */ MCD_OPC_CheckPredicate, + 80, + 113, + 2, + 0, // Skip to: 2458 + /* 1833 */ MCD_OPC_Decode, + 199, + 9, + 228, + 2, // Opcode: CRC32H + /* 1838 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1853 + /* 1843 */ MCD_OPC_CheckPredicate, + 80, + 98, + 2, + 0, // Skip to: 2458 + /* 1848 */ MCD_OPC_Decode, + 200, + 9, + 228, + 2, // Opcode: CRC32W + /* 1853 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1868 + /* 1858 */ MCD_OPC_CheckPredicate, + 81, + 83, + 2, + 0, // Skip to: 2458 + /* 1863 */ MCD_OPC_Decode, + 198, + 9, + 228, + 2, // Opcode: CRC32D + /* 1868 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 1883 + /* 1873 */ MCD_OPC_CheckPredicate, + 80, + 68, + 2, + 0, // Skip to: 2458 + /* 1878 */ MCD_OPC_Decode, + 194, + 9, + 228, + 2, // Opcode: CRC32CB + /* 1883 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1898 + /* 1888 */ MCD_OPC_CheckPredicate, + 80, + 53, + 2, + 0, // Skip to: 2458 + /* 1893 */ MCD_OPC_Decode, + 196, + 9, + 228, + 2, // Opcode: CRC32CH + /* 1898 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 1913 + /* 1903 */ MCD_OPC_CheckPredicate, + 80, + 38, + 2, + 0, // Skip to: 2458 + /* 1908 */ MCD_OPC_Decode, + 197, + 9, + 228, + 2, // Opcode: CRC32CW + /* 1913 */ MCD_OPC_FilterValue, + 7, + 28, + 2, + 0, // Skip to: 2458 + /* 1918 */ MCD_OPC_CheckPredicate, + 81, + 23, + 2, + 0, // Skip to: 2458 + /* 1923 */ MCD_OPC_Decode, + 195, + 9, + 228, + 2, // Opcode: CRC32CD + /* 1928 */ MCD_OPC_FilterValue, + 32, + 47, + 0, + 0, // Skip to: 1980 + /* 1933 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 1936 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 1965 + /* 1941 */ MCD_OPC_CheckPredicate, + 75, + 0, + 2, + 0, // Skip to: 2458 + /* 1946 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 249, + 1, + 0, // Skip to: 2458 + /* 1953 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 242, + 1, + 0, // Skip to: 2458 + /* 1960 */ MCD_OPC_Decode, + 177, + 7, + 193, + 2, // Opcode: BITSWAP + /* 1965 */ MCD_OPC_FilterValue, + 2, + 232, + 1, + 0, // Skip to: 2458 + /* 1970 */ MCD_OPC_CheckPredicate, + 75, + 227, + 1, + 0, // Skip to: 2458 + /* 1975 */ MCD_OPC_Decode, + 141, + 6, + 229, + 2, // Opcode: ALIGN + /* 1980 */ MCD_OPC_FilterValue, + 36, + 47, + 0, + 0, // Skip to: 2032 + /* 1985 */ MCD_OPC_ExtractField, + 9, + 2, // Inst{10-9} ... + /* 1988 */ MCD_OPC_FilterValue, + 0, + 24, + 0, + 0, // Skip to: 2017 + /* 1993 */ MCD_OPC_CheckPredicate, + 77, + 204, + 1, + 0, // Skip to: 2458 + /* 1998 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 197, + 1, + 0, // Skip to: 2458 + /* 2005 */ MCD_OPC_CheckField, + 6, + 3, + 0, + 190, + 1, + 0, // Skip to: 2458 + /* 2012 */ MCD_OPC_Decode, + 221, + 10, + 230, + 2, // Opcode: DBITSWAP + /* 2017 */ MCD_OPC_FilterValue, + 1, + 180, + 1, + 0, // Skip to: 2458 + /* 2022 */ MCD_OPC_CheckPredicate, + 77, + 175, + 1, + 0, // Skip to: 2458 + /* 2027 */ MCD_OPC_Decode, + 218, + 10, + 231, + 2, // Opcode: DALIGN + /* 2032 */ MCD_OPC_FilterValue, + 37, + 17, + 0, + 0, // Skip to: 2054 + /* 2037 */ MCD_OPC_CheckPredicate, + 76, + 160, + 1, + 0, // Skip to: 2458 + /* 2042 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 153, + 1, + 0, // Skip to: 2458 + /* 2049 */ MCD_OPC_Decode, + 154, + 8, + 198, + 2, // Opcode: CACHE_R6 + /* 2054 */ MCD_OPC_FilterValue, + 38, + 10, + 0, + 0, // Skip to: 2069 + /* 2059 */ MCD_OPC_CheckPredicate, + 82, + 138, + 1, + 0, // Skip to: 2458 + /* 2064 */ MCD_OPC_Decode, + 251, + 18, + 232, + 2, // Opcode: SC_R6 + /* 2069 */ MCD_OPC_FilterValue, + 39, + 10, + 0, + 0, // Skip to: 2084 + /* 2074 */ MCD_OPC_CheckPredicate, + 75, + 123, + 1, + 0, // Skip to: 2458 + /* 2079 */ MCD_OPC_Decode, + 246, + 18, + 232, + 2, // Opcode: SCD_R6 + /* 2084 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 2106 + /* 2089 */ MCD_OPC_CheckPredicate, + 76, + 108, + 1, + 0, // Skip to: 2458 + /* 2094 */ MCD_OPC_CheckField, + 6, + 1, + 0, + 101, + 1, + 0, // Skip to: 2458 + /* 2101 */ MCD_OPC_Decode, + 169, + 18, + 198, + 2, // Opcode: PREF_R6 + /* 2106 */ MCD_OPC_FilterValue, + 54, + 10, + 0, + 0, // Skip to: 2121 + /* 2111 */ MCD_OPC_CheckPredicate, + 82, + 86, + 1, + 0, // Skip to: 2458 + /* 2116 */ MCD_OPC_Decode, + 216, + 14, + 232, + 2, // Opcode: LL_R6 + /* 2121 */ MCD_OPC_FilterValue, + 55, + 10, + 0, + 0, // Skip to: 2136 + /* 2126 */ MCD_OPC_CheckPredicate, + 77, + 71, + 1, + 0, // Skip to: 2458 + /* 2131 */ MCD_OPC_Decode, + 211, + 14, + 232, + 2, // Opcode: LLD_R6 + /* 2136 */ MCD_OPC_FilterValue, + 61, + 61, + 1, + 0, // Skip to: 2458 + /* 2141 */ MCD_OPC_ExtractField, + 6, + 2, // Inst{7-6} ... + /* 2144 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 2166 + /* 2149 */ MCD_OPC_CheckPredicate, + 83, + 48, + 1, + 0, // Skip to: 2458 + /* 2154 */ MCD_OPC_CheckField, + 10, + 11, + 0, + 41, + 1, + 0, // Skip to: 2458 + /* 2161 */ MCD_OPC_Decode, + 191, + 13, + 175, + 1, // Opcode: GINVI + /* 2166 */ MCD_OPC_FilterValue, + 2, + 31, + 1, + 0, // Skip to: 2458 + /* 2171 */ MCD_OPC_CheckPredicate, + 83, + 26, + 1, + 0, // Skip to: 2458 + /* 2176 */ MCD_OPC_CheckField, + 10, + 11, + 0, + 19, + 1, + 0, // Skip to: 2458 + /* 2183 */ MCD_OPC_Decode, + 193, + 13, + 233, + 2, // Opcode: GINVT + /* 2188 */ MCD_OPC_FilterValue, + 50, + 10, + 0, + 0, // Skip to: 2203 + /* 2193 */ MCD_OPC_CheckPredicate, + 76, + 4, + 1, + 0, // Skip to: 2458 + /* 2198 */ MCD_OPC_Decode, + 209, + 6, + 234, + 2, // Opcode: BC + /* 2203 */ MCD_OPC_FilterValue, + 53, + 27, + 0, + 0, // Skip to: 2235 + /* 2208 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 2225 + /* 2213 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 2225 + /* 2220 */ MCD_OPC_Decode, + 156, + 7, + 169, + 1, // Opcode: BGTZC_MMR6 + /* 2225 */ MCD_OPC_CheckPredicate, + 24, + 228, + 0, + 0, // Skip to: 2458 + /* 2230 */ MCD_OPC_Decode, + 204, + 7, + 169, + 1, // Opcode: BLTZC_MMR6 + /* 2235 */ MCD_OPC_FilterValue, + 54, + 26, + 0, + 0, // Skip to: 2266 + /* 2240 */ MCD_OPC_CheckPredicate, + 75, + 11, + 0, + 0, // Skip to: 2256 + /* 2245 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 2256 + /* 2252 */ MCD_OPC_Decode, + 130, + 14, + 92, // Opcode: JIC + /* 2256 */ MCD_OPC_CheckPredicate, + 76, + 197, + 0, + 0, // Skip to: 2458 + /* 2261 */ MCD_OPC_Decode, + 253, + 6, + 235, + 2, // Opcode: BEQZC + /* 2266 */ MCD_OPC_FilterValue, + 58, + 10, + 0, + 0, // Skip to: 2281 + /* 2271 */ MCD_OPC_CheckPredicate, + 75, + 182, + 0, + 0, // Skip to: 2458 + /* 2276 */ MCD_OPC_Decode, + 201, + 6, + 234, + 2, // Opcode: BALC + /* 2281 */ MCD_OPC_FilterValue, + 59, + 109, + 0, + 0, // Skip to: 2395 + /* 2286 */ MCD_OPC_ExtractField, + 19, + 2, // Inst{20-19} ... + /* 2289 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2304 + /* 2294 */ MCD_OPC_CheckPredicate, + 75, + 159, + 0, + 0, // Skip to: 2458 + /* 2299 */ MCD_OPC_Decode, + 195, + 5, + 163, + 1, // Opcode: ADDIUPC + /* 2304 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2319 + /* 2309 */ MCD_OPC_CheckPredicate, + 75, + 144, + 0, + 0, // Skip to: 2458 + /* 2314 */ MCD_OPC_Decode, + 249, + 14, + 163, + 1, // Opcode: LWPC + /* 2319 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2334 + /* 2324 */ MCD_OPC_CheckPredicate, + 84, + 129, + 0, + 0, // Skip to: 2458 + /* 2329 */ MCD_OPC_Decode, + 130, + 15, + 163, + 1, // Opcode: LWUPC + /* 2334 */ MCD_OPC_FilterValue, + 3, + 119, + 0, + 0, // Skip to: 2458 + /* 2339 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 2342 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 2357 + /* 2347 */ MCD_OPC_CheckPredicate, + 84, + 106, + 0, + 0, // Skip to: 2458 + /* 2352 */ MCD_OPC_Decode, + 181, + 14, + 236, + 2, // Opcode: LDPC + /* 2357 */ MCD_OPC_FilterValue, + 1, + 96, + 0, + 0, // Skip to: 2458 + /* 2362 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 2365 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2380 + /* 2370 */ MCD_OPC_CheckPredicate, + 75, + 83, + 0, + 0, // Skip to: 2458 + /* 2375 */ MCD_OPC_Decode, + 170, + 6, + 164, + 1, // Opcode: AUIPC + /* 2380 */ MCD_OPC_FilterValue, + 3, + 73, + 0, + 0, // Skip to: 2458 + /* 2385 */ MCD_OPC_CheckPredicate, + 75, + 68, + 0, + 0, // Skip to: 2458 + /* 2390 */ MCD_OPC_Decode, + 143, + 6, + 164, + 1, // Opcode: ALUIPC + /* 2395 */ MCD_OPC_FilterValue, + 61, + 27, + 0, + 0, // Skip to: 2427 + /* 2400 */ MCD_OPC_CheckPredicate, + 24, + 12, + 0, + 0, // Skip to: 2417 + /* 2405 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 5, + 0, + 0, // Skip to: 2417 + /* 2412 */ MCD_OPC_Decode, + 185, + 7, + 171, + 1, // Opcode: BLEZC_MMR6 + /* 2417 */ MCD_OPC_CheckPredicate, + 24, + 36, + 0, + 0, // Skip to: 2458 + /* 2422 */ MCD_OPC_Decode, + 147, + 7, + 171, + 1, // Opcode: BGEZC_MMR6 + /* 2427 */ MCD_OPC_FilterValue, + 62, + 26, + 0, + 0, // Skip to: 2458 + /* 2432 */ MCD_OPC_CheckPredicate, + 75, + 11, + 0, + 0, // Skip to: 2448 + /* 2437 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 2448 + /* 2444 */ MCD_OPC_Decode, + 255, + 13, + 92, // Opcode: JIALC + /* 2448 */ MCD_OPC_CheckPredicate, + 76, + 5, + 0, + 0, // Skip to: 2458 + /* 2453 */ MCD_OPC_Decode, + 228, + 7, + 235, + 2, // Opcode: BNEZC + /* 2458 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMips32r6_64r6_Ambiguous32[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 6, + 27, + 0, + 0, // Skip to: 35 + /* 8 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 25 + /* 13 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 25 + /* 20 */ MCD_OPC_Decode, + 181, + 7, + 212, + 2, // Opcode: BLEZALC + /* 25 */ MCD_OPC_CheckPredicate, + 76, + 165, + 0, + 0, // Skip to: 195 + /* 30 */ MCD_OPC_Decode, + 134, + 7, + 212, + 2, // Opcode: BGEUC + /* 35 */ MCD_OPC_FilterValue, + 7, + 27, + 0, + 0, // Skip to: 67 + /* 40 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 57 + /* 45 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 57 + /* 52 */ MCD_OPC_Decode, + 152, + 7, + 213, + 2, // Opcode: BGTZALC + /* 57 */ MCD_OPC_CheckPredicate, + 76, + 133, + 0, + 0, // Skip to: 195 + /* 62 */ MCD_OPC_Decode, + 191, + 7, + 213, + 2, // Opcode: BLTUC + /* 67 */ MCD_OPC_FilterValue, + 8, + 27, + 0, + 0, // Skip to: 99 + /* 72 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 89 + /* 77 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 89 + /* 84 */ MCD_OPC_Decode, + 251, + 6, + 226, + 2, // Opcode: BEQZALC + /* 89 */ MCD_OPC_CheckPredicate, + 76, + 101, + 0, + 0, // Skip to: 195 + /* 94 */ MCD_OPC_Decode, + 241, + 7, + 214, + 2, // Opcode: BOVC + /* 99 */ MCD_OPC_FilterValue, + 22, + 27, + 0, + 0, // Skip to: 131 + /* 104 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 121 + /* 109 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 121 + /* 116 */ MCD_OPC_Decode, + 183, + 7, + 224, + 2, // Opcode: BLEZC + /* 121 */ MCD_OPC_CheckPredicate, + 76, + 69, + 0, + 0, // Skip to: 195 + /* 126 */ MCD_OPC_Decode, + 131, + 7, + 224, + 2, // Opcode: BGEC + /* 131 */ MCD_OPC_FilterValue, + 23, + 27, + 0, + 0, // Skip to: 163 + /* 136 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 153 + /* 141 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 153 + /* 148 */ MCD_OPC_Decode, + 154, + 7, + 225, + 2, // Opcode: BGTZC + /* 153 */ MCD_OPC_CheckPredicate, + 76, + 37, + 0, + 0, // Skip to: 195 + /* 158 */ MCD_OPC_Decode, + 188, + 7, + 225, + 2, // Opcode: BLTC + /* 163 */ MCD_OPC_FilterValue, + 24, + 27, + 0, + 0, // Skip to: 195 + /* 168 */ MCD_OPC_CheckPredicate, + 76, + 12, + 0, + 0, // Skip to: 185 + /* 173 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 185 + /* 180 */ MCD_OPC_Decode, + 226, + 7, + 226, + 2, // Opcode: BNEZALC + /* 185 */ MCD_OPC_CheckPredicate, + 76, + 5, + 0, + 0, // Skip to: 195 + /* 190 */ MCD_OPC_Decode, + 234, + 7, + 226, + 2, // Opcode: BNVC + /* 195 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMips32r6_64r6_BranchZero32[] = { + /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, 22, 10, 0, 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, 85, 20, 0, 0, // Skip to: 33 + /* 13 */ MCD_OPC_Decode, 146, 7, 224, 2, // Opcode: BGEZC64 + /* 18 */ MCD_OPC_FilterValue, 23, 10, 0, 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, 85, 5, 0, 0, // Skip to: 33 + /* 28 */ MCD_OPC_Decode, 203, 7, 225, 2, // Opcode: BLTZC64 + /* 33 */ MCD_OPC_Fail, 0}; static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = { -/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... -/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22 -/* 7 */ MCD_OPC_CheckPredicate, 39, 30, 0, // Skip to: 41 -/* 11 */ MCD_OPC_CheckField, 26, 6, 0, 24, 0, // Skip to: 41 -/* 17 */ MCD_OPC_Decode, 175, 11, 224, 1, // Opcode: SELEQZ64 -/* 22 */ MCD_OPC_FilterValue, 55, 15, 0, // Skip to: 41 -/* 26 */ MCD_OPC_CheckPredicate, 39, 11, 0, // Skip to: 41 -/* 30 */ MCD_OPC_CheckField, 26, 6, 0, 5, 0, // Skip to: 41 -/* 36 */ MCD_OPC_Decode, 179, 11, 224, 1, // Opcode: SELNEZ64 -/* 41 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 53, + 0, + 0, // Skip to: 61 + /* 8 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 11 */ MCD_OPC_FilterValue, + 53, + 9, + 0, + 0, // Skip to: 25 + /* 16 */ MCD_OPC_CheckPredicate, + 86, + 226, + 0, + 0, // Skip to: 247 + /* 21 */ MCD_OPC_Decode, + 152, + 19, + 12, // Opcode: SELEQZ64 + /* 25 */ MCD_OPC_FilterValue, + 55, + 9, + 0, + 0, // Skip to: 39 + /* 30 */ MCD_OPC_CheckPredicate, + 86, + 212, + 0, + 0, // Skip to: 247 + /* 35 */ MCD_OPC_Decode, + 159, + 19, + 12, // Opcode: SELNEZ64 + /* 39 */ MCD_OPC_FilterValue, + 137, + 8, + 202, + 0, + 0, // Skip to: 247 + /* 45 */ MCD_OPC_CheckPredicate, + 75, + 197, + 0, + 0, // Skip to: 247 + /* 50 */ MCD_OPC_CheckField, + 11, + 10, + 0, + 190, + 0, + 0, // Skip to: 247 + /* 57 */ MCD_OPC_Decode, + 142, + 14, + 13, // Opcode: JR_HB64_R6 + /* 61 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 76 + /* 66 */ MCD_OPC_CheckPredicate, + 85, + 176, + 0, + 0, // Skip to: 247 + /* 71 */ MCD_OPC_Decode, + 135, + 7, + 212, + 2, // Opcode: BGEUC64 + /* 76 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 91 + /* 81 */ MCD_OPC_CheckPredicate, + 85, + 161, + 0, + 0, // Skip to: 247 + /* 86 */ MCD_OPC_Decode, + 192, + 7, + 213, + 2, // Opcode: BLTUC64 + /* 91 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 106 + /* 96 */ MCD_OPC_CheckPredicate, + 85, + 146, + 0, + 0, // Skip to: 247 + /* 101 */ MCD_OPC_Decode, + 247, + 6, + 214, + 2, // Opcode: BEQC64 + /* 106 */ MCD_OPC_FilterValue, + 22, + 27, + 0, + 0, // Skip to: 138 + /* 111 */ MCD_OPC_CheckPredicate, + 85, + 12, + 0, + 0, // Skip to: 128 + /* 116 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 128 + /* 123 */ MCD_OPC_Decode, + 184, + 7, + 224, + 2, // Opcode: BLEZC64 + /* 128 */ MCD_OPC_CheckPredicate, + 85, + 114, + 0, + 0, // Skip to: 247 + /* 133 */ MCD_OPC_Decode, + 132, + 7, + 224, + 2, // Opcode: BGEC64 + /* 138 */ MCD_OPC_FilterValue, + 23, + 27, + 0, + 0, // Skip to: 170 + /* 143 */ MCD_OPC_CheckPredicate, + 85, + 12, + 0, + 0, // Skip to: 160 + /* 148 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 5, + 0, + 0, // Skip to: 160 + /* 155 */ MCD_OPC_Decode, + 155, + 7, + 225, + 2, // Opcode: BGTZC64 + /* 160 */ MCD_OPC_CheckPredicate, + 85, + 82, + 0, + 0, // Skip to: 247 + /* 165 */ MCD_OPC_Decode, + 189, + 7, + 225, + 2, // Opcode: BLTC64 + /* 170 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 185 + /* 175 */ MCD_OPC_CheckPredicate, + 85, + 67, + 0, + 0, // Skip to: 247 + /* 180 */ MCD_OPC_Decode, + 214, + 7, + 226, + 2, // Opcode: BNEC64 + /* 185 */ MCD_OPC_FilterValue, + 54, + 26, + 0, + 0, // Skip to: 216 + /* 190 */ MCD_OPC_CheckPredicate, + 85, + 11, + 0, + 0, // Skip to: 206 + /* 195 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 206 + /* 202 */ MCD_OPC_Decode, + 131, + 14, + 11, // Opcode: JIC64 + /* 206 */ MCD_OPC_CheckPredicate, + 85, + 36, + 0, + 0, // Skip to: 247 + /* 211 */ MCD_OPC_Decode, + 255, + 6, + 237, + 2, // Opcode: BEQZC64 + /* 216 */ MCD_OPC_FilterValue, + 62, + 26, + 0, + 0, // Skip to: 247 + /* 221 */ MCD_OPC_CheckPredicate, + 85, + 11, + 0, + 0, // Skip to: 237 + /* 226 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 4, + 0, + 0, // Skip to: 237 + /* 233 */ MCD_OPC_Decode, + 128, + 14, + 11, // Opcode: JIALC64 + /* 237 */ MCD_OPC_CheckPredicate, + 85, + 5, + 0, + 0, // Skip to: 247 + /* 242 */ MCD_OPC_Decode, + 230, + 7, + 237, + 2, // Opcode: BNEZC64 + /* 247 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMips32r6_64r6_PTR6432[] = { + /* 0 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 3 */ MCD_OPC_FilterValue, + 38, + 17, + 0, + 0, // Skip to: 25 + /* 8 */ MCD_OPC_CheckPredicate, + 87, + 34, + 0, + 0, // Skip to: 47 + /* 13 */ MCD_OPC_CheckField, + 26, + 6, + 31, + 27, + 0, + 0, // Skip to: 47 + /* 20 */ MCD_OPC_Decode, + 244, + 18, + 232, + 2, // Opcode: SC64_R6 + /* 25 */ MCD_OPC_FilterValue, + 54, + 17, + 0, + 0, // Skip to: 47 + /* 30 */ MCD_OPC_CheckPredicate, + 87, + 12, + 0, + 0, // Skip to: 47 + /* 35 */ MCD_OPC_CheckField, + 26, + 6, + 31, + 5, + 0, + 0, // Skip to: 47 + /* 42 */ MCD_OPC_Decode, + 209, + 14, + 232, + 2, // Opcode: LL64_R6 + /* 47 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableMips6432[] = { -/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375 -/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 29 -/* 14 */ MCD_OPC_CheckPredicate, 19, 42, 9, // Skip to: 2364 -/* 18 */ MCD_OPC_CheckField, 6, 5, 0, 36, 9, // Skip to: 2364 -/* 24 */ MCD_OPC_Decode, 255, 4, 252, 1, // Opcode: DSLLV -/* 29 */ MCD_OPC_FilterValue, 22, 29, 0, // Skip to: 62 -/* 33 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 49 -/* 40 */ MCD_OPC_CheckPredicate, 19, 16, 9, // Skip to: 2364 -/* 44 */ MCD_OPC_Decode, 133, 5, 252, 1, // Opcode: DSRLV -/* 49 */ MCD_OPC_FilterValue, 1, 7, 9, // Skip to: 2364 -/* 53 */ MCD_OPC_CheckPredicate, 40, 3, 9, // Skip to: 2364 -/* 57 */ MCD_OPC_Decode, 248, 4, 252, 1, // Opcode: DROTRV -/* 62 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 81 -/* 66 */ MCD_OPC_CheckPredicate, 19, 246, 8, // Skip to: 2364 -/* 70 */ MCD_OPC_CheckField, 6, 5, 0, 240, 8, // Skip to: 2364 -/* 76 */ MCD_OPC_Decode, 130, 5, 252, 1, // Opcode: DSRAV -/* 81 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 100 -/* 85 */ MCD_OPC_CheckPredicate, 41, 227, 8, // Skip to: 2364 -/* 89 */ MCD_OPC_CheckField, 6, 10, 0, 221, 8, // Skip to: 2364 -/* 95 */ MCD_OPC_Decode, 207, 4, 253, 1, // Opcode: DMULT -/* 100 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 119 -/* 104 */ MCD_OPC_CheckPredicate, 41, 208, 8, // Skip to: 2364 -/* 108 */ MCD_OPC_CheckField, 6, 10, 0, 202, 8, // Skip to: 2364 -/* 114 */ MCD_OPC_Decode, 208, 4, 253, 1, // Opcode: DMULTu -/* 119 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 138 -/* 123 */ MCD_OPC_CheckPredicate, 41, 189, 8, // Skip to: 2364 -/* 127 */ MCD_OPC_CheckField, 6, 10, 0, 183, 8, // Skip to: 2364 -/* 133 */ MCD_OPC_Decode, 250, 4, 253, 1, // Opcode: DSDIV -/* 138 */ MCD_OPC_FilterValue, 31, 15, 0, // Skip to: 157 -/* 142 */ MCD_OPC_CheckPredicate, 41, 170, 8, // Skip to: 2364 -/* 146 */ MCD_OPC_CheckField, 6, 10, 0, 164, 8, // Skip to: 2364 -/* 152 */ MCD_OPC_Decode, 136, 5, 253, 1, // Opcode: DUDIV -/* 157 */ MCD_OPC_FilterValue, 44, 15, 0, // Skip to: 176 -/* 161 */ MCD_OPC_CheckPredicate, 19, 151, 8, // Skip to: 2364 -/* 165 */ MCD_OPC_CheckField, 6, 5, 0, 145, 8, // Skip to: 2364 -/* 171 */ MCD_OPC_Decode, 159, 4, 224, 1, // Opcode: DADD -/* 176 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 195 -/* 180 */ MCD_OPC_CheckPredicate, 19, 132, 8, // Skip to: 2364 -/* 184 */ MCD_OPC_CheckField, 6, 5, 0, 126, 8, // Skip to: 2364 -/* 190 */ MCD_OPC_Decode, 162, 4, 224, 1, // Opcode: DADDu -/* 195 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 214 -/* 199 */ MCD_OPC_CheckPredicate, 19, 113, 8, // Skip to: 2364 -/* 203 */ MCD_OPC_CheckField, 6, 5, 0, 107, 8, // Skip to: 2364 -/* 209 */ MCD_OPC_Decode, 134, 5, 224, 1, // Opcode: DSUB -/* 214 */ MCD_OPC_FilterValue, 47, 15, 0, // Skip to: 233 -/* 218 */ MCD_OPC_CheckPredicate, 19, 94, 8, // Skip to: 2364 -/* 222 */ MCD_OPC_CheckField, 6, 5, 0, 88, 8, // Skip to: 2364 -/* 228 */ MCD_OPC_Decode, 135, 5, 224, 1, // Opcode: DSUBu -/* 233 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 252 -/* 237 */ MCD_OPC_CheckPredicate, 19, 75, 8, // Skip to: 2364 -/* 241 */ MCD_OPC_CheckField, 21, 5, 0, 69, 8, // Skip to: 2364 -/* 247 */ MCD_OPC_Decode, 252, 4, 254, 1, // Opcode: DSLL -/* 252 */ MCD_OPC_FilterValue, 58, 29, 0, // Skip to: 285 -/* 256 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 272 -/* 263 */ MCD_OPC_CheckPredicate, 19, 49, 8, // Skip to: 2364 -/* 267 */ MCD_OPC_Decode, 131, 5, 254, 1, // Opcode: DSRL -/* 272 */ MCD_OPC_FilterValue, 1, 40, 8, // Skip to: 2364 -/* 276 */ MCD_OPC_CheckPredicate, 40, 36, 8, // Skip to: 2364 -/* 280 */ MCD_OPC_Decode, 246, 4, 254, 1, // Opcode: DROTR -/* 285 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 304 -/* 289 */ MCD_OPC_CheckPredicate, 19, 23, 8, // Skip to: 2364 -/* 293 */ MCD_OPC_CheckField, 21, 5, 0, 17, 8, // Skip to: 2364 -/* 299 */ MCD_OPC_Decode, 128, 5, 254, 1, // Opcode: DSRA -/* 304 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 323 -/* 308 */ MCD_OPC_CheckPredicate, 19, 4, 8, // Skip to: 2364 -/* 312 */ MCD_OPC_CheckField, 21, 5, 0, 254, 7, // Skip to: 2364 -/* 318 */ MCD_OPC_Decode, 253, 4, 254, 1, // Opcode: DSLL32 -/* 323 */ MCD_OPC_FilterValue, 62, 29, 0, // Skip to: 356 -/* 327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 330 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 343 -/* 334 */ MCD_OPC_CheckPredicate, 19, 234, 7, // Skip to: 2364 -/* 338 */ MCD_OPC_Decode, 132, 5, 254, 1, // Opcode: DSRL32 -/* 343 */ MCD_OPC_FilterValue, 1, 225, 7, // Skip to: 2364 -/* 347 */ MCD_OPC_CheckPredicate, 40, 221, 7, // Skip to: 2364 -/* 351 */ MCD_OPC_Decode, 247, 4, 254, 1, // Opcode: DROTR32 -/* 356 */ MCD_OPC_FilterValue, 63, 212, 7, // Skip to: 2364 -/* 360 */ MCD_OPC_CheckPredicate, 19, 208, 7, // Skip to: 2364 -/* 364 */ MCD_OPC_CheckField, 21, 5, 0, 202, 7, // Skip to: 2364 -/* 370 */ MCD_OPC_Decode, 129, 5, 254, 1, // Opcode: DSRA32 -/* 375 */ MCD_OPC_FilterValue, 16, 41, 0, // Skip to: 420 -/* 379 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 382 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 401 -/* 386 */ MCD_OPC_CheckPredicate, 42, 182, 7, // Skip to: 2364 -/* 390 */ MCD_OPC_CheckField, 3, 8, 0, 176, 7, // Skip to: 2364 -/* 396 */ MCD_OPC_Decode, 196, 4, 255, 1, // Opcode: DMFC0 -/* 401 */ MCD_OPC_FilterValue, 5, 167, 7, // Skip to: 2364 -/* 405 */ MCD_OPC_CheckPredicate, 42, 163, 7, // Skip to: 2364 -/* 409 */ MCD_OPC_CheckField, 3, 8, 0, 157, 7, // Skip to: 2364 -/* 415 */ MCD_OPC_Decode, 201, 4, 255, 1, // Opcode: DMTC0 -/* 420 */ MCD_OPC_FilterValue, 17, 222, 3, // Skip to: 1414 -/* 424 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 427 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 485 -/* 431 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 434 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 453 -/* 438 */ MCD_OPC_CheckPredicate, 43, 130, 7, // Skip to: 2364 -/* 442 */ MCD_OPC_CheckField, 6, 5, 0, 124, 7, // Skip to: 2364 -/* 448 */ MCD_OPC_Decode, 184, 8, 128, 2, // Opcode: MFHC1_D64 -/* 453 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 472 -/* 457 */ MCD_OPC_CheckPredicate, 43, 111, 7, // Skip to: 2364 -/* 461 */ MCD_OPC_CheckField, 6, 5, 0, 105, 7, // Skip to: 2364 -/* 467 */ MCD_OPC_Decode, 174, 9, 129, 2, // Opcode: MTHC1_D64 -/* 472 */ MCD_OPC_FilterValue, 17, 96, 7, // Skip to: 2364 -/* 476 */ MCD_OPC_CheckPredicate, 44, 92, 7, // Skip to: 2364 -/* 480 */ MCD_OPC_Decode, 172, 5, 233, 1, // Opcode: FADD_D64 -/* 485 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 504 -/* 489 */ MCD_OPC_CheckPredicate, 44, 79, 7, // Skip to: 2364 -/* 493 */ MCD_OPC_CheckField, 21, 5, 17, 73, 7, // Skip to: 2364 -/* 499 */ MCD_OPC_Decode, 174, 6, 233, 1, // Opcode: FSUB_D64 -/* 504 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 523 -/* 508 */ MCD_OPC_CheckPredicate, 44, 60, 7, // Skip to: 2364 -/* 512 */ MCD_OPC_CheckField, 21, 5, 17, 54, 7, // Skip to: 2364 -/* 518 */ MCD_OPC_Decode, 137, 6, 233, 1, // Opcode: FMUL_D64 -/* 523 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 542 -/* 527 */ MCD_OPC_CheckPredicate, 44, 41, 7, // Skip to: 2364 -/* 531 */ MCD_OPC_CheckField, 21, 5, 17, 35, 7, // Skip to: 2364 -/* 537 */ MCD_OPC_Decode, 208, 5, 233, 1, // Opcode: FDIV_D64 -/* 542 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 561 -/* 546 */ MCD_OPC_CheckPredicate, 45, 22, 7, // Skip to: 2364 -/* 550 */ MCD_OPC_CheckField, 16, 10, 160, 4, 15, 7, // Skip to: 2364 -/* 557 */ MCD_OPC_Decode, 167, 6, 105, // Opcode: FSQRT_D64 -/* 561 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 580 -/* 565 */ MCD_OPC_CheckPredicate, 44, 3, 7, // Skip to: 2364 -/* 569 */ MCD_OPC_CheckField, 16, 10, 160, 4, 252, 6, // Skip to: 2364 -/* 576 */ MCD_OPC_Decode, 165, 5, 105, // Opcode: FABS_D64 -/* 580 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 599 -/* 584 */ MCD_OPC_CheckPredicate, 44, 240, 6, // Skip to: 2364 -/* 588 */ MCD_OPC_CheckField, 16, 10, 160, 4, 233, 6, // Skip to: 2364 -/* 595 */ MCD_OPC_Decode, 130, 6, 105, // Opcode: FMOV_D64 -/* 599 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 618 -/* 603 */ MCD_OPC_CheckPredicate, 44, 221, 6, // Skip to: 2364 -/* 607 */ MCD_OPC_CheckField, 16, 10, 160, 4, 214, 6, // Skip to: 2364 -/* 614 */ MCD_OPC_Decode, 143, 6, 105, // Opcode: FNEG_D64 -/* 618 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 651 -/* 622 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 625 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 638 -/* 630 */ MCD_OPC_CheckPredicate, 44, 194, 6, // Skip to: 2364 -/* 634 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: ROUND_L_S -/* 638 */ MCD_OPC_FilterValue, 160, 4, 185, 6, // Skip to: 2364 -/* 643 */ MCD_OPC_CheckPredicate, 44, 181, 6, // Skip to: 2364 -/* 647 */ MCD_OPC_Decode, 251, 10, 105, // Opcode: ROUND_L_D64 -/* 651 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 684 -/* 655 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 658 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 671 -/* 663 */ MCD_OPC_CheckPredicate, 44, 161, 6, // Skip to: 2364 -/* 667 */ MCD_OPC_Decode, 215, 13, 98, // Opcode: TRUNC_L_S -/* 671 */ MCD_OPC_FilterValue, 160, 4, 152, 6, // Skip to: 2364 -/* 676 */ MCD_OPC_CheckPredicate, 44, 148, 6, // Skip to: 2364 -/* 680 */ MCD_OPC_Decode, 214, 13, 105, // Opcode: TRUNC_L_D64 -/* 684 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 717 -/* 688 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 691 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 704 -/* 696 */ MCD_OPC_CheckPredicate, 44, 128, 6, // Skip to: 2364 -/* 700 */ MCD_OPC_Decode, 224, 2, 98, // Opcode: CEIL_L_S -/* 704 */ MCD_OPC_FilterValue, 160, 4, 119, 6, // Skip to: 2364 -/* 709 */ MCD_OPC_CheckPredicate, 44, 115, 6, // Skip to: 2364 -/* 713 */ MCD_OPC_Decode, 223, 2, 105, // Opcode: CEIL_L_D64 -/* 717 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 750 -/* 721 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 724 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 737 -/* 729 */ MCD_OPC_CheckPredicate, 44, 95, 6, // Skip to: 2364 -/* 733 */ MCD_OPC_Decode, 240, 5, 98, // Opcode: FLOOR_L_S -/* 737 */ MCD_OPC_FilterValue, 160, 4, 86, 6, // Skip to: 2364 -/* 742 */ MCD_OPC_CheckPredicate, 44, 82, 6, // Skip to: 2364 -/* 746 */ MCD_OPC_Decode, 239, 5, 105, // Opcode: FLOOR_L_D64 -/* 750 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 770 -/* 754 */ MCD_OPC_CheckPredicate, 45, 70, 6, // Skip to: 2364 -/* 758 */ MCD_OPC_CheckField, 16, 10, 160, 4, 63, 6, // Skip to: 2364 -/* 765 */ MCD_OPC_Decode, 254, 10, 130, 2, // Opcode: ROUND_W_D64 -/* 770 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 790 -/* 774 */ MCD_OPC_CheckPredicate, 45, 50, 6, // Skip to: 2364 -/* 778 */ MCD_OPC_CheckField, 16, 10, 160, 4, 43, 6, // Skip to: 2364 -/* 785 */ MCD_OPC_Decode, 217, 13, 130, 2, // Opcode: TRUNC_W_D64 -/* 790 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 810 -/* 794 */ MCD_OPC_CheckPredicate, 45, 30, 6, // Skip to: 2364 -/* 798 */ MCD_OPC_CheckField, 16, 10, 160, 4, 23, 6, // Skip to: 2364 -/* 805 */ MCD_OPC_Decode, 226, 2, 130, 2, // Opcode: CEIL_W_D64 -/* 810 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 830 -/* 814 */ MCD_OPC_CheckPredicate, 45, 10, 6, // Skip to: 2364 -/* 818 */ MCD_OPC_CheckField, 16, 10, 160, 4, 3, 6, // Skip to: 2364 -/* 825 */ MCD_OPC_Decode, 242, 5, 130, 2, // Opcode: FLOOR_W_D64 -/* 830 */ MCD_OPC_FilterValue, 17, 41, 0, // Skip to: 875 -/* 834 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... -/* 837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 856 -/* 841 */ MCD_OPC_CheckPredicate, 46, 239, 5, // Skip to: 2364 -/* 845 */ MCD_OPC_CheckField, 21, 5, 17, 233, 5, // Skip to: 2364 -/* 851 */ MCD_OPC_Decode, 238, 8, 131, 2, // Opcode: MOVF_D64 -/* 856 */ MCD_OPC_FilterValue, 1, 224, 5, // Skip to: 2364 -/* 860 */ MCD_OPC_CheckPredicate, 46, 220, 5, // Skip to: 2364 -/* 864 */ MCD_OPC_CheckField, 21, 5, 17, 214, 5, // Skip to: 2364 -/* 870 */ MCD_OPC_Decode, 130, 9, 131, 2, // Opcode: MOVT_D64 -/* 875 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 894 -/* 879 */ MCD_OPC_CheckPredicate, 46, 201, 5, // Skip to: 2364 -/* 883 */ MCD_OPC_CheckField, 21, 5, 17, 195, 5, // Skip to: 2364 -/* 889 */ MCD_OPC_Decode, 142, 9, 132, 2, // Opcode: MOVZ_I_D64 -/* 894 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 913 -/* 898 */ MCD_OPC_CheckPredicate, 46, 182, 5, // Skip to: 2364 -/* 902 */ MCD_OPC_CheckField, 21, 5, 17, 176, 5, // Skip to: 2364 -/* 908 */ MCD_OPC_Decode, 250, 8, 132, 2, // Opcode: MOVN_I_D64 -/* 913 */ MCD_OPC_FilterValue, 32, 31, 0, // Skip to: 948 -/* 917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 920 */ MCD_OPC_FilterValue, 160, 4, 9, 0, // Skip to: 934 -/* 925 */ MCD_OPC_CheckPredicate, 44, 155, 5, // Skip to: 2364 -/* 929 */ MCD_OPC_Decode, 226, 3, 130, 2, // Opcode: CVT_S_D64 -/* 934 */ MCD_OPC_FilterValue, 160, 5, 145, 5, // Skip to: 2364 -/* 939 */ MCD_OPC_CheckPredicate, 44, 141, 5, // Skip to: 2364 -/* 943 */ MCD_OPC_Decode, 227, 3, 130, 2, // Opcode: CVT_S_L -/* 948 */ MCD_OPC_FilterValue, 33, 42, 0, // Skip to: 994 -/* 952 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 955 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 968 -/* 960 */ MCD_OPC_CheckPredicate, 44, 120, 5, // Skip to: 2364 -/* 964 */ MCD_OPC_Decode, 217, 3, 98, // Opcode: CVT_D64_S -/* 968 */ MCD_OPC_FilterValue, 128, 5, 8, 0, // Skip to: 981 -/* 973 */ MCD_OPC_CheckPredicate, 44, 107, 5, // Skip to: 2364 -/* 977 */ MCD_OPC_Decode, 218, 3, 98, // Opcode: CVT_D64_W -/* 981 */ MCD_OPC_FilterValue, 160, 5, 98, 5, // Skip to: 2364 -/* 986 */ MCD_OPC_CheckPredicate, 44, 94, 5, // Skip to: 2364 -/* 990 */ MCD_OPC_Decode, 216, 3, 105, // Opcode: CVT_D64_L -/* 994 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1014 -/* 998 */ MCD_OPC_CheckPredicate, 44, 82, 5, // Skip to: 2364 -/* 1002 */ MCD_OPC_CheckField, 16, 10, 160, 4, 75, 5, // Skip to: 2364 -/* 1009 */ MCD_OPC_Decode, 231, 3, 130, 2, // Opcode: CVT_W_D64 -/* 1014 */ MCD_OPC_FilterValue, 48, 21, 0, // Skip to: 1039 -/* 1018 */ MCD_OPC_CheckPredicate, 47, 62, 5, // Skip to: 2364 -/* 1022 */ MCD_OPC_CheckField, 21, 5, 17, 56, 5, // Skip to: 2364 -/* 1028 */ MCD_OPC_CheckField, 6, 5, 0, 50, 5, // Skip to: 2364 -/* 1034 */ MCD_OPC_Decode, 239, 3, 133, 2, // Opcode: C_F_D64 -/* 1039 */ MCD_OPC_FilterValue, 49, 21, 0, // Skip to: 1064 -/* 1043 */ MCD_OPC_CheckPredicate, 47, 37, 5, // Skip to: 2364 -/* 1047 */ MCD_OPC_CheckField, 21, 5, 17, 31, 5, // Skip to: 2364 -/* 1053 */ MCD_OPC_CheckField, 6, 5, 0, 25, 5, // Skip to: 2364 -/* 1059 */ MCD_OPC_Decode, 153, 4, 133, 2, // Opcode: C_UN_D64 -/* 1064 */ MCD_OPC_FilterValue, 50, 21, 0, // Skip to: 1089 -/* 1068 */ MCD_OPC_CheckPredicate, 47, 12, 5, // Skip to: 2364 -/* 1072 */ MCD_OPC_CheckField, 21, 5, 17, 6, 5, // Skip to: 2364 -/* 1078 */ MCD_OPC_CheckField, 6, 5, 0, 0, 5, // Skip to: 2364 -/* 1084 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: C_EQ_D64 -/* 1089 */ MCD_OPC_FilterValue, 51, 21, 0, // Skip to: 1114 -/* 1093 */ MCD_OPC_CheckPredicate, 47, 243, 4, // Skip to: 2364 -/* 1097 */ MCD_OPC_CheckField, 21, 5, 17, 237, 4, // Skip to: 2364 -/* 1103 */ MCD_OPC_CheckField, 6, 5, 0, 231, 4, // Skip to: 2364 -/* 1109 */ MCD_OPC_Decode, 144, 4, 133, 2, // Opcode: C_UEQ_D64 -/* 1114 */ MCD_OPC_FilterValue, 52, 21, 0, // Skip to: 1139 -/* 1118 */ MCD_OPC_CheckPredicate, 47, 218, 4, // Skip to: 2364 -/* 1122 */ MCD_OPC_CheckField, 21, 5, 17, 212, 4, // Skip to: 2364 -/* 1128 */ MCD_OPC_CheckField, 6, 5, 0, 206, 4, // Skip to: 2364 -/* 1134 */ MCD_OPC_Decode, 135, 4, 133, 2, // Opcode: C_OLT_D64 -/* 1139 */ MCD_OPC_FilterValue, 53, 21, 0, // Skip to: 1164 -/* 1143 */ MCD_OPC_CheckPredicate, 47, 193, 4, // Skip to: 2364 -/* 1147 */ MCD_OPC_CheckField, 21, 5, 17, 187, 4, // Skip to: 2364 -/* 1153 */ MCD_OPC_CheckField, 6, 5, 0, 181, 4, // Skip to: 2364 -/* 1159 */ MCD_OPC_Decode, 150, 4, 133, 2, // Opcode: C_ULT_D64 -/* 1164 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 1189 -/* 1168 */ MCD_OPC_CheckPredicate, 47, 168, 4, // Skip to: 2364 -/* 1172 */ MCD_OPC_CheckField, 21, 5, 17, 162, 4, // Skip to: 2364 -/* 1178 */ MCD_OPC_CheckField, 6, 5, 0, 156, 4, // Skip to: 2364 -/* 1184 */ MCD_OPC_Decode, 132, 4, 133, 2, // Opcode: C_OLE_D64 -/* 1189 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 1214 -/* 1193 */ MCD_OPC_CheckPredicate, 47, 143, 4, // Skip to: 2364 -/* 1197 */ MCD_OPC_CheckField, 21, 5, 17, 137, 4, // Skip to: 2364 -/* 1203 */ MCD_OPC_CheckField, 6, 5, 0, 131, 4, // Skip to: 2364 -/* 1209 */ MCD_OPC_Decode, 147, 4, 133, 2, // Opcode: C_ULE_D64 -/* 1214 */ MCD_OPC_FilterValue, 56, 21, 0, // Skip to: 1239 -/* 1218 */ MCD_OPC_CheckPredicate, 47, 118, 4, // Skip to: 2364 -/* 1222 */ MCD_OPC_CheckField, 21, 5, 17, 112, 4, // Skip to: 2364 -/* 1228 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, // Skip to: 2364 -/* 1234 */ MCD_OPC_Decode, 141, 4, 133, 2, // Opcode: C_SF_D64 -/* 1239 */ MCD_OPC_FilterValue, 57, 21, 0, // Skip to: 1264 -/* 1243 */ MCD_OPC_CheckPredicate, 47, 93, 4, // Skip to: 2364 -/* 1247 */ MCD_OPC_CheckField, 21, 5, 17, 87, 4, // Skip to: 2364 -/* 1253 */ MCD_OPC_CheckField, 6, 5, 0, 81, 4, // Skip to: 2364 -/* 1259 */ MCD_OPC_Decode, 251, 3, 133, 2, // Opcode: C_NGLE_D64 -/* 1264 */ MCD_OPC_FilterValue, 58, 21, 0, // Skip to: 1289 -/* 1268 */ MCD_OPC_CheckPredicate, 47, 68, 4, // Skip to: 2364 -/* 1272 */ MCD_OPC_CheckField, 21, 5, 17, 62, 4, // Skip to: 2364 -/* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 56, 4, // Skip to: 2364 -/* 1284 */ MCD_OPC_Decode, 138, 4, 133, 2, // Opcode: C_SEQ_D64 -/* 1289 */ MCD_OPC_FilterValue, 59, 21, 0, // Skip to: 1314 -/* 1293 */ MCD_OPC_CheckPredicate, 47, 43, 4, // Skip to: 2364 -/* 1297 */ MCD_OPC_CheckField, 21, 5, 17, 37, 4, // Skip to: 2364 -/* 1303 */ MCD_OPC_CheckField, 6, 5, 0, 31, 4, // Skip to: 2364 -/* 1309 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: C_NGL_D64 -/* 1314 */ MCD_OPC_FilterValue, 60, 21, 0, // Skip to: 1339 -/* 1318 */ MCD_OPC_CheckPredicate, 47, 18, 4, // Skip to: 2364 -/* 1322 */ MCD_OPC_CheckField, 21, 5, 17, 12, 4, // Skip to: 2364 -/* 1328 */ MCD_OPC_CheckField, 6, 5, 0, 6, 4, // Skip to: 2364 -/* 1334 */ MCD_OPC_Decode, 245, 3, 133, 2, // Opcode: C_LT_D64 -/* 1339 */ MCD_OPC_FilterValue, 61, 21, 0, // Skip to: 1364 -/* 1343 */ MCD_OPC_CheckPredicate, 47, 249, 3, // Skip to: 2364 -/* 1347 */ MCD_OPC_CheckField, 21, 5, 17, 243, 3, // Skip to: 2364 -/* 1353 */ MCD_OPC_CheckField, 6, 5, 0, 237, 3, // Skip to: 2364 -/* 1359 */ MCD_OPC_Decode, 248, 3, 133, 2, // Opcode: C_NGE_D64 -/* 1364 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 1389 -/* 1368 */ MCD_OPC_CheckPredicate, 47, 224, 3, // Skip to: 2364 -/* 1372 */ MCD_OPC_CheckField, 21, 5, 17, 218, 3, // Skip to: 2364 -/* 1378 */ MCD_OPC_CheckField, 6, 5, 0, 212, 3, // Skip to: 2364 -/* 1384 */ MCD_OPC_Decode, 242, 3, 133, 2, // Opcode: C_LE_D64 -/* 1389 */ MCD_OPC_FilterValue, 63, 203, 3, // Skip to: 2364 -/* 1393 */ MCD_OPC_CheckPredicate, 47, 199, 3, // Skip to: 2364 -/* 1397 */ MCD_OPC_CheckField, 21, 5, 17, 193, 3, // Skip to: 2364 -/* 1403 */ MCD_OPC_CheckField, 6, 5, 0, 187, 3, // Skip to: 2364 -/* 1409 */ MCD_OPC_Decode, 129, 4, 133, 2, // Opcode: C_NGT_D64 -/* 1414 */ MCD_OPC_FilterValue, 18, 41, 0, // Skip to: 1459 -/* 1418 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 1421 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1440 -/* 1425 */ MCD_OPC_CheckPredicate, 42, 167, 3, // Skip to: 2364 -/* 1429 */ MCD_OPC_CheckField, 3, 8, 0, 161, 3, // Skip to: 2364 -/* 1435 */ MCD_OPC_Decode, 198, 4, 255, 1, // Opcode: DMFC2 -/* 1440 */ MCD_OPC_FilterValue, 5, 152, 3, // Skip to: 2364 -/* 1444 */ MCD_OPC_CheckPredicate, 42, 148, 3, // Skip to: 2364 -/* 1448 */ MCD_OPC_CheckField, 3, 8, 0, 142, 3, // Skip to: 2364 -/* 1454 */ MCD_OPC_Decode, 203, 4, 255, 1, // Opcode: DMTC2 -/* 1459 */ MCD_OPC_FilterValue, 19, 131, 0, // Skip to: 1594 -/* 1463 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1466 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1485 -/* 1470 */ MCD_OPC_CheckPredicate, 48, 122, 3, // Skip to: 2364 -/* 1474 */ MCD_OPC_CheckField, 11, 5, 0, 116, 3, // Skip to: 2364 -/* 1480 */ MCD_OPC_Decode, 176, 7, 134, 2, // Opcode: LDXC164 -/* 1485 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1504 -/* 1489 */ MCD_OPC_CheckPredicate, 49, 103, 3, // Skip to: 2364 -/* 1493 */ MCD_OPC_CheckField, 11, 5, 0, 97, 3, // Skip to: 2364 -/* 1499 */ MCD_OPC_Decode, 208, 7, 134, 2, // Opcode: LUXC164 -/* 1504 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1523 -/* 1508 */ MCD_OPC_CheckPredicate, 48, 84, 3, // Skip to: 2364 -/* 1512 */ MCD_OPC_CheckField, 6, 5, 0, 78, 3, // Skip to: 2364 -/* 1518 */ MCD_OPC_Decode, 167, 11, 135, 2, // Opcode: SDXC164 -/* 1523 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1542 -/* 1527 */ MCD_OPC_CheckPredicate, 49, 65, 3, // Skip to: 2364 -/* 1531 */ MCD_OPC_CheckField, 6, 5, 0, 59, 3, // Skip to: 2364 -/* 1537 */ MCD_OPC_Decode, 233, 12, 135, 2, // Opcode: SUXC164 -/* 1542 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 1555 -/* 1546 */ MCD_OPC_CheckPredicate, 48, 46, 3, // Skip to: 2364 -/* 1550 */ MCD_OPC_Decode, 144, 8, 136, 2, // Opcode: MADD_D64 -/* 1555 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 1568 -/* 1559 */ MCD_OPC_CheckPredicate, 48, 33, 3, // Skip to: 2364 -/* 1563 */ MCD_OPC_Decode, 162, 9, 136, 2, // Opcode: MSUB_D64 -/* 1568 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 1581 -/* 1572 */ MCD_OPC_CheckPredicate, 48, 20, 3, // Skip to: 2364 -/* 1576 */ MCD_OPC_Decode, 241, 9, 136, 2, // Opcode: NMADD_D64 -/* 1581 */ MCD_OPC_FilterValue, 57, 11, 3, // Skip to: 2364 -/* 1585 */ MCD_OPC_CheckPredicate, 48, 7, 3, // Skip to: 2364 -/* 1589 */ MCD_OPC_Decode, 246, 9, 136, 2, // Opcode: NMSUB_D64 -/* 1594 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1607 -/* 1598 */ MCD_OPC_CheckPredicate, 41, 250, 2, // Skip to: 2364 -/* 1602 */ MCD_OPC_Decode, 160, 4, 137, 2, // Opcode: DADDi -/* 1607 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 1620 -/* 1611 */ MCD_OPC_CheckPredicate, 19, 237, 2, // Skip to: 2364 -/* 1615 */ MCD_OPC_Decode, 161, 4, 137, 2, // Opcode: DADDiu -/* 1620 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 1633 -/* 1624 */ MCD_OPC_CheckPredicate, 41, 224, 2, // Skip to: 2364 -/* 1628 */ MCD_OPC_Decode, 172, 7, 217, 1, // Opcode: LDL -/* 1633 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 1646 -/* 1637 */ MCD_OPC_CheckPredicate, 41, 211, 2, // Skip to: 2364 -/* 1641 */ MCD_OPC_Decode, 174, 7, 217, 1, // Opcode: LDR -/* 1646 */ MCD_OPC_FilterValue, 28, 159, 1, // Skip to: 2065 -/* 1650 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 1653 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1672 -/* 1657 */ MCD_OPC_CheckPredicate, 50, 191, 2, // Skip to: 2364 -/* 1661 */ MCD_OPC_CheckField, 6, 5, 0, 185, 2, // Skip to: 2364 -/* 1667 */ MCD_OPC_Decode, 206, 4, 224, 1, // Opcode: DMUL -/* 1672 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1691 -/* 1676 */ MCD_OPC_CheckPredicate, 50, 172, 2, // Skip to: 2364 -/* 1680 */ MCD_OPC_CheckField, 6, 15, 0, 166, 2, // Skip to: 2364 -/* 1686 */ MCD_OPC_Decode, 185, 9, 138, 2, // Opcode: MTM0 -/* 1691 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1710 -/* 1695 */ MCD_OPC_CheckPredicate, 50, 153, 2, // Skip to: 2364 -/* 1699 */ MCD_OPC_CheckField, 6, 15, 0, 147, 2, // Skip to: 2364 -/* 1705 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: MTP0 -/* 1710 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1729 -/* 1714 */ MCD_OPC_CheckPredicate, 50, 134, 2, // Skip to: 2364 -/* 1718 */ MCD_OPC_CheckField, 6, 15, 0, 128, 2, // Skip to: 2364 -/* 1724 */ MCD_OPC_Decode, 189, 9, 138, 2, // Opcode: MTP1 -/* 1729 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1748 -/* 1733 */ MCD_OPC_CheckPredicate, 50, 115, 2, // Skip to: 2364 -/* 1737 */ MCD_OPC_CheckField, 6, 15, 0, 109, 2, // Skip to: 2364 -/* 1743 */ MCD_OPC_Decode, 190, 9, 138, 2, // Opcode: MTP2 -/* 1748 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1767 -/* 1752 */ MCD_OPC_CheckPredicate, 50, 96, 2, // Skip to: 2364 -/* 1756 */ MCD_OPC_CheckField, 6, 15, 0, 90, 2, // Skip to: 2364 -/* 1762 */ MCD_OPC_Decode, 186, 9, 138, 2, // Opcode: MTM1 -/* 1767 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1786 -/* 1771 */ MCD_OPC_CheckPredicate, 50, 77, 2, // Skip to: 2364 -/* 1775 */ MCD_OPC_CheckField, 6, 15, 0, 71, 2, // Skip to: 2364 -/* 1781 */ MCD_OPC_Decode, 187, 9, 138, 2, // Opcode: MTM2 -/* 1786 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 1805 -/* 1790 */ MCD_OPC_CheckPredicate, 50, 58, 2, // Skip to: 2364 -/* 1794 */ MCD_OPC_CheckField, 6, 5, 0, 52, 2, // Skip to: 2364 -/* 1800 */ MCD_OPC_Decode, 226, 13, 224, 1, // Opcode: VMULU -/* 1805 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 1824 -/* 1809 */ MCD_OPC_CheckPredicate, 50, 39, 2, // Skip to: 2364 -/* 1813 */ MCD_OPC_CheckField, 6, 5, 0, 33, 2, // Skip to: 2364 -/* 1819 */ MCD_OPC_Decode, 225, 13, 224, 1, // Opcode: VMM0 -/* 1824 */ MCD_OPC_FilterValue, 17, 15, 0, // Skip to: 1843 -/* 1828 */ MCD_OPC_CheckPredicate, 50, 20, 2, // Skip to: 2364 -/* 1832 */ MCD_OPC_CheckField, 6, 5, 0, 14, 2, // Skip to: 2364 -/* 1838 */ MCD_OPC_Decode, 224, 13, 224, 1, // Opcode: V3MULU -/* 1843 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 1862 -/* 1847 */ MCD_OPC_CheckPredicate, 51, 1, 2, // Skip to: 2364 -/* 1851 */ MCD_OPC_CheckField, 6, 5, 0, 251, 1, // Skip to: 2364 -/* 1857 */ MCD_OPC_Decode, 170, 4, 139, 2, // Opcode: DCLZ -/* 1862 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1881 -/* 1866 */ MCD_OPC_CheckPredicate, 51, 238, 1, // Skip to: 2364 -/* 1870 */ MCD_OPC_CheckField, 6, 5, 0, 232, 1, // Skip to: 2364 -/* 1876 */ MCD_OPC_Decode, 168, 4, 139, 2, // Opcode: DCLO -/* 1881 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 1900 -/* 1885 */ MCD_OPC_CheckPredicate, 50, 219, 1, // Skip to: 2364 -/* 1889 */ MCD_OPC_CheckField, 6, 5, 0, 213, 1, // Skip to: 2364 -/* 1895 */ MCD_OPC_Decode, 166, 1, 224, 1, // Opcode: BADDu -/* 1900 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 1919 -/* 1904 */ MCD_OPC_CheckPredicate, 50, 200, 1, // Skip to: 2364 -/* 1908 */ MCD_OPC_CheckField, 6, 5, 0, 194, 1, // Skip to: 2364 -/* 1914 */ MCD_OPC_Decode, 184, 11, 224, 1, // Opcode: SEQ -/* 1919 */ MCD_OPC_FilterValue, 43, 15, 0, // Skip to: 1938 -/* 1923 */ MCD_OPC_CheckPredicate, 50, 181, 1, // Skip to: 2364 -/* 1927 */ MCD_OPC_CheckField, 6, 5, 0, 175, 1, // Skip to: 2364 -/* 1933 */ MCD_OPC_Decode, 252, 11, 224, 1, // Opcode: SNE -/* 1938 */ MCD_OPC_FilterValue, 44, 20, 0, // Skip to: 1962 -/* 1942 */ MCD_OPC_CheckPredicate, 50, 162, 1, // Skip to: 2364 -/* 1946 */ MCD_OPC_CheckField, 16, 5, 0, 156, 1, // Skip to: 2364 -/* 1952 */ MCD_OPC_CheckField, 6, 5, 0, 150, 1, // Skip to: 2364 -/* 1958 */ MCD_OPC_Decode, 163, 10, 62, // Opcode: POP -/* 1962 */ MCD_OPC_FilterValue, 45, 21, 0, // Skip to: 1987 -/* 1966 */ MCD_OPC_CheckPredicate, 50, 138, 1, // Skip to: 2364 -/* 1970 */ MCD_OPC_CheckField, 16, 5, 0, 132, 1, // Skip to: 2364 -/* 1976 */ MCD_OPC_CheckField, 6, 5, 0, 126, 1, // Skip to: 2364 -/* 1982 */ MCD_OPC_Decode, 231, 4, 222, 1, // Opcode: DPOP -/* 1987 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 2000 -/* 1991 */ MCD_OPC_CheckPredicate, 50, 113, 1, // Skip to: 2364 -/* 1995 */ MCD_OPC_Decode, 185, 11, 140, 2, // Opcode: SEQi -/* 2000 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 2013 -/* 2004 */ MCD_OPC_CheckPredicate, 50, 100, 1, // Skip to: 2364 -/* 2008 */ MCD_OPC_Decode, 253, 11, 140, 2, // Opcode: SNEi -/* 2013 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2026 -/* 2017 */ MCD_OPC_CheckPredicate, 50, 87, 1, // Skip to: 2364 -/* 2021 */ MCD_OPC_Decode, 241, 2, 141, 2, // Opcode: CINS -/* 2026 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 2039 -/* 2030 */ MCD_OPC_CheckPredicate, 50, 74, 1, // Skip to: 2364 -/* 2034 */ MCD_OPC_Decode, 242, 2, 141, 2, // Opcode: CINS32 -/* 2039 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2052 -/* 2043 */ MCD_OPC_CheckPredicate, 50, 61, 1, // Skip to: 2364 -/* 2047 */ MCD_OPC_Decode, 158, 5, 141, 2, // Opcode: EXTS -/* 2052 */ MCD_OPC_FilterValue, 59, 52, 1, // Skip to: 2364 -/* 2056 */ MCD_OPC_CheckPredicate, 50, 48, 1, // Skip to: 2364 -/* 2060 */ MCD_OPC_Decode, 159, 5, 141, 2, // Opcode: EXTS32 -/* 2065 */ MCD_OPC_FilterValue, 31, 126, 0, // Skip to: 2195 -/* 2069 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 2072 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2085 -/* 2076 */ MCD_OPC_CheckPredicate, 6, 28, 1, // Skip to: 2364 -/* 2080 */ MCD_OPC_Decode, 177, 4, 142, 2, // Opcode: DEXTM -/* 2085 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2098 -/* 2089 */ MCD_OPC_CheckPredicate, 6, 15, 1, // Skip to: 2364 -/* 2093 */ MCD_OPC_Decode, 178, 4, 142, 2, // Opcode: DEXTU -/* 2098 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2111 -/* 2102 */ MCD_OPC_CheckPredicate, 6, 2, 1, // Skip to: 2364 -/* 2106 */ MCD_OPC_Decode, 176, 4, 142, 2, // Opcode: DEXT -/* 2111 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 2124 -/* 2115 */ MCD_OPC_CheckPredicate, 6, 245, 0, // Skip to: 2364 -/* 2119 */ MCD_OPC_Decode, 181, 4, 143, 2, // Opcode: DINSM -/* 2124 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 2137 -/* 2128 */ MCD_OPC_CheckPredicate, 6, 232, 0, // Skip to: 2364 -/* 2132 */ MCD_OPC_Decode, 182, 4, 143, 2, // Opcode: DINSU -/* 2137 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 2150 -/* 2141 */ MCD_OPC_CheckPredicate, 6, 219, 0, // Skip to: 2364 -/* 2145 */ MCD_OPC_Decode, 180, 4, 143, 2, // Opcode: DINS -/* 2150 */ MCD_OPC_FilterValue, 36, 210, 0, // Skip to: 2364 -/* 2154 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 2157 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2176 -/* 2161 */ MCD_OPC_CheckPredicate, 40, 199, 0, // Skip to: 2364 -/* 2165 */ MCD_OPC_CheckField, 21, 5, 0, 193, 0, // Skip to: 2364 -/* 2171 */ MCD_OPC_Decode, 249, 4, 243, 1, // Opcode: DSBH -/* 2176 */ MCD_OPC_FilterValue, 5, 184, 0, // Skip to: 2364 -/* 2180 */ MCD_OPC_CheckPredicate, 40, 180, 0, // Skip to: 2364 -/* 2184 */ MCD_OPC_CheckField, 21, 5, 0, 174, 0, // Skip to: 2364 -/* 2190 */ MCD_OPC_Decode, 251, 4, 243, 1, // Opcode: DSHD -/* 2195 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 2208 -/* 2199 */ MCD_OPC_CheckPredicate, 19, 161, 0, // Skip to: 2364 -/* 2203 */ MCD_OPC_Decode, 241, 7, 217, 1, // Opcode: LWu -/* 2208 */ MCD_OPC_FilterValue, 44, 9, 0, // Skip to: 2221 -/* 2212 */ MCD_OPC_CheckPredicate, 41, 148, 0, // Skip to: 2364 -/* 2216 */ MCD_OPC_Decode, 164, 11, 217, 1, // Opcode: SDL -/* 2221 */ MCD_OPC_FilterValue, 45, 9, 0, // Skip to: 2234 -/* 2225 */ MCD_OPC_CheckPredicate, 41, 135, 0, // Skip to: 2364 -/* 2229 */ MCD_OPC_Decode, 165, 11, 217, 1, // Opcode: SDR -/* 2234 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2247 -/* 2238 */ MCD_OPC_CheckPredicate, 50, 122, 0, // Skip to: 2364 -/* 2242 */ MCD_OPC_Decode, 171, 1, 144, 2, // Opcode: BBIT0 -/* 2247 */ MCD_OPC_FilterValue, 52, 9, 0, // Skip to: 2260 -/* 2251 */ MCD_OPC_CheckPredicate, 41, 109, 0, // Skip to: 2364 -/* 2255 */ MCD_OPC_Decode, 194, 7, 217, 1, // Opcode: LLD -/* 2260 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 2273 -/* 2264 */ MCD_OPC_CheckPredicate, 52, 96, 0, // Skip to: 2364 -/* 2268 */ MCD_OPC_Decode, 163, 7, 219, 1, // Opcode: LDC164 -/* 2273 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 2286 -/* 2277 */ MCD_OPC_CheckPredicate, 50, 83, 0, // Skip to: 2364 -/* 2281 */ MCD_OPC_Decode, 172, 1, 144, 2, // Opcode: BBIT032 -/* 2286 */ MCD_OPC_FilterValue, 55, 9, 0, // Skip to: 2299 -/* 2290 */ MCD_OPC_CheckPredicate, 19, 70, 0, // Skip to: 2364 -/* 2294 */ MCD_OPC_Decode, 161, 7, 217, 1, // Opcode: LD -/* 2299 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2312 -/* 2303 */ MCD_OPC_CheckPredicate, 50, 57, 0, // Skip to: 2364 -/* 2307 */ MCD_OPC_Decode, 173, 1, 144, 2, // Opcode: BBIT1 -/* 2312 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 2325 -/* 2316 */ MCD_OPC_CheckPredicate, 41, 44, 0, // Skip to: 2364 -/* 2320 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: SCD -/* 2325 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 2338 -/* 2329 */ MCD_OPC_CheckPredicate, 52, 31, 0, // Skip to: 2364 -/* 2333 */ MCD_OPC_Decode, 157, 11, 219, 1, // Opcode: SDC164 -/* 2338 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 2351 -/* 2342 */ MCD_OPC_CheckPredicate, 50, 18, 0, // Skip to: 2364 -/* 2346 */ MCD_OPC_Decode, 174, 1, 144, 2, // Opcode: BBIT132 -/* 2351 */ MCD_OPC_FilterValue, 63, 9, 0, // Skip to: 2364 -/* 2355 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 2364 -/* 2359 */ MCD_OPC_Decode, 151, 11, 217, 1, // Opcode: SD -/* 2364 */ MCD_OPC_Fail, - 0 -}; - -static bool getbool(uint64_t b) -{ - return b != 0; -} + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 236, + 1, + 0, // Skip to: 500 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 32 + /* 16 */ MCD_OPC_CheckPredicate, + 88, + 214, + 4, + 0, // Skip to: 1259 + /* 21 */ MCD_OPC_CheckField, + 6, + 15, + 16, + 207, + 4, + 0, // Skip to: 1259 + /* 28 */ MCD_OPC_Decode, + 141, + 14, + 13, // Opcode: JR_HB64 + /* 32 */ MCD_OPC_FilterValue, + 9, + 45, + 0, + 0, // Skip to: 82 + /* 37 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 40 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 61 + /* 45 */ MCD_OPC_CheckPredicate, + 89, + 185, + 4, + 0, // Skip to: 1259 + /* 50 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 178, + 4, + 0, // Skip to: 1259 + /* 57 */ MCD_OPC_Decode, + 242, + 13, + 15, // Opcode: JALR64 + /* 61 */ MCD_OPC_FilterValue, + 16, + 169, + 4, + 0, // Skip to: 1259 + /* 66 */ MCD_OPC_CheckPredicate, + 90, + 164, + 4, + 0, // Skip to: 1259 + /* 71 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 157, + 4, + 0, // Skip to: 1259 + /* 78 */ MCD_OPC_Decode, + 249, + 13, + 15, // Opcode: JALR_HB64 + /* 82 */ MCD_OPC_FilterValue, + 20, + 17, + 0, + 0, // Skip to: 104 + /* 87 */ MCD_OPC_CheckPredicate, + 91, + 143, + 4, + 0, // Skip to: 1259 + /* 92 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 136, + 4, + 0, // Skip to: 1259 + /* 99 */ MCD_OPC_Decode, + 207, + 11, + 238, + 2, // Opcode: DSLLV + /* 104 */ MCD_OPC_FilterValue, + 22, + 33, + 0, + 0, // Skip to: 142 + /* 109 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 112 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 127 + /* 117 */ MCD_OPC_CheckPredicate, + 91, + 113, + 4, + 0, // Skip to: 1259 + /* 122 */ MCD_OPC_Decode, + 213, + 11, + 238, + 2, // Opcode: DSRLV + /* 127 */ MCD_OPC_FilterValue, + 1, + 103, + 4, + 0, // Skip to: 1259 + /* 132 */ MCD_OPC_CheckPredicate, + 90, + 98, + 4, + 0, // Skip to: 1259 + /* 137 */ MCD_OPC_Decode, + 200, + 11, + 238, + 2, // Opcode: DROTRV + /* 142 */ MCD_OPC_FilterValue, + 23, + 17, + 0, + 0, // Skip to: 164 + /* 147 */ MCD_OPC_CheckPredicate, + 91, + 83, + 4, + 0, // Skip to: 1259 + /* 152 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 76, + 4, + 0, // Skip to: 1259 + /* 159 */ MCD_OPC_Decode, + 210, + 11, + 238, + 2, // Opcode: DSRAV + /* 164 */ MCD_OPC_FilterValue, + 28, + 17, + 0, + 0, // Skip to: 186 + /* 169 */ MCD_OPC_CheckPredicate, + 92, + 61, + 4, + 0, // Skip to: 1259 + /* 174 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 54, + 4, + 0, // Skip to: 1259 + /* 181 */ MCD_OPC_Decode, + 143, + 11, + 239, + 2, // Opcode: DMULT + /* 186 */ MCD_OPC_FilterValue, + 29, + 17, + 0, + 0, // Skip to: 208 + /* 191 */ MCD_OPC_CheckPredicate, + 92, + 39, + 4, + 0, // Skip to: 1259 + /* 196 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 32, + 4, + 0, // Skip to: 1259 + /* 203 */ MCD_OPC_Decode, + 144, + 11, + 239, + 2, // Opcode: DMULTu + /* 208 */ MCD_OPC_FilterValue, + 30, + 17, + 0, + 0, // Skip to: 230 + /* 213 */ MCD_OPC_CheckPredicate, + 92, + 17, + 4, + 0, // Skip to: 1259 + /* 218 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 10, + 4, + 0, // Skip to: 1259 + /* 225 */ MCD_OPC_Decode, + 202, + 11, + 239, + 2, // Opcode: DSDIV + /* 230 */ MCD_OPC_FilterValue, + 31, + 17, + 0, + 0, // Skip to: 252 + /* 235 */ MCD_OPC_CheckPredicate, + 92, + 251, + 3, + 0, // Skip to: 1259 + /* 240 */ MCD_OPC_CheckField, + 6, + 10, + 0, + 244, + 3, + 0, // Skip to: 1259 + /* 247 */ MCD_OPC_Decode, + 216, + 11, + 239, + 2, // Opcode: DUDIV + /* 252 */ MCD_OPC_FilterValue, + 44, + 16, + 0, + 0, // Skip to: 273 + /* 257 */ MCD_OPC_CheckPredicate, + 91, + 229, + 3, + 0, // Skip to: 1259 + /* 262 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 222, + 3, + 0, // Skip to: 1259 + /* 269 */ MCD_OPC_Decode, + 213, + 10, + 12, // Opcode: DADD + /* 273 */ MCD_OPC_FilterValue, + 45, + 16, + 0, + 0, // Skip to: 294 + /* 278 */ MCD_OPC_CheckPredicate, + 91, + 208, + 3, + 0, // Skip to: 1259 + /* 283 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 201, + 3, + 0, // Skip to: 1259 + /* 290 */ MCD_OPC_Decode, + 216, + 10, + 12, // Opcode: DADDu + /* 294 */ MCD_OPC_FilterValue, + 46, + 16, + 0, + 0, // Skip to: 315 + /* 299 */ MCD_OPC_CheckPredicate, + 91, + 187, + 3, + 0, // Skip to: 1259 + /* 304 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 180, + 3, + 0, // Skip to: 1259 + /* 311 */ MCD_OPC_Decode, + 214, + 11, + 12, // Opcode: DSUB + /* 315 */ MCD_OPC_FilterValue, + 47, + 16, + 0, + 0, // Skip to: 336 + /* 320 */ MCD_OPC_CheckPredicate, + 91, + 166, + 3, + 0, // Skip to: 1259 + /* 325 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 159, + 3, + 0, // Skip to: 1259 + /* 332 */ MCD_OPC_Decode, + 215, + 11, + 12, // Opcode: DSUBu + /* 336 */ MCD_OPC_FilterValue, + 56, + 17, + 0, + 0, // Skip to: 358 + /* 341 */ MCD_OPC_CheckPredicate, + 91, + 145, + 3, + 0, // Skip to: 1259 + /* 346 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 138, + 3, + 0, // Skip to: 1259 + /* 353 */ MCD_OPC_Decode, + 204, + 11, + 240, + 2, // Opcode: DSLL + /* 358 */ MCD_OPC_FilterValue, + 58, + 33, + 0, + 0, // Skip to: 396 + /* 363 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 366 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 381 + /* 371 */ MCD_OPC_CheckPredicate, + 91, + 115, + 3, + 0, // Skip to: 1259 + /* 376 */ MCD_OPC_Decode, + 211, + 11, + 240, + 2, // Opcode: DSRL + /* 381 */ MCD_OPC_FilterValue, + 1, + 105, + 3, + 0, // Skip to: 1259 + /* 386 */ MCD_OPC_CheckPredicate, + 90, + 100, + 3, + 0, // Skip to: 1259 + /* 391 */ MCD_OPC_Decode, + 198, + 11, + 240, + 2, // Opcode: DROTR + /* 396 */ MCD_OPC_FilterValue, + 59, + 17, + 0, + 0, // Skip to: 418 + /* 401 */ MCD_OPC_CheckPredicate, + 91, + 85, + 3, + 0, // Skip to: 1259 + /* 406 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 78, + 3, + 0, // Skip to: 1259 + /* 413 */ MCD_OPC_Decode, + 208, + 11, + 240, + 2, // Opcode: DSRA + /* 418 */ MCD_OPC_FilterValue, + 60, + 17, + 0, + 0, // Skip to: 440 + /* 423 */ MCD_OPC_CheckPredicate, + 91, + 63, + 3, + 0, // Skip to: 1259 + /* 428 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 56, + 3, + 0, // Skip to: 1259 + /* 435 */ MCD_OPC_Decode, + 205, + 11, + 240, + 2, // Opcode: DSLL32 + /* 440 */ MCD_OPC_FilterValue, + 62, + 33, + 0, + 0, // Skip to: 478 + /* 445 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 448 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 463 + /* 453 */ MCD_OPC_CheckPredicate, + 91, + 33, + 3, + 0, // Skip to: 1259 + /* 458 */ MCD_OPC_Decode, + 212, + 11, + 240, + 2, // Opcode: DSRL32 + /* 463 */ MCD_OPC_FilterValue, + 1, + 23, + 3, + 0, // Skip to: 1259 + /* 468 */ MCD_OPC_CheckPredicate, + 90, + 18, + 3, + 0, // Skip to: 1259 + /* 473 */ MCD_OPC_Decode, + 199, + 11, + 240, + 2, // Opcode: DROTR32 + /* 478 */ MCD_OPC_FilterValue, + 63, + 8, + 3, + 0, // Skip to: 1259 + /* 483 */ MCD_OPC_CheckPredicate, + 91, + 3, + 3, + 0, // Skip to: 1259 + /* 488 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 252, + 2, + 0, // Skip to: 1259 + /* 495 */ MCD_OPC_Decode, + 209, + 11, + 240, + 2, // Opcode: DSRA32 + /* 500 */ MCD_OPC_FilterValue, + 16, + 85, + 0, + 0, // Skip to: 590 + /* 505 */ MCD_OPC_ExtractField, + 3, + 8, // Inst{10-3} ... + /* 508 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 546 + /* 513 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 516 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 531 + /* 521 */ MCD_OPC_CheckPredicate, + 93, + 221, + 2, + 0, // Skip to: 1259 + /* 526 */ MCD_OPC_Decode, + 255, + 10, + 241, + 2, // Opcode: DMFC0 + /* 531 */ MCD_OPC_FilterValue, + 5, + 211, + 2, + 0, // Skip to: 1259 + /* 536 */ MCD_OPC_CheckPredicate, + 93, + 206, + 2, + 0, // Skip to: 1259 + /* 541 */ MCD_OPC_Decode, + 135, + 11, + 242, + 2, // Opcode: DMTC0 + /* 546 */ MCD_OPC_FilterValue, + 32, + 17, + 0, + 0, // Skip to: 568 + /* 551 */ MCD_OPC_CheckPredicate, + 94, + 191, + 2, + 0, // Skip to: 1259 + /* 556 */ MCD_OPC_CheckField, + 21, + 5, + 3, + 184, + 2, + 0, // Skip to: 1259 + /* 563 */ MCD_OPC_Decode, + 131, + 11, + 241, + 2, // Opcode: DMFGC0 + /* 568 */ MCD_OPC_FilterValue, + 96, + 174, + 2, + 0, // Skip to: 1259 + /* 573 */ MCD_OPC_CheckPredicate, + 94, + 169, + 2, + 0, // Skip to: 1259 + /* 578 */ MCD_OPC_CheckField, + 21, + 5, + 3, + 162, + 2, + 0, // Skip to: 1259 + /* 585 */ MCD_OPC_Decode, + 139, + 11, + 242, + 2, // Opcode: DMTGC0 + /* 590 */ MCD_OPC_FilterValue, + 18, + 47, + 0, + 0, // Skip to: 642 + /* 595 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 598 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 620 + /* 603 */ MCD_OPC_CheckPredicate, + 93, + 139, + 2, + 0, // Skip to: 1259 + /* 608 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 132, + 2, + 0, // Skip to: 1259 + /* 615 */ MCD_OPC_Decode, + 129, + 11, + 243, + 2, // Opcode: DMFC2 + /* 620 */ MCD_OPC_FilterValue, + 5, + 122, + 2, + 0, // Skip to: 1259 + /* 625 */ MCD_OPC_CheckPredicate, + 93, + 117, + 2, + 0, // Skip to: 1259 + /* 630 */ MCD_OPC_CheckField, + 3, + 8, + 0, + 110, + 2, + 0, // Skip to: 1259 + /* 637 */ MCD_OPC_Decode, + 137, + 11, + 244, + 2, // Opcode: DMTC2 + /* 642 */ MCD_OPC_FilterValue, + 21, + 3, + 1, + 0, // Skip to: 906 + /* 647 */ MCD_OPC_ExtractField, + 0, + 13, // Inst{12-0} ... + /* 650 */ MCD_OPC_FilterValue, + 188, + 8, + 10, + 0, + 0, // Skip to: 666 + /* 656 */ MCD_OPC_CheckPredicate, + 15, + 86, + 2, + 0, // Skip to: 1259 + /* 661 */ MCD_OPC_Decode, + 251, + 9, + 245, + 2, // Opcode: C_F_D64_MM + /* 666 */ MCD_OPC_FilterValue, + 252, + 8, + 10, + 0, + 0, // Skip to: 682 + /* 672 */ MCD_OPC_CheckPredicate, + 15, + 70, + 2, + 0, // Skip to: 1259 + /* 677 */ MCD_OPC_Decode, + 207, + 10, + 245, + 2, // Opcode: C_UN_D64_MM + /* 682 */ MCD_OPC_FilterValue, + 188, + 9, + 10, + 0, + 0, // Skip to: 698 + /* 688 */ MCD_OPC_CheckPredicate, + 15, + 54, + 2, + 0, // Skip to: 1259 + /* 693 */ MCD_OPC_Decode, + 245, + 9, + 245, + 2, // Opcode: C_EQ_D64_MM + /* 698 */ MCD_OPC_FilterValue, + 252, + 9, + 10, + 0, + 0, // Skip to: 714 + /* 704 */ MCD_OPC_CheckPredicate, + 15, + 38, + 2, + 0, // Skip to: 1259 + /* 709 */ MCD_OPC_Decode, + 189, + 10, + 245, + 2, // Opcode: C_UEQ_D64_MM + /* 714 */ MCD_OPC_FilterValue, + 188, + 10, + 10, + 0, + 0, // Skip to: 730 + /* 720 */ MCD_OPC_CheckPredicate, + 15, + 22, + 2, + 0, // Skip to: 1259 + /* 725 */ MCD_OPC_Decode, + 171, + 10, + 245, + 2, // Opcode: C_OLT_D64_MM + /* 730 */ MCD_OPC_FilterValue, + 252, + 10, + 10, + 0, + 0, // Skip to: 746 + /* 736 */ MCD_OPC_CheckPredicate, + 15, + 6, + 2, + 0, // Skip to: 1259 + /* 741 */ MCD_OPC_Decode, + 201, + 10, + 245, + 2, // Opcode: C_ULT_D64_MM + /* 746 */ MCD_OPC_FilterValue, + 188, + 11, + 10, + 0, + 0, // Skip to: 762 + /* 752 */ MCD_OPC_CheckPredicate, + 15, + 246, + 1, + 0, // Skip to: 1259 + /* 757 */ MCD_OPC_Decode, + 165, + 10, + 245, + 2, // Opcode: C_OLE_D64_MM + /* 762 */ MCD_OPC_FilterValue, + 252, + 11, + 10, + 0, + 0, // Skip to: 778 + /* 768 */ MCD_OPC_CheckPredicate, + 15, + 230, + 1, + 0, // Skip to: 1259 + /* 773 */ MCD_OPC_Decode, + 195, + 10, + 245, + 2, // Opcode: C_ULE_D64_MM + /* 778 */ MCD_OPC_FilterValue, + 188, + 12, + 10, + 0, + 0, // Skip to: 794 + /* 784 */ MCD_OPC_CheckPredicate, + 15, + 214, + 1, + 0, // Skip to: 1259 + /* 789 */ MCD_OPC_Decode, + 183, + 10, + 245, + 2, // Opcode: C_SF_D64_MM + /* 794 */ MCD_OPC_FilterValue, + 252, + 12, + 10, + 0, + 0, // Skip to: 810 + /* 800 */ MCD_OPC_CheckPredicate, + 15, + 198, + 1, + 0, // Skip to: 1259 + /* 805 */ MCD_OPC_Decode, + 147, + 10, + 245, + 2, // Opcode: C_NGLE_D64_MM + /* 810 */ MCD_OPC_FilterValue, + 188, + 13, + 10, + 0, + 0, // Skip to: 826 + /* 816 */ MCD_OPC_CheckPredicate, + 15, + 182, + 1, + 0, // Skip to: 1259 + /* 821 */ MCD_OPC_Decode, + 177, + 10, + 245, + 2, // Opcode: C_SEQ_D64_MM + /* 826 */ MCD_OPC_FilterValue, + 252, + 13, + 10, + 0, + 0, // Skip to: 842 + /* 832 */ MCD_OPC_CheckPredicate, + 15, + 166, + 1, + 0, // Skip to: 1259 + /* 837 */ MCD_OPC_Decode, + 153, + 10, + 245, + 2, // Opcode: C_NGL_D64_MM + /* 842 */ MCD_OPC_FilterValue, + 188, + 14, + 10, + 0, + 0, // Skip to: 858 + /* 848 */ MCD_OPC_CheckPredicate, + 15, + 150, + 1, + 0, // Skip to: 1259 + /* 853 */ MCD_OPC_Decode, + 135, + 10, + 245, + 2, // Opcode: C_LT_D64_MM + /* 858 */ MCD_OPC_FilterValue, + 252, + 14, + 10, + 0, + 0, // Skip to: 874 + /* 864 */ MCD_OPC_CheckPredicate, + 15, + 134, + 1, + 0, // Skip to: 1259 + /* 869 */ MCD_OPC_Decode, + 141, + 10, + 245, + 2, // Opcode: C_NGE_D64_MM + /* 874 */ MCD_OPC_FilterValue, + 188, + 15, + 10, + 0, + 0, // Skip to: 890 + /* 880 */ MCD_OPC_CheckPredicate, + 15, + 118, + 1, + 0, // Skip to: 1259 + /* 885 */ MCD_OPC_Decode, + 129, + 10, + 245, + 2, // Opcode: C_LE_D64_MM + /* 890 */ MCD_OPC_FilterValue, + 252, + 15, + 107, + 1, + 0, // Skip to: 1259 + /* 896 */ MCD_OPC_CheckPredicate, + 15, + 102, + 1, + 0, // Skip to: 1259 + /* 901 */ MCD_OPC_Decode, + 159, + 10, + 245, + 2, // Opcode: C_NGT_D64_MM + /* 906 */ MCD_OPC_FilterValue, + 24, + 10, + 0, + 0, // Skip to: 921 + /* 911 */ MCD_OPC_CheckPredicate, + 95, + 87, + 1, + 0, // Skip to: 1259 + /* 916 */ MCD_OPC_Decode, + 214, + 10, + 246, + 2, // Opcode: DADDi + /* 921 */ MCD_OPC_FilterValue, + 25, + 10, + 0, + 0, // Skip to: 936 + /* 926 */ MCD_OPC_CheckPredicate, + 91, + 72, + 1, + 0, // Skip to: 1259 + /* 931 */ MCD_OPC_Decode, + 215, + 10, + 246, + 2, // Opcode: DADDiu + /* 936 */ MCD_OPC_FilterValue, + 26, + 10, + 0, + 0, // Skip to: 951 + /* 941 */ MCD_OPC_CheckPredicate, + 95, + 57, + 1, + 0, // Skip to: 1259 + /* 946 */ MCD_OPC_Decode, + 180, + 14, + 130, + 1, // Opcode: LDL + /* 951 */ MCD_OPC_FilterValue, + 27, + 10, + 0, + 0, // Skip to: 966 + /* 956 */ MCD_OPC_CheckPredicate, + 95, + 42, + 1, + 0, // Skip to: 1259 + /* 961 */ MCD_OPC_Decode, + 182, + 14, + 130, + 1, // Opcode: LDR + /* 966 */ MCD_OPC_FilterValue, + 28, + 33, + 0, + 0, // Skip to: 1004 + /* 971 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 974 */ MCD_OPC_FilterValue, + 36, + 10, + 0, + 0, // Skip to: 989 + /* 979 */ MCD_OPC_CheckPredicate, + 96, + 19, + 1, + 0, // Skip to: 1259 + /* 984 */ MCD_OPC_Decode, + 224, + 10, + 247, + 2, // Opcode: DCLZ + /* 989 */ MCD_OPC_FilterValue, + 37, + 9, + 1, + 0, // Skip to: 1259 + /* 994 */ MCD_OPC_CheckPredicate, + 96, + 4, + 1, + 0, // Skip to: 1259 + /* 999 */ MCD_OPC_Decode, + 222, + 10, + 247, + 2, // Opcode: DCLO + /* 1004 */ MCD_OPC_FilterValue, + 31, + 145, + 0, + 0, // Skip to: 1154 + /* 1009 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1012 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1027 + /* 1017 */ MCD_OPC_CheckPredicate, + 90, + 237, + 0, + 0, // Skip to: 1259 + /* 1022 */ MCD_OPC_Decode, + 233, + 10, + 248, + 2, // Opcode: DEXTM + /* 1027 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1042 + /* 1032 */ MCD_OPC_CheckPredicate, + 90, + 222, + 0, + 0, // Skip to: 1259 + /* 1037 */ MCD_OPC_Decode, + 234, + 10, + 248, + 2, // Opcode: DEXTU + /* 1042 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1057 + /* 1047 */ MCD_OPC_CheckPredicate, + 90, + 207, + 0, + 0, // Skip to: 1259 + /* 1052 */ MCD_OPC_Decode, + 231, + 10, + 248, + 2, // Opcode: DEXT + /* 1057 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1072 + /* 1062 */ MCD_OPC_CheckPredicate, + 90, + 192, + 0, + 0, // Skip to: 1259 + /* 1067 */ MCD_OPC_Decode, + 237, + 10, + 249, + 2, // Opcode: DINSM + /* 1072 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 1087 + /* 1077 */ MCD_OPC_CheckPredicate, + 90, + 177, + 0, + 0, // Skip to: 1259 + /* 1082 */ MCD_OPC_Decode, + 238, + 10, + 249, + 2, // Opcode: DINSU + /* 1087 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1102 + /* 1092 */ MCD_OPC_CheckPredicate, + 90, + 162, + 0, + 0, // Skip to: 1259 + /* 1097 */ MCD_OPC_Decode, + 236, + 10, + 249, + 2, // Opcode: DINS + /* 1102 */ MCD_OPC_FilterValue, + 36, + 152, + 0, + 0, // Skip to: 1259 + /* 1107 */ MCD_OPC_ExtractField, + 6, + 5, // Inst{10-6} ... + /* 1110 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 1132 + /* 1115 */ MCD_OPC_CheckPredicate, + 90, + 139, + 0, + 0, // Skip to: 1259 + /* 1120 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 132, + 0, + 0, // Skip to: 1259 + /* 1127 */ MCD_OPC_Decode, + 201, + 11, + 230, + 2, // Opcode: DSBH + /* 1132 */ MCD_OPC_FilterValue, + 5, + 122, + 0, + 0, // Skip to: 1259 + /* 1137 */ MCD_OPC_CheckPredicate, + 90, + 117, + 0, + 0, // Skip to: 1259 + /* 1142 */ MCD_OPC_CheckField, + 21, + 5, + 0, + 110, + 0, + 0, // Skip to: 1259 + /* 1149 */ MCD_OPC_Decode, + 203, + 11, + 230, + 2, // Opcode: DSHD + /* 1154 */ MCD_OPC_FilterValue, + 39, + 10, + 0, + 0, // Skip to: 1169 + /* 1159 */ MCD_OPC_CheckPredicate, + 91, + 95, + 0, + 0, // Skip to: 1259 + /* 1164 */ MCD_OPC_Decode, + 139, + 15, + 130, + 1, // Opcode: LWu + /* 1169 */ MCD_OPC_FilterValue, + 44, + 10, + 0, + 0, // Skip to: 1184 + /* 1174 */ MCD_OPC_CheckPredicate, + 95, + 80, + 0, + 0, // Skip to: 1259 + /* 1179 */ MCD_OPC_Decode, + 141, + 19, + 130, + 1, // Opcode: SDL + /* 1184 */ MCD_OPC_FilterValue, + 45, + 10, + 0, + 0, // Skip to: 1199 + /* 1189 */ MCD_OPC_CheckPredicate, + 95, + 65, + 0, + 0, // Skip to: 1259 + /* 1194 */ MCD_OPC_Decode, + 142, + 19, + 130, + 1, // Opcode: SDR + /* 1199 */ MCD_OPC_FilterValue, + 52, + 10, + 0, + 0, // Skip to: 1214 + /* 1204 */ MCD_OPC_CheckPredicate, + 92, + 50, + 0, + 0, // Skip to: 1259 + /* 1209 */ MCD_OPC_Decode, + 210, + 14, + 130, + 1, // Opcode: LLD + /* 1214 */ MCD_OPC_FilterValue, + 55, + 10, + 0, + 0, // Skip to: 1229 + /* 1219 */ MCD_OPC_CheckPredicate, + 91, + 35, + 0, + 0, // Skip to: 1259 + /* 1224 */ MCD_OPC_Decode, + 167, + 14, + 130, + 1, // Opcode: LD + /* 1229 */ MCD_OPC_FilterValue, + 60, + 10, + 0, + 0, // Skip to: 1244 + /* 1234 */ MCD_OPC_CheckPredicate, + 95, + 20, + 0, + 0, // Skip to: 1259 + /* 1239 */ MCD_OPC_Decode, + 245, + 18, + 130, + 1, // Opcode: SCD + /* 1244 */ MCD_OPC_FilterValue, + 63, + 10, + 0, + 0, // Skip to: 1259 + /* 1249 */ MCD_OPC_CheckPredicate, + 91, + 5, + 0, + 0, // Skip to: 1259 + /* 1254 */ MCD_OPC_Decode, + 252, + 18, + 130, + 1, // Opcode: SD + /* 1259 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableMipsDSP32[] = { + /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 18 + /* 8 */ MCD_OPC_CheckPredicate, 97, 20, 0, 0, // Skip to: 33 + /* 13 */ MCD_OPC_Decode, 236, 14, 130, 1, // Opcode: LWDSP + /* 18 */ MCD_OPC_FilterValue, 43, 10, 0, 0, // Skip to: 33 + /* 23 */ MCD_OPC_CheckPredicate, 97, 5, 0, 0, // Skip to: 33 + /* 28 */ MCD_OPC_Decode, 143, 21, 130, 1, // Opcode: SWDSP + /* 33 */ MCD_OPC_Fail, 0}; + +static const uint8_t DecoderTableMipsFP6432[] = { + /* 0 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3 */ MCD_OPC_FilterValue, + 17, + 249, + 5, + 0, // Skip to: 1537 + /* 8 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 121, + 0, + 0, // Skip to: 137 + /* 16 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 41 + /* 24 */ MCD_OPC_CheckPredicate, + 98, + 158, + 6, + 0, // Skip to: 1723 + /* 29 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 151, + 6, + 0, // Skip to: 1723 + /* 36 */ MCD_OPC_Decode, + 215, + 15, + 250, + 2, // Opcode: MFC1_D64 + /* 41 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 63 + /* 46 */ MCD_OPC_CheckPredicate, + 99, + 136, + 6, + 0, // Skip to: 1723 + /* 51 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 129, + 6, + 0, // Skip to: 1723 + /* 58 */ MCD_OPC_Decode, + 225, + 15, + 250, + 2, // Opcode: MFHC1_D64 + /* 63 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 85 + /* 68 */ MCD_OPC_CheckPredicate, + 98, + 114, + 6, + 0, // Skip to: 1723 + /* 73 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 107, + 6, + 0, // Skip to: 1723 + /* 80 */ MCD_OPC_Decode, + 230, + 16, + 251, + 2, // Opcode: MTC1_D64 + /* 85 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 107 + /* 90 */ MCD_OPC_CheckPredicate, + 99, + 92, + 6, + 0, // Skip to: 1723 + /* 95 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 85, + 6, + 0, // Skip to: 1723 + /* 102 */ MCD_OPC_Decode, + 241, + 16, + 252, + 2, // Opcode: MTHC1_D64 + /* 107 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 122 + /* 112 */ MCD_OPC_CheckPredicate, + 98, + 70, + 6, + 0, // Skip to: 1723 + /* 117 */ MCD_OPC_Decode, + 147, + 12, + 219, + 2, // Opcode: FADD_D64 + /* 122 */ MCD_OPC_FilterValue, + 22, + 60, + 6, + 0, // Skip to: 1723 + /* 127 */ MCD_OPC_CheckPredicate, + 100, + 55, + 6, + 0, // Skip to: 1723 + /* 132 */ MCD_OPC_Decode, + 149, + 12, + 219, + 2, // Opcode: FADD_PS64 + /* 137 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 175 + /* 142 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 145 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 160 + /* 150 */ MCD_OPC_CheckPredicate, + 98, + 32, + 6, + 0, // Skip to: 1723 + /* 155 */ MCD_OPC_Decode, + 164, + 13, + 219, + 2, // Opcode: FSUB_D64 + /* 160 */ MCD_OPC_FilterValue, + 22, + 22, + 6, + 0, // Skip to: 1723 + /* 165 */ MCD_OPC_CheckPredicate, + 100, + 17, + 6, + 0, // Skip to: 1723 + /* 170 */ MCD_OPC_Decode, + 166, + 13, + 219, + 2, // Opcode: FSUB_PS64 + /* 175 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 213 + /* 180 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 183 */ MCD_OPC_FilterValue, + 17, + 10, + 0, + 0, // Skip to: 198 + /* 188 */ MCD_OPC_CheckPredicate, + 98, + 250, + 5, + 0, // Skip to: 1723 + /* 193 */ MCD_OPC_Decode, + 248, + 12, + 219, + 2, // Opcode: FMUL_D64 + /* 198 */ MCD_OPC_FilterValue, + 22, + 240, + 5, + 0, // Skip to: 1723 + /* 203 */ MCD_OPC_CheckPredicate, + 100, + 235, + 5, + 0, // Skip to: 1723 + /* 208 */ MCD_OPC_Decode, + 250, + 12, + 219, + 2, // Opcode: FMUL_PS64 + /* 213 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 235 + /* 218 */ MCD_OPC_CheckPredicate, + 98, + 220, + 5, + 0, // Skip to: 1723 + /* 223 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 213, + 5, + 0, // Skip to: 1723 + /* 230 */ MCD_OPC_Decode, + 186, + 12, + 219, + 2, // Opcode: FDIV_D64 + /* 235 */ MCD_OPC_FilterValue, + 4, + 18, + 0, + 0, // Skip to: 258 + /* 240 */ MCD_OPC_CheckPredicate, + 101, + 198, + 5, + 0, // Skip to: 1723 + /* 245 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 190, + 5, + 0, // Skip to: 1723 + /* 253 */ MCD_OPC_Decode, + 156, + 13, + 219, + 1, // Opcode: FSQRT_D64 + /* 258 */ MCD_OPC_FilterValue, + 5, + 18, + 0, + 0, // Skip to: 281 + /* 263 */ MCD_OPC_CheckPredicate, + 98, + 175, + 5, + 0, // Skip to: 1723 + /* 268 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 167, + 5, + 0, // Skip to: 1723 + /* 276 */ MCD_OPC_Decode, + 140, + 12, + 219, + 1, // Opcode: FABS_D64 + /* 281 */ MCD_OPC_FilterValue, + 6, + 18, + 0, + 0, // Skip to: 304 + /* 286 */ MCD_OPC_CheckPredicate, + 98, + 152, + 5, + 0, // Skip to: 1723 + /* 291 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 144, + 5, + 0, // Skip to: 1723 + /* 299 */ MCD_OPC_Decode, + 237, + 12, + 219, + 1, // Opcode: FMOV_D64 + /* 304 */ MCD_OPC_FilterValue, + 7, + 18, + 0, + 0, // Skip to: 327 + /* 309 */ MCD_OPC_CheckPredicate, + 98, + 129, + 5, + 0, // Skip to: 1723 + /* 314 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 121, + 5, + 0, // Skip to: 1723 + /* 322 */ MCD_OPC_Decode, + 129, + 13, + 219, + 1, // Opcode: FNEG_D64 + /* 327 */ MCD_OPC_FilterValue, + 8, + 35, + 0, + 0, // Skip to: 367 + /* 332 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 335 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 351 + /* 341 */ MCD_OPC_CheckPredicate, + 101, + 97, + 5, + 0, // Skip to: 1723 + /* 346 */ MCD_OPC_Decode, + 207, + 18, + 212, + 1, // Opcode: ROUND_L_S + /* 351 */ MCD_OPC_FilterValue, + 160, + 4, + 86, + 5, + 0, // Skip to: 1723 + /* 357 */ MCD_OPC_CheckPredicate, + 102, + 81, + 5, + 0, // Skip to: 1723 + /* 362 */ MCD_OPC_Decode, + 205, + 18, + 219, + 1, // Opcode: ROUND_L_D64 + /* 367 */ MCD_OPC_FilterValue, + 9, + 35, + 0, + 0, // Skip to: 407 + /* 372 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 375 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 391 + /* 381 */ MCD_OPC_CheckPredicate, + 101, + 57, + 5, + 0, // Skip to: 1723 + /* 386 */ MCD_OPC_Decode, + 245, + 21, + 212, + 1, // Opcode: TRUNC_L_S + /* 391 */ MCD_OPC_FilterValue, + 160, + 4, + 46, + 5, + 0, // Skip to: 1723 + /* 397 */ MCD_OPC_CheckPredicate, + 102, + 41, + 5, + 0, // Skip to: 1723 + /* 402 */ MCD_OPC_Decode, + 243, + 21, + 219, + 1, // Opcode: TRUNC_L_D64 + /* 407 */ MCD_OPC_FilterValue, + 10, + 35, + 0, + 0, // Skip to: 447 + /* 412 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 415 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 431 + /* 421 */ MCD_OPC_CheckPredicate, + 101, + 17, + 5, + 0, // Skip to: 1723 + /* 426 */ MCD_OPC_Decode, + 157, + 8, + 212, + 1, // Opcode: CEIL_L_S + /* 431 */ MCD_OPC_FilterValue, + 160, + 4, + 6, + 5, + 0, // Skip to: 1723 + /* 437 */ MCD_OPC_CheckPredicate, + 102, + 1, + 5, + 0, // Skip to: 1723 + /* 442 */ MCD_OPC_Decode, + 155, + 8, + 219, + 1, // Opcode: CEIL_L_D64 + /* 447 */ MCD_OPC_FilterValue, + 11, + 35, + 0, + 0, // Skip to: 487 + /* 452 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 455 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 471 + /* 461 */ MCD_OPC_CheckPredicate, + 101, + 233, + 4, + 0, // Skip to: 1723 + /* 466 */ MCD_OPC_Decode, + 216, + 12, + 212, + 1, // Opcode: FLOOR_L_S + /* 471 */ MCD_OPC_FilterValue, + 160, + 4, + 222, + 4, + 0, // Skip to: 1723 + /* 477 */ MCD_OPC_CheckPredicate, + 102, + 217, + 4, + 0, // Skip to: 1723 + /* 482 */ MCD_OPC_Decode, + 214, + 12, + 219, + 1, // Opcode: FLOOR_L_D64 + /* 487 */ MCD_OPC_FilterValue, + 12, + 18, + 0, + 0, // Skip to: 510 + /* 492 */ MCD_OPC_CheckPredicate, + 101, + 202, + 4, + 0, // Skip to: 1723 + /* 497 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 194, + 4, + 0, // Skip to: 1723 + /* 505 */ MCD_OPC_Decode, + 210, + 18, + 253, + 2, // Opcode: ROUND_W_D64 + /* 510 */ MCD_OPC_FilterValue, + 13, + 18, + 0, + 0, // Skip to: 533 + /* 515 */ MCD_OPC_CheckPredicate, + 101, + 179, + 4, + 0, // Skip to: 1723 + /* 520 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 171, + 4, + 0, // Skip to: 1723 + /* 528 */ MCD_OPC_Decode, + 248, + 21, + 253, + 2, // Opcode: TRUNC_W_D64 + /* 533 */ MCD_OPC_FilterValue, + 14, + 18, + 0, + 0, // Skip to: 556 + /* 538 */ MCD_OPC_CheckPredicate, + 101, + 156, + 4, + 0, // Skip to: 1723 + /* 543 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 148, + 4, + 0, // Skip to: 1723 + /* 551 */ MCD_OPC_Decode, + 160, + 8, + 253, + 2, // Opcode: CEIL_W_D64 + /* 556 */ MCD_OPC_FilterValue, + 15, + 18, + 0, + 0, // Skip to: 579 + /* 561 */ MCD_OPC_CheckPredicate, + 101, + 133, + 4, + 0, // Skip to: 1723 + /* 566 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 125, + 4, + 0, // Skip to: 1723 + /* 574 */ MCD_OPC_Decode, + 219, + 12, + 253, + 2, // Opcode: FLOOR_W_D64 + /* 579 */ MCD_OPC_FilterValue, + 17, + 47, + 0, + 0, // Skip to: 631 + /* 584 */ MCD_OPC_ExtractField, + 16, + 2, // Inst{17-16} ... + /* 587 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 609 + /* 592 */ MCD_OPC_CheckPredicate, + 103, + 102, + 4, + 0, // Skip to: 1723 + /* 597 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 95, + 4, + 0, // Skip to: 1723 + /* 604 */ MCD_OPC_Decode, + 164, + 16, + 254, + 2, // Opcode: MOVF_D64 + /* 609 */ MCD_OPC_FilterValue, + 1, + 85, + 4, + 0, // Skip to: 1723 + /* 614 */ MCD_OPC_CheckPredicate, + 103, + 80, + 4, + 0, // Skip to: 1723 + /* 619 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 73, + 4, + 0, // Skip to: 1723 + /* 626 */ MCD_OPC_Decode, + 184, + 16, + 254, + 2, // Opcode: MOVT_D64 + /* 631 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 653 + /* 636 */ MCD_OPC_CheckPredicate, + 103, + 58, + 4, + 0, // Skip to: 1723 + /* 641 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 51, + 4, + 0, // Skip to: 1723 + /* 648 */ MCD_OPC_Decode, + 196, + 16, + 255, + 2, // Opcode: MOVZ_I_D64 + /* 653 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 675 + /* 658 */ MCD_OPC_CheckPredicate, + 103, + 36, + 4, + 0, // Skip to: 1723 + /* 663 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 29, + 4, + 0, // Skip to: 1723 + /* 670 */ MCD_OPC_Decode, + 176, + 16, + 255, + 2, // Opcode: MOVN_I_D64 + /* 675 */ MCD_OPC_FilterValue, + 21, + 18, + 0, + 0, // Skip to: 698 + /* 680 */ MCD_OPC_CheckPredicate, + 104, + 14, + 4, + 0, // Skip to: 1723 + /* 685 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 6, + 4, + 0, // Skip to: 1723 + /* 693 */ MCD_OPC_Decode, + 185, + 18, + 219, + 1, // Opcode: RECIP_D64 + /* 698 */ MCD_OPC_FilterValue, + 22, + 18, + 0, + 0, // Skip to: 721 + /* 703 */ MCD_OPC_CheckPredicate, + 104, + 247, + 3, + 0, // Skip to: 1723 + /* 708 */ MCD_OPC_CheckField, + 16, + 10, + 160, + 4, + 239, + 3, + 0, // Skip to: 1723 + /* 716 */ MCD_OPC_Decode, + 218, + 18, + 219, + 1, // Opcode: RSQRT_D64 + /* 721 */ MCD_OPC_FilterValue, + 24, + 17, + 0, + 0, // Skip to: 743 + /* 726 */ MCD_OPC_CheckPredicate, + 105, + 224, + 3, + 0, // Skip to: 1723 + /* 731 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 217, + 3, + 0, // Skip to: 1723 + /* 738 */ MCD_OPC_Decode, + 217, + 5, + 219, + 2, // Opcode: ADDR_PS64 + /* 743 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 765 + /* 748 */ MCD_OPC_CheckPredicate, + 105, + 202, + 3, + 0, // Skip to: 1723 + /* 753 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 195, + 3, + 0, // Skip to: 1723 + /* 760 */ MCD_OPC_Decode, + 158, + 17, + 219, + 2, // Opcode: MULR_PS64 + /* 765 */ MCD_OPC_FilterValue, + 32, + 51, + 0, + 0, // Skip to: 821 + /* 770 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 773 */ MCD_OPC_FilterValue, + 160, + 4, + 10, + 0, + 0, // Skip to: 789 + /* 779 */ MCD_OPC_CheckPredicate, + 98, + 171, + 3, + 0, // Skip to: 1723 + /* 784 */ MCD_OPC_Decode, + 226, + 9, + 253, + 2, // Opcode: CVT_S_D64 + /* 789 */ MCD_OPC_FilterValue, + 160, + 5, + 10, + 0, + 0, // Skip to: 805 + /* 795 */ MCD_OPC_CheckPredicate, + 106, + 155, + 3, + 0, // Skip to: 1723 + /* 800 */ MCD_OPC_Decode, + 228, + 9, + 253, + 2, // Opcode: CVT_S_L + /* 805 */ MCD_OPC_FilterValue, + 192, + 5, + 144, + 3, + 0, // Skip to: 1723 + /* 811 */ MCD_OPC_CheckPredicate, + 100, + 139, + 3, + 0, // Skip to: 1723 + /* 816 */ MCD_OPC_Decode, + 231, + 9, + 253, + 2, // Opcode: CVT_S_PU64 + /* 821 */ MCD_OPC_FilterValue, + 33, + 51, + 0, + 0, // Skip to: 877 + /* 826 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 829 */ MCD_OPC_FilterValue, + 128, + 4, + 10, + 0, + 0, // Skip to: 845 + /* 835 */ MCD_OPC_CheckPredicate, + 98, + 115, + 3, + 0, // Skip to: 1723 + /* 840 */ MCD_OPC_Decode, + 210, + 9, + 212, + 1, // Opcode: CVT_D64_S + /* 845 */ MCD_OPC_FilterValue, + 128, + 5, + 10, + 0, + 0, // Skip to: 861 + /* 851 */ MCD_OPC_CheckPredicate, + 98, + 99, + 3, + 0, // Skip to: 1723 + /* 856 */ MCD_OPC_Decode, + 212, + 9, + 212, + 1, // Opcode: CVT_D64_W + /* 861 */ MCD_OPC_FilterValue, + 160, + 5, + 88, + 3, + 0, // Skip to: 1723 + /* 867 */ MCD_OPC_CheckPredicate, + 106, + 83, + 3, + 0, // Skip to: 1723 + /* 872 */ MCD_OPC_Decode, + 209, + 9, + 219, + 1, // Opcode: CVT_D64_L + /* 877 */ MCD_OPC_FilterValue, + 36, + 35, + 0, + 0, // Skip to: 917 + /* 882 */ MCD_OPC_ExtractField, + 16, + 10, // Inst{25-16} ... + /* 885 */ MCD_OPC_FilterValue, + 160, + 4, + 10, + 0, + 0, // Skip to: 901 + /* 891 */ MCD_OPC_CheckPredicate, + 98, + 59, + 3, + 0, // Skip to: 1723 + /* 896 */ MCD_OPC_Decode, + 237, + 9, + 253, + 2, // Opcode: CVT_W_D64 + /* 901 */ MCD_OPC_FilterValue, + 192, + 5, + 48, + 3, + 0, // Skip to: 1723 + /* 907 */ MCD_OPC_CheckPredicate, + 105, + 43, + 3, + 0, // Skip to: 1723 + /* 912 */ MCD_OPC_Decode, + 223, + 9, + 219, + 1, // Opcode: CVT_PW_PS64 + /* 917 */ MCD_OPC_FilterValue, + 38, + 40, + 0, + 0, // Skip to: 962 + /* 922 */ MCD_OPC_ExtractField, + 21, + 5, // Inst{25-21} ... + /* 925 */ MCD_OPC_FilterValue, + 16, + 10, + 0, + 0, // Skip to: 940 + /* 930 */ MCD_OPC_CheckPredicate, + 100, + 20, + 3, + 0, // Skip to: 1723 + /* 935 */ MCD_OPC_Decode, + 222, + 9, + 128, + 3, // Opcode: CVT_PS_S64 + /* 940 */ MCD_OPC_FilterValue, + 20, + 10, + 3, + 0, // Skip to: 1723 + /* 945 */ MCD_OPC_CheckPredicate, + 105, + 5, + 3, + 0, // Skip to: 1723 + /* 950 */ MCD_OPC_CheckField, + 16, + 5, + 0, + 254, + 2, + 0, // Skip to: 1723 + /* 957 */ MCD_OPC_Decode, + 221, + 9, + 219, + 1, // Opcode: CVT_PS_PW64 + /* 962 */ MCD_OPC_FilterValue, + 40, + 18, + 0, + 0, // Skip to: 985 + /* 967 */ MCD_OPC_CheckPredicate, + 100, + 239, + 2, + 0, // Skip to: 1723 + /* 972 */ MCD_OPC_CheckField, + 16, + 10, + 192, + 5, + 231, + 2, + 0, // Skip to: 1723 + /* 980 */ MCD_OPC_Decode, + 230, + 9, + 253, + 2, // Opcode: CVT_S_PL64 + /* 985 */ MCD_OPC_FilterValue, + 44, + 17, + 0, + 0, // Skip to: 1007 + /* 990 */ MCD_OPC_CheckPredicate, + 100, + 216, + 2, + 0, // Skip to: 1723 + /* 995 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 209, + 2, + 0, // Skip to: 1723 + /* 1002 */ MCD_OPC_Decode, + 254, + 17, + 219, + 2, // Opcode: PLL_PS64 + /* 1007 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 1029 + /* 1012 */ MCD_OPC_CheckPredicate, + 100, + 194, + 2, + 0, // Skip to: 1723 + /* 1017 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 187, + 2, + 0, // Skip to: 1723 + /* 1024 */ MCD_OPC_Decode, + 255, + 17, + 219, + 2, // Opcode: PLU_PS64 + /* 1029 */ MCD_OPC_FilterValue, + 46, + 17, + 0, + 0, // Skip to: 1051 + /* 1034 */ MCD_OPC_CheckPredicate, + 100, + 172, + 2, + 0, // Skip to: 1723 + /* 1039 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 165, + 2, + 0, // Skip to: 1723 + /* 1046 */ MCD_OPC_Decode, + 172, + 18, + 219, + 2, // Opcode: PUL_PS64 + /* 1051 */ MCD_OPC_FilterValue, + 47, + 17, + 0, + 0, // Skip to: 1073 + /* 1056 */ MCD_OPC_CheckPredicate, + 100, + 150, + 2, + 0, // Skip to: 1723 + /* 1061 */ MCD_OPC_CheckField, + 21, + 5, + 22, + 143, + 2, + 0, // Skip to: 1723 + /* 1068 */ MCD_OPC_Decode, + 173, + 18, + 219, + 2, // Opcode: PUU_PS64 + /* 1073 */ MCD_OPC_FilterValue, + 48, + 24, + 0, + 0, // Skip to: 1102 + /* 1078 */ MCD_OPC_CheckPredicate, + 107, + 128, + 2, + 0, // Skip to: 1723 + /* 1083 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 121, + 2, + 0, // Skip to: 1723 + /* 1090 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 114, + 2, + 0, // Skip to: 1723 + /* 1097 */ MCD_OPC_Decode, + 250, + 9, + 129, + 3, // Opcode: C_F_D64 + /* 1102 */ MCD_OPC_FilterValue, + 49, + 24, + 0, + 0, // Skip to: 1131 + /* 1107 */ MCD_OPC_CheckPredicate, + 107, + 99, + 2, + 0, // Skip to: 1723 + /* 1112 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 92, + 2, + 0, // Skip to: 1723 + /* 1119 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 85, + 2, + 0, // Skip to: 1723 + /* 1126 */ MCD_OPC_Decode, + 206, + 10, + 129, + 3, // Opcode: C_UN_D64 + /* 1131 */ MCD_OPC_FilterValue, + 50, + 24, + 0, + 0, // Skip to: 1160 + /* 1136 */ MCD_OPC_CheckPredicate, + 107, + 70, + 2, + 0, // Skip to: 1723 + /* 1141 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 63, + 2, + 0, // Skip to: 1723 + /* 1148 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 56, + 2, + 0, // Skip to: 1723 + /* 1155 */ MCD_OPC_Decode, + 244, + 9, + 129, + 3, // Opcode: C_EQ_D64 + /* 1160 */ MCD_OPC_FilterValue, + 51, + 24, + 0, + 0, // Skip to: 1189 + /* 1165 */ MCD_OPC_CheckPredicate, + 107, + 41, + 2, + 0, // Skip to: 1723 + /* 1170 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 34, + 2, + 0, // Skip to: 1723 + /* 1177 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 27, + 2, + 0, // Skip to: 1723 + /* 1184 */ MCD_OPC_Decode, + 188, + 10, + 129, + 3, // Opcode: C_UEQ_D64 + /* 1189 */ MCD_OPC_FilterValue, + 52, + 24, + 0, + 0, // Skip to: 1218 + /* 1194 */ MCD_OPC_CheckPredicate, + 107, + 12, + 2, + 0, // Skip to: 1723 + /* 1199 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 5, + 2, + 0, // Skip to: 1723 + /* 1206 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 254, + 1, + 0, // Skip to: 1723 + /* 1213 */ MCD_OPC_Decode, + 170, + 10, + 129, + 3, // Opcode: C_OLT_D64 + /* 1218 */ MCD_OPC_FilterValue, + 53, + 24, + 0, + 0, // Skip to: 1247 + /* 1223 */ MCD_OPC_CheckPredicate, + 107, + 239, + 1, + 0, // Skip to: 1723 + /* 1228 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 232, + 1, + 0, // Skip to: 1723 + /* 1235 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 225, + 1, + 0, // Skip to: 1723 + /* 1242 */ MCD_OPC_Decode, + 200, + 10, + 129, + 3, // Opcode: C_ULT_D64 + /* 1247 */ MCD_OPC_FilterValue, + 54, + 24, + 0, + 0, // Skip to: 1276 + /* 1252 */ MCD_OPC_CheckPredicate, + 107, + 210, + 1, + 0, // Skip to: 1723 + /* 1257 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 203, + 1, + 0, // Skip to: 1723 + /* 1264 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 196, + 1, + 0, // Skip to: 1723 + /* 1271 */ MCD_OPC_Decode, + 164, + 10, + 129, + 3, // Opcode: C_OLE_D64 + /* 1276 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 1305 + /* 1281 */ MCD_OPC_CheckPredicate, + 107, + 181, + 1, + 0, // Skip to: 1723 + /* 1286 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 174, + 1, + 0, // Skip to: 1723 + /* 1293 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 167, + 1, + 0, // Skip to: 1723 + /* 1300 */ MCD_OPC_Decode, + 194, + 10, + 129, + 3, // Opcode: C_ULE_D64 + /* 1305 */ MCD_OPC_FilterValue, + 56, + 24, + 0, + 0, // Skip to: 1334 + /* 1310 */ MCD_OPC_CheckPredicate, + 107, + 152, + 1, + 0, // Skip to: 1723 + /* 1315 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 145, + 1, + 0, // Skip to: 1723 + /* 1322 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 138, + 1, + 0, // Skip to: 1723 + /* 1329 */ MCD_OPC_Decode, + 182, + 10, + 129, + 3, // Opcode: C_SF_D64 + /* 1334 */ MCD_OPC_FilterValue, + 57, + 24, + 0, + 0, // Skip to: 1363 + /* 1339 */ MCD_OPC_CheckPredicate, + 107, + 123, + 1, + 0, // Skip to: 1723 + /* 1344 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 116, + 1, + 0, // Skip to: 1723 + /* 1351 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 109, + 1, + 0, // Skip to: 1723 + /* 1358 */ MCD_OPC_Decode, + 146, + 10, + 129, + 3, // Opcode: C_NGLE_D64 + /* 1363 */ MCD_OPC_FilterValue, + 58, + 24, + 0, + 0, // Skip to: 1392 + /* 1368 */ MCD_OPC_CheckPredicate, + 107, + 94, + 1, + 0, // Skip to: 1723 + /* 1373 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 87, + 1, + 0, // Skip to: 1723 + /* 1380 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 80, + 1, + 0, // Skip to: 1723 + /* 1387 */ MCD_OPC_Decode, + 176, + 10, + 129, + 3, // Opcode: C_SEQ_D64 + /* 1392 */ MCD_OPC_FilterValue, + 59, + 24, + 0, + 0, // Skip to: 1421 + /* 1397 */ MCD_OPC_CheckPredicate, + 107, + 65, + 1, + 0, // Skip to: 1723 + /* 1402 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 58, + 1, + 0, // Skip to: 1723 + /* 1409 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 51, + 1, + 0, // Skip to: 1723 + /* 1416 */ MCD_OPC_Decode, + 152, + 10, + 129, + 3, // Opcode: C_NGL_D64 + /* 1421 */ MCD_OPC_FilterValue, + 60, + 24, + 0, + 0, // Skip to: 1450 + /* 1426 */ MCD_OPC_CheckPredicate, + 107, + 36, + 1, + 0, // Skip to: 1723 + /* 1431 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 29, + 1, + 0, // Skip to: 1723 + /* 1438 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 22, + 1, + 0, // Skip to: 1723 + /* 1445 */ MCD_OPC_Decode, + 134, + 10, + 129, + 3, // Opcode: C_LT_D64 + /* 1450 */ MCD_OPC_FilterValue, + 61, + 24, + 0, + 0, // Skip to: 1479 + /* 1455 */ MCD_OPC_CheckPredicate, + 107, + 7, + 1, + 0, // Skip to: 1723 + /* 1460 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 0, + 1, + 0, // Skip to: 1723 + /* 1467 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 249, + 0, + 0, // Skip to: 1723 + /* 1474 */ MCD_OPC_Decode, + 140, + 10, + 129, + 3, // Opcode: C_NGE_D64 + /* 1479 */ MCD_OPC_FilterValue, + 62, + 24, + 0, + 0, // Skip to: 1508 + /* 1484 */ MCD_OPC_CheckPredicate, + 107, + 234, + 0, + 0, // Skip to: 1723 + /* 1489 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 227, + 0, + 0, // Skip to: 1723 + /* 1496 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 220, + 0, + 0, // Skip to: 1723 + /* 1503 */ MCD_OPC_Decode, + 128, + 10, + 129, + 3, // Opcode: C_LE_D64 + /* 1508 */ MCD_OPC_FilterValue, + 63, + 210, + 0, + 0, // Skip to: 1723 + /* 1513 */ MCD_OPC_CheckPredicate, + 107, + 205, + 0, + 0, // Skip to: 1723 + /* 1518 */ MCD_OPC_CheckField, + 21, + 5, + 17, + 198, + 0, + 0, // Skip to: 1723 + /* 1525 */ MCD_OPC_CheckField, + 6, + 2, + 0, + 191, + 0, + 0, // Skip to: 1723 + /* 1532 */ MCD_OPC_Decode, + 158, + 10, + 129, + 3, // Opcode: C_NGT_D64 + /* 1537 */ MCD_OPC_FilterValue, + 19, + 151, + 0, + 0, // Skip to: 1693 + /* 1542 */ MCD_OPC_ExtractField, + 0, + 6, // Inst{5-0} ... + /* 1545 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 1567 + /* 1550 */ MCD_OPC_CheckPredicate, + 108, + 168, + 0, + 0, // Skip to: 1723 + /* 1555 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 161, + 0, + 0, // Skip to: 1723 + /* 1562 */ MCD_OPC_Decode, + 184, + 14, + 130, + 3, // Opcode: LDXC164 + /* 1567 */ MCD_OPC_FilterValue, + 5, + 17, + 0, + 0, // Skip to: 1589 + /* 1572 */ MCD_OPC_CheckPredicate, + 109, + 146, + 0, + 0, // Skip to: 1723 + /* 1577 */ MCD_OPC_CheckField, + 11, + 5, + 0, + 139, + 0, + 0, // Skip to: 1723 + /* 1584 */ MCD_OPC_Decode, + 222, + 14, + 130, + 3, // Opcode: LUXC164 + /* 1589 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 1611 + /* 1594 */ MCD_OPC_CheckPredicate, + 108, + 124, + 0, + 0, // Skip to: 1723 + /* 1599 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 117, + 0, + 0, // Skip to: 1723 + /* 1606 */ MCD_OPC_Decode, + 144, + 19, + 131, + 3, // Opcode: SDXC164 + /* 1611 */ MCD_OPC_FilterValue, + 13, + 17, + 0, + 0, // Skip to: 1633 + /* 1616 */ MCD_OPC_CheckPredicate, + 109, + 102, + 0, + 0, // Skip to: 1723 + /* 1621 */ MCD_OPC_CheckField, + 6, + 5, + 0, + 95, + 0, + 0, // Skip to: 1723 + /* 1628 */ MCD_OPC_Decode, + 131, + 21, + 131, + 3, // Opcode: SUXC164 + /* 1633 */ MCD_OPC_FilterValue, + 33, + 10, + 0, + 0, // Skip to: 1648 + /* 1638 */ MCD_OPC_CheckPredicate, + 110, + 80, + 0, + 0, // Skip to: 1723 + /* 1643 */ MCD_OPC_Decode, + 168, + 15, + 132, + 3, // Opcode: MADD_D64 + /* 1648 */ MCD_OPC_FilterValue, + 41, + 10, + 0, + 0, // Skip to: 1663 + /* 1653 */ MCD_OPC_CheckPredicate, + 110, + 65, + 0, + 0, // Skip to: 1723 + /* 1658 */ MCD_OPC_Decode, + 219, + 16, + 132, + 3, // Opcode: MSUB_D64 + /* 1663 */ MCD_OPC_FilterValue, + 49, + 10, + 0, + 0, // Skip to: 1678 + /* 1668 */ MCD_OPC_CheckPredicate, + 111, + 50, + 0, + 0, // Skip to: 1723 + /* 1673 */ MCD_OPC_Decode, + 202, + 17, + 132, + 3, // Opcode: NMADD_D64 + /* 1678 */ MCD_OPC_FilterValue, + 57, + 40, + 0, + 0, // Skip to: 1723 + /* 1683 */ MCD_OPC_CheckPredicate, + 111, + 35, + 0, + 0, // Skip to: 1723 + /* 1688 */ MCD_OPC_Decode, + 207, + 17, + 132, + 3, // Opcode: NMSUB_D64 + /* 1693 */ MCD_OPC_FilterValue, + 53, + 10, + 0, + 0, // Skip to: 1708 + /* 1698 */ MCD_OPC_CheckPredicate, + 101, + 20, + 0, + 0, // Skip to: 1723 + /* 1703 */ MCD_OPC_Decode, + 169, + 14, + 208, + 2, // Opcode: LDC164 + /* 1708 */ MCD_OPC_FilterValue, + 61, + 10, + 0, + 0, // Skip to: 1723 + /* 1713 */ MCD_OPC_CheckPredicate, + 101, + 5, + 0, + 0, // Skip to: 1723 + /* 1718 */ MCD_OPC_Decode, + 132, + 19, + 208, + 2, // Opcode: SDC164 + /* 1723 */ MCD_OPC_Fail, + 0}; -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ +static bool getbool(uint64_t b) { return b != 0; } +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { - default: // llvm_unreachable("Invalid index!"); + default: + llvm_unreachable("Invalid index!"); case 0: - return getbool((Bits & Mips_FeatureMips16)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 1)); case 1: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureCnMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 2: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureCnMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 3: - return getbool((Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureCnMips, 1)); case 4: - return getbool((Bits & Mips_FeatureMips32) && (Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips64, 1) && + checkFeatureRequired(Bits, Mips_FeatureCnMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 5: - return getbool(!(Bits & Mips_FeatureMips16)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureCnMipsP, 1)); case 6: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0)); case 7: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1)); case 8: - return getbool((Bits & Mips_FeatureMSA)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureDSP, 1)); case 9: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureDSPR2, 1)); case 10: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r5, 1) && + checkFeatureRequired(Bits, Mips_FeatureVirt, 1)); case 11: - return getbool(!(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureDSPR3, 1)); case 12: - return getbool((Bits & Mips_FeatureDSP)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureDSP, 1)); case 13: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 14: - return getbool((Bits & Mips_FeatureMSA) && (Bits & Mips_FeatureMips64)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); case 15: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 16: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); case 17: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 18: - return getbool(!(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 19: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 20: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 21: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureEVA, 1)); case 22: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32r2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureEVA, 1)); case 23: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 24: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1)); case 25: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureGINV, 1)); case 26: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMicroMips, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); case 27: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 28: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 29: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 30: - return getbool((Bits & Mips_FeatureDSPR2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMSA, 1)); case 31: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 32: - return getbool((Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0)); case 33: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool( + checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureUseIndirectJumpsHazard, 0)); case 34: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32, 1)); case 35: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 36: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 37: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureDSP, 1)); case 38: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMSA, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64, 1)); case 39: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 40: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureDSP, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 41: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r5, 1) && + checkFeatureRequired(Bits, Mips_FeatureVirt, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 42: - return getbool((Bits & Mips_FeatureMips64)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMT, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 43: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && (Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureEVA, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 44: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 45: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && (Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r5, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 46: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 47: - return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && (Bits & Mips_FeatureFP64Bit)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 48: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 49: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 50: - return getbool((Bits & Mips_FeatureCnMips)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 51: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64) && !(Bits & Mips_FeatureMips64r6)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); case 52: - return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 53: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); + case 54: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 55: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 56: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 57: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 58: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 59: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 60: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 61: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); + case 62: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 63: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips5_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 64: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); + case 65: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); + case 66: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 67: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 68: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 69: + return getbool(checkFeatureRequired(Bits, Mips_FeatureDSPR2, 1)); + case 70: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureEVA, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 71: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 72: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 73: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 74: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 75: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1)); + case 76: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 77: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 78: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 79: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 80: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureCRC, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 81: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureCRC, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 82: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 83: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureGINV, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 84: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1)); + case 85: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1)); + case 86: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 1)); + case 87: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 88: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 89: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeaturePTR64Bit, 1)); + case 90: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 91: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 92: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 93: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1)); + case 94: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r5, 1) && + checkFeatureRequired(Bits, Mips_FeatureVirt, 1)); + case 95: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0)); + case 96: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureGP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 97: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureDSP, 1)); + case 98: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 99: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 100: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 101: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 102: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 103: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 104: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 105: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips3D, 1)); + case 106: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips3_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 107: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 108: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0)); + case 109: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips5_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); + case 110: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0)); + case 111: + return getbool(checkFeatureRequired(Bits, Mips_FeatureMips16, 0) && + checkFeatureRequired(Bits, Mips_FeatureFP64Bit, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips4_32r2, 1) && + checkFeatureRequired(Bits, Mips_FeatureMips32r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureMips64r6, 0) && + checkFeatureRequired(Bits, Mips_FeatureSoftFloat, 0) && + checkFeatureRequired(Bits, Mips_FeatureNoMadd4, 0) && + checkFeatureRequired(Bits, Mips_FeatureMicroMips, 0)); } } -#define DecodeToMCInst(fname,fieldname, InsnType) \ -static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, void *Decoder) \ -{ \ - InsnType tmp; \ - switch (Idx) { \ - default: \ - case 0: \ - return S; \ - case 1: \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 2: \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 3: \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 2) << 3; \ - tmp |= fieldname(insn, 5, 3) << 0; \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 4: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 5: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 6: \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 7: \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 8: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 11; \ - tmp |= fieldname(insn, 21, 6) << 5; \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 9: \ - tmp = fieldname(insn, 5, 3); \ - if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 10: \ - if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 11: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 12: \ - if (DecodeMemMMImm4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 13: \ - tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 14: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 15: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 16: \ - tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 17: \ - tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 3, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 18: \ - if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 19: \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 20: \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 21: \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeUImm5lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 22: \ - if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 23: \ - tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 4); \ - if (DecodeSimm4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 24: \ - tmp = fieldname(insn, 1, 9); \ - if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 25: \ - if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 26: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 27: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 6); \ - if (DecodeUImm6Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 28: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 1, 3); \ - if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 3); \ - if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 29: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 7); \ - if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 30: \ - tmp = fieldname(insn, 0, 10); \ - if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 31: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 7); \ - if (DecodeLiSimm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 32: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 33: \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 6, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 34: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 35: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 36: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 37: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 38: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 39: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 40: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 41: \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 42: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 43: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 44: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 45: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 46: \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 47: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 48: \ - if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 49: \ - if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 50: \ - if (DecodeCacheOpMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 51: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 52: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 53: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 54: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 13, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 55: \ - if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 56: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 23); \ - if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 57: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 58: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 59: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 60: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 61: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 62: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 63: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 64: \ - tmp = fieldname(insn, 6, 20); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 65: \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 66: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 67: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 68: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 69: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 70: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 71: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 72: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 73: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 74: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 75: \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 76: \ - if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 77: \ - if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 78: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 79: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 80: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 81: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 82: \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 83: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 84: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 85: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 86: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 87: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 88: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 89: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 90: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 91: \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 92: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 93: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 94: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 95: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 96: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 97: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 98: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 99: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 100: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 101: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 102: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 103: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 104: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 105: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 106: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 107: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 108: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 109: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 110: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 111: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 112: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 113: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 114: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 115: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 116: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 117: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 118: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 119: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 120: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 121: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 122: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 123: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 124: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 125: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 126: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 127: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 128: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 129: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 130: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 131: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 132: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 133: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 134: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 135: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 136: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 137: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 138: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 139: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 140: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 141: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 142: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 143: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 144: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 145: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 146: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 147: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 148: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 149: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 150: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 151: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 152: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 153: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 154: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 155: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 156: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 157: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 158: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 159: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 160: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 161: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 162: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 163: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 164: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 165: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 166: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 167: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 168: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 169: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 170: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 171: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 172: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 173: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 174: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 175: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 176: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 177: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 178: \ - if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 179: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 180: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 181: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 182: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 183: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 184: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 185: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 186: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 187: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 188: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 189: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 190: \ - if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 191: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 192: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 193: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 194: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 195: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 196: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 197: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 198: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 199: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 200: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 201: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 202: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 203: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 204: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 205: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 206: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 207: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 208: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 209: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 210: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 211: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 212: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 213: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 214: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 6); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 215: \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 216: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 217: \ - if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 218: \ - if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 219: \ - if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 220: \ - if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 221: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 222: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 223: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 224: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 225: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 226: \ - if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 227: \ - if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 228: \ - if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 229: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 230: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 231: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 232: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 233: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 234: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 235: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 236: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 237: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 238: \ - if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 239: \ - if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 240: \ - if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 241: \ - if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 242: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 243: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 244: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 245: \ - if (DecodeCacheOpR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 246: \ - if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 247: \ - tmp = fieldname(insn, 0, 26); \ - if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 248: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 21); \ - if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 249: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 19); \ - if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 250: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 18); \ - if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 251: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 252: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 253: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 254: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 255: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 256: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 257: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 258: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 259: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 260: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 261: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 262: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 263: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 264: \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 265: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 266: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 267: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 268: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 269: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 270: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 271: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 6, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 272: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 16); \ - if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - } \ -} +#define DecodeToMCInst(fname, fieldname, InsnType) \ + static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, \ + MCInst *MI, uint64_t Address, bool *Decoder) { \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + llvm_unreachable("Invalid index!"); \ + case 0: \ + return S; \ + case 1: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 2: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 3: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 3, 2) << 3; \ + tmp |= fieldname(insn, 5, 3) << 0; \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 5: \ + tmp = fieldname(insn, 2, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 6: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 7: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 8: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 11; \ + tmp |= fieldname(insn, 21, 6) << 5; \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 9: \ + tmp = fieldname(insn, 5, 3); \ + if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 10: \ + if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 11: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 12: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 13: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 14: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 15: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 16: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 10); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 10) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 18: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 21: \ + if (DecodeMemMMImm4(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodePOOL16BEncodedField(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 3, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 26: \ + tmp = fieldname(insn, 3, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 3, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 27: \ + if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 30: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeUImmWithOffsetAndScale(MI, tmp, Address, Decoder, 5, 0, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 31: \ + if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 4); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 1, 9); \ + if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 34: \ + if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 35: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 1, 6); \ + if (DecodeUImmWithOffsetAndScale(MI, tmp, Address, Decoder, 6, 0, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 37: \ + if (DecodeMovePOperands(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 7); \ + if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 0, 10); \ + if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 7); \ + if (DecodeLi16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 41: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 42: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 45: \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 6, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 46: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 47: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 48: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 49: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 50: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 51: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 52: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 53: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 55: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 5, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 57: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 58: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 59: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 60: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 61: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 62: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 64: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 65: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 66: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 68: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 69: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 70: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 72: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 73: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 74: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 75: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 76: \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 77: \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 78: \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 79: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 80: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 82: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 83: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 7); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 84: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 85: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 10); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 10) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 86: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 87: \ + if (DecodeMemMMImm16(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 88: \ + if (DecodeMemMMImm12(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 89: \ + if (DecodeCacheOpMM(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 90: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 91: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 92: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 93: \ + if (DecodeSyncI_MM(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 94: \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget1SImm16(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 95: \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 96: \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 97: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 98: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 99: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 100: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 101: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 102: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 103: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 104: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 105: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 106: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 107: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 108: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 109: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 110: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 111: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 112: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 113: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 114: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 115: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 116: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 117: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 118: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 119: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 120: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 121: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 122: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 123: \ + if (DecodeMemMMImm9(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 124: \ + if (DecodePrefeOpMM(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 125: \ + if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 126: \ + tmp = fieldname(insn, 23, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 23); \ + if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 127: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 128: \ + if (DecodeFMemMMR2(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 129: \ + if (DecodeJumpTargetXMM(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 130: \ + if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 131: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 132: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 133: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 134: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 135: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 136: \ + tmp = fieldname(insn, 1, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 137: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 138: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 139: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 140: \ + tmp = fieldname(insn, 5, 5); \ + if (DecodeUImmWithOffsetAndScale(MI, tmp, Address, Decoder, 5, 0, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 141: \ + tmp = fieldname(insn, 6, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 142: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 143: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 2); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 2, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 144: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 145: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 146: \ + tmp = fieldname(insn, 6, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 147: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 148: \ + if (DecodeLoadByte15(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 149: \ + if (DecodeFMemCop2MMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 150: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 151: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 152: \ + if (DecodeSynciR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 153: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 154: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 155: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 156: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 157: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 158: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 159: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 160: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 161: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 162: \ + if (DecodePOP35GroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 163: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 19); \ + if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 164: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 165: \ + if (DecodePOP37GroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 166: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 21); \ + if (DecodeBranchTarget21MM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 167: \ + tmp = fieldname(insn, 0, 26); \ + if (DecodeBranchTarget26MM(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 168: \ + if (DecodeBlezGroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 169: \ + if (DecodePOP65GroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 170: \ + if (DecodeBgtzGroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 171: \ + if (DecodePOP75GroupBranchMMR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 172: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 173: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 174: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 2); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 2, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 175: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 176: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 177: \ + tmp = fieldname(insn, 6, 20); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 178: \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 179: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 180: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 181: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 182: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 183: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 2); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 2, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 184: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 185: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 186: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 187: \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 188: \ + if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 189: \ + if (DecodeJumpTarget(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 190: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 191: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 192: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 193: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 194: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 195: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 4, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 196: \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 197: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 198: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 199: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 200: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 201: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 202: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 203: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 204: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 205: \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 206: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 207: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 208: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 209: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 210: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 211: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 212: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 213: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 214: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 215: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 216: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 217: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 218: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 219: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 220: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 221: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 222: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 223: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 224: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 225: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 226: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 227: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 228: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 229: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 230: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 231: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 232: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 233: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 234: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 235: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 236: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 237: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 238: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 239: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 240: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 241: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 242: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 243: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 244: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 245: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 246: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 247: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 248: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 249: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 250: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 251: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 252: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 253: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 254: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 255: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 256: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 257: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 258: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 259: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 260: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 261: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 262: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 263: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 264: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 265: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 266: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 267: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 268: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 269: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 270: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 271: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 272: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 273: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 274: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 275: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 276: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 277: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 278: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 279: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 280: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 281: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 282: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 283: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 284: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 285: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 286: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 287: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 288: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 289: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 290: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 291: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 292: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 293: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 294: \ + if (DecodeINSVE_DF(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 295: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 296: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 297: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 298: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 299: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 300: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 301: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 302: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 303: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 304: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 305: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 306: \ + if (DecodeMSA128Mem(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 307: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeUImmWithOffset(MI, tmp, Address, Decoder, 5, 1) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 308: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 309: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 310: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 311: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 312: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 313: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 314: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 315: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 316: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 317: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 318: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 319: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 320: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 321: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 322: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 323: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 324: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 325: \ + if (DecodeMemEVA(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 326: \ + if (DecodeCacheeOp_CacheOpR6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 327: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 328: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 329: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 330: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 331: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 332: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 6); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 333: \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 334: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 335: \ + if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 336: \ + if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 337: \ + if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 338: \ + if (DecodeDAHIDATI(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 339: \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 340: \ + if (DecodeBlezGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 341: \ + if (DecodeBgtzGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 342: \ + if (DecodeAddiGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 343: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 344: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 345: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 346: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 347: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 348: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 349: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 350: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeBranchTarget(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 351: \ + if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 352: \ + if (DecodeBlezlGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 353: \ + if (DecodeBgtzlGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 354: \ + if (DecodeDaddiGroupBranch(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 355: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 356: \ + if (DecodeCRC(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 357: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 358: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 359: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 360: \ + if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 361: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 362: \ + tmp = fieldname(insn, 0, 26); \ + if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 363: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 21); \ + if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 364: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 18); \ + if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 365: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 21); \ + if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 366: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 367: \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 368: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 369: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 370: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 371: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 372: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 373: \ + tmp = fieldname(insn, 13, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 374: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (DecodeSImmWithOffsetAndScale(MI, tmp, Address, Decoder, 16) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 375: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 376: \ + if (DecodeDEXT(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 377: \ + if (DecodeDINS(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 378: \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 379: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 380: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 381: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 382: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 18, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 383: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 384: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 385: \ + tmp = fieldname(insn, 8, 3); \ + if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 386: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 387: \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 388: \ + tmp = fieldname(insn, 6, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 5); \ + if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + } \ + } -#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ -{ \ - uint64_t Bits = getFeatureBits(feature); \ - const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0, ExpectedValue; \ - DecodeStatus S = MCDisassembler_Success; \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail; \ - for (;;) { \ - switch (*Ptr) { \ - default: \ - return MCDisassembler_Fail; \ - case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - ++Ptr; \ - CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ - break; \ - } \ - case MCD_OPC_FilterValue: { \ - Val = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (Val != CurFieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (ExpectedValue != FieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckPredicate: { \ - PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - Pred = checkDecoderPredicate(PIdx, Bits); \ - if (!Pred) \ - Ptr += NumToSkip; \ - (void)Pred; \ - break; \ - } \ - case MCD_OPC_Decode: { \ - Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - MCInst_setOpcode(MI, Opc); \ - return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ - } \ - case MCD_OPC_SoftFail: { \ - PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ - if (Fail) \ - S = MCDisassembler_SoftFail; \ - break; \ - } \ - case MCD_OPC_Fail: { \ - return MCDisassembler_Fail; \ - } \ - } \ - } \ -} +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ + static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + MCRegisterInfo *MRI, int feature) { \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, feature))) \ + Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could \ + * be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ + } FieldFromInstruction(fieldFromInstruction, uint32_t) -DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) -DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) + DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) + DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) + +#endif // MIPS_GET_DISASSEMBLER +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +#define Mips_AT 1 +#define Mips_DSPCCond 2 +#define Mips_DSPCarry 3 +#define Mips_DSPEFI 4 +#define Mips_DSPOutFlag 5 +#define Mips_DSPPos 6 +#define Mips_DSPSCount 7 +#define Mips_FP 8 +#define Mips_GP 9 +#define Mips_MSAAccess 10 +#define Mips_MSACSR 11 +#define Mips_MSAIR 12 +#define Mips_MSAMap 13 +#define Mips_MSAModify 14 +#define Mips_MSARequest 15 +#define Mips_MSASave 16 +#define Mips_MSAUnmap 17 +#define Mips_PC 18 +#define Mips_RA 19 +#define Mips_SP 20 +#define Mips_ZERO 21 +#define Mips_A0 22 +#define Mips_A1 23 +#define Mips_A2 24 +#define Mips_A3 25 +#define Mips_AC0 26 +#define Mips_AC1 27 +#define Mips_AC2 28 +#define Mips_AC3 29 +#define Mips_AT_64 30 +#define Mips_COP00 31 +#define Mips_COP01 32 +#define Mips_COP02 33 +#define Mips_COP03 34 +#define Mips_COP04 35 +#define Mips_COP05 36 +#define Mips_COP06 37 +#define Mips_COP07 38 +#define Mips_COP08 39 +#define Mips_COP09 40 +#define Mips_COP20 41 +#define Mips_COP21 42 +#define Mips_COP22 43 +#define Mips_COP23 44 +#define Mips_COP24 45 +#define Mips_COP25 46 +#define Mips_COP26 47 +#define Mips_COP27 48 +#define Mips_COP28 49 +#define Mips_COP29 50 +#define Mips_COP30 51 +#define Mips_COP31 52 +#define Mips_COP32 53 +#define Mips_COP33 54 +#define Mips_COP34 55 +#define Mips_COP35 56 +#define Mips_COP36 57 +#define Mips_COP37 58 +#define Mips_COP38 59 +#define Mips_COP39 60 +#define Mips_COP010 61 +#define Mips_COP011 62 +#define Mips_COP012 63 +#define Mips_COP013 64 +#define Mips_COP014 65 +#define Mips_COP015 66 +#define Mips_COP016 67 +#define Mips_COP017 68 +#define Mips_COP018 69 +#define Mips_COP019 70 +#define Mips_COP020 71 +#define Mips_COP021 72 +#define Mips_COP022 73 +#define Mips_COP023 74 +#define Mips_COP024 75 +#define Mips_COP025 76 +#define Mips_COP026 77 +#define Mips_COP027 78 +#define Mips_COP028 79 +#define Mips_COP029 80 +#define Mips_COP030 81 +#define Mips_COP031 82 +#define Mips_COP210 83 +#define Mips_COP211 84 +#define Mips_COP212 85 +#define Mips_COP213 86 +#define Mips_COP214 87 +#define Mips_COP215 88 +#define Mips_COP216 89 +#define Mips_COP217 90 +#define Mips_COP218 91 +#define Mips_COP219 92 +#define Mips_COP220 93 +#define Mips_COP221 94 +#define Mips_COP222 95 +#define Mips_COP223 96 +#define Mips_COP224 97 +#define Mips_COP225 98 +#define Mips_COP226 99 +#define Mips_COP227 100 +#define Mips_COP228 101 +#define Mips_COP229 102 +#define Mips_COP230 103 +#define Mips_COP231 104 +#define Mips_COP310 105 +#define Mips_COP311 106 +#define Mips_COP312 107 +#define Mips_COP313 108 +#define Mips_COP314 109 +#define Mips_COP315 110 +#define Mips_COP316 111 +#define Mips_COP317 112 +#define Mips_COP318 113 +#define Mips_COP319 114 +#define Mips_COP320 115 +#define Mips_COP321 116 +#define Mips_COP322 117 +#define Mips_COP323 118 +#define Mips_COP324 119 +#define Mips_COP325 120 +#define Mips_COP326 121 +#define Mips_COP327 122 +#define Mips_COP328 123 +#define Mips_COP329 124 +#define Mips_COP330 125 +#define Mips_COP331 126 +#define Mips_D0 127 +#define Mips_D1 128 +#define Mips_D2 129 +#define Mips_D3 130 +#define Mips_D4 131 +#define Mips_D5 132 +#define Mips_D6 133 +#define Mips_D7 134 +#define Mips_D8 135 +#define Mips_D9 136 +#define Mips_D10 137 +#define Mips_D11 138 +#define Mips_D12 139 +#define Mips_D13 140 +#define Mips_D14 141 +#define Mips_D15 142 +#define Mips_DSPOutFlag20 143 +#define Mips_DSPOutFlag21 144 +#define Mips_DSPOutFlag22 145 +#define Mips_DSPOutFlag23 146 +#define Mips_F0 147 +#define Mips_F1 148 +#define Mips_F2 149 +#define Mips_F3 150 +#define Mips_F4 151 +#define Mips_F5 152 +#define Mips_F6 153 +#define Mips_F7 154 +#define Mips_F8 155 +#define Mips_F9 156 +#define Mips_F10 157 +#define Mips_F11 158 +#define Mips_F12 159 +#define Mips_F13 160 +#define Mips_F14 161 +#define Mips_F15 162 +#define Mips_F16 163 +#define Mips_F17 164 +#define Mips_F18 165 +#define Mips_F19 166 +#define Mips_F20 167 +#define Mips_F21 168 +#define Mips_F22 169 +#define Mips_F23 170 +#define Mips_F24 171 +#define Mips_F25 172 +#define Mips_F26 173 +#define Mips_F27 174 +#define Mips_F28 175 +#define Mips_F29 176 +#define Mips_F30 177 +#define Mips_F31 178 +#define Mips_FCC0 179 +#define Mips_FCC1 180 +#define Mips_FCC2 181 +#define Mips_FCC3 182 +#define Mips_FCC4 183 +#define Mips_FCC5 184 +#define Mips_FCC6 185 +#define Mips_FCC7 186 +#define Mips_FCR0 187 +#define Mips_FCR1 188 +#define Mips_FCR2 189 +#define Mips_FCR3 190 +#define Mips_FCR4 191 +#define Mips_FCR5 192 +#define Mips_FCR6 193 +#define Mips_FCR7 194 +#define Mips_FCR8 195 +#define Mips_FCR9 196 +#define Mips_FCR10 197 +#define Mips_FCR11 198 +#define Mips_FCR12 199 +#define Mips_FCR13 200 +#define Mips_FCR14 201 +#define Mips_FCR15 202 +#define Mips_FCR16 203 +#define Mips_FCR17 204 +#define Mips_FCR18 205 +#define Mips_FCR19 206 +#define Mips_FCR20 207 +#define Mips_FCR21 208 +#define Mips_FCR22 209 +#define Mips_FCR23 210 +#define Mips_FCR24 211 +#define Mips_FCR25 212 +#define Mips_FCR26 213 +#define Mips_FCR27 214 +#define Mips_FCR28 215 +#define Mips_FCR29 216 +#define Mips_FCR30 217 +#define Mips_FCR31 218 +#define Mips_FP_64 219 +#define Mips_F_HI0 220 +#define Mips_F_HI1 221 +#define Mips_F_HI2 222 +#define Mips_F_HI3 223 +#define Mips_F_HI4 224 +#define Mips_F_HI5 225 +#define Mips_F_HI6 226 +#define Mips_F_HI7 227 +#define Mips_F_HI8 228 +#define Mips_F_HI9 229 +#define Mips_F_HI10 230 +#define Mips_F_HI11 231 +#define Mips_F_HI12 232 +#define Mips_F_HI13 233 +#define Mips_F_HI14 234 +#define Mips_F_HI15 235 +#define Mips_F_HI16 236 +#define Mips_F_HI17 237 +#define Mips_F_HI18 238 +#define Mips_F_HI19 239 +#define Mips_F_HI20 240 +#define Mips_F_HI21 241 +#define Mips_F_HI22 242 +#define Mips_F_HI23 243 +#define Mips_F_HI24 244 +#define Mips_F_HI25 245 +#define Mips_F_HI26 246 +#define Mips_F_HI27 247 +#define Mips_F_HI28 248 +#define Mips_F_HI29 249 +#define Mips_F_HI30 250 +#define Mips_F_HI31 251 +#define Mips_GP_64 252 +#define Mips_HI0 253 +#define Mips_HI1 254 +#define Mips_HI2 255 +#define Mips_HI3 256 +#define Mips_HWR0 257 +#define Mips_HWR1 258 +#define Mips_HWR2 259 +#define Mips_HWR3 260 +#define Mips_HWR4 261 +#define Mips_HWR5 262 +#define Mips_HWR6 263 +#define Mips_HWR7 264 +#define Mips_HWR8 265 +#define Mips_HWR9 266 +#define Mips_HWR10 267 +#define Mips_HWR11 268 +#define Mips_HWR12 269 +#define Mips_HWR13 270 +#define Mips_HWR14 271 +#define Mips_HWR15 272 +#define Mips_HWR16 273 +#define Mips_HWR17 274 +#define Mips_HWR18 275 +#define Mips_HWR19 276 +#define Mips_HWR20 277 +#define Mips_HWR21 278 +#define Mips_HWR22 279 +#define Mips_HWR23 280 +#define Mips_HWR24 281 +#define Mips_HWR25 282 +#define Mips_HWR26 283 +#define Mips_HWR27 284 +#define Mips_HWR28 285 +#define Mips_HWR29 286 +#define Mips_HWR30 287 +#define Mips_HWR31 288 +#define Mips_K0 289 +#define Mips_K1 290 +#define Mips_LO0 291 +#define Mips_LO1 292 +#define Mips_LO2 293 +#define Mips_LO3 294 +#define Mips_MPL0 295 +#define Mips_MPL1 296 +#define Mips_MPL2 297 +#define Mips_MSA8 298 +#define Mips_MSA9 299 +#define Mips_MSA10 300 +#define Mips_MSA11 301 +#define Mips_MSA12 302 +#define Mips_MSA13 303 +#define Mips_MSA14 304 +#define Mips_MSA15 305 +#define Mips_MSA16 306 +#define Mips_MSA17 307 +#define Mips_MSA18 308 +#define Mips_MSA19 309 +#define Mips_MSA20 310 +#define Mips_MSA21 311 +#define Mips_MSA22 312 +#define Mips_MSA23 313 +#define Mips_MSA24 314 +#define Mips_MSA25 315 +#define Mips_MSA26 316 +#define Mips_MSA27 317 +#define Mips_MSA28 318 +#define Mips_MSA29 319 +#define Mips_MSA30 320 +#define Mips_MSA31 321 +#define Mips_P0 322 +#define Mips_P1 323 +#define Mips_P2 324 +#define Mips_RA_64 325 +#define Mips_S0 326 +#define Mips_S1 327 +#define Mips_S2 328 +#define Mips_S3 329 +#define Mips_S4 330 +#define Mips_S5 331 +#define Mips_S6 332 +#define Mips_S7 333 +#define Mips_SP_64 334 +#define Mips_T0 335 +#define Mips_T1 336 +#define Mips_T2 337 +#define Mips_T3 338 +#define Mips_T4 339 +#define Mips_T5 340 +#define Mips_T6 341 +#define Mips_T7 342 +#define Mips_T8 343 +#define Mips_T9 344 +#define Mips_V0 345 +#define Mips_V1 346 +#define Mips_W0 347 +#define Mips_W1 348 +#define Mips_W2 349 +#define Mips_W3 350 +#define Mips_W4 351 +#define Mips_W5 352 +#define Mips_W6 353 +#define Mips_W7 354 +#define Mips_W8 355 +#define Mips_W9 356 +#define Mips_W10 357 +#define Mips_W11 358 +#define Mips_W12 359 +#define Mips_W13 360 +#define Mips_W14 361 +#define Mips_W15 362 +#define Mips_W16 363 +#define Mips_W17 364 +#define Mips_W18 365 +#define Mips_W19 366 +#define Mips_W20 367 +#define Mips_W21 368 +#define Mips_W22 369 +#define Mips_W23 370 +#define Mips_W24 371 +#define Mips_W25 372 +#define Mips_W26 373 +#define Mips_W27 374 +#define Mips_W28 375 +#define Mips_W29 376 +#define Mips_W30 377 +#define Mips_W31 378 +#define Mips_ZERO_64 379 +#define Mips_A0_64 380 +#define Mips_A1_64 381 +#define Mips_A2_64 382 +#define Mips_A3_64 383 +#define Mips_AC0_64 384 +#define Mips_D0_64 385 +#define Mips_D1_64 386 +#define Mips_D2_64 387 +#define Mips_D3_64 388 +#define Mips_D4_64 389 +#define Mips_D5_64 390 +#define Mips_D6_64 391 +#define Mips_D7_64 392 +#define Mips_D8_64 393 +#define Mips_D9_64 394 +#define Mips_D10_64 395 +#define Mips_D11_64 396 +#define Mips_D12_64 397 +#define Mips_D13_64 398 +#define Mips_D14_64 399 +#define Mips_D15_64 400 +#define Mips_D16_64 401 +#define Mips_D17_64 402 +#define Mips_D18_64 403 +#define Mips_D19_64 404 +#define Mips_D20_64 405 +#define Mips_D21_64 406 +#define Mips_D22_64 407 +#define Mips_D23_64 408 +#define Mips_D24_64 409 +#define Mips_D25_64 410 +#define Mips_D26_64 411 +#define Mips_D27_64 412 +#define Mips_D28_64 413 +#define Mips_D29_64 414 +#define Mips_D30_64 415 +#define Mips_D31_64 416 +#define Mips_DSPOutFlag16_19 417 +#define Mips_HI0_64 418 +#define Mips_K0_64 419 +#define Mips_K1_64 420 +#define Mips_LO0_64 421 +#define Mips_S0_64 422 +#define Mips_S1_64 423 +#define Mips_S2_64 424 +#define Mips_S3_64 425 +#define Mips_S4_64 426 +#define Mips_S5_64 427 +#define Mips_S6_64 428 +#define Mips_S7_64 429 +#define Mips_T0_64 430 +#define Mips_T1_64 431 +#define Mips_T2_64 432 +#define Mips_T3_64 433 +#define Mips_T4_64 434 +#define Mips_T5_64 435 +#define Mips_T6_64 436 +#define Mips_T7_64 437 +#define Mips_T8_64 438 +#define Mips_T9_64 439 +#define Mips_V0_64 440 +#define Mips_V1_64 441 +#define Mips_NUM_TARGET_REGS 442 + +// Register classes + +#define Mips_MSA128F16RegClassID 0 +#define Mips_CCRRegClassID 1 +#define Mips_COP0RegClassID 2 +#define Mips_COP2RegClassID 3 +#define Mips_COP3RegClassID 4 +#define Mips_DSPRRegClassID 5 +#define Mips_FGR32RegClassID 6 +#define Mips_FGRCCRegClassID 7 +#define Mips_GPR32RegClassID 8 +#define Mips_HWRegsRegClassID 9 +#define Mips_MSACtrlRegClassID 10 +#define Mips_GPR32NONZERORegClassID 11 +#define Mips_CPU16RegsPlusSPRegClassID 12 +#define Mips_CPU16RegsRegClassID 13 +#define Mips_FCCRegClassID 14 +#define Mips_GPRMM16RegClassID 15 +#define Mips_GPRMM16MovePRegClassID 16 +#define Mips_GPRMM16ZeroRegClassID 17 +#define Mips_CPU16Regs_and_GPRMM16ZeroRegClassID 18 +#define Mips_GPR32NONZERO_and_GPRMM16MovePRegClassID 19 +#define Mips_GPRMM16MovePPairSecondRegClassID 20 +#define Mips_CPU16Regs_and_GPRMM16MovePRegClassID 21 +#define Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID 22 +#define Mips_HI32DSPRegClassID 23 +#define Mips_LO32DSPRegClassID 24 +#define Mips_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID 25 +#define Mips_GPRMM16MovePPairFirstRegClassID 26 +#define Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID 27 +#define Mips_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID 28 +#define Mips_CPURARegRegClassID 29 +#define Mips_CPUSPRegRegClassID 30 +#define Mips_DSPCCRegClassID 31 +#define Mips_GP32RegClassID 32 +#define Mips_GPR32ZERORegClassID 33 +#define Mips_HI32RegClassID 34 +#define Mips_LO32RegClassID 35 +#define Mips_SP32RegClassID 36 +#define Mips_FGR64RegClassID 37 +#define Mips_GPR64RegClassID 38 +#define Mips_GPR64_with_sub_32_in_GPR32NONZERORegClassID 39 +#define Mips_AFGR64RegClassID 40 +#define Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID 41 +#define Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID 42 +#define Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID 43 +#define Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID 44 +#define Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID 45 +#define Mips_GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID 46 +#define Mips_GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID 47 +#define Mips_ACC64DSPRegClassID 48 +#define Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID 49 +#define Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID 50 +#define Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID \ + 51 +#define Mips_GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID 52 +#define Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID \ + 53 +#define Mips_OCTEON_MPLRegClassID 54 +#define Mips_OCTEON_PRegClassID 55 +#define Mips_GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID \ + 56 +#define Mips_ACC64RegClassID 57 +#define Mips_GP64RegClassID 58 +#define Mips_GPR64_with_sub_32_in_CPURARegRegClassID 59 +#define Mips_GPR64_with_sub_32_in_GPR32ZERORegClassID 60 +#define Mips_HI64RegClassID 61 +#define Mips_LO64RegClassID 62 +#define Mips_SP64RegClassID 63 +#define Mips_MSA128BRegClassID 64 +#define Mips_MSA128DRegClassID 65 +#define Mips_MSA128HRegClassID 66 +#define Mips_MSA128WRegClassID 67 +#define Mips_MSA128WEvensRegClassID 68 +#define Mips_ACC128RegClassID 69 + +#endif // GET_REGINFO_ENUM + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +#define Mips_PHI 0 +#define Mips_INLINEASM 1 +#define Mips_INLINEASM_BR 2 +#define Mips_CFI_INSTRUCTION 3 +#define Mips_EH_LABEL 4 +#define Mips_GC_LABEL 5 +#define Mips_ANNOTATION_LABEL 6 +#define Mips_KILL 7 +#define Mips_EXTRACT_SUBREG 8 +#define Mips_INSERT_SUBREG 9 +#define Mips_IMPLICIT_DEF 10 +#define Mips_SUBREG_TO_REG 11 +#define Mips_COPY_TO_REGCLASS 12 +#define Mips_DBG_VALUE 13 +#define Mips_DBG_VALUE_LIST 14 +#define Mips_DBG_INSTR_REF 15 +#define Mips_DBG_PHI 16 +#define Mips_DBG_LABEL 17 +#define Mips_REG_SEQUENCE 18 +#define Mips_COPY 19 +#define Mips_BUNDLE 20 +#define Mips_LIFETIME_START 21 +#define Mips_LIFETIME_END 22 +#define Mips_PSEUDO_PROBE 23 +#define Mips_ARITH_FENCE 24 +#define Mips_STACKMAP 25 +#define Mips_FENTRY_CALL 26 +#define Mips_PATCHPOINT 27 +#define Mips_LOAD_STACK_GUARD 28 +#define Mips_PREALLOCATED_SETUP 29 +#define Mips_PREALLOCATED_ARG 30 +#define Mips_STATEPOINT 31 +#define Mips_LOCAL_ESCAPE 32 +#define Mips_FAULTING_OP 33 +#define Mips_PATCHABLE_OP 34 +#define Mips_PATCHABLE_FUNCTION_ENTER 35 +#define Mips_PATCHABLE_RET 36 +#define Mips_PATCHABLE_FUNCTION_EXIT 37 +#define Mips_PATCHABLE_TAIL_CALL 38 +#define Mips_PATCHABLE_EVENT_CALL 39 +#define Mips_PATCHABLE_TYPED_EVENT_CALL 40 +#define Mips_ICALL_BRANCH_FUNNEL 41 +#define Mips_G_ASSERT_SEXT 42 +#define Mips_G_ASSERT_ZEXT 43 +#define Mips_G_ADD 44 +#define Mips_G_SUB 45 +#define Mips_G_MUL 46 +#define Mips_G_SDIV 47 +#define Mips_G_UDIV 48 +#define Mips_G_SREM 49 +#define Mips_G_UREM 50 +#define Mips_G_SDIVREM 51 +#define Mips_G_UDIVREM 52 +#define Mips_G_AND 53 +#define Mips_G_OR 54 +#define Mips_G_XOR 55 +#define Mips_G_IMPLICIT_DEF 56 +#define Mips_G_PHI 57 +#define Mips_G_FRAME_INDEX 58 +#define Mips_G_GLOBAL_VALUE 59 +#define Mips_G_EXTRACT 60 +#define Mips_G_UNMERGE_VALUES 61 +#define Mips_G_INSERT 62 +#define Mips_G_MERGE_VALUES 63 +#define Mips_G_BUILD_VECTOR 64 +#define Mips_G_BUILD_VECTOR_TRUNC 65 +#define Mips_G_CONCAT_VECTORS 66 +#define Mips_G_PTRTOINT 67 +#define Mips_G_INTTOPTR 68 +#define Mips_G_BITCAST 69 +#define Mips_G_FREEZE 70 +#define Mips_G_INTRINSIC_TRUNC 71 +#define Mips_G_INTRINSIC_ROUND 72 +#define Mips_G_INTRINSIC_LRINT 73 +#define Mips_G_INTRINSIC_ROUNDEVEN 74 +#define Mips_G_READCYCLECOUNTER 75 +#define Mips_G_LOAD 76 +#define Mips_G_SEXTLOAD 77 +#define Mips_G_ZEXTLOAD 78 +#define Mips_G_INDEXED_LOAD 79 +#define Mips_G_INDEXED_SEXTLOAD 80 +#define Mips_G_INDEXED_ZEXTLOAD 81 +#define Mips_G_STORE 82 +#define Mips_G_INDEXED_STORE 83 +#define Mips_G_ATOMIC_CMPXCHG_WITH_SUCCESS 84 +#define Mips_G_ATOMIC_CMPXCHG 85 +#define Mips_G_ATOMICRMW_XCHG 86 +#define Mips_G_ATOMICRMW_ADD 87 +#define Mips_G_ATOMICRMW_SUB 88 +#define Mips_G_ATOMICRMW_AND 89 +#define Mips_G_ATOMICRMW_NAND 90 +#define Mips_G_ATOMICRMW_OR 91 +#define Mips_G_ATOMICRMW_XOR 92 +#define Mips_G_ATOMICRMW_MAX 93 +#define Mips_G_ATOMICRMW_MIN 94 +#define Mips_G_ATOMICRMW_UMAX 95 +#define Mips_G_ATOMICRMW_UMIN 96 +#define Mips_G_ATOMICRMW_FADD 97 +#define Mips_G_ATOMICRMW_FSUB 98 +#define Mips_G_FENCE 99 +#define Mips_G_BRCOND 100 +#define Mips_G_BRINDIRECT 101 +#define Mips_G_INTRINSIC 102 +#define Mips_G_INTRINSIC_W_SIDE_EFFECTS 103 +#define Mips_G_ANYEXT 104 +#define Mips_G_TRUNC 105 +#define Mips_G_CONSTANT 106 +#define Mips_G_FCONSTANT 107 +#define Mips_G_VASTART 108 +#define Mips_G_VAARG 109 +#define Mips_G_SEXT 110 +#define Mips_G_SEXT_INREG 111 +#define Mips_G_ZEXT 112 +#define Mips_G_SHL 113 +#define Mips_G_LSHR 114 +#define Mips_G_ASHR 115 +#define Mips_G_FSHL 116 +#define Mips_G_FSHR 117 +#define Mips_G_ROTR 118 +#define Mips_G_ROTL 119 +#define Mips_G_ICMP 120 +#define Mips_G_FCMP 121 +#define Mips_G_SELECT 122 +#define Mips_G_UADDO 123 +#define Mips_G_UADDE 124 +#define Mips_G_USUBO 125 +#define Mips_G_USUBE 126 +#define Mips_G_SADDO 127 +#define Mips_G_SADDE 128 +#define Mips_G_SSUBO 129 +#define Mips_G_SSUBE 130 +#define Mips_G_UMULO 131 +#define Mips_G_SMULO 132 +#define Mips_G_UMULH 133 +#define Mips_G_SMULH 134 +#define Mips_G_UADDSAT 135 +#define Mips_G_SADDSAT 136 +#define Mips_G_USUBSAT 137 +#define Mips_G_SSUBSAT 138 +#define Mips_G_USHLSAT 139 +#define Mips_G_SSHLSAT 140 +#define Mips_G_SMULFIX 141 +#define Mips_G_UMULFIX 142 +#define Mips_G_SMULFIXSAT 143 +#define Mips_G_UMULFIXSAT 144 +#define Mips_G_SDIVFIX 145 +#define Mips_G_UDIVFIX 146 +#define Mips_G_SDIVFIXSAT 147 +#define Mips_G_UDIVFIXSAT 148 +#define Mips_G_FADD 149 +#define Mips_G_FSUB 150 +#define Mips_G_FMUL 151 +#define Mips_G_FMA 152 +#define Mips_G_FMAD 153 +#define Mips_G_FDIV 154 +#define Mips_G_FREM 155 +#define Mips_G_FPOW 156 +#define Mips_G_FPOWI 157 +#define Mips_G_FEXP 158 +#define Mips_G_FEXP2 159 +#define Mips_G_FLOG 160 +#define Mips_G_FLOG2 161 +#define Mips_G_FLOG10 162 +#define Mips_G_FNEG 163 +#define Mips_G_FPEXT 164 +#define Mips_G_FPTRUNC 165 +#define Mips_G_FPTOSI 166 +#define Mips_G_FPTOUI 167 +#define Mips_G_SITOFP 168 +#define Mips_G_UITOFP 169 +#define Mips_G_FABS 170 +#define Mips_G_FCOPYSIGN 171 +#define Mips_G_FCANONICALIZE 172 +#define Mips_G_FMINNUM 173 +#define Mips_G_FMAXNUM 174 +#define Mips_G_FMINNUM_IEEE 175 +#define Mips_G_FMAXNUM_IEEE 176 +#define Mips_G_FMINIMUM 177 +#define Mips_G_FMAXIMUM 178 +#define Mips_G_PTR_ADD 179 +#define Mips_G_PTRMASK 180 +#define Mips_G_SMIN 181 +#define Mips_G_SMAX 182 +#define Mips_G_UMIN 183 +#define Mips_G_UMAX 184 +#define Mips_G_ABS 185 +#define Mips_G_LROUND 186 +#define Mips_G_LLROUND 187 +#define Mips_G_BR 188 +#define Mips_G_BRJT 189 +#define Mips_G_INSERT_VECTOR_ELT 190 +#define Mips_G_EXTRACT_VECTOR_ELT 191 +#define Mips_G_SHUFFLE_VECTOR 192 +#define Mips_G_CTTZ 193 +#define Mips_G_CTTZ_ZERO_UNDEF 194 +#define Mips_G_CTLZ 195 +#define Mips_G_CTLZ_ZERO_UNDEF 196 +#define Mips_G_CTPOP 197 +#define Mips_G_BSWAP 198 +#define Mips_G_BITREVERSE 199 +#define Mips_G_FCEIL 200 +#define Mips_G_FCOS 201 +#define Mips_G_FSIN 202 +#define Mips_G_FSQRT 203 +#define Mips_G_FFLOOR 204 +#define Mips_G_FRINT 205 +#define Mips_G_FNEARBYINT 206 +#define Mips_G_ADDRSPACE_CAST 207 +#define Mips_G_BLOCK_ADDR 208 +#define Mips_G_JUMP_TABLE 209 +#define Mips_G_DYN_STACKALLOC 210 +#define Mips_G_STRICT_FADD 211 +#define Mips_G_STRICT_FSUB 212 +#define Mips_G_STRICT_FMUL 213 +#define Mips_G_STRICT_FDIV 214 +#define Mips_G_STRICT_FREM 215 +#define Mips_G_STRICT_FMA 216 +#define Mips_G_STRICT_FSQRT 217 +#define Mips_G_READ_REGISTER 218 +#define Mips_G_WRITE_REGISTER 219 +#define Mips_G_MEMCPY 220 +#define Mips_G_MEMCPY_INLINE 221 +#define Mips_G_MEMMOVE 222 +#define Mips_G_MEMSET 223 +#define Mips_G_BZERO 224 +#define Mips_G_VECREDUCE_SEQ_FADD 225 +#define Mips_G_VECREDUCE_SEQ_FMUL 226 +#define Mips_G_VECREDUCE_FADD 227 +#define Mips_G_VECREDUCE_FMUL 228 +#define Mips_G_VECREDUCE_FMAX 229 +#define Mips_G_VECREDUCE_FMIN 230 +#define Mips_G_VECREDUCE_ADD 231 +#define Mips_G_VECREDUCE_MUL 232 +#define Mips_G_VECREDUCE_AND 233 +#define Mips_G_VECREDUCE_OR 234 +#define Mips_G_VECREDUCE_XOR 235 +#define Mips_G_VECREDUCE_SMAX 236 +#define Mips_G_VECREDUCE_SMIN 237 +#define Mips_G_VECREDUCE_UMAX 238 +#define Mips_G_VECREDUCE_UMIN 239 +#define Mips_G_SBFX 240 +#define Mips_G_UBFX 241 +#define Mips_ABSMacro 242 +#define Mips_ADJCALLSTACKDOWN 243 +#define Mips_ADJCALLSTACKUP 244 +#define Mips_AND_V_D_PSEUDO 245 +#define Mips_AND_V_H_PSEUDO 246 +#define Mips_AND_V_W_PSEUDO 247 +#define Mips_ATOMIC_CMP_SWAP_I16 248 +#define Mips_ATOMIC_CMP_SWAP_I16_POSTRA 249 +#define Mips_ATOMIC_CMP_SWAP_I32 250 +#define Mips_ATOMIC_CMP_SWAP_I32_POSTRA 251 +#define Mips_ATOMIC_CMP_SWAP_I64 252 +#define Mips_ATOMIC_CMP_SWAP_I64_POSTRA 253 +#define Mips_ATOMIC_CMP_SWAP_I8 254 +#define Mips_ATOMIC_CMP_SWAP_I8_POSTRA 255 +#define Mips_ATOMIC_LOAD_ADD_I16 256 +#define Mips_ATOMIC_LOAD_ADD_I16_POSTRA 257 +#define Mips_ATOMIC_LOAD_ADD_I32 258 +#define Mips_ATOMIC_LOAD_ADD_I32_POSTRA 259 +#define Mips_ATOMIC_LOAD_ADD_I64 260 +#define Mips_ATOMIC_LOAD_ADD_I64_POSTRA 261 +#define Mips_ATOMIC_LOAD_ADD_I8 262 +#define Mips_ATOMIC_LOAD_ADD_I8_POSTRA 263 +#define Mips_ATOMIC_LOAD_AND_I16 264 +#define Mips_ATOMIC_LOAD_AND_I16_POSTRA 265 +#define Mips_ATOMIC_LOAD_AND_I32 266 +#define Mips_ATOMIC_LOAD_AND_I32_POSTRA 267 +#define Mips_ATOMIC_LOAD_AND_I64 268 +#define Mips_ATOMIC_LOAD_AND_I64_POSTRA 269 +#define Mips_ATOMIC_LOAD_AND_I8 270 +#define Mips_ATOMIC_LOAD_AND_I8_POSTRA 271 +#define Mips_ATOMIC_LOAD_MAX_I16 272 +#define Mips_ATOMIC_LOAD_MAX_I16_POSTRA 273 +#define Mips_ATOMIC_LOAD_MAX_I32 274 +#define Mips_ATOMIC_LOAD_MAX_I32_POSTRA 275 +#define Mips_ATOMIC_LOAD_MAX_I64 276 +#define Mips_ATOMIC_LOAD_MAX_I64_POSTRA 277 +#define Mips_ATOMIC_LOAD_MAX_I8 278 +#define Mips_ATOMIC_LOAD_MAX_I8_POSTRA 279 +#define Mips_ATOMIC_LOAD_MIN_I16 280 +#define Mips_ATOMIC_LOAD_MIN_I16_POSTRA 281 +#define Mips_ATOMIC_LOAD_MIN_I32 282 +#define Mips_ATOMIC_LOAD_MIN_I32_POSTRA 283 +#define Mips_ATOMIC_LOAD_MIN_I64 284 +#define Mips_ATOMIC_LOAD_MIN_I64_POSTRA 285 +#define Mips_ATOMIC_LOAD_MIN_I8 286 +#define Mips_ATOMIC_LOAD_MIN_I8_POSTRA 287 +#define Mips_ATOMIC_LOAD_NAND_I16 288 +#define Mips_ATOMIC_LOAD_NAND_I16_POSTRA 289 +#define Mips_ATOMIC_LOAD_NAND_I32 290 +#define Mips_ATOMIC_LOAD_NAND_I32_POSTRA 291 +#define Mips_ATOMIC_LOAD_NAND_I64 292 +#define Mips_ATOMIC_LOAD_NAND_I64_POSTRA 293 +#define Mips_ATOMIC_LOAD_NAND_I8 294 +#define Mips_ATOMIC_LOAD_NAND_I8_POSTRA 295 +#define Mips_ATOMIC_LOAD_OR_I16 296 +#define Mips_ATOMIC_LOAD_OR_I16_POSTRA 297 +#define Mips_ATOMIC_LOAD_OR_I32 298 +#define Mips_ATOMIC_LOAD_OR_I32_POSTRA 299 +#define Mips_ATOMIC_LOAD_OR_I64 300 +#define Mips_ATOMIC_LOAD_OR_I64_POSTRA 301 +#define Mips_ATOMIC_LOAD_OR_I8 302 +#define Mips_ATOMIC_LOAD_OR_I8_POSTRA 303 +#define Mips_ATOMIC_LOAD_SUB_I16 304 +#define Mips_ATOMIC_LOAD_SUB_I16_POSTRA 305 +#define Mips_ATOMIC_LOAD_SUB_I32 306 +#define Mips_ATOMIC_LOAD_SUB_I32_POSTRA 307 +#define Mips_ATOMIC_LOAD_SUB_I64 308 +#define Mips_ATOMIC_LOAD_SUB_I64_POSTRA 309 +#define Mips_ATOMIC_LOAD_SUB_I8 310 +#define Mips_ATOMIC_LOAD_SUB_I8_POSTRA 311 +#define Mips_ATOMIC_LOAD_UMAX_I16 312 +#define Mips_ATOMIC_LOAD_UMAX_I16_POSTRA 313 +#define Mips_ATOMIC_LOAD_UMAX_I32 314 +#define Mips_ATOMIC_LOAD_UMAX_I32_POSTRA 315 +#define Mips_ATOMIC_LOAD_UMAX_I64 316 +#define Mips_ATOMIC_LOAD_UMAX_I64_POSTRA 317 +#define Mips_ATOMIC_LOAD_UMAX_I8 318 +#define Mips_ATOMIC_LOAD_UMAX_I8_POSTRA 319 +#define Mips_ATOMIC_LOAD_UMIN_I16 320 +#define Mips_ATOMIC_LOAD_UMIN_I16_POSTRA 321 +#define Mips_ATOMIC_LOAD_UMIN_I32 322 +#define Mips_ATOMIC_LOAD_UMIN_I32_POSTRA 323 +#define Mips_ATOMIC_LOAD_UMIN_I64 324 +#define Mips_ATOMIC_LOAD_UMIN_I64_POSTRA 325 +#define Mips_ATOMIC_LOAD_UMIN_I8 326 +#define Mips_ATOMIC_LOAD_UMIN_I8_POSTRA 327 +#define Mips_ATOMIC_LOAD_XOR_I16 328 +#define Mips_ATOMIC_LOAD_XOR_I16_POSTRA 329 +#define Mips_ATOMIC_LOAD_XOR_I32 330 +#define Mips_ATOMIC_LOAD_XOR_I32_POSTRA 331 +#define Mips_ATOMIC_LOAD_XOR_I64 332 +#define Mips_ATOMIC_LOAD_XOR_I64_POSTRA 333 +#define Mips_ATOMIC_LOAD_XOR_I8 334 +#define Mips_ATOMIC_LOAD_XOR_I8_POSTRA 335 +#define Mips_ATOMIC_SWAP_I16 336 +#define Mips_ATOMIC_SWAP_I16_POSTRA 337 +#define Mips_ATOMIC_SWAP_I32 338 +#define Mips_ATOMIC_SWAP_I32_POSTRA 339 +#define Mips_ATOMIC_SWAP_I64 340 +#define Mips_ATOMIC_SWAP_I64_POSTRA 341 +#define Mips_ATOMIC_SWAP_I8 342 +#define Mips_ATOMIC_SWAP_I8_POSTRA 343 +#define Mips_B 344 +#define Mips_BAL_BR 345 +#define Mips_BAL_BR_MM 346 +#define Mips_BEQLImmMacro 347 +#define Mips_BGE 348 +#define Mips_BGEImmMacro 349 +#define Mips_BGEL 350 +#define Mips_BGELImmMacro 351 +#define Mips_BGEU 352 +#define Mips_BGEUImmMacro 353 +#define Mips_BGEUL 354 +#define Mips_BGEULImmMacro 355 +#define Mips_BGT 356 +#define Mips_BGTImmMacro 357 +#define Mips_BGTL 358 +#define Mips_BGTLImmMacro 359 +#define Mips_BGTU 360 +#define Mips_BGTUImmMacro 361 +#define Mips_BGTUL 362 +#define Mips_BGTULImmMacro 363 +#define Mips_BLE 364 +#define Mips_BLEImmMacro 365 +#define Mips_BLEL 366 +#define Mips_BLELImmMacro 367 +#define Mips_BLEU 368 +#define Mips_BLEUImmMacro 369 +#define Mips_BLEUL 370 +#define Mips_BLEULImmMacro 371 +#define Mips_BLT 372 +#define Mips_BLTImmMacro 373 +#define Mips_BLTL 374 +#define Mips_BLTLImmMacro 375 +#define Mips_BLTU 376 +#define Mips_BLTUImmMacro 377 +#define Mips_BLTUL 378 +#define Mips_BLTULImmMacro 379 +#define Mips_BNELImmMacro 380 +#define Mips_BPOSGE32_PSEUDO 381 +#define Mips_BSEL_D_PSEUDO 382 +#define Mips_BSEL_FD_PSEUDO 383 +#define Mips_BSEL_FW_PSEUDO 384 +#define Mips_BSEL_H_PSEUDO 385 +#define Mips_BSEL_W_PSEUDO 386 +#define Mips_B_MM 387 +#define Mips_B_MMR6_Pseudo 388 +#define Mips_B_MM_Pseudo 389 +#define Mips_BeqImm 390 +#define Mips_BneImm 391 +#define Mips_BteqzT8CmpX16 392 +#define Mips_BteqzT8CmpiX16 393 +#define Mips_BteqzT8SltX16 394 +#define Mips_BteqzT8SltiX16 395 +#define Mips_BteqzT8SltiuX16 396 +#define Mips_BteqzT8SltuX16 397 +#define Mips_BtnezT8CmpX16 398 +#define Mips_BtnezT8CmpiX16 399 +#define Mips_BtnezT8SltX16 400 +#define Mips_BtnezT8SltiX16 401 +#define Mips_BtnezT8SltiuX16 402 +#define Mips_BtnezT8SltuX16 403 +#define Mips_BuildPairF64 404 +#define Mips_BuildPairF64_64 405 +#define Mips_CFTC1 406 +#define Mips_CONSTPOOL_ENTRY 407 +#define Mips_COPY_FD_PSEUDO 408 +#define Mips_COPY_FW_PSEUDO 409 +#define Mips_CTTC1 410 +#define Mips_Constant32 411 +#define Mips_DMULImmMacro 412 +#define Mips_DMULMacro 413 +#define Mips_DMULOMacro 414 +#define Mips_DMULOUMacro 415 +#define Mips_DROL 416 +#define Mips_DROLImm 417 +#define Mips_DROR 418 +#define Mips_DRORImm 419 +#define Mips_DSDivIMacro 420 +#define Mips_DSDivMacro 421 +#define Mips_DSRemIMacro 422 +#define Mips_DSRemMacro 423 +#define Mips_DUDivIMacro 424 +#define Mips_DUDivMacro 425 +#define Mips_DURemIMacro 426 +#define Mips_DURemMacro 427 +#define Mips_ERet 428 +#define Mips_ExtractElementF64 429 +#define Mips_ExtractElementF64_64 430 +#define Mips_FABS_D 431 +#define Mips_FABS_W 432 +#define Mips_FEXP2_D_1_PSEUDO 433 +#define Mips_FEXP2_W_1_PSEUDO 434 +#define Mips_FILL_FD_PSEUDO 435 +#define Mips_FILL_FW_PSEUDO 436 +#define Mips_GotPrologue16 437 +#define Mips_INSERT_B_VIDX64_PSEUDO 438 +#define Mips_INSERT_B_VIDX_PSEUDO 439 +#define Mips_INSERT_D_VIDX64_PSEUDO 440 +#define Mips_INSERT_D_VIDX_PSEUDO 441 +#define Mips_INSERT_FD_PSEUDO 442 +#define Mips_INSERT_FD_VIDX64_PSEUDO 443 +#define Mips_INSERT_FD_VIDX_PSEUDO 444 +#define Mips_INSERT_FW_PSEUDO 445 +#define Mips_INSERT_FW_VIDX64_PSEUDO 446 +#define Mips_INSERT_FW_VIDX_PSEUDO 447 +#define Mips_INSERT_H_VIDX64_PSEUDO 448 +#define Mips_INSERT_H_VIDX_PSEUDO 449 +#define Mips_INSERT_W_VIDX64_PSEUDO 450 +#define Mips_INSERT_W_VIDX_PSEUDO 451 +#define Mips_JALR64Pseudo 452 +#define Mips_JALRHB64Pseudo 453 +#define Mips_JALRHBPseudo 454 +#define Mips_JALRPseudo 455 +#define Mips_JAL_MMR6 456 +#define Mips_JalOneReg 457 +#define Mips_JalTwoReg 458 +#define Mips_LDMacro 459 +#define Mips_LDR_D 460 +#define Mips_LDR_W 461 +#define Mips_LD_F16 462 +#define Mips_LOAD_ACC128 463 +#define Mips_LOAD_ACC64 464 +#define Mips_LOAD_ACC64DSP 465 +#define Mips_LOAD_CCOND_DSP 466 +#define Mips_LONG_BRANCH_ADDiu 467 +#define Mips_LONG_BRANCH_ADDiu2Op 468 +#define Mips_LONG_BRANCH_DADDiu 469 +#define Mips_LONG_BRANCH_DADDiu2Op 470 +#define Mips_LONG_BRANCH_LUi 471 +#define Mips_LONG_BRANCH_LUi2Op 472 +#define Mips_LONG_BRANCH_LUi2Op_64 473 +#define Mips_LWM_MM 474 +#define Mips_LoadAddrImm32 475 +#define Mips_LoadAddrImm64 476 +#define Mips_LoadAddrReg32 477 +#define Mips_LoadAddrReg64 478 +#define Mips_LoadImm32 479 +#define Mips_LoadImm64 480 +#define Mips_LoadImmDoubleFGR 481 +#define Mips_LoadImmDoubleFGR_32 482 +#define Mips_LoadImmDoubleGPR 483 +#define Mips_LoadImmSingleFGR 484 +#define Mips_LoadImmSingleGPR 485 +#define Mips_LwConstant32 486 +#define Mips_MFTACX 487 +#define Mips_MFTC0 488 +#define Mips_MFTC1 489 +#define Mips_MFTDSP 490 +#define Mips_MFTGPR 491 +#define Mips_MFTHC1 492 +#define Mips_MFTHI 493 +#define Mips_MFTLO 494 +#define Mips_MIPSeh_return32 495 +#define Mips_MIPSeh_return64 496 +#define Mips_MSA_FP_EXTEND_D_PSEUDO 497 +#define Mips_MSA_FP_EXTEND_W_PSEUDO 498 +#define Mips_MSA_FP_ROUND_D_PSEUDO 499 +#define Mips_MSA_FP_ROUND_W_PSEUDO 500 +#define Mips_MTTACX 501 +#define Mips_MTTC0 502 +#define Mips_MTTC1 503 +#define Mips_MTTDSP 504 +#define Mips_MTTGPR 505 +#define Mips_MTTHC1 506 +#define Mips_MTTHI 507 +#define Mips_MTTLO 508 +#define Mips_MULImmMacro 509 +#define Mips_MULOMacro 510 +#define Mips_MULOUMacro 511 +#define Mips_MultRxRy16 512 +#define Mips_MultRxRyRz16 513 +#define Mips_MultuRxRy16 514 +#define Mips_MultuRxRyRz16 515 +#define Mips_NOP 516 +#define Mips_NORImm 517 +#define Mips_NORImm64 518 +#define Mips_NOR_V_D_PSEUDO 519 +#define Mips_NOR_V_H_PSEUDO 520 +#define Mips_NOR_V_W_PSEUDO 521 +#define Mips_OR_V_D_PSEUDO 522 +#define Mips_OR_V_H_PSEUDO 523 +#define Mips_OR_V_W_PSEUDO 524 +#define Mips_PseudoCMPU_EQ_QB 525 +#define Mips_PseudoCMPU_LE_QB 526 +#define Mips_PseudoCMPU_LT_QB 527 +#define Mips_PseudoCMP_EQ_PH 528 +#define Mips_PseudoCMP_LE_PH 529 +#define Mips_PseudoCMP_LT_PH 530 +#define Mips_PseudoCVT_D32_W 531 +#define Mips_PseudoCVT_D64_L 532 +#define Mips_PseudoCVT_D64_W 533 +#define Mips_PseudoCVT_S_L 534 +#define Mips_PseudoCVT_S_W 535 +#define Mips_PseudoDMULT 536 +#define Mips_PseudoDMULTu 537 +#define Mips_PseudoDSDIV 538 +#define Mips_PseudoDUDIV 539 +#define Mips_PseudoD_SELECT_I 540 +#define Mips_PseudoD_SELECT_I64 541 +#define Mips_PseudoIndirectBranch 542 +#define Mips_PseudoIndirectBranch64 543 +#define Mips_PseudoIndirectBranch64R6 544 +#define Mips_PseudoIndirectBranchR6 545 +#define Mips_PseudoIndirectBranch_MM 546 +#define Mips_PseudoIndirectBranch_MMR6 547 +#define Mips_PseudoIndirectHazardBranch 548 +#define Mips_PseudoIndirectHazardBranch64 549 +#define Mips_PseudoIndrectHazardBranch64R6 550 +#define Mips_PseudoIndrectHazardBranchR6 551 +#define Mips_PseudoMADD 552 +#define Mips_PseudoMADDU 553 +#define Mips_PseudoMADDU_MM 554 +#define Mips_PseudoMADD_MM 555 +#define Mips_PseudoMFHI 556 +#define Mips_PseudoMFHI64 557 +#define Mips_PseudoMFHI_MM 558 +#define Mips_PseudoMFLO 559 +#define Mips_PseudoMFLO64 560 +#define Mips_PseudoMFLO_MM 561 +#define Mips_PseudoMSUB 562 +#define Mips_PseudoMSUBU 563 +#define Mips_PseudoMSUBU_MM 564 +#define Mips_PseudoMSUB_MM 565 +#define Mips_PseudoMTLOHI 566 +#define Mips_PseudoMTLOHI64 567 +#define Mips_PseudoMTLOHI_DSP 568 +#define Mips_PseudoMTLOHI_MM 569 +#define Mips_PseudoMULT 570 +#define Mips_PseudoMULT_MM 571 +#define Mips_PseudoMULTu 572 +#define Mips_PseudoMULTu_MM 573 +#define Mips_PseudoPICK_PH 574 +#define Mips_PseudoPICK_QB 575 +#define Mips_PseudoReturn 576 +#define Mips_PseudoReturn64 577 +#define Mips_PseudoSDIV 578 +#define Mips_PseudoSELECTFP_F_D32 579 +#define Mips_PseudoSELECTFP_F_D64 580 +#define Mips_PseudoSELECTFP_F_I 581 +#define Mips_PseudoSELECTFP_F_I64 582 +#define Mips_PseudoSELECTFP_F_S 583 +#define Mips_PseudoSELECTFP_T_D32 584 +#define Mips_PseudoSELECTFP_T_D64 585 +#define Mips_PseudoSELECTFP_T_I 586 +#define Mips_PseudoSELECTFP_T_I64 587 +#define Mips_PseudoSELECTFP_T_S 588 +#define Mips_PseudoSELECT_D32 589 +#define Mips_PseudoSELECT_D64 590 +#define Mips_PseudoSELECT_I 591 +#define Mips_PseudoSELECT_I64 592 +#define Mips_PseudoSELECT_S 593 +#define Mips_PseudoTRUNC_W_D 594 +#define Mips_PseudoTRUNC_W_D32 595 +#define Mips_PseudoTRUNC_W_S 596 +#define Mips_PseudoUDIV 597 +#define Mips_ROL 598 +#define Mips_ROLImm 599 +#define Mips_ROR 600 +#define Mips_RORImm 601 +#define Mips_RetRA 602 +#define Mips_RetRA16 603 +#define Mips_SDC1_M1 604 +#define Mips_SDIV_MM_Pseudo 605 +#define Mips_SDMacro 606 +#define Mips_SDivIMacro 607 +#define Mips_SDivMacro 608 +#define Mips_SEQIMacro 609 +#define Mips_SEQMacro 610 +#define Mips_SGE 611 +#define Mips_SGEImm 612 +#define Mips_SGEImm64 613 +#define Mips_SGEU 614 +#define Mips_SGEUImm 615 +#define Mips_SGEUImm64 616 +#define Mips_SGTImm 617 +#define Mips_SGTImm64 618 +#define Mips_SGTUImm 619 +#define Mips_SGTUImm64 620 +#define Mips_SLE 621 +#define Mips_SLEImm 622 +#define Mips_SLEImm64 623 +#define Mips_SLEU 624 +#define Mips_SLEUImm 625 +#define Mips_SLEUImm64 626 +#define Mips_SLTImm64 627 +#define Mips_SLTUImm64 628 +#define Mips_SNEIMacro 629 +#define Mips_SNEMacro 630 +#define Mips_SNZ_B_PSEUDO 631 +#define Mips_SNZ_D_PSEUDO 632 +#define Mips_SNZ_H_PSEUDO 633 +#define Mips_SNZ_V_PSEUDO 634 +#define Mips_SNZ_W_PSEUDO 635 +#define Mips_SRemIMacro 636 +#define Mips_SRemMacro 637 +#define Mips_STORE_ACC128 638 +#define Mips_STORE_ACC64 639 +#define Mips_STORE_ACC64DSP 640 +#define Mips_STORE_CCOND_DSP 641 +#define Mips_STR_D 642 +#define Mips_STR_W 643 +#define Mips_ST_F16 644 +#define Mips_SWM_MM 645 +#define Mips_SZ_B_PSEUDO 646 +#define Mips_SZ_D_PSEUDO 647 +#define Mips_SZ_H_PSEUDO 648 +#define Mips_SZ_V_PSEUDO 649 +#define Mips_SZ_W_PSEUDO 650 +#define Mips_SaaAddr 651 +#define Mips_SaadAddr 652 +#define Mips_SelBeqZ 653 +#define Mips_SelBneZ 654 +#define Mips_SelTBteqZCmp 655 +#define Mips_SelTBteqZCmpi 656 +#define Mips_SelTBteqZSlt 657 +#define Mips_SelTBteqZSlti 658 +#define Mips_SelTBteqZSltiu 659 +#define Mips_SelTBteqZSltu 660 +#define Mips_SelTBtneZCmp 661 +#define Mips_SelTBtneZCmpi 662 +#define Mips_SelTBtneZSlt 663 +#define Mips_SelTBtneZSlti 664 +#define Mips_SelTBtneZSltiu 665 +#define Mips_SelTBtneZSltu 666 +#define Mips_SltCCRxRy16 667 +#define Mips_SltiCCRxImmX16 668 +#define Mips_SltiuCCRxImmX16 669 +#define Mips_SltuCCRxRy16 670 +#define Mips_SltuRxRyRz16 671 +#define Mips_TAILCALL 672 +#define Mips_TAILCALL64R6REG 673 +#define Mips_TAILCALLHB64R6REG 674 +#define Mips_TAILCALLHBR6REG 675 +#define Mips_TAILCALLR6REG 676 +#define Mips_TAILCALLREG 677 +#define Mips_TAILCALLREG64 678 +#define Mips_TAILCALLREGHB 679 +#define Mips_TAILCALLREGHB64 680 +#define Mips_TAILCALLREG_MM 681 +#define Mips_TAILCALLREG_MMR6 682 +#define Mips_TAILCALL_MM 683 +#define Mips_TAILCALL_MMR6 684 +#define Mips_TRAP 685 +#define Mips_TRAP_MM 686 +#define Mips_UDIV_MM_Pseudo 687 +#define Mips_UDivIMacro 688 +#define Mips_UDivMacro 689 +#define Mips_URemIMacro 690 +#define Mips_URemMacro 691 +#define Mips_Ulh 692 +#define Mips_Ulhu 693 +#define Mips_Ulw 694 +#define Mips_Ush 695 +#define Mips_Usw 696 +#define Mips_XOR_V_D_PSEUDO 697 +#define Mips_XOR_V_H_PSEUDO 698 +#define Mips_XOR_V_W_PSEUDO 699 +#define Mips_ABSQ_S_PH 700 +#define Mips_ABSQ_S_PH_MM 701 +#define Mips_ABSQ_S_QB 702 +#define Mips_ABSQ_S_QB_MMR2 703 +#define Mips_ABSQ_S_W 704 +#define Mips_ABSQ_S_W_MM 705 +#define Mips_ADD 706 +#define Mips_ADDIUPC 707 +#define Mips_ADDIUPC_MM 708 +#define Mips_ADDIUPC_MMR6 709 +#define Mips_ADDIUR1SP_MM 710 +#define Mips_ADDIUR2_MM 711 +#define Mips_ADDIUS5_MM 712 +#define Mips_ADDIUSP_MM 713 +#define Mips_ADDIU_MMR6 714 +#define Mips_ADDQH_PH 715 +#define Mips_ADDQH_PH_MMR2 716 +#define Mips_ADDQH_R_PH 717 +#define Mips_ADDQH_R_PH_MMR2 718 +#define Mips_ADDQH_R_W 719 +#define Mips_ADDQH_R_W_MMR2 720 +#define Mips_ADDQH_W 721 +#define Mips_ADDQH_W_MMR2 722 +#define Mips_ADDQ_PH 723 +#define Mips_ADDQ_PH_MM 724 +#define Mips_ADDQ_S_PH 725 +#define Mips_ADDQ_S_PH_MM 726 +#define Mips_ADDQ_S_W 727 +#define Mips_ADDQ_S_W_MM 728 +#define Mips_ADDR_PS64 729 +#define Mips_ADDSC 730 +#define Mips_ADDSC_MM 731 +#define Mips_ADDS_A_B 732 +#define Mips_ADDS_A_D 733 +#define Mips_ADDS_A_H 734 +#define Mips_ADDS_A_W 735 +#define Mips_ADDS_S_B 736 +#define Mips_ADDS_S_D 737 +#define Mips_ADDS_S_H 738 +#define Mips_ADDS_S_W 739 +#define Mips_ADDS_U_B 740 +#define Mips_ADDS_U_D 741 +#define Mips_ADDS_U_H 742 +#define Mips_ADDS_U_W 743 +#define Mips_ADDU16_MM 744 +#define Mips_ADDU16_MMR6 745 +#define Mips_ADDUH_QB 746 +#define Mips_ADDUH_QB_MMR2 747 +#define Mips_ADDUH_R_QB 748 +#define Mips_ADDUH_R_QB_MMR2 749 +#define Mips_ADDU_MMR6 750 +#define Mips_ADDU_PH 751 +#define Mips_ADDU_PH_MMR2 752 +#define Mips_ADDU_QB 753 +#define Mips_ADDU_QB_MM 754 +#define Mips_ADDU_S_PH 755 +#define Mips_ADDU_S_PH_MMR2 756 +#define Mips_ADDU_S_QB 757 +#define Mips_ADDU_S_QB_MM 758 +#define Mips_ADDVI_B 759 +#define Mips_ADDVI_D 760 +#define Mips_ADDVI_H 761 +#define Mips_ADDVI_W 762 +#define Mips_ADDV_B 763 +#define Mips_ADDV_D 764 +#define Mips_ADDV_H 765 +#define Mips_ADDV_W 766 +#define Mips_ADDWC 767 +#define Mips_ADDWC_MM 768 +#define Mips_ADD_A_B 769 +#define Mips_ADD_A_D 770 +#define Mips_ADD_A_H 771 +#define Mips_ADD_A_W 772 +#define Mips_ADD_MM 773 +#define Mips_ADD_MMR6 774 +#define Mips_ADDi 775 +#define Mips_ADDi_MM 776 +#define Mips_ADDiu 777 +#define Mips_ADDiu_MM 778 +#define Mips_ADDu 779 +#define Mips_ADDu_MM 780 +#define Mips_ALIGN 781 +#define Mips_ALIGN_MMR6 782 +#define Mips_ALUIPC 783 +#define Mips_ALUIPC_MMR6 784 +#define Mips_AND 785 +#define Mips_AND16_MM 786 +#define Mips_AND16_MMR6 787 +#define Mips_AND64 788 +#define Mips_ANDI16_MM 789 +#define Mips_ANDI16_MMR6 790 +#define Mips_ANDI_B 791 +#define Mips_ANDI_MMR6 792 +#define Mips_AND_MM 793 +#define Mips_AND_MMR6 794 +#define Mips_AND_V 795 +#define Mips_ANDi 796 +#define Mips_ANDi64 797 +#define Mips_ANDi_MM 798 +#define Mips_APPEND 799 +#define Mips_APPEND_MMR2 800 +#define Mips_ASUB_S_B 801 +#define Mips_ASUB_S_D 802 +#define Mips_ASUB_S_H 803 +#define Mips_ASUB_S_W 804 +#define Mips_ASUB_U_B 805 +#define Mips_ASUB_U_D 806 +#define Mips_ASUB_U_H 807 +#define Mips_ASUB_U_W 808 +#define Mips_AUI 809 +#define Mips_AUIPC 810 +#define Mips_AUIPC_MMR6 811 +#define Mips_AUI_MMR6 812 +#define Mips_AVER_S_B 813 +#define Mips_AVER_S_D 814 +#define Mips_AVER_S_H 815 +#define Mips_AVER_S_W 816 +#define Mips_AVER_U_B 817 +#define Mips_AVER_U_D 818 +#define Mips_AVER_U_H 819 +#define Mips_AVER_U_W 820 +#define Mips_AVE_S_B 821 +#define Mips_AVE_S_D 822 +#define Mips_AVE_S_H 823 +#define Mips_AVE_S_W 824 +#define Mips_AVE_U_B 825 +#define Mips_AVE_U_D 826 +#define Mips_AVE_U_H 827 +#define Mips_AVE_U_W 828 +#define Mips_AddiuRxImmX16 829 +#define Mips_AddiuRxPcImmX16 830 +#define Mips_AddiuRxRxImm16 831 +#define Mips_AddiuRxRxImmX16 832 +#define Mips_AddiuRxRyOffMemX16 833 +#define Mips_AddiuSpImm16 834 +#define Mips_AddiuSpImmX16 835 +#define Mips_AdduRxRyRz16 836 +#define Mips_AndRxRxRy16 837 +#define Mips_B16_MM 838 +#define Mips_BADDu 839 +#define Mips_BAL 840 +#define Mips_BALC 841 +#define Mips_BALC_MMR6 842 +#define Mips_BALIGN 843 +#define Mips_BALIGN_MMR2 844 +#define Mips_BBIT0 845 +#define Mips_BBIT032 846 +#define Mips_BBIT1 847 +#define Mips_BBIT132 848 +#define Mips_BC 849 +#define Mips_BC0F 850 +#define Mips_BC0T 851 +#define Mips_BC16_MMR6 852 +#define Mips_BC1EQZ 853 +#define Mips_BC1EQZC_MMR6 854 +#define Mips_BC1F 855 +#define Mips_BC1FL 856 +#define Mips_BC1F_MM 857 +#define Mips_BC1NEZ 858 +#define Mips_BC1NEZC_MMR6 859 +#define Mips_BC1T 860 +#define Mips_BC1TL 861 +#define Mips_BC1T_MM 862 +#define Mips_BC2EQZ 863 +#define Mips_BC2EQZC_MMR6 864 +#define Mips_BC2F 865 +#define Mips_BC2FL 866 +#define Mips_BC2NEZ 867 +#define Mips_BC2NEZC_MMR6 868 +#define Mips_BC2T 869 +#define Mips_BC2TL 870 +#define Mips_BC3F 871 +#define Mips_BC3FL 872 +#define Mips_BC3T 873 +#define Mips_BC3TL 874 +#define Mips_BCLRI_B 875 +#define Mips_BCLRI_D 876 +#define Mips_BCLRI_H 877 +#define Mips_BCLRI_W 878 +#define Mips_BCLR_B 879 +#define Mips_BCLR_D 880 +#define Mips_BCLR_H 881 +#define Mips_BCLR_W 882 +#define Mips_BC_MMR6 883 +#define Mips_BEQ 884 +#define Mips_BEQ64 885 +#define Mips_BEQC 886 +#define Mips_BEQC64 887 +#define Mips_BEQC_MMR6 888 +#define Mips_BEQL 889 +#define Mips_BEQZ16_MM 890 +#define Mips_BEQZALC 891 +#define Mips_BEQZALC_MMR6 892 +#define Mips_BEQZC 893 +#define Mips_BEQZC16_MMR6 894 +#define Mips_BEQZC64 895 +#define Mips_BEQZC_MM 896 +#define Mips_BEQZC_MMR6 897 +#define Mips_BEQ_MM 898 +#define Mips_BGEC 899 +#define Mips_BGEC64 900 +#define Mips_BGEC_MMR6 901 +#define Mips_BGEUC 902 +#define Mips_BGEUC64 903 +#define Mips_BGEUC_MMR6 904 +#define Mips_BGEZ 905 +#define Mips_BGEZ64 906 +#define Mips_BGEZAL 907 +#define Mips_BGEZALC 908 +#define Mips_BGEZALC_MMR6 909 +#define Mips_BGEZALL 910 +#define Mips_BGEZALS_MM 911 +#define Mips_BGEZAL_MM 912 +#define Mips_BGEZC 913 +#define Mips_BGEZC64 914 +#define Mips_BGEZC_MMR6 915 +#define Mips_BGEZL 916 +#define Mips_BGEZ_MM 917 +#define Mips_BGTZ 918 +#define Mips_BGTZ64 919 +#define Mips_BGTZALC 920 +#define Mips_BGTZALC_MMR6 921 +#define Mips_BGTZC 922 +#define Mips_BGTZC64 923 +#define Mips_BGTZC_MMR6 924 +#define Mips_BGTZL 925 +#define Mips_BGTZ_MM 926 +#define Mips_BINSLI_B 927 +#define Mips_BINSLI_D 928 +#define Mips_BINSLI_H 929 +#define Mips_BINSLI_W 930 +#define Mips_BINSL_B 931 +#define Mips_BINSL_D 932 +#define Mips_BINSL_H 933 +#define Mips_BINSL_W 934 +#define Mips_BINSRI_B 935 +#define Mips_BINSRI_D 936 +#define Mips_BINSRI_H 937 +#define Mips_BINSRI_W 938 +#define Mips_BINSR_B 939 +#define Mips_BINSR_D 940 +#define Mips_BINSR_H 941 +#define Mips_BINSR_W 942 +#define Mips_BITREV 943 +#define Mips_BITREV_MM 944 +#define Mips_BITSWAP 945 +#define Mips_BITSWAP_MMR6 946 +#define Mips_BLEZ 947 +#define Mips_BLEZ64 948 +#define Mips_BLEZALC 949 +#define Mips_BLEZALC_MMR6 950 +#define Mips_BLEZC 951 +#define Mips_BLEZC64 952 +#define Mips_BLEZC_MMR6 953 +#define Mips_BLEZL 954 +#define Mips_BLEZ_MM 955 +#define Mips_BLTC 956 +#define Mips_BLTC64 957 +#define Mips_BLTC_MMR6 958 +#define Mips_BLTUC 959 +#define Mips_BLTUC64 960 +#define Mips_BLTUC_MMR6 961 +#define Mips_BLTZ 962 +#define Mips_BLTZ64 963 +#define Mips_BLTZAL 964 +#define Mips_BLTZALC 965 +#define Mips_BLTZALC_MMR6 966 +#define Mips_BLTZALL 967 +#define Mips_BLTZALS_MM 968 +#define Mips_BLTZAL_MM 969 +#define Mips_BLTZC 970 +#define Mips_BLTZC64 971 +#define Mips_BLTZC_MMR6 972 +#define Mips_BLTZL 973 +#define Mips_BLTZ_MM 974 +#define Mips_BMNZI_B 975 +#define Mips_BMNZ_V 976 +#define Mips_BMZI_B 977 +#define Mips_BMZ_V 978 +#define Mips_BNE 979 +#define Mips_BNE64 980 +#define Mips_BNEC 981 +#define Mips_BNEC64 982 +#define Mips_BNEC_MMR6 983 +#define Mips_BNEGI_B 984 +#define Mips_BNEGI_D 985 +#define Mips_BNEGI_H 986 +#define Mips_BNEGI_W 987 +#define Mips_BNEG_B 988 +#define Mips_BNEG_D 989 +#define Mips_BNEG_H 990 +#define Mips_BNEG_W 991 +#define Mips_BNEL 992 +#define Mips_BNEZ16_MM 993 +#define Mips_BNEZALC 994 +#define Mips_BNEZALC_MMR6 995 +#define Mips_BNEZC 996 +#define Mips_BNEZC16_MMR6 997 +#define Mips_BNEZC64 998 +#define Mips_BNEZC_MM 999 +#define Mips_BNEZC_MMR6 1000 +#define Mips_BNE_MM 1001 +#define Mips_BNVC 1002 +#define Mips_BNVC_MMR6 1003 +#define Mips_BNZ_B 1004 +#define Mips_BNZ_D 1005 +#define Mips_BNZ_H 1006 +#define Mips_BNZ_V 1007 +#define Mips_BNZ_W 1008 +#define Mips_BOVC 1009 +#define Mips_BOVC_MMR6 1010 +#define Mips_BPOSGE32 1011 +#define Mips_BPOSGE32C_MMR3 1012 +#define Mips_BPOSGE32_MM 1013 +#define Mips_BREAK 1014 +#define Mips_BREAK16_MM 1015 +#define Mips_BREAK16_MMR6 1016 +#define Mips_BREAK_MM 1017 +#define Mips_BREAK_MMR6 1018 +#define Mips_BSELI_B 1019 +#define Mips_BSEL_V 1020 +#define Mips_BSETI_B 1021 +#define Mips_BSETI_D 1022 +#define Mips_BSETI_H 1023 +#define Mips_BSETI_W 1024 +#define Mips_BSET_B 1025 +#define Mips_BSET_D 1026 +#define Mips_BSET_H 1027 +#define Mips_BSET_W 1028 +#define Mips_BZ_B 1029 +#define Mips_BZ_D 1030 +#define Mips_BZ_H 1031 +#define Mips_BZ_V 1032 +#define Mips_BZ_W 1033 +#define Mips_BeqzRxImm16 1034 +#define Mips_BeqzRxImmX16 1035 +#define Mips_Bimm16 1036 +#define Mips_BimmX16 1037 +#define Mips_BnezRxImm16 1038 +#define Mips_BnezRxImmX16 1039 +#define Mips_Break16 1040 +#define Mips_Bteqz16 1041 +#define Mips_BteqzX16 1042 +#define Mips_Btnez16 1043 +#define Mips_BtnezX16 1044 +#define Mips_CACHE 1045 +#define Mips_CACHEE 1046 +#define Mips_CACHEE_MM 1047 +#define Mips_CACHE_MM 1048 +#define Mips_CACHE_MMR6 1049 +#define Mips_CACHE_R6 1050 +#define Mips_CEIL_L_D64 1051 +#define Mips_CEIL_L_D_MMR6 1052 +#define Mips_CEIL_L_S 1053 +#define Mips_CEIL_L_S_MMR6 1054 +#define Mips_CEIL_W_D32 1055 +#define Mips_CEIL_W_D64 1056 +#define Mips_CEIL_W_D_MMR6 1057 +#define Mips_CEIL_W_MM 1058 +#define Mips_CEIL_W_S 1059 +#define Mips_CEIL_W_S_MM 1060 +#define Mips_CEIL_W_S_MMR6 1061 +#define Mips_CEQI_B 1062 +#define Mips_CEQI_D 1063 +#define Mips_CEQI_H 1064 +#define Mips_CEQI_W 1065 +#define Mips_CEQ_B 1066 +#define Mips_CEQ_D 1067 +#define Mips_CEQ_H 1068 +#define Mips_CEQ_W 1069 +#define Mips_CFC1 1070 +#define Mips_CFC1_MM 1071 +#define Mips_CFC2_MM 1072 +#define Mips_CFCMSA 1073 +#define Mips_CINS 1074 +#define Mips_CINS32 1075 +#define Mips_CINS64_32 1076 +#define Mips_CINS_i32 1077 +#define Mips_CLASS_D 1078 +#define Mips_CLASS_D_MMR6 1079 +#define Mips_CLASS_S 1080 +#define Mips_CLASS_S_MMR6 1081 +#define Mips_CLEI_S_B 1082 +#define Mips_CLEI_S_D 1083 +#define Mips_CLEI_S_H 1084 +#define Mips_CLEI_S_W 1085 +#define Mips_CLEI_U_B 1086 +#define Mips_CLEI_U_D 1087 +#define Mips_CLEI_U_H 1088 +#define Mips_CLEI_U_W 1089 +#define Mips_CLE_S_B 1090 +#define Mips_CLE_S_D 1091 +#define Mips_CLE_S_H 1092 +#define Mips_CLE_S_W 1093 +#define Mips_CLE_U_B 1094 +#define Mips_CLE_U_D 1095 +#define Mips_CLE_U_H 1096 +#define Mips_CLE_U_W 1097 +#define Mips_CLO 1098 +#define Mips_CLO_MM 1099 +#define Mips_CLO_MMR6 1100 +#define Mips_CLO_R6 1101 +#define Mips_CLTI_S_B 1102 +#define Mips_CLTI_S_D 1103 +#define Mips_CLTI_S_H 1104 +#define Mips_CLTI_S_W 1105 +#define Mips_CLTI_U_B 1106 +#define Mips_CLTI_U_D 1107 +#define Mips_CLTI_U_H 1108 +#define Mips_CLTI_U_W 1109 +#define Mips_CLT_S_B 1110 +#define Mips_CLT_S_D 1111 +#define Mips_CLT_S_H 1112 +#define Mips_CLT_S_W 1113 +#define Mips_CLT_U_B 1114 +#define Mips_CLT_U_D 1115 +#define Mips_CLT_U_H 1116 +#define Mips_CLT_U_W 1117 +#define Mips_CLZ 1118 +#define Mips_CLZ_MM 1119 +#define Mips_CLZ_MMR6 1120 +#define Mips_CLZ_R6 1121 +#define Mips_CMPGDU_EQ_QB 1122 +#define Mips_CMPGDU_EQ_QB_MMR2 1123 +#define Mips_CMPGDU_LE_QB 1124 +#define Mips_CMPGDU_LE_QB_MMR2 1125 +#define Mips_CMPGDU_LT_QB 1126 +#define Mips_CMPGDU_LT_QB_MMR2 1127 +#define Mips_CMPGU_EQ_QB 1128 +#define Mips_CMPGU_EQ_QB_MM 1129 +#define Mips_CMPGU_LE_QB 1130 +#define Mips_CMPGU_LE_QB_MM 1131 +#define Mips_CMPGU_LT_QB 1132 +#define Mips_CMPGU_LT_QB_MM 1133 +#define Mips_CMPU_EQ_QB 1134 +#define Mips_CMPU_EQ_QB_MM 1135 +#define Mips_CMPU_LE_QB 1136 +#define Mips_CMPU_LE_QB_MM 1137 +#define Mips_CMPU_LT_QB 1138 +#define Mips_CMPU_LT_QB_MM 1139 +#define Mips_CMP_AF_D_MMR6 1140 +#define Mips_CMP_AF_S_MMR6 1141 +#define Mips_CMP_EQ_D 1142 +#define Mips_CMP_EQ_D_MMR6 1143 +#define Mips_CMP_EQ_PH 1144 +#define Mips_CMP_EQ_PH_MM 1145 +#define Mips_CMP_EQ_S 1146 +#define Mips_CMP_EQ_S_MMR6 1147 +#define Mips_CMP_F_D 1148 +#define Mips_CMP_F_S 1149 +#define Mips_CMP_LE_D 1150 +#define Mips_CMP_LE_D_MMR6 1151 +#define Mips_CMP_LE_PH 1152 +#define Mips_CMP_LE_PH_MM 1153 +#define Mips_CMP_LE_S 1154 +#define Mips_CMP_LE_S_MMR6 1155 +#define Mips_CMP_LT_D 1156 +#define Mips_CMP_LT_D_MMR6 1157 +#define Mips_CMP_LT_PH 1158 +#define Mips_CMP_LT_PH_MM 1159 +#define Mips_CMP_LT_S 1160 +#define Mips_CMP_LT_S_MMR6 1161 +#define Mips_CMP_SAF_D 1162 +#define Mips_CMP_SAF_D_MMR6 1163 +#define Mips_CMP_SAF_S 1164 +#define Mips_CMP_SAF_S_MMR6 1165 +#define Mips_CMP_SEQ_D 1166 +#define Mips_CMP_SEQ_D_MMR6 1167 +#define Mips_CMP_SEQ_S 1168 +#define Mips_CMP_SEQ_S_MMR6 1169 +#define Mips_CMP_SLE_D 1170 +#define Mips_CMP_SLE_D_MMR6 1171 +#define Mips_CMP_SLE_S 1172 +#define Mips_CMP_SLE_S_MMR6 1173 +#define Mips_CMP_SLT_D 1174 +#define Mips_CMP_SLT_D_MMR6 1175 +#define Mips_CMP_SLT_S 1176 +#define Mips_CMP_SLT_S_MMR6 1177 +#define Mips_CMP_SUEQ_D 1178 +#define Mips_CMP_SUEQ_D_MMR6 1179 +#define Mips_CMP_SUEQ_S 1180 +#define Mips_CMP_SUEQ_S_MMR6 1181 +#define Mips_CMP_SULE_D 1182 +#define Mips_CMP_SULE_D_MMR6 1183 +#define Mips_CMP_SULE_S 1184 +#define Mips_CMP_SULE_S_MMR6 1185 +#define Mips_CMP_SULT_D 1186 +#define Mips_CMP_SULT_D_MMR6 1187 +#define Mips_CMP_SULT_S 1188 +#define Mips_CMP_SULT_S_MMR6 1189 +#define Mips_CMP_SUN_D 1190 +#define Mips_CMP_SUN_D_MMR6 1191 +#define Mips_CMP_SUN_S 1192 +#define Mips_CMP_SUN_S_MMR6 1193 +#define Mips_CMP_UEQ_D 1194 +#define Mips_CMP_UEQ_D_MMR6 1195 +#define Mips_CMP_UEQ_S 1196 +#define Mips_CMP_UEQ_S_MMR6 1197 +#define Mips_CMP_ULE_D 1198 +#define Mips_CMP_ULE_D_MMR6 1199 +#define Mips_CMP_ULE_S 1200 +#define Mips_CMP_ULE_S_MMR6 1201 +#define Mips_CMP_ULT_D 1202 +#define Mips_CMP_ULT_D_MMR6 1203 +#define Mips_CMP_ULT_S 1204 +#define Mips_CMP_ULT_S_MMR6 1205 +#define Mips_CMP_UN_D 1206 +#define Mips_CMP_UN_D_MMR6 1207 +#define Mips_CMP_UN_S 1208 +#define Mips_CMP_UN_S_MMR6 1209 +#define Mips_COPY_S_B 1210 +#define Mips_COPY_S_D 1211 +#define Mips_COPY_S_H 1212 +#define Mips_COPY_S_W 1213 +#define Mips_COPY_U_B 1214 +#define Mips_COPY_U_H 1215 +#define Mips_COPY_U_W 1216 +#define Mips_CRC32B 1217 +#define Mips_CRC32CB 1218 +#define Mips_CRC32CD 1219 +#define Mips_CRC32CH 1220 +#define Mips_CRC32CW 1221 +#define Mips_CRC32D 1222 +#define Mips_CRC32H 1223 +#define Mips_CRC32W 1224 +#define Mips_CTC1 1225 +#define Mips_CTC1_MM 1226 +#define Mips_CTC2_MM 1227 +#define Mips_CTCMSA 1228 +#define Mips_CVT_D32_S 1229 +#define Mips_CVT_D32_S_MM 1230 +#define Mips_CVT_D32_W 1231 +#define Mips_CVT_D32_W_MM 1232 +#define Mips_CVT_D64_L 1233 +#define Mips_CVT_D64_S 1234 +#define Mips_CVT_D64_S_MM 1235 +#define Mips_CVT_D64_W 1236 +#define Mips_CVT_D64_W_MM 1237 +#define Mips_CVT_D_L_MMR6 1238 +#define Mips_CVT_L_D64 1239 +#define Mips_CVT_L_D64_MM 1240 +#define Mips_CVT_L_D_MMR6 1241 +#define Mips_CVT_L_S 1242 +#define Mips_CVT_L_S_MM 1243 +#define Mips_CVT_L_S_MMR6 1244 +#define Mips_CVT_PS_PW64 1245 +#define Mips_CVT_PS_S64 1246 +#define Mips_CVT_PW_PS64 1247 +#define Mips_CVT_S_D32 1248 +#define Mips_CVT_S_D32_MM 1249 +#define Mips_CVT_S_D64 1250 +#define Mips_CVT_S_D64_MM 1251 +#define Mips_CVT_S_L 1252 +#define Mips_CVT_S_L_MMR6 1253 +#define Mips_CVT_S_PL64 1254 +#define Mips_CVT_S_PU64 1255 +#define Mips_CVT_S_W 1256 +#define Mips_CVT_S_W_MM 1257 +#define Mips_CVT_S_W_MMR6 1258 +#define Mips_CVT_W_D32 1259 +#define Mips_CVT_W_D32_MM 1260 +#define Mips_CVT_W_D64 1261 +#define Mips_CVT_W_D64_MM 1262 +#define Mips_CVT_W_S 1263 +#define Mips_CVT_W_S_MM 1264 +#define Mips_CVT_W_S_MMR6 1265 +#define Mips_C_EQ_D32 1266 +#define Mips_C_EQ_D32_MM 1267 +#define Mips_C_EQ_D64 1268 +#define Mips_C_EQ_D64_MM 1269 +#define Mips_C_EQ_S 1270 +#define Mips_C_EQ_S_MM 1271 +#define Mips_C_F_D32 1272 +#define Mips_C_F_D32_MM 1273 +#define Mips_C_F_D64 1274 +#define Mips_C_F_D64_MM 1275 +#define Mips_C_F_S 1276 +#define Mips_C_F_S_MM 1277 +#define Mips_C_LE_D32 1278 +#define Mips_C_LE_D32_MM 1279 +#define Mips_C_LE_D64 1280 +#define Mips_C_LE_D64_MM 1281 +#define Mips_C_LE_S 1282 +#define Mips_C_LE_S_MM 1283 +#define Mips_C_LT_D32 1284 +#define Mips_C_LT_D32_MM 1285 +#define Mips_C_LT_D64 1286 +#define Mips_C_LT_D64_MM 1287 +#define Mips_C_LT_S 1288 +#define Mips_C_LT_S_MM 1289 +#define Mips_C_NGE_D32 1290 +#define Mips_C_NGE_D32_MM 1291 +#define Mips_C_NGE_D64 1292 +#define Mips_C_NGE_D64_MM 1293 +#define Mips_C_NGE_S 1294 +#define Mips_C_NGE_S_MM 1295 +#define Mips_C_NGLE_D32 1296 +#define Mips_C_NGLE_D32_MM 1297 +#define Mips_C_NGLE_D64 1298 +#define Mips_C_NGLE_D64_MM 1299 +#define Mips_C_NGLE_S 1300 +#define Mips_C_NGLE_S_MM 1301 +#define Mips_C_NGL_D32 1302 +#define Mips_C_NGL_D32_MM 1303 +#define Mips_C_NGL_D64 1304 +#define Mips_C_NGL_D64_MM 1305 +#define Mips_C_NGL_S 1306 +#define Mips_C_NGL_S_MM 1307 +#define Mips_C_NGT_D32 1308 +#define Mips_C_NGT_D32_MM 1309 +#define Mips_C_NGT_D64 1310 +#define Mips_C_NGT_D64_MM 1311 +#define Mips_C_NGT_S 1312 +#define Mips_C_NGT_S_MM 1313 +#define Mips_C_OLE_D32 1314 +#define Mips_C_OLE_D32_MM 1315 +#define Mips_C_OLE_D64 1316 +#define Mips_C_OLE_D64_MM 1317 +#define Mips_C_OLE_S 1318 +#define Mips_C_OLE_S_MM 1319 +#define Mips_C_OLT_D32 1320 +#define Mips_C_OLT_D32_MM 1321 +#define Mips_C_OLT_D64 1322 +#define Mips_C_OLT_D64_MM 1323 +#define Mips_C_OLT_S 1324 +#define Mips_C_OLT_S_MM 1325 +#define Mips_C_SEQ_D32 1326 +#define Mips_C_SEQ_D32_MM 1327 +#define Mips_C_SEQ_D64 1328 +#define Mips_C_SEQ_D64_MM 1329 +#define Mips_C_SEQ_S 1330 +#define Mips_C_SEQ_S_MM 1331 +#define Mips_C_SF_D32 1332 +#define Mips_C_SF_D32_MM 1333 +#define Mips_C_SF_D64 1334 +#define Mips_C_SF_D64_MM 1335 +#define Mips_C_SF_S 1336 +#define Mips_C_SF_S_MM 1337 +#define Mips_C_UEQ_D32 1338 +#define Mips_C_UEQ_D32_MM 1339 +#define Mips_C_UEQ_D64 1340 +#define Mips_C_UEQ_D64_MM 1341 +#define Mips_C_UEQ_S 1342 +#define Mips_C_UEQ_S_MM 1343 +#define Mips_C_ULE_D32 1344 +#define Mips_C_ULE_D32_MM 1345 +#define Mips_C_ULE_D64 1346 +#define Mips_C_ULE_D64_MM 1347 +#define Mips_C_ULE_S 1348 +#define Mips_C_ULE_S_MM 1349 +#define Mips_C_ULT_D32 1350 +#define Mips_C_ULT_D32_MM 1351 +#define Mips_C_ULT_D64 1352 +#define Mips_C_ULT_D64_MM 1353 +#define Mips_C_ULT_S 1354 +#define Mips_C_ULT_S_MM 1355 +#define Mips_C_UN_D32 1356 +#define Mips_C_UN_D32_MM 1357 +#define Mips_C_UN_D64 1358 +#define Mips_C_UN_D64_MM 1359 +#define Mips_C_UN_S 1360 +#define Mips_C_UN_S_MM 1361 +#define Mips_CmpRxRy16 1362 +#define Mips_CmpiRxImm16 1363 +#define Mips_CmpiRxImmX16 1364 +#define Mips_DADD 1365 +#define Mips_DADDi 1366 +#define Mips_DADDiu 1367 +#define Mips_DADDu 1368 +#define Mips_DAHI 1369 +#define Mips_DALIGN 1370 +#define Mips_DATI 1371 +#define Mips_DAUI 1372 +#define Mips_DBITSWAP 1373 +#define Mips_DCLO 1374 +#define Mips_DCLO_R6 1375 +#define Mips_DCLZ 1376 +#define Mips_DCLZ_R6 1377 +#define Mips_DDIV 1378 +#define Mips_DDIVU 1379 +#define Mips_DERET 1380 +#define Mips_DERET_MM 1381 +#define Mips_DERET_MMR6 1382 +#define Mips_DEXT 1383 +#define Mips_DEXT64_32 1384 +#define Mips_DEXTM 1385 +#define Mips_DEXTU 1386 +#define Mips_DI 1387 +#define Mips_DINS 1388 +#define Mips_DINSM 1389 +#define Mips_DINSU 1390 +#define Mips_DIV 1391 +#define Mips_DIVU 1392 +#define Mips_DIVU_MMR6 1393 +#define Mips_DIV_MMR6 1394 +#define Mips_DIV_S_B 1395 +#define Mips_DIV_S_D 1396 +#define Mips_DIV_S_H 1397 +#define Mips_DIV_S_W 1398 +#define Mips_DIV_U_B 1399 +#define Mips_DIV_U_D 1400 +#define Mips_DIV_U_H 1401 +#define Mips_DIV_U_W 1402 +#define Mips_DI_MM 1403 +#define Mips_DI_MMR6 1404 +#define Mips_DLSA 1405 +#define Mips_DLSA_R6 1406 +#define Mips_DMFC0 1407 +#define Mips_DMFC1 1408 +#define Mips_DMFC2 1409 +#define Mips_DMFC2_OCTEON 1410 +#define Mips_DMFGC0 1411 +#define Mips_DMOD 1412 +#define Mips_DMODU 1413 +#define Mips_DMT 1414 +#define Mips_DMTC0 1415 +#define Mips_DMTC1 1416 +#define Mips_DMTC2 1417 +#define Mips_DMTC2_OCTEON 1418 +#define Mips_DMTGC0 1419 +#define Mips_DMUH 1420 +#define Mips_DMUHU 1421 +#define Mips_DMUL 1422 +#define Mips_DMULT 1423 +#define Mips_DMULTu 1424 +#define Mips_DMULU 1425 +#define Mips_DMUL_R6 1426 +#define Mips_DOTP_S_D 1427 +#define Mips_DOTP_S_H 1428 +#define Mips_DOTP_S_W 1429 +#define Mips_DOTP_U_D 1430 +#define Mips_DOTP_U_H 1431 +#define Mips_DOTP_U_W 1432 +#define Mips_DPADD_S_D 1433 +#define Mips_DPADD_S_H 1434 +#define Mips_DPADD_S_W 1435 +#define Mips_DPADD_U_D 1436 +#define Mips_DPADD_U_H 1437 +#define Mips_DPADD_U_W 1438 +#define Mips_DPAQX_SA_W_PH 1439 +#define Mips_DPAQX_SA_W_PH_MMR2 1440 +#define Mips_DPAQX_S_W_PH 1441 +#define Mips_DPAQX_S_W_PH_MMR2 1442 +#define Mips_DPAQ_SA_L_W 1443 +#define Mips_DPAQ_SA_L_W_MM 1444 +#define Mips_DPAQ_S_W_PH 1445 +#define Mips_DPAQ_S_W_PH_MM 1446 +#define Mips_DPAU_H_QBL 1447 +#define Mips_DPAU_H_QBL_MM 1448 +#define Mips_DPAU_H_QBR 1449 +#define Mips_DPAU_H_QBR_MM 1450 +#define Mips_DPAX_W_PH 1451 +#define Mips_DPAX_W_PH_MMR2 1452 +#define Mips_DPA_W_PH 1453 +#define Mips_DPA_W_PH_MMR2 1454 +#define Mips_DPOP 1455 +#define Mips_DPSQX_SA_W_PH 1456 +#define Mips_DPSQX_SA_W_PH_MMR2 1457 +#define Mips_DPSQX_S_W_PH 1458 +#define Mips_DPSQX_S_W_PH_MMR2 1459 +#define Mips_DPSQ_SA_L_W 1460 +#define Mips_DPSQ_SA_L_W_MM 1461 +#define Mips_DPSQ_S_W_PH 1462 +#define Mips_DPSQ_S_W_PH_MM 1463 +#define Mips_DPSUB_S_D 1464 +#define Mips_DPSUB_S_H 1465 +#define Mips_DPSUB_S_W 1466 +#define Mips_DPSUB_U_D 1467 +#define Mips_DPSUB_U_H 1468 +#define Mips_DPSUB_U_W 1469 +#define Mips_DPSU_H_QBL 1470 +#define Mips_DPSU_H_QBL_MM 1471 +#define Mips_DPSU_H_QBR 1472 +#define Mips_DPSU_H_QBR_MM 1473 +#define Mips_DPSX_W_PH 1474 +#define Mips_DPSX_W_PH_MMR2 1475 +#define Mips_DPS_W_PH 1476 +#define Mips_DPS_W_PH_MMR2 1477 +#define Mips_DROTR 1478 +#define Mips_DROTR32 1479 +#define Mips_DROTRV 1480 +#define Mips_DSBH 1481 +#define Mips_DSDIV 1482 +#define Mips_DSHD 1483 +#define Mips_DSLL 1484 +#define Mips_DSLL32 1485 +#define Mips_DSLL64_32 1486 +#define Mips_DSLLV 1487 +#define Mips_DSRA 1488 +#define Mips_DSRA32 1489 +#define Mips_DSRAV 1490 +#define Mips_DSRL 1491 +#define Mips_DSRL32 1492 +#define Mips_DSRLV 1493 +#define Mips_DSUB 1494 +#define Mips_DSUBu 1495 +#define Mips_DUDIV 1496 +#define Mips_DVP 1497 +#define Mips_DVPE 1498 +#define Mips_DVP_MMR6 1499 +#define Mips_DivRxRy16 1500 +#define Mips_DivuRxRy16 1501 +#define Mips_EHB 1502 +#define Mips_EHB_MM 1503 +#define Mips_EHB_MMR6 1504 +#define Mips_EI 1505 +#define Mips_EI_MM 1506 +#define Mips_EI_MMR6 1507 +#define Mips_EMT 1508 +#define Mips_ERET 1509 +#define Mips_ERETNC 1510 +#define Mips_ERETNC_MMR6 1511 +#define Mips_ERET_MM 1512 +#define Mips_ERET_MMR6 1513 +#define Mips_EVP 1514 +#define Mips_EVPE 1515 +#define Mips_EVP_MMR6 1516 +#define Mips_EXT 1517 +#define Mips_EXTP 1518 +#define Mips_EXTPDP 1519 +#define Mips_EXTPDPV 1520 +#define Mips_EXTPDPV_MM 1521 +#define Mips_EXTPDP_MM 1522 +#define Mips_EXTPV 1523 +#define Mips_EXTPV_MM 1524 +#define Mips_EXTP_MM 1525 +#define Mips_EXTRV_RS_W 1526 +#define Mips_EXTRV_RS_W_MM 1527 +#define Mips_EXTRV_R_W 1528 +#define Mips_EXTRV_R_W_MM 1529 +#define Mips_EXTRV_S_H 1530 +#define Mips_EXTRV_S_H_MM 1531 +#define Mips_EXTRV_W 1532 +#define Mips_EXTRV_W_MM 1533 +#define Mips_EXTR_RS_W 1534 +#define Mips_EXTR_RS_W_MM 1535 +#define Mips_EXTR_R_W 1536 +#define Mips_EXTR_R_W_MM 1537 +#define Mips_EXTR_S_H 1538 +#define Mips_EXTR_S_H_MM 1539 +#define Mips_EXTR_W 1540 +#define Mips_EXTR_W_MM 1541 +#define Mips_EXTS 1542 +#define Mips_EXTS32 1543 +#define Mips_EXT_MM 1544 +#define Mips_EXT_MMR6 1545 +#define Mips_FABS_D32 1546 +#define Mips_FABS_D32_MM 1547 +#define Mips_FABS_D64 1548 +#define Mips_FABS_D64_MM 1549 +#define Mips_FABS_S 1550 +#define Mips_FABS_S_MM 1551 +#define Mips_FADD_D 1552 +#define Mips_FADD_D32 1553 +#define Mips_FADD_D32_MM 1554 +#define Mips_FADD_D64 1555 +#define Mips_FADD_D64_MM 1556 +#define Mips_FADD_PS64 1557 +#define Mips_FADD_S 1558 +#define Mips_FADD_S_MM 1559 +#define Mips_FADD_S_MMR6 1560 +#define Mips_FADD_W 1561 +#define Mips_FCAF_D 1562 +#define Mips_FCAF_W 1563 +#define Mips_FCEQ_D 1564 +#define Mips_FCEQ_W 1565 +#define Mips_FCLASS_D 1566 +#define Mips_FCLASS_W 1567 +#define Mips_FCLE_D 1568 +#define Mips_FCLE_W 1569 +#define Mips_FCLT_D 1570 +#define Mips_FCLT_W 1571 +#define Mips_FCMP_D32 1572 +#define Mips_FCMP_D32_MM 1573 +#define Mips_FCMP_D64 1574 +#define Mips_FCMP_S32 1575 +#define Mips_FCMP_S32_MM 1576 +#define Mips_FCNE_D 1577 +#define Mips_FCNE_W 1578 +#define Mips_FCOR_D 1579 +#define Mips_FCOR_W 1580 +#define Mips_FCUEQ_D 1581 +#define Mips_FCUEQ_W 1582 +#define Mips_FCULE_D 1583 +#define Mips_FCULE_W 1584 +#define Mips_FCULT_D 1585 +#define Mips_FCULT_W 1586 +#define Mips_FCUNE_D 1587 +#define Mips_FCUNE_W 1588 +#define Mips_FCUN_D 1589 +#define Mips_FCUN_W 1590 +#define Mips_FDIV_D 1591 +#define Mips_FDIV_D32 1592 +#define Mips_FDIV_D32_MM 1593 +#define Mips_FDIV_D64 1594 +#define Mips_FDIV_D64_MM 1595 +#define Mips_FDIV_S 1596 +#define Mips_FDIV_S_MM 1597 +#define Mips_FDIV_S_MMR6 1598 +#define Mips_FDIV_W 1599 +#define Mips_FEXDO_H 1600 +#define Mips_FEXDO_W 1601 +#define Mips_FEXP2_D 1602 +#define Mips_FEXP2_W 1603 +#define Mips_FEXUPL_D 1604 +#define Mips_FEXUPL_W 1605 +#define Mips_FEXUPR_D 1606 +#define Mips_FEXUPR_W 1607 +#define Mips_FFINT_S_D 1608 +#define Mips_FFINT_S_W 1609 +#define Mips_FFINT_U_D 1610 +#define Mips_FFINT_U_W 1611 +#define Mips_FFQL_D 1612 +#define Mips_FFQL_W 1613 +#define Mips_FFQR_D 1614 +#define Mips_FFQR_W 1615 +#define Mips_FILL_B 1616 +#define Mips_FILL_D 1617 +#define Mips_FILL_H 1618 +#define Mips_FILL_W 1619 +#define Mips_FLOG2_D 1620 +#define Mips_FLOG2_W 1621 +#define Mips_FLOOR_L_D64 1622 +#define Mips_FLOOR_L_D_MMR6 1623 +#define Mips_FLOOR_L_S 1624 +#define Mips_FLOOR_L_S_MMR6 1625 +#define Mips_FLOOR_W_D32 1626 +#define Mips_FLOOR_W_D64 1627 +#define Mips_FLOOR_W_D_MMR6 1628 +#define Mips_FLOOR_W_MM 1629 +#define Mips_FLOOR_W_S 1630 +#define Mips_FLOOR_W_S_MM 1631 +#define Mips_FLOOR_W_S_MMR6 1632 +#define Mips_FMADD_D 1633 +#define Mips_FMADD_W 1634 +#define Mips_FMAX_A_D 1635 +#define Mips_FMAX_A_W 1636 +#define Mips_FMAX_D 1637 +#define Mips_FMAX_W 1638 +#define Mips_FMIN_A_D 1639 +#define Mips_FMIN_A_W 1640 +#define Mips_FMIN_D 1641 +#define Mips_FMIN_W 1642 +#define Mips_FMOV_D32 1643 +#define Mips_FMOV_D32_MM 1644 +#define Mips_FMOV_D64 1645 +#define Mips_FMOV_D64_MM 1646 +#define Mips_FMOV_D_MMR6 1647 +#define Mips_FMOV_S 1648 +#define Mips_FMOV_S_MM 1649 +#define Mips_FMOV_S_MMR6 1650 +#define Mips_FMSUB_D 1651 +#define Mips_FMSUB_W 1652 +#define Mips_FMUL_D 1653 +#define Mips_FMUL_D32 1654 +#define Mips_FMUL_D32_MM 1655 +#define Mips_FMUL_D64 1656 +#define Mips_FMUL_D64_MM 1657 +#define Mips_FMUL_PS64 1658 +#define Mips_FMUL_S 1659 +#define Mips_FMUL_S_MM 1660 +#define Mips_FMUL_S_MMR6 1661 +#define Mips_FMUL_W 1662 +#define Mips_FNEG_D32 1663 +#define Mips_FNEG_D32_MM 1664 +#define Mips_FNEG_D64 1665 +#define Mips_FNEG_D64_MM 1666 +#define Mips_FNEG_S 1667 +#define Mips_FNEG_S_MM 1668 +#define Mips_FNEG_S_MMR6 1669 +#define Mips_FORK 1670 +#define Mips_FRCP_D 1671 +#define Mips_FRCP_W 1672 +#define Mips_FRINT_D 1673 +#define Mips_FRINT_W 1674 +#define Mips_FRSQRT_D 1675 +#define Mips_FRSQRT_W 1676 +#define Mips_FSAF_D 1677 +#define Mips_FSAF_W 1678 +#define Mips_FSEQ_D 1679 +#define Mips_FSEQ_W 1680 +#define Mips_FSLE_D 1681 +#define Mips_FSLE_W 1682 +#define Mips_FSLT_D 1683 +#define Mips_FSLT_W 1684 +#define Mips_FSNE_D 1685 +#define Mips_FSNE_W 1686 +#define Mips_FSOR_D 1687 +#define Mips_FSOR_W 1688 +#define Mips_FSQRT_D 1689 +#define Mips_FSQRT_D32 1690 +#define Mips_FSQRT_D32_MM 1691 +#define Mips_FSQRT_D64 1692 +#define Mips_FSQRT_D64_MM 1693 +#define Mips_FSQRT_S 1694 +#define Mips_FSQRT_S_MM 1695 +#define Mips_FSQRT_W 1696 +#define Mips_FSUB_D 1697 +#define Mips_FSUB_D32 1698 +#define Mips_FSUB_D32_MM 1699 +#define Mips_FSUB_D64 1700 +#define Mips_FSUB_D64_MM 1701 +#define Mips_FSUB_PS64 1702 +#define Mips_FSUB_S 1703 +#define Mips_FSUB_S_MM 1704 +#define Mips_FSUB_S_MMR6 1705 +#define Mips_FSUB_W 1706 +#define Mips_FSUEQ_D 1707 +#define Mips_FSUEQ_W 1708 +#define Mips_FSULE_D 1709 +#define Mips_FSULE_W 1710 +#define Mips_FSULT_D 1711 +#define Mips_FSULT_W 1712 +#define Mips_FSUNE_D 1713 +#define Mips_FSUNE_W 1714 +#define Mips_FSUN_D 1715 +#define Mips_FSUN_W 1716 +#define Mips_FTINT_S_D 1717 +#define Mips_FTINT_S_W 1718 +#define Mips_FTINT_U_D 1719 +#define Mips_FTINT_U_W 1720 +#define Mips_FTQ_H 1721 +#define Mips_FTQ_W 1722 +#define Mips_FTRUNC_S_D 1723 +#define Mips_FTRUNC_S_W 1724 +#define Mips_FTRUNC_U_D 1725 +#define Mips_FTRUNC_U_W 1726 +#define Mips_GINVI 1727 +#define Mips_GINVI_MMR6 1728 +#define Mips_GINVT 1729 +#define Mips_GINVT_MMR6 1730 +#define Mips_HADD_S_D 1731 +#define Mips_HADD_S_H 1732 +#define Mips_HADD_S_W 1733 +#define Mips_HADD_U_D 1734 +#define Mips_HADD_U_H 1735 +#define Mips_HADD_U_W 1736 +#define Mips_HSUB_S_D 1737 +#define Mips_HSUB_S_H 1738 +#define Mips_HSUB_S_W 1739 +#define Mips_HSUB_U_D 1740 +#define Mips_HSUB_U_H 1741 +#define Mips_HSUB_U_W 1742 +#define Mips_HYPCALL 1743 +#define Mips_HYPCALL_MM 1744 +#define Mips_ILVEV_B 1745 +#define Mips_ILVEV_D 1746 +#define Mips_ILVEV_H 1747 +#define Mips_ILVEV_W 1748 +#define Mips_ILVL_B 1749 +#define Mips_ILVL_D 1750 +#define Mips_ILVL_H 1751 +#define Mips_ILVL_W 1752 +#define Mips_ILVOD_B 1753 +#define Mips_ILVOD_D 1754 +#define Mips_ILVOD_H 1755 +#define Mips_ILVOD_W 1756 +#define Mips_ILVR_B 1757 +#define Mips_ILVR_D 1758 +#define Mips_ILVR_H 1759 +#define Mips_ILVR_W 1760 +#define Mips_INS 1761 +#define Mips_INSERT_B 1762 +#define Mips_INSERT_D 1763 +#define Mips_INSERT_H 1764 +#define Mips_INSERT_W 1765 +#define Mips_INSV 1766 +#define Mips_INSVE_B 1767 +#define Mips_INSVE_D 1768 +#define Mips_INSVE_H 1769 +#define Mips_INSVE_W 1770 +#define Mips_INSV_MM 1771 +#define Mips_INS_MM 1772 +#define Mips_INS_MMR6 1773 +#define Mips_J 1774 +#define Mips_JAL 1775 +#define Mips_JALR 1776 +#define Mips_JALR16_MM 1777 +#define Mips_JALR64 1778 +#define Mips_JALRC16_MMR6 1779 +#define Mips_JALRC_HB_MMR6 1780 +#define Mips_JALRC_MMR6 1781 +#define Mips_JALRS16_MM 1782 +#define Mips_JALRS_MM 1783 +#define Mips_JALR_HB 1784 +#define Mips_JALR_HB64 1785 +#define Mips_JALR_MM 1786 +#define Mips_JALS_MM 1787 +#define Mips_JALX 1788 +#define Mips_JALX_MM 1789 +#define Mips_JAL_MM 1790 +#define Mips_JIALC 1791 +#define Mips_JIALC64 1792 +#define Mips_JIALC_MMR6 1793 +#define Mips_JIC 1794 +#define Mips_JIC64 1795 +#define Mips_JIC_MMR6 1796 +#define Mips_JR 1797 +#define Mips_JR16_MM 1798 +#define Mips_JR64 1799 +#define Mips_JRADDIUSP 1800 +#define Mips_JRC16_MM 1801 +#define Mips_JRC16_MMR6 1802 +#define Mips_JRCADDIUSP_MMR6 1803 +#define Mips_JR_HB 1804 +#define Mips_JR_HB64 1805 +#define Mips_JR_HB64_R6 1806 +#define Mips_JR_HB_R6 1807 +#define Mips_JR_MM 1808 +#define Mips_J_MM 1809 +#define Mips_Jal16 1810 +#define Mips_JalB16 1811 +#define Mips_JrRa16 1812 +#define Mips_JrcRa16 1813 +#define Mips_JrcRx16 1814 +#define Mips_JumpLinkReg16 1815 +#define Mips_LB 1816 +#define Mips_LB64 1817 +#define Mips_LBE 1818 +#define Mips_LBE_MM 1819 +#define Mips_LBU16_MM 1820 +#define Mips_LBUX 1821 +#define Mips_LBUX_MM 1822 +#define Mips_LBU_MMR6 1823 +#define Mips_LB_MM 1824 +#define Mips_LB_MMR6 1825 +#define Mips_LBu 1826 +#define Mips_LBu64 1827 +#define Mips_LBuE 1828 +#define Mips_LBuE_MM 1829 +#define Mips_LBu_MM 1830 +#define Mips_LD 1831 +#define Mips_LDC1 1832 +#define Mips_LDC164 1833 +#define Mips_LDC1_D64_MMR6 1834 +#define Mips_LDC1_MM 1835 +#define Mips_LDC2 1836 +#define Mips_LDC2_MMR6 1837 +#define Mips_LDC2_R6 1838 +#define Mips_LDC3 1839 +#define Mips_LDI_B 1840 +#define Mips_LDI_D 1841 +#define Mips_LDI_H 1842 +#define Mips_LDI_W 1843 +#define Mips_LDL 1844 +#define Mips_LDPC 1845 +#define Mips_LDR 1846 +#define Mips_LDXC1 1847 +#define Mips_LDXC164 1848 +#define Mips_LD_B 1849 +#define Mips_LD_D 1850 +#define Mips_LD_H 1851 +#define Mips_LD_W 1852 +#define Mips_LEA_ADDiu 1853 +#define Mips_LEA_ADDiu64 1854 +#define Mips_LEA_ADDiu_MM 1855 +#define Mips_LH 1856 +#define Mips_LH64 1857 +#define Mips_LHE 1858 +#define Mips_LHE_MM 1859 +#define Mips_LHU16_MM 1860 +#define Mips_LHX 1861 +#define Mips_LHX_MM 1862 +#define Mips_LH_MM 1863 +#define Mips_LHu 1864 +#define Mips_LHu64 1865 +#define Mips_LHuE 1866 +#define Mips_LHuE_MM 1867 +#define Mips_LHu_MM 1868 +#define Mips_LI16_MM 1869 +#define Mips_LI16_MMR6 1870 +#define Mips_LL 1871 +#define Mips_LL64 1872 +#define Mips_LL64_R6 1873 +#define Mips_LLD 1874 +#define Mips_LLD_R6 1875 +#define Mips_LLE 1876 +#define Mips_LLE_MM 1877 +#define Mips_LL_MM 1878 +#define Mips_LL_MMR6 1879 +#define Mips_LL_R6 1880 +#define Mips_LSA 1881 +#define Mips_LSA_MMR6 1882 +#define Mips_LSA_R6 1883 +#define Mips_LUI_MMR6 1884 +#define Mips_LUXC1 1885 +#define Mips_LUXC164 1886 +#define Mips_LUXC1_MM 1887 +#define Mips_LUi 1888 +#define Mips_LUi64 1889 +#define Mips_LUi_MM 1890 +#define Mips_LW 1891 +#define Mips_LW16_MM 1892 +#define Mips_LW64 1893 +#define Mips_LWC1 1894 +#define Mips_LWC1_MM 1895 +#define Mips_LWC2 1896 +#define Mips_LWC2_MMR6 1897 +#define Mips_LWC2_R6 1898 +#define Mips_LWC3 1899 +#define Mips_LWDSP 1900 +#define Mips_LWDSP_MM 1901 +#define Mips_LWE 1902 +#define Mips_LWE_MM 1903 +#define Mips_LWGP_MM 1904 +#define Mips_LWL 1905 +#define Mips_LWL64 1906 +#define Mips_LWLE 1907 +#define Mips_LWLE_MM 1908 +#define Mips_LWL_MM 1909 +#define Mips_LWM16_MM 1910 +#define Mips_LWM16_MMR6 1911 +#define Mips_LWM32_MM 1912 +#define Mips_LWPC 1913 +#define Mips_LWPC_MMR6 1914 +#define Mips_LWP_MM 1915 +#define Mips_LWR 1916 +#define Mips_LWR64 1917 +#define Mips_LWRE 1918 +#define Mips_LWRE_MM 1919 +#define Mips_LWR_MM 1920 +#define Mips_LWSP_MM 1921 +#define Mips_LWUPC 1922 +#define Mips_LWU_MM 1923 +#define Mips_LWX 1924 +#define Mips_LWXC1 1925 +#define Mips_LWXC1_MM 1926 +#define Mips_LWXS_MM 1927 +#define Mips_LWX_MM 1928 +#define Mips_LW_MM 1929 +#define Mips_LW_MMR6 1930 +#define Mips_LWu 1931 +#define Mips_LbRxRyOffMemX16 1932 +#define Mips_LbuRxRyOffMemX16 1933 +#define Mips_LhRxRyOffMemX16 1934 +#define Mips_LhuRxRyOffMemX16 1935 +#define Mips_LiRxImm16 1936 +#define Mips_LiRxImmAlignX16 1937 +#define Mips_LiRxImmX16 1938 +#define Mips_LwRxPcTcp16 1939 +#define Mips_LwRxPcTcpX16 1940 +#define Mips_LwRxRyOffMemX16 1941 +#define Mips_LwRxSpImmX16 1942 +#define Mips_MADD 1943 +#define Mips_MADDF_D 1944 +#define Mips_MADDF_D_MMR6 1945 +#define Mips_MADDF_S 1946 +#define Mips_MADDF_S_MMR6 1947 +#define Mips_MADDR_Q_H 1948 +#define Mips_MADDR_Q_W 1949 +#define Mips_MADDU 1950 +#define Mips_MADDU_DSP 1951 +#define Mips_MADDU_DSP_MM 1952 +#define Mips_MADDU_MM 1953 +#define Mips_MADDV_B 1954 +#define Mips_MADDV_D 1955 +#define Mips_MADDV_H 1956 +#define Mips_MADDV_W 1957 +#define Mips_MADD_D32 1958 +#define Mips_MADD_D32_MM 1959 +#define Mips_MADD_D64 1960 +#define Mips_MADD_DSP 1961 +#define Mips_MADD_DSP_MM 1962 +#define Mips_MADD_MM 1963 +#define Mips_MADD_Q_H 1964 +#define Mips_MADD_Q_W 1965 +#define Mips_MADD_S 1966 +#define Mips_MADD_S_MM 1967 +#define Mips_MAQ_SA_W_PHL 1968 +#define Mips_MAQ_SA_W_PHL_MM 1969 +#define Mips_MAQ_SA_W_PHR 1970 +#define Mips_MAQ_SA_W_PHR_MM 1971 +#define Mips_MAQ_S_W_PHL 1972 +#define Mips_MAQ_S_W_PHL_MM 1973 +#define Mips_MAQ_S_W_PHR 1974 +#define Mips_MAQ_S_W_PHR_MM 1975 +#define Mips_MAXA_D 1976 +#define Mips_MAXA_D_MMR6 1977 +#define Mips_MAXA_S 1978 +#define Mips_MAXA_S_MMR6 1979 +#define Mips_MAXI_S_B 1980 +#define Mips_MAXI_S_D 1981 +#define Mips_MAXI_S_H 1982 +#define Mips_MAXI_S_W 1983 +#define Mips_MAXI_U_B 1984 +#define Mips_MAXI_U_D 1985 +#define Mips_MAXI_U_H 1986 +#define Mips_MAXI_U_W 1987 +#define Mips_MAX_A_B 1988 +#define Mips_MAX_A_D 1989 +#define Mips_MAX_A_H 1990 +#define Mips_MAX_A_W 1991 +#define Mips_MAX_D 1992 +#define Mips_MAX_D_MMR6 1993 +#define Mips_MAX_S 1994 +#define Mips_MAX_S_B 1995 +#define Mips_MAX_S_D 1996 +#define Mips_MAX_S_H 1997 +#define Mips_MAX_S_MMR6 1998 +#define Mips_MAX_S_W 1999 +#define Mips_MAX_U_B 2000 +#define Mips_MAX_U_D 2001 +#define Mips_MAX_U_H 2002 +#define Mips_MAX_U_W 2003 +#define Mips_MFC0 2004 +#define Mips_MFC0_MMR6 2005 +#define Mips_MFC1 2006 +#define Mips_MFC1_D64 2007 +#define Mips_MFC1_MM 2008 +#define Mips_MFC1_MMR6 2009 +#define Mips_MFC2 2010 +#define Mips_MFC2_MMR6 2011 +#define Mips_MFGC0 2012 +#define Mips_MFGC0_MM 2013 +#define Mips_MFHC0_MMR6 2014 +#define Mips_MFHC1_D32 2015 +#define Mips_MFHC1_D32_MM 2016 +#define Mips_MFHC1_D64 2017 +#define Mips_MFHC1_D64_MM 2018 +#define Mips_MFHC2_MMR6 2019 +#define Mips_MFHGC0 2020 +#define Mips_MFHGC0_MM 2021 +#define Mips_MFHI 2022 +#define Mips_MFHI16_MM 2023 +#define Mips_MFHI64 2024 +#define Mips_MFHI_DSP 2025 +#define Mips_MFHI_DSP_MM 2026 +#define Mips_MFHI_MM 2027 +#define Mips_MFLO 2028 +#define Mips_MFLO16_MM 2029 +#define Mips_MFLO64 2030 +#define Mips_MFLO_DSP 2031 +#define Mips_MFLO_DSP_MM 2032 +#define Mips_MFLO_MM 2033 +#define Mips_MFTR 2034 +#define Mips_MINA_D 2035 +#define Mips_MINA_D_MMR6 2036 +#define Mips_MINA_S 2037 +#define Mips_MINA_S_MMR6 2038 +#define Mips_MINI_S_B 2039 +#define Mips_MINI_S_D 2040 +#define Mips_MINI_S_H 2041 +#define Mips_MINI_S_W 2042 +#define Mips_MINI_U_B 2043 +#define Mips_MINI_U_D 2044 +#define Mips_MINI_U_H 2045 +#define Mips_MINI_U_W 2046 +#define Mips_MIN_A_B 2047 +#define Mips_MIN_A_D 2048 +#define Mips_MIN_A_H 2049 +#define Mips_MIN_A_W 2050 +#define Mips_MIN_D 2051 +#define Mips_MIN_D_MMR6 2052 +#define Mips_MIN_S 2053 +#define Mips_MIN_S_B 2054 +#define Mips_MIN_S_D 2055 +#define Mips_MIN_S_H 2056 +#define Mips_MIN_S_MMR6 2057 +#define Mips_MIN_S_W 2058 +#define Mips_MIN_U_B 2059 +#define Mips_MIN_U_D 2060 +#define Mips_MIN_U_H 2061 +#define Mips_MIN_U_W 2062 +#define Mips_MOD 2063 +#define Mips_MODSUB 2064 +#define Mips_MODSUB_MM 2065 +#define Mips_MODU 2066 +#define Mips_MODU_MMR6 2067 +#define Mips_MOD_MMR6 2068 +#define Mips_MOD_S_B 2069 +#define Mips_MOD_S_D 2070 +#define Mips_MOD_S_H 2071 +#define Mips_MOD_S_W 2072 +#define Mips_MOD_U_B 2073 +#define Mips_MOD_U_D 2074 +#define Mips_MOD_U_H 2075 +#define Mips_MOD_U_W 2076 +#define Mips_MOVE16_MM 2077 +#define Mips_MOVE16_MMR6 2078 +#define Mips_MOVEP_MM 2079 +#define Mips_MOVEP_MMR6 2080 +#define Mips_MOVE_V 2081 +#define Mips_MOVF_D32 2082 +#define Mips_MOVF_D32_MM 2083 +#define Mips_MOVF_D64 2084 +#define Mips_MOVF_I 2085 +#define Mips_MOVF_I64 2086 +#define Mips_MOVF_I_MM 2087 +#define Mips_MOVF_S 2088 +#define Mips_MOVF_S_MM 2089 +#define Mips_MOVN_I64_D64 2090 +#define Mips_MOVN_I64_I 2091 +#define Mips_MOVN_I64_I64 2092 +#define Mips_MOVN_I64_S 2093 +#define Mips_MOVN_I_D32 2094 +#define Mips_MOVN_I_D32_MM 2095 +#define Mips_MOVN_I_D64 2096 +#define Mips_MOVN_I_I 2097 +#define Mips_MOVN_I_I64 2098 +#define Mips_MOVN_I_MM 2099 +#define Mips_MOVN_I_S 2100 +#define Mips_MOVN_I_S_MM 2101 +#define Mips_MOVT_D32 2102 +#define Mips_MOVT_D32_MM 2103 +#define Mips_MOVT_D64 2104 +#define Mips_MOVT_I 2105 +#define Mips_MOVT_I64 2106 +#define Mips_MOVT_I_MM 2107 +#define Mips_MOVT_S 2108 +#define Mips_MOVT_S_MM 2109 +#define Mips_MOVZ_I64_D64 2110 +#define Mips_MOVZ_I64_I 2111 +#define Mips_MOVZ_I64_I64 2112 +#define Mips_MOVZ_I64_S 2113 +#define Mips_MOVZ_I_D32 2114 +#define Mips_MOVZ_I_D32_MM 2115 +#define Mips_MOVZ_I_D64 2116 +#define Mips_MOVZ_I_I 2117 +#define Mips_MOVZ_I_I64 2118 +#define Mips_MOVZ_I_MM 2119 +#define Mips_MOVZ_I_S 2120 +#define Mips_MOVZ_I_S_MM 2121 +#define Mips_MSUB 2122 +#define Mips_MSUBF_D 2123 +#define Mips_MSUBF_D_MMR6 2124 +#define Mips_MSUBF_S 2125 +#define Mips_MSUBF_S_MMR6 2126 +#define Mips_MSUBR_Q_H 2127 +#define Mips_MSUBR_Q_W 2128 +#define Mips_MSUBU 2129 +#define Mips_MSUBU_DSP 2130 +#define Mips_MSUBU_DSP_MM 2131 +#define Mips_MSUBU_MM 2132 +#define Mips_MSUBV_B 2133 +#define Mips_MSUBV_D 2134 +#define Mips_MSUBV_H 2135 +#define Mips_MSUBV_W 2136 +#define Mips_MSUB_D32 2137 +#define Mips_MSUB_D32_MM 2138 +#define Mips_MSUB_D64 2139 +#define Mips_MSUB_DSP 2140 +#define Mips_MSUB_DSP_MM 2141 +#define Mips_MSUB_MM 2142 +#define Mips_MSUB_Q_H 2143 +#define Mips_MSUB_Q_W 2144 +#define Mips_MSUB_S 2145 +#define Mips_MSUB_S_MM 2146 +#define Mips_MTC0 2147 +#define Mips_MTC0_MMR6 2148 +#define Mips_MTC1 2149 +#define Mips_MTC1_D64 2150 +#define Mips_MTC1_D64_MM 2151 +#define Mips_MTC1_MM 2152 +#define Mips_MTC1_MMR6 2153 +#define Mips_MTC2 2154 +#define Mips_MTC2_MMR6 2155 +#define Mips_MTGC0 2156 +#define Mips_MTGC0_MM 2157 +#define Mips_MTHC0_MMR6 2158 +#define Mips_MTHC1_D32 2159 +#define Mips_MTHC1_D32_MM 2160 +#define Mips_MTHC1_D64 2161 +#define Mips_MTHC1_D64_MM 2162 +#define Mips_MTHC2_MMR6 2163 +#define Mips_MTHGC0 2164 +#define Mips_MTHGC0_MM 2165 +#define Mips_MTHI 2166 +#define Mips_MTHI64 2167 +#define Mips_MTHI_DSP 2168 +#define Mips_MTHI_DSP_MM 2169 +#define Mips_MTHI_MM 2170 +#define Mips_MTHLIP 2171 +#define Mips_MTHLIP_MM 2172 +#define Mips_MTLO 2173 +#define Mips_MTLO64 2174 +#define Mips_MTLO_DSP 2175 +#define Mips_MTLO_DSP_MM 2176 +#define Mips_MTLO_MM 2177 +#define Mips_MTM0 2178 +#define Mips_MTM1 2179 +#define Mips_MTM2 2180 +#define Mips_MTP0 2181 +#define Mips_MTP1 2182 +#define Mips_MTP2 2183 +#define Mips_MTTR 2184 +#define Mips_MUH 2185 +#define Mips_MUHU 2186 +#define Mips_MUHU_MMR6 2187 +#define Mips_MUH_MMR6 2188 +#define Mips_MUL 2189 +#define Mips_MULEQ_S_W_PHL 2190 +#define Mips_MULEQ_S_W_PHL_MM 2191 +#define Mips_MULEQ_S_W_PHR 2192 +#define Mips_MULEQ_S_W_PHR_MM 2193 +#define Mips_MULEU_S_PH_QBL 2194 +#define Mips_MULEU_S_PH_QBL_MM 2195 +#define Mips_MULEU_S_PH_QBR 2196 +#define Mips_MULEU_S_PH_QBR_MM 2197 +#define Mips_MULQ_RS_PH 2198 +#define Mips_MULQ_RS_PH_MM 2199 +#define Mips_MULQ_RS_W 2200 +#define Mips_MULQ_RS_W_MMR2 2201 +#define Mips_MULQ_S_PH 2202 +#define Mips_MULQ_S_PH_MMR2 2203 +#define Mips_MULQ_S_W 2204 +#define Mips_MULQ_S_W_MMR2 2205 +#define Mips_MULR_PS64 2206 +#define Mips_MULR_Q_H 2207 +#define Mips_MULR_Q_W 2208 +#define Mips_MULSAQ_S_W_PH 2209 +#define Mips_MULSAQ_S_W_PH_MM 2210 +#define Mips_MULSA_W_PH 2211 +#define Mips_MULSA_W_PH_MMR2 2212 +#define Mips_MULT 2213 +#define Mips_MULTU_DSP 2214 +#define Mips_MULTU_DSP_MM 2215 +#define Mips_MULT_DSP 2216 +#define Mips_MULT_DSP_MM 2217 +#define Mips_MULT_MM 2218 +#define Mips_MULTu 2219 +#define Mips_MULTu_MM 2220 +#define Mips_MULU 2221 +#define Mips_MULU_MMR6 2222 +#define Mips_MULV_B 2223 +#define Mips_MULV_D 2224 +#define Mips_MULV_H 2225 +#define Mips_MULV_W 2226 +#define Mips_MUL_MM 2227 +#define Mips_MUL_MMR6 2228 +#define Mips_MUL_PH 2229 +#define Mips_MUL_PH_MMR2 2230 +#define Mips_MUL_Q_H 2231 +#define Mips_MUL_Q_W 2232 +#define Mips_MUL_R6 2233 +#define Mips_MUL_S_PH 2234 +#define Mips_MUL_S_PH_MMR2 2235 +#define Mips_Mfhi16 2236 +#define Mips_Mflo16 2237 +#define Mips_Move32R16 2238 +#define Mips_MoveR3216 2239 +#define Mips_NLOC_B 2240 +#define Mips_NLOC_D 2241 +#define Mips_NLOC_H 2242 +#define Mips_NLOC_W 2243 +#define Mips_NLZC_B 2244 +#define Mips_NLZC_D 2245 +#define Mips_NLZC_H 2246 +#define Mips_NLZC_W 2247 +#define Mips_NMADD_D32 2248 +#define Mips_NMADD_D32_MM 2249 +#define Mips_NMADD_D64 2250 +#define Mips_NMADD_S 2251 +#define Mips_NMADD_S_MM 2252 +#define Mips_NMSUB_D32 2253 +#define Mips_NMSUB_D32_MM 2254 +#define Mips_NMSUB_D64 2255 +#define Mips_NMSUB_S 2256 +#define Mips_NMSUB_S_MM 2257 +#define Mips_NOR 2258 +#define Mips_NOR64 2259 +#define Mips_NORI_B 2260 +#define Mips_NOR_MM 2261 +#define Mips_NOR_MMR6 2262 +#define Mips_NOR_V 2263 +#define Mips_NOT16_MM 2264 +#define Mips_NOT16_MMR6 2265 +#define Mips_NegRxRy16 2266 +#define Mips_NotRxRy16 2267 +#define Mips_OR 2268 +#define Mips_OR16_MM 2269 +#define Mips_OR16_MMR6 2270 +#define Mips_OR64 2271 +#define Mips_ORI_B 2272 +#define Mips_ORI_MMR6 2273 +#define Mips_OR_MM 2274 +#define Mips_OR_MMR6 2275 +#define Mips_OR_V 2276 +#define Mips_ORi 2277 +#define Mips_ORi64 2278 +#define Mips_ORi_MM 2279 +#define Mips_OrRxRxRy16 2280 +#define Mips_PACKRL_PH 2281 +#define Mips_PACKRL_PH_MM 2282 +#define Mips_PAUSE 2283 +#define Mips_PAUSE_MM 2284 +#define Mips_PAUSE_MMR6 2285 +#define Mips_PCKEV_B 2286 +#define Mips_PCKEV_D 2287 +#define Mips_PCKEV_H 2288 +#define Mips_PCKEV_W 2289 +#define Mips_PCKOD_B 2290 +#define Mips_PCKOD_D 2291 +#define Mips_PCKOD_H 2292 +#define Mips_PCKOD_W 2293 +#define Mips_PCNT_B 2294 +#define Mips_PCNT_D 2295 +#define Mips_PCNT_H 2296 +#define Mips_PCNT_W 2297 +#define Mips_PICK_PH 2298 +#define Mips_PICK_PH_MM 2299 +#define Mips_PICK_QB 2300 +#define Mips_PICK_QB_MM 2301 +#define Mips_PLL_PS64 2302 +#define Mips_PLU_PS64 2303 +#define Mips_POP 2304 +#define Mips_PRECEQU_PH_QBL 2305 +#define Mips_PRECEQU_PH_QBLA 2306 +#define Mips_PRECEQU_PH_QBLA_MM 2307 +#define Mips_PRECEQU_PH_QBL_MM 2308 +#define Mips_PRECEQU_PH_QBR 2309 +#define Mips_PRECEQU_PH_QBRA 2310 +#define Mips_PRECEQU_PH_QBRA_MM 2311 +#define Mips_PRECEQU_PH_QBR_MM 2312 +#define Mips_PRECEQ_W_PHL 2313 +#define Mips_PRECEQ_W_PHL_MM 2314 +#define Mips_PRECEQ_W_PHR 2315 +#define Mips_PRECEQ_W_PHR_MM 2316 +#define Mips_PRECEU_PH_QBL 2317 +#define Mips_PRECEU_PH_QBLA 2318 +#define Mips_PRECEU_PH_QBLA_MM 2319 +#define Mips_PRECEU_PH_QBL_MM 2320 +#define Mips_PRECEU_PH_QBR 2321 +#define Mips_PRECEU_PH_QBRA 2322 +#define Mips_PRECEU_PH_QBRA_MM 2323 +#define Mips_PRECEU_PH_QBR_MM 2324 +#define Mips_PRECRQU_S_QB_PH 2325 +#define Mips_PRECRQU_S_QB_PH_MM 2326 +#define Mips_PRECRQ_PH_W 2327 +#define Mips_PRECRQ_PH_W_MM 2328 +#define Mips_PRECRQ_QB_PH 2329 +#define Mips_PRECRQ_QB_PH_MM 2330 +#define Mips_PRECRQ_RS_PH_W 2331 +#define Mips_PRECRQ_RS_PH_W_MM 2332 +#define Mips_PRECR_QB_PH 2333 +#define Mips_PRECR_QB_PH_MMR2 2334 +#define Mips_PRECR_SRA_PH_W 2335 +#define Mips_PRECR_SRA_PH_W_MMR2 2336 +#define Mips_PRECR_SRA_R_PH_W 2337 +#define Mips_PRECR_SRA_R_PH_W_MMR2 2338 +#define Mips_PREF 2339 +#define Mips_PREFE 2340 +#define Mips_PREFE_MM 2341 +#define Mips_PREFX_MM 2342 +#define Mips_PREF_MM 2343 +#define Mips_PREF_MMR6 2344 +#define Mips_PREF_R6 2345 +#define Mips_PREPEND 2346 +#define Mips_PREPEND_MMR2 2347 +#define Mips_PUL_PS64 2348 +#define Mips_PUU_PS64 2349 +#define Mips_RADDU_W_QB 2350 +#define Mips_RADDU_W_QB_MM 2351 +#define Mips_RDDSP 2352 +#define Mips_RDDSP_MM 2353 +#define Mips_RDHWR 2354 +#define Mips_RDHWR64 2355 +#define Mips_RDHWR_MM 2356 +#define Mips_RDHWR_MMR6 2357 +#define Mips_RDPGPR_MMR6 2358 +#define Mips_RECIP_D32 2359 +#define Mips_RECIP_D32_MM 2360 +#define Mips_RECIP_D64 2361 +#define Mips_RECIP_D64_MM 2362 +#define Mips_RECIP_S 2363 +#define Mips_RECIP_S_MM 2364 +#define Mips_REPLV_PH 2365 +#define Mips_REPLV_PH_MM 2366 +#define Mips_REPLV_QB 2367 +#define Mips_REPLV_QB_MM 2368 +#define Mips_REPL_PH 2369 +#define Mips_REPL_PH_MM 2370 +#define Mips_REPL_QB 2371 +#define Mips_REPL_QB_MM 2372 +#define Mips_RINT_D 2373 +#define Mips_RINT_D_MMR6 2374 +#define Mips_RINT_S 2375 +#define Mips_RINT_S_MMR6 2376 +#define Mips_ROTR 2377 +#define Mips_ROTRV 2378 +#define Mips_ROTRV_MM 2379 +#define Mips_ROTR_MM 2380 +#define Mips_ROUND_L_D64 2381 +#define Mips_ROUND_L_D_MMR6 2382 +#define Mips_ROUND_L_S 2383 +#define Mips_ROUND_L_S_MMR6 2384 +#define Mips_ROUND_W_D32 2385 +#define Mips_ROUND_W_D64 2386 +#define Mips_ROUND_W_D_MMR6 2387 +#define Mips_ROUND_W_MM 2388 +#define Mips_ROUND_W_S 2389 +#define Mips_ROUND_W_S_MM 2390 +#define Mips_ROUND_W_S_MMR6 2391 +#define Mips_RSQRT_D32 2392 +#define Mips_RSQRT_D32_MM 2393 +#define Mips_RSQRT_D64 2394 +#define Mips_RSQRT_D64_MM 2395 +#define Mips_RSQRT_S 2396 +#define Mips_RSQRT_S_MM 2397 +#define Mips_Restore16 2398 +#define Mips_RestoreX16 2399 +#define Mips_SAA 2400 +#define Mips_SAAD 2401 +#define Mips_SAT_S_B 2402 +#define Mips_SAT_S_D 2403 +#define Mips_SAT_S_H 2404 +#define Mips_SAT_S_W 2405 +#define Mips_SAT_U_B 2406 +#define Mips_SAT_U_D 2407 +#define Mips_SAT_U_H 2408 +#define Mips_SAT_U_W 2409 +#define Mips_SB 2410 +#define Mips_SB16_MM 2411 +#define Mips_SB16_MMR6 2412 +#define Mips_SB64 2413 +#define Mips_SBE 2414 +#define Mips_SBE_MM 2415 +#define Mips_SB_MM 2416 +#define Mips_SB_MMR6 2417 +#define Mips_SC 2418 +#define Mips_SC64 2419 +#define Mips_SC64_R6 2420 +#define Mips_SCD 2421 +#define Mips_SCD_R6 2422 +#define Mips_SCE 2423 +#define Mips_SCE_MM 2424 +#define Mips_SC_MM 2425 +#define Mips_SC_MMR6 2426 +#define Mips_SC_R6 2427 +#define Mips_SD 2428 +#define Mips_SDBBP 2429 +#define Mips_SDBBP16_MM 2430 +#define Mips_SDBBP16_MMR6 2431 +#define Mips_SDBBP_MM 2432 +#define Mips_SDBBP_MMR6 2433 +#define Mips_SDBBP_R6 2434 +#define Mips_SDC1 2435 +#define Mips_SDC164 2436 +#define Mips_SDC1_D64_MMR6 2437 +#define Mips_SDC1_MM 2438 +#define Mips_SDC2 2439 +#define Mips_SDC2_MMR6 2440 +#define Mips_SDC2_R6 2441 +#define Mips_SDC3 2442 +#define Mips_SDIV 2443 +#define Mips_SDIV_MM 2444 +#define Mips_SDL 2445 +#define Mips_SDR 2446 +#define Mips_SDXC1 2447 +#define Mips_SDXC164 2448 +#define Mips_SEB 2449 +#define Mips_SEB64 2450 +#define Mips_SEB_MM 2451 +#define Mips_SEH 2452 +#define Mips_SEH64 2453 +#define Mips_SEH_MM 2454 +#define Mips_SELEQZ 2455 +#define Mips_SELEQZ64 2456 +#define Mips_SELEQZ_D 2457 +#define Mips_SELEQZ_D_MMR6 2458 +#define Mips_SELEQZ_MMR6 2459 +#define Mips_SELEQZ_S 2460 +#define Mips_SELEQZ_S_MMR6 2461 +#define Mips_SELNEZ 2462 +#define Mips_SELNEZ64 2463 +#define Mips_SELNEZ_D 2464 +#define Mips_SELNEZ_D_MMR6 2465 +#define Mips_SELNEZ_MMR6 2466 +#define Mips_SELNEZ_S 2467 +#define Mips_SELNEZ_S_MMR6 2468 +#define Mips_SEL_D 2469 +#define Mips_SEL_D_MMR6 2470 +#define Mips_SEL_S 2471 +#define Mips_SEL_S_MMR6 2472 +#define Mips_SEQ 2473 +#define Mips_SEQi 2474 +#define Mips_SH 2475 +#define Mips_SH16_MM 2476 +#define Mips_SH16_MMR6 2477 +#define Mips_SH64 2478 +#define Mips_SHE 2479 +#define Mips_SHE_MM 2480 +#define Mips_SHF_B 2481 +#define Mips_SHF_H 2482 +#define Mips_SHF_W 2483 +#define Mips_SHILO 2484 +#define Mips_SHILOV 2485 +#define Mips_SHILOV_MM 2486 +#define Mips_SHILO_MM 2487 +#define Mips_SHLLV_PH 2488 +#define Mips_SHLLV_PH_MM 2489 +#define Mips_SHLLV_QB 2490 +#define Mips_SHLLV_QB_MM 2491 +#define Mips_SHLLV_S_PH 2492 +#define Mips_SHLLV_S_PH_MM 2493 +#define Mips_SHLLV_S_W 2494 +#define Mips_SHLLV_S_W_MM 2495 +#define Mips_SHLL_PH 2496 +#define Mips_SHLL_PH_MM 2497 +#define Mips_SHLL_QB 2498 +#define Mips_SHLL_QB_MM 2499 +#define Mips_SHLL_S_PH 2500 +#define Mips_SHLL_S_PH_MM 2501 +#define Mips_SHLL_S_W 2502 +#define Mips_SHLL_S_W_MM 2503 +#define Mips_SHRAV_PH 2504 +#define Mips_SHRAV_PH_MM 2505 +#define Mips_SHRAV_QB 2506 +#define Mips_SHRAV_QB_MMR2 2507 +#define Mips_SHRAV_R_PH 2508 +#define Mips_SHRAV_R_PH_MM 2509 +#define Mips_SHRAV_R_QB 2510 +#define Mips_SHRAV_R_QB_MMR2 2511 +#define Mips_SHRAV_R_W 2512 +#define Mips_SHRAV_R_W_MM 2513 +#define Mips_SHRA_PH 2514 +#define Mips_SHRA_PH_MM 2515 +#define Mips_SHRA_QB 2516 +#define Mips_SHRA_QB_MMR2 2517 +#define Mips_SHRA_R_PH 2518 +#define Mips_SHRA_R_PH_MM 2519 +#define Mips_SHRA_R_QB 2520 +#define Mips_SHRA_R_QB_MMR2 2521 +#define Mips_SHRA_R_W 2522 +#define Mips_SHRA_R_W_MM 2523 +#define Mips_SHRLV_PH 2524 +#define Mips_SHRLV_PH_MMR2 2525 +#define Mips_SHRLV_QB 2526 +#define Mips_SHRLV_QB_MM 2527 +#define Mips_SHRL_PH 2528 +#define Mips_SHRL_PH_MMR2 2529 +#define Mips_SHRL_QB 2530 +#define Mips_SHRL_QB_MM 2531 +#define Mips_SH_MM 2532 +#define Mips_SH_MMR6 2533 +#define Mips_SIGRIE 2534 +#define Mips_SIGRIE_MMR6 2535 +#define Mips_SLDI_B 2536 +#define Mips_SLDI_D 2537 +#define Mips_SLDI_H 2538 +#define Mips_SLDI_W 2539 +#define Mips_SLD_B 2540 +#define Mips_SLD_D 2541 +#define Mips_SLD_H 2542 +#define Mips_SLD_W 2543 +#define Mips_SLL 2544 +#define Mips_SLL16_MM 2545 +#define Mips_SLL16_MMR6 2546 +#define Mips_SLL64_32 2547 +#define Mips_SLL64_64 2548 +#define Mips_SLLI_B 2549 +#define Mips_SLLI_D 2550 +#define Mips_SLLI_H 2551 +#define Mips_SLLI_W 2552 +#define Mips_SLLV 2553 +#define Mips_SLLV_MM 2554 +#define Mips_SLL_B 2555 +#define Mips_SLL_D 2556 +#define Mips_SLL_H 2557 +#define Mips_SLL_MM 2558 +#define Mips_SLL_MMR6 2559 +#define Mips_SLL_W 2560 +#define Mips_SLT 2561 +#define Mips_SLT64 2562 +#define Mips_SLT_MM 2563 +#define Mips_SLTi 2564 +#define Mips_SLTi64 2565 +#define Mips_SLTi_MM 2566 +#define Mips_SLTiu 2567 +#define Mips_SLTiu64 2568 +#define Mips_SLTiu_MM 2569 +#define Mips_SLTu 2570 +#define Mips_SLTu64 2571 +#define Mips_SLTu_MM 2572 +#define Mips_SNE 2573 +#define Mips_SNEi 2574 +#define Mips_SPLATI_B 2575 +#define Mips_SPLATI_D 2576 +#define Mips_SPLATI_H 2577 +#define Mips_SPLATI_W 2578 +#define Mips_SPLAT_B 2579 +#define Mips_SPLAT_D 2580 +#define Mips_SPLAT_H 2581 +#define Mips_SPLAT_W 2582 +#define Mips_SRA 2583 +#define Mips_SRAI_B 2584 +#define Mips_SRAI_D 2585 +#define Mips_SRAI_H 2586 +#define Mips_SRAI_W 2587 +#define Mips_SRARI_B 2588 +#define Mips_SRARI_D 2589 +#define Mips_SRARI_H 2590 +#define Mips_SRARI_W 2591 +#define Mips_SRAR_B 2592 +#define Mips_SRAR_D 2593 +#define Mips_SRAR_H 2594 +#define Mips_SRAR_W 2595 +#define Mips_SRAV 2596 +#define Mips_SRAV_MM 2597 +#define Mips_SRA_B 2598 +#define Mips_SRA_D 2599 +#define Mips_SRA_H 2600 +#define Mips_SRA_MM 2601 +#define Mips_SRA_W 2602 +#define Mips_SRL 2603 +#define Mips_SRL16_MM 2604 +#define Mips_SRL16_MMR6 2605 +#define Mips_SRLI_B 2606 +#define Mips_SRLI_D 2607 +#define Mips_SRLI_H 2608 +#define Mips_SRLI_W 2609 +#define Mips_SRLRI_B 2610 +#define Mips_SRLRI_D 2611 +#define Mips_SRLRI_H 2612 +#define Mips_SRLRI_W 2613 +#define Mips_SRLR_B 2614 +#define Mips_SRLR_D 2615 +#define Mips_SRLR_H 2616 +#define Mips_SRLR_W 2617 +#define Mips_SRLV 2618 +#define Mips_SRLV_MM 2619 +#define Mips_SRL_B 2620 +#define Mips_SRL_D 2621 +#define Mips_SRL_H 2622 +#define Mips_SRL_MM 2623 +#define Mips_SRL_W 2624 +#define Mips_SSNOP 2625 +#define Mips_SSNOP_MM 2626 +#define Mips_SSNOP_MMR6 2627 +#define Mips_ST_B 2628 +#define Mips_ST_D 2629 +#define Mips_ST_H 2630 +#define Mips_ST_W 2631 +#define Mips_SUB 2632 +#define Mips_SUBQH_PH 2633 +#define Mips_SUBQH_PH_MMR2 2634 +#define Mips_SUBQH_R_PH 2635 +#define Mips_SUBQH_R_PH_MMR2 2636 +#define Mips_SUBQH_R_W 2637 +#define Mips_SUBQH_R_W_MMR2 2638 +#define Mips_SUBQH_W 2639 +#define Mips_SUBQH_W_MMR2 2640 +#define Mips_SUBQ_PH 2641 +#define Mips_SUBQ_PH_MM 2642 +#define Mips_SUBQ_S_PH 2643 +#define Mips_SUBQ_S_PH_MM 2644 +#define Mips_SUBQ_S_W 2645 +#define Mips_SUBQ_S_W_MM 2646 +#define Mips_SUBSUS_U_B 2647 +#define Mips_SUBSUS_U_D 2648 +#define Mips_SUBSUS_U_H 2649 +#define Mips_SUBSUS_U_W 2650 +#define Mips_SUBSUU_S_B 2651 +#define Mips_SUBSUU_S_D 2652 +#define Mips_SUBSUU_S_H 2653 +#define Mips_SUBSUU_S_W 2654 +#define Mips_SUBS_S_B 2655 +#define Mips_SUBS_S_D 2656 +#define Mips_SUBS_S_H 2657 +#define Mips_SUBS_S_W 2658 +#define Mips_SUBS_U_B 2659 +#define Mips_SUBS_U_D 2660 +#define Mips_SUBS_U_H 2661 +#define Mips_SUBS_U_W 2662 +#define Mips_SUBU16_MM 2663 +#define Mips_SUBU16_MMR6 2664 +#define Mips_SUBUH_QB 2665 +#define Mips_SUBUH_QB_MMR2 2666 +#define Mips_SUBUH_R_QB 2667 +#define Mips_SUBUH_R_QB_MMR2 2668 +#define Mips_SUBU_MMR6 2669 +#define Mips_SUBU_PH 2670 +#define Mips_SUBU_PH_MMR2 2671 +#define Mips_SUBU_QB 2672 +#define Mips_SUBU_QB_MM 2673 +#define Mips_SUBU_S_PH 2674 +#define Mips_SUBU_S_PH_MMR2 2675 +#define Mips_SUBU_S_QB 2676 +#define Mips_SUBU_S_QB_MM 2677 +#define Mips_SUBVI_B 2678 +#define Mips_SUBVI_D 2679 +#define Mips_SUBVI_H 2680 +#define Mips_SUBVI_W 2681 +#define Mips_SUBV_B 2682 +#define Mips_SUBV_D 2683 +#define Mips_SUBV_H 2684 +#define Mips_SUBV_W 2685 +#define Mips_SUB_MM 2686 +#define Mips_SUB_MMR6 2687 +#define Mips_SUBu 2688 +#define Mips_SUBu_MM 2689 +#define Mips_SUXC1 2690 +#define Mips_SUXC164 2691 +#define Mips_SUXC1_MM 2692 +#define Mips_SW 2693 +#define Mips_SW16_MM 2694 +#define Mips_SW16_MMR6 2695 +#define Mips_SW64 2696 +#define Mips_SWC1 2697 +#define Mips_SWC1_MM 2698 +#define Mips_SWC2 2699 +#define Mips_SWC2_MMR6 2700 +#define Mips_SWC2_R6 2701 +#define Mips_SWC3 2702 +#define Mips_SWDSP 2703 +#define Mips_SWDSP_MM 2704 +#define Mips_SWE 2705 +#define Mips_SWE_MM 2706 +#define Mips_SWL 2707 +#define Mips_SWL64 2708 +#define Mips_SWLE 2709 +#define Mips_SWLE_MM 2710 +#define Mips_SWL_MM 2711 +#define Mips_SWM16_MM 2712 +#define Mips_SWM16_MMR6 2713 +#define Mips_SWM32_MM 2714 +#define Mips_SWP_MM 2715 +#define Mips_SWR 2716 +#define Mips_SWR64 2717 +#define Mips_SWRE 2718 +#define Mips_SWRE_MM 2719 +#define Mips_SWR_MM 2720 +#define Mips_SWSP_MM 2721 +#define Mips_SWSP_MMR6 2722 +#define Mips_SWXC1 2723 +#define Mips_SWXC1_MM 2724 +#define Mips_SW_MM 2725 +#define Mips_SW_MMR6 2726 +#define Mips_SYNC 2727 +#define Mips_SYNCI 2728 +#define Mips_SYNCI_MM 2729 +#define Mips_SYNCI_MMR6 2730 +#define Mips_SYNC_MM 2731 +#define Mips_SYNC_MMR6 2732 +#define Mips_SYSCALL 2733 +#define Mips_SYSCALL_MM 2734 +#define Mips_Save16 2735 +#define Mips_SaveX16 2736 +#define Mips_SbRxRyOffMemX16 2737 +#define Mips_SebRx16 2738 +#define Mips_SehRx16 2739 +#define Mips_ShRxRyOffMemX16 2740 +#define Mips_SllX16 2741 +#define Mips_SllvRxRy16 2742 +#define Mips_SltRxRy16 2743 +#define Mips_SltiRxImm16 2744 +#define Mips_SltiRxImmX16 2745 +#define Mips_SltiuRxImm16 2746 +#define Mips_SltiuRxImmX16 2747 +#define Mips_SltuRxRy16 2748 +#define Mips_SraX16 2749 +#define Mips_SravRxRy16 2750 +#define Mips_SrlX16 2751 +#define Mips_SrlvRxRy16 2752 +#define Mips_SubuRxRyRz16 2753 +#define Mips_SwRxRyOffMemX16 2754 +#define Mips_SwRxSpImmX16 2755 +#define Mips_TEQ 2756 +#define Mips_TEQI 2757 +#define Mips_TEQI_MM 2758 +#define Mips_TEQ_MM 2759 +#define Mips_TGE 2760 +#define Mips_TGEI 2761 +#define Mips_TGEIU 2762 +#define Mips_TGEIU_MM 2763 +#define Mips_TGEI_MM 2764 +#define Mips_TGEU 2765 +#define Mips_TGEU_MM 2766 +#define Mips_TGE_MM 2767 +#define Mips_TLBGINV 2768 +#define Mips_TLBGINVF 2769 +#define Mips_TLBGINVF_MM 2770 +#define Mips_TLBGINV_MM 2771 +#define Mips_TLBGP 2772 +#define Mips_TLBGP_MM 2773 +#define Mips_TLBGR 2774 +#define Mips_TLBGR_MM 2775 +#define Mips_TLBGWI 2776 +#define Mips_TLBGWI_MM 2777 +#define Mips_TLBGWR 2778 +#define Mips_TLBGWR_MM 2779 +#define Mips_TLBINV 2780 +#define Mips_TLBINVF 2781 +#define Mips_TLBINVF_MMR6 2782 +#define Mips_TLBINV_MMR6 2783 +#define Mips_TLBP 2784 +#define Mips_TLBP_MM 2785 +#define Mips_TLBR 2786 +#define Mips_TLBR_MM 2787 +#define Mips_TLBWI 2788 +#define Mips_TLBWI_MM 2789 +#define Mips_TLBWR 2790 +#define Mips_TLBWR_MM 2791 +#define Mips_TLT 2792 +#define Mips_TLTI 2793 +#define Mips_TLTIU_MM 2794 +#define Mips_TLTI_MM 2795 +#define Mips_TLTU 2796 +#define Mips_TLTU_MM 2797 +#define Mips_TLT_MM 2798 +#define Mips_TNE 2799 +#define Mips_TNEI 2800 +#define Mips_TNEI_MM 2801 +#define Mips_TNE_MM 2802 +#define Mips_TRUNC_L_D64 2803 +#define Mips_TRUNC_L_D_MMR6 2804 +#define Mips_TRUNC_L_S 2805 +#define Mips_TRUNC_L_S_MMR6 2806 +#define Mips_TRUNC_W_D32 2807 +#define Mips_TRUNC_W_D64 2808 +#define Mips_TRUNC_W_D_MMR6 2809 +#define Mips_TRUNC_W_MM 2810 +#define Mips_TRUNC_W_S 2811 +#define Mips_TRUNC_W_S_MM 2812 +#define Mips_TRUNC_W_S_MMR6 2813 +#define Mips_TTLTIU 2814 +#define Mips_UDIV 2815 +#define Mips_UDIV_MM 2816 +#define Mips_V3MULU 2817 +#define Mips_VMM0 2818 +#define Mips_VMULU 2819 +#define Mips_VSHF_B 2820 +#define Mips_VSHF_D 2821 +#define Mips_VSHF_H 2822 +#define Mips_VSHF_W 2823 +#define Mips_WAIT 2824 +#define Mips_WAIT_MM 2825 +#define Mips_WAIT_MMR6 2826 +#define Mips_WRDSP 2827 +#define Mips_WRDSP_MM 2828 +#define Mips_WRPGPR_MMR6 2829 +#define Mips_WSBH 2830 +#define Mips_WSBH_MM 2831 +#define Mips_WSBH_MMR6 2832 +#define Mips_XOR 2833 +#define Mips_XOR16_MM 2834 +#define Mips_XOR16_MMR6 2835 +#define Mips_XOR64 2836 +#define Mips_XORI_B 2837 +#define Mips_XORI_MMR6 2838 +#define Mips_XOR_MM 2839 +#define Mips_XOR_MMR6 2840 +#define Mips_XOR_V 2841 +#define Mips_XORi 2842 +#define Mips_XORi64 2843 +#define Mips_XORi_MM 2844 +#define Mips_XorRxRxRy16 2845 +#define Mips_YIELD 2846 +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_REGINFO_EXTRA +#undef GET_REGINFO_EXTRA + + // Subregister indices + + enum { + NoSubRegister, + Mips_sub_32, // 1 + Mips_sub_64, // 2 + Mips_sub_dsp16_19, // 3 + Mips_sub_dsp20, // 4 + Mips_sub_dsp21, // 5 + Mips_sub_dsp22, // 6 + Mips_sub_dsp23, // 7 + Mips_sub_hi, // 8 + Mips_sub_lo, // 9 + Mips_sub_hi_then_sub_32, // 10 + Mips_sub_32_sub_hi_then_sub_32, // 11 + Mips_NUM_TARGET_SUBREGS + }; +#endif // GET_REGINFO_EXTRA + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg MipsRegDiffLists[] = { + /* 0 */ 0, 0, + /* 2 */ 4, 1, 1, 1, 1, 0, + /* 8 */ 412, 65262, 1, 1, 1, 0, + /* 14 */ 20, 1, 0, + /* 17 */ 21, 1, 0, + /* 20 */ 22, 1, 0, + /* 23 */ 23, 1, 0, + /* 26 */ 24, 1, 0, + /* 29 */ 25, 1, 0, + /* 32 */ 26, 1, 0, + /* 35 */ 27, 1, 0, + /* 38 */ 28, 1, 0, + /* 41 */ 29, 1, 0, + /* 44 */ 30, 1, 0, + /* 47 */ 31, 1, 0, + /* 50 */ 32, 1, 0, + /* 53 */ 33, 1, 0, + /* 56 */ 34, 1, 0, + /* 59 */ 35, 1, 0, + /* 62 */ 65415, 1, 0, + /* 65 */ 65513, 1, 0, + /* 68 */ 3, 0, + /* 70 */ 4, 0, + /* 72 */ 6, 0, + /* 74 */ 11, 0, + /* 76 */ 12, 0, + /* 78 */ 22, 0, + /* 80 */ 23, 0, + /* 82 */ 29, 0, + /* 84 */ 30, 0, + /* 86 */ 65284, 72, 0, + /* 89 */ 65322, 72, 0, + /* 92 */ 38, 65298, 73, 0, + /* 96 */ 95, 0, + /* 98 */ 96, 0, + /* 100 */ 130, 0, + /* 102 */ 211, 0, + /* 104 */ 243, 0, + /* 106 */ 306, 0, + /* 108 */ 314, 0, + /* 110 */ 358, 0, + /* 112 */ 64983, 0, + /* 114 */ 65060, 0, + /* 116 */ 65124, 0, + /* 118 */ 65178, 0, + /* 120 */ 65181, 0, + /* 122 */ 65222, 0, + /* 124 */ 65230, 0, + /* 126 */ 65271, 0, + /* 128 */ 65293, 0, + /* 130 */ 37, 65406, 127, 65371, 65309, 0, + /* 136 */ 65325, 0, + /* 138 */ 65371, 0, + /* 140 */ 65386, 0, + /* 142 */ 65395, 0, + /* 144 */ 65396, 0, + /* 146 */ 65397, 0, + /* 148 */ 65398, 0, + /* 150 */ 65406, 0, + /* 152 */ 65415, 0, + /* 154 */ 65440, 0, + /* 156 */ 65441, 0, + /* 158 */ 165, 65498, 0, + /* 161 */ 65516, 258, 65498, 0, + /* 165 */ 65515, 259, 65498, 0, + /* 169 */ 65514, 260, 65498, 0, + /* 173 */ 65513, 261, 65498, 0, + /* 177 */ 65512, 262, 65498, 0, + /* 181 */ 65511, 263, 65498, 0, + /* 185 */ 65510, 264, 65498, 0, + /* 189 */ 65509, 265, 65498, 0, + /* 193 */ 65508, 266, 65498, 0, + /* 197 */ 65507, 267, 65498, 0, + /* 201 */ 65506, 268, 65498, 0, + /* 205 */ 65505, 269, 65498, 0, + /* 209 */ 65504, 270, 65498, 0, + /* 213 */ 65503, 271, 65498, 0, + /* 217 */ 65502, 272, 65498, 0, + /* 221 */ 65501, 273, 65498, 0, + /* 225 */ 65500, 274, 65498, 0, + /* 229 */ 65271, 395, 65499, 0, + /* 233 */ 65309, 392, 65502, 0, + /* 237 */ 65507, 0, + /* 239 */ 65510, 0, + /* 241 */ 65511, 0, + /* 243 */ 65512, 0, + /* 245 */ 65516, 0, + /* 247 */ 65521, 0, + /* 249 */ 65522, 0, + /* 251 */ 65535, 0, +}; + +static const uint16_t MipsSubRegIdxLists[] = { + /* 0 */ 1, 0, + /* 2 */ 3, 4, 5, 6, 7, 0, + /* 8 */ 2, 9, 8, 0, + /* 12 */ 9, 1, 8, 10, 11, 0, +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char MipsRegStrings[] = { + /* 0 */ "COP00\0" + /* 6 */ "COP010\0" + /* 13 */ "COP210\0" + /* 20 */ "COP310\0" + /* 27 */ "MSA10\0" + /* 33 */ "D10\0" + /* 37 */ "F10\0" + /* 41 */ "F_HI10\0" + /* 48 */ "FCR10\0" + /* 54 */ "HWR10\0" + /* 60 */ "W10\0" + /* 64 */ "COP020\0" + /* 71 */ "COP220\0" + /* 78 */ "COP320\0" + /* 85 */ "MSA20\0" + /* 91 */ "F20\0" + /* 95 */ "F_HI20\0" + /* 102 */ "COP20\0" + /* 108 */ "FCR20\0" + /* 114 */ "HWR20\0" + /* 120 */ "W20\0" + /* 124 */ "DSPOutFlag20\0" + /* 137 */ "COP030\0" + /* 144 */ "COP230\0" + /* 151 */ "COP330\0" + /* 158 */ "MSA30\0" + /* 164 */ "F30\0" + /* 168 */ "F_HI30\0" + /* 175 */ "COP30\0" + /* 181 */ "FCR30\0" + /* 187 */ "HWR30\0" + /* 193 */ "W30\0" + /* 197 */ "A0\0" + /* 200 */ "AC0\0" + /* 204 */ "FCC0\0" + /* 209 */ "D0\0" + /* 212 */ "F0\0" + /* 215 */ "F_HI0\0" + /* 221 */ "K0\0" + /* 224 */ "MPL0\0" + /* 229 */ "LO0\0" + /* 233 */ "P0\0" + /* 236 */ "FCR0\0" + /* 241 */ "HWR0\0" + /* 246 */ "S0\0" + /* 249 */ "T0\0" + /* 252 */ "V0\0" + /* 255 */ "W0\0" + /* 258 */ "COP01\0" + /* 264 */ "COP011\0" + /* 271 */ "COP211\0" + /* 278 */ "COP311\0" + /* 285 */ "MSA11\0" + /* 291 */ "D11\0" + /* 295 */ "F11\0" + /* 299 */ "F_HI11\0" + /* 306 */ "FCR11\0" + /* 312 */ "HWR11\0" + /* 318 */ "W11\0" + /* 322 */ "COP021\0" + /* 329 */ "COP221\0" + /* 336 */ "COP321\0" + /* 343 */ "MSA21\0" + /* 349 */ "F21\0" + /* 353 */ "F_HI21\0" + /* 360 */ "COP21\0" + /* 366 */ "FCR21\0" + /* 372 */ "HWR21\0" + /* 378 */ "W21\0" + /* 382 */ "DSPOutFlag21\0" + /* 395 */ "COP031\0" + /* 402 */ "COP231\0" + /* 409 */ "COP331\0" + /* 416 */ "MSA31\0" + /* 422 */ "F31\0" + /* 426 */ "F_HI31\0" + /* 433 */ "COP31\0" + /* 439 */ "FCR31\0" + /* 445 */ "HWR31\0" + /* 451 */ "W31\0" + /* 455 */ "A1\0" + /* 458 */ "AC1\0" + /* 462 */ "FCC1\0" + /* 467 */ "D1\0" + /* 470 */ "F1\0" + /* 473 */ "F_HI1\0" + /* 479 */ "K1\0" + /* 482 */ "MPL1\0" + /* 487 */ "LO1\0" + /* 491 */ "P1\0" + /* 494 */ "FCR1\0" + /* 499 */ "HWR1\0" + /* 504 */ "S1\0" + /* 507 */ "T1\0" + /* 510 */ "V1\0" + /* 513 */ "W1\0" + /* 516 */ "COP02\0" + /* 522 */ "COP012\0" + /* 529 */ "COP212\0" + /* 536 */ "COP312\0" + /* 543 */ "MSA12\0" + /* 549 */ "D12\0" + /* 553 */ "F12\0" + /* 557 */ "F_HI12\0" + /* 564 */ "FCR12\0" + /* 570 */ "HWR12\0" + /* 576 */ "W12\0" + /* 580 */ "COP022\0" + /* 587 */ "COP222\0" + /* 594 */ "COP322\0" + /* 601 */ "MSA22\0" + /* 607 */ "F22\0" + /* 611 */ "F_HI22\0" + /* 618 */ "COP22\0" + /* 624 */ "FCR22\0" + /* 630 */ "HWR22\0" + /* 636 */ "W22\0" + /* 640 */ "DSPOutFlag22\0" + /* 653 */ "COP32\0" + /* 659 */ "A2\0" + /* 662 */ "AC2\0" + /* 666 */ "FCC2\0" + /* 671 */ "D2\0" + /* 674 */ "F2\0" + /* 677 */ "F_HI2\0" + /* 683 */ "MPL2\0" + /* 688 */ "LO2\0" + /* 692 */ "P2\0" + /* 695 */ "FCR2\0" + /* 700 */ "HWR2\0" + /* 705 */ "S2\0" + /* 708 */ "T2\0" + /* 711 */ "W2\0" + /* 714 */ "COP03\0" + /* 720 */ "COP013\0" + /* 727 */ "COP213\0" + /* 734 */ "COP313\0" + /* 741 */ "MSA13\0" + /* 747 */ "D13\0" + /* 751 */ "F13\0" + /* 755 */ "F_HI13\0" + /* 762 */ "FCR13\0" + /* 768 */ "HWR13\0" + /* 774 */ "W13\0" + /* 778 */ "COP023\0" + /* 785 */ "COP223\0" + /* 792 */ "COP323\0" + /* 799 */ "MSA23\0" + /* 805 */ "F23\0" + /* 809 */ "F_HI23\0" + /* 816 */ "COP23\0" + /* 822 */ "FCR23\0" + /* 828 */ "HWR23\0" + /* 834 */ "W23\0" + /* 838 */ "DSPOutFlag23\0" + /* 851 */ "COP33\0" + /* 857 */ "A3\0" + /* 860 */ "AC3\0" + /* 864 */ "FCC3\0" + /* 869 */ "D3\0" + /* 872 */ "F3\0" + /* 875 */ "F_HI3\0" + /* 881 */ "LO3\0" + /* 885 */ "FCR3\0" + /* 890 */ "HWR3\0" + /* 895 */ "S3\0" + /* 898 */ "T3\0" + /* 901 */ "W3\0" + /* 904 */ "COP04\0" + /* 910 */ "COP014\0" + /* 917 */ "COP214\0" + /* 924 */ "COP314\0" + /* 931 */ "MSA14\0" + /* 937 */ "D14\0" + /* 941 */ "F14\0" + /* 945 */ "F_HI14\0" + /* 952 */ "FCR14\0" + /* 958 */ "HWR14\0" + /* 964 */ "W14\0" + /* 968 */ "COP024\0" + /* 975 */ "COP224\0" + /* 982 */ "COP324\0" + /* 989 */ "MSA24\0" + /* 995 */ "F24\0" + /* 999 */ "F_HI24\0" + /* 1006 */ "COP24\0" + /* 1012 */ "FCR24\0" + /* 1018 */ "HWR24\0" + /* 1024 */ "W24\0" + /* 1028 */ "COP34\0" + /* 1034 */ "D10_64\0" + /* 1041 */ "D20_64\0" + /* 1048 */ "D30_64\0" + /* 1055 */ "A0_64\0" + /* 1061 */ "AC0_64\0" + /* 1068 */ "D0_64\0" + /* 1074 */ "HI0_64\0" + /* 1081 */ "K0_64\0" + /* 1087 */ "LO0_64\0" + /* 1094 */ "S0_64\0" + /* 1100 */ "T0_64\0" + /* 1106 */ "V0_64\0" + /* 1112 */ "D11_64\0" + /* 1119 */ "D21_64\0" + /* 1126 */ "D31_64\0" + /* 1133 */ "A1_64\0" + /* 1139 */ "D1_64\0" + /* 1145 */ "K1_64\0" + /* 1151 */ "S1_64\0" + /* 1157 */ "T1_64\0" + /* 1163 */ "V1_64\0" + /* 1169 */ "D12_64\0" + /* 1176 */ "D22_64\0" + /* 1183 */ "A2_64\0" + /* 1189 */ "D2_64\0" + /* 1195 */ "S2_64\0" + /* 1201 */ "T2_64\0" + /* 1207 */ "D13_64\0" + /* 1214 */ "D23_64\0" + /* 1221 */ "A3_64\0" + /* 1227 */ "D3_64\0" + /* 1233 */ "S3_64\0" + /* 1239 */ "T3_64\0" + /* 1245 */ "D14_64\0" + /* 1252 */ "D24_64\0" + /* 1259 */ "D4_64\0" + /* 1265 */ "S4_64\0" + /* 1271 */ "T4_64\0" + /* 1277 */ "D15_64\0" + /* 1284 */ "D25_64\0" + /* 1291 */ "D5_64\0" + /* 1297 */ "S5_64\0" + /* 1303 */ "T5_64\0" + /* 1309 */ "D16_64\0" + /* 1316 */ "D26_64\0" + /* 1323 */ "D6_64\0" + /* 1329 */ "S6_64\0" + /* 1335 */ "T6_64\0" + /* 1341 */ "D17_64\0" + /* 1348 */ "D27_64\0" + /* 1355 */ "D7_64\0" + /* 1361 */ "S7_64\0" + /* 1367 */ "T7_64\0" + /* 1373 */ "D18_64\0" + /* 1380 */ "D28_64\0" + /* 1387 */ "D8_64\0" + /* 1393 */ "T8_64\0" + /* 1399 */ "D19_64\0" + /* 1406 */ "D29_64\0" + /* 1413 */ "D9_64\0" + /* 1419 */ "T9_64\0" + /* 1425 */ "RA_64\0" + /* 1431 */ "ZERO_64\0" + /* 1439 */ "FP_64\0" + /* 1445 */ "GP_64\0" + /* 1451 */ "SP_64\0" + /* 1457 */ "AT_64\0" + /* 1463 */ "FCC4\0" + /* 1468 */ "D4\0" + /* 1471 */ "F4\0" + /* 1474 */ "F_HI4\0" + /* 1480 */ "FCR4\0" + /* 1485 */ "HWR4\0" + /* 1490 */ "S4\0" + /* 1493 */ "T4\0" + /* 1496 */ "W4\0" + /* 1499 */ "COP05\0" + /* 1505 */ "COP015\0" + /* 1512 */ "COP215\0" + /* 1519 */ "COP315\0" + /* 1526 */ "MSA15\0" + /* 1532 */ "D15\0" + /* 1536 */ "F15\0" + /* 1540 */ "F_HI15\0" + /* 1547 */ "FCR15\0" + /* 1553 */ "HWR15\0" + /* 1559 */ "W15\0" + /* 1563 */ "COP025\0" + /* 1570 */ "COP225\0" + /* 1577 */ "COP325\0" + /* 1584 */ "MSA25\0" + /* 1590 */ "F25\0" + /* 1594 */ "F_HI25\0" + /* 1601 */ "COP25\0" + /* 1607 */ "FCR25\0" + /* 1613 */ "HWR25\0" + /* 1619 */ "W25\0" + /* 1623 */ "COP35\0" + /* 1629 */ "FCC5\0" + /* 1634 */ "D5\0" + /* 1637 */ "F5\0" + /* 1640 */ "F_HI5\0" + /* 1646 */ "FCR5\0" + /* 1651 */ "HWR5\0" + /* 1656 */ "S5\0" + /* 1659 */ "T5\0" + /* 1662 */ "W5\0" + /* 1665 */ "COP06\0" + /* 1671 */ "COP016\0" + /* 1678 */ "COP216\0" + /* 1685 */ "COP316\0" + /* 1692 */ "MSA16\0" + /* 1698 */ "F16\0" + /* 1702 */ "F_HI16\0" + /* 1709 */ "FCR16\0" + /* 1715 */ "HWR16\0" + /* 1721 */ "W16\0" + /* 1725 */ "COP026\0" + /* 1732 */ "COP226\0" + /* 1739 */ "COP326\0" + /* 1746 */ "MSA26\0" + /* 1752 */ "F26\0" + /* 1756 */ "F_HI26\0" + /* 1763 */ "COP26\0" + /* 1769 */ "FCR26\0" + /* 1775 */ "HWR26\0" + /* 1781 */ "W26\0" + /* 1785 */ "COP36\0" + /* 1791 */ "FCC6\0" + /* 1796 */ "D6\0" + /* 1799 */ "F6\0" + /* 1802 */ "F_HI6\0" + /* 1808 */ "FCR6\0" + /* 1813 */ "HWR6\0" + /* 1818 */ "S6\0" + /* 1821 */ "T6\0" + /* 1824 */ "W6\0" + /* 1827 */ "COP07\0" + /* 1833 */ "COP017\0" + /* 1840 */ "COP217\0" + /* 1847 */ "COP317\0" + /* 1854 */ "MSA17\0" + /* 1860 */ "F17\0" + /* 1864 */ "F_HI17\0" + /* 1871 */ "FCR17\0" + /* 1877 */ "HWR17\0" + /* 1883 */ "W17\0" + /* 1887 */ "COP027\0" + /* 1894 */ "COP227\0" + /* 1901 */ "COP327\0" + /* 1908 */ "MSA27\0" + /* 1914 */ "F27\0" + /* 1918 */ "F_HI27\0" + /* 1925 */ "COP27\0" + /* 1931 */ "FCR27\0" + /* 1937 */ "HWR27\0" + /* 1943 */ "W27\0" + /* 1947 */ "COP37\0" + /* 1953 */ "FCC7\0" + /* 1958 */ "D7\0" + /* 1961 */ "F7\0" + /* 1964 */ "F_HI7\0" + /* 1970 */ "FCR7\0" + /* 1975 */ "HWR7\0" + /* 1980 */ "S7\0" + /* 1983 */ "T7\0" + /* 1986 */ "W7\0" + /* 1989 */ "COP08\0" + /* 1995 */ "COP018\0" + /* 2002 */ "COP218\0" + /* 2009 */ "COP318\0" + /* 2016 */ "MSA18\0" + /* 2022 */ "F18\0" + /* 2026 */ "F_HI18\0" + /* 2033 */ "FCR18\0" + /* 2039 */ "HWR18\0" + /* 2045 */ "W18\0" + /* 2049 */ "COP028\0" + /* 2056 */ "COP228\0" + /* 2063 */ "COP328\0" + /* 2070 */ "MSA28\0" + /* 2076 */ "F28\0" + /* 2080 */ "F_HI28\0" + /* 2087 */ "COP28\0" + /* 2093 */ "FCR28\0" + /* 2099 */ "HWR28\0" + /* 2105 */ "W28\0" + /* 2109 */ "COP38\0" + /* 2115 */ "MSA8\0" + /* 2120 */ "D8\0" + /* 2123 */ "F8\0" + /* 2126 */ "F_HI8\0" + /* 2132 */ "FCR8\0" + /* 2137 */ "HWR8\0" + /* 2142 */ "T8\0" + /* 2145 */ "W8\0" + /* 2148 */ "COP09\0" + /* 2154 */ "COP019\0" + /* 2161 */ "COP219\0" + /* 2168 */ "COP319\0" + /* 2175 */ "MSA19\0" + /* 2181 */ "F19\0" + /* 2185 */ "F_HI19\0" + /* 2192 */ "FCR19\0" + /* 2198 */ "HWR19\0" + /* 2204 */ "W19\0" + /* 2208 */ "DSPOutFlag16_19\0" + /* 2224 */ "COP029\0" + /* 2231 */ "COP229\0" + /* 2238 */ "COP329\0" + /* 2245 */ "MSA29\0" + /* 2251 */ "F29\0" + /* 2255 */ "F_HI29\0" + /* 2262 */ "COP29\0" + /* 2268 */ "FCR29\0" + /* 2274 */ "HWR29\0" + /* 2280 */ "W29\0" + /* 2284 */ "COP39\0" + /* 2290 */ "MSA9\0" + /* 2295 */ "D9\0" + /* 2298 */ "F9\0" + /* 2301 */ "F_HI9\0" + /* 2307 */ "FCR9\0" + /* 2312 */ "HWR9\0" + /* 2317 */ "T9\0" + /* 2320 */ "W9\0" + /* 2323 */ "RA\0" + /* 2326 */ "PC\0" + /* 2329 */ "DSPEFI\0" + /* 2336 */ "ZERO\0" + /* 2341 */ "FP\0" + /* 2344 */ "GP\0" + /* 2347 */ "SP\0" + /* 2350 */ "MSAIR\0" + /* 2356 */ "MSACSR\0" + /* 2363 */ "AT\0" + /* 2366 */ "DSPCCond\0" + /* 2375 */ "MSASave\0" + /* 2383 */ "DSPOutFlag\0" + /* 2394 */ "MSAMap\0" + /* 2401 */ "MSAUnmap\0" + /* 2410 */ "DSPPos\0" + /* 2417 */ "MSAAccess\0" + /* 2427 */ "DSPSCount\0" + /* 2437 */ "MSARequest\0" + /* 2448 */ "MSAModify\0" + /* 2458 */ "DSPCarry\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterDesc MipsRegDesc[] = { + // Descriptors + {5, 0, 0, 0, 0, 0}, + {2363, 1, 82, 1, 4017, 451}, + {2366, 1, 1, 1, 4017, 434}, + {2458, 1, 1, 1, 4017, 541}, + {2329, 1, 1, 1, 4017, 117}, + {2383, 8, 1, 2, 32, 204}, + {2410, 1, 1, 1, 1089, 54}, + {2427, 1, 1, 1, 1089, 108}, + {2341, 1, 102, 1, 1089, 442}, + {2344, 1, 104, 1, 1089, 440}, + {2417, 1, 1, 1, 1089, 117}, + {2356, 1, 1, 1, 1089, 436}, + {2350, 1, 1, 1, 1089, 117}, + {2394, 1, 1, 1, 1089, 157}, + {2448, 1, 1, 1, 1089, 555}, + {2437, 1, 1, 1, 1089, 139}, + {2375, 1, 1, 1, 1089, 99}, + {2401, 1, 1, 1, 1089, 108}, + {2326, 1, 1, 1, 1089, 449}, + {2323, 1, 106, 1, 1089, 541}, + {2347, 1, 108, 1, 1089, 444}, + {2336, 1, 110, 1, 1089, 438}, + {197, 1, 110, 1, 1089, 117}, + {455, 1, 110, 1, 1089, 139}, + {659, 1, 110, 1, 1089, 1}, + {857, 1, 110, 1, 1089, 36}, + {200, 190, 110, 9, 1042, 119}, + {458, 190, 1, 9, 1042, 119}, + {662, 190, 1, 9, 1042, 104}, + {860, 190, 1, 9, 1042, 42}, + {1457, 237, 1, 0, 0, 498}, + {0, 1, 1, 1, 1153, 56}, + {258, 1, 1, 1, 1153, 1}, + {516, 1, 1, 1, 1153, 117}, + {714, 1, 1, 1, 1153, 117}, + {904, 1, 1, 1, 1153, 1}, + {1499, 1, 1, 1, 1153, 494}, + {1665, 1, 1, 1, 1153, 30}, + {1827, 1, 1, 1, 1153, 110}, + {1989, 1, 1, 1, 1153, 231}, + {2148, 1, 1, 1, 1153, 68}, + {102, 1, 1, 1, 1153, 225}, + {360, 1, 1, 1, 1153, 32}, + {618, 1, 1, 1, 1153, 1}, + {816, 1, 1, 1, 1153, 135}, + {1006, 1, 1, 1, 1153, 1}, + {1601, 1, 1, 1, 1153, 159}, + {1763, 1, 1, 1, 1153, 518}, + {1925, 1, 1, 1, 1153, 1}, + {2087, 1, 1, 1, 1153, 117}, + {2262, 1, 1, 1, 1153, 54}, + {175, 1, 1, 1, 1153, 1}, + {433, 1, 1, 1, 1153, 43}, + {653, 1, 1, 1, 1153, 513}, + {851, 1, 1, 1, 1153, 229}, + {1028, 1, 1, 1, 1153, 496}, + {1623, 1, 1, 1, 1153, 1}, + {1785, 1, 1, 1, 1153, 1}, + {1947, 1, 1, 1, 1153, 1}, + {2109, 1, 1, 1, 1153, 108}, + {2284, 1, 1, 1, 1153, 117}, + {6, 1, 1, 1, 1153, 117}, + {264, 1, 1, 1, 1153, 117}, + {522, 1, 1, 1, 1153, 137}, + {720, 1, 1, 1, 1153, 163}, + {910, 1, 1, 1, 1153, 167}, + {1505, 1, 1, 1, 1153, 171}, + {1671, 1, 1, 1, 1153, 175}, + {1833, 1, 1, 1, 1153, 179}, + {1995, 1, 1, 1, 1153, 183}, + {2154, 1, 1, 1, 1153, 187}, + {64, 1, 1, 1, 1153, 1}, + {322, 1, 1, 1, 1153, 1}, + {580, 1, 1, 1, 1153, 1}, + {778, 1, 1, 1, 1153, 1}, + {968, 1, 1, 1, 1153, 566}, + {1563, 1, 1, 1, 1153, 566}, + {1725, 1, 1, 1, 1153, 566}, + {1887, 1, 1, 1, 1153, 566}, + {2049, 1, 1, 1, 1153, 566}, + {2224, 1, 1, 1, 1153, 566}, + {137, 1, 1, 1, 1153, 566}, + {395, 1, 1, 1, 1153, 566}, + {13, 1, 1, 1, 1153, 566}, + {271, 1, 1, 1, 1153, 566}, + {529, 1, 1, 1, 1153, 566}, + {727, 1, 1, 1, 1153, 566}, + {917, 1, 1, 1, 1153, 145}, + {1512, 1, 1, 1, 1153, 165}, + {1678, 1, 1, 1, 1153, 169}, + {1840, 1, 1, 1, 1153, 173}, + {2002, 1, 1, 1, 1153, 177}, + {2161, 1, 1, 1, 1153, 181}, + {71, 1, 1, 1, 1153, 185}, + {329, 1, 1, 1, 1153, 189}, + {587, 1, 1, 1, 1153, 543}, + {785, 1, 1, 1, 1153, 562}, + {975, 1, 1, 1, 1153, 545}, + {1570, 1, 1, 1, 1153, 564}, + {1732, 1, 1, 1, 1153, 566}, + {1894, 1, 1, 1, 1153, 197}, + {2056, 1, 1, 1, 1153, 191}, + {2231, 1, 1, 1, 1153, 1}, + {144, 1, 1, 1, 1153, 509}, + {402, 1, 1, 1, 1153, 1}, + {20, 1, 1, 1, 1153, 117}, + {278, 1, 1, 1, 1153, 492}, + {536, 1, 1, 1, 1153, 202}, + {734, 1, 1, 1, 1153, 1}, + {924, 1, 1, 1, 1153, 117}, + {1519, 1, 1, 1, 1153, 502}, + {1685, 1, 1, 1, 1153, 56}, + {1847, 1, 1, 1, 1153, 108}, + {2009, 1, 1, 1, 1153, 117}, + {2168, 1, 1, 1, 1153, 24}, + {78, 1, 1, 1, 1153, 108}, + {336, 1, 1, 1, 1153, 500}, + {594, 1, 1, 1, 1153, 34}, + {792, 1, 1, 1, 1153, 504}, + {982, 1, 1, 1, 1153, 1}, + {1577, 1, 1, 1, 1153, 117}, + {1739, 1, 1, 1, 1153, 131}, + {1901, 1, 1, 1, 1153, 133}, + {2063, 1, 1, 1, 1153, 143}, + {2238, 1, 1, 1, 1153, 149}, + {151, 1, 1, 1, 1153, 155}, + {409, 1, 1, 1, 1153, 161}, + {209, 14, 1, 9, 994, 42}, + {467, 17, 1, 9, 994, 0}, + {671, 20, 1, 9, 994, 104}, + {869, 23, 1, 9, 994, 42}, + {1468, 26, 1, 9, 994, 65}, + {1634, 29, 1, 9, 994, 431}, + {1796, 32, 1, 9, 994, 0}, + {1958, 35, 1, 9, 994, 446}, + {2120, 38, 1, 9, 994, 119}, + {2295, 41, 1, 9, 994, 107}, + {33, 44, 1, 9, 994, 523}, + {291, 47, 1, 9, 994, 520}, + {549, 50, 1, 9, 994, 79}, + {747, 53, 1, 9, 994, 0}, + {937, 56, 1, 9, 994, 526}, + {1532, 59, 1, 9, 994, 53}, + {124, 1, 148, 1, 2369, 147}, + {382, 1, 146, 1, 2369, 38}, + {640, 1, 144, 1, 2369, 529}, + {838, 1, 142, 1, 2369, 1}, + {212, 1, 161, 1, 3985, 531}, + {470, 1, 165, 1, 3985, 56}, + {674, 1, 165, 1, 3985, 108}, + {872, 1, 169, 1, 3985, 117}, + {1471, 1, 169, 1, 3985, 117}, + {1637, 1, 173, 1, 3985, 108}, + {1799, 1, 173, 1, 3985, 425}, + {1961, 1, 177, 1, 3985, 421}, + {2123, 1, 177, 1, 3985, 213}, + {2298, 1, 181, 1, 3985, 215}, + {37, 1, 181, 1, 3985, 541}, + {295, 1, 185, 1, 3985, 114}, + {553, 1, 185, 1, 3985, 108}, + {751, 1, 189, 1, 3985, 217}, + {941, 1, 189, 1, 3985, 40}, + {1536, 1, 193, 1, 3985, 219}, + {1698, 1, 193, 1, 3985, 1}, + {1860, 1, 197, 1, 3985, 117}, + {2022, 1, 197, 1, 3985, 453}, + {2181, 1, 201, 1, 3985, 117}, + {91, 1, 201, 1, 3985, 1}, + {349, 1, 205, 1, 3985, 221}, + {607, 1, 205, 1, 3985, 99}, + {805, 1, 209, 1, 3985, 541}, + {995, 1, 209, 1, 3985, 1}, + {1590, 1, 213, 1, 3985, 112}, + {1752, 1, 213, 1, 3985, 1}, + {1914, 1, 217, 1, 3985, 117}, + {2076, 1, 217, 1, 3985, 227}, + {2251, 1, 221, 1, 3985, 223}, + {164, 1, 221, 1, 3985, 88}, + {422, 1, 225, 1, 3985, 474}, + {204, 1, 1, 1, 3985, 117}, + {462, 1, 1, 1, 3985, 24}, + {666, 1, 1, 1, 3985, 1}, + {864, 1, 1, 1, 3985, 476}, + {1463, 1, 1, 1, 3985, 1}, + {1629, 1, 1, 1, 3985, 1}, + {1791, 1, 1, 1, 3985, 1}, + {1953, 1, 1, 1, 3985, 423}, + {236, 1, 1, 1, 3985, 117}, + {494, 1, 1, 1, 3985, 99}, + {695, 1, 1, 1, 3985, 1}, + {885, 1, 1, 1, 3985, 54}, + {1480, 1, 1, 1, 3985, 480}, + {1646, 1, 1, 1, 3985, 84}, + {1808, 1, 1, 1, 3985, 566}, + {1970, 1, 1, 1, 3985, 197}, + {2132, 1, 1, 1, 3985, 195}, + {2307, 1, 1, 1, 3985, 193}, + {48, 1, 1, 1, 3985, 566}, + {306, 1, 1, 1, 3985, 566}, + {564, 1, 1, 1, 3985, 90}, + {762, 1, 1, 1, 3985, 487}, + {952, 1, 1, 1, 3985, 1}, + {1547, 1, 1, 1, 3985, 485}, + {1709, 1, 1, 1, 3985, 423}, + {1871, 1, 1, 1, 3985, 117}, + {2033, 1, 1, 1, 3985, 99}, + {2192, 1, 1, 1, 3985, 1}, + {108, 1, 1, 1, 3985, 54}, + {366, 1, 1, 1, 3985, 1}, + {624, 1, 1, 1, 3985, 38}, + {822, 1, 1, 1, 3985, 117}, + {1012, 1, 1, 1, 3985, 117}, + {1607, 1, 1, 1, 3985, 1}, + {1769, 1, 1, 1, 3985, 141}, + {1931, 1, 1, 1, 3985, 1}, + {2093, 1, 1, 1, 3985, 233}, + {2268, 1, 1, 1, 3985, 429}, + {181, 1, 1, 1, 3985, 117}, + {439, 1, 1, 1, 3985, 110}, + {1439, 136, 1, 0, 1184, 108}, + {215, 1, 158, 1, 3953, 394}, + {473, 1, 158, 1, 3953, 82}, + {677, 1, 158, 1, 3953, 1}, + {875, 1, 158, 1, 3953, 377}, + {1474, 1, 158, 1, 3953, 86}, + {1640, 1, 158, 1, 3953, 375}, + {1802, 1, 158, 1, 3953, 1}, + {1964, 1, 158, 1, 3953, 427}, + {2126, 1, 158, 1, 3953, 453}, + {2301, 1, 158, 1, 3953, 117}, + {41, 1, 158, 1, 3953, 117}, + {299, 1, 158, 1, 3953, 16}, + {557, 1, 158, 1, 3953, 54}, + {755, 1, 158, 1, 3953, 1}, + {945, 1, 158, 1, 3953, 392}, + {1540, 1, 158, 1, 3953, 388}, + {1702, 1, 158, 1, 3953, 390}, + {1864, 1, 158, 1, 3953, 400}, + {2026, 1, 158, 1, 3953, 379}, + {2185, 1, 158, 1, 3953, 398}, + {95, 1, 158, 1, 3953, 108}, + {353, 1, 158, 1, 3953, 117}, + {611, 1, 158, 1, 3953, 24}, + {809, 1, 158, 1, 3953, 108}, + {999, 1, 158, 1, 3953, 402}, + {1594, 1, 158, 1, 3953, 30}, + {1756, 1, 158, 1, 3953, 63}, + {1918, 1, 158, 1, 3953, 1}, + {2080, 1, 158, 1, 3953, 96}, + {2255, 1, 158, 1, 3953, 383}, + {168, 1, 158, 1, 3953, 1}, + {426, 1, 158, 1, 3953, 381}, + {1445, 128, 1, 0, 1216, 453}, + {217, 1, 233, 1, 1826, 117}, + {475, 1, 134, 1, 1826, 117}, + {679, 1, 134, 1, 1826, 16}, + {877, 1, 134, 1, 1826, 54}, + {241, 1, 1, 1, 3921, 404}, + {499, 1, 1, 1, 3921, 396}, + {700, 1, 1, 1, 3921, 1}, + {890, 1, 1, 1, 3921, 411}, + {1485, 1, 1, 1, 3921, 413}, + {1651, 1, 1, 1, 3921, 1}, + {1813, 1, 1, 1, 3921, 415}, + {1975, 1, 1, 1, 3921, 406}, + {2137, 1, 1, 1, 3921, 417}, + {2312, 1, 1, 1, 3921, 419}, + {54, 1, 1, 1, 3921, 36}, + {312, 1, 1, 1, 3921, 117}, + {570, 1, 1, 1, 3921, 1}, + {768, 1, 1, 1, 3921, 117}, + {958, 1, 1, 1, 3921, 153}, + {1553, 1, 1, 1, 3921, 151}, + {1715, 1, 1, 1, 3921, 61}, + {1877, 1, 1, 1, 3921, 241}, + {2039, 1, 1, 1, 3921, 243}, + {2198, 1, 1, 1, 3921, 117}, + {114, 1, 1, 1, 3921, 550}, + {372, 1, 1, 1, 3921, 1}, + {630, 1, 1, 1, 3921, 239}, + {828, 1, 1, 1, 3921, 247}, + {1018, 1, 1, 1, 3921, 245}, + {1613, 1, 1, 1, 3921, 108}, + {1775, 1, 1, 1, 3921, 249}, + {1937, 1, 1, 1, 3921, 251}, + {2099, 1, 1, 1, 3921, 253}, + {2274, 1, 1, 1, 3921, 255}, + {187, 1, 1, 1, 3921, 117}, + {445, 1, 1, 1, 3921, 24}, + {221, 1, 100, 1, 3921, 1}, + {479, 1, 100, 1, 3921, 257}, + {229, 1, 229, 1, 1794, 26}, + {487, 1, 126, 1, 1794, 259}, + {688, 1, 126, 1, 1794, 1}, + {881, 1, 126, 1, 1794, 261}, + {224, 1, 1, 1, 3889, 541}, + {482, 1, 1, 1, 3889, 108}, + {683, 1, 1, 1, 3889, 117}, + {2115, 1, 1, 1, 3889, 1}, + {2290, 1, 1, 1, 3889, 265}, + {27, 1, 1, 1, 3889, 269}, + {285, 1, 1, 1, 3889, 267}, + {543, 1, 1, 1, 3889, 277}, + {741, 1, 1, 1, 3889, 1}, + {931, 1, 1, 1, 3889, 263}, + {1526, 1, 1, 1, 3889, 423}, + {1692, 1, 1, 1, 3889, 117}, + {1854, 1, 1, 1, 3889, 117}, + {2016, 1, 1, 1, 3889, 99}, + {2175, 1, 1, 1, 3889, 54}, + {85, 1, 1, 1, 3889, 273}, + {343, 1, 1, 1, 3889, 94}, + {601, 1, 1, 1, 3889, 271}, + {799, 1, 1, 1, 3889, 1}, + {989, 1, 1, 1, 3889, 235}, + {1584, 1, 1, 1, 3889, 275}, + {1746, 1, 1, 1, 3889, 1}, + {1908, 1, 1, 1, 3889, 279}, + {2070, 1, 1, 1, 3889, 108}, + {2245, 1, 1, 1, 3889, 117}, + {158, 1, 1, 1, 3889, 560}, + {416, 1, 1, 1, 3889, 1}, + {233, 1, 1, 1, 3889, 1}, + {491, 1, 1, 1, 3889, 423}, + {692, 1, 1, 1, 3889, 99}, + {1425, 124, 1, 0, 1248, 16}, + {246, 1, 98, 1, 3857, 541}, + {504, 1, 98, 1, 3857, 283}, + {705, 1, 98, 1, 3857, 117}, + {895, 1, 98, 1, 3857, 117}, + {1490, 1, 98, 1, 3857, 281}, + {1656, 1, 98, 1, 3857, 1}, + {1818, 1, 98, 1, 3857, 117}, + {1980, 1, 98, 1, 3857, 108}, + {1451, 122, 1, 0, 1280, 1}, + {249, 1, 96, 1, 3825, 293}, + {507, 1, 96, 1, 3825, 291}, + {708, 1, 96, 1, 3825, 541}, + {898, 1, 96, 1, 3825, 295}, + {1493, 1, 96, 1, 3825, 48}, + {1659, 1, 96, 1, 3825, 297}, + {1821, 1, 96, 1, 3825, 299}, + {1983, 1, 96, 1, 3825, 28}, + {2142, 1, 96, 1, 3825, 1}, + {2317, 1, 96, 1, 3825, 306}, + {252, 1, 96, 1, 3825, 1}, + {510, 1, 96, 1, 3825, 301}, + {255, 92, 1, 8, 1425, 311}, + {513, 92, 1, 8, 1425, 45}, + {711, 92, 1, 8, 1425, 70}, + {901, 92, 1, 8, 1425, 314}, + {1496, 92, 1, 8, 1425, 317}, + {1662, 92, 1, 8, 1425, 9}, + {1824, 92, 1, 8, 1425, 21}, + {1986, 92, 1, 8, 1425, 98}, + {2145, 92, 1, 8, 1425, 320}, + {2320, 92, 1, 8, 1425, 50}, + {60, 92, 1, 8, 1425, 18}, + {318, 92, 1, 8, 1425, 3}, + {576, 92, 1, 8, 1425, 325}, + {774, 92, 1, 8, 1425, 0}, + {964, 92, 1, 8, 1425, 547}, + {1559, 92, 1, 8, 1425, 119}, + {1721, 92, 1, 8, 1425, 12}, + {1883, 92, 1, 8, 1425, 42}, + {2045, 92, 1, 8, 1425, 6}, + {2204, 92, 1, 8, 1425, 116}, + {120, 92, 1, 8, 1425, 552}, + {378, 92, 1, 8, 1425, 15}, + {636, 92, 1, 8, 1425, 557}, + {834, 92, 1, 8, 1425, 331}, + {1024, 92, 1, 8, 1425, 334}, + {1619, 92, 1, 8, 1425, 337}, + {1781, 92, 1, 8, 1425, 340}, + {1943, 92, 1, 8, 1425, 343}, + {2105, 92, 1, 8, 1425, 73}, + {2280, 92, 1, 8, 1425, 0}, + {193, 92, 1, 8, 1425, 349}, + {451, 92, 1, 8, 1425, 58}, + {1431, 118, 1, 0, 1921, 108}, + {1055, 118, 1, 0, 1921, 117}, + {1133, 118, 1, 0, 1921, 24}, + {1183, 118, 1, 0, 1921, 1}, + {1221, 118, 1, 0, 1921, 352}, + {1061, 130, 1, 12, 656, 354}, + {1068, 93, 159, 9, 1377, 285}, + {1139, 93, 159, 9, 1377, 199}, + {1189, 93, 159, 9, 1377, 408}, + {1227, 93, 159, 9, 1377, 288}, + {1259, 93, 159, 9, 1377, 489}, + {1291, 93, 159, 9, 1377, 385}, + {1323, 93, 159, 9, 1377, 515}, + {1355, 93, 159, 9, 1377, 328}, + {1387, 93, 159, 9, 1377, 308}, + {1413, 93, 159, 9, 1377, 210}, + {1034, 93, 159, 9, 1377, 346}, + {1112, 93, 159, 9, 1377, 482}, + {1169, 93, 159, 9, 1377, 76}, + {1207, 93, 159, 9, 1377, 0}, + {1245, 93, 159, 9, 1377, 357}, + {1277, 93, 159, 9, 1377, 58}, + {1309, 93, 159, 9, 1377, 303}, + {1341, 93, 159, 9, 1377, 360}, + {1373, 93, 159, 9, 1377, 363}, + {1399, 93, 159, 9, 1377, 366}, + {1041, 93, 159, 9, 1377, 369}, + {1119, 93, 159, 9, 1377, 372}, + {1176, 93, 159, 9, 1377, 122}, + {1214, 93, 159, 9, 1377, 455}, + {1252, 93, 159, 9, 1377, 538}, + {1284, 93, 159, 9, 1377, 506}, + {1316, 93, 159, 9, 1377, 128}, + {1348, 93, 159, 9, 1377, 535}, + {1380, 93, 159, 9, 1377, 119}, + {1406, 93, 159, 9, 1377, 125}, + {1048, 93, 159, 9, 1377, 101}, + {1126, 93, 159, 9, 1377, 98}, + {2208, 1, 116, 1, 1120, 466}, + {1074, 138, 235, 0, 1344, 458}, + {1081, 150, 1, 0, 2241, 460}, + {1145, 150, 1, 0, 2241, 460}, + {1087, 150, 231, 0, 1312, 462}, + {1094, 154, 1, 0, 2433, 462}, + {1151, 154, 1, 0, 2433, 468}, + {1195, 154, 1, 0, 2433, 54}, + {1233, 154, 1, 0, 2433, 464}, + {1265, 154, 1, 0, 2433, 92}, + {1297, 154, 1, 0, 2433, 117}, + {1329, 154, 1, 0, 2433, 1}, + {1361, 154, 1, 0, 2433, 533}, + {1100, 156, 1, 0, 2433, 511}, + {1157, 156, 1, 0, 2433, 478}, + {1201, 156, 1, 0, 2433, 237}, + {1239, 156, 1, 0, 2433, 323}, + {1271, 156, 1, 0, 2433, 16}, + {1303, 156, 1, 0, 2433, 470}, + {1335, 156, 1, 0, 2433, 541}, + {1367, 156, 1, 0, 2433, 99}, + {1393, 156, 1, 0, 2433, 117}, + {1419, 156, 1, 0, 2433, 110}, + {1106, 156, 1, 0, 2433, 1}, + {1163, 156, 1, 0, 2433, 472}, +}; + +// MSA128F16 Register Class... +static const MCPhysReg MSA128F16[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128F16 Bit set. +static const uint8_t MSA128F16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// CCR Register Class... +static const MCPhysReg CCR[] = { + Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, + Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, + Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, + Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, + Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, + Mips_FCR30, Mips_FCR31, +}; + +// CCR Bit set. +static const uint8_t CCRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// COP0 Register Class... +static const MCPhysReg COP0[] = { + Mips_COP00, Mips_COP01, Mips_COP02, Mips_COP03, Mips_COP04, + Mips_COP05, Mips_COP06, Mips_COP07, Mips_COP08, Mips_COP09, + Mips_COP010, Mips_COP011, Mips_COP012, Mips_COP013, Mips_COP014, + Mips_COP015, Mips_COP016, Mips_COP017, Mips_COP018, Mips_COP019, + Mips_COP020, Mips_COP021, Mips_COP022, Mips_COP023, Mips_COP024, + Mips_COP025, Mips_COP026, Mips_COP027, Mips_COP028, Mips_COP029, + Mips_COP030, Mips_COP031, +}; + +// COP0 Bit set. +static const uint8_t COP0Bits[] = { + 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07, +}; + +// COP2 Register Class... +static const MCPhysReg COP2[] = { + Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, + Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, + Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, + Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, + Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, + Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, + Mips_COP230, Mips_COP231, +}; + +// COP2 Bit set. +static const uint8_t COP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, + 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, +}; + +// COP3 Register Class... +static const MCPhysReg COP3[] = { + Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, + Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, + Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, + Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, + Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, + Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, + Mips_COP330, Mips_COP331, +}; + +// COP3 Bit set. +static const uint8_t COP3Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, +}; + +// DSPR Register Class... +static const MCPhysReg DSPR[] = { + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, + Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, + Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, +}; + +// DSPR Bit set. +static const uint8_t DSPRBits[] = { + 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, +}; + +// FGR32 Register Class... +static const MCPhysReg FGR32[] = { + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, + Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, + Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, + Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, + Mips_F28, Mips_F29, Mips_F30, Mips_F31, +}; + +// FGR32 Bit set. +static const uint8_t FGR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// FGRCC Register Class... +static const MCPhysReg FGRCC[] = { + Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, + Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, + Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, + Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, + Mips_F28, Mips_F29, Mips_F30, Mips_F31, +}; + +// FGRCC Bit set. +static const uint8_t FGRCCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// GPR32 Register Class... +static const MCPhysReg GPR32[] = { + Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, + Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, + Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, + Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, +}; + +// GPR32 Bit set. +static const uint8_t GPR32Bits[] = { + 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, +}; + +// HWRegs Register Class... +static const MCPhysReg HWRegs[] = { + Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, + Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, + Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, + Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, + Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, + Mips_HWR30, Mips_HWR31, +}; + +// HWRegs Bit set. +static const uint8_t HWRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// MSACtrl Register Class... +static const MCPhysReg MSACtrl[] = { + Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, + Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, Mips_MSA8, Mips_MSA9, + Mips_MSA10, Mips_MSA11, Mips_MSA12, Mips_MSA13, Mips_MSA14, + Mips_MSA15, Mips_MSA16, Mips_MSA17, Mips_MSA18, Mips_MSA19, + Mips_MSA20, Mips_MSA21, Mips_MSA22, Mips_MSA23, Mips_MSA24, + Mips_MSA25, Mips_MSA26, Mips_MSA27, Mips_MSA28, Mips_MSA29, + Mips_MSA30, Mips_MSA31, +}; + +// MSACtrl Bit set. +static const uint8_t MSACtrlBits[] = { + 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03, +}; + +// GPR32NONZERO Register Class... +static const MCPhysReg GPR32NONZERO[] = { + Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, + Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, + Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, + Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, +}; + +// GPR32NONZERO Bit set. +static const uint8_t GPR32NONZEROBits[] = { + 0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, +}; + +// CPU16RegsPlusSP Register Class... +static const MCPhysReg CPU16RegsPlusSP[] = { + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, + Mips_A3, Mips_S0, Mips_S1, Mips_SP, +}; + +// CPU16RegsPlusSP Bit set. +static const uint8_t CPU16RegsPlusSPBits[] = { + 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, +}; + +// CPU16Regs Register Class... +static const MCPhysReg CPU16Regs[] = { + Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, +}; + +// CPU16Regs Bit set. +static const uint8_t CPU16RegsBits[] = { + 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, +}; + +// FCC Register Class... +static const MCPhysReg FCC[] = { + Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, + Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, +}; + +// FCC Bit set. +static const uint8_t FCCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, +}; + +// GPRMM16 Register Class... +static const MCPhysReg GPRMM16[] = { + Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, +}; + +// GPRMM16 Bit set. +static const uint8_t GPRMM16Bits[] = { + 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, +}; + +// GPRMM16MoveP Register Class... +static const MCPhysReg GPRMM16MoveP[] = { + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, +}; + +// GPRMM16MoveP Bit set. +static const uint8_t GPRMM16MovePBits[] = { + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, +}; + +// GPRMM16Zero Register Class... +static const MCPhysReg GPRMM16Zero[] = { + Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, +}; + +// GPRMM16Zero Bit set. +static const uint8_t GPRMM16ZeroBits[] = { + 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, +}; + +// CPU16Regs_and_GPRMM16Zero Register Class... +static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { + Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, +}; + +// CPU16Regs_and_GPRMM16Zero Bit set. +static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, +}; + +// GPR32NONZERO_and_GPRMM16MoveP Register Class... +static const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = { + Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, +}; + +// GPR32NONZERO_and_GPRMM16MoveP Bit set. +static const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, +}; + +// GPRMM16MovePPairSecond Register Class... +static const MCPhysReg GPRMM16MovePPairSecond[] = { + Mips_A1, Mips_A2, Mips_A3, Mips_S5, Mips_S6, +}; + +// GPRMM16MovePPairSecond Bit set. +static const uint8_t GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, +}; + +// CPU16Regs_and_GPRMM16MoveP Register Class... +static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { + Mips_S1, + Mips_V0, + Mips_V1, + Mips_S0, +}; + +// CPU16Regs_and_GPRMM16MoveP Bit set. +static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, +}; + +// GPRMM16MoveP_and_GPRMM16Zero Register Class... +static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { + Mips_ZERO, + Mips_S1, + Mips_V0, + Mips_V1, +}; + +// GPRMM16MoveP_and_GPRMM16Zero Bit set. +static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, +}; + +// HI32DSP Register Class... +static const MCPhysReg HI32DSP[] = { + Mips_HI0, + Mips_HI1, + Mips_HI2, + Mips_HI3, +}; + +// HI32DSP Bit set. +static const uint8_t HI32DSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, +}; + +// LO32DSP Register Class... +static const MCPhysReg LO32DSP[] = { + Mips_LO0, + Mips_LO1, + Mips_LO2, + Mips_LO3, +}; + +// LO32DSP Bit set. +static const uint8_t LO32DSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, +}; + +// CPU16Regs_and_GPRMM16MovePPairSecond Register Class... +static const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = { + Mips_A1, + Mips_A2, + Mips_A3, +}; + +// CPU16Regs_and_GPRMM16MovePPairSecond Bit set. +static const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { + 0x00, + 0x00, + 0x80, + 0x03, +}; + +// GPRMM16MovePPairFirst Register Class... +static const MCPhysReg GPRMM16MovePPairFirst[] = { + Mips_A0, + Mips_A1, + Mips_A2, +}; + +// GPRMM16MovePPairFirst Bit set. +static const uint8_t GPRMM16MovePPairFirstBits[] = { + 0x00, + 0x00, + 0xc0, + 0x01, +}; + +// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... +static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { + Mips_S1, + Mips_V0, + Mips_V1, +}; + +// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. +static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, +}; + +// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class... +static const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { + Mips_A1, + Mips_A2, +}; + +// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set. +static const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = { + 0x00, + 0x00, + 0x80, + 0x01, +}; + +// CPURAReg Register Class... +static const MCPhysReg CPURAReg[] = { + Mips_RA, +}; + +// CPURAReg Bit set. +static const uint8_t CPURARegBits[] = { + 0x00, + 0x00, + 0x08, +}; + +// CPUSPReg Register Class... +static const MCPhysReg CPUSPReg[] = { + Mips_SP, +}; + +// CPUSPReg Bit set. +static const uint8_t CPUSPRegBits[] = { + 0x00, + 0x00, + 0x10, +}; + +// DSPCC Register Class... +static const MCPhysReg DSPCC[] = { + Mips_DSPCCond, +}; + +// DSPCC Bit set. +static const uint8_t DSPCCBits[] = { + 0x04, +}; + +// GP32 Register Class... +static const MCPhysReg GP32[] = { + Mips_GP, +}; + +// GP32 Bit set. +static const uint8_t GP32Bits[] = { + 0x00, + 0x02, +}; + +// GPR32ZERO Register Class... +static const MCPhysReg GPR32ZERO[] = { + Mips_ZERO, +}; + +// GPR32ZERO Bit set. +static const uint8_t GPR32ZEROBits[] = { + 0x00, + 0x00, + 0x20, +}; + +// HI32 Register Class... +static const MCPhysReg HI32[] = { + Mips_HI0, +}; + +// HI32 Bit set. +static const uint8_t HI32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// LO32 Register Class... +static const MCPhysReg LO32[] = { + Mips_LO0, +}; + +// LO32 Bit set. +static const uint8_t LO32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, +}; + +// SP32 Register Class... +static const MCPhysReg SP32[] = { + Mips_SP, +}; + +// SP32 Bit set. +static const uint8_t SP32Bits[] = { + 0x00, + 0x00, + 0x10, +}; + +// FGR64 Register Class... +static const MCPhysReg FGR64[] = { + Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, + Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, + Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, + Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, + Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, + Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, + Mips_D30_64, Mips_D31_64, +}; + +// FGR64 Bit set. +static const uint8_t FGR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// GPR64 Register Class... +static const MCPhysReg GPR64[] = { + Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, + Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, + Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, + Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, + Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, + Mips_FP_64, Mips_RA_64, +}; + +// GPR64 Bit set. +static const uint8_t GPR64Bits[] = { + 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, + 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, +}; + +// GPR64_with_sub_32_in_GPR32NONZERO Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = { + Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, + Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, + Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, + Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, + Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, + Mips_RA_64, +}; + +// GPR64_with_sub_32_in_GPR32NONZERO Bit set. +static const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = { + 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, +}; + +// AFGR64 Register Class... +static const MCPhysReg AFGR64[] = { + Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, + Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, + Mips_D12, Mips_D13, Mips_D14, Mips_D15, +}; + +// AFGR64 Bit set. +static const uint8_t AFGR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, +}; + +// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, + Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, +}; + +// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. +static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_CPU16Regs Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, + Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, +}; + +// GPR64_with_sub_32_in_CPU16Regs Bit set. +static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, + Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPRMM16Zero Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { + Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, + Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, +}; + +// GPR64_with_sub_32_in_GPRMM16Zero Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { + Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, + Mips_A2_64, Mips_A3_64, Mips_S1_64, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. +static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = { + Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, + Mips_S2_64, Mips_S3_64, Mips_S4_64, +}; + +// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set. +static const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = { + Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S5_64, Mips_S6_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, +}; + +// ACC64DSP Register Class... +static const MCPhysReg ACC64DSP[] = { + Mips_AC0, + Mips_AC1, + Mips_AC2, + Mips_AC3, +}; + +// ACC64DSP Bit set. +static const uint8_t ACC64DSPBits[] = { + 0x00, + 0x00, + 0x00, + 0x3c, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { + Mips_V0_64, + Mips_V1_64, + Mips_S0_64, + Mips_S1_64, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. +static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { + Mips_ZERO_64, + Mips_V0_64, + Mips_V1_64, + Mips_S1_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class... +static const MCPhysReg + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = { + Mips_A1_64, + Mips_A2_64, + Mips_A3_64, +}; + +// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set. +static const uint8_t + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = { + Mips_A0_64, + Mips_A1_64, + Mips_A2_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set. +static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register +// Class... +static const MCPhysReg + GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { + Mips_V0_64, + Mips_V1_64, + Mips_S1_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. +static const uint8_t + GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, +}; + +// OCTEON_MPL Register Class... +static const MCPhysReg OCTEON_MPL[] = { + Mips_MPL0, + Mips_MPL1, + Mips_MPL2, +}; + +// OCTEON_MPL Bit set. +static const uint8_t OCTEON_MPLBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, +}; + +// OCTEON_P Register Class... +static const MCPhysReg OCTEON_P[] = { + Mips_P0, + Mips_P1, + Mips_P2, +}; + +// OCTEON_P Bit set. +static const uint8_t OCTEON_PBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond +// Register Class... +static const MCPhysReg + GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { + Mips_A1_64, + Mips_A2_64, +}; + +// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit +// set. +static const uint8_t + GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits + [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, +}; + +// ACC64 Register Class... +static const MCPhysReg ACC64[] = { + Mips_AC0, +}; + +// ACC64 Bit set. +static const uint8_t ACC64Bits[] = { + 0x00, + 0x00, + 0x00, + 0x04, +}; + +// GP64 Register Class... +static const MCPhysReg GP64[] = { + Mips_GP_64, +}; + +// GP64 Bit set. +static const uint8_t GP64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, +}; + +// GPR64_with_sub_32_in_CPURAReg Register Class... +static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { + Mips_RA_64, +}; + +// GPR64_with_sub_32_in_CPURAReg Bit set. +static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// GPR64_with_sub_32_in_GPR32ZERO Register Class... +static const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = { + Mips_ZERO_64, +}; + +// GPR64_with_sub_32_in_GPR32ZERO Bit set. +static const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, +}; + +// HI64 Register Class... +static const MCPhysReg HI64[] = { + Mips_HI0_64, +}; + +// HI64 Bit set. +static const uint8_t HI64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, +}; + +// LO64 Register Class... +static const MCPhysReg LO64[] = { + Mips_LO0_64, +}; + +// LO64 Bit set. +static const uint8_t LO64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// SP64 Register Class... +static const MCPhysReg SP64[] = { + Mips_SP_64, +}; + +// SP64 Bit set. +static const uint8_t SP64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, +}; + +// MSA128B Register Class... +static const MCPhysReg MSA128B[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128B Bit set. +static const uint8_t MSA128BBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// MSA128D Register Class... +static const MCPhysReg MSA128D[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128D Bit set. +static const uint8_t MSA128DBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// MSA128H Register Class... +static const MCPhysReg MSA128H[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128H Bit set. +static const uint8_t MSA128HBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// MSA128W Register Class... +static const MCPhysReg MSA128W[] = { + Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, + Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, + Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, + Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, + Mips_W28, Mips_W29, Mips_W30, Mips_W31, +}; + +// MSA128W Bit set. +static const uint8_t MSA128WBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// MSA128WEvens Register Class... +static const MCPhysReg MSA128WEvens[] = { + Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, + Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, + Mips_W24, Mips_W26, Mips_W28, Mips_W30, +}; + +// MSA128WEvens Bit set. +static const uint8_t MSA128WEvensBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, +}; + +// ACC128 Register Class... +static const MCPhysReg ACC128[] = { + Mips_AC0_64, +}; + +// ACC128 Bit set. +static const uint8_t ACC128Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, +}; + +// end of register classes misc + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char MipsRegClassStrings[] = { + /* 0 */ "COP0\0" + /* 5 */ "HI32\0" + /* 10 */ "LO32\0" + /* 15 */ "GP32\0" + /* 20 */ "SP32\0" + /* 25 */ "FGR32\0" + /* 31 */ "GPR32\0" + /* 37 */ "COP2\0" + /* 42 */ "COP3\0" + /* 47 */ "ACC64\0" + /* 53 */ "HI64\0" + /* 58 */ "LO64\0" + /* 63 */ "GP64\0" + /* 68 */ "SP64\0" + /* 73 */ "AFGR64\0" + /* 80 */ "GPR64\0" + /* 86 */ "MSA128F16\0" + /* 96 */ "GPRMM16\0" + /* 104 */ "ACC128\0" + /* 111 */ "MSA128B\0" + /* 119 */ "FCC\0" + /* 123 */ "DSPCC\0" + /* 129 */ "FGRCC\0" + /* 135 */ "MSA128D\0" + /* 143 */ "MSA128H\0" + /* 151 */ "OCTEON_MPL\0" + /* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\0" + /* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\0" + /* 227 */ "HI32DSP\0" + /* 235 */ "LO32DSP\0" + /* 243 */ "ACC64DSP\0" + /* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\0" + /* 289 */ "OCTEON_P\0" + /* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\0" + /* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\0" + /* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\0" + /* 431 */ "CCR\0" + /* 435 */ "DSPR\0" + /* 440 */ "MSA128W\0" + /* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_" + "GPRMM16MovePPairSecond\0" + /* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_" + "GPRMM16MovePPairSecond\0" + /* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\0" + /* 620 */ "GPR64_with_sub_32_in_CPURAReg\0" + /* 650 */ "CPUSPReg\0" + /* 659 */ "MSACtrl\0" + /* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\0" + /* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_" + "GPRMM16Zero\0" + /* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\0" + /* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\0" + /* 861 */ "GPR64_with_sub_32_in_CPU16Regs\0" + /* 892 */ "HWRegs\0" + /* 899 */ "MSA128WEvens\0" + /* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterClass MipsMCRegisterClasses[] = { + {MSA128F16, MSA128F16Bits, sizeof(MSA128F16Bits)}, + {CCR, CCRBits, sizeof(CCRBits)}, + {COP0, COP0Bits, sizeof(COP0Bits)}, + {COP2, COP2Bits, sizeof(COP2Bits)}, + {COP3, COP3Bits, sizeof(COP3Bits)}, + {DSPR, DSPRBits, sizeof(DSPRBits)}, + {FGR32, FGR32Bits, sizeof(FGR32Bits)}, + {FGRCC, FGRCCBits, sizeof(FGRCCBits)}, + {GPR32, GPR32Bits, sizeof(GPR32Bits)}, + {HWRegs, HWRegsBits, sizeof(HWRegsBits)}, + {MSACtrl, MSACtrlBits, sizeof(MSACtrlBits)}, + {GPR32NONZERO, GPR32NONZEROBits, sizeof(GPR32NONZEROBits)}, + {CPU16RegsPlusSP, CPU16RegsPlusSPBits, sizeof(CPU16RegsPlusSPBits)}, + {CPU16Regs, CPU16RegsBits, sizeof(CPU16RegsBits)}, + {FCC, FCCBits, sizeof(FCCBits)}, + {GPRMM16, GPRMM16Bits, sizeof(GPRMM16Bits)}, + {GPRMM16MoveP, GPRMM16MovePBits, sizeof(GPRMM16MovePBits)}, + {GPRMM16Zero, GPRMM16ZeroBits, sizeof(GPRMM16ZeroBits)}, + {CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, + sizeof(CPU16Regs_and_GPRMM16ZeroBits)}, + {GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, + sizeof(GPR32NONZERO_and_GPRMM16MovePBits)}, + {GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, + sizeof(GPRMM16MovePPairSecondBits)}, + {CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, + sizeof(CPU16Regs_and_GPRMM16MovePBits)}, + {GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, + sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits)}, + {HI32DSP, HI32DSPBits, sizeof(HI32DSPBits)}, + {LO32DSP, LO32DSPBits, sizeof(LO32DSPBits)}, + {CPU16Regs_and_GPRMM16MovePPairSecond, + CPU16Regs_and_GPRMM16MovePPairSecondBits, + sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits)}, + {GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, + sizeof(GPRMM16MovePPairFirstBits)}, + {GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, + GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, + sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits)}, + {GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, + GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, + sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits)}, + {CPURAReg, CPURARegBits, sizeof(CPURARegBits)}, + {CPUSPReg, CPUSPRegBits, sizeof(CPUSPRegBits)}, + {DSPCC, DSPCCBits, sizeof(DSPCCBits)}, + {GP32, GP32Bits, sizeof(GP32Bits)}, + {GPR32ZERO, GPR32ZEROBits, sizeof(GPR32ZEROBits)}, + {HI32, HI32Bits, sizeof(HI32Bits)}, + {LO32, LO32Bits, sizeof(LO32Bits)}, + {SP32, SP32Bits, sizeof(SP32Bits)}, + {FGR64, FGR64Bits, sizeof(FGR64Bits)}, + {GPR64, GPR64Bits, sizeof(GPR64Bits)}, + {GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, + sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits)}, + {AFGR64, AFGR64Bits, sizeof(AFGR64Bits)}, + {GPR64_with_sub_32_in_CPU16RegsPlusSP, + GPR64_with_sub_32_in_CPU16RegsPlusSPBits, + sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits)}, + {GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, + sizeof(GPR64_with_sub_32_in_CPU16RegsBits)}, + {GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, + sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits)}, + {GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, + sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits)}, + {GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, + sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits)}, + {GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, + GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, + sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits)}, + {GPR64_with_sub_32_in_GPRMM16MovePPairSecond, + GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, + sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits)}, + {ACC64DSP, ACC64DSPBits, sizeof(ACC64DSPBits)}, + {GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, + sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits)}, + {GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, + GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, + sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits)}, + {GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, + GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, + sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits)}, + {GPR64_with_sub_32_in_GPRMM16MovePPairFirst, + GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, + sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits)}, + {GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, + GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, + sizeof( + GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits)}, + {OCTEON_MPL, OCTEON_MPLBits, sizeof(OCTEON_MPLBits)}, + {OCTEON_P, OCTEON_PBits, sizeof(OCTEON_PBits)}, + {GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, + GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, + sizeof( + GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits)}, + {ACC64, ACC64Bits, sizeof(ACC64Bits)}, + {GP64, GP64Bits, sizeof(GP64Bits)}, + {GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, + sizeof(GPR64_with_sub_32_in_CPURARegBits)}, + {GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, + sizeof(GPR64_with_sub_32_in_GPR32ZEROBits)}, + {HI64, HI64Bits, sizeof(HI64Bits)}, + {LO64, LO64Bits, sizeof(LO64Bits)}, + {SP64, SP64Bits, sizeof(SP64Bits)}, + {MSA128B, MSA128BBits, sizeof(MSA128BBits)}, + {MSA128D, MSA128DBits, sizeof(MSA128DBits)}, + {MSA128H, MSA128HBits, sizeof(MSA128HBits)}, + {MSA128W, MSA128WBits, sizeof(MSA128WBits)}, + {MSA128WEvens, MSA128WEvensBits, sizeof(MSA128WEvensBits)}, + {ACC128, ACC128Bits, sizeof(ACC128Bits)}, +}; + +#endif // GET_REGINFO_MC_DESC + +#ifdef GET_ASM_WRITER +#undef GET_ASM_WRITER + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +typedef struct MCMnemonic { + const char *first; + uint64_t second; +} MCMnemonic; + +static MCMnemonic createMnemonic(const char *first, uint64_t second) { + MCMnemonic mnemonic; + mnemonic.first = first; + mnemonic.second = second; + return mnemonic; +} + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +MCMnemonic Mips_getMnemonic(const MCInst *MI) { + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "dmfc0\t\0" + /* 7 */ "dmfgc0\t\0" + /* 15 */ "mfhgc0\t\0" + /* 23 */ "mthgc0\t\0" + /* 31 */ "dmtgc0\t\0" + /* 39 */ "mfhc0\t\0" + /* 46 */ "mthc0\t\0" + /* 53 */ "dmtc0\t\0" + /* 60 */ "vmm0\t\0" + /* 66 */ "mtm0\t\0" + /* 72 */ "mtp0\t\0" + /* 78 */ "bbit0\t\0" + /* 85 */ "ldc1\t\0" + /* 91 */ "sdc1\t\0" + /* 97 */ "cfc1\t\0" + /* 103 */ "dmfc1\t\0" + /* 110 */ "mfhc1\t\0" + /* 117 */ "mthc1\t\0" + /* 124 */ "ctc1\t\0" + /* 130 */ "dmtc1\t\0" + /* 137 */ "lwc1\t\0" + /* 143 */ "swc1\t\0" + /* 149 */ "ldxc1\t\0" + /* 156 */ "sdxc1\t\0" + /* 163 */ "luxc1\t\0" + /* 170 */ "suxc1\t\0" + /* 177 */ "lwxc1\t\0" + /* 184 */ "swxc1\t\0" + /* 191 */ "mtm1\t\0" + /* 197 */ "mtp1\t\0" + /* 203 */ "bbit1\t\0" + /* 210 */ "bbit032\t\0" + /* 219 */ "bbit132\t\0" + /* 228 */ "dsra32\t\0" + /* 236 */ "bposge32\t\0" + /* 246 */ "dsll32\t\0" + /* 254 */ "dsrl32\t\0" + /* 262 */ "lwm32\t\0" + /* 269 */ "swm32\t\0" + /* 276 */ "drotr32\t\0" + /* 285 */ "cins32\t\0" + /* 293 */ "exts32\t\0" + /* 301 */ "ldc2\t\0" + /* 307 */ "sdc2\t\0" + /* 313 */ "cfc2\t\0" + /* 319 */ "dmfc2\t\0" + /* 326 */ "mfhc2\t\0" + /* 333 */ "mthc2\t\0" + /* 340 */ "ctc2\t\0" + /* 346 */ "dmtc2\t\0" + /* 353 */ "lwc2\t\0" + /* 359 */ "swc2\t\0" + /* 365 */ "mtm2\t\0" + /* 371 */ "mtp2\t\0" + /* 377 */ "addiur2\t\0" + /* 386 */ "ldc3\t\0" + /* 392 */ "sdc3\t\0" + /* 398 */ "lwc3\t\0" + /* 404 */ "swc3\t\0" + /* 410 */ "addius5\t\0" + /* 419 */ "sb16\t\0" + /* 425 */ "bc16\t\0" + /* 431 */ "jrc16\t\0" + /* 438 */ "bnezc16\t\0" + /* 447 */ "beqzc16\t\0" + /* 456 */ "and16\t\0" + /* 463 */ "move16\t\0" + /* 471 */ "sh16\t\0" + /* 477 */ "andi16\t\0" + /* 485 */ "mfhi16\t\0" + /* 493 */ "li16\t\0" + /* 499 */ "break16\t\0" + /* 508 */ "sll16\t\0" + /* 515 */ "srl16\t\0" + /* 522 */ "lwm16\t\0" + /* 529 */ "swm16\t\0" + /* 536 */ "mflo16\t\0" + /* 544 */ "sdbbp16\t\0" + /* 553 */ "jr16\t\0" + /* 559 */ "xor16\t\0" + /* 566 */ "jalrs16\t\0" + /* 575 */ "not16\t\0" + /* 582 */ "lbu16\t\0" + /* 589 */ "subu16\t\0" + /* 597 */ "addu16\t\0" + /* 605 */ "lhu16\t\0" + /* 612 */ "lw16\t\0" + /* 618 */ "sw16\t\0" + /* 624 */ "bnez16\t\0" + /* 632 */ "beqz16\t\0" + /* 640 */ "saa\t\0" + /* 645 */ "preceu.ph.qbla\t\0" + /* 661 */ "precequ.ph.qbla\t\0" + /* 678 */ "dla\t\0" + /* 683 */ "preceu.ph.qbra\t\0" + /* 699 */ "precequ.ph.qbra\t\0" + /* 716 */ "dsra\t\0" + /* 722 */ "dlsa\t\0" + /* 728 */ "cfcmsa\t\0" + /* 736 */ "ctcmsa\t\0" + /* 744 */ "add_a.b\t\0" + /* 753 */ "min_a.b\t\0" + /* 762 */ "adds_a.b\t\0" + /* 772 */ "max_a.b\t\0" + /* 781 */ "sra.b\t\0" + /* 788 */ "nloc.b\t\0" + /* 796 */ "nlzc.b\t\0" + /* 804 */ "sld.b\t\0" + /* 811 */ "pckod.b\t\0" + /* 820 */ "ilvod.b\t\0" + /* 829 */ "insve.b\t\0" + /* 838 */ "vshf.b\t\0" + /* 846 */ "bneg.b\t\0" + /* 854 */ "srai.b\t\0" + /* 862 */ "sldi.b\t\0" + /* 870 */ "andi.b\t\0" + /* 878 */ "bnegi.b\t\0" + /* 887 */ "bseli.b\t\0" + /* 896 */ "slli.b\t\0" + /* 904 */ "srli.b\t\0" + /* 912 */ "binsli.b\t\0" + /* 922 */ "ceqi.b\t\0" + /* 930 */ "srari.b\t\0" + /* 939 */ "bclri.b\t\0" + /* 948 */ "srlri.b\t\0" + /* 957 */ "nori.b\t\0" + /* 965 */ "xori.b\t\0" + /* 973 */ "binsri.b\t\0" + /* 983 */ "splati.b\t\0" + /* 993 */ "bseti.b\t\0" + /* 1002 */ "subvi.b\t\0" + /* 1011 */ "addvi.b\t\0" + /* 1020 */ "bmzi.b\t\0" + /* 1028 */ "bmnzi.b\t\0" + /* 1037 */ "fill.b\t\0" + /* 1045 */ "sll.b\t\0" + /* 1052 */ "srl.b\t\0" + /* 1059 */ "binsl.b\t\0" + /* 1068 */ "ilvl.b\t\0" + /* 1076 */ "ceq.b\t\0" + /* 1083 */ "srar.b\t\0" + /* 1091 */ "bclr.b\t\0" + /* 1099 */ "srlr.b\t\0" + /* 1107 */ "binsr.b\t\0" + /* 1116 */ "ilvr.b\t\0" + /* 1124 */ "asub_s.b\t\0" + /* 1134 */ "mod_s.b\t\0" + /* 1143 */ "cle_s.b\t\0" + /* 1152 */ "ave_s.b\t\0" + /* 1161 */ "clei_s.b\t\0" + /* 1171 */ "mini_s.b\t\0" + /* 1181 */ "clti_s.b\t\0" + /* 1191 */ "maxi_s.b\t\0" + /* 1201 */ "min_s.b\t\0" + /* 1210 */ "aver_s.b\t\0" + /* 1220 */ "subs_s.b\t\0" + /* 1230 */ "adds_s.b\t\0" + /* 1240 */ "sat_s.b\t\0" + /* 1249 */ "clt_s.b\t\0" + /* 1258 */ "subsuu_s.b\t\0" + /* 1270 */ "div_s.b\t\0" + /* 1279 */ "max_s.b\t\0" + /* 1288 */ "copy_s.b\t\0" + /* 1298 */ "splat.b\t\0" + /* 1307 */ "bset.b\t\0" + /* 1315 */ "pcnt.b\t\0" + /* 1323 */ "insert.b\t\0" + /* 1333 */ "st.b\t\0" + /* 1339 */ "asub_u.b\t\0" + /* 1349 */ "mod_u.b\t\0" + /* 1358 */ "cle_u.b\t\0" + /* 1367 */ "ave_u.b\t\0" + /* 1376 */ "clei_u.b\t\0" + /* 1386 */ "mini_u.b\t\0" + /* 1396 */ "clti_u.b\t\0" + /* 1406 */ "maxi_u.b\t\0" + /* 1416 */ "min_u.b\t\0" + /* 1425 */ "aver_u.b\t\0" + /* 1435 */ "subs_u.b\t\0" + /* 1445 */ "adds_u.b\t\0" + /* 1455 */ "subsus_u.b\t\0" + /* 1467 */ "sat_u.b\t\0" + /* 1476 */ "clt_u.b\t\0" + /* 1485 */ "div_u.b\t\0" + /* 1494 */ "max_u.b\t\0" + /* 1503 */ "copy_u.b\t\0" + /* 1513 */ "msubv.b\t\0" + /* 1522 */ "maddv.b\t\0" + /* 1531 */ "pckev.b\t\0" + /* 1540 */ "ilvev.b\t\0" + /* 1549 */ "mulv.b\t\0" + /* 1557 */ "bz.b\t\0" + /* 1563 */ "bnz.b\t\0" + /* 1570 */ "crc32b\t\0" + /* 1578 */ "crc32cb\t\0" + /* 1587 */ "seb\t\0" + /* 1592 */ "jalrc.hb\t\0" + /* 1602 */ "jr.hb\t\0" + /* 1609 */ "jalr.hb\t\0" + /* 1618 */ "lb\t\0" + /* 1622 */ "shra.qb\t\0" + /* 1631 */ "cmpgdu.le.qb\t\0" + /* 1645 */ "cmpgu.le.qb\t\0" + /* 1658 */ "cmpu.le.qb\t\0" + /* 1670 */ "subuh.qb\t\0" + /* 1680 */ "adduh.qb\t\0" + /* 1690 */ "pick.qb\t\0" + /* 1699 */ "shll.qb\t\0" + /* 1708 */ "repl.qb\t\0" + /* 1717 */ "shrl.qb\t\0" + /* 1726 */ "cmpgdu.eq.qb\t\0" + /* 1740 */ "cmpgu.eq.qb\t\0" + /* 1753 */ "cmpu.eq.qb\t\0" + /* 1765 */ "shra_r.qb\t\0" + /* 1776 */ "subuh_r.qb\t\0" + /* 1788 */ "adduh_r.qb\t\0" + /* 1800 */ "shrav_r.qb\t\0" + /* 1812 */ "absq_s.qb\t\0" + /* 1823 */ "subu_s.qb\t\0" + /* 1834 */ "addu_s.qb\t\0" + /* 1845 */ "cmpgdu.lt.qb\t\0" + /* 1859 */ "cmpgu.lt.qb\t\0" + /* 1872 */ "cmpu.lt.qb\t\0" + /* 1884 */ "subu.qb\t\0" + /* 1893 */ "addu.qb\t\0" + /* 1902 */ "shrav.qb\t\0" + /* 1912 */ "shllv.qb\t\0" + /* 1922 */ "replv.qb\t\0" + /* 1932 */ "shrlv.qb\t\0" + /* 1942 */ "raddu.w.qb\t\0" + /* 1954 */ "sb\t\0" + /* 1958 */ "modsub\t\0" + /* 1966 */ "msub\t\0" + /* 1972 */ "bposge32c\t\0" + /* 1983 */ "bc\t\0" + /* 1987 */ "bgec\t\0" + /* 1993 */ "bnec\t\0" + /* 1999 */ "jic\t\0" + /* 2004 */ "balc\t\0" + /* 2010 */ "jialc\t\0" + /* 2017 */ "bgezalc\t\0" + /* 2026 */ "blezalc\t\0" + /* 2035 */ "bnezalc\t\0" + /* 2044 */ "beqzalc\t\0" + /* 2053 */ "bgtzalc\t\0" + /* 2062 */ "bltzalc\t\0" + /* 2071 */ "sync\t\0" + /* 2077 */ "ldpc\t\0" + /* 2083 */ "auipc\t\0" + /* 2090 */ "aluipc\t\0" + /* 2098 */ "addiupc\t\0" + /* 2107 */ "lwupc\t\0" + /* 2114 */ "lwpc\t\0" + /* 2120 */ "beqc\t\0" + /* 2126 */ "jrc\t\0" + /* 2131 */ "jalrc\t\0" + /* 2138 */ "addsc\t\0" + /* 2145 */ "bltc\t\0" + /* 2151 */ "bgeuc\t\0" + /* 2158 */ "bltuc\t\0" + /* 2165 */ "bnvc\t\0" + /* 2171 */ "bovc\t\0" + /* 2177 */ "addwc\t\0" + /* 2184 */ "bgezc\t\0" + /* 2191 */ "blezc\t\0" + /* 2198 */ "bc1nezc\t\0" + /* 2207 */ "bc2nezc\t\0" + /* 2216 */ "bnezc\t\0" + /* 2223 */ "bc1eqzc\t\0" + /* 2232 */ "bc2eqzc\t\0" + /* 2241 */ "beqzc\t\0" + /* 2248 */ "bgtzc\t\0" + /* 2255 */ "bltzc\t\0" + /* 2262 */ "flog2.d\t\0" + /* 2271 */ "fexp2.d\t\0" + /* 2280 */ "add_a.d\t\0" + /* 2289 */ "fmin_a.d\t\0" + /* 2299 */ "adds_a.d\t\0" + /* 2309 */ "fmax_a.d\t\0" + /* 2319 */ "mina.d\t\0" + /* 2327 */ "sra.d\t\0" + /* 2334 */ "maxa.d\t\0" + /* 2342 */ "fsub.d\t\0" + /* 2350 */ "fmsub.d\t\0" + /* 2359 */ "nmsub.d\t\0" + /* 2368 */ "nloc.d\t\0" + /* 2376 */ "nlzc.d\t\0" + /* 2384 */ "fadd.d\t\0" + /* 2392 */ "fmadd.d\t\0" + /* 2401 */ "nmadd.d\t\0" + /* 2410 */ "sld.d\t\0" + /* 2417 */ "pckod.d\t\0" + /* 2426 */ "ilvod.d\t\0" + /* 2435 */ "c.nge.d\t\0" + /* 2444 */ "c.le.d\t\0" + /* 2452 */ "cmp.le.d\t\0" + /* 2462 */ "fcle.d\t\0" + /* 2470 */ "c.ngle.d\t\0" + /* 2480 */ "c.ole.d\t\0" + /* 2489 */ "cmp.sle.d\t\0" + /* 2500 */ "fsle.d\t\0" + /* 2508 */ "c.ule.d\t\0" + /* 2517 */ "cmp.ule.d\t\0" + /* 2528 */ "fcule.d\t\0" + /* 2537 */ "cmp.sule.d\t\0" + /* 2549 */ "fsule.d\t\0" + /* 2558 */ "fcne.d\t\0" + /* 2566 */ "fsne.d\t\0" + /* 2574 */ "fcune.d\t\0" + /* 2583 */ "fsune.d\t\0" + /* 2592 */ "insve.d\t\0" + /* 2601 */ "c.f.d\t\0" + /* 2608 */ "cmp.af.d\t\0" + /* 2618 */ "fcaf.d\t\0" + /* 2626 */ "cmp.saf.d\t\0" + /* 2637 */ "fsaf.d\t\0" + /* 2645 */ "msubf.d\t\0" + /* 2654 */ "maddf.d\t\0" + /* 2663 */ "vshf.d\t\0" + /* 2671 */ "c.sf.d\t\0" + /* 2679 */ "movf.d\t\0" + /* 2687 */ "bneg.d\t\0" + /* 2695 */ "srai.d\t\0" + /* 2703 */ "sldi.d\t\0" + /* 2711 */ "bnegi.d\t\0" + /* 2720 */ "slli.d\t\0" + /* 2728 */ "srli.d\t\0" + /* 2736 */ "binsli.d\t\0" + /* 2746 */ "ceqi.d\t\0" + /* 2754 */ "srari.d\t\0" + /* 2763 */ "bclri.d\t\0" + /* 2772 */ "srlri.d\t\0" + /* 2781 */ "binsri.d\t\0" + /* 2791 */ "splati.d\t\0" + /* 2801 */ "bseti.d\t\0" + /* 2810 */ "subvi.d\t\0" + /* 2819 */ "addvi.d\t\0" + /* 2828 */ "trunc.l.d\t\0" + /* 2839 */ "round.l.d\t\0" + /* 2850 */ "ceil.l.d\t\0" + /* 2860 */ "floor.l.d\t\0" + /* 2871 */ "cvt.l.d\t\0" + /* 2880 */ "sel.d\t\0" + /* 2887 */ "c.ngl.d\t\0" + /* 2896 */ "fill.d\t\0" + /* 2904 */ "sll.d\t\0" + /* 2911 */ "fexupl.d\t\0" + /* 2921 */ "ffql.d\t\0" + /* 2929 */ "srl.d\t\0" + /* 2936 */ "binsl.d\t\0" + /* 2945 */ "fmul.d\t\0" + /* 2953 */ "ilvl.d\t\0" + /* 2961 */ "fmin.d\t\0" + /* 2969 */ "c.un.d\t\0" + /* 2977 */ "cmp.un.d\t\0" + /* 2987 */ "fcun.d\t\0" + /* 2995 */ "cmp.sun.d\t\0" + /* 3006 */ "fsun.d\t\0" + /* 3014 */ "movn.d\t\0" + /* 3022 */ "frcp.d\t\0" + /* 3030 */ "recip.d\t\0" + /* 3039 */ "c.eq.d\t\0" + /* 3047 */ "cmp.eq.d\t\0" + /* 3057 */ "fceq.d\t\0" + /* 3065 */ "c.seq.d\t\0" + /* 3074 */ "cmp.seq.d\t\0" + /* 3085 */ "fseq.d\t\0" + /* 3093 */ "c.ueq.d\t\0" + /* 3102 */ "cmp.ueq.d\t\0" + /* 3113 */ "fcueq.d\t\0" + /* 3122 */ "cmp.sueq.d\t\0" + /* 3134 */ "fsueq.d\t\0" + /* 3143 */ "srar.d\t\0" + /* 3151 */ "bclr.d\t\0" + /* 3159 */ "srlr.d\t\0" + /* 3167 */ "fcor.d\t\0" + /* 3175 */ "fsor.d\t\0" + /* 3183 */ "fexupr.d\t\0" + /* 3193 */ "ffqr.d\t\0" + /* 3201 */ "binsr.d\t\0" + /* 3210 */ "ilvr.d\t\0" + /* 3218 */ "cvt.s.d\t\0" + /* 3227 */ "asub_s.d\t\0" + /* 3237 */ "hsub_s.d\t\0" + /* 3247 */ "dpsub_s.d\t\0" + /* 3258 */ "ftrunc_s.d\t\0" + /* 3270 */ "hadd_s.d\t\0" + /* 3280 */ "dpadd_s.d\t\0" + /* 3291 */ "mod_s.d\t\0" + /* 3300 */ "cle_s.d\t\0" + /* 3309 */ "ave_s.d\t\0" + /* 3318 */ "clei_s.d\t\0" + /* 3328 */ "mini_s.d\t\0" + /* 3338 */ "clti_s.d\t\0" + /* 3348 */ "maxi_s.d\t\0" + /* 3358 */ "min_s.d\t\0" + /* 3367 */ "dotp_s.d\t\0" + /* 3377 */ "aver_s.d\t\0" + /* 3387 */ "subs_s.d\t\0" + /* 3397 */ "adds_s.d\t\0" + /* 3407 */ "sat_s.d\t\0" + /* 3416 */ "clt_s.d\t\0" + /* 3425 */ "ffint_s.d\t\0" + /* 3436 */ "ftint_s.d\t\0" + /* 3447 */ "subsuu_s.d\t\0" + /* 3459 */ "div_s.d\t\0" + /* 3468 */ "max_s.d\t\0" + /* 3477 */ "copy_s.d\t\0" + /* 3487 */ "abs.d\t\0" + /* 3494 */ "fclass.d\t\0" + /* 3504 */ "splat.d\t\0" + /* 3513 */ "bset.d\t\0" + /* 3521 */ "c.ngt.d\t\0" + /* 3530 */ "c.lt.d\t\0" + /* 3538 */ "cmp.lt.d\t\0" + /* 3548 */ "fclt.d\t\0" + /* 3556 */ "c.olt.d\t\0" + /* 3565 */ "cmp.slt.d\t\0" + /* 3576 */ "fslt.d\t\0" + /* 3584 */ "c.ult.d\t\0" + /* 3593 */ "cmp.ult.d\t\0" + /* 3604 */ "fcult.d\t\0" + /* 3613 */ "cmp.sult.d\t\0" + /* 3625 */ "fsult.d\t\0" + /* 3634 */ "pcnt.d\t\0" + /* 3642 */ "frint.d\t\0" + /* 3651 */ "insert.d\t\0" + /* 3661 */ "fsqrt.d\t\0" + /* 3670 */ "frsqrt.d\t\0" + /* 3680 */ "st.d\t\0" + /* 3686 */ "movt.d\t\0" + /* 3694 */ "asub_u.d\t\0" + /* 3704 */ "hsub_u.d\t\0" + /* 3714 */ "dpsub_u.d\t\0" + /* 3725 */ "ftrunc_u.d\t\0" + /* 3737 */ "hadd_u.d\t\0" + /* 3747 */ "dpadd_u.d\t\0" + /* 3758 */ "mod_u.d\t\0" + /* 3767 */ "cle_u.d\t\0" + /* 3776 */ "ave_u.d\t\0" + /* 3785 */ "clei_u.d\t\0" + /* 3795 */ "mini_u.d\t\0" + /* 3805 */ "clti_u.d\t\0" + /* 3815 */ "maxi_u.d\t\0" + /* 3825 */ "min_u.d\t\0" + /* 3834 */ "dotp_u.d\t\0" + /* 3844 */ "aver_u.d\t\0" + /* 3854 */ "subs_u.d\t\0" + /* 3864 */ "adds_u.d\t\0" + /* 3874 */ "subsus_u.d\t\0" + /* 3886 */ "sat_u.d\t\0" + /* 3895 */ "clt_u.d\t\0" + /* 3904 */ "ffint_u.d\t\0" + /* 3915 */ "ftint_u.d\t\0" + /* 3926 */ "div_u.d\t\0" + /* 3935 */ "max_u.d\t\0" + /* 3944 */ "msubv.d\t\0" + /* 3953 */ "maddv.d\t\0" + /* 3962 */ "pckev.d\t\0" + /* 3971 */ "ilvev.d\t\0" + /* 3980 */ "fdiv.d\t\0" + /* 3988 */ "mulv.d\t\0" + /* 3996 */ "mov.d\t\0" + /* 4003 */ "trunc.w.d\t\0" + /* 4014 */ "round.w.d\t\0" + /* 4025 */ "ceil.w.d\t\0" + /* 4035 */ "floor.w.d\t\0" + /* 4046 */ "cvt.w.d\t\0" + /* 4055 */ "fmax.d\t\0" + /* 4063 */ "bz.d\t\0" + /* 4069 */ "selnez.d\t\0" + /* 4079 */ "bnz.d\t\0" + /* 4086 */ "seleqz.d\t\0" + /* 4096 */ "movz.d\t\0" + /* 4104 */ "crc32d\t\0" + /* 4112 */ "saad\t\0" + /* 4118 */ "crc32cd\t\0" + /* 4127 */ "scd\t\0" + /* 4132 */ "dadd\t\0" + /* 4138 */ "madd\t\0" + /* 4144 */ "dshd\t\0" + /* 4150 */ "yield\t\0" + /* 4157 */ "lld\t\0" + /* 4162 */ "and\t\0" + /* 4167 */ "prepend\t\0" + /* 4176 */ "append\t\0" + /* 4184 */ "dmod\t\0" + /* 4190 */ "sd\t\0" + /* 4194 */ "lbe\t\0" + /* 4199 */ "sbe\t\0" + /* 4204 */ "sce\t\0" + /* 4209 */ "cachee\t\0" + /* 4217 */ "prefe\t\0" + /* 4224 */ "bge\t\0" + /* 4229 */ "sge\t\0" + /* 4234 */ "tge\t\0" + /* 4239 */ "cache\t\0" + /* 4246 */ "lhe\t\0" + /* 4251 */ "she\t\0" + /* 4256 */ "sigrie\t\0" + /* 4264 */ "ble\t\0" + /* 4269 */ "lle\t\0" + /* 4274 */ "sle\t\0" + /* 4279 */ "lwle\t\0" + /* 4285 */ "swle\t\0" + /* 4291 */ "bne\t\0" + /* 4296 */ "sne\t\0" + /* 4301 */ "tne\t\0" + /* 4306 */ "dvpe\t\0" + /* 4312 */ "evpe\t\0" + /* 4318 */ "lwre\t\0" + /* 4324 */ "swre\t\0" + /* 4330 */ "lbue\t\0" + /* 4336 */ "lhue\t\0" + /* 4342 */ "move\t\0" + /* 4348 */ "lwe\t\0" + /* 4353 */ "swe\t\0" + /* 4358 */ "bc0f\t\0" + /* 4364 */ "bc1f\t\0" + /* 4370 */ "bc2f\t\0" + /* 4376 */ "bc3f\t\0" + /* 4382 */ "pref\t\0" + /* 4388 */ "movf\t\0" + /* 4394 */ "neg\t\0" + /* 4399 */ "add_a.h\t\0" + /* 4408 */ "min_a.h\t\0" + /* 4417 */ "adds_a.h\t\0" + /* 4427 */ "max_a.h\t\0" + /* 4436 */ "sra.h\t\0" + /* 4443 */ "nloc.h\t\0" + /* 4451 */ "nlzc.h\t\0" + /* 4459 */ "sld.h\t\0" + /* 4466 */ "pckod.h\t\0" + /* 4475 */ "ilvod.h\t\0" + /* 4484 */ "insve.h\t\0" + /* 4493 */ "vshf.h\t\0" + /* 4501 */ "bneg.h\t\0" + /* 4509 */ "srai.h\t\0" + /* 4517 */ "sldi.h\t\0" + /* 4525 */ "bnegi.h\t\0" + /* 4534 */ "slli.h\t\0" + /* 4542 */ "srli.h\t\0" + /* 4550 */ "binsli.h\t\0" + /* 4560 */ "ceqi.h\t\0" + /* 4568 */ "srari.h\t\0" + /* 4577 */ "bclri.h\t\0" + /* 4586 */ "srlri.h\t\0" + /* 4595 */ "binsri.h\t\0" + /* 4605 */ "splati.h\t\0" + /* 4615 */ "bseti.h\t\0" + /* 4624 */ "subvi.h\t\0" + /* 4633 */ "addvi.h\t\0" + /* 4642 */ "fill.h\t\0" + /* 4650 */ "sll.h\t\0" + /* 4657 */ "srl.h\t\0" + /* 4664 */ "binsl.h\t\0" + /* 4673 */ "ilvl.h\t\0" + /* 4681 */ "fexdo.h\t\0" + /* 4690 */ "msub_q.h\t\0" + /* 4700 */ "madd_q.h\t\0" + /* 4710 */ "mul_q.h\t\0" + /* 4719 */ "msubr_q.h\t\0" + /* 4730 */ "maddr_q.h\t\0" + /* 4741 */ "mulr_q.h\t\0" + /* 4751 */ "ceq.h\t\0" + /* 4758 */ "ftq.h\t\0" + /* 4765 */ "srar.h\t\0" + /* 4773 */ "bclr.h\t\0" + /* 4781 */ "srlr.h\t\0" + /* 4789 */ "binsr.h\t\0" + /* 4798 */ "ilvr.h\t\0" + /* 4806 */ "asub_s.h\t\0" + /* 4816 */ "hsub_s.h\t\0" + /* 4826 */ "dpsub_s.h\t\0" + /* 4837 */ "hadd_s.h\t\0" + /* 4847 */ "dpadd_s.h\t\0" + /* 4858 */ "mod_s.h\t\0" + /* 4867 */ "cle_s.h\t\0" + /* 4876 */ "ave_s.h\t\0" + /* 4885 */ "clei_s.h\t\0" + /* 4895 */ "mini_s.h\t\0" + /* 4905 */ "clti_s.h\t\0" + /* 4915 */ "maxi_s.h\t\0" + /* 4925 */ "min_s.h\t\0" + /* 4934 */ "dotp_s.h\t\0" + /* 4944 */ "aver_s.h\t\0" + /* 4954 */ "extr_s.h\t\0" + /* 4964 */ "subs_s.h\t\0" + /* 4974 */ "adds_s.h\t\0" + /* 4984 */ "sat_s.h\t\0" + /* 4993 */ "clt_s.h\t\0" + /* 5002 */ "subsuu_s.h\t\0" + /* 5014 */ "div_s.h\t\0" + /* 5023 */ "extrv_s.h\t\0" + /* 5034 */ "max_s.h\t\0" + /* 5043 */ "copy_s.h\t\0" + /* 5053 */ "splat.h\t\0" + /* 5062 */ "bset.h\t\0" + /* 5070 */ "pcnt.h\t\0" + /* 5078 */ "insert.h\t\0" + /* 5088 */ "st.h\t\0" + /* 5094 */ "asub_u.h\t\0" + /* 5104 */ "hsub_u.h\t\0" + /* 5114 */ "dpsub_u.h\t\0" + /* 5125 */ "hadd_u.h\t\0" + /* 5135 */ "dpadd_u.h\t\0" + /* 5146 */ "mod_u.h\t\0" + /* 5155 */ "cle_u.h\t\0" + /* 5164 */ "ave_u.h\t\0" + /* 5173 */ "clei_u.h\t\0" + /* 5183 */ "mini_u.h\t\0" + /* 5193 */ "clti_u.h\t\0" + /* 5203 */ "maxi_u.h\t\0" + /* 5213 */ "min_u.h\t\0" + /* 5222 */ "dotp_u.h\t\0" + /* 5232 */ "aver_u.h\t\0" + /* 5242 */ "subs_u.h\t\0" + /* 5252 */ "adds_u.h\t\0" + /* 5262 */ "subsus_u.h\t\0" + /* 5274 */ "sat_u.h\t\0" + /* 5283 */ "clt_u.h\t\0" + /* 5292 */ "div_u.h\t\0" + /* 5301 */ "max_u.h\t\0" + /* 5310 */ "copy_u.h\t\0" + /* 5320 */ "msubv.h\t\0" + /* 5329 */ "maddv.h\t\0" + /* 5338 */ "pckev.h\t\0" + /* 5347 */ "ilvev.h\t\0" + /* 5356 */ "mulv.h\t\0" + /* 5364 */ "bz.h\t\0" + /* 5370 */ "bnz.h\t\0" + /* 5377 */ "crc32h\t\0" + /* 5385 */ "dsbh\t\0" + /* 5391 */ "wsbh\t\0" + /* 5397 */ "crc32ch\t\0" + /* 5406 */ "seh\t\0" + /* 5411 */ "ulh\t\0" + /* 5416 */ "shra.ph\t\0" + /* 5425 */ "precrq.qb.ph\t\0" + /* 5439 */ "precr.qb.ph\t\0" + /* 5452 */ "precrqu_s.qb.ph\t\0" + /* 5469 */ "cmp.le.ph\t\0" + /* 5480 */ "subqh.ph\t\0" + /* 5490 */ "addqh.ph\t\0" + /* 5500 */ "pick.ph\t\0" + /* 5509 */ "shll.ph\t\0" + /* 5518 */ "repl.ph\t\0" + /* 5527 */ "shrl.ph\t\0" + /* 5536 */ "packrl.ph\t\0" + /* 5547 */ "mul.ph\t\0" + /* 5555 */ "subq.ph\t\0" + /* 5564 */ "addq.ph\t\0" + /* 5573 */ "cmp.eq.ph\t\0" + /* 5584 */ "shra_r.ph\t\0" + /* 5595 */ "subqh_r.ph\t\0" + /* 5607 */ "addqh_r.ph\t\0" + /* 5619 */ "shrav_r.ph\t\0" + /* 5631 */ "shll_s.ph\t\0" + /* 5642 */ "mul_s.ph\t\0" + /* 5652 */ "subq_s.ph\t\0" + /* 5663 */ "addq_s.ph\t\0" + /* 5674 */ "mulq_s.ph\t\0" + /* 5685 */ "absq_s.ph\t\0" + /* 5696 */ "subu_s.ph\t\0" + /* 5707 */ "addu_s.ph\t\0" + /* 5718 */ "shllv_s.ph\t\0" + /* 5730 */ "mulq_rs.ph\t\0" + /* 5742 */ "cmp.lt.ph\t\0" + /* 5753 */ "subu.ph\t\0" + /* 5762 */ "addu.ph\t\0" + /* 5771 */ "shrav.ph\t\0" + /* 5781 */ "shllv.ph\t\0" + /* 5791 */ "replv.ph\t\0" + /* 5801 */ "shrlv.ph\t\0" + /* 5811 */ "dpa.w.ph\t\0" + /* 5821 */ "dpaqx_sa.w.ph\t\0" + /* 5836 */ "dpsqx_sa.w.ph\t\0" + /* 5851 */ "mulsa.w.ph\t\0" + /* 5863 */ "dpaq_s.w.ph\t\0" + /* 5876 */ "mulsaq_s.w.ph\t\0" + /* 5891 */ "dpsq_s.w.ph\t\0" + /* 5904 */ "dpaqx_s.w.ph\t\0" + /* 5918 */ "dpsqx_s.w.ph\t\0" + /* 5932 */ "dps.w.ph\t\0" + /* 5942 */ "dpax.w.ph\t\0" + /* 5953 */ "dpsx.w.ph\t\0" + /* 5964 */ "ush\t\0" + /* 5969 */ "dmuh\t\0" + /* 5975 */ "synci\t\0" + /* 5982 */ "daddi\t\0" + /* 5989 */ "andi\t\0" + /* 5995 */ "tgei\t\0" + /* 6001 */ "snei\t\0" + /* 6007 */ "tnei\t\0" + /* 6013 */ "dahi\t\0" + /* 6019 */ "mfhi\t\0" + /* 6025 */ "mthi\t\0" + /* 6031 */ ".align 2\n\tli\t\0" + /* 6045 */ "dli\t\0" + /* 6050 */ "cmpi\t\0" + /* 6056 */ "seqi\t\0" + /* 6062 */ "teqi\t\0" + /* 6068 */ "xori\t\0" + /* 6074 */ "dati\t\0" + /* 6080 */ "slti\t\0" + /* 6086 */ "tlti\t\0" + /* 6092 */ "daui\t\0" + /* 6098 */ "lui\t\0" + /* 6103 */ "ginvi\t\0" + /* 6110 */ "j\t\0" + /* 6113 */ "break\t\0" + /* 6120 */ "fork\t\0" + /* 6126 */ "cvt.d.l\t\0" + /* 6135 */ "cvt.s.l\t\0" + /* 6144 */ "bal\t\0" + /* 6149 */ "jal\t\0" + /* 6154 */ "bgezal\t\0" + /* 6162 */ "bltzal\t\0" + /* 6170 */ "dpau.h.qbl\t\0" + /* 6182 */ "dpsu.h.qbl\t\0" + /* 6194 */ "muleu_s.ph.qbl\t\0" + /* 6210 */ "preceu.ph.qbl\t\0" + /* 6225 */ "precequ.ph.qbl\t\0" + /* 6241 */ "ldl\t\0" + /* 6246 */ "sdl\t\0" + /* 6251 */ "bgel\t\0" + /* 6257 */ "blel\t\0" + /* 6263 */ "bnel\t\0" + /* 6269 */ "bc1fl\t\0" + /* 6276 */ "bc2fl\t\0" + /* 6283 */ "bc3fl\t\0" + /* 6290 */ "maq_sa.w.phl\t\0" + /* 6304 */ "preceq.w.phl\t\0" + /* 6318 */ "maq_s.w.phl\t\0" + /* 6331 */ "muleq_s.w.phl\t\0" + /* 6346 */ "hypcall\t\0" + /* 6355 */ "syscall\t\0" + /* 6364 */ "bgezall\t\0" + /* 6373 */ "bltzall\t\0" + /* 6382 */ "dsll\t\0" + /* 6388 */ "drol\t\0" + /* 6394 */ "cvt.s.pl\t\0" + /* 6404 */ "beql\t\0" + /* 6410 */ "dsrl\t\0" + /* 6416 */ "bc1tl\t\0" + /* 6423 */ "bc2tl\t\0" + /* 6430 */ "bc3tl\t\0" + /* 6437 */ "bgtl\t\0" + /* 6443 */ "bltl\t\0" + /* 6449 */ "bgeul\t\0" + /* 6456 */ "bleul\t\0" + /* 6463 */ "dmul\t\0" + /* 6469 */ "bgtul\t\0" + /* 6476 */ "bltul\t\0" + /* 6483 */ "lwl\t\0" + /* 6488 */ "swl\t\0" + /* 6493 */ "bgezl\t\0" + /* 6500 */ "blezl\t\0" + /* 6507 */ "bgtzl\t\0" + /* 6514 */ "bltzl\t\0" + /* 6521 */ "drem\t\0" + /* 6527 */ "dinsm\t\0" + /* 6534 */ "dextm\t\0" + /* 6541 */ "lwm\t\0" + /* 6546 */ "swm\t\0" + /* 6551 */ "balign\t\0" + /* 6559 */ "dalign\t\0" + /* 6567 */ "movn\t\0" + /* 6573 */ "dclo\t\0" + /* 6579 */ "mflo\t\0" + /* 6585 */ "shilo\t\0" + /* 6592 */ "mtlo\t\0" + /* 6598 */ "dmulo\t\0" + /* 6605 */ "dbitswap\t\0" + /* 6615 */ "sdbbp\t\0" + /* 6622 */ "extpdp\t\0" + /* 6630 */ "movep\t\0" + /* 6637 */ "mthlip\t\0" + /* 6645 */ "cmp\t\0" + /* 6650 */ "dpop\t\0" + /* 6656 */ "addiur1sp\t\0" + /* 6667 */ "load_ccond_dsp\t\0" + /* 6683 */ "store_ccond_dsp\t\0" + /* 6700 */ "rddsp\t\0" + /* 6707 */ "wrdsp\t\0" + /* 6714 */ "jrcaddiusp\t\0" + /* 6726 */ "jraddiusp\t\0" + /* 6737 */ "swsp\t\0" + /* 6743 */ "extp\t\0" + /* 6749 */ "dvp\t\0" + /* 6754 */ "evp\t\0" + /* 6759 */ "lwp\t\0" + /* 6764 */ "swp\t\0" + /* 6769 */ "beq\t\0" + /* 6774 */ "seq\t\0" + /* 6779 */ "teq\t\0" + /* 6784 */ "dpau.h.qbr\t\0" + /* 6796 */ "dpsu.h.qbr\t\0" + /* 6808 */ "muleu_s.ph.qbr\t\0" + /* 6824 */ "preceu.ph.qbr\t\0" + /* 6839 */ "precequ.ph.qbr\t\0" + /* 6855 */ "ldr\t\0" + /* 6860 */ "sdr\t\0" + /* 6865 */ "maq_sa.w.phr\t\0" + /* 6879 */ "preceq.w.phr\t\0" + /* 6893 */ "maq_s.w.phr\t\0" + /* 6906 */ "muleq_s.w.phr\t\0" + /* 6921 */ "jr\t\0" + /* 6925 */ "jalr\t\0" + /* 6931 */ "nor\t\0" + /* 6936 */ "dror\t\0" + /* 6942 */ "xor\t\0" + /* 6947 */ "rdpgpr\t\0" + /* 6955 */ "wrpgpr\t\0" + /* 6963 */ "mftr\t\0" + /* 6969 */ "drotr\t\0" + /* 6976 */ "mttr\t\0" + /* 6982 */ "rdhwr\t\0" + /* 6989 */ "lwr\t\0" + /* 6994 */ "swr\t\0" + /* 6999 */ "mina.s\t\0" + /* 7007 */ "maxa.s\t\0" + /* 7015 */ "nmsub.s\t\0" + /* 7024 */ "cvt.d.s\t\0" + /* 7033 */ "nmadd.s\t\0" + /* 7042 */ "c.nge.s\t\0" + /* 7051 */ "c.le.s\t\0" + /* 7059 */ "cmp.le.s\t\0" + /* 7069 */ "c.ngle.s\t\0" + /* 7079 */ "c.ole.s\t\0" + /* 7088 */ "cmp.sle.s\t\0" + /* 7099 */ "c.ule.s\t\0" + /* 7108 */ "cmp.ule.s\t\0" + /* 7119 */ "cmp.sule.s\t\0" + /* 7131 */ "c.f.s\t\0" + /* 7138 */ "cmp.af.s\t\0" + /* 7148 */ "cmp.saf.s\t\0" + /* 7159 */ "msubf.s\t\0" + /* 7168 */ "maddf.s\t\0" + /* 7177 */ "c.sf.s\t\0" + /* 7185 */ "movf.s\t\0" + /* 7193 */ "neg.s\t\0" + /* 7200 */ "li.s\t\0" + /* 7206 */ "trunc.l.s\t\0" + /* 7217 */ "round.l.s\t\0" + /* 7228 */ "ceil.l.s\t\0" + /* 7238 */ "floor.l.s\t\0" + /* 7249 */ "cvt.l.s\t\0" + /* 7258 */ "sel.s\t\0" + /* 7265 */ "c.ngl.s\t\0" + /* 7274 */ "mul.s\t\0" + /* 7281 */ "min.s\t\0" + /* 7288 */ "c.un.s\t\0" + /* 7296 */ "cmp.un.s\t\0" + /* 7306 */ "cmp.sun.s\t\0" + /* 7317 */ "movn.s\t\0" + /* 7325 */ "recip.s\t\0" + /* 7334 */ "c.eq.s\t\0" + /* 7342 */ "cmp.eq.s\t\0" + /* 7352 */ "c.seq.s\t\0" + /* 7361 */ "cmp.seq.s\t\0" + /* 7372 */ "c.ueq.s\t\0" + /* 7381 */ "cmp.ueq.s\t\0" + /* 7392 */ "cmp.sueq.s\t\0" + /* 7404 */ "abs.s\t\0" + /* 7411 */ "cvt.ps.s\t\0" + /* 7421 */ "class.s\t\0" + /* 7430 */ "c.ngt.s\t\0" + /* 7439 */ "c.lt.s\t\0" + /* 7447 */ "cmp.lt.s\t\0" + /* 7457 */ "c.olt.s\t\0" + /* 7466 */ "cmp.slt.s\t\0" + /* 7477 */ "c.ult.s\t\0" + /* 7486 */ "cmp.ult.s\t\0" + /* 7497 */ "cmp.sult.s\t\0" + /* 7509 */ "rint.s\t\0" + /* 7517 */ "rsqrt.s\t\0" + /* 7526 */ "movt.s\t\0" + /* 7534 */ "div.s\t\0" + /* 7541 */ "mov.s\t\0" + /* 7548 */ "trunc.w.s\t\0" + /* 7559 */ "round.w.s\t\0" + /* 7570 */ "ceil.w.s\t\0" + /* 7580 */ "floor.w.s\t\0" + /* 7591 */ "cvt.w.s\t\0" + /* 7600 */ "max.s\t\0" + /* 7607 */ "selnez.s\t\0" + /* 7617 */ "seleqz.s\t\0" + /* 7627 */ "movz.s\t\0" + /* 7635 */ "abs\t\0" + /* 7640 */ "jals\t\0" + /* 7646 */ "bgezals\t\0" + /* 7655 */ "bltzals\t\0" + /* 7664 */ "cins\t\0" + /* 7670 */ "dins\t\0" + /* 7676 */ "sub.ps\t\0" + /* 7684 */ "add.ps\t\0" + /* 7692 */ "pll.ps\t\0" + /* 7700 */ "mul.ps\t\0" + /* 7708 */ "pul.ps\t\0" + /* 7716 */ "addr.ps\t\0" + /* 7725 */ "mulr.ps\t\0" + /* 7734 */ "plu.ps\t\0" + /* 7742 */ "puu.ps\t\0" + /* 7750 */ "cvt.pw.ps\t\0" + /* 7761 */ "jalrs\t\0" + /* 7768 */ "exts\t\0" + /* 7774 */ "lwxs\t\0" + /* 7780 */ "bc0t\t\0" + /* 7786 */ "bc1t\t\0" + /* 7792 */ "bc2t\t\0" + /* 7798 */ "bc3t\t\0" + /* 7804 */ "bgt\t\0" + /* 7809 */ "sgt\t\0" + /* 7814 */ "wait\t\0" + /* 7820 */ "blt\t\0" + /* 7825 */ "slt\t\0" + /* 7830 */ "tlt\t\0" + /* 7835 */ "dmult\t\0" + /* 7842 */ "dmt\t\0" + /* 7847 */ "emt\t\0" + /* 7852 */ "not\t\0" + /* 7857 */ "ginvt\t\0" + /* 7864 */ "movt\t\0" + /* 7870 */ "dext\t\0" + /* 7876 */ "lbu\t\0" + /* 7881 */ "dsubu\t\0" + /* 7888 */ "msubu\t\0" + /* 7895 */ "baddu\t\0" + /* 7902 */ "daddu\t\0" + /* 7909 */ "maddu\t\0" + /* 7916 */ "dmodu\t\0" + /* 7923 */ "bgeu\t\0" + /* 7929 */ "sgeu\t\0" + /* 7935 */ "tgeu\t\0" + /* 7941 */ "bleu\t\0" + /* 7947 */ "sleu\t\0" + /* 7953 */ "ulhu\t\0" + /* 7959 */ "dmuhu\t\0" + /* 7966 */ "daddiu\t\0" + /* 7974 */ "tgeiu\t\0" + /* 7981 */ "sltiu\t\0" + /* 7988 */ "tltiu\t\0" + /* 7995 */ "v3mulu\t\0" + /* 8003 */ "dmulu\t\0" + /* 8010 */ "vmulu\t\0" + /* 8017 */ "dremu\t\0" + /* 8024 */ "dmulou\t\0" + /* 8032 */ "cvt.s.pu\t\0" + /* 8042 */ "dinsu\t\0" + /* 8049 */ "bgtu\t\0" + /* 8055 */ "sgtu\t\0" + /* 8061 */ "bltu\t\0" + /* 8067 */ "sltu\t\0" + /* 8073 */ "tltu\t\0" + /* 8079 */ "dmultu\t\0" + /* 8087 */ "dextu\t\0" + /* 8094 */ "ddivu\t\0" + /* 8101 */ "lwu\t\0" + /* 8106 */ "and.v\t\0" + /* 8113 */ "move.v\t\0" + /* 8121 */ "bsel.v\t\0" + /* 8129 */ "nor.v\t\0" + /* 8136 */ "xor.v\t\0" + /* 8143 */ "bz.v\t\0" + /* 8149 */ "bmz.v\t\0" + /* 8156 */ "bnz.v\t\0" + /* 8163 */ "bmnz.v\t\0" + /* 8171 */ "dsrav\t\0" + /* 8178 */ "bitrev\t\0" + /* 8186 */ "ddiv\t\0" + /* 8192 */ "dsllv\t\0" + /* 8199 */ "dsrlv\t\0" + /* 8206 */ "shilov\t\0" + /* 8214 */ "extpdpv\t\0" + /* 8223 */ "extpv\t\0" + /* 8230 */ "drotrv\t\0" + /* 8238 */ "insv\t\0" + /* 8244 */ "flog2.w\t\0" + /* 8253 */ "fexp2.w\t\0" + /* 8262 */ "add_a.w\t\0" + /* 8271 */ "fmin_a.w\t\0" + /* 8281 */ "adds_a.w\t\0" + /* 8291 */ "fmax_a.w\t\0" + /* 8301 */ "sra.w\t\0" + /* 8308 */ "fsub.w\t\0" + /* 8316 */ "fmsub.w\t\0" + /* 8325 */ "nloc.w\t\0" + /* 8333 */ "nlzc.w\t\0" + /* 8341 */ "cvt.d.w\t\0" + /* 8350 */ "fadd.w\t\0" + /* 8358 */ "fmadd.w\t\0" + /* 8367 */ "sld.w\t\0" + /* 8374 */ "pckod.w\t\0" + /* 8383 */ "ilvod.w\t\0" + /* 8392 */ "fcle.w\t\0" + /* 8400 */ "fsle.w\t\0" + /* 8408 */ "fcule.w\t\0" + /* 8417 */ "fsule.w\t\0" + /* 8426 */ "fcne.w\t\0" + /* 8434 */ "fsne.w\t\0" + /* 8442 */ "fcune.w\t\0" + /* 8451 */ "fsune.w\t\0" + /* 8460 */ "insve.w\t\0" + /* 8469 */ "fcaf.w\t\0" + /* 8477 */ "fsaf.w\t\0" + /* 8485 */ "vshf.w\t\0" + /* 8493 */ "bneg.w\t\0" + /* 8501 */ "precr_sra.ph.w\t\0" + /* 8517 */ "precrq.ph.w\t\0" + /* 8530 */ "precr_sra_r.ph.w\t\0" + /* 8548 */ "precrq_rs.ph.w\t\0" + /* 8564 */ "subqh.w\t\0" + /* 8573 */ "addqh.w\t\0" + /* 8582 */ "srai.w\t\0" + /* 8590 */ "sldi.w\t\0" + /* 8598 */ "bnegi.w\t\0" + /* 8607 */ "slli.w\t\0" + /* 8615 */ "srli.w\t\0" + /* 8623 */ "binsli.w\t\0" + /* 8633 */ "ceqi.w\t\0" + /* 8641 */ "srari.w\t\0" + /* 8650 */ "bclri.w\t\0" + /* 8659 */ "srlri.w\t\0" + /* 8668 */ "binsri.w\t\0" + /* 8678 */ "splati.w\t\0" + /* 8688 */ "bseti.w\t\0" + /* 8697 */ "subvi.w\t\0" + /* 8706 */ "addvi.w\t\0" + /* 8715 */ "dpaq_sa.l.w\t\0" + /* 8728 */ "dpsq_sa.l.w\t\0" + /* 8741 */ "fill.w\t\0" + /* 8749 */ "sll.w\t\0" + /* 8756 */ "fexupl.w\t\0" + /* 8766 */ "ffql.w\t\0" + /* 8774 */ "srl.w\t\0" + /* 8781 */ "binsl.w\t\0" + /* 8790 */ "fmul.w\t\0" + /* 8798 */ "ilvl.w\t\0" + /* 8806 */ "fmin.w\t\0" + /* 8814 */ "fcun.w\t\0" + /* 8822 */ "fsun.w\t\0" + /* 8830 */ "fexdo.w\t\0" + /* 8839 */ "frcp.w\t\0" + /* 8847 */ "msub_q.w\t\0" + /* 8857 */ "madd_q.w\t\0" + /* 8867 */ "mul_q.w\t\0" + /* 8876 */ "msubr_q.w\t\0" + /* 8887 */ "maddr_q.w\t\0" + /* 8898 */ "mulr_q.w\t\0" + /* 8908 */ "fceq.w\t\0" + /* 8916 */ "fseq.w\t\0" + /* 8924 */ "fcueq.w\t\0" + /* 8933 */ "fsueq.w\t\0" + /* 8942 */ "ftq.w\t\0" + /* 8949 */ "shra_r.w\t\0" + /* 8959 */ "subqh_r.w\t\0" + /* 8970 */ "addqh_r.w\t\0" + /* 8981 */ "extr_r.w\t\0" + /* 8991 */ "shrav_r.w\t\0" + /* 9002 */ "extrv_r.w\t\0" + /* 9013 */ "srar.w\t\0" + /* 9021 */ "bclr.w\t\0" + /* 9029 */ "srlr.w\t\0" + /* 9037 */ "fcor.w\t\0" + /* 9045 */ "fsor.w\t\0" + /* 9053 */ "fexupr.w\t\0" + /* 9063 */ "ffqr.w\t\0" + /* 9071 */ "binsr.w\t\0" + /* 9080 */ "extr.w\t\0" + /* 9088 */ "ilvr.w\t\0" + /* 9096 */ "cvt.s.w\t\0" + /* 9105 */ "asub_s.w\t\0" + /* 9115 */ "hsub_s.w\t\0" + /* 9125 */ "dpsub_s.w\t\0" + /* 9136 */ "ftrunc_s.w\t\0" + /* 9148 */ "hadd_s.w\t\0" + /* 9158 */ "dpadd_s.w\t\0" + /* 9169 */ "mod_s.w\t\0" + /* 9178 */ "cle_s.w\t\0" + /* 9187 */ "ave_s.w\t\0" + /* 9196 */ "clei_s.w\t\0" + /* 9206 */ "mini_s.w\t\0" + /* 9216 */ "clti_s.w\t\0" + /* 9226 */ "maxi_s.w\t\0" + /* 9236 */ "shll_s.w\t\0" + /* 9246 */ "min_s.w\t\0" + /* 9255 */ "dotp_s.w\t\0" + /* 9265 */ "subq_s.w\t\0" + /* 9275 */ "addq_s.w\t\0" + /* 9285 */ "mulq_s.w\t\0" + /* 9295 */ "absq_s.w\t\0" + /* 9305 */ "aver_s.w\t\0" + /* 9315 */ "subs_s.w\t\0" + /* 9325 */ "adds_s.w\t\0" + /* 9335 */ "sat_s.w\t\0" + /* 9344 */ "clt_s.w\t\0" + /* 9353 */ "ffint_s.w\t\0" + /* 9364 */ "ftint_s.w\t\0" + /* 9375 */ "subsuu_s.w\t\0" + /* 9387 */ "div_s.w\t\0" + /* 9396 */ "shllv_s.w\t\0" + /* 9407 */ "max_s.w\t\0" + /* 9416 */ "copy_s.w\t\0" + /* 9426 */ "mulq_rs.w\t\0" + /* 9437 */ "extr_rs.w\t\0" + /* 9448 */ "extrv_rs.w\t\0" + /* 9460 */ "fclass.w\t\0" + /* 9470 */ "splat.w\t\0" + /* 9479 */ "bset.w\t\0" + /* 9487 */ "fclt.w\t\0" + /* 9495 */ "fslt.w\t\0" + /* 9503 */ "fcult.w\t\0" + /* 9512 */ "fsult.w\t\0" + /* 9521 */ "pcnt.w\t\0" + /* 9529 */ "frint.w\t\0" + /* 9538 */ "insert.w\t\0" + /* 9548 */ "fsqrt.w\t\0" + /* 9557 */ "frsqrt.w\t\0" + /* 9567 */ "st.w\t\0" + /* 9573 */ "asub_u.w\t\0" + /* 9583 */ "hsub_u.w\t\0" + /* 9593 */ "dpsub_u.w\t\0" + /* 9604 */ "ftrunc_u.w\t\0" + /* 9616 */ "hadd_u.w\t\0" + /* 9626 */ "dpadd_u.w\t\0" + /* 9637 */ "mod_u.w\t\0" + /* 9646 */ "cle_u.w\t\0" + /* 9655 */ "ave_u.w\t\0" + /* 9664 */ "clei_u.w\t\0" + /* 9674 */ "mini_u.w\t\0" + /* 9684 */ "clti_u.w\t\0" + /* 9694 */ "maxi_u.w\t\0" + /* 9704 */ "min_u.w\t\0" + /* 9713 */ "dotp_u.w\t\0" + /* 9723 */ "aver_u.w\t\0" + /* 9733 */ "subs_u.w\t\0" + /* 9743 */ "adds_u.w\t\0" + /* 9753 */ "subsus_u.w\t\0" + /* 9765 */ "sat_u.w\t\0" + /* 9774 */ "clt_u.w\t\0" + /* 9783 */ "ffint_u.w\t\0" + /* 9794 */ "ftint_u.w\t\0" + /* 9805 */ "div_u.w\t\0" + /* 9814 */ "max_u.w\t\0" + /* 9823 */ "copy_u.w\t\0" + /* 9833 */ "msubv.w\t\0" + /* 9842 */ "maddv.w\t\0" + /* 9851 */ "pckev.w\t\0" + /* 9860 */ "ilvev.w\t\0" + /* 9869 */ "fdiv.w\t\0" + /* 9877 */ "mulv.w\t\0" + /* 9885 */ "extrv.w\t\0" + /* 9894 */ "fmax.w\t\0" + /* 9902 */ "bz.w\t\0" + /* 9908 */ "bnz.w\t\0" + /* 9915 */ "crc32w\t\0" + /* 9923 */ "crc32cw\t\0" + /* 9932 */ "ulw\t\0" + /* 9937 */ "cvt.ps.pw\t\0" + /* 9948 */ "usw\t\0" + /* 9953 */ "prefx\t\0" + /* 9960 */ "lhx\t\0" + /* 9965 */ "jalx\t\0" + /* 9971 */ "lbux\t\0" + /* 9977 */ "lwx\t\0" + /* 9982 */ "bgez\t\0" + /* 9988 */ "blez\t\0" + /* 9994 */ "bnez\t\0" + /* 10000 */ "selnez\t\0" + /* 10008 */ "btnez\t\0" + /* 10015 */ "dclz\t\0" + /* 10021 */ "beqz\t\0" + /* 10027 */ "seleqz\t\0" + /* 10035 */ "bteqz\t\0" + /* 10042 */ "bgtz\t\0" + /* 10048 */ "bltz\t\0" + /* 10054 */ "movz\t\0" + /* 10060 */ "seb\t \0" + /* 10066 */ "seh\t \0" + /* 10072 */ "ddivu\t$zero, \0" + /* 10086 */ "ddiv\t$zero, \0" + /* 10099 */ "addiu\t$sp, \0" + /* 10111 */ "mftc0 \0" + /* 10118 */ "mttc0 \0" + /* 10125 */ "mfthc1 \0" + /* 10133 */ "mtthc1 \0" + /* 10141 */ "cftc1 \0" + /* 10148 */ "mftc1 \0" + /* 10155 */ "cttc1 \0" + /* 10162 */ "mttc1 \0" + /* 10169 */ "sync \0" + /* 10175 */ "ld \0" + /* 10179 */ "\t.word \0" + /* 10187 */ "sd \0" + /* 10191 */ "sne \0" + /* 10196 */ "mfthi \0" + /* 10203 */ "mtthi \0" + /* 10210 */ "mftlo \0" + /* 10217 */ "mttlo \0" + /* 10224 */ "mftdsp \0" + /* 10232 */ "mttdsp \0" + /* 10240 */ "seq \0" + /* 10245 */ "mftgpr \0" + /* 10253 */ "mttgpr \0" + /* 10261 */ "dext \0" + /* 10267 */ "mftacx \0" + /* 10275 */ "mttacx \0" + /* 10283 */ "bc1nez \0" + /* 10291 */ "bc2nez \0" + /* 10299 */ "bc1eqz \0" + /* 10307 */ "bc2eqz \0" + /* 10315 */ "# XRay Function Patchable RET.\0" + /* 10346 */ "c.\0" + /* 10349 */ "# XRay Typed Event Log.\0" + /* 10373 */ "# XRay Custom Event Log.\0" + /* 10398 */ "# XRay Function Enter.\0" + /* 10421 */ "# XRay Tail Call Exit.\0" + /* 10444 */ "# XRay Function Exit.\0" + /* 10466 */ "break 0\0" + /* 10474 */ "LIFETIME_END\0" + /* 10487 */ "PSEUDO_PROBE\0" + /* 10500 */ "BUNDLE\0" + /* 10507 */ "DBG_VALUE\0" + /* 10517 */ "DBG_INSTR_REF\0" + /* 10531 */ "DBG_PHI\0" + /* 10539 */ "DBG_LABEL\0" + /* 10549 */ "LIFETIME_START\0" + /* 10564 */ "DBG_VALUE_LIST\0" + /* 10579 */ "jrc\t$ra\0" + /* 10587 */ "jr\t$ra\0" + /* 10594 */ "ehb\0" + /* 10598 */ "eretnc\0" + /* 10605 */ "pause\0" + /* 10611 */ "tlbinvf\0" + /* 10619 */ "tlbginvf\0" + /* 10628 */ "tlbwi\0" + /* 10634 */ "tlbgwi\0" + /* 10641 */ "# FEntry call\0" + /* 10655 */ "foo\0" + /* 10659 */ "tlbp\0" + /* 10664 */ "tlbgp\0" + /* 10670 */ "ssnop\0" + /* 10676 */ "tlbr\0" + /* 10681 */ "tlbgr\0" + /* 10687 */ "tlbwr\0" + /* 10693 */ "tlbgwr\0" + /* 10700 */ "deret\0" + /* 10706 */ "wait\0" + /* 10711 */ "tlbinv\0" + /* 10718 */ "tlbginv\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 10508U, // DBG_VALUE + 10565U, // DBG_VALUE_LIST + 10518U, // DBG_INSTR_REF + 10532U, // DBG_PHI + 10540U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 10501U, // BUNDLE + 10550U, // LIFETIME_START + 10475U, // LIFETIME_END + 10488U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 10642U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 10399U, // PATCHABLE_FUNCTION_ENTER + 10316U, // PATCHABLE_RET + 10445U, // PATCHABLE_FUNCTION_EXIT + 10422U, // PATCHABLE_TAIL_CALL + 10374U, // PATCHABLE_EVENT_CALL + 10350U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 24020U, // ABSMacro + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I16_POSTRA + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I32_POSTRA + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I64_POSTRA + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_CMP_SWAP_I8_POSTRA + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I16_POSTRA + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I32_POSTRA + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I64_POSTRA + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_ADD_I8_POSTRA + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I16_POSTRA + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I32_POSTRA + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I64_POSTRA + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_AND_I8_POSTRA + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I16_POSTRA + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I32_POSTRA + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I64_POSTRA + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MAX_I8_POSTRA + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I16_POSTRA + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I32_POSTRA + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I64_POSTRA + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_MIN_I8_POSTRA + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I16_POSTRA + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I32_POSTRA + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I64_POSTRA + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_NAND_I8_POSTRA + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I16_POSTRA + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I32_POSTRA + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I64_POSTRA + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_OR_I8_POSTRA + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I16_POSTRA + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I32_POSTRA + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I64_POSTRA + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_SUB_I8_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I16_POSTRA + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I32_POSTRA + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I64_POSTRA + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_LOAD_XOR_I8_POSTRA + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I16_POSTRA + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I32_POSTRA + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I64_POSTRA + 0U, // ATOMIC_SWAP_I8 + 0U, // ATOMIC_SWAP_I8_POSTRA + 0U, // B + 0U, // BAL_BR + 0U, // BAL_BR_MM + 268458245U, // BEQLImmMacro + 268456065U, // BGE + 268456065U, // BGEImmMacro + 268458092U, // BGEL + 268458092U, // BGELImmMacro + 268459764U, // BGEU + 268459764U, // BGEUImmMacro + 268458290U, // BGEUL + 268458290U, // BGEULImmMacro + 268459645U, // BGT + 268459645U, // BGTImmMacro + 268458278U, // BGTL + 268458278U, // BGTLImmMacro + 268459890U, // BGTU + 268459890U, // BGTUImmMacro + 268458310U, // BGTUL + 268458310U, // BGTULImmMacro + 268456105U, // BLE + 268456105U, // BLEImmMacro + 268458098U, // BLEL + 268458098U, // BLELImmMacro + 268459782U, // BLEU + 268459782U, // BLEUImmMacro + 268458297U, // BLEUL + 268458297U, // BLEULImmMacro + 268459661U, // BLT + 268459661U, // BLTImmMacro + 268458284U, // BLTL + 268458284U, // BLTLImmMacro + 268459902U, // BLTU + 268459902U, // BLTUImmMacro + 268458317U, // BLTUL + 268458317U, // BLTULImmMacro + 268458104U, // BNELImmMacro + 0U, // BPOSGE32_PSEUDO + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 0U, // BSEL_W_PSEUDO + 0U, // B_MM + 279279U, // B_MMR6_Pseudo + 279279U, // B_MM_Pseudo + 268458610U, // BeqImm + 268456132U, // BneImm + 536893942U, // BteqzT8CmpX16 + 536893347U, // BteqzT8CmpiX16 + 536895122U, // BteqzT8SltX16 + 536893377U, // BteqzT8SltiX16 + 536895278U, // BteqzT8SltiuX16 + 536895364U, // BteqzT8SltuX16 + 805329398U, // BtnezT8CmpX16 + 805328803U, // BtnezT8CmpiX16 + 805330578U, // BtnezT8SltX16 + 805328833U, // BtnezT8SltiX16 + 805330734U, // BtnezT8SltiuX16 + 805330820U, // BtnezT8SltuX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 26526U, // CFTC1 + 10656U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 8955820U, // CTTC1 + 288708U, // Constant32 + 268458304U, // DMULImmMacro + 268458304U, // DMULMacro + 268458439U, // DMULOMacro + 268459865U, // DMULOUMacro + 268458229U, // DROL + 268458229U, // DROLImm + 268458777U, // DROR + 268458777U, // DRORImm + 268460027U, // DSDivIMacro + 268460027U, // DSDivMacro + 268458362U, // DSRemIMacro + 268458362U, // DSRemMacro + 268459935U, // DUDivIMacro + 268459935U, // DUDivMacro + 268459858U, // DURemIMacro + 268459858U, // DURemMacro + 0U, // ERet + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 0U, // FABS_W + 0U, // FEXP2_D_1_PSEUDO + 0U, // FEXP2_W_1_PSEUDO + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 1090541466U, // GotPrologue16 + 0U, // INSERT_B_VIDX64_PSEUDO + 0U, // INSERT_B_VIDX_PSEUDO + 0U, // INSERT_D_VIDX64_PSEUDO + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX64_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX64_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 0U, // INSERT_H_VIDX64_PSEUDO + 0U, // INSERT_H_VIDX_PSEUDO + 0U, // INSERT_W_VIDX64_PSEUDO + 0U, // INSERT_W_VIDX_PSEUDO + 0U, // JALR64Pseudo + 0U, // JALRHB64Pseudo + 0U, // JALRHBPseudo + 0U, // JALRPseudo + 0U, // JAL_MMR6 + 284678U, // JalOneReg + 22534U, // JalTwoReg + 25192384U, // LDMacro + 0U, // LDR_D + 0U, // LDR_W + 0U, // LD_F16 + 25182214U, // LOAD_ACC128 + 25182214U, // LOAD_ACC64 + 25182214U, // LOAD_ACC64DSP + 25188876U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_ADDiu2Op + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_DADDiu2Op + 0U, // LONG_BRANCH_LUi + 0U, // LONG_BRANCH_LUi2Op + 0U, // LONG_BRANCH_LUi2Op_64 + 55694U, // LWM_MM + 17042U, // LoadAddrImm32 + 17063U, // LoadAddrImm64 + 25182866U, // LoadAddrReg32 + 25182887U, // LoadAddrReg64 + 22426U, // LoadImm32 + 22430U, // LoadImm64 + 19107U, // LoadImmDoubleFGR + 19107U, // LoadImmDoubleFGR_32 + 19107U, // LoadImmDoubleGPR + 23585U, // LoadImmSingleFGR + 23585U, // LoadImmSingleGPR + 812750U, // LwConstant32 + 26652U, // MFTACX + 268461952U, // MFTC0 + 26533U, // MFTC1 + 288753U, // MFTDSP + 26630U, // MFTGPR + 26510U, // MFTHC1 + 26581U, // MFTHI + 26595U, // MFTLO + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 0U, // MSA_FP_EXTEND_D_PSEUDO + 0U, // MSA_FP_EXTEND_W_PSEUDO + 0U, // MSA_FP_ROUND_D_PSEUDO + 0U, // MSA_FP_ROUND_W_PSEUDO + 8955940U, // MTTACX + 1376298887U, // MTTC0 + 8955827U, // MTTC1 + 288761U, // MTTDSP + 8955918U, // MTTGPR + 8955798U, // MTTHC1 + 8955868U, // MTTHI + 8955882U, // MTTLO + 268458305U, // MULImmMacro + 268458440U, // MULOMacro + 268459866U, // MULOUMacro + 24221U, // MultRxRy16 + 43032221U, // MultRxRyRz16 + 24465U, // MultuRxRy16 + 43032465U, // MultuRxRyRz16 + 0U, // NOP + 268458772U, // NORImm + 268458772U, // NORImm64 + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 16390U, // PseudoCVT_D32_W + 16390U, // PseudoCVT_D64_L + 16390U, // PseudoCVT_D64_W + 16390U, // PseudoCVT_S_L + 16390U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoD_SELECT_I + 0U, // PseudoD_SELECT_I64 + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoIndirectBranch64R6 + 0U, // PseudoIndirectBranchR6 + 0U, // PseudoIndirectBranch_MM + 0U, // PseudoIndirectBranch_MMR6 + 0U, // PseudoIndirectHazardBranch + 0U, // PseudoIndirectHazardBranch64 + 0U, // PseudoIndrectHazardBranch64R6 + 0U, // PseudoIndrectHazardBranchR6 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMADDU_MM + 0U, // PseudoMADD_MM + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFHI_MM + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMFLO_MM + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMSUBU_MM + 0U, // PseudoMSUB_MM + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMTLOHI_MM + 0U, // PseudoMULT + 0U, // PseudoMULT_MM + 0U, // PseudoMULTu + 0U, // PseudoMULTu_MM + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 268455844U, // PseudoTRUNC_W_D + 268455844U, // PseudoTRUNC_W_D32 + 268459389U, // PseudoTRUNC_W_S + 0U, // PseudoUDIV + 268458230U, // ROL + 268458230U, // ROLImm + 268458778U, // ROR + 268458778U, // RORImm + 0U, // RetRA + 0U, // RetRA16 + 25185431U, // SDC1_M1 + 0U, // SDIV_MM_Pseudo + 25192396U, // SDMacro + 268460028U, // SDivIMacro + 268460028U, // SDivMacro + 268462081U, // SEQIMacro + 268462081U, // SEQMacro + 268456070U, // SGE + 268456070U, // SGEImm + 268456070U, // SGEImm64 + 268459770U, // SGEU + 268459770U, // SGEUImm + 268459770U, // SGEUImm64 + 268459650U, // SGTImm + 268459650U, // SGTImm64 + 268459896U, // SGTUImm + 268459896U, // SGTUImm64 + 268456115U, // SLE + 268456115U, // SLEImm + 268456115U, // SLEImm64 + 268459788U, // SLEU + 268459788U, // SLEUImm + 268459788U, // SLEUImm64 + 268459666U, // SLTImm64 + 268459908U, // SLTUImm64 + 268462032U, // SNEIMacro + 268462032U, // SNEMacro + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 268458363U, // SRemIMacro + 268458363U, // SRemMacro + 25182214U, // STORE_ACC128 + 25182214U, // STORE_ACC64 + 25182214U, // STORE_ACC64DSP + 25188892U, // STORE_CCOND_DSP + 0U, // STR_D + 0U, // STR_W + 0U, // ST_F16 + 55699U, // SWM_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 25182849U, // SaaAddr + 25186321U, // SaadAddr + 1386278U, // SelBeqZ + 1386251U, // SelBneZ + 1661016566U, // SelTBteqZCmp + 1661015971U, // SelTBteqZCmpi + 1661017746U, // SelTBteqZSlt + 1661016001U, // SelTBteqZSlti + 1661017902U, // SelTBteqZSltiu + 1661017988U, // SelTBteqZSltu + 1929452022U, // SelTBtneZCmp + 1929451427U, // SelTBtneZCmpi + 1929453202U, // SelTBtneZSlt + 1929451457U, // SelTBtneZSlti + 1929453358U, // SelTBtneZSltiu + 1929453444U, // SelTBtneZSltu + 59809426U, // SltCCRxRy16 + 59807681U, // SltiCCRxImmX16 + 59809582U, // SltiuCCRxImmX16 + 59809668U, // SltuCCRxRy16 + 59809668U, // SltuRxRyRz16 + 0U, // TAILCALL + 0U, // TAILCALL64R6REG + 0U, // TAILCALLHB64R6REG + 0U, // TAILCALLHBR6REG + 0U, // TAILCALLR6REG + 0U, // TAILCALLREG + 0U, // TAILCALLREG64 + 0U, // TAILCALLREGHB + 0U, // TAILCALLREGHB64 + 0U, // TAILCALLREG_MM + 0U, // TAILCALLREG_MMR6 + 0U, // TAILCALL_MM + 0U, // TAILCALL_MMR6 + 0U, // TRAP + 0U, // TRAP_MM + 0U, // UDIV_MM_Pseudo + 268459936U, // UDivIMacro + 268459936U, // UDivMacro + 268459859U, // URemIMacro + 268459859U, // URemMacro + 25187620U, // Ulh + 25190162U, // Ulhu + 25192141U, // Ulw + 25188173U, // Ush + 25192157U, // Usw + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 22070U, // ABSQ_S_PH + 22070U, // ABSQ_S_PH_MM + 18197U, // ABSQ_S_QB + 18197U, // ABSQ_S_QB_MMR2 + 25680U, // ABSQ_S_W + 25680U, // ABSQ_S_W_MM + 268455974U, // ADD + 18483U, // ADDIUPC + 18483U, // ADDIUPC_MM + 18483U, // ADDIUPC_MMR6 + 23041U, // ADDIUR1SP_MM + 268452218U, // ADDIUR2_MM + 9470363U, // ADDIUS5_MM + 285246U, // ADDIUSP_MM + 268459808U, // ADDIU_MMR6 + 268457331U, // ADDQH_PH + 268457331U, // ADDQH_PH_MMR2 + 268457448U, // ADDQH_R_PH + 268457448U, // ADDQH_R_PH_MMR2 + 268460811U, // ADDQH_R_W + 268460811U, // ADDQH_R_W_MMR2 + 268460414U, // ADDQH_W + 268460414U, // ADDQH_W_MMR2 + 268457405U, // ADDQ_PH + 268457405U, // ADDQ_PH_MM + 268457504U, // ADDQ_S_PH + 268457504U, // ADDQ_S_PH_MM + 268461116U, // ADDQ_S_W + 268461116U, // ADDQ_S_W_MM + 268459557U, // ADDR_PS64 + 268453979U, // ADDSC + 268453979U, // ADDSC_MM + 268452603U, // ADDS_A_B + 268454140U, // ADDS_A_D + 268456258U, // ADDS_A_H + 268460122U, // ADDS_A_W + 268453071U, // ADDS_S_B + 268455238U, // ADDS_S_D + 268456815U, // ADDS_S_H + 268461166U, // ADDS_S_W + 268453286U, // ADDS_U_B + 268455705U, // ADDS_U_D + 268457093U, // ADDS_U_H + 268461584U, // ADDS_U_W + 268452438U, // ADDU16_MM + 268452438U, // ADDU16_MMR6 + 268453521U, // ADDUH_QB + 268453521U, // ADDUH_QB_MMR2 + 268453629U, // ADDUH_R_QB + 268453629U, // ADDUH_R_QB_MMR2 + 268459737U, // ADDU_MMR6 + 268457603U, // ADDU_PH + 268457603U, // ADDU_PH_MMR2 + 268453734U, // ADDU_QB + 268453734U, // ADDU_QB_MM + 268457548U, // ADDU_S_PH + 268457548U, // ADDU_S_PH_MMR2 + 268453675U, // ADDU_S_QB + 268453675U, // ADDU_S_QB_MM + 268452852U, // ADDVI_B + 268454660U, // ADDVI_D + 268456474U, // ADDVI_H + 268460547U, // ADDVI_W + 268453364U, // ADDV_B + 268455795U, // ADDV_D + 268457171U, // ADDV_H + 268461684U, // ADDV_W + 268454018U, // ADDWC + 268454018U, // ADDWC_MM + 268452585U, // ADD_A_B + 268454121U, // ADD_A_D + 268456240U, // ADD_A_H + 268460103U, // ADD_A_W + 268455974U, // ADD_MM + 268455974U, // ADD_MMR6 + 268457824U, // ADDi + 268457824U, // ADDi_MM + 268459808U, // ADDiu + 268459808U, // ADDiu_MM + 268459737U, // ADDu + 268459737U, // ADDu_MM + 268458393U, // ALIGN + 268458393U, // ALIGN_MMR6 + 18475U, // ALUIPC + 18475U, // ALUIPC_MMR6 + 268456003U, // AND + 10043849U, // AND16_MM + 10043849U, // AND16_MMR6 + 268456003U, // AND64 + 268452318U, // ANDI16_MM + 268452318U, // ANDI16_MMR6 + 268452711U, // ANDI_B + 268457830U, // ANDI_MMR6 + 268456003U, // AND_MM + 268456003U, // AND_MMR6 + 268459947U, // AND_V + 268457830U, // ANDi + 268457830U, // ANDi64 + 268457830U, // ANDi_MM + 268456017U, // APPEND + 268456017U, // APPEND_MMR2 + 268452965U, // ASUB_S_B + 268455068U, // ASUB_S_D + 268456647U, // ASUB_S_H + 268460946U, // ASUB_S_W + 268453180U, // ASUB_U_B + 268455535U, // ASUB_U_D + 268456935U, // ASUB_U_H + 268461414U, // ASUB_U_W + 268457934U, // AUI + 18468U, // AUIPC + 18468U, // AUIPC_MMR6 + 268457934U, // AUI_MMR6 + 268453051U, // AVER_S_B + 268455218U, // AVER_S_D + 268456785U, // AVER_S_H + 268461146U, // AVER_S_W + 268453266U, // AVER_U_B + 268455685U, // AVER_U_D + 268457073U, // AVER_U_H + 268461564U, // AVER_U_W + 268452993U, // AVE_S_B + 268455150U, // AVE_S_D + 268456717U, // AVE_S_H + 268461028U, // AVE_S_W + 268453208U, // AVE_U_B + 268455617U, // AVE_U_D + 268457005U, // AVE_U_H + 268461496U, // AVE_U_W + 24352U, // AddiuRxImmX16 + 1859360U, // AddiuRxPcImmX16 + 2164285216U, // AddiuRxRxImm16 + 16801568U, // AddiuRxRxImmX16 + 67133216U, // AddiuRxRyOffMemX16 + 2123636U, // AddiuSpImm16 + 288628U, // AddiuSpImmX16 + 268459737U, // AdduRxRyRz16 + 16797763U, // AndRxRxRy16 + 278949U, // B16_MM + 268459736U, // BADDu + 284673U, // BAL + 280533U, // BALC + 280533U, // BALC_MMR6 + 268458392U, // BALIGN + 268458392U, // BALIGN_MMR2 + 75513935U, // BBIT0 + 75514067U, // BBIT032 + 75514060U, // BBIT1 + 75514076U, // BBIT132 + 280512U, // BC + 282887U, // BC0F + 286309U, // BC0T + 278954U, // BC16_MMR6 + 26684U, // BC1EQZ + 18608U, // BC1EQZC_MMR6 + 20749U, // BC1F + 22654U, // BC1FL + 20749U, // BC1F_MM + 26668U, // BC1NEZ + 18583U, // BC1NEZC_MMR6 + 24171U, // BC1T + 22801U, // BC1TL + 24171U, // BC1T_MM + 26692U, // BC2EQZ + 18617U, // BC2EQZC_MMR6 + 20755U, // BC2F + 22661U, // BC2FL + 26676U, // BC2NEZ + 18592U, // BC2NEZC_MMR6 + 24177U, // BC2T + 22808U, // BC2TL + 20761U, // BC3F + 22668U, // BC3FL + 24183U, // BC3T + 22815U, // BC3TL + 268452780U, // BCLRI_B + 268454604U, // BCLRI_D + 268456418U, // BCLRI_H + 268460491U, // BCLRI_W + 268452932U, // BCLR_B + 268454992U, // BCLR_D + 268456614U, // BCLR_H + 268460862U, // BCLR_W + 280512U, // BC_MMR6 + 268458610U, // BEQ + 268458610U, // BEQ64 + 268453961U, // BEQC + 268453961U, // BEQC64 + 268453961U, // BEQC_MMR6 + 268458245U, // BEQL + 17017U, // BEQZ16_MM + 18429U, // BEQZALC + 18429U, // BEQZALC_MMR6 + 18626U, // BEQZC + 16832U, // BEQZC16_MMR6 + 18626U, // BEQZC64 + 18626U, // BEQZC_MM + 18626U, // BEQZC_MMR6 + 268458610U, // BEQ_MM + 268453828U, // BGEC + 268453828U, // BGEC64 + 268453828U, // BGEC_MMR6 + 268453992U, // BGEUC + 268453992U, // BGEUC64 + 268453992U, // BGEUC_MMR6 + 26367U, // BGEZ + 26367U, // BGEZ64 + 22539U, // BGEZAL + 18402U, // BGEZALC + 18402U, // BGEZALC_MMR6 + 22749U, // BGEZALL + 24031U, // BGEZALS_MM + 22539U, // BGEZAL_MM + 18569U, // BGEZC + 18569U, // BGEZC64 + 18569U, // BGEZC_MMR6 + 22878U, // BGEZL + 26367U, // BGEZ_MM + 26427U, // BGTZ + 26427U, // BGTZ64 + 18438U, // BGTZALC + 18438U, // BGTZALC_MMR6 + 18633U, // BGTZC + 18633U, // BGTZC64 + 18633U, // BGTZC_MMR6 + 22892U, // BGTZL + 26427U, // BGTZ_MM + 285229969U, // BINSLI_B + 285231793U, // BINSLI_D + 285233607U, // BINSLI_H + 285237680U, // BINSLI_W + 285230116U, // BINSL_B + 285231993U, // BINSL_D + 285233721U, // BINSL_H + 285237838U, // BINSL_W + 285230030U, // BINSRI_B + 285231838U, // BINSRI_D + 285233652U, // BINSRI_H + 285237725U, // BINSRI_W + 285230164U, // BINSR_B + 285232258U, // BINSR_D + 285233846U, // BINSR_H + 285238128U, // BINSR_W + 24563U, // BITREV + 24563U, // BITREV_MM + 22991U, // BITSWAP + 22991U, // BITSWAP_MMR6 + 26373U, // BLEZ + 26373U, // BLEZ64 + 18411U, // BLEZALC + 18411U, // BLEZALC_MMR6 + 18576U, // BLEZC + 18576U, // BLEZC64 + 18576U, // BLEZC_MMR6 + 22885U, // BLEZL + 26373U, // BLEZ_MM + 268453986U, // BLTC + 268453986U, // BLTC64 + 268453986U, // BLTC_MMR6 + 268453999U, // BLTUC + 268453999U, // BLTUC64 + 268453999U, // BLTUC_MMR6 + 26433U, // BLTZ + 26433U, // BLTZ64 + 22547U, // BLTZAL + 18447U, // BLTZALC + 18447U, // BLTZALC_MMR6 + 22758U, // BLTZALL + 24040U, // BLTZALS_MM + 22547U, // BLTZAL_MM + 18640U, // BLTZC + 18640U, // BLTZC64 + 18640U, // BLTZC_MMR6 + 22899U, // BLTZL + 26433U, // BLTZ_MM + 285230085U, // BMNZI_B + 285237220U, // BMNZ_V + 285230077U, // BMZI_B + 285237206U, // BMZ_V + 268456132U, // BNE + 268456132U, // BNE64 + 268453834U, // BNEC + 268453834U, // BNEC64 + 268453834U, // BNEC_MMR6 + 268452719U, // BNEGI_B + 268454552U, // BNEGI_D + 268456366U, // BNEGI_H + 268460439U, // BNEGI_W + 268452687U, // BNEG_B + 268454528U, // BNEG_D + 268456342U, // BNEG_H + 268460334U, // BNEG_W + 268458104U, // BNEL + 17009U, // BNEZ16_MM + 18420U, // BNEZALC + 18420U, // BNEZALC_MMR6 + 18601U, // BNEZC + 16823U, // BNEZC16_MMR6 + 18601U, // BNEZC64 + 18601U, // BNEZC_MM + 18601U, // BNEZC_MMR6 + 268456132U, // BNE_MM + 268454006U, // BNVC + 268454006U, // BNVC_MMR6 + 17948U, // BNZ_B + 20464U, // BNZ_D + 21755U, // BNZ_H + 24541U, // BNZ_V + 26293U, // BNZ_W + 268454012U, // BOVC + 268454012U, // BOVC_MMR6 + 278765U, // BPOSGE32 + 280501U, // BPOSGE32C_MMR3 + 278765U, // BPOSGE32_MM + 83990498U, // BREAK + 115188U, // BREAK16_MM + 115188U, // BREAK16_MMR6 + 83990498U, // BREAK_MM + 83990498U, // BREAK_MMR6 + 285229944U, // BSELI_B + 285237178U, // BSEL_V + 268452834U, // BSETI_B + 268454642U, // BSETI_D + 268456456U, // BSETI_H + 268460529U, // BSETI_W + 268453148U, // BSET_B + 268455354U, // BSET_D + 268456903U, // BSET_H + 268461320U, // BSET_W + 17942U, // BZ_B + 20448U, // BZ_D + 21749U, // BZ_H + 24528U, // BZ_V + 26287U, // BZ_W + 2415945510U, // BeqzRxImm16 + 26406U, // BeqzRxImmX16 + 2114287U, // Bimm16 + 279279U, // BimmX16 + 2415945483U, // BnezRxImm16 + 26379U, // BnezRxImmX16 + 10467U, // Break16 + 2385716U, // Bteqz16 + 288564U, // BteqzX16 + 2385689U, // Btnez16 + 288537U, // BtnezX16 + 2756752U, // CACHE + 2756722U, // CACHEE + 2756722U, // CACHEE_MM + 2756752U, // CACHE_MM + 2756752U, // CACHE_MMR6 + 2756752U, // CACHE_R6 + 19235U, // CEIL_L_D64 + 19235U, // CEIL_L_D_MMR6 + 23613U, // CEIL_L_S + 23613U, // CEIL_L_S_MMR6 + 20410U, // CEIL_W_D32 + 20410U, // CEIL_W_D64 + 20410U, // CEIL_W_D_MMR6 + 20410U, // CEIL_W_MM + 23955U, // CEIL_W_S + 23955U, // CEIL_W_S_MM + 23955U, // CEIL_W_S_MMR6 + 268452763U, // CEQI_B + 268454587U, // CEQI_D + 268456401U, // CEQI_H + 268460474U, // CEQI_W + 268452917U, // CEQ_B + 268454899U, // CEQ_D + 268456592U, // CEQ_H + 268460750U, // CEQ_W + 16482U, // CFC1 + 16482U, // CFC1_MM + 16698U, // CFC2_MM + 17113U, // CFCMSA + 268459505U, // CINS + 268452126U, // CINS32 + 268459505U, // CINS64_32 + 268459505U, // CINS_i32 + 19880U, // CLASS_D + 19880U, // CLASS_D_MMR6 + 23806U, // CLASS_S + 23806U, // CLASS_S_MMR6 + 268453002U, // CLEI_S_B + 268455159U, // CLEI_S_D + 268456726U, // CLEI_S_H + 268461037U, // CLEI_S_W + 268453217U, // CLEI_U_B + 268455626U, // CLEI_U_D + 268457014U, // CLEI_U_H + 268461505U, // CLEI_U_W + 268452984U, // CLE_S_B + 268455141U, // CLE_S_D + 268456708U, // CLE_S_H + 268461019U, // CLE_S_W + 268453199U, // CLE_U_B + 268455608U, // CLE_U_D + 268456996U, // CLE_U_H + 268461487U, // CLE_U_W + 22959U, // CLO + 22959U, // CLO_MM + 22959U, // CLO_MMR6 + 22959U, // CLO_R6 + 268453022U, // CLTI_S_B + 268455179U, // CLTI_S_D + 268456746U, // CLTI_S_H + 268461057U, // CLTI_S_W + 268453237U, // CLTI_U_B + 268455646U, // CLTI_U_D + 268457034U, // CLTI_U_H + 268461525U, // CLTI_U_W + 268453090U, // CLT_S_B + 268455257U, // CLT_S_D + 268456834U, // CLT_S_H + 268461185U, // CLT_S_W + 268453317U, // CLT_U_B + 268455736U, // CLT_U_D + 268457124U, // CLT_U_H + 268461615U, // CLT_U_W + 26401U, // CLZ + 26401U, // CLZ_MM + 26401U, // CLZ_MMR6 + 26401U, // CLZ_R6 + 268453567U, // CMPGDU_EQ_QB + 268453567U, // CMPGDU_EQ_QB_MMR2 + 268453472U, // CMPGDU_LE_QB + 268453472U, // CMPGDU_LE_QB_MMR2 + 268453686U, // CMPGDU_LT_QB + 268453686U, // CMPGDU_LT_QB_MMR2 + 268453581U, // CMPGU_EQ_QB + 268453581U, // CMPGU_EQ_QB_MM + 268453486U, // CMPGU_LE_QB + 268453486U, // CMPGU_LE_QB_MM + 268453700U, // CMPGU_LT_QB + 268453700U, // CMPGU_LT_QB_MM + 18138U, // CMPU_EQ_QB + 18138U, // CMPU_EQ_QB_MM + 18043U, // CMPU_LE_QB + 18043U, // CMPU_LE_QB_MM + 18257U, // CMPU_LT_QB + 18257U, // CMPU_LT_QB_MM + 268454449U, // CMP_AF_D_MMR6 + 268458979U, // CMP_AF_S_MMR6 + 268454888U, // CMP_EQ_D + 268454888U, // CMP_EQ_D_MMR6 + 21958U, // CMP_EQ_PH + 21958U, // CMP_EQ_PH_MM + 268459183U, // CMP_EQ_S + 268459183U, // CMP_EQ_S_MMR6 + 268454449U, // CMP_F_D + 268458979U, // CMP_F_S + 268454293U, // CMP_LE_D + 268454293U, // CMP_LE_D_MMR6 + 21854U, // CMP_LE_PH + 21854U, // CMP_LE_PH_MM + 268458900U, // CMP_LE_S + 268458900U, // CMP_LE_S_MMR6 + 268455379U, // CMP_LT_D + 268455379U, // CMP_LT_D_MMR6 + 22127U, // CMP_LT_PH + 22127U, // CMP_LT_PH_MM + 268459288U, // CMP_LT_S + 268459288U, // CMP_LT_S_MMR6 + 268454467U, // CMP_SAF_D + 268454467U, // CMP_SAF_D_MMR6 + 268458989U, // CMP_SAF_S + 268458989U, // CMP_SAF_S_MMR6 + 268454915U, // CMP_SEQ_D + 268454915U, // CMP_SEQ_D_MMR6 + 268459202U, // CMP_SEQ_S + 268459202U, // CMP_SEQ_S_MMR6 + 268454330U, // CMP_SLE_D + 268454330U, // CMP_SLE_D_MMR6 + 268458929U, // CMP_SLE_S + 268458929U, // CMP_SLE_S_MMR6 + 268455406U, // CMP_SLT_D + 268455406U, // CMP_SLT_D_MMR6 + 268459307U, // CMP_SLT_S + 268459307U, // CMP_SLT_S_MMR6 + 268454963U, // CMP_SUEQ_D + 268454963U, // CMP_SUEQ_D_MMR6 + 268459233U, // CMP_SUEQ_S + 268459233U, // CMP_SUEQ_S_MMR6 + 268454378U, // CMP_SULE_D + 268454378U, // CMP_SULE_D_MMR6 + 268458960U, // CMP_SULE_S + 268458960U, // CMP_SULE_S_MMR6 + 268455454U, // CMP_SULT_D + 268455454U, // CMP_SULT_D_MMR6 + 268459338U, // CMP_SULT_S + 268459338U, // CMP_SULT_S_MMR6 + 268454836U, // CMP_SUN_D + 268454836U, // CMP_SUN_D_MMR6 + 268459147U, // CMP_SUN_S + 268459147U, // CMP_SUN_S_MMR6 + 268454943U, // CMP_UEQ_D + 268454943U, // CMP_UEQ_D_MMR6 + 268459222U, // CMP_UEQ_S + 268459222U, // CMP_UEQ_S_MMR6 + 268454358U, // CMP_ULE_D + 268454358U, // CMP_ULE_D_MMR6 + 268458949U, // CMP_ULE_S + 268458949U, // CMP_ULE_S_MMR6 + 268455434U, // CMP_ULT_D + 268455434U, // CMP_ULT_D_MMR6 + 268459327U, // CMP_ULT_S + 268459327U, // CMP_ULT_S_MMR6 + 268454818U, // CMP_UN_D + 268454818U, // CMP_UN_D_MMR6 + 268459137U, // CMP_UN_S + 268459137U, // CMP_UN_S_MMR6 + 2684372233U, // COPY_S_B + 2684374422U, // COPY_S_D + 2684375988U, // COPY_S_H + 2684380361U, // COPY_S_W + 2684372448U, // COPY_U_B + 2684376255U, // COPY_U_H + 2684380768U, // COPY_U_W + 268453411U, // CRC32B + 268453419U, // CRC32CB + 268455959U, // CRC32CD + 268457238U, // CRC32CH + 268461764U, // CRC32CW + 268455945U, // CRC32D + 268457218U, // CRC32H + 268461756U, // CRC32W + 8945789U, // CTC1 + 8945789U, // CTC1_MM + 8946005U, // CTC2_MM + 17121U, // CTCMSA + 23409U, // CVT_D32_S + 23409U, // CVT_D32_S_MM + 24726U, // CVT_D32_W + 24726U, // CVT_D32_W_MM + 22511U, // CVT_D64_L + 23409U, // CVT_D64_S + 23409U, // CVT_D64_S_MM + 24726U, // CVT_D64_W + 24726U, // CVT_D64_W_MM + 22511U, // CVT_D_L_MMR6 + 19256U, // CVT_L_D64 + 19256U, // CVT_L_D64_MM + 19256U, // CVT_L_D_MMR6 + 23634U, // CVT_L_S + 23634U, // CVT_L_S_MM + 23634U, // CVT_L_S_MMR6 + 26322U, // CVT_PS_PW64 + 268459252U, // CVT_PS_S64 + 24135U, // CVT_PW_PS64 + 19603U, // CVT_S_D32 + 19603U, // CVT_S_D32_MM + 19603U, // CVT_S_D64 + 19603U, // CVT_S_D64_MM + 22520U, // CVT_S_L + 22520U, // CVT_S_L_MMR6 + 22779U, // CVT_S_PL64 + 24417U, // CVT_S_PU64 + 25481U, // CVT_S_W + 25481U, // CVT_S_W_MM + 25481U, // CVT_S_W_MMR6 + 20431U, // CVT_W_D32 + 20431U, // CVT_W_D32_MM + 20431U, // CVT_W_D64 + 20431U, // CVT_W_D64_MM + 23976U, // CVT_W_S + 23976U, // CVT_W_S_MM + 23976U, // CVT_W_S_MMR6 + 268454880U, // C_EQ_D32 + 268454880U, // C_EQ_D32_MM + 268454880U, // C_EQ_D64 + 268454880U, // C_EQ_D64_MM + 268459175U, // C_EQ_S + 268459175U, // C_EQ_S_MM + 268454442U, // C_F_D32 + 268454442U, // C_F_D32_MM + 268454442U, // C_F_D64 + 268454442U, // C_F_D64_MM + 268458972U, // C_F_S + 268458972U, // C_F_S_MM + 268454285U, // C_LE_D32 + 268454285U, // C_LE_D32_MM + 268454285U, // C_LE_D64 + 268454285U, // C_LE_D64_MM + 268458892U, // C_LE_S + 268458892U, // C_LE_S_MM + 268455371U, // C_LT_D32 + 268455371U, // C_LT_D32_MM + 268455371U, // C_LT_D64 + 268455371U, // C_LT_D64_MM + 268459280U, // C_LT_S + 268459280U, // C_LT_S_MM + 268454276U, // C_NGE_D32 + 268454276U, // C_NGE_D32_MM + 268454276U, // C_NGE_D64 + 268454276U, // C_NGE_D64_MM + 268458883U, // C_NGE_S + 268458883U, // C_NGE_S_MM + 268454311U, // C_NGLE_D32 + 268454311U, // C_NGLE_D32_MM + 268454311U, // C_NGLE_D64 + 268454311U, // C_NGLE_D64_MM + 268458910U, // C_NGLE_S + 268458910U, // C_NGLE_S_MM + 268454728U, // C_NGL_D32 + 268454728U, // C_NGL_D32_MM + 268454728U, // C_NGL_D64 + 268454728U, // C_NGL_D64_MM + 268459106U, // C_NGL_S + 268459106U, // C_NGL_S_MM + 268455362U, // C_NGT_D32 + 268455362U, // C_NGT_D32_MM + 268455362U, // C_NGT_D64 + 268455362U, // C_NGT_D64_MM + 268459271U, // C_NGT_S + 268459271U, // C_NGT_S_MM + 268454321U, // C_OLE_D32 + 268454321U, // C_OLE_D32_MM + 268454321U, // C_OLE_D64 + 268454321U, // C_OLE_D64_MM + 268458920U, // C_OLE_S + 268458920U, // C_OLE_S_MM + 268455397U, // C_OLT_D32 + 268455397U, // C_OLT_D32_MM + 268455397U, // C_OLT_D64 + 268455397U, // C_OLT_D64_MM + 268459298U, // C_OLT_S + 268459298U, // C_OLT_S_MM + 268454906U, // C_SEQ_D32 + 268454906U, // C_SEQ_D32_MM + 268454906U, // C_SEQ_D64 + 268454906U, // C_SEQ_D64_MM + 268459193U, // C_SEQ_S + 268459193U, // C_SEQ_S_MM + 268454512U, // C_SF_D32 + 268454512U, // C_SF_D32_MM + 268454512U, // C_SF_D64 + 268454512U, // C_SF_D64_MM + 268459018U, // C_SF_S + 268459018U, // C_SF_S_MM + 268454934U, // C_UEQ_D32 + 268454934U, // C_UEQ_D32_MM + 268454934U, // C_UEQ_D64 + 268454934U, // C_UEQ_D64_MM + 268459213U, // C_UEQ_S + 268459213U, // C_UEQ_S_MM + 268454349U, // C_ULE_D32 + 268454349U, // C_ULE_D32_MM + 268454349U, // C_ULE_D64 + 268454349U, // C_ULE_D64_MM + 268458940U, // C_ULE_S + 268458940U, // C_ULE_S_MM + 268455425U, // C_ULT_D32 + 268455425U, // C_ULT_D32_MM + 268455425U, // C_ULT_D64 + 268455425U, // C_ULT_D64_MM + 268459318U, // C_ULT_S + 268459318U, // C_ULT_S_MM + 268454810U, // C_UN_D32 + 268454810U, // C_UN_D32_MM + 268454810U, // C_UN_D64 + 268454810U, // C_UN_D64_MM + 268459129U, // C_UN_S + 268459129U, // C_UN_S_MM + 23030U, // CmpRxRy16 + 2952812451U, // CmpiRxImm16 + 22435U, // CmpiRxImmX16 + 268455973U, // DADD + 268457823U, // DADDi + 268459807U, // DADDiu + 268459743U, // DADDu + 268457854U, // DAHI + 268458400U, // DALIGN + 268457915U, // DATI + 268457933U, // DAUI + 22990U, // DBITSWAP + 22958U, // DCLO + 22958U, // DCLO_R6 + 26400U, // DCLZ + 26400U, // DCLZ_R6 + 268460027U, // DDIV + 268459935U, // DDIVU + 10701U, // DERET + 10701U, // DERET_MM + 10701U, // DERET_MMR6 + 268459711U, // DEXT + 268462102U, // DEXT64_32 + 268458375U, // DEXTM + 268459928U, // DEXTU + 284514U, // DI + 268459511U, // DINS + 268458368U, // DINSM + 268459883U, // DINSU + 268460028U, // DIV + 268459936U, // DIVU + 268459936U, // DIVU_MMR6 + 268460028U, // DIV_MMR6 + 268453111U, // DIV_S_B + 268455300U, // DIV_S_D + 268456855U, // DIV_S_H + 268461228U, // DIV_S_W + 268453326U, // DIV_U_B + 268455767U, // DIV_U_D + 268457133U, // DIV_U_H + 268461646U, // DIV_U_W + 284514U, // DI_MM + 284514U, // DI_MMR6 + 268452563U, // DLSA + 268452563U, // DLSA_R6 + 268451841U, // DMFC0 + 16488U, // DMFC1 + 268452160U, // DMFC2 + 92291392U, // DMFC2_OCTEON + 268451848U, // DMFGC0 + 268456025U, // DMOD + 268459757U, // DMODU + 286371U, // DMT + 1376288822U, // DMTC0 + 8945795U, // DMTC1 + 1376289115U, // DMTC2 + 92291419U, // DMTC2_OCTEON + 1376288800U, // DMTGC0 + 268457810U, // DMUH + 268459800U, // DMUHU + 268458304U, // DMUL + 24220U, // DMULT + 24464U, // DMULTu + 268459844U, // DMULU + 268458304U, // DMUL_R6 + 268455208U, // DOTP_S_D + 268456775U, // DOTP_S_H + 268461096U, // DOTP_S_W + 268455675U, // DOTP_U_D + 268457063U, // DOTP_U_H + 268461554U, // DOTP_U_W + 285232337U, // DPADD_S_D + 285233904U, // DPADD_S_H + 285238215U, // DPADD_S_W + 285232804U, // DPADD_U_D + 285234192U, // DPADD_U_H + 285238683U, // DPADD_U_W + 268457662U, // DPAQX_SA_W_PH + 268457662U, // DPAQX_SA_W_PH_MMR2 + 268457745U, // DPAQX_S_W_PH + 268457745U, // DPAQX_S_W_PH_MMR2 + 268460556U, // DPAQ_SA_L_W + 268460556U, // DPAQ_SA_L_W_MM + 268457704U, // DPAQ_S_W_PH + 268457704U, // DPAQ_S_W_PH_MM + 268458011U, // DPAU_H_QBL + 268458011U, // DPAU_H_QBL_MM + 268458625U, // DPAU_H_QBR + 268458625U, // DPAU_H_QBR_MM + 268457783U, // DPAX_W_PH + 268457783U, // DPAX_W_PH_MMR2 + 268457652U, // DPA_W_PH + 268457652U, // DPA_W_PH_MMR2 + 23035U, // DPOP + 268457677U, // DPSQX_SA_W_PH + 268457677U, // DPSQX_SA_W_PH_MMR2 + 268457759U, // DPSQX_S_W_PH + 268457759U, // DPSQX_S_W_PH_MMR2 + 268460569U, // DPSQ_SA_L_W + 268460569U, // DPSQ_SA_L_W_MM + 268457732U, // DPSQ_S_W_PH + 268457732U, // DPSQ_S_W_PH_MM + 285232304U, // DPSUB_S_D + 285233883U, // DPSUB_S_H + 285238182U, // DPSUB_S_W + 285232771U, // DPSUB_U_D + 285234171U, // DPSUB_U_H + 285238650U, // DPSUB_U_W + 268458023U, // DPSU_H_QBL + 268458023U, // DPSU_H_QBL_MM + 268458637U, // DPSU_H_QBR + 268458637U, // DPSU_H_QBR_MM + 268457794U, // DPSX_W_PH + 268457794U, // DPSX_W_PH_MMR2 + 268457773U, // DPS_W_PH + 268457773U, // DPS_W_PH_MMR2 + 268458810U, // DROTR + 268452117U, // DROTR32 + 268460071U, // DROTRV + 21770U, // DSBH + 26471U, // DSDIV + 20529U, // DSHD + 268458223U, // DSLL + 268452087U, // DSLL32 + 3221248239U, // DSLL64_32 + 268460033U, // DSLLV + 268452557U, // DSRA + 268452069U, // DSRA32 + 268460012U, // DSRAV + 268458251U, // DSRL + 268452095U, // DSRL32 + 268460040U, // DSRLV + 268453801U, // DSUB + 268459722U, // DSUBu + 26457U, // DUDIV + 285278U, // DVP + 282835U, // DVPE + 285278U, // DVP_MMR6 + 26472U, // DivRxRy16 + 26458U, // DivuRxRy16 + 10595U, // EHB + 10595U, // EHB_MM + 10595U, // EHB_MMR6 + 284526U, // EI + 284526U, // EI_MM + 284526U, // EI_MMR6 + 286376U, // EMT + 10702U, // ERET + 10599U, // ERETNC + 10599U, // ERETNC_MMR6 + 10702U, // ERET_MM + 10702U, // ERET_MMR6 + 285283U, // EVP + 282841U, // EVPE + 285283U, // EVP_MMR6 + 268459712U, // EXT + 268458584U, // EXTP + 268458463U, // EXTPDP + 268460055U, // EXTPDPV + 268460055U, // EXTPDPV_MM + 268458463U, // EXTPDP_MM + 268460064U, // EXTPV + 268460064U, // EXTPV_MM + 268458584U, // EXTP_MM + 268461289U, // EXTRV_RS_W + 268461289U, // EXTRV_RS_W_MM + 268460843U, // EXTRV_R_W + 268460843U, // EXTRV_R_W_MM + 268456864U, // EXTRV_S_H + 268456864U, // EXTRV_S_H_MM + 268461726U, // EXTRV_W + 268461726U, // EXTRV_W_MM + 268461278U, // EXTR_RS_W + 268461278U, // EXTR_RS_W_MM + 268460822U, // EXTR_R_W + 268460822U, // EXTR_R_W_MM + 268456795U, // EXTR_S_H + 268456795U, // EXTR_S_H_MM + 268460921U, // EXTR_W + 268460921U, // EXTR_W_MM + 268459609U, // EXTS + 268452134U, // EXTS32 + 268459712U, // EXT_MM + 268459712U, // EXT_MMR6 + 19872U, // FABS_D32 + 19872U, // FABS_D32_MM + 19872U, // FABS_D64 + 19872U, // FABS_D64_MM + 23789U, // FABS_S + 23789U, // FABS_S_MM + 268454225U, // FADD_D + 268454226U, // FADD_D32 + 268454226U, // FADD_D32_MM + 268454226U, // FADD_D64 + 268454226U, // FADD_D64_MM + 268459525U, // FADD_PS64 + 268458876U, // FADD_S + 268458876U, // FADD_S_MM + 285236092U, // FADD_S_MMR6 + 268460191U, // FADD_W + 268454459U, // FCAF_D + 268460310U, // FCAF_W + 268454898U, // FCEQ_D + 268460749U, // FCEQ_W + 19879U, // FCLASS_D + 25845U, // FCLASS_W + 268454303U, // FCLE_D + 268460233U, // FCLE_W + 268455389U, // FCLT_D + 268461328U, // FCLT_W + 3041387U, // FCMP_D32 + 3041387U, // FCMP_D32_MM + 3041387U, // FCMP_D64 + 3303531U, // FCMP_S32 + 3303531U, // FCMP_S32_MM + 268454399U, // FCNE_D + 268460267U, // FCNE_W + 268455008U, // FCOR_D + 268460878U, // FCOR_W + 268454954U, // FCUEQ_D + 268460765U, // FCUEQ_W + 268454369U, // FCULE_D + 268460249U, // FCULE_W + 268455445U, // FCULT_D + 268461344U, // FCULT_W + 268454415U, // FCUNE_D + 268460283U, // FCUNE_W + 268454828U, // FCUN_D + 268460655U, // FCUN_W + 268455821U, // FDIV_D + 268455822U, // FDIV_D32 + 268455822U, // FDIV_D32_MM + 268455822U, // FDIV_D64 + 268455822U, // FDIV_D64_MM + 268459375U, // FDIV_S + 268459375U, // FDIV_S_MM + 285236591U, // FDIV_S_MMR6 + 268461710U, // FDIV_W + 268456522U, // FEXDO_H + 268460671U, // FEXDO_W + 268454112U, // FEXP2_D + 268460094U, // FEXP2_W + 19296U, // FEXUPL_D + 25141U, // FEXUPL_W + 19568U, // FEXUPR_D + 25438U, // FEXUPR_W + 19810U, // FFINT_S_D + 25738U, // FFINT_S_W + 20289U, // FFINT_U_D + 26168U, // FFINT_U_W + 19306U, // FFQL_D + 25151U, // FFQL_W + 19578U, // FFQR_D + 25448U, // FFQR_W + 17422U, // FILL_B + 19281U, // FILL_D + 21027U, // FILL_H + 25126U, // FILL_W + 18647U, // FLOG2_D + 24629U, // FLOG2_W + 19245U, // FLOOR_L_D64 + 19245U, // FLOOR_L_D_MMR6 + 23623U, // FLOOR_L_S + 23623U, // FLOOR_L_S_MMR6 + 20420U, // FLOOR_W_D32 + 20420U, // FLOOR_W_D64 + 20420U, // FLOOR_W_D_MMR6 + 20420U, // FLOOR_W_MM + 23965U, // FLOOR_W_S + 23965U, // FLOOR_W_S_MM + 23965U, // FLOOR_W_S_MMR6 + 285231449U, // FMADD_D + 285237415U, // FMADD_W + 268454150U, // FMAX_A_D + 268460132U, // FMAX_A_W + 268455896U, // FMAX_D + 268461735U, // FMAX_W + 268454130U, // FMIN_A_D + 268460112U, // FMIN_A_W + 268454802U, // FMIN_D + 268460647U, // FMIN_W + 20381U, // FMOV_D32 + 20381U, // FMOV_D32_MM + 20381U, // FMOV_D64 + 20381U, // FMOV_D64_MM + 20381U, // FMOV_D_MMR6 + 23926U, // FMOV_S + 23926U, // FMOV_S_MM + 23926U, // FMOV_S_MMR6 + 285231407U, // FMSUB_D + 285237373U, // FMSUB_W + 268454786U, // FMUL_D + 268454787U, // FMUL_D32 + 268454787U, // FMUL_D32_MM + 268454787U, // FMUL_D64 + 268454787U, // FMUL_D64_MM + 268459541U, // FMUL_PS64 + 268459115U, // FMUL_S + 268459115U, // FMUL_S_MM + 285236331U, // FMUL_S_MMR6 + 268460631U, // FMUL_W + 19073U, // FNEG_D32 + 19073U, // FNEG_D32_MM + 19073U, // FNEG_D64 + 19073U, // FNEG_D64_MM + 23578U, // FNEG_S + 23578U, // FNEG_S_MM + 23578U, // FNEG_S_MMR6 + 3523778537U, // FORK + 19407U, // FRCP_D + 25224U, // FRCP_W + 20027U, // FRINT_D + 25914U, // FRINT_W + 20055U, // FRSQRT_D + 25942U, // FRSQRT_W + 268454478U, // FSAF_D + 268460318U, // FSAF_W + 268454926U, // FSEQ_D + 268460757U, // FSEQ_W + 268454341U, // FSLE_D + 268460241U, // FSLE_W + 268455417U, // FSLT_D + 268461336U, // FSLT_W + 268454407U, // FSNE_D + 268460275U, // FSNE_W + 268455016U, // FSOR_D + 268460886U, // FSOR_W + 20046U, // FSQRT_D + 20047U, // FSQRT_D32 + 20047U, // FSQRT_D32_MM + 20047U, // FSQRT_D64 + 20047U, // FSQRT_D64_MM + 23903U, // FSQRT_S + 23903U, // FSQRT_S_MM + 25933U, // FSQRT_W + 268454183U, // FSUB_D + 268454184U, // FSUB_D32 + 268454184U, // FSUB_D32_MM + 268454184U, // FSUB_D64 + 268454184U, // FSUB_D64_MM + 268459517U, // FSUB_PS64 + 268458858U, // FSUB_S + 268458858U, // FSUB_S_MM + 285236074U, // FSUB_S_MMR6 + 268460149U, // FSUB_W + 268454975U, // FSUEQ_D + 268460774U, // FSUEQ_W + 268454390U, // FSULE_D + 268460258U, // FSULE_W + 268455466U, // FSULT_D + 268461353U, // FSULT_W + 268454424U, // FSUNE_D + 268460292U, // FSUNE_W + 268454847U, // FSUN_D + 268460663U, // FSUN_W + 19821U, // FTINT_S_D + 25749U, // FTINT_S_W + 20300U, // FTINT_U_D + 26179U, // FTINT_U_W + 268456599U, // FTQ_H + 268460783U, // FTQ_W + 19643U, // FTRUNC_S_D + 25521U, // FTRUNC_S_W + 20110U, // FTRUNC_U_D + 25989U, // FTRUNC_U_W + 284632U, // GINVI + 284632U, // GINVI_MMR6 + 100687538U, // GINVT + 100687538U, // GINVT_MMR6 + 268455111U, // HADD_S_D + 268456678U, // HADD_S_H + 268460989U, // HADD_S_W + 268455578U, // HADD_U_D + 268456966U, // HADD_U_H + 268461457U, // HADD_U_W + 268455078U, // HSUB_S_D + 268456657U, // HSUB_S_H + 268460956U, // HSUB_S_W + 268455545U, // HSUB_U_D + 268456945U, // HSUB_U_H + 268461424U, // HSUB_U_W + 366795U, // HYPCALL + 366795U, // HYPCALL_MM + 268453381U, // ILVEV_B + 268455812U, // ILVEV_D + 268457188U, // ILVEV_H + 268461701U, // ILVEV_W + 268452909U, // ILVL_B + 268454794U, // ILVL_D + 268456514U, // ILVL_H + 268460639U, // ILVL_W + 268452661U, // ILVOD_B + 268454267U, // ILVOD_D + 268456316U, // ILVOD_H + 268460224U, // ILVOD_W + 268452957U, // ILVR_B + 268455051U, // ILVR_D + 268456639U, // ILVR_H + 268460929U, // ILVR_W + 268459506U, // INS + 112477484U, // INSERT_B + 120868420U, // INSERT_D + 129258455U, // INSERT_H + 137651523U, // INSERT_W + 16801839U, // INSV + 146031422U, // INSVE_B + 154421793U, // INSVE_D + 162812293U, // INSVE_H + 171204877U, // INSVE_W + 16801839U, // INSV_MM + 268459506U, // INS_MM + 268459506U, // INS_MMR6 + 284639U, // J + 284678U, // JAL + 23310U, // JALR + 285454U, // JALR16_MM + 23310U, // JALR64 + 285454U, // JALRC16_MMR6 + 17977U, // JALRC_HB_MMR6 + 18516U, // JALRC_MMR6 + 279095U, // JALRS16_MM + 24146U, // JALRS_MM + 17994U, // JALR_HB + 17994U, // JALR_HB64 + 23310U, // JALR_MM + 286169U, // JALS_MM + 288494U, // JALX + 288494U, // JALX_MM + 284678U, // JAL_MM + 18395U, // JIALC + 18395U, // JIALC64 + 18395U, // JIALC_MMR6 + 18384U, // JIC + 18384U, // JIC64 + 18384U, // JIC_MMR6 + 285450U, // JR + 279082U, // JR16_MM + 285450U, // JR64 + 285255U, // JRADDIUSP + 280655U, // JRC16_MM + 278960U, // JRC16_MMR6 + 285243U, // JRCADDIUSP_MMR6 + 280131U, // JR_HB + 280131U, // JR_HB64 + 280131U, // JR_HB64_R6 + 280131U, // JR_HB_R6 + 285450U, // JR_MM + 284639U, // J_MM + 3840006U, // Jal16 + 4102150U, // JalB16 + 10588U, // JrRa16 + 10580U, // JrcRa16 + 280655U, // JrcRx16 + 280660U, // JumpLinkReg16 + 25183827U, // LB + 25183827U, // LB64 + 25186403U, // LBE + 25186403U, // LBE_MM + 25182791U, // LBU16_MM + 3774899956U, // LBUX + 3774899956U, // LBUX_MM + 25190085U, // LBU_MMR6 + 25183827U, // LB_MM + 25183827U, // LB_MMR6 + 25190085U, // LBu + 25190085U, // LBu64 + 25186539U, // LBuE + 25186539U, // LBuE_MM + 25190085U, // LBu_MM + 25186362U, // LD + 25182294U, // LDC1 + 25182294U, // LDC164 + 25182294U, // LDC1_D64_MMR6 + 25182294U, // LDC1_MM + 25182510U, // LDC2 + 25182510U, // LDC2_MMR6 + 25182510U, // LDC2_R6 + 25182595U, // LDC3 + 17248U, // LDI_B + 19089U, // LDI_D + 20903U, // LDI_H + 24976U, // LDI_W + 25188450U, // LDL + 18462U, // LDPC + 25189064U, // LDR + 3774890134U, // LDXC1 + 3774890134U, // LDXC164 + 25183014U, // LD_B + 25184620U, // LD_D + 25186669U, // LD_H + 25190577U, // LD_W + 67133216U, // LEA_ADDiu + 67133215U, // LEA_ADDiu64 + 67133216U, // LEA_ADDiu_MM + 25187621U, // LH + 25187621U, // LH64 + 25186455U, // LHE + 25186455U, // LHE_MM + 25182814U, // LHU16_MM + 3774899945U, // LHX + 3774899945U, // LHX_MM + 25187621U, // LH_MM + 25190163U, // LHu + 25190163U, // LHu64 + 25186545U, // LHuE + 25186545U, // LHuE_MM + 25190163U, // LHu_MM + 16878U, // LI16_MM + 16878U, // LI16_MMR6 + 25188560U, // LL + 25188560U, // LL64 + 25188560U, // LL64_R6 + 25186366U, // LLD + 25186366U, // LLD_R6 + 25186478U, // LLE + 25186478U, // LLE_MM + 25188560U, // LL_MM + 25188560U, // LL_MMR6 + 25188560U, // LL_R6 + 268452564U, // LSA + 4061741780U, // LSA_MMR6 + 268452564U, // LSA_R6 + 92297171U, // LUI_MMR6 + 3774890148U, // LUXC1 + 3774890148U, // LUXC164 + 3774890148U, // LUXC1_MM + 92297171U, // LUi + 92297171U, // LUi64 + 92297171U, // LUi_MM + 25192142U, // LW + 25182821U, // LW16_MM + 25192142U, // LW64 + 25182346U, // LWC1 + 25182346U, // LWC1_MM + 25182562U, // LWC2 + 25182562U, // LWC2_MMR6 + 25182562U, // LWC2_R6 + 25182607U, // LWC3 + 25192142U, // LWDSP + 25192142U, // LWDSP_MM + 25186557U, // LWE + 25186557U, // LWE_MM + 25192142U, // LWGP_MM + 25188692U, // LWL + 25188692U, // LWL64 + 25186488U, // LWLE + 25186488U, // LWLE_MM + 25188692U, // LWL_MM + 49675U, // LWM16_MM + 49675U, // LWM16_MMR6 + 49415U, // LWM32_MM + 18499U, // LWPC + 18499U, // LWPC_MMR6 + 176183912U, // LWP_MM + 25189198U, // LWR + 25189198U, // LWR64 + 25186527U, // LWRE + 25186527U, // LWRE_MM + 25189198U, // LWR_MM + 25192142U, // LWSP_MM + 18492U, // LWUPC + 25190310U, // LWU_MM + 3774899962U, // LWX + 3774890162U, // LWXC1 + 3774890162U, // LWXC1_MM + 3774897759U, // LWXS_MM + 3774899962U, // LWX_MM + 25192142U, // LW_MM + 25192142U, // LW_MMR6 + 25190310U, // LWu + 25183827U, // LbRxRyOffMemX16 + 25190085U, // LbuRxRyOffMemX16 + 25187621U, // LhRxRyOffMemX16 + 25190163U, // LhuRxRyOffMemX16 + 2952812442U, // LiRxImm16 + 22416U, // LiRxImmAlignX16 + 22426U, // LiRxImmX16 + 2147509966U, // LwRxPcTcp16 + 26318U, // LwRxPcTcpX16 + 25192142U, // LwRxRyOffMemX16 + 25192142U, // LwRxSpImmX16 + 20523U, // MADD + 285231711U, // MADDF_D + 285231711U, // MADDF_D_MMR6 + 285236225U, // MADDF_S + 285236225U, // MADDF_S_MMR6 + 285233787U, // MADDR_Q_H + 285237944U, // MADDR_Q_W + 24294U, // MADDU + 268459750U, // MADDU_DSP + 268459750U, // MADDU_DSP_MM + 24294U, // MADDU_MM + 285230579U, // MADDV_B + 285233010U, // MADDV_D + 285234386U, // MADDV_H + 285238899U, // MADDV_W + 268454234U, // MADD_D32 + 268454234U, // MADD_D32_MM + 268454234U, // MADD_D64 + 268455979U, // MADD_DSP + 268455979U, // MADD_DSP_MM + 20523U, // MADD_MM + 285233757U, // MADD_Q_H + 285237914U, // MADD_Q_W + 268458875U, // MADD_S + 268458875U, // MADD_S_MM + 268458131U, // MAQ_SA_W_PHL + 268458131U, // MAQ_SA_W_PHL_MM + 268458706U, // MAQ_SA_W_PHR + 268458706U, // MAQ_SA_W_PHR_MM + 268458159U, // MAQ_S_W_PHL + 268458159U, // MAQ_S_W_PHL_MM + 268458734U, // MAQ_S_W_PHR + 268458734U, // MAQ_S_W_PHR_MM + 268454175U, // MAXA_D + 268454175U, // MAXA_D_MMR6 + 268458848U, // MAXA_S + 268458848U, // MAXA_S_MMR6 + 268453032U, // MAXI_S_B + 268455189U, // MAXI_S_D + 268456756U, // MAXI_S_H + 268461067U, // MAXI_S_W + 268453247U, // MAXI_U_B + 268455656U, // MAXI_U_D + 268457044U, // MAXI_U_H + 268461535U, // MAXI_U_W + 268452613U, // MAX_A_B + 268454151U, // MAX_A_D + 268456268U, // MAX_A_H + 268460133U, // MAX_A_W + 268455897U, // MAX_D + 268455897U, // MAX_D_MMR6 + 268459441U, // MAX_S + 268453120U, // MAX_S_B + 268455309U, // MAX_S_D + 268456875U, // MAX_S_H + 268459441U, // MAX_S_MMR6 + 268461248U, // MAX_S_W + 268453335U, // MAX_U_B + 268455776U, // MAX_U_D + 268457142U, // MAX_U_H + 268461655U, // MAX_U_W + 268451842U, // MFC0 + 268451842U, // MFC0_MMR6 + 16489U, // MFC1 + 16489U, // MFC1_D64 + 16489U, // MFC1_MM + 16489U, // MFC1_MMR6 + 268452161U, // MFC2 + 16705U, // MFC2_MMR6 + 268451849U, // MFGC0 + 268451849U, // MFGC0_MM + 268451880U, // MFHC0_MMR6 + 16495U, // MFHC1_D32 + 16495U, // MFHC1_D32_MM + 16495U, // MFHC1_D64 + 16495U, // MFHC1_D64_MM + 16711U, // MFHC2_MMR6 + 268451856U, // MFHGC0 + 268451856U, // MFHGC0_MM + 284548U, // MFHI + 279014U, // MFHI16_MM + 284548U, // MFHI64 + 22404U, // MFHI_DSP + 22404U, // MFHI_DSP_MM + 284548U, // MFHI_MM + 285108U, // MFLO + 279065U, // MFLO16_MM + 285108U, // MFLO64 + 22964U, // MFLO_DSP + 22964U, // MFLO_DSP_MM + 285108U, // MFLO_MM + 268458804U, // MFTR + 268454160U, // MINA_D + 268454160U, // MINA_D_MMR6 + 268458840U, // MINA_S + 268458840U, // MINA_S_MMR6 + 268453012U, // MINI_S_B + 268455169U, // MINI_S_D + 268456736U, // MINI_S_H + 268461047U, // MINI_S_W + 268453227U, // MINI_U_B + 268455636U, // MINI_U_D + 268457024U, // MINI_U_H + 268461515U, // MINI_U_W + 268452594U, // MIN_A_B + 268454131U, // MIN_A_D + 268456249U, // MIN_A_H + 268460113U, // MIN_A_W + 268454803U, // MIN_D + 268454803U, // MIN_D_MMR6 + 268459122U, // MIN_S + 268453042U, // MIN_S_B + 268455199U, // MIN_S_D + 268456766U, // MIN_S_H + 268459122U, // MIN_S_MMR6 + 268461087U, // MIN_S_W + 268453257U, // MIN_U_B + 268455666U, // MIN_U_D + 268457054U, // MIN_U_H + 268461545U, // MIN_U_W + 268456026U, // MOD + 268453799U, // MODSUB + 268453799U, // MODSUB_MM + 268459758U, // MODU + 268459758U, // MODU_MMR6 + 268456026U, // MOD_MMR6 + 268452975U, // MOD_S_B + 268455132U, // MOD_S_D + 268456699U, // MOD_S_H + 268461010U, // MOD_S_W + 268453190U, // MOD_U_B + 268455599U, // MOD_U_D + 268456987U, // MOD_U_H + 268461478U, // MOD_U_W + 20727U, // MOVE16_MM + 16848U, // MOVE16_MMR6 + 268458471U, // MOVEP_MM + 268458471U, // MOVEP_MMR6 + 24498U, // MOVE_V + 268454520U, // MOVF_D32 + 268454520U, // MOVF_D32_MM + 268454520U, // MOVF_D64 + 268456229U, // MOVF_I + 268456229U, // MOVF_I64 + 268456229U, // MOVF_I_MM + 268459026U, // MOVF_S + 268459026U, // MOVF_S_MM + 268454855U, // MOVN_I64_D64 + 268458408U, // MOVN_I64_I + 268458408U, // MOVN_I64_I64 + 268459158U, // MOVN_I64_S + 268454855U, // MOVN_I_D32 + 268454855U, // MOVN_I_D32_MM + 268454855U, // MOVN_I_D64 + 268458408U, // MOVN_I_I + 268458408U, // MOVN_I_I64 + 268458408U, // MOVN_I_MM + 268459158U, // MOVN_I_S + 268459158U, // MOVN_I_S_MM + 268455527U, // MOVT_D32 + 268455527U, // MOVT_D32_MM + 268455527U, // MOVT_D64 + 268459705U, // MOVT_I + 268459705U, // MOVT_I64 + 268459705U, // MOVT_I_MM + 268459367U, // MOVT_S + 268459367U, // MOVT_S_MM + 268455937U, // MOVZ_I64_D64 + 268461895U, // MOVZ_I64_I + 268461895U, // MOVZ_I64_I64 + 268459468U, // MOVZ_I64_S + 268455937U, // MOVZ_I_D32 + 268455937U, // MOVZ_I_D32_MM + 268455937U, // MOVZ_I_D64 + 268461895U, // MOVZ_I_I + 268461895U, // MOVZ_I_I64 + 268461895U, // MOVZ_I_MM + 268459468U, // MOVZ_I_S + 268459468U, // MOVZ_I_S_MM + 18351U, // MSUB + 285231702U, // MSUBF_D + 285231702U, // MSUBF_D_MMR6 + 285236216U, // MSUBF_S + 285236216U, // MSUBF_S_MMR6 + 285233776U, // MSUBR_Q_H + 285237933U, // MSUBR_Q_W + 24273U, // MSUBU + 268459729U, // MSUBU_DSP + 268459729U, // MSUBU_DSP_MM + 24273U, // MSUBU_MM + 285230570U, // MSUBV_B + 285233001U, // MSUBV_D + 285234377U, // MSUBV_H + 285238890U, // MSUBV_W + 268454192U, // MSUB_D32 + 268454192U, // MSUB_D32_MM + 268454192U, // MSUB_D64 + 268453807U, // MSUB_DSP + 268453807U, // MSUB_DSP_MM + 18351U, // MSUB_MM + 285233747U, // MSUB_Q_H + 285237904U, // MSUB_Q_W + 268458857U, // MSUB_S + 268458857U, // MSUB_S_MM + 1376288823U, // MTC0 + 1376288823U, // MTC0_MMR6 + 8945796U, // MTC1 + 8945796U, // MTC1_D64 + 8945796U, // MTC1_D64_MM + 8945796U, // MTC1_MM + 8945796U, // MTC1_MMR6 + 1376289116U, // MTC2 + 8946012U, // MTC2_MMR6 + 1376288801U, // MTGC0 + 1376288801U, // MTGC0_MM + 1376288815U, // MTHC0_MMR6 + 8994934U, // MTHC1_D32 + 8994934U, // MTHC1_D32_MM + 8994934U, // MTHC1_D64 + 8994934U, // MTHC1_D64_MM + 8945998U, // MTHC2_MMR6 + 1376288792U, // MTHGC0 + 1376288792U, // MTHGC0_MM + 284554U, // MTHI + 284554U, // MTHI64 + 8951690U, // MTHI_DSP + 8951690U, // MTHI_DSP_MM + 284554U, // MTHI_MM + 8952302U, // MTHLIP + 8952302U, // MTHLIP_MM + 285121U, // MTLO + 285121U, // MTLO64 + 8952257U, // MTLO_DSP + 8952257U, // MTLO_DSP_MM + 285121U, // MTLO_MM + 278595U, // MTM0 + 278720U, // MTM1 + 278894U, // MTM2 + 278601U, // MTP0 + 278726U, // MTP1 + 278900U, // MTP2 + 34118465U, // MTTR + 268457811U, // MUH + 268459801U, // MUHU + 268459801U, // MUHU_MMR6 + 268457811U, // MUH_MMR6 + 268458305U, // MUL + 268458172U, // MULEQ_S_W_PHL + 268458172U, // MULEQ_S_W_PHL_MM + 268458747U, // MULEQ_S_W_PHR + 268458747U, // MULEQ_S_W_PHR_MM + 268458035U, // MULEU_S_PH_QBL + 268458035U, // MULEU_S_PH_QBL_MM + 268458649U, // MULEU_S_PH_QBR + 268458649U, // MULEU_S_PH_QBR_MM + 268457571U, // MULQ_RS_PH + 268457571U, // MULQ_RS_PH_MM + 268461267U, // MULQ_RS_W + 268461267U, // MULQ_RS_W_MMR2 + 268457515U, // MULQ_S_PH + 268457515U, // MULQ_S_PH_MMR2 + 268461126U, // MULQ_S_W + 268461126U, // MULQ_S_W_MMR2 + 268459566U, // MULR_PS64 + 268456582U, // MULR_Q_H + 268460739U, // MULR_Q_W + 268457717U, // MULSAQ_S_W_PH + 268457717U, // MULSAQ_S_W_PH_MM + 268457692U, // MULSA_W_PH + 268457692U, // MULSA_W_PH_MMR2 + 24221U, // MULT + 268459921U, // MULTU_DSP + 268459921U, // MULTU_DSP_MM + 268459677U, // MULT_DSP + 268459677U, // MULT_DSP_MM + 24221U, // MULT_MM + 24465U, // MULTu + 24465U, // MULTu_MM + 268459838U, // MULU + 268459838U, // MULU_MMR6 + 268453390U, // MULV_B + 268455829U, // MULV_D + 268457197U, // MULV_H + 268461718U, // MULV_W + 268458305U, // MUL_MM + 268458305U, // MUL_MMR6 + 268457388U, // MUL_PH + 268457388U, // MUL_PH_MMR2 + 268456551U, // MUL_Q_H + 268460708U, // MUL_Q_W + 268458305U, // MUL_R6 + 268457483U, // MUL_S_PH + 268457483U, // MUL_S_PH_MMR2 + 284548U, // Mfhi16 + 285108U, // Mflo16 + 20727U, // Move32R16 + 20727U, // MoveR3216 + 17173U, // NLOC_B + 18753U, // NLOC_D + 20828U, // NLOC_H + 24710U, // NLOC_W + 17181U, // NLZC_B + 18761U, // NLZC_D + 20836U, // NLZC_H + 24718U, // NLZC_W + 268454242U, // NMADD_D32 + 268454242U, // NMADD_D32_MM + 268454242U, // NMADD_D64 + 268458874U, // NMADD_S + 268458874U, // NMADD_S_MM + 268454200U, // NMSUB_D32 + 268454200U, // NMSUB_D32_MM + 268454200U, // NMSUB_D64 + 268458856U, // NMSUB_S + 268458856U, // NMSUB_S_MM + 268458772U, // NOR + 268458772U, // NOR64 + 268452798U, // NORI_B + 268458772U, // NOR_MM + 268458772U, // NOR_MMR6 + 268459970U, // NOR_V + 16960U, // NOT16_MM + 16960U, // NOT16_MMR6 + 20779U, // NegRxRy16 + 24237U, // NotRxRy16 + 268458773U, // OR + 10043953U, // OR16_MM + 10043953U, // OR16_MMR6 + 268458773U, // OR64 + 268452799U, // ORI_B + 268457910U, // ORI_MMR6 + 268458773U, // OR_MM + 268458773U, // OR_MMR6 + 268459971U, // OR_V + 268457910U, // ORi + 268457910U, // ORi64 + 268457910U, // ORi_MM + 16800533U, // OrRxRxRy16 + 268457377U, // PACKRL_PH + 268457377U, // PACKRL_PH_MM + 10606U, // PAUSE + 10606U, // PAUSE_MM + 10606U, // PAUSE_MMR6 + 268453372U, // PCKEV_B + 268455803U, // PCKEV_D + 268457179U, // PCKEV_H + 268461692U, // PCKEV_W + 268452652U, // PCKOD_B + 268454258U, // PCKOD_D + 268456307U, // PCKOD_H + 268460215U, // PCKOD_W + 17700U, // PCNT_B + 20019U, // PCNT_D + 21455U, // PCNT_H + 25906U, // PCNT_W + 268457341U, // PICK_PH + 268457341U, // PICK_PH_MM + 268453531U, // PICK_QB + 268453531U, // PICK_QB_MM + 268459533U, // PLL_PS64 + 268459575U, // PLU_PS64 + 23036U, // POP + 22610U, // PRECEQU_PH_QBL + 17046U, // PRECEQU_PH_QBLA + 17046U, // PRECEQU_PH_QBLA_MM + 22610U, // PRECEQU_PH_QBL_MM + 23224U, // PRECEQU_PH_QBR + 17084U, // PRECEQU_PH_QBRA + 17084U, // PRECEQU_PH_QBRA_MM + 23224U, // PRECEQU_PH_QBR_MM + 22689U, // PRECEQ_W_PHL + 22689U, // PRECEQ_W_PHL_MM + 23264U, // PRECEQ_W_PHR + 23264U, // PRECEQ_W_PHR_MM + 22595U, // PRECEU_PH_QBL + 17030U, // PRECEU_PH_QBLA + 17030U, // PRECEU_PH_QBLA_MM + 22595U, // PRECEU_PH_QBL_MM + 23209U, // PRECEU_PH_QBR + 17068U, // PRECEU_PH_QBRA + 17068U, // PRECEU_PH_QBRA_MM + 23209U, // PRECEU_PH_QBR_MM + 268457293U, // PRECRQU_S_QB_PH + 268457293U, // PRECRQU_S_QB_PH_MM + 268460358U, // PRECRQ_PH_W + 268460358U, // PRECRQ_PH_W_MM + 268457266U, // PRECRQ_QB_PH + 268457266U, // PRECRQ_QB_PH_MM + 268460389U, // PRECRQ_RS_PH_W + 268460389U, // PRECRQ_RS_PH_W_MM + 268457280U, // PRECR_QB_PH + 268457280U, // PRECR_QB_PH_MMR2 + 268460342U, // PRECR_SRA_PH_W + 268460342U, // PRECR_SRA_PH_W_MMR2 + 268460371U, // PRECR_SRA_R_PH_W + 268460371U, // PRECR_SRA_R_PH_W_MMR2 + 2756895U, // PREF + 2756730U, // PREFE + 2756730U, // PREFE_MM + 186263266U, // PREFX_MM + 2756895U, // PREF_MM + 2756895U, // PREF_MMR6 + 2756895U, // PREF_R6 + 268456008U, // PREPEND + 268456008U, // PREPEND_MMR2 + 268459549U, // PUL_PS64 + 268459583U, // PUU_PS64 + 18327U, // RADDU_W_QB + 18327U, // RADDU_W_QB_MM + 83909165U, // RDDSP + 192961069U, // RDDSP_MM + 268458823U, // RDHWR + 268458823U, // RDHWR64 + 268458823U, // RDHWR_MM + 268458823U, // RDHWR_MMR6 + 23332U, // RDPGPR_MMR6 + 19415U, // RECIP_D32 + 19415U, // RECIP_D32_MM + 19415U, // RECIP_D64 + 19415U, // RECIP_D64_MM + 23710U, // RECIP_S + 23710U, // RECIP_S_MM + 22176U, // REPLV_PH + 22176U, // REPLV_PH_MM + 18307U, // REPLV_QB + 18307U, // REPLV_QB_MM + 21903U, // REPL_PH + 21903U, // REPL_PH_MM + 201344685U, // REPL_QB + 201344685U, // REPL_QB_MM + 20028U, // RINT_D + 20028U, // RINT_D_MMR6 + 23894U, // RINT_S + 23894U, // RINT_S_MMR6 + 268458811U, // ROTR + 268460072U, // ROTRV + 268460072U, // ROTRV_MM + 268458811U, // ROTR_MM + 19224U, // ROUND_L_D64 + 19224U, // ROUND_L_D_MMR6 + 23602U, // ROUND_L_S + 23602U, // ROUND_L_S_MMR6 + 20399U, // ROUND_W_D32 + 20399U, // ROUND_W_D64 + 20399U, // ROUND_W_D_MMR6 + 20399U, // ROUND_W_MM + 23944U, // ROUND_W_S + 23944U, // ROUND_W_S_MM + 23944U, // ROUND_W_S_MMR6 + 20056U, // RSQRT_D32 + 20056U, // RSQRT_D32_MM + 20056U, // RSQRT_D64 + 20056U, // RSQRT_D64_MM + 23902U, // RSQRT_S + 23902U, // RSQRT_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 4211329U, // SAA + 4214801U, // SAAD + 268453081U, // SAT_S_B + 268455248U, // SAT_S_D + 268456825U, // SAT_S_H + 268461176U, // SAT_S_W + 268453308U, // SAT_U_B + 268455727U, // SAT_U_D + 268457115U, // SAT_U_H + 268461606U, // SAT_U_W + 25184163U, // SB + 25182628U, // SB16_MM + 25182628U, // SB16_MMR6 + 25184163U, // SB64 + 25186408U, // SBE + 25186408U, // SBE_MM + 25184163U, // SB_MM + 25184163U, // SB_MMR6 + 4491358U, // SC + 4491358U, // SC64 + 4491358U, // SC64_R6 + 4493344U, // SCD + 4493344U, // SCD_R6 + 4493421U, // SCE + 4493421U, // SCE_MM + 4491358U, // SC_MM + 4491358U, // SC_MMR6 + 4491358U, // SC_R6 + 25186399U, // SD + 186840U, // SDBBP + 115233U, // SDBBP16_MM + 115233U, // SDBBP16_MMR6 + 367064U, // SDBBP_MM + 186840U, // SDBBP_MMR6 + 186840U, // SDBBP_R6 + 25182300U, // SDC1 + 25182300U, // SDC164 + 25182300U, // SDC1_D64_MMR6 + 25182300U, // SDC1_MM + 25182516U, // SDC2 + 25182516U, // SDC2_MMR6 + 25182516U, // SDC2_R6 + 25182601U, // SDC3 + 26472U, // SDIV + 26472U, // SDIV_MM + 25188455U, // SDL + 25189069U, // SDR + 3774890141U, // SDXC1 + 3774890141U, // SDXC164 + 17972U, // SEB + 17972U, // SEB64 + 17972U, // SEB_MM + 21791U, // SEH + 21791U, // SEH64 + 21791U, // SEH_MM + 268461868U, // SELEQZ + 268461868U, // SELEQZ64 + 268455927U, // SELEQZ_D + 268455927U, // SELEQZ_D_MMR6 + 268461868U, // SELEQZ_MMR6 + 268459458U, // SELEQZ_S + 268459458U, // SELEQZ_S_MMR6 + 268461841U, // SELNEZ + 268461841U, // SELNEZ64 + 268455910U, // SELNEZ_D + 268455910U, // SELNEZ_D_MMR6 + 268461841U, // SELNEZ_MMR6 + 268459448U, // SELNEZ_S + 268459448U, // SELNEZ_S_MMR6 + 285231937U, // SEL_D + 285231937U, // SEL_D_MMR6 + 285236315U, // SEL_S + 285236315U, // SEL_S_MMR6 + 268458615U, // SEQ + 268457897U, // SEQi + 25188174U, // SH + 25182680U, // SH16_MM + 25182680U, // SH16_MMR6 + 25188174U, // SH64 + 25186460U, // SHE + 25186460U, // SHE_MM + 268452680U, // SHF_B + 268456335U, // SHF_H + 268460327U, // SHF_W + 22970U, // SHILO + 24591U, // SHILOV + 24591U, // SHILOV_MM + 22970U, // SHILO_MM + 268457622U, // SHLLV_PH + 268457622U, // SHLLV_PH_MM + 268453753U, // SHLLV_QB + 268453753U, // SHLLV_QB_MM + 268457559U, // SHLLV_S_PH + 268457559U, // SHLLV_S_PH_MM + 268461237U, // SHLLV_S_W + 268461237U, // SHLLV_S_W_MM + 268457350U, // SHLL_PH + 268457350U, // SHLL_PH_MM + 268453540U, // SHLL_QB + 268453540U, // SHLL_QB_MM + 268457472U, // SHLL_S_PH + 268457472U, // SHLL_S_PH_MM + 268461077U, // SHLL_S_W + 268461077U, // SHLL_S_W_MM + 268457612U, // SHRAV_PH + 268457612U, // SHRAV_PH_MM + 268453743U, // SHRAV_QB + 268453743U, // SHRAV_QB_MMR2 + 268457460U, // SHRAV_R_PH + 268457460U, // SHRAV_R_PH_MM + 268453641U, // SHRAV_R_QB + 268453641U, // SHRAV_R_QB_MMR2 + 268460832U, // SHRAV_R_W + 268460832U, // SHRAV_R_W_MM + 268457257U, // SHRA_PH + 268457257U, // SHRA_PH_MM + 268453463U, // SHRA_QB + 268453463U, // SHRA_QB_MMR2 + 268457425U, // SHRA_R_PH + 268457425U, // SHRA_R_PH_MM + 268453606U, // SHRA_R_QB + 268453606U, // SHRA_R_QB_MMR2 + 268460790U, // SHRA_R_W + 268460790U, // SHRA_R_W_MM + 268457642U, // SHRLV_PH + 268457642U, // SHRLV_PH_MMR2 + 268453773U, // SHRLV_QB + 268453773U, // SHRLV_QB_MM + 268457368U, // SHRL_PH + 268457368U, // SHRL_PH_MMR2 + 268453558U, // SHRL_QB + 268453558U, // SHRL_QB_MM + 25188174U, // SH_MM + 25188174U, // SH_MMR6 + 200865U, // SIGRIE + 200865U, // SIGRIE_MMR6 + 2701149023U, // SLDI_B + 2701150864U, // SLDI_D + 2701152678U, // SLDI_H + 2701156751U, // SLDI_W + 2701148965U, // SLD_B + 2701150571U, // SLD_D + 2701152620U, // SLD_H + 2701156528U, // SLD_W + 268458224U, // SLL + 268452349U, // SLL16_MM + 268452349U, // SLL16_MMR6 + 268458224U, // SLL64_32 + 268458224U, // SLL64_64 + 268452737U, // SLLI_B + 268454561U, // SLLI_D + 268456375U, // SLLI_H + 268460448U, // SLLI_W + 268460034U, // SLLV + 268460034U, // SLLV_MM + 268452886U, // SLL_B + 268454745U, // SLL_D + 268456491U, // SLL_H + 268458224U, // SLL_MM + 268458224U, // SLL_MMR6 + 268460590U, // SLL_W + 268459666U, // SLT + 268459666U, // SLT64 + 268459666U, // SLT_MM + 268457921U, // SLTi + 268457921U, // SLTi64 + 268457921U, // SLTi_MM + 268459822U, // SLTiu + 268459822U, // SLTiu64 + 268459822U, // SLTiu_MM + 268459908U, // SLTu + 268459908U, // SLTu64 + 268459908U, // SLTu_MM + 268456137U, // SNE + 268457842U, // SNEi + 2684371928U, // SPLATI_B + 2684373736U, // SPLATI_D + 2684375550U, // SPLATI_H + 2684379623U, // SPLATI_W + 2684372243U, // SPLAT_B + 2684374449U, // SPLAT_D + 2684375998U, // SPLAT_H + 2684380415U, // SPLAT_W + 268452558U, // SRA + 268452695U, // SRAI_B + 268454536U, // SRAI_D + 268456350U, // SRAI_H + 268460423U, // SRAI_W + 268452771U, // SRARI_B + 268454595U, // SRARI_D + 268456409U, // SRARI_H + 268460482U, // SRARI_W + 268452924U, // SRAR_B + 268454984U, // SRAR_D + 268456606U, // SRAR_H + 268460854U, // SRAR_W + 268460013U, // SRAV + 268460013U, // SRAV_MM + 268452622U, // SRA_B + 268454168U, // SRA_D + 268456277U, // SRA_H + 268452558U, // SRA_MM + 268460142U, // SRA_W + 268458252U, // SRL + 268452356U, // SRL16_MM + 268452356U, // SRL16_MMR6 + 268452745U, // SRLI_B + 268454569U, // SRLI_D + 268456383U, // SRLI_H + 268460456U, // SRLI_W + 268452789U, // SRLRI_B + 268454613U, // SRLRI_D + 268456427U, // SRLRI_H + 268460500U, // SRLRI_W + 268452940U, // SRLR_B + 268455000U, // SRLR_D + 268456622U, // SRLR_H + 268460870U, // SRLR_W + 268460041U, // SRLV + 268460041U, // SRLV_MM + 268452893U, // SRL_B + 268454770U, // SRL_D + 268456498U, // SRL_H + 268458252U, // SRL_MM + 268460615U, // SRL_W + 10671U, // SSNOP + 10671U, // SSNOP_MM + 10671U, // SSNOP_MMR6 + 25183542U, // ST_B + 25185889U, // ST_D + 25187297U, // ST_H + 25191776U, // ST_W + 268453802U, // SUB + 268457321U, // SUBQH_PH + 268457321U, // SUBQH_PH_MMR2 + 268457436U, // SUBQH_R_PH + 268457436U, // SUBQH_R_PH_MMR2 + 268460800U, // SUBQH_R_W + 268460800U, // SUBQH_R_W_MMR2 + 268460405U, // SUBQH_W + 268460405U, // SUBQH_W_MMR2 + 268457396U, // SUBQ_PH + 268457396U, // SUBQ_PH_MM + 268457493U, // SUBQ_S_PH + 268457493U, // SUBQ_S_PH_MM + 268461106U, // SUBQ_S_W + 268461106U, // SUBQ_S_W_MM + 268453296U, // SUBSUS_U_B + 268455715U, // SUBSUS_U_D + 268457103U, // SUBSUS_U_H + 268461594U, // SUBSUS_U_W + 268453099U, // SUBSUU_S_B + 268455288U, // SUBSUU_S_D + 268456843U, // SUBSUU_S_H + 268461216U, // SUBSUU_S_W + 268453061U, // SUBS_S_B + 268455228U, // SUBS_S_D + 268456805U, // SUBS_S_H + 268461156U, // SUBS_S_W + 268453276U, // SUBS_U_B + 268455695U, // SUBS_U_D + 268457083U, // SUBS_U_H + 268461574U, // SUBS_U_W + 268452430U, // SUBU16_MM + 268452430U, // SUBU16_MMR6 + 268453511U, // SUBUH_QB + 268453511U, // SUBUH_QB_MMR2 + 268453617U, // SUBUH_R_QB + 268453617U, // SUBUH_R_QB_MMR2 + 268459723U, // SUBU_MMR6 + 268457594U, // SUBU_PH + 268457594U, // SUBU_PH_MMR2 + 268453725U, // SUBU_QB + 268453725U, // SUBU_QB_MM + 268457537U, // SUBU_S_PH + 268457537U, // SUBU_S_PH_MMR2 + 268453664U, // SUBU_S_QB + 268453664U, // SUBU_S_QB_MM + 268452843U, // SUBVI_B + 268454651U, // SUBVI_D + 268456465U, // SUBVI_H + 268460538U, // SUBVI_W + 268453355U, // SUBV_B + 268455786U, // SUBV_D + 268457162U, // SUBV_H + 268461675U, // SUBV_W + 268453802U, // SUB_MM + 268453802U, // SUB_MMR6 + 268459723U, // SUBu + 268459723U, // SUBu_MM + 3774890155U, // SUXC1 + 3774890155U, // SUXC164 + 3774890155U, // SUXC1_MM + 25192158U, // SW + 25182827U, // SW16_MM + 25182827U, // SW16_MMR6 + 25192158U, // SW64 + 25182352U, // SWC1 + 25182352U, // SWC1_MM + 25182568U, // SWC2 + 25182568U, // SWC2_MMR6 + 25182568U, // SWC2_R6 + 25182613U, // SWC3 + 25192158U, // SWDSP + 25192158U, // SWDSP_MM + 25186562U, // SWE + 25186562U, // SWE_MM + 25188697U, // SWL + 25188697U, // SWL64 + 25186494U, // SWLE + 25186494U, // SWLE_MM + 25188697U, // SWL_MM + 49682U, // SWM16_MM + 49682U, // SWM16_MMR6 + 49422U, // SWM32_MM + 176183917U, // SWP_MM + 25189203U, // SWR + 25189203U, // SWR64 + 25186533U, // SWRE + 25186533U, // SWRE_MM + 25189203U, // SWR_MM + 25188946U, // SWSP_MM + 25192158U, // SWSP_MMR6 + 3774890169U, // SWXC1 + 3774890169U, // SWXC1_MM + 25192158U, // SW_MM + 25192158U, // SW_MMR6 + 223162U, // SYNC + 235352U, // SYNCI + 235352U, // SYNCI_MM + 235352U, // SYNCI_MMR6 + 223162U, // SYNC_MM + 215064U, // SYNC_MMR6 + 186580U, // SYSCALL + 366804U, // SYSCALL_MM + 0U, // Save16 + 0U, // SaveX16 + 25184163U, // SbRxRyOffMemX16 + 288589U, // SebRx16 + 288595U, // SehRx16 + 25188174U, // ShRxRyOffMemX16 + 268458224U, // SllX16 + 16801794U, // SllvRxRy16 + 24210U, // SltRxRy16 + 2952812481U, // SltiRxImm16 + 22465U, // SltiRxImmX16 + 2952814382U, // SltiuRxImm16 + 24366U, // SltiuRxImmX16 + 24452U, // SltuRxRy16 + 268452558U, // SraX16 + 16801773U, // SravRxRy16 + 268458252U, // SrlX16 + 16801801U, // SrlvRxRy16 + 268459723U, // SubuRxRyRz16 + 25192158U, // SwRxRyOffMemX16 + 25192158U, // SwRxSpImmX16 + 268458620U, // TEQ + 22447U, // TEQI + 22447U, // TEQI_MM + 268458620U, // TEQ_MM + 268456075U, // TGE + 22380U, // TGEI + 24359U, // TGEIU + 24359U, // TGEIU_MM + 22380U, // TGEI_MM + 268459776U, // TGEU + 268459776U, // TGEU_MM + 268456075U, // TGE_MM + 10719U, // TLBGINV + 10620U, // TLBGINVF + 10620U, // TLBGINVF_MM + 10719U, // TLBGINV_MM + 10665U, // TLBGP + 10665U, // TLBGP_MM + 10682U, // TLBGR + 10682U, // TLBGR_MM + 10635U, // TLBGWI + 10635U, // TLBGWI_MM + 10694U, // TLBGWR + 10694U, // TLBGWR_MM + 10712U, // TLBINV + 10612U, // TLBINVF + 10612U, // TLBINVF_MMR6 + 10712U, // TLBINV_MMR6 + 10660U, // TLBP + 10660U, // TLBP_MM + 10677U, // TLBR + 10677U, // TLBR_MM + 10629U, // TLBWI + 10629U, // TLBWI_MM + 10688U, // TLBWR + 10688U, // TLBWR_MM + 268459671U, // TLT + 22471U, // TLTI + 24373U, // TLTIU_MM + 22471U, // TLTI_MM + 268459914U, // TLTU + 268459914U, // TLTU_MM + 268459671U, // TLT_MM + 268456142U, // TNE + 22392U, // TNEI + 22392U, // TNEI_MM + 268456142U, // TNE_MM + 19213U, // TRUNC_L_D64 + 19213U, // TRUNC_L_D_MMR6 + 23591U, // TRUNC_L_S + 23591U, // TRUNC_L_S_MMR6 + 20388U, // TRUNC_W_D32 + 20388U, // TRUNC_W_D64 + 20388U, // TRUNC_W_D_MMR6 + 20388U, // TRUNC_W_MM + 23933U, // TRUNC_W_S + 23933U, // TRUNC_W_S_MM + 23933U, // TRUNC_W_S_MMR6 + 24373U, // TTLTIU + 26458U, // UDIV + 26458U, // UDIV_MM + 268459836U, // V3MULU + 268451901U, // VMM0 + 268459851U, // VMULU + 285229895U, // VSHF_B + 285231720U, // VSHF_D + 285233550U, // VSHF_H + 285237542U, // VSHF_W + 10707U, // WAIT + 368263U, // WAIT_MM + 368263U, // WAIT_MMR6 + 83909172U, // WRDSP + 192961076U, // WRDSP_MM + 23340U, // WRPGPR_MMR6 + 21776U, // WSBH + 21776U, // WSBH_MM + 21776U, // WSBH_MMR6 + 268458783U, // XOR + 10043952U, // XOR16_MM + 10043952U, // XOR16_MMR6 + 268458783U, // XOR64 + 268452806U, // XORI_B + 268457909U, // XORI_MMR6 + 268458783U, // XOR_MM + 268458783U, // XOR_MMR6 + 268459977U, // XOR_V + 268457909U, // XORi + 268457909U, // XORi64 + 268457909U, // XORi_MM + 16800543U, // XorRxRxRy16 + 20535U, // YIELD + }; + + static const uint16_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ABSMacro + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // AND_V_D_PSEUDO + 0U, // AND_V_H_PSEUDO + 0U, // AND_V_W_PSEUDO + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I16_POSTRA + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I32_POSTRA + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I64_POSTRA + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_CMP_SWAP_I8_POSTRA + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I16_POSTRA + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I32_POSTRA + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I64_POSTRA + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_ADD_I8_POSTRA + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I16_POSTRA + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I32_POSTRA + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I64_POSTRA + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_AND_I8_POSTRA + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I16_POSTRA + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I32_POSTRA + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I64_POSTRA + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MAX_I8_POSTRA + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I16_POSTRA + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I32_POSTRA + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I64_POSTRA + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_MIN_I8_POSTRA + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I16_POSTRA + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I32_POSTRA + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I64_POSTRA + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_NAND_I8_POSTRA + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I16_POSTRA + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I32_POSTRA + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I64_POSTRA + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_OR_I8_POSTRA + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I16_POSTRA + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I32_POSTRA + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I64_POSTRA + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_SUB_I8_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I16_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I32_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I64_POSTRA + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMAX_I8_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I16_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I32_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I64_POSTRA + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_UMIN_I8_POSTRA + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I16_POSTRA + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I32_POSTRA + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I64_POSTRA + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_LOAD_XOR_I8_POSTRA + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I16_POSTRA + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I32_POSTRA + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I64_POSTRA + 0U, // ATOMIC_SWAP_I8 + 0U, // ATOMIC_SWAP_I8_POSTRA + 0U, // B + 0U, // BAL_BR + 0U, // BAL_BR_MM + 0U, // BEQLImmMacro + 0U, // BGE + 0U, // BGEImmMacro + 0U, // BGEL + 0U, // BGELImmMacro + 0U, // BGEU + 0U, // BGEUImmMacro + 0U, // BGEUL + 0U, // BGEULImmMacro + 0U, // BGT + 0U, // BGTImmMacro + 0U, // BGTL + 0U, // BGTLImmMacro + 0U, // BGTU + 0U, // BGTUImmMacro + 0U, // BGTUL + 0U, // BGTULImmMacro + 0U, // BLE + 0U, // BLEImmMacro + 0U, // BLEL + 0U, // BLELImmMacro + 0U, // BLEU + 0U, // BLEUImmMacro + 0U, // BLEUL + 0U, // BLEULImmMacro + 0U, // BLT + 0U, // BLTImmMacro + 0U, // BLTL + 0U, // BLTLImmMacro + 0U, // BLTU + 0U, // BLTUImmMacro + 0U, // BLTUL + 0U, // BLTULImmMacro + 0U, // BNELImmMacro + 0U, // BPOSGE32_PSEUDO + 0U, // BSEL_D_PSEUDO + 0U, // BSEL_FD_PSEUDO + 0U, // BSEL_FW_PSEUDO + 0U, // BSEL_H_PSEUDO + 0U, // BSEL_W_PSEUDO + 0U, // B_MM + 0U, // B_MMR6_Pseudo + 0U, // B_MM_Pseudo + 0U, // BeqImm + 0U, // BneImm + 0U, // BteqzT8CmpX16 + 0U, // BteqzT8CmpiX16 + 0U, // BteqzT8SltX16 + 0U, // BteqzT8SltiX16 + 0U, // BteqzT8SltiuX16 + 0U, // BteqzT8SltuX16 + 0U, // BtnezT8CmpX16 + 0U, // BtnezT8CmpiX16 + 0U, // BtnezT8SltX16 + 0U, // BtnezT8SltiX16 + 0U, // BtnezT8SltiuX16 + 0U, // BtnezT8SltuX16 + 0U, // BuildPairF64 + 0U, // BuildPairF64_64 + 0U, // CFTC1 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_FD_PSEUDO + 0U, // COPY_FW_PSEUDO + 0U, // CTTC1 + 0U, // Constant32 + 0U, // DMULImmMacro + 0U, // DMULMacro + 0U, // DMULOMacro + 0U, // DMULOUMacro + 0U, // DROL + 0U, // DROLImm + 0U, // DROR + 0U, // DRORImm + 0U, // DSDivIMacro + 0U, // DSDivMacro + 0U, // DSRemIMacro + 0U, // DSRemMacro + 0U, // DUDivIMacro + 0U, // DUDivMacro + 0U, // DURemIMacro + 0U, // DURemMacro + 0U, // ERet + 0U, // ExtractElementF64 + 0U, // ExtractElementF64_64 + 0U, // FABS_D + 0U, // FABS_W + 0U, // FEXP2_D_1_PSEUDO + 0U, // FEXP2_W_1_PSEUDO + 0U, // FILL_FD_PSEUDO + 0U, // FILL_FW_PSEUDO + 0U, // GotPrologue16 + 0U, // INSERT_B_VIDX64_PSEUDO + 0U, // INSERT_B_VIDX_PSEUDO + 0U, // INSERT_D_VIDX64_PSEUDO + 0U, // INSERT_D_VIDX_PSEUDO + 0U, // INSERT_FD_PSEUDO + 0U, // INSERT_FD_VIDX64_PSEUDO + 0U, // INSERT_FD_VIDX_PSEUDO + 0U, // INSERT_FW_PSEUDO + 0U, // INSERT_FW_VIDX64_PSEUDO + 0U, // INSERT_FW_VIDX_PSEUDO + 0U, // INSERT_H_VIDX64_PSEUDO + 0U, // INSERT_H_VIDX_PSEUDO + 0U, // INSERT_W_VIDX64_PSEUDO + 0U, // INSERT_W_VIDX_PSEUDO + 0U, // JALR64Pseudo + 0U, // JALRHB64Pseudo + 0U, // JALRHBPseudo + 0U, // JALRPseudo + 0U, // JAL_MMR6 + 0U, // JalOneReg + 0U, // JalTwoReg + 0U, // LDMacro + 0U, // LDR_D + 0U, // LDR_W + 0U, // LD_F16 + 0U, // LOAD_ACC128 + 0U, // LOAD_ACC64 + 0U, // LOAD_ACC64DSP + 0U, // LOAD_CCOND_DSP + 0U, // LONG_BRANCH_ADDiu + 0U, // LONG_BRANCH_ADDiu2Op + 0U, // LONG_BRANCH_DADDiu + 0U, // LONG_BRANCH_DADDiu2Op + 0U, // LONG_BRANCH_LUi + 0U, // LONG_BRANCH_LUi2Op + 0U, // LONG_BRANCH_LUi2Op_64 + 0U, // LWM_MM + 0U, // LoadAddrImm32 + 0U, // LoadAddrImm64 + 0U, // LoadAddrReg32 + 0U, // LoadAddrReg64 + 0U, // LoadImm32 + 0U, // LoadImm64 + 0U, // LoadImmDoubleFGR + 0U, // LoadImmDoubleFGR_32 + 0U, // LoadImmDoubleGPR + 0U, // LoadImmSingleFGR + 0U, // LoadImmSingleGPR + 0U, // LwConstant32 + 0U, // MFTACX + 2U, // MFTC0 + 0U, // MFTC1 + 0U, // MFTDSP + 0U, // MFTGPR + 0U, // MFTHC1 + 0U, // MFTHI + 0U, // MFTLO + 0U, // MIPSeh_return32 + 0U, // MIPSeh_return64 + 0U, // MSA_FP_EXTEND_D_PSEUDO + 0U, // MSA_FP_EXTEND_W_PSEUDO + 0U, // MSA_FP_ROUND_D_PSEUDO + 0U, // MSA_FP_ROUND_W_PSEUDO + 0U, // MTTACX + 0U, // MTTC0 + 0U, // MTTC1 + 0U, // MTTDSP + 0U, // MTTGPR + 0U, // MTTHC1 + 0U, // MTTHI + 0U, // MTTLO + 0U, // MULImmMacro + 0U, // MULOMacro + 0U, // MULOUMacro + 0U, // MultRxRy16 + 0U, // MultRxRyRz16 + 0U, // MultuRxRy16 + 0U, // MultuRxRyRz16 + 0U, // NOP + 0U, // NORImm + 0U, // NORImm64 + 0U, // NOR_V_D_PSEUDO + 0U, // NOR_V_H_PSEUDO + 0U, // NOR_V_W_PSEUDO + 0U, // OR_V_D_PSEUDO + 0U, // OR_V_H_PSEUDO + 0U, // OR_V_W_PSEUDO + 0U, // PseudoCMPU_EQ_QB + 0U, // PseudoCMPU_LE_QB + 0U, // PseudoCMPU_LT_QB + 0U, // PseudoCMP_EQ_PH + 0U, // PseudoCMP_LE_PH + 0U, // PseudoCMP_LT_PH + 0U, // PseudoCVT_D32_W + 0U, // PseudoCVT_D64_L + 0U, // PseudoCVT_D64_W + 0U, // PseudoCVT_S_L + 0U, // PseudoCVT_S_W + 0U, // PseudoDMULT + 0U, // PseudoDMULTu + 0U, // PseudoDSDIV + 0U, // PseudoDUDIV + 0U, // PseudoD_SELECT_I + 0U, // PseudoD_SELECT_I64 + 0U, // PseudoIndirectBranch + 0U, // PseudoIndirectBranch64 + 0U, // PseudoIndirectBranch64R6 + 0U, // PseudoIndirectBranchR6 + 0U, // PseudoIndirectBranch_MM + 0U, // PseudoIndirectBranch_MMR6 + 0U, // PseudoIndirectHazardBranch + 0U, // PseudoIndirectHazardBranch64 + 0U, // PseudoIndrectHazardBranch64R6 + 0U, // PseudoIndrectHazardBranchR6 + 0U, // PseudoMADD + 0U, // PseudoMADDU + 0U, // PseudoMADDU_MM + 0U, // PseudoMADD_MM + 0U, // PseudoMFHI + 0U, // PseudoMFHI64 + 0U, // PseudoMFHI_MM + 0U, // PseudoMFLO + 0U, // PseudoMFLO64 + 0U, // PseudoMFLO_MM + 0U, // PseudoMSUB + 0U, // PseudoMSUBU + 0U, // PseudoMSUBU_MM + 0U, // PseudoMSUB_MM + 0U, // PseudoMTLOHI + 0U, // PseudoMTLOHI64 + 0U, // PseudoMTLOHI_DSP + 0U, // PseudoMTLOHI_MM + 0U, // PseudoMULT + 0U, // PseudoMULT_MM + 0U, // PseudoMULTu + 0U, // PseudoMULTu_MM + 0U, // PseudoPICK_PH + 0U, // PseudoPICK_QB + 0U, // PseudoReturn + 0U, // PseudoReturn64 + 0U, // PseudoSDIV + 0U, // PseudoSELECTFP_F_D32 + 0U, // PseudoSELECTFP_F_D64 + 0U, // PseudoSELECTFP_F_I + 0U, // PseudoSELECTFP_F_I64 + 0U, // PseudoSELECTFP_F_S + 0U, // PseudoSELECTFP_T_D32 + 0U, // PseudoSELECTFP_T_D64 + 0U, // PseudoSELECTFP_T_I + 0U, // PseudoSELECTFP_T_I64 + 0U, // PseudoSELECTFP_T_S + 0U, // PseudoSELECT_D32 + 0U, // PseudoSELECT_D64 + 0U, // PseudoSELECT_I + 0U, // PseudoSELECT_I64 + 0U, // PseudoSELECT_S + 0U, // PseudoTRUNC_W_D + 0U, // PseudoTRUNC_W_D32 + 0U, // PseudoTRUNC_W_S + 0U, // PseudoUDIV + 0U, // ROL + 0U, // ROLImm + 0U, // ROR + 0U, // RORImm + 0U, // RetRA + 0U, // RetRA16 + 0U, // SDC1_M1 + 0U, // SDIV_MM_Pseudo + 0U, // SDMacro + 0U, // SDivIMacro + 0U, // SDivMacro + 0U, // SEQIMacro + 0U, // SEQMacro + 0U, // SGE + 0U, // SGEImm + 0U, // SGEImm64 + 0U, // SGEU + 0U, // SGEUImm + 0U, // SGEUImm64 + 0U, // SGTImm + 0U, // SGTImm64 + 0U, // SGTUImm + 0U, // SGTUImm64 + 0U, // SLE + 0U, // SLEImm + 0U, // SLEImm64 + 0U, // SLEU + 0U, // SLEUImm + 0U, // SLEUImm64 + 0U, // SLTImm64 + 0U, // SLTUImm64 + 0U, // SNEIMacro + 0U, // SNEMacro + 0U, // SNZ_B_PSEUDO + 0U, // SNZ_D_PSEUDO + 0U, // SNZ_H_PSEUDO + 0U, // SNZ_V_PSEUDO + 0U, // SNZ_W_PSEUDO + 0U, // SRemIMacro + 0U, // SRemMacro + 0U, // STORE_ACC128 + 0U, // STORE_ACC64 + 0U, // STORE_ACC64DSP + 0U, // STORE_CCOND_DSP + 0U, // STR_D + 0U, // STR_W + 0U, // ST_F16 + 0U, // SWM_MM + 0U, // SZ_B_PSEUDO + 0U, // SZ_D_PSEUDO + 0U, // SZ_H_PSEUDO + 0U, // SZ_V_PSEUDO + 0U, // SZ_W_PSEUDO + 0U, // SaaAddr + 0U, // SaadAddr + 0U, // SelBeqZ + 0U, // SelBneZ + 0U, // SelTBteqZCmp + 0U, // SelTBteqZCmpi + 0U, // SelTBteqZSlt + 0U, // SelTBteqZSlti + 0U, // SelTBteqZSltiu + 0U, // SelTBteqZSltu + 0U, // SelTBtneZCmp + 0U, // SelTBtneZCmpi + 0U, // SelTBtneZSlt + 0U, // SelTBtneZSlti + 0U, // SelTBtneZSltiu + 0U, // SelTBtneZSltu + 0U, // SltCCRxRy16 + 0U, // SltiCCRxImmX16 + 0U, // SltiuCCRxImmX16 + 0U, // SltuCCRxRy16 + 0U, // SltuRxRyRz16 + 0U, // TAILCALL + 0U, // TAILCALL64R6REG + 0U, // TAILCALLHB64R6REG + 0U, // TAILCALLHBR6REG + 0U, // TAILCALLR6REG + 0U, // TAILCALLREG + 0U, // TAILCALLREG64 + 0U, // TAILCALLREGHB + 0U, // TAILCALLREGHB64 + 0U, // TAILCALLREG_MM + 0U, // TAILCALLREG_MMR6 + 0U, // TAILCALL_MM + 0U, // TAILCALL_MMR6 + 0U, // TRAP + 0U, // TRAP_MM + 0U, // UDIV_MM_Pseudo + 0U, // UDivIMacro + 0U, // UDivMacro + 0U, // URemIMacro + 0U, // URemMacro + 0U, // Ulh + 0U, // Ulhu + 0U, // Ulw + 0U, // Ush + 0U, // Usw + 0U, // XOR_V_D_PSEUDO + 0U, // XOR_V_H_PSEUDO + 0U, // XOR_V_W_PSEUDO + 0U, // ABSQ_S_PH + 0U, // ABSQ_S_PH_MM + 0U, // ABSQ_S_QB + 0U, // ABSQ_S_QB_MMR2 + 0U, // ABSQ_S_W + 0U, // ABSQ_S_W_MM + 0U, // ADD + 0U, // ADDIUPC + 0U, // ADDIUPC_MM + 0U, // ADDIUPC_MMR6 + 0U, // ADDIUR1SP_MM + 0U, // ADDIUR2_MM + 0U, // ADDIUS5_MM + 0U, // ADDIUSP_MM + 0U, // ADDIU_MMR6 + 0U, // ADDQH_PH + 0U, // ADDQH_PH_MMR2 + 0U, // ADDQH_R_PH + 0U, // ADDQH_R_PH_MMR2 + 0U, // ADDQH_R_W + 0U, // ADDQH_R_W_MMR2 + 0U, // ADDQH_W + 0U, // ADDQH_W_MMR2 + 0U, // ADDQ_PH + 0U, // ADDQ_PH_MM + 0U, // ADDQ_S_PH + 0U, // ADDQ_S_PH_MM + 0U, // ADDQ_S_W + 0U, // ADDQ_S_W_MM + 0U, // ADDR_PS64 + 0U, // ADDSC + 0U, // ADDSC_MM + 0U, // ADDS_A_B + 0U, // ADDS_A_D + 0U, // ADDS_A_H + 0U, // ADDS_A_W + 0U, // ADDS_S_B + 0U, // ADDS_S_D + 0U, // ADDS_S_H + 0U, // ADDS_S_W + 0U, // ADDS_U_B + 0U, // ADDS_U_D + 0U, // ADDS_U_H + 0U, // ADDS_U_W + 0U, // ADDU16_MM + 0U, // ADDU16_MMR6 + 0U, // ADDUH_QB + 0U, // ADDUH_QB_MMR2 + 0U, // ADDUH_R_QB + 0U, // ADDUH_R_QB_MMR2 + 0U, // ADDU_MMR6 + 0U, // ADDU_PH + 0U, // ADDU_PH_MMR2 + 0U, // ADDU_QB + 0U, // ADDU_QB_MM + 0U, // ADDU_S_PH + 0U, // ADDU_S_PH_MMR2 + 0U, // ADDU_S_QB + 0U, // ADDU_S_QB_MM + 4U, // ADDVI_B + 4U, // ADDVI_D + 4U, // ADDVI_H + 4U, // ADDVI_W + 0U, // ADDV_B + 0U, // ADDV_D + 0U, // ADDV_H + 0U, // ADDV_W + 0U, // ADDWC + 0U, // ADDWC_MM + 0U, // ADD_A_B + 0U, // ADD_A_D + 0U, // ADD_A_H + 0U, // ADD_A_W + 0U, // ADD_MM + 0U, // ADD_MMR6 + 0U, // ADDi + 0U, // ADDi_MM + 0U, // ADDiu + 0U, // ADDiu_MM + 0U, // ADDu + 0U, // ADDu_MM + 64U, // ALIGN + 64U, // ALIGN_MMR6 + 0U, // ALUIPC + 0U, // ALUIPC_MMR6 + 0U, // AND + 0U, // AND16_MM + 0U, // AND16_MMR6 + 0U, // AND64 + 0U, // ANDI16_MM + 0U, // ANDI16_MMR6 + 6U, // ANDI_B + 8U, // ANDI_MMR6 + 0U, // AND_MM + 0U, // AND_MMR6 + 0U, // AND_V + 8U, // ANDi + 8U, // ANDi64 + 8U, // ANDi_MM + 4U, // APPEND + 4U, // APPEND_MMR2 + 0U, // ASUB_S_B + 0U, // ASUB_S_D + 0U, // ASUB_S_H + 0U, // ASUB_S_W + 0U, // ASUB_U_B + 0U, // ASUB_U_D + 0U, // ASUB_U_H + 0U, // ASUB_U_W + 8U, // AUI + 0U, // AUIPC + 0U, // AUIPC_MMR6 + 8U, // AUI_MMR6 + 0U, // AVER_S_B + 0U, // AVER_S_D + 0U, // AVER_S_H + 0U, // AVER_S_W + 0U, // AVER_U_B + 0U, // AVER_U_D + 0U, // AVER_U_H + 0U, // AVER_U_W + 0U, // AVE_S_B + 0U, // AVE_S_D + 0U, // AVE_S_H + 0U, // AVE_S_W + 0U, // AVE_U_B + 0U, // AVE_U_D + 0U, // AVE_U_H + 0U, // AVE_U_W + 0U, // AddiuRxImmX16 + 0U, // AddiuRxPcImmX16 + 0U, // AddiuRxRxImm16 + 0U, // AddiuRxRxImmX16 + 0U, // AddiuRxRyOffMemX16 + 0U, // AddiuSpImm16 + 0U, // AddiuSpImmX16 + 0U, // AdduRxRyRz16 + 0U, // AndRxRxRy16 + 0U, // B16_MM + 0U, // BADDu + 0U, // BAL + 0U, // BALC + 0U, // BALC_MMR6 + 10U, // BALIGN + 10U, // BALIGN_MMR2 + 0U, // BBIT0 + 0U, // BBIT032 + 0U, // BBIT1 + 0U, // BBIT132 + 0U, // BC + 0U, // BC0F + 0U, // BC0T + 0U, // BC16_MMR6 + 0U, // BC1EQZ + 0U, // BC1EQZC_MMR6 + 0U, // BC1F + 0U, // BC1FL + 0U, // BC1F_MM + 0U, // BC1NEZ + 0U, // BC1NEZC_MMR6 + 0U, // BC1T + 0U, // BC1TL + 0U, // BC1T_MM + 0U, // BC2EQZ + 0U, // BC2EQZC_MMR6 + 0U, // BC2F + 0U, // BC2FL + 0U, // BC2NEZ + 0U, // BC2NEZC_MMR6 + 0U, // BC2T + 0U, // BC2TL + 0U, // BC3F + 0U, // BC3FL + 0U, // BC3T + 0U, // BC3TL + 2U, // BCLRI_B + 12U, // BCLRI_D + 14U, // BCLRI_H + 4U, // BCLRI_W + 0U, // BCLR_B + 0U, // BCLR_D + 0U, // BCLR_H + 0U, // BCLR_W + 0U, // BC_MMR6 + 0U, // BEQ + 0U, // BEQ64 + 0U, // BEQC + 0U, // BEQC64 + 0U, // BEQC_MMR6 + 0U, // BEQL + 0U, // BEQZ16_MM + 0U, // BEQZALC + 0U, // BEQZALC_MMR6 + 0U, // BEQZC + 0U, // BEQZC16_MMR6 + 0U, // BEQZC64 + 0U, // BEQZC_MM + 0U, // BEQZC_MMR6 + 0U, // BEQ_MM + 0U, // BGEC + 0U, // BGEC64 + 0U, // BGEC_MMR6 + 0U, // BGEUC + 0U, // BGEUC64 + 0U, // BGEUC_MMR6 + 0U, // BGEZ + 0U, // BGEZ64 + 0U, // BGEZAL + 0U, // BGEZALC + 0U, // BGEZALC_MMR6 + 0U, // BGEZALL + 0U, // BGEZALS_MM + 0U, // BGEZAL_MM + 0U, // BGEZC + 0U, // BGEZC64 + 0U, // BGEZC_MMR6 + 0U, // BGEZL + 0U, // BGEZ_MM + 0U, // BGTZ + 0U, // BGTZ64 + 0U, // BGTZALC + 0U, // BGTZALC_MMR6 + 0U, // BGTZC + 0U, // BGTZC64 + 0U, // BGTZC_MMR6 + 0U, // BGTZL + 0U, // BGTZ_MM + 16U, // BINSLI_B + 18U, // BINSLI_D + 20U, // BINSLI_H + 22U, // BINSLI_W + 24U, // BINSL_B + 24U, // BINSL_D + 24U, // BINSL_H + 24U, // BINSL_W + 16U, // BINSRI_B + 18U, // BINSRI_D + 20U, // BINSRI_H + 22U, // BINSRI_W + 24U, // BINSR_B + 24U, // BINSR_D + 24U, // BINSR_H + 24U, // BINSR_W + 0U, // BITREV + 0U, // BITREV_MM + 0U, // BITSWAP + 0U, // BITSWAP_MMR6 + 0U, // BLEZ + 0U, // BLEZ64 + 0U, // BLEZALC + 0U, // BLEZALC_MMR6 + 0U, // BLEZC + 0U, // BLEZC64 + 0U, // BLEZC_MMR6 + 0U, // BLEZL + 0U, // BLEZ_MM + 0U, // BLTC + 0U, // BLTC64 + 0U, // BLTC_MMR6 + 0U, // BLTUC + 0U, // BLTUC64 + 0U, // BLTUC_MMR6 + 0U, // BLTZ + 0U, // BLTZ64 + 0U, // BLTZAL + 0U, // BLTZALC + 0U, // BLTZALC_MMR6 + 0U, // BLTZALL + 0U, // BLTZALS_MM + 0U, // BLTZAL_MM + 0U, // BLTZC + 0U, // BLTZC64 + 0U, // BLTZC_MMR6 + 0U, // BLTZL + 0U, // BLTZ_MM + 26U, // BMNZI_B + 24U, // BMNZ_V + 26U, // BMZI_B + 24U, // BMZ_V + 0U, // BNE + 0U, // BNE64 + 0U, // BNEC + 0U, // BNEC64 + 0U, // BNEC_MMR6 + 2U, // BNEGI_B + 12U, // BNEGI_D + 14U, // BNEGI_H + 4U, // BNEGI_W + 0U, // BNEG_B + 0U, // BNEG_D + 0U, // BNEG_H + 0U, // BNEG_W + 0U, // BNEL + 0U, // BNEZ16_MM + 0U, // BNEZALC + 0U, // BNEZALC_MMR6 + 0U, // BNEZC + 0U, // BNEZC16_MMR6 + 0U, // BNEZC64 + 0U, // BNEZC_MM + 0U, // BNEZC_MMR6 + 0U, // BNE_MM + 0U, // BNVC + 0U, // BNVC_MMR6 + 0U, // BNZ_B + 0U, // BNZ_D + 0U, // BNZ_H + 0U, // BNZ_V + 0U, // BNZ_W + 0U, // BOVC + 0U, // BOVC_MMR6 + 0U, // BPOSGE32 + 0U, // BPOSGE32C_MMR3 + 0U, // BPOSGE32_MM + 0U, // BREAK + 0U, // BREAK16_MM + 0U, // BREAK16_MMR6 + 0U, // BREAK_MM + 0U, // BREAK_MMR6 + 26U, // BSELI_B + 24U, // BSEL_V + 2U, // BSETI_B + 12U, // BSETI_D + 14U, // BSETI_H + 4U, // BSETI_W + 0U, // BSET_B + 0U, // BSET_D + 0U, // BSET_H + 0U, // BSET_W + 0U, // BZ_B + 0U, // BZ_D + 0U, // BZ_H + 0U, // BZ_V + 0U, // BZ_W + 0U, // BeqzRxImm16 + 0U, // BeqzRxImmX16 + 0U, // Bimm16 + 0U, // BimmX16 + 0U, // BnezRxImm16 + 0U, // BnezRxImmX16 + 0U, // Break16 + 0U, // Bteqz16 + 0U, // BteqzX16 + 0U, // Btnez16 + 0U, // BtnezX16 + 0U, // CACHE + 0U, // CACHEE + 0U, // CACHEE_MM + 0U, // CACHE_MM + 0U, // CACHE_MMR6 + 0U, // CACHE_R6 + 0U, // CEIL_L_D64 + 0U, // CEIL_L_D_MMR6 + 0U, // CEIL_L_S + 0U, // CEIL_L_S_MMR6 + 0U, // CEIL_W_D32 + 0U, // CEIL_W_D64 + 0U, // CEIL_W_D_MMR6 + 0U, // CEIL_W_MM + 0U, // CEIL_W_S + 0U, // CEIL_W_S_MM + 0U, // CEIL_W_S_MMR6 + 0U, // CEQI_B + 0U, // CEQI_D + 0U, // CEQI_H + 0U, // CEQI_W + 0U, // CEQ_B + 0U, // CEQ_D + 0U, // CEQ_H + 0U, // CEQ_W + 0U, // CFC1 + 0U, // CFC1_MM + 0U, // CFC2_MM + 0U, // CFCMSA + 580U, // CINS + 580U, // CINS32 + 580U, // CINS64_32 + 580U, // CINS_i32 + 0U, // CLASS_D + 0U, // CLASS_D_MMR6 + 0U, // CLASS_S + 0U, // CLASS_S_MMR6 + 0U, // CLEI_S_B + 0U, // CLEI_S_D + 0U, // CLEI_S_H + 0U, // CLEI_S_W + 4U, // CLEI_U_B + 4U, // CLEI_U_D + 4U, // CLEI_U_H + 4U, // CLEI_U_W + 0U, // CLE_S_B + 0U, // CLE_S_D + 0U, // CLE_S_H + 0U, // CLE_S_W + 0U, // CLE_U_B + 0U, // CLE_U_D + 0U, // CLE_U_H + 0U, // CLE_U_W + 0U, // CLO + 0U, // CLO_MM + 0U, // CLO_MMR6 + 0U, // CLO_R6 + 0U, // CLTI_S_B + 0U, // CLTI_S_D + 0U, // CLTI_S_H + 0U, // CLTI_S_W + 4U, // CLTI_U_B + 4U, // CLTI_U_D + 4U, // CLTI_U_H + 4U, // CLTI_U_W + 0U, // CLT_S_B + 0U, // CLT_S_D + 0U, // CLT_S_H + 0U, // CLT_S_W + 0U, // CLT_U_B + 0U, // CLT_U_D + 0U, // CLT_U_H + 0U, // CLT_U_W + 0U, // CLZ + 0U, // CLZ_MM + 0U, // CLZ_MMR6 + 0U, // CLZ_R6 + 0U, // CMPGDU_EQ_QB + 0U, // CMPGDU_EQ_QB_MMR2 + 0U, // CMPGDU_LE_QB + 0U, // CMPGDU_LE_QB_MMR2 + 0U, // CMPGDU_LT_QB + 0U, // CMPGDU_LT_QB_MMR2 + 0U, // CMPGU_EQ_QB + 0U, // CMPGU_EQ_QB_MM + 0U, // CMPGU_LE_QB + 0U, // CMPGU_LE_QB_MM + 0U, // CMPGU_LT_QB + 0U, // CMPGU_LT_QB_MM + 0U, // CMPU_EQ_QB + 0U, // CMPU_EQ_QB_MM + 0U, // CMPU_LE_QB + 0U, // CMPU_LE_QB_MM + 0U, // CMPU_LT_QB + 0U, // CMPU_LT_QB_MM + 0U, // CMP_AF_D_MMR6 + 0U, // CMP_AF_S_MMR6 + 0U, // CMP_EQ_D + 0U, // CMP_EQ_D_MMR6 + 0U, // CMP_EQ_PH + 0U, // CMP_EQ_PH_MM + 0U, // CMP_EQ_S + 0U, // CMP_EQ_S_MMR6 + 0U, // CMP_F_D + 0U, // CMP_F_S + 0U, // CMP_LE_D + 0U, // CMP_LE_D_MMR6 + 0U, // CMP_LE_PH + 0U, // CMP_LE_PH_MM + 0U, // CMP_LE_S + 0U, // CMP_LE_S_MMR6 + 0U, // CMP_LT_D + 0U, // CMP_LT_D_MMR6 + 0U, // CMP_LT_PH + 0U, // CMP_LT_PH_MM + 0U, // CMP_LT_S + 0U, // CMP_LT_S_MMR6 + 0U, // CMP_SAF_D + 0U, // CMP_SAF_D_MMR6 + 0U, // CMP_SAF_S + 0U, // CMP_SAF_S_MMR6 + 0U, // CMP_SEQ_D + 0U, // CMP_SEQ_D_MMR6 + 0U, // CMP_SEQ_S + 0U, // CMP_SEQ_S_MMR6 + 0U, // CMP_SLE_D + 0U, // CMP_SLE_D_MMR6 + 0U, // CMP_SLE_S + 0U, // CMP_SLE_S_MMR6 + 0U, // CMP_SLT_D + 0U, // CMP_SLT_D_MMR6 + 0U, // CMP_SLT_S + 0U, // CMP_SLT_S_MMR6 + 0U, // CMP_SUEQ_D + 0U, // CMP_SUEQ_D_MMR6 + 0U, // CMP_SUEQ_S + 0U, // CMP_SUEQ_S_MMR6 + 0U, // CMP_SULE_D + 0U, // CMP_SULE_D_MMR6 + 0U, // CMP_SULE_S + 0U, // CMP_SULE_S_MMR6 + 0U, // CMP_SULT_D + 0U, // CMP_SULT_D_MMR6 + 0U, // CMP_SULT_S + 0U, // CMP_SULT_S_MMR6 + 0U, // CMP_SUN_D + 0U, // CMP_SUN_D_MMR6 + 0U, // CMP_SUN_S + 0U, // CMP_SUN_S_MMR6 + 0U, // CMP_UEQ_D + 0U, // CMP_UEQ_D_MMR6 + 0U, // CMP_UEQ_S + 0U, // CMP_UEQ_S_MMR6 + 0U, // CMP_ULE_D + 0U, // CMP_ULE_D_MMR6 + 0U, // CMP_ULE_S + 0U, // CMP_ULE_S_MMR6 + 0U, // CMP_ULT_D + 0U, // CMP_ULT_D_MMR6 + 0U, // CMP_ULT_S + 0U, // CMP_ULT_S_MMR6 + 0U, // CMP_UN_D + 0U, // CMP_UN_D_MMR6 + 0U, // CMP_UN_S + 0U, // CMP_UN_S_MMR6 + 142U, // COPY_S_B + 156U, // COPY_S_D + 130U, // COPY_S_H + 138U, // COPY_S_W + 142U, // COPY_U_B + 130U, // COPY_U_H + 138U, // COPY_U_W + 0U, // CRC32B + 0U, // CRC32CB + 0U, // CRC32CD + 0U, // CRC32CH + 0U, // CRC32CW + 0U, // CRC32D + 0U, // CRC32H + 0U, // CRC32W + 0U, // CTC1 + 0U, // CTC1_MM + 0U, // CTC2_MM + 0U, // CTCMSA + 0U, // CVT_D32_S + 0U, // CVT_D32_S_MM + 0U, // CVT_D32_W + 0U, // CVT_D32_W_MM + 0U, // CVT_D64_L + 0U, // CVT_D64_S + 0U, // CVT_D64_S_MM + 0U, // CVT_D64_W + 0U, // CVT_D64_W_MM + 0U, // CVT_D_L_MMR6 + 0U, // CVT_L_D64 + 0U, // CVT_L_D64_MM + 0U, // CVT_L_D_MMR6 + 0U, // CVT_L_S + 0U, // CVT_L_S_MM + 0U, // CVT_L_S_MMR6 + 0U, // CVT_PS_PW64 + 0U, // CVT_PS_S64 + 0U, // CVT_PW_PS64 + 0U, // CVT_S_D32 + 0U, // CVT_S_D32_MM + 0U, // CVT_S_D64 + 0U, // CVT_S_D64_MM + 0U, // CVT_S_L + 0U, // CVT_S_L_MMR6 + 0U, // CVT_S_PL64 + 0U, // CVT_S_PU64 + 0U, // CVT_S_W + 0U, // CVT_S_W_MM + 0U, // CVT_S_W_MMR6 + 0U, // CVT_W_D32 + 0U, // CVT_W_D32_MM + 0U, // CVT_W_D64 + 0U, // CVT_W_D64_MM + 0U, // CVT_W_S + 0U, // CVT_W_S_MM + 0U, // CVT_W_S_MMR6 + 0U, // C_EQ_D32 + 0U, // C_EQ_D32_MM + 0U, // C_EQ_D64 + 0U, // C_EQ_D64_MM + 0U, // C_EQ_S + 0U, // C_EQ_S_MM + 0U, // C_F_D32 + 0U, // C_F_D32_MM + 0U, // C_F_D64 + 0U, // C_F_D64_MM + 0U, // C_F_S + 0U, // C_F_S_MM + 0U, // C_LE_D32 + 0U, // C_LE_D32_MM + 0U, // C_LE_D64 + 0U, // C_LE_D64_MM + 0U, // C_LE_S + 0U, // C_LE_S_MM + 0U, // C_LT_D32 + 0U, // C_LT_D32_MM + 0U, // C_LT_D64 + 0U, // C_LT_D64_MM + 0U, // C_LT_S + 0U, // C_LT_S_MM + 0U, // C_NGE_D32 + 0U, // C_NGE_D32_MM + 0U, // C_NGE_D64 + 0U, // C_NGE_D64_MM + 0U, // C_NGE_S + 0U, // C_NGE_S_MM + 0U, // C_NGLE_D32 + 0U, // C_NGLE_D32_MM + 0U, // C_NGLE_D64 + 0U, // C_NGLE_D64_MM + 0U, // C_NGLE_S + 0U, // C_NGLE_S_MM + 0U, // C_NGL_D32 + 0U, // C_NGL_D32_MM + 0U, // C_NGL_D64 + 0U, // C_NGL_D64_MM + 0U, // C_NGL_S + 0U, // C_NGL_S_MM + 0U, // C_NGT_D32 + 0U, // C_NGT_D32_MM + 0U, // C_NGT_D64 + 0U, // C_NGT_D64_MM + 0U, // C_NGT_S + 0U, // C_NGT_S_MM + 0U, // C_OLE_D32 + 0U, // C_OLE_D32_MM + 0U, // C_OLE_D64 + 0U, // C_OLE_D64_MM + 0U, // C_OLE_S + 0U, // C_OLE_S_MM + 0U, // C_OLT_D32 + 0U, // C_OLT_D32_MM + 0U, // C_OLT_D64 + 0U, // C_OLT_D64_MM + 0U, // C_OLT_S + 0U, // C_OLT_S_MM + 0U, // C_SEQ_D32 + 0U, // C_SEQ_D32_MM + 0U, // C_SEQ_D64 + 0U, // C_SEQ_D64_MM + 0U, // C_SEQ_S + 0U, // C_SEQ_S_MM + 0U, // C_SF_D32 + 0U, // C_SF_D32_MM + 0U, // C_SF_D64 + 0U, // C_SF_D64_MM + 0U, // C_SF_S + 0U, // C_SF_S_MM + 0U, // C_UEQ_D32 + 0U, // C_UEQ_D32_MM + 0U, // C_UEQ_D64 + 0U, // C_UEQ_D64_MM + 0U, // C_UEQ_S + 0U, // C_UEQ_S_MM + 0U, // C_ULE_D32 + 0U, // C_ULE_D32_MM + 0U, // C_ULE_D64 + 0U, // C_ULE_D64_MM + 0U, // C_ULE_S + 0U, // C_ULE_S_MM + 0U, // C_ULT_D32 + 0U, // C_ULT_D32_MM + 0U, // C_ULT_D64 + 0U, // C_ULT_D64_MM + 0U, // C_ULT_S + 0U, // C_ULT_S_MM + 0U, // C_UN_D32 + 0U, // C_UN_D32_MM + 0U, // C_UN_D64 + 0U, // C_UN_D64_MM + 0U, // C_UN_S + 0U, // C_UN_S_MM + 0U, // CmpRxRy16 + 0U, // CmpiRxImm16 + 0U, // CmpiRxImmX16 + 0U, // DADD + 0U, // DADDi + 0U, // DADDiu + 0U, // DADDu + 8U, // DAHI + 1088U, // DALIGN + 8U, // DATI + 8U, // DAUI + 0U, // DBITSWAP + 0U, // DCLO + 0U, // DCLO_R6 + 0U, // DCLZ + 0U, // DCLZ_R6 + 0U, // DDIV + 0U, // DDIVU + 0U, // DERET + 0U, // DERET_MM + 0U, // DERET_MMR6 + 1612U, // DEXT + 2124U, // DEXT64_32 + 2628U, // DEXTM + 222U, // DEXTU + 0U, // DI + 3148U, // DINS + 3652U, // DINSM + 286U, // DINSU + 0U, // DIV + 0U, // DIVU + 0U, // DIVU_MMR6 + 0U, // DIV_MMR6 + 0U, // DIV_S_B + 0U, // DIV_S_D + 0U, // DIV_S_H + 0U, // DIV_S_W + 0U, // DIV_U_B + 0U, // DIV_U_D + 0U, // DIV_U_H + 0U, // DIV_U_W + 0U, // DI_MM + 0U, // DI_MMR6 + 4160U, // DLSA + 4160U, // DLSA_R6 + 2U, // DMFC0 + 0U, // DMFC1 + 2U, // DMFC2 + 0U, // DMFC2_OCTEON + 2U, // DMFGC0 + 0U, // DMOD + 0U, // DMODU + 0U, // DMT + 0U, // DMTC0 + 0U, // DMTC1 + 0U, // DMTC2 + 0U, // DMTC2_OCTEON + 0U, // DMTGC0 + 0U, // DMUH + 0U, // DMUHU + 0U, // DMUL + 0U, // DMULT + 0U, // DMULTu + 0U, // DMULU + 0U, // DMUL_R6 + 0U, // DOTP_S_D + 0U, // DOTP_S_H + 0U, // DOTP_S_W + 0U, // DOTP_U_D + 0U, // DOTP_U_H + 0U, // DOTP_U_W + 24U, // DPADD_S_D + 24U, // DPADD_S_H + 24U, // DPADD_S_W + 24U, // DPADD_U_D + 24U, // DPADD_U_H + 24U, // DPADD_U_W + 0U, // DPAQX_SA_W_PH + 0U, // DPAQX_SA_W_PH_MMR2 + 0U, // DPAQX_S_W_PH + 0U, // DPAQX_S_W_PH_MMR2 + 0U, // DPAQ_SA_L_W + 0U, // DPAQ_SA_L_W_MM + 0U, // DPAQ_S_W_PH + 0U, // DPAQ_S_W_PH_MM + 0U, // DPAU_H_QBL + 0U, // DPAU_H_QBL_MM + 0U, // DPAU_H_QBR + 0U, // DPAU_H_QBR_MM + 0U, // DPAX_W_PH + 0U, // DPAX_W_PH_MMR2 + 0U, // DPA_W_PH + 0U, // DPA_W_PH_MMR2 + 0U, // DPOP + 0U, // DPSQX_SA_W_PH + 0U, // DPSQX_SA_W_PH_MMR2 + 0U, // DPSQX_S_W_PH + 0U, // DPSQX_S_W_PH_MMR2 + 0U, // DPSQ_SA_L_W + 0U, // DPSQ_SA_L_W_MM + 0U, // DPSQ_S_W_PH + 0U, // DPSQ_S_W_PH_MM + 24U, // DPSUB_S_D + 24U, // DPSUB_S_H + 24U, // DPSUB_S_W + 24U, // DPSUB_U_D + 24U, // DPSUB_U_H + 24U, // DPSUB_U_W + 0U, // DPSU_H_QBL + 0U, // DPSU_H_QBL_MM + 0U, // DPSU_H_QBR + 0U, // DPSU_H_QBR_MM + 0U, // DPSX_W_PH + 0U, // DPSX_W_PH_MMR2 + 0U, // DPS_W_PH + 0U, // DPS_W_PH_MMR2 + 12U, // DROTR + 4U, // DROTR32 + 0U, // DROTRV + 0U, // DSBH + 0U, // DSDIV + 0U, // DSHD + 12U, // DSLL + 4U, // DSLL32 + 0U, // DSLL64_32 + 0U, // DSLLV + 12U, // DSRA + 4U, // DSRA32 + 0U, // DSRAV + 12U, // DSRL + 4U, // DSRL32 + 0U, // DSRLV + 0U, // DSUB + 0U, // DSUBu + 0U, // DUDIV + 0U, // DVP + 0U, // DVPE + 0U, // DVP_MMR6 + 0U, // DivRxRy16 + 0U, // DivuRxRy16 + 0U, // EHB + 0U, // EHB_MM + 0U, // EHB_MMR6 + 0U, // EI + 0U, // EI_MM + 0U, // EI_MMR6 + 0U, // EMT + 0U, // ERET + 0U, // ERETNC + 0U, // ERETNC_MMR6 + 0U, // ERET_MM + 0U, // ERET_MMR6 + 0U, // EVP + 0U, // EVPE + 0U, // EVP_MMR6 + 2116U, // EXT + 4U, // EXTP + 4U, // EXTPDP + 0U, // EXTPDPV + 0U, // EXTPDPV_MM + 4U, // EXTPDP_MM + 0U, // EXTPV + 0U, // EXTPV_MM + 4U, // EXTP_MM + 0U, // EXTRV_RS_W + 0U, // EXTRV_RS_W_MM + 0U, // EXTRV_R_W + 0U, // EXTRV_R_W_MM + 0U, // EXTRV_S_H + 0U, // EXTRV_S_H_MM + 0U, // EXTRV_W + 0U, // EXTRV_W_MM + 4U, // EXTR_RS_W + 4U, // EXTR_RS_W_MM + 4U, // EXTR_R_W + 4U, // EXTR_R_W_MM + 4U, // EXTR_S_H + 4U, // EXTR_S_H_MM + 4U, // EXTR_W + 4U, // EXTR_W_MM + 580U, // EXTS + 580U, // EXTS32 + 2116U, // EXT_MM + 2116U, // EXT_MMR6 + 0U, // FABS_D32 + 0U, // FABS_D32_MM + 0U, // FABS_D64 + 0U, // FABS_D64_MM + 0U, // FABS_S + 0U, // FABS_S_MM + 0U, // FADD_D + 0U, // FADD_D32 + 0U, // FADD_D32_MM + 0U, // FADD_D64 + 0U, // FADD_D64_MM + 0U, // FADD_PS64 + 0U, // FADD_S + 0U, // FADD_S_MM + 32U, // FADD_S_MMR6 + 0U, // FADD_W + 0U, // FCAF_D + 0U, // FCAF_W + 0U, // FCEQ_D + 0U, // FCEQ_W + 0U, // FCLASS_D + 0U, // FCLASS_W + 0U, // FCLE_D + 0U, // FCLE_W + 0U, // FCLT_D + 0U, // FCLT_W + 0U, // FCMP_D32 + 0U, // FCMP_D32_MM + 0U, // FCMP_D64 + 0U, // FCMP_S32 + 0U, // FCMP_S32_MM + 0U, // FCNE_D + 0U, // FCNE_W + 0U, // FCOR_D + 0U, // FCOR_W + 0U, // FCUEQ_D + 0U, // FCUEQ_W + 0U, // FCULE_D + 0U, // FCULE_W + 0U, // FCULT_D + 0U, // FCULT_W + 0U, // FCUNE_D + 0U, // FCUNE_W + 0U, // FCUN_D + 0U, // FCUN_W + 0U, // FDIV_D + 0U, // FDIV_D32 + 0U, // FDIV_D32_MM + 0U, // FDIV_D64 + 0U, // FDIV_D64_MM + 0U, // FDIV_S + 0U, // FDIV_S_MM + 32U, // FDIV_S_MMR6 + 0U, // FDIV_W + 0U, // FEXDO_H + 0U, // FEXDO_W + 0U, // FEXP2_D + 0U, // FEXP2_W + 0U, // FEXUPL_D + 0U, // FEXUPL_W + 0U, // FEXUPR_D + 0U, // FEXUPR_W + 0U, // FFINT_S_D + 0U, // FFINT_S_W + 0U, // FFINT_U_D + 0U, // FFINT_U_W + 0U, // FFQL_D + 0U, // FFQL_W + 0U, // FFQR_D + 0U, // FFQR_W + 0U, // FILL_B + 0U, // FILL_D + 0U, // FILL_H + 0U, // FILL_W + 0U, // FLOG2_D + 0U, // FLOG2_W + 0U, // FLOOR_L_D64 + 0U, // FLOOR_L_D_MMR6 + 0U, // FLOOR_L_S + 0U, // FLOOR_L_S_MMR6 + 0U, // FLOOR_W_D32 + 0U, // FLOOR_W_D64 + 0U, // FLOOR_W_D_MMR6 + 0U, // FLOOR_W_MM + 0U, // FLOOR_W_S + 0U, // FLOOR_W_S_MM + 0U, // FLOOR_W_S_MMR6 + 24U, // FMADD_D + 24U, // FMADD_W + 0U, // FMAX_A_D + 0U, // FMAX_A_W + 0U, // FMAX_D + 0U, // FMAX_W + 0U, // FMIN_A_D + 0U, // FMIN_A_W + 0U, // FMIN_D + 0U, // FMIN_W + 0U, // FMOV_D32 + 0U, // FMOV_D32_MM + 0U, // FMOV_D64 + 0U, // FMOV_D64_MM + 0U, // FMOV_D_MMR6 + 0U, // FMOV_S + 0U, // FMOV_S_MM + 0U, // FMOV_S_MMR6 + 24U, // FMSUB_D + 24U, // FMSUB_W + 0U, // FMUL_D + 0U, // FMUL_D32 + 0U, // FMUL_D32_MM + 0U, // FMUL_D64 + 0U, // FMUL_D64_MM + 0U, // FMUL_PS64 + 0U, // FMUL_S + 0U, // FMUL_S_MM + 32U, // FMUL_S_MMR6 + 0U, // FMUL_W + 0U, // FNEG_D32 + 0U, // FNEG_D32_MM + 0U, // FNEG_D64 + 0U, // FNEG_D64_MM + 0U, // FNEG_S + 0U, // FNEG_S_MM + 0U, // FNEG_S_MMR6 + 0U, // FORK + 0U, // FRCP_D + 0U, // FRCP_W + 0U, // FRINT_D + 0U, // FRINT_W + 0U, // FRSQRT_D + 0U, // FRSQRT_W + 0U, // FSAF_D + 0U, // FSAF_W + 0U, // FSEQ_D + 0U, // FSEQ_W + 0U, // FSLE_D + 0U, // FSLE_W + 0U, // FSLT_D + 0U, // FSLT_W + 0U, // FSNE_D + 0U, // FSNE_W + 0U, // FSOR_D + 0U, // FSOR_W + 0U, // FSQRT_D + 0U, // FSQRT_D32 + 0U, // FSQRT_D32_MM + 0U, // FSQRT_D64 + 0U, // FSQRT_D64_MM + 0U, // FSQRT_S + 0U, // FSQRT_S_MM + 0U, // FSQRT_W + 0U, // FSUB_D + 0U, // FSUB_D32 + 0U, // FSUB_D32_MM + 0U, // FSUB_D64 + 0U, // FSUB_D64_MM + 0U, // FSUB_PS64 + 0U, // FSUB_S + 0U, // FSUB_S_MM + 32U, // FSUB_S_MMR6 + 0U, // FSUB_W + 0U, // FSUEQ_D + 0U, // FSUEQ_W + 0U, // FSULE_D + 0U, // FSULE_W + 0U, // FSULT_D + 0U, // FSULT_W + 0U, // FSUNE_D + 0U, // FSUNE_W + 0U, // FSUN_D + 0U, // FSUN_W + 0U, // FTINT_S_D + 0U, // FTINT_S_W + 0U, // FTINT_U_D + 0U, // FTINT_U_W + 0U, // FTQ_H + 0U, // FTQ_W + 0U, // FTRUNC_S_D + 0U, // FTRUNC_S_W + 0U, // FTRUNC_U_D + 0U, // FTRUNC_U_W + 0U, // GINVI + 0U, // GINVI_MMR6 + 0U, // GINVT + 0U, // GINVT_MMR6 + 0U, // HADD_S_D + 0U, // HADD_S_H + 0U, // HADD_S_W + 0U, // HADD_U_D + 0U, // HADD_U_H + 0U, // HADD_U_W + 0U, // HSUB_S_D + 0U, // HSUB_S_H + 0U, // HSUB_S_W + 0U, // HSUB_U_D + 0U, // HSUB_U_H + 0U, // HSUB_U_W + 0U, // HYPCALL + 0U, // HYPCALL_MM + 0U, // ILVEV_B + 0U, // ILVEV_D + 0U, // ILVEV_H + 0U, // ILVEV_W + 0U, // ILVL_B + 0U, // ILVL_D + 0U, // ILVL_H + 0U, // ILVL_W + 0U, // ILVOD_B + 0U, // ILVOD_D + 0U, // ILVOD_H + 0U, // ILVOD_W + 0U, // ILVR_B + 0U, // ILVR_D + 0U, // ILVR_H + 0U, // ILVR_W + 3140U, // INS + 0U, // INSERT_B + 0U, // INSERT_D + 0U, // INSERT_H + 0U, // INSERT_W + 0U, // INSV + 0U, // INSVE_B + 0U, // INSVE_D + 0U, // INSVE_H + 0U, // INSVE_W + 0U, // INSV_MM + 3140U, // INS_MM + 3140U, // INS_MMR6 + 0U, // J + 0U, // JAL + 0U, // JALR + 0U, // JALR16_MM + 0U, // JALR64 + 0U, // JALRC16_MMR6 + 0U, // JALRC_HB_MMR6 + 0U, // JALRC_MMR6 + 0U, // JALRS16_MM + 0U, // JALRS_MM + 0U, // JALR_HB + 0U, // JALR_HB64 + 0U, // JALR_MM + 0U, // JALS_MM + 0U, // JALX + 0U, // JALX_MM + 0U, // JAL_MM + 0U, // JIALC + 0U, // JIALC64 + 0U, // JIALC_MMR6 + 0U, // JIC + 0U, // JIC64 + 0U, // JIC_MMR6 + 0U, // JR + 0U, // JR16_MM + 0U, // JR64 + 0U, // JRADDIUSP + 0U, // JRC16_MM + 0U, // JRC16_MMR6 + 0U, // JRCADDIUSP_MMR6 + 0U, // JR_HB + 0U, // JR_HB64 + 0U, // JR_HB64_R6 + 0U, // JR_HB_R6 + 0U, // JR_MM + 0U, // J_MM + 0U, // Jal16 + 0U, // JalB16 + 0U, // JrRa16 + 0U, // JrcRa16 + 0U, // JrcRx16 + 0U, // JumpLinkReg16 + 0U, // LB + 0U, // LB64 + 0U, // LBE + 0U, // LBE_MM + 0U, // LBU16_MM + 0U, // LBUX + 0U, // LBUX_MM + 0U, // LBU_MMR6 + 0U, // LB_MM + 0U, // LB_MMR6 + 0U, // LBu + 0U, // LBu64 + 0U, // LBuE + 0U, // LBuE_MM + 0U, // LBu_MM + 0U, // LD + 0U, // LDC1 + 0U, // LDC164 + 0U, // LDC1_D64_MMR6 + 0U, // LDC1_MM + 0U, // LDC2 + 0U, // LDC2_MMR6 + 0U, // LDC2_R6 + 0U, // LDC3 + 0U, // LDI_B + 0U, // LDI_D + 0U, // LDI_H + 0U, // LDI_W + 0U, // LDL + 0U, // LDPC + 0U, // LDR + 0U, // LDXC1 + 0U, // LDXC164 + 0U, // LD_B + 0U, // LD_D + 0U, // LD_H + 0U, // LD_W + 0U, // LEA_ADDiu + 0U, // LEA_ADDiu64 + 0U, // LEA_ADDiu_MM + 0U, // LH + 0U, // LH64 + 0U, // LHE + 0U, // LHE_MM + 0U, // LHU16_MM + 0U, // LHX + 0U, // LHX_MM + 0U, // LH_MM + 0U, // LHu + 0U, // LHu64 + 0U, // LHuE + 0U, // LHuE_MM + 0U, // LHu_MM + 0U, // LI16_MM + 0U, // LI16_MMR6 + 0U, // LL + 0U, // LL64 + 0U, // LL64_R6 + 0U, // LLD + 0U, // LLD_R6 + 0U, // LLE + 0U, // LLE_MM + 0U, // LL_MM + 0U, // LL_MMR6 + 0U, // LL_R6 + 4160U, // LSA + 0U, // LSA_MMR6 + 4160U, // LSA_R6 + 0U, // LUI_MMR6 + 0U, // LUXC1 + 0U, // LUXC164 + 0U, // LUXC1_MM + 0U, // LUi + 0U, // LUi64 + 0U, // LUi_MM + 0U, // LW + 0U, // LW16_MM + 0U, // LW64 + 0U, // LWC1 + 0U, // LWC1_MM + 0U, // LWC2 + 0U, // LWC2_MMR6 + 0U, // LWC2_R6 + 0U, // LWC3 + 0U, // LWDSP + 0U, // LWDSP_MM + 0U, // LWE + 0U, // LWE_MM + 0U, // LWGP_MM + 0U, // LWL + 0U, // LWL64 + 0U, // LWLE + 0U, // LWLE_MM + 0U, // LWL_MM + 0U, // LWM16_MM + 0U, // LWM16_MMR6 + 0U, // LWM32_MM + 0U, // LWPC + 0U, // LWPC_MMR6 + 0U, // LWP_MM + 0U, // LWR + 0U, // LWR64 + 0U, // LWRE + 0U, // LWRE_MM + 0U, // LWR_MM + 0U, // LWSP_MM + 0U, // LWUPC + 0U, // LWU_MM + 0U, // LWX + 0U, // LWXC1 + 0U, // LWXC1_MM + 0U, // LWXS_MM + 0U, // LWX_MM + 0U, // LW_MM + 0U, // LW_MMR6 + 0U, // LWu + 0U, // LbRxRyOffMemX16 + 0U, // LbuRxRyOffMemX16 + 0U, // LhRxRyOffMemX16 + 0U, // LhuRxRyOffMemX16 + 0U, // LiRxImm16 + 0U, // LiRxImmAlignX16 + 0U, // LiRxImmX16 + 0U, // LwRxPcTcp16 + 0U, // LwRxPcTcpX16 + 0U, // LwRxRyOffMemX16 + 0U, // LwRxSpImmX16 + 0U, // MADD + 24U, // MADDF_D + 24U, // MADDF_D_MMR6 + 24U, // MADDF_S + 24U, // MADDF_S_MMR6 + 24U, // MADDR_Q_H + 24U, // MADDR_Q_W + 0U, // MADDU + 0U, // MADDU_DSP + 0U, // MADDU_DSP_MM + 0U, // MADDU_MM + 24U, // MADDV_B + 24U, // MADDV_D + 24U, // MADDV_H + 24U, // MADDV_W + 4672U, // MADD_D32 + 4672U, // MADD_D32_MM + 4672U, // MADD_D64 + 0U, // MADD_DSP + 0U, // MADD_DSP_MM + 0U, // MADD_MM + 24U, // MADD_Q_H + 24U, // MADD_Q_W + 4672U, // MADD_S + 4672U, // MADD_S_MM + 0U, // MAQ_SA_W_PHL + 0U, // MAQ_SA_W_PHL_MM + 0U, // MAQ_SA_W_PHR + 0U, // MAQ_SA_W_PHR_MM + 0U, // MAQ_S_W_PHL + 0U, // MAQ_S_W_PHL_MM + 0U, // MAQ_S_W_PHR + 0U, // MAQ_S_W_PHR_MM + 0U, // MAXA_D + 0U, // MAXA_D_MMR6 + 0U, // MAXA_S + 0U, // MAXA_S_MMR6 + 0U, // MAXI_S_B + 0U, // MAXI_S_D + 0U, // MAXI_S_H + 0U, // MAXI_S_W + 4U, // MAXI_U_B + 4U, // MAXI_U_D + 4U, // MAXI_U_H + 4U, // MAXI_U_W + 0U, // MAX_A_B + 0U, // MAX_A_D + 0U, // MAX_A_H + 0U, // MAX_A_W + 0U, // MAX_D + 0U, // MAX_D_MMR6 + 0U, // MAX_S + 0U, // MAX_S_B + 0U, // MAX_S_D + 0U, // MAX_S_H + 0U, // MAX_S_MMR6 + 0U, // MAX_S_W + 0U, // MAX_U_B + 0U, // MAX_U_D + 0U, // MAX_U_H + 0U, // MAX_U_W + 2U, // MFC0 + 2U, // MFC0_MMR6 + 0U, // MFC1 + 0U, // MFC1_D64 + 0U, // MFC1_MM + 0U, // MFC1_MMR6 + 2U, // MFC2 + 0U, // MFC2_MMR6 + 2U, // MFGC0 + 2U, // MFGC0_MM + 2U, // MFHC0_MMR6 + 0U, // MFHC1_D32 + 0U, // MFHC1_D32_MM + 0U, // MFHC1_D64 + 0U, // MFHC1_D64_MM + 0U, // MFHC2_MMR6 + 2U, // MFHGC0 + 2U, // MFHGC0_MM + 0U, // MFHI + 0U, // MFHI16_MM + 0U, // MFHI64 + 0U, // MFHI_DSP + 0U, // MFHI_DSP_MM + 0U, // MFHI_MM + 0U, // MFLO + 0U, // MFLO16_MM + 0U, // MFLO64 + 0U, // MFLO_DSP + 0U, // MFLO_DSP_MM + 0U, // MFLO_MM + 9308U, // MFTR + 0U, // MINA_D + 0U, // MINA_D_MMR6 + 0U, // MINA_S + 0U, // MINA_S_MMR6 + 0U, // MINI_S_B + 0U, // MINI_S_D + 0U, // MINI_S_H + 0U, // MINI_S_W + 4U, // MINI_U_B + 4U, // MINI_U_D + 4U, // MINI_U_H + 4U, // MINI_U_W + 0U, // MIN_A_B + 0U, // MIN_A_D + 0U, // MIN_A_H + 0U, // MIN_A_W + 0U, // MIN_D + 0U, // MIN_D_MMR6 + 0U, // MIN_S + 0U, // MIN_S_B + 0U, // MIN_S_D + 0U, // MIN_S_H + 0U, // MIN_S_MMR6 + 0U, // MIN_S_W + 0U, // MIN_U_B + 0U, // MIN_U_D + 0U, // MIN_U_H + 0U, // MIN_U_W + 0U, // MOD + 0U, // MODSUB + 0U, // MODSUB_MM + 0U, // MODU + 0U, // MODU_MMR6 + 0U, // MOD_MMR6 + 0U, // MOD_S_B + 0U, // MOD_S_D + 0U, // MOD_S_H + 0U, // MOD_S_W + 0U, // MOD_U_B + 0U, // MOD_U_D + 0U, // MOD_U_H + 0U, // MOD_U_W + 0U, // MOVE16_MM + 0U, // MOVE16_MMR6 + 4672U, // MOVEP_MM + 4672U, // MOVEP_MMR6 + 0U, // MOVE_V + 0U, // MOVF_D32 + 0U, // MOVF_D32_MM + 0U, // MOVF_D64 + 0U, // MOVF_I + 0U, // MOVF_I64 + 0U, // MOVF_I_MM + 0U, // MOVF_S + 0U, // MOVF_S_MM + 0U, // MOVN_I64_D64 + 0U, // MOVN_I64_I + 0U, // MOVN_I64_I64 + 0U, // MOVN_I64_S + 0U, // MOVN_I_D32 + 0U, // MOVN_I_D32_MM + 0U, // MOVN_I_D64 + 0U, // MOVN_I_I + 0U, // MOVN_I_I64 + 0U, // MOVN_I_MM + 0U, // MOVN_I_S + 0U, // MOVN_I_S_MM + 0U, // MOVT_D32 + 0U, // MOVT_D32_MM + 0U, // MOVT_D64 + 0U, // MOVT_I + 0U, // MOVT_I64 + 0U, // MOVT_I_MM + 0U, // MOVT_S + 0U, // MOVT_S_MM + 0U, // MOVZ_I64_D64 + 0U, // MOVZ_I64_I + 0U, // MOVZ_I64_I64 + 0U, // MOVZ_I64_S + 0U, // MOVZ_I_D32 + 0U, // MOVZ_I_D32_MM + 0U, // MOVZ_I_D64 + 0U, // MOVZ_I_I + 0U, // MOVZ_I_I64 + 0U, // MOVZ_I_MM + 0U, // MOVZ_I_S + 0U, // MOVZ_I_S_MM + 0U, // MSUB + 24U, // MSUBF_D + 24U, // MSUBF_D_MMR6 + 24U, // MSUBF_S + 24U, // MSUBF_S_MMR6 + 24U, // MSUBR_Q_H + 24U, // MSUBR_Q_W + 0U, // MSUBU + 0U, // MSUBU_DSP + 0U, // MSUBU_DSP_MM + 0U, // MSUBU_MM + 24U, // MSUBV_B + 24U, // MSUBV_D + 24U, // MSUBV_H + 24U, // MSUBV_W + 4672U, // MSUB_D32 + 4672U, // MSUB_D32_MM + 4672U, // MSUB_D64 + 0U, // MSUB_DSP + 0U, // MSUB_DSP_MM + 0U, // MSUB_MM + 24U, // MSUB_Q_H + 24U, // MSUB_Q_W + 4672U, // MSUB_S + 4672U, // MSUB_S_MM + 0U, // MTC0 + 0U, // MTC0_MMR6 + 0U, // MTC1 + 0U, // MTC1_D64 + 0U, // MTC1_D64_MM + 0U, // MTC1_MM + 0U, // MTC1_MMR6 + 0U, // MTC2 + 0U, // MTC2_MMR6 + 0U, // MTGC0 + 0U, // MTGC0_MM + 0U, // MTHC0_MMR6 + 0U, // MTHC1_D32 + 0U, // MTHC1_D32_MM + 0U, // MTHC1_D64 + 0U, // MTHC1_D64_MM + 0U, // MTHC2_MMR6 + 0U, // MTHGC0 + 0U, // MTHGC0_MM + 0U, // MTHI + 0U, // MTHI64 + 0U, // MTHI_DSP + 0U, // MTHI_DSP_MM + 0U, // MTHI_MM + 0U, // MTHLIP + 0U, // MTHLIP_MM + 0U, // MTLO + 0U, // MTLO64 + 0U, // MTLO_DSP + 0U, // MTLO_DSP_MM + 0U, // MTLO_MM + 0U, // MTM0 + 0U, // MTM1 + 0U, // MTM2 + 0U, // MTP0 + 0U, // MTP1 + 0U, // MTP2 + 1U, // MTTR + 0U, // MUH + 0U, // MUHU + 0U, // MUHU_MMR6 + 0U, // MUH_MMR6 + 0U, // MUL + 0U, // MULEQ_S_W_PHL + 0U, // MULEQ_S_W_PHL_MM + 0U, // MULEQ_S_W_PHR + 0U, // MULEQ_S_W_PHR_MM + 0U, // MULEU_S_PH_QBL + 0U, // MULEU_S_PH_QBL_MM + 0U, // MULEU_S_PH_QBR + 0U, // MULEU_S_PH_QBR_MM + 0U, // MULQ_RS_PH + 0U, // MULQ_RS_PH_MM + 0U, // MULQ_RS_W + 0U, // MULQ_RS_W_MMR2 + 0U, // MULQ_S_PH + 0U, // MULQ_S_PH_MMR2 + 0U, // MULQ_S_W + 0U, // MULQ_S_W_MMR2 + 0U, // MULR_PS64 + 0U, // MULR_Q_H + 0U, // MULR_Q_W + 0U, // MULSAQ_S_W_PH + 0U, // MULSAQ_S_W_PH_MM + 0U, // MULSA_W_PH + 0U, // MULSA_W_PH_MMR2 + 0U, // MULT + 0U, // MULTU_DSP + 0U, // MULTU_DSP_MM + 0U, // MULT_DSP + 0U, // MULT_DSP_MM + 0U, // MULT_MM + 0U, // MULTu + 0U, // MULTu_MM + 0U, // MULU + 0U, // MULU_MMR6 + 0U, // MULV_B + 0U, // MULV_D + 0U, // MULV_H + 0U, // MULV_W + 0U, // MUL_MM + 0U, // MUL_MMR6 + 0U, // MUL_PH + 0U, // MUL_PH_MMR2 + 0U, // MUL_Q_H + 0U, // MUL_Q_W + 0U, // MUL_R6 + 0U, // MUL_S_PH + 0U, // MUL_S_PH_MMR2 + 0U, // Mfhi16 + 0U, // Mflo16 + 0U, // Move32R16 + 0U, // MoveR3216 + 0U, // NLOC_B + 0U, // NLOC_D + 0U, // NLOC_H + 0U, // NLOC_W + 0U, // NLZC_B + 0U, // NLZC_D + 0U, // NLZC_H + 0U, // NLZC_W + 4672U, // NMADD_D32 + 4672U, // NMADD_D32_MM + 4672U, // NMADD_D64 + 4672U, // NMADD_S + 4672U, // NMADD_S_MM + 4672U, // NMSUB_D32 + 4672U, // NMSUB_D32_MM + 4672U, // NMSUB_D64 + 4672U, // NMSUB_S + 4672U, // NMSUB_S_MM + 0U, // NOR + 0U, // NOR64 + 6U, // NORI_B + 0U, // NOR_MM + 0U, // NOR_MMR6 + 0U, // NOR_V + 0U, // NOT16_MM + 0U, // NOT16_MMR6 + 0U, // NegRxRy16 + 0U, // NotRxRy16 + 0U, // OR + 0U, // OR16_MM + 0U, // OR16_MMR6 + 0U, // OR64 + 6U, // ORI_B + 8U, // ORI_MMR6 + 0U, // OR_MM + 0U, // OR_MMR6 + 0U, // OR_V + 8U, // ORi + 8U, // ORi64 + 8U, // ORi_MM + 0U, // OrRxRxRy16 + 0U, // PACKRL_PH + 0U, // PACKRL_PH_MM + 0U, // PAUSE + 0U, // PAUSE_MM + 0U, // PAUSE_MMR6 + 0U, // PCKEV_B + 0U, // PCKEV_D + 0U, // PCKEV_H + 0U, // PCKEV_W + 0U, // PCKOD_B + 0U, // PCKOD_D + 0U, // PCKOD_H + 0U, // PCKOD_W + 0U, // PCNT_B + 0U, // PCNT_D + 0U, // PCNT_H + 0U, // PCNT_W + 0U, // PICK_PH + 0U, // PICK_PH_MM + 0U, // PICK_QB + 0U, // PICK_QB_MM + 0U, // PLL_PS64 + 0U, // PLU_PS64 + 0U, // POP + 0U, // PRECEQU_PH_QBL + 0U, // PRECEQU_PH_QBLA + 0U, // PRECEQU_PH_QBLA_MM + 0U, // PRECEQU_PH_QBL_MM + 0U, // PRECEQU_PH_QBR + 0U, // PRECEQU_PH_QBRA + 0U, // PRECEQU_PH_QBRA_MM + 0U, // PRECEQU_PH_QBR_MM + 0U, // PRECEQ_W_PHL + 0U, // PRECEQ_W_PHL_MM + 0U, // PRECEQ_W_PHR + 0U, // PRECEQ_W_PHR_MM + 0U, // PRECEU_PH_QBL + 0U, // PRECEU_PH_QBLA + 0U, // PRECEU_PH_QBLA_MM + 0U, // PRECEU_PH_QBL_MM + 0U, // PRECEU_PH_QBR + 0U, // PRECEU_PH_QBRA + 0U, // PRECEU_PH_QBRA_MM + 0U, // PRECEU_PH_QBR_MM + 0U, // PRECRQU_S_QB_PH + 0U, // PRECRQU_S_QB_PH_MM + 0U, // PRECRQ_PH_W + 0U, // PRECRQ_PH_W_MM + 0U, // PRECRQ_QB_PH + 0U, // PRECRQ_QB_PH_MM + 0U, // PRECRQ_RS_PH_W + 0U, // PRECRQ_RS_PH_W_MM + 0U, // PRECR_QB_PH + 0U, // PRECR_QB_PH_MMR2 + 4U, // PRECR_SRA_PH_W + 4U, // PRECR_SRA_PH_W_MMR2 + 4U, // PRECR_SRA_R_PH_W + 4U, // PRECR_SRA_R_PH_W_MMR2 + 0U, // PREF + 0U, // PREFE + 0U, // PREFE_MM + 0U, // PREFX_MM + 0U, // PREF_MM + 0U, // PREF_MMR6 + 0U, // PREF_R6 + 4U, // PREPEND + 4U, // PREPEND_MMR2 + 0U, // PUL_PS64 + 0U, // PUU_PS64 + 0U, // RADDU_W_QB + 0U, // RADDU_W_QB_MM + 0U, // RDDSP + 0U, // RDDSP_MM + 6U, // RDHWR + 6U, // RDHWR64 + 6U, // RDHWR_MM + 2U, // RDHWR_MMR6 + 0U, // RDPGPR_MMR6 + 0U, // RECIP_D32 + 0U, // RECIP_D32_MM + 0U, // RECIP_D64 + 0U, // RECIP_D64_MM + 0U, // RECIP_S + 0U, // RECIP_S_MM + 0U, // REPLV_PH + 0U, // REPLV_PH_MM + 0U, // REPLV_QB + 0U, // REPLV_QB_MM + 0U, // REPL_PH + 0U, // REPL_PH_MM + 0U, // REPL_QB + 0U, // REPL_QB_MM + 0U, // RINT_D + 0U, // RINT_D_MMR6 + 0U, // RINT_S + 0U, // RINT_S_MMR6 + 4U, // ROTR + 0U, // ROTRV + 0U, // ROTRV_MM + 4U, // ROTR_MM + 0U, // ROUND_L_D64 + 0U, // ROUND_L_D_MMR6 + 0U, // ROUND_L_S + 0U, // ROUND_L_S_MMR6 + 0U, // ROUND_W_D32 + 0U, // ROUND_W_D64 + 0U, // ROUND_W_D_MMR6 + 0U, // ROUND_W_MM + 0U, // ROUND_W_S + 0U, // ROUND_W_S_MM + 0U, // ROUND_W_S_MMR6 + 0U, // RSQRT_D32 + 0U, // RSQRT_D32_MM + 0U, // RSQRT_D64 + 0U, // RSQRT_D64_MM + 0U, // RSQRT_S + 0U, // RSQRT_S_MM + 0U, // Restore16 + 0U, // RestoreX16 + 0U, // SAA + 0U, // SAAD + 2U, // SAT_S_B + 12U, // SAT_S_D + 14U, // SAT_S_H + 4U, // SAT_S_W + 2U, // SAT_U_B + 12U, // SAT_U_D + 14U, // SAT_U_H + 4U, // SAT_U_W + 0U, // SB + 0U, // SB16_MM + 0U, // SB16_MMR6 + 0U, // SB64 + 0U, // SBE + 0U, // SBE_MM + 0U, // SB_MM + 0U, // SB_MMR6 + 0U, // SC + 0U, // SC64 + 0U, // SC64_R6 + 0U, // SCD + 0U, // SCD_R6 + 0U, // SCE + 0U, // SCE_MM + 0U, // SC_MM + 0U, // SC_MMR6 + 0U, // SC_R6 + 0U, // SD + 0U, // SDBBP + 0U, // SDBBP16_MM + 0U, // SDBBP16_MMR6 + 0U, // SDBBP_MM + 0U, // SDBBP_MMR6 + 0U, // SDBBP_R6 + 0U, // SDC1 + 0U, // SDC164 + 0U, // SDC1_D64_MMR6 + 0U, // SDC1_MM + 0U, // SDC2 + 0U, // SDC2_MMR6 + 0U, // SDC2_R6 + 0U, // SDC3 + 0U, // SDIV + 0U, // SDIV_MM + 0U, // SDL + 0U, // SDR + 0U, // SDXC1 + 0U, // SDXC164 + 0U, // SEB + 0U, // SEB64 + 0U, // SEB_MM + 0U, // SEH + 0U, // SEH64 + 0U, // SEH_MM + 0U, // SELEQZ + 0U, // SELEQZ64 + 0U, // SELEQZ_D + 0U, // SELEQZ_D_MMR6 + 0U, // SELEQZ_MMR6 + 0U, // SELEQZ_S + 0U, // SELEQZ_S_MMR6 + 0U, // SELNEZ + 0U, // SELNEZ64 + 0U, // SELNEZ_D + 0U, // SELNEZ_D_MMR6 + 0U, // SELNEZ_MMR6 + 0U, // SELNEZ_S + 0U, // SELNEZ_S_MMR6 + 24U, // SEL_D + 24U, // SEL_D_MMR6 + 24U, // SEL_S + 24U, // SEL_S_MMR6 + 0U, // SEQ + 0U, // SEQi + 0U, // SH + 0U, // SH16_MM + 0U, // SH16_MMR6 + 0U, // SH64 + 0U, // SHE + 0U, // SHE_MM + 6U, // SHF_B + 6U, // SHF_H + 6U, // SHF_W + 0U, // SHILO + 0U, // SHILOV + 0U, // SHILOV_MM + 0U, // SHILO_MM + 0U, // SHLLV_PH + 0U, // SHLLV_PH_MM + 0U, // SHLLV_QB + 0U, // SHLLV_QB_MM + 0U, // SHLLV_S_PH + 0U, // SHLLV_S_PH_MM + 0U, // SHLLV_S_W + 0U, // SHLLV_S_W_MM + 14U, // SHLL_PH + 14U, // SHLL_PH_MM + 2U, // SHLL_QB + 2U, // SHLL_QB_MM + 14U, // SHLL_S_PH + 14U, // SHLL_S_PH_MM + 4U, // SHLL_S_W + 4U, // SHLL_S_W_MM + 0U, // SHRAV_PH + 0U, // SHRAV_PH_MM + 0U, // SHRAV_QB + 0U, // SHRAV_QB_MMR2 + 0U, // SHRAV_R_PH + 0U, // SHRAV_R_PH_MM + 0U, // SHRAV_R_QB + 0U, // SHRAV_R_QB_MMR2 + 0U, // SHRAV_R_W + 0U, // SHRAV_R_W_MM + 14U, // SHRA_PH + 14U, // SHRA_PH_MM + 2U, // SHRA_QB + 2U, // SHRA_QB_MMR2 + 14U, // SHRA_R_PH + 14U, // SHRA_R_PH_MM + 2U, // SHRA_R_QB + 2U, // SHRA_R_QB_MMR2 + 4U, // SHRA_R_W + 4U, // SHRA_R_W_MM + 0U, // SHRLV_PH + 0U, // SHRLV_PH_MMR2 + 0U, // SHRLV_QB + 0U, // SHRLV_QB_MM + 14U, // SHRL_PH + 14U, // SHRL_PH_MMR2 + 2U, // SHRL_QB + 2U, // SHRL_QB_MM + 0U, // SH_MM + 0U, // SH_MMR6 + 0U, // SIGRIE + 0U, // SIGRIE_MMR6 + 148U, // SLDI_B + 34U, // SLDI_D + 144U, // SLDI_H + 36U, // SLDI_W + 152U, // SLD_B + 152U, // SLD_D + 152U, // SLD_H + 152U, // SLD_W + 4U, // SLL + 0U, // SLL16_MM + 0U, // SLL16_MMR6 + 1U, // SLL64_32 + 1U, // SLL64_64 + 2U, // SLLI_B + 12U, // SLLI_D + 14U, // SLLI_H + 4U, // SLLI_W + 0U, // SLLV + 0U, // SLLV_MM + 0U, // SLL_B + 0U, // SLL_D + 0U, // SLL_H + 4U, // SLL_MM + 4U, // SLL_MMR6 + 0U, // SLL_W + 0U, // SLT + 0U, // SLT64 + 0U, // SLT_MM + 0U, // SLTi + 0U, // SLTi64 + 0U, // SLTi_MM + 0U, // SLTiu + 0U, // SLTiu64 + 0U, // SLTiu_MM + 0U, // SLTu + 0U, // SLTu64 + 0U, // SLTu_MM + 0U, // SNE + 0U, // SNEi + 142U, // SPLATI_B + 156U, // SPLATI_D + 130U, // SPLATI_H + 138U, // SPLATI_W + 128U, // SPLAT_B + 128U, // SPLAT_D + 128U, // SPLAT_H + 128U, // SPLAT_W + 4U, // SRA + 2U, // SRAI_B + 12U, // SRAI_D + 14U, // SRAI_H + 4U, // SRAI_W + 2U, // SRARI_B + 12U, // SRARI_D + 14U, // SRARI_H + 4U, // SRARI_W + 0U, // SRAR_B + 0U, // SRAR_D + 0U, // SRAR_H + 0U, // SRAR_W + 0U, // SRAV + 0U, // SRAV_MM + 0U, // SRA_B + 0U, // SRA_D + 0U, // SRA_H + 4U, // SRA_MM + 0U, // SRA_W + 4U, // SRL + 0U, // SRL16_MM + 0U, // SRL16_MMR6 + 2U, // SRLI_B + 12U, // SRLI_D + 14U, // SRLI_H + 4U, // SRLI_W + 2U, // SRLRI_B + 12U, // SRLRI_D + 14U, // SRLRI_H + 4U, // SRLRI_W + 0U, // SRLR_B + 0U, // SRLR_D + 0U, // SRLR_H + 0U, // SRLR_W + 0U, // SRLV + 0U, // SRLV_MM + 0U, // SRL_B + 0U, // SRL_D + 0U, // SRL_H + 4U, // SRL_MM + 0U, // SRL_W + 0U, // SSNOP + 0U, // SSNOP_MM + 0U, // SSNOP_MMR6 + 0U, // ST_B + 0U, // ST_D + 0U, // ST_H + 0U, // ST_W + 0U, // SUB + 0U, // SUBQH_PH + 0U, // SUBQH_PH_MMR2 + 0U, // SUBQH_R_PH + 0U, // SUBQH_R_PH_MMR2 + 0U, // SUBQH_R_W + 0U, // SUBQH_R_W_MMR2 + 0U, // SUBQH_W + 0U, // SUBQH_W_MMR2 + 0U, // SUBQ_PH + 0U, // SUBQ_PH_MM + 0U, // SUBQ_S_PH + 0U, // SUBQ_S_PH_MM + 0U, // SUBQ_S_W + 0U, // SUBQ_S_W_MM + 0U, // SUBSUS_U_B + 0U, // SUBSUS_U_D + 0U, // SUBSUS_U_H + 0U, // SUBSUS_U_W + 0U, // SUBSUU_S_B + 0U, // SUBSUU_S_D + 0U, // SUBSUU_S_H + 0U, // SUBSUU_S_W + 0U, // SUBS_S_B + 0U, // SUBS_S_D + 0U, // SUBS_S_H + 0U, // SUBS_S_W + 0U, // SUBS_U_B + 0U, // SUBS_U_D + 0U, // SUBS_U_H + 0U, // SUBS_U_W + 0U, // SUBU16_MM + 0U, // SUBU16_MMR6 + 0U, // SUBUH_QB + 0U, // SUBUH_QB_MMR2 + 0U, // SUBUH_R_QB + 0U, // SUBUH_R_QB_MMR2 + 0U, // SUBU_MMR6 + 0U, // SUBU_PH + 0U, // SUBU_PH_MMR2 + 0U, // SUBU_QB + 0U, // SUBU_QB_MM + 0U, // SUBU_S_PH + 0U, // SUBU_S_PH_MMR2 + 0U, // SUBU_S_QB + 0U, // SUBU_S_QB_MM + 4U, // SUBVI_B + 4U, // SUBVI_D + 4U, // SUBVI_H + 4U, // SUBVI_W + 0U, // SUBV_B + 0U, // SUBV_D + 0U, // SUBV_H + 0U, // SUBV_W + 0U, // SUB_MM + 0U, // SUB_MMR6 + 0U, // SUBu + 0U, // SUBu_MM + 0U, // SUXC1 + 0U, // SUXC164 + 0U, // SUXC1_MM + 0U, // SW + 0U, // SW16_MM + 0U, // SW16_MMR6 + 0U, // SW64 + 0U, // SWC1 + 0U, // SWC1_MM + 0U, // SWC2 + 0U, // SWC2_MMR6 + 0U, // SWC2_R6 + 0U, // SWC3 + 0U, // SWDSP + 0U, // SWDSP_MM + 0U, // SWE + 0U, // SWE_MM + 0U, // SWL + 0U, // SWL64 + 0U, // SWLE + 0U, // SWLE_MM + 0U, // SWL_MM + 0U, // SWM16_MM + 0U, // SWM16_MMR6 + 0U, // SWM32_MM + 0U, // SWP_MM + 0U, // SWR + 0U, // SWR64 + 0U, // SWRE + 0U, // SWRE_MM + 0U, // SWR_MM + 0U, // SWSP_MM + 0U, // SWSP_MMR6 + 0U, // SWXC1 + 0U, // SWXC1_MM + 0U, // SW_MM + 0U, // SW_MMR6 + 0U, // SYNC + 0U, // SYNCI + 0U, // SYNCI_MM + 0U, // SYNCI_MMR6 + 0U, // SYNC_MM + 0U, // SYNC_MMR6 + 0U, // SYSCALL + 0U, // SYSCALL_MM + 0U, // Save16 + 0U, // SaveX16 + 0U, // SbRxRyOffMemX16 + 0U, // SebRx16 + 0U, // SehRx16 + 0U, // ShRxRyOffMemX16 + 4U, // SllX16 + 0U, // SllvRxRy16 + 0U, // SltRxRy16 + 0U, // SltiRxImm16 + 0U, // SltiRxImmX16 + 0U, // SltiuRxImm16 + 0U, // SltiuRxImmX16 + 0U, // SltuRxRy16 + 4U, // SraX16 + 0U, // SravRxRy16 + 4U, // SrlX16 + 0U, // SrlvRxRy16 + 0U, // SubuRxRyRz16 + 0U, // SwRxRyOffMemX16 + 0U, // SwRxSpImmX16 + 38U, // TEQ + 0U, // TEQI + 0U, // TEQI_MM + 14U, // TEQ_MM + 38U, // TGE + 0U, // TGEI + 0U, // TGEIU + 0U, // TGEIU_MM + 0U, // TGEI_MM + 38U, // TGEU + 14U, // TGEU_MM + 14U, // TGE_MM + 0U, // TLBGINV + 0U, // TLBGINVF + 0U, // TLBGINVF_MM + 0U, // TLBGINV_MM + 0U, // TLBGP + 0U, // TLBGP_MM + 0U, // TLBGR + 0U, // TLBGR_MM + 0U, // TLBGWI + 0U, // TLBGWI_MM + 0U, // TLBGWR + 0U, // TLBGWR_MM + 0U, // TLBINV + 0U, // TLBINVF + 0U, // TLBINVF_MMR6 + 0U, // TLBINV_MMR6 + 0U, // TLBP + 0U, // TLBP_MM + 0U, // TLBR + 0U, // TLBR_MM + 0U, // TLBWI + 0U, // TLBWI_MM + 0U, // TLBWR + 0U, // TLBWR_MM + 38U, // TLT + 0U, // TLTI + 0U, // TLTIU_MM + 0U, // TLTI_MM + 38U, // TLTU + 14U, // TLTU_MM + 14U, // TLT_MM + 38U, // TNE + 0U, // TNEI + 0U, // TNEI_MM + 14U, // TNE_MM + 0U, // TRUNC_L_D64 + 0U, // TRUNC_L_D_MMR6 + 0U, // TRUNC_L_S + 0U, // TRUNC_L_S_MMR6 + 0U, // TRUNC_W_D32 + 0U, // TRUNC_W_D64 + 0U, // TRUNC_W_D_MMR6 + 0U, // TRUNC_W_MM + 0U, // TRUNC_W_S + 0U, // TRUNC_W_S_MM + 0U, // TRUNC_W_S_MMR6 + 0U, // TTLTIU + 0U, // UDIV + 0U, // UDIV_MM + 0U, // V3MULU + 0U, // VMM0 + 0U, // VMULU + 24U, // VSHF_B + 24U, // VSHF_D + 24U, // VSHF_H + 24U, // VSHF_W + 0U, // WAIT + 0U, // WAIT_MM + 0U, // WAIT_MMR6 + 0U, // WRDSP + 0U, // WRDSP_MM + 0U, // WRPGPR_MMR6 + 0U, // WSBH + 0U, // WSBH_MM + 0U, // WSBH_MMR6 + 0U, // XOR + 0U, // XOR16_MM + 0U, // XOR16_MMR6 + 0U, // XOR64 + 6U, // XORI_B + 8U, // XORI_MMR6 + 0U, // XOR_MM + 0U, // XOR_MMR6 + 0U, // XOR_V + 8U, // XORi + 8U, // XORi64 + 8U, // XORi_MM + 0U, // XorRxRxRy16 + 0U, // YIELD + }; + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + return createMnemonic(AsmStrs + (Bits & 16383) - 1, Bits); +} +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) { + MCMnemonic MnemonicInfo = Mips_getMnemonic(MI); + +#ifndef CAPSTONE_DIET + + SStream_concat0(O, MnemonicInfo.first); +#endif + + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 4 bits for 15 unique commands. + switch ((Bits >> 14) & 15) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 2: + // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, MultRxRyRz1... + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 3: + // LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ... + printRegisterList /* printRegisterList (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printMemOperand /* printMemOperand (+ ) */ (MI, 1, O, ""); + return; + break; + case 4: + // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 5: + // AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT... + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + break; + case 6: + // BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM... + printUImm /* printUImm<10> (+ ) */ (MI, 0, O, 10); + break; + case 7: + // BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6 + printUImm /* printUImm<4> (+ ) */ (MI, 0, O, 4); + return; + break; + case 8: + // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... + printUImm /* printUImm<5> (+ ) */ (MI, 2, O, 5); + SStream_concat0(O, ", "); + break; + case 9: + // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM + printFCCOperand /* printFCCOperand (+ ) */ (MI, 2, O); + break; + case 10: + // Jal16, JalB16 + printUImm /* printUImm<26> (+ ) */ (MI, 0, O, 26); + break; + case 11: + // SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL + printUImm /* printUImm<20> (+ ) */ (MI, 0, O, 20); + return; + break; + case 12: + // SIGRIE, SIGRIE_MMR6 + printUImm /* printUImm<16> (+ ) */ (MI, 0, O, 16); + return; + break; + case 13: + // SYNC, SYNC_MM, SYNC_MMR6 + printUImm /* printUImm<5> (+ ) */ (MI, 0, O, 5); + return; + break; + case 14: + // SYNCI, SYNCI_MM, SYNCI_MMR6 + printMemOperand /* printMemOperand (+ ) */ (MI, 0, O, ""); + return; + break; + } + + // Fragment 1 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 18) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... + SStream_concat0(O, ", "); + break; + case 1: + // B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MTTDSP, ADD... + return; + break; + case 2: + // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, CTC1, CTC1_... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 3: + // LwConstant32 + SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "\n2:"); + return; + break; + case 4: + // MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 5: + // SelBeqZ, SelBneZ + SStream_concat0(O, ", .+4\n\t\n\tmove "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 6: + // AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 7: + // AddiuRxPcImmX16 + SStream_concat0(O, ", $pc, "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 8: + // AddiuSpImm16, Bimm16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 9: + // Bteqz16, Btnez16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 10: + // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,... + printMemOperand /* printMemOperand (+ ) */ (MI, 0, O, ""); + return; + break; + case 11: + // FCMP_D32, FCMP_D32_MM, FCMP_D64 + SStream_concat0(O, ".d\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 12: + // FCMP_S32, FCMP_S32_MM + SStream_concat0(O, ".s\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 13: + // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... + SStream_concat0(O, "["); + break; + case 14: + // Jal16 + SStream_concat0(O, "\n\tnop"); + return; + break; + case 15: + // JalB16 + SStream_concat0(O, "\t# branch\n\tnop"); + return; + break; + case 16: + // SAA, SAAD + SStream_concat0(O, ", ("); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + case 17: + // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6 + printMemOperand /* printMemOperand (+ ) */ (MI, 2, O, ""); + return; + break; + } + + // Fragment 2 encoded into 5 bits for 25 unique commands. + switch ((Bits >> 23) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 1: + // CTTC1, MTTACX, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, ADDIUS5_MM, AND16_... + return; + break; + case 2: + // GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 3: + // LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA... + printMemOperand /* printMemOperand (+ ) */ (MI, 1, O, ""); + return; + break; + case 4: + // MTTC0, DMTC0, DMTC2, DMTGC0, FORK, LSA_MMR6, MTC0, MTC0_MMR6, MTC2, MT... + SStream_concat0(O, ", "); + break; + case 5: + // MultRxRyRz16, MultuRxRyRz16 + SStream_concat0(O, "\n\tmflo\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 6: + // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... + printOperand /* printOperand (+ ) */ (MI, 4, O); + break; + case 7: + // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... + SStream_concat0(O, "\n\tmove\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", $t8"); + return; + break; + case 8: + // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM + printMemOperandEA /* printMemOperandEA (+ ) */ (MI, 1, O, ""); + return; + break; + case 9: + // BBIT0, BBIT032, BBIT1, BBIT132 + printUImm /* printUImm<5> (+ ) */ (MI, 1, O, 5); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 10: + // BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP + printUImm /* printUImm<10> (+ ) */ (MI, 1, O, 10); + return; + break; + case 11: + // DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM + printUImm /* printUImm<16> (+ ) */ (MI, 1, O, 16); + return; + break; + case 12: + // GINVT, GINVT_MMR6 + printUImm /* printUImm<2> (+ ) */ (MI, 1, O, 2); + return; + break; + case 13: + // INSERT_B + printUImm /* printUImm<4> (+ ) */ (MI, 3, O, 4); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 14: + // INSERT_D + printUImm /* printUImm<1> (+ ) */ (MI, 3, O, 1); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 15: + // INSERT_H + printUImm /* printUImm<3> (+ ) */ (MI, 3, O, 3); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 16: + // INSERT_W + printUImm /* printUImm<2> (+ ) */ (MI, 3, O, 2); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 17: + // INSVE_B + printUImm /* printUImm<4> (+ ) */ (MI, 2, O, 4); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "["); + printUImm /* printUImm<0> (+ ) */ (MI, 4, O, 0); + SStream_concat0(O, "]"); + return; + break; + case 18: + // INSVE_D + printUImm /* printUImm<1> (+ ) */ (MI, 2, O, 1); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "["); + printUImm /* printUImm<0> (+ ) */ (MI, 4, O, 0); + SStream_concat0(O, "]"); + return; + break; + case 19: + // INSVE_H + printUImm /* printUImm<3> (+ ) */ (MI, 2, O, 3); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "["); + printUImm /* printUImm<0> (+ ) */ (MI, 4, O, 0); + SStream_concat0(O, "]"); + return; + break; + case 20: + // INSVE_W + printUImm /* printUImm<2> (+ ) */ (MI, 2, O, 2); + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "["); + printUImm /* printUImm<0> (+ ) */ (MI, 4, O, 0); + SStream_concat0(O, "]"); + return; + break; + case 21: + // LWP_MM, SWP_MM + printMemOperand /* printMemOperand (+ ) */ (MI, 2, O, ""); + return; + break; + case 22: + // PREFX_MM + SStream_concat0(O, "("); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ")"); + return; + break; + case 23: + // RDDSP_MM, WRDSP_MM + printUImm /* printUImm<7> (+ ) */ (MI, 1, O, 7); + return; + break; + case 24: + // REPL_QB, REPL_QB_MM + printUImm /* printUImm<8> (+ ) */ (MI, 1, O, 8); + return; + break; + } + + // Fragment 3 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 28) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ABSMacro, CFTC1, JalTwoReg, LoadAddrImm32, LoadAddrImm64, LoadImm32, L... + return; + break; + case 1: + // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... + SStream_concat0(O, ", "); + break; + case 2: + // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... + SStream_concat0(O, "\n\tbteqz\t"); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 3: + // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... + SStream_concat0(O, "\n\tbtnez\t"); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 4: + // GotPrologue16 + SStream_concat0(O, "\n\taddiu\t"); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", $pc, "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, "\n "); + return; + break; + case 5: + // MTTC0, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, MTGC0_MM, M... + printUImm /* printUImm<3> (+ ) */ (MI, 2, O, 3); + return; + break; + case 6: + // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... + SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 7: + // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... + SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 8: + // AddiuRxRxImm16, LwRxPcTcp16 + SStream_concat0(O, "\t# 16 bit inst"); + return; + break; + case 9: + // BeqzRxImm16, BnezRxImm16 + SStream_concat0(O, " # 16 bit inst"); + return; + break; + case 10: + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... + SStream_concat0(O, "["); + break; + case 11: + // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 + SStream_concat0(O, " \t# 16 bit inst"); + return; + break; + case 12: + // DSLL64_32 + SStream_concat0(O, ", 32"); + return; + break; + case 13: + // FORK + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 14: + // LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ... + SStream_concat0(O, "("); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + case 15: + // LSA_MMR6 + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printUImm /* printUImm<2, 1> (+ ) */ (MI, 3, O, 2, 1); + return; + break; + case 16: + // MTTR + printUImm /* printUImm<1> (+ ) */ (MI, 2, O, 1); + SStream_concat0(O, ", "); + printUImm /* printUImm<3> (+ ) */ (MI, 3, O, 3); + SStream_concat0(O, ", "); + printUImm /* printUImm<1> (+ ) */ (MI, 4, O, 1); + return; + break; + case 17: + // SLL64_32, SLL64_64 + SStream_concat0(O, ", 0"); + return; + break; + } + + // Fragment 4 encoded into 5 bits for 20 unique commands. + switch ((Bits >> 33) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 1: + // MFTC0, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0, DMFC2, DM... + printUImm /* printUImm<3> (+ ) */ (MI, 2, O, 3); + break; + case 2: + // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG... + printUImm /* printUImm<5> (+ ) */ (MI, 2, O, 5); + break; + case 3: + // ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, SHF_H, SHF_W, ... + printUImm /* printUImm<8> (+ ) */ (MI, 2, O, 8); + return; + break; + case 4: + // ANDI_MMR6, ANDi, ANDi64, ANDi_MM, AUI, AUI_MMR6, DAHI, DATI, DAUI, ORI... + printUImm /* printUImm<16> (+ ) */ (MI, 2, O, 16); + return; + break; + case 5: + // BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W + printUImm /* printUImm<2> (+ ) */ (MI, 2, O, 2); + break; + case 6: + // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D... + printUImm /* printUImm<6> (+ ) */ (MI, 2, O, 6); + break; + case 7: + // BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_... + printUImm /* printUImm<4> (+ ) */ (MI, 2, O, 4); + break; + case 8: + // BINSLI_B, BINSRI_B, SLDI_H + printUImm /* printUImm<3> (+ ) */ (MI, 3, O, 3); + break; + case 9: + // BINSLI_D, BINSRI_D + printUImm /* printUImm<6> (+ ) */ (MI, 3, O, 6); + return; + break; + case 10: + // BINSLI_H, BINSRI_H, SLDI_B + printUImm /* printUImm<4> (+ ) */ (MI, 3, O, 4); + break; + case 11: + // BINSLI_W, BINSRI_W + printUImm /* printUImm<5> (+ ) */ (MI, 3, O, 5); + return; + break; + case 12: + // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 13: + // BMNZI_B, BMZI_B, BSELI_B + printUImm /* printUImm<8> (+ ) */ (MI, 3, O, 8); + return; + break; + case 14: + // COPY_S_D, MFTR, SPLATI_D + printUImm /* printUImm<1> (+ ) */ (MI, 2, O, 1); + break; + case 15: + // DEXTU, DINSU + printUImm /* printUImm<5, 32> (+ ) */ (MI, 2, O, 5, 32); + SStream_concat0(O, ", "); + break; + case 16: + // FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6 + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 17: + // SLDI_D + printUImm /* printUImm<1> (+ ) */ (MI, 3, O, 1); + SStream_concat0(O, "]"); + return; + break; + case 18: + // SLDI_W + printUImm /* printUImm<2> (+ ) */ (MI, 3, O, 2); + SStream_concat0(O, "]"); + return; + break; + case 19: + // TEQ, TGE, TGEU, TLT, TLTU, TNE + printUImm /* printUImm<10> (+ ) */ (MI, 2, O, 10); + return; + break; + } + + // Fragment 5 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 38) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro... + return; + break; + case 1: + // ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN, DEXT, DE... + SStream_concat0(O, ", "); + break; + case 2: + // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ... + SStream_concat0(O, "]"); + return; + break; + case 3: + // DEXTU + printUImm /* printUImm<5, 1> (+ ) */ (MI, 3, O, 5, 1); + return; + break; + case 4: + // DINSU + printUImm /* printUImm<6> (+ ) */ (MI, 3, O, 6); + return; + break; + } + + // Fragment 6 encoded into 4 bits for 10 unique commands. + switch ((Bits >> 41) & 15) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ALIGN, ALIGN_MMR6 + printUImm /* printUImm<2> (+ ) */ (MI, 3, O, 2); + return; + break; + case 1: + // CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32 + printUImm /* printUImm<5> (+ ) */ (MI, 3, O, 5); + return; + break; + case 2: + // DALIGN, MFTR + printUImm /* printUImm<3> (+ ) */ (MI, 3, O, 3); + break; + case 3: + // DEXT + printUImm /* printUImm<6, 1> (+ ) */ (MI, 3, O, 6, 1); + return; + break; + case 4: + // DEXT64_32, EXT, EXT_MM, EXT_MMR6 + printUImm /* printUImm<5, 1> (+ ) */ (MI, 3, O, 5, 1); + return; + break; + case 5: + // DEXTM + printUImm /* printUImm<5, 33> (+ ) */ (MI, 3, O, 5, 33); + return; + break; + case 6: + // DINS, INS, INS_MM, INS_MMR6 + printUImm /* printUImm<6> (+ ) */ (MI, 3, O, 6); + return; + break; + case 7: + // DINSM + printUImm /* printUImm<6, 2> (+ ) */ (MI, 3, O, 6, 2); + return; + break; + case 8: + // DLSA, DLSA_R6, LSA, LSA_R6 + printUImm /* printUImm<2, 1> (+ ) */ (MI, 3, O, 2, 1); + return; + break; + case 9: + // MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MOVEP_MM, MOVEP_MM... + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + } + + // Fragment 7 encoded into 1 bits for 2 unique commands. + if ((Bits >> 45) & 1) { + // MFTR + SStream_concat0(O, ", "); + printUImm /* printUImm<1> (+ ) */ (MI, 4, O, 1); + return; + } else { + // DALIGN + return; + } +} + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo) { + assert(RegNo && RegNo < 442 && "Invalid register number!"); + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = {/* 0 */ "f10\0" + /* 4 */ "w10\0" + /* 8 */ "f20\0" + /* 12 */ "DSPOutFlag20\0" + /* 25 */ "w20\0" + /* 29 */ "f30\0" + /* 33 */ "w30\0" + /* 37 */ "ac0\0" + /* 41 */ "fcc0\0" + /* 46 */ "f0\0" + /* 49 */ "mpl0\0" + /* 54 */ "p0\0" + /* 57 */ "w0\0" + /* 60 */ "f11\0" + /* 64 */ "w11\0" + /* 68 */ "f21\0" + /* 72 */ "DSPOutFlag21\0" + /* 85 */ "w21\0" + /* 89 */ "f31\0" + /* 93 */ "w31\0" + /* 97 */ "ac1\0" + /* 101 */ "fcc1\0" + /* 106 */ "f1\0" + /* 109 */ "mpl1\0" + /* 114 */ "p1\0" + /* 117 */ "w1\0" + /* 120 */ "f12\0" + /* 124 */ "w12\0" + /* 128 */ "f22\0" + /* 132 */ "DSPOutFlag22\0" + /* 145 */ "w22\0" + /* 149 */ "ac2\0" + /* 153 */ "fcc2\0" + /* 158 */ "f2\0" + /* 161 */ "mpl2\0" + /* 166 */ "p2\0" + /* 169 */ "w2\0" + /* 172 */ "f13\0" + /* 176 */ "w13\0" + /* 180 */ "f23\0" + /* 184 */ "DSPOutFlag23\0" + /* 197 */ "w23\0" + /* 201 */ "ac3\0" + /* 205 */ "fcc3\0" + /* 210 */ "f3\0" + /* 213 */ "w3\0" + /* 216 */ "f14\0" + /* 220 */ "w14\0" + /* 224 */ "f24\0" + /* 228 */ "w24\0" + /* 232 */ "fcc4\0" + /* 237 */ "f4\0" + /* 240 */ "w4\0" + /* 243 */ "f15\0" + /* 247 */ "w15\0" + /* 251 */ "f25\0" + /* 255 */ "w25\0" + /* 259 */ "fcc5\0" + /* 264 */ "f5\0" + /* 267 */ "w5\0" + /* 270 */ "f16\0" + /* 274 */ "w16\0" + /* 278 */ "f26\0" + /* 282 */ "w26\0" + /* 286 */ "fcc6\0" + /* 291 */ "f6\0" + /* 294 */ "w6\0" + /* 297 */ "f17\0" + /* 301 */ "w17\0" + /* 305 */ "f27\0" + /* 309 */ "w27\0" + /* 313 */ "fcc7\0" + /* 318 */ "f7\0" + /* 321 */ "w7\0" + /* 324 */ "f18\0" + /* 328 */ "w18\0" + /* 332 */ "f28\0" + /* 336 */ "w28\0" + /* 340 */ "f8\0" + /* 343 */ "w8\0" + /* 346 */ "DSPOutFlag16_19\0" + /* 362 */ "f19\0" + /* 366 */ "w19\0" + /* 370 */ "f29\0" + /* 374 */ "w29\0" + /* 378 */ "f9\0" + /* 381 */ "w9\0" + /* 384 */ "DSPEFI\0" + /* 391 */ "ra\0" + /* 394 */ "hwr_cc\0" + /* 401 */ "pc\0" + /* 404 */ "DSPCCond\0" + /* 413 */ "DSPOutFlag\0" + /* 424 */ "hi\0" + /* 427 */ "hwr_cpunum\0" + /* 438 */ "lo\0" + /* 441 */ "zero\0" + /* 446 */ "hwr_synci_step\0" + /* 461 */ "fp\0" + /* 464 */ "gp\0" + /* 467 */ "sp\0" + /* 470 */ "hwr_ccres\0" + /* 480 */ "DSPPos\0" + /* 487 */ "DSPSCount\0" + /* 497 */ "DSPCarry\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint16_t RegAsmOffset[] = { + 62, 404, 497, 384, 413, 480, 487, 461, 464, 122, 62, 2, 272, 218, 245, + 174, 299, 401, 391, 467, 441, 218, 245, 272, 299, 37, 97, 149, 201, 62, + 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, + 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, + 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, + 252, 279, 306, 333, 371, 30, 90, 1, 61, 121, 173, 217, 244, 271, 298, + 325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 1, + 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, + 279, 306, 333, 371, 30, 90, 46, 158, 237, 291, 340, 0, 120, 216, 270, + 324, 8, 128, 224, 278, 332, 29, 12, 72, 132, 184, 46, 106, 158, 210, + 237, 264, 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, + 362, 8, 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 41, 101, + 153, 205, 232, 259, 286, 313, 2, 62, 122, 174, 218, 245, 272, 299, 326, + 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, + 225, 252, 279, 306, 333, 371, 30, 90, 461, 46, 106, 158, 210, 237, 264, + 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, + 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 464, 37, 97, 149, + 201, 427, 446, 394, 470, 218, 245, 272, 299, 326, 360, 1, 61, 121, 173, + 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, + 371, 30, 90, 279, 306, 37, 97, 149, 201, 49, 109, 161, 326, 360, 1, + 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, + 279, 306, 333, 371, 30, 90, 54, 114, 166, 391, 271, 298, 325, 359, 9, + 69, 129, 181, 467, 326, 360, 1, 61, 121, 173, 217, 244, 225, 252, 122, + 174, 57, 117, 169, 213, 240, 267, 294, 321, 343, 381, 4, 64, 124, 176, + 220, 247, 274, 301, 328, 366, 25, 85, 145, 197, 228, 255, 282, 309, 336, + 374, 33, 93, 441, 218, 245, 272, 299, 37, 46, 106, 158, 210, 237, 264, + 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, + 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 346, 424, 279, 306, + 438, 271, 298, 325, 359, 9, 69, 129, 181, 326, 360, 1, 61, 121, 173, + 217, 244, 225, 252, 122, 174, + }; + + assert(*(AsmStrs + RegAsmOffset[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrs + RegAsmOffset[RegNo - 1]; +} +#endif +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +static char *printAliasInstr(MCInst *MI, SStream *OS) { + static const PatternsForOpcode OpToPatterns[] = { + {Mips_MFTACX, 0, 1}, + {Mips_MFTC0, 1, 1}, + {Mips_MFTHI, 2, 1}, + {Mips_MFTLO, 3, 1}, + {Mips_MTTACX, 4, 1}, + {Mips_MTTC0, 5, 1}, + {Mips_MTTHI, 6, 1}, + {Mips_MTTLO, 7, 1}, + {Mips_NORImm, 8, 1}, + {Mips_NORImm64, 9, 1}, + {Mips_SLTImm64, 10, 1}, + {Mips_SLTUImm64, 11, 1}, + {Mips_ADDIUPC, 12, 1}, + {Mips_ADDIUPC_MMR6, 13, 1}, + {Mips_ADDu, 14, 1}, + {Mips_BC1F, 15, 1}, + {Mips_BC1FL, 16, 1}, + {Mips_BC1F_MM, 17, 1}, + {Mips_BC1T, 18, 1}, + {Mips_BC1TL, 19, 1}, + {Mips_BC1T_MM, 20, 1}, + {Mips_BC2F, 21, 1}, + {Mips_BC2FL, 22, 1}, + {Mips_BC2T, 23, 1}, + {Mips_BC2TL, 24, 1}, + {Mips_BC3F, 25, 1}, + {Mips_BC3FL, 26, 1}, + {Mips_BC3T, 27, 1}, + {Mips_BC3TL, 28, 1}, + {Mips_BEQL, 29, 1}, + {Mips_BGEZAL, 30, 1}, + {Mips_BGEZAL_MM, 31, 1}, + {Mips_BNEL, 32, 1}, + {Mips_BREAK, 33, 2}, + {Mips_BREAK_MM, 35, 2}, + {Mips_C_EQ_D32, 37, 1}, + {Mips_C_EQ_D32_MM, 38, 1}, + {Mips_C_EQ_D64, 39, 1}, + {Mips_C_EQ_D64_MM, 40, 1}, + {Mips_C_EQ_S, 41, 1}, + {Mips_C_EQ_S_MM, 42, 1}, + {Mips_C_F_D32, 43, 1}, + {Mips_C_F_D32_MM, 44, 1}, + {Mips_C_F_D64, 45, 1}, + {Mips_C_F_D64_MM, 46, 1}, + {Mips_C_F_S, 47, 1}, + {Mips_C_F_S_MM, 48, 1}, + {Mips_C_LE_D32, 49, 1}, + {Mips_C_LE_D32_MM, 50, 1}, + {Mips_C_LE_D64, 51, 1}, + {Mips_C_LE_D64_MM, 52, 1}, + {Mips_C_LE_S, 53, 1}, + {Mips_C_LE_S_MM, 54, 1}, + {Mips_C_LT_D32, 55, 1}, + {Mips_C_LT_D32_MM, 56, 1}, + {Mips_C_LT_D64, 57, 1}, + {Mips_C_LT_D64_MM, 58, 1}, + {Mips_C_LT_S, 59, 1}, + {Mips_C_LT_S_MM, 60, 1}, + {Mips_C_NGE_D32, 61, 1}, + {Mips_C_NGE_D32_MM, 62, 1}, + {Mips_C_NGE_D64, 63, 1}, + {Mips_C_NGE_D64_MM, 64, 1}, + {Mips_C_NGE_S, 65, 1}, + {Mips_C_NGE_S_MM, 66, 1}, + {Mips_C_NGLE_D32, 67, 1}, + {Mips_C_NGLE_D32_MM, 68, 1}, + {Mips_C_NGLE_D64, 69, 1}, + {Mips_C_NGLE_D64_MM, 70, 1}, + {Mips_C_NGLE_S, 71, 1}, + {Mips_C_NGLE_S_MM, 72, 1}, + {Mips_C_NGL_D32, 73, 1}, + {Mips_C_NGL_D32_MM, 74, 1}, + {Mips_C_NGL_D64, 75, 1}, + {Mips_C_NGL_D64_MM, 76, 1}, + {Mips_C_NGL_S, 77, 1}, + {Mips_C_NGL_S_MM, 78, 1}, + {Mips_C_NGT_D32, 79, 1}, + {Mips_C_NGT_D32_MM, 80, 1}, + {Mips_C_NGT_D64, 81, 1}, + {Mips_C_NGT_D64_MM, 82, 1}, + {Mips_C_NGT_S, 83, 1}, + {Mips_C_NGT_S_MM, 84, 1}, + {Mips_C_OLE_D32, 85, 1}, + {Mips_C_OLE_D32_MM, 86, 1}, + {Mips_C_OLE_D64, 87, 1}, + {Mips_C_OLE_D64_MM, 88, 1}, + {Mips_C_OLE_S, 89, 1}, + {Mips_C_OLE_S_MM, 90, 1}, + {Mips_C_OLT_D32, 91, 1}, + {Mips_C_OLT_D32_MM, 92, 1}, + {Mips_C_OLT_D64, 93, 1}, + {Mips_C_OLT_D64_MM, 94, 1}, + {Mips_C_OLT_S, 95, 1}, + {Mips_C_OLT_S_MM, 96, 1}, + {Mips_C_SEQ_D32, 97, 1}, + {Mips_C_SEQ_D32_MM, 98, 1}, + {Mips_C_SEQ_D64, 99, 1}, + {Mips_C_SEQ_D64_MM, 100, 1}, + {Mips_C_SEQ_S, 101, 1}, + {Mips_C_SEQ_S_MM, 102, 1}, + {Mips_C_SF_D32, 103, 1}, + {Mips_C_SF_D32_MM, 104, 1}, + {Mips_C_SF_D64, 105, 1}, + {Mips_C_SF_D64_MM, 106, 1}, + {Mips_C_SF_S, 107, 1}, + {Mips_C_SF_S_MM, 108, 1}, + {Mips_C_UEQ_D32, 109, 1}, + {Mips_C_UEQ_D32_MM, 110, 1}, + {Mips_C_UEQ_D64, 111, 1}, + {Mips_C_UEQ_D64_MM, 112, 1}, + {Mips_C_UEQ_S, 113, 1}, + {Mips_C_UEQ_S_MM, 114, 1}, + {Mips_C_ULE_D32, 115, 1}, + {Mips_C_ULE_D32_MM, 116, 1}, + {Mips_C_ULE_D64, 117, 1}, + {Mips_C_ULE_D64_MM, 118, 1}, + {Mips_C_ULE_S, 119, 1}, + {Mips_C_ULE_S_MM, 120, 1}, + {Mips_C_ULT_D32, 121, 1}, + {Mips_C_ULT_D32_MM, 122, 1}, + {Mips_C_ULT_D64, 123, 1}, + {Mips_C_ULT_D64_MM, 124, 1}, + {Mips_C_ULT_S, 125, 1}, + {Mips_C_ULT_S_MM, 126, 1}, + {Mips_C_UN_D32, 127, 1}, + {Mips_C_UN_D32_MM, 128, 1}, + {Mips_C_UN_D64, 129, 1}, + {Mips_C_UN_D64_MM, 130, 1}, + {Mips_C_UN_S, 131, 1}, + {Mips_C_UN_S_MM, 132, 1}, + {Mips_DADDu, 133, 1}, + {Mips_DI, 134, 1}, + {Mips_DIV, 135, 1}, + {Mips_DIVU, 136, 1}, + {Mips_DI_MM, 137, 1}, + {Mips_DI_MMR6, 138, 1}, + {Mips_DMT, 139, 1}, + {Mips_DSUB, 140, 2}, + {Mips_DSUBu, 142, 2}, + {Mips_DVPE, 144, 1}, + {Mips_EI, 145, 1}, + {Mips_EI_MM, 146, 1}, + {Mips_EI_MMR6, 147, 1}, + {Mips_EMT, 148, 1}, + {Mips_EVPE, 149, 1}, + {Mips_HYPCALL, 150, 1}, + {Mips_HYPCALL_MM, 151, 1}, + {Mips_JALR, 152, 1}, + {Mips_JALR64, 153, 1}, + {Mips_JALRC_HB_MMR6, 154, 1}, + {Mips_JALRC_MMR6, 155, 1}, + {Mips_JALR_HB, 156, 1}, + {Mips_JALR_HB64, 157, 1}, + {Mips_JIALC, 158, 1}, + {Mips_JIALC64, 159, 1}, + {Mips_JIC, 160, 1}, + {Mips_JIC64, 161, 1}, + {Mips_MOVE16_MM, 162, 1}, + {Mips_Move32R16, 163, 1}, + {Mips_OR, 164, 1}, + {Mips_OR64, 165, 1}, + {Mips_RDHWR, 166, 1}, + {Mips_RDHWR64, 167, 1}, + {Mips_RDHWR_MM, 168, 1}, + {Mips_RDHWR_MMR6, 169, 1}, + {Mips_SDBBP, 170, 1}, + {Mips_SDBBP_MMR6, 171, 1}, + {Mips_SDBBP_R6, 172, 1}, + {Mips_SIGRIE, 173, 1}, + {Mips_SIGRIE_MMR6, 174, 1}, + {Mips_SLL, 175, 1}, + {Mips_SLL_MM, 176, 1}, + {Mips_SLL_MMR6, 177, 1}, + {Mips_SUB, 178, 2}, + {Mips_SUBU_MMR6, 180, 2}, + {Mips_SUB_MM, 182, 2}, + {Mips_SUB_MMR6, 184, 2}, + {Mips_SUBu, 186, 2}, + {Mips_SUBu_MM, 188, 2}, + {Mips_SWSP_MM, 190, 1}, + {Mips_SYNC, 191, 1}, + {Mips_SYNC_MM, 192, 1}, + {Mips_SYNC_MMR6, 193, 1}, + {Mips_SYSCALL, 194, 1}, + {Mips_SYSCALL_MM, 195, 1}, + {Mips_TEQ, 196, 1}, + {Mips_TEQ_MM, 197, 1}, + {Mips_TGE, 198, 1}, + {Mips_TGEU, 199, 1}, + {Mips_TGEU_MM, 200, 1}, + {Mips_TGE_MM, 201, 1}, + {Mips_TLT, 202, 1}, + {Mips_TLTU, 203, 1}, + {Mips_TLTU_MM, 204, 1}, + {Mips_TLT_MM, 205, 1}, + {Mips_TNE, 206, 1}, + {Mips_TNE_MM, 207, 1}, + {Mips_WAIT_MM, 208, 1}, + {Mips_WRDSP, 209, 1}, + {Mips_WRDSP_MM, 210, 1}, + {Mips_YIELD, 211, 1}, + }; + + static const AliasPattern Patterns[] = { + // Mips::MFTACX - 0 + {0, 0, 2, 2}, + // Mips::MFTC0 - 1 + {10, 2, 3, 3}, + // Mips::MFTHI - 2 + {23, 5, 2, 2}, + // Mips::MFTLO - 3 + {32, 7, 2, 2}, + // Mips::MTTACX - 4 + {41, 9, 2, 2}, + // Mips::MTTC0 - 5 + {51, 11, 3, 3}, + // Mips::MTTHI - 6 + {64, 14, 2, 2}, + // Mips::MTTLO - 7 + {73, 16, 2, 2}, + // Mips::NORImm - 8 + {82, 18, 3, 2}, + // Mips::NORImm64 - 9 + {82, 20, 3, 2}, + // Mips::SLTImm64 - 10 + {93, 22, 3, 2}, + // Mips::SLTUImm64 - 11 + {104, 24, 3, 2}, + // Mips::ADDIUPC - 12 + {116, 26, 2, 1}, + // Mips::ADDIUPC_MMR6 - 13 + {116, 27, 2, 1}, + // Mips::ADDu - 14 + {128, 28, 3, 3}, + // Mips::BC1F - 15 + {140, 31, 2, 1}, + // Mips::BC1FL - 16 + {148, 32, 2, 1}, + // Mips::BC1F_MM - 17 + {140, 33, 2, 1}, + // Mips::BC1T - 18 + {157, 34, 2, 1}, + // Mips::BC1TL - 19 + {165, 35, 2, 1}, + // Mips::BC1T_MM - 20 + {157, 36, 2, 1}, + // Mips::BC2F - 21 + {174, 37, 2, 1}, + // Mips::BC2FL - 22 + {182, 38, 2, 1}, + // Mips::BC2T - 23 + {191, 39, 2, 1}, + // Mips::BC2TL - 24 + {199, 40, 2, 1}, + // Mips::BC3F - 25 + {208, 41, 2, 1}, + // Mips::BC3FL - 26 + {216, 42, 2, 1}, + // Mips::BC3T - 27 + {225, 43, 2, 1}, + // Mips::BC3TL - 28 + {233, 44, 2, 1}, + // Mips::BEQL - 29 + {242, 45, 3, 2}, + // Mips::BGEZAL - 30 + {255, 47, 2, 1}, + // Mips::BGEZAL_MM - 31 + {255, 48, 2, 1}, + // Mips::BNEL - 32 + {262, 49, 3, 2}, + // Mips::BREAK - 33 + {275, 51, 2, 2}, + {281, 53, 2, 2}, + // Mips::BREAK_MM - 35 + {275, 55, 2, 2}, + {281, 57, 2, 2}, + // Mips::C_EQ_D32 - 37 + {292, 59, 3, 3}, + // Mips::C_EQ_D32_MM - 38 + {292, 62, 3, 3}, + // Mips::C_EQ_D64 - 39 + {292, 65, 3, 3}, + // Mips::C_EQ_D64_MM - 40 + {292, 68, 3, 3}, + // Mips::C_EQ_S - 41 + {306, 71, 3, 3}, + // Mips::C_EQ_S_MM - 42 + {306, 74, 3, 3}, + // Mips::C_F_D32 - 43 + {320, 77, 3, 3}, + // Mips::C_F_D32_MM - 44 + {320, 80, 3, 3}, + // Mips::C_F_D64 - 45 + {320, 83, 3, 3}, + // Mips::C_F_D64_MM - 46 + {320, 86, 3, 3}, + // Mips::C_F_S - 47 + {333, 89, 3, 3}, + // Mips::C_F_S_MM - 48 + {333, 92, 3, 3}, + // Mips::C_LE_D32 - 49 + {346, 95, 3, 3}, + // Mips::C_LE_D32_MM - 50 + {346, 98, 3, 3}, + // Mips::C_LE_D64 - 51 + {346, 101, 3, 3}, + // Mips::C_LE_D64_MM - 52 + {346, 104, 3, 3}, + // Mips::C_LE_S - 53 + {360, 107, 3, 3}, + // Mips::C_LE_S_MM - 54 + {360, 110, 3, 3}, + // Mips::C_LT_D32 - 55 + {374, 113, 3, 3}, + // Mips::C_LT_D32_MM - 56 + {374, 116, 3, 3}, + // Mips::C_LT_D64 - 57 + {374, 119, 3, 3}, + // Mips::C_LT_D64_MM - 58 + {374, 122, 3, 3}, + // Mips::C_LT_S - 59 + {388, 125, 3, 3}, + // Mips::C_LT_S_MM - 60 + {388, 128, 3, 3}, + // Mips::C_NGE_D32 - 61 + {402, 131, 3, 3}, + // Mips::C_NGE_D32_MM - 62 + {402, 134, 3, 3}, + // Mips::C_NGE_D64 - 63 + {402, 137, 3, 3}, + // Mips::C_NGE_D64_MM - 64 + {402, 140, 3, 3}, + // Mips::C_NGE_S - 65 + {417, 143, 3, 3}, + // Mips::C_NGE_S_MM - 66 + {417, 146, 3, 3}, + // Mips::C_NGLE_D32 - 67 + {432, 149, 3, 3}, + // Mips::C_NGLE_D32_MM - 68 + {432, 152, 3, 3}, + // Mips::C_NGLE_D64 - 69 + {432, 155, 3, 3}, + // Mips::C_NGLE_D64_MM - 70 + {432, 158, 3, 3}, + // Mips::C_NGLE_S - 71 + {448, 161, 3, 3}, + // Mips::C_NGLE_S_MM - 72 + {448, 164, 3, 3}, + // Mips::C_NGL_D32 - 73 + {464, 167, 3, 3}, + // Mips::C_NGL_D32_MM - 74 + {464, 170, 3, 3}, + // Mips::C_NGL_D64 - 75 + {464, 173, 3, 3}, + // Mips::C_NGL_D64_MM - 76 + {464, 176, 3, 3}, + // Mips::C_NGL_S - 77 + {479, 179, 3, 3}, + // Mips::C_NGL_S_MM - 78 + {479, 182, 3, 3}, + // Mips::C_NGT_D32 - 79 + {494, 185, 3, 3}, + // Mips::C_NGT_D32_MM - 80 + {494, 188, 3, 3}, + // Mips::C_NGT_D64 - 81 + {494, 191, 3, 3}, + // Mips::C_NGT_D64_MM - 82 + {494, 194, 3, 3}, + // Mips::C_NGT_S - 83 + {509, 197, 3, 3}, + // Mips::C_NGT_S_MM - 84 + {509, 200, 3, 3}, + // Mips::C_OLE_D32 - 85 + {524, 203, 3, 3}, + // Mips::C_OLE_D32_MM - 86 + {524, 206, 3, 3}, + // Mips::C_OLE_D64 - 87 + {524, 209, 3, 3}, + // Mips::C_OLE_D64_MM - 88 + {524, 212, 3, 3}, + // Mips::C_OLE_S - 89 + {539, 215, 3, 3}, + // Mips::C_OLE_S_MM - 90 + {539, 218, 3, 3}, + // Mips::C_OLT_D32 - 91 + {554, 221, 3, 3}, + // Mips::C_OLT_D32_MM - 92 + {554, 224, 3, 3}, + // Mips::C_OLT_D64 - 93 + {554, 227, 3, 3}, + // Mips::C_OLT_D64_MM - 94 + {554, 230, 3, 3}, + // Mips::C_OLT_S - 95 + {569, 233, 3, 3}, + // Mips::C_OLT_S_MM - 96 + {569, 236, 3, 3}, + // Mips::C_SEQ_D32 - 97 + {584, 239, 3, 3}, + // Mips::C_SEQ_D32_MM - 98 + {584, 242, 3, 3}, + // Mips::C_SEQ_D64 - 99 + {584, 245, 3, 3}, + // Mips::C_SEQ_D64_MM - 100 + {584, 248, 3, 3}, + // Mips::C_SEQ_S - 101 + {599, 251, 3, 3}, + // Mips::C_SEQ_S_MM - 102 + {599, 254, 3, 3}, + // Mips::C_SF_D32 - 103 + {614, 257, 3, 3}, + // Mips::C_SF_D32_MM - 104 + {614, 260, 3, 3}, + // Mips::C_SF_D64 - 105 + {614, 263, 3, 3}, + // Mips::C_SF_D64_MM - 106 + {614, 266, 3, 3}, + // Mips::C_SF_S - 107 + {628, 269, 3, 3}, + // Mips::C_SF_S_MM - 108 + {628, 272, 3, 3}, + // Mips::C_UEQ_D32 - 109 + {642, 275, 3, 3}, + // Mips::C_UEQ_D32_MM - 110 + {642, 278, 3, 3}, + // Mips::C_UEQ_D64 - 111 + {642, 281, 3, 3}, + // Mips::C_UEQ_D64_MM - 112 + {642, 284, 3, 3}, + // Mips::C_UEQ_S - 113 + {657, 287, 3, 3}, + // Mips::C_UEQ_S_MM - 114 + {657, 290, 3, 3}, + // Mips::C_ULE_D32 - 115 + {672, 293, 3, 3}, + // Mips::C_ULE_D32_MM - 116 + {672, 296, 3, 3}, + // Mips::C_ULE_D64 - 117 + {672, 299, 3, 3}, + // Mips::C_ULE_D64_MM - 118 + {672, 302, 3, 3}, + // Mips::C_ULE_S - 119 + {687, 305, 3, 3}, + // Mips::C_ULE_S_MM - 120 + {687, 308, 3, 3}, + // Mips::C_ULT_D32 - 121 + {702, 311, 3, 3}, + // Mips::C_ULT_D32_MM - 122 + {702, 314, 3, 3}, + // Mips::C_ULT_D64 - 123 + {702, 317, 3, 3}, + // Mips::C_ULT_D64_MM - 124 + {702, 320, 3, 3}, + // Mips::C_ULT_S - 125 + {717, 323, 3, 3}, + // Mips::C_ULT_S_MM - 126 + {717, 326, 3, 3}, + // Mips::C_UN_D32 - 127 + {732, 329, 3, 3}, + // Mips::C_UN_D32_MM - 128 + {732, 332, 3, 3}, + // Mips::C_UN_D64 - 129 + {732, 335, 3, 3}, + // Mips::C_UN_D64_MM - 130 + {732, 338, 3, 3}, + // Mips::C_UN_S - 131 + {746, 341, 3, 3}, + // Mips::C_UN_S_MM - 132 + {746, 344, 3, 3}, + // Mips::DADDu - 133 + {128, 347, 3, 3}, + // Mips::DI - 134 + {760, 350, 1, 1}, + // Mips::DIV - 135 + {763, 351, 3, 3}, + // Mips::DIVU - 136 + {774, 354, 3, 3}, + // Mips::DI_MM - 137 + {760, 357, 1, 1}, + // Mips::DI_MMR6 - 138 + {760, 358, 1, 1}, + // Mips::DMT - 139 + {786, 359, 1, 1}, + // Mips::DSUB - 140 + {790, 360, 3, 3}, + {802, 363, 3, 3}, + // Mips::DSUBu - 142 + {810, 366, 3, 3}, + {823, 369, 3, 3}, + // Mips::DVPE - 144 + {832, 372, 1, 1}, + // Mips::EI - 145 + {837, 373, 1, 1}, + // Mips::EI_MM - 146 + {837, 374, 1, 1}, + // Mips::EI_MMR6 - 147 + {837, 375, 1, 1}, + // Mips::EMT - 148 + {840, 376, 1, 1}, + // Mips::EVPE - 149 + {844, 377, 1, 1}, + // Mips::HYPCALL - 150 + {849, 378, 1, 1}, + // Mips::HYPCALL_MM - 151 + {849, 379, 1, 1}, + // Mips::JALR - 152 + {857, 380, 2, 2}, + // Mips::JALR64 - 153 + {857, 382, 2, 2}, + // Mips::JALRC_HB_MMR6 - 154 + {863, 384, 2, 2}, + // Mips::JALRC_MMR6 - 155 + {875, 386, 2, 2}, + // Mips::JALR_HB - 156 + {884, 388, 2, 2}, + // Mips::JALR_HB64 - 157 + {884, 390, 2, 2}, + // Mips::JIALC - 158 + {895, 392, 2, 2}, + // Mips::JIALC64 - 159 + {895, 394, 2, 2}, + // Mips::JIC - 160 + {904, 396, 2, 2}, + // Mips::JIC64 - 161 + {904, 398, 2, 2}, + // Mips::MOVE16_MM - 162 + {911, 400, 2, 2}, + // Mips::Move32R16 - 163 + {911, 402, 2, 2}, + // Mips::OR - 164 + {128, 404, 3, 3}, + // Mips::OR64 - 165 + {128, 407, 3, 3}, + // Mips::RDHWR - 166 + {915, 410, 3, 3}, + // Mips::RDHWR64 - 167 + {915, 413, 3, 3}, + // Mips::RDHWR_MM - 168 + {915, 416, 3, 3}, + // Mips::RDHWR_MMR6 - 169 + {915, 419, 3, 3}, + // Mips::SDBBP - 170 + {928, 422, 1, 1}, + // Mips::SDBBP_MMR6 - 171 + {928, 423, 1, 1}, + // Mips::SDBBP_R6 - 172 + {928, 424, 1, 1}, + // Mips::SIGRIE - 173 + {934, 425, 1, 1}, + // Mips::SIGRIE_MMR6 - 174 + {934, 426, 1, 1}, + // Mips::SLL - 175 + {911, 427, 3, 3}, + // Mips::SLL_MM - 176 + {911, 430, 3, 3}, + // Mips::SLL_MMR6 - 177 + {911, 433, 3, 3}, + // Mips::SUB - 178 + {941, 436, 3, 3}, + {952, 439, 3, 3}, + // Mips::SUBU_MMR6 - 180 + {959, 442, 3, 3}, + {971, 445, 3, 3}, + // Mips::SUB_MM - 182 + {941, 448, 3, 3}, + {952, 451, 3, 3}, + // Mips::SUB_MMR6 - 184 + {941, 454, 3, 3}, + {952, 457, 3, 3}, + // Mips::SUBu - 186 + {959, 460, 3, 3}, + {971, 463, 3, 3}, + // Mips::SUBu_MM - 188 + {959, 466, 3, 3}, + {971, 469, 3, 3}, + // Mips::SWSP_MM - 190 + {979, 472, 3, 1}, + // Mips::SYNC - 191 + {991, 473, 1, 1}, + // Mips::SYNC_MM - 192 + {991, 474, 1, 1}, + // Mips::SYNC_MMR6 - 193 + {991, 475, 1, 1}, + // Mips::SYSCALL - 194 + {996, 476, 1, 1}, + // Mips::SYSCALL_MM - 195 + {996, 477, 1, 1}, + // Mips::TEQ - 196 + {1004, 478, 3, 3}, + // Mips::TEQ_MM - 197 + {1004, 481, 3, 3}, + // Mips::TGE - 198 + {1015, 484, 3, 3}, + // Mips::TGEU - 199 + {1026, 487, 3, 3}, + // Mips::TGEU_MM - 200 + {1026, 490, 3, 3}, + // Mips::TGE_MM - 201 + {1015, 493, 3, 3}, + // Mips::TLT - 202 + {1038, 496, 3, 3}, + // Mips::TLTU - 203 + {1049, 499, 3, 3}, + // Mips::TLTU_MM - 204 + {1049, 502, 3, 3}, + // Mips::TLT_MM - 205 + {1038, 505, 3, 3}, + // Mips::TNE - 206 + {1061, 508, 3, 3}, + // Mips::TNE_MM - 207 + {1061, 511, 3, 3}, + // Mips::WAIT_MM - 208 + {1072, 514, 1, 1}, + // Mips::WRDSP - 209 + {1077, 515, 2, 2}, + // Mips::WRDSP_MM - 210 + {1077, 517, 2, 2}, + // Mips::YIELD - 211 + {1086, 519, 2, 2}, + }; + + static const AliasPatternCond Conds[] = { + // (MFTACX GPR32Opnd:$rt, AC0) - 0 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + // (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0) - 2 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MFTHI GPR32Opnd:$rt, AC0) - 5 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + // (MFTLO GPR32Opnd:$rt, AC0) - 7 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_AC0}, + // (MTTACX AC0, GPR32Opnd:$rt) - 9 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0) - 11 + {AliasPatternCond_K_RegClass, Mips_COP0RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MTTHI AC0, GPR32Opnd:$rt) - 14 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (MTTLO AC0, GPR32Opnd:$rt) - 16 + {AliasPatternCond_K_Reg, Mips_AC0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm) - 18 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + // (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 20 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + // (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 22 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + // (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 24 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + // (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm) - 26 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm) - 27 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 28 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BC1F FCC0, brtarget:$offset) - 31 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1FL FCC0, brtarget:$offset) - 32 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1F_MM FCC0, brtarget:$offset) - 33 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1T FCC0, brtarget:$offset) - 34 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1TL FCC0, brtarget:$offset) - 35 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC1T_MM FCC0, brtarget:$offset) - 36 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC2F FCC0, brtarget:$offset) - 37 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC2FL FCC0, brtarget:$offset) - 38 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC2T FCC0, brtarget:$offset) - 39 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC2TL FCC0, brtarget:$offset) - 40 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC3F FCC0, brtarget:$offset) - 41 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC3FL FCC0, brtarget:$offset) - 42 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC3T FCC0, brtarget:$offset) - 43 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BC3TL FCC0, brtarget:$offset) - 44 + {AliasPatternCond_K_Reg, Mips_FCC0}, + // (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 45 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BGEZAL ZERO, brtarget:$offset) - 47 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BGEZAL_MM ZERO, brtarget_mm:$offset) - 48 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 49 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (BREAK 0, 0) - 51 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BREAK uimm10:$imm, 0) - 53 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BREAK_MM 0, 0) - 55 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BREAK_MM uimm10:$imm, 0) - 57 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 59 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 62 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 65 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 68 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 71 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 74 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 77 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 80 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 83 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 86 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 89 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 92 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 95 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 98 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 101 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 104 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 107 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 110 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 113 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 116 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 119 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 122 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 125 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 128 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 131 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 134 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 137 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 140 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 143 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 146 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 149 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 152 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 155 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 158 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 161 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 164 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 167 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 170 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 173 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 176 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 179 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 182 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 185 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 188 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 191 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 194 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 197 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 200 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 203 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 206 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 209 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 212 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 215 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 218 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 221 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 224 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 227 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 230 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 233 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 236 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 239 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 242 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 245 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 248 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 251 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 254 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 257 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 260 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 263 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 266 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 269 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 272 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 275 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 278 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 281 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 284 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 287 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 290 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 293 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 296 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 299 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 302 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 305 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 308 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 311 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 314 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 317 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 320 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 323 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 326 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 329 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 332 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_AFGR64RegClassID}, + // (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 335 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 338 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR64RegClassID}, + // (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 341 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 344 + {AliasPatternCond_K_Reg, Mips_FCC0}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_FGR32RegClassID}, + // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 347 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + // (DI ZERO) - 350 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 351 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 354 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (DI_MM ZERO) - 357 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (DI_MMR6 ZERO) - 358 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (DMT ZERO) - 359 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 360 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 363 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_TiedReg, 0}, + // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 366 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 369 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_TiedReg, 0}, + // (DVPE ZERO) - 372 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EI ZERO) - 373 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EI_MM ZERO) - 374 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EI_MMR6 ZERO) - 375 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EMT ZERO) - 376 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (EVPE ZERO) - 377 + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (HYPCALL 0) - 378 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (HYPCALL_MM 0) - 379 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JALR ZERO, GPR32Opnd:$rs) - 380 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (JALR64 ZERO_64, GPR64Opnd:$rs) - 382 + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + // (JALRC_HB_MMR6 RA, GPR32Opnd:$rs) - 384 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (JALRC_MMR6 RA, GPR32Opnd:$rs) - 386 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (JALR_HB RA, GPR32Opnd:$rs) - 388 + {AliasPatternCond_K_Reg, Mips_RA}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (JALR_HB64 RA_64, GPR64Opnd:$rs) - 390 + {AliasPatternCond_K_Reg, Mips_RA_64}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + // (JIALC GPR32Opnd:$rs, 0) - 392 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JIALC64 GPR64Opnd:$rs, 0) - 394 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JIC GPR32Opnd:$rs, 0) - 396 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JIC64 GPR64Opnd:$rs, 0) - 398 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MOVE16_MM ZERO, ZERO) - 400 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (Move32R16 ZERO, S0) - 402 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_S0}, + // (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 404 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + // (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 407 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO_64}, + // (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 410 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0) - 413 + {AliasPatternCond_K_RegClass, Mips_GPR64RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 416 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 419 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_HWRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SDBBP 0) - 422 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SDBBP_MMR6 0) - 423 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SDBBP_R6 0) - 424 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SIGRIE 0) - 425 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SIGRIE_MMR6 0) - 426 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SLL ZERO, ZERO, 0) - 427 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SLL_MM ZERO, ZERO, 0) - 430 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SLL_MMR6 ZERO, ZERO, 0) - 433 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 436 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 439 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 442 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 445 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 448 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 451 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 454 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 457 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 460 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 463 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 466 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 469 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_TiedReg, 0}, + // (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset) - 472 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + // (SYNC 0) - 473 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SYNC_MM 0) - 474 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SYNC_MMR6 0) - 475 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SYSCALL 0) - 476 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SYSCALL_MM 0) - 477 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 478 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 481 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 484 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 487 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 490 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 493 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 496 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 499 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 502 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 505 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 508 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 511 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (WAIT_MM 0) - 514 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (WRDSP GPR32Opnd:$rt, 31) - 515 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (WRDSP_MM GPR32Opnd:$rt, 31) - 517 + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (YIELD ZERO, GPR32Opnd:$rs) - 519 + {AliasPatternCond_K_Reg, Mips_ZERO}, + {AliasPatternCond_K_RegClass, Mips_GPR32RegClassID}, + }; + + static const char *AsmStrings[] = { + /* 0 */ "mftacx $\x01\0" + /* 10 */ "mftc0 $\x01, $\x02\0" + /* 23 */ "mfthi $\x01\0" + /* 32 */ "mftlo $\x01\0" + /* 41 */ "mttacx $\x02\0" + /* 51 */ "mttc0 $\x02, $\x01\0" + /* 64 */ "mtthi $\x02\0" + /* 73 */ "mttlo $\x02\0" + /* 82 */ "nor $\x01, $\x03\0" + /* 93 */ "slt $\x01, $\x03\0" + /* 104 */ "sltu $\x01, $\x03\0" + /* 116 */ "lapc $\x01, $\x02\0" + /* 128 */ "move $\x01, $\x02\0" + /* 140 */ "bc1f $\x02\0" + /* 148 */ "bc1fl $\x02\0" + /* 157 */ "bc1t $\x02\0" + /* 165 */ "bc1tl $\x02\0" + /* 174 */ "bc2f $\x02\0" + /* 182 */ "bc2fl $\x02\0" + /* 191 */ "bc2t $\x02\0" + /* 199 */ "bc2tl $\x02\0" + /* 208 */ "bc3f $\x02\0" + /* 216 */ "bc3fl $\x02\0" + /* 225 */ "bc3t $\x02\0" + /* 233 */ "bc3tl $\x02\0" + /* 242 */ "beqzl $\x01, $\x03\0" + /* 255 */ "bal $\x02\0" + /* 262 */ "bnezl $\x01, $\x03\0" + /* 275 */ "break\0" + /* 281 */ "break $\xFF\x01\x01\0" + /* 292 */ "c.eq.d $\x02, $\x03\0" + /* 306 */ "c.eq.s $\x02, $\x03\0" + /* 320 */ "c.f.d $\x02, $\x03\0" + /* 333 */ "c.f.s $\x02, $\x03\0" + /* 346 */ "c.le.d $\x02, $\x03\0" + /* 360 */ "c.le.s $\x02, $\x03\0" + /* 374 */ "c.lt.d $\x02, $\x03\0" + /* 388 */ "c.lt.s $\x02, $\x03\0" + /* 402 */ "c.nge.d $\x02, $\x03\0" + /* 417 */ "c.nge.s $\x02, $\x03\0" + /* 432 */ "c.ngle.d $\x02, $\x03\0" + /* 448 */ "c.ngle.s $\x02, $\x03\0" + /* 464 */ "c.ngl.d $\x02, $\x03\0" + /* 479 */ "c.ngl.s $\x02, $\x03\0" + /* 494 */ "c.ngt.d $\x02, $\x03\0" + /* 509 */ "c.ngt.s $\x02, $\x03\0" + /* 524 */ "c.ole.d $\x02, $\x03\0" + /* 539 */ "c.ole.s $\x02, $\x03\0" + /* 554 */ "c.olt.d $\x02, $\x03\0" + /* 569 */ "c.olt.s $\x02, $\x03\0" + /* 584 */ "c.seq.d $\x02, $\x03\0" + /* 599 */ "c.seq.s $\x02, $\x03\0" + /* 614 */ "c.sf.d $\x02, $\x03\0" + /* 628 */ "c.sf.s $\x02, $\x03\0" + /* 642 */ "c.ueq.d $\x02, $\x03\0" + /* 657 */ "c.ueq.s $\x02, $\x03\0" + /* 672 */ "c.ule.d $\x02, $\x03\0" + /* 687 */ "c.ule.s $\x02, $\x03\0" + /* 702 */ "c.ult.d $\x02, $\x03\0" + /* 717 */ "c.ult.s $\x02, $\x03\0" + /* 732 */ "c.un.d $\x02, $\x03\0" + /* 746 */ "c.un.s $\x02, $\x03\0" + /* 760 */ "di\0" + /* 763 */ "div $\x01, $\x03\0" + /* 774 */ "divu $\x01, $\x03\0" + /* 786 */ "dmt\0" + /* 790 */ "dneg $\x01, $\x03\0" + /* 802 */ "dneg $\x01\0" + /* 810 */ "dnegu $\x01, $\x03\0" + /* 823 */ "dnegu $\x01\0" + /* 832 */ "dvpe\0" + /* 837 */ "ei\0" + /* 840 */ "emt\0" + /* 844 */ "evpe\0" + /* 849 */ "hypcall\0" + /* 857 */ "jr $\x02\0" + /* 863 */ "jalrc.hb $\x02\0" + /* 875 */ "jalrc $\x02\0" + /* 884 */ "jalr.hb $\x02\0" + /* 895 */ "jalrc $\x01\0" + /* 904 */ "jrc $\x01\0" + /* 911 */ "nop\0" + /* 915 */ "rdhwr $\x01, $\x02\0" + /* 928 */ "sdbbp\0" + /* 934 */ "sigrie\0" + /* 941 */ "neg $\x01, $\x03\0" + /* 952 */ "neg $\x01\0" + /* 959 */ "negu $\x01, $\x03\0" + /* 971 */ "negu $\x01\0" + /* 979 */ "sw $\x01, $\xFF\x02\x02\0" + /* 991 */ "sync\0" + /* 996 */ "syscall\0" + /* 1004 */ "teq $\x01, $\x02\0" + /* 1015 */ "tge $\x01, $\x02\0" + /* 1026 */ "tgeu $\x01, $\x02\0" + /* 1038 */ "tlt $\x01, $\x02\0" + /* 1049 */ "tltu $\x01, $\x02\0" + /* 1061 */ "tne $\x01, $\x02\0" + /* 1072 */ "wait\0" + /* 1077 */ "wrdsp $\x01\0" + /* 1086 */ "yield $\x02\0"}; + + const char *AsmString = MCInstPrinter_matchAliasPatterns( + MI, OpToPatterns, Patterns, Conds, AsmStrings, 202); + if (!AsmString) + return false; + + char *tmpString = cs_strdup(AsmString); + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, "\t"); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, *(tmpString + (I++))); + } + } while (AsmString[I] != '\0'); + } + + return tmpString; +} + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { + switch (PrintMethodIdx) { + default: + llvm_unreachable("Unknown PrintMethod kind"); + break; + // printUImm<10> + case 0: + printUImm(MI, OpIdx, OS, 10); + break; + // printMemOperand + case 1: + printMemOperand(MI, OpIdx, OS, ""); + break; + } +} + +#endif // PRINT_ALIAS_INSTR +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo3[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo4[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo5[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo6[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo7[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo8[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo9[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo10[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo11[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo12[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo13[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo14[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo15[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo16[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo17[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo18[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo19[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo20[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo21[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo22[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo23[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo24[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo25[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo26[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo27[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo28[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo29[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo30[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo31[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo32[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo33[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo34[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo35[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo36[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo37[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo38[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo39[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo40[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo41[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo42[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo43[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo44[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo45[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo46[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo47[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo48[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo49[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo50[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo51[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo52[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo53[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo54[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo55[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo56[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo57[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo58[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo59[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo60[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo61[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo62[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo63[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo64[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo65[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo66[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo67[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo68[] = { + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo69[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo70[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo71[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo72[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo73[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo74[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo75[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo76[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo77[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo78[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo79[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo80[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo81[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo82[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo83[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo84[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo85[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo86[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo87[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo88[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo89[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo90[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo91[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo92[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo93[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo94[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo95[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo96[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo97[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo98[] = { + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo99[] = { + {Mips_ACC128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo100[] = { + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo101[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo102[] = { + {Mips_DSPCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo103[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo104[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo105[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo106[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo107[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo108[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo109[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo110[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo111[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo112[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo113[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo114[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo115[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo116[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo117[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo118[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo119[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo120[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo121[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo122[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo123[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo124[] = { + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo125[] = { + {Mips_MSA128F16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo126[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo127[] = { + {Mips_COP0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo128[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo129[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo130[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo131[] = { + {Mips_DSPCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo132[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo133[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo134[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo135[] = { + {Mips_ACC128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo136[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo137[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo138[] = { + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo139[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo140[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC128RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo141[] = { + {Mips_ACC64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo142[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo143[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo144[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo145[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo146[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo147[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo148[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo149[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo150[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo151[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo152[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo153[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo154[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo155[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo156[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo157[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo158[] = { + {Mips_GPR32NONZERORegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo159[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo160[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo161[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo162[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo163[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo164[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo165[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo166[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo167[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo168[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo169[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo170[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo171[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo172[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo173[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo174[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo175[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo176[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo177[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo178[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo179[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo180[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo181[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo182[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo183[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo184[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsPlusSPRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo185[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo186[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo187[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo188[] = { + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo189[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo190[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo191[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo192[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo193[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo194[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo195[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo196[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo197[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo198[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo199[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo200[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo201[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo202[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo203[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo204[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo205[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo206[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo207[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo208[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo209[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSACtrlRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo210[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo211[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo212[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo213[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo214[] = { + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo215[] = { + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo216[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo217[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo218[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo219[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo220[] = { + {Mips_CCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo221[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo222[] = { + {Mips_MSACtrlRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo223[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo224[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo225[] = { + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo226[] = { + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo227[] = { + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo228[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo229[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo230[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo231[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo232[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo233[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo234[] = { + {Mips_COP0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo235[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo236[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo237[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo238[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo239[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo240[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo241[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo242[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo243[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo244[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo245[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo246[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo247[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo248[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo249[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo250[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo251[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo252[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo253[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo254[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo255[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo256[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo257[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo258[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo259[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo260[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo261[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo262[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo263[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo264[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo265[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo266[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo267[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo268[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo269[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo270[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo271[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo272[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {1, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo273[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo274[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo275[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo276[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo277[] = { + {Mips_COP3RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo278[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo279[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo280[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo281[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo282[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo283[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo284[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo285[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo286[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo287[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo288[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo289[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo290[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo291[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo292[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo293[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {3, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo294[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo295[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {2, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo296[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo297[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {2, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo298[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo299[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo300[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo301[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo302[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo303[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo304[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo305[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo306[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo307[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo308[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo309[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo310[] = { + {Mips_GPRMM16MovePPairFirstRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16MovePPairSecondRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16MovePRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16MovePRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo311[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo312[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo313[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo314[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo315[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo316[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FCCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo317[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo318[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo319[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo320[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo321[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo322[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo323[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo324[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo325[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo326[] = { + {Mips_COP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo327[] = { + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_AFGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo328[] = { + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo329[] = { + {Mips_HI32DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo330[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo331[] = { + {Mips_LO32DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo332[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo333[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo334[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo335[] = { + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPRMM16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo336[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo337[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo338[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo339[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo340[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_HWRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo341[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_HWRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo342[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo343[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo344[] = { + {Mips_GPRMM16ZeroRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {1, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo345[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo346[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo347[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo348[] = { + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo349[] = { + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGRCCRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_FGR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo350[] = { + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {Mips_ACC64DSPRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo351[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo352[] = { + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_DSPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo353[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo354[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo355[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo356[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo357[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo358[] = { + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo359[] = { + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128BRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo360[] = { + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128DRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo361[] = { + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128HRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo362[] = { + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_MSA128WRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_GPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo363[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo364[] = { + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {Mips_CPU16RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; + +extern const MCInstrDesc MipsInsts[] = { + {1, OperandInfo2}, // Inst #0 = PHI + {0, NULL}, // Inst #1 = INLINEASM + {0, NULL}, // Inst #2 = INLINEASM_BR + {1, OperandInfo3}, // Inst #3 = CFI_INSTRUCTION + {1, OperandInfo3}, // Inst #4 = EH_LABEL + {1, OperandInfo3}, // Inst #5 = GC_LABEL + {1, OperandInfo3}, // Inst #6 = ANNOTATION_LABEL + {0, NULL}, // Inst #7 = KILL + {3, OperandInfo4}, // Inst #8 = EXTRACT_SUBREG + {4, OperandInfo5}, // Inst #9 = INSERT_SUBREG + {1, OperandInfo2}, // Inst #10 = IMPLICIT_DEF + {4, OperandInfo6}, // Inst #11 = SUBREG_TO_REG + {3, OperandInfo4}, // Inst #12 = COPY_TO_REGCLASS + {0, NULL}, // Inst #13 = DBG_VALUE + {0, NULL}, // Inst #14 = DBG_VALUE_LIST + {0, NULL}, // Inst #15 = DBG_INSTR_REF + {0, NULL}, // Inst #16 = DBG_PHI + {1, OperandInfo2}, // Inst #17 = DBG_LABEL + {2, OperandInfo7}, // Inst #18 = REG_SEQUENCE + {2, OperandInfo7}, // Inst #19 = COPY + {0, NULL}, // Inst #20 = BUNDLE + {1, OperandInfo3}, // Inst #21 = LIFETIME_START + {1, OperandInfo3}, // Inst #22 = LIFETIME_END + {4, OperandInfo8}, // Inst #23 = PSEUDO_PROBE + {2, OperandInfo9}, // Inst #24 = ARITH_FENCE + {2, OperandInfo10}, // Inst #25 = STACKMAP + {0, NULL}, // Inst #26 = FENTRY_CALL + {6, OperandInfo11}, // Inst #27 = PATCHPOINT + {1, OperandInfo12}, // Inst #28 = LOAD_STACK_GUARD + {1, OperandInfo3}, // Inst #29 = PREALLOCATED_SETUP + {3, OperandInfo13}, // Inst #30 = PREALLOCATED_ARG + {0, NULL}, // Inst #31 = STATEPOINT + {2, OperandInfo14}, // Inst #32 = LOCAL_ESCAPE + {1, OperandInfo2}, // Inst #33 = FAULTING_OP + {0, NULL}, // Inst #34 = PATCHABLE_OP + {0, NULL}, // Inst #35 = PATCHABLE_FUNCTION_ENTER + {0, NULL}, // Inst #36 = PATCHABLE_RET + {0, NULL}, // Inst #37 = PATCHABLE_FUNCTION_EXIT + {0, NULL}, // Inst #38 = PATCHABLE_TAIL_CALL + {2, OperandInfo15}, // Inst #39 = PATCHABLE_EVENT_CALL + {3, OperandInfo16}, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + {0, NULL}, // Inst #41 = ICALL_BRANCH_FUNNEL + {3, OperandInfo17}, // Inst #42 = G_ASSERT_SEXT + {3, OperandInfo17}, // Inst #43 = G_ASSERT_ZEXT + {3, OperandInfo18}, // Inst #44 = G_ADD + {3, OperandInfo18}, // Inst #45 = G_SUB + {3, OperandInfo18}, // Inst #46 = G_MUL + {3, OperandInfo18}, // Inst #47 = G_SDIV + {3, OperandInfo18}, // Inst #48 = G_UDIV + {3, OperandInfo18}, // Inst #49 = G_SREM + {3, OperandInfo18}, // Inst #50 = G_UREM + {4, OperandInfo19}, // Inst #51 = G_SDIVREM + {4, OperandInfo19}, // Inst #52 = G_UDIVREM + {3, OperandInfo18}, // Inst #53 = G_AND + {3, OperandInfo18}, // Inst #54 = G_OR + {3, OperandInfo18}, // Inst #55 = G_XOR + {1, OperandInfo20}, // Inst #56 = G_IMPLICIT_DEF + {1, OperandInfo20}, // Inst #57 = G_PHI + {2, OperandInfo21}, // Inst #58 = G_FRAME_INDEX + {2, OperandInfo21}, // Inst #59 = G_GLOBAL_VALUE + {3, OperandInfo22}, // Inst #60 = G_EXTRACT + {2, OperandInfo23}, // Inst #61 = G_UNMERGE_VALUES + {4, OperandInfo24}, // Inst #62 = G_INSERT + {2, OperandInfo23}, // Inst #63 = G_MERGE_VALUES + {2, OperandInfo23}, // Inst #64 = G_BUILD_VECTOR + {2, OperandInfo23}, // Inst #65 = G_BUILD_VECTOR_TRUNC + {2, OperandInfo23}, // Inst #66 = G_CONCAT_VECTORS + {2, OperandInfo23}, // Inst #67 = G_PTRTOINT + {2, OperandInfo23}, // Inst #68 = G_INTTOPTR + {2, OperandInfo23}, // Inst #69 = G_BITCAST + {2, OperandInfo25}, // Inst #70 = G_FREEZE + {2, OperandInfo25}, // Inst #71 = G_INTRINSIC_TRUNC + {2, OperandInfo25}, // Inst #72 = G_INTRINSIC_ROUND + {2, OperandInfo23}, // Inst #73 = G_INTRINSIC_LRINT + {2, OperandInfo25}, // Inst #74 = G_INTRINSIC_ROUNDEVEN + {1, OperandInfo20}, // Inst #75 = G_READCYCLECOUNTER + {2, OperandInfo23}, // Inst #76 = G_LOAD + {2, OperandInfo23}, // Inst #77 = G_SEXTLOAD + {2, OperandInfo23}, // Inst #78 = G_ZEXTLOAD + {5, OperandInfo26}, // Inst #79 = G_INDEXED_LOAD + {5, OperandInfo26}, // Inst #80 = G_INDEXED_SEXTLOAD + {5, OperandInfo26}, // Inst #81 = G_INDEXED_ZEXTLOAD + {2, OperandInfo23}, // Inst #82 = G_STORE + {5, OperandInfo27}, // Inst #83 = G_INDEXED_STORE + {5, OperandInfo28}, // Inst #84 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + {4, OperandInfo29}, // Inst #85 = G_ATOMIC_CMPXCHG + {3, OperandInfo30}, // Inst #86 = G_ATOMICRMW_XCHG + {3, OperandInfo30}, // Inst #87 = G_ATOMICRMW_ADD + {3, OperandInfo30}, // Inst #88 = G_ATOMICRMW_SUB + {3, OperandInfo30}, // Inst #89 = G_ATOMICRMW_AND + {3, OperandInfo30}, // Inst #90 = G_ATOMICRMW_NAND + {3, OperandInfo30}, // Inst #91 = G_ATOMICRMW_OR + {3, OperandInfo30}, // Inst #92 = G_ATOMICRMW_XOR + {3, OperandInfo30}, // Inst #93 = G_ATOMICRMW_MAX + {3, OperandInfo30}, // Inst #94 = G_ATOMICRMW_MIN + {3, OperandInfo30}, // Inst #95 = G_ATOMICRMW_UMAX + {3, OperandInfo30}, // Inst #96 = G_ATOMICRMW_UMIN + {3, OperandInfo30}, // Inst #97 = G_ATOMICRMW_FADD + {3, OperandInfo30}, // Inst #98 = G_ATOMICRMW_FSUB + {2, OperandInfo10}, // Inst #99 = G_FENCE + {2, OperandInfo21}, // Inst #100 = G_BRCOND + {1, OperandInfo20}, // Inst #101 = G_BRINDIRECT + {1, OperandInfo2}, // Inst #102 = G_INTRINSIC + {1, OperandInfo2}, // Inst #103 = G_INTRINSIC_W_SIDE_EFFECTS + {2, OperandInfo23}, // Inst #104 = G_ANYEXT + {2, OperandInfo23}, // Inst #105 = G_TRUNC + {2, OperandInfo21}, // Inst #106 = G_CONSTANT + {2, OperandInfo21}, // Inst #107 = G_FCONSTANT + {1, OperandInfo20}, // Inst #108 = G_VASTART + {3, OperandInfo31}, // Inst #109 = G_VAARG + {2, OperandInfo23}, // Inst #110 = G_SEXT + {3, OperandInfo17}, // Inst #111 = G_SEXT_INREG + {2, OperandInfo23}, // Inst #112 = G_ZEXT + {3, OperandInfo32}, // Inst #113 = G_SHL + {3, OperandInfo32}, // Inst #114 = G_LSHR + {3, OperandInfo32}, // Inst #115 = G_ASHR + {4, OperandInfo33}, // Inst #116 = G_FSHL + {4, OperandInfo33}, // Inst #117 = G_FSHR + {3, OperandInfo32}, // Inst #118 = G_ROTR + {3, OperandInfo32}, // Inst #119 = G_ROTL + {4, OperandInfo34}, // Inst #120 = G_ICMP + {4, OperandInfo34}, // Inst #121 = G_FCMP + {4, OperandInfo29}, // Inst #122 = G_SELECT + {4, OperandInfo29}, // Inst #123 = G_UADDO + {5, OperandInfo35}, // Inst #124 = G_UADDE + {4, OperandInfo29}, // Inst #125 = G_USUBO + {5, OperandInfo35}, // Inst #126 = G_USUBE + {4, OperandInfo29}, // Inst #127 = G_SADDO + {5, OperandInfo35}, // Inst #128 = G_SADDE + {4, OperandInfo29}, // Inst #129 = G_SSUBO + {5, OperandInfo35}, // Inst #130 = G_SSUBE + {4, OperandInfo29}, // Inst #131 = G_UMULO + {4, OperandInfo29}, // Inst #132 = G_SMULO + {3, OperandInfo18}, // Inst #133 = G_UMULH + {3, OperandInfo18}, // Inst #134 = G_SMULH + {3, OperandInfo18}, // Inst #135 = G_UADDSAT + {3, OperandInfo18}, // Inst #136 = G_SADDSAT + {3, OperandInfo18}, // Inst #137 = G_USUBSAT + {3, OperandInfo18}, // Inst #138 = G_SSUBSAT + {3, OperandInfo32}, // Inst #139 = G_USHLSAT + {3, OperandInfo32}, // Inst #140 = G_SSHLSAT + {4, OperandInfo36}, // Inst #141 = G_SMULFIX + {4, OperandInfo36}, // Inst #142 = G_UMULFIX + {4, OperandInfo36}, // Inst #143 = G_SMULFIXSAT + {4, OperandInfo36}, // Inst #144 = G_UMULFIXSAT + {4, OperandInfo36}, // Inst #145 = G_SDIVFIX + {4, OperandInfo36}, // Inst #146 = G_UDIVFIX + {4, OperandInfo36}, // Inst #147 = G_SDIVFIXSAT + {4, OperandInfo36}, // Inst #148 = G_UDIVFIXSAT + {3, OperandInfo18}, // Inst #149 = G_FADD + {3, OperandInfo18}, // Inst #150 = G_FSUB + {3, OperandInfo18}, // Inst #151 = G_FMUL + {4, OperandInfo19}, // Inst #152 = G_FMA + {4, OperandInfo19}, // Inst #153 = G_FMAD + {3, OperandInfo18}, // Inst #154 = G_FDIV + {3, OperandInfo18}, // Inst #155 = G_FREM + {3, OperandInfo18}, // Inst #156 = G_FPOW + {3, OperandInfo32}, // Inst #157 = G_FPOWI + {2, OperandInfo25}, // Inst #158 = G_FEXP + {2, OperandInfo25}, // Inst #159 = G_FEXP2 + {2, OperandInfo25}, // Inst #160 = G_FLOG + {2, OperandInfo25}, // Inst #161 = G_FLOG2 + {2, OperandInfo25}, // Inst #162 = G_FLOG10 + {2, OperandInfo25}, // Inst #163 = G_FNEG + {2, OperandInfo23}, // Inst #164 = G_FPEXT + {2, OperandInfo23}, // Inst #165 = G_FPTRUNC + {2, OperandInfo23}, // Inst #166 = G_FPTOSI + {2, OperandInfo23}, // Inst #167 = G_FPTOUI + {2, OperandInfo23}, // Inst #168 = G_SITOFP + {2, OperandInfo23}, // Inst #169 = G_UITOFP + {2, OperandInfo25}, // Inst #170 = G_FABS + {3, OperandInfo32}, // Inst #171 = G_FCOPYSIGN + {2, OperandInfo25}, // Inst #172 = G_FCANONICALIZE + {3, OperandInfo18}, // Inst #173 = G_FMINNUM + {3, OperandInfo18}, // Inst #174 = G_FMAXNUM + {3, OperandInfo18}, // Inst #175 = G_FMINNUM_IEEE + {3, OperandInfo18}, // Inst #176 = G_FMAXNUM_IEEE + {3, OperandInfo18}, // Inst #177 = G_FMINIMUM + {3, OperandInfo18}, // Inst #178 = G_FMAXIMUM + {3, OperandInfo32}, // Inst #179 = G_PTR_ADD + {3, OperandInfo32}, // Inst #180 = G_PTRMASK + {3, OperandInfo18}, // Inst #181 = G_SMIN + {3, OperandInfo18}, // Inst #182 = G_SMAX + {3, OperandInfo18}, // Inst #183 = G_UMIN + {3, OperandInfo18}, // Inst #184 = G_UMAX + {2, OperandInfo25}, // Inst #185 = G_ABS + {2, OperandInfo23}, // Inst #186 = G_LROUND + {2, OperandInfo23}, // Inst #187 = G_LLROUND + {1, OperandInfo2}, // Inst #188 = G_BR + {3, OperandInfo37}, // Inst #189 = G_BRJT + {4, OperandInfo38}, // Inst #190 = G_INSERT_VECTOR_ELT + {3, OperandInfo39}, // Inst #191 = G_EXTRACT_VECTOR_ELT + {4, OperandInfo40}, // Inst #192 = G_SHUFFLE_VECTOR + {2, OperandInfo23}, // Inst #193 = G_CTTZ + {2, OperandInfo23}, // Inst #194 = G_CTTZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #195 = G_CTLZ + {2, OperandInfo23}, // Inst #196 = G_CTLZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #197 = G_CTPOP + {2, OperandInfo25}, // Inst #198 = G_BSWAP + {2, OperandInfo25}, // Inst #199 = G_BITREVERSE + {2, OperandInfo25}, // Inst #200 = G_FCEIL + {2, OperandInfo25}, // Inst #201 = G_FCOS + {2, OperandInfo25}, // Inst #202 = G_FSIN + {2, OperandInfo25}, // Inst #203 = G_FSQRT + {2, OperandInfo25}, // Inst #204 = G_FFLOOR + {2, OperandInfo25}, // Inst #205 = G_FRINT + {2, OperandInfo25}, // Inst #206 = G_FNEARBYINT + {2, OperandInfo23}, // Inst #207 = G_ADDRSPACE_CAST + {2, OperandInfo21}, // Inst #208 = G_BLOCK_ADDR + {2, OperandInfo21}, // Inst #209 = G_JUMP_TABLE + {3, OperandInfo22}, // Inst #210 = G_DYN_STACKALLOC + {3, OperandInfo18}, // Inst #211 = G_STRICT_FADD + {3, OperandInfo18}, // Inst #212 = G_STRICT_FSUB + {3, OperandInfo18}, // Inst #213 = G_STRICT_FMUL + {3, OperandInfo18}, // Inst #214 = G_STRICT_FDIV + {3, OperandInfo18}, // Inst #215 = G_STRICT_FREM + {4, OperandInfo19}, // Inst #216 = G_STRICT_FMA + {2, OperandInfo25}, // Inst #217 = G_STRICT_FSQRT + {2, OperandInfo21}, // Inst #218 = G_READ_REGISTER + {2, OperandInfo41}, // Inst #219 = G_WRITE_REGISTER + {4, OperandInfo42}, // Inst #220 = G_MEMCPY + {3, OperandInfo39}, // Inst #221 = G_MEMCPY_INLINE + {4, OperandInfo42}, // Inst #222 = G_MEMMOVE + {4, OperandInfo42}, // Inst #223 = G_MEMSET + {3, OperandInfo22}, // Inst #224 = G_BZERO + {3, OperandInfo39}, // Inst #225 = G_VECREDUCE_SEQ_FADD + {3, OperandInfo39}, // Inst #226 = G_VECREDUCE_SEQ_FMUL + {2, OperandInfo23}, // Inst #227 = G_VECREDUCE_FADD + {2, OperandInfo23}, // Inst #228 = G_VECREDUCE_FMUL + {2, OperandInfo23}, // Inst #229 = G_VECREDUCE_FMAX + {2, OperandInfo23}, // Inst #230 = G_VECREDUCE_FMIN + {2, OperandInfo23}, // Inst #231 = G_VECREDUCE_ADD + {2, OperandInfo23}, // Inst #232 = G_VECREDUCE_MUL + {2, OperandInfo23}, // Inst #233 = G_VECREDUCE_AND + {2, OperandInfo23}, // Inst #234 = G_VECREDUCE_OR + {2, OperandInfo23}, // Inst #235 = G_VECREDUCE_XOR + {2, OperandInfo23}, // Inst #236 = G_VECREDUCE_SMAX + {2, OperandInfo23}, // Inst #237 = G_VECREDUCE_SMIN + {2, OperandInfo23}, // Inst #238 = G_VECREDUCE_UMAX + {2, OperandInfo23}, // Inst #239 = G_VECREDUCE_UMIN + {4, OperandInfo43}, // Inst #240 = G_SBFX + {4, OperandInfo43}, // Inst #241 = G_UBFX + {2, OperandInfo44}, // Inst #242 = ABSMacro + {2, OperandInfo10}, // Inst #243 = ADJCALLSTACKDOWN + {2, OperandInfo10}, // Inst #244 = ADJCALLSTACKUP + {3, OperandInfo45}, // Inst #245 = AND_V_D_PSEUDO + {3, OperandInfo46}, // Inst #246 = AND_V_H_PSEUDO + {3, OperandInfo47}, // Inst #247 = AND_V_W_PSEUDO + {4, OperandInfo48}, // Inst #248 = ATOMIC_CMP_SWAP_I16 + {7, OperandInfo49}, // Inst #249 = ATOMIC_CMP_SWAP_I16_POSTRA + {4, OperandInfo48}, // Inst #250 = ATOMIC_CMP_SWAP_I32 + {4, OperandInfo48}, // Inst #251 = ATOMIC_CMP_SWAP_I32_POSTRA + {4, OperandInfo50}, // Inst #252 = ATOMIC_CMP_SWAP_I64 + {4, OperandInfo50}, // Inst #253 = ATOMIC_CMP_SWAP_I64_POSTRA + {4, OperandInfo48}, // Inst #254 = ATOMIC_CMP_SWAP_I8 + {7, OperandInfo49}, // Inst #255 = ATOMIC_CMP_SWAP_I8_POSTRA + {3, OperandInfo51}, // Inst #256 = ATOMIC_LOAD_ADD_I16 + {6, OperandInfo52}, // Inst #257 = ATOMIC_LOAD_ADD_I16_POSTRA + {3, OperandInfo51}, // Inst #258 = ATOMIC_LOAD_ADD_I32 + {3, OperandInfo51}, // Inst #259 = ATOMIC_LOAD_ADD_I32_POSTRA + {3, OperandInfo53}, // Inst #260 = ATOMIC_LOAD_ADD_I64 + {3, OperandInfo53}, // Inst #261 = ATOMIC_LOAD_ADD_I64_POSTRA + {3, OperandInfo51}, // Inst #262 = ATOMIC_LOAD_ADD_I8 + {6, OperandInfo52}, // Inst #263 = ATOMIC_LOAD_ADD_I8_POSTRA + {3, OperandInfo51}, // Inst #264 = ATOMIC_LOAD_AND_I16 + {6, OperandInfo52}, // Inst #265 = ATOMIC_LOAD_AND_I16_POSTRA + {3, OperandInfo51}, // Inst #266 = ATOMIC_LOAD_AND_I32 + {3, OperandInfo51}, // Inst #267 = ATOMIC_LOAD_AND_I32_POSTRA + {3, OperandInfo53}, // Inst #268 = ATOMIC_LOAD_AND_I64 + {3, OperandInfo53}, // Inst #269 = ATOMIC_LOAD_AND_I64_POSTRA + {3, OperandInfo51}, // Inst #270 = ATOMIC_LOAD_AND_I8 + {6, OperandInfo52}, // Inst #271 = ATOMIC_LOAD_AND_I8_POSTRA + {3, OperandInfo51}, // Inst #272 = ATOMIC_LOAD_MAX_I16 + {6, OperandInfo52}, // Inst #273 = ATOMIC_LOAD_MAX_I16_POSTRA + {3, OperandInfo51}, // Inst #274 = ATOMIC_LOAD_MAX_I32 + {3, OperandInfo51}, // Inst #275 = ATOMIC_LOAD_MAX_I32_POSTRA + {3, OperandInfo53}, // Inst #276 = ATOMIC_LOAD_MAX_I64 + {3, OperandInfo53}, // Inst #277 = ATOMIC_LOAD_MAX_I64_POSTRA + {3, OperandInfo51}, // Inst #278 = ATOMIC_LOAD_MAX_I8 + {6, OperandInfo52}, // Inst #279 = ATOMIC_LOAD_MAX_I8_POSTRA + {3, OperandInfo51}, // Inst #280 = ATOMIC_LOAD_MIN_I16 + {6, OperandInfo52}, // Inst #281 = ATOMIC_LOAD_MIN_I16_POSTRA + {3, OperandInfo51}, // Inst #282 = ATOMIC_LOAD_MIN_I32 + {3, OperandInfo51}, // Inst #283 = ATOMIC_LOAD_MIN_I32_POSTRA + {3, OperandInfo53}, // Inst #284 = ATOMIC_LOAD_MIN_I64 + {3, OperandInfo53}, // Inst #285 = ATOMIC_LOAD_MIN_I64_POSTRA + {3, OperandInfo51}, // Inst #286 = ATOMIC_LOAD_MIN_I8 + {6, OperandInfo52}, // Inst #287 = ATOMIC_LOAD_MIN_I8_POSTRA + {3, OperandInfo51}, // Inst #288 = ATOMIC_LOAD_NAND_I16 + {6, OperandInfo52}, // Inst #289 = ATOMIC_LOAD_NAND_I16_POSTRA + {3, OperandInfo51}, // Inst #290 = ATOMIC_LOAD_NAND_I32 + {3, OperandInfo51}, // Inst #291 = ATOMIC_LOAD_NAND_I32_POSTRA + {3, OperandInfo53}, // Inst #292 = ATOMIC_LOAD_NAND_I64 + {3, OperandInfo53}, // Inst #293 = ATOMIC_LOAD_NAND_I64_POSTRA + {3, OperandInfo51}, // Inst #294 = ATOMIC_LOAD_NAND_I8 + {6, OperandInfo52}, // Inst #295 = ATOMIC_LOAD_NAND_I8_POSTRA + {3, OperandInfo51}, // Inst #296 = ATOMIC_LOAD_OR_I16 + {6, OperandInfo52}, // Inst #297 = ATOMIC_LOAD_OR_I16_POSTRA + {3, OperandInfo51}, // Inst #298 = ATOMIC_LOAD_OR_I32 + {3, OperandInfo51}, // Inst #299 = ATOMIC_LOAD_OR_I32_POSTRA + {3, OperandInfo53}, // Inst #300 = ATOMIC_LOAD_OR_I64 + {3, OperandInfo53}, // Inst #301 = ATOMIC_LOAD_OR_I64_POSTRA + {3, OperandInfo51}, // Inst #302 = ATOMIC_LOAD_OR_I8 + {6, OperandInfo52}, // Inst #303 = ATOMIC_LOAD_OR_I8_POSTRA + {3, OperandInfo51}, // Inst #304 = ATOMIC_LOAD_SUB_I16 + {6, OperandInfo52}, // Inst #305 = ATOMIC_LOAD_SUB_I16_POSTRA + {3, OperandInfo51}, // Inst #306 = ATOMIC_LOAD_SUB_I32 + {3, OperandInfo51}, // Inst #307 = ATOMIC_LOAD_SUB_I32_POSTRA + {3, OperandInfo53}, // Inst #308 = ATOMIC_LOAD_SUB_I64 + {3, OperandInfo53}, // Inst #309 = ATOMIC_LOAD_SUB_I64_POSTRA + {3, OperandInfo51}, // Inst #310 = ATOMIC_LOAD_SUB_I8 + {6, OperandInfo52}, // Inst #311 = ATOMIC_LOAD_SUB_I8_POSTRA + {3, OperandInfo51}, // Inst #312 = ATOMIC_LOAD_UMAX_I16 + {6, OperandInfo52}, // Inst #313 = ATOMIC_LOAD_UMAX_I16_POSTRA + {3, OperandInfo51}, // Inst #314 = ATOMIC_LOAD_UMAX_I32 + {3, OperandInfo51}, // Inst #315 = ATOMIC_LOAD_UMAX_I32_POSTRA + {3, OperandInfo53}, // Inst #316 = ATOMIC_LOAD_UMAX_I64 + {3, OperandInfo53}, // Inst #317 = ATOMIC_LOAD_UMAX_I64_POSTRA + {3, OperandInfo51}, // Inst #318 = ATOMIC_LOAD_UMAX_I8 + {6, OperandInfo52}, // Inst #319 = ATOMIC_LOAD_UMAX_I8_POSTRA + {3, OperandInfo51}, // Inst #320 = ATOMIC_LOAD_UMIN_I16 + {6, OperandInfo52}, // Inst #321 = ATOMIC_LOAD_UMIN_I16_POSTRA + {3, OperandInfo51}, // Inst #322 = ATOMIC_LOAD_UMIN_I32 + {3, OperandInfo51}, // Inst #323 = ATOMIC_LOAD_UMIN_I32_POSTRA + {3, OperandInfo53}, // Inst #324 = ATOMIC_LOAD_UMIN_I64 + {3, OperandInfo53}, // Inst #325 = ATOMIC_LOAD_UMIN_I64_POSTRA + {3, OperandInfo51}, // Inst #326 = ATOMIC_LOAD_UMIN_I8 + {6, OperandInfo52}, // Inst #327 = ATOMIC_LOAD_UMIN_I8_POSTRA + {3, OperandInfo51}, // Inst #328 = ATOMIC_LOAD_XOR_I16 + {6, OperandInfo52}, // Inst #329 = ATOMIC_LOAD_XOR_I16_POSTRA + {3, OperandInfo51}, // Inst #330 = ATOMIC_LOAD_XOR_I32 + {3, OperandInfo51}, // Inst #331 = ATOMIC_LOAD_XOR_I32_POSTRA + {3, OperandInfo53}, // Inst #332 = ATOMIC_LOAD_XOR_I64 + {3, OperandInfo53}, // Inst #333 = ATOMIC_LOAD_XOR_I64_POSTRA + {3, OperandInfo51}, // Inst #334 = ATOMIC_LOAD_XOR_I8 + {6, OperandInfo52}, // Inst #335 = ATOMIC_LOAD_XOR_I8_POSTRA + {3, OperandInfo51}, // Inst #336 = ATOMIC_SWAP_I16 + {6, OperandInfo52}, // Inst #337 = ATOMIC_SWAP_I16_POSTRA + {3, OperandInfo51}, // Inst #338 = ATOMIC_SWAP_I32 + {3, OperandInfo51}, // Inst #339 = ATOMIC_SWAP_I32_POSTRA + {3, OperandInfo53}, // Inst #340 = ATOMIC_SWAP_I64 + {3, OperandInfo53}, // Inst #341 = ATOMIC_SWAP_I64_POSTRA + {3, OperandInfo51}, // Inst #342 = ATOMIC_SWAP_I8 + {6, OperandInfo52}, // Inst #343 = ATOMIC_SWAP_I8_POSTRA + {1, OperandInfo54}, // Inst #344 = B + {1, OperandInfo54}, // Inst #345 = BAL_BR + {1, OperandInfo54}, // Inst #346 = BAL_BR_MM + {3, OperandInfo55}, // Inst #347 = BEQLImmMacro + {3, OperandInfo56}, // Inst #348 = BGE + {3, OperandInfo55}, // Inst #349 = BGEImmMacro + {3, OperandInfo56}, // Inst #350 = BGEL + {3, OperandInfo55}, // Inst #351 = BGELImmMacro + {3, OperandInfo56}, // Inst #352 = BGEU + {3, OperandInfo55}, // Inst #353 = BGEUImmMacro + {3, OperandInfo56}, // Inst #354 = BGEUL + {3, OperandInfo55}, // Inst #355 = BGEULImmMacro + {3, OperandInfo56}, // Inst #356 = BGT + {3, OperandInfo55}, // Inst #357 = BGTImmMacro + {3, OperandInfo56}, // Inst #358 = BGTL + {3, OperandInfo55}, // Inst #359 = BGTLImmMacro + {3, OperandInfo56}, // Inst #360 = BGTU + {3, OperandInfo55}, // Inst #361 = BGTUImmMacro + {3, OperandInfo56}, // Inst #362 = BGTUL + {3, OperandInfo55}, // Inst #363 = BGTULImmMacro + {3, OperandInfo56}, // Inst #364 = BLE + {3, OperandInfo55}, // Inst #365 = BLEImmMacro + {3, OperandInfo56}, // Inst #366 = BLEL + {3, OperandInfo55}, // Inst #367 = BLELImmMacro + {3, OperandInfo56}, // Inst #368 = BLEU + {3, OperandInfo55}, // Inst #369 = BLEUImmMacro + {3, OperandInfo56}, // Inst #370 = BLEUL + {3, OperandInfo55}, // Inst #371 = BLEULImmMacro + {3, OperandInfo56}, // Inst #372 = BLT + {3, OperandInfo55}, // Inst #373 = BLTImmMacro + {3, OperandInfo56}, // Inst #374 = BLTL + {3, OperandInfo55}, // Inst #375 = BLTLImmMacro + {3, OperandInfo56}, // Inst #376 = BLTU + {3, OperandInfo55}, // Inst #377 = BLTUImmMacro + {3, OperandInfo56}, // Inst #378 = BLTUL + {3, OperandInfo55}, // Inst #379 = BLTULImmMacro + {3, OperandInfo55}, // Inst #380 = BNELImmMacro + {1, OperandInfo57}, // Inst #381 = BPOSGE32_PSEUDO + {4, OperandInfo58}, // Inst #382 = BSEL_D_PSEUDO + {4, OperandInfo58}, // Inst #383 = BSEL_FD_PSEUDO + {4, OperandInfo59}, // Inst #384 = BSEL_FW_PSEUDO + {4, OperandInfo60}, // Inst #385 = BSEL_H_PSEUDO + {4, OperandInfo59}, // Inst #386 = BSEL_W_PSEUDO + {1, OperandInfo54}, // Inst #387 = B_MM + {1, OperandInfo54}, // Inst #388 = B_MMR6_Pseudo + {1, OperandInfo54}, // Inst #389 = B_MM_Pseudo + {3, OperandInfo55}, // Inst #390 = BeqImm + {3, OperandInfo55}, // Inst #391 = BneImm + {3, OperandInfo61}, // Inst #392 = BteqzT8CmpX16 + {3, OperandInfo62}, // Inst #393 = BteqzT8CmpiX16 + {3, OperandInfo61}, // Inst #394 = BteqzT8SltX16 + {3, OperandInfo62}, // Inst #395 = BteqzT8SltiX16 + {3, OperandInfo62}, // Inst #396 = BteqzT8SltiuX16 + {3, OperandInfo61}, // Inst #397 = BteqzT8SltuX16 + {3, OperandInfo61}, // Inst #398 = BtnezT8CmpX16 + {3, OperandInfo62}, // Inst #399 = BtnezT8CmpiX16 + {3, OperandInfo61}, // Inst #400 = BtnezT8SltX16 + {3, OperandInfo62}, // Inst #401 = BtnezT8SltiX16 + {3, OperandInfo62}, // Inst #402 = BtnezT8SltiuX16 + {3, OperandInfo61}, // Inst #403 = BtnezT8SltuX16 + {3, OperandInfo63}, // Inst #404 = BuildPairF64 + {3, OperandInfo64}, // Inst #405 = BuildPairF64_64 + {2, OperandInfo65}, // Inst #406 = CFTC1 + {3, OperandInfo4}, // Inst #407 = CONSTPOOL_ENTRY + {3, OperandInfo66}, // Inst #408 = COPY_FD_PSEUDO + {3, OperandInfo67}, // Inst #409 = COPY_FW_PSEUDO + {2, OperandInfo68}, // Inst #410 = CTTC1 + {1, OperandInfo2}, // Inst #411 = Constant32 + {3, OperandInfo69}, // Inst #412 = DMULImmMacro + {3, OperandInfo70}, // Inst #413 = DMULMacro + {3, OperandInfo70}, // Inst #414 = DMULOMacro + {3, OperandInfo70}, // Inst #415 = DMULOUMacro + {3, OperandInfo71}, // Inst #416 = DROL + {3, OperandInfo72}, // Inst #417 = DROLImm + {3, OperandInfo71}, // Inst #418 = DROR + {3, OperandInfo72}, // Inst #419 = DRORImm + {3, OperandInfo69}, // Inst #420 = DSDivIMacro + {3, OperandInfo70}, // Inst #421 = DSDivMacro + {3, OperandInfo69}, // Inst #422 = DSRemIMacro + {3, OperandInfo70}, // Inst #423 = DSRemMacro + {3, OperandInfo69}, // Inst #424 = DUDivIMacro + {3, OperandInfo70}, // Inst #425 = DUDivMacro + {3, OperandInfo69}, // Inst #426 = DURemIMacro + {3, OperandInfo70}, // Inst #427 = DURemMacro + {0, NULL}, // Inst #428 = ERet + {3, OperandInfo73}, // Inst #429 = ExtractElementF64 + {3, OperandInfo74}, // Inst #430 = ExtractElementF64_64 + {2, OperandInfo75}, // Inst #431 = FABS_D + {2, OperandInfo76}, // Inst #432 = FABS_W + {2, OperandInfo75}, // Inst #433 = FEXP2_D_1_PSEUDO + {2, OperandInfo76}, // Inst #434 = FEXP2_W_1_PSEUDO + {2, OperandInfo77}, // Inst #435 = FILL_FD_PSEUDO + {2, OperandInfo78}, // Inst #436 = FILL_FW_PSEUDO + {4, OperandInfo79}, // Inst #437 = GotPrologue16 + {4, OperandInfo80}, // Inst #438 = INSERT_B_VIDX64_PSEUDO + {4, OperandInfo81}, // Inst #439 = INSERT_B_VIDX_PSEUDO + {4, OperandInfo82}, // Inst #440 = INSERT_D_VIDX64_PSEUDO + {4, OperandInfo83}, // Inst #441 = INSERT_D_VIDX_PSEUDO + {4, OperandInfo84}, // Inst #442 = INSERT_FD_PSEUDO + {4, OperandInfo85}, // Inst #443 = INSERT_FD_VIDX64_PSEUDO + {4, OperandInfo86}, // Inst #444 = INSERT_FD_VIDX_PSEUDO + {4, OperandInfo87}, // Inst #445 = INSERT_FW_PSEUDO + {4, OperandInfo88}, // Inst #446 = INSERT_FW_VIDX64_PSEUDO + {4, OperandInfo89}, // Inst #447 = INSERT_FW_VIDX_PSEUDO + {4, OperandInfo90}, // Inst #448 = INSERT_H_VIDX64_PSEUDO + {4, OperandInfo91}, // Inst #449 = INSERT_H_VIDX_PSEUDO + {4, OperandInfo92}, // Inst #450 = INSERT_W_VIDX64_PSEUDO + {4, OperandInfo93}, // Inst #451 = INSERT_W_VIDX_PSEUDO + {1, OperandInfo94}, // Inst #452 = JALR64Pseudo + {1, OperandInfo94}, // Inst #453 = JALRHB64Pseudo + {1, OperandInfo57}, // Inst #454 = JALRHBPseudo + {1, OperandInfo57}, // Inst #455 = JALRPseudo + {1, OperandInfo2}, // Inst #456 = JAL_MMR6 + {1, OperandInfo57}, // Inst #457 = JalOneReg + {2, OperandInfo44}, // Inst #458 = JalTwoReg + {3, OperandInfo95}, // Inst #459 = LDMacro + {3, OperandInfo96}, // Inst #460 = LDR_D + {3, OperandInfo97}, // Inst #461 = LDR_W + {3, OperandInfo98}, // Inst #462 = LD_F16 + {3, OperandInfo99}, // Inst #463 = LOAD_ACC128 + {3, OperandInfo100}, // Inst #464 = LOAD_ACC64 + {3, OperandInfo101}, // Inst #465 = LOAD_ACC64DSP + {3, OperandInfo102}, // Inst #466 = LOAD_CCOND_DSP + {4, OperandInfo103}, // Inst #467 = LONG_BRANCH_ADDiu + {3, OperandInfo56}, // Inst #468 = LONG_BRANCH_ADDiu2Op + {4, OperandInfo104}, // Inst #469 = LONG_BRANCH_DADDiu + {3, OperandInfo105}, // Inst #470 = LONG_BRANCH_DADDiu2Op + {3, OperandInfo106}, // Inst #471 = LONG_BRANCH_LUi + {2, OperandInfo107}, // Inst #472 = LONG_BRANCH_LUi2Op + {2, OperandInfo108}, // Inst #473 = LONG_BRANCH_LUi2Op_64 + {3, OperandInfo109}, // Inst #474 = LWM_MM + {2, OperandInfo110}, // Inst #475 = LoadAddrImm32 + {2, OperandInfo111}, // Inst #476 = LoadAddrImm64 + {3, OperandInfo95}, // Inst #477 = LoadAddrReg32 + {3, OperandInfo112}, // Inst #478 = LoadAddrReg64 + {2, OperandInfo113}, // Inst #479 = LoadImm32 + {2, OperandInfo111}, // Inst #480 = LoadImm64 + {2, OperandInfo114}, // Inst #481 = LoadImmDoubleFGR + {2, OperandInfo115}, // Inst #482 = LoadImmDoubleFGR_32 + {2, OperandInfo113}, // Inst #483 = LoadImmDoubleGPR + {2, OperandInfo116}, // Inst #484 = LoadImmSingleFGR + {2, OperandInfo113}, // Inst #485 = LoadImmSingleGPR + {3, OperandInfo117}, // Inst #486 = LwConstant32 + {2, OperandInfo118}, // Inst #487 = MFTACX + {3, OperandInfo119}, // Inst #488 = MFTC0 + {2, OperandInfo120}, // Inst #489 = MFTC1 + {1, OperandInfo57}, // Inst #490 = MFTDSP + {3, OperandInfo72}, // Inst #491 = MFTGPR + {2, OperandInfo120}, // Inst #492 = MFTHC1 + {2, OperandInfo118}, // Inst #493 = MFTHI + {2, OperandInfo118}, // Inst #494 = MFTLO + {2, OperandInfo44}, // Inst #495 = MIPSeh_return32 + {2, OperandInfo121}, // Inst #496 = MIPSeh_return64 + {2, OperandInfo122}, // Inst #497 = MSA_FP_EXTEND_D_PSEUDO + {2, OperandInfo123}, // Inst #498 = MSA_FP_EXTEND_W_PSEUDO + {2, OperandInfo124}, // Inst #499 = MSA_FP_ROUND_D_PSEUDO + {2, OperandInfo125}, // Inst #500 = MSA_FP_ROUND_W_PSEUDO + {2, OperandInfo126}, // Inst #501 = MTTACX + {3, OperandInfo127}, // Inst #502 = MTTC0 + {2, OperandInfo128}, // Inst #503 = MTTC1 + {1, OperandInfo57}, // Inst #504 = MTTDSP + {2, OperandInfo44}, // Inst #505 = MTTGPR + {2, OperandInfo128}, // Inst #506 = MTTHC1 + {2, OperandInfo126}, // Inst #507 = MTTHI + {2, OperandInfo126}, // Inst #508 = MTTLO + {3, OperandInfo72}, // Inst #509 = MULImmMacro + {3, OperandInfo71}, // Inst #510 = MULOMacro + {3, OperandInfo71}, // Inst #511 = MULOUMacro + {2, OperandInfo129}, // Inst #512 = MultRxRy16 + {3, OperandInfo130}, // Inst #513 = MultRxRyRz16 + {2, OperandInfo129}, // Inst #514 = MultuRxRy16 + {3, OperandInfo130}, // Inst #515 = MultuRxRyRz16 + {0, NULL}, // Inst #516 = NOP + {3, OperandInfo72}, // Inst #517 = NORImm + {3, OperandInfo69}, // Inst #518 = NORImm64 + {3, OperandInfo45}, // Inst #519 = NOR_V_D_PSEUDO + {3, OperandInfo46}, // Inst #520 = NOR_V_H_PSEUDO + {3, OperandInfo47}, // Inst #521 = NOR_V_W_PSEUDO + {3, OperandInfo45}, // Inst #522 = OR_V_D_PSEUDO + {3, OperandInfo46}, // Inst #523 = OR_V_H_PSEUDO + {3, OperandInfo47}, // Inst #524 = OR_V_W_PSEUDO + {3, OperandInfo131}, // Inst #525 = PseudoCMPU_EQ_QB + {3, OperandInfo131}, // Inst #526 = PseudoCMPU_LE_QB + {3, OperandInfo131}, // Inst #527 = PseudoCMPU_LT_QB + {3, OperandInfo131}, // Inst #528 = PseudoCMP_EQ_PH + {3, OperandInfo131}, // Inst #529 = PseudoCMP_LE_PH + {3, OperandInfo131}, // Inst #530 = PseudoCMP_LT_PH + {2, OperandInfo132}, // Inst #531 = PseudoCVT_D32_W + {2, OperandInfo133}, // Inst #532 = PseudoCVT_D64_L + {2, OperandInfo134}, // Inst #533 = PseudoCVT_D64_W + {2, OperandInfo133}, // Inst #534 = PseudoCVT_S_L + {2, OperandInfo128}, // Inst #535 = PseudoCVT_S_W + {3, OperandInfo135}, // Inst #536 = PseudoDMULT + {3, OperandInfo135}, // Inst #537 = PseudoDMULTu + {3, OperandInfo135}, // Inst #538 = PseudoDSDIV + {3, OperandInfo135}, // Inst #539 = PseudoDUDIV + {7, OperandInfo136}, // Inst #540 = PseudoD_SELECT_I + {7, OperandInfo137}, // Inst #541 = PseudoD_SELECT_I64 + {1, OperandInfo57}, // Inst #542 = PseudoIndirectBranch + {1, OperandInfo94}, // Inst #543 = PseudoIndirectBranch64 + {1, OperandInfo94}, // Inst #544 = PseudoIndirectBranch64R6 + {1, OperandInfo57}, // Inst #545 = PseudoIndirectBranchR6 + {1, OperandInfo57}, // Inst #546 = PseudoIndirectBranch_MM + {1, OperandInfo57}, // Inst #547 = PseudoIndirectBranch_MMR6 + {1, OperandInfo57}, // Inst #548 = PseudoIndirectHazardBranch + {1, OperandInfo94}, // Inst #549 = PseudoIndirectHazardBranch64 + {1, OperandInfo94}, // Inst #550 = PseudoIndrectHazardBranch64R6 + {1, OperandInfo57}, // Inst #551 = PseudoIndrectHazardBranchR6 + {4, OperandInfo138}, // Inst #552 = PseudoMADD + {4, OperandInfo138}, // Inst #553 = PseudoMADDU + {4, OperandInfo138}, // Inst #554 = PseudoMADDU_MM + {4, OperandInfo138}, // Inst #555 = PseudoMADD_MM + {2, OperandInfo139}, // Inst #556 = PseudoMFHI + {2, OperandInfo140}, // Inst #557 = PseudoMFHI64 + {2, OperandInfo139}, // Inst #558 = PseudoMFHI_MM + {2, OperandInfo139}, // Inst #559 = PseudoMFLO + {2, OperandInfo140}, // Inst #560 = PseudoMFLO64 + {2, OperandInfo139}, // Inst #561 = PseudoMFLO_MM + {4, OperandInfo138}, // Inst #562 = PseudoMSUB + {4, OperandInfo138}, // Inst #563 = PseudoMSUBU + {4, OperandInfo138}, // Inst #564 = PseudoMSUBU_MM + {4, OperandInfo138}, // Inst #565 = PseudoMSUB_MM + {3, OperandInfo141}, // Inst #566 = PseudoMTLOHI + {3, OperandInfo135}, // Inst #567 = PseudoMTLOHI64 + {3, OperandInfo142}, // Inst #568 = PseudoMTLOHI_DSP + {3, OperandInfo141}, // Inst #569 = PseudoMTLOHI_MM + {3, OperandInfo141}, // Inst #570 = PseudoMULT + {3, OperandInfo141}, // Inst #571 = PseudoMULT_MM + {3, OperandInfo141}, // Inst #572 = PseudoMULTu + {3, OperandInfo141}, // Inst #573 = PseudoMULTu_MM + {4, OperandInfo143}, // Inst #574 = PseudoPICK_PH + {4, OperandInfo143}, // Inst #575 = PseudoPICK_QB + {1, OperandInfo57}, // Inst #576 = PseudoReturn + {1, OperandInfo94}, // Inst #577 = PseudoReturn64 + {3, OperandInfo141}, // Inst #578 = PseudoSDIV + {4, OperandInfo144}, // Inst #579 = PseudoSELECTFP_F_D32 + {4, OperandInfo145}, // Inst #580 = PseudoSELECTFP_F_D64 + {4, OperandInfo146}, // Inst #581 = PseudoSELECTFP_F_I + {4, OperandInfo147}, // Inst #582 = PseudoSELECTFP_F_I64 + {4, OperandInfo148}, // Inst #583 = PseudoSELECTFP_F_S + {4, OperandInfo144}, // Inst #584 = PseudoSELECTFP_T_D32 + {4, OperandInfo145}, // Inst #585 = PseudoSELECTFP_T_D64 + {4, OperandInfo146}, // Inst #586 = PseudoSELECTFP_T_I + {4, OperandInfo147}, // Inst #587 = PseudoSELECTFP_T_I64 + {4, OperandInfo148}, // Inst #588 = PseudoSELECTFP_T_S + {4, OperandInfo149}, // Inst #589 = PseudoSELECT_D32 + {4, OperandInfo150}, // Inst #590 = PseudoSELECT_D64 + {4, OperandInfo151}, // Inst #591 = PseudoSELECT_I + {4, OperandInfo152}, // Inst #592 = PseudoSELECT_I64 + {4, OperandInfo153}, // Inst #593 = PseudoSELECT_S + {3, OperandInfo154}, // Inst #594 = PseudoTRUNC_W_D + {3, OperandInfo155}, // Inst #595 = PseudoTRUNC_W_D32 + {3, OperandInfo156}, // Inst #596 = PseudoTRUNC_W_S + {3, OperandInfo141}, // Inst #597 = PseudoUDIV + {3, OperandInfo71}, // Inst #598 = ROL + {3, OperandInfo72}, // Inst #599 = ROLImm + {3, OperandInfo71}, // Inst #600 = ROR + {3, OperandInfo72}, // Inst #601 = RORImm + {0, NULL}, // Inst #602 = RetRA + {0, NULL}, // Inst #603 = RetRA16 + {3, OperandInfo157}, // Inst #604 = SDC1_M1 + {3, OperandInfo141}, // Inst #605 = SDIV_MM_Pseudo + {3, OperandInfo95}, // Inst #606 = SDMacro + {3, OperandInfo72}, // Inst #607 = SDivIMacro + {3, OperandInfo158}, // Inst #608 = SDivMacro + {3, OperandInfo72}, // Inst #609 = SEQIMacro + {3, OperandInfo71}, // Inst #610 = SEQMacro + {3, OperandInfo71}, // Inst #611 = SGE + {3, OperandInfo72}, // Inst #612 = SGEImm + {3, OperandInfo69}, // Inst #613 = SGEImm64 + {3, OperandInfo71}, // Inst #614 = SGEU + {3, OperandInfo72}, // Inst #615 = SGEUImm + {3, OperandInfo69}, // Inst #616 = SGEUImm64 + {3, OperandInfo72}, // Inst #617 = SGTImm + {3, OperandInfo69}, // Inst #618 = SGTImm64 + {3, OperandInfo72}, // Inst #619 = SGTUImm + {3, OperandInfo69}, // Inst #620 = SGTUImm64 + {3, OperandInfo71}, // Inst #621 = SLE + {3, OperandInfo72}, // Inst #622 = SLEImm + {3, OperandInfo69}, // Inst #623 = SLEImm64 + {3, OperandInfo71}, // Inst #624 = SLEU + {3, OperandInfo72}, // Inst #625 = SLEUImm + {3, OperandInfo69}, // Inst #626 = SLEUImm64 + {3, OperandInfo69}, // Inst #627 = SLTImm64 + {3, OperandInfo69}, // Inst #628 = SLTUImm64 + {3, OperandInfo72}, // Inst #629 = SNEIMacro + {3, OperandInfo71}, // Inst #630 = SNEMacro + {2, OperandInfo159}, // Inst #631 = SNZ_B_PSEUDO + {2, OperandInfo160}, // Inst #632 = SNZ_D_PSEUDO + {2, OperandInfo161}, // Inst #633 = SNZ_H_PSEUDO + {2, OperandInfo159}, // Inst #634 = SNZ_V_PSEUDO + {2, OperandInfo162}, // Inst #635 = SNZ_W_PSEUDO + {3, OperandInfo72}, // Inst #636 = SRemIMacro + {3, OperandInfo71}, // Inst #637 = SRemMacro + {3, OperandInfo99}, // Inst #638 = STORE_ACC128 + {3, OperandInfo100}, // Inst #639 = STORE_ACC64 + {3, OperandInfo101}, // Inst #640 = STORE_ACC64DSP + {3, OperandInfo102}, // Inst #641 = STORE_CCOND_DSP + {3, OperandInfo96}, // Inst #642 = STR_D + {3, OperandInfo97}, // Inst #643 = STR_W + {3, OperandInfo98}, // Inst #644 = ST_F16 + {3, OperandInfo109}, // Inst #645 = SWM_MM + {2, OperandInfo159}, // Inst #646 = SZ_B_PSEUDO + {2, OperandInfo160}, // Inst #647 = SZ_D_PSEUDO + {2, OperandInfo161}, // Inst #648 = SZ_H_PSEUDO + {2, OperandInfo159}, // Inst #649 = SZ_V_PSEUDO + {2, OperandInfo162}, // Inst #650 = SZ_W_PSEUDO + {3, OperandInfo112}, // Inst #651 = SaaAddr + {3, OperandInfo112}, // Inst #652 = SaadAddr + {4, OperandInfo163}, // Inst #653 = SelBeqZ + {4, OperandInfo163}, // Inst #654 = SelBneZ + {5, OperandInfo164}, // Inst #655 = SelTBteqZCmp + {5, OperandInfo165}, // Inst #656 = SelTBteqZCmpi + {5, OperandInfo164}, // Inst #657 = SelTBteqZSlt + {5, OperandInfo165}, // Inst #658 = SelTBteqZSlti + {5, OperandInfo165}, // Inst #659 = SelTBteqZSltiu + {5, OperandInfo164}, // Inst #660 = SelTBteqZSltu + {5, OperandInfo164}, // Inst #661 = SelTBtneZCmp + {5, OperandInfo165}, // Inst #662 = SelTBtneZCmpi + {5, OperandInfo164}, // Inst #663 = SelTBtneZSlt + {5, OperandInfo165}, // Inst #664 = SelTBtneZSlti + {5, OperandInfo165}, // Inst #665 = SelTBtneZSltiu + {5, OperandInfo164}, // Inst #666 = SelTBtneZSltu + {3, OperandInfo130}, // Inst #667 = SltCCRxRy16 + {3, OperandInfo166}, // Inst #668 = SltiCCRxImmX16 + {3, OperandInfo166}, // Inst #669 = SltiuCCRxImmX16 + {3, OperandInfo130}, // Inst #670 = SltuCCRxRy16 + {3, OperandInfo130}, // Inst #671 = SltuRxRyRz16 + {1, OperandInfo2}, // Inst #672 = TAILCALL + {1, OperandInfo94}, // Inst #673 = TAILCALL64R6REG + {1, OperandInfo94}, // Inst #674 = TAILCALLHB64R6REG + {1, OperandInfo57}, // Inst #675 = TAILCALLHBR6REG + {1, OperandInfo57}, // Inst #676 = TAILCALLR6REG + {1, OperandInfo57}, // Inst #677 = TAILCALLREG + {1, OperandInfo94}, // Inst #678 = TAILCALLREG64 + {1, OperandInfo57}, // Inst #679 = TAILCALLREGHB + {1, OperandInfo94}, // Inst #680 = TAILCALLREGHB64 + {1, OperandInfo57}, // Inst #681 = TAILCALLREG_MM + {1, OperandInfo57}, // Inst #682 = TAILCALLREG_MMR6 + {1, OperandInfo2}, // Inst #683 = TAILCALL_MM + {1, OperandInfo2}, // Inst #684 = TAILCALL_MMR6 + {0, NULL}, // Inst #685 = TRAP + {0, NULL}, // Inst #686 = TRAP_MM + {3, OperandInfo141}, // Inst #687 = UDIV_MM_Pseudo + {3, OperandInfo72}, // Inst #688 = UDivIMacro + {3, OperandInfo71}, // Inst #689 = UDivMacro + {3, OperandInfo72}, // Inst #690 = URemIMacro + {3, OperandInfo71}, // Inst #691 = URemMacro + {3, OperandInfo95}, // Inst #692 = Ulh + {3, OperandInfo95}, // Inst #693 = Ulhu + {3, OperandInfo95}, // Inst #694 = Ulw + {3, OperandInfo95}, // Inst #695 = Ush + {3, OperandInfo95}, // Inst #696 = Usw + {3, OperandInfo45}, // Inst #697 = XOR_V_D_PSEUDO + {3, OperandInfo46}, // Inst #698 = XOR_V_H_PSEUDO + {3, OperandInfo47}, // Inst #699 = XOR_V_W_PSEUDO + {2, OperandInfo167}, // Inst #700 = ABSQ_S_PH + {2, OperandInfo167}, // Inst #701 = ABSQ_S_PH_MM + {2, OperandInfo167}, // Inst #702 = ABSQ_S_QB + {2, OperandInfo167}, // Inst #703 = ABSQ_S_QB_MMR2 + {2, OperandInfo44}, // Inst #704 = ABSQ_S_W + {2, OperandInfo44}, // Inst #705 = ABSQ_S_W_MM + {3, OperandInfo71}, // Inst #706 = ADD + {2, OperandInfo113}, // Inst #707 = ADDIUPC + {2, OperandInfo168}, // Inst #708 = ADDIUPC_MM + {2, OperandInfo113}, // Inst #709 = ADDIUPC_MMR6 + {2, OperandInfo168}, // Inst #710 = ADDIUR1SP_MM + {3, OperandInfo169}, // Inst #711 = ADDIUR2_MM + {3, OperandInfo170}, // Inst #712 = ADDIUS5_MM + {1, OperandInfo2}, // Inst #713 = ADDIUSP_MM + {3, OperandInfo72}, // Inst #714 = ADDIU_MMR6 + {3, OperandInfo171}, // Inst #715 = ADDQH_PH + {3, OperandInfo171}, // Inst #716 = ADDQH_PH_MMR2 + {3, OperandInfo171}, // Inst #717 = ADDQH_R_PH + {3, OperandInfo171}, // Inst #718 = ADDQH_R_PH_MMR2 + {3, OperandInfo71}, // Inst #719 = ADDQH_R_W + {3, OperandInfo71}, // Inst #720 = ADDQH_R_W_MMR2 + {3, OperandInfo71}, // Inst #721 = ADDQH_W + {3, OperandInfo71}, // Inst #722 = ADDQH_W_MMR2 + {3, OperandInfo171}, // Inst #723 = ADDQ_PH + {3, OperandInfo171}, // Inst #724 = ADDQ_PH_MM + {3, OperandInfo171}, // Inst #725 = ADDQ_S_PH + {3, OperandInfo171}, // Inst #726 = ADDQ_S_PH_MM + {3, OperandInfo71}, // Inst #727 = ADDQ_S_W + {3, OperandInfo71}, // Inst #728 = ADDQ_S_W_MM + {3, OperandInfo172}, // Inst #729 = ADDR_PS64 + {3, OperandInfo71}, // Inst #730 = ADDSC + {3, OperandInfo71}, // Inst #731 = ADDSC_MM + {3, OperandInfo173}, // Inst #732 = ADDS_A_B + {3, OperandInfo45}, // Inst #733 = ADDS_A_D + {3, OperandInfo46}, // Inst #734 = ADDS_A_H + {3, OperandInfo47}, // Inst #735 = ADDS_A_W + {3, OperandInfo173}, // Inst #736 = ADDS_S_B + {3, OperandInfo45}, // Inst #737 = ADDS_S_D + {3, OperandInfo46}, // Inst #738 = ADDS_S_H + {3, OperandInfo47}, // Inst #739 = ADDS_S_W + {3, OperandInfo173}, // Inst #740 = ADDS_U_B + {3, OperandInfo45}, // Inst #741 = ADDS_U_D + {3, OperandInfo46}, // Inst #742 = ADDS_U_H + {3, OperandInfo47}, // Inst #743 = ADDS_U_W + {3, OperandInfo174}, // Inst #744 = ADDU16_MM + {3, OperandInfo174}, // Inst #745 = ADDU16_MMR6 + {3, OperandInfo171}, // Inst #746 = ADDUH_QB + {3, OperandInfo171}, // Inst #747 = ADDUH_QB_MMR2 + {3, OperandInfo171}, // Inst #748 = ADDUH_R_QB + {3, OperandInfo171}, // Inst #749 = ADDUH_R_QB_MMR2 + {3, OperandInfo71}, // Inst #750 = ADDU_MMR6 + {3, OperandInfo171}, // Inst #751 = ADDU_PH + {3, OperandInfo171}, // Inst #752 = ADDU_PH_MMR2 + {3, OperandInfo171}, // Inst #753 = ADDU_QB + {3, OperandInfo171}, // Inst #754 = ADDU_QB_MM + {3, OperandInfo171}, // Inst #755 = ADDU_S_PH + {3, OperandInfo171}, // Inst #756 = ADDU_S_PH_MMR2 + {3, OperandInfo171}, // Inst #757 = ADDU_S_QB + {3, OperandInfo171}, // Inst #758 = ADDU_S_QB_MM + {3, OperandInfo175}, // Inst #759 = ADDVI_B + {3, OperandInfo176}, // Inst #760 = ADDVI_D + {3, OperandInfo177}, // Inst #761 = ADDVI_H + {3, OperandInfo178}, // Inst #762 = ADDVI_W + {3, OperandInfo173}, // Inst #763 = ADDV_B + {3, OperandInfo45}, // Inst #764 = ADDV_D + {3, OperandInfo46}, // Inst #765 = ADDV_H + {3, OperandInfo47}, // Inst #766 = ADDV_W + {3, OperandInfo71}, // Inst #767 = ADDWC + {3, OperandInfo71}, // Inst #768 = ADDWC_MM + {3, OperandInfo173}, // Inst #769 = ADD_A_B + {3, OperandInfo45}, // Inst #770 = ADD_A_D + {3, OperandInfo46}, // Inst #771 = ADD_A_H + {3, OperandInfo47}, // Inst #772 = ADD_A_W + {3, OperandInfo71}, // Inst #773 = ADD_MM + {3, OperandInfo71}, // Inst #774 = ADD_MMR6 + {3, OperandInfo72}, // Inst #775 = ADDi + {3, OperandInfo72}, // Inst #776 = ADDi_MM + {3, OperandInfo72}, // Inst #777 = ADDiu + {3, OperandInfo72}, // Inst #778 = ADDiu_MM + {3, OperandInfo71}, // Inst #779 = ADDu + {3, OperandInfo71}, // Inst #780 = ADDu_MM + {4, OperandInfo179}, // Inst #781 = ALIGN + {4, OperandInfo179}, // Inst #782 = ALIGN_MMR6 + {2, OperandInfo113}, // Inst #783 = ALUIPC + {2, OperandInfo113}, // Inst #784 = ALUIPC_MMR6 + {3, OperandInfo71}, // Inst #785 = AND + {3, OperandInfo180}, // Inst #786 = AND16_MM + {3, OperandInfo180}, // Inst #787 = AND16_MMR6 + {3, OperandInfo70}, // Inst #788 = AND64 + {3, OperandInfo169}, // Inst #789 = ANDI16_MM + {3, OperandInfo169}, // Inst #790 = ANDI16_MMR6 + {3, OperandInfo175}, // Inst #791 = ANDI_B + {3, OperandInfo72}, // Inst #792 = ANDI_MMR6 + {3, OperandInfo71}, // Inst #793 = AND_MM + {3, OperandInfo71}, // Inst #794 = AND_MMR6 + {3, OperandInfo173}, // Inst #795 = AND_V + {3, OperandInfo72}, // Inst #796 = ANDi + {3, OperandInfo69}, // Inst #797 = ANDi64 + {3, OperandInfo72}, // Inst #798 = ANDi_MM + {4, OperandInfo181}, // Inst #799 = APPEND + {4, OperandInfo181}, // Inst #800 = APPEND_MMR2 + {3, OperandInfo173}, // Inst #801 = ASUB_S_B + {3, OperandInfo45}, // Inst #802 = ASUB_S_D + {3, OperandInfo46}, // Inst #803 = ASUB_S_H + {3, OperandInfo47}, // Inst #804 = ASUB_S_W + {3, OperandInfo173}, // Inst #805 = ASUB_U_B + {3, OperandInfo45}, // Inst #806 = ASUB_U_D + {3, OperandInfo46}, // Inst #807 = ASUB_U_H + {3, OperandInfo47}, // Inst #808 = ASUB_U_W + {3, OperandInfo72}, // Inst #809 = AUI + {2, OperandInfo113}, // Inst #810 = AUIPC + {2, OperandInfo113}, // Inst #811 = AUIPC_MMR6 + {3, OperandInfo72}, // Inst #812 = AUI_MMR6 + {3, OperandInfo173}, // Inst #813 = AVER_S_B + {3, OperandInfo45}, // Inst #814 = AVER_S_D + {3, OperandInfo46}, // Inst #815 = AVER_S_H + {3, OperandInfo47}, // Inst #816 = AVER_S_W + {3, OperandInfo173}, // Inst #817 = AVER_U_B + {3, OperandInfo45}, // Inst #818 = AVER_U_D + {3, OperandInfo46}, // Inst #819 = AVER_U_H + {3, OperandInfo47}, // Inst #820 = AVER_U_W + {3, OperandInfo173}, // Inst #821 = AVE_S_B + {3, OperandInfo45}, // Inst #822 = AVE_S_D + {3, OperandInfo46}, // Inst #823 = AVE_S_H + {3, OperandInfo47}, // Inst #824 = AVE_S_W + {3, OperandInfo173}, // Inst #825 = AVE_U_B + {3, OperandInfo45}, // Inst #826 = AVE_U_D + {3, OperandInfo46}, // Inst #827 = AVE_U_H + {3, OperandInfo47}, // Inst #828 = AVE_U_W + {2, OperandInfo182}, // Inst #829 = AddiuRxImmX16 + {2, OperandInfo182}, // Inst #830 = AddiuRxPcImmX16 + {3, OperandInfo183}, // Inst #831 = AddiuRxRxImm16 + {3, OperandInfo183}, // Inst #832 = AddiuRxRxImmX16 + {3, OperandInfo184}, // Inst #833 = AddiuRxRyOffMemX16 + {1, OperandInfo2}, // Inst #834 = AddiuSpImm16 + {1, OperandInfo2}, // Inst #835 = AddiuSpImmX16 + {3, OperandInfo130}, // Inst #836 = AdduRxRyRz16 + {3, OperandInfo185}, // Inst #837 = AndRxRxRy16 + {1, OperandInfo54}, // Inst #838 = B16_MM + {3, OperandInfo70}, // Inst #839 = BADDu + {1, OperandInfo54}, // Inst #840 = BAL + {1, OperandInfo54}, // Inst #841 = BALC + {1, OperandInfo54}, // Inst #842 = BALC_MMR6 + {4, OperandInfo181}, // Inst #843 = BALIGN + {4, OperandInfo181}, // Inst #844 = BALIGN_MMR2 + {3, OperandInfo186}, // Inst #845 = BBIT0 + {3, OperandInfo186}, // Inst #846 = BBIT032 + {3, OperandInfo186}, // Inst #847 = BBIT1 + {3, OperandInfo186}, // Inst #848 = BBIT132 + {1, OperandInfo54}, // Inst #849 = BC + {1, OperandInfo54}, // Inst #850 = BC0F + {1, OperandInfo54}, // Inst #851 = BC0T + {1, OperandInfo54}, // Inst #852 = BC16_MMR6 + {2, OperandInfo187}, // Inst #853 = BC1EQZ + {2, OperandInfo187}, // Inst #854 = BC1EQZC_MMR6 + {2, OperandInfo188}, // Inst #855 = BC1F + {2, OperandInfo188}, // Inst #856 = BC1FL + {2, OperandInfo188}, // Inst #857 = BC1F_MM + {2, OperandInfo187}, // Inst #858 = BC1NEZ + {2, OperandInfo187}, // Inst #859 = BC1NEZC_MMR6 + {2, OperandInfo188}, // Inst #860 = BC1T + {2, OperandInfo188}, // Inst #861 = BC1TL + {2, OperandInfo188}, // Inst #862 = BC1T_MM + {2, OperandInfo189}, // Inst #863 = BC2EQZ + {2, OperandInfo189}, // Inst #864 = BC2EQZC_MMR6 + {2, OperandInfo188}, // Inst #865 = BC2F + {2, OperandInfo188}, // Inst #866 = BC2FL + {2, OperandInfo189}, // Inst #867 = BC2NEZ + {2, OperandInfo189}, // Inst #868 = BC2NEZC_MMR6 + {2, OperandInfo188}, // Inst #869 = BC2T + {2, OperandInfo188}, // Inst #870 = BC2TL + {2, OperandInfo188}, // Inst #871 = BC3F + {2, OperandInfo188}, // Inst #872 = BC3FL + {2, OperandInfo188}, // Inst #873 = BC3T + {2, OperandInfo188}, // Inst #874 = BC3TL + {3, OperandInfo175}, // Inst #875 = BCLRI_B + {3, OperandInfo176}, // Inst #876 = BCLRI_D + {3, OperandInfo177}, // Inst #877 = BCLRI_H + {3, OperandInfo178}, // Inst #878 = BCLRI_W + {3, OperandInfo173}, // Inst #879 = BCLR_B + {3, OperandInfo45}, // Inst #880 = BCLR_D + {3, OperandInfo46}, // Inst #881 = BCLR_H + {3, OperandInfo47}, // Inst #882 = BCLR_W + {1, OperandInfo54}, // Inst #883 = BC_MMR6 + {3, OperandInfo56}, // Inst #884 = BEQ + {3, OperandInfo105}, // Inst #885 = BEQ64 + {3, OperandInfo56}, // Inst #886 = BEQC + {3, OperandInfo105}, // Inst #887 = BEQC64 + {3, OperandInfo56}, // Inst #888 = BEQC_MMR6 + {3, OperandInfo56}, // Inst #889 = BEQL + {2, OperandInfo190}, // Inst #890 = BEQZ16_MM + {2, OperandInfo107}, // Inst #891 = BEQZALC + {2, OperandInfo107}, // Inst #892 = BEQZALC_MMR6 + {2, OperandInfo107}, // Inst #893 = BEQZC + {2, OperandInfo190}, // Inst #894 = BEQZC16_MMR6 + {2, OperandInfo108}, // Inst #895 = BEQZC64 + {2, OperandInfo107}, // Inst #896 = BEQZC_MM + {2, OperandInfo107}, // Inst #897 = BEQZC_MMR6 + {3, OperandInfo56}, // Inst #898 = BEQ_MM + {3, OperandInfo56}, // Inst #899 = BGEC + {3, OperandInfo105}, // Inst #900 = BGEC64 + {3, OperandInfo56}, // Inst #901 = BGEC_MMR6 + {3, OperandInfo56}, // Inst #902 = BGEUC + {3, OperandInfo105}, // Inst #903 = BGEUC64 + {3, OperandInfo56}, // Inst #904 = BGEUC_MMR6 + {2, OperandInfo107}, // Inst #905 = BGEZ + {2, OperandInfo108}, // Inst #906 = BGEZ64 + {2, OperandInfo107}, // Inst #907 = BGEZAL + {2, OperandInfo107}, // Inst #908 = BGEZALC + {2, OperandInfo107}, // Inst #909 = BGEZALC_MMR6 + {2, OperandInfo107}, // Inst #910 = BGEZALL + {2, OperandInfo107}, // Inst #911 = BGEZALS_MM + {2, OperandInfo107}, // Inst #912 = BGEZAL_MM + {2, OperandInfo107}, // Inst #913 = BGEZC + {2, OperandInfo108}, // Inst #914 = BGEZC64 + {2, OperandInfo107}, // Inst #915 = BGEZC_MMR6 + {2, OperandInfo107}, // Inst #916 = BGEZL + {2, OperandInfo107}, // Inst #917 = BGEZ_MM + {2, OperandInfo107}, // Inst #918 = BGTZ + {2, OperandInfo108}, // Inst #919 = BGTZ64 + {2, OperandInfo107}, // Inst #920 = BGTZALC + {2, OperandInfo107}, // Inst #921 = BGTZALC_MMR6 + {2, OperandInfo107}, // Inst #922 = BGTZC + {2, OperandInfo108}, // Inst #923 = BGTZC64 + {2, OperandInfo107}, // Inst #924 = BGTZC_MMR6 + {2, OperandInfo107}, // Inst #925 = BGTZL + {2, OperandInfo107}, // Inst #926 = BGTZ_MM + {4, OperandInfo191}, // Inst #927 = BINSLI_B + {4, OperandInfo192}, // Inst #928 = BINSLI_D + {4, OperandInfo193}, // Inst #929 = BINSLI_H + {4, OperandInfo194}, // Inst #930 = BINSLI_W + {4, OperandInfo195}, // Inst #931 = BINSL_B + {4, OperandInfo58}, // Inst #932 = BINSL_D + {4, OperandInfo60}, // Inst #933 = BINSL_H + {4, OperandInfo59}, // Inst #934 = BINSL_W + {4, OperandInfo191}, // Inst #935 = BINSRI_B + {4, OperandInfo192}, // Inst #936 = BINSRI_D + {4, OperandInfo193}, // Inst #937 = BINSRI_H + {4, OperandInfo194}, // Inst #938 = BINSRI_W + {4, OperandInfo195}, // Inst #939 = BINSR_B + {4, OperandInfo58}, // Inst #940 = BINSR_D + {4, OperandInfo60}, // Inst #941 = BINSR_H + {4, OperandInfo59}, // Inst #942 = BINSR_W + {2, OperandInfo44}, // Inst #943 = BITREV + {2, OperandInfo44}, // Inst #944 = BITREV_MM + {2, OperandInfo44}, // Inst #945 = BITSWAP + {2, OperandInfo44}, // Inst #946 = BITSWAP_MMR6 + {2, OperandInfo107}, // Inst #947 = BLEZ + {2, OperandInfo108}, // Inst #948 = BLEZ64 + {2, OperandInfo107}, // Inst #949 = BLEZALC + {2, OperandInfo107}, // Inst #950 = BLEZALC_MMR6 + {2, OperandInfo107}, // Inst #951 = BLEZC + {2, OperandInfo108}, // Inst #952 = BLEZC64 + {2, OperandInfo107}, // Inst #953 = BLEZC_MMR6 + {2, OperandInfo107}, // Inst #954 = BLEZL + {2, OperandInfo107}, // Inst #955 = BLEZ_MM + {3, OperandInfo56}, // Inst #956 = BLTC + {3, OperandInfo105}, // Inst #957 = BLTC64 + {3, OperandInfo56}, // Inst #958 = BLTC_MMR6 + {3, OperandInfo56}, // Inst #959 = BLTUC + {3, OperandInfo105}, // Inst #960 = BLTUC64 + {3, OperandInfo56}, // Inst #961 = BLTUC_MMR6 + {2, OperandInfo107}, // Inst #962 = BLTZ + {2, OperandInfo108}, // Inst #963 = BLTZ64 + {2, OperandInfo107}, // Inst #964 = BLTZAL + {2, OperandInfo107}, // Inst #965 = BLTZALC + {2, OperandInfo107}, // Inst #966 = BLTZALC_MMR6 + {2, OperandInfo107}, // Inst #967 = BLTZALL + {2, OperandInfo107}, // Inst #968 = BLTZALS_MM + {2, OperandInfo107}, // Inst #969 = BLTZAL_MM + {2, OperandInfo107}, // Inst #970 = BLTZC + {2, OperandInfo108}, // Inst #971 = BLTZC64 + {2, OperandInfo107}, // Inst #972 = BLTZC_MMR6 + {2, OperandInfo107}, // Inst #973 = BLTZL + {2, OperandInfo107}, // Inst #974 = BLTZ_MM + {4, OperandInfo191}, // Inst #975 = BMNZI_B + {4, OperandInfo195}, // Inst #976 = BMNZ_V + {4, OperandInfo191}, // Inst #977 = BMZI_B + {4, OperandInfo195}, // Inst #978 = BMZ_V + {3, OperandInfo56}, // Inst #979 = BNE + {3, OperandInfo105}, // Inst #980 = BNE64 + {3, OperandInfo56}, // Inst #981 = BNEC + {3, OperandInfo105}, // Inst #982 = BNEC64 + {3, OperandInfo56}, // Inst #983 = BNEC_MMR6 + {3, OperandInfo175}, // Inst #984 = BNEGI_B + {3, OperandInfo176}, // Inst #985 = BNEGI_D + {3, OperandInfo177}, // Inst #986 = BNEGI_H + {3, OperandInfo178}, // Inst #987 = BNEGI_W + {3, OperandInfo173}, // Inst #988 = BNEG_B + {3, OperandInfo45}, // Inst #989 = BNEG_D + {3, OperandInfo46}, // Inst #990 = BNEG_H + {3, OperandInfo47}, // Inst #991 = BNEG_W + {3, OperandInfo56}, // Inst #992 = BNEL + {2, OperandInfo190}, // Inst #993 = BNEZ16_MM + {2, OperandInfo107}, // Inst #994 = BNEZALC + {2, OperandInfo107}, // Inst #995 = BNEZALC_MMR6 + {2, OperandInfo107}, // Inst #996 = BNEZC + {2, OperandInfo190}, // Inst #997 = BNEZC16_MMR6 + {2, OperandInfo108}, // Inst #998 = BNEZC64 + {2, OperandInfo107}, // Inst #999 = BNEZC_MM + {2, OperandInfo107}, // Inst #1000 = BNEZC_MMR6 + {3, OperandInfo56}, // Inst #1001 = BNE_MM + {3, OperandInfo56}, // Inst #1002 = BNVC + {3, OperandInfo56}, // Inst #1003 = BNVC_MMR6 + {2, OperandInfo196}, // Inst #1004 = BNZ_B + {2, OperandInfo197}, // Inst #1005 = BNZ_D + {2, OperandInfo198}, // Inst #1006 = BNZ_H + {2, OperandInfo196}, // Inst #1007 = BNZ_V + {2, OperandInfo199}, // Inst #1008 = BNZ_W + {3, OperandInfo56}, // Inst #1009 = BOVC + {3, OperandInfo56}, // Inst #1010 = BOVC_MMR6 + {1, OperandInfo54}, // Inst #1011 = BPOSGE32 + {1, OperandInfo54}, // Inst #1012 = BPOSGE32C_MMR3 + {1, OperandInfo54}, // Inst #1013 = BPOSGE32_MM + {2, OperandInfo7}, // Inst #1014 = BREAK + {1, OperandInfo2}, // Inst #1015 = BREAK16_MM + {1, OperandInfo2}, // Inst #1016 = BREAK16_MMR6 + {2, OperandInfo7}, // Inst #1017 = BREAK_MM + {2, OperandInfo7}, // Inst #1018 = BREAK_MMR6 + {4, OperandInfo191}, // Inst #1019 = BSELI_B + {4, OperandInfo195}, // Inst #1020 = BSEL_V + {3, OperandInfo175}, // Inst #1021 = BSETI_B + {3, OperandInfo176}, // Inst #1022 = BSETI_D + {3, OperandInfo177}, // Inst #1023 = BSETI_H + {3, OperandInfo178}, // Inst #1024 = BSETI_W + {3, OperandInfo173}, // Inst #1025 = BSET_B + {3, OperandInfo45}, // Inst #1026 = BSET_D + {3, OperandInfo46}, // Inst #1027 = BSET_H + {3, OperandInfo47}, // Inst #1028 = BSET_W + {2, OperandInfo196}, // Inst #1029 = BZ_B + {2, OperandInfo197}, // Inst #1030 = BZ_D + {2, OperandInfo198}, // Inst #1031 = BZ_H + {2, OperandInfo196}, // Inst #1032 = BZ_V + {2, OperandInfo199}, // Inst #1033 = BZ_W + {2, OperandInfo200}, // Inst #1034 = BeqzRxImm16 + {2, OperandInfo200}, // Inst #1035 = BeqzRxImmX16 + {1, OperandInfo54}, // Inst #1036 = Bimm16 + {1, OperandInfo54}, // Inst #1037 = BimmX16 + {2, OperandInfo200}, // Inst #1038 = BnezRxImm16 + {2, OperandInfo200}, // Inst #1039 = BnezRxImmX16 + {0, NULL}, // Inst #1040 = Break16 + {1, OperandInfo2}, // Inst #1041 = Bteqz16 + {1, OperandInfo2}, // Inst #1042 = BteqzX16 + {1, OperandInfo2}, // Inst #1043 = Btnez16 + {1, OperandInfo2}, // Inst #1044 = BtnezX16 + {3, OperandInfo201}, // Inst #1045 = CACHE + {3, OperandInfo201}, // Inst #1046 = CACHEE + {3, OperandInfo201}, // Inst #1047 = CACHEE_MM + {3, OperandInfo201}, // Inst #1048 = CACHE_MM + {3, OperandInfo201}, // Inst #1049 = CACHE_MMR6 + {3, OperandInfo201}, // Inst #1050 = CACHE_R6 + {2, OperandInfo202}, // Inst #1051 = CEIL_L_D64 + {2, OperandInfo202}, // Inst #1052 = CEIL_L_D_MMR6 + {2, OperandInfo203}, // Inst #1053 = CEIL_L_S + {2, OperandInfo203}, // Inst #1054 = CEIL_L_S_MMR6 + {2, OperandInfo204}, // Inst #1055 = CEIL_W_D32 + {2, OperandInfo205}, // Inst #1056 = CEIL_W_D64 + {2, OperandInfo204}, // Inst #1057 = CEIL_W_D_MMR6 + {2, OperandInfo204}, // Inst #1058 = CEIL_W_MM + {2, OperandInfo206}, // Inst #1059 = CEIL_W_S + {2, OperandInfo206}, // Inst #1060 = CEIL_W_S_MM + {2, OperandInfo206}, // Inst #1061 = CEIL_W_S_MMR6 + {3, OperandInfo175}, // Inst #1062 = CEQI_B + {3, OperandInfo176}, // Inst #1063 = CEQI_D + {3, OperandInfo177}, // Inst #1064 = CEQI_H + {3, OperandInfo178}, // Inst #1065 = CEQI_W + {3, OperandInfo173}, // Inst #1066 = CEQ_B + {3, OperandInfo45}, // Inst #1067 = CEQ_D + {3, OperandInfo46}, // Inst #1068 = CEQ_H + {3, OperandInfo47}, // Inst #1069 = CEQ_W + {2, OperandInfo207}, // Inst #1070 = CFC1 + {2, OperandInfo207}, // Inst #1071 = CFC1_MM + {2, OperandInfo208}, // Inst #1072 = CFC2_MM + {2, OperandInfo209}, // Inst #1073 = CFCMSA + {4, OperandInfo210}, // Inst #1074 = CINS + {4, OperandInfo210}, // Inst #1075 = CINS32 + {4, OperandInfo211}, // Inst #1076 = CINS64_32 + {4, OperandInfo212}, // Inst #1077 = CINS_i32 + {2, OperandInfo202}, // Inst #1078 = CLASS_D + {2, OperandInfo202}, // Inst #1079 = CLASS_D_MMR6 + {2, OperandInfo206}, // Inst #1080 = CLASS_S + {2, OperandInfo206}, // Inst #1081 = CLASS_S_MMR6 + {3, OperandInfo175}, // Inst #1082 = CLEI_S_B + {3, OperandInfo176}, // Inst #1083 = CLEI_S_D + {3, OperandInfo177}, // Inst #1084 = CLEI_S_H + {3, OperandInfo178}, // Inst #1085 = CLEI_S_W + {3, OperandInfo175}, // Inst #1086 = CLEI_U_B + {3, OperandInfo176}, // Inst #1087 = CLEI_U_D + {3, OperandInfo177}, // Inst #1088 = CLEI_U_H + {3, OperandInfo178}, // Inst #1089 = CLEI_U_W + {3, OperandInfo173}, // Inst #1090 = CLE_S_B + {3, OperandInfo45}, // Inst #1091 = CLE_S_D + {3, OperandInfo46}, // Inst #1092 = CLE_S_H + {3, OperandInfo47}, // Inst #1093 = CLE_S_W + {3, OperandInfo173}, // Inst #1094 = CLE_U_B + {3, OperandInfo45}, // Inst #1095 = CLE_U_D + {3, OperandInfo46}, // Inst #1096 = CLE_U_H + {3, OperandInfo47}, // Inst #1097 = CLE_U_W + {2, OperandInfo44}, // Inst #1098 = CLO + {2, OperandInfo44}, // Inst #1099 = CLO_MM + {2, OperandInfo44}, // Inst #1100 = CLO_MMR6 + {2, OperandInfo44}, // Inst #1101 = CLO_R6 + {3, OperandInfo175}, // Inst #1102 = CLTI_S_B + {3, OperandInfo176}, // Inst #1103 = CLTI_S_D + {3, OperandInfo177}, // Inst #1104 = CLTI_S_H + {3, OperandInfo178}, // Inst #1105 = CLTI_S_W + {3, OperandInfo175}, // Inst #1106 = CLTI_U_B + {3, OperandInfo176}, // Inst #1107 = CLTI_U_D + {3, OperandInfo177}, // Inst #1108 = CLTI_U_H + {3, OperandInfo178}, // Inst #1109 = CLTI_U_W + {3, OperandInfo173}, // Inst #1110 = CLT_S_B + {3, OperandInfo45}, // Inst #1111 = CLT_S_D + {3, OperandInfo46}, // Inst #1112 = CLT_S_H + {3, OperandInfo47}, // Inst #1113 = CLT_S_W + {3, OperandInfo173}, // Inst #1114 = CLT_U_B + {3, OperandInfo45}, // Inst #1115 = CLT_U_D + {3, OperandInfo46}, // Inst #1116 = CLT_U_H + {3, OperandInfo47}, // Inst #1117 = CLT_U_W + {2, OperandInfo44}, // Inst #1118 = CLZ + {2, OperandInfo44}, // Inst #1119 = CLZ_MM + {2, OperandInfo44}, // Inst #1120 = CLZ_MMR6 + {2, OperandInfo44}, // Inst #1121 = CLZ_R6 + {3, OperandInfo213}, // Inst #1122 = CMPGDU_EQ_QB + {3, OperandInfo213}, // Inst #1123 = CMPGDU_EQ_QB_MMR2 + {3, OperandInfo213}, // Inst #1124 = CMPGDU_LE_QB + {3, OperandInfo213}, // Inst #1125 = CMPGDU_LE_QB_MMR2 + {3, OperandInfo213}, // Inst #1126 = CMPGDU_LT_QB + {3, OperandInfo213}, // Inst #1127 = CMPGDU_LT_QB_MMR2 + {3, OperandInfo213}, // Inst #1128 = CMPGU_EQ_QB + {3, OperandInfo213}, // Inst #1129 = CMPGU_EQ_QB_MM + {3, OperandInfo213}, // Inst #1130 = CMPGU_LE_QB + {3, OperandInfo213}, // Inst #1131 = CMPGU_LE_QB_MM + {3, OperandInfo213}, // Inst #1132 = CMPGU_LT_QB + {3, OperandInfo213}, // Inst #1133 = CMPGU_LT_QB_MM + {2, OperandInfo167}, // Inst #1134 = CMPU_EQ_QB + {2, OperandInfo167}, // Inst #1135 = CMPU_EQ_QB_MM + {2, OperandInfo167}, // Inst #1136 = CMPU_LE_QB + {2, OperandInfo167}, // Inst #1137 = CMPU_LE_QB_MM + {2, OperandInfo167}, // Inst #1138 = CMPU_LT_QB + {2, OperandInfo167}, // Inst #1139 = CMPU_LT_QB_MM + {3, OperandInfo214}, // Inst #1140 = CMP_AF_D_MMR6 + {3, OperandInfo215}, // Inst #1141 = CMP_AF_S_MMR6 + {3, OperandInfo214}, // Inst #1142 = CMP_EQ_D + {3, OperandInfo214}, // Inst #1143 = CMP_EQ_D_MMR6 + {2, OperandInfo167}, // Inst #1144 = CMP_EQ_PH + {2, OperandInfo167}, // Inst #1145 = CMP_EQ_PH_MM + {3, OperandInfo215}, // Inst #1146 = CMP_EQ_S + {3, OperandInfo215}, // Inst #1147 = CMP_EQ_S_MMR6 + {3, OperandInfo214}, // Inst #1148 = CMP_F_D + {3, OperandInfo215}, // Inst #1149 = CMP_F_S + {3, OperandInfo214}, // Inst #1150 = CMP_LE_D + {3, OperandInfo214}, // Inst #1151 = CMP_LE_D_MMR6 + {2, OperandInfo167}, // Inst #1152 = CMP_LE_PH + {2, OperandInfo167}, // Inst #1153 = CMP_LE_PH_MM + {3, OperandInfo215}, // Inst #1154 = CMP_LE_S + {3, OperandInfo215}, // Inst #1155 = CMP_LE_S_MMR6 + {3, OperandInfo214}, // Inst #1156 = CMP_LT_D + {3, OperandInfo214}, // Inst #1157 = CMP_LT_D_MMR6 + {2, OperandInfo167}, // Inst #1158 = CMP_LT_PH + {2, OperandInfo167}, // Inst #1159 = CMP_LT_PH_MM + {3, OperandInfo215}, // Inst #1160 = CMP_LT_S + {3, OperandInfo215}, // Inst #1161 = CMP_LT_S_MMR6 + {3, OperandInfo214}, // Inst #1162 = CMP_SAF_D + {3, OperandInfo214}, // Inst #1163 = CMP_SAF_D_MMR6 + {3, OperandInfo215}, // Inst #1164 = CMP_SAF_S + {3, OperandInfo215}, // Inst #1165 = CMP_SAF_S_MMR6 + {3, OperandInfo214}, // Inst #1166 = CMP_SEQ_D + {3, OperandInfo214}, // Inst #1167 = CMP_SEQ_D_MMR6 + {3, OperandInfo215}, // Inst #1168 = CMP_SEQ_S + {3, OperandInfo215}, // Inst #1169 = CMP_SEQ_S_MMR6 + {3, OperandInfo214}, // Inst #1170 = CMP_SLE_D + {3, OperandInfo214}, // Inst #1171 = CMP_SLE_D_MMR6 + {3, OperandInfo215}, // Inst #1172 = CMP_SLE_S + {3, OperandInfo215}, // Inst #1173 = CMP_SLE_S_MMR6 + {3, OperandInfo214}, // Inst #1174 = CMP_SLT_D + {3, OperandInfo214}, // Inst #1175 = CMP_SLT_D_MMR6 + {3, OperandInfo215}, // Inst #1176 = CMP_SLT_S + {3, OperandInfo215}, // Inst #1177 = CMP_SLT_S_MMR6 + {3, OperandInfo214}, // Inst #1178 = CMP_SUEQ_D + {3, OperandInfo214}, // Inst #1179 = CMP_SUEQ_D_MMR6 + {3, OperandInfo215}, // Inst #1180 = CMP_SUEQ_S + {3, OperandInfo215}, // Inst #1181 = CMP_SUEQ_S_MMR6 + {3, OperandInfo214}, // Inst #1182 = CMP_SULE_D + {3, OperandInfo214}, // Inst #1183 = CMP_SULE_D_MMR6 + {3, OperandInfo215}, // Inst #1184 = CMP_SULE_S + {3, OperandInfo215}, // Inst #1185 = CMP_SULE_S_MMR6 + {3, OperandInfo214}, // Inst #1186 = CMP_SULT_D + {3, OperandInfo214}, // Inst #1187 = CMP_SULT_D_MMR6 + {3, OperandInfo215}, // Inst #1188 = CMP_SULT_S + {3, OperandInfo215}, // Inst #1189 = CMP_SULT_S_MMR6 + {3, OperandInfo214}, // Inst #1190 = CMP_SUN_D + {3, OperandInfo214}, // Inst #1191 = CMP_SUN_D_MMR6 + {3, OperandInfo215}, // Inst #1192 = CMP_SUN_S + {3, OperandInfo215}, // Inst #1193 = CMP_SUN_S_MMR6 + {3, OperandInfo214}, // Inst #1194 = CMP_UEQ_D + {3, OperandInfo214}, // Inst #1195 = CMP_UEQ_D_MMR6 + {3, OperandInfo215}, // Inst #1196 = CMP_UEQ_S + {3, OperandInfo215}, // Inst #1197 = CMP_UEQ_S_MMR6 + {3, OperandInfo214}, // Inst #1198 = CMP_ULE_D + {3, OperandInfo214}, // Inst #1199 = CMP_ULE_D_MMR6 + {3, OperandInfo215}, // Inst #1200 = CMP_ULE_S + {3, OperandInfo215}, // Inst #1201 = CMP_ULE_S_MMR6 + {3, OperandInfo214}, // Inst #1202 = CMP_ULT_D + {3, OperandInfo214}, // Inst #1203 = CMP_ULT_D_MMR6 + {3, OperandInfo215}, // Inst #1204 = CMP_ULT_S + {3, OperandInfo215}, // Inst #1205 = CMP_ULT_S_MMR6 + {3, OperandInfo214}, // Inst #1206 = CMP_UN_D + {3, OperandInfo214}, // Inst #1207 = CMP_UN_D_MMR6 + {3, OperandInfo215}, // Inst #1208 = CMP_UN_S + {3, OperandInfo215}, // Inst #1209 = CMP_UN_S_MMR6 + {3, OperandInfo216}, // Inst #1210 = COPY_S_B + {3, OperandInfo217}, // Inst #1211 = COPY_S_D + {3, OperandInfo218}, // Inst #1212 = COPY_S_H + {3, OperandInfo219}, // Inst #1213 = COPY_S_W + {3, OperandInfo216}, // Inst #1214 = COPY_U_B + {3, OperandInfo218}, // Inst #1215 = COPY_U_H + {3, OperandInfo219}, // Inst #1216 = COPY_U_W + {3, OperandInfo71}, // Inst #1217 = CRC32B + {3, OperandInfo71}, // Inst #1218 = CRC32CB + {3, OperandInfo71}, // Inst #1219 = CRC32CD + {3, OperandInfo71}, // Inst #1220 = CRC32CH + {3, OperandInfo71}, // Inst #1221 = CRC32CW + {3, OperandInfo71}, // Inst #1222 = CRC32D + {3, OperandInfo71}, // Inst #1223 = CRC32H + {3, OperandInfo71}, // Inst #1224 = CRC32W + {2, OperandInfo220}, // Inst #1225 = CTC1 + {2, OperandInfo220}, // Inst #1226 = CTC1_MM + {2, OperandInfo221}, // Inst #1227 = CTC2_MM + {2, OperandInfo222}, // Inst #1228 = CTCMSA + {2, OperandInfo223}, // Inst #1229 = CVT_D32_S + {2, OperandInfo223}, // Inst #1230 = CVT_D32_S_MM + {2, OperandInfo223}, // Inst #1231 = CVT_D32_W + {2, OperandInfo223}, // Inst #1232 = CVT_D32_W_MM + {2, OperandInfo202}, // Inst #1233 = CVT_D64_L + {2, OperandInfo203}, // Inst #1234 = CVT_D64_S + {2, OperandInfo203}, // Inst #1235 = CVT_D64_S_MM + {2, OperandInfo203}, // Inst #1236 = CVT_D64_W + {2, OperandInfo203}, // Inst #1237 = CVT_D64_W_MM + {2, OperandInfo202}, // Inst #1238 = CVT_D_L_MMR6 + {2, OperandInfo202}, // Inst #1239 = CVT_L_D64 + {2, OperandInfo202}, // Inst #1240 = CVT_L_D64_MM + {2, OperandInfo202}, // Inst #1241 = CVT_L_D_MMR6 + {2, OperandInfo203}, // Inst #1242 = CVT_L_S + {2, OperandInfo203}, // Inst #1243 = CVT_L_S_MM + {2, OperandInfo203}, // Inst #1244 = CVT_L_S_MMR6 + {2, OperandInfo202}, // Inst #1245 = CVT_PS_PW64 + {3, OperandInfo224}, // Inst #1246 = CVT_PS_S64 + {2, OperandInfo202}, // Inst #1247 = CVT_PW_PS64 + {2, OperandInfo204}, // Inst #1248 = CVT_S_D32 + {2, OperandInfo204}, // Inst #1249 = CVT_S_D32_MM + {2, OperandInfo205}, // Inst #1250 = CVT_S_D64 + {2, OperandInfo205}, // Inst #1251 = CVT_S_D64_MM + {2, OperandInfo205}, // Inst #1252 = CVT_S_L + {2, OperandInfo203}, // Inst #1253 = CVT_S_L_MMR6 + {2, OperandInfo205}, // Inst #1254 = CVT_S_PL64 + {2, OperandInfo205}, // Inst #1255 = CVT_S_PU64 + {2, OperandInfo206}, // Inst #1256 = CVT_S_W + {2, OperandInfo206}, // Inst #1257 = CVT_S_W_MM + {2, OperandInfo206}, // Inst #1258 = CVT_S_W_MMR6 + {2, OperandInfo204}, // Inst #1259 = CVT_W_D32 + {2, OperandInfo204}, // Inst #1260 = CVT_W_D32_MM + {2, OperandInfo205}, // Inst #1261 = CVT_W_D64 + {2, OperandInfo205}, // Inst #1262 = CVT_W_D64_MM + {2, OperandInfo206}, // Inst #1263 = CVT_W_S + {2, OperandInfo206}, // Inst #1264 = CVT_W_S_MM + {2, OperandInfo206}, // Inst #1265 = CVT_W_S_MMR6 + {3, OperandInfo225}, // Inst #1266 = C_EQ_D32 + {3, OperandInfo225}, // Inst #1267 = C_EQ_D32_MM + {3, OperandInfo226}, // Inst #1268 = C_EQ_D64 + {3, OperandInfo226}, // Inst #1269 = C_EQ_D64_MM + {3, OperandInfo227}, // Inst #1270 = C_EQ_S + {3, OperandInfo227}, // Inst #1271 = C_EQ_S_MM + {3, OperandInfo225}, // Inst #1272 = C_F_D32 + {3, OperandInfo225}, // Inst #1273 = C_F_D32_MM + {3, OperandInfo226}, // Inst #1274 = C_F_D64 + {3, OperandInfo226}, // Inst #1275 = C_F_D64_MM + {3, OperandInfo227}, // Inst #1276 = C_F_S + {3, OperandInfo227}, // Inst #1277 = C_F_S_MM + {3, OperandInfo225}, // Inst #1278 = C_LE_D32 + {3, OperandInfo225}, // Inst #1279 = C_LE_D32_MM + {3, OperandInfo226}, // Inst #1280 = C_LE_D64 + {3, OperandInfo226}, // Inst #1281 = C_LE_D64_MM + {3, OperandInfo227}, // Inst #1282 = C_LE_S + {3, OperandInfo227}, // Inst #1283 = C_LE_S_MM + {3, OperandInfo225}, // Inst #1284 = C_LT_D32 + {3, OperandInfo225}, // Inst #1285 = C_LT_D32_MM + {3, OperandInfo226}, // Inst #1286 = C_LT_D64 + {3, OperandInfo226}, // Inst #1287 = C_LT_D64_MM + {3, OperandInfo227}, // Inst #1288 = C_LT_S + {3, OperandInfo227}, // Inst #1289 = C_LT_S_MM + {3, OperandInfo225}, // Inst #1290 = C_NGE_D32 + {3, OperandInfo225}, // Inst #1291 = C_NGE_D32_MM + {3, OperandInfo226}, // Inst #1292 = C_NGE_D64 + {3, OperandInfo226}, // Inst #1293 = C_NGE_D64_MM + {3, OperandInfo227}, // Inst #1294 = C_NGE_S + {3, OperandInfo227}, // Inst #1295 = C_NGE_S_MM + {3, OperandInfo225}, // Inst #1296 = C_NGLE_D32 + {3, OperandInfo225}, // Inst #1297 = C_NGLE_D32_MM + {3, OperandInfo226}, // Inst #1298 = C_NGLE_D64 + {3, OperandInfo226}, // Inst #1299 = C_NGLE_D64_MM + {3, OperandInfo227}, // Inst #1300 = C_NGLE_S + {3, OperandInfo227}, // Inst #1301 = C_NGLE_S_MM + {3, OperandInfo225}, // Inst #1302 = C_NGL_D32 + {3, OperandInfo225}, // Inst #1303 = C_NGL_D32_MM + {3, OperandInfo226}, // Inst #1304 = C_NGL_D64 + {3, OperandInfo226}, // Inst #1305 = C_NGL_D64_MM + {3, OperandInfo227}, // Inst #1306 = C_NGL_S + {3, OperandInfo227}, // Inst #1307 = C_NGL_S_MM + {3, OperandInfo225}, // Inst #1308 = C_NGT_D32 + {3, OperandInfo225}, // Inst #1309 = C_NGT_D32_MM + {3, OperandInfo226}, // Inst #1310 = C_NGT_D64 + {3, OperandInfo226}, // Inst #1311 = C_NGT_D64_MM + {3, OperandInfo227}, // Inst #1312 = C_NGT_S + {3, OperandInfo227}, // Inst #1313 = C_NGT_S_MM + {3, OperandInfo225}, // Inst #1314 = C_OLE_D32 + {3, OperandInfo225}, // Inst #1315 = C_OLE_D32_MM + {3, OperandInfo226}, // Inst #1316 = C_OLE_D64 + {3, OperandInfo226}, // Inst #1317 = C_OLE_D64_MM + {3, OperandInfo227}, // Inst #1318 = C_OLE_S + {3, OperandInfo227}, // Inst #1319 = C_OLE_S_MM + {3, OperandInfo225}, // Inst #1320 = C_OLT_D32 + {3, OperandInfo225}, // Inst #1321 = C_OLT_D32_MM + {3, OperandInfo226}, // Inst #1322 = C_OLT_D64 + {3, OperandInfo226}, // Inst #1323 = C_OLT_D64_MM + {3, OperandInfo227}, // Inst #1324 = C_OLT_S + {3, OperandInfo227}, // Inst #1325 = C_OLT_S_MM + {3, OperandInfo225}, // Inst #1326 = C_SEQ_D32 + {3, OperandInfo225}, // Inst #1327 = C_SEQ_D32_MM + {3, OperandInfo226}, // Inst #1328 = C_SEQ_D64 + {3, OperandInfo226}, // Inst #1329 = C_SEQ_D64_MM + {3, OperandInfo227}, // Inst #1330 = C_SEQ_S + {3, OperandInfo227}, // Inst #1331 = C_SEQ_S_MM + {3, OperandInfo225}, // Inst #1332 = C_SF_D32 + {3, OperandInfo225}, // Inst #1333 = C_SF_D32_MM + {3, OperandInfo226}, // Inst #1334 = C_SF_D64 + {3, OperandInfo226}, // Inst #1335 = C_SF_D64_MM + {3, OperandInfo227}, // Inst #1336 = C_SF_S + {3, OperandInfo227}, // Inst #1337 = C_SF_S_MM + {3, OperandInfo225}, // Inst #1338 = C_UEQ_D32 + {3, OperandInfo225}, // Inst #1339 = C_UEQ_D32_MM + {3, OperandInfo226}, // Inst #1340 = C_UEQ_D64 + {3, OperandInfo226}, // Inst #1341 = C_UEQ_D64_MM + {3, OperandInfo227}, // Inst #1342 = C_UEQ_S + {3, OperandInfo227}, // Inst #1343 = C_UEQ_S_MM + {3, OperandInfo225}, // Inst #1344 = C_ULE_D32 + {3, OperandInfo225}, // Inst #1345 = C_ULE_D32_MM + {3, OperandInfo226}, // Inst #1346 = C_ULE_D64 + {3, OperandInfo226}, // Inst #1347 = C_ULE_D64_MM + {3, OperandInfo227}, // Inst #1348 = C_ULE_S + {3, OperandInfo227}, // Inst #1349 = C_ULE_S_MM + {3, OperandInfo225}, // Inst #1350 = C_ULT_D32 + {3, OperandInfo225}, // Inst #1351 = C_ULT_D32_MM + {3, OperandInfo226}, // Inst #1352 = C_ULT_D64 + {3, OperandInfo226}, // Inst #1353 = C_ULT_D64_MM + {3, OperandInfo227}, // Inst #1354 = C_ULT_S + {3, OperandInfo227}, // Inst #1355 = C_ULT_S_MM + {3, OperandInfo225}, // Inst #1356 = C_UN_D32 + {3, OperandInfo225}, // Inst #1357 = C_UN_D32_MM + {3, OperandInfo226}, // Inst #1358 = C_UN_D64 + {3, OperandInfo226}, // Inst #1359 = C_UN_D64_MM + {3, OperandInfo227}, // Inst #1360 = C_UN_S + {3, OperandInfo227}, // Inst #1361 = C_UN_S_MM + {2, OperandInfo129}, // Inst #1362 = CmpRxRy16 + {2, OperandInfo182}, // Inst #1363 = CmpiRxImm16 + {2, OperandInfo182}, // Inst #1364 = CmpiRxImmX16 + {3, OperandInfo70}, // Inst #1365 = DADD + {3, OperandInfo69}, // Inst #1366 = DADDi + {3, OperandInfo69}, // Inst #1367 = DADDiu + {3, OperandInfo70}, // Inst #1368 = DADDu + {3, OperandInfo228}, // Inst #1369 = DAHI + {4, OperandInfo229}, // Inst #1370 = DALIGN + {3, OperandInfo228}, // Inst #1371 = DATI + {3, OperandInfo69}, // Inst #1372 = DAUI + {2, OperandInfo121}, // Inst #1373 = DBITSWAP + {2, OperandInfo121}, // Inst #1374 = DCLO + {2, OperandInfo121}, // Inst #1375 = DCLO_R6 + {2, OperandInfo121}, // Inst #1376 = DCLZ + {2, OperandInfo121}, // Inst #1377 = DCLZ_R6 + {3, OperandInfo70}, // Inst #1378 = DDIV + {3, OperandInfo70}, // Inst #1379 = DDIVU + {0, NULL}, // Inst #1380 = DERET + {0, NULL}, // Inst #1381 = DERET_MM + {0, NULL}, // Inst #1382 = DERET_MMR6 + {4, OperandInfo210}, // Inst #1383 = DEXT + {4, OperandInfo211}, // Inst #1384 = DEXT64_32 + {4, OperandInfo210}, // Inst #1385 = DEXTM + {4, OperandInfo210}, // Inst #1386 = DEXTU + {1, OperandInfo57}, // Inst #1387 = DI + {5, OperandInfo230}, // Inst #1388 = DINS + {5, OperandInfo230}, // Inst #1389 = DINSM + {5, OperandInfo230}, // Inst #1390 = DINSU + {3, OperandInfo71}, // Inst #1391 = DIV + {3, OperandInfo71}, // Inst #1392 = DIVU + {3, OperandInfo71}, // Inst #1393 = DIVU_MMR6 + {3, OperandInfo71}, // Inst #1394 = DIV_MMR6 + {3, OperandInfo173}, // Inst #1395 = DIV_S_B + {3, OperandInfo45}, // Inst #1396 = DIV_S_D + {3, OperandInfo46}, // Inst #1397 = DIV_S_H + {3, OperandInfo47}, // Inst #1398 = DIV_S_W + {3, OperandInfo173}, // Inst #1399 = DIV_U_B + {3, OperandInfo45}, // Inst #1400 = DIV_U_D + {3, OperandInfo46}, // Inst #1401 = DIV_U_H + {3, OperandInfo47}, // Inst #1402 = DIV_U_W + {1, OperandInfo57}, // Inst #1403 = DI_MM + {1, OperandInfo57}, // Inst #1404 = DI_MMR6 + {4, OperandInfo229}, // Inst #1405 = DLSA + {4, OperandInfo229}, // Inst #1406 = DLSA_R6 + {3, OperandInfo231}, // Inst #1407 = DMFC0 + {2, OperandInfo232}, // Inst #1408 = DMFC1 + {3, OperandInfo233}, // Inst #1409 = DMFC2 + {2, OperandInfo111}, // Inst #1410 = DMFC2_OCTEON + {3, OperandInfo231}, // Inst #1411 = DMFGC0 + {3, OperandInfo70}, // Inst #1412 = DMOD + {3, OperandInfo70}, // Inst #1413 = DMODU + {1, OperandInfo57}, // Inst #1414 = DMT + {3, OperandInfo234}, // Inst #1415 = DMTC0 + {2, OperandInfo133}, // Inst #1416 = DMTC1 + {3, OperandInfo235}, // Inst #1417 = DMTC2 + {2, OperandInfo111}, // Inst #1418 = DMTC2_OCTEON + {3, OperandInfo234}, // Inst #1419 = DMTGC0 + {3, OperandInfo70}, // Inst #1420 = DMUH + {3, OperandInfo70}, // Inst #1421 = DMUHU + {3, OperandInfo70}, // Inst #1422 = DMUL + {2, OperandInfo121}, // Inst #1423 = DMULT + {2, OperandInfo121}, // Inst #1424 = DMULTu + {3, OperandInfo70}, // Inst #1425 = DMULU + {3, OperandInfo70}, // Inst #1426 = DMUL_R6 + {3, OperandInfo236}, // Inst #1427 = DOTP_S_D + {3, OperandInfo237}, // Inst #1428 = DOTP_S_H + {3, OperandInfo238}, // Inst #1429 = DOTP_S_W + {3, OperandInfo236}, // Inst #1430 = DOTP_U_D + {3, OperandInfo237}, // Inst #1431 = DOTP_U_H + {3, OperandInfo238}, // Inst #1432 = DOTP_U_W + {4, OperandInfo239}, // Inst #1433 = DPADD_S_D + {4, OperandInfo240}, // Inst #1434 = DPADD_S_H + {4, OperandInfo241}, // Inst #1435 = DPADD_S_W + {4, OperandInfo239}, // Inst #1436 = DPADD_U_D + {4, OperandInfo240}, // Inst #1437 = DPADD_U_H + {4, OperandInfo241}, // Inst #1438 = DPADD_U_W + {4, OperandInfo242}, // Inst #1439 = DPAQX_SA_W_PH + {4, OperandInfo242}, // Inst #1440 = DPAQX_SA_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1441 = DPAQX_S_W_PH + {4, OperandInfo242}, // Inst #1442 = DPAQX_S_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1443 = DPAQ_SA_L_W + {4, OperandInfo242}, // Inst #1444 = DPAQ_SA_L_W_MM + {4, OperandInfo242}, // Inst #1445 = DPAQ_S_W_PH + {4, OperandInfo242}, // Inst #1446 = DPAQ_S_W_PH_MM + {4, OperandInfo242}, // Inst #1447 = DPAU_H_QBL + {4, OperandInfo242}, // Inst #1448 = DPAU_H_QBL_MM + {4, OperandInfo242}, // Inst #1449 = DPAU_H_QBR + {4, OperandInfo242}, // Inst #1450 = DPAU_H_QBR_MM + {4, OperandInfo242}, // Inst #1451 = DPAX_W_PH + {4, OperandInfo242}, // Inst #1452 = DPAX_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1453 = DPA_W_PH + {4, OperandInfo242}, // Inst #1454 = DPA_W_PH_MMR2 + {2, OperandInfo121}, // Inst #1455 = DPOP + {4, OperandInfo242}, // Inst #1456 = DPSQX_SA_W_PH + {4, OperandInfo242}, // Inst #1457 = DPSQX_SA_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1458 = DPSQX_S_W_PH + {4, OperandInfo242}, // Inst #1459 = DPSQX_S_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1460 = DPSQ_SA_L_W + {4, OperandInfo242}, // Inst #1461 = DPSQ_SA_L_W_MM + {4, OperandInfo242}, // Inst #1462 = DPSQ_S_W_PH + {4, OperandInfo242}, // Inst #1463 = DPSQ_S_W_PH_MM + {4, OperandInfo239}, // Inst #1464 = DPSUB_S_D + {4, OperandInfo240}, // Inst #1465 = DPSUB_S_H + {4, OperandInfo241}, // Inst #1466 = DPSUB_S_W + {4, OperandInfo239}, // Inst #1467 = DPSUB_U_D + {4, OperandInfo240}, // Inst #1468 = DPSUB_U_H + {4, OperandInfo241}, // Inst #1469 = DPSUB_U_W + {4, OperandInfo242}, // Inst #1470 = DPSU_H_QBL + {4, OperandInfo242}, // Inst #1471 = DPSU_H_QBL_MM + {4, OperandInfo242}, // Inst #1472 = DPSU_H_QBR + {4, OperandInfo242}, // Inst #1473 = DPSU_H_QBR_MM + {4, OperandInfo242}, // Inst #1474 = DPSX_W_PH + {4, OperandInfo242}, // Inst #1475 = DPSX_W_PH_MMR2 + {4, OperandInfo242}, // Inst #1476 = DPS_W_PH + {4, OperandInfo242}, // Inst #1477 = DPS_W_PH_MMR2 + {3, OperandInfo69}, // Inst #1478 = DROTR + {3, OperandInfo69}, // Inst #1479 = DROTR32 + {3, OperandInfo243}, // Inst #1480 = DROTRV + {2, OperandInfo121}, // Inst #1481 = DSBH + {2, OperandInfo121}, // Inst #1482 = DSDIV + {2, OperandInfo121}, // Inst #1483 = DSHD + {3, OperandInfo69}, // Inst #1484 = DSLL + {3, OperandInfo69}, // Inst #1485 = DSLL32 + {2, OperandInfo244}, // Inst #1486 = DSLL64_32 + {3, OperandInfo243}, // Inst #1487 = DSLLV + {3, OperandInfo69}, // Inst #1488 = DSRA + {3, OperandInfo69}, // Inst #1489 = DSRA32 + {3, OperandInfo243}, // Inst #1490 = DSRAV + {3, OperandInfo69}, // Inst #1491 = DSRL + {3, OperandInfo69}, // Inst #1492 = DSRL32 + {3, OperandInfo243}, // Inst #1493 = DSRLV + {3, OperandInfo70}, // Inst #1494 = DSUB + {3, OperandInfo70}, // Inst #1495 = DSUBu + {2, OperandInfo121}, // Inst #1496 = DUDIV + {1, OperandInfo57}, // Inst #1497 = DVP + {1, OperandInfo57}, // Inst #1498 = DVPE + {1, OperandInfo57}, // Inst #1499 = DVP_MMR6 + {2, OperandInfo129}, // Inst #1500 = DivRxRy16 + {2, OperandInfo129}, // Inst #1501 = DivuRxRy16 + {0, NULL}, // Inst #1502 = EHB + {0, NULL}, // Inst #1503 = EHB_MM + {0, NULL}, // Inst #1504 = EHB_MMR6 + {1, OperandInfo57}, // Inst #1505 = EI + {1, OperandInfo57}, // Inst #1506 = EI_MM + {1, OperandInfo57}, // Inst #1507 = EI_MMR6 + {1, OperandInfo57}, // Inst #1508 = EMT + {0, NULL}, // Inst #1509 = ERET + {0, NULL}, // Inst #1510 = ERETNC + {0, NULL}, // Inst #1511 = ERETNC_MMR6 + {0, NULL}, // Inst #1512 = ERET_MM + {0, NULL}, // Inst #1513 = ERET_MMR6 + {1, OperandInfo57}, // Inst #1514 = EVP + {1, OperandInfo57}, // Inst #1515 = EVPE + {1, OperandInfo57}, // Inst #1516 = EVP_MMR6 + {4, OperandInfo212}, // Inst #1517 = EXT + {3, OperandInfo245}, // Inst #1518 = EXTP + {3, OperandInfo245}, // Inst #1519 = EXTPDP + {3, OperandInfo246}, // Inst #1520 = EXTPDPV + {3, OperandInfo246}, // Inst #1521 = EXTPDPV_MM + {3, OperandInfo245}, // Inst #1522 = EXTPDP_MM + {3, OperandInfo246}, // Inst #1523 = EXTPV + {3, OperandInfo246}, // Inst #1524 = EXTPV_MM + {3, OperandInfo245}, // Inst #1525 = EXTP_MM + {3, OperandInfo246}, // Inst #1526 = EXTRV_RS_W + {3, OperandInfo246}, // Inst #1527 = EXTRV_RS_W_MM + {3, OperandInfo246}, // Inst #1528 = EXTRV_R_W + {3, OperandInfo246}, // Inst #1529 = EXTRV_R_W_MM + {3, OperandInfo246}, // Inst #1530 = EXTRV_S_H + {3, OperandInfo246}, // Inst #1531 = EXTRV_S_H_MM + {3, OperandInfo246}, // Inst #1532 = EXTRV_W + {3, OperandInfo246}, // Inst #1533 = EXTRV_W_MM + {3, OperandInfo245}, // Inst #1534 = EXTR_RS_W + {3, OperandInfo245}, // Inst #1535 = EXTR_RS_W_MM + {3, OperandInfo245}, // Inst #1536 = EXTR_R_W + {3, OperandInfo245}, // Inst #1537 = EXTR_R_W_MM + {3, OperandInfo245}, // Inst #1538 = EXTR_S_H + {3, OperandInfo245}, // Inst #1539 = EXTR_S_H_MM + {3, OperandInfo245}, // Inst #1540 = EXTR_W + {3, OperandInfo245}, // Inst #1541 = EXTR_W_MM + {4, OperandInfo210}, // Inst #1542 = EXTS + {4, OperandInfo210}, // Inst #1543 = EXTS32 + {4, OperandInfo212}, // Inst #1544 = EXT_MM + {4, OperandInfo212}, // Inst #1545 = EXT_MMR6 + {2, OperandInfo247}, // Inst #1546 = FABS_D32 + {2, OperandInfo247}, // Inst #1547 = FABS_D32_MM + {2, OperandInfo202}, // Inst #1548 = FABS_D64 + {2, OperandInfo202}, // Inst #1549 = FABS_D64_MM + {2, OperandInfo206}, // Inst #1550 = FABS_S + {2, OperandInfo206}, // Inst #1551 = FABS_S_MM + {3, OperandInfo45}, // Inst #1552 = FADD_D + {3, OperandInfo248}, // Inst #1553 = FADD_D32 + {3, OperandInfo248}, // Inst #1554 = FADD_D32_MM + {3, OperandInfo172}, // Inst #1555 = FADD_D64 + {3, OperandInfo172}, // Inst #1556 = FADD_D64_MM + {3, OperandInfo172}, // Inst #1557 = FADD_PS64 + {3, OperandInfo249}, // Inst #1558 = FADD_S + {3, OperandInfo249}, // Inst #1559 = FADD_S_MM + {3, OperandInfo249}, // Inst #1560 = FADD_S_MMR6 + {3, OperandInfo47}, // Inst #1561 = FADD_W + {3, OperandInfo45}, // Inst #1562 = FCAF_D + {3, OperandInfo47}, // Inst #1563 = FCAF_W + {3, OperandInfo45}, // Inst #1564 = FCEQ_D + {3, OperandInfo47}, // Inst #1565 = FCEQ_W + {2, OperandInfo75}, // Inst #1566 = FCLASS_D + {2, OperandInfo76}, // Inst #1567 = FCLASS_W + {3, OperandInfo45}, // Inst #1568 = FCLE_D + {3, OperandInfo47}, // Inst #1569 = FCLE_W + {3, OperandInfo45}, // Inst #1570 = FCLT_D + {3, OperandInfo47}, // Inst #1571 = FCLT_W + {3, OperandInfo250}, // Inst #1572 = FCMP_D32 + {3, OperandInfo250}, // Inst #1573 = FCMP_D32_MM + {3, OperandInfo251}, // Inst #1574 = FCMP_D64 + {3, OperandInfo252}, // Inst #1575 = FCMP_S32 + {3, OperandInfo252}, // Inst #1576 = FCMP_S32_MM + {3, OperandInfo45}, // Inst #1577 = FCNE_D + {3, OperandInfo47}, // Inst #1578 = FCNE_W + {3, OperandInfo45}, // Inst #1579 = FCOR_D + {3, OperandInfo47}, // Inst #1580 = FCOR_W + {3, OperandInfo45}, // Inst #1581 = FCUEQ_D + {3, OperandInfo47}, // Inst #1582 = FCUEQ_W + {3, OperandInfo45}, // Inst #1583 = FCULE_D + {3, OperandInfo47}, // Inst #1584 = FCULE_W + {3, OperandInfo45}, // Inst #1585 = FCULT_D + {3, OperandInfo47}, // Inst #1586 = FCULT_W + {3, OperandInfo45}, // Inst #1587 = FCUNE_D + {3, OperandInfo47}, // Inst #1588 = FCUNE_W + {3, OperandInfo45}, // Inst #1589 = FCUN_D + {3, OperandInfo47}, // Inst #1590 = FCUN_W + {3, OperandInfo45}, // Inst #1591 = FDIV_D + {3, OperandInfo248}, // Inst #1592 = FDIV_D32 + {3, OperandInfo248}, // Inst #1593 = FDIV_D32_MM + {3, OperandInfo172}, // Inst #1594 = FDIV_D64 + {3, OperandInfo172}, // Inst #1595 = FDIV_D64_MM + {3, OperandInfo249}, // Inst #1596 = FDIV_S + {3, OperandInfo249}, // Inst #1597 = FDIV_S_MM + {3, OperandInfo249}, // Inst #1598 = FDIV_S_MMR6 + {3, OperandInfo47}, // Inst #1599 = FDIV_W + {3, OperandInfo253}, // Inst #1600 = FEXDO_H + {3, OperandInfo254}, // Inst #1601 = FEXDO_W + {3, OperandInfo45}, // Inst #1602 = FEXP2_D + {3, OperandInfo47}, // Inst #1603 = FEXP2_W + {2, OperandInfo255}, // Inst #1604 = FEXUPL_D + {2, OperandInfo256}, // Inst #1605 = FEXUPL_W + {2, OperandInfo255}, // Inst #1606 = FEXUPR_D + {2, OperandInfo256}, // Inst #1607 = FEXUPR_W + {2, OperandInfo75}, // Inst #1608 = FFINT_S_D + {2, OperandInfo76}, // Inst #1609 = FFINT_S_W + {2, OperandInfo75}, // Inst #1610 = FFINT_U_D + {2, OperandInfo76}, // Inst #1611 = FFINT_U_W + {2, OperandInfo255}, // Inst #1612 = FFQL_D + {2, OperandInfo256}, // Inst #1613 = FFQL_W + {2, OperandInfo255}, // Inst #1614 = FFQR_D + {2, OperandInfo256}, // Inst #1615 = FFQR_W + {2, OperandInfo257}, // Inst #1616 = FILL_B + {2, OperandInfo258}, // Inst #1617 = FILL_D + {2, OperandInfo259}, // Inst #1618 = FILL_H + {2, OperandInfo260}, // Inst #1619 = FILL_W + {2, OperandInfo75}, // Inst #1620 = FLOG2_D + {2, OperandInfo76}, // Inst #1621 = FLOG2_W + {2, OperandInfo202}, // Inst #1622 = FLOOR_L_D64 + {2, OperandInfo202}, // Inst #1623 = FLOOR_L_D_MMR6 + {2, OperandInfo203}, // Inst #1624 = FLOOR_L_S + {2, OperandInfo203}, // Inst #1625 = FLOOR_L_S_MMR6 + {2, OperandInfo204}, // Inst #1626 = FLOOR_W_D32 + {2, OperandInfo205}, // Inst #1627 = FLOOR_W_D64 + {2, OperandInfo204}, // Inst #1628 = FLOOR_W_D_MMR6 + {2, OperandInfo204}, // Inst #1629 = FLOOR_W_MM + {2, OperandInfo206}, // Inst #1630 = FLOOR_W_S + {2, OperandInfo206}, // Inst #1631 = FLOOR_W_S_MM + {2, OperandInfo206}, // Inst #1632 = FLOOR_W_S_MMR6 + {4, OperandInfo58}, // Inst #1633 = FMADD_D + {4, OperandInfo59}, // Inst #1634 = FMADD_W + {3, OperandInfo45}, // Inst #1635 = FMAX_A_D + {3, OperandInfo47}, // Inst #1636 = FMAX_A_W + {3, OperandInfo45}, // Inst #1637 = FMAX_D + {3, OperandInfo47}, // Inst #1638 = FMAX_W + {3, OperandInfo45}, // Inst #1639 = FMIN_A_D + {3, OperandInfo47}, // Inst #1640 = FMIN_A_W + {3, OperandInfo45}, // Inst #1641 = FMIN_D + {3, OperandInfo47}, // Inst #1642 = FMIN_W + {2, OperandInfo247}, // Inst #1643 = FMOV_D32 + {2, OperandInfo247}, // Inst #1644 = FMOV_D32_MM + {2, OperandInfo202}, // Inst #1645 = FMOV_D64 + {2, OperandInfo202}, // Inst #1646 = FMOV_D64_MM + {2, OperandInfo202}, // Inst #1647 = FMOV_D_MMR6 + {2, OperandInfo206}, // Inst #1648 = FMOV_S + {2, OperandInfo206}, // Inst #1649 = FMOV_S_MM + {2, OperandInfo206}, // Inst #1650 = FMOV_S_MMR6 + {4, OperandInfo58}, // Inst #1651 = FMSUB_D + {4, OperandInfo59}, // Inst #1652 = FMSUB_W + {3, OperandInfo45}, // Inst #1653 = FMUL_D + {3, OperandInfo248}, // Inst #1654 = FMUL_D32 + {3, OperandInfo248}, // Inst #1655 = FMUL_D32_MM + {3, OperandInfo172}, // Inst #1656 = FMUL_D64 + {3, OperandInfo172}, // Inst #1657 = FMUL_D64_MM + {3, OperandInfo172}, // Inst #1658 = FMUL_PS64 + {3, OperandInfo249}, // Inst #1659 = FMUL_S + {3, OperandInfo249}, // Inst #1660 = FMUL_S_MM + {3, OperandInfo249}, // Inst #1661 = FMUL_S_MMR6 + {3, OperandInfo47}, // Inst #1662 = FMUL_W + {2, OperandInfo247}, // Inst #1663 = FNEG_D32 + {2, OperandInfo247}, // Inst #1664 = FNEG_D32_MM + {2, OperandInfo202}, // Inst #1665 = FNEG_D64 + {2, OperandInfo202}, // Inst #1666 = FNEG_D64_MM + {2, OperandInfo206}, // Inst #1667 = FNEG_S + {2, OperandInfo206}, // Inst #1668 = FNEG_S_MM + {2, OperandInfo206}, // Inst #1669 = FNEG_S_MMR6 + {3, OperandInfo71}, // Inst #1670 = FORK + {2, OperandInfo75}, // Inst #1671 = FRCP_D + {2, OperandInfo76}, // Inst #1672 = FRCP_W + {2, OperandInfo75}, // Inst #1673 = FRINT_D + {2, OperandInfo76}, // Inst #1674 = FRINT_W + {2, OperandInfo75}, // Inst #1675 = FRSQRT_D + {2, OperandInfo76}, // Inst #1676 = FRSQRT_W + {3, OperandInfo45}, // Inst #1677 = FSAF_D + {3, OperandInfo47}, // Inst #1678 = FSAF_W + {3, OperandInfo45}, // Inst #1679 = FSEQ_D + {3, OperandInfo47}, // Inst #1680 = FSEQ_W + {3, OperandInfo45}, // Inst #1681 = FSLE_D + {3, OperandInfo47}, // Inst #1682 = FSLE_W + {3, OperandInfo45}, // Inst #1683 = FSLT_D + {3, OperandInfo47}, // Inst #1684 = FSLT_W + {3, OperandInfo45}, // Inst #1685 = FSNE_D + {3, OperandInfo47}, // Inst #1686 = FSNE_W + {3, OperandInfo45}, // Inst #1687 = FSOR_D + {3, OperandInfo47}, // Inst #1688 = FSOR_W + {2, OperandInfo75}, // Inst #1689 = FSQRT_D + {2, OperandInfo247}, // Inst #1690 = FSQRT_D32 + {2, OperandInfo247}, // Inst #1691 = FSQRT_D32_MM + {2, OperandInfo202}, // Inst #1692 = FSQRT_D64 + {2, OperandInfo202}, // Inst #1693 = FSQRT_D64_MM + {2, OperandInfo206}, // Inst #1694 = FSQRT_S + {2, OperandInfo206}, // Inst #1695 = FSQRT_S_MM + {2, OperandInfo76}, // Inst #1696 = FSQRT_W + {3, OperandInfo45}, // Inst #1697 = FSUB_D + {3, OperandInfo248}, // Inst #1698 = FSUB_D32 + {3, OperandInfo248}, // Inst #1699 = FSUB_D32_MM + {3, OperandInfo172}, // Inst #1700 = FSUB_D64 + {3, OperandInfo172}, // Inst #1701 = FSUB_D64_MM + {3, OperandInfo172}, // Inst #1702 = FSUB_PS64 + {3, OperandInfo249}, // Inst #1703 = FSUB_S + {3, OperandInfo249}, // Inst #1704 = FSUB_S_MM + {3, OperandInfo249}, // Inst #1705 = FSUB_S_MMR6 + {3, OperandInfo47}, // Inst #1706 = FSUB_W + {3, OperandInfo45}, // Inst #1707 = FSUEQ_D + {3, OperandInfo47}, // Inst #1708 = FSUEQ_W + {3, OperandInfo45}, // Inst #1709 = FSULE_D + {3, OperandInfo47}, // Inst #1710 = FSULE_W + {3, OperandInfo45}, // Inst #1711 = FSULT_D + {3, OperandInfo47}, // Inst #1712 = FSULT_W + {3, OperandInfo45}, // Inst #1713 = FSUNE_D + {3, OperandInfo47}, // Inst #1714 = FSUNE_W + {3, OperandInfo45}, // Inst #1715 = FSUN_D + {3, OperandInfo47}, // Inst #1716 = FSUN_W + {2, OperandInfo75}, // Inst #1717 = FTINT_S_D + {2, OperandInfo76}, // Inst #1718 = FTINT_S_W + {2, OperandInfo75}, // Inst #1719 = FTINT_U_D + {2, OperandInfo76}, // Inst #1720 = FTINT_U_W + {3, OperandInfo253}, // Inst #1721 = FTQ_H + {3, OperandInfo254}, // Inst #1722 = FTQ_W + {2, OperandInfo75}, // Inst #1723 = FTRUNC_S_D + {2, OperandInfo76}, // Inst #1724 = FTRUNC_S_W + {2, OperandInfo75}, // Inst #1725 = FTRUNC_U_D + {2, OperandInfo76}, // Inst #1726 = FTRUNC_U_W + {1, OperandInfo57}, // Inst #1727 = GINVI + {1, OperandInfo57}, // Inst #1728 = GINVI_MMR6 + {2, OperandInfo113}, // Inst #1729 = GINVT + {2, OperandInfo113}, // Inst #1730 = GINVT_MMR6 + {3, OperandInfo236}, // Inst #1731 = HADD_S_D + {3, OperandInfo237}, // Inst #1732 = HADD_S_H + {3, OperandInfo238}, // Inst #1733 = HADD_S_W + {3, OperandInfo236}, // Inst #1734 = HADD_U_D + {3, OperandInfo237}, // Inst #1735 = HADD_U_H + {3, OperandInfo238}, // Inst #1736 = HADD_U_W + {3, OperandInfo236}, // Inst #1737 = HSUB_S_D + {3, OperandInfo237}, // Inst #1738 = HSUB_S_H + {3, OperandInfo238}, // Inst #1739 = HSUB_S_W + {3, OperandInfo236}, // Inst #1740 = HSUB_U_D + {3, OperandInfo237}, // Inst #1741 = HSUB_U_H + {3, OperandInfo238}, // Inst #1742 = HSUB_U_W + {1, OperandInfo2}, // Inst #1743 = HYPCALL + {1, OperandInfo2}, // Inst #1744 = HYPCALL_MM + {3, OperandInfo173}, // Inst #1745 = ILVEV_B + {3, OperandInfo45}, // Inst #1746 = ILVEV_D + {3, OperandInfo46}, // Inst #1747 = ILVEV_H + {3, OperandInfo47}, // Inst #1748 = ILVEV_W + {3, OperandInfo173}, // Inst #1749 = ILVL_B + {3, OperandInfo45}, // Inst #1750 = ILVL_D + {3, OperandInfo46}, // Inst #1751 = ILVL_H + {3, OperandInfo47}, // Inst #1752 = ILVL_W + {3, OperandInfo173}, // Inst #1753 = ILVOD_B + {3, OperandInfo45}, // Inst #1754 = ILVOD_D + {3, OperandInfo46}, // Inst #1755 = ILVOD_H + {3, OperandInfo47}, // Inst #1756 = ILVOD_W + {3, OperandInfo173}, // Inst #1757 = ILVR_B + {3, OperandInfo45}, // Inst #1758 = ILVR_D + {3, OperandInfo46}, // Inst #1759 = ILVR_H + {3, OperandInfo47}, // Inst #1760 = ILVR_W + {5, OperandInfo261}, // Inst #1761 = INS + {4, OperandInfo262}, // Inst #1762 = INSERT_B + {4, OperandInfo263}, // Inst #1763 = INSERT_D + {4, OperandInfo264}, // Inst #1764 = INSERT_H + {4, OperandInfo265}, // Inst #1765 = INSERT_W + {3, OperandInfo266}, // Inst #1766 = INSV + {5, OperandInfo267}, // Inst #1767 = INSVE_B + {5, OperandInfo268}, // Inst #1768 = INSVE_D + {5, OperandInfo269}, // Inst #1769 = INSVE_H + {5, OperandInfo270}, // Inst #1770 = INSVE_W + {3, OperandInfo266}, // Inst #1771 = INSV_MM + {5, OperandInfo261}, // Inst #1772 = INS_MM + {5, OperandInfo261}, // Inst #1773 = INS_MMR6 + {1, OperandInfo2}, // Inst #1774 = J + {1, OperandInfo2}, // Inst #1775 = JAL + {2, OperandInfo44}, // Inst #1776 = JALR + {1, OperandInfo57}, // Inst #1777 = JALR16_MM + {2, OperandInfo121}, // Inst #1778 = JALR64 + {1, OperandInfo57}, // Inst #1779 = JALRC16_MMR6 + {2, OperandInfo44}, // Inst #1780 = JALRC_HB_MMR6 + {2, OperandInfo44}, // Inst #1781 = JALRC_MMR6 + {1, OperandInfo57}, // Inst #1782 = JALRS16_MM + {2, OperandInfo44}, // Inst #1783 = JALRS_MM + {2, OperandInfo44}, // Inst #1784 = JALR_HB + {2, OperandInfo121}, // Inst #1785 = JALR_HB64 + {2, OperandInfo44}, // Inst #1786 = JALR_MM + {1, OperandInfo2}, // Inst #1787 = JALS_MM + {1, OperandInfo2}, // Inst #1788 = JALX + {1, OperandInfo2}, // Inst #1789 = JALX_MM + {1, OperandInfo2}, // Inst #1790 = JAL_MM + {2, OperandInfo113}, // Inst #1791 = JIALC + {2, OperandInfo111}, // Inst #1792 = JIALC64 + {2, OperandInfo113}, // Inst #1793 = JIALC_MMR6 + {2, OperandInfo113}, // Inst #1794 = JIC + {2, OperandInfo111}, // Inst #1795 = JIC64 + {2, OperandInfo113}, // Inst #1796 = JIC_MMR6 + {1, OperandInfo57}, // Inst #1797 = JR + {1, OperandInfo57}, // Inst #1798 = JR16_MM + {1, OperandInfo94}, // Inst #1799 = JR64 + {1, OperandInfo2}, // Inst #1800 = JRADDIUSP + {1, OperandInfo57}, // Inst #1801 = JRC16_MM + {1, OperandInfo57}, // Inst #1802 = JRC16_MMR6 + {1, OperandInfo2}, // Inst #1803 = JRCADDIUSP_MMR6 + {1, OperandInfo57}, // Inst #1804 = JR_HB + {1, OperandInfo94}, // Inst #1805 = JR_HB64 + {1, OperandInfo94}, // Inst #1806 = JR_HB64_R6 + {1, OperandInfo57}, // Inst #1807 = JR_HB_R6 + {1, OperandInfo57}, // Inst #1808 = JR_MM + {1, OperandInfo2}, // Inst #1809 = J_MM + {1, OperandInfo2}, // Inst #1810 = Jal16 + {1, OperandInfo2}, // Inst #1811 = JalB16 + {0, NULL}, // Inst #1812 = JrRa16 + {0, NULL}, // Inst #1813 = JrcRa16 + {1, OperandInfo271}, // Inst #1814 = JrcRx16 + {1, OperandInfo271}, // Inst #1815 = JumpLinkReg16 + {3, OperandInfo95}, // Inst #1816 = LB + {3, OperandInfo112}, // Inst #1817 = LB64 + {3, OperandInfo95}, // Inst #1818 = LBE + {3, OperandInfo95}, // Inst #1819 = LBE_MM + {3, OperandInfo272}, // Inst #1820 = LBU16_MM + {3, OperandInfo273}, // Inst #1821 = LBUX + {3, OperandInfo273}, // Inst #1822 = LBUX_MM + {3, OperandInfo95}, // Inst #1823 = LBU_MMR6 + {3, OperandInfo95}, // Inst #1824 = LB_MM + {3, OperandInfo95}, // Inst #1825 = LB_MMR6 + {3, OperandInfo95}, // Inst #1826 = LBu + {3, OperandInfo112}, // Inst #1827 = LBu64 + {3, OperandInfo95}, // Inst #1828 = LBuE + {3, OperandInfo95}, // Inst #1829 = LBuE_MM + {3, OperandInfo95}, // Inst #1830 = LBu_MM + {3, OperandInfo112}, // Inst #1831 = LD + {3, OperandInfo157}, // Inst #1832 = LDC1 + {3, OperandInfo274}, // Inst #1833 = LDC164 + {3, OperandInfo274}, // Inst #1834 = LDC1_D64_MMR6 + {3, OperandInfo157}, // Inst #1835 = LDC1_MM + {3, OperandInfo275}, // Inst #1836 = LDC2 + {3, OperandInfo276}, // Inst #1837 = LDC2_MMR6 + {3, OperandInfo275}, // Inst #1838 = LDC2_R6 + {3, OperandInfo277}, // Inst #1839 = LDC3 + {2, OperandInfo278}, // Inst #1840 = LDI_B + {2, OperandInfo279}, // Inst #1841 = LDI_D + {2, OperandInfo280}, // Inst #1842 = LDI_H + {2, OperandInfo281}, // Inst #1843 = LDI_W + {4, OperandInfo282}, // Inst #1844 = LDL + {2, OperandInfo111}, // Inst #1845 = LDPC + {4, OperandInfo282}, // Inst #1846 = LDR + {3, OperandInfo283}, // Inst #1847 = LDXC1 + {3, OperandInfo284}, // Inst #1848 = LDXC164 + {3, OperandInfo285}, // Inst #1849 = LD_B + {3, OperandInfo286}, // Inst #1850 = LD_D + {3, OperandInfo287}, // Inst #1851 = LD_H + {3, OperandInfo288}, // Inst #1852 = LD_W + {3, OperandInfo95}, // Inst #1853 = LEA_ADDiu + {3, OperandInfo112}, // Inst #1854 = LEA_ADDiu64 + {3, OperandInfo95}, // Inst #1855 = LEA_ADDiu_MM + {3, OperandInfo95}, // Inst #1856 = LH + {3, OperandInfo112}, // Inst #1857 = LH64 + {3, OperandInfo95}, // Inst #1858 = LHE + {3, OperandInfo95}, // Inst #1859 = LHE_MM + {3, OperandInfo272}, // Inst #1860 = LHU16_MM + {3, OperandInfo273}, // Inst #1861 = LHX + {3, OperandInfo273}, // Inst #1862 = LHX_MM + {3, OperandInfo95}, // Inst #1863 = LH_MM + {3, OperandInfo95}, // Inst #1864 = LHu + {3, OperandInfo112}, // Inst #1865 = LHu64 + {3, OperandInfo95}, // Inst #1866 = LHuE + {3, OperandInfo95}, // Inst #1867 = LHuE_MM + {3, OperandInfo95}, // Inst #1868 = LHu_MM + {2, OperandInfo168}, // Inst #1869 = LI16_MM + {2, OperandInfo168}, // Inst #1870 = LI16_MMR6 + {3, OperandInfo95}, // Inst #1871 = LL + {3, OperandInfo95}, // Inst #1872 = LL64 + {3, OperandInfo289}, // Inst #1873 = LL64_R6 + {3, OperandInfo112}, // Inst #1874 = LLD + {3, OperandInfo290}, // Inst #1875 = LLD_R6 + {3, OperandInfo95}, // Inst #1876 = LLE + {3, OperandInfo95}, // Inst #1877 = LLE_MM + {3, OperandInfo95}, // Inst #1878 = LL_MM + {3, OperandInfo95}, // Inst #1879 = LL_MMR6 + {3, OperandInfo289}, // Inst #1880 = LL_R6 + {4, OperandInfo179}, // Inst #1881 = LSA + {4, OperandInfo179}, // Inst #1882 = LSA_MMR6 + {4, OperandInfo179}, // Inst #1883 = LSA_R6 + {2, OperandInfo113}, // Inst #1884 = LUI_MMR6 + {3, OperandInfo283}, // Inst #1885 = LUXC1 + {3, OperandInfo284}, // Inst #1886 = LUXC164 + {3, OperandInfo284}, // Inst #1887 = LUXC1_MM + {2, OperandInfo113}, // Inst #1888 = LUi + {2, OperandInfo111}, // Inst #1889 = LUi64 + {2, OperandInfo113}, // Inst #1890 = LUi_MM + {3, OperandInfo95}, // Inst #1891 = LW + {3, OperandInfo272}, // Inst #1892 = LW16_MM + {3, OperandInfo112}, // Inst #1893 = LW64 + {3, OperandInfo291}, // Inst #1894 = LWC1 + {3, OperandInfo291}, // Inst #1895 = LWC1_MM + {3, OperandInfo275}, // Inst #1896 = LWC2 + {3, OperandInfo276}, // Inst #1897 = LWC2_MMR6 + {3, OperandInfo275}, // Inst #1898 = LWC2_R6 + {3, OperandInfo277}, // Inst #1899 = LWC3 + {3, OperandInfo292}, // Inst #1900 = LWDSP + {3, OperandInfo292}, // Inst #1901 = LWDSP_MM + {3, OperandInfo95}, // Inst #1902 = LWE + {3, OperandInfo95}, // Inst #1903 = LWE_MM + {3, OperandInfo293}, // Inst #1904 = LWGP_MM + {4, OperandInfo294}, // Inst #1905 = LWL + {4, OperandInfo282}, // Inst #1906 = LWL64 + {4, OperandInfo294}, // Inst #1907 = LWLE + {4, OperandInfo294}, // Inst #1908 = LWLE_MM + {4, OperandInfo294}, // Inst #1909 = LWL_MM + {3, OperandInfo295}, // Inst #1910 = LWM16_MM + {3, OperandInfo295}, // Inst #1911 = LWM16_MMR6 + {3, OperandInfo109}, // Inst #1912 = LWM32_MM + {2, OperandInfo113}, // Inst #1913 = LWPC + {2, OperandInfo113}, // Inst #1914 = LWPC_MMR6 + {4, OperandInfo296}, // Inst #1915 = LWP_MM + {4, OperandInfo294}, // Inst #1916 = LWR + {4, OperandInfo282}, // Inst #1917 = LWR64 + {4, OperandInfo294}, // Inst #1918 = LWRE + {4, OperandInfo294}, // Inst #1919 = LWRE_MM + {4, OperandInfo294}, // Inst #1920 = LWR_MM + {3, OperandInfo297}, // Inst #1921 = LWSP_MM + {2, OperandInfo113}, // Inst #1922 = LWUPC + {3, OperandInfo95}, // Inst #1923 = LWU_MM + {3, OperandInfo273}, // Inst #1924 = LWX + {3, OperandInfo298}, // Inst #1925 = LWXC1 + {3, OperandInfo298}, // Inst #1926 = LWXC1_MM + {3, OperandInfo273}, // Inst #1927 = LWXS_MM + {3, OperandInfo273}, // Inst #1928 = LWX_MM + {3, OperandInfo95}, // Inst #1929 = LW_MM + {3, OperandInfo95}, // Inst #1930 = LW_MMR6 + {3, OperandInfo112}, // Inst #1931 = LWu + {3, OperandInfo299}, // Inst #1932 = LbRxRyOffMemX16 + {3, OperandInfo299}, // Inst #1933 = LbuRxRyOffMemX16 + {3, OperandInfo299}, // Inst #1934 = LhRxRyOffMemX16 + {3, OperandInfo299}, // Inst #1935 = LhuRxRyOffMemX16 + {2, OperandInfo182}, // Inst #1936 = LiRxImm16 + {2, OperandInfo182}, // Inst #1937 = LiRxImmAlignX16 + {2, OperandInfo182}, // Inst #1938 = LiRxImmX16 + {3, OperandInfo300}, // Inst #1939 = LwRxPcTcp16 + {3, OperandInfo300}, // Inst #1940 = LwRxPcTcpX16 + {3, OperandInfo299}, // Inst #1941 = LwRxRyOffMemX16 + {3, OperandInfo184}, // Inst #1942 = LwRxSpImmX16 + {2, OperandInfo44}, // Inst #1943 = MADD + {4, OperandInfo301}, // Inst #1944 = MADDF_D + {4, OperandInfo301}, // Inst #1945 = MADDF_D_MMR6 + {4, OperandInfo302}, // Inst #1946 = MADDF_S + {4, OperandInfo302}, // Inst #1947 = MADDF_S_MMR6 + {4, OperandInfo60}, // Inst #1948 = MADDR_Q_H + {4, OperandInfo59}, // Inst #1949 = MADDR_Q_W + {2, OperandInfo44}, // Inst #1950 = MADDU + {4, OperandInfo242}, // Inst #1951 = MADDU_DSP + {4, OperandInfo242}, // Inst #1952 = MADDU_DSP_MM + {2, OperandInfo44}, // Inst #1953 = MADDU_MM + {4, OperandInfo195}, // Inst #1954 = MADDV_B + {4, OperandInfo58}, // Inst #1955 = MADDV_D + {4, OperandInfo60}, // Inst #1956 = MADDV_H + {4, OperandInfo59}, // Inst #1957 = MADDV_W + {4, OperandInfo303}, // Inst #1958 = MADD_D32 + {4, OperandInfo303}, // Inst #1959 = MADD_D32_MM + {4, OperandInfo304}, // Inst #1960 = MADD_D64 + {4, OperandInfo242}, // Inst #1961 = MADD_DSP + {4, OperandInfo242}, // Inst #1962 = MADD_DSP_MM + {2, OperandInfo44}, // Inst #1963 = MADD_MM + {4, OperandInfo60}, // Inst #1964 = MADD_Q_H + {4, OperandInfo59}, // Inst #1965 = MADD_Q_W + {4, OperandInfo305}, // Inst #1966 = MADD_S + {4, OperandInfo305}, // Inst #1967 = MADD_S_MM + {4, OperandInfo242}, // Inst #1968 = MAQ_SA_W_PHL + {4, OperandInfo242}, // Inst #1969 = MAQ_SA_W_PHL_MM + {4, OperandInfo242}, // Inst #1970 = MAQ_SA_W_PHR + {4, OperandInfo242}, // Inst #1971 = MAQ_SA_W_PHR_MM + {4, OperandInfo242}, // Inst #1972 = MAQ_S_W_PHL + {4, OperandInfo242}, // Inst #1973 = MAQ_S_W_PHL_MM + {4, OperandInfo242}, // Inst #1974 = MAQ_S_W_PHR + {4, OperandInfo242}, // Inst #1975 = MAQ_S_W_PHR_MM + {3, OperandInfo172}, // Inst #1976 = MAXA_D + {3, OperandInfo172}, // Inst #1977 = MAXA_D_MMR6 + {3, OperandInfo249}, // Inst #1978 = MAXA_S + {3, OperandInfo249}, // Inst #1979 = MAXA_S_MMR6 + {3, OperandInfo175}, // Inst #1980 = MAXI_S_B + {3, OperandInfo176}, // Inst #1981 = MAXI_S_D + {3, OperandInfo177}, // Inst #1982 = MAXI_S_H + {3, OperandInfo178}, // Inst #1983 = MAXI_S_W + {3, OperandInfo175}, // Inst #1984 = MAXI_U_B + {3, OperandInfo176}, // Inst #1985 = MAXI_U_D + {3, OperandInfo177}, // Inst #1986 = MAXI_U_H + {3, OperandInfo178}, // Inst #1987 = MAXI_U_W + {3, OperandInfo173}, // Inst #1988 = MAX_A_B + {3, OperandInfo45}, // Inst #1989 = MAX_A_D + {3, OperandInfo46}, // Inst #1990 = MAX_A_H + {3, OperandInfo47}, // Inst #1991 = MAX_A_W + {3, OperandInfo172}, // Inst #1992 = MAX_D + {3, OperandInfo172}, // Inst #1993 = MAX_D_MMR6 + {3, OperandInfo249}, // Inst #1994 = MAX_S + {3, OperandInfo173}, // Inst #1995 = MAX_S_B + {3, OperandInfo45}, // Inst #1996 = MAX_S_D + {3, OperandInfo46}, // Inst #1997 = MAX_S_H + {3, OperandInfo249}, // Inst #1998 = MAX_S_MMR6 + {3, OperandInfo47}, // Inst #1999 = MAX_S_W + {3, OperandInfo173}, // Inst #2000 = MAX_U_B + {3, OperandInfo45}, // Inst #2001 = MAX_U_D + {3, OperandInfo46}, // Inst #2002 = MAX_U_H + {3, OperandInfo47}, // Inst #2003 = MAX_U_W + {3, OperandInfo119}, // Inst #2004 = MFC0 + {3, OperandInfo119}, // Inst #2005 = MFC0_MMR6 + {2, OperandInfo120}, // Inst #2006 = MFC1 + {2, OperandInfo306}, // Inst #2007 = MFC1_D64 + {2, OperandInfo120}, // Inst #2008 = MFC1_MM + {2, OperandInfo120}, // Inst #2009 = MFC1_MMR6 + {3, OperandInfo307}, // Inst #2010 = MFC2 + {2, OperandInfo208}, // Inst #2011 = MFC2_MMR6 + {3, OperandInfo119}, // Inst #2012 = MFGC0 + {3, OperandInfo119}, // Inst #2013 = MFGC0_MM + {3, OperandInfo119}, // Inst #2014 = MFHC0_MMR6 + {2, OperandInfo308}, // Inst #2015 = MFHC1_D32 + {2, OperandInfo308}, // Inst #2016 = MFHC1_D32_MM + {2, OperandInfo306}, // Inst #2017 = MFHC1_D64 + {2, OperandInfo306}, // Inst #2018 = MFHC1_D64_MM + {2, OperandInfo208}, // Inst #2019 = MFHC2_MMR6 + {3, OperandInfo119}, // Inst #2020 = MFHGC0 + {3, OperandInfo119}, // Inst #2021 = MFHGC0_MM + {1, OperandInfo57}, // Inst #2022 = MFHI + {1, OperandInfo57}, // Inst #2023 = MFHI16_MM + {1, OperandInfo94}, // Inst #2024 = MFHI64 + {2, OperandInfo118}, // Inst #2025 = MFHI_DSP + {2, OperandInfo118}, // Inst #2026 = MFHI_DSP_MM + {1, OperandInfo57}, // Inst #2027 = MFHI_MM + {1, OperandInfo57}, // Inst #2028 = MFLO + {1, OperandInfo57}, // Inst #2029 = MFLO16_MM + {1, OperandInfo94}, // Inst #2030 = MFLO64 + {2, OperandInfo118}, // Inst #2031 = MFLO_DSP + {2, OperandInfo118}, // Inst #2032 = MFLO_DSP_MM + {1, OperandInfo57}, // Inst #2033 = MFLO_MM + {5, OperandInfo309}, // Inst #2034 = MFTR + {3, OperandInfo172}, // Inst #2035 = MINA_D + {3, OperandInfo172}, // Inst #2036 = MINA_D_MMR6 + {3, OperandInfo249}, // Inst #2037 = MINA_S + {3, OperandInfo249}, // Inst #2038 = MINA_S_MMR6 + {3, OperandInfo175}, // Inst #2039 = MINI_S_B + {3, OperandInfo176}, // Inst #2040 = MINI_S_D + {3, OperandInfo177}, // Inst #2041 = MINI_S_H + {3, OperandInfo178}, // Inst #2042 = MINI_S_W + {3, OperandInfo175}, // Inst #2043 = MINI_U_B + {3, OperandInfo176}, // Inst #2044 = MINI_U_D + {3, OperandInfo177}, // Inst #2045 = MINI_U_H + {3, OperandInfo178}, // Inst #2046 = MINI_U_W + {3, OperandInfo173}, // Inst #2047 = MIN_A_B + {3, OperandInfo45}, // Inst #2048 = MIN_A_D + {3, OperandInfo46}, // Inst #2049 = MIN_A_H + {3, OperandInfo47}, // Inst #2050 = MIN_A_W + {3, OperandInfo172}, // Inst #2051 = MIN_D + {3, OperandInfo172}, // Inst #2052 = MIN_D_MMR6 + {3, OperandInfo249}, // Inst #2053 = MIN_S + {3, OperandInfo173}, // Inst #2054 = MIN_S_B + {3, OperandInfo45}, // Inst #2055 = MIN_S_D + {3, OperandInfo46}, // Inst #2056 = MIN_S_H + {3, OperandInfo249}, // Inst #2057 = MIN_S_MMR6 + {3, OperandInfo47}, // Inst #2058 = MIN_S_W + {3, OperandInfo173}, // Inst #2059 = MIN_U_B + {3, OperandInfo45}, // Inst #2060 = MIN_U_D + {3, OperandInfo46}, // Inst #2061 = MIN_U_H + {3, OperandInfo47}, // Inst #2062 = MIN_U_W + {3, OperandInfo71}, // Inst #2063 = MOD + {3, OperandInfo71}, // Inst #2064 = MODSUB + {3, OperandInfo71}, // Inst #2065 = MODSUB_MM + {3, OperandInfo71}, // Inst #2066 = MODU + {3, OperandInfo71}, // Inst #2067 = MODU_MMR6 + {3, OperandInfo71}, // Inst #2068 = MOD_MMR6 + {3, OperandInfo173}, // Inst #2069 = MOD_S_B + {3, OperandInfo45}, // Inst #2070 = MOD_S_D + {3, OperandInfo46}, // Inst #2071 = MOD_S_H + {3, OperandInfo47}, // Inst #2072 = MOD_S_W + {3, OperandInfo173}, // Inst #2073 = MOD_U_B + {3, OperandInfo45}, // Inst #2074 = MOD_U_D + {3, OperandInfo46}, // Inst #2075 = MOD_U_H + {3, OperandInfo47}, // Inst #2076 = MOD_U_W + {2, OperandInfo44}, // Inst #2077 = MOVE16_MM + {2, OperandInfo44}, // Inst #2078 = MOVE16_MMR6 + {4, OperandInfo310}, // Inst #2079 = MOVEP_MM + {4, OperandInfo310}, // Inst #2080 = MOVEP_MMR6 + {2, OperandInfo311}, // Inst #2081 = MOVE_V + {4, OperandInfo312}, // Inst #2082 = MOVF_D32 + {4, OperandInfo312}, // Inst #2083 = MOVF_D32_MM + {4, OperandInfo313}, // Inst #2084 = MOVF_D64 + {4, OperandInfo314}, // Inst #2085 = MOVF_I + {4, OperandInfo315}, // Inst #2086 = MOVF_I64 + {4, OperandInfo314}, // Inst #2087 = MOVF_I_MM + {4, OperandInfo316}, // Inst #2088 = MOVF_S + {4, OperandInfo316}, // Inst #2089 = MOVF_S_MM + {4, OperandInfo317}, // Inst #2090 = MOVN_I64_D64 + {4, OperandInfo318}, // Inst #2091 = MOVN_I64_I + {4, OperandInfo319}, // Inst #2092 = MOVN_I64_I64 + {4, OperandInfo320}, // Inst #2093 = MOVN_I64_S + {4, OperandInfo321}, // Inst #2094 = MOVN_I_D32 + {4, OperandInfo321}, // Inst #2095 = MOVN_I_D32_MM + {4, OperandInfo322}, // Inst #2096 = MOVN_I_D64 + {4, OperandInfo323}, // Inst #2097 = MOVN_I_I + {4, OperandInfo324}, // Inst #2098 = MOVN_I_I64 + {4, OperandInfo323}, // Inst #2099 = MOVN_I_MM + {4, OperandInfo325}, // Inst #2100 = MOVN_I_S + {4, OperandInfo325}, // Inst #2101 = MOVN_I_S_MM + {4, OperandInfo312}, // Inst #2102 = MOVT_D32 + {4, OperandInfo312}, // Inst #2103 = MOVT_D32_MM + {4, OperandInfo313}, // Inst #2104 = MOVT_D64 + {4, OperandInfo314}, // Inst #2105 = MOVT_I + {4, OperandInfo315}, // Inst #2106 = MOVT_I64 + {4, OperandInfo314}, // Inst #2107 = MOVT_I_MM + {4, OperandInfo316}, // Inst #2108 = MOVT_S + {4, OperandInfo316}, // Inst #2109 = MOVT_S_MM + {4, OperandInfo317}, // Inst #2110 = MOVZ_I64_D64 + {4, OperandInfo318}, // Inst #2111 = MOVZ_I64_I + {4, OperandInfo319}, // Inst #2112 = MOVZ_I64_I64 + {4, OperandInfo320}, // Inst #2113 = MOVZ_I64_S + {4, OperandInfo321}, // Inst #2114 = MOVZ_I_D32 + {4, OperandInfo321}, // Inst #2115 = MOVZ_I_D32_MM + {4, OperandInfo322}, // Inst #2116 = MOVZ_I_D64 + {4, OperandInfo323}, // Inst #2117 = MOVZ_I_I + {4, OperandInfo324}, // Inst #2118 = MOVZ_I_I64 + {4, OperandInfo323}, // Inst #2119 = MOVZ_I_MM + {4, OperandInfo325}, // Inst #2120 = MOVZ_I_S + {4, OperandInfo325}, // Inst #2121 = MOVZ_I_S_MM + {2, OperandInfo44}, // Inst #2122 = MSUB + {4, OperandInfo301}, // Inst #2123 = MSUBF_D + {4, OperandInfo301}, // Inst #2124 = MSUBF_D_MMR6 + {4, OperandInfo302}, // Inst #2125 = MSUBF_S + {4, OperandInfo302}, // Inst #2126 = MSUBF_S_MMR6 + {4, OperandInfo60}, // Inst #2127 = MSUBR_Q_H + {4, OperandInfo59}, // Inst #2128 = MSUBR_Q_W + {2, OperandInfo44}, // Inst #2129 = MSUBU + {4, OperandInfo242}, // Inst #2130 = MSUBU_DSP + {4, OperandInfo242}, // Inst #2131 = MSUBU_DSP_MM + {2, OperandInfo44}, // Inst #2132 = MSUBU_MM + {4, OperandInfo195}, // Inst #2133 = MSUBV_B + {4, OperandInfo58}, // Inst #2134 = MSUBV_D + {4, OperandInfo60}, // Inst #2135 = MSUBV_H + {4, OperandInfo59}, // Inst #2136 = MSUBV_W + {4, OperandInfo303}, // Inst #2137 = MSUB_D32 + {4, OperandInfo303}, // Inst #2138 = MSUB_D32_MM + {4, OperandInfo304}, // Inst #2139 = MSUB_D64 + {4, OperandInfo242}, // Inst #2140 = MSUB_DSP + {4, OperandInfo242}, // Inst #2141 = MSUB_DSP_MM + {2, OperandInfo44}, // Inst #2142 = MSUB_MM + {4, OperandInfo60}, // Inst #2143 = MSUB_Q_H + {4, OperandInfo59}, // Inst #2144 = MSUB_Q_W + {4, OperandInfo305}, // Inst #2145 = MSUB_S + {4, OperandInfo305}, // Inst #2146 = MSUB_S_MM + {3, OperandInfo127}, // Inst #2147 = MTC0 + {3, OperandInfo127}, // Inst #2148 = MTC0_MMR6 + {2, OperandInfo128}, // Inst #2149 = MTC1 + {2, OperandInfo134}, // Inst #2150 = MTC1_D64 + {2, OperandInfo134}, // Inst #2151 = MTC1_D64_MM + {2, OperandInfo128}, // Inst #2152 = MTC1_MM + {2, OperandInfo128}, // Inst #2153 = MTC1_MMR6 + {3, OperandInfo326}, // Inst #2154 = MTC2 + {2, OperandInfo221}, // Inst #2155 = MTC2_MMR6 + {3, OperandInfo127}, // Inst #2156 = MTGC0 + {3, OperandInfo127}, // Inst #2157 = MTGC0_MM + {3, OperandInfo127}, // Inst #2158 = MTHC0_MMR6 + {3, OperandInfo327}, // Inst #2159 = MTHC1_D32 + {3, OperandInfo327}, // Inst #2160 = MTHC1_D32_MM + {3, OperandInfo328}, // Inst #2161 = MTHC1_D64 + {3, OperandInfo328}, // Inst #2162 = MTHC1_D64_MM + {2, OperandInfo221}, // Inst #2163 = MTHC2_MMR6 + {3, OperandInfo127}, // Inst #2164 = MTHGC0 + {3, OperandInfo127}, // Inst #2165 = MTHGC0_MM + {1, OperandInfo57}, // Inst #2166 = MTHI + {1, OperandInfo94}, // Inst #2167 = MTHI64 + {2, OperandInfo329}, // Inst #2168 = MTHI_DSP + {2, OperandInfo329}, // Inst #2169 = MTHI_DSP_MM + {1, OperandInfo57}, // Inst #2170 = MTHI_MM + {3, OperandInfo330}, // Inst #2171 = MTHLIP + {3, OperandInfo330}, // Inst #2172 = MTHLIP_MM + {1, OperandInfo57}, // Inst #2173 = MTLO + {1, OperandInfo94}, // Inst #2174 = MTLO64 + {2, OperandInfo331}, // Inst #2175 = MTLO_DSP + {2, OperandInfo331}, // Inst #2176 = MTLO_DSP_MM + {1, OperandInfo57}, // Inst #2177 = MTLO_MM + {1, OperandInfo94}, // Inst #2178 = MTM0 + {1, OperandInfo94}, // Inst #2179 = MTM1 + {1, OperandInfo94}, // Inst #2180 = MTM2 + {1, OperandInfo94}, // Inst #2181 = MTP0 + {1, OperandInfo94}, // Inst #2182 = MTP1 + {1, OperandInfo94}, // Inst #2183 = MTP2 + {5, OperandInfo309}, // Inst #2184 = MTTR + {3, OperandInfo71}, // Inst #2185 = MUH + {3, OperandInfo71}, // Inst #2186 = MUHU + {3, OperandInfo71}, // Inst #2187 = MUHU_MMR6 + {3, OperandInfo71}, // Inst #2188 = MUH_MMR6 + {3, OperandInfo71}, // Inst #2189 = MUL + {3, OperandInfo213}, // Inst #2190 = MULEQ_S_W_PHL + {3, OperandInfo213}, // Inst #2191 = MULEQ_S_W_PHL_MM + {3, OperandInfo213}, // Inst #2192 = MULEQ_S_W_PHR + {3, OperandInfo213}, // Inst #2193 = MULEQ_S_W_PHR_MM + {3, OperandInfo171}, // Inst #2194 = MULEU_S_PH_QBL + {3, OperandInfo171}, // Inst #2195 = MULEU_S_PH_QBL_MM + {3, OperandInfo171}, // Inst #2196 = MULEU_S_PH_QBR + {3, OperandInfo171}, // Inst #2197 = MULEU_S_PH_QBR_MM + {3, OperandInfo171}, // Inst #2198 = MULQ_RS_PH + {3, OperandInfo171}, // Inst #2199 = MULQ_RS_PH_MM + {3, OperandInfo71}, // Inst #2200 = MULQ_RS_W + {3, OperandInfo71}, // Inst #2201 = MULQ_RS_W_MMR2 + {3, OperandInfo171}, // Inst #2202 = MULQ_S_PH + {3, OperandInfo171}, // Inst #2203 = MULQ_S_PH_MMR2 + {3, OperandInfo71}, // Inst #2204 = MULQ_S_W + {3, OperandInfo71}, // Inst #2205 = MULQ_S_W_MMR2 + {3, OperandInfo172}, // Inst #2206 = MULR_PS64 + {3, OperandInfo46}, // Inst #2207 = MULR_Q_H + {3, OperandInfo47}, // Inst #2208 = MULR_Q_W + {4, OperandInfo242}, // Inst #2209 = MULSAQ_S_W_PH + {4, OperandInfo242}, // Inst #2210 = MULSAQ_S_W_PH_MM + {4, OperandInfo242}, // Inst #2211 = MULSA_W_PH + {4, OperandInfo242}, // Inst #2212 = MULSA_W_PH_MMR2 + {2, OperandInfo44}, // Inst #2213 = MULT + {3, OperandInfo142}, // Inst #2214 = MULTU_DSP + {3, OperandInfo142}, // Inst #2215 = MULTU_DSP_MM + {3, OperandInfo142}, // Inst #2216 = MULT_DSP + {3, OperandInfo142}, // Inst #2217 = MULT_DSP_MM + {2, OperandInfo44}, // Inst #2218 = MULT_MM + {2, OperandInfo44}, // Inst #2219 = MULTu + {2, OperandInfo44}, // Inst #2220 = MULTu_MM + {3, OperandInfo71}, // Inst #2221 = MULU + {3, OperandInfo71}, // Inst #2222 = MULU_MMR6 + {3, OperandInfo173}, // Inst #2223 = MULV_B + {3, OperandInfo45}, // Inst #2224 = MULV_D + {3, OperandInfo46}, // Inst #2225 = MULV_H + {3, OperandInfo47}, // Inst #2226 = MULV_W + {3, OperandInfo71}, // Inst #2227 = MUL_MM + {3, OperandInfo71}, // Inst #2228 = MUL_MMR6 + {3, OperandInfo171}, // Inst #2229 = MUL_PH + {3, OperandInfo171}, // Inst #2230 = MUL_PH_MMR2 + {3, OperandInfo46}, // Inst #2231 = MUL_Q_H + {3, OperandInfo47}, // Inst #2232 = MUL_Q_W + {3, OperandInfo71}, // Inst #2233 = MUL_R6 + {3, OperandInfo171}, // Inst #2234 = MUL_S_PH + {3, OperandInfo171}, // Inst #2235 = MUL_S_PH_MMR2 + {1, OperandInfo271}, // Inst #2236 = Mfhi16 + {1, OperandInfo271}, // Inst #2237 = Mflo16 + {2, OperandInfo332}, // Inst #2238 = Move32R16 + {2, OperandInfo333}, // Inst #2239 = MoveR3216 + {2, OperandInfo311}, // Inst #2240 = NLOC_B + {2, OperandInfo75}, // Inst #2241 = NLOC_D + {2, OperandInfo334}, // Inst #2242 = NLOC_H + {2, OperandInfo76}, // Inst #2243 = NLOC_W + {2, OperandInfo311}, // Inst #2244 = NLZC_B + {2, OperandInfo75}, // Inst #2245 = NLZC_D + {2, OperandInfo334}, // Inst #2246 = NLZC_H + {2, OperandInfo76}, // Inst #2247 = NLZC_W + {4, OperandInfo303}, // Inst #2248 = NMADD_D32 + {4, OperandInfo303}, // Inst #2249 = NMADD_D32_MM + {4, OperandInfo304}, // Inst #2250 = NMADD_D64 + {4, OperandInfo305}, // Inst #2251 = NMADD_S + {4, OperandInfo305}, // Inst #2252 = NMADD_S_MM + {4, OperandInfo303}, // Inst #2253 = NMSUB_D32 + {4, OperandInfo303}, // Inst #2254 = NMSUB_D32_MM + {4, OperandInfo304}, // Inst #2255 = NMSUB_D64 + {4, OperandInfo305}, // Inst #2256 = NMSUB_S + {4, OperandInfo305}, // Inst #2257 = NMSUB_S_MM + {3, OperandInfo71}, // Inst #2258 = NOR + {3, OperandInfo70}, // Inst #2259 = NOR64 + {3, OperandInfo175}, // Inst #2260 = NORI_B + {3, OperandInfo71}, // Inst #2261 = NOR_MM + {3, OperandInfo71}, // Inst #2262 = NOR_MMR6 + {3, OperandInfo173}, // Inst #2263 = NOR_V + {2, OperandInfo335}, // Inst #2264 = NOT16_MM + {2, OperandInfo335}, // Inst #2265 = NOT16_MMR6 + {2, OperandInfo129}, // Inst #2266 = NegRxRy16 + {2, OperandInfo129}, // Inst #2267 = NotRxRy16 + {3, OperandInfo71}, // Inst #2268 = OR + {3, OperandInfo180}, // Inst #2269 = OR16_MM + {3, OperandInfo180}, // Inst #2270 = OR16_MMR6 + {3, OperandInfo70}, // Inst #2271 = OR64 + {3, OperandInfo175}, // Inst #2272 = ORI_B + {3, OperandInfo72}, // Inst #2273 = ORI_MMR6 + {3, OperandInfo71}, // Inst #2274 = OR_MM + {3, OperandInfo71}, // Inst #2275 = OR_MMR6 + {3, OperandInfo173}, // Inst #2276 = OR_V + {3, OperandInfo72}, // Inst #2277 = ORi + {3, OperandInfo69}, // Inst #2278 = ORi64 + {3, OperandInfo72}, // Inst #2279 = ORi_MM + {3, OperandInfo185}, // Inst #2280 = OrRxRxRy16 + {3, OperandInfo171}, // Inst #2281 = PACKRL_PH + {3, OperandInfo171}, // Inst #2282 = PACKRL_PH_MM + {0, NULL}, // Inst #2283 = PAUSE + {0, NULL}, // Inst #2284 = PAUSE_MM + {0, NULL}, // Inst #2285 = PAUSE_MMR6 + {3, OperandInfo173}, // Inst #2286 = PCKEV_B + {3, OperandInfo45}, // Inst #2287 = PCKEV_D + {3, OperandInfo46}, // Inst #2288 = PCKEV_H + {3, OperandInfo47}, // Inst #2289 = PCKEV_W + {3, OperandInfo173}, // Inst #2290 = PCKOD_B + {3, OperandInfo45}, // Inst #2291 = PCKOD_D + {3, OperandInfo46}, // Inst #2292 = PCKOD_H + {3, OperandInfo47}, // Inst #2293 = PCKOD_W + {2, OperandInfo311}, // Inst #2294 = PCNT_B + {2, OperandInfo75}, // Inst #2295 = PCNT_D + {2, OperandInfo334}, // Inst #2296 = PCNT_H + {2, OperandInfo76}, // Inst #2297 = PCNT_W + {3, OperandInfo171}, // Inst #2298 = PICK_PH + {3, OperandInfo171}, // Inst #2299 = PICK_PH_MM + {3, OperandInfo171}, // Inst #2300 = PICK_QB + {3, OperandInfo171}, // Inst #2301 = PICK_QB_MM + {3, OperandInfo172}, // Inst #2302 = PLL_PS64 + {3, OperandInfo172}, // Inst #2303 = PLU_PS64 + {2, OperandInfo44}, // Inst #2304 = POP + {2, OperandInfo167}, // Inst #2305 = PRECEQU_PH_QBL + {2, OperandInfo167}, // Inst #2306 = PRECEQU_PH_QBLA + {2, OperandInfo167}, // Inst #2307 = PRECEQU_PH_QBLA_MM + {2, OperandInfo167}, // Inst #2308 = PRECEQU_PH_QBL_MM + {2, OperandInfo167}, // Inst #2309 = PRECEQU_PH_QBR + {2, OperandInfo167}, // Inst #2310 = PRECEQU_PH_QBRA + {2, OperandInfo167}, // Inst #2311 = PRECEQU_PH_QBRA_MM + {2, OperandInfo167}, // Inst #2312 = PRECEQU_PH_QBR_MM + {2, OperandInfo336}, // Inst #2313 = PRECEQ_W_PHL + {2, OperandInfo336}, // Inst #2314 = PRECEQ_W_PHL_MM + {2, OperandInfo336}, // Inst #2315 = PRECEQ_W_PHR + {2, OperandInfo336}, // Inst #2316 = PRECEQ_W_PHR_MM + {2, OperandInfo167}, // Inst #2317 = PRECEU_PH_QBL + {2, OperandInfo167}, // Inst #2318 = PRECEU_PH_QBLA + {2, OperandInfo167}, // Inst #2319 = PRECEU_PH_QBLA_MM + {2, OperandInfo167}, // Inst #2320 = PRECEU_PH_QBL_MM + {2, OperandInfo167}, // Inst #2321 = PRECEU_PH_QBR + {2, OperandInfo167}, // Inst #2322 = PRECEU_PH_QBRA + {2, OperandInfo167}, // Inst #2323 = PRECEU_PH_QBRA_MM + {2, OperandInfo167}, // Inst #2324 = PRECEU_PH_QBR_MM + {3, OperandInfo171}, // Inst #2325 = PRECRQU_S_QB_PH + {3, OperandInfo171}, // Inst #2326 = PRECRQU_S_QB_PH_MM + {3, OperandInfo337}, // Inst #2327 = PRECRQ_PH_W + {3, OperandInfo337}, // Inst #2328 = PRECRQ_PH_W_MM + {3, OperandInfo171}, // Inst #2329 = PRECRQ_QB_PH + {3, OperandInfo171}, // Inst #2330 = PRECRQ_QB_PH_MM + {3, OperandInfo337}, // Inst #2331 = PRECRQ_RS_PH_W + {3, OperandInfo337}, // Inst #2332 = PRECRQ_RS_PH_W_MM + {3, OperandInfo171}, // Inst #2333 = PRECR_QB_PH + {3, OperandInfo171}, // Inst #2334 = PRECR_QB_PH_MMR2 + {4, OperandInfo338}, // Inst #2335 = PRECR_SRA_PH_W + {4, OperandInfo338}, // Inst #2336 = PRECR_SRA_PH_W_MMR2 + {4, OperandInfo338}, // Inst #2337 = PRECR_SRA_R_PH_W + {4, OperandInfo338}, // Inst #2338 = PRECR_SRA_R_PH_W_MMR2 + {3, OperandInfo201}, // Inst #2339 = PREF + {3, OperandInfo201}, // Inst #2340 = PREFE + {3, OperandInfo201}, // Inst #2341 = PREFE_MM + {3, OperandInfo339}, // Inst #2342 = PREFX_MM + {3, OperandInfo201}, // Inst #2343 = PREF_MM + {3, OperandInfo201}, // Inst #2344 = PREF_MMR6 + {3, OperandInfo201}, // Inst #2345 = PREF_R6 + {4, OperandInfo181}, // Inst #2346 = PREPEND + {4, OperandInfo181}, // Inst #2347 = PREPEND_MMR2 + {3, OperandInfo172}, // Inst #2348 = PUL_PS64 + {3, OperandInfo172}, // Inst #2349 = PUU_PS64 + {2, OperandInfo336}, // Inst #2350 = RADDU_W_QB + {2, OperandInfo336}, // Inst #2351 = RADDU_W_QB_MM + {2, OperandInfo113}, // Inst #2352 = RDDSP + {2, OperandInfo113}, // Inst #2353 = RDDSP_MM + {3, OperandInfo340}, // Inst #2354 = RDHWR + {3, OperandInfo341}, // Inst #2355 = RDHWR64 + {3, OperandInfo340}, // Inst #2356 = RDHWR_MM + {3, OperandInfo340}, // Inst #2357 = RDHWR_MMR6 + {2, OperandInfo44}, // Inst #2358 = RDPGPR_MMR6 + {2, OperandInfo247}, // Inst #2359 = RECIP_D32 + {2, OperandInfo247}, // Inst #2360 = RECIP_D32_MM + {2, OperandInfo202}, // Inst #2361 = RECIP_D64 + {2, OperandInfo202}, // Inst #2362 = RECIP_D64_MM + {2, OperandInfo206}, // Inst #2363 = RECIP_S + {2, OperandInfo206}, // Inst #2364 = RECIP_S_MM + {2, OperandInfo342}, // Inst #2365 = REPLV_PH + {2, OperandInfo342}, // Inst #2366 = REPLV_PH_MM + {2, OperandInfo342}, // Inst #2367 = REPLV_QB + {2, OperandInfo342}, // Inst #2368 = REPLV_QB_MM + {2, OperandInfo343}, // Inst #2369 = REPL_PH + {2, OperandInfo343}, // Inst #2370 = REPL_PH_MM + {2, OperandInfo343}, // Inst #2371 = REPL_QB + {2, OperandInfo343}, // Inst #2372 = REPL_QB_MM + {2, OperandInfo202}, // Inst #2373 = RINT_D + {2, OperandInfo202}, // Inst #2374 = RINT_D_MMR6 + {2, OperandInfo206}, // Inst #2375 = RINT_S + {2, OperandInfo206}, // Inst #2376 = RINT_S_MMR6 + {3, OperandInfo72}, // Inst #2377 = ROTR + {3, OperandInfo71}, // Inst #2378 = ROTRV + {3, OperandInfo71}, // Inst #2379 = ROTRV_MM + {3, OperandInfo72}, // Inst #2380 = ROTR_MM + {2, OperandInfo202}, // Inst #2381 = ROUND_L_D64 + {2, OperandInfo202}, // Inst #2382 = ROUND_L_D_MMR6 + {2, OperandInfo203}, // Inst #2383 = ROUND_L_S + {2, OperandInfo203}, // Inst #2384 = ROUND_L_S_MMR6 + {2, OperandInfo204}, // Inst #2385 = ROUND_W_D32 + {2, OperandInfo205}, // Inst #2386 = ROUND_W_D64 + {2, OperandInfo202}, // Inst #2387 = ROUND_W_D_MMR6 + {2, OperandInfo204}, // Inst #2388 = ROUND_W_MM + {2, OperandInfo206}, // Inst #2389 = ROUND_W_S + {2, OperandInfo206}, // Inst #2390 = ROUND_W_S_MM + {2, OperandInfo206}, // Inst #2391 = ROUND_W_S_MMR6 + {2, OperandInfo247}, // Inst #2392 = RSQRT_D32 + {2, OperandInfo247}, // Inst #2393 = RSQRT_D32_MM + {2, OperandInfo202}, // Inst #2394 = RSQRT_D64 + {2, OperandInfo202}, // Inst #2395 = RSQRT_D64_MM + {2, OperandInfo206}, // Inst #2396 = RSQRT_S + {2, OperandInfo206}, // Inst #2397 = RSQRT_S_MM + {0, NULL}, // Inst #2398 = Restore16 + {0, NULL}, // Inst #2399 = RestoreX16 + {2, OperandInfo121}, // Inst #2400 = SAA + {2, OperandInfo121}, // Inst #2401 = SAAD + {3, OperandInfo175}, // Inst #2402 = SAT_S_B + {3, OperandInfo176}, // Inst #2403 = SAT_S_D + {3, OperandInfo177}, // Inst #2404 = SAT_S_H + {3, OperandInfo178}, // Inst #2405 = SAT_S_W + {3, OperandInfo175}, // Inst #2406 = SAT_U_B + {3, OperandInfo176}, // Inst #2407 = SAT_U_D + {3, OperandInfo177}, // Inst #2408 = SAT_U_H + {3, OperandInfo178}, // Inst #2409 = SAT_U_W + {3, OperandInfo95}, // Inst #2410 = SB + {3, OperandInfo344}, // Inst #2411 = SB16_MM + {3, OperandInfo344}, // Inst #2412 = SB16_MMR6 + {3, OperandInfo112}, // Inst #2413 = SB64 + {3, OperandInfo95}, // Inst #2414 = SBE + {3, OperandInfo95}, // Inst #2415 = SBE_MM + {3, OperandInfo95}, // Inst #2416 = SB_MM + {3, OperandInfo95}, // Inst #2417 = SB_MMR6 + {4, OperandInfo345}, // Inst #2418 = SC + {4, OperandInfo345}, // Inst #2419 = SC64 + {4, OperandInfo346}, // Inst #2420 = SC64_R6 + {4, OperandInfo347}, // Inst #2421 = SCD + {4, OperandInfo348}, // Inst #2422 = SCD_R6 + {4, OperandInfo345}, // Inst #2423 = SCE + {4, OperandInfo345}, // Inst #2424 = SCE_MM + {4, OperandInfo345}, // Inst #2425 = SC_MM + {4, OperandInfo345}, // Inst #2426 = SC_MMR6 + {4, OperandInfo346}, // Inst #2427 = SC_R6 + {3, OperandInfo112}, // Inst #2428 = SD + {1, OperandInfo2}, // Inst #2429 = SDBBP + {1, OperandInfo2}, // Inst #2430 = SDBBP16_MM + {1, OperandInfo2}, // Inst #2431 = SDBBP16_MMR6 + {1, OperandInfo2}, // Inst #2432 = SDBBP_MM + {1, OperandInfo2}, // Inst #2433 = SDBBP_MMR6 + {1, OperandInfo2}, // Inst #2434 = SDBBP_R6 + {3, OperandInfo157}, // Inst #2435 = SDC1 + {3, OperandInfo274}, // Inst #2436 = SDC164 + {3, OperandInfo274}, // Inst #2437 = SDC1_D64_MMR6 + {3, OperandInfo157}, // Inst #2438 = SDC1_MM + {3, OperandInfo275}, // Inst #2439 = SDC2 + {3, OperandInfo276}, // Inst #2440 = SDC2_MMR6 + {3, OperandInfo275}, // Inst #2441 = SDC2_R6 + {3, OperandInfo277}, // Inst #2442 = SDC3 + {2, OperandInfo44}, // Inst #2443 = SDIV + {2, OperandInfo44}, // Inst #2444 = SDIV_MM + {3, OperandInfo112}, // Inst #2445 = SDL + {3, OperandInfo112}, // Inst #2446 = SDR + {3, OperandInfo283}, // Inst #2447 = SDXC1 + {3, OperandInfo284}, // Inst #2448 = SDXC164 + {2, OperandInfo44}, // Inst #2449 = SEB + {2, OperandInfo121}, // Inst #2450 = SEB64 + {2, OperandInfo44}, // Inst #2451 = SEB_MM + {2, OperandInfo44}, // Inst #2452 = SEH + {2, OperandInfo121}, // Inst #2453 = SEH64 + {2, OperandInfo44}, // Inst #2454 = SEH_MM + {3, OperandInfo71}, // Inst #2455 = SELEQZ + {3, OperandInfo70}, // Inst #2456 = SELEQZ64 + {3, OperandInfo172}, // Inst #2457 = SELEQZ_D + {3, OperandInfo172}, // Inst #2458 = SELEQZ_D_MMR6 + {3, OperandInfo71}, // Inst #2459 = SELEQZ_MMR6 + {3, OperandInfo249}, // Inst #2460 = SELEQZ_S + {3, OperandInfo249}, // Inst #2461 = SELEQZ_S_MMR6 + {3, OperandInfo71}, // Inst #2462 = SELNEZ + {3, OperandInfo70}, // Inst #2463 = SELNEZ64 + {3, OperandInfo172}, // Inst #2464 = SELNEZ_D + {3, OperandInfo172}, // Inst #2465 = SELNEZ_D_MMR6 + {3, OperandInfo71}, // Inst #2466 = SELNEZ_MMR6 + {3, OperandInfo249}, // Inst #2467 = SELNEZ_S + {3, OperandInfo249}, // Inst #2468 = SELNEZ_S_MMR6 + {4, OperandInfo301}, // Inst #2469 = SEL_D + {4, OperandInfo301}, // Inst #2470 = SEL_D_MMR6 + {4, OperandInfo349}, // Inst #2471 = SEL_S + {4, OperandInfo349}, // Inst #2472 = SEL_S_MMR6 + {3, OperandInfo70}, // Inst #2473 = SEQ + {3, OperandInfo69}, // Inst #2474 = SEQi + {3, OperandInfo95}, // Inst #2475 = SH + {3, OperandInfo344}, // Inst #2476 = SH16_MM + {3, OperandInfo344}, // Inst #2477 = SH16_MMR6 + {3, OperandInfo112}, // Inst #2478 = SH64 + {3, OperandInfo95}, // Inst #2479 = SHE + {3, OperandInfo95}, // Inst #2480 = SHE_MM + {3, OperandInfo175}, // Inst #2481 = SHF_B + {3, OperandInfo177}, // Inst #2482 = SHF_H + {3, OperandInfo178}, // Inst #2483 = SHF_W + {3, OperandInfo350}, // Inst #2484 = SHILO + {3, OperandInfo330}, // Inst #2485 = SHILOV + {3, OperandInfo330}, // Inst #2486 = SHILOV_MM + {3, OperandInfo350}, // Inst #2487 = SHILO_MM + {3, OperandInfo351}, // Inst #2488 = SHLLV_PH + {3, OperandInfo351}, // Inst #2489 = SHLLV_PH_MM + {3, OperandInfo351}, // Inst #2490 = SHLLV_QB + {3, OperandInfo351}, // Inst #2491 = SHLLV_QB_MM + {3, OperandInfo351}, // Inst #2492 = SHLLV_S_PH + {3, OperandInfo351}, // Inst #2493 = SHLLV_S_PH_MM + {3, OperandInfo71}, // Inst #2494 = SHLLV_S_W + {3, OperandInfo71}, // Inst #2495 = SHLLV_S_W_MM + {3, OperandInfo352}, // Inst #2496 = SHLL_PH + {3, OperandInfo352}, // Inst #2497 = SHLL_PH_MM + {3, OperandInfo352}, // Inst #2498 = SHLL_QB + {3, OperandInfo352}, // Inst #2499 = SHLL_QB_MM + {3, OperandInfo352}, // Inst #2500 = SHLL_S_PH + {3, OperandInfo352}, // Inst #2501 = SHLL_S_PH_MM + {3, OperandInfo72}, // Inst #2502 = SHLL_S_W + {3, OperandInfo72}, // Inst #2503 = SHLL_S_W_MM + {3, OperandInfo351}, // Inst #2504 = SHRAV_PH + {3, OperandInfo351}, // Inst #2505 = SHRAV_PH_MM + {3, OperandInfo351}, // Inst #2506 = SHRAV_QB + {3, OperandInfo351}, // Inst #2507 = SHRAV_QB_MMR2 + {3, OperandInfo351}, // Inst #2508 = SHRAV_R_PH + {3, OperandInfo351}, // Inst #2509 = SHRAV_R_PH_MM + {3, OperandInfo351}, // Inst #2510 = SHRAV_R_QB + {3, OperandInfo351}, // Inst #2511 = SHRAV_R_QB_MMR2 + {3, OperandInfo71}, // Inst #2512 = SHRAV_R_W + {3, OperandInfo71}, // Inst #2513 = SHRAV_R_W_MM + {3, OperandInfo352}, // Inst #2514 = SHRA_PH + {3, OperandInfo352}, // Inst #2515 = SHRA_PH_MM + {3, OperandInfo352}, // Inst #2516 = SHRA_QB + {3, OperandInfo352}, // Inst #2517 = SHRA_QB_MMR2 + {3, OperandInfo352}, // Inst #2518 = SHRA_R_PH + {3, OperandInfo352}, // Inst #2519 = SHRA_R_PH_MM + {3, OperandInfo352}, // Inst #2520 = SHRA_R_QB + {3, OperandInfo352}, // Inst #2521 = SHRA_R_QB_MMR2 + {3, OperandInfo72}, // Inst #2522 = SHRA_R_W + {3, OperandInfo72}, // Inst #2523 = SHRA_R_W_MM + {3, OperandInfo351}, // Inst #2524 = SHRLV_PH + {3, OperandInfo351}, // Inst #2525 = SHRLV_PH_MMR2 + {3, OperandInfo351}, // Inst #2526 = SHRLV_QB + {3, OperandInfo351}, // Inst #2527 = SHRLV_QB_MM + {3, OperandInfo352}, // Inst #2528 = SHRL_PH + {3, OperandInfo352}, // Inst #2529 = SHRL_PH_MMR2 + {3, OperandInfo352}, // Inst #2530 = SHRL_QB + {3, OperandInfo352}, // Inst #2531 = SHRL_QB_MM + {3, OperandInfo95}, // Inst #2532 = SH_MM + {3, OperandInfo95}, // Inst #2533 = SH_MMR6 + {1, OperandInfo2}, // Inst #2534 = SIGRIE + {1, OperandInfo2}, // Inst #2535 = SIGRIE_MMR6 + {4, OperandInfo191}, // Inst #2536 = SLDI_B + {4, OperandInfo192}, // Inst #2537 = SLDI_D + {4, OperandInfo193}, // Inst #2538 = SLDI_H + {4, OperandInfo194}, // Inst #2539 = SLDI_W + {4, OperandInfo353}, // Inst #2540 = SLD_B + {4, OperandInfo354}, // Inst #2541 = SLD_D + {4, OperandInfo355}, // Inst #2542 = SLD_H + {4, OperandInfo356}, // Inst #2543 = SLD_W + {3, OperandInfo72}, // Inst #2544 = SLL + {3, OperandInfo169}, // Inst #2545 = SLL16_MM + {3, OperandInfo169}, // Inst #2546 = SLL16_MMR6 + {2, OperandInfo244}, // Inst #2547 = SLL64_32 + {2, OperandInfo121}, // Inst #2548 = SLL64_64 + {3, OperandInfo175}, // Inst #2549 = SLLI_B + {3, OperandInfo176}, // Inst #2550 = SLLI_D + {3, OperandInfo177}, // Inst #2551 = SLLI_H + {3, OperandInfo178}, // Inst #2552 = SLLI_W + {3, OperandInfo71}, // Inst #2553 = SLLV + {3, OperandInfo71}, // Inst #2554 = SLLV_MM + {3, OperandInfo173}, // Inst #2555 = SLL_B + {3, OperandInfo45}, // Inst #2556 = SLL_D + {3, OperandInfo46}, // Inst #2557 = SLL_H + {3, OperandInfo72}, // Inst #2558 = SLL_MM + {3, OperandInfo72}, // Inst #2559 = SLL_MMR6 + {3, OperandInfo47}, // Inst #2560 = SLL_W + {3, OperandInfo71}, // Inst #2561 = SLT + {3, OperandInfo357}, // Inst #2562 = SLT64 + {3, OperandInfo71}, // Inst #2563 = SLT_MM + {3, OperandInfo72}, // Inst #2564 = SLTi + {3, OperandInfo358}, // Inst #2565 = SLTi64 + {3, OperandInfo72}, // Inst #2566 = SLTi_MM + {3, OperandInfo72}, // Inst #2567 = SLTiu + {3, OperandInfo358}, // Inst #2568 = SLTiu64 + {3, OperandInfo72}, // Inst #2569 = SLTiu_MM + {3, OperandInfo71}, // Inst #2570 = SLTu + {3, OperandInfo357}, // Inst #2571 = SLTu64 + {3, OperandInfo71}, // Inst #2572 = SLTu_MM + {3, OperandInfo70}, // Inst #2573 = SNE + {3, OperandInfo69}, // Inst #2574 = SNEi + {3, OperandInfo175}, // Inst #2575 = SPLATI_B + {3, OperandInfo176}, // Inst #2576 = SPLATI_D + {3, OperandInfo177}, // Inst #2577 = SPLATI_H + {3, OperandInfo178}, // Inst #2578 = SPLATI_W + {3, OperandInfo359}, // Inst #2579 = SPLAT_B + {3, OperandInfo360}, // Inst #2580 = SPLAT_D + {3, OperandInfo361}, // Inst #2581 = SPLAT_H + {3, OperandInfo362}, // Inst #2582 = SPLAT_W + {3, OperandInfo72}, // Inst #2583 = SRA + {3, OperandInfo175}, // Inst #2584 = SRAI_B + {3, OperandInfo176}, // Inst #2585 = SRAI_D + {3, OperandInfo177}, // Inst #2586 = SRAI_H + {3, OperandInfo178}, // Inst #2587 = SRAI_W + {3, OperandInfo175}, // Inst #2588 = SRARI_B + {3, OperandInfo176}, // Inst #2589 = SRARI_D + {3, OperandInfo177}, // Inst #2590 = SRARI_H + {3, OperandInfo178}, // Inst #2591 = SRARI_W + {3, OperandInfo173}, // Inst #2592 = SRAR_B + {3, OperandInfo45}, // Inst #2593 = SRAR_D + {3, OperandInfo46}, // Inst #2594 = SRAR_H + {3, OperandInfo47}, // Inst #2595 = SRAR_W + {3, OperandInfo71}, // Inst #2596 = SRAV + {3, OperandInfo71}, // Inst #2597 = SRAV_MM + {3, OperandInfo173}, // Inst #2598 = SRA_B + {3, OperandInfo45}, // Inst #2599 = SRA_D + {3, OperandInfo46}, // Inst #2600 = SRA_H + {3, OperandInfo72}, // Inst #2601 = SRA_MM + {3, OperandInfo47}, // Inst #2602 = SRA_W + {3, OperandInfo72}, // Inst #2603 = SRL + {3, OperandInfo169}, // Inst #2604 = SRL16_MM + {3, OperandInfo169}, // Inst #2605 = SRL16_MMR6 + {3, OperandInfo175}, // Inst #2606 = SRLI_B + {3, OperandInfo176}, // Inst #2607 = SRLI_D + {3, OperandInfo177}, // Inst #2608 = SRLI_H + {3, OperandInfo178}, // Inst #2609 = SRLI_W + {3, OperandInfo175}, // Inst #2610 = SRLRI_B + {3, OperandInfo176}, // Inst #2611 = SRLRI_D + {3, OperandInfo177}, // Inst #2612 = SRLRI_H + {3, OperandInfo178}, // Inst #2613 = SRLRI_W + {3, OperandInfo173}, // Inst #2614 = SRLR_B + {3, OperandInfo45}, // Inst #2615 = SRLR_D + {3, OperandInfo46}, // Inst #2616 = SRLR_H + {3, OperandInfo47}, // Inst #2617 = SRLR_W + {3, OperandInfo71}, // Inst #2618 = SRLV + {3, OperandInfo71}, // Inst #2619 = SRLV_MM + {3, OperandInfo173}, // Inst #2620 = SRL_B + {3, OperandInfo45}, // Inst #2621 = SRL_D + {3, OperandInfo46}, // Inst #2622 = SRL_H + {3, OperandInfo72}, // Inst #2623 = SRL_MM + {3, OperandInfo47}, // Inst #2624 = SRL_W + {0, NULL}, // Inst #2625 = SSNOP + {0, NULL}, // Inst #2626 = SSNOP_MM + {0, NULL}, // Inst #2627 = SSNOP_MMR6 + {3, OperandInfo285}, // Inst #2628 = ST_B + {3, OperandInfo286}, // Inst #2629 = ST_D + {3, OperandInfo287}, // Inst #2630 = ST_H + {3, OperandInfo288}, // Inst #2631 = ST_W + {3, OperandInfo71}, // Inst #2632 = SUB + {3, OperandInfo171}, // Inst #2633 = SUBQH_PH + {3, OperandInfo171}, // Inst #2634 = SUBQH_PH_MMR2 + {3, OperandInfo171}, // Inst #2635 = SUBQH_R_PH + {3, OperandInfo171}, // Inst #2636 = SUBQH_R_PH_MMR2 + {3, OperandInfo71}, // Inst #2637 = SUBQH_R_W + {3, OperandInfo71}, // Inst #2638 = SUBQH_R_W_MMR2 + {3, OperandInfo71}, // Inst #2639 = SUBQH_W + {3, OperandInfo71}, // Inst #2640 = SUBQH_W_MMR2 + {3, OperandInfo171}, // Inst #2641 = SUBQ_PH + {3, OperandInfo171}, // Inst #2642 = SUBQ_PH_MM + {3, OperandInfo171}, // Inst #2643 = SUBQ_S_PH + {3, OperandInfo171}, // Inst #2644 = SUBQ_S_PH_MM + {3, OperandInfo71}, // Inst #2645 = SUBQ_S_W + {3, OperandInfo71}, // Inst #2646 = SUBQ_S_W_MM + {3, OperandInfo173}, // Inst #2647 = SUBSUS_U_B + {3, OperandInfo45}, // Inst #2648 = SUBSUS_U_D + {3, OperandInfo46}, // Inst #2649 = SUBSUS_U_H + {3, OperandInfo47}, // Inst #2650 = SUBSUS_U_W + {3, OperandInfo173}, // Inst #2651 = SUBSUU_S_B + {3, OperandInfo45}, // Inst #2652 = SUBSUU_S_D + {3, OperandInfo46}, // Inst #2653 = SUBSUU_S_H + {3, OperandInfo47}, // Inst #2654 = SUBSUU_S_W + {3, OperandInfo173}, // Inst #2655 = SUBS_S_B + {3, OperandInfo45}, // Inst #2656 = SUBS_S_D + {3, OperandInfo46}, // Inst #2657 = SUBS_S_H + {3, OperandInfo47}, // Inst #2658 = SUBS_S_W + {3, OperandInfo173}, // Inst #2659 = SUBS_U_B + {3, OperandInfo45}, // Inst #2660 = SUBS_U_D + {3, OperandInfo46}, // Inst #2661 = SUBS_U_H + {3, OperandInfo47}, // Inst #2662 = SUBS_U_W + {3, OperandInfo174}, // Inst #2663 = SUBU16_MM + {3, OperandInfo174}, // Inst #2664 = SUBU16_MMR6 + {3, OperandInfo171}, // Inst #2665 = SUBUH_QB + {3, OperandInfo171}, // Inst #2666 = SUBUH_QB_MMR2 + {3, OperandInfo171}, // Inst #2667 = SUBUH_R_QB + {3, OperandInfo171}, // Inst #2668 = SUBUH_R_QB_MMR2 + {3, OperandInfo71}, // Inst #2669 = SUBU_MMR6 + {3, OperandInfo171}, // Inst #2670 = SUBU_PH + {3, OperandInfo171}, // Inst #2671 = SUBU_PH_MMR2 + {3, OperandInfo171}, // Inst #2672 = SUBU_QB + {3, OperandInfo171}, // Inst #2673 = SUBU_QB_MM + {3, OperandInfo171}, // Inst #2674 = SUBU_S_PH + {3, OperandInfo171}, // Inst #2675 = SUBU_S_PH_MMR2 + {3, OperandInfo171}, // Inst #2676 = SUBU_S_QB + {3, OperandInfo171}, // Inst #2677 = SUBU_S_QB_MM + {3, OperandInfo175}, // Inst #2678 = SUBVI_B + {3, OperandInfo176}, // Inst #2679 = SUBVI_D + {3, OperandInfo177}, // Inst #2680 = SUBVI_H + {3, OperandInfo178}, // Inst #2681 = SUBVI_W + {3, OperandInfo173}, // Inst #2682 = SUBV_B + {3, OperandInfo45}, // Inst #2683 = SUBV_D + {3, OperandInfo46}, // Inst #2684 = SUBV_H + {3, OperandInfo47}, // Inst #2685 = SUBV_W + {3, OperandInfo71}, // Inst #2686 = SUB_MM + {3, OperandInfo71}, // Inst #2687 = SUB_MMR6 + {3, OperandInfo71}, // Inst #2688 = SUBu + {3, OperandInfo71}, // Inst #2689 = SUBu_MM + {3, OperandInfo283}, // Inst #2690 = SUXC1 + {3, OperandInfo284}, // Inst #2691 = SUXC164 + {3, OperandInfo284}, // Inst #2692 = SUXC1_MM + {3, OperandInfo95}, // Inst #2693 = SW + {3, OperandInfo344}, // Inst #2694 = SW16_MM + {3, OperandInfo344}, // Inst #2695 = SW16_MMR6 + {3, OperandInfo112}, // Inst #2696 = SW64 + {3, OperandInfo291}, // Inst #2697 = SWC1 + {3, OperandInfo291}, // Inst #2698 = SWC1_MM + {3, OperandInfo275}, // Inst #2699 = SWC2 + {3, OperandInfo276}, // Inst #2700 = SWC2_MMR6 + {3, OperandInfo275}, // Inst #2701 = SWC2_R6 + {3, OperandInfo277}, // Inst #2702 = SWC3 + {3, OperandInfo292}, // Inst #2703 = SWDSP + {3, OperandInfo292}, // Inst #2704 = SWDSP_MM + {3, OperandInfo95}, // Inst #2705 = SWE + {3, OperandInfo95}, // Inst #2706 = SWE_MM + {3, OperandInfo95}, // Inst #2707 = SWL + {3, OperandInfo112}, // Inst #2708 = SWL64 + {3, OperandInfo95}, // Inst #2709 = SWLE + {3, OperandInfo95}, // Inst #2710 = SWLE_MM + {3, OperandInfo95}, // Inst #2711 = SWL_MM + {3, OperandInfo295}, // Inst #2712 = SWM16_MM + {3, OperandInfo295}, // Inst #2713 = SWM16_MMR6 + {3, OperandInfo109}, // Inst #2714 = SWM32_MM + {4, OperandInfo296}, // Inst #2715 = SWP_MM + {3, OperandInfo95}, // Inst #2716 = SWR + {3, OperandInfo112}, // Inst #2717 = SWR64 + {3, OperandInfo95}, // Inst #2718 = SWRE + {3, OperandInfo95}, // Inst #2719 = SWRE_MM + {3, OperandInfo95}, // Inst #2720 = SWR_MM + {3, OperandInfo297}, // Inst #2721 = SWSP_MM + {3, OperandInfo297}, // Inst #2722 = SWSP_MMR6 + {3, OperandInfo298}, // Inst #2723 = SWXC1 + {3, OperandInfo298}, // Inst #2724 = SWXC1_MM + {3, OperandInfo95}, // Inst #2725 = SW_MM + {3, OperandInfo95}, // Inst #2726 = SW_MMR6 + {1, OperandInfo2}, // Inst #2727 = SYNC + {2, OperandInfo363}, // Inst #2728 = SYNCI + {2, OperandInfo363}, // Inst #2729 = SYNCI_MM + {2, OperandInfo363}, // Inst #2730 = SYNCI_MMR6 + {1, OperandInfo2}, // Inst #2731 = SYNC_MM + {1, OperandInfo2}, // Inst #2732 = SYNC_MMR6 + {1, OperandInfo2}, // Inst #2733 = SYSCALL + {1, OperandInfo2}, // Inst #2734 = SYSCALL_MM + {0, NULL}, // Inst #2735 = Save16 + {0, NULL}, // Inst #2736 = SaveX16 + {3, OperandInfo299}, // Inst #2737 = SbRxRyOffMemX16 + {2, OperandInfo364}, // Inst #2738 = SebRx16 + {2, OperandInfo364}, // Inst #2739 = SehRx16 + {3, OperandInfo299}, // Inst #2740 = ShRxRyOffMemX16 + {3, OperandInfo166}, // Inst #2741 = SllX16 + {3, OperandInfo185}, // Inst #2742 = SllvRxRy16 + {2, OperandInfo129}, // Inst #2743 = SltRxRy16 + {2, OperandInfo182}, // Inst #2744 = SltiRxImm16 + {2, OperandInfo182}, // Inst #2745 = SltiRxImmX16 + {2, OperandInfo182}, // Inst #2746 = SltiuRxImm16 + {2, OperandInfo182}, // Inst #2747 = SltiuRxImmX16 + {2, OperandInfo129}, // Inst #2748 = SltuRxRy16 + {3, OperandInfo166}, // Inst #2749 = SraX16 + {3, OperandInfo185}, // Inst #2750 = SravRxRy16 + {3, OperandInfo166}, // Inst #2751 = SrlX16 + {3, OperandInfo185}, // Inst #2752 = SrlvRxRy16 + {3, OperandInfo130}, // Inst #2753 = SubuRxRyRz16 + {3, OperandInfo299}, // Inst #2754 = SwRxRyOffMemX16 + {3, OperandInfo184}, // Inst #2755 = SwRxSpImmX16 + {3, OperandInfo72}, // Inst #2756 = TEQ + {2, OperandInfo113}, // Inst #2757 = TEQI + {2, OperandInfo113}, // Inst #2758 = TEQI_MM + {3, OperandInfo72}, // Inst #2759 = TEQ_MM + {3, OperandInfo72}, // Inst #2760 = TGE + {2, OperandInfo113}, // Inst #2761 = TGEI + {2, OperandInfo113}, // Inst #2762 = TGEIU + {2, OperandInfo113}, // Inst #2763 = TGEIU_MM + {2, OperandInfo113}, // Inst #2764 = TGEI_MM + {3, OperandInfo72}, // Inst #2765 = TGEU + {3, OperandInfo72}, // Inst #2766 = TGEU_MM + {3, OperandInfo72}, // Inst #2767 = TGE_MM + {0, NULL}, // Inst #2768 = TLBGINV + {0, NULL}, // Inst #2769 = TLBGINVF + {0, NULL}, // Inst #2770 = TLBGINVF_MM + {0, NULL}, // Inst #2771 = TLBGINV_MM + {0, NULL}, // Inst #2772 = TLBGP + {0, NULL}, // Inst #2773 = TLBGP_MM + {0, NULL}, // Inst #2774 = TLBGR + {0, NULL}, // Inst #2775 = TLBGR_MM + {0, NULL}, // Inst #2776 = TLBGWI + {0, NULL}, // Inst #2777 = TLBGWI_MM + {0, NULL}, // Inst #2778 = TLBGWR + {0, NULL}, // Inst #2779 = TLBGWR_MM + {0, NULL}, // Inst #2780 = TLBINV + {0, NULL}, // Inst #2781 = TLBINVF + {0, NULL}, // Inst #2782 = TLBINVF_MMR6 + {0, NULL}, // Inst #2783 = TLBINV_MMR6 + {0, NULL}, // Inst #2784 = TLBP + {0, NULL}, // Inst #2785 = TLBP_MM + {0, NULL}, // Inst #2786 = TLBR + {0, NULL}, // Inst #2787 = TLBR_MM + {0, NULL}, // Inst #2788 = TLBWI + {0, NULL}, // Inst #2789 = TLBWI_MM + {0, NULL}, // Inst #2790 = TLBWR + {0, NULL}, // Inst #2791 = TLBWR_MM + {3, OperandInfo72}, // Inst #2792 = TLT + {2, OperandInfo113}, // Inst #2793 = TLTI + {2, OperandInfo113}, // Inst #2794 = TLTIU_MM + {2, OperandInfo113}, // Inst #2795 = TLTI_MM + {3, OperandInfo72}, // Inst #2796 = TLTU + {3, OperandInfo72}, // Inst #2797 = TLTU_MM + {3, OperandInfo72}, // Inst #2798 = TLT_MM + {3, OperandInfo72}, // Inst #2799 = TNE + {2, OperandInfo113}, // Inst #2800 = TNEI + {2, OperandInfo113}, // Inst #2801 = TNEI_MM + {3, OperandInfo72}, // Inst #2802 = TNE_MM + {2, OperandInfo202}, // Inst #2803 = TRUNC_L_D64 + {2, OperandInfo202}, // Inst #2804 = TRUNC_L_D_MMR6 + {2, OperandInfo203}, // Inst #2805 = TRUNC_L_S + {2, OperandInfo203}, // Inst #2806 = TRUNC_L_S_MMR6 + {2, OperandInfo204}, // Inst #2807 = TRUNC_W_D32 + {2, OperandInfo205}, // Inst #2808 = TRUNC_W_D64 + {2, OperandInfo205}, // Inst #2809 = TRUNC_W_D_MMR6 + {2, OperandInfo204}, // Inst #2810 = TRUNC_W_MM + {2, OperandInfo206}, // Inst #2811 = TRUNC_W_S + {2, OperandInfo206}, // Inst #2812 = TRUNC_W_S_MM + {2, OperandInfo206}, // Inst #2813 = TRUNC_W_S_MMR6 + {2, OperandInfo113}, // Inst #2814 = TTLTIU + {2, OperandInfo44}, // Inst #2815 = UDIV + {2, OperandInfo44}, // Inst #2816 = UDIV_MM + {3, OperandInfo70}, // Inst #2817 = V3MULU + {3, OperandInfo70}, // Inst #2818 = VMM0 + {3, OperandInfo70}, // Inst #2819 = VMULU + {4, OperandInfo195}, // Inst #2820 = VSHF_B + {4, OperandInfo58}, // Inst #2821 = VSHF_D + {4, OperandInfo60}, // Inst #2822 = VSHF_H + {4, OperandInfo59}, // Inst #2823 = VSHF_W + {0, NULL}, // Inst #2824 = WAIT + {1, OperandInfo2}, // Inst #2825 = WAIT_MM + {1, OperandInfo2}, // Inst #2826 = WAIT_MMR6 + {2, OperandInfo113}, // Inst #2827 = WRDSP + {2, OperandInfo113}, // Inst #2828 = WRDSP_MM + {2, OperandInfo44}, // Inst #2829 = WRPGPR_MMR6 + {2, OperandInfo44}, // Inst #2830 = WSBH + {2, OperandInfo44}, // Inst #2831 = WSBH_MM + {2, OperandInfo44}, // Inst #2832 = WSBH_MMR6 + {3, OperandInfo71}, // Inst #2833 = XOR + {3, OperandInfo180}, // Inst #2834 = XOR16_MM + {3, OperandInfo180}, // Inst #2835 = XOR16_MMR6 + {3, OperandInfo70}, // Inst #2836 = XOR64 + {3, OperandInfo175}, // Inst #2837 = XORI_B + {3, OperandInfo72}, // Inst #2838 = XORI_MMR6 + {3, OperandInfo71}, // Inst #2839 = XOR_MM + {3, OperandInfo71}, // Inst #2840 = XOR_MMR6 + {3, OperandInfo173}, // Inst #2841 = XOR_V + {3, OperandInfo72}, // Inst #2842 = XORi + {3, OperandInfo69}, // Inst #2843 = XORi64 + {3, OperandInfo72}, // Inst #2844 = XORi_MM + {3, OperandInfo185}, // Inst #2845 = XorRxRxRy16 + {2, OperandInfo44}, // Inst #2846 = YIELD +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +extern const char MipsInstrNameData[] = { + /* 0 */ "G_FLOG10\0" + /* 9 */ "DMFC0\0" + /* 15 */ "DMFGC0\0" + /* 22 */ "MFHGC0\0" + /* 29 */ "MTHGC0\0" + /* 36 */ "DMTGC0\0" + /* 43 */ "MFTC0\0" + /* 49 */ "DMTC0\0" + /* 55 */ "MTTC0\0" + /* 61 */ "VMM0\0" + /* 66 */ "MTM0\0" + /* 71 */ "MTP0\0" + /* 76 */ "BBIT0\0" + /* 82 */ "LDC1\0" + /* 87 */ "SDC1\0" + /* 92 */ "CFC1\0" + /* 97 */ "DMFC1\0" + /* 103 */ "MFTHC1\0" + /* 110 */ "MTTHC1\0" + /* 117 */ "CTC1\0" + /* 122 */ "CFTC1\0" + /* 128 */ "MFTC1\0" + /* 134 */ "DMTC1\0" + /* 140 */ "CTTC1\0" + /* 146 */ "MTTC1\0" + /* 152 */ "LWC1\0" + /* 157 */ "SWC1\0" + /* 162 */ "LDXC1\0" + /* 168 */ "SDXC1\0" + /* 174 */ "LUXC1\0" + /* 180 */ "SUXC1\0" + /* 186 */ "LWXC1\0" + /* 192 */ "SWXC1\0" + /* 198 */ "MTM1\0" + /* 203 */ "SDC1_M1\0" + /* 211 */ "MTP1\0" + /* 216 */ "BBIT1\0" + /* 222 */ "BBIT032\0" + /* 230 */ "BBIT132\0" + /* 238 */ "DSRA32\0" + /* 245 */ "MFHC1_D32\0" + /* 255 */ "MTHC1_D32\0" + /* 265 */ "FSUB_D32\0" + /* 274 */ "NMSUB_D32\0" + /* 284 */ "FADD_D32\0" + /* 293 */ "NMADD_D32\0" + /* 303 */ "C_NGE_D32\0" + /* 313 */ "C_NGLE_D32\0" + /* 324 */ "C_OLE_D32\0" + /* 334 */ "C_ULE_D32\0" + /* 344 */ "C_LE_D32\0" + /* 353 */ "C_SF_D32\0" + /* 362 */ "MOVF_D32\0" + /* 371 */ "C_F_D32\0" + /* 379 */ "PseudoSELECTFP_F_D32\0" + /* 400 */ "FNEG_D32\0" + /* 409 */ "MOVN_I_D32\0" + /* 420 */ "MOVZ_I_D32\0" + /* 431 */ "C_NGL_D32\0" + /* 441 */ "FMUL_D32\0" + /* 450 */ "C_UN_D32\0" + /* 459 */ "RECIP_D32\0" + /* 469 */ "FCMP_D32\0" + /* 478 */ "C_SEQ_D32\0" + /* 488 */ "C_UEQ_D32\0" + /* 498 */ "C_EQ_D32\0" + /* 507 */ "FABS_D32\0" + /* 516 */ "CVT_S_D32\0" + /* 526 */ "PseudoSELECT_D32\0" + /* 543 */ "C_NGT_D32\0" + /* 553 */ "C_OLT_D32\0" + /* 563 */ "C_ULT_D32\0" + /* 573 */ "C_LT_D32\0" + /* 582 */ "FSQRT_D32\0" + /* 592 */ "RSQRT_D32\0" + /* 602 */ "MOVT_D32\0" + /* 611 */ "PseudoSELECTFP_T_D32\0" + /* 632 */ "FDIV_D32\0" + /* 641 */ "FMOV_D32\0" + /* 650 */ "PseudoTRUNC_W_D32\0" + /* 668 */ "ROUND_W_D32\0" + /* 680 */ "CEIL_W_D32\0" + /* 691 */ "FLOOR_W_D32\0" + /* 703 */ "CVT_W_D32\0" + /* 713 */ "BPOSGE32\0" + /* 722 */ "ATOMIC_LOAD_SUB_I32\0" + /* 742 */ "ATOMIC_LOAD_ADD_I32\0" + /* 762 */ "ATOMIC_LOAD_NAND_I32\0" + /* 783 */ "ATOMIC_LOAD_AND_I32\0" + /* 803 */ "ATOMIC_LOAD_UMIN_I32\0" + /* 824 */ "ATOMIC_LOAD_MIN_I32\0" + /* 844 */ "ATOMIC_SWAP_I32\0" + /* 860 */ "ATOMIC_CMP_SWAP_I32\0" + /* 880 */ "ATOMIC_LOAD_XOR_I32\0" + /* 900 */ "ATOMIC_LOAD_OR_I32\0" + /* 919 */ "ATOMIC_LOAD_UMAX_I32\0" + /* 940 */ "ATOMIC_LOAD_MAX_I32\0" + /* 960 */ "DSLL32\0" + /* 967 */ "DSRL32\0" + /* 974 */ "DROTR32\0" + /* 982 */ "CINS32\0" + /* 989 */ "EXTS32\0" + /* 996 */ "FCMP_S32\0" + /* 1005 */ "DSLL64_32\0" + /* 1015 */ "CINS64_32\0" + /* 1025 */ "DEXT64_32\0" + /* 1035 */ "LoadImmDoubleFGR_32\0" + /* 1055 */ "LoadAddrReg32\0" + /* 1069 */ "CINS_i32\0" + /* 1078 */ "LoadImm32\0" + /* 1088 */ "LoadAddrImm32\0" + /* 1102 */ "MIPSeh_return32\0" + /* 1118 */ "LwConstant32\0" + /* 1131 */ "LDC2\0" + /* 1136 */ "SDC2\0" + /* 1141 */ "DMFC2\0" + /* 1147 */ "DMTC2\0" + /* 1153 */ "LWC2\0" + /* 1158 */ "SWC2\0" + /* 1163 */ "G_FLOG2\0" + /* 1171 */ "MTM2\0" + /* 1176 */ "MTP2\0" + /* 1181 */ "G_FEXP2\0" + /* 1189 */ "SHRA_QB_MMR2\0" + /* 1202 */ "CMPGDU_LE_QB_MMR2\0" + /* 1220 */ "SUBUH_QB_MMR2\0" + /* 1234 */ "ADDUH_QB_MMR2\0" + /* 1248 */ "CMPGDU_EQ_QB_MMR2\0" + /* 1266 */ "SHRA_R_QB_MMR2\0" + /* 1281 */ "SUBUH_R_QB_MMR2\0" + /* 1297 */ "ADDUH_R_QB_MMR2\0" + /* 1313 */ "SHRAV_R_QB_MMR2\0" + /* 1329 */ "ABSQ_S_QB_MMR2\0" + /* 1344 */ "CMPGDU_LT_QB_MMR2\0" + /* 1362 */ "SHRAV_QB_MMR2\0" + /* 1376 */ "PREPEND_MMR2\0" + /* 1389 */ "APPEND_MMR2\0" + /* 1401 */ "PRECR_QB_PH_MMR2\0" + /* 1418 */ "SUBQH_PH_MMR2\0" + /* 1432 */ "ADDQH_PH_MMR2\0" + /* 1446 */ "SHRL_PH_MMR2\0" + /* 1459 */ "MUL_PH_MMR2\0" + /* 1471 */ "SUBQH_R_PH_MMR2\0" + /* 1487 */ "ADDQH_R_PH_MMR2\0" + /* 1503 */ "MUL_S_PH_MMR2\0" + /* 1517 */ "MULQ_S_PH_MMR2\0" + /* 1532 */ "SUBU_S_PH_MMR2\0" + /* 1547 */ "ADDU_S_PH_MMR2\0" + /* 1562 */ "SUBU_PH_MMR2\0" + /* 1575 */ "ADDU_PH_MMR2\0" + /* 1588 */ "SHRLV_PH_MMR2\0" + /* 1602 */ "DPA_W_PH_MMR2\0" + /* 1616 */ "MULSA_W_PH_MMR2\0" + /* 1632 */ "DPAQX_SA_W_PH_MMR2\0" + /* 1651 */ "DPSQX_SA_W_PH_MMR2\0" + /* 1670 */ "DPS_W_PH_MMR2\0" + /* 1684 */ "DPAQX_S_W_PH_MMR2\0" + /* 1702 */ "DPSQX_S_W_PH_MMR2\0" + /* 1720 */ "DPAX_W_PH_MMR2\0" + /* 1735 */ "DPSX_W_PH_MMR2\0" + /* 1750 */ "BALIGN_MMR2\0" + /* 1762 */ "PRECR_SRA_PH_W_MMR2\0" + /* 1782 */ "PRECR_SRA_R_PH_W_MMR2\0" + /* 1804 */ "SUBQH_W_MMR2\0" + /* 1817 */ "ADDQH_W_MMR2\0" + /* 1830 */ "SUBQH_R_W_MMR2\0" + /* 1845 */ "ADDQH_R_W_MMR2\0" + /* 1860 */ "MULQ_RS_W_MMR2\0" + /* 1875 */ "MULQ_S_W_MMR2\0" + /* 1889 */ "LDC3\0" + /* 1894 */ "SDC3\0" + /* 1899 */ "LWC3\0" + /* 1904 */ "SWC3\0" + /* 1909 */ "BPOSGE32C_MMR3\0" + /* 1924 */ "LDC164\0" + /* 1931 */ "SDC164\0" + /* 1938 */ "LDXC164\0" + /* 1946 */ "SDXC164\0" + /* 1954 */ "LUXC164\0" + /* 1962 */ "SUXC164\0" + /* 1970 */ "SEB64\0" + /* 1976 */ "TAILCALLREGHB64\0" + /* 1992 */ "JR_HB64\0" + /* 2000 */ "JALR_HB64\0" + /* 2010 */ "LB64\0" + /* 2015 */ "SB64\0" + /* 2020 */ "LOAD_ACC64\0" + /* 2031 */ "STORE_ACC64\0" + /* 2043 */ "BGEC64\0" + /* 2050 */ "BNEC64\0" + /* 2057 */ "JIC64\0" + /* 2063 */ "JIALC64\0" + /* 2071 */ "BEQC64\0" + /* 2078 */ "SC64\0" + /* 2083 */ "BLTC64\0" + /* 2090 */ "BGEUC64\0" + /* 2098 */ "BLTUC64\0" + /* 2106 */ "BGEZC64\0" + /* 2114 */ "BLEZC64\0" + /* 2122 */ "BNEZC64\0" + /* 2130 */ "BEQZC64\0" + /* 2138 */ "BGTZC64\0" + /* 2146 */ "BLTZC64\0" + /* 2154 */ "AND64\0" + /* 2160 */ "MFC1_D64\0" + /* 2169 */ "MFHC1_D64\0" + /* 2179 */ "MTHC1_D64\0" + /* 2189 */ "MTC1_D64\0" + /* 2198 */ "MOVN_I64_D64\0" + /* 2211 */ "MOVZ_I64_D64\0" + /* 2224 */ "FSUB_D64\0" + /* 2233 */ "NMSUB_D64\0" + /* 2243 */ "FADD_D64\0" + /* 2252 */ "NMADD_D64\0" + /* 2262 */ "C_NGE_D64\0" + /* 2272 */ "C_NGLE_D64\0" + /* 2283 */ "C_OLE_D64\0" + /* 2293 */ "C_ULE_D64\0" + /* 2303 */ "C_LE_D64\0" + /* 2312 */ "C_SF_D64\0" + /* 2321 */ "MOVF_D64\0" + /* 2330 */ "C_F_D64\0" + /* 2338 */ "PseudoSELECTFP_F_D64\0" + /* 2359 */ "FNEG_D64\0" + /* 2368 */ "MOVN_I_D64\0" + /* 2379 */ "MOVZ_I_D64\0" + /* 2390 */ "C_NGL_D64\0" + /* 2400 */ "FMUL_D64\0" + /* 2409 */ "TRUNC_L_D64\0" + /* 2421 */ "ROUND_L_D64\0" + /* 2433 */ "CEIL_L_D64\0" + /* 2444 */ "FLOOR_L_D64\0" + /* 2456 */ "CVT_L_D64\0" + /* 2466 */ "C_UN_D64\0" + /* 2475 */ "RECIP_D64\0" + /* 2485 */ "FCMP_D64\0" + /* 2494 */ "C_SEQ_D64\0" + /* 2504 */ "C_UEQ_D64\0" + /* 2514 */ "C_EQ_D64\0" + /* 2523 */ "FABS_D64\0" + /* 2532 */ "CVT_S_D64\0" + /* 2542 */ "PseudoSELECT_D64\0" + /* 2559 */ "C_NGT_D64\0" + /* 2569 */ "C_OLT_D64\0" + /* 2579 */ "C_ULT_D64\0" + /* 2589 */ "C_LT_D64\0" + /* 2598 */ "FSQRT_D64\0" + /* 2608 */ "RSQRT_D64\0" + /* 2618 */ "MOVT_D64\0" + /* 2627 */ "PseudoSELECTFP_T_D64\0" + /* 2648 */ "FDIV_D64\0" + /* 2657 */ "FMOV_D64\0" + /* 2666 */ "TRUNC_W_D64\0" + /* 2678 */ "ROUND_W_D64\0" + /* 2690 */ "CEIL_W_D64\0" + /* 2701 */ "FLOOR_W_D64\0" + /* 2713 */ "CVT_W_D64\0" + /* 2723 */ "BNE64\0" + /* 2729 */ "BuildPairF64\0" + /* 2742 */ "ExtractElementF64\0" + /* 2760 */ "TAILCALLREG64\0" + /* 2774 */ "SEH64\0" + /* 2780 */ "LH64\0" + /* 2785 */ "SH64\0" + /* 2790 */ "PseudoMFHI64\0" + /* 2803 */ "PseudoMTLOHI64\0" + /* 2818 */ "MTHI64\0" + /* 2825 */ "MOVN_I64_I64\0" + /* 2838 */ "MOVZ_I64_I64\0" + /* 2851 */ "ATOMIC_LOAD_SUB_I64\0" + /* 2871 */ "ATOMIC_LOAD_ADD_I64\0" + /* 2891 */ "ATOMIC_LOAD_NAND_I64\0" + /* 2912 */ "ATOMIC_LOAD_AND_I64\0" + /* 2932 */ "MOVF_I64\0" + /* 2941 */ "PseudoSELECTFP_F_I64\0" + /* 2962 */ "MOVN_I_I64\0" + /* 2973 */ "MOVZ_I_I64\0" + /* 2984 */ "ATOMIC_LOAD_UMIN_I64\0" + /* 3005 */ "ATOMIC_LOAD_MIN_I64\0" + /* 3025 */ "ATOMIC_SWAP_I64\0" + /* 3041 */ "ATOMIC_CMP_SWAP_I64\0" + /* 3061 */ "ATOMIC_LOAD_XOR_I64\0" + /* 3081 */ "ATOMIC_LOAD_OR_I64\0" + /* 3100 */ "PseudoD_SELECT_I64\0" + /* 3119 */ "PseudoSELECT_I64\0" + /* 3136 */ "MOVT_I64\0" + /* 3145 */ "PseudoSELECTFP_T_I64\0" + /* 3166 */ "ATOMIC_LOAD_UMAX_I64\0" + /* 3187 */ "ATOMIC_LOAD_MAX_I64\0" + /* 3207 */ "LL64\0" + /* 3212 */ "CVT_S_PL64\0" + /* 3223 */ "LWL64\0" + /* 3229 */ "SWL64\0" + /* 3235 */ "PseudoMFLO64\0" + /* 3248 */ "MTLO64\0" + /* 3255 */ "BEQ64\0" + /* 3261 */ "JR64\0" + /* 3266 */ "JALR64\0" + /* 3273 */ "NOR64\0" + /* 3279 */ "XOR64\0" + /* 3285 */ "RDHWR64\0" + /* 3293 */ "LWR64\0" + /* 3299 */ "SWR64\0" + /* 3305 */ "FSUB_PS64\0" + /* 3315 */ "FADD_PS64\0" + /* 3325 */ "PLL_PS64\0" + /* 3334 */ "FMUL_PS64\0" + /* 3344 */ "PUL_PS64\0" + /* 3353 */ "ADDR_PS64\0" + /* 3363 */ "MULR_PS64\0" + /* 3373 */ "PLU_PS64\0" + /* 3382 */ "PUU_PS64\0" + /* 3391 */ "CVT_PW_PS64\0" + /* 3403 */ "CVT_PS_S64\0" + /* 3414 */ "SLT64\0" + /* 3420 */ "CVT_S_PU64\0" + /* 3431 */ "LW64\0" + /* 3436 */ "CVT_PS_PW64\0" + /* 3448 */ "SW64\0" + /* 3453 */ "BGEZ64\0" + /* 3460 */ "BLEZ64\0" + /* 3467 */ "SELNEZ64\0" + /* 3476 */ "SELEQZ64\0" + /* 3485 */ "BGTZ64\0" + /* 3492 */ "BLTZ64\0" + /* 3499 */ "BuildPairF64_64\0" + /* 3515 */ "ExtractElementF64_64\0" + /* 3536 */ "SLL64_64\0" + /* 3545 */ "LONG_BRANCH_LUi2Op_64\0" + /* 3567 */ "LoadAddrReg64\0" + /* 3581 */ "PseudoIndirectHazardBranch64\0" + /* 3610 */ "PseudoIndirectBranch64\0" + /* 3633 */ "ANDi64\0" + /* 3640 */ "XORi64\0" + /* 3647 */ "SLTi64\0" + /* 3654 */ "LUi64\0" + /* 3660 */ "SGEImm64\0" + /* 3669 */ "SLEImm64\0" + /* 3678 */ "NORImm64\0" + /* 3687 */ "SGTImm64\0" + /* 3696 */ "SLTImm64\0" + /* 3705 */ "SGEUImm64\0" + /* 3715 */ "SLEUImm64\0" + /* 3725 */ "SGTUImm64\0" + /* 3735 */ "SLTUImm64\0" + /* 3745 */ "LoadImm64\0" + /* 3755 */ "LoadAddrImm64\0" + /* 3769 */ "PseudoReturn64\0" + /* 3784 */ "MIPSeh_return64\0" + /* 3800 */ "LBu64\0" + /* 3806 */ "LHu64\0" + /* 3812 */ "SLTu64\0" + /* 3819 */ "LEA_ADDiu64\0" + /* 3831 */ "SLTiu64\0" + /* 3839 */ "MoveR3216\0" + /* 3849 */ "RetRA16\0" + /* 3857 */ "JalB16\0" + /* 3864 */ "LD_F16\0" + /* 3871 */ "ST_F16\0" + /* 3878 */ "ATOMIC_LOAD_SUB_I16\0" + /* 3898 */ "ATOMIC_LOAD_ADD_I16\0" + /* 3918 */ "ATOMIC_LOAD_NAND_I16\0" + /* 3939 */ "ATOMIC_LOAD_AND_I16\0" + /* 3959 */ "ATOMIC_LOAD_UMIN_I16\0" + /* 3980 */ "ATOMIC_LOAD_MIN_I16\0" + /* 4000 */ "ATOMIC_SWAP_I16\0" + /* 4016 */ "ATOMIC_CMP_SWAP_I16\0" + /* 4036 */ "ATOMIC_LOAD_XOR_I16\0" + /* 4056 */ "ATOMIC_LOAD_OR_I16\0" + /* 4075 */ "ATOMIC_LOAD_UMAX_I16\0" + /* 4096 */ "ATOMIC_LOAD_MAX_I16\0" + /* 4116 */ "Move32R16\0" + /* 4126 */ "SraX16\0" + /* 4133 */ "RestoreX16\0" + /* 4144 */ "SaveX16\0" + /* 4152 */ "BtnezT8CmpiX16\0" + /* 4167 */ "BteqzT8CmpiX16\0" + /* 4182 */ "BtnezT8SltiX16\0" + /* 4197 */ "BteqzT8SltiX16\0" + /* 4212 */ "SllX16\0" + /* 4219 */ "SrlX16\0" + /* 4226 */ "LbRxRyOffMemX16\0" + /* 4242 */ "SbRxRyOffMemX16\0" + /* 4258 */ "LhRxRyOffMemX16\0" + /* 4274 */ "ShRxRyOffMemX16\0" + /* 4290 */ "LbuRxRyOffMemX16\0" + /* 4307 */ "LhuRxRyOffMemX16\0" + /* 4324 */ "AddiuRxRyOffMemX16\0" + /* 4343 */ "LwRxRyOffMemX16\0" + /* 4359 */ "SwRxRyOffMemX16\0" + /* 4375 */ "AddiuRxPcImmX16\0" + /* 4391 */ "AddiuSpImmX16\0" + /* 4405 */ "LwRxSpImmX16\0" + /* 4418 */ "SwRxSpImmX16\0" + /* 4431 */ "SltiCCRxImmX16\0" + /* 4446 */ "SltiuCCRxImmX16\0" + /* 4462 */ "LiRxImmX16\0" + /* 4473 */ "CmpiRxImmX16\0" + /* 4486 */ "SltiRxImmX16\0" + /* 4499 */ "AddiuRxImmX16\0" + /* 4513 */ "SltiuRxImmX16\0" + /* 4527 */ "AddiuRxRxImmX16\0" + /* 4543 */ "BnezRxImmX16\0" + /* 4556 */ "BeqzRxImmX16\0" + /* 4569 */ "BimmX16\0" + /* 4577 */ "LiRxImmAlignX16\0" + /* 4593 */ "LwRxPcTcpX16\0" + /* 4606 */ "BtnezT8CmpX16\0" + /* 4620 */ "BteqzT8CmpX16\0" + /* 4634 */ "BtnezT8SltX16\0" + /* 4648 */ "BteqzT8SltX16\0" + /* 4662 */ "BtnezT8SltiuX16\0" + /* 4678 */ "BteqzT8SltiuX16\0" + /* 4694 */ "BtnezT8SltuX16\0" + /* 4709 */ "BteqzT8SltuX16\0" + /* 4724 */ "BtnezX16\0" + /* 4733 */ "BteqzX16\0" + /* 4742 */ "JrcRa16\0" + /* 4750 */ "JrRa16\0" + /* 4757 */ "Restore16\0" + /* 4767 */ "GotPrologue16\0" + /* 4781 */ "Save16\0" + /* 4788 */ "JumpLinkReg16\0" + /* 4802 */ "Mfhi16\0" + /* 4809 */ "Break16\0" + /* 4817 */ "Jal16\0" + /* 4823 */ "AddiuSpImm16\0" + /* 4836 */ "LiRxImm16\0" + /* 4846 */ "CmpiRxImm16\0" + /* 4858 */ "SltiRxImm16\0" + /* 4870 */ "SltiuRxImm16\0" + /* 4883 */ "AddiuRxRxImm16\0" + /* 4898 */ "BnezRxImm16\0" + /* 4910 */ "BeqzRxImm16\0" + /* 4922 */ "Bimm16\0" + /* 4929 */ "Mflo16\0" + /* 4936 */ "LwRxPcTcp16\0" + /* 4948 */ "SebRx16\0" + /* 4956 */ "JrcRx16\0" + /* 4964 */ "SehRx16\0" + /* 4972 */ "SltCCRxRy16\0" + /* 4984 */ "SltuCCRxRy16\0" + /* 4997 */ "NegRxRy16\0" + /* 5007 */ "CmpRxRy16\0" + /* 5017 */ "SltRxRy16\0" + /* 5027 */ "MultRxRy16\0" + /* 5038 */ "NotRxRy16\0" + /* 5048 */ "SltuRxRy16\0" + /* 5059 */ "MultuRxRy16\0" + /* 5071 */ "DivuRxRy16\0" + /* 5082 */ "SravRxRy16\0" + /* 5093 */ "DivRxRy16\0" + /* 5103 */ "SllvRxRy16\0" + /* 5114 */ "SrlvRxRy16\0" + /* 5125 */ "AndRxRxRy16\0" + /* 5137 */ "OrRxRxRy16\0" + /* 5148 */ "XorRxRxRy16\0" + /* 5160 */ "MultRxRyRz16\0" + /* 5173 */ "SubuRxRyRz16\0" + /* 5186 */ "AdduRxRyRz16\0" + /* 5199 */ "SltuRxRyRz16\0" + /* 5212 */ "MultuRxRyRz16\0" + /* 5226 */ "Btnez16\0" + /* 5234 */ "Bteqz16\0" + /* 5242 */ "PseudoIndrectHazardBranch64R6\0" + /* 5272 */ "PseudoIndirectBranch64R6\0" + /* 5297 */ "MFC0_MMR6\0" + /* 5307 */ "MFHC0_MMR6\0" + /* 5318 */ "MTHC0_MMR6\0" + /* 5329 */ "MTC0_MMR6\0" + /* 5339 */ "MFC1_MMR6\0" + /* 5349 */ "MTC1_MMR6\0" + /* 5359 */ "LDC2_MMR6\0" + /* 5369 */ "SDC2_MMR6\0" + /* 5379 */ "MFC2_MMR6\0" + /* 5389 */ "MFHC2_MMR6\0" + /* 5400 */ "MTHC2_MMR6\0" + /* 5411 */ "MTC2_MMR6\0" + /* 5421 */ "LWC2_MMR6\0" + /* 5431 */ "SWC2_MMR6\0" + /* 5441 */ "LDC1_D64_MMR6\0" + /* 5455 */ "SDC1_D64_MMR6\0" + /* 5469 */ "SB16_MMR6\0" + /* 5479 */ "BC16_MMR6\0" + /* 5489 */ "JRC16_MMR6\0" + /* 5500 */ "JALRC16_MMR6\0" + /* 5513 */ "BNEZC16_MMR6\0" + /* 5526 */ "BEQZC16_MMR6\0" + /* 5539 */ "AND16_MMR6\0" + /* 5550 */ "MOVE16_MMR6\0" + /* 5562 */ "SH16_MMR6\0" + /* 5572 */ "ANDI16_MMR6\0" + /* 5584 */ "LI16_MMR6\0" + /* 5594 */ "BREAK16_MMR6\0" + /* 5607 */ "SLL16_MMR6\0" + /* 5618 */ "SRL16_MMR6\0" + /* 5629 */ "LWM16_MMR6\0" + /* 5640 */ "SWM16_MMR6\0" + /* 5651 */ "SDBBP16_MMR6\0" + /* 5664 */ "XOR16_MMR6\0" + /* 5675 */ "NOT16_MMR6\0" + /* 5686 */ "SUBU16_MMR6\0" + /* 5698 */ "ADDU16_MMR6\0" + /* 5710 */ "SW16_MMR6\0" + /* 5720 */ "LSA_MMR6\0" + /* 5729 */ "EHB_MMR6\0" + /* 5738 */ "JALRC_HB_MMR6\0" + /* 5752 */ "LB_MMR6\0" + /* 5760 */ "SB_MMR6\0" + /* 5768 */ "SUB_MMR6\0" + /* 5777 */ "BC_MMR6\0" + /* 5785 */ "BGEC_MMR6\0" + /* 5795 */ "BNEC_MMR6\0" + /* 5805 */ "JIC_MMR6\0" + /* 5814 */ "BALC_MMR6\0" + /* 5824 */ "JIALC_MMR6\0" + /* 5835 */ "BGEZALC_MMR6\0" + /* 5848 */ "BLEZALC_MMR6\0" + /* 5861 */ "BNEZALC_MMR6\0" + /* 5874 */ "BEQZALC_MMR6\0" + /* 5887 */ "BGTZALC_MMR6\0" + /* 5900 */ "BLTZALC_MMR6\0" + /* 5913 */ "ERETNC_MMR6\0" + /* 5925 */ "SYNC_MMR6\0" + /* 5935 */ "AUIPC_MMR6\0" + /* 5946 */ "ALUIPC_MMR6\0" + /* 5958 */ "ADDIUPC_MMR6\0" + /* 5971 */ "LWPC_MMR6\0" + /* 5981 */ "BEQC_MMR6\0" + /* 5991 */ "JALRC_MMR6\0" + /* 6002 */ "SC_MMR6\0" + /* 6010 */ "BLTC_MMR6\0" + /* 6020 */ "BGEUC_MMR6\0" + /* 6031 */ "BLTUC_MMR6\0" + /* 6042 */ "BNVC_MMR6\0" + /* 6052 */ "BOVC_MMR6\0" + /* 6062 */ "BGEZC_MMR6\0" + /* 6073 */ "BLEZC_MMR6\0" + /* 6084 */ "BC1NEZC_MMR6\0" + /* 6097 */ "BC2NEZC_MMR6\0" + /* 6110 */ "BNEZC_MMR6\0" + /* 6121 */ "BC1EQZC_MMR6\0" + /* 6134 */ "BC2EQZC_MMR6\0" + /* 6147 */ "BEQZC_MMR6\0" + /* 6158 */ "BGTZC_MMR6\0" + /* 6169 */ "BLTZC_MMR6\0" + /* 6180 */ "ADD_MMR6\0" + /* 6189 */ "AND_MMR6\0" + /* 6198 */ "MOD_MMR6\0" + /* 6207 */ "MINA_D_MMR6\0" + /* 6219 */ "MAXA_D_MMR6\0" + /* 6231 */ "CMP_SLE_D_MMR6\0" + /* 6246 */ "CMP_SULE_D_MMR6\0" + /* 6262 */ "CMP_ULE_D_MMR6\0" + /* 6277 */ "CMP_LE_D_MMR6\0" + /* 6291 */ "CMP_SAF_D_MMR6\0" + /* 6306 */ "CMP_AF_D_MMR6\0" + /* 6320 */ "MSUBF_D_MMR6\0" + /* 6333 */ "MADDF_D_MMR6\0" + /* 6346 */ "SEL_D_MMR6\0" + /* 6357 */ "TRUNC_L_D_MMR6\0" + /* 6372 */ "ROUND_L_D_MMR6\0" + /* 6387 */ "CEIL_L_D_MMR6\0" + /* 6401 */ "FLOOR_L_D_MMR6\0" + /* 6416 */ "CVT_L_D_MMR6\0" + /* 6429 */ "MIN_D_MMR6\0" + /* 6440 */ "CMP_SUN_D_MMR6\0" + /* 6455 */ "CMP_UN_D_MMR6\0" + /* 6469 */ "CMP_SEQ_D_MMR6\0" + /* 6484 */ "CMP_SUEQ_D_MMR6\0" + /* 6500 */ "CMP_UEQ_D_MMR6\0" + /* 6515 */ "CMP_EQ_D_MMR6\0" + /* 6529 */ "CLASS_D_MMR6\0" + /* 6542 */ "CMP_SLT_D_MMR6\0" + /* 6557 */ "CMP_SULT_D_MMR6\0" + /* 6573 */ "CMP_ULT_D_MMR6\0" + /* 6588 */ "CMP_LT_D_MMR6\0" + /* 6602 */ "RINT_D_MMR6\0" + /* 6614 */ "FMOV_D_MMR6\0" + /* 6626 */ "TRUNC_W_D_MMR6\0" + /* 6641 */ "ROUND_W_D_MMR6\0" + /* 6656 */ "CEIL_W_D_MMR6\0" + /* 6670 */ "FLOOR_W_D_MMR6\0" + /* 6685 */ "MAX_D_MMR6\0" + /* 6696 */ "SELNEZ_D_MMR6\0" + /* 6710 */ "SELEQZ_D_MMR6\0" + /* 6724 */ "CACHE_MMR6\0" + /* 6735 */ "SIGRIE_MMR6\0" + /* 6747 */ "PAUSE_MMR6\0" + /* 6758 */ "PREF_MMR6\0" + /* 6768 */ "TLBINVF_MMR6\0" + /* 6781 */ "TAILCALLREG_MMR6\0" + /* 6798 */ "WSBH_MMR6\0" + /* 6808 */ "SH_MMR6\0" + /* 6816 */ "MUH_MMR6\0" + /* 6825 */ "SYNCI_MMR6\0" + /* 6836 */ "ANDI_MMR6\0" + /* 6846 */ "EI_MMR6\0" + /* 6854 */ "XORI_MMR6\0" + /* 6864 */ "AUI_MMR6\0" + /* 6873 */ "LUI_MMR6\0" + /* 6882 */ "GINVI_MMR6\0" + /* 6893 */ "BREAK_MMR6\0" + /* 6904 */ "JAL_MMR6\0" + /* 6913 */ "TAILCALL_MMR6\0" + /* 6927 */ "SLL_MMR6\0" + /* 6936 */ "MUL_MMR6\0" + /* 6945 */ "CVT_D_L_MMR6\0" + /* 6958 */ "CVT_S_L_MMR6\0" + /* 6971 */ "ALIGN_MMR6\0" + /* 6982 */ "CLO_MMR6\0" + /* 6991 */ "BITSWAP_MMR6\0" + /* 7004 */ "SDBBP_MMR6\0" + /* 7015 */ "MOVEP_MMR6\0" + /* 7026 */ "SSNOP_MMR6\0" + /* 7037 */ "JRCADDIUSP_MMR6\0" + /* 7053 */ "SWSP_MMR6\0" + /* 7063 */ "DVP_MMR6\0" + /* 7072 */ "EVP_MMR6\0" + /* 7081 */ "NOR_MMR6\0" + /* 7090 */ "XOR_MMR6\0" + /* 7099 */ "RDPGPR_MMR6\0" + /* 7111 */ "WRPGPR_MMR6\0" + /* 7123 */ "RDHWR_MMR6\0" + /* 7134 */ "INS_MMR6\0" + /* 7143 */ "MINA_S_MMR6\0" + /* 7155 */ "MAXA_S_MMR6\0" + /* 7167 */ "FSUB_S_MMR6\0" + /* 7179 */ "FADD_S_MMR6\0" + /* 7191 */ "CMP_SLE_S_MMR6\0" + /* 7206 */ "CMP_SULE_S_MMR6\0" + /* 7222 */ "CMP_ULE_S_MMR6\0" + /* 7237 */ "CMP_LE_S_MMR6\0" + /* 7251 */ "CMP_SAF_S_MMR6\0" + /* 7266 */ "CMP_AF_S_MMR6\0" + /* 7280 */ "MSUBF_S_MMR6\0" + /* 7293 */ "MADDF_S_MMR6\0" + /* 7306 */ "FNEG_S_MMR6\0" + /* 7318 */ "SEL_S_MMR6\0" + /* 7329 */ "FMUL_S_MMR6\0" + /* 7341 */ "TRUNC_L_S_MMR6\0" + /* 7356 */ "ROUND_L_S_MMR6\0" + /* 7371 */ "CEIL_L_S_MMR6\0" + /* 7385 */ "FLOOR_L_S_MMR6\0" + /* 7400 */ "CVT_L_S_MMR6\0" + /* 7413 */ "MIN_S_MMR6\0" + /* 7424 */ "CMP_SUN_S_MMR6\0" + /* 7439 */ "CMP_UN_S_MMR6\0" + /* 7453 */ "CMP_SEQ_S_MMR6\0" + /* 7468 */ "CMP_SUEQ_S_MMR6\0" + /* 7484 */ "CMP_UEQ_S_MMR6\0" + /* 7499 */ "CMP_EQ_S_MMR6\0" + /* 7513 */ "CLASS_S_MMR6\0" + /* 7526 */ "CMP_SLT_S_MMR6\0" + /* 7541 */ "CMP_SULT_S_MMR6\0" + /* 7557 */ "CMP_ULT_S_MMR6\0" + /* 7572 */ "CMP_LT_S_MMR6\0" + /* 7586 */ "RINT_S_MMR6\0" + /* 7598 */ "FDIV_S_MMR6\0" + /* 7610 */ "FMOV_S_MMR6\0" + /* 7622 */ "TRUNC_W_S_MMR6\0" + /* 7637 */ "ROUND_W_S_MMR6\0" + /* 7652 */ "CEIL_W_S_MMR6\0" + /* 7666 */ "FLOOR_W_S_MMR6\0" + /* 7681 */ "CVT_W_S_MMR6\0" + /* 7694 */ "MAX_S_MMR6\0" + /* 7705 */ "SELNEZ_S_MMR6\0" + /* 7719 */ "SELEQZ_S_MMR6\0" + /* 7733 */ "DERET_MMR6\0" + /* 7744 */ "WAIT_MMR6\0" + /* 7754 */ "GINVT_MMR6\0" + /* 7765 */ "EXT_MMR6\0" + /* 7774 */ "LBU_MMR6\0" + /* 7783 */ "SUBU_MMR6\0" + /* 7793 */ "ADDU_MMR6\0" + /* 7803 */ "MODU_MMR6\0" + /* 7813 */ "MUHU_MMR6\0" + /* 7823 */ "ADDIU_MMR6\0" + /* 7834 */ "MULU_MMR6\0" + /* 7844 */ "DIVU_MMR6\0" + /* 7854 */ "DIV_MMR6\0" + /* 7863 */ "TLBINV_MMR6\0" + /* 7875 */ "LW_MMR6\0" + /* 7883 */ "SW_MMR6\0" + /* 7891 */ "CVT_S_W_MMR6\0" + /* 7904 */ "SELNEZ_MMR6\0" + /* 7916 */ "CLZ_MMR6\0" + /* 7925 */ "SELEQZ_MMR6\0" + /* 7937 */ "PseudoIndirectBranch_MMR6\0" + /* 7963 */ "LDC2_R6\0" + /* 7971 */ "SDC2_R6\0" + /* 7979 */ "LWC2_R6\0" + /* 7987 */ "SWC2_R6\0" + /* 7995 */ "JR_HB64_R6\0" + /* 8006 */ "SC64_R6\0" + /* 8014 */ "LL64_R6\0" + /* 8022 */ "DLSA_R6\0" + /* 8030 */ "JR_HB_R6\0" + /* 8039 */ "SC_R6\0" + /* 8045 */ "SCD_R6\0" + /* 8052 */ "LLD_R6\0" + /* 8059 */ "CACHE_R6\0" + /* 8068 */ "PREF_R6\0" + /* 8076 */ "LL_R6\0" + /* 8082 */ "DMUL_R6\0" + /* 8090 */ "DCLO_R6\0" + /* 8098 */ "SDBBP_R6\0" + /* 8107 */ "DCLZ_R6\0" + /* 8115 */ "PseudoIndrectHazardBranchR6\0" + /* 8143 */ "PseudoIndirectBranchR6\0" + /* 8166 */ "LOAD_ACC128\0" + /* 8178 */ "STORE_ACC128\0" + /* 8191 */ "ATOMIC_LOAD_SUB_I8\0" + /* 8210 */ "ATOMIC_LOAD_ADD_I8\0" + /* 8229 */ "ATOMIC_LOAD_NAND_I8\0" + /* 8249 */ "ATOMIC_LOAD_AND_I8\0" + /* 8268 */ "ATOMIC_LOAD_UMIN_I8\0" + /* 8288 */ "ATOMIC_LOAD_MIN_I8\0" + /* 8307 */ "ATOMIC_SWAP_I8\0" + /* 8322 */ "ATOMIC_CMP_SWAP_I8\0" + /* 8341 */ "ATOMIC_LOAD_XOR_I8\0" + /* 8360 */ "ATOMIC_LOAD_OR_I8\0" + /* 8378 */ "ATOMIC_LOAD_UMAX_I8\0" + /* 8398 */ "ATOMIC_LOAD_MAX_I8\0" + /* 8417 */ "SAA\0" + /* 8421 */ "PRECEU_PH_QBLA\0" + /* 8436 */ "PRECEQU_PH_QBLA\0" + /* 8452 */ "G_FMA\0" + /* 8458 */ "G_STRICT_FMA\0" + /* 8471 */ "PRECEU_PH_QBRA\0" + /* 8486 */ "PRECEQU_PH_QBRA\0" + /* 8502 */ "DSRA\0" + /* 8507 */ "ATOMIC_LOAD_SUB_I32_POSTRA\0" + /* 8534 */ "ATOMIC_LOAD_ADD_I32_POSTRA\0" + /* 8561 */ "ATOMIC_LOAD_NAND_I32_POSTRA\0" + /* 8589 */ "ATOMIC_LOAD_AND_I32_POSTRA\0" + /* 8616 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\0" + /* 8644 */ "ATOMIC_LOAD_MIN_I32_POSTRA\0" + /* 8671 */ "ATOMIC_SWAP_I32_POSTRA\0" + /* 8694 */ "ATOMIC_CMP_SWAP_I32_POSTRA\0" + /* 8721 */ "ATOMIC_LOAD_XOR_I32_POSTRA\0" + /* 8748 */ "ATOMIC_LOAD_OR_I32_POSTRA\0" + /* 8774 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\0" + /* 8802 */ "ATOMIC_LOAD_MAX_I32_POSTRA\0" + /* 8829 */ "ATOMIC_LOAD_SUB_I64_POSTRA\0" + /* 8856 */ "ATOMIC_LOAD_ADD_I64_POSTRA\0" + /* 8883 */ "ATOMIC_LOAD_NAND_I64_POSTRA\0" + /* 8911 */ "ATOMIC_LOAD_AND_I64_POSTRA\0" + /* 8938 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\0" + /* 8966 */ "ATOMIC_LOAD_MIN_I64_POSTRA\0" + /* 8993 */ "ATOMIC_SWAP_I64_POSTRA\0" + /* 9016 */ "ATOMIC_CMP_SWAP_I64_POSTRA\0" + /* 9043 */ "ATOMIC_LOAD_XOR_I64_POSTRA\0" + /* 9070 */ "ATOMIC_LOAD_OR_I64_POSTRA\0" + /* 9096 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\0" + /* 9124 */ "ATOMIC_LOAD_MAX_I64_POSTRA\0" + /* 9151 */ "ATOMIC_LOAD_SUB_I16_POSTRA\0" + /* 9178 */ "ATOMIC_LOAD_ADD_I16_POSTRA\0" + /* 9205 */ "ATOMIC_LOAD_NAND_I16_POSTRA\0" + /* 9233 */ "ATOMIC_LOAD_AND_I16_POSTRA\0" + /* 9260 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\0" + /* 9288 */ "ATOMIC_LOAD_MIN_I16_POSTRA\0" + /* 9315 */ "ATOMIC_SWAP_I16_POSTRA\0" + /* 9338 */ "ATOMIC_CMP_SWAP_I16_POSTRA\0" + /* 9365 */ "ATOMIC_LOAD_XOR_I16_POSTRA\0" + /* 9392 */ "ATOMIC_LOAD_OR_I16_POSTRA\0" + /* 9418 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\0" + /* 9446 */ "ATOMIC_LOAD_MAX_I16_POSTRA\0" + /* 9473 */ "ATOMIC_LOAD_SUB_I8_POSTRA\0" + /* 9499 */ "ATOMIC_LOAD_ADD_I8_POSTRA\0" + /* 9525 */ "ATOMIC_LOAD_NAND_I8_POSTRA\0" + /* 9552 */ "ATOMIC_LOAD_AND_I8_POSTRA\0" + /* 9578 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\0" + /* 9605 */ "ATOMIC_LOAD_MIN_I8_POSTRA\0" + /* 9631 */ "ATOMIC_SWAP_I8_POSTRA\0" + /* 9653 */ "ATOMIC_CMP_SWAP_I8_POSTRA\0" + /* 9679 */ "ATOMIC_LOAD_XOR_I8_POSTRA\0" + /* 9705 */ "ATOMIC_LOAD_OR_I8_POSTRA\0" + /* 9730 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\0" + /* 9757 */ "ATOMIC_LOAD_MAX_I8_POSTRA\0" + /* 9783 */ "RetRA\0" + /* 9789 */ "DLSA\0" + /* 9794 */ "CFCMSA\0" + /* 9801 */ "CTCMSA\0" + /* 9808 */ "CRC32B\0" + /* 9815 */ "CRC32CB\0" + /* 9823 */ "SEB\0" + /* 9827 */ "EHB\0" + /* 9831 */ "TAILCALLREGHB\0" + /* 9845 */ "JR_HB\0" + /* 9851 */ "JALR_HB\0" + /* 9859 */ "LB\0" + /* 9862 */ "SHRA_QB\0" + /* 9870 */ "CMPGDU_LE_QB\0" + /* 9883 */ "CMPGU_LE_QB\0" + /* 9895 */ "PseudoCMPU_LE_QB\0" + /* 9912 */ "SUBUH_QB\0" + /* 9921 */ "ADDUH_QB\0" + /* 9930 */ "PseudoPICK_QB\0" + /* 9944 */ "SHLL_QB\0" + /* 9952 */ "REPL_QB\0" + /* 9960 */ "SHRL_QB\0" + /* 9968 */ "CMPGDU_EQ_QB\0" + /* 9981 */ "CMPGU_EQ_QB\0" + /* 9993 */ "PseudoCMPU_EQ_QB\0" + /* 10010 */ "SHRA_R_QB\0" + /* 10020 */ "SUBUH_R_QB\0" + /* 10031 */ "ADDUH_R_QB\0" + /* 10042 */ "SHRAV_R_QB\0" + /* 10053 */ "ABSQ_S_QB\0" + /* 10063 */ "SUBU_S_QB\0" + /* 10073 */ "ADDU_S_QB\0" + /* 10083 */ "CMPGDU_LT_QB\0" + /* 10096 */ "CMPGU_LT_QB\0" + /* 10108 */ "PseudoCMPU_LT_QB\0" + /* 10125 */ "SUBU_QB\0" + /* 10133 */ "ADDU_QB\0" + /* 10141 */ "SHRAV_QB\0" + /* 10150 */ "SHLLV_QB\0" + /* 10159 */ "REPLV_QB\0" + /* 10168 */ "SHRLV_QB\0" + /* 10177 */ "RADDU_W_QB\0" + /* 10188 */ "SB\0" + /* 10191 */ "MODSUB\0" + /* 10198 */ "G_FSUB\0" + /* 10205 */ "G_STRICT_FSUB\0" + /* 10219 */ "G_ATOMICRMW_FSUB\0" + /* 10236 */ "PseudoMSUB\0" + /* 10247 */ "G_SUB\0" + /* 10253 */ "G_ATOMICRMW_SUB\0" + /* 10269 */ "SRA_B\0" + /* 10275 */ "ADD_A_B\0" + /* 10283 */ "MIN_A_B\0" + /* 10291 */ "ADDS_A_B\0" + /* 10300 */ "MAX_A_B\0" + /* 10308 */ "NLOC_B\0" + /* 10315 */ "NLZC_B\0" + /* 10322 */ "SLD_B\0" + /* 10328 */ "PCKOD_B\0" + /* 10336 */ "ILVOD_B\0" + /* 10344 */ "INSVE_B\0" + /* 10352 */ "VSHF_B\0" + /* 10359 */ "BNEG_B\0" + /* 10366 */ "SRAI_B\0" + /* 10373 */ "SLDI_B\0" + /* 10380 */ "ANDI_B\0" + /* 10387 */ "BNEGI_B\0" + /* 10395 */ "BSELI_B\0" + /* 10403 */ "SLLI_B\0" + /* 10410 */ "SRLI_B\0" + /* 10417 */ "BINSLI_B\0" + /* 10426 */ "CEQI_B\0" + /* 10433 */ "SRARI_B\0" + /* 10441 */ "BCLRI_B\0" + /* 10449 */ "SRLRI_B\0" + /* 10457 */ "NORI_B\0" + /* 10464 */ "XORI_B\0" + /* 10471 */ "BINSRI_B\0" + /* 10480 */ "SPLATI_B\0" + /* 10489 */ "BSETI_B\0" + /* 10497 */ "SUBVI_B\0" + /* 10505 */ "ADDVI_B\0" + /* 10513 */ "BMZI_B\0" + /* 10520 */ "BMNZI_B\0" + /* 10528 */ "FILL_B\0" + /* 10535 */ "SLL_B\0" + /* 10541 */ "SRL_B\0" + /* 10547 */ "BINSL_B\0" + /* 10555 */ "ILVL_B\0" + /* 10562 */ "CEQ_B\0" + /* 10568 */ "SRAR_B\0" + /* 10575 */ "BCLR_B\0" + /* 10582 */ "SRLR_B\0" + /* 10589 */ "BINSR_B\0" + /* 10597 */ "ILVR_B\0" + /* 10604 */ "ASUB_S_B\0" + /* 10613 */ "MOD_S_B\0" + /* 10621 */ "CLE_S_B\0" + /* 10629 */ "AVE_S_B\0" + /* 10637 */ "CLEI_S_B\0" + /* 10646 */ "MINI_S_B\0" + /* 10655 */ "CLTI_S_B\0" + /* 10664 */ "MAXI_S_B\0" + /* 10673 */ "MIN_S_B\0" + /* 10681 */ "AVER_S_B\0" + /* 10690 */ "SUBS_S_B\0" + /* 10699 */ "ADDS_S_B\0" + /* 10708 */ "SAT_S_B\0" + /* 10716 */ "CLT_S_B\0" + /* 10724 */ "SUBSUU_S_B\0" + /* 10735 */ "DIV_S_B\0" + /* 10743 */ "MAX_S_B\0" + /* 10751 */ "COPY_S_B\0" + /* 10760 */ "SPLAT_B\0" + /* 10768 */ "BSET_B\0" + /* 10775 */ "PCNT_B\0" + /* 10782 */ "INSERT_B\0" + /* 10791 */ "ST_B\0" + /* 10796 */ "ASUB_U_B\0" + /* 10805 */ "MOD_U_B\0" + /* 10813 */ "CLE_U_B\0" + /* 10821 */ "AVE_U_B\0" + /* 10829 */ "CLEI_U_B\0" + /* 10838 */ "MINI_U_B\0" + /* 10847 */ "CLTI_U_B\0" + /* 10856 */ "MAXI_U_B\0" + /* 10865 */ "MIN_U_B\0" + /* 10873 */ "AVER_U_B\0" + /* 10882 */ "SUBS_U_B\0" + /* 10891 */ "ADDS_U_B\0" + /* 10900 */ "SUBSUS_U_B\0" + /* 10911 */ "SAT_U_B\0" + /* 10919 */ "CLT_U_B\0" + /* 10927 */ "DIV_U_B\0" + /* 10935 */ "MAX_U_B\0" + /* 10943 */ "COPY_U_B\0" + /* 10952 */ "MSUBV_B\0" + /* 10960 */ "MADDV_B\0" + /* 10968 */ "PCKEV_B\0" + /* 10976 */ "ILVEV_B\0" + /* 10984 */ "MULV_B\0" + /* 10991 */ "BZ_B\0" + /* 10996 */ "BNZ_B\0" + /* 11002 */ "BC\0" + /* 11005 */ "BGEC\0" + /* 11010 */ "BNEC\0" + /* 11015 */ "JIC\0" + /* 11019 */ "G_INTRINSIC\0" + /* 11031 */ "BALC\0" + /* 11036 */ "JIALC\0" + /* 11042 */ "BGEZALC\0" + /* 11050 */ "BLEZALC\0" + /* 11058 */ "BNEZALC\0" + /* 11066 */ "BEQZALC\0" + /* 11074 */ "BGTZALC\0" + /* 11082 */ "BLTZALC\0" + /* 11090 */ "ERETNC\0" + /* 11097 */ "G_FPTRUNC\0" + /* 11107 */ "G_INTRINSIC_TRUNC\0" + /* 11125 */ "G_TRUNC\0" + /* 11133 */ "G_BUILD_VECTOR_TRUNC\0" + /* 11154 */ "SYNC\0" + /* 11159 */ "G_DYN_STACKALLOC\0" + /* 11176 */ "LDPC\0" + /* 11181 */ "AUIPC\0" + /* 11187 */ "ALUIPC\0" + /* 11194 */ "ADDIUPC\0" + /* 11202 */ "LWUPC\0" + /* 11208 */ "LWPC\0" + /* 11213 */ "BEQC\0" + /* 11218 */ "ADDSC\0" + /* 11224 */ "BLTC\0" + /* 11229 */ "BGEUC\0" + /* 11235 */ "BLTUC\0" + /* 11241 */ "BNVC\0" + /* 11246 */ "BOVC\0" + /* 11251 */ "ADDWC\0" + /* 11257 */ "BGEZC\0" + /* 11263 */ "BLEZC\0" + /* 11269 */ "BNEZC\0" + /* 11275 */ "BEQZC\0" + /* 11281 */ "BGTZC\0" + /* 11287 */ "BLTZC\0" + /* 11293 */ "CRC32D\0" + /* 11300 */ "SAAD\0" + /* 11305 */ "G_FMAD\0" + /* 11312 */ "G_INDEXED_SEXTLOAD\0" + /* 11331 */ "G_SEXTLOAD\0" + /* 11342 */ "G_INDEXED_ZEXTLOAD\0" + /* 11361 */ "G_ZEXTLOAD\0" + /* 11372 */ "G_INDEXED_LOAD\0" + /* 11387 */ "G_LOAD\0" + /* 11394 */ "CRC32CD\0" + /* 11402 */ "SCD\0" + /* 11406 */ "DADD\0" + /* 11411 */ "G_VECREDUCE_FADD\0" + /* 11428 */ "G_FADD\0" + /* 11435 */ "G_VECREDUCE_SEQ_FADD\0" + /* 11456 */ "G_STRICT_FADD\0" + /* 11470 */ "G_ATOMICRMW_FADD\0" + /* 11487 */ "PseudoMADD\0" + /* 11498 */ "G_VECREDUCE_ADD\0" + /* 11514 */ "G_ADD\0" + /* 11520 */ "G_PTR_ADD\0" + /* 11530 */ "G_ATOMICRMW_ADD\0" + /* 11546 */ "DSHD\0" + /* 11551 */ "YIELD\0" + /* 11557 */ "LLD\0" + /* 11561 */ "G_ATOMICRMW_NAND\0" + /* 11578 */ "G_VECREDUCE_AND\0" + /* 11594 */ "G_AND\0" + /* 11600 */ "G_ATOMICRMW_AND\0" + /* 11616 */ "PREPEND\0" + /* 11624 */ "APPEND\0" + /* 11631 */ "LIFETIME_END\0" + /* 11644 */ "G_BRCOND\0" + /* 11653 */ "G_LLROUND\0" + /* 11663 */ "G_LROUND\0" + /* 11672 */ "G_INTRINSIC_ROUND\0" + /* 11690 */ "DMOD\0" + /* 11695 */ "LOAD_STACK_GUARD\0" + /* 11712 */ "SD\0" + /* 11715 */ "FLOG2_D\0" + /* 11723 */ "FEXP2_D\0" + /* 11731 */ "MINA_D\0" + /* 11738 */ "SRA_D\0" + /* 11744 */ "MAXA_D\0" + /* 11751 */ "ADD_A_D\0" + /* 11759 */ "FMIN_A_D\0" + /* 11768 */ "ADDS_A_D\0" + /* 11777 */ "FMAX_A_D\0" + /* 11786 */ "FSUB_D\0" + /* 11793 */ "FMSUB_D\0" + /* 11801 */ "NLOC_D\0" + /* 11808 */ "NLZC_D\0" + /* 11815 */ "FADD_D\0" + /* 11822 */ "FMADD_D\0" + /* 11830 */ "SLD_D\0" + /* 11836 */ "PCKOD_D\0" + /* 11844 */ "ILVOD_D\0" + /* 11852 */ "FCLE_D\0" + /* 11859 */ "FSLE_D\0" + /* 11866 */ "CMP_SLE_D\0" + /* 11876 */ "FCULE_D\0" + /* 11884 */ "FSULE_D\0" + /* 11892 */ "CMP_SULE_D\0" + /* 11903 */ "CMP_ULE_D\0" + /* 11913 */ "CMP_LE_D\0" + /* 11922 */ "FCNE_D\0" + /* 11929 */ "FSNE_D\0" + /* 11936 */ "FCUNE_D\0" + /* 11944 */ "FSUNE_D\0" + /* 11952 */ "INSVE_D\0" + /* 11960 */ "FCAF_D\0" + /* 11967 */ "FSAF_D\0" + /* 11974 */ "CMP_SAF_D\0" + /* 11984 */ "MSUBF_D\0" + /* 11992 */ "MADDF_D\0" + /* 12000 */ "VSHF_D\0" + /* 12007 */ "CMP_F_D\0" + /* 12015 */ "BNEG_D\0" + /* 12022 */ "SRAI_D\0" + /* 12029 */ "SLDI_D\0" + /* 12036 */ "BNEGI_D\0" + /* 12044 */ "SLLI_D\0" + /* 12051 */ "SRLI_D\0" + /* 12058 */ "BINSLI_D\0" + /* 12067 */ "CEQI_D\0" + /* 12074 */ "SRARI_D\0" + /* 12082 */ "BCLRI_D\0" + /* 12090 */ "SRLRI_D\0" + /* 12098 */ "BINSRI_D\0" + /* 12107 */ "SPLATI_D\0" + /* 12116 */ "BSETI_D\0" + /* 12124 */ "SUBVI_D\0" + /* 12132 */ "ADDVI_D\0" + /* 12140 */ "SEL_D\0" + /* 12146 */ "FILL_D\0" + /* 12153 */ "SLL_D\0" + /* 12159 */ "FEXUPL_D\0" + /* 12168 */ "FFQL_D\0" + /* 12175 */ "SRL_D\0" + /* 12181 */ "BINSL_D\0" + /* 12189 */ "FMUL_D\0" + /* 12196 */ "ILVL_D\0" + /* 12203 */ "FMIN_D\0" + /* 12210 */ "FCUN_D\0" + /* 12217 */ "FSUN_D\0" + /* 12224 */ "CMP_SUN_D\0" + /* 12234 */ "CMP_UN_D\0" + /* 12243 */ "FRCP_D\0" + /* 12250 */ "FCEQ_D\0" + /* 12257 */ "FSEQ_D\0" + /* 12264 */ "CMP_SEQ_D\0" + /* 12274 */ "FCUEQ_D\0" + /* 12282 */ "FSUEQ_D\0" + /* 12290 */ "CMP_SUEQ_D\0" + /* 12301 */ "CMP_UEQ_D\0" + /* 12311 */ "CMP_EQ_D\0" + /* 12320 */ "SRAR_D\0" + /* 12327 */ "LDR_D\0" + /* 12333 */ "BCLR_D\0" + /* 12340 */ "SRLR_D\0" + /* 12347 */ "FCOR_D\0" + /* 12354 */ "FSOR_D\0" + /* 12361 */ "FEXUPR_D\0" + /* 12370 */ "FFQR_D\0" + /* 12377 */ "BINSR_D\0" + /* 12385 */ "STR_D\0" + /* 12391 */ "ILVR_D\0" + /* 12398 */ "FABS_D\0" + /* 12405 */ "FCLASS_D\0" + /* 12414 */ "ASUB_S_D\0" + /* 12423 */ "HSUB_S_D\0" + /* 12432 */ "DPSUB_S_D\0" + /* 12442 */ "FTRUNC_S_D\0" + /* 12453 */ "HADD_S_D\0" + /* 12462 */ "DPADD_S_D\0" + /* 12472 */ "MOD_S_D\0" + /* 12480 */ "CLE_S_D\0" + /* 12488 */ "AVE_S_D\0" + /* 12496 */ "CLEI_S_D\0" + /* 12505 */ "MINI_S_D\0" + /* 12514 */ "CLTI_S_D\0" + /* 12523 */ "MAXI_S_D\0" + /* 12532 */ "MIN_S_D\0" + /* 12540 */ "DOTP_S_D\0" + /* 12549 */ "AVER_S_D\0" + /* 12558 */ "SUBS_S_D\0" + /* 12567 */ "ADDS_S_D\0" + /* 12576 */ "SAT_S_D\0" + /* 12584 */ "CLT_S_D\0" + /* 12592 */ "FFINT_S_D\0" + /* 12602 */ "FTINT_S_D\0" + /* 12612 */ "SUBSUU_S_D\0" + /* 12623 */ "DIV_S_D\0" + /* 12631 */ "MAX_S_D\0" + /* 12639 */ "COPY_S_D\0" + /* 12648 */ "SPLAT_D\0" + /* 12656 */ "BSET_D\0" + /* 12663 */ "FCLT_D\0" + /* 12670 */ "FSLT_D\0" + /* 12677 */ "CMP_SLT_D\0" + /* 12687 */ "FCULT_D\0" + /* 12695 */ "FSULT_D\0" + /* 12703 */ "CMP_SULT_D\0" + /* 12714 */ "CMP_ULT_D\0" + /* 12724 */ "CMP_LT_D\0" + /* 12733 */ "PCNT_D\0" + /* 12740 */ "FRINT_D\0" + /* 12748 */ "INSERT_D\0" + /* 12757 */ "FSQRT_D\0" + /* 12765 */ "FRSQRT_D\0" + /* 12774 */ "ST_D\0" + /* 12779 */ "ASUB_U_D\0" + /* 12788 */ "HSUB_U_D\0" + /* 12797 */ "DPSUB_U_D\0" + /* 12807 */ "FTRUNC_U_D\0" + /* 12818 */ "HADD_U_D\0" + /* 12827 */ "DPADD_U_D\0" + /* 12837 */ "MOD_U_D\0" + /* 12845 */ "CLE_U_D\0" + /* 12853 */ "AVE_U_D\0" + /* 12861 */ "CLEI_U_D\0" + /* 12870 */ "MINI_U_D\0" + /* 12879 */ "CLTI_U_D\0" + /* 12888 */ "MAXI_U_D\0" + /* 12897 */ "MIN_U_D\0" + /* 12905 */ "DOTP_U_D\0" + /* 12914 */ "AVER_U_D\0" + /* 12923 */ "SUBS_U_D\0" + /* 12932 */ "ADDS_U_D\0" + /* 12941 */ "SUBSUS_U_D\0" + /* 12952 */ "SAT_U_D\0" + /* 12960 */ "CLT_U_D\0" + /* 12968 */ "FFINT_U_D\0" + /* 12978 */ "FTINT_U_D\0" + /* 12988 */ "DIV_U_D\0" + /* 12996 */ "MAX_U_D\0" + /* 13004 */ "MSUBV_D\0" + /* 13012 */ "MADDV_D\0" + /* 13020 */ "PCKEV_D\0" + /* 13028 */ "ILVEV_D\0" + /* 13036 */ "FDIV_D\0" + /* 13043 */ "MULV_D\0" + /* 13050 */ "PseudoTRUNC_W_D\0" + /* 13066 */ "FMAX_D\0" + /* 13073 */ "BZ_D\0" + /* 13078 */ "SELNEZ_D\0" + /* 13087 */ "BNZ_D\0" + /* 13093 */ "SELEQZ_D\0" + /* 13102 */ "LBE\0" + /* 13106 */ "PSEUDO_PROBE\0" + /* 13119 */ "SBE\0" + /* 13123 */ "G_SSUBE\0" + /* 13131 */ "G_USUBE\0" + /* 13139 */ "G_FENCE\0" + /* 13147 */ "ARITH_FENCE\0" + /* 13159 */ "REG_SEQUENCE\0" + /* 13172 */ "SCE\0" + /* 13176 */ "G_SADDE\0" + /* 13184 */ "G_UADDE\0" + /* 13192 */ "G_FMINNUM_IEEE\0" + /* 13207 */ "G_FMAXNUM_IEEE\0" + /* 13222 */ "CACHEE\0" + /* 13229 */ "PREFE\0" + /* 13235 */ "BGE\0" + /* 13239 */ "SGE\0" + /* 13243 */ "TGE\0" + /* 13247 */ "CACHE\0" + /* 13253 */ "LHE\0" + /* 13257 */ "SHE\0" + /* 13261 */ "SIGRIE\0" + /* 13268 */ "G_JUMP_TABLE\0" + /* 13281 */ "BUNDLE\0" + /* 13288 */ "LLE\0" + /* 13292 */ "SLE\0" + /* 13296 */ "LWLE\0" + /* 13301 */ "SWLE\0" + /* 13306 */ "BNE\0" + /* 13310 */ "G_MEMCPY_INLINE\0" + /* 13326 */ "SNE\0" + /* 13330 */ "TNE\0" + /* 13334 */ "LOCAL_ESCAPE\0" + /* 13347 */ "DVPE\0" + /* 13352 */ "EVPE\0" + /* 13357 */ "G_INDEXED_STORE\0" + /* 13373 */ "G_STORE\0" + /* 13381 */ "LWRE\0" + /* 13386 */ "SWRE\0" + /* 13391 */ "G_BITREVERSE\0" + /* 13404 */ "PAUSE\0" + /* 13410 */ "DBG_VALUE\0" + /* 13420 */ "G_GLOBAL_VALUE\0" + /* 13435 */ "G_MEMMOVE\0" + /* 13445 */ "LWE\0" + /* 13449 */ "SWE\0" + /* 13453 */ "G_FREEZE\0" + /* 13462 */ "G_FCANONICALIZE\0" + /* 13478 */ "LBuE\0" + /* 13483 */ "LHuE\0" + /* 13488 */ "BC0F\0" + /* 13493 */ "BC1F\0" + /* 13498 */ "BC2F\0" + /* 13503 */ "BC3F\0" + /* 13508 */ "G_CTLZ_ZERO_UNDEF\0" + /* 13526 */ "G_CTTZ_ZERO_UNDEF\0" + /* 13544 */ "G_IMPLICIT_DEF\0" + /* 13559 */ "PREF\0" + /* 13564 */ "DBG_INSTR_REF\0" + /* 13578 */ "TLBINVF\0" + /* 13586 */ "TLBGINVF\0" + /* 13595 */ "G_FNEG\0" + /* 13602 */ "TAILCALLHB64R6REG\0" + /* 13620 */ "TAILCALL64R6REG\0" + /* 13636 */ "TAILCALLHBR6REG\0" + /* 13652 */ "TAILCALLR6REG\0" + /* 13666 */ "EXTRACT_SUBREG\0" + /* 13681 */ "INSERT_SUBREG\0" + /* 13695 */ "TAILCALLREG\0" + /* 13707 */ "G_SEXT_INREG\0" + /* 13720 */ "SUBREG_TO_REG\0" + /* 13734 */ "G_ATOMIC_CMPXCHG\0" + /* 13751 */ "G_ATOMICRMW_XCHG\0" + /* 13768 */ "G_FLOG\0" + /* 13775 */ "G_VAARG\0" + /* 13783 */ "PREALLOCATED_ARG\0" + /* 13800 */ "CRC32H\0" + /* 13807 */ "DSBH\0" + /* 13812 */ "WSBH\0" + /* 13817 */ "CRC32CH\0" + /* 13825 */ "SEH\0" + /* 13829 */ "G_SMULH\0" + /* 13837 */ "G_UMULH\0" + /* 13845 */ "SHRA_PH\0" + /* 13853 */ "PRECRQ_QB_PH\0" + /* 13866 */ "PRECR_QB_PH\0" + /* 13878 */ "PRECRQU_S_QB_PH\0" + /* 13894 */ "PseudoCMP_LE_PH\0" + /* 13910 */ "SUBQH_PH\0" + /* 13919 */ "ADDQH_PH\0" + /* 13928 */ "PseudoPICK_PH\0" + /* 13942 */ "SHLL_PH\0" + /* 13950 */ "REPL_PH\0" + /* 13958 */ "SHRL_PH\0" + /* 13966 */ "PACKRL_PH\0" + /* 13976 */ "MUL_PH\0" + /* 13983 */ "SUBQ_PH\0" + /* 13991 */ "ADDQ_PH\0" + /* 13999 */ "PseudoCMP_EQ_PH\0" + /* 14015 */ "SHRA_R_PH\0" + /* 14025 */ "SUBQH_R_PH\0" + /* 14036 */ "ADDQH_R_PH\0" + /* 14047 */ "SHRAV_R_PH\0" + /* 14058 */ "MULQ_RS_PH\0" + /* 14069 */ "SHLL_S_PH\0" + /* 14079 */ "MUL_S_PH\0" + /* 14088 */ "SUBQ_S_PH\0" + /* 14098 */ "ADDQ_S_PH\0" + /* 14108 */ "MULQ_S_PH\0" + /* 14118 */ "ABSQ_S_PH\0" + /* 14128 */ "SUBU_S_PH\0" + /* 14138 */ "ADDU_S_PH\0" + /* 14148 */ "SHLLV_S_PH\0" + /* 14159 */ "PseudoCMP_LT_PH\0" + /* 14175 */ "SUBU_PH\0" + /* 14183 */ "ADDU_PH\0" + /* 14191 */ "SHRAV_PH\0" + /* 14200 */ "SHLLV_PH\0" + /* 14209 */ "REPLV_PH\0" + /* 14218 */ "SHRLV_PH\0" + /* 14227 */ "DPA_W_PH\0" + /* 14236 */ "MULSA_W_PH\0" + /* 14247 */ "DPAQX_SA_W_PH\0" + /* 14261 */ "DPSQX_SA_W_PH\0" + /* 14275 */ "DPS_W_PH\0" + /* 14284 */ "DPAQ_S_W_PH\0" + /* 14296 */ "MULSAQ_S_W_PH\0" + /* 14310 */ "DPSQ_S_W_PH\0" + /* 14322 */ "DPAQX_S_W_PH\0" + /* 14335 */ "DPSQX_S_W_PH\0" + /* 14348 */ "DPAX_W_PH\0" + /* 14358 */ "DPSX_W_PH\0" + /* 14368 */ "SH\0" + /* 14371 */ "DMUH\0" + /* 14376 */ "SRA_H\0" + /* 14382 */ "ADD_A_H\0" + /* 14390 */ "MIN_A_H\0" + /* 14398 */ "ADDS_A_H\0" + /* 14407 */ "MAX_A_H\0" + /* 14415 */ "NLOC_H\0" + /* 14422 */ "NLZC_H\0" + /* 14429 */ "SLD_H\0" + /* 14435 */ "PCKOD_H\0" + /* 14443 */ "ILVOD_H\0" + /* 14451 */ "INSVE_H\0" + /* 14459 */ "VSHF_H\0" + /* 14466 */ "BNEG_H\0" + /* 14473 */ "SRAI_H\0" + /* 14480 */ "SLDI_H\0" + /* 14487 */ "BNEGI_H\0" + /* 14495 */ "SLLI_H\0" + /* 14502 */ "SRLI_H\0" + /* 14509 */ "BINSLI_H\0" + /* 14518 */ "CEQI_H\0" + /* 14525 */ "SRARI_H\0" + /* 14533 */ "BCLRI_H\0" + /* 14541 */ "SRLRI_H\0" + /* 14549 */ "BINSRI_H\0" + /* 14558 */ "SPLATI_H\0" + /* 14567 */ "BSETI_H\0" + /* 14575 */ "SUBVI_H\0" + /* 14583 */ "ADDVI_H\0" + /* 14591 */ "FILL_H\0" + /* 14598 */ "SLL_H\0" + /* 14604 */ "SRL_H\0" + /* 14610 */ "BINSL_H\0" + /* 14618 */ "ILVL_H\0" + /* 14625 */ "FEXDO_H\0" + /* 14633 */ "CEQ_H\0" + /* 14639 */ "FTQ_H\0" + /* 14645 */ "MSUB_Q_H\0" + /* 14654 */ "MADD_Q_H\0" + /* 14663 */ "MUL_Q_H\0" + /* 14671 */ "MSUBR_Q_H\0" + /* 14681 */ "MADDR_Q_H\0" + /* 14691 */ "MULR_Q_H\0" + /* 14700 */ "SRAR_H\0" + /* 14707 */ "BCLR_H\0" + /* 14714 */ "SRLR_H\0" + /* 14721 */ "BINSR_H\0" + /* 14729 */ "ILVR_H\0" + /* 14736 */ "ASUB_S_H\0" + /* 14745 */ "HSUB_S_H\0" + /* 14754 */ "DPSUB_S_H\0" + /* 14764 */ "HADD_S_H\0" + /* 14773 */ "DPADD_S_H\0" + /* 14783 */ "MOD_S_H\0" + /* 14791 */ "CLE_S_H\0" + /* 14799 */ "AVE_S_H\0" + /* 14807 */ "CLEI_S_H\0" + /* 14816 */ "MINI_S_H\0" + /* 14825 */ "CLTI_S_H\0" + /* 14834 */ "MAXI_S_H\0" + /* 14843 */ "MIN_S_H\0" + /* 14851 */ "DOTP_S_H\0" + /* 14860 */ "AVER_S_H\0" + /* 14869 */ "EXTR_S_H\0" + /* 14878 */ "SUBS_S_H\0" + /* 14887 */ "ADDS_S_H\0" + /* 14896 */ "SAT_S_H\0" + /* 14904 */ "CLT_S_H\0" + /* 14912 */ "SUBSUU_S_H\0" + /* 14923 */ "DIV_S_H\0" + /* 14931 */ "EXTRV_S_H\0" + /* 14941 */ "MAX_S_H\0" + /* 14949 */ "COPY_S_H\0" + /* 14958 */ "SPLAT_H\0" + /* 14966 */ "BSET_H\0" + /* 14973 */ "PCNT_H\0" + /* 14980 */ "INSERT_H\0" + /* 14989 */ "ST_H\0" + /* 14994 */ "ASUB_U_H\0" + /* 15003 */ "HSUB_U_H\0" + /* 15012 */ "DPSUB_U_H\0" + /* 15022 */ "HADD_U_H\0" + /* 15031 */ "DPADD_U_H\0" + /* 15041 */ "MOD_U_H\0" + /* 15049 */ "CLE_U_H\0" + /* 15057 */ "AVE_U_H\0" + /* 15065 */ "CLEI_U_H\0" + /* 15074 */ "MINI_U_H\0" + /* 15083 */ "CLTI_U_H\0" + /* 15092 */ "MAXI_U_H\0" + /* 15101 */ "MIN_U_H\0" + /* 15109 */ "DOTP_U_H\0" + /* 15118 */ "AVER_U_H\0" + /* 15127 */ "SUBS_U_H\0" + /* 15136 */ "ADDS_U_H\0" + /* 15145 */ "SUBSUS_U_H\0" + /* 15156 */ "SAT_U_H\0" + /* 15164 */ "CLT_U_H\0" + /* 15172 */ "DIV_U_H\0" + /* 15180 */ "MAX_U_H\0" + /* 15188 */ "COPY_U_H\0" + /* 15197 */ "MSUBV_H\0" + /* 15205 */ "MADDV_H\0" + /* 15213 */ "PCKEV_H\0" + /* 15221 */ "ILVEV_H\0" + /* 15229 */ "MULV_H\0" + /* 15236 */ "BZ_H\0" + /* 15241 */ "BNZ_H\0" + /* 15247 */ "SYNCI\0" + /* 15253 */ "DI\0" + /* 15256 */ "TGEI\0" + /* 15261 */ "TNEI\0" + /* 15266 */ "DAHI\0" + /* 15271 */ "PseudoMFHI\0" + /* 15282 */ "PseudoMTLOHI\0" + /* 15295 */ "DBG_PHI\0" + /* 15303 */ "MFTHI\0" + /* 15309 */ "MTHI\0" + /* 15314 */ "MTTHI\0" + /* 15320 */ "TEQI\0" + /* 15325 */ "G_FPTOSI\0" + /* 15334 */ "DATI\0" + /* 15339 */ "TLTI\0" + /* 15344 */ "DAUI\0" + /* 15349 */ "G_FPTOUI\0" + /* 15358 */ "GINVI\0" + /* 15364 */ "TLBWI\0" + /* 15370 */ "TLBGWI\0" + /* 15377 */ "G_FPOWI\0" + /* 15385 */ "MOVN_I64_I\0" + /* 15396 */ "MOVZ_I64_I\0" + /* 15407 */ "MOVF_I\0" + /* 15414 */ "PseudoSELECTFP_F_I\0" + /* 15433 */ "MOVN_I_I\0" + /* 15442 */ "MOVZ_I_I\0" + /* 15451 */ "PseudoD_SELECT_I\0" + /* 15468 */ "PseudoSELECT_I\0" + /* 15483 */ "MOVT_I\0" + /* 15490 */ "PseudoSELECTFP_T_I\0" + /* 15509 */ "J\0" + /* 15511 */ "BREAK\0" + /* 15517 */ "FORK\0" + /* 15522 */ "G_PTRMASK\0" + /* 15532 */ "BAL\0" + /* 15536 */ "JAL\0" + /* 15540 */ "BGEZAL\0" + /* 15547 */ "BLTZAL\0" + /* 15554 */ "MULEU_S_PH_QBL\0" + /* 15569 */ "PRECEU_PH_QBL\0" + /* 15583 */ "PRECEQU_PH_QBL\0" + /* 15598 */ "DPAU_H_QBL\0" + /* 15609 */ "DPSU_H_QBL\0" + /* 15620 */ "LDL\0" + /* 15624 */ "SDL\0" + /* 15628 */ "GC_LABEL\0" + /* 15637 */ "DBG_LABEL\0" + /* 15647 */ "EH_LABEL\0" + /* 15656 */ "ANNOTATION_LABEL\0" + /* 15673 */ "BGEL\0" + /* 15678 */ "BLEL\0" + /* 15683 */ "BNEL\0" + /* 15688 */ "ICALL_BRANCH_FUNNEL\0" + /* 15708 */ "BC1FL\0" + /* 15714 */ "BC2FL\0" + /* 15720 */ "BC3FL\0" + /* 15726 */ "MAQ_SA_W_PHL\0" + /* 15739 */ "PRECEQ_W_PHL\0" + /* 15752 */ "MAQ_S_W_PHL\0" + /* 15764 */ "MULEQ_S_W_PHL\0" + /* 15778 */ "G_FSHL\0" + /* 15785 */ "G_SHL\0" + /* 15791 */ "G_FCEIL\0" + /* 15799 */ "TAILCALL\0" + /* 15808 */ "HYPCALL\0" + /* 15816 */ "SYSCALL\0" + /* 15824 */ "PATCHABLE_TAIL_CALL\0" + /* 15844 */ "PATCHABLE_TYPED_EVENT_CALL\0" + /* 15871 */ "PATCHABLE_EVENT_CALL\0" + /* 15892 */ "FENTRY_CALL\0" + /* 15904 */ "BGEZALL\0" + /* 15912 */ "BLTZALL\0" + /* 15920 */ "KILL\0" + /* 15925 */ "DSLL\0" + /* 15930 */ "DROL\0" + /* 15935 */ "BEQL\0" + /* 15940 */ "DSRL\0" + /* 15945 */ "BC1TL\0" + /* 15951 */ "BC2TL\0" + /* 15957 */ "BC3TL\0" + /* 15963 */ "BGTL\0" + /* 15968 */ "BLTL\0" + /* 15973 */ "G_ROTL\0" + /* 15980 */ "BGEUL\0" + /* 15986 */ "BLEUL\0" + /* 15992 */ "DMUL\0" + /* 15997 */ "G_VECREDUCE_FMUL\0" + /* 16014 */ "G_FMUL\0" + /* 16021 */ "G_VECREDUCE_SEQ_FMUL\0" + /* 16042 */ "G_STRICT_FMUL\0" + /* 16056 */ "G_VECREDUCE_MUL\0" + /* 16072 */ "G_MUL\0" + /* 16078 */ "BGTUL\0" + /* 16084 */ "BLTUL\0" + /* 16090 */ "LWL\0" + /* 16094 */ "SWL\0" + /* 16098 */ "BGEZL\0" + /* 16104 */ "BLEZL\0" + /* 16110 */ "BGTZL\0" + /* 16116 */ "BLTZL\0" + /* 16122 */ "PseudoCVT_D64_L\0" + /* 16138 */ "PseudoCVT_S_L\0" + /* 16152 */ "G_FREM\0" + /* 16159 */ "G_STRICT_FREM\0" + /* 16173 */ "G_SREM\0" + /* 16180 */ "G_UREM\0" + /* 16187 */ "G_SDIVREM\0" + /* 16197 */ "G_UDIVREM\0" + /* 16207 */ "MFGC0_MM\0" + /* 16216 */ "MFHGC0_MM\0" + /* 16226 */ "MTHGC0_MM\0" + /* 16236 */ "MTGC0_MM\0" + /* 16245 */ "LDC1_MM\0" + /* 16253 */ "SDC1_MM\0" + /* 16261 */ "CFC1_MM\0" + /* 16269 */ "MFC1_MM\0" + /* 16277 */ "CTC1_MM\0" + /* 16285 */ "MTC1_MM\0" + /* 16293 */ "LWC1_MM\0" + /* 16301 */ "SWC1_MM\0" + /* 16309 */ "LUXC1_MM\0" + /* 16318 */ "SUXC1_MM\0" + /* 16327 */ "LWXC1_MM\0" + /* 16336 */ "SWXC1_MM\0" + /* 16345 */ "MFHC1_D32_MM\0" + /* 16358 */ "MTHC1_D32_MM\0" + /* 16371 */ "FSUB_D32_MM\0" + /* 16383 */ "NMSUB_D32_MM\0" + /* 16396 */ "FADD_D32_MM\0" + /* 16408 */ "NMADD_D32_MM\0" + /* 16421 */ "C_NGE_D32_MM\0" + /* 16434 */ "C_NGLE_D32_MM\0" + /* 16448 */ "C_OLE_D32_MM\0" + /* 16461 */ "C_ULE_D32_MM\0" + /* 16474 */ "C_LE_D32_MM\0" + /* 16486 */ "C_SF_D32_MM\0" + /* 16498 */ "MOVF_D32_MM\0" + /* 16510 */ "C_F_D32_MM\0" + /* 16521 */ "FNEG_D32_MM\0" + /* 16533 */ "MOVN_I_D32_MM\0" + /* 16547 */ "MOVZ_I_D32_MM\0" + /* 16561 */ "C_NGL_D32_MM\0" + /* 16574 */ "FMUL_D32_MM\0" + /* 16586 */ "C_UN_D32_MM\0" + /* 16598 */ "RECIP_D32_MM\0" + /* 16611 */ "FCMP_D32_MM\0" + /* 16623 */ "C_SEQ_D32_MM\0" + /* 16636 */ "C_UEQ_D32_MM\0" + /* 16649 */ "C_EQ_D32_MM\0" + /* 16661 */ "FABS_D32_MM\0" + /* 16673 */ "CVT_S_D32_MM\0" + /* 16686 */ "C_NGT_D32_MM\0" + /* 16699 */ "C_OLT_D32_MM\0" + /* 16712 */ "C_ULT_D32_MM\0" + /* 16725 */ "C_LT_D32_MM\0" + /* 16737 */ "FSQRT_D32_MM\0" + /* 16750 */ "RSQRT_D32_MM\0" + /* 16763 */ "MOVT_D32_MM\0" + /* 16775 */ "FDIV_D32_MM\0" + /* 16787 */ "FMOV_D32_MM\0" + /* 16799 */ "CVT_W_D32_MM\0" + /* 16812 */ "BPOSGE32_MM\0" + /* 16824 */ "LWM32_MM\0" + /* 16833 */ "SWM32_MM\0" + /* 16842 */ "FCMP_S32_MM\0" + /* 16854 */ "CFC2_MM\0" + /* 16862 */ "CTC2_MM\0" + /* 16870 */ "ADDIUR2_MM\0" + /* 16881 */ "MFHC1_D64_MM\0" + /* 16894 */ "MTHC1_D64_MM\0" + /* 16907 */ "MTC1_D64_MM\0" + /* 16919 */ "FSUB_D64_MM\0" + /* 16931 */ "FADD_D64_MM\0" + /* 16943 */ "C_NGE_D64_MM\0" + /* 16956 */ "C_NGLE_D64_MM\0" + /* 16970 */ "C_OLE_D64_MM\0" + /* 16983 */ "C_ULE_D64_MM\0" + /* 16996 */ "C_LE_D64_MM\0" + /* 17008 */ "C_SF_D64_MM\0" + /* 17020 */ "C_F_D64_MM\0" + /* 17031 */ "FNEG_D64_MM\0" + /* 17043 */ "C_NGL_D64_MM\0" + /* 17056 */ "FMUL_D64_MM\0" + /* 17068 */ "CVT_L_D64_MM\0" + /* 17081 */ "C_UN_D64_MM\0" + /* 17093 */ "RECIP_D64_MM\0" + /* 17106 */ "C_SEQ_D64_MM\0" + /* 17119 */ "C_UEQ_D64_MM\0" + /* 17132 */ "C_EQ_D64_MM\0" + /* 17144 */ "FABS_D64_MM\0" + /* 17156 */ "CVT_S_D64_MM\0" + /* 17169 */ "C_NGT_D64_MM\0" + /* 17182 */ "C_OLT_D64_MM\0" + /* 17195 */ "C_ULT_D64_MM\0" + /* 17208 */ "C_LT_D64_MM\0" + /* 17220 */ "FSQRT_D64_MM\0" + /* 17233 */ "RSQRT_D64_MM\0" + /* 17246 */ "FDIV_D64_MM\0" + /* 17258 */ "FMOV_D64_MM\0" + /* 17270 */ "CVT_W_D64_MM\0" + /* 17283 */ "ADDIUS5_MM\0" + /* 17294 */ "SB16_MM\0" + /* 17302 */ "JRC16_MM\0" + /* 17311 */ "AND16_MM\0" + /* 17320 */ "MOVE16_MM\0" + /* 17330 */ "SH16_MM\0" + /* 17338 */ "ANDI16_MM\0" + /* 17348 */ "MFHI16_MM\0" + /* 17358 */ "LI16_MM\0" + /* 17366 */ "BREAK16_MM\0" + /* 17377 */ "SLL16_MM\0" + /* 17386 */ "SRL16_MM\0" + /* 17395 */ "LWM16_MM\0" + /* 17404 */ "SWM16_MM\0" + /* 17413 */ "MFLO16_MM\0" + /* 17423 */ "SDBBP16_MM\0" + /* 17434 */ "JR16_MM\0" + /* 17442 */ "JALR16_MM\0" + /* 17452 */ "XOR16_MM\0" + /* 17461 */ "JALRS16_MM\0" + /* 17472 */ "NOT16_MM\0" + /* 17481 */ "LBU16_MM\0" + /* 17490 */ "SUBU16_MM\0" + /* 17500 */ "ADDU16_MM\0" + /* 17510 */ "LHU16_MM\0" + /* 17519 */ "LW16_MM\0" + /* 17527 */ "SW16_MM\0" + /* 17535 */ "BNEZ16_MM\0" + /* 17545 */ "BEQZ16_MM\0" + /* 17555 */ "PRECEU_PH_QBLA_MM\0" + /* 17573 */ "PRECEQU_PH_QBLA_MM\0" + /* 17592 */ "PRECEU_PH_QBRA_MM\0" + /* 17610 */ "PRECEQU_PH_QBRA_MM\0" + /* 17629 */ "SRA_MM\0" + /* 17636 */ "SEB_MM\0" + /* 17643 */ "EHB_MM\0" + /* 17650 */ "LB_MM\0" + /* 17656 */ "CMPGU_LE_QB_MM\0" + /* 17671 */ "CMPU_LE_QB_MM\0" + /* 17685 */ "PICK_QB_MM\0" + /* 17696 */ "SHLL_QB_MM\0" + /* 17707 */ "REPL_QB_MM\0" + /* 17718 */ "SHRL_QB_MM\0" + /* 17729 */ "CMPGU_EQ_QB_MM\0" + /* 17744 */ "CMPU_EQ_QB_MM\0" + /* 17758 */ "SUBU_S_QB_MM\0" + /* 17771 */ "ADDU_S_QB_MM\0" + /* 17784 */ "CMPGU_LT_QB_MM\0" + /* 17799 */ "CMPU_LT_QB_MM\0" + /* 17813 */ "SUBU_QB_MM\0" + /* 17824 */ "ADDU_QB_MM\0" + /* 17835 */ "SHLLV_QB_MM\0" + /* 17847 */ "REPLV_QB_MM\0" + /* 17859 */ "SHRLV_QB_MM\0" + /* 17871 */ "RADDU_W_QB_MM\0" + /* 17885 */ "SB_MM\0" + /* 17891 */ "MODSUB_MM\0" + /* 17901 */ "PseudoMSUB_MM\0" + /* 17915 */ "SYNC_MM\0" + /* 17923 */ "ADDIUPC_MM\0" + /* 17934 */ "ADDSC_MM\0" + /* 17943 */ "ADDWC_MM\0" + /* 17952 */ "BNEZC_MM\0" + /* 17961 */ "BEQZC_MM\0" + /* 17970 */ "PseudoMADD_MM\0" + /* 17984 */ "AND_MM\0" + /* 17991 */ "LBE_MM\0" + /* 17998 */ "SBE_MM\0" + /* 18005 */ "SCE_MM\0" + /* 18012 */ "CACHEE_MM\0" + /* 18022 */ "PREFE_MM\0" + /* 18031 */ "TGE_MM\0" + /* 18038 */ "CACHE_MM\0" + /* 18047 */ "LHE_MM\0" + /* 18054 */ "SHE_MM\0" + /* 18061 */ "LLE_MM\0" + /* 18068 */ "LWLE_MM\0" + /* 18076 */ "SWLE_MM\0" + /* 18084 */ "BNE_MM\0" + /* 18091 */ "TNE_MM\0" + /* 18098 */ "LWRE_MM\0" + /* 18106 */ "SWRE_MM\0" + /* 18114 */ "PAUSE_MM\0" + /* 18123 */ "LWE_MM\0" + /* 18130 */ "SWE_MM\0" + /* 18137 */ "LBuE_MM\0" + /* 18145 */ "LHuE_MM\0" + /* 18153 */ "BC1F_MM\0" + /* 18161 */ "PREF_MM\0" + /* 18169 */ "TLBGINVF_MM\0" + /* 18181 */ "TAILCALLREG_MM\0" + /* 18196 */ "WSBH_MM\0" + /* 18204 */ "SEH_MM\0" + /* 18211 */ "LH_MM\0" + /* 18217 */ "SHRA_PH_MM\0" + /* 18228 */ "PRECRQ_QB_PH_MM\0" + /* 18244 */ "PRECRQU_S_QB_PH_MM\0" + /* 18263 */ "CMP_LE_PH_MM\0" + /* 18276 */ "PICK_PH_MM\0" + /* 18287 */ "SHLL_PH_MM\0" + /* 18298 */ "REPL_PH_MM\0" + /* 18309 */ "PACKRL_PH_MM\0" + /* 18322 */ "SUBQ_PH_MM\0" + /* 18333 */ "ADDQ_PH_MM\0" + /* 18344 */ "CMP_EQ_PH_MM\0" + /* 18357 */ "SHRA_R_PH_MM\0" + /* 18370 */ "SHRAV_R_PH_MM\0" + /* 18384 */ "MULQ_RS_PH_MM\0" + /* 18398 */ "SHLL_S_PH_MM\0" + /* 18411 */ "SUBQ_S_PH_MM\0" + /* 18424 */ "ADDQ_S_PH_MM\0" + /* 18437 */ "ABSQ_S_PH_MM\0" + /* 18450 */ "SHLLV_S_PH_MM\0" + /* 18464 */ "CMP_LT_PH_MM\0" + /* 18477 */ "SHRAV_PH_MM\0" + /* 18489 */ "SHLLV_PH_MM\0" + /* 18501 */ "REPLV_PH_MM\0" + /* 18513 */ "DPAQ_S_W_PH_MM\0" + /* 18528 */ "MULSAQ_S_W_PH_MM\0" + /* 18545 */ "DPSQ_S_W_PH_MM\0" + /* 18560 */ "SH_MM\0" + /* 18566 */ "EXTR_S_H_MM\0" + /* 18578 */ "EXTRV_S_H_MM\0" + /* 18591 */ "SYNCI_MM\0" + /* 18600 */ "DI_MM\0" + /* 18606 */ "TGEI_MM\0" + /* 18614 */ "TNEI_MM\0" + /* 18622 */ "PseudoMFHI_MM\0" + /* 18636 */ "PseudoMTLOHI_MM\0" + /* 18652 */ "MTHI_MM\0" + /* 18660 */ "TEQI_MM\0" + /* 18668 */ "TLTI_MM\0" + /* 18676 */ "TLBWI_MM\0" + /* 18685 */ "TLBGWI_MM\0" + /* 18695 */ "MOVF_I_MM\0" + /* 18705 */ "MOVN_I_MM\0" + /* 18715 */ "MOVT_I_MM\0" + /* 18725 */ "MOVZ_I_MM\0" + /* 18735 */ "J_MM\0" + /* 18740 */ "BREAK_MM\0" + /* 18749 */ "JAL_MM\0" + /* 18756 */ "BGEZAL_MM\0" + /* 18766 */ "BLTZAL_MM\0" + /* 18776 */ "MULEU_S_PH_QBL_MM\0" + /* 18794 */ "PRECEU_PH_QBL_MM\0" + /* 18811 */ "PRECEQU_PH_QBL_MM\0" + /* 18829 */ "DPAU_H_QBL_MM\0" + /* 18843 */ "DPSU_H_QBL_MM\0" + /* 18857 */ "MAQ_SA_W_PHL_MM\0" + /* 18873 */ "PRECEQ_W_PHL_MM\0" + /* 18889 */ "MAQ_S_W_PHL_MM\0" + /* 18904 */ "MULEQ_S_W_PHL_MM\0" + /* 18921 */ "TAILCALL_MM\0" + /* 18933 */ "HYPCALL_MM\0" + /* 18944 */ "SYSCALL_MM\0" + /* 18955 */ "SLL_MM\0" + /* 18962 */ "SRL_MM\0" + /* 18969 */ "MUL_MM\0" + /* 18976 */ "LWL_MM\0" + /* 18983 */ "SWL_MM\0" + /* 18990 */ "LWM_MM\0" + /* 18997 */ "SWM_MM\0" + /* 19004 */ "CLO_MM\0" + /* 19011 */ "PseudoMFLO_MM\0" + /* 19025 */ "SHILO_MM\0" + /* 19034 */ "MTLO_MM\0" + /* 19042 */ "TRAP_MM\0" + /* 19050 */ "SDBBP_MM\0" + /* 19059 */ "TLBP_MM\0" + /* 19067 */ "EXTPDP_MM\0" + /* 19077 */ "MOVEP_MM\0" + /* 19086 */ "TLBGP_MM\0" + /* 19095 */ "LWGP_MM\0" + /* 19103 */ "MTHLIP_MM\0" + /* 19113 */ "SSNOP_MM\0" + /* 19122 */ "ADDIUR1SP_MM\0" + /* 19135 */ "RDDSP_MM\0" + /* 19144 */ "WRDSP_MM\0" + /* 19153 */ "LWDSP_MM\0" + /* 19162 */ "SWDSP_MM\0" + /* 19171 */ "MSUB_DSP_MM\0" + /* 19183 */ "MADD_DSP_MM\0" + /* 19195 */ "MFHI_DSP_MM\0" + /* 19207 */ "MTHI_DSP_MM\0" + /* 19219 */ "MFLO_DSP_MM\0" + /* 19231 */ "MTLO_DSP_MM\0" + /* 19243 */ "MULT_DSP_MM\0" + /* 19255 */ "MSUBU_DSP_MM\0" + /* 19268 */ "MADDU_DSP_MM\0" + /* 19281 */ "MULTU_DSP_MM\0" + /* 19294 */ "ADDIUSP_MM\0" + /* 19305 */ "LWSP_MM\0" + /* 19313 */ "SWSP_MM\0" + /* 19321 */ "EXTP_MM\0" + /* 19329 */ "LWP_MM\0" + /* 19336 */ "SWP_MM\0" + /* 19343 */ "BEQ_MM\0" + /* 19350 */ "TEQ_MM\0" + /* 19357 */ "TLBR_MM\0" + /* 19365 */ "MULEU_S_PH_QBR_MM\0" + /* 19383 */ "PRECEU_PH_QBR_MM\0" + /* 19400 */ "PRECEQU_PH_QBR_MM\0" + /* 19418 */ "DPAU_H_QBR_MM\0" + /* 19432 */ "DPSU_H_QBR_MM\0" + /* 19446 */ "BAL_BR_MM\0" + /* 19456 */ "TLBGR_MM\0" + /* 19465 */ "MAQ_SA_W_PHR_MM\0" + /* 19481 */ "PRECEQ_W_PHR_MM\0" + /* 19497 */ "MAQ_S_W_PHR_MM\0" + /* 19512 */ "MULEQ_S_W_PHR_MM\0" + /* 19529 */ "JR_MM\0" + /* 19535 */ "JALR_MM\0" + /* 19543 */ "NOR_MM\0" + /* 19550 */ "XOR_MM\0" + /* 19557 */ "ROTR_MM\0" + /* 19565 */ "TLBWR_MM\0" + /* 19574 */ "TLBGWR_MM\0" + /* 19584 */ "RDHWR_MM\0" + /* 19593 */ "LWR_MM\0" + /* 19600 */ "SWR_MM\0" + /* 19607 */ "JALS_MM\0" + /* 19615 */ "BGEZALS_MM\0" + /* 19626 */ "BLTZALS_MM\0" + /* 19637 */ "INS_MM\0" + /* 19644 */ "JALRS_MM\0" + /* 19653 */ "LWXS_MM\0" + /* 19661 */ "CVT_D32_S_MM\0" + /* 19674 */ "CVT_D64_S_MM\0" + /* 19687 */ "FSUB_S_MM\0" + /* 19697 */ "NMSUB_S_MM\0" + /* 19708 */ "FADD_S_MM\0" + /* 19718 */ "NMADD_S_MM\0" + /* 19729 */ "C_NGE_S_MM\0" + /* 19740 */ "C_NGLE_S_MM\0" + /* 19752 */ "C_OLE_S_MM\0" + /* 19763 */ "C_ULE_S_MM\0" + /* 19774 */ "C_LE_S_MM\0" + /* 19784 */ "C_SF_S_MM\0" + /* 19794 */ "MOVF_S_MM\0" + /* 19804 */ "C_F_S_MM\0" + /* 19813 */ "FNEG_S_MM\0" + /* 19823 */ "MOVN_I_S_MM\0" + /* 19835 */ "MOVZ_I_S_MM\0" + /* 19847 */ "C_NGL_S_MM\0" + /* 19858 */ "FMUL_S_MM\0" + /* 19868 */ "CVT_L_S_MM\0" + /* 19879 */ "C_UN_S_MM\0" + /* 19889 */ "RECIP_S_MM\0" + /* 19900 */ "C_SEQ_S_MM\0" + /* 19911 */ "C_UEQ_S_MM\0" + /* 19922 */ "C_EQ_S_MM\0" + /* 19932 */ "FABS_S_MM\0" + /* 19942 */ "C_NGT_S_MM\0" + /* 19953 */ "C_OLT_S_MM\0" + /* 19964 */ "C_ULT_S_MM\0" + /* 19975 */ "C_LT_S_MM\0" + /* 19985 */ "FSQRT_S_MM\0" + /* 19996 */ "RSQRT_S_MM\0" + /* 20007 */ "MOVT_S_MM\0" + /* 20017 */ "FDIV_S_MM\0" + /* 20027 */ "FMOV_S_MM\0" + /* 20037 */ "TRUNC_W_S_MM\0" + /* 20050 */ "ROUND_W_S_MM\0" + /* 20063 */ "CEIL_W_S_MM\0" + /* 20075 */ "FLOOR_W_S_MM\0" + /* 20088 */ "CVT_W_S_MM\0" + /* 20099 */ "BC1T_MM\0" + /* 20107 */ "DERET_MM\0" + /* 20116 */ "WAIT_MM\0" + /* 20124 */ "SLT_MM\0" + /* 20131 */ "TLT_MM\0" + /* 20138 */ "PseudoMULT_MM\0" + /* 20152 */ "EXT_MM\0" + /* 20159 */ "PseudoMSUBU_MM\0" + /* 20174 */ "PseudoMADDU_MM\0" + /* 20189 */ "TGEU_MM\0" + /* 20197 */ "TGEIU_MM\0" + /* 20206 */ "TLTIU_MM\0" + /* 20215 */ "TLTU_MM\0" + /* 20223 */ "LWU_MM\0" + /* 20230 */ "SRAV_MM\0" + /* 20238 */ "BITREV_MM\0" + /* 20248 */ "SDIV_MM\0" + /* 20256 */ "UDIV_MM\0" + /* 20264 */ "SLLV_MM\0" + /* 20272 */ "SRLV_MM\0" + /* 20280 */ "TLBGINV_MM\0" + /* 20291 */ "SHILOV_MM\0" + /* 20301 */ "EXTPDPV_MM\0" + /* 20312 */ "EXTPV_MM\0" + /* 20321 */ "ROTRV_MM\0" + /* 20330 */ "INSV_MM\0" + /* 20338 */ "LW_MM\0" + /* 20344 */ "SW_MM\0" + /* 20350 */ "CVT_D32_W_MM\0" + /* 20363 */ "CVT_D64_W_MM\0" + /* 20376 */ "TRUNC_W_MM\0" + /* 20387 */ "ROUND_W_MM\0" + /* 20398 */ "PRECRQ_PH_W_MM\0" + /* 20413 */ "PRECRQ_RS_PH_W_MM\0" + /* 20431 */ "CEIL_W_MM\0" + /* 20441 */ "DPAQ_SA_L_W_MM\0" + /* 20456 */ "DPSQ_SA_L_W_MM\0" + /* 20471 */ "FLOOR_W_MM\0" + /* 20482 */ "EXTR_W_MM\0" + /* 20492 */ "SHRA_R_W_MM\0" + /* 20504 */ "EXTR_R_W_MM\0" + /* 20516 */ "SHRAV_R_W_MM\0" + /* 20529 */ "EXTRV_R_W_MM\0" + /* 20542 */ "EXTR_RS_W_MM\0" + /* 20555 */ "EXTRV_RS_W_MM\0" + /* 20569 */ "SHLL_S_W_MM\0" + /* 20581 */ "SUBQ_S_W_MM\0" + /* 20593 */ "ADDQ_S_W_MM\0" + /* 20605 */ "ABSQ_S_W_MM\0" + /* 20617 */ "CVT_S_W_MM\0" + /* 20628 */ "SHLLV_S_W_MM\0" + /* 20641 */ "EXTRV_W_MM\0" + /* 20652 */ "PREFX_MM\0" + /* 20661 */ "LHX_MM\0" + /* 20668 */ "JALX_MM\0" + /* 20676 */ "LBUX_MM\0" + /* 20684 */ "LWX_MM\0" + /* 20691 */ "BGEZ_MM\0" + /* 20699 */ "BLEZ_MM\0" + /* 20707 */ "CLZ_MM\0" + /* 20714 */ "BGTZ_MM\0" + /* 20722 */ "BLTZ_MM\0" + /* 20730 */ "PseudoIndirectBranch_MM\0" + /* 20754 */ "ADDi_MM\0" + /* 20762 */ "ANDi_MM\0" + /* 20770 */ "XORi_MM\0" + /* 20778 */ "SLTi_MM\0" + /* 20786 */ "LUi_MM\0" + /* 20793 */ "LBu_MM\0" + /* 20800 */ "SUBu_MM\0" + /* 20808 */ "ADDu_MM\0" + /* 20816 */ "LHu_MM\0" + /* 20823 */ "SLTu_MM\0" + /* 20831 */ "PseudoMULTu_MM\0" + /* 20846 */ "LEA_ADDiu_MM\0" + /* 20859 */ "SLTiu_MM\0" + /* 20868 */ "INLINEASM\0" + /* 20878 */ "DINSM\0" + /* 20884 */ "DEXTM\0" + /* 20890 */ "G_FMINIMUM\0" + /* 20901 */ "G_FMAXIMUM\0" + /* 20912 */ "G_FMINNUM\0" + /* 20922 */ "G_FMAXNUM\0" + /* 20932 */ "G_INTRINSIC_ROUNDEVEN\0" + /* 20954 */ "BALIGN\0" + /* 20961 */ "DALIGN\0" + /* 20968 */ "G_FCOPYSIGN\0" + /* 20980 */ "G_VECREDUCE_FMIN\0" + /* 20997 */ "G_VECREDUCE_SMIN\0" + /* 21014 */ "G_SMIN\0" + /* 21021 */ "G_VECREDUCE_UMIN\0" + /* 21038 */ "G_UMIN\0" + /* 21045 */ "G_ATOMICRMW_UMIN\0" + /* 21062 */ "G_ATOMICRMW_MIN\0" + /* 21078 */ "G_FSIN\0" + /* 21085 */ "DMFC2_OCTEON\0" + /* 21098 */ "DMTC2_OCTEON\0" + /* 21111 */ "CFI_INSTRUCTION\0" + /* 21127 */ "ADJCALLSTACKDOWN\0" + /* 21144 */ "G_SSUBO\0" + /* 21152 */ "G_USUBO\0" + /* 21160 */ "G_SADDO\0" + /* 21168 */ "G_UADDO\0" + /* 21176 */ "FEXP2_D_1_PSEUDO\0" + /* 21193 */ "FEXP2_W_1_PSEUDO\0" + /* 21210 */ "BPOSGE32_PSEUDO\0" + /* 21226 */ "INSERT_B_VIDX64_PSEUDO\0" + /* 21249 */ "INSERT_FD_VIDX64_PSEUDO\0" + /* 21273 */ "INSERT_D_VIDX64_PSEUDO\0" + /* 21296 */ "INSERT_H_VIDX64_PSEUDO\0" + /* 21319 */ "INSERT_FW_VIDX64_PSEUDO\0" + /* 21343 */ "INSERT_W_VIDX64_PSEUDO\0" + /* 21366 */ "SNZ_B_PSEUDO\0" + /* 21379 */ "SZ_B_PSEUDO\0" + /* 21391 */ "BSEL_FD_PSEUDO\0" + /* 21406 */ "FILL_FD_PSEUDO\0" + /* 21421 */ "INSERT_FD_PSEUDO\0" + /* 21438 */ "COPY_FD_PSEUDO\0" + /* 21453 */ "MSA_FP_EXTEND_D_PSEUDO\0" + /* 21476 */ "MSA_FP_ROUND_D_PSEUDO\0" + /* 21498 */ "BSEL_D_PSEUDO\0" + /* 21512 */ "AND_V_D_PSEUDO\0" + /* 21527 */ "NOR_V_D_PSEUDO\0" + /* 21542 */ "XOR_V_D_PSEUDO\0" + /* 21557 */ "SNZ_D_PSEUDO\0" + /* 21570 */ "SZ_D_PSEUDO\0" + /* 21582 */ "BSEL_H_PSEUDO\0" + /* 21596 */ "AND_V_H_PSEUDO\0" + /* 21611 */ "NOR_V_H_PSEUDO\0" + /* 21626 */ "XOR_V_H_PSEUDO\0" + /* 21641 */ "SNZ_H_PSEUDO\0" + /* 21654 */ "SZ_H_PSEUDO\0" + /* 21666 */ "SNZ_V_PSEUDO\0" + /* 21679 */ "SZ_V_PSEUDO\0" + /* 21691 */ "BSEL_FW_PSEUDO\0" + /* 21706 */ "FILL_FW_PSEUDO\0" + /* 21721 */ "INSERT_FW_PSEUDO\0" + /* 21738 */ "COPY_FW_PSEUDO\0" + /* 21753 */ "MSA_FP_EXTEND_W_PSEUDO\0" + /* 21776 */ "MSA_FP_ROUND_W_PSEUDO\0" + /* 21798 */ "BSEL_W_PSEUDO\0" + /* 21812 */ "AND_V_W_PSEUDO\0" + /* 21827 */ "NOR_V_W_PSEUDO\0" + /* 21842 */ "XOR_V_W_PSEUDO\0" + /* 21857 */ "SNZ_W_PSEUDO\0" + /* 21870 */ "SZ_W_PSEUDO\0" + /* 21882 */ "INSERT_B_VIDX_PSEUDO\0" + /* 21903 */ "INSERT_FD_VIDX_PSEUDO\0" + /* 21925 */ "INSERT_D_VIDX_PSEUDO\0" + /* 21946 */ "INSERT_H_VIDX_PSEUDO\0" + /* 21967 */ "INSERT_FW_VIDX_PSEUDO\0" + /* 21989 */ "INSERT_W_VIDX_PSEUDO\0" + /* 22010 */ "DCLO\0" + /* 22015 */ "PseudoMFLO\0" + /* 22026 */ "SHILO\0" + /* 22032 */ "MFTLO\0" + /* 22038 */ "MTLO\0" + /* 22043 */ "MTTLO\0" + /* 22049 */ "G_SMULO\0" + /* 22057 */ "G_UMULO\0" + /* 22065 */ "G_BZERO\0" + /* 22073 */ "STACKMAP\0" + /* 22082 */ "TRAP\0" + /* 22087 */ "G_BSWAP\0" + /* 22095 */ "DBITSWAP\0" + /* 22104 */ "SDBBP\0" + /* 22110 */ "TLBP\0" + /* 22115 */ "EXTPDP\0" + /* 22122 */ "G_SITOFP\0" + /* 22131 */ "G_UITOFP\0" + /* 22140 */ "TLBGP\0" + /* 22146 */ "MTHLIP\0" + /* 22153 */ "G_FCMP\0" + /* 22160 */ "G_ICMP\0" + /* 22167 */ "SSNOP\0" + /* 22173 */ "DPOP\0" + /* 22178 */ "G_CTPOP\0" + /* 22186 */ "PATCHABLE_OP\0" + /* 22199 */ "FAULTING_OP\0" + /* 22211 */ "LOAD_ACC64DSP\0" + /* 22225 */ "STORE_ACC64DSP\0" + /* 22240 */ "RDDSP\0" + /* 22246 */ "WRDSP\0" + /* 22252 */ "MFTDSP\0" + /* 22259 */ "MTTDSP\0" + /* 22266 */ "LWDSP\0" + /* 22272 */ "SWDSP\0" + /* 22278 */ "MSUB_DSP\0" + /* 22287 */ "MADD_DSP\0" + /* 22296 */ "LOAD_CCOND_DSP\0" + /* 22311 */ "STORE_CCOND_DSP\0" + /* 22327 */ "MFHI_DSP\0" + /* 22336 */ "PseudoMTLOHI_DSP\0" + /* 22353 */ "MTHI_DSP\0" + /* 22362 */ "MFLO_DSP\0" + /* 22371 */ "MTLO_DSP\0" + /* 22380 */ "MULT_DSP\0" + /* 22389 */ "MSUBU_DSP\0" + /* 22399 */ "MADDU_DSP\0" + /* 22409 */ "MULTU_DSP\0" + /* 22419 */ "JRADDIUSP\0" + /* 22429 */ "EXTP\0" + /* 22434 */ "ADJCALLSTACKUP\0" + /* 22449 */ "PREALLOCATED_SETUP\0" + /* 22468 */ "DVP\0" + /* 22472 */ "EVP\0" + /* 22476 */ "G_FEXP\0" + /* 22483 */ "BEQ\0" + /* 22487 */ "SEQ\0" + /* 22491 */ "TEQ\0" + /* 22495 */ "TLBR\0" + /* 22500 */ "MULEU_S_PH_QBR\0" + /* 22515 */ "PRECEU_PH_QBR\0" + /* 22529 */ "PRECEQU_PH_QBR\0" + /* 22544 */ "DPAU_H_QBR\0" + /* 22555 */ "DPSU_H_QBR\0" + /* 22566 */ "G_BR\0" + /* 22571 */ "BAL_BR\0" + /* 22578 */ "INLINEASM_BR\0" + /* 22591 */ "G_BLOCK_ADDR\0" + /* 22604 */ "LDR\0" + /* 22608 */ "SDR\0" + /* 22612 */ "PATCHABLE_FUNCTION_ENTER\0" + /* 22637 */ "G_READCYCLECOUNTER\0" + /* 22656 */ "G_READ_REGISTER\0" + /* 22672 */ "G_WRITE_REGISTER\0" + /* 22689 */ "TLBGR\0" + /* 22695 */ "LoadImmDoubleFGR\0" + /* 22712 */ "LoadImmSingleFGR\0" + /* 22729 */ "MAQ_SA_W_PHR\0" + /* 22742 */ "PRECEQ_W_PHR\0" + /* 22755 */ "MAQ_S_W_PHR\0" + /* 22767 */ "MULEQ_S_W_PHR\0" + /* 22781 */ "G_ASHR\0" + /* 22788 */ "G_FSHR\0" + /* 22795 */ "G_LSHR\0" + /* 22802 */ "JR\0" + /* 22805 */ "JALR\0" + /* 22810 */ "NOR\0" + /* 22814 */ "G_FFLOOR\0" + /* 22823 */ "DROR\0" + /* 22828 */ "G_BUILD_VECTOR\0" + /* 22843 */ "G_SHUFFLE_VECTOR\0" + /* 22860 */ "G_VECREDUCE_XOR\0" + /* 22876 */ "G_XOR\0" + /* 22882 */ "G_ATOMICRMW_XOR\0" + /* 22898 */ "G_VECREDUCE_OR\0" + /* 22913 */ "G_OR\0" + /* 22918 */ "G_ATOMICRMW_OR\0" + /* 22933 */ "MFTGPR\0" + /* 22940 */ "MTTGPR\0" + /* 22947 */ "LoadImmDoubleGPR\0" + /* 22964 */ "LoadImmSingleGPR\0" + /* 22981 */ "MFTR\0" + /* 22986 */ "DROTR\0" + /* 22992 */ "G_ROTR\0" + /* 22999 */ "G_INTTOPTR\0" + /* 23010 */ "MTTR\0" + /* 23015 */ "TLBWR\0" + /* 23021 */ "TLBGWR\0" + /* 23028 */ "RDHWR\0" + /* 23034 */ "LWR\0" + /* 23038 */ "SWR\0" + /* 23042 */ "G_FABS\0" + /* 23049 */ "G_ABS\0" + /* 23055 */ "G_UNMERGE_VALUES\0" + /* 23072 */ "G_MERGE_VALUES\0" + /* 23087 */ "CINS\0" + /* 23092 */ "DINS\0" + /* 23097 */ "G_FCOS\0" + /* 23104 */ "G_CONCAT_VECTORS\0" + /* 23121 */ "COPY_TO_REGCLASS\0" + /* 23138 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" + /* 23168 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" + /* 23195 */ "EXTS\0" + /* 23200 */ "CVT_D32_S\0" + /* 23210 */ "CVT_D64_S\0" + /* 23220 */ "MOVN_I64_S\0" + /* 23231 */ "MOVZ_I64_S\0" + /* 23242 */ "MINA_S\0" + /* 23249 */ "MAXA_S\0" + /* 23256 */ "FSUB_S\0" + /* 23263 */ "NMSUB_S\0" + /* 23271 */ "FADD_S\0" + /* 23278 */ "NMADD_S\0" + /* 23286 */ "C_NGE_S\0" + /* 23294 */ "C_NGLE_S\0" + /* 23303 */ "C_OLE_S\0" + /* 23311 */ "CMP_SLE_S\0" + /* 23321 */ "CMP_SULE_S\0" + /* 23332 */ "C_ULE_S\0" + /* 23340 */ "CMP_ULE_S\0" + /* 23350 */ "C_LE_S\0" + /* 23357 */ "CMP_LE_S\0" + /* 23366 */ "CMP_SAF_S\0" + /* 23376 */ "MSUBF_S\0" + /* 23384 */ "MADDF_S\0" + /* 23392 */ "C_SF_S\0" + /* 23399 */ "MOVF_S\0" + /* 23406 */ "C_F_S\0" + /* 23412 */ "PseudoSELECTFP_F_S\0" + /* 23431 */ "CMP_F_S\0" + /* 23439 */ "FNEG_S\0" + /* 23446 */ "MOVN_I_S\0" + /* 23455 */ "MOVZ_I_S\0" + /* 23464 */ "SEL_S\0" + /* 23470 */ "C_NGL_S\0" + /* 23478 */ "FMUL_S\0" + /* 23485 */ "TRUNC_L_S\0" + /* 23495 */ "ROUND_L_S\0" + /* 23505 */ "CEIL_L_S\0" + /* 23514 */ "FLOOR_L_S\0" + /* 23524 */ "CVT_L_S\0" + /* 23532 */ "MIN_S\0" + /* 23538 */ "CMP_SUN_S\0" + /* 23548 */ "C_UN_S\0" + /* 23555 */ "CMP_UN_S\0" + /* 23564 */ "RECIP_S\0" + /* 23572 */ "C_SEQ_S\0" + /* 23580 */ "CMP_SEQ_S\0" + /* 23590 */ "CMP_SUEQ_S\0" + /* 23601 */ "C_UEQ_S\0" + /* 23609 */ "CMP_UEQ_S\0" + /* 23619 */ "C_EQ_S\0" + /* 23626 */ "CMP_EQ_S\0" + /* 23635 */ "FABS_S\0" + /* 23642 */ "CLASS_S\0" + /* 23650 */ "PseudoSELECT_S\0" + /* 23665 */ "C_NGT_S\0" + /* 23673 */ "C_OLT_S\0" + /* 23681 */ "CMP_SLT_S\0" + /* 23691 */ "CMP_SULT_S\0" + /* 23702 */ "C_ULT_S\0" + /* 23710 */ "CMP_ULT_S\0" + /* 23720 */ "C_LT_S\0" + /* 23727 */ "CMP_LT_S\0" + /* 23736 */ "RINT_S\0" + /* 23743 */ "FSQRT_S\0" + /* 23751 */ "RSQRT_S\0" + /* 23759 */ "MOVT_S\0" + /* 23766 */ "PseudoSELECTFP_T_S\0" + /* 23785 */ "FDIV_S\0" + /* 23792 */ "FMOV_S\0" + /* 23799 */ "PseudoTRUNC_W_S\0" + /* 23815 */ "ROUND_W_S\0" + /* 23825 */ "CEIL_W_S\0" + /* 23834 */ "FLOOR_W_S\0" + /* 23844 */ "CVT_W_S\0" + /* 23852 */ "MAX_S\0" + /* 23858 */ "SELNEZ_S\0" + /* 23867 */ "SELEQZ_S\0" + /* 23876 */ "BC0T\0" + /* 23881 */ "BC1T\0" + /* 23886 */ "BC2T\0" + /* 23891 */ "BC3T\0" + /* 23896 */ "G_SSUBSAT\0" + /* 23906 */ "G_USUBSAT\0" + /* 23916 */ "G_SADDSAT\0" + /* 23926 */ "G_UADDSAT\0" + /* 23936 */ "G_SSHLSAT\0" + /* 23946 */ "G_USHLSAT\0" + /* 23956 */ "G_SMULFIXSAT\0" + /* 23969 */ "G_UMULFIXSAT\0" + /* 23982 */ "G_SDIVFIXSAT\0" + /* 23995 */ "G_UDIVFIXSAT\0" + /* 24008 */ "G_EXTRACT\0" + /* 24018 */ "G_SELECT\0" + /* 24027 */ "G_BRINDIRECT\0" + /* 24040 */ "DERET\0" + /* 24046 */ "PATCHABLE_RET\0" + /* 24060 */ "G_MEMSET\0" + /* 24069 */ "BGT\0" + /* 24073 */ "WAIT\0" + /* 24078 */ "PATCHABLE_FUNCTION_EXIT\0" + /* 24102 */ "G_BRJT\0" + /* 24109 */ "BLT\0" + /* 24113 */ "G_EXTRACT_VECTOR_ELT\0" + /* 24134 */ "G_INSERT_VECTOR_ELT\0" + /* 24154 */ "SLT\0" + /* 24158 */ "TLT\0" + /* 24162 */ "PseudoDMULT\0" + /* 24174 */ "PseudoMULT\0" + /* 24185 */ "DMT\0" + /* 24189 */ "EMT\0" + /* 24193 */ "G_FCONSTANT\0" + /* 24205 */ "G_CONSTANT\0" + /* 24216 */ "STATEPOINT\0" + /* 24227 */ "PATCHPOINT\0" + /* 24238 */ "G_PTRTOINT\0" + /* 24249 */ "G_FRINT\0" + /* 24257 */ "G_INTRINSIC_LRINT\0" + /* 24275 */ "G_FNEARBYINT\0" + /* 24288 */ "G_VASTART\0" + /* 24298 */ "LIFETIME_START\0" + /* 24313 */ "G_INSERT\0" + /* 24322 */ "G_FSQRT\0" + /* 24330 */ "G_STRICT_FSQRT\0" + /* 24345 */ "G_BITCAST\0" + /* 24355 */ "G_ADDRSPACE_CAST\0" + /* 24372 */ "DBG_VALUE_LIST\0" + /* 24387 */ "GINVT\0" + /* 24393 */ "DEXT\0" + /* 24398 */ "G_FPEXT\0" + /* 24406 */ "G_SEXT\0" + /* 24413 */ "G_ASSERT_SEXT\0" + /* 24427 */ "G_ANYEXT\0" + /* 24436 */ "G_ZEXT\0" + /* 24443 */ "G_ASSERT_ZEXT\0" + /* 24457 */ "PseudoMSUBU\0" + /* 24469 */ "PseudoMADDU\0" + /* 24481 */ "DMODU\0" + /* 24487 */ "BGEU\0" + /* 24492 */ "SGEU\0" + /* 24497 */ "TGEU\0" + /* 24502 */ "BLEU\0" + /* 24507 */ "SLEU\0" + /* 24512 */ "DMUHU\0" + /* 24518 */ "TGEIU\0" + /* 24524 */ "TTLTIU\0" + /* 24531 */ "V3MULU\0" + /* 24538 */ "DMULU\0" + /* 24544 */ "VMULU\0" + /* 24550 */ "DINSU\0" + /* 24556 */ "BGTU\0" + /* 24561 */ "BLTU\0" + /* 24566 */ "TLTU\0" + /* 24571 */ "DEXTU\0" + /* 24577 */ "DDIVU\0" + /* 24583 */ "DSRAV\0" + /* 24589 */ "BITREV\0" + /* 24596 */ "DDIV\0" + /* 24601 */ "G_FDIV\0" + /* 24608 */ "G_STRICT_FDIV\0" + /* 24622 */ "PseudoDSDIV\0" + /* 24634 */ "G_SDIV\0" + /* 24641 */ "PseudoSDIV\0" + /* 24652 */ "PseudoDUDIV\0" + /* 24664 */ "G_UDIV\0" + /* 24671 */ "PseudoUDIV\0" + /* 24682 */ "DSLLV\0" + /* 24688 */ "DSRLV\0" + /* 24694 */ "TLBINV\0" + /* 24701 */ "TLBGINV\0" + /* 24709 */ "SHILOV\0" + /* 24716 */ "EXTPDPV\0" + /* 24724 */ "EXTPV\0" + /* 24730 */ "DROTRV\0" + /* 24737 */ "INSV\0" + /* 24742 */ "AND_V\0" + /* 24748 */ "MOVE_V\0" + /* 24755 */ "BSEL_V\0" + /* 24762 */ "NOR_V\0" + /* 24768 */ "XOR_V\0" + /* 24774 */ "BZ_V\0" + /* 24779 */ "BMZ_V\0" + /* 24785 */ "BNZ_V\0" + /* 24791 */ "BMNZ_V\0" + /* 24798 */ "CRC32W\0" + /* 24805 */ "CRC32CW\0" + /* 24813 */ "LW\0" + /* 24816 */ "G_FPOW\0" + /* 24823 */ "SW\0" + /* 24826 */ "PseudoCVT_D32_W\0" + /* 24842 */ "FLOG2_W\0" + /* 24850 */ "FEXP2_W\0" + /* 24858 */ "PseudoCVT_D64_W\0" + /* 24874 */ "SRA_W\0" + /* 24880 */ "ADD_A_W\0" + /* 24888 */ "FMIN_A_W\0" + /* 24897 */ "ADDS_A_W\0" + /* 24906 */ "FMAX_A_W\0" + /* 24915 */ "FSUB_W\0" + /* 24922 */ "FMSUB_W\0" + /* 24930 */ "NLOC_W\0" + /* 24937 */ "NLZC_W\0" + /* 24944 */ "FADD_W\0" + /* 24951 */ "FMADD_W\0" + /* 24959 */ "SLD_W\0" + /* 24965 */ "PCKOD_W\0" + /* 24973 */ "ILVOD_W\0" + /* 24981 */ "FCLE_W\0" + /* 24988 */ "FSLE_W\0" + /* 24995 */ "FCULE_W\0" + /* 25003 */ "FSULE_W\0" + /* 25011 */ "FCNE_W\0" + /* 25018 */ "FSNE_W\0" + /* 25025 */ "FCUNE_W\0" + /* 25033 */ "FSUNE_W\0" + /* 25041 */ "INSVE_W\0" + /* 25049 */ "FCAF_W\0" + /* 25056 */ "FSAF_W\0" + /* 25063 */ "VSHF_W\0" + /* 25070 */ "BNEG_W\0" + /* 25077 */ "PRECR_SRA_PH_W\0" + /* 25092 */ "PRECRQ_PH_W\0" + /* 25104 */ "PRECR_SRA_R_PH_W\0" + /* 25121 */ "PRECRQ_RS_PH_W\0" + /* 25136 */ "SUBQH_W\0" + /* 25144 */ "ADDQH_W\0" + /* 25152 */ "SRAI_W\0" + /* 25159 */ "SLDI_W\0" + /* 25166 */ "BNEGI_W\0" + /* 25174 */ "SLLI_W\0" + /* 25181 */ "SRLI_W\0" + /* 25188 */ "BINSLI_W\0" + /* 25197 */ "CEQI_W\0" + /* 25204 */ "SRARI_W\0" + /* 25212 */ "BCLRI_W\0" + /* 25220 */ "SRLRI_W\0" + /* 25228 */ "BINSRI_W\0" + /* 25237 */ "SPLATI_W\0" + /* 25246 */ "BSETI_W\0" + /* 25254 */ "SUBVI_W\0" + /* 25262 */ "ADDVI_W\0" + /* 25270 */ "FILL_W\0" + /* 25277 */ "SLL_W\0" + /* 25283 */ "FEXUPL_W\0" + /* 25292 */ "FFQL_W\0" + /* 25299 */ "SRL_W\0" + /* 25305 */ "BINSL_W\0" + /* 25313 */ "FMUL_W\0" + /* 25320 */ "ILVL_W\0" + /* 25327 */ "DPAQ_SA_L_W\0" + /* 25339 */ "DPSQ_SA_L_W\0" + /* 25351 */ "FMIN_W\0" + /* 25358 */ "FCUN_W\0" + /* 25365 */ "FSUN_W\0" + /* 25372 */ "FEXDO_W\0" + /* 25380 */ "FRCP_W\0" + /* 25387 */ "FCEQ_W\0" + /* 25394 */ "FSEQ_W\0" + /* 25401 */ "FCUEQ_W\0" + /* 25409 */ "FSUEQ_W\0" + /* 25417 */ "FTQ_W\0" + /* 25423 */ "MSUB_Q_W\0" + /* 25432 */ "MADD_Q_W\0" + /* 25441 */ "MUL_Q_W\0" + /* 25449 */ "MSUBR_Q_W\0" + /* 25459 */ "MADDR_Q_W\0" + /* 25469 */ "MULR_Q_W\0" + /* 25478 */ "SRAR_W\0" + /* 25485 */ "LDR_W\0" + /* 25491 */ "BCLR_W\0" + /* 25498 */ "SRLR_W\0" + /* 25505 */ "FCOR_W\0" + /* 25512 */ "FSOR_W\0" + /* 25519 */ "FEXUPR_W\0" + /* 25528 */ "FFQR_W\0" + /* 25535 */ "BINSR_W\0" + /* 25543 */ "STR_W\0" + /* 25549 */ "EXTR_W\0" + /* 25556 */ "ILVR_W\0" + /* 25563 */ "SHRA_R_W\0" + /* 25572 */ "SUBQH_R_W\0" + /* 25582 */ "ADDQH_R_W\0" + /* 25592 */ "EXTR_R_W\0" + /* 25601 */ "SHRAV_R_W\0" + /* 25611 */ "EXTRV_R_W\0" + /* 25621 */ "FABS_W\0" + /* 25628 */ "MULQ_RS_W\0" + /* 25638 */ "EXTR_RS_W\0" + /* 25648 */ "EXTRV_RS_W\0" + /* 25659 */ "FCLASS_W\0" + /* 25668 */ "ASUB_S_W\0" + /* 25677 */ "HSUB_S_W\0" + /* 25686 */ "DPSUB_S_W\0" + /* 25696 */ "FTRUNC_S_W\0" + /* 25707 */ "HADD_S_W\0" + /* 25716 */ "DPADD_S_W\0" + /* 25726 */ "MOD_S_W\0" + /* 25734 */ "CLE_S_W\0" + /* 25742 */ "AVE_S_W\0" + /* 25750 */ "CLEI_S_W\0" + /* 25759 */ "MINI_S_W\0" + /* 25768 */ "CLTI_S_W\0" + /* 25777 */ "MAXI_S_W\0" + /* 25786 */ "SHLL_S_W\0" + /* 25795 */ "MIN_S_W\0" + /* 25803 */ "DOTP_S_W\0" + /* 25812 */ "SUBQ_S_W\0" + /* 25821 */ "ADDQ_S_W\0" + /* 25830 */ "MULQ_S_W\0" + /* 25839 */ "ABSQ_S_W\0" + /* 25848 */ "AVER_S_W\0" + /* 25857 */ "SUBS_S_W\0" + /* 25866 */ "ADDS_S_W\0" + /* 25875 */ "SAT_S_W\0" + /* 25883 */ "CLT_S_W\0" + /* 25891 */ "FFINT_S_W\0" + /* 25901 */ "FTINT_S_W\0" + /* 25911 */ "PseudoCVT_S_W\0" + /* 25925 */ "SUBSUU_S_W\0" + /* 25936 */ "DIV_S_W\0" + /* 25944 */ "SHLLV_S_W\0" + /* 25954 */ "MAX_S_W\0" + /* 25962 */ "COPY_S_W\0" + /* 25971 */ "SPLAT_W\0" + /* 25979 */ "BSET_W\0" + /* 25986 */ "FCLT_W\0" + /* 25993 */ "FSLT_W\0" + /* 26000 */ "FCULT_W\0" + /* 26008 */ "FSULT_W\0" + /* 26016 */ "PCNT_W\0" + /* 26023 */ "FRINT_W\0" + /* 26031 */ "INSERT_W\0" + /* 26040 */ "FSQRT_W\0" + /* 26048 */ "FRSQRT_W\0" + /* 26057 */ "ST_W\0" + /* 26062 */ "ASUB_U_W\0" + /* 26071 */ "HSUB_U_W\0" + /* 26080 */ "DPSUB_U_W\0" + /* 26090 */ "FTRUNC_U_W\0" + /* 26101 */ "HADD_U_W\0" + /* 26110 */ "DPADD_U_W\0" + /* 26120 */ "MOD_U_W\0" + /* 26128 */ "CLE_U_W\0" + /* 26136 */ "AVE_U_W\0" + /* 26144 */ "CLEI_U_W\0" + /* 26153 */ "MINI_U_W\0" + /* 26162 */ "CLTI_U_W\0" + /* 26171 */ "MAXI_U_W\0" + /* 26180 */ "MIN_U_W\0" + /* 26188 */ "DOTP_U_W\0" + /* 26197 */ "AVER_U_W\0" + /* 26206 */ "SUBS_U_W\0" + /* 26215 */ "ADDS_U_W\0" + /* 26224 */ "SUBSUS_U_W\0" + /* 26235 */ "SAT_U_W\0" + /* 26243 */ "CLT_U_W\0" + /* 26251 */ "FFINT_U_W\0" + /* 26261 */ "FTINT_U_W\0" + /* 26271 */ "DIV_U_W\0" + /* 26279 */ "MAX_U_W\0" + /* 26287 */ "COPY_U_W\0" + /* 26296 */ "MSUBV_W\0" + /* 26304 */ "MADDV_W\0" + /* 26312 */ "PCKEV_W\0" + /* 26320 */ "ILVEV_W\0" + /* 26328 */ "FDIV_W\0" + /* 26335 */ "MULV_W\0" + /* 26342 */ "EXTRV_W\0" + /* 26350 */ "FMAX_W\0" + /* 26357 */ "BZ_W\0" + /* 26362 */ "BNZ_W\0" + /* 26368 */ "G_VECREDUCE_FMAX\0" + /* 26385 */ "G_VECREDUCE_SMAX\0" + /* 26402 */ "G_SMAX\0" + /* 26409 */ "G_VECREDUCE_UMAX\0" + /* 26426 */ "G_UMAX\0" + /* 26433 */ "G_ATOMICRMW_UMAX\0" + /* 26450 */ "G_ATOMICRMW_MAX\0" + /* 26466 */ "MFTACX\0" + /* 26473 */ "MTTACX\0" + /* 26480 */ "G_FRAME_INDEX\0" + /* 26494 */ "G_SBFX\0" + /* 26501 */ "G_UBFX\0" + /* 26508 */ "LHX\0" + /* 26512 */ "G_SMULFIX\0" + /* 26522 */ "G_UMULFIX\0" + /* 26532 */ "G_SDIVFIX\0" + /* 26542 */ "G_UDIVFIX\0" + /* 26552 */ "JALX\0" + /* 26557 */ "LBUX\0" + /* 26562 */ "LWX\0" + /* 26566 */ "G_MEMCPY\0" + /* 26575 */ "COPY\0" + /* 26580 */ "CONSTPOOL_ENTRY\0" + /* 26596 */ "BGEZ\0" + /* 26601 */ "BLEZ\0" + /* 26606 */ "BC1NEZ\0" + /* 26613 */ "BC2NEZ\0" + /* 26620 */ "SELNEZ\0" + /* 26627 */ "DCLZ\0" + /* 26632 */ "G_CTLZ\0" + /* 26639 */ "BC1EQZ\0" + /* 26646 */ "BC2EQZ\0" + /* 26653 */ "SELEQZ\0" + /* 26660 */ "BGTZ\0" + /* 26665 */ "BLTZ\0" + /* 26670 */ "G_CTTZ\0" + /* 26677 */ "SelBneZ\0" + /* 26685 */ "SelBeqZ\0" + /* 26693 */ "JalOneReg\0" + /* 26703 */ "JalTwoReg\0" + /* 26713 */ "PseudoIndirectHazardBranch\0" + /* 26740 */ "PseudoIndirectBranch\0" + /* 26761 */ "Ulh\0" + /* 26765 */ "Ush\0" + /* 26769 */ "DADDi\0" + /* 26775 */ "ANDi\0" + /* 26780 */ "SNEi\0" + /* 26785 */ "SEQi\0" + /* 26790 */ "XORi\0" + /* 26795 */ "SLTi\0" + /* 26800 */ "LONG_BRANCH_LUi\0" + /* 26816 */ "SelTBtneZCmpi\0" + /* 26830 */ "SelTBteqZCmpi\0" + /* 26844 */ "SelTBtneZSlti\0" + /* 26858 */ "SelTBteqZSlti\0" + /* 26872 */ "SGEImm\0" + /* 26879 */ "SLEImm\0" + /* 26886 */ "DROLImm\0" + /* 26894 */ "NORImm\0" + /* 26901 */ "DRORImm\0" + /* 26909 */ "SGTImm\0" + /* 26916 */ "SGEUImm\0" + /* 26924 */ "SLEUImm\0" + /* 26932 */ "SGTUImm\0" + /* 26940 */ "BneImm\0" + /* 26947 */ "BeqImm\0" + /* 26954 */ "PseudoReturn\0" + /* 26967 */ "JALRHB64Pseudo\0" + /* 26982 */ "JALR64Pseudo\0" + /* 26995 */ "JALRHBPseudo\0" + /* 27008 */ "JALRPseudo\0" + /* 27019 */ "B_MMR6_Pseudo\0" + /* 27033 */ "B_MM_Pseudo\0" + /* 27045 */ "SDIV_MM_Pseudo\0" + /* 27060 */ "UDIV_MM_Pseudo\0" + /* 27075 */ "LDMacro\0" + /* 27083 */ "SDMacro\0" + /* 27091 */ "SNEMacro\0" + /* 27100 */ "SNEIMacro\0" + /* 27110 */ "SEQIMacro\0" + /* 27120 */ "DSRemIMacro\0" + /* 27132 */ "DURemIMacro\0" + /* 27144 */ "DSDivIMacro\0" + /* 27156 */ "DUDivIMacro\0" + /* 27168 */ "DMULMacro\0" + /* 27178 */ "DMULOMacro\0" + /* 27189 */ "SEQMacro\0" + /* 27198 */ "ABSMacro\0" + /* 27207 */ "DMULOUMacro\0" + /* 27219 */ "DSRemMacro\0" + /* 27230 */ "DURemMacro\0" + /* 27241 */ "BGEImmMacro\0" + /* 27253 */ "BLEImmMacro\0" + /* 27265 */ "BGELImmMacro\0" + /* 27278 */ "BLELImmMacro\0" + /* 27291 */ "BNELImmMacro\0" + /* 27304 */ "BEQLImmMacro\0" + /* 27317 */ "BGTLImmMacro\0" + /* 27330 */ "BLTLImmMacro\0" + /* 27343 */ "BGEULImmMacro\0" + /* 27357 */ "BLEULImmMacro\0" + /* 27371 */ "DMULImmMacro\0" + /* 27384 */ "BGTULImmMacro\0" + /* 27398 */ "BLTULImmMacro\0" + /* 27412 */ "BGTImmMacro\0" + /* 27424 */ "BLTImmMacro\0" + /* 27436 */ "BGEUImmMacro\0" + /* 27449 */ "BLEUImmMacro\0" + /* 27462 */ "BGTUImmMacro\0" + /* 27475 */ "BLTUImmMacro\0" + /* 27488 */ "DSDivMacro\0" + /* 27499 */ "DUDivMacro\0" + /* 27510 */ "LONG_BRANCH_LUi2Op\0" + /* 27529 */ "LONG_BRANCH_DADDiu2Op\0" + /* 27551 */ "LONG_BRANCH_ADDiu2Op\0" + /* 27572 */ "SelTBtneZCmp\0" + /* 27585 */ "SelTBteqZCmp\0" + /* 27598 */ "SaaAddr\0" + /* 27606 */ "SaadAddr\0" + /* 27615 */ "ERet\0" + /* 27620 */ "SelTBtneZSlt\0" + /* 27633 */ "SelTBteqZSlt\0" + /* 27646 */ "LBu\0" + /* 27650 */ "DSUBu\0" + /* 27656 */ "BADDu\0" + /* 27662 */ "DADDu\0" + /* 27668 */ "LHu\0" + /* 27672 */ "SLTu\0" + /* 27677 */ "PseudoDMULTu\0" + /* 27690 */ "PseudoMULTu\0" + /* 27702 */ "LWu\0" + /* 27706 */ "Ulhu\0" + /* 27711 */ "LONG_BRANCH_DADDiu\0" + /* 27730 */ "LEA_ADDiu\0" + /* 27740 */ "LONG_BRANCH_ADDiu\0" + /* 27758 */ "SLTiu\0" + /* 27764 */ "SelTBtneZSltiu\0" + /* 27779 */ "SelTBteqZSltiu\0" + /* 27794 */ "SelTBtneZSltu\0" + /* 27808 */ "SelTBteqZSltu\0" + /* 27822 */ "Ulw\0" + /* 27826 */ "Usw\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern const unsigned MipsInstrNameIndices[] = { + 15299U, 20868U, 22578U, 21111U, 15647U, 15628U, 15656U, 15920U, 13666U, + 13681U, 13546U, 13720U, 23121U, 13410U, 24372U, 13564U, 15295U, 15637U, + 13159U, 26575U, 13281U, 24298U, 11631U, 13106U, 13147U, 22073U, 15892U, + 24227U, 11695U, 22449U, 13783U, 24216U, 13334U, 22199U, 22186U, 22612U, + 24046U, 24078U, 15824U, 15871U, 15844U, 15688U, 24413U, 24443U, 11514U, + 10247U, 16072U, 24634U, 24664U, 16173U, 16180U, 16187U, 16197U, 11594U, + 22913U, 22876U, 13544U, 15297U, 26480U, 13420U, 24008U, 23055U, 24313U, + 23072U, 22828U, 11133U, 23104U, 24238U, 22999U, 24345U, 13453U, 11107U, + 11672U, 24257U, 20932U, 22637U, 11387U, 11331U, 11361U, 11372U, 11312U, + 11342U, 13373U, 13357U, 23138U, 13734U, 13751U, 11530U, 10253U, 11600U, + 11561U, 22918U, 22882U, 26450U, 21062U, 26433U, 21045U, 11470U, 10219U, + 13139U, 11644U, 24027U, 11019U, 23168U, 24427U, 11125U, 24205U, 24193U, + 24288U, 13775U, 24406U, 13707U, 24436U, 15785U, 22795U, 22781U, 15778U, + 22788U, 22992U, 15973U, 22160U, 22153U, 24018U, 21168U, 13184U, 21152U, + 13131U, 21160U, 13176U, 21144U, 13123U, 22057U, 22049U, 13837U, 13829U, + 23926U, 23916U, 23906U, 23896U, 23946U, 23936U, 26512U, 26522U, 23956U, + 23969U, 26532U, 26542U, 23982U, 23995U, 11428U, 10198U, 16014U, 8452U, + 11305U, 24601U, 16152U, 24816U, 15377U, 22476U, 1181U, 13768U, 1163U, + 0U, 13595U, 24398U, 11097U, 15325U, 15349U, 22122U, 22131U, 23042U, + 20968U, 13462U, 20912U, 20922U, 13192U, 13207U, 20890U, 20901U, 11520U, + 15522U, 21014U, 26402U, 21038U, 26426U, 23049U, 11663U, 11653U, 22566U, + 24102U, 24134U, 24113U, 22843U, 26670U, 13526U, 26632U, 13508U, 22178U, + 22087U, 13391U, 15791U, 23097U, 21078U, 24322U, 22814U, 24249U, 24275U, + 24355U, 22591U, 13268U, 11159U, 11456U, 10205U, 16042U, 24608U, 16159U, + 8458U, 24330U, 22656U, 22672U, 26566U, 13310U, 13435U, 24060U, 22065U, + 11435U, 16021U, 11411U, 15997U, 26368U, 20980U, 11498U, 16056U, 11578U, + 22898U, 22860U, 26385U, 20997U, 26409U, 21021U, 26494U, 26501U, 27198U, + 21127U, 22434U, 21512U, 21596U, 21812U, 4016U, 9338U, 860U, 8694U, + 3041U, 9016U, 8322U, 9653U, 3898U, 9178U, 742U, 8534U, 2871U, + 8856U, 8210U, 9499U, 3939U, 9233U, 783U, 8589U, 2912U, 8911U, + 8249U, 9552U, 4096U, 9446U, 940U, 8802U, 3187U, 9124U, 8398U, + 9757U, 3980U, 9288U, 824U, 8644U, 3005U, 8966U, 8288U, 9605U, + 3918U, 9205U, 762U, 8561U, 2891U, 8883U, 8229U, 9525U, 4056U, + 9392U, 900U, 8748U, 3081U, 9070U, 8360U, 9705U, 3878U, 9151U, + 722U, 8507U, 2851U, 8829U, 8191U, 9473U, 4075U, 9418U, 919U, + 8774U, 3166U, 9096U, 8378U, 9730U, 3959U, 9260U, 803U, 8616U, + 2984U, 8938U, 8268U, 9578U, 4036U, 9365U, 880U, 8721U, 3061U, + 9043U, 8341U, 9679U, 4000U, 9315U, 844U, 8671U, 3025U, 8993U, + 8307U, 9631U, 9813U, 22571U, 19446U, 27304U, 13235U, 27241U, 15673U, + 27265U, 24487U, 27436U, 15980U, 27343U, 24069U, 27412U, 15963U, 27317U, + 24556U, 27462U, 16078U, 27384U, 13277U, 27253U, 15678U, 27278U, 24502U, + 27449U, 15986U, 27357U, 24109U, 27424U, 15968U, 27330U, 24561U, 27475U, + 16084U, 27398U, 27291U, 21210U, 21498U, 21391U, 21691U, 21582U, 21798U, + 17638U, 27019U, 27033U, 26947U, 26940U, 4620U, 4167U, 4648U, 4197U, + 4678U, 4709U, 4606U, 4152U, 4634U, 4182U, 4662U, 4694U, 2729U, + 3499U, 122U, 26580U, 21438U, 21738U, 140U, 1120U, 27371U, 27168U, + 27178U, 27207U, 15930U, 26886U, 22823U, 26901U, 27144U, 27488U, 27120U, + 27219U, 27156U, 27499U, 27132U, 27230U, 27615U, 2742U, 3515U, 12398U, + 25621U, 21176U, 21193U, 21406U, 21706U, 4767U, 21226U, 21882U, 21273U, + 21925U, 21421U, 21249U, 21903U, 21721U, 21319U, 21967U, 21296U, 21946U, + 21343U, 21989U, 26982U, 26967U, 26995U, 27008U, 6904U, 26693U, 26703U, + 27075U, 12327U, 25485U, 3864U, 8166U, 2020U, 22211U, 22296U, 27740U, + 27551U, 27711U, 27529U, 26800U, 27510U, 3545U, 18990U, 1088U, 3755U, + 1055U, 3567U, 1078U, 3745U, 22695U, 1035U, 22947U, 22712U, 22964U, + 1118U, 26466U, 43U, 128U, 22252U, 22933U, 103U, 15303U, 22032U, + 1102U, 3784U, 21453U, 21753U, 21476U, 21776U, 26473U, 55U, 146U, + 22259U, 22940U, 110U, 15314U, 22043U, 27372U, 27179U, 27208U, 5027U, + 5160U, 5059U, 5212U, 22169U, 26894U, 3678U, 21527U, 21611U, 21827U, + 21528U, 21612U, 21828U, 9993U, 9895U, 10108U, 13999U, 13894U, 14159U, + 24826U, 16122U, 24858U, 16138U, 25911U, 24162U, 27677U, 24622U, 24652U, + 15451U, 3100U, 26740U, 3610U, 5272U, 8143U, 20730U, 7937U, 26713U, + 3581U, 5242U, 8115U, 11487U, 24469U, 20174U, 17970U, 15271U, 2790U, + 18622U, 22015U, 3235U, 19011U, 10236U, 24457U, 20159U, 17901U, 15282U, + 2803U, 22336U, 18636U, 24174U, 20138U, 27690U, 20831U, 13928U, 9930U, + 26954U, 3769U, 24641U, 379U, 2338U, 15414U, 2941U, 23412U, 611U, + 2627U, 15490U, 3145U, 23766U, 526U, 2542U, 15468U, 3119U, 23650U, + 13050U, 650U, 23799U, 24671U, 15931U, 26887U, 22824U, 26902U, 9783U, + 3849U, 203U, 27045U, 27083U, 27145U, 27489U, 27110U, 27189U, 13239U, + 26872U, 3660U, 24492U, 26916U, 3705U, 26909U, 3687U, 26932U, 3725U, + 13292U, 26879U, 3669U, 24507U, 26924U, 3715U, 3696U, 3735U, 27100U, + 27091U, 21366U, 21557U, 21641U, 21666U, 21857U, 27121U, 27220U, 8178U, + 2031U, 22225U, 22311U, 12385U, 25543U, 3871U, 18997U, 21379U, 21570U, + 21654U, 21679U, 21870U, 27598U, 27606U, 26685U, 26677U, 27585U, 26830U, + 27633U, 26858U, 27779U, 27808U, 27572U, 26816U, 27620U, 26844U, 27764U, + 27794U, 4972U, 4431U, 4446U, 4984U, 5199U, 15799U, 13620U, 13602U, + 13636U, 13652U, 13695U, 2760U, 9831U, 1976U, 18181U, 6781U, 18921U, + 6913U, 22082U, 19042U, 27060U, 27157U, 27500U, 27133U, 27231U, 26761U, + 27706U, 27822U, 26765U, 27826U, 21542U, 21626U, 21842U, 14118U, 18437U, + 10053U, 1329U, 25839U, 20605U, 11407U, 11194U, 17923U, 5958U, 19122U, + 16870U, 17283U, 19294U, 7823U, 13919U, 1432U, 14036U, 1487U, 25582U, + 1845U, 25144U, 1817U, 13991U, 18333U, 14098U, 18424U, 25821U, 20593U, + 3353U, 11218U, 17934U, 10291U, 11768U, 14398U, 24897U, 10699U, 12567U, + 14887U, 25866U, 10891U, 12932U, 15136U, 26215U, 17500U, 5698U, 9921U, + 1234U, 10031U, 1297U, 7793U, 14183U, 1575U, 10133U, 17824U, 14138U, + 1547U, 10073U, 17771U, 10505U, 12132U, 14583U, 25262U, 10961U, 13013U, + 15206U, 26305U, 11251U, 17943U, 10275U, 11751U, 14382U, 24880U, 17977U, + 6180U, 26770U, 20754U, 27724U, 20850U, 27657U, 20808U, 20955U, 6971U, + 11187U, 5946U, 11574U, 17311U, 5539U, 2154U, 17338U, 5572U, 10380U, + 6836U, 17984U, 6189U, 24742U, 26775U, 3633U, 20762U, 11624U, 1389U, + 10604U, 12414U, 14736U, 25668U, 10796U, 12779U, 14994U, 26062U, 15345U, + 11181U, 5935U, 6864U, 10681U, 12549U, 14860U, 25848U, 10873U, 12914U, + 15118U, 26197U, 10629U, 12488U, 14799U, 25742U, 10821U, 12853U, 15057U, + 26136U, 4499U, 4375U, 4883U, 4527U, 4324U, 4823U, 4391U, 5186U, + 5125U, 17295U, 27656U, 15532U, 11031U, 5814U, 20954U, 1750U, 76U, + 222U, 216U, 230U, 11002U, 13488U, 23876U, 5479U, 26639U, 6121U, + 13493U, 15708U, 18153U, 26606U, 6084U, 23881U, 15945U, 20099U, 26646U, + 6134U, 13498U, 15714U, 26613U, 6097U, 23886U, 15951U, 13503U, 15720U, + 23891U, 15957U, 10441U, 12082U, 14533U, 25212U, 10575U, 12333U, 14707U, + 25491U, 5777U, 22483U, 3255U, 11213U, 2071U, 5981U, 15935U, 17545U, + 11066U, 5874U, 11275U, 5526U, 2130U, 17961U, 6147U, 19343U, 11005U, + 2043U, 5785U, 11229U, 2090U, 6020U, 26596U, 3453U, 15540U, 11042U, + 5835U, 15904U, 19615U, 18756U, 11257U, 2106U, 6062U, 16098U, 20691U, + 26660U, 3485U, 11074U, 5887U, 11281U, 2138U, 6158U, 16110U, 20714U, + 10417U, 12058U, 14509U, 25188U, 10547U, 12181U, 14610U, 25305U, 10471U, + 12098U, 14549U, 25228U, 10589U, 12377U, 14721U, 25535U, 24589U, 20238U, + 22096U, 6991U, 26601U, 3460U, 11050U, 5848U, 11263U, 2114U, 6073U, + 16104U, 20699U, 11224U, 2083U, 6010U, 11235U, 2098U, 6031U, 26665U, + 3492U, 15547U, 11082U, 5900U, 15912U, 19626U, 18766U, 11287U, 2146U, + 6169U, 16116U, 20722U, 10520U, 24791U, 10513U, 24779U, 13306U, 2723U, + 11010U, 2050U, 5795U, 10387U, 12036U, 14487U, 25166U, 10359U, 12015U, + 14466U, 25070U, 15683U, 17535U, 11058U, 5861U, 11269U, 5513U, 2122U, + 17952U, 6110U, 18084U, 11241U, 6042U, 10996U, 13087U, 15241U, 24785U, + 26362U, 11246U, 6052U, 713U, 1909U, 16812U, 15511U, 17366U, 5594U, + 18740U, 6893U, 10395U, 24755U, 10489U, 12116U, 14567U, 25246U, 10768U, + 12656U, 14966U, 25979U, 10991U, 13073U, 15236U, 24774U, 26357U, 4910U, + 4556U, 4922U, 4569U, 4898U, 4543U, 4809U, 5234U, 4733U, 5226U, + 4724U, 13247U, 13222U, 18012U, 18038U, 6724U, 8059U, 2433U, 6387U, + 23505U, 7371U, 680U, 2690U, 6656U, 20431U, 23825U, 20063U, 7652U, + 10426U, 12067U, 14518U, 25197U, 10562U, 12251U, 14633U, 25388U, 92U, + 16261U, 16854U, 9794U, 23087U, 982U, 1015U, 1069U, 12406U, 6529U, + 23642U, 7513U, 10637U, 12496U, 14807U, 25750U, 10829U, 12861U, 15065U, + 26144U, 10621U, 12480U, 14791U, 25734U, 10813U, 12845U, 15049U, 26128U, + 22011U, 19004U, 6982U, 8091U, 10655U, 12514U, 14825U, 25768U, 10847U, + 12879U, 15083U, 26162U, 10716U, 12584U, 14904U, 25883U, 10919U, 12960U, + 15164U, 26243U, 26628U, 20707U, 7916U, 8108U, 9968U, 1248U, 9870U, + 1202U, 10083U, 1344U, 9981U, 17729U, 9883U, 17656U, 10096U, 17784U, + 9999U, 17744U, 9901U, 17671U, 10114U, 17799U, 6306U, 7266U, 12311U, + 6515U, 14005U, 18344U, 23626U, 7499U, 12007U, 23431U, 11913U, 6277U, + 13900U, 18263U, 23357U, 7237U, 12724U, 6588U, 14165U, 18464U, 23727U, + 7572U, 11974U, 6291U, 23366U, 7251U, 12264U, 6469U, 23580U, 7453U, + 11866U, 6231U, 23311U, 7191U, 12677U, 6542U, 23681U, 7526U, 12290U, + 6484U, 23590U, 7468U, 11892U, 6246U, 23321U, 7206U, 12703U, 6557U, + 23691U, 7541U, 12224U, 6440U, 23538U, 7424U, 12301U, 6500U, 23609U, + 7484U, 11903U, 6262U, 23340U, 7222U, 12714U, 6573U, 23710U, 7557U, + 12234U, 6455U, 23555U, 7439U, 10751U, 12639U, 14949U, 25962U, 10943U, + 15188U, 26287U, 9808U, 9815U, 11394U, 13817U, 24805U, 11293U, 13800U, + 24798U, 117U, 16277U, 16862U, 9801U, 23200U, 19661U, 24832U, 20350U, + 16128U, 23210U, 19674U, 24864U, 20363U, 6945U, 2456U, 17068U, 6416U, + 23524U, 19868U, 7400U, 3436U, 3403U, 3391U, 516U, 16673U, 2532U, + 17156U, 16144U, 6958U, 3212U, 3420U, 25917U, 20617U, 7891U, 703U, + 16799U, 2713U, 17270U, 23844U, 20088U, 7681U, 498U, 16649U, 2514U, + 17132U, 23619U, 19922U, 371U, 16510U, 2330U, 17020U, 23406U, 19804U, + 344U, 16474U, 2303U, 16996U, 23350U, 19774U, 573U, 16725U, 2589U, + 17208U, 23720U, 19975U, 303U, 16421U, 2262U, 16943U, 23286U, 19729U, + 313U, 16434U, 2272U, 16956U, 23294U, 19740U, 431U, 16561U, 2390U, + 17043U, 23470U, 19847U, 543U, 16686U, 2559U, 17169U, 23665U, 19942U, + 324U, 16448U, 2283U, 16970U, 23303U, 19752U, 553U, 16699U, 2569U, + 17182U, 23673U, 19953U, 478U, 16623U, 2494U, 17106U, 23572U, 19900U, + 353U, 16486U, 2312U, 17008U, 23392U, 19784U, 488U, 16636U, 2504U, + 17119U, 23601U, 19911U, 334U, 16461U, 2293U, 16983U, 23332U, 19763U, + 563U, 16712U, 2579U, 17195U, 23702U, 19964U, 450U, 16586U, 2466U, + 17081U, 23548U, 19879U, 5007U, 4846U, 4473U, 11406U, 26769U, 27723U, + 27662U, 15266U, 20961U, 15334U, 15344U, 22095U, 22010U, 8090U, 26627U, + 8107U, 24596U, 24577U, 24040U, 20107U, 7733U, 24393U, 1025U, 20884U, + 24571U, 15253U, 23092U, 20878U, 24550U, 24597U, 24578U, 7844U, 7854U, + 10735U, 12623U, 14923U, 25936U, 10927U, 12988U, 15172U, 26271U, 18600U, + 6838U, 9789U, 8022U, 9U, 97U, 1141U, 21085U, 15U, 11690U, + 24481U, 24185U, 49U, 134U, 1147U, 21098U, 36U, 14371U, 24512U, + 15992U, 24168U, 27683U, 24538U, 8082U, 12540U, 14851U, 25803U, 12905U, + 15109U, 26188U, 12462U, 14773U, 25716U, 12827U, 15031U, 26110U, 14247U, + 1632U, 14322U, 1684U, 25327U, 20441U, 14284U, 18513U, 15598U, 18829U, + 22544U, 19418U, 14348U, 1720U, 14227U, 1602U, 22173U, 14261U, 1651U, + 14335U, 1702U, 25339U, 20456U, 14310U, 18545U, 12432U, 14754U, 25686U, + 12797U, 15012U, 26080U, 15609U, 18843U, 22555U, 19432U, 14358U, 1735U, + 14275U, 1670U, 22986U, 974U, 24730U, 13807U, 24628U, 11546U, 15925U, + 960U, 1005U, 24682U, 8502U, 238U, 24583U, 15940U, 967U, 24688U, + 10193U, 27650U, 24658U, 22468U, 13347U, 7063U, 5093U, 5071U, 9827U, + 17643U, 5729U, 15258U, 18608U, 6846U, 24189U, 24041U, 11090U, 5913U, + 20108U, 7734U, 22472U, 13352U, 7072U, 24394U, 22429U, 22115U, 24716U, + 20301U, 19067U, 24724U, 20312U, 19321U, 25648U, 20555U, 25611U, 20529U, + 14931U, 18578U, 26342U, 20641U, 25638U, 20542U, 25592U, 20504U, 14869U, + 18566U, 25549U, 20482U, 23195U, 989U, 20152U, 7765U, 507U, 16661U, + 2523U, 17144U, 23635U, 19932U, 11815U, 284U, 16396U, 2243U, 16931U, + 3315U, 23271U, 19708U, 7179U, 24944U, 11960U, 25049U, 12250U, 25387U, + 12405U, 25659U, 11852U, 24981U, 12663U, 25986U, 469U, 16611U, 2485U, + 996U, 16842U, 11922U, 25011U, 12347U, 25505U, 12274U, 25401U, 11876U, + 24995U, 12687U, 26000U, 11936U, 25025U, 12210U, 25358U, 13036U, 632U, + 16775U, 2648U, 17246U, 23785U, 20017U, 7598U, 26328U, 14625U, 25372U, + 11723U, 24850U, 12159U, 25283U, 12361U, 25519U, 12592U, 25891U, 12968U, + 26251U, 12168U, 25292U, 12370U, 25528U, 10528U, 12146U, 14591U, 25270U, + 11715U, 24842U, 2444U, 6401U, 23514U, 7385U, 691U, 2701U, 6670U, + 20471U, 23834U, 20075U, 7666U, 11822U, 24951U, 11777U, 24906U, 13066U, + 26350U, 11759U, 24888U, 12203U, 25351U, 641U, 16787U, 2657U, 17258U, + 6614U, 23792U, 20027U, 7610U, 11793U, 24922U, 12189U, 441U, 16574U, + 2400U, 17056U, 3334U, 23478U, 19858U, 7329U, 25313U, 400U, 16521U, + 2359U, 17031U, 23439U, 19813U, 7306U, 15517U, 12243U, 25380U, 12740U, + 26023U, 12765U, 26048U, 11967U, 25056U, 12257U, 25394U, 11859U, 24988U, + 12670U, 25993U, 11929U, 25018U, 12354U, 25512U, 12757U, 582U, 16737U, + 2598U, 17220U, 23743U, 19985U, 26040U, 11786U, 265U, 16371U, 2224U, + 16919U, 3305U, 23256U, 19687U, 7167U, 24915U, 12282U, 25409U, 11884U, + 25003U, 12695U, 26008U, 11944U, 25033U, 12217U, 25365U, 12602U, 25901U, + 12978U, 26261U, 14639U, 25417U, 12442U, 25696U, 12807U, 26090U, 15358U, + 6882U, 24387U, 7754U, 12453U, 14764U, 25707U, 12818U, 15022U, 26101U, + 12423U, 14745U, 25677U, 12788U, 15003U, 26071U, 15808U, 18933U, 10976U, + 13028U, 15221U, 26320U, 10555U, 12196U, 14618U, 25320U, 10336U, 11844U, + 14443U, 24973U, 10597U, 12391U, 14729U, 25556U, 23088U, 10782U, 12748U, + 14980U, 26031U, 24737U, 10344U, 11952U, 14451U, 25041U, 20330U, 19637U, + 7134U, 15509U, 15536U, 22805U, 17442U, 3266U, 5500U, 5738U, 5991U, + 17461U, 19644U, 9851U, 2000U, 19535U, 19607U, 26552U, 20668U, 18749U, + 11036U, 2063U, 5824U, 11015U, 2057U, 5805U, 22802U, 17434U, 3261U, + 22419U, 17302U, 5489U, 7037U, 9845U, 1992U, 7995U, 8030U, 19529U, + 18735U, 4817U, 3857U, 4750U, 4742U, 4956U, 4788U, 9859U, 2010U, + 13102U, 17991U, 17481U, 26557U, 20676U, 7774U, 17650U, 5752U, 27646U, + 3800U, 13478U, 18137U, 20793U, 11554U, 82U, 1924U, 5441U, 16245U, + 1131U, 5359U, 7963U, 1889U, 10374U, 12030U, 14481U, 25160U, 15620U, + 11176U, 22604U, 162U, 1938U, 10323U, 11831U, 14430U, 24960U, 27730U, + 3819U, 20846U, 13834U, 2780U, 13253U, 18047U, 17510U, 26508U, 20661U, + 18211U, 27668U, 3806U, 13483U, 18145U, 20816U, 17358U, 5584U, 15805U, + 3207U, 8014U, 11557U, 8052U, 13288U, 18061U, 18927U, 6919U, 8076U, + 9790U, 5720U, 8023U, 6873U, 174U, 1954U, 16309U, 26812U, 3654U, + 20786U, 24813U, 17519U, 3431U, 152U, 16293U, 1153U, 5421U, 7979U, + 1899U, 22266U, 19153U, 13445U, 18123U, 19095U, 16090U, 3223U, 13296U, + 18068U, 18976U, 17395U, 5629U, 16824U, 11208U, 5971U, 19329U, 23034U, + 3293U, 13381U, 18098U, 19593U, 19305U, 11202U, 20223U, 26562U, 186U, + 16327U, 19653U, 20684U, 20338U, 7875U, 27702U, 4226U, 4290U, 4258U, + 4307U, 4836U, 4577U, 4462U, 4936U, 4593U, 4343U, 4405U, 11493U, + 11992U, 6333U, 23384U, 7293U, 14681U, 25459U, 24475U, 22399U, 19268U, + 20180U, 10960U, 13012U, 15205U, 26304U, 294U, 16409U, 2253U, 22287U, + 19183U, 17976U, 14654U, 25432U, 23279U, 19719U, 15726U, 18857U, 22729U, + 19465U, 15752U, 18889U, 22755U, 19497U, 11744U, 6219U, 23249U, 7155U, + 10664U, 12523U, 14834U, 25777U, 10856U, 12888U, 15092U, 26171U, 10300U, + 11778U, 14407U, 24907U, 13067U, 6685U, 23852U, 10743U, 12631U, 14941U, + 7694U, 25954U, 10935U, 12996U, 15180U, 26279U, 10U, 5297U, 98U, + 2160U, 16269U, 5339U, 1142U, 5379U, 16U, 16207U, 5307U, 245U, + 16345U, 2169U, 16881U, 5389U, 22U, 16216U, 15277U, 17348U, 2796U, + 22327U, 19195U, 18628U, 22021U, 17413U, 3241U, 22362U, 19219U, 19017U, + 22981U, 11731U, 6207U, 23242U, 7143U, 10646U, 12505U, 14816U, 25759U, + 10838U, 12870U, 15074U, 26153U, 10283U, 11760U, 14390U, 24889U, 12204U, + 6429U, 23532U, 10673U, 12532U, 14843U, 7413U, 25795U, 10865U, 12897U, + 15101U, 26180U, 11691U, 10191U, 17891U, 24482U, 7803U, 6198U, 10613U, + 12472U, 14783U, 25726U, 10805U, 12837U, 15041U, 26120U, 17320U, 5550U, + 19077U, 7015U, 24748U, 362U, 16498U, 2321U, 15407U, 2932U, 18695U, + 23399U, 19794U, 2198U, 15385U, 2825U, 23220U, 409U, 16533U, 2368U, + 15433U, 2962U, 18705U, 23446U, 19823U, 602U, 16763U, 2618U, 15483U, + 3136U, 18715U, 23759U, 20007U, 2211U, 15396U, 2838U, 23231U, 420U, + 16547U, 2379U, 15442U, 2973U, 18725U, 23455U, 19835U, 10242U, 11984U, + 6320U, 23376U, 7280U, 14671U, 25449U, 24463U, 22389U, 19255U, 20165U, + 10952U, 13004U, 15197U, 26296U, 275U, 16384U, 2234U, 22278U, 19171U, + 17907U, 14645U, 25423U, 23264U, 19698U, 50U, 5329U, 135U, 2189U, + 16907U, 16285U, 5349U, 1148U, 5411U, 37U, 16236U, 5318U, 255U, + 16358U, 2179U, 16894U, 5400U, 29U, 16226U, 15309U, 2818U, 22353U, + 19207U, 18652U, 22146U, 19103U, 22038U, 3248U, 22371U, 19231U, 19034U, + 66U, 198U, 1171U, 71U, 211U, 1176U, 23010U, 14372U, 24513U, + 7813U, 6816U, 15993U, 15764U, 18904U, 22767U, 19512U, 15554U, 18776U, + 22500U, 19365U, 14058U, 18384U, 25628U, 1860U, 14108U, 1517U, 25830U, + 1875U, 3363U, 14691U, 25469U, 14296U, 18528U, 14236U, 1616U, 24169U, + 22409U, 19281U, 22380U, 19243U, 20144U, 27684U, 20837U, 24533U, 7834U, + 10984U, 13043U, 15229U, 26335U, 18969U, 6936U, 13976U, 1459U, 14663U, + 25441U, 8083U, 14079U, 1503U, 4802U, 4929U, 4116U, 3839U, 10308U, + 11801U, 14415U, 24930U, 10315U, 11808U, 14422U, 24937U, 293U, 16408U, + 2252U, 23278U, 19718U, 274U, 16383U, 2233U, 23263U, 19697U, 22810U, + 3273U, 10457U, 19543U, 7081U, 24762U, 17472U, 5675U, 4997U, 5038U, + 22811U, 17453U, 5665U, 3274U, 10458U, 6855U, 19544U, 7082U, 24763U, + 26791U, 3641U, 20771U, 5137U, 13966U, 18309U, 13404U, 18114U, 6747U, + 10968U, 13020U, 15213U, 26312U, 10328U, 11836U, 14435U, 24965U, 10775U, + 12733U, 14973U, 26016U, 13934U, 18276U, 9936U, 17685U, 3325U, 3373U, + 22174U, 15583U, 8436U, 17573U, 18811U, 22529U, 8486U, 17610U, 19400U, + 15739U, 18873U, 22742U, 19481U, 15569U, 8421U, 17555U, 18794U, 22515U, + 8471U, 17592U, 19383U, 13878U, 18244U, 25092U, 20398U, 13853U, 18228U, + 25121U, 20413U, 13866U, 1401U, 25077U, 1762U, 25104U, 1782U, 13559U, + 13229U, 18022U, 20652U, 18161U, 6758U, 8068U, 11616U, 1376U, 3344U, + 3382U, 10177U, 17871U, 22240U, 19135U, 23028U, 3285U, 19584U, 7123U, + 7099U, 459U, 16598U, 2475U, 17093U, 23564U, 19889U, 14209U, 18501U, + 10159U, 17847U, 13950U, 18298U, 9952U, 17707U, 12741U, 6602U, 23736U, + 7586U, 22987U, 24731U, 20321U, 19557U, 2421U, 6372U, 23495U, 7356U, + 668U, 2678U, 6641U, 20387U, 23815U, 20050U, 7637U, 592U, 16750U, + 2608U, 17233U, 23751U, 19996U, 4757U, 4133U, 8417U, 11300U, 10708U, + 12576U, 14896U, 25875U, 10911U, 12952U, 15156U, 26235U, 10188U, 17294U, + 5469U, 2015U, 13119U, 17998U, 17885U, 5760U, 11221U, 2078U, 8006U, + 11402U, 8045U, 13172U, 18005U, 17937U, 6002U, 8039U, 11712U, 22104U, + 17423U, 5651U, 19050U, 7004U, 8098U, 87U, 1931U, 5455U, 16253U, + 1136U, 5369U, 7971U, 1894U, 24629U, 20248U, 15624U, 22608U, 168U, + 1946U, 9823U, 1970U, 17636U, 13825U, 2774U, 18204U, 26653U, 3476U, + 13093U, 6710U, 7925U, 23867U, 7719U, 26620U, 3467U, 13078U, 6696U, + 7904U, 23858U, 7705U, 12140U, 6346U, 23464U, 7318U, 22487U, 26785U, + 14368U, 17330U, 5562U, 2785U, 13257U, 18054U, 10353U, 14460U, 25064U, + 22026U, 24709U, 20291U, 19025U, 14200U, 18489U, 10150U, 17835U, 14148U, + 18450U, 25944U, 20628U, 13942U, 18287U, 9944U, 17696U, 14069U, 18398U, + 25786U, 20569U, 14191U, 18477U, 10141U, 1362U, 14047U, 18370U, 10042U, + 1313U, 25601U, 20516U, 13845U, 18217U, 9862U, 1189U, 14015U, 18357U, + 10010U, 1266U, 25563U, 20492U, 14218U, 1588U, 10168U, 17859U, 13958U, + 1446U, 9960U, 17718U, 18560U, 6808U, 13261U, 6735U, 10373U, 12029U, + 14480U, 25159U, 10322U, 11830U, 14429U, 24959U, 15926U, 17377U, 5607U, + 1006U, 3536U, 10403U, 12044U, 14495U, 25174U, 24683U, 20264U, 10535U, + 12153U, 14598U, 18955U, 6927U, 25277U, 24154U, 3414U, 20124U, 26795U, + 3647U, 20778U, 27758U, 3831U, 20859U, 27672U, 3812U, 20823U, 13326U, + 26780U, 10480U, 12107U, 14558U, 25237U, 10760U, 12648U, 14958U, 25971U, + 8503U, 10366U, 12022U, 14473U, 25152U, 10433U, 12074U, 14525U, 25204U, + 10568U, 12320U, 14700U, 25478U, 24584U, 20230U, 10269U, 11738U, 14376U, + 17629U, 24874U, 15941U, 17386U, 5618U, 10410U, 12051U, 14502U, 25181U, + 10449U, 12090U, 14541U, 25220U, 10582U, 12340U, 14714U, 25498U, 24689U, + 20272U, 10541U, 12175U, 14604U, 18962U, 25299U, 22167U, 19113U, 7026U, + 10791U, 12774U, 14989U, 26057U, 10194U, 13910U, 1418U, 14025U, 1471U, + 25572U, 1830U, 25136U, 1804U, 13983U, 18322U, 14088U, 18411U, 25812U, + 20581U, 10900U, 12941U, 15145U, 26224U, 10724U, 12612U, 14912U, 25925U, + 10690U, 12558U, 14878U, 25857U, 10882U, 12923U, 15127U, 26206U, 17490U, + 5686U, 9912U, 1220U, 10020U, 1281U, 7783U, 14175U, 1562U, 10125U, + 17813U, 14128U, 1532U, 10063U, 17758U, 10497U, 12124U, 14575U, 25254U, + 10953U, 13005U, 15198U, 26297U, 17894U, 5768U, 27651U, 20800U, 180U, + 1962U, 16318U, 24823U, 17527U, 5710U, 3448U, 157U, 16301U, 1158U, + 5431U, 7987U, 1904U, 22272U, 19162U, 13449U, 18130U, 16094U, 3229U, + 13301U, 18076U, 18983U, 17404U, 5640U, 16833U, 19336U, 23038U, 3299U, + 13386U, 18106U, 19600U, 19313U, 7053U, 192U, 16336U, 20344U, 7883U, + 11154U, 15247U, 18591U, 6825U, 17915U, 5925U, 15816U, 18944U, 4781U, + 4144U, 4242U, 4948U, 4964U, 4274U, 4212U, 5103U, 5017U, 4858U, + 4486U, 4870U, 4513U, 5048U, 4126U, 5082U, 4219U, 5114U, 5173U, + 4359U, 4418U, 22491U, 15320U, 18660U, 19350U, 13243U, 15256U, 24518U, + 20197U, 18606U, 24497U, 20189U, 18031U, 24701U, 13586U, 18169U, 20280U, + 22140U, 19086U, 22689U, 19456U, 15370U, 18685U, 23021U, 19574U, 24694U, + 13578U, 6768U, 7863U, 22110U, 19059U, 22495U, 19357U, 15364U, 18676U, + 23015U, 19565U, 24158U, 15339U, 20206U, 18668U, 24566U, 20215U, 20131U, + 13330U, 15261U, 18614U, 18091U, 2409U, 6357U, 23485U, 7341U, 656U, + 2666U, 6626U, 20376U, 23805U, 20037U, 7622U, 24524U, 24659U, 20256U, + 24531U, 61U, 24544U, 10352U, 12000U, 14459U, 25063U, 24073U, 20116U, + 7744U, 22246U, 19144U, 7111U, 13812U, 18196U, 6798U, 22872U, 17452U, + 5664U, 3279U, 10464U, 6854U, 19550U, 7090U, 24768U, 26790U, 3640U, + 20770U, 5148U, 11551U, +}; + +#endif // GET_INSTRINFO_MC_DESC diff --git a/arch/Mips/MipsGenInstrInfo.inc b/arch/Mips/MipsGenInstrInfo.inc deleted file mode 100644 index b6e8983edc..0000000000 --- a/arch/Mips/MipsGenInstrInfo.inc +++ /dev/null @@ -1,1805 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Target Instruction Enum Values *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ - - -#ifdef GET_INSTRINFO_ENUM -#undef GET_INSTRINFO_ENUM - -enum { - Mips_PHI = 0, - Mips_INLINEASM = 1, - Mips_CFI_INSTRUCTION = 2, - Mips_EH_LABEL = 3, - Mips_GC_LABEL = 4, - Mips_KILL = 5, - Mips_EXTRACT_SUBREG = 6, - Mips_INSERT_SUBREG = 7, - Mips_IMPLICIT_DEF = 8, - Mips_SUBREG_TO_REG = 9, - Mips_COPY_TO_REGCLASS = 10, - Mips_DBG_VALUE = 11, - Mips_REG_SEQUENCE = 12, - Mips_COPY = 13, - Mips_BUNDLE = 14, - Mips_LIFETIME_START = 15, - Mips_LIFETIME_END = 16, - Mips_STACKMAP = 17, - Mips_PATCHPOINT = 18, - Mips_LOAD_STACK_GUARD = 19, - Mips_STATEPOINT = 20, - Mips_FRAME_ALLOC = 21, - Mips_ABSQ_S_PH = 22, - Mips_ABSQ_S_QB = 23, - Mips_ABSQ_S_W = 24, - Mips_ADD = 25, - Mips_ADDIUPC = 26, - Mips_ADDIUPC_MM = 27, - Mips_ADDIUR1SP_MM = 28, - Mips_ADDIUR2_MM = 29, - Mips_ADDIUS5_MM = 30, - Mips_ADDIUSP_MM = 31, - Mips_ADDQH_PH = 32, - Mips_ADDQH_R_PH = 33, - Mips_ADDQH_R_W = 34, - Mips_ADDQH_W = 35, - Mips_ADDQ_PH = 36, - Mips_ADDQ_S_PH = 37, - Mips_ADDQ_S_W = 38, - Mips_ADDSC = 39, - Mips_ADDS_A_B = 40, - Mips_ADDS_A_D = 41, - Mips_ADDS_A_H = 42, - Mips_ADDS_A_W = 43, - Mips_ADDS_S_B = 44, - Mips_ADDS_S_D = 45, - Mips_ADDS_S_H = 46, - Mips_ADDS_S_W = 47, - Mips_ADDS_U_B = 48, - Mips_ADDS_U_D = 49, - Mips_ADDS_U_H = 50, - Mips_ADDS_U_W = 51, - Mips_ADDU16_MM = 52, - Mips_ADDUH_QB = 53, - Mips_ADDUH_R_QB = 54, - Mips_ADDU_PH = 55, - Mips_ADDU_QB = 56, - Mips_ADDU_S_PH = 57, - Mips_ADDU_S_QB = 58, - Mips_ADDVI_B = 59, - Mips_ADDVI_D = 60, - Mips_ADDVI_H = 61, - Mips_ADDVI_W = 62, - Mips_ADDV_B = 63, - Mips_ADDV_D = 64, - Mips_ADDV_H = 65, - Mips_ADDV_W = 66, - Mips_ADDWC = 67, - Mips_ADD_A_B = 68, - Mips_ADD_A_D = 69, - Mips_ADD_A_H = 70, - Mips_ADD_A_W = 71, - Mips_ADD_MM = 72, - Mips_ADDi = 73, - Mips_ADDi_MM = 74, - Mips_ADDiu = 75, - Mips_ADDiu_MM = 76, - Mips_ADDu = 77, - Mips_ADDu_MM = 78, - Mips_ADJCALLSTACKDOWN = 79, - Mips_ADJCALLSTACKUP = 80, - Mips_ALIGN = 81, - Mips_ALUIPC = 82, - Mips_AND = 83, - Mips_AND16_MM = 84, - Mips_AND64 = 85, - Mips_ANDI16_MM = 86, - Mips_ANDI_B = 87, - Mips_AND_MM = 88, - Mips_AND_V = 89, - Mips_AND_V_D_PSEUDO = 90, - Mips_AND_V_H_PSEUDO = 91, - Mips_AND_V_W_PSEUDO = 92, - Mips_ANDi = 93, - Mips_ANDi64 = 94, - Mips_ANDi_MM = 95, - Mips_APPEND = 96, - Mips_ASUB_S_B = 97, - Mips_ASUB_S_D = 98, - Mips_ASUB_S_H = 99, - Mips_ASUB_S_W = 100, - Mips_ASUB_U_B = 101, - Mips_ASUB_U_D = 102, - Mips_ASUB_U_H = 103, - Mips_ASUB_U_W = 104, - Mips_ATOMIC_CMP_SWAP_I16 = 105, - Mips_ATOMIC_CMP_SWAP_I32 = 106, - Mips_ATOMIC_CMP_SWAP_I64 = 107, - Mips_ATOMIC_CMP_SWAP_I8 = 108, - Mips_ATOMIC_LOAD_ADD_I16 = 109, - Mips_ATOMIC_LOAD_ADD_I32 = 110, - Mips_ATOMIC_LOAD_ADD_I64 = 111, - Mips_ATOMIC_LOAD_ADD_I8 = 112, - Mips_ATOMIC_LOAD_AND_I16 = 113, - Mips_ATOMIC_LOAD_AND_I32 = 114, - Mips_ATOMIC_LOAD_AND_I64 = 115, - Mips_ATOMIC_LOAD_AND_I8 = 116, - Mips_ATOMIC_LOAD_NAND_I16 = 117, - Mips_ATOMIC_LOAD_NAND_I32 = 118, - Mips_ATOMIC_LOAD_NAND_I64 = 119, - Mips_ATOMIC_LOAD_NAND_I8 = 120, - Mips_ATOMIC_LOAD_OR_I16 = 121, - Mips_ATOMIC_LOAD_OR_I32 = 122, - Mips_ATOMIC_LOAD_OR_I64 = 123, - Mips_ATOMIC_LOAD_OR_I8 = 124, - Mips_ATOMIC_LOAD_SUB_I16 = 125, - Mips_ATOMIC_LOAD_SUB_I32 = 126, - Mips_ATOMIC_LOAD_SUB_I64 = 127, - Mips_ATOMIC_LOAD_SUB_I8 = 128, - Mips_ATOMIC_LOAD_XOR_I16 = 129, - Mips_ATOMIC_LOAD_XOR_I32 = 130, - Mips_ATOMIC_LOAD_XOR_I64 = 131, - Mips_ATOMIC_LOAD_XOR_I8 = 132, - Mips_ATOMIC_SWAP_I16 = 133, - Mips_ATOMIC_SWAP_I32 = 134, - Mips_ATOMIC_SWAP_I64 = 135, - Mips_ATOMIC_SWAP_I8 = 136, - Mips_AUI = 137, - Mips_AUIPC = 138, - Mips_AVER_S_B = 139, - Mips_AVER_S_D = 140, - Mips_AVER_S_H = 141, - Mips_AVER_S_W = 142, - Mips_AVER_U_B = 143, - Mips_AVER_U_D = 144, - Mips_AVER_U_H = 145, - Mips_AVER_U_W = 146, - Mips_AVE_S_B = 147, - Mips_AVE_S_D = 148, - Mips_AVE_S_H = 149, - Mips_AVE_S_W = 150, - Mips_AVE_U_B = 151, - Mips_AVE_U_D = 152, - Mips_AVE_U_H = 153, - Mips_AVE_U_W = 154, - Mips_AddiuRxImmX16 = 155, - Mips_AddiuRxPcImmX16 = 156, - Mips_AddiuRxRxImm16 = 157, - Mips_AddiuRxRxImmX16 = 158, - Mips_AddiuRxRyOffMemX16 = 159, - Mips_AddiuSpImm16 = 160, - Mips_AddiuSpImmX16 = 161, - Mips_AdduRxRyRz16 = 162, - Mips_AndRxRxRy16 = 163, - Mips_B = 164, - Mips_B16_MM = 165, - Mips_BADDu = 166, - Mips_BAL = 167, - Mips_BALC = 168, - Mips_BALIGN = 169, - Mips_BAL_BR = 170, - Mips_BBIT0 = 171, - Mips_BBIT032 = 172, - Mips_BBIT1 = 173, - Mips_BBIT132 = 174, - Mips_BC = 175, - Mips_BC0F = 176, - Mips_BC0FL = 177, - Mips_BC0T = 178, - Mips_BC0TL = 179, - Mips_BC1EQZ = 180, - Mips_BC1F = 181, - Mips_BC1FL = 182, - Mips_BC1F_MM = 183, - Mips_BC1NEZ = 184, - Mips_BC1T = 185, - Mips_BC1TL = 186, - Mips_BC1T_MM = 187, - Mips_BC2EQZ = 188, - Mips_BC2F = 189, - Mips_BC2FL = 190, - Mips_BC2NEZ = 191, - Mips_BC2T = 192, - Mips_BC2TL = 193, - Mips_BC3F = 194, - Mips_BC3FL = 195, - Mips_BC3T = 196, - Mips_BC3TL = 197, - Mips_BCLRI_B = 198, - Mips_BCLRI_D = 199, - Mips_BCLRI_H = 200, - Mips_BCLRI_W = 201, - Mips_BCLR_B = 202, - Mips_BCLR_D = 203, - Mips_BCLR_H = 204, - Mips_BCLR_W = 205, - Mips_BEQ = 206, - Mips_BEQ64 = 207, - Mips_BEQC = 208, - Mips_BEQL = 209, - Mips_BEQZ16_MM = 210, - Mips_BEQZALC = 211, - Mips_BEQZC = 212, - Mips_BEQZC_MM = 213, - Mips_BEQ_MM = 214, - Mips_BGEC = 215, - Mips_BGEUC = 216, - Mips_BGEZ = 217, - Mips_BGEZ64 = 218, - Mips_BGEZAL = 219, - Mips_BGEZALC = 220, - Mips_BGEZALL = 221, - Mips_BGEZALS_MM = 222, - Mips_BGEZAL_MM = 223, - Mips_BGEZC = 224, - Mips_BGEZL = 225, - Mips_BGEZ_MM = 226, - Mips_BGTZ = 227, - Mips_BGTZ64 = 228, - Mips_BGTZALC = 229, - Mips_BGTZC = 230, - Mips_BGTZL = 231, - Mips_BGTZ_MM = 232, - Mips_BINSLI_B = 233, - Mips_BINSLI_D = 234, - Mips_BINSLI_H = 235, - Mips_BINSLI_W = 236, - Mips_BINSL_B = 237, - Mips_BINSL_D = 238, - Mips_BINSL_H = 239, - Mips_BINSL_W = 240, - Mips_BINSRI_B = 241, - Mips_BINSRI_D = 242, - Mips_BINSRI_H = 243, - Mips_BINSRI_W = 244, - Mips_BINSR_B = 245, - Mips_BINSR_D = 246, - Mips_BINSR_H = 247, - Mips_BINSR_W = 248, - Mips_BITREV = 249, - Mips_BITSWAP = 250, - Mips_BLEZ = 251, - Mips_BLEZ64 = 252, - Mips_BLEZALC = 253, - Mips_BLEZC = 254, - Mips_BLEZL = 255, - Mips_BLEZ_MM = 256, - Mips_BLTC = 257, - Mips_BLTUC = 258, - Mips_BLTZ = 259, - Mips_BLTZ64 = 260, - Mips_BLTZAL = 261, - Mips_BLTZALC = 262, - Mips_BLTZALL = 263, - Mips_BLTZALS_MM = 264, - Mips_BLTZAL_MM = 265, - Mips_BLTZC = 266, - Mips_BLTZL = 267, - Mips_BLTZ_MM = 268, - Mips_BMNZI_B = 269, - Mips_BMNZ_V = 270, - Mips_BMZI_B = 271, - Mips_BMZ_V = 272, - Mips_BNE = 273, - Mips_BNE64 = 274, - Mips_BNEC = 275, - Mips_BNEGI_B = 276, - Mips_BNEGI_D = 277, - Mips_BNEGI_H = 278, - Mips_BNEGI_W = 279, - Mips_BNEG_B = 280, - Mips_BNEG_D = 281, - Mips_BNEG_H = 282, - Mips_BNEG_W = 283, - Mips_BNEL = 284, - Mips_BNEZ16_MM = 285, - Mips_BNEZALC = 286, - Mips_BNEZC = 287, - Mips_BNEZC_MM = 288, - Mips_BNE_MM = 289, - Mips_BNVC = 290, - Mips_BNZ_B = 291, - Mips_BNZ_D = 292, - Mips_BNZ_H = 293, - Mips_BNZ_V = 294, - Mips_BNZ_W = 295, - Mips_BOVC = 296, - Mips_BPOSGE32 = 297, - Mips_BPOSGE32_PSEUDO = 298, - Mips_BREAK = 299, - Mips_BREAK16_MM = 300, - Mips_BREAK_MM = 301, - Mips_BSELI_B = 302, - Mips_BSEL_D_PSEUDO = 303, - Mips_BSEL_FD_PSEUDO = 304, - Mips_BSEL_FW_PSEUDO = 305, - Mips_BSEL_H_PSEUDO = 306, - Mips_BSEL_V = 307, - Mips_BSEL_W_PSEUDO = 308, - Mips_BSETI_B = 309, - Mips_BSETI_D = 310, - Mips_BSETI_H = 311, - Mips_BSETI_W = 312, - Mips_BSET_B = 313, - Mips_BSET_D = 314, - Mips_BSET_H = 315, - Mips_BSET_W = 316, - Mips_BZ_B = 317, - Mips_BZ_D = 318, - Mips_BZ_H = 319, - Mips_BZ_V = 320, - Mips_BZ_W = 321, - Mips_B_MM_Pseudo = 322, - Mips_BeqzRxImm16 = 323, - Mips_BeqzRxImmX16 = 324, - Mips_Bimm16 = 325, - Mips_BimmX16 = 326, - Mips_BnezRxImm16 = 327, - Mips_BnezRxImmX16 = 328, - Mips_Break16 = 329, - Mips_Bteqz16 = 330, - Mips_BteqzT8CmpX16 = 331, - Mips_BteqzT8CmpiX16 = 332, - Mips_BteqzT8SltX16 = 333, - Mips_BteqzT8SltiX16 = 334, - Mips_BteqzT8SltiuX16 = 335, - Mips_BteqzT8SltuX16 = 336, - Mips_BteqzX16 = 337, - Mips_Btnez16 = 338, - Mips_BtnezT8CmpX16 = 339, - Mips_BtnezT8CmpiX16 = 340, - Mips_BtnezT8SltX16 = 341, - Mips_BtnezT8SltiX16 = 342, - Mips_BtnezT8SltiuX16 = 343, - Mips_BtnezT8SltuX16 = 344, - Mips_BtnezX16 = 345, - Mips_BuildPairF64 = 346, - Mips_BuildPairF64_64 = 347, - Mips_CACHE = 348, - Mips_CACHE_MM = 349, - Mips_CACHE_R6 = 350, - Mips_CEIL_L_D64 = 351, - Mips_CEIL_L_S = 352, - Mips_CEIL_W_D32 = 353, - Mips_CEIL_W_D64 = 354, - Mips_CEIL_W_MM = 355, - Mips_CEIL_W_S = 356, - Mips_CEIL_W_S_MM = 357, - Mips_CEQI_B = 358, - Mips_CEQI_D = 359, - Mips_CEQI_H = 360, - Mips_CEQI_W = 361, - Mips_CEQ_B = 362, - Mips_CEQ_D = 363, - Mips_CEQ_H = 364, - Mips_CEQ_W = 365, - Mips_CFC1 = 366, - Mips_CFC1_MM = 367, - Mips_CFCMSA = 368, - Mips_CINS = 369, - Mips_CINS32 = 370, - Mips_CLASS_D = 371, - Mips_CLASS_S = 372, - Mips_CLEI_S_B = 373, - Mips_CLEI_S_D = 374, - Mips_CLEI_S_H = 375, - Mips_CLEI_S_W = 376, - Mips_CLEI_U_B = 377, - Mips_CLEI_U_D = 378, - Mips_CLEI_U_H = 379, - Mips_CLEI_U_W = 380, - Mips_CLE_S_B = 381, - Mips_CLE_S_D = 382, - Mips_CLE_S_H = 383, - Mips_CLE_S_W = 384, - Mips_CLE_U_B = 385, - Mips_CLE_U_D = 386, - Mips_CLE_U_H = 387, - Mips_CLE_U_W = 388, - Mips_CLO = 389, - Mips_CLO_MM = 390, - Mips_CLO_R6 = 391, - Mips_CLTI_S_B = 392, - Mips_CLTI_S_D = 393, - Mips_CLTI_S_H = 394, - Mips_CLTI_S_W = 395, - Mips_CLTI_U_B = 396, - Mips_CLTI_U_D = 397, - Mips_CLTI_U_H = 398, - Mips_CLTI_U_W = 399, - Mips_CLT_S_B = 400, - Mips_CLT_S_D = 401, - Mips_CLT_S_H = 402, - Mips_CLT_S_W = 403, - Mips_CLT_U_B = 404, - Mips_CLT_U_D = 405, - Mips_CLT_U_H = 406, - Mips_CLT_U_W = 407, - Mips_CLZ = 408, - Mips_CLZ_MM = 409, - Mips_CLZ_R6 = 410, - Mips_CMPGDU_EQ_QB = 411, - Mips_CMPGDU_LE_QB = 412, - Mips_CMPGDU_LT_QB = 413, - Mips_CMPGU_EQ_QB = 414, - Mips_CMPGU_LE_QB = 415, - Mips_CMPGU_LT_QB = 416, - Mips_CMPU_EQ_QB = 417, - Mips_CMPU_LE_QB = 418, - Mips_CMPU_LT_QB = 419, - Mips_CMP_EQ_D = 420, - Mips_CMP_EQ_PH = 421, - Mips_CMP_EQ_S = 422, - Mips_CMP_F_D = 423, - Mips_CMP_F_S = 424, - Mips_CMP_LE_D = 425, - Mips_CMP_LE_PH = 426, - Mips_CMP_LE_S = 427, - Mips_CMP_LT_D = 428, - Mips_CMP_LT_PH = 429, - Mips_CMP_LT_S = 430, - Mips_CMP_SAF_D = 431, - Mips_CMP_SAF_S = 432, - Mips_CMP_SEQ_D = 433, - Mips_CMP_SEQ_S = 434, - Mips_CMP_SLE_D = 435, - Mips_CMP_SLE_S = 436, - Mips_CMP_SLT_D = 437, - Mips_CMP_SLT_S = 438, - Mips_CMP_SUEQ_D = 439, - Mips_CMP_SUEQ_S = 440, - Mips_CMP_SULE_D = 441, - Mips_CMP_SULE_S = 442, - Mips_CMP_SULT_D = 443, - Mips_CMP_SULT_S = 444, - Mips_CMP_SUN_D = 445, - Mips_CMP_SUN_S = 446, - Mips_CMP_UEQ_D = 447, - Mips_CMP_UEQ_S = 448, - Mips_CMP_ULE_D = 449, - Mips_CMP_ULE_S = 450, - Mips_CMP_ULT_D = 451, - Mips_CMP_ULT_S = 452, - Mips_CMP_UN_D = 453, - Mips_CMP_UN_S = 454, - Mips_CONSTPOOL_ENTRY = 455, - Mips_COPY_FD_PSEUDO = 456, - Mips_COPY_FW_PSEUDO = 457, - Mips_COPY_S_B = 458, - Mips_COPY_S_D = 459, - Mips_COPY_S_H = 460, - Mips_COPY_S_W = 461, - Mips_COPY_U_B = 462, - Mips_COPY_U_D = 463, - Mips_COPY_U_H = 464, - Mips_COPY_U_W = 465, - Mips_CTC1 = 466, - Mips_CTC1_MM = 467, - Mips_CTCMSA = 468, - Mips_CVT_D32_S = 469, - Mips_CVT_D32_W = 470, - Mips_CVT_D32_W_MM = 471, - Mips_CVT_D64_L = 472, - Mips_CVT_D64_S = 473, - Mips_CVT_D64_W = 474, - Mips_CVT_D_S_MM = 475, - Mips_CVT_L_D64 = 476, - Mips_CVT_L_D64_MM = 477, - Mips_CVT_L_S = 478, - Mips_CVT_L_S_MM = 479, - Mips_CVT_S_D32 = 480, - Mips_CVT_S_D32_MM = 481, - Mips_CVT_S_D64 = 482, - Mips_CVT_S_L = 483, - Mips_CVT_S_W = 484, - Mips_CVT_S_W_MM = 485, - Mips_CVT_W_D32 = 486, - Mips_CVT_W_D64 = 487, - Mips_CVT_W_MM = 488, - Mips_CVT_W_S = 489, - Mips_CVT_W_S_MM = 490, - Mips_C_EQ_D32 = 491, - Mips_C_EQ_D64 = 492, - Mips_C_EQ_S = 493, - Mips_C_F_D32 = 494, - Mips_C_F_D64 = 495, - Mips_C_F_S = 496, - Mips_C_LE_D32 = 497, - Mips_C_LE_D64 = 498, - Mips_C_LE_S = 499, - Mips_C_LT_D32 = 500, - Mips_C_LT_D64 = 501, - Mips_C_LT_S = 502, - Mips_C_NGE_D32 = 503, - Mips_C_NGE_D64 = 504, - Mips_C_NGE_S = 505, - Mips_C_NGLE_D32 = 506, - Mips_C_NGLE_D64 = 507, - Mips_C_NGLE_S = 508, - Mips_C_NGL_D32 = 509, - Mips_C_NGL_D64 = 510, - Mips_C_NGL_S = 511, - Mips_C_NGT_D32 = 512, - Mips_C_NGT_D64 = 513, - Mips_C_NGT_S = 514, - Mips_C_OLE_D32 = 515, - Mips_C_OLE_D64 = 516, - Mips_C_OLE_S = 517, - Mips_C_OLT_D32 = 518, - Mips_C_OLT_D64 = 519, - Mips_C_OLT_S = 520, - Mips_C_SEQ_D32 = 521, - Mips_C_SEQ_D64 = 522, - Mips_C_SEQ_S = 523, - Mips_C_SF_D32 = 524, - Mips_C_SF_D64 = 525, - Mips_C_SF_S = 526, - Mips_C_UEQ_D32 = 527, - Mips_C_UEQ_D64 = 528, - Mips_C_UEQ_S = 529, - Mips_C_ULE_D32 = 530, - Mips_C_ULE_D64 = 531, - Mips_C_ULE_S = 532, - Mips_C_ULT_D32 = 533, - Mips_C_ULT_D64 = 534, - Mips_C_ULT_S = 535, - Mips_C_UN_D32 = 536, - Mips_C_UN_D64 = 537, - Mips_C_UN_S = 538, - Mips_CmpRxRy16 = 539, - Mips_CmpiRxImm16 = 540, - Mips_CmpiRxImmX16 = 541, - Mips_Constant32 = 542, - Mips_DADD = 543, - Mips_DADDi = 544, - Mips_DADDiu = 545, - Mips_DADDu = 546, - Mips_DAHI = 547, - Mips_DALIGN = 548, - Mips_DATI = 549, - Mips_DAUI = 550, - Mips_DBITSWAP = 551, - Mips_DCLO = 552, - Mips_DCLO_R6 = 553, - Mips_DCLZ = 554, - Mips_DCLZ_R6 = 555, - Mips_DDIV = 556, - Mips_DDIVU = 557, - Mips_DERET = 558, - Mips_DERET_MM = 559, - Mips_DEXT = 560, - Mips_DEXTM = 561, - Mips_DEXTU = 562, - Mips_DI = 563, - Mips_DINS = 564, - Mips_DINSM = 565, - Mips_DINSU = 566, - Mips_DIV = 567, - Mips_DIVU = 568, - Mips_DIV_S_B = 569, - Mips_DIV_S_D = 570, - Mips_DIV_S_H = 571, - Mips_DIV_S_W = 572, - Mips_DIV_U_B = 573, - Mips_DIV_U_D = 574, - Mips_DIV_U_H = 575, - Mips_DIV_U_W = 576, - Mips_DI_MM = 577, - Mips_DLSA = 578, - Mips_DLSA_R6 = 579, - Mips_DMFC0 = 580, - Mips_DMFC1 = 581, - Mips_DMFC2 = 582, - Mips_DMOD = 583, - Mips_DMODU = 584, - Mips_DMTC0 = 585, - Mips_DMTC1 = 586, - Mips_DMTC2 = 587, - Mips_DMUH = 588, - Mips_DMUHU = 589, - Mips_DMUL = 590, - Mips_DMULT = 591, - Mips_DMULTu = 592, - Mips_DMULU = 593, - Mips_DMUL_R6 = 594, - Mips_DOTP_S_D = 595, - Mips_DOTP_S_H = 596, - Mips_DOTP_S_W = 597, - Mips_DOTP_U_D = 598, - Mips_DOTP_U_H = 599, - Mips_DOTP_U_W = 600, - Mips_DPADD_S_D = 601, - Mips_DPADD_S_H = 602, - Mips_DPADD_S_W = 603, - Mips_DPADD_U_D = 604, - Mips_DPADD_U_H = 605, - Mips_DPADD_U_W = 606, - Mips_DPAQX_SA_W_PH = 607, - Mips_DPAQX_S_W_PH = 608, - Mips_DPAQ_SA_L_W = 609, - Mips_DPAQ_S_W_PH = 610, - Mips_DPAU_H_QBL = 611, - Mips_DPAU_H_QBR = 612, - Mips_DPAX_W_PH = 613, - Mips_DPA_W_PH = 614, - Mips_DPOP = 615, - Mips_DPSQX_SA_W_PH = 616, - Mips_DPSQX_S_W_PH = 617, - Mips_DPSQ_SA_L_W = 618, - Mips_DPSQ_S_W_PH = 619, - Mips_DPSUB_S_D = 620, - Mips_DPSUB_S_H = 621, - Mips_DPSUB_S_W = 622, - Mips_DPSUB_U_D = 623, - Mips_DPSUB_U_H = 624, - Mips_DPSUB_U_W = 625, - Mips_DPSU_H_QBL = 626, - Mips_DPSU_H_QBR = 627, - Mips_DPSX_W_PH = 628, - Mips_DPS_W_PH = 629, - Mips_DROTR = 630, - Mips_DROTR32 = 631, - Mips_DROTRV = 632, - Mips_DSBH = 633, - Mips_DSDIV = 634, - Mips_DSHD = 635, - Mips_DSLL = 636, - Mips_DSLL32 = 637, - Mips_DSLL64_32 = 638, - Mips_DSLLV = 639, - Mips_DSRA = 640, - Mips_DSRA32 = 641, - Mips_DSRAV = 642, - Mips_DSRL = 643, - Mips_DSRL32 = 644, - Mips_DSRLV = 645, - Mips_DSUB = 646, - Mips_DSUBu = 647, - Mips_DUDIV = 648, - Mips_DivRxRy16 = 649, - Mips_DivuRxRy16 = 650, - Mips_EHB = 651, - Mips_EHB_MM = 652, - Mips_EI = 653, - Mips_EI_MM = 654, - Mips_ERET = 655, - Mips_ERET_MM = 656, - Mips_EXT = 657, - Mips_EXTP = 658, - Mips_EXTPDP = 659, - Mips_EXTPDPV = 660, - Mips_EXTPV = 661, - Mips_EXTRV_RS_W = 662, - Mips_EXTRV_R_W = 663, - Mips_EXTRV_S_H = 664, - Mips_EXTRV_W = 665, - Mips_EXTR_RS_W = 666, - Mips_EXTR_R_W = 667, - Mips_EXTR_S_H = 668, - Mips_EXTR_W = 669, - Mips_EXTS = 670, - Mips_EXTS32 = 671, - Mips_EXT_MM = 672, - Mips_ExtractElementF64 = 673, - Mips_ExtractElementF64_64 = 674, - Mips_FABS_D = 675, - Mips_FABS_D32 = 676, - Mips_FABS_D64 = 677, - Mips_FABS_MM = 678, - Mips_FABS_S = 679, - Mips_FABS_S_MM = 680, - Mips_FABS_W = 681, - Mips_FADD_D = 682, - Mips_FADD_D32 = 683, - Mips_FADD_D64 = 684, - Mips_FADD_MM = 685, - Mips_FADD_S = 686, - Mips_FADD_S_MM = 687, - Mips_FADD_W = 688, - Mips_FCAF_D = 689, - Mips_FCAF_W = 690, - Mips_FCEQ_D = 691, - Mips_FCEQ_W = 692, - Mips_FCLASS_D = 693, - Mips_FCLASS_W = 694, - Mips_FCLE_D = 695, - Mips_FCLE_W = 696, - Mips_FCLT_D = 697, - Mips_FCLT_W = 698, - Mips_FCMP_D32 = 699, - Mips_FCMP_D32_MM = 700, - Mips_FCMP_D64 = 701, - Mips_FCMP_S32 = 702, - Mips_FCMP_S32_MM = 703, - Mips_FCNE_D = 704, - Mips_FCNE_W = 705, - Mips_FCOR_D = 706, - Mips_FCOR_W = 707, - Mips_FCUEQ_D = 708, - Mips_FCUEQ_W = 709, - Mips_FCULE_D = 710, - Mips_FCULE_W = 711, - Mips_FCULT_D = 712, - Mips_FCULT_W = 713, - Mips_FCUNE_D = 714, - Mips_FCUNE_W = 715, - Mips_FCUN_D = 716, - Mips_FCUN_W = 717, - Mips_FDIV_D = 718, - Mips_FDIV_D32 = 719, - Mips_FDIV_D64 = 720, - Mips_FDIV_MM = 721, - Mips_FDIV_S = 722, - Mips_FDIV_S_MM = 723, - Mips_FDIV_W = 724, - Mips_FEXDO_H = 725, - Mips_FEXDO_W = 726, - Mips_FEXP2_D = 727, - Mips_FEXP2_D_1_PSEUDO = 728, - Mips_FEXP2_W = 729, - Mips_FEXP2_W_1_PSEUDO = 730, - Mips_FEXUPL_D = 731, - Mips_FEXUPL_W = 732, - Mips_FEXUPR_D = 733, - Mips_FEXUPR_W = 734, - Mips_FFINT_S_D = 735, - Mips_FFINT_S_W = 736, - Mips_FFINT_U_D = 737, - Mips_FFINT_U_W = 738, - Mips_FFQL_D = 739, - Mips_FFQL_W = 740, - Mips_FFQR_D = 741, - Mips_FFQR_W = 742, - Mips_FILL_B = 743, - Mips_FILL_D = 744, - Mips_FILL_FD_PSEUDO = 745, - Mips_FILL_FW_PSEUDO = 746, - Mips_FILL_H = 747, - Mips_FILL_W = 748, - Mips_FLOG2_D = 749, - Mips_FLOG2_W = 750, - Mips_FLOOR_L_D64 = 751, - Mips_FLOOR_L_S = 752, - Mips_FLOOR_W_D32 = 753, - Mips_FLOOR_W_D64 = 754, - Mips_FLOOR_W_MM = 755, - Mips_FLOOR_W_S = 756, - Mips_FLOOR_W_S_MM = 757, - Mips_FMADD_D = 758, - Mips_FMADD_W = 759, - Mips_FMAX_A_D = 760, - Mips_FMAX_A_W = 761, - Mips_FMAX_D = 762, - Mips_FMAX_W = 763, - Mips_FMIN_A_D = 764, - Mips_FMIN_A_W = 765, - Mips_FMIN_D = 766, - Mips_FMIN_W = 767, - Mips_FMOV_D32 = 768, - Mips_FMOV_D32_MM = 769, - Mips_FMOV_D64 = 770, - Mips_FMOV_S = 771, - Mips_FMOV_S_MM = 772, - Mips_FMSUB_D = 773, - Mips_FMSUB_W = 774, - Mips_FMUL_D = 775, - Mips_FMUL_D32 = 776, - Mips_FMUL_D64 = 777, - Mips_FMUL_MM = 778, - Mips_FMUL_S = 779, - Mips_FMUL_S_MM = 780, - Mips_FMUL_W = 781, - Mips_FNEG_D32 = 782, - Mips_FNEG_D64 = 783, - Mips_FNEG_MM = 784, - Mips_FNEG_S = 785, - Mips_FNEG_S_MM = 786, - Mips_FRCP_D = 787, - Mips_FRCP_W = 788, - Mips_FRINT_D = 789, - Mips_FRINT_W = 790, - Mips_FRSQRT_D = 791, - Mips_FRSQRT_W = 792, - Mips_FSAF_D = 793, - Mips_FSAF_W = 794, - Mips_FSEQ_D = 795, - Mips_FSEQ_W = 796, - Mips_FSLE_D = 797, - Mips_FSLE_W = 798, - Mips_FSLT_D = 799, - Mips_FSLT_W = 800, - Mips_FSNE_D = 801, - Mips_FSNE_W = 802, - Mips_FSOR_D = 803, - Mips_FSOR_W = 804, - Mips_FSQRT_D = 805, - Mips_FSQRT_D32 = 806, - Mips_FSQRT_D64 = 807, - Mips_FSQRT_MM = 808, - Mips_FSQRT_S = 809, - Mips_FSQRT_S_MM = 810, - Mips_FSQRT_W = 811, - Mips_FSUB_D = 812, - Mips_FSUB_D32 = 813, - Mips_FSUB_D64 = 814, - Mips_FSUB_MM = 815, - Mips_FSUB_S = 816, - Mips_FSUB_S_MM = 817, - Mips_FSUB_W = 818, - Mips_FSUEQ_D = 819, - Mips_FSUEQ_W = 820, - Mips_FSULE_D = 821, - Mips_FSULE_W = 822, - Mips_FSULT_D = 823, - Mips_FSULT_W = 824, - Mips_FSUNE_D = 825, - Mips_FSUNE_W = 826, - Mips_FSUN_D = 827, - Mips_FSUN_W = 828, - Mips_FTINT_S_D = 829, - Mips_FTINT_S_W = 830, - Mips_FTINT_U_D = 831, - Mips_FTINT_U_W = 832, - Mips_FTQ_H = 833, - Mips_FTQ_W = 834, - Mips_FTRUNC_S_D = 835, - Mips_FTRUNC_S_W = 836, - Mips_FTRUNC_U_D = 837, - Mips_FTRUNC_U_W = 838, - Mips_GotPrologue16 = 839, - Mips_HADD_S_D = 840, - Mips_HADD_S_H = 841, - Mips_HADD_S_W = 842, - Mips_HADD_U_D = 843, - Mips_HADD_U_H = 844, - Mips_HADD_U_W = 845, - Mips_HSUB_S_D = 846, - Mips_HSUB_S_H = 847, - Mips_HSUB_S_W = 848, - Mips_HSUB_U_D = 849, - Mips_HSUB_U_H = 850, - Mips_HSUB_U_W = 851, - Mips_ILVEV_B = 852, - Mips_ILVEV_D = 853, - Mips_ILVEV_H = 854, - Mips_ILVEV_W = 855, - Mips_ILVL_B = 856, - Mips_ILVL_D = 857, - Mips_ILVL_H = 858, - Mips_ILVL_W = 859, - Mips_ILVOD_B = 860, - Mips_ILVOD_D = 861, - Mips_ILVOD_H = 862, - Mips_ILVOD_W = 863, - Mips_ILVR_B = 864, - Mips_ILVR_D = 865, - Mips_ILVR_H = 866, - Mips_ILVR_W = 867, - Mips_INS = 868, - Mips_INSERT_B = 869, - Mips_INSERT_B_VIDX_PSEUDO = 870, - Mips_INSERT_D = 871, - Mips_INSERT_D_VIDX_PSEUDO = 872, - Mips_INSERT_FD_PSEUDO = 873, - Mips_INSERT_FD_VIDX_PSEUDO = 874, - Mips_INSERT_FW_PSEUDO = 875, - Mips_INSERT_FW_VIDX_PSEUDO = 876, - Mips_INSERT_H = 877, - Mips_INSERT_H_VIDX_PSEUDO = 878, - Mips_INSERT_W = 879, - Mips_INSERT_W_VIDX_PSEUDO = 880, - Mips_INSV = 881, - Mips_INSVE_B = 882, - Mips_INSVE_D = 883, - Mips_INSVE_H = 884, - Mips_INSVE_W = 885, - Mips_INS_MM = 886, - Mips_J = 887, - Mips_JAL = 888, - Mips_JALR = 889, - Mips_JALR16_MM = 890, - Mips_JALR64 = 891, - Mips_JALR64Pseudo = 892, - Mips_JALRPseudo = 893, - Mips_JALRS16_MM = 894, - Mips_JALRS_MM = 895, - Mips_JALR_HB = 896, - Mips_JALR_MM = 897, - Mips_JALS_MM = 898, - Mips_JALX = 899, - Mips_JALX_MM = 900, - Mips_JAL_MM = 901, - Mips_JIALC = 902, - Mips_JIC = 903, - Mips_JR = 904, - Mips_JR16_MM = 905, - Mips_JR64 = 906, - Mips_JRADDIUSP = 907, - Mips_JRC16_MM = 908, - Mips_JR_HB = 909, - Mips_JR_HB_R6 = 910, - Mips_JR_MM = 911, - Mips_J_MM = 912, - Mips_Jal16 = 913, - Mips_JalB16 = 914, - Mips_JalOneReg = 915, - Mips_JalTwoReg = 916, - Mips_JrRa16 = 917, - Mips_JrcRa16 = 918, - Mips_JrcRx16 = 919, - Mips_JumpLinkReg16 = 920, - Mips_LB = 921, - Mips_LB64 = 922, - Mips_LBU16_MM = 923, - Mips_LBUX = 924, - Mips_LB_MM = 925, - Mips_LBu = 926, - Mips_LBu64 = 927, - Mips_LBu_MM = 928, - Mips_LD = 929, - Mips_LDC1 = 930, - Mips_LDC164 = 931, - Mips_LDC1_MM = 932, - Mips_LDC2 = 933, - Mips_LDC2_R6 = 934, - Mips_LDC3 = 935, - Mips_LDI_B = 936, - Mips_LDI_D = 937, - Mips_LDI_H = 938, - Mips_LDI_W = 939, - Mips_LDL = 940, - Mips_LDPC = 941, - Mips_LDR = 942, - Mips_LDXC1 = 943, - Mips_LDXC164 = 944, - Mips_LD_B = 945, - Mips_LD_D = 946, - Mips_LD_H = 947, - Mips_LD_W = 948, - Mips_LEA_ADDiu = 949, - Mips_LEA_ADDiu64 = 950, - Mips_LEA_ADDiu_MM = 951, - Mips_LH = 952, - Mips_LH64 = 953, - Mips_LHU16_MM = 954, - Mips_LHX = 955, - Mips_LH_MM = 956, - Mips_LHu = 957, - Mips_LHu64 = 958, - Mips_LHu_MM = 959, - Mips_LI16_MM = 960, - Mips_LL = 961, - Mips_LLD = 962, - Mips_LLD_R6 = 963, - Mips_LL_MM = 964, - Mips_LL_R6 = 965, - Mips_LOAD_ACC128 = 966, - Mips_LOAD_ACC64 = 967, - Mips_LOAD_ACC64DSP = 968, - Mips_LOAD_CCOND_DSP = 969, - Mips_LONG_BRANCH_ADDiu = 970, - Mips_LONG_BRANCH_DADDiu = 971, - Mips_LONG_BRANCH_LUi = 972, - Mips_LSA = 973, - Mips_LSA_R6 = 974, - Mips_LUXC1 = 975, - Mips_LUXC164 = 976, - Mips_LUXC1_MM = 977, - Mips_LUi = 978, - Mips_LUi64 = 979, - Mips_LUi_MM = 980, - Mips_LW = 981, - Mips_LW16_MM = 982, - Mips_LW64 = 983, - Mips_LWC1 = 984, - Mips_LWC1_MM = 985, - Mips_LWC2 = 986, - Mips_LWC2_R6 = 987, - Mips_LWC3 = 988, - Mips_LWGP_MM = 989, - Mips_LWL = 990, - Mips_LWL64 = 991, - Mips_LWL_MM = 992, - Mips_LWM16_MM = 993, - Mips_LWM32_MM = 994, - Mips_LWM_MM = 995, - Mips_LWPC = 996, - Mips_LWP_MM = 997, - Mips_LWR = 998, - Mips_LWR64 = 999, - Mips_LWR_MM = 1000, - Mips_LWSP_MM = 1001, - Mips_LWUPC = 1002, - Mips_LWU_MM = 1003, - Mips_LWX = 1004, - Mips_LWXC1 = 1005, - Mips_LWXC1_MM = 1006, - Mips_LWXS_MM = 1007, - Mips_LW_MM = 1008, - Mips_LWu = 1009, - Mips_LbRxRyOffMemX16 = 1010, - Mips_LbuRxRyOffMemX16 = 1011, - Mips_LhRxRyOffMemX16 = 1012, - Mips_LhuRxRyOffMemX16 = 1013, - Mips_LiRxImm16 = 1014, - Mips_LiRxImmAlignX16 = 1015, - Mips_LiRxImmX16 = 1016, - Mips_LoadAddr32Imm = 1017, - Mips_LoadAddr32Reg = 1018, - Mips_LoadImm32Reg = 1019, - Mips_LoadImm64Reg = 1020, - Mips_LwConstant32 = 1021, - Mips_LwRxPcTcp16 = 1022, - Mips_LwRxPcTcpX16 = 1023, - Mips_LwRxRyOffMemX16 = 1024, - Mips_LwRxSpImmX16 = 1025, - Mips_MADD = 1026, - Mips_MADDF_D = 1027, - Mips_MADDF_S = 1028, - Mips_MADDR_Q_H = 1029, - Mips_MADDR_Q_W = 1030, - Mips_MADDU = 1031, - Mips_MADDU_DSP = 1032, - Mips_MADDU_MM = 1033, - Mips_MADDV_B = 1034, - Mips_MADDV_D = 1035, - Mips_MADDV_H = 1036, - Mips_MADDV_W = 1037, - Mips_MADD_D32 = 1038, - Mips_MADD_D32_MM = 1039, - Mips_MADD_D64 = 1040, - Mips_MADD_DSP = 1041, - Mips_MADD_MM = 1042, - Mips_MADD_Q_H = 1043, - Mips_MADD_Q_W = 1044, - Mips_MADD_S = 1045, - Mips_MADD_S_MM = 1046, - Mips_MAQ_SA_W_PHL = 1047, - Mips_MAQ_SA_W_PHR = 1048, - Mips_MAQ_S_W_PHL = 1049, - Mips_MAQ_S_W_PHR = 1050, - Mips_MAXA_D = 1051, - Mips_MAXA_S = 1052, - Mips_MAXI_S_B = 1053, - Mips_MAXI_S_D = 1054, - Mips_MAXI_S_H = 1055, - Mips_MAXI_S_W = 1056, - Mips_MAXI_U_B = 1057, - Mips_MAXI_U_D = 1058, - Mips_MAXI_U_H = 1059, - Mips_MAXI_U_W = 1060, - Mips_MAX_A_B = 1061, - Mips_MAX_A_D = 1062, - Mips_MAX_A_H = 1063, - Mips_MAX_A_W = 1064, - Mips_MAX_D = 1065, - Mips_MAX_S = 1066, - Mips_MAX_S_B = 1067, - Mips_MAX_S_D = 1068, - Mips_MAX_S_H = 1069, - Mips_MAX_S_W = 1070, - Mips_MAX_U_B = 1071, - Mips_MAX_U_D = 1072, - Mips_MAX_U_H = 1073, - Mips_MAX_U_W = 1074, - Mips_MFC0 = 1075, - Mips_MFC1 = 1076, - Mips_MFC1_MM = 1077, - Mips_MFC2 = 1078, - Mips_MFHC1_D32 = 1079, - Mips_MFHC1_D64 = 1080, - Mips_MFHC1_MM = 1081, - Mips_MFHI = 1082, - Mips_MFHI16_MM = 1083, - Mips_MFHI64 = 1084, - Mips_MFHI_DSP = 1085, - Mips_MFHI_MM = 1086, - Mips_MFLO = 1087, - Mips_MFLO16_MM = 1088, - Mips_MFLO64 = 1089, - Mips_MFLO_DSP = 1090, - Mips_MFLO_MM = 1091, - Mips_MINA_D = 1092, - Mips_MINA_S = 1093, - Mips_MINI_S_B = 1094, - Mips_MINI_S_D = 1095, - Mips_MINI_S_H = 1096, - Mips_MINI_S_W = 1097, - Mips_MINI_U_B = 1098, - Mips_MINI_U_D = 1099, - Mips_MINI_U_H = 1100, - Mips_MINI_U_W = 1101, - Mips_MIN_A_B = 1102, - Mips_MIN_A_D = 1103, - Mips_MIN_A_H = 1104, - Mips_MIN_A_W = 1105, - Mips_MIN_D = 1106, - Mips_MIN_S = 1107, - Mips_MIN_S_B = 1108, - Mips_MIN_S_D = 1109, - Mips_MIN_S_H = 1110, - Mips_MIN_S_W = 1111, - Mips_MIN_U_B = 1112, - Mips_MIN_U_D = 1113, - Mips_MIN_U_H = 1114, - Mips_MIN_U_W = 1115, - Mips_MIPSeh_return32 = 1116, - Mips_MIPSeh_return64 = 1117, - Mips_MOD = 1118, - Mips_MODSUB = 1119, - Mips_MODU = 1120, - Mips_MOD_S_B = 1121, - Mips_MOD_S_D = 1122, - Mips_MOD_S_H = 1123, - Mips_MOD_S_W = 1124, - Mips_MOD_U_B = 1125, - Mips_MOD_U_D = 1126, - Mips_MOD_U_H = 1127, - Mips_MOD_U_W = 1128, - Mips_MOVE16_MM = 1129, - Mips_MOVEP_MM = 1130, - Mips_MOVE_V = 1131, - Mips_MOVF_D32 = 1132, - Mips_MOVF_D32_MM = 1133, - Mips_MOVF_D64 = 1134, - Mips_MOVF_I = 1135, - Mips_MOVF_I64 = 1136, - Mips_MOVF_I_MM = 1137, - Mips_MOVF_S = 1138, - Mips_MOVF_S_MM = 1139, - Mips_MOVN_I64_D64 = 1140, - Mips_MOVN_I64_I = 1141, - Mips_MOVN_I64_I64 = 1142, - Mips_MOVN_I64_S = 1143, - Mips_MOVN_I_D32 = 1144, - Mips_MOVN_I_D32_MM = 1145, - Mips_MOVN_I_D64 = 1146, - Mips_MOVN_I_I = 1147, - Mips_MOVN_I_I64 = 1148, - Mips_MOVN_I_MM = 1149, - Mips_MOVN_I_S = 1150, - Mips_MOVN_I_S_MM = 1151, - Mips_MOVT_D32 = 1152, - Mips_MOVT_D32_MM = 1153, - Mips_MOVT_D64 = 1154, - Mips_MOVT_I = 1155, - Mips_MOVT_I64 = 1156, - Mips_MOVT_I_MM = 1157, - Mips_MOVT_S = 1158, - Mips_MOVT_S_MM = 1159, - Mips_MOVZ_I64_D64 = 1160, - Mips_MOVZ_I64_I = 1161, - Mips_MOVZ_I64_I64 = 1162, - Mips_MOVZ_I64_S = 1163, - Mips_MOVZ_I_D32 = 1164, - Mips_MOVZ_I_D32_MM = 1165, - Mips_MOVZ_I_D64 = 1166, - Mips_MOVZ_I_I = 1167, - Mips_MOVZ_I_I64 = 1168, - Mips_MOVZ_I_MM = 1169, - Mips_MOVZ_I_S = 1170, - Mips_MOVZ_I_S_MM = 1171, - Mips_MSUB = 1172, - Mips_MSUBF_D = 1173, - Mips_MSUBF_S = 1174, - Mips_MSUBR_Q_H = 1175, - Mips_MSUBR_Q_W = 1176, - Mips_MSUBU = 1177, - Mips_MSUBU_DSP = 1178, - Mips_MSUBU_MM = 1179, - Mips_MSUBV_B = 1180, - Mips_MSUBV_D = 1181, - Mips_MSUBV_H = 1182, - Mips_MSUBV_W = 1183, - Mips_MSUB_D32 = 1184, - Mips_MSUB_D32_MM = 1185, - Mips_MSUB_D64 = 1186, - Mips_MSUB_DSP = 1187, - Mips_MSUB_MM = 1188, - Mips_MSUB_Q_H = 1189, - Mips_MSUB_Q_W = 1190, - Mips_MSUB_S = 1191, - Mips_MSUB_S_MM = 1192, - Mips_MTC0 = 1193, - Mips_MTC1 = 1194, - Mips_MTC1_MM = 1195, - Mips_MTC2 = 1196, - Mips_MTHC1_D32 = 1197, - Mips_MTHC1_D64 = 1198, - Mips_MTHC1_MM = 1199, - Mips_MTHI = 1200, - Mips_MTHI64 = 1201, - Mips_MTHI_DSP = 1202, - Mips_MTHI_MM = 1203, - Mips_MTHLIP = 1204, - Mips_MTLO = 1205, - Mips_MTLO64 = 1206, - Mips_MTLO_DSP = 1207, - Mips_MTLO_MM = 1208, - Mips_MTM0 = 1209, - Mips_MTM1 = 1210, - Mips_MTM2 = 1211, - Mips_MTP0 = 1212, - Mips_MTP1 = 1213, - Mips_MTP2 = 1214, - Mips_MUH = 1215, - Mips_MUHU = 1216, - Mips_MUL = 1217, - Mips_MULEQ_S_W_PHL = 1218, - Mips_MULEQ_S_W_PHR = 1219, - Mips_MULEU_S_PH_QBL = 1220, - Mips_MULEU_S_PH_QBR = 1221, - Mips_MULQ_RS_PH = 1222, - Mips_MULQ_RS_W = 1223, - Mips_MULQ_S_PH = 1224, - Mips_MULQ_S_W = 1225, - Mips_MULR_Q_H = 1226, - Mips_MULR_Q_W = 1227, - Mips_MULSAQ_S_W_PH = 1228, - Mips_MULSA_W_PH = 1229, - Mips_MULT = 1230, - Mips_MULTU_DSP = 1231, - Mips_MULT_DSP = 1232, - Mips_MULT_MM = 1233, - Mips_MULTu = 1234, - Mips_MULTu_MM = 1235, - Mips_MULU = 1236, - Mips_MULV_B = 1237, - Mips_MULV_D = 1238, - Mips_MULV_H = 1239, - Mips_MULV_W = 1240, - Mips_MUL_MM = 1241, - Mips_MUL_PH = 1242, - Mips_MUL_Q_H = 1243, - Mips_MUL_Q_W = 1244, - Mips_MUL_R6 = 1245, - Mips_MUL_S_PH = 1246, - Mips_Mfhi16 = 1247, - Mips_Mflo16 = 1248, - Mips_Move32R16 = 1249, - Mips_MoveR3216 = 1250, - Mips_MultRxRy16 = 1251, - Mips_MultRxRyRz16 = 1252, - Mips_MultuRxRy16 = 1253, - Mips_MultuRxRyRz16 = 1254, - Mips_NLOC_B = 1255, - Mips_NLOC_D = 1256, - Mips_NLOC_H = 1257, - Mips_NLOC_W = 1258, - Mips_NLZC_B = 1259, - Mips_NLZC_D = 1260, - Mips_NLZC_H = 1261, - Mips_NLZC_W = 1262, - Mips_NMADD_D32 = 1263, - Mips_NMADD_D32_MM = 1264, - Mips_NMADD_D64 = 1265, - Mips_NMADD_S = 1266, - Mips_NMADD_S_MM = 1267, - Mips_NMSUB_D32 = 1268, - Mips_NMSUB_D32_MM = 1269, - Mips_NMSUB_D64 = 1270, - Mips_NMSUB_S = 1271, - Mips_NMSUB_S_MM = 1272, - Mips_NOP = 1273, - Mips_NOR = 1274, - Mips_NOR64 = 1275, - Mips_NORI_B = 1276, - Mips_NOR_MM = 1277, - Mips_NOR_V = 1278, - Mips_NOR_V_D_PSEUDO = 1279, - Mips_NOR_V_H_PSEUDO = 1280, - Mips_NOR_V_W_PSEUDO = 1281, - Mips_NOT16_MM = 1282, - Mips_NegRxRy16 = 1283, - Mips_NotRxRy16 = 1284, - Mips_OR = 1285, - Mips_OR16_MM = 1286, - Mips_OR64 = 1287, - Mips_ORI_B = 1288, - Mips_OR_MM = 1289, - Mips_OR_V = 1290, - Mips_OR_V_D_PSEUDO = 1291, - Mips_OR_V_H_PSEUDO = 1292, - Mips_OR_V_W_PSEUDO = 1293, - Mips_ORi = 1294, - Mips_ORi64 = 1295, - Mips_ORi_MM = 1296, - Mips_OrRxRxRy16 = 1297, - Mips_PACKRL_PH = 1298, - Mips_PAUSE = 1299, - Mips_PAUSE_MM = 1300, - Mips_PCKEV_B = 1301, - Mips_PCKEV_D = 1302, - Mips_PCKEV_H = 1303, - Mips_PCKEV_W = 1304, - Mips_PCKOD_B = 1305, - Mips_PCKOD_D = 1306, - Mips_PCKOD_H = 1307, - Mips_PCKOD_W = 1308, - Mips_PCNT_B = 1309, - Mips_PCNT_D = 1310, - Mips_PCNT_H = 1311, - Mips_PCNT_W = 1312, - Mips_PICK_PH = 1313, - Mips_PICK_QB = 1314, - Mips_POP = 1315, - Mips_PRECEQU_PH_QBL = 1316, - Mips_PRECEQU_PH_QBLA = 1317, - Mips_PRECEQU_PH_QBR = 1318, - Mips_PRECEQU_PH_QBRA = 1319, - Mips_PRECEQ_W_PHL = 1320, - Mips_PRECEQ_W_PHR = 1321, - Mips_PRECEU_PH_QBL = 1322, - Mips_PRECEU_PH_QBLA = 1323, - Mips_PRECEU_PH_QBR = 1324, - Mips_PRECEU_PH_QBRA = 1325, - Mips_PRECRQU_S_QB_PH = 1326, - Mips_PRECRQ_PH_W = 1327, - Mips_PRECRQ_QB_PH = 1328, - Mips_PRECRQ_RS_PH_W = 1329, - Mips_PRECR_QB_PH = 1330, - Mips_PRECR_SRA_PH_W = 1331, - Mips_PRECR_SRA_R_PH_W = 1332, - Mips_PREF = 1333, - Mips_PREF_MM = 1334, - Mips_PREF_R6 = 1335, - Mips_PREPEND = 1336, - Mips_PseudoCMPU_EQ_QB = 1337, - Mips_PseudoCMPU_LE_QB = 1338, - Mips_PseudoCMPU_LT_QB = 1339, - Mips_PseudoCMP_EQ_PH = 1340, - Mips_PseudoCMP_LE_PH = 1341, - Mips_PseudoCMP_LT_PH = 1342, - Mips_PseudoCVT_D32_W = 1343, - Mips_PseudoCVT_D64_L = 1344, - Mips_PseudoCVT_D64_W = 1345, - Mips_PseudoCVT_S_L = 1346, - Mips_PseudoCVT_S_W = 1347, - Mips_PseudoDMULT = 1348, - Mips_PseudoDMULTu = 1349, - Mips_PseudoDSDIV = 1350, - Mips_PseudoDUDIV = 1351, - Mips_PseudoIndirectBranch = 1352, - Mips_PseudoIndirectBranch64 = 1353, - Mips_PseudoMADD = 1354, - Mips_PseudoMADDU = 1355, - Mips_PseudoMFHI = 1356, - Mips_PseudoMFHI64 = 1357, - Mips_PseudoMFLO = 1358, - Mips_PseudoMFLO64 = 1359, - Mips_PseudoMSUB = 1360, - Mips_PseudoMSUBU = 1361, - Mips_PseudoMTLOHI = 1362, - Mips_PseudoMTLOHI64 = 1363, - Mips_PseudoMTLOHI_DSP = 1364, - Mips_PseudoMULT = 1365, - Mips_PseudoMULTu = 1366, - Mips_PseudoPICK_PH = 1367, - Mips_PseudoPICK_QB = 1368, - Mips_PseudoReturn = 1369, - Mips_PseudoReturn64 = 1370, - Mips_PseudoSDIV = 1371, - Mips_PseudoSELECTFP_F_D32 = 1372, - Mips_PseudoSELECTFP_F_D64 = 1373, - Mips_PseudoSELECTFP_F_I = 1374, - Mips_PseudoSELECTFP_F_I64 = 1375, - Mips_PseudoSELECTFP_F_S = 1376, - Mips_PseudoSELECTFP_T_D32 = 1377, - Mips_PseudoSELECTFP_T_D64 = 1378, - Mips_PseudoSELECTFP_T_I = 1379, - Mips_PseudoSELECTFP_T_I64 = 1380, - Mips_PseudoSELECTFP_T_S = 1381, - Mips_PseudoSELECT_D32 = 1382, - Mips_PseudoSELECT_D64 = 1383, - Mips_PseudoSELECT_I = 1384, - Mips_PseudoSELECT_I64 = 1385, - Mips_PseudoSELECT_S = 1386, - Mips_PseudoUDIV = 1387, - Mips_RADDU_W_QB = 1388, - Mips_RDDSP = 1389, - Mips_RDHWR = 1390, - Mips_RDHWR64 = 1391, - Mips_RDHWR_MM = 1392, - Mips_REPLV_PH = 1393, - Mips_REPLV_QB = 1394, - Mips_REPL_PH = 1395, - Mips_REPL_QB = 1396, - Mips_RINT_D = 1397, - Mips_RINT_S = 1398, - Mips_ROTR = 1399, - Mips_ROTRV = 1400, - Mips_ROTRV_MM = 1401, - Mips_ROTR_MM = 1402, - Mips_ROUND_L_D64 = 1403, - Mips_ROUND_L_S = 1404, - Mips_ROUND_W_D32 = 1405, - Mips_ROUND_W_D64 = 1406, - Mips_ROUND_W_MM = 1407, - Mips_ROUND_W_S = 1408, - Mips_ROUND_W_S_MM = 1409, - Mips_Restore16 = 1410, - Mips_RestoreX16 = 1411, - Mips_RetRA = 1412, - Mips_RetRA16 = 1413, - Mips_SAT_S_B = 1414, - Mips_SAT_S_D = 1415, - Mips_SAT_S_H = 1416, - Mips_SAT_S_W = 1417, - Mips_SAT_U_B = 1418, - Mips_SAT_U_D = 1419, - Mips_SAT_U_H = 1420, - Mips_SAT_U_W = 1421, - Mips_SB = 1422, - Mips_SB16_MM = 1423, - Mips_SB64 = 1424, - Mips_SB_MM = 1425, - Mips_SC = 1426, - Mips_SCD = 1427, - Mips_SCD_R6 = 1428, - Mips_SC_MM = 1429, - Mips_SC_R6 = 1430, - Mips_SD = 1431, - Mips_SDBBP = 1432, - Mips_SDBBP16_MM = 1433, - Mips_SDBBP_MM = 1434, - Mips_SDBBP_R6 = 1435, - Mips_SDC1 = 1436, - Mips_SDC164 = 1437, - Mips_SDC1_MM = 1438, - Mips_SDC2 = 1439, - Mips_SDC2_R6 = 1440, - Mips_SDC3 = 1441, - Mips_SDIV = 1442, - Mips_SDIV_MM = 1443, - Mips_SDL = 1444, - Mips_SDR = 1445, - Mips_SDXC1 = 1446, - Mips_SDXC164 = 1447, - Mips_SEB = 1448, - Mips_SEB64 = 1449, - Mips_SEB_MM = 1450, - Mips_SEH = 1451, - Mips_SEH64 = 1452, - Mips_SEH_MM = 1453, - Mips_SELEQZ = 1454, - Mips_SELEQZ64 = 1455, - Mips_SELEQZ_D = 1456, - Mips_SELEQZ_S = 1457, - Mips_SELNEZ = 1458, - Mips_SELNEZ64 = 1459, - Mips_SELNEZ_D = 1460, - Mips_SELNEZ_S = 1461, - Mips_SEL_D = 1462, - Mips_SEL_S = 1463, - Mips_SEQ = 1464, - Mips_SEQi = 1465, - Mips_SH = 1466, - Mips_SH16_MM = 1467, - Mips_SH64 = 1468, - Mips_SHF_B = 1469, - Mips_SHF_H = 1470, - Mips_SHF_W = 1471, - Mips_SHILO = 1472, - Mips_SHILOV = 1473, - Mips_SHLLV_PH = 1474, - Mips_SHLLV_QB = 1475, - Mips_SHLLV_S_PH = 1476, - Mips_SHLLV_S_W = 1477, - Mips_SHLL_PH = 1478, - Mips_SHLL_QB = 1479, - Mips_SHLL_S_PH = 1480, - Mips_SHLL_S_W = 1481, - Mips_SHRAV_PH = 1482, - Mips_SHRAV_QB = 1483, - Mips_SHRAV_R_PH = 1484, - Mips_SHRAV_R_QB = 1485, - Mips_SHRAV_R_W = 1486, - Mips_SHRA_PH = 1487, - Mips_SHRA_QB = 1488, - Mips_SHRA_R_PH = 1489, - Mips_SHRA_R_QB = 1490, - Mips_SHRA_R_W = 1491, - Mips_SHRLV_PH = 1492, - Mips_SHRLV_QB = 1493, - Mips_SHRL_PH = 1494, - Mips_SHRL_QB = 1495, - Mips_SH_MM = 1496, - Mips_SLDI_B = 1497, - Mips_SLDI_D = 1498, - Mips_SLDI_H = 1499, - Mips_SLDI_W = 1500, - Mips_SLD_B = 1501, - Mips_SLD_D = 1502, - Mips_SLD_H = 1503, - Mips_SLD_W = 1504, - Mips_SLL = 1505, - Mips_SLL16_MM = 1506, - Mips_SLL64_32 = 1507, - Mips_SLL64_64 = 1508, - Mips_SLLI_B = 1509, - Mips_SLLI_D = 1510, - Mips_SLLI_H = 1511, - Mips_SLLI_W = 1512, - Mips_SLLV = 1513, - Mips_SLLV_MM = 1514, - Mips_SLL_B = 1515, - Mips_SLL_D = 1516, - Mips_SLL_H = 1517, - Mips_SLL_MM = 1518, - Mips_SLL_W = 1519, - Mips_SLT = 1520, - Mips_SLT64 = 1521, - Mips_SLT_MM = 1522, - Mips_SLTi = 1523, - Mips_SLTi64 = 1524, - Mips_SLTi_MM = 1525, - Mips_SLTiu = 1526, - Mips_SLTiu64 = 1527, - Mips_SLTiu_MM = 1528, - Mips_SLTu = 1529, - Mips_SLTu64 = 1530, - Mips_SLTu_MM = 1531, - Mips_SNE = 1532, - Mips_SNEi = 1533, - Mips_SNZ_B_PSEUDO = 1534, - Mips_SNZ_D_PSEUDO = 1535, - Mips_SNZ_H_PSEUDO = 1536, - Mips_SNZ_V_PSEUDO = 1537, - Mips_SNZ_W_PSEUDO = 1538, - Mips_SPLATI_B = 1539, - Mips_SPLATI_D = 1540, - Mips_SPLATI_H = 1541, - Mips_SPLATI_W = 1542, - Mips_SPLAT_B = 1543, - Mips_SPLAT_D = 1544, - Mips_SPLAT_H = 1545, - Mips_SPLAT_W = 1546, - Mips_SRA = 1547, - Mips_SRAI_B = 1548, - Mips_SRAI_D = 1549, - Mips_SRAI_H = 1550, - Mips_SRAI_W = 1551, - Mips_SRARI_B = 1552, - Mips_SRARI_D = 1553, - Mips_SRARI_H = 1554, - Mips_SRARI_W = 1555, - Mips_SRAR_B = 1556, - Mips_SRAR_D = 1557, - Mips_SRAR_H = 1558, - Mips_SRAR_W = 1559, - Mips_SRAV = 1560, - Mips_SRAV_MM = 1561, - Mips_SRA_B = 1562, - Mips_SRA_D = 1563, - Mips_SRA_H = 1564, - Mips_SRA_MM = 1565, - Mips_SRA_W = 1566, - Mips_SRL = 1567, - Mips_SRL16_MM = 1568, - Mips_SRLI_B = 1569, - Mips_SRLI_D = 1570, - Mips_SRLI_H = 1571, - Mips_SRLI_W = 1572, - Mips_SRLRI_B = 1573, - Mips_SRLRI_D = 1574, - Mips_SRLRI_H = 1575, - Mips_SRLRI_W = 1576, - Mips_SRLR_B = 1577, - Mips_SRLR_D = 1578, - Mips_SRLR_H = 1579, - Mips_SRLR_W = 1580, - Mips_SRLV = 1581, - Mips_SRLV_MM = 1582, - Mips_SRL_B = 1583, - Mips_SRL_D = 1584, - Mips_SRL_H = 1585, - Mips_SRL_MM = 1586, - Mips_SRL_W = 1587, - Mips_SSNOP = 1588, - Mips_SSNOP_MM = 1589, - Mips_STORE_ACC128 = 1590, - Mips_STORE_ACC64 = 1591, - Mips_STORE_ACC64DSP = 1592, - Mips_STORE_CCOND_DSP = 1593, - Mips_ST_B = 1594, - Mips_ST_D = 1595, - Mips_ST_H = 1596, - Mips_ST_W = 1597, - Mips_SUB = 1598, - Mips_SUBQH_PH = 1599, - Mips_SUBQH_R_PH = 1600, - Mips_SUBQH_R_W = 1601, - Mips_SUBQH_W = 1602, - Mips_SUBQ_PH = 1603, - Mips_SUBQ_S_PH = 1604, - Mips_SUBQ_S_W = 1605, - Mips_SUBSUS_U_B = 1606, - Mips_SUBSUS_U_D = 1607, - Mips_SUBSUS_U_H = 1608, - Mips_SUBSUS_U_W = 1609, - Mips_SUBSUU_S_B = 1610, - Mips_SUBSUU_S_D = 1611, - Mips_SUBSUU_S_H = 1612, - Mips_SUBSUU_S_W = 1613, - Mips_SUBS_S_B = 1614, - Mips_SUBS_S_D = 1615, - Mips_SUBS_S_H = 1616, - Mips_SUBS_S_W = 1617, - Mips_SUBS_U_B = 1618, - Mips_SUBS_U_D = 1619, - Mips_SUBS_U_H = 1620, - Mips_SUBS_U_W = 1621, - Mips_SUBU16_MM = 1622, - Mips_SUBUH_QB = 1623, - Mips_SUBUH_R_QB = 1624, - Mips_SUBU_PH = 1625, - Mips_SUBU_QB = 1626, - Mips_SUBU_S_PH = 1627, - Mips_SUBU_S_QB = 1628, - Mips_SUBVI_B = 1629, - Mips_SUBVI_D = 1630, - Mips_SUBVI_H = 1631, - Mips_SUBVI_W = 1632, - Mips_SUBV_B = 1633, - Mips_SUBV_D = 1634, - Mips_SUBV_H = 1635, - Mips_SUBV_W = 1636, - Mips_SUB_MM = 1637, - Mips_SUBu = 1638, - Mips_SUBu_MM = 1639, - Mips_SUXC1 = 1640, - Mips_SUXC164 = 1641, - Mips_SUXC1_MM = 1642, - Mips_SW = 1643, - Mips_SW16_MM = 1644, - Mips_SW64 = 1645, - Mips_SWC1 = 1646, - Mips_SWC1_MM = 1647, - Mips_SWC2 = 1648, - Mips_SWC2_R6 = 1649, - Mips_SWC3 = 1650, - Mips_SWL = 1651, - Mips_SWL64 = 1652, - Mips_SWL_MM = 1653, - Mips_SWM16_MM = 1654, - Mips_SWM32_MM = 1655, - Mips_SWM_MM = 1656, - Mips_SWP_MM = 1657, - Mips_SWR = 1658, - Mips_SWR64 = 1659, - Mips_SWR_MM = 1660, - Mips_SWSP_MM = 1661, - Mips_SWXC1 = 1662, - Mips_SWXC1_MM = 1663, - Mips_SW_MM = 1664, - Mips_SYNC = 1665, - Mips_SYNCI = 1666, - Mips_SYNC_MM = 1667, - Mips_SYSCALL = 1668, - Mips_SYSCALL_MM = 1669, - Mips_SZ_B_PSEUDO = 1670, - Mips_SZ_D_PSEUDO = 1671, - Mips_SZ_H_PSEUDO = 1672, - Mips_SZ_V_PSEUDO = 1673, - Mips_SZ_W_PSEUDO = 1674, - Mips_Save16 = 1675, - Mips_SaveX16 = 1676, - Mips_SbRxRyOffMemX16 = 1677, - Mips_SebRx16 = 1678, - Mips_SehRx16 = 1679, - Mips_SelBeqZ = 1680, - Mips_SelBneZ = 1681, - Mips_SelTBteqZCmp = 1682, - Mips_SelTBteqZCmpi = 1683, - Mips_SelTBteqZSlt = 1684, - Mips_SelTBteqZSlti = 1685, - Mips_SelTBteqZSltiu = 1686, - Mips_SelTBteqZSltu = 1687, - Mips_SelTBtneZCmp = 1688, - Mips_SelTBtneZCmpi = 1689, - Mips_SelTBtneZSlt = 1690, - Mips_SelTBtneZSlti = 1691, - Mips_SelTBtneZSltiu = 1692, - Mips_SelTBtneZSltu = 1693, - Mips_ShRxRyOffMemX16 = 1694, - Mips_SllX16 = 1695, - Mips_SllvRxRy16 = 1696, - Mips_SltCCRxRy16 = 1697, - Mips_SltRxRy16 = 1698, - Mips_SltiCCRxImmX16 = 1699, - Mips_SltiRxImm16 = 1700, - Mips_SltiRxImmX16 = 1701, - Mips_SltiuCCRxImmX16 = 1702, - Mips_SltiuRxImm16 = 1703, - Mips_SltiuRxImmX16 = 1704, - Mips_SltuCCRxRy16 = 1705, - Mips_SltuRxRy16 = 1706, - Mips_SltuRxRyRz16 = 1707, - Mips_SraX16 = 1708, - Mips_SravRxRy16 = 1709, - Mips_SrlX16 = 1710, - Mips_SrlvRxRy16 = 1711, - Mips_SubuRxRyRz16 = 1712, - Mips_SwRxRyOffMemX16 = 1713, - Mips_SwRxSpImmX16 = 1714, - Mips_TAILCALL = 1715, - Mips_TAILCALL64_R = 1716, - Mips_TAILCALL_R = 1717, - Mips_TEQ = 1718, - Mips_TEQI = 1719, - Mips_TEQI_MM = 1720, - Mips_TEQ_MM = 1721, - Mips_TGE = 1722, - Mips_TGEI = 1723, - Mips_TGEIU = 1724, - Mips_TGEIU_MM = 1725, - Mips_TGEI_MM = 1726, - Mips_TGEU = 1727, - Mips_TGEU_MM = 1728, - Mips_TGE_MM = 1729, - Mips_TLBP = 1730, - Mips_TLBP_MM = 1731, - Mips_TLBR = 1732, - Mips_TLBR_MM = 1733, - Mips_TLBWI = 1734, - Mips_TLBWI_MM = 1735, - Mips_TLBWR = 1736, - Mips_TLBWR_MM = 1737, - Mips_TLT = 1738, - Mips_TLTI = 1739, - Mips_TLTIU_MM = 1740, - Mips_TLTI_MM = 1741, - Mips_TLTU = 1742, - Mips_TLTU_MM = 1743, - Mips_TLT_MM = 1744, - Mips_TNE = 1745, - Mips_TNEI = 1746, - Mips_TNEI_MM = 1747, - Mips_TNE_MM = 1748, - Mips_TRAP = 1749, - Mips_TRUNC_L_D64 = 1750, - Mips_TRUNC_L_S = 1751, - Mips_TRUNC_W_D32 = 1752, - Mips_TRUNC_W_D64 = 1753, - Mips_TRUNC_W_MM = 1754, - Mips_TRUNC_W_S = 1755, - Mips_TRUNC_W_S_MM = 1756, - Mips_TTLTIU = 1757, - Mips_UDIV = 1758, - Mips_UDIV_MM = 1759, - Mips_V3MULU = 1760, - Mips_VMM0 = 1761, - Mips_VMULU = 1762, - Mips_VSHF_B = 1763, - Mips_VSHF_D = 1764, - Mips_VSHF_H = 1765, - Mips_VSHF_W = 1766, - Mips_WAIT = 1767, - Mips_WAIT_MM = 1768, - Mips_WRDSP = 1769, - Mips_WSBH = 1770, - Mips_WSBH_MM = 1771, - Mips_XOR = 1772, - Mips_XOR16_MM = 1773, - Mips_XOR64 = 1774, - Mips_XORI_B = 1775, - Mips_XOR_MM = 1776, - Mips_XOR_V = 1777, - Mips_XOR_V_D_PSEUDO = 1778, - Mips_XOR_V_H_PSEUDO = 1779, - Mips_XOR_V_W_PSEUDO = 1780, - Mips_XORi = 1781, - Mips_XORi64 = 1782, - Mips_XORi_MM = 1783, - Mips_XorRxRxRy16 = 1784, - Mips_INSTRUCTION_LIST_END = 1785 -}; - -#endif // GET_INSTRINFO_ENUM diff --git a/arch/Mips/MipsGenRegisterInfo.inc b/arch/Mips/MipsGenRegisterInfo.inc deleted file mode 100644 index 4501a407fd..0000000000 --- a/arch/Mips/MipsGenRegisterInfo.inc +++ /dev/null @@ -1,1679 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Target Register Enum Values *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2019 */ - - -#ifdef GET_REGINFO_ENUM -#undef GET_REGINFO_ENUM - -enum { - Mips_NoRegister, - Mips_AT = 1, - Mips_DSPCCond = 2, - Mips_DSPCarry = 3, - Mips_DSPEFI = 4, - Mips_DSPOutFlag = 5, - Mips_DSPPos = 6, - Mips_DSPSCount = 7, - Mips_FP = 8, - Mips_GP = 9, - Mips_MSAAccess = 10, - Mips_MSACSR = 11, - Mips_MSAIR = 12, - Mips_MSAMap = 13, - Mips_MSAModify = 14, - Mips_MSARequest = 15, - Mips_MSASave = 16, - Mips_MSAUnmap = 17, - Mips_PC = 18, - Mips_RA = 19, - Mips_SP = 20, - Mips_ZERO = 21, - Mips_A0 = 22, - Mips_A1 = 23, - Mips_A2 = 24, - Mips_A3 = 25, - Mips_AC0 = 26, - Mips_AC1 = 27, - Mips_AC2 = 28, - Mips_AC3 = 29, - Mips_AT_64 = 30, - Mips_CC0 = 31, - Mips_CC1 = 32, - Mips_CC2 = 33, - Mips_CC3 = 34, - Mips_CC4 = 35, - Mips_CC5 = 36, - Mips_CC6 = 37, - Mips_CC7 = 38, - Mips_COP20 = 39, - Mips_COP21 = 40, - Mips_COP22 = 41, - Mips_COP23 = 42, - Mips_COP24 = 43, - Mips_COP25 = 44, - Mips_COP26 = 45, - Mips_COP27 = 46, - Mips_COP28 = 47, - Mips_COP29 = 48, - Mips_COP30 = 49, - Mips_COP31 = 50, - Mips_COP32 = 51, - Mips_COP33 = 52, - Mips_COP34 = 53, - Mips_COP35 = 54, - Mips_COP36 = 55, - Mips_COP37 = 56, - Mips_COP38 = 57, - Mips_COP39 = 58, - Mips_COP210 = 59, - Mips_COP211 = 60, - Mips_COP212 = 61, - Mips_COP213 = 62, - Mips_COP214 = 63, - Mips_COP215 = 64, - Mips_COP216 = 65, - Mips_COP217 = 66, - Mips_COP218 = 67, - Mips_COP219 = 68, - Mips_COP220 = 69, - Mips_COP221 = 70, - Mips_COP222 = 71, - Mips_COP223 = 72, - Mips_COP224 = 73, - Mips_COP225 = 74, - Mips_COP226 = 75, - Mips_COP227 = 76, - Mips_COP228 = 77, - Mips_COP229 = 78, - Mips_COP230 = 79, - Mips_COP231 = 80, - Mips_COP310 = 81, - Mips_COP311 = 82, - Mips_COP312 = 83, - Mips_COP313 = 84, - Mips_COP314 = 85, - Mips_COP315 = 86, - Mips_COP316 = 87, - Mips_COP317 = 88, - Mips_COP318 = 89, - Mips_COP319 = 90, - Mips_COP320 = 91, - Mips_COP321 = 92, - Mips_COP322 = 93, - Mips_COP323 = 94, - Mips_COP324 = 95, - Mips_COP325 = 96, - Mips_COP326 = 97, - Mips_COP327 = 98, - Mips_COP328 = 99, - Mips_COP329 = 100, - Mips_COP330 = 101, - Mips_COP331 = 102, - Mips_D0 = 103, - Mips_D1 = 104, - Mips_D2 = 105, - Mips_D3 = 106, - Mips_D4 = 107, - Mips_D5 = 108, - Mips_D6 = 109, - Mips_D7 = 110, - Mips_D8 = 111, - Mips_D9 = 112, - Mips_D10 = 113, - Mips_D11 = 114, - Mips_D12 = 115, - Mips_D13 = 116, - Mips_D14 = 117, - Mips_D15 = 118, - Mips_DSPOutFlag20 = 119, - Mips_DSPOutFlag21 = 120, - Mips_DSPOutFlag22 = 121, - Mips_DSPOutFlag23 = 122, - Mips_F0 = 123, - Mips_F1 = 124, - Mips_F2 = 125, - Mips_F3 = 126, - Mips_F4 = 127, - Mips_F5 = 128, - Mips_F6 = 129, - Mips_F7 = 130, - Mips_F8 = 131, - Mips_F9 = 132, - Mips_F10 = 133, - Mips_F11 = 134, - Mips_F12 = 135, - Mips_F13 = 136, - Mips_F14 = 137, - Mips_F15 = 138, - Mips_F16 = 139, - Mips_F17 = 140, - Mips_F18 = 141, - Mips_F19 = 142, - Mips_F20 = 143, - Mips_F21 = 144, - Mips_F22 = 145, - Mips_F23 = 146, - Mips_F24 = 147, - Mips_F25 = 148, - Mips_F26 = 149, - Mips_F27 = 150, - Mips_F28 = 151, - Mips_F29 = 152, - Mips_F30 = 153, - Mips_F31 = 154, - Mips_FCC0 = 155, - Mips_FCC1 = 156, - Mips_FCC2 = 157, - Mips_FCC3 = 158, - Mips_FCC4 = 159, - Mips_FCC5 = 160, - Mips_FCC6 = 161, - Mips_FCC7 = 162, - Mips_FCR0 = 163, - Mips_FCR1 = 164, - Mips_FCR2 = 165, - Mips_FCR3 = 166, - Mips_FCR4 = 167, - Mips_FCR5 = 168, - Mips_FCR6 = 169, - Mips_FCR7 = 170, - Mips_FCR8 = 171, - Mips_FCR9 = 172, - Mips_FCR10 = 173, - Mips_FCR11 = 174, - Mips_FCR12 = 175, - Mips_FCR13 = 176, - Mips_FCR14 = 177, - Mips_FCR15 = 178, - Mips_FCR16 = 179, - Mips_FCR17 = 180, - Mips_FCR18 = 181, - Mips_FCR19 = 182, - Mips_FCR20 = 183, - Mips_FCR21 = 184, - Mips_FCR22 = 185, - Mips_FCR23 = 186, - Mips_FCR24 = 187, - Mips_FCR25 = 188, - Mips_FCR26 = 189, - Mips_FCR27 = 190, - Mips_FCR28 = 191, - Mips_FCR29 = 192, - Mips_FCR30 = 193, - Mips_FCR31 = 194, - Mips_FP_64 = 195, - Mips_F_HI0 = 196, - Mips_F_HI1 = 197, - Mips_F_HI2 = 198, - Mips_F_HI3 = 199, - Mips_F_HI4 = 200, - Mips_F_HI5 = 201, - Mips_F_HI6 = 202, - Mips_F_HI7 = 203, - Mips_F_HI8 = 204, - Mips_F_HI9 = 205, - Mips_F_HI10 = 206, - Mips_F_HI11 = 207, - Mips_F_HI12 = 208, - Mips_F_HI13 = 209, - Mips_F_HI14 = 210, - Mips_F_HI15 = 211, - Mips_F_HI16 = 212, - Mips_F_HI17 = 213, - Mips_F_HI18 = 214, - Mips_F_HI19 = 215, - Mips_F_HI20 = 216, - Mips_F_HI21 = 217, - Mips_F_HI22 = 218, - Mips_F_HI23 = 219, - Mips_F_HI24 = 220, - Mips_F_HI25 = 221, - Mips_F_HI26 = 222, - Mips_F_HI27 = 223, - Mips_F_HI28 = 224, - Mips_F_HI29 = 225, - Mips_F_HI30 = 226, - Mips_F_HI31 = 227, - Mips_GP_64 = 228, - Mips_HI0 = 229, - Mips_HI1 = 230, - Mips_HI2 = 231, - Mips_HI3 = 232, - Mips_HWR0 = 233, - Mips_HWR1 = 234, - Mips_HWR2 = 235, - Mips_HWR3 = 236, - Mips_HWR4 = 237, - Mips_HWR5 = 238, - Mips_HWR6 = 239, - Mips_HWR7 = 240, - Mips_HWR8 = 241, - Mips_HWR9 = 242, - Mips_HWR10 = 243, - Mips_HWR11 = 244, - Mips_HWR12 = 245, - Mips_HWR13 = 246, - Mips_HWR14 = 247, - Mips_HWR15 = 248, - Mips_HWR16 = 249, - Mips_HWR17 = 250, - Mips_HWR18 = 251, - Mips_HWR19 = 252, - Mips_HWR20 = 253, - Mips_HWR21 = 254, - Mips_HWR22 = 255, - Mips_HWR23 = 256, - Mips_HWR24 = 257, - Mips_HWR25 = 258, - Mips_HWR26 = 259, - Mips_HWR27 = 260, - Mips_HWR28 = 261, - Mips_HWR29 = 262, - Mips_HWR30 = 263, - Mips_HWR31 = 264, - Mips_K0 = 265, - Mips_K1 = 266, - Mips_LO0 = 267, - Mips_LO1 = 268, - Mips_LO2 = 269, - Mips_LO3 = 270, - Mips_MPL0 = 271, - Mips_MPL1 = 272, - Mips_MPL2 = 273, - Mips_P0 = 274, - Mips_P1 = 275, - Mips_P2 = 276, - Mips_RA_64 = 277, - Mips_S0 = 278, - Mips_S1 = 279, - Mips_S2 = 280, - Mips_S3 = 281, - Mips_S4 = 282, - Mips_S5 = 283, - Mips_S6 = 284, - Mips_S7 = 285, - Mips_SP_64 = 286, - Mips_T0 = 287, - Mips_T1 = 288, - Mips_T2 = 289, - Mips_T3 = 290, - Mips_T4 = 291, - Mips_T5 = 292, - Mips_T6 = 293, - Mips_T7 = 294, - Mips_T8 = 295, - Mips_T9 = 296, - Mips_V0 = 297, - Mips_V1 = 298, - Mips_W0 = 299, - Mips_W1 = 300, - Mips_W2 = 301, - Mips_W3 = 302, - Mips_W4 = 303, - Mips_W5 = 304, - Mips_W6 = 305, - Mips_W7 = 306, - Mips_W8 = 307, - Mips_W9 = 308, - Mips_W10 = 309, - Mips_W11 = 310, - Mips_W12 = 311, - Mips_W13 = 312, - Mips_W14 = 313, - Mips_W15 = 314, - Mips_W16 = 315, - Mips_W17 = 316, - Mips_W18 = 317, - Mips_W19 = 318, - Mips_W20 = 319, - Mips_W21 = 320, - Mips_W22 = 321, - Mips_W23 = 322, - Mips_W24 = 323, - Mips_W25 = 324, - Mips_W26 = 325, - Mips_W27 = 326, - Mips_W28 = 327, - Mips_W29 = 328, - Mips_W30 = 329, - Mips_W31 = 330, - Mips_ZERO_64 = 331, - Mips_A0_64 = 332, - Mips_A1_64 = 333, - Mips_A2_64 = 334, - Mips_A3_64 = 335, - Mips_AC0_64 = 336, - Mips_D0_64 = 337, - Mips_D1_64 = 338, - Mips_D2_64 = 339, - Mips_D3_64 = 340, - Mips_D4_64 = 341, - Mips_D5_64 = 342, - Mips_D6_64 = 343, - Mips_D7_64 = 344, - Mips_D8_64 = 345, - Mips_D9_64 = 346, - Mips_D10_64 = 347, - Mips_D11_64 = 348, - Mips_D12_64 = 349, - Mips_D13_64 = 350, - Mips_D14_64 = 351, - Mips_D15_64 = 352, - Mips_D16_64 = 353, - Mips_D17_64 = 354, - Mips_D18_64 = 355, - Mips_D19_64 = 356, - Mips_D20_64 = 357, - Mips_D21_64 = 358, - Mips_D22_64 = 359, - Mips_D23_64 = 360, - Mips_D24_64 = 361, - Mips_D25_64 = 362, - Mips_D26_64 = 363, - Mips_D27_64 = 364, - Mips_D28_64 = 365, - Mips_D29_64 = 366, - Mips_D30_64 = 367, - Mips_D31_64 = 368, - Mips_DSPOutFlag16_19 = 369, - Mips_HI0_64 = 370, - Mips_K0_64 = 371, - Mips_K1_64 = 372, - Mips_LO0_64 = 373, - Mips_S0_64 = 374, - Mips_S1_64 = 375, - Mips_S2_64 = 376, - Mips_S3_64 = 377, - Mips_S4_64 = 378, - Mips_S5_64 = 379, - Mips_S6_64 = 380, - Mips_S7_64 = 381, - Mips_T0_64 = 382, - Mips_T1_64 = 383, - Mips_T2_64 = 384, - Mips_T3_64 = 385, - Mips_T4_64 = 386, - Mips_T5_64 = 387, - Mips_T6_64 = 388, - Mips_T7_64 = 389, - Mips_T8_64 = 390, - Mips_T9_64 = 391, - Mips_V0_64 = 392, - Mips_V1_64 = 393, - Mips_NUM_TARGET_REGS // 394 -}; - -// Register classes -enum { - Mips_OddSPRegClassID = 0, - Mips_CCRRegClassID = 1, - Mips_COP2RegClassID = 2, - Mips_COP3RegClassID = 3, - Mips_DSPRRegClassID = 4, - Mips_FGR32RegClassID = 5, - Mips_FGRCCRegClassID = 6, - Mips_FGRH32RegClassID = 7, - Mips_GPR32RegClassID = 8, - Mips_HWRegsRegClassID = 9, - Mips_OddSP_with_sub_hiRegClassID = 10, - Mips_FGR32_and_OddSPRegClassID = 11, - Mips_FGRH32_and_OddSPRegClassID = 12, - Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13, - Mips_CPU16RegsPlusSPRegClassID = 14, - Mips_CCRegClassID = 15, - Mips_CPU16RegsRegClassID = 16, - Mips_FCCRegClassID = 17, - Mips_GPRMM16RegClassID = 18, - Mips_GPRMM16MovePRegClassID = 19, - Mips_GPRMM16ZeroRegClassID = 20, - Mips_MSACtrlRegClassID = 21, - Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22, - Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 23, - Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 24, - Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25, - Mips_HI32DSPRegClassID = 26, - Mips_LO32DSPRegClassID = 27, - Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, - Mips_CPURARegRegClassID = 29, - Mips_CPUSPRegRegClassID = 30, - Mips_DSPCCRegClassID = 31, - Mips_HI32RegClassID = 32, - Mips_LO32RegClassID = 33, - Mips_FGR64RegClassID = 34, - Mips_GPR64RegClassID = 35, - Mips_AFGR64RegClassID = 36, - Mips_FGR64_and_OddSPRegClassID = 37, - Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38, - Mips_AFGR64_and_OddSPRegClassID = 39, - Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 40, - Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41, - Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42, - Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43, - Mips_ACC64DSPRegClassID = 44, - Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45, - Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46, - Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47, - Mips_OCTEON_MPLRegClassID = 48, - Mips_OCTEON_PRegClassID = 49, - Mips_ACC64RegClassID = 50, - Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 51, - Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 52, - Mips_HI64RegClassID = 53, - Mips_LO64RegClassID = 54, - Mips_MSA128BRegClassID = 55, - Mips_MSA128DRegClassID = 56, - Mips_MSA128HRegClassID = 57, - Mips_MSA128WRegClassID = 58, - Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 59, - Mips_MSA128WEvensRegClassID = 60, - Mips_ACC128RegClassID = 61, -}; - -#endif // GET_REGINFO_ENUM - -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*MC Register Information *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2019 */ - - -#ifdef GET_REGINFO_MC_DESC -#undef GET_REGINFO_MC_DESC - -static const MCPhysReg MipsRegDiffLists[] = { - /* 0 */ 0, 0, - /* 2 */ 4, 1, 1, 1, 1, 0, - /* 8 */ 364, 65286, 1, 1, 1, 0, - /* 14 */ 20, 1, 0, - /* 17 */ 21, 1, 0, - /* 20 */ 22, 1, 0, - /* 23 */ 23, 1, 0, - /* 26 */ 24, 1, 0, - /* 29 */ 25, 1, 0, - /* 32 */ 26, 1, 0, - /* 35 */ 27, 1, 0, - /* 38 */ 28, 1, 0, - /* 41 */ 29, 1, 0, - /* 44 */ 30, 1, 0, - /* 47 */ 31, 1, 0, - /* 50 */ 32, 1, 0, - /* 53 */ 33, 1, 0, - /* 56 */ 34, 1, 0, - /* 59 */ 35, 1, 0, - /* 62 */ 65439, 1, 0, - /* 65 */ 65513, 1, 0, - /* 68 */ 3, 0, - /* 70 */ 4, 0, - /* 72 */ 6, 0, - /* 74 */ 11, 0, - /* 76 */ 12, 0, - /* 78 */ 22, 0, - /* 80 */ 23, 0, - /* 82 */ 29, 0, - /* 84 */ 30, 0, - /* 86 */ 65308, 72, 0, - /* 89 */ 65346, 72, 0, - /* 92 */ 38, 65322, 73, 0, - /* 96 */ 95, 0, - /* 98 */ 96, 0, - /* 100 */ 106, 0, - /* 102 */ 187, 0, - /* 104 */ 219, 0, - /* 106 */ 258, 0, - /* 108 */ 266, 0, - /* 110 */ 310, 0, - /* 112 */ 65031, 0, - /* 114 */ 65108, 0, - /* 116 */ 65172, 0, - /* 118 */ 65226, 0, - /* 120 */ 65229, 0, - /* 122 */ 65270, 0, - /* 124 */ 65278, 0, - /* 126 */ 65295, 0, - /* 128 */ 65317, 0, - /* 130 */ 37, 65430, 103, 65395, 65333, 0, - /* 136 */ 65349, 0, - /* 138 */ 65395, 0, - /* 140 */ 65410, 0, - /* 142 */ 65415, 0, - /* 144 */ 65419, 0, - /* 146 */ 65420, 0, - /* 148 */ 65421, 0, - /* 150 */ 65422, 0, - /* 152 */ 65430, 0, - /* 154 */ 65440, 0, - /* 156 */ 65441, 0, - /* 158 */ 141, 65498, 0, - /* 161 */ 65516, 234, 65498, 0, - /* 165 */ 65515, 235, 65498, 0, - /* 169 */ 65514, 236, 65498, 0, - /* 173 */ 65513, 237, 65498, 0, - /* 177 */ 65512, 238, 65498, 0, - /* 181 */ 65511, 239, 65498, 0, - /* 185 */ 65510, 240, 65498, 0, - /* 189 */ 65509, 241, 65498, 0, - /* 193 */ 65508, 242, 65498, 0, - /* 197 */ 65507, 243, 65498, 0, - /* 201 */ 65506, 244, 65498, 0, - /* 205 */ 65505, 245, 65498, 0, - /* 209 */ 65504, 246, 65498, 0, - /* 213 */ 65503, 247, 65498, 0, - /* 217 */ 65502, 248, 65498, 0, - /* 221 */ 65501, 249, 65498, 0, - /* 225 */ 65500, 250, 65498, 0, - /* 229 */ 65295, 347, 65499, 0, - /* 233 */ 65333, 344, 65502, 0, - /* 237 */ 65507, 0, - /* 239 */ 65510, 0, - /* 241 */ 65511, 0, - /* 243 */ 65512, 0, - /* 245 */ 65516, 0, - /* 247 */ 65521, 0, - /* 249 */ 65522, 0, - /* 251 */ 65535, 0, -}; - -static const uint16_t MipsSubRegIdxLists[] = { - /* 0 */ 1, 0, - /* 2 */ 3, 4, 5, 6, 7, 0, - /* 8 */ 2, 9, 8, 0, - /* 12 */ 9, 1, 8, 10, 11, 0, -}; - -static const MCRegisterDesc MipsRegDesc[] = { // Descriptors - { 6, 0, 0, 0, 0, 0 }, - { 2007, 1, 82, 1, 4017, 0 }, - { 2010, 1, 1, 1, 4017, 0 }, - { 2102, 1, 1, 1, 4017, 0 }, - { 1973, 1, 1, 1, 4017, 0 }, - { 2027, 8, 1, 2, 32, 4 }, - { 2054, 1, 1, 1, 1089, 0 }, - { 2071, 1, 1, 1, 1089, 0 }, - { 1985, 1, 102, 1, 1089, 0 }, - { 1988, 1, 104, 1, 1089, 0 }, - { 2061, 1, 1, 1, 1089, 0 }, - { 2000, 1, 1, 1, 1089, 0 }, - { 1994, 1, 1, 1, 1089, 0 }, - { 2038, 1, 1, 1, 1089, 0 }, - { 2092, 1, 1, 1, 1089, 0 }, - { 2081, 1, 1, 1, 1089, 0 }, - { 2019, 1, 1, 1, 1089, 0 }, - { 2045, 1, 1, 1, 1089, 0 }, - { 1970, 1, 1, 1, 1089, 0 }, - { 1967, 1, 106, 1, 1089, 0 }, - { 1991, 1, 108, 1, 1089, 0 }, - { 1980, 1, 110, 1, 1089, 0 }, - { 152, 1, 110, 1, 1089, 0 }, - { 365, 1, 110, 1, 1089, 0 }, - { 537, 1, 110, 1, 1089, 0 }, - { 703, 1, 110, 1, 1089, 0 }, - { 155, 190, 110, 9, 1042, 10 }, - { 368, 190, 1, 9, 1042, 10 }, - { 540, 190, 1, 9, 1042, 10 }, - { 706, 190, 1, 9, 1042, 10 }, - { 1271, 237, 1, 0, 0, 2 }, - { 160, 1, 1, 1, 1153, 0 }, - { 373, 1, 1, 1, 1153, 0 }, - { 545, 1, 1, 1, 1153, 0 }, - { 711, 1, 1, 1, 1153, 0 }, - { 1278, 1, 1, 1, 1153, 0 }, - { 1412, 1, 1, 1, 1153, 0 }, - { 1542, 1, 1, 1, 1153, 0 }, - { 1672, 1, 1, 1, 1153, 0 }, - { 70, 1, 1, 1, 1153, 0 }, - { 283, 1, 1, 1, 1153, 0 }, - { 496, 1, 1, 1, 1153, 0 }, - { 662, 1, 1, 1, 1153, 0 }, - { 820, 1, 1, 1, 1153, 0 }, - { 1383, 1, 1, 1, 1153, 0 }, - { 1513, 1, 1, 1, 1153, 0 }, - { 1643, 1, 1, 1, 1153, 0 }, - { 1773, 1, 1, 1, 1153, 0 }, - { 1911, 1, 1, 1, 1153, 0 }, - { 130, 1, 1, 1, 1153, 0 }, - { 343, 1, 1, 1, 1153, 0 }, - { 531, 1, 1, 1, 1153, 0 }, - { 697, 1, 1, 1, 1153, 0 }, - { 842, 1, 1, 1, 1153, 0 }, - { 1405, 1, 1, 1, 1153, 0 }, - { 1535, 1, 1, 1, 1153, 0 }, - { 1665, 1, 1, 1, 1153, 0 }, - { 1795, 1, 1, 1, 1153, 0 }, - { 1933, 1, 1, 1, 1153, 0 }, - { 0, 1, 1, 1, 1153, 0 }, - { 213, 1, 1, 1, 1153, 0 }, - { 426, 1, 1, 1, 1153, 0 }, - { 592, 1, 1, 1, 1153, 0 }, - { 750, 1, 1, 1, 1153, 0 }, - { 1313, 1, 1, 1, 1153, 0 }, - { 1447, 1, 1, 1, 1153, 0 }, - { 1577, 1, 1, 1, 1153, 0 }, - { 1707, 1, 1, 1, 1153, 0 }, - { 1829, 1, 1, 1, 1153, 0 }, - { 45, 1, 1, 1, 1153, 0 }, - { 258, 1, 1, 1, 1153, 0 }, - { 471, 1, 1, 1, 1153, 0 }, - { 637, 1, 1, 1, 1153, 0 }, - { 795, 1, 1, 1, 1153, 0 }, - { 1358, 1, 1, 1, 1153, 0 }, - { 1488, 1, 1, 1, 1153, 0 }, - { 1618, 1, 1, 1, 1153, 0 }, - { 1748, 1, 1, 1, 1153, 0 }, - { 1886, 1, 1, 1, 1153, 0 }, - { 105, 1, 1, 1, 1153, 0 }, - { 318, 1, 1, 1, 1153, 0 }, - { 7, 1, 1, 1, 1153, 0 }, - { 220, 1, 1, 1, 1153, 0 }, - { 433, 1, 1, 1, 1153, 0 }, - { 599, 1, 1, 1, 1153, 0 }, - { 757, 1, 1, 1, 1153, 0 }, - { 1320, 1, 1, 1, 1153, 0 }, - { 1454, 1, 1, 1, 1153, 0 }, - { 1584, 1, 1, 1, 1153, 0 }, - { 1714, 1, 1, 1, 1153, 0 }, - { 1836, 1, 1, 1, 1153, 0 }, - { 52, 1, 1, 1, 1153, 0 }, - { 265, 1, 1, 1, 1153, 0 }, - { 478, 1, 1, 1, 1153, 0 }, - { 644, 1, 1, 1, 1153, 0 }, - { 802, 1, 1, 1, 1153, 0 }, - { 1365, 1, 1, 1, 1153, 0 }, - { 1495, 1, 1, 1, 1153, 0 }, - { 1625, 1, 1, 1, 1153, 0 }, - { 1755, 1, 1, 1, 1153, 0 }, - { 1893, 1, 1, 1, 1153, 0 }, - { 112, 1, 1, 1, 1153, 0 }, - { 325, 1, 1, 1, 1153, 0 }, - { 164, 14, 1, 9, 994, 10 }, - { 377, 17, 1, 9, 994, 10 }, - { 549, 20, 1, 9, 994, 10 }, - { 715, 23, 1, 9, 994, 10 }, - { 1282, 26, 1, 9, 994, 10 }, - { 1416, 29, 1, 9, 994, 10 }, - { 1546, 32, 1, 9, 994, 10 }, - { 1676, 35, 1, 9, 994, 10 }, - { 1801, 38, 1, 9, 994, 10 }, - { 1939, 41, 1, 9, 994, 10 }, - { 14, 44, 1, 9, 994, 10 }, - { 227, 47, 1, 9, 994, 10 }, - { 440, 50, 1, 9, 994, 10 }, - { 606, 53, 1, 9, 994, 10 }, - { 764, 56, 1, 9, 994, 10 }, - { 1327, 59, 1, 9, 994, 10 }, - { 92, 1, 150, 1, 2401, 0 }, - { 305, 1, 148, 1, 2401, 0 }, - { 518, 1, 146, 1, 2401, 0 }, - { 684, 1, 144, 1, 2401, 0 }, - { 167, 1, 161, 1, 3985, 0 }, - { 380, 1, 165, 1, 3985, 0 }, - { 552, 1, 165, 1, 3985, 0 }, - { 718, 1, 169, 1, 3985, 0 }, - { 1285, 1, 169, 1, 3985, 0 }, - { 1419, 1, 173, 1, 3985, 0 }, - { 1549, 1, 173, 1, 3985, 0 }, - { 1679, 1, 177, 1, 3985, 0 }, - { 1804, 1, 177, 1, 3985, 0 }, - { 1942, 1, 181, 1, 3985, 0 }, - { 18, 1, 181, 1, 3985, 0 }, - { 231, 1, 185, 1, 3985, 0 }, - { 444, 1, 185, 1, 3985, 0 }, - { 610, 1, 189, 1, 3985, 0 }, - { 768, 1, 189, 1, 3985, 0 }, - { 1331, 1, 193, 1, 3985, 0 }, - { 1461, 1, 193, 1, 3985, 0 }, - { 1591, 1, 197, 1, 3985, 0 }, - { 1721, 1, 197, 1, 3985, 0 }, - { 1843, 1, 201, 1, 3985, 0 }, - { 59, 1, 201, 1, 3985, 0 }, - { 272, 1, 205, 1, 3985, 0 }, - { 485, 1, 205, 1, 3985, 0 }, - { 651, 1, 209, 1, 3985, 0 }, - { 809, 1, 209, 1, 3985, 0 }, - { 1372, 1, 213, 1, 3985, 0 }, - { 1502, 1, 213, 1, 3985, 0 }, - { 1632, 1, 217, 1, 3985, 0 }, - { 1762, 1, 217, 1, 3985, 0 }, - { 1900, 1, 221, 1, 3985, 0 }, - { 119, 1, 221, 1, 3985, 0 }, - { 332, 1, 225, 1, 3985, 0 }, - { 159, 1, 1, 1, 3985, 0 }, - { 372, 1, 1, 1, 3985, 0 }, - { 544, 1, 1, 1, 3985, 0 }, - { 710, 1, 1, 1, 3985, 0 }, - { 1277, 1, 1, 1, 3985, 0 }, - { 1411, 1, 1, 1, 3985, 0 }, - { 1541, 1, 1, 1, 3985, 0 }, - { 1671, 1, 1, 1, 3985, 0 }, - { 191, 1, 1, 1, 3985, 0 }, - { 404, 1, 1, 1, 3985, 0 }, - { 573, 1, 1, 1, 3985, 0 }, - { 731, 1, 1, 1, 3985, 0 }, - { 1294, 1, 1, 1, 3985, 0 }, - { 1428, 1, 1, 1, 3985, 0 }, - { 1558, 1, 1, 1, 3985, 0 }, - { 1688, 1, 1, 1, 3985, 0 }, - { 1813, 1, 1, 1, 3985, 0 }, - { 1951, 1, 1, 1, 3985, 0 }, - { 29, 1, 1, 1, 3985, 0 }, - { 242, 1, 1, 1, 3985, 0 }, - { 455, 1, 1, 1, 3985, 0 }, - { 621, 1, 1, 1, 3985, 0 }, - { 779, 1, 1, 1, 3985, 0 }, - { 1342, 1, 1, 1, 3985, 0 }, - { 1472, 1, 1, 1, 3985, 0 }, - { 1602, 1, 1, 1, 3985, 0 }, - { 1732, 1, 1, 1, 3985, 0 }, - { 1854, 1, 1, 1, 3985, 0 }, - { 76, 1, 1, 1, 3985, 0 }, - { 289, 1, 1, 1, 3985, 0 }, - { 502, 1, 1, 1, 3985, 0 }, - { 668, 1, 1, 1, 3985, 0 }, - { 826, 1, 1, 1, 3985, 0 }, - { 1389, 1, 1, 1, 3985, 0 }, - { 1519, 1, 1, 1, 3985, 0 }, - { 1649, 1, 1, 1, 3985, 0 }, - { 1779, 1, 1, 1, 3985, 0 }, - { 1917, 1, 1, 1, 3985, 0 }, - { 136, 1, 1, 1, 3985, 0 }, - { 349, 1, 1, 1, 3985, 0 }, - { 1253, 136, 1, 0, 1184, 2 }, - { 170, 1, 158, 1, 3953, 0 }, - { 383, 1, 158, 1, 3953, 0 }, - { 555, 1, 158, 1, 3953, 0 }, - { 721, 1, 158, 1, 3953, 0 }, - { 1288, 1, 158, 1, 3953, 0 }, - { 1422, 1, 158, 1, 3953, 0 }, - { 1552, 1, 158, 1, 3953, 0 }, - { 1682, 1, 158, 1, 3953, 0 }, - { 1807, 1, 158, 1, 3953, 0 }, - { 1945, 1, 158, 1, 3953, 0 }, - { 22, 1, 158, 1, 3953, 0 }, - { 235, 1, 158, 1, 3953, 0 }, - { 448, 1, 158, 1, 3953, 0 }, - { 614, 1, 158, 1, 3953, 0 }, - { 772, 1, 158, 1, 3953, 0 }, - { 1335, 1, 158, 1, 3953, 0 }, - { 1465, 1, 158, 1, 3953, 0 }, - { 1595, 1, 158, 1, 3953, 0 }, - { 1725, 1, 158, 1, 3953, 0 }, - { 1847, 1, 158, 1, 3953, 0 }, - { 63, 1, 158, 1, 3953, 0 }, - { 276, 1, 158, 1, 3953, 0 }, - { 489, 1, 158, 1, 3953, 0 }, - { 655, 1, 158, 1, 3953, 0 }, - { 813, 1, 158, 1, 3953, 0 }, - { 1376, 1, 158, 1, 3953, 0 }, - { 1506, 1, 158, 1, 3953, 0 }, - { 1636, 1, 158, 1, 3953, 0 }, - { 1766, 1, 158, 1, 3953, 0 }, - { 1904, 1, 158, 1, 3953, 0 }, - { 123, 1, 158, 1, 3953, 0 }, - { 336, 1, 158, 1, 3953, 0 }, - { 1259, 128, 1, 0, 1216, 2 }, - { 172, 1, 233, 1, 1826, 0 }, - { 385, 1, 134, 1, 1826, 0 }, - { 557, 1, 134, 1, 1826, 0 }, - { 723, 1, 134, 1, 1826, 0 }, - { 196, 1, 1, 1, 3921, 0 }, - { 409, 1, 1, 1, 3921, 0 }, - { 578, 1, 1, 1, 3921, 0 }, - { 736, 1, 1, 1, 3921, 0 }, - { 1299, 1, 1, 1, 3921, 0 }, - { 1433, 1, 1, 1, 3921, 0 }, - { 1563, 1, 1, 1, 3921, 0 }, - { 1693, 1, 1, 1, 3921, 0 }, - { 1818, 1, 1, 1, 3921, 0 }, - { 1956, 1, 1, 1, 3921, 0 }, - { 35, 1, 1, 1, 3921, 0 }, - { 248, 1, 1, 1, 3921, 0 }, - { 461, 1, 1, 1, 3921, 0 }, - { 627, 1, 1, 1, 3921, 0 }, - { 785, 1, 1, 1, 3921, 0 }, - { 1348, 1, 1, 1, 3921, 0 }, - { 1478, 1, 1, 1, 3921, 0 }, - { 1608, 1, 1, 1, 3921, 0 }, - { 1738, 1, 1, 1, 3921, 0 }, - { 1860, 1, 1, 1, 3921, 0 }, - { 82, 1, 1, 1, 3921, 0 }, - { 295, 1, 1, 1, 3921, 0 }, - { 508, 1, 1, 1, 3921, 0 }, - { 674, 1, 1, 1, 3921, 0 }, - { 832, 1, 1, 1, 3921, 0 }, - { 1395, 1, 1, 1, 3921, 0 }, - { 1525, 1, 1, 1, 3921, 0 }, - { 1655, 1, 1, 1, 3921, 0 }, - { 1785, 1, 1, 1, 3921, 0 }, - { 1923, 1, 1, 1, 3921, 0 }, - { 142, 1, 1, 1, 3921, 0 }, - { 355, 1, 1, 1, 3921, 0 }, - { 176, 1, 100, 1, 3921, 0 }, - { 389, 1, 100, 1, 3921, 0 }, - { 184, 1, 229, 1, 1794, 0 }, - { 397, 1, 126, 1, 1794, 0 }, - { 566, 1, 126, 1, 1794, 0 }, - { 727, 1, 126, 1, 1794, 0 }, - { 179, 1, 1, 1, 3889, 0 }, - { 392, 1, 1, 1, 3889, 0 }, - { 561, 1, 1, 1, 3889, 0 }, - { 188, 1, 1, 1, 3889, 0 }, - { 401, 1, 1, 1, 3889, 0 }, - { 570, 1, 1, 1, 3889, 0 }, - { 1239, 124, 1, 0, 1248, 2 }, - { 201, 1, 98, 1, 3857, 0 }, - { 414, 1, 98, 1, 3857, 0 }, - { 583, 1, 98, 1, 3857, 0 }, - { 741, 1, 98, 1, 3857, 0 }, - { 1304, 1, 98, 1, 3857, 0 }, - { 1438, 1, 98, 1, 3857, 0 }, - { 1568, 1, 98, 1, 3857, 0 }, - { 1698, 1, 98, 1, 3857, 0 }, - { 1265, 122, 1, 0, 1280, 2 }, - { 204, 1, 96, 1, 3825, 0 }, - { 417, 1, 96, 1, 3825, 0 }, - { 586, 1, 96, 1, 3825, 0 }, - { 744, 1, 96, 1, 3825, 0 }, - { 1307, 1, 96, 1, 3825, 0 }, - { 1441, 1, 96, 1, 3825, 0 }, - { 1571, 1, 96, 1, 3825, 0 }, - { 1701, 1, 96, 1, 3825, 0 }, - { 1823, 1, 96, 1, 3825, 0 }, - { 1961, 1, 96, 1, 3825, 0 }, - { 207, 1, 96, 1, 3825, 0 }, - { 420, 1, 96, 1, 3825, 0 }, - { 210, 92, 1, 8, 1425, 10 }, - { 423, 92, 1, 8, 1425, 10 }, - { 589, 92, 1, 8, 1425, 10 }, - { 747, 92, 1, 8, 1425, 10 }, - { 1310, 92, 1, 8, 1425, 10 }, - { 1444, 92, 1, 8, 1425, 10 }, - { 1574, 92, 1, 8, 1425, 10 }, - { 1704, 92, 1, 8, 1425, 10 }, - { 1826, 92, 1, 8, 1425, 10 }, - { 1964, 92, 1, 8, 1425, 10 }, - { 41, 92, 1, 8, 1425, 10 }, - { 254, 92, 1, 8, 1425, 10 }, - { 467, 92, 1, 8, 1425, 10 }, - { 633, 92, 1, 8, 1425, 10 }, - { 791, 92, 1, 8, 1425, 10 }, - { 1354, 92, 1, 8, 1425, 10 }, - { 1484, 92, 1, 8, 1425, 10 }, - { 1614, 92, 1, 8, 1425, 10 }, - { 1744, 92, 1, 8, 1425, 10 }, - { 1866, 92, 1, 8, 1425, 10 }, - { 88, 92, 1, 8, 1425, 10 }, - { 301, 92, 1, 8, 1425, 10 }, - { 514, 92, 1, 8, 1425, 10 }, - { 680, 92, 1, 8, 1425, 10 }, - { 838, 92, 1, 8, 1425, 10 }, - { 1401, 92, 1, 8, 1425, 10 }, - { 1531, 92, 1, 8, 1425, 10 }, - { 1661, 92, 1, 8, 1425, 10 }, - { 1791, 92, 1, 8, 1425, 10 }, - { 1929, 92, 1, 8, 1425, 10 }, - { 148, 92, 1, 8, 1425, 10 }, - { 361, 92, 1, 8, 1425, 10 }, - { 1245, 118, 1, 0, 1921, 2 }, - { 869, 118, 1, 0, 1921, 2 }, - { 947, 118, 1, 0, 1921, 2 }, - { 997, 118, 1, 0, 1921, 2 }, - { 1035, 118, 1, 0, 1921, 2 }, - { 875, 130, 1, 12, 656, 10 }, - { 882, 93, 159, 9, 1377, 10 }, - { 953, 93, 159, 9, 1377, 10 }, - { 1003, 93, 159, 9, 1377, 10 }, - { 1041, 93, 159, 9, 1377, 10 }, - { 1073, 93, 159, 9, 1377, 10 }, - { 1105, 93, 159, 9, 1377, 10 }, - { 1137, 93, 159, 9, 1377, 10 }, - { 1169, 93, 159, 9, 1377, 10 }, - { 1201, 93, 159, 9, 1377, 10 }, - { 1227, 93, 159, 9, 1377, 10 }, - { 848, 93, 159, 9, 1377, 10 }, - { 926, 93, 159, 9, 1377, 10 }, - { 983, 93, 159, 9, 1377, 10 }, - { 1021, 93, 159, 9, 1377, 10 }, - { 1059, 93, 159, 9, 1377, 10 }, - { 1091, 93, 159, 9, 1377, 10 }, - { 1123, 93, 159, 9, 1377, 10 }, - { 1155, 93, 159, 9, 1377, 10 }, - { 1187, 93, 159, 9, 1377, 10 }, - { 1213, 93, 159, 9, 1377, 10 }, - { 855, 93, 159, 9, 1377, 10 }, - { 933, 93, 159, 9, 1377, 10 }, - { 990, 93, 159, 9, 1377, 10 }, - { 1028, 93, 159, 9, 1377, 10 }, - { 1066, 93, 159, 9, 1377, 10 }, - { 1098, 93, 159, 9, 1377, 10 }, - { 1130, 93, 159, 9, 1377, 10 }, - { 1162, 93, 159, 9, 1377, 10 }, - { 1194, 93, 159, 9, 1377, 10 }, - { 1220, 93, 159, 9, 1377, 10 }, - { 862, 93, 159, 9, 1377, 10 }, - { 940, 93, 159, 9, 1377, 10 }, - { 1870, 1, 116, 1, 1120, 0 }, - { 888, 138, 235, 0, 1344, 2 }, - { 895, 152, 1, 0, 2241, 2 }, - { 959, 152, 1, 0, 2241, 2 }, - { 901, 152, 231, 0, 1312, 2 }, - { 908, 154, 1, 0, 2273, 2 }, - { 965, 154, 1, 0, 2273, 2 }, - { 1009, 154, 1, 0, 2273, 2 }, - { 1047, 154, 1, 0, 2273, 2 }, - { 1079, 154, 1, 0, 2273, 2 }, - { 1111, 154, 1, 0, 2273, 2 }, - { 1143, 154, 1, 0, 2273, 2 }, - { 1175, 154, 1, 0, 2273, 2 }, - { 914, 156, 1, 0, 2273, 2 }, - { 971, 156, 1, 0, 2273, 2 }, - { 1015, 156, 1, 0, 2273, 2 }, - { 1053, 156, 1, 0, 2273, 2 }, - { 1085, 156, 1, 0, 2273, 2 }, - { 1117, 156, 1, 0, 2273, 2 }, - { 1149, 156, 1, 0, 2273, 2 }, - { 1181, 156, 1, 0, 2273, 2 }, - { 1207, 156, 1, 0, 2273, 2 }, - { 1233, 156, 1, 0, 2273, 2 }, - { 920, 156, 1, 0, 2273, 2 }, - { 977, 156, 1, 0, 2273, 2 }, -}; - - // OddSP Register Class... - static const MCPhysReg OddSP[] = { - Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // OddSP Bit set. - static const uint8_t OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // CCR Register Class... - static const MCPhysReg CCR[] = { - Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, - }; - - // CCR Bit set. - static const uint8_t CCRBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // COP2 Register Class... - static const MCPhysReg COP2[] = { - Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, - }; - - // COP2 Bit set. - static const uint8_t COP2Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01, - }; - - // COP3 Register Class... - static const MCPhysReg COP3[] = { - Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, - }; - - // COP3 Bit set. - static const uint8_t COP3Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f, - }; - - // DSPR Register Class... - static const MCPhysReg DSPR[] = { - Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, - }; - - // DSPR Bit set. - static const uint8_t DSPRBits[] = { - 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, - }; - - // FGR32 Register Class... - static const MCPhysReg FGR32[] = { - Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, - }; - - // FGR32 Bit set. - static const uint8_t FGR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // FGRCC Register Class... - static const MCPhysReg FGRCC[] = { - Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, - }; - - // FGRCC Bit set. - static const uint8_t FGRCCBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // FGRH32 Register Class... - static const MCPhysReg FGRH32[] = { - Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31, - }; - - // FGRH32 Bit set. - static const uint8_t FGRH32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, - }; - - // GPR32 Register Class... - static const MCPhysReg GPR32[] = { - Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, - }; - - // GPR32 Bit set. - static const uint8_t GPR32Bits[] = { - 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, - }; - - // HWRegs Register Class... - static const MCPhysReg HWRegs[] = { - Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, - }; - - // HWRegs Bit set. - static const uint8_t HWRegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, - }; - - // OddSP_with_sub_hi Register Class... - static const MCPhysReg OddSP_with_sub_hi[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // OddSP_with_sub_hi Bit set. - static const uint8_t OddSP_with_sub_hiBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // FGR32_and_OddSP Register Class... - static const MCPhysReg FGR32_and_OddSP[] = { - Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, - }; - - // FGR32_and_OddSP Bit set. - static const uint8_t FGR32_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, - }; - - // FGRH32_and_OddSP Register Class... - static const MCPhysReg FGRH32_and_OddSP[] = { - Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, - }; - - // FGRH32_and_OddSP Bit set. - static const uint8_t FGRH32_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... - static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { - Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. - static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // CPU16RegsPlusSP Register Class... - static const MCPhysReg CPU16RegsPlusSP[] = { - Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, - }; - - // CPU16RegsPlusSP Bit set. - static const uint8_t CPU16RegsPlusSPBits[] = { - 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // CC Register Class... - static const MCPhysReg CC[] = { - Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7, - }; - - // CC Bit set. - static const uint8_t CCBits[] = { - 0x00, 0x00, 0x00, 0x80, 0x7f, - }; - - // CPU16Regs Register Class... - static const MCPhysReg CPU16Regs[] = { - Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, - }; - - // CPU16Regs Bit set. - static const uint8_t CPU16RegsBits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // FCC Register Class... - static const MCPhysReg FCC[] = { - Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, - }; - - // FCC Bit set. - static const uint8_t FCCBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, - }; - - // GPRMM16 Register Class... - static const MCPhysReg GPRMM16[] = { - Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, - }; - - // GPRMM16 Bit set. - static const uint8_t GPRMM16Bits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // GPRMM16MoveP Register Class... - static const MCPhysReg GPRMM16MoveP[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, - }; - - // GPRMM16MoveP Bit set. - static const uint8_t GPRMM16MovePBits[] = { - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, - }; - - // GPRMM16Zero Register Class... - static const MCPhysReg GPRMM16Zero[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, - }; - - // GPRMM16Zero Bit set. - static const uint8_t GPRMM16ZeroBits[] = { - 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, - }; - - // MSACtrl Register Class... - static const MCPhysReg MSACtrl[] = { - Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, - }; - - // MSACtrl Bit set. - static const uint8_t MSACtrlBits[] = { - 0x00, 0xfc, 0x03, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... - static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, - }; - - // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. - static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, - }; - - // CPU16Regs_and_GPRMM16Zero Register Class... - static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { - Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, - }; - - // CPU16Regs_and_GPRMM16Zero Bit set. - static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, - }; - - // CPU16Regs_and_GPRMM16MoveP Register Class... - static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { - Mips_S1, Mips_V0, Mips_V1, Mips_S0, - }; - - // CPU16Regs_and_GPRMM16MoveP Bit set. - static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, - }; - - // GPRMM16MoveP_and_GPRMM16Zero Register Class... - static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { - Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, - }; - - // GPRMM16MoveP_and_GPRMM16Zero Bit set. - static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, - }; - - // HI32DSP Register Class... - static const MCPhysReg HI32DSP[] = { - Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, - }; - - // HI32DSP Bit set. - static const uint8_t HI32DSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, - }; - - // LO32DSP Register Class... - static const MCPhysReg LO32DSP[] = { - Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, - }; - - // LO32DSP Bit set. - static const uint8_t LO32DSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, - }; - - // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... - static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { - Mips_S1, Mips_V0, Mips_V1, - }; - - // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. - static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, - }; - - // CPURAReg Register Class... - static const MCPhysReg CPURAReg[] = { - Mips_RA, - }; - - // CPURAReg Bit set. - static const uint8_t CPURARegBits[] = { - 0x00, 0x00, 0x08, - }; - - // CPUSPReg Register Class... - static const MCPhysReg CPUSPReg[] = { - Mips_SP, - }; - - // CPUSPReg Bit set. - static const uint8_t CPUSPRegBits[] = { - 0x00, 0x00, 0x10, - }; - - // DSPCC Register Class... - static const MCPhysReg DSPCC[] = { - Mips_DSPCCond, - }; - - // DSPCC Bit set. - static const uint8_t DSPCCBits[] = { - 0x04, - }; - - // HI32 Register Class... - static const MCPhysReg HI32[] = { - Mips_HI0, - }; - - // HI32 Bit set. - static const uint8_t HI32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, - }; - - // LO32 Register Class... - static const MCPhysReg LO32[] = { - Mips_LO0, - }; - - // LO32 Bit set. - static const uint8_t LO32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, - }; - - // FGR64 Register Class... - static const MCPhysReg FGR64[] = { - Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, - }; - - // FGR64 Bit set. - static const uint8_t FGR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, - }; - - // GPR64 Register Class... - static const MCPhysReg GPR64[] = { - Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, - }; - - // GPR64 Bit set. - static const uint8_t GPR64Bits[] = { - 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, - }; - - // AFGR64 Register Class... - static const MCPhysReg AFGR64[] = { - Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, - }; - - // AFGR64 Bit set. - static const uint8_t AFGR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, - }; - - // FGR64_and_OddSP Register Class... - static const MCPhysReg FGR64_and_OddSP[] = { - Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, - }; - - // FGR64_and_OddSP Bit set. - static const uint8_t FGR64_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, - }; - - // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, - }; - - // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. - static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, - }; - - // AFGR64_and_OddSP Register Class... - static const MCPhysReg AFGR64_and_OddSP[] = { - Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, - }; - - // AFGR64_and_OddSP Bit set. - static const uint8_t AFGR64_and_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, - }; - - // GPR64_with_sub_32_in_CPU16Regs Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_CPU16Regs Bit set. - static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... - static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. - static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_GPRMM16Zero Register Class... - static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_GPRMM16Zero Bit set. - static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { - Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. - static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, - }; - - // ACC64DSP Register Class... - static const MCPhysReg ACC64DSP[] = { - Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, - }; - - // ACC64DSP Bit set. - static const uint8_t ACC64DSPBits[] = { - 0x00, 0x00, 0x00, 0x3c, - }; - - // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { - Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. - static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... - static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { - Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. - static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... - static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { - Mips_V0_64, Mips_V1_64, Mips_S1_64, - }; - - // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. - static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, - }; - - // OCTEON_MPL Register Class... - static const MCPhysReg OCTEON_MPL[] = { - Mips_MPL0, Mips_MPL1, Mips_MPL2, - }; - - // OCTEON_MPL Bit set. - static const uint8_t OCTEON_MPLBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, - }; - - // OCTEON_P Register Class... - static const MCPhysReg OCTEON_P[] = { - Mips_P0, Mips_P1, Mips_P2, - }; - - // OCTEON_P Bit set. - static const uint8_t OCTEON_PBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, - }; - - // ACC64 Register Class... - static const MCPhysReg ACC64[] = { - Mips_AC0, - }; - - // ACC64 Bit set. - static const uint8_t ACC64Bits[] = { - 0x00, 0x00, 0x00, 0x04, - }; - - // GPR64_with_sub_32_in_CPURAReg Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { - Mips_RA_64, - }; - - // GPR64_with_sub_32_in_CPURAReg Bit set. - static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, - }; - - // GPR64_with_sub_32_in_CPUSPReg Register Class... - static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { - Mips_SP_64, - }; - - // GPR64_with_sub_32_in_CPUSPReg Bit set. - static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, - }; - - // HI64 Register Class... - static const MCPhysReg HI64[] = { - Mips_HI0_64, - }; - - // HI64 Bit set. - static const uint8_t HI64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, - }; - - // LO64 Register Class... - static const MCPhysReg LO64[] = { - Mips_LO0_64, - }; - - // LO64 Bit set. - static const uint8_t LO64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, - }; - - // MSA128B Register Class... - static const MCPhysReg MSA128B[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, - }; - - // MSA128B Bit set. - static const uint8_t MSA128BBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128D Register Class... - static const MCPhysReg MSA128D[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, - }; - - // MSA128D Bit set. - static const uint8_t MSA128DBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128H Register Class... - static const MCPhysReg MSA128H[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, - }; - - // MSA128H Bit set. - static const uint8_t MSA128HBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128W Register Class... - static const MCPhysReg MSA128W[] = { - Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, - }; - - // MSA128W Bit set. - static const uint8_t MSA128WBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; - - // MSA128B_with_sub_64_in_OddSP Register Class... - static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { - Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31, - }; - - // MSA128B_with_sub_64_in_OddSP Bit set. - static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, - }; - - // MSA128WEvens Register Class... - static const MCPhysReg MSA128WEvens[] = { - Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, - }; - - // MSA128WEvens Bit set. - static const uint8_t MSA128WEvensBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, - }; - - // ACC128 Register Class... - static const MCPhysReg ACC128[] = { - Mips_AC0_64, - }; - - // ACC128 Bit set. - static const uint8_t ACC128Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - }; - -static const MCRegisterClass MipsMCRegisterClasses[] = { - { OddSP, OddSPBits, sizeof(OddSPBits) }, - { CCR, CCRBits, sizeof(CCRBits) }, - { COP2, COP2Bits, sizeof(COP2Bits) }, - { COP3, COP3Bits, sizeof(COP3Bits) }, - { DSPR, DSPRBits, sizeof(DSPRBits) }, - { FGR32, FGR32Bits, sizeof(FGR32Bits) }, - { FGRCC, FGRCCBits, sizeof(FGRCCBits) }, - { FGRH32, FGRH32Bits, sizeof(FGRH32Bits) }, - { GPR32, GPR32Bits, sizeof(GPR32Bits) }, - { HWRegs, HWRegsBits, sizeof(HWRegsBits) }, - { OddSP_with_sub_hi, OddSP_with_sub_hiBits, sizeof(OddSP_with_sub_hiBits) }, - { FGR32_and_OddSP, FGR32_and_OddSPBits, sizeof(FGR32_and_OddSPBits) }, - { FGRH32_and_OddSP, FGRH32_and_OddSPBits, sizeof(FGRH32_and_OddSPBits) }, - { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits) }, - { CPU16RegsPlusSP, CPU16RegsPlusSPBits, sizeof(CPU16RegsPlusSPBits) }, - { CC, CCBits, sizeof(CCBits) }, - { CPU16Regs, CPU16RegsBits, sizeof(CPU16RegsBits) }, - { FCC, FCCBits, sizeof(FCCBits) }, - { GPRMM16, GPRMM16Bits, sizeof(GPRMM16Bits) }, - { GPRMM16MoveP, GPRMM16MovePBits, sizeof(GPRMM16MovePBits) }, - { GPRMM16Zero, GPRMM16ZeroBits, sizeof(GPRMM16ZeroBits) }, - { MSACtrl, MSACtrlBits, sizeof(MSACtrlBits) }, - { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits) }, - { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, sizeof(CPU16Regs_and_GPRMM16ZeroBits) }, - { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, sizeof(CPU16Regs_and_GPRMM16MovePBits) }, - { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits) }, - { HI32DSP, HI32DSPBits, sizeof(HI32DSPBits) }, - { LO32DSP, LO32DSPBits, sizeof(LO32DSPBits) }, - { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, - { CPURAReg, CPURARegBits, sizeof(CPURARegBits) }, - { CPUSPReg, CPUSPRegBits, sizeof(CPUSPRegBits) }, - { DSPCC, DSPCCBits, sizeof(DSPCCBits) }, - { HI32, HI32Bits, sizeof(HI32Bits) }, - { LO32, LO32Bits, sizeof(LO32Bits) }, - { FGR64, FGR64Bits, sizeof(FGR64Bits) }, - { GPR64, GPR64Bits, sizeof(GPR64Bits) }, - { AFGR64, AFGR64Bits, sizeof(AFGR64Bits) }, - { FGR64_and_OddSP, FGR64_and_OddSPBits, sizeof(FGR64_and_OddSPBits) }, - { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits) }, - { AFGR64_and_OddSP, AFGR64_and_OddSPBits, sizeof(AFGR64_and_OddSPBits) }, - { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, sizeof(GPR64_with_sub_32_in_CPU16RegsBits) }, - { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits) }, - { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits) }, - { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits) }, - { ACC64DSP, ACC64DSPBits, sizeof(ACC64DSPBits) }, - { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits) }, - { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits) }, - { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, - { OCTEON_MPL, OCTEON_MPLBits, sizeof(OCTEON_MPLBits) }, - { OCTEON_P, OCTEON_PBits, sizeof(OCTEON_PBits) }, - { ACC64, ACC64Bits, sizeof(ACC64Bits) }, - { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, sizeof(GPR64_with_sub_32_in_CPURARegBits) }, - { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, sizeof(GPR64_with_sub_32_in_CPUSPRegBits) }, - { HI64, HI64Bits, sizeof(HI64Bits) }, - { LO64, LO64Bits, sizeof(LO64Bits) }, - { MSA128B, MSA128BBits, sizeof(MSA128BBits) }, - { MSA128D, MSA128DBits, sizeof(MSA128DBits) }, - { MSA128H, MSA128HBits, sizeof(MSA128HBits) }, - { MSA128W, MSA128WBits, sizeof(MSA128WBits) }, - { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, sizeof(MSA128B_with_sub_64_in_OddSPBits) }, - { MSA128WEvens, MSA128WEvensBits, sizeof(MSA128WEvensBits) }, - { ACC128, ACC128Bits, sizeof(ACC128Bits) }, -}; - -#endif // GET_REGINFO_MC_DESC diff --git a/arch/Mips/MipsGenSubtargetInfo.inc b/arch/Mips/MipsGenSubtargetInfo.inc deleted file mode 100644 index 36e7a7f866..0000000000 --- a/arch/Mips/MipsGenSubtargetInfo.inc +++ /dev/null @@ -1,52 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Subtarget Enumeration Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ - - -#ifdef GET_SUBTARGETINFO_ENUM -#undef GET_SUBTARGETINFO_ENUM - -#define Mips_FeatureCnMips (1ULL << 0) -#define Mips_FeatureDSP (1ULL << 1) -#define Mips_FeatureDSPR2 (1ULL << 2) -#define Mips_FeatureFP64Bit (1ULL << 3) -#define Mips_FeatureFPXX (1ULL << 4) -#define Mips_FeatureGP64Bit (1ULL << 5) -#define Mips_FeatureMSA (1ULL << 6) -#define Mips_FeatureMicroMips (1ULL << 7) -#define Mips_FeatureMips1 (1ULL << 8) -#define Mips_FeatureMips2 (1ULL << 9) -#define Mips_FeatureMips3 (1ULL << 10) -#define Mips_FeatureMips3_32 (1ULL << 11) -#define Mips_FeatureMips3_32r2 (1ULL << 12) -#define Mips_FeatureMips4 (1ULL << 13) -#define Mips_FeatureMips4_32 (1ULL << 14) -#define Mips_FeatureMips4_32r2 (1ULL << 15) -#define Mips_FeatureMips5 (1ULL << 16) -#define Mips_FeatureMips5_32r2 (1ULL << 17) -#define Mips_FeatureMips16 (1ULL << 18) -#define Mips_FeatureMips32 (1ULL << 19) -#define Mips_FeatureMips32r2 (1ULL << 20) -#define Mips_FeatureMips32r3 (1ULL << 21) -#define Mips_FeatureMips32r5 (1ULL << 22) -#define Mips_FeatureMips32r6 (1ULL << 23) -#define Mips_FeatureMips64 (1ULL << 24) -#define Mips_FeatureMips64r2 (1ULL << 25) -#define Mips_FeatureMips64r3 (1ULL << 26) -#define Mips_FeatureMips64r5 (1ULL << 27) -#define Mips_FeatureMips64r6 (1ULL << 28) -#define Mips_FeatureNaN2008 (1ULL << 29) -#define Mips_FeatureNoABICalls (1ULL << 30) -#define Mips_FeatureNoOddSPReg (1ULL << 31) -#define Mips_FeatureSingleFloat (1ULL << 32) -#define Mips_FeatureVFPU (1ULL << 33) - -#endif // GET_SUBTARGETINFO_ENUM - diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c index 9bbf4bc2e5..b6063b508a 100644 --- a/arch/Mips/MipsInstPrinter.c +++ b/arch/Mips/MipsInstPrinter.c @@ -17,22 +17,25 @@ #ifdef CAPSTONE_HAS_MIPS #include +#include // debug #include -#include // debug #include -#include "MipsInstPrinter.h" #include "../../MCInst.h" -#include "../../utils.h" -#include "../../SStream.h" #include "../../MCRegisterInfo.h" +#include "../../SStream.h" +#include "../../utils.h" +#include "MipsInstPrinter.h" #include "MipsMapping.h" #include "MipsInstPrinter.h" static void printUnsignedImm(MCInst *MI, int opNum, SStream *O); -static char *printAliasInstr(MCInst *MI, SStream *O, void *info); +#define printUImm(MI, Op, O, ...) printUnsignedImm(MI, Op, O) +static char *printAliasInstr(MCInst *MI, SStream *O); static char *printAlias(MCInst *MI, SStream *OS); +static void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); // These enumeration declarations were originally in MipsInstrInfo.h but // had to be moved here to avoid circular dependencies between @@ -40,385 +43,433 @@ static char *printAlias(MCInst *MI, SStream *OS); // Mips Condition Codes typedef enum Mips_CondCode { - // To be used with float branch True - Mips_FCOND_F, - Mips_FCOND_UN, - Mips_FCOND_OEQ, - Mips_FCOND_UEQ, - Mips_FCOND_OLT, - Mips_FCOND_ULT, - Mips_FCOND_OLE, - Mips_FCOND_ULE, - Mips_FCOND_SF, - Mips_FCOND_NGLE, - Mips_FCOND_SEQ, - Mips_FCOND_NGL, - Mips_FCOND_LT, - Mips_FCOND_NGE, - Mips_FCOND_LE, - Mips_FCOND_NGT, - - // To be used with float branch False - // This conditions have the same mnemonic as the - // above ones, but are used with a branch False; - Mips_FCOND_T, - Mips_FCOND_OR, - Mips_FCOND_UNE, - Mips_FCOND_ONE, - Mips_FCOND_UGE, - Mips_FCOND_OGE, - Mips_FCOND_UGT, - Mips_FCOND_OGT, - Mips_FCOND_ST, - Mips_FCOND_GLE, - Mips_FCOND_SNE, - Mips_FCOND_GL, - Mips_FCOND_NLT, - Mips_FCOND_GE, - Mips_FCOND_NLE, - Mips_FCOND_GT + // To be used with float branch True + Mips_FCOND_F, + Mips_FCOND_UN, + Mips_FCOND_OEQ, + Mips_FCOND_UEQ, + Mips_FCOND_OLT, + Mips_FCOND_ULT, + Mips_FCOND_OLE, + Mips_FCOND_ULE, + Mips_FCOND_SF, + Mips_FCOND_NGLE, + Mips_FCOND_SEQ, + Mips_FCOND_NGL, + Mips_FCOND_LT, + Mips_FCOND_NGE, + Mips_FCOND_LE, + Mips_FCOND_NGT, + + // To be used with float branch False + // This conditions have the same mnemonic as the + // above ones, but are used with a branch False; + Mips_FCOND_T, + Mips_FCOND_OR, + Mips_FCOND_UNE, + Mips_FCOND_ONE, + Mips_FCOND_UGE, + Mips_FCOND_OGE, + Mips_FCOND_UGT, + Mips_FCOND_OGT, + Mips_FCOND_ST, + Mips_FCOND_GLE, + Mips_FCOND_SNE, + Mips_FCOND_GL, + Mips_FCOND_NLT, + Mips_FCOND_GE, + Mips_FCOND_NLE, + Mips_FCOND_GT } Mips_CondCode; -#define GET_INSTRINFO_ENUM -#include "MipsGenInstrInfo.inc" +//#include "MipsGenInstrInfo.inc" static const char *getRegisterName(unsigned RegNo); -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); - -static void set_mem_access(MCInst *MI, bool status) -{ - MI->csh->doing_mem = status; - - if (MI->csh->detail != CS_OPT_ON) - return; - - if (status) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; - } else { - // done, create the next operand slot - MI->flat_insn->detail->mips.op_count++; - } +static void printInstruction(MCInst *MI, SStream *O); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printMemOperand(MCInst *MI, int opNum, SStream *O, char *); +static void printMemOperandEA(MCInst *MI, int opNum, SStream *O, char *); +static void printFCCOperand(MCInst *MI, int opNum, SStream *O); +static void printRegisterList(MCInst *MI, int opNum, SStream *O); + +#include "../MCInstPrinter.h" +#include "../sync/logger.h" + +#define GET_INSTRINFO_ENUM +#define GET_REGINFO_ENUM +#define GET_ASM_WRITER +#define PRINT_ALIAS_INSTR +#include "MipsGenDisassemblerTables.inc" + +static void set_mem_access(MCInst *MI, bool status) { + MI->csh->doing_mem = status; + + if (MI->csh->detail != CS_OPT_ON) + return; + + if (status) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count] + .type = MIPS_OP_MEM; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count] + .mem.base = MIPS_REG_INVALID; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count] + .mem.disp = 0; + } else { + // done, create the next operand slot + MI->flat_insn->detail->mips.op_count++; + } } -static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) -{ - return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) && - MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R); +static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) { + return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) && + MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R); } -static const char* MipsFCCToString(Mips_CondCode CC) -{ - switch (CC) { - default: return 0; // never reach - case Mips_FCOND_F: - case Mips_FCOND_T: return "f"; - case Mips_FCOND_UN: - case Mips_FCOND_OR: return "un"; - case Mips_FCOND_OEQ: - case Mips_FCOND_UNE: return "eq"; - case Mips_FCOND_UEQ: - case Mips_FCOND_ONE: return "ueq"; - case Mips_FCOND_OLT: - case Mips_FCOND_UGE: return "olt"; - case Mips_FCOND_ULT: - case Mips_FCOND_OGE: return "ult"; - case Mips_FCOND_OLE: - case Mips_FCOND_UGT: return "ole"; - case Mips_FCOND_ULE: - case Mips_FCOND_OGT: return "ule"; - case Mips_FCOND_SF: - case Mips_FCOND_ST: return "sf"; - case Mips_FCOND_NGLE: - case Mips_FCOND_GLE: return "ngle"; - case Mips_FCOND_SEQ: - case Mips_FCOND_SNE: return "seq"; - case Mips_FCOND_NGL: - case Mips_FCOND_GL: return "ngl"; - case Mips_FCOND_LT: - case Mips_FCOND_NLT: return "lt"; - case Mips_FCOND_NGE: - case Mips_FCOND_GE: return "nge"; - case Mips_FCOND_LE: - case Mips_FCOND_NLE: return "le"; - case Mips_FCOND_NGT: - case Mips_FCOND_GT: return "ngt"; - } +static const char *MipsFCCToString(Mips_CondCode CC) { + switch (CC) { + default: + return 0; // never reach + case Mips_FCOND_F: + case Mips_FCOND_T: + return "f"; + case Mips_FCOND_UN: + case Mips_FCOND_OR: + return "un"; + case Mips_FCOND_OEQ: + case Mips_FCOND_UNE: + return "eq"; + case Mips_FCOND_UEQ: + case Mips_FCOND_ONE: + return "ueq"; + case Mips_FCOND_OLT: + case Mips_FCOND_UGE: + return "olt"; + case Mips_FCOND_ULT: + case Mips_FCOND_OGE: + return "ult"; + case Mips_FCOND_OLE: + case Mips_FCOND_UGT: + return "ole"; + case Mips_FCOND_ULE: + case Mips_FCOND_OGT: + return "ule"; + case Mips_FCOND_SF: + case Mips_FCOND_ST: + return "sf"; + case Mips_FCOND_NGLE: + case Mips_FCOND_GLE: + return "ngle"; + case Mips_FCOND_SEQ: + case Mips_FCOND_SNE: + return "seq"; + case Mips_FCOND_NGL: + case Mips_FCOND_GL: + return "ngl"; + case Mips_FCOND_LT: + case Mips_FCOND_NLT: + return "lt"; + case Mips_FCOND_NGE: + case Mips_FCOND_GE: + return "nge"; + case Mips_FCOND_LE: + case Mips_FCOND_NLE: + return "le"; + case Mips_FCOND_NGT: + case Mips_FCOND_GT: + return "ngt"; + } } -static void printRegName(SStream *OS, unsigned RegNo) -{ - SStream_concat(OS, "$%s", getRegisterName(RegNo)); +static void printRegName(SStream *OS, unsigned RegNo) { + debug("there is a name %s\n", getRegisterName(RegNo)); + char *Name = Mips_reg_name(0, RegNo); + if (Name) + SStream_concat(OS, "$%s", Name); + else + SStream_concat(OS, "$%s", getRegisterName(RegNo)); } -void Mips_printInst(MCInst *MI, SStream *O, void *info) -{ - char *mnem; - - switch (MCInst_getOpcode(MI)) { - default: break; - case Mips_Save16: - case Mips_SaveX16: - case Mips_Restore16: - case Mips_RestoreX16: - return; - } - - // Try to print any aliases first. - mnem = printAliasInstr(MI, O, info); - if (!mnem) { - mnem = printAlias(MI, O); - if (!mnem) { - printInstruction(MI, O, NULL); - } - } - - if (mnem) { - // fixup instruction id due to the change in alias instruction - MCInst_setOpcodePub(MI, Mips_map_insn(mnem)); - cs_mem_free(mnem); - } +void Mips_printInst(MCInst *MI, SStream *O, void *info) { + debug("start instr printing\n"); + char *mnem; + MRI = info; + switch (MCInst_getOpcode(MI)) { + default: + break; + case Mips_Save16: + case Mips_SaveX16: + case Mips_Restore16: + case Mips_RestoreX16: + return; + } + + // Try to print any aliases first. + mnem = printAliasInstr(MI, O); + if (!mnem) { + debug("no mnem found\n"); + mnem = printAlias(MI, O); + if (!mnem) { + debug("no alias found\n"); + printInstruction(MI, O); + } + } + + if (mnem) { + debug("start instr fix %s\n", mnem); + // fixup instruction id due to the change in alias instruction + MCInst_setOpcodePub(MI, Mips_map_insn(mnem)); + cs_mem_free(mnem); + } + debug("end instr printing\n"); } -static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - MCOperand *Op; - - if (OpNo >= MI->size) - return; - - Op = MCInst_getOperand(MI, OpNo); - if (MCOperand_isReg(Op)) { - unsigned int reg = MCOperand_getReg(Op); - printRegName(O, reg); - reg = Mips_map_register(reg); - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg; - } else { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; - MI->flat_insn->detail->mips.op_count++; - } - } - } else if (MCOperand_isImm(Op)) { - int64_t imm = MCOperand_getImm(Op); - if (MI->csh->doing_mem) { - if (imm) { // only print Imm offset if it is not 0 - printInt64(O, imm); - } - if (MI->csh->detail) - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm; - } else { - printInt64(O, imm); - - if (MI->csh->detail) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; - MI->flat_insn->detail->mips.op_count++; - } - } - } +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { + MCOperand *Op; + + if (OpNo >= MI->size) + return; + + Op = MCInst_getOperand(MI, OpNo); + if (MCOperand_isReg(Op)) { + unsigned int reg = MCOperand_getReg(Op); + printRegName(O, reg); + // reg = Mips_map_register(reg); + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->mips + .operands[MI->flat_insn->detail->mips.op_count] + .mem.base = reg; + } else { + MI->flat_insn->detail->mips + .operands[MI->flat_insn->detail->mips.op_count] + .type = MIPS_OP_REG; + MI->flat_insn->detail->mips + .operands[MI->flat_insn->detail->mips.op_count] + .reg = reg; + MI->flat_insn->detail->mips.op_count++; + } + } + debug("is reg complete\n"); + } else if (MCOperand_isImm(Op)) { + int64_t imm = MCOperand_getImm(Op); + debug("is imm %ld %d\n", imm, imm > 0); + if (MI->csh->doing_mem) { + if (imm) { // only print Imm offset if it is not 0 + printInt64(O, imm); + } + if (MI->csh->detail) + MI->flat_insn->detail->mips + .operands[MI->flat_insn->detail->mips.op_count] + .mem.disp = imm; + } else { + printInt64(O, imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->mips + .operands[MI->flat_insn->detail->mips.op_count] + .type = MIPS_OP_IMM; + MI->flat_insn->detail->mips + .operands[MI->flat_insn->detail->mips.op_count] + .imm = imm; + MI->flat_insn->detail->mips.op_count++; + } + } + } } -static void printUnsignedImm(MCInst *MI, int opNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, opNum); - if (MCOperand_isImm(MO)) { - int64_t imm = MCOperand_getImm(MO); - printInt64(O, imm); - - if (MI->csh->detail) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm; - MI->flat_insn->detail->mips.op_count++; - } - } else - printOperand(MI, opNum, O); +static void printUnsignedImm(MCInst *MI, int opNum, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, opNum); + if (MCOperand_isImm(MO)) { + int64_t imm = MCOperand_getImm(MO); + printInt64(O, imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count] + .type = MIPS_OP_IMM; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count] + .imm = (unsigned short int)imm; + MI->flat_insn->detail->mips.op_count++; + } + } else + printOperand(MI, opNum, O); } -static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, opNum); - if (MCOperand_isImm(MO)) { - uint8_t imm = (uint8_t)MCOperand_getImm(MO); - if (imm > HEX_THRESHOLD) - SStream_concat(O, "0x%x", imm); - else - SStream_concat(O, "%u", imm); - if (MI->csh->detail) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; - MI->flat_insn->detail->mips.op_count++; - } - } else - printOperand(MI, opNum, O); +static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, opNum); + if (MCOperand_isImm(MO)) { + uint8_t imm = (uint8_t)MCOperand_getImm(MO); + if (imm > HEX_THRESHOLD) + SStream_concat(O, "0x%x", imm); + else + SStream_concat(O, "%u", imm); + if (MI->csh->detail) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count] + .type = MIPS_OP_IMM; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count] + .imm = imm; + MI->flat_insn->detail->mips.op_count++; + } + } else + printOperand(MI, opNum, O); } -static void printMemOperand(MCInst *MI, int opNum, SStream *O) -{ - // Load/Store memory operands -- imm($reg) - // If PIC target the target is loaded as the - // pattern lw $25,%call16($28) - - // opNum can be invalid if instruction had reglist as operand. - // MemOperand is always last operand of instruction (base + offset). - switch (MCInst_getOpcode(MI)) { - default: - break; - case Mips_SWM32_MM: - case Mips_LWM32_MM: - case Mips_SWM16_MM: - case Mips_LWM16_MM: - opNum = MCInst_getNumOperands(MI) - 2; - break; - } - - set_mem_access(MI, true); - printOperand(MI, opNum + 1, O); - SStream_concat0(O, "("); - printOperand(MI, opNum, O); - SStream_concat0(O, ")"); - set_mem_access(MI, false); +static void printMemOperand(MCInst *MI, int opNum, SStream *O, char *ignored) { + // Load/Store memory operands -- imm($reg) + // If PIC target the target is loaded as the + // pattern lw $25,%call16($28) + + // opNum can be invalid if instruction had reglist as operand. + // MemOperand is always last operand of instruction (base + offset). + switch (MCInst_getOpcode(MI)) { + default: + break; + case Mips_SWM32_MM: + case Mips_LWM32_MM: + case Mips_SWM16_MM: + case Mips_LWM16_MM: + opNum = MCInst_getNumOperands(MI) - 2; + break; + } + + set_mem_access(MI, true); + printOperand(MI, opNum + 1, O); + SStream_concat0(O, "("); + printOperand(MI, opNum, O); + SStream_concat0(O, ")"); + set_mem_access(MI, false); } // TODO??? -static void printMemOperandEA(MCInst *MI, int opNum, SStream *O) -{ - // when using stack locations for not load/store instructions - // print the same way as all normal 3 operand instructions. - printOperand(MI, opNum, O); - SStream_concat0(O, ", "); - printOperand(MI, opNum + 1, O); - return; +static void printMemOperandEA(MCInst *MI, int opNum, SStream *O, + char *ignored) { + // when using stack locations for not load/store instructions + // print the same way as all normal 3 operand instructions. + printOperand(MI, opNum, O); + SStream_concat0(O, ", "); + printOperand(MI, opNum + 1, O); + return; } -static void printFCCOperand(MCInst *MI, int opNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, opNum); - SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); +static void printFCCOperand(MCInst *MI, int opNum, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, opNum); + SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); } -static void printRegisterPair(MCInst *MI, int opNum, SStream *O) -{ - printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum))); +static void printRegisterPair(MCInst *MI, int opNum, SStream *O) { + printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum))); } -static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS) -{ - SStream_concat(OS, "%s\t", Str); - printOperand(MI, OpNo, OS); - return cs_strdup(Str); +static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, + SStream *OS) { + SStream_concat(OS, "%s\t", Str); + printOperand(MI, OpNo, OS); + return cs_strdup(Str); } -static char *printAlias2(const char *Str, MCInst *MI, - unsigned OpNo0, unsigned OpNo1, SStream *OS) -{ - char *tmp; +static char *printAlias2(const char *Str, MCInst *MI, unsigned OpNo0, + unsigned OpNo1, SStream *OS) { + char *tmp; - tmp = printAlias1(Str, MI, OpNo0, OS); - SStream_concat0(OS, ", "); - printOperand(MI, OpNo1, OS); + tmp = printAlias1(Str, MI, OpNo0, OS); + SStream_concat0(OS, ", "); + printOperand(MI, OpNo1, OS); - return tmp; + return tmp; } -#define GET_REGINFO_ENUM -#include "MipsGenRegisterInfo.inc" - -static char *printAlias(MCInst *MI, SStream *OS) -{ - switch (MCInst_getOpcode(MI)) { - case Mips_BEQ: - case Mips_BEQ_MM: - // beq $zero, $zero, $L2 => b $L2 - // beq $r0, $zero, $L2 => beqz $r0, $L2 - if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) - return printAlias1("b", MI, 2, OS); - if (isReg(MI, 1, Mips_ZERO)) - return printAlias2("beqz", MI, 0, 2, OS); - return NULL; - case Mips_BEQ64: - // beq $r0, $zero, $L2 => beqz $r0, $L2 - if (isReg(MI, 1, Mips_ZERO_64)) - return printAlias2("beqz", MI, 0, 2, OS); - return NULL; - case Mips_BNE: - // bne $r0, $zero, $L2 => bnez $r0, $L2 - if (isReg(MI, 1, Mips_ZERO)) - return printAlias2("bnez", MI, 0, 2, OS); - return NULL; - case Mips_BNE64: - // bne $r0, $zero, $L2 => bnez $r0, $L2 - if (isReg(MI, 1, Mips_ZERO_64)) - return printAlias2("bnez", MI, 0, 2, OS); - return NULL; - case Mips_BGEZAL: - // bgezal $zero, $L1 => bal $L1 - if (isReg(MI, 0, Mips_ZERO)) - return printAlias1("bal", MI, 1, OS); - return NULL; - case Mips_BC1T: - // bc1t $fcc0, $L1 => bc1t $L1 - if (isReg(MI, 0, Mips_FCC0)) - return printAlias1("bc1t", MI, 1, OS); - return NULL; - case Mips_BC1F: - // bc1f $fcc0, $L1 => bc1f $L1 - if (isReg(MI, 0, Mips_FCC0)) - return printAlias1("bc1f", MI, 1, OS); - return NULL; - case Mips_JALR: - // jalr $ra, $r1 => jalr $r1 - if (isReg(MI, 0, Mips_RA)) - return printAlias1("jalr", MI, 1, OS); - return NULL; - case Mips_JALR64: - // jalr $ra, $r1 => jalr $r1 - if (isReg(MI, 0, Mips_RA_64)) - return printAlias1("jalr", MI, 1, OS); - return NULL; - case Mips_NOR: - case Mips_NOR_MM: - // nor $r0, $r1, $zero => not $r0, $r1 - if (isReg(MI, 2, Mips_ZERO)) - return printAlias2("not", MI, 0, 1, OS); - return NULL; - case Mips_NOR64: - // nor $r0, $r1, $zero => not $r0, $r1 - if (isReg(MI, 2, Mips_ZERO_64)) - return printAlias2("not", MI, 0, 1, OS); - return NULL; - case Mips_OR: - // or $r0, $r1, $zero => move $r0, $r1 - if (isReg(MI, 2, Mips_ZERO)) - return printAlias2("move", MI, 0, 1, OS); - return NULL; - default: return NULL; - } +//#define GET_REGINFO_ENUM +//#include "MipsGenRegisterInfo.inc" + +static char *printAlias(MCInst *MI, SStream *OS) { + switch (MCInst_getOpcode(MI)) { + case Mips_BEQ: + case Mips_BEQ_MM: + // beq $zero, $zero, $L2 => b $L2 + // beq $r0, $zero, $L2 => beqz $r0, $L2 + if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) + return printAlias1("b", MI, 2, OS); + if (isReg(MI, 1, Mips_ZERO)) + return printAlias2("beqz", MI, 0, 2, OS); + return NULL; + case Mips_BEQ64: + // beq $r0, $zero, $L2 => beqz $r0, $L2 + if (isReg(MI, 1, Mips_ZERO_64)) + return printAlias2("beqz", MI, 0, 2, OS); + return NULL; + case Mips_BNE: + // bne $r0, $zero, $L2 => bnez $r0, $L2 + if (isReg(MI, 1, Mips_ZERO)) + return printAlias2("bnez", MI, 0, 2, OS); + return NULL; + case Mips_BNE64: + // bne $r0, $zero, $L2 => bnez $r0, $L2 + if (isReg(MI, 1, Mips_ZERO_64)) + return printAlias2("bnez", MI, 0, 2, OS); + return NULL; + case Mips_BGEZAL: + // bgezal $zero, $L1 => bal $L1 + if (isReg(MI, 0, Mips_ZERO)) + return printAlias1("bal", MI, 1, OS); + return NULL; + case Mips_BC1T: + // bc1t $fcc0, $L1 => bc1t $L1 + if (isReg(MI, 0, Mips_FCC0)) + return printAlias1("bc1t", MI, 1, OS); + return NULL; + case Mips_BC1F: + // bc1f $fcc0, $L1 => bc1f $L1 + if (isReg(MI, 0, Mips_FCC0)) + return printAlias1("bc1f", MI, 1, OS); + return NULL; + case Mips_JALR: + // jalr $ra, $r1 => jalr $r1 + if (isReg(MI, 0, Mips_RA)) + return printAlias1("jalr", MI, 1, OS); + return NULL; + case Mips_JALR64: + // jalr $ra, $r1 => jalr $r1 + if (isReg(MI, 0, Mips_RA_64)) + return printAlias1("jalr", MI, 1, OS); + return NULL; + case Mips_NOR: + case Mips_NOR_MM: + // nor $r0, $r1, $zero => not $r0, $r1 + if (isReg(MI, 2, Mips_ZERO)) + return printAlias2("not", MI, 0, 1, OS); + return NULL; + case Mips_NOR64: + // nor $r0, $r1, $zero => not $r0, $r1 + if (isReg(MI, 2, Mips_ZERO_64)) + return printAlias2("not", MI, 0, 1, OS); + return NULL; + case Mips_OR: + // or $r0, $r1, $zero => move $r0, $r1 + if (isReg(MI, 2, Mips_ZERO)) + return printAlias2("move", MI, 0, 1, OS); + return NULL; + default: + return NULL; + } } -static void printRegisterList(MCInst *MI, int opNum, SStream *O) -{ - int i, e, reg; - - // - 2 because register List is always first operand of instruction and it is - // always followed by memory operand (base + offset). - for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { - if (i != opNum) - SStream_concat0(O, ", "); - reg = MCOperand_getReg(MCInst_getOperand(MI, i)); - printRegName(O, reg); - if (MI->csh->detail) { - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; - MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; - MI->flat_insn->detail->mips.op_count++; - } - } +static void printRegisterList(MCInst *MI, int opNum, SStream *O) { + int i, e, reg; + + // - 2 because register List is always first operand of instruction and it is + // always followed by memory operand (base + offset). + for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { + if (i != opNum) + SStream_concat0(O, ", "); + reg = MCOperand_getReg(MCInst_getOperand(MI, i)); + printRegName(O, reg); + if (MI->csh->detail) { + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count] + .type = MIPS_OP_REG; + MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count] + .reg = reg; + MI->flat_insn->detail->mips.op_count++; + } + } } -#define PRINT_ALIAS_INSTR -#include "MipsGenAsmWriter.inc" - #endif diff --git a/arch/Mips/MipsMapperInfo.inc b/arch/Mips/MipsMapperInfo.inc new file mode 100644 index 0000000000..65f7342010 --- /dev/null +++ b/arch/Mips/MipsMapperInfo.inc @@ -0,0 +1,30121 @@ +static const insn_map insns[] = { + // dummy item + {0, + 0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + + {/* abs */ + Mips_ABSMacro, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* abs.d */ + Mips_FABS_D32, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* abs.d */ + Mips_FABS_D32_MM, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* abs.d */ + Mips_FABS_D64, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* abs.d */ + Mips_FABS_D64_MM, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* abs.s */ + Mips_FABS_S, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* abs.s */ + Mips_FABS_S_MM, + MIPS_INS_ABS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* absq_s.ph */ + Mips_ABSQ_S_PH_MM, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* absq_s.ph */ + Mips_ABSQ_S_PH, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* absq_s.qb */ + Mips_ABSQ_S_QB_MMR2, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* absq_s.qb */ + Mips_ABSQ_S_QB, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* absq_s.w */ + Mips_ABSQ_S_W_MM, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* absq_s.w */ + Mips_ABSQ_S_W, + MIPS_INS_ABSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD_MMR6, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADDi, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADDi_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADD_MMR6, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADDi, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add */ + Mips_ADDi_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.d */ + Mips_FADD_D32, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.d */ + Mips_FADD_D32_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* add.d */ + Mips_FADD_D64, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.d */ + Mips_FADD_D64_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* add.ps */ + Mips_FADD_PS64, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.s */ + Mips_FADD_S, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* add.s */ + Mips_FADD_S_MMR6, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* add.s */ + Mips_FADD_S_MM, + MIPS_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* add_a.b */ + Mips_ADD_A_B, + MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* add_a.d */ + Mips_ADD_A_D, + MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* add_a.h */ + Mips_ADD_A_H, + MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* add_a.w */ + Mips_ADD_A_W, + MIPS_INS_ADD_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addi */ + Mips_ADDi_MM, + MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addi */ + Mips_ADDi, + MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addi */ + Mips_ADDi_MM, + MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addi */ + Mips_ADDi, + MIPS_INS_ADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuSpImmX16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuRxImmX16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDIU_MMR6, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDiu_MM, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDiu, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuRxPcImmX16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuRxRyOffMemX16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDIU_MMR6, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDiu_MM, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_ADDiu, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuSpImm16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiu */ + Mips_AddiuRxRxImm16, + MIPS_INS_ADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addiupc */ + Mips_ADDIUPC, + MIPS_INS_ADDIUPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiupc */ + Mips_ADDIUPC_MMR6, + MIPS_INS_ADDIUPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiupc */ + Mips_ADDIUPC_MM, + MIPS_INS_ADDIUPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addiur1sp */ + Mips_ADDIUR1SP_MM, + MIPS_INS_ADDIUR1SP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiur2 */ + Mips_ADDIUR2_MM, + MIPS_INS_ADDIUR2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addius5 */ + Mips_ADDIUS5_MM, + MIPS_INS_ADDIUS5, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addiusp */ + Mips_ADDIUSP_MM, + MIPS_INS_ADDIUSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addq.ph */ + Mips_ADDQ_PH_MM, + MIPS_INS_ADDQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq.ph */ + Mips_ADDQ_PH, + MIPS_INS_ADDQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq_s.ph */ + Mips_ADDQ_S_PH_MM, + MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq_s.ph */ + Mips_ADDQ_S_PH, + MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq_s.w */ + Mips_ADDQ_S_W_MM, + MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addq_s.w */ + Mips_ADDQ_S_W, + MIPS_INS_ADDQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addqh.ph */ + Mips_ADDQH_PH_MMR2, + MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh.ph */ + Mips_ADDQH_PH, + MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh.w */ + Mips_ADDQH_W_MMR2, + MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh.w */ + Mips_ADDQH_W, + MIPS_INS_ADDQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh_r.ph */ + Mips_ADDQH_R_PH_MMR2, + MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh_r.ph */ + Mips_ADDQH_R_PH, + MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh_r.w */ + Mips_ADDQH_R_W_MMR2, + MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addqh_r.w */ + Mips_ADDQH_R_W, + MIPS_INS_ADDQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addr.ps */ + Mips_ADDR_PS64, + MIPS_INS_ADDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MIPS3D, 0}, + 0, + 0 +#endif + }, + {/* adds_a.b */ + Mips_ADDS_A_B, + MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_a.d */ + Mips_ADDS_A_D, + MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_a.h */ + Mips_ADDS_A_H, + MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_a.w */ + Mips_ADDS_A_W, + MIPS_INS_ADDS_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_s.b */ + Mips_ADDS_S_B, + MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_s.d */ + Mips_ADDS_S_D, + MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_s.h */ + Mips_ADDS_S_H, + MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_s.w */ + Mips_ADDS_S_W, + MIPS_INS_ADDS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_u.b */ + Mips_ADDS_U_B, + MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_u.d */ + Mips_ADDS_U_D, + MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_u.h */ + Mips_ADDS_U_H, + MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* adds_u.w */ + Mips_ADDS_U_W, + MIPS_INS_ADDS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addsc */ + Mips_ADDSC_MM, + MIPS_INS_ADDSC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addsc */ + Mips_ADDSC, + MIPS_INS_ADDSC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDU_MMR6, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDu, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDu_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDiu, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDiu_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_AdduRxRyRz16, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDU_MMR6, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDu, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDu_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDiu, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu */ + Mips_ADDiu_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* addu.ph */ + Mips_ADDU_PH_MMR2, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addu.ph */ + Mips_ADDU_PH, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addu.qb */ + Mips_ADDU_QB_MM, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addu.qb */ + Mips_ADDU_QB, + MIPS_INS_ADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addu16 */ + Mips_ADDU16_MM, + MIPS_INS_ADDU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu16 */ + Mips_ADDU16_MMR6, + MIPS_INS_ADDU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* addu_s.ph */ + Mips_ADDU_S_PH_MMR2, + MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addu_s.ph */ + Mips_ADDU_S_PH, + MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addu_s.qb */ + Mips_ADDU_S_QB_MM, + MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addu_s.qb */ + Mips_ADDU_S_QB, + MIPS_INS_ADDU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* adduh.qb */ + Mips_ADDUH_QB_MMR2, + MIPS_INS_ADDUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* adduh.qb */ + Mips_ADDUH_QB, + MIPS_INS_ADDUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* adduh_r.qb */ + Mips_ADDUH_R_QB_MMR2, + MIPS_INS_ADDUH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* adduh_r.qb */ + Mips_ADDUH_R_QB, + MIPS_INS_ADDUH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* addv.b */ + Mips_ADDV_B, + MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addv.d */ + Mips_ADDV_D, + MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addv.h */ + Mips_ADDV_H, + MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addv.w */ + Mips_ADDV_W, + MIPS_INS_ADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addvi.b */ + Mips_ADDVI_B, + MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addvi.d */ + Mips_ADDVI_D, + MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addvi.h */ + Mips_ADDVI_H, + MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addvi.w */ + Mips_ADDVI_W, + MIPS_INS_ADDVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* addwc */ + Mips_ADDWC_MM, + MIPS_INS_ADDWC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* addwc */ + Mips_ADDWC, + MIPS_INS_ADDWC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* align */ + Mips_ALIGN, + MIPS_INS_ALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* align */ + Mips_ALIGN_MMR6, + MIPS_INS_ALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* aluipc */ + Mips_ALUIPC, + MIPS_INS_ALUIPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* aluipc */ + Mips_ALUIPC_MMR6, + MIPS_INS_ALUIPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AndRxRxRy16, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND_MM, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND_MMR6, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDI_MMR6, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi_MM, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi64, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND_MM, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_AND_MMR6, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDI_MMR6, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi_MM, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and */ + Mips_ANDi64, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* and.v */ + Mips_AND_V, + MIPS_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* and16 */ + Mips_AND16_MM, + MIPS_INS_AND16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* and16 */ + Mips_AND16_MMR6, + MIPS_INS_AND16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDI_MMR6, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDi, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDi_MM, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDI_MMR6, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDi, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* andi */ + Mips_ANDi_MM, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi.b */ + Mips_ANDI_B, + MIPS_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* andi16 */ + Mips_ANDI16_MM, + MIPS_INS_ANDI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* andi16 */ + Mips_ANDI16_MMR6, + MIPS_INS_ANDI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* append */ + Mips_APPEND_MMR2, + MIPS_INS_APPEND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* append */ + Mips_APPEND, + MIPS_INS_APPEND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* asub_s.b */ + Mips_ASUB_S_B, + MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_s.d */ + Mips_ASUB_S_D, + MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_s.h */ + Mips_ASUB_S_H, + MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_s.w */ + Mips_ASUB_S_W, + MIPS_INS_ASUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_u.b */ + Mips_ASUB_U_B, + MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_u.d */ + Mips_ASUB_U_D, + MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_u.h */ + Mips_ASUB_U_H, + MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* asub_u.w */ + Mips_ASUB_U_W, + MIPS_INS_ASUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aui */ + Mips_AUI, + MIPS_INS_AUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* aui */ + Mips_AUI_MMR6, + MIPS_INS_AUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* auipc */ + Mips_AUIPC, + MIPS_INS_AUIPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* auipc */ + Mips_AUIPC_MMR6, + MIPS_INS_AUIPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ave_s.b */ + Mips_AVE_S_B, + MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_s.d */ + Mips_AVE_S_D, + MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_s.h */ + Mips_AVE_S_H, + MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_s.w */ + Mips_AVE_S_W, + MIPS_INS_AVE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_u.b */ + Mips_AVE_U_B, + MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_u.d */ + Mips_AVE_U_D, + MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_u.h */ + Mips_AVE_U_H, + MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ave_u.w */ + Mips_AVE_U_W, + MIPS_INS_AVE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_s.b */ + Mips_AVER_S_B, + MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_s.d */ + Mips_AVER_S_D, + MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_s.h */ + Mips_AVER_S_H, + MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_s.w */ + Mips_AVER_S_W, + MIPS_INS_AVER_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_u.b */ + Mips_AVER_U_B, + MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_u.d */ + Mips_AVER_U_D, + MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_u.h */ + Mips_AVER_U_H, + MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* aver_u.w */ + Mips_AVER_U_W, + MIPS_INS_AVER_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* b */ + Mips_BEQ, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* b */ + Mips_B_MM_Pseudo, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* b */ + Mips_BimmX16, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* b */ + Mips_B_MMR6_Pseudo, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* b */ + Mips_Bimm16, + MIPS_INS_B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* b16 */ + Mips_BC16_MMR6, + MIPS_INS_B16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* b16 */ + Mips_B16_MM, + MIPS_INS_B16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* baddu */ + Mips_BADDu, + MIPS_INS_BADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* baddu */ + Mips_BADDu, + MIPS_INS_BADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* bal */ + Mips_BGEZAL, + MIPS_INS_BAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bal */ + Mips_BAL, + MIPS_INS_BAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bal */ + Mips_BGEZAL_MM, + MIPS_INS_BAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* balc */ + Mips_BALC, + MIPS_INS_BALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* balc */ + Mips_BALC_MMR6, + MIPS_INS_BALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* balign */ + Mips_BALIGN_MMR2, + MIPS_INS_BALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* balign */ + Mips_BALIGN, + MIPS_INS_BALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* bbit0 */ + Mips_BBIT032, + MIPS_INS_BBIT0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit0 */ + Mips_BBIT0, + MIPS_INS_BBIT0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit032 */ + Mips_BBIT032, + MIPS_INS_BBIT032, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit1 */ + Mips_BBIT132, + MIPS_INS_BBIT1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit1 */ + Mips_BBIT1, + MIPS_INS_BBIT1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bbit132 */ + Mips_BBIT132, + MIPS_INS_BBIT132, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc */ + Mips_BC, + MIPS_INS_BC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc */ + Mips_BC_MMR6, + MIPS_INS_BC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bc16 */ + Mips_BC16_MMR6, + MIPS_INS_BC16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bc1eqz */ + Mips_BC1EQZ, + MIPS_INS_BC1EQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1eqzc */ + Mips_BC1EQZC_MMR6, + MIPS_INS_BC1EQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1f */ + Mips_BC1F, + MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1f */ + Mips_BC1F_MM, + MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1f */ + Mips_BC1F, + MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1f */ + Mips_BC1F_MM, + MIPS_INS_BC1F, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1fl */ + Mips_BC1FL, + MIPS_INS_BC1FL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1fl */ + Mips_BC1FL, + MIPS_INS_BC1FL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1nez */ + Mips_BC1NEZ, + MIPS_INS_BC1NEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1nezc */ + Mips_BC1NEZC_MMR6, + MIPS_INS_BC1NEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1t */ + Mips_BC1T, + MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1t */ + Mips_BC1T_MM, + MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1t */ + Mips_BC1T, + MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1t */ + Mips_BC1T_MM, + MIPS_INS_BC1T, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 1, + 0 +#endif + }, + {/* bc1tl */ + Mips_BC1TL, + MIPS_INS_BC1TL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc1tl */ + Mips_BC1TL, + MIPS_INS_BC1TL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc2eqz */ + Mips_BC2EQZ, + MIPS_INS_BC2EQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc2eqzc */ + Mips_BC2EQZC_MMR6, + MIPS_INS_BC2EQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bc2nez */ + Mips_BC2NEZ, + MIPS_INS_BC2NEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bc2nezc */ + Mips_BC2NEZC_MMR6, + MIPS_INS_BC2NEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bclr.b */ + Mips_BCLR_B, + MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclr.d */ + Mips_BCLR_D, + MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclr.h */ + Mips_BCLR_H, + MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclr.w */ + Mips_BCLR_W, + MIPS_INS_BCLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclri.b */ + Mips_BCLRI_B, + MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclri.d */ + Mips_BCLRI_D, + MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclri.h */ + Mips_BCLRI_H, + MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bclri.w */ + Mips_BCLRI_W, + MIPS_INS_BCLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* beq */ + Mips_BEQ, + MIPS_INS_BEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beq */ + Mips_BEQ_MM, + MIPS_INS_BEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beq */ + Mips_BeqImm, + MIPS_INS_BEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* beqc */ + Mips_BEQC, + MIPS_INS_BEQC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqc */ + Mips_BEQC_MMR6, + MIPS_INS_BEQC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqc */ + Mips_BEQC64, + MIPS_INS_BEQC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* beql */ + Mips_BEQL, + MIPS_INS_BEQL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beql */ + Mips_BEQLImmMacro, + MIPS_INS_BEQL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* beqz */ + Mips_BeqzRxImmX16, + MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* beqz */ + Mips_BEQ, + MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqz */ + Mips_BEQ_MM, + MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqz */ + Mips_BeqzRxImm16, + MIPS_INS_BEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* beqz16 */ + Mips_BEQZ16_MM, + MIPS_INS_BEQZ16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqz16 */ + Mips_BEQZC16_MMR6, + MIPS_INS_BEQZ16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzalc */ + Mips_BEQZALC, + MIPS_INS_BEQZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqzalc */ + Mips_BEQZALC_MMR6, + MIPS_INS_BEQZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzc */ + Mips_BEQZC, + MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* beqzc */ + Mips_BEQZC_MM, + MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzc */ + Mips_BEQZC_MMR6, + MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzc */ + Mips_BEQZC64, + MIPS_INS_BEQZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* beqzc16 */ + Mips_BEQZC16_MMR6, + MIPS_INS_BEQZC16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* beqzl */ + Mips_BEQL, + MIPS_INS_BEQZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bge */ + Mips_BGE, + MIPS_INS_BGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bge */ + Mips_BGEImmMacro, + MIPS_INS_BGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgec */ + Mips_BGEC, + MIPS_INS_BGEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgec */ + Mips_BGEC_MMR6, + MIPS_INS_BGEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgec */ + Mips_BGEC64, + MIPS_INS_BGEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bgel */ + Mips_BGEL, + MIPS_INS_BGEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgel */ + Mips_BGELImmMacro, + MIPS_INS_BGEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgeu */ + Mips_BGEU, + MIPS_INS_BGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgeu */ + Mips_BGEUImmMacro, + MIPS_INS_BGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgeuc */ + Mips_BGEUC, + MIPS_INS_BGEUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgeuc */ + Mips_BGEUC_MMR6, + MIPS_INS_BGEUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgeuc */ + Mips_BGEUC64, + MIPS_INS_BGEUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bgeul */ + Mips_BGEUL, + MIPS_INS_BGEUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgeul */ + Mips_BGEULImmMacro, + MIPS_INS_BGEUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgez */ + Mips_BGEZ, + MIPS_INS_BGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgez */ + Mips_BGEZ_MM, + MIPS_INS_BGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgezal */ + Mips_BGEZAL, + MIPS_INS_BGEZAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bgezal */ + Mips_BGEZAL_MM, + MIPS_INS_BGEZAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bgezalc */ + Mips_BGEZALC, + MIPS_INS_BGEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgezalc */ + Mips_BGEZALC_MMR6, + MIPS_INS_BGEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgezall */ + Mips_BGEZALL, + MIPS_INS_BGEZALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bgezals */ + Mips_BGEZALS_MM, + MIPS_INS_BGEZALS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bgezc */ + Mips_BGEZC, + MIPS_INS_BGEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgezc */ + Mips_BGEZC_MMR6, + MIPS_INS_BGEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgezc */ + Mips_BGEZC64, + MIPS_INS_BGEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bgezl */ + Mips_BGEZL, + MIPS_INS_BGEZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgt */ + Mips_BGT, + MIPS_INS_BGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgt */ + Mips_BGTImmMacro, + MIPS_INS_BGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgtl */ + Mips_BGTL, + MIPS_INS_BGTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgtl */ + Mips_BGTLImmMacro, + MIPS_INS_BGTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgtu */ + Mips_BGTU, + MIPS_INS_BGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgtu */ + Mips_BGTUImmMacro, + MIPS_INS_BGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bgtul */ + Mips_BGTUL, + MIPS_INS_BGTUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgtul */ + Mips_BGTULImmMacro, + MIPS_INS_BGTUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bgtz */ + Mips_BGTZ, + MIPS_INS_BGTZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgtz */ + Mips_BGTZ_MM, + MIPS_INS_BGTZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgtzalc */ + Mips_BGTZALC, + MIPS_INS_BGTZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgtzalc */ + Mips_BGTZALC_MMR6, + MIPS_INS_BGTZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgtzc */ + Mips_BGTZC, + MIPS_INS_BGTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bgtzc */ + Mips_BGTZC_MMR6, + MIPS_INS_BGTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bgtzc */ + Mips_BGTZC64, + MIPS_INS_BGTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bgtzl */ + Mips_BGTZL, + MIPS_INS_BGTZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* binsl.b */ + Mips_BINSL_B, + MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsl.d */ + Mips_BINSL_D, + MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsl.h */ + Mips_BINSL_H, + MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsl.w */ + Mips_BINSL_W, + MIPS_INS_BINSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsli.b */ + Mips_BINSLI_B, + MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsli.d */ + Mips_BINSLI_D, + MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsli.h */ + Mips_BINSLI_H, + MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsli.w */ + Mips_BINSLI_W, + MIPS_INS_BINSLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsr.b */ + Mips_BINSR_B, + MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsr.d */ + Mips_BINSR_D, + MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsr.h */ + Mips_BINSR_H, + MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsr.w */ + Mips_BINSR_W, + MIPS_INS_BINSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsri.b */ + Mips_BINSRI_B, + MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsri.d */ + Mips_BINSRI_D, + MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsri.h */ + Mips_BINSRI_H, + MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* binsri.w */ + Mips_BINSRI_W, + MIPS_INS_BINSRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bitrev */ + Mips_BITREV_MM, + MIPS_INS_BITREV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* bitrev */ + Mips_BITREV, + MIPS_INS_BITREV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* bitswap */ + Mips_BITSWAP, + MIPS_INS_BITSWAP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bitswap */ + Mips_BITSWAP_MMR6, + MIPS_INS_BITSWAP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ble */ + Mips_BLE, + MIPS_INS_BLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ble */ + Mips_BLEImmMacro, + MIPS_INS_BLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* blel */ + Mips_BLEL, + MIPS_INS_BLEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* blel */ + Mips_BLELImmMacro, + MIPS_INS_BLEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bleu */ + Mips_BLEU, + MIPS_INS_BLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bleu */ + Mips_BLEUImmMacro, + MIPS_INS_BLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bleul */ + Mips_BLEUL, + MIPS_INS_BLEUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bleul */ + Mips_BLEULImmMacro, + MIPS_INS_BLEUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* blez */ + Mips_BLEZ, + MIPS_INS_BLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* blez */ + Mips_BLEZ_MM, + MIPS_INS_BLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* blezalc */ + Mips_BLEZALC, + MIPS_INS_BLEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* blezalc */ + Mips_BLEZALC_MMR6, + MIPS_INS_BLEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* blezc */ + Mips_BLEZC, + MIPS_INS_BLEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* blezc */ + Mips_BLEZC_MMR6, + MIPS_INS_BLEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* blezc */ + Mips_BLEZC64, + MIPS_INS_BLEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* blezl */ + Mips_BLEZL, + MIPS_INS_BLEZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* blt */ + Mips_BLT, + MIPS_INS_BLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* blt */ + Mips_BLTImmMacro, + MIPS_INS_BLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bltc */ + Mips_BLTC, + MIPS_INS_BLTC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltc */ + Mips_BLTC_MMR6, + MIPS_INS_BLTC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltc */ + Mips_BLTC64, + MIPS_INS_BLTC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bltl */ + Mips_BLTL, + MIPS_INS_BLTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bltl */ + Mips_BLTLImmMacro, + MIPS_INS_BLTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bltu */ + Mips_BLTU, + MIPS_INS_BLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bltu */ + Mips_BLTUImmMacro, + MIPS_INS_BLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bltuc */ + Mips_BLTUC, + MIPS_INS_BLTUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltuc */ + Mips_BLTUC_MMR6, + MIPS_INS_BLTUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltuc */ + Mips_BLTUC64, + MIPS_INS_BLTUC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bltul */ + Mips_BLTUL, + MIPS_INS_BLTUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bltul */ + Mips_BLTULImmMacro, + MIPS_INS_BLTUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bltz */ + Mips_BLTZ, + MIPS_INS_BLTZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltz */ + Mips_BLTZ_MM, + MIPS_INS_BLTZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltzal */ + Mips_BLTZAL, + MIPS_INS_BLTZAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bltzal */ + Mips_BLTZAL_MM, + MIPS_INS_BLTZAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bltzalc */ + Mips_BLTZALC, + MIPS_INS_BLTZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltzalc */ + Mips_BLTZALC_MMR6, + MIPS_INS_BLTZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltzall */ + Mips_BLTZALL, + MIPS_INS_BLTZALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* bltzals */ + Mips_BLTZALS_MM, + MIPS_INS_BLTZALS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bltzc */ + Mips_BLTZC, + MIPS_INS_BLTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bltzc */ + Mips_BLTZC_MMR6, + MIPS_INS_BLTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bltzc */ + Mips_BLTZC64, + MIPS_INS_BLTZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bltzl */ + Mips_BLTZL, + MIPS_INS_BLTZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bmnz.v */ + Mips_BMNZ_V, + MIPS_INS_BMNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bmnzi.b */ + Mips_BMNZI_B, + MIPS_INS_BMNZI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bmz.v */ + Mips_BMZ_V, + MIPS_INS_BMZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bmzi.b */ + Mips_BMZI_B, + MIPS_INS_BMZI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bne */ + Mips_BNE, + MIPS_INS_BNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bne */ + Mips_BNE_MM, + MIPS_INS_BNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bne */ + Mips_BneImm, + MIPS_INS_BNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* bnec */ + Mips_BNEC, + MIPS_INS_BNEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnec */ + Mips_BNEC_MMR6, + MIPS_INS_BNEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnec */ + Mips_BNEC64, + MIPS_INS_BNEC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bneg.b */ + Mips_BNEG_B, + MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bneg.d */ + Mips_BNEG_D, + MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bneg.h */ + Mips_BNEG_H, + MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bneg.w */ + Mips_BNEG_W, + MIPS_INS_BNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnegi.b */ + Mips_BNEGI_B, + MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnegi.d */ + Mips_BNEGI_D, + MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnegi.h */ + Mips_BNEGI_H, + MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnegi.w */ + Mips_BNEGI_W, + MIPS_INS_BNEGI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bnel */ + Mips_BNEL, + MIPS_INS_BNEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnel */ + Mips_BNELImmMacro, + MIPS_INS_BNEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* bnez */ + Mips_BnezRxImmX16, + MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* bnez */ + Mips_BNE, + MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnez */ + Mips_BNE_MM, + MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnez */ + Mips_BnezRxImm16, + MIPS_INS_BNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* bnez16 */ + Mips_BNEZ16_MM, + MIPS_INS_BNEZ16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnez16 */ + Mips_BNEZC16_MMR6, + MIPS_INS_BNEZ16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezalc */ + Mips_BNEZALC, + MIPS_INS_BNEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnezalc */ + Mips_BNEZALC_MMR6, + MIPS_INS_BNEZALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezc */ + Mips_BNEZC, + MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnezc */ + Mips_BNEZC_MM, + MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezc */ + Mips_BNEZC_MMR6, + MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezc */ + Mips_BNEZC64, + MIPS_INS_BNEZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 0 +#endif + }, + {/* bnezc16 */ + Mips_BNEZC16_MMR6, + MIPS_INS_BNEZC16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnezl */ + Mips_BNEL, + MIPS_INS_BNEZL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnvc */ + Mips_BNVC, + MIPS_INS_BNVC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bnvc */ + Mips_BNVC_MMR6, + MIPS_INS_BNVC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bnz.b */ + Mips_BNZ_B, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bnz.d */ + Mips_BNZ_D, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bnz.h */ + Mips_BNZ_H, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bnz.v */ + Mips_BNZ_V, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bnz.w */ + Mips_BNZ_W, + MIPS_INS_BNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bovc */ + Mips_BOVC, + MIPS_INS_BOVC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bovc */ + Mips_BOVC_MMR6, + MIPS_INS_BOVC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* bposge32 */ + Mips_BPOSGE32_MM, + MIPS_INS_BPOSGE32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_DSP, 0}, + 1, + 0 +#endif + }, + {/* bposge32 */ + Mips_BPOSGE32, + MIPS_INS_BPOSGE32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* bposge32c */ + Mips_BPOSGE32C_MMR3, + MIPS_INS_BPOSGE32C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR3, 0}, + 1, + 0 +#endif + }, + {/* break */ + Mips_BREAK, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK_MM, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_Break16, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK_MM, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK_MMR6, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* break */ + Mips_BREAK_MM, + MIPS_INS_BREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* break16 */ + Mips_BREAK16_MM, + MIPS_INS_BREAK16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* break16 */ + Mips_BREAK16_MMR6, + MIPS_INS_BREAK16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* bsel.v */ + Mips_BSEL_V, + MIPS_INS_BSEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseli.b */ + Mips_BSELI_B, + MIPS_INS_BSELI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bset.b */ + Mips_BSET_B, + MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bset.d */ + Mips_BSET_D, + MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bset.h */ + Mips_BSET_H, + MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bset.w */ + Mips_BSET_W, + MIPS_INS_BSET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseti.b */ + Mips_BSETI_B, + MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseti.d */ + Mips_BSETI_D, + MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseti.h */ + Mips_BSETI_H, + MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bseti.w */ + Mips_BSETI_W, + MIPS_INS_BSETI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* bteqz */ + Mips_BteqzX16, + MIPS_INS_BTEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* bteqz */ + Mips_Bteqz16, + MIPS_INS_BTEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* btnez */ + Mips_BtnezX16, + MIPS_INS_BTNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* btnez */ + Mips_Btnez16, + MIPS_INS_BTNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 0 +#endif + }, + {/* bz.b */ + Mips_BZ_B, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bz.d */ + Mips_BZ_D, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bz.h */ + Mips_BZ_H, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bz.v */ + Mips_BZ_V, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* bz.w */ + Mips_BZ_W, + MIPS_INS_BZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 1, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.d */ + Mips_C_EQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.s */ + Mips_C_EQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.s */ + Mips_C_EQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.eq.s */ + Mips_C_EQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.eq.s */ + Mips_C_EQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.d */ + Mips_C_F_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.s */ + Mips_C_F_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.s */ + Mips_C_F_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.f.s */ + Mips_C_F_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.f.s */ + Mips_C_F_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.d */ + Mips_C_LE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.s */ + Mips_C_LE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.s */ + Mips_C_LE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.le.s */ + Mips_C_LE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.le.s */ + Mips_C_LE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.d */ + Mips_C_LT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.s */ + Mips_C_LT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.s */ + Mips_C_LT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.lt.s */ + Mips_C_LT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.lt.s */ + Mips_C_LT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.d */ + Mips_C_NGE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.s */ + Mips_C_NGE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.s */ + Mips_C_NGE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.nge.s */ + Mips_C_NGE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.nge.s */ + Mips_C_NGE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.d */ + Mips_C_NGL_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.s */ + Mips_C_NGL_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.s */ + Mips_C_NGL_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.s */ + Mips_C_NGL_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngl.s */ + Mips_C_NGL_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.d */ + Mips_C_NGLE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.s */ + Mips_C_NGLE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.s */ + Mips_C_NGLE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.s */ + Mips_C_NGLE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngle.s */ + Mips_C_NGLE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.d */ + Mips_C_NGT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.s */ + Mips_C_NGT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.s */ + Mips_C_NGT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.s */ + Mips_C_NGT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ngt.s */ + Mips_C_NGT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.d */ + Mips_C_OLE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.s */ + Mips_C_OLE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.s */ + Mips_C_OLE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ole.s */ + Mips_C_OLE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ole.s */ + Mips_C_OLE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.d */ + Mips_C_OLT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.s */ + Mips_C_OLT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.s */ + Mips_C_OLT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.olt.s */ + Mips_C_OLT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.olt.s */ + Mips_C_OLT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.d */ + Mips_C_SEQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.s */ + Mips_C_SEQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.s */ + Mips_C_SEQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.seq.s */ + Mips_C_SEQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.seq.s */ + Mips_C_SEQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.d */ + Mips_C_SF_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.s */ + Mips_C_SF_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.s */ + Mips_C_SF_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.sf.s */ + Mips_C_SF_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.sf.s */ + Mips_C_SF_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.d */ + Mips_C_UEQ_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.s */ + Mips_C_UEQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.s */ + Mips_C_UEQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.s */ + Mips_C_UEQ_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ueq.s */ + Mips_C_UEQ_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.d */ + Mips_C_ULE_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.s */ + Mips_C_ULE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.s */ + Mips_C_ULE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ule.s */ + Mips_C_ULE_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ule.s */ + Mips_C_ULE_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.d */ + Mips_C_ULT_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.s */ + Mips_C_ULT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.s */ + Mips_C_ULT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.ult.s */ + Mips_C_ULT_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.ult.s */ + Mips_C_ULT_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D32, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D32_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D64, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.d */ + Mips_C_UN_D64_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.s */ + Mips_C_UN_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.s */ + Mips_C_UN_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* c.un.s */ + Mips_C_UN_S, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* c.un.s */ + Mips_C_UN_S_MM, + MIPS_INS_C, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cache */ + Mips_CACHE_R6, + MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cache */ + Mips_CACHE, + MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cache */ + Mips_CACHE_MM, + MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* cache */ + Mips_CACHE_MMR6, + MIPS_INS_CACHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* cachee */ + Mips_CACHEE, + MIPS_INS_CACHEE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* cachee */ + Mips_CACHEE_MM, + MIPS_INS_CACHEE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* ceil.l.d */ + Mips_CEIL_L_D64, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.l.d */ + Mips_CEIL_L_D_MMR6, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.l.s */ + Mips_CEIL_L_S, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.l.s */ + Mips_CEIL_L_S_MMR6, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.d */ + Mips_CEIL_W_D32, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.d */ + Mips_CEIL_W_D_MMR6, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.d */ + Mips_CEIL_W_MM, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.d */ + Mips_CEIL_W_D64, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.s */ + Mips_CEIL_W_S, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.s */ + Mips_CEIL_W_S_MMR6, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceil.w.s */ + Mips_CEIL_W_S_MM, + MIPS_INS_CEIL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ceq.b */ + Mips_CEQ_B, + MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceq.d */ + Mips_CEQ_D, + MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceq.h */ + Mips_CEQ_H, + MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceq.w */ + Mips_CEQ_W, + MIPS_INS_CEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceqi.b */ + Mips_CEQI_B, + MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceqi.d */ + Mips_CEQI_D, + MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceqi.h */ + Mips_CEQI_H, + MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ceqi.w */ + Mips_CEQI_W, + MIPS_INS_CEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cfc1 */ + Mips_CFC1, + MIPS_INS_CFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cfc1 */ + Mips_CFC1_MM, + MIPS_INS_CFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cfc2 */ + Mips_CFC2_MM, + MIPS_INS_CFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cfcmsa */ + Mips_CFCMSA, + MIPS_INS_CFCMSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cftc1 */ + Mips_CFTC1, + MIPS_INS_CFTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* cins */ + Mips_CINS, + MIPS_INS_CINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins */ + Mips_CINS32, + MIPS_INS_CINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins */ + Mips_CINS, + MIPS_INS_CINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins */ + Mips_CINS32, + MIPS_INS_CINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins32 */ + Mips_CINS32, + MIPS_INS_CINS32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cins32 */ + Mips_CINS32, + MIPS_INS_CINS32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* class.d */ + Mips_CLASS_D, + MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* class.d */ + Mips_CLASS_D_MMR6, + MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* class.s */ + Mips_CLASS_S, + MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* class.s */ + Mips_CLASS_S_MMR6, + MIPS_INS_CLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* cle_s.b */ + Mips_CLE_S_B, + MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_s.d */ + Mips_CLE_S_D, + MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_s.h */ + Mips_CLE_S_H, + MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_s.w */ + Mips_CLE_S_W, + MIPS_INS_CLE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_u.b */ + Mips_CLE_U_B, + MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_u.d */ + Mips_CLE_U_D, + MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_u.h */ + Mips_CLE_U_H, + MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cle_u.w */ + Mips_CLE_U_W, + MIPS_INS_CLE_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_s.b */ + Mips_CLEI_S_B, + MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_s.d */ + Mips_CLEI_S_D, + MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_s.h */ + Mips_CLEI_S_H, + MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_s.w */ + Mips_CLEI_S_W, + MIPS_INS_CLEI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_u.b */ + Mips_CLEI_U_B, + MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_u.d */ + Mips_CLEI_U_D, + MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_u.h */ + Mips_CLEI_U_H, + MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clei_u.w */ + Mips_CLEI_U_W, + MIPS_INS_CLEI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clo */ + Mips_CLO, + MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* clo */ + Mips_CLO_MMR6, + MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* clo */ + Mips_CLO_R6, + MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* clo */ + Mips_CLO_MM, + MIPS_INS_CLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* clt_s.b */ + Mips_CLT_S_B, + MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_s.d */ + Mips_CLT_S_D, + MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_s.h */ + Mips_CLT_S_H, + MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_s.w */ + Mips_CLT_S_W, + MIPS_INS_CLT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_u.b */ + Mips_CLT_U_B, + MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_u.d */ + Mips_CLT_U_D, + MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_u.h */ + Mips_CLT_U_H, + MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clt_u.w */ + Mips_CLT_U_W, + MIPS_INS_CLT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_s.b */ + Mips_CLTI_S_B, + MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_s.d */ + Mips_CLTI_S_D, + MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_s.h */ + Mips_CLTI_S_H, + MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_s.w */ + Mips_CLTI_S_W, + MIPS_INS_CLTI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_u.b */ + Mips_CLTI_U_B, + MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_u.d */ + Mips_CLTI_U_D, + MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_u.h */ + Mips_CLTI_U_H, + MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clti_u.w */ + Mips_CLTI_U_W, + MIPS_INS_CLTI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* clz */ + Mips_CLZ, + MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* clz */ + Mips_CLZ_MMR6, + MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* clz */ + Mips_CLZ_R6, + MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* clz */ + Mips_CLZ_MM, + MIPS_INS_CLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp */ + Mips_CmpRxRy16, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* cmp.af.d */ + Mips_CMP_F_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.af.d */ + Mips_CMP_AF_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.af.s */ + Mips_CMP_F_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.af.s */ + Mips_CMP_AF_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.d */ + Mips_CMP_EQ_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.d */ + Mips_CMP_EQ_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.ph */ + Mips_CMP_EQ_PH_MM, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.ph */ + Mips_CMP_EQ_PH, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.s */ + Mips_CMP_EQ_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.eq.s */ + Mips_CMP_EQ_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.d */ + Mips_CMP_LE_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.d */ + Mips_CMP_LE_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.ph */ + Mips_CMP_LE_PH_MM, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.ph */ + Mips_CMP_LE_PH, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.s */ + Mips_CMP_LE_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.le.s */ + Mips_CMP_LE_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.d */ + Mips_CMP_LT_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.d */ + Mips_CMP_LT_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.ph */ + Mips_CMP_LT_PH_MM, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.ph */ + Mips_CMP_LT_PH, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.s */ + Mips_CMP_LT_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.lt.s */ + Mips_CMP_LT_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.saf.d */ + Mips_CMP_SAF_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.saf.d */ + Mips_CMP_SAF_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.saf.s */ + Mips_CMP_SAF_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.saf.s */ + Mips_CMP_SAF_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.seq.d */ + Mips_CMP_SEQ_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.seq.d */ + Mips_CMP_SEQ_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.seq.s */ + Mips_CMP_SEQ_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.seq.s */ + Mips_CMP_SEQ_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sle.d */ + Mips_CMP_SLE_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sle.d */ + Mips_CMP_SLE_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sle.s */ + Mips_CMP_SLE_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sle.s */ + Mips_CMP_SLE_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.slt.d */ + Mips_CMP_SLT_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.slt.d */ + Mips_CMP_SLT_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.slt.s */ + Mips_CMP_SLT_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.slt.s */ + Mips_CMP_SLT_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sueq.d */ + Mips_CMP_SUEQ_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sueq.d */ + Mips_CMP_SUEQ_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sueq.s */ + Mips_CMP_SUEQ_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sueq.s */ + Mips_CMP_SUEQ_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sule.d */ + Mips_CMP_SULE_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sule.d */ + Mips_CMP_SULE_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sule.s */ + Mips_CMP_SULE_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sule.s */ + Mips_CMP_SULE_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sult.d */ + Mips_CMP_SULT_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sult.d */ + Mips_CMP_SULT_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sult.s */ + Mips_CMP_SULT_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sult.s */ + Mips_CMP_SULT_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sun.d */ + Mips_CMP_SUN_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sun.d */ + Mips_CMP_SUN_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.sun.s */ + Mips_CMP_SUN_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.sun.s */ + Mips_CMP_SUN_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ueq.d */ + Mips_CMP_UEQ_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ueq.d */ + Mips_CMP_UEQ_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ueq.s */ + Mips_CMP_UEQ_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ueq.s */ + Mips_CMP_UEQ_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ule.d */ + Mips_CMP_ULE_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ule.d */ + Mips_CMP_ULE_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ule.s */ + Mips_CMP_ULE_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ule.s */ + Mips_CMP_ULE_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ult.d */ + Mips_CMP_ULT_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ult.d */ + Mips_CMP_ULT_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.ult.s */ + Mips_CMP_ULT_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.ult.s */ + Mips_CMP_ULT_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.un.d */ + Mips_CMP_UN_D, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.un.d */ + Mips_CMP_UN_D_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmp.un.s */ + Mips_CMP_UN_S, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cmp.un.s */ + Mips_CMP_UN_S_MMR6, + MIPS_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.eq.qb */ + Mips_CMPGDU_EQ_QB_MMR2, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.eq.qb */ + Mips_CMPGDU_EQ_QB, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.le.qb */ + Mips_CMPGDU_LE_QB_MMR2, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.le.qb */ + Mips_CMPGDU_LE_QB, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.lt.qb */ + Mips_CMPGDU_LT_QB_MMR2, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgdu.lt.qb */ + Mips_CMPGDU_LT_QB, + MIPS_INS_CMPGDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.eq.qb */ + Mips_CMPGU_EQ_QB_MM, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.eq.qb */ + Mips_CMPGU_EQ_QB, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.le.qb */ + Mips_CMPGU_LE_QB_MM, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.le.qb */ + Mips_CMPGU_LE_QB, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.lt.qb */ + Mips_CMPGU_LT_QB_MM, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpgu.lt.qb */ + Mips_CMPGU_LT_QB, + MIPS_INS_CMPGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpi */ + Mips_CmpiRxImmX16, + MIPS_INS_CMPI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* cmpi */ + Mips_CmpiRxImm16, + MIPS_INS_CMPI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* cmpu.eq.qb */ + Mips_CMPU_EQ_QB_MM, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.eq.qb */ + Mips_CMPU_EQ_QB, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.le.qb */ + Mips_CMPU_LE_QB_MM, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.le.qb */ + Mips_CMPU_LE_QB, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.lt.qb */ + Mips_CMPU_LT_QB_MM, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* cmpu.lt.qb */ + Mips_CMPU_LT_QB, + MIPS_INS_CMPU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* copy_s.b */ + Mips_COPY_S_B, + MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_s.d */ + Mips_COPY_S_D, + MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* copy_s.h */ + Mips_COPY_S_H, + MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_s.w */ + Mips_COPY_S_W, + MIPS_INS_COPY_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_u.b */ + Mips_COPY_U_B, + MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_u.h */ + Mips_COPY_U_H, + MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* copy_u.w */ + Mips_COPY_U_W, + MIPS_INS_COPY_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* crc32b */ + Mips_CRC32B, + MIPS_INS_CRC32B, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32cb */ + Mips_CRC32CB, + MIPS_INS_CRC32CB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32cd */ + Mips_CRC32CD, + MIPS_INS_CRC32CD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32ch */ + Mips_CRC32CH, + MIPS_INS_CRC32CH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32cw */ + Mips_CRC32CW, + MIPS_INS_CRC32CW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32d */ + Mips_CRC32D, + MIPS_INS_CRC32D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32h */ + Mips_CRC32H, + MIPS_INS_CRC32H, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* crc32w */ + Mips_CRC32W, + MIPS_INS_CRC32W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_CRC, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* ctc1 */ + Mips_CTC1, + MIPS_INS_CTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ctc1 */ + Mips_CTC1_MM, + MIPS_INS_CTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ctc2 */ + Mips_CTC2_MM, + MIPS_INS_CTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ctcmsa */ + Mips_CTCMSA, + MIPS_INS_CTCMSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* cttc1 */ + Mips_CTTC1, + MIPS_INS_CTTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.l */ + Mips_CVT_D64_L, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.l */ + Mips_CVT_D_L_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.s */ + Mips_CVT_D32_S, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.s */ + Mips_CVT_D32_S_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.s */ + Mips_CVT_D64_S, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.s */ + Mips_CVT_D64_S_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.w */ + Mips_CVT_D32_W, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.w */ + Mips_CVT_D32_W_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.w */ + Mips_CVT_D64_W, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.d.w */ + Mips_CVT_D64_W_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.d */ + Mips_CVT_L_D64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.d */ + Mips_CVT_L_D64_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.d */ + Mips_CVT_L_D_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.s */ + Mips_CVT_L_S, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.s */ + Mips_CVT_L_S_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.l.s */ + Mips_CVT_L_S_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.ps.pw */ + Mips_CVT_PS_PW64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MIPS3D, 0}, + 0, + 0 +#endif + }, + {/* cvt.ps.s */ + Mips_CVT_PS_S64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.pw.ps */ + Mips_CVT_PW_PS64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MIPS3D, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.d */ + Mips_CVT_S_D32, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.d */ + Mips_CVT_S_D32_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.d */ + Mips_CVT_S_D64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.d */ + Mips_CVT_S_D64_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.l */ + Mips_CVT_S_L, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.l */ + Mips_CVT_S_L_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.pl */ + Mips_CVT_S_PL64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.pu */ + Mips_CVT_S_PU64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.w */ + Mips_CVT_S_W, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.w */ + Mips_CVT_S_W_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.s.w */ + Mips_CVT_S_W_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.d */ + Mips_CVT_W_D32, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.d */ + Mips_CVT_W_D32_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.d */ + Mips_CVT_W_D64, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.d */ + Mips_CVT_W_D64_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.s */ + Mips_CVT_W_S, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.s */ + Mips_CVT_W_S_MMR6, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* cvt.w.s */ + Mips_CVT_W_S_MM, + MIPS_INS_CVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* dadd */ + Mips_DADD, + MIPS_INS_DADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dadd */ + Mips_DADDi, + MIPS_INS_DADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dadd */ + Mips_DADD, + MIPS_INS_DADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dadd */ + Mips_DADDi, + MIPS_INS_DADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddi */ + Mips_DADDi, + MIPS_INS_DADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* daddi */ + Mips_DADDi, + MIPS_INS_DADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* daddiu */ + Mips_DADDiu, + MIPS_INS_DADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddiu */ + Mips_DADDiu, + MIPS_INS_DADDIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddu */ + Mips_DADDu, + MIPS_INS_DADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddu */ + Mips_DADDiu, + MIPS_INS_DADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddu */ + Mips_DADDu, + MIPS_INS_DADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daddu */ + Mips_DADDiu, + MIPS_INS_DADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dahi */ + Mips_DAHI, + MIPS_INS_DAHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dalign */ + Mips_DALIGN, + MIPS_INS_DALIGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dati */ + Mips_DATI, + MIPS_INS_DATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* daui */ + Mips_DAUI, + MIPS_INS_DAUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dbitswap */ + Mips_DBITSWAP, + MIPS_INS_DBITSWAP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dclo */ + Mips_DCLO, + MIPS_INS_DCLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dclo */ + Mips_DCLO_R6, + MIPS_INS_DCLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dclz */ + Mips_DCLZ, + MIPS_INS_DCLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dclz */ + Mips_DCLZ_R6, + MIPS_INS_DCLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDivMacro, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDivIMacro, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDIV, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDivMacro, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DDIV, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddiv */ + Mips_DSDivIMacro, + MIPS_INS_DDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDivMacro, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDivIMacro, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDIV, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDivMacro, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DDIVU, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ddivu */ + Mips_DUDivIMacro, + MIPS_INS_DDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* deret */ + Mips_DERET, + MIPS_INS_DERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* deret */ + Mips_DERET_MMR6, + MIPS_INS_DERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* deret */ + Mips_DERET_MM, + MIPS_INS_DERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dext */ + Mips_DEXTM, + MIPS_INS_DEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dext */ + Mips_DEXTU, + MIPS_INS_DEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dext */ + Mips_DEXT, + MIPS_INS_DEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dextm */ + Mips_DEXTM, + MIPS_INS_DEXTM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dextu */ + Mips_DEXTU, + MIPS_INS_DEXTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI_MMR6, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI_MM, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI_MMR6, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* di */ + Mips_DI_MM, + MIPS_INS_DI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dins */ + Mips_DINSM, + MIPS_INS_DINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dins */ + Mips_DINSU, + MIPS_INS_DINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dins */ + Mips_DINS, + MIPS_INS_DINS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dinsm */ + Mips_DINSM, + MIPS_INS_DINSM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dinsu */ + Mips_DINSU, + MIPS_INS_DINSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_DIV, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDivIMacro, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDivMacro, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDIV, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_DivRxRy16, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDIV, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDIV_MM, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_DIV, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_DIV_MMR6, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDivIMacro, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div */ + Mips_SDivMacro, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* div.d */ + Mips_FDIV_D32, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div.d */ + Mips_FDIV_D32_MM, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* div.d */ + Mips_FDIV_D64, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div.d */ + Mips_FDIV_D64_MM, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* div.s */ + Mips_FDIV_S, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* div.s */ + Mips_FDIV_S_MMR6, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* div.s */ + Mips_FDIV_S_MM, + MIPS_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* div_s.b */ + Mips_DIV_S_B, + MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_s.d */ + Mips_DIV_S_D, + MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_s.h */ + Mips_DIV_S_H, + MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_s.w */ + Mips_DIV_S_W, + MIPS_INS_DIV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_u.b */ + Mips_DIV_U_B, + MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_u.d */ + Mips_DIV_U_D, + MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_u.h */ + Mips_DIV_U_H, + MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* div_u.w */ + Mips_DIV_U_W, + MIPS_INS_DIV_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_DIVU, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDivIMacro, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDivMacro, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDIV, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_DivuRxRy16, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDIV, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDIV_MM, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDivMacro, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_DIVU, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_DIVU_MMR6, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* divu */ + Mips_UDivIMacro, + MIPS_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dla */ + Mips_LoadAddrImm64, + MIPS_INS_DLA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dla */ + Mips_LoadAddrReg64, + MIPS_INS_DLA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dli */ + Mips_LoadImm64, + MIPS_INS_DLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dlsa */ + Mips_DLSA, + MIPS_INS_DLSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dlsa */ + Mips_DLSA_R6, + MIPS_INS_DLSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfc0 */ + Mips_DMFC0, + MIPS_INS_DMFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfc0 */ + Mips_DMFC0, + MIPS_INS_DMFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dmfc1 */ + Mips_DMFC1, + MIPS_INS_DMFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfc2 */ + Mips_DMFC2, + MIPS_INS_DMFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dmfc2 */ + Mips_DMFC2_OCTEON, + MIPS_INS_DMFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfc2 */ + Mips_DMFC2, + MIPS_INS_DMFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dmfgc0 */ + Mips_DMFGC0, + MIPS_INS_DMFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmfgc0 */ + Mips_DMFGC0, + MIPS_INS_DMFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* dmod */ + Mips_DMOD, + MIPS_INS_DMOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmodu */ + Mips_DMODU, + MIPS_INS_DMODU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmt */ + Mips_DMT, + MIPS_INS_DMT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmt */ + Mips_DMT, + MIPS_INS_DMT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtc0 */ + Mips_DMTC0, + MIPS_INS_DMTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtc0 */ + Mips_DMTC0, + MIPS_INS_DMTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dmtc1 */ + Mips_DMTC1, + MIPS_INS_DMTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtc2 */ + Mips_DMTC2, + MIPS_INS_DMTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* dmtc2 */ + Mips_DMTC2_OCTEON, + MIPS_INS_DMTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtc2 */ + Mips_DMTC2, + MIPS_INS_DMTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dmtgc0 */ + Mips_DMTGC0, + MIPS_INS_DMTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmtgc0 */ + Mips_DMTGC0, + MIPS_INS_DMTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* dmuh */ + Mips_DMUH, + MIPS_INS_DMUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmuhu */ + Mips_DMUHU, + MIPS_INS_DMUHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMUL, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMULMacro, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMUL_R6, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMUL, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmul */ + Mips_DMULImmMacro, + MIPS_INS_DMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dmulo */ + Mips_DMULOMacro, + MIPS_INS_DMULO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dmulou */ + Mips_DMULOUMacro, + MIPS_INS_DMULOU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dmult */ + Mips_DMULT, + MIPS_INS_DMULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmultu */ + Mips_DMULTu, + MIPS_INS_DMULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dmulu */ + Mips_DMULU, + MIPS_INS_DMULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dneg */ + Mips_DSUB, + MIPS_INS_DNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dneg */ + Mips_DSUB, + MIPS_INS_DNEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dnegu */ + Mips_DSUBu, + MIPS_INS_DNEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dnegu */ + Mips_DSUBu, + MIPS_INS_DNEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dotp_s.d */ + Mips_DOTP_S_D, + MIPS_INS_DOTP_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_s.h */ + Mips_DOTP_S_H, + MIPS_INS_DOTP_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_s.w */ + Mips_DOTP_S_W, + MIPS_INS_DOTP_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_u.d */ + Mips_DOTP_U_D, + MIPS_INS_DOTP_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_u.h */ + Mips_DOTP_U_H, + MIPS_INS_DOTP_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dotp_u.w */ + Mips_DOTP_U_W, + MIPS_INS_DOTP_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpa.w.ph */ + Mips_DPA_W_PH_MMR2, + MIPS_INS_DPA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpa.w.ph */ + Mips_DPA_W_PH, + MIPS_INS_DPA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpadd_s.d */ + Mips_DPADD_S_D, + MIPS_INS_DPADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_s.h */ + Mips_DPADD_S_H, + MIPS_INS_DPADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_s.w */ + Mips_DPADD_S_W, + MIPS_INS_DPADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_u.d */ + Mips_DPADD_U_D, + MIPS_INS_DPADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_u.h */ + Mips_DPADD_U_H, + MIPS_INS_DPADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpadd_u.w */ + Mips_DPADD_U_W, + MIPS_INS_DPADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpaq_s.w.ph */ + Mips_DPAQ_S_W_PH_MM, + MIPS_INS_DPAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpaq_s.w.ph */ + Mips_DPAQ_S_W_PH, + MIPS_INS_DPAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpaq_sa.l.w */ + Mips_DPAQ_SA_L_W_MM, + MIPS_INS_DPAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpaq_sa.l.w */ + Mips_DPAQ_SA_L_W, + MIPS_INS_DPAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpaqx_s.w.ph */ + Mips_DPAQX_S_W_PH_MMR2, + MIPS_INS_DPAQX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpaqx_s.w.ph */ + Mips_DPAQX_S_W_PH, + MIPS_INS_DPAQX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpaqx_sa.w.ph */ + Mips_DPAQX_SA_W_PH_MMR2, + MIPS_INS_DPAQX_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpaqx_sa.w.ph */ + Mips_DPAQX_SA_W_PH, + MIPS_INS_DPAQX_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpau.h.qbl */ + Mips_DPAU_H_QBL_MM, + MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpau.h.qbl */ + Mips_DPAU_H_QBL, + MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpau.h.qbr */ + Mips_DPAU_H_QBR_MM, + MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpau.h.qbr */ + Mips_DPAU_H_QBR, + MIPS_INS_DPAU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpax.w.ph */ + Mips_DPAX_W_PH_MMR2, + MIPS_INS_DPAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpax.w.ph */ + Mips_DPAX_W_PH, + MIPS_INS_DPAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpop */ + Mips_DPOP, + MIPS_INS_DPOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dpop */ + Mips_DPOP, + MIPS_INS_DPOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* dps.w.ph */ + Mips_DPS_W_PH_MMR2, + MIPS_INS_DPS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dps.w.ph */ + Mips_DPS_W_PH, + MIPS_INS_DPS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsq_s.w.ph */ + Mips_DPSQ_S_W_PH_MM, + MIPS_INS_DPSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsq_s.w.ph */ + Mips_DPSQ_S_W_PH, + MIPS_INS_DPSQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsq_sa.l.w */ + Mips_DPSQ_SA_L_W_MM, + MIPS_INS_DPSQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsq_sa.l.w */ + Mips_DPSQ_SA_L_W, + MIPS_INS_DPSQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsqx_s.w.ph */ + Mips_DPSQX_S_W_PH_MMR2, + MIPS_INS_DPSQX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsqx_s.w.ph */ + Mips_DPSQX_S_W_PH, + MIPS_INS_DPSQX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsqx_sa.w.ph */ + Mips_DPSQX_SA_W_PH_MMR2, + MIPS_INS_DPSQX_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsqx_sa.w.ph */ + Mips_DPSQX_SA_W_PH, + MIPS_INS_DPSQX_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsu.h.qbl */ + Mips_DPSU_H_QBL_MM, + MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsu.h.qbl */ + Mips_DPSU_H_QBL, + MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsu.h.qbr */ + Mips_DPSU_H_QBR_MM, + MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsu.h.qbr */ + Mips_DPSU_H_QBR, + MIPS_INS_DPSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* dpsub_s.d */ + Mips_DPSUB_S_D, + MIPS_INS_DPSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_s.h */ + Mips_DPSUB_S_H, + MIPS_INS_DPSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_s.w */ + Mips_DPSUB_S_W, + MIPS_INS_DPSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_u.d */ + Mips_DPSUB_U_D, + MIPS_INS_DPSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_u.h */ + Mips_DPSUB_U_H, + MIPS_INS_DPSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsub_u.w */ + Mips_DPSUB_U_W, + MIPS_INS_DPSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* dpsx.w.ph */ + Mips_DPSX_W_PH_MMR2, + MIPS_INS_DPSX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* dpsx.w.ph */ + Mips_DPSX_W_PH, + MIPS_INS_DPSX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* drem */ + Mips_DSRemMacro, + MIPS_INS_DREM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drem */ + Mips_DSRemIMacro, + MIPS_INS_DREM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drem */ + Mips_DSRemMacro, + MIPS_INS_DREM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drem */ + Mips_DSRemIMacro, + MIPS_INS_DREM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dremu */ + Mips_DURemMacro, + MIPS_INS_DREMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dremu */ + Mips_DURemIMacro, + MIPS_INS_DREMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dremu */ + Mips_DURemMacro, + MIPS_INS_DREMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dremu */ + Mips_DURemIMacro, + MIPS_INS_DREMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drol */ + Mips_DROL, + MIPS_INS_DROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* drol */ + Mips_DROLImm, + MIPS_INS_DROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* drol */ + Mips_DROL, + MIPS_INS_DROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* drol */ + Mips_DROLImm, + MIPS_INS_DROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dror */ + Mips_DROR, + MIPS_INS_DROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dror */ + Mips_DRORImm, + MIPS_INS_DROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dror */ + Mips_DROR, + MIPS_INS_DROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* dror */ + Mips_DRORImm, + MIPS_INS_DROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* drotr */ + Mips_DROTR, + MIPS_INS_DROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drotr */ + Mips_DROTR, + MIPS_INS_DROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drotr32 */ + Mips_DROTR32, + MIPS_INS_DROTR32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drotr32 */ + Mips_DROTR32, + MIPS_INS_DROTR32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* drotrv */ + Mips_DROTRV, + MIPS_INS_DROTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsbh */ + Mips_DSBH, + MIPS_INS_DSBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dshd */ + Mips_DSHD, + MIPS_INS_DSHD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll */ + Mips_DSLLV, + MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll */ + Mips_DSLL, + MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll */ + Mips_DSLLV, + MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll */ + Mips_DSLL, + MIPS_INS_DSLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll32 */ + Mips_DSLL32, + MIPS_INS_DSLL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsll32 */ + Mips_DSLL32, + MIPS_INS_DSLL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsllv */ + Mips_DSLLV, + MIPS_INS_DSLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsra */ + Mips_DSRA, + MIPS_INS_DSRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsra */ + Mips_DSRAV, + MIPS_INS_DSRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0}, + 0, + 0 +#endif + }, + {/* dsra */ + Mips_DSRA, + MIPS_INS_DSRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsra32 */ + Mips_DSRA32, + MIPS_INS_DSRA32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsra32 */ + Mips_DSRA32, + MIPS_INS_DSRA32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrav */ + Mips_DSRAV, + MIPS_INS_DSRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl */ + Mips_DSRLV, + MIPS_INS_DSRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl */ + Mips_DSRL, + MIPS_INS_DSRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl */ + Mips_DSRLV, + MIPS_INS_DSRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl */ + Mips_DSRL, + MIPS_INS_DSRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl32 */ + Mips_DSRL32, + MIPS_INS_DSRL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrl32 */ + Mips_DSRL32, + MIPS_INS_DSRL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsrlv */ + Mips_DSRLV, + MIPS_INS_DSRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsub */ + Mips_DSUB, + MIPS_INS_DSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsub */ + Mips_DADDi, + MIPS_INS_DSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dsub */ + Mips_DSUB, + MIPS_INS_DSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsub */ + Mips_DADDi, + MIPS_INS_DSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dsubi */ + Mips_DADDi, + MIPS_INS_DSUBI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dsubi */ + Mips_DADDi, + MIPS_INS_DSUBI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* dsubu */ + Mips_DSUBu, + MIPS_INS_DSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsubu */ + Mips_DADDiu, + MIPS_INS_DSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsubu */ + Mips_DSUBu, + MIPS_INS_DSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dsubu */ + Mips_DADDiu, + MIPS_INS_DSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dvp */ + Mips_DVP, + MIPS_INS_DVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* dvp */ + Mips_DVP_MMR6, + MIPS_INS_DVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* dvp */ + Mips_DVP, + MIPS_INS_DVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* dvp */ + Mips_DVP_MMR6, + MIPS_INS_DVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* dvpe */ + Mips_DVPE, + MIPS_INS_DVPE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* dvpe */ + Mips_DVPE, + MIPS_INS_DVPE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ehb */ + Mips_EHB, + MIPS_INS_EHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ehb */ + Mips_EHB_MMR6, + MIPS_INS_EHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ehb */ + Mips_EHB_MM, + MIPS_INS_EHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI_MMR6, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI_MM, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI_MMR6, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ei */ + Mips_EI_MM, + MIPS_INS_EI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* emt */ + Mips_EMT, + MIPS_INS_EMT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* emt */ + Mips_EMT, + MIPS_INS_EMT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* eret */ + Mips_ERET, + MIPS_INS_ERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* eret */ + Mips_ERET_MMR6, + MIPS_INS_ERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* eret */ + Mips_ERET_MM, + MIPS_INS_ERET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* eretnc */ + Mips_ERETNC, + MIPS_INS_ERETNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* eretnc */ + Mips_ERETNC_MMR6, + MIPS_INS_ERETNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evp */ + Mips_EVP, + MIPS_INS_EVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evp */ + Mips_EVP_MMR6, + MIPS_INS_EVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evp */ + Mips_EVP, + MIPS_INS_EVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evp */ + Mips_EVP_MMR6, + MIPS_INS_EVP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* evpe */ + Mips_EVPE, + MIPS_INS_EVPE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* evpe */ + Mips_EVPE, + MIPS_INS_EVPE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ext */ + Mips_EXT, + MIPS_INS_EXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ext */ + Mips_EXT_MM, + MIPS_INS_EXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ext */ + Mips_EXT_MMR6, + MIPS_INS_EXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* extp */ + Mips_EXTP_MM, + MIPS_INS_EXTP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extp */ + Mips_EXTP, + MIPS_INS_EXTP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpdp */ + Mips_EXTPDP_MM, + MIPS_INS_EXTPDP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpdp */ + Mips_EXTPDP, + MIPS_INS_EXTPDP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpdpv */ + Mips_EXTPDPV_MM, + MIPS_INS_EXTPDPV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpdpv */ + Mips_EXTPDPV, + MIPS_INS_EXTPDPV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpv */ + Mips_EXTPV_MM, + MIPS_INS_EXTPV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extpv */ + Mips_EXTPV, + MIPS_INS_EXTPV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr.w */ + Mips_EXTR_W_MM, + MIPS_INS_EXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr.w */ + Mips_EXTR_W, + MIPS_INS_EXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_r.w */ + Mips_EXTR_R_W_MM, + MIPS_INS_EXTR_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_r.w */ + Mips_EXTR_R_W, + MIPS_INS_EXTR_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_rs.w */ + Mips_EXTR_RS_W_MM, + MIPS_INS_EXTR_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_rs.w */ + Mips_EXTR_RS_W, + MIPS_INS_EXTR_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_s.h */ + Mips_EXTR_S_H_MM, + MIPS_INS_EXTR_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extr_s.h */ + Mips_EXTR_S_H, + MIPS_INS_EXTR_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv.w */ + Mips_EXTRV_W_MM, + MIPS_INS_EXTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv.w */ + Mips_EXTRV_W, + MIPS_INS_EXTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_r.w */ + Mips_EXTRV_R_W_MM, + MIPS_INS_EXTRV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_r.w */ + Mips_EXTRV_R_W, + MIPS_INS_EXTRV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_rs.w */ + Mips_EXTRV_RS_W_MM, + MIPS_INS_EXTRV_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_rs.w */ + Mips_EXTRV_RS_W, + MIPS_INS_EXTRV_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_s.h */ + Mips_EXTRV_S_H_MM, + MIPS_INS_EXTRV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* extrv_s.h */ + Mips_EXTRV_S_H, + MIPS_INS_EXTRV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* exts */ + Mips_EXTS, + MIPS_INS_EXTS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts */ + Mips_EXTS32, + MIPS_INS_EXTS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts */ + Mips_EXTS, + MIPS_INS_EXTS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts */ + Mips_EXTS32, + MIPS_INS_EXTS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts32 */ + Mips_EXTS32, + MIPS_INS_EXTS32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* exts32 */ + Mips_EXTS32, + MIPS_INS_EXTS32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* fadd.d */ + Mips_FADD_D, + MIPS_INS_FADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fadd.w */ + Mips_FADD_W, + MIPS_INS_FADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcaf.d */ + Mips_FCAF_D, + MIPS_INS_FCAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcaf.w */ + Mips_FCAF_W, + MIPS_INS_FCAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fceq.d */ + Mips_FCEQ_D, + MIPS_INS_FCEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fceq.w */ + Mips_FCEQ_W, + MIPS_INS_FCEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fclass.d */ + Mips_FCLASS_D, + MIPS_INS_FCLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fclass.w */ + Mips_FCLASS_W, + MIPS_INS_FCLASS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcle.d */ + Mips_FCLE_D, + MIPS_INS_FCLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcle.w */ + Mips_FCLE_W, + MIPS_INS_FCLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fclt.d */ + Mips_FCLT_D, + MIPS_INS_FCLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fclt.w */ + Mips_FCLT_W, + MIPS_INS_FCLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcne.d */ + Mips_FCNE_D, + MIPS_INS_FCNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcne.w */ + Mips_FCNE_W, + MIPS_INS_FCNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcor.d */ + Mips_FCOR_D, + MIPS_INS_FCOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcor.w */ + Mips_FCOR_W, + MIPS_INS_FCOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcueq.d */ + Mips_FCUEQ_D, + MIPS_INS_FCUEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcueq.w */ + Mips_FCUEQ_W, + MIPS_INS_FCUEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcule.d */ + Mips_FCULE_D, + MIPS_INS_FCULE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcule.w */ + Mips_FCULE_W, + MIPS_INS_FCULE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcult.d */ + Mips_FCULT_D, + MIPS_INS_FCULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcult.w */ + Mips_FCULT_W, + MIPS_INS_FCULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcun.d */ + Mips_FCUN_D, + MIPS_INS_FCUN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcun.w */ + Mips_FCUN_W, + MIPS_INS_FCUN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcune.d */ + Mips_FCUNE_D, + MIPS_INS_FCUNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fcune.w */ + Mips_FCUNE_W, + MIPS_INS_FCUNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fdiv.d */ + Mips_FDIV_D, + MIPS_INS_FDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fdiv.w */ + Mips_FDIV_W, + MIPS_INS_FDIV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexdo.h */ + Mips_FEXDO_H, + MIPS_INS_FEXDO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexdo.w */ + Mips_FEXDO_W, + MIPS_INS_FEXDO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexp2.d */ + Mips_FEXP2_D, + MIPS_INS_FEXP2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexp2.w */ + Mips_FEXP2_W, + MIPS_INS_FEXP2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexupl.d */ + Mips_FEXUPL_D, + MIPS_INS_FEXUPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexupl.w */ + Mips_FEXUPL_W, + MIPS_INS_FEXUPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexupr.d */ + Mips_FEXUPR_D, + MIPS_INS_FEXUPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fexupr.w */ + Mips_FEXUPR_W, + MIPS_INS_FEXUPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffint_s.d */ + Mips_FFINT_S_D, + MIPS_INS_FFINT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffint_s.w */ + Mips_FFINT_S_W, + MIPS_INS_FFINT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffint_u.d */ + Mips_FFINT_U_D, + MIPS_INS_FFINT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffint_u.w */ + Mips_FFINT_U_W, + MIPS_INS_FFINT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffql.d */ + Mips_FFQL_D, + MIPS_INS_FFQL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffql.w */ + Mips_FFQL_W, + MIPS_INS_FFQL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffqr.d */ + Mips_FFQR_D, + MIPS_INS_FFQR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ffqr.w */ + Mips_FFQR_W, + MIPS_INS_FFQR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fill.b */ + Mips_FILL_B, + MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fill.d */ + Mips_FILL_D, + MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* fill.h */ + Mips_FILL_H, + MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fill.w */ + Mips_FILL_W, + MIPS_INS_FILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* flog2.d */ + Mips_FLOG2_D, + MIPS_INS_FLOG2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* flog2.w */ + Mips_FLOG2_W, + MIPS_INS_FLOG2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* floor.l.d */ + Mips_FLOOR_L_D64, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.l.d */ + Mips_FLOOR_L_D_MMR6, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.l.s */ + Mips_FLOOR_L_S, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.l.s */ + Mips_FLOOR_L_S_MMR6, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.w.d */ + Mips_FLOOR_W_D32, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.w.d */ + Mips_FLOOR_W_D_MMR6, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.w.d */ + Mips_FLOOR_W_MM, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.w.d */ + Mips_FLOOR_W_D64, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.w.s */ + Mips_FLOOR_W_S, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* floor.w.s */ + Mips_FLOOR_W_S_MMR6, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* floor.w.s */ + Mips_FLOOR_W_S_MM, + MIPS_INS_FLOOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* fmadd.d */ + Mips_FMADD_D, + MIPS_INS_FMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmadd.w */ + Mips_FMADD_W, + MIPS_INS_FMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmax.d */ + Mips_FMAX_D, + MIPS_INS_FMAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmax.w */ + Mips_FMAX_W, + MIPS_INS_FMAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmax_a.d */ + Mips_FMAX_A_D, + MIPS_INS_FMAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmax_a.w */ + Mips_FMAX_A_W, + MIPS_INS_FMAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmin.d */ + Mips_FMIN_D, + MIPS_INS_FMIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmin.w */ + Mips_FMIN_W, + MIPS_INS_FMIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmin_a.d */ + Mips_FMIN_A_D, + MIPS_INS_FMIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmin_a.w */ + Mips_FMIN_A_W, + MIPS_INS_FMIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmsub.d */ + Mips_FMSUB_D, + MIPS_INS_FMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmsub.w */ + Mips_FMSUB_W, + MIPS_INS_FMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmul.d */ + Mips_FMUL_D, + MIPS_INS_FMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fmul.w */ + Mips_FMUL_W, + MIPS_INS_FMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fork */ + Mips_FORK, + MIPS_INS_FORK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* frcp.d */ + Mips_FRCP_D, + MIPS_INS_FRCP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frcp.w */ + Mips_FRCP_W, + MIPS_INS_FRCP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frint.d */ + Mips_FRINT_D, + MIPS_INS_FRINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frint.w */ + Mips_FRINT_W, + MIPS_INS_FRINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frsqrt.d */ + Mips_FRSQRT_D, + MIPS_INS_FRSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* frsqrt.w */ + Mips_FRSQRT_W, + MIPS_INS_FRSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsaf.d */ + Mips_FSAF_D, + MIPS_INS_FSAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsaf.w */ + Mips_FSAF_W, + MIPS_INS_FSAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fseq.d */ + Mips_FSEQ_D, + MIPS_INS_FSEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fseq.w */ + Mips_FSEQ_W, + MIPS_INS_FSEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsle.d */ + Mips_FSLE_D, + MIPS_INS_FSLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsle.w */ + Mips_FSLE_W, + MIPS_INS_FSLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fslt.d */ + Mips_FSLT_D, + MIPS_INS_FSLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fslt.w */ + Mips_FSLT_W, + MIPS_INS_FSLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsne.d */ + Mips_FSNE_D, + MIPS_INS_FSNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsne.w */ + Mips_FSNE_W, + MIPS_INS_FSNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsor.d */ + Mips_FSOR_D, + MIPS_INS_FSOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsor.w */ + Mips_FSOR_W, + MIPS_INS_FSOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsqrt.d */ + Mips_FSQRT_D, + MIPS_INS_FSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsqrt.w */ + Mips_FSQRT_W, + MIPS_INS_FSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsub.d */ + Mips_FSUB_D, + MIPS_INS_FSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsub.w */ + Mips_FSUB_W, + MIPS_INS_FSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsueq.d */ + Mips_FSUEQ_D, + MIPS_INS_FSUEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsueq.w */ + Mips_FSUEQ_W, + MIPS_INS_FSUEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsule.d */ + Mips_FSULE_D, + MIPS_INS_FSULE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsule.w */ + Mips_FSULE_W, + MIPS_INS_FSULE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsult.d */ + Mips_FSULT_D, + MIPS_INS_FSULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsult.w */ + Mips_FSULT_W, + MIPS_INS_FSULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsun.d */ + Mips_FSUN_D, + MIPS_INS_FSUN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsun.w */ + Mips_FSUN_W, + MIPS_INS_FSUN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsune.d */ + Mips_FSUNE_D, + MIPS_INS_FSUNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* fsune.w */ + Mips_FSUNE_W, + MIPS_INS_FSUNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftint_s.d */ + Mips_FTINT_S_D, + MIPS_INS_FTINT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftint_s.w */ + Mips_FTINT_S_W, + MIPS_INS_FTINT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftint_u.d */ + Mips_FTINT_U_D, + MIPS_INS_FTINT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftint_u.w */ + Mips_FTINT_U_W, + MIPS_INS_FTINT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftq.h */ + Mips_FTQ_H, + MIPS_INS_FTQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftq.w */ + Mips_FTQ_W, + MIPS_INS_FTQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftrunc_s.d */ + Mips_FTRUNC_S_D, + MIPS_INS_FTRUNC_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftrunc_s.w */ + Mips_FTRUNC_S_W, + MIPS_INS_FTRUNC_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftrunc_u.d */ + Mips_FTRUNC_U_D, + MIPS_INS_FTRUNC_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ftrunc_u.w */ + Mips_FTRUNC_U_W, + MIPS_INS_FTRUNC_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ginvi */ + Mips_GINVI, + MIPS_INS_GINVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_GINV, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ginvi */ + Mips_GINVI_MMR6, + MIPS_INS_GINVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_GINV, 0}, + 0, + 0 +#endif + }, + {/* ginvt */ + Mips_GINVT, + MIPS_INS_GINVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_GINV, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ginvt */ + Mips_GINVT_MMR6, + MIPS_INS_GINVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_GINV, 0}, + 0, + 0 +#endif + }, + {/* hadd_s.d */ + Mips_HADD_S_D, + MIPS_INS_HADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_s.h */ + Mips_HADD_S_H, + MIPS_INS_HADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_s.w */ + Mips_HADD_S_W, + MIPS_INS_HADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_u.d */ + Mips_HADD_U_D, + MIPS_INS_HADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_u.h */ + Mips_HADD_U_H, + MIPS_INS_HADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hadd_u.w */ + Mips_HADD_U_W, + MIPS_INS_HADD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_s.d */ + Mips_HSUB_S_D, + MIPS_INS_HSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_s.h */ + Mips_HSUB_S_H, + MIPS_INS_HSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_s.w */ + Mips_HSUB_S_W, + MIPS_INS_HSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_u.d */ + Mips_HSUB_U_D, + MIPS_INS_HSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_u.h */ + Mips_HSUB_U_H, + MIPS_INS_HSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hsub_u.w */ + Mips_HSUB_U_W, + MIPS_INS_HSUB_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* hypcall */ + Mips_HYPCALL, + MIPS_INS_HYPCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* hypcall */ + Mips_HYPCALL_MM, + MIPS_INS_HYPCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* hypcall */ + Mips_HYPCALL, + MIPS_INS_HYPCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* hypcall */ + Mips_HYPCALL_MM, + MIPS_INS_HYPCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* ilvev.b */ + Mips_ILVEV_B, + MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvev.d */ + Mips_ILVEV_D, + MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvev.h */ + Mips_ILVEV_H, + MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvev.w */ + Mips_ILVEV_W, + MIPS_INS_ILVEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvl.b */ + Mips_ILVL_B, + MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvl.d */ + Mips_ILVL_D, + MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvl.h */ + Mips_ILVL_H, + MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvl.w */ + Mips_ILVL_W, + MIPS_INS_ILVL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvod.b */ + Mips_ILVOD_B, + MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvod.d */ + Mips_ILVOD_D, + MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvod.h */ + Mips_ILVOD_H, + MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvod.w */ + Mips_ILVOD_W, + MIPS_INS_ILVOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvr.b */ + Mips_ILVR_B, + MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvr.d */ + Mips_ILVR_D, + MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvr.h */ + Mips_ILVR_H, + MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ilvr.w */ + Mips_ILVR_W, + MIPS_INS_ILVR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ins */ + Mips_INS, + MIPS_INS_INS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ins */ + Mips_INS_MM, + MIPS_INS_INS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ins */ + Mips_INS_MMR6, + MIPS_INS_INS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* insert.b */ + Mips_INSERT_B, + MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insert.d */ + Mips_INSERT_D, + MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0}, + 0, + 0 +#endif + }, + {/* insert.h */ + Mips_INSERT_H, + MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insert.w */ + Mips_INSERT_W, + MIPS_INS_INSERT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insv */ + Mips_INSV_MM, + MIPS_INS_INSV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* insv */ + Mips_INSV, + MIPS_INS_INSV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* insve.b */ + Mips_INSVE_B, + MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insve.d */ + Mips_INSVE_D, + MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insve.h */ + Mips_INSVE_H, + MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* insve.w */ + Mips_INSVE_W, + MIPS_INS_INSVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* j */ + Mips_JR, + MIPS_INS_J, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* j */ + Mips_JR_MM, + MIPS_INS_J, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* j */ + Mips_J_MM, + MIPS_INS_J, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* j */ + Mips_J, + MIPS_INS_J, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 0 +#endif + }, + {/* jal */ + Mips_JalOneReg, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* jal */ + Mips_JAL_MM, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jal */ + Mips_JAL, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* jal */ + Mips_BALC_MMR6, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 0 +#endif + }, + {/* jal */ + Mips_JalTwoReg, + MIPS_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR16_MM, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALRC16_MMR6, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOINDIRECTJUMPGUARDS, + 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR_MM, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalr */ + Mips_JALR64, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMIPS16MODE, MIPS_GRP_PTR64BIT, 0}, + 0, + 0 +#endif + }, + {/* jalr.hb */ + Mips_JALR_HB, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 1 +#endif + }, + {/* jalr.hb */ + Mips_JALR_HB64, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 1 +#endif + }, + {/* jalr.hb */ + Mips_JALR_HB, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0}, + 0, + 1 +#endif + }, + {/* jalr.hb */ + Mips_JALR_HB64, + MIPS_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 1 +#endif + }, + {/* jalrc */ + Mips_JumpLinkReg16, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* jalrc */ + Mips_JIALC, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* jalrc */ + Mips_JALRC_MMR6, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalrc */ + Mips_JIALC64, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jalrc */ + Mips_JALRC_MMR6, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalrc.hb */ + Mips_JALRC_HB_MMR6, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 1 +#endif + }, + {/* jalrc.hb */ + Mips_JALRC_HB_MMR6, + MIPS_INS_JALRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 1 +#endif + }, + {/* jalrs */ + Mips_JALRS_MM, + MIPS_INS_JALRS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalrs16 */ + Mips_JALRS16_MM, + MIPS_INS_JALRS16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jals */ + Mips_JALS_MM, + MIPS_INS_JALS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jalx */ + Mips_JALX, + MIPS_INS_JALX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* jalx */ + Mips_JALX_MM, + MIPS_INS_JALX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jialc */ + Mips_JIALC, + MIPS_INS_JIALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jialc */ + Mips_JIALC_MMR6, + MIPS_INS_JIALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jialc */ + Mips_JIALC64, + MIPS_INS_JIALC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jic */ + Mips_JIC, + MIPS_INS_JIC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jic */ + Mips_JIC_MMR6, + MIPS_INS_JIC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* jic */ + Mips_JIC64, + MIPS_INS_JIC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JrRa16, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JR, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JALR, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* jr */ + Mips_JR_MM, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JR64, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMIPS16MODE, MIPS_GRP_PTR64BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* jr */ + Mips_JALR64, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* jr.hb */ + Mips_JR_HB, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jr.hb */ + Mips_JR_HB_R6, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jr.hb */ + Mips_JR_HB64, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 1, + 1 +#endif + }, + {/* jr.hb */ + Mips_JR_HB64_R6, + MIPS_INS_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jr16 */ + Mips_JR16_MM, + MIPS_INS_JR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jraddiusp */ + Mips_JRADDIUSP, + MIPS_INS_JRADDIUSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JrcRa16, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JrcRx16, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JIC, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JRC16_MM, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jrc */ + Mips_JIC64, + MIPS_INS_JRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 1, + 1 +#endif + }, + {/* jrc16 */ + Mips_JRC16_MMR6, + MIPS_INS_JRC16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* jrcaddiusp */ + Mips_JRCADDIUSP_MMR6, + MIPS_INS_JRCADDIUSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 1, + 1 +#endif + }, + {/* l.d */ + Mips_LDC1, + MIPS_INS_L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* l.d */ + Mips_LDC164, + MIPS_INS_L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + 0}, + 0, + 0 +#endif + }, + {/* l.s */ + Mips_LWC1, + MIPS_INS_L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* la */ + Mips_LoadAddrImm32, + MIPS_INS_LA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* la */ + Mips_LoadAddrReg32, + MIPS_INS_LA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* lapc */ + Mips_ADDIUPC, + MIPS_INS_LAPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lapc */ + Mips_ADDIUPC_MMR6, + MIPS_INS_LAPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lb */ + Mips_LB, + MIPS_INS_LB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lb */ + Mips_LB_MMR6, + MIPS_INS_LB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lb */ + Mips_LB_MM, + MIPS_INS_LB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lbe */ + Mips_LBE, + MIPS_INS_LBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lbe */ + Mips_LBE_MM, + MIPS_INS_LBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lbu */ + Mips_LBu, + MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lbu */ + Mips_LBU_MMR6, + MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lbu */ + Mips_LBu_MM, + MIPS_INS_LBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lbu16 */ + Mips_LBU16_MM, + MIPS_INS_LBU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lbue */ + Mips_LBuE, + MIPS_INS_LBUE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lbue */ + Mips_LBuE_MM, + MIPS_INS_LBUE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lbux */ + Mips_LBUX_MM, + MIPS_INS_LBUX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lbux */ + Mips_LBUX, + MIPS_INS_LBUX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* ld */ + Mips_LDMacro, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS3, 0}, + 0, + 0 +#endif + }, + {/* ld */ + Mips_LD, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ld.b */ + Mips_LD_B, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ld.d */ + Mips_LD_D, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ld.h */ + Mips_LD_H, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ld.w */ + Mips_LD_W, + MIPS_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldc1 */ + Mips_LDC1, + MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldc1 */ + Mips_LDC1_MM, + MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ldc1 */ + Mips_LDC164, + MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldc1 */ + Mips_LDC1_D64_MMR6, + MIPS_INS_LDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* ldc2 */ + Mips_LDC2_R6, + MIPS_INS_LDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldc2 */ + Mips_LDC2_MMR6, + MIPS_INS_LDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ldc2 */ + Mips_LDC2, + MIPS_INS_LDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldc3 */ + Mips_LDC3, + MIPS_INS_LDC3, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTCNMIPS, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldi.b */ + Mips_LDI_B, + MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldi.d */ + Mips_LDI_D, + MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldi.h */ + Mips_LDI_H, + MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldi.w */ + Mips_LDI_W, + MIPS_INS_LDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* ldl */ + Mips_LDL, + MIPS_INS_LDL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* ldpc */ + Mips_LDPC, + MIPS_INS_LDPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* ldr */ + Mips_LDR, + MIPS_INS_LDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* ldxc1 */ + Mips_LDXC1, + MIPS_INS_LDXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ldxc1 */ + Mips_LDXC164, + MIPS_INS_LDXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lh */ + Mips_LH, + MIPS_INS_LH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lh */ + Mips_LH_MM, + MIPS_INS_LH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lhe */ + Mips_LHE, + MIPS_INS_LHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lhe */ + Mips_LHE_MM, + MIPS_INS_LHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lhu */ + Mips_LHu, + MIPS_INS_LHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lhu */ + Mips_LHu_MM, + MIPS_INS_LHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lhu16 */ + Mips_LHU16_MM, + MIPS_INS_LHU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lhue */ + Mips_LHuE, + MIPS_INS_LHUE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lhue */ + Mips_LHuE_MM, + MIPS_INS_LHUE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lhx */ + Mips_LHX_MM, + MIPS_INS_LHX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lhx */ + Mips_LHX, + MIPS_INS_LHX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* li */ + Mips_LiRxImmX16, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* li */ + Mips_LoadImm32, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* li */ + Mips_LiRxImm16, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* li.d */ + Mips_LoadImmDoubleGPR, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* li.d */ + Mips_LoadImmDoubleFGR_32, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* li.d */ + Mips_LoadImmDoubleFGR, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* li.s */ + Mips_LoadImmSingleGPR, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* li.s */ + Mips_LoadImmSingleFGR, + MIPS_INS_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* li16 */ + Mips_LI16_MM, + MIPS_INS_LI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* li16 */ + Mips_LI16_MMR6, + MIPS_INS_LI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL64_R6, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR64BIT, MIPS_GRP_MIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL_R6, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL_MMR6, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR32BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL64, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ll */ + Mips_LL_MM, + MIPS_INS_LL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lld */ + Mips_LLD, + MIPS_INS_LLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lld */ + Mips_LLD_R6, + MIPS_INS_LLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lle */ + Mips_LLE, + MIPS_INS_LLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lle */ + Mips_LLE_MM, + MIPS_INS_LLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lsa */ + Mips_LSA, + MIPS_INS_LSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* lsa */ + Mips_LSA_MMR6, + MIPS_INS_LSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lsa */ + Mips_LSA_R6, + MIPS_INS_LSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lui */ + Mips_LUI_MMR6, + MIPS_INS_LUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lui */ + Mips_LUi, + MIPS_INS_LUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lui */ + Mips_LUi_MM, + MIPS_INS_LUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* luxc1 */ + Mips_LUXC1, + MIPS_INS_LUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* luxc1 */ + Mips_LUXC164, + MIPS_INS_LUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* luxc1 */ + Mips_LUXC1_MM, + MIPS_INS_LUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LwRxPcTcpX16, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LWSP_MM, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LW, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LWDSP, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMIPS16MODE, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LWDSP_MM, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LW_MMR6, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LW_MM, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LWGP_MM, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LwRxSpImmX16, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* lw */ + Mips_LwRxPcTcp16, + MIPS_INS_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* lw16 */ + Mips_LW16_MM, + MIPS_INS_LW16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwc1 */ + Mips_LWC1, + MIPS_INS_LWC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwc1 */ + Mips_LWC1_MM, + MIPS_INS_LWC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lwc2 */ + Mips_LWC2_R6, + MIPS_INS_LWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwc2 */ + Mips_LWC2_MMR6, + MIPS_INS_LWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwc2 */ + Mips_LWC2, + MIPS_INS_LWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwc3 */ + Mips_LWC3, + MIPS_INS_LWC3, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTCNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwe */ + Mips_LWE, + MIPS_INS_LWE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* lwe */ + Mips_LWE_MM, + MIPS_INS_LWE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lwl */ + Mips_LWL, + MIPS_INS_LWL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwl */ + Mips_LWL_MM, + MIPS_INS_LWL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwle */ + Mips_LWLE, + MIPS_INS_LWLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwle */ + Mips_LWLE_MM, + MIPS_INS_LWLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lwm */ + Mips_LWM_MM, + MIPS_INS_LWM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwm16 */ + Mips_LWM16_MM, + MIPS_INS_LWM16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwm16 */ + Mips_LWM16_MMR6, + MIPS_INS_LWM16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwm32 */ + Mips_LWM32_MM, + MIPS_INS_LWM32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwp */ + Mips_LWP_MM, + MIPS_INS_LWP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwpc */ + Mips_LWPC, + MIPS_INS_LWPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwpc */ + Mips_LWPC_MMR6, + MIPS_INS_LWPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwr */ + Mips_LWR, + MIPS_INS_LWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwr */ + Mips_LWR_MM, + MIPS_INS_LWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwre */ + Mips_LWRE, + MIPS_INS_LWRE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwre */ + Mips_LWRE_MM, + MIPS_INS_LWRE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* lwu */ + Mips_LWU_MM, + MIPS_INS_LWU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* lwu */ + Mips_LWu, + MIPS_INS_LWU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* lwupc */ + Mips_LWUPC, + MIPS_INS_LWUPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* lwx */ + Mips_LWX_MM, + MIPS_INS_LWX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lwx */ + Mips_LWX, + MIPS_INS_LWX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* lwxc1 */ + Mips_LWXC1, + MIPS_INS_LWXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lwxc1 */ + Mips_LWXC1_MM, + MIPS_INS_LWXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* lwxs */ + Mips_LWXS_MM, + MIPS_INS_LWXS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* madd */ + Mips_MADD, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* madd */ + Mips_MADD_MM, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* madd */ + Mips_MADD_DSP_MM, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* madd */ + Mips_MADD_DSP, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* madd.d */ + Mips_MADD_D32, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* madd.d */ + Mips_MADD_D32_MM, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* madd.d */ + Mips_MADD_D64, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* madd.s */ + Mips_MADD_S, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* madd.s */ + Mips_MADD_S_MM, + MIPS_INS_MADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* madd_q.h */ + Mips_MADD_Q_H, + MIPS_INS_MADD_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* madd_q.w */ + Mips_MADD_Q_W, + MIPS_INS_MADD_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddf.d */ + Mips_MADDF_D, + MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maddf.d */ + Mips_MADDF_D_MMR6, + MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* maddf.s */ + Mips_MADDF_S, + MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maddf.s */ + Mips_MADDF_S_MMR6, + MIPS_INS_MADDF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* maddr_q.h */ + Mips_MADDR_Q_H, + MIPS_INS_MADDR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddr_q.w */ + Mips_MADDR_Q_W, + MIPS_INS_MADDR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddu */ + Mips_MADDU, + MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maddu */ + Mips_MADDU_MM, + MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* maddu */ + Mips_MADDU_DSP_MM, + MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maddu */ + Mips_MADDU_DSP, + MIPS_INS_MADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maddv.b */ + Mips_MADDV_B, + MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddv.d */ + Mips_MADDV_D, + MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddv.h */ + Mips_MADDV_H, + MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maddv.w */ + Mips_MADDV_W, + MIPS_INS_MADDV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maq_s.w.phl */ + Mips_MAQ_S_W_PHL_MM, + MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_s.w.phl */ + Mips_MAQ_S_W_PHL, + MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_s.w.phr */ + Mips_MAQ_S_W_PHR_MM, + MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_s.w.phr */ + Mips_MAQ_S_W_PHR, + MIPS_INS_MAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_sa.w.phl */ + Mips_MAQ_SA_W_PHL_MM, + MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_sa.w.phl */ + Mips_MAQ_SA_W_PHL, + MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_sa.w.phr */ + Mips_MAQ_SA_W_PHR_MM, + MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* maq_sa.w.phr */ + Mips_MAQ_SA_W_PHR, + MIPS_INS_MAQ_SA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* max.d */ + Mips_MAX_D, + MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* max.d */ + Mips_MAX_D_MMR6, + MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* max.s */ + Mips_MAX_S, + MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* max.s */ + Mips_MAX_S_MMR6, + MIPS_INS_MAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* max_a.b */ + Mips_MAX_A_B, + MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_a.d */ + Mips_MAX_A_D, + MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_a.h */ + Mips_MAX_A_H, + MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_a.w */ + Mips_MAX_A_W, + MIPS_INS_MAX_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_s.b */ + Mips_MAX_S_B, + MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_s.d */ + Mips_MAX_S_D, + MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_s.h */ + Mips_MAX_S_H, + MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_s.w */ + Mips_MAX_S_W, + MIPS_INS_MAX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_u.b */ + Mips_MAX_U_B, + MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_u.d */ + Mips_MAX_U_D, + MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_u.h */ + Mips_MAX_U_H, + MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* max_u.w */ + Mips_MAX_U_W, + MIPS_INS_MAX_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxa.d */ + Mips_MAXA_D, + MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maxa.d */ + Mips_MAXA_D_MMR6, + MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* maxa.s */ + Mips_MAXA_S, + MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* maxa.s */ + Mips_MAXA_S_MMR6, + MIPS_INS_MAXA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* maxi_s.b */ + Mips_MAXI_S_B, + MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_s.d */ + Mips_MAXI_S_D, + MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_s.h */ + Mips_MAXI_S_H, + MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_s.w */ + Mips_MAXI_S_W, + MIPS_INS_MAXI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_u.b */ + Mips_MAXI_U_B, + MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_u.d */ + Mips_MAXI_U_D, + MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_u.h */ + Mips_MAXI_U_H, + MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* maxi_u.w */ + Mips_MAXI_U_W, + MIPS_INS_MAXI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mfc0 */ + Mips_MFC0, + MIPS_INS_MFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc0 */ + Mips_MFC0_MMR6, + MIPS_INS_MFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfc0 */ + Mips_MFC0, + MIPS_INS_MFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc0 */ + Mips_MFC0_MMR6, + MIPS_INS_MFC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfc1 */ + Mips_MFC1, + MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc1 */ + Mips_MFC1_MMR6, + MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mfc1 */ + Mips_MFC1_MM, + MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mfc1 */ + Mips_MFC1_D64, + MIPS_INS_MFC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc2 */ + Mips_MFC2_MMR6, + MIPS_INS_MFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfc2 */ + Mips_MFC2, + MIPS_INS_MFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfc2 */ + Mips_MFC2, + MIPS_INS_MFC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfgc0 */ + Mips_MFGC0, + MIPS_INS_MFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfgc0 */ + Mips_MFGC0_MM, + MIPS_INS_MFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mfgc0 */ + Mips_MFGC0, + MIPS_INS_MFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfgc0 */ + Mips_MFGC0_MM, + MIPS_INS_MFGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mfhc0 */ + Mips_MFHC0_MMR6, + MIPS_INS_MFHC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfhc0 */ + Mips_MFHC0_MMR6, + MIPS_INS_MFHC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfhc1 */ + Mips_MFHC1_D32, + MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhc1 */ + Mips_MFHC1_D32_MM, + MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mfhc1 */ + Mips_MFHC1_D64, + MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhc1 */ + Mips_MFHC1_D64_MM, + MIPS_INS_MFHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mfhc2 */ + Mips_MFHC2_MMR6, + MIPS_INS_MFHC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfhgc0 */ + Mips_MFHGC0, + MIPS_INS_MFHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhgc0 */ + Mips_MFHGC0_MM, + MIPS_INS_MFHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mfhgc0 */ + Mips_MFHGC0, + MIPS_INS_MFHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhgc0 */ + Mips_MFHGC0_MM, + MIPS_INS_MFHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_Mfhi16, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_MFHI, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_MFHI_MM, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_MFHI_DSP_MM, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mfhi */ + Mips_MFHI_DSP, + MIPS_INS_MFHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mfhi16 */ + Mips_MFHI16_MM, + MIPS_INS_MFHI16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_Mflo16, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_MFLO, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_MFLO_MM, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_MFLO_DSP_MM, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mflo */ + Mips_MFLO_DSP, + MIPS_INS_MFLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mflo16 */ + Mips_MFLO16_MM, + MIPS_INS_MFLO16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mftacx */ + Mips_MFTACX, + MIPS_INS_MFTACX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mftacx */ + Mips_MFTACX, + MIPS_INS_MFTACX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftc0 */ + Mips_MFTC0, + MIPS_INS_MFTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mftc0 */ + Mips_MFTC0, + MIPS_INS_MFTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftc1 */ + Mips_MFTC1, + MIPS_INS_MFTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftdsp */ + Mips_MFTDSP, + MIPS_INS_MFTDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftgpr */ + Mips_MFTGPR, + MIPS_INS_MFTGPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mfthc1 */ + Mips_MFTHC1, + MIPS_INS_MFTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mfthi */ + Mips_MFTHI, + MIPS_INS_MFTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mfthi */ + Mips_MFTHI, + MIPS_INS_MFTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftlo */ + Mips_MFTLO, + MIPS_INS_MFTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mftlo */ + Mips_MFTLO, + MIPS_INS_MFTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mftr */ + Mips_MFTR, + MIPS_INS_MFTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* min.d */ + Mips_MIN_D, + MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* min.d */ + Mips_MIN_D_MMR6, + MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* min.s */ + Mips_MIN_S, + MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* min.s */ + Mips_MIN_S_MMR6, + MIPS_INS_MIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* min_a.b */ + Mips_MIN_A_B, + MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_a.d */ + Mips_MIN_A_D, + MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_a.h */ + Mips_MIN_A_H, + MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_a.w */ + Mips_MIN_A_W, + MIPS_INS_MIN_A, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_s.b */ + Mips_MIN_S_B, + MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_s.d */ + Mips_MIN_S_D, + MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_s.h */ + Mips_MIN_S_H, + MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_s.w */ + Mips_MIN_S_W, + MIPS_INS_MIN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_u.b */ + Mips_MIN_U_B, + MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_u.d */ + Mips_MIN_U_D, + MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_u.h */ + Mips_MIN_U_H, + MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* min_u.w */ + Mips_MIN_U_W, + MIPS_INS_MIN_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mina.d */ + Mips_MINA_D, + MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mina.d */ + Mips_MINA_D_MMR6, + MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mina.s */ + Mips_MINA_S, + MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mina.s */ + Mips_MINA_S_MMR6, + MIPS_INS_MINA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mini_s.b */ + Mips_MINI_S_B, + MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_s.d */ + Mips_MINI_S_D, + MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_s.h */ + Mips_MINI_S_H, + MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_s.w */ + Mips_MINI_S_W, + MIPS_INS_MINI_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_u.b */ + Mips_MINI_U_B, + MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_u.d */ + Mips_MINI_U_D, + MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_u.h */ + Mips_MINI_U_H, + MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mini_u.w */ + Mips_MINI_U_W, + MIPS_INS_MINI_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod */ + Mips_MOD, + MIPS_INS_MOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mod */ + Mips_MOD_MMR6, + MIPS_INS_MOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mod_s.b */ + Mips_MOD_S_B, + MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_s.d */ + Mips_MOD_S_D, + MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_s.h */ + Mips_MOD_S_H, + MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_s.w */ + Mips_MOD_S_W, + MIPS_INS_MOD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_u.b */ + Mips_MOD_U_B, + MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_u.d */ + Mips_MOD_U_D, + MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_u.h */ + Mips_MOD_U_H, + MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mod_u.w */ + Mips_MOD_U_W, + MIPS_INS_MOD_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* modsub */ + Mips_MODSUB_MM, + MIPS_INS_MODSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* modsub */ + Mips_MODSUB, + MIPS_INS_MODSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* modu */ + Mips_MODU, + MIPS_INS_MODU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* modu */ + Mips_MODU_MMR6, + MIPS_INS_MODU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D32, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D32_MM, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D64, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D64_MM, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mov.d */ + Mips_FMOV_D_MMR6, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mov.s */ + Mips_FMOV_S, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mov.s */ + Mips_FMOV_S_MMR6, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mov.s */ + Mips_FMOV_S_MM, + MIPS_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_MoveR3216, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_Move32R16, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_OR, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_ADDu, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_MOVE16_MM, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_OR64, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* move */ + Mips_DADDu, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* move.v */ + Mips_MOVE_V, + MIPS_INS_MOVE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* move16 */ + Mips_MOVE16_MMR6, + MIPS_INS_MOVE16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movep */ + Mips_MOVEP_MM, + MIPS_INS_MOVEP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movep */ + Mips_MOVEP_MMR6, + MIPS_INS_MOVEP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movf */ + Mips_MOVF_I, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movf */ + Mips_MOVF_I_MM, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movf.d */ + Mips_MOVF_D32, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movf.d */ + Mips_MOVF_D32_MM, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movf.d */ + Mips_MOVF_D64, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movf.s */ + Mips_MOVF_S, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movf.s */ + Mips_MOVF_S_MM, + MIPS_INS_MOVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movn */ + Mips_MOVN_I_I, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movn */ + Mips_MOVN_I_MM, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movn.d */ + Mips_MOVN_I_D32, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movn.d */ + Mips_MOVN_I_D32_MM, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movn.d */ + Mips_MOVN_I_D64, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movn.s */ + Mips_MOVN_I_S, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movn.s */ + Mips_MOVN_I_S_MM, + MIPS_INS_MOVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movt */ + Mips_MOVT_I, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movt */ + Mips_MOVT_I_MM, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movt.d */ + Mips_MOVT_D32, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movt.d */ + Mips_MOVT_D32_MM, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movt.d */ + Mips_MOVT_D64, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movt.s */ + Mips_MOVT_S, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movt.s */ + Mips_MOVT_S_MM, + MIPS_INS_MOVT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movz */ + Mips_MOVZ_I_I, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movz */ + Mips_MOVZ_I_MM, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* movz.d */ + Mips_MOVZ_I_D32, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movz.d */ + Mips_MOVZ_I_D32_MM, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* movz.d */ + Mips_MOVZ_I_D64, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movz.s */ + Mips_MOVZ_I_S, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* movz.s */ + Mips_MOVZ_I_S_MM, + MIPS_INS_MOVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* msub */ + Mips_MSUB, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* msub */ + Mips_MSUB_MM, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* msub */ + Mips_MSUB_DSP_MM, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* msub */ + Mips_MSUB_DSP, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* msub.d */ + Mips_MSUB_D32, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub.d */ + Mips_MSUB_D32_MM, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub.d */ + Mips_MSUB_D64, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub.s */ + Mips_MSUB_S, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub.s */ + Mips_MSUB_S_MM, + MIPS_INS_MSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* msub_q.h */ + Mips_MSUB_Q_H, + MIPS_INS_MSUB_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msub_q.w */ + Mips_MSUB_Q_W, + MIPS_INS_MSUB_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubf.d */ + Mips_MSUBF_D, + MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* msubf.d */ + Mips_MSUBF_D_MMR6, + MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* msubf.s */ + Mips_MSUBF_S, + MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* msubf.s */ + Mips_MSUBF_S_MMR6, + MIPS_INS_MSUBF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* msubr_q.h */ + Mips_MSUBR_Q_H, + MIPS_INS_MSUBR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubr_q.w */ + Mips_MSUBR_Q_W, + MIPS_INS_MSUBR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubu */ + Mips_MSUBU, + MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* msubu */ + Mips_MSUBU_MM, + MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* msubu */ + Mips_MSUBU_DSP_MM, + MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* msubu */ + Mips_MSUBU_DSP, + MIPS_INS_MSUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* msubv.b */ + Mips_MSUBV_B, + MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubv.d */ + Mips_MSUBV_D, + MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubv.h */ + Mips_MSUBV_H, + MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* msubv.w */ + Mips_MSUBV_W, + MIPS_INS_MSUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mtc0 */ + Mips_MTC0, + MIPS_INS_MTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc0 */ + Mips_MTC0_MMR6, + MIPS_INS_MTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mtc0 */ + Mips_MTC0, + MIPS_INS_MTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc0 */ + Mips_MTC0_MMR6, + MIPS_INS_MTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1_MMR6, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1_MM, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1_D64, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc1 */ + Mips_MTC1_D64_MM, + MIPS_INS_MTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mtc2 */ + Mips_MTC2_MMR6, + MIPS_INS_MTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mtc2 */ + Mips_MTC2, + MIPS_INS_MTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtc2 */ + Mips_MTC2, + MIPS_INS_MTC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtgc0 */ + Mips_MTGC0, + MIPS_INS_MTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtgc0 */ + Mips_MTGC0_MM, + MIPS_INS_MTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mtgc0 */ + Mips_MTGC0, + MIPS_INS_MTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtgc0 */ + Mips_MTGC0_MM, + MIPS_INS_MTGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mthc0 */ + Mips_MTHC0_MMR6, + MIPS_INS_MTHC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mthc0 */ + Mips_MTHC0_MMR6, + MIPS_INS_MTHC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mthc1 */ + Mips_MTHC1_D32, + MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthc1 */ + Mips_MTHC1_D32_MM, + MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mthc1 */ + Mips_MTHC1_D64, + MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthc1 */ + Mips_MTHC1_D64_MM, + MIPS_INS_MTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mthc2 */ + Mips_MTHC2_MMR6, + MIPS_INS_MTHC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mthgc0 */ + Mips_MTHGC0, + MIPS_INS_MTHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthgc0 */ + Mips_MTHGC0_MM, + MIPS_INS_MTHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mthgc0 */ + Mips_MTHGC0, + MIPS_INS_MTHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthgc0 */ + Mips_MTHGC0_MM, + MIPS_INS_MTHGC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* mthi */ + Mips_MTHI, + MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mthi */ + Mips_MTHI_MM, + MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mthi */ + Mips_MTHI_DSP_MM, + MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mthi */ + Mips_MTHI_DSP, + MIPS_INS_MTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mthlip */ + Mips_MTHLIP_MM, + MIPS_INS_MTHLIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mthlip */ + Mips_MTHLIP, + MIPS_INS_MTHLIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mtlo */ + Mips_MTLO, + MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtlo */ + Mips_MTLO_MM, + MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mtlo */ + Mips_MTLO_DSP_MM, + MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mtlo */ + Mips_MTLO_DSP, + MIPS_INS_MTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mtm0 */ + Mips_MTM0, + MIPS_INS_MTM0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtm1 */ + Mips_MTM1, + MIPS_INS_MTM1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtm2 */ + Mips_MTM2, + MIPS_INS_MTM2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtp0 */ + Mips_MTP0, + MIPS_INS_MTP0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtp1 */ + Mips_MTP1, + MIPS_INS_MTP1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtp2 */ + Mips_MTP2, + MIPS_INS_MTP2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* mttacx */ + Mips_MTTACX, + MIPS_INS_MTTACX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mttacx */ + Mips_MTTACX, + MIPS_INS_MTTACX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttc0 */ + Mips_MTTC0, + MIPS_INS_MTTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mttc0 */ + Mips_MTTC0, + MIPS_INS_MTTC0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttc1 */ + Mips_MTTC1, + MIPS_INS_MTTC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttdsp */ + Mips_MTTDSP, + MIPS_INS_MTTDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttgpr */ + Mips_MTTGPR, + MIPS_INS_MTTGPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mtthc1 */ + Mips_MTTHC1, + MIPS_INS_MTTHC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mtthi */ + Mips_MTTHI, + MIPS_INS_MTTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mtthi */ + Mips_MTTHI, + MIPS_INS_MTTHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttlo */ + Mips_MTTLO, + MIPS_INS_MTTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mttlo */ + Mips_MTTLO, + MIPS_INS_MTTLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, 0}, + 0, + 0 +#endif + }, + {/* mttr */ + Mips_MTTR, + MIPS_INS_MTTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* muh */ + Mips_MUH_MMR6, + MIPS_INS_MUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* muh */ + Mips_MUH, + MIPS_INS_MUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* muh */ + Mips_MUH_MMR6, + MIPS_INS_MUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* muhu */ + Mips_MUHU_MMR6, + MIPS_INS_MUHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* muhu */ + Mips_MUHU, + MIPS_INS_MUHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* muhu */ + Mips_MUHU_MMR6, + MIPS_INS_MUHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_MMR6, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_R6, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MUL_MMR6, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mul */ + Mips_MULImmMacro, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mul.d */ + Mips_FMUL_D32, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul.d */ + Mips_FMUL_D32_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mul.d */ + Mips_FMUL_D64, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul.d */ + Mips_FMUL_D64_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mul.ph */ + Mips_MUL_PH_MMR2, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mul.ph */ + Mips_MUL_PH, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mul.ps */ + Mips_FMUL_PS64, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul.s */ + Mips_FMUL_S, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mul.s */ + Mips_FMUL_S_MMR6, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mul.s */ + Mips_FMUL_S_MM, + MIPS_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* mul_q.h */ + Mips_MUL_Q_H, + MIPS_INS_MUL_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mul_q.w */ + Mips_MUL_Q_W, + MIPS_INS_MUL_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mul_s.ph */ + Mips_MUL_S_PH_MMR2, + MIPS_INS_MUL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mul_s.ph */ + Mips_MUL_S_PH, + MIPS_INS_MUL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* muleq_s.w.phl */ + Mips_MULEQ_S_W_PHL_MM, + MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleq_s.w.phl */ + Mips_MULEQ_S_W_PHL, + MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleq_s.w.phr */ + Mips_MULEQ_S_W_PHR_MM, + MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleq_s.w.phr */ + Mips_MULEQ_S_W_PHR, + MIPS_INS_MULEQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleu_s.ph.qbl */ + Mips_MULEU_S_PH_QBL_MM, + MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleu_s.ph.qbl */ + Mips_MULEU_S_PH_QBL, + MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleu_s.ph.qbr */ + Mips_MULEU_S_PH_QBR_MM, + MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* muleu_s.ph.qbr */ + Mips_MULEU_S_PH_QBR, + MIPS_INS_MULEU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulo */ + Mips_MULOMacro, + MIPS_INS_MULO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mulo */ + Mips_MULOMacro, + MIPS_INS_MULO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mulou */ + Mips_MULOUMacro, + MIPS_INS_MULOU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mulou */ + Mips_MULOUMacro, + MIPS_INS_MULOU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* mulq_rs.ph */ + Mips_MULQ_RS_PH_MM, + MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulq_rs.ph */ + Mips_MULQ_RS_PH, + MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulq_rs.w */ + Mips_MULQ_RS_W_MMR2, + MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_rs.w */ + Mips_MULQ_RS_W, + MIPS_INS_MULQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_s.ph */ + Mips_MULQ_S_PH_MMR2, + MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_s.ph */ + Mips_MULQ_S_PH, + MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_s.w */ + Mips_MULQ_S_W_MMR2, + MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulq_s.w */ + Mips_MULQ_S_W, + MIPS_INS_MULQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulr.ps */ + Mips_MULR_PS64, + MIPS_INS_MULR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MIPS3D, 0}, + 0, + 0 +#endif + }, + {/* mulr_q.h */ + Mips_MULR_Q_H, + MIPS_INS_MULR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulr_q.w */ + Mips_MULR_Q_W, + MIPS_INS_MULR_Q, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulsa.w.ph */ + Mips_MULSA_W_PH_MMR2, + MIPS_INS_MULSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulsa.w.ph */ + Mips_MULSA_W_PH, + MIPS_INS_MULSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* mulsaq_s.w.ph */ + Mips_MULSAQ_S_W_PH_MM, + MIPS_INS_MULSAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulsaq_s.w.ph */ + Mips_MULSAQ_S_W_PH, + MIPS_INS_MULSAQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mult */ + Mips_MULT, + MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mult */ + Mips_MULT_MM, + MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mult */ + Mips_MULT_DSP_MM, + MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mult */ + Mips_MULT_DSP, + MIPS_INS_MULT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* multu */ + Mips_MULTu, + MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* multu */ + Mips_MULTu_MM, + MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* multu */ + Mips_MULTU_DSP_MM, + MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* multu */ + Mips_MULTU_DSP, + MIPS_INS_MULTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* mulu */ + Mips_MULU_MMR6, + MIPS_INS_MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mulu */ + Mips_MULU, + MIPS_INS_MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* mulu */ + Mips_MULU_MMR6, + MIPS_INS_MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* mulv.b */ + Mips_MULV_B, + MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulv.d */ + Mips_MULV_D, + MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulv.h */ + Mips_MULV_H, + MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* mulv.w */ + Mips_MULV_W, + MIPS_INS_MULV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB_MMR6, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_NegRxRy16, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* neg */ + Mips_SUB_MMR6, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* neg.d */ + Mips_FNEG_D32, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* neg.d */ + Mips_FNEG_D32_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* neg.d */ + Mips_FNEG_D64, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* neg.d */ + Mips_FNEG_D64_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* neg.s */ + Mips_FNEG_S_MMR6, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* neg.s */ + Mips_FNEG_S, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* neg.s */ + Mips_FNEG_S_MM, + MIPS_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBu, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBu_MM, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBU_MMR6, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBu, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBu_MM, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* negu */ + Mips_SUBU_MMR6, + MIPS_INS_NEGU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* nloc.b */ + Mips_NLOC_B, + MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nloc.d */ + Mips_NLOC_D, + MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nloc.h */ + Mips_NLOC_H, + MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nloc.w */ + Mips_NLOC_W, + MIPS_INS_NLOC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nlzc.b */ + Mips_NLZC_B, + MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nlzc.d */ + Mips_NLZC_D, + MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nlzc.h */ + Mips_NLZC_H, + MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nlzc.w */ + Mips_NLZC_W, + MIPS_INS_NLZC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nmadd.d */ + Mips_NMADD_D32, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmadd.d */ + Mips_NMADD_D32_MM, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* nmadd.d */ + Mips_NMADD_D64, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmadd.s */ + Mips_NMADD_S, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmadd.s */ + Mips_NMADD_S_MM, + MIPS_INS_NMADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* nmsub.d */ + Mips_NMSUB_D32, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmsub.d */ + Mips_NMSUB_D32_MM, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* nmsub.d */ + Mips_NMSUB_D64, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmsub.s */ + Mips_NMSUB_S, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_MADD4, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nmsub.s */ + Mips_NMSUB_S_MM, + MIPS_INS_NMSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_MADD4, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_SLL, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_SLL_MMR6, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_Move32R16, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_SLL_MM, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nop */ + Mips_MOVE16_MM, + MIPS_INS_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NORImm, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NORImm64, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NOR, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NOR_MM, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NOR_MMR6, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NORImm, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, 0}, + 0, + 0 +#endif + }, + {/* nor */ + Mips_NORImm64, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* nor.v */ + Mips_NOR_V, + MIPS_INS_NOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* nori.b */ + Mips_NORI_B, + MIPS_INS_NORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR_MM, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR_MMR6, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NotRxRy16, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR_MM, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not */ + Mips_NOR_MMR6, + MIPS_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not16 */ + Mips_NOT16_MM, + MIPS_INS_NOT16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* not16 */ + Mips_NOT16_MMR6, + MIPS_INS_NOT16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OrRxRxRy16, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR_MM, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR_MMR6, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORI_MMR6, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi_MM, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi64, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR_MM, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_OR_MMR6, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORI_MMR6, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi_MM, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or */ + Mips_ORi64, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* or.v */ + Mips_OR_V, + MIPS_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* or16 */ + Mips_OR16_MM, + MIPS_INS_OR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* or16 */ + Mips_OR16_MMR6, + MIPS_INS_OR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORI_MMR6, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORi, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORi_MM, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORI_MMR6, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORi, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ori */ + Mips_ORi_MM, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ori.b */ + Mips_ORI_B, + MIPS_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* packrl.ph */ + Mips_PACKRL_PH_MM, + MIPS_INS_PACKRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* packrl.ph */ + Mips_PACKRL_PH, + MIPS_INS_PACKRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pause */ + Mips_PAUSE, + MIPS_INS_PAUSE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pause */ + Mips_PAUSE_MMR6, + MIPS_INS_PAUSE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* pause */ + Mips_PAUSE_MM, + MIPS_INS_PAUSE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pckev.b */ + Mips_PCKEV_B, + MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckev.d */ + Mips_PCKEV_D, + MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckev.h */ + Mips_PCKEV_H, + MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckev.w */ + Mips_PCKEV_W, + MIPS_INS_PCKEV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckod.b */ + Mips_PCKOD_B, + MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckod.d */ + Mips_PCKOD_D, + MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckod.h */ + Mips_PCKOD_H, + MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pckod.w */ + Mips_PCKOD_W, + MIPS_INS_PCKOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pcnt.b */ + Mips_PCNT_B, + MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pcnt.d */ + Mips_PCNT_D, + MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pcnt.h */ + Mips_PCNT_H, + MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pcnt.w */ + Mips_PCNT_W, + MIPS_INS_PCNT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* pick.ph */ + Mips_PICK_PH_MM, + MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pick.ph */ + Mips_PICK_PH, + MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pick.qb */ + Mips_PICK_QB_MM, + MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pick.qb */ + Mips_PICK_QB, + MIPS_INS_PICK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pll.ps */ + Mips_PLL_PS64, + MIPS_INS_PLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* plu.ps */ + Mips_PLU_PS64, + MIPS_INS_PLU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pop */ + Mips_POP, + MIPS_INS_POP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* pop */ + Mips_POP, + MIPS_INS_POP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* preceq.w.phl */ + Mips_PRECEQ_W_PHL_MM, + MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceq.w.phl */ + Mips_PRECEQ_W_PHL, + MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceq.w.phr */ + Mips_PRECEQ_W_PHR_MM, + MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceq.w.phr */ + Mips_PRECEQ_W_PHR, + MIPS_INS_PRECEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbl */ + Mips_PRECEQU_PH_QBL_MM, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbl */ + Mips_PRECEQU_PH_QBL, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbla */ + Mips_PRECEQU_PH_QBLA_MM, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbla */ + Mips_PRECEQU_PH_QBLA, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbr */ + Mips_PRECEQU_PH_QBR_MM, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbr */ + Mips_PRECEQU_PH_QBR, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbra */ + Mips_PRECEQU_PH_QBRA_MM, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precequ.ph.qbra */ + Mips_PRECEQU_PH_QBRA, + MIPS_INS_PRECEQU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbl */ + Mips_PRECEU_PH_QBL_MM, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbl */ + Mips_PRECEU_PH_QBL, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbla */ + Mips_PRECEU_PH_QBLA_MM, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbla */ + Mips_PRECEU_PH_QBLA, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbr */ + Mips_PRECEU_PH_QBR_MM, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbr */ + Mips_PRECEU_PH_QBR, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbra */ + Mips_PRECEU_PH_QBRA_MM, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* preceu.ph.qbra */ + Mips_PRECEU_PH_QBRA, + MIPS_INS_PRECEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precr.qb.ph */ + Mips_PRECR_QB_PH_MMR2, + MIPS_INS_PRECR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr.qb.ph */ + Mips_PRECR_QB_PH, + MIPS_INS_PRECR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr_sra.ph.w */ + Mips_PRECR_SRA_PH_W_MMR2, + MIPS_INS_PRECR_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr_sra.ph.w */ + Mips_PRECR_SRA_PH_W, + MIPS_INS_PRECR_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr_sra_r.ph.w */ + Mips_PRECR_SRA_R_PH_W_MMR2, + MIPS_INS_PRECR_SRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precr_sra_r.ph.w */ + Mips_PRECR_SRA_R_PH_W, + MIPS_INS_PRECR_SRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* precrq.ph.w */ + Mips_PRECRQ_PH_W_MM, + MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq.ph.w */ + Mips_PRECRQ_PH_W, + MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq.qb.ph */ + Mips_PRECRQ_QB_PH_MM, + MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq.qb.ph */ + Mips_PRECRQ_QB_PH, + MIPS_INS_PRECRQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq_rs.ph.w */ + Mips_PRECRQ_RS_PH_W_MM, + MIPS_INS_PRECRQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrq_rs.ph.w */ + Mips_PRECRQ_RS_PH_W, + MIPS_INS_PRECRQ_RS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrqu_s.qb.ph */ + Mips_PRECRQU_S_QB_PH_MM, + MIPS_INS_PRECRQU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* precrqu_s.qb.ph */ + Mips_PRECRQU_S_QB_PH, + MIPS_INS_PRECRQU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* pref */ + Mips_PREF_R6, + MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pref */ + Mips_PREF, + MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* pref */ + Mips_PREF_MM, + MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* pref */ + Mips_PREF_MMR6, + MIPS_INS_PREF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* prefe */ + Mips_PREFE, + MIPS_INS_PREFE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* prefe */ + Mips_PREFE_MM, + MIPS_INS_PREFE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* prefx */ + Mips_PREFX_MM, + MIPS_INS_PREFX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* prepend */ + Mips_PREPEND_MMR2, + MIPS_INS_PREPEND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* prepend */ + Mips_PREPEND, + MIPS_INS_PREPEND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* pul.ps */ + Mips_PUL_PS64, + MIPS_INS_PUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* puu.ps */ + Mips_PUU_PS64, + MIPS_INS_PUU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* raddu.w.qb */ + Mips_RADDU_W_QB_MM, + MIPS_INS_RADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* raddu.w.qb */ + Mips_RADDU_W_QB, + MIPS_INS_RADDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* rddsp */ + Mips_RDDSP_MM, + MIPS_INS_RDDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* rddsp */ + Mips_RDDSP, + MIPS_INS_RDDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR_MM, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR_MMR6, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR64, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR_MMR6, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rdhwr */ + Mips_RDHWR_MM, + MIPS_INS_RDHWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rdpgpr */ + Mips_RDPGPR_MMR6, + MIPS_INS_RDPGPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* recip.d */ + Mips_RECIP_D32, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* recip.d */ + Mips_RECIP_D32_MM, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* recip.d */ + Mips_RECIP_D64, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* recip.d */ + Mips_RECIP_D64_MM, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* recip.s */ + Mips_RECIP_S, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* recip.s */ + Mips_RECIP_S_MM, + MIPS_INS_RECIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* rem */ + Mips_SRemMacro, + MIPS_INS_REM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* rem */ + Mips_SRemIMacro, + MIPS_INS_REM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* rem */ + Mips_SRemMacro, + MIPS_INS_REM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* rem */ + Mips_SRemIMacro, + MIPS_INS_REM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* remu */ + Mips_URemMacro, + MIPS_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* remu */ + Mips_URemIMacro, + MIPS_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* remu */ + Mips_URemMacro, + MIPS_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* remu */ + Mips_URemIMacro, + MIPS_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* repl.ph */ + Mips_REPL_PH_MM, + MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* repl.ph */ + Mips_REPL_PH, + MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* repl.qb */ + Mips_REPL_QB_MM, + MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* repl.qb */ + Mips_REPL_QB, + MIPS_INS_REPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* replv.ph */ + Mips_REPLV_PH_MM, + MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* replv.ph */ + Mips_REPLV_PH, + MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* replv.qb */ + Mips_REPLV_QB_MM, + MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* replv.qb */ + Mips_REPLV_QB, + MIPS_INS_REPLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* rint.d */ + Mips_RINT_D, + MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rint.d */ + Mips_RINT_D_MMR6, + MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rint.s */ + Mips_RINT_S, + MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rint.s */ + Mips_RINT_S_MMR6, + MIPS_INS_RINT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* rol */ + Mips_ROL, + MIPS_INS_ROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* rol */ + Mips_ROLImm, + MIPS_INS_ROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* rol */ + Mips_ROL, + MIPS_INS_ROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* rol */ + Mips_ROLImm, + MIPS_INS_ROL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ror */ + Mips_ROR, + MIPS_INS_ROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ror */ + Mips_RORImm, + MIPS_INS_ROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ror */ + Mips_ROR, + MIPS_INS_ROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ror */ + Mips_RORImm, + MIPS_INS_ROR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR_MM, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR_MM, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotr */ + Mips_ROTR_MM, + MIPS_INS_ROTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotrv */ + Mips_ROTRV, + MIPS_INS_ROTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rotrv */ + Mips_ROTRV_MM, + MIPS_INS_ROTRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.l.d */ + Mips_ROUND_L_D64, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.l.d */ + Mips_ROUND_L_D_MMR6, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.l.s */ + Mips_ROUND_L_S, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.l.s */ + Mips_ROUND_L_S_MMR6, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.w.d */ + Mips_ROUND_W_D32, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.w.d */ + Mips_ROUND_W_MM, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.w.d */ + Mips_ROUND_W_D64, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.w.d */ + Mips_ROUND_W_D_MMR6, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.w.s */ + Mips_ROUND_W_S, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* round.w.s */ + Mips_ROUND_W_S_MMR6, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* round.w.s */ + Mips_ROUND_W_S_MM, + MIPS_INS_ROUND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.d */ + Mips_RSQRT_D32, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.d */ + Mips_RSQRT_D32_MM, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.d */ + Mips_RSQRT_D64, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.d */ + Mips_RSQRT_D64_MM, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.s */ + Mips_RSQRT_S, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* rsqrt.s */ + Mips_RSQRT_S_MM, + MIPS_INS_RSQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* s.d */ + Mips_SDC1, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* s.d */ + Mips_SDC1_M1, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* s.d */ + Mips_SDC1_M1, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* s.d */ + Mips_SDC164, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + 0}, + 0, + 0 +#endif + }, + {/* s.s */ + Mips_SWC1, + MIPS_INS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* saa */ + Mips_SaaAddr, + MIPS_INS_SAA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPSP, 0}, + 0, + 0 +#endif + }, + {/* saa */ + Mips_SAA, + MIPS_INS_SAA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPSP, 0}, + 0, + 0 +#endif + }, + {/* saad */ + Mips_SaadAddr, + MIPS_INS_SAAD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPSP, 0}, + 0, + 0 +#endif + }, + {/* saad */ + Mips_SAAD, + MIPS_INS_SAAD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPSP, 0}, + 0, + 0 +#endif + }, + {/* sat_s.b */ + Mips_SAT_S_B, + MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_s.d */ + Mips_SAT_S_D, + MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_s.h */ + Mips_SAT_S_H, + MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_s.w */ + Mips_SAT_S_W, + MIPS_INS_SAT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_u.b */ + Mips_SAT_U_B, + MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_u.d */ + Mips_SAT_U_D, + MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_u.h */ + Mips_SAT_U_H, + MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sat_u.w */ + Mips_SAT_U_W, + MIPS_INS_SAT_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sb */ + Mips_SB, + MIPS_INS_SB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sb */ + Mips_SB_MMR6, + MIPS_INS_SB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sb */ + Mips_SB_MM, + MIPS_INS_SB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sb */ + Mips_SbRxRyOffMemX16, + MIPS_INS_SB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sb16 */ + Mips_SB16_MM, + MIPS_INS_SB16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sb16 */ + Mips_SB16_MMR6, + MIPS_INS_SB16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sbe */ + Mips_SBE, + MIPS_INS_SBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* sbe */ + Mips_SBE_MM, + MIPS_INS_SBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC64_R6, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR64BIT, MIPS_GRP_MIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC_R6, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC_MMR6, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR32BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC64, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_PTR64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sc */ + Mips_SC_MM, + MIPS_INS_SC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* scd */ + Mips_SCD_R6, + MIPS_INS_SCD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* scd */ + Mips_SCD, + MIPS_INS_SCD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sce */ + Mips_SCE, + MIPS_INS_SCE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* sce */ + Mips_SCE_MM, + MIPS_INS_SCE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* sd */ + Mips_SDMacro, + MIPS_INS_SD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS3, 0}, + 0, + 0 +#endif + }, + {/* sd */ + Mips_SD, + MIPS_INS_SD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_R6, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_MMR6, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_MM, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_R6, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdbbp */ + Mips_SDBBP_MMR6, + MIPS_INS_SDBBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdbbp16 */ + Mips_SDBBP16_MM, + MIPS_INS_SDBBP16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdbbp16 */ + Mips_SDBBP16_MMR6, + MIPS_INS_SDBBP16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdc1 */ + Mips_SDC1, + MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdc1 */ + Mips_SDC1_MM, + MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sdc1 */ + Mips_SDC164, + MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdc1 */ + Mips_SDC1_D64_MMR6, + MIPS_INS_SDC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sdc2 */ + Mips_SDC2_R6, + MIPS_INS_SDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdc2 */ + Mips_SDC2_MMR6, + MIPS_INS_SDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sdc2 */ + Mips_SDC2, + MIPS_INS_SDC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdc3 */ + Mips_SDC3, + MIPS_INS_SDC3, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTCNMIPS, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdl */ + Mips_SDL, + MIPS_INS_SDL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sdr */ + Mips_SDR, + MIPS_INS_SDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sdxc1 */ + Mips_SDXC1, + MIPS_INS_SDXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sdxc1 */ + Mips_SDXC164, + MIPS_INS_SDXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SebRx16, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SEB, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SEB_MM, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SEB, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seb */ + Mips_SEB_MM, + MIPS_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SehRx16, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SEH, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SEH_MM, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SEH, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seh */ + Mips_SEH_MM, + MIPS_INS_SEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sel.d */ + Mips_SEL_D, + MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sel.d */ + Mips_SEL_D_MMR6, + MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sel.s */ + Mips_SEL_S, + MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sel.s */ + Mips_SEL_S_MMR6, + MIPS_INS_SEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seleqz */ + Mips_SELEQZ, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seleqz */ + Mips_SELEQZ_MMR6, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seleqz */ + Mips_SELEQZ64, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seleqz.d */ + Mips_SELEQZ_D, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seleqz.d */ + Mips_SELEQZ_D_MMR6, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seleqz.s */ + Mips_SELEQZ_S, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* seleqz.s */ + Mips_SELEQZ_S_MMR6, + MIPS_INS_SELEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* selnez */ + Mips_SELNEZ, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* selnez */ + Mips_SELNEZ_MMR6, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* selnez */ + Mips_SELNEZ64, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* selnez.d */ + Mips_SELNEZ_D, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* selnez.d */ + Mips_SELNEZ_D_MMR6, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* selnez.s */ + Mips_SELNEZ_S, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* selnez.s */ + Mips_SELNEZ_S_MMR6, + MIPS_INS_SELNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQMacro, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQIMacro, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQ, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQMacro, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQIMacro, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seq */ + Mips_SEQ, + MIPS_INS_SEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seqi */ + Mips_SEQi, + MIPS_INS_SEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* seqi */ + Mips_SEQi, + MIPS_INS_SEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGE, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGEImm, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGEImm64, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGE, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGEImm, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sge */ + Mips_SGEImm64, + MIPS_INS_SGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEU, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEUImm, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEUImm64, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEU, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEUImm, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgeu */ + Mips_SGEUImm64, + MIPS_INS_SGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SLT, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SLT_MM, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SGTImm, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SGTImm64, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SLT, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SLT_MM, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SGTImm, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgt */ + Mips_SGTImm64, + MIPS_INS_SGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SLTu, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SLTu_MM, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SGTUImm, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SGTUImm64, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SLTu, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SLTu_MM, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SGTUImm, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sgtu */ + Mips_SGTUImm64, + MIPS_INS_SGTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sh */ + Mips_SH, + MIPS_INS_SH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sh */ + Mips_SH_MMR6, + MIPS_INS_SH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sh */ + Mips_SH_MM, + MIPS_INS_SH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sh */ + Mips_ShRxRyOffMemX16, + MIPS_INS_SH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sh16 */ + Mips_SH16_MM, + MIPS_INS_SH16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sh16 */ + Mips_SH16_MMR6, + MIPS_INS_SH16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* she */ + Mips_SHE, + MIPS_INS_SHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* she */ + Mips_SHE_MM, + MIPS_INS_SHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* shf.b */ + Mips_SHF_B, + MIPS_INS_SHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* shf.h */ + Mips_SHF_H, + MIPS_INS_SHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* shf.w */ + Mips_SHF_W, + MIPS_INS_SHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* shilo */ + Mips_SHILO_MM, + MIPS_INS_SHILO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shilo */ + Mips_SHILO, + MIPS_INS_SHILO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shilov */ + Mips_SHILOV_MM, + MIPS_INS_SHILOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shilov */ + Mips_SHILOV, + MIPS_INS_SHILOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll.ph */ + Mips_SHLL_PH_MM, + MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll.ph */ + Mips_SHLL_PH, + MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll.qb */ + Mips_SHLL_QB_MM, + MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll.qb */ + Mips_SHLL_QB, + MIPS_INS_SHLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll_s.ph */ + Mips_SHLL_S_PH_MM, + MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll_s.ph */ + Mips_SHLL_S_PH, + MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll_s.w */ + Mips_SHLL_S_W_MM, + MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shll_s.w */ + Mips_SHLL_S_W, + MIPS_INS_SHLL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv.ph */ + Mips_SHLLV_PH_MM, + MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv.ph */ + Mips_SHLLV_PH, + MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv.qb */ + Mips_SHLLV_QB_MM, + MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv.qb */ + Mips_SHLLV_QB, + MIPS_INS_SHLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv_s.ph */ + Mips_SHLLV_S_PH_MM, + MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv_s.ph */ + Mips_SHLLV_S_PH, + MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv_s.w */ + Mips_SHLLV_S_W_MM, + MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shllv_s.w */ + Mips_SHLLV_S_W, + MIPS_INS_SHLLV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra.ph */ + Mips_SHRA_PH_MM, + MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra.ph */ + Mips_SHRA_PH, + MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra.qb */ + Mips_SHRA_QB_MMR2, + MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shra.qb */ + Mips_SHRA_QB, + MIPS_INS_SHRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shra_r.ph */ + Mips_SHRA_R_PH_MM, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra_r.ph */ + Mips_SHRA_R_PH, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra_r.qb */ + Mips_SHRA_R_QB_MMR2, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shra_r.qb */ + Mips_SHRA_R_QB, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shra_r.w */ + Mips_SHRA_R_W_MM, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shra_r.w */ + Mips_SHRA_R_W, + MIPS_INS_SHRA_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav.ph */ + Mips_SHRAV_PH_MM, + MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav.ph */ + Mips_SHRAV_PH, + MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav.qb */ + Mips_SHRAV_QB_MMR2, + MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrav.qb */ + Mips_SHRAV_QB, + MIPS_INS_SHRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.ph */ + Mips_SHRAV_R_PH_MM, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.ph */ + Mips_SHRAV_R_PH, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.qb */ + Mips_SHRAV_R_QB_MMR2, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.qb */ + Mips_SHRAV_R_QB, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.w */ + Mips_SHRAV_R_W_MM, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrav_r.w */ + Mips_SHRAV_R_W, + MIPS_INS_SHRAV_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrl.ph */ + Mips_SHRL_PH_MMR2, + MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrl.ph */ + Mips_SHRL_PH, + MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrl.qb */ + Mips_SHRL_QB_MM, + MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrl.qb */ + Mips_SHRL_QB, + MIPS_INS_SHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrlv.ph */ + Mips_SHRLV_PH_MMR2, + MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrlv.ph */ + Mips_SHRLV_PH, + MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* shrlv.qb */ + Mips_SHRLV_QB_MM, + MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* shrlv.qb */ + Mips_SHRLV_QB, + MIPS_INS_SHRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* sigrie */ + Mips_SIGRIE, + MIPS_INS_SIGRIE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sigrie */ + Mips_SIGRIE_MMR6, + MIPS_INS_SIGRIE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sigrie */ + Mips_SIGRIE, + MIPS_INS_SIGRIE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sigrie */ + Mips_SIGRIE_MMR6, + MIPS_INS_SIGRIE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sld.b */ + Mips_SLD_B, + MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sld.d */ + Mips_SLD_D, + MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sld.h */ + Mips_SLD_H, + MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sld.w */ + Mips_SLD_W, + MIPS_INS_SLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sldi.b */ + Mips_SLDI_B, + MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sldi.d */ + Mips_SLDI_D, + MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sldi.h */ + Mips_SLDI_H, + MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sldi.w */ + Mips_SLDI_W, + MIPS_INS_SLDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLE, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLEImm, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLEImm64, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLE, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLEImm, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sle */ + Mips_SLEImm64, + MIPS_INS_SLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEU, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEUImm, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEUImm64, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEU, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEUImm, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sleu */ + Mips_SLEUImm64, + MIPS_INS_SLEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLLV, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLLV_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MMR6, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SllX16, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLLV, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLLV_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MMR6, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sll */ + Mips_SLL_MM, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sll.b */ + Mips_SLL_B, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sll.d */ + Mips_SLL_D, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sll.h */ + Mips_SLL_H, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sll.w */ + Mips_SLL_W, + MIPS_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sll16 */ + Mips_SLL16_MM, + MIPS_INS_SLL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sll16 */ + Mips_SLL16_MMR6, + MIPS_INS_SLL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* slli.b */ + Mips_SLLI_B, + MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* slli.d */ + Mips_SLLI_D, + MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* slli.h */ + Mips_SLLI_H, + MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* slli.w */ + Mips_SLLI_W, + MIPS_INS_SLLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sllv */ + Mips_SllvRxRy16, + MIPS_INS_SLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sllv */ + Mips_SLLV, + MIPS_INS_SLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sllv */ + Mips_SLLV_MM, + MIPS_INS_SLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SltRxRy16, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTi, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTi_MM, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTImm64, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLT, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLT_MM, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTi, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTi_MM, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slt */ + Mips_SLTImm64, + MIPS_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* slti */ + Mips_SltiRxImmX16, + MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* slti */ + Mips_SLTi, + MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slti */ + Mips_SLTi_MM, + MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* slti */ + Mips_SltiRxImm16, + MIPS_INS_SLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sltiu */ + Mips_SltiuRxImmX16, + MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sltiu */ + Mips_SLTiu, + MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltiu */ + Mips_SLTiu_MM, + MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltiu */ + Mips_SltiuRxImm16, + MIPS_INS_SLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SltuRxRy16, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTiu, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTiu_MM, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTUImm64, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTu, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTu_MM, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTiu, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTiu_MM, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sltu */ + Mips_SLTUImm64, + MIPS_INS_SLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_GP64BIT, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNEMacro, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNEIMacro, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNE, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNEMacro, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNEIMacro, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTCNMIPS, 0}, + 0, + 0 +#endif + }, + {/* sne */ + Mips_SNE, + MIPS_INS_SNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* snei */ + Mips_SNEi, + MIPS_INS_SNEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* snei */ + Mips_SNEi, + MIPS_INS_SNEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* splat.b */ + Mips_SPLAT_B, + MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splat.d */ + Mips_SPLAT_D, + MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splat.h */ + Mips_SPLAT_H, + MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splat.w */ + Mips_SPLAT_W, + MIPS_INS_SPLAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splati.b */ + Mips_SPLATI_B, + MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splati.d */ + Mips_SPLATI_D, + MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splati.h */ + Mips_SPLATI_H, + MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* splati.w */ + Mips_SPLATI_W, + MIPS_INS_SPLATI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sqrt.d */ + Mips_FSQRT_D32, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sqrt.d */ + Mips_FSQRT_D32_MM, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sqrt.d */ + Mips_FSQRT_D64, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sqrt.d */ + Mips_FSQRT_D64_MM, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sqrt.s */ + Mips_FSQRT_S, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sqrt.s */ + Mips_FSQRT_S_MM, + MIPS_INS_SQRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRAV, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRAV_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SraX16, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRAV, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRAV_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra */ + Mips_SRA_MM, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sra.b */ + Mips_SRA_B, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sra.d */ + Mips_SRA_D, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sra.h */ + Mips_SRA_H, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sra.w */ + Mips_SRA_W, + MIPS_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srai.b */ + Mips_SRAI_B, + MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srai.d */ + Mips_SRAI_D, + MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srai.h */ + Mips_SRAI_H, + MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srai.w */ + Mips_SRAI_W, + MIPS_INS_SRAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srar.b */ + Mips_SRAR_B, + MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srar.d */ + Mips_SRAR_D, + MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srar.h */ + Mips_SRAR_H, + MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srar.w */ + Mips_SRAR_W, + MIPS_INS_SRAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srari.b */ + Mips_SRARI_B, + MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srari.d */ + Mips_SRARI_D, + MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srari.h */ + Mips_SRARI_H, + MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srari.w */ + Mips_SRARI_W, + MIPS_INS_SRARI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srav */ + Mips_SravRxRy16, + MIPS_INS_SRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* srav */ + Mips_SRAV, + MIPS_INS_SRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srav */ + Mips_SRAV_MM, + MIPS_INS_SRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRLV, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRLV_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SrlX16, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRLV, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRLV_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl */ + Mips_SRL_MM, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srl.b */ + Mips_SRL_B, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srl.d */ + Mips_SRL_D, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srl.h */ + Mips_SRL_H, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srl.w */ + Mips_SRL_W, + MIPS_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srl16 */ + Mips_SRL16_MM, + MIPS_INS_SRL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* srl16 */ + Mips_SRL16_MMR6, + MIPS_INS_SRL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* srli.b */ + Mips_SRLI_B, + MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srli.d */ + Mips_SRLI_D, + MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srli.h */ + Mips_SRLI_H, + MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srli.w */ + Mips_SRLI_W, + MIPS_INS_SRLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlr.b */ + Mips_SRLR_B, + MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlr.d */ + Mips_SRLR_D, + MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlr.h */ + Mips_SRLR_H, + MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlr.w */ + Mips_SRLR_W, + MIPS_INS_SRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlri.b */ + Mips_SRLRI_B, + MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlri.d */ + Mips_SRLRI_D, + MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlri.h */ + Mips_SRLRI_H, + MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlri.w */ + Mips_SRLRI_W, + MIPS_INS_SRLRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* srlv */ + Mips_SrlvRxRy16, + MIPS_INS_SRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* srlv */ + Mips_SRLV, + MIPS_INS_SRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* srlv */ + Mips_SRLV_MM, + MIPS_INS_SRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ssnop */ + Mips_SSNOP, + MIPS_INS_SSNOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* ssnop */ + Mips_SSNOP_MMR6, + MIPS_INS_SSNOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* ssnop */ + Mips_SSNOP_MM, + MIPS_INS_SSNOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* st.b */ + Mips_ST_B, + MIPS_INS_ST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* st.d */ + Mips_ST_D, + MIPS_INS_ST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* st.h */ + Mips_ST_H, + MIPS_INS_ST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* st.w */ + Mips_ST_W, + MIPS_INS_ST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB_MMR6, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_ADDi, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_SUB_MMR6, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sub */ + Mips_ADDi, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0}, + 0, + 0 +#endif + }, + {/* sub.d */ + Mips_FSUB_D32, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub.d */ + Mips_FSUB_D32_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sub.d */ + Mips_FSUB_D64, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub.d */ + Mips_FSUB_D64_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sub.ps */ + Mips_FSUB_PS64, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub.s */ + Mips_FSUB_S, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sub.s */ + Mips_FSUB_S_MMR6, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sub.s */ + Mips_FSUB_S_MM, + MIPS_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* subq.ph */ + Mips_SUBQ_PH_MM, + MIPS_INS_SUBQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq.ph */ + Mips_SUBQ_PH, + MIPS_INS_SUBQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq_s.ph */ + Mips_SUBQ_S_PH_MM, + MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq_s.ph */ + Mips_SUBQ_S_PH, + MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq_s.w */ + Mips_SUBQ_S_W_MM, + MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subq_s.w */ + Mips_SUBQ_S_W, + MIPS_INS_SUBQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subqh.ph */ + Mips_SUBQH_PH_MMR2, + MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh.ph */ + Mips_SUBQH_PH, + MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh.w */ + Mips_SUBQH_W_MMR2, + MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh.w */ + Mips_SUBQH_W, + MIPS_INS_SUBQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh_r.ph */ + Mips_SUBQH_R_PH_MMR2, + MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh_r.ph */ + Mips_SUBQH_R_PH, + MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh_r.w */ + Mips_SUBQH_R_W_MMR2, + MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subqh_r.w */ + Mips_SUBQH_R_W, + MIPS_INS_SUBQH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subs_s.b */ + Mips_SUBS_S_B, + MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_s.d */ + Mips_SUBS_S_D, + MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_s.h */ + Mips_SUBS_S_H, + MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_s.w */ + Mips_SUBS_S_W, + MIPS_INS_SUBS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_u.b */ + Mips_SUBS_U_B, + MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_u.d */ + Mips_SUBS_U_D, + MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_u.h */ + Mips_SUBS_U_H, + MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subs_u.w */ + Mips_SUBS_U_W, + MIPS_INS_SUBS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsus_u.b */ + Mips_SUBSUS_U_B, + MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsus_u.d */ + Mips_SUBSUS_U_D, + MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsus_u.h */ + Mips_SUBSUS_U_H, + MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsus_u.w */ + Mips_SUBSUS_U_W, + MIPS_INS_SUBSUS_U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsuu_s.b */ + Mips_SUBSUU_S_B, + MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsuu_s.d */ + Mips_SUBSUU_S_D, + MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsuu_s.h */ + Mips_SUBSUU_S_H, + MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subsuu_s.w */ + Mips_SUBSUU_S_W, + MIPS_INS_SUBSUU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBU_MMR6, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBu, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBu_MM, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_ADDiu, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SubuRxRyRz16, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBU_MMR6, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBu, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_SUBu_MM, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu */ + Mips_ADDiu, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* subu.ph */ + Mips_SUBU_PH_MMR2, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subu.ph */ + Mips_SUBU_PH, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subu.qb */ + Mips_SUBU_QB_MM, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subu.qb */ + Mips_SUBU_QB, + MIPS_INS_SUBU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subu16 */ + Mips_SUBU16_MM, + MIPS_INS_SUBU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu16 */ + Mips_SUBU16_MMR6, + MIPS_INS_SUBU16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* subu_s.ph */ + Mips_SUBU_S_PH_MMR2, + MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subu_s.ph */ + Mips_SUBU_S_PH, + MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subu_s.qb */ + Mips_SUBU_S_QB_MM, + MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subu_s.qb */ + Mips_SUBU_S_QB, + MIPS_INS_SUBU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* subuh.qb */ + Mips_SUBUH_QB_MMR2, + MIPS_INS_SUBUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subuh.qb */ + Mips_SUBUH_QB, + MIPS_INS_SUBUH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subuh_r.qb */ + Mips_SUBUH_R_QB_MMR2, + MIPS_INS_SUBUH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subuh_r.qb */ + Mips_SUBUH_R_QB, + MIPS_INS_SUBUH_R, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSPR2, 0}, + 0, + 0 +#endif + }, + {/* subv.b */ + Mips_SUBV_B, + MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subv.d */ + Mips_SUBV_D, + MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subv.h */ + Mips_SUBV_H, + MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subv.w */ + Mips_SUBV_W, + MIPS_INS_SUBV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subvi.b */ + Mips_SUBVI_B, + MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subvi.d */ + Mips_SUBVI_D, + MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subvi.h */ + Mips_SUBVI_H, + MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* subvi.w */ + Mips_SUBVI_W, + MIPS_INS_SUBVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* suxc1 */ + Mips_SUXC1, + MIPS_INS_SUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* suxc1 */ + Mips_SUXC164, + MIPS_INS_SUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, + MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* suxc1 */ + Mips_SUXC1_MM, + MIPS_INS_SUXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_FP64BIT, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SWSP_MMR6, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SWSP_MM, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SW, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SWDSP, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTINMIPS16MODE, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SWDSP_MM, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SW_MMR6, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SW_MM, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SwRxRyOffMemX16, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sw */ + Mips_SwRxSpImmX16, + MIPS_INS_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* sw16 */ + Mips_SW16_MM, + MIPS_INS_SW16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sw16 */ + Mips_SW16_MMR6, + MIPS_INS_SW16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swc1 */ + Mips_SWC1, + MIPS_INS_SWC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swc1 */ + Mips_SWC1_MM, + MIPS_INS_SWC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* swc2 */ + Mips_SWC2_R6, + MIPS_INS_SWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swc2 */ + Mips_SWC2_MMR6, + MIPS_INS_SWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swc2 */ + Mips_SWC2, + MIPS_INS_SWC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swc3 */ + Mips_SWC3, + MIPS_INS_SWC3, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTCNMIPS, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swe */ + Mips_SWE, + MIPS_INS_SWE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* swe */ + Mips_SWE_MM, + MIPS_INS_SWE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* swl */ + Mips_SWL, + MIPS_INS_SWL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swl */ + Mips_SWL_MM, + MIPS_INS_SWL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swle */ + Mips_SWLE, + MIPS_INS_SWLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swle */ + Mips_SWLE_MM, + MIPS_INS_SWLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* swm */ + Mips_SWM_MM, + MIPS_INS_SWM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swm16 */ + Mips_SWM16_MM, + MIPS_INS_SWM16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swm16 */ + Mips_SWM16_MMR6, + MIPS_INS_SWM16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swm32 */ + Mips_SWM32_MM, + MIPS_INS_SWM32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swp */ + Mips_SWP_MM, + MIPS_INS_SWP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swr */ + Mips_SWR, + MIPS_INS_SWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swr */ + Mips_SWR_MM, + MIPS_INS_SWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swre */ + Mips_SWRE, + MIPS_INS_SWRE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* swre */ + Mips_SWRE_MM, + MIPS_INS_SWRE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_EVA, 0}, + 0, + 0 +#endif + }, + {/* swsp */ + Mips_SWSP_MM, + MIPS_INS_SWSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* swxc1 */ + Mips_SWXC1, + MIPS_INS_SWXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* swxc1 */ + Mips_SWXC1_MM, + MIPS_INS_SWXC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC_MMR6, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC_MM, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC_MMR6, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* sync */ + Mips_SYNC_MM, + MIPS_INS_SYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* synci */ + Mips_SYNCI, + MIPS_INS_SYNCI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* synci */ + Mips_SYNCI_MM, + MIPS_INS_SYNCI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* synci */ + Mips_SYNCI_MMR6, + MIPS_INS_SYNCI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* synciobdma */ + Mips_SYNC, + MIPS_INS_SYNCIOBDMA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* syncs */ + Mips_SYNC, + MIPS_INS_SYNCS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* syncw */ + Mips_SYNC, + MIPS_INS_SYNCW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* syncws */ + Mips_SYNC, + MIPS_INS_SYNCWS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS64, MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* syscall */ + Mips_SYSCALL, + MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* syscall */ + Mips_SYSCALL_MM, + MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* syscall */ + Mips_SYSCALL_MM, + MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* syscall */ + Mips_SYSCALL, + MIPS_INS_SYSCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teq */ + Mips_TEQ, + MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teq */ + Mips_TEQ_MM, + MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teq */ + Mips_TEQ_MM, + MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teq */ + Mips_TEQ, + MIPS_INS_TEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teqi */ + Mips_TEQI, + MIPS_INS_TEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* teqi */ + Mips_TEQI_MM, + MIPS_INS_TEQI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tge */ + Mips_TGE, + MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tge */ + Mips_TGE_MM, + MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tge */ + Mips_TGE_MM, + MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tge */ + Mips_TGE, + MIPS_INS_TGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgei */ + Mips_TGEI, + MIPS_INS_TGEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgei */ + Mips_TGEI_MM, + MIPS_INS_TGEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tgeiu */ + Mips_TGEIU, + MIPS_INS_TGEIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgeiu */ + Mips_TGEIU_MM, + MIPS_INS_TGEIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tgeu */ + Mips_TGEU, + MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgeu */ + Mips_TGEU_MM, + MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgeu */ + Mips_TGEU_MM, + MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tgeu */ + Mips_TGEU, + MIPS_INS_TGEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbginv */ + Mips_TLBGINV, + MIPS_INS_TLBGINV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbginv */ + Mips_TLBGINV_MM, + MIPS_INS_TLBGINV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbginvf */ + Mips_TLBGINVF, + MIPS_INS_TLBGINVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbginvf */ + Mips_TLBGINVF_MM, + MIPS_INS_TLBGINVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbgp */ + Mips_TLBGP, + MIPS_INS_TLBGP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbgp */ + Mips_TLBGP_MM, + MIPS_INS_TLBGP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbgr */ + Mips_TLBGR, + MIPS_INS_TLBGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbgr */ + Mips_TLBGR_MM, + MIPS_INS_TLBGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbgwi */ + Mips_TLBGWI, + MIPS_INS_TLBGWI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbgwi */ + Mips_TLBGWI_MM, + MIPS_INS_TLBGWI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbgwr */ + Mips_TLBGWR, + MIPS_INS_TLBGWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbgwr */ + Mips_TLBGWR_MM, + MIPS_INS_TLBGWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R5, MIPS_GRP_VIRT, 0}, + 0, + 0 +#endif + }, + {/* tlbinv */ + Mips_TLBINV, + MIPS_INS_TLBINV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* tlbinv */ + Mips_TLBINV_MMR6, + MIPS_INS_TLBINV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tlbinvf */ + Mips_TLBINVF, + MIPS_INS_TLBINVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_EVA, MIPS_GRP_NOTINMICROMIPS, + 0}, + 0, + 0 +#endif + }, + {/* tlbinvf */ + Mips_TLBINVF_MMR6, + MIPS_INS_TLBINVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tlbp */ + Mips_TLBP, + MIPS_INS_TLBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbp */ + Mips_TLBP_MM, + MIPS_INS_TLBP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbr */ + Mips_TLBR, + MIPS_INS_TLBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbr */ + Mips_TLBR_MM, + MIPS_INS_TLBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbwi */ + Mips_TLBWI, + MIPS_INS_TLBWI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbwi */ + Mips_TLBWI_MM, + MIPS_INS_TLBWI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbwr */ + Mips_TLBWR, + MIPS_INS_TLBWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlbwr */ + Mips_TLBWR_MM, + MIPS_INS_TLBWR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlt */ + Mips_TLT, + MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlt */ + Mips_TLT_MM, + MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlt */ + Mips_TLT_MM, + MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlt */ + Mips_TLT, + MIPS_INS_TLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlti */ + Mips_TLTI, + MIPS_INS_TLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tlti */ + Mips_TLTI_MM, + MIPS_INS_TLTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tltiu */ + Mips_TTLTIU, + MIPS_INS_TLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tltiu */ + Mips_TLTIU_MM, + MIPS_INS_TLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* tltu */ + Mips_TLTU, + MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tltu */ + Mips_TLTU_MM, + MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tltu */ + Mips_TLTU_MM, + MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tltu */ + Mips_TLTU, + MIPS_INS_TLTU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tne */ + Mips_TNE, + MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tne */ + Mips_TNE_MM, + MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tne */ + Mips_TNE_MM, + MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tne */ + Mips_TNE, + MIPS_INS_TNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tnei */ + Mips_TNEI, + MIPS_INS_TNEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* tnei */ + Mips_TNEI_MM, + MIPS_INS_TNEI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* trunc.l.d */ + Mips_TRUNC_L_D64, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS3_32, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.l.d */ + Mips_TRUNC_L_D_MMR6, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.l.s */ + Mips_TRUNC_L_S, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.l.s */ + Mips_TRUNC_L_S_MMR6, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_TRUNC_W_D32, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, + MIPS_GRP_NOTSOFTFLOAT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_TRUNC_W_MM, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_TRUNC_W_D64, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_TRUNC_W_D_MMR6, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_PseudoTRUNC_W_D32, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.d */ + Mips_PseudoTRUNC_W_D, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_FP64BIT, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.s */ + Mips_TRUNC_W_S, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.s */ + Mips_TRUNC_W_S_MMR6, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.s */ + Mips_TRUNC_W_S_MM, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTSOFTFLOAT, 0}, + 0, + 0 +#endif + }, + {/* trunc.w.s */ + Mips_PseudoTRUNC_W_S, + MIPS_INS_TRUNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ulh */ + Mips_Ulh, + MIPS_INS_ULH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ulhu */ + Mips_Ulhu, + MIPS_INS_ULHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ulw */ + Mips_Ulw, + MIPS_INS_ULW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* ush */ + Mips_Ush, + MIPS_INS_USH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* usw */ + Mips_Usw, + MIPS_INS_USW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {/* v3mulu */ + Mips_V3MULU, + MIPS_INS_V3MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* v3mulu */ + Mips_V3MULU, + MIPS_INS_V3MULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vmm0 */ + Mips_VMM0, + MIPS_INS_VMM0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vmm0 */ + Mips_VMM0, + MIPS_INS_VMM0, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vmulu */ + Mips_VMULU, + MIPS_INS_VMULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vmulu */ + Mips_VMULU, + MIPS_INS_VMULU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_CNMIPS, 0}, + 0, + 0 +#endif + }, + {/* vshf.b */ + Mips_VSHF_B, + MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* vshf.d */ + Mips_VSHF_D, + MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* vshf.h */ + Mips_VSHF_H, + MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* vshf.w */ + Mips_VSHF_W, + MIPS_INS_VSHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* wait */ + Mips_WAIT, + MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wait */ + Mips_WAIT_MM, + MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wait */ + Mips_WAIT_MMR6, + MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* wait */ + Mips_WAIT_MM, + MIPS_INS_WAIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wrdsp */ + Mips_WRDSP, + MIPS_INS_WRDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wrdsp */ + Mips_WRDSP_MM, + MIPS_INS_WRDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wrdsp */ + Mips_WRDSP_MM, + MIPS_INS_WRDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_DSP, 0}, + 0, + 0 +#endif + }, + {/* wrdsp */ + Mips_WRDSP, + MIPS_INS_WRDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_DSP, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wrpgpr */ + Mips_WRPGPR_MMR6, + MIPS_INS_WRPGPR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* wsbh */ + Mips_WSBH, + MIPS_INS_WSBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* wsbh */ + Mips_WSBH_MMR6, + MIPS_INS_WSBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* wsbh */ + Mips_WSBH_MM, + MIPS_INS_WSBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XorRxRxRy16, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MIPS16MODE, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR_MM, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR_MMR6, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORI_MMR6, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi_MM, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi64, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR_MM, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XOR_MMR6, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORI_MMR6, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi_MM, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor */ + Mips_XORi64, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS3, + MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xor.v */ + Mips_XOR_V, + MIPS_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* xor16 */ + Mips_XOR16_MM, + MIPS_INS_XOR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xor16 */ + Mips_XOR16_MMR6, + MIPS_INS_XOR16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORI_MMR6, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORi, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORi_MM, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORI_MMR6, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORi, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* xori */ + Mips_XORi_MM, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MICROMIPS, MIPS_GRP_NOTMIPS32R6, 0}, + 0, + 0 +#endif + }, + {/* xori.b */ + Mips_XORI_B, + MIPS_INS_XORI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MSA, 0}, + 0, + 0 +#endif + }, + {/* yield */ + Mips_YIELD, + MIPS_INS_YIELD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, + {/* yield */ + Mips_YIELD, + MIPS_INS_YIELD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {MIPS_GRP_STDENC, MIPS_GRP_MT, MIPS_GRP_NOTINMICROMIPS, 0}, + 0, + 0 +#endif + }, +}; diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c index c8a159d80e..84b233a93c 100644 --- a/arch/Mips/MipsMapping.c +++ b/arch/Mips/MipsMapping.c @@ -3,7 +3,7 @@ #ifdef CAPSTONE_HAS_MIPS -#include // debug +#include // debug #include #include "../../utils.h" @@ -11,1060 +11,1741 @@ #include "MipsMapping.h" #define GET_INSTRINFO_ENUM -#include "MipsGenInstrInfo.inc" +#define GET_REGINFO_ENUM +#include "MipsGenDisassemblerTables.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { - { MIPS_REG_INVALID, NULL }, + {MIPS_REG_INVALID, NULL}, - { MIPS_REG_PC, "pc"}, + {MIPS_REG_PC, "pc"}, - //{ MIPS_REG_0, "0"}, - { MIPS_REG_0, "zero"}, - { MIPS_REG_1, "at"}, - //{ MIPS_REG_1, "1"}, - { MIPS_REG_2, "v0"}, - //{ MIPS_REG_2, "2"}, - { MIPS_REG_3, "v1"}, - //{ MIPS_REG_3, "3"}, - { MIPS_REG_4, "a0"}, - //{ MIPS_REG_4, "4"}, - { MIPS_REG_5, "a1"}, - //{ MIPS_REG_5, "5"}, - { MIPS_REG_6, "a2"}, - //{ MIPS_REG_6, "6"}, - { MIPS_REG_7, "a3"}, - //{ MIPS_REG_7, "7"}, - { MIPS_REG_8, "t0"}, - //{ MIPS_REG_8, "8"}, - { MIPS_REG_9, "t1"}, - //{ MIPS_REG_9, "9"}, - { MIPS_REG_10, "t2"}, - //{ MIPS_REG_10, "10"}, - { MIPS_REG_11, "t3"}, - //{ MIPS_REG_11, "11"}, - { MIPS_REG_12, "t4"}, - //{ MIPS_REG_12, "12"}, - { MIPS_REG_13, "t5"}, - //{ MIPS_REG_13, "13"}, - { MIPS_REG_14, "t6"}, - //{ MIPS_REG_14, "14"}, - { MIPS_REG_15, "t7"}, - //{ MIPS_REG_15, "15"}, - { MIPS_REG_16, "s0"}, - //{ MIPS_REG_16, "16"}, - { MIPS_REG_17, "s1"}, - //{ MIPS_REG_17, "17"}, - { MIPS_REG_18, "s2"}, - //{ MIPS_REG_18, "18"}, - { MIPS_REG_19, "s3"}, - //{ MIPS_REG_19, "19"}, - { MIPS_REG_20, "s4"}, - //{ MIPS_REG_20, "20"}, - { MIPS_REG_21, "s5"}, - //{ MIPS_REG_21, "21"}, - { MIPS_REG_22, "s6"}, - //{ MIPS_REG_22, "22"}, - { MIPS_REG_23, "s7"}, - //{ MIPS_REG_23, "23"}, - { MIPS_REG_24, "t8"}, - //{ MIPS_REG_24, "24"}, - { MIPS_REG_25, "t9"}, - //{ MIPS_REG_25, "25"}, - { MIPS_REG_26, "k0"}, - //{ MIPS_REG_26, "26"}, - { MIPS_REG_27, "k1"}, - //{ MIPS_REG_27, "27"}, - { MIPS_REG_28, "gp"}, - //{ MIPS_REG_28, "28"}, - { MIPS_REG_29, "sp"}, - //{ MIPS_REG_29, "29"}, - { MIPS_REG_30, "fp"}, - //{ MIPS_REG_30, "30"}, - { MIPS_REG_31, "ra"}, - //{ MIPS_REG_31, "31"}, + //{ MIPS_REG_0, "0"}, + {MIPS_REG_0, "zero"}, + {MIPS_REG_1, "at"}, + //{ MIPS_REG_1, "1"}, + {MIPS_REG_2, "v0"}, + //{ MIPS_REG_2, "2"}, + {MIPS_REG_3, "v1"}, + //{ MIPS_REG_3, "3"}, + {MIPS_REG_4, "a0"}, + //{ MIPS_REG_4, "4"}, + {MIPS_REG_5, "a1"}, + //{ MIPS_REG_5, "5"}, + {MIPS_REG_6, "a2"}, + //{ MIPS_REG_6, "6"}, + {MIPS_REG_7, "a3"}, + //{ MIPS_REG_7, "7"}, + {MIPS_REG_8, "t0"}, + //{ MIPS_REG_8, "8"}, + {MIPS_REG_9, "t1"}, + //{ MIPS_REG_9, "9"}, + {MIPS_REG_10, "t2"}, + //{ MIPS_REG_10, "10"}, + {MIPS_REG_11, "t3"}, + //{ MIPS_REG_11, "11"}, + {MIPS_REG_12, "t4"}, + //{ MIPS_REG_12, "12"}, + {MIPS_REG_13, "t5"}, + //{ MIPS_REG_13, "13"}, + {MIPS_REG_14, "t6"}, + //{ MIPS_REG_14, "14"}, + {MIPS_REG_15, "t7"}, + //{ MIPS_REG_15, "15"}, + {MIPS_REG_16, "s0"}, + //{ MIPS_REG_16, "16"}, + {MIPS_REG_17, "s1"}, + //{ MIPS_REG_17, "17"}, + {MIPS_REG_18, "s2"}, + //{ MIPS_REG_18, "18"}, + {MIPS_REG_19, "s3"}, + //{ MIPS_REG_19, "19"}, + {MIPS_REG_20, "s4"}, + //{ MIPS_REG_20, "20"}, + {MIPS_REG_21, "s5"}, + //{ MIPS_REG_21, "21"}, + {MIPS_REG_22, "s6"}, + //{ MIPS_REG_22, "22"}, + {MIPS_REG_23, "s7"}, + //{ MIPS_REG_23, "23"}, + {MIPS_REG_24, "t8"}, + //{ MIPS_REG_24, "24"}, + {MIPS_REG_25, "t9"}, + //{ MIPS_REG_25, "25"}, + {MIPS_REG_26, "k0"}, + //{ MIPS_REG_26, "26"}, + {MIPS_REG_27, "k1"}, + //{ MIPS_REG_27, "27"}, + {MIPS_REG_28, "gp"}, + //{ MIPS_REG_28, "28"}, + {MIPS_REG_29, "sp"}, + //{ MIPS_REG_29, "29"}, + {MIPS_REG_30, "fp"}, + //{ MIPS_REG_30, "30"}, + {MIPS_REG_31, "ra"}, + //{ MIPS_REG_31, "31"}, - { MIPS_REG_DSPCCOND, "dspccond"}, - { MIPS_REG_DSPCARRY, "dspcarry"}, - { MIPS_REG_DSPEFI, "dspefi"}, - { MIPS_REG_DSPOUTFLAG, "dspoutflag"}, - { MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"}, - { MIPS_REG_DSPOUTFLAG20, "dspoutflag20"}, - { MIPS_REG_DSPOUTFLAG21, "dspoutflag21"}, - { MIPS_REG_DSPOUTFLAG22, "dspoutflag22"}, - { MIPS_REG_DSPOUTFLAG23, "dspoutflag23"}, - { MIPS_REG_DSPPOS, "dsppos"}, - { MIPS_REG_DSPSCOUNT, "dspscount"}, + {MIPS_REG_DSPCCOND, "dspccond"}, + {MIPS_REG_DSPCARRY, "dspcarry"}, + {MIPS_REG_DSPEFI, "dspefi"}, + {MIPS_REG_DSPOUTFLAG, "dspoutflag"}, + {MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"}, + {MIPS_REG_DSPOUTFLAG20, "dspoutflag20"}, + {MIPS_REG_DSPOUTFLAG21, "dspoutflag21"}, + {MIPS_REG_DSPOUTFLAG22, "dspoutflag22"}, + {MIPS_REG_DSPOUTFLAG23, "dspoutflag23"}, + {MIPS_REG_DSPPOS, "dsppos"}, + {MIPS_REG_DSPSCOUNT, "dspscount"}, - { MIPS_REG_AC0, "ac0"}, - { MIPS_REG_AC1, "ac1"}, - { MIPS_REG_AC2, "ac2"}, - { MIPS_REG_AC3, "ac3"}, + {MIPS_REG_AC0, "ac0"}, + {MIPS_REG_AC1, "ac1"}, + {MIPS_REG_AC2, "ac2"}, + {MIPS_REG_AC3, "ac3"}, - { MIPS_REG_CC0, "cc0"}, - { MIPS_REG_CC1, "cc1"}, - { MIPS_REG_CC2, "cc2"}, - { MIPS_REG_CC3, "cc3"}, - { MIPS_REG_CC4, "cc4"}, - { MIPS_REG_CC5, "cc5"}, - { MIPS_REG_CC6, "cc6"}, - { MIPS_REG_CC7, "cc7"}, + {MIPS_REG_CC0, "cc0"}, + {MIPS_REG_CC1, "cc1"}, + {MIPS_REG_CC2, "cc2"}, + {MIPS_REG_CC3, "cc3"}, + {MIPS_REG_CC4, "cc4"}, + {MIPS_REG_CC5, "cc5"}, + {MIPS_REG_CC6, "cc6"}, + {MIPS_REG_CC7, "cc7"}, - { MIPS_REG_F0, "f0"}, - { MIPS_REG_F1, "f1"}, - { MIPS_REG_F2, "f2"}, - { MIPS_REG_F3, "f3"}, - { MIPS_REG_F4, "f4"}, - { MIPS_REG_F5, "f5"}, - { MIPS_REG_F6, "f6"}, - { MIPS_REG_F7, "f7"}, - { MIPS_REG_F8, "f8"}, - { MIPS_REG_F9, "f9"}, - { MIPS_REG_F10, "f10"}, - { MIPS_REG_F11, "f11"}, - { MIPS_REG_F12, "f12"}, - { MIPS_REG_F13, "f13"}, - { MIPS_REG_F14, "f14"}, - { MIPS_REG_F15, "f15"}, - { MIPS_REG_F16, "f16"}, - { MIPS_REG_F17, "f17"}, - { MIPS_REG_F18, "f18"}, - { MIPS_REG_F19, "f19"}, - { MIPS_REG_F20, "f20"}, - { MIPS_REG_F21, "f21"}, - { MIPS_REG_F22, "f22"}, - { MIPS_REG_F23, "f23"}, - { MIPS_REG_F24, "f24"}, - { MIPS_REG_F25, "f25"}, - { MIPS_REG_F26, "f26"}, - { MIPS_REG_F27, "f27"}, - { MIPS_REG_F28, "f28"}, - { MIPS_REG_F29, "f29"}, - { MIPS_REG_F30, "f30"}, - { MIPS_REG_F31, "f31"}, + {MIPS_REG_F0, "f0"}, + {MIPS_REG_F1, "f1"}, + {MIPS_REG_F2, "f2"}, + {MIPS_REG_F3, "f3"}, + {MIPS_REG_F4, "f4"}, + {MIPS_REG_F5, "f5"}, + {MIPS_REG_F6, "f6"}, + {MIPS_REG_F7, "f7"}, + {MIPS_REG_F8, "f8"}, + {MIPS_REG_F9, "f9"}, + {MIPS_REG_F10, "f10"}, + {MIPS_REG_F11, "f11"}, + {MIPS_REG_F12, "f12"}, + {MIPS_REG_F13, "f13"}, + {MIPS_REG_F14, "f14"}, + {MIPS_REG_F15, "f15"}, + {MIPS_REG_F16, "f16"}, + {MIPS_REG_F17, "f17"}, + {MIPS_REG_F18, "f18"}, + {MIPS_REG_F19, "f19"}, + {MIPS_REG_F20, "f20"}, + {MIPS_REG_F21, "f21"}, + {MIPS_REG_F22, "f22"}, + {MIPS_REG_F23, "f23"}, + {MIPS_REG_F24, "f24"}, + {MIPS_REG_F25, "f25"}, + {MIPS_REG_F26, "f26"}, + {MIPS_REG_F27, "f27"}, + {MIPS_REG_F28, "f28"}, + {MIPS_REG_F29, "f29"}, + {MIPS_REG_F30, "f30"}, + {MIPS_REG_F31, "f31"}, - { MIPS_REG_FCC0, "fcc0"}, - { MIPS_REG_FCC1, "fcc1"}, - { MIPS_REG_FCC2, "fcc2"}, - { MIPS_REG_FCC3, "fcc3"}, - { MIPS_REG_FCC4, "fcc4"}, - { MIPS_REG_FCC5, "fcc5"}, - { MIPS_REG_FCC6, "fcc6"}, - { MIPS_REG_FCC7, "fcc7"}, + {MIPS_REG_FCC0, "fcc0"}, + {MIPS_REG_FCC1, "fcc1"}, + {MIPS_REG_FCC2, "fcc2"}, + {MIPS_REG_FCC3, "fcc3"}, + {MIPS_REG_FCC4, "fcc4"}, + {MIPS_REG_FCC5, "fcc5"}, + {MIPS_REG_FCC6, "fcc6"}, + {MIPS_REG_FCC7, "fcc7"}, - { MIPS_REG_W0, "w0"}, - { MIPS_REG_W1, "w1"}, - { MIPS_REG_W2, "w2"}, - { MIPS_REG_W3, "w3"}, - { MIPS_REG_W4, "w4"}, - { MIPS_REG_W5, "w5"}, - { MIPS_REG_W6, "w6"}, - { MIPS_REG_W7, "w7"}, - { MIPS_REG_W8, "w8"}, - { MIPS_REG_W9, "w9"}, - { MIPS_REG_W10, "w10"}, - { MIPS_REG_W11, "w11"}, - { MIPS_REG_W12, "w12"}, - { MIPS_REG_W13, "w13"}, - { MIPS_REG_W14, "w14"}, - { MIPS_REG_W15, "w15"}, - { MIPS_REG_W16, "w16"}, - { MIPS_REG_W17, "w17"}, - { MIPS_REG_W18, "w18"}, - { MIPS_REG_W19, "w19"}, - { MIPS_REG_W20, "w20"}, - { MIPS_REG_W21, "w21"}, - { MIPS_REG_W22, "w22"}, - { MIPS_REG_W23, "w23"}, - { MIPS_REG_W24, "w24"}, - { MIPS_REG_W25, "w25"}, - { MIPS_REG_W26, "w26"}, - { MIPS_REG_W27, "w27"}, - { MIPS_REG_W28, "w28"}, - { MIPS_REG_W29, "w29"}, - { MIPS_REG_W30, "w30"}, - { MIPS_REG_W31, "w31"}, + {MIPS_REG_W0, "w0"}, + {MIPS_REG_W1, "w1"}, + {MIPS_REG_W2, "w2"}, + {MIPS_REG_W3, "w3"}, + {MIPS_REG_W4, "w4"}, + {MIPS_REG_W5, "w5"}, + {MIPS_REG_W6, "w6"}, + {MIPS_REG_W7, "w7"}, + {MIPS_REG_W8, "w8"}, + {MIPS_REG_W9, "w9"}, + {MIPS_REG_W10, "w10"}, + {MIPS_REG_W11, "w11"}, + {MIPS_REG_W12, "w12"}, + {MIPS_REG_W13, "w13"}, + {MIPS_REG_W14, "w14"}, + {MIPS_REG_W15, "w15"}, + {MIPS_REG_W16, "w16"}, + {MIPS_REG_W17, "w17"}, + {MIPS_REG_W18, "w18"}, + {MIPS_REG_W19, "w19"}, + {MIPS_REG_W20, "w20"}, + {MIPS_REG_W21, "w21"}, + {MIPS_REG_W22, "w22"}, + {MIPS_REG_W23, "w23"}, + {MIPS_REG_W24, "w24"}, + {MIPS_REG_W25, "w25"}, + {MIPS_REG_W26, "w26"}, + {MIPS_REG_W27, "w27"}, + {MIPS_REG_W28, "w28"}, + {MIPS_REG_W29, "w29"}, + {MIPS_REG_W30, "w30"}, + {MIPS_REG_W31, "w31"}, - { MIPS_REG_HI, "hi"}, - { MIPS_REG_LO, "lo"}, + {MIPS_REG_HI, "hi"}, + {MIPS_REG_LO, "lo"}, - { MIPS_REG_P0, "p0"}, - { MIPS_REG_P1, "p1"}, - { MIPS_REG_P2, "p2"}, + {MIPS_REG_P0, "p0"}, + {MIPS_REG_P1, "p1"}, + {MIPS_REG_P2, "p2"}, - { MIPS_REG_MPL0, "mpl0"}, - { MIPS_REG_MPL1, "mpl1"}, - { MIPS_REG_MPL2, "mpl2"}, + {MIPS_REG_MPL0, "mpl0"}, + {MIPS_REG_MPL1, "mpl1"}, + {MIPS_REG_MPL2, "mpl2"}, }; #endif -const char *Mips_reg_name(csh handle, unsigned int reg) -{ +const char *Mips_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; - - return reg_name_maps[reg].name; + return reg_name_maps[Mips_map_register(reg)].name; +// return NULL; #else - return NULL; + return NULL; #endif } - -static const insn_map insns[] = { - // dummy item - { - 0, 0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - -#include "MipsMappingInsn.inc" -}; +// TODO needs refactor +#include "MipsMapperInfo.inc" // given internal insn id, return public instruction info -void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) -{ - unsigned int i; +void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { + unsigned int i; - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; - if (h->detail) { + if (h->detail) { #ifndef CAPSTONE_DIET - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + memcpy(insn->detail->regs_read, insns[i].regs_use, + sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = + (uint8_t)count_positive(insns[i].regs_use); - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + memcpy(insn->detail->regs_write, insns[i].regs_mod, + sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = + (uint8_t)count_positive(insns[i].regs_mod); - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP; - insn->detail->groups_count++; - } + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP; + insn->detail->groups_count++; + } #endif - } - } + } + } } static const name_map insn_name_maps[] = { - { MIPS_INS_INVALID, NULL }, + {MIPS_INS_INVALID, NULL}, - { MIPS_INS_ABSQ_S, "absq_s" }, - { MIPS_INS_ADD, "add" }, - { MIPS_INS_ADDIUPC, "addiupc" }, - { MIPS_INS_ADDIUR1SP, "addiur1sp" }, - { MIPS_INS_ADDIUR2, "addiur2" }, - { MIPS_INS_ADDIUS5, "addius5" }, - { MIPS_INS_ADDIUSP, "addiusp" }, - { MIPS_INS_ADDQH, "addqh" }, - { MIPS_INS_ADDQH_R, "addqh_r" }, - { MIPS_INS_ADDQ, "addq" }, - { MIPS_INS_ADDQ_S, "addq_s" }, - { MIPS_INS_ADDSC, "addsc" }, - { MIPS_INS_ADDS_A, "adds_a" }, - { MIPS_INS_ADDS_S, "adds_s" }, - { MIPS_INS_ADDS_U, "adds_u" }, - { MIPS_INS_ADDU16, "addu16" }, - { MIPS_INS_ADDUH, "adduh" }, - { MIPS_INS_ADDUH_R, "adduh_r" }, - { MIPS_INS_ADDU, "addu" }, - { MIPS_INS_ADDU_S, "addu_s" }, - { MIPS_INS_ADDVI, "addvi" }, - { MIPS_INS_ADDV, "addv" }, - { MIPS_INS_ADDWC, "addwc" }, - { MIPS_INS_ADD_A, "add_a" }, - { MIPS_INS_ADDI, "addi" }, - { MIPS_INS_ADDIU, "addiu" }, - { MIPS_INS_ALIGN, "align" }, - { MIPS_INS_ALUIPC, "aluipc" }, - { MIPS_INS_AND, "and" }, - { MIPS_INS_AND16, "and16" }, - { MIPS_INS_ANDI16, "andi16" }, - { MIPS_INS_ANDI, "andi" }, - { MIPS_INS_APPEND, "append" }, - { MIPS_INS_ASUB_S, "asub_s" }, - { MIPS_INS_ASUB_U, "asub_u" }, - { MIPS_INS_AUI, "aui" }, - { MIPS_INS_AUIPC, "auipc" }, - { MIPS_INS_AVER_S, "aver_s" }, - { MIPS_INS_AVER_U, "aver_u" }, - { MIPS_INS_AVE_S, "ave_s" }, - { MIPS_INS_AVE_U, "ave_u" }, - { MIPS_INS_B16, "b16" }, - { MIPS_INS_BADDU, "baddu" }, - { MIPS_INS_BAL, "bal" }, - { MIPS_INS_BALC, "balc" }, - { MIPS_INS_BALIGN, "balign" }, - { MIPS_INS_BBIT0, "bbit0" }, - { MIPS_INS_BBIT032, "bbit032" }, - { MIPS_INS_BBIT1, "bbit1" }, - { MIPS_INS_BBIT132, "bbit132" }, - { MIPS_INS_BC, "bc" }, - { MIPS_INS_BC0F, "bc0f" }, - { MIPS_INS_BC0FL, "bc0fl" }, - { MIPS_INS_BC0T, "bc0t" }, - { MIPS_INS_BC0TL, "bc0tl" }, - { MIPS_INS_BC1EQZ, "bc1eqz" }, - { MIPS_INS_BC1F, "bc1f" }, - { MIPS_INS_BC1FL, "bc1fl" }, - { MIPS_INS_BC1NEZ, "bc1nez" }, - { MIPS_INS_BC1T, "bc1t" }, - { MIPS_INS_BC1TL, "bc1tl" }, - { MIPS_INS_BC2EQZ, "bc2eqz" }, - { MIPS_INS_BC2F, "bc2f" }, - { MIPS_INS_BC2FL, "bc2fl" }, - { MIPS_INS_BC2NEZ, "bc2nez" }, - { MIPS_INS_BC2T, "bc2t" }, - { MIPS_INS_BC2TL, "bc2tl" }, - { MIPS_INS_BC3F, "bc3f" }, - { MIPS_INS_BC3FL, "bc3fl" }, - { MIPS_INS_BC3T, "bc3t" }, - { MIPS_INS_BC3TL, "bc3tl" }, - { MIPS_INS_BCLRI, "bclri" }, - { MIPS_INS_BCLR, "bclr" }, - { MIPS_INS_BEQ, "beq" }, - { MIPS_INS_BEQC, "beqc" }, - { MIPS_INS_BEQL, "beql" }, - { MIPS_INS_BEQZ16, "beqz16" }, - { MIPS_INS_BEQZALC, "beqzalc" }, - { MIPS_INS_BEQZC, "beqzc" }, - { MIPS_INS_BGEC, "bgec" }, - { MIPS_INS_BGEUC, "bgeuc" }, - { MIPS_INS_BGEZ, "bgez" }, - { MIPS_INS_BGEZAL, "bgezal" }, - { MIPS_INS_BGEZALC, "bgezalc" }, - { MIPS_INS_BGEZALL, "bgezall" }, - { MIPS_INS_BGEZALS, "bgezals" }, - { MIPS_INS_BGEZC, "bgezc" }, - { MIPS_INS_BGEZL, "bgezl" }, - { MIPS_INS_BGTZ, "bgtz" }, - { MIPS_INS_BGTZALC, "bgtzalc" }, - { MIPS_INS_BGTZC, "bgtzc" }, - { MIPS_INS_BGTZL, "bgtzl" }, - { MIPS_INS_BINSLI, "binsli" }, - { MIPS_INS_BINSL, "binsl" }, - { MIPS_INS_BINSRI, "binsri" }, - { MIPS_INS_BINSR, "binsr" }, - { MIPS_INS_BITREV, "bitrev" }, - { MIPS_INS_BITSWAP, "bitswap" }, - { MIPS_INS_BLEZ, "blez" }, - { MIPS_INS_BLEZALC, "blezalc" }, - { MIPS_INS_BLEZC, "blezc" }, - { MIPS_INS_BLEZL, "blezl" }, - { MIPS_INS_BLTC, "bltc" }, - { MIPS_INS_BLTUC, "bltuc" }, - { MIPS_INS_BLTZ, "bltz" }, - { MIPS_INS_BLTZAL, "bltzal" }, - { MIPS_INS_BLTZALC, "bltzalc" }, - { MIPS_INS_BLTZALL, "bltzall" }, - { MIPS_INS_BLTZALS, "bltzals" }, - { MIPS_INS_BLTZC, "bltzc" }, - { MIPS_INS_BLTZL, "bltzl" }, - { MIPS_INS_BMNZI, "bmnzi" }, - { MIPS_INS_BMNZ, "bmnz" }, - { MIPS_INS_BMZI, "bmzi" }, - { MIPS_INS_BMZ, "bmz" }, - { MIPS_INS_BNE, "bne" }, - { MIPS_INS_BNEC, "bnec" }, - { MIPS_INS_BNEGI, "bnegi" }, - { MIPS_INS_BNEG, "bneg" }, - { MIPS_INS_BNEL, "bnel" }, - { MIPS_INS_BNEZ16, "bnez16" }, - { MIPS_INS_BNEZALC, "bnezalc" }, - { MIPS_INS_BNEZC, "bnezc" }, - { MIPS_INS_BNVC, "bnvc" }, - { MIPS_INS_BNZ, "bnz" }, - { MIPS_INS_BOVC, "bovc" }, - { MIPS_INS_BPOSGE32, "bposge32" }, - { MIPS_INS_BREAK, "break" }, - { MIPS_INS_BREAK16, "break16" }, - { MIPS_INS_BSELI, "bseli" }, - { MIPS_INS_BSEL, "bsel" }, - { MIPS_INS_BSETI, "bseti" }, - { MIPS_INS_BSET, "bset" }, - { MIPS_INS_BZ, "bz" }, - { MIPS_INS_BEQZ, "beqz" }, - { MIPS_INS_B, "b" }, - { MIPS_INS_BNEZ, "bnez" }, - { MIPS_INS_BTEQZ, "bteqz" }, - { MIPS_INS_BTNEZ, "btnez" }, - { MIPS_INS_CACHE, "cache" }, - { MIPS_INS_CEIL, "ceil" }, - { MIPS_INS_CEQI, "ceqi" }, - { MIPS_INS_CEQ, "ceq" }, - { MIPS_INS_CFC1, "cfc1" }, - { MIPS_INS_CFCMSA, "cfcmsa" }, - { MIPS_INS_CINS, "cins" }, - { MIPS_INS_CINS32, "cins32" }, - { MIPS_INS_CLASS, "class" }, - { MIPS_INS_CLEI_S, "clei_s" }, - { MIPS_INS_CLEI_U, "clei_u" }, - { MIPS_INS_CLE_S, "cle_s" }, - { MIPS_INS_CLE_U, "cle_u" }, - { MIPS_INS_CLO, "clo" }, - { MIPS_INS_CLTI_S, "clti_s" }, - { MIPS_INS_CLTI_U, "clti_u" }, - { MIPS_INS_CLT_S, "clt_s" }, - { MIPS_INS_CLT_U, "clt_u" }, - { MIPS_INS_CLZ, "clz" }, - { MIPS_INS_CMPGDU, "cmpgdu" }, - { MIPS_INS_CMPGU, "cmpgu" }, - { MIPS_INS_CMPU, "cmpu" }, - { MIPS_INS_CMP, "cmp" }, - { MIPS_INS_COPY_S, "copy_s" }, - { MIPS_INS_COPY_U, "copy_u" }, - { MIPS_INS_CTC1, "ctc1" }, - { MIPS_INS_CTCMSA, "ctcmsa" }, - { MIPS_INS_CVT, "cvt" }, - { MIPS_INS_C, "c" }, - { MIPS_INS_CMPI, "cmpi" }, - { MIPS_INS_DADD, "dadd" }, - { MIPS_INS_DADDI, "daddi" }, - { MIPS_INS_DADDIU, "daddiu" }, - { MIPS_INS_DADDU, "daddu" }, - { MIPS_INS_DAHI, "dahi" }, - { MIPS_INS_DALIGN, "dalign" }, - { MIPS_INS_DATI, "dati" }, - { MIPS_INS_DAUI, "daui" }, - { MIPS_INS_DBITSWAP, "dbitswap" }, - { MIPS_INS_DCLO, "dclo" }, - { MIPS_INS_DCLZ, "dclz" }, - { MIPS_INS_DDIV, "ddiv" }, - { MIPS_INS_DDIVU, "ddivu" }, - { MIPS_INS_DERET, "deret" }, - { MIPS_INS_DEXT, "dext" }, - { MIPS_INS_DEXTM, "dextm" }, - { MIPS_INS_DEXTU, "dextu" }, - { MIPS_INS_DI, "di" }, - { MIPS_INS_DINS, "dins" }, - { MIPS_INS_DINSM, "dinsm" }, - { MIPS_INS_DINSU, "dinsu" }, - { MIPS_INS_DIV, "div" }, - { MIPS_INS_DIVU, "divu" }, - { MIPS_INS_DIV_S, "div_s" }, - { MIPS_INS_DIV_U, "div_u" }, - { MIPS_INS_DLSA, "dlsa" }, - { MIPS_INS_DMFC0, "dmfc0" }, - { MIPS_INS_DMFC1, "dmfc1" }, - { MIPS_INS_DMFC2, "dmfc2" }, - { MIPS_INS_DMOD, "dmod" }, - { MIPS_INS_DMODU, "dmodu" }, - { MIPS_INS_DMTC0, "dmtc0" }, - { MIPS_INS_DMTC1, "dmtc1" }, - { MIPS_INS_DMTC2, "dmtc2" }, - { MIPS_INS_DMUH, "dmuh" }, - { MIPS_INS_DMUHU, "dmuhu" }, - { MIPS_INS_DMUL, "dmul" }, - { MIPS_INS_DMULT, "dmult" }, - { MIPS_INS_DMULTU, "dmultu" }, - { MIPS_INS_DMULU, "dmulu" }, - { MIPS_INS_DOTP_S, "dotp_s" }, - { MIPS_INS_DOTP_U, "dotp_u" }, - { MIPS_INS_DPADD_S, "dpadd_s" }, - { MIPS_INS_DPADD_U, "dpadd_u" }, - { MIPS_INS_DPAQX_SA, "dpaqx_sa" }, - { MIPS_INS_DPAQX_S, "dpaqx_s" }, - { MIPS_INS_DPAQ_SA, "dpaq_sa" }, - { MIPS_INS_DPAQ_S, "dpaq_s" }, - { MIPS_INS_DPAU, "dpau" }, - { MIPS_INS_DPAX, "dpax" }, - { MIPS_INS_DPA, "dpa" }, - { MIPS_INS_DPOP, "dpop" }, - { MIPS_INS_DPSQX_SA, "dpsqx_sa" }, - { MIPS_INS_DPSQX_S, "dpsqx_s" }, - { MIPS_INS_DPSQ_SA, "dpsq_sa" }, - { MIPS_INS_DPSQ_S, "dpsq_s" }, - { MIPS_INS_DPSUB_S, "dpsub_s" }, - { MIPS_INS_DPSUB_U, "dpsub_u" }, - { MIPS_INS_DPSU, "dpsu" }, - { MIPS_INS_DPSX, "dpsx" }, - { MIPS_INS_DPS, "dps" }, - { MIPS_INS_DROTR, "drotr" }, - { MIPS_INS_DROTR32, "drotr32" }, - { MIPS_INS_DROTRV, "drotrv" }, - { MIPS_INS_DSBH, "dsbh" }, - { MIPS_INS_DSHD, "dshd" }, - { MIPS_INS_DSLL, "dsll" }, - { MIPS_INS_DSLL32, "dsll32" }, - { MIPS_INS_DSLLV, "dsllv" }, - { MIPS_INS_DSRA, "dsra" }, - { MIPS_INS_DSRA32, "dsra32" }, - { MIPS_INS_DSRAV, "dsrav" }, - { MIPS_INS_DSRL, "dsrl" }, - { MIPS_INS_DSRL32, "dsrl32" }, - { MIPS_INS_DSRLV, "dsrlv" }, - { MIPS_INS_DSUB, "dsub" }, - { MIPS_INS_DSUBU, "dsubu" }, - { MIPS_INS_EHB, "ehb" }, - { MIPS_INS_EI, "ei" }, - { MIPS_INS_ERET, "eret" }, - { MIPS_INS_EXT, "ext" }, - { MIPS_INS_EXTP, "extp" }, - { MIPS_INS_EXTPDP, "extpdp" }, - { MIPS_INS_EXTPDPV, "extpdpv" }, - { MIPS_INS_EXTPV, "extpv" }, - { MIPS_INS_EXTRV_RS, "extrv_rs" }, - { MIPS_INS_EXTRV_R, "extrv_r" }, - { MIPS_INS_EXTRV_S, "extrv_s" }, - { MIPS_INS_EXTRV, "extrv" }, - { MIPS_INS_EXTR_RS, "extr_rs" }, - { MIPS_INS_EXTR_R, "extr_r" }, - { MIPS_INS_EXTR_S, "extr_s" }, - { MIPS_INS_EXTR, "extr" }, - { MIPS_INS_EXTS, "exts" }, - { MIPS_INS_EXTS32, "exts32" }, - { MIPS_INS_ABS, "abs" }, - { MIPS_INS_FADD, "fadd" }, - { MIPS_INS_FCAF, "fcaf" }, - { MIPS_INS_FCEQ, "fceq" }, - { MIPS_INS_FCLASS, "fclass" }, - { MIPS_INS_FCLE, "fcle" }, - { MIPS_INS_FCLT, "fclt" }, - { MIPS_INS_FCNE, "fcne" }, - { MIPS_INS_FCOR, "fcor" }, - { MIPS_INS_FCUEQ, "fcueq" }, - { MIPS_INS_FCULE, "fcule" }, - { MIPS_INS_FCULT, "fcult" }, - { MIPS_INS_FCUNE, "fcune" }, - { MIPS_INS_FCUN, "fcun" }, - { MIPS_INS_FDIV, "fdiv" }, - { MIPS_INS_FEXDO, "fexdo" }, - { MIPS_INS_FEXP2, "fexp2" }, - { MIPS_INS_FEXUPL, "fexupl" }, - { MIPS_INS_FEXUPR, "fexupr" }, - { MIPS_INS_FFINT_S, "ffint_s" }, - { MIPS_INS_FFINT_U, "ffint_u" }, - { MIPS_INS_FFQL, "ffql" }, - { MIPS_INS_FFQR, "ffqr" }, - { MIPS_INS_FILL, "fill" }, - { MIPS_INS_FLOG2, "flog2" }, - { MIPS_INS_FLOOR, "floor" }, - { MIPS_INS_FMADD, "fmadd" }, - { MIPS_INS_FMAX_A, "fmax_a" }, - { MIPS_INS_FMAX, "fmax" }, - { MIPS_INS_FMIN_A, "fmin_a" }, - { MIPS_INS_FMIN, "fmin" }, - { MIPS_INS_MOV, "mov" }, - { MIPS_INS_FMSUB, "fmsub" }, - { MIPS_INS_FMUL, "fmul" }, - { MIPS_INS_MUL, "mul" }, - { MIPS_INS_NEG, "neg" }, - { MIPS_INS_FRCP, "frcp" }, - { MIPS_INS_FRINT, "frint" }, - { MIPS_INS_FRSQRT, "frsqrt" }, - { MIPS_INS_FSAF, "fsaf" }, - { MIPS_INS_FSEQ, "fseq" }, - { MIPS_INS_FSLE, "fsle" }, - { MIPS_INS_FSLT, "fslt" }, - { MIPS_INS_FSNE, "fsne" }, - { MIPS_INS_FSOR, "fsor" }, - { MIPS_INS_FSQRT, "fsqrt" }, - { MIPS_INS_SQRT, "sqrt" }, - { MIPS_INS_FSUB, "fsub" }, - { MIPS_INS_SUB, "sub" }, - { MIPS_INS_FSUEQ, "fsueq" }, - { MIPS_INS_FSULE, "fsule" }, - { MIPS_INS_FSULT, "fsult" }, - { MIPS_INS_FSUNE, "fsune" }, - { MIPS_INS_FSUN, "fsun" }, - { MIPS_INS_FTINT_S, "ftint_s" }, - { MIPS_INS_FTINT_U, "ftint_u" }, - { MIPS_INS_FTQ, "ftq" }, - { MIPS_INS_FTRUNC_S, "ftrunc_s" }, - { MIPS_INS_FTRUNC_U, "ftrunc_u" }, - { MIPS_INS_HADD_S, "hadd_s" }, - { MIPS_INS_HADD_U, "hadd_u" }, - { MIPS_INS_HSUB_S, "hsub_s" }, - { MIPS_INS_HSUB_U, "hsub_u" }, - { MIPS_INS_ILVEV, "ilvev" }, - { MIPS_INS_ILVL, "ilvl" }, - { MIPS_INS_ILVOD, "ilvod" }, - { MIPS_INS_ILVR, "ilvr" }, - { MIPS_INS_INS, "ins" }, - { MIPS_INS_INSERT, "insert" }, - { MIPS_INS_INSV, "insv" }, - { MIPS_INS_INSVE, "insve" }, - { MIPS_INS_J, "j" }, - { MIPS_INS_JAL, "jal" }, - { MIPS_INS_JALR, "jalr" }, - { MIPS_INS_JALRS16, "jalrs16" }, - { MIPS_INS_JALRS, "jalrs" }, - { MIPS_INS_JALS, "jals" }, - { MIPS_INS_JALX, "jalx" }, - { MIPS_INS_JIALC, "jialc" }, - { MIPS_INS_JIC, "jic" }, - { MIPS_INS_JR, "jr" }, - { MIPS_INS_JR16, "jr16" }, - { MIPS_INS_JRADDIUSP, "jraddiusp" }, - { MIPS_INS_JRC, "jrc" }, - { MIPS_INS_JALRC, "jalrc" }, - { MIPS_INS_LB, "lb" }, - { MIPS_INS_LBU16, "lbu16" }, - { MIPS_INS_LBUX, "lbux" }, - { MIPS_INS_LBU, "lbu" }, - { MIPS_INS_LD, "ld" }, - { MIPS_INS_LDC1, "ldc1" }, - { MIPS_INS_LDC2, "ldc2" }, - { MIPS_INS_LDC3, "ldc3" }, - { MIPS_INS_LDI, "ldi" }, - { MIPS_INS_LDL, "ldl" }, - { MIPS_INS_LDPC, "ldpc" }, - { MIPS_INS_LDR, "ldr" }, - { MIPS_INS_LDXC1, "ldxc1" }, - { MIPS_INS_LH, "lh" }, - { MIPS_INS_LHU16, "lhu16" }, - { MIPS_INS_LHX, "lhx" }, - { MIPS_INS_LHU, "lhu" }, - { MIPS_INS_LI16, "li16" }, - { MIPS_INS_LL, "ll" }, - { MIPS_INS_LLD, "lld" }, - { MIPS_INS_LSA, "lsa" }, - { MIPS_INS_LUXC1, "luxc1" }, - { MIPS_INS_LUI, "lui" }, - { MIPS_INS_LW, "lw" }, - { MIPS_INS_LW16, "lw16" }, - { MIPS_INS_LWC1, "lwc1" }, - { MIPS_INS_LWC2, "lwc2" }, - { MIPS_INS_LWC3, "lwc3" }, - { MIPS_INS_LWL, "lwl" }, - { MIPS_INS_LWM16, "lwm16" }, - { MIPS_INS_LWM32, "lwm32" }, - { MIPS_INS_LWPC, "lwpc" }, - { MIPS_INS_LWP, "lwp" }, - { MIPS_INS_LWR, "lwr" }, - { MIPS_INS_LWUPC, "lwupc" }, - { MIPS_INS_LWU, "lwu" }, - { MIPS_INS_LWX, "lwx" }, - { MIPS_INS_LWXC1, "lwxc1" }, - { MIPS_INS_LWXS, "lwxs" }, - { MIPS_INS_LI, "li" }, - { MIPS_INS_MADD, "madd" }, - { MIPS_INS_MADDF, "maddf" }, - { MIPS_INS_MADDR_Q, "maddr_q" }, - { MIPS_INS_MADDU, "maddu" }, - { MIPS_INS_MADDV, "maddv" }, - { MIPS_INS_MADD_Q, "madd_q" }, - { MIPS_INS_MAQ_SA, "maq_sa" }, - { MIPS_INS_MAQ_S, "maq_s" }, - { MIPS_INS_MAXA, "maxa" }, - { MIPS_INS_MAXI_S, "maxi_s" }, - { MIPS_INS_MAXI_U, "maxi_u" }, - { MIPS_INS_MAX_A, "max_a" }, - { MIPS_INS_MAX, "max" }, - { MIPS_INS_MAX_S, "max_s" }, - { MIPS_INS_MAX_U, "max_u" }, - { MIPS_INS_MFC0, "mfc0" }, - { MIPS_INS_MFC1, "mfc1" }, - { MIPS_INS_MFC2, "mfc2" }, - { MIPS_INS_MFHC1, "mfhc1" }, - { MIPS_INS_MFHI, "mfhi" }, - { MIPS_INS_MFLO, "mflo" }, - { MIPS_INS_MINA, "mina" }, - { MIPS_INS_MINI_S, "mini_s" }, - { MIPS_INS_MINI_U, "mini_u" }, - { MIPS_INS_MIN_A, "min_a" }, - { MIPS_INS_MIN, "min" }, - { MIPS_INS_MIN_S, "min_s" }, - { MIPS_INS_MIN_U, "min_u" }, - { MIPS_INS_MOD, "mod" }, - { MIPS_INS_MODSUB, "modsub" }, - { MIPS_INS_MODU, "modu" }, - { MIPS_INS_MOD_S, "mod_s" }, - { MIPS_INS_MOD_U, "mod_u" }, - { MIPS_INS_MOVE, "move" }, - { MIPS_INS_MOVEP, "movep" }, - { MIPS_INS_MOVF, "movf" }, - { MIPS_INS_MOVN, "movn" }, - { MIPS_INS_MOVT, "movt" }, - { MIPS_INS_MOVZ, "movz" }, - { MIPS_INS_MSUB, "msub" }, - { MIPS_INS_MSUBF, "msubf" }, - { MIPS_INS_MSUBR_Q, "msubr_q" }, - { MIPS_INS_MSUBU, "msubu" }, - { MIPS_INS_MSUBV, "msubv" }, - { MIPS_INS_MSUB_Q, "msub_q" }, - { MIPS_INS_MTC0, "mtc0" }, - { MIPS_INS_MTC1, "mtc1" }, - { MIPS_INS_MTC2, "mtc2" }, - { MIPS_INS_MTHC1, "mthc1" }, - { MIPS_INS_MTHI, "mthi" }, - { MIPS_INS_MTHLIP, "mthlip" }, - { MIPS_INS_MTLO, "mtlo" }, - { MIPS_INS_MTM0, "mtm0" }, - { MIPS_INS_MTM1, "mtm1" }, - { MIPS_INS_MTM2, "mtm2" }, - { MIPS_INS_MTP0, "mtp0" }, - { MIPS_INS_MTP1, "mtp1" }, - { MIPS_INS_MTP2, "mtp2" }, - { MIPS_INS_MUH, "muh" }, - { MIPS_INS_MUHU, "muhu" }, - { MIPS_INS_MULEQ_S, "muleq_s" }, - { MIPS_INS_MULEU_S, "muleu_s" }, - { MIPS_INS_MULQ_RS, "mulq_rs" }, - { MIPS_INS_MULQ_S, "mulq_s" }, - { MIPS_INS_MULR_Q, "mulr_q" }, - { MIPS_INS_MULSAQ_S, "mulsaq_s" }, - { MIPS_INS_MULSA, "mulsa" }, - { MIPS_INS_MULT, "mult" }, - { MIPS_INS_MULTU, "multu" }, - { MIPS_INS_MULU, "mulu" }, - { MIPS_INS_MULV, "mulv" }, - { MIPS_INS_MUL_Q, "mul_q" }, - { MIPS_INS_MUL_S, "mul_s" }, - { MIPS_INS_NLOC, "nloc" }, - { MIPS_INS_NLZC, "nlzc" }, - { MIPS_INS_NMADD, "nmadd" }, - { MIPS_INS_NMSUB, "nmsub" }, - { MIPS_INS_NOR, "nor" }, - { MIPS_INS_NORI, "nori" }, - { MIPS_INS_NOT16, "not16" }, - { MIPS_INS_NOT, "not" }, - { MIPS_INS_OR, "or" }, - { MIPS_INS_OR16, "or16" }, - { MIPS_INS_ORI, "ori" }, - { MIPS_INS_PACKRL, "packrl" }, - { MIPS_INS_PAUSE, "pause" }, - { MIPS_INS_PCKEV, "pckev" }, - { MIPS_INS_PCKOD, "pckod" }, - { MIPS_INS_PCNT, "pcnt" }, - { MIPS_INS_PICK, "pick" }, - { MIPS_INS_POP, "pop" }, - { MIPS_INS_PRECEQU, "precequ" }, - { MIPS_INS_PRECEQ, "preceq" }, - { MIPS_INS_PRECEU, "preceu" }, - { MIPS_INS_PRECRQU_S, "precrqu_s" }, - { MIPS_INS_PRECRQ, "precrq" }, - { MIPS_INS_PRECRQ_RS, "precrq_rs" }, - { MIPS_INS_PRECR, "precr" }, - { MIPS_INS_PRECR_SRA, "precr_sra" }, - { MIPS_INS_PRECR_SRA_R, "precr_sra_r" }, - { MIPS_INS_PREF, "pref" }, - { MIPS_INS_PREPEND, "prepend" }, - { MIPS_INS_RADDU, "raddu" }, - { MIPS_INS_RDDSP, "rddsp" }, - { MIPS_INS_RDHWR, "rdhwr" }, - { MIPS_INS_REPLV, "replv" }, - { MIPS_INS_REPL, "repl" }, - { MIPS_INS_RINT, "rint" }, - { MIPS_INS_ROTR, "rotr" }, - { MIPS_INS_ROTRV, "rotrv" }, - { MIPS_INS_ROUND, "round" }, - { MIPS_INS_SAT_S, "sat_s" }, - { MIPS_INS_SAT_U, "sat_u" }, - { MIPS_INS_SB, "sb" }, - { MIPS_INS_SB16, "sb16" }, - { MIPS_INS_SC, "sc" }, - { MIPS_INS_SCD, "scd" }, - { MIPS_INS_SD, "sd" }, - { MIPS_INS_SDBBP, "sdbbp" }, - { MIPS_INS_SDBBP16, "sdbbp16" }, - { MIPS_INS_SDC1, "sdc1" }, - { MIPS_INS_SDC2, "sdc2" }, - { MIPS_INS_SDC3, "sdc3" }, - { MIPS_INS_SDL, "sdl" }, - { MIPS_INS_SDR, "sdr" }, - { MIPS_INS_SDXC1, "sdxc1" }, - { MIPS_INS_SEB, "seb" }, - { MIPS_INS_SEH, "seh" }, - { MIPS_INS_SELEQZ, "seleqz" }, - { MIPS_INS_SELNEZ, "selnez" }, - { MIPS_INS_SEL, "sel" }, - { MIPS_INS_SEQ, "seq" }, - { MIPS_INS_SEQI, "seqi" }, - { MIPS_INS_SH, "sh" }, - { MIPS_INS_SH16, "sh16" }, - { MIPS_INS_SHF, "shf" }, - { MIPS_INS_SHILO, "shilo" }, - { MIPS_INS_SHILOV, "shilov" }, - { MIPS_INS_SHLLV, "shllv" }, - { MIPS_INS_SHLLV_S, "shllv_s" }, - { MIPS_INS_SHLL, "shll" }, - { MIPS_INS_SHLL_S, "shll_s" }, - { MIPS_INS_SHRAV, "shrav" }, - { MIPS_INS_SHRAV_R, "shrav_r" }, - { MIPS_INS_SHRA, "shra" }, - { MIPS_INS_SHRA_R, "shra_r" }, - { MIPS_INS_SHRLV, "shrlv" }, - { MIPS_INS_SHRL, "shrl" }, - { MIPS_INS_SLDI, "sldi" }, - { MIPS_INS_SLD, "sld" }, - { MIPS_INS_SLL, "sll" }, - { MIPS_INS_SLL16, "sll16" }, - { MIPS_INS_SLLI, "slli" }, - { MIPS_INS_SLLV, "sllv" }, - { MIPS_INS_SLT, "slt" }, - { MIPS_INS_SLTI, "slti" }, - { MIPS_INS_SLTIU, "sltiu" }, - { MIPS_INS_SLTU, "sltu" }, - { MIPS_INS_SNE, "sne" }, - { MIPS_INS_SNEI, "snei" }, - { MIPS_INS_SPLATI, "splati" }, - { MIPS_INS_SPLAT, "splat" }, - { MIPS_INS_SRA, "sra" }, - { MIPS_INS_SRAI, "srai" }, - { MIPS_INS_SRARI, "srari" }, - { MIPS_INS_SRAR, "srar" }, - { MIPS_INS_SRAV, "srav" }, - { MIPS_INS_SRL, "srl" }, - { MIPS_INS_SRL16, "srl16" }, - { MIPS_INS_SRLI, "srli" }, - { MIPS_INS_SRLRI, "srlri" }, - { MIPS_INS_SRLR, "srlr" }, - { MIPS_INS_SRLV, "srlv" }, - { MIPS_INS_SSNOP, "ssnop" }, - { MIPS_INS_ST, "st" }, - { MIPS_INS_SUBQH, "subqh" }, - { MIPS_INS_SUBQH_R, "subqh_r" }, - { MIPS_INS_SUBQ, "subq" }, - { MIPS_INS_SUBQ_S, "subq_s" }, - { MIPS_INS_SUBSUS_U, "subsus_u" }, - { MIPS_INS_SUBSUU_S, "subsuu_s" }, - { MIPS_INS_SUBS_S, "subs_s" }, - { MIPS_INS_SUBS_U, "subs_u" }, - { MIPS_INS_SUBU16, "subu16" }, - { MIPS_INS_SUBUH, "subuh" }, - { MIPS_INS_SUBUH_R, "subuh_r" }, - { MIPS_INS_SUBU, "subu" }, - { MIPS_INS_SUBU_S, "subu_s" }, - { MIPS_INS_SUBVI, "subvi" }, - { MIPS_INS_SUBV, "subv" }, - { MIPS_INS_SUXC1, "suxc1" }, - { MIPS_INS_SW, "sw" }, - { MIPS_INS_SW16, "sw16" }, - { MIPS_INS_SWC1, "swc1" }, - { MIPS_INS_SWC2, "swc2" }, - { MIPS_INS_SWC3, "swc3" }, - { MIPS_INS_SWL, "swl" }, - { MIPS_INS_SWM16, "swm16" }, - { MIPS_INS_SWM32, "swm32" }, - { MIPS_INS_SWP, "swp" }, - { MIPS_INS_SWR, "swr" }, - { MIPS_INS_SWXC1, "swxc1" }, - { MIPS_INS_SYNC, "sync" }, - { MIPS_INS_SYNCI, "synci" }, - { MIPS_INS_SYSCALL, "syscall" }, - { MIPS_INS_TEQ, "teq" }, - { MIPS_INS_TEQI, "teqi" }, - { MIPS_INS_TGE, "tge" }, - { MIPS_INS_TGEI, "tgei" }, - { MIPS_INS_TGEIU, "tgeiu" }, - { MIPS_INS_TGEU, "tgeu" }, - { MIPS_INS_TLBP, "tlbp" }, - { MIPS_INS_TLBR, "tlbr" }, - { MIPS_INS_TLBWI, "tlbwi" }, - { MIPS_INS_TLBWR, "tlbwr" }, - { MIPS_INS_TLT, "tlt" }, - { MIPS_INS_TLTI, "tlti" }, - { MIPS_INS_TLTIU, "tltiu" }, - { MIPS_INS_TLTU, "tltu" }, - { MIPS_INS_TNE, "tne" }, - { MIPS_INS_TNEI, "tnei" }, - { MIPS_INS_TRUNC, "trunc" }, - { MIPS_INS_V3MULU, "v3mulu" }, - { MIPS_INS_VMM0, "vmm0" }, - { MIPS_INS_VMULU, "vmulu" }, - { MIPS_INS_VSHF, "vshf" }, - { MIPS_INS_WAIT, "wait" }, - { MIPS_INS_WRDSP, "wrdsp" }, - { MIPS_INS_WSBH, "wsbh" }, - { MIPS_INS_XOR, "xor" }, - { MIPS_INS_XOR16, "xor16" }, - { MIPS_INS_XORI, "xori" }, + {MIPS_INS_ABSQ_S, "absq_s"}, + {MIPS_INS_ADD, "add"}, + {MIPS_INS_ADDIUPC, "addiupc"}, + {MIPS_INS_ADDIUR1SP, "addiur1sp"}, + {MIPS_INS_ADDIUR2, "addiur2"}, + {MIPS_INS_ADDIUS5, "addius5"}, + {MIPS_INS_ADDIUSP, "addiusp"}, + {MIPS_INS_ADDQH, "addqh"}, + {MIPS_INS_ADDQH_R, "addqh_r"}, + {MIPS_INS_ADDQ, "addq"}, + {MIPS_INS_ADDQ_S, "addq_s"}, + {MIPS_INS_ADDSC, "addsc"}, + {MIPS_INS_ADDS_A, "adds_a"}, + {MIPS_INS_ADDS_S, "adds_s"}, + {MIPS_INS_ADDS_U, "adds_u"}, + {MIPS_INS_ADDU16, "addu16"}, + {MIPS_INS_ADDUH, "adduh"}, + {MIPS_INS_ADDUH_R, "adduh_r"}, + {MIPS_INS_ADDU, "addu"}, + {MIPS_INS_ADDU_S, "addu_s"}, + {MIPS_INS_ADDVI, "addvi"}, + {MIPS_INS_ADDV, "addv"}, + {MIPS_INS_ADDWC, "addwc"}, + {MIPS_INS_ADD_A, "add_a"}, + {MIPS_INS_ADDI, "addi"}, + {MIPS_INS_ADDIU, "addiu"}, + {MIPS_INS_ALIGN, "align"}, + {MIPS_INS_ALUIPC, "aluipc"}, + {MIPS_INS_AND, "and"}, + {MIPS_INS_AND16, "and16"}, + {MIPS_INS_ANDI16, "andi16"}, + {MIPS_INS_ANDI, "andi"}, + {MIPS_INS_APPEND, "append"}, + {MIPS_INS_ASUB_S, "asub_s"}, + {MIPS_INS_ASUB_U, "asub_u"}, + {MIPS_INS_AUI, "aui"}, + {MIPS_INS_AUIPC, "auipc"}, + {MIPS_INS_AVER_S, "aver_s"}, + {MIPS_INS_AVER_U, "aver_u"}, + {MIPS_INS_AVE_S, "ave_s"}, + {MIPS_INS_AVE_U, "ave_u"}, + {MIPS_INS_B16, "b16"}, + {MIPS_INS_BADDU, "baddu"}, + {MIPS_INS_BAL, "bal"}, + {MIPS_INS_BALC, "balc"}, + {MIPS_INS_BALIGN, "balign"}, + {MIPS_INS_BBIT0, "bbit0"}, + {MIPS_INS_BBIT032, "bbit032"}, + {MIPS_INS_BBIT1, "bbit1"}, + {MIPS_INS_BBIT132, "bbit132"}, + {MIPS_INS_BC, "bc"}, + {MIPS_INS_BC1EQZ, "bc1eqz"}, + {MIPS_INS_BC1F, "bc1f"}, + {MIPS_INS_BC1FL, "bc1fl"}, + {MIPS_INS_BC1NEZ, "bc1nez"}, + {MIPS_INS_BC1T, "bc1t"}, + {MIPS_INS_BC1TL, "bc1tl"}, + {MIPS_INS_BC2EQZ, "bc2eqz"}, + {MIPS_INS_BC2NEZ, "bc2nez"}, + {MIPS_INS_BCLRI, "bclri"}, + {MIPS_INS_BCLR, "bclr"}, + {MIPS_INS_BEQ, "beq"}, + {MIPS_INS_BEQC, "beqc"}, + {MIPS_INS_BEQL, "beql"}, + {MIPS_INS_BEQZ16, "beqz16"}, + {MIPS_INS_BEQZALC, "beqzalc"}, + {MIPS_INS_BEQZC, "beqzc"}, + {MIPS_INS_BGEC, "bgec"}, + {MIPS_INS_BGEUC, "bgeuc"}, + {MIPS_INS_BGEZ, "bgez"}, + {MIPS_INS_BGEZAL, "bgezal"}, + {MIPS_INS_BGEZALC, "bgezalc"}, + {MIPS_INS_BGEZALL, "bgezall"}, + {MIPS_INS_BGEZALS, "bgezals"}, + {MIPS_INS_BGEZC, "bgezc"}, + {MIPS_INS_BGEZL, "bgezl"}, + {MIPS_INS_BGTZ, "bgtz"}, + {MIPS_INS_BGTZALC, "bgtzalc"}, + {MIPS_INS_BGTZC, "bgtzc"}, + {MIPS_INS_BGTZL, "bgtzl"}, + {MIPS_INS_BINSLI, "binsli"}, + {MIPS_INS_BINSL, "binsl"}, + {MIPS_INS_BINSRI, "binsri"}, + {MIPS_INS_BINSR, "binsr"}, + {MIPS_INS_BITREV, "bitrev"}, + {MIPS_INS_BITSWAP, "bitswap"}, + {MIPS_INS_BLEZ, "blez"}, + {MIPS_INS_BLEZALC, "blezalc"}, + {MIPS_INS_BLEZC, "blezc"}, + {MIPS_INS_BLEZL, "blezl"}, + {MIPS_INS_BLTC, "bltc"}, + {MIPS_INS_BLTUC, "bltuc"}, + {MIPS_INS_BLTZ, "bltz"}, + {MIPS_INS_BLTZAL, "bltzal"}, + {MIPS_INS_BLTZALC, "bltzalc"}, + {MIPS_INS_BLTZALL, "bltzall"}, + {MIPS_INS_BLTZALS, "bltzals"}, + {MIPS_INS_BLTZC, "bltzc"}, + {MIPS_INS_BLTZL, "bltzl"}, + {MIPS_INS_BMNZI, "bmnzi"}, + {MIPS_INS_BMNZ, "bmnz"}, + {MIPS_INS_BMZI, "bmzi"}, + {MIPS_INS_BMZ, "bmz"}, + {MIPS_INS_BNE, "bne"}, + {MIPS_INS_BNEC, "bnec"}, + {MIPS_INS_BNEGI, "bnegi"}, + {MIPS_INS_BNEG, "bneg"}, + {MIPS_INS_BNEL, "bnel"}, + {MIPS_INS_BNEZ16, "bnez16"}, + {MIPS_INS_BNEZALC, "bnezalc"}, + {MIPS_INS_BNEZC, "bnezc"}, + {MIPS_INS_BNVC, "bnvc"}, + {MIPS_INS_BNZ, "bnz"}, + {MIPS_INS_BOVC, "bovc"}, + {MIPS_INS_BPOSGE32, "bposge32"}, + {MIPS_INS_BREAK, "break"}, + {MIPS_INS_BREAK16, "break16"}, + {MIPS_INS_BSELI, "bseli"}, + {MIPS_INS_BSEL, "bsel"}, + {MIPS_INS_BSETI, "bseti"}, + {MIPS_INS_BSET, "bset"}, + {MIPS_INS_BZ, "bz"}, + {MIPS_INS_BEQZ, "beqz"}, + {MIPS_INS_B, "b"}, + {MIPS_INS_BNEZ, "bnez"}, + {MIPS_INS_BTEQZ, "bteqz"}, + {MIPS_INS_BTNEZ, "btnez"}, + {MIPS_INS_CACHE, "cache"}, + {MIPS_INS_CEIL, "ceil"}, + {MIPS_INS_CEQI, "ceqi"}, + {MIPS_INS_CEQ, "ceq"}, + {MIPS_INS_CFC1, "cfc1"}, + {MIPS_INS_CFCMSA, "cfcmsa"}, + {MIPS_INS_CINS, "cins"}, + {MIPS_INS_CINS32, "cins32"}, + {MIPS_INS_CLASS, "class"}, + {MIPS_INS_CLEI_S, "clei_s"}, + {MIPS_INS_CLEI_U, "clei_u"}, + {MIPS_INS_CLE_S, "cle_s"}, + {MIPS_INS_CLE_U, "cle_u"}, + {MIPS_INS_CLO, "clo"}, + {MIPS_INS_CLTI_S, "clti_s"}, + {MIPS_INS_CLTI_U, "clti_u"}, + {MIPS_INS_CLT_S, "clt_s"}, + {MIPS_INS_CLT_U, "clt_u"}, + {MIPS_INS_CLZ, "clz"}, + {MIPS_INS_CMPGDU, "cmpgdu"}, + {MIPS_INS_CMPGU, "cmpgu"}, + {MIPS_INS_CMPU, "cmpu"}, + {MIPS_INS_CMP, "cmp"}, + {MIPS_INS_COPY_S, "copy_s"}, + {MIPS_INS_COPY_U, "copy_u"}, + {MIPS_INS_CTC1, "ctc1"}, + {MIPS_INS_CTCMSA, "ctcmsa"}, + {MIPS_INS_CVT, "cvt"}, + {MIPS_INS_C, "c"}, + {MIPS_INS_CMPI, "cmpi"}, + {MIPS_INS_DADD, "dadd"}, + {MIPS_INS_DADDI, "daddi"}, + {MIPS_INS_DADDIU, "daddiu"}, + {MIPS_INS_DADDU, "daddu"}, + {MIPS_INS_DAHI, "dahi"}, + {MIPS_INS_DALIGN, "dalign"}, + {MIPS_INS_DATI, "dati"}, + {MIPS_INS_DAUI, "daui"}, + {MIPS_INS_DBITSWAP, "dbitswap"}, + {MIPS_INS_DCLO, "dclo"}, + {MIPS_INS_DCLZ, "dclz"}, + {MIPS_INS_DDIV, "ddiv"}, + {MIPS_INS_DDIVU, "ddivu"}, + {MIPS_INS_DERET, "deret"}, + {MIPS_INS_DEXT, "dext"}, + {MIPS_INS_DEXTM, "dextm"}, + {MIPS_INS_DEXTU, "dextu"}, + {MIPS_INS_DI, "di"}, + {MIPS_INS_DINS, "dins"}, + {MIPS_INS_DINSM, "dinsm"}, + {MIPS_INS_DINSU, "dinsu"}, + {MIPS_INS_DIV, "div"}, + {MIPS_INS_DIVU, "divu"}, + {MIPS_INS_DIV_S, "div_s"}, + {MIPS_INS_DIV_U, "div_u"}, + {MIPS_INS_DLSA, "dlsa"}, + {MIPS_INS_DMFC0, "dmfc0"}, + {MIPS_INS_DMFC1, "dmfc1"}, + {MIPS_INS_DMFC2, "dmfc2"}, + {MIPS_INS_DMOD, "dmod"}, + {MIPS_INS_DMODU, "dmodu"}, + {MIPS_INS_DMTC0, "dmtc0"}, + {MIPS_INS_DMTC1, "dmtc1"}, + {MIPS_INS_DMTC2, "dmtc2"}, + {MIPS_INS_DMUH, "dmuh"}, + {MIPS_INS_DMUHU, "dmuhu"}, + {MIPS_INS_DMUL, "dmul"}, + {MIPS_INS_DMULT, "dmult"}, + {MIPS_INS_DMULTU, "dmultu"}, + {MIPS_INS_DMULU, "dmulu"}, + {MIPS_INS_DOTP_S, "dotp_s"}, + {MIPS_INS_DOTP_U, "dotp_u"}, + {MIPS_INS_DPADD_S, "dpadd_s"}, + {MIPS_INS_DPADD_U, "dpadd_u"}, + {MIPS_INS_DPAQX_SA, "dpaqx_sa"}, + {MIPS_INS_DPAQX_S, "dpaqx_s"}, + {MIPS_INS_DPAQ_SA, "dpaq_sa"}, + {MIPS_INS_DPAQ_S, "dpaq_s"}, + {MIPS_INS_DPAU, "dpau"}, + {MIPS_INS_DPAX, "dpax"}, + {MIPS_INS_DPA, "dpa"}, + {MIPS_INS_DPOP, "dpop"}, + {MIPS_INS_DPSQX_SA, "dpsqx_sa"}, + {MIPS_INS_DPSQX_S, "dpsqx_s"}, + {MIPS_INS_DPSQ_SA, "dpsq_sa"}, + {MIPS_INS_DPSQ_S, "dpsq_s"}, + {MIPS_INS_DPSUB_S, "dpsub_s"}, + {MIPS_INS_DPSUB_U, "dpsub_u"}, + {MIPS_INS_DPSU, "dpsu"}, + {MIPS_INS_DPSX, "dpsx"}, + {MIPS_INS_DPS, "dps"}, + {MIPS_INS_DROTR, "drotr"}, + {MIPS_INS_DROTR32, "drotr32"}, + {MIPS_INS_DROTRV, "drotrv"}, + {MIPS_INS_DSBH, "dsbh"}, + {MIPS_INS_DSHD, "dshd"}, + {MIPS_INS_DSLL, "dsll"}, + {MIPS_INS_DSLL32, "dsll32"}, + {MIPS_INS_DSLLV, "dsllv"}, + {MIPS_INS_DSRA, "dsra"}, + {MIPS_INS_DSRA32, "dsra32"}, + {MIPS_INS_DSRAV, "dsrav"}, + {MIPS_INS_DSRL, "dsrl"}, + {MIPS_INS_DSRL32, "dsrl32"}, + {MIPS_INS_DSRLV, "dsrlv"}, + {MIPS_INS_DSUB, "dsub"}, + {MIPS_INS_DSUBU, "dsubu"}, + {MIPS_INS_EHB, "ehb"}, + {MIPS_INS_EI, "ei"}, + {MIPS_INS_ERET, "eret"}, + {MIPS_INS_EXT, "ext"}, + {MIPS_INS_EXTP, "extp"}, + {MIPS_INS_EXTPDP, "extpdp"}, + {MIPS_INS_EXTPDPV, "extpdpv"}, + {MIPS_INS_EXTPV, "extpv"}, + {MIPS_INS_EXTRV_RS, "extrv_rs"}, + {MIPS_INS_EXTRV_R, "extrv_r"}, + {MIPS_INS_EXTRV_S, "extrv_s"}, + {MIPS_INS_EXTRV, "extrv"}, + {MIPS_INS_EXTR_RS, "extr_rs"}, + {MIPS_INS_EXTR_R, "extr_r"}, + {MIPS_INS_EXTR_S, "extr_s"}, + {MIPS_INS_EXTR, "extr"}, + {MIPS_INS_EXTS, "exts"}, + {MIPS_INS_EXTS32, "exts32"}, + {MIPS_INS_ABS, "abs"}, + {MIPS_INS_FADD, "fadd"}, + {MIPS_INS_FCAF, "fcaf"}, + {MIPS_INS_FCEQ, "fceq"}, + {MIPS_INS_FCLASS, "fclass"}, + {MIPS_INS_FCLE, "fcle"}, + {MIPS_INS_FCLT, "fclt"}, + {MIPS_INS_FCNE, "fcne"}, + {MIPS_INS_FCOR, "fcor"}, + {MIPS_INS_FCUEQ, "fcueq"}, + {MIPS_INS_FCULE, "fcule"}, + {MIPS_INS_FCULT, "fcult"}, + {MIPS_INS_FCUNE, "fcune"}, + {MIPS_INS_FCUN, "fcun"}, + {MIPS_INS_FDIV, "fdiv"}, + {MIPS_INS_FEXDO, "fexdo"}, + {MIPS_INS_FEXP2, "fexp2"}, + {MIPS_INS_FEXUPL, "fexupl"}, + {MIPS_INS_FEXUPR, "fexupr"}, + {MIPS_INS_FFINT_S, "ffint_s"}, + {MIPS_INS_FFINT_U, "ffint_u"}, + {MIPS_INS_FFQL, "ffql"}, + {MIPS_INS_FFQR, "ffqr"}, + {MIPS_INS_FILL, "fill"}, + {MIPS_INS_FLOG2, "flog2"}, + {MIPS_INS_FLOOR, "floor"}, + {MIPS_INS_FMADD, "fmadd"}, + {MIPS_INS_FMAX_A, "fmax_a"}, + {MIPS_INS_FMAX, "fmax"}, + {MIPS_INS_FMIN_A, "fmin_a"}, + {MIPS_INS_FMIN, "fmin"}, + {MIPS_INS_MOV, "mov"}, + {MIPS_INS_FMSUB, "fmsub"}, + {MIPS_INS_FMUL, "fmul"}, + {MIPS_INS_MUL, "mul"}, + {MIPS_INS_NEG, "neg"}, + {MIPS_INS_FRCP, "frcp"}, + {MIPS_INS_FRINT, "frint"}, + {MIPS_INS_FRSQRT, "frsqrt"}, + {MIPS_INS_FSAF, "fsaf"}, + {MIPS_INS_FSEQ, "fseq"}, + {MIPS_INS_FSLE, "fsle"}, + {MIPS_INS_FSLT, "fslt"}, + {MIPS_INS_FSNE, "fsne"}, + {MIPS_INS_FSOR, "fsor"}, + {MIPS_INS_FSQRT, "fsqrt"}, + {MIPS_INS_SQRT, "sqrt"}, + {MIPS_INS_FSUB, "fsub"}, + {MIPS_INS_SUB, "sub"}, + {MIPS_INS_FSUEQ, "fsueq"}, + {MIPS_INS_FSULE, "fsule"}, + {MIPS_INS_FSULT, "fsult"}, + {MIPS_INS_FSUNE, "fsune"}, + {MIPS_INS_FSUN, "fsun"}, + {MIPS_INS_FTINT_S, "ftint_s"}, + {MIPS_INS_FTINT_U, "ftint_u"}, + {MIPS_INS_FTQ, "ftq"}, + {MIPS_INS_FTRUNC_S, "ftrunc_s"}, + {MIPS_INS_FTRUNC_U, "ftrunc_u"}, + {MIPS_INS_HADD_S, "hadd_s"}, + {MIPS_INS_HADD_U, "hadd_u"}, + {MIPS_INS_HSUB_S, "hsub_s"}, + {MIPS_INS_HSUB_U, "hsub_u"}, + {MIPS_INS_ILVEV, "ilvev"}, + {MIPS_INS_ILVL, "ilvl"}, + {MIPS_INS_ILVOD, "ilvod"}, + {MIPS_INS_ILVR, "ilvr"}, + {MIPS_INS_INS, "ins"}, + {MIPS_INS_INSERT, "insert"}, + {MIPS_INS_INSV, "insv"}, + {MIPS_INS_INSVE, "insve"}, + {MIPS_INS_J, "j"}, + {MIPS_INS_JAL, "jal"}, + {MIPS_INS_JALR, "jalr"}, + {MIPS_INS_JALRS16, "jalrs16"}, + {MIPS_INS_JALRS, "jalrs"}, + {MIPS_INS_JALS, "jals"}, + {MIPS_INS_JALX, "jalx"}, + {MIPS_INS_JIALC, "jialc"}, + {MIPS_INS_JIC, "jic"}, + {MIPS_INS_JR, "jr"}, + {MIPS_INS_JR16, "jr16"}, + {MIPS_INS_JRADDIUSP, "jraddiusp"}, + {MIPS_INS_JRC, "jrc"}, + {MIPS_INS_JALRC, "jalrc"}, + {MIPS_INS_LB, "lb"}, + {MIPS_INS_LBU16, "lbu16"}, + {MIPS_INS_LBUX, "lbux"}, + {MIPS_INS_LBU, "lbu"}, + {MIPS_INS_LD, "ld"}, + {MIPS_INS_LDC1, "ldc1"}, + {MIPS_INS_LDC2, "ldc2"}, + {MIPS_INS_LDC3, "ldc3"}, + {MIPS_INS_LDI, "ldi"}, + {MIPS_INS_LDL, "ldl"}, + {MIPS_INS_LDPC, "ldpc"}, + {MIPS_INS_LDR, "ldr"}, + {MIPS_INS_LDXC1, "ldxc1"}, + {MIPS_INS_LH, "lh"}, + {MIPS_INS_LHU16, "lhu16"}, + {MIPS_INS_LHX, "lhx"}, + {MIPS_INS_LHU, "lhu"}, + {MIPS_INS_LI16, "li16"}, + {MIPS_INS_LL, "ll"}, + {MIPS_INS_LLD, "lld"}, + {MIPS_INS_LSA, "lsa"}, + {MIPS_INS_LUXC1, "luxc1"}, + {MIPS_INS_LUI, "lui"}, + {MIPS_INS_LW, "lw"}, + {MIPS_INS_LW16, "lw16"}, + {MIPS_INS_LWC1, "lwc1"}, + {MIPS_INS_LWC2, "lwc2"}, + {MIPS_INS_LWC3, "lwc3"}, + {MIPS_INS_LWL, "lwl"}, + {MIPS_INS_LWM16, "lwm16"}, + {MIPS_INS_LWM32, "lwm32"}, + {MIPS_INS_LWPC, "lwpc"}, + {MIPS_INS_LWP, "lwp"}, + {MIPS_INS_LWR, "lwr"}, + {MIPS_INS_LWUPC, "lwupc"}, + {MIPS_INS_LWU, "lwu"}, + {MIPS_INS_LWX, "lwx"}, + {MIPS_INS_LWXC1, "lwxc1"}, + {MIPS_INS_LWXS, "lwxs"}, + {MIPS_INS_LI, "li"}, + {MIPS_INS_MADD, "madd"}, + {MIPS_INS_MADDF, "maddf"}, + {MIPS_INS_MADDR_Q, "maddr_q"}, + {MIPS_INS_MADDU, "maddu"}, + {MIPS_INS_MADDV, "maddv"}, + {MIPS_INS_MADD_Q, "madd_q"}, + {MIPS_INS_MAQ_SA, "maq_sa"}, + {MIPS_INS_MAQ_S, "maq_s"}, + {MIPS_INS_MAXA, "maxa"}, + {MIPS_INS_MAXI_S, "maxi_s"}, + {MIPS_INS_MAXI_U, "maxi_u"}, + {MIPS_INS_MAX_A, "max_a"}, + {MIPS_INS_MAX, "max"}, + {MIPS_INS_MAX_S, "max_s"}, + {MIPS_INS_MAX_U, "max_u"}, + {MIPS_INS_MFC0, "mfc0"}, + {MIPS_INS_MFC1, "mfc1"}, + {MIPS_INS_MFC2, "mfc2"}, + {MIPS_INS_MFHC1, "mfhc1"}, + {MIPS_INS_MFHI, "mfhi"}, + {MIPS_INS_MFLO, "mflo"}, + {MIPS_INS_MINA, "mina"}, + {MIPS_INS_MINI_S, "mini_s"}, + {MIPS_INS_MINI_U, "mini_u"}, + {MIPS_INS_MIN_A, "min_a"}, + {MIPS_INS_MIN, "min"}, + {MIPS_INS_MIN_S, "min_s"}, + {MIPS_INS_MIN_U, "min_u"}, + {MIPS_INS_MOD, "mod"}, + {MIPS_INS_MODSUB, "modsub"}, + {MIPS_INS_MODU, "modu"}, + {MIPS_INS_MOD_S, "mod_s"}, + {MIPS_INS_MOD_U, "mod_u"}, + {MIPS_INS_MOVE, "move"}, + {MIPS_INS_MOVEP, "movep"}, + {MIPS_INS_MOVF, "movf"}, + {MIPS_INS_MOVN, "movn"}, + {MIPS_INS_MOVT, "movt"}, + {MIPS_INS_MOVZ, "movz"}, + {MIPS_INS_MSUB, "msub"}, + {MIPS_INS_MSUBF, "msubf"}, + {MIPS_INS_MSUBR_Q, "msubr_q"}, + {MIPS_INS_MSUBU, "msubu"}, + {MIPS_INS_MSUBV, "msubv"}, + {MIPS_INS_MSUB_Q, "msub_q"}, + {MIPS_INS_MTC0, "mtc0"}, + {MIPS_INS_MTC1, "mtc1"}, + {MIPS_INS_MTC2, "mtc2"}, + {MIPS_INS_MTHC1, "mthc1"}, + {MIPS_INS_MTHI, "mthi"}, + {MIPS_INS_MTHLIP, "mthlip"}, + {MIPS_INS_MTLO, "mtlo"}, + {MIPS_INS_MTM0, "mtm0"}, + {MIPS_INS_MTM1, "mtm1"}, + {MIPS_INS_MTM2, "mtm2"}, + {MIPS_INS_MTP0, "mtp0"}, + {MIPS_INS_MTP1, "mtp1"}, + {MIPS_INS_MTP2, "mtp2"}, + {MIPS_INS_MUH, "muh"}, + {MIPS_INS_MUHU, "muhu"}, + {MIPS_INS_MULEQ_S, "muleq_s"}, + {MIPS_INS_MULEU_S, "muleu_s"}, + {MIPS_INS_MULQ_RS, "mulq_rs"}, + {MIPS_INS_MULQ_S, "mulq_s"}, + {MIPS_INS_MULR_Q, "mulr_q"}, + {MIPS_INS_MULSAQ_S, "mulsaq_s"}, + {MIPS_INS_MULSA, "mulsa"}, + {MIPS_INS_MULT, "mult"}, + {MIPS_INS_MULTU, "multu"}, + {MIPS_INS_MULU, "mulu"}, + {MIPS_INS_MULV, "mulv"}, + {MIPS_INS_MUL_Q, "mul_q"}, + {MIPS_INS_MUL_S, "mul_s"}, + {MIPS_INS_NLOC, "nloc"}, + {MIPS_INS_NLZC, "nlzc"}, + {MIPS_INS_NMADD, "nmadd"}, + {MIPS_INS_NMSUB, "nmsub"}, + {MIPS_INS_NOR, "nor"}, + {MIPS_INS_NORI, "nori"}, + {MIPS_INS_NOT16, "not16"}, + {MIPS_INS_NOT, "not"}, + {MIPS_INS_OR, "or"}, + {MIPS_INS_OR16, "or16"}, + {MIPS_INS_ORI, "ori"}, + {MIPS_INS_PACKRL, "packrl"}, + {MIPS_INS_PAUSE, "pause"}, + {MIPS_INS_PCKEV, "pckev"}, + {MIPS_INS_PCKOD, "pckod"}, + {MIPS_INS_PCNT, "pcnt"}, + {MIPS_INS_PICK, "pick"}, + {MIPS_INS_POP, "pop"}, + {MIPS_INS_PRECEQU, "precequ"}, + {MIPS_INS_PRECEQ, "preceq"}, + {MIPS_INS_PRECEU, "preceu"}, + {MIPS_INS_PRECRQU_S, "precrqu_s"}, + {MIPS_INS_PRECRQ, "precrq"}, + {MIPS_INS_PRECRQ_RS, "precrq_rs"}, + {MIPS_INS_PRECR, "precr"}, + {MIPS_INS_PRECR_SRA, "precr_sra"}, + {MIPS_INS_PRECR_SRA_R, "precr_sra_r"}, + {MIPS_INS_PREF, "pref"}, + {MIPS_INS_PREPEND, "prepend"}, + {MIPS_INS_RADDU, "raddu"}, + {MIPS_INS_RDDSP, "rddsp"}, + {MIPS_INS_RDHWR, "rdhwr"}, + {MIPS_INS_REPLV, "replv"}, + {MIPS_INS_REPL, "repl"}, + {MIPS_INS_RINT, "rint"}, + {MIPS_INS_ROTR, "rotr"}, + {MIPS_INS_ROTRV, "rotrv"}, + {MIPS_INS_ROUND, "round"}, + {MIPS_INS_SAT_S, "sat_s"}, + {MIPS_INS_SAT_U, "sat_u"}, + {MIPS_INS_SB, "sb"}, + {MIPS_INS_SB16, "sb16"}, + {MIPS_INS_SC, "sc"}, + {MIPS_INS_SCD, "scd"}, + {MIPS_INS_SD, "sd"}, + {MIPS_INS_SDBBP, "sdbbp"}, + {MIPS_INS_SDBBP16, "sdbbp16"}, + {MIPS_INS_SDC1, "sdc1"}, + {MIPS_INS_SDC2, "sdc2"}, + {MIPS_INS_SDC3, "sdc3"}, + {MIPS_INS_SDL, "sdl"}, + {MIPS_INS_SDR, "sdr"}, + {MIPS_INS_SDXC1, "sdxc1"}, + {MIPS_INS_SEB, "seb"}, + {MIPS_INS_SEH, "seh"}, + {MIPS_INS_SELEQZ, "seleqz"}, + {MIPS_INS_SELNEZ, "selnez"}, + {MIPS_INS_SEL, "sel"}, + {MIPS_INS_SEQ, "seq"}, + {MIPS_INS_SEQI, "seqi"}, + {MIPS_INS_SH, "sh"}, + {MIPS_INS_SH16, "sh16"}, + {MIPS_INS_SHF, "shf"}, + {MIPS_INS_SHILO, "shilo"}, + {MIPS_INS_SHILOV, "shilov"}, + {MIPS_INS_SHLLV, "shllv"}, + {MIPS_INS_SHLLV_S, "shllv_s"}, + {MIPS_INS_SHLL, "shll"}, + {MIPS_INS_SHLL_S, "shll_s"}, + {MIPS_INS_SHRAV, "shrav"}, + {MIPS_INS_SHRAV_R, "shrav_r"}, + {MIPS_INS_SHRA, "shra"}, + {MIPS_INS_SHRA_R, "shra_r"}, + {MIPS_INS_SHRLV, "shrlv"}, + {MIPS_INS_SHRL, "shrl"}, + {MIPS_INS_SLDI, "sldi"}, + {MIPS_INS_SLD, "sld"}, + {MIPS_INS_SLL, "sll"}, + {MIPS_INS_SLL16, "sll16"}, + {MIPS_INS_SLLI, "slli"}, + {MIPS_INS_SLLV, "sllv"}, + {MIPS_INS_SLT, "slt"}, + {MIPS_INS_SLTI, "slti"}, + {MIPS_INS_SLTIU, "sltiu"}, + {MIPS_INS_SLTU, "sltu"}, + {MIPS_INS_SNE, "sne"}, + {MIPS_INS_SNEI, "snei"}, + {MIPS_INS_SPLATI, "splati"}, + {MIPS_INS_SPLAT, "splat"}, + {MIPS_INS_SRA, "sra"}, + {MIPS_INS_SRAI, "srai"}, + {MIPS_INS_SRARI, "srari"}, + {MIPS_INS_SRAR, "srar"}, + {MIPS_INS_SRAV, "srav"}, + {MIPS_INS_SRL, "srl"}, + {MIPS_INS_SRL16, "srl16"}, + {MIPS_INS_SRLI, "srli"}, + {MIPS_INS_SRLRI, "srlri"}, + {MIPS_INS_SRLR, "srlr"}, + {MIPS_INS_SRLV, "srlv"}, + {MIPS_INS_SSNOP, "ssnop"}, + {MIPS_INS_ST, "st"}, + {MIPS_INS_SUBQH, "subqh"}, + {MIPS_INS_SUBQH_R, "subqh_r"}, + {MIPS_INS_SUBQ, "subq"}, + {MIPS_INS_SUBQ_S, "subq_s"}, + {MIPS_INS_SUBSUS_U, "subsus_u"}, + {MIPS_INS_SUBSUU_S, "subsuu_s"}, + {MIPS_INS_SUBS_S, "subs_s"}, + {MIPS_INS_SUBS_U, "subs_u"}, + {MIPS_INS_SUBU16, "subu16"}, + {MIPS_INS_SUBUH, "subuh"}, + {MIPS_INS_SUBUH_R, "subuh_r"}, + {MIPS_INS_SUBU, "subu"}, + {MIPS_INS_SUBU_S, "subu_s"}, + {MIPS_INS_SUBVI, "subvi"}, + {MIPS_INS_SUBV, "subv"}, + {MIPS_INS_SUXC1, "suxc1"}, + {MIPS_INS_SW, "sw"}, + {MIPS_INS_SW16, "sw16"}, + {MIPS_INS_SWC1, "swc1"}, + {MIPS_INS_SWC2, "swc2"}, + {MIPS_INS_SWC3, "swc3"}, + {MIPS_INS_SWL, "swl"}, + {MIPS_INS_SWM16, "swm16"}, + {MIPS_INS_SWM32, "swm32"}, + {MIPS_INS_SWP, "swp"}, + {MIPS_INS_SWR, "swr"}, + {MIPS_INS_SWXC1, "swxc1"}, + {MIPS_INS_SYNC, "sync"}, + {MIPS_INS_SYNCI, "synci"}, + {MIPS_INS_SYSCALL, "syscall"}, + {MIPS_INS_TEQ, "teq"}, + {MIPS_INS_TEQI, "teqi"}, + {MIPS_INS_TGE, "tge"}, + {MIPS_INS_TGEI, "tgei"}, + {MIPS_INS_TGEIU, "tgeiu"}, + {MIPS_INS_TGEU, "tgeu"}, + {MIPS_INS_TLBP, "tlbp"}, + {MIPS_INS_TLBR, "tlbr"}, + {MIPS_INS_TLBWI, "tlbwi"}, + {MIPS_INS_TLBWR, "tlbwr"}, + {MIPS_INS_TLT, "tlt"}, + {MIPS_INS_TLTI, "tlti"}, + {MIPS_INS_TLTIU, "tltiu"}, + {MIPS_INS_TLTU, "tltu"}, + {MIPS_INS_TNE, "tne"}, + {MIPS_INS_TNEI, "tnei"}, + {MIPS_INS_TRUNC, "trunc"}, + {MIPS_INS_V3MULU, "v3mulu"}, + {MIPS_INS_VMM0, "vmm0"}, + {MIPS_INS_VMULU, "vmulu"}, + {MIPS_INS_VSHF, "vshf"}, + {MIPS_INS_WAIT, "wait"}, + {MIPS_INS_WRDSP, "wrdsp"}, + {MIPS_INS_WSBH, "wsbh"}, + {MIPS_INS_XOR, "xor"}, + {MIPS_INS_XOR16, "xor16"}, + {MIPS_INS_XORI, "xori"}, - // alias instructions - { MIPS_INS_NOP, "nop" }, - { MIPS_INS_NEGU, "negu" }, - - { MIPS_INS_JALR_HB, "jalr.hb" }, - { MIPS_INS_JR_HB, "jr.hb" }, + // alias instructions + {MIPS_INS_NOP, "nop"}, + {MIPS_INS_NEGU, "negu"}, }; -const char *Mips_insn_name(csh handle, unsigned int id) -{ +const char *Mips_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - if (id >= MIPS_INS_ENDING) - return NULL; + if (id >= MIPS_INS_ENDING) + return NULL; - return insn_name_maps[id].name; + return insn_name_maps[id].name; #else - return NULL; + return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { - // generic groups - { MIPS_GRP_INVALID, NULL }, - { MIPS_GRP_JUMP, "jump" }, - { MIPS_GRP_CALL, "call" }, - { MIPS_GRP_RET, "ret" }, - { MIPS_GRP_INT, "int" }, - { MIPS_GRP_IRET, "iret" }, - { MIPS_GRP_PRIVILEGE, "privileged" }, - { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" }, + // generic groups + {MIPS_GRP_INVALID, NULL}, + {MIPS_GRP_JUMP, "jump"}, + {MIPS_GRP_CALL, "call"}, + {MIPS_GRP_RET, "ret"}, + {MIPS_GRP_INT, "int"}, + {MIPS_GRP_IRET, "iret"}, + {MIPS_GRP_PRIVILEGE, "privileged"}, + {MIPS_GRP_BRANCH_RELATIVE, "branch_relative"}, - // architecture-specific groups - { MIPS_GRP_BITCOUNT, "bitcount" }, - { MIPS_GRP_DSP, "dsp" }, - { MIPS_GRP_DSPR2, "dspr2" }, - { MIPS_GRP_FPIDX, "fpidx" }, - { MIPS_GRP_MSA, "msa" }, - { MIPS_GRP_MIPS32R2, "mips32r2" }, - { MIPS_GRP_MIPS64, "mips64" }, - { MIPS_GRP_MIPS64R2, "mips64r2" }, - { MIPS_GRP_SEINREG, "seinreg" }, - { MIPS_GRP_STDENC, "stdenc" }, - { MIPS_GRP_SWAP, "swap" }, - { MIPS_GRP_MICROMIPS, "micromips" }, - { MIPS_GRP_MIPS16MODE, "mips16mode" }, - { MIPS_GRP_FP64BIT, "fp64bit" }, - { MIPS_GRP_NONANSFPMATH, "nonansfpmath" }, - { MIPS_GRP_NOTFP64BIT, "notfp64bit" }, - { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" }, - { MIPS_GRP_NOTNACL, "notnacl" }, + // architecture-specific groups + {MIPS_GRP_BITCOUNT, "bitcount"}, + {MIPS_GRP_DSP, "dsp"}, + {MIPS_GRP_DSPR2, "dspr2"}, + {MIPS_GRP_FPIDX, "fpidx"}, + {MIPS_GRP_MSA, "msa"}, + {MIPS_GRP_MIPS32R2, "mips32r2"}, + {MIPS_GRP_MIPS64, "mips64"}, + {MIPS_GRP_MIPS64R2, "mips64r2"}, + {MIPS_GRP_SEINREG, "seinreg"}, + {MIPS_GRP_STDENC, "stdenc"}, + {MIPS_GRP_SWAP, "swap"}, + {MIPS_GRP_MICROMIPS, "micromips"}, + {MIPS_GRP_MIPS16MODE, "mips16mode"}, + {MIPS_GRP_FP64BIT, "fp64bit"}, + {MIPS_GRP_NONANSFPMATH, "nonansfpmath"}, + {MIPS_GRP_NOTFP64BIT, "notfp64bit"}, + {MIPS_GRP_NOTINMICROMIPS, "notinmicromips"}, + {MIPS_GRP_NOTNACL, "notnacl"}, - { MIPS_GRP_NOTMIPS32R6, "notmips32r6" }, - { MIPS_GRP_NOTMIPS64R6, "notmips64r6" }, - { MIPS_GRP_CNMIPS, "cnmips" }, + {MIPS_GRP_NOTMIPS32R6, "notmips32r6"}, + {MIPS_GRP_NOTMIPS64R6, "notmips64r6"}, + {MIPS_GRP_CNMIPS, "cnmips"}, - { MIPS_GRP_MIPS32, "mips32" }, - { MIPS_GRP_MIPS32R6, "mips32r6" }, - { MIPS_GRP_MIPS64R6, "mips64r6" }, + {MIPS_GRP_MIPS32, "mips32"}, + {MIPS_GRP_MIPS32R6, "mips32r6"}, + {MIPS_GRP_MIPS64R6, "mips64r6"}, - { MIPS_GRP_MIPS2, "mips2" }, - { MIPS_GRP_MIPS3, "mips3" }, - { MIPS_GRP_MIPS3_32, "mips3_32"}, - { MIPS_GRP_MIPS3_32R2, "mips3_32r2" }, + {MIPS_GRP_MIPS2, "mips2"}, + {MIPS_GRP_MIPS3, "mips3"}, + {MIPS_GRP_MIPS3_32, "mips3_32"}, + {MIPS_GRP_MIPS3_32R2, "mips3_32r2"}, - { MIPS_GRP_MIPS4_32, "mips4_32" }, - { MIPS_GRP_MIPS4_32R2, "mips4_32r2" }, - { MIPS_GRP_MIPS5_32R2, "mips5_32r2" }, + {MIPS_GRP_MIPS4_32, "mips4_32"}, + {MIPS_GRP_MIPS4_32R2, "mips4_32r2"}, + {MIPS_GRP_MIPS5_32R2, "mips5_32r2"}, - { MIPS_GRP_GP32BIT, "gp32bit" }, - { MIPS_GRP_GP64BIT, "gp64bit" }, + {MIPS_GRP_GP32BIT, "gp32bit"}, + {MIPS_GRP_GP64BIT, "gp64bit"}, }; #endif -const char *Mips_group_name(csh handle, unsigned int id) -{ +const char *Mips_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else - return NULL; + return NULL; #endif } // map instruction name to public instruction ID -mips_reg Mips_map_insn(const char *name) -{ - // handle special alias first - unsigned int i; +mips_reg Mips_map_insn(const char *name) { + // handle special alias first + unsigned int i; - // NOTE: skip first NULL name in insn_name_maps - i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + // NOTE: skip first NULL name in insn_name_maps + i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); - return (i != -1)? i : MIPS_REG_INVALID; + return (i != -1) ? i : MIPS_REG_INVALID; } // map internal raw register to 'public' register -mips_reg Mips_map_register(unsigned int r) -{ - // for some reasons different Mips modes can map different register number to - // the same Mips register. this function handles the issue for exposing Mips - // operands by mapping internal registers to 'public' register. - static const unsigned int map[] = { 0, - MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG, - MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2, - MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5, - MIPS_REG_3, MIPS_REG_7, MIPS_REG_PC, MIPS_REG_RA, MIPS_REG_SP, - MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, - MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT, - MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4, - MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1, - MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, - MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1, - MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, - MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, - MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, - MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, - MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, - MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, - MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, - MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, - MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, - MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, - MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4, - MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14, - MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24, - MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21, - MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, - MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, - MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, - MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, - MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, - MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, - MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0, - MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5, - MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, - MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, - MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, - MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, - MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, - MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, - MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP, - MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, - MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, - MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, - MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, - MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, - MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, - MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1, - MIPS_REG_AC2, MIPS_REG_AC3, 0, 0, 0, - 0, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, - MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, - MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, - MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, - MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, - MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0, - MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, - MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, - MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, - MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7, - MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, - MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, - MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1, - MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, - MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, - MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, - MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, - MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, - MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, - MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, - MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, - MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, - MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, - MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, - MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, - MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, - MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI, - MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1, - MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, - MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, - MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, - MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1 - }; +mips_reg Mips_map_register(unsigned int r) { + // for some reasons different Mips modes can map different register number to + // the same Mips register. this function handles the issue for exposing Mips + // operands by mapping internal registers to 'public' register. + static const unsigned int map_outer[] = { + 0, + Mips_AT, + Mips_DSPCCond, + Mips_DSPCarry, + Mips_DSPEFI, + Mips_DSPOutFlag, + Mips_DSPPos, + Mips_DSPSCount, + Mips_FP, + Mips_GP, + Mips_MSAAccess, + Mips_MSACSR, + Mips_MSAIR, + Mips_MSAMap, + Mips_MSAModify, + Mips_MSARequest, + Mips_MSASave, + Mips_MSAUnmap, + Mips_PC, + Mips_RA, + Mips_SP, + Mips_ZERO, + Mips_A0, + Mips_A1, + Mips_A2, + Mips_A3, + Mips_AC0, + Mips_AC1, + Mips_AC2, + Mips_AC3, + Mips_AT_64, + Mips_FCC0, + Mips_FCC1, + Mips_FCC2, + Mips_FCC3, + Mips_FCC4, + Mips_FCC5, + Mips_FCC6, + Mips_FCC7, + Mips_COP20, + Mips_COP21, + Mips_COP22, + Mips_COP23, + Mips_COP24, + Mips_COP25, + Mips_COP26, + Mips_COP27, + Mips_COP28, + Mips_COP29, + Mips_COP30, + Mips_COP31, + Mips_COP32, + Mips_COP33, + Mips_COP34, + Mips_COP35, + Mips_COP36, + Mips_COP37, + Mips_COP38, + Mips_COP39, + Mips_COP210, + Mips_COP211, + Mips_COP212, + Mips_COP213, + Mips_COP214, + Mips_COP215, + Mips_COP216, + Mips_COP217, + Mips_COP218, + Mips_COP219, + Mips_COP220, + Mips_COP221, + Mips_COP222, + Mips_COP223, + Mips_COP224, + Mips_COP225, + Mips_COP226, + Mips_COP227, + Mips_COP228, + Mips_COP229, + Mips_COP230, + Mips_COP231, + Mips_COP310, + Mips_COP311, + Mips_COP312, + Mips_COP313, + Mips_COP314, + Mips_COP315, + Mips_COP316, + Mips_COP317, + Mips_COP318, + Mips_COP319, + Mips_COP320, + Mips_COP321, + Mips_COP322, + Mips_COP323, + Mips_COP324, + Mips_COP325, + Mips_COP326, + Mips_COP327, + Mips_COP328, + Mips_COP329, + Mips_COP330, + Mips_COP331, + Mips_D0, + Mips_D1, + Mips_D2, + Mips_D3, + Mips_D4, + Mips_D5, + Mips_D6, + Mips_D7, + Mips_D8, + Mips_D9, + Mips_D10, + Mips_D11, + Mips_D12, + Mips_D13, + Mips_D14, + Mips_D15, + Mips_DSPOutFlag20, + Mips_DSPOutFlag21, + Mips_DSPOutFlag22, + Mips_DSPOutFlag23, + Mips_F0, + Mips_F1, + Mips_F2, + Mips_F3, + Mips_F4, + Mips_F5, + Mips_F6, + Mips_F7, + Mips_F8, + Mips_F9, + Mips_F10, + Mips_F11, + Mips_F12, + Mips_F13, + Mips_F14, + Mips_F15, + Mips_F16, + Mips_F17, + Mips_F18, + Mips_F19, + Mips_F20, + Mips_F21, + Mips_F22, + Mips_F23, + Mips_F24, + Mips_F25, + Mips_F26, + Mips_F27, + Mips_F28, + Mips_F29, + Mips_F30, + Mips_F31, + Mips_FCC0, + Mips_FCC1, + Mips_FCC2, + Mips_FCC3, + Mips_FCC4, + Mips_FCC5, + Mips_FCC6, + Mips_FCC7, + Mips_FCR0, + Mips_FCR1, + Mips_FCR2, + Mips_FCR3, + Mips_FCR4, + Mips_FCR5, + Mips_FCR6, + Mips_FCR7, + Mips_FCR8, + Mips_FCR9, + Mips_FCR10, + Mips_FCR11, + Mips_FCR12, + Mips_FCR13, + Mips_FCR14, + Mips_FCR15, + Mips_FCR16, + Mips_FCR17, + Mips_FCR18, + Mips_FCR19, + Mips_FCR20, + Mips_FCR21, + Mips_FCR22, + Mips_FCR23, + Mips_FCR24, + Mips_FCR25, + Mips_FCR26, + Mips_FCR27, + Mips_FCR28, + Mips_FCR29, + Mips_FCR30, + Mips_FCR31, + Mips_FP_64, + Mips_F_HI0, + Mips_F_HI1, + Mips_F_HI2, + Mips_F_HI3, + Mips_F_HI4, + Mips_F_HI5, + Mips_F_HI6, + Mips_F_HI7, + Mips_F_HI8, + Mips_F_HI9, + Mips_F_HI10, + Mips_F_HI11, + Mips_F_HI12, + Mips_F_HI13, + Mips_F_HI14, + Mips_F_HI15, + Mips_F_HI16, + Mips_F_HI17, + Mips_F_HI18, + Mips_F_HI19, + Mips_F_HI20, + Mips_F_HI21, + Mips_F_HI22, + Mips_F_HI23, + Mips_F_HI24, + Mips_F_HI25, + Mips_F_HI26, + Mips_F_HI27, + Mips_F_HI28, + Mips_F_HI29, + Mips_F_HI30, + Mips_F_HI31, + Mips_GP_64, + Mips_HI0, + Mips_HI1, + Mips_HI2, + Mips_HI3, + Mips_HWR0, + Mips_HWR1, + Mips_HWR2, + Mips_HWR3, + Mips_HWR4, + Mips_HWR5, + Mips_HWR6, + Mips_HWR7, + Mips_HWR8, + Mips_HWR9, + Mips_HWR10, + Mips_HWR11, + Mips_HWR12, + Mips_HWR13, + Mips_HWR14, + Mips_HWR15, + Mips_HWR16, + Mips_HWR17, + Mips_HWR18, + Mips_HWR19, + Mips_HWR20, + Mips_HWR21, + Mips_HWR22, + Mips_HWR23, + Mips_HWR24, + Mips_HWR25, + Mips_HWR26, + Mips_HWR27, + Mips_HWR28, + Mips_HWR29, + Mips_HWR30, + Mips_HWR31, + Mips_K0, + Mips_K1, + Mips_LO0, + Mips_LO1, + Mips_LO2, + Mips_LO3, + Mips_MPL0, + Mips_MPL1, + Mips_MPL2, + Mips_P0, + Mips_P1, + Mips_P2, + Mips_RA_64, + Mips_S0, + Mips_S1, + Mips_S2, + Mips_S3, + Mips_S4, + Mips_S5, + Mips_S6, + Mips_S7, + Mips_SP_64, + Mips_T0, + Mips_T1, + Mips_T2, + Mips_T3, + Mips_T4, + Mips_T5, + Mips_T6, + Mips_T7, + Mips_T8, + Mips_T9, + Mips_V0, + Mips_V1, + Mips_W0, + Mips_W1, + Mips_W2, + Mips_W3, + Mips_W4, + Mips_W5, + Mips_W6, + Mips_W7, + Mips_W8, + Mips_W9, + Mips_W10, + Mips_W11, + Mips_W12, + Mips_W13, + Mips_W14, + Mips_W15, + Mips_W16, + Mips_W17, + Mips_W18, + Mips_W19, + Mips_W20, + Mips_W21, + Mips_W22, + Mips_W23, + Mips_W24, + Mips_W25, + Mips_W26, + Mips_W27, + Mips_W28, + Mips_W29, + Mips_W30, + Mips_W31, + Mips_ZERO_64, + Mips_A0_64, + Mips_A1_64, + Mips_A2_64, + Mips_A3_64, + Mips_AC0_64, + Mips_D0_64, + Mips_D1_64, + Mips_D2_64, + Mips_D3_64, + Mips_D4_64, + Mips_D5_64, + Mips_D6_64, + Mips_D7_64, + Mips_D8_64, + Mips_D9_64, + Mips_D10_64, + Mips_D11_64, + Mips_D12_64, + Mips_D13_64, + Mips_D14_64, + Mips_D15_64, + Mips_D16_64, + Mips_D17_64, + Mips_D18_64, + Mips_D19_64, + Mips_D20_64, + Mips_D21_64, + Mips_D22_64, + Mips_D23_64, + Mips_D24_64, + Mips_D25_64, + Mips_D26_64, + Mips_D27_64, + Mips_D28_64, + Mips_D29_64, + Mips_D30_64, + Mips_D31_64, + Mips_DSPOutFlag16_19, + Mips_HI0_64, + Mips_K0_64, + Mips_K1_64, + Mips_LO0_64, + Mips_S0_64, + Mips_S1_64, + Mips_S2_64, + Mips_S3_64, + Mips_S4_64, + Mips_S5_64, + Mips_S6_64, + Mips_S7_64, + Mips_T0_64, + Mips_T1_64, + Mips_T2_64, + Mips_T3_64, + Mips_T4_64, + Mips_T5_64, + Mips_T6_64, + Mips_T7_64, + Mips_T8_64, + Mips_T9_64, + }; + + static const unsigned int map[] = {0, + MIPS_REG_AT, + MIPS_REG_DSPCCOND, + MIPS_REG_DSPCARRY, + MIPS_REG_DSPEFI, + MIPS_REG_DSPOUTFLAG, + MIPS_REG_DSPPOS, + MIPS_REG_DSPSCOUNT, + MIPS_REG_FP, + MIPS_REG_GP, + MIPS_REG_2, + MIPS_REG_1, + MIPS_REG_0, + MIPS_REG_6, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_3, + MIPS_REG_7, + MIPS_REG_PC, + MIPS_REG_RA, + MIPS_REG_SP, + MIPS_REG_ZERO, + MIPS_REG_A0, + MIPS_REG_A1, + MIPS_REG_A2, + MIPS_REG_A3, + MIPS_REG_AC0, + MIPS_REG_AC1, + MIPS_REG_AC2, + MIPS_REG_AC3, + MIPS_REG_AT, + MIPS_REG_CC0, + MIPS_REG_CC1, + MIPS_REG_CC2, + MIPS_REG_CC3, + MIPS_REG_CC4, + MIPS_REG_CC5, + MIPS_REG_CC6, + MIPS_REG_CC7, + MIPS_REG_0, + MIPS_REG_1, + MIPS_REG_2, + MIPS_REG_3, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_0, + MIPS_REG_1, + MIPS_REG_2, + MIPS_REG_3, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + MIPS_REG_F0, + MIPS_REG_F2, + MIPS_REG_F4, + MIPS_REG_F6, + MIPS_REG_F8, + MIPS_REG_F10, + MIPS_REG_F12, + MIPS_REG_F14, + MIPS_REG_F16, + MIPS_REG_F18, + MIPS_REG_F20, + MIPS_REG_F22, + MIPS_REG_F24, + MIPS_REG_F26, + MIPS_REG_F28, + MIPS_REG_F30, + MIPS_REG_DSPOUTFLAG20, + MIPS_REG_DSPOUTFLAG21, + MIPS_REG_DSPOUTFLAG22, + MIPS_REG_DSPOUTFLAG23, + MIPS_REG_F0, + MIPS_REG_F1, + MIPS_REG_F2, + MIPS_REG_F3, + MIPS_REG_F4, + MIPS_REG_F5, + MIPS_REG_F6, + MIPS_REG_F7, + MIPS_REG_F8, + MIPS_REG_F9, + MIPS_REG_F10, + MIPS_REG_F11, + MIPS_REG_F12, + MIPS_REG_F13, + MIPS_REG_F14, + MIPS_REG_F15, + MIPS_REG_F16, + MIPS_REG_F17, + MIPS_REG_F18, + MIPS_REG_F19, + MIPS_REG_F20, + MIPS_REG_F21, + MIPS_REG_F22, + MIPS_REG_F23, + MIPS_REG_F24, + MIPS_REG_F25, + MIPS_REG_F26, + MIPS_REG_F27, + MIPS_REG_F28, + MIPS_REG_F29, + MIPS_REG_F30, + MIPS_REG_F31, + MIPS_REG_FCC0, + MIPS_REG_FCC1, + MIPS_REG_FCC2, + MIPS_REG_FCC3, + MIPS_REG_FCC4, + MIPS_REG_FCC5, + MIPS_REG_FCC6, + MIPS_REG_FCC7, + MIPS_REG_0, + MIPS_REG_1, + MIPS_REG_2, + MIPS_REG_3, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + MIPS_REG_FP, + MIPS_REG_F0, + MIPS_REG_F1, + MIPS_REG_F2, + MIPS_REG_F3, + MIPS_REG_F4, + MIPS_REG_F5, + MIPS_REG_F6, + MIPS_REG_F7, + MIPS_REG_F8, + MIPS_REG_F9, + MIPS_REG_F10, + MIPS_REG_F11, + MIPS_REG_F12, + MIPS_REG_F13, + MIPS_REG_F14, + MIPS_REG_F15, + MIPS_REG_F16, + MIPS_REG_F17, + MIPS_REG_F18, + MIPS_REG_F19, + MIPS_REG_F20, + MIPS_REG_F21, + MIPS_REG_F22, + MIPS_REG_F23, + MIPS_REG_F24, + MIPS_REG_F25, + MIPS_REG_F26, + MIPS_REG_F27, + MIPS_REG_F28, + MIPS_REG_F29, + MIPS_REG_F30, + MIPS_REG_F31, + MIPS_REG_GP, + MIPS_REG_AC0, + MIPS_REG_AC1, + MIPS_REG_AC2, + MIPS_REG_AC3, + 0, + 0, + 0, + 0, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + MIPS_REG_K0, + MIPS_REG_K1, + MIPS_REG_AC0, + MIPS_REG_AC1, + MIPS_REG_AC2, + MIPS_REG_AC3, + MIPS_REG_MPL0, + MIPS_REG_MPL1, + MIPS_REG_MPL2, + MIPS_REG_P0, + MIPS_REG_P1, + MIPS_REG_P2, + MIPS_REG_RA, + MIPS_REG_S0, + MIPS_REG_S1, + MIPS_REG_S2, + MIPS_REG_S3, + MIPS_REG_S4, + MIPS_REG_S5, + MIPS_REG_S6, + MIPS_REG_S7, + MIPS_REG_SP, + MIPS_REG_T0, + MIPS_REG_T1, + MIPS_REG_T2, + MIPS_REG_T3, + MIPS_REG_T4, + MIPS_REG_T5, + MIPS_REG_T6, + MIPS_REG_T7, + MIPS_REG_T8, + MIPS_REG_T9, + MIPS_REG_V0, + MIPS_REG_V1, + MIPS_REG_W0, + MIPS_REG_W1, + MIPS_REG_W2, + MIPS_REG_W3, + MIPS_REG_W4, + MIPS_REG_W5, + MIPS_REG_W6, + MIPS_REG_W7, + MIPS_REG_W8, + MIPS_REG_W9, + MIPS_REG_W10, + MIPS_REG_W11, + MIPS_REG_W12, + MIPS_REG_W13, + MIPS_REG_W14, + MIPS_REG_W15, + MIPS_REG_W16, + MIPS_REG_W17, + MIPS_REG_W18, + MIPS_REG_W19, + MIPS_REG_W20, + MIPS_REG_W21, + MIPS_REG_W22, + MIPS_REG_W23, + MIPS_REG_W24, + MIPS_REG_W25, + MIPS_REG_W26, + MIPS_REG_W27, + MIPS_REG_W28, + MIPS_REG_W29, + MIPS_REG_W30, + MIPS_REG_W31, + MIPS_REG_ZERO, + MIPS_REG_A0, + MIPS_REG_A1, + MIPS_REG_A2, + MIPS_REG_A3, + MIPS_REG_AC0, + MIPS_REG_F0, + MIPS_REG_F1, + MIPS_REG_F2, + MIPS_REG_F3, + MIPS_REG_F4, + MIPS_REG_F5, + MIPS_REG_F6, + MIPS_REG_F7, + MIPS_REG_F8, + MIPS_REG_F9, + MIPS_REG_F10, + MIPS_REG_F11, + MIPS_REG_F12, + MIPS_REG_F13, + MIPS_REG_F14, + MIPS_REG_F15, + MIPS_REG_F16, + MIPS_REG_F17, + MIPS_REG_F18, + MIPS_REG_F19, + MIPS_REG_F20, + MIPS_REG_F21, + MIPS_REG_F22, + MIPS_REG_F23, + MIPS_REG_F24, + MIPS_REG_F25, + MIPS_REG_F26, + MIPS_REG_F27, + MIPS_REG_F28, + MIPS_REG_F29, + MIPS_REG_F30, + MIPS_REG_F31, + MIPS_REG_DSPOUTFLAG16_19, + MIPS_REG_HI, + MIPS_REG_K0, + MIPS_REG_K1, + MIPS_REG_LO, + MIPS_REG_S0, + MIPS_REG_S1, + MIPS_REG_S2, + MIPS_REG_S3, + MIPS_REG_S4, + MIPS_REG_S5, + MIPS_REG_S6, + MIPS_REG_S7, + MIPS_REG_T0, + MIPS_REG_T1, + MIPS_REG_T2, + MIPS_REG_T3, + MIPS_REG_T4, + MIPS_REG_T5, + MIPS_REG_T6, + MIPS_REG_T7, + MIPS_REG_T8, + MIPS_REG_T9, + MIPS_REG_V0, + MIPS_REG_V1}; - if (r < ARR_SIZE(map)) - return map[r]; + for (int i = 0; i < ARR_SIZE(map_outer); i++) + if (map_outer[i] == r) + return map[i]; - // cannot find this register - return 0; + // cannot find this register + return 0; } #endif diff --git a/arch/Mips/MipsMappingInsn.inc b/arch/Mips/MipsMappingInsn.inc deleted file mode 100644 index beb026c71e..0000000000 --- a/arch/Mips/MipsMappingInsn.inc +++ /dev/null @@ -1,9315 +0,0 @@ -// This is auto-gen data for Capstone engine (www.capstone-engine.org) -// By Nguyen Anh Quynh - -{ - Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ABSQ_S_W, MIPS_INS_ABSQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUPC, MIPS_INS_ADDIUPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUPC_MM, MIPS_INS_ADDIUPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUR1SP_MM, MIPS_INS_ADDIUR1SP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUR2_MM, MIPS_INS_ADDIUR2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUS5_MM, MIPS_INS_ADDIUS5, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDIUSP_MM, MIPS_INS_ADDIUSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQH_PH, MIPS_INS_ADDQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQH_R_W, MIPS_INS_ADDQH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQH_W, MIPS_INS_ADDQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQ_PH, MIPS_INS_ADDQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDQ_S_W, MIPS_INS_ADDQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDSC, MIPS_INS_ADDSC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_A_B, MIPS_INS_ADDS_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_A_D, MIPS_INS_ADDS_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_A_H, MIPS_INS_ADDS_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_A_W, MIPS_INS_ADDS_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_S_B, MIPS_INS_ADDS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_S_D, MIPS_INS_ADDS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_S_H, MIPS_INS_ADDS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_S_W, MIPS_INS_ADDS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_U_B, MIPS_INS_ADDS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_U_D, MIPS_INS_ADDS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_U_H, MIPS_INS_ADDS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDS_U_W, MIPS_INS_ADDS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU16_MM, MIPS_INS_ADDU16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDUH_QB, MIPS_INS_ADDUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU_PH, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU_QB, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU_S_PH, MIPS_INS_ADDU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDU_S_QB, MIPS_INS_ADDU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDVI_B, MIPS_INS_ADDVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDVI_D, MIPS_INS_ADDVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDVI_H, MIPS_INS_ADDVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDVI_W, MIPS_INS_ADDVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDV_B, MIPS_INS_ADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDV_D, MIPS_INS_ADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDV_H, MIPS_INS_ADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDV_W, MIPS_INS_ADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDWC, MIPS_INS_ADDWC, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_A_B, MIPS_INS_ADD_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_A_D, MIPS_INS_ADD_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_A_H, MIPS_INS_ADD_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_A_W, MIPS_INS_ADD_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ADD_MM, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDi, MIPS_INS_ADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDi_MM, MIPS_INS_ADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDiu, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDiu_MM, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDu, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ADDu_MM, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ALIGN, MIPS_INS_ALIGN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_ALUIPC, MIPS_INS_ALUIPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_AND, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_AND16_MM, MIPS_INS_AND16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_AND64, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDI16_MM, MIPS_INS_ANDI16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDI_B, MIPS_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AND_MM, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_AND_V, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDi, MIPS_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDi64, MIPS_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ANDi_MM, MIPS_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_APPEND, MIPS_INS_APPEND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_S_B, MIPS_INS_ASUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_S_D, MIPS_INS_ASUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_S_H, MIPS_INS_ASUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_S_W, MIPS_INS_ASUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_U_B, MIPS_INS_ASUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_U_D, MIPS_INS_ASUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_U_H, MIPS_INS_ASUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ASUB_U_W, MIPS_INS_ASUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AUI, MIPS_INS_AUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_AUIPC, MIPS_INS_AUIPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_S_B, MIPS_INS_AVER_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_S_D, MIPS_INS_AVER_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_S_H, MIPS_INS_AVER_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_S_W, MIPS_INS_AVER_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_U_B, MIPS_INS_AVER_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_U_D, MIPS_INS_AVER_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_U_H, MIPS_INS_AVER_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVER_U_W, MIPS_INS_AVER_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_S_B, MIPS_INS_AVE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_S_D, MIPS_INS_AVE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_S_H, MIPS_INS_AVE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_S_W, MIPS_INS_AVE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_U_B, MIPS_INS_AVE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_U_D, MIPS_INS_AVE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_U_H, MIPS_INS_AVE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AVE_U_W, MIPS_INS_AVE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxImmX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxRxImm16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuSpImm16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AddiuSpImmX16, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AdduRxRyRz16, MIPS_INS_ADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_AndRxRxRy16, MIPS_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_B16_MM, MIPS_INS_B16, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BADDu, MIPS_INS_BADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BAL, MIPS_INS_BAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BALC, MIPS_INS_BALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BALIGN, MIPS_INS_BALIGN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_BBIT0, MIPS_INS_BBIT0, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BBIT032, MIPS_INS_BBIT032, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BBIT1, MIPS_INS_BBIT1, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BBIT132, MIPS_INS_BBIT132, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BC, MIPS_INS_BC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC0F, MIPS_INS_BC0F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC0FL, MIPS_INS_BC0FL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC0T, MIPS_INS_BC0T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC0TL, MIPS_INS_BC0TL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1EQZ, MIPS_INS_BC1EQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1F, MIPS_INS_BC1F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1FL, MIPS_INS_BC1FL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1F_MM, MIPS_INS_BC1F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1NEZ, MIPS_INS_BC1NEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1T, MIPS_INS_BC1T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1TL, MIPS_INS_BC1TL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC1T_MM, MIPS_INS_BC1T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2EQZ, MIPS_INS_BC2EQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2F, MIPS_INS_BC2F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2FL, MIPS_INS_BC2FL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2NEZ, MIPS_INS_BC2NEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2T, MIPS_INS_BC2T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC2TL, MIPS_INS_BC2TL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC3F, MIPS_INS_BC3F, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC3FL, MIPS_INS_BC3FL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC3T, MIPS_INS_BC3T, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BC3TL, MIPS_INS_BC3TL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BCLRI_B, MIPS_INS_BCLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLRI_D, MIPS_INS_BCLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLRI_H, MIPS_INS_BCLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLRI_W, MIPS_INS_BCLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLR_B, MIPS_INS_BCLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLR_D, MIPS_INS_BCLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLR_H, MIPS_INS_BCLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BCLR_W, MIPS_INS_BCLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BEQ, MIPS_INS_BEQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQ64, MIPS_INS_BEQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQC, MIPS_INS_BEQC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQL, MIPS_INS_BEQL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQZ16_MM, MIPS_INS_BEQZ16, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQZALC, MIPS_INS_BEQZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQZC, MIPS_INS_BEQZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQZC_MM, MIPS_INS_BEQZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BEQ_MM, MIPS_INS_BEQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEC, MIPS_INS_BGEC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEUC, MIPS_INS_BGEUC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZ, MIPS_INS_BGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZ64, MIPS_INS_BGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZAL, MIPS_INS_BGEZAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BGEZALC, MIPS_INS_BGEZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZALL, MIPS_INS_BGEZALL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BGEZALS_MM, MIPS_INS_BGEZALS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BGEZAL_MM, MIPS_INS_BGEZAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BGEZC, MIPS_INS_BGEZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZL, MIPS_INS_BGEZL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGEZ_MM, MIPS_INS_BGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZ, MIPS_INS_BGTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZ64, MIPS_INS_BGTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZALC, MIPS_INS_BGTZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZC, MIPS_INS_BGTZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZL, MIPS_INS_BGTZL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BGTZ_MM, MIPS_INS_BGTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BINSLI_B, MIPS_INS_BINSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSLI_D, MIPS_INS_BINSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSLI_H, MIPS_INS_BINSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSLI_W, MIPS_INS_BINSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSL_B, MIPS_INS_BINSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSL_D, MIPS_INS_BINSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSL_H, MIPS_INS_BINSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSL_W, MIPS_INS_BINSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSRI_B, MIPS_INS_BINSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSRI_D, MIPS_INS_BINSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSRI_H, MIPS_INS_BINSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSRI_W, MIPS_INS_BINSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSR_B, MIPS_INS_BINSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSR_D, MIPS_INS_BINSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSR_H, MIPS_INS_BINSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BINSR_W, MIPS_INS_BINSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BITREV, MIPS_INS_BITREV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_BITSWAP, MIPS_INS_BITSWAP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BLEZ, MIPS_INS_BLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZ64, MIPS_INS_BLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZALC, MIPS_INS_BLEZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZC, MIPS_INS_BLEZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZL, MIPS_INS_BLEZL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLEZ_MM, MIPS_INS_BLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTC, MIPS_INS_BLTC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTUC, MIPS_INS_BLTUC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZ, MIPS_INS_BLTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZ64, MIPS_INS_BLTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZAL, MIPS_INS_BLTZAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BLTZALC, MIPS_INS_BLTZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZALL, MIPS_INS_BLTZALL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_BLTZALS_MM, MIPS_INS_BLTZALS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BLTZAL_MM, MIPS_INS_BLTZAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BLTZC, MIPS_INS_BLTZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZL, MIPS_INS_BLTZL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BLTZ_MM, MIPS_INS_BLTZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BMNZI_B, MIPS_INS_BMNZI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BMNZ_V, MIPS_INS_BMNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BMZI_B, MIPS_INS_BMZI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BMZ_V, MIPS_INS_BMZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNE, MIPS_INS_BNE, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BNE64, MIPS_INS_BNE, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEC, MIPS_INS_BNEC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEGI_B, MIPS_INS_BNEGI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEGI_D, MIPS_INS_BNEGI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEGI_H, MIPS_INS_BNEGI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEGI_W, MIPS_INS_BNEGI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEG_B, MIPS_INS_BNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEG_D, MIPS_INS_BNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEG_H, MIPS_INS_BNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEG_W, MIPS_INS_BNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BNEL, MIPS_INS_BNEL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEZ16_MM, MIPS_INS_BNEZ16, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEZALC, MIPS_INS_BNEZALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEZC, MIPS_INS_BNEZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNEZC_MM, MIPS_INS_BNEZC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BNE_MM, MIPS_INS_BNE, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 -#endif -}, -{ - Mips_BNVC, MIPS_INS_BNVC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_B, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_D, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_H, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_V, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BNZ_W, MIPS_INS_BNZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BOVC, MIPS_INS_BOVC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 -#endif -}, -{ - Mips_BPOSGE32, MIPS_INS_BPOSGE32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_DSP, 0 }, 1, 0 -#endif -}, -{ - Mips_BREAK, MIPS_INS_BREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_BREAK16_MM, MIPS_INS_BREAK16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BREAK_MM, MIPS_INS_BREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_BSELI_B, MIPS_INS_BSELI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSEL_V, MIPS_INS_BSEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSETI_B, MIPS_INS_BSETI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSETI_D, MIPS_INS_BSETI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSETI_H, MIPS_INS_BSETI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSETI_W, MIPS_INS_BSETI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSET_B, MIPS_INS_BSET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSET_D, MIPS_INS_BSET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSET_H, MIPS_INS_BSET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BSET_W, MIPS_INS_BSET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_BZ_B, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BZ_D, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BZ_H, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BZ_V, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BZ_W, MIPS_INS_BZ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 -#endif -}, -{ - Mips_BeqzRxImm16, MIPS_INS_BEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BeqzRxImmX16, MIPS_INS_BEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_Bimm16, MIPS_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BimmX16, MIPS_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BnezRxImm16, MIPS_INS_BNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BnezRxImmX16, MIPS_INS_BNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_Break16, MIPS_INS_BREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_Bteqz16, MIPS_INS_BTEQZ, -#ifndef CAPSTONE_DIET - { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BteqzX16, MIPS_INS_BTEQZ, -#ifndef CAPSTONE_DIET - { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_Btnez16, MIPS_INS_BTNEZ, -#ifndef CAPSTONE_DIET - { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_BtnezX16, MIPS_INS_BTNEZ, -#ifndef CAPSTONE_DIET - { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 -#endif -}, -{ - Mips_CACHE, MIPS_INS_CACHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CACHE_MM, MIPS_INS_CACHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CACHE_R6, MIPS_INS_CACHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_L_D64, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_L_S, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_D32, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_D64, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_MM, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_S, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_CEIL_W_S_MM, MIPS_INS_CEIL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQI_B, MIPS_INS_CEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQI_D, MIPS_INS_CEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQI_H, MIPS_INS_CEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQI_W, MIPS_INS_CEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQ_B, MIPS_INS_CEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQ_D, MIPS_INS_CEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQ_H, MIPS_INS_CEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CEQ_W, MIPS_INS_CEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CFC1, MIPS_INS_CFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_CFC1_MM, MIPS_INS_CFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CFCMSA, MIPS_INS_CFCMSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CINS, MIPS_INS_CINS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CINS32, MIPS_INS_CINS32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CLASS_D, MIPS_INS_CLASS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLASS_S, MIPS_INS_CLASS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_S_B, MIPS_INS_CLEI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_S_D, MIPS_INS_CLEI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_S_H, MIPS_INS_CLEI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_S_W, MIPS_INS_CLEI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_U_B, MIPS_INS_CLEI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_U_D, MIPS_INS_CLEI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_U_H, MIPS_INS_CLEI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLEI_U_W, MIPS_INS_CLEI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_S_B, MIPS_INS_CLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_S_D, MIPS_INS_CLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_S_H, MIPS_INS_CLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_S_W, MIPS_INS_CLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_U_B, MIPS_INS_CLE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_U_D, MIPS_INS_CLE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_U_H, MIPS_INS_CLE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLE_U_W, MIPS_INS_CLE_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLO, MIPS_INS_CLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLO_MM, MIPS_INS_CLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CLO_R6, MIPS_INS_CLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_S_B, MIPS_INS_CLTI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_S_D, MIPS_INS_CLTI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_S_H, MIPS_INS_CLTI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_S_W, MIPS_INS_CLTI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_U_B, MIPS_INS_CLTI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_U_D, MIPS_INS_CLTI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_U_H, MIPS_INS_CLTI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLTI_U_W, MIPS_INS_CLTI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_S_B, MIPS_INS_CLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_S_D, MIPS_INS_CLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_S_H, MIPS_INS_CLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_S_W, MIPS_INS_CLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_U_B, MIPS_INS_CLT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_U_D, MIPS_INS_CLT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_U_H, MIPS_INS_CLT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLT_U_W, MIPS_INS_CLT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CLZ, MIPS_INS_CLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CLZ_MM, MIPS_INS_CLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CLZ_R6, MIPS_INS_CLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGU_LE_QB, MIPS_INS_CMPGU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPGU_LT_QB, MIPS_INS_CMPGU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPU_EQ_QB, MIPS_INS_CMPU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPU_LE_QB, MIPS_INS_CMPU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMPU_LT_QB, MIPS_INS_CMPU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_EQ_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_EQ_PH, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_EQ_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_F_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_F_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LE_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LE_PH, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LE_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LT_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LT_PH, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_LT_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SAF_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SAF_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SEQ_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SEQ_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SLE_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SLE_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SLT_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SLT_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SUEQ_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SUEQ_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SULE_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SULE_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SULT_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SULT_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SUN_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_SUN_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_UEQ_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_UEQ_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_ULE_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_ULE_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_ULT_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_ULT_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_UN_D, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CMP_UN_S, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_S_B, MIPS_INS_COPY_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_S_D, MIPS_INS_COPY_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_S_H, MIPS_INS_COPY_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_S_W, MIPS_INS_COPY_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_U_B, MIPS_INS_COPY_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_U_D, MIPS_INS_COPY_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_U_H, MIPS_INS_COPY_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_COPY_U_W, MIPS_INS_COPY_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CTC1, MIPS_INS_CTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_CTC1_MM, MIPS_INS_CTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CTCMSA, MIPS_INS_CTCMSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D32_S, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D32_W, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D32_W_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D64_L, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D64_S, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D64_W, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_D_S_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_L_D64, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_L_D64_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_L_S, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_L_S_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_D32, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_D32_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_D64, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_L, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_W, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_S_W_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_D32, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_D64, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_S, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_CVT_W_S_MM, MIPS_INS_CVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_C_EQ_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_EQ_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_EQ_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_F_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_F_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_F_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LT_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LT_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_LT_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGLE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGLE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGLE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGL_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGL_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGL_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGT_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGT_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_NGT_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLT_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLT_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_OLT_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SEQ_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SEQ_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SEQ_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SF_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SF_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_SF_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UEQ_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UEQ_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UEQ_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULE_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULE_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULE_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULT_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULT_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_ULT_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UN_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UN_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_C_UN_S, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_CmpRxRy16, MIPS_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_CmpiRxImm16, MIPS_INS_CMPI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_CmpiRxImmX16, MIPS_INS_CMPI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_DADD, MIPS_INS_DADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DADDi, MIPS_INS_DADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DADDiu, MIPS_INS_DADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DADDu, MIPS_INS_DADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DAHI, MIPS_INS_DAHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DALIGN, MIPS_INS_DALIGN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DATI, MIPS_INS_DATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DAUI, MIPS_INS_DAUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DBITSWAP, MIPS_INS_DBITSWAP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DCLO, MIPS_INS_DCLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DCLO_R6, MIPS_INS_DCLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DCLZ, MIPS_INS_DCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DCLZ_R6, MIPS_INS_DCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DDIV, MIPS_INS_DDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DDIVU, MIPS_INS_DDIVU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DERET, MIPS_INS_DERET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 -#endif -}, -{ - Mips_DERET_MM, MIPS_INS_DERET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_DEXT, MIPS_INS_DEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DEXTM, MIPS_INS_DEXTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DEXTU, MIPS_INS_DEXTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DI, MIPS_INS_DI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DINS, MIPS_INS_DINS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DINSM, MIPS_INS_DINSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DINSU, MIPS_INS_DINSU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DIVU, MIPS_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_S_B, MIPS_INS_DIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_S_D, MIPS_INS_DIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_S_H, MIPS_INS_DIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_S_W, MIPS_INS_DIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_U_B, MIPS_INS_DIV_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_U_D, MIPS_INS_DIV_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_U_H, MIPS_INS_DIV_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DIV_U_W, MIPS_INS_DIV_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DI_MM, MIPS_INS_DI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_DLSA, MIPS_INS_DLSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DLSA_R6, MIPS_INS_DLSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMFC0, MIPS_INS_DMFC0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DMFC1, MIPS_INS_DMFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DMFC2, MIPS_INS_DMFC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DMOD, MIPS_INS_DMOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMODU, MIPS_INS_DMODU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMTC0, MIPS_INS_DMTC0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DMTC1, MIPS_INS_DMTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DMTC2, MIPS_INS_DMTC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_DMUH, MIPS_INS_DMUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMUHU, MIPS_INS_DMUHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMUL, MIPS_INS_DMUL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_DMULT, MIPS_INS_DMULT, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMULTu, MIPS_INS_DMULTU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMULU, MIPS_INS_DMULU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DMUL_R6, MIPS_INS_DMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_S_D, MIPS_INS_DOTP_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_S_H, MIPS_INS_DOTP_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_S_W, MIPS_INS_DOTP_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_U_D, MIPS_INS_DOTP_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_U_H, MIPS_INS_DOTP_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DOTP_U_W, MIPS_INS_DOTP_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_S_D, MIPS_INS_DPADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_S_H, MIPS_INS_DPADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_S_W, MIPS_INS_DPADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_U_D, MIPS_INS_DPADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_U_H, MIPS_INS_DPADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPADD_U_W, MIPS_INS_DPADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAU_H_QBL, MIPS_INS_DPAU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAU_H_QBR, MIPS_INS_DPAU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPAX_W_PH, MIPS_INS_DPAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPA_W_PH, MIPS_INS_DPA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPOP, MIPS_INS_DPOP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_S_D, MIPS_INS_DPSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_S_H, MIPS_INS_DPSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_S_W, MIPS_INS_DPSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_U_D, MIPS_INS_DPSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_U_H, MIPS_INS_DPSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSUB_U_W, MIPS_INS_DPSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSU_H_QBL, MIPS_INS_DPSU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSU_H_QBR, MIPS_INS_DPSU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_DPSX_W_PH, MIPS_INS_DPSX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DPS_W_PH, MIPS_INS_DPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_DROTR, MIPS_INS_DROTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DROTR32, MIPS_INS_DROTR32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DROTRV, MIPS_INS_DROTRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DSBH, MIPS_INS_DSBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DSDIV, MIPS_INS_DDIV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DSHD, MIPS_INS_DSHD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 -#endif -}, -{ - Mips_DSLL, MIPS_INS_DSLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSLL32, MIPS_INS_DSLL32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSLL64_32, MIPS_INS_DSLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_DSLLV, MIPS_INS_DSLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRA, MIPS_INS_DSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRA32, MIPS_INS_DSRA32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRAV, MIPS_INS_DSRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRL, MIPS_INS_DSRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRL32, MIPS_INS_DSRL32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSRLV, MIPS_INS_DSRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSUB, MIPS_INS_DSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DSUBu, MIPS_INS_DSUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_DUDIV, MIPS_INS_DDIVU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_DivRxRy16, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_DivuRxRy16, MIPS_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_EHB, MIPS_INS_EHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_EHB_MM, MIPS_INS_EHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_EI, MIPS_INS_EI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_EI_MM, MIPS_INS_EI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ERET, MIPS_INS_ERET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, 0 }, 0, 0 -#endif -}, -{ - Mips_ERET_MM, MIPS_INS_ERET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_EXT, MIPS_INS_EXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTP, MIPS_INS_EXTP, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTPDP, MIPS_INS_EXTPDP, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTPDPV, MIPS_INS_EXTPDPV, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTPV, MIPS_INS_EXTPV, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTRV_R_W, MIPS_INS_EXTRV_R, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTRV_S_H, MIPS_INS_EXTRV_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTRV_W, MIPS_INS_EXTRV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTR_RS_W, MIPS_INS_EXTR_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTR_R_W, MIPS_INS_EXTR_R, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTR_S_H, MIPS_INS_EXTR_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTR_W, MIPS_INS_EXTR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTS, MIPS_INS_EXTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_EXTS32, MIPS_INS_EXTS32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_EXT_MM, MIPS_INS_EXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_D32, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_D64, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_MM, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_S, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FABS_S_MM, MIPS_INS_ABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_D, MIPS_INS_FADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_D32, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_D64, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_MM, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_S, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_S_MM, MIPS_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FADD_W, MIPS_INS_FADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCAF_D, MIPS_INS_FCAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCAF_W, MIPS_INS_FCAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCEQ_D, MIPS_INS_FCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCEQ_W, MIPS_INS_FCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLASS_D, MIPS_INS_FCLASS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLASS_W, MIPS_INS_FCLASS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLE_D, MIPS_INS_FCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLE_W, MIPS_INS_FCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLT_D, MIPS_INS_FCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCLT_W, MIPS_INS_FCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_D32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_D32_MM, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_D64, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_S32, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_FCMP_S32_MM, MIPS_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FCNE_D, MIPS_INS_FCNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCNE_W, MIPS_INS_FCNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCOR_D, MIPS_INS_FCOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCOR_W, MIPS_INS_FCOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUEQ_D, MIPS_INS_FCUEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUEQ_W, MIPS_INS_FCUEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCULE_D, MIPS_INS_FCULE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCULE_W, MIPS_INS_FCULE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCULT_D, MIPS_INS_FCULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCULT_W, MIPS_INS_FCULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUNE_D, MIPS_INS_FCUNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUNE_W, MIPS_INS_FCUNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUN_D, MIPS_INS_FCUN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FCUN_W, MIPS_INS_FCUN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_D, MIPS_INS_FDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_D32, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_D64, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_MM, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_S, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_S_MM, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FDIV_W, MIPS_INS_FDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXDO_H, MIPS_INS_FEXDO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXDO_W, MIPS_INS_FEXDO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXP2_D, MIPS_INS_FEXP2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXP2_W, MIPS_INS_FEXP2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXUPL_D, MIPS_INS_FEXUPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXUPL_W, MIPS_INS_FEXUPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXUPR_D, MIPS_INS_FEXUPR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FEXUPR_W, MIPS_INS_FEXUPR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFINT_S_D, MIPS_INS_FFINT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFINT_S_W, MIPS_INS_FFINT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFINT_U_D, MIPS_INS_FFINT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFINT_U_W, MIPS_INS_FFINT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFQL_D, MIPS_INS_FFQL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFQL_W, MIPS_INS_FFQL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFQR_D, MIPS_INS_FFQR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FFQR_W, MIPS_INS_FFQR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FILL_B, MIPS_INS_FILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FILL_D, MIPS_INS_FILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_FILL_H, MIPS_INS_FILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FILL_W, MIPS_INS_FILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOG2_D, MIPS_INS_FLOG2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOG2_W, MIPS_INS_FLOG2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_L_D64, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_L_S, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_D32, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_D64, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_MM, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_S, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMADD_D, MIPS_INS_FMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMADD_W, MIPS_INS_FMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMAX_A_D, MIPS_INS_FMAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMAX_A_W, MIPS_INS_FMAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMAX_D, MIPS_INS_FMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMAX_W, MIPS_INS_FMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMIN_A_D, MIPS_INS_FMIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMIN_A_W, MIPS_INS_FMIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMIN_D, MIPS_INS_FMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMIN_W, MIPS_INS_FMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_D32, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_D32_MM, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_D64, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_S, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FMOV_S_MM, MIPS_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMSUB_D, MIPS_INS_FMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMSUB_W, MIPS_INS_FMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_D, MIPS_INS_FMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_D32, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_D64, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_MM, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_S, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_S_MM, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FMUL_W, MIPS_INS_FMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_D32, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_D64, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_MM, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_S, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FNEG_S_MM, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FRCP_D, MIPS_INS_FRCP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRCP_W, MIPS_INS_FRCP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRINT_D, MIPS_INS_FRINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRINT_W, MIPS_INS_FRINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRSQRT_D, MIPS_INS_FRSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FRSQRT_W, MIPS_INS_FRSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSAF_D, MIPS_INS_FSAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSAF_W, MIPS_INS_FSAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSEQ_D, MIPS_INS_FSEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSEQ_W, MIPS_INS_FSEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSLE_D, MIPS_INS_FSLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSLE_W, MIPS_INS_FSLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSLT_D, MIPS_INS_FSLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSLT_W, MIPS_INS_FSLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSNE_D, MIPS_INS_FSNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSNE_W, MIPS_INS_FSNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSOR_D, MIPS_INS_FSOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSOR_W, MIPS_INS_FSOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_D, MIPS_INS_FSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_D32, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_D64, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_MM, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_S, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_S_MM, MIPS_INS_SQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FSQRT_W, MIPS_INS_FSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_D, MIPS_INS_FSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_D32, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_D64, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_MM, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_S, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_S_MM, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUB_W, MIPS_INS_FSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUEQ_D, MIPS_INS_FSUEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUEQ_W, MIPS_INS_FSUEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSULE_D, MIPS_INS_FSULE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSULE_W, MIPS_INS_FSULE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSULT_D, MIPS_INS_FSULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSULT_W, MIPS_INS_FSULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUNE_D, MIPS_INS_FSUNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUNE_W, MIPS_INS_FSUNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUN_D, MIPS_INS_FSUN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FSUN_W, MIPS_INS_FSUN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTINT_S_D, MIPS_INS_FTINT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTINT_S_W, MIPS_INS_FTINT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTINT_U_D, MIPS_INS_FTINT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTINT_U_W, MIPS_INS_FTINT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTQ_H, MIPS_INS_FTQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTQ_W, MIPS_INS_FTQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_S_D, MIPS_INS_HADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_S_H, MIPS_INS_HADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_S_W, MIPS_INS_HADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_U_D, MIPS_INS_HADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_U_H, MIPS_INS_HADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HADD_U_W, MIPS_INS_HADD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_S_D, MIPS_INS_HSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_S_H, MIPS_INS_HSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_S_W, MIPS_INS_HSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_U_D, MIPS_INS_HSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_U_H, MIPS_INS_HSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_HSUB_U_W, MIPS_INS_HSUB_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVEV_B, MIPS_INS_ILVEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVEV_D, MIPS_INS_ILVEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVEV_H, MIPS_INS_ILVEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVEV_W, MIPS_INS_ILVEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVL_B, MIPS_INS_ILVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVL_D, MIPS_INS_ILVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVL_H, MIPS_INS_ILVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVL_W, MIPS_INS_ILVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVOD_B, MIPS_INS_ILVOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVOD_D, MIPS_INS_ILVOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVOD_H, MIPS_INS_ILVOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVOD_W, MIPS_INS_ILVOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVR_B, MIPS_INS_ILVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVR_D, MIPS_INS_ILVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVR_H, MIPS_INS_ILVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ILVR_W, MIPS_INS_ILVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INS, MIPS_INS_INS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_INSERT_B, MIPS_INS_INSERT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSERT_D, MIPS_INS_INSERT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_INSERT_H, MIPS_INS_INSERT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSERT_W, MIPS_INS_INSERT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSV, MIPS_INS_INSV, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_INSVE_B, MIPS_INS_INSVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSVE_D, MIPS_INS_INSVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSVE_H, MIPS_INS_INSVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INSVE_W, MIPS_INS_INSVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_INS_MM, MIPS_INS_INS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_J, MIPS_INS_J, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 -#endif -}, -{ - Mips_JAL, MIPS_INS_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_JALR, MIPS_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALR16_MM, MIPS_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALR64, MIPS_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALRS16_MM, MIPS_INS_JALRS16, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALRS_MM, MIPS_INS_JALRS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALR_HB, MIPS_INS_JALR_HB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_CALL, 0 }, 0, 1 -#endif -}, -{ - Mips_JALR_MM, MIPS_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_JALS_MM, MIPS_INS_JALS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_JALX, MIPS_INS_JALX, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_JALX_MM, MIPS_INS_JALX, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_JAL_MM, MIPS_INS_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_JIALC, MIPS_INS_JIALC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_JIC, MIPS_INS_JIC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_JR, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 -#endif -}, -{ - Mips_JR16_MM, MIPS_INS_JR16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 -#endif -}, -{ - Mips_JR64, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 -#endif -}, -{ - Mips_JRADDIUSP, MIPS_INS_JRADDIUSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 -#endif -}, -{ - Mips_JRC16_MM, MIPS_INS_JRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 -#endif -}, -{ - Mips_JR_HB, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1 -#endif -}, -{ - Mips_JR_HB_R6, MIPS_INS_JR_HB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1 -#endif -}, -{ - Mips_JR_MM, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 -#endif -}, -{ - Mips_J_MM, MIPS_INS_J, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_Jal16, MIPS_INS_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_JrRa16, MIPS_INS_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 -#endif -}, -{ - Mips_JrcRa16, MIPS_INS_JRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 -#endif -}, -{ - Mips_JrcRx16, MIPS_INS_JRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 -#endif -}, -{ - Mips_JumpLinkReg16, MIPS_INS_JALRC, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, MIPS_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - Mips_LB, MIPS_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LB64, MIPS_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LBU16_MM, MIPS_INS_LBU16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LBUX, MIPS_INS_LBUX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_LB_MM, MIPS_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LBu, MIPS_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LBu64, MIPS_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LBu_MM, MIPS_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LD, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC1, MIPS_INS_LDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC164, MIPS_INS_LDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC1_MM, MIPS_INS_LDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC2, MIPS_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC2_R6, MIPS_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LDC3, MIPS_INS_LDC3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LDI_B, MIPS_INS_LDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LDI_D, MIPS_INS_LDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LDI_H, MIPS_INS_LDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LDI_W, MIPS_INS_LDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LDL, MIPS_INS_LDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LDPC, MIPS_INS_LDPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LDR, MIPS_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LDXC1, MIPS_INS_LDXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_LDXC164, MIPS_INS_LDXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LD_B, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LD_D, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LD_H, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LD_W, MIPS_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LEA_ADDiu, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LEA_ADDiu64, MIPS_INS_DADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LH, MIPS_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LH64, MIPS_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LHU16_MM, MIPS_INS_LHU16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LHX, MIPS_INS_LHX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_LH_MM, MIPS_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LHu, MIPS_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LHu64, MIPS_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LHu_MM, MIPS_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LI16_MM, MIPS_INS_LI16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LL, MIPS_INS_LL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LLD, MIPS_INS_LLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LLD_R6, MIPS_INS_LLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LL_MM, MIPS_INS_LL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LL_R6, MIPS_INS_LL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LSA, MIPS_INS_LSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_LSA_R6, MIPS_INS_LSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LUXC1, MIPS_INS_LUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_LUXC164, MIPS_INS_LUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LUXC1_MM, MIPS_INS_LUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LUi, MIPS_INS_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LUi64, MIPS_INS_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LUi_MM, MIPS_INS_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LW, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LW16_MM, MIPS_INS_LW16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LW64, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC1, MIPS_INS_LWC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC1_MM, MIPS_INS_LWC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC2, MIPS_INS_LWC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC2_R6, MIPS_INS_LWC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LWC3, MIPS_INS_LWC3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWGP_MM, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWL, MIPS_INS_LWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWL64, MIPS_INS_LWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LWL_MM, MIPS_INS_LWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWM16_MM, MIPS_INS_LWM16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWM32_MM, MIPS_INS_LWM32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWPC, MIPS_INS_LWPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LWP_MM, MIPS_INS_LWP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWR, MIPS_INS_LWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWR64, MIPS_INS_LWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_LWR_MM, MIPS_INS_LWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWSP_MM, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWUPC, MIPS_INS_LWUPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_LWU_MM, MIPS_INS_LWU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWX, MIPS_INS_LWX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_LWXC1, MIPS_INS_LWXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_LWXC1_MM, MIPS_INS_LWXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWXS_MM, MIPS_INS_LWXS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LW_MM, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_LWu, MIPS_INS_LWU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_LbRxRyOffMemX16, MIPS_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LbuRxRyOffMemX16, MIPS_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LhRxRyOffMemX16, MIPS_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LhuRxRyOffMemX16, MIPS_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LiRxImm16, MIPS_INS_LI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LiRxImmX16, MIPS_INS_LI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LwRxPcTcp16, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LwRxPcTcpX16, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LwRxRyOffMemX16, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_LwRxSpImmX16, MIPS_INS_LW, -#ifndef CAPSTONE_DIET - { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDF_D, MIPS_INS_MADDF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDF_S, MIPS_INS_MADDF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDR_Q_H, MIPS_INS_MADDR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDR_Q_W, MIPS_INS_MADDR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDU, MIPS_INS_MADDU, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDU_DSP, MIPS_INS_MADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDU_MM, MIPS_INS_MADDU, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDV_B, MIPS_INS_MADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDV_D, MIPS_INS_MADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDV_H, MIPS_INS_MADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADDV_W, MIPS_INS_MADDV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_D32, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_D32_MM, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_D64, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_DSP, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_MM, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_Q_H, MIPS_INS_MADD_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_Q_W, MIPS_INS_MADD_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_S, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MADD_S_MM, MIPS_INS_MADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXA_D, MIPS_INS_MAXA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXA_S, MIPS_INS_MAXA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_S_B, MIPS_INS_MAXI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_S_D, MIPS_INS_MAXI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_S_H, MIPS_INS_MAXI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_S_W, MIPS_INS_MAXI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_U_B, MIPS_INS_MAXI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_U_D, MIPS_INS_MAXI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_U_H, MIPS_INS_MAXI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAXI_U_W, MIPS_INS_MAXI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_A_B, MIPS_INS_MAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_A_D, MIPS_INS_MAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_A_H, MIPS_INS_MAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_A_W, MIPS_INS_MAX_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_D, MIPS_INS_MAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S, MIPS_INS_MAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S_B, MIPS_INS_MAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S_D, MIPS_INS_MAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S_H, MIPS_INS_MAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_S_W, MIPS_INS_MAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_U_B, MIPS_INS_MAX_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_U_D, MIPS_INS_MAX_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_U_H, MIPS_INS_MAX_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MAX_U_W, MIPS_INS_MAX_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MFC0, MIPS_INS_MFC0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 -#endif -}, -{ - Mips_MFC1, MIPS_INS_MFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_MFC1_MM, MIPS_INS_MFC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFC2, MIPS_INS_MFC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHC1_D32, MIPS_INS_MFHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHC1_D64, MIPS_INS_MFHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHC1_MM, MIPS_INS_MFHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI16_MM, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI64, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI_DSP, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MFHI_MM, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO16_MM, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO64, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO_DSP, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MFLO_MM, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MINA_D, MIPS_INS_MINA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MINA_S, MIPS_INS_MINA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_S_B, MIPS_INS_MINI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_S_D, MIPS_INS_MINI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_S_H, MIPS_INS_MINI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_S_W, MIPS_INS_MINI_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_U_B, MIPS_INS_MINI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_U_D, MIPS_INS_MINI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_U_H, MIPS_INS_MINI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MINI_U_W, MIPS_INS_MINI_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_A_B, MIPS_INS_MIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_A_D, MIPS_INS_MIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_A_H, MIPS_INS_MIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_A_W, MIPS_INS_MIN_A, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_D, MIPS_INS_MIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S, MIPS_INS_MIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S_B, MIPS_INS_MIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S_D, MIPS_INS_MIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S_H, MIPS_INS_MIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_S_W, MIPS_INS_MIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_U_B, MIPS_INS_MIN_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_U_D, MIPS_INS_MIN_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_U_H, MIPS_INS_MIN_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MIN_U_W, MIPS_INS_MIN_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD, MIPS_INS_MOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MODSUB, MIPS_INS_MODSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MODU, MIPS_INS_MODU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_S_B, MIPS_INS_MOD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_S_D, MIPS_INS_MOD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_S_H, MIPS_INS_MOD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_S_W, MIPS_INS_MOD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_U_B, MIPS_INS_MOD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_U_D, MIPS_INS_MOD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_U_H, MIPS_INS_MOD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOD_U_W, MIPS_INS_MOD_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVE16_MM, MIPS_INS_MOVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVEP_MM, MIPS_INS_MOVEP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVE_V, MIPS_INS_MOVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_D32, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_D32_MM, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_D64, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_I, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_I64, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_I_MM, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_S, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVF_S_MM, MIPS_INS_MOVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I64_D64, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I64_I, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I64_I64, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I64_S, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_D32, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_D32_MM, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_D64, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_I, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_I64, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_MM, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_S, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVN_I_S_MM, MIPS_INS_MOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_D32, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_D32_MM, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_D64, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_I, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_I64, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_I_MM, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_S, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVT_S_MM, MIPS_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I64_D64, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I64_I, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I64_I64, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I64_S, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_MIPS64, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_D32, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_D64, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_I, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_I64, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_MM, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_S, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBF_D, MIPS_INS_MSUBF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBF_S, MIPS_INS_MSUBF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBU, MIPS_INS_MSUBU, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBU_DSP, MIPS_INS_MSUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBU_MM, MIPS_INS_MSUBU, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBV_B, MIPS_INS_MSUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBV_D, MIPS_INS_MSUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBV_H, MIPS_INS_MSUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUBV_W, MIPS_INS_MSUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_D32, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_D32_MM, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_D64, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_DSP, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_MM, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_Q_H, MIPS_INS_MSUB_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_Q_W, MIPS_INS_MSUB_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_S, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MSUB_S_MM, MIPS_INS_MSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTC0, MIPS_INS_MTC0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 -#endif -}, -{ - Mips_MTC1, MIPS_INS_MTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_MTC1_MM, MIPS_INS_MTC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTC2, MIPS_INS_MTC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHC1_D32, MIPS_INS_MTHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHC1_D64, MIPS_INS_MTHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHC1_MM, MIPS_INS_MTHC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHI, MIPS_INS_MTHI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHI64, MIPS_INS_MTHI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHI_DSP, MIPS_INS_MTHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHI_MM, MIPS_INS_MTHI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTHLIP, MIPS_INS_MTHLIP, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MTLO, MIPS_INS_MTLO, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MTLO64, MIPS_INS_MTLO, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MTLO_DSP, MIPS_INS_MTLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MTLO_MM, MIPS_INS_MTLO, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTM0, MIPS_INS_MTM0, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTM1, MIPS_INS_MTM1, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTM2, MIPS_INS_MTM2, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTP0, MIPS_INS_MTP0, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_P0, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTP1, MIPS_INS_MTP1, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_P1, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MTP2, MIPS_INS_MTP2, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MUH, MIPS_INS_MUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MUHU, MIPS_INS_MUHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULQ_RS_W, MIPS_INS_MULQ_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MULQ_S_PH, MIPS_INS_MULQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MULQ_S_W, MIPS_INS_MULQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MULR_Q_H, MIPS_INS_MULR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULR_Q_W, MIPS_INS_MULR_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULSA_W_PH, MIPS_INS_MULSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MULT, MIPS_INS_MULT, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MULTU_DSP, MIPS_INS_MULTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULT_DSP, MIPS_INS_MULT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_MULT_MM, MIPS_INS_MULT, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MULTu, MIPS_INS_MULTU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MULTu_MM, MIPS_INS_MULTU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MULU, MIPS_INS_MULU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MULV_B, MIPS_INS_MULV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULV_D, MIPS_INS_MULV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULV_H, MIPS_INS_MULV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MULV_W, MIPS_INS_MULV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_MM, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_PH, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_Q_H, MIPS_INS_MUL_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_Q_W, MIPS_INS_MUL_Q, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_R6, MIPS_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_MUL_S_PH, MIPS_INS_MUL_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_Mfhi16, MIPS_INS_MFHI, -#ifndef CAPSTONE_DIET - { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_Mflo16, MIPS_INS_MFLO, -#ifndef CAPSTONE_DIET - { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_Move32R16, MIPS_INS_MOVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_MoveR3216, MIPS_INS_MOVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_NLOC_B, MIPS_INS_NLOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLOC_D, MIPS_INS_NLOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLOC_H, MIPS_INS_NLOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLOC_W, MIPS_INS_NLOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLZC_B, MIPS_INS_NLZC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLZC_D, MIPS_INS_NLZC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLZC_H, MIPS_INS_NLZC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NLZC_W, MIPS_INS_NLZC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_D32, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_D32_MM, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_D64, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_S, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMADD_S_MM, MIPS_INS_NMADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_D32, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_D32_MM, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_D64, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_S, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 -#endif -}, -{ - Mips_NMSUB_S_MM, MIPS_INS_NMSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NOR, MIPS_INS_NOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_NOR64, MIPS_INS_NOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_NORI_B, MIPS_INS_NORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NOR_MM, MIPS_INS_NOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NOR_V, MIPS_INS_NOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_NOT16_MM, MIPS_INS_NOT16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_NegRxRy16, MIPS_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_NotRxRy16, MIPS_INS_NOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_OR, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_OR16_MM, MIPS_INS_OR16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_OR64, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ORI_B, MIPS_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_OR_MM, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_OR_V, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ORi, MIPS_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ORi64, MIPS_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_ORi_MM, MIPS_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_OrRxRxRy16, MIPS_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_PACKRL_PH, MIPS_INS_PACKRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PAUSE, MIPS_INS_PAUSE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_PAUSE_MM, MIPS_INS_PAUSE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKEV_B, MIPS_INS_PCKEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKEV_D, MIPS_INS_PCKEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKEV_H, MIPS_INS_PCKEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKEV_W, MIPS_INS_PCKEV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKOD_B, MIPS_INS_PCKOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKOD_D, MIPS_INS_PCKOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKOD_H, MIPS_INS_PCKOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCKOD_W, MIPS_INS_PCKOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCNT_B, MIPS_INS_PCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCNT_D, MIPS_INS_PCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCNT_H, MIPS_INS_PCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PCNT_W, MIPS_INS_PCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_PICK_PH, MIPS_INS_PICK, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PICK_QB, MIPS_INS_PICK, -#ifndef CAPSTONE_DIET - { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_POP, MIPS_INS_POP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECR_QB_PH, MIPS_INS_PRECR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_PREF, MIPS_INS_PREF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_PREF_MM, MIPS_INS_PREF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_PREF_R6, MIPS_INS_PREF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_PREPEND, MIPS_INS_PREPEND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_RADDU_W_QB, MIPS_INS_RADDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_RDDSP, MIPS_INS_RDDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_RDHWR, MIPS_INS_RDHWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_RDHWR64, MIPS_INS_RDHWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_RDHWR_MM, MIPS_INS_RDHWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_REPLV_PH, MIPS_INS_REPLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_REPLV_QB, MIPS_INS_REPLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_REPL_PH, MIPS_INS_REPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_REPL_QB, MIPS_INS_REPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_RINT_D, MIPS_INS_RINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_RINT_S, MIPS_INS_RINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_ROTR, MIPS_INS_ROTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_ROTRV, MIPS_INS_ROTRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_ROTRV_MM, MIPS_INS_ROTRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ROTR_MM, MIPS_INS_ROTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_L_D64, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_L_S, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_D32, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_D64, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_MM, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_S, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_ROUND_W_S_MM, MIPS_INS_ROUND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_S_B, MIPS_INS_SAT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_S_D, MIPS_INS_SAT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_S_H, MIPS_INS_SAT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_S_W, MIPS_INS_SAT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_U_B, MIPS_INS_SAT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_U_D, MIPS_INS_SAT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_U_H, MIPS_INS_SAT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SAT_U_W, MIPS_INS_SAT_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SB, MIPS_INS_SB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SB16_MM, MIPS_INS_SB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SB64, MIPS_INS_SB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SB_MM, MIPS_INS_SB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SC, MIPS_INS_SC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SCD, MIPS_INS_SCD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SCD_R6, MIPS_INS_SCD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SC_MM, MIPS_INS_SC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SC_R6, MIPS_INS_SC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SD, MIPS_INS_SD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 -#endif -}, -{ - Mips_SDBBP, MIPS_INS_SDBBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDBBP16_MM, MIPS_INS_SDBBP16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDBBP_MM, MIPS_INS_SDBBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDBBP_R6, MIPS_INS_SDBBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC1, MIPS_INS_SDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC164, MIPS_INS_SDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC1_MM, MIPS_INS_SDC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC2, MIPS_INS_SDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC2_R6, MIPS_INS_SDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDC3, MIPS_INS_SDC3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDIV, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDIV_MM, MIPS_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SDL, MIPS_INS_SDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDR, MIPS_INS_SDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SDXC1, MIPS_INS_SDXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_SDXC164, MIPS_INS_SDXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SEB, MIPS_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SEB64, MIPS_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SEB_MM, MIPS_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SEH, MIPS_INS_SEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SEH64, MIPS_INS_SEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SEH_MM, MIPS_INS_SEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SELEQZ, MIPS_INS_SELEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELEQZ64, MIPS_INS_SELEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELEQZ_D, MIPS_INS_SELEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELEQZ_S, MIPS_INS_SELEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELNEZ, MIPS_INS_SELNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELNEZ64, MIPS_INS_SELNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELNEZ_D, MIPS_INS_SELNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SELNEZ_S, MIPS_INS_SELNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SEL_D, MIPS_INS_SEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SEL_S, MIPS_INS_SEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SEQ, MIPS_INS_SEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SEQi, MIPS_INS_SEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SH, MIPS_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SH16_MM, MIPS_INS_SH16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SH64, MIPS_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SHF_B, MIPS_INS_SHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SHF_H, MIPS_INS_SHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SHF_W, MIPS_INS_SHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SHILO, MIPS_INS_SHILO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHILOV, MIPS_INS_SHILOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLLV_PH, MIPS_INS_SHLLV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLLV_QB, MIPS_INS_SHLLV, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLLV_S_W, MIPS_INS_SHLLV_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLL_PH, MIPS_INS_SHLL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLL_QB, MIPS_INS_SHLL, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLL_S_PH, MIPS_INS_SHLL_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHLL_S_W, MIPS_INS_SHLL_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_PH, MIPS_INS_SHRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_QB, MIPS_INS_SHRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRAV_R_W, MIPS_INS_SHRAV_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_PH, MIPS_INS_SHRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_QB, MIPS_INS_SHRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_R_PH, MIPS_INS_SHRA_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_R_QB, MIPS_INS_SHRA_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRA_R_W, MIPS_INS_SHRA_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRLV_PH, MIPS_INS_SHRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRLV_QB, MIPS_INS_SHRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRL_PH, MIPS_INS_SHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SHRL_QB, MIPS_INS_SHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SH_MM, MIPS_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLDI_B, MIPS_INS_SLDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLDI_D, MIPS_INS_SLDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLDI_H, MIPS_INS_SLDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLDI_W, MIPS_INS_SLDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLD_B, MIPS_INS_SLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLD_D, MIPS_INS_SLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLD_H, MIPS_INS_SLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLD_W, MIPS_INS_SLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL16_MM, MIPS_INS_SLL16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL64_32, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL64_64, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLI_B, MIPS_INS_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLI_D, MIPS_INS_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLI_H, MIPS_INS_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLI_W, MIPS_INS_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLV, MIPS_INS_SLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLLV_MM, MIPS_INS_SLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_B, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_D, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_H, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_MM, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLL_W, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SLT, MIPS_INS_SLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLT64, MIPS_INS_SLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLT_MM, MIPS_INS_SLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTi, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTi64, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTi_MM, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTiu, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTiu64, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTiu_MM, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTu, MIPS_INS_SLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTu64, MIPS_INS_SLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SLTu_MM, MIPS_INS_SLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SNE, MIPS_INS_SNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SNEi, MIPS_INS_SNEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLATI_B, MIPS_INS_SPLATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLATI_D, MIPS_INS_SPLATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLATI_H, MIPS_INS_SPLATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLATI_W, MIPS_INS_SPLATI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLAT_B, MIPS_INS_SPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLAT_D, MIPS_INS_SPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLAT_H, MIPS_INS_SPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SPLAT_W, MIPS_INS_SPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAI_B, MIPS_INS_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAI_D, MIPS_INS_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAI_H, MIPS_INS_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAI_W, MIPS_INS_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRARI_B, MIPS_INS_SRARI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRARI_D, MIPS_INS_SRARI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRARI_H, MIPS_INS_SRARI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRARI_W, MIPS_INS_SRARI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAR_B, MIPS_INS_SRAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAR_D, MIPS_INS_SRAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAR_H, MIPS_INS_SRAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAR_W, MIPS_INS_SRAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAV, MIPS_INS_SRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SRAV_MM, MIPS_INS_SRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_B, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_D, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_H, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_MM, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRA_W, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL16_MM, MIPS_INS_SRL16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLI_B, MIPS_INS_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLI_D, MIPS_INS_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLI_H, MIPS_INS_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLI_W, MIPS_INS_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLRI_B, MIPS_INS_SRLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLRI_D, MIPS_INS_SRLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLRI_H, MIPS_INS_SRLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLRI_W, MIPS_INS_SRLRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLR_B, MIPS_INS_SRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLR_D, MIPS_INS_SRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLR_H, MIPS_INS_SRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLR_W, MIPS_INS_SRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLV, MIPS_INS_SRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SRLV_MM, MIPS_INS_SRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_B, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_D, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_H, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_MM, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SRL_W, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SSNOP, MIPS_INS_SSNOP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SSNOP_MM, MIPS_INS_SSNOP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_ST_B, MIPS_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ST_D, MIPS_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ST_H, MIPS_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_ST_W, MIPS_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUB, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQH_PH, MIPS_INS_SUBQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQH_R_W, MIPS_INS_SUBQH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQH_W, MIPS_INS_SUBQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQ_PH, MIPS_INS_SUBQ, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBQ_S_W, MIPS_INS_SUBQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_S_B, MIPS_INS_SUBS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_S_D, MIPS_INS_SUBS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_S_H, MIPS_INS_SUBS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_S_W, MIPS_INS_SUBS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_U_B, MIPS_INS_SUBS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_U_D, MIPS_INS_SUBS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_U_H, MIPS_INS_SUBS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBS_U_W, MIPS_INS_SUBS_U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU16_MM, MIPS_INS_SUBU16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBUH_QB, MIPS_INS_SUBUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU_PH, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU_QB, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU_S_PH, MIPS_INS_SUBU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBU_S_QB, MIPS_INS_SUBU_S, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBVI_B, MIPS_INS_SUBVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBVI_D, MIPS_INS_SUBVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBVI_H, MIPS_INS_SUBVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBVI_W, MIPS_INS_SUBVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBV_B, MIPS_INS_SUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBV_D, MIPS_INS_SUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBV_H, MIPS_INS_SUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBV_W, MIPS_INS_SUBV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_SUB_MM, MIPS_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBu, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SUBu_MM, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SUXC1, MIPS_INS_SUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_SUXC164, MIPS_INS_SUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SUXC1_MM, MIPS_INS_SUXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SW, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SW16_MM, MIPS_INS_SW16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SW64, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC1, MIPS_INS_SWC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC1_MM, MIPS_INS_SWC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC2, MIPS_INS_SWC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC2_R6, MIPS_INS_SWC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 -#endif -}, -{ - Mips_SWC3, MIPS_INS_SWC3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWL, MIPS_INS_SWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWL64, MIPS_INS_SWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SWL_MM, MIPS_INS_SWL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWM16_MM, MIPS_INS_SWM16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWM32_MM, MIPS_INS_SWM32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWP_MM, MIPS_INS_SWP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWR, MIPS_INS_SWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWR64, MIPS_INS_SWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_SWR_MM, MIPS_INS_SWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWSP_MM, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SWXC1, MIPS_INS_SWXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 -#endif -}, -{ - Mips_SWXC1_MM, MIPS_INS_SWXC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SW_MM, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SYNC, MIPS_INS_SYNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 -#endif -}, -{ - Mips_SYNCI, MIPS_INS_SYNCI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_SYNC_MM, MIPS_INS_SYNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_SYSCALL, MIPS_INS_SYSCALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_INT, 0 }, 0, 0 -#endif -}, -{ - Mips_SYSCALL_MM, MIPS_INS_SYSCALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_INT, 0 }, 0, 0 -#endif -}, -{ - Mips_SbRxRyOffMemX16, MIPS_INS_SB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SebRx16, MIPS_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SehRx16, MIPS_INS_SEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_ShRxRyOffMemX16, MIPS_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SllX16, MIPS_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SllvRxRy16, MIPS_INS_SLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltRxRy16, MIPS_INS_SLT, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltiRxImm16, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltiRxImmX16, MIPS_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltiuRxImm16, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltiuRxImmX16, MIPS_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SltuRxRy16, MIPS_INS_SLTU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SraX16, MIPS_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SravRxRy16, MIPS_INS_SRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SrlX16, MIPS_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SrlvRxRy16, MIPS_INS_SRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SubuRxRyRz16, MIPS_INS_SUBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SwRxRyOffMemX16, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_SwRxSpImmX16, MIPS_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, -{ - Mips_TEQ, MIPS_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TEQI, MIPS_INS_TEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TEQI_MM, MIPS_INS_TEQI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TEQ_MM, MIPS_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TGE, MIPS_INS_TGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEI, MIPS_INS_TGEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEIU, MIPS_INS_TGEIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEIU_MM, MIPS_INS_TGEIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEI_MM, MIPS_INS_TGEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEU, MIPS_INS_TGEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TGEU_MM, MIPS_INS_TGEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TGE_MM, MIPS_INS_TGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBP, MIPS_INS_TLBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBP_MM, MIPS_INS_TLBP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBR, MIPS_INS_TLBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBR_MM, MIPS_INS_TLBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBWI, MIPS_INS_TLBWI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBWI_MM, MIPS_INS_TLBWI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBWR, MIPS_INS_TLBWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_TLBWR_MM, MIPS_INS_TLBWR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLT, MIPS_INS_TLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTI, MIPS_INS_TLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTIU_MM, MIPS_INS_TLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTI_MM, MIPS_INS_TLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTU, MIPS_INS_TLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TLTU_MM, MIPS_INS_TLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TLT_MM, MIPS_INS_TLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TNE, MIPS_INS_TNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TNEI, MIPS_INS_TNEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_TNEI_MM, MIPS_INS_TNEI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TNE_MM, MIPS_INS_TNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_L_D64, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_L_S, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_D32, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_D64, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_MM, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_S, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 -#endif -}, -{ - Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_TTLTIU, MIPS_INS_TLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_UDIV, MIPS_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 -#endif -}, -{ - Mips_UDIV_MM, MIPS_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_V3MULU, MIPS_INS_V3MULU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_VMM0, MIPS_INS_VMM0, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_VMULU, MIPS_INS_VMULU, -#ifndef CAPSTONE_DIET - { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_VSHF_B, MIPS_INS_VSHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_VSHF_D, MIPS_INS_VSHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_VSHF_H, MIPS_INS_VSHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_VSHF_W, MIPS_INS_VSHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_WAIT, MIPS_INS_WAIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_WAIT_MM, MIPS_INS_WAIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_WRDSP, MIPS_INS_WRDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 -#endif -}, -{ - Mips_WSBH, MIPS_INS_WSBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 -#endif -}, -{ - Mips_WSBH_MM, MIPS_INS_WSBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR16_MM, MIPS_INS_XOR16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR64, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_XORI_B, MIPS_INS_XORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR_MM, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XOR_V, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 -#endif -}, -{ - Mips_XORi, MIPS_INS_XORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_XORi64, MIPS_INS_XORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 -#endif -}, -{ - Mips_XORi_MM, MIPS_INS_XORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 -#endif -}, -{ - Mips_XorRxRxRy16, MIPS_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 -#endif -}, diff --git a/arch/Mips/MipsModule.c b/arch/Mips/MipsModule.c index e06871d3b4..bf3d6cb3cc 100644 --- a/arch/Mips/MipsModule.c +++ b/arch/Mips/MipsModule.c @@ -3,50 +3,47 @@ #ifdef CAPSTONE_HAS_MIPS -#include "../../utils.h" +#include "MipsModule.h" #include "../../MCRegisterInfo.h" +#include "../../utils.h" #include "MipsDisassembler.h" #include "MipsInstPrinter.h" #include "MipsMapping.h" -#include "MipsModule.h" // Returns mode value with implied bits set -static cs_mode updated_mode(cs_mode mode) -{ - if (mode & CS_MODE_MIPS32R6) { - mode |= CS_MODE_32; - } +static cs_mode updated_mode(cs_mode mode) { + if (mode & CS_MODE_MIPS32R6) { + mode |= CS_MODE_32; + } - return mode; + return mode; } -cs_err Mips_global_init(cs_struct *ud) -{ - MCRegisterInfo *mri; - mri = cs_mem_malloc(sizeof(*mri)); +cs_err Mips_global_init(cs_struct *ud) { + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); - Mips_init(mri); - ud->printer = Mips_printInst; - ud->printer_info = mri; - ud->getinsn_info = mri; - ud->reg_name = Mips_reg_name; - ud->insn_id = Mips_get_insn_id; - ud->insn_name = Mips_insn_name; - ud->group_name = Mips_group_name; + Mips_init(mri); + ud->printer = Mips_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->reg_name = Mips_reg_name; + ud->insn_id = Mips_get_insn_id; + ud->insn_name = Mips_insn_name; + ud->group_name = Mips_group_name; - ud->disasm = Mips_getInstruction; + ud->disasm = Mips_getInstruction; - return CS_ERR_OK; + return CS_ERR_OK; } -cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value) -{ - if (type == CS_OPT_MODE) { - handle->mode = updated_mode(value); - return CS_ERR_OK; - } +cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value) { + if (type == CS_OPT_MODE) { + handle->mode = updated_mode(value); + return CS_ERR_OK; + } - return CS_ERR_OPTION; + return CS_ERR_OPTION; } #endif diff --git a/arch/PowerPC/CapstonePPCModule.h b/arch/PowerPC/CapstonePPCModule.h new file mode 100644 index 0000000000..0624f0af66 --- /dev/null +++ b/arch/PowerPC/CapstonePPCModule.h @@ -0,0 +1,621 @@ +// +// Created by Phosphorus15 on 2021/7/12. +// + +#ifndef CAPSTONE_CAPSTONEPPCMODULE_H +#define CAPSTONE_CAPSTONEPPCMODULE_H + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} + +#define PPC_REGS0_31(X) \ + { \ + X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \ + X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \ + X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \ + } + +#define PPC_REGS_NO0_31(Z, X) \ + { \ + Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \ + X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \ + X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \ + } + +#define PPC_REGS0_7(X) \ + { X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 } + +static DecodeStatus decodeCondBrTarget(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeDirectBrTarget(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, + const unsigned *Regs); + +static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVFRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVSSRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeG8pRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSPERCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); +static DecodeStatus DecodeACCRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVSRpRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, void *Decoder, + int); + +static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, void *Decoder, + unsigned N); + +static DecodeStatus decodeImmZeroOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeVSRpEvenOperands(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeMemRIHashOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeMemRI34PCRelOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeMemRI34Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder); + +#define GET_REGINFO_ENUM +#define GET_INSTRINFO_ENUM +#define MIPS_GET_DISASSEMBLER +#define GET_REGINFO_MC_DESC +#include "PPCGenDisassemblerTables.inc" + +FieldFromInstruction(fieldFromInstruction4, uint64_t) + DecodeToMCInst(decodeToMCInst4, fieldFromInstruction4, uint64_t) + DecodeInstruction(decodeInstruction4, fieldFromInstruction4, + decodeToMCInst4, uint64_t) + +static const unsigned RRegs[32] = PPC_REGS0_31(PPC_R); + +static const unsigned RRegsNoR0[32] = PPC_REGS_NO0_31(PPC_ZERO, PPC_R); + +static const unsigned XRegs[32] = PPC_REGS0_31(PPC_X); + +static const unsigned XRegsNoX0[32] = PPC_REGS_NO0_31(PPC_ZERO8, PPC_X); + +static const unsigned VSRpRegs[32] = PPC_REGS0_31(PPC_VSRp); + +static const unsigned ACCRegs[8] = PPC_REGS0_7(PPC_ACC); + +static const unsigned CRRegs[] = {PPC_CR0, PPC_CR1, PPC_CR2, PPC_CR3, + PPC_CR4, PPC_CR5, PPC_CR6, PPC_CR7}; + +static const unsigned CRBITRegs[] = { + PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, + PPC_CR1UN, PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, + PPC_CR3EQ, PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, PPC_CR5LT, + PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, + PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN}; + +static const unsigned FRegs[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, + PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F14, PPC_F15, + PPC_F16, PPC_F17, PPC_F18, PPC_F19, PPC_F20, PPC_F21, PPC_F22, PPC_F23, + PPC_F24, PPC_F25, PPC_F26, PPC_F27, PPC_F28, PPC_F29, PPC_F30, PPC_F31}; + +static const unsigned VFRegs[] = { + PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF6, + PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, + PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF20, + PPC_VF21, PPC_VF22, PPC_VF23, PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, + PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31}; + +static const unsigned VRegs[] = { + PPC_V0, PPC_V1, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V6, PPC_V7, + PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, + PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V20, PPC_V21, PPC_V22, PPC_V23, + PPC_V24, PPC_V25, PPC_V26, PPC_V27, PPC_V28, PPC_V29, PPC_V30, PPC_V31}; + +static const unsigned VSRegs[] = { + PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, + PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, + PPC_VSL14, PPC_VSL15, PPC_VSL16, PPC_VSL17, PPC_VSL18, PPC_VSL19, PPC_VSL20, + PPC_VSL21, PPC_VSL22, PPC_VSL23, PPC_VSL24, PPC_VSL25, PPC_VSL26, PPC_VSL27, + PPC_VSL28, PPC_VSL29, PPC_VSL30, PPC_VSL31, + + PPC_V0, PPC_V1, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V6, + PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, + PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V20, + PPC_V21, PPC_V22, PPC_V23, PPC_V24, PPC_V25, PPC_V26, PPC_V27, + PPC_V28, PPC_V29, PPC_V30, PPC_V31}; + +static const unsigned VSFRegs[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, + PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, + PPC_F14, PPC_F15, PPC_F16, PPC_F17, PPC_F18, PPC_F19, PPC_F20, + PPC_F21, PPC_F22, PPC_F23, PPC_F24, PPC_F25, PPC_F26, PPC_F27, + PPC_F28, PPC_F29, PPC_F30, PPC_F31, + + PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF6, + PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, + PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF20, + PPC_VF21, PPC_VF22, PPC_VF23, PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, + PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31}; + +static const unsigned VSSRegs[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, + PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, + PPC_F14, PPC_F15, PPC_F16, PPC_F17, PPC_F18, PPC_F19, PPC_F20, + PPC_F21, PPC_F22, PPC_F23, PPC_F24, PPC_F25, PPC_F26, PPC_F27, + PPC_F28, PPC_F29, PPC_F30, PPC_F31, + + PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF6, + PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, + PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF20, + PPC_VF21, PPC_VF22, PPC_VF23, PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, + PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31}; + +static const unsigned GPRegs[] = { + PPC_R0, PPC_R1, PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, + PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R13, PPC_R14, PPC_R15, + PPC_R16, PPC_R17, PPC_R18, PPC_R19, PPC_R20, PPC_R21, PPC_R22, PPC_R23, + PPC_R24, PPC_R25, PPC_R26, PPC_R27, PPC_R28, PPC_R29, PPC_R30, PPC_R31}; + +static const unsigned GP0Regs[] = { + PPC_ZERO, PPC_R1, PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, + PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R13, PPC_R14, PPC_R15, + PPC_R16, PPC_R17, PPC_R18, PPC_R19, PPC_R20, PPC_R21, PPC_R22, PPC_R23, + PPC_R24, PPC_R25, PPC_R26, PPC_R27, PPC_R28, PPC_R29, PPC_R30, PPC_R31}; + +static const unsigned G8Regs[] = { + PPC_X0, PPC_X1, PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, + PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X13, PPC_X14, PPC_X15, + PPC_X16, PPC_X17, PPC_X18, PPC_X19, PPC_X20, PPC_X21, PPC_X22, PPC_X23, + PPC_X24, PPC_X25, PPC_X26, PPC_X27, PPC_X28, PPC_X29, PPC_X30, PPC_X31}; + +static const unsigned G80Regs[] = { + PPC_ZERO8, PPC_X1, PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, + PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X13, PPC_X14, PPC_X15, + PPC_X16, PPC_X17, PPC_X18, PPC_X19, PPC_X20, PPC_X21, PPC_X22, PPC_X23, + PPC_X24, PPC_X25, PPC_X26, PPC_X27, PPC_X28, PPC_X29, PPC_X30, PPC_X31}; + +static const unsigned SPERegs[] = { + PPC_S0, PPC_S1, PPC_S2, PPC_S3, PPC_S4, PPC_S5, PPC_S6, PPC_S7, + PPC_S8, PPC_S9, PPC_S10, PPC_S11, PPC_S12, PPC_S13, PPC_S14, PPC_S15, + PPC_S16, PPC_S17, PPC_S18, PPC_S19, PPC_S20, PPC_S21, PPC_S22, PPC_S23, + PPC_S24, PPC_S25, PPC_S26, PPC_S27, PPC_S28, PPC_S29, PPC_S30, PPC_S31}; + +static DecodeStatus decodeCondBrTarget(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder) { + MCOperand_CreateImm0(Inst, SignExtend32(Imm, 14)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeDirectBrTarget(MCInst *Inst, unsigned Imm, + uint64_t Address, + void *Decoder) { + int32_t Offset = SignExtend32(Imm, 24); + MCOperand_CreateImm0(Inst, Offset); + return MCDisassembler_Success; +} + +static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, + const unsigned *Regs) { + MCOperand_CreateReg0(Inst, Regs[RegNo]); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, CRRegs); +} + +static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, CRBITRegs); +} + +static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, FRegs); +} + +static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, FRegs); +} + +static DecodeStatus DecodeVFRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, VFRegs); +} + +static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, VRegs); +} + +static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, VSRegs); +} + +static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, VSFRegs); +} + +static DecodeStatus DecodeVSSRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, VSSRegs); +} + +static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, RRegs); +} + +static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, RRegsNoR0); +} + +static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, XRegs); +} + +static DecodeStatus DecodeG8pRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, XRegs); +} + +static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, XRegsNoX0); +} + +static DecodeStatus DecodeSPERCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SPERegs); +} + +static DecodeStatus DecodeACCRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, ACCRegs); +} + +static DecodeStatus DecodeVSRpRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, VSRpRegs); +} + +static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, void *Decoder, + int N) { + // assert(isUInt(Imm, N) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, Imm); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, void *Decoder, + unsigned N) { + // assert(isUInt(Imm, N) && "Invalid immediate"); + MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeImmZeroOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + if (Imm != 0) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, Imm); + return MCDisassembler_Success; +} + +static DecodeStatus decodeVSRpEvenOperands(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo & 1) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, VSRpRegs[RegNo >> 1]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // Decode the memri field (imm, reg), which has the low 16-bits as the + // displacement and the next 5 bits as the register #. + + uint64_t Base = Imm >> 16; + uint64_t Disp = Imm & 0xFFFF; + + assert(Base < 32 && "Invalid base register"); + + switch (MCInst_getOpcode(Inst)) { + default: + break; + case PPC_LBZU: + case PPC_LHAU: + case PPC_LHZU: + case PPC_LWZU: + case PPC_LFSU: + case PPC_LFDU: + // Add the tied output operand. + MCOperand_CreateReg0(Inst, RRegsNoR0[Base]); + break; + case PPC_STBU: + case PPC_STHU: + case PPC_STWU: + case PPC_STFSU: + case PPC_STFDU: + MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, RRegsNoR0[Base])); + break; + } + + MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16)); + MCOperand_CreateReg0(Inst, RRegsNoR0[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // Decode the memrix field (imm, reg), which has the low 14-bits as the + // displacement and the next 5 bits as the register #. + + uint64_t Base = Imm >> 14; + uint64_t Disp = Imm & 0x3FFF; + + assert(Base < 32 && "Invalid base register"); + + if (MCInst_getOpcode(Inst) == PPC_LDU) + // Add the tied output operand. + MCOperand_CreateReg0(Inst, RRegsNoR0[Base]); + else if (MCInst_getOpcode(Inst) == PPC_STDU) + MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, RRegsNoR0[Base])); + + MCOperand_CreateImm0(Inst, SignExtend64(Disp << 2, 16)); + MCOperand_CreateReg0(Inst, RRegsNoR0[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeMemRIHashOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // Decode the memrix field for a hash store or hash check operation. + // The field is composed of a register and an immediate value that is 6 bits + // and covers the range -8 to -512. The immediate is always negative and 2s + // complement which is why we sign extend a 7 bit value. + const uint64_t Base = Imm >> 6; + const int64_t Disp = SignExtend64((Imm & 0x3F, 7) + 64, 64) * 8; + + assert(Base < 32 && "Invalid base register"); + + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateReg0(Inst, RRegs[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // Decode the memrix16 field (imm, reg), which has the low 12-bits as the + // displacement with 16-byte aligned, and the next 5 bits as the register #. + + uint64_t Base = Imm >> 12; + uint64_t Disp = Imm & 0xFFF; + + assert(Base < 32 && "Invalid base register"); + + MCOperand_CreateImm0(Inst, SignExtend64(Disp << 4, 16)); + MCOperand_CreateReg0(Inst, RRegsNoR0[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeMemRI34PCRelOperands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the + // displacement, and the next 5 bits as an immediate 0. + uint64_t Base = Imm >> 34; + uint64_t Disp = Imm & 0x3FFFFFFFFUL; + + assert(Base < 32 && "Invalid base register"); + + MCOperand_CreateImm0(Inst, SignExtend64(Disp, 34)); + return decodeImmZeroOperand(Inst, Base, Address, Decoder); +} + +static DecodeStatus decodeMemRI34Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // Decode the memri34 field (imm, reg), which has the low 34-bits as the + // displacement, and the next 5 bits as the register #. + uint64_t Base = Imm >> 34; + uint64_t Disp = Imm & 0x3FFFFFFFFUL; + + assert(Base < 32 && "Invalid base register"); + + MCOperand_CreateImm0(Inst, SignExtend64(Disp, 34)); + MCOperand_CreateReg0(Inst, RRegsNoR0[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // Decode the spe8disp field (imm, reg), which has the low 5-bits as the + // displacement with 8-byte aligned, and the next 5 bits as the register #. + + uint64_t Base = Imm >> 5; + uint64_t Disp = Imm & 0x1F; + + assert(Base < 32 && "Invalid base register"); + + MCOperand_CreateImm0(Inst, Disp << 3); + MCOperand_CreateReg0(Inst, RRegsNoR0[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // Decode the spe4disp field (imm, reg), which has the low 5-bits as the + // displacement with 4-byte aligned, and the next 5 bits as the register #. + + uint64_t Base = Imm >> 5; + uint64_t Disp = Imm & 0x1F; + + assert(Base < 32 && "Invalid base register"); + + MCOperand_CreateImm0(Inst, Disp << 2); + MCOperand_CreateReg0(Inst, RRegsNoR0[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // Decode the spe2disp field (imm, reg), which has the low 5-bits as the + // displacement with 2-byte aligned, and the next 5 bits as the register #. + + uint64_t Base = Imm >> 5; + uint64_t Disp = Imm & 0x1F; + + assert(Base < 32 && "Invalid base register"); + + MCOperand_CreateImm0(Inst, Disp << 1); + MCOperand_CreateReg0(Inst, RRegsNoR0[Base]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, + void *Decoder) { + // The cr bit encoding is 0x80 >> cr_reg_num. + + unsigned Zeros = CountTrailingZeros_64(Imm); + assert(Zeros < 8 && "Invalid CR bit value"); + + MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]); + return MCDisassembler_Success; +} + +#endif // CAPSTONE_CAPSTONEPPCMODULE_H diff --git a/arch/PowerPC/PPCDisassembler.c b/arch/PowerPC/PPCDisassembler.c index 14bcb20bb1..102d977911 100644 --- a/arch/PowerPC/PPCDisassembler.c +++ b/arch/PowerPC/PPCDisassembler.c @@ -12,7 +12,7 @@ #ifdef CAPSTONE_HAS_POWERPC -#include // DEBUG +#include // DEBUG #include #include @@ -21,195 +21,29 @@ #include "PPCDisassembler.h" +#include "../../MCDisassembler.h" +#include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" -#include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" -#include "../../MCDisassembler.h" #include "../../MathExtras.h" -#define GET_REGINFO_ENUM -#include "PPCGenRegisterInfo.inc" +// Currently, we have no feature checks upon PPC, but there might be later, so +// dummy +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require) { + // extended from original arm module + return Require; +} +#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass +#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass + +#include "CapstonePPCModule.h" // FIXME: These can be generated by TableGen from the existing register // encoding values! -static const unsigned CRRegs[] = { - PPC_CR0, PPC_CR1, PPC_CR2, PPC_CR3, - PPC_CR4, PPC_CR5, PPC_CR6, PPC_CR7 -}; - -static const unsigned CRBITRegs[] = { - PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, - PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, - PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, - PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, - PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, - PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, - PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, - PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN -}; - -static const unsigned FRegs[] = { - PPC_F0, PPC_F1, PPC_F2, PPC_F3, - PPC_F4, PPC_F5, PPC_F6, PPC_F7, - PPC_F8, PPC_F9, PPC_F10, PPC_F11, - PPC_F12, PPC_F13, PPC_F14, PPC_F15, - PPC_F16, PPC_F17, PPC_F18, PPC_F19, - PPC_F20, PPC_F21, PPC_F22, PPC_F23, - PPC_F24, PPC_F25, PPC_F26, PPC_F27, - PPC_F28, PPC_F29, PPC_F30, PPC_F31 -}; - -static const unsigned VFRegs[] = { - PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, - PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, - PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, - PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, - PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, - PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, - PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, - PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 -}; - -static const unsigned VRegs[] = { - PPC_V0, PPC_V1, PPC_V2, PPC_V3, - PPC_V4, PPC_V5, PPC_V6, PPC_V7, - PPC_V8, PPC_V9, PPC_V10, PPC_V11, - PPC_V12, PPC_V13, PPC_V14, PPC_V15, - PPC_V16, PPC_V17, PPC_V18, PPC_V19, - PPC_V20, PPC_V21, PPC_V22, PPC_V23, - PPC_V24, PPC_V25, PPC_V26, PPC_V27, - PPC_V28, PPC_V29, PPC_V30, PPC_V31 -}; - -static const unsigned VSRegs[] = { - PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, - PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, - PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, - PPC_VSL12, PPC_VSL13, PPC_VSL14, PPC_VSL15, - PPC_VSL16, PPC_VSL17, PPC_VSL18, PPC_VSL19, - PPC_VSL20, PPC_VSL21, PPC_VSL22, PPC_VSL23, - PPC_VSL24, PPC_VSL25, PPC_VSL26, PPC_VSL27, - PPC_VSL28, PPC_VSL29, PPC_VSL30, PPC_VSL31, - - PPC_V0, PPC_V1, PPC_V2, PPC_V3, - PPC_V4, PPC_V5, PPC_V6, PPC_V7, - PPC_V8, PPC_V9, PPC_V10, PPC_V11, - PPC_V12, PPC_V13, PPC_V14, PPC_V15, - PPC_V16, PPC_V17, PPC_V18, PPC_V19, - PPC_V20, PPC_V21, PPC_V22, PPC_V23, - PPC_V24, PPC_V25, PPC_V26, PPC_V27, - PPC_V28, PPC_V29, PPC_V30, PPC_V31 -}; - -static const unsigned VSFRegs[] = { - PPC_F0, PPC_F1, PPC_F2, PPC_F3, - PPC_F4, PPC_F5, PPC_F6, PPC_F7, - PPC_F8, PPC_F9, PPC_F10, PPC_F11, - PPC_F12, PPC_F13, PPC_F14, PPC_F15, - PPC_F16, PPC_F17, PPC_F18, PPC_F19, - PPC_F20, PPC_F21, PPC_F22, PPC_F23, - PPC_F24, PPC_F25, PPC_F26, PPC_F27, - PPC_F28, PPC_F29, PPC_F30, PPC_F31, - - PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, - PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, - PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, - PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, - PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, - PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, - PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, - PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 -}; - -static const unsigned VSSRegs[] = { - PPC_F0, PPC_F1, PPC_F2, PPC_F3, - PPC_F4, PPC_F5, PPC_F6, PPC_F7, - PPC_F8, PPC_F9, PPC_F10, PPC_F11, - PPC_F12, PPC_F13, PPC_F14, PPC_F15, - PPC_F16, PPC_F17, PPC_F18, PPC_F19, - PPC_F20, PPC_F21, PPC_F22, PPC_F23, - PPC_F24, PPC_F25, PPC_F26, PPC_F27, - PPC_F28, PPC_F29, PPC_F30, PPC_F31, - - PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, - PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, - PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, - PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, - PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, - PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, - PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, - PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 -}; - -static const unsigned GPRegs[] = { - PPC_R0, PPC_R1, PPC_R2, PPC_R3, - PPC_R4, PPC_R5, PPC_R6, PPC_R7, - PPC_R8, PPC_R9, PPC_R10, PPC_R11, - PPC_R12, PPC_R13, PPC_R14, PPC_R15, - PPC_R16, PPC_R17, PPC_R18, PPC_R19, - PPC_R20, PPC_R21, PPC_R22, PPC_R23, - PPC_R24, PPC_R25, PPC_R26, PPC_R27, - PPC_R28, PPC_R29, PPC_R30, PPC_R31 -}; - -static const unsigned GP0Regs[] = { - PPC_ZERO, PPC_R1, PPC_R2, PPC_R3, - PPC_R4, PPC_R5, PPC_R6, PPC_R7, - PPC_R8, PPC_R9, PPC_R10, PPC_R11, - PPC_R12, PPC_R13, PPC_R14, PPC_R15, - PPC_R16, PPC_R17, PPC_R18, PPC_R19, - PPC_R20, PPC_R21, PPC_R22, PPC_R23, - PPC_R24, PPC_R25, PPC_R26, PPC_R27, - PPC_R28, PPC_R29, PPC_R30, PPC_R31 -}; - -static const unsigned G8Regs[] = { - PPC_X0, PPC_X1, PPC_X2, PPC_X3, - PPC_X4, PPC_X5, PPC_X6, PPC_X7, - PPC_X8, PPC_X9, PPC_X10, PPC_X11, - PPC_X12, PPC_X13, PPC_X14, PPC_X15, - PPC_X16, PPC_X17, PPC_X18, PPC_X19, - PPC_X20, PPC_X21, PPC_X22, PPC_X23, - PPC_X24, PPC_X25, PPC_X26, PPC_X27, - PPC_X28, PPC_X29, PPC_X30, PPC_X31 -}; - -static const unsigned G80Regs[] = { - PPC_ZERO8, PPC_X1, PPC_X2, PPC_X3, - PPC_X4, PPC_X5, PPC_X6, PPC_X7, - PPC_X8, PPC_X9, PPC_X10, PPC_X11, - PPC_X12, PPC_X13, PPC_X14, PPC_X15, - PPC_X16, PPC_X17, PPC_X18, PPC_X19, - PPC_X20, PPC_X21, PPC_X22, PPC_X23, - PPC_X24, PPC_X25, PPC_X26, PPC_X27, - PPC_X28, PPC_X29, PPC_X30, PPC_X31 -}; - -static const unsigned QFRegs[] = { - PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, - PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, - PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, - PPC_QF12, PPC_QF13, PPC_QF14, PPC_QF15, - PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19, - PPC_QF20, PPC_QF21, PPC_QF22, PPC_QF23, - PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27, - PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31 -}; - -static const unsigned SPERegs[] = { - PPC_S0, PPC_S1, PPC_S2, PPC_S3, - PPC_S4, PPC_S5, PPC_S6, PPC_S7, - PPC_S8, PPC_S9, PPC_S10, PPC_S11, - PPC_S12, PPC_S13, PPC_S14, PPC_S15, - PPC_S16, PPC_S17, PPC_S18, PPC_S19, - PPC_S20, PPC_S21, PPC_S22, PPC_S23, - PPC_S24, PPC_S25, PPC_S26, PPC_S27, - PPC_S28, PPC_S29, PPC_S30, PPC_S31 -}; - #if 0 static uint64_t getFeatureBits(int feature) { @@ -218,398 +52,93 @@ static uint64_t getFeatureBits(int feature) } #endif -static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, - const unsigned *Regs, size_t RegsLen) -{ - if (RegNo >= RegsLen / sizeof(unsigned)) { - return MCDisassembler_Fail; - } - MCOperand_CreateReg0(Inst, Regs[RegNo]); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, CRRegs, sizeof(CRRegs)); -} - -static DecodeStatus DecodeCRRC0RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, CRRegs, sizeof(CRRegs)); -} - -static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, CRBITRegs, sizeof(CRBITRegs)); -} - -static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs)); -} - -static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs)); -} - -static DecodeStatus DecodeVFRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, VFRegs, sizeof(VFRegs)); -} - -static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, VRegs, sizeof(VRegs)); -} - -static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, VSRegs, sizeof(VSRegs)); -} - -static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, VSFRegs, sizeof(VSFRegs)); -} - -static DecodeStatus DecodeVSSRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, VSSRegs, sizeof(VSSRegs)); -} - -static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, GPRegs, sizeof(GPRegs)); -} - -static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, GP0Regs, sizeof(GP0Regs)); -} - -static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, G8Regs, sizeof(G8Regs)); -} - -static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, G80Regs, sizeof(G80Regs)); -} - -#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass -#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass - -static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, QFRegs, sizeof(QFRegs)); -} - -static DecodeStatus DecodeSPE4RCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, GPRegs, sizeof(GPRegs)); -} - -static DecodeStatus DecodeSPERCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SPERegs, sizeof(SPERegs)); -} - -#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass -#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass - -static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder, unsigned N) -{ - //assert(isUInt(Imm) && "Invalid immediate"); - MCOperand_CreateImm0(Inst, Imm); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder, unsigned N) -{ - // assert(isUInt(Imm) && "Invalid immediate"); - MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); - - return MCDisassembler_Success; -} - - -#define GET_INSTRINFO_ENUM -#include "PPCGenInstrInfo.inc" - -static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder) -{ - // Decode the memri field (imm, reg), which has the low 16-bits as the - // displacement and the next 5 bits as the register #. - - uint64_t Base = Imm >> 16; - uint64_t Disp = Imm & 0xFFFF; - - // assert(Base < 32 && "Invalid base register"); - if (Base >= 32) - return MCDisassembler_Fail; - - switch (MCInst_getOpcode(Inst)) { - default: break; - case PPC_LBZU: - case PPC_LHAU: - case PPC_LHZU: - case PPC_LWZU: - case PPC_LFSU: - case PPC_LFDU: - // Add the tied output operand. - MCOperand_CreateReg0(Inst, GP0Regs[Base]); - break; - case PPC_STBU: - case PPC_STHU: - case PPC_STWU: - case PPC_STFSU: - case PPC_STFDU: - MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base])); - break; - } - - MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16)); - MCOperand_CreateReg0(Inst, GP0Regs[Base]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder) -{ - // Decode the memrix field (imm, reg), which has the low 14-bits as the - // displacement and the next 5 bits as the register #. - - uint64_t Base = Imm >> 14; - uint64_t Disp = Imm & 0x3FFF; - - // assert(Base < 32 && "Invalid base register"); - if (Base >= 32) - return MCDisassembler_Fail; - - if (MCInst_getOpcode(Inst) == PPC_LDU) - // Add the tied output operand. - MCOperand_CreateReg0(Inst, GP0Regs[Base]); - else if (MCInst_getOpcode(Inst) == PPC_STDU) - MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base])); - - MCOperand_CreateImm0(Inst, SignExtend64(Disp << 2, 16)); - MCOperand_CreateReg0(Inst, GP0Regs[Base]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder) -{ - // Decode the memrix16 field (imm, reg), which has the low 12-bits as the - // displacement with 16-byte aligned, and the next 5 bits as the register #. - - uint64_t Base = Imm >> 12; - uint64_t Disp = Imm & 0xFFF; - - // assert(Base < 32 && "Invalid base register"); - if (Base >= 32) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, SignExtend64(Disp << 4, 16)); - MCOperand_CreateReg0(Inst, GP0Regs[Base]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder) -{ - // Decode the spe8disp field (imm, reg), which has the low 5-bits as the - // displacement with 8-byte aligned, and the next 5 bits as the register #. - - uint64_t Base = Imm >> 5; - uint64_t Disp = Imm & 0x1F; - - // assert(Base < 32 && "Invalid base register"); - if (Base >= 32) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, Disp << 3); - MCOperand_CreateReg0(Inst, GP0Regs[Base]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder) -{ - // Decode the spe4disp field (imm, reg), which has the low 5-bits as the - // displacement with 4-byte aligned, and the next 5 bits as the register #. - - uint64_t Base = Imm >> 5; - uint64_t Disp = Imm & 0x1F; - - // assert(Base < 32 && "Invalid base register"); - if (Base >= 32) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, Disp << 2); - MCOperand_CreateReg0(Inst, GP0Regs[Base]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder) -{ - // Decode the spe2disp field (imm, reg), which has the low 5-bits as the - // displacement with 2-byte aligned, and the next 5 bits as the register #. - - uint64_t Base = Imm >> 5; - uint64_t Disp = Imm & 0x1F; - - // assert(Base < 32 && "Invalid base register"); - if (Base >= 32) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, Disp << 1); - MCOperand_CreateReg0(Inst, GP0Regs[Base]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder) -{ - // The cr bit encoding is 0x80 >> cr_reg_num. - - unsigned Zeros = CountTrailingZeros_64(Imm); - // assert(Zeros < 8 && "Invalid CR bit value"); - if (Zeros >= 8) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]); - - return MCDisassembler_Success; -} - -#include "PPCGenDisassemblerTables.inc" - -static DecodeStatus getInstruction(MCInst *MI, - const uint8_t *code, size_t code_len, - uint16_t *Size, - uint64_t Address, MCRegisterInfo *MRI) -{ - uint32_t insn; - DecodeStatus result; - - // Get the four bytes of the instruction. - if (code_len < 4) { - // not enough data - *Size = 0; - return MCDisassembler_Fail; - } - - // The instruction is big-endian encoded. - if (MODE_IS_BIG_ENDIAN(MI->csh->mode)) - insn = ((uint32_t) code[0] << 24) | (code[1] << 16) | - (code[2] << 8) | (code[3] << 0); - else // little endian - insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | - (code[1] << 8) | (code[0] << 0); - - if (MI->flat_insn->detail) { - memset(MI->flat_insn->detail, 0, offsetof(cs_detail, ppc) + sizeof(cs_ppc)); - } - - if (MI->csh->mode & CS_MODE_QPX) { - result = decodeInstruction_4(DecoderTableQPX32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - - return result; - } - - // failed to decode - MCInst_clear(MI); - } else if (MI->csh->mode & CS_MODE_SPE) { - result = decodeInstruction_4(DecoderTableSPE32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - - return result; - } - - // failed to decode - MCInst_clear(MI); - } - - result = decodeInstruction_4(DecoderTable32, MI, insn, Address); - if (result != MCDisassembler_Fail) { - *Size = 4; - - return result; - } - - // cannot decode, report error - MCInst_clear(MI); - *Size = 0; - - return MCDisassembler_Fail; +static DecodeStatus getInstruction(MCInst *MI, const uint8_t *code, + size_t code_len, uint16_t *Size, + uint64_t Address, MCRegisterInfo *info) { + MI->MRI = info; + uint32_t insn; + DecodeStatus result; + + // Get the four bytes of the instruction. + if (code_len < 4) { + // not enough data + *Size = 0; + return MCDisassembler_Fail; + } + + // The instruction is big-endian encoded. + if (MODE_IS_BIG_ENDIAN(MI->csh->mode)) + insn = ((uint32_t)code[0] << 24) | (code[1] << 16) | (code[2] << 8) | + (code[3] << 0); + else // little endian + insn = ((uint32_t)code[3] << 24) | (code[2] << 16) | (code[1] << 8) | + (code[0] << 0); + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, ppc) + sizeof(cs_ppc)); + } + + if (MI->csh->mode & CS_MODE_QPX) { + // fixme what exactly is qpx + // result = decodeInstruction(DecoderTableQPX32, MI, insn, + // Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + + return result; + } + + // failed to decode + MCInst_clear(MI); + } else if (MI->csh->mode & CS_MODE_SPE) { + result = decodeInstruction4(DecoderTableSPE32, MI, insn, Address, 0, 0); + if (result != MCDisassembler_Fail) { + *Size = 4; + + return result; + } + + // failed to decode + MCInst_clear(MI); + } + + result = decodeInstruction4(DecoderTable32, MI, insn, Address, 0, 0); + if (result != MCDisassembler_Fail) { + *Size = 4; + + return result; + } + + // cannot decode, report error + MCInst_clear(MI); + *Size = 0; + + return MCDisassembler_Fail; } bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info) -{ - DecodeStatus status = getInstruction(instr, - code, code_len, - size, - address, (MCRegisterInfo *)info); - - return status == MCDisassembler_Success; -} - -#define GET_REGINFO_MC_DESC -#include "PPCGenRegisterInfo.inc" -void PPC_init(MCRegisterInfo *MRI) -{ - /* - InitMCRegisterInfo(PPCRegDesc, 344, - RA, PC, - PPCMCRegisterClasses, 36, - PPCRegUnitRoots, 171, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings, - PPCSubRegIdxLists, 7, - PPCSubRegIdxRanges, PPCRegEncodingTable); - */ - - MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, 344, - 0, 0, - PPCMCRegisterClasses, 36, - 0, 0, - PPCRegDiffLists, - 0, - PPCSubRegIdxLists, 7, - 0); + MCInst *instr, uint16_t *size, uint64_t address, + void *info) { + DecodeStatus status = getInstruction(instr, code, code_len, size, address, + (MCRegisterInfo *)info); + + return status == MCDisassembler_Success; +} + +void PPC_init(MCRegisterInfo *MRI) { + /* + InitMCRegisterInfo(PPCRegDesc, 344, + RA, PC, + PPCMCRegisterClasses, 36, + PPCRegUnitRoots, 171, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, + PPCRegClassStrings, PPCSubRegIdxLists, 7, PPCSubRegIdxRanges, + PPCRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo( + MRI, PPCRegDesc, ARR_SIZE(PPCRegDesc), 0, 0, PPCMCRegisterClasses, + ARR_SIZE(PPCMCRegisterClasses), 0, 0, PPCRegDiffLists, 0, + PPCSubRegIdxLists, ARR_SIZE(PPCSubRegIdxLists), 0); } #endif diff --git a/arch/PowerPC/PPCDisassembler.h b/arch/PowerPC/PPCDisassembler.h index 5ffab28620..feed12eabf 100644 --- a/arch/PowerPC/PPCDisassembler.h +++ b/arch/PowerPC/PPCDisassembler.h @@ -4,14 +4,14 @@ #ifndef CS_PPCDISASSEMBLER_H #define CS_PPCDISASSEMBLER_H -#include "capstone/capstone.h" -#include "../../MCRegisterInfo.h" #include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "capstone/capstone.h" void PPC_init(MCRegisterInfo *MRI); bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); + MCInst *instr, uint16_t *size, uint64_t address, + void *info); #endif - diff --git a/arch/PowerPC/PPCGenAsmWriter.inc b/arch/PowerPC/PPCGenAsmWriter.inc index 30ebed3780..a6f507849f 100644 --- a/arch/PowerPC/PPCGenAsmWriter.inc +++ b/arch/PowerPC/PPCGenAsmWriter.inc @@ -11,5929 +11,19809 @@ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O) -{ +static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0, - /* 16 */ 'b', 'd', 'z', 'l', 'a', '+', 32, 0, - /* 24 */ 'b', 'd', 'n', 'z', 'l', 'a', '+', 32, 0, - /* 33 */ 'b', 'd', 'z', 'a', '+', 32, 0, - /* 40 */ 'b', 'd', 'n', 'z', 'a', '+', 32, 0, - /* 48 */ 'b', 'd', 'z', 'l', '+', 32, 0, - /* 55 */ 'b', 'd', 'n', 'z', 'l', '+', 32, 0, - /* 63 */ 'b', 'd', 'z', '+', 32, 0, - /* 69 */ 'b', 'd', 'n', 'z', '+', 32, 0, - /* 76 */ 'b', 'c', 'l', 32, '2', '0', ',', 32, '3', '1', ',', 32, 0, - /* 89 */ 'b', 'c', 't', 'r', 'l', 10, 9, 'l', 'd', 32, '2', ',', 32, 0, - /* 103 */ 'b', 'c', 32, '1', '2', ',', 32, 0, - /* 111 */ 'b', 'c', 'l', 32, '1', '2', ',', 32, 0, - /* 120 */ 'b', 'c', 'l', 'r', 'l', 32, '1', '2', ',', 32, 0, - /* 131 */ 'b', 'c', 'c', 't', 'r', 'l', 32, '1', '2', ',', 32, 0, - /* 143 */ 'b', 'c', 'l', 'r', 32, '1', '2', ',', 32, 0, - /* 153 */ 'b', 'c', 'c', 't', 'r', 32, '1', '2', ',', 32, 0, - /* 164 */ 'b', 'c', 32, '4', ',', 32, 0, - /* 171 */ 'b', 'c', 'l', 32, '4', ',', 32, 0, - /* 179 */ 'b', 'c', 'l', 'r', 'l', 32, '4', ',', 32, 0, - /* 189 */ 'b', 'c', 'c', 't', 'r', 'l', 32, '4', ',', 32, 0, - /* 200 */ 'b', 'c', 'l', 'r', 32, '4', ',', 32, 0, - /* 209 */ 'b', 'c', 'c', 't', 'r', 32, '4', ',', 32, 0, - /* 219 */ 'm', 't', 's', 'p', 'r', 32, '2', '5', '6', ',', 32, 0, - /* 231 */ 'b', 'd', 'z', 'l', 'a', '-', 32, 0, - /* 239 */ 'b', 'd', 'n', 'z', 'l', 'a', '-', 32, 0, - /* 248 */ 'b', 'd', 'z', 'a', '-', 32, 0, - /* 255 */ 'b', 'd', 'n', 'z', 'a', '-', 32, 0, - /* 263 */ 'b', 'd', 'z', 'l', '-', 32, 0, - /* 270 */ 'b', 'd', 'n', 'z', 'l', '-', 32, 0, - /* 278 */ 'b', 'd', 'z', '-', 32, 0, - /* 284 */ 'b', 'd', 'n', 'z', '-', 32, 0, - /* 291 */ 'v', 'c', 'm', 'p', 'n', 'e', 'b', '.', 32, 0, - /* 301 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'b', '.', 32, 0, - /* 312 */ 'e', 'x', 't', 's', 'b', '.', 32, 0, - /* 320 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'b', '.', 32, 0, - /* 331 */ 'f', 's', 'u', 'b', '.', 32, 0, - /* 338 */ 'f', 'm', 's', 'u', 'b', '.', 32, 0, - /* 346 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 32, 0, - /* 355 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'b', '.', 32, 0, - /* 366 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'b', '.', 32, 0, - /* 377 */ 'a', 'd', 'd', 'c', '.', 32, 0, - /* 384 */ 'a', 'n', 'd', 'c', '.', 32, 0, - /* 391 */ 't', 'a', 'b', 'o', 'r', 't', 'd', 'c', '.', 32, 0, - /* 402 */ 's', 'u', 'b', 'f', 'c', '.', 32, 0, - /* 410 */ 's', 'u', 'b', 'i', 'c', '.', 32, 0, - /* 418 */ 'a', 'd', 'd', 'i', 'c', '.', 32, 0, - /* 426 */ 'r', 'l', 'd', 'i', 'c', '.', 32, 0, - /* 434 */ 'b', 'c', 'd', 't', 'r', 'u', 'n', 'c', '.', 32, 0, - /* 445 */ 'b', 'c', 'd', 'u', 't', 'r', 'u', 'n', 'c', '.', 32, 0, - /* 457 */ 'o', 'r', 'c', '.', 32, 0, - /* 463 */ 't', 'a', 'b', 'o', 'r', 't', 'w', 'c', '.', 32, 0, - /* 474 */ 's', 'r', 'a', 'd', '.', 32, 0, - /* 481 */ 'f', 'a', 'd', 'd', '.', 32, 0, - /* 488 */ 'f', 'm', 'a', 'd', 'd', '.', 32, 0, - /* 496 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 32, 0, - /* 505 */ 'm', 'u', 'l', 'h', 'd', '.', 32, 0, - /* 513 */ 'f', 'c', 'f', 'i', 'd', '.', 32, 0, - /* 521 */ 'f', 'c', 't', 'i', 'd', '.', 32, 0, - /* 529 */ 'm', 'u', 'l', 'l', 'd', '.', 32, 0, - /* 537 */ 's', 'l', 'd', '.', 32, 0, - /* 543 */ 'n', 'a', 'n', 'd', '.', 32, 0, - /* 550 */ 't', 'e', 'n', 'd', '.', 32, 0, - /* 557 */ 's', 'r', 'd', '.', 32, 0, - /* 563 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'd', '.', 32, 0, - /* 574 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'd', '.', 32, 0, - /* 585 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'd', '.', 32, 0, - /* 596 */ 'd', 'i', 'v', 'd', '.', 32, 0, - /* 603 */ 'c', 'n', 't', 'l', 'z', 'd', '.', 32, 0, - /* 612 */ 'c', 'n', 't', 't', 'z', 'd', '.', 32, 0, - /* 621 */ 'a', 'd', 'd', 'e', '.', 32, 0, - /* 628 */ 'd', 'i', 'v', 'd', 'e', '.', 32, 0, - /* 636 */ 's', 'u', 'b', 'f', 'e', '.', 32, 0, - /* 644 */ 'a', 'd', 'd', 'm', 'e', '.', 32, 0, - /* 652 */ 's', 'u', 'b', 'f', 'm', 'e', '.', 32, 0, - /* 661 */ 'f', 'r', 'e', '.', 32, 0, - /* 667 */ 'f', 'r', 's', 'q', 'r', 't', 'e', '.', 32, 0, - /* 677 */ 'p', 'a', 's', 't', 'e', '.', 32, 0, - /* 685 */ 'd', 'i', 'v', 'w', 'e', '.', 32, 0, - /* 693 */ 'a', 'd', 'd', 'z', 'e', '.', 32, 0, - /* 701 */ 's', 'u', 'b', 'f', 'z', 'e', '.', 32, 0, - /* 710 */ 's', 'u', 'b', 'f', '.', 32, 0, - /* 717 */ 'm', 't', 'f', 's', 'f', '.', 32, 0, - /* 725 */ 'f', 'n', 'e', 'g', '.', 32, 0, - /* 732 */ 'v', 'c', 'm', 'p', 'n', 'e', 'h', '.', 32, 0, - /* 742 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'h', '.', 32, 0, - /* 753 */ 'e', 'x', 't', 's', 'h', '.', 32, 0, - /* 761 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'h', '.', 32, 0, - /* 772 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'h', '.', 32, 0, - /* 783 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'h', '.', 32, 0, - /* 794 */ 't', 'a', 'b', 'o', 'r', 't', 'd', 'c', 'i', '.', 32, 0, - /* 806 */ 't', 'a', 'b', 'o', 'r', 't', 'w', 'c', 'i', '.', 32, 0, - /* 818 */ 's', 'r', 'a', 'd', 'i', '.', 32, 0, - /* 826 */ 'c', 'l', 'r', 'l', 's', 'l', 'd', 'i', '.', 32, 0, - /* 837 */ 'e', 'x', 't', 'l', 'd', 'i', '.', 32, 0, - /* 846 */ 'a', 'n', 'd', 'i', '.', 32, 0, - /* 853 */ 'c', 'l', 'r', 'r', 'd', 'i', '.', 32, 0, - /* 862 */ 'i', 'n', 's', 'r', 'd', 'i', '.', 32, 0, - /* 871 */ 'r', 'o', 't', 'r', 'd', 'i', '.', 32, 0, - /* 880 */ 'e', 'x', 't', 'r', 'd', 'i', '.', 32, 0, - /* 889 */ 'm', 't', 'f', 's', 'f', 'i', '.', 32, 0, - /* 898 */ 'e', 'x', 't', 's', 'w', 's', 'l', 'i', '.', 32, 0, - /* 909 */ 'r', 'l', 'd', 'i', 'm', 'i', '.', 32, 0, - /* 918 */ 'r', 'l', 'w', 'i', 'm', 'i', '.', 32, 0, - /* 927 */ 's', 'r', 'a', 'w', 'i', '.', 32, 0, - /* 935 */ 'c', 'l', 'r', 'l', 's', 'l', 'w', 'i', '.', 32, 0, - /* 946 */ 'i', 'n', 's', 'l', 'w', 'i', '.', 32, 0, - /* 955 */ 'e', 'x', 't', 'l', 'w', 'i', '.', 32, 0, - /* 964 */ 'c', 'l', 'r', 'r', 'w', 'i', '.', 32, 0, - /* 973 */ 'i', 'n', 's', 'r', 'w', 'i', '.', 32, 0, - /* 982 */ 'r', 'o', 't', 'r', 'w', 'i', '.', 32, 0, - /* 991 */ 'e', 'x', 't', 'r', 'w', 'i', '.', 32, 0, - /* 1000 */ 'r', 'l', 'd', 'c', 'l', '.', 32, 0, - /* 1008 */ 'r', 'l', 'd', 'i', 'c', 'l', '.', 32, 0, - /* 1017 */ 'f', 's', 'e', 'l', '.', 32, 0, - /* 1024 */ 'f', 'm', 'u', 'l', '.', 32, 0, - /* 1031 */ 't', 'r', 'e', 'c', 'l', 'a', 'i', 'm', '.', 32, 0, - /* 1042 */ 'f', 'r', 'i', 'm', '.', 32, 0, - /* 1049 */ 'r', 'l', 'w', 'i', 'n', 'm', '.', 32, 0, - /* 1058 */ 'r', 'l', 'w', 'n', 'm', '.', 32, 0, - /* 1066 */ 'b', 'c', 'd', 'c', 'f', 'n', '.', 32, 0, - /* 1075 */ 'b', 'c', 'd', 'c', 'p', 's', 'g', 'n', '.', 32, 0, - /* 1086 */ 'f', 'c', 'p', 's', 'g', 'n', '.', 32, 0, - /* 1095 */ 'b', 'c', 'd', 's', 'e', 't', 's', 'g', 'n', '.', 32, 0, - /* 1107 */ 't', 'b', 'e', 'g', 'i', 'n', '.', 32, 0, - /* 1116 */ 'f', 'r', 'i', 'n', '.', 32, 0, - /* 1123 */ 'b', 'c', 'd', 'c', 't', 'n', '.', 32, 0, - /* 1132 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 'd', 'p', '.', 32, 0, - /* 1144 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 'd', 'p', '.', 32, 0, - /* 1156 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 'd', 'p', '.', 32, 0, - /* 1168 */ 'v', 'c', 'm', 'p', 'b', 'f', 'p', '.', 32, 0, - /* 1178 */ 'v', 'c', 'm', 'p', 'g', 'e', 'f', 'p', '.', 32, 0, - /* 1189 */ 'v', 'c', 'm', 'p', 'e', 'q', 'f', 'p', '.', 32, 0, - /* 1200 */ 'v', 'c', 'm', 'p', 'g', 't', 'f', 'p', '.', 32, 0, - /* 1211 */ 'f', 'r', 'i', 'p', '.', 32, 0, - /* 1218 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 's', 'p', '.', 32, 0, - /* 1230 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 's', 'p', '.', 32, 0, - /* 1242 */ 'f', 'r', 's', 'p', '.', 32, 0, - /* 1249 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 's', 'p', '.', 32, 0, - /* 1261 */ 'i', 'c', 'b', 'l', 'q', '.', 32, 0, - /* 1269 */ 'b', 'c', 'd', 'c', 'f', 's', 'q', '.', 32, 0, - /* 1279 */ 'b', 'c', 'd', 'c', 't', 's', 'q', '.', 32, 0, - /* 1289 */ 'r', 'l', 'd', 'c', 'r', '.', 32, 0, - /* 1297 */ 'r', 'l', 'd', 'i', 'c', 'r', '.', 32, 0, - /* 1306 */ 'f', 'm', 'r', '.', 32, 0, - /* 1312 */ 'n', 'o', 'r', '.', 32, 0, - /* 1318 */ 'x', 'o', 'r', '.', 32, 0, - /* 1324 */ 'b', 'c', 'd', 's', 'r', '.', 32, 0, - /* 1332 */ 't', 's', 'r', '.', 32, 0, - /* 1338 */ 'f', 'a', 'b', 's', '.', 32, 0, - /* 1345 */ 'f', 'n', 'a', 'b', 's', '.', 32, 0, - /* 1353 */ 'f', 's', 'u', 'b', 's', '.', 32, 0, - /* 1361 */ 'f', 'm', 's', 'u', 'b', 's', '.', 32, 0, - /* 1370 */ 'f', 'n', 'm', 's', 'u', 'b', 's', '.', 32, 0, - /* 1380 */ 'b', 'c', 'd', 's', '.', 32, 0, - /* 1387 */ 'f', 'a', 'd', 'd', 's', '.', 32, 0, - /* 1395 */ 'f', 'm', 'a', 'd', 'd', 's', '.', 32, 0, - /* 1404 */ 'f', 'n', 'm', 'a', 'd', 'd', 's', '.', 32, 0, - /* 1414 */ 'f', 'c', 'f', 'i', 'd', 's', '.', 32, 0, - /* 1423 */ 'f', 'r', 'e', 's', '.', 32, 0, - /* 1430 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 's', '.', 32, 0, - /* 1441 */ 'm', 'f', 'f', 's', '.', 32, 0, - /* 1448 */ 'a', 'n', 'd', 'i', 's', '.', 32, 0, - /* 1456 */ 'f', 'm', 'u', 'l', 's', '.', 32, 0, - /* 1464 */ 'f', 's', 'q', 'r', 't', 's', '.', 32, 0, - /* 1473 */ 'b', 'c', 'd', 'u', 's', '.', 32, 0, - /* 1481 */ 'f', 'c', 'f', 'i', 'd', 'u', 's', '.', 32, 0, - /* 1491 */ 'f', 'd', 'i', 'v', 's', '.', 32, 0, - /* 1499 */ 't', 'a', 'b', 'o', 'r', 't', '.', 32, 0, - /* 1508 */ 'f', 's', 'q', 'r', 't', '.', 32, 0, - /* 1516 */ 'm', 'u', 'l', 'h', 'd', 'u', '.', 32, 0, - /* 1525 */ 'f', 'c', 'f', 'i', 'd', 'u', '.', 32, 0, - /* 1534 */ 'f', 'c', 't', 'i', 'd', 'u', '.', 32, 0, - /* 1543 */ 'd', 'i', 'v', 'd', 'u', '.', 32, 0, - /* 1551 */ 'd', 'i', 'v', 'd', 'e', 'u', '.', 32, 0, - /* 1560 */ 'd', 'i', 'v', 'w', 'e', 'u', '.', 32, 0, - /* 1569 */ 'm', 'u', 'l', 'h', 'w', 'u', '.', 32, 0, - /* 1578 */ 'f', 'c', 't', 'i', 'w', 'u', '.', 32, 0, - /* 1587 */ 'd', 'i', 'v', 'w', 'u', '.', 32, 0, - /* 1595 */ 'f', 'd', 'i', 'v', '.', 32, 0, - /* 1602 */ 'e', 'q', 'v', '.', 32, 0, - /* 1608 */ 's', 'r', 'a', 'w', '.', 32, 0, - /* 1615 */ 'v', 'c', 'm', 'p', 'n', 'e', 'w', '.', 32, 0, - /* 1625 */ 'm', 'u', 'l', 'h', 'w', '.', 32, 0, - /* 1633 */ 'f', 'c', 't', 'i', 'w', '.', 32, 0, - /* 1641 */ 'm', 'u', 'l', 'l', 'w', '.', 32, 0, - /* 1649 */ 's', 'l', 'w', '.', 32, 0, - /* 1655 */ 's', 'r', 'w', '.', 32, 0, - /* 1661 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'w', '.', 32, 0, - /* 1672 */ 'e', 'x', 't', 's', 'w', '.', 32, 0, - /* 1680 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'w', '.', 32, 0, - /* 1691 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'w', '.', 32, 0, - /* 1702 */ 'd', 'i', 'v', 'w', '.', 32, 0, - /* 1709 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'w', '.', 32, 0, - /* 1720 */ 'c', 'n', 't', 'l', 'z', 'w', '.', 32, 0, - /* 1729 */ 'c', 'n', 't', 't', 'z', 'w', '.', 32, 0, - /* 1738 */ 's', 't', 'b', 'c', 'x', '.', 32, 0, - /* 1746 */ 's', 't', 'd', 'c', 'x', '.', 32, 0, - /* 1754 */ 's', 't', 'h', 'c', 'x', '.', 32, 0, - /* 1762 */ 's', 't', 'w', 'c', 'x', '.', 32, 0, - /* 1770 */ 't', 'l', 'b', 's', 'x', '.', 32, 0, - /* 1778 */ 'f', 'c', 't', 'i', 'd', 'z', '.', 32, 0, - /* 1787 */ 'b', 'c', 'd', 'c', 'f', 'z', '.', 32, 0, - /* 1796 */ 'f', 'r', 'i', 'z', '.', 32, 0, - /* 1803 */ 'b', 'c', 'd', 'c', 't', 'z', '.', 32, 0, - /* 1812 */ 'f', 'c', 't', 'i', 'd', 'u', 'z', '.', 32, 0, - /* 1822 */ 'f', 'c', 't', 'i', 'w', 'u', 'z', '.', 32, 0, - /* 1832 */ 'f', 'c', 't', 'i', 'w', 'z', '.', 32, 0, - /* 1841 */ 'm', 't', 'f', 's', 'b', '0', 32, 0, - /* 1849 */ 'm', 't', 'f', 's', 'b', '1', 32, 0, - /* 1857 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 32, 0, - /* 1879 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 32, 0, - /* 1901 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'a', '8', 32, 0, - /* 1915 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'd', '8', 32, 0, - /* 1929 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'r', '8', 32, 0, - /* 1943 */ 'U', 'P', 'D', 'A', 'T', 'E', '_', 'V', 'R', 'S', 'A', 'V', 'E', 32, 0, - /* 1958 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, - /* 1977 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, - /* 1994 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'a', 32, 0, - /* 2007 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'f', 'a', 'a', 32, 0, - /* 2020 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'f', 'a', 'a', 32, 0, - /* 2033 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 'a', 32, 0, - /* 2044 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 'a', 32, 0, - /* 2055 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'i', 'a', 'a', 32, 0, - /* 2068 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'i', 'a', 'a', 32, 0, - /* 2081 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 'a', 32, 0, - /* 2092 */ 'e', 'v', 'm', 'h', 'e', 'g', 'u', 'm', 'i', 'a', 'a', 32, 0, - /* 2105 */ 'e', 'v', 'm', 'h', 'o', 'g', 'u', 'm', 'i', 'a', 'a', 32, 0, - /* 2118 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 'a', 32, 0, - /* 2129 */ 'd', 'c', 'b', 'a', 32, 0, - /* 2135 */ 'b', 'c', 'a', 32, 0, - /* 2140 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 32, 0, - /* 2151 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'f', 'a', 32, 0, - /* 2162 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 32, 0, - /* 2173 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 32, 0, - /* 2183 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 32, 0, - /* 2194 */ 'e', 'v', 'm', 'w', 'h', 's', 's', 'f', 'a', 32, 0, - /* 2205 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 32, 0, - /* 2216 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 32, 0, - /* 2226 */ 'l', 'h', 'a', 32, 0, - /* 2231 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 32, 0, - /* 2242 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'i', 'a', 32, 0, - /* 2253 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 32, 0, - /* 2264 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 32, 0, - /* 2274 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 32, 0, - /* 2285 */ 'e', 'v', 'm', 'w', 'h', 'u', 'm', 'i', 'a', 32, 0, - /* 2296 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 32, 0, - /* 2307 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 32, 0, - /* 2318 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 32, 0, - /* 2328 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'i', 'a', 32, 0, - /* 2340 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'i', 'a', 32, 0, - /* 2351 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'i', 'a', 32, 0, - /* 2363 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'i', 'a', 32, 0, - /* 2374 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'i', 'a', 32, 0, - /* 2387 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'i', 'a', 32, 0, - /* 2399 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'i', 'a', 32, 0, - /* 2412 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'i', 'a', 32, 0, - /* 2424 */ 'b', 'l', 'a', 32, 0, - /* 2429 */ 'b', 'c', 'l', 'a', 32, 0, - /* 2435 */ 'b', 'd', 'z', 'l', 'a', 32, 0, - /* 2442 */ 'b', 'd', 'n', 'z', 'l', 'a', 32, 0, - /* 2450 */ 'e', 'v', 'm', 'r', 'a', 32, 0, - /* 2457 */ 'l', 'w', 'a', 32, 0, - /* 2462 */ 'm', 't', 'v', 's', 'r', 'w', 'a', 32, 0, - /* 2471 */ 'q', 'v', 'l', 'f', 'i', 'w', 'a', 'x', 'a', 32, 0, - /* 2482 */ 'q', 'v', 'l', 'f', 'c', 'd', 'x', 'a', 32, 0, - /* 2492 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'a', 32, 0, - /* 2503 */ 'q', 'v', 'l', 'f', 'd', 'x', 'a', 32, 0, - /* 2512 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'a', 32, 0, - /* 2522 */ 'q', 'v', 'l', 'f', 'c', 's', 'x', 'a', 32, 0, - /* 2532 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'a', 32, 0, - /* 2543 */ 'q', 'v', 'l', 'f', 's', 'x', 'a', 32, 0, - /* 2552 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'a', 32, 0, - /* 2562 */ 'q', 'v', 'l', 'f', 'c', 'd', 'u', 'x', 'a', 32, 0, - /* 2573 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'a', 32, 0, - /* 2585 */ 'q', 'v', 'l', 'f', 'd', 'u', 'x', 'a', 32, 0, - /* 2595 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'a', 32, 0, - /* 2606 */ 'q', 'v', 'l', 'f', 'c', 's', 'u', 'x', 'a', 32, 0, - /* 2617 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'a', 32, 0, - /* 2629 */ 'q', 'v', 'l', 'f', 's', 'u', 'x', 'a', 32, 0, - /* 2639 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'a', 32, 0, - /* 2650 */ 'q', 'v', 's', 't', 'f', 'i', 'w', 'x', 'a', 32, 0, - /* 2661 */ 'q', 'v', 'l', 'f', 'i', 'w', 'z', 'x', 'a', 32, 0, - /* 2672 */ 'b', 'd', 'z', 'a', 32, 0, - /* 2678 */ 'b', 'd', 'n', 'z', 'a', 32, 0, - /* 2685 */ 'v', 's', 'r', 'a', 'b', 32, 0, - /* 2692 */ 'r', 'f', 'e', 'b', 'b', 32, 0, - /* 2699 */ 'v', 'c', 'l', 'z', 'l', 's', 'b', 'b', 32, 0, - /* 2709 */ 'v', 'c', 't', 'z', 'l', 's', 'b', 'b', 32, 0, - /* 2719 */ 'v', 'c', 'm', 'p', 'n', 'e', 'b', 32, 0, - /* 2728 */ 'v', 'm', 'r', 'g', 'h', 'b', 32, 0, - /* 2736 */ 'x', 'x', 's', 'p', 'l', 't', 'i', 'b', 32, 0, - /* 2746 */ 'v', 'm', 'r', 'g', 'l', 'b', 32, 0, - /* 2754 */ 'v', 'r', 'l', 'b', 32, 0, - /* 2760 */ 'v', 's', 'l', 'b', 32, 0, - /* 2766 */ 'v', 'p', 'm', 's', 'u', 'm', 'b', 32, 0, - /* 2775 */ 'c', 'm', 'p', 'b', 32, 0, - /* 2781 */ 'c', 'm', 'p', 'e', 'q', 'b', 32, 0, - /* 2789 */ 'c', 'm', 'p', 'r', 'b', 32, 0, - /* 2796 */ 'v', 's', 'r', 'b', 32, 0, - /* 2802 */ 'v', 'm', 'u', 'l', 'e', 's', 'b', 32, 0, - /* 2811 */ 'v', 'a', 'v', 'g', 's', 'b', 32, 0, - /* 2819 */ 'v', 'u', 'p', 'k', 'h', 's', 'b', 32, 0, - /* 2828 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'b', 32, 0, - /* 2838 */ 'v', 'u', 'p', 'k', 'l', 's', 'b', 32, 0, - /* 2847 */ 'v', 'm', 'i', 'n', 's', 'b', 32, 0, - /* 2855 */ 'v', 'm', 'u', 'l', 'o', 's', 'b', 32, 0, - /* 2864 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'b', 32, 0, - /* 2874 */ 'e', 'v', 'e', 'x', 't', 's', 'b', 32, 0, - /* 2883 */ 'v', 'm', 'a', 'x', 's', 'b', 32, 0, - /* 2891 */ 's', 'e', 't', 'b', 32, 0, - /* 2897 */ 'm', 'f', 't', 'b', 32, 0, - /* 2903 */ 'v', 's', 'p', 'l', 't', 'b', 32, 0, - /* 2911 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'b', 32, 0, - /* 2921 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'b', 32, 0, - /* 2931 */ 's', 't', 'b', 32, 0, - /* 2936 */ 'v', 'a', 'b', 's', 'd', 'u', 'b', 32, 0, - /* 2945 */ 'v', 'm', 'u', 'l', 'e', 'u', 'b', 32, 0, - /* 2954 */ 'v', 'a', 'v', 'g', 'u', 'b', 32, 0, - /* 2962 */ 'v', 'm', 'i', 'n', 'u', 'b', 32, 0, - /* 2970 */ 'v', 'm', 'u', 'l', 'o', 'u', 'b', 32, 0, - /* 2979 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'b', 32, 0, - /* 2989 */ 'e', 'f', 'd', 's', 'u', 'b', 32, 0, - /* 2997 */ 'q', 'v', 'f', 's', 'u', 'b', 32, 0, - /* 3005 */ 'q', 'v', 'f', 'm', 's', 'u', 'b', 32, 0, - /* 3014 */ 'q', 'v', 'f', 'n', 'm', 's', 'u', 'b', 32, 0, - /* 3024 */ 'e', 'f', 's', 's', 'u', 'b', 32, 0, - /* 3032 */ 'e', 'v', 'f', 's', 's', 'u', 'b', 32, 0, - /* 3041 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'b', 32, 0, - /* 3053 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'b', 32, 0, - /* 3063 */ 'v', 'm', 'a', 'x', 'u', 'b', 32, 0, - /* 3071 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'b', 32, 0, - /* 3081 */ 'v', 'c', 'l', 'z', 'b', 32, 0, - /* 3088 */ 'v', 'c', 't', 'z', 'b', 32, 0, - /* 3095 */ 'b', 'c', 32, 0, - /* 3099 */ 'a', 'd', 'd', 'c', 32, 0, - /* 3105 */ 'x', 'x', 'l', 'a', 'n', 'd', 'c', 32, 0, - /* 3114 */ 'c', 'r', 'a', 'n', 'd', 'c', 32, 0, - /* 3122 */ 'e', 'v', 'a', 'n', 'd', 'c', 32, 0, - /* 3130 */ 's', 'u', 'b', 'f', 'c', 32, 0, - /* 3137 */ 's', 'u', 'b', 'i', 'c', 32, 0, - /* 3144 */ 'a', 'd', 'd', 'i', 'c', 32, 0, - /* 3151 */ 'r', 'l', 'd', 'i', 'c', 32, 0, - /* 3158 */ 's', 'u', 'b', 'f', 'i', 'c', 32, 0, - /* 3166 */ 'x', 's', 'r', 'd', 'p', 'i', 'c', 32, 0, - /* 3175 */ 'x', 'v', 'r', 'd', 'p', 'i', 'c', 32, 0, - /* 3184 */ 'x', 'v', 'r', 's', 'p', 'i', 'c', 32, 0, - /* 3193 */ 'i', 'c', 'b', 'l', 'c', 32, 0, - /* 3200 */ 'b', 'r', 'i', 'n', 'c', 32, 0, - /* 3207 */ 's', 'y', 'n', 'c', 32, 0, - /* 3213 */ 'x', 'x', 'l', 'o', 'r', 'c', 32, 0, - /* 3221 */ 'c', 'r', 'o', 'r', 'c', 32, 0, - /* 3228 */ 'e', 'v', 'o', 'r', 'c', 32, 0, - /* 3235 */ 's', 'c', 32, 0, - /* 3239 */ 'v', 'e', 'x', 't', 's', 'b', '2', 'd', 32, 0, - /* 3249 */ 'v', 'e', 'x', 't', 's', 'h', '2', 'd', 32, 0, - /* 3259 */ 'v', 'e', 'x', 't', 's', 'w', '2', 'd', 32, 0, - /* 3269 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'd', 32, 0, - /* 3282 */ 'v', 's', 'h', 'a', 's', 'i', 'g', 'm', 'a', 'd', 32, 0, - /* 3294 */ 'v', 's', 'r', 'a', 'd', 32, 0, - /* 3301 */ 'v', 'g', 'b', 'b', 'd', 32, 0, - /* 3308 */ 'v', 'p', 'r', 't', 'y', 'b', 'd', 32, 0, - /* 3317 */ 'e', 'f', 'd', 'a', 'd', 'd', 32, 0, - /* 3325 */ 'q', 'v', 'f', 'a', 'd', 'd', 32, 0, - /* 3333 */ 'q', 'v', 'f', 'm', 'a', 'd', 'd', 32, 0, - /* 3342 */ 'q', 'v', 'f', 'n', 'm', 'a', 'd', 'd', 32, 0, - /* 3352 */ 'q', 'v', 'f', 'x', 'x', 'c', 'p', 'n', 'm', 'a', 'd', 'd', 32, 0, - /* 3366 */ 'q', 'v', 'f', 'x', 'x', 'n', 'p', 'm', 'a', 'd', 'd', 32, 0, - /* 3379 */ 'q', 'v', 'f', 'x', 'm', 'a', 'd', 'd', 32, 0, - /* 3389 */ 'q', 'v', 'f', 'x', 'x', 'm', 'a', 'd', 'd', 32, 0, - /* 3400 */ 'e', 'f', 's', 'a', 'd', 'd', 32, 0, - /* 3408 */ 'e', 'v', 'f', 's', 'a', 'd', 'd', 32, 0, - /* 3417 */ 'e', 'v', 'l', 'd', 'd', 32, 0, - /* 3424 */ 'm', 't', 'v', 's', 'r', 'd', 'd', 32, 0, - /* 3433 */ 'e', 'v', 's', 't', 'd', 'd', 32, 0, - /* 3441 */ 'e', 'f', 's', 'c', 'f', 'd', 32, 0, - /* 3449 */ 'l', 'f', 'd', 32, 0, - /* 3454 */ 's', 't', 'f', 'd', 32, 0, - /* 3460 */ 'v', 'n', 'e', 'g', 'd', 32, 0, - /* 3467 */ 'm', 'a', 'd', 'd', 'h', 'd', 32, 0, - /* 3475 */ 'm', 'u', 'l', 'h', 'd', 32, 0, - /* 3482 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 32, 0, - /* 3491 */ 'e', 'f', 'd', 'c', 'f', 's', 'i', 'd', 32, 0, - /* 3501 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 32, 0, - /* 3510 */ 'e', 'f', 'd', 'c', 'f', 'u', 'i', 'd', 32, 0, - /* 3520 */ 't', 'l', 'b', 'l', 'd', 32, 0, - /* 3527 */ 'm', 'a', 'd', 'd', 'l', 'd', 32, 0, - /* 3535 */ 'm', 'u', 'l', 'l', 'd', 32, 0, - /* 3542 */ 'c', 'm', 'p', 'l', 'd', 32, 0, - /* 3549 */ 'm', 'f', 'v', 's', 'r', 'l', 'd', 32, 0, - /* 3558 */ 'v', 'r', 'l', 'd', 32, 0, - /* 3564 */ 'v', 's', 'l', 'd', 32, 0, - /* 3570 */ 'v', 'b', 'p', 'e', 'r', 'm', 'd', 32, 0, - /* 3579 */ 'v', 'p', 'm', 's', 'u', 'm', 'd', 32, 0, - /* 3588 */ 'x', 'x', 'l', 'a', 'n', 'd', 32, 0, - /* 3596 */ 'x', 'x', 'l', 'n', 'a', 'n', 'd', 32, 0, - /* 3605 */ 'c', 'r', 'n', 'a', 'n', 'd', 32, 0, - /* 3613 */ 'e', 'v', 'n', 'a', 'n', 'd', 32, 0, - /* 3621 */ 'c', 'r', 'a', 'n', 'd', 32, 0, - /* 3628 */ 'e', 'v', 'a', 'n', 'd', 32, 0, - /* 3635 */ 'c', 'm', 'p', 'd', 32, 0, - /* 3641 */ 'x', 'x', 'b', 'r', 'd', 32, 0, - /* 3648 */ 'm', 't', 'm', 's', 'r', 'd', 32, 0, - /* 3656 */ 'm', 'f', 'v', 's', 'r', 'd', 32, 0, - /* 3664 */ 'm', 't', 'v', 's', 'r', 'd', 32, 0, - /* 3672 */ 'm', 'o', 'd', 's', 'd', 32, 0, - /* 3679 */ 'v', 'm', 'i', 'n', 's', 'd', 32, 0, - /* 3687 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'd', 32, 0, - /* 3697 */ 'v', 'm', 'a', 'x', 's', 'd', 32, 0, - /* 3705 */ 'l', 'x', 's', 'd', 32, 0, - /* 3711 */ 's', 't', 'x', 's', 'd', 32, 0, - /* 3718 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'd', 32, 0, - /* 3729 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'd', 32, 0, - /* 3739 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'd', 32, 0, - /* 3749 */ 's', 't', 'd', 32, 0, - /* 3754 */ 'm', 'o', 'd', 'u', 'd', 32, 0, - /* 3761 */ 'v', 'm', 'i', 'n', 'u', 'd', 32, 0, - /* 3769 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'd', 32, 0, - /* 3779 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'd', 32, 0, - /* 3789 */ 'v', 'm', 'a', 'x', 'u', 'd', 32, 0, - /* 3797 */ 'd', 'i', 'v', 'd', 32, 0, - /* 3803 */ 'v', 'c', 'l', 'z', 'd', 32, 0, - /* 3810 */ 'c', 'n', 't', 'l', 'z', 'd', 32, 0, - /* 3818 */ 'v', 'c', 't', 'z', 'd', 32, 0, - /* 3825 */ 'c', 'n', 't', 't', 'z', 'd', 32, 0, - /* 3833 */ 'm', 'f', 'b', 'h', 'r', 'b', 'e', 32, 0, - /* 3842 */ 'm', 'f', 'f', 's', 'c', 'e', 32, 0, - /* 3850 */ 'a', 'd', 'd', 'e', 32, 0, - /* 3856 */ 'd', 'i', 'v', 'd', 'e', 32, 0, - /* 3863 */ 's', 'l', 'b', 'm', 'f', 'e', 'e', 32, 0, - /* 3872 */ 'w', 'r', 't', 'e', 'e', 32, 0, - /* 3879 */ 's', 'u', 'b', 'f', 'e', 32, 0, - /* 3886 */ 'e', 'v', 'l', 'w', 'h', 'e', 32, 0, - /* 3894 */ 'e', 'v', 's', 't', 'w', 'h', 'e', 32, 0, - /* 3903 */ 's', 'l', 'b', 'i', 'e', 32, 0, - /* 3910 */ 't', 'l', 'b', 'i', 'e', 32, 0, - /* 3917 */ 'a', 'd', 'd', 'm', 'e', 32, 0, - /* 3924 */ 's', 'u', 'b', 'f', 'm', 'e', 32, 0, - /* 3932 */ 't', 'l', 'b', 'r', 'e', 32, 0, - /* 3939 */ 'q', 'v', 'f', 'r', 'e', 32, 0, - /* 3946 */ 's', 'l', 'b', 'm', 't', 'e', 32, 0, - /* 3954 */ 'q', 'v', 'f', 'r', 's', 'q', 'r', 't', 'e', 32, 0, - /* 3965 */ 'p', 'a', 's', 't', 'e', 32, 0, - /* 3972 */ 't', 'l', 'b', 'w', 'e', 32, 0, - /* 3979 */ 'd', 'i', 'v', 'w', 'e', 32, 0, - /* 3986 */ 'e', 'v', 's', 't', 'w', 'w', 'e', 32, 0, - /* 3995 */ 'a', 'd', 'd', 'z', 'e', 32, 0, - /* 4002 */ 's', 'u', 'b', 'f', 'z', 'e', 32, 0, - /* 4010 */ 'd', 'c', 'b', 'f', 32, 0, - /* 4016 */ 's', 'u', 'b', 'f', 32, 0, - /* 4022 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 32, 0, - /* 4032 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'f', 32, 0, - /* 4042 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 32, 0, - /* 4052 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 32, 0, - /* 4061 */ 'm', 'c', 'r', 'f', 32, 0, - /* 4067 */ 'm', 'f', 'o', 'c', 'r', 'f', 32, 0, - /* 4075 */ 'm', 't', 'o', 'c', 'r', 'f', 32, 0, - /* 4083 */ 'm', 't', 'c', 'r', 'f', 32, 0, - /* 4090 */ 'e', 'f', 'd', 'c', 'f', 's', 'f', 32, 0, - /* 4099 */ 'e', 'f', 's', 'c', 'f', 's', 'f', 32, 0, - /* 4108 */ 'e', 'v', 'f', 's', 'c', 'f', 's', 'f', 32, 0, - /* 4118 */ 'm', 't', 'f', 's', 'f', 32, 0, - /* 4125 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 32, 0, - /* 4135 */ 'e', 'v', 'm', 'w', 'h', 's', 's', 'f', 32, 0, - /* 4145 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 32, 0, - /* 4155 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 32, 0, - /* 4164 */ 'e', 'f', 'd', 'c', 't', 's', 'f', 32, 0, - /* 4173 */ 'e', 'f', 's', 'c', 't', 's', 'f', 32, 0, - /* 4182 */ 'e', 'v', 'f', 's', 'c', 't', 's', 'f', 32, 0, - /* 4192 */ 'e', 'f', 'd', 'c', 'f', 'u', 'f', 32, 0, - /* 4201 */ 'e', 'f', 's', 'c', 'f', 'u', 'f', 32, 0, - /* 4210 */ 'e', 'v', 'f', 's', 'c', 'f', 'u', 'f', 32, 0, - /* 4220 */ 'e', 'f', 'd', 'c', 't', 'u', 'f', 32, 0, - /* 4229 */ 'e', 'f', 's', 'c', 't', 'u', 'f', 32, 0, - /* 4238 */ 's', 'l', 'b', 'i', 'e', 'g', 32, 0, - /* 4246 */ 'e', 'f', 'd', 'n', 'e', 'g', 32, 0, - /* 4254 */ 'q', 'v', 'f', 'n', 'e', 'g', 32, 0, - /* 4262 */ 'e', 'f', 's', 'n', 'e', 'g', 32, 0, - /* 4270 */ 'e', 'v', 'f', 's', 'n', 'e', 'g', 32, 0, - /* 4279 */ 'e', 'v', 'n', 'e', 'g', 32, 0, - /* 4286 */ 'v', 's', 'r', 'a', 'h', 32, 0, - /* 4293 */ 'e', 'v', 'l', 'd', 'h', 32, 0, - /* 4300 */ 'e', 'v', 's', 't', 'd', 'h', 32, 0, - /* 4308 */ 'v', 'c', 'm', 'p', 'n', 'e', 'h', 32, 0, - /* 4317 */ 'v', 'm', 'r', 'g', 'h', 'h', 32, 0, - /* 4325 */ 'v', 'm', 'r', 'g', 'l', 'h', 32, 0, - /* 4333 */ 'v', 'r', 'l', 'h', 32, 0, - /* 4339 */ 'v', 's', 'l', 'h', 32, 0, - /* 4345 */ 'v', 'p', 'm', 's', 'u', 'm', 'h', 32, 0, - /* 4354 */ 'x', 'x', 'b', 'r', 'h', 32, 0, - /* 4361 */ 'v', 's', 'r', 'h', 32, 0, - /* 4367 */ 'v', 'm', 'u', 'l', 'e', 's', 'h', 32, 0, - /* 4376 */ 'v', 'a', 'v', 'g', 's', 'h', 32, 0, - /* 4384 */ 'v', 'u', 'p', 'k', 'h', 's', 'h', 32, 0, - /* 4393 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'h', 32, 0, - /* 4403 */ 'v', 'u', 'p', 'k', 'l', 's', 'h', 32, 0, - /* 4412 */ 'v', 'm', 'i', 'n', 's', 'h', 32, 0, - /* 4420 */ 'v', 'm', 'u', 'l', 'o', 's', 'h', 32, 0, - /* 4429 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'h', 32, 0, - /* 4439 */ 'e', 'v', 'e', 'x', 't', 's', 'h', 32, 0, - /* 4448 */ 'v', 'm', 'a', 'x', 's', 'h', 32, 0, - /* 4456 */ 'v', 's', 'p', 'l', 't', 'h', 32, 0, - /* 4464 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'h', 32, 0, - /* 4474 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'h', 32, 0, - /* 4484 */ 's', 't', 'h', 32, 0, - /* 4489 */ 'v', 'a', 'b', 's', 'd', 'u', 'h', 32, 0, - /* 4498 */ 'v', 'm', 'u', 'l', 'e', 'u', 'h', 32, 0, - /* 4507 */ 'v', 'a', 'v', 'g', 'u', 'h', 32, 0, - /* 4515 */ 'v', 'm', 'i', 'n', 'u', 'h', 32, 0, - /* 4523 */ 'v', 'm', 'u', 'l', 'o', 'u', 'h', 32, 0, - /* 4532 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'h', 32, 0, - /* 4542 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'h', 32, 0, - /* 4554 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'h', 32, 0, - /* 4564 */ 'v', 'm', 'a', 'x', 'u', 'h', 32, 0, - /* 4572 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'h', 32, 0, - /* 4582 */ 'v', 'c', 'l', 'z', 'h', 32, 0, - /* 4589 */ 'v', 'c', 't', 'z', 'h', 32, 0, - /* 4596 */ 'd', 'c', 'b', 'i', 32, 0, - /* 4602 */ 'i', 'c', 'b', 'i', 32, 0, - /* 4608 */ 's', 'u', 'b', 'i', 32, 0, - /* 4614 */ 'd', 'c', 'c', 'c', 'i', 32, 0, - /* 4621 */ 'i', 'c', 'c', 'c', 'i', 32, 0, - /* 4628 */ 'q', 'v', 'g', 'p', 'c', 'i', 32, 0, - /* 4636 */ 's', 'r', 'a', 'd', 'i', 32, 0, - /* 4643 */ 'a', 'd', 'd', 'i', 32, 0, - /* 4649 */ 'c', 'm', 'p', 'l', 'd', 'i', 32, 0, - /* 4657 */ 'c', 'l', 'r', 'l', 's', 'l', 'd', 'i', 32, 0, - /* 4667 */ 'e', 'x', 't', 'l', 'd', 'i', 32, 0, - /* 4675 */ 'x', 'x', 'p', 'e', 'r', 'm', 'd', 'i', 32, 0, - /* 4685 */ 'c', 'm', 'p', 'd', 'i', 32, 0, - /* 4692 */ 'c', 'l', 'r', 'r', 'd', 'i', 32, 0, - /* 4700 */ 'i', 'n', 's', 'r', 'd', 'i', 32, 0, - /* 4708 */ 'r', 'o', 't', 'r', 'd', 'i', 32, 0, - /* 4716 */ 'e', 'x', 't', 'r', 'd', 'i', 32, 0, - /* 4724 */ 't', 'd', 'i', 32, 0, - /* 4729 */ 'w', 'r', 't', 'e', 'e', 'i', 32, 0, - /* 4737 */ 'm', 't', 'f', 's', 'f', 'i', 32, 0, - /* 4745 */ 'e', 'v', 's', 'p', 'l', 'a', 't', 'f', 'i', 32, 0, - /* 4756 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'h', 'i', 32, 0, - /* 4767 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'l', 'o', 'h', 'i', 32, 0, - /* 4780 */ 't', 'l', 'b', 'l', 'i', 32, 0, - /* 4787 */ 'm', 'u', 'l', 'l', 'i', 32, 0, - /* 4794 */ 'e', 'x', 't', 's', 'w', 's', 'l', 'i', 32, 0, - /* 4804 */ 'v', 'r', 'l', 'd', 'm', 'i', 32, 0, - /* 4812 */ 'r', 'l', 'd', 'i', 'm', 'i', 32, 0, - /* 4820 */ 'r', 'l', 'w', 'i', 'm', 'i', 32, 0, - /* 4828 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 32, 0, - /* 4838 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'i', 32, 0, - /* 4848 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 32, 0, - /* 4858 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 32, 0, - /* 4867 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 32, 0, - /* 4877 */ 'e', 'v', 'm', 'w', 'h', 'u', 'm', 'i', 32, 0, - /* 4887 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 32, 0, - /* 4897 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 32, 0, - /* 4907 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 32, 0, - /* 4916 */ 'v', 'r', 'l', 'w', 'm', 'i', 32, 0, - /* 4924 */ 'q', 'v', 'a', 'l', 'i', 'g', 'n', 'i', 32, 0, - /* 4934 */ 'm', 'f', 'f', 's', 'c', 'r', 'n', 'i', 32, 0, - /* 4944 */ 'm', 'f', 'f', 's', 'c', 'd', 'r', 'n', 'i', 32, 0, - /* 4955 */ 'v', 's', 'l', 'd', 'o', 'i', 32, 0, - /* 4963 */ 'x', 's', 'r', 'd', 'p', 'i', 32, 0, - /* 4971 */ 'x', 'v', 'r', 'd', 'p', 'i', 32, 0, - /* 4979 */ 'x', 's', 'r', 'q', 'p', 'i', 32, 0, - /* 4987 */ 'x', 'v', 'r', 's', 'p', 'i', 32, 0, - /* 4995 */ 'x', 'o', 'r', 'i', 32, 0, - /* 5001 */ 'e', 'f', 'd', 'c', 'f', 's', 'i', 32, 0, - /* 5010 */ 'e', 'f', 's', 'c', 'f', 's', 'i', 32, 0, - /* 5019 */ 'e', 'v', 'f', 's', 'c', 'f', 's', 'i', 32, 0, - /* 5029 */ 'e', 'f', 'd', 'c', 't', 's', 'i', 32, 0, - /* 5038 */ 'e', 'f', 's', 'c', 't', 's', 'i', 32, 0, - /* 5047 */ 'e', 'v', 'f', 's', 'c', 't', 's', 'i', 32, 0, - /* 5057 */ 'q', 'v', 'e', 's', 'p', 'l', 'a', 't', 'i', 32, 0, - /* 5068 */ 'e', 'v', 's', 'p', 'l', 'a', 't', 'i', 32, 0, - /* 5078 */ 'e', 'f', 'd', 'c', 'f', 'u', 'i', 32, 0, - /* 5087 */ 'e', 'f', 's', 'c', 'f', 'u', 'i', 32, 0, - /* 5096 */ 'e', 'v', 'f', 's', 'c', 'f', 'u', 'i', 32, 0, - /* 5106 */ 'e', 'f', 'd', 'c', 't', 'u', 'i', 32, 0, - /* 5115 */ 'e', 'f', 's', 'c', 't', 'u', 'i', 32, 0, - /* 5124 */ 'e', 'v', 'f', 's', 'c', 't', 'u', 'i', 32, 0, - /* 5134 */ 's', 'r', 'a', 'w', 'i', 32, 0, - /* 5141 */ 'x', 'x', 's', 'l', 'd', 'w', 'i', 32, 0, - /* 5150 */ 'c', 'm', 'p', 'l', 'w', 'i', 32, 0, - /* 5158 */ 'e', 'v', 'r', 'l', 'w', 'i', 32, 0, - /* 5166 */ 'c', 'l', 'r', 'l', 's', 'l', 'w', 'i', 32, 0, - /* 5176 */ 'i', 'n', 's', 'l', 'w', 'i', 32, 0, - /* 5184 */ 'e', 'v', 's', 'l', 'w', 'i', 32, 0, - /* 5192 */ 'e', 'x', 't', 'l', 'w', 'i', 32, 0, - /* 5200 */ 'c', 'm', 'p', 'w', 'i', 32, 0, - /* 5207 */ 'c', 'l', 'r', 'r', 'w', 'i', 32, 0, - /* 5215 */ 'i', 'n', 's', 'r', 'w', 'i', 32, 0, - /* 5223 */ 'r', 'o', 't', 'r', 'w', 'i', 32, 0, - /* 5231 */ 'e', 'x', 't', 'r', 'w', 'i', 32, 0, - /* 5239 */ 'l', 's', 'w', 'i', 32, 0, - /* 5245 */ 's', 't', 's', 'w', 'i', 32, 0, - /* 5252 */ 't', 'w', 'i', 32, 0, - /* 5257 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'i', 32, 0, - /* 5268 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'i', 32, 0, - /* 5278 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'i', 32, 0, - /* 5289 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'i', 32, 0, - /* 5299 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'i', 32, 0, - /* 5311 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'i', 32, 0, - /* 5322 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'i', 32, 0, - /* 5334 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'i', 32, 0, - /* 5345 */ 't', 'c', 'h', 'e', 'c', 'k', 32, 0, - /* 5353 */ 'q', 'v', 'f', 'l', 'o', 'g', 'i', 'c', 'a', 'l', 32, 0, - /* 5365 */ 'b', 'l', 32, 0, - /* 5369 */ 'b', 'c', 'l', 32, 0, - /* 5374 */ 'r', 'l', 'd', 'c', 'l', 32, 0, - /* 5381 */ 'r', 'l', 'd', 'i', 'c', 'l', 32, 0, - /* 5389 */ 't', 'l', 'b', 'i', 'e', 'l', 32, 0, - /* 5397 */ 'q', 'v', 'f', 's', 'e', 'l', 32, 0, - /* 5405 */ 'i', 's', 'e', 'l', 32, 0, - /* 5411 */ 'v', 's', 'e', 'l', 32, 0, - /* 5417 */ 'x', 'x', 's', 'e', 'l', 32, 0, - /* 5424 */ 'd', 'c', 'b', 'f', 'l', 32, 0, - /* 5431 */ 'l', 'x', 'v', 'l', 'l', 32, 0, - /* 5438 */ 's', 't', 'x', 'v', 'l', 'l', 32, 0, - /* 5446 */ 'b', 'c', 'l', 'r', 'l', 32, 0, - /* 5453 */ 'b', 'c', 'c', 't', 'r', 'l', 32, 0, - /* 5461 */ 'm', 'f', 'f', 's', 'l', 32, 0, - /* 5468 */ 'l', 'v', 's', 'l', 32, 0, - /* 5474 */ 'e', 'f', 'd', 'm', 'u', 'l', 32, 0, - /* 5482 */ 'q', 'v', 'f', 'm', 'u', 'l', 32, 0, - /* 5490 */ 'e', 'f', 's', 'm', 'u', 'l', 32, 0, - /* 5498 */ 'e', 'v', 'f', 's', 'm', 'u', 'l', 32, 0, - /* 5507 */ 'q', 'v', 'f', 'x', 'm', 'u', 'l', 32, 0, - /* 5516 */ 'l', 'x', 'v', 'l', 32, 0, - /* 5522 */ 's', 't', 'x', 'v', 'l', 32, 0, - /* 5529 */ 'l', 'v', 'x', 'l', 32, 0, - /* 5535 */ 's', 't', 'v', 'x', 'l', 32, 0, - /* 5542 */ 'd', 'c', 'b', 'z', 'l', 32, 0, - /* 5549 */ 'b', 'd', 'z', 'l', 32, 0, - /* 5555 */ 'b', 'd', 'n', 'z', 'l', 32, 0, - /* 5562 */ 'v', 'm', 's', 'u', 'm', 'm', 'b', 'm', 32, 0, - /* 5572 */ 'v', 's', 'u', 'b', 'u', 'b', 'm', 32, 0, - /* 5581 */ 'v', 'a', 'd', 'd', 'u', 'b', 'm', 32, 0, - /* 5590 */ 'v', 'm', 's', 'u', 'm', 'u', 'b', 'm', 32, 0, - /* 5600 */ 'v', 's', 'u', 'b', 'u', 'd', 'm', 32, 0, - /* 5609 */ 'v', 'a', 'd', 'd', 'u', 'd', 'm', 32, 0, - /* 5618 */ 'v', 'm', 's', 'u', 'm', 's', 'h', 'm', 32, 0, - /* 5628 */ 'v', 's', 'u', 'b', 'u', 'h', 'm', 32, 0, - /* 5637 */ 'v', 'm', 'l', 'a', 'd', 'd', 'u', 'h', 'm', 32, 0, - /* 5648 */ 'v', 'a', 'd', 'd', 'u', 'h', 'm', 32, 0, - /* 5657 */ 'v', 'm', 's', 'u', 'm', 'u', 'h', 'm', 32, 0, - /* 5667 */ 'v', 'r', 'f', 'i', 'm', 32, 0, - /* 5674 */ 'x', 's', 'r', 'd', 'p', 'i', 'm', 32, 0, - /* 5683 */ 'x', 'v', 'r', 'd', 'p', 'i', 'm', 32, 0, - /* 5692 */ 'x', 'v', 'r', 's', 'p', 'i', 'm', 32, 0, - /* 5701 */ 'q', 'v', 'f', 'r', 'i', 'm', 32, 0, - /* 5709 */ 'v', 'r', 'l', 'd', 'n', 'm', 32, 0, - /* 5717 */ 'r', 'l', 'w', 'i', 'n', 'm', 32, 0, - /* 5725 */ 'v', 'r', 'l', 'w', 'n', 'm', 32, 0, - /* 5733 */ 'v', 's', 'u', 'b', 'u', 'q', 'm', 32, 0, - /* 5742 */ 'v', 'a', 'd', 'd', 'u', 'q', 'm', 32, 0, - /* 5751 */ 'v', 's', 'u', 'b', 'e', 'u', 'q', 'm', 32, 0, - /* 5761 */ 'v', 'a', 'd', 'd', 'e', 'u', 'q', 'm', 32, 0, - /* 5771 */ 'q', 'v', 'f', 'p', 'e', 'r', 'm', 32, 0, - /* 5780 */ 'v', 'p', 'e', 'r', 'm', 32, 0, - /* 5787 */ 'x', 'x', 'p', 'e', 'r', 'm', 32, 0, - /* 5795 */ 'v', 'p', 'k', 'u', 'd', 'u', 'm', 32, 0, - /* 5804 */ 'v', 'p', 'k', 'u', 'h', 'u', 'm', 32, 0, - /* 5813 */ 'v', 'p', 'k', 'u', 'w', 'u', 'm', 32, 0, - /* 5822 */ 'v', 's', 'u', 'b', 'u', 'w', 'm', 32, 0, - /* 5831 */ 'v', 'a', 'd', 'd', 'u', 'w', 'm', 32, 0, - /* 5840 */ 'v', 'm', 'u', 'l', 'u', 'w', 'm', 32, 0, - /* 5849 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'f', 'a', 'n', 32, 0, - /* 5862 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'f', 'a', 'n', 32, 0, - /* 5875 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 'n', 32, 0, - /* 5886 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 'n', 32, 0, - /* 5897 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'i', 'a', 'n', 32, 0, - /* 5910 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'i', 'a', 'n', 32, 0, - /* 5923 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 'n', 32, 0, - /* 5934 */ 'e', 'v', 'm', 'h', 'e', 'g', 'u', 'm', 'i', 'a', 'n', 32, 0, - /* 5947 */ 'e', 'v', 'm', 'h', 'o', 'g', 'u', 'm', 'i', 'a', 'n', 32, 0, - /* 5960 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 'n', 32, 0, - /* 5971 */ 'q', 'v', 'f', 't', 's', 't', 'n', 'a', 'n', 32, 0, - /* 5982 */ 'q', 'v', 'f', 'c', 'p', 's', 'g', 'n', 32, 0, - /* 5992 */ 'v', 'r', 'f', 'i', 'n', 32, 0, - /* 5999 */ 'q', 'v', 'f', 'r', 'i', 'n', 32, 0, - /* 6007 */ 'm', 'f', 's', 'r', 'i', 'n', 32, 0, - /* 6015 */ 'm', 't', 's', 'r', 'i', 'n', 32, 0, - /* 6023 */ 'x', 's', 'c', 'v', 's', 'p', 'd', 'p', 'n', 32, 0, - /* 6034 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'p', 'n', 32, 0, - /* 6045 */ 'd', 'a', 'r', 'n', 32, 0, - /* 6051 */ 'm', 'f', 'f', 's', 'c', 'r', 'n', 32, 0, - /* 6060 */ 'm', 'f', 'f', 's', 'c', 'd', 'r', 'n', 32, 0, - /* 6070 */ 'e', 'v', 's', 't', 'w', 'h', 'o', 32, 0, - /* 6079 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'l', 'o', 32, 0, - /* 6090 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'h', 'i', 'l', 'o', 32, 0, - /* 6103 */ 'v', 's', 'l', 'o', 32, 0, - /* 6109 */ 'x', 's', 'c', 'v', 'q', 'p', 'd', 'p', 'o', 32, 0, - /* 6120 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'q', 'p', 'o', 32, 0, - /* 6132 */ 'x', 's', 'm', 's', 'u', 'b', 'q', 'p', 'o', 32, 0, - /* 6143 */ 'x', 's', 's', 'u', 'b', 'q', 'p', 'o', 32, 0, - /* 6153 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'q', 'p', 'o', 32, 0, - /* 6165 */ 'x', 's', 'm', 'a', 'd', 'd', 'q', 'p', 'o', 32, 0, - /* 6176 */ 'x', 's', 'a', 'd', 'd', 'q', 'p', 'o', 32, 0, - /* 6186 */ 'x', 's', 'm', 'u', 'l', 'q', 'p', 'o', 32, 0, - /* 6196 */ 'x', 's', 's', 'q', 'r', 't', 'q', 'p', 'o', 32, 0, - /* 6207 */ 'x', 's', 'd', 'i', 'v', 'q', 'p', 'o', 32, 0, - /* 6217 */ 'v', 's', 'r', 'o', 32, 0, - /* 6223 */ 'e', 'v', 's', 't', 'w', 'w', 'o', 32, 0, - /* 6232 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, - /* 6244 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, - /* 6256 */ 'x', 's', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, - /* 6267 */ 'x', 'v', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, - /* 6278 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, - /* 6290 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, - /* 6302 */ 'x', 's', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, - /* 6313 */ 'x', 'v', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, - /* 6324 */ 'x', 's', 's', 'u', 'b', 'd', 'p', 32, 0, - /* 6333 */ 'x', 'v', 's', 'u', 'b', 'd', 'p', 32, 0, - /* 6342 */ 'x', 's', 't', 's', 't', 'd', 'c', 'd', 'p', 32, 0, - /* 6353 */ 'x', 'v', 't', 's', 't', 'd', 'c', 'd', 'p', 32, 0, - /* 6364 */ 'x', 's', 'm', 'i', 'n', 'c', 'd', 'p', 32, 0, - /* 6374 */ 'x', 's', 'm', 'a', 'x', 'c', 'd', 'p', 32, 0, - /* 6384 */ 'x', 's', 'a', 'd', 'd', 'd', 'p', 32, 0, - /* 6393 */ 'x', 'v', 'a', 'd', 'd', 'd', 'p', 32, 0, - /* 6402 */ 'x', 's', 'c', 'v', 's', 'x', 'd', 'd', 'p', 32, 0, - /* 6413 */ 'x', 'v', 'c', 'v', 's', 'x', 'd', 'd', 'p', 32, 0, - /* 6424 */ 'x', 's', 'c', 'v', 'u', 'x', 'd', 'd', 'p', 32, 0, - /* 6435 */ 'x', 'v', 'c', 'v', 'u', 'x', 'd', 'd', 'p', 32, 0, - /* 6446 */ 'x', 's', 'c', 'm', 'p', 'g', 'e', 'd', 'p', 32, 0, - /* 6457 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 'd', 'p', 32, 0, - /* 6468 */ 'x', 's', 'r', 'e', 'd', 'p', 32, 0, - /* 6476 */ 'x', 'v', 'r', 'e', 'd', 'p', 32, 0, - /* 6484 */ 'x', 's', 'r', 's', 'q', 'r', 't', 'e', 'd', 'p', 32, 0, - /* 6496 */ 'x', 'v', 'r', 's', 'q', 'r', 't', 'e', 'd', 'p', 32, 0, - /* 6508 */ 'x', 's', 'n', 'e', 'g', 'd', 'p', 32, 0, - /* 6517 */ 'x', 'v', 'n', 'e', 'g', 'd', 'p', 32, 0, - /* 6526 */ 'x', 's', 'x', 's', 'i', 'g', 'd', 'p', 32, 0, - /* 6536 */ 'x', 'v', 'x', 's', 'i', 'g', 'd', 'p', 32, 0, - /* 6546 */ 'x', 's', 'm', 'i', 'n', 'j', 'd', 'p', 32, 0, - /* 6556 */ 'x', 's', 'm', 'a', 'x', 'j', 'd', 'p', 32, 0, - /* 6566 */ 'x', 's', 'm', 'u', 'l', 'd', 'p', 32, 0, - /* 6575 */ 'x', 'v', 'm', 'u', 'l', 'd', 'p', 32, 0, - /* 6584 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, - /* 6596 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, - /* 6608 */ 'x', 's', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, - /* 6619 */ 'x', 'v', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, - /* 6630 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, - /* 6642 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, - /* 6654 */ 'x', 's', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, - /* 6665 */ 'x', 'v', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, - /* 6676 */ 'x', 's', 'c', 'p', 's', 'g', 'n', 'd', 'p', 32, 0, - /* 6687 */ 'x', 'v', 'c', 'p', 's', 'g', 'n', 'd', 'p', 32, 0, - /* 6698 */ 'x', 's', 'm', 'i', 'n', 'd', 'p', 32, 0, - /* 6707 */ 'x', 'v', 'm', 'i', 'n', 'd', 'p', 32, 0, - /* 6716 */ 'x', 's', 'c', 'm', 'p', 'o', 'd', 'p', 32, 0, - /* 6726 */ 'x', 's', 'c', 'v', 'h', 'p', 'd', 'p', 32, 0, - /* 6736 */ 'x', 's', 'c', 'v', 'q', 'p', 'd', 'p', 32, 0, - /* 6746 */ 'x', 's', 'c', 'v', 's', 'p', 'd', 'p', 32, 0, - /* 6756 */ 'x', 'v', 'c', 'v', 's', 'p', 'd', 'p', 32, 0, - /* 6766 */ 'x', 's', 'i', 'e', 'x', 'p', 'd', 'p', 32, 0, - /* 6776 */ 'x', 'v', 'i', 'e', 'x', 'p', 'd', 'p', 32, 0, - /* 6786 */ 'x', 's', 'c', 'm', 'p', 'e', 'x', 'p', 'd', 'p', 32, 0, - /* 6798 */ 'x', 's', 'x', 'e', 'x', 'p', 'd', 'p', 32, 0, - /* 6808 */ 'x', 'v', 'x', 'e', 'x', 'p', 'd', 'p', 32, 0, - /* 6818 */ 'x', 's', 'c', 'm', 'p', 'e', 'q', 'd', 'p', 32, 0, - /* 6829 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 'd', 'p', 32, 0, - /* 6840 */ 'x', 's', 'n', 'a', 'b', 's', 'd', 'p', 32, 0, - /* 6850 */ 'x', 'v', 'n', 'a', 'b', 's', 'd', 'p', 32, 0, - /* 6860 */ 'x', 's', 'a', 'b', 's', 'd', 'p', 32, 0, - /* 6869 */ 'x', 'v', 'a', 'b', 's', 'd', 'p', 32, 0, - /* 6878 */ 'x', 's', 'c', 'm', 'p', 'g', 't', 'd', 'p', 32, 0, - /* 6889 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 'd', 'p', 32, 0, - /* 6900 */ 'x', 's', 's', 'q', 'r', 't', 'd', 'p', 32, 0, - /* 6910 */ 'x', 's', 't', 's', 'q', 'r', 't', 'd', 'p', 32, 0, - /* 6921 */ 'x', 'v', 't', 's', 'q', 'r', 't', 'd', 'p', 32, 0, - /* 6932 */ 'x', 'v', 's', 'q', 'r', 't', 'd', 'p', 32, 0, - /* 6942 */ 'x', 's', 'c', 'm', 'p', 'u', 'd', 'p', 32, 0, - /* 6952 */ 'x', 's', 'd', 'i', 'v', 'd', 'p', 32, 0, - /* 6961 */ 'x', 's', 't', 'd', 'i', 'v', 'd', 'p', 32, 0, - /* 6971 */ 'x', 'v', 't', 'd', 'i', 'v', 'd', 'p', 32, 0, - /* 6981 */ 'x', 'v', 'd', 'i', 'v', 'd', 'p', 32, 0, - /* 6990 */ 'x', 'v', 'c', 'v', 's', 'x', 'w', 'd', 'p', 32, 0, - /* 7001 */ 'x', 'v', 'c', 'v', 'u', 'x', 'w', 'd', 'p', 32, 0, - /* 7012 */ 'x', 's', 'm', 'a', 'x', 'd', 'p', 32, 0, - /* 7021 */ 'x', 'v', 'm', 'a', 'x', 'd', 'p', 32, 0, - /* 7030 */ 'd', 'c', 'b', 'f', 'e', 'p', 32, 0, - /* 7038 */ 'i', 'c', 'b', 'i', 'e', 'p', 32, 0, - /* 7046 */ 'd', 'c', 'b', 'z', 'l', 'e', 'p', 32, 0, - /* 7055 */ 'd', 'c', 'b', 't', 'e', 'p', 32, 0, - /* 7063 */ 'd', 'c', 'b', 's', 't', 'e', 'p', 32, 0, - /* 7072 */ 'd', 'c', 'b', 't', 's', 't', 'e', 'p', 32, 0, - /* 7082 */ 'd', 'c', 'b', 'z', 'e', 'p', 32, 0, - /* 7090 */ 'v', 'c', 'm', 'p', 'b', 'f', 'p', 32, 0, - /* 7099 */ 'v', 'n', 'm', 's', 'u', 'b', 'f', 'p', 32, 0, - /* 7109 */ 'v', 's', 'u', 'b', 'f', 'p', 32, 0, - /* 7117 */ 'v', 'm', 'a', 'd', 'd', 'f', 'p', 32, 0, - /* 7126 */ 'v', 'a', 'd', 'd', 'f', 'p', 32, 0, - /* 7134 */ 'v', 'l', 'o', 'g', 'e', 'f', 'p', 32, 0, - /* 7143 */ 'v', 'c', 'm', 'p', 'g', 'e', 'f', 'p', 32, 0, - /* 7153 */ 'v', 'r', 'e', 'f', 'p', 32, 0, - /* 7160 */ 'v', 'e', 'x', 'p', 't', 'e', 'f', 'p', 32, 0, - /* 7170 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 'f', 'p', 32, 0, - /* 7181 */ 'v', 'm', 'i', 'n', 'f', 'p', 32, 0, - /* 7189 */ 'v', 'c', 'm', 'p', 'e', 'q', 'f', 'p', 32, 0, - /* 7199 */ 'v', 'c', 'm', 'p', 'g', 't', 'f', 'p', 32, 0, - /* 7209 */ 'v', 'm', 'a', 'x', 'f', 'p', 32, 0, - /* 7217 */ 'x', 's', 'c', 'v', 'd', 'p', 'h', 'p', 32, 0, - /* 7227 */ 'x', 'v', 'c', 'v', 's', 'p', 'h', 'p', 32, 0, - /* 7237 */ 'v', 'r', 'f', 'i', 'p', 32, 0, - /* 7244 */ 'x', 's', 'r', 'd', 'p', 'i', 'p', 32, 0, - /* 7253 */ 'x', 'v', 'r', 'd', 'p', 'i', 'p', 32, 0, - /* 7262 */ 'x', 'v', 'r', 's', 'p', 'i', 'p', 32, 0, - /* 7271 */ 'q', 'v', 'f', 'r', 'i', 'p', 32, 0, - /* 7279 */ 'd', 'c', 'b', 'f', 'l', 'p', 32, 0, - /* 7287 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'q', 'p', 32, 0, - /* 7298 */ 'x', 's', 'm', 's', 'u', 'b', 'q', 'p', 32, 0, - /* 7308 */ 'x', 's', 's', 'u', 'b', 'q', 'p', 32, 0, - /* 7317 */ 'x', 's', 't', 's', 't', 'd', 'c', 'q', 'p', 32, 0, - /* 7328 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'q', 'p', 32, 0, - /* 7339 */ 'x', 's', 'm', 'a', 'd', 'd', 'q', 'p', 32, 0, - /* 7349 */ 'x', 's', 'a', 'd', 'd', 'q', 'p', 32, 0, - /* 7358 */ 'x', 's', 'c', 'v', 's', 'd', 'q', 'p', 32, 0, - /* 7368 */ 'x', 's', 'c', 'v', 'u', 'd', 'q', 'p', 32, 0, - /* 7378 */ 'x', 's', 'n', 'e', 'g', 'q', 'p', 32, 0, - /* 7387 */ 'x', 's', 'x', 's', 'i', 'g', 'q', 'p', 32, 0, - /* 7397 */ 'x', 's', 'm', 'u', 'l', 'q', 'p', 32, 0, - /* 7406 */ 'x', 's', 'c', 'p', 's', 'g', 'n', 'q', 'p', 32, 0, - /* 7417 */ 'x', 's', 'c', 'm', 'p', 'o', 'q', 'p', 32, 0, - /* 7427 */ 'x', 's', 'c', 'v', 'd', 'p', 'q', 'p', 32, 0, - /* 7437 */ 'x', 's', 'i', 'e', 'x', 'p', 'q', 'p', 32, 0, - /* 7447 */ 'x', 's', 'c', 'm', 'p', 'e', 'x', 'p', 'q', 'p', 32, 0, - /* 7459 */ 'x', 's', 'x', 'e', 'x', 'p', 'q', 'p', 32, 0, - /* 7469 */ 'x', 's', 'n', 'a', 'b', 's', 'q', 'p', 32, 0, - /* 7479 */ 'x', 's', 'a', 'b', 's', 'q', 'p', 32, 0, - /* 7488 */ 'x', 's', 's', 'q', 'r', 't', 'q', 'p', 32, 0, - /* 7498 */ 'x', 's', 'c', 'm', 'p', 'u', 'q', 'p', 32, 0, - /* 7508 */ 'x', 's', 'd', 'i', 'v', 'q', 'p', 32, 0, - /* 7517 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, - /* 7529 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, - /* 7541 */ 'x', 's', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, - /* 7552 */ 'x', 'v', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, - /* 7563 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, - /* 7575 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, - /* 7587 */ 'x', 's', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, - /* 7598 */ 'x', 'v', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, - /* 7609 */ 'x', 's', 's', 'u', 'b', 's', 'p', 32, 0, - /* 7618 */ 'x', 'v', 's', 'u', 'b', 's', 'p', 32, 0, - /* 7627 */ 'x', 's', 't', 's', 't', 'd', 'c', 's', 'p', 32, 0, - /* 7638 */ 'x', 'v', 't', 's', 't', 'd', 'c', 's', 'p', 32, 0, - /* 7649 */ 'x', 's', 'a', 'd', 'd', 's', 'p', 32, 0, - /* 7658 */ 'x', 'v', 'a', 'd', 'd', 's', 'p', 32, 0, - /* 7667 */ 'x', 's', 'c', 'v', 's', 'x', 'd', 's', 'p', 32, 0, - /* 7678 */ 'x', 'v', 'c', 'v', 's', 'x', 'd', 's', 'p', 32, 0, - /* 7689 */ 'x', 's', 'c', 'v', 'u', 'x', 'd', 's', 'p', 32, 0, - /* 7700 */ 'x', 'v', 'c', 'v', 'u', 'x', 'd', 's', 'p', 32, 0, - /* 7711 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 's', 'p', 32, 0, - /* 7722 */ 'x', 's', 'r', 'e', 's', 'p', 32, 0, - /* 7730 */ 'x', 'v', 'r', 'e', 's', 'p', 32, 0, - /* 7738 */ 'x', 's', 'r', 's', 'q', 'r', 't', 'e', 's', 'p', 32, 0, - /* 7750 */ 'x', 'v', 'r', 's', 'q', 'r', 't', 'e', 's', 'p', 32, 0, - /* 7762 */ 'x', 'v', 'n', 'e', 'g', 's', 'p', 32, 0, - /* 7771 */ 'x', 'v', 'x', 's', 'i', 'g', 's', 'p', 32, 0, - /* 7781 */ 'x', 's', 'm', 'u', 'l', 's', 'p', 32, 0, - /* 7790 */ 'x', 'v', 'm', 'u', 'l', 's', 'p', 32, 0, - /* 7799 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, - /* 7811 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, - /* 7823 */ 'x', 's', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, - /* 7834 */ 'x', 'v', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, - /* 7845 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, - /* 7857 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, - /* 7869 */ 'x', 's', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, - /* 7880 */ 'x', 'v', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, - /* 7891 */ 'x', 'v', 'c', 'p', 's', 'g', 'n', 's', 'p', 32, 0, - /* 7902 */ 'x', 'v', 'm', 'i', 'n', 's', 'p', 32, 0, - /* 7911 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'p', 32, 0, - /* 7921 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'p', 32, 0, - /* 7931 */ 'x', 'v', 'c', 'v', 'h', 'p', 's', 'p', 32, 0, - /* 7941 */ 'x', 'v', 'i', 'e', 'x', 'p', 's', 'p', 32, 0, - /* 7951 */ 'x', 'v', 'x', 'e', 'x', 'p', 's', 'p', 32, 0, - /* 7961 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 's', 'p', 32, 0, - /* 7972 */ 'q', 'v', 'f', 'r', 's', 'p', 32, 0, - /* 7980 */ 'x', 's', 'r', 's', 'p', 32, 0, - /* 7987 */ 'x', 'v', 'n', 'a', 'b', 's', 's', 'p', 32, 0, - /* 7997 */ 'x', 'v', 'a', 'b', 's', 's', 'p', 32, 0, - /* 8006 */ 'l', 'x', 's', 's', 'p', 32, 0, - /* 8013 */ 's', 't', 'x', 's', 's', 'p', 32, 0, - /* 8021 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 's', 'p', 32, 0, - /* 8032 */ 'x', 's', 's', 'q', 'r', 't', 's', 'p', 32, 0, - /* 8042 */ 'x', 'v', 't', 's', 'q', 'r', 't', 's', 'p', 32, 0, - /* 8053 */ 'x', 'v', 's', 'q', 'r', 't', 's', 'p', 32, 0, - /* 8063 */ 'x', 's', 'd', 'i', 'v', 's', 'p', 32, 0, - /* 8072 */ 'x', 'v', 't', 'd', 'i', 'v', 's', 'p', 32, 0, - /* 8082 */ 'x', 'v', 'd', 'i', 'v', 's', 'p', 32, 0, - /* 8091 */ 'x', 'v', 'c', 'v', 's', 'x', 'w', 's', 'p', 32, 0, - /* 8102 */ 'x', 'v', 'c', 'v', 'u', 'x', 'w', 's', 'p', 32, 0, - /* 8113 */ 'x', 'v', 'm', 'a', 'x', 's', 'p', 32, 0, - /* 8122 */ 'x', 's', 'r', 'q', 'p', 'x', 'p', 32, 0, - /* 8131 */ 'v', 'p', 'r', 't', 'y', 'b', 'q', 32, 0, - /* 8140 */ 'e', 'f', 'd', 'c', 'm', 'p', 'e', 'q', 32, 0, - /* 8150 */ 'q', 'v', 'f', 'c', 'm', 'p', 'e', 'q', 32, 0, - /* 8160 */ 'e', 'f', 's', 'c', 'm', 'p', 'e', 'q', 32, 0, - /* 8170 */ 'e', 'v', 'f', 's', 'c', 'm', 'p', 'e', 'q', 32, 0, - /* 8181 */ 'e', 'v', 'c', 'm', 'p', 'e', 'q', 32, 0, - /* 8190 */ 'e', 'f', 'd', 't', 's', 't', 'e', 'q', 32, 0, - /* 8200 */ 'e', 'f', 's', 't', 's', 't', 'e', 'q', 32, 0, - /* 8210 */ 'e', 'v', 'f', 's', 't', 's', 't', 'e', 'q', 32, 0, - /* 8221 */ 'v', 'b', 'p', 'e', 'r', 'm', 'q', 32, 0, - /* 8230 */ 'x', 'x', 'b', 'r', 'q', 32, 0, - /* 8237 */ 'v', 'm', 'u', 'l', '1', '0', 'u', 'q', 32, 0, - /* 8247 */ 'v', 'm', 'u', 'l', '1', '0', 'c', 'u', 'q', 32, 0, - /* 8258 */ 'v', 's', 'u', 'b', 'c', 'u', 'q', 32, 0, - /* 8267 */ 'v', 'a', 'd', 'd', 'c', 'u', 'q', 32, 0, - /* 8276 */ 'v', 'm', 'u', 'l', '1', '0', 'e', 'c', 'u', 'q', 32, 0, - /* 8288 */ 'v', 's', 'u', 'b', 'e', 'c', 'u', 'q', 32, 0, - /* 8298 */ 'v', 'a', 'd', 'd', 'e', 'c', 'u', 'q', 32, 0, - /* 8308 */ 'v', 'm', 'u', 'l', '1', '0', 'e', 'u', 'q', 32, 0, - /* 8319 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'r', 32, 0, - /* 8332 */ 'm', 'b', 'a', 'r', 32, 0, - /* 8338 */ 'm', 'f', 'd', 'c', 'r', 32, 0, - /* 8345 */ 'r', 'l', 'd', 'c', 'r', 32, 0, - /* 8352 */ 'm', 't', 'd', 'c', 'r', 32, 0, - /* 8359 */ 'm', 'f', 'c', 'r', 32, 0, - /* 8365 */ 'r', 'l', 'd', 'i', 'c', 'r', 32, 0, - /* 8373 */ 'm', 'f', 'v', 's', 'c', 'r', 32, 0, - /* 8381 */ 'm', 't', 'v', 's', 'c', 'r', 32, 0, - /* 8389 */ 'v', 'n', 'c', 'i', 'p', 'h', 'e', 'r', 32, 0, - /* 8399 */ 'v', 'c', 'i', 'p', 'h', 'e', 'r', 32, 0, - /* 8408 */ 'b', 'c', 'l', 'r', 32, 0, - /* 8414 */ 'm', 'f', 'l', 'r', 32, 0, - /* 8420 */ 'm', 't', 'l', 'r', 32, 0, - /* 8426 */ 'q', 'v', 'f', 'm', 'r', 32, 0, - /* 8433 */ 'm', 'f', 'p', 'm', 'r', 32, 0, - /* 8440 */ 'm', 't', 'p', 'm', 'r', 32, 0, - /* 8447 */ 'v', 'p', 'e', 'r', 'm', 'r', 32, 0, - /* 8455 */ 'x', 'x', 'p', 'e', 'r', 'm', 'r', 32, 0, - /* 8464 */ 'x', 'x', 'l', 'o', 'r', 32, 0, - /* 8471 */ 'x', 'x', 'l', 'n', 'o', 'r', 32, 0, - /* 8479 */ 'c', 'r', 'n', 'o', 'r', 32, 0, - /* 8486 */ 'e', 'v', 'n', 'o', 'r', 32, 0, - /* 8493 */ 'c', 'r', 'o', 'r', 32, 0, - /* 8499 */ 'e', 'v', 'o', 'r', 32, 0, - /* 8505 */ 'x', 'x', 'l', 'x', 'o', 'r', 32, 0, - /* 8513 */ 'v', 'p', 'e', 'r', 'm', 'x', 'o', 'r', 32, 0, - /* 8523 */ 'c', 'r', 'x', 'o', 'r', 32, 0, - /* 8530 */ 'e', 'v', 'x', 'o', 'r', 32, 0, - /* 8537 */ 'm', 'f', 's', 'p', 'r', 32, 0, - /* 8544 */ 'm', 't', 's', 'p', 'r', 32, 0, - /* 8551 */ 'm', 'f', 's', 'r', 32, 0, - /* 8557 */ 'm', 'f', 'm', 's', 'r', 32, 0, - /* 8564 */ 'm', 't', 'm', 's', 'r', 32, 0, - /* 8571 */ 'm', 't', 's', 'r', 32, 0, - /* 8577 */ 'l', 'v', 's', 'r', 32, 0, - /* 8583 */ 'b', 'c', 'c', 't', 'r', 32, 0, - /* 8590 */ 'm', 'f', 'c', 't', 'r', 32, 0, - /* 8597 */ 'm', 't', 'c', 't', 'r', 32, 0, - /* 8604 */ 'e', 'f', 'd', 'a', 'b', 's', 32, 0, - /* 8612 */ 'q', 'v', 'f', 'a', 'b', 's', 32, 0, - /* 8620 */ 'e', 'f', 'd', 'n', 'a', 'b', 's', 32, 0, - /* 8629 */ 'q', 'v', 'f', 'n', 'a', 'b', 's', 32, 0, - /* 8638 */ 'e', 'f', 's', 'n', 'a', 'b', 's', 32, 0, - /* 8647 */ 'e', 'v', 'f', 's', 'n', 'a', 'b', 's', 32, 0, - /* 8657 */ 'e', 'f', 's', 'a', 'b', 's', 32, 0, - /* 8665 */ 'e', 'v', 'f', 's', 'a', 'b', 's', 32, 0, - /* 8674 */ 'e', 'v', 'a', 'b', 's', 32, 0, - /* 8681 */ 'v', 's', 'u', 'm', '4', 's', 'b', 's', 32, 0, - /* 8691 */ 'v', 's', 'u', 'b', 's', 'b', 's', 32, 0, - /* 8700 */ 'v', 'a', 'd', 'd', 's', 'b', 's', 32, 0, - /* 8709 */ 'v', 's', 'u', 'm', '4', 'u', 'b', 's', 32, 0, - /* 8719 */ 'v', 's', 'u', 'b', 'u', 'b', 's', 32, 0, - /* 8728 */ 'v', 'a', 'd', 'd', 'u', 'b', 's', 32, 0, - /* 8737 */ 'q', 'v', 'f', 's', 'u', 'b', 's', 32, 0, - /* 8746 */ 'q', 'v', 'f', 'm', 's', 'u', 'b', 's', 32, 0, - /* 8756 */ 'q', 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 32, 0, - /* 8767 */ 'q', 'v', 'f', 'a', 'd', 'd', 's', 32, 0, - /* 8776 */ 'q', 'v', 'f', 'm', 'a', 'd', 'd', 's', 32, 0, - /* 8786 */ 'q', 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 32, 0, - /* 8797 */ 'q', 'v', 'f', 'x', 'x', 'c', 'p', 'n', 'm', 'a', 'd', 'd', 's', 32, 0, - /* 8812 */ 'q', 'v', 'f', 'x', 'x', 'n', 'p', 'm', 'a', 'd', 'd', 's', 32, 0, - /* 8826 */ 'q', 'v', 'f', 'x', 'm', 'a', 'd', 'd', 's', 32, 0, - /* 8837 */ 'q', 'v', 'f', 'x', 'x', 'm', 'a', 'd', 'd', 's', 32, 0, - /* 8849 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 's', 32, 0, - /* 8859 */ 'd', 'c', 'b', 't', 'd', 's', 32, 0, - /* 8867 */ 'd', 'c', 'b', 't', 's', 't', 'd', 's', 32, 0, - /* 8877 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'x', 'd', 's', 32, 0, - /* 8889 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'x', 'd', 's', 32, 0, - /* 8901 */ 'x', 'v', 'c', 'v', 's', 'p', 's', 'x', 'd', 's', 32, 0, - /* 8913 */ 'x', 's', 'c', 'v', 'd', 'p', 'u', 'x', 'd', 's', 32, 0, - /* 8925 */ 'x', 'v', 'c', 'v', 'd', 'p', 'u', 'x', 'd', 's', 32, 0, - /* 8937 */ 'x', 'v', 'c', 'v', 's', 'p', 'u', 'x', 'd', 's', 32, 0, - /* 8949 */ 'q', 'v', 'f', 'r', 'e', 's', 32, 0, - /* 8957 */ 'q', 'v', 'f', 'r', 's', 'q', 'r', 't', 'e', 's', 32, 0, - /* 8969 */ 'e', 'f', 'd', 'c', 'f', 's', 32, 0, - /* 8977 */ 'm', 'f', 'f', 's', 32, 0, - /* 8983 */ 'l', 'f', 's', 32, 0, - /* 8988 */ 'm', 'c', 'r', 'f', 's', 32, 0, - /* 8995 */ 's', 't', 'f', 's', 32, 0, - /* 9001 */ 'v', 's', 'u', 'm', '4', 's', 'h', 's', 32, 0, - /* 9011 */ 'v', 's', 'u', 'b', 's', 'h', 's', 32, 0, - /* 9020 */ 'v', 'm', 'h', 'a', 'd', 'd', 's', 'h', 's', 32, 0, - /* 9031 */ 'v', 'm', 'h', 'r', 'a', 'd', 'd', 's', 'h', 's', 32, 0, - /* 9043 */ 'v', 'a', 'd', 'd', 's', 'h', 's', 32, 0, - /* 9052 */ 'v', 'm', 's', 'u', 'm', 's', 'h', 's', 32, 0, - /* 9062 */ 'v', 's', 'u', 'b', 'u', 'h', 's', 32, 0, - /* 9071 */ 'v', 'a', 'd', 'd', 'u', 'h', 's', 32, 0, - /* 9080 */ 'v', 'm', 's', 'u', 'm', 'u', 'h', 's', 32, 0, - /* 9090 */ 's', 'u', 'b', 'i', 's', 32, 0, - /* 9097 */ 's', 'u', 'b', 'p', 'c', 'i', 's', 32, 0, - /* 9106 */ 'a', 'd', 'd', 'p', 'c', 'i', 's', 32, 0, - /* 9115 */ 'a', 'd', 'd', 'i', 's', 32, 0, - /* 9122 */ 'l', 'i', 's', 32, 0, - /* 9127 */ 'x', 'o', 'r', 'i', 's', 32, 0, - /* 9134 */ 'e', 'v', 's', 'r', 'w', 'i', 's', 32, 0, - /* 9143 */ 'i', 'c', 'b', 't', 'l', 's', 32, 0, - /* 9151 */ 'q', 'v', 'f', 'm', 'u', 'l', 's', 32, 0, - /* 9160 */ 'q', 'v', 'f', 'x', 'm', 'u', 'l', 's', 32, 0, - /* 9170 */ 'e', 'v', 'l', 'w', 'h', 'o', 's', 32, 0, - /* 9179 */ 'v', 'p', 'k', 's', 'd', 's', 's', 32, 0, - /* 9188 */ 'v', 'p', 'k', 's', 'h', 's', 's', 32, 0, - /* 9197 */ 'v', 'p', 'k', 's', 'w', 's', 's', 32, 0, - /* 9206 */ 'e', 'v', 'c', 'm', 'p', 'g', 't', 's', 32, 0, - /* 9216 */ 'e', 'v', 'c', 'm', 'p', 'l', 't', 's', 32, 0, - /* 9226 */ 'f', 's', 'q', 'r', 't', 's', 32, 0, - /* 9234 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 'u', 's', 32, 0, - /* 9245 */ 'v', 'p', 'k', 's', 'd', 'u', 's', 32, 0, - /* 9254 */ 'v', 'p', 'k', 'u', 'd', 'u', 's', 32, 0, - /* 9263 */ 'v', 'p', 'k', 's', 'h', 'u', 's', 32, 0, - /* 9272 */ 'v', 'p', 'k', 'u', 'h', 'u', 's', 32, 0, - /* 9281 */ 'v', 'p', 'k', 's', 'w', 'u', 's', 32, 0, - /* 9290 */ 'v', 'p', 'k', 'u', 'w', 'u', 's', 32, 0, - /* 9299 */ 'f', 'd', 'i', 'v', 's', 32, 0, - /* 9306 */ 'e', 'v', 's', 'r', 'w', 's', 32, 0, - /* 9314 */ 'm', 't', 'v', 's', 'r', 'w', 's', 32, 0, - /* 9323 */ 'v', 's', 'u', 'm', '2', 's', 'w', 's', 32, 0, - /* 9333 */ 'v', 's', 'u', 'b', 's', 'w', 's', 32, 0, - /* 9342 */ 'v', 'a', 'd', 'd', 's', 'w', 's', 32, 0, - /* 9351 */ 'v', 's', 'u', 'm', 's', 'w', 's', 32, 0, - /* 9360 */ 'v', 's', 'u', 'b', 'u', 'w', 's', 32, 0, - /* 9369 */ 'v', 'a', 'd', 'd', 'u', 'w', 's', 32, 0, - /* 9378 */ 'e', 'v', 'd', 'i', 'v', 'w', 's', 32, 0, - /* 9387 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'x', 'w', 's', 32, 0, - /* 9399 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'x', 'w', 's', 32, 0, - /* 9411 */ 'x', 'v', 'c', 'v', 's', 'p', 's', 'x', 'w', 's', 32, 0, - /* 9423 */ 'x', 's', 'c', 'v', 'd', 'p', 'u', 'x', 'w', 's', 32, 0, - /* 9435 */ 'x', 'v', 'c', 'v', 'd', 'p', 'u', 'x', 'w', 's', 32, 0, - /* 9447 */ 'x', 'v', 'c', 'v', 's', 'p', 'u', 'x', 'w', 's', 32, 0, - /* 9459 */ 'v', 'c', 't', 's', 'x', 's', 32, 0, - /* 9467 */ 'v', 'c', 't', 'u', 'x', 's', 32, 0, - /* 9475 */ 'l', 'd', 'a', 't', 32, 0, - /* 9481 */ 's', 't', 'd', 'a', 't', 32, 0, - /* 9488 */ 'e', 'v', 'l', 'h', 'h', 'e', 's', 'p', 'l', 'a', 't', 32, 0, - /* 9501 */ 'e', 'v', 'l', 'w', 'h', 's', 'p', 'l', 'a', 't', 32, 0, - /* 9513 */ 'e', 'v', 'l', 'h', 'h', 'o', 's', 's', 'p', 'l', 'a', 't', 32, 0, - /* 9527 */ 'e', 'v', 'l', 'h', 'h', 'o', 'u', 's', 'p', 'l', 'a', 't', 32, 0, - /* 9541 */ 'e', 'v', 'l', 'w', 'w', 's', 'p', 'l', 'a', 't', 32, 0, - /* 9553 */ 'l', 'w', 'a', 't', 32, 0, - /* 9559 */ 's', 't', 'w', 'a', 't', 32, 0, - /* 9566 */ 'd', 'c', 'b', 't', 32, 0, - /* 9572 */ 'i', 'c', 'b', 't', 32, 0, - /* 9578 */ 'd', 'c', 'b', 't', 'c', 't', 32, 0, - /* 9586 */ 'd', 'c', 'b', 't', 's', 't', 'c', 't', 32, 0, - /* 9596 */ 'e', 'f', 'd', 'c', 'm', 'p', 'g', 't', 32, 0, - /* 9606 */ 'q', 'v', 'f', 'c', 'm', 'p', 'g', 't', 32, 0, - /* 9616 */ 'e', 'f', 's', 'c', 'm', 'p', 'g', 't', 32, 0, - /* 9626 */ 'e', 'v', 'f', 's', 'c', 'm', 'p', 'g', 't', 32, 0, - /* 9637 */ 'e', 'f', 'd', 't', 's', 't', 'g', 't', 32, 0, - /* 9647 */ 'e', 'f', 's', 't', 's', 't', 'g', 't', 32, 0, - /* 9657 */ 'e', 'v', 'f', 's', 't', 's', 't', 'g', 't', 32, 0, - /* 9668 */ 'w', 'a', 'i', 't', 32, 0, - /* 9674 */ 'e', 'f', 'd', 'c', 'm', 'p', 'l', 't', 32, 0, - /* 9684 */ 'q', 'v', 'f', 'c', 'm', 'p', 'l', 't', 32, 0, - /* 9694 */ 'e', 'f', 's', 'c', 'm', 'p', 'l', 't', 32, 0, - /* 9704 */ 'e', 'v', 'f', 's', 'c', 'm', 'p', 'l', 't', 32, 0, - /* 9715 */ 'e', 'f', 'd', 't', 's', 't', 'l', 't', 32, 0, - /* 9725 */ 'e', 'f', 's', 't', 's', 't', 'l', 't', 32, 0, - /* 9735 */ 'e', 'v', 'f', 's', 't', 's', 't', 'l', 't', 32, 0, - /* 9746 */ 'f', 's', 'q', 'r', 't', 32, 0, - /* 9753 */ 'f', 't', 's', 'q', 'r', 't', 32, 0, - /* 9761 */ 'p', 'a', 's', 't', 'e', '_', 'l', 'a', 's', 't', 32, 0, - /* 9773 */ 'v', 'n', 'c', 'i', 'p', 'h', 'e', 'r', 'l', 'a', 's', 't', 32, 0, - /* 9787 */ 'v', 'c', 'i', 'p', 'h', 'e', 'r', 'l', 'a', 's', 't', 32, 0, - /* 9800 */ 'd', 'c', 'b', 's', 't', 32, 0, - /* 9807 */ 'd', 's', 't', 32, 0, - /* 9812 */ 'c', 'o', 'p', 'y', '_', 'f', 'i', 'r', 's', 't', 32, 0, - /* 9824 */ 'd', 'c', 'b', 't', 's', 't', 32, 0, - /* 9832 */ 'd', 's', 't', 's', 't', 32, 0, - /* 9839 */ 'd', 'c', 'b', 't', 't', 32, 0, - /* 9846 */ 'd', 's', 't', 't', 32, 0, - /* 9852 */ 'd', 'c', 'b', 't', 's', 't', 't', 32, 0, - /* 9861 */ 'd', 's', 't', 's', 't', 't', 32, 0, - /* 9869 */ 'l', 'h', 'a', 'u', 32, 0, - /* 9875 */ 's', 't', 'b', 'u', 32, 0, - /* 9881 */ 'l', 'f', 'd', 'u', 32, 0, - /* 9887 */ 's', 't', 'f', 'd', 'u', 32, 0, - /* 9894 */ 'm', 'a', 'd', 'd', 'h', 'd', 'u', 32, 0, - /* 9903 */ 'm', 'u', 'l', 'h', 'd', 'u', 32, 0, - /* 9911 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 'u', 32, 0, - /* 9921 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'u', 32, 0, - /* 9931 */ 'l', 'd', 'u', 32, 0, - /* 9936 */ 's', 't', 'd', 'u', 32, 0, - /* 9942 */ 'd', 'i', 'v', 'd', 'u', 32, 0, - /* 9949 */ 'd', 'i', 'v', 'd', 'e', 'u', 32, 0, - /* 9957 */ 'd', 'i', 'v', 'w', 'e', 'u', 32, 0, - /* 9965 */ 's', 't', 'h', 'u', 32, 0, - /* 9971 */ 'e', 'v', 's', 'r', 'w', 'i', 'u', 32, 0, - /* 9980 */ 'e', 'v', 'l', 'w', 'h', 'o', 'u', 32, 0, - /* 9989 */ 'f', 'c', 'm', 'p', 'u', 32, 0, - /* 9996 */ 'l', 'f', 's', 'u', 32, 0, - /* 10002 */ 's', 't', 'f', 's', 'u', 32, 0, - /* 10009 */ 'e', 'v', 'c', 'm', 'p', 'g', 't', 'u', 32, 0, - /* 10019 */ 'e', 'v', 'c', 'm', 'p', 'l', 't', 'u', 32, 0, - /* 10029 */ 'm', 'u', 'l', 'h', 'w', 'u', 32, 0, - /* 10037 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'u', 32, 0, - /* 10047 */ 'e', 'v', 's', 'r', 'w', 'u', 32, 0, - /* 10055 */ 's', 't', 'w', 'u', 32, 0, - /* 10061 */ 'e', 'v', 'd', 'i', 'v', 'w', 'u', 32, 0, - /* 10070 */ 'l', 'b', 'z', 'u', 32, 0, - /* 10076 */ 'l', 'h', 'z', 'u', 32, 0, - /* 10082 */ 'l', 'w', 'z', 'u', 32, 0, - /* 10088 */ 's', 'l', 'b', 'm', 'f', 'e', 'v', 32, 0, - /* 10097 */ 'e', 'f', 'd', 'd', 'i', 'v', 32, 0, - /* 10105 */ 'f', 'd', 'i', 'v', 32, 0, - /* 10111 */ 'e', 'f', 's', 'd', 'i', 'v', 32, 0, - /* 10119 */ 'e', 'v', 'f', 's', 'd', 'i', 'v', 32, 0, - /* 10128 */ 'f', 't', 'd', 'i', 'v', 32, 0, - /* 10135 */ 'v', 's', 'l', 'v', 32, 0, - /* 10141 */ 'x', 'x', 'l', 'e', 'q', 'v', 32, 0, - /* 10149 */ 'c', 'r', 'e', 'q', 'v', 32, 0, - /* 10156 */ 'e', 'v', 'e', 'q', 'v', 32, 0, - /* 10163 */ 'v', 's', 'r', 'v', 32, 0, - /* 10169 */ 'l', 'x', 'v', 32, 0, - /* 10174 */ 's', 't', 'x', 'v', 32, 0, - /* 10180 */ 'v', 'e', 'x', 't', 's', 'b', '2', 'w', 32, 0, - /* 10190 */ 'v', 'e', 'x', 't', 's', 'h', '2', 'w', 32, 0, - /* 10200 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 'a', 'w', 32, 0, - /* 10213 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 'a', 'w', 32, 0, - /* 10226 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 'a', 'w', 32, 0, - /* 10239 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 'a', 'w', 32, 0, - /* 10252 */ 'e', 'v', 'a', 'd', 'd', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10265 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10278 */ 'e', 'v', 's', 'u', 'b', 'f', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10292 */ 'e', 'v', 'm', 'w', 'l', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10305 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10318 */ 'e', 'v', 'a', 'd', 'd', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10331 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10344 */ 'e', 'v', 's', 'u', 'b', 'f', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10358 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10371 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, - /* 10384 */ 'e', 'v', 'a', 'd', 'd', 's', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10397 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10410 */ 'e', 'v', 's', 'u', 'b', 'f', 's', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10424 */ 'e', 'v', 'm', 'w', 'l', 's', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10437 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10450 */ 'e', 'v', 'a', 'd', 'd', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10463 */ 'e', 'v', 'm', 'h', 'e', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10476 */ 'e', 'v', 's', 'u', 'b', 'f', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10490 */ 'e', 'v', 'm', 'w', 'l', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10503 */ 'e', 'v', 'm', 'h', 'o', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, - /* 10516 */ 'v', 's', 'h', 'a', 's', 'i', 'g', 'm', 'a', 'w', 32, 0, - /* 10528 */ 'v', 's', 'r', 'a', 'w', 32, 0, - /* 10535 */ 'v', 'p', 'r', 't', 'y', 'b', 'w', 32, 0, - /* 10544 */ 'e', 'v', 'a', 'd', 'd', 'w', 32, 0, - /* 10552 */ 'e', 'v', 'l', 'd', 'w', 32, 0, - /* 10559 */ 'e', 'v', 'r', 'n', 'd', 'w', 32, 0, - /* 10567 */ 'e', 'v', 's', 't', 'd', 'w', 32, 0, - /* 10575 */ 'v', 'm', 'r', 'g', 'e', 'w', 32, 0, - /* 10583 */ 'v', 'c', 'm', 'p', 'n', 'e', 'w', 32, 0, - /* 10592 */ 'e', 'v', 's', 'u', 'b', 'f', 'w', 32, 0, - /* 10601 */ 'e', 'v', 's', 'u', 'b', 'i', 'f', 'w', 32, 0, - /* 10611 */ 'v', 'n', 'e', 'g', 'w', 32, 0, - /* 10618 */ 'v', 'm', 'r', 'g', 'h', 'w', 32, 0, - /* 10626 */ 'x', 'x', 'm', 'r', 'g', 'h', 'w', 32, 0, - /* 10635 */ 'm', 'u', 'l', 'h', 'w', 32, 0, - /* 10642 */ 'e', 'v', 'a', 'd', 'd', 'i', 'w', 32, 0, - /* 10651 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 32, 0, - /* 10660 */ 'v', 'm', 'r', 'g', 'l', 'w', 32, 0, - /* 10668 */ 'x', 'x', 'm', 'r', 'g', 'l', 'w', 32, 0, - /* 10677 */ 'm', 'u', 'l', 'l', 'w', 32, 0, - /* 10684 */ 'c', 'm', 'p', 'l', 'w', 32, 0, - /* 10691 */ 'e', 'v', 'r', 'l', 'w', 32, 0, - /* 10698 */ 'e', 'v', 's', 'l', 'w', 32, 0, - /* 10705 */ 'l', 'm', 'w', 32, 0, - /* 10710 */ 's', 't', 'm', 'w', 32, 0, - /* 10716 */ 'v', 'p', 'm', 's', 'u', 'm', 'w', 32, 0, - /* 10725 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 'n', 'w', 32, 0, - /* 10738 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 'n', 'w', 32, 0, - /* 10751 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 'n', 'w', 32, 0, - /* 10764 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 'n', 'w', 32, 0, - /* 10777 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 'n', 'w', 32, 0, - /* 10790 */ 'e', 'v', 'm', 'w', 'l', 's', 'm', 'i', 'a', 'n', 'w', 32, 0, - /* 10803 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 'n', 'w', 32, 0, - /* 10816 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0, - /* 10829 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0, - /* 10842 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0, - /* 10855 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'i', 'a', 'n', 'w', 32, 0, - /* 10868 */ 'e', 'v', 'm', 'w', 'l', 's', 's', 'i', 'a', 'n', 'w', 32, 0, - /* 10881 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'i', 'a', 'n', 'w', 32, 0, - /* 10894 */ 'e', 'v', 'm', 'h', 'e', 'u', 's', 'i', 'a', 'n', 'w', 32, 0, - /* 10907 */ 'e', 'v', 'm', 'w', 'l', 'u', 's', 'i', 'a', 'n', 'w', 32, 0, - /* 10920 */ 'e', 'v', 'm', 'h', 'o', 'u', 's', 'i', 'a', 'n', 'w', 32, 0, - /* 10933 */ 'v', 'm', 'r', 'g', 'o', 'w', 32, 0, - /* 10941 */ 'c', 'm', 'p', 'w', 32, 0, - /* 10947 */ 'x', 'x', 'b', 'r', 'w', 32, 0, - /* 10954 */ 'v', 's', 'r', 'w', 32, 0, - /* 10960 */ 'm', 'o', 'd', 's', 'w', 32, 0, - /* 10967 */ 'v', 'm', 'u', 'l', 'e', 's', 'w', 32, 0, - /* 10976 */ 'v', 'a', 'v', 'g', 's', 'w', 32, 0, - /* 10984 */ 'v', 'u', 'p', 'k', 'h', 's', 'w', 32, 0, - /* 10993 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'w', 32, 0, - /* 11003 */ 'v', 'u', 'p', 'k', 'l', 's', 'w', 32, 0, - /* 11012 */ 'e', 'v', 'c', 'n', 't', 'l', 's', 'w', 32, 0, - /* 11022 */ 'v', 'm', 'i', 'n', 's', 'w', 32, 0, - /* 11030 */ 'v', 'm', 'u', 'l', 'o', 's', 'w', 32, 0, - /* 11039 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'w', 32, 0, - /* 11049 */ 'e', 'x', 't', 's', 'w', 32, 0, - /* 11056 */ 'v', 'm', 'a', 'x', 's', 'w', 32, 0, - /* 11064 */ 'v', 's', 'p', 'l', 't', 'w', 32, 0, - /* 11072 */ 'x', 'x', 's', 'p', 'l', 't', 'w', 32, 0, - /* 11081 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'w', 32, 0, - /* 11091 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'w', 32, 0, - /* 11101 */ 'x', 'x', 'i', 'n', 's', 'e', 'r', 't', 'w', 32, 0, - /* 11112 */ 's', 't', 'w', 32, 0, - /* 11117 */ 'v', 's', 'u', 'b', 'c', 'u', 'w', 32, 0, - /* 11126 */ 'v', 'a', 'd', 'd', 'c', 'u', 'w', 32, 0, - /* 11135 */ 'm', 'o', 'd', 'u', 'w', 32, 0, - /* 11142 */ 'v', 'a', 'b', 's', 'd', 'u', 'w', 32, 0, - /* 11151 */ 'v', 'm', 'u', 'l', 'e', 'u', 'w', 32, 0, - /* 11160 */ 'v', 'a', 'v', 'g', 'u', 'w', 32, 0, - /* 11168 */ 'v', 'm', 'i', 'n', 'u', 'w', 32, 0, - /* 11176 */ 'v', 'm', 'u', 'l', 'o', 'u', 'w', 32, 0, - /* 11185 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'w', 32, 0, - /* 11195 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'w', 32, 0, - /* 11207 */ 'x', 'x', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'w', 32, 0, - /* 11220 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'w', 32, 0, - /* 11230 */ 'v', 'm', 'a', 'x', 'u', 'w', 32, 0, - /* 11238 */ 'd', 'i', 'v', 'w', 32, 0, - /* 11244 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'w', 32, 0, - /* 11254 */ 'v', 'c', 'l', 'z', 'w', 32, 0, - /* 11261 */ 'e', 'v', 'c', 'n', 't', 'l', 'z', 'w', 32, 0, - /* 11271 */ 'v', 'c', 't', 'z', 'w', 32, 0, - /* 11278 */ 'c', 'n', 't', 't', 'z', 'w', 32, 0, - /* 11286 */ 'l', 'x', 'v', 'd', '2', 'x', 32, 0, - /* 11294 */ 's', 't', 'x', 'v', 'd', '2', 'x', 32, 0, - /* 11303 */ 'l', 'x', 'v', 'w', '4', 'x', 32, 0, - /* 11311 */ 's', 't', 'x', 'v', 'w', '4', 'x', 32, 0, - /* 11320 */ 'l', 'x', 'v', 'b', '1', '6', 'x', 32, 0, - /* 11329 */ 's', 't', 'x', 'v', 'b', '1', '6', 'x', 32, 0, - /* 11339 */ 'l', 'x', 'v', 'h', '8', 'x', 32, 0, - /* 11347 */ 's', 't', 'x', 'v', 'h', '8', 'x', 32, 0, - /* 11356 */ 'l', 'h', 'a', 'x', 32, 0, - /* 11362 */ 't', 'l', 'b', 'i', 'v', 'a', 'x', 32, 0, - /* 11371 */ 'q', 'v', 'l', 'f', 'i', 'w', 'a', 'x', 32, 0, - /* 11381 */ 'l', 'x', 's', 'i', 'w', 'a', 'x', 32, 0, - /* 11390 */ 'l', 'w', 'a', 'x', 32, 0, - /* 11396 */ 'l', 'v', 'e', 'b', 'x', 32, 0, - /* 11403 */ 's', 't', 'v', 'e', 'b', 'x', 32, 0, - /* 11411 */ 's', 't', 'x', 's', 'i', 'b', 'x', 32, 0, - /* 11420 */ 's', 't', 'b', 'x', 32, 0, - /* 11426 */ 'q', 'v', 'l', 'f', 'c', 'd', 'x', 32, 0, - /* 11435 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 32, 0, - /* 11445 */ 'e', 'v', 'l', 'd', 'd', 'x', 32, 0, - /* 11453 */ 'e', 'v', 's', 't', 'd', 'd', 'x', 32, 0, - /* 11462 */ 'q', 'v', 'l', 'f', 'd', 'x', 32, 0, - /* 11470 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 32, 0, - /* 11479 */ 'q', 'v', 'l', 'p', 'c', 'l', 'd', 'x', 32, 0, - /* 11489 */ 'q', 'v', 'l', 'p', 'c', 'r', 'd', 'x', 32, 0, - /* 11499 */ 'l', 'x', 's', 'd', 'x', 32, 0, - /* 11506 */ 's', 't', 'x', 's', 'd', 'x', 32, 0, - /* 11514 */ 's', 't', 'd', 'x', 32, 0, - /* 11520 */ 'e', 'v', 'l', 'w', 'h', 'e', 'x', 32, 0, - /* 11529 */ 'e', 'v', 's', 't', 'w', 'h', 'e', 'x', 32, 0, - /* 11539 */ 'e', 'v', 's', 't', 'w', 'w', 'e', 'x', 32, 0, - /* 11549 */ 'e', 'v', 'l', 'd', 'h', 'x', 32, 0, - /* 11557 */ 'e', 'v', 's', 't', 'd', 'h', 'x', 32, 0, - /* 11566 */ 'l', 'v', 'e', 'h', 'x', 32, 0, - /* 11573 */ 's', 't', 'v', 'e', 'h', 'x', 32, 0, - /* 11581 */ 's', 't', 'x', 's', 'i', 'h', 'x', 32, 0, - /* 11590 */ 's', 't', 'h', 'x', 32, 0, - /* 11596 */ 's', 't', 'b', 'c', 'i', 'x', 32, 0, - /* 11604 */ 'l', 'd', 'c', 'i', 'x', 32, 0, - /* 11611 */ 's', 't', 'd', 'c', 'i', 'x', 32, 0, - /* 11619 */ 's', 't', 'h', 'c', 'i', 'x', 32, 0, - /* 11627 */ 's', 't', 'w', 'c', 'i', 'x', 32, 0, - /* 11635 */ 'l', 'b', 'z', 'c', 'i', 'x', 32, 0, - /* 11643 */ 'l', 'h', 'z', 'c', 'i', 'x', 32, 0, - /* 11651 */ 'l', 'w', 'z', 'c', 'i', 'x', 32, 0, - /* 11659 */ 'x', 's', 'r', 'q', 'p', 'i', 'x', 32, 0, - /* 11668 */ 'v', 'e', 'x', 't', 'u', 'b', 'l', 'x', 32, 0, - /* 11678 */ 'v', 'e', 'x', 't', 'u', 'h', 'l', 'x', 32, 0, - /* 11688 */ 'v', 'e', 'x', 't', 'u', 'w', 'l', 'x', 32, 0, - /* 11698 */ 'l', 'd', 'm', 'x', 32, 0, - /* 11704 */ 'v', 's', 'b', 'o', 'x', 32, 0, - /* 11711 */ 'e', 'v', 's', 't', 'w', 'h', 'o', 'x', 32, 0, - /* 11721 */ 'e', 'v', 's', 't', 'w', 'w', 'o', 'x', 32, 0, - /* 11731 */ 'l', 'b', 'e', 'p', 'x', 32, 0, - /* 11738 */ 's', 't', 'b', 'e', 'p', 'x', 32, 0, - /* 11746 */ 'l', 'f', 'd', 'e', 'p', 'x', 32, 0, - /* 11754 */ 's', 't', 'f', 'd', 'e', 'p', 'x', 32, 0, - /* 11763 */ 'l', 'h', 'e', 'p', 'x', 32, 0, - /* 11770 */ 's', 't', 'h', 'e', 'p', 'x', 32, 0, - /* 11778 */ 'l', 'w', 'e', 'p', 'x', 32, 0, - /* 11785 */ 's', 't', 'w', 'e', 'p', 'x', 32, 0, - /* 11793 */ 'v', 'u', 'p', 'k', 'h', 'p', 'x', 32, 0, - /* 11802 */ 'v', 'p', 'k', 'p', 'x', 32, 0, - /* 11809 */ 'v', 'u', 'p', 'k', 'l', 'p', 'x', 32, 0, - /* 11818 */ 'l', 'x', 's', 's', 'p', 'x', 32, 0, - /* 11826 */ 's', 't', 'x', 's', 's', 'p', 'x', 32, 0, - /* 11835 */ 'l', 'b', 'a', 'r', 'x', 32, 0, - /* 11842 */ 'l', 'd', 'a', 'r', 'x', 32, 0, - /* 11849 */ 'l', 'h', 'a', 'r', 'x', 32, 0, - /* 11856 */ 'l', 'w', 'a', 'r', 'x', 32, 0, - /* 11863 */ 'l', 'd', 'b', 'r', 'x', 32, 0, - /* 11870 */ 's', 't', 'd', 'b', 'r', 'x', 32, 0, - /* 11878 */ 'l', 'h', 'b', 'r', 'x', 32, 0, - /* 11885 */ 's', 't', 'h', 'b', 'r', 'x', 32, 0, - /* 11893 */ 'v', 'e', 'x', 't', 'u', 'b', 'r', 'x', 32, 0, - /* 11903 */ 'l', 'w', 'b', 'r', 'x', 32, 0, - /* 11910 */ 's', 't', 'w', 'b', 'r', 'x', 32, 0, - /* 11918 */ 'v', 'e', 'x', 't', 'u', 'h', 'r', 'x', 32, 0, - /* 11928 */ 'v', 'e', 'x', 't', 'u', 'w', 'r', 'x', 32, 0, - /* 11938 */ 'm', 'c', 'r', 'x', 'r', 'x', 32, 0, - /* 11946 */ 't', 'l', 'b', 's', 'x', 32, 0, - /* 11953 */ 'q', 'v', 'l', 'f', 'c', 's', 'x', 32, 0, - /* 11962 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 32, 0, - /* 11972 */ 'l', 'x', 'v', 'd', 's', 'x', 32, 0, - /* 11980 */ 'v', 'c', 'f', 's', 'x', 32, 0, - /* 11987 */ 'q', 'v', 'l', 'f', 's', 'x', 32, 0, - /* 11995 */ 'q', 'v', 's', 't', 'f', 's', 'x', 32, 0, - /* 12004 */ 'q', 'v', 'l', 'p', 'c', 'l', 's', 'x', 32, 0, - /* 12014 */ 'e', 'v', 'l', 'w', 'h', 'o', 's', 'x', 32, 0, - /* 12024 */ 'q', 'v', 'l', 'p', 'c', 'r', 's', 'x', 32, 0, - /* 12034 */ 'l', 'x', 'v', 'w', 's', 'x', 32, 0, - /* 12042 */ 'e', 'v', 'l', 'h', 'h', 'e', 's', 'p', 'l', 'a', 't', 'x', 32, 0, - /* 12056 */ 'e', 'v', 'l', 'w', 'h', 's', 'p', 'l', 'a', 't', 'x', 32, 0, - /* 12069 */ 'e', 'v', 'l', 'h', 'h', 'o', 's', 's', 'p', 'l', 'a', 't', 'x', 32, 0, - /* 12084 */ 'e', 'v', 'l', 'h', 'h', 'o', 'u', 's', 'p', 'l', 'a', 't', 'x', 32, 0, - /* 12099 */ 'e', 'v', 'l', 'w', 'w', 's', 'p', 'l', 'a', 't', 'x', 32, 0, - /* 12112 */ 'l', 'h', 'a', 'u', 'x', 32, 0, - /* 12119 */ 'l', 'w', 'a', 'u', 'x', 32, 0, - /* 12126 */ 's', 't', 'b', 'u', 'x', 32, 0, - /* 12133 */ 'q', 'v', 'l', 'f', 'c', 'd', 'u', 'x', 32, 0, - /* 12143 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 32, 0, - /* 12154 */ 'q', 'v', 'l', 'f', 'd', 'u', 'x', 32, 0, - /* 12163 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 32, 0, - /* 12173 */ 'l', 'd', 'u', 'x', 32, 0, - /* 12179 */ 's', 't', 'd', 'u', 'x', 32, 0, - /* 12186 */ 'v', 'c', 'f', 'u', 'x', 32, 0, - /* 12193 */ 's', 't', 'h', 'u', 'x', 32, 0, - /* 12200 */ 'e', 'v', 'l', 'w', 'h', 'o', 'u', 'x', 32, 0, - /* 12210 */ 'q', 'v', 'l', 'f', 'c', 's', 'u', 'x', 32, 0, - /* 12220 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 32, 0, - /* 12231 */ 'q', 'v', 'l', 'f', 's', 'u', 'x', 32, 0, - /* 12240 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 32, 0, - /* 12250 */ 's', 't', 'w', 'u', 'x', 32, 0, - /* 12257 */ 'l', 'b', 'z', 'u', 'x', 32, 0, - /* 12264 */ 'l', 'h', 'z', 'u', 'x', 32, 0, - /* 12271 */ 'l', 'w', 'z', 'u', 'x', 32, 0, - /* 12278 */ 'l', 'v', 'x', 32, 0, - /* 12283 */ 's', 't', 'v', 'x', 32, 0, - /* 12289 */ 'l', 'x', 'v', 'x', 32, 0, - /* 12295 */ 's', 't', 'x', 'v', 'x', 32, 0, - /* 12302 */ 'e', 'v', 'l', 'd', 'w', 'x', 32, 0, - /* 12310 */ 'e', 'v', 's', 't', 'd', 'w', 'x', 32, 0, - /* 12319 */ 'l', 'v', 'e', 'w', 'x', 32, 0, - /* 12326 */ 's', 't', 'v', 'e', 'w', 'x', 32, 0, - /* 12334 */ 'q', 'v', 's', 't', 'f', 'i', 'w', 'x', 32, 0, - /* 12344 */ 's', 't', 'x', 's', 'i', 'w', 'x', 32, 0, - /* 12353 */ 's', 't', 'w', 'x', 32, 0, - /* 12359 */ 'l', 'x', 's', 'i', 'b', 'z', 'x', 32, 0, - /* 12368 */ 'l', 'b', 'z', 'x', 32, 0, - /* 12374 */ 'l', 'x', 's', 'i', 'h', 'z', 'x', 32, 0, - /* 12383 */ 'l', 'h', 'z', 'x', 32, 0, - /* 12389 */ 'q', 'v', 'l', 'f', 'i', 'w', 'z', 'x', 32, 0, - /* 12399 */ 'l', 'x', 's', 'i', 'w', 'z', 'x', 32, 0, - /* 12408 */ 'l', 'w', 'z', 'x', 32, 0, - /* 12414 */ 'c', 'o', 'p', 'y', 32, 0, - /* 12420 */ 'd', 'c', 'b', 'z', 32, 0, - /* 12426 */ 'l', 'b', 'z', 32, 0, - /* 12431 */ 'b', 'd', 'z', 32, 0, - /* 12436 */ 'e', 'f', 'd', 'c', 't', 's', 'i', 'd', 'z', 32, 0, - /* 12447 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'z', 32, 0, - /* 12457 */ 'e', 'f', 'd', 'c', 't', 'u', 'i', 'd', 'z', 32, 0, - /* 12468 */ 'x', 's', 'c', 'v', 'q', 'p', 's', 'd', 'z', 32, 0, - /* 12479 */ 'x', 's', 'c', 'v', 'q', 'p', 'u', 'd', 'z', 32, 0, - /* 12490 */ 'l', 'h', 'z', 32, 0, - /* 12495 */ 'v', 'r', 'f', 'i', 'z', 32, 0, - /* 12502 */ 'x', 's', 'r', 'd', 'p', 'i', 'z', 32, 0, - /* 12511 */ 'x', 'v', 'r', 'd', 'p', 'i', 'z', 32, 0, - /* 12520 */ 'x', 'v', 'r', 's', 'p', 'i', 'z', 32, 0, - /* 12529 */ 'q', 'v', 'f', 'r', 'i', 'z', 32, 0, - /* 12537 */ 'e', 'f', 'd', 'c', 't', 's', 'i', 'z', 32, 0, - /* 12547 */ 'e', 'f', 's', 'c', 't', 's', 'i', 'z', 32, 0, - /* 12557 */ 'e', 'v', 'f', 's', 'c', 't', 's', 'i', 'z', 32, 0, - /* 12568 */ 'e', 'f', 'd', 'c', 't', 'u', 'i', 'z', 32, 0, - /* 12578 */ 'e', 'f', 's', 'c', 't', 'u', 'i', 'z', 32, 0, - /* 12588 */ 'b', 'd', 'n', 'z', 32, 0, - /* 12594 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'u', 'z', 32, 0, - /* 12605 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'u', 'z', 32, 0, - /* 12616 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'z', 32, 0, - /* 12626 */ 'l', 'w', 'z', 32, 0, - /* 12631 */ 'm', 'f', 'v', 's', 'r', 'w', 'z', 32, 0, - /* 12640 */ 'm', 't', 'v', 's', 'r', 'w', 'z', 32, 0, - /* 12649 */ 'x', 's', 'c', 'v', 'q', 'p', 's', 'w', 'z', 32, 0, - /* 12660 */ 'x', 's', 'c', 'v', 'q', 'p', 'u', 'w', 'z', 32, 0, - /* 12671 */ 'b', 'd', 'z', 'l', 'r', 'l', '+', 0, - /* 12679 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', '+', 0, - /* 12688 */ 'b', 'd', 'z', 'l', 'r', '+', 0, - /* 12695 */ 'b', 'd', 'n', 'z', 'l', 'r', '+', 0, - /* 12703 */ 'e', 'v', 's', 'e', 'l', 32, 'c', 'r', 'D', ',', 0, - /* 12714 */ 'b', 'd', 'z', 'l', 'r', 'l', '-', 0, - /* 12722 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', '-', 0, - /* 12731 */ 'b', 'd', 'z', 'l', 'r', '-', 0, - /* 12738 */ 'b', 'd', 'n', 'z', 'l', 'r', '-', 0, - /* 12746 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, - /* 12777 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 12801 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 12826 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, - /* 12849 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, - /* 12872 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, - /* 12894 */ 't', 'r', 'e', 'c', 'h', 'k', 'p', 't', '.', 0, - /* 12904 */ 'o', 'r', 'i', 32, '1', ',', 32, '1', ',', 32, '0', 0, - /* 12916 */ 'o', 'r', 'i', 32, '2', ',', 32, '2', ',', 32, '0', 0, - /* 12928 */ '#', 'A', 'D', 'D', 'I', 'S', 'd', 't', 'p', 'r', 'e', 'l', 'H', 'A', '3', '2', 0, - /* 12945 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0, - /* 12966 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0, - /* 12987 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', 0, - /* 13009 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0, - /* 13030 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '3', '2', 0, - /* 13052 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '3', '2', 0, - /* 13073 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, - /* 13090 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0, - /* 13111 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', 0, - /* 13131 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '3', '2', 0, - /* 13153 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '3', '2', 0, - /* 13174 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', '3', '2', 0, - /* 13188 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', '3', '2', 0, - /* 13202 */ '#', 'L', 'D', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'L', '3', '2', 0, - /* 13217 */ '#', 'A', 'D', 'D', 'I', 'd', 't', 'p', 'r', 'e', 'l', 'L', '3', '2', 0, - /* 13232 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'L', 'O', 'N', 'G', 'J', 'M', 'P', '3', '2', 0, - /* 13251 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'S', 'E', 'T', 'J', 'M', 'P', '3', '2', 0, - /* 13269 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 'A', 'D', 'D', 'R', '3', '2', 0, - /* 13287 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 'A', 'D', 'D', 'R', '3', '2', 0, - /* 13305 */ 'G', 'E', 'T', 't', 'l', 's', 'l', 'd', 'A', 'D', 'D', 'R', '3', '2', 0, - /* 13320 */ 'G', 'E', 'T', 't', 'l', 's', 'A', 'D', 'D', 'R', '3', '2', 0, - /* 13333 */ '#', 'D', 'F', 'L', 'O', 'A', 'D', 'f', '3', '2', 0, - /* 13344 */ '#', 'X', 'F', 'L', 'O', 'A', 'D', 'f', '3', '2', 0, - /* 13355 */ '#', 'D', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '3', '2', 0, - /* 13367 */ '#', 'X', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '3', '2', 0, - /* 13379 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0, - /* 13400 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0, - /* 13421 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', 0, - /* 13443 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '6', '4', 0, - /* 13465 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '6', '4', 0, - /* 13486 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, - /* 13503 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, - /* 13524 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0, - /* 13545 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', 0, - /* 13565 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '6', '4', 0, - /* 13587 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '6', '4', 0, - /* 13608 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'L', 'O', 'N', 'G', 'J', 'M', 'P', '6', '4', 0, - /* 13627 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'S', 'E', 'T', 'J', 'M', 'P', '6', '4', 0, - /* 13645 */ '#', 'D', 'F', 'L', 'O', 'A', 'D', 'f', '6', '4', 0, - /* 13656 */ '#', 'X', 'F', 'L', 'O', 'A', 'D', 'f', '6', '4', 0, - /* 13667 */ '#', 'D', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '6', '4', 0, - /* 13679 */ '#', 'X', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '6', '4', 0, - /* 13691 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'i', '6', '4', 0, - /* 13712 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'S', 'P', 'E', '4', 0, - /* 13728 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'S', 'P', 'E', '4', 0, - /* 13741 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '4', 0, - /* 13755 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '4', 0, - /* 13766 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', '4', 0, - /* 13780 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '4', 0, - /* 13791 */ 'c', 'r', 'x', 'o', 'r', 32, '6', ',', 32, '6', ',', 32, '6', 0, - /* 13805 */ 'c', 'r', 'e', 'q', 'v', 32, '6', ',', 32, '6', ',', 32, '6', 0, - /* 13819 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '1', '6', 0, - /* 13834 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '1', '6', 0, - /* 13846 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', 0, - /* 13867 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', 0, - /* 13888 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', 0, - /* 13910 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', 0, - /* 13931 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '1', '6', 0, - /* 13953 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '1', '6', 0, - /* 13974 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0, - /* 13991 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', 0, - /* 14012 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', 0, - /* 14032 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '1', '6', 0, - /* 14054 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '1', '6', 0, - /* 14075 */ '#', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', '8', 0, - /* 14086 */ '#', 'C', 'F', 'E', 'N', 'C', 'E', '8', 0, - /* 14095 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '8', 0, - /* 14109 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '8', 0, - /* 14120 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', 0, - /* 14140 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', '8', 0, - /* 14154 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', 0, - /* 14174 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', 0, - /* 14195 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', 0, - /* 14215 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '8', 0, - /* 14236 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '8', 0, - /* 14256 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0, - /* 14276 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', 0, - /* 14295 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', 0, - /* 14314 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '8', 0, - /* 14325 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '8', 0, - /* 14346 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '8', 0, - /* 14366 */ '#', 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', '8', 0, - /* 14379 */ '#', 'D', 'Y', 'N', 'A', 'R', 'E', 'A', 'O', 'F', 'F', 'S', 'E', 'T', '8', 0, - /* 14395 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', '8', 0, - /* 14412 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', '8', 0, - /* 14429 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'i', '8', 0, - /* 14445 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'o', 'c', 'H', 'A', 0, - /* 14457 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'g', 'd', 'H', 'A', 0, - /* 14471 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'l', 'd', 'H', 'A', 0, - /* 14485 */ '#', 'A', 'D', 'D', 'I', 'S', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'H', 'A', 0, - /* 14502 */ '#', 'A', 'D', 'D', 'I', 'S', 'd', 't', 'p', 'r', 'e', 'l', 'H', 'A', 0, - /* 14517 */ '#', 'R', 'e', 'a', 'd', 'T', 'B', 0, - /* 14525 */ '#', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0, - /* 14535 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'B', 'R', 'C', 0, - /* 14551 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'B', 'R', 'C', 0, - /* 14564 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'R', 'C', 0, - /* 14580 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'F', 'R', 'C', 0, - /* 14593 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'F', 'R', 'C', 0, - /* 14610 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'F', 'R', 'C', 0, - /* 14624 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'R', 'R', 'C', 0, - /* 14640 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'R', 'R', 'C', 0, - /* 14653 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'S', 'R', 'C', 0, - /* 14669 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'S', 'R', 'C', 0, - /* 14682 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'S', 'R', 'C', 0, - /* 14699 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'S', 'R', 'C', 0, - /* 14713 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'R', 'C', 0, - /* 14729 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'R', 'C', 0, - /* 14742 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'L', 'D', 0, - /* 14757 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 14770 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 14777 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'S', 'P', 'E', 0, - /* 14792 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'S', 'P', 'E', 0, - /* 14804 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 14814 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'V', 'R', 'S', 'A', 'V', 'E', 0, - /* 14830 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'V', 'R', 'S', 'A', 'V', 'E', 0, - /* 14844 */ '#', 'L', 'D', 't', 'o', 'c', 'J', 'T', 'I', 0, - /* 14854 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, - /* 14864 */ '#', 'L', 'D', 't', 'o', 'c', 'L', 0, - /* 14872 */ '#', 'A', 'D', 'D', 'I', 't', 'o', 'c', 'L', 0, - /* 14882 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 0, - /* 14894 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 0, - /* 14906 */ '#', 'L', 'D', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'L', 0, - /* 14919 */ '#', 'A', 'D', 'D', 'I', 'd', 't', 'p', 'r', 'e', 'l', 'L', 0, - /* 14932 */ '#', 'U', 'p', 'd', 'a', 't', 'e', 'G', 'B', 'R', 0, - /* 14943 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'C', 'R', 0, - /* 14955 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 0, - /* 14965 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 'A', 'D', 'D', 'R', 0, - /* 14981 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 'A', 'D', 'D', 'R', 0, - /* 14997 */ '#', 'G', 'E', 'T', 't', 'l', 's', 'l', 'd', 'A', 'D', 'D', 'R', 0, - /* 15011 */ '#', 'G', 'E', 'T', 't', 'l', 's', 'A', 'D', 'D', 'R', 0, - /* 15023 */ '#', 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', 0, - /* 15035 */ '#', 'M', 'o', 'v', 'e', 'G', 'O', 'T', 't', 'o', 'L', 'R', 0, - /* 15048 */ '#', 'T', 'C', 'H', 'E', 'C', 'K', '_', 'R', 'E', 'T', 0, - /* 15060 */ '#', 'D', 'Y', 'N', 'A', 'R', 'E', 'A', 'O', 'F', 'F', 'S', 'E', 'T', 0, - /* 15075 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'C', 'R', 'B', 'I', 'T', 0, - /* 15090 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 'B', 'I', 'T', 0, - /* 15103 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', 0, - /* 15119 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', 0, - /* 15135 */ '#', 'P', 'P', 'C', '3', '2', 'G', 'O', 'T', 0, - /* 15145 */ '#', 'P', 'P', 'C', '3', '2', 'P', 'I', 'C', 'G', 'O', 'T', 0, - /* 15158 */ '#', 'L', 'D', 't', 'o', 'c', 'C', 'P', 'T', 0, - /* 15168 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 15183 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'S', 'T', 0, - /* 15198 */ '#', 'L', 'I', 'W', 'A', 'X', 0, - /* 15205 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'L', 'D', 'X', 0, - /* 15221 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'S', 'T', 'X', 0, - /* 15237 */ '#', 'S', 'T', 'I', 'W', 'X', 0, - /* 15244 */ '#', 'L', 'I', 'W', 'Z', 'X', 0, - /* 15251 */ 'b', 'c', 'a', 0, - /* 15255 */ 's', 'l', 'b', 'i', 'a', 0, - /* 15261 */ 't', 'l', 'b', 'i', 'a', 0, - /* 15267 */ 'b', 'c', 'l', 'a', 0, - /* 15272 */ 'c', 'l', 'r', 'b', 'h', 'r', 'b', 0, - /* 15280 */ 'b', 'c', 0, - /* 15283 */ 's', 'l', 'b', 's', 'y', 'n', 'c', 0, - /* 15291 */ 't', 'l', 'b', 's', 'y', 'n', 'c', 0, - /* 15299 */ 'm', 's', 'g', 's', 'y', 'n', 'c', 0, - /* 15307 */ 'i', 's', 'y', 'n', 'c', 0, - /* 15313 */ 'm', 's', 'y', 'n', 'c', 0, - /* 15319 */ '#', 'L', 'D', 't', 'o', 'c', 0, - /* 15326 */ '#', 'L', 'W', 'Z', 't', 'o', 'c', 0, - /* 15334 */ 'h', 'r', 'f', 'i', 'd', 0, - /* 15340 */ 't', 'l', 'b', 'r', 'e', 0, - /* 15346 */ 't', 'l', 'b', 'w', 'e', 0, - /* 15352 */ 'r', 'f', 'c', 'i', 0, - /* 15357 */ 'r', 'f', 'm', 'c', 'i', 0, - /* 15363 */ 'r', 'f', 'd', 'i', 0, - /* 15368 */ 'r', 'f', 'i', 0, - /* 15372 */ 'b', 'c', 'l', 0, - /* 15376 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, - /* 15390 */ 'd', 's', 's', 'a', 'l', 'l', 0, - /* 15397 */ 'b', 'l', 'r', 'l', 0, - /* 15402 */ 'b', 'd', 'z', 'l', 'r', 'l', 0, - /* 15409 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', 0, - /* 15417 */ 'b', 'c', 't', 'r', 'l', 0, - /* 15423 */ 'a', 't', 't', 'n', 0, - /* 15428 */ 'e', 'i', 'e', 'i', 'o', 0, - /* 15434 */ 'n', 'a', 'p', 0, - /* 15438 */ 't', 'r', 'a', 'p', 0, - /* 15443 */ 'n', 'o', 'p', 0, - /* 15447 */ 's', 't', 'o', 'p', 0, - /* 15452 */ 'b', 'l', 'r', 0, - /* 15456 */ 'b', 'd', 'z', 'l', 'r', 0, - /* 15462 */ 'b', 'd', 'n', 'z', 'l', 'r', 0, - /* 15469 */ 'b', 'c', 't', 'r', 0, - /* 15474 */ 'c', 'p', '_', 'a', 'b', 'o', 'r', 't', 0, + /* 0 */ '#', + 'E', + 'H', + '_', + 'S', + 'j', + 'L', + 'j', + '_', + 'S', + 'e', + 't', + 'u', + 'p', + 9, + 0, + /* 16 */ 'b', + 'd', + 'z', + 'l', + 'a', + '+', + 32, + 0, + /* 24 */ 'b', + 'd', + 'n', + 'z', + 'l', + 'a', + '+', + 32, + 0, + /* 33 */ 'b', + 'd', + 'z', + 'a', + '+', + 32, + 0, + /* 40 */ 'b', + 'd', + 'n', + 'z', + 'a', + '+', + 32, + 0, + /* 48 */ 'b', + 'd', + 'z', + 'l', + '+', + 32, + 0, + /* 55 */ 'b', + 'd', + 'n', + 'z', + 'l', + '+', + 32, + 0, + /* 63 */ 'b', + 'd', + 'z', + '+', + 32, + 0, + /* 69 */ 'b', + 'd', + 'n', + 'z', + '+', + 32, + 0, + /* 76 */ 'b', + 'c', + 'l', + 32, + '2', + '0', + ',', + 32, + '3', + '1', + ',', + 32, + 0, + /* 89 */ 'b', + 'c', + 't', + 'r', + 'l', + 10, + 9, + 'l', + 'd', + 32, + '2', + ',', + 32, + 0, + /* 103 */ 'b', + 'c', + 32, + '1', + '2', + ',', + 32, + 0, + /* 111 */ 'b', + 'c', + 'l', + 32, + '1', + '2', + ',', + 32, + 0, + /* 120 */ 'b', + 'c', + 'l', + 'r', + 'l', + 32, + '1', + '2', + ',', + 32, + 0, + /* 131 */ 'b', + 'c', + 'c', + 't', + 'r', + 'l', + 32, + '1', + '2', + ',', + 32, + 0, + /* 143 */ 'b', + 'c', + 'l', + 'r', + 32, + '1', + '2', + ',', + 32, + 0, + /* 153 */ 'b', + 'c', + 'c', + 't', + 'r', + 32, + '1', + '2', + ',', + 32, + 0, + /* 164 */ 'b', + 'c', + 32, + '4', + ',', + 32, + 0, + /* 171 */ 'b', + 'c', + 'l', + 32, + '4', + ',', + 32, + 0, + /* 179 */ 'b', + 'c', + 'l', + 'r', + 'l', + 32, + '4', + ',', + 32, + 0, + /* 189 */ 'b', + 'c', + 'c', + 't', + 'r', + 'l', + 32, + '4', + ',', + 32, + 0, + /* 200 */ 'b', + 'c', + 'l', + 'r', + 32, + '4', + ',', + 32, + 0, + /* 209 */ 'b', + 'c', + 'c', + 't', + 'r', + 32, + '4', + ',', + 32, + 0, + /* 219 */ 'm', + 't', + 's', + 'p', + 'r', + 32, + '2', + '5', + '6', + ',', + 32, + 0, + /* 231 */ 'b', + 'd', + 'z', + 'l', + 'a', + '-', + 32, + 0, + /* 239 */ 'b', + 'd', + 'n', + 'z', + 'l', + 'a', + '-', + 32, + 0, + /* 248 */ 'b', + 'd', + 'z', + 'a', + '-', + 32, + 0, + /* 255 */ 'b', + 'd', + 'n', + 'z', + 'a', + '-', + 32, + 0, + /* 263 */ 'b', + 'd', + 'z', + 'l', + '-', + 32, + 0, + /* 270 */ 'b', + 'd', + 'n', + 'z', + 'l', + '-', + 32, + 0, + /* 278 */ 'b', + 'd', + 'z', + '-', + 32, + 0, + /* 284 */ 'b', + 'd', + 'n', + 'z', + '-', + 32, + 0, + /* 291 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'b', + '.', + 32, + 0, + /* 301 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'b', + '.', + 32, + 0, + /* 312 */ 'e', + 'x', + 't', + 's', + 'b', + '.', + 32, + 0, + /* 320 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'u', + 'b', + '.', + 32, + 0, + /* 331 */ 'f', + 's', + 'u', + 'b', + '.', + 32, + 0, + /* 338 */ 'f', + 'm', + 's', + 'u', + 'b', + '.', + 32, + 0, + /* 346 */ 'f', + 'n', + 'm', + 's', + 'u', + 'b', + '.', + 32, + 0, + /* 355 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'u', + 'b', + '.', + 32, + 0, + /* 366 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'z', + 'b', + '.', + 32, + 0, + /* 377 */ 'a', + 'd', + 'd', + 'c', + '.', + 32, + 0, + /* 384 */ 'a', + 'n', + 'd', + 'c', + '.', + 32, + 0, + /* 391 */ 't', + 'a', + 'b', + 'o', + 'r', + 't', + 'd', + 'c', + '.', + 32, + 0, + /* 402 */ 's', + 'u', + 'b', + 'f', + 'c', + '.', + 32, + 0, + /* 410 */ 's', + 'u', + 'b', + 'i', + 'c', + '.', + 32, + 0, + /* 418 */ 'a', + 'd', + 'd', + 'i', + 'c', + '.', + 32, + 0, + /* 426 */ 'r', + 'l', + 'd', + 'i', + 'c', + '.', + 32, + 0, + /* 434 */ 'b', + 'c', + 'd', + 't', + 'r', + 'u', + 'n', + 'c', + '.', + 32, + 0, + /* 445 */ 'b', + 'c', + 'd', + 'u', + 't', + 'r', + 'u', + 'n', + 'c', + '.', + 32, + 0, + /* 457 */ 'o', + 'r', + 'c', + '.', + 32, + 0, + /* 463 */ 't', + 'a', + 'b', + 'o', + 'r', + 't', + 'w', + 'c', + '.', + 32, + 0, + /* 474 */ 's', + 'r', + 'a', + 'd', + '.', + 32, + 0, + /* 481 */ 'f', + 'a', + 'd', + 'd', + '.', + 32, + 0, + /* 488 */ 'f', + 'm', + 'a', + 'd', + 'd', + '.', + 32, + 0, + /* 496 */ 'f', + 'n', + 'm', + 'a', + 'd', + 'd', + '.', + 32, + 0, + /* 505 */ 'm', + 'u', + 'l', + 'h', + 'd', + '.', + 32, + 0, + /* 513 */ 'f', + 'c', + 'f', + 'i', + 'd', + '.', + 32, + 0, + /* 521 */ 'f', + 'c', + 't', + 'i', + 'd', + '.', + 32, + 0, + /* 529 */ 'm', + 'u', + 'l', + 'l', + 'd', + '.', + 32, + 0, + /* 537 */ 's', + 'l', + 'd', + '.', + 32, + 0, + /* 543 */ 'n', + 'a', + 'n', + 'd', + '.', + 32, + 0, + /* 550 */ 't', + 'e', + 'n', + 'd', + '.', + 32, + 0, + /* 557 */ 's', + 'r', + 'd', + '.', + 32, + 0, + /* 563 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'd', + '.', + 32, + 0, + /* 574 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'u', + 'd', + '.', + 32, + 0, + /* 585 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'u', + 'd', + '.', + 32, + 0, + /* 596 */ 'd', + 'i', + 'v', + 'd', + '.', + 32, + 0, + /* 603 */ 'c', + 'n', + 't', + 'l', + 'z', + 'd', + '.', + 32, + 0, + /* 612 */ 'c', + 'n', + 't', + 't', + 'z', + 'd', + '.', + 32, + 0, + /* 621 */ 'a', + 'd', + 'd', + 'e', + '.', + 32, + 0, + /* 628 */ 'd', + 'i', + 'v', + 'd', + 'e', + '.', + 32, + 0, + /* 636 */ 's', + 'u', + 'b', + 'f', + 'e', + '.', + 32, + 0, + /* 644 */ 'a', + 'd', + 'd', + 'm', + 'e', + '.', + 32, + 0, + /* 652 */ 's', + 'u', + 'b', + 'f', + 'm', + 'e', + '.', + 32, + 0, + /* 661 */ 'f', + 'r', + 'e', + '.', + 32, + 0, + /* 667 */ 'f', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + '.', + 32, + 0, + /* 677 */ 'p', + 'a', + 's', + 't', + 'e', + '.', + 32, + 0, + /* 685 */ 'd', + 'i', + 'v', + 'w', + 'e', + '.', + 32, + 0, + /* 693 */ 'a', + 'd', + 'd', + 'z', + 'e', + '.', + 32, + 0, + /* 701 */ 's', + 'u', + 'b', + 'f', + 'z', + 'e', + '.', + 32, + 0, + /* 710 */ 's', + 'u', + 'b', + 'f', + '.', + 32, + 0, + /* 717 */ 'm', + 't', + 'f', + 's', + 'f', + '.', + 32, + 0, + /* 725 */ 'f', + 'n', + 'e', + 'g', + '.', + 32, + 0, + /* 732 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'h', + '.', + 32, + 0, + /* 742 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'h', + '.', + 32, + 0, + /* 753 */ 'e', + 'x', + 't', + 's', + 'h', + '.', + 32, + 0, + /* 761 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'u', + 'h', + '.', + 32, + 0, + /* 772 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'u', + 'h', + '.', + 32, + 0, + /* 783 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'z', + 'h', + '.', + 32, + 0, + /* 794 */ 't', + 'a', + 'b', + 'o', + 'r', + 't', + 'd', + 'c', + 'i', + '.', + 32, + 0, + /* 806 */ 't', + 'a', + 'b', + 'o', + 'r', + 't', + 'w', + 'c', + 'i', + '.', + 32, + 0, + /* 818 */ 's', + 'r', + 'a', + 'd', + 'i', + '.', + 32, + 0, + /* 826 */ 'c', + 'l', + 'r', + 'l', + 's', + 'l', + 'd', + 'i', + '.', + 32, + 0, + /* 837 */ 'e', + 'x', + 't', + 'l', + 'd', + 'i', + '.', + 32, + 0, + /* 846 */ 'a', + 'n', + 'd', + 'i', + '.', + 32, + 0, + /* 853 */ 'c', + 'l', + 'r', + 'r', + 'd', + 'i', + '.', + 32, + 0, + /* 862 */ 'i', + 'n', + 's', + 'r', + 'd', + 'i', + '.', + 32, + 0, + /* 871 */ 'r', + 'o', + 't', + 'r', + 'd', + 'i', + '.', + 32, + 0, + /* 880 */ 'e', + 'x', + 't', + 'r', + 'd', + 'i', + '.', + 32, + 0, + /* 889 */ 'm', + 't', + 'f', + 's', + 'f', + 'i', + '.', + 32, + 0, + /* 898 */ 'e', + 'x', + 't', + 's', + 'w', + 's', + 'l', + 'i', + '.', + 32, + 0, + /* 909 */ 'r', + 'l', + 'd', + 'i', + 'm', + 'i', + '.', + 32, + 0, + /* 918 */ 'r', + 'l', + 'w', + 'i', + 'm', + 'i', + '.', + 32, + 0, + /* 927 */ 's', + 'r', + 'a', + 'w', + 'i', + '.', + 32, + 0, + /* 935 */ 'c', + 'l', + 'r', + 'l', + 's', + 'l', + 'w', + 'i', + '.', + 32, + 0, + /* 946 */ 'i', + 'n', + 's', + 'l', + 'w', + 'i', + '.', + 32, + 0, + /* 955 */ 'e', + 'x', + 't', + 'l', + 'w', + 'i', + '.', + 32, + 0, + /* 964 */ 'c', + 'l', + 'r', + 'r', + 'w', + 'i', + '.', + 32, + 0, + /* 973 */ 'i', + 'n', + 's', + 'r', + 'w', + 'i', + '.', + 32, + 0, + /* 982 */ 'r', + 'o', + 't', + 'r', + 'w', + 'i', + '.', + 32, + 0, + /* 991 */ 'e', + 'x', + 't', + 'r', + 'w', + 'i', + '.', + 32, + 0, + /* 1000 */ 'r', + 'l', + 'd', + 'c', + 'l', + '.', + 32, + 0, + /* 1008 */ 'r', + 'l', + 'd', + 'i', + 'c', + 'l', + '.', + 32, + 0, + /* 1017 */ 'f', + 's', + 'e', + 'l', + '.', + 32, + 0, + /* 1024 */ 'f', + 'm', + 'u', + 'l', + '.', + 32, + 0, + /* 1031 */ 't', + 'r', + 'e', + 'c', + 'l', + 'a', + 'i', + 'm', + '.', + 32, + 0, + /* 1042 */ 'f', + 'r', + 'i', + 'm', + '.', + 32, + 0, + /* 1049 */ 'r', + 'l', + 'w', + 'i', + 'n', + 'm', + '.', + 32, + 0, + /* 1058 */ 'r', + 'l', + 'w', + 'n', + 'm', + '.', + 32, + 0, + /* 1066 */ 'b', + 'c', + 'd', + 'c', + 'f', + 'n', + '.', + 32, + 0, + /* 1075 */ 'b', + 'c', + 'd', + 'c', + 'p', + 's', + 'g', + 'n', + '.', + 32, + 0, + /* 1086 */ 'f', + 'c', + 'p', + 's', + 'g', + 'n', + '.', + 32, + 0, + /* 1095 */ 'b', + 'c', + 'd', + 's', + 'e', + 't', + 's', + 'g', + 'n', + '.', + 32, + 0, + /* 1107 */ 't', + 'b', + 'e', + 'g', + 'i', + 'n', + '.', + 32, + 0, + /* 1116 */ 'f', + 'r', + 'i', + 'n', + '.', + 32, + 0, + /* 1123 */ 'b', + 'c', + 'd', + 'c', + 't', + 'n', + '.', + 32, + 0, + /* 1132 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'g', + 'e', + 'd', + 'p', + '.', + 32, + 0, + /* 1144 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'd', + 'p', + '.', + 32, + 0, + /* 1156 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'd', + 'p', + '.', + 32, + 0, + /* 1168 */ 'v', + 'c', + 'm', + 'p', + 'b', + 'f', + 'p', + '.', + 32, + 0, + /* 1178 */ 'v', + 'c', + 'm', + 'p', + 'g', + 'e', + 'f', + 'p', + '.', + 32, + 0, + /* 1189 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'f', + 'p', + '.', + 32, + 0, + /* 1200 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'f', + 'p', + '.', + 32, + 0, + /* 1211 */ 'f', + 'r', + 'i', + 'p', + '.', + 32, + 0, + /* 1218 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'g', + 'e', + 's', + 'p', + '.', + 32, + 0, + /* 1230 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 's', + 'p', + '.', + 32, + 0, + /* 1242 */ 'f', + 'r', + 's', + 'p', + '.', + 32, + 0, + /* 1249 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'p', + '.', + 32, + 0, + /* 1261 */ 'i', + 'c', + 'b', + 'l', + 'q', + '.', + 32, + 0, + /* 1269 */ 'b', + 'c', + 'd', + 'c', + 'f', + 's', + 'q', + '.', + 32, + 0, + /* 1279 */ 'b', + 'c', + 'd', + 'c', + 't', + 's', + 'q', + '.', + 32, + 0, + /* 1289 */ 'r', + 'l', + 'd', + 'c', + 'r', + '.', + 32, + 0, + /* 1297 */ 'r', + 'l', + 'd', + 'i', + 'c', + 'r', + '.', + 32, + 0, + /* 1306 */ 'f', + 'm', + 'r', + '.', + 32, + 0, + /* 1312 */ 'n', + 'o', + 'r', + '.', + 32, + 0, + /* 1318 */ 'x', + 'o', + 'r', + '.', + 32, + 0, + /* 1324 */ 'b', + 'c', + 'd', + 's', + 'r', + '.', + 32, + 0, + /* 1332 */ 't', + 's', + 'r', + '.', + 32, + 0, + /* 1338 */ 'f', + 'a', + 'b', + 's', + '.', + 32, + 0, + /* 1345 */ 'f', + 'n', + 'a', + 'b', + 's', + '.', + 32, + 0, + /* 1353 */ 'f', + 's', + 'u', + 'b', + 's', + '.', + 32, + 0, + /* 1361 */ 'f', + 'm', + 's', + 'u', + 'b', + 's', + '.', + 32, + 0, + /* 1370 */ 'f', + 'n', + 'm', + 's', + 'u', + 'b', + 's', + '.', + 32, + 0, + /* 1380 */ 'b', + 'c', + 'd', + 's', + '.', + 32, + 0, + /* 1387 */ 'f', + 'a', + 'd', + 'd', + 's', + '.', + 32, + 0, + /* 1395 */ 'f', + 'm', + 'a', + 'd', + 'd', + 's', + '.', + 32, + 0, + /* 1404 */ 'f', + 'n', + 'm', + 'a', + 'd', + 'd', + 's', + '.', + 32, + 0, + /* 1414 */ 'f', + 'c', + 'f', + 'i', + 'd', + 's', + '.', + 32, + 0, + /* 1423 */ 'f', + 'r', + 'e', + 's', + '.', + 32, + 0, + /* 1430 */ 'f', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 's', + '.', + 32, + 0, + /* 1441 */ 'm', + 'f', + 'f', + 's', + '.', + 32, + 0, + /* 1448 */ 'a', + 'n', + 'd', + 'i', + 's', + '.', + 32, + 0, + /* 1456 */ 'f', + 'm', + 'u', + 'l', + 's', + '.', + 32, + 0, + /* 1464 */ 'f', + 's', + 'q', + 'r', + 't', + 's', + '.', + 32, + 0, + /* 1473 */ 'b', + 'c', + 'd', + 'u', + 's', + '.', + 32, + 0, + /* 1481 */ 'f', + 'c', + 'f', + 'i', + 'd', + 'u', + 's', + '.', + 32, + 0, + /* 1491 */ 'f', + 'd', + 'i', + 'v', + 's', + '.', + 32, + 0, + /* 1499 */ 't', + 'a', + 'b', + 'o', + 'r', + 't', + '.', + 32, + 0, + /* 1508 */ 'f', + 's', + 'q', + 'r', + 't', + '.', + 32, + 0, + /* 1516 */ 'm', + 'u', + 'l', + 'h', + 'd', + 'u', + '.', + 32, + 0, + /* 1525 */ 'f', + 'c', + 'f', + 'i', + 'd', + 'u', + '.', + 32, + 0, + /* 1534 */ 'f', + 'c', + 't', + 'i', + 'd', + 'u', + '.', + 32, + 0, + /* 1543 */ 'd', + 'i', + 'v', + 'd', + 'u', + '.', + 32, + 0, + /* 1551 */ 'd', + 'i', + 'v', + 'd', + 'e', + 'u', + '.', + 32, + 0, + /* 1560 */ 'd', + 'i', + 'v', + 'w', + 'e', + 'u', + '.', + 32, + 0, + /* 1569 */ 'm', + 'u', + 'l', + 'h', + 'w', + 'u', + '.', + 32, + 0, + /* 1578 */ 'f', + 'c', + 't', + 'i', + 'w', + 'u', + '.', + 32, + 0, + /* 1587 */ 'd', + 'i', + 'v', + 'w', + 'u', + '.', + 32, + 0, + /* 1595 */ 'f', + 'd', + 'i', + 'v', + '.', + 32, + 0, + /* 1602 */ 'e', + 'q', + 'v', + '.', + 32, + 0, + /* 1608 */ 's', + 'r', + 'a', + 'w', + '.', + 32, + 0, + /* 1615 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'w', + '.', + 32, + 0, + /* 1625 */ 'm', + 'u', + 'l', + 'h', + 'w', + '.', + 32, + 0, + /* 1633 */ 'f', + 'c', + 't', + 'i', + 'w', + '.', + 32, + 0, + /* 1641 */ 'm', + 'u', + 'l', + 'l', + 'w', + '.', + 32, + 0, + /* 1649 */ 's', + 'l', + 'w', + '.', + 32, + 0, + /* 1655 */ 's', + 'r', + 'w', + '.', + 32, + 0, + /* 1661 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'w', + '.', + 32, + 0, + /* 1672 */ 'e', + 'x', + 't', + 's', + 'w', + '.', + 32, + 0, + /* 1680 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'u', + 'w', + '.', + 32, + 0, + /* 1691 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'u', + 'w', + '.', + 32, + 0, + /* 1702 */ 'd', + 'i', + 'v', + 'w', + '.', + 32, + 0, + /* 1709 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'z', + 'w', + '.', + 32, + 0, + /* 1720 */ 'c', + 'n', + 't', + 'l', + 'z', + 'w', + '.', + 32, + 0, + /* 1729 */ 'c', + 'n', + 't', + 't', + 'z', + 'w', + '.', + 32, + 0, + /* 1738 */ 's', + 't', + 'b', + 'c', + 'x', + '.', + 32, + 0, + /* 1746 */ 's', + 't', + 'd', + 'c', + 'x', + '.', + 32, + 0, + /* 1754 */ 's', + 't', + 'h', + 'c', + 'x', + '.', + 32, + 0, + /* 1762 */ 's', + 't', + 'w', + 'c', + 'x', + '.', + 32, + 0, + /* 1770 */ 't', + 'l', + 'b', + 's', + 'x', + '.', + 32, + 0, + /* 1778 */ 'f', + 'c', + 't', + 'i', + 'd', + 'z', + '.', + 32, + 0, + /* 1787 */ 'b', + 'c', + 'd', + 'c', + 'f', + 'z', + '.', + 32, + 0, + /* 1796 */ 'f', + 'r', + 'i', + 'z', + '.', + 32, + 0, + /* 1803 */ 'b', + 'c', + 'd', + 'c', + 't', + 'z', + '.', + 32, + 0, + /* 1812 */ 'f', + 'c', + 't', + 'i', + 'd', + 'u', + 'z', + '.', + 32, + 0, + /* 1822 */ 'f', + 'c', + 't', + 'i', + 'w', + 'u', + 'z', + '.', + 32, + 0, + /* 1832 */ 'f', + 'c', + 't', + 'i', + 'w', + 'z', + '.', + 32, + 0, + /* 1841 */ 'm', + 't', + 'f', + 's', + 'b', + '0', + 32, + 0, + /* 1849 */ 'm', + 't', + 'f', + 's', + 'b', + '1', + 32, + 0, + /* 1857 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'C', + 'M', + 'P', + '_', + 'S', + 'W', + 'A', + 'P', + '_', + 'I', + '3', + '2', + 32, + 0, + /* 1879 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'C', + 'M', + 'P', + '_', + 'S', + 'W', + 'A', + 'P', + '_', + 'I', + '1', + '6', + 32, + 0, + /* 1901 */ '#', + 'T', + 'C', + '_', + 'R', + 'E', + 'T', + 'U', + 'R', + 'N', + 'a', + '8', + 32, + 0, + /* 1915 */ '#', + 'T', + 'C', + '_', + 'R', + 'E', + 'T', + 'U', + 'R', + 'N', + 'd', + '8', + 32, + 0, + /* 1929 */ '#', + 'T', + 'C', + '_', + 'R', + 'E', + 'T', + 'U', + 'R', + 'N', + 'r', + '8', + 32, + 0, + /* 1943 */ 'U', + 'P', + 'D', + 'A', + 'T', + 'E', + '_', + 'V', + 'R', + 'S', + 'A', + 'V', + 'E', + 32, + 0, + /* 1958 */ '#', + 'A', + 'D', + 'J', + 'C', + 'A', + 'L', + 'L', + 'S', + 'T', + 'A', + 'C', + 'K', + 'D', + 'O', + 'W', + 'N', + 32, + 0, + /* 1977 */ '#', + 'A', + 'D', + 'J', + 'C', + 'A', + 'L', + 'L', + 'S', + 'T', + 'A', + 'C', + 'K', + 'U', + 'P', + 32, + 0, + /* 1994 */ '#', + 'T', + 'C', + '_', + 'R', + 'E', + 'T', + 'U', + 'R', + 'N', + 'a', + 32, + 0, + /* 2007 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'g', + 's', + 'm', + 'f', + 'a', + 'a', + 32, + 0, + /* 2020 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'g', + 's', + 'm', + 'f', + 'a', + 'a', + 32, + 0, + /* 2033 */ 'e', + 'v', + 'm', + 'w', + 's', + 'm', + 'f', + 'a', + 'a', + 32, + 0, + /* 2044 */ 'e', + 'v', + 'm', + 'w', + 's', + 's', + 'f', + 'a', + 'a', + 32, + 0, + /* 2055 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'g', + 's', + 'm', + 'i', + 'a', + 'a', + 32, + 0, + /* 2068 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'g', + 's', + 'm', + 'i', + 'a', + 'a', + 32, + 0, + /* 2081 */ 'e', + 'v', + 'm', + 'w', + 's', + 'm', + 'i', + 'a', + 'a', + 32, + 0, + /* 2092 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'g', + 'u', + 'm', + 'i', + 'a', + 'a', + 32, + 0, + /* 2105 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'g', + 'u', + 'm', + 'i', + 'a', + 'a', + 32, + 0, + /* 2118 */ 'e', + 'v', + 'm', + 'w', + 'u', + 'm', + 'i', + 'a', + 'a', + 32, + 0, + /* 2129 */ 'd', + 'c', + 'b', + 'a', + 32, + 0, + /* 2135 */ 'b', + 'c', + 'a', + 32, + 0, + /* 2140 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 'm', + 'f', + 'a', + 32, + 0, + /* 2151 */ 'e', + 'v', + 'm', + 'w', + 'h', + 's', + 'm', + 'f', + 'a', + 32, + 0, + /* 2162 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 'm', + 'f', + 'a', + 32, + 0, + /* 2173 */ 'e', + 'v', + 'm', + 'w', + 's', + 'm', + 'f', + 'a', + 32, + 0, + /* 2183 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 's', + 'f', + 'a', + 32, + 0, + /* 2194 */ 'e', + 'v', + 'm', + 'w', + 'h', + 's', + 's', + 'f', + 'a', + 32, + 0, + /* 2205 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 's', + 'f', + 'a', + 32, + 0, + /* 2216 */ 'e', + 'v', + 'm', + 'w', + 's', + 's', + 'f', + 'a', + 32, + 0, + /* 2226 */ 'l', + 'h', + 'a', + 32, + 0, + /* 2231 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 'm', + 'i', + 'a', + 32, + 0, + /* 2242 */ 'e', + 'v', + 'm', + 'w', + 'h', + 's', + 'm', + 'i', + 'a', + 32, + 0, + /* 2253 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 'm', + 'i', + 'a', + 32, + 0, + /* 2264 */ 'e', + 'v', + 'm', + 'w', + 's', + 'm', + 'i', + 'a', + 32, + 0, + /* 2274 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'u', + 'm', + 'i', + 'a', + 32, + 0, + /* 2285 */ 'e', + 'v', + 'm', + 'w', + 'h', + 'u', + 'm', + 'i', + 'a', + 32, + 0, + /* 2296 */ 'e', + 'v', + 'm', + 'w', + 'l', + 'u', + 'm', + 'i', + 'a', + 32, + 0, + /* 2307 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'u', + 'm', + 'i', + 'a', + 32, + 0, + /* 2318 */ 'e', + 'v', + 'm', + 'w', + 'u', + 'm', + 'i', + 'a', + 32, + 0, + /* 2328 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 'd', + 'x', + 'i', + 'a', + 32, + 0, + /* 2340 */ 'q', + 'v', + 's', + 't', + 'f', + 'd', + 'x', + 'i', + 'a', + 32, + 0, + /* 2351 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 's', + 'x', + 'i', + 'a', + 32, + 0, + /* 2363 */ 'q', + 'v', + 's', + 't', + 'f', + 's', + 'x', + 'i', + 'a', + 32, + 0, + /* 2374 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 'd', + 'u', + 'x', + 'i', + 'a', + 32, + 0, + /* 2387 */ 'q', + 'v', + 's', + 't', + 'f', + 'd', + 'u', + 'x', + 'i', + 'a', + 32, + 0, + /* 2399 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 's', + 'u', + 'x', + 'i', + 'a', + 32, + 0, + /* 2412 */ 'q', + 'v', + 's', + 't', + 'f', + 's', + 'u', + 'x', + 'i', + 'a', + 32, + 0, + /* 2424 */ 'b', + 'l', + 'a', + 32, + 0, + /* 2429 */ 'b', + 'c', + 'l', + 'a', + 32, + 0, + /* 2435 */ 'b', + 'd', + 'z', + 'l', + 'a', + 32, + 0, + /* 2442 */ 'b', + 'd', + 'n', + 'z', + 'l', + 'a', + 32, + 0, + /* 2450 */ 'e', + 'v', + 'm', + 'r', + 'a', + 32, + 0, + /* 2457 */ 'l', + 'w', + 'a', + 32, + 0, + /* 2462 */ 'm', + 't', + 'v', + 's', + 'r', + 'w', + 'a', + 32, + 0, + /* 2471 */ 'q', + 'v', + 'l', + 'f', + 'i', + 'w', + 'a', + 'x', + 'a', + 32, + 0, + /* 2482 */ 'q', + 'v', + 'l', + 'f', + 'c', + 'd', + 'x', + 'a', + 32, + 0, + /* 2492 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 'd', + 'x', + 'a', + 32, + 0, + /* 2503 */ 'q', + 'v', + 'l', + 'f', + 'd', + 'x', + 'a', + 32, + 0, + /* 2512 */ 'q', + 'v', + 's', + 't', + 'f', + 'd', + 'x', + 'a', + 32, + 0, + /* 2522 */ 'q', + 'v', + 'l', + 'f', + 'c', + 's', + 'x', + 'a', + 32, + 0, + /* 2532 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 's', + 'x', + 'a', + 32, + 0, + /* 2543 */ 'q', + 'v', + 'l', + 'f', + 's', + 'x', + 'a', + 32, + 0, + /* 2552 */ 'q', + 'v', + 's', + 't', + 'f', + 's', + 'x', + 'a', + 32, + 0, + /* 2562 */ 'q', + 'v', + 'l', + 'f', + 'c', + 'd', + 'u', + 'x', + 'a', + 32, + 0, + /* 2573 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 'd', + 'u', + 'x', + 'a', + 32, + 0, + /* 2585 */ 'q', + 'v', + 'l', + 'f', + 'd', + 'u', + 'x', + 'a', + 32, + 0, + /* 2595 */ 'q', + 'v', + 's', + 't', + 'f', + 'd', + 'u', + 'x', + 'a', + 32, + 0, + /* 2606 */ 'q', + 'v', + 'l', + 'f', + 'c', + 's', + 'u', + 'x', + 'a', + 32, + 0, + /* 2617 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 's', + 'u', + 'x', + 'a', + 32, + 0, + /* 2629 */ 'q', + 'v', + 'l', + 'f', + 's', + 'u', + 'x', + 'a', + 32, + 0, + /* 2639 */ 'q', + 'v', + 's', + 't', + 'f', + 's', + 'u', + 'x', + 'a', + 32, + 0, + /* 2650 */ 'q', + 'v', + 's', + 't', + 'f', + 'i', + 'w', + 'x', + 'a', + 32, + 0, + /* 2661 */ 'q', + 'v', + 'l', + 'f', + 'i', + 'w', + 'z', + 'x', + 'a', + 32, + 0, + /* 2672 */ 'b', + 'd', + 'z', + 'a', + 32, + 0, + /* 2678 */ 'b', + 'd', + 'n', + 'z', + 'a', + 32, + 0, + /* 2685 */ 'v', + 's', + 'r', + 'a', + 'b', + 32, + 0, + /* 2692 */ 'r', + 'f', + 'e', + 'b', + 'b', + 32, + 0, + /* 2699 */ 'v', + 'c', + 'l', + 'z', + 'l', + 's', + 'b', + 'b', + 32, + 0, + /* 2709 */ 'v', + 'c', + 't', + 'z', + 'l', + 's', + 'b', + 'b', + 32, + 0, + /* 2719 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'b', + 32, + 0, + /* 2728 */ 'v', + 'm', + 'r', + 'g', + 'h', + 'b', + 32, + 0, + /* 2736 */ 'x', + 'x', + 's', + 'p', + 'l', + 't', + 'i', + 'b', + 32, + 0, + /* 2746 */ 'v', + 'm', + 'r', + 'g', + 'l', + 'b', + 32, + 0, + /* 2754 */ 'v', + 'r', + 'l', + 'b', + 32, + 0, + /* 2760 */ 'v', + 's', + 'l', + 'b', + 32, + 0, + /* 2766 */ 'v', + 'p', + 'm', + 's', + 'u', + 'm', + 'b', + 32, + 0, + /* 2775 */ 'c', + 'm', + 'p', + 'b', + 32, + 0, + /* 2781 */ 'c', + 'm', + 'p', + 'e', + 'q', + 'b', + 32, + 0, + /* 2789 */ 'c', + 'm', + 'p', + 'r', + 'b', + 32, + 0, + /* 2796 */ 'v', + 's', + 'r', + 'b', + 32, + 0, + /* 2802 */ 'v', + 'm', + 'u', + 'l', + 'e', + 's', + 'b', + 32, + 0, + /* 2811 */ 'v', + 'a', + 'v', + 'g', + 's', + 'b', + 32, + 0, + /* 2819 */ 'v', + 'u', + 'p', + 'k', + 'h', + 's', + 'b', + 32, + 0, + /* 2828 */ 'v', + 's', + 'p', + 'l', + 't', + 'i', + 's', + 'b', + 32, + 0, + /* 2838 */ 'v', + 'u', + 'p', + 'k', + 'l', + 's', + 'b', + 32, + 0, + /* 2847 */ 'v', + 'm', + 'i', + 'n', + 's', + 'b', + 32, + 0, + /* 2855 */ 'v', + 'm', + 'u', + 'l', + 'o', + 's', + 'b', + 32, + 0, + /* 2864 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'b', + 32, + 0, + /* 2874 */ 'e', + 'v', + 'e', + 'x', + 't', + 's', + 'b', + 32, + 0, + /* 2883 */ 'v', + 'm', + 'a', + 'x', + 's', + 'b', + 32, + 0, + /* 2891 */ 's', + 'e', + 't', + 'b', + 32, + 0, + /* 2897 */ 'm', + 'f', + 't', + 'b', + 32, + 0, + /* 2903 */ 'v', + 's', + 'p', + 'l', + 't', + 'b', + 32, + 0, + /* 2911 */ 'v', + 'p', + 'o', + 'p', + 'c', + 'n', + 't', + 'b', + 32, + 0, + /* 2921 */ 'v', + 'i', + 'n', + 's', + 'e', + 'r', + 't', + 'b', + 32, + 0, + /* 2931 */ 's', + 't', + 'b', + 32, + 0, + /* 2936 */ 'v', + 'a', + 'b', + 's', + 'd', + 'u', + 'b', + 32, + 0, + /* 2945 */ 'v', + 'm', + 'u', + 'l', + 'e', + 'u', + 'b', + 32, + 0, + /* 2954 */ 'v', + 'a', + 'v', + 'g', + 'u', + 'b', + 32, + 0, + /* 2962 */ 'v', + 'm', + 'i', + 'n', + 'u', + 'b', + 32, + 0, + /* 2970 */ 'v', + 'm', + 'u', + 'l', + 'o', + 'u', + 'b', + 32, + 0, + /* 2979 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'u', + 'b', + 32, + 0, + /* 2989 */ 'e', + 'f', + 'd', + 's', + 'u', + 'b', + 32, + 0, + /* 2997 */ 'q', + 'v', + 'f', + 's', + 'u', + 'b', + 32, + 0, + /* 3005 */ 'q', + 'v', + 'f', + 'm', + 's', + 'u', + 'b', + 32, + 0, + /* 3014 */ 'q', + 'v', + 'f', + 'n', + 'm', + 's', + 'u', + 'b', + 32, + 0, + /* 3024 */ 'e', + 'f', + 's', + 's', + 'u', + 'b', + 32, + 0, + /* 3032 */ 'e', + 'v', + 'f', + 's', + 's', + 'u', + 'b', + 32, + 0, + /* 3041 */ 'v', + 'e', + 'x', + 't', + 'r', + 'a', + 'c', + 't', + 'u', + 'b', + 32, + 0, + /* 3053 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'u', + 'b', + 32, + 0, + /* 3063 */ 'v', + 'm', + 'a', + 'x', + 'u', + 'b', + 32, + 0, + /* 3071 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'z', + 'b', + 32, + 0, + /* 3081 */ 'v', + 'c', + 'l', + 'z', + 'b', + 32, + 0, + /* 3088 */ 'v', + 'c', + 't', + 'z', + 'b', + 32, + 0, + /* 3095 */ 'b', + 'c', + 32, + 0, + /* 3099 */ 'a', + 'd', + 'd', + 'c', + 32, + 0, + /* 3105 */ 'x', + 'x', + 'l', + 'a', + 'n', + 'd', + 'c', + 32, + 0, + /* 3114 */ 'c', + 'r', + 'a', + 'n', + 'd', + 'c', + 32, + 0, + /* 3122 */ 'e', + 'v', + 'a', + 'n', + 'd', + 'c', + 32, + 0, + /* 3130 */ 's', + 'u', + 'b', + 'f', + 'c', + 32, + 0, + /* 3137 */ 's', + 'u', + 'b', + 'i', + 'c', + 32, + 0, + /* 3144 */ 'a', + 'd', + 'd', + 'i', + 'c', + 32, + 0, + /* 3151 */ 'r', + 'l', + 'd', + 'i', + 'c', + 32, + 0, + /* 3158 */ 's', + 'u', + 'b', + 'f', + 'i', + 'c', + 32, + 0, + /* 3166 */ 'x', + 's', + 'r', + 'd', + 'p', + 'i', + 'c', + 32, + 0, + /* 3175 */ 'x', + 'v', + 'r', + 'd', + 'p', + 'i', + 'c', + 32, + 0, + /* 3184 */ 'x', + 'v', + 'r', + 's', + 'p', + 'i', + 'c', + 32, + 0, + /* 3193 */ 'i', + 'c', + 'b', + 'l', + 'c', + 32, + 0, + /* 3200 */ 'b', + 'r', + 'i', + 'n', + 'c', + 32, + 0, + /* 3207 */ 's', + 'y', + 'n', + 'c', + 32, + 0, + /* 3213 */ 'x', + 'x', + 'l', + 'o', + 'r', + 'c', + 32, + 0, + /* 3221 */ 'c', + 'r', + 'o', + 'r', + 'c', + 32, + 0, + /* 3228 */ 'e', + 'v', + 'o', + 'r', + 'c', + 32, + 0, + /* 3235 */ 's', + 'c', + 32, + 0, + /* 3239 */ 'v', + 'e', + 'x', + 't', + 's', + 'b', + '2', + 'd', + 32, + 0, + /* 3249 */ 'v', + 'e', + 'x', + 't', + 's', + 'h', + '2', + 'd', + 32, + 0, + /* 3259 */ 'v', + 'e', + 'x', + 't', + 's', + 'w', + '2', + 'd', + 32, + 0, + /* 3269 */ '#', + 'T', + 'C', + '_', + 'R', + 'E', + 'T', + 'U', + 'R', + 'N', + 'd', + 32, + 0, + /* 3282 */ 'v', + 's', + 'h', + 'a', + 's', + 'i', + 'g', + 'm', + 'a', + 'd', + 32, + 0, + /* 3294 */ 'v', + 's', + 'r', + 'a', + 'd', + 32, + 0, + /* 3301 */ 'v', + 'g', + 'b', + 'b', + 'd', + 32, + 0, + /* 3308 */ 'v', + 'p', + 'r', + 't', + 'y', + 'b', + 'd', + 32, + 0, + /* 3317 */ 'e', + 'f', + 'd', + 'a', + 'd', + 'd', + 32, + 0, + /* 3325 */ 'q', + 'v', + 'f', + 'a', + 'd', + 'd', + 32, + 0, + /* 3333 */ 'q', + 'v', + 'f', + 'm', + 'a', + 'd', + 'd', + 32, + 0, + /* 3342 */ 'q', + 'v', + 'f', + 'n', + 'm', + 'a', + 'd', + 'd', + 32, + 0, + /* 3352 */ 'q', + 'v', + 'f', + 'x', + 'x', + 'c', + 'p', + 'n', + 'm', + 'a', + 'd', + 'd', + 32, + 0, + /* 3366 */ 'q', + 'v', + 'f', + 'x', + 'x', + 'n', + 'p', + 'm', + 'a', + 'd', + 'd', + 32, + 0, + /* 3379 */ 'q', + 'v', + 'f', + 'x', + 'm', + 'a', + 'd', + 'd', + 32, + 0, + /* 3389 */ 'q', + 'v', + 'f', + 'x', + 'x', + 'm', + 'a', + 'd', + 'd', + 32, + 0, + /* 3400 */ 'e', + 'f', + 's', + 'a', + 'd', + 'd', + 32, + 0, + /* 3408 */ 'e', + 'v', + 'f', + 's', + 'a', + 'd', + 'd', + 32, + 0, + /* 3417 */ 'e', + 'v', + 'l', + 'd', + 'd', + 32, + 0, + /* 3424 */ 'm', + 't', + 'v', + 's', + 'r', + 'd', + 'd', + 32, + 0, + /* 3433 */ 'e', + 'v', + 's', + 't', + 'd', + 'd', + 32, + 0, + /* 3441 */ 'e', + 'f', + 's', + 'c', + 'f', + 'd', + 32, + 0, + /* 3449 */ 'l', + 'f', + 'd', + 32, + 0, + /* 3454 */ 's', + 't', + 'f', + 'd', + 32, + 0, + /* 3460 */ 'v', + 'n', + 'e', + 'g', + 'd', + 32, + 0, + /* 3467 */ 'm', + 'a', + 'd', + 'd', + 'h', + 'd', + 32, + 0, + /* 3475 */ 'm', + 'u', + 'l', + 'h', + 'd', + 32, + 0, + /* 3482 */ 'q', + 'v', + 'f', + 'c', + 'f', + 'i', + 'd', + 32, + 0, + /* 3491 */ 'e', + 'f', + 'd', + 'c', + 'f', + 's', + 'i', + 'd', + 32, + 0, + /* 3501 */ 'q', + 'v', + 'f', + 'c', + 't', + 'i', + 'd', + 32, + 0, + /* 3510 */ 'e', + 'f', + 'd', + 'c', + 'f', + 'u', + 'i', + 'd', + 32, + 0, + /* 3520 */ 't', + 'l', + 'b', + 'l', + 'd', + 32, + 0, + /* 3527 */ 'm', + 'a', + 'd', + 'd', + 'l', + 'd', + 32, + 0, + /* 3535 */ 'm', + 'u', + 'l', + 'l', + 'd', + 32, + 0, + /* 3542 */ 'c', + 'm', + 'p', + 'l', + 'd', + 32, + 0, + /* 3549 */ 'm', + 'f', + 'v', + 's', + 'r', + 'l', + 'd', + 32, + 0, + /* 3558 */ 'v', + 'r', + 'l', + 'd', + 32, + 0, + /* 3564 */ 'v', + 's', + 'l', + 'd', + 32, + 0, + /* 3570 */ 'v', + 'b', + 'p', + 'e', + 'r', + 'm', + 'd', + 32, + 0, + /* 3579 */ 'v', + 'p', + 'm', + 's', + 'u', + 'm', + 'd', + 32, + 0, + /* 3588 */ 'x', + 'x', + 'l', + 'a', + 'n', + 'd', + 32, + 0, + /* 3596 */ 'x', + 'x', + 'l', + 'n', + 'a', + 'n', + 'd', + 32, + 0, + /* 3605 */ 'c', + 'r', + 'n', + 'a', + 'n', + 'd', + 32, + 0, + /* 3613 */ 'e', + 'v', + 'n', + 'a', + 'n', + 'd', + 32, + 0, + /* 3621 */ 'c', + 'r', + 'a', + 'n', + 'd', + 32, + 0, + /* 3628 */ 'e', + 'v', + 'a', + 'n', + 'd', + 32, + 0, + /* 3635 */ 'c', + 'm', + 'p', + 'd', + 32, + 0, + /* 3641 */ 'x', + 'x', + 'b', + 'r', + 'd', + 32, + 0, + /* 3648 */ 'm', + 't', + 'm', + 's', + 'r', + 'd', + 32, + 0, + /* 3656 */ 'm', + 'f', + 'v', + 's', + 'r', + 'd', + 32, + 0, + /* 3664 */ 'm', + 't', + 'v', + 's', + 'r', + 'd', + 32, + 0, + /* 3672 */ 'm', + 'o', + 'd', + 's', + 'd', + 32, + 0, + /* 3679 */ 'v', + 'm', + 'i', + 'n', + 's', + 'd', + 32, + 0, + /* 3687 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'd', + 32, + 0, + /* 3697 */ 'v', + 'm', + 'a', + 'x', + 's', + 'd', + 32, + 0, + /* 3705 */ 'l', + 'x', + 's', + 'd', + 32, + 0, + /* 3711 */ 's', + 't', + 'x', + 's', + 'd', + 32, + 0, + /* 3718 */ 'v', + 'e', + 'x', + 't', + 'r', + 'a', + 'c', + 't', + 'd', + 32, + 0, + /* 3729 */ 'v', + 'p', + 'o', + 'p', + 'c', + 'n', + 't', + 'd', + 32, + 0, + /* 3739 */ 'v', + 'i', + 'n', + 's', + 'e', + 'r', + 't', + 'd', + 32, + 0, + /* 3749 */ 's', + 't', + 'd', + 32, + 0, + /* 3754 */ 'm', + 'o', + 'd', + 'u', + 'd', + 32, + 0, + /* 3761 */ 'v', + 'm', + 'i', + 'n', + 'u', + 'd', + 32, + 0, + /* 3769 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'u', + 'd', + 32, + 0, + /* 3779 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'u', + 'd', + 32, + 0, + /* 3789 */ 'v', + 'm', + 'a', + 'x', + 'u', + 'd', + 32, + 0, + /* 3797 */ 'd', + 'i', + 'v', + 'd', + 32, + 0, + /* 3803 */ 'v', + 'c', + 'l', + 'z', + 'd', + 32, + 0, + /* 3810 */ 'c', + 'n', + 't', + 'l', + 'z', + 'd', + 32, + 0, + /* 3818 */ 'v', + 'c', + 't', + 'z', + 'd', + 32, + 0, + /* 3825 */ 'c', + 'n', + 't', + 't', + 'z', + 'd', + 32, + 0, + /* 3833 */ 'm', + 'f', + 'b', + 'h', + 'r', + 'b', + 'e', + 32, + 0, + /* 3842 */ 'm', + 'f', + 'f', + 's', + 'c', + 'e', + 32, + 0, + /* 3850 */ 'a', + 'd', + 'd', + 'e', + 32, + 0, + /* 3856 */ 'd', + 'i', + 'v', + 'd', + 'e', + 32, + 0, + /* 3863 */ 's', + 'l', + 'b', + 'm', + 'f', + 'e', + 'e', + 32, + 0, + /* 3872 */ 'w', + 'r', + 't', + 'e', + 'e', + 32, + 0, + /* 3879 */ 's', + 'u', + 'b', + 'f', + 'e', + 32, + 0, + /* 3886 */ 'e', + 'v', + 'l', + 'w', + 'h', + 'e', + 32, + 0, + /* 3894 */ 'e', + 'v', + 's', + 't', + 'w', + 'h', + 'e', + 32, + 0, + /* 3903 */ 's', + 'l', + 'b', + 'i', + 'e', + 32, + 0, + /* 3910 */ 't', + 'l', + 'b', + 'i', + 'e', + 32, + 0, + /* 3917 */ 'a', + 'd', + 'd', + 'm', + 'e', + 32, + 0, + /* 3924 */ 's', + 'u', + 'b', + 'f', + 'm', + 'e', + 32, + 0, + /* 3932 */ 't', + 'l', + 'b', + 'r', + 'e', + 32, + 0, + /* 3939 */ 'q', + 'v', + 'f', + 'r', + 'e', + 32, + 0, + /* 3946 */ 's', + 'l', + 'b', + 'm', + 't', + 'e', + 32, + 0, + /* 3954 */ 'q', + 'v', + 'f', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 32, + 0, + /* 3965 */ 'p', + 'a', + 's', + 't', + 'e', + 32, + 0, + /* 3972 */ 't', + 'l', + 'b', + 'w', + 'e', + 32, + 0, + /* 3979 */ 'd', + 'i', + 'v', + 'w', + 'e', + 32, + 0, + /* 3986 */ 'e', + 'v', + 's', + 't', + 'w', + 'w', + 'e', + 32, + 0, + /* 3995 */ 'a', + 'd', + 'd', + 'z', + 'e', + 32, + 0, + /* 4002 */ 's', + 'u', + 'b', + 'f', + 'z', + 'e', + 32, + 0, + /* 4010 */ 'd', + 'c', + 'b', + 'f', + 32, + 0, + /* 4016 */ 's', + 'u', + 'b', + 'f', + 32, + 0, + /* 4022 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 'm', + 'f', + 32, + 0, + /* 4032 */ 'e', + 'v', + 'm', + 'w', + 'h', + 's', + 'm', + 'f', + 32, + 0, + /* 4042 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 'm', + 'f', + 32, + 0, + /* 4052 */ 'e', + 'v', + 'm', + 'w', + 's', + 'm', + 'f', + 32, + 0, + /* 4061 */ 'm', + 'c', + 'r', + 'f', + 32, + 0, + /* 4067 */ 'm', + 'f', + 'o', + 'c', + 'r', + 'f', + 32, + 0, + /* 4075 */ 'm', + 't', + 'o', + 'c', + 'r', + 'f', + 32, + 0, + /* 4083 */ 'm', + 't', + 'c', + 'r', + 'f', + 32, + 0, + /* 4090 */ 'e', + 'f', + 'd', + 'c', + 'f', + 's', + 'f', + 32, + 0, + /* 4099 */ 'e', + 'f', + 's', + 'c', + 'f', + 's', + 'f', + 32, + 0, + /* 4108 */ 'e', + 'v', + 'f', + 's', + 'c', + 'f', + 's', + 'f', + 32, + 0, + /* 4118 */ 'm', + 't', + 'f', + 's', + 'f', + 32, + 0, + /* 4125 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 's', + 'f', + 32, + 0, + /* 4135 */ 'e', + 'v', + 'm', + 'w', + 'h', + 's', + 's', + 'f', + 32, + 0, + /* 4145 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 's', + 'f', + 32, + 0, + /* 4155 */ 'e', + 'v', + 'm', + 'w', + 's', + 's', + 'f', + 32, + 0, + /* 4164 */ 'e', + 'f', + 'd', + 'c', + 't', + 's', + 'f', + 32, + 0, + /* 4173 */ 'e', + 'f', + 's', + 'c', + 't', + 's', + 'f', + 32, + 0, + /* 4182 */ 'e', + 'v', + 'f', + 's', + 'c', + 't', + 's', + 'f', + 32, + 0, + /* 4192 */ 'e', + 'f', + 'd', + 'c', + 'f', + 'u', + 'f', + 32, + 0, + /* 4201 */ 'e', + 'f', + 's', + 'c', + 'f', + 'u', + 'f', + 32, + 0, + /* 4210 */ 'e', + 'v', + 'f', + 's', + 'c', + 'f', + 'u', + 'f', + 32, + 0, + /* 4220 */ 'e', + 'f', + 'd', + 'c', + 't', + 'u', + 'f', + 32, + 0, + /* 4229 */ 'e', + 'f', + 's', + 'c', + 't', + 'u', + 'f', + 32, + 0, + /* 4238 */ 's', + 'l', + 'b', + 'i', + 'e', + 'g', + 32, + 0, + /* 4246 */ 'e', + 'f', + 'd', + 'n', + 'e', + 'g', + 32, + 0, + /* 4254 */ 'q', + 'v', + 'f', + 'n', + 'e', + 'g', + 32, + 0, + /* 4262 */ 'e', + 'f', + 's', + 'n', + 'e', + 'g', + 32, + 0, + /* 4270 */ 'e', + 'v', + 'f', + 's', + 'n', + 'e', + 'g', + 32, + 0, + /* 4279 */ 'e', + 'v', + 'n', + 'e', + 'g', + 32, + 0, + /* 4286 */ 'v', + 's', + 'r', + 'a', + 'h', + 32, + 0, + /* 4293 */ 'e', + 'v', + 'l', + 'd', + 'h', + 32, + 0, + /* 4300 */ 'e', + 'v', + 's', + 't', + 'd', + 'h', + 32, + 0, + /* 4308 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'h', + 32, + 0, + /* 4317 */ 'v', + 'm', + 'r', + 'g', + 'h', + 'h', + 32, + 0, + /* 4325 */ 'v', + 'm', + 'r', + 'g', + 'l', + 'h', + 32, + 0, + /* 4333 */ 'v', + 'r', + 'l', + 'h', + 32, + 0, + /* 4339 */ 'v', + 's', + 'l', + 'h', + 32, + 0, + /* 4345 */ 'v', + 'p', + 'm', + 's', + 'u', + 'm', + 'h', + 32, + 0, + /* 4354 */ 'x', + 'x', + 'b', + 'r', + 'h', + 32, + 0, + /* 4361 */ 'v', + 's', + 'r', + 'h', + 32, + 0, + /* 4367 */ 'v', + 'm', + 'u', + 'l', + 'e', + 's', + 'h', + 32, + 0, + /* 4376 */ 'v', + 'a', + 'v', + 'g', + 's', + 'h', + 32, + 0, + /* 4384 */ 'v', + 'u', + 'p', + 'k', + 'h', + 's', + 'h', + 32, + 0, + /* 4393 */ 'v', + 's', + 'p', + 'l', + 't', + 'i', + 's', + 'h', + 32, + 0, + /* 4403 */ 'v', + 'u', + 'p', + 'k', + 'l', + 's', + 'h', + 32, + 0, + /* 4412 */ 'v', + 'm', + 'i', + 'n', + 's', + 'h', + 32, + 0, + /* 4420 */ 'v', + 'm', + 'u', + 'l', + 'o', + 's', + 'h', + 32, + 0, + /* 4429 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'h', + 32, + 0, + /* 4439 */ 'e', + 'v', + 'e', + 'x', + 't', + 's', + 'h', + 32, + 0, + /* 4448 */ 'v', + 'm', + 'a', + 'x', + 's', + 'h', + 32, + 0, + /* 4456 */ 'v', + 's', + 'p', + 'l', + 't', + 'h', + 32, + 0, + /* 4464 */ 'v', + 'p', + 'o', + 'p', + 'c', + 'n', + 't', + 'h', + 32, + 0, + /* 4474 */ 'v', + 'i', + 'n', + 's', + 'e', + 'r', + 't', + 'h', + 32, + 0, + /* 4484 */ 's', + 't', + 'h', + 32, + 0, + /* 4489 */ 'v', + 'a', + 'b', + 's', + 'd', + 'u', + 'h', + 32, + 0, + /* 4498 */ 'v', + 'm', + 'u', + 'l', + 'e', + 'u', + 'h', + 32, + 0, + /* 4507 */ 'v', + 'a', + 'v', + 'g', + 'u', + 'h', + 32, + 0, + /* 4515 */ 'v', + 'm', + 'i', + 'n', + 'u', + 'h', + 32, + 0, + /* 4523 */ 'v', + 'm', + 'u', + 'l', + 'o', + 'u', + 'h', + 32, + 0, + /* 4532 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'u', + 'h', + 32, + 0, + /* 4542 */ 'v', + 'e', + 'x', + 't', + 'r', + 'a', + 'c', + 't', + 'u', + 'h', + 32, + 0, + /* 4554 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'u', + 'h', + 32, + 0, + /* 4564 */ 'v', + 'm', + 'a', + 'x', + 'u', + 'h', + 32, + 0, + /* 4572 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'z', + 'h', + 32, + 0, + /* 4582 */ 'v', + 'c', + 'l', + 'z', + 'h', + 32, + 0, + /* 4589 */ 'v', + 'c', + 't', + 'z', + 'h', + 32, + 0, + /* 4596 */ 'd', + 'c', + 'b', + 'i', + 32, + 0, + /* 4602 */ 'i', + 'c', + 'b', + 'i', + 32, + 0, + /* 4608 */ 's', + 'u', + 'b', + 'i', + 32, + 0, + /* 4614 */ 'd', + 'c', + 'c', + 'c', + 'i', + 32, + 0, + /* 4621 */ 'i', + 'c', + 'c', + 'c', + 'i', + 32, + 0, + /* 4628 */ 'q', + 'v', + 'g', + 'p', + 'c', + 'i', + 32, + 0, + /* 4636 */ 's', + 'r', + 'a', + 'd', + 'i', + 32, + 0, + /* 4643 */ 'a', + 'd', + 'd', + 'i', + 32, + 0, + /* 4649 */ 'c', + 'm', + 'p', + 'l', + 'd', + 'i', + 32, + 0, + /* 4657 */ 'c', + 'l', + 'r', + 'l', + 's', + 'l', + 'd', + 'i', + 32, + 0, + /* 4667 */ 'e', + 'x', + 't', + 'l', + 'd', + 'i', + 32, + 0, + /* 4675 */ 'x', + 'x', + 'p', + 'e', + 'r', + 'm', + 'd', + 'i', + 32, + 0, + /* 4685 */ 'c', + 'm', + 'p', + 'd', + 'i', + 32, + 0, + /* 4692 */ 'c', + 'l', + 'r', + 'r', + 'd', + 'i', + 32, + 0, + /* 4700 */ 'i', + 'n', + 's', + 'r', + 'd', + 'i', + 32, + 0, + /* 4708 */ 'r', + 'o', + 't', + 'r', + 'd', + 'i', + 32, + 0, + /* 4716 */ 'e', + 'x', + 't', + 'r', + 'd', + 'i', + 32, + 0, + /* 4724 */ 't', + 'd', + 'i', + 32, + 0, + /* 4729 */ 'w', + 'r', + 't', + 'e', + 'e', + 'i', + 32, + 0, + /* 4737 */ 'm', + 't', + 'f', + 's', + 'f', + 'i', + 32, + 0, + /* 4745 */ 'e', + 'v', + 's', + 'p', + 'l', + 'a', + 't', + 'f', + 'i', + 32, + 0, + /* 4756 */ 'e', + 'v', + 'm', + 'e', + 'r', + 'g', + 'e', + 'h', + 'i', + 32, + 0, + /* 4767 */ 'e', + 'v', + 'm', + 'e', + 'r', + 'g', + 'e', + 'l', + 'o', + 'h', + 'i', + 32, + 0, + /* 4780 */ 't', + 'l', + 'b', + 'l', + 'i', + 32, + 0, + /* 4787 */ 'm', + 'u', + 'l', + 'l', + 'i', + 32, + 0, + /* 4794 */ 'e', + 'x', + 't', + 's', + 'w', + 's', + 'l', + 'i', + 32, + 0, + /* 4804 */ 'v', + 'r', + 'l', + 'd', + 'm', + 'i', + 32, + 0, + /* 4812 */ 'r', + 'l', + 'd', + 'i', + 'm', + 'i', + 32, + 0, + /* 4820 */ 'r', + 'l', + 'w', + 'i', + 'm', + 'i', + 32, + 0, + /* 4828 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 'm', + 'i', + 32, + 0, + /* 4838 */ 'e', + 'v', + 'm', + 'w', + 'h', + 's', + 'm', + 'i', + 32, + 0, + /* 4848 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 'm', + 'i', + 32, + 0, + /* 4858 */ 'e', + 'v', + 'm', + 'w', + 's', + 'm', + 'i', + 32, + 0, + /* 4867 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'u', + 'm', + 'i', + 32, + 0, + /* 4877 */ 'e', + 'v', + 'm', + 'w', + 'h', + 'u', + 'm', + 'i', + 32, + 0, + /* 4887 */ 'e', + 'v', + 'm', + 'w', + 'l', + 'u', + 'm', + 'i', + 32, + 0, + /* 4897 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'u', + 'm', + 'i', + 32, + 0, + /* 4907 */ 'e', + 'v', + 'm', + 'w', + 'u', + 'm', + 'i', + 32, + 0, + /* 4916 */ 'v', + 'r', + 'l', + 'w', + 'm', + 'i', + 32, + 0, + /* 4924 */ 'q', + 'v', + 'a', + 'l', + 'i', + 'g', + 'n', + 'i', + 32, + 0, + /* 4934 */ 'm', + 'f', + 'f', + 's', + 'c', + 'r', + 'n', + 'i', + 32, + 0, + /* 4944 */ 'm', + 'f', + 'f', + 's', + 'c', + 'd', + 'r', + 'n', + 'i', + 32, + 0, + /* 4955 */ 'v', + 's', + 'l', + 'd', + 'o', + 'i', + 32, + 0, + /* 4963 */ 'x', + 's', + 'r', + 'd', + 'p', + 'i', + 32, + 0, + /* 4971 */ 'x', + 'v', + 'r', + 'd', + 'p', + 'i', + 32, + 0, + /* 4979 */ 'x', + 's', + 'r', + 'q', + 'p', + 'i', + 32, + 0, + /* 4987 */ 'x', + 'v', + 'r', + 's', + 'p', + 'i', + 32, + 0, + /* 4995 */ 'x', + 'o', + 'r', + 'i', + 32, + 0, + /* 5001 */ 'e', + 'f', + 'd', + 'c', + 'f', + 's', + 'i', + 32, + 0, + /* 5010 */ 'e', + 'f', + 's', + 'c', + 'f', + 's', + 'i', + 32, + 0, + /* 5019 */ 'e', + 'v', + 'f', + 's', + 'c', + 'f', + 's', + 'i', + 32, + 0, + /* 5029 */ 'e', + 'f', + 'd', + 'c', + 't', + 's', + 'i', + 32, + 0, + /* 5038 */ 'e', + 'f', + 's', + 'c', + 't', + 's', + 'i', + 32, + 0, + /* 5047 */ 'e', + 'v', + 'f', + 's', + 'c', + 't', + 's', + 'i', + 32, + 0, + /* 5057 */ 'q', + 'v', + 'e', + 's', + 'p', + 'l', + 'a', + 't', + 'i', + 32, + 0, + /* 5068 */ 'e', + 'v', + 's', + 'p', + 'l', + 'a', + 't', + 'i', + 32, + 0, + /* 5078 */ 'e', + 'f', + 'd', + 'c', + 'f', + 'u', + 'i', + 32, + 0, + /* 5087 */ 'e', + 'f', + 's', + 'c', + 'f', + 'u', + 'i', + 32, + 0, + /* 5096 */ 'e', + 'v', + 'f', + 's', + 'c', + 'f', + 'u', + 'i', + 32, + 0, + /* 5106 */ 'e', + 'f', + 'd', + 'c', + 't', + 'u', + 'i', + 32, + 0, + /* 5115 */ 'e', + 'f', + 's', + 'c', + 't', + 'u', + 'i', + 32, + 0, + /* 5124 */ 'e', + 'v', + 'f', + 's', + 'c', + 't', + 'u', + 'i', + 32, + 0, + /* 5134 */ 's', + 'r', + 'a', + 'w', + 'i', + 32, + 0, + /* 5141 */ 'x', + 'x', + 's', + 'l', + 'd', + 'w', + 'i', + 32, + 0, + /* 5150 */ 'c', + 'm', + 'p', + 'l', + 'w', + 'i', + 32, + 0, + /* 5158 */ 'e', + 'v', + 'r', + 'l', + 'w', + 'i', + 32, + 0, + /* 5166 */ 'c', + 'l', + 'r', + 'l', + 's', + 'l', + 'w', + 'i', + 32, + 0, + /* 5176 */ 'i', + 'n', + 's', + 'l', + 'w', + 'i', + 32, + 0, + /* 5184 */ 'e', + 'v', + 's', + 'l', + 'w', + 'i', + 32, + 0, + /* 5192 */ 'e', + 'x', + 't', + 'l', + 'w', + 'i', + 32, + 0, + /* 5200 */ 'c', + 'm', + 'p', + 'w', + 'i', + 32, + 0, + /* 5207 */ 'c', + 'l', + 'r', + 'r', + 'w', + 'i', + 32, + 0, + /* 5215 */ 'i', + 'n', + 's', + 'r', + 'w', + 'i', + 32, + 0, + /* 5223 */ 'r', + 'o', + 't', + 'r', + 'w', + 'i', + 32, + 0, + /* 5231 */ 'e', + 'x', + 't', + 'r', + 'w', + 'i', + 32, + 0, + /* 5239 */ 'l', + 's', + 'w', + 'i', + 32, + 0, + /* 5245 */ 's', + 't', + 's', + 'w', + 'i', + 32, + 0, + /* 5252 */ 't', + 'w', + 'i', + 32, + 0, + /* 5257 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 'd', + 'x', + 'i', + 32, + 0, + /* 5268 */ 'q', + 'v', + 's', + 't', + 'f', + 'd', + 'x', + 'i', + 32, + 0, + /* 5278 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 's', + 'x', + 'i', + 32, + 0, + /* 5289 */ 'q', + 'v', + 's', + 't', + 'f', + 's', + 'x', + 'i', + 32, + 0, + /* 5299 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 'd', + 'u', + 'x', + 'i', + 32, + 0, + /* 5311 */ 'q', + 'v', + 's', + 't', + 'f', + 'd', + 'u', + 'x', + 'i', + 32, + 0, + /* 5322 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 's', + 'u', + 'x', + 'i', + 32, + 0, + /* 5334 */ 'q', + 'v', + 's', + 't', + 'f', + 's', + 'u', + 'x', + 'i', + 32, + 0, + /* 5345 */ 't', + 'c', + 'h', + 'e', + 'c', + 'k', + 32, + 0, + /* 5353 */ 'q', + 'v', + 'f', + 'l', + 'o', + 'g', + 'i', + 'c', + 'a', + 'l', + 32, + 0, + /* 5365 */ 'b', + 'l', + 32, + 0, + /* 5369 */ 'b', + 'c', + 'l', + 32, + 0, + /* 5374 */ 'r', + 'l', + 'd', + 'c', + 'l', + 32, + 0, + /* 5381 */ 'r', + 'l', + 'd', + 'i', + 'c', + 'l', + 32, + 0, + /* 5389 */ 't', + 'l', + 'b', + 'i', + 'e', + 'l', + 32, + 0, + /* 5397 */ 'q', + 'v', + 'f', + 's', + 'e', + 'l', + 32, + 0, + /* 5405 */ 'i', + 's', + 'e', + 'l', + 32, + 0, + /* 5411 */ 'v', + 's', + 'e', + 'l', + 32, + 0, + /* 5417 */ 'x', + 'x', + 's', + 'e', + 'l', + 32, + 0, + /* 5424 */ 'd', + 'c', + 'b', + 'f', + 'l', + 32, + 0, + /* 5431 */ 'l', + 'x', + 'v', + 'l', + 'l', + 32, + 0, + /* 5438 */ 's', + 't', + 'x', + 'v', + 'l', + 'l', + 32, + 0, + /* 5446 */ 'b', + 'c', + 'l', + 'r', + 'l', + 32, + 0, + /* 5453 */ 'b', + 'c', + 'c', + 't', + 'r', + 'l', + 32, + 0, + /* 5461 */ 'm', + 'f', + 'f', + 's', + 'l', + 32, + 0, + /* 5468 */ 'l', + 'v', + 's', + 'l', + 32, + 0, + /* 5474 */ 'e', + 'f', + 'd', + 'm', + 'u', + 'l', + 32, + 0, + /* 5482 */ 'q', + 'v', + 'f', + 'm', + 'u', + 'l', + 32, + 0, + /* 5490 */ 'e', + 'f', + 's', + 'm', + 'u', + 'l', + 32, + 0, + /* 5498 */ 'e', + 'v', + 'f', + 's', + 'm', + 'u', + 'l', + 32, + 0, + /* 5507 */ 'q', + 'v', + 'f', + 'x', + 'm', + 'u', + 'l', + 32, + 0, + /* 5516 */ 'l', + 'x', + 'v', + 'l', + 32, + 0, + /* 5522 */ 's', + 't', + 'x', + 'v', + 'l', + 32, + 0, + /* 5529 */ 'l', + 'v', + 'x', + 'l', + 32, + 0, + /* 5535 */ 's', + 't', + 'v', + 'x', + 'l', + 32, + 0, + /* 5542 */ 'd', + 'c', + 'b', + 'z', + 'l', + 32, + 0, + /* 5549 */ 'b', + 'd', + 'z', + 'l', + 32, + 0, + /* 5555 */ 'b', + 'd', + 'n', + 'z', + 'l', + 32, + 0, + /* 5562 */ 'v', + 'm', + 's', + 'u', + 'm', + 'm', + 'b', + 'm', + 32, + 0, + /* 5572 */ 'v', + 's', + 'u', + 'b', + 'u', + 'b', + 'm', + 32, + 0, + /* 5581 */ 'v', + 'a', + 'd', + 'd', + 'u', + 'b', + 'm', + 32, + 0, + /* 5590 */ 'v', + 'm', + 's', + 'u', + 'm', + 'u', + 'b', + 'm', + 32, + 0, + /* 5600 */ 'v', + 's', + 'u', + 'b', + 'u', + 'd', + 'm', + 32, + 0, + /* 5609 */ 'v', + 'a', + 'd', + 'd', + 'u', + 'd', + 'm', + 32, + 0, + /* 5618 */ 'v', + 'm', + 's', + 'u', + 'm', + 's', + 'h', + 'm', + 32, + 0, + /* 5628 */ 'v', + 's', + 'u', + 'b', + 'u', + 'h', + 'm', + 32, + 0, + /* 5637 */ 'v', + 'm', + 'l', + 'a', + 'd', + 'd', + 'u', + 'h', + 'm', + 32, + 0, + /* 5648 */ 'v', + 'a', + 'd', + 'd', + 'u', + 'h', + 'm', + 32, + 0, + /* 5657 */ 'v', + 'm', + 's', + 'u', + 'm', + 'u', + 'h', + 'm', + 32, + 0, + /* 5667 */ 'v', + 'r', + 'f', + 'i', + 'm', + 32, + 0, + /* 5674 */ 'x', + 's', + 'r', + 'd', + 'p', + 'i', + 'm', + 32, + 0, + /* 5683 */ 'x', + 'v', + 'r', + 'd', + 'p', + 'i', + 'm', + 32, + 0, + /* 5692 */ 'x', + 'v', + 'r', + 's', + 'p', + 'i', + 'm', + 32, + 0, + /* 5701 */ 'q', + 'v', + 'f', + 'r', + 'i', + 'm', + 32, + 0, + /* 5709 */ 'v', + 'r', + 'l', + 'd', + 'n', + 'm', + 32, + 0, + /* 5717 */ 'r', + 'l', + 'w', + 'i', + 'n', + 'm', + 32, + 0, + /* 5725 */ 'v', + 'r', + 'l', + 'w', + 'n', + 'm', + 32, + 0, + /* 5733 */ 'v', + 's', + 'u', + 'b', + 'u', + 'q', + 'm', + 32, + 0, + /* 5742 */ 'v', + 'a', + 'd', + 'd', + 'u', + 'q', + 'm', + 32, + 0, + /* 5751 */ 'v', + 's', + 'u', + 'b', + 'e', + 'u', + 'q', + 'm', + 32, + 0, + /* 5761 */ 'v', + 'a', + 'd', + 'd', + 'e', + 'u', + 'q', + 'm', + 32, + 0, + /* 5771 */ 'q', + 'v', + 'f', + 'p', + 'e', + 'r', + 'm', + 32, + 0, + /* 5780 */ 'v', + 'p', + 'e', + 'r', + 'm', + 32, + 0, + /* 5787 */ 'x', + 'x', + 'p', + 'e', + 'r', + 'm', + 32, + 0, + /* 5795 */ 'v', + 'p', + 'k', + 'u', + 'd', + 'u', + 'm', + 32, + 0, + /* 5804 */ 'v', + 'p', + 'k', + 'u', + 'h', + 'u', + 'm', + 32, + 0, + /* 5813 */ 'v', + 'p', + 'k', + 'u', + 'w', + 'u', + 'm', + 32, + 0, + /* 5822 */ 'v', + 's', + 'u', + 'b', + 'u', + 'w', + 'm', + 32, + 0, + /* 5831 */ 'v', + 'a', + 'd', + 'd', + 'u', + 'w', + 'm', + 32, + 0, + /* 5840 */ 'v', + 'm', + 'u', + 'l', + 'u', + 'w', + 'm', + 32, + 0, + /* 5849 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'g', + 's', + 'm', + 'f', + 'a', + 'n', + 32, + 0, + /* 5862 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'g', + 's', + 'm', + 'f', + 'a', + 'n', + 32, + 0, + /* 5875 */ 'e', + 'v', + 'm', + 'w', + 's', + 'm', + 'f', + 'a', + 'n', + 32, + 0, + /* 5886 */ 'e', + 'v', + 'm', + 'w', + 's', + 's', + 'f', + 'a', + 'n', + 32, + 0, + /* 5897 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'g', + 's', + 'm', + 'i', + 'a', + 'n', + 32, + 0, + /* 5910 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'g', + 's', + 'm', + 'i', + 'a', + 'n', + 32, + 0, + /* 5923 */ 'e', + 'v', + 'm', + 'w', + 's', + 'm', + 'i', + 'a', + 'n', + 32, + 0, + /* 5934 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'g', + 'u', + 'm', + 'i', + 'a', + 'n', + 32, + 0, + /* 5947 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'g', + 'u', + 'm', + 'i', + 'a', + 'n', + 32, + 0, + /* 5960 */ 'e', + 'v', + 'm', + 'w', + 'u', + 'm', + 'i', + 'a', + 'n', + 32, + 0, + /* 5971 */ 'q', + 'v', + 'f', + 't', + 's', + 't', + 'n', + 'a', + 'n', + 32, + 0, + /* 5982 */ 'q', + 'v', + 'f', + 'c', + 'p', + 's', + 'g', + 'n', + 32, + 0, + /* 5992 */ 'v', + 'r', + 'f', + 'i', + 'n', + 32, + 0, + /* 5999 */ 'q', + 'v', + 'f', + 'r', + 'i', + 'n', + 32, + 0, + /* 6007 */ 'm', + 'f', + 's', + 'r', + 'i', + 'n', + 32, + 0, + /* 6015 */ 'm', + 't', + 's', + 'r', + 'i', + 'n', + 32, + 0, + /* 6023 */ 'x', + 's', + 'c', + 'v', + 's', + 'p', + 'd', + 'p', + 'n', + 32, + 0, + /* 6034 */ 'x', + 's', + 'c', + 'v', + 'd', + 'p', + 's', + 'p', + 'n', + 32, + 0, + /* 6045 */ 'd', + 'a', + 'r', + 'n', + 32, + 0, + /* 6051 */ 'm', + 'f', + 'f', + 's', + 'c', + 'r', + 'n', + 32, + 0, + /* 6060 */ 'm', + 'f', + 'f', + 's', + 'c', + 'd', + 'r', + 'n', + 32, + 0, + /* 6070 */ 'e', + 'v', + 's', + 't', + 'w', + 'h', + 'o', + 32, + 0, + /* 6079 */ 'e', + 'v', + 'm', + 'e', + 'r', + 'g', + 'e', + 'l', + 'o', + 32, + 0, + /* 6090 */ 'e', + 'v', + 'm', + 'e', + 'r', + 'g', + 'e', + 'h', + 'i', + 'l', + 'o', + 32, + 0, + /* 6103 */ 'v', + 's', + 'l', + 'o', + 32, + 0, + /* 6109 */ 'x', + 's', + 'c', + 'v', + 'q', + 'p', + 'd', + 'p', + 'o', + 32, + 0, + /* 6120 */ 'x', + 's', + 'n', + 'm', + 's', + 'u', + 'b', + 'q', + 'p', + 'o', + 32, + 0, + /* 6132 */ 'x', + 's', + 'm', + 's', + 'u', + 'b', + 'q', + 'p', + 'o', + 32, + 0, + /* 6143 */ 'x', + 's', + 's', + 'u', + 'b', + 'q', + 'p', + 'o', + 32, + 0, + /* 6153 */ 'x', + 's', + 'n', + 'm', + 'a', + 'd', + 'd', + 'q', + 'p', + 'o', + 32, + 0, + /* 6165 */ 'x', + 's', + 'm', + 'a', + 'd', + 'd', + 'q', + 'p', + 'o', + 32, + 0, + /* 6176 */ 'x', + 's', + 'a', + 'd', + 'd', + 'q', + 'p', + 'o', + 32, + 0, + /* 6186 */ 'x', + 's', + 'm', + 'u', + 'l', + 'q', + 'p', + 'o', + 32, + 0, + /* 6196 */ 'x', + 's', + 's', + 'q', + 'r', + 't', + 'q', + 'p', + 'o', + 32, + 0, + /* 6207 */ 'x', + 's', + 'd', + 'i', + 'v', + 'q', + 'p', + 'o', + 32, + 0, + /* 6217 */ 'v', + 's', + 'r', + 'o', + 32, + 0, + /* 6223 */ 'e', + 'v', + 's', + 't', + 'w', + 'w', + 'o', + 32, + 0, + /* 6232 */ 'x', + 's', + 'n', + 'm', + 's', + 'u', + 'b', + 'a', + 'd', + 'p', + 32, + 0, + /* 6244 */ 'x', + 'v', + 'n', + 'm', + 's', + 'u', + 'b', + 'a', + 'd', + 'p', + 32, + 0, + /* 6256 */ 'x', + 's', + 'm', + 's', + 'u', + 'b', + 'a', + 'd', + 'p', + 32, + 0, + /* 6267 */ 'x', + 'v', + 'm', + 's', + 'u', + 'b', + 'a', + 'd', + 'p', + 32, + 0, + /* 6278 */ 'x', + 's', + 'n', + 'm', + 'a', + 'd', + 'd', + 'a', + 'd', + 'p', + 32, + 0, + /* 6290 */ 'x', + 'v', + 'n', + 'm', + 'a', + 'd', + 'd', + 'a', + 'd', + 'p', + 32, + 0, + /* 6302 */ 'x', + 's', + 'm', + 'a', + 'd', + 'd', + 'a', + 'd', + 'p', + 32, + 0, + /* 6313 */ 'x', + 'v', + 'm', + 'a', + 'd', + 'd', + 'a', + 'd', + 'p', + 32, + 0, + /* 6324 */ 'x', + 's', + 's', + 'u', + 'b', + 'd', + 'p', + 32, + 0, + /* 6333 */ 'x', + 'v', + 's', + 'u', + 'b', + 'd', + 'p', + 32, + 0, + /* 6342 */ 'x', + 's', + 't', + 's', + 't', + 'd', + 'c', + 'd', + 'p', + 32, + 0, + /* 6353 */ 'x', + 'v', + 't', + 's', + 't', + 'd', + 'c', + 'd', + 'p', + 32, + 0, + /* 6364 */ 'x', + 's', + 'm', + 'i', + 'n', + 'c', + 'd', + 'p', + 32, + 0, + /* 6374 */ 'x', + 's', + 'm', + 'a', + 'x', + 'c', + 'd', + 'p', + 32, + 0, + /* 6384 */ 'x', + 's', + 'a', + 'd', + 'd', + 'd', + 'p', + 32, + 0, + /* 6393 */ 'x', + 'v', + 'a', + 'd', + 'd', + 'd', + 'p', + 32, + 0, + /* 6402 */ 'x', + 's', + 'c', + 'v', + 's', + 'x', + 'd', + 'd', + 'p', + 32, + 0, + /* 6413 */ 'x', + 'v', + 'c', + 'v', + 's', + 'x', + 'd', + 'd', + 'p', + 32, + 0, + /* 6424 */ 'x', + 's', + 'c', + 'v', + 'u', + 'x', + 'd', + 'd', + 'p', + 32, + 0, + /* 6435 */ 'x', + 'v', + 'c', + 'v', + 'u', + 'x', + 'd', + 'd', + 'p', + 32, + 0, + /* 6446 */ 'x', + 's', + 'c', + 'm', + 'p', + 'g', + 'e', + 'd', + 'p', + 32, + 0, + /* 6457 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'g', + 'e', + 'd', + 'p', + 32, + 0, + /* 6468 */ 'x', + 's', + 'r', + 'e', + 'd', + 'p', + 32, + 0, + /* 6476 */ 'x', + 'v', + 'r', + 'e', + 'd', + 'p', + 32, + 0, + /* 6484 */ 'x', + 's', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 'd', + 'p', + 32, + 0, + /* 6496 */ 'x', + 'v', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 'd', + 'p', + 32, + 0, + /* 6508 */ 'x', + 's', + 'n', + 'e', + 'g', + 'd', + 'p', + 32, + 0, + /* 6517 */ 'x', + 'v', + 'n', + 'e', + 'g', + 'd', + 'p', + 32, + 0, + /* 6526 */ 'x', + 's', + 'x', + 's', + 'i', + 'g', + 'd', + 'p', + 32, + 0, + /* 6536 */ 'x', + 'v', + 'x', + 's', + 'i', + 'g', + 'd', + 'p', + 32, + 0, + /* 6546 */ 'x', + 's', + 'm', + 'i', + 'n', + 'j', + 'd', + 'p', + 32, + 0, + /* 6556 */ 'x', + 's', + 'm', + 'a', + 'x', + 'j', + 'd', + 'p', + 32, + 0, + /* 6566 */ 'x', + 's', + 'm', + 'u', + 'l', + 'd', + 'p', + 32, + 0, + /* 6575 */ 'x', + 'v', + 'm', + 'u', + 'l', + 'd', + 'p', + 32, + 0, + /* 6584 */ 'x', + 's', + 'n', + 'm', + 's', + 'u', + 'b', + 'm', + 'd', + 'p', + 32, + 0, + /* 6596 */ 'x', + 'v', + 'n', + 'm', + 's', + 'u', + 'b', + 'm', + 'd', + 'p', + 32, + 0, + /* 6608 */ 'x', + 's', + 'm', + 's', + 'u', + 'b', + 'm', + 'd', + 'p', + 32, + 0, + /* 6619 */ 'x', + 'v', + 'm', + 's', + 'u', + 'b', + 'm', + 'd', + 'p', + 32, + 0, + /* 6630 */ 'x', + 's', + 'n', + 'm', + 'a', + 'd', + 'd', + 'm', + 'd', + 'p', + 32, + 0, + /* 6642 */ 'x', + 'v', + 'n', + 'm', + 'a', + 'd', + 'd', + 'm', + 'd', + 'p', + 32, + 0, + /* 6654 */ 'x', + 's', + 'm', + 'a', + 'd', + 'd', + 'm', + 'd', + 'p', + 32, + 0, + /* 6665 */ 'x', + 'v', + 'm', + 'a', + 'd', + 'd', + 'm', + 'd', + 'p', + 32, + 0, + /* 6676 */ 'x', + 's', + 'c', + 'p', + 's', + 'g', + 'n', + 'd', + 'p', + 32, + 0, + /* 6687 */ 'x', + 'v', + 'c', + 'p', + 's', + 'g', + 'n', + 'd', + 'p', + 32, + 0, + /* 6698 */ 'x', + 's', + 'm', + 'i', + 'n', + 'd', + 'p', + 32, + 0, + /* 6707 */ 'x', + 'v', + 'm', + 'i', + 'n', + 'd', + 'p', + 32, + 0, + /* 6716 */ 'x', + 's', + 'c', + 'm', + 'p', + 'o', + 'd', + 'p', + 32, + 0, + /* 6726 */ 'x', + 's', + 'c', + 'v', + 'h', + 'p', + 'd', + 'p', + 32, + 0, + /* 6736 */ 'x', + 's', + 'c', + 'v', + 'q', + 'p', + 'd', + 'p', + 32, + 0, + /* 6746 */ 'x', + 's', + 'c', + 'v', + 's', + 'p', + 'd', + 'p', + 32, + 0, + /* 6756 */ 'x', + 'v', + 'c', + 'v', + 's', + 'p', + 'd', + 'p', + 32, + 0, + /* 6766 */ 'x', + 's', + 'i', + 'e', + 'x', + 'p', + 'd', + 'p', + 32, + 0, + /* 6776 */ 'x', + 'v', + 'i', + 'e', + 'x', + 'p', + 'd', + 'p', + 32, + 0, + /* 6786 */ 'x', + 's', + 'c', + 'm', + 'p', + 'e', + 'x', + 'p', + 'd', + 'p', + 32, + 0, + /* 6798 */ 'x', + 's', + 'x', + 'e', + 'x', + 'p', + 'd', + 'p', + 32, + 0, + /* 6808 */ 'x', + 'v', + 'x', + 'e', + 'x', + 'p', + 'd', + 'p', + 32, + 0, + /* 6818 */ 'x', + 's', + 'c', + 'm', + 'p', + 'e', + 'q', + 'd', + 'p', + 32, + 0, + /* 6829 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'd', + 'p', + 32, + 0, + /* 6840 */ 'x', + 's', + 'n', + 'a', + 'b', + 's', + 'd', + 'p', + 32, + 0, + /* 6850 */ 'x', + 'v', + 'n', + 'a', + 'b', + 's', + 'd', + 'p', + 32, + 0, + /* 6860 */ 'x', + 's', + 'a', + 'b', + 's', + 'd', + 'p', + 32, + 0, + /* 6869 */ 'x', + 'v', + 'a', + 'b', + 's', + 'd', + 'p', + 32, + 0, + /* 6878 */ 'x', + 's', + 'c', + 'm', + 'p', + 'g', + 't', + 'd', + 'p', + 32, + 0, + /* 6889 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'd', + 'p', + 32, + 0, + /* 6900 */ 'x', + 's', + 's', + 'q', + 'r', + 't', + 'd', + 'p', + 32, + 0, + /* 6910 */ 'x', + 's', + 't', + 's', + 'q', + 'r', + 't', + 'd', + 'p', + 32, + 0, + /* 6921 */ 'x', + 'v', + 't', + 's', + 'q', + 'r', + 't', + 'd', + 'p', + 32, + 0, + /* 6932 */ 'x', + 'v', + 's', + 'q', + 'r', + 't', + 'd', + 'p', + 32, + 0, + /* 6942 */ 'x', + 's', + 'c', + 'm', + 'p', + 'u', + 'd', + 'p', + 32, + 0, + /* 6952 */ 'x', + 's', + 'd', + 'i', + 'v', + 'd', + 'p', + 32, + 0, + /* 6961 */ 'x', + 's', + 't', + 'd', + 'i', + 'v', + 'd', + 'p', + 32, + 0, + /* 6971 */ 'x', + 'v', + 't', + 'd', + 'i', + 'v', + 'd', + 'p', + 32, + 0, + /* 6981 */ 'x', + 'v', + 'd', + 'i', + 'v', + 'd', + 'p', + 32, + 0, + /* 6990 */ 'x', + 'v', + 'c', + 'v', + 's', + 'x', + 'w', + 'd', + 'p', + 32, + 0, + /* 7001 */ 'x', + 'v', + 'c', + 'v', + 'u', + 'x', + 'w', + 'd', + 'p', + 32, + 0, + /* 7012 */ 'x', + 's', + 'm', + 'a', + 'x', + 'd', + 'p', + 32, + 0, + /* 7021 */ 'x', + 'v', + 'm', + 'a', + 'x', + 'd', + 'p', + 32, + 0, + /* 7030 */ 'd', + 'c', + 'b', + 'f', + 'e', + 'p', + 32, + 0, + /* 7038 */ 'i', + 'c', + 'b', + 'i', + 'e', + 'p', + 32, + 0, + /* 7046 */ 'd', + 'c', + 'b', + 'z', + 'l', + 'e', + 'p', + 32, + 0, + /* 7055 */ 'd', + 'c', + 'b', + 't', + 'e', + 'p', + 32, + 0, + /* 7063 */ 'd', + 'c', + 'b', + 's', + 't', + 'e', + 'p', + 32, + 0, + /* 7072 */ 'd', + 'c', + 'b', + 't', + 's', + 't', + 'e', + 'p', + 32, + 0, + /* 7082 */ 'd', + 'c', + 'b', + 'z', + 'e', + 'p', + 32, + 0, + /* 7090 */ 'v', + 'c', + 'm', + 'p', + 'b', + 'f', + 'p', + 32, + 0, + /* 7099 */ 'v', + 'n', + 'm', + 's', + 'u', + 'b', + 'f', + 'p', + 32, + 0, + /* 7109 */ 'v', + 's', + 'u', + 'b', + 'f', + 'p', + 32, + 0, + /* 7117 */ 'v', + 'm', + 'a', + 'd', + 'd', + 'f', + 'p', + 32, + 0, + /* 7126 */ 'v', + 'a', + 'd', + 'd', + 'f', + 'p', + 32, + 0, + /* 7134 */ 'v', + 'l', + 'o', + 'g', + 'e', + 'f', + 'p', + 32, + 0, + /* 7143 */ 'v', + 'c', + 'm', + 'p', + 'g', + 'e', + 'f', + 'p', + 32, + 0, + /* 7153 */ 'v', + 'r', + 'e', + 'f', + 'p', + 32, + 0, + /* 7160 */ 'v', + 'e', + 'x', + 'p', + 't', + 'e', + 'f', + 'p', + 32, + 0, + /* 7170 */ 'v', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 'f', + 'p', + 32, + 0, + /* 7181 */ 'v', + 'm', + 'i', + 'n', + 'f', + 'p', + 32, + 0, + /* 7189 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'f', + 'p', + 32, + 0, + /* 7199 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'f', + 'p', + 32, + 0, + /* 7209 */ 'v', + 'm', + 'a', + 'x', + 'f', + 'p', + 32, + 0, + /* 7217 */ 'x', + 's', + 'c', + 'v', + 'd', + 'p', + 'h', + 'p', + 32, + 0, + /* 7227 */ 'x', + 'v', + 'c', + 'v', + 's', + 'p', + 'h', + 'p', + 32, + 0, + /* 7237 */ 'v', + 'r', + 'f', + 'i', + 'p', + 32, + 0, + /* 7244 */ 'x', + 's', + 'r', + 'd', + 'p', + 'i', + 'p', + 32, + 0, + /* 7253 */ 'x', + 'v', + 'r', + 'd', + 'p', + 'i', + 'p', + 32, + 0, + /* 7262 */ 'x', + 'v', + 'r', + 's', + 'p', + 'i', + 'p', + 32, + 0, + /* 7271 */ 'q', + 'v', + 'f', + 'r', + 'i', + 'p', + 32, + 0, + /* 7279 */ 'd', + 'c', + 'b', + 'f', + 'l', + 'p', + 32, + 0, + /* 7287 */ 'x', + 's', + 'n', + 'm', + 's', + 'u', + 'b', + 'q', + 'p', + 32, + 0, + /* 7298 */ 'x', + 's', + 'm', + 's', + 'u', + 'b', + 'q', + 'p', + 32, + 0, + /* 7308 */ 'x', + 's', + 's', + 'u', + 'b', + 'q', + 'p', + 32, + 0, + /* 7317 */ 'x', + 's', + 't', + 's', + 't', + 'd', + 'c', + 'q', + 'p', + 32, + 0, + /* 7328 */ 'x', + 's', + 'n', + 'm', + 'a', + 'd', + 'd', + 'q', + 'p', + 32, + 0, + /* 7339 */ 'x', + 's', + 'm', + 'a', + 'd', + 'd', + 'q', + 'p', + 32, + 0, + /* 7349 */ 'x', + 's', + 'a', + 'd', + 'd', + 'q', + 'p', + 32, + 0, + /* 7358 */ 'x', + 's', + 'c', + 'v', + 's', + 'd', + 'q', + 'p', + 32, + 0, + /* 7368 */ 'x', + 's', + 'c', + 'v', + 'u', + 'd', + 'q', + 'p', + 32, + 0, + /* 7378 */ 'x', + 's', + 'n', + 'e', + 'g', + 'q', + 'p', + 32, + 0, + /* 7387 */ 'x', + 's', + 'x', + 's', + 'i', + 'g', + 'q', + 'p', + 32, + 0, + /* 7397 */ 'x', + 's', + 'm', + 'u', + 'l', + 'q', + 'p', + 32, + 0, + /* 7406 */ 'x', + 's', + 'c', + 'p', + 's', + 'g', + 'n', + 'q', + 'p', + 32, + 0, + /* 7417 */ 'x', + 's', + 'c', + 'm', + 'p', + 'o', + 'q', + 'p', + 32, + 0, + /* 7427 */ 'x', + 's', + 'c', + 'v', + 'd', + 'p', + 'q', + 'p', + 32, + 0, + /* 7437 */ 'x', + 's', + 'i', + 'e', + 'x', + 'p', + 'q', + 'p', + 32, + 0, + /* 7447 */ 'x', + 's', + 'c', + 'm', + 'p', + 'e', + 'x', + 'p', + 'q', + 'p', + 32, + 0, + /* 7459 */ 'x', + 's', + 'x', + 'e', + 'x', + 'p', + 'q', + 'p', + 32, + 0, + /* 7469 */ 'x', + 's', + 'n', + 'a', + 'b', + 's', + 'q', + 'p', + 32, + 0, + /* 7479 */ 'x', + 's', + 'a', + 'b', + 's', + 'q', + 'p', + 32, + 0, + /* 7488 */ 'x', + 's', + 's', + 'q', + 'r', + 't', + 'q', + 'p', + 32, + 0, + /* 7498 */ 'x', + 's', + 'c', + 'm', + 'p', + 'u', + 'q', + 'p', + 32, + 0, + /* 7508 */ 'x', + 's', + 'd', + 'i', + 'v', + 'q', + 'p', + 32, + 0, + /* 7517 */ 'x', + 's', + 'n', + 'm', + 's', + 'u', + 'b', + 'a', + 's', + 'p', + 32, + 0, + /* 7529 */ 'x', + 'v', + 'n', + 'm', + 's', + 'u', + 'b', + 'a', + 's', + 'p', + 32, + 0, + /* 7541 */ 'x', + 's', + 'm', + 's', + 'u', + 'b', + 'a', + 's', + 'p', + 32, + 0, + /* 7552 */ 'x', + 'v', + 'm', + 's', + 'u', + 'b', + 'a', + 's', + 'p', + 32, + 0, + /* 7563 */ 'x', + 's', + 'n', + 'm', + 'a', + 'd', + 'd', + 'a', + 's', + 'p', + 32, + 0, + /* 7575 */ 'x', + 'v', + 'n', + 'm', + 'a', + 'd', + 'd', + 'a', + 's', + 'p', + 32, + 0, + /* 7587 */ 'x', + 's', + 'm', + 'a', + 'd', + 'd', + 'a', + 's', + 'p', + 32, + 0, + /* 7598 */ 'x', + 'v', + 'm', + 'a', + 'd', + 'd', + 'a', + 's', + 'p', + 32, + 0, + /* 7609 */ 'x', + 's', + 's', + 'u', + 'b', + 's', + 'p', + 32, + 0, + /* 7618 */ 'x', + 'v', + 's', + 'u', + 'b', + 's', + 'p', + 32, + 0, + /* 7627 */ 'x', + 's', + 't', + 's', + 't', + 'd', + 'c', + 's', + 'p', + 32, + 0, + /* 7638 */ 'x', + 'v', + 't', + 's', + 't', + 'd', + 'c', + 's', + 'p', + 32, + 0, + /* 7649 */ 'x', + 's', + 'a', + 'd', + 'd', + 's', + 'p', + 32, + 0, + /* 7658 */ 'x', + 'v', + 'a', + 'd', + 'd', + 's', + 'p', + 32, + 0, + /* 7667 */ 'x', + 's', + 'c', + 'v', + 's', + 'x', + 'd', + 's', + 'p', + 32, + 0, + /* 7678 */ 'x', + 'v', + 'c', + 'v', + 's', + 'x', + 'd', + 's', + 'p', + 32, + 0, + /* 7689 */ 'x', + 's', + 'c', + 'v', + 'u', + 'x', + 'd', + 's', + 'p', + 32, + 0, + /* 7700 */ 'x', + 'v', + 'c', + 'v', + 'u', + 'x', + 'd', + 's', + 'p', + 32, + 0, + /* 7711 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'g', + 'e', + 's', + 'p', + 32, + 0, + /* 7722 */ 'x', + 's', + 'r', + 'e', + 's', + 'p', + 32, + 0, + /* 7730 */ 'x', + 'v', + 'r', + 'e', + 's', + 'p', + 32, + 0, + /* 7738 */ 'x', + 's', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 's', + 'p', + 32, + 0, + /* 7750 */ 'x', + 'v', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 's', + 'p', + 32, + 0, + /* 7762 */ 'x', + 'v', + 'n', + 'e', + 'g', + 's', + 'p', + 32, + 0, + /* 7771 */ 'x', + 'v', + 'x', + 's', + 'i', + 'g', + 's', + 'p', + 32, + 0, + /* 7781 */ 'x', + 's', + 'm', + 'u', + 'l', + 's', + 'p', + 32, + 0, + /* 7790 */ 'x', + 'v', + 'm', + 'u', + 'l', + 's', + 'p', + 32, + 0, + /* 7799 */ 'x', + 's', + 'n', + 'm', + 's', + 'u', + 'b', + 'm', + 's', + 'p', + 32, + 0, + /* 7811 */ 'x', + 'v', + 'n', + 'm', + 's', + 'u', + 'b', + 'm', + 's', + 'p', + 32, + 0, + /* 7823 */ 'x', + 's', + 'm', + 's', + 'u', + 'b', + 'm', + 's', + 'p', + 32, + 0, + /* 7834 */ 'x', + 'v', + 'm', + 's', + 'u', + 'b', + 'm', + 's', + 'p', + 32, + 0, + /* 7845 */ 'x', + 's', + 'n', + 'm', + 'a', + 'd', + 'd', + 'm', + 's', + 'p', + 32, + 0, + /* 7857 */ 'x', + 'v', + 'n', + 'm', + 'a', + 'd', + 'd', + 'm', + 's', + 'p', + 32, + 0, + /* 7869 */ 'x', + 's', + 'm', + 'a', + 'd', + 'd', + 'm', + 's', + 'p', + 32, + 0, + /* 7880 */ 'x', + 'v', + 'm', + 'a', + 'd', + 'd', + 'm', + 's', + 'p', + 32, + 0, + /* 7891 */ 'x', + 'v', + 'c', + 'p', + 's', + 'g', + 'n', + 's', + 'p', + 32, + 0, + /* 7902 */ 'x', + 'v', + 'm', + 'i', + 'n', + 's', + 'p', + 32, + 0, + /* 7911 */ 'x', + 's', + 'c', + 'v', + 'd', + 'p', + 's', + 'p', + 32, + 0, + /* 7921 */ 'x', + 'v', + 'c', + 'v', + 'd', + 'p', + 's', + 'p', + 32, + 0, + /* 7931 */ 'x', + 'v', + 'c', + 'v', + 'h', + 'p', + 's', + 'p', + 32, + 0, + /* 7941 */ 'x', + 'v', + 'i', + 'e', + 'x', + 'p', + 's', + 'p', + 32, + 0, + /* 7951 */ 'x', + 'v', + 'x', + 'e', + 'x', + 'p', + 's', + 'p', + 32, + 0, + /* 7961 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 's', + 'p', + 32, + 0, + /* 7972 */ 'q', + 'v', + 'f', + 'r', + 's', + 'p', + 32, + 0, + /* 7980 */ 'x', + 's', + 'r', + 's', + 'p', + 32, + 0, + /* 7987 */ 'x', + 'v', + 'n', + 'a', + 'b', + 's', + 's', + 'p', + 32, + 0, + /* 7997 */ 'x', + 'v', + 'a', + 'b', + 's', + 's', + 'p', + 32, + 0, + /* 8006 */ 'l', + 'x', + 's', + 's', + 'p', + 32, + 0, + /* 8013 */ 's', + 't', + 'x', + 's', + 's', + 'p', + 32, + 0, + /* 8021 */ 'x', + 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'p', + 32, + 0, + /* 8032 */ 'x', + 's', + 's', + 'q', + 'r', + 't', + 's', + 'p', + 32, + 0, + /* 8042 */ 'x', + 'v', + 't', + 's', + 'q', + 'r', + 't', + 's', + 'p', + 32, + 0, + /* 8053 */ 'x', + 'v', + 's', + 'q', + 'r', + 't', + 's', + 'p', + 32, + 0, + /* 8063 */ 'x', + 's', + 'd', + 'i', + 'v', + 's', + 'p', + 32, + 0, + /* 8072 */ 'x', + 'v', + 't', + 'd', + 'i', + 'v', + 's', + 'p', + 32, + 0, + /* 8082 */ 'x', + 'v', + 'd', + 'i', + 'v', + 's', + 'p', + 32, + 0, + /* 8091 */ 'x', + 'v', + 'c', + 'v', + 's', + 'x', + 'w', + 's', + 'p', + 32, + 0, + /* 8102 */ 'x', + 'v', + 'c', + 'v', + 'u', + 'x', + 'w', + 's', + 'p', + 32, + 0, + /* 8113 */ 'x', + 'v', + 'm', + 'a', + 'x', + 's', + 'p', + 32, + 0, + /* 8122 */ 'x', + 's', + 'r', + 'q', + 'p', + 'x', + 'p', + 32, + 0, + /* 8131 */ 'v', + 'p', + 'r', + 't', + 'y', + 'b', + 'q', + 32, + 0, + /* 8140 */ 'e', + 'f', + 'd', + 'c', + 'm', + 'p', + 'e', + 'q', + 32, + 0, + /* 8150 */ 'q', + 'v', + 'f', + 'c', + 'm', + 'p', + 'e', + 'q', + 32, + 0, + /* 8160 */ 'e', + 'f', + 's', + 'c', + 'm', + 'p', + 'e', + 'q', + 32, + 0, + /* 8170 */ 'e', + 'v', + 'f', + 's', + 'c', + 'm', + 'p', + 'e', + 'q', + 32, + 0, + /* 8181 */ 'e', + 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 32, + 0, + /* 8190 */ 'e', + 'f', + 'd', + 't', + 's', + 't', + 'e', + 'q', + 32, + 0, + /* 8200 */ 'e', + 'f', + 's', + 't', + 's', + 't', + 'e', + 'q', + 32, + 0, + /* 8210 */ 'e', + 'v', + 'f', + 's', + 't', + 's', + 't', + 'e', + 'q', + 32, + 0, + /* 8221 */ 'v', + 'b', + 'p', + 'e', + 'r', + 'm', + 'q', + 32, + 0, + /* 8230 */ 'x', + 'x', + 'b', + 'r', + 'q', + 32, + 0, + /* 8237 */ 'v', + 'm', + 'u', + 'l', + '1', + '0', + 'u', + 'q', + 32, + 0, + /* 8247 */ 'v', + 'm', + 'u', + 'l', + '1', + '0', + 'c', + 'u', + 'q', + 32, + 0, + /* 8258 */ 'v', + 's', + 'u', + 'b', + 'c', + 'u', + 'q', + 32, + 0, + /* 8267 */ 'v', + 'a', + 'd', + 'd', + 'c', + 'u', + 'q', + 32, + 0, + /* 8276 */ 'v', + 'm', + 'u', + 'l', + '1', + '0', + 'e', + 'c', + 'u', + 'q', + 32, + 0, + /* 8288 */ 'v', + 's', + 'u', + 'b', + 'e', + 'c', + 'u', + 'q', + 32, + 0, + /* 8298 */ 'v', + 'a', + 'd', + 'd', + 'e', + 'c', + 'u', + 'q', + 32, + 0, + /* 8308 */ 'v', + 'm', + 'u', + 'l', + '1', + '0', + 'e', + 'u', + 'q', + 32, + 0, + /* 8319 */ '#', + 'T', + 'C', + '_', + 'R', + 'E', + 'T', + 'U', + 'R', + 'N', + 'r', + 32, + 0, + /* 8332 */ 'm', + 'b', + 'a', + 'r', + 32, + 0, + /* 8338 */ 'm', + 'f', + 'd', + 'c', + 'r', + 32, + 0, + /* 8345 */ 'r', + 'l', + 'd', + 'c', + 'r', + 32, + 0, + /* 8352 */ 'm', + 't', + 'd', + 'c', + 'r', + 32, + 0, + /* 8359 */ 'm', + 'f', + 'c', + 'r', + 32, + 0, + /* 8365 */ 'r', + 'l', + 'd', + 'i', + 'c', + 'r', + 32, + 0, + /* 8373 */ 'm', + 'f', + 'v', + 's', + 'c', + 'r', + 32, + 0, + /* 8381 */ 'm', + 't', + 'v', + 's', + 'c', + 'r', + 32, + 0, + /* 8389 */ 'v', + 'n', + 'c', + 'i', + 'p', + 'h', + 'e', + 'r', + 32, + 0, + /* 8399 */ 'v', + 'c', + 'i', + 'p', + 'h', + 'e', + 'r', + 32, + 0, + /* 8408 */ 'b', + 'c', + 'l', + 'r', + 32, + 0, + /* 8414 */ 'm', + 'f', + 'l', + 'r', + 32, + 0, + /* 8420 */ 'm', + 't', + 'l', + 'r', + 32, + 0, + /* 8426 */ 'q', + 'v', + 'f', + 'm', + 'r', + 32, + 0, + /* 8433 */ 'm', + 'f', + 'p', + 'm', + 'r', + 32, + 0, + /* 8440 */ 'm', + 't', + 'p', + 'm', + 'r', + 32, + 0, + /* 8447 */ 'v', + 'p', + 'e', + 'r', + 'm', + 'r', + 32, + 0, + /* 8455 */ 'x', + 'x', + 'p', + 'e', + 'r', + 'm', + 'r', + 32, + 0, + /* 8464 */ 'x', + 'x', + 'l', + 'o', + 'r', + 32, + 0, + /* 8471 */ 'x', + 'x', + 'l', + 'n', + 'o', + 'r', + 32, + 0, + /* 8479 */ 'c', + 'r', + 'n', + 'o', + 'r', + 32, + 0, + /* 8486 */ 'e', + 'v', + 'n', + 'o', + 'r', + 32, + 0, + /* 8493 */ 'c', + 'r', + 'o', + 'r', + 32, + 0, + /* 8499 */ 'e', + 'v', + 'o', + 'r', + 32, + 0, + /* 8505 */ 'x', + 'x', + 'l', + 'x', + 'o', + 'r', + 32, + 0, + /* 8513 */ 'v', + 'p', + 'e', + 'r', + 'm', + 'x', + 'o', + 'r', + 32, + 0, + /* 8523 */ 'c', + 'r', + 'x', + 'o', + 'r', + 32, + 0, + /* 8530 */ 'e', + 'v', + 'x', + 'o', + 'r', + 32, + 0, + /* 8537 */ 'm', + 'f', + 's', + 'p', + 'r', + 32, + 0, + /* 8544 */ 'm', + 't', + 's', + 'p', + 'r', + 32, + 0, + /* 8551 */ 'm', + 'f', + 's', + 'r', + 32, + 0, + /* 8557 */ 'm', + 'f', + 'm', + 's', + 'r', + 32, + 0, + /* 8564 */ 'm', + 't', + 'm', + 's', + 'r', + 32, + 0, + /* 8571 */ 'm', + 't', + 's', + 'r', + 32, + 0, + /* 8577 */ 'l', + 'v', + 's', + 'r', + 32, + 0, + /* 8583 */ 'b', + 'c', + 'c', + 't', + 'r', + 32, + 0, + /* 8590 */ 'm', + 'f', + 'c', + 't', + 'r', + 32, + 0, + /* 8597 */ 'm', + 't', + 'c', + 't', + 'r', + 32, + 0, + /* 8604 */ 'e', + 'f', + 'd', + 'a', + 'b', + 's', + 32, + 0, + /* 8612 */ 'q', + 'v', + 'f', + 'a', + 'b', + 's', + 32, + 0, + /* 8620 */ 'e', + 'f', + 'd', + 'n', + 'a', + 'b', + 's', + 32, + 0, + /* 8629 */ 'q', + 'v', + 'f', + 'n', + 'a', + 'b', + 's', + 32, + 0, + /* 8638 */ 'e', + 'f', + 's', + 'n', + 'a', + 'b', + 's', + 32, + 0, + /* 8647 */ 'e', + 'v', + 'f', + 's', + 'n', + 'a', + 'b', + 's', + 32, + 0, + /* 8657 */ 'e', + 'f', + 's', + 'a', + 'b', + 's', + 32, + 0, + /* 8665 */ 'e', + 'v', + 'f', + 's', + 'a', + 'b', + 's', + 32, + 0, + /* 8674 */ 'e', + 'v', + 'a', + 'b', + 's', + 32, + 0, + /* 8681 */ 'v', + 's', + 'u', + 'm', + '4', + 's', + 'b', + 's', + 32, + 0, + /* 8691 */ 'v', + 's', + 'u', + 'b', + 's', + 'b', + 's', + 32, + 0, + /* 8700 */ 'v', + 'a', + 'd', + 'd', + 's', + 'b', + 's', + 32, + 0, + /* 8709 */ 'v', + 's', + 'u', + 'm', + '4', + 'u', + 'b', + 's', + 32, + 0, + /* 8719 */ 'v', + 's', + 'u', + 'b', + 'u', + 'b', + 's', + 32, + 0, + /* 8728 */ 'v', + 'a', + 'd', + 'd', + 'u', + 'b', + 's', + 32, + 0, + /* 8737 */ 'q', + 'v', + 'f', + 's', + 'u', + 'b', + 's', + 32, + 0, + /* 8746 */ 'q', + 'v', + 'f', + 'm', + 's', + 'u', + 'b', + 's', + 32, + 0, + /* 8756 */ 'q', + 'v', + 'f', + 'n', + 'm', + 's', + 'u', + 'b', + 's', + 32, + 0, + /* 8767 */ 'q', + 'v', + 'f', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 8776 */ 'q', + 'v', + 'f', + 'm', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 8786 */ 'q', + 'v', + 'f', + 'n', + 'm', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 8797 */ 'q', + 'v', + 'f', + 'x', + 'x', + 'c', + 'p', + 'n', + 'm', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 8812 */ 'q', + 'v', + 'f', + 'x', + 'x', + 'n', + 'p', + 'm', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 8826 */ 'q', + 'v', + 'f', + 'x', + 'm', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 8837 */ 'q', + 'v', + 'f', + 'x', + 'x', + 'm', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 8849 */ 'q', + 'v', + 'f', + 'c', + 'f', + 'i', + 'd', + 's', + 32, + 0, + /* 8859 */ 'd', + 'c', + 'b', + 't', + 'd', + 's', + 32, + 0, + /* 8867 */ 'd', + 'c', + 'b', + 't', + 's', + 't', + 'd', + 's', + 32, + 0, + /* 8877 */ 'x', + 's', + 'c', + 'v', + 'd', + 'p', + 's', + 'x', + 'd', + 's', + 32, + 0, + /* 8889 */ 'x', + 'v', + 'c', + 'v', + 'd', + 'p', + 's', + 'x', + 'd', + 's', + 32, + 0, + /* 8901 */ 'x', + 'v', + 'c', + 'v', + 's', + 'p', + 's', + 'x', + 'd', + 's', + 32, + 0, + /* 8913 */ 'x', + 's', + 'c', + 'v', + 'd', + 'p', + 'u', + 'x', + 'd', + 's', + 32, + 0, + /* 8925 */ 'x', + 'v', + 'c', + 'v', + 'd', + 'p', + 'u', + 'x', + 'd', + 's', + 32, + 0, + /* 8937 */ 'x', + 'v', + 'c', + 'v', + 's', + 'p', + 'u', + 'x', + 'd', + 's', + 32, + 0, + /* 8949 */ 'q', + 'v', + 'f', + 'r', + 'e', + 's', + 32, + 0, + /* 8957 */ 'q', + 'v', + 'f', + 'r', + 's', + 'q', + 'r', + 't', + 'e', + 's', + 32, + 0, + /* 8969 */ 'e', + 'f', + 'd', + 'c', + 'f', + 's', + 32, + 0, + /* 8977 */ 'm', + 'f', + 'f', + 's', + 32, + 0, + /* 8983 */ 'l', + 'f', + 's', + 32, + 0, + /* 8988 */ 'm', + 'c', + 'r', + 'f', + 's', + 32, + 0, + /* 8995 */ 's', + 't', + 'f', + 's', + 32, + 0, + /* 9001 */ 'v', + 's', + 'u', + 'm', + '4', + 's', + 'h', + 's', + 32, + 0, + /* 9011 */ 'v', + 's', + 'u', + 'b', + 's', + 'h', + 's', + 32, + 0, + /* 9020 */ 'v', + 'm', + 'h', + 'a', + 'd', + 'd', + 's', + 'h', + 's', + 32, + 0, + /* 9031 */ 'v', + 'm', + 'h', + 'r', + 'a', + 'd', + 'd', + 's', + 'h', + 's', + 32, + 0, + /* 9043 */ 'v', + 'a', + 'd', + 'd', + 's', + 'h', + 's', + 32, + 0, + /* 9052 */ 'v', + 'm', + 's', + 'u', + 'm', + 's', + 'h', + 's', + 32, + 0, + /* 9062 */ 'v', + 's', + 'u', + 'b', + 'u', + 'h', + 's', + 32, + 0, + /* 9071 */ 'v', + 'a', + 'd', + 'd', + 'u', + 'h', + 's', + 32, + 0, + /* 9080 */ 'v', + 'm', + 's', + 'u', + 'm', + 'u', + 'h', + 's', + 32, + 0, + /* 9090 */ 's', + 'u', + 'b', + 'i', + 's', + 32, + 0, + /* 9097 */ 's', + 'u', + 'b', + 'p', + 'c', + 'i', + 's', + 32, + 0, + /* 9106 */ 'a', + 'd', + 'd', + 'p', + 'c', + 'i', + 's', + 32, + 0, + /* 9115 */ 'a', + 'd', + 'd', + 'i', + 's', + 32, + 0, + /* 9122 */ 'l', + 'i', + 's', + 32, + 0, + /* 9127 */ 'x', + 'o', + 'r', + 'i', + 's', + 32, + 0, + /* 9134 */ 'e', + 'v', + 's', + 'r', + 'w', + 'i', + 's', + 32, + 0, + /* 9143 */ 'i', + 'c', + 'b', + 't', + 'l', + 's', + 32, + 0, + /* 9151 */ 'q', + 'v', + 'f', + 'm', + 'u', + 'l', + 's', + 32, + 0, + /* 9160 */ 'q', + 'v', + 'f', + 'x', + 'm', + 'u', + 'l', + 's', + 32, + 0, + /* 9170 */ 'e', + 'v', + 'l', + 'w', + 'h', + 'o', + 's', + 32, + 0, + /* 9179 */ 'v', + 'p', + 'k', + 's', + 'd', + 's', + 's', + 32, + 0, + /* 9188 */ 'v', + 'p', + 'k', + 's', + 'h', + 's', + 's', + 32, + 0, + /* 9197 */ 'v', + 'p', + 'k', + 's', + 'w', + 's', + 's', + 32, + 0, + /* 9206 */ 'e', + 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 32, + 0, + /* 9216 */ 'e', + 'v', + 'c', + 'm', + 'p', + 'l', + 't', + 's', + 32, + 0, + /* 9226 */ 'f', + 's', + 'q', + 'r', + 't', + 's', + 32, + 0, + /* 9234 */ 'q', + 'v', + 'f', + 'c', + 'f', + 'i', + 'd', + 'u', + 's', + 32, + 0, + /* 9245 */ 'v', + 'p', + 'k', + 's', + 'd', + 'u', + 's', + 32, + 0, + /* 9254 */ 'v', + 'p', + 'k', + 'u', + 'd', + 'u', + 's', + 32, + 0, + /* 9263 */ 'v', + 'p', + 'k', + 's', + 'h', + 'u', + 's', + 32, + 0, + /* 9272 */ 'v', + 'p', + 'k', + 'u', + 'h', + 'u', + 's', + 32, + 0, + /* 9281 */ 'v', + 'p', + 'k', + 's', + 'w', + 'u', + 's', + 32, + 0, + /* 9290 */ 'v', + 'p', + 'k', + 'u', + 'w', + 'u', + 's', + 32, + 0, + /* 9299 */ 'f', + 'd', + 'i', + 'v', + 's', + 32, + 0, + /* 9306 */ 'e', + 'v', + 's', + 'r', + 'w', + 's', + 32, + 0, + /* 9314 */ 'm', + 't', + 'v', + 's', + 'r', + 'w', + 's', + 32, + 0, + /* 9323 */ 'v', + 's', + 'u', + 'm', + '2', + 's', + 'w', + 's', + 32, + 0, + /* 9333 */ 'v', + 's', + 'u', + 'b', + 's', + 'w', + 's', + 32, + 0, + /* 9342 */ 'v', + 'a', + 'd', + 'd', + 's', + 'w', + 's', + 32, + 0, + /* 9351 */ 'v', + 's', + 'u', + 'm', + 's', + 'w', + 's', + 32, + 0, + /* 9360 */ 'v', + 's', + 'u', + 'b', + 'u', + 'w', + 's', + 32, + 0, + /* 9369 */ 'v', + 'a', + 'd', + 'd', + 'u', + 'w', + 's', + 32, + 0, + /* 9378 */ 'e', + 'v', + 'd', + 'i', + 'v', + 'w', + 's', + 32, + 0, + /* 9387 */ 'x', + 's', + 'c', + 'v', + 'd', + 'p', + 's', + 'x', + 'w', + 's', + 32, + 0, + /* 9399 */ 'x', + 'v', + 'c', + 'v', + 'd', + 'p', + 's', + 'x', + 'w', + 's', + 32, + 0, + /* 9411 */ 'x', + 'v', + 'c', + 'v', + 's', + 'p', + 's', + 'x', + 'w', + 's', + 32, + 0, + /* 9423 */ 'x', + 's', + 'c', + 'v', + 'd', + 'p', + 'u', + 'x', + 'w', + 's', + 32, + 0, + /* 9435 */ 'x', + 'v', + 'c', + 'v', + 'd', + 'p', + 'u', + 'x', + 'w', + 's', + 32, + 0, + /* 9447 */ 'x', + 'v', + 'c', + 'v', + 's', + 'p', + 'u', + 'x', + 'w', + 's', + 32, + 0, + /* 9459 */ 'v', + 'c', + 't', + 's', + 'x', + 's', + 32, + 0, + /* 9467 */ 'v', + 'c', + 't', + 'u', + 'x', + 's', + 32, + 0, + /* 9475 */ 'l', + 'd', + 'a', + 't', + 32, + 0, + /* 9481 */ 's', + 't', + 'd', + 'a', + 't', + 32, + 0, + /* 9488 */ 'e', + 'v', + 'l', + 'h', + 'h', + 'e', + 's', + 'p', + 'l', + 'a', + 't', + 32, + 0, + /* 9501 */ 'e', + 'v', + 'l', + 'w', + 'h', + 's', + 'p', + 'l', + 'a', + 't', + 32, + 0, + /* 9513 */ 'e', + 'v', + 'l', + 'h', + 'h', + 'o', + 's', + 's', + 'p', + 'l', + 'a', + 't', + 32, + 0, + /* 9527 */ 'e', + 'v', + 'l', + 'h', + 'h', + 'o', + 'u', + 's', + 'p', + 'l', + 'a', + 't', + 32, + 0, + /* 9541 */ 'e', + 'v', + 'l', + 'w', + 'w', + 's', + 'p', + 'l', + 'a', + 't', + 32, + 0, + /* 9553 */ 'l', + 'w', + 'a', + 't', + 32, + 0, + /* 9559 */ 's', + 't', + 'w', + 'a', + 't', + 32, + 0, + /* 9566 */ 'd', + 'c', + 'b', + 't', + 32, + 0, + /* 9572 */ 'i', + 'c', + 'b', + 't', + 32, + 0, + /* 9578 */ 'd', + 'c', + 'b', + 't', + 'c', + 't', + 32, + 0, + /* 9586 */ 'd', + 'c', + 'b', + 't', + 's', + 't', + 'c', + 't', + 32, + 0, + /* 9596 */ 'e', + 'f', + 'd', + 'c', + 'm', + 'p', + 'g', + 't', + 32, + 0, + /* 9606 */ 'q', + 'v', + 'f', + 'c', + 'm', + 'p', + 'g', + 't', + 32, + 0, + /* 9616 */ 'e', + 'f', + 's', + 'c', + 'm', + 'p', + 'g', + 't', + 32, + 0, + /* 9626 */ 'e', + 'v', + 'f', + 's', + 'c', + 'm', + 'p', + 'g', + 't', + 32, + 0, + /* 9637 */ 'e', + 'f', + 'd', + 't', + 's', + 't', + 'g', + 't', + 32, + 0, + /* 9647 */ 'e', + 'f', + 's', + 't', + 's', + 't', + 'g', + 't', + 32, + 0, + /* 9657 */ 'e', + 'v', + 'f', + 's', + 't', + 's', + 't', + 'g', + 't', + 32, + 0, + /* 9668 */ 'w', + 'a', + 'i', + 't', + 32, + 0, + /* 9674 */ 'e', + 'f', + 'd', + 'c', + 'm', + 'p', + 'l', + 't', + 32, + 0, + /* 9684 */ 'q', + 'v', + 'f', + 'c', + 'm', + 'p', + 'l', + 't', + 32, + 0, + /* 9694 */ 'e', + 'f', + 's', + 'c', + 'm', + 'p', + 'l', + 't', + 32, + 0, + /* 9704 */ 'e', + 'v', + 'f', + 's', + 'c', + 'm', + 'p', + 'l', + 't', + 32, + 0, + /* 9715 */ 'e', + 'f', + 'd', + 't', + 's', + 't', + 'l', + 't', + 32, + 0, + /* 9725 */ 'e', + 'f', + 's', + 't', + 's', + 't', + 'l', + 't', + 32, + 0, + /* 9735 */ 'e', + 'v', + 'f', + 's', + 't', + 's', + 't', + 'l', + 't', + 32, + 0, + /* 9746 */ 'f', + 's', + 'q', + 'r', + 't', + 32, + 0, + /* 9753 */ 'f', + 't', + 's', + 'q', + 'r', + 't', + 32, + 0, + /* 9761 */ 'p', + 'a', + 's', + 't', + 'e', + '_', + 'l', + 'a', + 's', + 't', + 32, + 0, + /* 9773 */ 'v', + 'n', + 'c', + 'i', + 'p', + 'h', + 'e', + 'r', + 'l', + 'a', + 's', + 't', + 32, + 0, + /* 9787 */ 'v', + 'c', + 'i', + 'p', + 'h', + 'e', + 'r', + 'l', + 'a', + 's', + 't', + 32, + 0, + /* 9800 */ 'd', + 'c', + 'b', + 's', + 't', + 32, + 0, + /* 9807 */ 'd', + 's', + 't', + 32, + 0, + /* 9812 */ 'c', + 'o', + 'p', + 'y', + '_', + 'f', + 'i', + 'r', + 's', + 't', + 32, + 0, + /* 9824 */ 'd', + 'c', + 'b', + 't', + 's', + 't', + 32, + 0, + /* 9832 */ 'd', + 's', + 't', + 's', + 't', + 32, + 0, + /* 9839 */ 'd', + 'c', + 'b', + 't', + 't', + 32, + 0, + /* 9846 */ 'd', + 's', + 't', + 't', + 32, + 0, + /* 9852 */ 'd', + 'c', + 'b', + 't', + 's', + 't', + 't', + 32, + 0, + /* 9861 */ 'd', + 's', + 't', + 's', + 't', + 't', + 32, + 0, + /* 9869 */ 'l', + 'h', + 'a', + 'u', + 32, + 0, + /* 9875 */ 's', + 't', + 'b', + 'u', + 32, + 0, + /* 9881 */ 'l', + 'f', + 'd', + 'u', + 32, + 0, + /* 9887 */ 's', + 't', + 'f', + 'd', + 'u', + 32, + 0, + /* 9894 */ 'm', + 'a', + 'd', + 'd', + 'h', + 'd', + 'u', + 32, + 0, + /* 9903 */ 'm', + 'u', + 'l', + 'h', + 'd', + 'u', + 32, + 0, + /* 9911 */ 'q', + 'v', + 'f', + 'c', + 'f', + 'i', + 'd', + 'u', + 32, + 0, + /* 9921 */ 'q', + 'v', + 'f', + 'c', + 't', + 'i', + 'd', + 'u', + 32, + 0, + /* 9931 */ 'l', + 'd', + 'u', + 32, + 0, + /* 9936 */ 's', + 't', + 'd', + 'u', + 32, + 0, + /* 9942 */ 'd', + 'i', + 'v', + 'd', + 'u', + 32, + 0, + /* 9949 */ 'd', + 'i', + 'v', + 'd', + 'e', + 'u', + 32, + 0, + /* 9957 */ 'd', + 'i', + 'v', + 'w', + 'e', + 'u', + 32, + 0, + /* 9965 */ 's', + 't', + 'h', + 'u', + 32, + 0, + /* 9971 */ 'e', + 'v', + 's', + 'r', + 'w', + 'i', + 'u', + 32, + 0, + /* 9980 */ 'e', + 'v', + 'l', + 'w', + 'h', + 'o', + 'u', + 32, + 0, + /* 9989 */ 'f', + 'c', + 'm', + 'p', + 'u', + 32, + 0, + /* 9996 */ 'l', + 'f', + 's', + 'u', + 32, + 0, + /* 10002 */ 's', + 't', + 'f', + 's', + 'u', + 32, + 0, + /* 10009 */ 'e', + 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'u', + 32, + 0, + /* 10019 */ 'e', + 'v', + 'c', + 'm', + 'p', + 'l', + 't', + 'u', + 32, + 0, + /* 10029 */ 'm', + 'u', + 'l', + 'h', + 'w', + 'u', + 32, + 0, + /* 10037 */ 'q', + 'v', + 'f', + 'c', + 't', + 'i', + 'w', + 'u', + 32, + 0, + /* 10047 */ 'e', + 'v', + 's', + 'r', + 'w', + 'u', + 32, + 0, + /* 10055 */ 's', + 't', + 'w', + 'u', + 32, + 0, + /* 10061 */ 'e', + 'v', + 'd', + 'i', + 'v', + 'w', + 'u', + 32, + 0, + /* 10070 */ 'l', + 'b', + 'z', + 'u', + 32, + 0, + /* 10076 */ 'l', + 'h', + 'z', + 'u', + 32, + 0, + /* 10082 */ 'l', + 'w', + 'z', + 'u', + 32, + 0, + /* 10088 */ 's', + 'l', + 'b', + 'm', + 'f', + 'e', + 'v', + 32, + 0, + /* 10097 */ 'e', + 'f', + 'd', + 'd', + 'i', + 'v', + 32, + 0, + /* 10105 */ 'f', + 'd', + 'i', + 'v', + 32, + 0, + /* 10111 */ 'e', + 'f', + 's', + 'd', + 'i', + 'v', + 32, + 0, + /* 10119 */ 'e', + 'v', + 'f', + 's', + 'd', + 'i', + 'v', + 32, + 0, + /* 10128 */ 'f', + 't', + 'd', + 'i', + 'v', + 32, + 0, + /* 10135 */ 'v', + 's', + 'l', + 'v', + 32, + 0, + /* 10141 */ 'x', + 'x', + 'l', + 'e', + 'q', + 'v', + 32, + 0, + /* 10149 */ 'c', + 'r', + 'e', + 'q', + 'v', + 32, + 0, + /* 10156 */ 'e', + 'v', + 'e', + 'q', + 'v', + 32, + 0, + /* 10163 */ 'v', + 's', + 'r', + 'v', + 32, + 0, + /* 10169 */ 'l', + 'x', + 'v', + 32, + 0, + /* 10174 */ 's', + 't', + 'x', + 'v', + 32, + 0, + /* 10180 */ 'v', + 'e', + 'x', + 't', + 's', + 'b', + '2', + 'w', + 32, + 0, + /* 10190 */ 'v', + 'e', + 'x', + 't', + 's', + 'h', + '2', + 'w', + 32, + 0, + /* 10200 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 'm', + 'f', + 'a', + 'a', + 'w', + 32, + 0, + /* 10213 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 'm', + 'f', + 'a', + 'a', + 'w', + 32, + 0, + /* 10226 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 's', + 'f', + 'a', + 'a', + 'w', + 32, + 0, + /* 10239 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 's', + 'f', + 'a', + 'a', + 'w', + 32, + 0, + /* 10252 */ 'e', + 'v', + 'a', + 'd', + 'd', + 's', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10265 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10278 */ 'e', + 'v', + 's', + 'u', + 'b', + 'f', + 's', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10292 */ 'e', + 'v', + 'm', + 'w', + 'l', + 's', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10305 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10318 */ 'e', + 'v', + 'a', + 'd', + 'd', + 'u', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10331 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'u', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10344 */ 'e', + 'v', + 's', + 'u', + 'b', + 'f', + 'u', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10358 */ 'e', + 'v', + 'm', + 'w', + 'l', + 'u', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10371 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'u', + 'm', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10384 */ 'e', + 'v', + 'a', + 'd', + 'd', + 's', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10397 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10410 */ 'e', + 'v', + 's', + 'u', + 'b', + 'f', + 's', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10424 */ 'e', + 'v', + 'm', + 'w', + 'l', + 's', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10437 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10450 */ 'e', + 'v', + 'a', + 'd', + 'd', + 'u', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10463 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'u', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10476 */ 'e', + 'v', + 's', + 'u', + 'b', + 'f', + 'u', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10490 */ 'e', + 'v', + 'm', + 'w', + 'l', + 'u', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10503 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'u', + 's', + 'i', + 'a', + 'a', + 'w', + 32, + 0, + /* 10516 */ 'v', + 's', + 'h', + 'a', + 's', + 'i', + 'g', + 'm', + 'a', + 'w', + 32, + 0, + /* 10528 */ 'v', + 's', + 'r', + 'a', + 'w', + 32, + 0, + /* 10535 */ 'v', + 'p', + 'r', + 't', + 'y', + 'b', + 'w', + 32, + 0, + /* 10544 */ 'e', + 'v', + 'a', + 'd', + 'd', + 'w', + 32, + 0, + /* 10552 */ 'e', + 'v', + 'l', + 'd', + 'w', + 32, + 0, + /* 10559 */ 'e', + 'v', + 'r', + 'n', + 'd', + 'w', + 32, + 0, + /* 10567 */ 'e', + 'v', + 's', + 't', + 'd', + 'w', + 32, + 0, + /* 10575 */ 'v', + 'm', + 'r', + 'g', + 'e', + 'w', + 32, + 0, + /* 10583 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'w', + 32, + 0, + /* 10592 */ 'e', + 'v', + 's', + 'u', + 'b', + 'f', + 'w', + 32, + 0, + /* 10601 */ 'e', + 'v', + 's', + 'u', + 'b', + 'i', + 'f', + 'w', + 32, + 0, + /* 10611 */ 'v', + 'n', + 'e', + 'g', + 'w', + 32, + 0, + /* 10618 */ 'v', + 'm', + 'r', + 'g', + 'h', + 'w', + 32, + 0, + /* 10626 */ 'x', + 'x', + 'm', + 'r', + 'g', + 'h', + 'w', + 32, + 0, + /* 10635 */ 'm', + 'u', + 'l', + 'h', + 'w', + 32, + 0, + /* 10642 */ 'e', + 'v', + 'a', + 'd', + 'd', + 'i', + 'w', + 32, + 0, + /* 10651 */ 'q', + 'v', + 'f', + 'c', + 't', + 'i', + 'w', + 32, + 0, + /* 10660 */ 'v', + 'm', + 'r', + 'g', + 'l', + 'w', + 32, + 0, + /* 10668 */ 'x', + 'x', + 'm', + 'r', + 'g', + 'l', + 'w', + 32, + 0, + /* 10677 */ 'm', + 'u', + 'l', + 'l', + 'w', + 32, + 0, + /* 10684 */ 'c', + 'm', + 'p', + 'l', + 'w', + 32, + 0, + /* 10691 */ 'e', + 'v', + 'r', + 'l', + 'w', + 32, + 0, + /* 10698 */ 'e', + 'v', + 's', + 'l', + 'w', + 32, + 0, + /* 10705 */ 'l', + 'm', + 'w', + 32, + 0, + /* 10710 */ 's', + 't', + 'm', + 'w', + 32, + 0, + /* 10716 */ 'v', + 'p', + 'm', + 's', + 'u', + 'm', + 'w', + 32, + 0, + /* 10725 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 'm', + 'f', + 'a', + 'n', + 'w', + 32, + 0, + /* 10738 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 'm', + 'f', + 'a', + 'n', + 'w', + 32, + 0, + /* 10751 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 's', + 'f', + 'a', + 'n', + 'w', + 32, + 0, + /* 10764 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 's', + 'f', + 'a', + 'n', + 'w', + 32, + 0, + /* 10777 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 'm', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10790 */ 'e', + 'v', + 'm', + 'w', + 'l', + 's', + 'm', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10803 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 'm', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10816 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'u', + 'm', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10829 */ 'e', + 'v', + 'm', + 'w', + 'l', + 'u', + 'm', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10842 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'u', + 'm', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10855 */ 'e', + 'v', + 'm', + 'h', + 'e', + 's', + 's', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10868 */ 'e', + 'v', + 'm', + 'w', + 'l', + 's', + 's', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10881 */ 'e', + 'v', + 'm', + 'h', + 'o', + 's', + 's', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10894 */ 'e', + 'v', + 'm', + 'h', + 'e', + 'u', + 's', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10907 */ 'e', + 'v', + 'm', + 'w', + 'l', + 'u', + 's', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10920 */ 'e', + 'v', + 'm', + 'h', + 'o', + 'u', + 's', + 'i', + 'a', + 'n', + 'w', + 32, + 0, + /* 10933 */ 'v', + 'm', + 'r', + 'g', + 'o', + 'w', + 32, + 0, + /* 10941 */ 'c', + 'm', + 'p', + 'w', + 32, + 0, + /* 10947 */ 'x', + 'x', + 'b', + 'r', + 'w', + 32, + 0, + /* 10954 */ 'v', + 's', + 'r', + 'w', + 32, + 0, + /* 10960 */ 'm', + 'o', + 'd', + 's', + 'w', + 32, + 0, + /* 10967 */ 'v', + 'm', + 'u', + 'l', + 'e', + 's', + 'w', + 32, + 0, + /* 10976 */ 'v', + 'a', + 'v', + 'g', + 's', + 'w', + 32, + 0, + /* 10984 */ 'v', + 'u', + 'p', + 'k', + 'h', + 's', + 'w', + 32, + 0, + /* 10993 */ 'v', + 's', + 'p', + 'l', + 't', + 'i', + 's', + 'w', + 32, + 0, + /* 11003 */ 'v', + 'u', + 'p', + 'k', + 'l', + 's', + 'w', + 32, + 0, + /* 11012 */ 'e', + 'v', + 'c', + 'n', + 't', + 'l', + 's', + 'w', + 32, + 0, + /* 11022 */ 'v', + 'm', + 'i', + 'n', + 's', + 'w', + 32, + 0, + /* 11030 */ 'v', + 'm', + 'u', + 'l', + 'o', + 's', + 'w', + 32, + 0, + /* 11039 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 's', + 'w', + 32, + 0, + /* 11049 */ 'e', + 'x', + 't', + 's', + 'w', + 32, + 0, + /* 11056 */ 'v', + 'm', + 'a', + 'x', + 's', + 'w', + 32, + 0, + /* 11064 */ 'v', + 's', + 'p', + 'l', + 't', + 'w', + 32, + 0, + /* 11072 */ 'x', + 'x', + 's', + 'p', + 'l', + 't', + 'w', + 32, + 0, + /* 11081 */ 'v', + 'p', + 'o', + 'p', + 'c', + 'n', + 't', + 'w', + 32, + 0, + /* 11091 */ 'v', + 'i', + 'n', + 's', + 'e', + 'r', + 't', + 'w', + 32, + 0, + /* 11101 */ 'x', + 'x', + 'i', + 'n', + 's', + 'e', + 'r', + 't', + 'w', + 32, + 0, + /* 11112 */ 's', + 't', + 'w', + 32, + 0, + /* 11117 */ 'v', + 's', + 'u', + 'b', + 'c', + 'u', + 'w', + 32, + 0, + /* 11126 */ 'v', + 'a', + 'd', + 'd', + 'c', + 'u', + 'w', + 32, + 0, + /* 11135 */ 'm', + 'o', + 'd', + 'u', + 'w', + 32, + 0, + /* 11142 */ 'v', + 'a', + 'b', + 's', + 'd', + 'u', + 'w', + 32, + 0, + /* 11151 */ 'v', + 'm', + 'u', + 'l', + 'e', + 'u', + 'w', + 32, + 0, + /* 11160 */ 'v', + 'a', + 'v', + 'g', + 'u', + 'w', + 32, + 0, + /* 11168 */ 'v', + 'm', + 'i', + 'n', + 'u', + 'w', + 32, + 0, + /* 11176 */ 'v', + 'm', + 'u', + 'l', + 'o', + 'u', + 'w', + 32, + 0, + /* 11185 */ 'v', + 'c', + 'm', + 'p', + 'e', + 'q', + 'u', + 'w', + 32, + 0, + /* 11195 */ 'v', + 'e', + 'x', + 't', + 'r', + 'a', + 'c', + 't', + 'u', + 'w', + 32, + 0, + /* 11207 */ 'x', + 'x', + 'e', + 'x', + 't', + 'r', + 'a', + 'c', + 't', + 'u', + 'w', + 32, + 0, + /* 11220 */ 'v', + 'c', + 'm', + 'p', + 'g', + 't', + 'u', + 'w', + 32, + 0, + /* 11230 */ 'v', + 'm', + 'a', + 'x', + 'u', + 'w', + 32, + 0, + /* 11238 */ 'd', + 'i', + 'v', + 'w', + 32, + 0, + /* 11244 */ 'v', + 'c', + 'm', + 'p', + 'n', + 'e', + 'z', + 'w', + 32, + 0, + /* 11254 */ 'v', + 'c', + 'l', + 'z', + 'w', + 32, + 0, + /* 11261 */ 'e', + 'v', + 'c', + 'n', + 't', + 'l', + 'z', + 'w', + 32, + 0, + /* 11271 */ 'v', + 'c', + 't', + 'z', + 'w', + 32, + 0, + /* 11278 */ 'c', + 'n', + 't', + 't', + 'z', + 'w', + 32, + 0, + /* 11286 */ 'l', + 'x', + 'v', + 'd', + '2', + 'x', + 32, + 0, + /* 11294 */ 's', + 't', + 'x', + 'v', + 'd', + '2', + 'x', + 32, + 0, + /* 11303 */ 'l', + 'x', + 'v', + 'w', + '4', + 'x', + 32, + 0, + /* 11311 */ 's', + 't', + 'x', + 'v', + 'w', + '4', + 'x', + 32, + 0, + /* 11320 */ 'l', + 'x', + 'v', + 'b', + '1', + '6', + 'x', + 32, + 0, + /* 11329 */ 's', + 't', + 'x', + 'v', + 'b', + '1', + '6', + 'x', + 32, + 0, + /* 11339 */ 'l', + 'x', + 'v', + 'h', + '8', + 'x', + 32, + 0, + /* 11347 */ 's', + 't', + 'x', + 'v', + 'h', + '8', + 'x', + 32, + 0, + /* 11356 */ 'l', + 'h', + 'a', + 'x', + 32, + 0, + /* 11362 */ 't', + 'l', + 'b', + 'i', + 'v', + 'a', + 'x', + 32, + 0, + /* 11371 */ 'q', + 'v', + 'l', + 'f', + 'i', + 'w', + 'a', + 'x', + 32, + 0, + /* 11381 */ 'l', + 'x', + 's', + 'i', + 'w', + 'a', + 'x', + 32, + 0, + /* 11390 */ 'l', + 'w', + 'a', + 'x', + 32, + 0, + /* 11396 */ 'l', + 'v', + 'e', + 'b', + 'x', + 32, + 0, + /* 11403 */ 's', + 't', + 'v', + 'e', + 'b', + 'x', + 32, + 0, + /* 11411 */ 's', + 't', + 'x', + 's', + 'i', + 'b', + 'x', + 32, + 0, + /* 11420 */ 's', + 't', + 'b', + 'x', + 32, + 0, + /* 11426 */ 'q', + 'v', + 'l', + 'f', + 'c', + 'd', + 'x', + 32, + 0, + /* 11435 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 'd', + 'x', + 32, + 0, + /* 11445 */ 'e', + 'v', + 'l', + 'd', + 'd', + 'x', + 32, + 0, + /* 11453 */ 'e', + 'v', + 's', + 't', + 'd', + 'd', + 'x', + 32, + 0, + /* 11462 */ 'q', + 'v', + 'l', + 'f', + 'd', + 'x', + 32, + 0, + /* 11470 */ 'q', + 'v', + 's', + 't', + 'f', + 'd', + 'x', + 32, + 0, + /* 11479 */ 'q', + 'v', + 'l', + 'p', + 'c', + 'l', + 'd', + 'x', + 32, + 0, + /* 11489 */ 'q', + 'v', + 'l', + 'p', + 'c', + 'r', + 'd', + 'x', + 32, + 0, + /* 11499 */ 'l', + 'x', + 's', + 'd', + 'x', + 32, + 0, + /* 11506 */ 's', + 't', + 'x', + 's', + 'd', + 'x', + 32, + 0, + /* 11514 */ 's', + 't', + 'd', + 'x', + 32, + 0, + /* 11520 */ 'e', + 'v', + 'l', + 'w', + 'h', + 'e', + 'x', + 32, + 0, + /* 11529 */ 'e', + 'v', + 's', + 't', + 'w', + 'h', + 'e', + 'x', + 32, + 0, + /* 11539 */ 'e', + 'v', + 's', + 't', + 'w', + 'w', + 'e', + 'x', + 32, + 0, + /* 11549 */ 'e', + 'v', + 'l', + 'd', + 'h', + 'x', + 32, + 0, + /* 11557 */ 'e', + 'v', + 's', + 't', + 'd', + 'h', + 'x', + 32, + 0, + /* 11566 */ 'l', + 'v', + 'e', + 'h', + 'x', + 32, + 0, + /* 11573 */ 's', + 't', + 'v', + 'e', + 'h', + 'x', + 32, + 0, + /* 11581 */ 's', + 't', + 'x', + 's', + 'i', + 'h', + 'x', + 32, + 0, + /* 11590 */ 's', + 't', + 'h', + 'x', + 32, + 0, + /* 11596 */ 's', + 't', + 'b', + 'c', + 'i', + 'x', + 32, + 0, + /* 11604 */ 'l', + 'd', + 'c', + 'i', + 'x', + 32, + 0, + /* 11611 */ 's', + 't', + 'd', + 'c', + 'i', + 'x', + 32, + 0, + /* 11619 */ 's', + 't', + 'h', + 'c', + 'i', + 'x', + 32, + 0, + /* 11627 */ 's', + 't', + 'w', + 'c', + 'i', + 'x', + 32, + 0, + /* 11635 */ 'l', + 'b', + 'z', + 'c', + 'i', + 'x', + 32, + 0, + /* 11643 */ 'l', + 'h', + 'z', + 'c', + 'i', + 'x', + 32, + 0, + /* 11651 */ 'l', + 'w', + 'z', + 'c', + 'i', + 'x', + 32, + 0, + /* 11659 */ 'x', + 's', + 'r', + 'q', + 'p', + 'i', + 'x', + 32, + 0, + /* 11668 */ 'v', + 'e', + 'x', + 't', + 'u', + 'b', + 'l', + 'x', + 32, + 0, + /* 11678 */ 'v', + 'e', + 'x', + 't', + 'u', + 'h', + 'l', + 'x', + 32, + 0, + /* 11688 */ 'v', + 'e', + 'x', + 't', + 'u', + 'w', + 'l', + 'x', + 32, + 0, + /* 11698 */ 'l', + 'd', + 'm', + 'x', + 32, + 0, + /* 11704 */ 'v', + 's', + 'b', + 'o', + 'x', + 32, + 0, + /* 11711 */ 'e', + 'v', + 's', + 't', + 'w', + 'h', + 'o', + 'x', + 32, + 0, + /* 11721 */ 'e', + 'v', + 's', + 't', + 'w', + 'w', + 'o', + 'x', + 32, + 0, + /* 11731 */ 'l', + 'b', + 'e', + 'p', + 'x', + 32, + 0, + /* 11738 */ 's', + 't', + 'b', + 'e', + 'p', + 'x', + 32, + 0, + /* 11746 */ 'l', + 'f', + 'd', + 'e', + 'p', + 'x', + 32, + 0, + /* 11754 */ 's', + 't', + 'f', + 'd', + 'e', + 'p', + 'x', + 32, + 0, + /* 11763 */ 'l', + 'h', + 'e', + 'p', + 'x', + 32, + 0, + /* 11770 */ 's', + 't', + 'h', + 'e', + 'p', + 'x', + 32, + 0, + /* 11778 */ 'l', + 'w', + 'e', + 'p', + 'x', + 32, + 0, + /* 11785 */ 's', + 't', + 'w', + 'e', + 'p', + 'x', + 32, + 0, + /* 11793 */ 'v', + 'u', + 'p', + 'k', + 'h', + 'p', + 'x', + 32, + 0, + /* 11802 */ 'v', + 'p', + 'k', + 'p', + 'x', + 32, + 0, + /* 11809 */ 'v', + 'u', + 'p', + 'k', + 'l', + 'p', + 'x', + 32, + 0, + /* 11818 */ 'l', + 'x', + 's', + 's', + 'p', + 'x', + 32, + 0, + /* 11826 */ 's', + 't', + 'x', + 's', + 's', + 'p', + 'x', + 32, + 0, + /* 11835 */ 'l', + 'b', + 'a', + 'r', + 'x', + 32, + 0, + /* 11842 */ 'l', + 'd', + 'a', + 'r', + 'x', + 32, + 0, + /* 11849 */ 'l', + 'h', + 'a', + 'r', + 'x', + 32, + 0, + /* 11856 */ 'l', + 'w', + 'a', + 'r', + 'x', + 32, + 0, + /* 11863 */ 'l', + 'd', + 'b', + 'r', + 'x', + 32, + 0, + /* 11870 */ 's', + 't', + 'd', + 'b', + 'r', + 'x', + 32, + 0, + /* 11878 */ 'l', + 'h', + 'b', + 'r', + 'x', + 32, + 0, + /* 11885 */ 's', + 't', + 'h', + 'b', + 'r', + 'x', + 32, + 0, + /* 11893 */ 'v', + 'e', + 'x', + 't', + 'u', + 'b', + 'r', + 'x', + 32, + 0, + /* 11903 */ 'l', + 'w', + 'b', + 'r', + 'x', + 32, + 0, + /* 11910 */ 's', + 't', + 'w', + 'b', + 'r', + 'x', + 32, + 0, + /* 11918 */ 'v', + 'e', + 'x', + 't', + 'u', + 'h', + 'r', + 'x', + 32, + 0, + /* 11928 */ 'v', + 'e', + 'x', + 't', + 'u', + 'w', + 'r', + 'x', + 32, + 0, + /* 11938 */ 'm', + 'c', + 'r', + 'x', + 'r', + 'x', + 32, + 0, + /* 11946 */ 't', + 'l', + 'b', + 's', + 'x', + 32, + 0, + /* 11953 */ 'q', + 'v', + 'l', + 'f', + 'c', + 's', + 'x', + 32, + 0, + /* 11962 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 's', + 'x', + 32, + 0, + /* 11972 */ 'l', + 'x', + 'v', + 'd', + 's', + 'x', + 32, + 0, + /* 11980 */ 'v', + 'c', + 'f', + 's', + 'x', + 32, + 0, + /* 11987 */ 'q', + 'v', + 'l', + 'f', + 's', + 'x', + 32, + 0, + /* 11995 */ 'q', + 'v', + 's', + 't', + 'f', + 's', + 'x', + 32, + 0, + /* 12004 */ 'q', + 'v', + 'l', + 'p', + 'c', + 'l', + 's', + 'x', + 32, + 0, + /* 12014 */ 'e', + 'v', + 'l', + 'w', + 'h', + 'o', + 's', + 'x', + 32, + 0, + /* 12024 */ 'q', + 'v', + 'l', + 'p', + 'c', + 'r', + 's', + 'x', + 32, + 0, + /* 12034 */ 'l', + 'x', + 'v', + 'w', + 's', + 'x', + 32, + 0, + /* 12042 */ 'e', + 'v', + 'l', + 'h', + 'h', + 'e', + 's', + 'p', + 'l', + 'a', + 't', + 'x', + 32, + 0, + /* 12056 */ 'e', + 'v', + 'l', + 'w', + 'h', + 's', + 'p', + 'l', + 'a', + 't', + 'x', + 32, + 0, + /* 12069 */ 'e', + 'v', + 'l', + 'h', + 'h', + 'o', + 's', + 's', + 'p', + 'l', + 'a', + 't', + 'x', + 32, + 0, + /* 12084 */ 'e', + 'v', + 'l', + 'h', + 'h', + 'o', + 'u', + 's', + 'p', + 'l', + 'a', + 't', + 'x', + 32, + 0, + /* 12099 */ 'e', + 'v', + 'l', + 'w', + 'w', + 's', + 'p', + 'l', + 'a', + 't', + 'x', + 32, + 0, + /* 12112 */ 'l', + 'h', + 'a', + 'u', + 'x', + 32, + 0, + /* 12119 */ 'l', + 'w', + 'a', + 'u', + 'x', + 32, + 0, + /* 12126 */ 's', + 't', + 'b', + 'u', + 'x', + 32, + 0, + /* 12133 */ 'q', + 'v', + 'l', + 'f', + 'c', + 'd', + 'u', + 'x', + 32, + 0, + /* 12143 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 'd', + 'u', + 'x', + 32, + 0, + /* 12154 */ 'q', + 'v', + 'l', + 'f', + 'd', + 'u', + 'x', + 32, + 0, + /* 12163 */ 'q', + 'v', + 's', + 't', + 'f', + 'd', + 'u', + 'x', + 32, + 0, + /* 12173 */ 'l', + 'd', + 'u', + 'x', + 32, + 0, + /* 12179 */ 's', + 't', + 'd', + 'u', + 'x', + 32, + 0, + /* 12186 */ 'v', + 'c', + 'f', + 'u', + 'x', + 32, + 0, + /* 12193 */ 's', + 't', + 'h', + 'u', + 'x', + 32, + 0, + /* 12200 */ 'e', + 'v', + 'l', + 'w', + 'h', + 'o', + 'u', + 'x', + 32, + 0, + /* 12210 */ 'q', + 'v', + 'l', + 'f', + 'c', + 's', + 'u', + 'x', + 32, + 0, + /* 12220 */ 'q', + 'v', + 's', + 't', + 'f', + 'c', + 's', + 'u', + 'x', + 32, + 0, + /* 12231 */ 'q', + 'v', + 'l', + 'f', + 's', + 'u', + 'x', + 32, + 0, + /* 12240 */ 'q', + 'v', + 's', + 't', + 'f', + 's', + 'u', + 'x', + 32, + 0, + /* 12250 */ 's', + 't', + 'w', + 'u', + 'x', + 32, + 0, + /* 12257 */ 'l', + 'b', + 'z', + 'u', + 'x', + 32, + 0, + /* 12264 */ 'l', + 'h', + 'z', + 'u', + 'x', + 32, + 0, + /* 12271 */ 'l', + 'w', + 'z', + 'u', + 'x', + 32, + 0, + /* 12278 */ 'l', + 'v', + 'x', + 32, + 0, + /* 12283 */ 's', + 't', + 'v', + 'x', + 32, + 0, + /* 12289 */ 'l', + 'x', + 'v', + 'x', + 32, + 0, + /* 12295 */ 's', + 't', + 'x', + 'v', + 'x', + 32, + 0, + /* 12302 */ 'e', + 'v', + 'l', + 'd', + 'w', + 'x', + 32, + 0, + /* 12310 */ 'e', + 'v', + 's', + 't', + 'd', + 'w', + 'x', + 32, + 0, + /* 12319 */ 'l', + 'v', + 'e', + 'w', + 'x', + 32, + 0, + /* 12326 */ 's', + 't', + 'v', + 'e', + 'w', + 'x', + 32, + 0, + /* 12334 */ 'q', + 'v', + 's', + 't', + 'f', + 'i', + 'w', + 'x', + 32, + 0, + /* 12344 */ 's', + 't', + 'x', + 's', + 'i', + 'w', + 'x', + 32, + 0, + /* 12353 */ 's', + 't', + 'w', + 'x', + 32, + 0, + /* 12359 */ 'l', + 'x', + 's', + 'i', + 'b', + 'z', + 'x', + 32, + 0, + /* 12368 */ 'l', + 'b', + 'z', + 'x', + 32, + 0, + /* 12374 */ 'l', + 'x', + 's', + 'i', + 'h', + 'z', + 'x', + 32, + 0, + /* 12383 */ 'l', + 'h', + 'z', + 'x', + 32, + 0, + /* 12389 */ 'q', + 'v', + 'l', + 'f', + 'i', + 'w', + 'z', + 'x', + 32, + 0, + /* 12399 */ 'l', + 'x', + 's', + 'i', + 'w', + 'z', + 'x', + 32, + 0, + /* 12408 */ 'l', + 'w', + 'z', + 'x', + 32, + 0, + /* 12414 */ 'c', + 'o', + 'p', + 'y', + 32, + 0, + /* 12420 */ 'd', + 'c', + 'b', + 'z', + 32, + 0, + /* 12426 */ 'l', + 'b', + 'z', + 32, + 0, + /* 12431 */ 'b', + 'd', + 'z', + 32, + 0, + /* 12436 */ 'e', + 'f', + 'd', + 'c', + 't', + 's', + 'i', + 'd', + 'z', + 32, + 0, + /* 12447 */ 'q', + 'v', + 'f', + 'c', + 't', + 'i', + 'd', + 'z', + 32, + 0, + /* 12457 */ 'e', + 'f', + 'd', + 'c', + 't', + 'u', + 'i', + 'd', + 'z', + 32, + 0, + /* 12468 */ 'x', + 's', + 'c', + 'v', + 'q', + 'p', + 's', + 'd', + 'z', + 32, + 0, + /* 12479 */ 'x', + 's', + 'c', + 'v', + 'q', + 'p', + 'u', + 'd', + 'z', + 32, + 0, + /* 12490 */ 'l', + 'h', + 'z', + 32, + 0, + /* 12495 */ 'v', + 'r', + 'f', + 'i', + 'z', + 32, + 0, + /* 12502 */ 'x', + 's', + 'r', + 'd', + 'p', + 'i', + 'z', + 32, + 0, + /* 12511 */ 'x', + 'v', + 'r', + 'd', + 'p', + 'i', + 'z', + 32, + 0, + /* 12520 */ 'x', + 'v', + 'r', + 's', + 'p', + 'i', + 'z', + 32, + 0, + /* 12529 */ 'q', + 'v', + 'f', + 'r', + 'i', + 'z', + 32, + 0, + /* 12537 */ 'e', + 'f', + 'd', + 'c', + 't', + 's', + 'i', + 'z', + 32, + 0, + /* 12547 */ 'e', + 'f', + 's', + 'c', + 't', + 's', + 'i', + 'z', + 32, + 0, + /* 12557 */ 'e', + 'v', + 'f', + 's', + 'c', + 't', + 's', + 'i', + 'z', + 32, + 0, + /* 12568 */ 'e', + 'f', + 'd', + 'c', + 't', + 'u', + 'i', + 'z', + 32, + 0, + /* 12578 */ 'e', + 'f', + 's', + 'c', + 't', + 'u', + 'i', + 'z', + 32, + 0, + /* 12588 */ 'b', + 'd', + 'n', + 'z', + 32, + 0, + /* 12594 */ 'q', + 'v', + 'f', + 'c', + 't', + 'i', + 'd', + 'u', + 'z', + 32, + 0, + /* 12605 */ 'q', + 'v', + 'f', + 'c', + 't', + 'i', + 'w', + 'u', + 'z', + 32, + 0, + /* 12616 */ 'q', + 'v', + 'f', + 'c', + 't', + 'i', + 'w', + 'z', + 32, + 0, + /* 12626 */ 'l', + 'w', + 'z', + 32, + 0, + /* 12631 */ 'm', + 'f', + 'v', + 's', + 'r', + 'w', + 'z', + 32, + 0, + /* 12640 */ 'm', + 't', + 'v', + 's', + 'r', + 'w', + 'z', + 32, + 0, + /* 12649 */ 'x', + 's', + 'c', + 'v', + 'q', + 'p', + 's', + 'w', + 'z', + 32, + 0, + /* 12660 */ 'x', + 's', + 'c', + 'v', + 'q', + 'p', + 'u', + 'w', + 'z', + 32, + 0, + /* 12671 */ 'b', + 'd', + 'z', + 'l', + 'r', + 'l', + '+', + 0, + /* 12679 */ 'b', + 'd', + 'n', + 'z', + 'l', + 'r', + 'l', + '+', + 0, + /* 12688 */ 'b', + 'd', + 'z', + 'l', + 'r', + '+', + 0, + /* 12695 */ 'b', + 'd', + 'n', + 'z', + 'l', + 'r', + '+', + 0, + /* 12703 */ 'e', + 'v', + 's', + 'e', + 'l', + 32, + 'c', + 'r', + 'D', + ',', + 0, + /* 12714 */ 'b', + 'd', + 'z', + 'l', + 'r', + 'l', + '-', + 0, + /* 12722 */ 'b', + 'd', + 'n', + 'z', + 'l', + 'r', + 'l', + '-', + 0, + /* 12731 */ 'b', + 'd', + 'z', + 'l', + 'r', + '-', + 0, + /* 12738 */ 'b', + 'd', + 'n', + 'z', + 'l', + 'r', + '-', + 0, + /* 12746 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'P', + 'a', + 't', + 'c', + 'h', + 'a', + 'b', + 'l', + 'e', + 32, + 'R', + 'E', + 'T', + '.', + 0, + /* 12777 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'y', + 'p', + 'e', + 'd', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 12801 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'C', + 'u', + 's', + 't', + 'o', + 'm', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 12826 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'n', + 't', + 'e', + 'r', + '.', + 0, + /* 12849 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'a', + 'i', + 'l', + 32, + 'C', + 'a', + 'l', + 'l', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 12872 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 12894 */ 't', + 'r', + 'e', + 'c', + 'h', + 'k', + 'p', + 't', + '.', + 0, + /* 12904 */ 'o', + 'r', + 'i', + 32, + '1', + ',', + 32, + '1', + ',', + 32, + '0', + 0, + /* 12916 */ 'o', + 'r', + 'i', + 32, + '2', + ',', + 32, + '2', + ',', + 32, + '0', + 0, + /* 12928 */ '#', + 'A', + 'D', + 'D', + 'I', + 'S', + 'd', + 't', + 'p', + 'r', + 'e', + 'l', + 'H', + 'A', + '3', + '2', + 0, + /* 12945 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'S', + 'U', + 'B', + '_', + 'I', + '3', + '2', + 0, + /* 12966 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'A', + 'D', + 'D', + '_', + 'I', + '3', + '2', + 0, + /* 12987 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'N', + 'A', + 'N', + 'D', + '_', + 'I', + '3', + '2', + 0, + /* 13009 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'A', + 'N', + 'D', + '_', + 'I', + '3', + '2', + 0, + /* 13030 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'U', + 'M', + 'I', + 'N', + '_', + 'I', + '3', + '2', + 0, + /* 13052 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'M', + 'I', + 'N', + '_', + 'I', + '3', + '2', + 0, + /* 13073 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'S', + 'W', + 'A', + 'P', + '_', + 'I', + '3', + '2', + 0, + /* 13090 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'X', + 'O', + 'R', + '_', + 'I', + '3', + '2', + 0, + /* 13111 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'O', + 'R', + '_', + 'I', + '3', + '2', + 0, + /* 13131 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'U', + 'M', + 'A', + 'X', + '_', + 'I', + '3', + '2', + 0, + /* 13153 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'M', + 'A', + 'X', + '_', + 'I', + '3', + '2', + 0, + /* 13174 */ '#', + 'A', + 'D', + 'D', + 'I', + 't', + 'l', + 's', + 'g', + 'd', + 'L', + '3', + '2', + 0, + /* 13188 */ '#', + 'A', + 'D', + 'D', + 'I', + 't', + 'l', + 's', + 'l', + 'd', + 'L', + '3', + '2', + 0, + /* 13202 */ '#', + 'L', + 'D', + 'g', + 'o', + 't', + 'T', + 'p', + 'r', + 'e', + 'l', + 'L', + '3', + '2', + 0, + /* 13217 */ '#', + 'A', + 'D', + 'D', + 'I', + 'd', + 't', + 'p', + 'r', + 'e', + 'l', + 'L', + '3', + '2', + 0, + /* 13232 */ '#', + 'E', + 'H', + '_', + 'S', + 'J', + 'L', + 'J', + '_', + 'L', + 'O', + 'N', + 'G', + 'J', + 'M', + 'P', + '3', + '2', + 0, + /* 13251 */ '#', + 'E', + 'H', + '_', + 'S', + 'J', + 'L', + 'J', + '_', + 'S', + 'E', + 'T', + 'J', + 'M', + 'P', + '3', + '2', + 0, + /* 13269 */ '#', + 'A', + 'D', + 'D', + 'I', + 't', + 'l', + 's', + 'g', + 'd', + 'L', + 'A', + 'D', + 'D', + 'R', + '3', + '2', + 0, + /* 13287 */ '#', + 'A', + 'D', + 'D', + 'I', + 't', + 'l', + 's', + 'l', + 'd', + 'L', + 'A', + 'D', + 'D', + 'R', + '3', + '2', + 0, + /* 13305 */ 'G', + 'E', + 'T', + 't', + 'l', + 's', + 'l', + 'd', + 'A', + 'D', + 'D', + 'R', + '3', + '2', + 0, + /* 13320 */ 'G', + 'E', + 'T', + 't', + 'l', + 's', + 'A', + 'D', + 'D', + 'R', + '3', + '2', + 0, + /* 13333 */ '#', + 'D', + 'F', + 'L', + 'O', + 'A', + 'D', + 'f', + '3', + '2', + 0, + /* 13344 */ '#', + 'X', + 'F', + 'L', + 'O', + 'A', + 'D', + 'f', + '3', + '2', + 0, + /* 13355 */ '#', + 'D', + 'F', + 'S', + 'T', + 'O', + 'R', + 'E', + 'f', + '3', + '2', + 0, + /* 13367 */ '#', + 'X', + 'F', + 'S', + 'T', + 'O', + 'R', + 'E', + 'f', + '3', + '2', + 0, + /* 13379 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'S', + 'U', + 'B', + '_', + 'I', + '6', + '4', + 0, + /* 13400 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'A', + 'D', + 'D', + '_', + 'I', + '6', + '4', + 0, + /* 13421 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'N', + 'A', + 'N', + 'D', + '_', + 'I', + '6', + '4', + 0, + /* 13443 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'U', + 'M', + 'I', + 'N', + '_', + 'I', + '6', + '4', + 0, + /* 13465 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'M', + 'I', + 'N', + '_', + 'I', + '6', + '4', + 0, + /* 13486 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'S', + 'W', + 'A', + 'P', + '_', + 'I', + '6', + '4', + 0, + /* 13503 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'C', + 'M', + 'P', + '_', + 'S', + 'W', + 'A', + 'P', + '_', + 'I', + '6', + '4', + 0, + /* 13524 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'X', + 'O', + 'R', + '_', + 'I', + '6', + '4', + 0, + /* 13545 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'O', + 'R', + '_', + 'I', + '6', + '4', + 0, + /* 13565 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'U', + 'M', + 'A', + 'X', + '_', + 'I', + '6', + '4', + 0, + /* 13587 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'M', + 'A', + 'X', + '_', + 'I', + '6', + '4', + 0, + /* 13608 */ '#', + 'E', + 'H', + '_', + 'S', + 'J', + 'L', + 'J', + '_', + 'L', + 'O', + 'N', + 'G', + 'J', + 'M', + 'P', + '6', + '4', + 0, + /* 13627 */ '#', + 'E', + 'H', + '_', + 'S', + 'J', + 'L', + 'J', + '_', + 'S', + 'E', + 'T', + 'J', + 'M', + 'P', + '6', + '4', + 0, + /* 13645 */ '#', + 'D', + 'F', + 'L', + 'O', + 'A', + 'D', + 'f', + '6', + '4', + 0, + /* 13656 */ '#', + 'X', + 'F', + 'L', + 'O', + 'A', + 'D', + 'f', + '6', + '4', + 0, + /* 13667 */ '#', + 'D', + 'F', + 'S', + 'T', + 'O', + 'R', + 'E', + 'f', + '6', + '4', + 0, + /* 13679 */ '#', + 'X', + 'F', + 'S', + 'T', + 'O', + 'R', + 'E', + 'f', + '6', + '4', + 0, + /* 13691 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'A', + 'N', + 'D', + '_', + 'i', + '6', + '4', + 0, + /* 13712 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'S', + 'P', + 'E', + '4', + 0, + /* 13728 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'S', + 'P', + 'E', + '4', + 0, + /* 13741 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'F', + '4', + 0, + /* 13755 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'F', + '4', + 0, + /* 13766 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'I', + '4', + 0, + /* 13780 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'I', + '4', + 0, + /* 13791 */ 'c', + 'r', + 'x', + 'o', + 'r', + 32, + '6', + ',', + 32, + '6', + ',', + 32, + '6', + 0, + /* 13805 */ 'c', + 'r', + 'e', + 'q', + 'v', + 32, + '6', + ',', + 32, + '6', + ',', + 32, + '6', + 0, + /* 13819 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'F', + '1', + '6', + 0, + /* 13834 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'F', + '1', + '6', + 0, + /* 13846 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'S', + 'U', + 'B', + '_', + 'I', + '1', + '6', + 0, + /* 13867 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'A', + 'D', + 'D', + '_', + 'I', + '1', + '6', + 0, + /* 13888 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'N', + 'A', + 'N', + 'D', + '_', + 'I', + '1', + '6', + 0, + /* 13910 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'A', + 'N', + 'D', + '_', + 'I', + '1', + '6', + 0, + /* 13931 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'U', + 'M', + 'I', + 'N', + '_', + 'I', + '1', + '6', + 0, + /* 13953 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'M', + 'I', + 'N', + '_', + 'I', + '1', + '6', + 0, + /* 13974 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'S', + 'W', + 'A', + 'P', + '_', + 'I', + '1', + '6', + 0, + /* 13991 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'X', + 'O', + 'R', + '_', + 'I', + '1', + '6', + 0, + /* 14012 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'O', + 'R', + '_', + 'I', + '1', + '6', + 0, + /* 14032 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'U', + 'M', + 'A', + 'X', + '_', + 'I', + '1', + '6', + 0, + /* 14054 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'M', + 'A', + 'X', + '_', + 'I', + '1', + '6', + 0, + /* 14075 */ '#', + 'D', + 'Y', + 'N', + 'A', + 'L', + 'L', + 'O', + 'C', + '8', + 0, + /* 14086 */ '#', + 'C', + 'F', + 'E', + 'N', + 'C', + 'E', + '8', + 0, + /* 14095 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'F', + '8', + 0, + /* 14109 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'F', + '8', + 0, + /* 14120 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'S', + 'U', + 'B', + '_', + 'I', + '8', + 0, + /* 14140 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'I', + '8', + 0, + /* 14154 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'A', + 'D', + 'D', + '_', + 'I', + '8', + 0, + /* 14174 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'N', + 'A', + 'N', + 'D', + '_', + 'I', + '8', + 0, + /* 14195 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'A', + 'N', + 'D', + '_', + 'I', + '8', + 0, + /* 14215 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'U', + 'M', + 'I', + 'N', + '_', + 'I', + '8', + 0, + /* 14236 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'M', + 'I', + 'N', + '_', + 'I', + '8', + 0, + /* 14256 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'C', + 'M', + 'P', + '_', + 'S', + 'W', + 'A', + 'P', + '_', + 'I', + '8', + 0, + /* 14276 */ 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'X', + 'O', + 'R', + '_', + 'I', + '8', + 0, + /* 14295 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'O', + 'R', + '_', + 'I', + '8', + 0, + /* 14314 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'I', + '8', + 0, + /* 14325 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'U', + 'M', + 'A', + 'X', + '_', + 'I', + '8', + 0, + /* 14346 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'L', + 'O', + 'A', + 'D', + '_', + 'M', + 'A', + 'X', + '_', + 'I', + '8', + 0, + /* 14366 */ '#', + 'M', + 'o', + 'v', + 'e', + 'P', + 'C', + 't', + 'o', + 'L', + 'R', + '8', + 0, + /* 14379 */ '#', + 'D', + 'Y', + 'N', + 'A', + 'R', + 'E', + 'A', + 'O', + 'F', + 'F', + 'S', + 'E', + 'T', + '8', + 0, + /* 14395 */ '#', + 'A', + 'N', + 'D', + 'I', + 'o', + '_', + '1', + '_', + 'E', + 'Q', + '_', + 'B', + 'I', + 'T', + '8', + 0, + /* 14412 */ '#', + 'A', + 'N', + 'D', + 'I', + 'o', + '_', + '1', + '_', + 'G', + 'T', + '_', + 'B', + 'I', + 'T', + '8', + 0, + /* 14429 */ '#', + 'A', + 'T', + 'O', + 'M', + 'I', + 'C', + '_', + 'S', + 'W', + 'A', + 'P', + '_', + 'i', + '8', + 0, + /* 14445 */ '#', + 'A', + 'D', + 'D', + 'I', + 'S', + 't', + 'o', + 'c', + 'H', + 'A', + 0, + /* 14457 */ '#', + 'A', + 'D', + 'D', + 'I', + 'S', + 't', + 'l', + 's', + 'g', + 'd', + 'H', + 'A', + 0, + /* 14471 */ '#', + 'A', + 'D', + 'D', + 'I', + 'S', + 't', + 'l', + 's', + 'l', + 'd', + 'H', + 'A', + 0, + /* 14485 */ '#', + 'A', + 'D', + 'D', + 'I', + 'S', + 'g', + 'o', + 't', + 'T', + 'p', + 'r', + 'e', + 'l', + 'H', + 'A', + 0, + /* 14502 */ '#', + 'A', + 'D', + 'D', + 'I', + 'S', + 'd', + 't', + 'p', + 'r', + 'e', + 'l', + 'H', + 'A', + 0, + /* 14517 */ '#', + 'R', + 'e', + 'a', + 'd', + 'T', + 'B', + 0, + /* 14525 */ '#', + 'D', + 'Y', + 'N', + 'A', + 'L', + 'L', + 'O', + 'C', + 0, + /* 14535 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'Q', + 'B', + 'R', + 'C', + 0, + /* 14551 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'Q', + 'B', + 'R', + 'C', + 0, + /* 14564 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'Q', + 'F', + 'R', + 'C', + 0, + /* 14580 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'Q', + 'F', + 'R', + 'C', + 0, + /* 14593 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'V', + 'S', + 'F', + 'R', + 'C', + 0, + /* 14610 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'V', + 'S', + 'F', + 'R', + 'C', + 0, + /* 14624 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'V', + 'R', + 'R', + 'C', + 0, + /* 14640 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'V', + 'R', + 'R', + 'C', + 0, + /* 14653 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'Q', + 'S', + 'R', + 'C', + 0, + /* 14669 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'Q', + 'S', + 'R', + 'C', + 0, + /* 14682 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'V', + 'S', + 'S', + 'R', + 'C', + 0, + /* 14699 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'V', + 'S', + 'S', + 'R', + 'C', + 0, + /* 14713 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'V', + 'S', + 'R', + 'C', + 0, + /* 14729 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'V', + 'S', + 'R', + 'C', + 0, + /* 14742 */ '#', + 'S', + 'P', + 'I', + 'L', + 'L', + 'T', + 'O', + 'V', + 'S', + 'R', + '_', + 'L', + 'D', + 0, + /* 14757 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'E', + 'N', + 'D', + 0, + /* 14770 */ 'B', + 'U', + 'N', + 'D', + 'L', + 'E', + 0, + /* 14777 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'S', + 'P', + 'E', + 0, + /* 14792 */ '#', + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'S', + 'P', + 'E', + 0, + /* 14804 */ 'D', + 'B', + 'G', + '_', + 'V', + 'A', + 'L', + 'U', + 'E', + 0, + /* 14814 */ '#', + 'R', + 'E', + 'S', + 'T', + 'O', + 'R', + 'E', + '_', + 'V', + 'R', + 'S', + 'A', + 'V', + 'E', + 0, + /* 14830 */ '#', + 'S', + 'P', + 'I', + 'L', + 'L', + '_', + 'V', + 'R', + 'S', + 'A', + 'V', + 'E', + 0, + /* 14844 */ '#', + 'L', + 'D', + 't', + 'o', + 'c', + 'J', + 'T', + 'I', + 0, + /* 14854 */ 'D', + 'B', + 'G', + '_', + 'L', + 'A', + 'B', + 'E', + 'L', + 0, + /* 14864 */ '#', + 'L', + 'D', + 't', + 'o', + 'c', + 'L', + 0, + /* 14872 */ '#', + 'A', + 'D', + 'D', + 'I', + 't', + 'o', + 'c', + 'L', + 0, + /* 14882 */ '#', + 'A', + 'D', + 'D', + 'I', + 't', + 'l', + 's', + 'g', + 'd', + 'L', + 0, + /* 14894 */ '#', + 'A', + 'D', + 'D', + 'I', + 't', + 'l', + 's', + 'l', + 'd', + 'L', + 0, + /* 14906 */ '#', + 'L', + 'D', + 'g', + 'o', + 't', + 'T', + 'p', + 'r', + 'e', + 'l', + 'L', + 0, + /* 14919 */ '#', + 'A', + 'D', + 'D', + 'I', + 'd', + 't', + 'p', + 'r', + 'e', + 'l', + 'L', + 0, + /* 14932 */ '#', + 'U', + 'p', + 'd', + 'a', + 't', + 'e', + 'G', + 'B', + 'R', + 0, + /* 14943 */ '#', + 'R', + 'E', + 'S', + 'T', + 'O', + 'R', + 'E', + '_', + 'C', + 'R', + 0, + /* 14955 */ '#', + 'S', + 'P', + 'I', + 'L', + 'L', + '_', + 'C', + 'R', + 0, + /* 14965 */ '#', + 'A', + 'D', + 'D', + 'I', + 't', + 'l', + 's', + 'g', + 'd', + 'L', + 'A', + 'D', + 'D', + 'R', + 0, + /* 14981 */ '#', + 'A', + 'D', + 'D', + 'I', + 't', + 'l', + 's', + 'l', + 'd', + 'L', + 'A', + 'D', + 'D', + 'R', + 0, + /* 14997 */ '#', + 'G', + 'E', + 'T', + 't', + 'l', + 's', + 'l', + 'd', + 'A', + 'D', + 'D', + 'R', + 0, + /* 15011 */ '#', + 'G', + 'E', + 'T', + 't', + 'l', + 's', + 'A', + 'D', + 'D', + 'R', + 0, + /* 15023 */ '#', + 'M', + 'o', + 'v', + 'e', + 'P', + 'C', + 't', + 'o', + 'L', + 'R', + 0, + /* 15035 */ '#', + 'M', + 'o', + 'v', + 'e', + 'G', + 'O', + 'T', + 't', + 'o', + 'L', + 'R', + 0, + /* 15048 */ '#', + 'T', + 'C', + 'H', + 'E', + 'C', + 'K', + '_', + 'R', + 'E', + 'T', + 0, + /* 15060 */ '#', + 'D', + 'Y', + 'N', + 'A', + 'R', + 'E', + 'A', + 'O', + 'F', + 'F', + 'S', + 'E', + 'T', + 0, + /* 15075 */ '#', + 'R', + 'E', + 'S', + 'T', + 'O', + 'R', + 'E', + '_', + 'C', + 'R', + 'B', + 'I', + 'T', + 0, + /* 15090 */ '#', + 'S', + 'P', + 'I', + 'L', + 'L', + '_', + 'C', + 'R', + 'B', + 'I', + 'T', + 0, + /* 15103 */ '#', + 'A', + 'N', + 'D', + 'I', + 'o', + '_', + '1', + '_', + 'E', + 'Q', + '_', + 'B', + 'I', + 'T', + 0, + /* 15119 */ '#', + 'A', + 'N', + 'D', + 'I', + 'o', + '_', + '1', + '_', + 'G', + 'T', + '_', + 'B', + 'I', + 'T', + 0, + /* 15135 */ '#', + 'P', + 'P', + 'C', + '3', + '2', + 'G', + 'O', + 'T', + 0, + /* 15145 */ '#', + 'P', + 'P', + 'C', + '3', + '2', + 'P', + 'I', + 'C', + 'G', + 'O', + 'T', + 0, + /* 15158 */ '#', + 'L', + 'D', + 't', + 'o', + 'c', + 'C', + 'P', + 'T', + 0, + /* 15168 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'S', + 'T', + 'A', + 'R', + 'T', + 0, + /* 15183 */ '#', + 'S', + 'P', + 'I', + 'L', + 'L', + 'T', + 'O', + 'V', + 'S', + 'R', + '_', + 'S', + 'T', + 0, + /* 15198 */ '#', + 'L', + 'I', + 'W', + 'A', + 'X', + 0, + /* 15205 */ '#', + 'S', + 'P', + 'I', + 'L', + 'L', + 'T', + 'O', + 'V', + 'S', + 'R', + '_', + 'L', + 'D', + 'X', + 0, + /* 15221 */ '#', + 'S', + 'P', + 'I', + 'L', + 'L', + 'T', + 'O', + 'V', + 'S', + 'R', + '_', + 'S', + 'T', + 'X', + 0, + /* 15237 */ '#', + 'S', + 'T', + 'I', + 'W', + 'X', + 0, + /* 15244 */ '#', + 'L', + 'I', + 'W', + 'Z', + 'X', + 0, + /* 15251 */ 'b', + 'c', + 'a', + 0, + /* 15255 */ 's', + 'l', + 'b', + 'i', + 'a', + 0, + /* 15261 */ 't', + 'l', + 'b', + 'i', + 'a', + 0, + /* 15267 */ 'b', + 'c', + 'l', + 'a', + 0, + /* 15272 */ 'c', + 'l', + 'r', + 'b', + 'h', + 'r', + 'b', + 0, + /* 15280 */ 'b', + 'c', + 0, + /* 15283 */ 's', + 'l', + 'b', + 's', + 'y', + 'n', + 'c', + 0, + /* 15291 */ 't', + 'l', + 'b', + 's', + 'y', + 'n', + 'c', + 0, + /* 15299 */ 'm', + 's', + 'g', + 's', + 'y', + 'n', + 'c', + 0, + /* 15307 */ 'i', + 's', + 'y', + 'n', + 'c', + 0, + /* 15313 */ 'm', + 's', + 'y', + 'n', + 'c', + 0, + /* 15319 */ '#', + 'L', + 'D', + 't', + 'o', + 'c', + 0, + /* 15326 */ '#', + 'L', + 'W', + 'Z', + 't', + 'o', + 'c', + 0, + /* 15334 */ 'h', + 'r', + 'f', + 'i', + 'd', + 0, + /* 15340 */ 't', + 'l', + 'b', + 'r', + 'e', + 0, + /* 15346 */ 't', + 'l', + 'b', + 'w', + 'e', + 0, + /* 15352 */ 'r', + 'f', + 'c', + 'i', + 0, + /* 15357 */ 'r', + 'f', + 'm', + 'c', + 'i', + 0, + /* 15363 */ 'r', + 'f', + 'd', + 'i', + 0, + /* 15368 */ 'r', + 'f', + 'i', + 0, + /* 15372 */ 'b', + 'c', + 'l', + 0, + /* 15376 */ '#', + 32, + 'F', + 'E', + 'n', + 't', + 'r', + 'y', + 32, + 'c', + 'a', + 'l', + 'l', + 0, + /* 15390 */ 'd', + 's', + 's', + 'a', + 'l', + 'l', + 0, + /* 15397 */ 'b', + 'l', + 'r', + 'l', + 0, + /* 15402 */ 'b', + 'd', + 'z', + 'l', + 'r', + 'l', + 0, + /* 15409 */ 'b', + 'd', + 'n', + 'z', + 'l', + 'r', + 'l', + 0, + /* 15417 */ 'b', + 'c', + 't', + 'r', + 'l', + 0, + /* 15423 */ 'a', + 't', + 't', + 'n', + 0, + /* 15428 */ 'e', + 'i', + 'e', + 'i', + 'o', + 0, + /* 15434 */ 'n', + 'a', + 'p', + 0, + /* 15438 */ 't', + 'r', + 'a', + 'p', + 0, + /* 15443 */ 'n', + 'o', + 'p', + 0, + /* 15447 */ 's', + 't', + 'o', + 'p', + 0, + /* 15452 */ 'b', + 'l', + 'r', + 0, + /* 15456 */ 'b', + 'd', + 'z', + 'l', + 'r', + 0, + /* 15462 */ 'b', + 'd', + 'n', + 'z', + 'l', + 'r', + 0, + /* 15469 */ 'b', + 'c', + 't', + 'r', + 0, + /* 15474 */ 'c', + 'p', + '_', + 'a', + 'b', + 'o', + 'r', + 't', + 0, }; #endif static const uint32_t OpInfo0[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 14805U, // DBG_VALUE - 14855U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 14771U, // BUNDLE - 15169U, // LIFETIME_START - 14758U, // LIFETIME_END - 0U, // STACKMAP - 15377U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 12827U, // PATCHABLE_FUNCTION_ENTER - 12747U, // PATCHABLE_RET - 12873U, // PATCHABLE_FUNCTION_EXIT - 12850U, // PATCHABLE_TAIL_CALL - 12802U, // PATCHABLE_EVENT_CALL - 12778U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDE - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SSUBO - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_BSWAP - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 14087U, // CFENCE8 - 21042U, // CLRLSLDI - 17211U, // CLRLSLDIo - 21551U, // CLRLSLWI - 17320U, // CLRLSLWIo - 21077U, // CLRRDI - 17238U, // CLRRDIo - 21592U, // CLRRWI - 17349U, // CLRRWIo - 536897109U, // CP_COPY_FIRST - 536899711U, // CP_COPYx - 536897058U, // CP_PASTE_LAST - 536891262U, // CP_PASTEx - 562481U, // DCBFL - 564336U, // DCBFLP - 561067U, // DCBFx - 553690475U, // DCBTCT - 553689756U, // DCBTDS - 553690483U, // DCBTSTCT - 553689764U, // DCBTSTDS - 566909U, // DCBTSTT - 566881U, // DCBTSTx - 566896U, // DCBTT - 566623U, // DCBTx - 13334U, // DFLOADf32 - 13646U, // DFLOADf64 - 13356U, // DFSTOREf32 - 13668U, // DFSTOREf64 - 21052U, // EXTLDI - 17222U, // EXTLDIo - 21577U, // EXTLWI - 17340U, // EXTLWIo - 21101U, // EXTRDI - 17265U, // EXTRDIo - 21616U, // EXTRWI - 17376U, // EXTRWIo - 21561U, // INSLWI - 17331U, // INSLWIo - 21085U, // INSRDI - 17247U, // INSRDIo - 21600U, // INSRWI - 17358U, // INSRWIo - 33573242U, // LAx - 15199U, // LIWAX - 15245U, // LIWZX - 21205U, // RLWIMIbm - 17303U, // RLWIMIobm - 22102U, // RLWINMbm - 17434U, // RLWINMobm - 22111U, // RLWNMbm - 17443U, // RLWNMobm - 21093U, // ROTRDI - 17256U, // ROTRDIo - 21608U, // ROTRWI - 17367U, // ROTRWIo - 21046U, // SLDI - 17215U, // SLDIo - 21555U, // SLWI - 17324U, // SLWIo - 14743U, // SPILLTOVSR_LD - 15206U, // SPILLTOVSR_LDX - 15184U, // SPILLTOVSR_ST - 15222U, // SPILLTOVSR_STX - 21087U, // SRDI - 17249U, // SRDIo - 21602U, // SRWI - 17360U, // SRWIo - 15238U, // STIWX - 20993U, // SUBI - 19522U, // SUBIC - 16795U, // SUBICo - 25475U, // SUBIS - 50357130U, // SUBPCIS - 13345U, // XFLOADf32 - 13657U, // XFLOADf64 - 13368U, // XFSTOREf32 - 13680U, // XFSTOREf64 - 19705U, // ADD4 - 19705U, // ADD4TLS - 16867U, // ADD4o - 19705U, // ADD8 - 19705U, // ADD8TLS - 19705U, // ADD8TLS_ - 16867U, // ADD8o - 19484U, // ADDC - 19484U, // ADDC8 - 16762U, // ADDC8o - 16762U, // ADDCo - 20235U, // ADDE - 20235U, // ADDE8 - 17006U, // ADDE8o - 17006U, // ADDEo - 21028U, // ADDI - 21028U, // ADDI8 - 19529U, // ADDIC - 19529U, // ADDIC8 - 16803U, // ADDICo - 25500U, // ADDIS - 25500U, // ADDIS8 - 14503U, // ADDISdtprelHA - 12929U, // ADDISdtprelHA32 - 14486U, // ADDISgotTprelHA - 14458U, // ADDIStlsgdHA - 14472U, // ADDIStlsldHA - 14446U, // ADDIStocHA - 14920U, // ADDIdtprelL - 13218U, // ADDIdtprelL32 - 14883U, // ADDItlsgdL - 13175U, // ADDItlsgdL32 - 14966U, // ADDItlsgdLADDR - 13270U, // ADDItlsgdLADDR32 - 14895U, // ADDItlsldL - 13189U, // ADDItlsldL32 - 14982U, // ADDItlsldLADDR - 13288U, // ADDItlsldLADDR32 - 14873U, // ADDItocL - 536891214U, // ADDME - 536891214U, // ADDME8 - 536887941U, // ADDME8o - 536887941U, // ADDMEo - 536896403U, // ADDPCIS - 536891292U, // ADDZE - 536891292U, // ADDZE8 - 536887990U, // ADDZE8o - 536887990U, // ADDZEo - 51111U, // ADJCALLSTACKDOWN - 51130U, // ADJCALLSTACKUP - 19976U, // AND - 19976U, // AND8 - 16929U, // AND8o - 19493U, // ANDC - 19493U, // ANDC8 - 16769U, // ANDC8o - 16769U, // ANDCo - 17833U, // ANDISo - 17833U, // ANDISo8 - 17231U, // ANDIo - 17231U, // ANDIo8 - 15104U, // ANDIo_1_EQ_BIT - 14396U, // ANDIo_1_EQ_BIT8 - 15120U, // ANDIo_1_GT_BIT - 14413U, // ANDIo_1_GT_BIT8 - 16929U, // ANDo - 1141917528U, // ATOMIC_CMP_SWAP_I16 - 1141917506U, // ATOMIC_CMP_SWAP_I32 - 13504U, // ATOMIC_CMP_SWAP_I64 - 14257U, // ATOMIC_CMP_SWAP_I8 - 13868U, // ATOMIC_LOAD_ADD_I16 - 12967U, // ATOMIC_LOAD_ADD_I32 - 13401U, // ATOMIC_LOAD_ADD_I64 - 14155U, // ATOMIC_LOAD_ADD_I8 - 13911U, // ATOMIC_LOAD_AND_I16 - 13010U, // ATOMIC_LOAD_AND_I32 - 13692U, // ATOMIC_LOAD_AND_I64 - 14196U, // ATOMIC_LOAD_AND_I8 - 14055U, // ATOMIC_LOAD_MAX_I16 - 13154U, // ATOMIC_LOAD_MAX_I32 - 13588U, // ATOMIC_LOAD_MAX_I64 - 14347U, // ATOMIC_LOAD_MAX_I8 - 13954U, // ATOMIC_LOAD_MIN_I16 - 13053U, // ATOMIC_LOAD_MIN_I32 - 13466U, // ATOMIC_LOAD_MIN_I64 - 14237U, // ATOMIC_LOAD_MIN_I8 - 13889U, // ATOMIC_LOAD_NAND_I16 - 12988U, // ATOMIC_LOAD_NAND_I32 - 13422U, // ATOMIC_LOAD_NAND_I64 - 14175U, // ATOMIC_LOAD_NAND_I8 - 14013U, // ATOMIC_LOAD_OR_I16 - 13112U, // ATOMIC_LOAD_OR_I32 - 13546U, // ATOMIC_LOAD_OR_I64 - 14296U, // ATOMIC_LOAD_OR_I8 - 13847U, // ATOMIC_LOAD_SUB_I16 - 12946U, // ATOMIC_LOAD_SUB_I32 - 13380U, // ATOMIC_LOAD_SUB_I64 - 14121U, // ATOMIC_LOAD_SUB_I8 - 14033U, // ATOMIC_LOAD_UMAX_I16 - 13132U, // ATOMIC_LOAD_UMAX_I32 - 13566U, // ATOMIC_LOAD_UMAX_I64 - 14326U, // ATOMIC_LOAD_UMAX_I8 - 13932U, // ATOMIC_LOAD_UMIN_I16 - 13031U, // ATOMIC_LOAD_UMIN_I32 - 13444U, // ATOMIC_LOAD_UMIN_I64 - 14216U, // ATOMIC_LOAD_UMIN_I8 - 13992U, // ATOMIC_LOAD_XOR_I16 - 13091U, // ATOMIC_LOAD_XOR_I32 - 13525U, // ATOMIC_LOAD_XOR_I64 - 14277U, // ATOMIC_LOAD_XOR_I8 - 13975U, // ATOMIC_SWAP_I16 - 13074U, // ATOMIC_SWAP_I32 - 13487U, // ATOMIC_SWAP_I64 - 14430U, // ATOMIC_SWAP_I8 - 15424U, // ATTN - 592514U, // B - 608340U, // BA - 83902568U, // BC - 1686447U, // BCC - 2210735U, // BCCA - 2735023U, // BCCCTR - 2735023U, // BCCCTR8 - 3259311U, // BCCCTRL - 3259311U, // BCCCTRL8 - 3783599U, // BCCL - 4307887U, // BCCLA - 4832175U, // BCCLR - 5356463U, // BCCLRL - 5783706U, // BCCTR - 5783706U, // BCCTR8 - 5783762U, // BCCTR8n - 5783684U, // BCCTRL - 5783684U, // BCCTRL8 - 5783742U, // BCCTRL8n - 5783742U, // BCCTRLn - 5783762U, // BCCTRn - 17451U, // BCDCFNo - 17654U, // BCDCFSQo - 18172U, // BCDCFZo - 17460U, // BCDCPSGNo - 536888420U, // BCDCTNo - 536888576U, // BCDCTSQo - 18188U, // BCDCTZo - 17480U, // BCDSETSGNo - 17709U, // BCDSRo - 17765U, // BCDSo - 16819U, // BCDTRUNCo - 17858U, // BCDUSo - 16830U, // BCDUTRUNCo - 83902576U, // BCL - 5783696U, // BCLR - 5783673U, // BCLRL - 5783732U, // BCLRLn - 5783753U, // BCLRn - 589901U, // BCLalways - 83902636U, // BCLn - 15470U, // BCTR - 15470U, // BCTR8 - 15418U, // BCTRL - 15418U, // BCTRL8 - 114778U, // BCTRL8_LDinto_toc - 83902629U, // BCn - 602413U, // BDNZ - 602413U, // BDNZ8 - 608887U, // BDNZA - 606464U, // BDNZAm - 606249U, // BDNZAp - 595380U, // BDNZL - 608651U, // BDNZLA - 606448U, // BDNZLAm - 606233U, // BDNZLAp - 15463U, // BDNZLR - 15463U, // BDNZLR8 - 15410U, // BDNZLRL - 12723U, // BDNZLRLm - 12680U, // BDNZLRLp - 12739U, // BDNZLRm - 12696U, // BDNZLRp - 590095U, // BDNZLm - 589880U, // BDNZLp - 590109U, // BDNZm - 589894U, // BDNZp - 602256U, // BDZ - 602256U, // BDZ8 - 608881U, // BDZA - 606457U, // BDZAm - 606242U, // BDZAp - 595374U, // BDZL - 608644U, // BDZLA - 606440U, // BDZLAm - 606225U, // BDZLAp - 15457U, // BDZLR - 15457U, // BDZLR8 - 15403U, // BDZLRL - 12715U, // BDZLRLm - 12672U, // BDZLRLp - 12732U, // BDZLRm - 12689U, // BDZLRp - 590088U, // BDZLm - 589873U, // BDZLp - 590103U, // BDZm - 589888U, // BDZp - 595190U, // BL - 595190U, // BL8 - 6362358U, // BL8_NOP - 6427894U, // BL8_NOP_TLS - 660726U, // BL8_TLS - 660726U, // BL8_TLS_ - 608633U, // BLA - 608633U, // BLA8 - 6375801U, // BLA8_NOP - 15453U, // BLR - 15453U, // BLR8 - 15398U, // BLRL - 660726U, // BL_TLS - 19956U, // BPERMD - 19585U, // BRINC - 15273U, // CLRBHRB - 19160U, // CMPB - 19160U, // CMPB8 - 20020U, // CMPD - 21070U, // CMPDI - 19166U, // CMPEQB - 19927U, // CMPLD - 21034U, // CMPLDI - 27069U, // CMPLW - 21535U, // CMPLWI - 100682470U, // CMPRB - 100682470U, // CMPRB8 - 27326U, // CMPW - 21585U, // CMPWI - 536891107U, // CNTLZD - 536887900U, // CNTLZDo - 536898560U, // CNTLZW - 536898560U, // CNTLZW8 - 536889017U, // CNTLZW8o - 536889017U, // CNTLZWo - 536891122U, // CNTTZD - 536887909U, // CNTTZDo - 536898575U, // CNTTZW - 536898575U, // CNTTZW8 - 536889026U, // CNTTZW8o - 536889026U, // CNTTZWo - 15475U, // CP_ABORT - 28799U, // CP_COPY - 28799U, // CP_COPY8 - 20350U, // CP_PASTE - 20350U, // CP_PASTE8 - 17062U, // CP_PASTE8o - 17062U, // CP_PASTEo - 13806U, // CR6SET - 13792U, // CR6UNSET - 20006U, // CRAND - 19499U, // CRANDC - 26534U, // CREQV - 19990U, // CRNAND - 24864U, // CRNOR - 24878U, // CROR - 19606U, // CRORC - 117467046U, // CRSET - 117465420U, // CRUNSET - 24908U, // CRXOR - 1686447U, // CTRL_DEP - 536893342U, // DARN - 559186U, // DCBA - 151467U, // DCBF - 564087U, // DCBFEP - 561653U, // DCBI - 566857U, // DCBST - 564120U, // DCBSTEP - 157023U, // DCBT - 170896U, // DCBTEP - 157281U, // DCBTST - 170913U, // DCBTSTEP - 569477U, // DCBZ - 564139U, // DCBZEP - 562599U, // DCBZL - 564103U, // DCBZLEP - 536891911U, // DCCCI - 20182U, // DIVD - 20241U, // DIVDE - 26334U, // DIVDEU - 17936U, // DIVDEUo - 17013U, // DIVDEo - 26327U, // DIVDU - 17928U, // DIVDUo - 16981U, // DIVDo - 27623U, // DIVW - 20364U, // DIVWE - 26342U, // DIVWEU - 17945U, // DIVWEUo - 17070U, // DIVWEo - 26448U, // DIVWU - 17972U, // DIVWUo - 18087U, // DIVWo - 713696U, // DSS - 15391U, // DSSALL - 1745036880U, // DST - 1745036880U, // DST64 - 1745036905U, // DSTST - 1745036905U, // DSTST64 - 1745036934U, // DSTSTT - 1745036934U, // DSTSTT64 - 1745036919U, // DSTT - 1745036919U, // DSTT64 - 14526U, // DYNALLOC - 14076U, // DYNALLOC8 - 15061U, // DYNAREAOFFSET - 14380U, // DYNAREAOFFSET8 - 536895901U, // EFDABS - 19702U, // EFDADD - 536896266U, // EFDCFS - 536891387U, // EFDCFSF - 536892298U, // EFDCFSI - 536890788U, // EFDCFSID - 536891489U, // EFDCFUF - 536892375U, // EFDCFUI - 536890807U, // EFDCFUID - 24525U, // EFDCMPEQ - 25981U, // EFDCMPGT - 26059U, // EFDCMPLT - 536891461U, // EFDCTSF - 536892326U, // EFDCTSI - 536899733U, // EFDCTSIDZ - 536899834U, // EFDCTSIZ - 536891517U, // EFDCTUF - 536892403U, // EFDCTUI - 536899754U, // EFDCTUIDZ - 536899865U, // EFDCTUIZ - 26482U, // EFDDIV - 21859U, // EFDMUL - 536895917U, // EFDNABS - 536891543U, // EFDNEG - 19374U, // EFDSUB - 24575U, // EFDTSTEQ - 26022U, // EFDTSTGT - 26100U, // EFDTSTLT - 536895954U, // EFSABS - 19785U, // EFSADD - 536890738U, // EFSCFD - 536891396U, // EFSCFSF - 536892307U, // EFSCFSI - 536891498U, // EFSCFUF - 536892384U, // EFSCFUI - 24545U, // EFSCMPEQ - 26001U, // EFSCMPGT - 26079U, // EFSCMPLT - 536891470U, // EFSCTSF - 536892335U, // EFSCTSI - 536899844U, // EFSCTSIZ - 536891526U, // EFSCTUF - 536892412U, // EFSCTUI - 536899875U, // EFSCTUIZ - 26496U, // EFSDIV - 21875U, // EFSMUL - 536895935U, // EFSNABS - 536891559U, // EFSNEG - 19409U, // EFSSUB - 24585U, // EFSTSTEQ - 26032U, // EFSTSTGT - 26110U, // EFSTSTLT - 13233U, // EH_SjLj_LongJmp32 - 13609U, // EH_SjLj_LongJmp64 - 13252U, // EH_SjLj_SetJmp32 - 13628U, // EH_SjLj_SetJmp64 - 589825U, // EH_SjLj_Setup - 26529U, // EQV - 26529U, // EQV8 - 17987U, // EQV8o - 17987U, // EQVo - 536895971U, // EVABS - 16804243U, // EVADDIW - 536897549U, // EVADDSMIAAW - 536897681U, // EVADDSSIAAW - 536897615U, // EVADDUMIAAW - 536897747U, // EVADDUSIAAW - 26929U, // EVADDW - 20013U, // EVAND - 19507U, // EVANDC - 24566U, // EVCMPEQ - 25591U, // EVCMPGTS - 26394U, // EVCMPGTU - 25601U, // EVCMPLTS - 26404U, // EVCMPLTU - 536898309U, // EVCNTLSW - 536898558U, // EVCNTLZW - 25763U, // EVDIVWS - 26446U, // EVDIVWU - 26541U, // EVEQV - 536890171U, // EVEXTSB - 536891736U, // EVEXTSH - 536895962U, // EVFSABS - 19793U, // EVFSADD - 536891405U, // EVFSCFSF - 536892316U, // EVFSCFSI - 536891507U, // EVFSCFUF - 536892393U, // EVFSCFUI - 24555U, // EVFSCMPEQ - 26011U, // EVFSCMPGT - 26089U, // EVFSCMPLT - 536891479U, // EVFSCTSF - 536892344U, // EVFSCTSI - 536899854U, // EVFSCTSIZ - 536891479U, // EVFSCTUF - 536892421U, // EVFSCTUI - 536899854U, // EVFSCTUIZ - 26504U, // EVFSDIV - 21883U, // EVFSMUL - 536895944U, // EVFSNABS - 536891567U, // EVFSNEG - 19417U, // EVFSSUB - 24595U, // EVFSTSTEQ - 26042U, // EVFSTSTGT - 26120U, // EVFSTSTLT - 33574234U, // EVLDD - 604007606U, // EVLDDX - 33575110U, // EVLDH - 604007710U, // EVLDHX - 33581369U, // EVLDW - 604008463U, // EVLDWX - 33580305U, // EVLHHESPLAT - 604008203U, // EVLHHESPLATX - 33580330U, // EVLHHOSSPLAT - 604008230U, // EVLHHOSSPLATX - 33580344U, // EVLHHOUSPLAT - 604008245U, // EVLHHOUSPLATX - 33574703U, // EVLWHE - 604007681U, // EVLWHEX - 33579987U, // EVLWHOS - 604008175U, // EVLWHOSX - 33580797U, // EVLWHOU - 604008361U, // EVLWHOUX - 33580318U, // EVLWHSPLAT - 604008217U, // EVLWHSPLATX - 33580358U, // EVLWWSPLAT - 604008260U, // EVLWWSPLATX - 21141U, // EVMERGEHI - 22475U, // EVMERGEHILO - 22464U, // EVMERGELO - 21152U, // EVMERGELOHI - 18392U, // EVMHEGSMFAA - 22234U, // EVMHEGSMFAN - 18440U, // EVMHEGSMIAA - 22282U, // EVMHEGSMIAN - 18477U, // EVMHEGUMIAA - 22319U, // EVMHEGUMIAN - 20407U, // EVMHESMF - 18525U, // EVMHESMFA - 26585U, // EVMHESMFAAW - 27110U, // EVMHESMFANW - 21213U, // EVMHESMI - 18616U, // EVMHESMIA - 26650U, // EVMHESMIAAW - 27162U, // EVMHESMIANW - 20510U, // EVMHESSF - 18568U, // EVMHESSFA - 26611U, // EVMHESSFAAW - 27136U, // EVMHESSFANW - 26782U, // EVMHESSIAAW - 27240U, // EVMHESSIANW - 21252U, // EVMHEUMI - 18659U, // EVMHEUMIA - 26716U, // EVMHEUMIAAW - 27201U, // EVMHEUMIANW - 26848U, // EVMHEUSIAAW - 27279U, // EVMHEUSIANW - 18405U, // EVMHOGSMFAA - 22247U, // EVMHOGSMFAN - 18453U, // EVMHOGSMIAA - 22295U, // EVMHOGSMIAN - 18490U, // EVMHOGUMIAA - 22332U, // EVMHOGUMIAN - 20427U, // EVMHOSMF - 18547U, // EVMHOSMFA - 26598U, // EVMHOSMFAAW - 27123U, // EVMHOSMFANW - 21233U, // EVMHOSMI - 18638U, // EVMHOSMIA - 26690U, // EVMHOSMIAAW - 27188U, // EVMHOSMIANW - 20530U, // EVMHOSSF - 18590U, // EVMHOSSFA - 26624U, // EVMHOSSFAAW - 27149U, // EVMHOSSFANW - 26822U, // EVMHOSSIAAW - 27266U, // EVMHOSSIANW - 21282U, // EVMHOUMI - 18692U, // EVMHOUMIA - 26756U, // EVMHOUMIAAW - 27227U, // EVMHOUMIANW - 26888U, // EVMHOUSIAAW - 27305U, // EVMHOUSIANW - 536889747U, // EVMRA - 20417U, // EVMWHSMF - 18536U, // EVMWHSMFA - 21223U, // EVMWHSMI - 18627U, // EVMWHSMIA - 20520U, // EVMWHSSF - 18579U, // EVMWHSSFA - 21262U, // EVMWHUMI - 18670U, // EVMWHUMIA - 26677U, // EVMWLSMIAAW - 27175U, // EVMWLSMIANW - 26809U, // EVMWLSSIAAW - 27253U, // EVMWLSSIANW - 21272U, // EVMWLUMI - 18681U, // EVMWLUMIA - 26743U, // EVMWLUMIAAW - 27214U, // EVMWLUMIANW - 26875U, // EVMWLUSIAAW - 27292U, // EVMWLUSIANW - 20437U, // EVMWSMF - 18558U, // EVMWSMFA - 18418U, // EVMWSMFAA - 22260U, // EVMWSMFAN - 21243U, // EVMWSMI - 18649U, // EVMWSMIA - 18466U, // EVMWSMIAA - 22308U, // EVMWSMIAN - 20540U, // EVMWSSF - 18601U, // EVMWSSFA - 18429U, // EVMWSSFAA - 22271U, // EVMWSSFAN - 21292U, // EVMWUMI - 18703U, // EVMWUMIA - 18503U, // EVMWUMIAA - 22345U, // EVMWUMIAN - 19998U, // EVNAND - 536891576U, // EVNEG - 24871U, // EVNOR - 24884U, // EVOR - 19613U, // EVORC - 27076U, // EVRLW - 21543U, // EVRLWI - 536897856U, // EVRNDW - 2154328480U, // EVSEL - 27083U, // EVSLW - 21569U, // EVSLWI - 151016074U, // EVSPLATFI - 151016397U, // EVSPLATI - 25519U, // EVSRWIS - 26356U, // EVSRWIU - 25691U, // EVSRWS - 26432U, // EVSRWU - 33574250U, // EVSTDD - 604007614U, // EVSTDDX - 33575117U, // EVSTDH - 604007718U, // EVSTDHX - 33581384U, // EVSTDW - 604008471U, // EVSTDWX - 33574711U, // EVSTWHE - 604007690U, // EVSTWHEX - 33576887U, // EVSTWHO - 604007872U, // EVSTWHOX - 33574803U, // EVSTWWE - 604007700U, // EVSTWWEX - 33577040U, // EVSTWWO - 604007882U, // EVSTWWOX - 536897575U, // EVSUBFSMIAAW - 536897707U, // EVSUBFSSIAAW - 536897641U, // EVSUBFUMIAAW - 536897773U, // EVSUBFUSIAAW - 26977U, // EVSUBFW - 167799146U, // EVSUBIFW - 24915U, // EVXOR - 536890173U, // EXTSB - 536890173U, // EXTSB8 - 536890173U, // EXTSB8_32_64 - 536887609U, // EXTSB8o - 536887609U, // EXTSBo - 536891738U, // EXTSH - 536891738U, // EXTSH8 - 536891738U, // EXTSH8_32_64 - 536888050U, // EXTSH8o - 536888050U, // EXTSHo - 536898346U, // EXTSW - 21179U, // EXTSWSLI - 17283U, // EXTSWSLIo - 536898346U, // EXTSW_32 - 536898346U, // EXTSW_32_64 - 536888969U, // EXTSW_32_64o - 536888969U, // EXTSWo - 15429U, // EnforceIEIO - 536895911U, // FABSD - 536888635U, // FABSDo - 536895911U, // FABSS - 536888635U, // FABSSo - 19712U, // FADD - 25154U, // FADDS - 17772U, // FADDSo - 16866U, // FADDo - 0U, // FADDrtz - 536890781U, // FCFID - 536896148U, // FCFIDS - 536888711U, // FCFIDSo - 536897210U, // FCFIDU - 536896533U, // FCFIDUS - 536888778U, // FCFIDUSo - 536888822U, // FCFIDUo - 536887810U, // FCFIDo - 26374U, // FCMPUD - 26374U, // FCMPUS - 22369U, // FCPSGND - 17471U, // FCPSGNDo - 22369U, // FCPSGNS - 17471U, // FCPSGNSo - 536890800U, // FCTID - 536897220U, // FCTIDU - 536899893U, // FCTIDUZ - 536889109U, // FCTIDUZo - 536888831U, // FCTIDUo - 536899746U, // FCTIDZ - 536889075U, // FCTIDZo - 536887818U, // FCTIDo - 536897950U, // FCTIW - 536897336U, // FCTIWU - 536899904U, // FCTIWUZ - 536889119U, // FCTIWUZo - 536888875U, // FCTIWUo - 536899915U, // FCTIWZ - 536889129U, // FCTIWZo - 536888930U, // FCTIWo - 26490U, // FDIV - 25684U, // FDIVS - 17876U, // FDIVSo - 17980U, // FDIVo - 19720U, // FMADD - 25163U, // FMADDS - 17780U, // FMADDSo - 16873U, // FMADDo - 536895725U, // FMR - 536888603U, // FMRo - 19392U, // FMSUB - 25133U, // FMSUBS - 17746U, // FMSUBSo - 16723U, // FMSUBo - 21869U, // FMUL - 25538U, // FMULS - 17841U, // FMULSo - 17409U, // FMULo - 536895928U, // FNABSD - 536888642U, // FNABSDo - 536895928U, // FNABSS - 536888642U, // FNABSSo - 536891553U, // FNEGD - 536888022U, // FNEGDo - 536891553U, // FNEGS - 536888022U, // FNEGSo - 19729U, // FNMADD - 25173U, // FNMADDS - 17789U, // FNMADDSo - 16881U, // FNMADDo - 19401U, // FNMSUB - 25143U, // FNMSUBS - 17755U, // FNMSUBSo - 16731U, // FNMSUBo - 536891238U, // FRE - 536896248U, // FRES - 536888720U, // FRESo - 536887958U, // FREo - 536893000U, // FRIMD - 536888339U, // FRIMDo - 536893000U, // FRIMS - 536888339U, // FRIMSo - 536893298U, // FRIND - 536888413U, // FRINDo - 536893298U, // FRINS - 536888413U, // FRINSo - 536894570U, // FRIPD - 536888508U, // FRIPDo - 536894570U, // FRIPS - 536888508U, // FRIPSo - 536899828U, // FRIZD - 536889093U, // FRIZDo - 536899828U, // FRIZS - 536889093U, // FRIZSo - 536895271U, // FRSP - 536888539U, // FRSPo - 536891253U, // FRSQRTE - 536896256U, // FRSQRTES - 536888727U, // FRSQRTESo - 536887964U, // FRSQRTEo - 21784U, // FSELD - 17402U, // FSELDo - 21784U, // FSELS - 17402U, // FSELSo - 536897043U, // FSQRT - 536896523U, // FSQRTS - 536888761U, // FSQRTSo - 536888805U, // FSQRTo - 19384U, // FSUB - 25124U, // FSUBS - 17738U, // FSUBSo - 16716U, // FSUBo - 26513U, // FTDIV - 536897050U, // FTSQRT - 15012U, // GETtlsADDR - 13321U, // GETtlsADDR32 - 14998U, // GETtlsldADDR - 13306U, // GETtlsldADDR32 - 15335U, // HRFID - 561659U, // ICBI - 564095U, // ICBIEP - 216186U, // ICBLC - 214254U, // ICBLQ - 222565U, // ICBT - 222136U, // ICBTLS - 536891918U, // ICCCI - 21790U, // ISEL - 21790U, // ISEL8 - 15308U, // ISYNC - 184568186U, // LA - 604007996U, // LBARX - 2751491644U, // LBARXL - 604007892U, // LBEPX - 33583243U, // LBZ - 33583243U, // LBZ8 - 28020U, // LBZCIX - 201353047U, // LBZU - 201353047U, // LBZU8 - 218132450U, // LBZUX - 218132450U, // LBZUX8 - 604008529U, // LBZX - 604008529U, // LBZX8 - 28753U, // LBZXTLS - 28753U, // LBZXTLS_ - 28753U, // LBZXTLS_32 - 33574340U, // LD - 604008003U, // LDARX - 2751491651U, // LDARXL - 25860U, // LDAT - 604008024U, // LDBRX - 27989U, // LDCIX - 604007859U, // LDMX - 201352908U, // LDU - 218132366U, // LDUX - 604007645U, // LDX - 27869U, // LDXTLS - 27869U, // LDXTLS_ - 14907U, // LDgotTprelL - 13203U, // LDgotTprelL32 - 15320U, // LDtoc - 15159U, // LDtocBA - 15159U, // LDtocCPT - 14845U, // LDtocJTI - 14865U, // LDtocL - 33574266U, // LFD - 604007907U, // LFDEPX - 201352858U, // LFDU - 218132349U, // LFDUX - 604007625U, // LFDX - 604007534U, // LFIWAX - 604008552U, // LFIWZX - 33579800U, // LFS - 201352973U, // LFSU - 218132426U, // LFSUX - 604008150U, // LFSX - 33573043U, // LHA - 33573043U, // LHA8 - 604008010U, // LHARX - 2751491658U, // LHARXL - 201352846U, // LHAU - 201352846U, // LHAU8 - 218132305U, // LHAUX - 218132305U, // LHAUX8 - 604007517U, // LHAX - 604007517U, // LHAX8 - 604008039U, // LHBRX - 604008039U, // LHBRX8 - 604007924U, // LHEPX - 33583307U, // LHZ - 33583307U, // LHZ8 - 28028U, // LHZCIX - 201353053U, // LHZU - 201353053U, // LHZU8 - 218132457U, // LHZUX - 218132457U, // LHZUX8 - 604008544U, // LHZX - 604008544U, // LHZX8 - 28768U, // LHZXTLS - 28768U, // LHZXTLS_ - 28768U, // LHZXTLS_32 - 50352816U, // LI - 50352816U, // LI8 - 50357155U, // LIS - 50357155U, // LIS8 - 33581522U, // LMW - 21624U, // LSWI - 604007557U, // LVEBX - 604007727U, // LVEHX - 604008480U, // LVEWX - 604001629U, // LVSL - 604004738U, // LVSR - 604008439U, // LVX - 604001690U, // LVXL - 33573274U, // LWA - 604008017U, // LWARX - 2751491665U, // LWARXL - 25938U, // LWAT - 218132312U, // LWAUX - 604007551U, // LWAX - 604007551U, // LWAX_32 - 33573274U, // LWA_32 - 604008064U, // LWBRX - 604008064U, // LWBRX8 - 604007939U, // LWEPX - 33583443U, // LWZ - 33583443U, // LWZ8 - 28036U, // LWZCIX - 201353059U, // LWZU - 201353059U, // LWZU8 - 218132464U, // LWZUX - 218132464U, // LWZUX8 - 604008569U, // LWZX - 604008569U, // LWZX8 - 28793U, // LWZXTLS - 28793U, // LWZXTLS_ - 28793U, // LWZXTLS_32 - 15327U, // LWZtoc - 33574522U, // LXSD - 604007660U, // LXSDX - 604008520U, // LXSIBZX - 604008535U, // LXSIHZX - 604007542U, // LXSIWAX - 604008560U, // LXSIWZX - 33578823U, // LXSSP - 604007979U, // LXSSPX - 33580986U, // LXV - 604007481U, // LXVB16X - 604007447U, // LXVD2X - 604008133U, // LXVDSX - 604007500U, // LXVH8X - 21901U, // LXVL - 21816U, // LXVLL - 604007464U, // LXVW4X - 604008195U, // LXVWSX - 604008450U, // LXVX - 19852U, // MADDHD - 26279U, // MADDHDU - 19912U, // MADDLD - 712845U, // MBAR - 536891358U, // MCRF - 536896285U, // MCRFS - 552611U, // MCRXRX - 234901242U, // MFBHRBE - 549032U, // MFCR - 549032U, // MFCR8 - 549263U, // MFCTR - 549263U, // MFCTR8 - 536895635U, // MFDCR - 549650U, // MFFS - 536893357U, // MFFSCDRN - 251679569U, // MFFSCDRNI - 544515U, // MFFSCE - 536893348U, // MFFSCRN - 268456775U, // MFFSCRNI - 546134U, // MFFSL - 542114U, // MFFSo - 549087U, // MFLR - 549087U, // MFLR8 - 549230U, // MFMSR - 285233124U, // MFOCRF - 285233124U, // MFOCRF8 - 536895730U, // MFPMR - 536895834U, // MFSPR - 536895834U, // MFSPR8 - 302014824U, // MFSR - 536893304U, // MFSRIN - 536890194U, // MFTB - 7364954U, // MFTB8 - 536890953U, // MFVRD - 7889242U, // MFVRSAVE - 7889242U, // MFVRSAVEv - 549046U, // MFVSCR - 536890953U, // MFVSRD - 536890846U, // MFVSRLD - 536899928U, // MFVSRWZ - 20057U, // MODSD - 27345U, // MODSW - 20139U, // MODUD - 27520U, // MODUW - 15300U, // MSGSYNC - 15314U, // MSYNC - 536891380U, // MTCRF - 536891380U, // MTCRF8 - 549270U, // MTCTR - 549270U, // MTCTR8 - 549270U, // MTCTR8loop - 549270U, // MTCTRloop - 654516385U, // MTDCR - 706354U, // MTFSB0 - 706362U, // MTFSB1 - 20503U, // MTFSF - 21122U, // MTFSFI - 17274U, // MTFSFIo - 536891415U, // MTFSFb - 17102U, // MTFSFo - 549093U, // MTLR - 549093U, // MTLR8 - 536895861U, // MTMSR - 536890945U, // MTMSRD - 233452U, // MTOCRF - 233452U, // MTOCRF8 - 536895737U, // MTPMR - 536895841U, // MTSPR - 536895841U, // MTSPR8 - 254332U, // MTSR - 536893312U, // MTSRIN - 540892U, // MTVRSAVE - 721116U, // MTVRSAVEv - 549054U, // MTVSCR - 536890961U, // MTVSRD - 19809U, // MTVSRDD - 536889759U, // MTVSRWA - 536896611U, // MTVSRWS - 536899937U, // MTVSRWZ - 19860U, // MULHD - 26288U, // MULHDU - 17901U, // MULHDUo - 16890U, // MULHDo - 27020U, // MULHW - 26414U, // MULHWU - 17954U, // MULHWUo - 18010U, // MULHWo - 19920U, // MULLD - 16914U, // MULLDo - 21172U, // MULLI - 21172U, // MULLI8 - 27062U, // MULLW - 18026U, // MULLWo - 15036U, // MoveGOTtoLR - 15024U, // MovePCtoLR - 14367U, // MovePCtoLR8 - 19984U, // NAND - 19984U, // NAND8 - 16928U, // NAND8o - 16928U, // NANDo - 15435U, // NAP - 536891546U, // NEG - 536891546U, // NEG8 - 536888023U, // NEG8o - 536888023U, // NEGo - 15444U, // NOP - 12905U, // NOP_GT_PWR6 - 12917U, // NOP_GT_PWR7 - 24859U, // NOR - 24859U, // NOR8 - 17697U, // NOR8o - 17697U, // NORo - 24852U, // OR - 24852U, // OR8 - 17698U, // OR8o - 19601U, // ORC - 19601U, // ORC8 - 16842U, // ORC8o - 16842U, // ORCo - 21381U, // ORI - 21381U, // ORI8 - 25513U, // ORIS - 25513U, // ORIS8 - 17698U, // ORo - 536890209U, // POPCNTB - 536891027U, // POPCNTD - 536898379U, // POPCNTW - 15136U, // PPC32GOT - 15146U, // PPC32PICGOT - 21309U, // QVALIGNI - 21309U, // QVALIGNIb - 21309U, // QVALIGNIs - 21442U, // QVESPLATI - 21442U, // QVESPLATIb - 21442U, // QVESPLATIs - 536895909U, // QVFABS - 536895909U, // QVFABSs - 19710U, // QVFADD - 25152U, // QVFADDS - 25152U, // QVFADDSs - 536890779U, // QVFCFID - 536896146U, // QVFCFIDS - 536897208U, // QVFCFIDU - 536896531U, // QVFCFIDUS - 536890779U, // QVFCFIDb - 24535U, // QVFCMPEQ - 24535U, // QVFCMPEQb - 24535U, // QVFCMPEQbs - 25991U, // QVFCMPGT - 25991U, // QVFCMPGTb - 25991U, // QVFCMPGTbs - 26069U, // QVFCMPLT - 26069U, // QVFCMPLTb - 26069U, // QVFCMPLTbs - 22367U, // QVFCPSGN - 22367U, // QVFCPSGNs - 536890798U, // QVFCTID - 536897218U, // QVFCTIDU - 536899891U, // QVFCTIDUZ - 536899744U, // QVFCTIDZ - 536890798U, // QVFCTIDb - 536897948U, // QVFCTIW - 536897334U, // QVFCTIWU - 536899902U, // QVFCTIWUZ - 536899913U, // QVFCTIWZ - 21738U, // QVFLOGICAL - 21738U, // QVFLOGICALb - 21738U, // QVFLOGICALs - 19718U, // QVFMADD - 25161U, // QVFMADDS - 25161U, // QVFMADDSs - 536895723U, // QVFMR - 536895723U, // QVFMRb - 536895723U, // QVFMRs - 19390U, // QVFMSUB - 25131U, // QVFMSUBS - 25131U, // QVFMSUBSs - 21867U, // QVFMUL - 25536U, // QVFMULS - 25536U, // QVFMULSs - 536895926U, // QVFNABS - 536895926U, // QVFNABSs - 536891551U, // QVFNEG - 536891551U, // QVFNEGs - 19727U, // QVFNMADD - 25171U, // QVFNMADDS - 25171U, // QVFNMADDSs - 19399U, // QVFNMSUB - 25141U, // QVFNMSUBS - 25141U, // QVFNMSUBSs - 22156U, // QVFPERM - 22156U, // QVFPERMs - 536891236U, // QVFRE - 536896246U, // QVFRES - 536896246U, // QVFRESs - 536892998U, // QVFRIM - 536892998U, // QVFRIMs - 536893296U, // QVFRIN - 536893296U, // QVFRINs - 536894568U, // QVFRIP - 536894568U, // QVFRIPs - 536899826U, // QVFRIZ - 536899826U, // QVFRIZs - 536895269U, // QVFRSP - 536895269U, // QVFRSPs - 536891251U, // QVFRSQRTE - 536896254U, // QVFRSQRTES - 536896254U, // QVFRSQRTESs - 21782U, // QVFSEL - 21782U, // QVFSELb - 21782U, // QVFSELbb - 21782U, // QVFSELbs - 19382U, // QVFSUB - 25122U, // QVFSUBS - 25122U, // QVFSUBSs - 22356U, // QVFTSTNAN - 22356U, // QVFTSTNANb - 22356U, // QVFTSTNANbs - 19764U, // QVFXMADD - 25211U, // QVFXMADDS - 21892U, // QVFXMUL - 25545U, // QVFXMULS - 19737U, // QVFXXCPNMADD - 25182U, // QVFXXCPNMADDS - 19774U, // QVFXXMADD - 25222U, // QVFXXMADDS - 19751U, // QVFXXNPMADD - 25197U, // QVFXXNPMADDS - 318788117U, // QVGPCI - 604008294U, // QVLFCDUX - 603998723U, // QVLFCDUXA - 604007587U, // QVLFCDX - 603998643U, // QVLFCDXA - 604008371U, // QVLFCSUX - 603998767U, // QVLFCSUXA - 604008114U, // QVLFCSX - 603998683U, // QVLFCSXA - 604008114U, // QVLFCSXs - 218132347U, // QVLFDUX - 603998746U, // QVLFDUXA - 604007623U, // QVLFDX - 603998664U, // QVLFDXA - 604007623U, // QVLFDXb - 604007532U, // QVLFIWAX - 603998632U, // QVLFIWAXA - 604008550U, // QVLFIWZX - 603998822U, // QVLFIWZXA - 218132424U, // QVLFSUX - 603998790U, // QVLFSUXA - 604008148U, // QVLFSX - 603998704U, // QVLFSXA - 604008148U, // QVLFSXb - 604008148U, // QVLFSXs - 604007640U, // QVLPCLDX - 604008165U, // QVLPCLSX - 8416997U, // QVLPCLSXint - 604007650U, // QVLPCRDX - 604008185U, // QVLPCRSX - 604008304U, // QVSTFCDUX - 603998734U, // QVSTFCDUXA - 604001460U, // QVSTFCDUXI - 603998535U, // QVSTFCDUXIA - 604007596U, // QVSTFCDX - 603998653U, // QVSTFCDXA - 604001418U, // QVSTFCDXI - 603998489U, // QVSTFCDXIA - 604008381U, // QVSTFCSUX - 603998778U, // QVSTFCSUXA - 604001483U, // QVSTFCSUXI - 603998560U, // QVSTFCSUXIA - 604008123U, // QVSTFCSX - 603998693U, // QVSTFCSXA - 604001439U, // QVSTFCSXI - 603998512U, // QVSTFCSXIA - 604008123U, // QVSTFCSXs - 218312580U, // QVSTFDUX - 603998756U, // QVSTFDUXA - 604001472U, // QVSTFDUXI - 603998548U, // QVSTFDUXIA - 604007631U, // QVSTFDX - 603998673U, // QVSTFDXA - 604001429U, // QVSTFDXI - 603998501U, // QVSTFDXIA - 604007631U, // QVSTFDXb - 604008495U, // QVSTFIWX - 603998811U, // QVSTFIWXA - 218312657U, // QVSTFSUX - 603998800U, // QVSTFSUXA - 604001495U, // QVSTFSUXI - 603998573U, // QVSTFSUXIA - 218312657U, // QVSTFSUXs - 604008156U, // QVSTFSX - 603998713U, // QVSTFSXA - 604001450U, // QVSTFSXI - 603998524U, // QVSTFSXIA - 604008156U, // QVSTFSXs - 14944U, // RESTORE_CR - 15076U, // RESTORE_CRBIT - 14815U, // RESTORE_VRSAVE - 15353U, // RFCI - 15364U, // RFDI - 264837U, // RFEBB - 15369U, // RFI - 15336U, // RFID - 15358U, // RFMCI - 21759U, // RLDCL - 17385U, // RLDCLo - 24730U, // RLDCR - 17674U, // RLDCRo - 19536U, // RLDIC - 21766U, // RLDICL - 21766U, // RLDICL_32 - 21766U, // RLDICL_32_64 - 17393U, // RLDICL_32o - 17393U, // RLDICLo - 24750U, // RLDICR - 24750U, // RLDICR_32 - 17682U, // RLDICRo - 16811U, // RLDICo - 3355464397U, // RLDIMI - 3355460494U, // RLDIMIo - 3892335317U, // RLWIMI - 3892335317U, // RLWIMI8 - 3892331415U, // RLWIMI8o - 3892331415U, // RLWIMIo - 22102U, // RLWINM - 22102U, // RLWINM8 - 17434U, // RLWINM8o - 17434U, // RLWINMo - 22111U, // RLWNM - 22111U, // RLWNM8 - 17443U, // RLWNM8o - 17443U, // RLWNMo - 14518U, // ReadTB - 543908U, // SC - 13820U, // SELECT_CC_F16 - 13742U, // SELECT_CC_F4 - 14096U, // SELECT_CC_F8 - 13767U, // SELECT_CC_I4 - 14141U, // SELECT_CC_I8 - 14536U, // SELECT_CC_QBRC - 14565U, // SELECT_CC_QFRC - 14654U, // SELECT_CC_QSRC - 14778U, // SELECT_CC_SPE - 13713U, // SELECT_CC_SPE4 - 14625U, // SELECT_CC_VRRC - 14594U, // SELECT_CC_VSFRC - 14714U, // SELECT_CC_VSRC - 14683U, // SELECT_CC_VSSRC - 13835U, // SELECT_F16 - 13756U, // SELECT_F4 - 14110U, // SELECT_F8 - 13781U, // SELECT_I4 - 14315U, // SELECT_I8 - 14552U, // SELECT_QBRC - 14581U, // SELECT_QFRC - 14670U, // SELECT_QSRC - 14793U, // SELECT_SPE - 13729U, // SELECT_SPE4 - 14641U, // SELECT_VRRC - 14611U, // SELECT_VSFRC - 14730U, // SELECT_VSRC - 14700U, // SELECT_VSSRC - 536890188U, // SETB - 15256U, // SLBIA - 544576U, // SLBIE - 536891535U, // SLBIEG - 536891160U, // SLBMFEE - 536897385U, // SLBMFEV - 536891243U, // SLBMTE - 15284U, // SLBSYNC - 19950U, // SLD - 16922U, // SLDo - 27085U, // SLW - 27085U, // SLW8 - 18034U, // SLW8o - 18034U, // SLWo - 33583443U, // SPELWZ - 604008569U, // SPELWZX - 33581929U, // SPESTW - 604008514U, // SPESTWX - 14956U, // SPILL_CR - 15091U, // SPILL_CRBIT - 14831U, // SPILL_VRSAVE - 19680U, // SRAD - 21021U, // SRADI - 21021U, // SRADI_32 - 17203U, // SRADIo - 16859U, // SRADo - 26914U, // SRAW - 21519U, // SRAWI - 17312U, // SRAWIo - 17993U, // SRAWo - 20036U, // SRD - 16942U, // SRDo - 27340U, // SRW - 27340U, // SRW8 - 18040U, // SRW8o - 18040U, // SRWo - 33573748U, // STB - 33573748U, // STB8 - 27981U, // STBCIX - 603997899U, // STBCX - 604007899U, // STBEPX - 201533076U, // STBU - 201533076U, // STBU8 - 218312543U, // STBUX - 218312543U, // STBUX8 - 604007581U, // STBX - 604007581U, // STBX8 - 27805U, // STBXTLS - 27805U, // STBXTLS_ - 27805U, // STBXTLS_32 - 33574566U, // STD - 25866U, // STDAT - 604008031U, // STDBRX - 27996U, // STDCIX - 603997907U, // STDCX - 201533137U, // STDU - 218312596U, // STDUX - 604007675U, // STDX - 27899U, // STDXTLS - 27899U, // STDXTLS_ - 33574271U, // STFD - 604007915U, // STFDEPX - 201533088U, // STFDU - 218312582U, // STFDUX - 604007633U, // STFDX - 604008497U, // STFIWX - 33579812U, // STFS - 201533203U, // STFSU - 218312659U, // STFSUX - 604008158U, // STFSX - 33575301U, // STH - 33575301U, // STH8 - 604008046U, // STHBRX - 28004U, // STHCIX - 603997915U, // STHCX - 604007931U, // STHEPX - 201533166U, // STHU - 201533166U, // STHU8 - 218312610U, // STHUX - 218312610U, // STHUX8 - 604007751U, // STHX - 604007751U, // STHX8 - 27975U, // STHXTLS - 27975U, // STHXTLS_ - 27975U, // STHXTLS_32 - 33581527U, // STMW - 15448U, // STOP - 21630U, // STSWI - 604007564U, // STVEBX - 604007734U, // STVEHX - 604008487U, // STVEWX - 604008444U, // STVX - 604001696U, // STVXL - 33581929U, // STW - 33581929U, // STW8 - 25944U, // STWAT - 604008071U, // STWBRX - 28012U, // STWCIX - 603997923U, // STWCX - 604007946U, // STWEPX - 201533256U, // STWU - 201533256U, // STWU8 - 218312667U, // STWUX - 218312667U, // STWUX8 - 604008514U, // STWX - 604008514U, // STWX8 - 28738U, // STWXTLS - 28738U, // STWXTLS_ - 28738U, // STWXTLS_32 - 33574528U, // STXSD - 604007667U, // STXSDX - 604007572U, // STXSIBX - 604007572U, // STXSIBXv - 604007742U, // STXSIHX - 604007742U, // STXSIHXv - 604008505U, // STXSIWX - 33578830U, // STXSSP - 604007987U, // STXSSPX - 33580991U, // STXV - 604007490U, // STXVB16X - 604007455U, // STXVD2X - 604007508U, // STXVH8X - 21907U, // STXVL - 21823U, // STXVLL - 604007472U, // STXVW4X - 604008456U, // STXVX - 20401U, // SUBF - 20401U, // SUBF8 - 17095U, // SUBF8o - 19515U, // SUBFC - 19515U, // SUBFC8 - 16787U, // SUBFC8o - 16787U, // SUBFCo - 20264U, // SUBFE - 20264U, // SUBFE8 - 17021U, // SUBFE8o - 17021U, // SUBFEo - 19543U, // SUBFIC - 19543U, // SUBFIC8 - 536891221U, // SUBFME - 536891221U, // SUBFME8 - 536887949U, // SUBFME8o - 536887949U, // SUBFMEo - 536891299U, // SUBFZE - 536891299U, // SUBFZE8 - 536887998U, // SUBFZE8o - 536887998U, // SUBFZEo - 17095U, // SUBFo - 543880U, // SYNC - 722396U, // TABORT - 9191816U, // TABORTDC - 9716507U, // TABORTDCI - 9191888U, // TABORTWC - 9716519U, // TABORTWCI - 592514U, // TAILB - 592514U, // TAILB8 - 608340U, // TAILBA - 608340U, // TAILBA8 - 15470U, // TAILBCTR - 15470U, // TAILBCTR8 - 263252U, // TBEGIN - 546018U, // TCHECK - 15049U, // TCHECK_RET - 538003403U, // TCRETURNai - 538003310U, // TCRETURNai8 - 537988294U, // TCRETURNdi - 537986940U, // TCRETURNdi8 - 537944192U, // TCRETURNri - 537937802U, // TCRETURNri8 - 183950U, // TD - 184949U, // TDI - 819751U, // TEND - 15262U, // TLBIA - 661327687U, // TLBIE - 546062U, // TLBIEL - 536898659U, // TLBIVAX - 544193U, // TLBLD - 545453U, // TLBLI - 15341U, // TLBRE - 20317U, // TLBRE2 - 536899243U, // TLBSX - 28331U, // TLBSX2 - 18155U, // TLBSX2D - 15292U, // TLBSYNC - 15347U, // TLBWE - 20357U, // TLBWE2 - 15439U, // TRAP - 12895U, // TRECHKPT - 721928U, // TRECLAIM - 820533U, // TSR - 191293U, // TW - 185477U, // TWI - 536889240U, // UPDATE_VRSAVE - 14933U, // UpdateGBR - 19321U, // VABSDUB - 20874U, // VABSDUH - 27527U, // VABSDUW - 24652U, // VADDCUQ - 27511U, // VADDCUW - 24683U, // VADDECUQ - 22146U, // VADDEUQM - 23511U, // VADDFP - 25085U, // VADDSBS - 25428U, // VADDSHS - 25727U, // VADDSWS - 21966U, // VADDUBM - 25113U, // VADDUBS - 21994U, // VADDUDM - 22033U, // VADDUHM - 25456U, // VADDUHS - 22127U, // VADDUQM - 22216U, // VADDUWM - 25754U, // VADDUWS - 20014U, // VAND - 19508U, // VANDC - 19196U, // VAVGSB - 20761U, // VAVGSH - 27361U, // VAVGSW - 19339U, // VAVGUB - 20892U, // VAVGUH - 27545U, // VAVGUW - 19955U, // VBPERMD - 24606U, // VBPERMQ - 134246093U, // VCFSX - 536899277U, // VCFSX_0 - 134246299U, // VCFUX - 536899483U, // VCFUX_0 - 24784U, // VCIPHER - 26172U, // VCIPHERLAST - 536890378U, // VCLZB - 536891100U, // VCLZD - 536891879U, // VCLZH - 536889996U, // VCLZLSBB - 536898551U, // VCLZW - 23475U, // VCMPBFP - 17553U, // VCMPBFPo - 23574U, // VCMPEQFP - 17574U, // VCMPEQFPo - 19364U, // VCMPEQUB - 16705U, // VCMPEQUBo - 20154U, // VCMPEQUD - 16959U, // VCMPEQUDo - 20917U, // VCMPEQUH - 17146U, // VCMPEQUHo - 27570U, // VCMPEQUW - 18065U, // VCMPEQUWo - 23528U, // VCMPGEFP - 17563U, // VCMPGEFPo - 23584U, // VCMPGTFP - 17585U, // VCMPGTFPo - 19249U, // VCMPGTSB - 16686U, // VCMPGTSBo - 20072U, // VCMPGTSD - 16948U, // VCMPGTSDo - 20814U, // VCMPGTSH - 17127U, // VCMPGTSHo - 27424U, // VCMPGTSW - 18046U, // VCMPGTSWo - 19438U, // VCMPGTUB - 16740U, // VCMPGTUBo - 20164U, // VCMPGTUD - 16970U, // VCMPGTUDo - 20939U, // VCMPGTUH - 17157U, // VCMPGTUHo - 27605U, // VCMPGTUW - 18076U, // VCMPGTUWo - 19104U, // VCMPNEB - 16676U, // VCMPNEBo - 20693U, // VCMPNEH - 17117U, // VCMPNEHo - 26968U, // VCMPNEW - 18000U, // VCMPNEWo - 19456U, // VCMPNEZB - 16751U, // VCMPNEZBo - 20957U, // VCMPNEZH - 17168U, // VCMPNEZHo - 27629U, // VCMPNEZW - 18094U, // VCMPNEZWo - 134243572U, // VCTSXS - 536896756U, // VCTSXS_0 - 134243580U, // VCTUXS - 536896764U, // VCTUXS_0 - 536890385U, // VCTZB - 536891115U, // VCTZD - 536891886U, // VCTZH - 536890006U, // VCTZLSBB - 536898568U, // VCTZW - 26542U, // VEQV - 536894457U, // VEXPTEFP - 1207979655U, // VEXTRACTD - 1207978978U, // VEXTRACTUB - 1207980479U, // VEXTRACTUH - 1207987132U, // VEXTRACTUW - 536890536U, // VEXTSB2D - 536890536U, // VEXTSB2Ds - 536897477U, // VEXTSB2W - 536897477U, // VEXTSB2Ws - 536890546U, // VEXTSH2D - 536890546U, // VEXTSH2Ds - 536897487U, // VEXTSH2W - 536897487U, // VEXTSH2Ws - 536890556U, // VEXTSW2D - 536890556U, // VEXTSW2Ds - 28053U, // VEXTUBLX - 28278U, // VEXTUBRX - 28063U, // VEXTUHLX - 28303U, // VEXTUHRX - 28073U, // VEXTUWLX - 28313U, // VEXTUWRX - 536890598U, // VGBBD - 335563626U, // VINSERTB - 1207979676U, // VINSERTD - 335565179U, // VINSERTH - 1207987028U, // VINSERTW - 536894431U, // VLOGEFP - 23502U, // VMADDFP - 23594U, // VMAXFP - 19268U, // VMAXSB - 20082U, // VMAXSD - 20833U, // VMAXSH - 27441U, // VMAXSW - 19448U, // VMAXUB - 20174U, // VMAXUD - 20949U, // VMAXUH - 27615U, // VMAXUW - 25405U, // VMHADDSHS - 25416U, // VMHRADDSHS - 23566U, // VMINFP - 19232U, // VMINSB - 20064U, // VMINSD - 20797U, // VMINSH - 27407U, // VMINSW - 19347U, // VMINUB - 20146U, // VMINUD - 20900U, // VMINUH - 27553U, // VMINUW - 22022U, // VMLADDUHM - 26960U, // VMRGEW - 19113U, // VMRGHB - 20702U, // VMRGHH - 27003U, // VMRGHW - 19131U, // VMRGLB - 20710U, // VMRGLH - 27045U, // VMRGLW - 27318U, // VMRGOW - 21947U, // VMSUMMBM - 22003U, // VMSUMSHM - 25437U, // VMSUMSHS - 21975U, // VMSUMUBM - 22042U, // VMSUMUHM - 25465U, // VMSUMUHS - 536895544U, // VMUL10CUQ - 24661U, // VMUL10ECUQ - 24693U, // VMUL10EUQ - 536895534U, // VMUL10UQ - 19187U, // VMULESB - 20752U, // VMULESH - 27352U, // VMULESW - 19330U, // VMULEUB - 20883U, // VMULEUH - 27536U, // VMULEUW - 19240U, // VMULOSB - 20805U, // VMULOSH - 27415U, // VMULOSW - 19355U, // VMULOUB - 20908U, // VMULOUH - 27561U, // VMULOUW - 22225U, // VMULUWM - 19999U, // VNAND - 24774U, // VNCIPHER - 26158U, // VNCIPHERLAST - 536890757U, // VNEGD - 536897908U, // VNEGW - 23484U, // VNMSUBFP - 24872U, // VNOR - 24885U, // VOR - 19614U, // VORC - 22165U, // VPERM - 24832U, // VPERMR - 24898U, // VPERMXOR - 28187U, // VPKPX - 25564U, // VPKSDSS - 25630U, // VPKSDUS - 25573U, // VPKSHSS - 25648U, // VPKSHUS - 25582U, // VPKSWSS - 25666U, // VPKSWUS - 22180U, // VPKUDUM - 25639U, // VPKUDUS - 22189U, // VPKUHUM - 25657U, // VPKUHUS - 22198U, // VPKUWUM - 25675U, // VPKUWUS - 19151U, // VPMSUMB - 19964U, // VPMSUMD - 20730U, // VPMSUMH - 27101U, // VPMSUMW - 536890208U, // VPOPCNTB - 536891026U, // VPOPCNTD - 536891761U, // VPOPCNTH - 536898378U, // VPOPCNTW - 536890605U, // VPRTYBD - 536895428U, // VPRTYBQ - 536897832U, // VPRTYBW - 536894450U, // VREFP - 536892964U, // VRFIM - 536893289U, // VRFIN - 536894534U, // VRFIP - 536899792U, // VRFIZ - 19139U, // VRLB - 19943U, // VRLD - 21189U, // VRLDMI - 22094U, // VRLDNM - 20718U, // VRLH - 27077U, // VRLW - 21301U, // VRLWMI - 22110U, // VRLWNM - 536894467U, // VRSQRTEFP - 536899001U, // VSBOX - 21796U, // VSEL - 19667U, // VSHASIGMAD - 26901U, // VSHASIGMAW - 21854U, // VSL - 19145U, // VSLB - 19949U, // VSLD - 21340U, // VSLDOI - 20724U, // VSLH - 22488U, // VSLO - 26520U, // VSLV - 27084U, // VSLW - 134237016U, // VSPLTB - 134237016U, // VSPLTBs - 134238569U, // VSPLTH - 134238569U, // VSPLTHs - 151014157U, // VSPLTISB - 151015722U, // VSPLTISH - 151022322U, // VSPLTISW - 134245177U, // VSPLTW - 24963U, // VSR - 19070U, // VSRAB - 19679U, // VSRAD - 20671U, // VSRAH - 26913U, // VSRAW - 19181U, // VSRB - 20043U, // VSRD - 20746U, // VSRH - 22602U, // VSRO - 26548U, // VSRV - 27339U, // VSRW - 24643U, // VSUBCUQ - 27502U, // VSUBCUW - 24673U, // VSUBECUQ - 22136U, // VSUBEUQM - 23494U, // VSUBFP - 25076U, // VSUBSBS - 25396U, // VSUBSHS - 25718U, // VSUBSWS - 21957U, // VSUBUBM - 25104U, // VSUBUBS - 21985U, // VSUBUDM - 22013U, // VSUBUHM - 25447U, // VSUBUHS - 22118U, // VSUBUQM - 22207U, // VSUBUWM - 25745U, // VSUBUWS - 25708U, // VSUM2SWS - 25066U, // VSUM4SBS - 25386U, // VSUM4SHS - 25094U, // VSUM4UBS - 25736U, // VSUMSWS - 536899090U, // VUPKHPX - 536890116U, // VUPKHSB - 536891681U, // VUPKHSH - 536898281U, // VUPKHSW - 536899106U, // VUPKLPX - 536890135U, // VUPKLSB - 536891700U, // VUPKLSH - 536898300U, // VUPKLSW - 24916U, // VXOR - 117465428U, // V_SET0 - 117465428U, // V_SET0B - 117465428U, // V_SET0H - 9988850U, // V_SETALLONES - 9988850U, // V_SETALLONESB - 9988850U, // V_SETALLONESH - 550341U, // WAIT - 544545U, // WRTEE - 545402U, // WRTEEI - 24893U, // XOR - 24893U, // XOR8 - 17703U, // XOR8o - 21380U, // XORI - 21380U, // XORI8 - 25512U, // XORIS - 25512U, // XORIS8 - 17703U, // XORo - 536894157U, // XSABSDP - 536894776U, // XSABSQP - 22769U, // XSADDDP - 23734U, // XSADDQP - 22561U, // XSADDQPO - 24034U, // XSADDSP - 23203U, // XSCMPEQDP - 23171U, // XSCMPEXPDP - 23832U, // XSCMPEXPQP - 22831U, // XSCMPGEDP - 23263U, // XSCMPGTDP - 23101U, // XSCMPODP - 23802U, // XSCMPOQP - 23327U, // XSCMPUDP - 23883U, // XSCMPUQP - 23061U, // XSCPSGNDP - 23791U, // XSCPSGNQP - 536894514U, // XSCVDPHP - 536894724U, // XSCVDPQP - 536895208U, // XSCVDPSP - 536893331U, // XSCVDPSPN - 536896174U, // XSCVDPSXDS - 536896174U, // XSCVDPSXDSs - 536896684U, // XSCVDPSXWS - 536896684U, // XSCVDPSXWSs - 536896210U, // XSCVDPUXDS - 536896210U, // XSCVDPUXDSs - 536896720U, // XSCVDPUXWS - 536896720U, // XSCVDPUXWSs - 536894023U, // XSCVHPDP - 536894033U, // XSCVQPDP - 536893406U, // XSCVQPDPO - 536899765U, // XSCVQPSDZ - 536899946U, // XSCVQPSWZ - 536899776U, // XSCVQPUDZ - 536899957U, // XSCVQPUWZ - 536894655U, // XSCVSDQP - 536894043U, // XSCVSPDP - 536893320U, // XSCVSPDPN - 536893699U, // XSCVSXDDP - 536894964U, // XSCVSXDSP - 536894665U, // XSCVUDQP - 536893721U, // XSCVUXDDP - 536894986U, // XSCVUXDSP - 23337U, // XSDIVDP - 23893U, // XSDIVQP - 22592U, // XSDIVQPO - 24448U, // XSDIVSP - 23151U, // XSIEXPDP - 23822U, // XSIEXPQP - 1744853151U, // XSMADDADP - 1744854436U, // XSMADDASP - 1744853503U, // XSMADDMDP - 1744854718U, // XSMADDMSP - 1744854188U, // XSMADDQP - 1744853014U, // XSMADDQPO - 22759U, // XSMAXCDP - 23397U, // XSMAXDP - 22941U, // XSMAXJDP - 22749U, // XSMINCDP - 23083U, // XSMINDP - 22931U, // XSMINJDP - 1744853105U, // XSMSUBADP - 1744854390U, // XSMSUBASP - 1744853457U, // XSMSUBMDP - 1744854672U, // XSMSUBMSP - 1744854147U, // XSMSUBQP - 1744852981U, // XSMSUBQPO - 22951U, // XSMULDP - 23782U, // XSMULQP - 22571U, // XSMULQPO - 24166U, // XSMULSP - 536894137U, // XSNABSDP - 536894766U, // XSNABSQP - 536893805U, // XSNEGDP - 536894675U, // XSNEGQP - 1744853127U, // XSNMADDADP - 1744854412U, // XSNMADDASP - 1744853479U, // XSNMADDMDP - 1744854694U, // XSNMADDMSP - 1744854177U, // XSNMADDQP - 1744853002U, // XSNMADDQPO - 1744853081U, // XSNMSUBADP - 1744854366U, // XSNMSUBASP - 1744853433U, // XSNMSUBMDP - 1744854648U, // XSNMSUBMSP - 1744854136U, // XSNMSUBQP - 1744852969U, // XSNMSUBQPO - 536892260U, // XSRDPI - 536890463U, // XSRDPIC - 536892971U, // XSRDPIM - 536894541U, // XSRDPIP - 536899799U, // XSRDPIZ - 536893765U, // XSREDP - 536895019U, // XSRESP - 117740404U, // XSRQPI - 117747084U, // XSRQPIX - 117743547U, // XSRQPXP - 536895277U, // XSRSP - 536893781U, // XSRSQRTEDP - 536895035U, // XSRSQRTESP - 536894197U, // XSSQRTDP - 536894785U, // XSSQRTQP - 536893493U, // XSSQRTQPO - 536895329U, // XSSQRTSP - 22709U, // XSSUBDP - 23693U, // XSSUBQP - 22528U, // XSSUBQPO - 23994U, // XSSUBSP - 23346U, // XSTDIVDP - 536894207U, // XSTSQRTDP - 2281724103U, // XSTSTDCDP - 2281725078U, // XSTSTDCQP - 2281725388U, // XSTSTDCSP - 536894095U, // XSXEXPDP - 536894756U, // XSXEXPQP - 536893823U, // XSXSIGDP - 536894684U, // XSXSIGQP - 536894166U, // XVABSDP - 536895294U, // XVABSSP - 22778U, // XVADDDP - 24043U, // XVADDSP - 23214U, // XVCMPEQDP - 17529U, // XVCMPEQDPo - 24346U, // XVCMPEQSP - 17615U, // XVCMPEQSPo - 22842U, // XVCMPGEDP - 17517U, // XVCMPGEDPo - 24096U, // XVCMPGESP - 17603U, // XVCMPGESPo - 23274U, // XVCMPGTDP - 17541U, // XVCMPGTDPo - 24406U, // XVCMPGTSP - 17634U, // XVCMPGTSPo - 23072U, // XVCPSGNDP - 24276U, // XVCPSGNSP - 536895218U, // XVCVDPSP - 536896186U, // XVCVDPSXDS - 536896696U, // XVCVDPSXWS - 536896222U, // XVCVDPUXDS - 536896732U, // XVCVDPUXWS - 536895228U, // XVCVHPSP - 536894053U, // XVCVSPDP - 536894524U, // XVCVSPHP - 536896198U, // XVCVSPSXDS - 536896708U, // XVCVSPSXWS - 536896234U, // XVCVSPUXDS - 536896744U, // XVCVSPUXWS - 536893710U, // XVCVSXDDP - 536894975U, // XVCVSXDSP - 536894287U, // XVCVSXWDP - 536895388U, // XVCVSXWSP - 536893732U, // XVCVUXDDP - 536894997U, // XVCVUXDSP - 536894298U, // XVCVUXWDP - 536895399U, // XVCVUXWSP - 23366U, // XVDIVDP - 24467U, // XVDIVSP - 23161U, // XVIEXPDP - 24326U, // XVIEXPSP - 1744853162U, // XVMADDADP - 1744854447U, // XVMADDASP - 1744853514U, // XVMADDMDP - 1744854729U, // XVMADDMSP - 23406U, // XVMAXDP - 24498U, // XVMAXSP - 23092U, // XVMINDP - 24287U, // XVMINSP - 1744853116U, // XVMSUBADP - 1744854401U, // XVMSUBASP - 1744853468U, // XVMSUBMDP - 1744854683U, // XVMSUBMSP - 22960U, // XVMULDP - 24175U, // XVMULSP - 536894147U, // XVNABSDP - 536895284U, // XVNABSSP - 536893814U, // XVNEGDP - 536895059U, // XVNEGSP - 1744853139U, // XVNMADDADP - 1744854424U, // XVNMADDASP - 1744853491U, // XVNMADDMDP - 1744854706U, // XVNMADDMSP - 1744853093U, // XVNMSUBADP - 1744854378U, // XVNMSUBASP - 1744853445U, // XVNMSUBMDP - 1744854660U, // XVNMSUBMSP - 536892268U, // XVRDPI - 536890472U, // XVRDPIC - 536892980U, // XVRDPIM - 536894550U, // XVRDPIP - 536899808U, // XVRDPIZ - 536893773U, // XVREDP - 536895027U, // XVRESP - 536892284U, // XVRSPI - 536890481U, // XVRSPIC - 536892989U, // XVRSPIM - 536894559U, // XVRSPIP - 536899817U, // XVRSPIZ - 536893793U, // XVRSQRTEDP - 536895047U, // XVRSQRTESP - 536894229U, // XVSQRTDP - 536895350U, // XVSQRTSP - 22718U, // XVSUBDP - 24003U, // XVSUBSP - 23356U, // XVTDIVDP - 24457U, // XVTDIVSP - 536894218U, // XVTSQRTDP - 536895339U, // XVTSQRTSP - 2281724114U, // XVTSTDCDP - 2281725399U, // XVTSTDCSP - 536894105U, // XVXEXPDP - 536895248U, // XVXEXPSP - 536893833U, // XVXSIGDP - 536895068U, // XVXSIGSP - 536890938U, // XXBRD - 536891651U, // XXBRH - 536895527U, // XXBRQ - 536898244U, // XXBRW - 27592U, // XXEXTRACTUW - 2818599774U, // XXINSERTW - 19973U, // XXLAND - 19490U, // XXLANDC - 26526U, // XXLEQV - 19981U, // XXLNAND - 24856U, // XXLNOR - 24849U, // XXLOR - 19598U, // XXLORC - 24849U, // XXLORf - 24890U, // XXLXOR - 117465402U, // XXLXORdpz - 117465402U, // XXLXORspz - 117465402U, // XXLXORz - 27011U, // XXMRGHW - 27053U, // XXMRGLW - 22172U, // XXPERM - 21060U, // XXPERMDI - 21060U, // XXPERMDIs - 24840U, // XXPERMR - 21802U, // XXSEL - 21526U, // XXSLDWI - 21526U, // XXSLDWIs - 352340657U, // XXSPLTIB - 27457U, // XXSPLTW - 27457U, // XXSPLTWs - 183320U, // gBC - 182360U, // gBCA - 10812308U, // gBCAat - 188808U, // gBCCTR - 185678U, // gBCCTRL - 185594U, // gBCL - 182654U, // gBCLA - 10812324U, // gBCLAat - 188633U, // gBCLR - 185671U, // gBCLRL - 11336717U, // gBCLat - 11336625U, // gBCat + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 14805U, // DBG_VALUE + 14855U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 14771U, // BUNDLE + 15169U, // LIFETIME_START + 14758U, // LIFETIME_END + 0U, // STACKMAP + 15377U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 12827U, // PATCHABLE_FUNCTION_ENTER + 12747U, // PATCHABLE_RET + 12873U, // PATCHABLE_FUNCTION_EXIT + 12850U, // PATCHABLE_TAIL_CALL + 12802U, // PATCHABLE_EVENT_CALL + 12778U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 14087U, // CFENCE8 + 21042U, // CLRLSLDI + 17211U, // CLRLSLDIo + 21551U, // CLRLSLWI + 17320U, // CLRLSLWIo + 21077U, // CLRRDI + 17238U, // CLRRDIo + 21592U, // CLRRWI + 17349U, // CLRRWIo + 536897109U, // CP_COPY_FIRST + 536899711U, // CP_COPYx + 536897058U, // CP_PASTE_LAST + 536891262U, // CP_PASTEx + 562481U, // DCBFL + 564336U, // DCBFLP + 561067U, // DCBFx + 553690475U, // DCBTCT + 553689756U, // DCBTDS + 553690483U, // DCBTSTCT + 553689764U, // DCBTSTDS + 566909U, // DCBTSTT + 566881U, // DCBTSTx + 566896U, // DCBTT + 566623U, // DCBTx + 13334U, // DFLOADf32 + 13646U, // DFLOADf64 + 13356U, // DFSTOREf32 + 13668U, // DFSTOREf64 + 21052U, // EXTLDI + 17222U, // EXTLDIo + 21577U, // EXTLWI + 17340U, // EXTLWIo + 21101U, // EXTRDI + 17265U, // EXTRDIo + 21616U, // EXTRWI + 17376U, // EXTRWIo + 21561U, // INSLWI + 17331U, // INSLWIo + 21085U, // INSRDI + 17247U, // INSRDIo + 21600U, // INSRWI + 17358U, // INSRWIo + 33573242U, // LAx + 15199U, // LIWAX + 15245U, // LIWZX + 21205U, // RLWIMIbm + 17303U, // RLWIMIobm + 22102U, // RLWINMbm + 17434U, // RLWINMobm + 22111U, // RLWNMbm + 17443U, // RLWNMobm + 21093U, // ROTRDI + 17256U, // ROTRDIo + 21608U, // ROTRWI + 17367U, // ROTRWIo + 21046U, // SLDI + 17215U, // SLDIo + 21555U, // SLWI + 17324U, // SLWIo + 14743U, // SPILLTOVSR_LD + 15206U, // SPILLTOVSR_LDX + 15184U, // SPILLTOVSR_ST + 15222U, // SPILLTOVSR_STX + 21087U, // SRDI + 17249U, // SRDIo + 21602U, // SRWI + 17360U, // SRWIo + 15238U, // STIWX + 20993U, // SUBI + 19522U, // SUBIC + 16795U, // SUBICo + 25475U, // SUBIS + 50357130U, // SUBPCIS + 13345U, // XFLOADf32 + 13657U, // XFLOADf64 + 13368U, // XFSTOREf32 + 13680U, // XFSTOREf64 + 19705U, // ADD4 + 19705U, // ADD4TLS + 16867U, // ADD4o + 19705U, // ADD8 + 19705U, // ADD8TLS + 19705U, // ADD8TLS_ + 16867U, // ADD8o + 19484U, // ADDC + 19484U, // ADDC8 + 16762U, // ADDC8o + 16762U, // ADDCo + 20235U, // ADDE + 20235U, // ADDE8 + 17006U, // ADDE8o + 17006U, // ADDEo + 21028U, // ADDI + 21028U, // ADDI8 + 19529U, // ADDIC + 19529U, // ADDIC8 + 16803U, // ADDICo + 25500U, // ADDIS + 25500U, // ADDIS8 + 14503U, // ADDISdtprelHA + 12929U, // ADDISdtprelHA32 + 14486U, // ADDISgotTprelHA + 14458U, // ADDIStlsgdHA + 14472U, // ADDIStlsldHA + 14446U, // ADDIStocHA + 14920U, // ADDIdtprelL + 13218U, // ADDIdtprelL32 + 14883U, // ADDItlsgdL + 13175U, // ADDItlsgdL32 + 14966U, // ADDItlsgdLADDR + 13270U, // ADDItlsgdLADDR32 + 14895U, // ADDItlsldL + 13189U, // ADDItlsldL32 + 14982U, // ADDItlsldLADDR + 13288U, // ADDItlsldLADDR32 + 14873U, // ADDItocL + 536891214U, // ADDME + 536891214U, // ADDME8 + 536887941U, // ADDME8o + 536887941U, // ADDMEo + 536896403U, // ADDPCIS + 536891292U, // ADDZE + 536891292U, // ADDZE8 + 536887990U, // ADDZE8o + 536887990U, // ADDZEo + 51111U, // ADJCALLSTACKDOWN + 51130U, // ADJCALLSTACKUP + 19976U, // AND + 19976U, // AND8 + 16929U, // AND8o + 19493U, // ANDC + 19493U, // ANDC8 + 16769U, // ANDC8o + 16769U, // ANDCo + 17833U, // ANDISo + 17833U, // ANDISo8 + 17231U, // ANDIo + 17231U, // ANDIo8 + 15104U, // ANDIo_1_EQ_BIT + 14396U, // ANDIo_1_EQ_BIT8 + 15120U, // ANDIo_1_GT_BIT + 14413U, // ANDIo_1_GT_BIT8 + 16929U, // ANDo + 1141917528U, // ATOMIC_CMP_SWAP_I16 + 1141917506U, // ATOMIC_CMP_SWAP_I32 + 13504U, // ATOMIC_CMP_SWAP_I64 + 14257U, // ATOMIC_CMP_SWAP_I8 + 13868U, // ATOMIC_LOAD_ADD_I16 + 12967U, // ATOMIC_LOAD_ADD_I32 + 13401U, // ATOMIC_LOAD_ADD_I64 + 14155U, // ATOMIC_LOAD_ADD_I8 + 13911U, // ATOMIC_LOAD_AND_I16 + 13010U, // ATOMIC_LOAD_AND_I32 + 13692U, // ATOMIC_LOAD_AND_I64 + 14196U, // ATOMIC_LOAD_AND_I8 + 14055U, // ATOMIC_LOAD_MAX_I16 + 13154U, // ATOMIC_LOAD_MAX_I32 + 13588U, // ATOMIC_LOAD_MAX_I64 + 14347U, // ATOMIC_LOAD_MAX_I8 + 13954U, // ATOMIC_LOAD_MIN_I16 + 13053U, // ATOMIC_LOAD_MIN_I32 + 13466U, // ATOMIC_LOAD_MIN_I64 + 14237U, // ATOMIC_LOAD_MIN_I8 + 13889U, // ATOMIC_LOAD_NAND_I16 + 12988U, // ATOMIC_LOAD_NAND_I32 + 13422U, // ATOMIC_LOAD_NAND_I64 + 14175U, // ATOMIC_LOAD_NAND_I8 + 14013U, // ATOMIC_LOAD_OR_I16 + 13112U, // ATOMIC_LOAD_OR_I32 + 13546U, // ATOMIC_LOAD_OR_I64 + 14296U, // ATOMIC_LOAD_OR_I8 + 13847U, // ATOMIC_LOAD_SUB_I16 + 12946U, // ATOMIC_LOAD_SUB_I32 + 13380U, // ATOMIC_LOAD_SUB_I64 + 14121U, // ATOMIC_LOAD_SUB_I8 + 14033U, // ATOMIC_LOAD_UMAX_I16 + 13132U, // ATOMIC_LOAD_UMAX_I32 + 13566U, // ATOMIC_LOAD_UMAX_I64 + 14326U, // ATOMIC_LOAD_UMAX_I8 + 13932U, // ATOMIC_LOAD_UMIN_I16 + 13031U, // ATOMIC_LOAD_UMIN_I32 + 13444U, // ATOMIC_LOAD_UMIN_I64 + 14216U, // ATOMIC_LOAD_UMIN_I8 + 13992U, // ATOMIC_LOAD_XOR_I16 + 13091U, // ATOMIC_LOAD_XOR_I32 + 13525U, // ATOMIC_LOAD_XOR_I64 + 14277U, // ATOMIC_LOAD_XOR_I8 + 13975U, // ATOMIC_SWAP_I16 + 13074U, // ATOMIC_SWAP_I32 + 13487U, // ATOMIC_SWAP_I64 + 14430U, // ATOMIC_SWAP_I8 + 15424U, // ATTN + 592514U, // B + 608340U, // BA + 83902568U, // BC + 1686447U, // BCC + 2210735U, // BCCA + 2735023U, // BCCCTR + 2735023U, // BCCCTR8 + 3259311U, // BCCCTRL + 3259311U, // BCCCTRL8 + 3783599U, // BCCL + 4307887U, // BCCLA + 4832175U, // BCCLR + 5356463U, // BCCLRL + 5783706U, // BCCTR + 5783706U, // BCCTR8 + 5783762U, // BCCTR8n + 5783684U, // BCCTRL + 5783684U, // BCCTRL8 + 5783742U, // BCCTRL8n + 5783742U, // BCCTRLn + 5783762U, // BCCTRn + 17451U, // BCDCFNo + 17654U, // BCDCFSQo + 18172U, // BCDCFZo + 17460U, // BCDCPSGNo + 536888420U, // BCDCTNo + 536888576U, // BCDCTSQo + 18188U, // BCDCTZo + 17480U, // BCDSETSGNo + 17709U, // BCDSRo + 17765U, // BCDSo + 16819U, // BCDTRUNCo + 17858U, // BCDUSo + 16830U, // BCDUTRUNCo + 83902576U, // BCL + 5783696U, // BCLR + 5783673U, // BCLRL + 5783732U, // BCLRLn + 5783753U, // BCLRn + 589901U, // BCLalways + 83902636U, // BCLn + 15470U, // BCTR + 15470U, // BCTR8 + 15418U, // BCTRL + 15418U, // BCTRL8 + 114778U, // BCTRL8_LDinto_toc + 83902629U, // BCn + 602413U, // BDNZ + 602413U, // BDNZ8 + 608887U, // BDNZA + 606464U, // BDNZAm + 606249U, // BDNZAp + 595380U, // BDNZL + 608651U, // BDNZLA + 606448U, // BDNZLAm + 606233U, // BDNZLAp + 15463U, // BDNZLR + 15463U, // BDNZLR8 + 15410U, // BDNZLRL + 12723U, // BDNZLRLm + 12680U, // BDNZLRLp + 12739U, // BDNZLRm + 12696U, // BDNZLRp + 590095U, // BDNZLm + 589880U, // BDNZLp + 590109U, // BDNZm + 589894U, // BDNZp + 602256U, // BDZ + 602256U, // BDZ8 + 608881U, // BDZA + 606457U, // BDZAm + 606242U, // BDZAp + 595374U, // BDZL + 608644U, // BDZLA + 606440U, // BDZLAm + 606225U, // BDZLAp + 15457U, // BDZLR + 15457U, // BDZLR8 + 15403U, // BDZLRL + 12715U, // BDZLRLm + 12672U, // BDZLRLp + 12732U, // BDZLRm + 12689U, // BDZLRp + 590088U, // BDZLm + 589873U, // BDZLp + 590103U, // BDZm + 589888U, // BDZp + 595190U, // BL + 595190U, // BL8 + 6362358U, // BL8_NOP + 6427894U, // BL8_NOP_TLS + 660726U, // BL8_TLS + 660726U, // BL8_TLS_ + 608633U, // BLA + 608633U, // BLA8 + 6375801U, // BLA8_NOP + 15453U, // BLR + 15453U, // BLR8 + 15398U, // BLRL + 660726U, // BL_TLS + 19956U, // BPERMD + 19585U, // BRINC + 15273U, // CLRBHRB + 19160U, // CMPB + 19160U, // CMPB8 + 20020U, // CMPD + 21070U, // CMPDI + 19166U, // CMPEQB + 19927U, // CMPLD + 21034U, // CMPLDI + 27069U, // CMPLW + 21535U, // CMPLWI + 100682470U, // CMPRB + 100682470U, // CMPRB8 + 27326U, // CMPW + 21585U, // CMPWI + 536891107U, // CNTLZD + 536887900U, // CNTLZDo + 536898560U, // CNTLZW + 536898560U, // CNTLZW8 + 536889017U, // CNTLZW8o + 536889017U, // CNTLZWo + 536891122U, // CNTTZD + 536887909U, // CNTTZDo + 536898575U, // CNTTZW + 536898575U, // CNTTZW8 + 536889026U, // CNTTZW8o + 536889026U, // CNTTZWo + 15475U, // CP_ABORT + 28799U, // CP_COPY + 28799U, // CP_COPY8 + 20350U, // CP_PASTE + 20350U, // CP_PASTE8 + 17062U, // CP_PASTE8o + 17062U, // CP_PASTEo + 13806U, // CR6SET + 13792U, // CR6UNSET + 20006U, // CRAND + 19499U, // CRANDC + 26534U, // CREQV + 19990U, // CRNAND + 24864U, // CRNOR + 24878U, // CROR + 19606U, // CRORC + 117467046U, // CRSET + 117465420U, // CRUNSET + 24908U, // CRXOR + 1686447U, // CTRL_DEP + 536893342U, // DARN + 559186U, // DCBA + 151467U, // DCBF + 564087U, // DCBFEP + 561653U, // DCBI + 566857U, // DCBST + 564120U, // DCBSTEP + 157023U, // DCBT + 170896U, // DCBTEP + 157281U, // DCBTST + 170913U, // DCBTSTEP + 569477U, // DCBZ + 564139U, // DCBZEP + 562599U, // DCBZL + 564103U, // DCBZLEP + 536891911U, // DCCCI + 20182U, // DIVD + 20241U, // DIVDE + 26334U, // DIVDEU + 17936U, // DIVDEUo + 17013U, // DIVDEo + 26327U, // DIVDU + 17928U, // DIVDUo + 16981U, // DIVDo + 27623U, // DIVW + 20364U, // DIVWE + 26342U, // DIVWEU + 17945U, // DIVWEUo + 17070U, // DIVWEo + 26448U, // DIVWU + 17972U, // DIVWUo + 18087U, // DIVWo + 713696U, // DSS + 15391U, // DSSALL + 1745036880U, // DST + 1745036880U, // DST64 + 1745036905U, // DSTST + 1745036905U, // DSTST64 + 1745036934U, // DSTSTT + 1745036934U, // DSTSTT64 + 1745036919U, // DSTT + 1745036919U, // DSTT64 + 14526U, // DYNALLOC + 14076U, // DYNALLOC8 + 15061U, // DYNAREAOFFSET + 14380U, // DYNAREAOFFSET8 + 536895901U, // EFDABS + 19702U, // EFDADD + 536896266U, // EFDCFS + 536891387U, // EFDCFSF + 536892298U, // EFDCFSI + 536890788U, // EFDCFSID + 536891489U, // EFDCFUF + 536892375U, // EFDCFUI + 536890807U, // EFDCFUID + 24525U, // EFDCMPEQ + 25981U, // EFDCMPGT + 26059U, // EFDCMPLT + 536891461U, // EFDCTSF + 536892326U, // EFDCTSI + 536899733U, // EFDCTSIDZ + 536899834U, // EFDCTSIZ + 536891517U, // EFDCTUF + 536892403U, // EFDCTUI + 536899754U, // EFDCTUIDZ + 536899865U, // EFDCTUIZ + 26482U, // EFDDIV + 21859U, // EFDMUL + 536895917U, // EFDNABS + 536891543U, // EFDNEG + 19374U, // EFDSUB + 24575U, // EFDTSTEQ + 26022U, // EFDTSTGT + 26100U, // EFDTSTLT + 536895954U, // EFSABS + 19785U, // EFSADD + 536890738U, // EFSCFD + 536891396U, // EFSCFSF + 536892307U, // EFSCFSI + 536891498U, // EFSCFUF + 536892384U, // EFSCFUI + 24545U, // EFSCMPEQ + 26001U, // EFSCMPGT + 26079U, // EFSCMPLT + 536891470U, // EFSCTSF + 536892335U, // EFSCTSI + 536899844U, // EFSCTSIZ + 536891526U, // EFSCTUF + 536892412U, // EFSCTUI + 536899875U, // EFSCTUIZ + 26496U, // EFSDIV + 21875U, // EFSMUL + 536895935U, // EFSNABS + 536891559U, // EFSNEG + 19409U, // EFSSUB + 24585U, // EFSTSTEQ + 26032U, // EFSTSTGT + 26110U, // EFSTSTLT + 13233U, // EH_SjLj_LongJmp32 + 13609U, // EH_SjLj_LongJmp64 + 13252U, // EH_SjLj_SetJmp32 + 13628U, // EH_SjLj_SetJmp64 + 589825U, // EH_SjLj_Setup + 26529U, // EQV + 26529U, // EQV8 + 17987U, // EQV8o + 17987U, // EQVo + 536895971U, // EVABS + 16804243U, // EVADDIW + 536897549U, // EVADDSMIAAW + 536897681U, // EVADDSSIAAW + 536897615U, // EVADDUMIAAW + 536897747U, // EVADDUSIAAW + 26929U, // EVADDW + 20013U, // EVAND + 19507U, // EVANDC + 24566U, // EVCMPEQ + 25591U, // EVCMPGTS + 26394U, // EVCMPGTU + 25601U, // EVCMPLTS + 26404U, // EVCMPLTU + 536898309U, // EVCNTLSW + 536898558U, // EVCNTLZW + 25763U, // EVDIVWS + 26446U, // EVDIVWU + 26541U, // EVEQV + 536890171U, // EVEXTSB + 536891736U, // EVEXTSH + 536895962U, // EVFSABS + 19793U, // EVFSADD + 536891405U, // EVFSCFSF + 536892316U, // EVFSCFSI + 536891507U, // EVFSCFUF + 536892393U, // EVFSCFUI + 24555U, // EVFSCMPEQ + 26011U, // EVFSCMPGT + 26089U, // EVFSCMPLT + 536891479U, // EVFSCTSF + 536892344U, // EVFSCTSI + 536899854U, // EVFSCTSIZ + 536891479U, // EVFSCTUF + 536892421U, // EVFSCTUI + 536899854U, // EVFSCTUIZ + 26504U, // EVFSDIV + 21883U, // EVFSMUL + 536895944U, // EVFSNABS + 536891567U, // EVFSNEG + 19417U, // EVFSSUB + 24595U, // EVFSTSTEQ + 26042U, // EVFSTSTGT + 26120U, // EVFSTSTLT + 33574234U, // EVLDD + 604007606U, // EVLDDX + 33575110U, // EVLDH + 604007710U, // EVLDHX + 33581369U, // EVLDW + 604008463U, // EVLDWX + 33580305U, // EVLHHESPLAT + 604008203U, // EVLHHESPLATX + 33580330U, // EVLHHOSSPLAT + 604008230U, // EVLHHOSSPLATX + 33580344U, // EVLHHOUSPLAT + 604008245U, // EVLHHOUSPLATX + 33574703U, // EVLWHE + 604007681U, // EVLWHEX + 33579987U, // EVLWHOS + 604008175U, // EVLWHOSX + 33580797U, // EVLWHOU + 604008361U, // EVLWHOUX + 33580318U, // EVLWHSPLAT + 604008217U, // EVLWHSPLATX + 33580358U, // EVLWWSPLAT + 604008260U, // EVLWWSPLATX + 21141U, // EVMERGEHI + 22475U, // EVMERGEHILO + 22464U, // EVMERGELO + 21152U, // EVMERGELOHI + 18392U, // EVMHEGSMFAA + 22234U, // EVMHEGSMFAN + 18440U, // EVMHEGSMIAA + 22282U, // EVMHEGSMIAN + 18477U, // EVMHEGUMIAA + 22319U, // EVMHEGUMIAN + 20407U, // EVMHESMF + 18525U, // EVMHESMFA + 26585U, // EVMHESMFAAW + 27110U, // EVMHESMFANW + 21213U, // EVMHESMI + 18616U, // EVMHESMIA + 26650U, // EVMHESMIAAW + 27162U, // EVMHESMIANW + 20510U, // EVMHESSF + 18568U, // EVMHESSFA + 26611U, // EVMHESSFAAW + 27136U, // EVMHESSFANW + 26782U, // EVMHESSIAAW + 27240U, // EVMHESSIANW + 21252U, // EVMHEUMI + 18659U, // EVMHEUMIA + 26716U, // EVMHEUMIAAW + 27201U, // EVMHEUMIANW + 26848U, // EVMHEUSIAAW + 27279U, // EVMHEUSIANW + 18405U, // EVMHOGSMFAA + 22247U, // EVMHOGSMFAN + 18453U, // EVMHOGSMIAA + 22295U, // EVMHOGSMIAN + 18490U, // EVMHOGUMIAA + 22332U, // EVMHOGUMIAN + 20427U, // EVMHOSMF + 18547U, // EVMHOSMFA + 26598U, // EVMHOSMFAAW + 27123U, // EVMHOSMFANW + 21233U, // EVMHOSMI + 18638U, // EVMHOSMIA + 26690U, // EVMHOSMIAAW + 27188U, // EVMHOSMIANW + 20530U, // EVMHOSSF + 18590U, // EVMHOSSFA + 26624U, // EVMHOSSFAAW + 27149U, // EVMHOSSFANW + 26822U, // EVMHOSSIAAW + 27266U, // EVMHOSSIANW + 21282U, // EVMHOUMI + 18692U, // EVMHOUMIA + 26756U, // EVMHOUMIAAW + 27227U, // EVMHOUMIANW + 26888U, // EVMHOUSIAAW + 27305U, // EVMHOUSIANW + 536889747U, // EVMRA + 20417U, // EVMWHSMF + 18536U, // EVMWHSMFA + 21223U, // EVMWHSMI + 18627U, // EVMWHSMIA + 20520U, // EVMWHSSF + 18579U, // EVMWHSSFA + 21262U, // EVMWHUMI + 18670U, // EVMWHUMIA + 26677U, // EVMWLSMIAAW + 27175U, // EVMWLSMIANW + 26809U, // EVMWLSSIAAW + 27253U, // EVMWLSSIANW + 21272U, // EVMWLUMI + 18681U, // EVMWLUMIA + 26743U, // EVMWLUMIAAW + 27214U, // EVMWLUMIANW + 26875U, // EVMWLUSIAAW + 27292U, // EVMWLUSIANW + 20437U, // EVMWSMF + 18558U, // EVMWSMFA + 18418U, // EVMWSMFAA + 22260U, // EVMWSMFAN + 21243U, // EVMWSMI + 18649U, // EVMWSMIA + 18466U, // EVMWSMIAA + 22308U, // EVMWSMIAN + 20540U, // EVMWSSF + 18601U, // EVMWSSFA + 18429U, // EVMWSSFAA + 22271U, // EVMWSSFAN + 21292U, // EVMWUMI + 18703U, // EVMWUMIA + 18503U, // EVMWUMIAA + 22345U, // EVMWUMIAN + 19998U, // EVNAND + 536891576U, // EVNEG + 24871U, // EVNOR + 24884U, // EVOR + 19613U, // EVORC + 27076U, // EVRLW + 21543U, // EVRLWI + 536897856U, // EVRNDW + 2154328480U, // EVSEL + 27083U, // EVSLW + 21569U, // EVSLWI + 151016074U, // EVSPLATFI + 151016397U, // EVSPLATI + 25519U, // EVSRWIS + 26356U, // EVSRWIU + 25691U, // EVSRWS + 26432U, // EVSRWU + 33574250U, // EVSTDD + 604007614U, // EVSTDDX + 33575117U, // EVSTDH + 604007718U, // EVSTDHX + 33581384U, // EVSTDW + 604008471U, // EVSTDWX + 33574711U, // EVSTWHE + 604007690U, // EVSTWHEX + 33576887U, // EVSTWHO + 604007872U, // EVSTWHOX + 33574803U, // EVSTWWE + 604007700U, // EVSTWWEX + 33577040U, // EVSTWWO + 604007882U, // EVSTWWOX + 536897575U, // EVSUBFSMIAAW + 536897707U, // EVSUBFSSIAAW + 536897641U, // EVSUBFUMIAAW + 536897773U, // EVSUBFUSIAAW + 26977U, // EVSUBFW + 167799146U, // EVSUBIFW + 24915U, // EVXOR + 536890173U, // EXTSB + 536890173U, // EXTSB8 + 536890173U, // EXTSB8_32_64 + 536887609U, // EXTSB8o + 536887609U, // EXTSBo + 536891738U, // EXTSH + 536891738U, // EXTSH8 + 536891738U, // EXTSH8_32_64 + 536888050U, // EXTSH8o + 536888050U, // EXTSHo + 536898346U, // EXTSW + 21179U, // EXTSWSLI + 17283U, // EXTSWSLIo + 536898346U, // EXTSW_32 + 536898346U, // EXTSW_32_64 + 536888969U, // EXTSW_32_64o + 536888969U, // EXTSWo + 15429U, // EnforceIEIO + 536895911U, // FABSD + 536888635U, // FABSDo + 536895911U, // FABSS + 536888635U, // FABSSo + 19712U, // FADD + 25154U, // FADDS + 17772U, // FADDSo + 16866U, // FADDo + 0U, // FADDrtz + 536890781U, // FCFID + 536896148U, // FCFIDS + 536888711U, // FCFIDSo + 536897210U, // FCFIDU + 536896533U, // FCFIDUS + 536888778U, // FCFIDUSo + 536888822U, // FCFIDUo + 536887810U, // FCFIDo + 26374U, // FCMPUD + 26374U, // FCMPUS + 22369U, // FCPSGND + 17471U, // FCPSGNDo + 22369U, // FCPSGNS + 17471U, // FCPSGNSo + 536890800U, // FCTID + 536897220U, // FCTIDU + 536899893U, // FCTIDUZ + 536889109U, // FCTIDUZo + 536888831U, // FCTIDUo + 536899746U, // FCTIDZ + 536889075U, // FCTIDZo + 536887818U, // FCTIDo + 536897950U, // FCTIW + 536897336U, // FCTIWU + 536899904U, // FCTIWUZ + 536889119U, // FCTIWUZo + 536888875U, // FCTIWUo + 536899915U, // FCTIWZ + 536889129U, // FCTIWZo + 536888930U, // FCTIWo + 26490U, // FDIV + 25684U, // FDIVS + 17876U, // FDIVSo + 17980U, // FDIVo + 19720U, // FMADD + 25163U, // FMADDS + 17780U, // FMADDSo + 16873U, // FMADDo + 536895725U, // FMR + 536888603U, // FMRo + 19392U, // FMSUB + 25133U, // FMSUBS + 17746U, // FMSUBSo + 16723U, // FMSUBo + 21869U, // FMUL + 25538U, // FMULS + 17841U, // FMULSo + 17409U, // FMULo + 536895928U, // FNABSD + 536888642U, // FNABSDo + 536895928U, // FNABSS + 536888642U, // FNABSSo + 536891553U, // FNEGD + 536888022U, // FNEGDo + 536891553U, // FNEGS + 536888022U, // FNEGSo + 19729U, // FNMADD + 25173U, // FNMADDS + 17789U, // FNMADDSo + 16881U, // FNMADDo + 19401U, // FNMSUB + 25143U, // FNMSUBS + 17755U, // FNMSUBSo + 16731U, // FNMSUBo + 536891238U, // FRE + 536896248U, // FRES + 536888720U, // FRESo + 536887958U, // FREo + 536893000U, // FRIMD + 536888339U, // FRIMDo + 536893000U, // FRIMS + 536888339U, // FRIMSo + 536893298U, // FRIND + 536888413U, // FRINDo + 536893298U, // FRINS + 536888413U, // FRINSo + 536894570U, // FRIPD + 536888508U, // FRIPDo + 536894570U, // FRIPS + 536888508U, // FRIPSo + 536899828U, // FRIZD + 536889093U, // FRIZDo + 536899828U, // FRIZS + 536889093U, // FRIZSo + 536895271U, // FRSP + 536888539U, // FRSPo + 536891253U, // FRSQRTE + 536896256U, // FRSQRTES + 536888727U, // FRSQRTESo + 536887964U, // FRSQRTEo + 21784U, // FSELD + 17402U, // FSELDo + 21784U, // FSELS + 17402U, // FSELSo + 536897043U, // FSQRT + 536896523U, // FSQRTS + 536888761U, // FSQRTSo + 536888805U, // FSQRTo + 19384U, // FSUB + 25124U, // FSUBS + 17738U, // FSUBSo + 16716U, // FSUBo + 26513U, // FTDIV + 536897050U, // FTSQRT + 15012U, // GETtlsADDR + 13321U, // GETtlsADDR32 + 14998U, // GETtlsldADDR + 13306U, // GETtlsldADDR32 + 15335U, // HRFID + 561659U, // ICBI + 564095U, // ICBIEP + 216186U, // ICBLC + 214254U, // ICBLQ + 222565U, // ICBT + 222136U, // ICBTLS + 536891918U, // ICCCI + 21790U, // ISEL + 21790U, // ISEL8 + 15308U, // ISYNC + 184568186U, // LA + 604007996U, // LBARX + 2751491644U, // LBARXL + 604007892U, // LBEPX + 33583243U, // LBZ + 33583243U, // LBZ8 + 28020U, // LBZCIX + 201353047U, // LBZU + 201353047U, // LBZU8 + 218132450U, // LBZUX + 218132450U, // LBZUX8 + 604008529U, // LBZX + 604008529U, // LBZX8 + 28753U, // LBZXTLS + 28753U, // LBZXTLS_ + 28753U, // LBZXTLS_32 + 33574340U, // LD + 604008003U, // LDARX + 2751491651U, // LDARXL + 25860U, // LDAT + 604008024U, // LDBRX + 27989U, // LDCIX + 604007859U, // LDMX + 201352908U, // LDU + 218132366U, // LDUX + 604007645U, // LDX + 27869U, // LDXTLS + 27869U, // LDXTLS_ + 14907U, // LDgotTprelL + 13203U, // LDgotTprelL32 + 15320U, // LDtoc + 15159U, // LDtocBA + 15159U, // LDtocCPT + 14845U, // LDtocJTI + 14865U, // LDtocL + 33574266U, // LFD + 604007907U, // LFDEPX + 201352858U, // LFDU + 218132349U, // LFDUX + 604007625U, // LFDX + 604007534U, // LFIWAX + 604008552U, // LFIWZX + 33579800U, // LFS + 201352973U, // LFSU + 218132426U, // LFSUX + 604008150U, // LFSX + 33573043U, // LHA + 33573043U, // LHA8 + 604008010U, // LHARX + 2751491658U, // LHARXL + 201352846U, // LHAU + 201352846U, // LHAU8 + 218132305U, // LHAUX + 218132305U, // LHAUX8 + 604007517U, // LHAX + 604007517U, // LHAX8 + 604008039U, // LHBRX + 604008039U, // LHBRX8 + 604007924U, // LHEPX + 33583307U, // LHZ + 33583307U, // LHZ8 + 28028U, // LHZCIX + 201353053U, // LHZU + 201353053U, // LHZU8 + 218132457U, // LHZUX + 218132457U, // LHZUX8 + 604008544U, // LHZX + 604008544U, // LHZX8 + 28768U, // LHZXTLS + 28768U, // LHZXTLS_ + 28768U, // LHZXTLS_32 + 50352816U, // LI + 50352816U, // LI8 + 50357155U, // LIS + 50357155U, // LIS8 + 33581522U, // LMW + 21624U, // LSWI + 604007557U, // LVEBX + 604007727U, // LVEHX + 604008480U, // LVEWX + 604001629U, // LVSL + 604004738U, // LVSR + 604008439U, // LVX + 604001690U, // LVXL + 33573274U, // LWA + 604008017U, // LWARX + 2751491665U, // LWARXL + 25938U, // LWAT + 218132312U, // LWAUX + 604007551U, // LWAX + 604007551U, // LWAX_32 + 33573274U, // LWA_32 + 604008064U, // LWBRX + 604008064U, // LWBRX8 + 604007939U, // LWEPX + 33583443U, // LWZ + 33583443U, // LWZ8 + 28036U, // LWZCIX + 201353059U, // LWZU + 201353059U, // LWZU8 + 218132464U, // LWZUX + 218132464U, // LWZUX8 + 604008569U, // LWZX + 604008569U, // LWZX8 + 28793U, // LWZXTLS + 28793U, // LWZXTLS_ + 28793U, // LWZXTLS_32 + 15327U, // LWZtoc + 33574522U, // LXSD + 604007660U, // LXSDX + 604008520U, // LXSIBZX + 604008535U, // LXSIHZX + 604007542U, // LXSIWAX + 604008560U, // LXSIWZX + 33578823U, // LXSSP + 604007979U, // LXSSPX + 33580986U, // LXV + 604007481U, // LXVB16X + 604007447U, // LXVD2X + 604008133U, // LXVDSX + 604007500U, // LXVH8X + 21901U, // LXVL + 21816U, // LXVLL + 604007464U, // LXVW4X + 604008195U, // LXVWSX + 604008450U, // LXVX + 19852U, // MADDHD + 26279U, // MADDHDU + 19912U, // MADDLD + 712845U, // MBAR + 536891358U, // MCRF + 536896285U, // MCRFS + 552611U, // MCRXRX + 234901242U, // MFBHRBE + 549032U, // MFCR + 549032U, // MFCR8 + 549263U, // MFCTR + 549263U, // MFCTR8 + 536895635U, // MFDCR + 549650U, // MFFS + 536893357U, // MFFSCDRN + 251679569U, // MFFSCDRNI + 544515U, // MFFSCE + 536893348U, // MFFSCRN + 268456775U, // MFFSCRNI + 546134U, // MFFSL + 542114U, // MFFSo + 549087U, // MFLR + 549087U, // MFLR8 + 549230U, // MFMSR + 285233124U, // MFOCRF + 285233124U, // MFOCRF8 + 536895730U, // MFPMR + 536895834U, // MFSPR + 536895834U, // MFSPR8 + 302014824U, // MFSR + 536893304U, // MFSRIN + 536890194U, // MFTB + 7364954U, // MFTB8 + 536890953U, // MFVRD + 7889242U, // MFVRSAVE + 7889242U, // MFVRSAVEv + 549046U, // MFVSCR + 536890953U, // MFVSRD + 536890846U, // MFVSRLD + 536899928U, // MFVSRWZ + 20057U, // MODSD + 27345U, // MODSW + 20139U, // MODUD + 27520U, // MODUW + 15300U, // MSGSYNC + 15314U, // MSYNC + 536891380U, // MTCRF + 536891380U, // MTCRF8 + 549270U, // MTCTR + 549270U, // MTCTR8 + 549270U, // MTCTR8loop + 549270U, // MTCTRloop + 654516385U, // MTDCR + 706354U, // MTFSB0 + 706362U, // MTFSB1 + 20503U, // MTFSF + 21122U, // MTFSFI + 17274U, // MTFSFIo + 536891415U, // MTFSFb + 17102U, // MTFSFo + 549093U, // MTLR + 549093U, // MTLR8 + 536895861U, // MTMSR + 536890945U, // MTMSRD + 233452U, // MTOCRF + 233452U, // MTOCRF8 + 536895737U, // MTPMR + 536895841U, // MTSPR + 536895841U, // MTSPR8 + 254332U, // MTSR + 536893312U, // MTSRIN + 540892U, // MTVRSAVE + 721116U, // MTVRSAVEv + 549054U, // MTVSCR + 536890961U, // MTVSRD + 19809U, // MTVSRDD + 536889759U, // MTVSRWA + 536896611U, // MTVSRWS + 536899937U, // MTVSRWZ + 19860U, // MULHD + 26288U, // MULHDU + 17901U, // MULHDUo + 16890U, // MULHDo + 27020U, // MULHW + 26414U, // MULHWU + 17954U, // MULHWUo + 18010U, // MULHWo + 19920U, // MULLD + 16914U, // MULLDo + 21172U, // MULLI + 21172U, // MULLI8 + 27062U, // MULLW + 18026U, // MULLWo + 15036U, // MoveGOTtoLR + 15024U, // MovePCtoLR + 14367U, // MovePCtoLR8 + 19984U, // NAND + 19984U, // NAND8 + 16928U, // NAND8o + 16928U, // NANDo + 15435U, // NAP + 536891546U, // NEG + 536891546U, // NEG8 + 536888023U, // NEG8o + 536888023U, // NEGo + 15444U, // NOP + 12905U, // NOP_GT_PWR6 + 12917U, // NOP_GT_PWR7 + 24859U, // NOR + 24859U, // NOR8 + 17697U, // NOR8o + 17697U, // NORo + 24852U, // OR + 24852U, // OR8 + 17698U, // OR8o + 19601U, // ORC + 19601U, // ORC8 + 16842U, // ORC8o + 16842U, // ORCo + 21381U, // ORI + 21381U, // ORI8 + 25513U, // ORIS + 25513U, // ORIS8 + 17698U, // ORo + 536890209U, // POPCNTB + 536891027U, // POPCNTD + 536898379U, // POPCNTW + 15136U, // PPC32GOT + 15146U, // PPC32PICGOT + 21309U, // QVALIGNI + 21309U, // QVALIGNIb + 21309U, // QVALIGNIs + 21442U, // QVESPLATI + 21442U, // QVESPLATIb + 21442U, // QVESPLATIs + 536895909U, // QVFABS + 536895909U, // QVFABSs + 19710U, // QVFADD + 25152U, // QVFADDS + 25152U, // QVFADDSs + 536890779U, // QVFCFID + 536896146U, // QVFCFIDS + 536897208U, // QVFCFIDU + 536896531U, // QVFCFIDUS + 536890779U, // QVFCFIDb + 24535U, // QVFCMPEQ + 24535U, // QVFCMPEQb + 24535U, // QVFCMPEQbs + 25991U, // QVFCMPGT + 25991U, // QVFCMPGTb + 25991U, // QVFCMPGTbs + 26069U, // QVFCMPLT + 26069U, // QVFCMPLTb + 26069U, // QVFCMPLTbs + 22367U, // QVFCPSGN + 22367U, // QVFCPSGNs + 536890798U, // QVFCTID + 536897218U, // QVFCTIDU + 536899891U, // QVFCTIDUZ + 536899744U, // QVFCTIDZ + 536890798U, // QVFCTIDb + 536897948U, // QVFCTIW + 536897334U, // QVFCTIWU + 536899902U, // QVFCTIWUZ + 536899913U, // QVFCTIWZ + 21738U, // QVFLOGICAL + 21738U, // QVFLOGICALb + 21738U, // QVFLOGICALs + 19718U, // QVFMADD + 25161U, // QVFMADDS + 25161U, // QVFMADDSs + 536895723U, // QVFMR + 536895723U, // QVFMRb + 536895723U, // QVFMRs + 19390U, // QVFMSUB + 25131U, // QVFMSUBS + 25131U, // QVFMSUBSs + 21867U, // QVFMUL + 25536U, // QVFMULS + 25536U, // QVFMULSs + 536895926U, // QVFNABS + 536895926U, // QVFNABSs + 536891551U, // QVFNEG + 536891551U, // QVFNEGs + 19727U, // QVFNMADD + 25171U, // QVFNMADDS + 25171U, // QVFNMADDSs + 19399U, // QVFNMSUB + 25141U, // QVFNMSUBS + 25141U, // QVFNMSUBSs + 22156U, // QVFPERM + 22156U, // QVFPERMs + 536891236U, // QVFRE + 536896246U, // QVFRES + 536896246U, // QVFRESs + 536892998U, // QVFRIM + 536892998U, // QVFRIMs + 536893296U, // QVFRIN + 536893296U, // QVFRINs + 536894568U, // QVFRIP + 536894568U, // QVFRIPs + 536899826U, // QVFRIZ + 536899826U, // QVFRIZs + 536895269U, // QVFRSP + 536895269U, // QVFRSPs + 536891251U, // QVFRSQRTE + 536896254U, // QVFRSQRTES + 536896254U, // QVFRSQRTESs + 21782U, // QVFSEL + 21782U, // QVFSELb + 21782U, // QVFSELbb + 21782U, // QVFSELbs + 19382U, // QVFSUB + 25122U, // QVFSUBS + 25122U, // QVFSUBSs + 22356U, // QVFTSTNAN + 22356U, // QVFTSTNANb + 22356U, // QVFTSTNANbs + 19764U, // QVFXMADD + 25211U, // QVFXMADDS + 21892U, // QVFXMUL + 25545U, // QVFXMULS + 19737U, // QVFXXCPNMADD + 25182U, // QVFXXCPNMADDS + 19774U, // QVFXXMADD + 25222U, // QVFXXMADDS + 19751U, // QVFXXNPMADD + 25197U, // QVFXXNPMADDS + 318788117U, // QVGPCI + 604008294U, // QVLFCDUX + 603998723U, // QVLFCDUXA + 604007587U, // QVLFCDX + 603998643U, // QVLFCDXA + 604008371U, // QVLFCSUX + 603998767U, // QVLFCSUXA + 604008114U, // QVLFCSX + 603998683U, // QVLFCSXA + 604008114U, // QVLFCSXs + 218132347U, // QVLFDUX + 603998746U, // QVLFDUXA + 604007623U, // QVLFDX + 603998664U, // QVLFDXA + 604007623U, // QVLFDXb + 604007532U, // QVLFIWAX + 603998632U, // QVLFIWAXA + 604008550U, // QVLFIWZX + 603998822U, // QVLFIWZXA + 218132424U, // QVLFSUX + 603998790U, // QVLFSUXA + 604008148U, // QVLFSX + 603998704U, // QVLFSXA + 604008148U, // QVLFSXb + 604008148U, // QVLFSXs + 604007640U, // QVLPCLDX + 604008165U, // QVLPCLSX + 8416997U, // QVLPCLSXint + 604007650U, // QVLPCRDX + 604008185U, // QVLPCRSX + 604008304U, // QVSTFCDUX + 603998734U, // QVSTFCDUXA + 604001460U, // QVSTFCDUXI + 603998535U, // QVSTFCDUXIA + 604007596U, // QVSTFCDX + 603998653U, // QVSTFCDXA + 604001418U, // QVSTFCDXI + 603998489U, // QVSTFCDXIA + 604008381U, // QVSTFCSUX + 603998778U, // QVSTFCSUXA + 604001483U, // QVSTFCSUXI + 603998560U, // QVSTFCSUXIA + 604008123U, // QVSTFCSX + 603998693U, // QVSTFCSXA + 604001439U, // QVSTFCSXI + 603998512U, // QVSTFCSXIA + 604008123U, // QVSTFCSXs + 218312580U, // QVSTFDUX + 603998756U, // QVSTFDUXA + 604001472U, // QVSTFDUXI + 603998548U, // QVSTFDUXIA + 604007631U, // QVSTFDX + 603998673U, // QVSTFDXA + 604001429U, // QVSTFDXI + 603998501U, // QVSTFDXIA + 604007631U, // QVSTFDXb + 604008495U, // QVSTFIWX + 603998811U, // QVSTFIWXA + 218312657U, // QVSTFSUX + 603998800U, // QVSTFSUXA + 604001495U, // QVSTFSUXI + 603998573U, // QVSTFSUXIA + 218312657U, // QVSTFSUXs + 604008156U, // QVSTFSX + 603998713U, // QVSTFSXA + 604001450U, // QVSTFSXI + 603998524U, // QVSTFSXIA + 604008156U, // QVSTFSXs + 14944U, // RESTORE_CR + 15076U, // RESTORE_CRBIT + 14815U, // RESTORE_VRSAVE + 15353U, // RFCI + 15364U, // RFDI + 264837U, // RFEBB + 15369U, // RFI + 15336U, // RFID + 15358U, // RFMCI + 21759U, // RLDCL + 17385U, // RLDCLo + 24730U, // RLDCR + 17674U, // RLDCRo + 19536U, // RLDIC + 21766U, // RLDICL + 21766U, // RLDICL_32 + 21766U, // RLDICL_32_64 + 17393U, // RLDICL_32o + 17393U, // RLDICLo + 24750U, // RLDICR + 24750U, // RLDICR_32 + 17682U, // RLDICRo + 16811U, // RLDICo + 3355464397U, // RLDIMI + 3355460494U, // RLDIMIo + 3892335317U, // RLWIMI + 3892335317U, // RLWIMI8 + 3892331415U, // RLWIMI8o + 3892331415U, // RLWIMIo + 22102U, // RLWINM + 22102U, // RLWINM8 + 17434U, // RLWINM8o + 17434U, // RLWINMo + 22111U, // RLWNM + 22111U, // RLWNM8 + 17443U, // RLWNM8o + 17443U, // RLWNMo + 14518U, // ReadTB + 543908U, // SC + 13820U, // SELECT_CC_F16 + 13742U, // SELECT_CC_F4 + 14096U, // SELECT_CC_F8 + 13767U, // SELECT_CC_I4 + 14141U, // SELECT_CC_I8 + 14536U, // SELECT_CC_QBRC + 14565U, // SELECT_CC_QFRC + 14654U, // SELECT_CC_QSRC + 14778U, // SELECT_CC_SPE + 13713U, // SELECT_CC_SPE4 + 14625U, // SELECT_CC_VRRC + 14594U, // SELECT_CC_VSFRC + 14714U, // SELECT_CC_VSRC + 14683U, // SELECT_CC_VSSRC + 13835U, // SELECT_F16 + 13756U, // SELECT_F4 + 14110U, // SELECT_F8 + 13781U, // SELECT_I4 + 14315U, // SELECT_I8 + 14552U, // SELECT_QBRC + 14581U, // SELECT_QFRC + 14670U, // SELECT_QSRC + 14793U, // SELECT_SPE + 13729U, // SELECT_SPE4 + 14641U, // SELECT_VRRC + 14611U, // SELECT_VSFRC + 14730U, // SELECT_VSRC + 14700U, // SELECT_VSSRC + 536890188U, // SETB + 15256U, // SLBIA + 544576U, // SLBIE + 536891535U, // SLBIEG + 536891160U, // SLBMFEE + 536897385U, // SLBMFEV + 536891243U, // SLBMTE + 15284U, // SLBSYNC + 19950U, // SLD + 16922U, // SLDo + 27085U, // SLW + 27085U, // SLW8 + 18034U, // SLW8o + 18034U, // SLWo + 33583443U, // SPELWZ + 604008569U, // SPELWZX + 33581929U, // SPESTW + 604008514U, // SPESTWX + 14956U, // SPILL_CR + 15091U, // SPILL_CRBIT + 14831U, // SPILL_VRSAVE + 19680U, // SRAD + 21021U, // SRADI + 21021U, // SRADI_32 + 17203U, // SRADIo + 16859U, // SRADo + 26914U, // SRAW + 21519U, // SRAWI + 17312U, // SRAWIo + 17993U, // SRAWo + 20036U, // SRD + 16942U, // SRDo + 27340U, // SRW + 27340U, // SRW8 + 18040U, // SRW8o + 18040U, // SRWo + 33573748U, // STB + 33573748U, // STB8 + 27981U, // STBCIX + 603997899U, // STBCX + 604007899U, // STBEPX + 201533076U, // STBU + 201533076U, // STBU8 + 218312543U, // STBUX + 218312543U, // STBUX8 + 604007581U, // STBX + 604007581U, // STBX8 + 27805U, // STBXTLS + 27805U, // STBXTLS_ + 27805U, // STBXTLS_32 + 33574566U, // STD + 25866U, // STDAT + 604008031U, // STDBRX + 27996U, // STDCIX + 603997907U, // STDCX + 201533137U, // STDU + 218312596U, // STDUX + 604007675U, // STDX + 27899U, // STDXTLS + 27899U, // STDXTLS_ + 33574271U, // STFD + 604007915U, // STFDEPX + 201533088U, // STFDU + 218312582U, // STFDUX + 604007633U, // STFDX + 604008497U, // STFIWX + 33579812U, // STFS + 201533203U, // STFSU + 218312659U, // STFSUX + 604008158U, // STFSX + 33575301U, // STH + 33575301U, // STH8 + 604008046U, // STHBRX + 28004U, // STHCIX + 603997915U, // STHCX + 604007931U, // STHEPX + 201533166U, // STHU + 201533166U, // STHU8 + 218312610U, // STHUX + 218312610U, // STHUX8 + 604007751U, // STHX + 604007751U, // STHX8 + 27975U, // STHXTLS + 27975U, // STHXTLS_ + 27975U, // STHXTLS_32 + 33581527U, // STMW + 15448U, // STOP + 21630U, // STSWI + 604007564U, // STVEBX + 604007734U, // STVEHX + 604008487U, // STVEWX + 604008444U, // STVX + 604001696U, // STVXL + 33581929U, // STW + 33581929U, // STW8 + 25944U, // STWAT + 604008071U, // STWBRX + 28012U, // STWCIX + 603997923U, // STWCX + 604007946U, // STWEPX + 201533256U, // STWU + 201533256U, // STWU8 + 218312667U, // STWUX + 218312667U, // STWUX8 + 604008514U, // STWX + 604008514U, // STWX8 + 28738U, // STWXTLS + 28738U, // STWXTLS_ + 28738U, // STWXTLS_32 + 33574528U, // STXSD + 604007667U, // STXSDX + 604007572U, // STXSIBX + 604007572U, // STXSIBXv + 604007742U, // STXSIHX + 604007742U, // STXSIHXv + 604008505U, // STXSIWX + 33578830U, // STXSSP + 604007987U, // STXSSPX + 33580991U, // STXV + 604007490U, // STXVB16X + 604007455U, // STXVD2X + 604007508U, // STXVH8X + 21907U, // STXVL + 21823U, // STXVLL + 604007472U, // STXVW4X + 604008456U, // STXVX + 20401U, // SUBF + 20401U, // SUBF8 + 17095U, // SUBF8o + 19515U, // SUBFC + 19515U, // SUBFC8 + 16787U, // SUBFC8o + 16787U, // SUBFCo + 20264U, // SUBFE + 20264U, // SUBFE8 + 17021U, // SUBFE8o + 17021U, // SUBFEo + 19543U, // SUBFIC + 19543U, // SUBFIC8 + 536891221U, // SUBFME + 536891221U, // SUBFME8 + 536887949U, // SUBFME8o + 536887949U, // SUBFMEo + 536891299U, // SUBFZE + 536891299U, // SUBFZE8 + 536887998U, // SUBFZE8o + 536887998U, // SUBFZEo + 17095U, // SUBFo + 543880U, // SYNC + 722396U, // TABORT + 9191816U, // TABORTDC + 9716507U, // TABORTDCI + 9191888U, // TABORTWC + 9716519U, // TABORTWCI + 592514U, // TAILB + 592514U, // TAILB8 + 608340U, // TAILBA + 608340U, // TAILBA8 + 15470U, // TAILBCTR + 15470U, // TAILBCTR8 + 263252U, // TBEGIN + 546018U, // TCHECK + 15049U, // TCHECK_RET + 538003403U, // TCRETURNai + 538003310U, // TCRETURNai8 + 537988294U, // TCRETURNdi + 537986940U, // TCRETURNdi8 + 537944192U, // TCRETURNri + 537937802U, // TCRETURNri8 + 183950U, // TD + 184949U, // TDI + 819751U, // TEND + 15262U, // TLBIA + 661327687U, // TLBIE + 546062U, // TLBIEL + 536898659U, // TLBIVAX + 544193U, // TLBLD + 545453U, // TLBLI + 15341U, // TLBRE + 20317U, // TLBRE2 + 536899243U, // TLBSX + 28331U, // TLBSX2 + 18155U, // TLBSX2D + 15292U, // TLBSYNC + 15347U, // TLBWE + 20357U, // TLBWE2 + 15439U, // TRAP + 12895U, // TRECHKPT + 721928U, // TRECLAIM + 820533U, // TSR + 191293U, // TW + 185477U, // TWI + 536889240U, // UPDATE_VRSAVE + 14933U, // UpdateGBR + 19321U, // VABSDUB + 20874U, // VABSDUH + 27527U, // VABSDUW + 24652U, // VADDCUQ + 27511U, // VADDCUW + 24683U, // VADDECUQ + 22146U, // VADDEUQM + 23511U, // VADDFP + 25085U, // VADDSBS + 25428U, // VADDSHS + 25727U, // VADDSWS + 21966U, // VADDUBM + 25113U, // VADDUBS + 21994U, // VADDUDM + 22033U, // VADDUHM + 25456U, // VADDUHS + 22127U, // VADDUQM + 22216U, // VADDUWM + 25754U, // VADDUWS + 20014U, // VAND + 19508U, // VANDC + 19196U, // VAVGSB + 20761U, // VAVGSH + 27361U, // VAVGSW + 19339U, // VAVGUB + 20892U, // VAVGUH + 27545U, // VAVGUW + 19955U, // VBPERMD + 24606U, // VBPERMQ + 134246093U, // VCFSX + 536899277U, // VCFSX_0 + 134246299U, // VCFUX + 536899483U, // VCFUX_0 + 24784U, // VCIPHER + 26172U, // VCIPHERLAST + 536890378U, // VCLZB + 536891100U, // VCLZD + 536891879U, // VCLZH + 536889996U, // VCLZLSBB + 536898551U, // VCLZW + 23475U, // VCMPBFP + 17553U, // VCMPBFPo + 23574U, // VCMPEQFP + 17574U, // VCMPEQFPo + 19364U, // VCMPEQUB + 16705U, // VCMPEQUBo + 20154U, // VCMPEQUD + 16959U, // VCMPEQUDo + 20917U, // VCMPEQUH + 17146U, // VCMPEQUHo + 27570U, // VCMPEQUW + 18065U, // VCMPEQUWo + 23528U, // VCMPGEFP + 17563U, // VCMPGEFPo + 23584U, // VCMPGTFP + 17585U, // VCMPGTFPo + 19249U, // VCMPGTSB + 16686U, // VCMPGTSBo + 20072U, // VCMPGTSD + 16948U, // VCMPGTSDo + 20814U, // VCMPGTSH + 17127U, // VCMPGTSHo + 27424U, // VCMPGTSW + 18046U, // VCMPGTSWo + 19438U, // VCMPGTUB + 16740U, // VCMPGTUBo + 20164U, // VCMPGTUD + 16970U, // VCMPGTUDo + 20939U, // VCMPGTUH + 17157U, // VCMPGTUHo + 27605U, // VCMPGTUW + 18076U, // VCMPGTUWo + 19104U, // VCMPNEB + 16676U, // VCMPNEBo + 20693U, // VCMPNEH + 17117U, // VCMPNEHo + 26968U, // VCMPNEW + 18000U, // VCMPNEWo + 19456U, // VCMPNEZB + 16751U, // VCMPNEZBo + 20957U, // VCMPNEZH + 17168U, // VCMPNEZHo + 27629U, // VCMPNEZW + 18094U, // VCMPNEZWo + 134243572U, // VCTSXS + 536896756U, // VCTSXS_0 + 134243580U, // VCTUXS + 536896764U, // VCTUXS_0 + 536890385U, // VCTZB + 536891115U, // VCTZD + 536891886U, // VCTZH + 536890006U, // VCTZLSBB + 536898568U, // VCTZW + 26542U, // VEQV + 536894457U, // VEXPTEFP + 1207979655U, // VEXTRACTD + 1207978978U, // VEXTRACTUB + 1207980479U, // VEXTRACTUH + 1207987132U, // VEXTRACTUW + 536890536U, // VEXTSB2D + 536890536U, // VEXTSB2Ds + 536897477U, // VEXTSB2W + 536897477U, // VEXTSB2Ws + 536890546U, // VEXTSH2D + 536890546U, // VEXTSH2Ds + 536897487U, // VEXTSH2W + 536897487U, // VEXTSH2Ws + 536890556U, // VEXTSW2D + 536890556U, // VEXTSW2Ds + 28053U, // VEXTUBLX + 28278U, // VEXTUBRX + 28063U, // VEXTUHLX + 28303U, // VEXTUHRX + 28073U, // VEXTUWLX + 28313U, // VEXTUWRX + 536890598U, // VGBBD + 335563626U, // VINSERTB + 1207979676U, // VINSERTD + 335565179U, // VINSERTH + 1207987028U, // VINSERTW + 536894431U, // VLOGEFP + 23502U, // VMADDFP + 23594U, // VMAXFP + 19268U, // VMAXSB + 20082U, // VMAXSD + 20833U, // VMAXSH + 27441U, // VMAXSW + 19448U, // VMAXUB + 20174U, // VMAXUD + 20949U, // VMAXUH + 27615U, // VMAXUW + 25405U, // VMHADDSHS + 25416U, // VMHRADDSHS + 23566U, // VMINFP + 19232U, // VMINSB + 20064U, // VMINSD + 20797U, // VMINSH + 27407U, // VMINSW + 19347U, // VMINUB + 20146U, // VMINUD + 20900U, // VMINUH + 27553U, // VMINUW + 22022U, // VMLADDUHM + 26960U, // VMRGEW + 19113U, // VMRGHB + 20702U, // VMRGHH + 27003U, // VMRGHW + 19131U, // VMRGLB + 20710U, // VMRGLH + 27045U, // VMRGLW + 27318U, // VMRGOW + 21947U, // VMSUMMBM + 22003U, // VMSUMSHM + 25437U, // VMSUMSHS + 21975U, // VMSUMUBM + 22042U, // VMSUMUHM + 25465U, // VMSUMUHS + 536895544U, // VMUL10CUQ + 24661U, // VMUL10ECUQ + 24693U, // VMUL10EUQ + 536895534U, // VMUL10UQ + 19187U, // VMULESB + 20752U, // VMULESH + 27352U, // VMULESW + 19330U, // VMULEUB + 20883U, // VMULEUH + 27536U, // VMULEUW + 19240U, // VMULOSB + 20805U, // VMULOSH + 27415U, // VMULOSW + 19355U, // VMULOUB + 20908U, // VMULOUH + 27561U, // VMULOUW + 22225U, // VMULUWM + 19999U, // VNAND + 24774U, // VNCIPHER + 26158U, // VNCIPHERLAST + 536890757U, // VNEGD + 536897908U, // VNEGW + 23484U, // VNMSUBFP + 24872U, // VNOR + 24885U, // VOR + 19614U, // VORC + 22165U, // VPERM + 24832U, // VPERMR + 24898U, // VPERMXOR + 28187U, // VPKPX + 25564U, // VPKSDSS + 25630U, // VPKSDUS + 25573U, // VPKSHSS + 25648U, // VPKSHUS + 25582U, // VPKSWSS + 25666U, // VPKSWUS + 22180U, // VPKUDUM + 25639U, // VPKUDUS + 22189U, // VPKUHUM + 25657U, // VPKUHUS + 22198U, // VPKUWUM + 25675U, // VPKUWUS + 19151U, // VPMSUMB + 19964U, // VPMSUMD + 20730U, // VPMSUMH + 27101U, // VPMSUMW + 536890208U, // VPOPCNTB + 536891026U, // VPOPCNTD + 536891761U, // VPOPCNTH + 536898378U, // VPOPCNTW + 536890605U, // VPRTYBD + 536895428U, // VPRTYBQ + 536897832U, // VPRTYBW + 536894450U, // VREFP + 536892964U, // VRFIM + 536893289U, // VRFIN + 536894534U, // VRFIP + 536899792U, // VRFIZ + 19139U, // VRLB + 19943U, // VRLD + 21189U, // VRLDMI + 22094U, // VRLDNM + 20718U, // VRLH + 27077U, // VRLW + 21301U, // VRLWMI + 22110U, // VRLWNM + 536894467U, // VRSQRTEFP + 536899001U, // VSBOX + 21796U, // VSEL + 19667U, // VSHASIGMAD + 26901U, // VSHASIGMAW + 21854U, // VSL + 19145U, // VSLB + 19949U, // VSLD + 21340U, // VSLDOI + 20724U, // VSLH + 22488U, // VSLO + 26520U, // VSLV + 27084U, // VSLW + 134237016U, // VSPLTB + 134237016U, // VSPLTBs + 134238569U, // VSPLTH + 134238569U, // VSPLTHs + 151014157U, // VSPLTISB + 151015722U, // VSPLTISH + 151022322U, // VSPLTISW + 134245177U, // VSPLTW + 24963U, // VSR + 19070U, // VSRAB + 19679U, // VSRAD + 20671U, // VSRAH + 26913U, // VSRAW + 19181U, // VSRB + 20043U, // VSRD + 20746U, // VSRH + 22602U, // VSRO + 26548U, // VSRV + 27339U, // VSRW + 24643U, // VSUBCUQ + 27502U, // VSUBCUW + 24673U, // VSUBECUQ + 22136U, // VSUBEUQM + 23494U, // VSUBFP + 25076U, // VSUBSBS + 25396U, // VSUBSHS + 25718U, // VSUBSWS + 21957U, // VSUBUBM + 25104U, // VSUBUBS + 21985U, // VSUBUDM + 22013U, // VSUBUHM + 25447U, // VSUBUHS + 22118U, // VSUBUQM + 22207U, // VSUBUWM + 25745U, // VSUBUWS + 25708U, // VSUM2SWS + 25066U, // VSUM4SBS + 25386U, // VSUM4SHS + 25094U, // VSUM4UBS + 25736U, // VSUMSWS + 536899090U, // VUPKHPX + 536890116U, // VUPKHSB + 536891681U, // VUPKHSH + 536898281U, // VUPKHSW + 536899106U, // VUPKLPX + 536890135U, // VUPKLSB + 536891700U, // VUPKLSH + 536898300U, // VUPKLSW + 24916U, // VXOR + 117465428U, // V_SET0 + 117465428U, // V_SET0B + 117465428U, // V_SET0H + 9988850U, // V_SETALLONES + 9988850U, // V_SETALLONESB + 9988850U, // V_SETALLONESH + 550341U, // WAIT + 544545U, // WRTEE + 545402U, // WRTEEI + 24893U, // XOR + 24893U, // XOR8 + 17703U, // XOR8o + 21380U, // XORI + 21380U, // XORI8 + 25512U, // XORIS + 25512U, // XORIS8 + 17703U, // XORo + 536894157U, // XSABSDP + 536894776U, // XSABSQP + 22769U, // XSADDDP + 23734U, // XSADDQP + 22561U, // XSADDQPO + 24034U, // XSADDSP + 23203U, // XSCMPEQDP + 23171U, // XSCMPEXPDP + 23832U, // XSCMPEXPQP + 22831U, // XSCMPGEDP + 23263U, // XSCMPGTDP + 23101U, // XSCMPODP + 23802U, // XSCMPOQP + 23327U, // XSCMPUDP + 23883U, // XSCMPUQP + 23061U, // XSCPSGNDP + 23791U, // XSCPSGNQP + 536894514U, // XSCVDPHP + 536894724U, // XSCVDPQP + 536895208U, // XSCVDPSP + 536893331U, // XSCVDPSPN + 536896174U, // XSCVDPSXDS + 536896174U, // XSCVDPSXDSs + 536896684U, // XSCVDPSXWS + 536896684U, // XSCVDPSXWSs + 536896210U, // XSCVDPUXDS + 536896210U, // XSCVDPUXDSs + 536896720U, // XSCVDPUXWS + 536896720U, // XSCVDPUXWSs + 536894023U, // XSCVHPDP + 536894033U, // XSCVQPDP + 536893406U, // XSCVQPDPO + 536899765U, // XSCVQPSDZ + 536899946U, // XSCVQPSWZ + 536899776U, // XSCVQPUDZ + 536899957U, // XSCVQPUWZ + 536894655U, // XSCVSDQP + 536894043U, // XSCVSPDP + 536893320U, // XSCVSPDPN + 536893699U, // XSCVSXDDP + 536894964U, // XSCVSXDSP + 536894665U, // XSCVUDQP + 536893721U, // XSCVUXDDP + 536894986U, // XSCVUXDSP + 23337U, // XSDIVDP + 23893U, // XSDIVQP + 22592U, // XSDIVQPO + 24448U, // XSDIVSP + 23151U, // XSIEXPDP + 23822U, // XSIEXPQP + 1744853151U, // XSMADDADP + 1744854436U, // XSMADDASP + 1744853503U, // XSMADDMDP + 1744854718U, // XSMADDMSP + 1744854188U, // XSMADDQP + 1744853014U, // XSMADDQPO + 22759U, // XSMAXCDP + 23397U, // XSMAXDP + 22941U, // XSMAXJDP + 22749U, // XSMINCDP + 23083U, // XSMINDP + 22931U, // XSMINJDP + 1744853105U, // XSMSUBADP + 1744854390U, // XSMSUBASP + 1744853457U, // XSMSUBMDP + 1744854672U, // XSMSUBMSP + 1744854147U, // XSMSUBQP + 1744852981U, // XSMSUBQPO + 22951U, // XSMULDP + 23782U, // XSMULQP + 22571U, // XSMULQPO + 24166U, // XSMULSP + 536894137U, // XSNABSDP + 536894766U, // XSNABSQP + 536893805U, // XSNEGDP + 536894675U, // XSNEGQP + 1744853127U, // XSNMADDADP + 1744854412U, // XSNMADDASP + 1744853479U, // XSNMADDMDP + 1744854694U, // XSNMADDMSP + 1744854177U, // XSNMADDQP + 1744853002U, // XSNMADDQPO + 1744853081U, // XSNMSUBADP + 1744854366U, // XSNMSUBASP + 1744853433U, // XSNMSUBMDP + 1744854648U, // XSNMSUBMSP + 1744854136U, // XSNMSUBQP + 1744852969U, // XSNMSUBQPO + 536892260U, // XSRDPI + 536890463U, // XSRDPIC + 536892971U, // XSRDPIM + 536894541U, // XSRDPIP + 536899799U, // XSRDPIZ + 536893765U, // XSREDP + 536895019U, // XSRESP + 117740404U, // XSRQPI + 117747084U, // XSRQPIX + 117743547U, // XSRQPXP + 536895277U, // XSRSP + 536893781U, // XSRSQRTEDP + 536895035U, // XSRSQRTESP + 536894197U, // XSSQRTDP + 536894785U, // XSSQRTQP + 536893493U, // XSSQRTQPO + 536895329U, // XSSQRTSP + 22709U, // XSSUBDP + 23693U, // XSSUBQP + 22528U, // XSSUBQPO + 23994U, // XSSUBSP + 23346U, // XSTDIVDP + 536894207U, // XSTSQRTDP + 2281724103U, // XSTSTDCDP + 2281725078U, // XSTSTDCQP + 2281725388U, // XSTSTDCSP + 536894095U, // XSXEXPDP + 536894756U, // XSXEXPQP + 536893823U, // XSXSIGDP + 536894684U, // XSXSIGQP + 536894166U, // XVABSDP + 536895294U, // XVABSSP + 22778U, // XVADDDP + 24043U, // XVADDSP + 23214U, // XVCMPEQDP + 17529U, // XVCMPEQDPo + 24346U, // XVCMPEQSP + 17615U, // XVCMPEQSPo + 22842U, // XVCMPGEDP + 17517U, // XVCMPGEDPo + 24096U, // XVCMPGESP + 17603U, // XVCMPGESPo + 23274U, // XVCMPGTDP + 17541U, // XVCMPGTDPo + 24406U, // XVCMPGTSP + 17634U, // XVCMPGTSPo + 23072U, // XVCPSGNDP + 24276U, // XVCPSGNSP + 536895218U, // XVCVDPSP + 536896186U, // XVCVDPSXDS + 536896696U, // XVCVDPSXWS + 536896222U, // XVCVDPUXDS + 536896732U, // XVCVDPUXWS + 536895228U, // XVCVHPSP + 536894053U, // XVCVSPDP + 536894524U, // XVCVSPHP + 536896198U, // XVCVSPSXDS + 536896708U, // XVCVSPSXWS + 536896234U, // XVCVSPUXDS + 536896744U, // XVCVSPUXWS + 536893710U, // XVCVSXDDP + 536894975U, // XVCVSXDSP + 536894287U, // XVCVSXWDP + 536895388U, // XVCVSXWSP + 536893732U, // XVCVUXDDP + 536894997U, // XVCVUXDSP + 536894298U, // XVCVUXWDP + 536895399U, // XVCVUXWSP + 23366U, // XVDIVDP + 24467U, // XVDIVSP + 23161U, // XVIEXPDP + 24326U, // XVIEXPSP + 1744853162U, // XVMADDADP + 1744854447U, // XVMADDASP + 1744853514U, // XVMADDMDP + 1744854729U, // XVMADDMSP + 23406U, // XVMAXDP + 24498U, // XVMAXSP + 23092U, // XVMINDP + 24287U, // XVMINSP + 1744853116U, // XVMSUBADP + 1744854401U, // XVMSUBASP + 1744853468U, // XVMSUBMDP + 1744854683U, // XVMSUBMSP + 22960U, // XVMULDP + 24175U, // XVMULSP + 536894147U, // XVNABSDP + 536895284U, // XVNABSSP + 536893814U, // XVNEGDP + 536895059U, // XVNEGSP + 1744853139U, // XVNMADDADP + 1744854424U, // XVNMADDASP + 1744853491U, // XVNMADDMDP + 1744854706U, // XVNMADDMSP + 1744853093U, // XVNMSUBADP + 1744854378U, // XVNMSUBASP + 1744853445U, // XVNMSUBMDP + 1744854660U, // XVNMSUBMSP + 536892268U, // XVRDPI + 536890472U, // XVRDPIC + 536892980U, // XVRDPIM + 536894550U, // XVRDPIP + 536899808U, // XVRDPIZ + 536893773U, // XVREDP + 536895027U, // XVRESP + 536892284U, // XVRSPI + 536890481U, // XVRSPIC + 536892989U, // XVRSPIM + 536894559U, // XVRSPIP + 536899817U, // XVRSPIZ + 536893793U, // XVRSQRTEDP + 536895047U, // XVRSQRTESP + 536894229U, // XVSQRTDP + 536895350U, // XVSQRTSP + 22718U, // XVSUBDP + 24003U, // XVSUBSP + 23356U, // XVTDIVDP + 24457U, // XVTDIVSP + 536894218U, // XVTSQRTDP + 536895339U, // XVTSQRTSP + 2281724114U, // XVTSTDCDP + 2281725399U, // XVTSTDCSP + 536894105U, // XVXEXPDP + 536895248U, // XVXEXPSP + 536893833U, // XVXSIGDP + 536895068U, // XVXSIGSP + 536890938U, // XXBRD + 536891651U, // XXBRH + 536895527U, // XXBRQ + 536898244U, // XXBRW + 27592U, // XXEXTRACTUW + 2818599774U, // XXINSERTW + 19973U, // XXLAND + 19490U, // XXLANDC + 26526U, // XXLEQV + 19981U, // XXLNAND + 24856U, // XXLNOR + 24849U, // XXLOR + 19598U, // XXLORC + 24849U, // XXLORf + 24890U, // XXLXOR + 117465402U, // XXLXORdpz + 117465402U, // XXLXORspz + 117465402U, // XXLXORz + 27011U, // XXMRGHW + 27053U, // XXMRGLW + 22172U, // XXPERM + 21060U, // XXPERMDI + 21060U, // XXPERMDIs + 24840U, // XXPERMR + 21802U, // XXSEL + 21526U, // XXSLDWI + 21526U, // XXSLDWIs + 352340657U, // XXSPLTIB + 27457U, // XXSPLTW + 27457U, // XXSPLTWs + 183320U, // gBC + 182360U, // gBCA + 10812308U, // gBCAat + 188808U, // gBCCTR + 185678U, // gBCCTRL + 185594U, // gBCL + 182654U, // gBCLA + 10812324U, // gBCLAat + 188633U, // gBCLR + 185671U, // gBCLRL + 11336717U, // gBCLat + 11336625U, // gBCat }; static const uint16_t OpInfo1[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 0U, // DBG_VALUE - 0U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 0U, // BUNDLE - 0U, // LIFETIME_START - 0U, // LIFETIME_END - 0U, // STACKMAP - 0U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 0U, // PATCHABLE_FUNCTION_ENTER - 0U, // PATCHABLE_RET - 0U, // PATCHABLE_FUNCTION_EXIT - 0U, // PATCHABLE_TAIL_CALL - 0U, // PATCHABLE_EVENT_CALL - 0U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDE - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SSUBO - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_BSWAP - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 0U, // CFENCE8 - 0U, // CLRLSLDI - 0U, // CLRLSLDIo - 66U, // CLRLSLWI - 66U, // CLRLSLWIo - 32U, // CLRRDI - 32U, // CLRRDIo - 34U, // CLRRWI - 34U, // CLRRWIo - 0U, // CP_COPY_FIRST - 0U, // CP_COPYx - 0U, // CP_PASTE_LAST - 0U, // CP_PASTEx - 0U, // DCBFL - 0U, // DCBFLP - 0U, // DCBFx - 0U, // DCBTCT - 0U, // DCBTDS - 0U, // DCBTSTCT - 0U, // DCBTSTDS - 0U, // DCBTSTT - 0U, // DCBTSTx - 0U, // DCBTT - 0U, // DCBTx - 0U, // DFLOADf32 - 0U, // DFLOADf64 - 0U, // DFSTOREf32 - 0U, // DFSTOREf64 - 0U, // EXTLDI - 0U, // EXTLDIo - 66U, // EXTLWI - 66U, // EXTLWIo - 0U, // EXTRDI - 0U, // EXTRDIo - 66U, // EXTRWI - 66U, // EXTRWIo - 66U, // INSLWI - 66U, // INSLWIo - 0U, // INSRDI - 0U, // INSRDIo - 66U, // INSRWI - 66U, // INSRWIo - 0U, // LAx - 0U, // LIWAX - 0U, // LIWZX - 130U, // RLWIMIbm - 130U, // RLWIMIobm - 130U, // RLWINMbm - 130U, // RLWINMobm - 130U, // RLWNMbm - 130U, // RLWNMobm - 32U, // ROTRDI - 32U, // ROTRDIo - 34U, // ROTRWI - 34U, // ROTRWIo - 32U, // SLDI - 32U, // SLDIo - 34U, // SLWI - 34U, // SLWIo - 0U, // SPILLTOVSR_LD - 0U, // SPILLTOVSR_LDX - 0U, // SPILLTOVSR_ST - 0U, // SPILLTOVSR_STX - 32U, // SRDI - 32U, // SRDIo - 34U, // SRWI - 34U, // SRWIo - 0U, // STIWX - 4U, // SUBI - 4U, // SUBIC - 4U, // SUBICo - 4U, // SUBIS - 0U, // SUBPCIS - 0U, // XFLOADf32 - 0U, // XFLOADf64 - 0U, // XFSTOREf32 - 0U, // XFSTOREf64 - 38U, // ADD4 - 38U, // ADD4TLS - 38U, // ADD4o - 38U, // ADD8 - 38U, // ADD8TLS - 38U, // ADD8TLS_ - 38U, // ADD8o - 38U, // ADDC - 38U, // ADDC8 - 38U, // ADDC8o - 38U, // ADDCo - 38U, // ADDE - 38U, // ADDE8 - 38U, // ADDE8o - 38U, // ADDEo - 4U, // ADDI - 4U, // ADDI8 - 4U, // ADDIC - 4U, // ADDIC8 - 4U, // ADDICo - 4U, // ADDIS - 4U, // ADDIS8 - 0U, // ADDISdtprelHA - 0U, // ADDISdtprelHA32 - 0U, // ADDISgotTprelHA - 0U, // ADDIStlsgdHA - 0U, // ADDIStlsldHA - 0U, // ADDIStocHA - 0U, // ADDIdtprelL - 0U, // ADDIdtprelL32 - 0U, // ADDItlsgdL - 0U, // ADDItlsgdL32 - 0U, // ADDItlsgdLADDR - 0U, // ADDItlsgdLADDR32 - 0U, // ADDItlsldL - 0U, // ADDItlsldL32 - 0U, // ADDItlsldLADDR - 0U, // ADDItlsldLADDR32 - 0U, // ADDItocL - 0U, // ADDME - 0U, // ADDME8 - 0U, // ADDME8o - 0U, // ADDMEo - 0U, // ADDPCIS - 0U, // ADDZE - 0U, // ADDZE8 - 0U, // ADDZE8o - 0U, // ADDZEo - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 38U, // AND - 38U, // AND8 - 38U, // AND8o - 38U, // ANDC - 38U, // ANDC8 - 38U, // ANDC8o - 38U, // ANDCo - 8U, // ANDISo - 8U, // ANDISo8 - 8U, // ANDIo - 8U, // ANDIo8 - 0U, // ANDIo_1_EQ_BIT - 0U, // ANDIo_1_EQ_BIT8 - 0U, // ANDIo_1_GT_BIT - 0U, // ANDIo_1_GT_BIT8 - 38U, // ANDo - 0U, // ATOMIC_CMP_SWAP_I16 - 0U, // ATOMIC_CMP_SWAP_I32 - 0U, // ATOMIC_CMP_SWAP_I64 - 0U, // ATOMIC_CMP_SWAP_I8 - 0U, // ATOMIC_LOAD_ADD_I16 - 0U, // ATOMIC_LOAD_ADD_I32 - 0U, // ATOMIC_LOAD_ADD_I64 - 0U, // ATOMIC_LOAD_ADD_I8 - 0U, // ATOMIC_LOAD_AND_I16 - 0U, // ATOMIC_LOAD_AND_I32 - 0U, // ATOMIC_LOAD_AND_I64 - 0U, // ATOMIC_LOAD_AND_I8 - 0U, // ATOMIC_LOAD_MAX_I16 - 0U, // ATOMIC_LOAD_MAX_I32 - 0U, // ATOMIC_LOAD_MAX_I64 - 0U, // ATOMIC_LOAD_MAX_I8 - 0U, // ATOMIC_LOAD_MIN_I16 - 0U, // ATOMIC_LOAD_MIN_I32 - 0U, // ATOMIC_LOAD_MIN_I64 - 0U, // ATOMIC_LOAD_MIN_I8 - 0U, // ATOMIC_LOAD_NAND_I16 - 0U, // ATOMIC_LOAD_NAND_I32 - 0U, // ATOMIC_LOAD_NAND_I64 - 0U, // ATOMIC_LOAD_NAND_I8 - 0U, // ATOMIC_LOAD_OR_I16 - 0U, // ATOMIC_LOAD_OR_I32 - 0U, // ATOMIC_LOAD_OR_I64 - 0U, // ATOMIC_LOAD_OR_I8 - 0U, // ATOMIC_LOAD_SUB_I16 - 0U, // ATOMIC_LOAD_SUB_I32 - 0U, // ATOMIC_LOAD_SUB_I64 - 0U, // ATOMIC_LOAD_SUB_I8 - 0U, // ATOMIC_LOAD_UMAX_I16 - 0U, // ATOMIC_LOAD_UMAX_I32 - 0U, // ATOMIC_LOAD_UMAX_I64 - 0U, // ATOMIC_LOAD_UMAX_I8 - 0U, // ATOMIC_LOAD_UMIN_I16 - 0U, // ATOMIC_LOAD_UMIN_I32 - 0U, // ATOMIC_LOAD_UMIN_I64 - 0U, // ATOMIC_LOAD_UMIN_I8 - 0U, // ATOMIC_LOAD_XOR_I16 - 0U, // ATOMIC_LOAD_XOR_I32 - 0U, // ATOMIC_LOAD_XOR_I64 - 0U, // ATOMIC_LOAD_XOR_I8 - 0U, // ATOMIC_SWAP_I16 - 0U, // ATOMIC_SWAP_I32 - 0U, // ATOMIC_SWAP_I64 - 0U, // ATOMIC_SWAP_I8 - 0U, // ATTN - 0U, // B - 0U, // BA - 0U, // BC - 0U, // BCC - 0U, // BCCA - 0U, // BCCCTR - 0U, // BCCCTR8 - 0U, // BCCCTRL - 0U, // BCCCTRL8 - 0U, // BCCL - 0U, // BCCLA - 0U, // BCCLR - 0U, // BCCLRL - 0U, // BCCTR - 0U, // BCCTR8 - 0U, // BCCTR8n - 0U, // BCCTRL - 0U, // BCCTRL8 - 0U, // BCCTRL8n - 0U, // BCCTRLn - 0U, // BCCTRn - 42U, // BCDCFNo - 42U, // BCDCFSQo - 42U, // BCDCFZo - 38U, // BCDCPSGNo - 0U, // BCDCTNo - 0U, // BCDCTSQo - 42U, // BCDCTZo - 42U, // BCDSETSGNo - 198U, // BCDSRo - 198U, // BCDSo - 198U, // BCDTRUNCo - 38U, // BCDUSo - 38U, // BCDUTRUNCo - 0U, // BCL - 0U, // BCLR - 0U, // BCLRL - 0U, // BCLRLn - 0U, // BCLRn - 0U, // BCLalways - 0U, // BCLn - 0U, // BCTR - 0U, // BCTR8 - 0U, // BCTRL - 0U, // BCTRL8 - 0U, // BCTRL8_LDinto_toc - 0U, // BCn - 0U, // BDNZ - 0U, // BDNZ8 - 0U, // BDNZA - 0U, // BDNZAm - 0U, // BDNZAp - 0U, // BDNZL - 0U, // BDNZLA - 0U, // BDNZLAm - 0U, // BDNZLAp - 0U, // BDNZLR - 0U, // BDNZLR8 - 0U, // BDNZLRL - 0U, // BDNZLRLm - 0U, // BDNZLRLp - 0U, // BDNZLRm - 0U, // BDNZLRp - 0U, // BDNZLm - 0U, // BDNZLp - 0U, // BDNZm - 0U, // BDNZp - 0U, // BDZ - 0U, // BDZ8 - 0U, // BDZA - 0U, // BDZAm - 0U, // BDZAp - 0U, // BDZL - 0U, // BDZLA - 0U, // BDZLAm - 0U, // BDZLAp - 0U, // BDZLR - 0U, // BDZLR8 - 0U, // BDZLRL - 0U, // BDZLRLm - 0U, // BDZLRLp - 0U, // BDZLRm - 0U, // BDZLRp - 0U, // BDZLm - 0U, // BDZLp - 0U, // BDZm - 0U, // BDZp - 0U, // BL - 0U, // BL8 - 0U, // BL8_NOP - 0U, // BL8_NOP_TLS - 0U, // BL8_TLS - 0U, // BL8_TLS_ - 0U, // BLA - 0U, // BLA8 - 0U, // BLA8_NOP - 0U, // BLR - 0U, // BLR8 - 0U, // BLRL - 0U, // BL_TLS - 38U, // BPERMD - 38U, // BRINC - 0U, // CLRBHRB - 38U, // CMPB - 38U, // CMPB8 - 38U, // CMPD - 4U, // CMPDI - 38U, // CMPEQB - 38U, // CMPLD - 8U, // CMPLDI - 38U, // CMPLW - 8U, // CMPLWI - 0U, // CMPRB - 0U, // CMPRB8 - 38U, // CMPW - 4U, // CMPWI - 0U, // CNTLZD - 0U, // CNTLZDo - 0U, // CNTLZW - 0U, // CNTLZW8 - 0U, // CNTLZW8o - 0U, // CNTLZWo - 0U, // CNTTZD - 0U, // CNTTZDo - 0U, // CNTTZW - 0U, // CNTTZW8 - 0U, // CNTTZW8o - 0U, // CNTTZWo - 0U, // CP_ABORT - 42U, // CP_COPY - 42U, // CP_COPY8 - 42U, // CP_PASTE - 42U, // CP_PASTE8 - 42U, // CP_PASTE8o - 42U, // CP_PASTEo - 0U, // CR6SET - 0U, // CR6UNSET - 38U, // CRAND - 38U, // CRANDC - 38U, // CREQV - 38U, // CRNAND - 38U, // CRNOR - 38U, // CROR - 38U, // CRORC - 12U, // CRSET - 12U, // CRUNSET - 38U, // CRXOR - 0U, // CTRL_DEP - 0U, // DARN - 0U, // DCBA - 0U, // DCBF - 0U, // DCBFEP - 0U, // DCBI - 0U, // DCBST - 0U, // DCBSTEP - 0U, // DCBT - 0U, // DCBTEP - 0U, // DCBTST - 0U, // DCBTSTEP - 0U, // DCBZ - 0U, // DCBZEP - 0U, // DCBZL - 0U, // DCBZLEP - 0U, // DCCCI - 38U, // DIVD - 38U, // DIVDE - 38U, // DIVDEU - 38U, // DIVDEUo - 38U, // DIVDEo - 38U, // DIVDU - 38U, // DIVDUo - 38U, // DIVDo - 38U, // DIVW - 38U, // DIVWE - 38U, // DIVWEU - 38U, // DIVWEUo - 38U, // DIVWEo - 38U, // DIVWU - 38U, // DIVWUo - 38U, // DIVWo - 0U, // DSS - 0U, // DSSALL - 0U, // DST - 0U, // DST64 - 0U, // DSTST - 0U, // DSTST64 - 0U, // DSTSTT - 0U, // DSTSTT64 - 0U, // DSTT - 0U, // DSTT64 - 0U, // DYNALLOC - 0U, // DYNALLOC8 - 0U, // DYNAREAOFFSET - 0U, // DYNAREAOFFSET8 - 0U, // EFDABS - 38U, // EFDADD - 0U, // EFDCFS - 0U, // EFDCFSF - 0U, // EFDCFSI - 0U, // EFDCFSID - 0U, // EFDCFUF - 0U, // EFDCFUI - 0U, // EFDCFUID - 38U, // EFDCMPEQ - 38U, // EFDCMPGT - 38U, // EFDCMPLT - 0U, // EFDCTSF - 0U, // EFDCTSI - 0U, // EFDCTSIDZ - 0U, // EFDCTSIZ - 0U, // EFDCTUF - 0U, // EFDCTUI - 0U, // EFDCTUIDZ - 0U, // EFDCTUIZ - 38U, // EFDDIV - 38U, // EFDMUL - 0U, // EFDNABS - 0U, // EFDNEG - 38U, // EFDSUB - 38U, // EFDTSTEQ - 38U, // EFDTSTGT - 38U, // EFDTSTLT - 0U, // EFSABS - 38U, // EFSADD - 0U, // EFSCFD - 0U, // EFSCFSF - 0U, // EFSCFSI - 0U, // EFSCFUF - 0U, // EFSCFUI - 38U, // EFSCMPEQ - 38U, // EFSCMPGT - 38U, // EFSCMPLT - 0U, // EFSCTSF - 0U, // EFSCTSI - 0U, // EFSCTSIZ - 0U, // EFSCTUF - 0U, // EFSCTUI - 0U, // EFSCTUIZ - 38U, // EFSDIV - 38U, // EFSMUL - 0U, // EFSNABS - 0U, // EFSNEG - 38U, // EFSSUB - 38U, // EFSTSTEQ - 38U, // EFSTSTGT - 38U, // EFSTSTLT - 0U, // EH_SjLj_LongJmp32 - 0U, // EH_SjLj_LongJmp64 - 0U, // EH_SjLj_SetJmp32 - 0U, // EH_SjLj_SetJmp64 - 0U, // EH_SjLj_Setup - 38U, // EQV - 38U, // EQV8 - 38U, // EQV8o - 38U, // EQVo - 0U, // EVABS - 46U, // EVADDIW - 0U, // EVADDSMIAAW - 0U, // EVADDSSIAAW - 0U, // EVADDUMIAAW - 0U, // EVADDUSIAAW - 38U, // EVADDW - 38U, // EVAND - 38U, // EVANDC - 38U, // EVCMPEQ - 38U, // EVCMPGTS - 38U, // EVCMPGTU - 38U, // EVCMPLTS - 38U, // EVCMPLTU - 0U, // EVCNTLSW - 0U, // EVCNTLZW - 38U, // EVDIVWS - 38U, // EVDIVWU - 38U, // EVEQV - 0U, // EVEXTSB - 0U, // EVEXTSH - 0U, // EVFSABS - 38U, // EVFSADD - 0U, // EVFSCFSF - 0U, // EVFSCFSI - 0U, // EVFSCFUF - 0U, // EVFSCFUI - 38U, // EVFSCMPEQ - 38U, // EVFSCMPGT - 38U, // EVFSCMPLT - 0U, // EVFSCTSF - 0U, // EVFSCTSI - 0U, // EVFSCTSIZ - 0U, // EVFSCTUF - 0U, // EVFSCTUI - 0U, // EVFSCTUIZ - 38U, // EVFSDIV - 38U, // EVFSMUL - 0U, // EVFSNABS - 0U, // EVFSNEG - 38U, // EVFSSUB - 38U, // EVFSTSTEQ - 38U, // EVFSTSTGT - 38U, // EVFSTSTLT - 0U, // EVLDD - 0U, // EVLDDX - 0U, // EVLDH - 0U, // EVLDHX - 0U, // EVLDW - 0U, // EVLDWX - 0U, // EVLHHESPLAT - 0U, // EVLHHESPLATX - 0U, // EVLHHOSSPLAT - 0U, // EVLHHOSSPLATX - 0U, // EVLHHOUSPLAT - 0U, // EVLHHOUSPLATX - 0U, // EVLWHE - 0U, // EVLWHEX - 0U, // EVLWHOS - 0U, // EVLWHOSX - 0U, // EVLWHOU - 0U, // EVLWHOUX - 0U, // EVLWHSPLAT - 0U, // EVLWHSPLATX - 0U, // EVLWWSPLAT - 0U, // EVLWWSPLATX - 38U, // EVMERGEHI - 38U, // EVMERGEHILO - 38U, // EVMERGELO - 38U, // EVMERGELOHI - 38U, // EVMHEGSMFAA - 38U, // EVMHEGSMFAN - 38U, // EVMHEGSMIAA - 38U, // EVMHEGSMIAN - 38U, // EVMHEGUMIAA - 38U, // EVMHEGUMIAN - 38U, // EVMHESMF - 38U, // EVMHESMFA - 38U, // EVMHESMFAAW - 38U, // EVMHESMFANW - 38U, // EVMHESMI - 38U, // EVMHESMIA - 38U, // EVMHESMIAAW - 38U, // EVMHESMIANW - 38U, // EVMHESSF - 38U, // EVMHESSFA - 38U, // EVMHESSFAAW - 38U, // EVMHESSFANW - 38U, // EVMHESSIAAW - 38U, // EVMHESSIANW - 38U, // EVMHEUMI - 38U, // EVMHEUMIA - 38U, // EVMHEUMIAAW - 38U, // EVMHEUMIANW - 38U, // EVMHEUSIAAW - 38U, // EVMHEUSIANW - 38U, // EVMHOGSMFAA - 38U, // EVMHOGSMFAN - 38U, // EVMHOGSMIAA - 38U, // EVMHOGSMIAN - 38U, // EVMHOGUMIAA - 38U, // EVMHOGUMIAN - 38U, // EVMHOSMF - 38U, // EVMHOSMFA - 38U, // EVMHOSMFAAW - 38U, // EVMHOSMFANW - 38U, // EVMHOSMI - 38U, // EVMHOSMIA - 38U, // EVMHOSMIAAW - 38U, // EVMHOSMIANW - 38U, // EVMHOSSF - 38U, // EVMHOSSFA - 38U, // EVMHOSSFAAW - 38U, // EVMHOSSFANW - 38U, // EVMHOSSIAAW - 38U, // EVMHOSSIANW - 38U, // EVMHOUMI - 38U, // EVMHOUMIA - 38U, // EVMHOUMIAAW - 38U, // EVMHOUMIANW - 38U, // EVMHOUSIAAW - 38U, // EVMHOUSIANW - 0U, // EVMRA - 38U, // EVMWHSMF - 38U, // EVMWHSMFA - 38U, // EVMWHSMI - 38U, // EVMWHSMIA - 38U, // EVMWHSSF - 38U, // EVMWHSSFA - 38U, // EVMWHUMI - 38U, // EVMWHUMIA - 38U, // EVMWLSMIAAW - 38U, // EVMWLSMIANW - 38U, // EVMWLSSIAAW - 38U, // EVMWLSSIANW - 38U, // EVMWLUMI - 38U, // EVMWLUMIA - 38U, // EVMWLUMIAAW - 38U, // EVMWLUMIANW - 38U, // EVMWLUSIAAW - 38U, // EVMWLUSIANW - 38U, // EVMWSMF - 38U, // EVMWSMFA - 38U, // EVMWSMFAA - 38U, // EVMWSMFAN - 38U, // EVMWSMI - 38U, // EVMWSMIA - 38U, // EVMWSMIAA - 38U, // EVMWSMIAN - 38U, // EVMWSSF - 38U, // EVMWSSFA - 38U, // EVMWSSFAA - 38U, // EVMWSSFAN - 38U, // EVMWUMI - 38U, // EVMWUMIA - 38U, // EVMWUMIAA - 38U, // EVMWUMIAN - 38U, // EVNAND - 0U, // EVNEG - 38U, // EVNOR - 38U, // EVOR - 38U, // EVORC - 38U, // EVRLW - 34U, // EVRLWI - 0U, // EVRNDW - 0U, // EVSEL - 38U, // EVSLW - 34U, // EVSLWI - 0U, // EVSPLATFI - 0U, // EVSPLATI - 34U, // EVSRWIS - 34U, // EVSRWIU - 38U, // EVSRWS - 38U, // EVSRWU - 0U, // EVSTDD - 0U, // EVSTDDX - 0U, // EVSTDH - 0U, // EVSTDHX - 0U, // EVSTDW - 0U, // EVSTDWX - 0U, // EVSTWHE - 0U, // EVSTWHEX - 0U, // EVSTWHO - 0U, // EVSTWHOX - 0U, // EVSTWWE - 0U, // EVSTWWEX - 0U, // EVSTWWO - 0U, // EVSTWWOX - 0U, // EVSUBFSMIAAW - 0U, // EVSUBFSSIAAW - 0U, // EVSUBFUMIAAW - 0U, // EVSUBFUSIAAW - 38U, // EVSUBFW - 0U, // EVSUBIFW - 38U, // EVXOR - 0U, // EXTSB - 0U, // EXTSB8 - 0U, // EXTSB8_32_64 - 0U, // EXTSB8o - 0U, // EXTSBo - 0U, // EXTSH - 0U, // EXTSH8 - 0U, // EXTSH8_32_64 - 0U, // EXTSH8o - 0U, // EXTSHo - 0U, // EXTSW - 32U, // EXTSWSLI - 32U, // EXTSWSLIo - 0U, // EXTSW_32 - 0U, // EXTSW_32_64 - 0U, // EXTSW_32_64o - 0U, // EXTSWo - 0U, // EnforceIEIO - 0U, // FABSD - 0U, // FABSDo - 0U, // FABSS - 0U, // FABSSo - 38U, // FADD - 38U, // FADDS - 38U, // FADDSo - 38U, // FADDo - 0U, // FADDrtz - 0U, // FCFID - 0U, // FCFIDS - 0U, // FCFIDSo - 0U, // FCFIDU - 0U, // FCFIDUS - 0U, // FCFIDUSo - 0U, // FCFIDUo - 0U, // FCFIDo - 38U, // FCMPUD - 38U, // FCMPUS - 38U, // FCPSGND - 38U, // FCPSGNDo - 38U, // FCPSGNS - 38U, // FCPSGNSo - 0U, // FCTID - 0U, // FCTIDU - 0U, // FCTIDUZ - 0U, // FCTIDUZo - 0U, // FCTIDUo - 0U, // FCTIDZ - 0U, // FCTIDZo - 0U, // FCTIDo - 0U, // FCTIW - 0U, // FCTIWU - 0U, // FCTIWUZ - 0U, // FCTIWUZo - 0U, // FCTIWUo - 0U, // FCTIWZ - 0U, // FCTIWZo - 0U, // FCTIWo - 38U, // FDIV - 38U, // FDIVS - 38U, // FDIVSo - 38U, // FDIVo - 134U, // FMADD - 134U, // FMADDS - 134U, // FMADDSo - 134U, // FMADDo - 0U, // FMR - 0U, // FMRo - 134U, // FMSUB - 134U, // FMSUBS - 134U, // FMSUBSo - 134U, // FMSUBo - 38U, // FMUL - 38U, // FMULS - 38U, // FMULSo - 38U, // FMULo - 0U, // FNABSD - 0U, // FNABSDo - 0U, // FNABSS - 0U, // FNABSSo - 0U, // FNEGD - 0U, // FNEGDo - 0U, // FNEGS - 0U, // FNEGSo - 134U, // FNMADD - 134U, // FNMADDS - 134U, // FNMADDSo - 134U, // FNMADDo - 134U, // FNMSUB - 134U, // FNMSUBS - 134U, // FNMSUBSo - 134U, // FNMSUBo - 0U, // FRE - 0U, // FRES - 0U, // FRESo - 0U, // FREo - 0U, // FRIMD - 0U, // FRIMDo - 0U, // FRIMS - 0U, // FRIMSo - 0U, // FRIND - 0U, // FRINDo - 0U, // FRINS - 0U, // FRINSo - 0U, // FRIPD - 0U, // FRIPDo - 0U, // FRIPS - 0U, // FRIPSo - 0U, // FRIZD - 0U, // FRIZDo - 0U, // FRIZS - 0U, // FRIZSo - 0U, // FRSP - 0U, // FRSPo - 0U, // FRSQRTE - 0U, // FRSQRTES - 0U, // FRSQRTESo - 0U, // FRSQRTEo - 134U, // FSELD - 134U, // FSELDo - 134U, // FSELS - 134U, // FSELSo - 0U, // FSQRT - 0U, // FSQRTS - 0U, // FSQRTSo - 0U, // FSQRTo - 38U, // FSUB - 38U, // FSUBS - 38U, // FSUBSo - 38U, // FSUBo - 38U, // FTDIV - 0U, // FTSQRT - 0U, // GETtlsADDR - 0U, // GETtlsADDR32 - 0U, // GETtlsldADDR - 0U, // GETtlsldADDR32 - 0U, // HRFID - 0U, // ICBI - 0U, // ICBIEP - 0U, // ICBLC - 0U, // ICBLQ - 0U, // ICBT - 0U, // ICBTLS - 0U, // ICCCI - 134U, // ISEL - 134U, // ISEL8 - 0U, // ISYNC - 0U, // LA - 0U, // LBARX - 0U, // LBARXL - 0U, // LBEPX - 0U, // LBZ - 0U, // LBZ8 - 38U, // LBZCIX - 0U, // LBZU - 0U, // LBZU8 - 0U, // LBZUX - 0U, // LBZUX8 - 0U, // LBZX - 0U, // LBZX8 - 38U, // LBZXTLS - 38U, // LBZXTLS_ - 38U, // LBZXTLS_32 - 0U, // LD - 0U, // LDARX - 0U, // LDARXL - 34U, // LDAT - 0U, // LDBRX - 38U, // LDCIX - 0U, // LDMX - 0U, // LDU - 0U, // LDUX - 0U, // LDX - 38U, // LDXTLS - 38U, // LDXTLS_ - 0U, // LDgotTprelL - 0U, // LDgotTprelL32 - 0U, // LDtoc - 0U, // LDtocBA - 0U, // LDtocCPT - 0U, // LDtocJTI - 0U, // LDtocL - 0U, // LFD - 0U, // LFDEPX - 0U, // LFDU - 0U, // LFDUX - 0U, // LFDX - 0U, // LFIWAX - 0U, // LFIWZX - 0U, // LFS - 0U, // LFSU - 0U, // LFSUX - 0U, // LFSX - 0U, // LHA - 0U, // LHA8 - 0U, // LHARX - 0U, // LHARXL - 0U, // LHAU - 0U, // LHAU8 - 0U, // LHAUX - 0U, // LHAUX8 - 0U, // LHAX - 0U, // LHAX8 - 0U, // LHBRX - 0U, // LHBRX8 - 0U, // LHEPX - 0U, // LHZ - 0U, // LHZ8 - 38U, // LHZCIX - 0U, // LHZU - 0U, // LHZU8 - 0U, // LHZUX - 0U, // LHZUX8 - 0U, // LHZX - 0U, // LHZX8 - 38U, // LHZXTLS - 38U, // LHZXTLS_ - 38U, // LHZXTLS_32 - 0U, // LI - 0U, // LI8 - 0U, // LIS - 0U, // LIS8 - 0U, // LMW - 34U, // LSWI - 0U, // LVEBX - 0U, // LVEHX - 0U, // LVEWX - 0U, // LVSL - 0U, // LVSR - 0U, // LVX - 0U, // LVXL - 0U, // LWA - 0U, // LWARX - 0U, // LWARXL - 34U, // LWAT - 0U, // LWAUX - 0U, // LWAX - 0U, // LWAX_32 - 0U, // LWA_32 - 0U, // LWBRX - 0U, // LWBRX8 - 0U, // LWEPX - 0U, // LWZ - 0U, // LWZ8 - 38U, // LWZCIX - 0U, // LWZU - 0U, // LWZU8 - 0U, // LWZUX - 0U, // LWZUX8 - 0U, // LWZX - 0U, // LWZX8 - 38U, // LWZXTLS - 38U, // LWZXTLS_ - 38U, // LWZXTLS_32 - 0U, // LWZtoc - 0U, // LXSD - 0U, // LXSDX - 0U, // LXSIBZX - 0U, // LXSIHZX - 0U, // LXSIWAX - 0U, // LXSIWZX - 0U, // LXSSP - 0U, // LXSSPX - 0U, // LXV - 0U, // LXVB16X - 0U, // LXVD2X - 0U, // LXVDSX - 0U, // LXVH8X - 38U, // LXVL - 38U, // LXVLL - 0U, // LXVW4X - 0U, // LXVWSX - 0U, // LXVX - 134U, // MADDHD - 134U, // MADDHDU - 134U, // MADDLD - 0U, // MBAR - 0U, // MCRF - 0U, // MCRFS - 0U, // MCRXRX - 0U, // MFBHRBE - 0U, // MFCR - 0U, // MFCR8 - 0U, // MFCTR - 0U, // MFCTR8 - 0U, // MFDCR - 0U, // MFFS - 0U, // MFFSCDRN - 0U, // MFFSCDRNI - 0U, // MFFSCE - 0U, // MFFSCRN - 0U, // MFFSCRNI - 0U, // MFFSL - 0U, // MFFSo - 0U, // MFLR - 0U, // MFLR8 - 0U, // MFMSR - 0U, // MFOCRF - 0U, // MFOCRF8 - 0U, // MFPMR - 0U, // MFSPR - 0U, // MFSPR8 - 0U, // MFSR - 0U, // MFSRIN - 0U, // MFTB - 0U, // MFTB8 - 0U, // MFVRD - 0U, // MFVRSAVE - 0U, // MFVRSAVEv - 0U, // MFVSCR - 0U, // MFVSRD - 0U, // MFVSRLD - 0U, // MFVSRWZ - 38U, // MODSD - 38U, // MODSW - 38U, // MODUD - 38U, // MODUW - 0U, // MSGSYNC - 0U, // MSYNC - 0U, // MTCRF - 0U, // MTCRF8 - 0U, // MTCTR - 0U, // MTCTR8 - 0U, // MTCTR8loop - 0U, // MTCTRloop - 0U, // MTDCR - 0U, // MTFSB0 - 0U, // MTFSB1 - 134U, // MTFSF - 38U, // MTFSFI - 38U, // MTFSFIo - 0U, // MTFSFb - 134U, // MTFSFo - 0U, // MTLR - 0U, // MTLR8 - 0U, // MTMSR - 0U, // MTMSRD - 0U, // MTOCRF - 0U, // MTOCRF8 - 0U, // MTPMR - 0U, // MTSPR - 0U, // MTSPR8 - 0U, // MTSR - 0U, // MTSRIN - 0U, // MTVRSAVE - 0U, // MTVRSAVEv - 0U, // MTVSCR - 0U, // MTVSRD - 38U, // MTVSRDD - 0U, // MTVSRWA - 0U, // MTVSRWS - 0U, // MTVSRWZ - 38U, // MULHD - 38U, // MULHDU - 38U, // MULHDUo - 38U, // MULHDo - 38U, // MULHW - 38U, // MULHWU - 38U, // MULHWUo - 38U, // MULHWo - 38U, // MULLD - 38U, // MULLDo - 4U, // MULLI - 4U, // MULLI8 - 38U, // MULLW - 38U, // MULLWo - 0U, // MoveGOTtoLR - 0U, // MovePCtoLR - 0U, // MovePCtoLR8 - 38U, // NAND - 38U, // NAND8 - 38U, // NAND8o - 38U, // NANDo - 0U, // NAP - 0U, // NEG - 0U, // NEG8 - 0U, // NEG8o - 0U, // NEGo - 0U, // NOP - 0U, // NOP_GT_PWR6 - 0U, // NOP_GT_PWR7 - 38U, // NOR - 38U, // NOR8 - 38U, // NOR8o - 38U, // NORo - 38U, // OR - 38U, // OR8 - 38U, // OR8o - 38U, // ORC - 38U, // ORC8 - 38U, // ORC8o - 38U, // ORCo - 8U, // ORI - 8U, // ORI8 - 8U, // ORIS - 8U, // ORIS8 - 38U, // ORo - 0U, // POPCNTB - 0U, // POPCNTD - 0U, // POPCNTW - 0U, // PPC32GOT - 0U, // PPC32PICGOT - 262U, // QVALIGNI - 262U, // QVALIGNIb - 262U, // QVALIGNIs - 16U, // QVESPLATI - 16U, // QVESPLATIb - 16U, // QVESPLATIs - 0U, // QVFABS - 0U, // QVFABSs - 38U, // QVFADD - 38U, // QVFADDS - 38U, // QVFADDSs - 0U, // QVFCFID - 0U, // QVFCFIDS - 0U, // QVFCFIDU - 0U, // QVFCFIDUS - 0U, // QVFCFIDb - 38U, // QVFCMPEQ - 38U, // QVFCMPEQb - 38U, // QVFCMPEQbs - 38U, // QVFCMPGT - 38U, // QVFCMPGTb - 38U, // QVFCMPGTbs - 38U, // QVFCMPLT - 38U, // QVFCMPLTb - 38U, // QVFCMPLTbs - 38U, // QVFCPSGN - 38U, // QVFCPSGNs - 0U, // QVFCTID - 0U, // QVFCTIDU - 0U, // QVFCTIDUZ - 0U, // QVFCTIDZ - 0U, // QVFCTIDb - 0U, // QVFCTIW - 0U, // QVFCTIWU - 0U, // QVFCTIWUZ - 0U, // QVFCTIWZ - 326U, // QVFLOGICAL - 326U, // QVFLOGICALb - 326U, // QVFLOGICALs - 18U, // QVFMADD - 18U, // QVFMADDS - 18U, // QVFMADDSs - 0U, // QVFMR - 0U, // QVFMRb - 0U, // QVFMRs - 18U, // QVFMSUB - 18U, // QVFMSUBS - 18U, // QVFMSUBSs - 38U, // QVFMUL - 38U, // QVFMULS - 38U, // QVFMULSs - 0U, // QVFNABS - 0U, // QVFNABSs - 0U, // QVFNEG - 0U, // QVFNEGs - 18U, // QVFNMADD - 18U, // QVFNMADDS - 18U, // QVFNMADDSs - 18U, // QVFNMSUB - 18U, // QVFNMSUBS - 18U, // QVFNMSUBSs - 134U, // QVFPERM - 134U, // QVFPERMs - 0U, // QVFRE - 0U, // QVFRES - 0U, // QVFRESs - 0U, // QVFRIM - 0U, // QVFRIMs - 0U, // QVFRIN - 0U, // QVFRINs - 0U, // QVFRIP - 0U, // QVFRIPs - 0U, // QVFRIZ - 0U, // QVFRIZs - 0U, // QVFRSP - 0U, // QVFRSPs - 0U, // QVFRSQRTE - 0U, // QVFRSQRTES - 0U, // QVFRSQRTESs - 18U, // QVFSEL - 18U, // QVFSELb - 18U, // QVFSELbb - 18U, // QVFSELbs - 38U, // QVFSUB - 38U, // QVFSUBS - 38U, // QVFSUBSs - 38U, // QVFTSTNAN - 38U, // QVFTSTNANb - 38U, // QVFTSTNANbs - 18U, // QVFXMADD - 18U, // QVFXMADDS - 38U, // QVFXMUL - 38U, // QVFXMULS - 18U, // QVFXXCPNMADD - 18U, // QVFXXCPNMADDS - 18U, // QVFXXMADD - 18U, // QVFXXMADDS - 18U, // QVFXXNPMADD - 18U, // QVFXXNPMADDS - 0U, // QVGPCI - 0U, // QVLFCDUX - 0U, // QVLFCDUXA - 0U, // QVLFCDX - 0U, // QVLFCDXA - 0U, // QVLFCSUX - 0U, // QVLFCSUXA - 0U, // QVLFCSX - 0U, // QVLFCSXA - 0U, // QVLFCSXs - 0U, // QVLFDUX - 0U, // QVLFDUXA - 0U, // QVLFDX - 0U, // QVLFDXA - 0U, // QVLFDXb - 0U, // QVLFIWAX - 0U, // QVLFIWAXA - 0U, // QVLFIWZX - 0U, // QVLFIWZXA - 0U, // QVLFSUX - 0U, // QVLFSUXA - 0U, // QVLFSX - 0U, // QVLFSXA - 0U, // QVLFSXb - 0U, // QVLFSXs - 0U, // QVLPCLDX - 0U, // QVLPCLSX - 0U, // QVLPCLSXint - 0U, // QVLPCRDX - 0U, // QVLPCRSX - 0U, // QVSTFCDUX - 0U, // QVSTFCDUXA - 0U, // QVSTFCDUXI - 0U, // QVSTFCDUXIA - 0U, // QVSTFCDX - 0U, // QVSTFCDXA - 0U, // QVSTFCDXI - 0U, // QVSTFCDXIA - 0U, // QVSTFCSUX - 0U, // QVSTFCSUXA - 0U, // QVSTFCSUXI - 0U, // QVSTFCSUXIA - 0U, // QVSTFCSX - 0U, // QVSTFCSXA - 0U, // QVSTFCSXI - 0U, // QVSTFCSXIA - 0U, // QVSTFCSXs - 0U, // QVSTFDUX - 0U, // QVSTFDUXA - 0U, // QVSTFDUXI - 0U, // QVSTFDUXIA - 0U, // QVSTFDX - 0U, // QVSTFDXA - 0U, // QVSTFDXI - 0U, // QVSTFDXIA - 0U, // QVSTFDXb - 0U, // QVSTFIWX - 0U, // QVSTFIWXA - 0U, // QVSTFSUX - 0U, // QVSTFSUXA - 0U, // QVSTFSUXI - 0U, // QVSTFSUXIA - 0U, // QVSTFSUXs - 0U, // QVSTFSX - 0U, // QVSTFSXA - 0U, // QVSTFSXI - 0U, // QVSTFSXIA - 0U, // QVSTFSXs - 0U, // RESTORE_CR - 0U, // RESTORE_CRBIT - 0U, // RESTORE_VRSAVE - 0U, // RFCI - 0U, // RFDI - 0U, // RFEBB - 0U, // RFI - 0U, // RFID - 0U, // RFMCI - 6U, // RLDCL - 6U, // RLDCLo - 6U, // RLDCR - 6U, // RLDCRo - 0U, // RLDIC - 0U, // RLDICL - 0U, // RLDICL_32 - 0U, // RLDICL_32_64 - 0U, // RLDICL_32o - 0U, // RLDICLo - 0U, // RLDICR - 0U, // RLDICR_32 - 0U, // RLDICRo - 0U, // RLDICo - 0U, // RLDIMI - 0U, // RLDIMIo - 0U, // RLWIMI - 0U, // RLWIMI8 - 0U, // RLWIMI8o - 0U, // RLWIMIo - 578U, // RLWINM - 578U, // RLWINM8 - 578U, // RLWINM8o - 578U, // RLWINMo - 582U, // RLWNM - 582U, // RLWNM8 - 582U, // RLWNM8o - 582U, // RLWNMo - 0U, // ReadTB - 0U, // SC - 0U, // SELECT_CC_F16 - 0U, // SELECT_CC_F4 - 0U, // SELECT_CC_F8 - 0U, // SELECT_CC_I4 - 0U, // SELECT_CC_I8 - 0U, // SELECT_CC_QBRC - 0U, // SELECT_CC_QFRC - 0U, // SELECT_CC_QSRC - 0U, // SELECT_CC_SPE - 0U, // SELECT_CC_SPE4 - 0U, // SELECT_CC_VRRC - 0U, // SELECT_CC_VSFRC - 0U, // SELECT_CC_VSRC - 0U, // SELECT_CC_VSSRC - 0U, // SELECT_F16 - 0U, // SELECT_F4 - 0U, // SELECT_F8 - 0U, // SELECT_I4 - 0U, // SELECT_I8 - 0U, // SELECT_QBRC - 0U, // SELECT_QFRC - 0U, // SELECT_QSRC - 0U, // SELECT_SPE - 0U, // SELECT_SPE4 - 0U, // SELECT_VRRC - 0U, // SELECT_VSFRC - 0U, // SELECT_VSRC - 0U, // SELECT_VSSRC - 0U, // SETB - 0U, // SLBIA - 0U, // SLBIE - 0U, // SLBIEG - 0U, // SLBMFEE - 0U, // SLBMFEV - 0U, // SLBMTE - 0U, // SLBSYNC - 38U, // SLD - 38U, // SLDo - 38U, // SLW - 38U, // SLW8 - 38U, // SLW8o - 38U, // SLWo - 0U, // SPELWZ - 0U, // SPELWZX - 0U, // SPESTW - 0U, // SPESTWX - 0U, // SPILL_CR - 0U, // SPILL_CRBIT - 0U, // SPILL_VRSAVE - 38U, // SRAD - 32U, // SRADI - 32U, // SRADI_32 - 32U, // SRADIo - 38U, // SRADo - 38U, // SRAW - 34U, // SRAWI - 34U, // SRAWIo - 38U, // SRAWo - 38U, // SRD - 38U, // SRDo - 38U, // SRW - 38U, // SRW8 - 38U, // SRW8o - 38U, // SRWo - 0U, // STB - 0U, // STB8 - 38U, // STBCIX - 0U, // STBCX - 0U, // STBEPX - 0U, // STBU - 0U, // STBU8 - 0U, // STBUX - 0U, // STBUX8 - 0U, // STBX - 0U, // STBX8 - 38U, // STBXTLS - 38U, // STBXTLS_ - 38U, // STBXTLS_32 - 0U, // STD - 34U, // STDAT - 0U, // STDBRX - 38U, // STDCIX - 0U, // STDCX - 0U, // STDU - 0U, // STDUX - 0U, // STDX - 38U, // STDXTLS - 38U, // STDXTLS_ - 0U, // STFD - 0U, // STFDEPX - 0U, // STFDU - 0U, // STFDUX - 0U, // STFDX - 0U, // STFIWX - 0U, // STFS - 0U, // STFSU - 0U, // STFSUX - 0U, // STFSX - 0U, // STH - 0U, // STH8 - 0U, // STHBRX - 38U, // STHCIX - 0U, // STHCX - 0U, // STHEPX - 0U, // STHU - 0U, // STHU8 - 0U, // STHUX - 0U, // STHUX8 - 0U, // STHX - 0U, // STHX8 - 38U, // STHXTLS - 38U, // STHXTLS_ - 38U, // STHXTLS_32 - 0U, // STMW - 0U, // STOP - 34U, // STSWI - 0U, // STVEBX - 0U, // STVEHX - 0U, // STVEWX - 0U, // STVX - 0U, // STVXL - 0U, // STW - 0U, // STW8 - 34U, // STWAT - 0U, // STWBRX - 38U, // STWCIX - 0U, // STWCX - 0U, // STWEPX - 0U, // STWU - 0U, // STWU8 - 0U, // STWUX - 0U, // STWUX8 - 0U, // STWX - 0U, // STWX8 - 38U, // STWXTLS - 38U, // STWXTLS_ - 38U, // STWXTLS_32 - 0U, // STXSD - 0U, // STXSDX - 0U, // STXSIBX - 0U, // STXSIBXv - 0U, // STXSIHX - 0U, // STXSIHXv - 0U, // STXSIWX - 0U, // STXSSP - 0U, // STXSSPX - 0U, // STXV - 0U, // STXVB16X - 0U, // STXVD2X - 0U, // STXVH8X - 38U, // STXVL - 38U, // STXVLL - 0U, // STXVW4X - 0U, // STXVX - 38U, // SUBF - 38U, // SUBF8 - 38U, // SUBF8o - 38U, // SUBFC - 38U, // SUBFC8 - 38U, // SUBFC8o - 38U, // SUBFCo - 38U, // SUBFE - 38U, // SUBFE8 - 38U, // SUBFE8o - 38U, // SUBFEo - 4U, // SUBFIC - 4U, // SUBFIC8 - 0U, // SUBFME - 0U, // SUBFME8 - 0U, // SUBFME8o - 0U, // SUBFMEo - 0U, // SUBFZE - 0U, // SUBFZE8 - 0U, // SUBFZE8o - 0U, // SUBFZEo - 38U, // SUBFo - 0U, // SYNC - 0U, // TABORT - 0U, // TABORTDC - 0U, // TABORTDCI - 0U, // TABORTWC - 0U, // TABORTWCI - 0U, // TAILB - 0U, // TAILB8 - 0U, // TAILBA - 0U, // TAILBA8 - 0U, // TAILBCTR - 0U, // TAILBCTR8 - 0U, // TBEGIN - 0U, // TCHECK - 0U, // TCHECK_RET - 0U, // TCRETURNai - 0U, // TCRETURNai8 - 0U, // TCRETURNdi - 0U, // TCRETURNdi8 - 0U, // TCRETURNri - 0U, // TCRETURNri8 - 38U, // TD - 4U, // TDI - 0U, // TEND - 0U, // TLBIA - 0U, // TLBIE - 0U, // TLBIEL - 0U, // TLBIVAX - 0U, // TLBLD - 0U, // TLBLI - 0U, // TLBRE - 38U, // TLBRE2 - 0U, // TLBSX - 38U, // TLBSX2 - 38U, // TLBSX2D - 0U, // TLBSYNC - 0U, // TLBWE - 38U, // TLBWE2 - 0U, // TRAP - 0U, // TRECHKPT - 0U, // TRECLAIM - 0U, // TSR - 38U, // TW - 4U, // TWI - 0U, // UPDATE_VRSAVE - 0U, // UpdateGBR - 38U, // VABSDUB - 38U, // VABSDUH - 38U, // VABSDUW - 38U, // VADDCUQ - 38U, // VADDCUW - 134U, // VADDECUQ - 134U, // VADDEUQM - 38U, // VADDFP - 38U, // VADDSBS - 38U, // VADDSHS - 38U, // VADDSWS - 38U, // VADDUBM - 38U, // VADDUBS - 38U, // VADDUDM - 38U, // VADDUHM - 38U, // VADDUHS - 38U, // VADDUQM - 38U, // VADDUWM - 38U, // VADDUWS - 38U, // VAND - 38U, // VANDC - 38U, // VAVGSB - 38U, // VAVGSH - 38U, // VAVGSW - 38U, // VAVGUB - 38U, // VAVGUH - 38U, // VAVGUW - 38U, // VBPERMD - 38U, // VBPERMQ - 1U, // VCFSX - 1U, // VCFSX_0 - 1U, // VCFUX - 1U, // VCFUX_0 - 38U, // VCIPHER - 38U, // VCIPHERLAST - 0U, // VCLZB - 0U, // VCLZD - 0U, // VCLZH - 0U, // VCLZLSBB - 0U, // VCLZW - 38U, // VCMPBFP - 38U, // VCMPBFPo - 38U, // VCMPEQFP - 38U, // VCMPEQFPo - 38U, // VCMPEQUB - 38U, // VCMPEQUBo - 38U, // VCMPEQUD - 38U, // VCMPEQUDo - 38U, // VCMPEQUH - 38U, // VCMPEQUHo - 38U, // VCMPEQUW - 38U, // VCMPEQUWo - 38U, // VCMPGEFP - 38U, // VCMPGEFPo - 38U, // VCMPGTFP - 38U, // VCMPGTFPo - 38U, // VCMPGTSB - 38U, // VCMPGTSBo - 38U, // VCMPGTSD - 38U, // VCMPGTSDo - 38U, // VCMPGTSH - 38U, // VCMPGTSHo - 38U, // VCMPGTSW - 38U, // VCMPGTSWo - 38U, // VCMPGTUB - 38U, // VCMPGTUBo - 38U, // VCMPGTUD - 38U, // VCMPGTUDo - 38U, // VCMPGTUH - 38U, // VCMPGTUHo - 38U, // VCMPGTUW - 38U, // VCMPGTUWo - 38U, // VCMPNEB - 38U, // VCMPNEBo - 38U, // VCMPNEH - 38U, // VCMPNEHo - 38U, // VCMPNEW - 38U, // VCMPNEWo - 38U, // VCMPNEZB - 38U, // VCMPNEZBo - 38U, // VCMPNEZH - 38U, // VCMPNEZHo - 38U, // VCMPNEZW - 38U, // VCMPNEZWo - 1U, // VCTSXS - 1U, // VCTSXS_0 - 1U, // VCTUXS - 1U, // VCTUXS_0 - 0U, // VCTZB - 0U, // VCTZD - 0U, // VCTZH - 0U, // VCTZLSBB - 0U, // VCTZW - 38U, // VEQV - 0U, // VEXPTEFP - 1U, // VEXTRACTD - 1U, // VEXTRACTUB - 1U, // VEXTRACTUH - 1U, // VEXTRACTUW - 0U, // VEXTSB2D - 0U, // VEXTSB2Ds - 0U, // VEXTSB2W - 0U, // VEXTSB2Ws - 0U, // VEXTSH2D - 0U, // VEXTSH2Ds - 0U, // VEXTSH2W - 0U, // VEXTSH2Ws - 0U, // VEXTSW2D - 0U, // VEXTSW2Ds - 38U, // VEXTUBLX - 38U, // VEXTUBRX - 38U, // VEXTUHLX - 38U, // VEXTUHRX - 38U, // VEXTUWLX - 38U, // VEXTUWRX - 0U, // VGBBD - 0U, // VINSERTB - 1U, // VINSERTD - 0U, // VINSERTH - 1U, // VINSERTW - 0U, // VLOGEFP - 134U, // VMADDFP - 38U, // VMAXFP - 38U, // VMAXSB - 38U, // VMAXSD - 38U, // VMAXSH - 38U, // VMAXSW - 38U, // VMAXUB - 38U, // VMAXUD - 38U, // VMAXUH - 38U, // VMAXUW - 134U, // VMHADDSHS - 134U, // VMHRADDSHS - 38U, // VMINFP - 38U, // VMINSB - 38U, // VMINSD - 38U, // VMINSH - 38U, // VMINSW - 38U, // VMINUB - 38U, // VMINUD - 38U, // VMINUH - 38U, // VMINUW - 134U, // VMLADDUHM - 38U, // VMRGEW - 38U, // VMRGHB - 38U, // VMRGHH - 38U, // VMRGHW - 38U, // VMRGLB - 38U, // VMRGLH - 38U, // VMRGLW - 38U, // VMRGOW - 134U, // VMSUMMBM - 134U, // VMSUMSHM - 134U, // VMSUMSHS - 134U, // VMSUMUBM - 134U, // VMSUMUHM - 134U, // VMSUMUHS - 0U, // VMUL10CUQ - 38U, // VMUL10ECUQ - 38U, // VMUL10EUQ - 0U, // VMUL10UQ - 38U, // VMULESB - 38U, // VMULESH - 38U, // VMULESW - 38U, // VMULEUB - 38U, // VMULEUH - 38U, // VMULEUW - 38U, // VMULOSB - 38U, // VMULOSH - 38U, // VMULOSW - 38U, // VMULOUB - 38U, // VMULOUH - 38U, // VMULOUW - 38U, // VMULUWM - 38U, // VNAND - 38U, // VNCIPHER - 38U, // VNCIPHERLAST - 0U, // VNEGD - 0U, // VNEGW - 134U, // VNMSUBFP - 38U, // VNOR - 38U, // VOR - 38U, // VORC - 134U, // VPERM - 134U, // VPERMR - 134U, // VPERMXOR - 38U, // VPKPX - 38U, // VPKSDSS - 38U, // VPKSDUS - 38U, // VPKSHSS - 38U, // VPKSHUS - 38U, // VPKSWSS - 38U, // VPKSWUS - 38U, // VPKUDUM - 38U, // VPKUDUS - 38U, // VPKUHUM - 38U, // VPKUHUS - 38U, // VPKUWUM - 38U, // VPKUWUS - 38U, // VPMSUMB - 38U, // VPMSUMD - 38U, // VPMSUMH - 38U, // VPMSUMW - 0U, // VPOPCNTB - 0U, // VPOPCNTD - 0U, // VPOPCNTH - 0U, // VPOPCNTW - 0U, // VPRTYBD - 0U, // VPRTYBQ - 0U, // VPRTYBW - 0U, // VREFP - 0U, // VRFIM - 0U, // VRFIN - 0U, // VRFIP - 0U, // VRFIZ - 38U, // VRLB - 38U, // VRLD - 38U, // VRLDMI - 38U, // VRLDNM - 38U, // VRLH - 38U, // VRLW - 38U, // VRLWMI - 38U, // VRLWNM - 0U, // VRSQRTEFP - 0U, // VSBOX - 134U, // VSEL - 394U, // VSHASIGMAD - 394U, // VSHASIGMAW - 38U, // VSL - 38U, // VSLB - 38U, // VSLD - 390U, // VSLDOI - 38U, // VSLH - 38U, // VSLO - 38U, // VSLV - 38U, // VSLW - 1U, // VSPLTB - 1U, // VSPLTBs - 1U, // VSPLTH - 1U, // VSPLTHs - 0U, // VSPLTISB - 0U, // VSPLTISH - 0U, // VSPLTISW - 1U, // VSPLTW - 38U, // VSR - 38U, // VSRAB - 38U, // VSRAD - 38U, // VSRAH - 38U, // VSRAW - 38U, // VSRB - 38U, // VSRD - 38U, // VSRH - 38U, // VSRO - 38U, // VSRV - 38U, // VSRW - 38U, // VSUBCUQ - 38U, // VSUBCUW - 134U, // VSUBECUQ - 134U, // VSUBEUQM - 38U, // VSUBFP - 38U, // VSUBSBS - 38U, // VSUBSHS - 38U, // VSUBSWS - 38U, // VSUBUBM - 38U, // VSUBUBS - 38U, // VSUBUDM - 38U, // VSUBUHM - 38U, // VSUBUHS - 38U, // VSUBUQM - 38U, // VSUBUWM - 38U, // VSUBUWS - 38U, // VSUM2SWS - 38U, // VSUM4SBS - 38U, // VSUM4SHS - 38U, // VSUM4UBS - 38U, // VSUMSWS - 0U, // VUPKHPX - 0U, // VUPKHSB - 0U, // VUPKHSH - 0U, // VUPKHSW - 0U, // VUPKLPX - 0U, // VUPKLSB - 0U, // VUPKLSH - 0U, // VUPKLSW - 38U, // VXOR - 12U, // V_SET0 - 12U, // V_SET0B - 12U, // V_SET0H - 0U, // V_SETALLONES - 0U, // V_SETALLONESB - 0U, // V_SETALLONESH - 0U, // WAIT - 0U, // WRTEE - 0U, // WRTEEI - 38U, // XOR - 38U, // XOR8 - 38U, // XOR8o - 8U, // XORI - 8U, // XORI8 - 8U, // XORIS - 8U, // XORIS8 - 38U, // XORo - 0U, // XSABSDP - 0U, // XSABSQP - 38U, // XSADDDP - 38U, // XSADDQP - 38U, // XSADDQPO - 38U, // XSADDSP - 38U, // XSCMPEQDP - 38U, // XSCMPEXPDP - 38U, // XSCMPEXPQP - 38U, // XSCMPGEDP - 38U, // XSCMPGTDP - 38U, // XSCMPODP - 38U, // XSCMPOQP - 38U, // XSCMPUDP - 38U, // XSCMPUQP - 38U, // XSCPSGNDP - 38U, // XSCPSGNQP - 0U, // XSCVDPHP - 0U, // XSCVDPQP - 0U, // XSCVDPSP - 0U, // XSCVDPSPN - 0U, // XSCVDPSXDS - 0U, // XSCVDPSXDSs - 0U, // XSCVDPSXWS - 0U, // XSCVDPSXWSs - 0U, // XSCVDPUXDS - 0U, // XSCVDPUXDSs - 0U, // XSCVDPUXWS - 0U, // XSCVDPUXWSs - 0U, // XSCVHPDP - 0U, // XSCVQPDP - 0U, // XSCVQPDPO - 0U, // XSCVQPSDZ - 0U, // XSCVQPSWZ - 0U, // XSCVQPUDZ - 0U, // XSCVQPUWZ - 0U, // XSCVSDQP - 0U, // XSCVSPDP - 0U, // XSCVSPDPN - 0U, // XSCVSXDDP - 0U, // XSCVSXDSP - 0U, // XSCVUDQP - 0U, // XSCVUXDDP - 0U, // XSCVUXDSP - 38U, // XSDIVDP - 38U, // XSDIVQP - 38U, // XSDIVQPO - 38U, // XSDIVSP - 38U, // XSIEXPDP - 38U, // XSIEXPQP - 1U, // XSMADDADP - 1U, // XSMADDASP - 1U, // XSMADDMDP - 1U, // XSMADDMSP - 1U, // XSMADDQP - 1U, // XSMADDQPO - 38U, // XSMAXCDP - 38U, // XSMAXDP - 38U, // XSMAXJDP - 38U, // XSMINCDP - 38U, // XSMINDP - 38U, // XSMINJDP - 1U, // XSMSUBADP - 1U, // XSMSUBASP - 1U, // XSMSUBMDP - 1U, // XSMSUBMSP - 1U, // XSMSUBQP - 1U, // XSMSUBQPO - 38U, // XSMULDP - 38U, // XSMULQP - 38U, // XSMULQPO - 38U, // XSMULSP - 0U, // XSNABSDP - 0U, // XSNABSQP - 0U, // XSNEGDP - 0U, // XSNEGQP - 1U, // XSNMADDADP - 1U, // XSNMADDASP - 1U, // XSNMADDMDP - 1U, // XSNMADDMSP - 1U, // XSNMADDQP - 1U, // XSNMADDQPO - 1U, // XSNMSUBADP - 1U, // XSNMSUBASP - 1U, // XSNMSUBMDP - 1U, // XSNMSUBMSP - 1U, // XSNMSUBQP - 1U, // XSNMSUBQPO - 0U, // XSRDPI - 0U, // XSRDPIC - 0U, // XSRDPIM - 0U, // XSRDPIP - 0U, // XSRDPIZ - 0U, // XSREDP - 0U, // XSRESP - 262U, // XSRQPI - 262U, // XSRQPIX - 262U, // XSRQPXP - 0U, // XSRSP - 0U, // XSRSQRTEDP - 0U, // XSRSQRTESP - 0U, // XSSQRTDP - 0U, // XSSQRTQP - 0U, // XSSQRTQPO - 0U, // XSSQRTSP - 38U, // XSSUBDP - 38U, // XSSUBQP - 38U, // XSSUBQPO - 38U, // XSSUBSP - 38U, // XSTDIVDP - 0U, // XSTSQRTDP - 1U, // XSTSTDCDP - 1U, // XSTSTDCQP - 1U, // XSTSTDCSP - 0U, // XSXEXPDP - 0U, // XSXEXPQP - 0U, // XSXSIGDP - 0U, // XSXSIGQP - 0U, // XVABSDP - 0U, // XVABSSP - 38U, // XVADDDP - 38U, // XVADDSP - 38U, // XVCMPEQDP - 38U, // XVCMPEQDPo - 38U, // XVCMPEQSP - 38U, // XVCMPEQSPo - 38U, // XVCMPGEDP - 38U, // XVCMPGEDPo - 38U, // XVCMPGESP - 38U, // XVCMPGESPo - 38U, // XVCMPGTDP - 38U, // XVCMPGTDPo - 38U, // XVCMPGTSP - 38U, // XVCMPGTSPo - 38U, // XVCPSGNDP - 38U, // XVCPSGNSP - 0U, // XVCVDPSP - 0U, // XVCVDPSXDS - 0U, // XVCVDPSXWS - 0U, // XVCVDPUXDS - 0U, // XVCVDPUXWS - 0U, // XVCVHPSP - 0U, // XVCVSPDP - 0U, // XVCVSPHP - 0U, // XVCVSPSXDS - 0U, // XVCVSPSXWS - 0U, // XVCVSPUXDS - 0U, // XVCVSPUXWS - 0U, // XVCVSXDDP - 0U, // XVCVSXDSP - 0U, // XVCVSXWDP - 0U, // XVCVSXWSP - 0U, // XVCVUXDDP - 0U, // XVCVUXDSP - 0U, // XVCVUXWDP - 0U, // XVCVUXWSP - 38U, // XVDIVDP - 38U, // XVDIVSP - 38U, // XVIEXPDP - 38U, // XVIEXPSP - 1U, // XVMADDADP - 1U, // XVMADDASP - 1U, // XVMADDMDP - 1U, // XVMADDMSP - 38U, // XVMAXDP - 38U, // XVMAXSP - 38U, // XVMINDP - 38U, // XVMINSP - 1U, // XVMSUBADP - 1U, // XVMSUBASP - 1U, // XVMSUBMDP - 1U, // XVMSUBMSP - 38U, // XVMULDP - 38U, // XVMULSP - 0U, // XVNABSDP - 0U, // XVNABSSP - 0U, // XVNEGDP - 0U, // XVNEGSP - 1U, // XVNMADDADP - 1U, // XVNMADDASP - 1U, // XVNMADDMDP - 1U, // XVNMADDMSP - 1U, // XVNMSUBADP - 1U, // XVNMSUBASP - 1U, // XVNMSUBMDP - 1U, // XVNMSUBMSP - 0U, // XVRDPI - 0U, // XVRDPIC - 0U, // XVRDPIM - 0U, // XVRDPIP - 0U, // XVRDPIZ - 0U, // XVREDP - 0U, // XVRESP - 0U, // XVRSPI - 0U, // XVRSPIC - 0U, // XVRSPIM - 0U, // XVRSPIP - 0U, // XVRSPIZ - 0U, // XVRSQRTEDP - 0U, // XVRSQRTESP - 0U, // XVSQRTDP - 0U, // XVSQRTSP - 38U, // XVSUBDP - 38U, // XVSUBSP - 38U, // XVTDIVDP - 38U, // XVTDIVSP - 0U, // XVTSQRTDP - 0U, // XVTSQRTSP - 1U, // XVTSTDCDP - 1U, // XVTSTDCSP - 0U, // XVXEXPDP - 0U, // XVXEXPSP - 0U, // XVXSIGDP - 0U, // XVXSIGSP - 0U, // XXBRD - 0U, // XXBRH - 0U, // XXBRQ - 0U, // XXBRW - 20U, // XXEXTRACTUW - 1U, // XXINSERTW - 38U, // XXLAND - 38U, // XXLANDC - 38U, // XXLEQV - 38U, // XXLNAND - 38U, // XXLNOR - 38U, // XXLOR - 38U, // XXLORC - 38U, // XXLORf - 38U, // XXLXOR - 12U, // XXLXORdpz - 12U, // XXLXORspz - 12U, // XXLXORz - 38U, // XXMRGHW - 38U, // XXMRGLW - 38U, // XXPERM - 262U, // XXPERMDI - 462U, // XXPERMDIs - 38U, // XXPERMR - 134U, // XXSEL - 262U, // XXSLDWI - 462U, // XXSLDWIs - 0U, // XXSPLTIB - 16U, // XXSPLTW - 16U, // XXSPLTWs - 22U, // gBC - 24U, // gBCA - 0U, // gBCAat - 38U, // gBCCTR - 38U, // gBCCTRL - 22U, // gBCL - 24U, // gBCLA - 0U, // gBCLAat - 38U, // gBCLR - 38U, // gBCLRL - 0U, // gBCLat - 0U, // gBCat + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // CFENCE8 + 0U, // CLRLSLDI + 0U, // CLRLSLDIo + 66U, // CLRLSLWI + 66U, // CLRLSLWIo + 32U, // CLRRDI + 32U, // CLRRDIo + 34U, // CLRRWI + 34U, // CLRRWIo + 0U, // CP_COPY_FIRST + 0U, // CP_COPYx + 0U, // CP_PASTE_LAST + 0U, // CP_PASTEx + 0U, // DCBFL + 0U, // DCBFLP + 0U, // DCBFx + 0U, // DCBTCT + 0U, // DCBTDS + 0U, // DCBTSTCT + 0U, // DCBTSTDS + 0U, // DCBTSTT + 0U, // DCBTSTx + 0U, // DCBTT + 0U, // DCBTx + 0U, // DFLOADf32 + 0U, // DFLOADf64 + 0U, // DFSTOREf32 + 0U, // DFSTOREf64 + 0U, // EXTLDI + 0U, // EXTLDIo + 66U, // EXTLWI + 66U, // EXTLWIo + 0U, // EXTRDI + 0U, // EXTRDIo + 66U, // EXTRWI + 66U, // EXTRWIo + 66U, // INSLWI + 66U, // INSLWIo + 0U, // INSRDI + 0U, // INSRDIo + 66U, // INSRWI + 66U, // INSRWIo + 0U, // LAx + 0U, // LIWAX + 0U, // LIWZX + 130U, // RLWIMIbm + 130U, // RLWIMIobm + 130U, // RLWINMbm + 130U, // RLWINMobm + 130U, // RLWNMbm + 130U, // RLWNMobm + 32U, // ROTRDI + 32U, // ROTRDIo + 34U, // ROTRWI + 34U, // ROTRWIo + 32U, // SLDI + 32U, // SLDIo + 34U, // SLWI + 34U, // SLWIo + 0U, // SPILLTOVSR_LD + 0U, // SPILLTOVSR_LDX + 0U, // SPILLTOVSR_ST + 0U, // SPILLTOVSR_STX + 32U, // SRDI + 32U, // SRDIo + 34U, // SRWI + 34U, // SRWIo + 0U, // STIWX + 4U, // SUBI + 4U, // SUBIC + 4U, // SUBICo + 4U, // SUBIS + 0U, // SUBPCIS + 0U, // XFLOADf32 + 0U, // XFLOADf64 + 0U, // XFSTOREf32 + 0U, // XFSTOREf64 + 38U, // ADD4 + 38U, // ADD4TLS + 38U, // ADD4o + 38U, // ADD8 + 38U, // ADD8TLS + 38U, // ADD8TLS_ + 38U, // ADD8o + 38U, // ADDC + 38U, // ADDC8 + 38U, // ADDC8o + 38U, // ADDCo + 38U, // ADDE + 38U, // ADDE8 + 38U, // ADDE8o + 38U, // ADDEo + 4U, // ADDI + 4U, // ADDI8 + 4U, // ADDIC + 4U, // ADDIC8 + 4U, // ADDICo + 4U, // ADDIS + 4U, // ADDIS8 + 0U, // ADDISdtprelHA + 0U, // ADDISdtprelHA32 + 0U, // ADDISgotTprelHA + 0U, // ADDIStlsgdHA + 0U, // ADDIStlsldHA + 0U, // ADDIStocHA + 0U, // ADDIdtprelL + 0U, // ADDIdtprelL32 + 0U, // ADDItlsgdL + 0U, // ADDItlsgdL32 + 0U, // ADDItlsgdLADDR + 0U, // ADDItlsgdLADDR32 + 0U, // ADDItlsldL + 0U, // ADDItlsldL32 + 0U, // ADDItlsldLADDR + 0U, // ADDItlsldLADDR32 + 0U, // ADDItocL + 0U, // ADDME + 0U, // ADDME8 + 0U, // ADDME8o + 0U, // ADDMEo + 0U, // ADDPCIS + 0U, // ADDZE + 0U, // ADDZE8 + 0U, // ADDZE8o + 0U, // ADDZEo + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 38U, // AND + 38U, // AND8 + 38U, // AND8o + 38U, // ANDC + 38U, // ANDC8 + 38U, // ANDC8o + 38U, // ANDCo + 8U, // ANDISo + 8U, // ANDISo8 + 8U, // ANDIo + 8U, // ANDIo8 + 0U, // ANDIo_1_EQ_BIT + 0U, // ANDIo_1_EQ_BIT8 + 0U, // ANDIo_1_GT_BIT + 0U, // ANDIo_1_GT_BIT8 + 38U, // ANDo + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 0U, // ATTN + 0U, // B + 0U, // BA + 0U, // BC + 0U, // BCC + 0U, // BCCA + 0U, // BCCCTR + 0U, // BCCCTR8 + 0U, // BCCCTRL + 0U, // BCCCTRL8 + 0U, // BCCL + 0U, // BCCLA + 0U, // BCCLR + 0U, // BCCLRL + 0U, // BCCTR + 0U, // BCCTR8 + 0U, // BCCTR8n + 0U, // BCCTRL + 0U, // BCCTRL8 + 0U, // BCCTRL8n + 0U, // BCCTRLn + 0U, // BCCTRn + 42U, // BCDCFNo + 42U, // BCDCFSQo + 42U, // BCDCFZo + 38U, // BCDCPSGNo + 0U, // BCDCTNo + 0U, // BCDCTSQo + 42U, // BCDCTZo + 42U, // BCDSETSGNo + 198U, // BCDSRo + 198U, // BCDSo + 198U, // BCDTRUNCo + 38U, // BCDUSo + 38U, // BCDUTRUNCo + 0U, // BCL + 0U, // BCLR + 0U, // BCLRL + 0U, // BCLRLn + 0U, // BCLRn + 0U, // BCLalways + 0U, // BCLn + 0U, // BCTR + 0U, // BCTR8 + 0U, // BCTRL + 0U, // BCTRL8 + 0U, // BCTRL8_LDinto_toc + 0U, // BCn + 0U, // BDNZ + 0U, // BDNZ8 + 0U, // BDNZA + 0U, // BDNZAm + 0U, // BDNZAp + 0U, // BDNZL + 0U, // BDNZLA + 0U, // BDNZLAm + 0U, // BDNZLAp + 0U, // BDNZLR + 0U, // BDNZLR8 + 0U, // BDNZLRL + 0U, // BDNZLRLm + 0U, // BDNZLRLp + 0U, // BDNZLRm + 0U, // BDNZLRp + 0U, // BDNZLm + 0U, // BDNZLp + 0U, // BDNZm + 0U, // BDNZp + 0U, // BDZ + 0U, // BDZ8 + 0U, // BDZA + 0U, // BDZAm + 0U, // BDZAp + 0U, // BDZL + 0U, // BDZLA + 0U, // BDZLAm + 0U, // BDZLAp + 0U, // BDZLR + 0U, // BDZLR8 + 0U, // BDZLRL + 0U, // BDZLRLm + 0U, // BDZLRLp + 0U, // BDZLRm + 0U, // BDZLRp + 0U, // BDZLm + 0U, // BDZLp + 0U, // BDZm + 0U, // BDZp + 0U, // BL + 0U, // BL8 + 0U, // BL8_NOP + 0U, // BL8_NOP_TLS + 0U, // BL8_TLS + 0U, // BL8_TLS_ + 0U, // BLA + 0U, // BLA8 + 0U, // BLA8_NOP + 0U, // BLR + 0U, // BLR8 + 0U, // BLRL + 0U, // BL_TLS + 38U, // BPERMD + 38U, // BRINC + 0U, // CLRBHRB + 38U, // CMPB + 38U, // CMPB8 + 38U, // CMPD + 4U, // CMPDI + 38U, // CMPEQB + 38U, // CMPLD + 8U, // CMPLDI + 38U, // CMPLW + 8U, // CMPLWI + 0U, // CMPRB + 0U, // CMPRB8 + 38U, // CMPW + 4U, // CMPWI + 0U, // CNTLZD + 0U, // CNTLZDo + 0U, // CNTLZW + 0U, // CNTLZW8 + 0U, // CNTLZW8o + 0U, // CNTLZWo + 0U, // CNTTZD + 0U, // CNTTZDo + 0U, // CNTTZW + 0U, // CNTTZW8 + 0U, // CNTTZW8o + 0U, // CNTTZWo + 0U, // CP_ABORT + 42U, // CP_COPY + 42U, // CP_COPY8 + 42U, // CP_PASTE + 42U, // CP_PASTE8 + 42U, // CP_PASTE8o + 42U, // CP_PASTEo + 0U, // CR6SET + 0U, // CR6UNSET + 38U, // CRAND + 38U, // CRANDC + 38U, // CREQV + 38U, // CRNAND + 38U, // CRNOR + 38U, // CROR + 38U, // CRORC + 12U, // CRSET + 12U, // CRUNSET + 38U, // CRXOR + 0U, // CTRL_DEP + 0U, // DARN + 0U, // DCBA + 0U, // DCBF + 0U, // DCBFEP + 0U, // DCBI + 0U, // DCBST + 0U, // DCBSTEP + 0U, // DCBT + 0U, // DCBTEP + 0U, // DCBTST + 0U, // DCBTSTEP + 0U, // DCBZ + 0U, // DCBZEP + 0U, // DCBZL + 0U, // DCBZLEP + 0U, // DCCCI + 38U, // DIVD + 38U, // DIVDE + 38U, // DIVDEU + 38U, // DIVDEUo + 38U, // DIVDEo + 38U, // DIVDU + 38U, // DIVDUo + 38U, // DIVDo + 38U, // DIVW + 38U, // DIVWE + 38U, // DIVWEU + 38U, // DIVWEUo + 38U, // DIVWEo + 38U, // DIVWU + 38U, // DIVWUo + 38U, // DIVWo + 0U, // DSS + 0U, // DSSALL + 0U, // DST + 0U, // DST64 + 0U, // DSTST + 0U, // DSTST64 + 0U, // DSTSTT + 0U, // DSTSTT64 + 0U, // DSTT + 0U, // DSTT64 + 0U, // DYNALLOC + 0U, // DYNALLOC8 + 0U, // DYNAREAOFFSET + 0U, // DYNAREAOFFSET8 + 0U, // EFDABS + 38U, // EFDADD + 0U, // EFDCFS + 0U, // EFDCFSF + 0U, // EFDCFSI + 0U, // EFDCFSID + 0U, // EFDCFUF + 0U, // EFDCFUI + 0U, // EFDCFUID + 38U, // EFDCMPEQ + 38U, // EFDCMPGT + 38U, // EFDCMPLT + 0U, // EFDCTSF + 0U, // EFDCTSI + 0U, // EFDCTSIDZ + 0U, // EFDCTSIZ + 0U, // EFDCTUF + 0U, // EFDCTUI + 0U, // EFDCTUIDZ + 0U, // EFDCTUIZ + 38U, // EFDDIV + 38U, // EFDMUL + 0U, // EFDNABS + 0U, // EFDNEG + 38U, // EFDSUB + 38U, // EFDTSTEQ + 38U, // EFDTSTGT + 38U, // EFDTSTLT + 0U, // EFSABS + 38U, // EFSADD + 0U, // EFSCFD + 0U, // EFSCFSF + 0U, // EFSCFSI + 0U, // EFSCFUF + 0U, // EFSCFUI + 38U, // EFSCMPEQ + 38U, // EFSCMPGT + 38U, // EFSCMPLT + 0U, // EFSCTSF + 0U, // EFSCTSI + 0U, // EFSCTSIZ + 0U, // EFSCTUF + 0U, // EFSCTUI + 0U, // EFSCTUIZ + 38U, // EFSDIV + 38U, // EFSMUL + 0U, // EFSNABS + 0U, // EFSNEG + 38U, // EFSSUB + 38U, // EFSTSTEQ + 38U, // EFSTSTGT + 38U, // EFSTSTLT + 0U, // EH_SjLj_LongJmp32 + 0U, // EH_SjLj_LongJmp64 + 0U, // EH_SjLj_SetJmp32 + 0U, // EH_SjLj_SetJmp64 + 0U, // EH_SjLj_Setup + 38U, // EQV + 38U, // EQV8 + 38U, // EQV8o + 38U, // EQVo + 0U, // EVABS + 46U, // EVADDIW + 0U, // EVADDSMIAAW + 0U, // EVADDSSIAAW + 0U, // EVADDUMIAAW + 0U, // EVADDUSIAAW + 38U, // EVADDW + 38U, // EVAND + 38U, // EVANDC + 38U, // EVCMPEQ + 38U, // EVCMPGTS + 38U, // EVCMPGTU + 38U, // EVCMPLTS + 38U, // EVCMPLTU + 0U, // EVCNTLSW + 0U, // EVCNTLZW + 38U, // EVDIVWS + 38U, // EVDIVWU + 38U, // EVEQV + 0U, // EVEXTSB + 0U, // EVEXTSH + 0U, // EVFSABS + 38U, // EVFSADD + 0U, // EVFSCFSF + 0U, // EVFSCFSI + 0U, // EVFSCFUF + 0U, // EVFSCFUI + 38U, // EVFSCMPEQ + 38U, // EVFSCMPGT + 38U, // EVFSCMPLT + 0U, // EVFSCTSF + 0U, // EVFSCTSI + 0U, // EVFSCTSIZ + 0U, // EVFSCTUF + 0U, // EVFSCTUI + 0U, // EVFSCTUIZ + 38U, // EVFSDIV + 38U, // EVFSMUL + 0U, // EVFSNABS + 0U, // EVFSNEG + 38U, // EVFSSUB + 38U, // EVFSTSTEQ + 38U, // EVFSTSTGT + 38U, // EVFSTSTLT + 0U, // EVLDD + 0U, // EVLDDX + 0U, // EVLDH + 0U, // EVLDHX + 0U, // EVLDW + 0U, // EVLDWX + 0U, // EVLHHESPLAT + 0U, // EVLHHESPLATX + 0U, // EVLHHOSSPLAT + 0U, // EVLHHOSSPLATX + 0U, // EVLHHOUSPLAT + 0U, // EVLHHOUSPLATX + 0U, // EVLWHE + 0U, // EVLWHEX + 0U, // EVLWHOS + 0U, // EVLWHOSX + 0U, // EVLWHOU + 0U, // EVLWHOUX + 0U, // EVLWHSPLAT + 0U, // EVLWHSPLATX + 0U, // EVLWWSPLAT + 0U, // EVLWWSPLATX + 38U, // EVMERGEHI + 38U, // EVMERGEHILO + 38U, // EVMERGELO + 38U, // EVMERGELOHI + 38U, // EVMHEGSMFAA + 38U, // EVMHEGSMFAN + 38U, // EVMHEGSMIAA + 38U, // EVMHEGSMIAN + 38U, // EVMHEGUMIAA + 38U, // EVMHEGUMIAN + 38U, // EVMHESMF + 38U, // EVMHESMFA + 38U, // EVMHESMFAAW + 38U, // EVMHESMFANW + 38U, // EVMHESMI + 38U, // EVMHESMIA + 38U, // EVMHESMIAAW + 38U, // EVMHESMIANW + 38U, // EVMHESSF + 38U, // EVMHESSFA + 38U, // EVMHESSFAAW + 38U, // EVMHESSFANW + 38U, // EVMHESSIAAW + 38U, // EVMHESSIANW + 38U, // EVMHEUMI + 38U, // EVMHEUMIA + 38U, // EVMHEUMIAAW + 38U, // EVMHEUMIANW + 38U, // EVMHEUSIAAW + 38U, // EVMHEUSIANW + 38U, // EVMHOGSMFAA + 38U, // EVMHOGSMFAN + 38U, // EVMHOGSMIAA + 38U, // EVMHOGSMIAN + 38U, // EVMHOGUMIAA + 38U, // EVMHOGUMIAN + 38U, // EVMHOSMF + 38U, // EVMHOSMFA + 38U, // EVMHOSMFAAW + 38U, // EVMHOSMFANW + 38U, // EVMHOSMI + 38U, // EVMHOSMIA + 38U, // EVMHOSMIAAW + 38U, // EVMHOSMIANW + 38U, // EVMHOSSF + 38U, // EVMHOSSFA + 38U, // EVMHOSSFAAW + 38U, // EVMHOSSFANW + 38U, // EVMHOSSIAAW + 38U, // EVMHOSSIANW + 38U, // EVMHOUMI + 38U, // EVMHOUMIA + 38U, // EVMHOUMIAAW + 38U, // EVMHOUMIANW + 38U, // EVMHOUSIAAW + 38U, // EVMHOUSIANW + 0U, // EVMRA + 38U, // EVMWHSMF + 38U, // EVMWHSMFA + 38U, // EVMWHSMI + 38U, // EVMWHSMIA + 38U, // EVMWHSSF + 38U, // EVMWHSSFA + 38U, // EVMWHUMI + 38U, // EVMWHUMIA + 38U, // EVMWLSMIAAW + 38U, // EVMWLSMIANW + 38U, // EVMWLSSIAAW + 38U, // EVMWLSSIANW + 38U, // EVMWLUMI + 38U, // EVMWLUMIA + 38U, // EVMWLUMIAAW + 38U, // EVMWLUMIANW + 38U, // EVMWLUSIAAW + 38U, // EVMWLUSIANW + 38U, // EVMWSMF + 38U, // EVMWSMFA + 38U, // EVMWSMFAA + 38U, // EVMWSMFAN + 38U, // EVMWSMI + 38U, // EVMWSMIA + 38U, // EVMWSMIAA + 38U, // EVMWSMIAN + 38U, // EVMWSSF + 38U, // EVMWSSFA + 38U, // EVMWSSFAA + 38U, // EVMWSSFAN + 38U, // EVMWUMI + 38U, // EVMWUMIA + 38U, // EVMWUMIAA + 38U, // EVMWUMIAN + 38U, // EVNAND + 0U, // EVNEG + 38U, // EVNOR + 38U, // EVOR + 38U, // EVORC + 38U, // EVRLW + 34U, // EVRLWI + 0U, // EVRNDW + 0U, // EVSEL + 38U, // EVSLW + 34U, // EVSLWI + 0U, // EVSPLATFI + 0U, // EVSPLATI + 34U, // EVSRWIS + 34U, // EVSRWIU + 38U, // EVSRWS + 38U, // EVSRWU + 0U, // EVSTDD + 0U, // EVSTDDX + 0U, // EVSTDH + 0U, // EVSTDHX + 0U, // EVSTDW + 0U, // EVSTDWX + 0U, // EVSTWHE + 0U, // EVSTWHEX + 0U, // EVSTWHO + 0U, // EVSTWHOX + 0U, // EVSTWWE + 0U, // EVSTWWEX + 0U, // EVSTWWO + 0U, // EVSTWWOX + 0U, // EVSUBFSMIAAW + 0U, // EVSUBFSSIAAW + 0U, // EVSUBFUMIAAW + 0U, // EVSUBFUSIAAW + 38U, // EVSUBFW + 0U, // EVSUBIFW + 38U, // EVXOR + 0U, // EXTSB + 0U, // EXTSB8 + 0U, // EXTSB8_32_64 + 0U, // EXTSB8o + 0U, // EXTSBo + 0U, // EXTSH + 0U, // EXTSH8 + 0U, // EXTSH8_32_64 + 0U, // EXTSH8o + 0U, // EXTSHo + 0U, // EXTSW + 32U, // EXTSWSLI + 32U, // EXTSWSLIo + 0U, // EXTSW_32 + 0U, // EXTSW_32_64 + 0U, // EXTSW_32_64o + 0U, // EXTSWo + 0U, // EnforceIEIO + 0U, // FABSD + 0U, // FABSDo + 0U, // FABSS + 0U, // FABSSo + 38U, // FADD + 38U, // FADDS + 38U, // FADDSo + 38U, // FADDo + 0U, // FADDrtz + 0U, // FCFID + 0U, // FCFIDS + 0U, // FCFIDSo + 0U, // FCFIDU + 0U, // FCFIDUS + 0U, // FCFIDUSo + 0U, // FCFIDUo + 0U, // FCFIDo + 38U, // FCMPUD + 38U, // FCMPUS + 38U, // FCPSGND + 38U, // FCPSGNDo + 38U, // FCPSGNS + 38U, // FCPSGNSo + 0U, // FCTID + 0U, // FCTIDU + 0U, // FCTIDUZ + 0U, // FCTIDUZo + 0U, // FCTIDUo + 0U, // FCTIDZ + 0U, // FCTIDZo + 0U, // FCTIDo + 0U, // FCTIW + 0U, // FCTIWU + 0U, // FCTIWUZ + 0U, // FCTIWUZo + 0U, // FCTIWUo + 0U, // FCTIWZ + 0U, // FCTIWZo + 0U, // FCTIWo + 38U, // FDIV + 38U, // FDIVS + 38U, // FDIVSo + 38U, // FDIVo + 134U, // FMADD + 134U, // FMADDS + 134U, // FMADDSo + 134U, // FMADDo + 0U, // FMR + 0U, // FMRo + 134U, // FMSUB + 134U, // FMSUBS + 134U, // FMSUBSo + 134U, // FMSUBo + 38U, // FMUL + 38U, // FMULS + 38U, // FMULSo + 38U, // FMULo + 0U, // FNABSD + 0U, // FNABSDo + 0U, // FNABSS + 0U, // FNABSSo + 0U, // FNEGD + 0U, // FNEGDo + 0U, // FNEGS + 0U, // FNEGSo + 134U, // FNMADD + 134U, // FNMADDS + 134U, // FNMADDSo + 134U, // FNMADDo + 134U, // FNMSUB + 134U, // FNMSUBS + 134U, // FNMSUBSo + 134U, // FNMSUBo + 0U, // FRE + 0U, // FRES + 0U, // FRESo + 0U, // FREo + 0U, // FRIMD + 0U, // FRIMDo + 0U, // FRIMS + 0U, // FRIMSo + 0U, // FRIND + 0U, // FRINDo + 0U, // FRINS + 0U, // FRINSo + 0U, // FRIPD + 0U, // FRIPDo + 0U, // FRIPS + 0U, // FRIPSo + 0U, // FRIZD + 0U, // FRIZDo + 0U, // FRIZS + 0U, // FRIZSo + 0U, // FRSP + 0U, // FRSPo + 0U, // FRSQRTE + 0U, // FRSQRTES + 0U, // FRSQRTESo + 0U, // FRSQRTEo + 134U, // FSELD + 134U, // FSELDo + 134U, // FSELS + 134U, // FSELSo + 0U, // FSQRT + 0U, // FSQRTS + 0U, // FSQRTSo + 0U, // FSQRTo + 38U, // FSUB + 38U, // FSUBS + 38U, // FSUBSo + 38U, // FSUBo + 38U, // FTDIV + 0U, // FTSQRT + 0U, // GETtlsADDR + 0U, // GETtlsADDR32 + 0U, // GETtlsldADDR + 0U, // GETtlsldADDR32 + 0U, // HRFID + 0U, // ICBI + 0U, // ICBIEP + 0U, // ICBLC + 0U, // ICBLQ + 0U, // ICBT + 0U, // ICBTLS + 0U, // ICCCI + 134U, // ISEL + 134U, // ISEL8 + 0U, // ISYNC + 0U, // LA + 0U, // LBARX + 0U, // LBARXL + 0U, // LBEPX + 0U, // LBZ + 0U, // LBZ8 + 38U, // LBZCIX + 0U, // LBZU + 0U, // LBZU8 + 0U, // LBZUX + 0U, // LBZUX8 + 0U, // LBZX + 0U, // LBZX8 + 38U, // LBZXTLS + 38U, // LBZXTLS_ + 38U, // LBZXTLS_32 + 0U, // LD + 0U, // LDARX + 0U, // LDARXL + 34U, // LDAT + 0U, // LDBRX + 38U, // LDCIX + 0U, // LDMX + 0U, // LDU + 0U, // LDUX + 0U, // LDX + 38U, // LDXTLS + 38U, // LDXTLS_ + 0U, // LDgotTprelL + 0U, // LDgotTprelL32 + 0U, // LDtoc + 0U, // LDtocBA + 0U, // LDtocCPT + 0U, // LDtocJTI + 0U, // LDtocL + 0U, // LFD + 0U, // LFDEPX + 0U, // LFDU + 0U, // LFDUX + 0U, // LFDX + 0U, // LFIWAX + 0U, // LFIWZX + 0U, // LFS + 0U, // LFSU + 0U, // LFSUX + 0U, // LFSX + 0U, // LHA + 0U, // LHA8 + 0U, // LHARX + 0U, // LHARXL + 0U, // LHAU + 0U, // LHAU8 + 0U, // LHAUX + 0U, // LHAUX8 + 0U, // LHAX + 0U, // LHAX8 + 0U, // LHBRX + 0U, // LHBRX8 + 0U, // LHEPX + 0U, // LHZ + 0U, // LHZ8 + 38U, // LHZCIX + 0U, // LHZU + 0U, // LHZU8 + 0U, // LHZUX + 0U, // LHZUX8 + 0U, // LHZX + 0U, // LHZX8 + 38U, // LHZXTLS + 38U, // LHZXTLS_ + 38U, // LHZXTLS_32 + 0U, // LI + 0U, // LI8 + 0U, // LIS + 0U, // LIS8 + 0U, // LMW + 34U, // LSWI + 0U, // LVEBX + 0U, // LVEHX + 0U, // LVEWX + 0U, // LVSL + 0U, // LVSR + 0U, // LVX + 0U, // LVXL + 0U, // LWA + 0U, // LWARX + 0U, // LWARXL + 34U, // LWAT + 0U, // LWAUX + 0U, // LWAX + 0U, // LWAX_32 + 0U, // LWA_32 + 0U, // LWBRX + 0U, // LWBRX8 + 0U, // LWEPX + 0U, // LWZ + 0U, // LWZ8 + 38U, // LWZCIX + 0U, // LWZU + 0U, // LWZU8 + 0U, // LWZUX + 0U, // LWZUX8 + 0U, // LWZX + 0U, // LWZX8 + 38U, // LWZXTLS + 38U, // LWZXTLS_ + 38U, // LWZXTLS_32 + 0U, // LWZtoc + 0U, // LXSD + 0U, // LXSDX + 0U, // LXSIBZX + 0U, // LXSIHZX + 0U, // LXSIWAX + 0U, // LXSIWZX + 0U, // LXSSP + 0U, // LXSSPX + 0U, // LXV + 0U, // LXVB16X + 0U, // LXVD2X + 0U, // LXVDSX + 0U, // LXVH8X + 38U, // LXVL + 38U, // LXVLL + 0U, // LXVW4X + 0U, // LXVWSX + 0U, // LXVX + 134U, // MADDHD + 134U, // MADDHDU + 134U, // MADDLD + 0U, // MBAR + 0U, // MCRF + 0U, // MCRFS + 0U, // MCRXRX + 0U, // MFBHRBE + 0U, // MFCR + 0U, // MFCR8 + 0U, // MFCTR + 0U, // MFCTR8 + 0U, // MFDCR + 0U, // MFFS + 0U, // MFFSCDRN + 0U, // MFFSCDRNI + 0U, // MFFSCE + 0U, // MFFSCRN + 0U, // MFFSCRNI + 0U, // MFFSL + 0U, // MFFSo + 0U, // MFLR + 0U, // MFLR8 + 0U, // MFMSR + 0U, // MFOCRF + 0U, // MFOCRF8 + 0U, // MFPMR + 0U, // MFSPR + 0U, // MFSPR8 + 0U, // MFSR + 0U, // MFSRIN + 0U, // MFTB + 0U, // MFTB8 + 0U, // MFVRD + 0U, // MFVRSAVE + 0U, // MFVRSAVEv + 0U, // MFVSCR + 0U, // MFVSRD + 0U, // MFVSRLD + 0U, // MFVSRWZ + 38U, // MODSD + 38U, // MODSW + 38U, // MODUD + 38U, // MODUW + 0U, // MSGSYNC + 0U, // MSYNC + 0U, // MTCRF + 0U, // MTCRF8 + 0U, // MTCTR + 0U, // MTCTR8 + 0U, // MTCTR8loop + 0U, // MTCTRloop + 0U, // MTDCR + 0U, // MTFSB0 + 0U, // MTFSB1 + 134U, // MTFSF + 38U, // MTFSFI + 38U, // MTFSFIo + 0U, // MTFSFb + 134U, // MTFSFo + 0U, // MTLR + 0U, // MTLR8 + 0U, // MTMSR + 0U, // MTMSRD + 0U, // MTOCRF + 0U, // MTOCRF8 + 0U, // MTPMR + 0U, // MTSPR + 0U, // MTSPR8 + 0U, // MTSR + 0U, // MTSRIN + 0U, // MTVRSAVE + 0U, // MTVRSAVEv + 0U, // MTVSCR + 0U, // MTVSRD + 38U, // MTVSRDD + 0U, // MTVSRWA + 0U, // MTVSRWS + 0U, // MTVSRWZ + 38U, // MULHD + 38U, // MULHDU + 38U, // MULHDUo + 38U, // MULHDo + 38U, // MULHW + 38U, // MULHWU + 38U, // MULHWUo + 38U, // MULHWo + 38U, // MULLD + 38U, // MULLDo + 4U, // MULLI + 4U, // MULLI8 + 38U, // MULLW + 38U, // MULLWo + 0U, // MoveGOTtoLR + 0U, // MovePCtoLR + 0U, // MovePCtoLR8 + 38U, // NAND + 38U, // NAND8 + 38U, // NAND8o + 38U, // NANDo + 0U, // NAP + 0U, // NEG + 0U, // NEG8 + 0U, // NEG8o + 0U, // NEGo + 0U, // NOP + 0U, // NOP_GT_PWR6 + 0U, // NOP_GT_PWR7 + 38U, // NOR + 38U, // NOR8 + 38U, // NOR8o + 38U, // NORo + 38U, // OR + 38U, // OR8 + 38U, // OR8o + 38U, // ORC + 38U, // ORC8 + 38U, // ORC8o + 38U, // ORCo + 8U, // ORI + 8U, // ORI8 + 8U, // ORIS + 8U, // ORIS8 + 38U, // ORo + 0U, // POPCNTB + 0U, // POPCNTD + 0U, // POPCNTW + 0U, // PPC32GOT + 0U, // PPC32PICGOT + 262U, // QVALIGNI + 262U, // QVALIGNIb + 262U, // QVALIGNIs + 16U, // QVESPLATI + 16U, // QVESPLATIb + 16U, // QVESPLATIs + 0U, // QVFABS + 0U, // QVFABSs + 38U, // QVFADD + 38U, // QVFADDS + 38U, // QVFADDSs + 0U, // QVFCFID + 0U, // QVFCFIDS + 0U, // QVFCFIDU + 0U, // QVFCFIDUS + 0U, // QVFCFIDb + 38U, // QVFCMPEQ + 38U, // QVFCMPEQb + 38U, // QVFCMPEQbs + 38U, // QVFCMPGT + 38U, // QVFCMPGTb + 38U, // QVFCMPGTbs + 38U, // QVFCMPLT + 38U, // QVFCMPLTb + 38U, // QVFCMPLTbs + 38U, // QVFCPSGN + 38U, // QVFCPSGNs + 0U, // QVFCTID + 0U, // QVFCTIDU + 0U, // QVFCTIDUZ + 0U, // QVFCTIDZ + 0U, // QVFCTIDb + 0U, // QVFCTIW + 0U, // QVFCTIWU + 0U, // QVFCTIWUZ + 0U, // QVFCTIWZ + 326U, // QVFLOGICAL + 326U, // QVFLOGICALb + 326U, // QVFLOGICALs + 18U, // QVFMADD + 18U, // QVFMADDS + 18U, // QVFMADDSs + 0U, // QVFMR + 0U, // QVFMRb + 0U, // QVFMRs + 18U, // QVFMSUB + 18U, // QVFMSUBS + 18U, // QVFMSUBSs + 38U, // QVFMUL + 38U, // QVFMULS + 38U, // QVFMULSs + 0U, // QVFNABS + 0U, // QVFNABSs + 0U, // QVFNEG + 0U, // QVFNEGs + 18U, // QVFNMADD + 18U, // QVFNMADDS + 18U, // QVFNMADDSs + 18U, // QVFNMSUB + 18U, // QVFNMSUBS + 18U, // QVFNMSUBSs + 134U, // QVFPERM + 134U, // QVFPERMs + 0U, // QVFRE + 0U, // QVFRES + 0U, // QVFRESs + 0U, // QVFRIM + 0U, // QVFRIMs + 0U, // QVFRIN + 0U, // QVFRINs + 0U, // QVFRIP + 0U, // QVFRIPs + 0U, // QVFRIZ + 0U, // QVFRIZs + 0U, // QVFRSP + 0U, // QVFRSPs + 0U, // QVFRSQRTE + 0U, // QVFRSQRTES + 0U, // QVFRSQRTESs + 18U, // QVFSEL + 18U, // QVFSELb + 18U, // QVFSELbb + 18U, // QVFSELbs + 38U, // QVFSUB + 38U, // QVFSUBS + 38U, // QVFSUBSs + 38U, // QVFTSTNAN + 38U, // QVFTSTNANb + 38U, // QVFTSTNANbs + 18U, // QVFXMADD + 18U, // QVFXMADDS + 38U, // QVFXMUL + 38U, // QVFXMULS + 18U, // QVFXXCPNMADD + 18U, // QVFXXCPNMADDS + 18U, // QVFXXMADD + 18U, // QVFXXMADDS + 18U, // QVFXXNPMADD + 18U, // QVFXXNPMADDS + 0U, // QVGPCI + 0U, // QVLFCDUX + 0U, // QVLFCDUXA + 0U, // QVLFCDX + 0U, // QVLFCDXA + 0U, // QVLFCSUX + 0U, // QVLFCSUXA + 0U, // QVLFCSX + 0U, // QVLFCSXA + 0U, // QVLFCSXs + 0U, // QVLFDUX + 0U, // QVLFDUXA + 0U, // QVLFDX + 0U, // QVLFDXA + 0U, // QVLFDXb + 0U, // QVLFIWAX + 0U, // QVLFIWAXA + 0U, // QVLFIWZX + 0U, // QVLFIWZXA + 0U, // QVLFSUX + 0U, // QVLFSUXA + 0U, // QVLFSX + 0U, // QVLFSXA + 0U, // QVLFSXb + 0U, // QVLFSXs + 0U, // QVLPCLDX + 0U, // QVLPCLSX + 0U, // QVLPCLSXint + 0U, // QVLPCRDX + 0U, // QVLPCRSX + 0U, // QVSTFCDUX + 0U, // QVSTFCDUXA + 0U, // QVSTFCDUXI + 0U, // QVSTFCDUXIA + 0U, // QVSTFCDX + 0U, // QVSTFCDXA + 0U, // QVSTFCDXI + 0U, // QVSTFCDXIA + 0U, // QVSTFCSUX + 0U, // QVSTFCSUXA + 0U, // QVSTFCSUXI + 0U, // QVSTFCSUXIA + 0U, // QVSTFCSX + 0U, // QVSTFCSXA + 0U, // QVSTFCSXI + 0U, // QVSTFCSXIA + 0U, // QVSTFCSXs + 0U, // QVSTFDUX + 0U, // QVSTFDUXA + 0U, // QVSTFDUXI + 0U, // QVSTFDUXIA + 0U, // QVSTFDX + 0U, // QVSTFDXA + 0U, // QVSTFDXI + 0U, // QVSTFDXIA + 0U, // QVSTFDXb + 0U, // QVSTFIWX + 0U, // QVSTFIWXA + 0U, // QVSTFSUX + 0U, // QVSTFSUXA + 0U, // QVSTFSUXI + 0U, // QVSTFSUXIA + 0U, // QVSTFSUXs + 0U, // QVSTFSX + 0U, // QVSTFSXA + 0U, // QVSTFSXI + 0U, // QVSTFSXIA + 0U, // QVSTFSXs + 0U, // RESTORE_CR + 0U, // RESTORE_CRBIT + 0U, // RESTORE_VRSAVE + 0U, // RFCI + 0U, // RFDI + 0U, // RFEBB + 0U, // RFI + 0U, // RFID + 0U, // RFMCI + 6U, // RLDCL + 6U, // RLDCLo + 6U, // RLDCR + 6U, // RLDCRo + 0U, // RLDIC + 0U, // RLDICL + 0U, // RLDICL_32 + 0U, // RLDICL_32_64 + 0U, // RLDICL_32o + 0U, // RLDICLo + 0U, // RLDICR + 0U, // RLDICR_32 + 0U, // RLDICRo + 0U, // RLDICo + 0U, // RLDIMI + 0U, // RLDIMIo + 0U, // RLWIMI + 0U, // RLWIMI8 + 0U, // RLWIMI8o + 0U, // RLWIMIo + 578U, // RLWINM + 578U, // RLWINM8 + 578U, // RLWINM8o + 578U, // RLWINMo + 582U, // RLWNM + 582U, // RLWNM8 + 582U, // RLWNM8o + 582U, // RLWNMo + 0U, // ReadTB + 0U, // SC + 0U, // SELECT_CC_F16 + 0U, // SELECT_CC_F4 + 0U, // SELECT_CC_F8 + 0U, // SELECT_CC_I4 + 0U, // SELECT_CC_I8 + 0U, // SELECT_CC_QBRC + 0U, // SELECT_CC_QFRC + 0U, // SELECT_CC_QSRC + 0U, // SELECT_CC_SPE + 0U, // SELECT_CC_SPE4 + 0U, // SELECT_CC_VRRC + 0U, // SELECT_CC_VSFRC + 0U, // SELECT_CC_VSRC + 0U, // SELECT_CC_VSSRC + 0U, // SELECT_F16 + 0U, // SELECT_F4 + 0U, // SELECT_F8 + 0U, // SELECT_I4 + 0U, // SELECT_I8 + 0U, // SELECT_QBRC + 0U, // SELECT_QFRC + 0U, // SELECT_QSRC + 0U, // SELECT_SPE + 0U, // SELECT_SPE4 + 0U, // SELECT_VRRC + 0U, // SELECT_VSFRC + 0U, // SELECT_VSRC + 0U, // SELECT_VSSRC + 0U, // SETB + 0U, // SLBIA + 0U, // SLBIE + 0U, // SLBIEG + 0U, // SLBMFEE + 0U, // SLBMFEV + 0U, // SLBMTE + 0U, // SLBSYNC + 38U, // SLD + 38U, // SLDo + 38U, // SLW + 38U, // SLW8 + 38U, // SLW8o + 38U, // SLWo + 0U, // SPELWZ + 0U, // SPELWZX + 0U, // SPESTW + 0U, // SPESTWX + 0U, // SPILL_CR + 0U, // SPILL_CRBIT + 0U, // SPILL_VRSAVE + 38U, // SRAD + 32U, // SRADI + 32U, // SRADI_32 + 32U, // SRADIo + 38U, // SRADo + 38U, // SRAW + 34U, // SRAWI + 34U, // SRAWIo + 38U, // SRAWo + 38U, // SRD + 38U, // SRDo + 38U, // SRW + 38U, // SRW8 + 38U, // SRW8o + 38U, // SRWo + 0U, // STB + 0U, // STB8 + 38U, // STBCIX + 0U, // STBCX + 0U, // STBEPX + 0U, // STBU + 0U, // STBU8 + 0U, // STBUX + 0U, // STBUX8 + 0U, // STBX + 0U, // STBX8 + 38U, // STBXTLS + 38U, // STBXTLS_ + 38U, // STBXTLS_32 + 0U, // STD + 34U, // STDAT + 0U, // STDBRX + 38U, // STDCIX + 0U, // STDCX + 0U, // STDU + 0U, // STDUX + 0U, // STDX + 38U, // STDXTLS + 38U, // STDXTLS_ + 0U, // STFD + 0U, // STFDEPX + 0U, // STFDU + 0U, // STFDUX + 0U, // STFDX + 0U, // STFIWX + 0U, // STFS + 0U, // STFSU + 0U, // STFSUX + 0U, // STFSX + 0U, // STH + 0U, // STH8 + 0U, // STHBRX + 38U, // STHCIX + 0U, // STHCX + 0U, // STHEPX + 0U, // STHU + 0U, // STHU8 + 0U, // STHUX + 0U, // STHUX8 + 0U, // STHX + 0U, // STHX8 + 38U, // STHXTLS + 38U, // STHXTLS_ + 38U, // STHXTLS_32 + 0U, // STMW + 0U, // STOP + 34U, // STSWI + 0U, // STVEBX + 0U, // STVEHX + 0U, // STVEWX + 0U, // STVX + 0U, // STVXL + 0U, // STW + 0U, // STW8 + 34U, // STWAT + 0U, // STWBRX + 38U, // STWCIX + 0U, // STWCX + 0U, // STWEPX + 0U, // STWU + 0U, // STWU8 + 0U, // STWUX + 0U, // STWUX8 + 0U, // STWX + 0U, // STWX8 + 38U, // STWXTLS + 38U, // STWXTLS_ + 38U, // STWXTLS_32 + 0U, // STXSD + 0U, // STXSDX + 0U, // STXSIBX + 0U, // STXSIBXv + 0U, // STXSIHX + 0U, // STXSIHXv + 0U, // STXSIWX + 0U, // STXSSP + 0U, // STXSSPX + 0U, // STXV + 0U, // STXVB16X + 0U, // STXVD2X + 0U, // STXVH8X + 38U, // STXVL + 38U, // STXVLL + 0U, // STXVW4X + 0U, // STXVX + 38U, // SUBF + 38U, // SUBF8 + 38U, // SUBF8o + 38U, // SUBFC + 38U, // SUBFC8 + 38U, // SUBFC8o + 38U, // SUBFCo + 38U, // SUBFE + 38U, // SUBFE8 + 38U, // SUBFE8o + 38U, // SUBFEo + 4U, // SUBFIC + 4U, // SUBFIC8 + 0U, // SUBFME + 0U, // SUBFME8 + 0U, // SUBFME8o + 0U, // SUBFMEo + 0U, // SUBFZE + 0U, // SUBFZE8 + 0U, // SUBFZE8o + 0U, // SUBFZEo + 38U, // SUBFo + 0U, // SYNC + 0U, // TABORT + 0U, // TABORTDC + 0U, // TABORTDCI + 0U, // TABORTWC + 0U, // TABORTWCI + 0U, // TAILB + 0U, // TAILB8 + 0U, // TAILBA + 0U, // TAILBA8 + 0U, // TAILBCTR + 0U, // TAILBCTR8 + 0U, // TBEGIN + 0U, // TCHECK + 0U, // TCHECK_RET + 0U, // TCRETURNai + 0U, // TCRETURNai8 + 0U, // TCRETURNdi + 0U, // TCRETURNdi8 + 0U, // TCRETURNri + 0U, // TCRETURNri8 + 38U, // TD + 4U, // TDI + 0U, // TEND + 0U, // TLBIA + 0U, // TLBIE + 0U, // TLBIEL + 0U, // TLBIVAX + 0U, // TLBLD + 0U, // TLBLI + 0U, // TLBRE + 38U, // TLBRE2 + 0U, // TLBSX + 38U, // TLBSX2 + 38U, // TLBSX2D + 0U, // TLBSYNC + 0U, // TLBWE + 38U, // TLBWE2 + 0U, // TRAP + 0U, // TRECHKPT + 0U, // TRECLAIM + 0U, // TSR + 38U, // TW + 4U, // TWI + 0U, // UPDATE_VRSAVE + 0U, // UpdateGBR + 38U, // VABSDUB + 38U, // VABSDUH + 38U, // VABSDUW + 38U, // VADDCUQ + 38U, // VADDCUW + 134U, // VADDECUQ + 134U, // VADDEUQM + 38U, // VADDFP + 38U, // VADDSBS + 38U, // VADDSHS + 38U, // VADDSWS + 38U, // VADDUBM + 38U, // VADDUBS + 38U, // VADDUDM + 38U, // VADDUHM + 38U, // VADDUHS + 38U, // VADDUQM + 38U, // VADDUWM + 38U, // VADDUWS + 38U, // VAND + 38U, // VANDC + 38U, // VAVGSB + 38U, // VAVGSH + 38U, // VAVGSW + 38U, // VAVGUB + 38U, // VAVGUH + 38U, // VAVGUW + 38U, // VBPERMD + 38U, // VBPERMQ + 1U, // VCFSX + 1U, // VCFSX_0 + 1U, // VCFUX + 1U, // VCFUX_0 + 38U, // VCIPHER + 38U, // VCIPHERLAST + 0U, // VCLZB + 0U, // VCLZD + 0U, // VCLZH + 0U, // VCLZLSBB + 0U, // VCLZW + 38U, // VCMPBFP + 38U, // VCMPBFPo + 38U, // VCMPEQFP + 38U, // VCMPEQFPo + 38U, // VCMPEQUB + 38U, // VCMPEQUBo + 38U, // VCMPEQUD + 38U, // VCMPEQUDo + 38U, // VCMPEQUH + 38U, // VCMPEQUHo + 38U, // VCMPEQUW + 38U, // VCMPEQUWo + 38U, // VCMPGEFP + 38U, // VCMPGEFPo + 38U, // VCMPGTFP + 38U, // VCMPGTFPo + 38U, // VCMPGTSB + 38U, // VCMPGTSBo + 38U, // VCMPGTSD + 38U, // VCMPGTSDo + 38U, // VCMPGTSH + 38U, // VCMPGTSHo + 38U, // VCMPGTSW + 38U, // VCMPGTSWo + 38U, // VCMPGTUB + 38U, // VCMPGTUBo + 38U, // VCMPGTUD + 38U, // VCMPGTUDo + 38U, // VCMPGTUH + 38U, // VCMPGTUHo + 38U, // VCMPGTUW + 38U, // VCMPGTUWo + 38U, // VCMPNEB + 38U, // VCMPNEBo + 38U, // VCMPNEH + 38U, // VCMPNEHo + 38U, // VCMPNEW + 38U, // VCMPNEWo + 38U, // VCMPNEZB + 38U, // VCMPNEZBo + 38U, // VCMPNEZH + 38U, // VCMPNEZHo + 38U, // VCMPNEZW + 38U, // VCMPNEZWo + 1U, // VCTSXS + 1U, // VCTSXS_0 + 1U, // VCTUXS + 1U, // VCTUXS_0 + 0U, // VCTZB + 0U, // VCTZD + 0U, // VCTZH + 0U, // VCTZLSBB + 0U, // VCTZW + 38U, // VEQV + 0U, // VEXPTEFP + 1U, // VEXTRACTD + 1U, // VEXTRACTUB + 1U, // VEXTRACTUH + 1U, // VEXTRACTUW + 0U, // VEXTSB2D + 0U, // VEXTSB2Ds + 0U, // VEXTSB2W + 0U, // VEXTSB2Ws + 0U, // VEXTSH2D + 0U, // VEXTSH2Ds + 0U, // VEXTSH2W + 0U, // VEXTSH2Ws + 0U, // VEXTSW2D + 0U, // VEXTSW2Ds + 38U, // VEXTUBLX + 38U, // VEXTUBRX + 38U, // VEXTUHLX + 38U, // VEXTUHRX + 38U, // VEXTUWLX + 38U, // VEXTUWRX + 0U, // VGBBD + 0U, // VINSERTB + 1U, // VINSERTD + 0U, // VINSERTH + 1U, // VINSERTW + 0U, // VLOGEFP + 134U, // VMADDFP + 38U, // VMAXFP + 38U, // VMAXSB + 38U, // VMAXSD + 38U, // VMAXSH + 38U, // VMAXSW + 38U, // VMAXUB + 38U, // VMAXUD + 38U, // VMAXUH + 38U, // VMAXUW + 134U, // VMHADDSHS + 134U, // VMHRADDSHS + 38U, // VMINFP + 38U, // VMINSB + 38U, // VMINSD + 38U, // VMINSH + 38U, // VMINSW + 38U, // VMINUB + 38U, // VMINUD + 38U, // VMINUH + 38U, // VMINUW + 134U, // VMLADDUHM + 38U, // VMRGEW + 38U, // VMRGHB + 38U, // VMRGHH + 38U, // VMRGHW + 38U, // VMRGLB + 38U, // VMRGLH + 38U, // VMRGLW + 38U, // VMRGOW + 134U, // VMSUMMBM + 134U, // VMSUMSHM + 134U, // VMSUMSHS + 134U, // VMSUMUBM + 134U, // VMSUMUHM + 134U, // VMSUMUHS + 0U, // VMUL10CUQ + 38U, // VMUL10ECUQ + 38U, // VMUL10EUQ + 0U, // VMUL10UQ + 38U, // VMULESB + 38U, // VMULESH + 38U, // VMULESW + 38U, // VMULEUB + 38U, // VMULEUH + 38U, // VMULEUW + 38U, // VMULOSB + 38U, // VMULOSH + 38U, // VMULOSW + 38U, // VMULOUB + 38U, // VMULOUH + 38U, // VMULOUW + 38U, // VMULUWM + 38U, // VNAND + 38U, // VNCIPHER + 38U, // VNCIPHERLAST + 0U, // VNEGD + 0U, // VNEGW + 134U, // VNMSUBFP + 38U, // VNOR + 38U, // VOR + 38U, // VORC + 134U, // VPERM + 134U, // VPERMR + 134U, // VPERMXOR + 38U, // VPKPX + 38U, // VPKSDSS + 38U, // VPKSDUS + 38U, // VPKSHSS + 38U, // VPKSHUS + 38U, // VPKSWSS + 38U, // VPKSWUS + 38U, // VPKUDUM + 38U, // VPKUDUS + 38U, // VPKUHUM + 38U, // VPKUHUS + 38U, // VPKUWUM + 38U, // VPKUWUS + 38U, // VPMSUMB + 38U, // VPMSUMD + 38U, // VPMSUMH + 38U, // VPMSUMW + 0U, // VPOPCNTB + 0U, // VPOPCNTD + 0U, // VPOPCNTH + 0U, // VPOPCNTW + 0U, // VPRTYBD + 0U, // VPRTYBQ + 0U, // VPRTYBW + 0U, // VREFP + 0U, // VRFIM + 0U, // VRFIN + 0U, // VRFIP + 0U, // VRFIZ + 38U, // VRLB + 38U, // VRLD + 38U, // VRLDMI + 38U, // VRLDNM + 38U, // VRLH + 38U, // VRLW + 38U, // VRLWMI + 38U, // VRLWNM + 0U, // VRSQRTEFP + 0U, // VSBOX + 134U, // VSEL + 394U, // VSHASIGMAD + 394U, // VSHASIGMAW + 38U, // VSL + 38U, // VSLB + 38U, // VSLD + 390U, // VSLDOI + 38U, // VSLH + 38U, // VSLO + 38U, // VSLV + 38U, // VSLW + 1U, // VSPLTB + 1U, // VSPLTBs + 1U, // VSPLTH + 1U, // VSPLTHs + 0U, // VSPLTISB + 0U, // VSPLTISH + 0U, // VSPLTISW + 1U, // VSPLTW + 38U, // VSR + 38U, // VSRAB + 38U, // VSRAD + 38U, // VSRAH + 38U, // VSRAW + 38U, // VSRB + 38U, // VSRD + 38U, // VSRH + 38U, // VSRO + 38U, // VSRV + 38U, // VSRW + 38U, // VSUBCUQ + 38U, // VSUBCUW + 134U, // VSUBECUQ + 134U, // VSUBEUQM + 38U, // VSUBFP + 38U, // VSUBSBS + 38U, // VSUBSHS + 38U, // VSUBSWS + 38U, // VSUBUBM + 38U, // VSUBUBS + 38U, // VSUBUDM + 38U, // VSUBUHM + 38U, // VSUBUHS + 38U, // VSUBUQM + 38U, // VSUBUWM + 38U, // VSUBUWS + 38U, // VSUM2SWS + 38U, // VSUM4SBS + 38U, // VSUM4SHS + 38U, // VSUM4UBS + 38U, // VSUMSWS + 0U, // VUPKHPX + 0U, // VUPKHSB + 0U, // VUPKHSH + 0U, // VUPKHSW + 0U, // VUPKLPX + 0U, // VUPKLSB + 0U, // VUPKLSH + 0U, // VUPKLSW + 38U, // VXOR + 12U, // V_SET0 + 12U, // V_SET0B + 12U, // V_SET0H + 0U, // V_SETALLONES + 0U, // V_SETALLONESB + 0U, // V_SETALLONESH + 0U, // WAIT + 0U, // WRTEE + 0U, // WRTEEI + 38U, // XOR + 38U, // XOR8 + 38U, // XOR8o + 8U, // XORI + 8U, // XORI8 + 8U, // XORIS + 8U, // XORIS8 + 38U, // XORo + 0U, // XSABSDP + 0U, // XSABSQP + 38U, // XSADDDP + 38U, // XSADDQP + 38U, // XSADDQPO + 38U, // XSADDSP + 38U, // XSCMPEQDP + 38U, // XSCMPEXPDP + 38U, // XSCMPEXPQP + 38U, // XSCMPGEDP + 38U, // XSCMPGTDP + 38U, // XSCMPODP + 38U, // XSCMPOQP + 38U, // XSCMPUDP + 38U, // XSCMPUQP + 38U, // XSCPSGNDP + 38U, // XSCPSGNQP + 0U, // XSCVDPHP + 0U, // XSCVDPQP + 0U, // XSCVDPSP + 0U, // XSCVDPSPN + 0U, // XSCVDPSXDS + 0U, // XSCVDPSXDSs + 0U, // XSCVDPSXWS + 0U, // XSCVDPSXWSs + 0U, // XSCVDPUXDS + 0U, // XSCVDPUXDSs + 0U, // XSCVDPUXWS + 0U, // XSCVDPUXWSs + 0U, // XSCVHPDP + 0U, // XSCVQPDP + 0U, // XSCVQPDPO + 0U, // XSCVQPSDZ + 0U, // XSCVQPSWZ + 0U, // XSCVQPUDZ + 0U, // XSCVQPUWZ + 0U, // XSCVSDQP + 0U, // XSCVSPDP + 0U, // XSCVSPDPN + 0U, // XSCVSXDDP + 0U, // XSCVSXDSP + 0U, // XSCVUDQP + 0U, // XSCVUXDDP + 0U, // XSCVUXDSP + 38U, // XSDIVDP + 38U, // XSDIVQP + 38U, // XSDIVQPO + 38U, // XSDIVSP + 38U, // XSIEXPDP + 38U, // XSIEXPQP + 1U, // XSMADDADP + 1U, // XSMADDASP + 1U, // XSMADDMDP + 1U, // XSMADDMSP + 1U, // XSMADDQP + 1U, // XSMADDQPO + 38U, // XSMAXCDP + 38U, // XSMAXDP + 38U, // XSMAXJDP + 38U, // XSMINCDP + 38U, // XSMINDP + 38U, // XSMINJDP + 1U, // XSMSUBADP + 1U, // XSMSUBASP + 1U, // XSMSUBMDP + 1U, // XSMSUBMSP + 1U, // XSMSUBQP + 1U, // XSMSUBQPO + 38U, // XSMULDP + 38U, // XSMULQP + 38U, // XSMULQPO + 38U, // XSMULSP + 0U, // XSNABSDP + 0U, // XSNABSQP + 0U, // XSNEGDP + 0U, // XSNEGQP + 1U, // XSNMADDADP + 1U, // XSNMADDASP + 1U, // XSNMADDMDP + 1U, // XSNMADDMSP + 1U, // XSNMADDQP + 1U, // XSNMADDQPO + 1U, // XSNMSUBADP + 1U, // XSNMSUBASP + 1U, // XSNMSUBMDP + 1U, // XSNMSUBMSP + 1U, // XSNMSUBQP + 1U, // XSNMSUBQPO + 0U, // XSRDPI + 0U, // XSRDPIC + 0U, // XSRDPIM + 0U, // XSRDPIP + 0U, // XSRDPIZ + 0U, // XSREDP + 0U, // XSRESP + 262U, // XSRQPI + 262U, // XSRQPIX + 262U, // XSRQPXP + 0U, // XSRSP + 0U, // XSRSQRTEDP + 0U, // XSRSQRTESP + 0U, // XSSQRTDP + 0U, // XSSQRTQP + 0U, // XSSQRTQPO + 0U, // XSSQRTSP + 38U, // XSSUBDP + 38U, // XSSUBQP + 38U, // XSSUBQPO + 38U, // XSSUBSP + 38U, // XSTDIVDP + 0U, // XSTSQRTDP + 1U, // XSTSTDCDP + 1U, // XSTSTDCQP + 1U, // XSTSTDCSP + 0U, // XSXEXPDP + 0U, // XSXEXPQP + 0U, // XSXSIGDP + 0U, // XSXSIGQP + 0U, // XVABSDP + 0U, // XVABSSP + 38U, // XVADDDP + 38U, // XVADDSP + 38U, // XVCMPEQDP + 38U, // XVCMPEQDPo + 38U, // XVCMPEQSP + 38U, // XVCMPEQSPo + 38U, // XVCMPGEDP + 38U, // XVCMPGEDPo + 38U, // XVCMPGESP + 38U, // XVCMPGESPo + 38U, // XVCMPGTDP + 38U, // XVCMPGTDPo + 38U, // XVCMPGTSP + 38U, // XVCMPGTSPo + 38U, // XVCPSGNDP + 38U, // XVCPSGNSP + 0U, // XVCVDPSP + 0U, // XVCVDPSXDS + 0U, // XVCVDPSXWS + 0U, // XVCVDPUXDS + 0U, // XVCVDPUXWS + 0U, // XVCVHPSP + 0U, // XVCVSPDP + 0U, // XVCVSPHP + 0U, // XVCVSPSXDS + 0U, // XVCVSPSXWS + 0U, // XVCVSPUXDS + 0U, // XVCVSPUXWS + 0U, // XVCVSXDDP + 0U, // XVCVSXDSP + 0U, // XVCVSXWDP + 0U, // XVCVSXWSP + 0U, // XVCVUXDDP + 0U, // XVCVUXDSP + 0U, // XVCVUXWDP + 0U, // XVCVUXWSP + 38U, // XVDIVDP + 38U, // XVDIVSP + 38U, // XVIEXPDP + 38U, // XVIEXPSP + 1U, // XVMADDADP + 1U, // XVMADDASP + 1U, // XVMADDMDP + 1U, // XVMADDMSP + 38U, // XVMAXDP + 38U, // XVMAXSP + 38U, // XVMINDP + 38U, // XVMINSP + 1U, // XVMSUBADP + 1U, // XVMSUBASP + 1U, // XVMSUBMDP + 1U, // XVMSUBMSP + 38U, // XVMULDP + 38U, // XVMULSP + 0U, // XVNABSDP + 0U, // XVNABSSP + 0U, // XVNEGDP + 0U, // XVNEGSP + 1U, // XVNMADDADP + 1U, // XVNMADDASP + 1U, // XVNMADDMDP + 1U, // XVNMADDMSP + 1U, // XVNMSUBADP + 1U, // XVNMSUBASP + 1U, // XVNMSUBMDP + 1U, // XVNMSUBMSP + 0U, // XVRDPI + 0U, // XVRDPIC + 0U, // XVRDPIM + 0U, // XVRDPIP + 0U, // XVRDPIZ + 0U, // XVREDP + 0U, // XVRESP + 0U, // XVRSPI + 0U, // XVRSPIC + 0U, // XVRSPIM + 0U, // XVRSPIP + 0U, // XVRSPIZ + 0U, // XVRSQRTEDP + 0U, // XVRSQRTESP + 0U, // XVSQRTDP + 0U, // XVSQRTSP + 38U, // XVSUBDP + 38U, // XVSUBSP + 38U, // XVTDIVDP + 38U, // XVTDIVSP + 0U, // XVTSQRTDP + 0U, // XVTSQRTSP + 1U, // XVTSTDCDP + 1U, // XVTSTDCSP + 0U, // XVXEXPDP + 0U, // XVXEXPSP + 0U, // XVXSIGDP + 0U, // XVXSIGSP + 0U, // XXBRD + 0U, // XXBRH + 0U, // XXBRQ + 0U, // XXBRW + 20U, // XXEXTRACTUW + 1U, // XXINSERTW + 38U, // XXLAND + 38U, // XXLANDC + 38U, // XXLEQV + 38U, // XXLNAND + 38U, // XXLNOR + 38U, // XXLOR + 38U, // XXLORC + 38U, // XXLORf + 38U, // XXLXOR + 12U, // XXLXORdpz + 12U, // XXLXORspz + 12U, // XXLXORz + 38U, // XXMRGHW + 38U, // XXMRGLW + 38U, // XXPERM + 262U, // XXPERMDI + 462U, // XXPERMDIs + 38U, // XXPERMR + 134U, // XXSEL + 262U, // XXSLDWI + 462U, // XXSLDWIs + 0U, // XXSPLTIB + 16U, // XXSPLTW + 16U, // XXSPLTWs + 22U, // gBC + 24U, // gBCA + 0U, // gBCAat + 38U, // gBCCTR + 38U, // gBCCTRL + 22U, // gBCL + 24U, // gBCLA + 0U, // gBCLAat + 38U, // gBCLR + 38U, // gBCLRL + 0U, // gBCLat + 0U, // gBCat }; unsigned int opcode = MCInst_getOpcode(MI); @@ -5944,10 +19824,9 @@ static void printInstruction(MCInst *MI, SStream *O) Bits |= (uint64_t)OpInfo0[opcode] << 0; Bits |= (uint64_t)OpInfo1[opcode] << 32; #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 16383)-1); + SStream_concat0(O, AsmStrs + (Bits & 16383) - 1); #endif - // Fragment 0 encoded into 5 bits for 20 unique commands. // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 14) & 31)); switch ((Bits >> 14) & 31) { @@ -6062,7 +19941,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 1 encoded into 5 bits for 22 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 19) & 31)); switch ((Bits >> 19) & 31) { @@ -6212,7 +20090,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 2 encoded into 5 bits for 22 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 31)); switch ((Bits >> 24) & 31) { @@ -6336,7 +20213,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 3 encoded into 4 bits for 14 unique commands. // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 29) & 15)); switch ((Bits >> 29) & 15) { @@ -6423,7 +20299,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 4 encoded into 4 bits for 13 unique commands. // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 33) & 15)); switch ((Bits >> 33) & 15) { @@ -6492,7 +20367,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 5 encoded into 1 bits for 2 unique commands. // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 37) & 1)); if ((Bits >> 37) & 1) { @@ -6503,7 +20377,6 @@ static void printInstruction(MCInst *MI, SStream *O) SStream_concat0(O, ", "); } - // Fragment 6 encoded into 3 bits for 8 unique commands. // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 38) & 7)); switch ((Bits >> 38) & 7) { @@ -6549,7 +20422,6 @@ static void printInstruction(MCInst *MI, SStream *O) break; } - // Fragment 7 encoded into 1 bits for 2 unique commands. // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 41) & 1)); if ((Bits >> 41) & 1) { @@ -6561,22 +20433,21 @@ static void printInstruction(MCInst *MI, SStream *O) // CLRLSLWI, CLRLSLWIo, EXTLWI, EXTLWIo, EXTRWI, EXTRWIo, INSLWI, INSLWIo... return; } - } - - #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR -static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) -{ - #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) +static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) { +#define GETREGCLASS_CONTAIN(_class, _reg) \ + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), \ + MCOperand_getReg(MCInst_getOperand(MI, _reg))) unsigned int I = 0, OpIdx, PrintMethodIdx; char *tmpString; const char *AsmString; switch (MCInst_getOpcode(MI)) { - default: return false; + default: + return false; case PPC_ADDPCIS: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && @@ -8351,9 +22222,11 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 0))) { // (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) AsmString = "crset $\x01"; break; @@ -8366,7 +22239,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by) AsmString = "crnot $\x01, $\x02"; break; @@ -8379,7 +22253,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by) AsmString = "crmove $\x01, $\x02"; break; @@ -8390,9 +22265,11 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 0))) { // (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) AsmString = "crclr $\x01"; break; @@ -9335,7 +23212,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) AsmString = "not $\x01, $\x02"; break; @@ -9348,7 +23226,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB) AsmString = "not. $\x01, $\x02"; break; @@ -9361,7 +23240,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) AsmString = "mr $\x01, $\x02"; break; @@ -9374,7 +23254,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB) AsmString = "mr. $\x01, $\x02"; break; @@ -9385,9 +23266,11 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 0) @@ -9426,7 +23309,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 5) @@ -9491,7 +23375,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 10) @@ -9528,9 +23413,11 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 15) @@ -10156,7 +24043,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA) AsmString = "vnot $\x01, $\x02"; break; @@ -10169,7 +24057,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA) AsmString = "vmr $\x01, $\x02"; break; @@ -10216,7 +24105,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB) AsmString = "xvmovdp $\x01, $\x02"; break; @@ -10229,7 +24119,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB) AsmString = "xvmovsp $\x01, $\x02"; break; @@ -10242,7 +24133,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0) @@ -10255,7 +24147,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3) @@ -10294,7 +24187,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2) @@ -11183,11 +25077,10 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) return NULL; } - tmpString = cs_strdup(AsmString); - while (AsmString[I] != ' ' && AsmString[I] != '\t' && - AsmString[I] != '$' && AsmString[I] != '\0') + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') ++I; tmpString[I] = 0; @@ -11208,21 +25101,18 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) PrintMethodIdx = AsmString[I++] - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else - printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); + printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); } else { - SStream_concat1(OS, AsmString[I++]); + SStream_concat1(OS, AsmString[I++]); } } while (AsmString[I] != '\0'); } return tmpString; } - -static void printCustomAliasOperand( - MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - SStream *OS) -{ + +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { switch (PrintMethodIdx) { default: break; diff --git a/arch/PowerPC/PPCGenDisassemblerTables.inc b/arch/PowerPC/PPCGenDisassemblerTables.inc index be6d0b9e6b..bea7264dd2 100644 --- a/arch/PowerPC/PPCGenDisassemblerTables.inc +++ b/arch/PowerPC/PPCGenDisassemblerTables.inc @@ -1,22 +1,118 @@ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2019 */ -/* Automatically generated file, do not edit! */ - #include "../../MCInst.h" #include "../../LEB128.h" -// Helper function for extracting fields from encoded instructions. - -//#if defined(_MSC_VER) && !defined(__clang__) -//__declspec(noinline) -//#endif +#define PPC_AIXOS 0ULL +#define PPC_DeprecatedDST 1ULL +#define PPC_Directive32 2ULL +#define PPC_Directive64 3ULL +#define PPC_Directive440 4ULL +#define PPC_Directive601 5ULL +#define PPC_Directive602 6ULL +#define PPC_Directive603 7ULL +#define PPC_Directive604 8ULL +#define PPC_Directive620 9ULL +#define PPC_Directive750 10ULL +#define PPC_Directive970 11ULL +#define PPC_Directive7400 12ULL +#define PPC_DirectiveA2 13ULL +#define PPC_DirectiveE500 14ULL +#define PPC_DirectiveE500mc 15ULL +#define PPC_DirectiveE5500 16ULL +#define PPC_DirectivePwr3 17ULL +#define PPC_DirectivePwr4 18ULL +#define PPC_DirectivePwr5 19ULL +#define PPC_DirectivePwr5x 20ULL +#define PPC_DirectivePwr6 21ULL +#define PPC_DirectivePwr6x 22ULL +#define PPC_DirectivePwr7 23ULL +#define PPC_DirectivePwr8 24ULL +#define PPC_DirectivePwr9 25ULL +#define PPC_DirectivePwr10 26ULL +#define PPC_DirectivePwrFuture 27ULL +#define PPC_Feature64Bit 28ULL +#define PPC_Feature64BitRegs 29ULL +#define PPC_FeatureAddLogicalFusion 30ULL +#define PPC_FeatureAddiLoadFusion 31ULL +#define PPC_FeatureAddisLoadFusion 32ULL +#define PPC_FeatureAltivec 33ULL +#define PPC_FeatureArithAddFusion 34ULL +#define PPC_FeatureBPERMD 35ULL +#define PPC_FeatureBookE 36ULL +#define PPC_FeatureCMPB 37ULL +#define PPC_FeatureCRBits 38ULL +#define PPC_FeatureDirectMove 39ULL +#define PPC_FeatureE500 40ULL +#define PPC_FeatureEFPU2 41ULL +#define PPC_FeatureExtDiv 42ULL +#define PPC_FeatureFCPSGN 43ULL +#define PPC_FeatureFPCVT 44ULL +#define PPC_FeatureFPRND 45ULL +#define PPC_FeatureFPU 46ULL +#define PPC_FeatureFRE 47ULL +#define PPC_FeatureFRES 48ULL +#define PPC_FeatureFRSQRTE 49ULL +#define PPC_FeatureFRSQRTES 50ULL +#define PPC_FeatureFSqrt 51ULL +#define PPC_FeatureFloat128 52ULL +#define PPC_FeatureFusion 53ULL +#define PPC_FeatureHTM 54ULL +#define PPC_FeatureHardFloat 55ULL +#define PPC_FeatureICBT 56ULL +#define PPC_FeatureISA2_06 57ULL +#define PPC_FeatureISA2_07 58ULL +#define PPC_FeatureISA3_0 59ULL +#define PPC_FeatureISA3_1 60ULL +#define PPC_FeatureISEL 61ULL +#define PPC_FeatureInvariantFunctionDescriptors 62ULL +#define PPC_FeatureLDBRX 63ULL +#define PPC_FeatureLFIWAX 64ULL +#define PPC_FeatureLogicalAddFusion 65ULL +#define PPC_FeatureLogicalFusion 66ULL +#define PPC_FeatureLongCall 67ULL +#define PPC_FeatureMFOCRF 68ULL +#define PPC_FeatureMFTB 69ULL +#define PPC_FeatureMMA 70ULL +#define PPC_FeatureMSYNC 71ULL +#define PPC_FeatureModernAIXAs 72ULL +#define PPC_FeatureP8Altivec 73ULL +#define PPC_FeatureP8Crypto 74ULL +#define PPC_FeatureP8Vector 75ULL +#define PPC_FeatureP9Altivec 76ULL +#define PPC_FeatureP9Vector 77ULL +#define PPC_FeatureP10Vector 78ULL +#define PPC_FeaturePCRelativeMemops 79ULL +#define PPC_FeaturePOPCNTD 80ULL +#define PPC_FeaturePPC4xx 81ULL +#define PPC_FeaturePPC6xx 82ULL +#define PPC_FeaturePPCPostRASched 83ULL +#define PPC_FeaturePPCPreRASched 84ULL +#define PPC_FeaturePairedVectorMemops 85ULL +#define PPC_FeaturePartwordAtomic 86ULL +#define PPC_FeaturePredictableSelectIsExpensive 87ULL +#define PPC_FeaturePrefixInstrs 88ULL +#define PPC_FeaturePrivileged 89ULL +#define PPC_FeatureQuadwordAtomic 90ULL +#define PPC_FeatureROPProtect 91ULL +#define PPC_FeatureRecipPrec 92ULL +#define PPC_FeatureSPE 93ULL +#define PPC_FeatureSTFIWX 94ULL +#define PPC_FeatureSecurePlt 95ULL +#define PPC_FeatureSlowPOPCNTD 96ULL +#define PPC_FeatureStoreFusion 97ULL +#define PPC_FeatureTwoConstNR 98ULL +#define PPC_FeatureUnalignedFloats 99ULL +#define PPC_FeatureVSX 100ULL +#define PPC_FeatureVectorsUseTwoUnits 101ULL +#ifdef MIPS_GET_DISASSEMBLER +#undef MIPS_GET_DISASSEMBLER +// Helper function for extracting fields from encoded instructions. #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ - if (numBits == sizeof(InsnType) * 8) \ + if (numBits == sizeof(InsnType)*8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ @@ -26,3779 +122,4781 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 3 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 20 -/* 8 */ MCD_OPC_CheckField, 1, 10, 128, 2, 34, 64, 0, // Skip to: 16434 -/* 16 */ MCD_OPC_Decode, 189, 2, 0, // Opcode: ATTN +/* 8 */ MCD_OPC_CheckField, 1, 10, 128, 2, 100, 84, 0, // Skip to: 21620 +/* 16 */ MCD_OPC_Decode, 210, 3, 0, // Opcode: ATTN /* 20 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 29 -/* 25 */ MCD_OPC_Decode, 165, 12, 1, // Opcode: TDI +/* 25 */ MCD_OPC_Decode, 245, 13, 1, // Opcode: TDI /* 29 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 38 -/* 34 */ MCD_OPC_Decode, 186, 12, 2, // Opcode: TWI -/* 38 */ MCD_OPC_FilterValue, 4, 12, 12, 0, // Skip to: 3127 -/* 43 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 46 */ MCD_OPC_FilterValue, 0, 237, 0, 0, // Skip to: 288 -/* 51 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 54 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 63 -/* 59 */ MCD_OPC_Decode, 200, 12, 3, // Opcode: VADDUBM -/* 63 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 72 -/* 68 */ MCD_OPC_Decode, 203, 12, 3, // Opcode: VADDUHM -/* 72 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 81 -/* 77 */ MCD_OPC_Decode, 206, 12, 3, // Opcode: VADDUWM -/* 81 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 90 -/* 86 */ MCD_OPC_Decode, 202, 12, 3, // Opcode: VADDUDM -/* 90 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 99 -/* 95 */ MCD_OPC_Decode, 205, 12, 3, // Opcode: VADDUQM -/* 99 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 108 -/* 104 */ MCD_OPC_Decode, 192, 12, 3, // Opcode: VADDCUQ -/* 108 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 117 -/* 113 */ MCD_OPC_Decode, 193, 12, 3, // Opcode: VADDCUW -/* 117 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 126 -/* 122 */ MCD_OPC_Decode, 201, 12, 3, // Opcode: VADDUBS -/* 126 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 135 -/* 131 */ MCD_OPC_Decode, 204, 12, 3, // Opcode: VADDUHS -/* 135 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 144 -/* 140 */ MCD_OPC_Decode, 207, 12, 3, // Opcode: VADDUWS -/* 144 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 153 -/* 149 */ MCD_OPC_Decode, 197, 12, 3, // Opcode: VADDSBS -/* 153 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 162 -/* 158 */ MCD_OPC_Decode, 198, 12, 3, // Opcode: VADDSHS -/* 162 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 171 -/* 167 */ MCD_OPC_Decode, 199, 12, 3, // Opcode: VADDSWS -/* 171 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 180 -/* 176 */ MCD_OPC_Decode, 196, 14, 3, // Opcode: VSUBUBM -/* 180 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 189 -/* 185 */ MCD_OPC_Decode, 199, 14, 3, // Opcode: VSUBUHM -/* 189 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 198 -/* 194 */ MCD_OPC_Decode, 202, 14, 3, // Opcode: VSUBUWM -/* 198 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 207 -/* 203 */ MCD_OPC_Decode, 198, 14, 3, // Opcode: VSUBUDM -/* 207 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 216 -/* 212 */ MCD_OPC_Decode, 201, 14, 3, // Opcode: VSUBUQM -/* 216 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 225 -/* 221 */ MCD_OPC_Decode, 188, 14, 3, // Opcode: VSUBCUQ -/* 225 */ MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 234 -/* 230 */ MCD_OPC_Decode, 189, 14, 3, // Opcode: VSUBCUW -/* 234 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 243 -/* 239 */ MCD_OPC_Decode, 197, 14, 3, // Opcode: VSUBUBS -/* 243 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 252 -/* 248 */ MCD_OPC_Decode, 200, 14, 3, // Opcode: VSUBUHS -/* 252 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 261 -/* 257 */ MCD_OPC_Decode, 203, 14, 3, // Opcode: VSUBUWS -/* 261 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 270 -/* 266 */ MCD_OPC_Decode, 193, 14, 3, // Opcode: VSUBSBS -/* 270 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 279 -/* 275 */ MCD_OPC_Decode, 194, 14, 3, // Opcode: VSUBSHS -/* 279 */ MCD_OPC_FilterValue, 30, 22, 63, 0, // Skip to: 16434 -/* 284 */ MCD_OPC_Decode, 195, 14, 3, // Opcode: VSUBSWS -/* 288 */ MCD_OPC_FilterValue, 1, 9, 1, 0, // Skip to: 558 -/* 293 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... -/* 296 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 322 -/* 301 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... -/* 304 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 313 -/* 309 */ MCD_OPC_Decode, 218, 13, 4, // Opcode: VMUL10CUQ -/* 313 */ MCD_OPC_FilterValue, 1, 244, 62, 0, // Skip to: 16434 -/* 318 */ MCD_OPC_Decode, 221, 13, 4, // Opcode: VMUL10UQ -/* 322 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 348 -/* 327 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 330 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 339 -/* 335 */ MCD_OPC_Decode, 219, 13, 3, // Opcode: VMUL10ECUQ -/* 339 */ MCD_OPC_FilterValue, 1, 218, 62, 0, // Skip to: 16434 -/* 344 */ MCD_OPC_Decode, 220, 13, 3, // Opcode: VMUL10EUQ -/* 348 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 364 -/* 353 */ MCD_OPC_CheckField, 9, 2, 2, 202, 62, 0, // Skip to: 16434 -/* 360 */ MCD_OPC_Decode, 222, 2, 3, // Opcode: BCDUSo -/* 364 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 380 -/* 369 */ MCD_OPC_CheckField, 10, 1, 1, 186, 62, 0, // Skip to: 16434 -/* 376 */ MCD_OPC_Decode, 220, 2, 5, // Opcode: BCDSo -/* 380 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 396 -/* 385 */ MCD_OPC_CheckField, 10, 1, 1, 170, 62, 0, // Skip to: 16434 -/* 392 */ MCD_OPC_Decode, 221, 2, 5, // Opcode: BCDTRUNCo -/* 396 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 422 -/* 401 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 404 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 413 -/* 409 */ MCD_OPC_Decode, 214, 2, 3, // Opcode: BCDCPSGNo -/* 413 */ MCD_OPC_FilterValue, 2, 144, 62, 0, // Skip to: 16434 -/* 418 */ MCD_OPC_Decode, 223, 2, 3, // Opcode: BCDUTRUNCo -/* 422 */ MCD_OPC_FilterValue, 6, 115, 0, 0, // Skip to: 542 -/* 427 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 430 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 446 -/* 435 */ MCD_OPC_CheckField, 9, 2, 2, 120, 62, 0, // Skip to: 16434 -/* 442 */ MCD_OPC_Decode, 216, 2, 6, // Opcode: BCDCTSQo -/* 446 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 462 -/* 451 */ MCD_OPC_CheckField, 10, 1, 1, 104, 62, 0, // Skip to: 16434 -/* 458 */ MCD_OPC_Decode, 212, 2, 7, // Opcode: BCDCFSQo -/* 462 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 478 -/* 467 */ MCD_OPC_CheckField, 10, 1, 1, 88, 62, 0, // Skip to: 16434 -/* 474 */ MCD_OPC_Decode, 217, 2, 7, // Opcode: BCDCTZo -/* 478 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 494 -/* 483 */ MCD_OPC_CheckField, 9, 2, 2, 72, 62, 0, // Skip to: 16434 -/* 490 */ MCD_OPC_Decode, 215, 2, 6, // Opcode: BCDCTNo -/* 494 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 510 -/* 499 */ MCD_OPC_CheckField, 10, 1, 1, 56, 62, 0, // Skip to: 16434 -/* 506 */ MCD_OPC_Decode, 213, 2, 7, // Opcode: BCDCFZo -/* 510 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 526 -/* 515 */ MCD_OPC_CheckField, 10, 1, 1, 40, 62, 0, // Skip to: 16434 -/* 522 */ MCD_OPC_Decode, 211, 2, 7, // Opcode: BCDCFNo -/* 526 */ MCD_OPC_FilterValue, 31, 31, 62, 0, // Skip to: 16434 -/* 531 */ MCD_OPC_CheckField, 10, 1, 1, 24, 62, 0, // Skip to: 16434 -/* 538 */ MCD_OPC_Decode, 218, 2, 7, // Opcode: BCDSETSGNo -/* 542 */ MCD_OPC_FilterValue, 7, 15, 62, 0, // Skip to: 16434 -/* 547 */ MCD_OPC_CheckField, 10, 1, 1, 8, 62, 0, // Skip to: 16434 -/* 554 */ MCD_OPC_Decode, 219, 2, 5, // Opcode: BCDSRo -/* 558 */ MCD_OPC_FilterValue, 2, 179, 1, 0, // Skip to: 998 -/* 563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 566 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 575 -/* 571 */ MCD_OPC_Decode, 188, 13, 3, // Opcode: VMAXUB -/* 575 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 584 -/* 580 */ MCD_OPC_Decode, 190, 13, 3, // Opcode: VMAXUH -/* 584 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 593 -/* 589 */ MCD_OPC_Decode, 191, 13, 3, // Opcode: VMAXUW -/* 593 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 602 -/* 598 */ MCD_OPC_Decode, 189, 13, 3, // Opcode: VMAXUD -/* 602 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 611 -/* 607 */ MCD_OPC_Decode, 184, 13, 3, // Opcode: VMAXSB -/* 611 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 620 -/* 616 */ MCD_OPC_Decode, 186, 13, 3, // Opcode: VMAXSH -/* 620 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 629 -/* 625 */ MCD_OPC_Decode, 187, 13, 3, // Opcode: VMAXSW -/* 629 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 638 -/* 634 */ MCD_OPC_Decode, 185, 13, 3, // Opcode: VMAXSD -/* 638 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 647 -/* 643 */ MCD_OPC_Decode, 199, 13, 3, // Opcode: VMINUB -/* 647 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 656 -/* 652 */ MCD_OPC_Decode, 201, 13, 3, // Opcode: VMINUH -/* 656 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 665 -/* 661 */ MCD_OPC_Decode, 202, 13, 3, // Opcode: VMINUW -/* 665 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 674 -/* 670 */ MCD_OPC_Decode, 200, 13, 3, // Opcode: VMINUD -/* 674 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 683 -/* 679 */ MCD_OPC_Decode, 195, 13, 3, // Opcode: VMINSB -/* 683 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 692 -/* 688 */ MCD_OPC_Decode, 197, 13, 3, // Opcode: VMINSH -/* 692 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 701 -/* 697 */ MCD_OPC_Decode, 198, 13, 3, // Opcode: VMINSW -/* 701 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 710 -/* 706 */ MCD_OPC_Decode, 196, 13, 3, // Opcode: VMINSD -/* 710 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 719 -/* 715 */ MCD_OPC_Decode, 213, 12, 3, // Opcode: VAVGUB -/* 719 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 728 -/* 724 */ MCD_OPC_Decode, 214, 12, 3, // Opcode: VAVGUH -/* 728 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 737 -/* 733 */ MCD_OPC_Decode, 215, 12, 3, // Opcode: VAVGUW -/* 737 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 746 -/* 742 */ MCD_OPC_Decode, 210, 12, 3, // Opcode: VAVGSB -/* 746 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 755 -/* 751 */ MCD_OPC_Decode, 211, 12, 3, // Opcode: VAVGSH -/* 755 */ MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 764 -/* 760 */ MCD_OPC_Decode, 212, 12, 3, // Opcode: VAVGSW -/* 764 */ MCD_OPC_FilterValue, 24, 147, 0, 0, // Skip to: 916 -/* 769 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 772 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 781 -/* 777 */ MCD_OPC_Decode, 227, 12, 8, // Opcode: VCLZLSBB -/* 781 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 790 -/* 786 */ MCD_OPC_Decode, 152, 13, 8, // Opcode: VCTZLSBB -/* 790 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 799 -/* 795 */ MCD_OPC_Decode, 239, 13, 6, // Opcode: VNEGW -/* 799 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 808 -/* 804 */ MCD_OPC_Decode, 238, 13, 6, // Opcode: VNEGD -/* 808 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 817 -/* 813 */ MCD_OPC_Decode, 142, 14, 6, // Opcode: VPRTYBW -/* 817 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 826 -/* 822 */ MCD_OPC_Decode, 140, 14, 6, // Opcode: VPRTYBD -/* 826 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 835 -/* 831 */ MCD_OPC_Decode, 141, 14, 6, // Opcode: VPRTYBQ -/* 835 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 844 -/* 840 */ MCD_OPC_Decode, 162, 13, 6, // Opcode: VEXTSB2W -/* 844 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 853 -/* 849 */ MCD_OPC_Decode, 166, 13, 6, // Opcode: VEXTSH2W -/* 853 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 862 -/* 858 */ MCD_OPC_Decode, 160, 13, 6, // Opcode: VEXTSB2D -/* 862 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 871 -/* 867 */ MCD_OPC_Decode, 164, 13, 6, // Opcode: VEXTSH2D -/* 871 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 880 -/* 876 */ MCD_OPC_Decode, 168, 13, 6, // Opcode: VEXTSW2D -/* 880 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 889 -/* 885 */ MCD_OPC_Decode, 149, 13, 6, // Opcode: VCTZB -/* 889 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 898 -/* 894 */ MCD_OPC_Decode, 151, 13, 6, // Opcode: VCTZH -/* 898 */ MCD_OPC_FilterValue, 30, 4, 0, 0, // Skip to: 907 -/* 903 */ MCD_OPC_Decode, 153, 13, 6, // Opcode: VCTZW -/* 907 */ MCD_OPC_FilterValue, 31, 162, 60, 0, // Skip to: 16434 -/* 912 */ MCD_OPC_Decode, 150, 13, 6, // Opcode: VCTZD -/* 916 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 925 -/* 921 */ MCD_OPC_Decode, 160, 14, 9, // Opcode: VSHASIGMAW -/* 925 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 934 -/* 930 */ MCD_OPC_Decode, 159, 14, 9, // Opcode: VSHASIGMAD -/* 934 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 950 -/* 939 */ MCD_OPC_CheckField, 16, 5, 0, 128, 60, 0, // Skip to: 16434 -/* 946 */ MCD_OPC_Decode, 224, 12, 6, // Opcode: VCLZB -/* 950 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 966 -/* 955 */ MCD_OPC_CheckField, 16, 5, 0, 112, 60, 0, // Skip to: 16434 -/* 962 */ MCD_OPC_Decode, 226, 12, 6, // Opcode: VCLZH -/* 966 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 982 -/* 971 */ MCD_OPC_CheckField, 16, 5, 0, 96, 60, 0, // Skip to: 16434 -/* 978 */ MCD_OPC_Decode, 228, 12, 6, // Opcode: VCLZW -/* 982 */ MCD_OPC_FilterValue, 31, 87, 60, 0, // Skip to: 16434 -/* 987 */ MCD_OPC_CheckField, 16, 5, 0, 80, 60, 0, // Skip to: 16434 -/* 994 */ MCD_OPC_Decode, 225, 12, 6, // Opcode: VCLZD -/* 998 */ MCD_OPC_FilterValue, 3, 94, 0, 0, // Skip to: 1097 -/* 1003 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 1006 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1015 -/* 1011 */ MCD_OPC_Decode, 189, 12, 3, // Opcode: VABSDUB -/* 1015 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1024 -/* 1020 */ MCD_OPC_Decode, 190, 12, 3, // Opcode: VABSDUH -/* 1024 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1033 -/* 1029 */ MCD_OPC_Decode, 191, 12, 3, // Opcode: VABSDUW -/* 1033 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 1049 -/* 1038 */ MCD_OPC_CheckField, 16, 5, 0, 29, 60, 0, // Skip to: 16434 -/* 1045 */ MCD_OPC_Decode, 136, 14, 6, // Opcode: VPOPCNTB -/* 1049 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 1065 -/* 1054 */ MCD_OPC_CheckField, 16, 5, 0, 13, 60, 0, // Skip to: 16434 -/* 1061 */ MCD_OPC_Decode, 138, 14, 6, // Opcode: VPOPCNTH -/* 1065 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 1081 -/* 1070 */ MCD_OPC_CheckField, 16, 5, 0, 253, 59, 0, // Skip to: 16434 -/* 1077 */ MCD_OPC_Decode, 139, 14, 6, // Opcode: VPOPCNTW -/* 1081 */ MCD_OPC_FilterValue, 31, 244, 59, 0, // Skip to: 16434 -/* 1086 */ MCD_OPC_CheckField, 16, 5, 0, 237, 59, 0, // Skip to: 16434 -/* 1093 */ MCD_OPC_Decode, 137, 14, 6, // Opcode: VPOPCNTD -/* 1097 */ MCD_OPC_FilterValue, 4, 31, 1, 0, // Skip to: 1389 -/* 1102 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 1105 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1114 -/* 1110 */ MCD_OPC_Decode, 148, 14, 3, // Opcode: VRLB -/* 1114 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1123 -/* 1119 */ MCD_OPC_Decode, 152, 14, 3, // Opcode: VRLH -/* 1123 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1132 -/* 1128 */ MCD_OPC_Decode, 153, 14, 3, // Opcode: VRLW -/* 1132 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1141 -/* 1137 */ MCD_OPC_Decode, 149, 14, 3, // Opcode: VRLD -/* 1141 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1150 -/* 1146 */ MCD_OPC_Decode, 162, 14, 3, // Opcode: VSLB -/* 1150 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1159 -/* 1155 */ MCD_OPC_Decode, 165, 14, 3, // Opcode: VSLH -/* 1159 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1168 -/* 1164 */ MCD_OPC_Decode, 168, 14, 3, // Opcode: VSLW -/* 1168 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 1177 -/* 1173 */ MCD_OPC_Decode, 161, 14, 3, // Opcode: VSL -/* 1177 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1186 -/* 1182 */ MCD_OPC_Decode, 182, 14, 3, // Opcode: VSRB -/* 1186 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1195 -/* 1191 */ MCD_OPC_Decode, 184, 14, 3, // Opcode: VSRH -/* 1195 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1204 -/* 1200 */ MCD_OPC_Decode, 187, 14, 3, // Opcode: VSRW -/* 1204 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 1213 -/* 1209 */ MCD_OPC_Decode, 177, 14, 3, // Opcode: VSR -/* 1213 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 1222 -/* 1218 */ MCD_OPC_Decode, 178, 14, 3, // Opcode: VSRAB -/* 1222 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 1231 -/* 1227 */ MCD_OPC_Decode, 180, 14, 3, // Opcode: VSRAH -/* 1231 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 1240 -/* 1236 */ MCD_OPC_Decode, 181, 14, 3, // Opcode: VSRAW -/* 1240 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 1249 -/* 1245 */ MCD_OPC_Decode, 179, 14, 3, // Opcode: VSRAD -/* 1249 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1258 -/* 1254 */ MCD_OPC_Decode, 208, 12, 3, // Opcode: VAND -/* 1258 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1267 -/* 1263 */ MCD_OPC_Decode, 209, 12, 3, // Opcode: VANDC -/* 1267 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1276 -/* 1272 */ MCD_OPC_Decode, 242, 13, 3, // Opcode: VOR -/* 1276 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 1285 -/* 1281 */ MCD_OPC_Decode, 217, 14, 3, // Opcode: VXOR -/* 1285 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 1294 -/* 1290 */ MCD_OPC_Decode, 241, 13, 3, // Opcode: VNOR -/* 1294 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 1303 -/* 1299 */ MCD_OPC_Decode, 243, 13, 3, // Opcode: VORC -/* 1303 */ MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 1312 -/* 1308 */ MCD_OPC_Decode, 235, 13, 3, // Opcode: VNAND -/* 1312 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 1321 -/* 1317 */ MCD_OPC_Decode, 163, 14, 3, // Opcode: VSLD -/* 1321 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 1337 -/* 1326 */ MCD_OPC_CheckField, 11, 10, 0, 253, 58, 0, // Skip to: 16434 -/* 1333 */ MCD_OPC_Decode, 180, 8, 10, // Opcode: MFVSCR -/* 1337 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 1353 -/* 1342 */ MCD_OPC_CheckField, 16, 10, 0, 237, 58, 0, // Skip to: 16434 -/* 1349 */ MCD_OPC_Decode, 217, 8, 11, // Opcode: MTVSCR -/* 1353 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 1362 -/* 1358 */ MCD_OPC_Decode, 154, 13, 3, // Opcode: VEQV -/* 1362 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 1371 -/* 1367 */ MCD_OPC_Decode, 183, 14, 3, // Opcode: VSRD -/* 1371 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 1380 -/* 1376 */ MCD_OPC_Decode, 186, 14, 3, // Opcode: VSRV -/* 1380 */ MCD_OPC_FilterValue, 29, 201, 58, 0, // Skip to: 16434 -/* 1385 */ MCD_OPC_Decode, 167, 14, 3, // Opcode: VSLV -/* 1389 */ MCD_OPC_FilterValue, 5, 39, 0, 0, // Skip to: 1433 -/* 1394 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 1397 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1406 -/* 1402 */ MCD_OPC_Decode, 154, 14, 12, // Opcode: VRLWMI -/* 1406 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1415 -/* 1411 */ MCD_OPC_Decode, 150, 14, 12, // Opcode: VRLDMI -/* 1415 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1424 -/* 1420 */ MCD_OPC_Decode, 155, 14, 3, // Opcode: VRLWNM -/* 1424 */ MCD_OPC_FilterValue, 7, 157, 58, 0, // Skip to: 16434 -/* 1429 */ MCD_OPC_Decode, 151, 14, 3, // Opcode: VRLDNM -/* 1433 */ MCD_OPC_FilterValue, 6, 237, 0, 0, // Skip to: 1675 -/* 1438 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 1441 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1450 -/* 1446 */ MCD_OPC_Decode, 233, 12, 3, // Opcode: VCMPEQUB -/* 1450 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1459 -/* 1455 */ MCD_OPC_Decode, 237, 12, 3, // Opcode: VCMPEQUH -/* 1459 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1468 -/* 1464 */ MCD_OPC_Decode, 239, 12, 3, // Opcode: VCMPEQUW -/* 1468 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1477 -/* 1473 */ MCD_OPC_Decode, 231, 12, 3, // Opcode: VCMPEQFP -/* 1477 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 1486 -/* 1482 */ MCD_OPC_Decode, 241, 12, 3, // Opcode: VCMPGEFP -/* 1486 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1495 -/* 1491 */ MCD_OPC_Decode, 253, 12, 3, // Opcode: VCMPGTUB -/* 1495 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1504 -/* 1500 */ MCD_OPC_Decode, 129, 13, 3, // Opcode: VCMPGTUH -/* 1504 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1513 -/* 1509 */ MCD_OPC_Decode, 131, 13, 3, // Opcode: VCMPGTUW -/* 1513 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 1522 -/* 1518 */ MCD_OPC_Decode, 243, 12, 3, // Opcode: VCMPGTFP -/* 1522 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 1531 -/* 1527 */ MCD_OPC_Decode, 245, 12, 3, // Opcode: VCMPGTSB -/* 1531 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 1540 -/* 1536 */ MCD_OPC_Decode, 249, 12, 3, // Opcode: VCMPGTSH -/* 1540 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 1549 -/* 1545 */ MCD_OPC_Decode, 251, 12, 3, // Opcode: VCMPGTSW -/* 1549 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 1558 -/* 1554 */ MCD_OPC_Decode, 229, 12, 3, // Opcode: VCMPBFP -/* 1558 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1567 -/* 1563 */ MCD_OPC_Decode, 234, 12, 3, // Opcode: VCMPEQUBo -/* 1567 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1576 -/* 1572 */ MCD_OPC_Decode, 238, 12, 3, // Opcode: VCMPEQUHo -/* 1576 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1585 -/* 1581 */ MCD_OPC_Decode, 240, 12, 3, // Opcode: VCMPEQUWo -/* 1585 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 1594 -/* 1590 */ MCD_OPC_Decode, 232, 12, 3, // Opcode: VCMPEQFPo -/* 1594 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 1603 -/* 1599 */ MCD_OPC_Decode, 242, 12, 3, // Opcode: VCMPGEFPo -/* 1603 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 1612 -/* 1608 */ MCD_OPC_Decode, 254, 12, 3, // Opcode: VCMPGTUBo -/* 1612 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 1621 -/* 1617 */ MCD_OPC_Decode, 130, 13, 3, // Opcode: VCMPGTUHo -/* 1621 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 1630 -/* 1626 */ MCD_OPC_Decode, 132, 13, 3, // Opcode: VCMPGTUWo -/* 1630 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 1639 -/* 1635 */ MCD_OPC_Decode, 244, 12, 3, // Opcode: VCMPGTFPo -/* 1639 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 1648 -/* 1644 */ MCD_OPC_Decode, 246, 12, 3, // Opcode: VCMPGTSBo -/* 1648 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 1657 -/* 1653 */ MCD_OPC_Decode, 250, 12, 3, // Opcode: VCMPGTSHo -/* 1657 */ MCD_OPC_FilterValue, 30, 4, 0, 0, // Skip to: 1666 -/* 1662 */ MCD_OPC_Decode, 252, 12, 3, // Opcode: VCMPGTSWo -/* 1666 */ MCD_OPC_FilterValue, 31, 171, 57, 0, // Skip to: 16434 -/* 1671 */ MCD_OPC_Decode, 230, 12, 3, // Opcode: VCMPBFPo -/* 1675 */ MCD_OPC_FilterValue, 7, 165, 0, 0, // Skip to: 1845 -/* 1680 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 1683 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1692 -/* 1688 */ MCD_OPC_Decode, 133, 13, 3, // Opcode: VCMPNEB -/* 1692 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1701 -/* 1697 */ MCD_OPC_Decode, 135, 13, 3, // Opcode: VCMPNEH -/* 1701 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1710 -/* 1706 */ MCD_OPC_Decode, 137, 13, 3, // Opcode: VCMPNEW -/* 1710 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1719 -/* 1715 */ MCD_OPC_Decode, 235, 12, 3, // Opcode: VCMPEQUD -/* 1719 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1728 -/* 1724 */ MCD_OPC_Decode, 139, 13, 3, // Opcode: VCMPNEZB -/* 1728 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1737 -/* 1733 */ MCD_OPC_Decode, 141, 13, 3, // Opcode: VCMPNEZH -/* 1737 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1746 -/* 1742 */ MCD_OPC_Decode, 143, 13, 3, // Opcode: VCMPNEZW -/* 1746 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 1755 -/* 1751 */ MCD_OPC_Decode, 255, 12, 3, // Opcode: VCMPGTUD -/* 1755 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 1764 -/* 1760 */ MCD_OPC_Decode, 247, 12, 3, // Opcode: VCMPGTSD -/* 1764 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1773 -/* 1769 */ MCD_OPC_Decode, 134, 13, 3, // Opcode: VCMPNEBo -/* 1773 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1782 -/* 1778 */ MCD_OPC_Decode, 136, 13, 3, // Opcode: VCMPNEHo -/* 1782 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1791 -/* 1787 */ MCD_OPC_Decode, 138, 13, 3, // Opcode: VCMPNEWo -/* 1791 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 1800 -/* 1796 */ MCD_OPC_Decode, 236, 12, 3, // Opcode: VCMPEQUDo -/* 1800 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 1809 -/* 1805 */ MCD_OPC_Decode, 140, 13, 3, // Opcode: VCMPNEZBo -/* 1809 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 1818 -/* 1814 */ MCD_OPC_Decode, 142, 13, 3, // Opcode: VCMPNEZHo -/* 1818 */ MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 1827 -/* 1823 */ MCD_OPC_Decode, 144, 13, 3, // Opcode: VCMPNEZWo -/* 1827 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 1836 -/* 1832 */ MCD_OPC_Decode, 128, 13, 3, // Opcode: VCMPGTUDo -/* 1836 */ MCD_OPC_FilterValue, 31, 1, 57, 0, // Skip to: 16434 -/* 1841 */ MCD_OPC_Decode, 248, 12, 3, // Opcode: VCMPGTSDo -/* 1845 */ MCD_OPC_FilterValue, 8, 226, 0, 0, // Skip to: 2076 -/* 1850 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 1853 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1862 -/* 1858 */ MCD_OPC_Decode, 231, 13, 3, // Opcode: VMULOUB -/* 1862 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1871 -/* 1867 */ MCD_OPC_Decode, 232, 13, 3, // Opcode: VMULOUH -/* 1871 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1880 -/* 1876 */ MCD_OPC_Decode, 233, 13, 3, // Opcode: VMULOUW -/* 1880 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1889 -/* 1885 */ MCD_OPC_Decode, 228, 13, 3, // Opcode: VMULOSB -/* 1889 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1898 -/* 1894 */ MCD_OPC_Decode, 229, 13, 3, // Opcode: VMULOSH -/* 1898 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1907 -/* 1903 */ MCD_OPC_Decode, 230, 13, 3, // Opcode: VMULOSW -/* 1907 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1916 -/* 1912 */ MCD_OPC_Decode, 225, 13, 3, // Opcode: VMULEUB -/* 1916 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1925 -/* 1921 */ MCD_OPC_Decode, 226, 13, 3, // Opcode: VMULEUH -/* 1925 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1934 -/* 1930 */ MCD_OPC_Decode, 227, 13, 3, // Opcode: VMULEUW -/* 1934 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 1943 -/* 1939 */ MCD_OPC_Decode, 222, 13, 3, // Opcode: VMULESB -/* 1943 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 1952 -/* 1948 */ MCD_OPC_Decode, 223, 13, 3, // Opcode: VMULESH -/* 1952 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 1961 -/* 1957 */ MCD_OPC_Decode, 224, 13, 3, // Opcode: VMULESW -/* 1961 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1970 -/* 1966 */ MCD_OPC_Decode, 132, 14, 3, // Opcode: VPMSUMB -/* 1970 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1979 -/* 1975 */ MCD_OPC_Decode, 134, 14, 3, // Opcode: VPMSUMH -/* 1979 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1988 -/* 1984 */ MCD_OPC_Decode, 135, 14, 3, // Opcode: VPMSUMW -/* 1988 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 1997 -/* 1993 */ MCD_OPC_Decode, 133, 14, 3, // Opcode: VPMSUMD -/* 1997 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 2006 -/* 2002 */ MCD_OPC_Decode, 222, 12, 3, // Opcode: VCIPHER -/* 2006 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 2015 -/* 2011 */ MCD_OPC_Decode, 236, 13, 3, // Opcode: VNCIPHER -/* 2015 */ MCD_OPC_FilterValue, 23, 11, 0, 0, // Skip to: 2031 -/* 2020 */ MCD_OPC_CheckField, 11, 5, 0, 71, 56, 0, // Skip to: 16434 -/* 2027 */ MCD_OPC_Decode, 157, 14, 4, // Opcode: VSBOX -/* 2031 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 2040 -/* 2036 */ MCD_OPC_Decode, 207, 14, 3, // Opcode: VSUM4UBS -/* 2040 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 2049 -/* 2045 */ MCD_OPC_Decode, 206, 14, 3, // Opcode: VSUM4SHS -/* 2049 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 2058 -/* 2054 */ MCD_OPC_Decode, 204, 14, 3, // Opcode: VSUM2SWS -/* 2058 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 2067 -/* 2063 */ MCD_OPC_Decode, 205, 14, 3, // Opcode: VSUM4SBS -/* 2067 */ MCD_OPC_FilterValue, 30, 26, 56, 0, // Skip to: 16434 -/* 2072 */ MCD_OPC_Decode, 208, 14, 3, // Opcode: VSUMSWS -/* 2076 */ MCD_OPC_FilterValue, 9, 30, 0, 0, // Skip to: 2111 -/* 2081 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 2084 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2093 -/* 2089 */ MCD_OPC_Decode, 234, 13, 3, // Opcode: VMULUWM -/* 2093 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 2102 -/* 2098 */ MCD_OPC_Decode, 223, 12, 3, // Opcode: VCIPHERLAST -/* 2102 */ MCD_OPC_FilterValue, 21, 247, 55, 0, // Skip to: 16434 -/* 2107 */ MCD_OPC_Decode, 237, 13, 3, // Opcode: VNCIPHERLAST -/* 2111 */ MCD_OPC_FilterValue, 10, 203, 0, 0, // Skip to: 2319 -/* 2116 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 2119 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2128 -/* 2124 */ MCD_OPC_Decode, 196, 12, 3, // Opcode: VADDFP -/* 2128 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2137 -/* 2133 */ MCD_OPC_Decode, 192, 14, 3, // Opcode: VSUBFP -/* 2137 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 2153 -/* 2142 */ MCD_OPC_CheckField, 16, 5, 0, 205, 55, 0, // Skip to: 16434 -/* 2149 */ MCD_OPC_Decode, 143, 14, 6, // Opcode: VREFP -/* 2153 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 2169 -/* 2158 */ MCD_OPC_CheckField, 16, 5, 0, 189, 55, 0, // Skip to: 16434 -/* 2165 */ MCD_OPC_Decode, 156, 14, 6, // Opcode: VRSQRTEFP -/* 2169 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 2185 -/* 2174 */ MCD_OPC_CheckField, 16, 5, 0, 173, 55, 0, // Skip to: 16434 -/* 2181 */ MCD_OPC_Decode, 155, 13, 6, // Opcode: VEXPTEFP -/* 2185 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 2201 -/* 2190 */ MCD_OPC_CheckField, 16, 5, 0, 157, 55, 0, // Skip to: 16434 -/* 2197 */ MCD_OPC_Decode, 181, 13, 6, // Opcode: VLOGEFP -/* 2201 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 2217 -/* 2206 */ MCD_OPC_CheckField, 16, 5, 0, 141, 55, 0, // Skip to: 16434 -/* 2213 */ MCD_OPC_Decode, 145, 14, 6, // Opcode: VRFIN -/* 2217 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 2233 -/* 2222 */ MCD_OPC_CheckField, 16, 5, 0, 125, 55, 0, // Skip to: 16434 -/* 2229 */ MCD_OPC_Decode, 147, 14, 6, // Opcode: VRFIZ -/* 2233 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 2249 -/* 2238 */ MCD_OPC_CheckField, 16, 5, 0, 109, 55, 0, // Skip to: 16434 -/* 2245 */ MCD_OPC_Decode, 146, 14, 6, // Opcode: VRFIP -/* 2249 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 2265 -/* 2254 */ MCD_OPC_CheckField, 16, 5, 0, 93, 55, 0, // Skip to: 16434 -/* 2261 */ MCD_OPC_Decode, 144, 14, 6, // Opcode: VRFIM -/* 2265 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 2274 -/* 2270 */ MCD_OPC_Decode, 220, 12, 13, // Opcode: VCFUX -/* 2274 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 2283 -/* 2279 */ MCD_OPC_Decode, 218, 12, 13, // Opcode: VCFSX -/* 2283 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 2292 -/* 2288 */ MCD_OPC_Decode, 147, 13, 13, // Opcode: VCTUXS -/* 2292 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 2301 -/* 2297 */ MCD_OPC_Decode, 145, 13, 13, // Opcode: VCTSXS -/* 2301 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 2310 -/* 2306 */ MCD_OPC_Decode, 183, 13, 3, // Opcode: VMAXFP -/* 2310 */ MCD_OPC_FilterValue, 17, 39, 55, 0, // Skip to: 16434 -/* 2315 */ MCD_OPC_Decode, 194, 13, 3, // Opcode: VMINFP -/* 2319 */ MCD_OPC_FilterValue, 12, 202, 0, 0, // Skip to: 2526 -/* 2324 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 2327 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2336 -/* 2332 */ MCD_OPC_Decode, 205, 13, 3, // Opcode: VMRGHB -/* 2336 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2345 -/* 2341 */ MCD_OPC_Decode, 206, 13, 3, // Opcode: VMRGHH -/* 2345 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2354 -/* 2350 */ MCD_OPC_Decode, 207, 13, 3, // Opcode: VMRGHW -/* 2354 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 2363 -/* 2359 */ MCD_OPC_Decode, 208, 13, 3, // Opcode: VMRGLB -/* 2363 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 2372 -/* 2368 */ MCD_OPC_Decode, 209, 13, 3, // Opcode: VMRGLH -/* 2372 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 2381 -/* 2377 */ MCD_OPC_Decode, 210, 13, 3, // Opcode: VMRGLW -/* 2381 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 2390 -/* 2386 */ MCD_OPC_Decode, 169, 14, 13, // Opcode: VSPLTB -/* 2390 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 2399 -/* 2395 */ MCD_OPC_Decode, 171, 14, 13, // Opcode: VSPLTH -/* 2399 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 2408 -/* 2404 */ MCD_OPC_Decode, 176, 14, 13, // Opcode: VSPLTW -/* 2408 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 2424 -/* 2413 */ MCD_OPC_CheckField, 11, 5, 0, 190, 54, 0, // Skip to: 16434 -/* 2420 */ MCD_OPC_Decode, 173, 14, 14, // Opcode: VSPLTISB -/* 2424 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 2440 -/* 2429 */ MCD_OPC_CheckField, 11, 5, 0, 174, 54, 0, // Skip to: 16434 -/* 2436 */ MCD_OPC_Decode, 174, 14, 14, // Opcode: VSPLTISH -/* 2440 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 2456 -/* 2445 */ MCD_OPC_CheckField, 11, 5, 0, 158, 54, 0, // Skip to: 16434 -/* 2452 */ MCD_OPC_Decode, 175, 14, 14, // Opcode: VSPLTISW -/* 2456 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 2465 -/* 2461 */ MCD_OPC_Decode, 166, 14, 3, // Opcode: VSLO -/* 2465 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 2474 -/* 2470 */ MCD_OPC_Decode, 185, 14, 3, // Opcode: VSRO -/* 2474 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 2490 -/* 2479 */ MCD_OPC_CheckField, 16, 5, 0, 124, 54, 0, // Skip to: 16434 -/* 2486 */ MCD_OPC_Decode, 176, 13, 6, // Opcode: VGBBD -/* 2490 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 2499 -/* 2495 */ MCD_OPC_Decode, 217, 12, 3, // Opcode: VBPERMQ -/* 2499 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 2508 -/* 2504 */ MCD_OPC_Decode, 216, 12, 3, // Opcode: VBPERMD -/* 2508 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 2517 -/* 2513 */ MCD_OPC_Decode, 211, 13, 3, // Opcode: VMRGOW -/* 2517 */ MCD_OPC_FilterValue, 30, 88, 54, 0, // Skip to: 16434 -/* 2522 */ MCD_OPC_Decode, 204, 13, 3, // Opcode: VMRGEW -/* 2526 */ MCD_OPC_FilterValue, 13, 129, 0, 0, // Skip to: 2660 -/* 2531 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 2534 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 2543 -/* 2539 */ MCD_OPC_Decode, 157, 13, 15, // Opcode: VEXTRACTUB -/* 2543 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 2552 -/* 2548 */ MCD_OPC_Decode, 158, 13, 15, // Opcode: VEXTRACTUH -/* 2552 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 2561 -/* 2557 */ MCD_OPC_Decode, 159, 13, 15, // Opcode: VEXTRACTUW -/* 2561 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 2570 -/* 2566 */ MCD_OPC_Decode, 156, 13, 15, // Opcode: VEXTRACTD -/* 2570 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 2579 -/* 2575 */ MCD_OPC_Decode, 177, 13, 16, // Opcode: VINSERTB -/* 2579 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 2588 -/* 2584 */ MCD_OPC_Decode, 179, 13, 16, // Opcode: VINSERTH -/* 2588 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 2597 -/* 2593 */ MCD_OPC_Decode, 180, 13, 15, // Opcode: VINSERTW -/* 2597 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 2606 -/* 2602 */ MCD_OPC_Decode, 178, 13, 15, // Opcode: VINSERTD -/* 2606 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 2615 -/* 2611 */ MCD_OPC_Decode, 170, 13, 17, // Opcode: VEXTUBLX -/* 2615 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 2624 -/* 2620 */ MCD_OPC_Decode, 172, 13, 17, // Opcode: VEXTUHLX -/* 2624 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 2633 -/* 2629 */ MCD_OPC_Decode, 174, 13, 17, // Opcode: VEXTUWLX -/* 2633 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 2642 -/* 2638 */ MCD_OPC_Decode, 171, 13, 17, // Opcode: VEXTUBRX -/* 2642 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 2651 -/* 2647 */ MCD_OPC_Decode, 173, 13, 17, // Opcode: VEXTUHRX -/* 2651 */ MCD_OPC_FilterValue, 30, 210, 53, 0, // Skip to: 16434 -/* 2656 */ MCD_OPC_Decode, 175, 13, 17, // Opcode: VEXTUWRX -/* 2660 */ MCD_OPC_FilterValue, 14, 248, 0, 0, // Skip to: 2913 -/* 2665 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 2668 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2677 -/* 2673 */ MCD_OPC_Decode, 128, 14, 3, // Opcode: VPKUHUM -/* 2677 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2686 -/* 2682 */ MCD_OPC_Decode, 130, 14, 3, // Opcode: VPKUWUM -/* 2686 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2695 -/* 2691 */ MCD_OPC_Decode, 129, 14, 3, // Opcode: VPKUHUS -/* 2695 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 2704 -/* 2700 */ MCD_OPC_Decode, 131, 14, 3, // Opcode: VPKUWUS -/* 2704 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 2713 -/* 2709 */ MCD_OPC_Decode, 251, 13, 3, // Opcode: VPKSHUS -/* 2713 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 2722 -/* 2718 */ MCD_OPC_Decode, 253, 13, 3, // Opcode: VPKSWUS -/* 2722 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 2731 -/* 2727 */ MCD_OPC_Decode, 250, 13, 3, // Opcode: VPKSHSS -/* 2731 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 2740 -/* 2736 */ MCD_OPC_Decode, 252, 13, 3, // Opcode: VPKSWSS -/* 2740 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 2756 -/* 2745 */ MCD_OPC_CheckField, 16, 5, 0, 114, 53, 0, // Skip to: 16434 -/* 2752 */ MCD_OPC_Decode, 210, 14, 6, // Opcode: VUPKHSB -/* 2756 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 2772 -/* 2761 */ MCD_OPC_CheckField, 16, 5, 0, 98, 53, 0, // Skip to: 16434 -/* 2768 */ MCD_OPC_Decode, 211, 14, 6, // Opcode: VUPKHSH -/* 2772 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 2788 -/* 2777 */ MCD_OPC_CheckField, 16, 5, 0, 82, 53, 0, // Skip to: 16434 -/* 2784 */ MCD_OPC_Decode, 214, 14, 6, // Opcode: VUPKLSB -/* 2788 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 2804 -/* 2793 */ MCD_OPC_CheckField, 16, 5, 0, 66, 53, 0, // Skip to: 16434 -/* 2800 */ MCD_OPC_Decode, 215, 14, 6, // Opcode: VUPKLSH -/* 2804 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 2813 -/* 2809 */ MCD_OPC_Decode, 247, 13, 3, // Opcode: VPKPX -/* 2813 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 2829 -/* 2818 */ MCD_OPC_CheckField, 16, 5, 0, 41, 53, 0, // Skip to: 16434 -/* 2825 */ MCD_OPC_Decode, 209, 14, 6, // Opcode: VUPKHPX -/* 2829 */ MCD_OPC_FilterValue, 15, 11, 0, 0, // Skip to: 2845 -/* 2834 */ MCD_OPC_CheckField, 16, 5, 0, 25, 53, 0, // Skip to: 16434 -/* 2841 */ MCD_OPC_Decode, 213, 14, 6, // Opcode: VUPKLPX -/* 2845 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 2854 -/* 2850 */ MCD_OPC_Decode, 254, 13, 3, // Opcode: VPKUDUM -/* 2854 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 2863 -/* 2859 */ MCD_OPC_Decode, 255, 13, 3, // Opcode: VPKUDUS -/* 2863 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 2872 -/* 2868 */ MCD_OPC_Decode, 249, 13, 3, // Opcode: VPKSDUS -/* 2872 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 2881 -/* 2877 */ MCD_OPC_Decode, 248, 13, 3, // Opcode: VPKSDSS -/* 2881 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 2897 -/* 2886 */ MCD_OPC_CheckField, 16, 5, 0, 229, 52, 0, // Skip to: 16434 -/* 2893 */ MCD_OPC_Decode, 212, 14, 6, // Opcode: VUPKHSW -/* 2897 */ MCD_OPC_FilterValue, 27, 220, 52, 0, // Skip to: 16434 -/* 2902 */ MCD_OPC_CheckField, 16, 5, 0, 213, 52, 0, // Skip to: 16434 -/* 2909 */ MCD_OPC_Decode, 216, 14, 6, // Opcode: VUPKLSW -/* 2913 */ MCD_OPC_FilterValue, 32, 4, 0, 0, // Skip to: 2922 -/* 2918 */ MCD_OPC_Decode, 192, 13, 18, // Opcode: VMHADDSHS -/* 2922 */ MCD_OPC_FilterValue, 33, 4, 0, 0, // Skip to: 2931 -/* 2927 */ MCD_OPC_Decode, 193, 13, 18, // Opcode: VMHRADDSHS -/* 2931 */ MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 2940 -/* 2936 */ MCD_OPC_Decode, 203, 13, 18, // Opcode: VMLADDUHM -/* 2940 */ MCD_OPC_FilterValue, 36, 4, 0, 0, // Skip to: 2949 -/* 2945 */ MCD_OPC_Decode, 215, 13, 18, // Opcode: VMSUMUBM -/* 2949 */ MCD_OPC_FilterValue, 37, 4, 0, 0, // Skip to: 2958 -/* 2954 */ MCD_OPC_Decode, 212, 13, 18, // Opcode: VMSUMMBM -/* 2958 */ MCD_OPC_FilterValue, 38, 4, 0, 0, // Skip to: 2967 -/* 2963 */ MCD_OPC_Decode, 216, 13, 18, // Opcode: VMSUMUHM -/* 2967 */ MCD_OPC_FilterValue, 39, 4, 0, 0, // Skip to: 2976 -/* 2972 */ MCD_OPC_Decode, 217, 13, 18, // Opcode: VMSUMUHS -/* 2976 */ MCD_OPC_FilterValue, 40, 4, 0, 0, // Skip to: 2985 -/* 2981 */ MCD_OPC_Decode, 213, 13, 18, // Opcode: VMSUMSHM -/* 2985 */ MCD_OPC_FilterValue, 41, 4, 0, 0, // Skip to: 2994 -/* 2990 */ MCD_OPC_Decode, 214, 13, 18, // Opcode: VMSUMSHS -/* 2994 */ MCD_OPC_FilterValue, 42, 4, 0, 0, // Skip to: 3003 -/* 2999 */ MCD_OPC_Decode, 158, 14, 18, // Opcode: VSEL -/* 3003 */ MCD_OPC_FilterValue, 43, 4, 0, 0, // Skip to: 3012 -/* 3008 */ MCD_OPC_Decode, 244, 13, 18, // Opcode: VPERM -/* 3012 */ MCD_OPC_FilterValue, 44, 11, 0, 0, // Skip to: 3028 -/* 3017 */ MCD_OPC_CheckField, 10, 1, 0, 98, 52, 0, // Skip to: 16434 -/* 3024 */ MCD_OPC_Decode, 164, 14, 19, // Opcode: VSLDOI -/* 3028 */ MCD_OPC_FilterValue, 45, 4, 0, 0, // Skip to: 3037 -/* 3033 */ MCD_OPC_Decode, 246, 13, 18, // Opcode: VPERMXOR -/* 3037 */ MCD_OPC_FilterValue, 46, 4, 0, 0, // Skip to: 3046 -/* 3042 */ MCD_OPC_Decode, 182, 13, 20, // Opcode: VMADDFP -/* 3046 */ MCD_OPC_FilterValue, 47, 4, 0, 0, // Skip to: 3055 -/* 3051 */ MCD_OPC_Decode, 240, 13, 20, // Opcode: VNMSUBFP -/* 3055 */ MCD_OPC_FilterValue, 48, 4, 0, 0, // Skip to: 3064 -/* 3060 */ MCD_OPC_Decode, 144, 8, 21, // Opcode: MADDHD -/* 3064 */ MCD_OPC_FilterValue, 49, 4, 0, 0, // Skip to: 3073 -/* 3069 */ MCD_OPC_Decode, 145, 8, 21, // Opcode: MADDHDU -/* 3073 */ MCD_OPC_FilterValue, 51, 4, 0, 0, // Skip to: 3082 -/* 3078 */ MCD_OPC_Decode, 146, 8, 21, // Opcode: MADDLD -/* 3082 */ MCD_OPC_FilterValue, 59, 4, 0, 0, // Skip to: 3091 -/* 3087 */ MCD_OPC_Decode, 245, 13, 18, // Opcode: VPERMR -/* 3091 */ MCD_OPC_FilterValue, 60, 4, 0, 0, // Skip to: 3100 -/* 3096 */ MCD_OPC_Decode, 195, 12, 18, // Opcode: VADDEUQM -/* 3100 */ MCD_OPC_FilterValue, 61, 4, 0, 0, // Skip to: 3109 -/* 3105 */ MCD_OPC_Decode, 194, 12, 18, // Opcode: VADDECUQ -/* 3109 */ MCD_OPC_FilterValue, 62, 4, 0, 0, // Skip to: 3118 -/* 3114 */ MCD_OPC_Decode, 191, 14, 18, // Opcode: VSUBEUQM -/* 3118 */ MCD_OPC_FilterValue, 63, 255, 51, 0, // Skip to: 16434 -/* 3123 */ MCD_OPC_Decode, 190, 14, 18, // Opcode: VSUBECUQ -/* 3127 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 3136 -/* 3132 */ MCD_OPC_Decode, 233, 8, 22, // Opcode: MULLI -/* 3136 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 3145 -/* 3141 */ MCD_OPC_Decode, 132, 12, 22, // Opcode: SUBFIC -/* 3145 */ MCD_OPC_FilterValue, 10, 21, 0, 0, // Skip to: 3171 -/* 3150 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 3153 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3162 -/* 3158 */ MCD_OPC_Decode, 173, 3, 23, // Opcode: CMPLWI -/* 3162 */ MCD_OPC_FilterValue, 1, 211, 51, 0, // Skip to: 16434 -/* 3167 */ MCD_OPC_Decode, 171, 3, 24, // Opcode: CMPLDI -/* 3171 */ MCD_OPC_FilterValue, 11, 21, 0, 0, // Skip to: 3197 -/* 3176 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 3179 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3188 -/* 3184 */ MCD_OPC_Decode, 177, 3, 25, // Opcode: CMPWI -/* 3188 */ MCD_OPC_FilterValue, 1, 185, 51, 0, // Skip to: 16434 -/* 3193 */ MCD_OPC_Decode, 168, 3, 26, // Opcode: CMPDI -/* 3197 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 3206 -/* 3202 */ MCD_OPC_Decode, 220, 1, 22, // Opcode: ADDIC -/* 3206 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 3215 -/* 3211 */ MCD_OPC_Decode, 222, 1, 22, // Opcode: ADDICo -/* 3215 */ MCD_OPC_FilterValue, 14, 15, 0, 0, // Skip to: 3235 -/* 3220 */ MCD_OPC_CheckField, 16, 5, 0, 4, 0, 0, // Skip to: 3231 -/* 3227 */ MCD_OPC_Decode, 217, 7, 27, // Opcode: LI -/* 3231 */ MCD_OPC_Decode, 218, 1, 28, // Opcode: ADDI -/* 3235 */ MCD_OPC_FilterValue, 15, 15, 0, 0, // Skip to: 3255 -/* 3240 */ MCD_OPC_CheckField, 16, 5, 0, 4, 0, 0, // Skip to: 3251 -/* 3247 */ MCD_OPC_Decode, 219, 7, 27, // Opcode: LIS -/* 3251 */ MCD_OPC_Decode, 223, 1, 28, // Opcode: ADDIS -/* 3255 */ MCD_OPC_FilterValue, 16, 35, 1, 0, // Skip to: 3551 -/* 3260 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 3263 */ MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 3335 -/* 3268 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 3271 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 3281 -/* 3277 */ MCD_OPC_Decode, 237, 2, 29, // Opcode: BDNZ -/* 3281 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 3291 -/* 3287 */ MCD_OPC_Decode, 129, 3, 29, // Opcode: BDZ -/* 3291 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 3301 -/* 3297 */ MCD_OPC_Decode, 255, 2, 29, // Opcode: BDNZm -/* 3301 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 3311 -/* 3307 */ MCD_OPC_Decode, 128, 3, 29, // Opcode: BDNZp -/* 3311 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 3321 -/* 3317 */ MCD_OPC_Decode, 147, 3, 29, // Opcode: BDZm -/* 3321 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 3331 -/* 3327 */ MCD_OPC_Decode, 148, 3, 29, // Opcode: BDZp -/* 3331 */ MCD_OPC_Decode, 223, 16, 30, // Opcode: gBC -/* 3335 */ MCD_OPC_FilterValue, 1, 67, 0, 0, // Skip to: 3407 -/* 3340 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 3343 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 3353 -/* 3349 */ MCD_OPC_Decode, 242, 2, 29, // Opcode: BDNZL -/* 3353 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 3363 -/* 3359 */ MCD_OPC_Decode, 134, 3, 29, // Opcode: BDZL -/* 3363 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 3373 -/* 3369 */ MCD_OPC_Decode, 253, 2, 29, // Opcode: BDNZLm -/* 3373 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 3383 -/* 3379 */ MCD_OPC_Decode, 254, 2, 29, // Opcode: BDNZLp -/* 3383 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 3393 -/* 3389 */ MCD_OPC_Decode, 145, 3, 29, // Opcode: BDZLm -/* 3393 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 3403 -/* 3399 */ MCD_OPC_Decode, 146, 3, 29, // Opcode: BDZLp -/* 3403 */ MCD_OPC_Decode, 228, 16, 30, // Opcode: gBCL -/* 3407 */ MCD_OPC_FilterValue, 2, 67, 0, 0, // Skip to: 3479 -/* 3412 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 3415 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 3425 -/* 3421 */ MCD_OPC_Decode, 239, 2, 29, // Opcode: BDNZA -/* 3425 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 3435 -/* 3431 */ MCD_OPC_Decode, 131, 3, 29, // Opcode: BDZA -/* 3435 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 3445 -/* 3441 */ MCD_OPC_Decode, 240, 2, 29, // Opcode: BDNZAm -/* 3445 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 3455 -/* 3451 */ MCD_OPC_Decode, 241, 2, 29, // Opcode: BDNZAp -/* 3455 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 3465 -/* 3461 */ MCD_OPC_Decode, 132, 3, 29, // Opcode: BDZAm -/* 3465 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 3475 -/* 3471 */ MCD_OPC_Decode, 133, 3, 29, // Opcode: BDZAp -/* 3475 */ MCD_OPC_Decode, 224, 16, 30, // Opcode: gBCA -/* 3479 */ MCD_OPC_FilterValue, 3, 150, 50, 0, // Skip to: 16434 -/* 3484 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 3487 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 3497 -/* 3493 */ MCD_OPC_Decode, 243, 2, 29, // Opcode: BDNZLA -/* 3497 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 3507 -/* 3503 */ MCD_OPC_Decode, 135, 3, 29, // Opcode: BDZLA -/* 3507 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 3517 -/* 3513 */ MCD_OPC_Decode, 244, 2, 29, // Opcode: BDNZLAm -/* 3517 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 3527 -/* 3523 */ MCD_OPC_Decode, 245, 2, 29, // Opcode: BDNZLAp -/* 3527 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 3537 -/* 3533 */ MCD_OPC_Decode, 136, 3, 29, // Opcode: BDZLAm -/* 3537 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 3547 -/* 3543 */ MCD_OPC_Decode, 137, 3, 29, // Opcode: BDZLAp -/* 3547 */ MCD_OPC_Decode, 229, 16, 30, // Opcode: gBCLA -/* 3551 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 3567 -/* 3556 */ MCD_OPC_CheckField, 1, 1, 1, 71, 50, 0, // Skip to: 16434 -/* 3563 */ MCD_OPC_Decode, 222, 10, 31, // Opcode: SC -/* 3567 */ MCD_OPC_FilterValue, 18, 39, 0, 0, // Skip to: 3611 -/* 3572 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 3575 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3584 -/* 3580 */ MCD_OPC_Decode, 190, 2, 32, // Opcode: B -/* 3584 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 3593 -/* 3589 */ MCD_OPC_Decode, 149, 3, 32, // Opcode: BL -/* 3593 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 3602 -/* 3598 */ MCD_OPC_Decode, 191, 2, 32, // Opcode: BA -/* 3602 */ MCD_OPC_FilterValue, 3, 27, 50, 0, // Skip to: 16434 -/* 3607 */ MCD_OPC_Decode, 155, 3, 32, // Opcode: BLA -/* 3611 */ MCD_OPC_FilterValue, 19, 22, 3, 0, // Skip to: 4406 -/* 3616 */ MCD_OPC_ExtractField, 1, 5, // Inst{5-1} ... -/* 3619 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 3649 -/* 3624 */ MCD_OPC_CheckField, 21, 2, 0, 3, 50, 0, // Skip to: 16434 -/* 3631 */ MCD_OPC_CheckField, 6, 12, 0, 252, 49, 0, // Skip to: 16434 -/* 3638 */ MCD_OPC_CheckField, 0, 1, 0, 245, 49, 0, // Skip to: 16434 -/* 3645 */ MCD_OPC_Decode, 148, 8, 33, // Opcode: MCRF -/* 3649 */ MCD_OPC_FilterValue, 1, 131, 0, 0, // Skip to: 3785 -/* 3654 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3657 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 3673 -/* 3662 */ MCD_OPC_CheckField, 0, 1, 0, 221, 49, 0, // Skip to: 16434 -/* 3669 */ MCD_OPC_Decode, 203, 3, 34, // Opcode: CRNOR -/* 3673 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 3689 -/* 3678 */ MCD_OPC_CheckField, 0, 1, 0, 205, 49, 0, // Skip to: 16434 -/* 3685 */ MCD_OPC_Decode, 200, 3, 34, // Opcode: CRANDC -/* 3689 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 3705 -/* 3694 */ MCD_OPC_CheckField, 0, 1, 0, 189, 49, 0, // Skip to: 16434 -/* 3701 */ MCD_OPC_Decode, 208, 3, 34, // Opcode: CRXOR -/* 3705 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 3721 -/* 3710 */ MCD_OPC_CheckField, 0, 1, 0, 173, 49, 0, // Skip to: 16434 -/* 3717 */ MCD_OPC_Decode, 202, 3, 34, // Opcode: CRNAND -/* 3721 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 3737 -/* 3726 */ MCD_OPC_CheckField, 0, 1, 0, 157, 49, 0, // Skip to: 16434 -/* 3733 */ MCD_OPC_Decode, 199, 3, 34, // Opcode: CRAND -/* 3737 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 3753 -/* 3742 */ MCD_OPC_CheckField, 0, 1, 0, 141, 49, 0, // Skip to: 16434 -/* 3749 */ MCD_OPC_Decode, 201, 3, 34, // Opcode: CREQV -/* 3753 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 3769 -/* 3758 */ MCD_OPC_CheckField, 0, 1, 0, 125, 49, 0, // Skip to: 16434 -/* 3765 */ MCD_OPC_Decode, 205, 3, 34, // Opcode: CRORC -/* 3769 */ MCD_OPC_FilterValue, 14, 116, 49, 0, // Skip to: 16434 -/* 3774 */ MCD_OPC_CheckField, 0, 1, 0, 109, 49, 0, // Skip to: 16434 -/* 3781 */ MCD_OPC_Decode, 204, 3, 34, // Opcode: CROR -/* 3785 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 3794 -/* 3790 */ MCD_OPC_Decode, 246, 1, 35, // Opcode: ADDPCIS -/* 3794 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 3817 -/* 3799 */ MCD_OPC_CheckField, 6, 20, 1, 84, 49, 0, // Skip to: 16434 -/* 3806 */ MCD_OPC_CheckField, 0, 1, 0, 77, 49, 0, // Skip to: 16434 -/* 3813 */ MCD_OPC_Decode, 192, 10, 0, // Opcode: RFMCI -/* 3817 */ MCD_OPC_FilterValue, 7, 18, 0, 0, // Skip to: 3840 -/* 3822 */ MCD_OPC_CheckField, 6, 20, 1, 61, 49, 0, // Skip to: 16434 -/* 3829 */ MCD_OPC_CheckField, 0, 1, 0, 54, 49, 0, // Skip to: 16434 -/* 3836 */ MCD_OPC_Decode, 188, 10, 0, // Opcode: RFDI -/* 3840 */ MCD_OPC_FilterValue, 16, 113, 1, 0, // Skip to: 4214 -/* 3845 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 3848 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 4031 -/* 3853 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 3856 */ MCD_OPC_FilterValue, 0, 134, 0, 0, // Skip to: 3995 -/* 3861 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3864 */ MCD_OPC_FilterValue, 0, 21, 49, 0, // Skip to: 16434 -/* 3869 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 3872 */ MCD_OPC_FilterValue, 128, 4, 11, 0, 0, // Skip to: 3889 -/* 3878 */ MCD_OPC_CheckField, 11, 2, 0, 106, 0, 0, // Skip to: 3991 -/* 3885 */ MCD_OPC_Decode, 246, 2, 0, // Opcode: BDNZLR -/* 3889 */ MCD_OPC_FilterValue, 192, 4, 11, 0, 0, // Skip to: 3906 -/* 3895 */ MCD_OPC_CheckField, 11, 2, 0, 89, 0, 0, // Skip to: 3991 -/* 3902 */ MCD_OPC_Decode, 138, 3, 0, // Opcode: BDZLR -/* 3906 */ MCD_OPC_FilterValue, 128, 5, 11, 0, 0, // Skip to: 3923 -/* 3912 */ MCD_OPC_CheckField, 11, 2, 0, 72, 0, 0, // Skip to: 3991 -/* 3919 */ MCD_OPC_Decode, 158, 3, 0, // Opcode: BLR -/* 3923 */ MCD_OPC_FilterValue, 128, 6, 11, 0, 0, // Skip to: 3940 -/* 3929 */ MCD_OPC_CheckField, 11, 2, 0, 55, 0, 0, // Skip to: 3991 -/* 3936 */ MCD_OPC_Decode, 251, 2, 0, // Opcode: BDNZLRm -/* 3940 */ MCD_OPC_FilterValue, 160, 6, 11, 0, 0, // Skip to: 3957 -/* 3946 */ MCD_OPC_CheckField, 11, 2, 0, 38, 0, 0, // Skip to: 3991 -/* 3953 */ MCD_OPC_Decode, 252, 2, 0, // Opcode: BDNZLRp -/* 3957 */ MCD_OPC_FilterValue, 192, 6, 11, 0, 0, // Skip to: 3974 -/* 3963 */ MCD_OPC_CheckField, 11, 2, 0, 21, 0, 0, // Skip to: 3991 -/* 3970 */ MCD_OPC_Decode, 143, 3, 0, // Opcode: BDZLRm -/* 3974 */ MCD_OPC_FilterValue, 224, 6, 11, 0, 0, // Skip to: 3991 -/* 3980 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 3991 -/* 3987 */ MCD_OPC_Decode, 144, 3, 0, // Opcode: BDZLRp -/* 3991 */ MCD_OPC_Decode, 231, 16, 36, // Opcode: gBCLR -/* 3995 */ MCD_OPC_FilterValue, 16, 146, 48, 0, // Skip to: 16434 -/* 4000 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 4003 */ MCD_OPC_FilterValue, 0, 138, 48, 0, // Skip to: 16434 -/* 4008 */ MCD_OPC_CheckField, 16, 10, 128, 5, 11, 0, 0, // Skip to: 4027 -/* 4016 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4027 -/* 4023 */ MCD_OPC_Decode, 231, 2, 0, // Opcode: BCTR -/* 4027 */ MCD_OPC_Decode, 226, 16, 36, // Opcode: gBCCTR -/* 4031 */ MCD_OPC_FilterValue, 1, 110, 48, 0, // Skip to: 16434 -/* 4036 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 4039 */ MCD_OPC_FilterValue, 0, 134, 0, 0, // Skip to: 4178 -/* 4044 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 4047 */ MCD_OPC_FilterValue, 0, 94, 48, 0, // Skip to: 16434 -/* 4052 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... -/* 4055 */ MCD_OPC_FilterValue, 128, 4, 11, 0, 0, // Skip to: 4072 -/* 4061 */ MCD_OPC_CheckField, 11, 2, 0, 106, 0, 0, // Skip to: 4174 -/* 4068 */ MCD_OPC_Decode, 248, 2, 0, // Opcode: BDNZLRL -/* 4072 */ MCD_OPC_FilterValue, 192, 4, 11, 0, 0, // Skip to: 4089 -/* 4078 */ MCD_OPC_CheckField, 11, 2, 0, 89, 0, 0, // Skip to: 4174 -/* 4085 */ MCD_OPC_Decode, 140, 3, 0, // Opcode: BDZLRL -/* 4089 */ MCD_OPC_FilterValue, 128, 5, 11, 0, 0, // Skip to: 4106 -/* 4095 */ MCD_OPC_CheckField, 11, 2, 0, 72, 0, 0, // Skip to: 4174 -/* 4102 */ MCD_OPC_Decode, 160, 3, 0, // Opcode: BLRL -/* 4106 */ MCD_OPC_FilterValue, 128, 6, 11, 0, 0, // Skip to: 4123 -/* 4112 */ MCD_OPC_CheckField, 11, 2, 0, 55, 0, 0, // Skip to: 4174 -/* 4119 */ MCD_OPC_Decode, 249, 2, 0, // Opcode: BDNZLRLm -/* 4123 */ MCD_OPC_FilterValue, 160, 6, 11, 0, 0, // Skip to: 4140 -/* 4129 */ MCD_OPC_CheckField, 11, 2, 0, 38, 0, 0, // Skip to: 4174 -/* 4136 */ MCD_OPC_Decode, 250, 2, 0, // Opcode: BDNZLRLp -/* 4140 */ MCD_OPC_FilterValue, 192, 6, 11, 0, 0, // Skip to: 4157 -/* 4146 */ MCD_OPC_CheckField, 11, 2, 0, 21, 0, 0, // Skip to: 4174 -/* 4153 */ MCD_OPC_Decode, 141, 3, 0, // Opcode: BDZLRLm -/* 4157 */ MCD_OPC_FilterValue, 224, 6, 11, 0, 0, // Skip to: 4174 -/* 4163 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4174 -/* 4170 */ MCD_OPC_Decode, 142, 3, 0, // Opcode: BDZLRLp -/* 4174 */ MCD_OPC_Decode, 232, 16, 36, // Opcode: gBCLRL -/* 4178 */ MCD_OPC_FilterValue, 16, 219, 47, 0, // Skip to: 16434 -/* 4183 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 4186 */ MCD_OPC_FilterValue, 0, 211, 47, 0, // Skip to: 16434 -/* 4191 */ MCD_OPC_CheckField, 16, 10, 128, 5, 11, 0, 0, // Skip to: 4210 -/* 4199 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4210 -/* 4206 */ MCD_OPC_Decode, 233, 2, 0, // Opcode: BCTRL -/* 4210 */ MCD_OPC_Decode, 227, 16, 36, // Opcode: gBCCTRL -/* 4214 */ MCD_OPC_FilterValue, 18, 141, 0, 0, // Skip to: 4360 -/* 4219 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 4222 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 4245 -/* 4227 */ MCD_OPC_CheckField, 11, 15, 0, 168, 47, 0, // Skip to: 16434 -/* 4234 */ MCD_OPC_CheckField, 0, 1, 0, 161, 47, 0, // Skip to: 16434 -/* 4241 */ MCD_OPC_Decode, 191, 10, 0, // Opcode: RFID -/* 4245 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 4268 -/* 4250 */ MCD_OPC_CheckField, 11, 15, 0, 145, 47, 0, // Skip to: 16434 -/* 4257 */ MCD_OPC_CheckField, 0, 1, 0, 138, 47, 0, // Skip to: 16434 -/* 4264 */ MCD_OPC_Decode, 190, 10, 0, // Opcode: RFI -/* 4268 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 4291 -/* 4273 */ MCD_OPC_CheckField, 12, 14, 0, 122, 47, 0, // Skip to: 16434 -/* 4280 */ MCD_OPC_CheckField, 0, 1, 0, 115, 47, 0, // Skip to: 16434 -/* 4287 */ MCD_OPC_Decode, 189, 10, 37, // Opcode: RFEBB -/* 4291 */ MCD_OPC_FilterValue, 8, 18, 0, 0, // Skip to: 4314 -/* 4296 */ MCD_OPC_CheckField, 11, 15, 0, 99, 47, 0, // Skip to: 16434 -/* 4303 */ MCD_OPC_CheckField, 0, 1, 0, 92, 47, 0, // Skip to: 16434 -/* 4310 */ MCD_OPC_Decode, 135, 7, 0, // Opcode: HRFID -/* 4314 */ MCD_OPC_FilterValue, 11, 18, 0, 0, // Skip to: 4337 -/* 4319 */ MCD_OPC_CheckField, 11, 15, 0, 76, 47, 0, // Skip to: 16434 -/* 4326 */ MCD_OPC_CheckField, 0, 1, 0, 69, 47, 0, // Skip to: 16434 -/* 4333 */ MCD_OPC_Decode, 209, 11, 0, // Opcode: STOP -/* 4337 */ MCD_OPC_FilterValue, 13, 60, 47, 0, // Skip to: 16434 -/* 4342 */ MCD_OPC_CheckField, 11, 15, 0, 53, 47, 0, // Skip to: 16434 -/* 4349 */ MCD_OPC_CheckField, 0, 1, 0, 46, 47, 0, // Skip to: 16434 -/* 4356 */ MCD_OPC_Decode, 244, 8, 0, // Opcode: NAP -/* 4360 */ MCD_OPC_FilterValue, 19, 18, 0, 0, // Skip to: 4383 -/* 4365 */ MCD_OPC_CheckField, 6, 20, 1, 30, 47, 0, // Skip to: 16434 -/* 4372 */ MCD_OPC_CheckField, 0, 1, 0, 23, 47, 0, // Skip to: 16434 -/* 4379 */ MCD_OPC_Decode, 187, 10, 0, // Opcode: RFCI -/* 4383 */ MCD_OPC_FilterValue, 22, 14, 47, 0, // Skip to: 16434 -/* 4388 */ MCD_OPC_CheckField, 6, 20, 4, 7, 47, 0, // Skip to: 16434 -/* 4395 */ MCD_OPC_CheckField, 0, 1, 0, 0, 47, 0, // Skip to: 16434 -/* 4402 */ MCD_OPC_Decode, 145, 7, 0, // Opcode: ISYNC -/* 4406 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 4432 -/* 4411 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 4414 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4423 -/* 4419 */ MCD_OPC_Decode, 209, 10, 38, // Opcode: RLWIMI -/* 4423 */ MCD_OPC_FilterValue, 1, 230, 46, 0, // Skip to: 16434 -/* 4428 */ MCD_OPC_Decode, 212, 10, 38, // Opcode: RLWIMIo -/* 4432 */ MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 4458 -/* 4437 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 4440 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4449 -/* 4445 */ MCD_OPC_Decode, 213, 10, 39, // Opcode: RLWINM -/* 4449 */ MCD_OPC_FilterValue, 1, 204, 46, 0, // Skip to: 16434 -/* 4454 */ MCD_OPC_Decode, 216, 10, 39, // Opcode: RLWINMo -/* 4458 */ MCD_OPC_FilterValue, 23, 21, 0, 0, // Skip to: 4484 -/* 4463 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 4466 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4475 -/* 4471 */ MCD_OPC_Decode, 217, 10, 40, // Opcode: RLWNM -/* 4475 */ MCD_OPC_FilterValue, 1, 178, 46, 0, // Skip to: 16434 -/* 4480 */ MCD_OPC_Decode, 220, 10, 40, // Opcode: RLWNMo -/* 4484 */ MCD_OPC_FilterValue, 24, 15, 0, 0, // Skip to: 4504 -/* 4489 */ MCD_OPC_CheckField, 0, 26, 0, 4, 0, 0, // Skip to: 4500 -/* 4496 */ MCD_OPC_Decode, 249, 8, 0, // Opcode: NOP -/* 4500 */ MCD_OPC_Decode, 135, 9, 41, // Opcode: ORI -/* 4504 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 4513 -/* 4509 */ MCD_OPC_Decode, 137, 9, 41, // Opcode: ORIS -/* 4513 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 4522 -/* 4518 */ MCD_OPC_Decode, 230, 14, 41, // Opcode: XORI -/* 4522 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 4531 -/* 4527 */ MCD_OPC_Decode, 232, 14, 41, // Opcode: XORIS -/* 4531 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 4540 -/* 4536 */ MCD_OPC_Decode, 134, 2, 41, // Opcode: ANDIo -/* 4540 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 4549 -/* 4545 */ MCD_OPC_Decode, 132, 2, 41, // Opcode: ANDISo -/* 4549 */ MCD_OPC_FilterValue, 30, 151, 0, 0, // Skip to: 4705 -/* 4554 */ MCD_OPC_ExtractField, 2, 3, // Inst{4-2} ... -/* 4557 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 4583 -/* 4562 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 4565 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4574 -/* 4570 */ MCD_OPC_Decode, 198, 10, 42, // Opcode: RLDICL -/* 4574 */ MCD_OPC_FilterValue, 1, 79, 46, 0, // Skip to: 16434 -/* 4579 */ MCD_OPC_Decode, 202, 10, 42, // Opcode: RLDICLo -/* 4583 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 4609 -/* 4588 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 4591 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4600 -/* 4596 */ MCD_OPC_Decode, 203, 10, 42, // Opcode: RLDICR -/* 4600 */ MCD_OPC_FilterValue, 1, 53, 46, 0, // Skip to: 16434 -/* 4605 */ MCD_OPC_Decode, 205, 10, 42, // Opcode: RLDICRo -/* 4609 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 4635 -/* 4614 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 4617 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4626 -/* 4622 */ MCD_OPC_Decode, 197, 10, 42, // Opcode: RLDIC -/* 4626 */ MCD_OPC_FilterValue, 1, 27, 46, 0, // Skip to: 16434 -/* 4631 */ MCD_OPC_Decode, 206, 10, 42, // Opcode: RLDICo -/* 4635 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 4661 -/* 4640 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 4643 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4652 -/* 4648 */ MCD_OPC_Decode, 207, 10, 43, // Opcode: RLDIMI -/* 4652 */ MCD_OPC_FilterValue, 1, 1, 46, 0, // Skip to: 16434 -/* 4657 */ MCD_OPC_Decode, 208, 10, 43, // Opcode: RLDIMIo -/* 4661 */ MCD_OPC_FilterValue, 4, 248, 45, 0, // Skip to: 16434 -/* 4666 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 4669 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4678 -/* 4674 */ MCD_OPC_Decode, 193, 10, 44, // Opcode: RLDCL -/* 4678 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4687 -/* 4683 */ MCD_OPC_Decode, 194, 10, 44, // Opcode: RLDCLo -/* 4687 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4696 -/* 4692 */ MCD_OPC_Decode, 195, 10, 44, // Opcode: RLDCR -/* 4696 */ MCD_OPC_FilterValue, 3, 213, 45, 0, // Skip to: 16434 -/* 4701 */ MCD_OPC_Decode, 196, 10, 44, // Opcode: RLDCRo -/* 4705 */ MCD_OPC_FilterValue, 31, 64, 21, 0, // Skip to: 10150 -/* 4710 */ MCD_OPC_ExtractField, 2, 4, // Inst{5-2} ... -/* 4713 */ MCD_OPC_FilterValue, 0, 175, 0, 0, // Skip to: 4893 -/* 4718 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 4721 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4761 -/* 4726 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 4729 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4745 -/* 4734 */ MCD_OPC_CheckField, 0, 2, 0, 173, 45, 0, // Skip to: 16434 -/* 4741 */ MCD_OPC_Decode, 176, 3, 45, // Opcode: CMPW -/* 4745 */ MCD_OPC_FilterValue, 1, 164, 45, 0, // Skip to: 16434 -/* 4750 */ MCD_OPC_CheckField, 0, 2, 0, 157, 45, 0, // Skip to: 16434 -/* 4757 */ MCD_OPC_Decode, 167, 3, 46, // Opcode: CMPD -/* 4761 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 4801 -/* 4766 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... -/* 4769 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4785 -/* 4774 */ MCD_OPC_CheckField, 0, 2, 0, 133, 45, 0, // Skip to: 16434 -/* 4781 */ MCD_OPC_Decode, 172, 3, 45, // Opcode: CMPLW -/* 4785 */ MCD_OPC_FilterValue, 1, 124, 45, 0, // Skip to: 16434 -/* 4790 */ MCD_OPC_CheckField, 0, 2, 0, 117, 45, 0, // Skip to: 16434 -/* 4797 */ MCD_OPC_Decode, 170, 3, 46, // Opcode: CMPLD -/* 4801 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 4824 -/* 4806 */ MCD_OPC_CheckField, 11, 7, 0, 101, 45, 0, // Skip to: 16434 -/* 4813 */ MCD_OPC_CheckField, 0, 2, 0, 94, 45, 0, // Skip to: 16434 -/* 4820 */ MCD_OPC_Decode, 251, 10, 47, // Opcode: SETB -/* 4824 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 4847 -/* 4829 */ MCD_OPC_CheckField, 22, 1, 0, 78, 45, 0, // Skip to: 16434 -/* 4836 */ MCD_OPC_CheckField, 0, 2, 0, 71, 45, 0, // Skip to: 16434 -/* 4843 */ MCD_OPC_Decode, 174, 3, 48, // Opcode: CMPRB -/* 4847 */ MCD_OPC_FilterValue, 7, 18, 0, 0, // Skip to: 4870 -/* 4852 */ MCD_OPC_CheckField, 21, 2, 0, 55, 45, 0, // Skip to: 16434 -/* 4859 */ MCD_OPC_CheckField, 0, 2, 0, 48, 45, 0, // Skip to: 16434 -/* 4866 */ MCD_OPC_Decode, 169, 3, 49, // Opcode: CMPEQB -/* 4870 */ MCD_OPC_FilterValue, 18, 39, 45, 0, // Skip to: 16434 -/* 4875 */ MCD_OPC_CheckField, 11, 12, 0, 32, 45, 0, // Skip to: 16434 -/* 4882 */ MCD_OPC_CheckField, 0, 2, 0, 25, 45, 0, // Skip to: 16434 -/* 4889 */ MCD_OPC_Decode, 150, 8, 50, // Opcode: MCRXRX -/* 4893 */ MCD_OPC_FilterValue, 1, 74, 0, 0, // Skip to: 4972 -/* 4898 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 4901 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 4924 -/* 4906 */ MCD_OPC_CheckField, 16, 1, 0, 1, 45, 0, // Skip to: 16434 -/* 4913 */ MCD_OPC_CheckField, 1, 1, 1, 250, 44, 0, // Skip to: 16434 -/* 4920 */ MCD_OPC_Decode, 225, 14, 51, // Opcode: WRTEE -/* 4924 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 4940 -/* 4929 */ MCD_OPC_CheckField, 1, 1, 1, 234, 44, 0, // Skip to: 16434 -/* 4936 */ MCD_OPC_Decode, 226, 14, 52, // Opcode: WRTEEI -/* 4940 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 4956 -/* 4945 */ MCD_OPC_CheckField, 0, 2, 2, 218, 44, 0, // Skip to: 16434 -/* 4952 */ MCD_OPC_Decode, 156, 8, 53, // Opcode: MFDCR -/* 4956 */ MCD_OPC_FilterValue, 14, 209, 44, 0, // Skip to: 16434 -/* 4961 */ MCD_OPC_CheckField, 0, 2, 2, 202, 44, 0, // Skip to: 16434 -/* 4968 */ MCD_OPC_Decode, 196, 8, 53, // Opcode: MTDCR -/* 4972 */ MCD_OPC_FilterValue, 2, 49, 0, 0, // Skip to: 5026 -/* 4977 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 4980 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 5010 -/* 4985 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 4988 */ MCD_OPC_FilterValue, 0, 177, 44, 0, // Skip to: 16434 -/* 4993 */ MCD_OPC_CheckField, 11, 15, 128, 248, 1, 4, 0, 0, // Skip to: 5006 -/* 5002 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: TRAP -/* 5006 */ MCD_OPC_Decode, 185, 12, 54, // Opcode: TW -/* 5010 */ MCD_OPC_FilterValue, 2, 155, 44, 0, // Skip to: 16434 -/* 5015 */ MCD_OPC_CheckField, 0, 2, 0, 148, 44, 0, // Skip to: 16434 -/* 5022 */ MCD_OPC_Decode, 164, 12, 55, // Opcode: TD -/* 5026 */ MCD_OPC_FilterValue, 3, 174, 1, 0, // Skip to: 5461 -/* 5031 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 5034 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 5060 -/* 5039 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5042 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5051 -/* 5047 */ MCD_OPC_Decode, 226, 7, 56, // Opcode: LVSL -/* 5051 */ MCD_OPC_FilterValue, 2, 114, 44, 0, // Skip to: 16434 -/* 5056 */ MCD_OPC_Decode, 223, 7, 56, // Opcode: LVEBX -/* 5060 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 5086 -/* 5065 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5068 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5077 -/* 5073 */ MCD_OPC_Decode, 227, 7, 56, // Opcode: LVSR -/* 5077 */ MCD_OPC_FilterValue, 2, 88, 44, 0, // Skip to: 16434 -/* 5082 */ MCD_OPC_Decode, 224, 7, 56, // Opcode: LVEHX -/* 5086 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 5102 -/* 5091 */ MCD_OPC_CheckField, 0, 2, 2, 72, 44, 0, // Skip to: 16434 -/* 5098 */ MCD_OPC_Decode, 225, 7, 56, // Opcode: LVEWX -/* 5102 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 5118 -/* 5107 */ MCD_OPC_CheckField, 0, 2, 2, 56, 44, 0, // Skip to: 16434 -/* 5114 */ MCD_OPC_Decode, 228, 7, 56, // Opcode: LVX -/* 5118 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 5134 -/* 5123 */ MCD_OPC_CheckField, 0, 2, 2, 40, 44, 0, // Skip to: 16434 -/* 5130 */ MCD_OPC_Decode, 211, 11, 56, // Opcode: STVEBX -/* 5134 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 5150 -/* 5139 */ MCD_OPC_CheckField, 0, 2, 2, 24, 44, 0, // Skip to: 16434 -/* 5146 */ MCD_OPC_Decode, 212, 11, 56, // Opcode: STVEHX -/* 5150 */ MCD_OPC_FilterValue, 6, 28, 0, 0, // Skip to: 5183 -/* 5155 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5158 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5174 -/* 5163 */ MCD_OPC_CheckField, 25, 1, 0, 0, 44, 0, // Skip to: 16434 -/* 5170 */ MCD_OPC_Decode, 139, 7, 57, // Opcode: ICBLQ -/* 5174 */ MCD_OPC_FilterValue, 2, 247, 43, 0, // Skip to: 16434 -/* 5179 */ MCD_OPC_Decode, 213, 11, 56, // Opcode: STVEWX -/* 5183 */ MCD_OPC_FilterValue, 7, 28, 0, 0, // Skip to: 5216 -/* 5188 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5191 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5207 -/* 5196 */ MCD_OPC_CheckField, 25, 1, 0, 223, 43, 0, // Skip to: 16434 -/* 5203 */ MCD_OPC_Decode, 138, 7, 57, // Opcode: ICBLC -/* 5207 */ MCD_OPC_FilterValue, 2, 214, 43, 0, // Skip to: 16434 -/* 5212 */ MCD_OPC_Decode, 214, 11, 56, // Opcode: STVX -/* 5216 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 5232 -/* 5221 */ MCD_OPC_CheckField, 0, 2, 2, 198, 43, 0, // Skip to: 16434 -/* 5228 */ MCD_OPC_Decode, 229, 7, 56, // Opcode: LVXL -/* 5232 */ MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 5255 -/* 5237 */ MCD_OPC_CheckField, 21, 5, 0, 182, 43, 0, // Skip to: 16434 -/* 5244 */ MCD_OPC_CheckField, 0, 2, 0, 175, 43, 0, // Skip to: 16434 -/* 5251 */ MCD_OPC_Decode, 225, 3, 58, // Opcode: DCCCI -/* 5255 */ MCD_OPC_FilterValue, 15, 28, 0, 0, // Skip to: 5288 -/* 5260 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5263 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5279 -/* 5268 */ MCD_OPC_CheckField, 25, 1, 0, 151, 43, 0, // Skip to: 16434 -/* 5275 */ MCD_OPC_Decode, 141, 7, 57, // Opcode: ICBTLS -/* 5279 */ MCD_OPC_FilterValue, 2, 142, 43, 0, // Skip to: 16434 -/* 5284 */ MCD_OPC_Decode, 215, 11, 56, // Opcode: STVXL -/* 5288 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 5304 -/* 5293 */ MCD_OPC_CheckField, 0, 2, 0, 126, 43, 0, // Skip to: 16434 -/* 5300 */ MCD_OPC_Decode, 233, 7, 59, // Opcode: LWAT -/* 5304 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 5320 -/* 5309 */ MCD_OPC_CheckField, 0, 2, 0, 110, 43, 0, // Skip to: 16434 -/* 5316 */ MCD_OPC_Decode, 165, 7, 60, // Opcode: LDAT -/* 5320 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 5336 -/* 5325 */ MCD_OPC_CheckField, 0, 2, 0, 94, 43, 0, // Skip to: 16434 -/* 5332 */ MCD_OPC_Decode, 218, 11, 59, // Opcode: STWAT -/* 5336 */ MCD_OPC_FilterValue, 23, 11, 0, 0, // Skip to: 5352 -/* 5341 */ MCD_OPC_CheckField, 0, 2, 0, 78, 43, 0, // Skip to: 16434 -/* 5348 */ MCD_OPC_Decode, 174, 11, 60, // Opcode: STDAT -/* 5352 */ MCD_OPC_FilterValue, 24, 18, 0, 0, // Skip to: 5375 -/* 5357 */ MCD_OPC_CheckField, 22, 4, 0, 62, 43, 0, // Skip to: 16434 -/* 5364 */ MCD_OPC_CheckField, 0, 2, 0, 55, 43, 0, // Skip to: 16434 -/* 5371 */ MCD_OPC_Decode, 191, 3, 61, // Opcode: CP_COPY -/* 5375 */ MCD_OPC_FilterValue, 26, 18, 0, 0, // Skip to: 5398 -/* 5380 */ MCD_OPC_CheckField, 11, 15, 0, 39, 43, 0, // Skip to: 16434 -/* 5387 */ MCD_OPC_CheckField, 0, 2, 0, 32, 43, 0, // Skip to: 16434 -/* 5394 */ MCD_OPC_Decode, 190, 3, 0, // Opcode: CP_ABORT -/* 5398 */ MCD_OPC_FilterValue, 28, 35, 0, 0, // Skip to: 5438 -/* 5403 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5406 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5422 -/* 5411 */ MCD_OPC_CheckField, 22, 4, 0, 8, 43, 0, // Skip to: 16434 -/* 5418 */ MCD_OPC_Decode, 193, 3, 61, // Opcode: CP_PASTE -/* 5422 */ MCD_OPC_FilterValue, 1, 255, 42, 0, // Skip to: 16434 -/* 5427 */ MCD_OPC_CheckField, 22, 4, 0, 248, 42, 0, // Skip to: 16434 -/* 5434 */ MCD_OPC_Decode, 196, 3, 61, // Opcode: CP_PASTEo -/* 5438 */ MCD_OPC_FilterValue, 30, 239, 42, 0, // Skip to: 16434 -/* 5443 */ MCD_OPC_CheckField, 21, 5, 0, 232, 42, 0, // Skip to: 16434 -/* 5450 */ MCD_OPC_CheckField, 0, 2, 0, 225, 42, 0, // Skip to: 16434 -/* 5457 */ MCD_OPC_Decode, 142, 7, 58, // Opcode: ICCCI -/* 5461 */ MCD_OPC_FilterValue, 4, 143, 1, 0, // Skip to: 5865 -/* 5466 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 5469 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 5513 -/* 5474 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5477 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5486 -/* 5482 */ MCD_OPC_Decode, 252, 11, 62, // Opcode: SUBFC -/* 5486 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 5495 -/* 5491 */ MCD_OPC_Decode, 255, 11, 62, // Opcode: SUBFCo -/* 5495 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5504 -/* 5500 */ MCD_OPC_Decode, 224, 8, 63, // Opcode: MULHDU -/* 5504 */ MCD_OPC_FilterValue, 3, 173, 42, 0, // Skip to: 16434 -/* 5509 */ MCD_OPC_Decode, 225, 8, 63, // Opcode: MULHDUo -/* 5513 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 5539 -/* 5518 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5521 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5530 -/* 5526 */ MCD_OPC_Decode, 249, 11, 62, // Opcode: SUBF -/* 5530 */ MCD_OPC_FilterValue, 1, 147, 42, 0, // Skip to: 16434 -/* 5535 */ MCD_OPC_Decode, 142, 12, 62, // Opcode: SUBFo -/* 5539 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 5565 -/* 5544 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5547 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5556 -/* 5552 */ MCD_OPC_Decode, 223, 8, 63, // Opcode: MULHD -/* 5556 */ MCD_OPC_FilterValue, 3, 121, 42, 0, // Skip to: 16434 -/* 5561 */ MCD_OPC_Decode, 226, 8, 63, // Opcode: MULHDo -/* 5565 */ MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 5605 -/* 5570 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5573 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5589 -/* 5578 */ MCD_OPC_CheckField, 11, 5, 0, 97, 42, 0, // Skip to: 16434 -/* 5585 */ MCD_OPC_Decode, 245, 8, 64, // Opcode: NEG -/* 5589 */ MCD_OPC_FilterValue, 1, 88, 42, 0, // Skip to: 16434 -/* 5594 */ MCD_OPC_CheckField, 11, 5, 0, 81, 42, 0, // Skip to: 16434 -/* 5601 */ MCD_OPC_Decode, 248, 8, 64, // Opcode: NEGo -/* 5605 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 5631 -/* 5610 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5613 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5622 -/* 5618 */ MCD_OPC_Decode, 128, 12, 62, // Opcode: SUBFE -/* 5622 */ MCD_OPC_FilterValue, 1, 55, 42, 0, // Skip to: 16434 -/* 5627 */ MCD_OPC_Decode, 131, 12, 62, // Opcode: SUBFEo -/* 5631 */ MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 5671 -/* 5636 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5639 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5655 -/* 5644 */ MCD_OPC_CheckField, 11, 5, 0, 31, 42, 0, // Skip to: 16434 -/* 5651 */ MCD_OPC_Decode, 138, 12, 64, // Opcode: SUBFZE -/* 5655 */ MCD_OPC_FilterValue, 1, 22, 42, 0, // Skip to: 16434 -/* 5660 */ MCD_OPC_CheckField, 11, 5, 0, 15, 42, 0, // Skip to: 16434 -/* 5667 */ MCD_OPC_Decode, 141, 12, 64, // Opcode: SUBFZEo -/* 5671 */ MCD_OPC_FilterValue, 7, 53, 0, 0, // Skip to: 5729 -/* 5676 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5679 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5695 -/* 5684 */ MCD_OPC_CheckField, 11, 5, 0, 247, 41, 0, // Skip to: 16434 -/* 5691 */ MCD_OPC_Decode, 134, 12, 64, // Opcode: SUBFME -/* 5695 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 5711 -/* 5700 */ MCD_OPC_CheckField, 11, 5, 0, 231, 41, 0, // Skip to: 16434 -/* 5707 */ MCD_OPC_Decode, 137, 12, 64, // Opcode: SUBFMEo -/* 5711 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5720 -/* 5716 */ MCD_OPC_Decode, 231, 8, 63, // Opcode: MULLD -/* 5720 */ MCD_OPC_FilterValue, 3, 213, 41, 0, // Skip to: 16434 -/* 5725 */ MCD_OPC_Decode, 232, 8, 63, // Opcode: MULLDo -/* 5729 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 5745 -/* 5734 */ MCD_OPC_CheckField, 0, 2, 2, 197, 41, 0, // Skip to: 16434 -/* 5741 */ MCD_OPC_Decode, 186, 8, 63, // Opcode: MODUD -/* 5745 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 5771 -/* 5750 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5753 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5762 -/* 5758 */ MCD_OPC_Decode, 228, 3, 63, // Opcode: DIVDEU -/* 5762 */ MCD_OPC_FilterValue, 3, 171, 41, 0, // Skip to: 16434 -/* 5767 */ MCD_OPC_Decode, 229, 3, 63, // Opcode: DIVDEUo -/* 5771 */ MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 5797 -/* 5776 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5779 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5788 -/* 5784 */ MCD_OPC_Decode, 227, 3, 63, // Opcode: DIVDE -/* 5788 */ MCD_OPC_FilterValue, 3, 145, 41, 0, // Skip to: 16434 -/* 5793 */ MCD_OPC_Decode, 230, 3, 63, // Opcode: DIVDEo -/* 5797 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 5823 -/* 5802 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5805 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5814 -/* 5810 */ MCD_OPC_Decode, 231, 3, 63, // Opcode: DIVDU -/* 5814 */ MCD_OPC_FilterValue, 3, 119, 41, 0, // Skip to: 16434 -/* 5819 */ MCD_OPC_Decode, 232, 3, 63, // Opcode: DIVDUo -/* 5823 */ MCD_OPC_FilterValue, 15, 21, 0, 0, // Skip to: 5849 -/* 5828 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5831 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5840 -/* 5836 */ MCD_OPC_Decode, 226, 3, 63, // Opcode: DIVD -/* 5840 */ MCD_OPC_FilterValue, 3, 93, 41, 0, // Skip to: 16434 -/* 5845 */ MCD_OPC_Decode, 233, 3, 63, // Opcode: DIVDo -/* 5849 */ MCD_OPC_FilterValue, 24, 84, 41, 0, // Skip to: 16434 -/* 5854 */ MCD_OPC_CheckField, 0, 2, 2, 77, 41, 0, // Skip to: 16434 -/* 5861 */ MCD_OPC_Decode, 184, 8, 63, // Opcode: MODSD -/* 5865 */ MCD_OPC_FilterValue, 5, 96, 1, 0, // Skip to: 6222 -/* 5870 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 5873 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 5917 -/* 5878 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5881 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5890 -/* 5886 */ MCD_OPC_Decode, 210, 1, 62, // Opcode: ADDC -/* 5890 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 5899 -/* 5895 */ MCD_OPC_Decode, 213, 1, 62, // Opcode: ADDCo -/* 5899 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5908 -/* 5904 */ MCD_OPC_Decode, 228, 8, 62, // Opcode: MULHWU -/* 5908 */ MCD_OPC_FilterValue, 3, 25, 41, 0, // Skip to: 16434 -/* 5913 */ MCD_OPC_Decode, 229, 8, 62, // Opcode: MULHWUo -/* 5917 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 5943 -/* 5922 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5925 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5934 -/* 5930 */ MCD_OPC_Decode, 227, 8, 62, // Opcode: MULHW -/* 5934 */ MCD_OPC_FilterValue, 3, 255, 40, 0, // Skip to: 16434 -/* 5939 */ MCD_OPC_Decode, 230, 8, 62, // Opcode: MULHWo -/* 5943 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 5969 -/* 5948 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5951 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5960 -/* 5956 */ MCD_OPC_Decode, 214, 1, 62, // Opcode: ADDE -/* 5960 */ MCD_OPC_FilterValue, 1, 229, 40, 0, // Skip to: 16434 -/* 5965 */ MCD_OPC_Decode, 217, 1, 62, // Opcode: ADDEo -/* 5969 */ MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 6009 -/* 5974 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 5977 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5993 -/* 5982 */ MCD_OPC_CheckField, 11, 5, 0, 205, 40, 0, // Skip to: 16434 -/* 5989 */ MCD_OPC_Decode, 247, 1, 64, // Opcode: ADDZE -/* 5993 */ MCD_OPC_FilterValue, 1, 196, 40, 0, // Skip to: 16434 -/* 5998 */ MCD_OPC_CheckField, 11, 5, 0, 189, 40, 0, // Skip to: 16434 -/* 6005 */ MCD_OPC_Decode, 250, 1, 64, // Opcode: ADDZEo -/* 6009 */ MCD_OPC_FilterValue, 7, 53, 0, 0, // Skip to: 6067 -/* 6014 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 6017 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 6033 -/* 6022 */ MCD_OPC_CheckField, 11, 5, 0, 165, 40, 0, // Skip to: 16434 -/* 6029 */ MCD_OPC_Decode, 242, 1, 64, // Opcode: ADDME -/* 6033 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 6049 -/* 6038 */ MCD_OPC_CheckField, 11, 5, 0, 149, 40, 0, // Skip to: 16434 -/* 6045 */ MCD_OPC_Decode, 245, 1, 64, // Opcode: ADDMEo -/* 6049 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6058 -/* 6054 */ MCD_OPC_Decode, 235, 8, 62, // Opcode: MULLW -/* 6058 */ MCD_OPC_FilterValue, 3, 131, 40, 0, // Skip to: 16434 -/* 6063 */ MCD_OPC_Decode, 236, 8, 62, // Opcode: MULLWo -/* 6067 */ MCD_OPC_FilterValue, 8, 30, 0, 0, // Skip to: 6102 -/* 6072 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 6075 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6084 -/* 6080 */ MCD_OPC_Decode, 203, 1, 62, // Opcode: ADD4 -/* 6084 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 6093 -/* 6089 */ MCD_OPC_Decode, 205, 1, 62, // Opcode: ADD4o -/* 6093 */ MCD_OPC_FilterValue, 2, 96, 40, 0, // Skip to: 16434 -/* 6098 */ MCD_OPC_Decode, 187, 8, 62, // Opcode: MODUW -/* 6102 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 6128 -/* 6107 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 6110 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6119 -/* 6115 */ MCD_OPC_Decode, 236, 3, 62, // Opcode: DIVWEU -/* 6119 */ MCD_OPC_FilterValue, 3, 70, 40, 0, // Skip to: 16434 -/* 6124 */ MCD_OPC_Decode, 237, 3, 62, // Opcode: DIVWEUo -/* 6128 */ MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 6154 -/* 6133 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 6136 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6145 -/* 6141 */ MCD_OPC_Decode, 235, 3, 62, // Opcode: DIVWE -/* 6145 */ MCD_OPC_FilterValue, 3, 44, 40, 0, // Skip to: 16434 -/* 6150 */ MCD_OPC_Decode, 238, 3, 62, // Opcode: DIVWEo -/* 6154 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 6180 -/* 6159 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 6162 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6171 -/* 6167 */ MCD_OPC_Decode, 239, 3, 62, // Opcode: DIVWU -/* 6171 */ MCD_OPC_FilterValue, 3, 18, 40, 0, // Skip to: 16434 -/* 6176 */ MCD_OPC_Decode, 240, 3, 62, // Opcode: DIVWUo -/* 6180 */ MCD_OPC_FilterValue, 15, 21, 0, 0, // Skip to: 6206 -/* 6185 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 6188 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6197 -/* 6193 */ MCD_OPC_Decode, 234, 3, 62, // Opcode: DIVW -/* 6197 */ MCD_OPC_FilterValue, 3, 248, 39, 0, // Skip to: 16434 -/* 6202 */ MCD_OPC_Decode, 241, 3, 62, // Opcode: DIVWo -/* 6206 */ MCD_OPC_FilterValue, 24, 239, 39, 0, // Skip to: 16434 -/* 6211 */ MCD_OPC_CheckField, 0, 2, 2, 232, 39, 0, // Skip to: 16434 -/* 6218 */ MCD_OPC_Decode, 185, 8, 62, // Opcode: MODSW -/* 6222 */ MCD_OPC_FilterValue, 6, 143, 1, 0, // Skip to: 6626 -/* 6227 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 6230 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 6246 -/* 6235 */ MCD_OPC_CheckField, 1, 1, 0, 208, 39, 0, // Skip to: 16434 -/* 6242 */ MCD_OPC_Decode, 131, 8, 65, // Opcode: LXSIWZX -/* 6246 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 6262 -/* 6251 */ MCD_OPC_CheckField, 1, 1, 0, 192, 39, 0, // Skip to: 16434 -/* 6258 */ MCD_OPC_Decode, 130, 8, 65, // Opcode: LXSIWAX -/* 6262 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 6278 -/* 6267 */ MCD_OPC_CheckField, 1, 1, 0, 176, 39, 0, // Skip to: 16434 -/* 6274 */ MCD_OPC_Decode, 238, 11, 65, // Opcode: STXSIWX -/* 6278 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 6304 -/* 6283 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 6286 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6295 -/* 6291 */ MCD_OPC_Decode, 143, 8, 66, // Opcode: LXVX -/* 6295 */ MCD_OPC_FilterValue, 1, 150, 39, 0, // Skip to: 16434 -/* 6300 */ MCD_OPC_Decode, 139, 8, 67, // Opcode: LXVL -/* 6304 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 6320 -/* 6309 */ MCD_OPC_CheckField, 1, 1, 1, 134, 39, 0, // Skip to: 16434 -/* 6316 */ MCD_OPC_Decode, 140, 8, 67, // Opcode: LXVLL -/* 6320 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 6336 -/* 6325 */ MCD_OPC_CheckField, 1, 1, 0, 118, 39, 0, // Skip to: 16434 -/* 6332 */ MCD_OPC_Decode, 137, 8, 66, // Opcode: LXVDSX -/* 6336 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 6352 -/* 6341 */ MCD_OPC_CheckField, 1, 1, 0, 102, 39, 0, // Skip to: 16434 -/* 6348 */ MCD_OPC_Decode, 142, 8, 66, // Opcode: LXVWSX -/* 6352 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 6378 -/* 6357 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 6360 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6369 -/* 6365 */ MCD_OPC_Decode, 248, 11, 66, // Opcode: STXVX -/* 6369 */ MCD_OPC_FilterValue, 1, 76, 39, 0, // Skip to: 16434 -/* 6374 */ MCD_OPC_Decode, 245, 11, 67, // Opcode: STXVL -/* 6378 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 6394 -/* 6383 */ MCD_OPC_CheckField, 1, 1, 1, 60, 39, 0, // Skip to: 16434 -/* 6390 */ MCD_OPC_Decode, 246, 11, 67, // Opcode: STXVLL -/* 6394 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 6410 -/* 6399 */ MCD_OPC_CheckField, 1, 1, 0, 44, 39, 0, // Skip to: 16434 -/* 6406 */ MCD_OPC_Decode, 133, 8, 68, // Opcode: LXSSPX -/* 6410 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 6426 -/* 6415 */ MCD_OPC_CheckField, 1, 1, 0, 28, 39, 0, // Skip to: 16434 -/* 6422 */ MCD_OPC_Decode, 255, 7, 65, // Opcode: LXSDX -/* 6426 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 6442 -/* 6431 */ MCD_OPC_CheckField, 1, 1, 0, 12, 39, 0, // Skip to: 16434 -/* 6438 */ MCD_OPC_Decode, 240, 11, 68, // Opcode: STXSSPX -/* 6442 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 6458 -/* 6447 */ MCD_OPC_CheckField, 1, 1, 0, 252, 38, 0, // Skip to: 16434 -/* 6454 */ MCD_OPC_Decode, 233, 11, 65, // Opcode: STXSDX -/* 6458 */ MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 6484 -/* 6463 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 6466 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6475 -/* 6471 */ MCD_OPC_Decode, 141, 8, 66, // Opcode: LXVW4X -/* 6475 */ MCD_OPC_FilterValue, 1, 226, 38, 0, // Skip to: 16434 -/* 6480 */ MCD_OPC_Decode, 128, 8, 65, // Opcode: LXSIBZX -/* 6484 */ MCD_OPC_FilterValue, 25, 21, 0, 0, // Skip to: 6510 -/* 6489 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 6492 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6501 -/* 6497 */ MCD_OPC_Decode, 138, 8, 66, // Opcode: LXVH8X -/* 6501 */ MCD_OPC_FilterValue, 1, 200, 38, 0, // Skip to: 16434 -/* 6506 */ MCD_OPC_Decode, 129, 8, 65, // Opcode: LXSIHZX -/* 6510 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 6526 -/* 6515 */ MCD_OPC_CheckField, 1, 1, 0, 184, 38, 0, // Skip to: 16434 -/* 6522 */ MCD_OPC_Decode, 136, 8, 66, // Opcode: LXVD2X -/* 6526 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 6542 -/* 6531 */ MCD_OPC_CheckField, 1, 1, 0, 168, 38, 0, // Skip to: 16434 -/* 6538 */ MCD_OPC_Decode, 135, 8, 66, // Opcode: LXVB16X -/* 6542 */ MCD_OPC_FilterValue, 28, 21, 0, 0, // Skip to: 6568 -/* 6547 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 6550 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6559 -/* 6555 */ MCD_OPC_Decode, 247, 11, 66, // Opcode: STXVW4X -/* 6559 */ MCD_OPC_FilterValue, 1, 142, 38, 0, // Skip to: 16434 -/* 6564 */ MCD_OPC_Decode, 234, 11, 65, // Opcode: STXSIBX -/* 6568 */ MCD_OPC_FilterValue, 29, 21, 0, 0, // Skip to: 6594 -/* 6573 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 6576 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6585 -/* 6581 */ MCD_OPC_Decode, 244, 11, 66, // Opcode: STXVH8X -/* 6585 */ MCD_OPC_FilterValue, 1, 116, 38, 0, // Skip to: 16434 -/* 6590 */ MCD_OPC_Decode, 236, 11, 65, // Opcode: STXSIHX -/* 6594 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 6610 -/* 6599 */ MCD_OPC_CheckField, 1, 1, 0, 100, 38, 0, // Skip to: 16434 -/* 6606 */ MCD_OPC_Decode, 243, 11, 66, // Opcode: STXVD2X -/* 6610 */ MCD_OPC_FilterValue, 31, 91, 38, 0, // Skip to: 16434 -/* 6615 */ MCD_OPC_CheckField, 1, 1, 0, 84, 38, 0, // Skip to: 16434 -/* 6622 */ MCD_OPC_Decode, 242, 11, 66, // Opcode: STXVB16X -/* 6626 */ MCD_OPC_FilterValue, 7, 247, 0, 0, // Skip to: 6878 -/* 6631 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 6634 */ MCD_OPC_FilterValue, 0, 62, 0, 0, // Skip to: 6701 -/* 6639 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 6642 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 6651 -/* 6647 */ MCD_OPC_Decode, 151, 8, 69, // Opcode: MFBHRBE -/* 6651 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 6660 -/* 6656 */ MCD_OPC_Decode, 170, 8, 53, // Opcode: MFPMR -/* 6660 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 6676 -/* 6665 */ MCD_OPC_CheckField, 11, 15, 0, 34, 38, 0, // Skip to: 16434 -/* 6672 */ MCD_OPC_Decode, 164, 3, 0, // Opcode: CLRBHRB -/* 6676 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 6685 -/* 6681 */ MCD_OPC_Decode, 210, 8, 70, // Opcode: MTPMR -/* 6685 */ MCD_OPC_FilterValue, 22, 16, 38, 0, // Skip to: 16434 -/* 6690 */ MCD_OPC_CheckField, 11, 12, 0, 9, 38, 0, // Skip to: 16434 -/* 6697 */ MCD_OPC_Decode, 156, 12, 50, // Opcode: TCHECK -/* 6701 */ MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 6869 -/* 6706 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 6709 */ MCD_OPC_FilterValue, 20, 18, 0, 0, // Skip to: 6732 -/* 6714 */ MCD_OPC_CheckField, 22, 4, 0, 241, 37, 0, // Skip to: 16434 -/* 6721 */ MCD_OPC_CheckField, 11, 10, 0, 234, 37, 0, // Skip to: 16434 -/* 6728 */ MCD_OPC_Decode, 155, 12, 71, // Opcode: TBEGIN -/* 6732 */ MCD_OPC_FilterValue, 21, 11, 0, 0, // Skip to: 6748 -/* 6737 */ MCD_OPC_CheckField, 11, 14, 0, 218, 37, 0, // Skip to: 16434 -/* 6744 */ MCD_OPC_Decode, 166, 12, 72, // Opcode: TEND -/* 6748 */ MCD_OPC_FilterValue, 23, 18, 0, 0, // Skip to: 6771 -/* 6753 */ MCD_OPC_CheckField, 22, 3, 0, 202, 37, 0, // Skip to: 16434 -/* 6760 */ MCD_OPC_CheckField, 11, 10, 0, 195, 37, 0, // Skip to: 16434 -/* 6767 */ MCD_OPC_Decode, 184, 12, 71, // Opcode: TSR -/* 6771 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 6780 -/* 6776 */ MCD_OPC_Decode, 147, 12, 73, // Opcode: TABORTWC -/* 6780 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 6789 -/* 6785 */ MCD_OPC_Decode, 145, 12, 73, // Opcode: TABORTDC -/* 6789 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 6798 -/* 6794 */ MCD_OPC_Decode, 148, 12, 74, // Opcode: TABORTWCI -/* 6798 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 6807 -/* 6803 */ MCD_OPC_Decode, 146, 12, 74, // Opcode: TABORTDCI -/* 6807 */ MCD_OPC_FilterValue, 28, 18, 0, 0, // Skip to: 6830 -/* 6812 */ MCD_OPC_CheckField, 21, 5, 0, 143, 37, 0, // Skip to: 16434 -/* 6819 */ MCD_OPC_CheckField, 11, 5, 0, 136, 37, 0, // Skip to: 16434 -/* 6826 */ MCD_OPC_Decode, 144, 12, 75, // Opcode: TABORT -/* 6830 */ MCD_OPC_FilterValue, 29, 18, 0, 0, // Skip to: 6853 -/* 6835 */ MCD_OPC_CheckField, 21, 5, 0, 120, 37, 0, // Skip to: 16434 -/* 6842 */ MCD_OPC_CheckField, 11, 5, 0, 113, 37, 0, // Skip to: 16434 -/* 6849 */ MCD_OPC_Decode, 183, 12, 75, // Opcode: TRECLAIM -/* 6853 */ MCD_OPC_FilterValue, 31, 104, 37, 0, // Skip to: 16434 -/* 6858 */ MCD_OPC_CheckField, 11, 15, 0, 97, 37, 0, // Skip to: 16434 -/* 6865 */ MCD_OPC_Decode, 182, 12, 0, // Opcode: TRECHKPT -/* 6869 */ MCD_OPC_FilterValue, 2, 88, 37, 0, // Skip to: 16434 -/* 6874 */ MCD_OPC_Decode, 143, 7, 76, // Opcode: ISEL -/* 6878 */ MCD_OPC_FilterValue, 8, 49, 0, 0, // Skip to: 6932 -/* 6883 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6886 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 6909 -/* 6891 */ MCD_OPC_CheckField, 6, 6, 4, 64, 37, 0, // Skip to: 16434 -/* 6898 */ MCD_OPC_CheckField, 0, 2, 0, 57, 37, 0, // Skip to: 16434 -/* 6905 */ MCD_OPC_Decode, 190, 8, 77, // Opcode: MTCRF -/* 6909 */ MCD_OPC_FilterValue, 1, 48, 37, 0, // Skip to: 16434 -/* 6914 */ MCD_OPC_CheckField, 6, 6, 4, 41, 37, 0, // Skip to: 16434 -/* 6921 */ MCD_OPC_CheckField, 0, 2, 0, 34, 37, 0, // Skip to: 16434 -/* 6928 */ MCD_OPC_Decode, 208, 8, 78, // Opcode: MTOCRF -/* 6932 */ MCD_OPC_FilterValue, 9, 49, 3, 0, // Skip to: 7754 -/* 6937 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 6940 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6994 -/* 6945 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 6948 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 6971 -/* 6953 */ MCD_OPC_CheckField, 11, 9, 0, 2, 37, 0, // Skip to: 16434 -/* 6960 */ MCD_OPC_CheckField, 0, 2, 2, 251, 36, 0, // Skip to: 16434 -/* 6967 */ MCD_OPC_Decode, 152, 8, 51, // Opcode: MFCR -/* 6971 */ MCD_OPC_FilterValue, 1, 242, 36, 0, // Skip to: 16434 -/* 6976 */ MCD_OPC_CheckField, 11, 1, 0, 235, 36, 0, // Skip to: 16434 -/* 6983 */ MCD_OPC_CheckField, 0, 2, 2, 228, 36, 0, // Skip to: 16434 -/* 6990 */ MCD_OPC_Decode, 168, 8, 79, // Opcode: MFOCRF -/* 6994 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 7017 -/* 6999 */ MCD_OPC_CheckField, 11, 5, 0, 212, 36, 0, // Skip to: 16434 -/* 7006 */ MCD_OPC_CheckField, 1, 1, 1, 205, 36, 0, // Skip to: 16434 -/* 7013 */ MCD_OPC_Decode, 181, 8, 80, // Opcode: MFVSRD -/* 7017 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 7040 -/* 7022 */ MCD_OPC_CheckField, 11, 10, 0, 189, 36, 0, // Skip to: 16434 -/* 7029 */ MCD_OPC_CheckField, 0, 2, 2, 182, 36, 0, // Skip to: 16434 -/* 7036 */ MCD_OPC_Decode, 167, 8, 51, // Opcode: MFMSR -/* 7040 */ MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 7063 -/* 7045 */ MCD_OPC_CheckField, 11, 5, 0, 166, 36, 0, // Skip to: 16434 -/* 7052 */ MCD_OPC_CheckField, 1, 1, 1, 159, 36, 0, // Skip to: 16434 -/* 7059 */ MCD_OPC_Decode, 183, 8, 81, // Opcode: MFVSRWZ -/* 7063 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 7079 -/* 7068 */ MCD_OPC_CheckField, 1, 1, 0, 143, 36, 0, // Skip to: 16434 -/* 7075 */ MCD_OPC_Decode, 206, 8, 82, // Opcode: MTMSR -/* 7079 */ MCD_OPC_FilterValue, 5, 28, 0, 0, // Skip to: 7112 -/* 7084 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 7087 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7096 -/* 7092 */ MCD_OPC_Decode, 207, 8, 82, // Opcode: MTMSRD -/* 7096 */ MCD_OPC_FilterValue, 1, 117, 36, 0, // Skip to: 16434 -/* 7101 */ MCD_OPC_CheckField, 11, 5, 0, 110, 36, 0, // Skip to: 16434 -/* 7108 */ MCD_OPC_Decode, 218, 8, 83, // Opcode: MTVSRD -/* 7112 */ MCD_OPC_FilterValue, 6, 28, 0, 0, // Skip to: 7145 -/* 7117 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 7120 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7129 -/* 7125 */ MCD_OPC_Decode, 213, 8, 84, // Opcode: MTSR -/* 7129 */ MCD_OPC_FilterValue, 1, 84, 36, 0, // Skip to: 16434 -/* 7134 */ MCD_OPC_CheckField, 11, 5, 0, 77, 36, 0, // Skip to: 16434 -/* 7141 */ MCD_OPC_Decode, 220, 8, 85, // Opcode: MTVSRWA -/* 7145 */ MCD_OPC_FilterValue, 7, 28, 0, 0, // Skip to: 7178 -/* 7150 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 7153 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7162 -/* 7158 */ MCD_OPC_Decode, 214, 8, 86, // Opcode: MTSRIN -/* 7162 */ MCD_OPC_FilterValue, 1, 51, 36, 0, // Skip to: 16434 -/* 7167 */ MCD_OPC_CheckField, 11, 5, 0, 44, 36, 0, // Skip to: 16434 -/* 7174 */ MCD_OPC_Decode, 222, 8, 85, // Opcode: MTVSRWZ -/* 7178 */ MCD_OPC_FilterValue, 8, 18, 0, 0, // Skip to: 7201 -/* 7183 */ MCD_OPC_CheckField, 16, 10, 0, 28, 36, 0, // Skip to: 16434 -/* 7190 */ MCD_OPC_CheckField, 0, 2, 0, 21, 36, 0, // Skip to: 16434 -/* 7197 */ MCD_OPC_Decode, 169, 12, 87, // Opcode: TLBIEL -/* 7201 */ MCD_OPC_FilterValue, 9, 42, 0, 0, // Skip to: 7248 -/* 7206 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 7209 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 7232 -/* 7214 */ MCD_OPC_CheckField, 16, 5, 0, 253, 35, 0, // Skip to: 16434 -/* 7221 */ MCD_OPC_CheckField, 0, 1, 0, 246, 35, 0, // Skip to: 16434 -/* 7228 */ MCD_OPC_Decode, 168, 12, 86, // Opcode: TLBIE -/* 7232 */ MCD_OPC_FilterValue, 1, 237, 35, 0, // Skip to: 16434 -/* 7237 */ MCD_OPC_CheckField, 11, 5, 0, 230, 35, 0, // Skip to: 16434 -/* 7244 */ MCD_OPC_Decode, 182, 8, 88, // Opcode: MFVSRLD -/* 7248 */ MCD_OPC_FilterValue, 10, 51, 0, 0, // Skip to: 7304 -/* 7253 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7256 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 7272 -/* 7261 */ MCD_OPC_CheckField, 11, 15, 0, 206, 35, 0, // Skip to: 16434 -/* 7268 */ MCD_OPC_Decode, 130, 11, 0, // Opcode: SLBSYNC -/* 7272 */ MCD_OPC_FilterValue, 2, 197, 35, 0, // Skip to: 16434 -/* 7277 */ MCD_OPC_ExtractField, 11, 10, // Inst{20-11} ... -/* 7280 */ MCD_OPC_FilterValue, 128, 2, 4, 0, 0, // Skip to: 7290 -/* 7286 */ MCD_OPC_Decode, 165, 8, 51, // Opcode: MFLR -/* 7290 */ MCD_OPC_FilterValue, 160, 2, 4, 0, 0, // Skip to: 7300 -/* 7296 */ MCD_OPC_Decode, 154, 8, 51, // Opcode: MFCTR -/* 7300 */ MCD_OPC_Decode, 171, 8, 53, // Opcode: MFSPR -/* 7304 */ MCD_OPC_FilterValue, 11, 28, 0, 0, // Skip to: 7337 -/* 7309 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7312 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 7328 -/* 7317 */ MCD_OPC_CheckField, 11, 15, 0, 150, 35, 0, // Skip to: 16434 -/* 7324 */ MCD_OPC_Decode, 167, 12, 0, // Opcode: TLBIA -/* 7328 */ MCD_OPC_FilterValue, 2, 141, 35, 0, // Skip to: 16434 -/* 7333 */ MCD_OPC_Decode, 175, 8, 53, // Opcode: MFTB -/* 7337 */ MCD_OPC_FilterValue, 12, 42, 0, 0, // Skip to: 7384 -/* 7342 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 7345 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 7368 -/* 7350 */ MCD_OPC_CheckField, 16, 5, 0, 117, 35, 0, // Skip to: 16434 -/* 7357 */ MCD_OPC_CheckField, 0, 1, 0, 110, 35, 0, // Skip to: 16434 -/* 7364 */ MCD_OPC_Decode, 129, 11, 86, // Opcode: SLBMTE -/* 7368 */ MCD_OPC_FilterValue, 1, 101, 35, 0, // Skip to: 16434 -/* 7373 */ MCD_OPC_CheckField, 11, 5, 0, 94, 35, 0, // Skip to: 16434 -/* 7380 */ MCD_OPC_Decode, 221, 8, 89, // Opcode: MTVSRWS -/* 7384 */ MCD_OPC_FilterValue, 13, 35, 0, 0, // Skip to: 7424 -/* 7389 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 7392 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 7415 -/* 7397 */ MCD_OPC_CheckField, 16, 10, 0, 70, 35, 0, // Skip to: 16434 -/* 7404 */ MCD_OPC_CheckField, 0, 1, 0, 63, 35, 0, // Skip to: 16434 -/* 7411 */ MCD_OPC_Decode, 253, 10, 87, // Opcode: SLBIE -/* 7415 */ MCD_OPC_FilterValue, 1, 54, 35, 0, // Skip to: 16434 -/* 7420 */ MCD_OPC_Decode, 219, 8, 90, // Opcode: MTVSRDD -/* 7424 */ MCD_OPC_FilterValue, 14, 51, 0, 0, // Skip to: 7480 -/* 7429 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7432 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 7448 -/* 7437 */ MCD_OPC_CheckField, 16, 5, 0, 30, 35, 0, // Skip to: 16434 -/* 7444 */ MCD_OPC_Decode, 254, 10, 86, // Opcode: SLBIEG -/* 7448 */ MCD_OPC_FilterValue, 2, 21, 35, 0, // Skip to: 16434 -/* 7453 */ MCD_OPC_ExtractField, 11, 10, // Inst{20-11} ... -/* 7456 */ MCD_OPC_FilterValue, 128, 2, 4, 0, 0, // Skip to: 7466 -/* 7462 */ MCD_OPC_Decode, 204, 8, 51, // Opcode: MTLR -/* 7466 */ MCD_OPC_FilterValue, 160, 2, 4, 0, 0, // Skip to: 7476 -/* 7472 */ MCD_OPC_Decode, 192, 8, 51, // Opcode: MTCTR -/* 7476 */ MCD_OPC_Decode, 211, 8, 70, // Opcode: MTSPR -/* 7480 */ MCD_OPC_FilterValue, 15, 18, 0, 0, // Skip to: 7503 -/* 7485 */ MCD_OPC_CheckField, 11, 15, 0, 238, 34, 0, // Skip to: 16434 -/* 7492 */ MCD_OPC_CheckField, 0, 2, 0, 231, 34, 0, // Skip to: 16434 -/* 7499 */ MCD_OPC_Decode, 252, 10, 0, // Opcode: SLBIA -/* 7503 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 7519 -/* 7508 */ MCD_OPC_CheckField, 1, 1, 1, 215, 34, 0, // Skip to: 16434 -/* 7515 */ MCD_OPC_Decode, 173, 8, 84, // Opcode: MFSR -/* 7519 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 7535 -/* 7524 */ MCD_OPC_CheckField, 1, 1, 1, 199, 34, 0, // Skip to: 16434 -/* 7531 */ MCD_OPC_Decode, 174, 8, 86, // Opcode: MFSRIN -/* 7535 */ MCD_OPC_FilterValue, 23, 25, 0, 0, // Skip to: 7565 -/* 7540 */ MCD_OPC_CheckField, 18, 3, 0, 183, 34, 0, // Skip to: 16434 -/* 7547 */ MCD_OPC_CheckField, 11, 5, 0, 176, 34, 0, // Skip to: 16434 -/* 7554 */ MCD_OPC_CheckField, 0, 2, 2, 169, 34, 0, // Skip to: 16434 -/* 7561 */ MCD_OPC_Decode, 210, 3, 91, // Opcode: DARN -/* 7565 */ MCD_OPC_FilterValue, 24, 18, 0, 0, // Skip to: 7588 -/* 7570 */ MCD_OPC_CheckField, 21, 5, 0, 153, 34, 0, // Skip to: 16434 -/* 7577 */ MCD_OPC_CheckField, 0, 2, 0, 146, 34, 0, // Skip to: 16434 -/* 7584 */ MCD_OPC_Decode, 170, 12, 58, // Opcode: TLBIVAX -/* 7588 */ MCD_OPC_FilterValue, 26, 18, 0, 0, // Skip to: 7611 -/* 7593 */ MCD_OPC_CheckField, 16, 5, 0, 130, 34, 0, // Skip to: 16434 -/* 7600 */ MCD_OPC_CheckField, 0, 2, 2, 123, 34, 0, // Skip to: 16434 -/* 7607 */ MCD_OPC_Decode, 128, 11, 86, // Opcode: SLBMFEV -/* 7611 */ MCD_OPC_FilterValue, 28, 48, 0, 0, // Skip to: 7664 -/* 7616 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7619 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 7639 -/* 7624 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 7635 -/* 7631 */ MCD_OPC_Decode, 175, 12, 58, // Opcode: TLBSX -/* 7635 */ MCD_OPC_Decode, 176, 12, 62, // Opcode: TLBSX2 -/* 7639 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 7648 -/* 7644 */ MCD_OPC_Decode, 177, 12, 62, // Opcode: TLBSX2D -/* 7648 */ MCD_OPC_FilterValue, 2, 77, 34, 0, // Skip to: 16434 -/* 7653 */ MCD_OPC_CheckField, 16, 5, 0, 70, 34, 0, // Skip to: 16434 -/* 7660 */ MCD_OPC_Decode, 255, 10, 86, // Opcode: SLBMFEE -/* 7664 */ MCD_OPC_FilterValue, 29, 23, 0, 0, // Skip to: 7692 -/* 7669 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7672 */ MCD_OPC_FilterValue, 0, 53, 34, 0, // Skip to: 16434 -/* 7677 */ MCD_OPC_CheckField, 11, 15, 0, 4, 0, 0, // Skip to: 7688 -/* 7684 */ MCD_OPC_Decode, 173, 12, 0, // Opcode: TLBRE -/* 7688 */ MCD_OPC_Decode, 174, 12, 92, // Opcode: TLBRE2 -/* 7692 */ MCD_OPC_FilterValue, 30, 34, 0, 0, // Skip to: 7731 -/* 7697 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7700 */ MCD_OPC_FilterValue, 0, 25, 34, 0, // Skip to: 16434 -/* 7705 */ MCD_OPC_CheckField, 11, 15, 0, 4, 0, 0, // Skip to: 7716 -/* 7712 */ MCD_OPC_Decode, 179, 12, 0, // Opcode: TLBWE -/* 7716 */ MCD_OPC_CheckField, 16, 10, 0, 4, 0, 0, // Skip to: 7727 -/* 7723 */ MCD_OPC_Decode, 171, 12, 87, // Opcode: TLBLD -/* 7727 */ MCD_OPC_Decode, 180, 12, 92, // Opcode: TLBWE2 -/* 7731 */ MCD_OPC_FilterValue, 31, 250, 33, 0, // Skip to: 16434 -/* 7736 */ MCD_OPC_CheckField, 16, 10, 0, 243, 33, 0, // Skip to: 16434 -/* 7743 */ MCD_OPC_CheckField, 0, 2, 0, 236, 33, 0, // Skip to: 16434 -/* 7750 */ MCD_OPC_Decode, 172, 12, 87, // Opcode: TLBLI -/* 7754 */ MCD_OPC_FilterValue, 10, 141, 1, 0, // Skip to: 8156 -/* 7759 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 7762 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 7797 -/* 7767 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7770 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7779 -/* 7775 */ MCD_OPC_Decode, 231, 7, 93, // Opcode: LWARX -/* 7779 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 7788 -/* 7784 */ MCD_OPC_Decode, 232, 7, 93, // Opcode: LWARXL -/* 7788 */ MCD_OPC_FilterValue, 2, 193, 33, 0, // Skip to: 16434 -/* 7793 */ MCD_OPC_Decode, 171, 7, 94, // Opcode: LDX -/* 7797 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 7832 -/* 7802 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7805 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7814 -/* 7810 */ MCD_OPC_Decode, 147, 7, 93, // Opcode: LBARX -/* 7814 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 7823 -/* 7819 */ MCD_OPC_Decode, 148, 7, 93, // Opcode: LBARXL -/* 7823 */ MCD_OPC_FilterValue, 2, 158, 33, 0, // Skip to: 16434 -/* 7828 */ MCD_OPC_Decode, 170, 7, 95, // Opcode: LDUX -/* 7832 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 7858 -/* 7837 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7840 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7849 -/* 7845 */ MCD_OPC_Decode, 163, 7, 94, // Opcode: LDARX -/* 7849 */ MCD_OPC_FilterValue, 1, 132, 33, 0, // Skip to: 16434 -/* 7854 */ MCD_OPC_Decode, 164, 7, 94, // Opcode: LDARXL -/* 7858 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 7884 -/* 7863 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 7866 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7875 -/* 7871 */ MCD_OPC_Decode, 194, 7, 93, // Opcode: LHARX -/* 7875 */ MCD_OPC_FilterValue, 1, 106, 33, 0, // Skip to: 16434 -/* 7880 */ MCD_OPC_Decode, 195, 7, 93, // Opcode: LHARXL -/* 7884 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 7900 -/* 7889 */ MCD_OPC_CheckField, 0, 2, 2, 90, 33, 0, // Skip to: 16434 -/* 7896 */ MCD_OPC_Decode, 180, 11, 94, // Opcode: STDX -/* 7900 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 7916 -/* 7905 */ MCD_OPC_CheckField, 0, 2, 2, 74, 33, 0, // Skip to: 16434 -/* 7912 */ MCD_OPC_Decode, 179, 11, 96, // Opcode: STDUX -/* 7916 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 7932 -/* 7921 */ MCD_OPC_CheckField, 0, 2, 2, 58, 33, 0, // Skip to: 16434 -/* 7928 */ MCD_OPC_Decode, 168, 7, 94, // Opcode: LDMX -/* 7932 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 7948 -/* 7937 */ MCD_OPC_CheckField, 0, 2, 2, 42, 33, 0, // Skip to: 16434 -/* 7944 */ MCD_OPC_Decode, 235, 7, 94, // Opcode: LWAX -/* 7948 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 7964 -/* 7953 */ MCD_OPC_CheckField, 0, 2, 2, 26, 33, 0, // Skip to: 16434 -/* 7960 */ MCD_OPC_Decode, 234, 7, 95, // Opcode: LWAUX -/* 7964 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 7980 -/* 7969 */ MCD_OPC_CheckField, 0, 2, 0, 10, 33, 0, // Skip to: 16434 -/* 7976 */ MCD_OPC_Decode, 166, 7, 94, // Opcode: LDBRX -/* 7980 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 7996 -/* 7985 */ MCD_OPC_CheckField, 0, 2, 2, 250, 32, 0, // Skip to: 16434 -/* 7992 */ MCD_OPC_Decode, 222, 7, 59, // Opcode: LSWI -/* 7996 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 8012 -/* 8001 */ MCD_OPC_CheckField, 0, 2, 0, 234, 32, 0, // Skip to: 16434 -/* 8008 */ MCD_OPC_Decode, 175, 11, 94, // Opcode: STDBRX -/* 8012 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 8028 -/* 8017 */ MCD_OPC_CheckField, 0, 2, 2, 218, 32, 0, // Skip to: 16434 -/* 8024 */ MCD_OPC_Decode, 210, 11, 59, // Opcode: STSWI -/* 8028 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 8044 -/* 8033 */ MCD_OPC_CheckField, 0, 2, 2, 202, 32, 0, // Skip to: 16434 -/* 8040 */ MCD_OPC_Decode, 243, 7, 62, // Opcode: LWZCIX -/* 8044 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 8060 -/* 8049 */ MCD_OPC_CheckField, 0, 2, 2, 186, 32, 0, // Skip to: 16434 -/* 8056 */ MCD_OPC_Decode, 207, 7, 62, // Opcode: LHZCIX -/* 8060 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 8076 -/* 8065 */ MCD_OPC_CheckField, 0, 2, 2, 170, 32, 0, // Skip to: 16434 -/* 8072 */ MCD_OPC_Decode, 152, 7, 62, // Opcode: LBZCIX -/* 8076 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 8092 -/* 8081 */ MCD_OPC_CheckField, 0, 2, 2, 154, 32, 0, // Skip to: 16434 -/* 8088 */ MCD_OPC_Decode, 167, 7, 62, // Opcode: LDCIX -/* 8092 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 8108 -/* 8097 */ MCD_OPC_CheckField, 0, 2, 2, 138, 32, 0, // Skip to: 16434 -/* 8104 */ MCD_OPC_Decode, 220, 11, 62, // Opcode: STWCIX -/* 8108 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 8124 -/* 8113 */ MCD_OPC_CheckField, 0, 2, 2, 122, 32, 0, // Skip to: 16434 -/* 8120 */ MCD_OPC_Decode, 196, 11, 62, // Opcode: STHCIX -/* 8124 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 8140 -/* 8129 */ MCD_OPC_CheckField, 0, 2, 2, 106, 32, 0, // Skip to: 16434 -/* 8136 */ MCD_OPC_Decode, 161, 11, 62, // Opcode: STBCIX -/* 8140 */ MCD_OPC_FilterValue, 31, 97, 32, 0, // Skip to: 16434 -/* 8145 */ MCD_OPC_CheckField, 0, 2, 2, 90, 32, 0, // Skip to: 16434 -/* 8152 */ MCD_OPC_Decode, 176, 11, 62, // Opcode: STDCIX -/* 8156 */ MCD_OPC_FilterValue, 11, 89, 3, 0, // Skip to: 9018 -/* 8161 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 8164 */ MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 8197 -/* 8169 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8172 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8188 -/* 8177 */ MCD_OPC_CheckField, 25, 1, 0, 58, 32, 0, // Skip to: 16434 -/* 8184 */ MCD_OPC_Decode, 140, 7, 57, // Opcode: ICBT -/* 8188 */ MCD_OPC_FilterValue, 2, 49, 32, 0, // Skip to: 16434 -/* 8193 */ MCD_OPC_Decode, 248, 7, 93, // Opcode: LWZX -/* 8197 */ MCD_OPC_FilterValue, 1, 28, 0, 0, // Skip to: 8230 -/* 8202 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8205 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8221 -/* 8210 */ MCD_OPC_CheckField, 21, 5, 0, 25, 32, 0, // Skip to: 16434 -/* 8217 */ MCD_OPC_Decode, 215, 3, 97, // Opcode: DCBST -/* 8221 */ MCD_OPC_FilterValue, 2, 16, 32, 0, // Skip to: 16434 -/* 8226 */ MCD_OPC_Decode, 246, 7, 98, // Opcode: LWZUX -/* 8230 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 8256 -/* 8235 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8238 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8247 -/* 8243 */ MCD_OPC_Decode, 212, 3, 99, // Opcode: DCBF -/* 8247 */ MCD_OPC_FilterValue, 2, 246, 31, 0, // Skip to: 16434 -/* 8252 */ MCD_OPC_Decode, 157, 7, 93, // Opcode: LBZX -/* 8256 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 8272 -/* 8261 */ MCD_OPC_CheckField, 0, 2, 2, 230, 31, 0, // Skip to: 16434 -/* 8268 */ MCD_OPC_Decode, 155, 7, 98, // Opcode: LBZUX -/* 8272 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 8298 -/* 8277 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8280 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 8289 -/* 8285 */ MCD_OPC_Decode, 221, 11, 93, // Opcode: STWCX -/* 8289 */ MCD_OPC_FilterValue, 2, 204, 31, 0, // Skip to: 16434 -/* 8294 */ MCD_OPC_Decode, 227, 11, 93, // Opcode: STWX -/* 8298 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 8314 -/* 8303 */ MCD_OPC_CheckField, 0, 2, 2, 188, 31, 0, // Skip to: 16434 -/* 8310 */ MCD_OPC_Decode, 225, 11, 100, // Opcode: STWUX -/* 8314 */ MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 8340 -/* 8319 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8322 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 8331 -/* 8327 */ MCD_OPC_Decode, 177, 11, 94, // Opcode: STDCX -/* 8331 */ MCD_OPC_FilterValue, 2, 162, 31, 0, // Skip to: 16434 -/* 8336 */ MCD_OPC_Decode, 168, 11, 93, // Opcode: STBX -/* 8340 */ MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 8366 -/* 8345 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8348 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8357 -/* 8353 */ MCD_OPC_Decode, 219, 3, 99, // Opcode: DCBTST -/* 8357 */ MCD_OPC_FilterValue, 2, 136, 31, 0, // Skip to: 16434 -/* 8362 */ MCD_OPC_Decode, 166, 11, 100, // Opcode: STBUX -/* 8366 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 8392 -/* 8371 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8374 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8383 -/* 8379 */ MCD_OPC_Decode, 217, 3, 99, // Opcode: DCBT -/* 8383 */ MCD_OPC_FilterValue, 2, 110, 31, 0, // Skip to: 16434 -/* 8388 */ MCD_OPC_Decode, 212, 7, 93, // Opcode: LHZX -/* 8392 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 8408 -/* 8397 */ MCD_OPC_CheckField, 0, 2, 2, 94, 31, 0, // Skip to: 16434 -/* 8404 */ MCD_OPC_Decode, 210, 7, 98, // Opcode: LHZUX -/* 8408 */ MCD_OPC_FilterValue, 10, 38, 0, 0, // Skip to: 8451 -/* 8413 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8416 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 8442 -/* 8421 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 8424 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8433 -/* 8429 */ MCD_OPC_Decode, 244, 3, 101, // Opcode: DST -/* 8433 */ MCD_OPC_FilterValue, 4, 60, 31, 0, // Skip to: 16434 -/* 8438 */ MCD_OPC_Decode, 250, 3, 101, // Opcode: DSTT -/* 8442 */ MCD_OPC_FilterValue, 2, 51, 31, 0, // Skip to: 16434 -/* 8447 */ MCD_OPC_Decode, 200, 7, 93, // Opcode: LHAX -/* 8451 */ MCD_OPC_FilterValue, 11, 38, 0, 0, // Skip to: 8494 -/* 8456 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8459 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 8485 -/* 8464 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 8467 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8476 -/* 8472 */ MCD_OPC_Decode, 246, 3, 101, // Opcode: DSTST -/* 8476 */ MCD_OPC_FilterValue, 4, 17, 31, 0, // Skip to: 16434 -/* 8481 */ MCD_OPC_Decode, 248, 3, 101, // Opcode: DSTSTT -/* 8485 */ MCD_OPC_FilterValue, 2, 8, 31, 0, // Skip to: 16434 -/* 8490 */ MCD_OPC_Decode, 198, 7, 98, // Opcode: LHAUX -/* 8494 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 8510 -/* 8499 */ MCD_OPC_CheckField, 0, 2, 2, 248, 30, 0, // Skip to: 16434 -/* 8506 */ MCD_OPC_Decode, 203, 11, 93, // Opcode: STHX -/* 8510 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 8526 -/* 8515 */ MCD_OPC_CheckField, 0, 2, 2, 232, 30, 0, // Skip to: 16434 -/* 8522 */ MCD_OPC_Decode, 201, 11, 100, // Opcode: STHUX -/* 8526 */ MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 8549 -/* 8531 */ MCD_OPC_CheckField, 21, 5, 0, 216, 30, 0, // Skip to: 16434 -/* 8538 */ MCD_OPC_CheckField, 0, 2, 0, 209, 30, 0, // Skip to: 16434 -/* 8545 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: DCBI -/* 8549 */ MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 8575 -/* 8554 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8557 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8566 -/* 8562 */ MCD_OPC_Decode, 238, 7, 93, // Opcode: LWBRX -/* 8566 */ MCD_OPC_FilterValue, 2, 183, 30, 0, // Skip to: 16434 -/* 8571 */ MCD_OPC_Decode, 191, 7, 102, // Opcode: LFSX -/* 8575 */ MCD_OPC_FilterValue, 17, 28, 0, 0, // Skip to: 8608 -/* 8580 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8583 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8599 -/* 8588 */ MCD_OPC_CheckField, 11, 15, 0, 159, 30, 0, // Skip to: 16434 -/* 8595 */ MCD_OPC_Decode, 178, 12, 0, // Opcode: TLBSYNC -/* 8599 */ MCD_OPC_FilterValue, 2, 150, 30, 0, // Skip to: 16434 -/* 8604 */ MCD_OPC_Decode, 190, 7, 103, // Opcode: LFSUX -/* 8608 */ MCD_OPC_FilterValue, 18, 35, 0, 0, // Skip to: 8648 -/* 8613 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8616 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 8639 -/* 8621 */ MCD_OPC_CheckField, 23, 3, 0, 126, 30, 0, // Skip to: 16434 -/* 8628 */ MCD_OPC_CheckField, 11, 10, 0, 119, 30, 0, // Skip to: 16434 -/* 8635 */ MCD_OPC_Decode, 143, 12, 104, // Opcode: SYNC -/* 8639 */ MCD_OPC_FilterValue, 2, 110, 30, 0, // Skip to: 16434 -/* 8644 */ MCD_OPC_Decode, 185, 7, 105, // Opcode: LFDX -/* 8648 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 8664 -/* 8653 */ MCD_OPC_CheckField, 0, 2, 2, 94, 30, 0, // Skip to: 16434 -/* 8660 */ MCD_OPC_Decode, 184, 7, 106, // Opcode: LFDUX -/* 8664 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 8690 -/* 8669 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8672 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8681 -/* 8677 */ MCD_OPC_Decode, 219, 11, 93, // Opcode: STWBRX -/* 8681 */ MCD_OPC_FilterValue, 2, 68, 30, 0, // Skip to: 16434 -/* 8686 */ MCD_OPC_Decode, 192, 11, 102, // Opcode: STFSX -/* 8690 */ MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 8716 -/* 8695 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8698 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 8707 -/* 8703 */ MCD_OPC_Decode, 162, 11, 93, // Opcode: STBCX -/* 8707 */ MCD_OPC_FilterValue, 2, 42, 30, 0, // Skip to: 16434 -/* 8712 */ MCD_OPC_Decode, 191, 11, 107, // Opcode: STFSUX -/* 8716 */ MCD_OPC_FilterValue, 22, 21, 0, 0, // Skip to: 8742 -/* 8721 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8724 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 8733 -/* 8729 */ MCD_OPC_Decode, 197, 11, 93, // Opcode: STHCX -/* 8733 */ MCD_OPC_FilterValue, 2, 16, 30, 0, // Skip to: 16434 -/* 8738 */ MCD_OPC_Decode, 187, 11, 105, // Opcode: STFDX -/* 8742 */ MCD_OPC_FilterValue, 23, 28, 0, 0, // Skip to: 8775 -/* 8747 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8750 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8766 -/* 8755 */ MCD_OPC_CheckField, 21, 5, 0, 248, 29, 0, // Skip to: 16434 -/* 8762 */ MCD_OPC_Decode, 211, 3, 97, // Opcode: DCBA -/* 8766 */ MCD_OPC_FilterValue, 2, 239, 29, 0, // Skip to: 16434 -/* 8771 */ MCD_OPC_Decode, 186, 11, 108, // Opcode: STFDUX -/* 8775 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 8791 -/* 8780 */ MCD_OPC_CheckField, 0, 2, 0, 223, 29, 0, // Skip to: 16434 -/* 8787 */ MCD_OPC_Decode, 202, 7, 93, // Opcode: LHBRX -/* 8791 */ MCD_OPC_FilterValue, 25, 49, 0, 0, // Skip to: 8845 -/* 8796 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... -/* 8799 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 8822 -/* 8804 */ MCD_OPC_CheckField, 11, 10, 0, 199, 29, 0, // Skip to: 16434 -/* 8811 */ MCD_OPC_CheckField, 0, 2, 0, 192, 29, 0, // Skip to: 16434 -/* 8818 */ MCD_OPC_Decode, 242, 3, 109, // Opcode: DSS -/* 8822 */ MCD_OPC_FilterValue, 4, 183, 29, 0, // Skip to: 16434 -/* 8827 */ MCD_OPC_CheckField, 11, 12, 0, 176, 29, 0, // Skip to: 16434 -/* 8834 */ MCD_OPC_CheckField, 0, 2, 0, 169, 29, 0, // Skip to: 16434 -/* 8841 */ MCD_OPC_Decode, 243, 3, 0, // Opcode: DSSALL -/* 8845 */ MCD_OPC_FilterValue, 26, 46, 0, 0, // Skip to: 8896 -/* 8850 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... -/* 8853 */ MCD_OPC_FilterValue, 0, 22, 0, 0, // Skip to: 8880 -/* 8858 */ MCD_OPC_CheckField, 11, 15, 0, 11, 0, 0, // Skip to: 8876 -/* 8865 */ MCD_OPC_CheckField, 0, 1, 0, 4, 0, 0, // Skip to: 8876 -/* 8872 */ MCD_OPC_Decode, 145, 6, 0, // Opcode: EnforceIEIO -/* 8876 */ MCD_OPC_Decode, 147, 8, 110, // Opcode: MBAR -/* 8880 */ MCD_OPC_FilterValue, 1, 125, 29, 0, // Skip to: 16434 -/* 8885 */ MCD_OPC_CheckField, 0, 1, 0, 118, 29, 0, // Skip to: 16434 -/* 8892 */ MCD_OPC_Decode, 186, 7, 105, // Opcode: LFIWAX -/* 8896 */ MCD_OPC_FilterValue, 27, 28, 0, 0, // Skip to: 8929 -/* 8901 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8904 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8920 -/* 8909 */ MCD_OPC_CheckField, 11, 15, 0, 94, 29, 0, // Skip to: 16434 -/* 8916 */ MCD_OPC_Decode, 188, 8, 0, // Opcode: MSGSYNC -/* 8920 */ MCD_OPC_FilterValue, 2, 85, 29, 0, // Skip to: 16434 -/* 8925 */ MCD_OPC_Decode, 187, 7, 105, // Opcode: LFIWZX -/* 8929 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 8945 -/* 8934 */ MCD_OPC_CheckField, 0, 2, 0, 69, 29, 0, // Skip to: 16434 -/* 8941 */ MCD_OPC_Decode, 195, 11, 93, // Opcode: STHBRX -/* 8945 */ MCD_OPC_FilterValue, 30, 28, 0, 0, // Skip to: 8978 -/* 8950 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 8953 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8969 -/* 8958 */ MCD_OPC_CheckField, 21, 5, 0, 45, 29, 0, // Skip to: 16434 -/* 8965 */ MCD_OPC_Decode, 136, 7, 97, // Opcode: ICBI -/* 8969 */ MCD_OPC_FilterValue, 2, 36, 29, 0, // Skip to: 16434 -/* 8974 */ MCD_OPC_Decode, 188, 11, 105, // Opcode: STFIWX -/* 8978 */ MCD_OPC_FilterValue, 31, 27, 29, 0, // Skip to: 16434 -/* 8983 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 8986 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9002 -/* 8991 */ MCD_OPC_CheckField, 0, 2, 0, 12, 29, 0, // Skip to: 16434 -/* 8998 */ MCD_OPC_Decode, 221, 3, 97, // Opcode: DCBZ -/* 9002 */ MCD_OPC_FilterValue, 1, 3, 29, 0, // Skip to: 16434 -/* 9007 */ MCD_OPC_CheckField, 0, 2, 0, 252, 28, 0, // Skip to: 16434 -/* 9014 */ MCD_OPC_Decode, 223, 3, 97, // Opcode: DCBZL -/* 9018 */ MCD_OPC_FilterValue, 12, 107, 0, 0, // Skip to: 9130 -/* 9023 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 9026 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 9052 -/* 9031 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9034 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9043 -/* 9039 */ MCD_OPC_Decode, 133, 11, 111, // Opcode: SLW -/* 9043 */ MCD_OPC_FilterValue, 1, 218, 28, 0, // Skip to: 16434 -/* 9048 */ MCD_OPC_Decode, 136, 11, 111, // Opcode: SLWo -/* 9052 */ MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 9078 -/* 9057 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9060 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9069 -/* 9065 */ MCD_OPC_Decode, 155, 11, 111, // Opcode: SRW -/* 9069 */ MCD_OPC_FilterValue, 1, 192, 28, 0, // Skip to: 16434 -/* 9074 */ MCD_OPC_Decode, 158, 11, 111, // Opcode: SRWo -/* 9078 */ MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 9104 -/* 9083 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9086 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9095 -/* 9091 */ MCD_OPC_Decode, 149, 11, 111, // Opcode: SRAW -/* 9095 */ MCD_OPC_FilterValue, 1, 166, 28, 0, // Skip to: 16434 -/* 9100 */ MCD_OPC_Decode, 152, 11, 111, // Opcode: SRAWo -/* 9104 */ MCD_OPC_FilterValue, 25, 157, 28, 0, // Skip to: 16434 -/* 9109 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9112 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9121 -/* 9117 */ MCD_OPC_Decode, 150, 11, 112, // Opcode: SRAWI -/* 9121 */ MCD_OPC_FilterValue, 1, 140, 28, 0, // Skip to: 16434 -/* 9126 */ MCD_OPC_Decode, 151, 11, 112, // Opcode: SRAWIo -/* 9130 */ MCD_OPC_FilterValue, 13, 210, 1, 0, // Skip to: 9601 -/* 9135 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 9138 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 9196 -/* 9143 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9146 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9162 -/* 9151 */ MCD_OPC_CheckField, 11, 5, 0, 108, 28, 0, // Skip to: 16434 -/* 9158 */ MCD_OPC_Decode, 180, 3, 113, // Opcode: CNTLZW -/* 9162 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 9178 -/* 9167 */ MCD_OPC_CheckField, 11, 5, 0, 92, 28, 0, // Skip to: 16434 -/* 9174 */ MCD_OPC_Decode, 183, 3, 113, // Opcode: CNTLZWo -/* 9178 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9187 -/* 9183 */ MCD_OPC_Decode, 131, 11, 114, // Opcode: SLD -/* 9187 */ MCD_OPC_FilterValue, 3, 74, 28, 0, // Skip to: 16434 -/* 9192 */ MCD_OPC_Decode, 132, 11, 114, // Opcode: SLDo -/* 9196 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 9236 -/* 9201 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9204 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9220 -/* 9209 */ MCD_OPC_CheckField, 11, 5, 0, 50, 28, 0, // Skip to: 16434 -/* 9216 */ MCD_OPC_Decode, 178, 3, 115, // Opcode: CNTLZD -/* 9220 */ MCD_OPC_FilterValue, 1, 41, 28, 0, // Skip to: 16434 -/* 9225 */ MCD_OPC_CheckField, 11, 5, 0, 34, 28, 0, // Skip to: 16434 -/* 9232 */ MCD_OPC_Decode, 179, 3, 115, // Opcode: CNTLZDo -/* 9236 */ MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 9259 -/* 9241 */ MCD_OPC_CheckField, 11, 5, 0, 18, 28, 0, // Skip to: 16434 -/* 9248 */ MCD_OPC_CheckField, 0, 2, 0, 11, 28, 0, // Skip to: 16434 -/* 9255 */ MCD_OPC_Decode, 140, 9, 113, // Opcode: POPCNTB -/* 9259 */ MCD_OPC_FilterValue, 11, 18, 0, 0, // Skip to: 9282 -/* 9264 */ MCD_OPC_CheckField, 11, 5, 0, 251, 27, 0, // Skip to: 16434 -/* 9271 */ MCD_OPC_CheckField, 0, 2, 0, 244, 27, 0, // Skip to: 16434 -/* 9278 */ MCD_OPC_Decode, 142, 9, 113, // Opcode: POPCNTW -/* 9282 */ MCD_OPC_FilterValue, 15, 18, 0, 0, // Skip to: 9305 -/* 9287 */ MCD_OPC_CheckField, 11, 5, 0, 228, 27, 0, // Skip to: 16434 -/* 9294 */ MCD_OPC_CheckField, 0, 2, 0, 221, 27, 0, // Skip to: 16434 -/* 9301 */ MCD_OPC_Decode, 141, 9, 115, // Opcode: POPCNTD -/* 9305 */ MCD_OPC_FilterValue, 16, 53, 0, 0, // Skip to: 9363 -/* 9310 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9313 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9329 -/* 9318 */ MCD_OPC_CheckField, 11, 5, 0, 197, 27, 0, // Skip to: 16434 -/* 9325 */ MCD_OPC_Decode, 186, 3, 113, // Opcode: CNTTZW -/* 9329 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 9345 -/* 9334 */ MCD_OPC_CheckField, 11, 5, 0, 181, 27, 0, // Skip to: 16434 -/* 9341 */ MCD_OPC_Decode, 189, 3, 113, // Opcode: CNTTZWo -/* 9345 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9354 -/* 9350 */ MCD_OPC_Decode, 153, 11, 114, // Opcode: SRD -/* 9354 */ MCD_OPC_FilterValue, 3, 163, 27, 0, // Skip to: 16434 -/* 9359 */ MCD_OPC_Decode, 154, 11, 114, // Opcode: SRDo -/* 9363 */ MCD_OPC_FilterValue, 17, 35, 0, 0, // Skip to: 9403 -/* 9368 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9371 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9387 -/* 9376 */ MCD_OPC_CheckField, 11, 5, 0, 139, 27, 0, // Skip to: 16434 -/* 9383 */ MCD_OPC_Decode, 184, 3, 115, // Opcode: CNTTZD -/* 9387 */ MCD_OPC_FilterValue, 1, 130, 27, 0, // Skip to: 16434 -/* 9392 */ MCD_OPC_CheckField, 11, 5, 0, 123, 27, 0, // Skip to: 16434 -/* 9399 */ MCD_OPC_Decode, 185, 3, 115, // Opcode: CNTTZDo -/* 9403 */ MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 9429 -/* 9408 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9411 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9420 -/* 9416 */ MCD_OPC_Decode, 144, 11, 114, // Opcode: SRAD -/* 9420 */ MCD_OPC_FilterValue, 1, 97, 27, 0, // Skip to: 16434 -/* 9425 */ MCD_OPC_Decode, 148, 11, 114, // Opcode: SRADo -/* 9429 */ MCD_OPC_FilterValue, 25, 21, 0, 0, // Skip to: 9455 -/* 9434 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 9437 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9446 -/* 9442 */ MCD_OPC_Decode, 145, 11, 116, // Opcode: SRADI -/* 9446 */ MCD_OPC_FilterValue, 1, 71, 27, 0, // Skip to: 16434 -/* 9451 */ MCD_OPC_Decode, 147, 11, 116, // Opcode: SRADIo -/* 9455 */ MCD_OPC_FilterValue, 27, 21, 0, 0, // Skip to: 9481 -/* 9460 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... -/* 9463 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9472 -/* 9468 */ MCD_OPC_Decode, 139, 6, 116, // Opcode: EXTSWSLI -/* 9472 */ MCD_OPC_FilterValue, 1, 45, 27, 0, // Skip to: 16434 -/* 9477 */ MCD_OPC_Decode, 140, 6, 116, // Opcode: EXTSWSLIo -/* 9481 */ MCD_OPC_FilterValue, 28, 35, 0, 0, // Skip to: 9521 -/* 9486 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9489 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9505 -/* 9494 */ MCD_OPC_CheckField, 11, 5, 0, 21, 27, 0, // Skip to: 16434 -/* 9501 */ MCD_OPC_Decode, 133, 6, 113, // Opcode: EXTSH -/* 9505 */ MCD_OPC_FilterValue, 1, 12, 27, 0, // Skip to: 16434 -/* 9510 */ MCD_OPC_CheckField, 11, 5, 0, 5, 27, 0, // Skip to: 16434 -/* 9517 */ MCD_OPC_Decode, 137, 6, 113, // Opcode: EXTSHo -/* 9521 */ MCD_OPC_FilterValue, 29, 35, 0, 0, // Skip to: 9561 -/* 9526 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9529 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9545 -/* 9534 */ MCD_OPC_CheckField, 11, 5, 0, 237, 26, 0, // Skip to: 16434 -/* 9541 */ MCD_OPC_Decode, 128, 6, 113, // Opcode: EXTSB -/* 9545 */ MCD_OPC_FilterValue, 1, 228, 26, 0, // Skip to: 16434 -/* 9550 */ MCD_OPC_CheckField, 11, 5, 0, 221, 26, 0, // Skip to: 16434 -/* 9557 */ MCD_OPC_Decode, 132, 6, 113, // Opcode: EXTSBo -/* 9561 */ MCD_OPC_FilterValue, 30, 212, 26, 0, // Skip to: 16434 -/* 9566 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9569 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9585 -/* 9574 */ MCD_OPC_CheckField, 11, 5, 0, 197, 26, 0, // Skip to: 16434 -/* 9581 */ MCD_OPC_Decode, 138, 6, 115, // Opcode: EXTSW -/* 9585 */ MCD_OPC_FilterValue, 1, 188, 26, 0, // Skip to: 16434 -/* 9590 */ MCD_OPC_CheckField, 11, 5, 0, 181, 26, 0, // Skip to: 16434 -/* 9597 */ MCD_OPC_Decode, 144, 6, 115, // Opcode: EXTSWo -/* 9601 */ MCD_OPC_FilterValue, 14, 243, 0, 0, // Skip to: 9849 -/* 9606 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 9609 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 9635 -/* 9614 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9617 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9626 -/* 9622 */ MCD_OPC_Decode, 253, 1, 111, // Opcode: AND -/* 9626 */ MCD_OPC_FilterValue, 1, 147, 26, 0, // Skip to: 16434 -/* 9631 */ MCD_OPC_Decode, 140, 2, 111, // Opcode: ANDo -/* 9635 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 9661 -/* 9640 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9643 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9652 -/* 9648 */ MCD_OPC_Decode, 128, 2, 111, // Opcode: ANDC -/* 9652 */ MCD_OPC_FilterValue, 1, 121, 26, 0, // Skip to: 16434 -/* 9657 */ MCD_OPC_Decode, 131, 2, 111, // Opcode: ANDCo -/* 9661 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 9687 -/* 9666 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9669 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9678 -/* 9674 */ MCD_OPC_Decode, 252, 8, 111, // Opcode: NOR -/* 9678 */ MCD_OPC_FilterValue, 1, 95, 26, 0, // Skip to: 16434 -/* 9683 */ MCD_OPC_Decode, 255, 8, 111, // Opcode: NORo -/* 9687 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 9703 -/* 9692 */ MCD_OPC_CheckField, 0, 2, 0, 79, 26, 0, // Skip to: 16434 -/* 9699 */ MCD_OPC_Decode, 162, 3, 117, // Opcode: BPERMD -/* 9703 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 9729 -/* 9708 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9711 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9720 -/* 9716 */ MCD_OPC_Decode, 185, 4, 111, // Opcode: EQV -/* 9720 */ MCD_OPC_FilterValue, 1, 53, 26, 0, // Skip to: 16434 -/* 9725 */ MCD_OPC_Decode, 188, 4, 111, // Opcode: EQVo -/* 9729 */ MCD_OPC_FilterValue, 9, 21, 0, 0, // Skip to: 9755 -/* 9734 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 34 */ MCD_OPC_Decode, 140, 14, 2, // Opcode: TWI +/* 38 */ MCD_OPC_FilterValue, 4, 255, 23, 0, // Skip to: 6186 +/* 43 */ MCD_OPC_ExtractField, 1, 5, // Inst{5-1} ... +/* 46 */ MCD_OPC_FilterValue, 0, 217, 2, 0, // Skip to: 780 +/* 51 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... +/* 54 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 160 +/* 59 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 62 */ MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 95 +/* 67 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 70 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 79 +/* 75 */ MCD_OPC_Decode, 154, 14, 3, // Opcode: VADDUBM +/* 79 */ MCD_OPC_FilterValue, 1, 32, 84, 0, // Skip to: 21620 +/* 84 */ MCD_OPC_CheckField, 11, 5, 0, 25, 84, 0, // Skip to: 21620 +/* 91 */ MCD_OPC_Decode, 245, 15, 4, // Opcode: VMUL10CUQ +/* 95 */ MCD_OPC_FilterValue, 1, 28, 0, 0, // Skip to: 128 +/* 100 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 103 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 112 +/* 108 */ MCD_OPC_Decode, 155, 14, 3, // Opcode: VADDUBS +/* 112 */ MCD_OPC_FilterValue, 1, 255, 83, 0, // Skip to: 21620 +/* 117 */ MCD_OPC_CheckField, 11, 5, 0, 248, 83, 0, // Skip to: 21620 +/* 124 */ MCD_OPC_Decode, 248, 15, 4, // Opcode: VMUL10UQ +/* 128 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 144 +/* 133 */ MCD_OPC_CheckField, 0, 1, 0, 232, 83, 0, // Skip to: 21620 +/* 140 */ MCD_OPC_Decode, 250, 16, 3, // Opcode: VSUBUBM +/* 144 */ MCD_OPC_FilterValue, 3, 223, 83, 0, // Skip to: 21620 +/* 149 */ MCD_OPC_CheckField, 0, 1, 0, 216, 83, 0, // Skip to: 21620 +/* 156 */ MCD_OPC_Decode, 251, 16, 3, // Opcode: VSUBUBS +/* 160 */ MCD_OPC_FilterValue, 1, 87, 0, 0, // Skip to: 252 +/* 165 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 168 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 194 +/* 173 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 176 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 185 +/* 181 */ MCD_OPC_Decode, 157, 14, 3, // Opcode: VADDUHM +/* 185 */ MCD_OPC_FilterValue, 1, 182, 83, 0, // Skip to: 21620 +/* 190 */ MCD_OPC_Decode, 246, 15, 3, // Opcode: VMUL10ECUQ +/* 194 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 220 +/* 199 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 202 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 211 +/* 207 */ MCD_OPC_Decode, 158, 14, 3, // Opcode: VADDUHS +/* 211 */ MCD_OPC_FilterValue, 1, 156, 83, 0, // Skip to: 21620 +/* 216 */ MCD_OPC_Decode, 247, 15, 3, // Opcode: VMUL10EUQ +/* 220 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 236 +/* 225 */ MCD_OPC_CheckField, 0, 1, 0, 140, 83, 0, // Skip to: 21620 +/* 232 */ MCD_OPC_Decode, 253, 16, 3, // Opcode: VSUBUHM +/* 236 */ MCD_OPC_FilterValue, 3, 131, 83, 0, // Skip to: 21620 +/* 241 */ MCD_OPC_CheckField, 0, 1, 0, 124, 83, 0, // Skip to: 21620 +/* 248 */ MCD_OPC_Decode, 254, 16, 3, // Opcode: VSUBUHS +/* 252 */ MCD_OPC_FilterValue, 2, 77, 0, 0, // Skip to: 334 +/* 257 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 260 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 276 +/* 265 */ MCD_OPC_CheckField, 0, 1, 0, 100, 83, 0, // Skip to: 21620 +/* 272 */ MCD_OPC_Decode, 160, 14, 3, // Opcode: VADDUWM +/* 276 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 292 +/* 281 */ MCD_OPC_CheckField, 0, 1, 0, 84, 83, 0, // Skip to: 21620 +/* 288 */ MCD_OPC_Decode, 161, 14, 3, // Opcode: VADDUWS +/* 292 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 318 +/* 297 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 300 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 309 +/* 305 */ MCD_OPC_Decode, 128, 17, 3, // Opcode: VSUBUWM +/* 309 */ MCD_OPC_FilterValue, 1, 58, 83, 0, // Skip to: 21620 +/* 314 */ MCD_OPC_Decode, 243, 3, 3, // Opcode: BCDUS_rec +/* 318 */ MCD_OPC_FilterValue, 3, 49, 83, 0, // Skip to: 21620 +/* 323 */ MCD_OPC_CheckField, 0, 1, 0, 42, 83, 0, // Skip to: 21620 +/* 330 */ MCD_OPC_Decode, 129, 17, 3, // Opcode: VSUBUWS +/* 334 */ MCD_OPC_FilterValue, 3, 45, 0, 0, // Skip to: 384 +/* 339 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 342 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 368 +/* 347 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 350 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 359 +/* 355 */ MCD_OPC_Decode, 156, 14, 3, // Opcode: VADDUDM +/* 359 */ MCD_OPC_FilterValue, 2, 8, 83, 0, // Skip to: 21620 +/* 364 */ MCD_OPC_Decode, 252, 16, 3, // Opcode: VSUBUDM +/* 368 */ MCD_OPC_FilterValue, 1, 255, 82, 0, // Skip to: 21620 +/* 373 */ MCD_OPC_CheckField, 10, 1, 1, 248, 82, 0, // Skip to: 21620 +/* 380 */ MCD_OPC_Decode, 241, 3, 5, // Opcode: BCDS_rec +/* 384 */ MCD_OPC_FilterValue, 4, 87, 0, 0, // Skip to: 476 +/* 389 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 392 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 436 +/* 397 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 400 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 409 +/* 405 */ MCD_OPC_Decode, 159, 14, 3, // Opcode: VADDUQM +/* 409 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 418 +/* 414 */ MCD_OPC_Decode, 151, 14, 3, // Opcode: VADDSBS +/* 418 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 427 +/* 423 */ MCD_OPC_Decode, 255, 16, 3, // Opcode: VSUBUQM +/* 427 */ MCD_OPC_FilterValue, 3, 196, 82, 0, // Skip to: 21620 +/* 432 */ MCD_OPC_Decode, 247, 16, 3, // Opcode: VSUBSBS +/* 436 */ MCD_OPC_FilterValue, 1, 187, 82, 0, // Skip to: 21620 +/* 441 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 444 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 467 +/* 449 */ MCD_OPC_CheckField, 21, 2, 0, 172, 82, 0, // Skip to: 21620 +/* 456 */ MCD_OPC_CheckField, 9, 1, 0, 165, 82, 0, // Skip to: 21620 +/* 463 */ MCD_OPC_Decode, 238, 14, 6, // Opcode: VCMPUQ +/* 467 */ MCD_OPC_FilterValue, 1, 156, 82, 0, // Skip to: 21620 +/* 472 */ MCD_OPC_Decode, 242, 3, 5, // Opcode: BCDTRUNC_rec +/* 476 */ MCD_OPC_FilterValue, 5, 104, 0, 0, // Skip to: 585 +/* 481 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 484 */ MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 517 +/* 489 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 492 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 501 +/* 497 */ MCD_OPC_Decode, 146, 14, 3, // Opcode: VADDCUQ +/* 501 */ MCD_OPC_FilterValue, 1, 122, 82, 0, // Skip to: 21620 +/* 506 */ MCD_OPC_CheckField, 21, 2, 0, 115, 82, 0, // Skip to: 21620 +/* 513 */ MCD_OPC_Decode, 237, 14, 6, // Opcode: VCMPSQ +/* 517 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 543 +/* 522 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 525 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 534 +/* 530 */ MCD_OPC_Decode, 152, 14, 3, // Opcode: VADDSHS +/* 534 */ MCD_OPC_FilterValue, 1, 89, 82, 0, // Skip to: 21620 +/* 539 */ MCD_OPC_Decode, 235, 3, 3, // Opcode: BCDCPSGN_rec +/* 543 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 569 +/* 548 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 551 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 560 +/* 556 */ MCD_OPC_Decode, 242, 16, 3, // Opcode: VSUBCUQ +/* 560 */ MCD_OPC_FilterValue, 1, 63, 82, 0, // Skip to: 21620 +/* 565 */ MCD_OPC_Decode, 244, 3, 3, // Opcode: BCDUTRUNC_rec +/* 569 */ MCD_OPC_FilterValue, 3, 54, 82, 0, // Skip to: 21620 +/* 574 */ MCD_OPC_CheckField, 0, 1, 0, 47, 82, 0, // Skip to: 21620 +/* 581 */ MCD_OPC_Decode, 248, 16, 3, // Opcode: VSUBSHS +/* 585 */ MCD_OPC_FilterValue, 6, 167, 0, 0, // Skip to: 757 +/* 590 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 593 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 637 +/* 598 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 601 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 610 +/* 606 */ MCD_OPC_Decode, 147, 14, 3, // Opcode: VADDCUW +/* 610 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 619 +/* 615 */ MCD_OPC_Decode, 153, 14, 3, // Opcode: VADDSWS +/* 619 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 628 +/* 624 */ MCD_OPC_Decode, 243, 16, 3, // Opcode: VSUBCUW +/* 628 */ MCD_OPC_FilterValue, 3, 251, 81, 0, // Skip to: 21620 +/* 633 */ MCD_OPC_Decode, 249, 16, 3, // Opcode: VSUBSWS +/* 637 */ MCD_OPC_FilterValue, 1, 242, 81, 0, // Skip to: 21620 +/* 642 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 645 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 661 +/* 650 */ MCD_OPC_CheckField, 9, 2, 2, 227, 81, 0, // Skip to: 21620 +/* 657 */ MCD_OPC_Decode, 237, 3, 7, // Opcode: BCDCTSQ_rec +/* 661 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 677 +/* 666 */ MCD_OPC_CheckField, 10, 1, 1, 211, 81, 0, // Skip to: 21620 +/* 673 */ MCD_OPC_Decode, 233, 3, 8, // Opcode: BCDCFSQ_rec +/* 677 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 693 +/* 682 */ MCD_OPC_CheckField, 10, 1, 1, 195, 81, 0, // Skip to: 21620 +/* 689 */ MCD_OPC_Decode, 238, 3, 8, // Opcode: BCDCTZ_rec +/* 693 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 709 +/* 698 */ MCD_OPC_CheckField, 9, 2, 2, 179, 81, 0, // Skip to: 21620 +/* 705 */ MCD_OPC_Decode, 236, 3, 7, // Opcode: BCDCTN_rec +/* 709 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 725 +/* 714 */ MCD_OPC_CheckField, 10, 1, 1, 163, 81, 0, // Skip to: 21620 +/* 721 */ MCD_OPC_Decode, 234, 3, 8, // Opcode: BCDCFZ_rec +/* 725 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 741 +/* 730 */ MCD_OPC_CheckField, 10, 1, 1, 147, 81, 0, // Skip to: 21620 +/* 737 */ MCD_OPC_Decode, 232, 3, 8, // Opcode: BCDCFN_rec +/* 741 */ MCD_OPC_FilterValue, 31, 138, 81, 0, // Skip to: 21620 +/* 746 */ MCD_OPC_CheckField, 10, 1, 1, 131, 81, 0, // Skip to: 21620 +/* 753 */ MCD_OPC_Decode, 239, 3, 8, // Opcode: BCDSETSGN_rec +/* 757 */ MCD_OPC_FilterValue, 7, 122, 81, 0, // Skip to: 21620 +/* 762 */ MCD_OPC_CheckField, 10, 1, 1, 115, 81, 0, // Skip to: 21620 +/* 769 */ MCD_OPC_CheckField, 0, 1, 1, 108, 81, 0, // Skip to: 21620 +/* 776 */ MCD_OPC_Decode, 240, 3, 5, // Opcode: BCDSR_rec +/* 780 */ MCD_OPC_FilterValue, 1, 214, 4, 0, // Skip to: 2023 +/* 785 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 788 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 804 +/* 793 */ MCD_OPC_CheckField, 0, 1, 0, 84, 81, 0, // Skip to: 21620 +/* 800 */ MCD_OPC_Decode, 207, 15, 3, // Opcode: VMAXUB +/* 804 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 820 +/* 809 */ MCD_OPC_CheckField, 0, 1, 0, 68, 81, 0, // Skip to: 21620 +/* 816 */ MCD_OPC_Decode, 209, 15, 3, // Opcode: VMAXUH +/* 820 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 836 +/* 825 */ MCD_OPC_CheckField, 0, 1, 0, 52, 81, 0, // Skip to: 21620 +/* 832 */ MCD_OPC_Decode, 210, 15, 3, // Opcode: VMAXUW +/* 836 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 852 +/* 841 */ MCD_OPC_CheckField, 0, 1, 0, 36, 81, 0, // Skip to: 21620 +/* 848 */ MCD_OPC_Decode, 208, 15, 3, // Opcode: VMAXUD +/* 852 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 868 +/* 857 */ MCD_OPC_CheckField, 0, 1, 0, 20, 81, 0, // Skip to: 21620 +/* 864 */ MCD_OPC_Decode, 203, 15, 3, // Opcode: VMAXSB +/* 868 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 884 +/* 873 */ MCD_OPC_CheckField, 0, 1, 0, 4, 81, 0, // Skip to: 21620 +/* 880 */ MCD_OPC_Decode, 205, 15, 3, // Opcode: VMAXSH +/* 884 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 900 +/* 889 */ MCD_OPC_CheckField, 0, 1, 0, 244, 80, 0, // Skip to: 21620 +/* 896 */ MCD_OPC_Decode, 206, 15, 3, // Opcode: VMAXSW +/* 900 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 916 +/* 905 */ MCD_OPC_CheckField, 0, 1, 0, 228, 80, 0, // Skip to: 21620 +/* 912 */ MCD_OPC_Decode, 204, 15, 3, // Opcode: VMAXSD +/* 916 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 932 +/* 921 */ MCD_OPC_CheckField, 0, 1, 0, 212, 80, 0, // Skip to: 21620 +/* 928 */ MCD_OPC_Decode, 218, 15, 3, // Opcode: VMINUB +/* 932 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 948 +/* 937 */ MCD_OPC_CheckField, 0, 1, 0, 196, 80, 0, // Skip to: 21620 +/* 944 */ MCD_OPC_Decode, 220, 15, 3, // Opcode: VMINUH +/* 948 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 964 +/* 953 */ MCD_OPC_CheckField, 0, 1, 0, 180, 80, 0, // Skip to: 21620 +/* 960 */ MCD_OPC_Decode, 221, 15, 3, // Opcode: VMINUW +/* 964 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 980 +/* 969 */ MCD_OPC_CheckField, 0, 1, 0, 164, 80, 0, // Skip to: 21620 +/* 976 */ MCD_OPC_Decode, 219, 15, 3, // Opcode: VMINUD +/* 980 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 996 +/* 985 */ MCD_OPC_CheckField, 0, 1, 0, 148, 80, 0, // Skip to: 21620 +/* 992 */ MCD_OPC_Decode, 214, 15, 3, // Opcode: VMINSB +/* 996 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 1012 +/* 1001 */ MCD_OPC_CheckField, 0, 1, 0, 132, 80, 0, // Skip to: 21620 +/* 1008 */ MCD_OPC_Decode, 216, 15, 3, // Opcode: VMINSH +/* 1012 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 1028 +/* 1017 */ MCD_OPC_CheckField, 0, 1, 0, 116, 80, 0, // Skip to: 21620 +/* 1024 */ MCD_OPC_Decode, 217, 15, 3, // Opcode: VMINSW +/* 1028 */ MCD_OPC_FilterValue, 15, 11, 0, 0, // Skip to: 1044 +/* 1033 */ MCD_OPC_CheckField, 0, 1, 0, 100, 80, 0, // Skip to: 21620 +/* 1040 */ MCD_OPC_Decode, 215, 15, 3, // Opcode: VMINSD +/* 1044 */ MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 1070 +/* 1049 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1052 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1061 +/* 1057 */ MCD_OPC_Decode, 167, 14, 3, // Opcode: VAVGUB +/* 1061 */ MCD_OPC_FilterValue, 1, 74, 80, 0, // Skip to: 21620 +/* 1066 */ MCD_OPC_Decode, 143, 14, 3, // Opcode: VABSDUB +/* 1070 */ MCD_OPC_FilterValue, 17, 21, 0, 0, // Skip to: 1096 +/* 1075 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1078 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1087 +/* 1083 */ MCD_OPC_Decode, 168, 14, 3, // Opcode: VAVGUH +/* 1087 */ MCD_OPC_FilterValue, 1, 48, 80, 0, // Skip to: 21620 +/* 1092 */ MCD_OPC_Decode, 144, 14, 3, // Opcode: VABSDUH +/* 1096 */ MCD_OPC_FilterValue, 18, 21, 0, 0, // Skip to: 1122 +/* 1101 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1104 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1113 +/* 1109 */ MCD_OPC_Decode, 169, 14, 3, // Opcode: VAVGUW +/* 1113 */ MCD_OPC_FilterValue, 1, 22, 80, 0, // Skip to: 21620 +/* 1118 */ MCD_OPC_Decode, 145, 14, 3, // Opcode: VABSDUW +/* 1122 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 1138 +/* 1127 */ MCD_OPC_CheckField, 0, 1, 0, 6, 80, 0, // Skip to: 21620 +/* 1134 */ MCD_OPC_Decode, 164, 14, 3, // Opcode: VAVGSB +/* 1138 */ MCD_OPC_FilterValue, 21, 11, 0, 0, // Skip to: 1154 +/* 1143 */ MCD_OPC_CheckField, 0, 1, 0, 246, 79, 0, // Skip to: 21620 +/* 1150 */ MCD_OPC_Decode, 165, 14, 3, // Opcode: VAVGSH +/* 1154 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 1170 +/* 1159 */ MCD_OPC_CheckField, 0, 1, 0, 230, 79, 0, // Skip to: 21620 +/* 1166 */ MCD_OPC_Decode, 166, 14, 3, // Opcode: VAVGSW +/* 1170 */ MCD_OPC_FilterValue, 24, 19, 1, 0, // Skip to: 1450 +/* 1175 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 1178 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1194 +/* 1183 */ MCD_OPC_CheckField, 0, 1, 0, 206, 79, 0, // Skip to: 21620 +/* 1190 */ MCD_OPC_Decode, 185, 14, 9, // Opcode: VCLZLSBB +/* 1194 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 1210 +/* 1199 */ MCD_OPC_CheckField, 0, 1, 0, 190, 79, 0, // Skip to: 21620 +/* 1206 */ MCD_OPC_Decode, 251, 14, 9, // Opcode: VCTZLSBB +/* 1210 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 1226 +/* 1215 */ MCD_OPC_CheckField, 0, 1, 0, 174, 79, 0, // Skip to: 21620 +/* 1222 */ MCD_OPC_Decode, 147, 16, 7, // Opcode: VNEGW +/* 1226 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 1242 +/* 1231 */ MCD_OPC_CheckField, 0, 1, 0, 158, 79, 0, // Skip to: 21620 +/* 1238 */ MCD_OPC_Decode, 146, 16, 7, // Opcode: VNEGD +/* 1242 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 1258 +/* 1247 */ MCD_OPC_CheckField, 0, 1, 0, 142, 79, 0, // Skip to: 21620 +/* 1254 */ MCD_OPC_Decode, 180, 16, 7, // Opcode: VPRTYBW +/* 1258 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 1274 +/* 1263 */ MCD_OPC_CheckField, 0, 1, 0, 126, 79, 0, // Skip to: 21620 +/* 1270 */ MCD_OPC_Decode, 178, 16, 7, // Opcode: VPRTYBD +/* 1274 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 1290 +/* 1279 */ MCD_OPC_CheckField, 0, 1, 0, 110, 79, 0, // Skip to: 21620 +/* 1286 */ MCD_OPC_Decode, 179, 16, 7, // Opcode: VPRTYBQ +/* 1290 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 1306 +/* 1295 */ MCD_OPC_CheckField, 0, 1, 0, 94, 79, 0, // Skip to: 21620 +/* 1302 */ MCD_OPC_Decode, 163, 15, 7, // Opcode: VEXTSB2W +/* 1306 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 1322 +/* 1311 */ MCD_OPC_CheckField, 0, 1, 0, 78, 79, 0, // Skip to: 21620 +/* 1318 */ MCD_OPC_Decode, 168, 15, 7, // Opcode: VEXTSH2W +/* 1322 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 1338 +/* 1327 */ MCD_OPC_CheckField, 0, 1, 0, 62, 79, 0, // Skip to: 21620 +/* 1334 */ MCD_OPC_Decode, 161, 15, 7, // Opcode: VEXTSB2D +/* 1338 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 1354 +/* 1343 */ MCD_OPC_CheckField, 0, 1, 0, 46, 79, 0, // Skip to: 21620 +/* 1350 */ MCD_OPC_Decode, 166, 15, 7, // Opcode: VEXTSH2D +/* 1354 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 1370 +/* 1359 */ MCD_OPC_CheckField, 0, 1, 0, 30, 79, 0, // Skip to: 21620 +/* 1366 */ MCD_OPC_Decode, 170, 15, 7, // Opcode: VEXTSW2D +/* 1370 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 1386 +/* 1375 */ MCD_OPC_CheckField, 0, 1, 0, 14, 79, 0, // Skip to: 21620 +/* 1382 */ MCD_OPC_Decode, 165, 15, 7, // Opcode: VEXTSD2Q +/* 1386 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 1402 +/* 1391 */ MCD_OPC_CheckField, 0, 1, 0, 254, 78, 0, // Skip to: 21620 +/* 1398 */ MCD_OPC_Decode, 247, 14, 7, // Opcode: VCTZB +/* 1402 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 1418 +/* 1407 */ MCD_OPC_CheckField, 0, 1, 0, 238, 78, 0, // Skip to: 21620 +/* 1414 */ MCD_OPC_Decode, 250, 14, 7, // Opcode: VCTZH +/* 1418 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 1434 +/* 1423 */ MCD_OPC_CheckField, 0, 1, 0, 222, 78, 0, // Skip to: 21620 +/* 1430 */ MCD_OPC_Decode, 252, 14, 7, // Opcode: VCTZW +/* 1434 */ MCD_OPC_FilterValue, 31, 213, 78, 0, // Skip to: 21620 +/* 1439 */ MCD_OPC_CheckField, 0, 1, 0, 206, 78, 0, // Skip to: 21620 +/* 1446 */ MCD_OPC_Decode, 248, 14, 7, // Opcode: VCTZD +/* 1450 */ MCD_OPC_FilterValue, 25, 120, 1, 0, // Skip to: 1831 +/* 1455 */ MCD_OPC_ExtractField, 17, 4, // Inst{20-17} ... +/* 1458 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 1498 +/* 1463 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1466 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1482 +/* 1471 */ MCD_OPC_CheckField, 0, 1, 0, 174, 78, 0, // Skip to: 21620 +/* 1478 */ MCD_OPC_Decode, 138, 15, 7, // Opcode: VEXPANDBM +/* 1482 */ MCD_OPC_FilterValue, 1, 165, 78, 0, // Skip to: 21620 +/* 1487 */ MCD_OPC_CheckField, 0, 1, 0, 158, 78, 0, // Skip to: 21620 +/* 1494 */ MCD_OPC_Decode, 140, 15, 7, // Opcode: VEXPANDHM +/* 1498 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 1538 +/* 1503 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1506 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1522 +/* 1511 */ MCD_OPC_CheckField, 0, 1, 0, 134, 78, 0, // Skip to: 21620 +/* 1518 */ MCD_OPC_Decode, 142, 15, 7, // Opcode: VEXPANDWM +/* 1522 */ MCD_OPC_FilterValue, 1, 125, 78, 0, // Skip to: 21620 +/* 1527 */ MCD_OPC_CheckField, 0, 1, 0, 118, 78, 0, // Skip to: 21620 +/* 1534 */ MCD_OPC_Decode, 139, 15, 7, // Opcode: VEXPANDDM +/* 1538 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 1561 +/* 1543 */ MCD_OPC_CheckField, 16, 1, 0, 102, 78, 0, // Skip to: 21620 +/* 1550 */ MCD_OPC_CheckField, 0, 1, 0, 95, 78, 0, // Skip to: 21620 +/* 1557 */ MCD_OPC_Decode, 141, 15, 7, // Opcode: VEXPANDQM +/* 1561 */ MCD_OPC_FilterValue, 4, 35, 0, 0, // Skip to: 1601 +/* 1566 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1569 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1585 +/* 1574 */ MCD_OPC_CheckField, 0, 1, 0, 71, 78, 0, // Skip to: 21620 +/* 1581 */ MCD_OPC_Decode, 152, 15, 9, // Opcode: VEXTRACTBM +/* 1585 */ MCD_OPC_FilterValue, 1, 62, 78, 0, // Skip to: 21620 +/* 1590 */ MCD_OPC_CheckField, 0, 1, 0, 55, 78, 0, // Skip to: 21620 +/* 1597 */ MCD_OPC_Decode, 155, 15, 9, // Opcode: VEXTRACTHM +/* 1601 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 1641 +/* 1606 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1609 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1625 +/* 1614 */ MCD_OPC_CheckField, 0, 1, 0, 31, 78, 0, // Skip to: 21620 +/* 1621 */ MCD_OPC_Decode, 160, 15, 9, // Opcode: VEXTRACTWM +/* 1625 */ MCD_OPC_FilterValue, 1, 22, 78, 0, // Skip to: 21620 +/* 1630 */ MCD_OPC_CheckField, 0, 1, 0, 15, 78, 0, // Skip to: 21620 +/* 1637 */ MCD_OPC_Decode, 154, 15, 9, // Opcode: VEXTRACTDM +/* 1641 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 1664 +/* 1646 */ MCD_OPC_CheckField, 16, 1, 0, 255, 77, 0, // Skip to: 21620 +/* 1653 */ MCD_OPC_CheckField, 0, 1, 0, 248, 77, 0, // Skip to: 21620 +/* 1660 */ MCD_OPC_Decode, 156, 15, 9, // Opcode: VEXTRACTQM +/* 1664 */ MCD_OPC_FilterValue, 8, 35, 0, 0, // Skip to: 1704 +/* 1669 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1672 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1688 +/* 1677 */ MCD_OPC_CheckField, 0, 1, 0, 224, 77, 0, // Skip to: 21620 +/* 1684 */ MCD_OPC_Decode, 173, 10, 10, // Opcode: MTVSRBM +/* 1688 */ MCD_OPC_FilterValue, 1, 215, 77, 0, // Skip to: 21620 +/* 1693 */ MCD_OPC_CheckField, 0, 1, 0, 208, 77, 0, // Skip to: 21620 +/* 1700 */ MCD_OPC_Decode, 178, 10, 10, // Opcode: MTVSRHM +/* 1704 */ MCD_OPC_FilterValue, 9, 35, 0, 0, // Skip to: 1744 +/* 1709 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 1712 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1728 +/* 1717 */ MCD_OPC_CheckField, 0, 1, 0, 184, 77, 0, // Skip to: 21620 +/* 1724 */ MCD_OPC_Decode, 181, 10, 10, // Opcode: MTVSRWM +/* 1728 */ MCD_OPC_FilterValue, 1, 175, 77, 0, // Skip to: 21620 +/* 1733 */ MCD_OPC_CheckField, 0, 1, 0, 168, 77, 0, // Skip to: 21620 +/* 1740 */ MCD_OPC_Decode, 177, 10, 10, // Opcode: MTVSRDM +/* 1744 */ MCD_OPC_FilterValue, 10, 18, 0, 0, // Skip to: 1767 +/* 1749 */ MCD_OPC_CheckField, 16, 1, 0, 152, 77, 0, // Skip to: 21620 +/* 1756 */ MCD_OPC_CheckField, 0, 1, 0, 145, 77, 0, // Skip to: 21620 +/* 1763 */ MCD_OPC_Decode, 179, 10, 10, // Opcode: MTVSRQM +/* 1767 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 1783 +/* 1772 */ MCD_OPC_CheckField, 0, 1, 0, 129, 77, 0, // Skip to: 21620 +/* 1779 */ MCD_OPC_Decode, 239, 14, 11, // Opcode: VCNTMBB +/* 1783 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 1799 +/* 1788 */ MCD_OPC_CheckField, 0, 1, 0, 113, 77, 0, // Skip to: 21620 +/* 1795 */ MCD_OPC_Decode, 241, 14, 11, // Opcode: VCNTMBH +/* 1799 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 1815 +/* 1804 */ MCD_OPC_CheckField, 0, 1, 0, 97, 77, 0, // Skip to: 21620 +/* 1811 */ MCD_OPC_Decode, 242, 14, 11, // Opcode: VCNTMBW +/* 1815 */ MCD_OPC_FilterValue, 15, 88, 77, 0, // Skip to: 21620 +/* 1820 */ MCD_OPC_CheckField, 0, 1, 0, 81, 77, 0, // Skip to: 21620 +/* 1827 */ MCD_OPC_Decode, 240, 14, 11, // Opcode: VCNTMBD +/* 1831 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 1847 +/* 1836 */ MCD_OPC_CheckField, 0, 1, 0, 65, 77, 0, // Skip to: 21620 +/* 1843 */ MCD_OPC_Decode, 201, 16, 12, // Opcode: VSHASIGMAW +/* 1847 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 1863 +/* 1852 */ MCD_OPC_CheckField, 0, 1, 0, 49, 77, 0, // Skip to: 21620 +/* 1859 */ MCD_OPC_Decode, 200, 16, 12, // Opcode: VSHASIGMAD +/* 1863 */ MCD_OPC_FilterValue, 28, 35, 0, 0, // Skip to: 1903 +/* 1868 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1871 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1887 +/* 1876 */ MCD_OPC_CheckField, 16, 5, 0, 25, 77, 0, // Skip to: 21620 +/* 1883 */ MCD_OPC_Decode, 181, 14, 7, // Opcode: VCLZB +/* 1887 */ MCD_OPC_FilterValue, 1, 16, 77, 0, // Skip to: 21620 +/* 1892 */ MCD_OPC_CheckField, 16, 5, 0, 9, 77, 0, // Skip to: 21620 +/* 1899 */ MCD_OPC_Decode, 174, 16, 7, // Opcode: VPOPCNTB +/* 1903 */ MCD_OPC_FilterValue, 29, 35, 0, 0, // Skip to: 1943 +/* 1908 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1911 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1927 +/* 1916 */ MCD_OPC_CheckField, 16, 5, 0, 241, 76, 0, // Skip to: 21620 +/* 1923 */ MCD_OPC_Decode, 184, 14, 7, // Opcode: VCLZH +/* 1927 */ MCD_OPC_FilterValue, 1, 232, 76, 0, // Skip to: 21620 +/* 1932 */ MCD_OPC_CheckField, 16, 5, 0, 225, 76, 0, // Skip to: 21620 +/* 1939 */ MCD_OPC_Decode, 176, 16, 7, // Opcode: VPOPCNTH +/* 1943 */ MCD_OPC_FilterValue, 30, 35, 0, 0, // Skip to: 1983 +/* 1948 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1951 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1967 +/* 1956 */ MCD_OPC_CheckField, 16, 5, 0, 201, 76, 0, // Skip to: 21620 +/* 1963 */ MCD_OPC_Decode, 186, 14, 7, // Opcode: VCLZW +/* 1967 */ MCD_OPC_FilterValue, 1, 192, 76, 0, // Skip to: 21620 +/* 1972 */ MCD_OPC_CheckField, 16, 5, 0, 185, 76, 0, // Skip to: 21620 +/* 1979 */ MCD_OPC_Decode, 177, 16, 7, // Opcode: VPOPCNTW +/* 1983 */ MCD_OPC_FilterValue, 31, 176, 76, 0, // Skip to: 21620 +/* 1988 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1991 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 2007 +/* 1996 */ MCD_OPC_CheckField, 16, 5, 0, 161, 76, 0, // Skip to: 21620 +/* 2003 */ MCD_OPC_Decode, 182, 14, 7, // Opcode: VCLZD +/* 2007 */ MCD_OPC_FilterValue, 1, 152, 76, 0, // Skip to: 21620 +/* 2012 */ MCD_OPC_CheckField, 16, 5, 0, 145, 76, 0, // Skip to: 21620 +/* 2019 */ MCD_OPC_Decode, 175, 16, 7, // Opcode: VPOPCNTD +/* 2023 */ MCD_OPC_FilterValue, 2, 117, 2, 0, // Skip to: 2657 +/* 2028 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 2031 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2057 +/* 2036 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2039 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2048 +/* 2044 */ MCD_OPC_Decode, 186, 16, 3, // Opcode: VRLB +/* 2048 */ MCD_OPC_FilterValue, 1, 111, 76, 0, // Skip to: 21620 +/* 2053 */ MCD_OPC_Decode, 191, 16, 3, // Opcode: VRLQ +/* 2057 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 2083 +/* 2062 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2065 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2074 +/* 2070 */ MCD_OPC_Decode, 190, 16, 3, // Opcode: VRLH +/* 2074 */ MCD_OPC_FilterValue, 1, 85, 76, 0, // Skip to: 21620 +/* 2079 */ MCD_OPC_Decode, 192, 16, 13, // Opcode: VRLQMI +/* 2083 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 2109 +/* 2088 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2091 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2100 +/* 2096 */ MCD_OPC_Decode, 194, 16, 3, // Opcode: VRLW +/* 2100 */ MCD_OPC_FilterValue, 1, 59, 76, 0, // Skip to: 21620 +/* 2105 */ MCD_OPC_Decode, 195, 16, 13, // Opcode: VRLWMI +/* 2109 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 2135 +/* 2114 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2117 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2126 +/* 2122 */ MCD_OPC_Decode, 187, 16, 3, // Opcode: VRLD +/* 2126 */ MCD_OPC_FilterValue, 1, 33, 76, 0, // Skip to: 21620 +/* 2131 */ MCD_OPC_Decode, 188, 16, 13, // Opcode: VRLDMI +/* 2135 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 2161 +/* 2140 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2143 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2152 +/* 2148 */ MCD_OPC_Decode, 203, 16, 3, // Opcode: VSLB +/* 2152 */ MCD_OPC_FilterValue, 1, 7, 76, 0, // Skip to: 21620 +/* 2157 */ MCD_OPC_Decode, 209, 16, 3, // Opcode: VSLQ +/* 2161 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 2187 +/* 2166 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2169 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2178 +/* 2174 */ MCD_OPC_Decode, 207, 16, 3, // Opcode: VSLH +/* 2178 */ MCD_OPC_FilterValue, 1, 237, 75, 0, // Skip to: 21620 +/* 2183 */ MCD_OPC_Decode, 193, 16, 3, // Opcode: VRLQNM +/* 2187 */ MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 2213 +/* 2192 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2195 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2204 +/* 2200 */ MCD_OPC_Decode, 211, 16, 3, // Opcode: VSLW +/* 2204 */ MCD_OPC_FilterValue, 1, 211, 75, 0, // Skip to: 21620 +/* 2209 */ MCD_OPC_Decode, 196, 16, 3, // Opcode: VRLWNM +/* 2213 */ MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 2239 +/* 2218 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2221 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2230 +/* 2226 */ MCD_OPC_Decode, 202, 16, 3, // Opcode: VSL +/* 2230 */ MCD_OPC_FilterValue, 1, 185, 75, 0, // Skip to: 21620 +/* 2235 */ MCD_OPC_Decode, 189, 16, 3, // Opcode: VRLDNM +/* 2239 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 2265 +/* 2244 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2247 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2256 +/* 2252 */ MCD_OPC_Decode, 226, 16, 3, // Opcode: VSRB +/* 2256 */ MCD_OPC_FilterValue, 1, 159, 75, 0, // Skip to: 21620 +/* 2261 */ MCD_OPC_Decode, 231, 16, 3, // Opcode: VSRQ +/* 2265 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 2281 +/* 2270 */ MCD_OPC_CheckField, 0, 1, 0, 143, 75, 0, // Skip to: 21620 +/* 2277 */ MCD_OPC_Decode, 229, 16, 3, // Opcode: VSRH +/* 2281 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 2297 +/* 2286 */ MCD_OPC_CheckField, 0, 1, 0, 127, 75, 0, // Skip to: 21620 +/* 2293 */ MCD_OPC_Decode, 233, 16, 3, // Opcode: VSRW +/* 2297 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 2313 +/* 2302 */ MCD_OPC_CheckField, 0, 1, 0, 111, 75, 0, // Skip to: 21620 +/* 2309 */ MCD_OPC_Decode, 220, 16, 3, // Opcode: VSR +/* 2313 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 2339 +/* 2318 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2321 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2330 +/* 2326 */ MCD_OPC_Decode, 221, 16, 3, // Opcode: VSRAB +/* 2330 */ MCD_OPC_FilterValue, 1, 85, 75, 0, // Skip to: 21620 +/* 2335 */ MCD_OPC_Decode, 224, 16, 3, // Opcode: VSRAQ +/* 2339 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 2355 +/* 2344 */ MCD_OPC_CheckField, 0, 1, 0, 69, 75, 0, // Skip to: 21620 +/* 2351 */ MCD_OPC_Decode, 223, 16, 3, // Opcode: VSRAH +/* 2355 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 2371 +/* 2360 */ MCD_OPC_CheckField, 0, 1, 0, 53, 75, 0, // Skip to: 21620 +/* 2367 */ MCD_OPC_Decode, 225, 16, 3, // Opcode: VSRAW +/* 2371 */ MCD_OPC_FilterValue, 15, 11, 0, 0, // Skip to: 2387 +/* 2376 */ MCD_OPC_CheckField, 0, 1, 0, 37, 75, 0, // Skip to: 21620 +/* 2383 */ MCD_OPC_Decode, 222, 16, 3, // Opcode: VSRAD +/* 2387 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 2403 +/* 2392 */ MCD_OPC_CheckField, 0, 1, 0, 21, 75, 0, // Skip to: 21620 +/* 2399 */ MCD_OPC_Decode, 162, 14, 3, // Opcode: VAND +/* 2403 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 2419 +/* 2408 */ MCD_OPC_CheckField, 0, 1, 0, 5, 75, 0, // Skip to: 21620 +/* 2415 */ MCD_OPC_Decode, 163, 14, 3, // Opcode: VANDC +/* 2419 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 2435 +/* 2424 */ MCD_OPC_CheckField, 0, 1, 0, 245, 74, 0, // Skip to: 21620 +/* 2431 */ MCD_OPC_Decode, 150, 16, 3, // Opcode: VOR +/* 2435 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 2451 +/* 2440 */ MCD_OPC_CheckField, 0, 1, 0, 229, 74, 0, // Skip to: 21620 +/* 2447 */ MCD_OPC_Decode, 143, 17, 3, // Opcode: VXOR +/* 2451 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 2467 +/* 2456 */ MCD_OPC_CheckField, 0, 1, 0, 213, 74, 0, // Skip to: 21620 +/* 2463 */ MCD_OPC_Decode, 149, 16, 3, // Opcode: VNOR +/* 2467 */ MCD_OPC_FilterValue, 21, 11, 0, 0, // Skip to: 2483 +/* 2472 */ MCD_OPC_CheckField, 0, 1, 0, 197, 74, 0, // Skip to: 21620 +/* 2479 */ MCD_OPC_Decode, 151, 16, 3, // Opcode: VORC +/* 2483 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 2499 +/* 2488 */ MCD_OPC_CheckField, 0, 1, 0, 181, 74, 0, // Skip to: 21620 +/* 2495 */ MCD_OPC_Decode, 143, 16, 3, // Opcode: VNAND +/* 2499 */ MCD_OPC_FilterValue, 23, 11, 0, 0, // Skip to: 2515 +/* 2504 */ MCD_OPC_CheckField, 0, 1, 0, 165, 74, 0, // Skip to: 21620 +/* 2511 */ MCD_OPC_Decode, 204, 16, 3, // Opcode: VSLD +/* 2515 */ MCD_OPC_FilterValue, 24, 18, 0, 0, // Skip to: 2538 +/* 2520 */ MCD_OPC_CheckField, 11, 10, 0, 149, 74, 0, // Skip to: 21620 +/* 2527 */ MCD_OPC_CheckField, 0, 1, 0, 142, 74, 0, // Skip to: 21620 +/* 2534 */ MCD_OPC_Decode, 131, 10, 14, // Opcode: MFVSCR +/* 2538 */ MCD_OPC_FilterValue, 25, 18, 0, 0, // Skip to: 2561 +/* 2543 */ MCD_OPC_CheckField, 16, 10, 0, 126, 74, 0, // Skip to: 21620 +/* 2550 */ MCD_OPC_CheckField, 0, 1, 0, 119, 74, 0, // Skip to: 21620 +/* 2557 */ MCD_OPC_Decode, 172, 10, 15, // Opcode: MTVSCR +/* 2561 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 2577 +/* 2566 */ MCD_OPC_CheckField, 0, 1, 0, 103, 74, 0, // Skip to: 21620 +/* 2573 */ MCD_OPC_Decode, 137, 15, 3, // Opcode: VEQV +/* 2577 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 2593 +/* 2582 */ MCD_OPC_CheckField, 0, 1, 0, 87, 74, 0, // Skip to: 21620 +/* 2589 */ MCD_OPC_Decode, 227, 16, 3, // Opcode: VSRD +/* 2593 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 2609 +/* 2598 */ MCD_OPC_CheckField, 0, 1, 0, 71, 74, 0, // Skip to: 21620 +/* 2605 */ MCD_OPC_Decode, 232, 16, 3, // Opcode: VSRV +/* 2609 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 2625 +/* 2614 */ MCD_OPC_CheckField, 0, 1, 0, 55, 74, 0, // Skip to: 21620 +/* 2621 */ MCD_OPC_Decode, 210, 16, 3, // Opcode: VSLV +/* 2625 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 2641 +/* 2630 */ MCD_OPC_CheckField, 0, 1, 0, 39, 74, 0, // Skip to: 21620 +/* 2637 */ MCD_OPC_Decode, 183, 14, 3, // Opcode: VCLZDM +/* 2641 */ MCD_OPC_FilterValue, 31, 30, 74, 0, // Skip to: 21620 +/* 2646 */ MCD_OPC_CheckField, 0, 1, 0, 23, 74, 0, // Skip to: 21620 +/* 2653 */ MCD_OPC_Decode, 249, 14, 3, // Opcode: VCTZDM +/* 2657 */ MCD_OPC_FilterValue, 3, 183, 2, 0, // Skip to: 3357 +/* 2662 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 2665 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2691 +/* 2670 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2673 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2682 +/* 2678 */ MCD_OPC_Decode, 191, 14, 3, // Opcode: VCMPEQUB +/* 2682 */ MCD_OPC_FilterValue, 1, 245, 73, 0, // Skip to: 21620 +/* 2687 */ MCD_OPC_Decode, 225, 14, 3, // Opcode: VCMPNEB +/* 2691 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 2717 +/* 2696 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2699 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2708 +/* 2704 */ MCD_OPC_Decode, 195, 14, 3, // Opcode: VCMPEQUH +/* 2708 */ MCD_OPC_FilterValue, 1, 219, 73, 0, // Skip to: 21620 +/* 2713 */ MCD_OPC_Decode, 227, 14, 3, // Opcode: VCMPNEH +/* 2717 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 2743 +/* 2722 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2725 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2734 +/* 2730 */ MCD_OPC_Decode, 199, 14, 3, // Opcode: VCMPEQUW +/* 2734 */ MCD_OPC_FilterValue, 1, 193, 73, 0, // Skip to: 21620 +/* 2739 */ MCD_OPC_Decode, 229, 14, 3, // Opcode: VCMPNEW +/* 2743 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 2769 +/* 2748 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2751 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2760 +/* 2756 */ MCD_OPC_Decode, 189, 14, 3, // Opcode: VCMPEQFP +/* 2760 */ MCD_OPC_FilterValue, 1, 167, 73, 0, // Skip to: 21620 +/* 2765 */ MCD_OPC_Decode, 193, 14, 3, // Opcode: VCMPEQUD +/* 2769 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 2785 +/* 2774 */ MCD_OPC_CheckField, 0, 1, 1, 151, 73, 0, // Skip to: 21620 +/* 2781 */ MCD_OPC_Decode, 231, 14, 3, // Opcode: VCMPNEZB +/* 2785 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 2801 +/* 2790 */ MCD_OPC_CheckField, 0, 1, 1, 135, 73, 0, // Skip to: 21620 +/* 2797 */ MCD_OPC_Decode, 233, 14, 3, // Opcode: VCMPNEZH +/* 2801 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 2817 +/* 2806 */ MCD_OPC_CheckField, 0, 1, 1, 119, 73, 0, // Skip to: 21620 +/* 2813 */ MCD_OPC_Decode, 235, 14, 3, // Opcode: VCMPNEZW +/* 2817 */ MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 2843 +/* 2822 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2825 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2834 +/* 2830 */ MCD_OPC_Decode, 201, 14, 3, // Opcode: VCMPGEFP +/* 2834 */ MCD_OPC_FilterValue, 1, 93, 73, 0, // Skip to: 21620 +/* 2839 */ MCD_OPC_Decode, 197, 14, 3, // Opcode: VCMPEQUQ +/* 2843 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 2859 +/* 2848 */ MCD_OPC_CheckField, 0, 1, 0, 77, 73, 0, // Skip to: 21620 +/* 2855 */ MCD_OPC_Decode, 215, 14, 3, // Opcode: VCMPGTUB +/* 2859 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 2875 +/* 2864 */ MCD_OPC_CheckField, 0, 1, 0, 61, 73, 0, // Skip to: 21620 +/* 2871 */ MCD_OPC_Decode, 219, 14, 3, // Opcode: VCMPGTUH +/* 2875 */ MCD_OPC_FilterValue, 10, 21, 0, 0, // Skip to: 2901 +/* 2880 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2883 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2892 +/* 2888 */ MCD_OPC_Decode, 223, 14, 3, // Opcode: VCMPGTUW +/* 2892 */ MCD_OPC_FilterValue, 1, 35, 73, 0, // Skip to: 21620 +/* 2897 */ MCD_OPC_Decode, 221, 14, 3, // Opcode: VCMPGTUQ +/* 2901 */ MCD_OPC_FilterValue, 11, 21, 0, 0, // Skip to: 2927 +/* 2906 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2909 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2918 +/* 2914 */ MCD_OPC_Decode, 203, 14, 3, // Opcode: VCMPGTFP +/* 2918 */ MCD_OPC_FilterValue, 1, 9, 73, 0, // Skip to: 21620 +/* 2923 */ MCD_OPC_Decode, 217, 14, 3, // Opcode: VCMPGTUD +/* 2927 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 2943 +/* 2932 */ MCD_OPC_CheckField, 0, 1, 0, 249, 72, 0, // Skip to: 21620 +/* 2939 */ MCD_OPC_Decode, 205, 14, 3, // Opcode: VCMPGTSB +/* 2943 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 2959 +/* 2948 */ MCD_OPC_CheckField, 0, 1, 0, 233, 72, 0, // Skip to: 21620 +/* 2955 */ MCD_OPC_Decode, 209, 14, 3, // Opcode: VCMPGTSH +/* 2959 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 2985 +/* 2964 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2967 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2976 +/* 2972 */ MCD_OPC_Decode, 213, 14, 3, // Opcode: VCMPGTSW +/* 2976 */ MCD_OPC_FilterValue, 1, 207, 72, 0, // Skip to: 21620 +/* 2981 */ MCD_OPC_Decode, 211, 14, 3, // Opcode: VCMPGTSQ +/* 2985 */ MCD_OPC_FilterValue, 15, 21, 0, 0, // Skip to: 3011 +/* 2990 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 2993 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3002 +/* 2998 */ MCD_OPC_Decode, 187, 14, 3, // Opcode: VCMPBFP +/* 3002 */ MCD_OPC_FilterValue, 1, 181, 72, 0, // Skip to: 21620 +/* 3007 */ MCD_OPC_Decode, 207, 14, 3, // Opcode: VCMPGTSD +/* 3011 */ MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 3037 +/* 3016 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3019 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3028 +/* 3024 */ MCD_OPC_Decode, 192, 14, 3, // Opcode: VCMPEQUB_rec +/* 3028 */ MCD_OPC_FilterValue, 1, 155, 72, 0, // Skip to: 21620 +/* 3033 */ MCD_OPC_Decode, 226, 14, 3, // Opcode: VCMPNEB_rec +/* 3037 */ MCD_OPC_FilterValue, 17, 21, 0, 0, // Skip to: 3063 +/* 3042 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3045 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3054 +/* 3050 */ MCD_OPC_Decode, 196, 14, 3, // Opcode: VCMPEQUH_rec +/* 3054 */ MCD_OPC_FilterValue, 1, 129, 72, 0, // Skip to: 21620 +/* 3059 */ MCD_OPC_Decode, 228, 14, 3, // Opcode: VCMPNEH_rec +/* 3063 */ MCD_OPC_FilterValue, 18, 21, 0, 0, // Skip to: 3089 +/* 3068 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3071 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3080 +/* 3076 */ MCD_OPC_Decode, 200, 14, 3, // Opcode: VCMPEQUW_rec +/* 3080 */ MCD_OPC_FilterValue, 1, 103, 72, 0, // Skip to: 21620 +/* 3085 */ MCD_OPC_Decode, 230, 14, 3, // Opcode: VCMPNEW_rec +/* 3089 */ MCD_OPC_FilterValue, 19, 21, 0, 0, // Skip to: 3115 +/* 3094 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3097 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3106 +/* 3102 */ MCD_OPC_Decode, 190, 14, 3, // Opcode: VCMPEQFP_rec +/* 3106 */ MCD_OPC_FilterValue, 1, 77, 72, 0, // Skip to: 21620 +/* 3111 */ MCD_OPC_Decode, 194, 14, 3, // Opcode: VCMPEQUD_rec +/* 3115 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 3131 +/* 3120 */ MCD_OPC_CheckField, 0, 1, 1, 61, 72, 0, // Skip to: 21620 +/* 3127 */ MCD_OPC_Decode, 232, 14, 3, // Opcode: VCMPNEZB_rec +/* 3131 */ MCD_OPC_FilterValue, 21, 11, 0, 0, // Skip to: 3147 +/* 3136 */ MCD_OPC_CheckField, 0, 1, 1, 45, 72, 0, // Skip to: 21620 +/* 3143 */ MCD_OPC_Decode, 234, 14, 3, // Opcode: VCMPNEZH_rec +/* 3147 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 3163 +/* 3152 */ MCD_OPC_CheckField, 0, 1, 1, 29, 72, 0, // Skip to: 21620 +/* 3159 */ MCD_OPC_Decode, 236, 14, 3, // Opcode: VCMPNEZW_rec +/* 3163 */ MCD_OPC_FilterValue, 23, 21, 0, 0, // Skip to: 3189 +/* 3168 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3171 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3180 +/* 3176 */ MCD_OPC_Decode, 202, 14, 3, // Opcode: VCMPGEFP_rec +/* 3180 */ MCD_OPC_FilterValue, 1, 3, 72, 0, // Skip to: 21620 +/* 3185 */ MCD_OPC_Decode, 198, 14, 3, // Opcode: VCMPEQUQ_rec +/* 3189 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 3205 +/* 3194 */ MCD_OPC_CheckField, 0, 1, 0, 243, 71, 0, // Skip to: 21620 +/* 3201 */ MCD_OPC_Decode, 216, 14, 3, // Opcode: VCMPGTUB_rec +/* 3205 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 3221 +/* 3210 */ MCD_OPC_CheckField, 0, 1, 0, 227, 71, 0, // Skip to: 21620 +/* 3217 */ MCD_OPC_Decode, 220, 14, 3, // Opcode: VCMPGTUH_rec +/* 3221 */ MCD_OPC_FilterValue, 26, 21, 0, 0, // Skip to: 3247 +/* 3226 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3229 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3238 +/* 3234 */ MCD_OPC_Decode, 224, 14, 3, // Opcode: VCMPGTUW_rec +/* 3238 */ MCD_OPC_FilterValue, 1, 201, 71, 0, // Skip to: 21620 +/* 3243 */ MCD_OPC_Decode, 222, 14, 3, // Opcode: VCMPGTUQ_rec +/* 3247 */ MCD_OPC_FilterValue, 27, 21, 0, 0, // Skip to: 3273 +/* 3252 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3255 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3264 +/* 3260 */ MCD_OPC_Decode, 204, 14, 3, // Opcode: VCMPGTFP_rec +/* 3264 */ MCD_OPC_FilterValue, 1, 175, 71, 0, // Skip to: 21620 +/* 3269 */ MCD_OPC_Decode, 218, 14, 3, // Opcode: VCMPGTUD_rec +/* 3273 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 3289 +/* 3278 */ MCD_OPC_CheckField, 0, 1, 0, 159, 71, 0, // Skip to: 21620 +/* 3285 */ MCD_OPC_Decode, 206, 14, 3, // Opcode: VCMPGTSB_rec +/* 3289 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 3305 +/* 3294 */ MCD_OPC_CheckField, 0, 1, 0, 143, 71, 0, // Skip to: 21620 +/* 3301 */ MCD_OPC_Decode, 210, 14, 3, // Opcode: VCMPGTSH_rec +/* 3305 */ MCD_OPC_FilterValue, 30, 21, 0, 0, // Skip to: 3331 +/* 3310 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3313 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3322 +/* 3318 */ MCD_OPC_Decode, 214, 14, 3, // Opcode: VCMPGTSW_rec +/* 3322 */ MCD_OPC_FilterValue, 1, 117, 71, 0, // Skip to: 21620 +/* 3327 */ MCD_OPC_Decode, 212, 14, 3, // Opcode: VCMPGTSQ_rec +/* 3331 */ MCD_OPC_FilterValue, 31, 108, 71, 0, // Skip to: 21620 +/* 3336 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3339 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3348 +/* 3344 */ MCD_OPC_Decode, 188, 14, 3, // Opcode: VCMPBFP_rec +/* 3348 */ MCD_OPC_FilterValue, 1, 91, 71, 0, // Skip to: 21620 +/* 3353 */ MCD_OPC_Decode, 208, 14, 3, // Opcode: VCMPGTSD_rec +/* 3357 */ MCD_OPC_FilterValue, 4, 26, 2, 0, // Skip to: 3900 +/* 3362 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3365 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3381 +/* 3370 */ MCD_OPC_CheckField, 0, 1, 0, 67, 71, 0, // Skip to: 21620 +/* 3377 */ MCD_OPC_Decode, 138, 16, 3, // Opcode: VMULOUB +/* 3381 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 3397 +/* 3386 */ MCD_OPC_CheckField, 0, 1, 0, 51, 71, 0, // Skip to: 21620 +/* 3393 */ MCD_OPC_Decode, 140, 16, 3, // Opcode: VMULOUH +/* 3397 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 3423 +/* 3402 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3405 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3414 +/* 3410 */ MCD_OPC_Decode, 141, 16, 3, // Opcode: VMULOUW +/* 3414 */ MCD_OPC_FilterValue, 1, 25, 71, 0, // Skip to: 21620 +/* 3419 */ MCD_OPC_Decode, 142, 16, 3, // Opcode: VMULUWM +/* 3423 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 3439 +/* 3428 */ MCD_OPC_CheckField, 0, 1, 0, 9, 71, 0, // Skip to: 21620 +/* 3435 */ MCD_OPC_Decode, 139, 16, 3, // Opcode: VMULOUD +/* 3439 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 3455 +/* 3444 */ MCD_OPC_CheckField, 0, 1, 0, 249, 70, 0, // Skip to: 21620 +/* 3451 */ MCD_OPC_Decode, 134, 16, 3, // Opcode: VMULOSB +/* 3455 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 3471 +/* 3460 */ MCD_OPC_CheckField, 0, 1, 0, 233, 70, 0, // Skip to: 21620 +/* 3467 */ MCD_OPC_Decode, 136, 16, 3, // Opcode: VMULOSH +/* 3471 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 3487 +/* 3476 */ MCD_OPC_CheckField, 0, 1, 0, 217, 70, 0, // Skip to: 21620 +/* 3483 */ MCD_OPC_Decode, 137, 16, 3, // Opcode: VMULOSW +/* 3487 */ MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 3513 +/* 3492 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3495 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3504 +/* 3500 */ MCD_OPC_Decode, 135, 16, 3, // Opcode: VMULOSD +/* 3504 */ MCD_OPC_FilterValue, 1, 191, 70, 0, // Skip to: 21620 +/* 3509 */ MCD_OPC_Decode, 133, 16, 3, // Opcode: VMULLD +/* 3513 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 3529 +/* 3518 */ MCD_OPC_CheckField, 0, 1, 0, 175, 70, 0, // Skip to: 21620 +/* 3525 */ MCD_OPC_Decode, 253, 15, 3, // Opcode: VMULEUB +/* 3529 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 3545 +/* 3534 */ MCD_OPC_CheckField, 0, 1, 0, 159, 70, 0, // Skip to: 21620 +/* 3541 */ MCD_OPC_Decode, 255, 15, 3, // Opcode: VMULEUH +/* 3545 */ MCD_OPC_FilterValue, 10, 21, 0, 0, // Skip to: 3571 +/* 3550 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3553 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3562 +/* 3558 */ MCD_OPC_Decode, 128, 16, 3, // Opcode: VMULEUW +/* 3562 */ MCD_OPC_FilterValue, 1, 133, 70, 0, // Skip to: 21620 +/* 3567 */ MCD_OPC_Decode, 132, 16, 3, // Opcode: VMULHUW +/* 3571 */ MCD_OPC_FilterValue, 11, 21, 0, 0, // Skip to: 3597 +/* 3576 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3579 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3588 +/* 3584 */ MCD_OPC_Decode, 254, 15, 3, // Opcode: VMULEUD +/* 3588 */ MCD_OPC_FilterValue, 1, 107, 70, 0, // Skip to: 21620 +/* 3593 */ MCD_OPC_Decode, 131, 16, 3, // Opcode: VMULHUD +/* 3597 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 3613 +/* 3602 */ MCD_OPC_CheckField, 0, 1, 0, 91, 70, 0, // Skip to: 21620 +/* 3609 */ MCD_OPC_Decode, 249, 15, 3, // Opcode: VMULESB +/* 3613 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 3629 +/* 3618 */ MCD_OPC_CheckField, 0, 1, 0, 75, 70, 0, // Skip to: 21620 +/* 3625 */ MCD_OPC_Decode, 251, 15, 3, // Opcode: VMULESH +/* 3629 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 3655 +/* 3634 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3637 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3646 +/* 3642 */ MCD_OPC_Decode, 252, 15, 3, // Opcode: VMULESW +/* 3646 */ MCD_OPC_FilterValue, 1, 49, 70, 0, // Skip to: 21620 +/* 3651 */ MCD_OPC_Decode, 130, 16, 3, // Opcode: VMULHSW +/* 3655 */ MCD_OPC_FilterValue, 15, 21, 0, 0, // Skip to: 3681 +/* 3660 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3663 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3672 +/* 3668 */ MCD_OPC_Decode, 250, 15, 3, // Opcode: VMULESD +/* 3672 */ MCD_OPC_FilterValue, 1, 23, 70, 0, // Skip to: 21620 +/* 3677 */ MCD_OPC_Decode, 129, 16, 3, // Opcode: VMULHSD +/* 3681 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 3697 +/* 3686 */ MCD_OPC_CheckField, 0, 1, 0, 7, 70, 0, // Skip to: 21620 +/* 3693 */ MCD_OPC_Decode, 170, 16, 3, // Opcode: VPMSUMB +/* 3697 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 3713 +/* 3702 */ MCD_OPC_CheckField, 0, 1, 0, 247, 69, 0, // Skip to: 21620 +/* 3709 */ MCD_OPC_Decode, 172, 16, 3, // Opcode: VPMSUMH +/* 3713 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 3729 +/* 3718 */ MCD_OPC_CheckField, 0, 1, 0, 231, 69, 0, // Skip to: 21620 +/* 3725 */ MCD_OPC_Decode, 173, 16, 3, // Opcode: VPMSUMW +/* 3729 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 3745 +/* 3734 */ MCD_OPC_CheckField, 0, 1, 0, 215, 69, 0, // Skip to: 21620 +/* 3741 */ MCD_OPC_Decode, 171, 16, 3, // Opcode: VPMSUMD +/* 3745 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 3771 +/* 3750 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3753 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3762 +/* 3758 */ MCD_OPC_Decode, 177, 14, 3, // Opcode: VCIPHER +/* 3762 */ MCD_OPC_FilterValue, 1, 189, 69, 0, // Skip to: 21620 +/* 3767 */ MCD_OPC_Decode, 178, 14, 3, // Opcode: VCIPHERLAST +/* 3771 */ MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 3797 +/* 3776 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3779 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3788 +/* 3784 */ MCD_OPC_Decode, 144, 16, 3, // Opcode: VNCIPHER +/* 3788 */ MCD_OPC_FilterValue, 1, 163, 69, 0, // Skip to: 21620 +/* 3793 */ MCD_OPC_Decode, 145, 16, 3, // Opcode: VNCIPHERLAST +/* 3797 */ MCD_OPC_FilterValue, 23, 18, 0, 0, // Skip to: 3820 +/* 3802 */ MCD_OPC_CheckField, 11, 5, 0, 147, 69, 0, // Skip to: 21620 +/* 3809 */ MCD_OPC_CheckField, 0, 1, 0, 140, 69, 0, // Skip to: 21620 +/* 3816 */ MCD_OPC_Decode, 198, 16, 4, // Opcode: VSBOX +/* 3820 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 3836 +/* 3825 */ MCD_OPC_CheckField, 0, 1, 0, 124, 69, 0, // Skip to: 21620 +/* 3832 */ MCD_OPC_Decode, 133, 17, 3, // Opcode: VSUM4UBS +/* 3836 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 3852 +/* 3841 */ MCD_OPC_CheckField, 0, 1, 0, 108, 69, 0, // Skip to: 21620 +/* 3848 */ MCD_OPC_Decode, 132, 17, 3, // Opcode: VSUM4SHS +/* 3852 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 3868 +/* 3857 */ MCD_OPC_CheckField, 0, 1, 0, 92, 69, 0, // Skip to: 21620 +/* 3864 */ MCD_OPC_Decode, 130, 17, 3, // Opcode: VSUM2SWS +/* 3868 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 3884 +/* 3873 */ MCD_OPC_CheckField, 0, 1, 0, 76, 69, 0, // Skip to: 21620 +/* 3880 */ MCD_OPC_Decode, 131, 17, 3, // Opcode: VSUM4SBS +/* 3884 */ MCD_OPC_FilterValue, 30, 67, 69, 0, // Skip to: 21620 +/* 3889 */ MCD_OPC_CheckField, 0, 1, 0, 60, 69, 0, // Skip to: 21620 +/* 3896 */ MCD_OPC_Decode, 134, 17, 3, // Opcode: VSUMSWS +/* 3900 */ MCD_OPC_FilterValue, 5, 31, 2, 0, // Skip to: 4448 +/* 3905 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 3908 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 3934 +/* 3913 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3916 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3925 +/* 3921 */ MCD_OPC_Decode, 150, 14, 3, // Opcode: VADDFP +/* 3925 */ MCD_OPC_FilterValue, 1, 26, 69, 0, // Skip to: 21620 +/* 3930 */ MCD_OPC_Decode, 135, 15, 3, // Opcode: VDIVUQ +/* 3934 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 3950 +/* 3939 */ MCD_OPC_CheckField, 0, 1, 0, 10, 69, 0, // Skip to: 21620 +/* 3946 */ MCD_OPC_Decode, 246, 16, 3, // Opcode: VSUBFP +/* 3950 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 3966 +/* 3955 */ MCD_OPC_CheckField, 0, 1, 1, 250, 68, 0, // Skip to: 21620 +/* 3962 */ MCD_OPC_Decode, 136, 15, 3, // Opcode: VDIVUW +/* 3966 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 3982 +/* 3971 */ MCD_OPC_CheckField, 0, 1, 1, 234, 68, 0, // Skip to: 21620 +/* 3978 */ MCD_OPC_Decode, 134, 15, 3, // Opcode: VDIVUD +/* 3982 */ MCD_OPC_FilterValue, 4, 28, 0, 0, // Skip to: 4015 +/* 3987 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 3990 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4006 +/* 3995 */ MCD_OPC_CheckField, 16, 5, 0, 210, 68, 0, // Skip to: 21620 +/* 4002 */ MCD_OPC_Decode, 181, 16, 7, // Opcode: VREFP +/* 4006 */ MCD_OPC_FilterValue, 1, 201, 68, 0, // Skip to: 21620 +/* 4011 */ MCD_OPC_Decode, 132, 15, 3, // Opcode: VDIVSQ +/* 4015 */ MCD_OPC_FilterValue, 5, 18, 0, 0, // Skip to: 4038 +/* 4020 */ MCD_OPC_CheckField, 16, 5, 0, 185, 68, 0, // Skip to: 21620 +/* 4027 */ MCD_OPC_CheckField, 0, 1, 0, 178, 68, 0, // Skip to: 21620 +/* 4034 */ MCD_OPC_Decode, 197, 16, 7, // Opcode: VRSQRTEFP +/* 4038 */ MCD_OPC_FilterValue, 6, 28, 0, 0, // Skip to: 4071 +/* 4043 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4046 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4062 +/* 4051 */ MCD_OPC_CheckField, 16, 5, 0, 154, 68, 0, // Skip to: 21620 +/* 4058 */ MCD_OPC_Decode, 143, 15, 7, // Opcode: VEXPTEFP +/* 4062 */ MCD_OPC_FilterValue, 1, 145, 68, 0, // Skip to: 21620 +/* 4067 */ MCD_OPC_Decode, 133, 15, 3, // Opcode: VDIVSW +/* 4071 */ MCD_OPC_FilterValue, 7, 28, 0, 0, // Skip to: 4104 +/* 4076 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4079 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4095 +/* 4084 */ MCD_OPC_CheckField, 16, 5, 0, 121, 68, 0, // Skip to: 21620 +/* 4091 */ MCD_OPC_Decode, 200, 15, 7, // Opcode: VLOGEFP +/* 4095 */ MCD_OPC_FilterValue, 1, 112, 68, 0, // Skip to: 21620 +/* 4100 */ MCD_OPC_Decode, 131, 15, 3, // Opcode: VDIVSD +/* 4104 */ MCD_OPC_FilterValue, 8, 28, 0, 0, // Skip to: 4137 +/* 4109 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4112 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4128 +/* 4117 */ MCD_OPC_CheckField, 16, 5, 0, 88, 68, 0, // Skip to: 21620 +/* 4124 */ MCD_OPC_Decode, 183, 16, 7, // Opcode: VRFIN +/* 4128 */ MCD_OPC_FilterValue, 1, 79, 68, 0, // Skip to: 21620 +/* 4133 */ MCD_OPC_Decode, 129, 15, 3, // Opcode: VDIVEUQ +/* 4137 */ MCD_OPC_FilterValue, 9, 18, 0, 0, // Skip to: 4160 +/* 4142 */ MCD_OPC_CheckField, 16, 5, 0, 63, 68, 0, // Skip to: 21620 +/* 4149 */ MCD_OPC_CheckField, 0, 1, 0, 56, 68, 0, // Skip to: 21620 +/* 4156 */ MCD_OPC_Decode, 185, 16, 7, // Opcode: VRFIZ +/* 4160 */ MCD_OPC_FilterValue, 10, 28, 0, 0, // Skip to: 4193 +/* 4165 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4168 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4184 +/* 4173 */ MCD_OPC_CheckField, 16, 5, 0, 32, 68, 0, // Skip to: 21620 +/* 4180 */ MCD_OPC_Decode, 184, 16, 7, // Opcode: VRFIP +/* 4184 */ MCD_OPC_FilterValue, 1, 23, 68, 0, // Skip to: 21620 +/* 4189 */ MCD_OPC_Decode, 130, 15, 3, // Opcode: VDIVEUW +/* 4193 */ MCD_OPC_FilterValue, 11, 28, 0, 0, // Skip to: 4226 +/* 4198 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4201 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4217 +/* 4206 */ MCD_OPC_CheckField, 16, 5, 0, 255, 67, 0, // Skip to: 21620 +/* 4213 */ MCD_OPC_Decode, 182, 16, 7, // Opcode: VRFIM +/* 4217 */ MCD_OPC_FilterValue, 1, 246, 67, 0, // Skip to: 21620 +/* 4222 */ MCD_OPC_Decode, 128, 15, 3, // Opcode: VDIVEUD +/* 4226 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 4252 +/* 4231 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4234 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4243 +/* 4239 */ MCD_OPC_Decode, 175, 14, 16, // Opcode: VCFUX +/* 4243 */ MCD_OPC_FilterValue, 1, 220, 67, 0, // Skip to: 21620 +/* 4248 */ MCD_OPC_Decode, 254, 14, 3, // Opcode: VDIVESQ +/* 4252 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 4268 +/* 4257 */ MCD_OPC_CheckField, 0, 1, 0, 204, 67, 0, // Skip to: 21620 +/* 4264 */ MCD_OPC_Decode, 172, 14, 16, // Opcode: VCFSX +/* 4268 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 4294 +/* 4273 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4276 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4285 +/* 4281 */ MCD_OPC_Decode, 245, 14, 16, // Opcode: VCTUXS +/* 4285 */ MCD_OPC_FilterValue, 1, 178, 67, 0, // Skip to: 21620 +/* 4290 */ MCD_OPC_Decode, 255, 14, 3, // Opcode: VDIVESW +/* 4294 */ MCD_OPC_FilterValue, 15, 21, 0, 0, // Skip to: 4320 +/* 4299 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4302 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4311 +/* 4307 */ MCD_OPC_Decode, 243, 14, 16, // Opcode: VCTSXS +/* 4311 */ MCD_OPC_FilterValue, 1, 152, 67, 0, // Skip to: 21620 +/* 4316 */ MCD_OPC_Decode, 253, 14, 3, // Opcode: VDIVESD +/* 4320 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 4336 +/* 4325 */ MCD_OPC_CheckField, 0, 1, 0, 136, 67, 0, // Skip to: 21620 +/* 4332 */ MCD_OPC_Decode, 202, 15, 3, // Opcode: VMAXFP +/* 4336 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 4352 +/* 4341 */ MCD_OPC_CheckField, 0, 1, 0, 120, 67, 0, // Skip to: 21620 +/* 4348 */ MCD_OPC_Decode, 213, 15, 3, // Opcode: VMINFP +/* 4352 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 4368 +/* 4357 */ MCD_OPC_CheckField, 0, 1, 1, 104, 67, 0, // Skip to: 21620 +/* 4364 */ MCD_OPC_Decode, 227, 15, 3, // Opcode: VMODUQ +/* 4368 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 4384 +/* 4373 */ MCD_OPC_CheckField, 0, 1, 1, 88, 67, 0, // Skip to: 21620 +/* 4380 */ MCD_OPC_Decode, 228, 15, 3, // Opcode: VMODUW +/* 4384 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 4400 +/* 4389 */ MCD_OPC_CheckField, 0, 1, 1, 72, 67, 0, // Skip to: 21620 +/* 4396 */ MCD_OPC_Decode, 226, 15, 3, // Opcode: VMODUD +/* 4400 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 4416 +/* 4405 */ MCD_OPC_CheckField, 0, 1, 1, 56, 67, 0, // Skip to: 21620 +/* 4412 */ MCD_OPC_Decode, 224, 15, 3, // Opcode: VMODSQ +/* 4416 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 4432 +/* 4421 */ MCD_OPC_CheckField, 0, 1, 1, 40, 67, 0, // Skip to: 21620 +/* 4428 */ MCD_OPC_Decode, 225, 15, 3, // Opcode: VMODSW +/* 4432 */ MCD_OPC_FilterValue, 31, 31, 67, 0, // Skip to: 21620 +/* 4437 */ MCD_OPC_CheckField, 0, 1, 1, 24, 67, 0, // Skip to: 21620 +/* 4444 */ MCD_OPC_Decode, 223, 15, 3, // Opcode: VMODSD +/* 4448 */ MCD_OPC_FilterValue, 6, 174, 2, 0, // Skip to: 5139 +/* 4453 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 4456 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 4517 +/* 4461 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4464 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4473 +/* 4469 */ MCD_OPC_Decode, 230, 15, 3, // Opcode: VMRGHB +/* 4473 */ MCD_OPC_FilterValue, 1, 246, 66, 0, // Skip to: 21620 +/* 4478 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 4481 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4490 +/* 4486 */ MCD_OPC_Decode, 234, 16, 7, // Opcode: VSTRIBL +/* 4490 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4499 +/* 4495 */ MCD_OPC_Decode, 236, 16, 7, // Opcode: VSTRIBR +/* 4499 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4508 +/* 4504 */ MCD_OPC_Decode, 238, 16, 7, // Opcode: VSTRIHL +/* 4508 */ MCD_OPC_FilterValue, 3, 211, 66, 0, // Skip to: 21620 +/* 4513 */ MCD_OPC_Decode, 240, 16, 7, // Opcode: VSTRIHR +/* 4517 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 4533 +/* 4522 */ MCD_OPC_CheckField, 0, 1, 0, 195, 66, 0, // Skip to: 21620 +/* 4529 */ MCD_OPC_Decode, 231, 15, 3, // Opcode: VMRGHH +/* 4533 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 4549 +/* 4538 */ MCD_OPC_CheckField, 0, 1, 0, 179, 66, 0, // Skip to: 21620 +/* 4545 */ MCD_OPC_Decode, 232, 15, 3, // Opcode: VMRGHW +/* 4549 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 4565 +/* 4554 */ MCD_OPC_CheckField, 0, 1, 0, 163, 66, 0, // Skip to: 21620 +/* 4561 */ MCD_OPC_Decode, 233, 15, 3, // Opcode: VMRGLB +/* 4565 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 4581 +/* 4570 */ MCD_OPC_CheckField, 0, 1, 0, 147, 66, 0, // Skip to: 21620 +/* 4577 */ MCD_OPC_Decode, 234, 15, 3, // Opcode: VMRGLH +/* 4581 */ MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 4607 +/* 4586 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4589 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4598 +/* 4594 */ MCD_OPC_Decode, 235, 15, 3, // Opcode: VMRGLW +/* 4598 */ MCD_OPC_FilterValue, 1, 121, 66, 0, // Skip to: 21620 +/* 4603 */ MCD_OPC_Decode, 179, 14, 17, // Opcode: VCLRLB +/* 4607 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 4623 +/* 4612 */ MCD_OPC_CheckField, 0, 1, 1, 105, 66, 0, // Skip to: 21620 +/* 4619 */ MCD_OPC_Decode, 180, 14, 17, // Opcode: VCLRRB +/* 4623 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 4649 +/* 4628 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4631 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4640 +/* 4636 */ MCD_OPC_Decode, 212, 16, 16, // Opcode: VSPLTB +/* 4640 */ MCD_OPC_FilterValue, 1, 79, 66, 0, // Skip to: 21620 +/* 4645 */ MCD_OPC_Decode, 157, 15, 18, // Opcode: VEXTRACTUB +/* 4649 */ MCD_OPC_FilterValue, 9, 21, 0, 0, // Skip to: 4675 +/* 4654 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4657 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4666 +/* 4662 */ MCD_OPC_Decode, 214, 16, 16, // Opcode: VSPLTH +/* 4666 */ MCD_OPC_FilterValue, 1, 53, 66, 0, // Skip to: 21620 +/* 4671 */ MCD_OPC_Decode, 158, 15, 18, // Opcode: VEXTRACTUH +/* 4675 */ MCD_OPC_FilterValue, 10, 21, 0, 0, // Skip to: 4701 +/* 4680 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4683 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4692 +/* 4688 */ MCD_OPC_Decode, 219, 16, 16, // Opcode: VSPLTW +/* 4692 */ MCD_OPC_FilterValue, 1, 27, 66, 0, // Skip to: 21620 +/* 4697 */ MCD_OPC_Decode, 159, 15, 18, // Opcode: VEXTRACTUW +/* 4701 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 4717 +/* 4706 */ MCD_OPC_CheckField, 0, 1, 1, 11, 66, 0, // Skip to: 21620 +/* 4713 */ MCD_OPC_Decode, 153, 15, 18, // Opcode: VEXTRACTD +/* 4717 */ MCD_OPC_FilterValue, 12, 28, 0, 0, // Skip to: 4750 +/* 4722 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4725 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4741 +/* 4730 */ MCD_OPC_CheckField, 11, 5, 0, 243, 65, 0, // Skip to: 21620 +/* 4737 */ MCD_OPC_Decode, 216, 16, 19, // Opcode: VSPLTISB +/* 4741 */ MCD_OPC_FilterValue, 1, 234, 65, 0, // Skip to: 21620 +/* 4746 */ MCD_OPC_Decode, 187, 15, 20, // Opcode: VINSERTB +/* 4750 */ MCD_OPC_FilterValue, 13, 28, 0, 0, // Skip to: 4783 +/* 4755 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4758 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4774 +/* 4763 */ MCD_OPC_CheckField, 11, 5, 0, 210, 65, 0, // Skip to: 21620 +/* 4770 */ MCD_OPC_Decode, 217, 16, 19, // Opcode: VSPLTISH +/* 4774 */ MCD_OPC_FilterValue, 1, 201, 65, 0, // Skip to: 21620 +/* 4779 */ MCD_OPC_Decode, 189, 15, 20, // Opcode: VINSERTH +/* 4783 */ MCD_OPC_FilterValue, 14, 28, 0, 0, // Skip to: 4816 +/* 4788 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4791 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4807 +/* 4796 */ MCD_OPC_CheckField, 11, 5, 0, 177, 65, 0, // Skip to: 21620 +/* 4803 */ MCD_OPC_Decode, 218, 16, 19, // Opcode: VSPLTISW +/* 4807 */ MCD_OPC_FilterValue, 1, 168, 65, 0, // Skip to: 21620 +/* 4812 */ MCD_OPC_Decode, 190, 15, 18, // Opcode: VINSERTW +/* 4816 */ MCD_OPC_FilterValue, 15, 11, 0, 0, // Skip to: 4832 +/* 4821 */ MCD_OPC_CheckField, 0, 1, 1, 152, 65, 0, // Skip to: 21620 +/* 4828 */ MCD_OPC_Decode, 188, 15, 18, // Opcode: VINSERTD +/* 4832 */ MCD_OPC_FilterValue, 16, 56, 0, 0, // Skip to: 4893 +/* 4837 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4840 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4849 +/* 4845 */ MCD_OPC_Decode, 208, 16, 3, // Opcode: VSLO +/* 4849 */ MCD_OPC_FilterValue, 1, 126, 65, 0, // Skip to: 21620 +/* 4854 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 4857 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4866 +/* 4862 */ MCD_OPC_Decode, 235, 16, 7, // Opcode: VSTRIBL_rec +/* 4866 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4875 +/* 4871 */ MCD_OPC_Decode, 237, 16, 7, // Opcode: VSTRIBR_rec +/* 4875 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4884 +/* 4880 */ MCD_OPC_Decode, 239, 16, 7, // Opcode: VSTRIHL_rec +/* 4884 */ MCD_OPC_FilterValue, 3, 91, 65, 0, // Skip to: 21620 +/* 4889 */ MCD_OPC_Decode, 241, 16, 7, // Opcode: VSTRIHR_rec +/* 4893 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 4909 +/* 4898 */ MCD_OPC_CheckField, 0, 1, 0, 75, 65, 0, // Skip to: 21620 +/* 4905 */ MCD_OPC_Decode, 230, 16, 3, // Opcode: VSRO +/* 4909 */ MCD_OPC_FilterValue, 19, 18, 0, 0, // Skip to: 4932 +/* 4914 */ MCD_OPC_CheckField, 19, 2, 0, 59, 65, 0, // Skip to: 21620 +/* 4921 */ MCD_OPC_CheckField, 0, 1, 0, 52, 65, 0, // Skip to: 21620 +/* 4928 */ MCD_OPC_Decode, 179, 15, 21, // Opcode: VGNB +/* 4932 */ MCD_OPC_FilterValue, 20, 18, 0, 0, // Skip to: 4955 +/* 4937 */ MCD_OPC_CheckField, 16, 5, 0, 36, 65, 0, // Skip to: 21620 +/* 4944 */ MCD_OPC_CheckField, 0, 1, 0, 29, 65, 0, // Skip to: 21620 +/* 4951 */ MCD_OPC_Decode, 178, 15, 7, // Opcode: VGBBD +/* 4955 */ MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 4981 +/* 4960 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 4963 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4972 +/* 4968 */ MCD_OPC_Decode, 171, 14, 3, // Opcode: VBPERMQ +/* 4972 */ MCD_OPC_FilterValue, 1, 3, 65, 0, // Skip to: 21620 +/* 4977 */ MCD_OPC_Decode, 174, 14, 3, // Opcode: VCFUGED +/* 4981 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 4997 +/* 4986 */ MCD_OPC_CheckField, 0, 1, 1, 243, 64, 0, // Skip to: 21620 +/* 4993 */ MCD_OPC_Decode, 156, 16, 3, // Opcode: VPEXTD +/* 4997 */ MCD_OPC_FilterValue, 23, 21, 0, 0, // Skip to: 5023 +/* 5002 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5005 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5014 +/* 5010 */ MCD_OPC_Decode, 170, 14, 3, // Opcode: VBPERMD +/* 5014 */ MCD_OPC_FilterValue, 1, 217, 64, 0, // Skip to: 21620 +/* 5019 */ MCD_OPC_Decode, 152, 16, 3, // Opcode: VPDEPD +/* 5023 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 5039 +/* 5028 */ MCD_OPC_CheckField, 0, 1, 1, 201, 64, 0, // Skip to: 21620 +/* 5035 */ MCD_OPC_Decode, 172, 15, 22, // Opcode: VEXTUBLX +/* 5039 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 5055 +/* 5044 */ MCD_OPC_CheckField, 0, 1, 1, 185, 64, 0, // Skip to: 21620 +/* 5051 */ MCD_OPC_Decode, 174, 15, 22, // Opcode: VEXTUHLX +/* 5055 */ MCD_OPC_FilterValue, 26, 21, 0, 0, // Skip to: 5081 +/* 5060 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5063 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5072 +/* 5068 */ MCD_OPC_Decode, 236, 15, 3, // Opcode: VMRGOW +/* 5072 */ MCD_OPC_FilterValue, 1, 159, 64, 0, // Skip to: 21620 +/* 5077 */ MCD_OPC_Decode, 176, 15, 22, // Opcode: VEXTUWLX +/* 5081 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 5097 +/* 5086 */ MCD_OPC_CheckField, 0, 1, 1, 143, 64, 0, // Skip to: 21620 +/* 5093 */ MCD_OPC_Decode, 173, 15, 22, // Opcode: VEXTUBRX +/* 5097 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 5113 +/* 5102 */ MCD_OPC_CheckField, 0, 1, 1, 127, 64, 0, // Skip to: 21620 +/* 5109 */ MCD_OPC_Decode, 175, 15, 22, // Opcode: VEXTUHRX +/* 5113 */ MCD_OPC_FilterValue, 30, 118, 64, 0, // Skip to: 21620 +/* 5118 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5121 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5130 +/* 5126 */ MCD_OPC_Decode, 229, 15, 3, // Opcode: VMRGEW +/* 5130 */ MCD_OPC_FilterValue, 1, 101, 64, 0, // Skip to: 21620 +/* 5135 */ MCD_OPC_Decode, 177, 15, 22, // Opcode: VEXTUWRX +/* 5139 */ MCD_OPC_FilterValue, 7, 49, 2, 0, // Skip to: 5705 +/* 5144 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 5147 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 5173 +/* 5152 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5155 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5164 +/* 5160 */ MCD_OPC_Decode, 166, 16, 3, // Opcode: VPKUHUM +/* 5164 */ MCD_OPC_FilterValue, 1, 67, 64, 0, // Skip to: 21620 +/* 5169 */ MCD_OPC_Decode, 182, 15, 23, // Opcode: VINSBVLX +/* 5173 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 5199 +/* 5178 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5181 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5190 +/* 5186 */ MCD_OPC_Decode, 168, 16, 3, // Opcode: VPKUWUM +/* 5190 */ MCD_OPC_FilterValue, 1, 41, 64, 0, // Skip to: 21620 +/* 5195 */ MCD_OPC_Decode, 193, 15, 23, // Opcode: VINSHVLX +/* 5199 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 5225 +/* 5204 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5207 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5216 +/* 5212 */ MCD_OPC_Decode, 167, 16, 3, // Opcode: VPKUHUS +/* 5216 */ MCD_OPC_FilterValue, 1, 15, 64, 0, // Skip to: 21620 +/* 5221 */ MCD_OPC_Decode, 198, 15, 23, // Opcode: VINSWVLX +/* 5225 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 5251 +/* 5230 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5233 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5242 +/* 5238 */ MCD_OPC_Decode, 169, 16, 3, // Opcode: VPKUWUS +/* 5242 */ MCD_OPC_FilterValue, 1, 245, 63, 0, // Skip to: 21620 +/* 5247 */ MCD_OPC_Decode, 195, 15, 24, // Opcode: VINSW +/* 5251 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 5277 +/* 5256 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5259 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5268 +/* 5264 */ MCD_OPC_Decode, 161, 16, 3, // Opcode: VPKSHUS +/* 5268 */ MCD_OPC_FilterValue, 1, 219, 63, 0, // Skip to: 21620 +/* 5273 */ MCD_OPC_Decode, 183, 15, 23, // Opcode: VINSBVRX +/* 5277 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 5303 +/* 5282 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5285 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5294 +/* 5290 */ MCD_OPC_Decode, 163, 16, 3, // Opcode: VPKSWUS +/* 5294 */ MCD_OPC_FilterValue, 1, 193, 63, 0, // Skip to: 21620 +/* 5299 */ MCD_OPC_Decode, 194, 15, 23, // Opcode: VINSHVRX +/* 5303 */ MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 5329 +/* 5308 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5311 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5320 +/* 5316 */ MCD_OPC_Decode, 160, 16, 3, // Opcode: VPKSHSS +/* 5320 */ MCD_OPC_FilterValue, 1, 167, 63, 0, // Skip to: 21620 +/* 5325 */ MCD_OPC_Decode, 199, 15, 23, // Opcode: VINSWVRX +/* 5329 */ MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 5355 +/* 5334 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5337 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5346 +/* 5342 */ MCD_OPC_Decode, 162, 16, 3, // Opcode: VPKSWSS +/* 5346 */ MCD_OPC_FilterValue, 1, 141, 63, 0, // Skip to: 21620 +/* 5351 */ MCD_OPC_Decode, 184, 15, 25, // Opcode: VINSD +/* 5355 */ MCD_OPC_FilterValue, 8, 28, 0, 0, // Skip to: 5388 +/* 5360 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5363 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5379 +/* 5368 */ MCD_OPC_CheckField, 16, 5, 0, 117, 63, 0, // Skip to: 21620 +/* 5375 */ MCD_OPC_Decode, 136, 17, 7, // Opcode: VUPKHSB +/* 5379 */ MCD_OPC_FilterValue, 1, 108, 63, 0, // Skip to: 21620 +/* 5384 */ MCD_OPC_Decode, 180, 15, 26, // Opcode: VINSBLX +/* 5388 */ MCD_OPC_FilterValue, 9, 28, 0, 0, // Skip to: 5421 +/* 5393 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5396 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5412 +/* 5401 */ MCD_OPC_CheckField, 16, 5, 0, 84, 63, 0, // Skip to: 21620 +/* 5408 */ MCD_OPC_Decode, 137, 17, 7, // Opcode: VUPKHSH +/* 5412 */ MCD_OPC_FilterValue, 1, 75, 63, 0, // Skip to: 21620 +/* 5417 */ MCD_OPC_Decode, 191, 15, 26, // Opcode: VINSHLX +/* 5421 */ MCD_OPC_FilterValue, 10, 28, 0, 0, // Skip to: 5454 +/* 5426 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5429 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5445 +/* 5434 */ MCD_OPC_CheckField, 16, 5, 0, 51, 63, 0, // Skip to: 21620 +/* 5441 */ MCD_OPC_Decode, 140, 17, 7, // Opcode: VUPKLSB +/* 5445 */ MCD_OPC_FilterValue, 1, 42, 63, 0, // Skip to: 21620 +/* 5450 */ MCD_OPC_Decode, 196, 15, 26, // Opcode: VINSWLX +/* 5454 */ MCD_OPC_FilterValue, 11, 28, 0, 0, // Skip to: 5487 +/* 5459 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5462 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5478 +/* 5467 */ MCD_OPC_CheckField, 16, 5, 0, 18, 63, 0, // Skip to: 21620 +/* 5474 */ MCD_OPC_Decode, 141, 17, 7, // Opcode: VUPKLSH +/* 5478 */ MCD_OPC_FilterValue, 1, 9, 63, 0, // Skip to: 21620 +/* 5483 */ MCD_OPC_Decode, 185, 15, 27, // Opcode: VINSDLX +/* 5487 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 5513 +/* 5492 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5495 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5504 +/* 5500 */ MCD_OPC_Decode, 157, 16, 3, // Opcode: VPKPX +/* 5504 */ MCD_OPC_FilterValue, 1, 239, 62, 0, // Skip to: 21620 +/* 5509 */ MCD_OPC_Decode, 181, 15, 26, // Opcode: VINSBRX +/* 5513 */ MCD_OPC_FilterValue, 13, 28, 0, 0, // Skip to: 5546 +/* 5518 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5521 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5537 +/* 5526 */ MCD_OPC_CheckField, 16, 5, 0, 215, 62, 0, // Skip to: 21620 +/* 5533 */ MCD_OPC_Decode, 135, 17, 7, // Opcode: VUPKHPX +/* 5537 */ MCD_OPC_FilterValue, 1, 206, 62, 0, // Skip to: 21620 +/* 5542 */ MCD_OPC_Decode, 192, 15, 26, // Opcode: VINSHRX +/* 5546 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 5562 +/* 5551 */ MCD_OPC_CheckField, 0, 1, 1, 190, 62, 0, // Skip to: 21620 +/* 5558 */ MCD_OPC_Decode, 197, 15, 26, // Opcode: VINSWRX +/* 5562 */ MCD_OPC_FilterValue, 15, 28, 0, 0, // Skip to: 5595 +/* 5567 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5570 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5586 +/* 5575 */ MCD_OPC_CheckField, 16, 5, 0, 166, 62, 0, // Skip to: 21620 +/* 5582 */ MCD_OPC_Decode, 139, 17, 7, // Opcode: VUPKLPX +/* 5586 */ MCD_OPC_FilterValue, 1, 157, 62, 0, // Skip to: 21620 +/* 5591 */ MCD_OPC_Decode, 186, 15, 27, // Opcode: VINSDRX +/* 5595 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 5611 +/* 5600 */ MCD_OPC_CheckField, 0, 1, 0, 141, 62, 0, // Skip to: 21620 +/* 5607 */ MCD_OPC_Decode, 164, 16, 3, // Opcode: VPKUDUM +/* 5611 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 5627 +/* 5616 */ MCD_OPC_CheckField, 0, 1, 0, 125, 62, 0, // Skip to: 21620 +/* 5623 */ MCD_OPC_Decode, 165, 16, 3, // Opcode: VPKUDUS +/* 5627 */ MCD_OPC_FilterValue, 21, 11, 0, 0, // Skip to: 5643 +/* 5632 */ MCD_OPC_CheckField, 0, 1, 0, 109, 62, 0, // Skip to: 21620 +/* 5639 */ MCD_OPC_Decode, 159, 16, 3, // Opcode: VPKSDUS +/* 5643 */ MCD_OPC_FilterValue, 23, 11, 0, 0, // Skip to: 5659 +/* 5648 */ MCD_OPC_CheckField, 0, 1, 0, 93, 62, 0, // Skip to: 21620 +/* 5655 */ MCD_OPC_Decode, 158, 16, 3, // Opcode: VPKSDSS +/* 5659 */ MCD_OPC_FilterValue, 25, 18, 0, 0, // Skip to: 5682 +/* 5664 */ MCD_OPC_CheckField, 16, 5, 0, 77, 62, 0, // Skip to: 21620 +/* 5671 */ MCD_OPC_CheckField, 0, 1, 0, 70, 62, 0, // Skip to: 21620 +/* 5678 */ MCD_OPC_Decode, 138, 17, 7, // Opcode: VUPKHSW +/* 5682 */ MCD_OPC_FilterValue, 27, 61, 62, 0, // Skip to: 21620 +/* 5687 */ MCD_OPC_CheckField, 16, 5, 0, 54, 62, 0, // Skip to: 21620 +/* 5694 */ MCD_OPC_CheckField, 0, 1, 0, 47, 62, 0, // Skip to: 21620 +/* 5701 */ MCD_OPC_Decode, 142, 17, 7, // Opcode: VUPKLSW +/* 5705 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 5714 +/* 5710 */ MCD_OPC_Decode, 174, 10, 28, // Opcode: MTVSRBMI +/* 5714 */ MCD_OPC_FilterValue, 11, 38, 0, 0, // Skip to: 5757 +/* 5719 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5722 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 5748 +/* 5727 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 5730 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5739 +/* 5735 */ MCD_OPC_Decode, 205, 16, 29, // Opcode: VSLDBI +/* 5739 */ MCD_OPC_FilterValue, 1, 4, 62, 0, // Skip to: 21620 +/* 5744 */ MCD_OPC_Decode, 228, 16, 29, // Opcode: VSRDBI +/* 5748 */ MCD_OPC_FilterValue, 1, 251, 61, 0, // Skip to: 21620 +/* 5753 */ MCD_OPC_Decode, 237, 15, 30, // Opcode: VMSUMCUD +/* 5757 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 5783 +/* 5762 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5765 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5774 +/* 5770 */ MCD_OPC_Decode, 146, 15, 31, // Opcode: VEXTDUBVLX +/* 5774 */ MCD_OPC_FilterValue, 1, 225, 61, 0, // Skip to: 21620 +/* 5779 */ MCD_OPC_Decode, 147, 15, 31, // Opcode: VEXTDUBVRX +/* 5783 */ MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 5809 +/* 5788 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5791 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5800 +/* 5796 */ MCD_OPC_Decode, 148, 15, 31, // Opcode: VEXTDUHVLX +/* 5800 */ MCD_OPC_FilterValue, 1, 199, 61, 0, // Skip to: 21620 +/* 5805 */ MCD_OPC_Decode, 149, 15, 31, // Opcode: VEXTDUHVRX +/* 5809 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 5835 +/* 5814 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5817 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5826 +/* 5822 */ MCD_OPC_Decode, 150, 15, 31, // Opcode: VEXTDUWVLX +/* 5826 */ MCD_OPC_FilterValue, 1, 173, 61, 0, // Skip to: 21620 +/* 5831 */ MCD_OPC_Decode, 151, 15, 31, // Opcode: VEXTDUWVRX +/* 5835 */ MCD_OPC_FilterValue, 15, 21, 0, 0, // Skip to: 5861 +/* 5840 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5843 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5852 +/* 5848 */ MCD_OPC_Decode, 144, 15, 31, // Opcode: VEXTDDVLX +/* 5852 */ MCD_OPC_FilterValue, 1, 147, 61, 0, // Skip to: 21620 +/* 5857 */ MCD_OPC_Decode, 145, 15, 31, // Opcode: VEXTDDVRX +/* 5861 */ MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 5887 +/* 5866 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5869 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5878 +/* 5874 */ MCD_OPC_Decode, 211, 15, 30, // Opcode: VMHADDSHS +/* 5878 */ MCD_OPC_FilterValue, 1, 121, 61, 0, // Skip to: 21620 +/* 5883 */ MCD_OPC_Decode, 212, 15, 30, // Opcode: VMHRADDSHS +/* 5887 */ MCD_OPC_FilterValue, 17, 21, 0, 0, // Skip to: 5913 +/* 5892 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5895 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5904 +/* 5900 */ MCD_OPC_Decode, 222, 15, 30, // Opcode: VMLADDUHM +/* 5904 */ MCD_OPC_FilterValue, 1, 95, 61, 0, // Skip to: 21620 +/* 5909 */ MCD_OPC_Decode, 242, 15, 30, // Opcode: VMSUMUDM +/* 5913 */ MCD_OPC_FilterValue, 18, 21, 0, 0, // Skip to: 5939 +/* 5918 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5921 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5930 +/* 5926 */ MCD_OPC_Decode, 241, 15, 30, // Opcode: VMSUMUBM +/* 5930 */ MCD_OPC_FilterValue, 1, 69, 61, 0, // Skip to: 21620 +/* 5935 */ MCD_OPC_Decode, 238, 15, 30, // Opcode: VMSUMMBM +/* 5939 */ MCD_OPC_FilterValue, 19, 21, 0, 0, // Skip to: 5965 +/* 5944 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5947 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5956 +/* 5952 */ MCD_OPC_Decode, 243, 15, 30, // Opcode: VMSUMUHM +/* 5956 */ MCD_OPC_FilterValue, 1, 43, 61, 0, // Skip to: 21620 +/* 5961 */ MCD_OPC_Decode, 244, 15, 30, // Opcode: VMSUMUHS +/* 5965 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 5991 +/* 5970 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5973 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5982 +/* 5978 */ MCD_OPC_Decode, 239, 15, 30, // Opcode: VMSUMSHM +/* 5982 */ MCD_OPC_FilterValue, 1, 17, 61, 0, // Skip to: 21620 +/* 5987 */ MCD_OPC_Decode, 240, 15, 30, // Opcode: VMSUMSHS +/* 5991 */ MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 6017 +/* 5996 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 5999 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6008 +/* 6004 */ MCD_OPC_Decode, 199, 16, 30, // Opcode: VSEL +/* 6008 */ MCD_OPC_FilterValue, 1, 247, 60, 0, // Skip to: 21620 +/* 6013 */ MCD_OPC_Decode, 153, 16, 30, // Opcode: VPERM +/* 6017 */ MCD_OPC_FilterValue, 22, 28, 0, 0, // Skip to: 6050 +/* 6022 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 6025 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 6041 +/* 6030 */ MCD_OPC_CheckField, 10, 1, 0, 223, 60, 0, // Skip to: 21620 +/* 6037 */ MCD_OPC_Decode, 206, 16, 32, // Opcode: VSLDOI +/* 6041 */ MCD_OPC_FilterValue, 1, 214, 60, 0, // Skip to: 21620 +/* 6046 */ MCD_OPC_Decode, 155, 16, 30, // Opcode: VPERMXOR +/* 6050 */ MCD_OPC_FilterValue, 23, 21, 0, 0, // Skip to: 6076 +/* 6055 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 6058 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6067 +/* 6063 */ MCD_OPC_Decode, 201, 15, 33, // Opcode: VMADDFP +/* 6067 */ MCD_OPC_FilterValue, 1, 188, 60, 0, // Skip to: 21620 +/* 6072 */ MCD_OPC_Decode, 148, 16, 33, // Opcode: VNMSUBFP +/* 6076 */ MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 6102 +/* 6081 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 6084 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6093 +/* 6089 */ MCD_OPC_Decode, 221, 9, 34, // Opcode: MADDHD +/* 6093 */ MCD_OPC_FilterValue, 1, 162, 60, 0, // Skip to: 21620 +/* 6098 */ MCD_OPC_Decode, 222, 9, 34, // Opcode: MADDHDU +/* 6102 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 6118 +/* 6107 */ MCD_OPC_CheckField, 0, 1, 1, 146, 60, 0, // Skip to: 21620 +/* 6114 */ MCD_OPC_Decode, 223, 9, 35, // Opcode: MADDLD +/* 6118 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 6134 +/* 6123 */ MCD_OPC_CheckField, 0, 1, 1, 130, 60, 0, // Skip to: 21620 +/* 6130 */ MCD_OPC_Decode, 154, 16, 30, // Opcode: VPERMR +/* 6134 */ MCD_OPC_FilterValue, 30, 21, 0, 0, // Skip to: 6160 +/* 6139 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 6142 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6151 +/* 6147 */ MCD_OPC_Decode, 149, 14, 30, // Opcode: VADDEUQM +/* 6151 */ MCD_OPC_FilterValue, 1, 104, 60, 0, // Skip to: 21620 +/* 6156 */ MCD_OPC_Decode, 148, 14, 30, // Opcode: VADDECUQ +/* 6160 */ MCD_OPC_FilterValue, 31, 95, 60, 0, // Skip to: 21620 +/* 6165 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 6168 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6177 +/* 6173 */ MCD_OPC_Decode, 245, 16, 30, // Opcode: VSUBEUQM +/* 6177 */ MCD_OPC_FilterValue, 1, 78, 60, 0, // Skip to: 21620 +/* 6182 */ MCD_OPC_Decode, 244, 16, 30, // Opcode: VSUBECUQ +/* 6186 */ MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 6212 +/* 6191 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 6194 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6203 +/* 6199 */ MCD_OPC_Decode, 212, 9, 36, // Opcode: LXVP +/* 6203 */ MCD_OPC_FilterValue, 1, 52, 60, 0, // Skip to: 21620 +/* 6208 */ MCD_OPC_Decode, 172, 13, 36, // Opcode: STXVP +/* 6212 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 6221 +/* 6217 */ MCD_OPC_Decode, 196, 10, 37, // Opcode: MULLI +/* 6221 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 6230 +/* 6226 */ MCD_OPC_Decode, 201, 13, 37, // Opcode: SUBFIC +/* 6230 */ MCD_OPC_FilterValue, 10, 21, 0, 0, // Skip to: 6256 +/* 6235 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 6238 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6247 +/* 6243 */ MCD_OPC_Decode, 211, 4, 38, // Opcode: CMPLWI +/* 6247 */ MCD_OPC_FilterValue, 1, 8, 60, 0, // Skip to: 21620 +/* 6252 */ MCD_OPC_Decode, 209, 4, 39, // Opcode: CMPLDI +/* 6256 */ MCD_OPC_FilterValue, 11, 21, 0, 0, // Skip to: 6282 +/* 6261 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 6264 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6273 +/* 6269 */ MCD_OPC_Decode, 215, 4, 40, // Opcode: CMPWI +/* 6273 */ MCD_OPC_FilterValue, 1, 238, 59, 0, // Skip to: 21620 +/* 6278 */ MCD_OPC_Decode, 206, 4, 41, // Opcode: CMPDI +/* 6282 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 6291 +/* 6287 */ MCD_OPC_Decode, 231, 2, 37, // Opcode: ADDIC +/* 6291 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 6300 +/* 6296 */ MCD_OPC_Decode, 233, 2, 37, // Opcode: ADDIC_rec +/* 6300 */ MCD_OPC_FilterValue, 14, 15, 0, 0, // Skip to: 6320 +/* 6305 */ MCD_OPC_CheckField, 16, 5, 0, 4, 0, 0, // Skip to: 6316 +/* 6312 */ MCD_OPC_Decode, 155, 9, 42, // Opcode: LI +/* 6316 */ MCD_OPC_Decode, 229, 2, 43, // Opcode: ADDI +/* 6320 */ MCD_OPC_FilterValue, 15, 15, 0, 0, // Skip to: 6340 +/* 6325 */ MCD_OPC_CheckField, 16, 5, 0, 4, 0, 0, // Skip to: 6336 +/* 6332 */ MCD_OPC_Decode, 157, 9, 42, // Opcode: LIS +/* 6336 */ MCD_OPC_Decode, 234, 2, 43, // Opcode: ADDIS +/* 6340 */ MCD_OPC_FilterValue, 16, 35, 1, 0, // Skip to: 6636 +/* 6345 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6348 */ MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 6420 +/* 6353 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 6356 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 6366 +/* 6362 */ MCD_OPC_Decode, 135, 4, 44, // Opcode: BDNZ +/* 6366 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 6376 +/* 6372 */ MCD_OPC_Decode, 155, 4, 44, // Opcode: BDZ +/* 6376 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 6386 +/* 6382 */ MCD_OPC_Decode, 153, 4, 44, // Opcode: BDNZm +/* 6386 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 6396 +/* 6392 */ MCD_OPC_Decode, 154, 4, 44, // Opcode: BDNZp +/* 6396 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 6406 +/* 6402 */ MCD_OPC_Decode, 173, 4, 44, // Opcode: BDZm +/* 6406 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 6416 +/* 6412 */ MCD_OPC_Decode, 174, 4, 44, // Opcode: BDZp +/* 6416 */ MCD_OPC_Decode, 202, 19, 45, // Opcode: gBC +/* 6420 */ MCD_OPC_FilterValue, 1, 67, 0, 0, // Skip to: 6492 +/* 6425 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 6428 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 6438 +/* 6434 */ MCD_OPC_Decode, 140, 4, 44, // Opcode: BDNZL +/* 6438 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 6448 +/* 6444 */ MCD_OPC_Decode, 160, 4, 44, // Opcode: BDZL +/* 6448 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 6458 +/* 6454 */ MCD_OPC_Decode, 151, 4, 44, // Opcode: BDNZLm +/* 6458 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 6468 +/* 6464 */ MCD_OPC_Decode, 152, 4, 44, // Opcode: BDNZLp +/* 6468 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 6478 +/* 6474 */ MCD_OPC_Decode, 171, 4, 44, // Opcode: BDZLm +/* 6478 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 6488 +/* 6484 */ MCD_OPC_Decode, 172, 4, 44, // Opcode: BDZLp +/* 6488 */ MCD_OPC_Decode, 207, 19, 45, // Opcode: gBCL +/* 6492 */ MCD_OPC_FilterValue, 2, 67, 0, 0, // Skip to: 6564 +/* 6497 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 6500 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 6510 +/* 6506 */ MCD_OPC_Decode, 137, 4, 46, // Opcode: BDNZA +/* 6510 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 6520 +/* 6516 */ MCD_OPC_Decode, 157, 4, 46, // Opcode: BDZA +/* 6520 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 6530 +/* 6526 */ MCD_OPC_Decode, 138, 4, 46, // Opcode: BDNZAm +/* 6530 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 6540 +/* 6536 */ MCD_OPC_Decode, 139, 4, 46, // Opcode: BDNZAp +/* 6540 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 6550 +/* 6546 */ MCD_OPC_Decode, 158, 4, 46, // Opcode: BDZAm +/* 6550 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 6560 +/* 6556 */ MCD_OPC_Decode, 159, 4, 46, // Opcode: BDZAp +/* 6560 */ MCD_OPC_Decode, 203, 19, 47, // Opcode: gBCA +/* 6564 */ MCD_OPC_FilterValue, 3, 203, 58, 0, // Skip to: 21620 +/* 6569 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 6572 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 6582 +/* 6578 */ MCD_OPC_Decode, 141, 4, 46, // Opcode: BDNZLA +/* 6582 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 6592 +/* 6588 */ MCD_OPC_Decode, 161, 4, 46, // Opcode: BDZLA +/* 6592 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 6602 +/* 6598 */ MCD_OPC_Decode, 142, 4, 46, // Opcode: BDNZLAm +/* 6602 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 6612 +/* 6608 */ MCD_OPC_Decode, 143, 4, 46, // Opcode: BDNZLAp +/* 6612 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 6622 +/* 6618 */ MCD_OPC_Decode, 162, 4, 46, // Opcode: BDZLAm +/* 6622 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 6632 +/* 6628 */ MCD_OPC_Decode, 163, 4, 46, // Opcode: BDZLAp +/* 6632 */ MCD_OPC_Decode, 208, 19, 47, // Opcode: gBCLA +/* 6636 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 6652 +/* 6641 */ MCD_OPC_CheckField, 1, 1, 1, 124, 58, 0, // Skip to: 21620 +/* 6648 */ MCD_OPC_Decode, 134, 12, 48, // Opcode: SC +/* 6652 */ MCD_OPC_FilterValue, 18, 39, 0, 0, // Skip to: 6696 +/* 6657 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 6660 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6669 +/* 6665 */ MCD_OPC_Decode, 211, 3, 49, // Opcode: B +/* 6669 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 6678 +/* 6674 */ MCD_OPC_Decode, 175, 4, 49, // Opcode: BL +/* 6678 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6687 +/* 6683 */ MCD_OPC_Decode, 212, 3, 50, // Opcode: BA +/* 6687 */ MCD_OPC_FilterValue, 3, 80, 58, 0, // Skip to: 21620 +/* 6692 */ MCD_OPC_Decode, 186, 4, 50, // Opcode: BLA +/* 6696 */ MCD_OPC_FilterValue, 19, 22, 3, 0, // Skip to: 7491 +/* 6701 */ MCD_OPC_ExtractField, 1, 5, // Inst{5-1} ... +/* 6704 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 6734 +/* 6709 */ MCD_OPC_CheckField, 21, 2, 0, 56, 58, 0, // Skip to: 21620 +/* 6716 */ MCD_OPC_CheckField, 6, 12, 0, 49, 58, 0, // Skip to: 21620 +/* 6723 */ MCD_OPC_CheckField, 0, 1, 0, 42, 58, 0, // Skip to: 21620 +/* 6730 */ MCD_OPC_Decode, 226, 9, 51, // Opcode: MCRF +/* 6734 */ MCD_OPC_FilterValue, 1, 131, 0, 0, // Skip to: 6870 +/* 6739 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 6742 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 6758 +/* 6747 */ MCD_OPC_CheckField, 0, 1, 0, 18, 58, 0, // Skip to: 21620 +/* 6754 */ MCD_OPC_Decode, 241, 4, 52, // Opcode: CRNOR +/* 6758 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 6774 +/* 6763 */ MCD_OPC_CheckField, 0, 1, 0, 2, 58, 0, // Skip to: 21620 +/* 6770 */ MCD_OPC_Decode, 238, 4, 52, // Opcode: CRANDC +/* 6774 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 6790 +/* 6779 */ MCD_OPC_CheckField, 0, 1, 0, 242, 57, 0, // Skip to: 21620 +/* 6786 */ MCD_OPC_Decode, 246, 4, 52, // Opcode: CRXOR +/* 6790 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 6806 +/* 6795 */ MCD_OPC_CheckField, 0, 1, 0, 226, 57, 0, // Skip to: 21620 +/* 6802 */ MCD_OPC_Decode, 240, 4, 52, // Opcode: CRNAND +/* 6806 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 6822 +/* 6811 */ MCD_OPC_CheckField, 0, 1, 0, 210, 57, 0, // Skip to: 21620 +/* 6818 */ MCD_OPC_Decode, 237, 4, 52, // Opcode: CRAND +/* 6822 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 6838 +/* 6827 */ MCD_OPC_CheckField, 0, 1, 0, 194, 57, 0, // Skip to: 21620 +/* 6834 */ MCD_OPC_Decode, 239, 4, 52, // Opcode: CREQV +/* 6838 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 6854 +/* 6843 */ MCD_OPC_CheckField, 0, 1, 0, 178, 57, 0, // Skip to: 21620 +/* 6850 */ MCD_OPC_Decode, 243, 4, 52, // Opcode: CRORC +/* 6854 */ MCD_OPC_FilterValue, 14, 169, 57, 0, // Skip to: 21620 +/* 6859 */ MCD_OPC_CheckField, 0, 1, 0, 162, 57, 0, // Skip to: 21620 +/* 6866 */ MCD_OPC_Decode, 242, 4, 52, // Opcode: CROR +/* 6870 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6879 +/* 6875 */ MCD_OPC_Decode, 135, 3, 53, // Opcode: ADDPCIS +/* 6879 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 6902 +/* 6884 */ MCD_OPC_CheckField, 6, 20, 1, 137, 57, 0, // Skip to: 21620 +/* 6891 */ MCD_OPC_CheckField, 0, 1, 0, 130, 57, 0, // Skip to: 21620 +/* 6898 */ MCD_OPC_Decode, 232, 11, 0, // Opcode: RFMCI +/* 6902 */ MCD_OPC_FilterValue, 7, 18, 0, 0, // Skip to: 6925 +/* 6907 */ MCD_OPC_CheckField, 6, 20, 1, 114, 57, 0, // Skip to: 21620 +/* 6914 */ MCD_OPC_CheckField, 0, 1, 0, 107, 57, 0, // Skip to: 21620 +/* 6921 */ MCD_OPC_Decode, 228, 11, 0, // Opcode: RFDI +/* 6925 */ MCD_OPC_FilterValue, 16, 113, 1, 0, // Skip to: 7299 +/* 6930 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 6933 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 7116 +/* 6938 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 6941 */ MCD_OPC_FilterValue, 0, 134, 0, 0, // Skip to: 7080 +/* 6946 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 6949 */ MCD_OPC_FilterValue, 0, 74, 57, 0, // Skip to: 21620 +/* 6954 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 6957 */ MCD_OPC_FilterValue, 128, 4, 11, 0, 0, // Skip to: 6974 +/* 6963 */ MCD_OPC_CheckField, 11, 2, 0, 106, 0, 0, // Skip to: 7076 +/* 6970 */ MCD_OPC_Decode, 144, 4, 0, // Opcode: BDNZLR +/* 6974 */ MCD_OPC_FilterValue, 192, 4, 11, 0, 0, // Skip to: 6991 +/* 6980 */ MCD_OPC_CheckField, 11, 2, 0, 89, 0, 0, // Skip to: 7076 +/* 6987 */ MCD_OPC_Decode, 164, 4, 0, // Opcode: BDZLR +/* 6991 */ MCD_OPC_FilterValue, 128, 5, 11, 0, 0, // Skip to: 7008 +/* 6997 */ MCD_OPC_CheckField, 11, 2, 0, 72, 0, 0, // Skip to: 7076 +/* 7004 */ MCD_OPC_Decode, 192, 4, 0, // Opcode: BLR +/* 7008 */ MCD_OPC_FilterValue, 128, 6, 11, 0, 0, // Skip to: 7025 +/* 7014 */ MCD_OPC_CheckField, 11, 2, 0, 55, 0, 0, // Skip to: 7076 +/* 7021 */ MCD_OPC_Decode, 149, 4, 0, // Opcode: BDNZLRm +/* 7025 */ MCD_OPC_FilterValue, 160, 6, 11, 0, 0, // Skip to: 7042 +/* 7031 */ MCD_OPC_CheckField, 11, 2, 0, 38, 0, 0, // Skip to: 7076 +/* 7038 */ MCD_OPC_Decode, 150, 4, 0, // Opcode: BDNZLRp +/* 7042 */ MCD_OPC_FilterValue, 192, 6, 11, 0, 0, // Skip to: 7059 +/* 7048 */ MCD_OPC_CheckField, 11, 2, 0, 21, 0, 0, // Skip to: 7076 +/* 7055 */ MCD_OPC_Decode, 169, 4, 0, // Opcode: BDZLRm +/* 7059 */ MCD_OPC_FilterValue, 224, 6, 11, 0, 0, // Skip to: 7076 +/* 7065 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 7076 +/* 7072 */ MCD_OPC_Decode, 170, 4, 0, // Opcode: BDZLRp +/* 7076 */ MCD_OPC_Decode, 210, 19, 54, // Opcode: gBCLR +/* 7080 */ MCD_OPC_FilterValue, 16, 199, 56, 0, // Skip to: 21620 +/* 7085 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 7088 */ MCD_OPC_FilterValue, 0, 191, 56, 0, // Skip to: 21620 +/* 7093 */ MCD_OPC_CheckField, 16, 10, 128, 5, 11, 0, 0, // Skip to: 7112 +/* 7101 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 7112 +/* 7108 */ MCD_OPC_Decode, 252, 3, 0, // Opcode: BCTR +/* 7112 */ MCD_OPC_Decode, 205, 19, 54, // Opcode: gBCCTR +/* 7116 */ MCD_OPC_FilterValue, 1, 163, 56, 0, // Skip to: 21620 +/* 7121 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 7124 */ MCD_OPC_FilterValue, 0, 134, 0, 0, // Skip to: 7263 +/* 7129 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 7132 */ MCD_OPC_FilterValue, 0, 147, 56, 0, // Skip to: 21620 +/* 7137 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... +/* 7140 */ MCD_OPC_FilterValue, 128, 4, 11, 0, 0, // Skip to: 7157 +/* 7146 */ MCD_OPC_CheckField, 11, 2, 0, 106, 0, 0, // Skip to: 7259 +/* 7153 */ MCD_OPC_Decode, 146, 4, 0, // Opcode: BDNZLRL +/* 7157 */ MCD_OPC_FilterValue, 192, 4, 11, 0, 0, // Skip to: 7174 +/* 7163 */ MCD_OPC_CheckField, 11, 2, 0, 89, 0, 0, // Skip to: 7259 +/* 7170 */ MCD_OPC_Decode, 166, 4, 0, // Opcode: BDZLRL +/* 7174 */ MCD_OPC_FilterValue, 128, 5, 11, 0, 0, // Skip to: 7191 +/* 7180 */ MCD_OPC_CheckField, 11, 2, 0, 72, 0, 0, // Skip to: 7259 +/* 7187 */ MCD_OPC_Decode, 194, 4, 0, // Opcode: BLRL +/* 7191 */ MCD_OPC_FilterValue, 128, 6, 11, 0, 0, // Skip to: 7208 +/* 7197 */ MCD_OPC_CheckField, 11, 2, 0, 55, 0, 0, // Skip to: 7259 +/* 7204 */ MCD_OPC_Decode, 147, 4, 0, // Opcode: BDNZLRLm +/* 7208 */ MCD_OPC_FilterValue, 160, 6, 11, 0, 0, // Skip to: 7225 +/* 7214 */ MCD_OPC_CheckField, 11, 2, 0, 38, 0, 0, // Skip to: 7259 +/* 7221 */ MCD_OPC_Decode, 148, 4, 0, // Opcode: BDNZLRLp +/* 7225 */ MCD_OPC_FilterValue, 192, 6, 11, 0, 0, // Skip to: 7242 +/* 7231 */ MCD_OPC_CheckField, 11, 2, 0, 21, 0, 0, // Skip to: 7259 +/* 7238 */ MCD_OPC_Decode, 167, 4, 0, // Opcode: BDZLRLm +/* 7242 */ MCD_OPC_FilterValue, 224, 6, 11, 0, 0, // Skip to: 7259 +/* 7248 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 7259 +/* 7255 */ MCD_OPC_Decode, 168, 4, 0, // Opcode: BDZLRLp +/* 7259 */ MCD_OPC_Decode, 211, 19, 54, // Opcode: gBCLRL +/* 7263 */ MCD_OPC_FilterValue, 16, 16, 56, 0, // Skip to: 21620 +/* 7268 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 7271 */ MCD_OPC_FilterValue, 0, 8, 56, 0, // Skip to: 21620 +/* 7276 */ MCD_OPC_CheckField, 16, 10, 128, 5, 11, 0, 0, // Skip to: 7295 +/* 7284 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 7295 +/* 7291 */ MCD_OPC_Decode, 254, 3, 0, // Opcode: BCTRL +/* 7295 */ MCD_OPC_Decode, 206, 19, 54, // Opcode: gBCCTRL +/* 7299 */ MCD_OPC_FilterValue, 18, 141, 0, 0, // Skip to: 7445 +/* 7304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 7307 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 7330 +/* 7312 */ MCD_OPC_CheckField, 11, 15, 0, 221, 55, 0, // Skip to: 21620 +/* 7319 */ MCD_OPC_CheckField, 0, 1, 0, 214, 55, 0, // Skip to: 21620 +/* 7326 */ MCD_OPC_Decode, 231, 11, 0, // Opcode: RFID +/* 7330 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 7353 +/* 7335 */ MCD_OPC_CheckField, 11, 15, 0, 198, 55, 0, // Skip to: 21620 +/* 7342 */ MCD_OPC_CheckField, 0, 1, 0, 191, 55, 0, // Skip to: 21620 +/* 7349 */ MCD_OPC_Decode, 230, 11, 0, // Opcode: RFI +/* 7353 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 7376 +/* 7358 */ MCD_OPC_CheckField, 12, 14, 0, 175, 55, 0, // Skip to: 21620 +/* 7365 */ MCD_OPC_CheckField, 0, 1, 0, 168, 55, 0, // Skip to: 21620 +/* 7372 */ MCD_OPC_Decode, 229, 11, 55, // Opcode: RFEBB +/* 7376 */ MCD_OPC_FilterValue, 8, 18, 0, 0, // Skip to: 7399 +/* 7381 */ MCD_OPC_CheckField, 11, 15, 0, 152, 55, 0, // Skip to: 21620 +/* 7388 */ MCD_OPC_CheckField, 0, 1, 0, 145, 55, 0, // Skip to: 21620 +/* 7395 */ MCD_OPC_Decode, 201, 8, 0, // Opcode: HRFID +/* 7399 */ MCD_OPC_FilterValue, 11, 18, 0, 0, // Skip to: 7422 +/* 7404 */ MCD_OPC_CheckField, 11, 15, 0, 129, 55, 0, // Skip to: 21620 +/* 7411 */ MCD_OPC_CheckField, 0, 1, 0, 122, 55, 0, // Skip to: 21620 +/* 7418 */ MCD_OPC_Decode, 131, 13, 0, // Opcode: STOP +/* 7422 */ MCD_OPC_FilterValue, 13, 113, 55, 0, // Skip to: 21620 +/* 7427 */ MCD_OPC_CheckField, 11, 15, 0, 106, 55, 0, // Skip to: 21620 +/* 7434 */ MCD_OPC_CheckField, 0, 1, 0, 99, 55, 0, // Skip to: 21620 +/* 7441 */ MCD_OPC_Decode, 209, 10, 0, // Opcode: NAP +/* 7445 */ MCD_OPC_FilterValue, 19, 18, 0, 0, // Skip to: 7468 +/* 7450 */ MCD_OPC_CheckField, 6, 20, 1, 83, 55, 0, // Skip to: 21620 +/* 7457 */ MCD_OPC_CheckField, 0, 1, 0, 76, 55, 0, // Skip to: 21620 +/* 7464 */ MCD_OPC_Decode, 227, 11, 0, // Opcode: RFCI +/* 7468 */ MCD_OPC_FilterValue, 22, 67, 55, 0, // Skip to: 21620 +/* 7473 */ MCD_OPC_CheckField, 6, 20, 4, 60, 55, 0, // Skip to: 21620 +/* 7480 */ MCD_OPC_CheckField, 0, 1, 0, 53, 55, 0, // Skip to: 21620 +/* 7487 */ MCD_OPC_Decode, 211, 8, 0, // Opcode: ISYNC +/* 7491 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 7517 +/* 7496 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 7499 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7508 +/* 7504 */ MCD_OPC_Decode, 249, 11, 56, // Opcode: RLWIMI +/* 7508 */ MCD_OPC_FilterValue, 1, 27, 55, 0, // Skip to: 21620 +/* 7513 */ MCD_OPC_Decode, 252, 11, 56, // Opcode: RLWIMI_rec +/* 7517 */ MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 7543 +/* 7522 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 7525 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7534 +/* 7530 */ MCD_OPC_Decode, 253, 11, 57, // Opcode: RLWINM +/* 7534 */ MCD_OPC_FilterValue, 1, 1, 55, 0, // Skip to: 21620 +/* 7539 */ MCD_OPC_Decode, 128, 12, 57, // Opcode: RLWINM_rec +/* 7543 */ MCD_OPC_FilterValue, 23, 21, 0, 0, // Skip to: 7569 +/* 7548 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 7551 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7560 +/* 7556 */ MCD_OPC_Decode, 129, 12, 58, // Opcode: RLWNM +/* 7560 */ MCD_OPC_FilterValue, 1, 231, 54, 0, // Skip to: 21620 +/* 7565 */ MCD_OPC_Decode, 132, 12, 58, // Opcode: RLWNM_rec +/* 7569 */ MCD_OPC_FilterValue, 24, 15, 0, 0, // Skip to: 7589 +/* 7574 */ MCD_OPC_CheckField, 0, 26, 0, 4, 0, 0, // Skip to: 7585 +/* 7581 */ MCD_OPC_Decode, 218, 10, 0, // Opcode: NOP +/* 7585 */ MCD_OPC_Decode, 232, 10, 59, // Opcode: ORI +/* 7589 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 7598 +/* 7594 */ MCD_OPC_Decode, 234, 10, 59, // Opcode: ORIS +/* 7598 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 7607 +/* 7603 */ MCD_OPC_Decode, 156, 17, 59, // Opcode: XORI +/* 7607 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 7616 +/* 7612 */ MCD_OPC_Decode, 158, 17, 59, // Opcode: XORIS +/* 7616 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 7625 +/* 7621 */ MCD_OPC_Decode, 156, 3, 59, // Opcode: ANDI_rec +/* 7625 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 7634 +/* 7630 */ MCD_OPC_Decode, 155, 3, 59, // Opcode: ANDIS_rec +/* 7634 */ MCD_OPC_FilterValue, 30, 151, 0, 0, // Skip to: 7790 +/* 7639 */ MCD_OPC_ExtractField, 2, 3, // Inst{4-2} ... +/* 7642 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 7668 +/* 7647 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 7650 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7659 +/* 7655 */ MCD_OPC_Decode, 238, 11, 60, // Opcode: RLDICL +/* 7659 */ MCD_OPC_FilterValue, 1, 132, 54, 0, // Skip to: 21620 +/* 7664 */ MCD_OPC_Decode, 242, 11, 60, // Opcode: RLDICL_rec +/* 7668 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 7694 +/* 7673 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 7676 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7685 +/* 7681 */ MCD_OPC_Decode, 243, 11, 60, // Opcode: RLDICR +/* 7685 */ MCD_OPC_FilterValue, 1, 106, 54, 0, // Skip to: 21620 +/* 7690 */ MCD_OPC_Decode, 245, 11, 60, // Opcode: RLDICR_rec +/* 7694 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 7720 +/* 7699 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 7702 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7711 +/* 7707 */ MCD_OPC_Decode, 237, 11, 60, // Opcode: RLDIC +/* 7711 */ MCD_OPC_FilterValue, 1, 80, 54, 0, // Skip to: 21620 +/* 7716 */ MCD_OPC_Decode, 246, 11, 60, // Opcode: RLDIC_rec +/* 7720 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 7746 +/* 7725 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 7728 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7737 +/* 7733 */ MCD_OPC_Decode, 247, 11, 61, // Opcode: RLDIMI +/* 7737 */ MCD_OPC_FilterValue, 1, 54, 54, 0, // Skip to: 21620 +/* 7742 */ MCD_OPC_Decode, 248, 11, 61, // Opcode: RLDIMI_rec +/* 7746 */ MCD_OPC_FilterValue, 4, 45, 54, 0, // Skip to: 21620 +/* 7751 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 7754 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7763 +/* 7759 */ MCD_OPC_Decode, 233, 11, 62, // Opcode: RLDCL +/* 7763 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 7772 +/* 7768 */ MCD_OPC_Decode, 234, 11, 62, // Opcode: RLDCL_rec +/* 7772 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 7781 +/* 7777 */ MCD_OPC_Decode, 235, 11, 62, // Opcode: RLDCR +/* 7781 */ MCD_OPC_FilterValue, 3, 10, 54, 0, // Skip to: 21620 +/* 7786 */ MCD_OPC_Decode, 236, 11, 62, // Opcode: RLDCR_rec +/* 7790 */ MCD_OPC_FilterValue, 31, 139, 25, 0, // Skip to: 14334 +/* 7795 */ MCD_OPC_ExtractField, 2, 4, // Inst{5-2} ... +/* 7798 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 8070 +/* 7803 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 7806 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7846 +/* 7811 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 7814 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 7830 +/* 7819 */ MCD_OPC_CheckField, 0, 2, 0, 226, 53, 0, // Skip to: 21620 +/* 7826 */ MCD_OPC_Decode, 214, 4, 63, // Opcode: CMPW +/* 7830 */ MCD_OPC_FilterValue, 1, 217, 53, 0, // Skip to: 21620 +/* 7835 */ MCD_OPC_CheckField, 0, 2, 0, 210, 53, 0, // Skip to: 21620 +/* 7842 */ MCD_OPC_Decode, 205, 4, 64, // Opcode: CMPD +/* 7846 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 7886 +/* 7851 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 7854 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 7870 +/* 7859 */ MCD_OPC_CheckField, 0, 2, 0, 186, 53, 0, // Skip to: 21620 +/* 7866 */ MCD_OPC_Decode, 210, 4, 63, // Opcode: CMPLW +/* 7870 */ MCD_OPC_FilterValue, 1, 177, 53, 0, // Skip to: 21620 +/* 7875 */ MCD_OPC_CheckField, 0, 2, 0, 170, 53, 0, // Skip to: 21620 +/* 7882 */ MCD_OPC_Decode, 208, 4, 64, // Opcode: CMPLD +/* 7886 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 7909 +/* 7891 */ MCD_OPC_CheckField, 11, 7, 0, 154, 53, 0, // Skip to: 21620 +/* 7898 */ MCD_OPC_CheckField, 0, 2, 0, 147, 53, 0, // Skip to: 21620 +/* 7905 */ MCD_OPC_Decode, 157, 12, 65, // Opcode: SETB +/* 7909 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 7932 +/* 7914 */ MCD_OPC_CheckField, 22, 1, 0, 131, 53, 0, // Skip to: 21620 +/* 7921 */ MCD_OPC_CheckField, 0, 2, 0, 124, 53, 0, // Skip to: 21620 +/* 7928 */ MCD_OPC_Decode, 212, 4, 66, // Opcode: CMPRB +/* 7932 */ MCD_OPC_FilterValue, 7, 18, 0, 0, // Skip to: 7955 +/* 7937 */ MCD_OPC_CheckField, 21, 2, 0, 108, 53, 0, // Skip to: 21620 +/* 7944 */ MCD_OPC_CheckField, 0, 2, 0, 101, 53, 0, // Skip to: 21620 +/* 7951 */ MCD_OPC_Decode, 207, 4, 64, // Opcode: CMPEQB +/* 7955 */ MCD_OPC_FilterValue, 12, 18, 0, 0, // Skip to: 7978 +/* 7960 */ MCD_OPC_CheckField, 11, 5, 0, 85, 53, 0, // Skip to: 21620 +/* 7967 */ MCD_OPC_CheckField, 0, 2, 0, 78, 53, 0, // Skip to: 21620 +/* 7974 */ MCD_OPC_Decode, 159, 12, 67, // Opcode: SETBC +/* 7978 */ MCD_OPC_FilterValue, 13, 18, 0, 0, // Skip to: 8001 +/* 7983 */ MCD_OPC_CheckField, 11, 5, 0, 62, 53, 0, // Skip to: 21620 +/* 7990 */ MCD_OPC_CheckField, 0, 2, 0, 55, 53, 0, // Skip to: 21620 +/* 7997 */ MCD_OPC_Decode, 161, 12, 67, // Opcode: SETBCR +/* 8001 */ MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 8024 +/* 8006 */ MCD_OPC_CheckField, 11, 5, 0, 39, 53, 0, // Skip to: 21620 +/* 8013 */ MCD_OPC_CheckField, 0, 2, 0, 32, 53, 0, // Skip to: 21620 +/* 8020 */ MCD_OPC_Decode, 164, 12, 67, // Opcode: SETNBC +/* 8024 */ MCD_OPC_FilterValue, 15, 18, 0, 0, // Skip to: 8047 +/* 8029 */ MCD_OPC_CheckField, 11, 5, 0, 16, 53, 0, // Skip to: 21620 +/* 8036 */ MCD_OPC_CheckField, 0, 2, 0, 9, 53, 0, // Skip to: 21620 +/* 8043 */ MCD_OPC_Decode, 166, 12, 67, // Opcode: SETNBCR +/* 8047 */ MCD_OPC_FilterValue, 18, 0, 53, 0, // Skip to: 21620 +/* 8052 */ MCD_OPC_CheckField, 11, 12, 0, 249, 52, 0, // Skip to: 21620 +/* 8059 */ MCD_OPC_CheckField, 0, 2, 0, 242, 52, 0, // Skip to: 21620 +/* 8066 */ MCD_OPC_Decode, 228, 9, 68, // Opcode: MCRXRX +/* 8070 */ MCD_OPC_FilterValue, 1, 74, 0, 0, // Skip to: 8149 +/* 8075 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 8078 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 8101 +/* 8083 */ MCD_OPC_CheckField, 16, 1, 0, 218, 52, 0, // Skip to: 21620 +/* 8090 */ MCD_OPC_CheckField, 1, 1, 1, 211, 52, 0, // Skip to: 21620 +/* 8097 */ MCD_OPC_Decode, 151, 17, 69, // Opcode: WRTEE +/* 8101 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 8117 +/* 8106 */ MCD_OPC_CheckField, 1, 1, 1, 195, 52, 0, // Skip to: 21620 +/* 8113 */ MCD_OPC_Decode, 152, 17, 70, // Opcode: WRTEEI +/* 8117 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 8133 +/* 8122 */ MCD_OPC_CheckField, 0, 2, 2, 179, 52, 0, // Skip to: 21620 +/* 8129 */ MCD_OPC_Decode, 234, 9, 71, // Opcode: MFDCR +/* 8133 */ MCD_OPC_FilterValue, 14, 170, 52, 0, // Skip to: 21620 +/* 8138 */ MCD_OPC_CheckField, 0, 2, 2, 163, 52, 0, // Skip to: 21620 +/* 8145 */ MCD_OPC_Decode, 147, 10, 71, // Opcode: MTDCR +/* 8149 */ MCD_OPC_FilterValue, 2, 49, 0, 0, // Skip to: 8203 +/* 8154 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 8157 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 8187 +/* 8162 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8165 */ MCD_OPC_FilterValue, 0, 138, 52, 0, // Skip to: 21620 +/* 8170 */ MCD_OPC_CheckField, 11, 15, 128, 248, 1, 4, 0, 0, // Skip to: 8183 +/* 8179 */ MCD_OPC_Decode, 135, 14, 0, // Opcode: TRAP +/* 8183 */ MCD_OPC_Decode, 139, 14, 72, // Opcode: TW +/* 8187 */ MCD_OPC_FilterValue, 2, 116, 52, 0, // Skip to: 21620 +/* 8192 */ MCD_OPC_CheckField, 0, 2, 0, 109, 52, 0, // Skip to: 21620 +/* 8199 */ MCD_OPC_Decode, 244, 13, 73, // Opcode: TD +/* 8203 */ MCD_OPC_FilterValue, 3, 157, 1, 0, // Skip to: 8621 +/* 8208 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 8211 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 8237 +/* 8216 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8219 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8228 +/* 8224 */ MCD_OPC_Decode, 168, 9, 74, // Opcode: LVSL +/* 8228 */ MCD_OPC_FilterValue, 2, 75, 52, 0, // Skip to: 21620 +/* 8233 */ MCD_OPC_Decode, 165, 9, 74, // Opcode: LVEBX +/* 8237 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 8263 +/* 8242 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8245 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8254 +/* 8250 */ MCD_OPC_Decode, 169, 9, 74, // Opcode: LVSR +/* 8254 */ MCD_OPC_FilterValue, 2, 49, 52, 0, // Skip to: 21620 +/* 8259 */ MCD_OPC_Decode, 166, 9, 74, // Opcode: LVEHX +/* 8263 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 8279 +/* 8268 */ MCD_OPC_CheckField, 0, 2, 2, 33, 52, 0, // Skip to: 21620 +/* 8275 */ MCD_OPC_Decode, 167, 9, 74, // Opcode: LVEWX +/* 8279 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 8295 +/* 8284 */ MCD_OPC_CheckField, 0, 2, 2, 17, 52, 0, // Skip to: 21620 +/* 8291 */ MCD_OPC_Decode, 170, 9, 74, // Opcode: LVX +/* 8295 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 8311 +/* 8300 */ MCD_OPC_CheckField, 0, 2, 2, 1, 52, 0, // Skip to: 21620 +/* 8307 */ MCD_OPC_Decode, 136, 13, 74, // Opcode: STVEBX +/* 8311 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 8327 +/* 8316 */ MCD_OPC_CheckField, 0, 2, 2, 241, 51, 0, // Skip to: 21620 +/* 8323 */ MCD_OPC_Decode, 137, 13, 74, // Opcode: STVEHX +/* 8327 */ MCD_OPC_FilterValue, 6, 28, 0, 0, // Skip to: 8360 +/* 8332 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8335 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8351 +/* 8340 */ MCD_OPC_CheckField, 25, 1, 0, 217, 51, 0, // Skip to: 21620 +/* 8347 */ MCD_OPC_Decode, 205, 8, 75, // Opcode: ICBLQ +/* 8351 */ MCD_OPC_FilterValue, 2, 208, 51, 0, // Skip to: 21620 +/* 8356 */ MCD_OPC_Decode, 138, 13, 74, // Opcode: STVEWX +/* 8360 */ MCD_OPC_FilterValue, 7, 28, 0, 0, // Skip to: 8393 +/* 8365 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8368 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8384 +/* 8373 */ MCD_OPC_CheckField, 25, 1, 0, 184, 51, 0, // Skip to: 21620 +/* 8380 */ MCD_OPC_Decode, 204, 8, 75, // Opcode: ICBLC +/* 8384 */ MCD_OPC_FilterValue, 2, 175, 51, 0, // Skip to: 21620 +/* 8389 */ MCD_OPC_Decode, 139, 13, 74, // Opcode: STVX +/* 8393 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 8409 +/* 8398 */ MCD_OPC_CheckField, 0, 2, 2, 159, 51, 0, // Skip to: 21620 +/* 8405 */ MCD_OPC_Decode, 171, 9, 74, // Opcode: LVXL +/* 8409 */ MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 8432 +/* 8414 */ MCD_OPC_CheckField, 21, 5, 0, 143, 51, 0, // Skip to: 21620 +/* 8421 */ MCD_OPC_CheckField, 0, 2, 0, 136, 51, 0, // Skip to: 21620 +/* 8428 */ MCD_OPC_Decode, 135, 5, 76, // Opcode: DCCCI +/* 8432 */ MCD_OPC_FilterValue, 15, 28, 0, 0, // Skip to: 8465 +/* 8437 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8440 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8456 +/* 8445 */ MCD_OPC_CheckField, 25, 1, 0, 112, 51, 0, // Skip to: 21620 +/* 8452 */ MCD_OPC_Decode, 207, 8, 75, // Opcode: ICBTLS +/* 8456 */ MCD_OPC_FilterValue, 2, 103, 51, 0, // Skip to: 21620 +/* 8461 */ MCD_OPC_Decode, 140, 13, 74, // Opcode: STVXL +/* 8465 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 8481 +/* 8470 */ MCD_OPC_CheckField, 0, 2, 0, 87, 51, 0, // Skip to: 21620 +/* 8477 */ MCD_OPC_Decode, 175, 9, 77, // Opcode: LWAT +/* 8481 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 8497 +/* 8486 */ MCD_OPC_CheckField, 0, 2, 0, 71, 51, 0, // Skip to: 21620 +/* 8493 */ MCD_OPC_Decode, 231, 8, 78, // Opcode: LDAT +/* 8497 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 8513 +/* 8502 */ MCD_OPC_CheckField, 0, 2, 0, 55, 51, 0, // Skip to: 21620 +/* 8509 */ MCD_OPC_Decode, 143, 13, 77, // Opcode: STWAT +/* 8513 */ MCD_OPC_FilterValue, 23, 11, 0, 0, // Skip to: 8529 +/* 8518 */ MCD_OPC_CheckField, 0, 2, 0, 39, 51, 0, // Skip to: 21620 +/* 8525 */ MCD_OPC_Decode, 224, 12, 78, // Opcode: STDAT +/* 8529 */ MCD_OPC_FilterValue, 24, 18, 0, 0, // Skip to: 8552 +/* 8534 */ MCD_OPC_CheckField, 21, 5, 1, 23, 51, 0, // Skip to: 21620 +/* 8541 */ MCD_OPC_CheckField, 0, 2, 0, 16, 51, 0, // Skip to: 21620 +/* 8548 */ MCD_OPC_Decode, 231, 4, 76, // Opcode: CP_COPY +/* 8552 */ MCD_OPC_FilterValue, 26, 18, 0, 0, // Skip to: 8575 +/* 8557 */ MCD_OPC_CheckField, 11, 15, 0, 0, 51, 0, // Skip to: 21620 +/* 8564 */ MCD_OPC_CheckField, 0, 2, 0, 249, 50, 0, // Skip to: 21620 +/* 8571 */ MCD_OPC_Decode, 230, 4, 0, // Opcode: CP_ABORT +/* 8575 */ MCD_OPC_FilterValue, 28, 18, 0, 0, // Skip to: 8598 +/* 8580 */ MCD_OPC_CheckField, 22, 4, 0, 233, 50, 0, // Skip to: 21620 +/* 8587 */ MCD_OPC_CheckField, 0, 2, 1, 226, 50, 0, // Skip to: 21620 +/* 8594 */ MCD_OPC_Decode, 234, 4, 79, // Opcode: CP_PASTE_rec +/* 8598 */ MCD_OPC_FilterValue, 30, 217, 50, 0, // Skip to: 21620 +/* 8603 */ MCD_OPC_CheckField, 21, 5, 0, 210, 50, 0, // Skip to: 21620 +/* 8610 */ MCD_OPC_CheckField, 0, 2, 0, 203, 50, 0, // Skip to: 21620 +/* 8617 */ MCD_OPC_Decode, 208, 8, 76, // Opcode: ICCCI +/* 8621 */ MCD_OPC_FilterValue, 4, 207, 2, 0, // Skip to: 9345 +/* 8626 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 8629 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 8673 +/* 8634 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8637 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8646 +/* 8642 */ MCD_OPC_Decode, 185, 13, 80, // Opcode: SUBFC +/* 8646 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 8655 +/* 8651 */ MCD_OPC_Decode, 192, 13, 80, // Opcode: SUBFC_rec +/* 8655 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 8664 +/* 8660 */ MCD_OPC_Decode, 185, 10, 81, // Opcode: MULHDU +/* 8664 */ MCD_OPC_FilterValue, 3, 151, 50, 0, // Skip to: 21620 +/* 8669 */ MCD_OPC_Decode, 186, 10, 81, // Opcode: MULHDU_rec +/* 8673 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 8699 +/* 8678 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8681 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8690 +/* 8686 */ MCD_OPC_Decode, 180, 13, 80, // Opcode: SUBF +/* 8690 */ MCD_OPC_FilterValue, 1, 125, 50, 0, // Skip to: 21620 +/* 8695 */ MCD_OPC_Decode, 221, 13, 80, // Opcode: SUBF_rec +/* 8699 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 8725 +/* 8704 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8707 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 8716 +/* 8712 */ MCD_OPC_Decode, 184, 10, 81, // Opcode: MULHD +/* 8716 */ MCD_OPC_FilterValue, 3, 99, 50, 0, // Skip to: 21620 +/* 8721 */ MCD_OPC_Decode, 187, 10, 81, // Opcode: MULHD_rec +/* 8725 */ MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 8765 +/* 8730 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8733 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8749 +/* 8738 */ MCD_OPC_CheckField, 11, 5, 0, 75, 50, 0, // Skip to: 21620 +/* 8745 */ MCD_OPC_Decode, 210, 10, 82, // Opcode: NEG +/* 8749 */ MCD_OPC_FilterValue, 1, 66, 50, 0, // Skip to: 21620 +/* 8754 */ MCD_OPC_CheckField, 11, 5, 0, 59, 50, 0, // Skip to: 21620 +/* 8761 */ MCD_OPC_Decode, 217, 10, 82, // Opcode: NEG_rec +/* 8765 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 8791 +/* 8770 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8773 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8782 +/* 8778 */ MCD_OPC_Decode, 193, 13, 80, // Opcode: SUBFE +/* 8782 */ MCD_OPC_FilterValue, 1, 33, 50, 0, // Skip to: 21620 +/* 8787 */ MCD_OPC_Decode, 200, 13, 80, // Opcode: SUBFE_rec +/* 8791 */ MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 8831 +/* 8796 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8799 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8815 +/* 8804 */ MCD_OPC_CheckField, 11, 5, 0, 9, 50, 0, // Skip to: 21620 +/* 8811 */ MCD_OPC_Decode, 213, 13, 82, // Opcode: SUBFZE +/* 8815 */ MCD_OPC_FilterValue, 1, 0, 50, 0, // Skip to: 21620 +/* 8820 */ MCD_OPC_CheckField, 11, 5, 0, 249, 49, 0, // Skip to: 21620 +/* 8827 */ MCD_OPC_Decode, 220, 13, 82, // Opcode: SUBFZE_rec +/* 8831 */ MCD_OPC_FilterValue, 7, 53, 0, 0, // Skip to: 8889 +/* 8836 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8839 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8855 +/* 8844 */ MCD_OPC_CheckField, 11, 5, 0, 225, 49, 0, // Skip to: 21620 +/* 8851 */ MCD_OPC_Decode, 203, 13, 82, // Opcode: SUBFME +/* 8855 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 8871 +/* 8860 */ MCD_OPC_CheckField, 11, 5, 0, 209, 49, 0, // Skip to: 21620 +/* 8867 */ MCD_OPC_Decode, 210, 13, 82, // Opcode: SUBFME_rec +/* 8871 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 8880 +/* 8876 */ MCD_OPC_Decode, 192, 10, 81, // Opcode: MULLD +/* 8880 */ MCD_OPC_FilterValue, 3, 191, 49, 0, // Skip to: 21620 +/* 8885 */ MCD_OPC_Decode, 195, 10, 81, // Opcode: MULLD_rec +/* 8889 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 8905 +/* 8894 */ MCD_OPC_CheckField, 0, 2, 2, 175, 49, 0, // Skip to: 21620 +/* 8901 */ MCD_OPC_Decode, 137, 10, 81, // Opcode: MODUD +/* 8905 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 8931 +/* 8910 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8913 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 8922 +/* 8918 */ MCD_OPC_Decode, 140, 5, 81, // Opcode: DIVDEU +/* 8922 */ MCD_OPC_FilterValue, 3, 149, 49, 0, // Skip to: 21620 +/* 8927 */ MCD_OPC_Decode, 143, 5, 81, // Opcode: DIVDEU_rec +/* 8931 */ MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 8957 +/* 8936 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8939 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 8948 +/* 8944 */ MCD_OPC_Decode, 137, 5, 81, // Opcode: DIVDE +/* 8948 */ MCD_OPC_FilterValue, 3, 123, 49, 0, // Skip to: 21620 +/* 8953 */ MCD_OPC_Decode, 144, 5, 81, // Opcode: DIVDE_rec +/* 8957 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 8983 +/* 8962 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8965 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 8974 +/* 8970 */ MCD_OPC_Decode, 147, 5, 81, // Opcode: DIVDU +/* 8974 */ MCD_OPC_FilterValue, 3, 97, 49, 0, // Skip to: 21620 +/* 8979 */ MCD_OPC_Decode, 150, 5, 81, // Opcode: DIVDU_rec +/* 8983 */ MCD_OPC_FilterValue, 15, 21, 0, 0, // Skip to: 9009 +/* 8988 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 8991 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9000 +/* 8996 */ MCD_OPC_Decode, 136, 5, 81, // Opcode: DIVD +/* 9000 */ MCD_OPC_FilterValue, 3, 71, 49, 0, // Skip to: 21620 +/* 9005 */ MCD_OPC_Decode, 151, 5, 81, // Opcode: DIVD_rec +/* 9009 */ MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 9035 +/* 9014 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9017 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9026 +/* 9022 */ MCD_OPC_Decode, 190, 13, 80, // Opcode: SUBFCO +/* 9026 */ MCD_OPC_FilterValue, 1, 45, 49, 0, // Skip to: 21620 +/* 9031 */ MCD_OPC_Decode, 191, 13, 80, // Opcode: SUBFCO_rec +/* 9035 */ MCD_OPC_FilterValue, 17, 21, 0, 0, // Skip to: 9061 +/* 9040 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9043 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9052 +/* 9048 */ MCD_OPC_Decode, 211, 13, 80, // Opcode: SUBFO +/* 9052 */ MCD_OPC_FilterValue, 1, 19, 49, 0, // Skip to: 21620 +/* 9057 */ MCD_OPC_Decode, 212, 13, 80, // Opcode: SUBFO_rec +/* 9061 */ MCD_OPC_FilterValue, 19, 35, 0, 0, // Skip to: 9101 +/* 9066 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9069 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9085 +/* 9074 */ MCD_OPC_CheckField, 11, 5, 0, 251, 48, 0, // Skip to: 21620 +/* 9081 */ MCD_OPC_Decode, 215, 10, 82, // Opcode: NEGO +/* 9085 */ MCD_OPC_FilterValue, 1, 242, 48, 0, // Skip to: 21620 +/* 9090 */ MCD_OPC_CheckField, 11, 5, 0, 235, 48, 0, // Skip to: 21620 +/* 9097 */ MCD_OPC_Decode, 216, 10, 82, // Opcode: NEGO_rec +/* 9101 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 9127 +/* 9106 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9109 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9118 +/* 9114 */ MCD_OPC_Decode, 198, 13, 80, // Opcode: SUBFEO +/* 9118 */ MCD_OPC_FilterValue, 1, 209, 48, 0, // Skip to: 21620 +/* 9123 */ MCD_OPC_Decode, 199, 13, 80, // Opcode: SUBFEO_rec +/* 9127 */ MCD_OPC_FilterValue, 22, 35, 0, 0, // Skip to: 9167 +/* 9132 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9135 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9151 +/* 9140 */ MCD_OPC_CheckField, 11, 5, 0, 185, 48, 0, // Skip to: 21620 +/* 9147 */ MCD_OPC_Decode, 218, 13, 82, // Opcode: SUBFZEO +/* 9151 */ MCD_OPC_FilterValue, 1, 176, 48, 0, // Skip to: 21620 +/* 9156 */ MCD_OPC_CheckField, 11, 5, 0, 169, 48, 0, // Skip to: 21620 +/* 9163 */ MCD_OPC_Decode, 219, 13, 82, // Opcode: SUBFZEO_rec +/* 9167 */ MCD_OPC_FilterValue, 23, 53, 0, 0, // Skip to: 9225 +/* 9172 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9175 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9191 +/* 9180 */ MCD_OPC_CheckField, 11, 5, 0, 145, 48, 0, // Skip to: 21620 +/* 9187 */ MCD_OPC_Decode, 208, 13, 82, // Opcode: SUBFMEO +/* 9191 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 9207 +/* 9196 */ MCD_OPC_CheckField, 11, 5, 0, 129, 48, 0, // Skip to: 21620 +/* 9203 */ MCD_OPC_Decode, 209, 13, 82, // Opcode: SUBFMEO_rec +/* 9207 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9216 +/* 9212 */ MCD_OPC_Decode, 193, 10, 81, // Opcode: MULLDO +/* 9216 */ MCD_OPC_FilterValue, 3, 111, 48, 0, // Skip to: 21620 +/* 9221 */ MCD_OPC_Decode, 194, 10, 81, // Opcode: MULLDO_rec +/* 9225 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 9241 +/* 9230 */ MCD_OPC_CheckField, 0, 2, 2, 95, 48, 0, // Skip to: 21620 +/* 9237 */ MCD_OPC_Decode, 135, 10, 81, // Opcode: MODSD +/* 9241 */ MCD_OPC_FilterValue, 28, 21, 0, 0, // Skip to: 9267 +/* 9246 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9249 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9258 +/* 9254 */ MCD_OPC_Decode, 141, 5, 81, // Opcode: DIVDEUO +/* 9258 */ MCD_OPC_FilterValue, 3, 69, 48, 0, // Skip to: 21620 +/* 9263 */ MCD_OPC_Decode, 142, 5, 81, // Opcode: DIVDEUO_rec +/* 9267 */ MCD_OPC_FilterValue, 29, 21, 0, 0, // Skip to: 9293 +/* 9272 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9275 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9284 +/* 9280 */ MCD_OPC_Decode, 138, 5, 81, // Opcode: DIVDEO +/* 9284 */ MCD_OPC_FilterValue, 3, 43, 48, 0, // Skip to: 21620 +/* 9289 */ MCD_OPC_Decode, 139, 5, 81, // Opcode: DIVDEO_rec +/* 9293 */ MCD_OPC_FilterValue, 30, 21, 0, 0, // Skip to: 9319 +/* 9298 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9301 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9310 +/* 9306 */ MCD_OPC_Decode, 148, 5, 81, // Opcode: DIVDUO +/* 9310 */ MCD_OPC_FilterValue, 3, 17, 48, 0, // Skip to: 21620 +/* 9315 */ MCD_OPC_Decode, 149, 5, 81, // Opcode: DIVDUO_rec +/* 9319 */ MCD_OPC_FilterValue, 31, 8, 48, 0, // Skip to: 21620 +/* 9324 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9327 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9336 +/* 9332 */ MCD_OPC_Decode, 145, 5, 81, // Opcode: DIVDO +/* 9336 */ MCD_OPC_FilterValue, 3, 247, 47, 0, // Skip to: 21620 +/* 9341 */ MCD_OPC_Decode, 146, 5, 81, // Opcode: DIVDO_rec +/* 9345 */ MCD_OPC_FilterValue, 5, 119, 2, 0, // Skip to: 9981 +/* 9350 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... +/* 9353 */ MCD_OPC_FilterValue, 0, 142, 0, 0, // Skip to: 9500 +/* 9358 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9361 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 9405 +/* 9366 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9369 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9378 +/* 9374 */ MCD_OPC_Decode, 211, 2, 80, // Opcode: ADDC +/* 9378 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9387 +/* 9383 */ MCD_OPC_Decode, 200, 2, 80, // Opcode: ADD4 +/* 9387 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9396 +/* 9392 */ MCD_OPC_Decode, 216, 2, 80, // Opcode: ADDCO +/* 9396 */ MCD_OPC_FilterValue, 3, 187, 47, 0, // Skip to: 21620 +/* 9401 */ MCD_OPC_Decode, 201, 2, 80, // Opcode: ADD4O +/* 9405 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 9449 +/* 9410 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9413 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9422 +/* 9418 */ MCD_OPC_Decode, 218, 2, 80, // Opcode: ADDC_rec +/* 9422 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9431 +/* 9427 */ MCD_OPC_Decode, 204, 2, 80, // Opcode: ADD4_rec +/* 9431 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9440 +/* 9436 */ MCD_OPC_Decode, 217, 2, 80, // Opcode: ADDCO_rec +/* 9440 */ MCD_OPC_FilterValue, 3, 143, 47, 0, // Skip to: 21620 +/* 9445 */ MCD_OPC_Decode, 202, 2, 80, // Opcode: ADD4O_rec +/* 9449 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 9484 +/* 9454 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9457 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9466 +/* 9462 */ MCD_OPC_Decode, 189, 10, 80, // Opcode: MULHWU +/* 9466 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9475 +/* 9471 */ MCD_OPC_Decode, 138, 10, 80, // Opcode: MODUW +/* 9475 */ MCD_OPC_FilterValue, 3, 108, 47, 0, // Skip to: 21620 +/* 9480 */ MCD_OPC_Decode, 136, 10, 80, // Opcode: MODSW +/* 9484 */ MCD_OPC_FilterValue, 3, 99, 47, 0, // Skip to: 21620 +/* 9489 */ MCD_OPC_CheckField, 9, 2, 0, 92, 47, 0, // Skip to: 21620 +/* 9496 */ MCD_OPC_Decode, 190, 10, 80, // Opcode: MULHWU_rec +/* 9500 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 9540 +/* 9505 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9508 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 9524 +/* 9513 */ MCD_OPC_CheckField, 9, 2, 0, 68, 47, 0, // Skip to: 21620 +/* 9520 */ MCD_OPC_Decode, 188, 10, 80, // Opcode: MULHW +/* 9524 */ MCD_OPC_FilterValue, 3, 59, 47, 0, // Skip to: 21620 +/* 9529 */ MCD_OPC_CheckField, 9, 2, 0, 52, 47, 0, // Skip to: 21620 +/* 9536 */ MCD_OPC_Decode, 191, 10, 80, // Opcode: MULHW_rec +/* 9540 */ MCD_OPC_FilterValue, 4, 107, 0, 0, // Skip to: 9652 +/* 9545 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9548 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 9574 +/* 9553 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9556 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9565 +/* 9561 */ MCD_OPC_Decode, 219, 2, 80, // Opcode: ADDE +/* 9565 */ MCD_OPC_FilterValue, 2, 18, 47, 0, // Skip to: 21620 +/* 9570 */ MCD_OPC_Decode, 224, 2, 80, // Opcode: ADDEO +/* 9574 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 9600 +/* 9579 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9582 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9591 +/* 9587 */ MCD_OPC_Decode, 228, 2, 80, // Opcode: ADDE_rec +/* 9591 */ MCD_OPC_FilterValue, 2, 248, 46, 0, // Skip to: 21620 +/* 9596 */ MCD_OPC_Decode, 225, 2, 80, // Opcode: ADDEO_rec +/* 9600 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 9626 +/* 9605 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9608 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9617 +/* 9613 */ MCD_OPC_Decode, 156, 5, 80, // Opcode: DIVWEU +/* 9617 */ MCD_OPC_FilterValue, 3, 222, 46, 0, // Skip to: 21620 +/* 9622 */ MCD_OPC_Decode, 157, 5, 80, // Opcode: DIVWEUO +/* 9626 */ MCD_OPC_FilterValue, 3, 213, 46, 0, // Skip to: 21620 +/* 9631 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9634 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9643 +/* 9639 */ MCD_OPC_Decode, 159, 5, 80, // Opcode: DIVWEU_rec +/* 9643 */ MCD_OPC_FilterValue, 3, 196, 46, 0, // Skip to: 21620 +/* 9648 */ MCD_OPC_Decode, 158, 5, 80, // Opcode: DIVWEUO_rec +/* 9652 */ MCD_OPC_FilterValue, 5, 64, 0, 0, // Skip to: 9721 +/* 9657 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9660 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9669 +/* 9665 */ MCD_OPC_Decode, 226, 2, 83, // Opcode: ADDEX +/* 9669 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 9695 +/* 9674 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9677 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9686 +/* 9682 */ MCD_OPC_Decode, 153, 5, 80, // Opcode: DIVWE +/* 9686 */ MCD_OPC_FilterValue, 3, 153, 46, 0, // Skip to: 21620 +/* 9691 */ MCD_OPC_Decode, 154, 5, 80, // Opcode: DIVWEO +/* 9695 */ MCD_OPC_FilterValue, 3, 144, 46, 0, // Skip to: 21620 +/* 9700 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9703 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9712 +/* 9708 */ MCD_OPC_Decode, 160, 5, 80, // Opcode: DIVWE_rec +/* 9712 */ MCD_OPC_FilterValue, 3, 127, 46, 0, // Skip to: 21620 +/* 9717 */ MCD_OPC_Decode, 155, 5, 80, // Opcode: DIVWEO_rec +/* 9721 */ MCD_OPC_FilterValue, 6, 107, 0, 0, // Skip to: 9833 +/* 9726 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9729 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 9755 +/* 9734 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... /* 9737 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9746 -/* 9742 */ MCD_OPC_Decode, 227, 14, 111, // Opcode: XOR -/* 9746 */ MCD_OPC_FilterValue, 1, 27, 26, 0, // Skip to: 16434 -/* 9751 */ MCD_OPC_Decode, 234, 14, 111, // Opcode: XORo -/* 9755 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 9781 -/* 9760 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9742 */ MCD_OPC_Decode, 136, 3, 82, // Opcode: ADDZE +/* 9746 */ MCD_OPC_FilterValue, 2, 93, 46, 0, // Skip to: 21620 +/* 9751 */ MCD_OPC_Decode, 141, 3, 82, // Opcode: ADDZEO +/* 9755 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 9781 +/* 9760 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... /* 9763 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9772 -/* 9768 */ MCD_OPC_Decode, 131, 9, 111, // Opcode: ORC -/* 9772 */ MCD_OPC_FilterValue, 1, 1, 26, 0, // Skip to: 16434 -/* 9777 */ MCD_OPC_Decode, 134, 9, 111, // Opcode: ORCo -/* 9781 */ MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 9807 -/* 9786 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9789 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9798 -/* 9794 */ MCD_OPC_Decode, 128, 9, 111, // Opcode: OR -/* 9798 */ MCD_OPC_FilterValue, 1, 231, 25, 0, // Skip to: 16434 -/* 9803 */ MCD_OPC_Decode, 139, 9, 111, // Opcode: ORo -/* 9807 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 9833 -/* 9812 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9815 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9824 -/* 9820 */ MCD_OPC_Decode, 240, 8, 111, // Opcode: NAND -/* 9824 */ MCD_OPC_FilterValue, 1, 205, 25, 0, // Skip to: 16434 -/* 9829 */ MCD_OPC_Decode, 243, 8, 111, // Opcode: NANDo -/* 9833 */ MCD_OPC_FilterValue, 15, 196, 25, 0, // Skip to: 16434 -/* 9838 */ MCD_OPC_CheckField, 0, 2, 0, 189, 25, 0, // Skip to: 16434 -/* 9845 */ MCD_OPC_Decode, 165, 3, 111, // Opcode: CMPB -/* 9849 */ MCD_OPC_FilterValue, 15, 180, 25, 0, // Skip to: 16434 -/* 9854 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 9857 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 9897 -/* 9862 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 9865 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 9888 -/* 9870 */ MCD_OPC_CheckField, 23, 3, 0, 157, 25, 0, // Skip to: 16434 -/* 9877 */ MCD_OPC_CheckField, 11, 10, 0, 150, 25, 0, // Skip to: 16434 -/* 9884 */ MCD_OPC_Decode, 224, 14, 104, // Opcode: WAIT -/* 9888 */ MCD_OPC_FilterValue, 2, 141, 25, 0, // Skip to: 16434 -/* 9893 */ MCD_OPC_Decode, 240, 7, 93, // Opcode: LWEPX -/* 9897 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 9920 -/* 9902 */ MCD_OPC_CheckField, 21, 5, 0, 125, 25, 0, // Skip to: 16434 -/* 9909 */ MCD_OPC_CheckField, 0, 2, 2, 118, 25, 0, // Skip to: 16434 -/* 9916 */ MCD_OPC_Decode, 216, 3, 97, // Opcode: DCBSTEP -/* 9920 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 9936 -/* 9925 */ MCD_OPC_CheckField, 0, 2, 2, 102, 25, 0, // Skip to: 16434 -/* 9932 */ MCD_OPC_Decode, 149, 7, 93, // Opcode: LBEPX -/* 9936 */ MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 9959 -/* 9941 */ MCD_OPC_CheckField, 21, 5, 0, 86, 25, 0, // Skip to: 16434 -/* 9948 */ MCD_OPC_CheckField, 0, 2, 2, 79, 25, 0, // Skip to: 16434 -/* 9955 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: DCBFEP -/* 9959 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 9975 -/* 9964 */ MCD_OPC_CheckField, 0, 2, 2, 63, 25, 0, // Skip to: 16434 -/* 9971 */ MCD_OPC_Decode, 222, 11, 93, // Opcode: STWEPX -/* 9975 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 9991 -/* 9980 */ MCD_OPC_CheckField, 0, 2, 2, 47, 25, 0, // Skip to: 16434 -/* 9987 */ MCD_OPC_Decode, 163, 11, 93, // Opcode: STBEPX -/* 9991 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 10007 -/* 9996 */ MCD_OPC_CheckField, 0, 2, 2, 31, 25, 0, // Skip to: 16434 -/* 10003 */ MCD_OPC_Decode, 220, 3, 118, // Opcode: DCBTSTEP -/* 10007 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 10023 -/* 10012 */ MCD_OPC_CheckField, 0, 2, 2, 15, 25, 0, // Skip to: 16434 -/* 10019 */ MCD_OPC_Decode, 204, 7, 93, // Opcode: LHEPX -/* 10023 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 10039 -/* 10028 */ MCD_OPC_CheckField, 0, 2, 2, 255, 24, 0, // Skip to: 16434 -/* 10035 */ MCD_OPC_Decode, 218, 3, 118, // Opcode: DCBTEP -/* 10039 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 10055 -/* 10044 */ MCD_OPC_CheckField, 0, 2, 2, 239, 24, 0, // Skip to: 16434 -/* 10051 */ MCD_OPC_Decode, 198, 11, 93, // Opcode: STHEPX -/* 10055 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 10071 -/* 10060 */ MCD_OPC_CheckField, 0, 2, 2, 223, 24, 0, // Skip to: 16434 -/* 10067 */ MCD_OPC_Decode, 182, 7, 105, // Opcode: LFDEPX -/* 10071 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 10087 -/* 10076 */ MCD_OPC_CheckField, 0, 2, 2, 207, 24, 0, // Skip to: 16434 -/* 10083 */ MCD_OPC_Decode, 184, 11, 105, // Opcode: STFDEPX -/* 10087 */ MCD_OPC_FilterValue, 30, 18, 0, 0, // Skip to: 10110 -/* 10092 */ MCD_OPC_CheckField, 21, 5, 0, 191, 24, 0, // Skip to: 16434 -/* 10099 */ MCD_OPC_CheckField, 0, 2, 2, 184, 24, 0, // Skip to: 16434 -/* 10106 */ MCD_OPC_Decode, 137, 7, 97, // Opcode: ICBIEP -/* 10110 */ MCD_OPC_FilterValue, 31, 175, 24, 0, // Skip to: 16434 -/* 10115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 10118 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 10134 -/* 10123 */ MCD_OPC_CheckField, 0, 2, 2, 160, 24, 0, // Skip to: 16434 -/* 10130 */ MCD_OPC_Decode, 222, 3, 97, // Opcode: DCBZEP -/* 10134 */ MCD_OPC_FilterValue, 1, 151, 24, 0, // Skip to: 16434 -/* 10139 */ MCD_OPC_CheckField, 0, 2, 2, 144, 24, 0, // Skip to: 16434 -/* 10146 */ MCD_OPC_Decode, 224, 3, 97, // Opcode: DCBZLEP -/* 10150 */ MCD_OPC_FilterValue, 32, 4, 0, 0, // Skip to: 10159 -/* 10155 */ MCD_OPC_Decode, 241, 7, 119, // Opcode: LWZ -/* 10159 */ MCD_OPC_FilterValue, 33, 4, 0, 0, // Skip to: 10168 -/* 10164 */ MCD_OPC_Decode, 244, 7, 119, // Opcode: LWZU -/* 10168 */ MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 10177 -/* 10173 */ MCD_OPC_Decode, 150, 7, 119, // Opcode: LBZ -/* 10177 */ MCD_OPC_FilterValue, 35, 4, 0, 0, // Skip to: 10186 -/* 10182 */ MCD_OPC_Decode, 153, 7, 119, // Opcode: LBZU -/* 10186 */ MCD_OPC_FilterValue, 36, 4, 0, 0, // Skip to: 10195 -/* 10191 */ MCD_OPC_Decode, 216, 11, 119, // Opcode: STW -/* 10195 */ MCD_OPC_FilterValue, 37, 4, 0, 0, // Skip to: 10204 -/* 10200 */ MCD_OPC_Decode, 223, 11, 119, // Opcode: STWU -/* 10204 */ MCD_OPC_FilterValue, 38, 4, 0, 0, // Skip to: 10213 -/* 10209 */ MCD_OPC_Decode, 159, 11, 119, // Opcode: STB -/* 10213 */ MCD_OPC_FilterValue, 39, 4, 0, 0, // Skip to: 10222 -/* 10218 */ MCD_OPC_Decode, 164, 11, 119, // Opcode: STBU -/* 10222 */ MCD_OPC_FilterValue, 40, 4, 0, 0, // Skip to: 10231 -/* 10227 */ MCD_OPC_Decode, 205, 7, 119, // Opcode: LHZ -/* 10231 */ MCD_OPC_FilterValue, 41, 4, 0, 0, // Skip to: 10240 -/* 10236 */ MCD_OPC_Decode, 208, 7, 119, // Opcode: LHZU -/* 10240 */ MCD_OPC_FilterValue, 42, 4, 0, 0, // Skip to: 10249 -/* 10245 */ MCD_OPC_Decode, 192, 7, 119, // Opcode: LHA -/* 10249 */ MCD_OPC_FilterValue, 43, 4, 0, 0, // Skip to: 10258 -/* 10254 */ MCD_OPC_Decode, 196, 7, 119, // Opcode: LHAU -/* 10258 */ MCD_OPC_FilterValue, 44, 4, 0, 0, // Skip to: 10267 -/* 10263 */ MCD_OPC_Decode, 193, 11, 119, // Opcode: STH -/* 10267 */ MCD_OPC_FilterValue, 45, 4, 0, 0, // Skip to: 10276 -/* 10272 */ MCD_OPC_Decode, 199, 11, 119, // Opcode: STHU -/* 10276 */ MCD_OPC_FilterValue, 46, 4, 0, 0, // Skip to: 10285 -/* 10281 */ MCD_OPC_Decode, 221, 7, 119, // Opcode: LMW -/* 10285 */ MCD_OPC_FilterValue, 47, 4, 0, 0, // Skip to: 10294 -/* 10290 */ MCD_OPC_Decode, 208, 11, 119, // Opcode: STMW -/* 10294 */ MCD_OPC_FilterValue, 48, 4, 0, 0, // Skip to: 10303 -/* 10299 */ MCD_OPC_Decode, 188, 7, 120, // Opcode: LFS -/* 10303 */ MCD_OPC_FilterValue, 49, 4, 0, 0, // Skip to: 10312 -/* 10308 */ MCD_OPC_Decode, 189, 7, 120, // Opcode: LFSU -/* 10312 */ MCD_OPC_FilterValue, 50, 4, 0, 0, // Skip to: 10321 -/* 10317 */ MCD_OPC_Decode, 181, 7, 121, // Opcode: LFD -/* 10321 */ MCD_OPC_FilterValue, 51, 4, 0, 0, // Skip to: 10330 -/* 10326 */ MCD_OPC_Decode, 183, 7, 121, // Opcode: LFDU -/* 10330 */ MCD_OPC_FilterValue, 52, 4, 0, 0, // Skip to: 10339 -/* 10335 */ MCD_OPC_Decode, 189, 11, 120, // Opcode: STFS -/* 10339 */ MCD_OPC_FilterValue, 53, 4, 0, 0, // Skip to: 10348 -/* 10344 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: STFSU -/* 10348 */ MCD_OPC_FilterValue, 54, 4, 0, 0, // Skip to: 10357 -/* 10353 */ MCD_OPC_Decode, 183, 11, 121, // Opcode: STFD -/* 10357 */ MCD_OPC_FilterValue, 55, 4, 0, 0, // Skip to: 10366 -/* 10362 */ MCD_OPC_Decode, 185, 11, 121, // Opcode: STFDU -/* 10366 */ MCD_OPC_FilterValue, 57, 21, 0, 0, // Skip to: 10392 -/* 10371 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 10374 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 10383 -/* 10379 */ MCD_OPC_Decode, 254, 7, 122, // Opcode: LXSD -/* 10383 */ MCD_OPC_FilterValue, 3, 158, 23, 0, // Skip to: 16434 -/* 10388 */ MCD_OPC_Decode, 132, 8, 122, // Opcode: LXSSP -/* 10392 */ MCD_OPC_FilterValue, 58, 30, 0, 0, // Skip to: 10427 -/* 10397 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 10400 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10409 -/* 10405 */ MCD_OPC_Decode, 162, 7, 123, // Opcode: LD -/* 10409 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 10418 -/* 10414 */ MCD_OPC_Decode, 169, 7, 123, // Opcode: LDU -/* 10418 */ MCD_OPC_FilterValue, 2, 123, 23, 0, // Skip to: 16434 -/* 10423 */ MCD_OPC_Decode, 230, 7, 123, // Opcode: LWA -/* 10427 */ MCD_OPC_FilterValue, 59, 173, 1, 0, // Skip to: 10861 -/* 10432 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 10435 */ MCD_OPC_FilterValue, 28, 35, 0, 0, // Skip to: 10475 -/* 10440 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 10443 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 10459 -/* 10448 */ MCD_OPC_CheckField, 16, 5, 0, 91, 23, 0, // Skip to: 16434 -/* 10455 */ MCD_OPC_Decode, 156, 6, 124, // Opcode: FCFIDS -/* 10459 */ MCD_OPC_FilterValue, 30, 82, 23, 0, // Skip to: 16434 -/* 10464 */ MCD_OPC_CheckField, 16, 5, 0, 75, 23, 0, // Skip to: 16434 -/* 10471 */ MCD_OPC_Decode, 159, 6, 124, // Opcode: FCFIDUS -/* 10475 */ MCD_OPC_FilterValue, 29, 35, 0, 0, // Skip to: 10515 -/* 10480 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 10483 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 10499 -/* 10488 */ MCD_OPC_CheckField, 16, 5, 0, 51, 23, 0, // Skip to: 16434 -/* 10495 */ MCD_OPC_Decode, 157, 6, 124, // Opcode: FCFIDSo -/* 10499 */ MCD_OPC_FilterValue, 30, 42, 23, 0, // Skip to: 16434 -/* 10504 */ MCD_OPC_CheckField, 16, 5, 0, 35, 23, 0, // Skip to: 16434 -/* 10511 */ MCD_OPC_Decode, 160, 6, 124, // Opcode: FCFIDUSo -/* 10515 */ MCD_OPC_FilterValue, 36, 11, 0, 0, // Skip to: 10531 -/* 10520 */ MCD_OPC_CheckField, 6, 5, 0, 19, 23, 0, // Skip to: 16434 -/* 10527 */ MCD_OPC_Decode, 186, 6, 125, // Opcode: FDIVS -/* 10531 */ MCD_OPC_FilterValue, 37, 11, 0, 0, // Skip to: 10547 -/* 10536 */ MCD_OPC_CheckField, 6, 5, 0, 3, 23, 0, // Skip to: 16434 -/* 10543 */ MCD_OPC_Decode, 187, 6, 125, // Opcode: FDIVSo -/* 10547 */ MCD_OPC_FilterValue, 40, 11, 0, 0, // Skip to: 10563 -/* 10552 */ MCD_OPC_CheckField, 6, 5, 0, 243, 22, 0, // Skip to: 16434 -/* 10559 */ MCD_OPC_Decode, 254, 6, 125, // Opcode: FSUBS -/* 10563 */ MCD_OPC_FilterValue, 41, 11, 0, 0, // Skip to: 10579 -/* 10568 */ MCD_OPC_CheckField, 6, 5, 0, 227, 22, 0, // Skip to: 16434 -/* 10575 */ MCD_OPC_Decode, 255, 6, 125, // Opcode: FSUBSo -/* 10579 */ MCD_OPC_FilterValue, 42, 11, 0, 0, // Skip to: 10595 -/* 10584 */ MCD_OPC_CheckField, 6, 5, 0, 211, 22, 0, // Skip to: 16434 -/* 10591 */ MCD_OPC_Decode, 151, 6, 125, // Opcode: FADDS -/* 10595 */ MCD_OPC_FilterValue, 43, 11, 0, 0, // Skip to: 10611 -/* 10600 */ MCD_OPC_CheckField, 6, 5, 0, 195, 22, 0, // Skip to: 16434 -/* 10607 */ MCD_OPC_Decode, 152, 6, 125, // Opcode: FADDSo -/* 10611 */ MCD_OPC_FilterValue, 44, 18, 0, 0, // Skip to: 10634 -/* 10616 */ MCD_OPC_CheckField, 16, 5, 0, 179, 22, 0, // Skip to: 16434 -/* 10623 */ MCD_OPC_CheckField, 6, 5, 0, 172, 22, 0, // Skip to: 16434 -/* 10630 */ MCD_OPC_Decode, 250, 6, 126, // Opcode: FSQRTS -/* 10634 */ MCD_OPC_FilterValue, 45, 18, 0, 0, // Skip to: 10657 -/* 10639 */ MCD_OPC_CheckField, 16, 5, 0, 156, 22, 0, // Skip to: 16434 -/* 10646 */ MCD_OPC_CheckField, 6, 5, 0, 149, 22, 0, // Skip to: 16434 -/* 10653 */ MCD_OPC_Decode, 251, 6, 126, // Opcode: FSQRTSo -/* 10657 */ MCD_OPC_FilterValue, 48, 18, 0, 0, // Skip to: 10680 -/* 10662 */ MCD_OPC_CheckField, 16, 5, 0, 133, 22, 0, // Skip to: 16434 -/* 10669 */ MCD_OPC_CheckField, 6, 5, 0, 126, 22, 0, // Skip to: 16434 -/* 10676 */ MCD_OPC_Decode, 220, 6, 126, // Opcode: FRES -/* 10680 */ MCD_OPC_FilterValue, 49, 18, 0, 0, // Skip to: 10703 -/* 10685 */ MCD_OPC_CheckField, 16, 5, 0, 110, 22, 0, // Skip to: 16434 -/* 10692 */ MCD_OPC_CheckField, 6, 5, 0, 103, 22, 0, // Skip to: 16434 -/* 10699 */ MCD_OPC_Decode, 221, 6, 126, // Opcode: FRESo -/* 10703 */ MCD_OPC_FilterValue, 50, 11, 0, 0, // Skip to: 10719 -/* 10708 */ MCD_OPC_CheckField, 11, 5, 0, 87, 22, 0, // Skip to: 16434 -/* 10715 */ MCD_OPC_Decode, 200, 6, 127, // Opcode: FMULS -/* 10719 */ MCD_OPC_FilterValue, 51, 11, 0, 0, // Skip to: 10735 -/* 10724 */ MCD_OPC_CheckField, 11, 5, 0, 71, 22, 0, // Skip to: 16434 -/* 10731 */ MCD_OPC_Decode, 201, 6, 127, // Opcode: FMULSo -/* 10735 */ MCD_OPC_FilterValue, 52, 18, 0, 0, // Skip to: 10758 -/* 10740 */ MCD_OPC_CheckField, 16, 5, 0, 55, 22, 0, // Skip to: 16434 -/* 10747 */ MCD_OPC_CheckField, 6, 5, 0, 48, 22, 0, // Skip to: 16434 -/* 10754 */ MCD_OPC_Decode, 242, 6, 126, // Opcode: FRSQRTES -/* 10758 */ MCD_OPC_FilterValue, 53, 18, 0, 0, // Skip to: 10781 -/* 10763 */ MCD_OPC_CheckField, 16, 5, 0, 32, 22, 0, // Skip to: 16434 -/* 10770 */ MCD_OPC_CheckField, 6, 5, 0, 25, 22, 0, // Skip to: 16434 -/* 10777 */ MCD_OPC_Decode, 243, 6, 126, // Opcode: FRSQRTESo -/* 10781 */ MCD_OPC_FilterValue, 56, 5, 0, 0, // Skip to: 10791 -/* 10786 */ MCD_OPC_Decode, 196, 6, 128, 1, // Opcode: FMSUBS -/* 10791 */ MCD_OPC_FilterValue, 57, 5, 0, 0, // Skip to: 10801 -/* 10796 */ MCD_OPC_Decode, 197, 6, 128, 1, // Opcode: FMSUBSo -/* 10801 */ MCD_OPC_FilterValue, 58, 5, 0, 0, // Skip to: 10811 -/* 10806 */ MCD_OPC_Decode, 190, 6, 128, 1, // Opcode: FMADDS -/* 10811 */ MCD_OPC_FilterValue, 59, 5, 0, 0, // Skip to: 10821 -/* 10816 */ MCD_OPC_Decode, 191, 6, 128, 1, // Opcode: FMADDSo -/* 10821 */ MCD_OPC_FilterValue, 60, 5, 0, 0, // Skip to: 10831 -/* 10826 */ MCD_OPC_Decode, 216, 6, 128, 1, // Opcode: FNMSUBS -/* 10831 */ MCD_OPC_FilterValue, 61, 5, 0, 0, // Skip to: 10841 -/* 10836 */ MCD_OPC_Decode, 217, 6, 128, 1, // Opcode: FNMSUBSo -/* 10841 */ MCD_OPC_FilterValue, 62, 5, 0, 0, // Skip to: 10851 -/* 10846 */ MCD_OPC_Decode, 212, 6, 128, 1, // Opcode: FNMADDS -/* 10851 */ MCD_OPC_FilterValue, 63, 202, 21, 0, // Skip to: 16434 -/* 10856 */ MCD_OPC_Decode, 213, 6, 128, 1, // Opcode: FNMADDSo -/* 10861 */ MCD_OPC_FilterValue, 60, 242, 13, 0, // Skip to: 14436 -/* 10866 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... -/* 10869 */ MCD_OPC_FilterValue, 0, 120, 3, 0, // Skip to: 11762 -/* 10874 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 10877 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 10905 -/* 10882 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 10885 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 10895 -/* 10890 */ MCD_OPC_Decode, 240, 14, 129, 1, // Opcode: XSADDSP -/* 10895 */ MCD_OPC_FilterValue, 1, 158, 21, 0, // Skip to: 16434 -/* 10900 */ MCD_OPC_Decode, 158, 15, 130, 1, // Opcode: XSMADDASP -/* 10905 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 10933 -/* 10910 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 10913 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 10923 -/* 10918 */ MCD_OPC_Decode, 215, 15, 129, 1, // Opcode: XSSUBSP -/* 10923 */ MCD_OPC_FilterValue, 1, 130, 21, 0, // Skip to: 16434 -/* 10928 */ MCD_OPC_Decode, 160, 15, 130, 1, // Opcode: XSMADDMSP -/* 10933 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 10961 -/* 10938 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 10941 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 10951 -/* 10946 */ MCD_OPC_Decode, 178, 15, 129, 1, // Opcode: XSMULSP -/* 10951 */ MCD_OPC_FilterValue, 1, 102, 21, 0, // Skip to: 16434 -/* 10956 */ MCD_OPC_Decode, 170, 15, 130, 1, // Opcode: XSMSUBASP -/* 10961 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 10989 -/* 10966 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 10969 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 10979 -/* 10974 */ MCD_OPC_Decode, 154, 15, 129, 1, // Opcode: XSDIVSP -/* 10979 */ MCD_OPC_FilterValue, 1, 74, 21, 0, // Skip to: 16434 -/* 10984 */ MCD_OPC_Decode, 172, 15, 130, 1, // Opcode: XSMSUBMSP -/* 10989 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 11017 -/* 10994 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 10997 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11007 -/* 11002 */ MCD_OPC_Decode, 237, 14, 131, 1, // Opcode: XSADDDP -/* 11007 */ MCD_OPC_FilterValue, 1, 46, 21, 0, // Skip to: 16434 -/* 11012 */ MCD_OPC_Decode, 157, 15, 132, 1, // Opcode: XSMADDADP -/* 11017 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 11045 -/* 11022 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11025 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11035 -/* 11030 */ MCD_OPC_Decode, 212, 15, 131, 1, // Opcode: XSSUBDP -/* 11035 */ MCD_OPC_FilterValue, 1, 18, 21, 0, // Skip to: 16434 -/* 11040 */ MCD_OPC_Decode, 159, 15, 132, 1, // Opcode: XSMADDMDP -/* 11045 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 11073 -/* 11050 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11053 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11063 -/* 11058 */ MCD_OPC_Decode, 175, 15, 131, 1, // Opcode: XSMULDP -/* 11063 */ MCD_OPC_FilterValue, 1, 246, 20, 0, // Skip to: 16434 -/* 11068 */ MCD_OPC_Decode, 169, 15, 132, 1, // Opcode: XSMSUBADP -/* 11073 */ MCD_OPC_FilterValue, 7, 23, 0, 0, // Skip to: 11101 -/* 11078 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11081 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11091 -/* 11086 */ MCD_OPC_Decode, 151, 15, 131, 1, // Opcode: XSDIVDP -/* 11091 */ MCD_OPC_FilterValue, 1, 218, 20, 0, // Skip to: 16434 -/* 11096 */ MCD_OPC_Decode, 171, 15, 132, 1, // Opcode: XSMSUBMDP -/* 11101 */ MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 11129 -/* 11106 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11109 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11119 -/* 11114 */ MCD_OPC_Decode, 228, 15, 133, 1, // Opcode: XVADDSP -/* 11119 */ MCD_OPC_FilterValue, 1, 190, 20, 0, // Skip to: 16434 -/* 11124 */ MCD_OPC_Decode, 140, 16, 134, 1, // Opcode: XVMADDASP -/* 11129 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 11157 -/* 11134 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11137 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11147 -/* 11142 */ MCD_OPC_Decode, 182, 16, 133, 1, // Opcode: XVSUBSP -/* 11147 */ MCD_OPC_FilterValue, 1, 162, 20, 0, // Skip to: 16434 -/* 11152 */ MCD_OPC_Decode, 142, 16, 134, 1, // Opcode: XVMADDMSP -/* 11157 */ MCD_OPC_FilterValue, 10, 23, 0, 0, // Skip to: 11185 -/* 11162 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11165 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11175 -/* 11170 */ MCD_OPC_Decode, 152, 16, 133, 1, // Opcode: XVMULSP -/* 11175 */ MCD_OPC_FilterValue, 1, 134, 20, 0, // Skip to: 16434 -/* 11180 */ MCD_OPC_Decode, 148, 16, 134, 1, // Opcode: XVMSUBASP -/* 11185 */ MCD_OPC_FilterValue, 11, 23, 0, 0, // Skip to: 11213 -/* 11190 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11193 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11203 -/* 11198 */ MCD_OPC_Decode, 136, 16, 133, 1, // Opcode: XVDIVSP -/* 11203 */ MCD_OPC_FilterValue, 1, 106, 20, 0, // Skip to: 16434 -/* 11208 */ MCD_OPC_Decode, 150, 16, 134, 1, // Opcode: XVMSUBMSP -/* 11213 */ MCD_OPC_FilterValue, 12, 23, 0, 0, // Skip to: 11241 -/* 11218 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11221 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11231 -/* 11226 */ MCD_OPC_Decode, 227, 15, 133, 1, // Opcode: XVADDDP -/* 11231 */ MCD_OPC_FilterValue, 1, 78, 20, 0, // Skip to: 16434 -/* 11236 */ MCD_OPC_Decode, 139, 16, 134, 1, // Opcode: XVMADDADP -/* 11241 */ MCD_OPC_FilterValue, 13, 23, 0, 0, // Skip to: 11269 -/* 11246 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11249 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11259 -/* 11254 */ MCD_OPC_Decode, 181, 16, 133, 1, // Opcode: XVSUBDP -/* 11259 */ MCD_OPC_FilterValue, 1, 50, 20, 0, // Skip to: 16434 -/* 11264 */ MCD_OPC_Decode, 141, 16, 134, 1, // Opcode: XVMADDMDP -/* 11269 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 11297 -/* 11274 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11277 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11287 -/* 11282 */ MCD_OPC_Decode, 151, 16, 133, 1, // Opcode: XVMULDP -/* 11287 */ MCD_OPC_FilterValue, 1, 22, 20, 0, // Skip to: 16434 -/* 11292 */ MCD_OPC_Decode, 147, 16, 134, 1, // Opcode: XVMSUBADP -/* 11297 */ MCD_OPC_FilterValue, 15, 23, 0, 0, // Skip to: 11325 -/* 11302 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11305 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11315 -/* 11310 */ MCD_OPC_Decode, 135, 16, 133, 1, // Opcode: XVDIVDP -/* 11315 */ MCD_OPC_FilterValue, 1, 250, 19, 0, // Skip to: 16434 -/* 11320 */ MCD_OPC_Decode, 149, 16, 134, 1, // Opcode: XVMSUBMDP -/* 11325 */ MCD_OPC_FilterValue, 16, 23, 0, 0, // Skip to: 11353 -/* 11330 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11333 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11343 -/* 11338 */ MCD_OPC_Decode, 163, 15, 135, 1, // Opcode: XSMAXCDP -/* 11343 */ MCD_OPC_FilterValue, 1, 222, 19, 0, // Skip to: 16434 -/* 11348 */ MCD_OPC_Decode, 184, 15, 130, 1, // Opcode: XSNMADDASP -/* 11353 */ MCD_OPC_FilterValue, 17, 23, 0, 0, // Skip to: 11381 -/* 11358 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11361 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11371 -/* 11366 */ MCD_OPC_Decode, 166, 15, 135, 1, // Opcode: XSMINCDP -/* 11371 */ MCD_OPC_FilterValue, 1, 194, 19, 0, // Skip to: 16434 -/* 11376 */ MCD_OPC_Decode, 186, 15, 130, 1, // Opcode: XSNMADDMSP -/* 11381 */ MCD_OPC_FilterValue, 18, 23, 0, 0, // Skip to: 11409 -/* 11386 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11389 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11399 -/* 11394 */ MCD_OPC_Decode, 165, 15, 135, 1, // Opcode: XSMAXJDP -/* 11399 */ MCD_OPC_FilterValue, 1, 166, 19, 0, // Skip to: 16434 -/* 11404 */ MCD_OPC_Decode, 190, 15, 130, 1, // Opcode: XSNMSUBASP -/* 11409 */ MCD_OPC_FilterValue, 19, 23, 0, 0, // Skip to: 11437 -/* 11414 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11417 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11427 -/* 11422 */ MCD_OPC_Decode, 168, 15, 135, 1, // Opcode: XSMINJDP -/* 11427 */ MCD_OPC_FilterValue, 1, 138, 19, 0, // Skip to: 16434 -/* 11432 */ MCD_OPC_Decode, 192, 15, 130, 1, // Opcode: XSNMSUBMSP -/* 11437 */ MCD_OPC_FilterValue, 20, 23, 0, 0, // Skip to: 11465 -/* 11442 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11445 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11455 -/* 11450 */ MCD_OPC_Decode, 164, 15, 131, 1, // Opcode: XSMAXDP -/* 11455 */ MCD_OPC_FilterValue, 1, 110, 19, 0, // Skip to: 16434 -/* 11460 */ MCD_OPC_Decode, 183, 15, 132, 1, // Opcode: XSNMADDADP -/* 11465 */ MCD_OPC_FilterValue, 21, 23, 0, 0, // Skip to: 11493 -/* 11470 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11473 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11483 -/* 11478 */ MCD_OPC_Decode, 167, 15, 131, 1, // Opcode: XSMINDP -/* 11483 */ MCD_OPC_FilterValue, 1, 82, 19, 0, // Skip to: 16434 -/* 11488 */ MCD_OPC_Decode, 185, 15, 132, 1, // Opcode: XSNMADDMDP -/* 11493 */ MCD_OPC_FilterValue, 22, 23, 0, 0, // Skip to: 11521 -/* 11498 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11501 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11511 -/* 11506 */ MCD_OPC_Decode, 250, 14, 131, 1, // Opcode: XSCPSGNDP -/* 11511 */ MCD_OPC_FilterValue, 1, 54, 19, 0, // Skip to: 16434 -/* 11516 */ MCD_OPC_Decode, 189, 15, 132, 1, // Opcode: XSNMSUBADP -/* 11521 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 11538 -/* 11526 */ MCD_OPC_CheckField, 3, 1, 1, 37, 19, 0, // Skip to: 16434 -/* 11533 */ MCD_OPC_Decode, 191, 15, 132, 1, // Opcode: XSNMSUBMDP -/* 11538 */ MCD_OPC_FilterValue, 24, 23, 0, 0, // Skip to: 11566 -/* 11543 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11546 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11556 -/* 11551 */ MCD_OPC_Decode, 144, 16, 133, 1, // Opcode: XVMAXSP -/* 11556 */ MCD_OPC_FilterValue, 1, 9, 19, 0, // Skip to: 16434 -/* 11561 */ MCD_OPC_Decode, 158, 16, 134, 1, // Opcode: XVNMADDASP -/* 11566 */ MCD_OPC_FilterValue, 25, 23, 0, 0, // Skip to: 11594 -/* 11571 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11574 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11584 -/* 11579 */ MCD_OPC_Decode, 146, 16, 133, 1, // Opcode: XVMINSP -/* 11584 */ MCD_OPC_FilterValue, 1, 237, 18, 0, // Skip to: 16434 -/* 11589 */ MCD_OPC_Decode, 160, 16, 134, 1, // Opcode: XVNMADDMSP -/* 11594 */ MCD_OPC_FilterValue, 26, 23, 0, 0, // Skip to: 11622 -/* 11599 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11602 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11612 -/* 11607 */ MCD_OPC_Decode, 242, 15, 133, 1, // Opcode: XVCPSGNSP -/* 11612 */ MCD_OPC_FilterValue, 1, 209, 18, 0, // Skip to: 16434 -/* 11617 */ MCD_OPC_Decode, 162, 16, 134, 1, // Opcode: XVNMSUBASP -/* 11622 */ MCD_OPC_FilterValue, 27, 23, 0, 0, // Skip to: 11650 -/* 11627 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11630 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11640 -/* 11635 */ MCD_OPC_Decode, 138, 16, 133, 1, // Opcode: XVIEXPSP -/* 11640 */ MCD_OPC_FilterValue, 1, 181, 18, 0, // Skip to: 16434 -/* 11645 */ MCD_OPC_Decode, 164, 16, 134, 1, // Opcode: XVNMSUBMSP -/* 11650 */ MCD_OPC_FilterValue, 28, 23, 0, 0, // Skip to: 11678 -/* 11655 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11658 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11668 -/* 11663 */ MCD_OPC_Decode, 143, 16, 133, 1, // Opcode: XVMAXDP -/* 11668 */ MCD_OPC_FilterValue, 1, 153, 18, 0, // Skip to: 16434 -/* 11673 */ MCD_OPC_Decode, 157, 16, 134, 1, // Opcode: XVNMADDADP -/* 11678 */ MCD_OPC_FilterValue, 29, 23, 0, 0, // Skip to: 11706 -/* 11683 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11686 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11696 -/* 11691 */ MCD_OPC_Decode, 145, 16, 133, 1, // Opcode: XVMINDP -/* 11696 */ MCD_OPC_FilterValue, 1, 125, 18, 0, // Skip to: 16434 -/* 11701 */ MCD_OPC_Decode, 159, 16, 134, 1, // Opcode: XVNMADDMDP -/* 11706 */ MCD_OPC_FilterValue, 30, 23, 0, 0, // Skip to: 11734 -/* 11711 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11714 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11724 -/* 11719 */ MCD_OPC_Decode, 241, 15, 133, 1, // Opcode: XVCPSGNDP -/* 11724 */ MCD_OPC_FilterValue, 1, 97, 18, 0, // Skip to: 16434 -/* 11729 */ MCD_OPC_Decode, 161, 16, 134, 1, // Opcode: XVNMSUBADP -/* 11734 */ MCD_OPC_FilterValue, 31, 87, 18, 0, // Skip to: 16434 -/* 11739 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11742 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11752 -/* 11747 */ MCD_OPC_Decode, 137, 16, 133, 1, // Opcode: XVIEXPDP -/* 11752 */ MCD_OPC_FilterValue, 1, 69, 18, 0, // Skip to: 16434 -/* 11757 */ MCD_OPC_Decode, 163, 16, 134, 1, // Opcode: XVNMSUBMDP -/* 11762 */ MCD_OPC_FilterValue, 1, 97, 2, 0, // Skip to: 12376 -/* 11767 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... -/* 11770 */ MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 11906 -/* 11775 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11778 */ MCD_OPC_FilterValue, 0, 41, 0, 0, // Skip to: 11824 -/* 11783 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 11786 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11796 -/* 11791 */ MCD_OPC_Decode, 218, 16, 136, 1, // Opcode: XXSLDWI -/* 11796 */ MCD_OPC_FilterValue, 1, 25, 18, 0, // Skip to: 16434 -/* 11801 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 11804 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11814 -/* 11809 */ MCD_OPC_Decode, 199, 16, 133, 1, // Opcode: XXLAND -/* 11814 */ MCD_OPC_FilterValue, 1, 7, 18, 0, // Skip to: 16434 -/* 11819 */ MCD_OPC_Decode, 203, 16, 133, 1, // Opcode: XXLNOR -/* 11824 */ MCD_OPC_FilterValue, 1, 253, 17, 0, // Skip to: 16434 -/* 11829 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 11832 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11842 -/* 11837 */ MCD_OPC_Decode, 241, 14, 135, 1, // Opcode: XSCMPEQDP -/* 11842 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 11866 -/* 11847 */ MCD_OPC_CheckField, 21, 2, 0, 228, 17, 0, // Skip to: 16434 -/* 11854 */ MCD_OPC_CheckField, 0, 1, 0, 221, 17, 0, // Skip to: 16434 -/* 11861 */ MCD_OPC_Decode, 248, 14, 137, 1, // Opcode: XSCMPUDP -/* 11866 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 11876 -/* 11871 */ MCD_OPC_Decode, 231, 15, 133, 1, // Opcode: XVCMPEQSP -/* 11876 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 11886 -/* 11881 */ MCD_OPC_Decode, 229, 15, 133, 1, // Opcode: XVCMPEQDP -/* 11886 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 11896 -/* 11891 */ MCD_OPC_Decode, 232, 15, 133, 1, // Opcode: XVCMPEQSPo -/* 11896 */ MCD_OPC_FilterValue, 7, 181, 17, 0, // Skip to: 16434 -/* 11901 */ MCD_OPC_Decode, 230, 15, 133, 1, // Opcode: XVCMPEQDPo -/* 11906 */ MCD_OPC_FilterValue, 1, 131, 0, 0, // Skip to: 12042 -/* 11911 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 11914 */ MCD_OPC_FilterValue, 0, 41, 0, 0, // Skip to: 11960 -/* 11919 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 11922 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11932 -/* 11927 */ MCD_OPC_Decode, 214, 16, 136, 1, // Opcode: XXPERMDI -/* 11932 */ MCD_OPC_FilterValue, 1, 145, 17, 0, // Skip to: 16434 -/* 11937 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 11940 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11950 -/* 11945 */ MCD_OPC_Decode, 200, 16, 133, 1, // Opcode: XXLANDC -/* 11950 */ MCD_OPC_FilterValue, 1, 127, 17, 0, // Skip to: 16434 -/* 11955 */ MCD_OPC_Decode, 205, 16, 133, 1, // Opcode: XXLORC -/* 11960 */ MCD_OPC_FilterValue, 1, 117, 17, 0, // Skip to: 16434 -/* 11965 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 11968 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11978 -/* 11973 */ MCD_OPC_Decode, 245, 14, 135, 1, // Opcode: XSCMPGTDP -/* 11978 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 12002 -/* 11983 */ MCD_OPC_CheckField, 21, 2, 0, 92, 17, 0, // Skip to: 16434 -/* 11990 */ MCD_OPC_CheckField, 0, 1, 0, 85, 17, 0, // Skip to: 16434 -/* 11997 */ MCD_OPC_Decode, 246, 14, 137, 1, // Opcode: XSCMPODP -/* 12002 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 12012 -/* 12007 */ MCD_OPC_Decode, 239, 15, 133, 1, // Opcode: XVCMPGTSP -/* 12012 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 12022 -/* 12017 */ MCD_OPC_Decode, 237, 15, 133, 1, // Opcode: XVCMPGTDP -/* 12022 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 12032 -/* 12027 */ MCD_OPC_Decode, 240, 15, 133, 1, // Opcode: XVCMPGTSPo -/* 12032 */ MCD_OPC_FilterValue, 7, 45, 17, 0, // Skip to: 16434 -/* 12037 */ MCD_OPC_Decode, 238, 15, 133, 1, // Opcode: XVCMPGTDPo -/* 12042 */ MCD_OPC_FilterValue, 2, 186, 0, 0, // Skip to: 12233 -/* 12047 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 12050 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 12078 -/* 12055 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 12058 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 12068 -/* 12063 */ MCD_OPC_Decode, 211, 16, 133, 1, // Opcode: XXMRGHW -/* 12068 */ MCD_OPC_FilterValue, 1, 9, 17, 0, // Skip to: 16434 -/* 12073 */ MCD_OPC_Decode, 244, 14, 135, 1, // Opcode: XSCMPGEDP -/* 12078 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 12095 -/* 12083 */ MCD_OPC_CheckField, 3, 1, 0, 248, 16, 0, // Skip to: 16434 -/* 12090 */ MCD_OPC_Decode, 212, 16, 133, 1, // Opcode: XXMRGLW -/* 12095 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 12148 -/* 12100 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 12103 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 12138 -/* 12108 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 12111 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12128 -/* 12116 */ MCD_OPC_CheckField, 18, 3, 0, 215, 16, 0, // Skip to: 16434 -/* 12123 */ MCD_OPC_Decode, 221, 16, 138, 1, // Opcode: XXSPLTW -/* 12128 */ MCD_OPC_FilterValue, 1, 205, 16, 0, // Skip to: 16434 -/* 12133 */ MCD_OPC_Decode, 197, 16, 139, 1, // Opcode: XXEXTRACTUW -/* 12138 */ MCD_OPC_FilterValue, 1, 195, 16, 0, // Skip to: 16434 -/* 12143 */ MCD_OPC_Decode, 235, 15, 133, 1, // Opcode: XVCMPGESP -/* 12148 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 12165 -/* 12153 */ MCD_OPC_CheckField, 3, 1, 1, 178, 16, 0, // Skip to: 16434 -/* 12160 */ MCD_OPC_Decode, 233, 15, 133, 1, // Opcode: XVCMPGEDP -/* 12165 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 12182 -/* 12170 */ MCD_OPC_CheckField, 3, 1, 0, 161, 16, 0, // Skip to: 16434 -/* 12177 */ MCD_OPC_Decode, 204, 16, 133, 1, // Opcode: XXLOR -/* 12182 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 12199 -/* 12187 */ MCD_OPC_CheckField, 3, 1, 0, 144, 16, 0, // Skip to: 16434 -/* 12194 */ MCD_OPC_Decode, 202, 16, 133, 1, // Opcode: XXLNAND -/* 12199 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 12216 -/* 12204 */ MCD_OPC_CheckField, 3, 1, 1, 127, 16, 0, // Skip to: 16434 -/* 12211 */ MCD_OPC_Decode, 236, 15, 133, 1, // Opcode: XVCMPGESPo -/* 12216 */ MCD_OPC_FilterValue, 7, 117, 16, 0, // Skip to: 16434 -/* 12221 */ MCD_OPC_CheckField, 3, 1, 1, 110, 16, 0, // Skip to: 16434 -/* 12228 */ MCD_OPC_Decode, 234, 15, 133, 1, // Opcode: XVCMPGEDPo -/* 12233 */ MCD_OPC_FilterValue, 3, 100, 16, 0, // Skip to: 16434 -/* 12238 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 12241 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12258 -/* 12246 */ MCD_OPC_CheckField, 3, 1, 0, 85, 16, 0, // Skip to: 16434 -/* 12253 */ MCD_OPC_Decode, 213, 16, 133, 1, // Opcode: XXPERM -/* 12258 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 12300 -/* 12263 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 12266 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 12276 -/* 12271 */ MCD_OPC_Decode, 216, 16, 133, 1, // Opcode: XXPERMR -/* 12276 */ MCD_OPC_FilterValue, 1, 57, 16, 0, // Skip to: 16434 -/* 12281 */ MCD_OPC_CheckField, 21, 2, 0, 50, 16, 0, // Skip to: 16434 -/* 12288 */ MCD_OPC_CheckField, 0, 1, 0, 43, 16, 0, // Skip to: 16434 -/* 12295 */ MCD_OPC_Decode, 242, 14, 137, 1, // Opcode: XSCMPEXPDP -/* 12300 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 12342 -/* 12305 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 12308 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 12332 -/* 12313 */ MCD_OPC_CheckField, 19, 2, 0, 18, 16, 0, // Skip to: 16434 -/* 12320 */ MCD_OPC_CheckField, 1, 1, 0, 11, 16, 0, // Skip to: 16434 -/* 12327 */ MCD_OPC_Decode, 220, 16, 140, 1, // Opcode: XXSPLTIB -/* 12332 */ MCD_OPC_FilterValue, 1, 1, 16, 0, // Skip to: 16434 -/* 12337 */ MCD_OPC_Decode, 198, 16, 141, 1, // Opcode: XXINSERTW -/* 12342 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 12359 -/* 12347 */ MCD_OPC_CheckField, 3, 1, 0, 240, 15, 0, // Skip to: 16434 -/* 12354 */ MCD_OPC_Decode, 207, 16, 133, 1, // Opcode: XXLXOR -/* 12359 */ MCD_OPC_FilterValue, 5, 230, 15, 0, // Skip to: 16434 -/* 12364 */ MCD_OPC_CheckField, 3, 1, 0, 223, 15, 0, // Skip to: 16434 -/* 12371 */ MCD_OPC_Decode, 201, 16, 133, 1, // Opcode: XXLEQV -/* 12376 */ MCD_OPC_FilterValue, 2, 253, 7, 0, // Skip to: 14426 -/* 12381 */ MCD_OPC_ExtractField, 7, 4, // Inst{10-7} ... -/* 12384 */ MCD_OPC_FilterValue, 0, 69, 0, 0, // Skip to: 12458 -/* 12389 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 12392 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 12434 -/* 12397 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12400 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12417 -/* 12405 */ MCD_OPC_CheckField, 16, 5, 0, 182, 15, 0, // Skip to: 16434 -/* 12412 */ MCD_OPC_Decode, 207, 15, 142, 1, // Opcode: XSRSQRTESP -/* 12417 */ MCD_OPC_FilterValue, 1, 172, 15, 0, // Skip to: 16434 -/* 12422 */ MCD_OPC_CheckField, 16, 5, 0, 165, 15, 0, // Skip to: 16434 -/* 12429 */ MCD_OPC_Decode, 201, 15, 142, 1, // Opcode: XSRESP -/* 12434 */ MCD_OPC_FilterValue, 3, 155, 15, 0, // Skip to: 16434 -/* 12439 */ MCD_OPC_CheckField, 16, 5, 0, 148, 15, 0, // Skip to: 16434 -/* 12446 */ MCD_OPC_CheckField, 6, 1, 0, 141, 15, 0, // Skip to: 16434 -/* 12453 */ MCD_OPC_Decode, 211, 15, 142, 1, // Opcode: XSSQRTSP -/* 12458 */ MCD_OPC_FilterValue, 2, 153, 0, 0, // Skip to: 12616 -/* 12463 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 12466 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 12508 -/* 12471 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12474 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12491 -/* 12479 */ MCD_OPC_CheckField, 16, 5, 0, 108, 15, 0, // Skip to: 16434 -/* 12486 */ MCD_OPC_Decode, 134, 15, 143, 1, // Opcode: XSCVDPUXWS -/* 12491 */ MCD_OPC_FilterValue, 1, 98, 15, 0, // Skip to: 16434 -/* 12496 */ MCD_OPC_CheckField, 16, 5, 0, 91, 15, 0, // Skip to: 16434 -/* 12503 */ MCD_OPC_Decode, 130, 15, 143, 1, // Opcode: XSCVDPSXWS -/* 12508 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 12550 -/* 12513 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12516 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12533 -/* 12521 */ MCD_OPC_CheckField, 16, 5, 0, 66, 15, 0, // Skip to: 16434 -/* 12528 */ MCD_OPC_Decode, 195, 15, 143, 1, // Opcode: XSRDPI -/* 12533 */ MCD_OPC_FilterValue, 1, 56, 15, 0, // Skip to: 16434 -/* 12538 */ MCD_OPC_CheckField, 16, 5, 0, 49, 15, 0, // Skip to: 16434 -/* 12545 */ MCD_OPC_Decode, 199, 15, 143, 1, // Opcode: XSRDPIZ -/* 12550 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 12592 -/* 12555 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12558 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12575 -/* 12563 */ MCD_OPC_CheckField, 16, 5, 0, 24, 15, 0, // Skip to: 16434 -/* 12570 */ MCD_OPC_Decode, 206, 15, 143, 1, // Opcode: XSRSQRTEDP -/* 12575 */ MCD_OPC_FilterValue, 1, 14, 15, 0, // Skip to: 16434 -/* 12580 */ MCD_OPC_CheckField, 16, 5, 0, 7, 15, 0, // Skip to: 16434 -/* 12587 */ MCD_OPC_Decode, 200, 15, 143, 1, // Opcode: XSREDP -/* 12592 */ MCD_OPC_FilterValue, 3, 253, 14, 0, // Skip to: 16434 -/* 12597 */ MCD_OPC_CheckField, 16, 5, 0, 246, 14, 0, // Skip to: 16434 -/* 12604 */ MCD_OPC_CheckField, 6, 1, 0, 239, 14, 0, // Skip to: 16434 -/* 12611 */ MCD_OPC_Decode, 208, 15, 143, 1, // Opcode: XSSQRTDP -/* 12616 */ MCD_OPC_FilterValue, 3, 140, 0, 0, // Skip to: 12761 -/* 12621 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 12624 */ MCD_OPC_FilterValue, 0, 51, 0, 0, // Skip to: 12680 -/* 12629 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12632 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 12656 -/* 12637 */ MCD_OPC_CheckField, 16, 5, 0, 206, 14, 0, // Skip to: 16434 -/* 12644 */ MCD_OPC_CheckField, 2, 1, 1, 199, 14, 0, // Skip to: 16434 -/* 12651 */ MCD_OPC_Decode, 198, 15, 143, 1, // Opcode: XSRDPIP -/* 12656 */ MCD_OPC_FilterValue, 1, 189, 14, 0, // Skip to: 16434 -/* 12661 */ MCD_OPC_CheckField, 16, 5, 0, 182, 14, 0, // Skip to: 16434 -/* 12668 */ MCD_OPC_CheckField, 2, 1, 1, 175, 14, 0, // Skip to: 16434 -/* 12675 */ MCD_OPC_Decode, 197, 15, 143, 1, // Opcode: XSRDPIM -/* 12680 */ MCD_OPC_FilterValue, 1, 165, 14, 0, // Skip to: 16434 -/* 12685 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12688 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 12737 -/* 12693 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 12696 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 12720 -/* 12701 */ MCD_OPC_CheckField, 16, 7, 0, 142, 14, 0, // Skip to: 16434 -/* 12708 */ MCD_OPC_CheckField, 0, 1, 0, 135, 14, 0, // Skip to: 16434 -/* 12715 */ MCD_OPC_Decode, 217, 15, 144, 1, // Opcode: XSTSQRTDP -/* 12720 */ MCD_OPC_FilterValue, 1, 125, 14, 0, // Skip to: 16434 -/* 12725 */ MCD_OPC_CheckField, 16, 5, 0, 118, 14, 0, // Skip to: 16434 -/* 12732 */ MCD_OPC_Decode, 196, 15, 143, 1, // Opcode: XSRDPIC -/* 12737 */ MCD_OPC_FilterValue, 1, 108, 14, 0, // Skip to: 16434 -/* 12742 */ MCD_OPC_CheckField, 21, 2, 0, 101, 14, 0, // Skip to: 16434 -/* 12749 */ MCD_OPC_CheckField, 0, 1, 0, 94, 14, 0, // Skip to: 16434 -/* 12756 */ MCD_OPC_Decode, 216, 15, 137, 1, // Opcode: XSTDIVDP -/* 12761 */ MCD_OPC_FilterValue, 4, 153, 0, 0, // Skip to: 12919 -/* 12766 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 12769 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 12811 -/* 12774 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12777 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12794 -/* 12782 */ MCD_OPC_CheckField, 16, 5, 0, 61, 14, 0, // Skip to: 16434 -/* 12789 */ MCD_OPC_Decode, 254, 15, 145, 1, // Opcode: XVCVSPUXWS -/* 12794 */ MCD_OPC_FilterValue, 1, 51, 14, 0, // Skip to: 16434 -/* 12799 */ MCD_OPC_CheckField, 16, 5, 0, 44, 14, 0, // Skip to: 16434 -/* 12806 */ MCD_OPC_Decode, 252, 15, 145, 1, // Opcode: XVCVSPSXWS -/* 12811 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 12853 -/* 12816 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12819 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12836 -/* 12824 */ MCD_OPC_CheckField, 16, 5, 0, 19, 14, 0, // Skip to: 16434 -/* 12831 */ MCD_OPC_Decode, 172, 16, 145, 1, // Opcode: XVRSPI -/* 12836 */ MCD_OPC_FilterValue, 1, 9, 14, 0, // Skip to: 16434 -/* 12841 */ MCD_OPC_CheckField, 16, 5, 0, 2, 14, 0, // Skip to: 16434 -/* 12848 */ MCD_OPC_Decode, 176, 16, 145, 1, // Opcode: XVRSPIZ -/* 12853 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 12895 -/* 12858 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12861 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12878 -/* 12866 */ MCD_OPC_CheckField, 16, 5, 0, 233, 13, 0, // Skip to: 16434 -/* 12873 */ MCD_OPC_Decode, 178, 16, 145, 1, // Opcode: XVRSQRTESP -/* 12878 */ MCD_OPC_FilterValue, 1, 223, 13, 0, // Skip to: 16434 -/* 12883 */ MCD_OPC_CheckField, 16, 5, 0, 216, 13, 0, // Skip to: 16434 -/* 12890 */ MCD_OPC_Decode, 171, 16, 145, 1, // Opcode: XVRESP -/* 12895 */ MCD_OPC_FilterValue, 3, 206, 13, 0, // Skip to: 16434 -/* 12900 */ MCD_OPC_CheckField, 16, 5, 0, 199, 13, 0, // Skip to: 16434 -/* 12907 */ MCD_OPC_CheckField, 6, 1, 0, 192, 13, 0, // Skip to: 16434 -/* 12914 */ MCD_OPC_Decode, 180, 16, 145, 1, // Opcode: XVSQRTSP -/* 12919 */ MCD_OPC_FilterValue, 5, 176, 0, 0, // Skip to: 13100 -/* 12924 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 12927 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 13019 -/* 12932 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 12935 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 12977 -/* 12940 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12943 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12960 -/* 12948 */ MCD_OPC_CheckField, 16, 5, 0, 151, 13, 0, // Skip to: 16434 -/* 12955 */ MCD_OPC_Decode, 134, 16, 145, 1, // Opcode: XVCVUXWSP -/* 12960 */ MCD_OPC_FilterValue, 1, 141, 13, 0, // Skip to: 16434 -/* 12965 */ MCD_OPC_CheckField, 16, 5, 0, 134, 13, 0, // Skip to: 16434 -/* 12972 */ MCD_OPC_Decode, 130, 16, 145, 1, // Opcode: XVCVSXWSP -/* 12977 */ MCD_OPC_FilterValue, 1, 124, 13, 0, // Skip to: 16434 -/* 12982 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 12985 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13002 -/* 12990 */ MCD_OPC_CheckField, 16, 5, 0, 109, 13, 0, // Skip to: 16434 -/* 12997 */ MCD_OPC_Decode, 175, 16, 145, 1, // Opcode: XVRSPIP -/* 13002 */ MCD_OPC_FilterValue, 1, 99, 13, 0, // Skip to: 16434 -/* 13007 */ MCD_OPC_CheckField, 16, 5, 0, 92, 13, 0, // Skip to: 16434 -/* 13014 */ MCD_OPC_Decode, 174, 16, 145, 1, // Opcode: XVRSPIM -/* 13019 */ MCD_OPC_FilterValue, 1, 82, 13, 0, // Skip to: 16434 -/* 13024 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13027 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 13076 -/* 13032 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 13035 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 13059 -/* 13040 */ MCD_OPC_CheckField, 16, 7, 0, 59, 13, 0, // Skip to: 16434 -/* 13047 */ MCD_OPC_CheckField, 0, 1, 0, 52, 13, 0, // Skip to: 16434 -/* 13054 */ MCD_OPC_Decode, 186, 16, 146, 1, // Opcode: XVTSQRTSP -/* 13059 */ MCD_OPC_FilterValue, 1, 42, 13, 0, // Skip to: 16434 -/* 13064 */ MCD_OPC_CheckField, 16, 5, 0, 35, 13, 0, // Skip to: 16434 -/* 13071 */ MCD_OPC_Decode, 173, 16, 145, 1, // Opcode: XVRSPIC -/* 13076 */ MCD_OPC_FilterValue, 1, 25, 13, 0, // Skip to: 16434 -/* 13081 */ MCD_OPC_CheckField, 21, 2, 0, 18, 13, 0, // Skip to: 16434 -/* 13088 */ MCD_OPC_CheckField, 0, 1, 0, 11, 13, 0, // Skip to: 16434 -/* 13095 */ MCD_OPC_Decode, 184, 16, 147, 1, // Opcode: XVTDIVSP -/* 13100 */ MCD_OPC_FilterValue, 6, 153, 0, 0, // Skip to: 13258 -/* 13105 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 13108 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13150 -/* 13113 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13116 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13133 -/* 13121 */ MCD_OPC_CheckField, 16, 5, 0, 234, 12, 0, // Skip to: 16434 -/* 13128 */ MCD_OPC_Decode, 247, 15, 145, 1, // Opcode: XVCVDPUXWS -/* 13133 */ MCD_OPC_FilterValue, 1, 224, 12, 0, // Skip to: 16434 -/* 13138 */ MCD_OPC_CheckField, 16, 5, 0, 217, 12, 0, // Skip to: 16434 -/* 13145 */ MCD_OPC_Decode, 245, 15, 145, 1, // Opcode: XVCVDPSXWS -/* 13150 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 13192 -/* 13155 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13158 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13175 -/* 13163 */ MCD_OPC_CheckField, 16, 5, 0, 192, 12, 0, // Skip to: 16434 -/* 13170 */ MCD_OPC_Decode, 165, 16, 145, 1, // Opcode: XVRDPI -/* 13175 */ MCD_OPC_FilterValue, 1, 182, 12, 0, // Skip to: 16434 -/* 13180 */ MCD_OPC_CheckField, 16, 5, 0, 175, 12, 0, // Skip to: 16434 -/* 13187 */ MCD_OPC_Decode, 169, 16, 145, 1, // Opcode: XVRDPIZ -/* 13192 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 13234 -/* 13197 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13200 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13217 -/* 13205 */ MCD_OPC_CheckField, 16, 5, 0, 150, 12, 0, // Skip to: 16434 -/* 13212 */ MCD_OPC_Decode, 177, 16, 145, 1, // Opcode: XVRSQRTEDP -/* 13217 */ MCD_OPC_FilterValue, 1, 140, 12, 0, // Skip to: 16434 -/* 13222 */ MCD_OPC_CheckField, 16, 5, 0, 133, 12, 0, // Skip to: 16434 -/* 13229 */ MCD_OPC_Decode, 170, 16, 145, 1, // Opcode: XVREDP -/* 13234 */ MCD_OPC_FilterValue, 3, 123, 12, 0, // Skip to: 16434 -/* 13239 */ MCD_OPC_CheckField, 16, 5, 0, 116, 12, 0, // Skip to: 16434 -/* 13246 */ MCD_OPC_CheckField, 6, 1, 0, 109, 12, 0, // Skip to: 16434 -/* 13253 */ MCD_OPC_Decode, 179, 16, 145, 1, // Opcode: XVSQRTDP -/* 13258 */ MCD_OPC_FilterValue, 7, 176, 0, 0, // Skip to: 13439 -/* 13263 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 13266 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 13358 -/* 13271 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 13274 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13316 -/* 13279 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13282 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13299 -/* 13287 */ MCD_OPC_CheckField, 16, 5, 0, 68, 12, 0, // Skip to: 16434 -/* 13294 */ MCD_OPC_Decode, 133, 16, 145, 1, // Opcode: XVCVUXWDP -/* 13299 */ MCD_OPC_FilterValue, 1, 58, 12, 0, // Skip to: 16434 -/* 13304 */ MCD_OPC_CheckField, 16, 5, 0, 51, 12, 0, // Skip to: 16434 -/* 13311 */ MCD_OPC_Decode, 129, 16, 145, 1, // Opcode: XVCVSXWDP -/* 13316 */ MCD_OPC_FilterValue, 1, 41, 12, 0, // Skip to: 16434 -/* 13321 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13324 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13341 -/* 13329 */ MCD_OPC_CheckField, 16, 5, 0, 26, 12, 0, // Skip to: 16434 -/* 13336 */ MCD_OPC_Decode, 168, 16, 145, 1, // Opcode: XVRDPIP -/* 13341 */ MCD_OPC_FilterValue, 1, 16, 12, 0, // Skip to: 16434 -/* 13346 */ MCD_OPC_CheckField, 16, 5, 0, 9, 12, 0, // Skip to: 16434 -/* 13353 */ MCD_OPC_Decode, 167, 16, 145, 1, // Opcode: XVRDPIM -/* 13358 */ MCD_OPC_FilterValue, 1, 255, 11, 0, // Skip to: 16434 -/* 13363 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13366 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 13415 -/* 13371 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 13374 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 13398 -/* 13379 */ MCD_OPC_CheckField, 16, 7, 0, 232, 11, 0, // Skip to: 16434 -/* 13386 */ MCD_OPC_CheckField, 0, 1, 0, 225, 11, 0, // Skip to: 16434 -/* 13393 */ MCD_OPC_Decode, 185, 16, 146, 1, // Opcode: XVTSQRTDP -/* 13398 */ MCD_OPC_FilterValue, 1, 215, 11, 0, // Skip to: 16434 -/* 13403 */ MCD_OPC_CheckField, 16, 5, 0, 208, 11, 0, // Skip to: 16434 -/* 13410 */ MCD_OPC_Decode, 166, 16, 145, 1, // Opcode: XVRDPIC -/* 13415 */ MCD_OPC_FilterValue, 1, 198, 11, 0, // Skip to: 16434 -/* 13420 */ MCD_OPC_CheckField, 21, 2, 0, 191, 11, 0, // Skip to: 16434 -/* 13427 */ MCD_OPC_CheckField, 0, 1, 0, 184, 11, 0, // Skip to: 16434 -/* 13434 */ MCD_OPC_Decode, 183, 16, 147, 1, // Opcode: XVTDIVDP -/* 13439 */ MCD_OPC_FilterValue, 8, 69, 0, 0, // Skip to: 13513 -/* 13444 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 13447 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 13489 -/* 13452 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13455 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13472 -/* 13460 */ MCD_OPC_CheckField, 16, 5, 0, 151, 11, 0, // Skip to: 16434 -/* 13467 */ MCD_OPC_Decode, 254, 14, 143, 1, // Opcode: XSCVDPSP -/* 13472 */ MCD_OPC_FilterValue, 1, 141, 11, 0, // Skip to: 16434 -/* 13477 */ MCD_OPC_CheckField, 16, 5, 0, 134, 11, 0, // Skip to: 16434 -/* 13484 */ MCD_OPC_Decode, 205, 15, 148, 1, // Opcode: XSRSP -/* 13489 */ MCD_OPC_FilterValue, 3, 124, 11, 0, // Skip to: 16434 -/* 13494 */ MCD_OPC_CheckField, 16, 5, 0, 117, 11, 0, // Skip to: 16434 -/* 13501 */ MCD_OPC_CheckField, 6, 1, 0, 110, 11, 0, // Skip to: 16434 -/* 13508 */ MCD_OPC_Decode, 255, 14, 149, 1, // Opcode: XSCVDPSPN -/* 13513 */ MCD_OPC_FilterValue, 9, 69, 0, 0, // Skip to: 13587 -/* 13518 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 13521 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13563 -/* 13526 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13529 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13546 -/* 13534 */ MCD_OPC_CheckField, 16, 5, 0, 77, 11, 0, // Skip to: 16434 -/* 13541 */ MCD_OPC_Decode, 150, 15, 148, 1, // Opcode: XSCVUXDSP -/* 13546 */ MCD_OPC_FilterValue, 1, 67, 11, 0, // Skip to: 16434 -/* 13551 */ MCD_OPC_CheckField, 16, 5, 0, 60, 11, 0, // Skip to: 16434 -/* 13558 */ MCD_OPC_Decode, 147, 15, 148, 1, // Opcode: XSCVSXDSP -/* 13563 */ MCD_OPC_FilterValue, 2, 50, 11, 0, // Skip to: 16434 -/* 13568 */ MCD_OPC_CheckField, 6, 1, 0, 43, 11, 0, // Skip to: 16434 -/* 13575 */ MCD_OPC_CheckField, 0, 1, 0, 36, 11, 0, // Skip to: 16434 -/* 13582 */ MCD_OPC_Decode, 220, 15, 150, 1, // Opcode: XSTSTDCSP -/* 13587 */ MCD_OPC_FilterValue, 10, 181, 0, 0, // Skip to: 13773 -/* 13592 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 13595 */ MCD_OPC_FilterValue, 0, 94, 0, 0, // Skip to: 13694 -/* 13600 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 13603 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 13631 -/* 13608 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13611 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13621 -/* 13616 */ MCD_OPC_Decode, 132, 15, 143, 1, // Opcode: XSCVDPUXDS -/* 13621 */ MCD_OPC_FilterValue, 1, 248, 10, 0, // Skip to: 16434 -/* 13626 */ MCD_OPC_Decode, 128, 15, 143, 1, // Opcode: XSCVDPSXDS -/* 13631 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 13659 -/* 13636 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13639 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13649 -/* 13644 */ MCD_OPC_Decode, 144, 15, 143, 1, // Opcode: XSCVSPDP -/* 13649 */ MCD_OPC_FilterValue, 1, 220, 10, 0, // Skip to: 16434 -/* 13654 */ MCD_OPC_Decode, 235, 14, 143, 1, // Opcode: XSABSDP -/* 13659 */ MCD_OPC_FilterValue, 3, 210, 10, 0, // Skip to: 16434 -/* 13664 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13667 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13677 -/* 13672 */ MCD_OPC_Decode, 145, 15, 151, 1, // Opcode: XSCVSPDPN -/* 13677 */ MCD_OPC_FilterValue, 1, 192, 10, 0, // Skip to: 16434 -/* 13682 */ MCD_OPC_CheckField, 0, 1, 0, 185, 10, 0, // Skip to: 16434 -/* 13689 */ MCD_OPC_Decode, 221, 15, 152, 1, // Opcode: XSXEXPDP -/* 13694 */ MCD_OPC_FilterValue, 1, 26, 0, 0, // Skip to: 13725 -/* 13699 */ MCD_OPC_CheckField, 6, 1, 1, 168, 10, 0, // Skip to: 16434 -/* 13706 */ MCD_OPC_CheckField, 2, 2, 3, 161, 10, 0, // Skip to: 16434 -/* 13713 */ MCD_OPC_CheckField, 0, 1, 0, 154, 10, 0, // Skip to: 16434 -/* 13720 */ MCD_OPC_Decode, 223, 15, 152, 1, // Opcode: XSXSIGDP -/* 13725 */ MCD_OPC_FilterValue, 16, 19, 0, 0, // Skip to: 13749 -/* 13730 */ MCD_OPC_CheckField, 6, 1, 1, 137, 10, 0, // Skip to: 16434 -/* 13737 */ MCD_OPC_CheckField, 2, 2, 3, 130, 10, 0, // Skip to: 16434 -/* 13744 */ MCD_OPC_Decode, 136, 15, 143, 1, // Opcode: XSCVHPDP -/* 13749 */ MCD_OPC_FilterValue, 17, 120, 10, 0, // Skip to: 16434 -/* 13754 */ MCD_OPC_CheckField, 6, 1, 1, 113, 10, 0, // Skip to: 16434 -/* 13761 */ MCD_OPC_CheckField, 2, 2, 3, 106, 10, 0, // Skip to: 16434 -/* 13768 */ MCD_OPC_Decode, 252, 14, 143, 1, // Opcode: XSCVDPHP -/* 13773 */ MCD_OPC_FilterValue, 11, 111, 0, 0, // Skip to: 13889 -/* 13778 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 13781 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13823 -/* 13786 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13789 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13806 -/* 13794 */ MCD_OPC_CheckField, 16, 5, 0, 73, 10, 0, // Skip to: 16434 -/* 13801 */ MCD_OPC_Decode, 149, 15, 143, 1, // Opcode: XSCVUXDDP -/* 13806 */ MCD_OPC_FilterValue, 1, 63, 10, 0, // Skip to: 16434 -/* 13811 */ MCD_OPC_CheckField, 16, 5, 0, 56, 10, 0, // Skip to: 16434 -/* 13818 */ MCD_OPC_Decode, 146, 15, 143, 1, // Opcode: XSCVSXDDP -/* 13823 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 13865 -/* 13828 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13831 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13848 -/* 13836 */ MCD_OPC_CheckField, 16, 5, 0, 31, 10, 0, // Skip to: 16434 -/* 13843 */ MCD_OPC_Decode, 179, 15, 143, 1, // Opcode: XSNABSDP -/* 13848 */ MCD_OPC_FilterValue, 1, 21, 10, 0, // Skip to: 16434 -/* 13853 */ MCD_OPC_CheckField, 16, 5, 0, 14, 10, 0, // Skip to: 16434 -/* 13860 */ MCD_OPC_Decode, 181, 15, 143, 1, // Opcode: XSNEGDP -/* 13865 */ MCD_OPC_FilterValue, 2, 4, 10, 0, // Skip to: 16434 -/* 13870 */ MCD_OPC_CheckField, 6, 1, 0, 253, 9, 0, // Skip to: 16434 -/* 13877 */ MCD_OPC_CheckField, 0, 1, 0, 246, 9, 0, // Skip to: 16434 -/* 13884 */ MCD_OPC_Decode, 218, 15, 150, 1, // Opcode: XSTSTDCDP -/* 13889 */ MCD_OPC_FilterValue, 12, 87, 0, 0, // Skip to: 13981 -/* 13894 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 13897 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13939 -/* 13902 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13905 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13922 -/* 13910 */ MCD_OPC_CheckField, 16, 5, 0, 213, 9, 0, // Skip to: 16434 -/* 13917 */ MCD_OPC_Decode, 253, 15, 145, 1, // Opcode: XVCVSPUXDS -/* 13922 */ MCD_OPC_FilterValue, 1, 203, 9, 0, // Skip to: 16434 -/* 13927 */ MCD_OPC_CheckField, 16, 5, 0, 196, 9, 0, // Skip to: 16434 -/* 13934 */ MCD_OPC_Decode, 251, 15, 145, 1, // Opcode: XVCVSPSXDS -/* 13939 */ MCD_OPC_FilterValue, 1, 186, 9, 0, // Skip to: 16434 -/* 13944 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 13947 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13964 -/* 13952 */ MCD_OPC_CheckField, 16, 5, 0, 171, 9, 0, // Skip to: 16434 -/* 13959 */ MCD_OPC_Decode, 243, 15, 145, 1, // Opcode: XVCVDPSP -/* 13964 */ MCD_OPC_FilterValue, 1, 161, 9, 0, // Skip to: 16434 -/* 13969 */ MCD_OPC_CheckField, 16, 5, 0, 154, 9, 0, // Skip to: 16434 -/* 13976 */ MCD_OPC_Decode, 226, 15, 145, 1, // Opcode: XVABSSP -/* 13981 */ MCD_OPC_FilterValue, 13, 105, 0, 0, // Skip to: 14091 -/* 13986 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 13989 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 14081 -/* 13994 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 13997 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 14039 -/* 14002 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 14005 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14022 -/* 14010 */ MCD_OPC_CheckField, 16, 5, 0, 113, 9, 0, // Skip to: 16434 -/* 14017 */ MCD_OPC_Decode, 132, 16, 145, 1, // Opcode: XVCVUXDSP -/* 14022 */ MCD_OPC_FilterValue, 1, 103, 9, 0, // Skip to: 16434 -/* 14027 */ MCD_OPC_CheckField, 16, 5, 0, 96, 9, 0, // Skip to: 16434 -/* 14034 */ MCD_OPC_Decode, 128, 16, 145, 1, // Opcode: XVCVSXDSP -/* 14039 */ MCD_OPC_FilterValue, 1, 86, 9, 0, // Skip to: 16434 -/* 14044 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 14047 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14064 -/* 14052 */ MCD_OPC_CheckField, 16, 5, 0, 71, 9, 0, // Skip to: 16434 -/* 14059 */ MCD_OPC_Decode, 154, 16, 145, 1, // Opcode: XVNABSSP -/* 14064 */ MCD_OPC_FilterValue, 1, 61, 9, 0, // Skip to: 16434 -/* 14069 */ MCD_OPC_CheckField, 16, 5, 0, 54, 9, 0, // Skip to: 16434 -/* 14076 */ MCD_OPC_Decode, 156, 16, 145, 1, // Opcode: XVNEGSP -/* 14081 */ MCD_OPC_FilterValue, 1, 44, 9, 0, // Skip to: 16434 -/* 14086 */ MCD_OPC_Decode, 188, 16, 153, 1, // Opcode: XVTSTDCSP -/* 14091 */ MCD_OPC_FilterValue, 14, 220, 0, 0, // Skip to: 14316 -/* 14096 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... -/* 14099 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 14141 -/* 14104 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 14107 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14124 -/* 14112 */ MCD_OPC_CheckField, 16, 5, 0, 11, 9, 0, // Skip to: 16434 -/* 14119 */ MCD_OPC_Decode, 246, 15, 145, 1, // Opcode: XVCVDPUXDS -/* 14124 */ MCD_OPC_FilterValue, 1, 1, 9, 0, // Skip to: 16434 -/* 14129 */ MCD_OPC_CheckField, 16, 5, 0, 250, 8, 0, // Skip to: 16434 -/* 14136 */ MCD_OPC_Decode, 244, 15, 145, 1, // Opcode: XVCVDPSXDS -/* 14141 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 14183 -/* 14146 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 14149 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14166 -/* 14154 */ MCD_OPC_CheckField, 16, 5, 0, 225, 8, 0, // Skip to: 16434 -/* 14161 */ MCD_OPC_Decode, 249, 15, 145, 1, // Opcode: XVCVSPDP -/* 14166 */ MCD_OPC_FilterValue, 1, 215, 8, 0, // Skip to: 16434 -/* 14171 */ MCD_OPC_CheckField, 16, 5, 0, 208, 8, 0, // Skip to: 16434 -/* 14178 */ MCD_OPC_Decode, 225, 15, 145, 1, // Opcode: XVABSDP -/* 14183 */ MCD_OPC_FilterValue, 3, 198, 8, 0, // Skip to: 16434 -/* 14188 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 14191 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14208 -/* 14196 */ MCD_OPC_CheckField, 1, 1, 0, 183, 8, 0, // Skip to: 16434 -/* 14203 */ MCD_OPC_Decode, 155, 15, 154, 1, // Opcode: XSIEXPDP -/* 14208 */ MCD_OPC_FilterValue, 1, 173, 8, 0, // Skip to: 16434 -/* 14213 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 14216 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 14226 -/* 14221 */ MCD_OPC_Decode, 189, 16, 145, 1, // Opcode: XVXEXPDP -/* 14226 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 14236 -/* 14231 */ MCD_OPC_Decode, 191, 16, 145, 1, // Opcode: XVXSIGDP -/* 14236 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 14246 -/* 14241 */ MCD_OPC_Decode, 194, 16, 145, 1, // Opcode: XXBRH -/* 14246 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 14256 -/* 14251 */ MCD_OPC_Decode, 190, 16, 145, 1, // Opcode: XVXEXPSP -/* 14256 */ MCD_OPC_FilterValue, 9, 5, 0, 0, // Skip to: 14266 -/* 14261 */ MCD_OPC_Decode, 192, 16, 145, 1, // Opcode: XVXSIGSP -/* 14266 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 14276 -/* 14271 */ MCD_OPC_Decode, 196, 16, 145, 1, // Opcode: XXBRW -/* 14276 */ MCD_OPC_FilterValue, 23, 5, 0, 0, // Skip to: 14286 -/* 14281 */ MCD_OPC_Decode, 193, 16, 145, 1, // Opcode: XXBRD -/* 14286 */ MCD_OPC_FilterValue, 24, 5, 0, 0, // Skip to: 14296 -/* 14291 */ MCD_OPC_Decode, 248, 15, 145, 1, // Opcode: XVCVHPSP -/* 14296 */ MCD_OPC_FilterValue, 25, 5, 0, 0, // Skip to: 14306 -/* 14301 */ MCD_OPC_Decode, 250, 15, 145, 1, // Opcode: XVCVSPHP -/* 14306 */ MCD_OPC_FilterValue, 31, 75, 8, 0, // Skip to: 16434 -/* 14311 */ MCD_OPC_Decode, 195, 16, 145, 1, // Opcode: XXBRQ -/* 14316 */ MCD_OPC_FilterValue, 15, 65, 8, 0, // Skip to: 16434 -/* 14321 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... -/* 14324 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 14416 -/* 14329 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 14332 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 14374 -/* 14337 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 14340 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14357 -/* 14345 */ MCD_OPC_CheckField, 16, 5, 0, 34, 8, 0, // Skip to: 16434 -/* 14352 */ MCD_OPC_Decode, 131, 16, 145, 1, // Opcode: XVCVUXDDP -/* 14357 */ MCD_OPC_FilterValue, 1, 24, 8, 0, // Skip to: 16434 -/* 14362 */ MCD_OPC_CheckField, 16, 5, 0, 17, 8, 0, // Skip to: 16434 -/* 14369 */ MCD_OPC_Decode, 255, 15, 145, 1, // Opcode: XVCVSXDDP -/* 14374 */ MCD_OPC_FilterValue, 1, 7, 8, 0, // Skip to: 16434 -/* 14379 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... -/* 14382 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14399 -/* 14387 */ MCD_OPC_CheckField, 16, 5, 0, 248, 7, 0, // Skip to: 16434 -/* 14394 */ MCD_OPC_Decode, 153, 16, 145, 1, // Opcode: XVNABSDP -/* 14399 */ MCD_OPC_FilterValue, 1, 238, 7, 0, // Skip to: 16434 -/* 14404 */ MCD_OPC_CheckField, 16, 5, 0, 231, 7, 0, // Skip to: 16434 -/* 14411 */ MCD_OPC_Decode, 155, 16, 145, 1, // Opcode: XVNEGDP -/* 14416 */ MCD_OPC_FilterValue, 1, 221, 7, 0, // Skip to: 16434 -/* 14421 */ MCD_OPC_Decode, 187, 16, 153, 1, // Opcode: XVTSTDCDP -/* 14426 */ MCD_OPC_FilterValue, 3, 211, 7, 0, // Skip to: 16434 -/* 14431 */ MCD_OPC_Decode, 217, 16, 155, 1, // Opcode: XXSEL -/* 14436 */ MCD_OPC_FilterValue, 61, 49, 0, 0, // Skip to: 14490 -/* 14441 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 14444 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 14472 -/* 14449 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... -/* 14452 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 14462 -/* 14457 */ MCD_OPC_Decode, 134, 8, 156, 1, // Opcode: LXV -/* 14462 */ MCD_OPC_FilterValue, 1, 175, 7, 0, // Skip to: 16434 -/* 14467 */ MCD_OPC_Decode, 241, 11, 156, 1, // Opcode: STXV -/* 14472 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 14481 -/* 14477 */ MCD_OPC_Decode, 232, 11, 122, // Opcode: STXSD -/* 14481 */ MCD_OPC_FilterValue, 3, 156, 7, 0, // Skip to: 16434 -/* 14486 */ MCD_OPC_Decode, 239, 11, 122, // Opcode: STXSSP -/* 14490 */ MCD_OPC_FilterValue, 62, 21, 0, 0, // Skip to: 14516 -/* 14495 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 14498 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 14507 -/* 14503 */ MCD_OPC_Decode, 173, 11, 123, // Opcode: STD -/* 14507 */ MCD_OPC_FilterValue, 1, 130, 7, 0, // Skip to: 16434 -/* 14512 */ MCD_OPC_Decode, 178, 11, 123, // Opcode: STDU -/* 14516 */ MCD_OPC_FilterValue, 63, 121, 7, 0, // Skip to: 16434 -/* 14521 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 14524 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 14606 -/* 14529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 14532 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14549 -/* 14537 */ MCD_OPC_CheckField, 21, 2, 0, 98, 7, 0, // Skip to: 16434 -/* 14544 */ MCD_OPC_Decode, 164, 6, 157, 1, // Opcode: FCMPUS -/* 14549 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 14572 -/* 14554 */ MCD_OPC_CheckField, 21, 2, 0, 81, 7, 0, // Skip to: 16434 -/* 14561 */ MCD_OPC_CheckField, 11, 7, 0, 74, 7, 0, // Skip to: 16434 -/* 14568 */ MCD_OPC_Decode, 149, 8, 33, // Opcode: MCRFS -/* 14572 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 14589 -/* 14577 */ MCD_OPC_CheckField, 21, 2, 0, 58, 7, 0, // Skip to: 16434 -/* 14584 */ MCD_OPC_Decode, 129, 7, 158, 1, // Opcode: FTDIV -/* 14589 */ MCD_OPC_FilterValue, 5, 48, 7, 0, // Skip to: 16434 -/* 14594 */ MCD_OPC_CheckField, 16, 7, 0, 41, 7, 0, // Skip to: 16434 -/* 14601 */ MCD_OPC_Decode, 130, 7, 159, 1, // Opcode: FTSQRT -/* 14606 */ MCD_OPC_FilterValue, 8, 49, 1, 0, // Skip to: 14916 -/* 14611 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 14614 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 14623 -/* 14619 */ MCD_OPC_Decode, 238, 14, 3, // Opcode: XSADDQP -/* 14623 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 14632 -/* 14628 */ MCD_OPC_Decode, 176, 15, 3, // Opcode: XSMULQP -/* 14632 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 14641 -/* 14637 */ MCD_OPC_Decode, 251, 14, 3, // Opcode: XSCPSGNQP -/* 14641 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 14658 -/* 14646 */ MCD_OPC_CheckField, 21, 2, 0, 245, 6, 0, // Skip to: 16434 -/* 14653 */ MCD_OPC_Decode, 247, 14, 160, 1, // Opcode: XSCMPOQP -/* 14658 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 14675 -/* 14663 */ MCD_OPC_CheckField, 21, 2, 0, 228, 6, 0, // Skip to: 16434 -/* 14670 */ MCD_OPC_Decode, 243, 14, 160, 1, // Opcode: XSCMPEXPQP -/* 14675 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 14685 -/* 14680 */ MCD_OPC_Decode, 161, 15, 161, 1, // Opcode: XSMADDQP -/* 14685 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 14695 -/* 14690 */ MCD_OPC_Decode, 173, 15, 161, 1, // Opcode: XSMSUBQP -/* 14695 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 14705 -/* 14700 */ MCD_OPC_Decode, 187, 15, 161, 1, // Opcode: XSNMADDQP -/* 14705 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 14715 -/* 14710 */ MCD_OPC_Decode, 193, 15, 161, 1, // Opcode: XSNMSUBQP -/* 14715 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 14724 -/* 14720 */ MCD_OPC_Decode, 213, 15, 3, // Opcode: XSSUBQP -/* 14724 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 14733 -/* 14729 */ MCD_OPC_Decode, 152, 15, 3, // Opcode: XSDIVQP -/* 14733 */ MCD_OPC_FilterValue, 20, 12, 0, 0, // Skip to: 14750 -/* 14738 */ MCD_OPC_CheckField, 21, 2, 0, 153, 6, 0, // Skip to: 16434 -/* 14745 */ MCD_OPC_Decode, 249, 14, 160, 1, // Opcode: XSCMPUQP -/* 14750 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 14760 -/* 14755 */ MCD_OPC_Decode, 219, 15, 162, 1, // Opcode: XSTSTDCQP -/* 14760 */ MCD_OPC_FilterValue, 25, 57, 0, 0, // Skip to: 14822 -/* 14765 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 14768 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 14777 -/* 14773 */ MCD_OPC_Decode, 236, 14, 6, // Opcode: XSABSQP -/* 14777 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 14786 -/* 14782 */ MCD_OPC_Decode, 222, 15, 6, // Opcode: XSXEXPQP -/* 14786 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 14795 -/* 14791 */ MCD_OPC_Decode, 180, 15, 6, // Opcode: XSNABSQP -/* 14795 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 14804 -/* 14800 */ MCD_OPC_Decode, 182, 15, 6, // Opcode: XSNEGQP -/* 14804 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 14813 -/* 14809 */ MCD_OPC_Decode, 224, 15, 6, // Opcode: XSXSIGQP -/* 14813 */ MCD_OPC_FilterValue, 27, 80, 6, 0, // Skip to: 16434 -/* 14818 */ MCD_OPC_Decode, 209, 15, 6, // Opcode: XSSQRTQP -/* 14822 */ MCD_OPC_FilterValue, 26, 79, 0, 0, // Skip to: 14906 -/* 14827 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 14830 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 14839 -/* 14835 */ MCD_OPC_Decode, 142, 15, 6, // Opcode: XSCVQPUWZ -/* 14839 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 14849 -/* 14844 */ MCD_OPC_Decode, 148, 15, 163, 1, // Opcode: XSCVUDQP -/* 14849 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 14858 -/* 14854 */ MCD_OPC_Decode, 140, 15, 6, // Opcode: XSCVQPSWZ -/* 14858 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 14868 -/* 14863 */ MCD_OPC_Decode, 143, 15, 163, 1, // Opcode: XSCVSDQP -/* 14868 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 14877 -/* 14873 */ MCD_OPC_Decode, 141, 15, 6, // Opcode: XSCVQPUDZ -/* 14877 */ MCD_OPC_FilterValue, 20, 5, 0, 0, // Skip to: 14887 -/* 14882 */ MCD_OPC_Decode, 137, 15, 164, 1, // Opcode: XSCVQPDP -/* 14887 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 14897 -/* 14892 */ MCD_OPC_Decode, 253, 14, 163, 1, // Opcode: XSCVDPQP -/* 14897 */ MCD_OPC_FilterValue, 25, 252, 5, 0, // Skip to: 16434 -/* 14902 */ MCD_OPC_Decode, 139, 15, 6, // Opcode: XSCVQPSDZ -/* 14906 */ MCD_OPC_FilterValue, 27, 243, 5, 0, // Skip to: 16434 -/* 14911 */ MCD_OPC_Decode, 156, 15, 165, 1, // Opcode: XSIEXPQP -/* 14916 */ MCD_OPC_FilterValue, 9, 112, 0, 0, // Skip to: 15033 -/* 14921 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 14924 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 14933 -/* 14929 */ MCD_OPC_Decode, 239, 14, 3, // Opcode: XSADDQPO -/* 14933 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 14942 -/* 14938 */ MCD_OPC_Decode, 177, 15, 3, // Opcode: XSMULQPO -/* 14942 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 14952 -/* 14947 */ MCD_OPC_Decode, 162, 15, 161, 1, // Opcode: XSMADDQPO -/* 14952 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 14962 -/* 14957 */ MCD_OPC_Decode, 174, 15, 161, 1, // Opcode: XSMSUBQPO -/* 14962 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 14972 -/* 14967 */ MCD_OPC_Decode, 188, 15, 161, 1, // Opcode: XSNMADDQPO -/* 14972 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 14982 -/* 14977 */ MCD_OPC_Decode, 194, 15, 161, 1, // Opcode: XSNMSUBQPO -/* 14982 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 14991 -/* 14987 */ MCD_OPC_Decode, 214, 15, 3, // Opcode: XSSUBQPO -/* 14991 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 15000 -/* 14996 */ MCD_OPC_Decode, 153, 15, 3, // Opcode: XSDIVQPO -/* 15000 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 15016 -/* 15005 */ MCD_OPC_CheckField, 16, 5, 27, 142, 5, 0, // Skip to: 16434 -/* 15012 */ MCD_OPC_Decode, 210, 15, 6, // Opcode: XSSQRTQPO -/* 15016 */ MCD_OPC_FilterValue, 26, 133, 5, 0, // Skip to: 16434 -/* 15021 */ MCD_OPC_CheckField, 16, 5, 20, 126, 5, 0, // Skip to: 16434 -/* 15028 */ MCD_OPC_Decode, 138, 15, 164, 1, // Opcode: XSCVQPDPO -/* 15033 */ MCD_OPC_FilterValue, 10, 37, 0, 0, // Skip to: 15075 -/* 15038 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... -/* 15041 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15058 -/* 15046 */ MCD_OPC_CheckField, 17, 4, 0, 101, 5, 0, // Skip to: 16434 -/* 15053 */ MCD_OPC_Decode, 202, 15, 166, 1, // Opcode: XSRQPI -/* 15058 */ MCD_OPC_FilterValue, 1, 91, 5, 0, // Skip to: 16434 -/* 15063 */ MCD_OPC_CheckField, 17, 4, 0, 84, 5, 0, // Skip to: 16434 -/* 15070 */ MCD_OPC_Decode, 204, 15, 166, 1, // Opcode: XSRQPXP -/* 15075 */ MCD_OPC_FilterValue, 11, 19, 0, 0, // Skip to: 15099 -/* 15080 */ MCD_OPC_CheckField, 17, 4, 0, 67, 5, 0, // Skip to: 16434 -/* 15087 */ MCD_OPC_CheckField, 6, 3, 0, 60, 5, 0, // Skip to: 16434 -/* 15094 */ MCD_OPC_Decode, 203, 15, 166, 1, // Opcode: XSRQPIX -/* 15099 */ MCD_OPC_FilterValue, 12, 52, 0, 0, // Skip to: 15156 -/* 15104 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... -/* 15107 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 15123 -/* 15112 */ MCD_OPC_CheckField, 12, 9, 0, 35, 5, 0, // Skip to: 16434 -/* 15119 */ MCD_OPC_Decode, 198, 8, 110, // Opcode: MTFSB1 -/* 15123 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 15139 -/* 15128 */ MCD_OPC_CheckField, 12, 9, 0, 19, 5, 0, // Skip to: 16434 -/* 15135 */ MCD_OPC_Decode, 197, 8, 110, // Opcode: MTFSB0 -/* 15139 */ MCD_OPC_FilterValue, 4, 10, 5, 0, // Skip to: 16434 -/* 15144 */ MCD_OPC_CheckField, 17, 6, 0, 3, 5, 0, // Skip to: 16434 -/* 15151 */ MCD_OPC_Decode, 200, 8, 167, 1, // Opcode: MTFSFI -/* 15156 */ MCD_OPC_FilterValue, 13, 19, 0, 0, // Skip to: 15180 -/* 15161 */ MCD_OPC_CheckField, 17, 6, 0, 242, 4, 0, // Skip to: 16434 -/* 15168 */ MCD_OPC_CheckField, 6, 6, 4, 235, 4, 0, // Skip to: 16434 -/* 15175 */ MCD_OPC_Decode, 201, 8, 167, 1, // Opcode: MTFSFIo -/* 15180 */ MCD_OPC_FilterValue, 14, 126, 0, 0, // Skip to: 15311 -/* 15185 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 15188 */ MCD_OPC_FilterValue, 18, 108, 0, 0, // Skip to: 15301 -/* 15193 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 15196 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15213 -/* 15201 */ MCD_OPC_CheckField, 11, 5, 0, 202, 4, 0, // Skip to: 16434 -/* 15208 */ MCD_OPC_Decode, 157, 8, 168, 1, // Opcode: MFFS -/* 15213 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 15230 -/* 15218 */ MCD_OPC_CheckField, 11, 5, 0, 185, 4, 0, // Skip to: 16434 -/* 15225 */ MCD_OPC_Decode, 160, 8, 168, 1, // Opcode: MFFSCE -/* 15230 */ MCD_OPC_FilterValue, 20, 5, 0, 0, // Skip to: 15240 -/* 15235 */ MCD_OPC_Decode, 158, 8, 169, 1, // Opcode: MFFSCDRN -/* 15240 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 15257 -/* 15245 */ MCD_OPC_CheckField, 14, 2, 0, 158, 4, 0, // Skip to: 16434 -/* 15252 */ MCD_OPC_Decode, 159, 8, 170, 1, // Opcode: MFFSCDRNI -/* 15257 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 15267 -/* 15262 */ MCD_OPC_Decode, 161, 8, 169, 1, // Opcode: MFFSCRN -/* 15267 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 15284 -/* 15272 */ MCD_OPC_CheckField, 13, 3, 0, 131, 4, 0, // Skip to: 16434 -/* 15279 */ MCD_OPC_Decode, 162, 8, 171, 1, // Opcode: MFFSCRNI -/* 15284 */ MCD_OPC_FilterValue, 24, 121, 4, 0, // Skip to: 16434 -/* 15289 */ MCD_OPC_CheckField, 11, 5, 0, 114, 4, 0, // Skip to: 16434 -/* 15296 */ MCD_OPC_Decode, 163, 8, 168, 1, // Opcode: MFFSL -/* 15301 */ MCD_OPC_FilterValue, 22, 104, 4, 0, // Skip to: 16434 -/* 15306 */ MCD_OPC_Decode, 199, 8, 172, 1, // Opcode: MTFSF -/* 15311 */ MCD_OPC_FilterValue, 15, 30, 0, 0, // Skip to: 15346 -/* 15316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 15319 */ MCD_OPC_FilterValue, 18, 12, 0, 0, // Skip to: 15336 -/* 15324 */ MCD_OPC_CheckField, 11, 10, 0, 79, 4, 0, // Skip to: 16434 -/* 15331 */ MCD_OPC_Decode, 164, 8, 168, 1, // Opcode: MFFSo -/* 15336 */ MCD_OPC_FilterValue, 22, 69, 4, 0, // Skip to: 16434 -/* 15341 */ MCD_OPC_Decode, 203, 8, 172, 1, // Opcode: MTFSFo -/* 15346 */ MCD_OPC_FilterValue, 16, 140, 0, 0, // Skip to: 15491 -/* 15351 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 15354 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 15363 -/* 15359 */ MCD_OPC_Decode, 167, 6, 125, // Opcode: FCPSGNS -/* 15363 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 15379 -/* 15368 */ MCD_OPC_CheckField, 16, 5, 0, 35, 4, 0, // Skip to: 16434 -/* 15375 */ MCD_OPC_Decode, 209, 6, 126, // Opcode: FNEGS -/* 15379 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 15395 -/* 15384 */ MCD_OPC_CheckField, 16, 5, 0, 19, 4, 0, // Skip to: 16434 -/* 15391 */ MCD_OPC_Decode, 193, 6, 126, // Opcode: FMR -/* 15395 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 15411 -/* 15400 */ MCD_OPC_CheckField, 16, 5, 0, 3, 4, 0, // Skip to: 16434 -/* 15407 */ MCD_OPC_Decode, 205, 6, 126, // Opcode: FNABSS -/* 15411 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 15427 -/* 15416 */ MCD_OPC_CheckField, 16, 5, 0, 243, 3, 0, // Skip to: 16434 -/* 15423 */ MCD_OPC_Decode, 148, 6, 126, // Opcode: FABSS -/* 15427 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 15443 -/* 15432 */ MCD_OPC_CheckField, 16, 5, 0, 227, 3, 0, // Skip to: 16434 -/* 15439 */ MCD_OPC_Decode, 229, 6, 126, // Opcode: FRINS -/* 15443 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 15459 -/* 15448 */ MCD_OPC_CheckField, 16, 5, 0, 211, 3, 0, // Skip to: 16434 -/* 15455 */ MCD_OPC_Decode, 237, 6, 126, // Opcode: FRIZS -/* 15459 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 15475 -/* 15464 */ MCD_OPC_CheckField, 16, 5, 0, 195, 3, 0, // Skip to: 16434 -/* 15471 */ MCD_OPC_Decode, 233, 6, 126, // Opcode: FRIPS -/* 15475 */ MCD_OPC_FilterValue, 15, 186, 3, 0, // Skip to: 16434 -/* 15480 */ MCD_OPC_CheckField, 16, 5, 0, 179, 3, 0, // Skip to: 16434 -/* 15487 */ MCD_OPC_Decode, 225, 6, 126, // Opcode: FRIMS -/* 15491 */ MCD_OPC_FilterValue, 17, 140, 0, 0, // Skip to: 15636 -/* 15496 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 15499 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 15508 -/* 15504 */ MCD_OPC_Decode, 168, 6, 125, // Opcode: FCPSGNSo -/* 15508 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 15524 -/* 15513 */ MCD_OPC_CheckField, 16, 5, 0, 146, 3, 0, // Skip to: 16434 -/* 15520 */ MCD_OPC_Decode, 210, 6, 126, // Opcode: FNEGSo -/* 15524 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 15540 -/* 15529 */ MCD_OPC_CheckField, 16, 5, 0, 130, 3, 0, // Skip to: 16434 -/* 15536 */ MCD_OPC_Decode, 194, 6, 126, // Opcode: FMRo -/* 15540 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 15556 -/* 15545 */ MCD_OPC_CheckField, 16, 5, 0, 114, 3, 0, // Skip to: 16434 -/* 15552 */ MCD_OPC_Decode, 206, 6, 126, // Opcode: FNABSSo -/* 15556 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 15572 -/* 15561 */ MCD_OPC_CheckField, 16, 5, 0, 98, 3, 0, // Skip to: 16434 -/* 15568 */ MCD_OPC_Decode, 149, 6, 126, // Opcode: FABSSo -/* 15572 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 15588 -/* 15577 */ MCD_OPC_CheckField, 16, 5, 0, 82, 3, 0, // Skip to: 16434 -/* 15584 */ MCD_OPC_Decode, 230, 6, 126, // Opcode: FRINSo -/* 15588 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 15604 -/* 15593 */ MCD_OPC_CheckField, 16, 5, 0, 66, 3, 0, // Skip to: 16434 -/* 15600 */ MCD_OPC_Decode, 238, 6, 126, // Opcode: FRIZSo -/* 15604 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 15620 -/* 15609 */ MCD_OPC_CheckField, 16, 5, 0, 50, 3, 0, // Skip to: 16434 -/* 15616 */ MCD_OPC_Decode, 234, 6, 126, // Opcode: FRIPSo -/* 15620 */ MCD_OPC_FilterValue, 15, 41, 3, 0, // Skip to: 16434 -/* 15625 */ MCD_OPC_CheckField, 16, 5, 0, 34, 3, 0, // Skip to: 16434 -/* 15632 */ MCD_OPC_Decode, 226, 6, 126, // Opcode: FRIMSo -/* 15636 */ MCD_OPC_FilterValue, 24, 18, 0, 0, // Skip to: 15659 -/* 15641 */ MCD_OPC_CheckField, 16, 5, 0, 18, 3, 0, // Skip to: 16434 -/* 15648 */ MCD_OPC_CheckField, 6, 5, 0, 11, 3, 0, // Skip to: 16434 -/* 15655 */ MCD_OPC_Decode, 239, 6, 124, // Opcode: FRSP -/* 15659 */ MCD_OPC_FilterValue, 25, 18, 0, 0, // Skip to: 15682 -/* 15664 */ MCD_OPC_CheckField, 16, 5, 0, 251, 2, 0, // Skip to: 16434 -/* 15671 */ MCD_OPC_CheckField, 6, 5, 0, 244, 2, 0, // Skip to: 16434 -/* 15678 */ MCD_OPC_Decode, 240, 6, 124, // Opcode: FRSPo -/* 15682 */ MCD_OPC_FilterValue, 28, 105, 0, 0, // Skip to: 15792 -/* 15687 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 15690 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15707 -/* 15695 */ MCD_OPC_CheckField, 16, 5, 0, 220, 2, 0, // Skip to: 16434 -/* 15702 */ MCD_OPC_Decode, 177, 6, 169, 1, // Opcode: FCTIW -/* 15707 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 15724 -/* 15712 */ MCD_OPC_CheckField, 16, 5, 0, 203, 2, 0, // Skip to: 16434 -/* 15719 */ MCD_OPC_Decode, 178, 6, 169, 1, // Opcode: FCTIWU -/* 15724 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 15741 -/* 15729 */ MCD_OPC_CheckField, 16, 5, 0, 186, 2, 0, // Skip to: 16434 -/* 15736 */ MCD_OPC_Decode, 169, 6, 169, 1, // Opcode: FCTID -/* 15741 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 15758 -/* 15746 */ MCD_OPC_CheckField, 16, 5, 0, 169, 2, 0, // Skip to: 16434 -/* 15753 */ MCD_OPC_Decode, 155, 6, 169, 1, // Opcode: FCFID -/* 15758 */ MCD_OPC_FilterValue, 29, 12, 0, 0, // Skip to: 15775 -/* 15763 */ MCD_OPC_CheckField, 16, 5, 0, 152, 2, 0, // Skip to: 16434 -/* 15770 */ MCD_OPC_Decode, 170, 6, 169, 1, // Opcode: FCTIDU -/* 15775 */ MCD_OPC_FilterValue, 30, 142, 2, 0, // Skip to: 16434 -/* 15780 */ MCD_OPC_CheckField, 16, 5, 0, 135, 2, 0, // Skip to: 16434 -/* 15787 */ MCD_OPC_Decode, 158, 6, 169, 1, // Opcode: FCFIDU -/* 15792 */ MCD_OPC_FilterValue, 29, 105, 0, 0, // Skip to: 15902 -/* 15797 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 15800 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15817 -/* 15805 */ MCD_OPC_CheckField, 16, 5, 0, 110, 2, 0, // Skip to: 16434 -/* 15812 */ MCD_OPC_Decode, 184, 6, 169, 1, // Opcode: FCTIWo -/* 15817 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 15834 -/* 15822 */ MCD_OPC_CheckField, 16, 5, 0, 93, 2, 0, // Skip to: 16434 -/* 15829 */ MCD_OPC_Decode, 181, 6, 169, 1, // Opcode: FCTIWUo -/* 15834 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 15851 -/* 15839 */ MCD_OPC_CheckField, 16, 5, 0, 76, 2, 0, // Skip to: 16434 -/* 15846 */ MCD_OPC_Decode, 176, 6, 169, 1, // Opcode: FCTIDo -/* 15851 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 15868 -/* 15856 */ MCD_OPC_CheckField, 16, 5, 0, 59, 2, 0, // Skip to: 16434 -/* 15863 */ MCD_OPC_Decode, 162, 6, 169, 1, // Opcode: FCFIDo -/* 15868 */ MCD_OPC_FilterValue, 29, 12, 0, 0, // Skip to: 15885 -/* 15873 */ MCD_OPC_CheckField, 16, 5, 0, 42, 2, 0, // Skip to: 16434 -/* 15880 */ MCD_OPC_Decode, 173, 6, 169, 1, // Opcode: FCTIDUo -/* 15885 */ MCD_OPC_FilterValue, 30, 32, 2, 0, // Skip to: 16434 -/* 15890 */ MCD_OPC_CheckField, 16, 5, 0, 25, 2, 0, // Skip to: 16434 -/* 15897 */ MCD_OPC_Decode, 161, 6, 169, 1, // Opcode: FCFIDUo -/* 15902 */ MCD_OPC_FilterValue, 30, 71, 0, 0, // Skip to: 15978 -/* 15907 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 15910 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15927 -/* 15915 */ MCD_OPC_CheckField, 16, 5, 0, 0, 2, 0, // Skip to: 16434 -/* 15922 */ MCD_OPC_Decode, 182, 6, 169, 1, // Opcode: FCTIWZ -/* 15927 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 15944 -/* 15932 */ MCD_OPC_CheckField, 16, 5, 0, 239, 1, 0, // Skip to: 16434 -/* 15939 */ MCD_OPC_Decode, 179, 6, 169, 1, // Opcode: FCTIWUZ -/* 15944 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 15961 -/* 15949 */ MCD_OPC_CheckField, 16, 5, 0, 222, 1, 0, // Skip to: 16434 -/* 15956 */ MCD_OPC_Decode, 174, 6, 169, 1, // Opcode: FCTIDZ -/* 15961 */ MCD_OPC_FilterValue, 29, 212, 1, 0, // Skip to: 16434 -/* 15966 */ MCD_OPC_CheckField, 16, 5, 0, 205, 1, 0, // Skip to: 16434 -/* 15973 */ MCD_OPC_Decode, 171, 6, 169, 1, // Opcode: FCTIDUZ -/* 15978 */ MCD_OPC_FilterValue, 31, 71, 0, 0, // Skip to: 16054 -/* 15983 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 15986 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 16003 -/* 15991 */ MCD_OPC_CheckField, 16, 5, 0, 180, 1, 0, // Skip to: 16434 -/* 15998 */ MCD_OPC_Decode, 183, 6, 169, 1, // Opcode: FCTIWZo -/* 16003 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 16020 -/* 16008 */ MCD_OPC_CheckField, 16, 5, 0, 163, 1, 0, // Skip to: 16434 -/* 16015 */ MCD_OPC_Decode, 180, 6, 169, 1, // Opcode: FCTIWUZo -/* 16020 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 16037 -/* 16025 */ MCD_OPC_CheckField, 16, 5, 0, 146, 1, 0, // Skip to: 16434 -/* 16032 */ MCD_OPC_Decode, 175, 6, 169, 1, // Opcode: FCTIDZo -/* 16037 */ MCD_OPC_FilterValue, 29, 136, 1, 0, // Skip to: 16434 -/* 16042 */ MCD_OPC_CheckField, 16, 5, 0, 129, 1, 0, // Skip to: 16434 -/* 16049 */ MCD_OPC_Decode, 172, 6, 169, 1, // Opcode: FCTIDUZo -/* 16054 */ MCD_OPC_FilterValue, 36, 12, 0, 0, // Skip to: 16071 -/* 16059 */ MCD_OPC_CheckField, 6, 5, 0, 112, 1, 0, // Skip to: 16434 -/* 16066 */ MCD_OPC_Decode, 185, 6, 173, 1, // Opcode: FDIV -/* 16071 */ MCD_OPC_FilterValue, 37, 12, 0, 0, // Skip to: 16088 -/* 16076 */ MCD_OPC_CheckField, 6, 5, 0, 95, 1, 0, // Skip to: 16434 -/* 16083 */ MCD_OPC_Decode, 188, 6, 173, 1, // Opcode: FDIVo -/* 16088 */ MCD_OPC_FilterValue, 40, 12, 0, 0, // Skip to: 16105 -/* 16093 */ MCD_OPC_CheckField, 6, 5, 0, 78, 1, 0, // Skip to: 16434 -/* 16100 */ MCD_OPC_Decode, 253, 6, 173, 1, // Opcode: FSUB -/* 16105 */ MCD_OPC_FilterValue, 41, 12, 0, 0, // Skip to: 16122 -/* 16110 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, 0, // Skip to: 16434 -/* 16117 */ MCD_OPC_Decode, 128, 7, 173, 1, // Opcode: FSUBo -/* 16122 */ MCD_OPC_FilterValue, 42, 12, 0, 0, // Skip to: 16139 -/* 16127 */ MCD_OPC_CheckField, 6, 5, 0, 44, 1, 0, // Skip to: 16434 -/* 16134 */ MCD_OPC_Decode, 150, 6, 173, 1, // Opcode: FADD -/* 16139 */ MCD_OPC_FilterValue, 43, 12, 0, 0, // Skip to: 16156 -/* 16144 */ MCD_OPC_CheckField, 6, 5, 0, 27, 1, 0, // Skip to: 16434 -/* 16151 */ MCD_OPC_Decode, 153, 6, 173, 1, // Opcode: FADDo -/* 16156 */ MCD_OPC_FilterValue, 44, 19, 0, 0, // Skip to: 16180 -/* 16161 */ MCD_OPC_CheckField, 16, 5, 0, 10, 1, 0, // Skip to: 16434 -/* 16168 */ MCD_OPC_CheckField, 6, 5, 0, 3, 1, 0, // Skip to: 16434 -/* 16175 */ MCD_OPC_Decode, 249, 6, 169, 1, // Opcode: FSQRT -/* 16180 */ MCD_OPC_FilterValue, 45, 19, 0, 0, // Skip to: 16204 -/* 16185 */ MCD_OPC_CheckField, 16, 5, 0, 242, 0, 0, // Skip to: 16434 -/* 16192 */ MCD_OPC_CheckField, 6, 5, 0, 235, 0, 0, // Skip to: 16434 -/* 16199 */ MCD_OPC_Decode, 252, 6, 169, 1, // Opcode: FSQRTo -/* 16204 */ MCD_OPC_FilterValue, 46, 5, 0, 0, // Skip to: 16214 -/* 16209 */ MCD_OPC_Decode, 247, 6, 174, 1, // Opcode: FSELS -/* 16214 */ MCD_OPC_FilterValue, 47, 5, 0, 0, // Skip to: 16224 -/* 16219 */ MCD_OPC_Decode, 248, 6, 174, 1, // Opcode: FSELSo -/* 16224 */ MCD_OPC_FilterValue, 48, 19, 0, 0, // Skip to: 16248 -/* 16229 */ MCD_OPC_CheckField, 16, 5, 0, 198, 0, 0, // Skip to: 16434 -/* 16236 */ MCD_OPC_CheckField, 6, 5, 0, 191, 0, 0, // Skip to: 16434 -/* 16243 */ MCD_OPC_Decode, 219, 6, 169, 1, // Opcode: FRE -/* 16248 */ MCD_OPC_FilterValue, 49, 19, 0, 0, // Skip to: 16272 -/* 16253 */ MCD_OPC_CheckField, 16, 5, 0, 174, 0, 0, // Skip to: 16434 -/* 16260 */ MCD_OPC_CheckField, 6, 5, 0, 167, 0, 0, // Skip to: 16434 -/* 16267 */ MCD_OPC_Decode, 222, 6, 169, 1, // Opcode: FREo -/* 16272 */ MCD_OPC_FilterValue, 50, 12, 0, 0, // Skip to: 16289 -/* 16277 */ MCD_OPC_CheckField, 11, 5, 0, 150, 0, 0, // Skip to: 16434 -/* 16284 */ MCD_OPC_Decode, 199, 6, 175, 1, // Opcode: FMUL -/* 16289 */ MCD_OPC_FilterValue, 51, 12, 0, 0, // Skip to: 16306 -/* 16294 */ MCD_OPC_CheckField, 11, 5, 0, 133, 0, 0, // Skip to: 16434 -/* 16301 */ MCD_OPC_Decode, 202, 6, 175, 1, // Opcode: FMULo -/* 16306 */ MCD_OPC_FilterValue, 52, 19, 0, 0, // Skip to: 16330 -/* 16311 */ MCD_OPC_CheckField, 16, 5, 0, 116, 0, 0, // Skip to: 16434 -/* 16318 */ MCD_OPC_CheckField, 6, 5, 0, 109, 0, 0, // Skip to: 16434 -/* 16325 */ MCD_OPC_Decode, 241, 6, 169, 1, // Opcode: FRSQRTE -/* 16330 */ MCD_OPC_FilterValue, 53, 19, 0, 0, // Skip to: 16354 -/* 16335 */ MCD_OPC_CheckField, 16, 5, 0, 92, 0, 0, // Skip to: 16434 -/* 16342 */ MCD_OPC_CheckField, 6, 5, 0, 85, 0, 0, // Skip to: 16434 -/* 16349 */ MCD_OPC_Decode, 244, 6, 169, 1, // Opcode: FRSQRTEo -/* 16354 */ MCD_OPC_FilterValue, 56, 5, 0, 0, // Skip to: 16364 -/* 16359 */ MCD_OPC_Decode, 195, 6, 176, 1, // Opcode: FMSUB -/* 16364 */ MCD_OPC_FilterValue, 57, 5, 0, 0, // Skip to: 16374 -/* 16369 */ MCD_OPC_Decode, 198, 6, 176, 1, // Opcode: FMSUBo -/* 16374 */ MCD_OPC_FilterValue, 58, 5, 0, 0, // Skip to: 16384 -/* 16379 */ MCD_OPC_Decode, 189, 6, 176, 1, // Opcode: FMADD -/* 16384 */ MCD_OPC_FilterValue, 59, 5, 0, 0, // Skip to: 16394 -/* 16389 */ MCD_OPC_Decode, 192, 6, 176, 1, // Opcode: FMADDo -/* 16394 */ MCD_OPC_FilterValue, 60, 5, 0, 0, // Skip to: 16404 -/* 16399 */ MCD_OPC_Decode, 215, 6, 176, 1, // Opcode: FNMSUB -/* 16404 */ MCD_OPC_FilterValue, 61, 5, 0, 0, // Skip to: 16414 -/* 16409 */ MCD_OPC_Decode, 218, 6, 176, 1, // Opcode: FNMSUBo -/* 16414 */ MCD_OPC_FilterValue, 62, 5, 0, 0, // Skip to: 16424 -/* 16419 */ MCD_OPC_Decode, 211, 6, 176, 1, // Opcode: FNMADD -/* 16424 */ MCD_OPC_FilterValue, 63, 5, 0, 0, // Skip to: 16434 -/* 16429 */ MCD_OPC_Decode, 214, 6, 176, 1, // Opcode: FNMADDo -/* 16434 */ MCD_OPC_Fail, +/* 9768 */ MCD_OPC_Decode, 143, 3, 82, // Opcode: ADDZE_rec +/* 9772 */ MCD_OPC_FilterValue, 2, 67, 46, 0, // Skip to: 21620 +/* 9777 */ MCD_OPC_Decode, 142, 3, 82, // Opcode: ADDZEO_rec +/* 9781 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 9807 +/* 9786 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9789 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9798 +/* 9794 */ MCD_OPC_Decode, 163, 5, 80, // Opcode: DIVWU +/* 9798 */ MCD_OPC_FilterValue, 3, 41, 46, 0, // Skip to: 21620 +/* 9803 */ MCD_OPC_Decode, 164, 5, 80, // Opcode: DIVWUO +/* 9807 */ MCD_OPC_FilterValue, 3, 32, 46, 0, // Skip to: 21620 +/* 9812 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9815 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9824 +/* 9820 */ MCD_OPC_Decode, 166, 5, 80, // Opcode: DIVWU_rec +/* 9824 */ MCD_OPC_FilterValue, 3, 15, 46, 0, // Skip to: 21620 +/* 9829 */ MCD_OPC_Decode, 165, 5, 80, // Opcode: DIVWUO_rec +/* 9833 */ MCD_OPC_FilterValue, 7, 6, 46, 0, // Skip to: 21620 +/* 9838 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 9841 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 9867 +/* 9846 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... +/* 9849 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9858 +/* 9854 */ MCD_OPC_Decode, 255, 2, 82, // Opcode: ADDME +/* 9858 */ MCD_OPC_FilterValue, 2, 237, 45, 0, // Skip to: 21620 +/* 9863 */ MCD_OPC_Decode, 132, 3, 82, // Opcode: ADDMEO +/* 9867 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 9893 +/* 9872 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... +/* 9875 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9884 +/* 9880 */ MCD_OPC_Decode, 134, 3, 82, // Opcode: ADDME_rec +/* 9884 */ MCD_OPC_FilterValue, 2, 211, 45, 0, // Skip to: 21620 +/* 9889 */ MCD_OPC_Decode, 133, 3, 82, // Opcode: ADDMEO_rec +/* 9893 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 9937 +/* 9898 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9901 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9910 +/* 9906 */ MCD_OPC_Decode, 198, 10, 80, // Opcode: MULLW +/* 9910 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9919 +/* 9915 */ MCD_OPC_Decode, 152, 5, 80, // Opcode: DIVW +/* 9919 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9928 +/* 9924 */ MCD_OPC_Decode, 199, 10, 80, // Opcode: MULLWO +/* 9928 */ MCD_OPC_FilterValue, 3, 167, 45, 0, // Skip to: 21620 +/* 9933 */ MCD_OPC_Decode, 161, 5, 80, // Opcode: DIVWO +/* 9937 */ MCD_OPC_FilterValue, 3, 158, 45, 0, // Skip to: 21620 +/* 9942 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 9945 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9954 +/* 9950 */ MCD_OPC_Decode, 201, 10, 80, // Opcode: MULLW_rec +/* 9954 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 9963 +/* 9959 */ MCD_OPC_Decode, 167, 5, 80, // Opcode: DIVW_rec +/* 9963 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9972 +/* 9968 */ MCD_OPC_Decode, 200, 10, 80, // Opcode: MULLWO_rec +/* 9972 */ MCD_OPC_FilterValue, 3, 123, 45, 0, // Skip to: 21620 +/* 9977 */ MCD_OPC_Decode, 162, 5, 80, // Opcode: DIVWO_rec +/* 9981 */ MCD_OPC_FilterValue, 6, 30, 2, 0, // Skip to: 10528 +/* 9986 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 9989 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 10015 +/* 9994 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 9997 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10006 +/* 10002 */ MCD_OPC_Decode, 202, 9, 84, // Opcode: LXSIWZX +/* 10006 */ MCD_OPC_FilterValue, 1, 89, 45, 0, // Skip to: 21620 +/* 10011 */ MCD_OPC_Decode, 214, 9, 85, // Opcode: LXVRBX +/* 10015 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 10031 +/* 10020 */ MCD_OPC_CheckField, 1, 1, 1, 73, 45, 0, // Skip to: 21620 +/* 10027 */ MCD_OPC_Decode, 216, 9, 85, // Opcode: LXVRHX +/* 10031 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 10057 +/* 10036 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 10039 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10048 +/* 10044 */ MCD_OPC_Decode, 201, 9, 84, // Opcode: LXSIWAX +/* 10048 */ MCD_OPC_FilterValue, 1, 47, 45, 0, // Skip to: 21620 +/* 10053 */ MCD_OPC_Decode, 217, 9, 85, // Opcode: LXVRWX +/* 10057 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 10073 +/* 10062 */ MCD_OPC_CheckField, 1, 1, 1, 31, 45, 0, // Skip to: 21620 +/* 10069 */ MCD_OPC_Decode, 215, 9, 85, // Opcode: LXVRDX +/* 10073 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 10099 +/* 10078 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 10081 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10090 +/* 10086 */ MCD_OPC_Decode, 163, 13, 84, // Opcode: STXSIWX +/* 10090 */ MCD_OPC_FilterValue, 1, 5, 45, 0, // Skip to: 21620 +/* 10095 */ MCD_OPC_Decode, 174, 13, 85, // Opcode: STXVRBX +/* 10099 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 10115 +/* 10104 */ MCD_OPC_CheckField, 1, 1, 1, 245, 44, 0, // Skip to: 21620 +/* 10111 */ MCD_OPC_Decode, 176, 13, 85, // Opcode: STXVRHX +/* 10115 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 10131 +/* 10120 */ MCD_OPC_CheckField, 1, 1, 1, 229, 44, 0, // Skip to: 21620 +/* 10127 */ MCD_OPC_Decode, 177, 13, 85, // Opcode: STXVRWX +/* 10131 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 10147 +/* 10136 */ MCD_OPC_CheckField, 1, 1, 1, 213, 44, 0, // Skip to: 21620 +/* 10143 */ MCD_OPC_Decode, 175, 13, 85, // Opcode: STXVRDX +/* 10147 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 10173 +/* 10152 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 10155 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10164 +/* 10160 */ MCD_OPC_Decode, 220, 9, 85, // Opcode: LXVX +/* 10164 */ MCD_OPC_FilterValue, 1, 187, 44, 0, // Skip to: 21620 +/* 10169 */ MCD_OPC_Decode, 210, 9, 86, // Opcode: LXVL +/* 10173 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 10189 +/* 10178 */ MCD_OPC_CheckField, 1, 1, 1, 171, 44, 0, // Skip to: 21620 +/* 10185 */ MCD_OPC_Decode, 211, 9, 86, // Opcode: LXVLL +/* 10189 */ MCD_OPC_FilterValue, 10, 28, 0, 0, // Skip to: 10222 +/* 10194 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 10197 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10206 +/* 10202 */ MCD_OPC_Decode, 208, 9, 85, // Opcode: LXVDSX +/* 10206 */ MCD_OPC_FilterValue, 1, 145, 44, 0, // Skip to: 21620 +/* 10211 */ MCD_OPC_CheckField, 0, 1, 0, 138, 44, 0, // Skip to: 21620 +/* 10218 */ MCD_OPC_Decode, 213, 9, 87, // Opcode: LXVPX +/* 10222 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 10238 +/* 10227 */ MCD_OPC_CheckField, 1, 1, 0, 122, 44, 0, // Skip to: 21620 +/* 10234 */ MCD_OPC_Decode, 219, 9, 85, // Opcode: LXVWSX +/* 10238 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 10264 +/* 10243 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 10246 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10255 +/* 10251 */ MCD_OPC_Decode, 179, 13, 85, // Opcode: STXVX +/* 10255 */ MCD_OPC_FilterValue, 1, 96, 44, 0, // Skip to: 21620 +/* 10260 */ MCD_OPC_Decode, 170, 13, 86, // Opcode: STXVL +/* 10264 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 10280 +/* 10269 */ MCD_OPC_CheckField, 1, 1, 1, 80, 44, 0, // Skip to: 21620 +/* 10276 */ MCD_OPC_Decode, 171, 13, 86, // Opcode: STXVLL +/* 10280 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 10296 +/* 10285 */ MCD_OPC_CheckField, 0, 2, 2, 64, 44, 0, // Skip to: 21620 +/* 10292 */ MCD_OPC_Decode, 173, 13, 87, // Opcode: STXVPX +/* 10296 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 10312 +/* 10301 */ MCD_OPC_CheckField, 1, 1, 0, 48, 44, 0, // Skip to: 21620 +/* 10308 */ MCD_OPC_Decode, 204, 9, 88, // Opcode: LXSSPX +/* 10312 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 10328 +/* 10317 */ MCD_OPC_CheckField, 1, 1, 0, 32, 44, 0, // Skip to: 21620 +/* 10324 */ MCD_OPC_Decode, 198, 9, 84, // Opcode: LXSDX +/* 10328 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 10344 +/* 10333 */ MCD_OPC_CheckField, 1, 1, 0, 16, 44, 0, // Skip to: 21620 +/* 10340 */ MCD_OPC_Decode, 165, 13, 88, // Opcode: STXSSPX +/* 10344 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 10360 +/* 10349 */ MCD_OPC_CheckField, 1, 1, 0, 0, 44, 0, // Skip to: 21620 +/* 10356 */ MCD_OPC_Decode, 158, 13, 84, // Opcode: STXSDX +/* 10360 */ MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 10386 +/* 10365 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 10368 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10377 +/* 10373 */ MCD_OPC_Decode, 218, 9, 85, // Opcode: LXVW4X +/* 10377 */ MCD_OPC_FilterValue, 1, 230, 43, 0, // Skip to: 21620 +/* 10382 */ MCD_OPC_Decode, 199, 9, 84, // Opcode: LXSIBZX +/* 10386 */ MCD_OPC_FilterValue, 25, 21, 0, 0, // Skip to: 10412 +/* 10391 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 10394 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10403 +/* 10399 */ MCD_OPC_Decode, 209, 9, 85, // Opcode: LXVH8X +/* 10403 */ MCD_OPC_FilterValue, 1, 204, 43, 0, // Skip to: 21620 +/* 10408 */ MCD_OPC_Decode, 200, 9, 84, // Opcode: LXSIHZX +/* 10412 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 10428 +/* 10417 */ MCD_OPC_CheckField, 1, 1, 0, 188, 43, 0, // Skip to: 21620 +/* 10424 */ MCD_OPC_Decode, 207, 9, 85, // Opcode: LXVD2X +/* 10428 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 10444 +/* 10433 */ MCD_OPC_CheckField, 1, 1, 0, 172, 43, 0, // Skip to: 21620 +/* 10440 */ MCD_OPC_Decode, 206, 9, 85, // Opcode: LXVB16X +/* 10444 */ MCD_OPC_FilterValue, 28, 21, 0, 0, // Skip to: 10470 +/* 10449 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 10452 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10461 +/* 10457 */ MCD_OPC_Decode, 178, 13, 85, // Opcode: STXVW4X +/* 10461 */ MCD_OPC_FilterValue, 1, 146, 43, 0, // Skip to: 21620 +/* 10466 */ MCD_OPC_Decode, 159, 13, 84, // Opcode: STXSIBX +/* 10470 */ MCD_OPC_FilterValue, 29, 21, 0, 0, // Skip to: 10496 +/* 10475 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 10478 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10487 +/* 10483 */ MCD_OPC_Decode, 169, 13, 85, // Opcode: STXVH8X +/* 10487 */ MCD_OPC_FilterValue, 1, 120, 43, 0, // Skip to: 21620 +/* 10492 */ MCD_OPC_Decode, 161, 13, 84, // Opcode: STXSIHX +/* 10496 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 10512 +/* 10501 */ MCD_OPC_CheckField, 1, 1, 0, 104, 43, 0, // Skip to: 21620 +/* 10508 */ MCD_OPC_Decode, 168, 13, 85, // Opcode: STXVD2X +/* 10512 */ MCD_OPC_FilterValue, 31, 95, 43, 0, // Skip to: 21620 +/* 10517 */ MCD_OPC_CheckField, 1, 1, 0, 88, 43, 0, // Skip to: 21620 +/* 10524 */ MCD_OPC_Decode, 167, 13, 85, // Opcode: STXVB16X +/* 10528 */ MCD_OPC_FilterValue, 7, 247, 0, 0, // Skip to: 10780 +/* 10533 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 10536 */ MCD_OPC_FilterValue, 0, 62, 0, 0, // Skip to: 10603 +/* 10541 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 10544 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 10553 +/* 10549 */ MCD_OPC_Decode, 229, 9, 89, // Opcode: MFBHRBE +/* 10553 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 10562 +/* 10558 */ MCD_OPC_Decode, 248, 9, 71, // Opcode: MFPMR +/* 10562 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 10578 +/* 10567 */ MCD_OPC_CheckField, 11, 15, 0, 38, 43, 0, // Skip to: 21620 +/* 10574 */ MCD_OPC_Decode, 202, 4, 0, // Opcode: CLRBHRB +/* 10578 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 10587 +/* 10583 */ MCD_OPC_Decode, 162, 10, 90, // Opcode: MTPMR +/* 10587 */ MCD_OPC_FilterValue, 22, 20, 43, 0, // Skip to: 21620 +/* 10592 */ MCD_OPC_CheckField, 11, 12, 0, 13, 43, 0, // Skip to: 21620 +/* 10599 */ MCD_OPC_Decode, 236, 13, 68, // Opcode: TCHECK +/* 10603 */ MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 10771 +/* 10608 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 10611 */ MCD_OPC_FilterValue, 20, 18, 0, 0, // Skip to: 10634 +/* 10616 */ MCD_OPC_CheckField, 22, 4, 0, 245, 42, 0, // Skip to: 21620 +/* 10623 */ MCD_OPC_CheckField, 11, 10, 0, 238, 42, 0, // Skip to: 21620 +/* 10630 */ MCD_OPC_Decode, 234, 13, 91, // Opcode: TBEGIN +/* 10634 */ MCD_OPC_FilterValue, 21, 11, 0, 0, // Skip to: 10650 +/* 10639 */ MCD_OPC_CheckField, 11, 14, 0, 222, 42, 0, // Skip to: 21620 +/* 10646 */ MCD_OPC_Decode, 246, 13, 92, // Opcode: TEND +/* 10650 */ MCD_OPC_FilterValue, 23, 18, 0, 0, // Skip to: 10673 +/* 10655 */ MCD_OPC_CheckField, 22, 3, 0, 206, 42, 0, // Skip to: 21620 +/* 10662 */ MCD_OPC_CheckField, 11, 10, 0, 199, 42, 0, // Skip to: 21620 +/* 10669 */ MCD_OPC_Decode, 138, 14, 91, // Opcode: TSR +/* 10673 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 10682 +/* 10678 */ MCD_OPC_Decode, 226, 13, 72, // Opcode: TABORTWC +/* 10682 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 10691 +/* 10687 */ MCD_OPC_Decode, 224, 13, 72, // Opcode: TABORTDC +/* 10691 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 10700 +/* 10696 */ MCD_OPC_Decode, 227, 13, 93, // Opcode: TABORTWCI +/* 10700 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 10709 +/* 10705 */ MCD_OPC_Decode, 225, 13, 93, // Opcode: TABORTDCI +/* 10709 */ MCD_OPC_FilterValue, 28, 18, 0, 0, // Skip to: 10732 +/* 10714 */ MCD_OPC_CheckField, 21, 5, 0, 147, 42, 0, // Skip to: 21620 +/* 10721 */ MCD_OPC_CheckField, 11, 5, 0, 140, 42, 0, // Skip to: 21620 +/* 10728 */ MCD_OPC_Decode, 223, 13, 94, // Opcode: TABORT +/* 10732 */ MCD_OPC_FilterValue, 29, 18, 0, 0, // Skip to: 10755 +/* 10737 */ MCD_OPC_CheckField, 21, 5, 0, 124, 42, 0, // Skip to: 21620 +/* 10744 */ MCD_OPC_CheckField, 11, 5, 0, 117, 42, 0, // Skip to: 21620 +/* 10751 */ MCD_OPC_Decode, 137, 14, 94, // Opcode: TRECLAIM +/* 10755 */ MCD_OPC_FilterValue, 31, 108, 42, 0, // Skip to: 21620 +/* 10760 */ MCD_OPC_CheckField, 11, 15, 0, 101, 42, 0, // Skip to: 21620 +/* 10767 */ MCD_OPC_Decode, 136, 14, 0, // Opcode: TRECHKPT +/* 10771 */ MCD_OPC_FilterValue, 2, 92, 42, 0, // Skip to: 21620 +/* 10776 */ MCD_OPC_Decode, 209, 8, 95, // Opcode: ISEL +/* 10780 */ MCD_OPC_FilterValue, 8, 80, 0, 0, // Skip to: 10865 +/* 10785 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 10788 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 10828 +/* 10793 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10796 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 10812 +/* 10801 */ MCD_OPC_CheckField, 6, 6, 4, 60, 42, 0, // Skip to: 21620 +/* 10808 */ MCD_OPC_Decode, 141, 10, 96, // Opcode: MTCRF +/* 10812 */ MCD_OPC_FilterValue, 1, 51, 42, 0, // Skip to: 21620 +/* 10817 */ MCD_OPC_CheckField, 6, 6, 4, 44, 42, 0, // Skip to: 21620 +/* 10824 */ MCD_OPC_Decode, 160, 10, 97, // Opcode: MTOCRF +/* 10828 */ MCD_OPC_FilterValue, 2, 35, 42, 0, // Skip to: 21620 +/* 10833 */ MCD_OPC_ExtractField, 6, 17, // Inst{22-6} ... +/* 10836 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 10845 +/* 10841 */ MCD_OPC_Decode, 183, 19, 98, // Opcode: XXMFACC +/* 10845 */ MCD_OPC_FilterValue, 133, 8, 4, 0, 0, // Skip to: 10855 +/* 10851 */ MCD_OPC_Decode, 186, 19, 98, // Opcode: XXMTACC +/* 10855 */ MCD_OPC_FilterValue, 133, 24, 7, 42, 0, // Skip to: 21620 +/* 10861 */ MCD_OPC_Decode, 193, 19, 99, // Opcode: XXSETACCZ +/* 10865 */ MCD_OPC_FilterValue, 9, 124, 3, 0, // Skip to: 11762 +/* 10870 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 10873 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 10927 +/* 10878 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10881 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 10904 +/* 10886 */ MCD_OPC_CheckField, 11, 9, 0, 231, 41, 0, // Skip to: 21620 +/* 10893 */ MCD_OPC_CheckField, 0, 2, 2, 224, 41, 0, // Skip to: 21620 +/* 10900 */ MCD_OPC_Decode, 230, 9, 69, // Opcode: MFCR +/* 10904 */ MCD_OPC_FilterValue, 1, 215, 41, 0, // Skip to: 21620 +/* 10909 */ MCD_OPC_CheckField, 11, 1, 0, 208, 41, 0, // Skip to: 21620 +/* 10916 */ MCD_OPC_CheckField, 0, 2, 2, 201, 41, 0, // Skip to: 21620 +/* 10923 */ MCD_OPC_Decode, 246, 9, 100, // Opcode: MFOCRF +/* 10927 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 10950 +/* 10932 */ MCD_OPC_CheckField, 11, 5, 0, 185, 41, 0, // Skip to: 21620 +/* 10939 */ MCD_OPC_CheckField, 1, 1, 1, 178, 41, 0, // Skip to: 21620 +/* 10946 */ MCD_OPC_Decode, 132, 10, 101, // Opcode: MFVSRD +/* 10950 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 10973 +/* 10955 */ MCD_OPC_CheckField, 11, 10, 0, 162, 41, 0, // Skip to: 21620 +/* 10962 */ MCD_OPC_CheckField, 0, 2, 2, 155, 41, 0, // Skip to: 21620 +/* 10969 */ MCD_OPC_Decode, 245, 9, 69, // Opcode: MFMSR +/* 10973 */ MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 10996 +/* 10978 */ MCD_OPC_CheckField, 11, 5, 0, 139, 41, 0, // Skip to: 21620 +/* 10985 */ MCD_OPC_CheckField, 1, 1, 1, 132, 41, 0, // Skip to: 21620 +/* 10992 */ MCD_OPC_Decode, 134, 10, 102, // Opcode: MFVSRWZ +/* 10996 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 11012 +/* 11001 */ MCD_OPC_CheckField, 1, 1, 0, 116, 41, 0, // Skip to: 21620 +/* 11008 */ MCD_OPC_Decode, 158, 10, 103, // Opcode: MTMSR +/* 11012 */ MCD_OPC_FilterValue, 5, 28, 0, 0, // Skip to: 11045 +/* 11017 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 11020 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11029 +/* 11025 */ MCD_OPC_Decode, 159, 10, 103, // Opcode: MTMSRD +/* 11029 */ MCD_OPC_FilterValue, 1, 90, 41, 0, // Skip to: 21620 +/* 11034 */ MCD_OPC_CheckField, 11, 5, 0, 83, 41, 0, // Skip to: 21620 +/* 11041 */ MCD_OPC_Decode, 175, 10, 104, // Opcode: MTVSRD +/* 11045 */ MCD_OPC_FilterValue, 6, 28, 0, 0, // Skip to: 11078 +/* 11050 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 11053 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11062 +/* 11058 */ MCD_OPC_Decode, 165, 10, 105, // Opcode: MTSR +/* 11062 */ MCD_OPC_FilterValue, 1, 57, 41, 0, // Skip to: 21620 +/* 11067 */ MCD_OPC_CheckField, 11, 5, 0, 50, 41, 0, // Skip to: 21620 +/* 11074 */ MCD_OPC_Decode, 180, 10, 106, // Opcode: MTVSRWA +/* 11078 */ MCD_OPC_FilterValue, 7, 28, 0, 0, // Skip to: 11111 +/* 11083 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 11086 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11095 +/* 11091 */ MCD_OPC_Decode, 166, 10, 107, // Opcode: MTSRIN +/* 11095 */ MCD_OPC_FilterValue, 1, 24, 41, 0, // Skip to: 21620 +/* 11100 */ MCD_OPC_CheckField, 11, 5, 0, 17, 41, 0, // Skip to: 21620 +/* 11107 */ MCD_OPC_Decode, 183, 10, 106, // Opcode: MTVSRWZ +/* 11111 */ MCD_OPC_FilterValue, 8, 18, 0, 0, // Skip to: 11134 +/* 11116 */ MCD_OPC_CheckField, 16, 10, 0, 1, 41, 0, // Skip to: 21620 +/* 11123 */ MCD_OPC_CheckField, 0, 2, 0, 250, 40, 0, // Skip to: 21620 +/* 11130 */ MCD_OPC_Decode, 249, 13, 108, // Opcode: TLBIEL +/* 11134 */ MCD_OPC_FilterValue, 9, 42, 0, 0, // Skip to: 11181 +/* 11139 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 11142 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 11165 +/* 11147 */ MCD_OPC_CheckField, 16, 5, 0, 226, 40, 0, // Skip to: 21620 +/* 11154 */ MCD_OPC_CheckField, 0, 1, 0, 219, 40, 0, // Skip to: 21620 +/* 11161 */ MCD_OPC_Decode, 248, 13, 107, // Opcode: TLBIE +/* 11165 */ MCD_OPC_FilterValue, 1, 210, 40, 0, // Skip to: 21620 +/* 11170 */ MCD_OPC_CheckField, 11, 5, 0, 203, 40, 0, // Skip to: 21620 +/* 11177 */ MCD_OPC_Decode, 133, 10, 109, // Opcode: MFVSRLD +/* 11181 */ MCD_OPC_FilterValue, 10, 51, 0, 0, // Skip to: 11237 +/* 11186 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11189 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 11205 +/* 11194 */ MCD_OPC_CheckField, 11, 15, 0, 179, 40, 0, // Skip to: 21620 +/* 11201 */ MCD_OPC_Decode, 177, 12, 0, // Opcode: SLBSYNC +/* 11205 */ MCD_OPC_FilterValue, 2, 170, 40, 0, // Skip to: 21620 +/* 11210 */ MCD_OPC_ExtractField, 11, 10, // Inst{20-11} ... +/* 11213 */ MCD_OPC_FilterValue, 128, 2, 4, 0, 0, // Skip to: 11223 +/* 11219 */ MCD_OPC_Decode, 243, 9, 69, // Opcode: MFLR +/* 11223 */ MCD_OPC_FilterValue, 160, 2, 4, 0, 0, // Skip to: 11233 +/* 11229 */ MCD_OPC_Decode, 232, 9, 69, // Opcode: MFCTR +/* 11233 */ MCD_OPC_Decode, 249, 9, 71, // Opcode: MFSPR +/* 11237 */ MCD_OPC_FilterValue, 11, 28, 0, 0, // Skip to: 11270 +/* 11242 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11245 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 11261 +/* 11250 */ MCD_OPC_CheckField, 11, 15, 0, 123, 40, 0, // Skip to: 21620 +/* 11257 */ MCD_OPC_Decode, 247, 13, 0, // Opcode: TLBIA +/* 11261 */ MCD_OPC_FilterValue, 2, 114, 40, 0, // Skip to: 21620 +/* 11266 */ MCD_OPC_Decode, 253, 9, 71, // Opcode: MFTB +/* 11270 */ MCD_OPC_FilterValue, 12, 42, 0, 0, // Skip to: 11317 +/* 11275 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 11278 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 11301 +/* 11283 */ MCD_OPC_CheckField, 16, 5, 0, 90, 40, 0, // Skip to: 21620 +/* 11290 */ MCD_OPC_CheckField, 0, 1, 0, 83, 40, 0, // Skip to: 21620 +/* 11297 */ MCD_OPC_Decode, 176, 12, 107, // Opcode: SLBMTE +/* 11301 */ MCD_OPC_FilterValue, 1, 74, 40, 0, // Skip to: 21620 +/* 11306 */ MCD_OPC_CheckField, 11, 5, 0, 67, 40, 0, // Skip to: 21620 +/* 11313 */ MCD_OPC_Decode, 182, 10, 110, // Opcode: MTVSRWS +/* 11317 */ MCD_OPC_FilterValue, 13, 35, 0, 0, // Skip to: 11357 +/* 11322 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 11325 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 11348 +/* 11330 */ MCD_OPC_CheckField, 16, 10, 0, 43, 40, 0, // Skip to: 21620 +/* 11337 */ MCD_OPC_CheckField, 0, 1, 0, 36, 40, 0, // Skip to: 21620 +/* 11344 */ MCD_OPC_Decode, 172, 12, 108, // Opcode: SLBIE +/* 11348 */ MCD_OPC_FilterValue, 1, 27, 40, 0, // Skip to: 21620 +/* 11353 */ MCD_OPC_Decode, 176, 10, 111, // Opcode: MTVSRDD +/* 11357 */ MCD_OPC_FilterValue, 14, 51, 0, 0, // Skip to: 11413 +/* 11362 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11365 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 11381 +/* 11370 */ MCD_OPC_CheckField, 16, 5, 0, 3, 40, 0, // Skip to: 21620 +/* 11377 */ MCD_OPC_Decode, 173, 12, 107, // Opcode: SLBIEG +/* 11381 */ MCD_OPC_FilterValue, 2, 250, 39, 0, // Skip to: 21620 +/* 11386 */ MCD_OPC_ExtractField, 11, 10, // Inst{20-11} ... +/* 11389 */ MCD_OPC_FilterValue, 128, 2, 4, 0, 0, // Skip to: 11399 +/* 11395 */ MCD_OPC_Decode, 156, 10, 69, // Opcode: MTLR +/* 11399 */ MCD_OPC_FilterValue, 160, 2, 4, 0, 0, // Skip to: 11409 +/* 11405 */ MCD_OPC_Decode, 143, 10, 69, // Opcode: MTCTR +/* 11409 */ MCD_OPC_Decode, 163, 10, 90, // Opcode: MTSPR +/* 11413 */ MCD_OPC_FilterValue, 15, 18, 0, 0, // Skip to: 11436 +/* 11418 */ MCD_OPC_CheckField, 11, 15, 0, 211, 39, 0, // Skip to: 21620 +/* 11425 */ MCD_OPC_CheckField, 0, 2, 0, 204, 39, 0, // Skip to: 21620 +/* 11432 */ MCD_OPC_Decode, 171, 12, 0, // Opcode: SLBIA +/* 11436 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 11452 +/* 11441 */ MCD_OPC_CheckField, 1, 1, 1, 188, 39, 0, // Skip to: 21620 +/* 11448 */ MCD_OPC_Decode, 251, 9, 105, // Opcode: MFSR +/* 11452 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 11478 +/* 11457 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 11460 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11469 +/* 11465 */ MCD_OPC_Decode, 200, 8, 112, // Opcode: HASHSTP +/* 11469 */ MCD_OPC_FilterValue, 1, 162, 39, 0, // Skip to: 21620 +/* 11474 */ MCD_OPC_Decode, 252, 9, 107, // Opcode: MFSRIN +/* 11478 */ MCD_OPC_FilterValue, 21, 11, 0, 0, // Skip to: 11494 +/* 11483 */ MCD_OPC_CheckField, 1, 1, 0, 146, 39, 0, // Skip to: 21620 +/* 11490 */ MCD_OPC_Decode, 198, 8, 112, // Opcode: HASHCHKP +/* 11494 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 11510 +/* 11499 */ MCD_OPC_CheckField, 1, 1, 0, 130, 39, 0, // Skip to: 21620 +/* 11506 */ MCD_OPC_Decode, 199, 8, 112, // Opcode: HASHST +/* 11510 */ MCD_OPC_FilterValue, 23, 42, 0, 0, // Skip to: 11557 +/* 11515 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 11518 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11527 +/* 11523 */ MCD_OPC_Decode, 197, 8, 112, // Opcode: HASHCHK +/* 11527 */ MCD_OPC_FilterValue, 1, 104, 39, 0, // Skip to: 21620 +/* 11532 */ MCD_OPC_CheckField, 18, 3, 0, 97, 39, 0, // Skip to: 21620 +/* 11539 */ MCD_OPC_CheckField, 11, 5, 0, 90, 39, 0, // Skip to: 21620 +/* 11546 */ MCD_OPC_CheckField, 0, 1, 0, 83, 39, 0, // Skip to: 21620 +/* 11553 */ MCD_OPC_Decode, 248, 4, 113, // Opcode: DARN +/* 11557 */ MCD_OPC_FilterValue, 24, 18, 0, 0, // Skip to: 11580 +/* 11562 */ MCD_OPC_CheckField, 21, 5, 0, 67, 39, 0, // Skip to: 21620 +/* 11569 */ MCD_OPC_CheckField, 0, 2, 0, 60, 39, 0, // Skip to: 21620 +/* 11576 */ MCD_OPC_Decode, 250, 13, 76, // Opcode: TLBIVAX +/* 11580 */ MCD_OPC_FilterValue, 26, 18, 0, 0, // Skip to: 11603 +/* 11585 */ MCD_OPC_CheckField, 16, 5, 0, 44, 39, 0, // Skip to: 21620 +/* 11592 */ MCD_OPC_CheckField, 0, 2, 2, 37, 39, 0, // Skip to: 21620 +/* 11599 */ MCD_OPC_Decode, 175, 12, 107, // Opcode: SLBMFEV +/* 11603 */ MCD_OPC_FilterValue, 28, 48, 0, 0, // Skip to: 11656 +/* 11608 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11611 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 11631 +/* 11616 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 11627 +/* 11623 */ MCD_OPC_Decode, 255, 13, 76, // Opcode: TLBSX +/* 11627 */ MCD_OPC_Decode, 128, 14, 80, // Opcode: TLBSX2 +/* 11631 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 11640 +/* 11636 */ MCD_OPC_Decode, 129, 14, 80, // Opcode: TLBSX2D +/* 11640 */ MCD_OPC_FilterValue, 2, 247, 38, 0, // Skip to: 21620 +/* 11645 */ MCD_OPC_CheckField, 16, 5, 0, 240, 38, 0, // Skip to: 21620 +/* 11652 */ MCD_OPC_Decode, 174, 12, 107, // Opcode: SLBMFEE +/* 11656 */ MCD_OPC_FilterValue, 29, 23, 0, 0, // Skip to: 11684 +/* 11661 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11664 */ MCD_OPC_FilterValue, 0, 223, 38, 0, // Skip to: 21620 +/* 11669 */ MCD_OPC_CheckField, 11, 15, 0, 4, 0, 0, // Skip to: 11680 +/* 11676 */ MCD_OPC_Decode, 253, 13, 0, // Opcode: TLBRE +/* 11680 */ MCD_OPC_Decode, 254, 13, 114, // Opcode: TLBRE2 +/* 11684 */ MCD_OPC_FilterValue, 30, 50, 0, 0, // Skip to: 11739 +/* 11689 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11692 */ MCD_OPC_FilterValue, 0, 26, 0, 0, // Skip to: 11723 +/* 11697 */ MCD_OPC_CheckField, 11, 15, 0, 4, 0, 0, // Skip to: 11708 +/* 11704 */ MCD_OPC_Decode, 131, 14, 0, // Opcode: TLBWE +/* 11708 */ MCD_OPC_CheckField, 16, 10, 0, 4, 0, 0, // Skip to: 11719 +/* 11715 */ MCD_OPC_Decode, 251, 13, 108, // Opcode: TLBLD +/* 11719 */ MCD_OPC_Decode, 132, 14, 114, // Opcode: TLBWE2 +/* 11723 */ MCD_OPC_FilterValue, 3, 164, 38, 0, // Skip to: 21620 +/* 11728 */ MCD_OPC_CheckField, 16, 5, 0, 157, 38, 0, // Skip to: 21620 +/* 11735 */ MCD_OPC_Decode, 170, 12, 107, // Opcode: SLBFEE_rec +/* 11739 */ MCD_OPC_FilterValue, 31, 148, 38, 0, // Skip to: 21620 +/* 11744 */ MCD_OPC_CheckField, 16, 10, 0, 141, 38, 0, // Skip to: 21620 +/* 11751 */ MCD_OPC_CheckField, 0, 2, 0, 134, 38, 0, // Skip to: 21620 +/* 11758 */ MCD_OPC_Decode, 252, 13, 108, // Opcode: TLBLI +/* 11762 */ MCD_OPC_FilterValue, 10, 167, 1, 0, // Skip to: 12190 +/* 11767 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 11770 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 11805 +/* 11775 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11778 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11787 +/* 11783 */ MCD_OPC_Decode, 173, 9, 115, // Opcode: LWARX +/* 11787 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 11796 +/* 11792 */ MCD_OPC_Decode, 174, 9, 115, // Opcode: LWARXL +/* 11796 */ MCD_OPC_FilterValue, 2, 91, 38, 0, // Skip to: 21620 +/* 11801 */ MCD_OPC_Decode, 237, 8, 116, // Opcode: LDX +/* 11805 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 11840 +/* 11810 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11813 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11822 +/* 11818 */ MCD_OPC_Decode, 213, 8, 115, // Opcode: LBARX +/* 11822 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 11831 +/* 11827 */ MCD_OPC_Decode, 214, 8, 115, // Opcode: LBARXL +/* 11831 */ MCD_OPC_FilterValue, 2, 56, 38, 0, // Skip to: 21620 +/* 11836 */ MCD_OPC_Decode, 236, 8, 117, // Opcode: LDUX +/* 11840 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 11866 +/* 11845 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11848 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11857 +/* 11853 */ MCD_OPC_Decode, 229, 8, 116, // Opcode: LDARX +/* 11857 */ MCD_OPC_FilterValue, 1, 30, 38, 0, // Skip to: 21620 +/* 11862 */ MCD_OPC_Decode, 230, 8, 116, // Opcode: LDARXL +/* 11866 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 11892 +/* 11871 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11874 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11883 +/* 11879 */ MCD_OPC_Decode, 132, 9, 115, // Opcode: LHARX +/* 11883 */ MCD_OPC_FilterValue, 1, 4, 38, 0, // Skip to: 21620 +/* 11888 */ MCD_OPC_Decode, 133, 9, 115, // Opcode: LHARXL +/* 11892 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 11908 +/* 11897 */ MCD_OPC_CheckField, 0, 2, 2, 244, 37, 0, // Skip to: 21620 +/* 11904 */ MCD_OPC_Decode, 230, 12, 116, // Opcode: STDX +/* 11908 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 11924 +/* 11913 */ MCD_OPC_CheckField, 0, 2, 2, 228, 37, 0, // Skip to: 21620 +/* 11920 */ MCD_OPC_Decode, 229, 12, 118, // Opcode: STDUX +/* 11924 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 11950 +/* 11929 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 11932 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11941 +/* 11937 */ MCD_OPC_Decode, 161, 9, 119, // Opcode: LQARX +/* 11941 */ MCD_OPC_FilterValue, 1, 202, 37, 0, // Skip to: 21620 +/* 11946 */ MCD_OPC_Decode, 162, 9, 119, // Opcode: LQARXL +/* 11950 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 11966 +/* 11955 */ MCD_OPC_CheckField, 0, 2, 2, 186, 37, 0, // Skip to: 21620 +/* 11962 */ MCD_OPC_Decode, 234, 8, 116, // Opcode: LDMX +/* 11966 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 11982 +/* 11971 */ MCD_OPC_CheckField, 0, 2, 2, 170, 37, 0, // Skip to: 21620 +/* 11978 */ MCD_OPC_Decode, 177, 9, 116, // Opcode: LWAX +/* 11982 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 11998 +/* 11987 */ MCD_OPC_CheckField, 0, 2, 2, 154, 37, 0, // Skip to: 21620 +/* 11994 */ MCD_OPC_Decode, 176, 9, 117, // Opcode: LWAUX +/* 11998 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 12014 +/* 12003 */ MCD_OPC_CheckField, 0, 2, 0, 138, 37, 0, // Skip to: 21620 +/* 12010 */ MCD_OPC_Decode, 232, 8, 116, // Opcode: LDBRX +/* 12014 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 12030 +/* 12019 */ MCD_OPC_CheckField, 0, 2, 2, 122, 37, 0, // Skip to: 21620 +/* 12026 */ MCD_OPC_Decode, 164, 9, 77, // Opcode: LSWI +/* 12030 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 12046 +/* 12035 */ MCD_OPC_CheckField, 0, 2, 0, 106, 37, 0, // Skip to: 21620 +/* 12042 */ MCD_OPC_Decode, 225, 12, 116, // Opcode: STDBRX +/* 12046 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 12062 +/* 12051 */ MCD_OPC_CheckField, 0, 2, 2, 90, 37, 0, // Skip to: 21620 +/* 12058 */ MCD_OPC_Decode, 135, 13, 77, // Opcode: STSWI +/* 12062 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 12078 +/* 12067 */ MCD_OPC_CheckField, 0, 2, 2, 74, 37, 0, // Skip to: 21620 +/* 12074 */ MCD_OPC_Decode, 185, 9, 80, // Opcode: LWZCIX +/* 12078 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 12094 +/* 12083 */ MCD_OPC_CheckField, 0, 2, 2, 58, 37, 0, // Skip to: 21620 +/* 12090 */ MCD_OPC_Decode, 145, 9, 80, // Opcode: LHZCIX +/* 12094 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 12110 +/* 12099 */ MCD_OPC_CheckField, 0, 2, 2, 42, 37, 0, // Skip to: 21620 +/* 12106 */ MCD_OPC_Decode, 218, 8, 80, // Opcode: LBZCIX +/* 12110 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 12126 +/* 12115 */ MCD_OPC_CheckField, 0, 2, 2, 26, 37, 0, // Skip to: 21620 +/* 12122 */ MCD_OPC_Decode, 233, 8, 80, // Opcode: LDCIX +/* 12126 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 12142 +/* 12131 */ MCD_OPC_CheckField, 0, 2, 2, 10, 37, 0, // Skip to: 21620 +/* 12138 */ MCD_OPC_Decode, 145, 13, 80, // Opcode: STWCIX +/* 12142 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 12158 +/* 12147 */ MCD_OPC_CheckField, 0, 2, 2, 250, 36, 0, // Skip to: 21620 +/* 12154 */ MCD_OPC_Decode, 246, 12, 80, // Opcode: STHCIX +/* 12158 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 12174 +/* 12163 */ MCD_OPC_CheckField, 0, 2, 2, 234, 36, 0, // Skip to: 21620 +/* 12170 */ MCD_OPC_Decode, 211, 12, 80, // Opcode: STBCIX +/* 12174 */ MCD_OPC_FilterValue, 31, 225, 36, 0, // Skip to: 21620 +/* 12179 */ MCD_OPC_CheckField, 0, 2, 2, 218, 36, 0, // Skip to: 21620 +/* 12186 */ MCD_OPC_Decode, 226, 12, 80, // Opcode: STDCIX +/* 12190 */ MCD_OPC_FilterValue, 11, 110, 3, 0, // Skip to: 13073 +/* 12195 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 12198 */ MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 12231 +/* 12203 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12206 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 12222 +/* 12211 */ MCD_OPC_CheckField, 25, 1, 0, 186, 36, 0, // Skip to: 21620 +/* 12218 */ MCD_OPC_Decode, 206, 8, 75, // Opcode: ICBT +/* 12222 */ MCD_OPC_FilterValue, 2, 177, 36, 0, // Skip to: 21620 +/* 12227 */ MCD_OPC_Decode, 190, 9, 115, // Opcode: LWZX +/* 12231 */ MCD_OPC_FilterValue, 1, 28, 0, 0, // Skip to: 12264 +/* 12236 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12239 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 12255 +/* 12244 */ MCD_OPC_CheckField, 21, 5, 0, 153, 36, 0, // Skip to: 21620 +/* 12251 */ MCD_OPC_Decode, 253, 4, 120, // Opcode: DCBST +/* 12255 */ MCD_OPC_FilterValue, 2, 144, 36, 0, // Skip to: 21620 +/* 12260 */ MCD_OPC_Decode, 188, 9, 121, // Opcode: LWZUX +/* 12264 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 12290 +/* 12269 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12272 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12281 +/* 12277 */ MCD_OPC_Decode, 250, 4, 122, // Opcode: DCBF +/* 12281 */ MCD_OPC_FilterValue, 2, 118, 36, 0, // Skip to: 21620 +/* 12286 */ MCD_OPC_Decode, 223, 8, 115, // Opcode: LBZX +/* 12290 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 12306 +/* 12295 */ MCD_OPC_CheckField, 0, 2, 2, 102, 36, 0, // Skip to: 21620 +/* 12302 */ MCD_OPC_Decode, 221, 8, 121, // Opcode: LBZUX +/* 12306 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 12332 +/* 12311 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12314 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 12323 +/* 12319 */ MCD_OPC_Decode, 146, 13, 115, // Opcode: STWCX +/* 12323 */ MCD_OPC_FilterValue, 2, 76, 36, 0, // Skip to: 21620 +/* 12328 */ MCD_OPC_Decode, 152, 13, 115, // Opcode: STWX +/* 12332 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 12358 +/* 12337 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12340 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 12349 +/* 12345 */ MCD_OPC_Decode, 133, 13, 119, // Opcode: STQCX +/* 12349 */ MCD_OPC_FilterValue, 2, 50, 36, 0, // Skip to: 21620 +/* 12354 */ MCD_OPC_Decode, 150, 13, 123, // Opcode: STWUX +/* 12358 */ MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 12384 +/* 12363 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12366 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 12375 +/* 12371 */ MCD_OPC_Decode, 227, 12, 116, // Opcode: STDCX +/* 12375 */ MCD_OPC_FilterValue, 2, 24, 36, 0, // Skip to: 21620 +/* 12380 */ MCD_OPC_Decode, 218, 12, 115, // Opcode: STBX +/* 12384 */ MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 12410 +/* 12389 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12392 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12401 +/* 12397 */ MCD_OPC_Decode, 129, 5, 124, // Opcode: DCBTST +/* 12401 */ MCD_OPC_FilterValue, 2, 254, 35, 0, // Skip to: 21620 +/* 12406 */ MCD_OPC_Decode, 216, 12, 123, // Opcode: STBUX +/* 12410 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 12436 +/* 12415 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12418 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12427 +/* 12423 */ MCD_OPC_Decode, 255, 4, 124, // Opcode: DCBT +/* 12427 */ MCD_OPC_FilterValue, 2, 228, 35, 0, // Skip to: 21620 +/* 12432 */ MCD_OPC_Decode, 150, 9, 115, // Opcode: LHZX +/* 12436 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 12452 +/* 12441 */ MCD_OPC_CheckField, 0, 2, 2, 212, 35, 0, // Skip to: 21620 +/* 12448 */ MCD_OPC_Decode, 148, 9, 121, // Opcode: LHZUX +/* 12452 */ MCD_OPC_FilterValue, 10, 38, 0, 0, // Skip to: 12495 +/* 12457 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12460 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 12486 +/* 12465 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 12468 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12477 +/* 12473 */ MCD_OPC_Decode, 170, 5, 125, // Opcode: DST +/* 12477 */ MCD_OPC_FilterValue, 4, 178, 35, 0, // Skip to: 21620 +/* 12482 */ MCD_OPC_Decode, 176, 5, 125, // Opcode: DSTT +/* 12486 */ MCD_OPC_FilterValue, 2, 169, 35, 0, // Skip to: 21620 +/* 12491 */ MCD_OPC_Decode, 138, 9, 115, // Opcode: LHAX +/* 12495 */ MCD_OPC_FilterValue, 11, 38, 0, 0, // Skip to: 12538 +/* 12500 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12503 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 12529 +/* 12508 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 12511 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12520 +/* 12516 */ MCD_OPC_Decode, 172, 5, 125, // Opcode: DSTST +/* 12520 */ MCD_OPC_FilterValue, 4, 135, 35, 0, // Skip to: 21620 +/* 12525 */ MCD_OPC_Decode, 174, 5, 125, // Opcode: DSTSTT +/* 12529 */ MCD_OPC_FilterValue, 2, 126, 35, 0, // Skip to: 21620 +/* 12534 */ MCD_OPC_Decode, 136, 9, 121, // Opcode: LHAUX +/* 12538 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 12554 +/* 12543 */ MCD_OPC_CheckField, 0, 2, 2, 110, 35, 0, // Skip to: 21620 +/* 12550 */ MCD_OPC_Decode, 253, 12, 115, // Opcode: STHX +/* 12554 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 12570 +/* 12559 */ MCD_OPC_CheckField, 0, 2, 2, 94, 35, 0, // Skip to: 21620 +/* 12566 */ MCD_OPC_Decode, 251, 12, 123, // Opcode: STHUX +/* 12570 */ MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 12593 +/* 12575 */ MCD_OPC_CheckField, 21, 5, 0, 78, 35, 0, // Skip to: 21620 +/* 12582 */ MCD_OPC_CheckField, 0, 2, 0, 71, 35, 0, // Skip to: 21620 +/* 12589 */ MCD_OPC_Decode, 252, 4, 120, // Opcode: DCBI +/* 12593 */ MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 12619 +/* 12598 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12601 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12610 +/* 12606 */ MCD_OPC_Decode, 180, 9, 115, // Opcode: LWBRX +/* 12610 */ MCD_OPC_FilterValue, 2, 45, 35, 0, // Skip to: 21620 +/* 12615 */ MCD_OPC_Decode, 129, 9, 126, // Opcode: LFSX +/* 12619 */ MCD_OPC_FilterValue, 17, 28, 0, 0, // Skip to: 12652 +/* 12624 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12627 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 12643 +/* 12632 */ MCD_OPC_CheckField, 11, 15, 0, 21, 35, 0, // Skip to: 21620 +/* 12639 */ MCD_OPC_Decode, 130, 14, 0, // Opcode: TLBSYNC +/* 12643 */ MCD_OPC_FilterValue, 2, 12, 35, 0, // Skip to: 21620 +/* 12648 */ MCD_OPC_Decode, 128, 9, 127, // Opcode: LFSUX +/* 12652 */ MCD_OPC_FilterValue, 18, 37, 0, 0, // Skip to: 12694 +/* 12657 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12660 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 12684 +/* 12665 */ MCD_OPC_CheckField, 23, 3, 0, 244, 34, 0, // Skip to: 21620 +/* 12672 */ MCD_OPC_CheckField, 11, 10, 0, 237, 34, 0, // Skip to: 21620 +/* 12679 */ MCD_OPC_Decode, 222, 13, 128, 1, // Opcode: SYNC +/* 12684 */ MCD_OPC_FilterValue, 2, 227, 34, 0, // Skip to: 21620 +/* 12689 */ MCD_OPC_Decode, 251, 8, 129, 1, // Opcode: LFDX +/* 12694 */ MCD_OPC_FilterValue, 19, 12, 0, 0, // Skip to: 12711 +/* 12699 */ MCD_OPC_CheckField, 0, 2, 2, 210, 34, 0, // Skip to: 21620 +/* 12706 */ MCD_OPC_Decode, 250, 8, 130, 1, // Opcode: LFDUX +/* 12711 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 12737 +/* 12716 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12719 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 12728 +/* 12724 */ MCD_OPC_Decode, 144, 13, 115, // Opcode: STWBRX +/* 12728 */ MCD_OPC_FilterValue, 2, 183, 34, 0, // Skip to: 21620 +/* 12733 */ MCD_OPC_Decode, 242, 12, 126, // Opcode: STFSX +/* 12737 */ MCD_OPC_FilterValue, 21, 22, 0, 0, // Skip to: 12764 +/* 12742 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12745 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 12754 +/* 12750 */ MCD_OPC_Decode, 212, 12, 115, // Opcode: STBCX +/* 12754 */ MCD_OPC_FilterValue, 2, 157, 34, 0, // Skip to: 21620 +/* 12759 */ MCD_OPC_Decode, 241, 12, 131, 1, // Opcode: STFSUX +/* 12764 */ MCD_OPC_FilterValue, 22, 22, 0, 0, // Skip to: 12791 +/* 12769 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12772 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 12781 +/* 12777 */ MCD_OPC_Decode, 247, 12, 115, // Opcode: STHCX +/* 12781 */ MCD_OPC_FilterValue, 2, 130, 34, 0, // Skip to: 21620 +/* 12786 */ MCD_OPC_Decode, 237, 12, 129, 1, // Opcode: STFDX +/* 12791 */ MCD_OPC_FilterValue, 23, 29, 0, 0, // Skip to: 12825 +/* 12796 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12799 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 12815 +/* 12804 */ MCD_OPC_CheckField, 21, 5, 0, 105, 34, 0, // Skip to: 21620 +/* 12811 */ MCD_OPC_Decode, 249, 4, 120, // Opcode: DCBA +/* 12815 */ MCD_OPC_FilterValue, 2, 96, 34, 0, // Skip to: 21620 +/* 12820 */ MCD_OPC_Decode, 236, 12, 132, 1, // Opcode: STFDUX +/* 12825 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 12841 +/* 12830 */ MCD_OPC_CheckField, 0, 2, 0, 79, 34, 0, // Skip to: 21620 +/* 12837 */ MCD_OPC_Decode, 140, 9, 115, // Opcode: LHBRX +/* 12841 */ MCD_OPC_FilterValue, 25, 50, 0, 0, // Skip to: 12896 +/* 12846 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 12849 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 12873 +/* 12854 */ MCD_OPC_CheckField, 11, 10, 0, 55, 34, 0, // Skip to: 21620 +/* 12861 */ MCD_OPC_CheckField, 0, 2, 0, 48, 34, 0, // Skip to: 21620 +/* 12868 */ MCD_OPC_Decode, 168, 5, 133, 1, // Opcode: DSS +/* 12873 */ MCD_OPC_FilterValue, 4, 38, 34, 0, // Skip to: 21620 +/* 12878 */ MCD_OPC_CheckField, 11, 12, 0, 31, 34, 0, // Skip to: 21620 +/* 12885 */ MCD_OPC_CheckField, 0, 2, 0, 24, 34, 0, // Skip to: 21620 +/* 12892 */ MCD_OPC_Decode, 169, 5, 0, // Opcode: DSSALL +/* 12896 */ MCD_OPC_FilterValue, 26, 48, 0, 0, // Skip to: 12949 +/* 12901 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 12904 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 12932 +/* 12909 */ MCD_OPC_CheckField, 11, 15, 0, 11, 0, 0, // Skip to: 12927 +/* 12916 */ MCD_OPC_CheckField, 0, 1, 0, 4, 0, 0, // Skip to: 12927 +/* 12923 */ MCD_OPC_Decode, 201, 7, 0, // Opcode: EnforceIEIO +/* 12927 */ MCD_OPC_Decode, 225, 9, 134, 1, // Opcode: MBAR +/* 12932 */ MCD_OPC_FilterValue, 1, 235, 33, 0, // Skip to: 21620 +/* 12937 */ MCD_OPC_CheckField, 0, 1, 0, 228, 33, 0, // Skip to: 21620 +/* 12944 */ MCD_OPC_Decode, 252, 8, 129, 1, // Opcode: LFIWAX +/* 12949 */ MCD_OPC_FilterValue, 27, 29, 0, 0, // Skip to: 12983 +/* 12954 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 12957 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 12973 +/* 12962 */ MCD_OPC_CheckField, 11, 15, 0, 203, 33, 0, // Skip to: 21620 +/* 12969 */ MCD_OPC_Decode, 139, 10, 0, // Opcode: MSGSYNC +/* 12973 */ MCD_OPC_FilterValue, 2, 194, 33, 0, // Skip to: 21620 +/* 12978 */ MCD_OPC_Decode, 253, 8, 129, 1, // Opcode: LFIWZX +/* 12983 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 12999 +/* 12988 */ MCD_OPC_CheckField, 0, 2, 0, 177, 33, 0, // Skip to: 21620 +/* 12995 */ MCD_OPC_Decode, 245, 12, 115, // Opcode: STHBRX +/* 12999 */ MCD_OPC_FilterValue, 30, 29, 0, 0, // Skip to: 13033 +/* 13004 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13007 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 13023 +/* 13012 */ MCD_OPC_CheckField, 21, 5, 0, 153, 33, 0, // Skip to: 21620 +/* 13019 */ MCD_OPC_Decode, 202, 8, 120, // Opcode: ICBI +/* 13023 */ MCD_OPC_FilterValue, 2, 144, 33, 0, // Skip to: 21620 +/* 13028 */ MCD_OPC_Decode, 238, 12, 129, 1, // Opcode: STFIWX +/* 13033 */ MCD_OPC_FilterValue, 31, 134, 33, 0, // Skip to: 21620 +/* 13038 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 13041 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 13057 +/* 13046 */ MCD_OPC_CheckField, 0, 2, 0, 119, 33, 0, // Skip to: 21620 +/* 13053 */ MCD_OPC_Decode, 131, 5, 120, // Opcode: DCBZ +/* 13057 */ MCD_OPC_FilterValue, 1, 110, 33, 0, // Skip to: 21620 +/* 13062 */ MCD_OPC_CheckField, 0, 2, 0, 103, 33, 0, // Skip to: 21620 +/* 13069 */ MCD_OPC_Decode, 133, 5, 120, // Opcode: DCBZL +/* 13073 */ MCD_OPC_FilterValue, 12, 115, 0, 0, // Skip to: 13193 +/* 13078 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 13081 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 13109 +/* 13086 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13089 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13099 +/* 13094 */ MCD_OPC_Decode, 180, 12, 135, 1, // Opcode: SLW +/* 13099 */ MCD_OPC_FilterValue, 1, 68, 33, 0, // Skip to: 21620 +/* 13104 */ MCD_OPC_Decode, 183, 12, 135, 1, // Opcode: SLW_rec +/* 13109 */ MCD_OPC_FilterValue, 16, 23, 0, 0, // Skip to: 13137 +/* 13114 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13117 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13127 +/* 13122 */ MCD_OPC_Decode, 205, 12, 135, 1, // Opcode: SRW +/* 13127 */ MCD_OPC_FilterValue, 1, 40, 33, 0, // Skip to: 21620 +/* 13132 */ MCD_OPC_Decode, 208, 12, 135, 1, // Opcode: SRW_rec +/* 13137 */ MCD_OPC_FilterValue, 24, 23, 0, 0, // Skip to: 13165 +/* 13142 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13145 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13155 +/* 13150 */ MCD_OPC_Decode, 199, 12, 135, 1, // Opcode: SRAW +/* 13155 */ MCD_OPC_FilterValue, 1, 12, 33, 0, // Skip to: 21620 +/* 13160 */ MCD_OPC_Decode, 202, 12, 135, 1, // Opcode: SRAW_rec +/* 13165 */ MCD_OPC_FilterValue, 25, 2, 33, 0, // Skip to: 21620 +/* 13170 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13173 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13183 +/* 13178 */ MCD_OPC_Decode, 200, 12, 136, 1, // Opcode: SRAWI +/* 13183 */ MCD_OPC_FilterValue, 1, 240, 32, 0, // Skip to: 21620 +/* 13188 */ MCD_OPC_Decode, 201, 12, 136, 1, // Opcode: SRAWI_rec +/* 13193 */ MCD_OPC_FilterValue, 13, 1, 2, 0, // Skip to: 13711 +/* 13198 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 13201 */ MCD_OPC_FilterValue, 0, 57, 0, 0, // Skip to: 13263 +/* 13206 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13209 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13226 +/* 13214 */ MCD_OPC_CheckField, 11, 5, 0, 207, 32, 0, // Skip to: 21620 +/* 13221 */ MCD_OPC_Decode, 219, 4, 137, 1, // Opcode: CNTLZW +/* 13226 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 13243 +/* 13231 */ MCD_OPC_CheckField, 11, 5, 0, 190, 32, 0, // Skip to: 21620 +/* 13238 */ MCD_OPC_Decode, 222, 4, 137, 1, // Opcode: CNTLZW_rec +/* 13243 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 13253 +/* 13248 */ MCD_OPC_Decode, 178, 12, 138, 1, // Opcode: SLD +/* 13253 */ MCD_OPC_FilterValue, 3, 170, 32, 0, // Skip to: 21620 +/* 13258 */ MCD_OPC_Decode, 179, 12, 138, 1, // Opcode: SLD_rec +/* 13263 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 13315 +/* 13268 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13271 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13288 +/* 13276 */ MCD_OPC_CheckField, 11, 5, 0, 145, 32, 0, // Skip to: 21620 +/* 13283 */ MCD_OPC_Decode, 216, 4, 139, 1, // Opcode: CNTLZD +/* 13288 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 13305 +/* 13293 */ MCD_OPC_CheckField, 11, 5, 0, 128, 32, 0, // Skip to: 21620 +/* 13300 */ MCD_OPC_Decode, 218, 4, 139, 1, // Opcode: CNTLZD_rec +/* 13305 */ MCD_OPC_FilterValue, 2, 118, 32, 0, // Skip to: 21620 +/* 13310 */ MCD_OPC_Decode, 217, 4, 140, 1, // Opcode: CNTLZDM +/* 13315 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 13339 +/* 13320 */ MCD_OPC_CheckField, 11, 5, 0, 101, 32, 0, // Skip to: 21620 +/* 13327 */ MCD_OPC_CheckField, 0, 2, 0, 94, 32, 0, // Skip to: 21620 +/* 13334 */ MCD_OPC_Decode, 181, 11, 137, 1, // Opcode: POPCNTB +/* 13339 */ MCD_OPC_FilterValue, 11, 19, 0, 0, // Skip to: 13363 +/* 13344 */ MCD_OPC_CheckField, 11, 5, 0, 77, 32, 0, // Skip to: 21620 +/* 13351 */ MCD_OPC_CheckField, 0, 2, 0, 70, 32, 0, // Skip to: 21620 +/* 13358 */ MCD_OPC_Decode, 184, 11, 137, 1, // Opcode: POPCNTW +/* 13363 */ MCD_OPC_FilterValue, 15, 19, 0, 0, // Skip to: 13387 +/* 13368 */ MCD_OPC_CheckField, 11, 5, 0, 53, 32, 0, // Skip to: 21620 +/* 13375 */ MCD_OPC_CheckField, 0, 2, 0, 46, 32, 0, // Skip to: 21620 +/* 13382 */ MCD_OPC_Decode, 183, 11, 139, 1, // Opcode: POPCNTD +/* 13387 */ MCD_OPC_FilterValue, 16, 57, 0, 0, // Skip to: 13449 +/* 13392 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13395 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13412 +/* 13400 */ MCD_OPC_CheckField, 11, 5, 0, 21, 32, 0, // Skip to: 21620 +/* 13407 */ MCD_OPC_Decode, 226, 4, 137, 1, // Opcode: CNTTZW +/* 13412 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 13429 +/* 13417 */ MCD_OPC_CheckField, 11, 5, 0, 4, 32, 0, // Skip to: 21620 +/* 13424 */ MCD_OPC_Decode, 229, 4, 137, 1, // Opcode: CNTTZW_rec +/* 13429 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 13439 +/* 13434 */ MCD_OPC_Decode, 203, 12, 138, 1, // Opcode: SRD +/* 13439 */ MCD_OPC_FilterValue, 3, 240, 31, 0, // Skip to: 21620 +/* 13444 */ MCD_OPC_Decode, 204, 12, 138, 1, // Opcode: SRD_rec +/* 13449 */ MCD_OPC_FilterValue, 17, 47, 0, 0, // Skip to: 13501 +/* 13454 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13457 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13474 +/* 13462 */ MCD_OPC_CheckField, 11, 5, 0, 215, 31, 0, // Skip to: 21620 +/* 13469 */ MCD_OPC_Decode, 223, 4, 139, 1, // Opcode: CNTTZD +/* 13474 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 13491 +/* 13479 */ MCD_OPC_CheckField, 11, 5, 0, 198, 31, 0, // Skip to: 21620 +/* 13486 */ MCD_OPC_Decode, 225, 4, 139, 1, // Opcode: CNTTZD_rec +/* 13491 */ MCD_OPC_FilterValue, 2, 188, 31, 0, // Skip to: 21620 +/* 13496 */ MCD_OPC_Decode, 224, 4, 140, 1, // Opcode: CNTTZDM +/* 13501 */ MCD_OPC_FilterValue, 24, 23, 0, 0, // Skip to: 13529 +/* 13506 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13509 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13519 +/* 13514 */ MCD_OPC_Decode, 194, 12, 138, 1, // Opcode: SRAD +/* 13519 */ MCD_OPC_FilterValue, 1, 160, 31, 0, // Skip to: 21620 +/* 13524 */ MCD_OPC_Decode, 198, 12, 138, 1, // Opcode: SRAD_rec +/* 13529 */ MCD_OPC_FilterValue, 25, 23, 0, 0, // Skip to: 13557 +/* 13534 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 13537 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13547 +/* 13542 */ MCD_OPC_Decode, 195, 12, 141, 1, // Opcode: SRADI +/* 13547 */ MCD_OPC_FilterValue, 1, 132, 31, 0, // Skip to: 21620 +/* 13552 */ MCD_OPC_Decode, 197, 12, 141, 1, // Opcode: SRADI_rec +/* 13557 */ MCD_OPC_FilterValue, 27, 23, 0, 0, // Skip to: 13585 +/* 13562 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 13565 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13575 +/* 13570 */ MCD_OPC_Decode, 193, 7, 141, 1, // Opcode: EXTSWSLI +/* 13575 */ MCD_OPC_FilterValue, 1, 104, 31, 0, // Skip to: 21620 +/* 13580 */ MCD_OPC_Decode, 196, 7, 141, 1, // Opcode: EXTSWSLI_rec +/* 13585 */ MCD_OPC_FilterValue, 28, 37, 0, 0, // Skip to: 13627 +/* 13590 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13593 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13610 +/* 13598 */ MCD_OPC_CheckField, 11, 5, 0, 79, 31, 0, // Skip to: 21620 +/* 13605 */ MCD_OPC_Decode, 187, 7, 137, 1, // Opcode: EXTSH +/* 13610 */ MCD_OPC_FilterValue, 1, 69, 31, 0, // Skip to: 21620 +/* 13615 */ MCD_OPC_CheckField, 11, 5, 0, 62, 31, 0, // Skip to: 21620 +/* 13622 */ MCD_OPC_Decode, 191, 7, 137, 1, // Opcode: EXTSH_rec +/* 13627 */ MCD_OPC_FilterValue, 29, 37, 0, 0, // Skip to: 13669 +/* 13632 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13635 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13652 +/* 13640 */ MCD_OPC_CheckField, 11, 5, 0, 37, 31, 0, // Skip to: 21620 +/* 13647 */ MCD_OPC_Decode, 182, 7, 137, 1, // Opcode: EXTSB +/* 13652 */ MCD_OPC_FilterValue, 1, 27, 31, 0, // Skip to: 21620 +/* 13657 */ MCD_OPC_CheckField, 11, 5, 0, 20, 31, 0, // Skip to: 21620 +/* 13664 */ MCD_OPC_Decode, 186, 7, 137, 1, // Opcode: EXTSB_rec +/* 13669 */ MCD_OPC_FilterValue, 30, 10, 31, 0, // Skip to: 21620 +/* 13674 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13677 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13694 +/* 13682 */ MCD_OPC_CheckField, 11, 5, 0, 251, 30, 0, // Skip to: 21620 +/* 13689 */ MCD_OPC_Decode, 192, 7, 139, 1, // Opcode: EXTSW +/* 13694 */ MCD_OPC_FilterValue, 1, 241, 30, 0, // Skip to: 21620 +/* 13699 */ MCD_OPC_CheckField, 11, 5, 0, 234, 30, 0, // Skip to: 21620 +/* 13706 */ MCD_OPC_Decode, 200, 7, 139, 1, // Opcode: EXTSW_rec +/* 13711 */ MCD_OPC_FilterValue, 14, 56, 1, 0, // Skip to: 14028 +/* 13716 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 13719 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 13747 +/* 13724 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13727 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13737 +/* 13732 */ MCD_OPC_Decode, 146, 3, 135, 1, // Opcode: AND +/* 13737 */ MCD_OPC_FilterValue, 1, 198, 30, 0, // Skip to: 21620 +/* 13742 */ MCD_OPC_Decode, 161, 3, 135, 1, // Opcode: AND_rec +/* 13747 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 13775 +/* 13752 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13755 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13765 +/* 13760 */ MCD_OPC_Decode, 149, 3, 135, 1, // Opcode: ANDC +/* 13765 */ MCD_OPC_FilterValue, 1, 170, 30, 0, // Skip to: 21620 +/* 13770 */ MCD_OPC_Decode, 152, 3, 135, 1, // Opcode: ANDC_rec +/* 13775 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 13803 +/* 13780 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13783 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13793 +/* 13788 */ MCD_OPC_Decode, 221, 10, 135, 1, // Opcode: NOR +/* 13793 */ MCD_OPC_FilterValue, 1, 142, 30, 0, // Skip to: 21620 +/* 13798 */ MCD_OPC_Decode, 224, 10, 135, 1, // Opcode: NOR_rec +/* 13803 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 13820 +/* 13808 */ MCD_OPC_CheckField, 0, 2, 0, 125, 30, 0, // Skip to: 21620 +/* 13815 */ MCD_OPC_Decode, 242, 10, 140, 1, // Opcode: PDEPD +/* 13820 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 13837 +/* 13825 */ MCD_OPC_CheckField, 0, 2, 0, 108, 30, 0, // Skip to: 21620 +/* 13832 */ MCD_OPC_Decode, 243, 10, 140, 1, // Opcode: PEXTD +/* 13837 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 13854 +/* 13842 */ MCD_OPC_CheckField, 0, 2, 0, 91, 30, 0, // Skip to: 21620 +/* 13849 */ MCD_OPC_Decode, 201, 4, 140, 1, // Opcode: CFUGED +/* 13854 */ MCD_OPC_FilterValue, 7, 12, 0, 0, // Skip to: 13871 +/* 13859 */ MCD_OPC_CheckField, 0, 2, 0, 74, 30, 0, // Skip to: 21620 +/* 13866 */ MCD_OPC_Decode, 199, 4, 140, 1, // Opcode: BPERMD +/* 13871 */ MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 13899 +/* 13876 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13879 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13889 +/* 13884 */ MCD_OPC_Decode, 239, 5, 135, 1, // Opcode: EQV +/* 13889 */ MCD_OPC_FilterValue, 1, 46, 30, 0, // Skip to: 21620 +/* 13894 */ MCD_OPC_Decode, 242, 5, 135, 1, // Opcode: EQV_rec +/* 13899 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 13927 +/* 13904 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13907 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13917 +/* 13912 */ MCD_OPC_Decode, 153, 17, 135, 1, // Opcode: XOR +/* 13917 */ MCD_OPC_FilterValue, 1, 18, 30, 0, // Skip to: 21620 +/* 13922 */ MCD_OPC_Decode, 160, 17, 135, 1, // Opcode: XOR_rec +/* 13927 */ MCD_OPC_FilterValue, 12, 23, 0, 0, // Skip to: 13955 +/* 13932 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13935 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13945 +/* 13940 */ MCD_OPC_Decode, 228, 10, 135, 1, // Opcode: ORC +/* 13945 */ MCD_OPC_FilterValue, 1, 246, 29, 0, // Skip to: 21620 +/* 13950 */ MCD_OPC_Decode, 231, 10, 135, 1, // Opcode: ORC_rec +/* 13955 */ MCD_OPC_FilterValue, 13, 23, 0, 0, // Skip to: 13983 +/* 13960 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13963 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13973 +/* 13968 */ MCD_OPC_Decode, 225, 10, 135, 1, // Opcode: OR +/* 13973 */ MCD_OPC_FilterValue, 1, 218, 29, 0, // Skip to: 21620 +/* 13978 */ MCD_OPC_Decode, 236, 10, 135, 1, // Opcode: OR_rec +/* 13983 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 14011 +/* 13988 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 13991 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 14001 +/* 13996 */ MCD_OPC_Decode, 205, 10, 135, 1, // Opcode: NAND +/* 14001 */ MCD_OPC_FilterValue, 1, 190, 29, 0, // Skip to: 21620 +/* 14006 */ MCD_OPC_Decode, 208, 10, 135, 1, // Opcode: NAND_rec +/* 14011 */ MCD_OPC_FilterValue, 15, 180, 29, 0, // Skip to: 21620 +/* 14016 */ MCD_OPC_CheckField, 0, 2, 0, 173, 29, 0, // Skip to: 21620 +/* 14023 */ MCD_OPC_Decode, 203, 4, 135, 1, // Opcode: CMPB +/* 14028 */ MCD_OPC_FilterValue, 15, 163, 29, 0, // Skip to: 21620 +/* 14033 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 14036 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 14077 +/* 14041 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 14044 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 14068 +/* 14049 */ MCD_OPC_CheckField, 23, 3, 0, 140, 29, 0, // Skip to: 21620 +/* 14056 */ MCD_OPC_CheckField, 11, 10, 0, 133, 29, 0, // Skip to: 21620 +/* 14063 */ MCD_OPC_Decode, 150, 17, 128, 1, // Opcode: WAIT +/* 14068 */ MCD_OPC_FilterValue, 2, 123, 29, 0, // Skip to: 21620 +/* 14073 */ MCD_OPC_Decode, 182, 9, 115, // Opcode: LWEPX +/* 14077 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 14100 +/* 14082 */ MCD_OPC_CheckField, 21, 5, 0, 107, 29, 0, // Skip to: 21620 +/* 14089 */ MCD_OPC_CheckField, 0, 2, 2, 100, 29, 0, // Skip to: 21620 +/* 14096 */ MCD_OPC_Decode, 254, 4, 120, // Opcode: DCBSTEP +/* 14100 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 14116 +/* 14105 */ MCD_OPC_CheckField, 0, 2, 2, 84, 29, 0, // Skip to: 21620 +/* 14112 */ MCD_OPC_Decode, 215, 8, 115, // Opcode: LBEPX +/* 14116 */ MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 14139 +/* 14121 */ MCD_OPC_CheckField, 21, 5, 0, 68, 29, 0, // Skip to: 21620 +/* 14128 */ MCD_OPC_CheckField, 0, 2, 2, 61, 29, 0, // Skip to: 21620 +/* 14135 */ MCD_OPC_Decode, 251, 4, 120, // Opcode: DCBFEP +/* 14139 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 14155 +/* 14144 */ MCD_OPC_CheckField, 0, 2, 2, 45, 29, 0, // Skip to: 21620 +/* 14151 */ MCD_OPC_Decode, 147, 13, 115, // Opcode: STWEPX +/* 14155 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 14171 +/* 14160 */ MCD_OPC_CheckField, 0, 2, 2, 29, 29, 0, // Skip to: 21620 +/* 14167 */ MCD_OPC_Decode, 213, 12, 115, // Opcode: STBEPX +/* 14171 */ MCD_OPC_FilterValue, 7, 12, 0, 0, // Skip to: 14188 +/* 14176 */ MCD_OPC_CheckField, 0, 2, 2, 13, 29, 0, // Skip to: 21620 +/* 14183 */ MCD_OPC_Decode, 130, 5, 142, 1, // Opcode: DCBTSTEP +/* 14188 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 14204 +/* 14193 */ MCD_OPC_CheckField, 0, 2, 2, 252, 28, 0, // Skip to: 21620 +/* 14200 */ MCD_OPC_Decode, 142, 9, 115, // Opcode: LHEPX +/* 14204 */ MCD_OPC_FilterValue, 9, 12, 0, 0, // Skip to: 14221 +/* 14209 */ MCD_OPC_CheckField, 0, 2, 2, 236, 28, 0, // Skip to: 21620 +/* 14216 */ MCD_OPC_Decode, 128, 5, 142, 1, // Opcode: DCBTEP +/* 14221 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 14237 +/* 14226 */ MCD_OPC_CheckField, 0, 2, 2, 219, 28, 0, // Skip to: 21620 +/* 14233 */ MCD_OPC_Decode, 248, 12, 115, // Opcode: STHEPX +/* 14237 */ MCD_OPC_FilterValue, 18, 12, 0, 0, // Skip to: 14254 +/* 14242 */ MCD_OPC_CheckField, 0, 2, 2, 203, 28, 0, // Skip to: 21620 +/* 14249 */ MCD_OPC_Decode, 248, 8, 129, 1, // Opcode: LFDEPX +/* 14254 */ MCD_OPC_FilterValue, 22, 12, 0, 0, // Skip to: 14271 +/* 14259 */ MCD_OPC_CheckField, 0, 2, 2, 186, 28, 0, // Skip to: 21620 +/* 14266 */ MCD_OPC_Decode, 234, 12, 129, 1, // Opcode: STFDEPX +/* 14271 */ MCD_OPC_FilterValue, 30, 18, 0, 0, // Skip to: 14294 +/* 14276 */ MCD_OPC_CheckField, 21, 5, 0, 169, 28, 0, // Skip to: 21620 +/* 14283 */ MCD_OPC_CheckField, 0, 2, 2, 162, 28, 0, // Skip to: 21620 +/* 14290 */ MCD_OPC_Decode, 203, 8, 120, // Opcode: ICBIEP +/* 14294 */ MCD_OPC_FilterValue, 31, 153, 28, 0, // Skip to: 21620 +/* 14299 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 14302 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 14318 +/* 14307 */ MCD_OPC_CheckField, 0, 2, 2, 138, 28, 0, // Skip to: 21620 +/* 14314 */ MCD_OPC_Decode, 132, 5, 120, // Opcode: DCBZEP +/* 14318 */ MCD_OPC_FilterValue, 1, 129, 28, 0, // Skip to: 21620 +/* 14323 */ MCD_OPC_CheckField, 0, 2, 2, 122, 28, 0, // Skip to: 21620 +/* 14330 */ MCD_OPC_Decode, 134, 5, 120, // Opcode: DCBZLEP +/* 14334 */ MCD_OPC_FilterValue, 32, 5, 0, 0, // Skip to: 14344 +/* 14339 */ MCD_OPC_Decode, 183, 9, 143, 1, // Opcode: LWZ +/* 14344 */ MCD_OPC_FilterValue, 33, 5, 0, 0, // Skip to: 14354 +/* 14349 */ MCD_OPC_Decode, 186, 9, 143, 1, // Opcode: LWZU +/* 14354 */ MCD_OPC_FilterValue, 34, 5, 0, 0, // Skip to: 14364 +/* 14359 */ MCD_OPC_Decode, 216, 8, 143, 1, // Opcode: LBZ +/* 14364 */ MCD_OPC_FilterValue, 35, 5, 0, 0, // Skip to: 14374 +/* 14369 */ MCD_OPC_Decode, 219, 8, 143, 1, // Opcode: LBZU +/* 14374 */ MCD_OPC_FilterValue, 36, 5, 0, 0, // Skip to: 14384 +/* 14379 */ MCD_OPC_Decode, 141, 13, 143, 1, // Opcode: STW +/* 14384 */ MCD_OPC_FilterValue, 37, 5, 0, 0, // Skip to: 14394 +/* 14389 */ MCD_OPC_Decode, 148, 13, 143, 1, // Opcode: STWU +/* 14394 */ MCD_OPC_FilterValue, 38, 5, 0, 0, // Skip to: 14404 +/* 14399 */ MCD_OPC_Decode, 209, 12, 143, 1, // Opcode: STB +/* 14404 */ MCD_OPC_FilterValue, 39, 5, 0, 0, // Skip to: 14414 +/* 14409 */ MCD_OPC_Decode, 214, 12, 143, 1, // Opcode: STBU +/* 14414 */ MCD_OPC_FilterValue, 40, 5, 0, 0, // Skip to: 14424 +/* 14419 */ MCD_OPC_Decode, 143, 9, 143, 1, // Opcode: LHZ +/* 14424 */ MCD_OPC_FilterValue, 41, 5, 0, 0, // Skip to: 14434 +/* 14429 */ MCD_OPC_Decode, 146, 9, 143, 1, // Opcode: LHZU +/* 14434 */ MCD_OPC_FilterValue, 42, 5, 0, 0, // Skip to: 14444 +/* 14439 */ MCD_OPC_Decode, 130, 9, 143, 1, // Opcode: LHA +/* 14444 */ MCD_OPC_FilterValue, 43, 5, 0, 0, // Skip to: 14454 +/* 14449 */ MCD_OPC_Decode, 134, 9, 143, 1, // Opcode: LHAU +/* 14454 */ MCD_OPC_FilterValue, 44, 5, 0, 0, // Skip to: 14464 +/* 14459 */ MCD_OPC_Decode, 243, 12, 143, 1, // Opcode: STH +/* 14464 */ MCD_OPC_FilterValue, 45, 5, 0, 0, // Skip to: 14474 +/* 14469 */ MCD_OPC_Decode, 249, 12, 143, 1, // Opcode: STHU +/* 14474 */ MCD_OPC_FilterValue, 46, 5, 0, 0, // Skip to: 14484 +/* 14479 */ MCD_OPC_Decode, 159, 9, 143, 1, // Opcode: LMW +/* 14484 */ MCD_OPC_FilterValue, 47, 5, 0, 0, // Skip to: 14494 +/* 14489 */ MCD_OPC_Decode, 130, 13, 143, 1, // Opcode: STMW +/* 14494 */ MCD_OPC_FilterValue, 48, 5, 0, 0, // Skip to: 14504 +/* 14499 */ MCD_OPC_Decode, 254, 8, 144, 1, // Opcode: LFS +/* 14504 */ MCD_OPC_FilterValue, 49, 5, 0, 0, // Skip to: 14514 +/* 14509 */ MCD_OPC_Decode, 255, 8, 144, 1, // Opcode: LFSU +/* 14514 */ MCD_OPC_FilterValue, 50, 5, 0, 0, // Skip to: 14524 +/* 14519 */ MCD_OPC_Decode, 247, 8, 145, 1, // Opcode: LFD +/* 14524 */ MCD_OPC_FilterValue, 51, 5, 0, 0, // Skip to: 14534 +/* 14529 */ MCD_OPC_Decode, 249, 8, 145, 1, // Opcode: LFDU +/* 14534 */ MCD_OPC_FilterValue, 52, 5, 0, 0, // Skip to: 14544 +/* 14539 */ MCD_OPC_Decode, 239, 12, 144, 1, // Opcode: STFS +/* 14544 */ MCD_OPC_FilterValue, 53, 5, 0, 0, // Skip to: 14554 +/* 14549 */ MCD_OPC_Decode, 240, 12, 144, 1, // Opcode: STFSU +/* 14554 */ MCD_OPC_FilterValue, 54, 5, 0, 0, // Skip to: 14564 +/* 14559 */ MCD_OPC_Decode, 233, 12, 145, 1, // Opcode: STFD +/* 14564 */ MCD_OPC_FilterValue, 55, 5, 0, 0, // Skip to: 14574 +/* 14569 */ MCD_OPC_Decode, 235, 12, 145, 1, // Opcode: STFDU +/* 14574 */ MCD_OPC_FilterValue, 56, 12, 0, 0, // Skip to: 14591 +/* 14579 */ MCD_OPC_CheckField, 0, 4, 0, 122, 27, 0, // Skip to: 21620 +/* 14586 */ MCD_OPC_Decode, 160, 9, 146, 1, // Opcode: LQ +/* 14591 */ MCD_OPC_FilterValue, 57, 23, 0, 0, // Skip to: 14619 +/* 14596 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 14599 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 14609 +/* 14604 */ MCD_OPC_Decode, 197, 9, 147, 1, // Opcode: LXSD +/* 14609 */ MCD_OPC_FilterValue, 3, 94, 27, 0, // Skip to: 21620 +/* 14614 */ MCD_OPC_Decode, 203, 9, 147, 1, // Opcode: LXSSP +/* 14619 */ MCD_OPC_FilterValue, 58, 33, 0, 0, // Skip to: 14657 +/* 14624 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 14627 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 14637 +/* 14632 */ MCD_OPC_Decode, 228, 8, 148, 1, // Opcode: LD +/* 14637 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 14647 +/* 14642 */ MCD_OPC_Decode, 235, 8, 148, 1, // Opcode: LDU +/* 14647 */ MCD_OPC_FilterValue, 2, 56, 27, 0, // Skip to: 21620 +/* 14652 */ MCD_OPC_Decode, 172, 9, 148, 1, // Opcode: LWA +/* 14657 */ MCD_OPC_FilterValue, 59, 167, 4, 0, // Skip to: 15853 +/* 14662 */ MCD_OPC_ExtractField, 3, 3, // Inst{5-3} ... +/* 14665 */ MCD_OPC_FilterValue, 2, 203, 1, 0, // Skip to: 15129 +/* 14670 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 14673 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 14697 +/* 14678 */ MCD_OPC_CheckField, 21, 2, 0, 23, 27, 0, // Skip to: 21620 +/* 14685 */ MCD_OPC_CheckField, 0, 1, 0, 16, 27, 0, // Skip to: 21620 +/* 14692 */ MCD_OPC_Decode, 224, 18, 149, 1, // Opcode: XVI8GER4PP +/* 14697 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 14721 +/* 14702 */ MCD_OPC_CheckField, 21, 2, 0, 255, 26, 0, // Skip to: 21620 +/* 14709 */ MCD_OPC_CheckField, 0, 1, 0, 248, 26, 0, // Skip to: 21620 +/* 14716 */ MCD_OPC_Decode, 206, 18, 149, 1, // Opcode: XVF16GER2PP +/* 14721 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 14745 +/* 14726 */ MCD_OPC_CheckField, 21, 2, 0, 231, 26, 0, // Skip to: 21620 +/* 14733 */ MCD_OPC_CheckField, 0, 1, 0, 224, 26, 0, // Skip to: 21620 +/* 14740 */ MCD_OPC_Decode, 211, 18, 149, 1, // Opcode: XVF32GERPP +/* 14745 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 14769 +/* 14750 */ MCD_OPC_CheckField, 21, 2, 0, 207, 26, 0, // Skip to: 21620 +/* 14757 */ MCD_OPC_CheckField, 0, 1, 0, 200, 26, 0, // Skip to: 21620 +/* 14764 */ MCD_OPC_Decode, 222, 18, 149, 1, // Opcode: XVI4GER8PP +/* 14769 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 14793 +/* 14774 */ MCD_OPC_CheckField, 21, 2, 0, 183, 26, 0, // Skip to: 21620 +/* 14781 */ MCD_OPC_CheckField, 0, 1, 0, 176, 26, 0, // Skip to: 21620 +/* 14788 */ MCD_OPC_Decode, 220, 18, 149, 1, // Opcode: XVI16GER2SPP +/* 14793 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 14817 +/* 14798 */ MCD_OPC_CheckField, 21, 2, 0, 159, 26, 0, // Skip to: 21620 +/* 14805 */ MCD_OPC_CheckField, 0, 1, 0, 152, 26, 0, // Skip to: 21620 +/* 14812 */ MCD_OPC_Decode, 163, 18, 149, 1, // Opcode: XVBF16GER2PP +/* 14817 */ MCD_OPC_FilterValue, 7, 19, 0, 0, // Skip to: 14841 +/* 14822 */ MCD_OPC_CheckField, 21, 2, 0, 135, 26, 0, // Skip to: 21620 +/* 14829 */ MCD_OPC_CheckField, 0, 1, 0, 128, 26, 0, // Skip to: 21620 +/* 14836 */ MCD_OPC_Decode, 216, 18, 150, 1, // Opcode: XVF64GERPP +/* 14841 */ MCD_OPC_FilterValue, 10, 19, 0, 0, // Skip to: 14865 +/* 14846 */ MCD_OPC_CheckField, 21, 2, 0, 111, 26, 0, // Skip to: 21620 +/* 14853 */ MCD_OPC_CheckField, 0, 1, 0, 104, 26, 0, // Skip to: 21620 +/* 14860 */ MCD_OPC_Decode, 204, 18, 149, 1, // Opcode: XVF16GER2NP +/* 14865 */ MCD_OPC_FilterValue, 11, 19, 0, 0, // Skip to: 14889 +/* 14870 */ MCD_OPC_CheckField, 21, 2, 0, 87, 26, 0, // Skip to: 21620 +/* 14877 */ MCD_OPC_CheckField, 0, 1, 0, 80, 26, 0, // Skip to: 21620 +/* 14884 */ MCD_OPC_Decode, 209, 18, 149, 1, // Opcode: XVF32GERNP +/* 14889 */ MCD_OPC_FilterValue, 14, 19, 0, 0, // Skip to: 14913 +/* 14894 */ MCD_OPC_CheckField, 21, 2, 0, 63, 26, 0, // Skip to: 21620 +/* 14901 */ MCD_OPC_CheckField, 0, 1, 0, 56, 26, 0, // Skip to: 21620 +/* 14908 */ MCD_OPC_Decode, 161, 18, 149, 1, // Opcode: XVBF16GER2NP +/* 14913 */ MCD_OPC_FilterValue, 15, 19, 0, 0, // Skip to: 14937 +/* 14918 */ MCD_OPC_CheckField, 21, 2, 0, 39, 26, 0, // Skip to: 21620 +/* 14925 */ MCD_OPC_CheckField, 0, 1, 0, 32, 26, 0, // Skip to: 21620 +/* 14932 */ MCD_OPC_Decode, 214, 18, 150, 1, // Opcode: XVF64GERNP +/* 14937 */ MCD_OPC_FilterValue, 18, 19, 0, 0, // Skip to: 14961 +/* 14942 */ MCD_OPC_CheckField, 21, 2, 0, 15, 26, 0, // Skip to: 21620 +/* 14949 */ MCD_OPC_CheckField, 0, 1, 0, 8, 26, 0, // Skip to: 21620 +/* 14956 */ MCD_OPC_Decode, 205, 18, 149, 1, // Opcode: XVF16GER2PN +/* 14961 */ MCD_OPC_FilterValue, 19, 19, 0, 0, // Skip to: 14985 +/* 14966 */ MCD_OPC_CheckField, 21, 2, 0, 247, 25, 0, // Skip to: 21620 +/* 14973 */ MCD_OPC_CheckField, 0, 1, 0, 240, 25, 0, // Skip to: 21620 +/* 14980 */ MCD_OPC_Decode, 210, 18, 149, 1, // Opcode: XVF32GERPN +/* 14985 */ MCD_OPC_FilterValue, 22, 19, 0, 0, // Skip to: 15009 +/* 14990 */ MCD_OPC_CheckField, 21, 2, 0, 223, 25, 0, // Skip to: 21620 +/* 14997 */ MCD_OPC_CheckField, 0, 1, 0, 216, 25, 0, // Skip to: 21620 +/* 15004 */ MCD_OPC_Decode, 162, 18, 149, 1, // Opcode: XVBF16GER2PN +/* 15009 */ MCD_OPC_FilterValue, 23, 19, 0, 0, // Skip to: 15033 +/* 15014 */ MCD_OPC_CheckField, 21, 2, 0, 199, 25, 0, // Skip to: 21620 +/* 15021 */ MCD_OPC_CheckField, 0, 1, 0, 192, 25, 0, // Skip to: 21620 +/* 15028 */ MCD_OPC_Decode, 215, 18, 150, 1, // Opcode: XVF64GERPN +/* 15033 */ MCD_OPC_FilterValue, 26, 19, 0, 0, // Skip to: 15057 +/* 15038 */ MCD_OPC_CheckField, 21, 2, 0, 175, 25, 0, // Skip to: 21620 +/* 15045 */ MCD_OPC_CheckField, 0, 1, 0, 168, 25, 0, // Skip to: 21620 +/* 15052 */ MCD_OPC_Decode, 203, 18, 149, 1, // Opcode: XVF16GER2NN +/* 15057 */ MCD_OPC_FilterValue, 27, 19, 0, 0, // Skip to: 15081 +/* 15062 */ MCD_OPC_CheckField, 21, 2, 0, 151, 25, 0, // Skip to: 21620 +/* 15069 */ MCD_OPC_CheckField, 0, 1, 0, 144, 25, 0, // Skip to: 21620 +/* 15076 */ MCD_OPC_Decode, 208, 18, 149, 1, // Opcode: XVF32GERNN +/* 15081 */ MCD_OPC_FilterValue, 30, 19, 0, 0, // Skip to: 15105 +/* 15086 */ MCD_OPC_CheckField, 21, 2, 0, 127, 25, 0, // Skip to: 21620 +/* 15093 */ MCD_OPC_CheckField, 0, 1, 0, 120, 25, 0, // Skip to: 21620 +/* 15100 */ MCD_OPC_Decode, 160, 18, 149, 1, // Opcode: XVBF16GER2NN +/* 15105 */ MCD_OPC_FilterValue, 31, 110, 25, 0, // Skip to: 21620 +/* 15110 */ MCD_OPC_CheckField, 21, 2, 0, 103, 25, 0, // Skip to: 21620 +/* 15117 */ MCD_OPC_CheckField, 0, 1, 0, 96, 25, 0, // Skip to: 21620 +/* 15124 */ MCD_OPC_Decode, 213, 18, 150, 1, // Opcode: XVF64GERNN +/* 15129 */ MCD_OPC_FilterValue, 3, 71, 1, 0, // Skip to: 15461 +/* 15134 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 15137 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 15161 +/* 15142 */ MCD_OPC_CheckField, 21, 2, 0, 71, 25, 0, // Skip to: 21620 +/* 15149 */ MCD_OPC_CheckField, 0, 1, 0, 64, 25, 0, // Skip to: 21620 +/* 15156 */ MCD_OPC_Decode, 223, 18, 151, 1, // Opcode: XVI8GER4 +/* 15161 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 15185 +/* 15166 */ MCD_OPC_CheckField, 21, 2, 0, 47, 25, 0, // Skip to: 21620 +/* 15173 */ MCD_OPC_CheckField, 0, 1, 0, 40, 25, 0, // Skip to: 21620 +/* 15180 */ MCD_OPC_Decode, 202, 18, 151, 1, // Opcode: XVF16GER2 +/* 15185 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 15209 +/* 15190 */ MCD_OPC_CheckField, 21, 2, 0, 23, 25, 0, // Skip to: 21620 +/* 15197 */ MCD_OPC_CheckField, 0, 1, 0, 16, 25, 0, // Skip to: 21620 +/* 15204 */ MCD_OPC_Decode, 207, 18, 151, 1, // Opcode: XVF32GER +/* 15209 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 15233 +/* 15214 */ MCD_OPC_CheckField, 21, 2, 0, 255, 24, 0, // Skip to: 21620 +/* 15221 */ MCD_OPC_CheckField, 0, 1, 0, 248, 24, 0, // Skip to: 21620 +/* 15228 */ MCD_OPC_Decode, 221, 18, 151, 1, // Opcode: XVI4GER8 +/* 15233 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 15257 +/* 15238 */ MCD_OPC_CheckField, 21, 2, 0, 231, 24, 0, // Skip to: 21620 +/* 15245 */ MCD_OPC_CheckField, 0, 1, 0, 224, 24, 0, // Skip to: 21620 +/* 15252 */ MCD_OPC_Decode, 219, 18, 151, 1, // Opcode: XVI16GER2S +/* 15257 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 15281 +/* 15262 */ MCD_OPC_CheckField, 21, 2, 0, 207, 24, 0, // Skip to: 21620 +/* 15269 */ MCD_OPC_CheckField, 0, 1, 0, 200, 24, 0, // Skip to: 21620 +/* 15276 */ MCD_OPC_Decode, 159, 18, 151, 1, // Opcode: XVBF16GER2 +/* 15281 */ MCD_OPC_FilterValue, 7, 19, 0, 0, // Skip to: 15305 +/* 15286 */ MCD_OPC_CheckField, 21, 2, 0, 183, 24, 0, // Skip to: 21620 +/* 15293 */ MCD_OPC_CheckField, 0, 1, 0, 176, 24, 0, // Skip to: 21620 +/* 15300 */ MCD_OPC_Decode, 212, 18, 152, 1, // Opcode: XVF64GER +/* 15305 */ MCD_OPC_FilterValue, 9, 19, 0, 0, // Skip to: 15329 +/* 15310 */ MCD_OPC_CheckField, 21, 2, 0, 159, 24, 0, // Skip to: 21620 +/* 15317 */ MCD_OPC_CheckField, 0, 1, 0, 152, 24, 0, // Skip to: 21620 +/* 15324 */ MCD_OPC_Decode, 217, 18, 151, 1, // Opcode: XVI16GER2 +/* 15329 */ MCD_OPC_FilterValue, 12, 19, 0, 0, // Skip to: 15353 +/* 15334 */ MCD_OPC_CheckField, 21, 2, 0, 135, 24, 0, // Skip to: 21620 +/* 15341 */ MCD_OPC_CheckField, 0, 1, 0, 128, 24, 0, // Skip to: 21620 +/* 15348 */ MCD_OPC_Decode, 225, 18, 149, 1, // Opcode: XVI8GER4SPP +/* 15353 */ MCD_OPC_FilterValue, 13, 19, 0, 0, // Skip to: 15377 +/* 15358 */ MCD_OPC_CheckField, 21, 2, 0, 111, 24, 0, // Skip to: 21620 +/* 15365 */ MCD_OPC_CheckField, 0, 1, 0, 104, 24, 0, // Skip to: 21620 +/* 15372 */ MCD_OPC_Decode, 218, 18, 149, 1, // Opcode: XVI16GER2PP +/* 15377 */ MCD_OPC_FilterValue, 26, 37, 0, 0, // Skip to: 15419 +/* 15382 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 15385 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 15402 +/* 15390 */ MCD_OPC_CheckField, 16, 5, 0, 79, 24, 0, // Skip to: 21620 +/* 15397 */ MCD_OPC_Decode, 212, 7, 153, 1, // Opcode: FCFIDS +/* 15402 */ MCD_OPC_FilterValue, 5, 69, 24, 0, // Skip to: 21620 +/* 15407 */ MCD_OPC_CheckField, 16, 5, 0, 62, 24, 0, // Skip to: 21620 +/* 15414 */ MCD_OPC_Decode, 213, 7, 153, 1, // Opcode: FCFIDS_rec +/* 15419 */ MCD_OPC_FilterValue, 30, 52, 24, 0, // Skip to: 21620 +/* 15424 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 15427 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 15444 +/* 15432 */ MCD_OPC_CheckField, 16, 5, 0, 37, 24, 0, // Skip to: 21620 +/* 15439 */ MCD_OPC_Decode, 215, 7, 153, 1, // Opcode: FCFIDUS +/* 15444 */ MCD_OPC_FilterValue, 5, 27, 24, 0, // Skip to: 21620 +/* 15449 */ MCD_OPC_CheckField, 16, 5, 0, 20, 24, 0, // Skip to: 21620 +/* 15456 */ MCD_OPC_Decode, 216, 7, 153, 1, // Opcode: FCFIDUS_rec +/* 15461 */ MCD_OPC_FilterValue, 4, 37, 0, 0, // Skip to: 15503 +/* 15466 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 15469 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 15486 +/* 15474 */ MCD_OPC_CheckField, 6, 5, 0, 251, 23, 0, // Skip to: 21620 +/* 15481 */ MCD_OPC_Decode, 244, 7, 154, 1, // Opcode: FDIVS +/* 15486 */ MCD_OPC_FilterValue, 5, 241, 23, 0, // Skip to: 21620 +/* 15491 */ MCD_OPC_CheckField, 6, 5, 0, 234, 23, 0, // Skip to: 21620 +/* 15498 */ MCD_OPC_Decode, 245, 7, 154, 1, // Opcode: FDIVS_rec +/* 15503 */ MCD_OPC_FilterValue, 5, 119, 0, 0, // Skip to: 15627 +/* 15508 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 15511 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15528 +/* 15516 */ MCD_OPC_CheckField, 6, 5, 0, 209, 23, 0, // Skip to: 21620 +/* 15523 */ MCD_OPC_Decode, 184, 8, 154, 1, // Opcode: FSUBS +/* 15528 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 15545 +/* 15533 */ MCD_OPC_CheckField, 6, 5, 0, 192, 23, 0, // Skip to: 21620 +/* 15540 */ MCD_OPC_Decode, 185, 8, 154, 1, // Opcode: FSUBS_rec +/* 15545 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 15562 +/* 15550 */ MCD_OPC_CheckField, 6, 5, 0, 175, 23, 0, // Skip to: 21620 +/* 15557 */ MCD_OPC_Decode, 207, 7, 154, 1, // Opcode: FADDS +/* 15562 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 15579 +/* 15567 */ MCD_OPC_CheckField, 6, 5, 0, 158, 23, 0, // Skip to: 21620 +/* 15574 */ MCD_OPC_Decode, 208, 7, 154, 1, // Opcode: FADDS_rec +/* 15579 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 15603 +/* 15584 */ MCD_OPC_CheckField, 16, 5, 0, 141, 23, 0, // Skip to: 21620 +/* 15591 */ MCD_OPC_CheckField, 6, 5, 0, 134, 23, 0, // Skip to: 21620 +/* 15598 */ MCD_OPC_Decode, 180, 8, 155, 1, // Opcode: FSQRTS +/* 15603 */ MCD_OPC_FilterValue, 5, 124, 23, 0, // Skip to: 21620 +/* 15608 */ MCD_OPC_CheckField, 16, 5, 0, 117, 23, 0, // Skip to: 21620 +/* 15615 */ MCD_OPC_CheckField, 6, 5, 0, 110, 23, 0, // Skip to: 21620 +/* 15622 */ MCD_OPC_Decode, 181, 8, 155, 1, // Opcode: FSQRTS_rec +/* 15627 */ MCD_OPC_FilterValue, 6, 133, 0, 0, // Skip to: 15765 +/* 15632 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 15635 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 15659 +/* 15640 */ MCD_OPC_CheckField, 16, 5, 0, 85, 23, 0, // Skip to: 21620 +/* 15647 */ MCD_OPC_CheckField, 6, 5, 0, 78, 23, 0, // Skip to: 21620 +/* 15654 */ MCD_OPC_Decode, 150, 8, 155, 1, // Opcode: FRES +/* 15659 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 15683 +/* 15664 */ MCD_OPC_CheckField, 16, 5, 0, 61, 23, 0, // Skip to: 21620 +/* 15671 */ MCD_OPC_CheckField, 6, 5, 0, 54, 23, 0, // Skip to: 21620 +/* 15678 */ MCD_OPC_Decode, 151, 8, 155, 1, // Opcode: FRES_rec +/* 15683 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 15700 +/* 15688 */ MCD_OPC_CheckField, 11, 5, 0, 37, 23, 0, // Skip to: 21620 +/* 15695 */ MCD_OPC_Decode, 130, 8, 156, 1, // Opcode: FMULS +/* 15700 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 15717 +/* 15705 */ MCD_OPC_CheckField, 11, 5, 0, 20, 23, 0, // Skip to: 21620 +/* 15712 */ MCD_OPC_Decode, 131, 8, 156, 1, // Opcode: FMULS_rec +/* 15717 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 15741 +/* 15722 */ MCD_OPC_CheckField, 16, 5, 0, 3, 23, 0, // Skip to: 21620 +/* 15729 */ MCD_OPC_CheckField, 6, 5, 0, 252, 22, 0, // Skip to: 21620 +/* 15736 */ MCD_OPC_Decode, 172, 8, 155, 1, // Opcode: FRSQRTES +/* 15741 */ MCD_OPC_FilterValue, 5, 242, 22, 0, // Skip to: 21620 +/* 15746 */ MCD_OPC_CheckField, 16, 5, 0, 235, 22, 0, // Skip to: 21620 +/* 15753 */ MCD_OPC_CheckField, 6, 5, 0, 228, 22, 0, // Skip to: 21620 +/* 15760 */ MCD_OPC_Decode, 173, 8, 155, 1, // Opcode: FRSQRTES_rec +/* 15765 */ MCD_OPC_FilterValue, 7, 218, 22, 0, // Skip to: 21620 +/* 15770 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 15773 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 15783 +/* 15778 */ MCD_OPC_Decode, 254, 7, 157, 1, // Opcode: FMSUBS +/* 15783 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 15793 +/* 15788 */ MCD_OPC_Decode, 255, 7, 157, 1, // Opcode: FMSUBS_rec +/* 15793 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 15803 +/* 15798 */ MCD_OPC_Decode, 248, 7, 157, 1, // Opcode: FMADDS +/* 15803 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 15813 +/* 15808 */ MCD_OPC_Decode, 249, 7, 157, 1, // Opcode: FMADDS_rec +/* 15813 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 15823 +/* 15818 */ MCD_OPC_Decode, 146, 8, 157, 1, // Opcode: FNMSUBS +/* 15823 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 15833 +/* 15828 */ MCD_OPC_Decode, 147, 8, 157, 1, // Opcode: FNMSUBS_rec +/* 15833 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 15843 +/* 15838 */ MCD_OPC_Decode, 142, 8, 157, 1, // Opcode: FNMADDS +/* 15843 */ MCD_OPC_FilterValue, 7, 140, 22, 0, // Skip to: 21620 +/* 15848 */ MCD_OPC_Decode, 143, 8, 157, 1, // Opcode: FNMADDS_rec +/* 15853 */ MCD_OPC_FilterValue, 60, 94, 14, 0, // Skip to: 19536 +/* 15858 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 15861 */ MCD_OPC_FilterValue, 0, 120, 3, 0, // Skip to: 16754 +/* 15866 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 15869 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 15897 +/* 15874 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 15877 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 15887 +/* 15882 */ MCD_OPC_Decode, 166, 17, 158, 1, // Opcode: XSADDSP +/* 15887 */ MCD_OPC_FilterValue, 1, 96, 22, 0, // Skip to: 21620 +/* 15892 */ MCD_OPC_Decode, 216, 17, 159, 1, // Opcode: XSMADDASP +/* 15897 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 15925 +/* 15902 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 15905 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 15915 +/* 15910 */ MCD_OPC_Decode, 145, 18, 158, 1, // Opcode: XSSUBSP +/* 15915 */ MCD_OPC_FilterValue, 1, 68, 22, 0, // Skip to: 21620 +/* 15920 */ MCD_OPC_Decode, 218, 17, 159, 1, // Opcode: XSMADDMSP +/* 15925 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 15953 +/* 15930 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 15933 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 15943 +/* 15938 */ MCD_OPC_Decode, 236, 17, 158, 1, // Opcode: XSMULSP +/* 15943 */ MCD_OPC_FilterValue, 1, 40, 22, 0, // Skip to: 21620 +/* 15948 */ MCD_OPC_Decode, 228, 17, 159, 1, // Opcode: XSMSUBASP +/* 15953 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 15981 +/* 15958 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 15961 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 15971 +/* 15966 */ MCD_OPC_Decode, 212, 17, 158, 1, // Opcode: XSDIVSP +/* 15971 */ MCD_OPC_FilterValue, 1, 12, 22, 0, // Skip to: 21620 +/* 15976 */ MCD_OPC_Decode, 230, 17, 159, 1, // Opcode: XSMSUBMSP +/* 15981 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 16009 +/* 15986 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 15989 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 15999 +/* 15994 */ MCD_OPC_Decode, 163, 17, 160, 1, // Opcode: XSADDDP +/* 15999 */ MCD_OPC_FilterValue, 1, 240, 21, 0, // Skip to: 21620 +/* 16004 */ MCD_OPC_Decode, 215, 17, 161, 1, // Opcode: XSMADDADP +/* 16009 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 16037 +/* 16014 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16017 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16027 +/* 16022 */ MCD_OPC_Decode, 142, 18, 160, 1, // Opcode: XSSUBDP +/* 16027 */ MCD_OPC_FilterValue, 1, 212, 21, 0, // Skip to: 21620 +/* 16032 */ MCD_OPC_Decode, 217, 17, 161, 1, // Opcode: XSMADDMDP +/* 16037 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 16065 +/* 16042 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16045 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16055 +/* 16050 */ MCD_OPC_Decode, 233, 17, 160, 1, // Opcode: XSMULDP +/* 16055 */ MCD_OPC_FilterValue, 1, 184, 21, 0, // Skip to: 21620 +/* 16060 */ MCD_OPC_Decode, 227, 17, 161, 1, // Opcode: XSMSUBADP +/* 16065 */ MCD_OPC_FilterValue, 7, 23, 0, 0, // Skip to: 16093 +/* 16070 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16073 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16083 +/* 16078 */ MCD_OPC_Decode, 209, 17, 160, 1, // Opcode: XSDIVDP +/* 16083 */ MCD_OPC_FilterValue, 1, 156, 21, 0, // Skip to: 21620 +/* 16088 */ MCD_OPC_Decode, 229, 17, 161, 1, // Opcode: XSMSUBMDP +/* 16093 */ MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 16121 +/* 16098 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16101 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16111 +/* 16106 */ MCD_OPC_Decode, 158, 18, 162, 1, // Opcode: XVADDSP +/* 16111 */ MCD_OPC_FilterValue, 1, 128, 21, 0, // Skip to: 21620 +/* 16116 */ MCD_OPC_Decode, 229, 18, 163, 1, // Opcode: XVMADDASP +/* 16121 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 16149 +/* 16126 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16129 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16139 +/* 16134 */ MCD_OPC_Decode, 143, 19, 162, 1, // Opcode: XVSUBSP +/* 16139 */ MCD_OPC_FilterValue, 1, 100, 21, 0, // Skip to: 21620 +/* 16144 */ MCD_OPC_Decode, 231, 18, 163, 1, // Opcode: XVMADDMSP +/* 16149 */ MCD_OPC_FilterValue, 10, 23, 0, 0, // Skip to: 16177 +/* 16154 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16157 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16167 +/* 16162 */ MCD_OPC_Decode, 241, 18, 162, 1, // Opcode: XVMULSP +/* 16167 */ MCD_OPC_FilterValue, 1, 72, 21, 0, // Skip to: 21620 +/* 16172 */ MCD_OPC_Decode, 237, 18, 163, 1, // Opcode: XVMSUBASP +/* 16177 */ MCD_OPC_FilterValue, 11, 23, 0, 0, // Skip to: 16205 +/* 16182 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16185 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16195 +/* 16190 */ MCD_OPC_Decode, 201, 18, 162, 1, // Opcode: XVDIVSP +/* 16195 */ MCD_OPC_FilterValue, 1, 44, 21, 0, // Skip to: 21620 +/* 16200 */ MCD_OPC_Decode, 239, 18, 163, 1, // Opcode: XVMSUBMSP +/* 16205 */ MCD_OPC_FilterValue, 12, 23, 0, 0, // Skip to: 16233 +/* 16210 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16213 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16223 +/* 16218 */ MCD_OPC_Decode, 157, 18, 162, 1, // Opcode: XVADDDP +/* 16223 */ MCD_OPC_FilterValue, 1, 16, 21, 0, // Skip to: 21620 +/* 16228 */ MCD_OPC_Decode, 228, 18, 163, 1, // Opcode: XVMADDADP +/* 16233 */ MCD_OPC_FilterValue, 13, 23, 0, 0, // Skip to: 16261 +/* 16238 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16241 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16251 +/* 16246 */ MCD_OPC_Decode, 142, 19, 162, 1, // Opcode: XVSUBDP +/* 16251 */ MCD_OPC_FilterValue, 1, 244, 20, 0, // Skip to: 21620 +/* 16256 */ MCD_OPC_Decode, 230, 18, 163, 1, // Opcode: XVMADDMDP +/* 16261 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 16289 +/* 16266 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16269 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16279 +/* 16274 */ MCD_OPC_Decode, 240, 18, 162, 1, // Opcode: XVMULDP +/* 16279 */ MCD_OPC_FilterValue, 1, 216, 20, 0, // Skip to: 21620 +/* 16284 */ MCD_OPC_Decode, 236, 18, 163, 1, // Opcode: XVMSUBADP +/* 16289 */ MCD_OPC_FilterValue, 15, 23, 0, 0, // Skip to: 16317 +/* 16294 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16297 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16307 +/* 16302 */ MCD_OPC_Decode, 200, 18, 162, 1, // Opcode: XVDIVDP +/* 16307 */ MCD_OPC_FilterValue, 1, 188, 20, 0, // Skip to: 21620 +/* 16312 */ MCD_OPC_Decode, 238, 18, 163, 1, // Opcode: XVMSUBMDP +/* 16317 */ MCD_OPC_FilterValue, 16, 23, 0, 0, // Skip to: 16345 +/* 16322 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16325 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16335 +/* 16330 */ MCD_OPC_Decode, 221, 17, 160, 1, // Opcode: XSMAXCDP +/* 16335 */ MCD_OPC_FilterValue, 1, 160, 20, 0, // Skip to: 21620 +/* 16340 */ MCD_OPC_Decode, 242, 17, 159, 1, // Opcode: XSNMADDASP +/* 16345 */ MCD_OPC_FilterValue, 17, 23, 0, 0, // Skip to: 16373 +/* 16350 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16353 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16363 +/* 16358 */ MCD_OPC_Decode, 224, 17, 160, 1, // Opcode: XSMINCDP +/* 16363 */ MCD_OPC_FilterValue, 1, 132, 20, 0, // Skip to: 21620 +/* 16368 */ MCD_OPC_Decode, 244, 17, 159, 1, // Opcode: XSNMADDMSP +/* 16373 */ MCD_OPC_FilterValue, 18, 23, 0, 0, // Skip to: 16401 +/* 16378 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16381 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16391 +/* 16386 */ MCD_OPC_Decode, 223, 17, 164, 1, // Opcode: XSMAXJDP +/* 16391 */ MCD_OPC_FilterValue, 1, 104, 20, 0, // Skip to: 21620 +/* 16396 */ MCD_OPC_Decode, 248, 17, 159, 1, // Opcode: XSNMSUBASP +/* 16401 */ MCD_OPC_FilterValue, 19, 23, 0, 0, // Skip to: 16429 +/* 16406 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16409 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16419 +/* 16414 */ MCD_OPC_Decode, 226, 17, 164, 1, // Opcode: XSMINJDP +/* 16419 */ MCD_OPC_FilterValue, 1, 76, 20, 0, // Skip to: 21620 +/* 16424 */ MCD_OPC_Decode, 250, 17, 159, 1, // Opcode: XSNMSUBMSP +/* 16429 */ MCD_OPC_FilterValue, 20, 23, 0, 0, // Skip to: 16457 +/* 16434 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16437 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16447 +/* 16442 */ MCD_OPC_Decode, 222, 17, 160, 1, // Opcode: XSMAXDP +/* 16447 */ MCD_OPC_FilterValue, 1, 48, 20, 0, // Skip to: 21620 +/* 16452 */ MCD_OPC_Decode, 241, 17, 161, 1, // Opcode: XSNMADDADP +/* 16457 */ MCD_OPC_FilterValue, 21, 23, 0, 0, // Skip to: 16485 +/* 16462 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16465 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16475 +/* 16470 */ MCD_OPC_Decode, 225, 17, 160, 1, // Opcode: XSMINDP +/* 16475 */ MCD_OPC_FilterValue, 1, 20, 20, 0, // Skip to: 21620 +/* 16480 */ MCD_OPC_Decode, 243, 17, 161, 1, // Opcode: XSNMADDMDP +/* 16485 */ MCD_OPC_FilterValue, 22, 23, 0, 0, // Skip to: 16513 +/* 16490 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16493 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16503 +/* 16498 */ MCD_OPC_Decode, 176, 17, 160, 1, // Opcode: XSCPSGNDP +/* 16503 */ MCD_OPC_FilterValue, 1, 248, 19, 0, // Skip to: 21620 +/* 16508 */ MCD_OPC_Decode, 247, 17, 161, 1, // Opcode: XSNMSUBADP +/* 16513 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 16530 +/* 16518 */ MCD_OPC_CheckField, 3, 1, 1, 231, 19, 0, // Skip to: 21620 +/* 16525 */ MCD_OPC_Decode, 249, 17, 161, 1, // Opcode: XSNMSUBMDP +/* 16530 */ MCD_OPC_FilterValue, 24, 23, 0, 0, // Skip to: 16558 +/* 16535 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16538 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16548 +/* 16543 */ MCD_OPC_Decode, 233, 18, 162, 1, // Opcode: XVMAXSP +/* 16548 */ MCD_OPC_FilterValue, 1, 203, 19, 0, // Skip to: 21620 +/* 16553 */ MCD_OPC_Decode, 247, 18, 163, 1, // Opcode: XVNMADDASP +/* 16558 */ MCD_OPC_FilterValue, 25, 23, 0, 0, // Skip to: 16586 +/* 16563 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16566 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16576 +/* 16571 */ MCD_OPC_Decode, 235, 18, 162, 1, // Opcode: XVMINSP +/* 16576 */ MCD_OPC_FilterValue, 1, 175, 19, 0, // Skip to: 21620 +/* 16581 */ MCD_OPC_Decode, 249, 18, 163, 1, // Opcode: XVNMADDMSP +/* 16586 */ MCD_OPC_FilterValue, 26, 23, 0, 0, // Skip to: 16614 +/* 16591 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16594 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16604 +/* 16599 */ MCD_OPC_Decode, 177, 18, 162, 1, // Opcode: XVCPSGNSP +/* 16604 */ MCD_OPC_FilterValue, 1, 147, 19, 0, // Skip to: 21620 +/* 16609 */ MCD_OPC_Decode, 251, 18, 163, 1, // Opcode: XVNMSUBASP +/* 16614 */ MCD_OPC_FilterValue, 27, 23, 0, 0, // Skip to: 16642 +/* 16619 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16622 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16632 +/* 16627 */ MCD_OPC_Decode, 227, 18, 162, 1, // Opcode: XVIEXPSP +/* 16632 */ MCD_OPC_FilterValue, 1, 119, 19, 0, // Skip to: 21620 +/* 16637 */ MCD_OPC_Decode, 253, 18, 163, 1, // Opcode: XVNMSUBMSP +/* 16642 */ MCD_OPC_FilterValue, 28, 23, 0, 0, // Skip to: 16670 +/* 16647 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16650 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16660 +/* 16655 */ MCD_OPC_Decode, 232, 18, 162, 1, // Opcode: XVMAXDP +/* 16660 */ MCD_OPC_FilterValue, 1, 91, 19, 0, // Skip to: 21620 +/* 16665 */ MCD_OPC_Decode, 246, 18, 163, 1, // Opcode: XVNMADDADP +/* 16670 */ MCD_OPC_FilterValue, 29, 23, 0, 0, // Skip to: 16698 +/* 16675 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16678 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16688 +/* 16683 */ MCD_OPC_Decode, 234, 18, 162, 1, // Opcode: XVMINDP +/* 16688 */ MCD_OPC_FilterValue, 1, 63, 19, 0, // Skip to: 21620 +/* 16693 */ MCD_OPC_Decode, 248, 18, 163, 1, // Opcode: XVNMADDMDP +/* 16698 */ MCD_OPC_FilterValue, 30, 23, 0, 0, // Skip to: 16726 +/* 16703 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16706 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16716 +/* 16711 */ MCD_OPC_Decode, 176, 18, 162, 1, // Opcode: XVCPSGNDP +/* 16716 */ MCD_OPC_FilterValue, 1, 35, 19, 0, // Skip to: 21620 +/* 16721 */ MCD_OPC_Decode, 250, 18, 163, 1, // Opcode: XVNMSUBADP +/* 16726 */ MCD_OPC_FilterValue, 31, 25, 19, 0, // Skip to: 21620 +/* 16731 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16734 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16744 +/* 16739 */ MCD_OPC_Decode, 226, 18, 162, 1, // Opcode: XVIEXPDP +/* 16744 */ MCD_OPC_FilterValue, 1, 7, 19, 0, // Skip to: 21620 +/* 16749 */ MCD_OPC_Decode, 252, 18, 163, 1, // Opcode: XVNMSUBMDP +/* 16754 */ MCD_OPC_FilterValue, 1, 97, 2, 0, // Skip to: 17368 +/* 16759 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 16762 */ MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 16898 +/* 16767 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16770 */ MCD_OPC_FilterValue, 0, 41, 0, 0, // Skip to: 16816 +/* 16775 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 16778 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16788 +/* 16783 */ MCD_OPC_Decode, 194, 19, 165, 1, // Opcode: XXSLDWI +/* 16788 */ MCD_OPC_FilterValue, 1, 219, 18, 0, // Skip to: 21620 +/* 16793 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 16796 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16806 +/* 16801 */ MCD_OPC_Decode, 170, 19, 162, 1, // Opcode: XXLAND +/* 16806 */ MCD_OPC_FilterValue, 1, 201, 18, 0, // Skip to: 21620 +/* 16811 */ MCD_OPC_Decode, 175, 19, 162, 1, // Opcode: XXLNOR +/* 16816 */ MCD_OPC_FilterValue, 1, 191, 18, 0, // Skip to: 21620 +/* 16821 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 16824 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16834 +/* 16829 */ MCD_OPC_Decode, 167, 17, 164, 1, // Opcode: XSCMPEQDP +/* 16834 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 16858 +/* 16839 */ MCD_OPC_CheckField, 21, 2, 0, 166, 18, 0, // Skip to: 21620 +/* 16846 */ MCD_OPC_CheckField, 0, 1, 0, 159, 18, 0, // Skip to: 21620 +/* 16853 */ MCD_OPC_Decode, 174, 17, 166, 1, // Opcode: XSCMPUDP +/* 16858 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 16868 +/* 16863 */ MCD_OPC_Decode, 166, 18, 162, 1, // Opcode: XVCMPEQSP +/* 16868 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 16878 +/* 16873 */ MCD_OPC_Decode, 164, 18, 162, 1, // Opcode: XVCMPEQDP +/* 16878 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 16888 +/* 16883 */ MCD_OPC_Decode, 167, 18, 162, 1, // Opcode: XVCMPEQSP_rec +/* 16888 */ MCD_OPC_FilterValue, 7, 119, 18, 0, // Skip to: 21620 +/* 16893 */ MCD_OPC_Decode, 165, 18, 162, 1, // Opcode: XVCMPEQDP_rec +/* 16898 */ MCD_OPC_FilterValue, 1, 131, 0, 0, // Skip to: 17034 +/* 16903 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 16906 */ MCD_OPC_FilterValue, 0, 41, 0, 0, // Skip to: 16952 +/* 16911 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 16914 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16924 +/* 16919 */ MCD_OPC_Decode, 188, 19, 165, 1, // Opcode: XXPERMDI +/* 16924 */ MCD_OPC_FilterValue, 1, 83, 18, 0, // Skip to: 21620 +/* 16929 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... +/* 16932 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16942 +/* 16937 */ MCD_OPC_Decode, 171, 19, 162, 1, // Opcode: XXLANDC +/* 16942 */ MCD_OPC_FilterValue, 1, 65, 18, 0, // Skip to: 21620 +/* 16947 */ MCD_OPC_Decode, 177, 19, 162, 1, // Opcode: XXLORC +/* 16952 */ MCD_OPC_FilterValue, 1, 55, 18, 0, // Skip to: 21620 +/* 16957 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 16960 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 16970 +/* 16965 */ MCD_OPC_Decode, 171, 17, 164, 1, // Opcode: XSCMPGTDP +/* 16970 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 16994 +/* 16975 */ MCD_OPC_CheckField, 21, 2, 0, 30, 18, 0, // Skip to: 21620 +/* 16982 */ MCD_OPC_CheckField, 0, 1, 0, 23, 18, 0, // Skip to: 21620 +/* 16989 */ MCD_OPC_Decode, 172, 17, 166, 1, // Opcode: XSCMPODP +/* 16994 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 17004 +/* 16999 */ MCD_OPC_Decode, 174, 18, 162, 1, // Opcode: XVCMPGTSP +/* 17004 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 17014 +/* 17009 */ MCD_OPC_Decode, 172, 18, 162, 1, // Opcode: XVCMPGTDP +/* 17014 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 17024 +/* 17019 */ MCD_OPC_Decode, 175, 18, 162, 1, // Opcode: XVCMPGTSP_rec +/* 17024 */ MCD_OPC_FilterValue, 7, 239, 17, 0, // Skip to: 21620 +/* 17029 */ MCD_OPC_Decode, 173, 18, 162, 1, // Opcode: XVCMPGTDP_rec +/* 17034 */ MCD_OPC_FilterValue, 2, 186, 0, 0, // Skip to: 17225 +/* 17039 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 17042 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 17070 +/* 17047 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 17050 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 17060 +/* 17055 */ MCD_OPC_Decode, 184, 19, 162, 1, // Opcode: XXMRGHW +/* 17060 */ MCD_OPC_FilterValue, 1, 203, 17, 0, // Skip to: 21620 +/* 17065 */ MCD_OPC_Decode, 170, 17, 164, 1, // Opcode: XSCMPGEDP +/* 17070 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 17087 +/* 17075 */ MCD_OPC_CheckField, 3, 1, 0, 186, 17, 0, // Skip to: 21620 +/* 17082 */ MCD_OPC_Decode, 185, 19, 162, 1, // Opcode: XXMRGLW +/* 17087 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 17140 +/* 17092 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 17095 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 17130 +/* 17100 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 17103 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17120 +/* 17108 */ MCD_OPC_CheckField, 18, 3, 0, 153, 17, 0, // Skip to: 21620 +/* 17115 */ MCD_OPC_Decode, 200, 19, 167, 1, // Opcode: XXSPLTW +/* 17120 */ MCD_OPC_FilterValue, 1, 143, 17, 0, // Skip to: 21620 +/* 17125 */ MCD_OPC_Decode, 164, 19, 168, 1, // Opcode: XXEXTRACTUW +/* 17130 */ MCD_OPC_FilterValue, 1, 133, 17, 0, // Skip to: 21620 +/* 17135 */ MCD_OPC_Decode, 170, 18, 162, 1, // Opcode: XVCMPGESP +/* 17140 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 17157 +/* 17145 */ MCD_OPC_CheckField, 3, 1, 1, 116, 17, 0, // Skip to: 21620 +/* 17152 */ MCD_OPC_Decode, 168, 18, 162, 1, // Opcode: XVCMPGEDP +/* 17157 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 17174 +/* 17162 */ MCD_OPC_CheckField, 3, 1, 0, 99, 17, 0, // Skip to: 21620 +/* 17169 */ MCD_OPC_Decode, 176, 19, 162, 1, // Opcode: XXLOR +/* 17174 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 17191 +/* 17179 */ MCD_OPC_CheckField, 3, 1, 0, 82, 17, 0, // Skip to: 21620 +/* 17186 */ MCD_OPC_Decode, 174, 19, 162, 1, // Opcode: XXLNAND +/* 17191 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 17208 +/* 17196 */ MCD_OPC_CheckField, 3, 1, 1, 65, 17, 0, // Skip to: 21620 +/* 17203 */ MCD_OPC_Decode, 171, 18, 162, 1, // Opcode: XVCMPGESP_rec +/* 17208 */ MCD_OPC_FilterValue, 7, 55, 17, 0, // Skip to: 21620 +/* 17213 */ MCD_OPC_CheckField, 3, 1, 1, 48, 17, 0, // Skip to: 21620 +/* 17220 */ MCD_OPC_Decode, 169, 18, 162, 1, // Opcode: XVCMPGEDP_rec +/* 17225 */ MCD_OPC_FilterValue, 3, 38, 17, 0, // Skip to: 21620 +/* 17230 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 17233 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17250 +/* 17238 */ MCD_OPC_CheckField, 3, 1, 0, 23, 17, 0, // Skip to: 21620 +/* 17245 */ MCD_OPC_Decode, 187, 19, 162, 1, // Opcode: XXPERM +/* 17250 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 17292 +/* 17255 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 17258 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 17268 +/* 17263 */ MCD_OPC_Decode, 190, 19, 162, 1, // Opcode: XXPERMR +/* 17268 */ MCD_OPC_FilterValue, 1, 251, 16, 0, // Skip to: 21620 +/* 17273 */ MCD_OPC_CheckField, 21, 2, 0, 244, 16, 0, // Skip to: 21620 +/* 17280 */ MCD_OPC_CheckField, 0, 1, 0, 237, 16, 0, // Skip to: 21620 +/* 17287 */ MCD_OPC_Decode, 168, 17, 166, 1, // Opcode: XSCMPEXPDP +/* 17292 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 17334 +/* 17297 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 17300 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 17324 +/* 17305 */ MCD_OPC_CheckField, 19, 2, 0, 212, 16, 0, // Skip to: 21620 +/* 17312 */ MCD_OPC_CheckField, 1, 1, 0, 205, 16, 0, // Skip to: 21620 +/* 17319 */ MCD_OPC_Decode, 197, 19, 169, 1, // Opcode: XXSPLTIB +/* 17324 */ MCD_OPC_FilterValue, 1, 195, 16, 0, // Skip to: 21620 +/* 17329 */ MCD_OPC_Decode, 169, 19, 170, 1, // Opcode: XXINSERTW +/* 17334 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 17351 +/* 17339 */ MCD_OPC_CheckField, 3, 1, 0, 178, 16, 0, // Skip to: 21620 +/* 17346 */ MCD_OPC_Decode, 179, 19, 162, 1, // Opcode: XXLXOR +/* 17351 */ MCD_OPC_FilterValue, 5, 168, 16, 0, // Skip to: 21620 +/* 17356 */ MCD_OPC_CheckField, 3, 1, 0, 161, 16, 0, // Skip to: 21620 +/* 17363 */ MCD_OPC_Decode, 172, 19, 162, 1, // Opcode: XXLEQV +/* 17368 */ MCD_OPC_FilterValue, 2, 105, 8, 0, // Skip to: 19526 +/* 17373 */ MCD_OPC_ExtractField, 7, 4, // Inst{10-7} ... +/* 17376 */ MCD_OPC_FilterValue, 0, 69, 0, 0, // Skip to: 17450 +/* 17381 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 17384 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 17426 +/* 17389 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17392 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17409 +/* 17397 */ MCD_OPC_CheckField, 16, 5, 0, 120, 16, 0, // Skip to: 21620 +/* 17404 */ MCD_OPC_Decode, 137, 18, 171, 1, // Opcode: XSRSQRTESP +/* 17409 */ MCD_OPC_FilterValue, 1, 110, 16, 0, // Skip to: 21620 +/* 17414 */ MCD_OPC_CheckField, 16, 5, 0, 103, 16, 0, // Skip to: 21620 +/* 17421 */ MCD_OPC_Decode, 131, 18, 171, 1, // Opcode: XSRESP +/* 17426 */ MCD_OPC_FilterValue, 3, 93, 16, 0, // Skip to: 21620 +/* 17431 */ MCD_OPC_CheckField, 16, 5, 0, 86, 16, 0, // Skip to: 21620 +/* 17438 */ MCD_OPC_CheckField, 6, 1, 0, 79, 16, 0, // Skip to: 21620 +/* 17445 */ MCD_OPC_Decode, 141, 18, 171, 1, // Opcode: XSSQRTSP +/* 17450 */ MCD_OPC_FilterValue, 2, 153, 0, 0, // Skip to: 17608 +/* 17455 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 17458 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 17500 +/* 17463 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17466 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17483 +/* 17471 */ MCD_OPC_CheckField, 16, 5, 0, 46, 16, 0, // Skip to: 21620 +/* 17478 */ MCD_OPC_Decode, 188, 17, 172, 1, // Opcode: XSCVDPUXWS +/* 17483 */ MCD_OPC_FilterValue, 1, 36, 16, 0, // Skip to: 21620 +/* 17488 */ MCD_OPC_CheckField, 16, 5, 0, 29, 16, 0, // Skip to: 21620 +/* 17495 */ MCD_OPC_Decode, 184, 17, 172, 1, // Opcode: XSCVDPSXWS +/* 17500 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 17542 +/* 17505 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17508 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17525 +/* 17513 */ MCD_OPC_CheckField, 16, 5, 0, 4, 16, 0, // Skip to: 21620 +/* 17520 */ MCD_OPC_Decode, 253, 17, 172, 1, // Opcode: XSRDPI +/* 17525 */ MCD_OPC_FilterValue, 1, 250, 15, 0, // Skip to: 21620 +/* 17530 */ MCD_OPC_CheckField, 16, 5, 0, 243, 15, 0, // Skip to: 21620 +/* 17537 */ MCD_OPC_Decode, 129, 18, 172, 1, // Opcode: XSRDPIZ +/* 17542 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 17584 +/* 17547 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17550 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17567 +/* 17555 */ MCD_OPC_CheckField, 16, 5, 0, 218, 15, 0, // Skip to: 21620 +/* 17562 */ MCD_OPC_Decode, 136, 18, 172, 1, // Opcode: XSRSQRTEDP +/* 17567 */ MCD_OPC_FilterValue, 1, 208, 15, 0, // Skip to: 21620 +/* 17572 */ MCD_OPC_CheckField, 16, 5, 0, 201, 15, 0, // Skip to: 21620 +/* 17579 */ MCD_OPC_Decode, 130, 18, 172, 1, // Opcode: XSREDP +/* 17584 */ MCD_OPC_FilterValue, 3, 191, 15, 0, // Skip to: 21620 +/* 17589 */ MCD_OPC_CheckField, 16, 5, 0, 184, 15, 0, // Skip to: 21620 +/* 17596 */ MCD_OPC_CheckField, 6, 1, 0, 177, 15, 0, // Skip to: 21620 +/* 17603 */ MCD_OPC_Decode, 138, 18, 172, 1, // Opcode: XSSQRTDP +/* 17608 */ MCD_OPC_FilterValue, 3, 140, 0, 0, // Skip to: 17753 +/* 17613 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 17616 */ MCD_OPC_FilterValue, 0, 51, 0, 0, // Skip to: 17672 +/* 17621 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17624 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 17648 +/* 17629 */ MCD_OPC_CheckField, 16, 5, 0, 144, 15, 0, // Skip to: 21620 +/* 17636 */ MCD_OPC_CheckField, 2, 1, 1, 137, 15, 0, // Skip to: 21620 +/* 17643 */ MCD_OPC_Decode, 128, 18, 172, 1, // Opcode: XSRDPIP +/* 17648 */ MCD_OPC_FilterValue, 1, 127, 15, 0, // Skip to: 21620 +/* 17653 */ MCD_OPC_CheckField, 16, 5, 0, 120, 15, 0, // Skip to: 21620 +/* 17660 */ MCD_OPC_CheckField, 2, 1, 1, 113, 15, 0, // Skip to: 21620 +/* 17667 */ MCD_OPC_Decode, 255, 17, 172, 1, // Opcode: XSRDPIM +/* 17672 */ MCD_OPC_FilterValue, 1, 103, 15, 0, // Skip to: 21620 +/* 17677 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17680 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 17729 +/* 17685 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 17688 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 17712 +/* 17693 */ MCD_OPC_CheckField, 16, 7, 0, 80, 15, 0, // Skip to: 21620 +/* 17700 */ MCD_OPC_CheckField, 0, 1, 0, 73, 15, 0, // Skip to: 21620 +/* 17707 */ MCD_OPC_Decode, 147, 18, 173, 1, // Opcode: XSTSQRTDP +/* 17712 */ MCD_OPC_FilterValue, 1, 63, 15, 0, // Skip to: 21620 +/* 17717 */ MCD_OPC_CheckField, 16, 5, 0, 56, 15, 0, // Skip to: 21620 +/* 17724 */ MCD_OPC_Decode, 254, 17, 172, 1, // Opcode: XSRDPIC +/* 17729 */ MCD_OPC_FilterValue, 1, 46, 15, 0, // Skip to: 21620 +/* 17734 */ MCD_OPC_CheckField, 21, 2, 0, 39, 15, 0, // Skip to: 21620 +/* 17741 */ MCD_OPC_CheckField, 0, 1, 0, 32, 15, 0, // Skip to: 21620 +/* 17748 */ MCD_OPC_Decode, 146, 18, 166, 1, // Opcode: XSTDIVDP +/* 17753 */ MCD_OPC_FilterValue, 4, 153, 0, 0, // Skip to: 17911 +/* 17758 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 17761 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 17803 +/* 17766 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17769 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17786 +/* 17774 */ MCD_OPC_CheckField, 16, 5, 0, 255, 14, 0, // Skip to: 21620 +/* 17781 */ MCD_OPC_Decode, 191, 18, 174, 1, // Opcode: XVCVSPUXWS +/* 17786 */ MCD_OPC_FilterValue, 1, 245, 14, 0, // Skip to: 21620 +/* 17791 */ MCD_OPC_CheckField, 16, 5, 0, 238, 14, 0, // Skip to: 21620 +/* 17798 */ MCD_OPC_Decode, 189, 18, 174, 1, // Opcode: XVCVSPSXWS +/* 17803 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 17845 +/* 17808 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17811 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17828 +/* 17816 */ MCD_OPC_CheckField, 16, 5, 0, 213, 14, 0, // Skip to: 21620 +/* 17823 */ MCD_OPC_Decode, 133, 19, 174, 1, // Opcode: XVRSPI +/* 17828 */ MCD_OPC_FilterValue, 1, 203, 14, 0, // Skip to: 21620 +/* 17833 */ MCD_OPC_CheckField, 16, 5, 0, 196, 14, 0, // Skip to: 21620 +/* 17840 */ MCD_OPC_Decode, 137, 19, 174, 1, // Opcode: XVRSPIZ +/* 17845 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 17887 +/* 17850 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17853 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17870 +/* 17858 */ MCD_OPC_CheckField, 16, 5, 0, 171, 14, 0, // Skip to: 21620 +/* 17865 */ MCD_OPC_Decode, 139, 19, 174, 1, // Opcode: XVRSQRTESP +/* 17870 */ MCD_OPC_FilterValue, 1, 161, 14, 0, // Skip to: 21620 +/* 17875 */ MCD_OPC_CheckField, 16, 5, 0, 154, 14, 0, // Skip to: 21620 +/* 17882 */ MCD_OPC_Decode, 132, 19, 174, 1, // Opcode: XVRESP +/* 17887 */ MCD_OPC_FilterValue, 3, 144, 14, 0, // Skip to: 21620 +/* 17892 */ MCD_OPC_CheckField, 16, 5, 0, 137, 14, 0, // Skip to: 21620 +/* 17899 */ MCD_OPC_CheckField, 6, 1, 0, 130, 14, 0, // Skip to: 21620 +/* 17906 */ MCD_OPC_Decode, 141, 19, 174, 1, // Opcode: XVSQRTSP +/* 17911 */ MCD_OPC_FilterValue, 5, 176, 0, 0, // Skip to: 18092 +/* 17916 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 17919 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 18011 +/* 17924 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 17927 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 17969 +/* 17932 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17935 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17952 +/* 17940 */ MCD_OPC_CheckField, 16, 5, 0, 89, 14, 0, // Skip to: 21620 +/* 17947 */ MCD_OPC_Decode, 199, 18, 174, 1, // Opcode: XVCVUXWSP +/* 17952 */ MCD_OPC_FilterValue, 1, 79, 14, 0, // Skip to: 21620 +/* 17957 */ MCD_OPC_CheckField, 16, 5, 0, 72, 14, 0, // Skip to: 21620 +/* 17964 */ MCD_OPC_Decode, 195, 18, 174, 1, // Opcode: XVCVSXWSP +/* 17969 */ MCD_OPC_FilterValue, 1, 62, 14, 0, // Skip to: 21620 +/* 17974 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 17977 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 17994 +/* 17982 */ MCD_OPC_CheckField, 16, 5, 0, 47, 14, 0, // Skip to: 21620 +/* 17989 */ MCD_OPC_Decode, 136, 19, 174, 1, // Opcode: XVRSPIP +/* 17994 */ MCD_OPC_FilterValue, 1, 37, 14, 0, // Skip to: 21620 +/* 17999 */ MCD_OPC_CheckField, 16, 5, 0, 30, 14, 0, // Skip to: 21620 +/* 18006 */ MCD_OPC_Decode, 135, 19, 174, 1, // Opcode: XVRSPIM +/* 18011 */ MCD_OPC_FilterValue, 1, 20, 14, 0, // Skip to: 21620 +/* 18016 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18019 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 18068 +/* 18024 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 18027 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 18051 +/* 18032 */ MCD_OPC_CheckField, 16, 7, 0, 253, 13, 0, // Skip to: 21620 +/* 18039 */ MCD_OPC_CheckField, 0, 1, 0, 246, 13, 0, // Skip to: 21620 +/* 18046 */ MCD_OPC_Decode, 148, 19, 175, 1, // Opcode: XVTSQRTSP +/* 18051 */ MCD_OPC_FilterValue, 1, 236, 13, 0, // Skip to: 21620 +/* 18056 */ MCD_OPC_CheckField, 16, 5, 0, 229, 13, 0, // Skip to: 21620 +/* 18063 */ MCD_OPC_Decode, 134, 19, 174, 1, // Opcode: XVRSPIC +/* 18068 */ MCD_OPC_FilterValue, 1, 219, 13, 0, // Skip to: 21620 +/* 18073 */ MCD_OPC_CheckField, 21, 2, 0, 212, 13, 0, // Skip to: 21620 +/* 18080 */ MCD_OPC_CheckField, 0, 1, 0, 205, 13, 0, // Skip to: 21620 +/* 18087 */ MCD_OPC_Decode, 145, 19, 176, 1, // Opcode: XVTDIVSP +/* 18092 */ MCD_OPC_FilterValue, 6, 153, 0, 0, // Skip to: 18250 +/* 18097 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 18100 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 18142 +/* 18105 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18108 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18125 +/* 18113 */ MCD_OPC_CheckField, 16, 5, 0, 172, 13, 0, // Skip to: 21620 +/* 18120 */ MCD_OPC_Decode, 183, 18, 174, 1, // Opcode: XVCVDPUXWS +/* 18125 */ MCD_OPC_FilterValue, 1, 162, 13, 0, // Skip to: 21620 +/* 18130 */ MCD_OPC_CheckField, 16, 5, 0, 155, 13, 0, // Skip to: 21620 +/* 18137 */ MCD_OPC_Decode, 181, 18, 174, 1, // Opcode: XVCVDPSXWS +/* 18142 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 18184 +/* 18147 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18150 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18167 +/* 18155 */ MCD_OPC_CheckField, 16, 5, 0, 130, 13, 0, // Skip to: 21620 +/* 18162 */ MCD_OPC_Decode, 254, 18, 174, 1, // Opcode: XVRDPI +/* 18167 */ MCD_OPC_FilterValue, 1, 120, 13, 0, // Skip to: 21620 +/* 18172 */ MCD_OPC_CheckField, 16, 5, 0, 113, 13, 0, // Skip to: 21620 +/* 18179 */ MCD_OPC_Decode, 130, 19, 174, 1, // Opcode: XVRDPIZ +/* 18184 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 18226 +/* 18189 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18192 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18209 +/* 18197 */ MCD_OPC_CheckField, 16, 5, 0, 88, 13, 0, // Skip to: 21620 +/* 18204 */ MCD_OPC_Decode, 138, 19, 174, 1, // Opcode: XVRSQRTEDP +/* 18209 */ MCD_OPC_FilterValue, 1, 78, 13, 0, // Skip to: 21620 +/* 18214 */ MCD_OPC_CheckField, 16, 5, 0, 71, 13, 0, // Skip to: 21620 +/* 18221 */ MCD_OPC_Decode, 131, 19, 174, 1, // Opcode: XVREDP +/* 18226 */ MCD_OPC_FilterValue, 3, 61, 13, 0, // Skip to: 21620 +/* 18231 */ MCD_OPC_CheckField, 16, 5, 0, 54, 13, 0, // Skip to: 21620 +/* 18238 */ MCD_OPC_CheckField, 6, 1, 0, 47, 13, 0, // Skip to: 21620 +/* 18245 */ MCD_OPC_Decode, 140, 19, 174, 1, // Opcode: XVSQRTDP +/* 18250 */ MCD_OPC_FilterValue, 7, 176, 0, 0, // Skip to: 18431 +/* 18255 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 18258 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 18350 +/* 18263 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 18266 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 18308 +/* 18271 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18274 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18291 +/* 18279 */ MCD_OPC_CheckField, 16, 5, 0, 6, 13, 0, // Skip to: 21620 +/* 18286 */ MCD_OPC_Decode, 198, 18, 174, 1, // Opcode: XVCVUXWDP +/* 18291 */ MCD_OPC_FilterValue, 1, 252, 12, 0, // Skip to: 21620 +/* 18296 */ MCD_OPC_CheckField, 16, 5, 0, 245, 12, 0, // Skip to: 21620 +/* 18303 */ MCD_OPC_Decode, 194, 18, 174, 1, // Opcode: XVCVSXWDP +/* 18308 */ MCD_OPC_FilterValue, 1, 235, 12, 0, // Skip to: 21620 +/* 18313 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18316 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18333 +/* 18321 */ MCD_OPC_CheckField, 16, 5, 0, 220, 12, 0, // Skip to: 21620 +/* 18328 */ MCD_OPC_Decode, 129, 19, 174, 1, // Opcode: XVRDPIP +/* 18333 */ MCD_OPC_FilterValue, 1, 210, 12, 0, // Skip to: 21620 +/* 18338 */ MCD_OPC_CheckField, 16, 5, 0, 203, 12, 0, // Skip to: 21620 +/* 18345 */ MCD_OPC_Decode, 128, 19, 174, 1, // Opcode: XVRDPIM +/* 18350 */ MCD_OPC_FilterValue, 1, 193, 12, 0, // Skip to: 21620 +/* 18355 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18358 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 18407 +/* 18363 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 18366 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 18390 +/* 18371 */ MCD_OPC_CheckField, 16, 7, 0, 170, 12, 0, // Skip to: 21620 +/* 18378 */ MCD_OPC_CheckField, 0, 1, 0, 163, 12, 0, // Skip to: 21620 +/* 18385 */ MCD_OPC_Decode, 147, 19, 175, 1, // Opcode: XVTSQRTDP +/* 18390 */ MCD_OPC_FilterValue, 1, 153, 12, 0, // Skip to: 21620 +/* 18395 */ MCD_OPC_CheckField, 16, 5, 0, 146, 12, 0, // Skip to: 21620 +/* 18402 */ MCD_OPC_Decode, 255, 18, 174, 1, // Opcode: XVRDPIC +/* 18407 */ MCD_OPC_FilterValue, 1, 136, 12, 0, // Skip to: 21620 +/* 18412 */ MCD_OPC_CheckField, 21, 2, 0, 129, 12, 0, // Skip to: 21620 +/* 18419 */ MCD_OPC_CheckField, 0, 1, 0, 122, 12, 0, // Skip to: 21620 +/* 18426 */ MCD_OPC_Decode, 144, 19, 176, 1, // Opcode: XVTDIVDP +/* 18431 */ MCD_OPC_FilterValue, 8, 69, 0, 0, // Skip to: 18505 +/* 18436 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 18439 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 18481 +/* 18444 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18447 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18464 +/* 18452 */ MCD_OPC_CheckField, 16, 5, 0, 89, 12, 0, // Skip to: 21620 +/* 18459 */ MCD_OPC_Decode, 180, 17, 172, 1, // Opcode: XSCVDPSP +/* 18464 */ MCD_OPC_FilterValue, 1, 79, 12, 0, // Skip to: 21620 +/* 18469 */ MCD_OPC_CheckField, 16, 5, 0, 72, 12, 0, // Skip to: 21620 +/* 18476 */ MCD_OPC_Decode, 135, 18, 177, 1, // Opcode: XSRSP +/* 18481 */ MCD_OPC_FilterValue, 3, 62, 12, 0, // Skip to: 21620 +/* 18486 */ MCD_OPC_CheckField, 16, 5, 0, 55, 12, 0, // Skip to: 21620 +/* 18493 */ MCD_OPC_CheckField, 6, 1, 0, 48, 12, 0, // Skip to: 21620 +/* 18500 */ MCD_OPC_Decode, 181, 17, 178, 1, // Opcode: XSCVDPSPN +/* 18505 */ MCD_OPC_FilterValue, 9, 69, 0, 0, // Skip to: 18579 +/* 18510 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 18513 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 18555 +/* 18518 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18521 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18538 +/* 18526 */ MCD_OPC_CheckField, 16, 5, 0, 15, 12, 0, // Skip to: 21620 +/* 18533 */ MCD_OPC_Decode, 208, 17, 177, 1, // Opcode: XSCVUXDSP +/* 18538 */ MCD_OPC_FilterValue, 1, 5, 12, 0, // Skip to: 21620 +/* 18543 */ MCD_OPC_CheckField, 16, 5, 0, 254, 11, 0, // Skip to: 21620 +/* 18550 */ MCD_OPC_Decode, 204, 17, 177, 1, // Opcode: XSCVSXDSP +/* 18555 */ MCD_OPC_FilterValue, 2, 244, 11, 0, // Skip to: 21620 +/* 18560 */ MCD_OPC_CheckField, 6, 1, 0, 237, 11, 0, // Skip to: 21620 +/* 18567 */ MCD_OPC_CheckField, 0, 1, 0, 230, 11, 0, // Skip to: 21620 +/* 18574 */ MCD_OPC_Decode, 150, 18, 179, 1, // Opcode: XSTSTDCSP +/* 18579 */ MCD_OPC_FilterValue, 10, 181, 0, 0, // Skip to: 18765 +/* 18584 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 18587 */ MCD_OPC_FilterValue, 0, 94, 0, 0, // Skip to: 18686 +/* 18592 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 18595 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 18623 +/* 18600 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18603 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 18613 +/* 18608 */ MCD_OPC_Decode, 186, 17, 172, 1, // Opcode: XSCVDPUXDS +/* 18613 */ MCD_OPC_FilterValue, 1, 186, 11, 0, // Skip to: 21620 +/* 18618 */ MCD_OPC_Decode, 182, 17, 172, 1, // Opcode: XSCVDPSXDS +/* 18623 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 18651 +/* 18628 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18631 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 18641 +/* 18636 */ MCD_OPC_Decode, 200, 17, 172, 1, // Opcode: XSCVSPDP +/* 18641 */ MCD_OPC_FilterValue, 1, 158, 11, 0, // Skip to: 21620 +/* 18646 */ MCD_OPC_Decode, 161, 17, 172, 1, // Opcode: XSABSDP +/* 18651 */ MCD_OPC_FilterValue, 3, 148, 11, 0, // Skip to: 21620 +/* 18656 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18659 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 18669 +/* 18664 */ MCD_OPC_Decode, 201, 17, 180, 1, // Opcode: XSCVSPDPN +/* 18669 */ MCD_OPC_FilterValue, 1, 130, 11, 0, // Skip to: 21620 +/* 18674 */ MCD_OPC_CheckField, 0, 1, 0, 123, 11, 0, // Skip to: 21620 +/* 18681 */ MCD_OPC_Decode, 151, 18, 181, 1, // Opcode: XSXEXPDP +/* 18686 */ MCD_OPC_FilterValue, 1, 26, 0, 0, // Skip to: 18717 +/* 18691 */ MCD_OPC_CheckField, 6, 1, 1, 106, 11, 0, // Skip to: 21620 +/* 18698 */ MCD_OPC_CheckField, 2, 2, 3, 99, 11, 0, // Skip to: 21620 +/* 18705 */ MCD_OPC_CheckField, 0, 1, 0, 92, 11, 0, // Skip to: 21620 +/* 18712 */ MCD_OPC_Decode, 153, 18, 181, 1, // Opcode: XSXSIGDP +/* 18717 */ MCD_OPC_FilterValue, 16, 19, 0, 0, // Skip to: 18741 +/* 18722 */ MCD_OPC_CheckField, 6, 1, 1, 75, 11, 0, // Skip to: 21620 +/* 18729 */ MCD_OPC_CheckField, 2, 2, 3, 68, 11, 0, // Skip to: 21620 +/* 18736 */ MCD_OPC_Decode, 190, 17, 172, 1, // Opcode: XSCVHPDP +/* 18741 */ MCD_OPC_FilterValue, 17, 58, 11, 0, // Skip to: 21620 +/* 18746 */ MCD_OPC_CheckField, 6, 1, 1, 51, 11, 0, // Skip to: 21620 +/* 18753 */ MCD_OPC_CheckField, 2, 2, 3, 44, 11, 0, // Skip to: 21620 +/* 18760 */ MCD_OPC_Decode, 178, 17, 172, 1, // Opcode: XSCVDPHP +/* 18765 */ MCD_OPC_FilterValue, 11, 111, 0, 0, // Skip to: 18881 +/* 18770 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 18773 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 18815 +/* 18778 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18781 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18798 +/* 18786 */ MCD_OPC_CheckField, 16, 5, 0, 11, 11, 0, // Skip to: 21620 +/* 18793 */ MCD_OPC_Decode, 207, 17, 172, 1, // Opcode: XSCVUXDDP +/* 18798 */ MCD_OPC_FilterValue, 1, 1, 11, 0, // Skip to: 21620 +/* 18803 */ MCD_OPC_CheckField, 16, 5, 0, 250, 10, 0, // Skip to: 21620 +/* 18810 */ MCD_OPC_Decode, 203, 17, 172, 1, // Opcode: XSCVSXDDP +/* 18815 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 18857 +/* 18820 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18823 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18840 +/* 18828 */ MCD_OPC_CheckField, 16, 5, 0, 225, 10, 0, // Skip to: 21620 +/* 18835 */ MCD_OPC_Decode, 237, 17, 172, 1, // Opcode: XSNABSDP +/* 18840 */ MCD_OPC_FilterValue, 1, 215, 10, 0, // Skip to: 21620 +/* 18845 */ MCD_OPC_CheckField, 16, 5, 0, 208, 10, 0, // Skip to: 21620 +/* 18852 */ MCD_OPC_Decode, 239, 17, 172, 1, // Opcode: XSNEGDP +/* 18857 */ MCD_OPC_FilterValue, 2, 198, 10, 0, // Skip to: 21620 +/* 18862 */ MCD_OPC_CheckField, 6, 1, 0, 191, 10, 0, // Skip to: 21620 +/* 18869 */ MCD_OPC_CheckField, 0, 1, 0, 184, 10, 0, // Skip to: 21620 +/* 18876 */ MCD_OPC_Decode, 148, 18, 179, 1, // Opcode: XSTSTDCDP +/* 18881 */ MCD_OPC_FilterValue, 12, 87, 0, 0, // Skip to: 18973 +/* 18886 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 18889 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 18931 +/* 18894 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18897 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18914 +/* 18902 */ MCD_OPC_CheckField, 16, 5, 0, 151, 10, 0, // Skip to: 21620 +/* 18909 */ MCD_OPC_Decode, 190, 18, 174, 1, // Opcode: XVCVSPUXDS +/* 18914 */ MCD_OPC_FilterValue, 1, 141, 10, 0, // Skip to: 21620 +/* 18919 */ MCD_OPC_CheckField, 16, 5, 0, 134, 10, 0, // Skip to: 21620 +/* 18926 */ MCD_OPC_Decode, 188, 18, 174, 1, // Opcode: XVCVSPSXDS +/* 18931 */ MCD_OPC_FilterValue, 1, 124, 10, 0, // Skip to: 21620 +/* 18936 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18939 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 18956 +/* 18944 */ MCD_OPC_CheckField, 16, 5, 0, 109, 10, 0, // Skip to: 21620 +/* 18951 */ MCD_OPC_Decode, 179, 18, 174, 1, // Opcode: XVCVDPSP +/* 18956 */ MCD_OPC_FilterValue, 1, 99, 10, 0, // Skip to: 21620 +/* 18961 */ MCD_OPC_CheckField, 16, 5, 0, 92, 10, 0, // Skip to: 21620 +/* 18968 */ MCD_OPC_Decode, 156, 18, 174, 1, // Opcode: XVABSSP +/* 18973 */ MCD_OPC_FilterValue, 13, 105, 0, 0, // Skip to: 19083 +/* 18978 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 18981 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 19073 +/* 18986 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 18989 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 19031 +/* 18994 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 18997 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 19014 +/* 19002 */ MCD_OPC_CheckField, 16, 5, 0, 51, 10, 0, // Skip to: 21620 +/* 19009 */ MCD_OPC_Decode, 197, 18, 174, 1, // Opcode: XVCVUXDSP +/* 19014 */ MCD_OPC_FilterValue, 1, 41, 10, 0, // Skip to: 21620 +/* 19019 */ MCD_OPC_CheckField, 16, 5, 0, 34, 10, 0, // Skip to: 21620 +/* 19026 */ MCD_OPC_Decode, 193, 18, 174, 1, // Opcode: XVCVSXDSP +/* 19031 */ MCD_OPC_FilterValue, 1, 24, 10, 0, // Skip to: 21620 +/* 19036 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 19039 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 19056 +/* 19044 */ MCD_OPC_CheckField, 16, 5, 0, 9, 10, 0, // Skip to: 21620 +/* 19051 */ MCD_OPC_Decode, 243, 18, 174, 1, // Opcode: XVNABSSP +/* 19056 */ MCD_OPC_FilterValue, 1, 255, 9, 0, // Skip to: 21620 +/* 19061 */ MCD_OPC_CheckField, 16, 5, 0, 248, 9, 0, // Skip to: 21620 +/* 19068 */ MCD_OPC_Decode, 245, 18, 174, 1, // Opcode: XVNEGSP +/* 19073 */ MCD_OPC_FilterValue, 1, 238, 9, 0, // Skip to: 21620 +/* 19078 */ MCD_OPC_Decode, 150, 19, 182, 1, // Opcode: XVTSTDCSP +/* 19083 */ MCD_OPC_FilterValue, 14, 72, 1, 0, // Skip to: 19416 +/* 19088 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... +/* 19091 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 19133 +/* 19096 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 19099 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 19116 +/* 19104 */ MCD_OPC_CheckField, 16, 5, 0, 205, 9, 0, // Skip to: 21620 +/* 19111 */ MCD_OPC_Decode, 182, 18, 174, 1, // Opcode: XVCVDPUXDS +/* 19116 */ MCD_OPC_FilterValue, 1, 195, 9, 0, // Skip to: 21620 +/* 19121 */ MCD_OPC_CheckField, 16, 5, 0, 188, 9, 0, // Skip to: 21620 +/* 19128 */ MCD_OPC_Decode, 180, 18, 174, 1, // Opcode: XVCVDPSXDS +/* 19133 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 19175 +/* 19138 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 19141 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 19158 +/* 19146 */ MCD_OPC_CheckField, 16, 5, 0, 163, 9, 0, // Skip to: 21620 +/* 19153 */ MCD_OPC_Decode, 186, 18, 174, 1, // Opcode: XVCVSPDP +/* 19158 */ MCD_OPC_FilterValue, 1, 153, 9, 0, // Skip to: 21620 +/* 19163 */ MCD_OPC_CheckField, 16, 5, 0, 146, 9, 0, // Skip to: 21620 +/* 19170 */ MCD_OPC_Decode, 155, 18, 174, 1, // Opcode: XVABSDP +/* 19175 */ MCD_OPC_FilterValue, 2, 59, 0, 0, // Skip to: 19239 +/* 19180 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... +/* 19183 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 19211 +/* 19188 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 19191 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 19201 +/* 19196 */ MCD_OPC_Decode, 165, 19, 183, 1, // Opcode: XXGENPCVBM +/* 19201 */ MCD_OPC_FilterValue, 1, 110, 9, 0, // Skip to: 21620 +/* 19206 */ MCD_OPC_Decode, 168, 19, 183, 1, // Opcode: XXGENPCVWM +/* 19211 */ MCD_OPC_FilterValue, 1, 100, 9, 0, // Skip to: 21620 +/* 19216 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 19219 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 19229 +/* 19224 */ MCD_OPC_Decode, 167, 19, 183, 1, // Opcode: XXGENPCVHM +/* 19229 */ MCD_OPC_FilterValue, 1, 82, 9, 0, // Skip to: 21620 +/* 19234 */ MCD_OPC_Decode, 166, 19, 183, 1, // Opcode: XXGENPCVDM +/* 19239 */ MCD_OPC_FilterValue, 3, 72, 9, 0, // Skip to: 21620 +/* 19244 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 19247 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 19264 +/* 19252 */ MCD_OPC_CheckField, 1, 1, 0, 57, 9, 0, // Skip to: 21620 +/* 19259 */ MCD_OPC_Decode, 213, 17, 184, 1, // Opcode: XSIEXPDP +/* 19264 */ MCD_OPC_FilterValue, 1, 47, 9, 0, // Skip to: 21620 +/* 19269 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 19272 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 19282 +/* 19277 */ MCD_OPC_Decode, 151, 19, 174, 1, // Opcode: XVXEXPDP +/* 19282 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 19292 +/* 19287 */ MCD_OPC_Decode, 153, 19, 174, 1, // Opcode: XVXSIGDP +/* 19292 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 19316 +/* 19297 */ MCD_OPC_CheckField, 21, 2, 0, 12, 9, 0, // Skip to: 21620 +/* 19304 */ MCD_OPC_CheckField, 0, 1, 0, 5, 9, 0, // Skip to: 21620 +/* 19311 */ MCD_OPC_Decode, 146, 19, 175, 1, // Opcode: XVTLSBB +/* 19316 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 19326 +/* 19321 */ MCD_OPC_Decode, 160, 19, 174, 1, // Opcode: XXBRH +/* 19326 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 19336 +/* 19331 */ MCD_OPC_Decode, 152, 19, 174, 1, // Opcode: XVXEXPSP +/* 19336 */ MCD_OPC_FilterValue, 9, 5, 0, 0, // Skip to: 19346 +/* 19341 */ MCD_OPC_Decode, 154, 19, 174, 1, // Opcode: XVXSIGSP +/* 19346 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 19356 +/* 19351 */ MCD_OPC_Decode, 162, 19, 174, 1, // Opcode: XXBRW +/* 19356 */ MCD_OPC_FilterValue, 16, 5, 0, 0, // Skip to: 19366 +/* 19361 */ MCD_OPC_Decode, 178, 18, 174, 1, // Opcode: XVCVBF16SPN +/* 19366 */ MCD_OPC_FilterValue, 17, 5, 0, 0, // Skip to: 19376 +/* 19371 */ MCD_OPC_Decode, 185, 18, 174, 1, // Opcode: XVCVSPBF16 +/* 19376 */ MCD_OPC_FilterValue, 23, 5, 0, 0, // Skip to: 19386 +/* 19381 */ MCD_OPC_Decode, 159, 19, 174, 1, // Opcode: XXBRD +/* 19386 */ MCD_OPC_FilterValue, 24, 5, 0, 0, // Skip to: 19396 +/* 19391 */ MCD_OPC_Decode, 184, 18, 174, 1, // Opcode: XVCVHPSP +/* 19396 */ MCD_OPC_FilterValue, 25, 5, 0, 0, // Skip to: 19406 +/* 19401 */ MCD_OPC_Decode, 187, 18, 174, 1, // Opcode: XVCVSPHP +/* 19406 */ MCD_OPC_FilterValue, 31, 161, 8, 0, // Skip to: 21620 +/* 19411 */ MCD_OPC_Decode, 161, 19, 174, 1, // Opcode: XXBRQ +/* 19416 */ MCD_OPC_FilterValue, 15, 151, 8, 0, // Skip to: 21620 +/* 19421 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... +/* 19424 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 19516 +/* 19429 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 19432 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 19474 +/* 19437 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 19440 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 19457 +/* 19445 */ MCD_OPC_CheckField, 16, 5, 0, 120, 8, 0, // Skip to: 21620 +/* 19452 */ MCD_OPC_Decode, 196, 18, 174, 1, // Opcode: XVCVUXDDP +/* 19457 */ MCD_OPC_FilterValue, 1, 110, 8, 0, // Skip to: 21620 +/* 19462 */ MCD_OPC_CheckField, 16, 5, 0, 103, 8, 0, // Skip to: 21620 +/* 19469 */ MCD_OPC_Decode, 192, 18, 174, 1, // Opcode: XVCVSXDDP +/* 19474 */ MCD_OPC_FilterValue, 1, 93, 8, 0, // Skip to: 21620 +/* 19479 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 19482 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 19499 +/* 19487 */ MCD_OPC_CheckField, 16, 5, 0, 78, 8, 0, // Skip to: 21620 +/* 19494 */ MCD_OPC_Decode, 242, 18, 174, 1, // Opcode: XVNABSDP +/* 19499 */ MCD_OPC_FilterValue, 1, 68, 8, 0, // Skip to: 21620 +/* 19504 */ MCD_OPC_CheckField, 16, 5, 0, 61, 8, 0, // Skip to: 21620 +/* 19511 */ MCD_OPC_Decode, 244, 18, 174, 1, // Opcode: XVNEGDP +/* 19516 */ MCD_OPC_FilterValue, 1, 51, 8, 0, // Skip to: 21620 +/* 19521 */ MCD_OPC_Decode, 149, 19, 182, 1, // Opcode: XVTSTDCDP +/* 19526 */ MCD_OPC_FilterValue, 3, 41, 8, 0, // Skip to: 21620 +/* 19531 */ MCD_OPC_Decode, 192, 19, 185, 1, // Opcode: XXSEL +/* 19536 */ MCD_OPC_FilterValue, 61, 51, 0, 0, // Skip to: 19592 +/* 19541 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 19544 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 19572 +/* 19549 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 19552 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 19562 +/* 19557 */ MCD_OPC_Decode, 205, 9, 186, 1, // Opcode: LXV +/* 19562 */ MCD_OPC_FilterValue, 1, 5, 8, 0, // Skip to: 21620 +/* 19567 */ MCD_OPC_Decode, 166, 13, 186, 1, // Opcode: STXV +/* 19572 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 19582 +/* 19577 */ MCD_OPC_Decode, 157, 13, 147, 1, // Opcode: STXSD +/* 19582 */ MCD_OPC_FilterValue, 3, 241, 7, 0, // Skip to: 21620 +/* 19587 */ MCD_OPC_Decode, 164, 13, 147, 1, // Opcode: STXSSP +/* 19592 */ MCD_OPC_FilterValue, 62, 33, 0, 0, // Skip to: 19630 +/* 19597 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... +/* 19600 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 19610 +/* 19605 */ MCD_OPC_Decode, 223, 12, 148, 1, // Opcode: STD +/* 19610 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 19620 +/* 19615 */ MCD_OPC_Decode, 228, 12, 148, 1, // Opcode: STDU +/* 19620 */ MCD_OPC_FilterValue, 2, 203, 7, 0, // Skip to: 21620 +/* 19625 */ MCD_OPC_Decode, 132, 13, 187, 1, // Opcode: STQ +/* 19630 */ MCD_OPC_FilterValue, 63, 193, 7, 0, // Skip to: 21620 +/* 19635 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 19638 */ MCD_OPC_FilterValue, 0, 94, 0, 0, // Skip to: 19737 +/* 19643 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 19646 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 19663 +/* 19651 */ MCD_OPC_CheckField, 21, 2, 0, 170, 7, 0, // Skip to: 21620 +/* 19658 */ MCD_OPC_Decode, 222, 7, 188, 1, // Opcode: FCMPUS +/* 19663 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 19680 +/* 19668 */ MCD_OPC_CheckField, 21, 2, 0, 153, 7, 0, // Skip to: 21620 +/* 19675 */ MCD_OPC_Decode, 220, 7, 188, 1, // Opcode: FCMPOS +/* 19680 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 19703 +/* 19685 */ MCD_OPC_CheckField, 21, 2, 0, 136, 7, 0, // Skip to: 21620 +/* 19692 */ MCD_OPC_CheckField, 11, 7, 0, 129, 7, 0, // Skip to: 21620 +/* 19699 */ MCD_OPC_Decode, 227, 9, 51, // Opcode: MCRFS +/* 19703 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 19720 +/* 19708 */ MCD_OPC_CheckField, 21, 2, 0, 113, 7, 0, // Skip to: 21620 +/* 19715 */ MCD_OPC_Decode, 187, 8, 189, 1, // Opcode: FTDIV +/* 19720 */ MCD_OPC_FilterValue, 5, 103, 7, 0, // Skip to: 21620 +/* 19725 */ MCD_OPC_CheckField, 16, 7, 0, 96, 7, 0, // Skip to: 21620 +/* 19732 */ MCD_OPC_Decode, 188, 8, 190, 1, // Opcode: FTSQRT +/* 19737 */ MCD_OPC_FilterValue, 8, 82, 1, 0, // Skip to: 20080 +/* 19742 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 19745 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 19754 +/* 19750 */ MCD_OPC_Decode, 164, 17, 3, // Opcode: XSADDQP +/* 19754 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 19763 +/* 19759 */ MCD_OPC_Decode, 234, 17, 3, // Opcode: XSMULQP +/* 19763 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 19772 +/* 19768 */ MCD_OPC_Decode, 177, 17, 3, // Opcode: XSCPSGNQP +/* 19772 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 19788 +/* 19777 */ MCD_OPC_CheckField, 21, 2, 0, 44, 7, 0, // Skip to: 21620 +/* 19784 */ MCD_OPC_Decode, 173, 17, 6, // Opcode: XSCMPOQP +/* 19788 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 19804 +/* 19793 */ MCD_OPC_CheckField, 21, 2, 0, 28, 7, 0, // Skip to: 21620 +/* 19800 */ MCD_OPC_Decode, 169, 17, 6, // Opcode: XSCMPEXPQP +/* 19804 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 19814 +/* 19809 */ MCD_OPC_Decode, 219, 17, 191, 1, // Opcode: XSMADDQP +/* 19814 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 19824 +/* 19819 */ MCD_OPC_Decode, 231, 17, 191, 1, // Opcode: XSMSUBQP +/* 19824 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 19834 +/* 19829 */ MCD_OPC_Decode, 245, 17, 191, 1, // Opcode: XSNMADDQP +/* 19834 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 19844 +/* 19839 */ MCD_OPC_Decode, 251, 17, 191, 1, // Opcode: XSNMSUBQP +/* 19844 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 19853 +/* 19849 */ MCD_OPC_Decode, 143, 18, 3, // Opcode: XSSUBQP +/* 19853 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 19862 +/* 19858 */ MCD_OPC_Decode, 210, 17, 3, // Opcode: XSDIVQP +/* 19862 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 19878 +/* 19867 */ MCD_OPC_CheckField, 21, 2, 0, 210, 6, 0, // Skip to: 21620 +/* 19874 */ MCD_OPC_Decode, 175, 17, 6, // Opcode: XSCMPUQP +/* 19878 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 19888 +/* 19883 */ MCD_OPC_Decode, 149, 18, 192, 1, // Opcode: XSTSTDCQP +/* 19888 */ MCD_OPC_FilterValue, 25, 57, 0, 0, // Skip to: 19950 +/* 19893 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 19896 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 19905 +/* 19901 */ MCD_OPC_Decode, 162, 17, 7, // Opcode: XSABSQP +/* 19905 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 19914 +/* 19910 */ MCD_OPC_Decode, 152, 18, 7, // Opcode: XSXEXPQP +/* 19914 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 19923 +/* 19919 */ MCD_OPC_Decode, 238, 17, 7, // Opcode: XSNABSQP +/* 19923 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 19932 +/* 19928 */ MCD_OPC_Decode, 240, 17, 7, // Opcode: XSNEGQP +/* 19932 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 19941 +/* 19937 */ MCD_OPC_Decode, 154, 18, 7, // Opcode: XSXSIGQP +/* 19941 */ MCD_OPC_FilterValue, 27, 138, 6, 0, // Skip to: 21620 +/* 19946 */ MCD_OPC_Decode, 139, 18, 7, // Opcode: XSSQRTQP +/* 19950 */ MCD_OPC_FilterValue, 26, 115, 0, 0, // Skip to: 20070 +/* 19955 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 19958 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 19967 +/* 19963 */ MCD_OPC_Decode, 197, 17, 7, // Opcode: XSCVQPUQZ +/* 19967 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 19976 +/* 19972 */ MCD_OPC_Decode, 198, 17, 7, // Opcode: XSCVQPUWZ +/* 19976 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 19986 +/* 19981 */ MCD_OPC_Decode, 205, 17, 193, 1, // Opcode: XSCVUDQP +/* 19986 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 19995 +/* 19991 */ MCD_OPC_Decode, 206, 17, 7, // Opcode: XSCVUQQP +/* 19995 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 20004 +/* 20000 */ MCD_OPC_Decode, 194, 17, 7, // Opcode: XSCVQPSQZ +/* 20004 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 20013 +/* 20009 */ MCD_OPC_Decode, 195, 17, 7, // Opcode: XSCVQPSWZ +/* 20013 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 20023 +/* 20018 */ MCD_OPC_Decode, 199, 17, 193, 1, // Opcode: XSCVSDQP +/* 20023 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 20032 +/* 20028 */ MCD_OPC_Decode, 202, 17, 7, // Opcode: XSCVSQQP +/* 20032 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 20041 +/* 20037 */ MCD_OPC_Decode, 196, 17, 7, // Opcode: XSCVQPUDZ +/* 20041 */ MCD_OPC_FilterValue, 20, 5, 0, 0, // Skip to: 20051 +/* 20046 */ MCD_OPC_Decode, 191, 17, 194, 1, // Opcode: XSCVQPDP +/* 20051 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 20061 +/* 20056 */ MCD_OPC_Decode, 179, 17, 193, 1, // Opcode: XSCVDPQP +/* 20061 */ MCD_OPC_FilterValue, 25, 18, 6, 0, // Skip to: 21620 +/* 20066 */ MCD_OPC_Decode, 193, 17, 7, // Opcode: XSCVQPSDZ +/* 20070 */ MCD_OPC_FilterValue, 27, 9, 6, 0, // Skip to: 21620 +/* 20075 */ MCD_OPC_Decode, 214, 17, 195, 1, // Opcode: XSIEXPQP +/* 20080 */ MCD_OPC_FilterValue, 9, 112, 0, 0, // Skip to: 20197 +/* 20085 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 20088 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 20097 +/* 20093 */ MCD_OPC_Decode, 165, 17, 3, // Opcode: XSADDQPO +/* 20097 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 20106 +/* 20102 */ MCD_OPC_Decode, 235, 17, 3, // Opcode: XSMULQPO +/* 20106 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 20116 +/* 20111 */ MCD_OPC_Decode, 220, 17, 191, 1, // Opcode: XSMADDQPO +/* 20116 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 20126 +/* 20121 */ MCD_OPC_Decode, 232, 17, 191, 1, // Opcode: XSMSUBQPO +/* 20126 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 20136 +/* 20131 */ MCD_OPC_Decode, 246, 17, 191, 1, // Opcode: XSNMADDQPO +/* 20136 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 20146 +/* 20141 */ MCD_OPC_Decode, 252, 17, 191, 1, // Opcode: XSNMSUBQPO +/* 20146 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 20155 +/* 20151 */ MCD_OPC_Decode, 144, 18, 3, // Opcode: XSSUBQPO +/* 20155 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 20164 +/* 20160 */ MCD_OPC_Decode, 211, 17, 3, // Opcode: XSDIVQPO +/* 20164 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 20180 +/* 20169 */ MCD_OPC_CheckField, 16, 5, 27, 164, 5, 0, // Skip to: 21620 +/* 20176 */ MCD_OPC_Decode, 140, 18, 7, // Opcode: XSSQRTQPO +/* 20180 */ MCD_OPC_FilterValue, 26, 155, 5, 0, // Skip to: 21620 +/* 20185 */ MCD_OPC_CheckField, 16, 5, 20, 148, 5, 0, // Skip to: 21620 +/* 20192 */ MCD_OPC_Decode, 192, 17, 194, 1, // Opcode: XSCVQPDPO +/* 20197 */ MCD_OPC_FilterValue, 10, 37, 0, 0, // Skip to: 20239 +/* 20202 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... +/* 20205 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 20222 +/* 20210 */ MCD_OPC_CheckField, 17, 4, 0, 123, 5, 0, // Skip to: 21620 +/* 20217 */ MCD_OPC_Decode, 132, 18, 196, 1, // Opcode: XSRQPI +/* 20222 */ MCD_OPC_FilterValue, 1, 113, 5, 0, // Skip to: 21620 +/* 20227 */ MCD_OPC_CheckField, 17, 4, 0, 106, 5, 0, // Skip to: 21620 +/* 20234 */ MCD_OPC_Decode, 134, 18, 196, 1, // Opcode: XSRQPXP +/* 20239 */ MCD_OPC_FilterValue, 11, 19, 0, 0, // Skip to: 20263 +/* 20244 */ MCD_OPC_CheckField, 17, 4, 0, 89, 5, 0, // Skip to: 21620 +/* 20251 */ MCD_OPC_CheckField, 6, 3, 0, 82, 5, 0, // Skip to: 21620 +/* 20258 */ MCD_OPC_Decode, 133, 18, 196, 1, // Opcode: XSRQPIX +/* 20263 */ MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 20322 +/* 20268 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... +/* 20271 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 20288 +/* 20276 */ MCD_OPC_CheckField, 12, 9, 0, 57, 5, 0, // Skip to: 21620 +/* 20283 */ MCD_OPC_Decode, 149, 10, 134, 1, // Opcode: MTFSB1 +/* 20288 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 20305 +/* 20293 */ MCD_OPC_CheckField, 12, 9, 0, 40, 5, 0, // Skip to: 21620 +/* 20300 */ MCD_OPC_Decode, 148, 10, 134, 1, // Opcode: MTFSB0 +/* 20305 */ MCD_OPC_FilterValue, 4, 30, 5, 0, // Skip to: 21620 +/* 20310 */ MCD_OPC_CheckField, 17, 6, 0, 23, 5, 0, // Skip to: 21620 +/* 20317 */ MCD_OPC_Decode, 151, 10, 197, 1, // Opcode: MTFSFI +/* 20322 */ MCD_OPC_FilterValue, 13, 19, 0, 0, // Skip to: 20346 +/* 20327 */ MCD_OPC_CheckField, 17, 6, 0, 6, 5, 0, // Skip to: 21620 +/* 20334 */ MCD_OPC_CheckField, 6, 6, 4, 255, 4, 0, // Skip to: 21620 +/* 20341 */ MCD_OPC_Decode, 152, 10, 197, 1, // Opcode: MTFSFI_rec +/* 20346 */ MCD_OPC_FilterValue, 14, 126, 0, 0, // Skip to: 20477 +/* 20351 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 20354 */ MCD_OPC_FilterValue, 18, 108, 0, 0, // Skip to: 20467 +/* 20359 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 20362 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 20379 +/* 20367 */ MCD_OPC_CheckField, 11, 5, 0, 222, 4, 0, // Skip to: 21620 +/* 20374 */ MCD_OPC_Decode, 235, 9, 198, 1, // Opcode: MFFS +/* 20379 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 20396 +/* 20384 */ MCD_OPC_CheckField, 11, 5, 0, 205, 4, 0, // Skip to: 21620 +/* 20391 */ MCD_OPC_Decode, 238, 9, 198, 1, // Opcode: MFFSCE +/* 20396 */ MCD_OPC_FilterValue, 20, 5, 0, 0, // Skip to: 20406 +/* 20401 */ MCD_OPC_Decode, 236, 9, 199, 1, // Opcode: MFFSCDRN +/* 20406 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 20423 +/* 20411 */ MCD_OPC_CheckField, 14, 2, 0, 178, 4, 0, // Skip to: 21620 +/* 20418 */ MCD_OPC_Decode, 237, 9, 200, 1, // Opcode: MFFSCDRNI +/* 20423 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 20433 +/* 20428 */ MCD_OPC_Decode, 239, 9, 199, 1, // Opcode: MFFSCRN +/* 20433 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 20450 +/* 20438 */ MCD_OPC_CheckField, 13, 3, 0, 151, 4, 0, // Skip to: 21620 +/* 20445 */ MCD_OPC_Decode, 240, 9, 201, 1, // Opcode: MFFSCRNI +/* 20450 */ MCD_OPC_FilterValue, 24, 141, 4, 0, // Skip to: 21620 +/* 20455 */ MCD_OPC_CheckField, 11, 5, 0, 134, 4, 0, // Skip to: 21620 +/* 20462 */ MCD_OPC_Decode, 241, 9, 198, 1, // Opcode: MFFSL +/* 20467 */ MCD_OPC_FilterValue, 22, 124, 4, 0, // Skip to: 21620 +/* 20472 */ MCD_OPC_Decode, 150, 10, 202, 1, // Opcode: MTFSF +/* 20477 */ MCD_OPC_FilterValue, 15, 30, 0, 0, // Skip to: 20512 +/* 20482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 20485 */ MCD_OPC_FilterValue, 18, 12, 0, 0, // Skip to: 20502 +/* 20490 */ MCD_OPC_CheckField, 11, 10, 0, 99, 4, 0, // Skip to: 21620 +/* 20497 */ MCD_OPC_Decode, 242, 9, 198, 1, // Opcode: MFFS_rec +/* 20502 */ MCD_OPC_FilterValue, 22, 89, 4, 0, // Skip to: 21620 +/* 20507 */ MCD_OPC_Decode, 154, 10, 202, 1, // Opcode: MTFSF_rec +/* 20512 */ MCD_OPC_FilterValue, 16, 149, 0, 0, // Skip to: 20666 +/* 20517 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 20520 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 20530 +/* 20525 */ MCD_OPC_Decode, 225, 7, 154, 1, // Opcode: FCPSGNS +/* 20530 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 20547 +/* 20535 */ MCD_OPC_CheckField, 16, 5, 0, 54, 4, 0, // Skip to: 21620 +/* 20542 */ MCD_OPC_Decode, 139, 8, 155, 1, // Opcode: FNEGS +/* 20547 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 20564 +/* 20552 */ MCD_OPC_CheckField, 16, 5, 0, 37, 4, 0, // Skip to: 21620 +/* 20559 */ MCD_OPC_Decode, 251, 7, 155, 1, // Opcode: FMR +/* 20564 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 20581 +/* 20569 */ MCD_OPC_CheckField, 16, 5, 0, 20, 4, 0, // Skip to: 21620 +/* 20576 */ MCD_OPC_Decode, 135, 8, 155, 1, // Opcode: FNABSS +/* 20581 */ MCD_OPC_FilterValue, 8, 12, 0, 0, // Skip to: 20598 +/* 20586 */ MCD_OPC_CheckField, 16, 5, 0, 3, 4, 0, // Skip to: 21620 +/* 20593 */ MCD_OPC_Decode, 204, 7, 155, 1, // Opcode: FABSS +/* 20598 */ MCD_OPC_FilterValue, 12, 12, 0, 0, // Skip to: 20615 +/* 20603 */ MCD_OPC_CheckField, 16, 5, 0, 242, 3, 0, // Skip to: 21620 +/* 20610 */ MCD_OPC_Decode, 159, 8, 155, 1, // Opcode: FRINS +/* 20615 */ MCD_OPC_FilterValue, 13, 12, 0, 0, // Skip to: 20632 +/* 20620 */ MCD_OPC_CheckField, 16, 5, 0, 225, 3, 0, // Skip to: 21620 +/* 20627 */ MCD_OPC_Decode, 167, 8, 155, 1, // Opcode: FRIZS +/* 20632 */ MCD_OPC_FilterValue, 14, 12, 0, 0, // Skip to: 20649 +/* 20637 */ MCD_OPC_CheckField, 16, 5, 0, 208, 3, 0, // Skip to: 21620 +/* 20644 */ MCD_OPC_Decode, 163, 8, 155, 1, // Opcode: FRIPS +/* 20649 */ MCD_OPC_FilterValue, 15, 198, 3, 0, // Skip to: 21620 +/* 20654 */ MCD_OPC_CheckField, 16, 5, 0, 191, 3, 0, // Skip to: 21620 +/* 20661 */ MCD_OPC_Decode, 155, 8, 155, 1, // Opcode: FRIMS +/* 20666 */ MCD_OPC_FilterValue, 17, 149, 0, 0, // Skip to: 20820 +/* 20671 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 20674 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 20684 +/* 20679 */ MCD_OPC_Decode, 226, 7, 154, 1, // Opcode: FCPSGNS_rec +/* 20684 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 20701 +/* 20689 */ MCD_OPC_CheckField, 16, 5, 0, 156, 3, 0, // Skip to: 21620 +/* 20696 */ MCD_OPC_Decode, 140, 8, 155, 1, // Opcode: FNEGS_rec +/* 20701 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 20718 +/* 20706 */ MCD_OPC_CheckField, 16, 5, 0, 139, 3, 0, // Skip to: 21620 +/* 20713 */ MCD_OPC_Decode, 252, 7, 155, 1, // Opcode: FMR_rec +/* 20718 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 20735 +/* 20723 */ MCD_OPC_CheckField, 16, 5, 0, 122, 3, 0, // Skip to: 21620 +/* 20730 */ MCD_OPC_Decode, 136, 8, 155, 1, // Opcode: FNABSS_rec +/* 20735 */ MCD_OPC_FilterValue, 8, 12, 0, 0, // Skip to: 20752 +/* 20740 */ MCD_OPC_CheckField, 16, 5, 0, 105, 3, 0, // Skip to: 21620 +/* 20747 */ MCD_OPC_Decode, 205, 7, 155, 1, // Opcode: FABSS_rec +/* 20752 */ MCD_OPC_FilterValue, 12, 12, 0, 0, // Skip to: 20769 +/* 20757 */ MCD_OPC_CheckField, 16, 5, 0, 88, 3, 0, // Skip to: 21620 +/* 20764 */ MCD_OPC_Decode, 160, 8, 155, 1, // Opcode: FRINS_rec +/* 20769 */ MCD_OPC_FilterValue, 13, 12, 0, 0, // Skip to: 20786 +/* 20774 */ MCD_OPC_CheckField, 16, 5, 0, 71, 3, 0, // Skip to: 21620 +/* 20781 */ MCD_OPC_Decode, 168, 8, 155, 1, // Opcode: FRIZS_rec +/* 20786 */ MCD_OPC_FilterValue, 14, 12, 0, 0, // Skip to: 20803 +/* 20791 */ MCD_OPC_CheckField, 16, 5, 0, 54, 3, 0, // Skip to: 21620 +/* 20798 */ MCD_OPC_Decode, 164, 8, 155, 1, // Opcode: FRIPS_rec +/* 20803 */ MCD_OPC_FilterValue, 15, 44, 3, 0, // Skip to: 21620 +/* 20808 */ MCD_OPC_CheckField, 16, 5, 0, 37, 3, 0, // Skip to: 21620 +/* 20815 */ MCD_OPC_Decode, 156, 8, 155, 1, // Opcode: FRIMS_rec +/* 20820 */ MCD_OPC_FilterValue, 24, 19, 0, 0, // Skip to: 20844 +/* 20825 */ MCD_OPC_CheckField, 16, 5, 0, 20, 3, 0, // Skip to: 21620 +/* 20832 */ MCD_OPC_CheckField, 6, 5, 0, 13, 3, 0, // Skip to: 21620 +/* 20839 */ MCD_OPC_Decode, 169, 8, 153, 1, // Opcode: FRSP +/* 20844 */ MCD_OPC_FilterValue, 25, 19, 0, 0, // Skip to: 20868 +/* 20849 */ MCD_OPC_CheckField, 16, 5, 0, 252, 2, 0, // Skip to: 21620 +/* 20856 */ MCD_OPC_CheckField, 6, 5, 0, 245, 2, 0, // Skip to: 21620 +/* 20863 */ MCD_OPC_Decode, 170, 8, 153, 1, // Opcode: FRSP_rec +/* 20868 */ MCD_OPC_FilterValue, 28, 105, 0, 0, // Skip to: 20978 +/* 20873 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 20876 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 20893 +/* 20881 */ MCD_OPC_CheckField, 16, 5, 0, 220, 2, 0, // Skip to: 21620 +/* 20888 */ MCD_OPC_Decode, 235, 7, 199, 1, // Opcode: FCTIW +/* 20893 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 20910 +/* 20898 */ MCD_OPC_CheckField, 16, 5, 0, 203, 2, 0, // Skip to: 21620 +/* 20905 */ MCD_OPC_Decode, 236, 7, 199, 1, // Opcode: FCTIWU +/* 20910 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 20927 +/* 20915 */ MCD_OPC_CheckField, 16, 5, 0, 186, 2, 0, // Skip to: 21620 +/* 20922 */ MCD_OPC_Decode, 227, 7, 199, 1, // Opcode: FCTID +/* 20927 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 20944 +/* 20932 */ MCD_OPC_CheckField, 16, 5, 0, 169, 2, 0, // Skip to: 21620 +/* 20939 */ MCD_OPC_Decode, 211, 7, 199, 1, // Opcode: FCFID +/* 20944 */ MCD_OPC_FilterValue, 29, 12, 0, 0, // Skip to: 20961 +/* 20949 */ MCD_OPC_CheckField, 16, 5, 0, 152, 2, 0, // Skip to: 21620 +/* 20956 */ MCD_OPC_Decode, 228, 7, 199, 1, // Opcode: FCTIDU +/* 20961 */ MCD_OPC_FilterValue, 30, 142, 2, 0, // Skip to: 21620 +/* 20966 */ MCD_OPC_CheckField, 16, 5, 0, 135, 2, 0, // Skip to: 21620 +/* 20973 */ MCD_OPC_Decode, 214, 7, 199, 1, // Opcode: FCFIDU +/* 20978 */ MCD_OPC_FilterValue, 29, 105, 0, 0, // Skip to: 21088 +/* 20983 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 20986 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 21003 +/* 20991 */ MCD_OPC_CheckField, 16, 5, 0, 110, 2, 0, // Skip to: 21620 +/* 20998 */ MCD_OPC_Decode, 242, 7, 199, 1, // Opcode: FCTIW_rec +/* 21003 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 21020 +/* 21008 */ MCD_OPC_CheckField, 16, 5, 0, 93, 2, 0, // Skip to: 21620 +/* 21015 */ MCD_OPC_Decode, 239, 7, 199, 1, // Opcode: FCTIWU_rec +/* 21020 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 21037 +/* 21025 */ MCD_OPC_CheckField, 16, 5, 0, 76, 2, 0, // Skip to: 21620 +/* 21032 */ MCD_OPC_Decode, 234, 7, 199, 1, // Opcode: FCTID_rec +/* 21037 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 21054 +/* 21042 */ MCD_OPC_CheckField, 16, 5, 0, 59, 2, 0, // Skip to: 21620 +/* 21049 */ MCD_OPC_Decode, 218, 7, 199, 1, // Opcode: FCFID_rec +/* 21054 */ MCD_OPC_FilterValue, 29, 12, 0, 0, // Skip to: 21071 +/* 21059 */ MCD_OPC_CheckField, 16, 5, 0, 42, 2, 0, // Skip to: 21620 +/* 21066 */ MCD_OPC_Decode, 231, 7, 199, 1, // Opcode: FCTIDU_rec +/* 21071 */ MCD_OPC_FilterValue, 30, 32, 2, 0, // Skip to: 21620 +/* 21076 */ MCD_OPC_CheckField, 16, 5, 0, 25, 2, 0, // Skip to: 21620 +/* 21083 */ MCD_OPC_Decode, 217, 7, 199, 1, // Opcode: FCFIDU_rec +/* 21088 */ MCD_OPC_FilterValue, 30, 71, 0, 0, // Skip to: 21164 +/* 21093 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 21096 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 21113 +/* 21101 */ MCD_OPC_CheckField, 16, 5, 0, 0, 2, 0, // Skip to: 21620 +/* 21108 */ MCD_OPC_Decode, 240, 7, 199, 1, // Opcode: FCTIWZ +/* 21113 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 21130 +/* 21118 */ MCD_OPC_CheckField, 16, 5, 0, 239, 1, 0, // Skip to: 21620 +/* 21125 */ MCD_OPC_Decode, 237, 7, 199, 1, // Opcode: FCTIWUZ +/* 21130 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 21147 +/* 21135 */ MCD_OPC_CheckField, 16, 5, 0, 222, 1, 0, // Skip to: 21620 +/* 21142 */ MCD_OPC_Decode, 232, 7, 199, 1, // Opcode: FCTIDZ +/* 21147 */ MCD_OPC_FilterValue, 29, 212, 1, 0, // Skip to: 21620 +/* 21152 */ MCD_OPC_CheckField, 16, 5, 0, 205, 1, 0, // Skip to: 21620 +/* 21159 */ MCD_OPC_Decode, 229, 7, 199, 1, // Opcode: FCTIDUZ +/* 21164 */ MCD_OPC_FilterValue, 31, 71, 0, 0, // Skip to: 21240 +/* 21169 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 21172 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 21189 +/* 21177 */ MCD_OPC_CheckField, 16, 5, 0, 180, 1, 0, // Skip to: 21620 +/* 21184 */ MCD_OPC_Decode, 241, 7, 199, 1, // Opcode: FCTIWZ_rec +/* 21189 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 21206 +/* 21194 */ MCD_OPC_CheckField, 16, 5, 0, 163, 1, 0, // Skip to: 21620 +/* 21201 */ MCD_OPC_Decode, 238, 7, 199, 1, // Opcode: FCTIWUZ_rec +/* 21206 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 21223 +/* 21211 */ MCD_OPC_CheckField, 16, 5, 0, 146, 1, 0, // Skip to: 21620 +/* 21218 */ MCD_OPC_Decode, 233, 7, 199, 1, // Opcode: FCTIDZ_rec +/* 21223 */ MCD_OPC_FilterValue, 29, 136, 1, 0, // Skip to: 21620 +/* 21228 */ MCD_OPC_CheckField, 16, 5, 0, 129, 1, 0, // Skip to: 21620 +/* 21235 */ MCD_OPC_Decode, 230, 7, 199, 1, // Opcode: FCTIDUZ_rec +/* 21240 */ MCD_OPC_FilterValue, 36, 12, 0, 0, // Skip to: 21257 +/* 21245 */ MCD_OPC_CheckField, 6, 5, 0, 112, 1, 0, // Skip to: 21620 +/* 21252 */ MCD_OPC_Decode, 243, 7, 203, 1, // Opcode: FDIV +/* 21257 */ MCD_OPC_FilterValue, 37, 12, 0, 0, // Skip to: 21274 +/* 21262 */ MCD_OPC_CheckField, 6, 5, 0, 95, 1, 0, // Skip to: 21620 +/* 21269 */ MCD_OPC_Decode, 246, 7, 203, 1, // Opcode: FDIV_rec +/* 21274 */ MCD_OPC_FilterValue, 40, 12, 0, 0, // Skip to: 21291 +/* 21279 */ MCD_OPC_CheckField, 6, 5, 0, 78, 1, 0, // Skip to: 21620 +/* 21286 */ MCD_OPC_Decode, 183, 8, 203, 1, // Opcode: FSUB +/* 21291 */ MCD_OPC_FilterValue, 41, 12, 0, 0, // Skip to: 21308 +/* 21296 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, 0, // Skip to: 21620 +/* 21303 */ MCD_OPC_Decode, 186, 8, 203, 1, // Opcode: FSUB_rec +/* 21308 */ MCD_OPC_FilterValue, 42, 12, 0, 0, // Skip to: 21325 +/* 21313 */ MCD_OPC_CheckField, 6, 5, 0, 44, 1, 0, // Skip to: 21620 +/* 21320 */ MCD_OPC_Decode, 206, 7, 203, 1, // Opcode: FADD +/* 21325 */ MCD_OPC_FilterValue, 43, 12, 0, 0, // Skip to: 21342 +/* 21330 */ MCD_OPC_CheckField, 6, 5, 0, 27, 1, 0, // Skip to: 21620 +/* 21337 */ MCD_OPC_Decode, 209, 7, 203, 1, // Opcode: FADD_rec +/* 21342 */ MCD_OPC_FilterValue, 44, 19, 0, 0, // Skip to: 21366 +/* 21347 */ MCD_OPC_CheckField, 16, 5, 0, 10, 1, 0, // Skip to: 21620 +/* 21354 */ MCD_OPC_CheckField, 6, 5, 0, 3, 1, 0, // Skip to: 21620 +/* 21361 */ MCD_OPC_Decode, 179, 8, 199, 1, // Opcode: FSQRT +/* 21366 */ MCD_OPC_FilterValue, 45, 19, 0, 0, // Skip to: 21390 +/* 21371 */ MCD_OPC_CheckField, 16, 5, 0, 242, 0, 0, // Skip to: 21620 +/* 21378 */ MCD_OPC_CheckField, 6, 5, 0, 235, 0, 0, // Skip to: 21620 +/* 21385 */ MCD_OPC_Decode, 182, 8, 199, 1, // Opcode: FSQRT_rec +/* 21390 */ MCD_OPC_FilterValue, 46, 5, 0, 0, // Skip to: 21400 +/* 21395 */ MCD_OPC_Decode, 177, 8, 204, 1, // Opcode: FSELS +/* 21400 */ MCD_OPC_FilterValue, 47, 5, 0, 0, // Skip to: 21410 +/* 21405 */ MCD_OPC_Decode, 178, 8, 204, 1, // Opcode: FSELS_rec +/* 21410 */ MCD_OPC_FilterValue, 48, 19, 0, 0, // Skip to: 21434 +/* 21415 */ MCD_OPC_CheckField, 16, 5, 0, 198, 0, 0, // Skip to: 21620 +/* 21422 */ MCD_OPC_CheckField, 6, 5, 0, 191, 0, 0, // Skip to: 21620 +/* 21429 */ MCD_OPC_Decode, 149, 8, 199, 1, // Opcode: FRE +/* 21434 */ MCD_OPC_FilterValue, 49, 19, 0, 0, // Skip to: 21458 +/* 21439 */ MCD_OPC_CheckField, 16, 5, 0, 174, 0, 0, // Skip to: 21620 +/* 21446 */ MCD_OPC_CheckField, 6, 5, 0, 167, 0, 0, // Skip to: 21620 +/* 21453 */ MCD_OPC_Decode, 152, 8, 199, 1, // Opcode: FRE_rec +/* 21458 */ MCD_OPC_FilterValue, 50, 12, 0, 0, // Skip to: 21475 +/* 21463 */ MCD_OPC_CheckField, 11, 5, 0, 150, 0, 0, // Skip to: 21620 +/* 21470 */ MCD_OPC_Decode, 129, 8, 205, 1, // Opcode: FMUL +/* 21475 */ MCD_OPC_FilterValue, 51, 12, 0, 0, // Skip to: 21492 +/* 21480 */ MCD_OPC_CheckField, 11, 5, 0, 133, 0, 0, // Skip to: 21620 +/* 21487 */ MCD_OPC_Decode, 132, 8, 205, 1, // Opcode: FMUL_rec +/* 21492 */ MCD_OPC_FilterValue, 52, 19, 0, 0, // Skip to: 21516 +/* 21497 */ MCD_OPC_CheckField, 16, 5, 0, 116, 0, 0, // Skip to: 21620 +/* 21504 */ MCD_OPC_CheckField, 6, 5, 0, 109, 0, 0, // Skip to: 21620 +/* 21511 */ MCD_OPC_Decode, 171, 8, 199, 1, // Opcode: FRSQRTE +/* 21516 */ MCD_OPC_FilterValue, 53, 19, 0, 0, // Skip to: 21540 +/* 21521 */ MCD_OPC_CheckField, 16, 5, 0, 92, 0, 0, // Skip to: 21620 +/* 21528 */ MCD_OPC_CheckField, 6, 5, 0, 85, 0, 0, // Skip to: 21620 +/* 21535 */ MCD_OPC_Decode, 174, 8, 199, 1, // Opcode: FRSQRTE_rec +/* 21540 */ MCD_OPC_FilterValue, 56, 5, 0, 0, // Skip to: 21550 +/* 21545 */ MCD_OPC_Decode, 253, 7, 206, 1, // Opcode: FMSUB +/* 21550 */ MCD_OPC_FilterValue, 57, 5, 0, 0, // Skip to: 21560 +/* 21555 */ MCD_OPC_Decode, 128, 8, 206, 1, // Opcode: FMSUB_rec +/* 21560 */ MCD_OPC_FilterValue, 58, 5, 0, 0, // Skip to: 21570 +/* 21565 */ MCD_OPC_Decode, 247, 7, 206, 1, // Opcode: FMADD +/* 21570 */ MCD_OPC_FilterValue, 59, 5, 0, 0, // Skip to: 21580 +/* 21575 */ MCD_OPC_Decode, 250, 7, 206, 1, // Opcode: FMADD_rec +/* 21580 */ MCD_OPC_FilterValue, 60, 5, 0, 0, // Skip to: 21590 +/* 21585 */ MCD_OPC_Decode, 145, 8, 206, 1, // Opcode: FNMSUB +/* 21590 */ MCD_OPC_FilterValue, 61, 5, 0, 0, // Skip to: 21600 +/* 21595 */ MCD_OPC_Decode, 148, 8, 206, 1, // Opcode: FNMSUB_rec +/* 21600 */ MCD_OPC_FilterValue, 62, 5, 0, 0, // Skip to: 21610 +/* 21605 */ MCD_OPC_Decode, 141, 8, 206, 1, // Opcode: FNMADD +/* 21610 */ MCD_OPC_FilterValue, 63, 5, 0, 0, // Skip to: 21620 +/* 21615 */ MCD_OPC_Decode, 144, 8, 206, 1, // Opcode: FNMADD_rec +/* 21620 */ MCD_OPC_Fail, 0 }; -static const uint8_t DecoderTableQPX32[] = { -/* 0 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... -/* 3 */ MCD_OPC_FilterValue, 0, 71, 0, 0, // Skip to: 79 -/* 8 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 11 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 28 -/* 16 */ MCD_OPC_CheckField, 26, 6, 4, 186, 8, 0, // Skip to: 2257 -/* 23 */ MCD_OPC_Decode, 162, 9, 177, 1, // Opcode: QVFCMPEQb -/* 28 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 45 -/* 33 */ MCD_OPC_CheckField, 26, 6, 4, 169, 8, 0, // Skip to: 2257 -/* 40 */ MCD_OPC_Decode, 165, 9, 177, 1, // Opcode: QVFCMPGTb -/* 45 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 62 -/* 50 */ MCD_OPC_CheckField, 26, 6, 4, 152, 8, 0, // Skip to: 2257 -/* 57 */ MCD_OPC_Decode, 232, 9, 177, 1, // Opcode: QVFTSTNANb -/* 62 */ MCD_OPC_FilterValue, 3, 142, 8, 0, // Skip to: 2257 -/* 67 */ MCD_OPC_CheckField, 26, 6, 4, 135, 8, 0, // Skip to: 2257 -/* 74 */ MCD_OPC_Decode, 168, 9, 177, 1, // Opcode: QVFCMPLTb -/* 79 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 107 -/* 84 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 87 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 97 -/* 92 */ MCD_OPC_Decode, 241, 9, 178, 1, // Opcode: QVFXXMADDS -/* 97 */ MCD_OPC_FilterValue, 4, 107, 8, 0, // Skip to: 2257 -/* 102 */ MCD_OPC_Decode, 240, 9, 178, 1, // Opcode: QVFXXMADD -/* 107 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 135 -/* 112 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 115 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 125 -/* 120 */ MCD_OPC_Decode, 239, 9, 178, 1, // Opcode: QVFXXCPNMADDS -/* 125 */ MCD_OPC_FilterValue, 4, 79, 8, 0, // Skip to: 2257 -/* 130 */ MCD_OPC_Decode, 238, 9, 178, 1, // Opcode: QVFXXCPNMADD -/* 135 */ MCD_OPC_FilterValue, 8, 19, 0, 0, // Skip to: 159 -/* 140 */ MCD_OPC_CheckField, 26, 6, 4, 62, 8, 0, // Skip to: 2257 -/* 147 */ MCD_OPC_CheckField, 6, 1, 0, 55, 8, 0, // Skip to: 2257 -/* 154 */ MCD_OPC_Decode, 182, 9, 179, 1, // Opcode: QVFLOGICALb -/* 159 */ MCD_OPC_FilterValue, 10, 216, 0, 0, // Skip to: 380 -/* 164 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... -/* 167 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 184 -/* 172 */ MCD_OPC_CheckField, 26, 6, 4, 30, 8, 0, // Skip to: 2257 -/* 179 */ MCD_OPC_Decode, 145, 9, 180, 1, // Opcode: QVALIGNI -/* 184 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 208 -/* 189 */ MCD_OPC_CheckField, 26, 6, 4, 13, 8, 0, // Skip to: 2257 -/* 196 */ MCD_OPC_CheckField, 11, 5, 0, 6, 8, 0, // Skip to: 2257 -/* 203 */ MCD_OPC_Decode, 148, 9, 181, 1, // Opcode: QVESPLATI -/* 208 */ MCD_OPC_FilterValue, 4, 41, 0, 0, // Skip to: 254 -/* 213 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 216 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 226 -/* 221 */ MCD_OPC_Decode, 244, 9, 182, 1, // Opcode: QVGPCI -/* 226 */ MCD_OPC_FilterValue, 31, 234, 7, 0, // Skip to: 2257 -/* 231 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 234 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 244 -/* 239 */ MCD_OPC_Decode, 160, 10, 183, 1, // Opcode: QVSTFCSXI -/* 244 */ MCD_OPC_FilterValue, 2, 216, 7, 0, // Skip to: 2257 -/* 249 */ MCD_OPC_Decode, 181, 10, 183, 1, // Opcode: QVSTFSXI -/* 254 */ MCD_OPC_FilterValue, 5, 37, 0, 0, // Skip to: 296 -/* 259 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 262 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 279 -/* 267 */ MCD_OPC_CheckField, 26, 6, 31, 191, 7, 0, // Skip to: 2257 -/* 274 */ MCD_OPC_Decode, 156, 10, 183, 1, // Opcode: QVSTFCSUXI -/* 279 */ MCD_OPC_FilterValue, 2, 181, 7, 0, // Skip to: 2257 -/* 284 */ MCD_OPC_CheckField, 26, 6, 31, 174, 7, 0, // Skip to: 2257 -/* 291 */ MCD_OPC_Decode, 176, 10, 183, 1, // Opcode: QVSTFSUXI -/* 296 */ MCD_OPC_FilterValue, 6, 37, 0, 0, // Skip to: 338 -/* 301 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 304 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 321 -/* 309 */ MCD_OPC_CheckField, 26, 6, 31, 149, 7, 0, // Skip to: 2257 -/* 316 */ MCD_OPC_Decode, 152, 10, 183, 1, // Opcode: QVSTFCDXI -/* 321 */ MCD_OPC_FilterValue, 2, 139, 7, 0, // Skip to: 2257 -/* 326 */ MCD_OPC_CheckField, 26, 6, 31, 132, 7, 0, // Skip to: 2257 -/* 333 */ MCD_OPC_Decode, 169, 10, 183, 1, // Opcode: QVSTFDXI -/* 338 */ MCD_OPC_FilterValue, 7, 122, 7, 0, // Skip to: 2257 -/* 343 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... -/* 346 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 363 -/* 351 */ MCD_OPC_CheckField, 26, 6, 31, 107, 7, 0, // Skip to: 2257 -/* 358 */ MCD_OPC_Decode, 148, 10, 183, 1, // Opcode: QVSTFCDUXI -/* 363 */ MCD_OPC_FilterValue, 2, 97, 7, 0, // Skip to: 2257 -/* 368 */ MCD_OPC_CheckField, 26, 6, 31, 90, 7, 0, // Skip to: 2257 -/* 375 */ MCD_OPC_Decode, 165, 10, 183, 1, // Opcode: QVSTFDUXI -/* 380 */ MCD_OPC_FilterValue, 11, 139, 0, 0, // Skip to: 524 -/* 385 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 388 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 405 -/* 393 */ MCD_OPC_CheckField, 26, 6, 31, 65, 7, 0, // Skip to: 2257 -/* 400 */ MCD_OPC_Decode, 161, 10, 183, 1, // Opcode: QVSTFCSXIA -/* 405 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 422 -/* 410 */ MCD_OPC_CheckField, 26, 6, 31, 48, 7, 0, // Skip to: 2257 -/* 417 */ MCD_OPC_Decode, 157, 10, 183, 1, // Opcode: QVSTFCSUXIA -/* 422 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 439 -/* 427 */ MCD_OPC_CheckField, 26, 6, 31, 31, 7, 0, // Skip to: 2257 -/* 434 */ MCD_OPC_Decode, 153, 10, 183, 1, // Opcode: QVSTFCDXIA -/* 439 */ MCD_OPC_FilterValue, 7, 12, 0, 0, // Skip to: 456 -/* 444 */ MCD_OPC_CheckField, 26, 6, 31, 14, 7, 0, // Skip to: 2257 -/* 451 */ MCD_OPC_Decode, 149, 10, 183, 1, // Opcode: QVSTFCDUXIA -/* 456 */ MCD_OPC_FilterValue, 20, 12, 0, 0, // Skip to: 473 -/* 461 */ MCD_OPC_CheckField, 26, 6, 31, 253, 6, 0, // Skip to: 2257 -/* 468 */ MCD_OPC_Decode, 182, 10, 183, 1, // Opcode: QVSTFSXIA -/* 473 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 490 -/* 478 */ MCD_OPC_CheckField, 26, 6, 31, 236, 6, 0, // Skip to: 2257 -/* 485 */ MCD_OPC_Decode, 177, 10, 183, 1, // Opcode: QVSTFSUXIA -/* 490 */ MCD_OPC_FilterValue, 22, 12, 0, 0, // Skip to: 507 -/* 495 */ MCD_OPC_CheckField, 26, 6, 31, 219, 6, 0, // Skip to: 2257 -/* 502 */ MCD_OPC_Decode, 170, 10, 183, 1, // Opcode: QVSTFDXIA -/* 507 */ MCD_OPC_FilterValue, 23, 209, 6, 0, // Skip to: 2257 -/* 512 */ MCD_OPC_CheckField, 26, 6, 31, 202, 6, 0, // Skip to: 2257 -/* 519 */ MCD_OPC_Decode, 166, 10, 183, 1, // Opcode: QVSTFDUXIA -/* 524 */ MCD_OPC_FilterValue, 12, 61, 0, 0, // Skip to: 590 -/* 529 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 532 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 542 -/* 537 */ MCD_OPC_Decode, 206, 9, 178, 1, // Opcode: QVFPERM -/* 542 */ MCD_OPC_FilterValue, 31, 174, 6, 0, // Skip to: 2257 -/* 547 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 550 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 560 -/* 555 */ MCD_OPC_Decode, 145, 10, 183, 1, // Opcode: QVLPCRSX -/* 560 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 570 -/* 565 */ MCD_OPC_Decode, 144, 10, 183, 1, // Opcode: QVLPCRDX -/* 570 */ MCD_OPC_FilterValue, 16, 5, 0, 0, // Skip to: 580 -/* 575 */ MCD_OPC_Decode, 142, 10, 183, 1, // Opcode: QVLPCLSX -/* 580 */ MCD_OPC_FilterValue, 18, 136, 6, 0, // Skip to: 2257 -/* 585 */ MCD_OPC_Decode, 141, 10, 183, 1, // Opcode: QVLPCLDX -/* 590 */ MCD_OPC_FilterValue, 14, 70, 1, 0, // Skip to: 921 -/* 595 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 598 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 615 -/* 603 */ MCD_OPC_CheckField, 26, 6, 31, 111, 6, 0, // Skip to: 2257 -/* 610 */ MCD_OPC_Decode, 251, 9, 183, 1, // Opcode: QVLFCSX -/* 615 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 632 -/* 620 */ MCD_OPC_CheckField, 26, 6, 31, 94, 6, 0, // Skip to: 2257 -/* 627 */ MCD_OPC_Decode, 249, 9, 183, 1, // Opcode: QVLFCSUX -/* 632 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 649 -/* 637 */ MCD_OPC_CheckField, 26, 6, 31, 77, 6, 0, // Skip to: 2257 -/* 644 */ MCD_OPC_Decode, 247, 9, 183, 1, // Opcode: QVLFCDX -/* 649 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 666 -/* 654 */ MCD_OPC_CheckField, 26, 6, 31, 60, 6, 0, // Skip to: 2257 -/* 661 */ MCD_OPC_Decode, 245, 9, 183, 1, // Opcode: QVLFCDUX -/* 666 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 683 -/* 671 */ MCD_OPC_CheckField, 26, 6, 31, 43, 6, 0, // Skip to: 2257 -/* 678 */ MCD_OPC_Decode, 158, 10, 183, 1, // Opcode: QVSTFCSX -/* 683 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 700 -/* 688 */ MCD_OPC_CheckField, 26, 6, 31, 26, 6, 0, // Skip to: 2257 -/* 695 */ MCD_OPC_Decode, 154, 10, 183, 1, // Opcode: QVSTFCSUX -/* 700 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 717 -/* 705 */ MCD_OPC_CheckField, 26, 6, 31, 9, 6, 0, // Skip to: 2257 -/* 712 */ MCD_OPC_Decode, 150, 10, 183, 1, // Opcode: QVSTFCDX -/* 717 */ MCD_OPC_FilterValue, 7, 12, 0, 0, // Skip to: 734 -/* 722 */ MCD_OPC_CheckField, 26, 6, 31, 248, 5, 0, // Skip to: 2257 -/* 729 */ MCD_OPC_Decode, 146, 10, 183, 1, // Opcode: QVSTFCDUX -/* 734 */ MCD_OPC_FilterValue, 16, 12, 0, 0, // Skip to: 751 -/* 739 */ MCD_OPC_CheckField, 26, 6, 31, 231, 5, 0, // Skip to: 2257 -/* 746 */ MCD_OPC_Decode, 137, 10, 183, 1, // Opcode: QVLFSX -/* 751 */ MCD_OPC_FilterValue, 17, 12, 0, 0, // Skip to: 768 -/* 756 */ MCD_OPC_CheckField, 26, 6, 31, 214, 5, 0, // Skip to: 2257 -/* 763 */ MCD_OPC_Decode, 135, 10, 184, 1, // Opcode: QVLFSUX -/* 768 */ MCD_OPC_FilterValue, 18, 12, 0, 0, // Skip to: 785 -/* 773 */ MCD_OPC_CheckField, 26, 6, 31, 197, 5, 0, // Skip to: 2257 -/* 780 */ MCD_OPC_Decode, 128, 10, 183, 1, // Opcode: QVLFDX -/* 785 */ MCD_OPC_FilterValue, 19, 12, 0, 0, // Skip to: 802 -/* 790 */ MCD_OPC_CheckField, 26, 6, 31, 180, 5, 0, // Skip to: 2257 -/* 797 */ MCD_OPC_Decode, 254, 9, 185, 1, // Opcode: QVLFDUX -/* 802 */ MCD_OPC_FilterValue, 20, 12, 0, 0, // Skip to: 819 -/* 807 */ MCD_OPC_CheckField, 26, 6, 31, 163, 5, 0, // Skip to: 2257 -/* 814 */ MCD_OPC_Decode, 179, 10, 183, 1, // Opcode: QVSTFSX -/* 819 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 836 -/* 824 */ MCD_OPC_CheckField, 26, 6, 31, 146, 5, 0, // Skip to: 2257 -/* 831 */ MCD_OPC_Decode, 174, 10, 186, 1, // Opcode: QVSTFSUX -/* 836 */ MCD_OPC_FilterValue, 22, 12, 0, 0, // Skip to: 853 -/* 841 */ MCD_OPC_CheckField, 26, 6, 31, 129, 5, 0, // Skip to: 2257 -/* 848 */ MCD_OPC_Decode, 167, 10, 183, 1, // Opcode: QVSTFDX -/* 853 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 870 -/* 858 */ MCD_OPC_CheckField, 26, 6, 31, 112, 5, 0, // Skip to: 2257 -/* 865 */ MCD_OPC_Decode, 163, 10, 187, 1, // Opcode: QVSTFDUX -/* 870 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 887 -/* 875 */ MCD_OPC_CheckField, 26, 6, 31, 95, 5, 0, // Skip to: 2257 -/* 882 */ MCD_OPC_Decode, 133, 10, 183, 1, // Opcode: QVLFIWZX -/* 887 */ MCD_OPC_FilterValue, 27, 12, 0, 0, // Skip to: 904 -/* 892 */ MCD_OPC_CheckField, 26, 6, 31, 78, 5, 0, // Skip to: 2257 -/* 899 */ MCD_OPC_Decode, 131, 10, 183, 1, // Opcode: QVLFIWAX -/* 904 */ MCD_OPC_FilterValue, 30, 68, 5, 0, // Skip to: 2257 -/* 909 */ MCD_OPC_CheckField, 26, 6, 31, 61, 5, 0, // Skip to: 2257 -/* 916 */ MCD_OPC_Decode, 172, 10, 183, 1, // Opcode: QVSTFIWX -/* 921 */ MCD_OPC_FilterValue, 15, 70, 1, 0, // Skip to: 1252 -/* 926 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 929 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 946 -/* 934 */ MCD_OPC_CheckField, 26, 6, 31, 36, 5, 0, // Skip to: 2257 -/* 941 */ MCD_OPC_Decode, 252, 9, 183, 1, // Opcode: QVLFCSXA -/* 946 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 963 -/* 951 */ MCD_OPC_CheckField, 26, 6, 31, 19, 5, 0, // Skip to: 2257 -/* 958 */ MCD_OPC_Decode, 250, 9, 183, 1, // Opcode: QVLFCSUXA -/* 963 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 980 -/* 968 */ MCD_OPC_CheckField, 26, 6, 31, 2, 5, 0, // Skip to: 2257 -/* 975 */ MCD_OPC_Decode, 248, 9, 183, 1, // Opcode: QVLFCDXA -/* 980 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 997 -/* 985 */ MCD_OPC_CheckField, 26, 6, 31, 241, 4, 0, // Skip to: 2257 -/* 992 */ MCD_OPC_Decode, 246, 9, 183, 1, // Opcode: QVLFCDUXA -/* 997 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 1014 -/* 1002 */ MCD_OPC_CheckField, 26, 6, 31, 224, 4, 0, // Skip to: 2257 -/* 1009 */ MCD_OPC_Decode, 159, 10, 183, 1, // Opcode: QVSTFCSXA -/* 1014 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 1031 -/* 1019 */ MCD_OPC_CheckField, 26, 6, 31, 207, 4, 0, // Skip to: 2257 -/* 1026 */ MCD_OPC_Decode, 155, 10, 183, 1, // Opcode: QVSTFCSUXA -/* 1031 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 1048 -/* 1036 */ MCD_OPC_CheckField, 26, 6, 31, 190, 4, 0, // Skip to: 2257 -/* 1043 */ MCD_OPC_Decode, 151, 10, 183, 1, // Opcode: QVSTFCDXA -/* 1048 */ MCD_OPC_FilterValue, 7, 12, 0, 0, // Skip to: 1065 -/* 1053 */ MCD_OPC_CheckField, 26, 6, 31, 173, 4, 0, // Skip to: 2257 -/* 1060 */ MCD_OPC_Decode, 147, 10, 183, 1, // Opcode: QVSTFCDUXA -/* 1065 */ MCD_OPC_FilterValue, 16, 12, 0, 0, // Skip to: 1082 -/* 1070 */ MCD_OPC_CheckField, 26, 6, 31, 156, 4, 0, // Skip to: 2257 -/* 1077 */ MCD_OPC_Decode, 138, 10, 183, 1, // Opcode: QVLFSXA -/* 1082 */ MCD_OPC_FilterValue, 17, 12, 0, 0, // Skip to: 1099 -/* 1087 */ MCD_OPC_CheckField, 26, 6, 31, 139, 4, 0, // Skip to: 2257 -/* 1094 */ MCD_OPC_Decode, 136, 10, 183, 1, // Opcode: QVLFSUXA -/* 1099 */ MCD_OPC_FilterValue, 18, 12, 0, 0, // Skip to: 1116 -/* 1104 */ MCD_OPC_CheckField, 26, 6, 31, 122, 4, 0, // Skip to: 2257 -/* 1111 */ MCD_OPC_Decode, 129, 10, 183, 1, // Opcode: QVLFDXA -/* 1116 */ MCD_OPC_FilterValue, 19, 12, 0, 0, // Skip to: 1133 -/* 1121 */ MCD_OPC_CheckField, 26, 6, 31, 105, 4, 0, // Skip to: 2257 -/* 1128 */ MCD_OPC_Decode, 255, 9, 183, 1, // Opcode: QVLFDUXA -/* 1133 */ MCD_OPC_FilterValue, 20, 12, 0, 0, // Skip to: 1150 -/* 1138 */ MCD_OPC_CheckField, 26, 6, 31, 88, 4, 0, // Skip to: 2257 -/* 1145 */ MCD_OPC_Decode, 180, 10, 183, 1, // Opcode: QVSTFSXA -/* 1150 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 1167 -/* 1155 */ MCD_OPC_CheckField, 26, 6, 31, 71, 4, 0, // Skip to: 2257 -/* 1162 */ MCD_OPC_Decode, 175, 10, 183, 1, // Opcode: QVSTFSUXA -/* 1167 */ MCD_OPC_FilterValue, 22, 12, 0, 0, // Skip to: 1184 -/* 1172 */ MCD_OPC_CheckField, 26, 6, 31, 54, 4, 0, // Skip to: 2257 -/* 1179 */ MCD_OPC_Decode, 168, 10, 183, 1, // Opcode: QVSTFDXA -/* 1184 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 1201 -/* 1189 */ MCD_OPC_CheckField, 26, 6, 31, 37, 4, 0, // Skip to: 2257 -/* 1196 */ MCD_OPC_Decode, 164, 10, 183, 1, // Opcode: QVSTFDUXA -/* 1201 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 1218 -/* 1206 */ MCD_OPC_CheckField, 26, 6, 31, 20, 4, 0, // Skip to: 2257 -/* 1213 */ MCD_OPC_Decode, 134, 10, 183, 1, // Opcode: QVLFIWZXA -/* 1218 */ MCD_OPC_FilterValue, 27, 12, 0, 0, // Skip to: 1235 -/* 1223 */ MCD_OPC_CheckField, 26, 6, 31, 3, 4, 0, // Skip to: 2257 -/* 1230 */ MCD_OPC_Decode, 132, 10, 183, 1, // Opcode: QVLFIWAXA -/* 1235 */ MCD_OPC_FilterValue, 30, 249, 3, 0, // Skip to: 2257 -/* 1240 */ MCD_OPC_CheckField, 26, 6, 31, 242, 3, 0, // Skip to: 2257 -/* 1247 */ MCD_OPC_Decode, 173, 10, 183, 1, // Opcode: QVSTFIWXA -/* 1252 */ MCD_OPC_FilterValue, 16, 212, 0, 0, // Skip to: 1469 -/* 1257 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 1260 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1277 -/* 1265 */ MCD_OPC_CheckField, 26, 6, 4, 217, 3, 0, // Skip to: 2257 -/* 1272 */ MCD_OPC_Decode, 170, 9, 188, 1, // Opcode: QVFCPSGN -/* 1277 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 1301 -/* 1282 */ MCD_OPC_CheckField, 26, 6, 4, 200, 3, 0, // Skip to: 2257 -/* 1289 */ MCD_OPC_CheckField, 16, 5, 0, 193, 3, 0, // Skip to: 2257 -/* 1296 */ MCD_OPC_Decode, 198, 9, 189, 1, // Opcode: QVFNEG -/* 1301 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1325 -/* 1306 */ MCD_OPC_CheckField, 26, 6, 4, 176, 3, 0, // Skip to: 2257 -/* 1313 */ MCD_OPC_CheckField, 16, 5, 0, 169, 3, 0, // Skip to: 2257 -/* 1320 */ MCD_OPC_Decode, 187, 9, 189, 1, // Opcode: QVFMR -/* 1325 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1349 -/* 1330 */ MCD_OPC_CheckField, 26, 6, 4, 152, 3, 0, // Skip to: 2257 -/* 1337 */ MCD_OPC_CheckField, 16, 5, 0, 145, 3, 0, // Skip to: 2257 -/* 1344 */ MCD_OPC_Decode, 196, 9, 189, 1, // Opcode: QVFNABS -/* 1349 */ MCD_OPC_FilterValue, 8, 19, 0, 0, // Skip to: 1373 -/* 1354 */ MCD_OPC_CheckField, 26, 6, 4, 128, 3, 0, // Skip to: 2257 -/* 1361 */ MCD_OPC_CheckField, 16, 5, 0, 121, 3, 0, // Skip to: 2257 -/* 1368 */ MCD_OPC_Decode, 151, 9, 189, 1, // Opcode: QVFABS -/* 1373 */ MCD_OPC_FilterValue, 12, 19, 0, 0, // Skip to: 1397 -/* 1378 */ MCD_OPC_CheckField, 26, 6, 4, 104, 3, 0, // Skip to: 2257 -/* 1385 */ MCD_OPC_CheckField, 16, 5, 0, 97, 3, 0, // Skip to: 2257 -/* 1392 */ MCD_OPC_Decode, 213, 9, 189, 1, // Opcode: QVFRIN -/* 1397 */ MCD_OPC_FilterValue, 13, 19, 0, 0, // Skip to: 1421 -/* 1402 */ MCD_OPC_CheckField, 26, 6, 4, 80, 3, 0, // Skip to: 2257 -/* 1409 */ MCD_OPC_CheckField, 16, 5, 0, 73, 3, 0, // Skip to: 2257 -/* 1416 */ MCD_OPC_Decode, 217, 9, 189, 1, // Opcode: QVFRIZ -/* 1421 */ MCD_OPC_FilterValue, 14, 19, 0, 0, // Skip to: 1445 -/* 1426 */ MCD_OPC_CheckField, 26, 6, 4, 56, 3, 0, // Skip to: 2257 -/* 1433 */ MCD_OPC_CheckField, 16, 5, 0, 49, 3, 0, // Skip to: 2257 -/* 1440 */ MCD_OPC_Decode, 215, 9, 189, 1, // Opcode: QVFRIP -/* 1445 */ MCD_OPC_FilterValue, 15, 39, 3, 0, // Skip to: 2257 -/* 1450 */ MCD_OPC_CheckField, 26, 6, 4, 32, 3, 0, // Skip to: 2257 -/* 1457 */ MCD_OPC_CheckField, 16, 5, 0, 25, 3, 0, // Skip to: 2257 -/* 1464 */ MCD_OPC_Decode, 211, 9, 189, 1, // Opcode: QVFRIM -/* 1469 */ MCD_OPC_FilterValue, 18, 23, 0, 0, // Skip to: 1497 -/* 1474 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 1477 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 1487 -/* 1482 */ MCD_OPC_Decode, 235, 9, 178, 1, // Opcode: QVFXMADDS -/* 1487 */ MCD_OPC_FilterValue, 4, 253, 2, 0, // Skip to: 2257 -/* 1492 */ MCD_OPC_Decode, 234, 9, 178, 1, // Opcode: QVFXMADD -/* 1497 */ MCD_OPC_FilterValue, 22, 23, 0, 0, // Skip to: 1525 -/* 1502 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 1505 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 1515 -/* 1510 */ MCD_OPC_Decode, 243, 9, 178, 1, // Opcode: QVFXXNPMADDS -/* 1515 */ MCD_OPC_FilterValue, 4, 225, 2, 0, // Skip to: 2257 -/* 1520 */ MCD_OPC_Decode, 242, 9, 178, 1, // Opcode: QVFXXNPMADD -/* 1525 */ MCD_OPC_FilterValue, 24, 26, 0, 0, // Skip to: 1556 -/* 1530 */ MCD_OPC_CheckField, 26, 6, 4, 208, 2, 0, // Skip to: 2257 -/* 1537 */ MCD_OPC_CheckField, 16, 5, 0, 201, 2, 0, // Skip to: 2257 -/* 1544 */ MCD_OPC_CheckField, 6, 5, 0, 194, 2, 0, // Skip to: 2257 -/* 1551 */ MCD_OPC_Decode, 220, 9, 190, 1, // Opcode: QVFRSPs -/* 1556 */ MCD_OPC_FilterValue, 28, 183, 0, 0, // Skip to: 1744 -/* 1561 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 1564 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1588 -/* 1569 */ MCD_OPC_CheckField, 26, 6, 4, 169, 2, 0, // Skip to: 2257 -/* 1576 */ MCD_OPC_CheckField, 16, 5, 0, 162, 2, 0, // Skip to: 2257 -/* 1583 */ MCD_OPC_Decode, 177, 9, 189, 1, // Opcode: QVFCTIW -/* 1588 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1612 -/* 1593 */ MCD_OPC_CheckField, 26, 6, 4, 145, 2, 0, // Skip to: 2257 -/* 1600 */ MCD_OPC_CheckField, 16, 5, 0, 138, 2, 0, // Skip to: 2257 -/* 1607 */ MCD_OPC_Decode, 178, 9, 189, 1, // Opcode: QVFCTIWU -/* 1612 */ MCD_OPC_FilterValue, 25, 19, 0, 0, // Skip to: 1636 -/* 1617 */ MCD_OPC_CheckField, 26, 6, 4, 121, 2, 0, // Skip to: 2257 -/* 1624 */ MCD_OPC_CheckField, 16, 5, 0, 114, 2, 0, // Skip to: 2257 -/* 1631 */ MCD_OPC_Decode, 172, 9, 189, 1, // Opcode: QVFCTID -/* 1636 */ MCD_OPC_FilterValue, 26, 37, 0, 0, // Skip to: 1678 -/* 1641 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 1644 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1661 -/* 1649 */ MCD_OPC_CheckField, 16, 5, 0, 89, 2, 0, // Skip to: 2257 -/* 1656 */ MCD_OPC_Decode, 157, 9, 189, 1, // Opcode: QVFCFIDS -/* 1661 */ MCD_OPC_FilterValue, 4, 79, 2, 0, // Skip to: 2257 -/* 1666 */ MCD_OPC_CheckField, 16, 5, 0, 72, 2, 0, // Skip to: 2257 -/* 1673 */ MCD_OPC_Decode, 156, 9, 189, 1, // Opcode: QVFCFID -/* 1678 */ MCD_OPC_FilterValue, 29, 19, 0, 0, // Skip to: 1702 -/* 1683 */ MCD_OPC_CheckField, 26, 6, 4, 55, 2, 0, // Skip to: 2257 -/* 1690 */ MCD_OPC_CheckField, 16, 5, 0, 48, 2, 0, // Skip to: 2257 -/* 1697 */ MCD_OPC_Decode, 173, 9, 189, 1, // Opcode: QVFCTIDU -/* 1702 */ MCD_OPC_FilterValue, 30, 38, 2, 0, // Skip to: 2257 -/* 1707 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 1710 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1727 -/* 1715 */ MCD_OPC_CheckField, 16, 5, 0, 23, 2, 0, // Skip to: 2257 -/* 1722 */ MCD_OPC_Decode, 159, 9, 189, 1, // Opcode: QVFCFIDUS -/* 1727 */ MCD_OPC_FilterValue, 4, 13, 2, 0, // Skip to: 2257 -/* 1732 */ MCD_OPC_CheckField, 16, 5, 0, 6, 2, 0, // Skip to: 2257 -/* 1739 */ MCD_OPC_Decode, 158, 9, 189, 1, // Opcode: QVFCFIDU -/* 1744 */ MCD_OPC_FilterValue, 30, 99, 0, 0, // Skip to: 1848 -/* 1749 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... -/* 1752 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1776 -/* 1757 */ MCD_OPC_CheckField, 26, 6, 4, 237, 1, 0, // Skip to: 2257 -/* 1764 */ MCD_OPC_CheckField, 16, 5, 0, 230, 1, 0, // Skip to: 2257 -/* 1771 */ MCD_OPC_Decode, 180, 9, 189, 1, // Opcode: QVFCTIWZ -/* 1776 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1800 -/* 1781 */ MCD_OPC_CheckField, 26, 6, 4, 213, 1, 0, // Skip to: 2257 -/* 1788 */ MCD_OPC_CheckField, 16, 5, 0, 206, 1, 0, // Skip to: 2257 -/* 1795 */ MCD_OPC_Decode, 179, 9, 189, 1, // Opcode: QVFCTIWUZ -/* 1800 */ MCD_OPC_FilterValue, 25, 19, 0, 0, // Skip to: 1824 -/* 1805 */ MCD_OPC_CheckField, 26, 6, 4, 189, 1, 0, // Skip to: 2257 -/* 1812 */ MCD_OPC_CheckField, 16, 5, 0, 182, 1, 0, // Skip to: 2257 -/* 1819 */ MCD_OPC_Decode, 175, 9, 189, 1, // Opcode: QVFCTIDZ -/* 1824 */ MCD_OPC_FilterValue, 29, 172, 1, 0, // Skip to: 2257 -/* 1829 */ MCD_OPC_CheckField, 26, 6, 4, 165, 1, 0, // Skip to: 2257 -/* 1836 */ MCD_OPC_CheckField, 16, 5, 0, 158, 1, 0, // Skip to: 2257 -/* 1843 */ MCD_OPC_Decode, 174, 9, 189, 1, // Opcode: QVFCTIDUZ -/* 1848 */ MCD_OPC_FilterValue, 34, 37, 0, 0, // Skip to: 1890 -/* 1853 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 1856 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1873 -/* 1861 */ MCD_OPC_CheckField, 11, 5, 0, 133, 1, 0, // Skip to: 2257 -/* 1868 */ MCD_OPC_Decode, 237, 9, 191, 1, // Opcode: QVFXMULS -/* 1873 */ MCD_OPC_FilterValue, 4, 123, 1, 0, // Skip to: 2257 -/* 1878 */ MCD_OPC_CheckField, 11, 5, 0, 116, 1, 0, // Skip to: 2257 -/* 1885 */ MCD_OPC_Decode, 236, 9, 191, 1, // Opcode: QVFXMUL -/* 1890 */ MCD_OPC_FilterValue, 40, 37, 0, 0, // Skip to: 1932 -/* 1895 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 1898 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1915 -/* 1903 */ MCD_OPC_CheckField, 6, 5, 0, 91, 1, 0, // Skip to: 2257 -/* 1910 */ MCD_OPC_Decode, 230, 9, 192, 1, // Opcode: QVFSUBSs -/* 1915 */ MCD_OPC_FilterValue, 4, 81, 1, 0, // Skip to: 2257 -/* 1920 */ MCD_OPC_CheckField, 6, 5, 0, 74, 1, 0, // Skip to: 2257 -/* 1927 */ MCD_OPC_Decode, 228, 9, 188, 1, // Opcode: QVFSUB -/* 1932 */ MCD_OPC_FilterValue, 42, 37, 0, 0, // Skip to: 1974 -/* 1937 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 1940 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1957 -/* 1945 */ MCD_OPC_CheckField, 6, 5, 0, 49, 1, 0, // Skip to: 2257 -/* 1952 */ MCD_OPC_Decode, 155, 9, 192, 1, // Opcode: QVFADDSs -/* 1957 */ MCD_OPC_FilterValue, 4, 39, 1, 0, // Skip to: 2257 -/* 1962 */ MCD_OPC_CheckField, 6, 5, 0, 32, 1, 0, // Skip to: 2257 -/* 1969 */ MCD_OPC_Decode, 153, 9, 188, 1, // Opcode: QVFADD -/* 1974 */ MCD_OPC_FilterValue, 46, 12, 0, 0, // Skip to: 1991 -/* 1979 */ MCD_OPC_CheckField, 26, 6, 4, 15, 1, 0, // Skip to: 2257 -/* 1986 */ MCD_OPC_Decode, 225, 9, 193, 1, // Opcode: QVFSELb -/* 1991 */ MCD_OPC_FilterValue, 48, 51, 0, 0, // Skip to: 2047 -/* 1996 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 1999 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2023 -/* 2004 */ MCD_OPC_CheckField, 16, 5, 0, 246, 0, 0, // Skip to: 2257 -/* 2011 */ MCD_OPC_CheckField, 6, 5, 0, 239, 0, 0, // Skip to: 2257 -/* 2018 */ MCD_OPC_Decode, 209, 9, 189, 1, // Opcode: QVFRES -/* 2023 */ MCD_OPC_FilterValue, 4, 229, 0, 0, // Skip to: 2257 -/* 2028 */ MCD_OPC_CheckField, 16, 5, 0, 222, 0, 0, // Skip to: 2257 -/* 2035 */ MCD_OPC_CheckField, 6, 5, 0, 215, 0, 0, // Skip to: 2257 -/* 2042 */ MCD_OPC_Decode, 208, 9, 189, 1, // Opcode: QVFRE -/* 2047 */ MCD_OPC_FilterValue, 50, 37, 0, 0, // Skip to: 2089 -/* 2052 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 2055 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2072 -/* 2060 */ MCD_OPC_CheckField, 11, 5, 0, 190, 0, 0, // Skip to: 2257 -/* 2067 */ MCD_OPC_Decode, 195, 9, 194, 1, // Opcode: QVFMULSs -/* 2072 */ MCD_OPC_FilterValue, 4, 180, 0, 0, // Skip to: 2257 -/* 2077 */ MCD_OPC_CheckField, 11, 5, 0, 173, 0, 0, // Skip to: 2257 -/* 2084 */ MCD_OPC_Decode, 193, 9, 191, 1, // Opcode: QVFMUL -/* 2089 */ MCD_OPC_FilterValue, 52, 51, 0, 0, // Skip to: 2145 -/* 2094 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 2097 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2121 -/* 2102 */ MCD_OPC_CheckField, 16, 5, 0, 148, 0, 0, // Skip to: 2257 -/* 2109 */ MCD_OPC_CheckField, 6, 5, 0, 141, 0, 0, // Skip to: 2257 -/* 2116 */ MCD_OPC_Decode, 222, 9, 189, 1, // Opcode: QVFRSQRTES -/* 2121 */ MCD_OPC_FilterValue, 4, 131, 0, 0, // Skip to: 2257 -/* 2126 */ MCD_OPC_CheckField, 16, 5, 0, 124, 0, 0, // Skip to: 2257 -/* 2133 */ MCD_OPC_CheckField, 6, 5, 0, 117, 0, 0, // Skip to: 2257 -/* 2140 */ MCD_OPC_Decode, 221, 9, 189, 1, // Opcode: QVFRSQRTE -/* 2145 */ MCD_OPC_FilterValue, 56, 23, 0, 0, // Skip to: 2173 -/* 2150 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 2153 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 2163 -/* 2158 */ MCD_OPC_Decode, 192, 9, 195, 1, // Opcode: QVFMSUBSs -/* 2163 */ MCD_OPC_FilterValue, 4, 89, 0, 0, // Skip to: 2257 -/* 2168 */ MCD_OPC_Decode, 190, 9, 178, 1, // Opcode: QVFMSUB -/* 2173 */ MCD_OPC_FilterValue, 58, 23, 0, 0, // Skip to: 2201 -/* 2178 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 2181 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 2191 -/* 2186 */ MCD_OPC_Decode, 186, 9, 195, 1, // Opcode: QVFMADDSs -/* 2191 */ MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 2257 -/* 2196 */ MCD_OPC_Decode, 184, 9, 178, 1, // Opcode: QVFMADD -/* 2201 */ MCD_OPC_FilterValue, 60, 23, 0, 0, // Skip to: 2229 -/* 2206 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 2209 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 2219 -/* 2214 */ MCD_OPC_Decode, 205, 9, 195, 1, // Opcode: QVFNMSUBSs -/* 2219 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 2257 -/* 2224 */ MCD_OPC_Decode, 203, 9, 178, 1, // Opcode: QVFNMSUB -/* 2229 */ MCD_OPC_FilterValue, 62, 23, 0, 0, // Skip to: 2257 -/* 2234 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 2237 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 2247 -/* 2242 */ MCD_OPC_Decode, 202, 9, 195, 1, // Opcode: QVFNMADDSs -/* 2247 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 2257 -/* 2252 */ MCD_OPC_Decode, 200, 9, 178, 1, // Opcode: QVFNMADD -/* 2257 */ MCD_OPC_Fail, +static const uint8_t DecoderTable64[] = { +/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... +/* 3 */ MCD_OPC_FilterValue, 7, 52, 0, 0, // Skip to: 60 +/* 8 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 11 */ MCD_OPC_FilterValue, 128, 3, 25, 0, 0, // Skip to: 42 +/* 17 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 20 */ MCD_OPC_FilterValue, 0, 79, 9, 0, // Skip to: 2408 +/* 25 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 37 +/* 32 */ MCD_OPC_Decode, 134, 11, 207, 1, // Opcode: PLI +/* 37 */ MCD_OPC_Decode, 237, 10, 208, 1, // Opcode: PADDI +/* 42 */ MCD_OPC_FilterValue, 132, 3, 56, 9, 0, // Skip to: 2408 +/* 48 */ MCD_OPC_CheckField, 26, 1, 0, 49, 9, 0, // Skip to: 2408 +/* 55 */ MCD_OPC_Decode, 241, 10, 209, 1, // Opcode: PADDIpc +/* 60 */ MCD_OPC_FilterValue, 16, 191, 0, 0, // Skip to: 256 +/* 65 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 68 */ MCD_OPC_FilterValue, 192, 2, 146, 0, 0, // Skip to: 220 +/* 74 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 77 */ MCD_OPC_FilterValue, 0, 62, 0, 0, // Skip to: 144 +/* 82 */ MCD_OPC_ExtractField, 18, 3, // Inst{20-18} ... +/* 85 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 102 +/* 90 */ MCD_OPC_CheckField, 48, 2, 0, 7, 9, 0, // Skip to: 2408 +/* 97 */ MCD_OPC_Decode, 196, 19, 210, 1, // Opcode: XXSPLTI32DX +/* 102 */ MCD_OPC_FilterValue, 1, 253, 8, 0, // Skip to: 2408 +/* 107 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 110 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 127 +/* 115 */ MCD_OPC_CheckField, 48, 2, 0, 238, 8, 0, // Skip to: 2408 +/* 122 */ MCD_OPC_Decode, 198, 19, 211, 1, // Opcode: XXSPLTIDP +/* 127 */ MCD_OPC_FilterValue, 1, 228, 8, 0, // Skip to: 2408 +/* 132 */ MCD_OPC_CheckField, 48, 2, 0, 221, 8, 0, // Skip to: 2408 +/* 139 */ MCD_OPC_Decode, 199, 19, 211, 1, // Opcode: XXSPLTIW +/* 144 */ MCD_OPC_FilterValue, 1, 211, 8, 0, // Skip to: 2408 +/* 149 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 152 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 169 +/* 157 */ MCD_OPC_CheckField, 32, 18, 0, 196, 8, 0, // Skip to: 2408 +/* 164 */ MCD_OPC_Decode, 155, 19, 185, 1, // Opcode: XXBLENDVB +/* 169 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 186 +/* 174 */ MCD_OPC_CheckField, 32, 18, 0, 179, 8, 0, // Skip to: 2408 +/* 181 */ MCD_OPC_Decode, 157, 19, 185, 1, // Opcode: XXBLENDVH +/* 186 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 203 +/* 191 */ MCD_OPC_CheckField, 32, 18, 0, 162, 8, 0, // Skip to: 2408 +/* 198 */ MCD_OPC_Decode, 158, 19, 185, 1, // Opcode: XXBLENDVW +/* 203 */ MCD_OPC_FilterValue, 3, 152, 8, 0, // Skip to: 2408 +/* 208 */ MCD_OPC_CheckField, 32, 18, 0, 145, 8, 0, // Skip to: 2408 +/* 215 */ MCD_OPC_Decode, 156, 19, 185, 1, // Opcode: XXBLENDVD +/* 220 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 238 +/* 226 */ MCD_OPC_CheckField, 26, 1, 0, 127, 8, 0, // Skip to: 2408 +/* 233 */ MCD_OPC_Decode, 140, 11, 212, 1, // Opcode: PLWZ +/* 238 */ MCD_OPC_FilterValue, 132, 3, 116, 8, 0, // Skip to: 2408 +/* 244 */ MCD_OPC_CheckField, 26, 1, 0, 109, 8, 0, // Skip to: 2408 +/* 251 */ MCD_OPC_Decode, 143, 11, 213, 1, // Opcode: PLWZpc +/* 256 */ MCD_OPC_FilterValue, 17, 96, 0, 0, // Skip to: 357 +/* 261 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 264 */ MCD_OPC_FilterValue, 192, 2, 51, 0, 0, // Skip to: 321 +/* 270 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 273 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 297 +/* 278 */ MCD_OPC_CheckField, 35, 15, 0, 75, 8, 0, // Skip to: 2408 +/* 285 */ MCD_OPC_CheckField, 26, 1, 0, 68, 8, 0, // Skip to: 2408 +/* 292 */ MCD_OPC_Decode, 191, 19, 214, 1, // Opcode: XXPERMX +/* 297 */ MCD_OPC_FilterValue, 1, 58, 8, 0, // Skip to: 2408 +/* 302 */ MCD_OPC_CheckField, 40, 10, 0, 51, 8, 0, // Skip to: 2408 +/* 309 */ MCD_OPC_CheckField, 26, 1, 0, 44, 8, 0, // Skip to: 2408 +/* 316 */ MCD_OPC_Decode, 163, 19, 215, 1, // Opcode: XXEVAL +/* 321 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 339 +/* 327 */ MCD_OPC_CheckField, 26, 1, 0, 26, 8, 0, // Skip to: 2408 +/* 334 */ MCD_OPC_Decode, 244, 10, 212, 1, // Opcode: PLBZ +/* 339 */ MCD_OPC_FilterValue, 132, 3, 15, 8, 0, // Skip to: 2408 +/* 345 */ MCD_OPC_CheckField, 26, 1, 0, 8, 8, 0, // Skip to: 2408 +/* 352 */ MCD_OPC_Decode, 247, 10, 213, 1, // Opcode: PLBZpc +/* 357 */ MCD_OPC_FilterValue, 18, 39, 0, 0, // Skip to: 401 +/* 362 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 365 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 383 +/* 371 */ MCD_OPC_CheckField, 26, 1, 0, 238, 7, 0, // Skip to: 2408 +/* 378 */ MCD_OPC_Decode, 209, 11, 212, 1, // Opcode: PSTW +/* 383 */ MCD_OPC_FilterValue, 132, 3, 227, 7, 0, // Skip to: 2408 +/* 389 */ MCD_OPC_CheckField, 26, 1, 0, 220, 7, 0, // Skip to: 2408 +/* 396 */ MCD_OPC_Decode, 212, 11, 213, 1, // Opcode: PSTWpc +/* 401 */ MCD_OPC_FilterValue, 19, 39, 0, 0, // Skip to: 445 +/* 406 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 409 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 427 +/* 415 */ MCD_OPC_CheckField, 26, 1, 0, 194, 7, 0, // Skip to: 2408 +/* 422 */ MCD_OPC_Decode, 195, 11, 212, 1, // Opcode: PSTB +/* 427 */ MCD_OPC_FilterValue, 132, 3, 183, 7, 0, // Skip to: 2408 +/* 433 */ MCD_OPC_CheckField, 26, 1, 0, 176, 7, 0, // Skip to: 2408 +/* 440 */ MCD_OPC_Decode, 198, 11, 213, 1, // Opcode: PSTBpc +/* 445 */ MCD_OPC_FilterValue, 20, 75, 0, 0, // Skip to: 525 +/* 450 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 453 */ MCD_OPC_FilterValue, 128, 2, 12, 0, 0, // Skip to: 471 +/* 459 */ MCD_OPC_CheckField, 26, 1, 1, 150, 7, 0, // Skip to: 2408 +/* 466 */ MCD_OPC_Decode, 136, 11, 212, 1, // Opcode: PLWA +/* 471 */ MCD_OPC_FilterValue, 132, 2, 12, 0, 0, // Skip to: 489 +/* 477 */ MCD_OPC_CheckField, 26, 1, 1, 132, 7, 0, // Skip to: 2408 +/* 484 */ MCD_OPC_Decode, 139, 11, 213, 1, // Opcode: PLWApc +/* 489 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 507 +/* 495 */ MCD_OPC_CheckField, 26, 1, 0, 114, 7, 0, // Skip to: 2408 +/* 502 */ MCD_OPC_Decode, 130, 11, 212, 1, // Opcode: PLHZ +/* 507 */ MCD_OPC_FilterValue, 132, 3, 103, 7, 0, // Skip to: 2408 +/* 513 */ MCD_OPC_CheckField, 26, 1, 0, 96, 7, 0, // Skip to: 2408 +/* 520 */ MCD_OPC_Decode, 133, 11, 213, 1, // Opcode: PLHZpc +/* 525 */ MCD_OPC_FilterValue, 21, 97, 0, 0, // Skip to: 627 +/* 530 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 533 */ MCD_OPC_FilterValue, 128, 2, 23, 0, 0, // Skip to: 562 +/* 539 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 542 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 552 +/* 547 */ MCD_OPC_Decode, 144, 11, 216, 1, // Opcode: PLXSD +/* 552 */ MCD_OPC_FilterValue, 1, 59, 7, 0, // Skip to: 2408 +/* 557 */ MCD_OPC_Decode, 146, 11, 216, 1, // Opcode: PLXSSP +/* 562 */ MCD_OPC_FilterValue, 132, 2, 23, 0, 0, // Skip to: 591 +/* 568 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 571 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 581 +/* 576 */ MCD_OPC_Decode, 145, 11, 217, 1, // Opcode: PLXSDpc +/* 581 */ MCD_OPC_FilterValue, 1, 30, 7, 0, // Skip to: 2408 +/* 586 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: PLXSSPpc +/* 591 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 609 +/* 597 */ MCD_OPC_CheckField, 26, 1, 0, 12, 7, 0, // Skip to: 2408 +/* 604 */ MCD_OPC_Decode, 254, 10, 212, 1, // Opcode: PLHA +/* 609 */ MCD_OPC_FilterValue, 132, 3, 1, 7, 0, // Skip to: 2408 +/* 615 */ MCD_OPC_CheckField, 26, 1, 0, 250, 6, 0, // Skip to: 2408 +/* 622 */ MCD_OPC_Decode, 129, 11, 213, 1, // Opcode: PLHApc +/* 627 */ MCD_OPC_FilterValue, 22, 39, 0, 0, // Skip to: 671 +/* 632 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 635 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 653 +/* 641 */ MCD_OPC_CheckField, 26, 1, 0, 224, 6, 0, // Skip to: 2408 +/* 648 */ MCD_OPC_Decode, 205, 11, 212, 1, // Opcode: PSTH +/* 653 */ MCD_OPC_FilterValue, 132, 3, 213, 6, 0, // Skip to: 2408 +/* 659 */ MCD_OPC_CheckField, 26, 1, 0, 206, 6, 0, // Skip to: 2408 +/* 666 */ MCD_OPC_Decode, 208, 11, 213, 1, // Opcode: PSTHpc +/* 671 */ MCD_OPC_FilterValue, 23, 63, 0, 0, // Skip to: 739 +/* 676 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 679 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 709 +/* 684 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 687 */ MCD_OPC_FilterValue, 128, 2, 5, 0, 0, // Skip to: 698 +/* 693 */ MCD_OPC_Decode, 213, 11, 216, 1, // Opcode: PSTXSD +/* 698 */ MCD_OPC_FilterValue, 132, 2, 168, 6, 0, // Skip to: 2408 +/* 704 */ MCD_OPC_Decode, 214, 11, 217, 1, // Opcode: PSTXSDpc +/* 709 */ MCD_OPC_FilterValue, 1, 158, 6, 0, // Skip to: 2408 +/* 714 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 717 */ MCD_OPC_FilterValue, 128, 2, 5, 0, 0, // Skip to: 728 +/* 723 */ MCD_OPC_Decode, 215, 11, 216, 1, // Opcode: PSTXSSP +/* 728 */ MCD_OPC_FilterValue, 132, 2, 138, 6, 0, // Skip to: 2408 +/* 734 */ MCD_OPC_Decode, 216, 11, 217, 1, // Opcode: PSTXSSPpc +/* 739 */ MCD_OPC_FilterValue, 24, 39, 0, 0, // Skip to: 783 +/* 744 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 747 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 765 +/* 753 */ MCD_OPC_CheckField, 26, 1, 0, 112, 6, 0, // Skip to: 2408 +/* 760 */ MCD_OPC_Decode, 252, 10, 218, 1, // Opcode: PLFS +/* 765 */ MCD_OPC_FilterValue, 132, 3, 101, 6, 0, // Skip to: 2408 +/* 771 */ MCD_OPC_CheckField, 26, 1, 0, 94, 6, 0, // Skip to: 2408 +/* 778 */ MCD_OPC_Decode, 253, 10, 219, 1, // Opcode: PLFSpc +/* 783 */ MCD_OPC_FilterValue, 25, 61, 0, 0, // Skip to: 849 +/* 788 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 791 */ MCD_OPC_FilterValue, 128, 2, 5, 0, 0, // Skip to: 802 +/* 797 */ MCD_OPC_Decode, 148, 11, 220, 1, // Opcode: PLXV +/* 802 */ MCD_OPC_FilterValue, 132, 2, 5, 0, 0, // Skip to: 813 +/* 808 */ MCD_OPC_Decode, 151, 11, 221, 1, // Opcode: PLXVpc +/* 813 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 831 +/* 819 */ MCD_OPC_CheckField, 26, 1, 0, 46, 6, 0, // Skip to: 2408 +/* 826 */ MCD_OPC_Decode, 250, 10, 222, 1, // Opcode: PLFD +/* 831 */ MCD_OPC_FilterValue, 132, 3, 35, 6, 0, // Skip to: 2408 +/* 837 */ MCD_OPC_CheckField, 26, 1, 0, 28, 6, 0, // Skip to: 2408 +/* 844 */ MCD_OPC_Decode, 251, 10, 223, 1, // Opcode: PLFDpc +/* 849 */ MCD_OPC_FilterValue, 26, 39, 0, 0, // Skip to: 893 +/* 854 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 857 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 875 +/* 863 */ MCD_OPC_CheckField, 26, 1, 0, 2, 6, 0, // Skip to: 2408 +/* 870 */ MCD_OPC_Decode, 203, 11, 218, 1, // Opcode: PSTFS +/* 875 */ MCD_OPC_FilterValue, 132, 3, 247, 5, 0, // Skip to: 2408 +/* 881 */ MCD_OPC_CheckField, 26, 1, 0, 240, 5, 0, // Skip to: 2408 +/* 888 */ MCD_OPC_Decode, 204, 11, 219, 1, // Opcode: PSTFSpc +/* 893 */ MCD_OPC_FilterValue, 27, 61, 0, 0, // Skip to: 959 +/* 898 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 901 */ MCD_OPC_FilterValue, 128, 2, 5, 0, 0, // Skip to: 912 +/* 907 */ MCD_OPC_Decode, 217, 11, 220, 1, // Opcode: PSTXV +/* 912 */ MCD_OPC_FilterValue, 132, 2, 5, 0, 0, // Skip to: 923 +/* 918 */ MCD_OPC_Decode, 220, 11, 221, 1, // Opcode: PSTXVpc +/* 923 */ MCD_OPC_FilterValue, 128, 3, 12, 0, 0, // Skip to: 941 +/* 929 */ MCD_OPC_CheckField, 26, 1, 0, 192, 5, 0, // Skip to: 2408 +/* 936 */ MCD_OPC_Decode, 201, 11, 222, 1, // Opcode: PSTFD +/* 941 */ MCD_OPC_FilterValue, 132, 3, 181, 5, 0, // Skip to: 2408 +/* 947 */ MCD_OPC_CheckField, 26, 1, 0, 174, 5, 0, // Skip to: 2408 +/* 954 */ MCD_OPC_Decode, 202, 11, 223, 1, // Opcode: PSTFDpc +/* 959 */ MCD_OPC_FilterValue, 28, 39, 0, 0, // Skip to: 1003 +/* 964 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 967 */ MCD_OPC_FilterValue, 128, 2, 12, 0, 0, // Skip to: 985 +/* 973 */ MCD_OPC_CheckField, 26, 1, 1, 148, 5, 0, // Skip to: 2408 +/* 980 */ MCD_OPC_Decode, 248, 10, 224, 1, // Opcode: PLD +/* 985 */ MCD_OPC_FilterValue, 132, 2, 137, 5, 0, // Skip to: 2408 +/* 991 */ MCD_OPC_CheckField, 26, 1, 1, 130, 5, 0, // Skip to: 2408 +/* 998 */ MCD_OPC_Decode, 249, 10, 225, 1, // Opcode: PLDpc +/* 1003 */ MCD_OPC_FilterValue, 29, 32, 5, 0, // Skip to: 2320 +/* 1008 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 1011 */ MCD_OPC_FilterValue, 128, 2, 12, 0, 0, // Skip to: 1029 +/* 1017 */ MCD_OPC_CheckField, 26, 1, 0, 104, 5, 0, // Skip to: 2408 +/* 1024 */ MCD_OPC_Decode, 149, 11, 226, 1, // Opcode: PLXVP +/* 1029 */ MCD_OPC_FilterValue, 132, 2, 12, 0, 0, // Skip to: 1047 +/* 1035 */ MCD_OPC_CheckField, 26, 1, 0, 86, 5, 0, // Skip to: 2408 +/* 1042 */ MCD_OPC_Decode, 150, 11, 227, 1, // Opcode: PLXVPpc +/* 1047 */ MCD_OPC_FilterValue, 228, 3, 75, 5, 0, // Skip to: 2408 +/* 1053 */ MCD_OPC_ExtractField, 3, 8, // Inst{10-3} ... +/* 1056 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 1101 +/* 1061 */ MCD_OPC_CheckField, 48, 2, 0, 60, 5, 0, // Skip to: 2408 +/* 1068 */ MCD_OPC_CheckField, 40, 4, 0, 53, 5, 0, // Skip to: 2408 +/* 1075 */ MCD_OPC_CheckField, 26, 1, 1, 46, 5, 0, // Skip to: 2408 +/* 1082 */ MCD_OPC_CheckField, 21, 2, 0, 39, 5, 0, // Skip to: 2408 +/* 1089 */ MCD_OPC_CheckField, 0, 1, 0, 32, 5, 0, // Skip to: 2408 +/* 1096 */ MCD_OPC_Decode, 179, 11, 228, 1, // Opcode: PMXVI8GER4PP +/* 1101 */ MCD_OPC_FilterValue, 3, 40, 0, 0, // Skip to: 1146 +/* 1106 */ MCD_OPC_CheckField, 48, 2, 0, 15, 5, 0, // Skip to: 2408 +/* 1113 */ MCD_OPC_CheckField, 40, 4, 0, 8, 5, 0, // Skip to: 2408 +/* 1120 */ MCD_OPC_CheckField, 26, 1, 1, 1, 5, 0, // Skip to: 2408 +/* 1127 */ MCD_OPC_CheckField, 21, 2, 0, 250, 4, 0, // Skip to: 2408 +/* 1134 */ MCD_OPC_CheckField, 0, 1, 0, 243, 4, 0, // Skip to: 2408 +/* 1141 */ MCD_OPC_Decode, 178, 11, 229, 1, // Opcode: PMXVI8GER4 +/* 1146 */ MCD_OPC_FilterValue, 18, 40, 0, 0, // Skip to: 1191 +/* 1151 */ MCD_OPC_CheckField, 48, 2, 0, 226, 4, 0, // Skip to: 2408 +/* 1158 */ MCD_OPC_CheckField, 40, 6, 0, 219, 4, 0, // Skip to: 2408 +/* 1165 */ MCD_OPC_CheckField, 26, 1, 1, 212, 4, 0, // Skip to: 2408 +/* 1172 */ MCD_OPC_CheckField, 21, 2, 0, 205, 4, 0, // Skip to: 2408 +/* 1179 */ MCD_OPC_CheckField, 0, 1, 0, 198, 4, 0, // Skip to: 2408 +/* 1186 */ MCD_OPC_Decode, 161, 11, 230, 1, // Opcode: PMXVF16GER2PP +/* 1191 */ MCD_OPC_FilterValue, 19, 40, 0, 0, // Skip to: 1236 +/* 1196 */ MCD_OPC_CheckField, 48, 2, 0, 181, 4, 0, // Skip to: 2408 +/* 1203 */ MCD_OPC_CheckField, 40, 6, 0, 174, 4, 0, // Skip to: 2408 +/* 1210 */ MCD_OPC_CheckField, 26, 1, 1, 167, 4, 0, // Skip to: 2408 +/* 1217 */ MCD_OPC_CheckField, 21, 2, 0, 160, 4, 0, // Skip to: 2408 +/* 1224 */ MCD_OPC_CheckField, 0, 1, 0, 153, 4, 0, // Skip to: 2408 +/* 1231 */ MCD_OPC_Decode, 157, 11, 231, 1, // Opcode: PMXVF16GER2 +/* 1236 */ MCD_OPC_FilterValue, 26, 33, 0, 0, // Skip to: 1274 +/* 1241 */ MCD_OPC_CheckField, 40, 10, 0, 136, 4, 0, // Skip to: 2408 +/* 1248 */ MCD_OPC_CheckField, 26, 1, 1, 129, 4, 0, // Skip to: 2408 +/* 1255 */ MCD_OPC_CheckField, 21, 2, 0, 122, 4, 0, // Skip to: 2408 +/* 1262 */ MCD_OPC_CheckField, 0, 1, 0, 115, 4, 0, // Skip to: 2408 +/* 1269 */ MCD_OPC_Decode, 166, 11, 232, 1, // Opcode: PMXVF32GERPP +/* 1274 */ MCD_OPC_FilterValue, 27, 33, 0, 0, // Skip to: 1312 +/* 1279 */ MCD_OPC_CheckField, 40, 10, 0, 98, 4, 0, // Skip to: 2408 +/* 1286 */ MCD_OPC_CheckField, 26, 1, 1, 91, 4, 0, // Skip to: 2408 +/* 1293 */ MCD_OPC_CheckField, 21, 2, 0, 84, 4, 0, // Skip to: 2408 +/* 1300 */ MCD_OPC_CheckField, 0, 1, 0, 77, 4, 0, // Skip to: 2408 +/* 1307 */ MCD_OPC_Decode, 162, 11, 233, 1, // Opcode: PMXVF32GER +/* 1312 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 1350 +/* 1317 */ MCD_OPC_CheckField, 48, 2, 0, 60, 4, 0, // Skip to: 2408 +/* 1324 */ MCD_OPC_CheckField, 26, 1, 1, 53, 4, 0, // Skip to: 2408 +/* 1331 */ MCD_OPC_CheckField, 21, 2, 0, 46, 4, 0, // Skip to: 2408 +/* 1338 */ MCD_OPC_CheckField, 0, 1, 0, 39, 4, 0, // Skip to: 2408 +/* 1345 */ MCD_OPC_Decode, 177, 11, 234, 1, // Opcode: PMXVI4GER8PP +/* 1350 */ MCD_OPC_FilterValue, 35, 33, 0, 0, // Skip to: 1388 +/* 1355 */ MCD_OPC_CheckField, 48, 2, 0, 22, 4, 0, // Skip to: 2408 +/* 1362 */ MCD_OPC_CheckField, 26, 1, 1, 15, 4, 0, // Skip to: 2408 +/* 1369 */ MCD_OPC_CheckField, 21, 2, 0, 8, 4, 0, // Skip to: 2408 +/* 1376 */ MCD_OPC_CheckField, 0, 1, 0, 1, 4, 0, // Skip to: 2408 +/* 1383 */ MCD_OPC_Decode, 176, 11, 235, 1, // Opcode: PMXVI4GER8 +/* 1388 */ MCD_OPC_FilterValue, 42, 40, 0, 0, // Skip to: 1433 +/* 1393 */ MCD_OPC_CheckField, 48, 2, 0, 240, 3, 0, // Skip to: 2408 +/* 1400 */ MCD_OPC_CheckField, 40, 6, 0, 233, 3, 0, // Skip to: 2408 +/* 1407 */ MCD_OPC_CheckField, 26, 1, 1, 226, 3, 0, // Skip to: 2408 +/* 1414 */ MCD_OPC_CheckField, 21, 2, 0, 219, 3, 0, // Skip to: 2408 +/* 1421 */ MCD_OPC_CheckField, 0, 1, 0, 212, 3, 0, // Skip to: 2408 +/* 1428 */ MCD_OPC_Decode, 175, 11, 230, 1, // Opcode: PMXVI16GER2SPP +/* 1433 */ MCD_OPC_FilterValue, 43, 40, 0, 0, // Skip to: 1478 +/* 1438 */ MCD_OPC_CheckField, 48, 2, 0, 195, 3, 0, // Skip to: 2408 +/* 1445 */ MCD_OPC_CheckField, 40, 6, 0, 188, 3, 0, // Skip to: 2408 +/* 1452 */ MCD_OPC_CheckField, 26, 1, 1, 181, 3, 0, // Skip to: 2408 +/* 1459 */ MCD_OPC_CheckField, 21, 2, 0, 174, 3, 0, // Skip to: 2408 +/* 1466 */ MCD_OPC_CheckField, 0, 1, 0, 167, 3, 0, // Skip to: 2408 +/* 1473 */ MCD_OPC_Decode, 174, 11, 231, 1, // Opcode: PMXVI16GER2S +/* 1478 */ MCD_OPC_FilterValue, 50, 40, 0, 0, // Skip to: 1523 +/* 1483 */ MCD_OPC_CheckField, 48, 2, 0, 150, 3, 0, // Skip to: 2408 +/* 1490 */ MCD_OPC_CheckField, 40, 6, 0, 143, 3, 0, // Skip to: 2408 +/* 1497 */ MCD_OPC_CheckField, 26, 1, 1, 136, 3, 0, // Skip to: 2408 +/* 1504 */ MCD_OPC_CheckField, 21, 2, 0, 129, 3, 0, // Skip to: 2408 +/* 1511 */ MCD_OPC_CheckField, 0, 1, 0, 122, 3, 0, // Skip to: 2408 +/* 1518 */ MCD_OPC_Decode, 156, 11, 230, 1, // Opcode: PMXVBF16GER2PP +/* 1523 */ MCD_OPC_FilterValue, 51, 40, 0, 0, // Skip to: 1568 +/* 1528 */ MCD_OPC_CheckField, 48, 2, 0, 105, 3, 0, // Skip to: 2408 +/* 1535 */ MCD_OPC_CheckField, 40, 6, 0, 98, 3, 0, // Skip to: 2408 +/* 1542 */ MCD_OPC_CheckField, 26, 1, 1, 91, 3, 0, // Skip to: 2408 +/* 1549 */ MCD_OPC_CheckField, 21, 2, 0, 84, 3, 0, // Skip to: 2408 +/* 1556 */ MCD_OPC_CheckField, 0, 1, 0, 77, 3, 0, // Skip to: 2408 +/* 1563 */ MCD_OPC_Decode, 152, 11, 231, 1, // Opcode: PMXVBF16GER2 +/* 1568 */ MCD_OPC_FilterValue, 58, 40, 0, 0, // Skip to: 1613 +/* 1573 */ MCD_OPC_CheckField, 40, 10, 0, 60, 3, 0, // Skip to: 2408 +/* 1580 */ MCD_OPC_CheckField, 32, 2, 0, 53, 3, 0, // Skip to: 2408 +/* 1587 */ MCD_OPC_CheckField, 26, 1, 1, 46, 3, 0, // Skip to: 2408 +/* 1594 */ MCD_OPC_CheckField, 21, 2, 0, 39, 3, 0, // Skip to: 2408 +/* 1601 */ MCD_OPC_CheckField, 0, 1, 0, 32, 3, 0, // Skip to: 2408 +/* 1608 */ MCD_OPC_Decode, 171, 11, 236, 1, // Opcode: PMXVF64GERPP +/* 1613 */ MCD_OPC_FilterValue, 59, 40, 0, 0, // Skip to: 1658 +/* 1618 */ MCD_OPC_CheckField, 40, 10, 0, 15, 3, 0, // Skip to: 2408 +/* 1625 */ MCD_OPC_CheckField, 32, 2, 0, 8, 3, 0, // Skip to: 2408 +/* 1632 */ MCD_OPC_CheckField, 26, 1, 1, 1, 3, 0, // Skip to: 2408 +/* 1639 */ MCD_OPC_CheckField, 21, 2, 0, 250, 2, 0, // Skip to: 2408 +/* 1646 */ MCD_OPC_CheckField, 0, 1, 0, 243, 2, 0, // Skip to: 2408 +/* 1653 */ MCD_OPC_Decode, 167, 11, 237, 1, // Opcode: PMXVF64GER +/* 1658 */ MCD_OPC_FilterValue, 75, 40, 0, 0, // Skip to: 1703 +/* 1663 */ MCD_OPC_CheckField, 48, 2, 0, 226, 2, 0, // Skip to: 2408 +/* 1670 */ MCD_OPC_CheckField, 40, 6, 0, 219, 2, 0, // Skip to: 2408 +/* 1677 */ MCD_OPC_CheckField, 26, 1, 1, 212, 2, 0, // Skip to: 2408 +/* 1684 */ MCD_OPC_CheckField, 21, 2, 0, 205, 2, 0, // Skip to: 2408 +/* 1691 */ MCD_OPC_CheckField, 0, 1, 0, 198, 2, 0, // Skip to: 2408 +/* 1698 */ MCD_OPC_Decode, 172, 11, 231, 1, // Opcode: PMXVI16GER2 +/* 1703 */ MCD_OPC_FilterValue, 82, 40, 0, 0, // Skip to: 1748 +/* 1708 */ MCD_OPC_CheckField, 48, 2, 0, 181, 2, 0, // Skip to: 2408 +/* 1715 */ MCD_OPC_CheckField, 40, 6, 0, 174, 2, 0, // Skip to: 2408 +/* 1722 */ MCD_OPC_CheckField, 26, 1, 1, 167, 2, 0, // Skip to: 2408 +/* 1729 */ MCD_OPC_CheckField, 21, 2, 0, 160, 2, 0, // Skip to: 2408 +/* 1736 */ MCD_OPC_CheckField, 0, 1, 0, 153, 2, 0, // Skip to: 2408 +/* 1743 */ MCD_OPC_Decode, 159, 11, 230, 1, // Opcode: PMXVF16GER2NP +/* 1748 */ MCD_OPC_FilterValue, 90, 33, 0, 0, // Skip to: 1786 +/* 1753 */ MCD_OPC_CheckField, 40, 10, 0, 136, 2, 0, // Skip to: 2408 +/* 1760 */ MCD_OPC_CheckField, 26, 1, 1, 129, 2, 0, // Skip to: 2408 +/* 1767 */ MCD_OPC_CheckField, 21, 2, 0, 122, 2, 0, // Skip to: 2408 +/* 1774 */ MCD_OPC_CheckField, 0, 1, 0, 115, 2, 0, // Skip to: 2408 +/* 1781 */ MCD_OPC_Decode, 164, 11, 232, 1, // Opcode: PMXVF32GERNP +/* 1786 */ MCD_OPC_FilterValue, 99, 40, 0, 0, // Skip to: 1831 +/* 1791 */ MCD_OPC_CheckField, 48, 2, 0, 98, 2, 0, // Skip to: 2408 +/* 1798 */ MCD_OPC_CheckField, 40, 4, 0, 91, 2, 0, // Skip to: 2408 +/* 1805 */ MCD_OPC_CheckField, 26, 1, 1, 84, 2, 0, // Skip to: 2408 +/* 1812 */ MCD_OPC_CheckField, 21, 2, 0, 77, 2, 0, // Skip to: 2408 +/* 1819 */ MCD_OPC_CheckField, 0, 1, 0, 70, 2, 0, // Skip to: 2408 +/* 1826 */ MCD_OPC_Decode, 180, 11, 228, 1, // Opcode: PMXVI8GER4SPP +/* 1831 */ MCD_OPC_FilterValue, 107, 40, 0, 0, // Skip to: 1876 +/* 1836 */ MCD_OPC_CheckField, 48, 2, 0, 53, 2, 0, // Skip to: 2408 +/* 1843 */ MCD_OPC_CheckField, 40, 6, 0, 46, 2, 0, // Skip to: 2408 +/* 1850 */ MCD_OPC_CheckField, 26, 1, 1, 39, 2, 0, // Skip to: 2408 +/* 1857 */ MCD_OPC_CheckField, 21, 2, 0, 32, 2, 0, // Skip to: 2408 +/* 1864 */ MCD_OPC_CheckField, 0, 1, 0, 25, 2, 0, // Skip to: 2408 +/* 1871 */ MCD_OPC_Decode, 173, 11, 230, 1, // Opcode: PMXVI16GER2PP +/* 1876 */ MCD_OPC_FilterValue, 114, 40, 0, 0, // Skip to: 1921 +/* 1881 */ MCD_OPC_CheckField, 48, 2, 0, 8, 2, 0, // Skip to: 2408 +/* 1888 */ MCD_OPC_CheckField, 40, 6, 0, 1, 2, 0, // Skip to: 2408 +/* 1895 */ MCD_OPC_CheckField, 26, 1, 1, 250, 1, 0, // Skip to: 2408 +/* 1902 */ MCD_OPC_CheckField, 21, 2, 0, 243, 1, 0, // Skip to: 2408 +/* 1909 */ MCD_OPC_CheckField, 0, 1, 0, 236, 1, 0, // Skip to: 2408 +/* 1916 */ MCD_OPC_Decode, 154, 11, 230, 1, // Opcode: PMXVBF16GER2NP +/* 1921 */ MCD_OPC_FilterValue, 122, 40, 0, 0, // Skip to: 1966 +/* 1926 */ MCD_OPC_CheckField, 40, 10, 0, 219, 1, 0, // Skip to: 2408 +/* 1933 */ MCD_OPC_CheckField, 32, 2, 0, 212, 1, 0, // Skip to: 2408 +/* 1940 */ MCD_OPC_CheckField, 26, 1, 1, 205, 1, 0, // Skip to: 2408 +/* 1947 */ MCD_OPC_CheckField, 21, 2, 0, 198, 1, 0, // Skip to: 2408 +/* 1954 */ MCD_OPC_CheckField, 0, 1, 0, 191, 1, 0, // Skip to: 2408 +/* 1961 */ MCD_OPC_Decode, 169, 11, 236, 1, // Opcode: PMXVF64GERNP +/* 1966 */ MCD_OPC_FilterValue, 146, 1, 40, 0, 0, // Skip to: 2012 +/* 1972 */ MCD_OPC_CheckField, 48, 2, 0, 173, 1, 0, // Skip to: 2408 +/* 1979 */ MCD_OPC_CheckField, 40, 6, 0, 166, 1, 0, // Skip to: 2408 +/* 1986 */ MCD_OPC_CheckField, 26, 1, 1, 159, 1, 0, // Skip to: 2408 +/* 1993 */ MCD_OPC_CheckField, 21, 2, 0, 152, 1, 0, // Skip to: 2408 +/* 2000 */ MCD_OPC_CheckField, 0, 1, 0, 145, 1, 0, // Skip to: 2408 +/* 2007 */ MCD_OPC_Decode, 160, 11, 230, 1, // Opcode: PMXVF16GER2PN +/* 2012 */ MCD_OPC_FilterValue, 154, 1, 33, 0, 0, // Skip to: 2051 +/* 2018 */ MCD_OPC_CheckField, 40, 10, 0, 127, 1, 0, // Skip to: 2408 +/* 2025 */ MCD_OPC_CheckField, 26, 1, 1, 120, 1, 0, // Skip to: 2408 +/* 2032 */ MCD_OPC_CheckField, 21, 2, 0, 113, 1, 0, // Skip to: 2408 +/* 2039 */ MCD_OPC_CheckField, 0, 1, 0, 106, 1, 0, // Skip to: 2408 +/* 2046 */ MCD_OPC_Decode, 165, 11, 232, 1, // Opcode: PMXVF32GERPN +/* 2051 */ MCD_OPC_FilterValue, 178, 1, 40, 0, 0, // Skip to: 2097 +/* 2057 */ MCD_OPC_CheckField, 48, 2, 0, 88, 1, 0, // Skip to: 2408 +/* 2064 */ MCD_OPC_CheckField, 40, 6, 0, 81, 1, 0, // Skip to: 2408 +/* 2071 */ MCD_OPC_CheckField, 26, 1, 1, 74, 1, 0, // Skip to: 2408 +/* 2078 */ MCD_OPC_CheckField, 21, 2, 0, 67, 1, 0, // Skip to: 2408 +/* 2085 */ MCD_OPC_CheckField, 0, 1, 0, 60, 1, 0, // Skip to: 2408 +/* 2092 */ MCD_OPC_Decode, 155, 11, 230, 1, // Opcode: PMXVBF16GER2PN +/* 2097 */ MCD_OPC_FilterValue, 186, 1, 40, 0, 0, // Skip to: 2143 +/* 2103 */ MCD_OPC_CheckField, 40, 10, 0, 42, 1, 0, // Skip to: 2408 +/* 2110 */ MCD_OPC_CheckField, 32, 2, 0, 35, 1, 0, // Skip to: 2408 +/* 2117 */ MCD_OPC_CheckField, 26, 1, 1, 28, 1, 0, // Skip to: 2408 +/* 2124 */ MCD_OPC_CheckField, 21, 2, 0, 21, 1, 0, // Skip to: 2408 +/* 2131 */ MCD_OPC_CheckField, 0, 1, 0, 14, 1, 0, // Skip to: 2408 +/* 2138 */ MCD_OPC_Decode, 170, 11, 236, 1, // Opcode: PMXVF64GERPN +/* 2143 */ MCD_OPC_FilterValue, 210, 1, 40, 0, 0, // Skip to: 2189 +/* 2149 */ MCD_OPC_CheckField, 48, 2, 0, 252, 0, 0, // Skip to: 2408 +/* 2156 */ MCD_OPC_CheckField, 40, 6, 0, 245, 0, 0, // Skip to: 2408 +/* 2163 */ MCD_OPC_CheckField, 26, 1, 1, 238, 0, 0, // Skip to: 2408 +/* 2170 */ MCD_OPC_CheckField, 21, 2, 0, 231, 0, 0, // Skip to: 2408 +/* 2177 */ MCD_OPC_CheckField, 0, 1, 0, 224, 0, 0, // Skip to: 2408 +/* 2184 */ MCD_OPC_Decode, 158, 11, 230, 1, // Opcode: PMXVF16GER2NN +/* 2189 */ MCD_OPC_FilterValue, 218, 1, 33, 0, 0, // Skip to: 2228 +/* 2195 */ MCD_OPC_CheckField, 40, 10, 0, 206, 0, 0, // Skip to: 2408 +/* 2202 */ MCD_OPC_CheckField, 26, 1, 1, 199, 0, 0, // Skip to: 2408 +/* 2209 */ MCD_OPC_CheckField, 21, 2, 0, 192, 0, 0, // Skip to: 2408 +/* 2216 */ MCD_OPC_CheckField, 0, 1, 0, 185, 0, 0, // Skip to: 2408 +/* 2223 */ MCD_OPC_Decode, 163, 11, 232, 1, // Opcode: PMXVF32GERNN +/* 2228 */ MCD_OPC_FilterValue, 242, 1, 40, 0, 0, // Skip to: 2274 +/* 2234 */ MCD_OPC_CheckField, 48, 2, 0, 167, 0, 0, // Skip to: 2408 +/* 2241 */ MCD_OPC_CheckField, 40, 6, 0, 160, 0, 0, // Skip to: 2408 +/* 2248 */ MCD_OPC_CheckField, 26, 1, 1, 153, 0, 0, // Skip to: 2408 +/* 2255 */ MCD_OPC_CheckField, 21, 2, 0, 146, 0, 0, // Skip to: 2408 +/* 2262 */ MCD_OPC_CheckField, 0, 1, 0, 139, 0, 0, // Skip to: 2408 +/* 2269 */ MCD_OPC_Decode, 153, 11, 230, 1, // Opcode: PMXVBF16GER2NN +/* 2274 */ MCD_OPC_FilterValue, 250, 1, 128, 0, 0, // Skip to: 2408 +/* 2280 */ MCD_OPC_CheckField, 40, 10, 0, 121, 0, 0, // Skip to: 2408 +/* 2287 */ MCD_OPC_CheckField, 32, 2, 0, 114, 0, 0, // Skip to: 2408 +/* 2294 */ MCD_OPC_CheckField, 26, 1, 1, 107, 0, 0, // Skip to: 2408 +/* 2301 */ MCD_OPC_CheckField, 21, 2, 0, 100, 0, 0, // Skip to: 2408 +/* 2308 */ MCD_OPC_CheckField, 0, 1, 0, 93, 0, 0, // Skip to: 2408 +/* 2315 */ MCD_OPC_Decode, 168, 11, 236, 1, // Opcode: PMXVF64GERNN +/* 2320 */ MCD_OPC_FilterValue, 30, 39, 0, 0, // Skip to: 2364 +/* 2325 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 2328 */ MCD_OPC_FilterValue, 128, 2, 12, 0, 0, // Skip to: 2346 +/* 2334 */ MCD_OPC_CheckField, 26, 1, 1, 67, 0, 0, // Skip to: 2408 +/* 2341 */ MCD_OPC_Decode, 199, 11, 224, 1, // Opcode: PSTD +/* 2346 */ MCD_OPC_FilterValue, 132, 2, 56, 0, 0, // Skip to: 2408 +/* 2352 */ MCD_OPC_CheckField, 26, 1, 1, 49, 0, 0, // Skip to: 2408 +/* 2359 */ MCD_OPC_Decode, 200, 11, 225, 1, // Opcode: PSTDpc +/* 2364 */ MCD_OPC_FilterValue, 31, 39, 0, 0, // Skip to: 2408 +/* 2369 */ MCD_OPC_ExtractField, 50, 14, // Inst{63-50} ... +/* 2372 */ MCD_OPC_FilterValue, 128, 2, 12, 0, 0, // Skip to: 2390 +/* 2378 */ MCD_OPC_CheckField, 26, 1, 0, 23, 0, 0, // Skip to: 2408 +/* 2385 */ MCD_OPC_Decode, 218, 11, 226, 1, // Opcode: PSTXVP +/* 2390 */ MCD_OPC_FilterValue, 132, 2, 12, 0, 0, // Skip to: 2408 +/* 2396 */ MCD_OPC_CheckField, 26, 1, 0, 5, 0, 0, // Skip to: 2408 +/* 2403 */ MCD_OPC_Decode, 219, 11, 227, 1, // Opcode: PSTXVPpc +/* 2408 */ MCD_OPC_Fail, 0 }; @@ -3807,2760 +4905,3221 @@ static const uint8_t DecoderTableSPE32[] = { /* 3 */ MCD_OPC_FilterValue, 64, 71, 0, 0, // Skip to: 79 /* 8 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 11 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 28 -/* 16 */ MCD_OPC_CheckField, 26, 6, 4, 131, 20, 0, // Skip to: 5274 -/* 23 */ MCD_OPC_Decode, 195, 4, 196, 1, // Opcode: EVADDW +/* 16 */ MCD_OPC_CheckField, 26, 6, 4, 112, 20, 0, // Skip to: 5255 +/* 23 */ MCD_OPC_Decode, 249, 5, 238, 1, // Opcode: EVADDW /* 28 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 45 -/* 33 */ MCD_OPC_CheckField, 26, 6, 4, 114, 20, 0, // Skip to: 5274 -/* 40 */ MCD_OPC_Decode, 190, 4, 197, 1, // Opcode: EVADDIW +/* 33 */ MCD_OPC_CheckField, 26, 6, 4, 95, 20, 0, // Skip to: 5255 +/* 40 */ MCD_OPC_Decode, 244, 5, 239, 1, // Opcode: EVADDIW /* 45 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 62 -/* 50 */ MCD_OPC_CheckField, 26, 6, 4, 97, 20, 0, // Skip to: 5274 -/* 57 */ MCD_OPC_Decode, 253, 5, 196, 1, // Opcode: EVSUBFW -/* 62 */ MCD_OPC_FilterValue, 6, 87, 20, 0, // Skip to: 5274 -/* 67 */ MCD_OPC_CheckField, 26, 6, 4, 80, 20, 0, // Skip to: 5274 -/* 74 */ MCD_OPC_Decode, 254, 5, 198, 1, // Opcode: EVSUBIFW +/* 50 */ MCD_OPC_CheckField, 26, 6, 4, 78, 20, 0, // Skip to: 5255 +/* 57 */ MCD_OPC_Decode, 179, 7, 238, 1, // Opcode: EVSUBFW +/* 62 */ MCD_OPC_FilterValue, 6, 68, 20, 0, // Skip to: 5255 +/* 67 */ MCD_OPC_CheckField, 26, 6, 4, 61, 20, 0, // Skip to: 5255 +/* 74 */ MCD_OPC_Decode, 180, 7, 240, 1, // Opcode: EVSUBIFW /* 79 */ MCD_OPC_FilterValue, 65, 187, 0, 0, // Skip to: 271 /* 84 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 87 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 111 -/* 92 */ MCD_OPC_CheckField, 26, 6, 4, 55, 20, 0, // Skip to: 5274 -/* 99 */ MCD_OPC_CheckField, 11, 5, 0, 48, 20, 0, // Skip to: 5274 -/* 106 */ MCD_OPC_Decode, 189, 4, 199, 1, // Opcode: EVABS +/* 92 */ MCD_OPC_CheckField, 26, 6, 4, 36, 20, 0, // Skip to: 5255 +/* 99 */ MCD_OPC_CheckField, 11, 5, 0, 29, 20, 0, // Skip to: 5255 +/* 106 */ MCD_OPC_Decode, 243, 5, 241, 1, // Opcode: EVABS /* 111 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 135 -/* 116 */ MCD_OPC_CheckField, 26, 6, 4, 31, 20, 0, // Skip to: 5274 -/* 123 */ MCD_OPC_CheckField, 11, 5, 0, 24, 20, 0, // Skip to: 5274 -/* 130 */ MCD_OPC_Decode, 219, 5, 199, 1, // Opcode: EVNEG +/* 116 */ MCD_OPC_CheckField, 26, 6, 4, 12, 20, 0, // Skip to: 5255 +/* 123 */ MCD_OPC_CheckField, 11, 5, 0, 5, 20, 0, // Skip to: 5255 +/* 130 */ MCD_OPC_Decode, 145, 7, 241, 1, // Opcode: EVNEG /* 135 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 159 -/* 140 */ MCD_OPC_CheckField, 26, 6, 4, 7, 20, 0, // Skip to: 5274 -/* 147 */ MCD_OPC_CheckField, 11, 5, 0, 0, 20, 0, // Skip to: 5274 -/* 154 */ MCD_OPC_Decode, 208, 4, 199, 1, // Opcode: EVEXTSB +/* 140 */ MCD_OPC_CheckField, 26, 6, 4, 244, 19, 0, // Skip to: 5255 +/* 147 */ MCD_OPC_CheckField, 11, 5, 0, 237, 19, 0, // Skip to: 5255 +/* 154 */ MCD_OPC_Decode, 134, 6, 241, 1, // Opcode: EVEXTSB /* 159 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 183 -/* 164 */ MCD_OPC_CheckField, 26, 6, 4, 239, 19, 0, // Skip to: 5274 -/* 171 */ MCD_OPC_CheckField, 11, 5, 0, 232, 19, 0, // Skip to: 5274 -/* 178 */ MCD_OPC_Decode, 209, 4, 199, 1, // Opcode: EVEXTSH +/* 164 */ MCD_OPC_CheckField, 26, 6, 4, 220, 19, 0, // Skip to: 5255 +/* 171 */ MCD_OPC_CheckField, 11, 5, 0, 213, 19, 0, // Skip to: 5255 +/* 178 */ MCD_OPC_Decode, 135, 6, 241, 1, // Opcode: EVEXTSH /* 183 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 207 -/* 188 */ MCD_OPC_CheckField, 26, 6, 4, 215, 19, 0, // Skip to: 5274 -/* 195 */ MCD_OPC_CheckField, 11, 5, 0, 208, 19, 0, // Skip to: 5274 -/* 202 */ MCD_OPC_Decode, 225, 5, 199, 1, // Opcode: EVRNDW +/* 188 */ MCD_OPC_CheckField, 26, 6, 4, 196, 19, 0, // Skip to: 5255 +/* 195 */ MCD_OPC_CheckField, 11, 5, 0, 189, 19, 0, // Skip to: 5255 +/* 202 */ MCD_OPC_Decode, 151, 7, 241, 1, // Opcode: EVRNDW /* 207 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 231 -/* 212 */ MCD_OPC_CheckField, 26, 6, 4, 191, 19, 0, // Skip to: 5274 -/* 219 */ MCD_OPC_CheckField, 11, 5, 0, 184, 19, 0, // Skip to: 5274 -/* 226 */ MCD_OPC_Decode, 204, 4, 199, 1, // Opcode: EVCNTLZW +/* 212 */ MCD_OPC_CheckField, 26, 6, 4, 172, 19, 0, // Skip to: 5255 +/* 219 */ MCD_OPC_CheckField, 11, 5, 0, 165, 19, 0, // Skip to: 5255 +/* 226 */ MCD_OPC_Decode, 130, 6, 241, 1, // Opcode: EVCNTLZW /* 231 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 255 -/* 236 */ MCD_OPC_CheckField, 26, 6, 4, 167, 19, 0, // Skip to: 5274 -/* 243 */ MCD_OPC_CheckField, 11, 5, 0, 160, 19, 0, // Skip to: 5274 -/* 250 */ MCD_OPC_Decode, 203, 4, 199, 1, // Opcode: EVCNTLSW -/* 255 */ MCD_OPC_FilterValue, 7, 150, 19, 0, // Skip to: 5274 -/* 260 */ MCD_OPC_CheckField, 26, 6, 4, 143, 19, 0, // Skip to: 5274 -/* 267 */ MCD_OPC_Decode, 163, 3, 62, // Opcode: BRINC +/* 236 */ MCD_OPC_CheckField, 26, 6, 4, 148, 19, 0, // Skip to: 5255 +/* 243 */ MCD_OPC_CheckField, 11, 5, 0, 141, 19, 0, // Skip to: 5255 +/* 250 */ MCD_OPC_Decode, 129, 6, 241, 1, // Opcode: EVCNTLSW +/* 255 */ MCD_OPC_FilterValue, 7, 131, 19, 0, // Skip to: 5255 +/* 260 */ MCD_OPC_CheckField, 26, 6, 4, 124, 19, 0, // Skip to: 5255 +/* 267 */ MCD_OPC_Decode, 200, 4, 80, // Opcode: BRINC /* 271 */ MCD_OPC_FilterValue, 66, 71, 0, 0, // Skip to: 347 /* 276 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 279 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 296 -/* 284 */ MCD_OPC_CheckField, 26, 6, 4, 119, 19, 0, // Skip to: 5274 -/* 291 */ MCD_OPC_Decode, 196, 4, 196, 1, // Opcode: EVAND +/* 284 */ MCD_OPC_CheckField, 26, 6, 4, 100, 19, 0, // Skip to: 5255 +/* 291 */ MCD_OPC_Decode, 250, 5, 238, 1, // Opcode: EVAND /* 296 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 313 -/* 301 */ MCD_OPC_CheckField, 26, 6, 4, 102, 19, 0, // Skip to: 5274 -/* 308 */ MCD_OPC_Decode, 197, 4, 196, 1, // Opcode: EVANDC +/* 301 */ MCD_OPC_CheckField, 26, 6, 4, 83, 19, 0, // Skip to: 5255 +/* 308 */ MCD_OPC_Decode, 251, 5, 238, 1, // Opcode: EVANDC /* 313 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 330 -/* 318 */ MCD_OPC_CheckField, 26, 6, 4, 85, 19, 0, // Skip to: 5274 -/* 325 */ MCD_OPC_Decode, 255, 5, 196, 1, // Opcode: EVXOR -/* 330 */ MCD_OPC_FilterValue, 7, 75, 19, 0, // Skip to: 5274 -/* 335 */ MCD_OPC_CheckField, 26, 6, 4, 68, 19, 0, // Skip to: 5274 -/* 342 */ MCD_OPC_Decode, 221, 5, 196, 1, // Opcode: EVOR +/* 318 */ MCD_OPC_CheckField, 26, 6, 4, 66, 19, 0, // Skip to: 5255 +/* 325 */ MCD_OPC_Decode, 181, 7, 238, 1, // Opcode: EVXOR +/* 330 */ MCD_OPC_FilterValue, 7, 56, 19, 0, // Skip to: 5255 +/* 335 */ MCD_OPC_CheckField, 26, 6, 4, 49, 19, 0, // Skip to: 5255 +/* 342 */ MCD_OPC_Decode, 147, 7, 238, 1, // Opcode: EVOR /* 347 */ MCD_OPC_FilterValue, 67, 71, 0, 0, // Skip to: 423 /* 352 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 355 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 372 -/* 360 */ MCD_OPC_CheckField, 26, 6, 4, 43, 19, 0, // Skip to: 5274 -/* 367 */ MCD_OPC_Decode, 220, 5, 196, 1, // Opcode: EVNOR +/* 360 */ MCD_OPC_CheckField, 26, 6, 4, 24, 19, 0, // Skip to: 5255 +/* 367 */ MCD_OPC_Decode, 146, 7, 238, 1, // Opcode: EVNOR /* 372 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 389 -/* 377 */ MCD_OPC_CheckField, 26, 6, 4, 26, 19, 0, // Skip to: 5274 -/* 384 */ MCD_OPC_Decode, 207, 4, 196, 1, // Opcode: EVEQV +/* 377 */ MCD_OPC_CheckField, 26, 6, 4, 7, 19, 0, // Skip to: 5255 +/* 384 */ MCD_OPC_Decode, 133, 6, 238, 1, // Opcode: EVEQV /* 389 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 406 -/* 394 */ MCD_OPC_CheckField, 26, 6, 4, 9, 19, 0, // Skip to: 5274 -/* 401 */ MCD_OPC_Decode, 222, 5, 196, 1, // Opcode: EVORC -/* 406 */ MCD_OPC_FilterValue, 6, 255, 18, 0, // Skip to: 5274 -/* 411 */ MCD_OPC_CheckField, 26, 6, 4, 248, 18, 0, // Skip to: 5274 -/* 418 */ MCD_OPC_Decode, 218, 5, 196, 1, // Opcode: EVNAND +/* 394 */ MCD_OPC_CheckField, 26, 6, 4, 246, 18, 0, // Skip to: 5255 +/* 401 */ MCD_OPC_Decode, 148, 7, 238, 1, // Opcode: EVORC +/* 406 */ MCD_OPC_FilterValue, 6, 236, 18, 0, // Skip to: 5255 +/* 411 */ MCD_OPC_CheckField, 26, 6, 4, 229, 18, 0, // Skip to: 5255 +/* 418 */ MCD_OPC_Decode, 144, 7, 238, 1, // Opcode: EVNAND /* 423 */ MCD_OPC_FilterValue, 68, 105, 0, 0, // Skip to: 533 /* 428 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 431 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 448 -/* 436 */ MCD_OPC_CheckField, 26, 6, 4, 223, 18, 0, // Skip to: 5274 -/* 443 */ MCD_OPC_Decode, 234, 5, 196, 1, // Opcode: EVSRWU +/* 436 */ MCD_OPC_CheckField, 26, 6, 4, 204, 18, 0, // Skip to: 5255 +/* 443 */ MCD_OPC_Decode, 160, 7, 238, 1, // Opcode: EVSRWU /* 448 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 465 -/* 453 */ MCD_OPC_CheckField, 26, 6, 4, 206, 18, 0, // Skip to: 5274 -/* 460 */ MCD_OPC_Decode, 233, 5, 196, 1, // Opcode: EVSRWS +/* 453 */ MCD_OPC_CheckField, 26, 6, 4, 187, 18, 0, // Skip to: 5255 +/* 460 */ MCD_OPC_Decode, 159, 7, 238, 1, // Opcode: EVSRWS /* 465 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 482 -/* 470 */ MCD_OPC_CheckField, 26, 6, 4, 189, 18, 0, // Skip to: 5274 -/* 477 */ MCD_OPC_Decode, 232, 5, 197, 1, // Opcode: EVSRWIU +/* 470 */ MCD_OPC_CheckField, 26, 6, 4, 170, 18, 0, // Skip to: 5255 +/* 477 */ MCD_OPC_Decode, 158, 7, 239, 1, // Opcode: EVSRWIU /* 482 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 499 -/* 487 */ MCD_OPC_CheckField, 26, 6, 4, 172, 18, 0, // Skip to: 5274 -/* 494 */ MCD_OPC_Decode, 231, 5, 197, 1, // Opcode: EVSRWIS +/* 487 */ MCD_OPC_CheckField, 26, 6, 4, 153, 18, 0, // Skip to: 5255 +/* 494 */ MCD_OPC_Decode, 157, 7, 239, 1, // Opcode: EVSRWIS /* 499 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 516 -/* 504 */ MCD_OPC_CheckField, 26, 6, 4, 155, 18, 0, // Skip to: 5274 -/* 511 */ MCD_OPC_Decode, 227, 5, 196, 1, // Opcode: EVSLW -/* 516 */ MCD_OPC_FilterValue, 6, 145, 18, 0, // Skip to: 5274 -/* 521 */ MCD_OPC_CheckField, 26, 6, 4, 138, 18, 0, // Skip to: 5274 -/* 528 */ MCD_OPC_Decode, 228, 5, 197, 1, // Opcode: EVSLWI +/* 504 */ MCD_OPC_CheckField, 26, 6, 4, 136, 18, 0, // Skip to: 5255 +/* 511 */ MCD_OPC_Decode, 153, 7, 238, 1, // Opcode: EVSLW +/* 516 */ MCD_OPC_FilterValue, 6, 126, 18, 0, // Skip to: 5255 +/* 521 */ MCD_OPC_CheckField, 26, 6, 4, 119, 18, 0, // Skip to: 5255 +/* 528 */ MCD_OPC_Decode, 154, 7, 239, 1, // Opcode: EVSLWI /* 533 */ MCD_OPC_FilterValue, 69, 153, 0, 0, // Skip to: 691 /* 538 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 541 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 558 -/* 546 */ MCD_OPC_CheckField, 26, 6, 4, 113, 18, 0, // Skip to: 5274 -/* 553 */ MCD_OPC_Decode, 223, 5, 196, 1, // Opcode: EVRLW +/* 546 */ MCD_OPC_CheckField, 26, 6, 4, 94, 18, 0, // Skip to: 5255 +/* 553 */ MCD_OPC_Decode, 149, 7, 238, 1, // Opcode: EVRLW /* 558 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 582 -/* 563 */ MCD_OPC_CheckField, 26, 6, 4, 96, 18, 0, // Skip to: 5274 -/* 570 */ MCD_OPC_CheckField, 11, 5, 0, 89, 18, 0, // Skip to: 5274 -/* 577 */ MCD_OPC_Decode, 230, 5, 200, 1, // Opcode: EVSPLATI +/* 563 */ MCD_OPC_CheckField, 26, 6, 4, 77, 18, 0, // Skip to: 5255 +/* 570 */ MCD_OPC_CheckField, 11, 5, 0, 70, 18, 0, // Skip to: 5255 +/* 577 */ MCD_OPC_Decode, 156, 7, 242, 1, // Opcode: EVSPLATI /* 582 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 599 -/* 587 */ MCD_OPC_CheckField, 26, 6, 4, 72, 18, 0, // Skip to: 5274 -/* 594 */ MCD_OPC_Decode, 224, 5, 197, 1, // Opcode: EVRLWI +/* 587 */ MCD_OPC_CheckField, 26, 6, 4, 53, 18, 0, // Skip to: 5255 +/* 594 */ MCD_OPC_Decode, 150, 7, 239, 1, // Opcode: EVRLWI /* 599 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 623 -/* 604 */ MCD_OPC_CheckField, 26, 6, 4, 55, 18, 0, // Skip to: 5274 -/* 611 */ MCD_OPC_CheckField, 11, 5, 0, 48, 18, 0, // Skip to: 5274 -/* 618 */ MCD_OPC_Decode, 229, 5, 200, 1, // Opcode: EVSPLATFI +/* 604 */ MCD_OPC_CheckField, 26, 6, 4, 36, 18, 0, // Skip to: 5255 +/* 611 */ MCD_OPC_CheckField, 11, 5, 0, 29, 18, 0, // Skip to: 5255 +/* 618 */ MCD_OPC_Decode, 155, 7, 242, 1, // Opcode: EVSPLATFI /* 623 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 640 -/* 628 */ MCD_OPC_CheckField, 26, 6, 4, 31, 18, 0, // Skip to: 5274 -/* 635 */ MCD_OPC_Decode, 255, 4, 196, 1, // Opcode: EVMERGEHI +/* 628 */ MCD_OPC_CheckField, 26, 6, 4, 12, 18, 0, // Skip to: 5255 +/* 635 */ MCD_OPC_Decode, 181, 6, 238, 1, // Opcode: EVMERGEHI /* 640 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 657 -/* 645 */ MCD_OPC_CheckField, 26, 6, 4, 14, 18, 0, // Skip to: 5274 -/* 652 */ MCD_OPC_Decode, 129, 5, 196, 1, // Opcode: EVMERGELO +/* 645 */ MCD_OPC_CheckField, 26, 6, 4, 251, 17, 0, // Skip to: 5255 +/* 652 */ MCD_OPC_Decode, 183, 6, 243, 1, // Opcode: EVMERGELO /* 657 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 674 -/* 662 */ MCD_OPC_CheckField, 26, 6, 4, 253, 17, 0, // Skip to: 5274 -/* 669 */ MCD_OPC_Decode, 128, 5, 196, 1, // Opcode: EVMERGEHILO -/* 674 */ MCD_OPC_FilterValue, 7, 243, 17, 0, // Skip to: 5274 -/* 679 */ MCD_OPC_CheckField, 26, 6, 4, 236, 17, 0, // Skip to: 5274 -/* 686 */ MCD_OPC_Decode, 130, 5, 196, 1, // Opcode: EVMERGELOHI +/* 662 */ MCD_OPC_CheckField, 26, 6, 4, 234, 17, 0, // Skip to: 5255 +/* 669 */ MCD_OPC_Decode, 182, 6, 238, 1, // Opcode: EVMERGEHILO +/* 674 */ MCD_OPC_FilterValue, 7, 224, 17, 0, // Skip to: 5255 +/* 679 */ MCD_OPC_CheckField, 26, 6, 4, 217, 17, 0, // Skip to: 5255 +/* 686 */ MCD_OPC_Decode, 184, 6, 238, 1, // Opcode: EVMERGELOHI /* 691 */ MCD_OPC_FilterValue, 70, 123, 0, 0, // Skip to: 819 /* 696 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 699 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 723 -/* 704 */ MCD_OPC_CheckField, 26, 6, 4, 211, 17, 0, // Skip to: 5274 -/* 711 */ MCD_OPC_CheckField, 21, 2, 0, 204, 17, 0, // Skip to: 5274 -/* 718 */ MCD_OPC_Decode, 200, 4, 201, 1, // Opcode: EVCMPGTU +/* 704 */ MCD_OPC_CheckField, 26, 6, 4, 192, 17, 0, // Skip to: 5255 +/* 711 */ MCD_OPC_CheckField, 21, 2, 0, 185, 17, 0, // Skip to: 5255 +/* 718 */ MCD_OPC_Decode, 254, 5, 244, 1, // Opcode: EVCMPGTU /* 723 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 747 -/* 728 */ MCD_OPC_CheckField, 26, 6, 4, 187, 17, 0, // Skip to: 5274 -/* 735 */ MCD_OPC_CheckField, 21, 2, 0, 180, 17, 0, // Skip to: 5274 -/* 742 */ MCD_OPC_Decode, 199, 4, 201, 1, // Opcode: EVCMPGTS +/* 728 */ MCD_OPC_CheckField, 26, 6, 4, 168, 17, 0, // Skip to: 5255 +/* 735 */ MCD_OPC_CheckField, 21, 2, 0, 161, 17, 0, // Skip to: 5255 +/* 742 */ MCD_OPC_Decode, 253, 5, 244, 1, // Opcode: EVCMPGTS /* 747 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 771 -/* 752 */ MCD_OPC_CheckField, 26, 6, 4, 163, 17, 0, // Skip to: 5274 -/* 759 */ MCD_OPC_CheckField, 21, 2, 0, 156, 17, 0, // Skip to: 5274 -/* 766 */ MCD_OPC_Decode, 202, 4, 201, 1, // Opcode: EVCMPLTU +/* 752 */ MCD_OPC_CheckField, 26, 6, 4, 144, 17, 0, // Skip to: 5255 +/* 759 */ MCD_OPC_CheckField, 21, 2, 0, 137, 17, 0, // Skip to: 5255 +/* 766 */ MCD_OPC_Decode, 128, 6, 244, 1, // Opcode: EVCMPLTU /* 771 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 795 -/* 776 */ MCD_OPC_CheckField, 26, 6, 4, 139, 17, 0, // Skip to: 5274 -/* 783 */ MCD_OPC_CheckField, 21, 2, 0, 132, 17, 0, // Skip to: 5274 -/* 790 */ MCD_OPC_Decode, 201, 4, 201, 1, // Opcode: EVCMPLTS -/* 795 */ MCD_OPC_FilterValue, 4, 122, 17, 0, // Skip to: 5274 -/* 800 */ MCD_OPC_CheckField, 26, 6, 4, 115, 17, 0, // Skip to: 5274 -/* 807 */ MCD_OPC_CheckField, 21, 2, 0, 108, 17, 0, // Skip to: 5274 -/* 814 */ MCD_OPC_Decode, 198, 4, 201, 1, // Opcode: EVCMPEQ +/* 776 */ MCD_OPC_CheckField, 26, 6, 4, 120, 17, 0, // Skip to: 5255 +/* 783 */ MCD_OPC_CheckField, 21, 2, 0, 113, 17, 0, // Skip to: 5255 +/* 790 */ MCD_OPC_Decode, 255, 5, 244, 1, // Opcode: EVCMPLTS +/* 795 */ MCD_OPC_FilterValue, 4, 103, 17, 0, // Skip to: 5255 +/* 800 */ MCD_OPC_CheckField, 26, 6, 4, 96, 17, 0, // Skip to: 5255 +/* 807 */ MCD_OPC_CheckField, 21, 2, 0, 89, 17, 0, // Skip to: 5255 +/* 814 */ MCD_OPC_Decode, 252, 5, 244, 1, // Opcode: EVCMPEQ /* 819 */ MCD_OPC_FilterValue, 79, 12, 0, 0, // Skip to: 836 -/* 824 */ MCD_OPC_CheckField, 26, 6, 4, 91, 17, 0, // Skip to: 5274 -/* 831 */ MCD_OPC_Decode, 226, 5, 202, 1, // Opcode: EVSEL +/* 824 */ MCD_OPC_CheckField, 26, 6, 4, 72, 17, 0, // Skip to: 5255 +/* 831 */ MCD_OPC_Decode, 152, 7, 245, 1, // Opcode: EVSEL /* 836 */ MCD_OPC_FilterValue, 80, 109, 0, 0, // Skip to: 950 /* 841 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 844 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 861 -/* 849 */ MCD_OPC_CheckField, 26, 6, 4, 66, 17, 0, // Skip to: 5274 -/* 856 */ MCD_OPC_Decode, 211, 4, 196, 1, // Opcode: EVFSADD +/* 849 */ MCD_OPC_CheckField, 26, 6, 4, 47, 17, 0, // Skip to: 5255 +/* 856 */ MCD_OPC_Decode, 137, 6, 238, 1, // Opcode: EVFSADD /* 861 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 878 -/* 866 */ MCD_OPC_CheckField, 26, 6, 4, 49, 17, 0, // Skip to: 5274 -/* 873 */ MCD_OPC_Decode, 229, 4, 196, 1, // Opcode: EVFSSUB +/* 866 */ MCD_OPC_CheckField, 26, 6, 4, 30, 17, 0, // Skip to: 5255 +/* 873 */ MCD_OPC_Decode, 155, 6, 238, 1, // Opcode: EVFSSUB /* 878 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 902 -/* 883 */ MCD_OPC_CheckField, 26, 6, 4, 32, 17, 0, // Skip to: 5274 -/* 890 */ MCD_OPC_CheckField, 11, 5, 0, 25, 17, 0, // Skip to: 5274 -/* 897 */ MCD_OPC_Decode, 210, 4, 199, 1, // Opcode: EVFSABS +/* 883 */ MCD_OPC_CheckField, 26, 6, 4, 13, 17, 0, // Skip to: 5255 +/* 890 */ MCD_OPC_CheckField, 11, 5, 0, 6, 17, 0, // Skip to: 5255 +/* 897 */ MCD_OPC_Decode, 136, 6, 241, 1, // Opcode: EVFSABS /* 902 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 926 -/* 907 */ MCD_OPC_CheckField, 26, 6, 4, 8, 17, 0, // Skip to: 5274 -/* 914 */ MCD_OPC_CheckField, 11, 5, 0, 1, 17, 0, // Skip to: 5274 -/* 921 */ MCD_OPC_Decode, 227, 4, 199, 1, // Opcode: EVFSNABS -/* 926 */ MCD_OPC_FilterValue, 6, 247, 16, 0, // Skip to: 5274 -/* 931 */ MCD_OPC_CheckField, 26, 6, 4, 240, 16, 0, // Skip to: 5274 -/* 938 */ MCD_OPC_CheckField, 11, 5, 0, 233, 16, 0, // Skip to: 5274 -/* 945 */ MCD_OPC_Decode, 228, 4, 199, 1, // Opcode: EVFSNEG +/* 907 */ MCD_OPC_CheckField, 26, 6, 4, 245, 16, 0, // Skip to: 5255 +/* 914 */ MCD_OPC_CheckField, 11, 5, 0, 238, 16, 0, // Skip to: 5255 +/* 921 */ MCD_OPC_Decode, 153, 6, 241, 1, // Opcode: EVFSNABS +/* 926 */ MCD_OPC_FilterValue, 6, 228, 16, 0, // Skip to: 5255 +/* 931 */ MCD_OPC_CheckField, 26, 6, 4, 221, 16, 0, // Skip to: 5255 +/* 938 */ MCD_OPC_CheckField, 11, 5, 0, 214, 16, 0, // Skip to: 5255 +/* 945 */ MCD_OPC_Decode, 154, 6, 241, 1, // Opcode: EVFSNEG /* 950 */ MCD_OPC_FilterValue, 81, 133, 0, 0, // Skip to: 1088 /* 955 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 958 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 975 -/* 963 */ MCD_OPC_CheckField, 26, 6, 4, 208, 16, 0, // Skip to: 5274 -/* 970 */ MCD_OPC_Decode, 226, 4, 196, 1, // Opcode: EVFSMUL +/* 963 */ MCD_OPC_CheckField, 26, 6, 4, 189, 16, 0, // Skip to: 5255 +/* 970 */ MCD_OPC_Decode, 152, 6, 238, 1, // Opcode: EVFSMUL /* 975 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 992 -/* 980 */ MCD_OPC_CheckField, 26, 6, 4, 191, 16, 0, // Skip to: 5274 -/* 987 */ MCD_OPC_Decode, 225, 4, 196, 1, // Opcode: EVFSDIV +/* 980 */ MCD_OPC_CheckField, 26, 6, 4, 172, 16, 0, // Skip to: 5255 +/* 987 */ MCD_OPC_Decode, 151, 6, 238, 1, // Opcode: EVFSDIV /* 992 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1016 -/* 997 */ MCD_OPC_CheckField, 26, 6, 4, 174, 16, 0, // Skip to: 5274 -/* 1004 */ MCD_OPC_CheckField, 16, 5, 0, 167, 16, 0, // Skip to: 5274 -/* 1011 */ MCD_OPC_Decode, 215, 4, 203, 1, // Opcode: EVFSCFUI +/* 997 */ MCD_OPC_CheckField, 26, 6, 4, 155, 16, 0, // Skip to: 5255 +/* 1004 */ MCD_OPC_CheckField, 16, 5, 0, 148, 16, 0, // Skip to: 5255 +/* 1011 */ MCD_OPC_Decode, 141, 6, 246, 1, // Opcode: EVFSCFUI /* 1016 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1040 -/* 1021 */ MCD_OPC_CheckField, 26, 6, 4, 150, 16, 0, // Skip to: 5274 -/* 1028 */ MCD_OPC_CheckField, 21, 2, 0, 143, 16, 0, // Skip to: 5274 -/* 1035 */ MCD_OPC_Decode, 217, 4, 201, 1, // Opcode: EVFSCMPGT +/* 1021 */ MCD_OPC_CheckField, 26, 6, 4, 131, 16, 0, // Skip to: 5255 +/* 1028 */ MCD_OPC_CheckField, 21, 2, 0, 124, 16, 0, // Skip to: 5255 +/* 1035 */ MCD_OPC_Decode, 143, 6, 244, 1, // Opcode: EVFSCMPGT /* 1040 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1064 -/* 1045 */ MCD_OPC_CheckField, 26, 6, 4, 126, 16, 0, // Skip to: 5274 -/* 1052 */ MCD_OPC_CheckField, 21, 2, 0, 119, 16, 0, // Skip to: 5274 -/* 1059 */ MCD_OPC_Decode, 218, 4, 201, 1, // Opcode: EVFSCMPLT -/* 1064 */ MCD_OPC_FilterValue, 6, 109, 16, 0, // Skip to: 5274 -/* 1069 */ MCD_OPC_CheckField, 26, 6, 4, 102, 16, 0, // Skip to: 5274 -/* 1076 */ MCD_OPC_CheckField, 21, 2, 0, 95, 16, 0, // Skip to: 5274 -/* 1083 */ MCD_OPC_Decode, 216, 4, 201, 1, // Opcode: EVFSCMPEQ +/* 1045 */ MCD_OPC_CheckField, 26, 6, 4, 107, 16, 0, // Skip to: 5255 +/* 1052 */ MCD_OPC_CheckField, 21, 2, 0, 100, 16, 0, // Skip to: 5255 +/* 1059 */ MCD_OPC_Decode, 144, 6, 244, 1, // Opcode: EVFSCMPLT +/* 1064 */ MCD_OPC_FilterValue, 6, 90, 16, 0, // Skip to: 5255 +/* 1069 */ MCD_OPC_CheckField, 26, 6, 4, 83, 16, 0, // Skip to: 5255 +/* 1076 */ MCD_OPC_CheckField, 21, 2, 0, 76, 16, 0, // Skip to: 5255 +/* 1083 */ MCD_OPC_Decode, 142, 6, 244, 1, // Opcode: EVFSCMPEQ /* 1088 */ MCD_OPC_FilterValue, 82, 171, 0, 0, // Skip to: 1264 /* 1093 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 1096 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 1120 -/* 1101 */ MCD_OPC_CheckField, 26, 6, 4, 70, 16, 0, // Skip to: 5274 -/* 1108 */ MCD_OPC_CheckField, 16, 5, 0, 63, 16, 0, // Skip to: 5274 -/* 1115 */ MCD_OPC_Decode, 213, 4, 203, 1, // Opcode: EVFSCFSI +/* 1101 */ MCD_OPC_CheckField, 26, 6, 4, 51, 16, 0, // Skip to: 5255 +/* 1108 */ MCD_OPC_CheckField, 16, 5, 0, 44, 16, 0, // Skip to: 5255 +/* 1115 */ MCD_OPC_Decode, 139, 6, 246, 1, // Opcode: EVFSCFSI /* 1120 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1144 -/* 1125 */ MCD_OPC_CheckField, 26, 6, 4, 46, 16, 0, // Skip to: 5274 -/* 1132 */ MCD_OPC_CheckField, 16, 5, 0, 39, 16, 0, // Skip to: 5274 -/* 1139 */ MCD_OPC_Decode, 214, 4, 203, 1, // Opcode: EVFSCFUF +/* 1125 */ MCD_OPC_CheckField, 26, 6, 4, 27, 16, 0, // Skip to: 5255 +/* 1132 */ MCD_OPC_CheckField, 16, 5, 0, 20, 16, 0, // Skip to: 5255 +/* 1139 */ MCD_OPC_Decode, 140, 6, 246, 1, // Opcode: EVFSCFUF /* 1144 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 1168 -/* 1149 */ MCD_OPC_CheckField, 26, 6, 4, 22, 16, 0, // Skip to: 5274 -/* 1156 */ MCD_OPC_CheckField, 16, 5, 0, 15, 16, 0, // Skip to: 5274 -/* 1163 */ MCD_OPC_Decode, 212, 4, 203, 1, // Opcode: EVFSCFSF +/* 1149 */ MCD_OPC_CheckField, 26, 6, 4, 3, 16, 0, // Skip to: 5255 +/* 1156 */ MCD_OPC_CheckField, 16, 5, 0, 252, 15, 0, // Skip to: 5255 +/* 1163 */ MCD_OPC_Decode, 138, 6, 246, 1, // Opcode: EVFSCFSF /* 1168 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1192 -/* 1173 */ MCD_OPC_CheckField, 26, 6, 4, 254, 15, 0, // Skip to: 5274 -/* 1180 */ MCD_OPC_CheckField, 16, 5, 0, 247, 15, 0, // Skip to: 5274 -/* 1187 */ MCD_OPC_Decode, 223, 4, 203, 1, // Opcode: EVFSCTUI +/* 1173 */ MCD_OPC_CheckField, 26, 6, 4, 235, 15, 0, // Skip to: 5255 +/* 1180 */ MCD_OPC_CheckField, 16, 5, 0, 228, 15, 0, // Skip to: 5255 +/* 1187 */ MCD_OPC_Decode, 149, 6, 246, 1, // Opcode: EVFSCTUI /* 1192 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1216 -/* 1197 */ MCD_OPC_CheckField, 26, 6, 4, 230, 15, 0, // Skip to: 5274 -/* 1204 */ MCD_OPC_CheckField, 16, 5, 0, 223, 15, 0, // Skip to: 5274 -/* 1211 */ MCD_OPC_Decode, 220, 4, 203, 1, // Opcode: EVFSCTSI +/* 1197 */ MCD_OPC_CheckField, 26, 6, 4, 211, 15, 0, // Skip to: 5255 +/* 1204 */ MCD_OPC_CheckField, 16, 5, 0, 204, 15, 0, // Skip to: 5255 +/* 1211 */ MCD_OPC_Decode, 146, 6, 246, 1, // Opcode: EVFSCTSI /* 1216 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 1240 -/* 1221 */ MCD_OPC_CheckField, 26, 6, 4, 206, 15, 0, // Skip to: 5274 -/* 1228 */ MCD_OPC_CheckField, 16, 5, 0, 199, 15, 0, // Skip to: 5274 -/* 1235 */ MCD_OPC_Decode, 222, 4, 203, 1, // Opcode: EVFSCTUF -/* 1240 */ MCD_OPC_FilterValue, 7, 189, 15, 0, // Skip to: 5274 -/* 1245 */ MCD_OPC_CheckField, 26, 6, 4, 182, 15, 0, // Skip to: 5274 -/* 1252 */ MCD_OPC_CheckField, 16, 5, 0, 175, 15, 0, // Skip to: 5274 -/* 1259 */ MCD_OPC_Decode, 219, 4, 203, 1, // Opcode: EVFSCTSF +/* 1221 */ MCD_OPC_CheckField, 26, 6, 4, 187, 15, 0, // Skip to: 5255 +/* 1228 */ MCD_OPC_CheckField, 16, 5, 0, 180, 15, 0, // Skip to: 5255 +/* 1235 */ MCD_OPC_Decode, 148, 6, 246, 1, // Opcode: EVFSCTUF +/* 1240 */ MCD_OPC_FilterValue, 7, 170, 15, 0, // Skip to: 5255 +/* 1245 */ MCD_OPC_CheckField, 26, 6, 4, 163, 15, 0, // Skip to: 5255 +/* 1252 */ MCD_OPC_CheckField, 16, 5, 0, 156, 15, 0, // Skip to: 5255 +/* 1259 */ MCD_OPC_Decode, 145, 6, 246, 1, // Opcode: EVFSCTSF /* 1264 */ MCD_OPC_FilterValue, 83, 123, 0, 0, // Skip to: 1392 /* 1269 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 1272 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1296 -/* 1277 */ MCD_OPC_CheckField, 26, 6, 4, 150, 15, 0, // Skip to: 5274 -/* 1284 */ MCD_OPC_CheckField, 16, 5, 0, 143, 15, 0, // Skip to: 5274 -/* 1291 */ MCD_OPC_Decode, 224, 4, 203, 1, // Opcode: EVFSCTUIZ +/* 1277 */ MCD_OPC_CheckField, 26, 6, 4, 131, 15, 0, // Skip to: 5255 +/* 1284 */ MCD_OPC_CheckField, 16, 5, 0, 124, 15, 0, // Skip to: 5255 +/* 1291 */ MCD_OPC_Decode, 150, 6, 246, 1, // Opcode: EVFSCTUIZ /* 1296 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1320 -/* 1301 */ MCD_OPC_CheckField, 26, 6, 4, 126, 15, 0, // Skip to: 5274 -/* 1308 */ MCD_OPC_CheckField, 16, 5, 0, 119, 15, 0, // Skip to: 5274 -/* 1315 */ MCD_OPC_Decode, 221, 4, 203, 1, // Opcode: EVFSCTSIZ +/* 1301 */ MCD_OPC_CheckField, 26, 6, 4, 107, 15, 0, // Skip to: 5255 +/* 1308 */ MCD_OPC_CheckField, 16, 5, 0, 100, 15, 0, // Skip to: 5255 +/* 1315 */ MCD_OPC_Decode, 147, 6, 246, 1, // Opcode: EVFSCTSIZ /* 1320 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1344 -/* 1325 */ MCD_OPC_CheckField, 26, 6, 4, 102, 15, 0, // Skip to: 5274 -/* 1332 */ MCD_OPC_CheckField, 21, 2, 0, 95, 15, 0, // Skip to: 5274 -/* 1339 */ MCD_OPC_Decode, 231, 4, 201, 1, // Opcode: EVFSTSTGT +/* 1325 */ MCD_OPC_CheckField, 26, 6, 4, 83, 15, 0, // Skip to: 5255 +/* 1332 */ MCD_OPC_CheckField, 21, 2, 0, 76, 15, 0, // Skip to: 5255 +/* 1339 */ MCD_OPC_Decode, 157, 6, 244, 1, // Opcode: EVFSTSTGT /* 1344 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1368 -/* 1349 */ MCD_OPC_CheckField, 26, 6, 4, 78, 15, 0, // Skip to: 5274 -/* 1356 */ MCD_OPC_CheckField, 21, 2, 0, 71, 15, 0, // Skip to: 5274 -/* 1363 */ MCD_OPC_Decode, 232, 4, 201, 1, // Opcode: EVFSTSTLT -/* 1368 */ MCD_OPC_FilterValue, 6, 61, 15, 0, // Skip to: 5274 -/* 1373 */ MCD_OPC_CheckField, 26, 6, 4, 54, 15, 0, // Skip to: 5274 -/* 1380 */ MCD_OPC_CheckField, 21, 2, 0, 47, 15, 0, // Skip to: 5274 -/* 1387 */ MCD_OPC_Decode, 230, 4, 201, 1, // Opcode: EVFSTSTEQ -/* 1392 */ MCD_OPC_FilterValue, 88, 109, 0, 0, // Skip to: 1506 +/* 1349 */ MCD_OPC_CheckField, 26, 6, 4, 59, 15, 0, // Skip to: 5255 +/* 1356 */ MCD_OPC_CheckField, 21, 2, 0, 52, 15, 0, // Skip to: 5255 +/* 1363 */ MCD_OPC_Decode, 158, 6, 244, 1, // Opcode: EVFSTSTLT +/* 1368 */ MCD_OPC_FilterValue, 6, 42, 15, 0, // Skip to: 5255 +/* 1373 */ MCD_OPC_CheckField, 26, 6, 4, 35, 15, 0, // Skip to: 5255 +/* 1380 */ MCD_OPC_CheckField, 21, 2, 0, 28, 15, 0, // Skip to: 5255 +/* 1387 */ MCD_OPC_Decode, 156, 6, 244, 1, // Opcode: EVFSTSTEQ +/* 1392 */ MCD_OPC_FilterValue, 88, 104, 0, 0, // Skip to: 1501 /* 1397 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 1400 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1417 -/* 1405 */ MCD_OPC_CheckField, 26, 6, 4, 22, 15, 0, // Skip to: 5274 -/* 1412 */ MCD_OPC_Decode, 157, 4, 204, 1, // Opcode: EFSADD -/* 1417 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 1434 -/* 1422 */ MCD_OPC_CheckField, 26, 6, 4, 5, 15, 0, // Skip to: 5274 -/* 1429 */ MCD_OPC_Decode, 176, 4, 204, 1, // Opcode: EFSSUB -/* 1434 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1458 -/* 1439 */ MCD_OPC_CheckField, 26, 6, 4, 244, 14, 0, // Skip to: 5274 -/* 1446 */ MCD_OPC_CheckField, 11, 5, 0, 237, 14, 0, // Skip to: 5274 -/* 1453 */ MCD_OPC_Decode, 156, 4, 205, 1, // Opcode: EFSABS -/* 1458 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1482 -/* 1463 */ MCD_OPC_CheckField, 26, 6, 4, 220, 14, 0, // Skip to: 5274 -/* 1470 */ MCD_OPC_CheckField, 11, 5, 0, 213, 14, 0, // Skip to: 5274 -/* 1477 */ MCD_OPC_Decode, 174, 4, 205, 1, // Opcode: EFSNABS -/* 1482 */ MCD_OPC_FilterValue, 6, 203, 14, 0, // Skip to: 5274 -/* 1487 */ MCD_OPC_CheckField, 26, 6, 4, 196, 14, 0, // Skip to: 5274 -/* 1494 */ MCD_OPC_CheckField, 11, 5, 0, 189, 14, 0, // Skip to: 5274 -/* 1501 */ MCD_OPC_Decode, 175, 4, 205, 1, // Opcode: EFSNEG -/* 1506 */ MCD_OPC_FilterValue, 89, 133, 0, 0, // Skip to: 1644 -/* 1511 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 1514 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1531 -/* 1519 */ MCD_OPC_CheckField, 26, 6, 4, 164, 14, 0, // Skip to: 5274 -/* 1526 */ MCD_OPC_Decode, 173, 4, 204, 1, // Opcode: EFSMUL -/* 1531 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 1548 -/* 1536 */ MCD_OPC_CheckField, 26, 6, 4, 147, 14, 0, // Skip to: 5274 -/* 1543 */ MCD_OPC_Decode, 172, 4, 204, 1, // Opcode: EFSDIV -/* 1548 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1572 -/* 1553 */ MCD_OPC_CheckField, 26, 6, 4, 130, 14, 0, // Skip to: 5274 -/* 1560 */ MCD_OPC_CheckField, 21, 2, 0, 123, 14, 0, // Skip to: 5274 -/* 1567 */ MCD_OPC_Decode, 164, 4, 206, 1, // Opcode: EFSCMPGT -/* 1572 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1596 -/* 1577 */ MCD_OPC_CheckField, 26, 6, 4, 106, 14, 0, // Skip to: 5274 -/* 1584 */ MCD_OPC_CheckField, 21, 2, 0, 99, 14, 0, // Skip to: 5274 -/* 1591 */ MCD_OPC_Decode, 165, 4, 206, 1, // Opcode: EFSCMPLT -/* 1596 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 1620 -/* 1601 */ MCD_OPC_CheckField, 26, 6, 4, 82, 14, 0, // Skip to: 5274 -/* 1608 */ MCD_OPC_CheckField, 21, 2, 0, 75, 14, 0, // Skip to: 5274 -/* 1615 */ MCD_OPC_Decode, 163, 4, 206, 1, // Opcode: EFSCMPEQ -/* 1620 */ MCD_OPC_FilterValue, 7, 65, 14, 0, // Skip to: 5274 -/* 1625 */ MCD_OPC_CheckField, 26, 6, 4, 58, 14, 0, // Skip to: 5274 -/* 1632 */ MCD_OPC_CheckField, 16, 5, 0, 51, 14, 0, // Skip to: 5274 -/* 1639 */ MCD_OPC_Decode, 158, 4, 207, 1, // Opcode: EFSCFD -/* 1644 */ MCD_OPC_FilterValue, 90, 195, 0, 0, // Skip to: 1844 -/* 1649 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 1652 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1676 -/* 1657 */ MCD_OPC_CheckField, 26, 6, 4, 26, 14, 0, // Skip to: 5274 -/* 1664 */ MCD_OPC_CheckField, 16, 5, 0, 19, 14, 0, // Skip to: 5274 -/* 1671 */ MCD_OPC_Decode, 162, 4, 208, 1, // Opcode: EFSCFUI -/* 1676 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 1700 -/* 1681 */ MCD_OPC_CheckField, 26, 6, 4, 2, 14, 0, // Skip to: 5274 -/* 1688 */ MCD_OPC_CheckField, 16, 5, 0, 251, 13, 0, // Skip to: 5274 -/* 1695 */ MCD_OPC_Decode, 160, 4, 208, 1, // Opcode: EFSCFSI -/* 1700 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1724 -/* 1705 */ MCD_OPC_CheckField, 26, 6, 4, 234, 13, 0, // Skip to: 5274 -/* 1712 */ MCD_OPC_CheckField, 16, 5, 0, 227, 13, 0, // Skip to: 5274 -/* 1719 */ MCD_OPC_Decode, 161, 4, 209, 1, // Opcode: EFSCFUF -/* 1724 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 1748 -/* 1729 */ MCD_OPC_CheckField, 26, 6, 4, 210, 13, 0, // Skip to: 5274 -/* 1736 */ MCD_OPC_CheckField, 16, 5, 0, 203, 13, 0, // Skip to: 5274 -/* 1743 */ MCD_OPC_Decode, 159, 4, 209, 1, // Opcode: EFSCFSF -/* 1748 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1772 -/* 1753 */ MCD_OPC_CheckField, 26, 6, 4, 186, 13, 0, // Skip to: 5274 -/* 1760 */ MCD_OPC_CheckField, 16, 5, 0, 179, 13, 0, // Skip to: 5274 -/* 1767 */ MCD_OPC_Decode, 170, 4, 210, 1, // Opcode: EFSCTUI -/* 1772 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1796 -/* 1777 */ MCD_OPC_CheckField, 26, 6, 4, 162, 13, 0, // Skip to: 5274 -/* 1784 */ MCD_OPC_CheckField, 16, 5, 0, 155, 13, 0, // Skip to: 5274 -/* 1791 */ MCD_OPC_Decode, 167, 4, 210, 1, // Opcode: EFSCTSI -/* 1796 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 1820 -/* 1801 */ MCD_OPC_CheckField, 26, 6, 4, 138, 13, 0, // Skip to: 5274 -/* 1808 */ MCD_OPC_CheckField, 16, 5, 0, 131, 13, 0, // Skip to: 5274 -/* 1815 */ MCD_OPC_Decode, 169, 4, 211, 1, // Opcode: EFSCTUF -/* 1820 */ MCD_OPC_FilterValue, 7, 121, 13, 0, // Skip to: 5274 -/* 1825 */ MCD_OPC_CheckField, 26, 6, 4, 114, 13, 0, // Skip to: 5274 -/* 1832 */ MCD_OPC_CheckField, 16, 5, 0, 107, 13, 0, // Skip to: 5274 -/* 1839 */ MCD_OPC_Decode, 166, 4, 209, 1, // Opcode: EFSCTSF -/* 1844 */ MCD_OPC_FilterValue, 91, 123, 0, 0, // Skip to: 1972 -/* 1849 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 1852 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1876 -/* 1857 */ MCD_OPC_CheckField, 26, 6, 4, 82, 13, 0, // Skip to: 5274 -/* 1864 */ MCD_OPC_CheckField, 16, 5, 0, 75, 13, 0, // Skip to: 5274 -/* 1871 */ MCD_OPC_Decode, 171, 4, 210, 1, // Opcode: EFSCTUIZ -/* 1876 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1900 -/* 1881 */ MCD_OPC_CheckField, 26, 6, 4, 58, 13, 0, // Skip to: 5274 -/* 1888 */ MCD_OPC_CheckField, 16, 5, 0, 51, 13, 0, // Skip to: 5274 -/* 1895 */ MCD_OPC_Decode, 168, 4, 210, 1, // Opcode: EFSCTSIZ -/* 1900 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1924 -/* 1905 */ MCD_OPC_CheckField, 26, 6, 4, 34, 13, 0, // Skip to: 5274 -/* 1912 */ MCD_OPC_CheckField, 21, 2, 0, 27, 13, 0, // Skip to: 5274 -/* 1919 */ MCD_OPC_Decode, 178, 4, 201, 1, // Opcode: EFSTSTGT -/* 1924 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1948 -/* 1929 */ MCD_OPC_CheckField, 26, 6, 4, 10, 13, 0, // Skip to: 5274 -/* 1936 */ MCD_OPC_CheckField, 21, 2, 0, 3, 13, 0, // Skip to: 5274 -/* 1943 */ MCD_OPC_Decode, 179, 4, 201, 1, // Opcode: EFSTSTLT -/* 1948 */ MCD_OPC_FilterValue, 6, 249, 12, 0, // Skip to: 5274 -/* 1953 */ MCD_OPC_CheckField, 26, 6, 4, 242, 12, 0, // Skip to: 5274 -/* 1960 */ MCD_OPC_CheckField, 21, 2, 0, 235, 12, 0, // Skip to: 5274 -/* 1967 */ MCD_OPC_Decode, 177, 4, 201, 1, // Opcode: EFSTSTEQ -/* 1972 */ MCD_OPC_FilterValue, 92, 157, 0, 0, // Skip to: 2134 -/* 1977 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 1980 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1997 -/* 1985 */ MCD_OPC_CheckField, 26, 6, 4, 210, 12, 0, // Skip to: 5274 -/* 1992 */ MCD_OPC_Decode, 129, 4, 196, 1, // Opcode: EFDADD -/* 1997 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2014 -/* 2002 */ MCD_OPC_CheckField, 26, 6, 4, 193, 12, 0, // Skip to: 5274 -/* 2009 */ MCD_OPC_Decode, 152, 4, 196, 1, // Opcode: EFDSUB -/* 2014 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2038 -/* 2019 */ MCD_OPC_CheckField, 26, 6, 4, 176, 12, 0, // Skip to: 5274 -/* 2026 */ MCD_OPC_CheckField, 16, 5, 0, 169, 12, 0, // Skip to: 5274 -/* 2033 */ MCD_OPC_Decode, 136, 4, 212, 1, // Opcode: EFDCFUID -/* 2038 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2062 -/* 2043 */ MCD_OPC_CheckField, 26, 6, 4, 152, 12, 0, // Skip to: 5274 -/* 2050 */ MCD_OPC_CheckField, 16, 5, 0, 145, 12, 0, // Skip to: 5274 -/* 2057 */ MCD_OPC_Decode, 133, 4, 212, 1, // Opcode: EFDCFSID -/* 2062 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2086 -/* 2067 */ MCD_OPC_CheckField, 26, 6, 4, 128, 12, 0, // Skip to: 5274 -/* 2074 */ MCD_OPC_CheckField, 11, 5, 0, 121, 12, 0, // Skip to: 5274 -/* 2081 */ MCD_OPC_Decode, 128, 4, 199, 1, // Opcode: EFDABS -/* 2086 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2110 -/* 2091 */ MCD_OPC_CheckField, 26, 6, 4, 104, 12, 0, // Skip to: 5274 -/* 2098 */ MCD_OPC_CheckField, 11, 5, 0, 97, 12, 0, // Skip to: 5274 -/* 2105 */ MCD_OPC_Decode, 150, 4, 199, 1, // Opcode: EFDNABS -/* 2110 */ MCD_OPC_FilterValue, 6, 87, 12, 0, // Skip to: 5274 -/* 2115 */ MCD_OPC_CheckField, 26, 6, 4, 80, 12, 0, // Skip to: 5274 -/* 2122 */ MCD_OPC_CheckField, 11, 5, 0, 73, 12, 0, // Skip to: 5274 -/* 2129 */ MCD_OPC_Decode, 151, 4, 199, 1, // Opcode: EFDNEG -/* 2134 */ MCD_OPC_FilterValue, 93, 181, 0, 0, // Skip to: 2320 -/* 2139 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 2142 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2159 -/* 2147 */ MCD_OPC_CheckField, 26, 6, 4, 48, 12, 0, // Skip to: 5274 -/* 2154 */ MCD_OPC_Decode, 149, 4, 196, 1, // Opcode: EFDMUL -/* 2159 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2176 -/* 2164 */ MCD_OPC_CheckField, 26, 6, 4, 31, 12, 0, // Skip to: 5274 -/* 2171 */ MCD_OPC_Decode, 148, 4, 196, 1, // Opcode: EFDDIV -/* 2176 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2200 -/* 2181 */ MCD_OPC_CheckField, 26, 6, 4, 14, 12, 0, // Skip to: 5274 -/* 2188 */ MCD_OPC_CheckField, 16, 5, 0, 7, 12, 0, // Skip to: 5274 -/* 2195 */ MCD_OPC_Decode, 146, 4, 213, 1, // Opcode: EFDCTUIDZ -/* 2200 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2224 -/* 2205 */ MCD_OPC_CheckField, 26, 6, 4, 246, 11, 0, // Skip to: 5274 -/* 2212 */ MCD_OPC_CheckField, 16, 5, 0, 239, 11, 0, // Skip to: 5274 -/* 2219 */ MCD_OPC_Decode, 142, 4, 213, 1, // Opcode: EFDCTSIDZ -/* 2224 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2248 -/* 2229 */ MCD_OPC_CheckField, 26, 6, 4, 222, 11, 0, // Skip to: 5274 -/* 2236 */ MCD_OPC_CheckField, 21, 2, 0, 215, 11, 0, // Skip to: 5274 -/* 2243 */ MCD_OPC_Decode, 138, 4, 201, 1, // Opcode: EFDCMPGT -/* 2248 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2272 -/* 2253 */ MCD_OPC_CheckField, 26, 6, 4, 198, 11, 0, // Skip to: 5274 -/* 2260 */ MCD_OPC_CheckField, 21, 2, 0, 191, 11, 0, // Skip to: 5274 -/* 2267 */ MCD_OPC_Decode, 139, 4, 201, 1, // Opcode: EFDCMPLT -/* 2272 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 2296 -/* 2277 */ MCD_OPC_CheckField, 26, 6, 4, 174, 11, 0, // Skip to: 5274 -/* 2284 */ MCD_OPC_CheckField, 21, 2, 0, 167, 11, 0, // Skip to: 5274 -/* 2291 */ MCD_OPC_Decode, 137, 4, 201, 1, // Opcode: EFDCMPEQ -/* 2296 */ MCD_OPC_FilterValue, 7, 157, 11, 0, // Skip to: 5274 -/* 2301 */ MCD_OPC_CheckField, 26, 6, 4, 150, 11, 0, // Skip to: 5274 -/* 2308 */ MCD_OPC_CheckField, 16, 5, 0, 143, 11, 0, // Skip to: 5274 -/* 2315 */ MCD_OPC_Decode, 130, 4, 211, 1, // Opcode: EFDCFS -/* 2320 */ MCD_OPC_FilterValue, 94, 195, 0, 0, // Skip to: 2520 -/* 2325 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 2328 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2352 -/* 2333 */ MCD_OPC_CheckField, 26, 6, 4, 118, 11, 0, // Skip to: 5274 -/* 2340 */ MCD_OPC_CheckField, 16, 5, 0, 111, 11, 0, // Skip to: 5274 -/* 2347 */ MCD_OPC_Decode, 135, 4, 212, 1, // Opcode: EFDCFUI -/* 2352 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 2376 -/* 2357 */ MCD_OPC_CheckField, 26, 6, 4, 94, 11, 0, // Skip to: 5274 -/* 2364 */ MCD_OPC_CheckField, 16, 5, 0, 87, 11, 0, // Skip to: 5274 -/* 2371 */ MCD_OPC_Decode, 132, 4, 212, 1, // Opcode: EFDCFSI -/* 2376 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2400 -/* 2381 */ MCD_OPC_CheckField, 26, 6, 4, 70, 11, 0, // Skip to: 5274 -/* 2388 */ MCD_OPC_CheckField, 16, 5, 0, 63, 11, 0, // Skip to: 5274 -/* 2395 */ MCD_OPC_Decode, 134, 4, 211, 1, // Opcode: EFDCFUF -/* 2400 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2424 -/* 2405 */ MCD_OPC_CheckField, 26, 6, 4, 46, 11, 0, // Skip to: 5274 -/* 2412 */ MCD_OPC_CheckField, 16, 5, 0, 39, 11, 0, // Skip to: 5274 -/* 2419 */ MCD_OPC_Decode, 131, 4, 211, 1, // Opcode: EFDCFSF -/* 2424 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2448 -/* 2429 */ MCD_OPC_CheckField, 26, 6, 4, 22, 11, 0, // Skip to: 5274 -/* 2436 */ MCD_OPC_CheckField, 16, 5, 0, 15, 11, 0, // Skip to: 5274 -/* 2443 */ MCD_OPC_Decode, 145, 4, 213, 1, // Opcode: EFDCTUI -/* 2448 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2472 -/* 2453 */ MCD_OPC_CheckField, 26, 6, 4, 254, 10, 0, // Skip to: 5274 -/* 2460 */ MCD_OPC_CheckField, 16, 5, 0, 247, 10, 0, // Skip to: 5274 -/* 2467 */ MCD_OPC_Decode, 141, 4, 213, 1, // Opcode: EFDCTSI -/* 2472 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 2496 -/* 2477 */ MCD_OPC_CheckField, 26, 6, 4, 230, 10, 0, // Skip to: 5274 -/* 2484 */ MCD_OPC_CheckField, 16, 5, 0, 223, 10, 0, // Skip to: 5274 -/* 2491 */ MCD_OPC_Decode, 144, 4, 211, 1, // Opcode: EFDCTUF -/* 2496 */ MCD_OPC_FilterValue, 7, 213, 10, 0, // Skip to: 5274 -/* 2501 */ MCD_OPC_CheckField, 26, 6, 4, 206, 10, 0, // Skip to: 5274 -/* 2508 */ MCD_OPC_CheckField, 16, 5, 0, 199, 10, 0, // Skip to: 5274 -/* 2515 */ MCD_OPC_Decode, 140, 4, 211, 1, // Opcode: EFDCTSF -/* 2520 */ MCD_OPC_FilterValue, 95, 123, 0, 0, // Skip to: 2648 -/* 2525 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 2528 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2552 -/* 2533 */ MCD_OPC_CheckField, 26, 6, 4, 174, 10, 0, // Skip to: 5274 -/* 2540 */ MCD_OPC_CheckField, 16, 5, 0, 167, 10, 0, // Skip to: 5274 -/* 2547 */ MCD_OPC_Decode, 147, 4, 213, 1, // Opcode: EFDCTUIZ -/* 2552 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2576 -/* 2557 */ MCD_OPC_CheckField, 26, 6, 4, 150, 10, 0, // Skip to: 5274 -/* 2564 */ MCD_OPC_CheckField, 16, 5, 0, 143, 10, 0, // Skip to: 5274 -/* 2571 */ MCD_OPC_Decode, 143, 4, 213, 1, // Opcode: EFDCTSIZ -/* 2576 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2600 -/* 2581 */ MCD_OPC_CheckField, 26, 6, 4, 126, 10, 0, // Skip to: 5274 -/* 2588 */ MCD_OPC_CheckField, 21, 2, 0, 119, 10, 0, // Skip to: 5274 -/* 2595 */ MCD_OPC_Decode, 154, 4, 201, 1, // Opcode: EFDTSTGT -/* 2600 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2624 -/* 2605 */ MCD_OPC_CheckField, 26, 6, 4, 102, 10, 0, // Skip to: 5274 -/* 2612 */ MCD_OPC_CheckField, 21, 2, 0, 95, 10, 0, // Skip to: 5274 -/* 2619 */ MCD_OPC_Decode, 155, 4, 201, 1, // Opcode: EFDTSTLT -/* 2624 */ MCD_OPC_FilterValue, 6, 85, 10, 0, // Skip to: 5274 -/* 2629 */ MCD_OPC_CheckField, 26, 6, 4, 78, 10, 0, // Skip to: 5274 -/* 2636 */ MCD_OPC_CheckField, 21, 2, 0, 71, 10, 0, // Skip to: 5274 -/* 2643 */ MCD_OPC_Decode, 153, 4, 201, 1, // Opcode: EFDTSTEQ -/* 2648 */ MCD_OPC_FilterValue, 96, 105, 0, 0, // Skip to: 2758 -/* 2653 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 2656 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2673 -/* 2661 */ MCD_OPC_CheckField, 26, 6, 4, 46, 10, 0, // Skip to: 5274 -/* 2668 */ MCD_OPC_Decode, 234, 4, 214, 1, // Opcode: EVLDDX -/* 2673 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2690 -/* 2678 */ MCD_OPC_CheckField, 26, 6, 4, 29, 10, 0, // Skip to: 5274 -/* 2685 */ MCD_OPC_Decode, 233, 4, 215, 1, // Opcode: EVLDD -/* 2690 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 2707 -/* 2695 */ MCD_OPC_CheckField, 26, 6, 4, 12, 10, 0, // Skip to: 5274 -/* 2702 */ MCD_OPC_Decode, 238, 4, 214, 1, // Opcode: EVLDWX -/* 2707 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 2724 -/* 2712 */ MCD_OPC_CheckField, 26, 6, 4, 251, 9, 0, // Skip to: 5274 -/* 2719 */ MCD_OPC_Decode, 237, 4, 215, 1, // Opcode: EVLDW -/* 2724 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 2741 -/* 2729 */ MCD_OPC_CheckField, 26, 6, 4, 234, 9, 0, // Skip to: 5274 -/* 2736 */ MCD_OPC_Decode, 236, 4, 214, 1, // Opcode: EVLDHX -/* 2741 */ MCD_OPC_FilterValue, 5, 224, 9, 0, // Skip to: 5274 -/* 2746 */ MCD_OPC_CheckField, 26, 6, 4, 217, 9, 0, // Skip to: 5274 -/* 2753 */ MCD_OPC_Decode, 235, 4, 215, 1, // Opcode: EVLDH -/* 2758 */ MCD_OPC_FilterValue, 97, 105, 0, 0, // Skip to: 2868 -/* 2763 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 2766 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2783 -/* 2771 */ MCD_OPC_CheckField, 26, 6, 4, 192, 9, 0, // Skip to: 5274 -/* 2778 */ MCD_OPC_Decode, 240, 4, 214, 1, // Opcode: EVLHHESPLATX -/* 2783 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2800 -/* 2788 */ MCD_OPC_CheckField, 26, 6, 4, 175, 9, 0, // Skip to: 5274 -/* 2795 */ MCD_OPC_Decode, 239, 4, 216, 1, // Opcode: EVLHHESPLAT -/* 2800 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 2817 -/* 2805 */ MCD_OPC_CheckField, 26, 6, 4, 158, 9, 0, // Skip to: 5274 -/* 2812 */ MCD_OPC_Decode, 244, 4, 214, 1, // Opcode: EVLHHOUSPLATX -/* 2817 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 2834 -/* 2822 */ MCD_OPC_CheckField, 26, 6, 4, 141, 9, 0, // Skip to: 5274 -/* 2829 */ MCD_OPC_Decode, 243, 4, 216, 1, // Opcode: EVLHHOUSPLAT -/* 2834 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 2851 -/* 2839 */ MCD_OPC_CheckField, 26, 6, 4, 124, 9, 0, // Skip to: 5274 -/* 2846 */ MCD_OPC_Decode, 242, 4, 214, 1, // Opcode: EVLHHOSSPLATX -/* 2851 */ MCD_OPC_FilterValue, 7, 114, 9, 0, // Skip to: 5274 -/* 2856 */ MCD_OPC_CheckField, 26, 6, 4, 107, 9, 0, // Skip to: 5274 -/* 2863 */ MCD_OPC_Decode, 241, 4, 216, 1, // Opcode: EVLHHOSSPLAT -/* 2868 */ MCD_OPC_FilterValue, 98, 105, 0, 0, // Skip to: 2978 -/* 2873 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 2876 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2893 -/* 2881 */ MCD_OPC_CheckField, 26, 6, 4, 82, 9, 0, // Skip to: 5274 -/* 2888 */ MCD_OPC_Decode, 246, 4, 214, 1, // Opcode: EVLWHEX -/* 2893 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2910 -/* 2898 */ MCD_OPC_CheckField, 26, 6, 4, 65, 9, 0, // Skip to: 5274 -/* 2905 */ MCD_OPC_Decode, 245, 4, 217, 1, // Opcode: EVLWHE -/* 2910 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 2927 -/* 2915 */ MCD_OPC_CheckField, 26, 6, 4, 48, 9, 0, // Skip to: 5274 -/* 2922 */ MCD_OPC_Decode, 250, 4, 214, 1, // Opcode: EVLWHOUX -/* 2927 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 2944 -/* 2932 */ MCD_OPC_CheckField, 26, 6, 4, 31, 9, 0, // Skip to: 5274 -/* 2939 */ MCD_OPC_Decode, 249, 4, 217, 1, // Opcode: EVLWHOU -/* 2944 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 2961 -/* 2949 */ MCD_OPC_CheckField, 26, 6, 4, 14, 9, 0, // Skip to: 5274 -/* 2956 */ MCD_OPC_Decode, 248, 4, 214, 1, // Opcode: EVLWHOSX -/* 2961 */ MCD_OPC_FilterValue, 7, 4, 9, 0, // Skip to: 5274 -/* 2966 */ MCD_OPC_CheckField, 26, 6, 4, 253, 8, 0, // Skip to: 5274 -/* 2973 */ MCD_OPC_Decode, 247, 4, 217, 1, // Opcode: EVLWHOS -/* 2978 */ MCD_OPC_FilterValue, 99, 71, 0, 0, // Skip to: 3054 -/* 2983 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 2986 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3003 -/* 2991 */ MCD_OPC_CheckField, 26, 6, 4, 228, 8, 0, // Skip to: 5274 -/* 2998 */ MCD_OPC_Decode, 254, 4, 214, 1, // Opcode: EVLWWSPLATX -/* 3003 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3020 -/* 3008 */ MCD_OPC_CheckField, 26, 6, 4, 211, 8, 0, // Skip to: 5274 -/* 3015 */ MCD_OPC_Decode, 253, 4, 217, 1, // Opcode: EVLWWSPLAT -/* 3020 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3037 -/* 3025 */ MCD_OPC_CheckField, 26, 6, 4, 194, 8, 0, // Skip to: 5274 -/* 3032 */ MCD_OPC_Decode, 252, 4, 214, 1, // Opcode: EVLWHSPLATX -/* 3037 */ MCD_OPC_FilterValue, 5, 184, 8, 0, // Skip to: 5274 -/* 3042 */ MCD_OPC_CheckField, 26, 6, 4, 177, 8, 0, // Skip to: 5274 -/* 3049 */ MCD_OPC_Decode, 251, 4, 217, 1, // Opcode: EVLWHSPLAT -/* 3054 */ MCD_OPC_FilterValue, 100, 105, 0, 0, // Skip to: 3164 -/* 3059 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3062 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3079 -/* 3067 */ MCD_OPC_CheckField, 26, 6, 4, 152, 8, 0, // Skip to: 5274 -/* 3074 */ MCD_OPC_Decode, 236, 5, 214, 1, // Opcode: EVSTDDX -/* 3079 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3096 -/* 3084 */ MCD_OPC_CheckField, 26, 6, 4, 135, 8, 0, // Skip to: 5274 -/* 3091 */ MCD_OPC_Decode, 235, 5, 215, 1, // Opcode: EVSTDD -/* 3096 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 3113 -/* 3101 */ MCD_OPC_CheckField, 26, 6, 4, 118, 8, 0, // Skip to: 5274 -/* 3108 */ MCD_OPC_Decode, 240, 5, 214, 1, // Opcode: EVSTDWX -/* 3113 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3130 -/* 3118 */ MCD_OPC_CheckField, 26, 6, 4, 101, 8, 0, // Skip to: 5274 -/* 3125 */ MCD_OPC_Decode, 239, 5, 215, 1, // Opcode: EVSTDW -/* 3130 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3147 -/* 3135 */ MCD_OPC_CheckField, 26, 6, 4, 84, 8, 0, // Skip to: 5274 -/* 3142 */ MCD_OPC_Decode, 238, 5, 214, 1, // Opcode: EVSTDHX -/* 3147 */ MCD_OPC_FilterValue, 5, 74, 8, 0, // Skip to: 5274 -/* 3152 */ MCD_OPC_CheckField, 26, 6, 4, 67, 8, 0, // Skip to: 5274 -/* 3159 */ MCD_OPC_Decode, 237, 5, 215, 1, // Opcode: EVSTDH -/* 3164 */ MCD_OPC_FilterValue, 102, 71, 0, 0, // Skip to: 3240 -/* 3169 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3172 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3189 -/* 3177 */ MCD_OPC_CheckField, 26, 6, 4, 42, 8, 0, // Skip to: 5274 -/* 3184 */ MCD_OPC_Decode, 242, 5, 214, 1, // Opcode: EVSTWHEX -/* 3189 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3206 -/* 3194 */ MCD_OPC_CheckField, 26, 6, 4, 25, 8, 0, // Skip to: 5274 -/* 3201 */ MCD_OPC_Decode, 241, 5, 217, 1, // Opcode: EVSTWHE -/* 3206 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3223 -/* 3211 */ MCD_OPC_CheckField, 26, 6, 4, 8, 8, 0, // Skip to: 5274 -/* 3218 */ MCD_OPC_Decode, 244, 5, 214, 1, // Opcode: EVSTWHOX -/* 3223 */ MCD_OPC_FilterValue, 5, 254, 7, 0, // Skip to: 5274 -/* 3228 */ MCD_OPC_CheckField, 26, 6, 4, 247, 7, 0, // Skip to: 5274 -/* 3235 */ MCD_OPC_Decode, 243, 5, 217, 1, // Opcode: EVSTWHO -/* 3240 */ MCD_OPC_FilterValue, 103, 71, 0, 0, // Skip to: 3316 -/* 3245 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3248 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3265 -/* 3253 */ MCD_OPC_CheckField, 26, 6, 4, 222, 7, 0, // Skip to: 5274 -/* 3260 */ MCD_OPC_Decode, 246, 5, 214, 1, // Opcode: EVSTWWEX -/* 3265 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3282 -/* 3270 */ MCD_OPC_CheckField, 26, 6, 4, 205, 7, 0, // Skip to: 5274 -/* 3277 */ MCD_OPC_Decode, 245, 5, 217, 1, // Opcode: EVSTWWE -/* 3282 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3299 -/* 3287 */ MCD_OPC_CheckField, 26, 6, 4, 188, 7, 0, // Skip to: 5274 -/* 3294 */ MCD_OPC_Decode, 248, 5, 214, 1, // Opcode: EVSTWWOX -/* 3299 */ MCD_OPC_FilterValue, 5, 178, 7, 0, // Skip to: 5274 -/* 3304 */ MCD_OPC_CheckField, 26, 6, 4, 171, 7, 0, // Skip to: 5274 -/* 3311 */ MCD_OPC_Decode, 247, 5, 217, 1, // Opcode: EVSTWWO -/* 3316 */ MCD_OPC_FilterValue, 128, 1, 37, 0, 0, // Skip to: 3359 -/* 3322 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3325 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3342 -/* 3330 */ MCD_OPC_CheckField, 26, 6, 4, 145, 7, 0, // Skip to: 5274 -/* 3337 */ MCD_OPC_Decode, 145, 5, 196, 1, // Opcode: EVMHESSF -/* 3342 */ MCD_OPC_FilterValue, 7, 135, 7, 0, // Skip to: 5274 -/* 3347 */ MCD_OPC_CheckField, 26, 6, 4, 128, 7, 0, // Skip to: 5274 -/* 3354 */ MCD_OPC_Decode, 171, 5, 196, 1, // Opcode: EVMHOSSF -/* 3359 */ MCD_OPC_FilterValue, 129, 1, 105, 0, 0, // Skip to: 3470 -/* 3365 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3368 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3385 -/* 3373 */ MCD_OPC_CheckField, 26, 6, 4, 102, 7, 0, // Skip to: 5274 -/* 3380 */ MCD_OPC_Decode, 151, 5, 196, 1, // Opcode: EVMHEUMI -/* 3385 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3402 -/* 3390 */ MCD_OPC_CheckField, 26, 6, 4, 85, 7, 0, // Skip to: 5274 -/* 3397 */ MCD_OPC_Decode, 141, 5, 196, 1, // Opcode: EVMHESMI -/* 3402 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3419 -/* 3407 */ MCD_OPC_CheckField, 26, 6, 4, 68, 7, 0, // Skip to: 5274 -/* 3414 */ MCD_OPC_Decode, 137, 5, 196, 1, // Opcode: EVMHESMF -/* 3419 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3436 -/* 3424 */ MCD_OPC_CheckField, 26, 6, 4, 51, 7, 0, // Skip to: 5274 -/* 3431 */ MCD_OPC_Decode, 177, 5, 196, 1, // Opcode: EVMHOUMI -/* 3436 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3453 -/* 3441 */ MCD_OPC_CheckField, 26, 6, 4, 34, 7, 0, // Skip to: 5274 -/* 3448 */ MCD_OPC_Decode, 167, 5, 196, 1, // Opcode: EVMHOSMI -/* 3453 */ MCD_OPC_FilterValue, 7, 24, 7, 0, // Skip to: 5274 -/* 3458 */ MCD_OPC_CheckField, 26, 6, 4, 17, 7, 0, // Skip to: 5274 -/* 3465 */ MCD_OPC_Decode, 163, 5, 196, 1, // Opcode: EVMHOSMF -/* 3470 */ MCD_OPC_FilterValue, 132, 1, 37, 0, 0, // Skip to: 3513 -/* 3476 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3479 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3496 -/* 3484 */ MCD_OPC_CheckField, 26, 6, 4, 247, 6, 0, // Skip to: 5274 -/* 3491 */ MCD_OPC_Decode, 146, 5, 196, 1, // Opcode: EVMHESSFA -/* 3496 */ MCD_OPC_FilterValue, 7, 237, 6, 0, // Skip to: 5274 -/* 3501 */ MCD_OPC_CheckField, 26, 6, 4, 230, 6, 0, // Skip to: 5274 -/* 3508 */ MCD_OPC_Decode, 172, 5, 196, 1, // Opcode: EVMHOSSFA -/* 3513 */ MCD_OPC_FilterValue, 133, 1, 105, 0, 0, // Skip to: 3624 -/* 3519 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3522 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3539 -/* 3527 */ MCD_OPC_CheckField, 26, 6, 4, 204, 6, 0, // Skip to: 5274 -/* 3534 */ MCD_OPC_Decode, 152, 5, 196, 1, // Opcode: EVMHEUMIA -/* 3539 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3556 -/* 3544 */ MCD_OPC_CheckField, 26, 6, 4, 187, 6, 0, // Skip to: 5274 -/* 3551 */ MCD_OPC_Decode, 142, 5, 196, 1, // Opcode: EVMHESMIA -/* 3556 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3573 -/* 3561 */ MCD_OPC_CheckField, 26, 6, 4, 170, 6, 0, // Skip to: 5274 -/* 3568 */ MCD_OPC_Decode, 138, 5, 196, 1, // Opcode: EVMHESMFA -/* 3573 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3590 -/* 3578 */ MCD_OPC_CheckField, 26, 6, 4, 153, 6, 0, // Skip to: 5274 -/* 3585 */ MCD_OPC_Decode, 178, 5, 196, 1, // Opcode: EVMHOUMIA -/* 3590 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3607 -/* 3595 */ MCD_OPC_CheckField, 26, 6, 4, 136, 6, 0, // Skip to: 5274 -/* 3602 */ MCD_OPC_Decode, 168, 5, 196, 1, // Opcode: EVMHOSMIA -/* 3607 */ MCD_OPC_FilterValue, 7, 126, 6, 0, // Skip to: 5274 -/* 3612 */ MCD_OPC_CheckField, 26, 6, 4, 119, 6, 0, // Skip to: 5274 -/* 3619 */ MCD_OPC_Decode, 164, 5, 196, 1, // Opcode: EVMHOSMFA -/* 3624 */ MCD_OPC_FilterValue, 136, 1, 19, 0, 0, // Skip to: 3649 -/* 3630 */ MCD_OPC_CheckField, 26, 6, 4, 101, 6, 0, // Skip to: 5274 -/* 3637 */ MCD_OPC_CheckField, 0, 3, 7, 94, 6, 0, // Skip to: 5274 -/* 3644 */ MCD_OPC_Decode, 188, 5, 196, 1, // Opcode: EVMWHSSF -/* 3649 */ MCD_OPC_FilterValue, 137, 1, 71, 0, 0, // Skip to: 3726 -/* 3655 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3658 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3675 -/* 3663 */ MCD_OPC_CheckField, 26, 6, 4, 68, 6, 0, // Skip to: 5274 -/* 3670 */ MCD_OPC_Decode, 196, 5, 196, 1, // Opcode: EVMWLUMI -/* 3675 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3692 -/* 3680 */ MCD_OPC_CheckField, 26, 6, 4, 51, 6, 0, // Skip to: 5274 -/* 3687 */ MCD_OPC_Decode, 190, 5, 196, 1, // Opcode: EVMWHUMI -/* 3692 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3709 -/* 3697 */ MCD_OPC_CheckField, 26, 6, 4, 34, 6, 0, // Skip to: 5274 -/* 3704 */ MCD_OPC_Decode, 186, 5, 196, 1, // Opcode: EVMWHSMI -/* 3709 */ MCD_OPC_FilterValue, 7, 24, 6, 0, // Skip to: 5274 -/* 3714 */ MCD_OPC_CheckField, 26, 6, 4, 17, 6, 0, // Skip to: 5274 -/* 3721 */ MCD_OPC_Decode, 184, 5, 196, 1, // Opcode: EVMWHSMF -/* 3726 */ MCD_OPC_FilterValue, 138, 1, 19, 0, 0, // Skip to: 3751 -/* 3732 */ MCD_OPC_CheckField, 26, 6, 4, 255, 5, 0, // Skip to: 5274 -/* 3739 */ MCD_OPC_CheckField, 0, 3, 3, 248, 5, 0, // Skip to: 5274 -/* 3746 */ MCD_OPC_Decode, 210, 5, 196, 1, // Opcode: EVMWSSF -/* 3751 */ MCD_OPC_FilterValue, 139, 1, 54, 0, 0, // Skip to: 3811 -/* 3757 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3760 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3777 -/* 3765 */ MCD_OPC_CheckField, 26, 6, 4, 222, 5, 0, // Skip to: 5274 -/* 3772 */ MCD_OPC_Decode, 214, 5, 196, 1, // Opcode: EVMWUMI -/* 3777 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3794 -/* 3782 */ MCD_OPC_CheckField, 26, 6, 4, 205, 5, 0, // Skip to: 5274 -/* 3789 */ MCD_OPC_Decode, 206, 5, 196, 1, // Opcode: EVMWSMI -/* 3794 */ MCD_OPC_FilterValue, 3, 195, 5, 0, // Skip to: 5274 -/* 3799 */ MCD_OPC_CheckField, 26, 6, 4, 188, 5, 0, // Skip to: 5274 -/* 3806 */ MCD_OPC_Decode, 202, 5, 196, 1, // Opcode: EVMWSMF -/* 3811 */ MCD_OPC_FilterValue, 140, 1, 19, 0, 0, // Skip to: 3836 -/* 3817 */ MCD_OPC_CheckField, 26, 6, 4, 170, 5, 0, // Skip to: 5274 -/* 3824 */ MCD_OPC_CheckField, 0, 3, 7, 163, 5, 0, // Skip to: 5274 -/* 3831 */ MCD_OPC_Decode, 189, 5, 196, 1, // Opcode: EVMWHSSFA -/* 3836 */ MCD_OPC_FilterValue, 141, 1, 71, 0, 0, // Skip to: 3913 -/* 3842 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3845 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3862 -/* 3850 */ MCD_OPC_CheckField, 26, 6, 4, 137, 5, 0, // Skip to: 5274 -/* 3857 */ MCD_OPC_Decode, 197, 5, 196, 1, // Opcode: EVMWLUMIA -/* 3862 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3879 -/* 3867 */ MCD_OPC_CheckField, 26, 6, 4, 120, 5, 0, // Skip to: 5274 -/* 3874 */ MCD_OPC_Decode, 191, 5, 196, 1, // Opcode: EVMWHUMIA -/* 3879 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3896 -/* 3884 */ MCD_OPC_CheckField, 26, 6, 4, 103, 5, 0, // Skip to: 5274 -/* 3891 */ MCD_OPC_Decode, 187, 5, 196, 1, // Opcode: EVMWHSMIA -/* 3896 */ MCD_OPC_FilterValue, 7, 93, 5, 0, // Skip to: 5274 -/* 3901 */ MCD_OPC_CheckField, 26, 6, 4, 86, 5, 0, // Skip to: 5274 -/* 3908 */ MCD_OPC_Decode, 185, 5, 196, 1, // Opcode: EVMWHSMFA -/* 3913 */ MCD_OPC_FilterValue, 142, 1, 19, 0, 0, // Skip to: 3938 -/* 3919 */ MCD_OPC_CheckField, 26, 6, 4, 68, 5, 0, // Skip to: 5274 -/* 3926 */ MCD_OPC_CheckField, 0, 3, 3, 61, 5, 0, // Skip to: 5274 -/* 3933 */ MCD_OPC_Decode, 211, 5, 196, 1, // Opcode: EVMWSSFA -/* 3938 */ MCD_OPC_FilterValue, 143, 1, 54, 0, 0, // Skip to: 3998 -/* 3944 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 3947 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3964 -/* 3952 */ MCD_OPC_CheckField, 26, 6, 4, 35, 5, 0, // Skip to: 5274 -/* 3959 */ MCD_OPC_Decode, 215, 5, 196, 1, // Opcode: EVMWUMIA -/* 3964 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3981 -/* 3969 */ MCD_OPC_CheckField, 26, 6, 4, 18, 5, 0, // Skip to: 5274 -/* 3976 */ MCD_OPC_Decode, 207, 5, 196, 1, // Opcode: EVMWSMIA -/* 3981 */ MCD_OPC_FilterValue, 3, 8, 5, 0, // Skip to: 5274 -/* 3986 */ MCD_OPC_CheckField, 26, 6, 4, 1, 5, 0, // Skip to: 5274 -/* 3993 */ MCD_OPC_Decode, 203, 5, 196, 1, // Opcode: EVMWSMFA -/* 3998 */ MCD_OPC_FilterValue, 152, 1, 157, 0, 0, // Skip to: 4161 -/* 4004 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4007 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 4031 -/* 4012 */ MCD_OPC_CheckField, 26, 6, 4, 231, 4, 0, // Skip to: 5274 -/* 4019 */ MCD_OPC_CheckField, 11, 5, 0, 224, 4, 0, // Skip to: 5274 -/* 4026 */ MCD_OPC_Decode, 194, 4, 199, 1, // Opcode: EVADDUSIAAW -/* 4031 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 4055 -/* 4036 */ MCD_OPC_CheckField, 26, 6, 4, 207, 4, 0, // Skip to: 5274 -/* 4043 */ MCD_OPC_CheckField, 11, 5, 0, 200, 4, 0, // Skip to: 5274 -/* 4050 */ MCD_OPC_Decode, 192, 4, 199, 1, // Opcode: EVADDSSIAAW -/* 4055 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 4079 -/* 4060 */ MCD_OPC_CheckField, 26, 6, 4, 183, 4, 0, // Skip to: 5274 -/* 4067 */ MCD_OPC_CheckField, 11, 5, 0, 176, 4, 0, // Skip to: 5274 -/* 4074 */ MCD_OPC_Decode, 252, 5, 199, 1, // Opcode: EVSUBFUSIAAW -/* 4079 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 4103 -/* 4084 */ MCD_OPC_CheckField, 26, 6, 4, 159, 4, 0, // Skip to: 5274 -/* 4091 */ MCD_OPC_CheckField, 11, 5, 0, 152, 4, 0, // Skip to: 5274 -/* 4098 */ MCD_OPC_Decode, 250, 5, 199, 1, // Opcode: EVSUBFSSIAAW -/* 4103 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 4127 -/* 4108 */ MCD_OPC_CheckField, 26, 6, 4, 135, 4, 0, // Skip to: 5274 -/* 4115 */ MCD_OPC_CheckField, 11, 5, 0, 128, 4, 0, // Skip to: 5274 -/* 4122 */ MCD_OPC_Decode, 183, 5, 199, 1, // Opcode: EVMRA -/* 4127 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 4144 -/* 4132 */ MCD_OPC_CheckField, 26, 6, 4, 111, 4, 0, // Skip to: 5274 -/* 4139 */ MCD_OPC_Decode, 205, 4, 196, 1, // Opcode: EVDIVWS -/* 4144 */ MCD_OPC_FilterValue, 7, 101, 4, 0, // Skip to: 5274 -/* 4149 */ MCD_OPC_CheckField, 26, 6, 4, 94, 4, 0, // Skip to: 5274 -/* 4156 */ MCD_OPC_Decode, 206, 4, 196, 1, // Opcode: EVDIVWU -/* 4161 */ MCD_OPC_FilterValue, 153, 1, 99, 0, 0, // Skip to: 4266 -/* 4167 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4170 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 4194 -/* 4175 */ MCD_OPC_CheckField, 26, 6, 4, 68, 4, 0, // Skip to: 5274 -/* 4182 */ MCD_OPC_CheckField, 11, 5, 0, 61, 4, 0, // Skip to: 5274 -/* 4189 */ MCD_OPC_Decode, 193, 4, 199, 1, // Opcode: EVADDUMIAAW -/* 4194 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 4218 -/* 4199 */ MCD_OPC_CheckField, 26, 6, 4, 44, 4, 0, // Skip to: 5274 -/* 4206 */ MCD_OPC_CheckField, 11, 5, 0, 37, 4, 0, // Skip to: 5274 -/* 4213 */ MCD_OPC_Decode, 191, 4, 199, 1, // Opcode: EVADDSMIAAW -/* 4218 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 4242 -/* 4223 */ MCD_OPC_CheckField, 26, 6, 4, 20, 4, 0, // Skip to: 5274 -/* 4230 */ MCD_OPC_CheckField, 11, 5, 0, 13, 4, 0, // Skip to: 5274 -/* 4237 */ MCD_OPC_Decode, 251, 5, 199, 1, // Opcode: EVSUBFUMIAAW -/* 4242 */ MCD_OPC_FilterValue, 3, 3, 4, 0, // Skip to: 5274 -/* 4247 */ MCD_OPC_CheckField, 26, 6, 4, 252, 3, 0, // Skip to: 5274 -/* 4254 */ MCD_OPC_CheckField, 11, 5, 0, 245, 3, 0, // Skip to: 5274 -/* 4261 */ MCD_OPC_Decode, 249, 5, 199, 1, // Opcode: EVSUBFSMIAAW -/* 4266 */ MCD_OPC_FilterValue, 160, 1, 105, 0, 0, // Skip to: 4377 -/* 4272 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4275 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4292 -/* 4280 */ MCD_OPC_CheckField, 26, 6, 4, 219, 3, 0, // Skip to: 5274 -/* 4287 */ MCD_OPC_Decode, 155, 5, 196, 1, // Opcode: EVMHEUSIAAW -/* 4292 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4309 -/* 4297 */ MCD_OPC_CheckField, 26, 6, 4, 202, 3, 0, // Skip to: 5274 -/* 4304 */ MCD_OPC_Decode, 149, 5, 196, 1, // Opcode: EVMHESSIAAW -/* 4309 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4326 -/* 4314 */ MCD_OPC_CheckField, 26, 6, 4, 185, 3, 0, // Skip to: 5274 -/* 4321 */ MCD_OPC_Decode, 147, 5, 196, 1, // Opcode: EVMHESSFAAW -/* 4326 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4343 -/* 4331 */ MCD_OPC_CheckField, 26, 6, 4, 168, 3, 0, // Skip to: 5274 -/* 4338 */ MCD_OPC_Decode, 181, 5, 196, 1, // Opcode: EVMHOUSIAAW -/* 4343 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4360 -/* 4348 */ MCD_OPC_CheckField, 26, 6, 4, 151, 3, 0, // Skip to: 5274 -/* 4355 */ MCD_OPC_Decode, 175, 5, 196, 1, // Opcode: EVMHOSSIAAW -/* 4360 */ MCD_OPC_FilterValue, 7, 141, 3, 0, // Skip to: 5274 -/* 4365 */ MCD_OPC_CheckField, 26, 6, 4, 134, 3, 0, // Skip to: 5274 -/* 4372 */ MCD_OPC_Decode, 173, 5, 196, 1, // Opcode: EVMHOSSFAAW -/* 4377 */ MCD_OPC_FilterValue, 161, 1, 105, 0, 0, // Skip to: 4488 -/* 4383 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4386 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4403 -/* 4391 */ MCD_OPC_CheckField, 26, 6, 4, 108, 3, 0, // Skip to: 5274 -/* 4398 */ MCD_OPC_Decode, 153, 5, 196, 1, // Opcode: EVMHEUMIAAW -/* 4403 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4420 -/* 4408 */ MCD_OPC_CheckField, 26, 6, 4, 91, 3, 0, // Skip to: 5274 -/* 4415 */ MCD_OPC_Decode, 143, 5, 196, 1, // Opcode: EVMHESMIAAW -/* 4420 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4437 -/* 4425 */ MCD_OPC_CheckField, 26, 6, 4, 74, 3, 0, // Skip to: 5274 -/* 4432 */ MCD_OPC_Decode, 139, 5, 196, 1, // Opcode: EVMHESMFAAW -/* 4437 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4454 -/* 4442 */ MCD_OPC_CheckField, 26, 6, 4, 57, 3, 0, // Skip to: 5274 -/* 4449 */ MCD_OPC_Decode, 179, 5, 196, 1, // Opcode: EVMHOUMIAAW -/* 4454 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4471 -/* 4459 */ MCD_OPC_CheckField, 26, 6, 4, 40, 3, 0, // Skip to: 5274 -/* 4466 */ MCD_OPC_Decode, 169, 5, 196, 1, // Opcode: EVMHOSMIAAW -/* 4471 */ MCD_OPC_FilterValue, 7, 30, 3, 0, // Skip to: 5274 -/* 4476 */ MCD_OPC_CheckField, 26, 6, 4, 23, 3, 0, // Skip to: 5274 -/* 4483 */ MCD_OPC_Decode, 165, 5, 196, 1, // Opcode: EVMHOSMFAAW -/* 4488 */ MCD_OPC_FilterValue, 165, 1, 105, 0, 0, // Skip to: 4599 -/* 4494 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4497 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4514 -/* 4502 */ MCD_OPC_CheckField, 26, 6, 4, 253, 2, 0, // Skip to: 5274 -/* 4509 */ MCD_OPC_Decode, 135, 5, 196, 1, // Opcode: EVMHEGUMIAA -/* 4514 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4531 -/* 4519 */ MCD_OPC_CheckField, 26, 6, 4, 236, 2, 0, // Skip to: 5274 -/* 4526 */ MCD_OPC_Decode, 133, 5, 196, 1, // Opcode: EVMHEGSMIAA -/* 4531 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4548 -/* 4536 */ MCD_OPC_CheckField, 26, 6, 4, 219, 2, 0, // Skip to: 5274 -/* 4543 */ MCD_OPC_Decode, 131, 5, 196, 1, // Opcode: EVMHEGSMFAA -/* 4548 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4565 -/* 4553 */ MCD_OPC_CheckField, 26, 6, 4, 202, 2, 0, // Skip to: 5274 -/* 4560 */ MCD_OPC_Decode, 161, 5, 196, 1, // Opcode: EVMHOGUMIAA -/* 4565 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4582 -/* 4570 */ MCD_OPC_CheckField, 26, 6, 4, 185, 2, 0, // Skip to: 5274 -/* 4577 */ MCD_OPC_Decode, 159, 5, 196, 1, // Opcode: EVMHOGSMIAA -/* 4582 */ MCD_OPC_FilterValue, 7, 175, 2, 0, // Skip to: 5274 -/* 4587 */ MCD_OPC_CheckField, 26, 6, 4, 168, 2, 0, // Skip to: 5274 -/* 4594 */ MCD_OPC_Decode, 157, 5, 196, 1, // Opcode: EVMHOGSMFAA -/* 4599 */ MCD_OPC_FilterValue, 168, 1, 37, 0, 0, // Skip to: 4642 -/* 4605 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4608 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4625 -/* 4613 */ MCD_OPC_CheckField, 26, 6, 4, 142, 2, 0, // Skip to: 5274 -/* 4620 */ MCD_OPC_Decode, 200, 5, 196, 1, // Opcode: EVMWLUSIAAW -/* 4625 */ MCD_OPC_FilterValue, 1, 132, 2, 0, // Skip to: 5274 -/* 4630 */ MCD_OPC_CheckField, 26, 6, 4, 125, 2, 0, // Skip to: 5274 -/* 4637 */ MCD_OPC_Decode, 194, 5, 196, 1, // Opcode: EVMWLSSIAAW -/* 4642 */ MCD_OPC_FilterValue, 169, 1, 37, 0, 0, // Skip to: 4685 -/* 4648 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4651 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4668 -/* 4656 */ MCD_OPC_CheckField, 26, 6, 4, 99, 2, 0, // Skip to: 5274 -/* 4663 */ MCD_OPC_Decode, 198, 5, 196, 1, // Opcode: EVMWLUMIAAW -/* 4668 */ MCD_OPC_FilterValue, 1, 89, 2, 0, // Skip to: 5274 -/* 4673 */ MCD_OPC_CheckField, 26, 6, 4, 82, 2, 0, // Skip to: 5274 -/* 4680 */ MCD_OPC_Decode, 192, 5, 196, 1, // Opcode: EVMWLSMIAAW -/* 4685 */ MCD_OPC_FilterValue, 170, 1, 19, 0, 0, // Skip to: 4710 -/* 4691 */ MCD_OPC_CheckField, 26, 6, 4, 64, 2, 0, // Skip to: 5274 -/* 4698 */ MCD_OPC_CheckField, 0, 3, 3, 57, 2, 0, // Skip to: 5274 -/* 4705 */ MCD_OPC_Decode, 212, 5, 196, 1, // Opcode: EVMWSSFAA -/* 4710 */ MCD_OPC_FilterValue, 171, 1, 54, 0, 0, // Skip to: 4770 -/* 4716 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4719 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4736 -/* 4724 */ MCD_OPC_CheckField, 26, 6, 4, 31, 2, 0, // Skip to: 5274 -/* 4731 */ MCD_OPC_Decode, 216, 5, 196, 1, // Opcode: EVMWUMIAA -/* 4736 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4753 -/* 4741 */ MCD_OPC_CheckField, 26, 6, 4, 14, 2, 0, // Skip to: 5274 -/* 4748 */ MCD_OPC_Decode, 208, 5, 196, 1, // Opcode: EVMWSMIAA -/* 4753 */ MCD_OPC_FilterValue, 3, 4, 2, 0, // Skip to: 5274 -/* 4758 */ MCD_OPC_CheckField, 26, 6, 4, 253, 1, 0, // Skip to: 5274 -/* 4765 */ MCD_OPC_Decode, 204, 5, 196, 1, // Opcode: EVMWSMFAA -/* 4770 */ MCD_OPC_FilterValue, 176, 1, 105, 0, 0, // Skip to: 4881 -/* 4776 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4779 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4796 -/* 4784 */ MCD_OPC_CheckField, 26, 6, 4, 227, 1, 0, // Skip to: 5274 -/* 4791 */ MCD_OPC_Decode, 156, 5, 196, 1, // Opcode: EVMHEUSIANW -/* 4796 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4813 -/* 4801 */ MCD_OPC_CheckField, 26, 6, 4, 210, 1, 0, // Skip to: 5274 -/* 4808 */ MCD_OPC_Decode, 150, 5, 196, 1, // Opcode: EVMHESSIANW -/* 4813 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4830 -/* 4818 */ MCD_OPC_CheckField, 26, 6, 4, 193, 1, 0, // Skip to: 5274 -/* 4825 */ MCD_OPC_Decode, 148, 5, 196, 1, // Opcode: EVMHESSFANW -/* 4830 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4847 -/* 4835 */ MCD_OPC_CheckField, 26, 6, 4, 176, 1, 0, // Skip to: 5274 -/* 4842 */ MCD_OPC_Decode, 182, 5, 196, 1, // Opcode: EVMHOUSIANW -/* 4847 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4864 -/* 4852 */ MCD_OPC_CheckField, 26, 6, 4, 159, 1, 0, // Skip to: 5274 -/* 4859 */ MCD_OPC_Decode, 176, 5, 196, 1, // Opcode: EVMHOSSIANW -/* 4864 */ MCD_OPC_FilterValue, 7, 149, 1, 0, // Skip to: 5274 -/* 4869 */ MCD_OPC_CheckField, 26, 6, 4, 142, 1, 0, // Skip to: 5274 -/* 4876 */ MCD_OPC_Decode, 174, 5, 196, 1, // Opcode: EVMHOSSFANW -/* 4881 */ MCD_OPC_FilterValue, 177, 1, 105, 0, 0, // Skip to: 4992 -/* 4887 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 4890 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4907 -/* 4895 */ MCD_OPC_CheckField, 26, 6, 4, 116, 1, 0, // Skip to: 5274 -/* 4902 */ MCD_OPC_Decode, 154, 5, 196, 1, // Opcode: EVMHEUMIANW -/* 4907 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4924 -/* 4912 */ MCD_OPC_CheckField, 26, 6, 4, 99, 1, 0, // Skip to: 5274 -/* 4919 */ MCD_OPC_Decode, 144, 5, 196, 1, // Opcode: EVMHESMIANW -/* 4924 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4941 -/* 4929 */ MCD_OPC_CheckField, 26, 6, 4, 82, 1, 0, // Skip to: 5274 -/* 4936 */ MCD_OPC_Decode, 140, 5, 196, 1, // Opcode: EVMHESMFANW -/* 4941 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4958 -/* 4946 */ MCD_OPC_CheckField, 26, 6, 4, 65, 1, 0, // Skip to: 5274 -/* 4953 */ MCD_OPC_Decode, 180, 5, 196, 1, // Opcode: EVMHOUMIANW -/* 4958 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4975 -/* 4963 */ MCD_OPC_CheckField, 26, 6, 4, 48, 1, 0, // Skip to: 5274 -/* 4970 */ MCD_OPC_Decode, 170, 5, 196, 1, // Opcode: EVMHOSMIANW -/* 4975 */ MCD_OPC_FilterValue, 7, 38, 1, 0, // Skip to: 5274 -/* 4980 */ MCD_OPC_CheckField, 26, 6, 4, 31, 1, 0, // Skip to: 5274 -/* 4987 */ MCD_OPC_Decode, 166, 5, 196, 1, // Opcode: EVMHOSMFANW -/* 4992 */ MCD_OPC_FilterValue, 181, 1, 105, 0, 0, // Skip to: 5103 -/* 4998 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 5001 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5018 -/* 5006 */ MCD_OPC_CheckField, 26, 6, 4, 5, 1, 0, // Skip to: 5274 -/* 5013 */ MCD_OPC_Decode, 136, 5, 196, 1, // Opcode: EVMHEGUMIAN -/* 5018 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 5035 -/* 5023 */ MCD_OPC_CheckField, 26, 6, 4, 244, 0, 0, // Skip to: 5274 -/* 5030 */ MCD_OPC_Decode, 134, 5, 196, 1, // Opcode: EVMHEGSMIAN -/* 5035 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 5052 -/* 5040 */ MCD_OPC_CheckField, 26, 6, 4, 227, 0, 0, // Skip to: 5274 -/* 5047 */ MCD_OPC_Decode, 132, 5, 196, 1, // Opcode: EVMHEGSMFAN -/* 5052 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 5069 -/* 5057 */ MCD_OPC_CheckField, 26, 6, 4, 210, 0, 0, // Skip to: 5274 -/* 5064 */ MCD_OPC_Decode, 162, 5, 196, 1, // Opcode: EVMHOGUMIAN -/* 5069 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 5086 -/* 5074 */ MCD_OPC_CheckField, 26, 6, 4, 193, 0, 0, // Skip to: 5274 -/* 5081 */ MCD_OPC_Decode, 160, 5, 196, 1, // Opcode: EVMHOGSMIAN -/* 5086 */ MCD_OPC_FilterValue, 7, 183, 0, 0, // Skip to: 5274 -/* 5091 */ MCD_OPC_CheckField, 26, 6, 4, 176, 0, 0, // Skip to: 5274 -/* 5098 */ MCD_OPC_Decode, 158, 5, 196, 1, // Opcode: EVMHOGSMFAN -/* 5103 */ MCD_OPC_FilterValue, 184, 1, 37, 0, 0, // Skip to: 5146 -/* 5109 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 5112 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5129 -/* 5117 */ MCD_OPC_CheckField, 26, 6, 4, 150, 0, 0, // Skip to: 5274 -/* 5124 */ MCD_OPC_Decode, 201, 5, 196, 1, // Opcode: EVMWLUSIANW -/* 5129 */ MCD_OPC_FilterValue, 1, 140, 0, 0, // Skip to: 5274 -/* 5134 */ MCD_OPC_CheckField, 26, 6, 4, 133, 0, 0, // Skip to: 5274 -/* 5141 */ MCD_OPC_Decode, 195, 5, 196, 1, // Opcode: EVMWLSSIANW -/* 5146 */ MCD_OPC_FilterValue, 185, 1, 37, 0, 0, // Skip to: 5189 -/* 5152 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 5155 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5172 -/* 5160 */ MCD_OPC_CheckField, 26, 6, 4, 107, 0, 0, // Skip to: 5274 -/* 5167 */ MCD_OPC_Decode, 199, 5, 196, 1, // Opcode: EVMWLUMIANW -/* 5172 */ MCD_OPC_FilterValue, 1, 97, 0, 0, // Skip to: 5274 -/* 5177 */ MCD_OPC_CheckField, 26, 6, 4, 90, 0, 0, // Skip to: 5274 -/* 5184 */ MCD_OPC_Decode, 193, 5, 196, 1, // Opcode: EVMWLSMIANW -/* 5189 */ MCD_OPC_FilterValue, 186, 1, 19, 0, 0, // Skip to: 5214 -/* 5195 */ MCD_OPC_CheckField, 26, 6, 4, 72, 0, 0, // Skip to: 5274 -/* 5202 */ MCD_OPC_CheckField, 0, 3, 3, 65, 0, 0, // Skip to: 5274 -/* 5209 */ MCD_OPC_Decode, 213, 5, 196, 1, // Opcode: EVMWSSFAN -/* 5214 */ MCD_OPC_FilterValue, 187, 1, 54, 0, 0, // Skip to: 5274 -/* 5220 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... -/* 5223 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5240 -/* 5228 */ MCD_OPC_CheckField, 26, 6, 4, 39, 0, 0, // Skip to: 5274 -/* 5235 */ MCD_OPC_Decode, 217, 5, 196, 1, // Opcode: EVMWUMIAN -/* 5240 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 5257 -/* 5245 */ MCD_OPC_CheckField, 26, 6, 4, 22, 0, 0, // Skip to: 5274 -/* 5252 */ MCD_OPC_Decode, 209, 5, 196, 1, // Opcode: EVMWSMIAN -/* 5257 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 5274 -/* 5262 */ MCD_OPC_CheckField, 26, 6, 4, 5, 0, 0, // Skip to: 5274 -/* 5269 */ MCD_OPC_Decode, 205, 5, 196, 1, // Opcode: EVMWSMFAN -/* 5274 */ MCD_OPC_Fail, +/* 1400 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1416 +/* 1405 */ MCD_OPC_CheckField, 26, 6, 4, 3, 15, 0, // Skip to: 5255 +/* 1412 */ MCD_OPC_Decode, 211, 5, 80, // Opcode: EFSADD +/* 1416 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 1432 +/* 1421 */ MCD_OPC_CheckField, 26, 6, 4, 243, 14, 0, // Skip to: 5255 +/* 1428 */ MCD_OPC_Decode, 230, 5, 80, // Opcode: EFSSUB +/* 1432 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 1455 +/* 1437 */ MCD_OPC_CheckField, 26, 6, 4, 227, 14, 0, // Skip to: 5255 +/* 1444 */ MCD_OPC_CheckField, 11, 5, 0, 220, 14, 0, // Skip to: 5255 +/* 1451 */ MCD_OPC_Decode, 210, 5, 82, // Opcode: EFSABS +/* 1455 */ MCD_OPC_FilterValue, 5, 18, 0, 0, // Skip to: 1478 +/* 1460 */ MCD_OPC_CheckField, 26, 6, 4, 204, 14, 0, // Skip to: 5255 +/* 1467 */ MCD_OPC_CheckField, 11, 5, 0, 197, 14, 0, // Skip to: 5255 +/* 1474 */ MCD_OPC_Decode, 228, 5, 82, // Opcode: EFSNABS +/* 1478 */ MCD_OPC_FilterValue, 6, 188, 14, 0, // Skip to: 5255 +/* 1483 */ MCD_OPC_CheckField, 26, 6, 4, 181, 14, 0, // Skip to: 5255 +/* 1490 */ MCD_OPC_CheckField, 11, 5, 0, 174, 14, 0, // Skip to: 5255 +/* 1497 */ MCD_OPC_Decode, 229, 5, 82, // Opcode: EFSNEG +/* 1501 */ MCD_OPC_FilterValue, 89, 128, 0, 0, // Skip to: 1634 +/* 1506 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 1509 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1525 +/* 1514 */ MCD_OPC_CheckField, 26, 6, 4, 150, 14, 0, // Skip to: 5255 +/* 1521 */ MCD_OPC_Decode, 227, 5, 80, // Opcode: EFSMUL +/* 1525 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 1541 +/* 1530 */ MCD_OPC_CheckField, 26, 6, 4, 134, 14, 0, // Skip to: 5255 +/* 1537 */ MCD_OPC_Decode, 226, 5, 80, // Opcode: EFSDIV +/* 1541 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 1564 +/* 1546 */ MCD_OPC_CheckField, 26, 6, 4, 118, 14, 0, // Skip to: 5255 +/* 1553 */ MCD_OPC_CheckField, 21, 2, 0, 111, 14, 0, // Skip to: 5255 +/* 1560 */ MCD_OPC_Decode, 218, 5, 63, // Opcode: EFSCMPGT +/* 1564 */ MCD_OPC_FilterValue, 5, 18, 0, 0, // Skip to: 1587 +/* 1569 */ MCD_OPC_CheckField, 26, 6, 4, 95, 14, 0, // Skip to: 5255 +/* 1576 */ MCD_OPC_CheckField, 21, 2, 0, 88, 14, 0, // Skip to: 5255 +/* 1583 */ MCD_OPC_Decode, 219, 5, 63, // Opcode: EFSCMPLT +/* 1587 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 1610 +/* 1592 */ MCD_OPC_CheckField, 26, 6, 4, 72, 14, 0, // Skip to: 5255 +/* 1599 */ MCD_OPC_CheckField, 21, 2, 0, 65, 14, 0, // Skip to: 5255 +/* 1606 */ MCD_OPC_Decode, 217, 5, 63, // Opcode: EFSCMPEQ +/* 1610 */ MCD_OPC_FilterValue, 7, 56, 14, 0, // Skip to: 5255 +/* 1615 */ MCD_OPC_CheckField, 26, 6, 4, 49, 14, 0, // Skip to: 5255 +/* 1622 */ MCD_OPC_CheckField, 16, 5, 0, 42, 14, 0, // Skip to: 5255 +/* 1629 */ MCD_OPC_Decode, 212, 5, 247, 1, // Opcode: EFSCFD +/* 1634 */ MCD_OPC_FilterValue, 90, 188, 0, 0, // Skip to: 1827 +/* 1639 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 1642 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 1665 +/* 1647 */ MCD_OPC_CheckField, 26, 6, 4, 17, 14, 0, // Skip to: 5255 +/* 1654 */ MCD_OPC_CheckField, 16, 5, 0, 10, 14, 0, // Skip to: 5255 +/* 1661 */ MCD_OPC_Decode, 216, 5, 107, // Opcode: EFSCFUI +/* 1665 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 1688 +/* 1670 */ MCD_OPC_CheckField, 26, 6, 4, 250, 13, 0, // Skip to: 5255 +/* 1677 */ MCD_OPC_CheckField, 16, 5, 0, 243, 13, 0, // Skip to: 5255 +/* 1684 */ MCD_OPC_Decode, 214, 5, 107, // Opcode: EFSCFSI +/* 1688 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 1711 +/* 1693 */ MCD_OPC_CheckField, 26, 6, 4, 227, 13, 0, // Skip to: 5255 +/* 1700 */ MCD_OPC_CheckField, 16, 5, 0, 220, 13, 0, // Skip to: 5255 +/* 1707 */ MCD_OPC_Decode, 215, 5, 107, // Opcode: EFSCFUF +/* 1711 */ MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 1734 +/* 1716 */ MCD_OPC_CheckField, 26, 6, 4, 204, 13, 0, // Skip to: 5255 +/* 1723 */ MCD_OPC_CheckField, 16, 5, 0, 197, 13, 0, // Skip to: 5255 +/* 1730 */ MCD_OPC_Decode, 213, 5, 107, // Opcode: EFSCFSF +/* 1734 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 1757 +/* 1739 */ MCD_OPC_CheckField, 26, 6, 4, 181, 13, 0, // Skip to: 5255 +/* 1746 */ MCD_OPC_CheckField, 16, 5, 0, 174, 13, 0, // Skip to: 5255 +/* 1753 */ MCD_OPC_Decode, 224, 5, 107, // Opcode: EFSCTUI +/* 1757 */ MCD_OPC_FilterValue, 5, 18, 0, 0, // Skip to: 1780 +/* 1762 */ MCD_OPC_CheckField, 26, 6, 4, 158, 13, 0, // Skip to: 5255 +/* 1769 */ MCD_OPC_CheckField, 16, 5, 0, 151, 13, 0, // Skip to: 5255 +/* 1776 */ MCD_OPC_Decode, 221, 5, 107, // Opcode: EFSCTSI +/* 1780 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 1804 +/* 1785 */ MCD_OPC_CheckField, 26, 6, 4, 135, 13, 0, // Skip to: 5255 +/* 1792 */ MCD_OPC_CheckField, 16, 5, 0, 128, 13, 0, // Skip to: 5255 +/* 1799 */ MCD_OPC_Decode, 223, 5, 248, 1, // Opcode: EFSCTUF +/* 1804 */ MCD_OPC_FilterValue, 7, 118, 13, 0, // Skip to: 5255 +/* 1809 */ MCD_OPC_CheckField, 26, 6, 4, 111, 13, 0, // Skip to: 5255 +/* 1816 */ MCD_OPC_CheckField, 16, 5, 0, 104, 13, 0, // Skip to: 5255 +/* 1823 */ MCD_OPC_Decode, 220, 5, 107, // Opcode: EFSCTSF +/* 1827 */ MCD_OPC_FilterValue, 91, 121, 0, 0, // Skip to: 1953 +/* 1832 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 1835 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 1858 +/* 1840 */ MCD_OPC_CheckField, 26, 6, 4, 80, 13, 0, // Skip to: 5255 +/* 1847 */ MCD_OPC_CheckField, 16, 5, 0, 73, 13, 0, // Skip to: 5255 +/* 1854 */ MCD_OPC_Decode, 225, 5, 107, // Opcode: EFSCTUIZ +/* 1858 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 1881 +/* 1863 */ MCD_OPC_CheckField, 26, 6, 4, 57, 13, 0, // Skip to: 5255 +/* 1870 */ MCD_OPC_CheckField, 16, 5, 0, 50, 13, 0, // Skip to: 5255 +/* 1877 */ MCD_OPC_Decode, 222, 5, 107, // Opcode: EFSCTSIZ +/* 1881 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1905 +/* 1886 */ MCD_OPC_CheckField, 26, 6, 4, 34, 13, 0, // Skip to: 5255 +/* 1893 */ MCD_OPC_CheckField, 21, 2, 0, 27, 13, 0, // Skip to: 5255 +/* 1900 */ MCD_OPC_Decode, 232, 5, 244, 1, // Opcode: EFSTSTGT +/* 1905 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1929 +/* 1910 */ MCD_OPC_CheckField, 26, 6, 4, 10, 13, 0, // Skip to: 5255 +/* 1917 */ MCD_OPC_CheckField, 21, 2, 0, 3, 13, 0, // Skip to: 5255 +/* 1924 */ MCD_OPC_Decode, 233, 5, 244, 1, // Opcode: EFSTSTLT +/* 1929 */ MCD_OPC_FilterValue, 6, 249, 12, 0, // Skip to: 5255 +/* 1934 */ MCD_OPC_CheckField, 26, 6, 4, 242, 12, 0, // Skip to: 5255 +/* 1941 */ MCD_OPC_CheckField, 21, 2, 0, 235, 12, 0, // Skip to: 5255 +/* 1948 */ MCD_OPC_Decode, 231, 5, 244, 1, // Opcode: EFSTSTEQ +/* 1953 */ MCD_OPC_FilterValue, 92, 157, 0, 0, // Skip to: 2115 +/* 1958 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 1961 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1978 +/* 1966 */ MCD_OPC_CheckField, 26, 6, 4, 210, 12, 0, // Skip to: 5255 +/* 1973 */ MCD_OPC_Decode, 183, 5, 238, 1, // Opcode: EFDADD +/* 1978 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 1995 +/* 1983 */ MCD_OPC_CheckField, 26, 6, 4, 193, 12, 0, // Skip to: 5255 +/* 1990 */ MCD_OPC_Decode, 206, 5, 238, 1, // Opcode: EFDSUB +/* 1995 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2019 +/* 2000 */ MCD_OPC_CheckField, 26, 6, 4, 176, 12, 0, // Skip to: 5255 +/* 2007 */ MCD_OPC_CheckField, 16, 5, 0, 169, 12, 0, // Skip to: 5255 +/* 2014 */ MCD_OPC_Decode, 190, 5, 248, 1, // Opcode: EFDCFUID +/* 2019 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2043 +/* 2024 */ MCD_OPC_CheckField, 26, 6, 4, 152, 12, 0, // Skip to: 5255 +/* 2031 */ MCD_OPC_CheckField, 16, 5, 0, 145, 12, 0, // Skip to: 5255 +/* 2038 */ MCD_OPC_Decode, 187, 5, 248, 1, // Opcode: EFDCFSID +/* 2043 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2067 +/* 2048 */ MCD_OPC_CheckField, 26, 6, 4, 128, 12, 0, // Skip to: 5255 +/* 2055 */ MCD_OPC_CheckField, 11, 5, 0, 121, 12, 0, // Skip to: 5255 +/* 2062 */ MCD_OPC_Decode, 182, 5, 241, 1, // Opcode: EFDABS +/* 2067 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2091 +/* 2072 */ MCD_OPC_CheckField, 26, 6, 4, 104, 12, 0, // Skip to: 5255 +/* 2079 */ MCD_OPC_CheckField, 11, 5, 0, 97, 12, 0, // Skip to: 5255 +/* 2086 */ MCD_OPC_Decode, 204, 5, 241, 1, // Opcode: EFDNABS +/* 2091 */ MCD_OPC_FilterValue, 6, 87, 12, 0, // Skip to: 5255 +/* 2096 */ MCD_OPC_CheckField, 26, 6, 4, 80, 12, 0, // Skip to: 5255 +/* 2103 */ MCD_OPC_CheckField, 11, 5, 0, 73, 12, 0, // Skip to: 5255 +/* 2110 */ MCD_OPC_Decode, 205, 5, 241, 1, // Opcode: EFDNEG +/* 2115 */ MCD_OPC_FilterValue, 93, 181, 0, 0, // Skip to: 2301 +/* 2120 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 2123 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2140 +/* 2128 */ MCD_OPC_CheckField, 26, 6, 4, 48, 12, 0, // Skip to: 5255 +/* 2135 */ MCD_OPC_Decode, 203, 5, 238, 1, // Opcode: EFDMUL +/* 2140 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2157 +/* 2145 */ MCD_OPC_CheckField, 26, 6, 4, 31, 12, 0, // Skip to: 5255 +/* 2152 */ MCD_OPC_Decode, 202, 5, 238, 1, // Opcode: EFDDIV +/* 2157 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2181 +/* 2162 */ MCD_OPC_CheckField, 26, 6, 4, 14, 12, 0, // Skip to: 5255 +/* 2169 */ MCD_OPC_CheckField, 16, 5, 0, 7, 12, 0, // Skip to: 5255 +/* 2176 */ MCD_OPC_Decode, 200, 5, 247, 1, // Opcode: EFDCTUIDZ +/* 2181 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2205 +/* 2186 */ MCD_OPC_CheckField, 26, 6, 4, 246, 11, 0, // Skip to: 5255 +/* 2193 */ MCD_OPC_CheckField, 16, 5, 0, 239, 11, 0, // Skip to: 5255 +/* 2200 */ MCD_OPC_Decode, 196, 5, 247, 1, // Opcode: EFDCTSIDZ +/* 2205 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2229 +/* 2210 */ MCD_OPC_CheckField, 26, 6, 4, 222, 11, 0, // Skip to: 5255 +/* 2217 */ MCD_OPC_CheckField, 21, 2, 0, 215, 11, 0, // Skip to: 5255 +/* 2224 */ MCD_OPC_Decode, 192, 5, 244, 1, // Opcode: EFDCMPGT +/* 2229 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2253 +/* 2234 */ MCD_OPC_CheckField, 26, 6, 4, 198, 11, 0, // Skip to: 5255 +/* 2241 */ MCD_OPC_CheckField, 21, 2, 0, 191, 11, 0, // Skip to: 5255 +/* 2248 */ MCD_OPC_Decode, 193, 5, 244, 1, // Opcode: EFDCMPLT +/* 2253 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 2277 +/* 2258 */ MCD_OPC_CheckField, 26, 6, 4, 174, 11, 0, // Skip to: 5255 +/* 2265 */ MCD_OPC_CheckField, 21, 2, 0, 167, 11, 0, // Skip to: 5255 +/* 2272 */ MCD_OPC_Decode, 191, 5, 244, 1, // Opcode: EFDCMPEQ +/* 2277 */ MCD_OPC_FilterValue, 7, 157, 11, 0, // Skip to: 5255 +/* 2282 */ MCD_OPC_CheckField, 26, 6, 4, 150, 11, 0, // Skip to: 5255 +/* 2289 */ MCD_OPC_CheckField, 16, 5, 0, 143, 11, 0, // Skip to: 5255 +/* 2296 */ MCD_OPC_Decode, 184, 5, 248, 1, // Opcode: EFDCFS +/* 2301 */ MCD_OPC_FilterValue, 94, 195, 0, 0, // Skip to: 2501 +/* 2306 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 2309 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2333 +/* 2314 */ MCD_OPC_CheckField, 26, 6, 4, 118, 11, 0, // Skip to: 5255 +/* 2321 */ MCD_OPC_CheckField, 16, 5, 0, 111, 11, 0, // Skip to: 5255 +/* 2328 */ MCD_OPC_Decode, 189, 5, 248, 1, // Opcode: EFDCFUI +/* 2333 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 2357 +/* 2338 */ MCD_OPC_CheckField, 26, 6, 4, 94, 11, 0, // Skip to: 5255 +/* 2345 */ MCD_OPC_CheckField, 16, 5, 0, 87, 11, 0, // Skip to: 5255 +/* 2352 */ MCD_OPC_Decode, 186, 5, 248, 1, // Opcode: EFDCFSI +/* 2357 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2381 +/* 2362 */ MCD_OPC_CheckField, 26, 6, 4, 70, 11, 0, // Skip to: 5255 +/* 2369 */ MCD_OPC_CheckField, 16, 5, 0, 63, 11, 0, // Skip to: 5255 +/* 2376 */ MCD_OPC_Decode, 188, 5, 248, 1, // Opcode: EFDCFUF +/* 2381 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2405 +/* 2386 */ MCD_OPC_CheckField, 26, 6, 4, 46, 11, 0, // Skip to: 5255 +/* 2393 */ MCD_OPC_CheckField, 16, 5, 0, 39, 11, 0, // Skip to: 5255 +/* 2400 */ MCD_OPC_Decode, 185, 5, 248, 1, // Opcode: EFDCFSF +/* 2405 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2429 +/* 2410 */ MCD_OPC_CheckField, 26, 6, 4, 22, 11, 0, // Skip to: 5255 +/* 2417 */ MCD_OPC_CheckField, 16, 5, 0, 15, 11, 0, // Skip to: 5255 +/* 2424 */ MCD_OPC_Decode, 199, 5, 247, 1, // Opcode: EFDCTUI +/* 2429 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2453 +/* 2434 */ MCD_OPC_CheckField, 26, 6, 4, 254, 10, 0, // Skip to: 5255 +/* 2441 */ MCD_OPC_CheckField, 16, 5, 0, 247, 10, 0, // Skip to: 5255 +/* 2448 */ MCD_OPC_Decode, 195, 5, 247, 1, // Opcode: EFDCTSI +/* 2453 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 2477 +/* 2458 */ MCD_OPC_CheckField, 26, 6, 4, 230, 10, 0, // Skip to: 5255 +/* 2465 */ MCD_OPC_CheckField, 16, 5, 0, 223, 10, 0, // Skip to: 5255 +/* 2472 */ MCD_OPC_Decode, 198, 5, 248, 1, // Opcode: EFDCTUF +/* 2477 */ MCD_OPC_FilterValue, 7, 213, 10, 0, // Skip to: 5255 +/* 2482 */ MCD_OPC_CheckField, 26, 6, 4, 206, 10, 0, // Skip to: 5255 +/* 2489 */ MCD_OPC_CheckField, 16, 5, 0, 199, 10, 0, // Skip to: 5255 +/* 2496 */ MCD_OPC_Decode, 194, 5, 248, 1, // Opcode: EFDCTSF +/* 2501 */ MCD_OPC_FilterValue, 95, 123, 0, 0, // Skip to: 2629 +/* 2506 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 2509 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2533 +/* 2514 */ MCD_OPC_CheckField, 26, 6, 4, 174, 10, 0, // Skip to: 5255 +/* 2521 */ MCD_OPC_CheckField, 16, 5, 0, 167, 10, 0, // Skip to: 5255 +/* 2528 */ MCD_OPC_Decode, 201, 5, 247, 1, // Opcode: EFDCTUIZ +/* 2533 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2557 +/* 2538 */ MCD_OPC_CheckField, 26, 6, 4, 150, 10, 0, // Skip to: 5255 +/* 2545 */ MCD_OPC_CheckField, 16, 5, 0, 143, 10, 0, // Skip to: 5255 +/* 2552 */ MCD_OPC_Decode, 197, 5, 247, 1, // Opcode: EFDCTSIZ +/* 2557 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2581 +/* 2562 */ MCD_OPC_CheckField, 26, 6, 4, 126, 10, 0, // Skip to: 5255 +/* 2569 */ MCD_OPC_CheckField, 21, 2, 0, 119, 10, 0, // Skip to: 5255 +/* 2576 */ MCD_OPC_Decode, 208, 5, 244, 1, // Opcode: EFDTSTGT +/* 2581 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2605 +/* 2586 */ MCD_OPC_CheckField, 26, 6, 4, 102, 10, 0, // Skip to: 5255 +/* 2593 */ MCD_OPC_CheckField, 21, 2, 0, 95, 10, 0, // Skip to: 5255 +/* 2600 */ MCD_OPC_Decode, 209, 5, 244, 1, // Opcode: EFDTSTLT +/* 2605 */ MCD_OPC_FilterValue, 6, 85, 10, 0, // Skip to: 5255 +/* 2610 */ MCD_OPC_CheckField, 26, 6, 4, 78, 10, 0, // Skip to: 5255 +/* 2617 */ MCD_OPC_CheckField, 21, 2, 0, 71, 10, 0, // Skip to: 5255 +/* 2624 */ MCD_OPC_Decode, 207, 5, 244, 1, // Opcode: EFDTSTEQ +/* 2629 */ MCD_OPC_FilterValue, 96, 105, 0, 0, // Skip to: 2739 +/* 2634 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 2637 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2654 +/* 2642 */ MCD_OPC_CheckField, 26, 6, 4, 46, 10, 0, // Skip to: 5255 +/* 2649 */ MCD_OPC_Decode, 160, 6, 249, 1, // Opcode: EVLDDX +/* 2654 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2671 +/* 2659 */ MCD_OPC_CheckField, 26, 6, 4, 29, 10, 0, // Skip to: 5255 +/* 2666 */ MCD_OPC_Decode, 159, 6, 250, 1, // Opcode: EVLDD +/* 2671 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 2688 +/* 2676 */ MCD_OPC_CheckField, 26, 6, 4, 12, 10, 0, // Skip to: 5255 +/* 2683 */ MCD_OPC_Decode, 164, 6, 249, 1, // Opcode: EVLDWX +/* 2688 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 2705 +/* 2693 */ MCD_OPC_CheckField, 26, 6, 4, 251, 9, 0, // Skip to: 5255 +/* 2700 */ MCD_OPC_Decode, 163, 6, 250, 1, // Opcode: EVLDW +/* 2705 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 2722 +/* 2710 */ MCD_OPC_CheckField, 26, 6, 4, 234, 9, 0, // Skip to: 5255 +/* 2717 */ MCD_OPC_Decode, 162, 6, 249, 1, // Opcode: EVLDHX +/* 2722 */ MCD_OPC_FilterValue, 5, 224, 9, 0, // Skip to: 5255 +/* 2727 */ MCD_OPC_CheckField, 26, 6, 4, 217, 9, 0, // Skip to: 5255 +/* 2734 */ MCD_OPC_Decode, 161, 6, 250, 1, // Opcode: EVLDH +/* 2739 */ MCD_OPC_FilterValue, 97, 105, 0, 0, // Skip to: 2849 +/* 2744 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 2747 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2764 +/* 2752 */ MCD_OPC_CheckField, 26, 6, 4, 192, 9, 0, // Skip to: 5255 +/* 2759 */ MCD_OPC_Decode, 166, 6, 249, 1, // Opcode: EVLHHESPLATX +/* 2764 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2781 +/* 2769 */ MCD_OPC_CheckField, 26, 6, 4, 175, 9, 0, // Skip to: 5255 +/* 2776 */ MCD_OPC_Decode, 165, 6, 251, 1, // Opcode: EVLHHESPLAT +/* 2781 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 2798 +/* 2786 */ MCD_OPC_CheckField, 26, 6, 4, 158, 9, 0, // Skip to: 5255 +/* 2793 */ MCD_OPC_Decode, 170, 6, 249, 1, // Opcode: EVLHHOUSPLATX +/* 2798 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 2815 +/* 2803 */ MCD_OPC_CheckField, 26, 6, 4, 141, 9, 0, // Skip to: 5255 +/* 2810 */ MCD_OPC_Decode, 169, 6, 251, 1, // Opcode: EVLHHOUSPLAT +/* 2815 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 2832 +/* 2820 */ MCD_OPC_CheckField, 26, 6, 4, 124, 9, 0, // Skip to: 5255 +/* 2827 */ MCD_OPC_Decode, 168, 6, 249, 1, // Opcode: EVLHHOSSPLATX +/* 2832 */ MCD_OPC_FilterValue, 7, 114, 9, 0, // Skip to: 5255 +/* 2837 */ MCD_OPC_CheckField, 26, 6, 4, 107, 9, 0, // Skip to: 5255 +/* 2844 */ MCD_OPC_Decode, 167, 6, 251, 1, // Opcode: EVLHHOSSPLAT +/* 2849 */ MCD_OPC_FilterValue, 98, 105, 0, 0, // Skip to: 2959 +/* 2854 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 2857 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2874 +/* 2862 */ MCD_OPC_CheckField, 26, 6, 4, 82, 9, 0, // Skip to: 5255 +/* 2869 */ MCD_OPC_Decode, 172, 6, 249, 1, // Opcode: EVLWHEX +/* 2874 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2891 +/* 2879 */ MCD_OPC_CheckField, 26, 6, 4, 65, 9, 0, // Skip to: 5255 +/* 2886 */ MCD_OPC_Decode, 171, 6, 252, 1, // Opcode: EVLWHE +/* 2891 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 2908 +/* 2896 */ MCD_OPC_CheckField, 26, 6, 4, 48, 9, 0, // Skip to: 5255 +/* 2903 */ MCD_OPC_Decode, 176, 6, 249, 1, // Opcode: EVLWHOUX +/* 2908 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 2925 +/* 2913 */ MCD_OPC_CheckField, 26, 6, 4, 31, 9, 0, // Skip to: 5255 +/* 2920 */ MCD_OPC_Decode, 175, 6, 252, 1, // Opcode: EVLWHOU +/* 2925 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 2942 +/* 2930 */ MCD_OPC_CheckField, 26, 6, 4, 14, 9, 0, // Skip to: 5255 +/* 2937 */ MCD_OPC_Decode, 174, 6, 249, 1, // Opcode: EVLWHOSX +/* 2942 */ MCD_OPC_FilterValue, 7, 4, 9, 0, // Skip to: 5255 +/* 2947 */ MCD_OPC_CheckField, 26, 6, 4, 253, 8, 0, // Skip to: 5255 +/* 2954 */ MCD_OPC_Decode, 173, 6, 252, 1, // Opcode: EVLWHOS +/* 2959 */ MCD_OPC_FilterValue, 99, 71, 0, 0, // Skip to: 3035 +/* 2964 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 2967 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2984 +/* 2972 */ MCD_OPC_CheckField, 26, 6, 4, 228, 8, 0, // Skip to: 5255 +/* 2979 */ MCD_OPC_Decode, 180, 6, 249, 1, // Opcode: EVLWWSPLATX +/* 2984 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3001 +/* 2989 */ MCD_OPC_CheckField, 26, 6, 4, 211, 8, 0, // Skip to: 5255 +/* 2996 */ MCD_OPC_Decode, 179, 6, 252, 1, // Opcode: EVLWWSPLAT +/* 3001 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3018 +/* 3006 */ MCD_OPC_CheckField, 26, 6, 4, 194, 8, 0, // Skip to: 5255 +/* 3013 */ MCD_OPC_Decode, 178, 6, 249, 1, // Opcode: EVLWHSPLATX +/* 3018 */ MCD_OPC_FilterValue, 5, 184, 8, 0, // Skip to: 5255 +/* 3023 */ MCD_OPC_CheckField, 26, 6, 4, 177, 8, 0, // Skip to: 5255 +/* 3030 */ MCD_OPC_Decode, 177, 6, 252, 1, // Opcode: EVLWHSPLAT +/* 3035 */ MCD_OPC_FilterValue, 100, 105, 0, 0, // Skip to: 3145 +/* 3040 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3043 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3060 +/* 3048 */ MCD_OPC_CheckField, 26, 6, 4, 152, 8, 0, // Skip to: 5255 +/* 3055 */ MCD_OPC_Decode, 162, 7, 249, 1, // Opcode: EVSTDDX +/* 3060 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3077 +/* 3065 */ MCD_OPC_CheckField, 26, 6, 4, 135, 8, 0, // Skip to: 5255 +/* 3072 */ MCD_OPC_Decode, 161, 7, 250, 1, // Opcode: EVSTDD +/* 3077 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 3094 +/* 3082 */ MCD_OPC_CheckField, 26, 6, 4, 118, 8, 0, // Skip to: 5255 +/* 3089 */ MCD_OPC_Decode, 166, 7, 249, 1, // Opcode: EVSTDWX +/* 3094 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3111 +/* 3099 */ MCD_OPC_CheckField, 26, 6, 4, 101, 8, 0, // Skip to: 5255 +/* 3106 */ MCD_OPC_Decode, 165, 7, 250, 1, // Opcode: EVSTDW +/* 3111 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3128 +/* 3116 */ MCD_OPC_CheckField, 26, 6, 4, 84, 8, 0, // Skip to: 5255 +/* 3123 */ MCD_OPC_Decode, 164, 7, 249, 1, // Opcode: EVSTDHX +/* 3128 */ MCD_OPC_FilterValue, 5, 74, 8, 0, // Skip to: 5255 +/* 3133 */ MCD_OPC_CheckField, 26, 6, 4, 67, 8, 0, // Skip to: 5255 +/* 3140 */ MCD_OPC_Decode, 163, 7, 250, 1, // Opcode: EVSTDH +/* 3145 */ MCD_OPC_FilterValue, 102, 71, 0, 0, // Skip to: 3221 +/* 3150 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3153 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3170 +/* 3158 */ MCD_OPC_CheckField, 26, 6, 4, 42, 8, 0, // Skip to: 5255 +/* 3165 */ MCD_OPC_Decode, 168, 7, 249, 1, // Opcode: EVSTWHEX +/* 3170 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3187 +/* 3175 */ MCD_OPC_CheckField, 26, 6, 4, 25, 8, 0, // Skip to: 5255 +/* 3182 */ MCD_OPC_Decode, 167, 7, 252, 1, // Opcode: EVSTWHE +/* 3187 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3204 +/* 3192 */ MCD_OPC_CheckField, 26, 6, 4, 8, 8, 0, // Skip to: 5255 +/* 3199 */ MCD_OPC_Decode, 170, 7, 249, 1, // Opcode: EVSTWHOX +/* 3204 */ MCD_OPC_FilterValue, 5, 254, 7, 0, // Skip to: 5255 +/* 3209 */ MCD_OPC_CheckField, 26, 6, 4, 247, 7, 0, // Skip to: 5255 +/* 3216 */ MCD_OPC_Decode, 169, 7, 252, 1, // Opcode: EVSTWHO +/* 3221 */ MCD_OPC_FilterValue, 103, 71, 0, 0, // Skip to: 3297 +/* 3226 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3229 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3246 +/* 3234 */ MCD_OPC_CheckField, 26, 6, 4, 222, 7, 0, // Skip to: 5255 +/* 3241 */ MCD_OPC_Decode, 172, 7, 249, 1, // Opcode: EVSTWWEX +/* 3246 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3263 +/* 3251 */ MCD_OPC_CheckField, 26, 6, 4, 205, 7, 0, // Skip to: 5255 +/* 3258 */ MCD_OPC_Decode, 171, 7, 252, 1, // Opcode: EVSTWWE +/* 3263 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3280 +/* 3268 */ MCD_OPC_CheckField, 26, 6, 4, 188, 7, 0, // Skip to: 5255 +/* 3275 */ MCD_OPC_Decode, 174, 7, 249, 1, // Opcode: EVSTWWOX +/* 3280 */ MCD_OPC_FilterValue, 5, 178, 7, 0, // Skip to: 5255 +/* 3285 */ MCD_OPC_CheckField, 26, 6, 4, 171, 7, 0, // Skip to: 5255 +/* 3292 */ MCD_OPC_Decode, 173, 7, 252, 1, // Opcode: EVSTWWO +/* 3297 */ MCD_OPC_FilterValue, 128, 1, 37, 0, 0, // Skip to: 3340 +/* 3303 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3306 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3323 +/* 3311 */ MCD_OPC_CheckField, 26, 6, 4, 145, 7, 0, // Skip to: 5255 +/* 3318 */ MCD_OPC_Decode, 199, 6, 238, 1, // Opcode: EVMHESSF +/* 3323 */ MCD_OPC_FilterValue, 7, 135, 7, 0, // Skip to: 5255 +/* 3328 */ MCD_OPC_CheckField, 26, 6, 4, 128, 7, 0, // Skip to: 5255 +/* 3335 */ MCD_OPC_Decode, 225, 6, 238, 1, // Opcode: EVMHOSSF +/* 3340 */ MCD_OPC_FilterValue, 129, 1, 105, 0, 0, // Skip to: 3451 +/* 3346 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3349 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3366 +/* 3354 */ MCD_OPC_CheckField, 26, 6, 4, 102, 7, 0, // Skip to: 5255 +/* 3361 */ MCD_OPC_Decode, 205, 6, 238, 1, // Opcode: EVMHEUMI +/* 3366 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3383 +/* 3371 */ MCD_OPC_CheckField, 26, 6, 4, 85, 7, 0, // Skip to: 5255 +/* 3378 */ MCD_OPC_Decode, 195, 6, 238, 1, // Opcode: EVMHESMI +/* 3383 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3400 +/* 3388 */ MCD_OPC_CheckField, 26, 6, 4, 68, 7, 0, // Skip to: 5255 +/* 3395 */ MCD_OPC_Decode, 191, 6, 238, 1, // Opcode: EVMHESMF +/* 3400 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3417 +/* 3405 */ MCD_OPC_CheckField, 26, 6, 4, 51, 7, 0, // Skip to: 5255 +/* 3412 */ MCD_OPC_Decode, 231, 6, 238, 1, // Opcode: EVMHOUMI +/* 3417 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3434 +/* 3422 */ MCD_OPC_CheckField, 26, 6, 4, 34, 7, 0, // Skip to: 5255 +/* 3429 */ MCD_OPC_Decode, 221, 6, 238, 1, // Opcode: EVMHOSMI +/* 3434 */ MCD_OPC_FilterValue, 7, 24, 7, 0, // Skip to: 5255 +/* 3439 */ MCD_OPC_CheckField, 26, 6, 4, 17, 7, 0, // Skip to: 5255 +/* 3446 */ MCD_OPC_Decode, 217, 6, 238, 1, // Opcode: EVMHOSMF +/* 3451 */ MCD_OPC_FilterValue, 132, 1, 37, 0, 0, // Skip to: 3494 +/* 3457 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3460 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3477 +/* 3465 */ MCD_OPC_CheckField, 26, 6, 4, 247, 6, 0, // Skip to: 5255 +/* 3472 */ MCD_OPC_Decode, 200, 6, 238, 1, // Opcode: EVMHESSFA +/* 3477 */ MCD_OPC_FilterValue, 7, 237, 6, 0, // Skip to: 5255 +/* 3482 */ MCD_OPC_CheckField, 26, 6, 4, 230, 6, 0, // Skip to: 5255 +/* 3489 */ MCD_OPC_Decode, 226, 6, 238, 1, // Opcode: EVMHOSSFA +/* 3494 */ MCD_OPC_FilterValue, 133, 1, 105, 0, 0, // Skip to: 3605 +/* 3500 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3503 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3520 +/* 3508 */ MCD_OPC_CheckField, 26, 6, 4, 204, 6, 0, // Skip to: 5255 +/* 3515 */ MCD_OPC_Decode, 206, 6, 238, 1, // Opcode: EVMHEUMIA +/* 3520 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3537 +/* 3525 */ MCD_OPC_CheckField, 26, 6, 4, 187, 6, 0, // Skip to: 5255 +/* 3532 */ MCD_OPC_Decode, 196, 6, 238, 1, // Opcode: EVMHESMIA +/* 3537 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3554 +/* 3542 */ MCD_OPC_CheckField, 26, 6, 4, 170, 6, 0, // Skip to: 5255 +/* 3549 */ MCD_OPC_Decode, 192, 6, 238, 1, // Opcode: EVMHESMFA +/* 3554 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3571 +/* 3559 */ MCD_OPC_CheckField, 26, 6, 4, 153, 6, 0, // Skip to: 5255 +/* 3566 */ MCD_OPC_Decode, 232, 6, 238, 1, // Opcode: EVMHOUMIA +/* 3571 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3588 +/* 3576 */ MCD_OPC_CheckField, 26, 6, 4, 136, 6, 0, // Skip to: 5255 +/* 3583 */ MCD_OPC_Decode, 222, 6, 238, 1, // Opcode: EVMHOSMIA +/* 3588 */ MCD_OPC_FilterValue, 7, 126, 6, 0, // Skip to: 5255 +/* 3593 */ MCD_OPC_CheckField, 26, 6, 4, 119, 6, 0, // Skip to: 5255 +/* 3600 */ MCD_OPC_Decode, 218, 6, 238, 1, // Opcode: EVMHOSMFA +/* 3605 */ MCD_OPC_FilterValue, 136, 1, 19, 0, 0, // Skip to: 3630 +/* 3611 */ MCD_OPC_CheckField, 26, 6, 4, 101, 6, 0, // Skip to: 5255 +/* 3618 */ MCD_OPC_CheckField, 0, 3, 7, 94, 6, 0, // Skip to: 5255 +/* 3625 */ MCD_OPC_Decode, 242, 6, 238, 1, // Opcode: EVMWHSSF +/* 3630 */ MCD_OPC_FilterValue, 137, 1, 71, 0, 0, // Skip to: 3707 +/* 3636 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3639 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3656 +/* 3644 */ MCD_OPC_CheckField, 26, 6, 4, 68, 6, 0, // Skip to: 5255 +/* 3651 */ MCD_OPC_Decode, 250, 6, 238, 1, // Opcode: EVMWLUMI +/* 3656 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3673 +/* 3661 */ MCD_OPC_CheckField, 26, 6, 4, 51, 6, 0, // Skip to: 5255 +/* 3668 */ MCD_OPC_Decode, 244, 6, 238, 1, // Opcode: EVMWHUMI +/* 3673 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3690 +/* 3678 */ MCD_OPC_CheckField, 26, 6, 4, 34, 6, 0, // Skip to: 5255 +/* 3685 */ MCD_OPC_Decode, 240, 6, 238, 1, // Opcode: EVMWHSMI +/* 3690 */ MCD_OPC_FilterValue, 7, 24, 6, 0, // Skip to: 5255 +/* 3695 */ MCD_OPC_CheckField, 26, 6, 4, 17, 6, 0, // Skip to: 5255 +/* 3702 */ MCD_OPC_Decode, 238, 6, 238, 1, // Opcode: EVMWHSMF +/* 3707 */ MCD_OPC_FilterValue, 138, 1, 19, 0, 0, // Skip to: 3732 +/* 3713 */ MCD_OPC_CheckField, 26, 6, 4, 255, 5, 0, // Skip to: 5255 +/* 3720 */ MCD_OPC_CheckField, 0, 3, 3, 248, 5, 0, // Skip to: 5255 +/* 3727 */ MCD_OPC_Decode, 136, 7, 238, 1, // Opcode: EVMWSSF +/* 3732 */ MCD_OPC_FilterValue, 139, 1, 54, 0, 0, // Skip to: 3792 +/* 3738 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3741 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3758 +/* 3746 */ MCD_OPC_CheckField, 26, 6, 4, 222, 5, 0, // Skip to: 5255 +/* 3753 */ MCD_OPC_Decode, 140, 7, 238, 1, // Opcode: EVMWUMI +/* 3758 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3775 +/* 3763 */ MCD_OPC_CheckField, 26, 6, 4, 205, 5, 0, // Skip to: 5255 +/* 3770 */ MCD_OPC_Decode, 132, 7, 238, 1, // Opcode: EVMWSMI +/* 3775 */ MCD_OPC_FilterValue, 3, 195, 5, 0, // Skip to: 5255 +/* 3780 */ MCD_OPC_CheckField, 26, 6, 4, 188, 5, 0, // Skip to: 5255 +/* 3787 */ MCD_OPC_Decode, 128, 7, 238, 1, // Opcode: EVMWSMF +/* 3792 */ MCD_OPC_FilterValue, 140, 1, 19, 0, 0, // Skip to: 3817 +/* 3798 */ MCD_OPC_CheckField, 26, 6, 4, 170, 5, 0, // Skip to: 5255 +/* 3805 */ MCD_OPC_CheckField, 0, 3, 7, 163, 5, 0, // Skip to: 5255 +/* 3812 */ MCD_OPC_Decode, 243, 6, 238, 1, // Opcode: EVMWHSSFA +/* 3817 */ MCD_OPC_FilterValue, 141, 1, 71, 0, 0, // Skip to: 3894 +/* 3823 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3826 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3843 +/* 3831 */ MCD_OPC_CheckField, 26, 6, 4, 137, 5, 0, // Skip to: 5255 +/* 3838 */ MCD_OPC_Decode, 251, 6, 238, 1, // Opcode: EVMWLUMIA +/* 3843 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3860 +/* 3848 */ MCD_OPC_CheckField, 26, 6, 4, 120, 5, 0, // Skip to: 5255 +/* 3855 */ MCD_OPC_Decode, 245, 6, 238, 1, // Opcode: EVMWHUMIA +/* 3860 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3877 +/* 3865 */ MCD_OPC_CheckField, 26, 6, 4, 103, 5, 0, // Skip to: 5255 +/* 3872 */ MCD_OPC_Decode, 241, 6, 238, 1, // Opcode: EVMWHSMIA +/* 3877 */ MCD_OPC_FilterValue, 7, 93, 5, 0, // Skip to: 5255 +/* 3882 */ MCD_OPC_CheckField, 26, 6, 4, 86, 5, 0, // Skip to: 5255 +/* 3889 */ MCD_OPC_Decode, 239, 6, 238, 1, // Opcode: EVMWHSMFA +/* 3894 */ MCD_OPC_FilterValue, 142, 1, 19, 0, 0, // Skip to: 3919 +/* 3900 */ MCD_OPC_CheckField, 26, 6, 4, 68, 5, 0, // Skip to: 5255 +/* 3907 */ MCD_OPC_CheckField, 0, 3, 3, 61, 5, 0, // Skip to: 5255 +/* 3914 */ MCD_OPC_Decode, 137, 7, 238, 1, // Opcode: EVMWSSFA +/* 3919 */ MCD_OPC_FilterValue, 143, 1, 54, 0, 0, // Skip to: 3979 +/* 3925 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3928 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3945 +/* 3933 */ MCD_OPC_CheckField, 26, 6, 4, 35, 5, 0, // Skip to: 5255 +/* 3940 */ MCD_OPC_Decode, 141, 7, 238, 1, // Opcode: EVMWUMIA +/* 3945 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3962 +/* 3950 */ MCD_OPC_CheckField, 26, 6, 4, 18, 5, 0, // Skip to: 5255 +/* 3957 */ MCD_OPC_Decode, 133, 7, 238, 1, // Opcode: EVMWSMIA +/* 3962 */ MCD_OPC_FilterValue, 3, 8, 5, 0, // Skip to: 5255 +/* 3967 */ MCD_OPC_CheckField, 26, 6, 4, 1, 5, 0, // Skip to: 5255 +/* 3974 */ MCD_OPC_Decode, 129, 7, 238, 1, // Opcode: EVMWSMFA +/* 3979 */ MCD_OPC_FilterValue, 152, 1, 157, 0, 0, // Skip to: 4142 +/* 3985 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 3988 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 4012 +/* 3993 */ MCD_OPC_CheckField, 26, 6, 4, 231, 4, 0, // Skip to: 5255 +/* 4000 */ MCD_OPC_CheckField, 11, 5, 0, 224, 4, 0, // Skip to: 5255 +/* 4007 */ MCD_OPC_Decode, 248, 5, 241, 1, // Opcode: EVADDUSIAAW +/* 4012 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 4036 +/* 4017 */ MCD_OPC_CheckField, 26, 6, 4, 207, 4, 0, // Skip to: 5255 +/* 4024 */ MCD_OPC_CheckField, 11, 5, 0, 200, 4, 0, // Skip to: 5255 +/* 4031 */ MCD_OPC_Decode, 246, 5, 241, 1, // Opcode: EVADDSSIAAW +/* 4036 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 4060 +/* 4041 */ MCD_OPC_CheckField, 26, 6, 4, 183, 4, 0, // Skip to: 5255 +/* 4048 */ MCD_OPC_CheckField, 11, 5, 0, 176, 4, 0, // Skip to: 5255 +/* 4055 */ MCD_OPC_Decode, 178, 7, 241, 1, // Opcode: EVSUBFUSIAAW +/* 4060 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 4084 +/* 4065 */ MCD_OPC_CheckField, 26, 6, 4, 159, 4, 0, // Skip to: 5255 +/* 4072 */ MCD_OPC_CheckField, 11, 5, 0, 152, 4, 0, // Skip to: 5255 +/* 4079 */ MCD_OPC_Decode, 176, 7, 241, 1, // Opcode: EVSUBFSSIAAW +/* 4084 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 4108 +/* 4089 */ MCD_OPC_CheckField, 26, 6, 4, 135, 4, 0, // Skip to: 5255 +/* 4096 */ MCD_OPC_CheckField, 11, 5, 0, 128, 4, 0, // Skip to: 5255 +/* 4103 */ MCD_OPC_Decode, 237, 6, 241, 1, // Opcode: EVMRA +/* 4108 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 4125 +/* 4113 */ MCD_OPC_CheckField, 26, 6, 4, 111, 4, 0, // Skip to: 5255 +/* 4120 */ MCD_OPC_Decode, 131, 6, 238, 1, // Opcode: EVDIVWS +/* 4125 */ MCD_OPC_FilterValue, 7, 101, 4, 0, // Skip to: 5255 +/* 4130 */ MCD_OPC_CheckField, 26, 6, 4, 94, 4, 0, // Skip to: 5255 +/* 4137 */ MCD_OPC_Decode, 132, 6, 238, 1, // Opcode: EVDIVWU +/* 4142 */ MCD_OPC_FilterValue, 153, 1, 99, 0, 0, // Skip to: 4247 +/* 4148 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4151 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 4175 +/* 4156 */ MCD_OPC_CheckField, 26, 6, 4, 68, 4, 0, // Skip to: 5255 +/* 4163 */ MCD_OPC_CheckField, 11, 5, 0, 61, 4, 0, // Skip to: 5255 +/* 4170 */ MCD_OPC_Decode, 247, 5, 241, 1, // Opcode: EVADDUMIAAW +/* 4175 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 4199 +/* 4180 */ MCD_OPC_CheckField, 26, 6, 4, 44, 4, 0, // Skip to: 5255 +/* 4187 */ MCD_OPC_CheckField, 11, 5, 0, 37, 4, 0, // Skip to: 5255 +/* 4194 */ MCD_OPC_Decode, 245, 5, 241, 1, // Opcode: EVADDSMIAAW +/* 4199 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 4223 +/* 4204 */ MCD_OPC_CheckField, 26, 6, 4, 20, 4, 0, // Skip to: 5255 +/* 4211 */ MCD_OPC_CheckField, 11, 5, 0, 13, 4, 0, // Skip to: 5255 +/* 4218 */ MCD_OPC_Decode, 177, 7, 241, 1, // Opcode: EVSUBFUMIAAW +/* 4223 */ MCD_OPC_FilterValue, 3, 3, 4, 0, // Skip to: 5255 +/* 4228 */ MCD_OPC_CheckField, 26, 6, 4, 252, 3, 0, // Skip to: 5255 +/* 4235 */ MCD_OPC_CheckField, 11, 5, 0, 245, 3, 0, // Skip to: 5255 +/* 4242 */ MCD_OPC_Decode, 175, 7, 241, 1, // Opcode: EVSUBFSMIAAW +/* 4247 */ MCD_OPC_FilterValue, 160, 1, 105, 0, 0, // Skip to: 4358 +/* 4253 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4256 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4273 +/* 4261 */ MCD_OPC_CheckField, 26, 6, 4, 219, 3, 0, // Skip to: 5255 +/* 4268 */ MCD_OPC_Decode, 209, 6, 238, 1, // Opcode: EVMHEUSIAAW +/* 4273 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4290 +/* 4278 */ MCD_OPC_CheckField, 26, 6, 4, 202, 3, 0, // Skip to: 5255 +/* 4285 */ MCD_OPC_Decode, 203, 6, 238, 1, // Opcode: EVMHESSIAAW +/* 4290 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4307 +/* 4295 */ MCD_OPC_CheckField, 26, 6, 4, 185, 3, 0, // Skip to: 5255 +/* 4302 */ MCD_OPC_Decode, 201, 6, 238, 1, // Opcode: EVMHESSFAAW +/* 4307 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4324 +/* 4312 */ MCD_OPC_CheckField, 26, 6, 4, 168, 3, 0, // Skip to: 5255 +/* 4319 */ MCD_OPC_Decode, 235, 6, 238, 1, // Opcode: EVMHOUSIAAW +/* 4324 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4341 +/* 4329 */ MCD_OPC_CheckField, 26, 6, 4, 151, 3, 0, // Skip to: 5255 +/* 4336 */ MCD_OPC_Decode, 229, 6, 238, 1, // Opcode: EVMHOSSIAAW +/* 4341 */ MCD_OPC_FilterValue, 7, 141, 3, 0, // Skip to: 5255 +/* 4346 */ MCD_OPC_CheckField, 26, 6, 4, 134, 3, 0, // Skip to: 5255 +/* 4353 */ MCD_OPC_Decode, 227, 6, 238, 1, // Opcode: EVMHOSSFAAW +/* 4358 */ MCD_OPC_FilterValue, 161, 1, 105, 0, 0, // Skip to: 4469 +/* 4364 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4367 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4384 +/* 4372 */ MCD_OPC_CheckField, 26, 6, 4, 108, 3, 0, // Skip to: 5255 +/* 4379 */ MCD_OPC_Decode, 207, 6, 238, 1, // Opcode: EVMHEUMIAAW +/* 4384 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4401 +/* 4389 */ MCD_OPC_CheckField, 26, 6, 4, 91, 3, 0, // Skip to: 5255 +/* 4396 */ MCD_OPC_Decode, 197, 6, 238, 1, // Opcode: EVMHESMIAAW +/* 4401 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4418 +/* 4406 */ MCD_OPC_CheckField, 26, 6, 4, 74, 3, 0, // Skip to: 5255 +/* 4413 */ MCD_OPC_Decode, 193, 6, 238, 1, // Opcode: EVMHESMFAAW +/* 4418 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4435 +/* 4423 */ MCD_OPC_CheckField, 26, 6, 4, 57, 3, 0, // Skip to: 5255 +/* 4430 */ MCD_OPC_Decode, 233, 6, 238, 1, // Opcode: EVMHOUMIAAW +/* 4435 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4452 +/* 4440 */ MCD_OPC_CheckField, 26, 6, 4, 40, 3, 0, // Skip to: 5255 +/* 4447 */ MCD_OPC_Decode, 223, 6, 238, 1, // Opcode: EVMHOSMIAAW +/* 4452 */ MCD_OPC_FilterValue, 7, 30, 3, 0, // Skip to: 5255 +/* 4457 */ MCD_OPC_CheckField, 26, 6, 4, 23, 3, 0, // Skip to: 5255 +/* 4464 */ MCD_OPC_Decode, 219, 6, 238, 1, // Opcode: EVMHOSMFAAW +/* 4469 */ MCD_OPC_FilterValue, 165, 1, 105, 0, 0, // Skip to: 4580 +/* 4475 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4478 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4495 +/* 4483 */ MCD_OPC_CheckField, 26, 6, 4, 253, 2, 0, // Skip to: 5255 +/* 4490 */ MCD_OPC_Decode, 189, 6, 238, 1, // Opcode: EVMHEGUMIAA +/* 4495 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4512 +/* 4500 */ MCD_OPC_CheckField, 26, 6, 4, 236, 2, 0, // Skip to: 5255 +/* 4507 */ MCD_OPC_Decode, 187, 6, 238, 1, // Opcode: EVMHEGSMIAA +/* 4512 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4529 +/* 4517 */ MCD_OPC_CheckField, 26, 6, 4, 219, 2, 0, // Skip to: 5255 +/* 4524 */ MCD_OPC_Decode, 185, 6, 238, 1, // Opcode: EVMHEGSMFAA +/* 4529 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4546 +/* 4534 */ MCD_OPC_CheckField, 26, 6, 4, 202, 2, 0, // Skip to: 5255 +/* 4541 */ MCD_OPC_Decode, 215, 6, 238, 1, // Opcode: EVMHOGUMIAA +/* 4546 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4563 +/* 4551 */ MCD_OPC_CheckField, 26, 6, 4, 185, 2, 0, // Skip to: 5255 +/* 4558 */ MCD_OPC_Decode, 213, 6, 238, 1, // Opcode: EVMHOGSMIAA +/* 4563 */ MCD_OPC_FilterValue, 7, 175, 2, 0, // Skip to: 5255 +/* 4568 */ MCD_OPC_CheckField, 26, 6, 4, 168, 2, 0, // Skip to: 5255 +/* 4575 */ MCD_OPC_Decode, 211, 6, 238, 1, // Opcode: EVMHOGSMFAA +/* 4580 */ MCD_OPC_FilterValue, 168, 1, 37, 0, 0, // Skip to: 4623 +/* 4586 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4589 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4606 +/* 4594 */ MCD_OPC_CheckField, 26, 6, 4, 142, 2, 0, // Skip to: 5255 +/* 4601 */ MCD_OPC_Decode, 254, 6, 238, 1, // Opcode: EVMWLUSIAAW +/* 4606 */ MCD_OPC_FilterValue, 1, 132, 2, 0, // Skip to: 5255 +/* 4611 */ MCD_OPC_CheckField, 26, 6, 4, 125, 2, 0, // Skip to: 5255 +/* 4618 */ MCD_OPC_Decode, 248, 6, 238, 1, // Opcode: EVMWLSSIAAW +/* 4623 */ MCD_OPC_FilterValue, 169, 1, 37, 0, 0, // Skip to: 4666 +/* 4629 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4632 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4649 +/* 4637 */ MCD_OPC_CheckField, 26, 6, 4, 99, 2, 0, // Skip to: 5255 +/* 4644 */ MCD_OPC_Decode, 252, 6, 238, 1, // Opcode: EVMWLUMIAAW +/* 4649 */ MCD_OPC_FilterValue, 1, 89, 2, 0, // Skip to: 5255 +/* 4654 */ MCD_OPC_CheckField, 26, 6, 4, 82, 2, 0, // Skip to: 5255 +/* 4661 */ MCD_OPC_Decode, 246, 6, 238, 1, // Opcode: EVMWLSMIAAW +/* 4666 */ MCD_OPC_FilterValue, 170, 1, 19, 0, 0, // Skip to: 4691 +/* 4672 */ MCD_OPC_CheckField, 26, 6, 4, 64, 2, 0, // Skip to: 5255 +/* 4679 */ MCD_OPC_CheckField, 0, 3, 3, 57, 2, 0, // Skip to: 5255 +/* 4686 */ MCD_OPC_Decode, 138, 7, 238, 1, // Opcode: EVMWSSFAA +/* 4691 */ MCD_OPC_FilterValue, 171, 1, 54, 0, 0, // Skip to: 4751 +/* 4697 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4700 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4717 +/* 4705 */ MCD_OPC_CheckField, 26, 6, 4, 31, 2, 0, // Skip to: 5255 +/* 4712 */ MCD_OPC_Decode, 142, 7, 238, 1, // Opcode: EVMWUMIAA +/* 4717 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4734 +/* 4722 */ MCD_OPC_CheckField, 26, 6, 4, 14, 2, 0, // Skip to: 5255 +/* 4729 */ MCD_OPC_Decode, 134, 7, 238, 1, // Opcode: EVMWSMIAA +/* 4734 */ MCD_OPC_FilterValue, 3, 4, 2, 0, // Skip to: 5255 +/* 4739 */ MCD_OPC_CheckField, 26, 6, 4, 253, 1, 0, // Skip to: 5255 +/* 4746 */ MCD_OPC_Decode, 130, 7, 238, 1, // Opcode: EVMWSMFAA +/* 4751 */ MCD_OPC_FilterValue, 176, 1, 105, 0, 0, // Skip to: 4862 +/* 4757 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4760 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4777 +/* 4765 */ MCD_OPC_CheckField, 26, 6, 4, 227, 1, 0, // Skip to: 5255 +/* 4772 */ MCD_OPC_Decode, 210, 6, 238, 1, // Opcode: EVMHEUSIANW +/* 4777 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4794 +/* 4782 */ MCD_OPC_CheckField, 26, 6, 4, 210, 1, 0, // Skip to: 5255 +/* 4789 */ MCD_OPC_Decode, 204, 6, 238, 1, // Opcode: EVMHESSIANW +/* 4794 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4811 +/* 4799 */ MCD_OPC_CheckField, 26, 6, 4, 193, 1, 0, // Skip to: 5255 +/* 4806 */ MCD_OPC_Decode, 202, 6, 238, 1, // Opcode: EVMHESSFANW +/* 4811 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4828 +/* 4816 */ MCD_OPC_CheckField, 26, 6, 4, 176, 1, 0, // Skip to: 5255 +/* 4823 */ MCD_OPC_Decode, 236, 6, 238, 1, // Opcode: EVMHOUSIANW +/* 4828 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4845 +/* 4833 */ MCD_OPC_CheckField, 26, 6, 4, 159, 1, 0, // Skip to: 5255 +/* 4840 */ MCD_OPC_Decode, 230, 6, 238, 1, // Opcode: EVMHOSSIANW +/* 4845 */ MCD_OPC_FilterValue, 7, 149, 1, 0, // Skip to: 5255 +/* 4850 */ MCD_OPC_CheckField, 26, 6, 4, 142, 1, 0, // Skip to: 5255 +/* 4857 */ MCD_OPC_Decode, 228, 6, 238, 1, // Opcode: EVMHOSSFANW +/* 4862 */ MCD_OPC_FilterValue, 177, 1, 105, 0, 0, // Skip to: 4973 +/* 4868 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4871 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4888 +/* 4876 */ MCD_OPC_CheckField, 26, 6, 4, 116, 1, 0, // Skip to: 5255 +/* 4883 */ MCD_OPC_Decode, 208, 6, 238, 1, // Opcode: EVMHEUMIANW +/* 4888 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4905 +/* 4893 */ MCD_OPC_CheckField, 26, 6, 4, 99, 1, 0, // Skip to: 5255 +/* 4900 */ MCD_OPC_Decode, 198, 6, 238, 1, // Opcode: EVMHESMIANW +/* 4905 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4922 +/* 4910 */ MCD_OPC_CheckField, 26, 6, 4, 82, 1, 0, // Skip to: 5255 +/* 4917 */ MCD_OPC_Decode, 194, 6, 238, 1, // Opcode: EVMHESMFANW +/* 4922 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4939 +/* 4927 */ MCD_OPC_CheckField, 26, 6, 4, 65, 1, 0, // Skip to: 5255 +/* 4934 */ MCD_OPC_Decode, 234, 6, 238, 1, // Opcode: EVMHOUMIANW +/* 4939 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4956 +/* 4944 */ MCD_OPC_CheckField, 26, 6, 4, 48, 1, 0, // Skip to: 5255 +/* 4951 */ MCD_OPC_Decode, 224, 6, 238, 1, // Opcode: EVMHOSMIANW +/* 4956 */ MCD_OPC_FilterValue, 7, 38, 1, 0, // Skip to: 5255 +/* 4961 */ MCD_OPC_CheckField, 26, 6, 4, 31, 1, 0, // Skip to: 5255 +/* 4968 */ MCD_OPC_Decode, 220, 6, 238, 1, // Opcode: EVMHOSMFANW +/* 4973 */ MCD_OPC_FilterValue, 181, 1, 105, 0, 0, // Skip to: 5084 +/* 4979 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 4982 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4999 +/* 4987 */ MCD_OPC_CheckField, 26, 6, 4, 5, 1, 0, // Skip to: 5255 +/* 4994 */ MCD_OPC_Decode, 190, 6, 238, 1, // Opcode: EVMHEGUMIAN +/* 4999 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 5016 +/* 5004 */ MCD_OPC_CheckField, 26, 6, 4, 244, 0, 0, // Skip to: 5255 +/* 5011 */ MCD_OPC_Decode, 188, 6, 238, 1, // Opcode: EVMHEGSMIAN +/* 5016 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 5033 +/* 5021 */ MCD_OPC_CheckField, 26, 6, 4, 227, 0, 0, // Skip to: 5255 +/* 5028 */ MCD_OPC_Decode, 186, 6, 238, 1, // Opcode: EVMHEGSMFAN +/* 5033 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 5050 +/* 5038 */ MCD_OPC_CheckField, 26, 6, 4, 210, 0, 0, // Skip to: 5255 +/* 5045 */ MCD_OPC_Decode, 216, 6, 238, 1, // Opcode: EVMHOGUMIAN +/* 5050 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 5067 +/* 5055 */ MCD_OPC_CheckField, 26, 6, 4, 193, 0, 0, // Skip to: 5255 +/* 5062 */ MCD_OPC_Decode, 214, 6, 238, 1, // Opcode: EVMHOGSMIAN +/* 5067 */ MCD_OPC_FilterValue, 7, 183, 0, 0, // Skip to: 5255 +/* 5072 */ MCD_OPC_CheckField, 26, 6, 4, 176, 0, 0, // Skip to: 5255 +/* 5079 */ MCD_OPC_Decode, 212, 6, 238, 1, // Opcode: EVMHOGSMFAN +/* 5084 */ MCD_OPC_FilterValue, 184, 1, 37, 0, 0, // Skip to: 5127 +/* 5090 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 5093 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5110 +/* 5098 */ MCD_OPC_CheckField, 26, 6, 4, 150, 0, 0, // Skip to: 5255 +/* 5105 */ MCD_OPC_Decode, 255, 6, 238, 1, // Opcode: EVMWLUSIANW +/* 5110 */ MCD_OPC_FilterValue, 1, 140, 0, 0, // Skip to: 5255 +/* 5115 */ MCD_OPC_CheckField, 26, 6, 4, 133, 0, 0, // Skip to: 5255 +/* 5122 */ MCD_OPC_Decode, 249, 6, 238, 1, // Opcode: EVMWLSSIANW +/* 5127 */ MCD_OPC_FilterValue, 185, 1, 37, 0, 0, // Skip to: 5170 +/* 5133 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 5136 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5153 +/* 5141 */ MCD_OPC_CheckField, 26, 6, 4, 107, 0, 0, // Skip to: 5255 +/* 5148 */ MCD_OPC_Decode, 253, 6, 238, 1, // Opcode: EVMWLUMIANW +/* 5153 */ MCD_OPC_FilterValue, 1, 97, 0, 0, // Skip to: 5255 +/* 5158 */ MCD_OPC_CheckField, 26, 6, 4, 90, 0, 0, // Skip to: 5255 +/* 5165 */ MCD_OPC_Decode, 247, 6, 238, 1, // Opcode: EVMWLSMIANW +/* 5170 */ MCD_OPC_FilterValue, 186, 1, 19, 0, 0, // Skip to: 5195 +/* 5176 */ MCD_OPC_CheckField, 26, 6, 4, 72, 0, 0, // Skip to: 5255 +/* 5183 */ MCD_OPC_CheckField, 0, 3, 3, 65, 0, 0, // Skip to: 5255 +/* 5190 */ MCD_OPC_Decode, 139, 7, 238, 1, // Opcode: EVMWSSFAN +/* 5195 */ MCD_OPC_FilterValue, 187, 1, 54, 0, 0, // Skip to: 5255 +/* 5201 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... +/* 5204 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5221 +/* 5209 */ MCD_OPC_CheckField, 26, 6, 4, 39, 0, 0, // Skip to: 5255 +/* 5216 */ MCD_OPC_Decode, 143, 7, 238, 1, // Opcode: EVMWUMIAN +/* 5221 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 5238 +/* 5226 */ MCD_OPC_CheckField, 26, 6, 4, 22, 0, 0, // Skip to: 5255 +/* 5233 */ MCD_OPC_Decode, 135, 7, 238, 1, // Opcode: EVMWSMIAN +/* 5238 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 5255 +/* 5243 */ MCD_OPC_CheckField, 26, 6, 4, 5, 0, 0, // Skip to: 5255 +/* 5250 */ MCD_OPC_Decode, 131, 7, 238, 1, // Opcode: EVMWSMFAN +/* 5255 */ MCD_OPC_Fail, 0 }; -static bool checkDecoderPredicate(unsigned Idx, MCInst *MI) +static bool getbool(uint64_t b) { - /* llvm_unreachable("Invalid index!");*/ - return true; + return b != 0; +} +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { + llvm_unreachable("Invalid index!"); } #define DecodeToMCInst(fname, fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, bool *Decoder) \ -{ \ - InsnType tmp; \ - switch (Idx) { \ - default: /* llvm_unreachable("Invalid index!");*/ \ - case 0: \ - return S; \ - case 1: \ - tmp = fieldname(insn, 21, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 2: \ - tmp = fieldname(insn, 21, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 3: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 4: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 5: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 9, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 6: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 7: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 9, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 8: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 9: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 15, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 10: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 11: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 12: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 13: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 14: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 15: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 16: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 17: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 18: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 19: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 20: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 21: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 22: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 23: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 24: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 25: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 26: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 27: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 28: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 29: \ - tmp = fieldname(insn, 2, 14); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 30: \ - tmp = fieldname(insn, 21, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 2, 14); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 31: \ - tmp = fieldname(insn, 5, 7); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 32: \ - tmp = fieldname(insn, 2, 24); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 33: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 34: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 35: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 0; \ - tmp |= fieldname(insn, 6, 10) << 6; \ - tmp |= fieldname(insn, 16, 5) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 36: \ - tmp = fieldname(insn, 21, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 37: \ - tmp = fieldname(insn, 11, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 38: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 1, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 39: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 1, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 40: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 1, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 41: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 16); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 42: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 1) << 5; \ - tmp |= fieldname(insn, 6, 5) << 0; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 43: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 1) << 5; \ - tmp |= fieldname(insn, 6, 5) << 0; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 44: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 1) << 5; \ - tmp |= fieldname(insn, 6, 5) << 0; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 45: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 46: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 47: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 18, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 48: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 49: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 50: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 51: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 52: \ - tmp = fieldname(insn, 15, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 53: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 54: \ - tmp = fieldname(insn, 21, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 55: \ - tmp = fieldname(insn, 21, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 56: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 57: \ - tmp = fieldname(insn, 21, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 58: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 59: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 60: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 61: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 62: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 63: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 64: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 65: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 66: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 67: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 68: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 69: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 10); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 10) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 70: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 5) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 71: \ - tmp = fieldname(insn, 21, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 72: \ - tmp = fieldname(insn, 25, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 73: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeCRRC0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 74: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeCRRC0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 75: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 76: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 77: \ - tmp = fieldname(insn, 12, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 78: \ - tmp = fieldname(insn, 12, 8); \ - if (decodeCRBitMOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 79: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 8); \ - if (decodeCRBitMOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 80: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 81: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 82: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 83: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 84: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 85: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 86: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 87: \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 88: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 89: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 90: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RC_NOX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 91: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 92: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 93: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 94: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 95: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 96: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 97: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 98: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 99: \ - tmp = fieldname(insn, 21, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 100: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 101: \ - tmp = fieldname(insn, 21, 2); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 102: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 103: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 104: \ - tmp = fieldname(insn, 21, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 105: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 106: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 107: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 108: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 109: \ - tmp = fieldname(insn, 21, 2); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 110: \ - tmp = fieldname(insn, 21, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 111: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 112: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 113: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 114: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 115: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 116: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 117: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 118: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 119: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 21); \ - if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 120: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 21); \ - if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 121: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 21); \ - if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 122: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 2, 19); \ - if (decodeMemRIXOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 123: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 2, 19); \ - if (decodeMemRIXOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 124: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 125: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 126: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 127: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 128: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 129: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 130: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 131: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 132: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 133: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 134: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 135: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 136: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 8, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 137: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 138: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 139: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 140: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 8); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 141: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 142: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 143: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 144: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 145: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 146: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 147: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 148: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 149: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 150: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 7); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 151: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 152: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 153: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 6; \ - tmp |= fieldname(insn, 6, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 154: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 155: \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 16, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 1, 1) << 5; \ - tmp |= fieldname(insn, 11, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 1) << 5; \ - tmp |= fieldname(insn, 6, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 156: \ - tmp = 0; \ - tmp |= fieldname(insn, 3, 1) << 5; \ - tmp |= fieldname(insn, 21, 5) << 0; \ - if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 4, 17); \ - if (decodeMemRIX16Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 157: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 158: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 159: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 160: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 161: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 162: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 7); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 163: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 164: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 165: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 166: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 9, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 167: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 168: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 169: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 170: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 171: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 172: \ - tmp = fieldname(insn, 17, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 25, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 16, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 173: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 174: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 175: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 176: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 177: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 178: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 179: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 7, 4); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 180: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 9, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 181: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 9, 2); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 182: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 9, 12); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 183: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 184: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 185: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 186: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 187: \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 188: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 189: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 190: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 191: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 192: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 193: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 194: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 195: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 6, 5); \ - if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 196: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 197: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 198: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 199: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 200: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 201: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 202: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 0, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 203: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 204: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 205: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 206: \ - tmp = fieldname(insn, 23, 3); \ - if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 207: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 208: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 209: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 210: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 211: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 212: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 213: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 214: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 16, 5); \ - if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 5); \ - if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 215: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 10); \ - if (decodeSPE8Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 216: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 10); \ - if (decodeSPE2Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - case 217: \ - tmp = fieldname(insn, 21, 5); \ - if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - tmp = fieldname(insn, 11, 10); \ - if (decodeSPE4Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ - return S; \ - } \ -} + uint64_t Address, bool *Decoder) {\ + InsnType tmp;\ + switch (Idx) {\ + default: llvm_unreachable("Invalid index!");\ + case 0:\ + return S;\ + case 1:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 2:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 3:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 4:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 5:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 9, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 6:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 7:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 8:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 9, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 9:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 10:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 11:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 12:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 15, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 11, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 13:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 14:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 15:\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 16:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 17:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 18:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 19:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 20:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 21:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 3);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 22:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 23:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 24:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 25:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 26:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 27:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 28:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 0;\ + tmp |= fieldname(insn, 6, 10) << 6;\ + tmp |= fieldname(insn, 16, 5) << 1;\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 29:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 3);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 30:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 31:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 32:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 33:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 34:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 35:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 36:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 21, 1) << 4;\ + tmp |= fieldname(insn, 22, 4) << 0;\ + if (DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 4, 17);\ + if (decodeMemRIX16Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 37:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 38:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 39:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 40:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 41:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 42:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 43:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 44:\ + tmp = fieldname(insn, 2, 14);\ + if (decodeCondBrTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 45:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 2, 14);\ + if (decodeCondBrTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 46:\ + tmp = fieldname(insn, 2, 14);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 47:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 2, 14);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 48:\ + tmp = fieldname(insn, 5, 7);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 49:\ + tmp = fieldname(insn, 2, 24);\ + if (decodeDirectBrTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 50:\ + tmp = fieldname(insn, 2, 24);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 51:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 18, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 52:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 53:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 0;\ + tmp |= fieldname(insn, 6, 10) << 6;\ + tmp |= fieldname(insn, 16, 5) << 1;\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 54:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 55:\ + tmp = fieldname(insn, 11, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 56:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 1, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 57:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 1, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 58:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 1, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 59:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 16);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 60:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 5, 1) << 5;\ + tmp |= fieldname(insn, 6, 5) << 0;\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 61:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 5, 1) << 5;\ + tmp |= fieldname(insn, 6, 5) << 0;\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 62:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 5, 1) << 5;\ + tmp |= fieldname(insn, 6, 5) << 0;\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 63:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 64:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 65:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 18, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 66:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 67:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 68:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 69:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 70:\ + tmp = fieldname(insn, 15, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 71:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 11, 5) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 72:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 73:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 74:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 75:\ + tmp = fieldname(insn, 21, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 76:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 77:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 78:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 79:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 80:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 81:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 82:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 83:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 9, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 84:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 85:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 86:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 87:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 21, 1) << 4;\ + tmp |= fieldname(insn, 22, 4) << 0;\ + if (DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 88:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 89:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 10);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 10) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 90:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 11, 5) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 91:\ + tmp = fieldname(insn, 21, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 92:\ + tmp = fieldname(insn, 25, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 93:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 94:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 95:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 96:\ + tmp = fieldname(insn, 12, 8);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 97:\ + tmp = fieldname(insn, 12, 8);\ + if (decodeCRBitMOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 98:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 99:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 100:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 12, 8);\ + if (decodeCRBitMOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 101:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 102:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 103:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 104:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 105:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 106:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 107:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 108:\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 109:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 110:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 111:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RC_NOX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 112:\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 6;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (decodeMemRIHashOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 113:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 114:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 115:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 116:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 117:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 118:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 119:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 120:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 121:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 122:\ + tmp = fieldname(insn, 21, 5);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 123:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 124:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 125:\ + tmp = fieldname(insn, 21, 2);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 126:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 127:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 128:\ + tmp = fieldname(insn, 21, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 129:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 130:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 131:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 132:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 133:\ + tmp = fieldname(insn, 21, 2);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 134:\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 135:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 136:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 137:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 138:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 139:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 140:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 141:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 142:\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 143:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 21);\ + if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 144:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 21);\ + if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 145:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 21);\ + if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 146:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 4, 17);\ + if (decodeMemRIX16Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 147:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 2, 19);\ + if (decodeMemRIXOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 148:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 2, 19);\ + if (decodeMemRIXOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 149:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 150:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (decodeVSRpEvenOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 151:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 152:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (decodeVSRpEvenOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 153:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 154:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 155:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 156:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 157:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 158:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 159:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 160:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 161:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 162:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 163:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 164:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 165:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 8, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 166:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 167:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 168:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 169:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 8);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 170:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 171:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 172:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 173:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 174:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 175:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 176:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 177:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 178:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 179:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 7);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 180:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 181:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 182:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 6, 1) << 6;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 183:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 184:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 185:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 3, 1) << 5;\ + tmp |= fieldname(insn, 6, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 186:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 3, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 4, 17);\ + if (decodeMemRIX16Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 187:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8pRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 2, 19);\ + if (decodeMemRIXOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 188:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 189:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 190:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 191:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 192:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 7);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 193:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 194:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 195:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 196:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 9, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 197:\ + tmp = fieldname(insn, 23, 3);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 12, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 16, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 198:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 199:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 200:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 3);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 201:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 202:\ + tmp = fieldname(insn, 17, 8);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 25, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 16, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 203:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 204:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 205:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 206:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 6, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 207:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 34) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 208:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 34) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 209:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (decodeImmZeroOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 34) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 210:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 16, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 16, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 17, 1);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 32, 16) << 16;\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 211:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 16, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 32, 16) << 16;\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 212:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 213:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34PCRelOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 214:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 3, 1) << 5;\ + tmp |= fieldname(insn, 6, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 32, 3);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 215:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 1) << 5;\ + tmp |= fieldname(insn, 21, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 3, 1) << 5;\ + tmp |= fieldname(insn, 6, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 32, 8);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 216:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 217:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34PCRelOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 218:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 219:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34PCRelOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 220:\ + tmp = fieldname(insn, 21, 6);\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 221:\ + tmp = fieldname(insn, 21, 6);\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34PCRelOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 222:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 223:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34PCRelOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 224:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 225:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34PCRelOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 226:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 21, 1) << 4;\ + tmp |= fieldname(insn, 22, 4) << 0;\ + if (DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 227:\ + tmp = 0x0;\ + tmp |= fieldname(insn, 21, 1) << 4;\ + tmp |= fieldname(insn, 22, 4) << 0;\ + if (DecodeVSRpRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 0, 16) << 0;\ + tmp |= fieldname(insn, 16, 5) << 34;\ + tmp |= fieldname(insn, 32, 18) << 16;\ + if (decodeMemRI34PCRelOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 228:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 32, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 44, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 229:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 32, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 44, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 230:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 32, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 46, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 231:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 32, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 46, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 232:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 32, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 233:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 32, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 234:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 32, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 40, 8);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 235:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 32, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 40, 8);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 236:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (decodeVSRpEvenOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 34, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 237:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeACCRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 2, 1) << 5;\ + tmp |= fieldname(insn, 16, 5) << 0;\ + if (decodeVSRpEvenOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = 0x0;\ + tmp |= fieldname(insn, 1, 1) << 5;\ + tmp |= fieldname(insn, 11, 5) << 0;\ + if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 36, 4);\ + MCOperand_CreateImm0(MI, tmp);\ + tmp = fieldname(insn, 34, 2);\ + MCOperand_CreateImm0(MI, tmp);\ + return S;\ + case 238:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 239:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 240:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 241:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 242:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 243:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 244:\ + tmp = fieldname(insn, 23, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 245:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 0, 3);\ + if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 246:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 247:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 248:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 249:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 16, 5);\ + if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 5);\ + if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 250:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 10);\ + if (decodeSPE8Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 251:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 10);\ + if (decodeSPE2Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + case 252:\ + tmp = fieldname(insn, 21, 5);\ + if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + tmp = fieldname(insn, 11, 10);\ + if (decodeSPE4Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; }\ + return S;\ + }\ +}\ #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address) \ + InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ { \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ @@ -6618,8 +8177,9 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Check the predicate. */ \ - if (!(Pred = checkDecoderPredicate(PIdx, MI))) \ + if (!(Pred = checkDecoderPredicate(PIdx, feature))) \ Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ (void)Pred; \ break; \ } \ @@ -6680,9 +8240,24080 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ } +FieldFromInstruction(fieldFromInstruction, uint32_t) +DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) +DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) + +#endif // MIPS_GET_DISASSEMBLER +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +#define PPC_BP 1 +#define PPC_CARRY 2 +#define PPC_CTR 3 +#define PPC_FP 4 +#define PPC_LR 5 +#define PPC_RM 6 +#define PPC_SPEFSCR 7 +#define PPC_VRSAVE 8 +#define PPC_XER 9 +#define PPC_ZERO 10 +#define PPC_ACC0 11 +#define PPC_ACC1 12 +#define PPC_ACC2 13 +#define PPC_ACC3 14 +#define PPC_ACC4 15 +#define PPC_ACC5 16 +#define PPC_ACC6 17 +#define PPC_ACC7 18 +#define PPC_BP8 19 +#define PPC_CR0 20 +#define PPC_CR1 21 +#define PPC_CR2 22 +#define PPC_CR3 23 +#define PPC_CR4 24 +#define PPC_CR5 25 +#define PPC_CR6 26 +#define PPC_CR7 27 +#define PPC_CTR8 28 +#define PPC_F0 29 +#define PPC_F1 30 +#define PPC_F2 31 +#define PPC_F3 32 +#define PPC_F4 33 +#define PPC_F5 34 +#define PPC_F6 35 +#define PPC_F7 36 +#define PPC_F8 37 +#define PPC_F9 38 +#define PPC_F10 39 +#define PPC_F11 40 +#define PPC_F12 41 +#define PPC_F13 42 +#define PPC_F14 43 +#define PPC_F15 44 +#define PPC_F16 45 +#define PPC_F17 46 +#define PPC_F18 47 +#define PPC_F19 48 +#define PPC_F20 49 +#define PPC_F21 50 +#define PPC_F22 51 +#define PPC_F23 52 +#define PPC_F24 53 +#define PPC_F25 54 +#define PPC_F26 55 +#define PPC_F27 56 +#define PPC_F28 57 +#define PPC_F29 58 +#define PPC_F30 59 +#define PPC_F31 60 +#define PPC_FP8 61 +#define PPC_LR8 62 +#define PPC_R0 63 +#define PPC_R1 64 +#define PPC_R2 65 +#define PPC_R3 66 +#define PPC_R4 67 +#define PPC_R5 68 +#define PPC_R6 69 +#define PPC_R7 70 +#define PPC_R8 71 +#define PPC_R9 72 +#define PPC_R10 73 +#define PPC_R11 74 +#define PPC_R12 75 +#define PPC_R13 76 +#define PPC_R14 77 +#define PPC_R15 78 +#define PPC_R16 79 +#define PPC_R17 80 +#define PPC_R18 81 +#define PPC_R19 82 +#define PPC_R20 83 +#define PPC_R21 84 +#define PPC_R22 85 +#define PPC_R23 86 +#define PPC_R24 87 +#define PPC_R25 88 +#define PPC_R26 89 +#define PPC_R27 90 +#define PPC_R28 91 +#define PPC_R29 92 +#define PPC_R30 93 +#define PPC_R31 94 +#define PPC_S0 95 +#define PPC_S1 96 +#define PPC_S2 97 +#define PPC_S3 98 +#define PPC_S4 99 +#define PPC_S5 100 +#define PPC_S6 101 +#define PPC_S7 102 +#define PPC_S8 103 +#define PPC_S9 104 +#define PPC_S10 105 +#define PPC_S11 106 +#define PPC_S12 107 +#define PPC_S13 108 +#define PPC_S14 109 +#define PPC_S15 110 +#define PPC_S16 111 +#define PPC_S17 112 +#define PPC_S18 113 +#define PPC_S19 114 +#define PPC_S20 115 +#define PPC_S21 116 +#define PPC_S22 117 +#define PPC_S23 118 +#define PPC_S24 119 +#define PPC_S25 120 +#define PPC_S26 121 +#define PPC_S27 122 +#define PPC_S28 123 +#define PPC_S29 124 +#define PPC_S30 125 +#define PPC_S31 126 +#define PPC_UACC0 127 +#define PPC_UACC1 128 +#define PPC_UACC2 129 +#define PPC_UACC3 130 +#define PPC_UACC4 131 +#define PPC_UACC5 132 +#define PPC_UACC6 133 +#define PPC_UACC7 134 +#define PPC_V0 135 +#define PPC_V1 136 +#define PPC_V2 137 +#define PPC_V3 138 +#define PPC_V4 139 +#define PPC_V5 140 +#define PPC_V6 141 +#define PPC_V7 142 +#define PPC_V8 143 +#define PPC_V9 144 +#define PPC_V10 145 +#define PPC_V11 146 +#define PPC_V12 147 +#define PPC_V13 148 +#define PPC_V14 149 +#define PPC_V15 150 +#define PPC_V16 151 +#define PPC_V17 152 +#define PPC_V18 153 +#define PPC_V19 154 +#define PPC_V20 155 +#define PPC_V21 156 +#define PPC_V22 157 +#define PPC_V23 158 +#define PPC_V24 159 +#define PPC_V25 160 +#define PPC_V26 161 +#define PPC_V27 162 +#define PPC_V28 163 +#define PPC_V29 164 +#define PPC_V30 165 +#define PPC_V31 166 +#define PPC_VF0 167 +#define PPC_VF1 168 +#define PPC_VF2 169 +#define PPC_VF3 170 +#define PPC_VF4 171 +#define PPC_VF5 172 +#define PPC_VF6 173 +#define PPC_VF7 174 +#define PPC_VF8 175 +#define PPC_VF9 176 +#define PPC_VF10 177 +#define PPC_VF11 178 +#define PPC_VF12 179 +#define PPC_VF13 180 +#define PPC_VF14 181 +#define PPC_VF15 182 +#define PPC_VF16 183 +#define PPC_VF17 184 +#define PPC_VF18 185 +#define PPC_VF19 186 +#define PPC_VF20 187 +#define PPC_VF21 188 +#define PPC_VF22 189 +#define PPC_VF23 190 +#define PPC_VF24 191 +#define PPC_VF25 192 +#define PPC_VF26 193 +#define PPC_VF27 194 +#define PPC_VF28 195 +#define PPC_VF29 196 +#define PPC_VF30 197 +#define PPC_VF31 198 +#define PPC_VSL0 199 +#define PPC_VSL1 200 +#define PPC_VSL2 201 +#define PPC_VSL3 202 +#define PPC_VSL4 203 +#define PPC_VSL5 204 +#define PPC_VSL6 205 +#define PPC_VSL7 206 +#define PPC_VSL8 207 +#define PPC_VSL9 208 +#define PPC_VSL10 209 +#define PPC_VSL11 210 +#define PPC_VSL12 211 +#define PPC_VSL13 212 +#define PPC_VSL14 213 +#define PPC_VSL15 214 +#define PPC_VSL16 215 +#define PPC_VSL17 216 +#define PPC_VSL18 217 +#define PPC_VSL19 218 +#define PPC_VSL20 219 +#define PPC_VSL21 220 +#define PPC_VSL22 221 +#define PPC_VSL23 222 +#define PPC_VSL24 223 +#define PPC_VSL25 224 +#define PPC_VSL26 225 +#define PPC_VSL27 226 +#define PPC_VSL28 227 +#define PPC_VSL29 228 +#define PPC_VSL30 229 +#define PPC_VSL31 230 +#define PPC_VSRp0 231 +#define PPC_VSRp1 232 +#define PPC_VSRp2 233 +#define PPC_VSRp3 234 +#define PPC_VSRp4 235 +#define PPC_VSRp5 236 +#define PPC_VSRp6 237 +#define PPC_VSRp7 238 +#define PPC_VSRp8 239 +#define PPC_VSRp9 240 +#define PPC_VSRp10 241 +#define PPC_VSRp11 242 +#define PPC_VSRp12 243 +#define PPC_VSRp13 244 +#define PPC_VSRp14 245 +#define PPC_VSRp15 246 +#define PPC_VSRp16 247 +#define PPC_VSRp17 248 +#define PPC_VSRp18 249 +#define PPC_VSRp19 250 +#define PPC_VSRp20 251 +#define PPC_VSRp21 252 +#define PPC_VSRp22 253 +#define PPC_VSRp23 254 +#define PPC_VSRp24 255 +#define PPC_VSRp25 256 +#define PPC_VSRp26 257 +#define PPC_VSRp27 258 +#define PPC_VSRp28 259 +#define PPC_VSRp29 260 +#define PPC_VSRp30 261 +#define PPC_VSRp31 262 +#define PPC_VSX32 263 +#define PPC_VSX33 264 +#define PPC_VSX34 265 +#define PPC_VSX35 266 +#define PPC_VSX36 267 +#define PPC_VSX37 268 +#define PPC_VSX38 269 +#define PPC_VSX39 270 +#define PPC_VSX40 271 +#define PPC_VSX41 272 +#define PPC_VSX42 273 +#define PPC_VSX43 274 +#define PPC_VSX44 275 +#define PPC_VSX45 276 +#define PPC_VSX46 277 +#define PPC_VSX47 278 +#define PPC_VSX48 279 +#define PPC_VSX49 280 +#define PPC_VSX50 281 +#define PPC_VSX51 282 +#define PPC_VSX52 283 +#define PPC_VSX53 284 +#define PPC_VSX54 285 +#define PPC_VSX55 286 +#define PPC_VSX56 287 +#define PPC_VSX57 288 +#define PPC_VSX58 289 +#define PPC_VSX59 290 +#define PPC_VSX60 291 +#define PPC_VSX61 292 +#define PPC_VSX62 293 +#define PPC_VSX63 294 +#define PPC_X0 295 +#define PPC_X1 296 +#define PPC_X2 297 +#define PPC_X3 298 +#define PPC_X4 299 +#define PPC_X5 300 +#define PPC_X6 301 +#define PPC_X7 302 +#define PPC_X8 303 +#define PPC_X9 304 +#define PPC_X10 305 +#define PPC_X11 306 +#define PPC_X12 307 +#define PPC_X13 308 +#define PPC_X14 309 +#define PPC_X15 310 +#define PPC_X16 311 +#define PPC_X17 312 +#define PPC_X18 313 +#define PPC_X19 314 +#define PPC_X20 315 +#define PPC_X21 316 +#define PPC_X22 317 +#define PPC_X23 318 +#define PPC_X24 319 +#define PPC_X25 320 +#define PPC_X26 321 +#define PPC_X27 322 +#define PPC_X28 323 +#define PPC_X29 324 +#define PPC_X30 325 +#define PPC_X31 326 +#define PPC_ZERO8 327 +#define PPC_CR0EQ 328 +#define PPC_CR1EQ 329 +#define PPC_CR2EQ 330 +#define PPC_CR3EQ 331 +#define PPC_CR4EQ 332 +#define PPC_CR5EQ 333 +#define PPC_CR6EQ 334 +#define PPC_CR7EQ 335 +#define PPC_CR0GT 336 +#define PPC_CR1GT 337 +#define PPC_CR2GT 338 +#define PPC_CR3GT 339 +#define PPC_CR4GT 340 +#define PPC_CR5GT 341 +#define PPC_CR6GT 342 +#define PPC_CR7GT 343 +#define PPC_CR0LT 344 +#define PPC_CR1LT 345 +#define PPC_CR2LT 346 +#define PPC_CR3LT 347 +#define PPC_CR4LT 348 +#define PPC_CR5LT 349 +#define PPC_CR6LT 350 +#define PPC_CR7LT 351 +#define PPC_CR0UN 352 +#define PPC_CR1UN 353 +#define PPC_CR2UN 354 +#define PPC_CR3UN 355 +#define PPC_CR4UN 356 +#define PPC_CR5UN 357 +#define PPC_CR6UN 358 +#define PPC_CR7UN 359 +#define PPC_G8p0 360 +#define PPC_G8p1 361 +#define PPC_G8p2 362 +#define PPC_G8p3 363 +#define PPC_G8p4 364 +#define PPC_G8p5 365 +#define PPC_G8p6 366 +#define PPC_G8p7 367 +#define PPC_G8p8 368 +#define PPC_G8p9 369 +#define PPC_G8p10 370 +#define PPC_G8p11 371 +#define PPC_G8p12 372 +#define PPC_G8p13 373 +#define PPC_G8p14 374 +#define PPC_G8p15 375 +#define PPC_NUM_TARGET_REGS 376 + + +// Register classes + +#define PPC_VSSRCRegClassID 0 +#define PPC_GPRCRegClassID 1 +#define PPC_GPRC_NOR0RegClassID 2 +#define PPC_GPRC_and_GPRC_NOR0RegClassID 3 +#define PPC_CRBITRCRegClassID 4 +#define PPC_F4RCRegClassID 5 +#define PPC_CRRCRegClassID 6 +#define PPC_CARRYRCRegClassID 7 +#define PPC_CTRRCRegClassID 8 +#define PPC_LRRCRegClassID 9 +#define PPC_VRSAVERCRegClassID 10 +#define PPC_SPILLTOVSRRCRegClassID 11 +#define PPC_VSFRCRegClassID 12 +#define PPC_G8RCRegClassID 13 +#define PPC_G8RC_NOX0RegClassID 14 +#define PPC_SPILLTOVSRRC_and_VSFRCRegClassID 15 +#define PPC_G8RC_and_G8RC_NOX0RegClassID 16 +#define PPC_F8RCRegClassID 17 +#define PPC_SPERCRegClassID 18 +#define PPC_VFRCRegClassID 19 +#define PPC_SPERC_with_sub_32_in_GPRC_NOR0RegClassID 20 +#define PPC_SPILLTOVSRRC_and_VFRCRegClassID 21 +#define PPC_SPILLTOVSRRC_and_F4RCRegClassID 22 +#define PPC_CTRRC8RegClassID 23 +#define PPC_LR8RCRegClassID 24 +#define PPC_VSRCRegClassID 25 +#define PPC_VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID 26 +#define PPC_VRRCRegClassID 27 +#define PPC_VSLRCRegClassID 28 +#define PPC_VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID 29 +#define PPC_G8pRCRegClassID 30 +#define PPC_G8pRC_with_sub_32_in_GPRC_NOR0RegClassID 31 +#define PPC_VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID 32 +#define PPC_VSRpRCRegClassID 33 +#define PPC_VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID 34 +#define PPC_VSRpRC_with_sub_64_in_F4RCRegClassID 35 +#define PPC_VSRpRC_with_sub_64_in_VFRCRegClassID 36 +#define PPC_VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID 37 +#define PPC_VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID 38 +#define PPC_ACCRCRegClassID 39 +#define PPC_UACCRCRegClassID 40 +#define PPC_ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID 41 +#define PPC_UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID 42 +#define PPC_ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID 43 +#define PPC_UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID 44 + +#endif // GET_REGINFO_ENUM + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +#define PPC_PHI 0 +#define PPC_INLINEASM 1 +#define PPC_INLINEASM_BR 2 +#define PPC_CFI_INSTRUCTION 3 +#define PPC_EH_LABEL 4 +#define PPC_GC_LABEL 5 +#define PPC_ANNOTATION_LABEL 6 +#define PPC_KILL 7 +#define PPC_EXTRACT_SUBREG 8 +#define PPC_INSERT_SUBREG 9 +#define PPC_IMPLICIT_DEF 10 +#define PPC_SUBREG_TO_REG 11 +#define PPC_COPY_TO_REGCLASS 12 +#define PPC_DBG_VALUE 13 +#define PPC_DBG_VALUE_LIST 14 +#define PPC_DBG_INSTR_REF 15 +#define PPC_DBG_PHI 16 +#define PPC_DBG_LABEL 17 +#define PPC_REG_SEQUENCE 18 +#define PPC_COPY 19 +#define PPC_BUNDLE 20 +#define PPC_LIFETIME_START 21 +#define PPC_LIFETIME_END 22 +#define PPC_PSEUDO_PROBE 23 +#define PPC_ARITH_FENCE 24 +#define PPC_STACKMAP 25 +#define PPC_FENTRY_CALL 26 +#define PPC_PATCHPOINT 27 +#define PPC_LOAD_STACK_GUARD 28 +#define PPC_PREALLOCATED_SETUP 29 +#define PPC_PREALLOCATED_ARG 30 +#define PPC_STATEPOINT 31 +#define PPC_LOCAL_ESCAPE 32 +#define PPC_FAULTING_OP 33 +#define PPC_PATCHABLE_OP 34 +#define PPC_PATCHABLE_FUNCTION_ENTER 35 +#define PPC_PATCHABLE_RET 36 +#define PPC_PATCHABLE_FUNCTION_EXIT 37 +#define PPC_PATCHABLE_TAIL_CALL 38 +#define PPC_PATCHABLE_EVENT_CALL 39 +#define PPC_PATCHABLE_TYPED_EVENT_CALL 40 +#define PPC_ICALL_BRANCH_FUNNEL 41 +#define PPC_G_ASSERT_SEXT 42 +#define PPC_G_ASSERT_ZEXT 43 +#define PPC_G_ADD 44 +#define PPC_G_SUB 45 +#define PPC_G_MUL 46 +#define PPC_G_SDIV 47 +#define PPC_G_UDIV 48 +#define PPC_G_SREM 49 +#define PPC_G_UREM 50 +#define PPC_G_SDIVREM 51 +#define PPC_G_UDIVREM 52 +#define PPC_G_AND 53 +#define PPC_G_OR 54 +#define PPC_G_XOR 55 +#define PPC_G_IMPLICIT_DEF 56 +#define PPC_G_PHI 57 +#define PPC_G_FRAME_INDEX 58 +#define PPC_G_GLOBAL_VALUE 59 +#define PPC_G_EXTRACT 60 +#define PPC_G_UNMERGE_VALUES 61 +#define PPC_G_INSERT 62 +#define PPC_G_MERGE_VALUES 63 +#define PPC_G_BUILD_VECTOR 64 +#define PPC_G_BUILD_VECTOR_TRUNC 65 +#define PPC_G_CONCAT_VECTORS 66 +#define PPC_G_PTRTOINT 67 +#define PPC_G_INTTOPTR 68 +#define PPC_G_BITCAST 69 +#define PPC_G_FREEZE 70 +#define PPC_G_INTRINSIC_TRUNC 71 +#define PPC_G_INTRINSIC_ROUND 72 +#define PPC_G_INTRINSIC_LRINT 73 +#define PPC_G_INTRINSIC_ROUNDEVEN 74 +#define PPC_G_READCYCLECOUNTER 75 +#define PPC_G_LOAD 76 +#define PPC_G_SEXTLOAD 77 +#define PPC_G_ZEXTLOAD 78 +#define PPC_G_INDEXED_LOAD 79 +#define PPC_G_INDEXED_SEXTLOAD 80 +#define PPC_G_INDEXED_ZEXTLOAD 81 +#define PPC_G_STORE 82 +#define PPC_G_INDEXED_STORE 83 +#define PPC_G_ATOMIC_CMPXCHG_WITH_SUCCESS 84 +#define PPC_G_ATOMIC_CMPXCHG 85 +#define PPC_G_ATOMICRMW_XCHG 86 +#define PPC_G_ATOMICRMW_ADD 87 +#define PPC_G_ATOMICRMW_SUB 88 +#define PPC_G_ATOMICRMW_AND 89 +#define PPC_G_ATOMICRMW_NAND 90 +#define PPC_G_ATOMICRMW_OR 91 +#define PPC_G_ATOMICRMW_XOR 92 +#define PPC_G_ATOMICRMW_MAX 93 +#define PPC_G_ATOMICRMW_MIN 94 +#define PPC_G_ATOMICRMW_UMAX 95 +#define PPC_G_ATOMICRMW_UMIN 96 +#define PPC_G_ATOMICRMW_FADD 97 +#define PPC_G_ATOMICRMW_FSUB 98 +#define PPC_G_FENCE 99 +#define PPC_G_BRCOND 100 +#define PPC_G_BRINDIRECT 101 +#define PPC_G_INTRINSIC 102 +#define PPC_G_INTRINSIC_W_SIDE_EFFECTS 103 +#define PPC_G_ANYEXT 104 +#define PPC_G_TRUNC 105 +#define PPC_G_CONSTANT 106 +#define PPC_G_FCONSTANT 107 +#define PPC_G_VASTART 108 +#define PPC_G_VAARG 109 +#define PPC_G_SEXT 110 +#define PPC_G_SEXT_INREG 111 +#define PPC_G_ZEXT 112 +#define PPC_G_SHL 113 +#define PPC_G_LSHR 114 +#define PPC_G_ASHR 115 +#define PPC_G_FSHL 116 +#define PPC_G_FSHR 117 +#define PPC_G_ROTR 118 +#define PPC_G_ROTL 119 +#define PPC_G_ICMP 120 +#define PPC_G_FCMP 121 +#define PPC_G_SELECT 122 +#define PPC_G_UADDO 123 +#define PPC_G_UADDE 124 +#define PPC_G_USUBO 125 +#define PPC_G_USUBE 126 +#define PPC_G_SADDO 127 +#define PPC_G_SADDE 128 +#define PPC_G_SSUBO 129 +#define PPC_G_SSUBE 130 +#define PPC_G_UMULO 131 +#define PPC_G_SMULO 132 +#define PPC_G_UMULH 133 +#define PPC_G_SMULH 134 +#define PPC_G_UADDSAT 135 +#define PPC_G_SADDSAT 136 +#define PPC_G_USUBSAT 137 +#define PPC_G_SSUBSAT 138 +#define PPC_G_USHLSAT 139 +#define PPC_G_SSHLSAT 140 +#define PPC_G_SMULFIX 141 +#define PPC_G_UMULFIX 142 +#define PPC_G_SMULFIXSAT 143 +#define PPC_G_UMULFIXSAT 144 +#define PPC_G_SDIVFIX 145 +#define PPC_G_UDIVFIX 146 +#define PPC_G_SDIVFIXSAT 147 +#define PPC_G_UDIVFIXSAT 148 +#define PPC_G_FADD 149 +#define PPC_G_FSUB 150 +#define PPC_G_FMUL 151 +#define PPC_G_FMA 152 +#define PPC_G_FMAD 153 +#define PPC_G_FDIV 154 +#define PPC_G_FREM 155 +#define PPC_G_FPOW 156 +#define PPC_G_FPOWI 157 +#define PPC_G_FEXP 158 +#define PPC_G_FEXP2 159 +#define PPC_G_FLOG 160 +#define PPC_G_FLOG2 161 +#define PPC_G_FLOG10 162 +#define PPC_G_FNEG 163 +#define PPC_G_FPEXT 164 +#define PPC_G_FPTRUNC 165 +#define PPC_G_FPTOSI 166 +#define PPC_G_FPTOUI 167 +#define PPC_G_SITOFP 168 +#define PPC_G_UITOFP 169 +#define PPC_G_FABS 170 +#define PPC_G_FCOPYSIGN 171 +#define PPC_G_FCANONICALIZE 172 +#define PPC_G_FMINNUM 173 +#define PPC_G_FMAXNUM 174 +#define PPC_G_FMINNUM_IEEE 175 +#define PPC_G_FMAXNUM_IEEE 176 +#define PPC_G_FMINIMUM 177 +#define PPC_G_FMAXIMUM 178 +#define PPC_G_PTR_ADD 179 +#define PPC_G_PTRMASK 180 +#define PPC_G_SMIN 181 +#define PPC_G_SMAX 182 +#define PPC_G_UMIN 183 +#define PPC_G_UMAX 184 +#define PPC_G_ABS 185 +#define PPC_G_LROUND 186 +#define PPC_G_LLROUND 187 +#define PPC_G_BR 188 +#define PPC_G_BRJT 189 +#define PPC_G_INSERT_VECTOR_ELT 190 +#define PPC_G_EXTRACT_VECTOR_ELT 191 +#define PPC_G_SHUFFLE_VECTOR 192 +#define PPC_G_CTTZ 193 +#define PPC_G_CTTZ_ZERO_UNDEF 194 +#define PPC_G_CTLZ 195 +#define PPC_G_CTLZ_ZERO_UNDEF 196 +#define PPC_G_CTPOP 197 +#define PPC_G_BSWAP 198 +#define PPC_G_BITREVERSE 199 +#define PPC_G_FCEIL 200 +#define PPC_G_FCOS 201 +#define PPC_G_FSIN 202 +#define PPC_G_FSQRT 203 +#define PPC_G_FFLOOR 204 +#define PPC_G_FRINT 205 +#define PPC_G_FNEARBYINT 206 +#define PPC_G_ADDRSPACE_CAST 207 +#define PPC_G_BLOCK_ADDR 208 +#define PPC_G_JUMP_TABLE 209 +#define PPC_G_DYN_STACKALLOC 210 +#define PPC_G_STRICT_FADD 211 +#define PPC_G_STRICT_FSUB 212 +#define PPC_G_STRICT_FMUL 213 +#define PPC_G_STRICT_FDIV 214 +#define PPC_G_STRICT_FREM 215 +#define PPC_G_STRICT_FMA 216 +#define PPC_G_STRICT_FSQRT 217 +#define PPC_G_READ_REGISTER 218 +#define PPC_G_WRITE_REGISTER 219 +#define PPC_G_MEMCPY 220 +#define PPC_G_MEMCPY_INLINE 221 +#define PPC_G_MEMMOVE 222 +#define PPC_G_MEMSET 223 +#define PPC_G_BZERO 224 +#define PPC_G_VECREDUCE_SEQ_FADD 225 +#define PPC_G_VECREDUCE_SEQ_FMUL 226 +#define PPC_G_VECREDUCE_FADD 227 +#define PPC_G_VECREDUCE_FMUL 228 +#define PPC_G_VECREDUCE_FMAX 229 +#define PPC_G_VECREDUCE_FMIN 230 +#define PPC_G_VECREDUCE_ADD 231 +#define PPC_G_VECREDUCE_MUL 232 +#define PPC_G_VECREDUCE_AND 233 +#define PPC_G_VECREDUCE_OR 234 +#define PPC_G_VECREDUCE_XOR 235 +#define PPC_G_VECREDUCE_SMAX 236 +#define PPC_G_VECREDUCE_SMIN 237 +#define PPC_G_VECREDUCE_UMAX 238 +#define PPC_G_VECREDUCE_UMIN 239 +#define PPC_G_SBFX 240 +#define PPC_G_UBFX 241 +#define PPC_ATOMIC_CMP_SWAP_I128 242 +#define PPC_ATOMIC_LOAD_ADD_I128 243 +#define PPC_ATOMIC_LOAD_AND_I128 244 +#define PPC_ATOMIC_LOAD_NAND_I128 245 +#define PPC_ATOMIC_LOAD_OR_I128 246 +#define PPC_ATOMIC_LOAD_SUB_I128 247 +#define PPC_ATOMIC_LOAD_XOR_I128 248 +#define PPC_ATOMIC_SWAP_I128 249 +#define PPC_BUILD_QUADWORD 250 +#define PPC_BUILD_UACC 251 +#define PPC_CFENCE8 252 +#define PPC_CLRLSLDI 253 +#define PPC_CLRLSLDI_rec 254 +#define PPC_CLRLSLWI 255 +#define PPC_CLRLSLWI_rec 256 +#define PPC_CLRRDI 257 +#define PPC_CLRRDI_rec 258 +#define PPC_CLRRWI 259 +#define PPC_CLRRWI_rec 260 +#define PPC_DCBFL 261 +#define PPC_DCBFLP 262 +#define PPC_DCBFPS 263 +#define PPC_DCBFx 264 +#define PPC_DCBSTPS 265 +#define PPC_DCBTCT 266 +#define PPC_DCBTDS 267 +#define PPC_DCBTSTCT 268 +#define PPC_DCBTSTDS 269 +#define PPC_DCBTSTT 270 +#define PPC_DCBTSTx 271 +#define PPC_DCBTT 272 +#define PPC_DCBTx 273 +#define PPC_DFLOADf32 274 +#define PPC_DFLOADf64 275 +#define PPC_DFSTOREf32 276 +#define PPC_DFSTOREf64 277 +#define PPC_EXTLDI 278 +#define PPC_EXTLDI_rec 279 +#define PPC_EXTLWI 280 +#define PPC_EXTLWI_rec 281 +#define PPC_EXTRDI 282 +#define PPC_EXTRDI_rec 283 +#define PPC_EXTRWI 284 +#define PPC_EXTRWI_rec 285 +#define PPC_INSLWI 286 +#define PPC_INSLWI_rec 287 +#define PPC_INSRDI 288 +#define PPC_INSRDI_rec 289 +#define PPC_INSRWI 290 +#define PPC_INSRWI_rec 291 +#define PPC_KILL_PAIR 292 +#define PPC_LAx 293 +#define PPC_LIWAX 294 +#define PPC_LIWZX 295 +#define PPC_RLWIMIbm 296 +#define PPC_RLWIMIbm_rec 297 +#define PPC_RLWINMbm 298 +#define PPC_RLWINMbm_rec 299 +#define PPC_RLWNMbm 300 +#define PPC_RLWNMbm_rec 301 +#define PPC_ROTRDI 302 +#define PPC_ROTRDI_rec 303 +#define PPC_ROTRWI 304 +#define PPC_ROTRWI_rec 305 +#define PPC_SLDI 306 +#define PPC_SLDI_rec 307 +#define PPC_SLWI 308 +#define PPC_SLWI_rec 309 +#define PPC_SPILLTOVSR_LD 310 +#define PPC_SPILLTOVSR_LDX 311 +#define PPC_SPILLTOVSR_ST 312 +#define PPC_SPILLTOVSR_STX 313 +#define PPC_SRDI 314 +#define PPC_SRDI_rec 315 +#define PPC_SRWI 316 +#define PPC_SRWI_rec 317 +#define PPC_STIWX 318 +#define PPC_SUBI 319 +#define PPC_SUBIC 320 +#define PPC_SUBIC_rec 321 +#define PPC_SUBIS 322 +#define PPC_SUBPCIS 323 +#define PPC_XFLOADf32 324 +#define PPC_XFLOADf64 325 +#define PPC_XFSTOREf32 326 +#define PPC_XFSTOREf64 327 +#define PPC_ADD4 328 +#define PPC_ADD4O 329 +#define PPC_ADD4O_rec 330 +#define PPC_ADD4TLS 331 +#define PPC_ADD4_rec 332 +#define PPC_ADD8 333 +#define PPC_ADD8O 334 +#define PPC_ADD8O_rec 335 +#define PPC_ADD8TLS 336 +#define PPC_ADD8TLS_ 337 +#define PPC_ADD8_rec 338 +#define PPC_ADDC 339 +#define PPC_ADDC8 340 +#define PPC_ADDC8O 341 +#define PPC_ADDC8O_rec 342 +#define PPC_ADDC8_rec 343 +#define PPC_ADDCO 344 +#define PPC_ADDCO_rec 345 +#define PPC_ADDC_rec 346 +#define PPC_ADDE 347 +#define PPC_ADDE8 348 +#define PPC_ADDE8O 349 +#define PPC_ADDE8O_rec 350 +#define PPC_ADDE8_rec 351 +#define PPC_ADDEO 352 +#define PPC_ADDEO_rec 353 +#define PPC_ADDEX 354 +#define PPC_ADDEX8 355 +#define PPC_ADDE_rec 356 +#define PPC_ADDI 357 +#define PPC_ADDI8 358 +#define PPC_ADDIC 359 +#define PPC_ADDIC8 360 +#define PPC_ADDIC_rec 361 +#define PPC_ADDIS 362 +#define PPC_ADDIS8 363 +#define PPC_ADDISdtprelHA 364 +#define PPC_ADDISdtprelHA32 365 +#define PPC_ADDISgotTprelHA 366 +#define PPC_ADDIStlsgdHA 367 +#define PPC_ADDIStlsldHA 368 +#define PPC_ADDIStocHA 369 +#define PPC_ADDIStocHA8 370 +#define PPC_ADDIdtprelL 371 +#define PPC_ADDIdtprelL32 372 +#define PPC_ADDItlsgdL 373 +#define PPC_ADDItlsgdL32 374 +#define PPC_ADDItlsgdLADDR 375 +#define PPC_ADDItlsgdLADDR32 376 +#define PPC_ADDItlsldL 377 +#define PPC_ADDItlsldL32 378 +#define PPC_ADDItlsldLADDR 379 +#define PPC_ADDItlsldLADDR32 380 +#define PPC_ADDItoc 381 +#define PPC_ADDItocL 382 +#define PPC_ADDME 383 +#define PPC_ADDME8 384 +#define PPC_ADDME8O 385 +#define PPC_ADDME8O_rec 386 +#define PPC_ADDME8_rec 387 +#define PPC_ADDMEO 388 +#define PPC_ADDMEO_rec 389 +#define PPC_ADDME_rec 390 +#define PPC_ADDPCIS 391 +#define PPC_ADDZE 392 +#define PPC_ADDZE8 393 +#define PPC_ADDZE8O 394 +#define PPC_ADDZE8O_rec 395 +#define PPC_ADDZE8_rec 396 +#define PPC_ADDZEO 397 +#define PPC_ADDZEO_rec 398 +#define PPC_ADDZE_rec 399 +#define PPC_ADJCALLSTACKDOWN 400 +#define PPC_ADJCALLSTACKUP 401 +#define PPC_AND 402 +#define PPC_AND8 403 +#define PPC_AND8_rec 404 +#define PPC_ANDC 405 +#define PPC_ANDC8 406 +#define PPC_ANDC8_rec 407 +#define PPC_ANDC_rec 408 +#define PPC_ANDI8_rec 409 +#define PPC_ANDIS8_rec 410 +#define PPC_ANDIS_rec 411 +#define PPC_ANDI_rec 412 +#define PPC_ANDI_rec_1_EQ_BIT 413 +#define PPC_ANDI_rec_1_EQ_BIT8 414 +#define PPC_ANDI_rec_1_GT_BIT 415 +#define PPC_ANDI_rec_1_GT_BIT8 416 +#define PPC_AND_rec 417 +#define PPC_ATOMIC_CMP_SWAP_I16 418 +#define PPC_ATOMIC_CMP_SWAP_I32 419 +#define PPC_ATOMIC_CMP_SWAP_I64 420 +#define PPC_ATOMIC_CMP_SWAP_I8 421 +#define PPC_ATOMIC_LOAD_ADD_I16 422 +#define PPC_ATOMIC_LOAD_ADD_I32 423 +#define PPC_ATOMIC_LOAD_ADD_I64 424 +#define PPC_ATOMIC_LOAD_ADD_I8 425 +#define PPC_ATOMIC_LOAD_AND_I16 426 +#define PPC_ATOMIC_LOAD_AND_I32 427 +#define PPC_ATOMIC_LOAD_AND_I64 428 +#define PPC_ATOMIC_LOAD_AND_I8 429 +#define PPC_ATOMIC_LOAD_MAX_I16 430 +#define PPC_ATOMIC_LOAD_MAX_I32 431 +#define PPC_ATOMIC_LOAD_MAX_I64 432 +#define PPC_ATOMIC_LOAD_MAX_I8 433 +#define PPC_ATOMIC_LOAD_MIN_I16 434 +#define PPC_ATOMIC_LOAD_MIN_I32 435 +#define PPC_ATOMIC_LOAD_MIN_I64 436 +#define PPC_ATOMIC_LOAD_MIN_I8 437 +#define PPC_ATOMIC_LOAD_NAND_I16 438 +#define PPC_ATOMIC_LOAD_NAND_I32 439 +#define PPC_ATOMIC_LOAD_NAND_I64 440 +#define PPC_ATOMIC_LOAD_NAND_I8 441 +#define PPC_ATOMIC_LOAD_OR_I16 442 +#define PPC_ATOMIC_LOAD_OR_I32 443 +#define PPC_ATOMIC_LOAD_OR_I64 444 +#define PPC_ATOMIC_LOAD_OR_I8 445 +#define PPC_ATOMIC_LOAD_SUB_I16 446 +#define PPC_ATOMIC_LOAD_SUB_I32 447 +#define PPC_ATOMIC_LOAD_SUB_I64 448 +#define PPC_ATOMIC_LOAD_SUB_I8 449 +#define PPC_ATOMIC_LOAD_UMAX_I16 450 +#define PPC_ATOMIC_LOAD_UMAX_I32 451 +#define PPC_ATOMIC_LOAD_UMAX_I64 452 +#define PPC_ATOMIC_LOAD_UMAX_I8 453 +#define PPC_ATOMIC_LOAD_UMIN_I16 454 +#define PPC_ATOMIC_LOAD_UMIN_I32 455 +#define PPC_ATOMIC_LOAD_UMIN_I64 456 +#define PPC_ATOMIC_LOAD_UMIN_I8 457 +#define PPC_ATOMIC_LOAD_XOR_I16 458 +#define PPC_ATOMIC_LOAD_XOR_I32 459 +#define PPC_ATOMIC_LOAD_XOR_I64 460 +#define PPC_ATOMIC_LOAD_XOR_I8 461 +#define PPC_ATOMIC_SWAP_I16 462 +#define PPC_ATOMIC_SWAP_I32 463 +#define PPC_ATOMIC_SWAP_I64 464 +#define PPC_ATOMIC_SWAP_I8 465 +#define PPC_ATTN 466 +#define PPC_B 467 +#define PPC_BA 468 +#define PPC_BC 469 +#define PPC_BCC 470 +#define PPC_BCCA 471 +#define PPC_BCCCTR 472 +#define PPC_BCCCTR8 473 +#define PPC_BCCCTRL 474 +#define PPC_BCCCTRL8 475 +#define PPC_BCCL 476 +#define PPC_BCCLA 477 +#define PPC_BCCLR 478 +#define PPC_BCCLRL 479 +#define PPC_BCCTR 480 +#define PPC_BCCTR8 481 +#define PPC_BCCTR8n 482 +#define PPC_BCCTRL 483 +#define PPC_BCCTRL8 484 +#define PPC_BCCTRL8n 485 +#define PPC_BCCTRLn 486 +#define PPC_BCCTRn 487 +#define PPC_BCDCFN_rec 488 +#define PPC_BCDCFSQ_rec 489 +#define PPC_BCDCFZ_rec 490 +#define PPC_BCDCPSGN_rec 491 +#define PPC_BCDCTN_rec 492 +#define PPC_BCDCTSQ_rec 493 +#define PPC_BCDCTZ_rec 494 +#define PPC_BCDSETSGN_rec 495 +#define PPC_BCDSR_rec 496 +#define PPC_BCDS_rec 497 +#define PPC_BCDTRUNC_rec 498 +#define PPC_BCDUS_rec 499 +#define PPC_BCDUTRUNC_rec 500 +#define PPC_BCL 501 +#define PPC_BCLR 502 +#define PPC_BCLRL 503 +#define PPC_BCLRLn 504 +#define PPC_BCLRn 505 +#define PPC_BCLalways 506 +#define PPC_BCLn 507 +#define PPC_BCTR 508 +#define PPC_BCTR8 509 +#define PPC_BCTRL 510 +#define PPC_BCTRL8 511 +#define PPC_BCTRL8_LDinto_toc 512 +#define PPC_BCTRL8_LDinto_toc_RM 513 +#define PPC_BCTRL8_RM 514 +#define PPC_BCTRL_LWZinto_toc 515 +#define PPC_BCTRL_LWZinto_toc_RM 516 +#define PPC_BCTRL_RM 517 +#define PPC_BCn 518 +#define PPC_BDNZ 519 +#define PPC_BDNZ8 520 +#define PPC_BDNZA 521 +#define PPC_BDNZAm 522 +#define PPC_BDNZAp 523 +#define PPC_BDNZL 524 +#define PPC_BDNZLA 525 +#define PPC_BDNZLAm 526 +#define PPC_BDNZLAp 527 +#define PPC_BDNZLR 528 +#define PPC_BDNZLR8 529 +#define PPC_BDNZLRL 530 +#define PPC_BDNZLRLm 531 +#define PPC_BDNZLRLp 532 +#define PPC_BDNZLRm 533 +#define PPC_BDNZLRp 534 +#define PPC_BDNZLm 535 +#define PPC_BDNZLp 536 +#define PPC_BDNZm 537 +#define PPC_BDNZp 538 +#define PPC_BDZ 539 +#define PPC_BDZ8 540 +#define PPC_BDZA 541 +#define PPC_BDZAm 542 +#define PPC_BDZAp 543 +#define PPC_BDZL 544 +#define PPC_BDZLA 545 +#define PPC_BDZLAm 546 +#define PPC_BDZLAp 547 +#define PPC_BDZLR 548 +#define PPC_BDZLR8 549 +#define PPC_BDZLRL 550 +#define PPC_BDZLRLm 551 +#define PPC_BDZLRLp 552 +#define PPC_BDZLRm 553 +#define PPC_BDZLRp 554 +#define PPC_BDZLm 555 +#define PPC_BDZLp 556 +#define PPC_BDZm 557 +#define PPC_BDZp 558 +#define PPC_BL 559 +#define PPC_BL8 560 +#define PPC_BL8_NOP 561 +#define PPC_BL8_NOP_RM 562 +#define PPC_BL8_NOP_TLS 563 +#define PPC_BL8_NOTOC 564 +#define PPC_BL8_NOTOC_RM 565 +#define PPC_BL8_NOTOC_TLS 566 +#define PPC_BL8_RM 567 +#define PPC_BL8_TLS 568 +#define PPC_BL8_TLS_ 569 +#define PPC_BLA 570 +#define PPC_BLA8 571 +#define PPC_BLA8_NOP 572 +#define PPC_BLA8_NOP_RM 573 +#define PPC_BLA8_RM 574 +#define PPC_BLA_RM 575 +#define PPC_BLR 576 +#define PPC_BLR8 577 +#define PPC_BLRL 578 +#define PPC_BL_NOP 579 +#define PPC_BL_NOP_RM 580 +#define PPC_BL_RM 581 +#define PPC_BL_TLS 582 +#define PPC_BPERMD 583 +#define PPC_BRINC 584 +#define PPC_CFUGED 585 +#define PPC_CLRBHRB 586 +#define PPC_CMPB 587 +#define PPC_CMPB8 588 +#define PPC_CMPD 589 +#define PPC_CMPDI 590 +#define PPC_CMPEQB 591 +#define PPC_CMPLD 592 +#define PPC_CMPLDI 593 +#define PPC_CMPLW 594 +#define PPC_CMPLWI 595 +#define PPC_CMPRB 596 +#define PPC_CMPRB8 597 +#define PPC_CMPW 598 +#define PPC_CMPWI 599 +#define PPC_CNTLZD 600 +#define PPC_CNTLZDM 601 +#define PPC_CNTLZD_rec 602 +#define PPC_CNTLZW 603 +#define PPC_CNTLZW8 604 +#define PPC_CNTLZW8_rec 605 +#define PPC_CNTLZW_rec 606 +#define PPC_CNTTZD 607 +#define PPC_CNTTZDM 608 +#define PPC_CNTTZD_rec 609 +#define PPC_CNTTZW 610 +#define PPC_CNTTZW8 611 +#define PPC_CNTTZW8_rec 612 +#define PPC_CNTTZW_rec 613 +#define PPC_CP_ABORT 614 +#define PPC_CP_COPY 615 +#define PPC_CP_COPY8 616 +#define PPC_CP_PASTE8_rec 617 +#define PPC_CP_PASTE_rec 618 +#define PPC_CR6SET 619 +#define PPC_CR6UNSET 620 +#define PPC_CRAND 621 +#define PPC_CRANDC 622 +#define PPC_CREQV 623 +#define PPC_CRNAND 624 +#define PPC_CRNOR 625 +#define PPC_CROR 626 +#define PPC_CRORC 627 +#define PPC_CRSET 628 +#define PPC_CRUNSET 629 +#define PPC_CRXOR 630 +#define PPC_CTRL_DEP 631 +#define PPC_DARN 632 +#define PPC_DCBA 633 +#define PPC_DCBF 634 +#define PPC_DCBFEP 635 +#define PPC_DCBI 636 +#define PPC_DCBST 637 +#define PPC_DCBSTEP 638 +#define PPC_DCBT 639 +#define PPC_DCBTEP 640 +#define PPC_DCBTST 641 +#define PPC_DCBTSTEP 642 +#define PPC_DCBZ 643 +#define PPC_DCBZEP 644 +#define PPC_DCBZL 645 +#define PPC_DCBZLEP 646 +#define PPC_DCCCI 647 +#define PPC_DIVD 648 +#define PPC_DIVDE 649 +#define PPC_DIVDEO 650 +#define PPC_DIVDEO_rec 651 +#define PPC_DIVDEU 652 +#define PPC_DIVDEUO 653 +#define PPC_DIVDEUO_rec 654 +#define PPC_DIVDEU_rec 655 +#define PPC_DIVDE_rec 656 +#define PPC_DIVDO 657 +#define PPC_DIVDO_rec 658 +#define PPC_DIVDU 659 +#define PPC_DIVDUO 660 +#define PPC_DIVDUO_rec 661 +#define PPC_DIVDU_rec 662 +#define PPC_DIVD_rec 663 +#define PPC_DIVW 664 +#define PPC_DIVWE 665 +#define PPC_DIVWEO 666 +#define PPC_DIVWEO_rec 667 +#define PPC_DIVWEU 668 +#define PPC_DIVWEUO 669 +#define PPC_DIVWEUO_rec 670 +#define PPC_DIVWEU_rec 671 +#define PPC_DIVWE_rec 672 +#define PPC_DIVWO 673 +#define PPC_DIVWO_rec 674 +#define PPC_DIVWU 675 +#define PPC_DIVWUO 676 +#define PPC_DIVWUO_rec 677 +#define PPC_DIVWU_rec 678 +#define PPC_DIVW_rec 679 +#define PPC_DSS 680 +#define PPC_DSSALL 681 +#define PPC_DST 682 +#define PPC_DST64 683 +#define PPC_DSTST 684 +#define PPC_DSTST64 685 +#define PPC_DSTSTT 686 +#define PPC_DSTSTT64 687 +#define PPC_DSTT 688 +#define PPC_DSTT64 689 +#define PPC_DYNALLOC 690 +#define PPC_DYNALLOC8 691 +#define PPC_DYNAREAOFFSET 692 +#define PPC_DYNAREAOFFSET8 693 +#define PPC_EFDABS 694 +#define PPC_EFDADD 695 +#define PPC_EFDCFS 696 +#define PPC_EFDCFSF 697 +#define PPC_EFDCFSI 698 +#define PPC_EFDCFSID 699 +#define PPC_EFDCFUF 700 +#define PPC_EFDCFUI 701 +#define PPC_EFDCFUID 702 +#define PPC_EFDCMPEQ 703 +#define PPC_EFDCMPGT 704 +#define PPC_EFDCMPLT 705 +#define PPC_EFDCTSF 706 +#define PPC_EFDCTSI 707 +#define PPC_EFDCTSIDZ 708 +#define PPC_EFDCTSIZ 709 +#define PPC_EFDCTUF 710 +#define PPC_EFDCTUI 711 +#define PPC_EFDCTUIDZ 712 +#define PPC_EFDCTUIZ 713 +#define PPC_EFDDIV 714 +#define PPC_EFDMUL 715 +#define PPC_EFDNABS 716 +#define PPC_EFDNEG 717 +#define PPC_EFDSUB 718 +#define PPC_EFDTSTEQ 719 +#define PPC_EFDTSTGT 720 +#define PPC_EFDTSTLT 721 +#define PPC_EFSABS 722 +#define PPC_EFSADD 723 +#define PPC_EFSCFD 724 +#define PPC_EFSCFSF 725 +#define PPC_EFSCFSI 726 +#define PPC_EFSCFUF 727 +#define PPC_EFSCFUI 728 +#define PPC_EFSCMPEQ 729 +#define PPC_EFSCMPGT 730 +#define PPC_EFSCMPLT 731 +#define PPC_EFSCTSF 732 +#define PPC_EFSCTSI 733 +#define PPC_EFSCTSIZ 734 +#define PPC_EFSCTUF 735 +#define PPC_EFSCTUI 736 +#define PPC_EFSCTUIZ 737 +#define PPC_EFSDIV 738 +#define PPC_EFSMUL 739 +#define PPC_EFSNABS 740 +#define PPC_EFSNEG 741 +#define PPC_EFSSUB 742 +#define PPC_EFSTSTEQ 743 +#define PPC_EFSTSTGT 744 +#define PPC_EFSTSTLT 745 +#define PPC_EH_SjLj_LongJmp32 746 +#define PPC_EH_SjLj_LongJmp64 747 +#define PPC_EH_SjLj_SetJmp32 748 +#define PPC_EH_SjLj_SetJmp64 749 +#define PPC_EH_SjLj_Setup 750 +#define PPC_EQV 751 +#define PPC_EQV8 752 +#define PPC_EQV8_rec 753 +#define PPC_EQV_rec 754 +#define PPC_EVABS 755 +#define PPC_EVADDIW 756 +#define PPC_EVADDSMIAAW 757 +#define PPC_EVADDSSIAAW 758 +#define PPC_EVADDUMIAAW 759 +#define PPC_EVADDUSIAAW 760 +#define PPC_EVADDW 761 +#define PPC_EVAND 762 +#define PPC_EVANDC 763 +#define PPC_EVCMPEQ 764 +#define PPC_EVCMPGTS 765 +#define PPC_EVCMPGTU 766 +#define PPC_EVCMPLTS 767 +#define PPC_EVCMPLTU 768 +#define PPC_EVCNTLSW 769 +#define PPC_EVCNTLZW 770 +#define PPC_EVDIVWS 771 +#define PPC_EVDIVWU 772 +#define PPC_EVEQV 773 +#define PPC_EVEXTSB 774 +#define PPC_EVEXTSH 775 +#define PPC_EVFSABS 776 +#define PPC_EVFSADD 777 +#define PPC_EVFSCFSF 778 +#define PPC_EVFSCFSI 779 +#define PPC_EVFSCFUF 780 +#define PPC_EVFSCFUI 781 +#define PPC_EVFSCMPEQ 782 +#define PPC_EVFSCMPGT 783 +#define PPC_EVFSCMPLT 784 +#define PPC_EVFSCTSF 785 +#define PPC_EVFSCTSI 786 +#define PPC_EVFSCTSIZ 787 +#define PPC_EVFSCTUF 788 +#define PPC_EVFSCTUI 789 +#define PPC_EVFSCTUIZ 790 +#define PPC_EVFSDIV 791 +#define PPC_EVFSMUL 792 +#define PPC_EVFSNABS 793 +#define PPC_EVFSNEG 794 +#define PPC_EVFSSUB 795 +#define PPC_EVFSTSTEQ 796 +#define PPC_EVFSTSTGT 797 +#define PPC_EVFSTSTLT 798 +#define PPC_EVLDD 799 +#define PPC_EVLDDX 800 +#define PPC_EVLDH 801 +#define PPC_EVLDHX 802 +#define PPC_EVLDW 803 +#define PPC_EVLDWX 804 +#define PPC_EVLHHESPLAT 805 +#define PPC_EVLHHESPLATX 806 +#define PPC_EVLHHOSSPLAT 807 +#define PPC_EVLHHOSSPLATX 808 +#define PPC_EVLHHOUSPLAT 809 +#define PPC_EVLHHOUSPLATX 810 +#define PPC_EVLWHE 811 +#define PPC_EVLWHEX 812 +#define PPC_EVLWHOS 813 +#define PPC_EVLWHOSX 814 +#define PPC_EVLWHOU 815 +#define PPC_EVLWHOUX 816 +#define PPC_EVLWHSPLAT 817 +#define PPC_EVLWHSPLATX 818 +#define PPC_EVLWWSPLAT 819 +#define PPC_EVLWWSPLATX 820 +#define PPC_EVMERGEHI 821 +#define PPC_EVMERGEHILO 822 +#define PPC_EVMERGELO 823 +#define PPC_EVMERGELOHI 824 +#define PPC_EVMHEGSMFAA 825 +#define PPC_EVMHEGSMFAN 826 +#define PPC_EVMHEGSMIAA 827 +#define PPC_EVMHEGSMIAN 828 +#define PPC_EVMHEGUMIAA 829 +#define PPC_EVMHEGUMIAN 830 +#define PPC_EVMHESMF 831 +#define PPC_EVMHESMFA 832 +#define PPC_EVMHESMFAAW 833 +#define PPC_EVMHESMFANW 834 +#define PPC_EVMHESMI 835 +#define PPC_EVMHESMIA 836 +#define PPC_EVMHESMIAAW 837 +#define PPC_EVMHESMIANW 838 +#define PPC_EVMHESSF 839 +#define PPC_EVMHESSFA 840 +#define PPC_EVMHESSFAAW 841 +#define PPC_EVMHESSFANW 842 +#define PPC_EVMHESSIAAW 843 +#define PPC_EVMHESSIANW 844 +#define PPC_EVMHEUMI 845 +#define PPC_EVMHEUMIA 846 +#define PPC_EVMHEUMIAAW 847 +#define PPC_EVMHEUMIANW 848 +#define PPC_EVMHEUSIAAW 849 +#define PPC_EVMHEUSIANW 850 +#define PPC_EVMHOGSMFAA 851 +#define PPC_EVMHOGSMFAN 852 +#define PPC_EVMHOGSMIAA 853 +#define PPC_EVMHOGSMIAN 854 +#define PPC_EVMHOGUMIAA 855 +#define PPC_EVMHOGUMIAN 856 +#define PPC_EVMHOSMF 857 +#define PPC_EVMHOSMFA 858 +#define PPC_EVMHOSMFAAW 859 +#define PPC_EVMHOSMFANW 860 +#define PPC_EVMHOSMI 861 +#define PPC_EVMHOSMIA 862 +#define PPC_EVMHOSMIAAW 863 +#define PPC_EVMHOSMIANW 864 +#define PPC_EVMHOSSF 865 +#define PPC_EVMHOSSFA 866 +#define PPC_EVMHOSSFAAW 867 +#define PPC_EVMHOSSFANW 868 +#define PPC_EVMHOSSIAAW 869 +#define PPC_EVMHOSSIANW 870 +#define PPC_EVMHOUMI 871 +#define PPC_EVMHOUMIA 872 +#define PPC_EVMHOUMIAAW 873 +#define PPC_EVMHOUMIANW 874 +#define PPC_EVMHOUSIAAW 875 +#define PPC_EVMHOUSIANW 876 +#define PPC_EVMRA 877 +#define PPC_EVMWHSMF 878 +#define PPC_EVMWHSMFA 879 +#define PPC_EVMWHSMI 880 +#define PPC_EVMWHSMIA 881 +#define PPC_EVMWHSSF 882 +#define PPC_EVMWHSSFA 883 +#define PPC_EVMWHUMI 884 +#define PPC_EVMWHUMIA 885 +#define PPC_EVMWLSMIAAW 886 +#define PPC_EVMWLSMIANW 887 +#define PPC_EVMWLSSIAAW 888 +#define PPC_EVMWLSSIANW 889 +#define PPC_EVMWLUMI 890 +#define PPC_EVMWLUMIA 891 +#define PPC_EVMWLUMIAAW 892 +#define PPC_EVMWLUMIANW 893 +#define PPC_EVMWLUSIAAW 894 +#define PPC_EVMWLUSIANW 895 +#define PPC_EVMWSMF 896 +#define PPC_EVMWSMFA 897 +#define PPC_EVMWSMFAA 898 +#define PPC_EVMWSMFAN 899 +#define PPC_EVMWSMI 900 +#define PPC_EVMWSMIA 901 +#define PPC_EVMWSMIAA 902 +#define PPC_EVMWSMIAN 903 +#define PPC_EVMWSSF 904 +#define PPC_EVMWSSFA 905 +#define PPC_EVMWSSFAA 906 +#define PPC_EVMWSSFAN 907 +#define PPC_EVMWUMI 908 +#define PPC_EVMWUMIA 909 +#define PPC_EVMWUMIAA 910 +#define PPC_EVMWUMIAN 911 +#define PPC_EVNAND 912 +#define PPC_EVNEG 913 +#define PPC_EVNOR 914 +#define PPC_EVOR 915 +#define PPC_EVORC 916 +#define PPC_EVRLW 917 +#define PPC_EVRLWI 918 +#define PPC_EVRNDW 919 +#define PPC_EVSEL 920 +#define PPC_EVSLW 921 +#define PPC_EVSLWI 922 +#define PPC_EVSPLATFI 923 +#define PPC_EVSPLATI 924 +#define PPC_EVSRWIS 925 +#define PPC_EVSRWIU 926 +#define PPC_EVSRWS 927 +#define PPC_EVSRWU 928 +#define PPC_EVSTDD 929 +#define PPC_EVSTDDX 930 +#define PPC_EVSTDH 931 +#define PPC_EVSTDHX 932 +#define PPC_EVSTDW 933 +#define PPC_EVSTDWX 934 +#define PPC_EVSTWHE 935 +#define PPC_EVSTWHEX 936 +#define PPC_EVSTWHO 937 +#define PPC_EVSTWHOX 938 +#define PPC_EVSTWWE 939 +#define PPC_EVSTWWEX 940 +#define PPC_EVSTWWO 941 +#define PPC_EVSTWWOX 942 +#define PPC_EVSUBFSMIAAW 943 +#define PPC_EVSUBFSSIAAW 944 +#define PPC_EVSUBFUMIAAW 945 +#define PPC_EVSUBFUSIAAW 946 +#define PPC_EVSUBFW 947 +#define PPC_EVSUBIFW 948 +#define PPC_EVXOR 949 +#define PPC_EXTSB 950 +#define PPC_EXTSB8 951 +#define PPC_EXTSB8_32_64 952 +#define PPC_EXTSB8_rec 953 +#define PPC_EXTSB_rec 954 +#define PPC_EXTSH 955 +#define PPC_EXTSH8 956 +#define PPC_EXTSH8_32_64 957 +#define PPC_EXTSH8_rec 958 +#define PPC_EXTSH_rec 959 +#define PPC_EXTSW 960 +#define PPC_EXTSWSLI 961 +#define PPC_EXTSWSLI_32_64 962 +#define PPC_EXTSWSLI_32_64_rec 963 +#define PPC_EXTSWSLI_rec 964 +#define PPC_EXTSW_32 965 +#define PPC_EXTSW_32_64 966 +#define PPC_EXTSW_32_64_rec 967 +#define PPC_EXTSW_rec 968 +#define PPC_EnforceIEIO 969 +#define PPC_FABSD 970 +#define PPC_FABSD_rec 971 +#define PPC_FABSS 972 +#define PPC_FABSS_rec 973 +#define PPC_FADD 974 +#define PPC_FADDS 975 +#define PPC_FADDS_rec 976 +#define PPC_FADD_rec 977 +#define PPC_FADDrtz 978 +#define PPC_FCFID 979 +#define PPC_FCFIDS 980 +#define PPC_FCFIDS_rec 981 +#define PPC_FCFIDU 982 +#define PPC_FCFIDUS 983 +#define PPC_FCFIDUS_rec 984 +#define PPC_FCFIDU_rec 985 +#define PPC_FCFID_rec 986 +#define PPC_FCMPOD 987 +#define PPC_FCMPOS 988 +#define PPC_FCMPUD 989 +#define PPC_FCMPUS 990 +#define PPC_FCPSGND 991 +#define PPC_FCPSGND_rec 992 +#define PPC_FCPSGNS 993 +#define PPC_FCPSGNS_rec 994 +#define PPC_FCTID 995 +#define PPC_FCTIDU 996 +#define PPC_FCTIDUZ 997 +#define PPC_FCTIDUZ_rec 998 +#define PPC_FCTIDU_rec 999 +#define PPC_FCTIDZ 1000 +#define PPC_FCTIDZ_rec 1001 +#define PPC_FCTID_rec 1002 +#define PPC_FCTIW 1003 +#define PPC_FCTIWU 1004 +#define PPC_FCTIWUZ 1005 +#define PPC_FCTIWUZ_rec 1006 +#define PPC_FCTIWU_rec 1007 +#define PPC_FCTIWZ 1008 +#define PPC_FCTIWZ_rec 1009 +#define PPC_FCTIW_rec 1010 +#define PPC_FDIV 1011 +#define PPC_FDIVS 1012 +#define PPC_FDIVS_rec 1013 +#define PPC_FDIV_rec 1014 +#define PPC_FMADD 1015 +#define PPC_FMADDS 1016 +#define PPC_FMADDS_rec 1017 +#define PPC_FMADD_rec 1018 +#define PPC_FMR 1019 +#define PPC_FMR_rec 1020 +#define PPC_FMSUB 1021 +#define PPC_FMSUBS 1022 +#define PPC_FMSUBS_rec 1023 +#define PPC_FMSUB_rec 1024 +#define PPC_FMUL 1025 +#define PPC_FMULS 1026 +#define PPC_FMULS_rec 1027 +#define PPC_FMUL_rec 1028 +#define PPC_FNABSD 1029 +#define PPC_FNABSD_rec 1030 +#define PPC_FNABSS 1031 +#define PPC_FNABSS_rec 1032 +#define PPC_FNEGD 1033 +#define PPC_FNEGD_rec 1034 +#define PPC_FNEGS 1035 +#define PPC_FNEGS_rec 1036 +#define PPC_FNMADD 1037 +#define PPC_FNMADDS 1038 +#define PPC_FNMADDS_rec 1039 +#define PPC_FNMADD_rec 1040 +#define PPC_FNMSUB 1041 +#define PPC_FNMSUBS 1042 +#define PPC_FNMSUBS_rec 1043 +#define PPC_FNMSUB_rec 1044 +#define PPC_FRE 1045 +#define PPC_FRES 1046 +#define PPC_FRES_rec 1047 +#define PPC_FRE_rec 1048 +#define PPC_FRIMD 1049 +#define PPC_FRIMD_rec 1050 +#define PPC_FRIMS 1051 +#define PPC_FRIMS_rec 1052 +#define PPC_FRIND 1053 +#define PPC_FRIND_rec 1054 +#define PPC_FRINS 1055 +#define PPC_FRINS_rec 1056 +#define PPC_FRIPD 1057 +#define PPC_FRIPD_rec 1058 +#define PPC_FRIPS 1059 +#define PPC_FRIPS_rec 1060 +#define PPC_FRIZD 1061 +#define PPC_FRIZD_rec 1062 +#define PPC_FRIZS 1063 +#define PPC_FRIZS_rec 1064 +#define PPC_FRSP 1065 +#define PPC_FRSP_rec 1066 +#define PPC_FRSQRTE 1067 +#define PPC_FRSQRTES 1068 +#define PPC_FRSQRTES_rec 1069 +#define PPC_FRSQRTE_rec 1070 +#define PPC_FSELD 1071 +#define PPC_FSELD_rec 1072 +#define PPC_FSELS 1073 +#define PPC_FSELS_rec 1074 +#define PPC_FSQRT 1075 +#define PPC_FSQRTS 1076 +#define PPC_FSQRTS_rec 1077 +#define PPC_FSQRT_rec 1078 +#define PPC_FSUB 1079 +#define PPC_FSUBS 1080 +#define PPC_FSUBS_rec 1081 +#define PPC_FSUB_rec 1082 +#define PPC_FTDIV 1083 +#define PPC_FTSQRT 1084 +#define PPC_GETtlsADDR 1085 +#define PPC_GETtlsADDR32 1086 +#define PPC_GETtlsADDR32AIX 1087 +#define PPC_GETtlsADDR64AIX 1088 +#define PPC_GETtlsADDRPCREL 1089 +#define PPC_GETtlsldADDR 1090 +#define PPC_GETtlsldADDR32 1091 +#define PPC_GETtlsldADDRPCREL 1092 +#define PPC_HASHCHK 1093 +#define PPC_HASHCHKP 1094 +#define PPC_HASHST 1095 +#define PPC_HASHSTP 1096 +#define PPC_HRFID 1097 +#define PPC_ICBI 1098 +#define PPC_ICBIEP 1099 +#define PPC_ICBLC 1100 +#define PPC_ICBLQ 1101 +#define PPC_ICBT 1102 +#define PPC_ICBTLS 1103 +#define PPC_ICCCI 1104 +#define PPC_ISEL 1105 +#define PPC_ISEL8 1106 +#define PPC_ISYNC 1107 +#define PPC_LA 1108 +#define PPC_LBARX 1109 +#define PPC_LBARXL 1110 +#define PPC_LBEPX 1111 +#define PPC_LBZ 1112 +#define PPC_LBZ8 1113 +#define PPC_LBZCIX 1114 +#define PPC_LBZU 1115 +#define PPC_LBZU8 1116 +#define PPC_LBZUX 1117 +#define PPC_LBZUX8 1118 +#define PPC_LBZX 1119 +#define PPC_LBZX8 1120 +#define PPC_LBZXTLS 1121 +#define PPC_LBZXTLS_ 1122 +#define PPC_LBZXTLS_32 1123 +#define PPC_LD 1124 +#define PPC_LDARX 1125 +#define PPC_LDARXL 1126 +#define PPC_LDAT 1127 +#define PPC_LDBRX 1128 +#define PPC_LDCIX 1129 +#define PPC_LDMX 1130 +#define PPC_LDU 1131 +#define PPC_LDUX 1132 +#define PPC_LDX 1133 +#define PPC_LDXTLS 1134 +#define PPC_LDXTLS_ 1135 +#define PPC_LDgotTprelL 1136 +#define PPC_LDgotTprelL32 1137 +#define PPC_LDtoc 1138 +#define PPC_LDtocBA 1139 +#define PPC_LDtocCPT 1140 +#define PPC_LDtocJTI 1141 +#define PPC_LDtocL 1142 +#define PPC_LFD 1143 +#define PPC_LFDEPX 1144 +#define PPC_LFDU 1145 +#define PPC_LFDUX 1146 +#define PPC_LFDX 1147 +#define PPC_LFIWAX 1148 +#define PPC_LFIWZX 1149 +#define PPC_LFS 1150 +#define PPC_LFSU 1151 +#define PPC_LFSUX 1152 +#define PPC_LFSX 1153 +#define PPC_LHA 1154 +#define PPC_LHA8 1155 +#define PPC_LHARX 1156 +#define PPC_LHARXL 1157 +#define PPC_LHAU 1158 +#define PPC_LHAU8 1159 +#define PPC_LHAUX 1160 +#define PPC_LHAUX8 1161 +#define PPC_LHAX 1162 +#define PPC_LHAX8 1163 +#define PPC_LHBRX 1164 +#define PPC_LHBRX8 1165 +#define PPC_LHEPX 1166 +#define PPC_LHZ 1167 +#define PPC_LHZ8 1168 +#define PPC_LHZCIX 1169 +#define PPC_LHZU 1170 +#define PPC_LHZU8 1171 +#define PPC_LHZUX 1172 +#define PPC_LHZUX8 1173 +#define PPC_LHZX 1174 +#define PPC_LHZX8 1175 +#define PPC_LHZXTLS 1176 +#define PPC_LHZXTLS_ 1177 +#define PPC_LHZXTLS_32 1178 +#define PPC_LI 1179 +#define PPC_LI8 1180 +#define PPC_LIS 1181 +#define PPC_LIS8 1182 +#define PPC_LMW 1183 +#define PPC_LQ 1184 +#define PPC_LQARX 1185 +#define PPC_LQARXL 1186 +#define PPC_LQX_PSEUDO 1187 +#define PPC_LSWI 1188 +#define PPC_LVEBX 1189 +#define PPC_LVEHX 1190 +#define PPC_LVEWX 1191 +#define PPC_LVSL 1192 +#define PPC_LVSR 1193 +#define PPC_LVX 1194 +#define PPC_LVXL 1195 +#define PPC_LWA 1196 +#define PPC_LWARX 1197 +#define PPC_LWARXL 1198 +#define PPC_LWAT 1199 +#define PPC_LWAUX 1200 +#define PPC_LWAX 1201 +#define PPC_LWAX_32 1202 +#define PPC_LWA_32 1203 +#define PPC_LWBRX 1204 +#define PPC_LWBRX8 1205 +#define PPC_LWEPX 1206 +#define PPC_LWZ 1207 +#define PPC_LWZ8 1208 +#define PPC_LWZCIX 1209 +#define PPC_LWZU 1210 +#define PPC_LWZU8 1211 +#define PPC_LWZUX 1212 +#define PPC_LWZUX8 1213 +#define PPC_LWZX 1214 +#define PPC_LWZX8 1215 +#define PPC_LWZXTLS 1216 +#define PPC_LWZXTLS_ 1217 +#define PPC_LWZXTLS_32 1218 +#define PPC_LWZtoc 1219 +#define PPC_LWZtocL 1220 +#define PPC_LXSD 1221 +#define PPC_LXSDX 1222 +#define PPC_LXSIBZX 1223 +#define PPC_LXSIHZX 1224 +#define PPC_LXSIWAX 1225 +#define PPC_LXSIWZX 1226 +#define PPC_LXSSP 1227 +#define PPC_LXSSPX 1228 +#define PPC_LXV 1229 +#define PPC_LXVB16X 1230 +#define PPC_LXVD2X 1231 +#define PPC_LXVDSX 1232 +#define PPC_LXVH8X 1233 +#define PPC_LXVL 1234 +#define PPC_LXVLL 1235 +#define PPC_LXVP 1236 +#define PPC_LXVPX 1237 +#define PPC_LXVRBX 1238 +#define PPC_LXVRDX 1239 +#define PPC_LXVRHX 1240 +#define PPC_LXVRWX 1241 +#define PPC_LXVW4X 1242 +#define PPC_LXVWSX 1243 +#define PPC_LXVX 1244 +#define PPC_MADDHD 1245 +#define PPC_MADDHDU 1246 +#define PPC_MADDLD 1247 +#define PPC_MADDLD8 1248 +#define PPC_MBAR 1249 +#define PPC_MCRF 1250 +#define PPC_MCRFS 1251 +#define PPC_MCRXRX 1252 +#define PPC_MFBHRBE 1253 +#define PPC_MFCR 1254 +#define PPC_MFCR8 1255 +#define PPC_MFCTR 1256 +#define PPC_MFCTR8 1257 +#define PPC_MFDCR 1258 +#define PPC_MFFS 1259 +#define PPC_MFFSCDRN 1260 +#define PPC_MFFSCDRNI 1261 +#define PPC_MFFSCE 1262 +#define PPC_MFFSCRN 1263 +#define PPC_MFFSCRNI 1264 +#define PPC_MFFSL 1265 +#define PPC_MFFS_rec 1266 +#define PPC_MFLR 1267 +#define PPC_MFLR8 1268 +#define PPC_MFMSR 1269 +#define PPC_MFOCRF 1270 +#define PPC_MFOCRF8 1271 +#define PPC_MFPMR 1272 +#define PPC_MFSPR 1273 +#define PPC_MFSPR8 1274 +#define PPC_MFSR 1275 +#define PPC_MFSRIN 1276 +#define PPC_MFTB 1277 +#define PPC_MFTB8 1278 +#define PPC_MFVRD 1279 +#define PPC_MFVRSAVE 1280 +#define PPC_MFVRSAVEv 1281 +#define PPC_MFVRWZ 1282 +#define PPC_MFVSCR 1283 +#define PPC_MFVSRD 1284 +#define PPC_MFVSRLD 1285 +#define PPC_MFVSRWZ 1286 +#define PPC_MODSD 1287 +#define PPC_MODSW 1288 +#define PPC_MODUD 1289 +#define PPC_MODUW 1290 +#define PPC_MSGSYNC 1291 +#define PPC_MSYNC 1292 +#define PPC_MTCRF 1293 +#define PPC_MTCRF8 1294 +#define PPC_MTCTR 1295 +#define PPC_MTCTR8 1296 +#define PPC_MTCTR8loop 1297 +#define PPC_MTCTRloop 1298 +#define PPC_MTDCR 1299 +#define PPC_MTFSB0 1300 +#define PPC_MTFSB1 1301 +#define PPC_MTFSF 1302 +#define PPC_MTFSFI 1303 +#define PPC_MTFSFI_rec 1304 +#define PPC_MTFSFIb 1305 +#define PPC_MTFSF_rec 1306 +#define PPC_MTFSFb 1307 +#define PPC_MTLR 1308 +#define PPC_MTLR8 1309 +#define PPC_MTMSR 1310 +#define PPC_MTMSRD 1311 +#define PPC_MTOCRF 1312 +#define PPC_MTOCRF8 1313 +#define PPC_MTPMR 1314 +#define PPC_MTSPR 1315 +#define PPC_MTSPR8 1316 +#define PPC_MTSR 1317 +#define PPC_MTSRIN 1318 +#define PPC_MTVRD 1319 +#define PPC_MTVRSAVE 1320 +#define PPC_MTVRSAVEv 1321 +#define PPC_MTVRWA 1322 +#define PPC_MTVRWZ 1323 +#define PPC_MTVSCR 1324 +#define PPC_MTVSRBM 1325 +#define PPC_MTVSRBMI 1326 +#define PPC_MTVSRD 1327 +#define PPC_MTVSRDD 1328 +#define PPC_MTVSRDM 1329 +#define PPC_MTVSRHM 1330 +#define PPC_MTVSRQM 1331 +#define PPC_MTVSRWA 1332 +#define PPC_MTVSRWM 1333 +#define PPC_MTVSRWS 1334 +#define PPC_MTVSRWZ 1335 +#define PPC_MULHD 1336 +#define PPC_MULHDU 1337 +#define PPC_MULHDU_rec 1338 +#define PPC_MULHD_rec 1339 +#define PPC_MULHW 1340 +#define PPC_MULHWU 1341 +#define PPC_MULHWU_rec 1342 +#define PPC_MULHW_rec 1343 +#define PPC_MULLD 1344 +#define PPC_MULLDO 1345 +#define PPC_MULLDO_rec 1346 +#define PPC_MULLD_rec 1347 +#define PPC_MULLI 1348 +#define PPC_MULLI8 1349 +#define PPC_MULLW 1350 +#define PPC_MULLWO 1351 +#define PPC_MULLWO_rec 1352 +#define PPC_MULLW_rec 1353 +#define PPC_MoveGOTtoLR 1354 +#define PPC_MovePCtoLR 1355 +#define PPC_MovePCtoLR8 1356 +#define PPC_NAND 1357 +#define PPC_NAND8 1358 +#define PPC_NAND8_rec 1359 +#define PPC_NAND_rec 1360 +#define PPC_NAP 1361 +#define PPC_NEG 1362 +#define PPC_NEG8 1363 +#define PPC_NEG8O 1364 +#define PPC_NEG8O_rec 1365 +#define PPC_NEG8_rec 1366 +#define PPC_NEGO 1367 +#define PPC_NEGO_rec 1368 +#define PPC_NEG_rec 1369 +#define PPC_NOP 1370 +#define PPC_NOP_GT_PWR6 1371 +#define PPC_NOP_GT_PWR7 1372 +#define PPC_NOR 1373 +#define PPC_NOR8 1374 +#define PPC_NOR8_rec 1375 +#define PPC_NOR_rec 1376 +#define PPC_OR 1377 +#define PPC_OR8 1378 +#define PPC_OR8_rec 1379 +#define PPC_ORC 1380 +#define PPC_ORC8 1381 +#define PPC_ORC8_rec 1382 +#define PPC_ORC_rec 1383 +#define PPC_ORI 1384 +#define PPC_ORI8 1385 +#define PPC_ORIS 1386 +#define PPC_ORIS8 1387 +#define PPC_OR_rec 1388 +#define PPC_PADDI 1389 +#define PPC_PADDI8 1390 +#define PPC_PADDI8pc 1391 +#define PPC_PADDIdtprel 1392 +#define PPC_PADDIpc 1393 +#define PPC_PDEPD 1394 +#define PPC_PEXTD 1395 +#define PPC_PLBZ 1396 +#define PPC_PLBZ8 1397 +#define PPC_PLBZ8pc 1398 +#define PPC_PLBZpc 1399 +#define PPC_PLD 1400 +#define PPC_PLDpc 1401 +#define PPC_PLFD 1402 +#define PPC_PLFDpc 1403 +#define PPC_PLFS 1404 +#define PPC_PLFSpc 1405 +#define PPC_PLHA 1406 +#define PPC_PLHA8 1407 +#define PPC_PLHA8pc 1408 +#define PPC_PLHApc 1409 +#define PPC_PLHZ 1410 +#define PPC_PLHZ8 1411 +#define PPC_PLHZ8pc 1412 +#define PPC_PLHZpc 1413 +#define PPC_PLI 1414 +#define PPC_PLI8 1415 +#define PPC_PLWA 1416 +#define PPC_PLWA8 1417 +#define PPC_PLWA8pc 1418 +#define PPC_PLWApc 1419 +#define PPC_PLWZ 1420 +#define PPC_PLWZ8 1421 +#define PPC_PLWZ8pc 1422 +#define PPC_PLWZpc 1423 +#define PPC_PLXSD 1424 +#define PPC_PLXSDpc 1425 +#define PPC_PLXSSP 1426 +#define PPC_PLXSSPpc 1427 +#define PPC_PLXV 1428 +#define PPC_PLXVP 1429 +#define PPC_PLXVPpc 1430 +#define PPC_PLXVpc 1431 +#define PPC_PMXVBF16GER2 1432 +#define PPC_PMXVBF16GER2NN 1433 +#define PPC_PMXVBF16GER2NP 1434 +#define PPC_PMXVBF16GER2PN 1435 +#define PPC_PMXVBF16GER2PP 1436 +#define PPC_PMXVF16GER2 1437 +#define PPC_PMXVF16GER2NN 1438 +#define PPC_PMXVF16GER2NP 1439 +#define PPC_PMXVF16GER2PN 1440 +#define PPC_PMXVF16GER2PP 1441 +#define PPC_PMXVF32GER 1442 +#define PPC_PMXVF32GERNN 1443 +#define PPC_PMXVF32GERNP 1444 +#define PPC_PMXVF32GERPN 1445 +#define PPC_PMXVF32GERPP 1446 +#define PPC_PMXVF64GER 1447 +#define PPC_PMXVF64GERNN 1448 +#define PPC_PMXVF64GERNP 1449 +#define PPC_PMXVF64GERPN 1450 +#define PPC_PMXVF64GERPP 1451 +#define PPC_PMXVI16GER2 1452 +#define PPC_PMXVI16GER2PP 1453 +#define PPC_PMXVI16GER2S 1454 +#define PPC_PMXVI16GER2SPP 1455 +#define PPC_PMXVI4GER8 1456 +#define PPC_PMXVI4GER8PP 1457 +#define PPC_PMXVI8GER4 1458 +#define PPC_PMXVI8GER4PP 1459 +#define PPC_PMXVI8GER4SPP 1460 +#define PPC_POPCNTB 1461 +#define PPC_POPCNTB8 1462 +#define PPC_POPCNTD 1463 +#define PPC_POPCNTW 1464 +#define PPC_PPC32GOT 1465 +#define PPC_PPC32PICGOT 1466 +#define PPC_PREPARE_PROBED_ALLOCA_32 1467 +#define PPC_PREPARE_PROBED_ALLOCA_64 1468 +#define PPC_PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 1469 +#define PPC_PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 1470 +#define PPC_PROBED_ALLOCA_32 1471 +#define PPC_PROBED_ALLOCA_64 1472 +#define PPC_PROBED_STACKALLOC_32 1473 +#define PPC_PROBED_STACKALLOC_64 1474 +#define PPC_PSTB 1475 +#define PPC_PSTB8 1476 +#define PPC_PSTB8pc 1477 +#define PPC_PSTBpc 1478 +#define PPC_PSTD 1479 +#define PPC_PSTDpc 1480 +#define PPC_PSTFD 1481 +#define PPC_PSTFDpc 1482 +#define PPC_PSTFS 1483 +#define PPC_PSTFSpc 1484 +#define PPC_PSTH 1485 +#define PPC_PSTH8 1486 +#define PPC_PSTH8pc 1487 +#define PPC_PSTHpc 1488 +#define PPC_PSTW 1489 +#define PPC_PSTW8 1490 +#define PPC_PSTW8pc 1491 +#define PPC_PSTWpc 1492 +#define PPC_PSTXSD 1493 +#define PPC_PSTXSDpc 1494 +#define PPC_PSTXSSP 1495 +#define PPC_PSTXSSPpc 1496 +#define PPC_PSTXV 1497 +#define PPC_PSTXVP 1498 +#define PPC_PSTXVPpc 1499 +#define PPC_PSTXVpc 1500 +#define PPC_PseudoEIEIO 1501 +#define PPC_RESTORE_ACC 1502 +#define PPC_RESTORE_CR 1503 +#define PPC_RESTORE_CRBIT 1504 +#define PPC_RESTORE_QUADWORD 1505 +#define PPC_RESTORE_UACC 1506 +#define PPC_RFCI 1507 +#define PPC_RFDI 1508 +#define PPC_RFEBB 1509 +#define PPC_RFI 1510 +#define PPC_RFID 1511 +#define PPC_RFMCI 1512 +#define PPC_RLDCL 1513 +#define PPC_RLDCL_rec 1514 +#define PPC_RLDCR 1515 +#define PPC_RLDCR_rec 1516 +#define PPC_RLDIC 1517 +#define PPC_RLDICL 1518 +#define PPC_RLDICL_32 1519 +#define PPC_RLDICL_32_64 1520 +#define PPC_RLDICL_32_rec 1521 +#define PPC_RLDICL_rec 1522 +#define PPC_RLDICR 1523 +#define PPC_RLDICR_32 1524 +#define PPC_RLDICR_rec 1525 +#define PPC_RLDIC_rec 1526 +#define PPC_RLDIMI 1527 +#define PPC_RLDIMI_rec 1528 +#define PPC_RLWIMI 1529 +#define PPC_RLWIMI8 1530 +#define PPC_RLWIMI8_rec 1531 +#define PPC_RLWIMI_rec 1532 +#define PPC_RLWINM 1533 +#define PPC_RLWINM8 1534 +#define PPC_RLWINM8_rec 1535 +#define PPC_RLWINM_rec 1536 +#define PPC_RLWNM 1537 +#define PPC_RLWNM8 1538 +#define PPC_RLWNM8_rec 1539 +#define PPC_RLWNM_rec 1540 +#define PPC_ReadTB 1541 +#define PPC_SC 1542 +#define PPC_SELECT_CC_F16 1543 +#define PPC_SELECT_CC_F4 1544 +#define PPC_SELECT_CC_F8 1545 +#define PPC_SELECT_CC_I4 1546 +#define PPC_SELECT_CC_I8 1547 +#define PPC_SELECT_CC_SPE 1548 +#define PPC_SELECT_CC_SPE4 1549 +#define PPC_SELECT_CC_VRRC 1550 +#define PPC_SELECT_CC_VSFRC 1551 +#define PPC_SELECT_CC_VSRC 1552 +#define PPC_SELECT_CC_VSSRC 1553 +#define PPC_SELECT_F16 1554 +#define PPC_SELECT_F4 1555 +#define PPC_SELECT_F8 1556 +#define PPC_SELECT_I4 1557 +#define PPC_SELECT_I8 1558 +#define PPC_SELECT_SPE 1559 +#define PPC_SELECT_SPE4 1560 +#define PPC_SELECT_VRRC 1561 +#define PPC_SELECT_VSFRC 1562 +#define PPC_SELECT_VSRC 1563 +#define PPC_SELECT_VSSRC 1564 +#define PPC_SETB 1565 +#define PPC_SETB8 1566 +#define PPC_SETBC 1567 +#define PPC_SETBC8 1568 +#define PPC_SETBCR 1569 +#define PPC_SETBCR8 1570 +#define PPC_SETFLM 1571 +#define PPC_SETNBC 1572 +#define PPC_SETNBC8 1573 +#define PPC_SETNBCR 1574 +#define PPC_SETNBCR8 1575 +#define PPC_SETRND 1576 +#define PPC_SETRNDi 1577 +#define PPC_SLBFEE_rec 1578 +#define PPC_SLBIA 1579 +#define PPC_SLBIE 1580 +#define PPC_SLBIEG 1581 +#define PPC_SLBMFEE 1582 +#define PPC_SLBMFEV 1583 +#define PPC_SLBMTE 1584 +#define PPC_SLBSYNC 1585 +#define PPC_SLD 1586 +#define PPC_SLD_rec 1587 +#define PPC_SLW 1588 +#define PPC_SLW8 1589 +#define PPC_SLW8_rec 1590 +#define PPC_SLW_rec 1591 +#define PPC_SPELWZ 1592 +#define PPC_SPELWZX 1593 +#define PPC_SPESTW 1594 +#define PPC_SPESTWX 1595 +#define PPC_SPILL_ACC 1596 +#define PPC_SPILL_CR 1597 +#define PPC_SPILL_CRBIT 1598 +#define PPC_SPILL_QUADWORD 1599 +#define PPC_SPILL_UACC 1600 +#define PPC_SPLIT_QUADWORD 1601 +#define PPC_SRAD 1602 +#define PPC_SRADI 1603 +#define PPC_SRADI_32 1604 +#define PPC_SRADI_rec 1605 +#define PPC_SRAD_rec 1606 +#define PPC_SRAW 1607 +#define PPC_SRAWI 1608 +#define PPC_SRAWI_rec 1609 +#define PPC_SRAW_rec 1610 +#define PPC_SRD 1611 +#define PPC_SRD_rec 1612 +#define PPC_SRW 1613 +#define PPC_SRW8 1614 +#define PPC_SRW8_rec 1615 +#define PPC_SRW_rec 1616 +#define PPC_STB 1617 +#define PPC_STB8 1618 +#define PPC_STBCIX 1619 +#define PPC_STBCX 1620 +#define PPC_STBEPX 1621 +#define PPC_STBU 1622 +#define PPC_STBU8 1623 +#define PPC_STBUX 1624 +#define PPC_STBUX8 1625 +#define PPC_STBX 1626 +#define PPC_STBX8 1627 +#define PPC_STBXTLS 1628 +#define PPC_STBXTLS_ 1629 +#define PPC_STBXTLS_32 1630 +#define PPC_STD 1631 +#define PPC_STDAT 1632 +#define PPC_STDBRX 1633 +#define PPC_STDCIX 1634 +#define PPC_STDCX 1635 +#define PPC_STDU 1636 +#define PPC_STDUX 1637 +#define PPC_STDX 1638 +#define PPC_STDXTLS 1639 +#define PPC_STDXTLS_ 1640 +#define PPC_STFD 1641 +#define PPC_STFDEPX 1642 +#define PPC_STFDU 1643 +#define PPC_STFDUX 1644 +#define PPC_STFDX 1645 +#define PPC_STFIWX 1646 +#define PPC_STFS 1647 +#define PPC_STFSU 1648 +#define PPC_STFSUX 1649 +#define PPC_STFSX 1650 +#define PPC_STH 1651 +#define PPC_STH8 1652 +#define PPC_STHBRX 1653 +#define PPC_STHCIX 1654 +#define PPC_STHCX 1655 +#define PPC_STHEPX 1656 +#define PPC_STHU 1657 +#define PPC_STHU8 1658 +#define PPC_STHUX 1659 +#define PPC_STHUX8 1660 +#define PPC_STHX 1661 +#define PPC_STHX8 1662 +#define PPC_STHXTLS 1663 +#define PPC_STHXTLS_ 1664 +#define PPC_STHXTLS_32 1665 +#define PPC_STMW 1666 +#define PPC_STOP 1667 +#define PPC_STQ 1668 +#define PPC_STQCX 1669 +#define PPC_STQX_PSEUDO 1670 +#define PPC_STSWI 1671 +#define PPC_STVEBX 1672 +#define PPC_STVEHX 1673 +#define PPC_STVEWX 1674 +#define PPC_STVX 1675 +#define PPC_STVXL 1676 +#define PPC_STW 1677 +#define PPC_STW8 1678 +#define PPC_STWAT 1679 +#define PPC_STWBRX 1680 +#define PPC_STWCIX 1681 +#define PPC_STWCX 1682 +#define PPC_STWEPX 1683 +#define PPC_STWU 1684 +#define PPC_STWU8 1685 +#define PPC_STWUX 1686 +#define PPC_STWUX8 1687 +#define PPC_STWX 1688 +#define PPC_STWX8 1689 +#define PPC_STWXTLS 1690 +#define PPC_STWXTLS_ 1691 +#define PPC_STWXTLS_32 1692 +#define PPC_STXSD 1693 +#define PPC_STXSDX 1694 +#define PPC_STXSIBX 1695 +#define PPC_STXSIBXv 1696 +#define PPC_STXSIHX 1697 +#define PPC_STXSIHXv 1698 +#define PPC_STXSIWX 1699 +#define PPC_STXSSP 1700 +#define PPC_STXSSPX 1701 +#define PPC_STXV 1702 +#define PPC_STXVB16X 1703 +#define PPC_STXVD2X 1704 +#define PPC_STXVH8X 1705 +#define PPC_STXVL 1706 +#define PPC_STXVLL 1707 +#define PPC_STXVP 1708 +#define PPC_STXVPX 1709 +#define PPC_STXVRBX 1710 +#define PPC_STXVRDX 1711 +#define PPC_STXVRHX 1712 +#define PPC_STXVRWX 1713 +#define PPC_STXVW4X 1714 +#define PPC_STXVX 1715 +#define PPC_SUBF 1716 +#define PPC_SUBF8 1717 +#define PPC_SUBF8O 1718 +#define PPC_SUBF8O_rec 1719 +#define PPC_SUBF8_rec 1720 +#define PPC_SUBFC 1721 +#define PPC_SUBFC8 1722 +#define PPC_SUBFC8O 1723 +#define PPC_SUBFC8O_rec 1724 +#define PPC_SUBFC8_rec 1725 +#define PPC_SUBFCO 1726 +#define PPC_SUBFCO_rec 1727 +#define PPC_SUBFC_rec 1728 +#define PPC_SUBFE 1729 +#define PPC_SUBFE8 1730 +#define PPC_SUBFE8O 1731 +#define PPC_SUBFE8O_rec 1732 +#define PPC_SUBFE8_rec 1733 +#define PPC_SUBFEO 1734 +#define PPC_SUBFEO_rec 1735 +#define PPC_SUBFE_rec 1736 +#define PPC_SUBFIC 1737 +#define PPC_SUBFIC8 1738 +#define PPC_SUBFME 1739 +#define PPC_SUBFME8 1740 +#define PPC_SUBFME8O 1741 +#define PPC_SUBFME8O_rec 1742 +#define PPC_SUBFME8_rec 1743 +#define PPC_SUBFMEO 1744 +#define PPC_SUBFMEO_rec 1745 +#define PPC_SUBFME_rec 1746 +#define PPC_SUBFO 1747 +#define PPC_SUBFO_rec 1748 +#define PPC_SUBFZE 1749 +#define PPC_SUBFZE8 1750 +#define PPC_SUBFZE8O 1751 +#define PPC_SUBFZE8O_rec 1752 +#define PPC_SUBFZE8_rec 1753 +#define PPC_SUBFZEO 1754 +#define PPC_SUBFZEO_rec 1755 +#define PPC_SUBFZE_rec 1756 +#define PPC_SUBF_rec 1757 +#define PPC_SYNC 1758 +#define PPC_TABORT 1759 +#define PPC_TABORTDC 1760 +#define PPC_TABORTDCI 1761 +#define PPC_TABORTWC 1762 +#define PPC_TABORTWCI 1763 +#define PPC_TAILB 1764 +#define PPC_TAILB8 1765 +#define PPC_TAILBA 1766 +#define PPC_TAILBA8 1767 +#define PPC_TAILBCTR 1768 +#define PPC_TAILBCTR8 1769 +#define PPC_TBEGIN 1770 +#define PPC_TBEGIN_RET 1771 +#define PPC_TCHECK 1772 +#define PPC_TCHECK_RET 1773 +#define PPC_TCRETURNai 1774 +#define PPC_TCRETURNai8 1775 +#define PPC_TCRETURNdi 1776 +#define PPC_TCRETURNdi8 1777 +#define PPC_TCRETURNri 1778 +#define PPC_TCRETURNri8 1779 +#define PPC_TD 1780 +#define PPC_TDI 1781 +#define PPC_TEND 1782 +#define PPC_TLBIA 1783 +#define PPC_TLBIE 1784 +#define PPC_TLBIEL 1785 +#define PPC_TLBIVAX 1786 +#define PPC_TLBLD 1787 +#define PPC_TLBLI 1788 +#define PPC_TLBRE 1789 +#define PPC_TLBRE2 1790 +#define PPC_TLBSX 1791 +#define PPC_TLBSX2 1792 +#define PPC_TLBSX2D 1793 +#define PPC_TLBSYNC 1794 +#define PPC_TLBWE 1795 +#define PPC_TLBWE2 1796 +#define PPC_TLSGDAIX 1797 +#define PPC_TLSGDAIX8 1798 +#define PPC_TRAP 1799 +#define PPC_TRECHKPT 1800 +#define PPC_TRECLAIM 1801 +#define PPC_TSR 1802 +#define PPC_TW 1803 +#define PPC_TWI 1804 +#define PPC_UNENCODED_NOP 1805 +#define PPC_UpdateGBR 1806 +#define PPC_VABSDUB 1807 +#define PPC_VABSDUH 1808 +#define PPC_VABSDUW 1809 +#define PPC_VADDCUQ 1810 +#define PPC_VADDCUW 1811 +#define PPC_VADDECUQ 1812 +#define PPC_VADDEUQM 1813 +#define PPC_VADDFP 1814 +#define PPC_VADDSBS 1815 +#define PPC_VADDSHS 1816 +#define PPC_VADDSWS 1817 +#define PPC_VADDUBM 1818 +#define PPC_VADDUBS 1819 +#define PPC_VADDUDM 1820 +#define PPC_VADDUHM 1821 +#define PPC_VADDUHS 1822 +#define PPC_VADDUQM 1823 +#define PPC_VADDUWM 1824 +#define PPC_VADDUWS 1825 +#define PPC_VAND 1826 +#define PPC_VANDC 1827 +#define PPC_VAVGSB 1828 +#define PPC_VAVGSH 1829 +#define PPC_VAVGSW 1830 +#define PPC_VAVGUB 1831 +#define PPC_VAVGUH 1832 +#define PPC_VAVGUW 1833 +#define PPC_VBPERMD 1834 +#define PPC_VBPERMQ 1835 +#define PPC_VCFSX 1836 +#define PPC_VCFSX_0 1837 +#define PPC_VCFUGED 1838 +#define PPC_VCFUX 1839 +#define PPC_VCFUX_0 1840 +#define PPC_VCIPHER 1841 +#define PPC_VCIPHERLAST 1842 +#define PPC_VCLRLB 1843 +#define PPC_VCLRRB 1844 +#define PPC_VCLZB 1845 +#define PPC_VCLZD 1846 +#define PPC_VCLZDM 1847 +#define PPC_VCLZH 1848 +#define PPC_VCLZLSBB 1849 +#define PPC_VCLZW 1850 +#define PPC_VCMPBFP 1851 +#define PPC_VCMPBFP_rec 1852 +#define PPC_VCMPEQFP 1853 +#define PPC_VCMPEQFP_rec 1854 +#define PPC_VCMPEQUB 1855 +#define PPC_VCMPEQUB_rec 1856 +#define PPC_VCMPEQUD 1857 +#define PPC_VCMPEQUD_rec 1858 +#define PPC_VCMPEQUH 1859 +#define PPC_VCMPEQUH_rec 1860 +#define PPC_VCMPEQUQ 1861 +#define PPC_VCMPEQUQ_rec 1862 +#define PPC_VCMPEQUW 1863 +#define PPC_VCMPEQUW_rec 1864 +#define PPC_VCMPGEFP 1865 +#define PPC_VCMPGEFP_rec 1866 +#define PPC_VCMPGTFP 1867 +#define PPC_VCMPGTFP_rec 1868 +#define PPC_VCMPGTSB 1869 +#define PPC_VCMPGTSB_rec 1870 +#define PPC_VCMPGTSD 1871 +#define PPC_VCMPGTSD_rec 1872 +#define PPC_VCMPGTSH 1873 +#define PPC_VCMPGTSH_rec 1874 +#define PPC_VCMPGTSQ 1875 +#define PPC_VCMPGTSQ_rec 1876 +#define PPC_VCMPGTSW 1877 +#define PPC_VCMPGTSW_rec 1878 +#define PPC_VCMPGTUB 1879 +#define PPC_VCMPGTUB_rec 1880 +#define PPC_VCMPGTUD 1881 +#define PPC_VCMPGTUD_rec 1882 +#define PPC_VCMPGTUH 1883 +#define PPC_VCMPGTUH_rec 1884 +#define PPC_VCMPGTUQ 1885 +#define PPC_VCMPGTUQ_rec 1886 +#define PPC_VCMPGTUW 1887 +#define PPC_VCMPGTUW_rec 1888 +#define PPC_VCMPNEB 1889 +#define PPC_VCMPNEB_rec 1890 +#define PPC_VCMPNEH 1891 +#define PPC_VCMPNEH_rec 1892 +#define PPC_VCMPNEW 1893 +#define PPC_VCMPNEW_rec 1894 +#define PPC_VCMPNEZB 1895 +#define PPC_VCMPNEZB_rec 1896 +#define PPC_VCMPNEZH 1897 +#define PPC_VCMPNEZH_rec 1898 +#define PPC_VCMPNEZW 1899 +#define PPC_VCMPNEZW_rec 1900 +#define PPC_VCMPSQ 1901 +#define PPC_VCMPUQ 1902 +#define PPC_VCNTMBB 1903 +#define PPC_VCNTMBD 1904 +#define PPC_VCNTMBH 1905 +#define PPC_VCNTMBW 1906 +#define PPC_VCTSXS 1907 +#define PPC_VCTSXS_0 1908 +#define PPC_VCTUXS 1909 +#define PPC_VCTUXS_0 1910 +#define PPC_VCTZB 1911 +#define PPC_VCTZD 1912 +#define PPC_VCTZDM 1913 +#define PPC_VCTZH 1914 +#define PPC_VCTZLSBB 1915 +#define PPC_VCTZW 1916 +#define PPC_VDIVESD 1917 +#define PPC_VDIVESQ 1918 +#define PPC_VDIVESW 1919 +#define PPC_VDIVEUD 1920 +#define PPC_VDIVEUQ 1921 +#define PPC_VDIVEUW 1922 +#define PPC_VDIVSD 1923 +#define PPC_VDIVSQ 1924 +#define PPC_VDIVSW 1925 +#define PPC_VDIVUD 1926 +#define PPC_VDIVUQ 1927 +#define PPC_VDIVUW 1928 +#define PPC_VEQV 1929 +#define PPC_VEXPANDBM 1930 +#define PPC_VEXPANDDM 1931 +#define PPC_VEXPANDHM 1932 +#define PPC_VEXPANDQM 1933 +#define PPC_VEXPANDWM 1934 +#define PPC_VEXPTEFP 1935 +#define PPC_VEXTDDVLX 1936 +#define PPC_VEXTDDVRX 1937 +#define PPC_VEXTDUBVLX 1938 +#define PPC_VEXTDUBVRX 1939 +#define PPC_VEXTDUHVLX 1940 +#define PPC_VEXTDUHVRX 1941 +#define PPC_VEXTDUWVLX 1942 +#define PPC_VEXTDUWVRX 1943 +#define PPC_VEXTRACTBM 1944 +#define PPC_VEXTRACTD 1945 +#define PPC_VEXTRACTDM 1946 +#define PPC_VEXTRACTHM 1947 +#define PPC_VEXTRACTQM 1948 +#define PPC_VEXTRACTUB 1949 +#define PPC_VEXTRACTUH 1950 +#define PPC_VEXTRACTUW 1951 +#define PPC_VEXTRACTWM 1952 +#define PPC_VEXTSB2D 1953 +#define PPC_VEXTSB2Ds 1954 +#define PPC_VEXTSB2W 1955 +#define PPC_VEXTSB2Ws 1956 +#define PPC_VEXTSD2Q 1957 +#define PPC_VEXTSH2D 1958 +#define PPC_VEXTSH2Ds 1959 +#define PPC_VEXTSH2W 1960 +#define PPC_VEXTSH2Ws 1961 +#define PPC_VEXTSW2D 1962 +#define PPC_VEXTSW2Ds 1963 +#define PPC_VEXTUBLX 1964 +#define PPC_VEXTUBRX 1965 +#define PPC_VEXTUHLX 1966 +#define PPC_VEXTUHRX 1967 +#define PPC_VEXTUWLX 1968 +#define PPC_VEXTUWRX 1969 +#define PPC_VGBBD 1970 +#define PPC_VGNB 1971 +#define PPC_VINSBLX 1972 +#define PPC_VINSBRX 1973 +#define PPC_VINSBVLX 1974 +#define PPC_VINSBVRX 1975 +#define PPC_VINSD 1976 +#define PPC_VINSDLX 1977 +#define PPC_VINSDRX 1978 +#define PPC_VINSERTB 1979 +#define PPC_VINSERTD 1980 +#define PPC_VINSERTH 1981 +#define PPC_VINSERTW 1982 +#define PPC_VINSHLX 1983 +#define PPC_VINSHRX 1984 +#define PPC_VINSHVLX 1985 +#define PPC_VINSHVRX 1986 +#define PPC_VINSW 1987 +#define PPC_VINSWLX 1988 +#define PPC_VINSWRX 1989 +#define PPC_VINSWVLX 1990 +#define PPC_VINSWVRX 1991 +#define PPC_VLOGEFP 1992 +#define PPC_VMADDFP 1993 +#define PPC_VMAXFP 1994 +#define PPC_VMAXSB 1995 +#define PPC_VMAXSD 1996 +#define PPC_VMAXSH 1997 +#define PPC_VMAXSW 1998 +#define PPC_VMAXUB 1999 +#define PPC_VMAXUD 2000 +#define PPC_VMAXUH 2001 +#define PPC_VMAXUW 2002 +#define PPC_VMHADDSHS 2003 +#define PPC_VMHRADDSHS 2004 +#define PPC_VMINFP 2005 +#define PPC_VMINSB 2006 +#define PPC_VMINSD 2007 +#define PPC_VMINSH 2008 +#define PPC_VMINSW 2009 +#define PPC_VMINUB 2010 +#define PPC_VMINUD 2011 +#define PPC_VMINUH 2012 +#define PPC_VMINUW 2013 +#define PPC_VMLADDUHM 2014 +#define PPC_VMODSD 2015 +#define PPC_VMODSQ 2016 +#define PPC_VMODSW 2017 +#define PPC_VMODUD 2018 +#define PPC_VMODUQ 2019 +#define PPC_VMODUW 2020 +#define PPC_VMRGEW 2021 +#define PPC_VMRGHB 2022 +#define PPC_VMRGHH 2023 +#define PPC_VMRGHW 2024 +#define PPC_VMRGLB 2025 +#define PPC_VMRGLH 2026 +#define PPC_VMRGLW 2027 +#define PPC_VMRGOW 2028 +#define PPC_VMSUMCUD 2029 +#define PPC_VMSUMMBM 2030 +#define PPC_VMSUMSHM 2031 +#define PPC_VMSUMSHS 2032 +#define PPC_VMSUMUBM 2033 +#define PPC_VMSUMUDM 2034 +#define PPC_VMSUMUHM 2035 +#define PPC_VMSUMUHS 2036 +#define PPC_VMUL10CUQ 2037 +#define PPC_VMUL10ECUQ 2038 +#define PPC_VMUL10EUQ 2039 +#define PPC_VMUL10UQ 2040 +#define PPC_VMULESB 2041 +#define PPC_VMULESD 2042 +#define PPC_VMULESH 2043 +#define PPC_VMULESW 2044 +#define PPC_VMULEUB 2045 +#define PPC_VMULEUD 2046 +#define PPC_VMULEUH 2047 +#define PPC_VMULEUW 2048 +#define PPC_VMULHSD 2049 +#define PPC_VMULHSW 2050 +#define PPC_VMULHUD 2051 +#define PPC_VMULHUW 2052 +#define PPC_VMULLD 2053 +#define PPC_VMULOSB 2054 +#define PPC_VMULOSD 2055 +#define PPC_VMULOSH 2056 +#define PPC_VMULOSW 2057 +#define PPC_VMULOUB 2058 +#define PPC_VMULOUD 2059 +#define PPC_VMULOUH 2060 +#define PPC_VMULOUW 2061 +#define PPC_VMULUWM 2062 +#define PPC_VNAND 2063 +#define PPC_VNCIPHER 2064 +#define PPC_VNCIPHERLAST 2065 +#define PPC_VNEGD 2066 +#define PPC_VNEGW 2067 +#define PPC_VNMSUBFP 2068 +#define PPC_VNOR 2069 +#define PPC_VOR 2070 +#define PPC_VORC 2071 +#define PPC_VPDEPD 2072 +#define PPC_VPERM 2073 +#define PPC_VPERMR 2074 +#define PPC_VPERMXOR 2075 +#define PPC_VPEXTD 2076 +#define PPC_VPKPX 2077 +#define PPC_VPKSDSS 2078 +#define PPC_VPKSDUS 2079 +#define PPC_VPKSHSS 2080 +#define PPC_VPKSHUS 2081 +#define PPC_VPKSWSS 2082 +#define PPC_VPKSWUS 2083 +#define PPC_VPKUDUM 2084 +#define PPC_VPKUDUS 2085 +#define PPC_VPKUHUM 2086 +#define PPC_VPKUHUS 2087 +#define PPC_VPKUWUM 2088 +#define PPC_VPKUWUS 2089 +#define PPC_VPMSUMB 2090 +#define PPC_VPMSUMD 2091 +#define PPC_VPMSUMH 2092 +#define PPC_VPMSUMW 2093 +#define PPC_VPOPCNTB 2094 +#define PPC_VPOPCNTD 2095 +#define PPC_VPOPCNTH 2096 +#define PPC_VPOPCNTW 2097 +#define PPC_VPRTYBD 2098 +#define PPC_VPRTYBQ 2099 +#define PPC_VPRTYBW 2100 +#define PPC_VREFP 2101 +#define PPC_VRFIM 2102 +#define PPC_VRFIN 2103 +#define PPC_VRFIP 2104 +#define PPC_VRFIZ 2105 +#define PPC_VRLB 2106 +#define PPC_VRLD 2107 +#define PPC_VRLDMI 2108 +#define PPC_VRLDNM 2109 +#define PPC_VRLH 2110 +#define PPC_VRLQ 2111 +#define PPC_VRLQMI 2112 +#define PPC_VRLQNM 2113 +#define PPC_VRLW 2114 +#define PPC_VRLWMI 2115 +#define PPC_VRLWNM 2116 +#define PPC_VRSQRTEFP 2117 +#define PPC_VSBOX 2118 +#define PPC_VSEL 2119 +#define PPC_VSHASIGMAD 2120 +#define PPC_VSHASIGMAW 2121 +#define PPC_VSL 2122 +#define PPC_VSLB 2123 +#define PPC_VSLD 2124 +#define PPC_VSLDBI 2125 +#define PPC_VSLDOI 2126 +#define PPC_VSLH 2127 +#define PPC_VSLO 2128 +#define PPC_VSLQ 2129 +#define PPC_VSLV 2130 +#define PPC_VSLW 2131 +#define PPC_VSPLTB 2132 +#define PPC_VSPLTBs 2133 +#define PPC_VSPLTH 2134 +#define PPC_VSPLTHs 2135 +#define PPC_VSPLTISB 2136 +#define PPC_VSPLTISH 2137 +#define PPC_VSPLTISW 2138 +#define PPC_VSPLTW 2139 +#define PPC_VSR 2140 +#define PPC_VSRAB 2141 +#define PPC_VSRAD 2142 +#define PPC_VSRAH 2143 +#define PPC_VSRAQ 2144 +#define PPC_VSRAW 2145 +#define PPC_VSRB 2146 +#define PPC_VSRD 2147 +#define PPC_VSRDBI 2148 +#define PPC_VSRH 2149 +#define PPC_VSRO 2150 +#define PPC_VSRQ 2151 +#define PPC_VSRV 2152 +#define PPC_VSRW 2153 +#define PPC_VSTRIBL 2154 +#define PPC_VSTRIBL_rec 2155 +#define PPC_VSTRIBR 2156 +#define PPC_VSTRIBR_rec 2157 +#define PPC_VSTRIHL 2158 +#define PPC_VSTRIHL_rec 2159 +#define PPC_VSTRIHR 2160 +#define PPC_VSTRIHR_rec 2161 +#define PPC_VSUBCUQ 2162 +#define PPC_VSUBCUW 2163 +#define PPC_VSUBECUQ 2164 +#define PPC_VSUBEUQM 2165 +#define PPC_VSUBFP 2166 +#define PPC_VSUBSBS 2167 +#define PPC_VSUBSHS 2168 +#define PPC_VSUBSWS 2169 +#define PPC_VSUBUBM 2170 +#define PPC_VSUBUBS 2171 +#define PPC_VSUBUDM 2172 +#define PPC_VSUBUHM 2173 +#define PPC_VSUBUHS 2174 +#define PPC_VSUBUQM 2175 +#define PPC_VSUBUWM 2176 +#define PPC_VSUBUWS 2177 +#define PPC_VSUM2SWS 2178 +#define PPC_VSUM4SBS 2179 +#define PPC_VSUM4SHS 2180 +#define PPC_VSUM4UBS 2181 +#define PPC_VSUMSWS 2182 +#define PPC_VUPKHPX 2183 +#define PPC_VUPKHSB 2184 +#define PPC_VUPKHSH 2185 +#define PPC_VUPKHSW 2186 +#define PPC_VUPKLPX 2187 +#define PPC_VUPKLSB 2188 +#define PPC_VUPKLSH 2189 +#define PPC_VUPKLSW 2190 +#define PPC_VXOR 2191 +#define PPC_V_SET0 2192 +#define PPC_V_SET0B 2193 +#define PPC_V_SET0H 2194 +#define PPC_V_SETALLONES 2195 +#define PPC_V_SETALLONESB 2196 +#define PPC_V_SETALLONESH 2197 +#define PPC_WAIT 2198 +#define PPC_WRTEE 2199 +#define PPC_WRTEEI 2200 +#define PPC_XOR 2201 +#define PPC_XOR8 2202 +#define PPC_XOR8_rec 2203 +#define PPC_XORI 2204 +#define PPC_XORI8 2205 +#define PPC_XORIS 2206 +#define PPC_XORIS8 2207 +#define PPC_XOR_rec 2208 +#define PPC_XSABSDP 2209 +#define PPC_XSABSQP 2210 +#define PPC_XSADDDP 2211 +#define PPC_XSADDQP 2212 +#define PPC_XSADDQPO 2213 +#define PPC_XSADDSP 2214 +#define PPC_XSCMPEQDP 2215 +#define PPC_XSCMPEXPDP 2216 +#define PPC_XSCMPEXPQP 2217 +#define PPC_XSCMPGEDP 2218 +#define PPC_XSCMPGTDP 2219 +#define PPC_XSCMPODP 2220 +#define PPC_XSCMPOQP 2221 +#define PPC_XSCMPUDP 2222 +#define PPC_XSCMPUQP 2223 +#define PPC_XSCPSGNDP 2224 +#define PPC_XSCPSGNQP 2225 +#define PPC_XSCVDPHP 2226 +#define PPC_XSCVDPQP 2227 +#define PPC_XSCVDPSP 2228 +#define PPC_XSCVDPSPN 2229 +#define PPC_XSCVDPSXDS 2230 +#define PPC_XSCVDPSXDSs 2231 +#define PPC_XSCVDPSXWS 2232 +#define PPC_XSCVDPSXWSs 2233 +#define PPC_XSCVDPUXDS 2234 +#define PPC_XSCVDPUXDSs 2235 +#define PPC_XSCVDPUXWS 2236 +#define PPC_XSCVDPUXWSs 2237 +#define PPC_XSCVHPDP 2238 +#define PPC_XSCVQPDP 2239 +#define PPC_XSCVQPDPO 2240 +#define PPC_XSCVQPSDZ 2241 +#define PPC_XSCVQPSQZ 2242 +#define PPC_XSCVQPSWZ 2243 +#define PPC_XSCVQPUDZ 2244 +#define PPC_XSCVQPUQZ 2245 +#define PPC_XSCVQPUWZ 2246 +#define PPC_XSCVSDQP 2247 +#define PPC_XSCVSPDP 2248 +#define PPC_XSCVSPDPN 2249 +#define PPC_XSCVSQQP 2250 +#define PPC_XSCVSXDDP 2251 +#define PPC_XSCVSXDSP 2252 +#define PPC_XSCVUDQP 2253 +#define PPC_XSCVUQQP 2254 +#define PPC_XSCVUXDDP 2255 +#define PPC_XSCVUXDSP 2256 +#define PPC_XSDIVDP 2257 +#define PPC_XSDIVQP 2258 +#define PPC_XSDIVQPO 2259 +#define PPC_XSDIVSP 2260 +#define PPC_XSIEXPDP 2261 +#define PPC_XSIEXPQP 2262 +#define PPC_XSMADDADP 2263 +#define PPC_XSMADDASP 2264 +#define PPC_XSMADDMDP 2265 +#define PPC_XSMADDMSP 2266 +#define PPC_XSMADDQP 2267 +#define PPC_XSMADDQPO 2268 +#define PPC_XSMAXCDP 2269 +#define PPC_XSMAXDP 2270 +#define PPC_XSMAXJDP 2271 +#define PPC_XSMINCDP 2272 +#define PPC_XSMINDP 2273 +#define PPC_XSMINJDP 2274 +#define PPC_XSMSUBADP 2275 +#define PPC_XSMSUBASP 2276 +#define PPC_XSMSUBMDP 2277 +#define PPC_XSMSUBMSP 2278 +#define PPC_XSMSUBQP 2279 +#define PPC_XSMSUBQPO 2280 +#define PPC_XSMULDP 2281 +#define PPC_XSMULQP 2282 +#define PPC_XSMULQPO 2283 +#define PPC_XSMULSP 2284 +#define PPC_XSNABSDP 2285 +#define PPC_XSNABSQP 2286 +#define PPC_XSNEGDP 2287 +#define PPC_XSNEGQP 2288 +#define PPC_XSNMADDADP 2289 +#define PPC_XSNMADDASP 2290 +#define PPC_XSNMADDMDP 2291 +#define PPC_XSNMADDMSP 2292 +#define PPC_XSNMADDQP 2293 +#define PPC_XSNMADDQPO 2294 +#define PPC_XSNMSUBADP 2295 +#define PPC_XSNMSUBASP 2296 +#define PPC_XSNMSUBMDP 2297 +#define PPC_XSNMSUBMSP 2298 +#define PPC_XSNMSUBQP 2299 +#define PPC_XSNMSUBQPO 2300 +#define PPC_XSRDPI 2301 +#define PPC_XSRDPIC 2302 +#define PPC_XSRDPIM 2303 +#define PPC_XSRDPIP 2304 +#define PPC_XSRDPIZ 2305 +#define PPC_XSREDP 2306 +#define PPC_XSRESP 2307 +#define PPC_XSRQPI 2308 +#define PPC_XSRQPIX 2309 +#define PPC_XSRQPXP 2310 +#define PPC_XSRSP 2311 +#define PPC_XSRSQRTEDP 2312 +#define PPC_XSRSQRTESP 2313 +#define PPC_XSSQRTDP 2314 +#define PPC_XSSQRTQP 2315 +#define PPC_XSSQRTQPO 2316 +#define PPC_XSSQRTSP 2317 +#define PPC_XSSUBDP 2318 +#define PPC_XSSUBQP 2319 +#define PPC_XSSUBQPO 2320 +#define PPC_XSSUBSP 2321 +#define PPC_XSTDIVDP 2322 +#define PPC_XSTSQRTDP 2323 +#define PPC_XSTSTDCDP 2324 +#define PPC_XSTSTDCQP 2325 +#define PPC_XSTSTDCSP 2326 +#define PPC_XSXEXPDP 2327 +#define PPC_XSXEXPQP 2328 +#define PPC_XSXSIGDP 2329 +#define PPC_XSXSIGQP 2330 +#define PPC_XVABSDP 2331 +#define PPC_XVABSSP 2332 +#define PPC_XVADDDP 2333 +#define PPC_XVADDSP 2334 +#define PPC_XVBF16GER2 2335 +#define PPC_XVBF16GER2NN 2336 +#define PPC_XVBF16GER2NP 2337 +#define PPC_XVBF16GER2PN 2338 +#define PPC_XVBF16GER2PP 2339 +#define PPC_XVCMPEQDP 2340 +#define PPC_XVCMPEQDP_rec 2341 +#define PPC_XVCMPEQSP 2342 +#define PPC_XVCMPEQSP_rec 2343 +#define PPC_XVCMPGEDP 2344 +#define PPC_XVCMPGEDP_rec 2345 +#define PPC_XVCMPGESP 2346 +#define PPC_XVCMPGESP_rec 2347 +#define PPC_XVCMPGTDP 2348 +#define PPC_XVCMPGTDP_rec 2349 +#define PPC_XVCMPGTSP 2350 +#define PPC_XVCMPGTSP_rec 2351 +#define PPC_XVCPSGNDP 2352 +#define PPC_XVCPSGNSP 2353 +#define PPC_XVCVBF16SPN 2354 +#define PPC_XVCVDPSP 2355 +#define PPC_XVCVDPSXDS 2356 +#define PPC_XVCVDPSXWS 2357 +#define PPC_XVCVDPUXDS 2358 +#define PPC_XVCVDPUXWS 2359 +#define PPC_XVCVHPSP 2360 +#define PPC_XVCVSPBF16 2361 +#define PPC_XVCVSPDP 2362 +#define PPC_XVCVSPHP 2363 +#define PPC_XVCVSPSXDS 2364 +#define PPC_XVCVSPSXWS 2365 +#define PPC_XVCVSPUXDS 2366 +#define PPC_XVCVSPUXWS 2367 +#define PPC_XVCVSXDDP 2368 +#define PPC_XVCVSXDSP 2369 +#define PPC_XVCVSXWDP 2370 +#define PPC_XVCVSXWSP 2371 +#define PPC_XVCVUXDDP 2372 +#define PPC_XVCVUXDSP 2373 +#define PPC_XVCVUXWDP 2374 +#define PPC_XVCVUXWSP 2375 +#define PPC_XVDIVDP 2376 +#define PPC_XVDIVSP 2377 +#define PPC_XVF16GER2 2378 +#define PPC_XVF16GER2NN 2379 +#define PPC_XVF16GER2NP 2380 +#define PPC_XVF16GER2PN 2381 +#define PPC_XVF16GER2PP 2382 +#define PPC_XVF32GER 2383 +#define PPC_XVF32GERNN 2384 +#define PPC_XVF32GERNP 2385 +#define PPC_XVF32GERPN 2386 +#define PPC_XVF32GERPP 2387 +#define PPC_XVF64GER 2388 +#define PPC_XVF64GERNN 2389 +#define PPC_XVF64GERNP 2390 +#define PPC_XVF64GERPN 2391 +#define PPC_XVF64GERPP 2392 +#define PPC_XVI16GER2 2393 +#define PPC_XVI16GER2PP 2394 +#define PPC_XVI16GER2S 2395 +#define PPC_XVI16GER2SPP 2396 +#define PPC_XVI4GER8 2397 +#define PPC_XVI4GER8PP 2398 +#define PPC_XVI8GER4 2399 +#define PPC_XVI8GER4PP 2400 +#define PPC_XVI8GER4SPP 2401 +#define PPC_XVIEXPDP 2402 +#define PPC_XVIEXPSP 2403 +#define PPC_XVMADDADP 2404 +#define PPC_XVMADDASP 2405 +#define PPC_XVMADDMDP 2406 +#define PPC_XVMADDMSP 2407 +#define PPC_XVMAXDP 2408 +#define PPC_XVMAXSP 2409 +#define PPC_XVMINDP 2410 +#define PPC_XVMINSP 2411 +#define PPC_XVMSUBADP 2412 +#define PPC_XVMSUBASP 2413 +#define PPC_XVMSUBMDP 2414 +#define PPC_XVMSUBMSP 2415 +#define PPC_XVMULDP 2416 +#define PPC_XVMULSP 2417 +#define PPC_XVNABSDP 2418 +#define PPC_XVNABSSP 2419 +#define PPC_XVNEGDP 2420 +#define PPC_XVNEGSP 2421 +#define PPC_XVNMADDADP 2422 +#define PPC_XVNMADDASP 2423 +#define PPC_XVNMADDMDP 2424 +#define PPC_XVNMADDMSP 2425 +#define PPC_XVNMSUBADP 2426 +#define PPC_XVNMSUBASP 2427 +#define PPC_XVNMSUBMDP 2428 +#define PPC_XVNMSUBMSP 2429 +#define PPC_XVRDPI 2430 +#define PPC_XVRDPIC 2431 +#define PPC_XVRDPIM 2432 +#define PPC_XVRDPIP 2433 +#define PPC_XVRDPIZ 2434 +#define PPC_XVREDP 2435 +#define PPC_XVRESP 2436 +#define PPC_XVRSPI 2437 +#define PPC_XVRSPIC 2438 +#define PPC_XVRSPIM 2439 +#define PPC_XVRSPIP 2440 +#define PPC_XVRSPIZ 2441 +#define PPC_XVRSQRTEDP 2442 +#define PPC_XVRSQRTESP 2443 +#define PPC_XVSQRTDP 2444 +#define PPC_XVSQRTSP 2445 +#define PPC_XVSUBDP 2446 +#define PPC_XVSUBSP 2447 +#define PPC_XVTDIVDP 2448 +#define PPC_XVTDIVSP 2449 +#define PPC_XVTLSBB 2450 +#define PPC_XVTSQRTDP 2451 +#define PPC_XVTSQRTSP 2452 +#define PPC_XVTSTDCDP 2453 +#define PPC_XVTSTDCSP 2454 +#define PPC_XVXEXPDP 2455 +#define PPC_XVXEXPSP 2456 +#define PPC_XVXSIGDP 2457 +#define PPC_XVXSIGSP 2458 +#define PPC_XXBLENDVB 2459 +#define PPC_XXBLENDVD 2460 +#define PPC_XXBLENDVH 2461 +#define PPC_XXBLENDVW 2462 +#define PPC_XXBRD 2463 +#define PPC_XXBRH 2464 +#define PPC_XXBRQ 2465 +#define PPC_XXBRW 2466 +#define PPC_XXEVAL 2467 +#define PPC_XXEXTRACTUW 2468 +#define PPC_XXGENPCVBM 2469 +#define PPC_XXGENPCVDM 2470 +#define PPC_XXGENPCVHM 2471 +#define PPC_XXGENPCVWM 2472 +#define PPC_XXINSERTW 2473 +#define PPC_XXLAND 2474 +#define PPC_XXLANDC 2475 +#define PPC_XXLEQV 2476 +#define PPC_XXLEQVOnes 2477 +#define PPC_XXLNAND 2478 +#define PPC_XXLNOR 2479 +#define PPC_XXLOR 2480 +#define PPC_XXLORC 2481 +#define PPC_XXLORf 2482 +#define PPC_XXLXOR 2483 +#define PPC_XXLXORdpz 2484 +#define PPC_XXLXORspz 2485 +#define PPC_XXLXORz 2486 +#define PPC_XXMFACC 2487 +#define PPC_XXMRGHW 2488 +#define PPC_XXMRGLW 2489 +#define PPC_XXMTACC 2490 +#define PPC_XXPERM 2491 +#define PPC_XXPERMDI 2492 +#define PPC_XXPERMDIs 2493 +#define PPC_XXPERMR 2494 +#define PPC_XXPERMX 2495 +#define PPC_XXSEL 2496 +#define PPC_XXSETACCZ 2497 +#define PPC_XXSLDWI 2498 +#define PPC_XXSLDWIs 2499 +#define PPC_XXSPLTI32DX 2500 +#define PPC_XXSPLTIB 2501 +#define PPC_XXSPLTIDP 2502 +#define PPC_XXSPLTIW 2503 +#define PPC_XXSPLTW 2504 +#define PPC_XXSPLTWs 2505 +#define PPC_gBC 2506 +#define PPC_gBCA 2507 +#define PPC_gBCAat 2508 +#define PPC_gBCCTR 2509 +#define PPC_gBCCTRL 2510 +#define PPC_gBCL 2511 +#define PPC_gBCLA 2512 +#define PPC_gBCLAat 2513 +#define PPC_gBCLR 2514 +#define PPC_gBCLRL 2515 +#define PPC_gBCLat 2516 +#define PPC_gBCat 2517 +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_REGINFO_EXTRA +#undef GET_REGINFO_EXTRA + +// Subregister indices + +enum { + NoSubRegister, + PPC_sub_32, // 1 + PPC_sub_64, // 2 + PPC_sub_eq, // 3 + PPC_sub_gp8_x0, // 4 + PPC_sub_gp8_x1, // 5 + PPC_sub_gt, // 6 + PPC_sub_lt, // 7 + PPC_sub_pair0, // 8 + PPC_sub_pair1, // 9 + PPC_sub_un, // 10 + PPC_sub_vsx0, // 11 + PPC_sub_vsx1, // 12 + PPC_sub_vsx1_then_sub_64, // 13 + PPC_sub_pair1_then_sub_64, // 14 + PPC_sub_pair1_then_sub_vsx0, // 15 + PPC_sub_pair1_then_sub_vsx1, // 16 + PPC_sub_pair1_then_sub_vsx1_then_sub_64, // 17 + PPC_sub_gp8_x1_then_sub_32, // 18 + PPC_NUM_TARGET_SUBREGS +}; +#endif // GET_REGINFO_EXTRA + + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + + + +static const MCPhysReg PPCRegDiffLists[] = { + /* 0 */ 0, 0, + /* 2 */ 65037, 1, 1, 1, 0, + /* 7 */ 65497, 1, 1, 1, 0, + /* 12 */ 65501, 1, 1, 1, 0, + /* 17 */ 64891, 1, 0, + /* 20 */ 65083, 1, 0, + /* 23 */ 65149, 1, 0, + /* 26 */ 3, 0, + /* 28 */ 8, 0, + /* 30 */ 12, 0, + /* 32 */ 18, 0, + /* 34 */ 324, 65528, 65528, 24, 0, + /* 39 */ 65424, 32, 65505, 32, 0, + /* 44 */ 65425, 32, 65505, 32, 0, + /* 49 */ 65426, 32, 65505, 32, 0, + /* 54 */ 65427, 32, 65505, 32, 0, + /* 59 */ 65428, 32, 65505, 32, 0, + /* 64 */ 65429, 32, 65505, 32, 0, + /* 69 */ 65430, 32, 65505, 32, 0, + /* 74 */ 65431, 32, 65505, 32, 0, + /* 79 */ 65432, 32, 65505, 32, 0, + /* 84 */ 65433, 32, 65505, 32, 0, + /* 89 */ 65434, 32, 65505, 32, 0, + /* 94 */ 65435, 32, 65505, 32, 0, + /* 99 */ 65436, 32, 65505, 32, 0, + /* 104 */ 65437, 32, 65505, 32, 0, + /* 109 */ 65438, 32, 65505, 32, 0, + /* 114 */ 65439, 32, 65505, 32, 0, + /* 119 */ 32, 200, 49, 0, + /* 123 */ 32, 200, 50, 0, + /* 127 */ 32, 200, 51, 0, + /* 131 */ 32, 200, 52, 0, + /* 135 */ 32, 200, 53, 0, + /* 139 */ 32, 200, 54, 0, + /* 143 */ 32, 200, 55, 0, + /* 147 */ 32, 200, 56, 0, + /* 151 */ 32, 200, 57, 0, + /* 155 */ 32, 200, 58, 0, + /* 159 */ 32, 200, 59, 0, + /* 163 */ 32, 200, 60, 0, + /* 167 */ 32, 200, 61, 0, + /* 171 */ 32, 200, 62, 0, + /* 175 */ 32, 200, 63, 0, + /* 179 */ 32, 200, 64, 0, + /* 183 */ 32, 200, 65, 0, + /* 187 */ 73, 0, + /* 189 */ 65504, 96, 0, + /* 192 */ 65504, 97, 0, + /* 195 */ 65504, 98, 0, + /* 198 */ 65504, 99, 0, + /* 201 */ 65504, 100, 0, + /* 204 */ 65504, 101, 0, + /* 207 */ 65504, 102, 0, + /* 210 */ 65504, 103, 0, + /* 213 */ 65504, 104, 0, + /* 216 */ 65504, 105, 0, + /* 219 */ 65504, 106, 0, + /* 222 */ 65504, 107, 0, + /* 225 */ 65504, 108, 0, + /* 228 */ 65504, 109, 0, + /* 231 */ 65504, 110, 0, + /* 234 */ 65504, 111, 0, + /* 237 */ 65504, 112, 0, + /* 240 */ 170, 16, 65308, 116, 0, + /* 245 */ 170, 17, 65308, 116, 0, + /* 250 */ 170, 17, 65309, 116, 0, + /* 255 */ 170, 18, 65309, 116, 0, + /* 260 */ 170, 19, 65309, 116, 0, + /* 265 */ 170, 19, 65310, 116, 0, + /* 270 */ 170, 20, 65310, 116, 0, + /* 275 */ 170, 21, 65310, 116, 0, + /* 280 */ 170, 21, 65311, 116, 0, + /* 285 */ 170, 22, 65311, 116, 0, + /* 290 */ 170, 23, 65311, 116, 0, + /* 295 */ 170, 23, 65312, 116, 0, + /* 300 */ 170, 24, 65312, 116, 0, + /* 305 */ 170, 25, 65312, 116, 0, + /* 310 */ 170, 25, 65313, 116, 0, + /* 315 */ 170, 26, 65313, 116, 0, + /* 320 */ 170, 27, 65313, 116, 0, + /* 325 */ 170, 27, 65314, 116, 0, + /* 330 */ 170, 28, 65314, 116, 0, + /* 335 */ 170, 29, 65314, 116, 0, + /* 340 */ 170, 29, 65315, 116, 0, + /* 345 */ 170, 30, 65315, 116, 0, + /* 350 */ 170, 31, 65315, 116, 0, + /* 355 */ 170, 31, 65316, 116, 0, + /* 360 */ 170, 32, 65316, 116, 0, + /* 365 */ 317, 0, + /* 367 */ 64172, 0, + /* 369 */ 64201, 0, + /* 371 */ 64234, 0, + /* 373 */ 64267, 0, + /* 375 */ 65204, 0, + /* 377 */ 65212, 0, + /* 379 */ 65219, 0, + /* 381 */ 65220, 0, + /* 383 */ 65228, 0, + /* 385 */ 65471, 65304, 233, 65304, 0, + /* 390 */ 65472, 65304, 233, 65304, 0, + /* 395 */ 65473, 65304, 233, 65304, 0, + /* 400 */ 65474, 65304, 233, 65304, 0, + /* 405 */ 65475, 65304, 233, 65304, 0, + /* 410 */ 65476, 65304, 233, 65304, 0, + /* 415 */ 65477, 65304, 233, 65304, 0, + /* 420 */ 65478, 65304, 233, 65304, 0, + /* 425 */ 65479, 65304, 233, 65304, 0, + /* 430 */ 65480, 65304, 233, 65304, 0, + /* 435 */ 65481, 65304, 233, 65304, 0, + /* 440 */ 65482, 65304, 233, 65304, 0, + /* 445 */ 65483, 65304, 233, 65304, 0, + /* 450 */ 65484, 65304, 233, 65304, 0, + /* 455 */ 65485, 65304, 233, 65304, 0, + /* 460 */ 65486, 65304, 233, 65304, 0, + /* 465 */ 65316, 0, + /* 467 */ 65346, 0, + /* 469 */ 65504, 65366, 171, 65366, 0, + /* 474 */ 104, 65504, 65366, 171, 65366, 202, 65505, 65366, 171, 65366, 0, + /* 485 */ 220, 65504, 65366, 171, 65366, 202, 65505, 65366, 171, 65366, 0, + /* 496 */ 65506, 65366, 171, 65366, 0, + /* 501 */ 105, 65506, 65366, 171, 65366, 200, 65507, 65366, 171, 65366, 0, + /* 512 */ 221, 65506, 65366, 171, 65366, 200, 65507, 65366, 171, 65366, 0, + /* 523 */ 65508, 65366, 171, 65366, 0, + /* 528 */ 106, 65508, 65366, 171, 65366, 198, 65509, 65366, 171, 65366, 0, + /* 539 */ 222, 65508, 65366, 171, 65366, 198, 65509, 65366, 171, 65366, 0, + /* 550 */ 65510, 65366, 171, 65366, 0, + /* 555 */ 107, 65510, 65366, 171, 65366, 196, 65511, 65366, 171, 65366, 0, + /* 566 */ 223, 65510, 65366, 171, 65366, 196, 65511, 65366, 171, 65366, 0, + /* 577 */ 65512, 65366, 171, 65366, 0, + /* 582 */ 108, 65512, 65366, 171, 65366, 194, 65513, 65366, 171, 65366, 0, + /* 593 */ 224, 65512, 65366, 171, 65366, 194, 65513, 65366, 171, 65366, 0, + /* 604 */ 65514, 65366, 171, 65366, 0, + /* 609 */ 109, 65514, 65366, 171, 65366, 192, 65515, 65366, 171, 65366, 0, + /* 620 */ 225, 65514, 65366, 171, 65366, 192, 65515, 65366, 171, 65366, 0, + /* 631 */ 65516, 65366, 171, 65366, 0, + /* 636 */ 110, 65516, 65366, 171, 65366, 190, 65517, 65366, 171, 65366, 0, + /* 647 */ 226, 65516, 65366, 171, 65366, 190, 65517, 65366, 171, 65366, 0, + /* 658 */ 65518, 65366, 171, 65366, 0, + /* 663 */ 111, 65518, 65366, 171, 65366, 188, 65519, 65366, 171, 65366, 0, + /* 674 */ 227, 65518, 65366, 171, 65366, 188, 65519, 65366, 171, 65366, 0, + /* 685 */ 65412, 0, + /* 687 */ 65474, 0, + /* 689 */ 65476, 0, + /* 691 */ 65479, 0, + /* 693 */ 65504, 0, + /* 695 */ 65508, 0, + /* 697 */ 65516, 0, + /* 699 */ 65518, 0, + /* 701 */ 65535, 0, +}; + +static const uint16_t PPCSubRegIdxLists[] = { + /* 0 */ 1, 0, + /* 2 */ 2, 0, + /* 4 */ 7, 6, 3, 10, 0, + /* 9 */ 11, 2, 12, 13, 0, + /* 14 */ 8, 11, 2, 12, 13, 9, 15, 14, 16, 17, 0, + /* 25 */ 4, 1, 5, 18, 0, +}; + + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char PPCRegStrings[] = { + /* 0 */ "VF10\0" + /* 5 */ "VSL10\0" + /* 11 */ "R10\0" + /* 15 */ "S10\0" + /* 19 */ "V10\0" + /* 23 */ "X10\0" + /* 27 */ "G8p10\0" + /* 33 */ "VSRp10\0" + /* 40 */ "VF20\0" + /* 45 */ "VSL20\0" + /* 51 */ "R20\0" + /* 55 */ "S20\0" + /* 59 */ "V20\0" + /* 63 */ "X20\0" + /* 67 */ "VSRp20\0" + /* 74 */ "VF30\0" + /* 79 */ "VSL30\0" + /* 85 */ "R30\0" + /* 89 */ "S30\0" + /* 93 */ "V30\0" + /* 97 */ "X30\0" + /* 101 */ "VSRp30\0" + /* 108 */ "VSX40\0" + /* 114 */ "VSX50\0" + /* 120 */ "VSX60\0" + /* 126 */ "UACC0\0" + /* 132 */ "VF0\0" + /* 136 */ "VSL0\0" + /* 141 */ "CR0\0" + /* 145 */ "S0\0" + /* 148 */ "V0\0" + /* 151 */ "X0\0" + /* 154 */ "G8p0\0" + /* 159 */ "VSRp0\0" + /* 165 */ "VF11\0" + /* 170 */ "VSL11\0" + /* 176 */ "R11\0" + /* 180 */ "S11\0" + /* 184 */ "V11\0" + /* 188 */ "X11\0" + /* 192 */ "G8p11\0" + /* 198 */ "VSRp11\0" + /* 205 */ "VF21\0" + /* 210 */ "VSL21\0" + /* 216 */ "R21\0" + /* 220 */ "S21\0" + /* 224 */ "V21\0" + /* 228 */ "X21\0" + /* 232 */ "VSRp21\0" + /* 239 */ "VF31\0" + /* 244 */ "VSL31\0" + /* 250 */ "R31\0" + /* 254 */ "S31\0" + /* 258 */ "V31\0" + /* 262 */ "X31\0" + /* 266 */ "VSRp31\0" + /* 273 */ "VSX41\0" + /* 279 */ "VSX51\0" + /* 285 */ "VSX61\0" + /* 291 */ "UACC1\0" + /* 297 */ "VF1\0" + /* 301 */ "VSL1\0" + /* 306 */ "CR1\0" + /* 310 */ "S1\0" + /* 313 */ "V1\0" + /* 316 */ "X1\0" + /* 319 */ "G8p1\0" + /* 324 */ "VSRp1\0" + /* 330 */ "VF12\0" + /* 335 */ "VSL12\0" + /* 341 */ "R12\0" + /* 345 */ "S12\0" + /* 349 */ "V12\0" + /* 353 */ "X12\0" + /* 357 */ "G8p12\0" + /* 363 */ "VSRp12\0" + /* 370 */ "VF22\0" + /* 375 */ "VSL22\0" + /* 381 */ "R22\0" + /* 385 */ "S22\0" + /* 389 */ "V22\0" + /* 393 */ "X22\0" + /* 397 */ "VSRp22\0" + /* 404 */ "VSX32\0" + /* 410 */ "VSX42\0" + /* 416 */ "VSX52\0" + /* 422 */ "VSX62\0" + /* 428 */ "UACC2\0" + /* 434 */ "VF2\0" + /* 438 */ "VSL2\0" + /* 443 */ "CR2\0" + /* 447 */ "S2\0" + /* 450 */ "V2\0" + /* 453 */ "X2\0" + /* 456 */ "G8p2\0" + /* 461 */ "VSRp2\0" + /* 467 */ "VF13\0" + /* 472 */ "VSL13\0" + /* 478 */ "R13\0" + /* 482 */ "S13\0" + /* 486 */ "V13\0" + /* 490 */ "X13\0" + /* 494 */ "G8p13\0" + /* 500 */ "VSRp13\0" + /* 507 */ "VF23\0" + /* 512 */ "VSL23\0" + /* 518 */ "R23\0" + /* 522 */ "S23\0" + /* 526 */ "V23\0" + /* 530 */ "X23\0" + /* 534 */ "VSRp23\0" + /* 541 */ "VSX33\0" + /* 547 */ "VSX43\0" + /* 553 */ "VSX53\0" + /* 559 */ "VSX63\0" + /* 565 */ "UACC3\0" + /* 571 */ "VF3\0" + /* 575 */ "VSL3\0" + /* 580 */ "CR3\0" + /* 584 */ "S3\0" + /* 587 */ "V3\0" + /* 590 */ "X3\0" + /* 593 */ "G8p3\0" + /* 598 */ "VSRp3\0" + /* 604 */ "VF14\0" + /* 609 */ "VSL14\0" + /* 615 */ "R14\0" + /* 619 */ "S14\0" + /* 623 */ "V14\0" + /* 627 */ "X14\0" + /* 631 */ "G8p14\0" + /* 637 */ "VSRp14\0" + /* 644 */ "VF24\0" + /* 649 */ "VSL24\0" + /* 655 */ "R24\0" + /* 659 */ "S24\0" + /* 663 */ "V24\0" + /* 667 */ "X24\0" + /* 671 */ "VSRp24\0" + /* 678 */ "VSX34\0" + /* 684 */ "VSX44\0" + /* 690 */ "VSX54\0" + /* 696 */ "UACC4\0" + /* 702 */ "VF4\0" + /* 706 */ "VSL4\0" + /* 711 */ "CR4\0" + /* 715 */ "S4\0" + /* 718 */ "V4\0" + /* 721 */ "X4\0" + /* 724 */ "G8p4\0" + /* 729 */ "VSRp4\0" + /* 735 */ "VF15\0" + /* 740 */ "VSL15\0" + /* 746 */ "R15\0" + /* 750 */ "S15\0" + /* 754 */ "V15\0" + /* 758 */ "X15\0" + /* 762 */ "G8p15\0" + /* 768 */ "VSRp15\0" + /* 775 */ "VF25\0" + /* 780 */ "VSL25\0" + /* 786 */ "R25\0" + /* 790 */ "S25\0" + /* 794 */ "V25\0" + /* 798 */ "X25\0" + /* 802 */ "VSRp25\0" + /* 809 */ "VSX35\0" + /* 815 */ "VSX45\0" + /* 821 */ "VSX55\0" + /* 827 */ "UACC5\0" + /* 833 */ "VF5\0" + /* 837 */ "VSL5\0" + /* 842 */ "CR5\0" + /* 846 */ "S5\0" + /* 849 */ "V5\0" + /* 852 */ "X5\0" + /* 855 */ "G8p5\0" + /* 860 */ "VSRp5\0" + /* 866 */ "VF16\0" + /* 871 */ "VSL16\0" + /* 877 */ "R16\0" + /* 881 */ "S16\0" + /* 885 */ "V16\0" + /* 889 */ "X16\0" + /* 893 */ "VSRp16\0" + /* 900 */ "VF26\0" + /* 905 */ "VSL26\0" + /* 911 */ "R26\0" + /* 915 */ "S26\0" + /* 919 */ "V26\0" + /* 923 */ "X26\0" + /* 927 */ "VSRp26\0" + /* 934 */ "VSX36\0" + /* 940 */ "VSX46\0" + /* 946 */ "VSX56\0" + /* 952 */ "UACC6\0" + /* 958 */ "VF6\0" + /* 962 */ "VSL6\0" + /* 967 */ "CR6\0" + /* 971 */ "S6\0" + /* 974 */ "V6\0" + /* 977 */ "X6\0" + /* 980 */ "G8p6\0" + /* 985 */ "VSRp6\0" + /* 991 */ "VF17\0" + /* 996 */ "VSL17\0" + /* 1002 */ "R17\0" + /* 1006 */ "S17\0" + /* 1010 */ "V17\0" + /* 1014 */ "X17\0" + /* 1018 */ "VSRp17\0" + /* 1025 */ "VF27\0" + /* 1030 */ "VSL27\0" + /* 1036 */ "R27\0" + /* 1040 */ "S27\0" + /* 1044 */ "V27\0" + /* 1048 */ "X27\0" + /* 1052 */ "VSRp27\0" + /* 1059 */ "VSX37\0" + /* 1065 */ "VSX47\0" + /* 1071 */ "VSX57\0" + /* 1077 */ "UACC7\0" + /* 1083 */ "VF7\0" + /* 1087 */ "VSL7\0" + /* 1092 */ "CR7\0" + /* 1096 */ "S7\0" + /* 1099 */ "V7\0" + /* 1102 */ "X7\0" + /* 1105 */ "G8p7\0" + /* 1110 */ "VSRp7\0" + /* 1116 */ "VF18\0" + /* 1121 */ "VSL18\0" + /* 1127 */ "R18\0" + /* 1131 */ "S18\0" + /* 1135 */ "V18\0" + /* 1139 */ "X18\0" + /* 1143 */ "VSRp18\0" + /* 1150 */ "VF28\0" + /* 1155 */ "VSL28\0" + /* 1161 */ "R28\0" + /* 1165 */ "S28\0" + /* 1169 */ "V28\0" + /* 1173 */ "X28\0" + /* 1177 */ "VSRp28\0" + /* 1184 */ "VSX38\0" + /* 1190 */ "VSX48\0" + /* 1196 */ "VSX58\0" + /* 1202 */ "VF8\0" + /* 1206 */ "VSL8\0" + /* 1211 */ "ZERO8\0" + /* 1217 */ "BP8\0" + /* 1221 */ "FP8\0" + /* 1225 */ "LR8\0" + /* 1229 */ "CTR8\0" + /* 1234 */ "S8\0" + /* 1237 */ "V8\0" + /* 1240 */ "X8\0" + /* 1243 */ "G8p8\0" + /* 1248 */ "VSRp8\0" + /* 1254 */ "VF19\0" + /* 1259 */ "VSL19\0" + /* 1265 */ "R19\0" + /* 1269 */ "S19\0" + /* 1273 */ "V19\0" + /* 1277 */ "X19\0" + /* 1281 */ "VSRp19\0" + /* 1288 */ "VF29\0" + /* 1293 */ "VSL29\0" + /* 1299 */ "R29\0" + /* 1303 */ "S29\0" + /* 1307 */ "V29\0" + /* 1311 */ "X29\0" + /* 1315 */ "VSRp29\0" + /* 1322 */ "VSX39\0" + /* 1328 */ "VSX49\0" + /* 1334 */ "VSX59\0" + /* 1340 */ "VF9\0" + /* 1344 */ "VSL9\0" + /* 1349 */ "R9\0" + /* 1352 */ "S9\0" + /* 1355 */ "V9\0" + /* 1358 */ "X9\0" + /* 1361 */ "G8p9\0" + /* 1366 */ "VSRp9\0" + /* 1372 */ "VRSAVE\0" + /* 1379 */ "RM\0" + /* 1382 */ "CR0UN\0" + /* 1388 */ "CR1UN\0" + /* 1394 */ "CR2UN\0" + /* 1400 */ "CR3UN\0" + /* 1406 */ "CR4UN\0" + /* 1412 */ "CR5UN\0" + /* 1418 */ "CR6UN\0" + /* 1424 */ "CR7UN\0" + /* 1430 */ "ZERO\0" + /* 1435 */ "BP\0" + /* 1438 */ "FP\0" + /* 1441 */ "CR0EQ\0" + /* 1447 */ "CR1EQ\0" + /* 1453 */ "CR2EQ\0" + /* 1459 */ "CR3EQ\0" + /* 1465 */ "CR4EQ\0" + /* 1471 */ "CR5EQ\0" + /* 1477 */ "CR6EQ\0" + /* 1483 */ "CR7EQ\0" + /* 1489 */ "SPEFSCR\0" + /* 1497 */ "XER\0" + /* 1501 */ "LR\0" + /* 1504 */ "CTR\0" + /* 1508 */ "CR0GT\0" + /* 1514 */ "CR1GT\0" + /* 1520 */ "CR2GT\0" + /* 1526 */ "CR3GT\0" + /* 1532 */ "CR4GT\0" + /* 1538 */ "CR5GT\0" + /* 1544 */ "CR6GT\0" + /* 1550 */ "CR7GT\0" + /* 1556 */ "CR0LT\0" + /* 1562 */ "CR1LT\0" + /* 1568 */ "CR2LT\0" + /* 1574 */ "CR3LT\0" + /* 1580 */ "CR4LT\0" + /* 1586 */ "CR5LT\0" + /* 1592 */ "CR6LT\0" + /* 1598 */ "CR7LT\0" + /* 1604 */ "CARRY\0" +}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterDesc PPCRegDesc[] = { // Descriptors + { 4, 0, 0, 0, 0, 0 }, + { 1435, 1, 32, 1, 11217, 512 }, + { 1604, 1, 1, 1, 11217, 265 }, + { 1504, 1, 1, 1, 11217, 3 }, + { 1438, 1, 153, 1, 11217, 148 }, + { 1501, 1, 1, 1, 11217, 3 }, + { 1379, 1, 1, 1, 11217, 148 }, + { 1489, 1, 1, 1, 11217, 16 }, + { 1372, 1, 1, 1, 11217, 3 }, + { 1497, 1, 1, 1, 10999, 212 }, + { 1430, 1, 365, 1, 10999, 25 }, + { 127, 485, 1, 14, 196, 0 }, + { 292, 512, 1, 14, 196, 214 }, + { 429, 539, 1, 14, 196, 479 }, + { 566, 566, 1, 14, 196, 5 }, + { 697, 593, 1, 14, 196, 497 }, + { 828, 620, 1, 14, 196, 514 }, + { 953, 647, 1, 14, 196, 145 }, + { 1078, 674, 1, 14, 196, 465 }, + { 1217, 699, 1, 0, 0, 37 }, + { 141, 34, 1, 4, 116, 470 }, + { 306, 34, 1, 4, 116, 492 }, + { 443, 34, 1, 4, 116, 460 }, + { 580, 34, 1, 4, 116, 145 }, + { 711, 34, 1, 4, 116, 145 }, + { 842, 34, 1, 4, 116, 44 }, + { 967, 34, 1, 4, 116, 237 }, + { 1092, 34, 1, 4, 116, 52 }, + { 1229, 1, 1, 1, 2992, 148 }, + { 133, 1, 360, 1, 11153, 384 }, + { 298, 1, 355, 1, 11153, 13 }, + { 435, 1, 350, 1, 11153, 382 }, + { 572, 1, 345, 1, 11153, 3 }, + { 703, 1, 345, 1, 11153, 3 }, + { 834, 1, 340, 1, 11153, 150 }, + { 959, 1, 335, 1, 11153, 148 }, + { 1084, 1, 330, 1, 11153, 71 }, + { 1203, 1, 330, 1, 11153, 388 }, + { 1341, 1, 325, 1, 11153, 3 }, + { 1, 1, 320, 1, 11153, 386 }, + { 166, 1, 315, 1, 11153, 258 }, + { 331, 1, 315, 1, 11153, 148 }, + { 468, 1, 310, 1, 11153, 71 }, + { 605, 1, 305, 1, 11153, 3 }, + { 736, 1, 300, 1, 11153, 120 }, + { 867, 1, 300, 1, 11153, 148 }, + { 992, 1, 295, 1, 11153, 3 }, + { 1117, 1, 290, 1, 11153, 87 }, + { 1255, 1, 285, 1, 11153, 3 }, + { 41, 1, 285, 1, 11153, 267 }, + { 206, 1, 280, 1, 11153, 510 }, + { 371, 1, 275, 1, 11153, 13 }, + { 508, 1, 270, 1, 11153, 148 }, + { 645, 1, 270, 1, 11153, 23 }, + { 776, 1, 265, 1, 11153, 390 }, + { 901, 1, 260, 1, 11153, 3 }, + { 1026, 1, 255, 1, 11153, 407 }, + { 1151, 1, 255, 1, 11153, 228 }, + { 1289, 1, 250, 1, 11153, 3 }, + { 75, 1, 245, 1, 11153, 148 }, + { 240, 1, 240, 1, 11153, 198 }, + { 1221, 691, 1, 0, 416, 148 }, + { 1225, 1, 1, 1, 481, 71 }, + { 142, 1, 183, 1, 481, 290 }, + { 307, 1, 179, 1, 481, 292 }, + { 444, 1, 179, 1, 481, 148 }, + { 581, 1, 175, 1, 481, 148 }, + { 712, 1, 175, 1, 481, 296 }, + { 843, 1, 171, 1, 481, 3 }, + { 968, 1, 171, 1, 481, 510 }, + { 1093, 1, 167, 1, 481, 131 }, + { 1226, 1, 167, 1, 481, 16 }, + { 1349, 1, 163, 1, 481, 294 }, + { 11, 1, 163, 1, 481, 3 }, + { 176, 1, 159, 1, 481, 23 }, + { 341, 1, 159, 1, 481, 148 }, + { 478, 1, 155, 1, 481, 148 }, + { 615, 1, 155, 1, 481, 23 }, + { 746, 1, 151, 1, 481, 3 }, + { 877, 1, 151, 1, 481, 510 }, + { 1002, 1, 147, 1, 481, 3 }, + { 1127, 1, 147, 1, 481, 148 }, + { 1265, 1, 143, 1, 481, 60 }, + { 51, 1, 143, 1, 481, 39 }, + { 216, 1, 139, 1, 481, 3 }, + { 381, 1, 139, 1, 481, 288 }, + { 518, 1, 135, 1, 481, 164 }, + { 655, 1, 135, 1, 481, 184 }, + { 786, 1, 131, 1, 481, 3 }, + { 911, 1, 131, 1, 481, 162 }, + { 1036, 1, 127, 1, 481, 182 }, + { 1161, 1, 127, 1, 481, 148 }, + { 1299, 1, 123, 1, 481, 13 }, + { 85, 1, 123, 1, 481, 166 }, + { 250, 1, 119, 1, 481, 212 }, + { 145, 693, 1, 0, 11153, 134 }, + { 310, 693, 1, 0, 11153, 186 }, + { 447, 693, 1, 0, 11153, 519 }, + { 584, 693, 1, 0, 11153, 190 }, + { 715, 693, 1, 0, 11153, 519 }, + { 846, 693, 1, 0, 11153, 376 }, + { 971, 693, 1, 0, 11153, 3 }, + { 1096, 693, 1, 0, 11153, 134 }, + { 1234, 693, 1, 0, 11153, 148 }, + { 1352, 693, 1, 0, 11153, 378 }, + { 15, 693, 1, 0, 11153, 188 }, + { 180, 693, 1, 0, 11153, 134 }, + { 345, 693, 1, 0, 11153, 409 }, + { 482, 693, 1, 0, 11153, 148 }, + { 619, 693, 1, 0, 11153, 134 }, + { 750, 693, 1, 0, 11153, 380 }, + { 881, 693, 1, 0, 11153, 403 }, + { 1006, 693, 1, 0, 11153, 143 }, + { 1131, 693, 1, 0, 11153, 134 }, + { 1269, 693, 1, 0, 11153, 148 }, + { 55, 693, 1, 0, 11153, 148 }, + { 220, 693, 1, 0, 11153, 148 }, + { 385, 693, 1, 0, 11153, 154 }, + { 522, 693, 1, 0, 11153, 202 }, + { 659, 693, 1, 0, 11153, 3 }, + { 790, 693, 1, 0, 11153, 204 }, + { 915, 693, 1, 0, 11153, 200 }, + { 1040, 693, 1, 0, 11153, 458 }, + { 1165, 693, 1, 0, 11153, 206 }, + { 1303, 693, 1, 0, 11153, 122 }, + { 89, 693, 1, 0, 11153, 405 }, + { 254, 693, 1, 0, 11153, 210 }, + { 126, 474, 1, 14, 36, 77 }, + { 291, 501, 1, 14, 36, 396 }, + { 428, 528, 1, 14, 36, 82 }, + { 565, 555, 1, 14, 36, 232 }, + { 696, 582, 1, 14, 36, 145 }, + { 827, 609, 1, 14, 36, 281 }, + { 952, 636, 1, 14, 36, 145 }, + { 1077, 663, 1, 14, 36, 223 }, + { 148, 42, 238, 2, 11121, 3 }, + { 313, 42, 235, 2, 11121, 124 }, + { 450, 42, 235, 2, 11121, 392 }, + { 587, 42, 232, 2, 11121, 3 }, + { 718, 42, 232, 2, 11121, 176 }, + { 849, 42, 229, 2, 11121, 148 }, + { 974, 42, 229, 2, 11121, 148 }, + { 1099, 42, 226, 2, 11121, 148 }, + { 1237, 42, 226, 2, 11121, 148 }, + { 1355, 42, 223, 2, 11121, 475 }, + { 19, 42, 223, 2, 11121, 148 }, + { 184, 42, 220, 2, 11121, 477 }, + { 349, 42, 220, 2, 11121, 23 }, + { 486, 42, 217, 2, 11121, 230 }, + { 623, 42, 217, 2, 11121, 286 }, + { 754, 42, 214, 2, 11121, 212 }, + { 885, 42, 214, 2, 11121, 134 }, + { 1010, 42, 211, 2, 11121, 401 }, + { 1135, 42, 211, 2, 11121, 160 }, + { 1273, 42, 208, 2, 11121, 510 }, + { 59, 42, 208, 2, 11121, 484 }, + { 224, 42, 205, 2, 11121, 21 }, + { 389, 42, 205, 2, 11121, 158 }, + { 526, 42, 202, 2, 11121, 148 }, + { 663, 42, 202, 2, 11121, 486 }, + { 794, 42, 199, 2, 11121, 3 }, + { 919, 42, 199, 2, 11121, 212 }, + { 1044, 42, 196, 2, 11121, 508 }, + { 1169, 42, 196, 2, 11121, 242 }, + { 1307, 42, 193, 2, 11121, 148 }, + { 93, 42, 193, 2, 11121, 91 }, + { 258, 42, 190, 2, 11121, 89 }, + { 132, 1, 237, 1, 11025, 244 }, + { 297, 1, 234, 1, 11025, 27 }, + { 434, 1, 234, 1, 11025, 3 }, + { 571, 1, 231, 1, 11025, 219 }, + { 702, 1, 231, 1, 11025, 13 }, + { 833, 1, 228, 1, 11025, 246 }, + { 958, 1, 228, 1, 11025, 248 }, + { 1083, 1, 225, 1, 11025, 510 }, + { 1202, 1, 225, 1, 11025, 3 }, + { 1340, 1, 222, 1, 11025, 148 }, + { 0, 1, 222, 1, 11025, 3 }, + { 165, 1, 219, 1, 11025, 75 }, + { 330, 1, 219, 1, 11025, 131 }, + { 467, 1, 216, 1, 11025, 252 }, + { 604, 1, 216, 1, 11025, 148 }, + { 735, 1, 213, 1, 11025, 250 }, + { 866, 1, 213, 1, 11025, 131 }, + { 991, 1, 210, 1, 11025, 254 }, + { 1116, 1, 210, 1, 11025, 3 }, + { 1254, 1, 207, 1, 11025, 148 }, + { 40, 1, 207, 1, 11025, 116 }, + { 205, 1, 204, 1, 11025, 3 }, + { 370, 1, 204, 1, 11025, 148 }, + { 507, 1, 201, 1, 11025, 148 }, + { 644, 1, 201, 1, 11025, 148 }, + { 775, 1, 198, 1, 11025, 256 }, + { 900, 1, 198, 1, 11025, 3 }, + { 1025, 1, 195, 1, 11025, 194 }, + { 1150, 1, 195, 1, 11025, 190 }, + { 1288, 1, 192, 1, 11025, 192 }, + { 74, 1, 192, 1, 11025, 519 }, + { 239, 1, 189, 1, 11025, 519 }, + { 136, 472, 361, 2, 7473, 196 }, + { 301, 472, 356, 2, 7473, 316 }, + { 438, 472, 351, 2, 7473, 3 }, + { 575, 472, 346, 2, 7473, 306 }, + { 706, 472, 346, 2, 7473, 131 }, + { 837, 472, 341, 2, 7473, 3 }, + { 962, 472, 336, 2, 7473, 148 }, + { 1087, 472, 331, 2, 7473, 302 }, + { 1206, 472, 331, 2, 7473, 3 }, + { 1344, 472, 326, 2, 7473, 310 }, + { 5, 472, 321, 2, 7473, 3 }, + { 170, 472, 316, 2, 7473, 304 }, + { 335, 472, 316, 2, 7473, 178 }, + { 472, 472, 311, 2, 7473, 308 }, + { 609, 472, 306, 2, 7473, 312 }, + { 740, 472, 301, 2, 7473, 71 }, + { 871, 472, 301, 2, 7473, 260 }, + { 996, 472, 296, 2, 7473, 208 }, + { 1121, 472, 291, 2, 7473, 442 }, + { 1259, 472, 286, 2, 7473, 314 }, + { 45, 472, 286, 2, 7473, 510 }, + { 210, 472, 281, 2, 7473, 148 }, + { 375, 472, 276, 2, 7473, 131 }, + { 512, 472, 271, 2, 7473, 134 }, + { 649, 472, 271, 2, 7473, 131 }, + { 780, 472, 266, 2, 7473, 298 }, + { 905, 472, 261, 2, 7473, 3 }, + { 1030, 472, 256, 2, 7473, 318 }, + { 1155, 472, 256, 2, 7473, 323 }, + { 1293, 472, 251, 2, 7473, 300 }, + { 79, 472, 246, 2, 7473, 170 }, + { 244, 472, 241, 2, 7473, 436 }, + { 159, 469, 357, 9, 322, 2 }, + { 324, 480, 342, 9, 322, 320 }, + { 461, 496, 342, 9, 322, 502 }, + { 598, 507, 327, 9, 322, 147 }, + { 729, 523, 327, 9, 322, 41 }, + { 860, 534, 312, 9, 322, 101 }, + { 985, 550, 312, 9, 322, 328 }, + { 1110, 561, 297, 9, 322, 142 }, + { 1248, 577, 297, 9, 322, 142 }, + { 1366, 588, 282, 9, 322, 334 }, + { 33, 604, 282, 9, 322, 331 }, + { 198, 615, 267, 9, 322, 133 }, + { 363, 631, 267, 9, 322, 15 }, + { 500, 642, 252, 9, 322, 46 }, + { 637, 658, 252, 9, 322, 325 }, + { 768, 669, 242, 9, 322, 110 }, + { 893, 39, 1, 9, 370, 147 }, + { 1018, 44, 1, 9, 370, 505 }, + { 1143, 49, 1, 9, 370, 57 }, + { 1281, 54, 1, 9, 370, 142 }, + { 67, 59, 1, 9, 370, 337 }, + { 232, 64, 1, 9, 370, 2 }, + { 397, 69, 1, 9, 370, 46 }, + { 534, 74, 1, 9, 370, 340 }, + { 671, 79, 1, 9, 370, 18 }, + { 802, 84, 1, 9, 370, 343 }, + { 927, 89, 1, 9, 370, 139 }, + { 1052, 94, 1, 9, 370, 68 }, + { 1177, 99, 1, 9, 370, 2 }, + { 1315, 104, 1, 9, 370, 2 }, + { 101, 109, 1, 9, 370, 349 }, + { 266, 114, 1, 9, 370, 346 }, + { 404, 1, 1, 1, 10961, 352 }, + { 541, 1, 1, 1, 10961, 3 }, + { 678, 1, 1, 1, 10961, 174 }, + { 809, 1, 1, 1, 10961, 148 }, + { 934, 1, 1, 1, 10961, 168 }, + { 1059, 1, 1, 1, 10961, 3 }, + { 1184, 1, 1, 1, 10961, 302 }, + { 1322, 1, 1, 1, 10961, 354 }, + { 108, 1, 1, 1, 10961, 13 }, + { 273, 1, 1, 1, 10961, 356 }, + { 410, 1, 1, 1, 10961, 358 }, + { 547, 1, 1, 1, 10961, 360 }, + { 684, 1, 1, 1, 10961, 93 }, + { 815, 1, 1, 1, 10961, 126 }, + { 940, 1, 1, 1, 10961, 3 }, + { 1065, 1, 1, 1, 10961, 3 }, + { 1190, 1, 1, 1, 10961, 3 }, + { 1328, 1, 1, 1, 10961, 366 }, + { 114, 1, 1, 1, 10961, 368 }, + { 279, 1, 1, 1, 10961, 370 }, + { 416, 1, 1, 1, 10961, 364 }, + { 553, 1, 1, 1, 10961, 394 }, + { 690, 1, 1, 1, 10961, 362 }, + { 821, 1, 1, 1, 10961, 3 }, + { 946, 1, 1, 1, 10961, 148 }, + { 1071, 1, 1, 1, 10961, 372 }, + { 1196, 1, 1, 1, 10961, 172 }, + { 1334, 1, 1, 1, 10961, 374 }, + { 120, 1, 1, 1, 10961, 411 }, + { 285, 1, 1, 1, 10961, 152 }, + { 422, 1, 1, 1, 10961, 148 }, + { 559, 1, 1, 1, 10961, 3 }, + { 151, 388, 185, 0, 7441, 148 }, + { 316, 388, 181, 0, 7441, 416 }, + { 453, 388, 181, 0, 7441, 221 }, + { 590, 388, 177, 0, 7441, 3 }, + { 721, 388, 177, 0, 7441, 63 }, + { 852, 388, 173, 0, 7441, 420 }, + { 977, 388, 173, 0, 7441, 3 }, + { 1102, 388, 169, 0, 7441, 31 }, + { 1240, 388, 169, 0, 7441, 3 }, + { 1358, 388, 165, 0, 7441, 97 }, + { 23, 388, 165, 0, 7441, 418 }, + { 188, 388, 161, 0, 7441, 106 }, + { 353, 388, 161, 0, 7441, 95 }, + { 490, 388, 157, 0, 7441, 73 }, + { 627, 388, 157, 0, 7441, 3 }, + { 758, 388, 153, 0, 7441, 510 }, + { 889, 388, 153, 0, 7441, 134 }, + { 1014, 388, 149, 0, 7441, 148 }, + { 1139, 388, 149, 0, 7441, 148 }, + { 1277, 388, 145, 0, 7441, 3 }, + { 63, 388, 145, 0, 7441, 424 }, + { 228, 388, 141, 0, 7441, 13 }, + { 393, 388, 141, 0, 7441, 99 }, + { 530, 388, 137, 0, 7441, 3 }, + { 667, 388, 137, 0, 7441, 426 }, + { 798, 388, 133, 0, 7441, 510 }, + { 923, 388, 133, 0, 7441, 148 }, + { 1048, 388, 129, 0, 7441, 33 }, + { 1173, 388, 129, 0, 7441, 21 }, + { 1311, 388, 125, 0, 7441, 108 }, + { 97, 388, 125, 0, 7441, 430 }, + { 262, 388, 121, 0, 7441, 3 }, + { 1211, 379, 1, 0, 448, 428 }, + { 1441, 1, 383, 1, 5972, 488 }, + { 1447, 1, 383, 1, 5972, 422 }, + { 1453, 1, 383, 1, 5972, 432 }, + { 1459, 1, 383, 1, 5972, 434 }, + { 1465, 1, 383, 1, 5972, 134 }, + { 1471, 1, 383, 1, 5972, 148 }, + { 1477, 1, 383, 1, 5972, 148 }, + { 1483, 1, 383, 1, 5972, 3 }, + { 1508, 1, 381, 1, 5940, 440 }, + { 1514, 1, 381, 1, 5940, 490 }, + { 1520, 1, 381, 1, 5940, 438 }, + { 1526, 1, 381, 1, 5940, 29 }, + { 1532, 1, 381, 1, 5940, 13 }, + { 1538, 1, 381, 1, 5940, 35 }, + { 1544, 1, 381, 1, 5940, 99 }, + { 1550, 1, 381, 1, 5940, 104 }, + { 1556, 1, 377, 1, 5908, 156 }, + { 1562, 1, 377, 1, 5908, 180 }, + { 1568, 1, 377, 1, 5908, 3 }, + { 1574, 1, 377, 1, 5908, 444 }, + { 1580, 1, 377, 1, 5908, 510 }, + { 1586, 1, 377, 1, 5908, 134 }, + { 1592, 1, 377, 1, 5908, 35 }, + { 1598, 1, 377, 1, 5908, 446 }, + { 1382, 1, 375, 1, 5876, 148 }, + { 1388, 1, 375, 1, 5876, 3 }, + { 1394, 1, 375, 1, 5876, 148 }, + { 1400, 1, 375, 1, 5876, 71 }, + { 1406, 1, 375, 1, 5876, 3 }, + { 1412, 1, 375, 1, 5876, 118 }, + { 1418, 1, 375, 1, 5876, 448 }, + { 1424, 1, 375, 1, 5876, 450 }, + { 154, 385, 1, 25, 274, 452 }, + { 319, 390, 1, 25, 274, 10 }, + { 456, 395, 1, 25, 274, 46 }, + { 593, 400, 1, 25, 274, 455 }, + { 724, 405, 1, 25, 274, 65 }, + { 855, 410, 1, 25, 274, 49 }, + { 980, 415, 1, 25, 274, 269 }, + { 1105, 420, 1, 25, 274, 113 }, + { 1243, 425, 1, 25, 274, 413 }, + { 1361, 430, 1, 25, 274, 272 }, + { 27, 435, 1, 25, 274, 128 }, + { 192, 440, 1, 25, 274, 62 }, + { 357, 445, 1, 25, 274, 278 }, + { 494, 450, 1, 25, 274, 136 }, + { 631, 455, 1, 25, 274, 275 }, + { 762, 460, 1, 25, 274, 262 }, +}; + + // VSSRC Register Class... + static const MCPhysReg VSSRC[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, + }; + + // VSSRC Bit set. + static const uint8_t VSSRCBits[] = { + 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // GPRC Register Class... + static const MCPhysReg GPRC[] = { + PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R0, PPC_R1, PPC_FP, PPC_BP, + }; + + // GPRC Bit set. + static const uint8_t GPRCBits[] = { + 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // GPRC_NOR0 Register Class... + static const MCPhysReg GPRC_NOR0[] = { + PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, PPC_ZERO, + }; + + // GPRC_NOR0 Bit set. + static const uint8_t GPRC_NOR0Bits[] = { + 0x12, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + }; + + // GPRC_and_GPRC_NOR0 Register Class... + static const MCPhysReg GPRC_and_GPRC_NOR0[] = { + PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, + }; + + // GPRC_and_GPRC_NOR0 Bit set. + static const uint8_t GPRC_and_GPRC_NOR0Bits[] = { + 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + }; + + // CRBITRC Register Class... + static const MCPhysReg CRBITRC[] = { + PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN, PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, + }; + + // CRBITRC Bit set. + static const uint8_t CRBITRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + }; + + // F4RC Register Class... + static const MCPhysReg F4RC[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, + }; + + // F4RC Bit set. + static const uint8_t F4RCBits[] = { + 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // CRRC Register Class... + static const MCPhysReg CRRC[] = { + PPC_CR0, PPC_CR1, PPC_CR5, PPC_CR6, PPC_CR7, PPC_CR2, PPC_CR3, PPC_CR4, + }; + + // CRRC Bit set. + static const uint8_t CRRCBits[] = { + 0x00, 0x00, 0xf0, 0x0f, + }; + + // CARRYRC Register Class... + static const MCPhysReg CARRYRC[] = { + PPC_CARRY, PPC_XER, + }; + + // CARRYRC Bit set. + static const uint8_t CARRYRCBits[] = { + 0x04, 0x02, + }; + + // CTRRC Register Class... + static const MCPhysReg CTRRC[] = { + PPC_CTR, + }; + + // CTRRC Bit set. + static const uint8_t CTRRCBits[] = { + 0x08, + }; + + // LRRC Register Class... + static const MCPhysReg LRRC[] = { + PPC_LR, + }; + + // LRRC Bit set. + static const uint8_t LRRCBits[] = { + 0x20, + }; + + // VRSAVERC Register Class... + static const MCPhysReg VRSAVERC[] = { + PPC_VRSAVE, + }; + + // VRSAVERC Bit set. + static const uint8_t VRSAVERCBits[] = { + 0x00, 0x01, + }; + + // SPILLTOVSRRC Register Class... + static const MCPhysReg SPILLTOVSRRC[] = { + PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8, PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, + }; + + // SPILLTOVSRRC Bit set. + static const uint8_t SPILLTOVSRRCBits[] = { + 0x00, 0x00, 0x08, 0xe0, 0xff, 0x07, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // VSFRC Register Class... + static const MCPhysReg VSFRC[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, + }; + + // VSFRC Bit set. + static const uint8_t VSFRCBits[] = { + 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // G8RC Register Class... + static const MCPhysReg G8RC[] = { + PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8, + }; + + // G8RC Bit set. + static const uint8_t G8RCBits[] = { + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // G8RC_NOX0 Register Class... + static const MCPhysReg G8RC_NOX0[] = { + PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, PPC_ZERO8, + }; + + // G8RC_NOX0 Bit set. + static const uint8_t G8RC_NOX0Bits[] = { + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + }; + + // SPILLTOVSRRC_and_VSFRC Register Class... + static const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, + }; + + // SPILLTOVSRRC_and_VSFRC Bit set. + static const uint8_t SPILLTOVSRRC_and_VSFRCBits[] = { + 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, + }; + + // G8RC_and_G8RC_NOX0 Register Class... + static const MCPhysReg G8RC_and_G8RC_NOX0[] = { + PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, + }; + + // G8RC_and_G8RC_NOX0 Bit set. + static const uint8_t G8RC_and_G8RC_NOX0Bits[] = { + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + }; + + // F8RC Register Class... + static const MCPhysReg F8RC[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, + }; + + // F8RC Bit set. + static const uint8_t F8RCBits[] = { + 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + + // SPERC Register Class... + static const MCPhysReg SPERC[] = { + PPC_S2, PPC_S3, PPC_S4, PPC_S5, PPC_S6, PPC_S7, PPC_S8, PPC_S9, PPC_S10, PPC_S11, PPC_S12, PPC_S30, PPC_S29, PPC_S28, PPC_S27, PPC_S26, PPC_S25, PPC_S24, PPC_S23, PPC_S22, PPC_S21, PPC_S20, PPC_S19, PPC_S18, PPC_S17, PPC_S16, PPC_S15, PPC_S14, PPC_S13, PPC_S31, PPC_S0, PPC_S1, + }; + + // SPERC Bit set. + static const uint8_t SPERCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // VFRC Register Class... + static const MCPhysReg VFRC[] = { + PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, + }; + + // VFRC Bit set. + static const uint8_t VFRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // SPERC_with_sub_32_in_GPRC_NOR0 Register Class... + static const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = { + PPC_S2, PPC_S3, PPC_S4, PPC_S5, PPC_S6, PPC_S7, PPC_S8, PPC_S9, PPC_S10, PPC_S11, PPC_S12, PPC_S30, PPC_S29, PPC_S28, PPC_S27, PPC_S26, PPC_S25, PPC_S24, PPC_S23, PPC_S22, PPC_S21, PPC_S20, PPC_S19, PPC_S18, PPC_S17, PPC_S16, PPC_S15, PPC_S14, PPC_S13, PPC_S31, PPC_S1, + }; + + // SPERC_with_sub_32_in_GPRC_NOR0 Bit set. + static const uint8_t SPERC_with_sub_32_in_GPRC_NOR0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + }; + + // SPILLTOVSRRC_and_VFRC Register Class... + static const MCPhysReg SPILLTOVSRRC_and_VFRC[] = { + PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, + }; + + // SPILLTOVSRRC_and_VFRC Bit set. + static const uint8_t SPILLTOVSRRC_and_VFRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, + }; + + // SPILLTOVSRRC_and_F4RC Register Class... + static const MCPhysReg SPILLTOVSRRC_and_F4RC[] = { + PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, + }; + + // SPILLTOVSRRC_and_F4RC Bit set. + static const uint8_t SPILLTOVSRRC_and_F4RCBits[] = { + 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, + }; + + // CTRRC8 Register Class... + static const MCPhysReg CTRRC8[] = { + PPC_CTR8, + }; + + // CTRRC8 Bit set. + static const uint8_t CTRRC8Bits[] = { + 0x00, 0x00, 0x00, 0x10, + }; + + // LR8RC Register Class... + static const MCPhysReg LR8RC[] = { + PPC_LR8, + }; + + // LR8RC Bit set. + static const uint8_t LR8RCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + }; + + // VSRC Register Class... + static const MCPhysReg VSRC[] = { + PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20, + }; + + // VSRC Bit set. + static const uint8_t VSRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // VSRC_with_sub_64_in_SPILLTOVSRRC Register Class... + static const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = { + PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, + }; + + // VSRC_with_sub_64_in_SPILLTOVSRRC Bit set. + static const uint8_t VSRC_with_sub_64_in_SPILLTOVSRRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, + }; + + // VRRC Register Class... + static const MCPhysReg VRRC[] = { + PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20, + }; + + // VRRC Bit set. + static const uint8_t VRRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // VSLRC Register Class... + static const MCPhysReg VSLRC[] = { + PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, + }; + + // VSLRC Bit set. + static const uint8_t VSLRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // VRRC_with_sub_64_in_SPILLTOVSRRC Register Class... + static const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = { + PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, + }; + + // VRRC_with_sub_64_in_SPILLTOVSRRC Bit set. + static const uint8_t VRRC_with_sub_64_in_SPILLTOVSRRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, + }; + + // G8pRC Register Class... + static const MCPhysReg G8pRC[] = { + PPC_G8p1, PPC_G8p2, PPC_G8p3, PPC_G8p4, PPC_G8p5, PPC_G8p14, PPC_G8p13, PPC_G8p12, PPC_G8p11, PPC_G8p10, PPC_G8p9, PPC_G8p8, PPC_G8p7, PPC_G8p15, PPC_G8p6, PPC_G8p0, + }; + + // G8pRC Bit set. + static const uint8_t G8pRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, + }; + + // G8pRC_with_sub_32_in_GPRC_NOR0 Register Class... + static const MCPhysReg G8pRC_with_sub_32_in_GPRC_NOR0[] = { + PPC_G8p1, PPC_G8p2, PPC_G8p3, PPC_G8p4, PPC_G8p5, PPC_G8p14, PPC_G8p13, PPC_G8p12, PPC_G8p11, PPC_G8p10, PPC_G8p9, PPC_G8p8, PPC_G8p7, PPC_G8p15, PPC_G8p6, + }; + + // G8pRC_with_sub_32_in_GPRC_NOR0 Bit set. + static const uint8_t G8pRC_with_sub_32_in_GPRC_NOR0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, + }; + + // VSLRC_with_sub_64_in_SPILLTOVSRRC Register Class... + static const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = { + PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, + }; + + // VSLRC_with_sub_64_in_SPILLTOVSRRC Bit set. + static const uint8_t VSLRC_with_sub_64_in_SPILLTOVSRRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, + }; + + // VSRpRC Register Class... + static const MCPhysReg VSRpRC[] = { + PPC_VSRp17, PPC_VSRp18, PPC_VSRp16, PPC_VSRp19, PPC_VSRp20, PPC_VSRp21, PPC_VSRp22, PPC_VSRp23, PPC_VSRp24, PPC_VSRp25, PPC_VSRp31, PPC_VSRp30, PPC_VSRp29, PPC_VSRp28, PPC_VSRp27, PPC_VSRp26, PPC_VSRp0, PPC_VSRp1, PPC_VSRp2, PPC_VSRp3, PPC_VSRp4, PPC_VSRp5, PPC_VSRp6, PPC_VSRp15, PPC_VSRp14, PPC_VSRp13, PPC_VSRp12, PPC_VSRp11, PPC_VSRp10, PPC_VSRp9, PPC_VSRp8, PPC_VSRp7, + }; + // VSRpRC Bit set. + static const uint8_t VSRpRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + + // VSRpRC_with_sub_64_in_SPILLTOVSRRC Register Class... + static const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC[] = { + PPC_VSRp17, PPC_VSRp18, PPC_VSRp16, PPC_VSRp19, PPC_VSRp20, PPC_VSRp21, PPC_VSRp22, PPC_VSRp23, PPC_VSRp24, PPC_VSRp25, PPC_VSRp0, PPC_VSRp1, PPC_VSRp2, PPC_VSRp3, PPC_VSRp4, PPC_VSRp5, PPC_VSRp6, + }; + + // VSRpRC_with_sub_64_in_SPILLTOVSRRC Bit set. + static const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x80, 0xff, 0x01, + }; + + // VSRpRC_with_sub_64_in_F4RC Register Class... + static const MCPhysReg VSRpRC_with_sub_64_in_F4RC[] = { + PPC_VSRp0, PPC_VSRp1, PPC_VSRp2, PPC_VSRp3, PPC_VSRp4, PPC_VSRp5, PPC_VSRp6, PPC_VSRp15, PPC_VSRp14, PPC_VSRp13, PPC_VSRp12, PPC_VSRp11, PPC_VSRp10, PPC_VSRp9, PPC_VSRp8, PPC_VSRp7, + }; + + // VSRpRC_with_sub_64_in_F4RC Bit set. + static const uint8_t VSRpRC_with_sub_64_in_F4RCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + }; + + // VSRpRC_with_sub_64_in_VFRC Register Class... + static const MCPhysReg VSRpRC_with_sub_64_in_VFRC[] = { + PPC_VSRp17, PPC_VSRp18, PPC_VSRp16, PPC_VSRp19, PPC_VSRp20, PPC_VSRp21, PPC_VSRp22, PPC_VSRp23, PPC_VSRp24, PPC_VSRp25, PPC_VSRp31, PPC_VSRp30, PPC_VSRp29, PPC_VSRp28, PPC_VSRp27, PPC_VSRp26, + }; + + // VSRpRC_with_sub_64_in_VFRC Bit set. + static const uint8_t VSRpRC_with_sub_64_in_VFRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + }; + + // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Register Class... + static const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC[] = { + PPC_VSRp17, PPC_VSRp18, PPC_VSRp16, PPC_VSRp19, PPC_VSRp20, PPC_VSRp21, PPC_VSRp22, PPC_VSRp23, PPC_VSRp24, PPC_VSRp25, + }; + + // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Bit set. + static const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, + }; + + // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Register Class... + static const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC[] = { + PPC_VSRp0, PPC_VSRp1, PPC_VSRp2, PPC_VSRp3, PPC_VSRp4, PPC_VSRp5, PPC_VSRp6, + }; + + // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Bit set. + static const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, + }; + + // ACCRC Register Class... + static const MCPhysReg ACCRC[] = { + PPC_ACC0, PPC_ACC1, PPC_ACC2, PPC_ACC3, PPC_ACC4, PPC_ACC5, PPC_ACC6, PPC_ACC7, + }; + + // ACCRC Bit set. + static const uint8_t ACCRCBits[] = { + 0x00, 0xf8, 0x07, + }; + + // UACCRC Register Class... + static const MCPhysReg UACCRC[] = { + PPC_UACC0, PPC_UACC1, PPC_UACC2, PPC_UACC3, PPC_UACC4, PPC_UACC5, PPC_UACC6, PPC_UACC7, + }; + + // UACCRC Bit set. + static const uint8_t UACCRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, + }; + + // ACCRC_with_sub_64_in_SPILLTOVSRRC Register Class... + static const MCPhysReg ACCRC_with_sub_64_in_SPILLTOVSRRC[] = { + PPC_ACC0, PPC_ACC1, PPC_ACC2, PPC_ACC3, + }; + + // ACCRC_with_sub_64_in_SPILLTOVSRRC Bit set. + static const uint8_t ACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = { + 0x00, 0x78, + }; + + // UACCRC_with_sub_64_in_SPILLTOVSRRC Register Class... + static const MCPhysReg UACCRC_with_sub_64_in_SPILLTOVSRRC[] = { + PPC_UACC0, PPC_UACC1, PPC_UACC2, PPC_UACC3, + }; + + // UACCRC_with_sub_64_in_SPILLTOVSRRC Bit set. + static const uint8_t UACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, + }; + + // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class... + static const MCPhysReg ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = { + PPC_ACC0, PPC_ACC1, PPC_ACC2, + }; + + // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set. + static const uint8_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = { + 0x00, 0x38, + }; + + // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class... + static const MCPhysReg UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = { + PPC_UACC0, PPC_UACC1, PPC_UACC2, + }; + + // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set. + static const uint8_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, + }; + +// end of register classes misc + + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char PPCRegClassStrings[] = { + /* 0 */ "GPRC_and_GPRC_NOR0\0" + /* 19 */ "SPERC_with_sub_32_in_GPRC_NOR0\0" + /* 50 */ "G8pRC_with_sub_32_in_GPRC_NOR0\0" + /* 81 */ "G8RC_and_G8RC_NOX0\0" + /* 100 */ "CTRRC8\0" + /* 107 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC\0" + /* 151 */ "VSRpRC_with_sub_64_in_F4RC\0" + /* 178 */ "F8RC\0" + /* 183 */ "G8RC\0" + /* 188 */ "LR8RC\0" + /* 194 */ "UACCRC\0" + /* 201 */ "SPERC\0" + /* 207 */ "VRSAVERC\0" + /* 216 */ "SPILLTOVSRRC_and_VSFRC\0" + /* 239 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC\0" + /* 283 */ "VSRpRC_with_sub_64_in_VFRC\0" + /* 310 */ "VSLRC\0" + /* 316 */ "GPRC\0" + /* 321 */ "CRRC\0" + /* 326 */ "LRRC\0" + /* 331 */ "UACCRC_with_sub_64_in_SPILLTOVSRRC\0" + /* 366 */ "VSLRC_with_sub_64_in_SPILLTOVSRRC\0" + /* 400 */ "VRRC_with_sub_64_in_SPILLTOVSRRC\0" + /* 433 */ "VSRC_with_sub_64_in_SPILLTOVSRRC\0" + /* 466 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC\0" + /* 501 */ "UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC\0" + /* 551 */ "CTRRC\0" + /* 557 */ "VRRC\0" + /* 562 */ "VSSRC\0" + /* 568 */ "VSRC\0" + /* 573 */ "CRBITRC\0" + /* 581 */ "CARRYRC\0" + /* 589 */ "G8pRC\0" + /* 595 */ "VSRpRC\0" +}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterClass PPCMCRegisterClasses[] = { + { VSSRC, VSSRCBits, sizeof(VSSRCBits) }, + { GPRC, GPRCBits, sizeof(GPRCBits) }, + { GPRC_NOR0, GPRC_NOR0Bits, sizeof(GPRC_NOR0Bits) }, + { GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, sizeof(GPRC_and_GPRC_NOR0Bits) }, + { CRBITRC, CRBITRCBits, sizeof(CRBITRCBits) }, + { F4RC, F4RCBits, sizeof(F4RCBits) }, + { CRRC, CRRCBits, sizeof(CRRCBits) }, + { CARRYRC, CARRYRCBits, sizeof(CARRYRCBits) }, + { CTRRC, CTRRCBits, sizeof(CTRRCBits) }, + { LRRC, LRRCBits, sizeof(LRRCBits) }, + { VRSAVERC, VRSAVERCBits, sizeof(VRSAVERCBits) }, + { SPILLTOVSRRC, SPILLTOVSRRCBits, sizeof(SPILLTOVSRRCBits) }, + { VSFRC, VSFRCBits, sizeof(VSFRCBits) }, + { G8RC, G8RCBits, sizeof(G8RCBits) }, + { G8RC_NOX0, G8RC_NOX0Bits, sizeof(G8RC_NOX0Bits) }, + { SPILLTOVSRRC_and_VSFRC, SPILLTOVSRRC_and_VSFRCBits, sizeof(SPILLTOVSRRC_and_VSFRCBits) }, + { G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, sizeof(G8RC_and_G8RC_NOX0Bits) }, + { F8RC, F8RCBits, sizeof(F8RCBits) }, + { SPERC, SPERCBits, sizeof(SPERCBits) }, + { VFRC, VFRCBits, sizeof(VFRCBits) }, + { SPERC_with_sub_32_in_GPRC_NOR0, SPERC_with_sub_32_in_GPRC_NOR0Bits, sizeof(SPERC_with_sub_32_in_GPRC_NOR0Bits) }, + { SPILLTOVSRRC_and_VFRC, SPILLTOVSRRC_and_VFRCBits, sizeof(SPILLTOVSRRC_and_VFRCBits) }, + { SPILLTOVSRRC_and_F4RC, SPILLTOVSRRC_and_F4RCBits, sizeof(SPILLTOVSRRC_and_F4RCBits) }, + { CTRRC8, CTRRC8Bits, sizeof(CTRRC8Bits) }, + { LR8RC, LR8RCBits, sizeof(LR8RCBits) }, + { VSRC, VSRCBits, sizeof(VSRCBits) }, + { VSRC_with_sub_64_in_SPILLTOVSRRC, VSRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VSRC_with_sub_64_in_SPILLTOVSRRCBits) }, + { VRRC, VRRCBits, sizeof(VRRCBits) }, + { VSLRC, VSLRCBits, sizeof(VSLRCBits) }, + { VRRC_with_sub_64_in_SPILLTOVSRRC, VRRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VRRC_with_sub_64_in_SPILLTOVSRRCBits) }, + { G8pRC, G8pRCBits, sizeof(G8pRCBits) }, + { G8pRC_with_sub_32_in_GPRC_NOR0, G8pRC_with_sub_32_in_GPRC_NOR0Bits, sizeof(G8pRC_with_sub_32_in_GPRC_NOR0Bits) }, + { VSLRC_with_sub_64_in_SPILLTOVSRRC, VSLRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VSLRC_with_sub_64_in_SPILLTOVSRRCBits) }, + { VSRpRC, VSRpRCBits, sizeof(VSRpRCBits) }, + { VSRpRC_with_sub_64_in_SPILLTOVSRRC, VSRpRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRCBits) }, + { VSRpRC_with_sub_64_in_F4RC, VSRpRC_with_sub_64_in_F4RCBits, sizeof(VSRpRC_with_sub_64_in_F4RCBits) }, + { VSRpRC_with_sub_64_in_VFRC, VSRpRC_with_sub_64_in_VFRCBits, sizeof(VSRpRC_with_sub_64_in_VFRCBits) }, + { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits) }, + { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits) }, + { ACCRC, ACCRCBits, sizeof(ACCRCBits) }, + { UACCRC, UACCRCBits, sizeof(UACCRCBits) }, + { ACCRC_with_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(ACCRC_with_sub_64_in_SPILLTOVSRRCBits) }, + { UACCRC_with_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(UACCRC_with_sub_64_in_SPILLTOVSRRCBits) }, + { ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, sizeof(ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits) }, + { UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, sizeof(UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits) }, +}; + +#endif // GET_REGINFO_MC_DESC + +#ifdef GET_ASM_WRITER +#undef GET_ASM_WRITER + +static void llvm_unreachable(const char * info) {} +static void assert(int val) {} +typedef struct MCMnemonic { + const char *first; + uint64_t second; +} MCMnemonic; + +static MCMnemonic createMnemonic(const char* first, uint64_t second) { + MCMnemonic mnemonic; + mnemonic.first = first; + mnemonic.second = second; + return mnemonic; +} + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +MCMnemonic PPC_getMnemonic(const MCInst *MI) { + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "#EH_SjLj_Setup\t\0" + /* 16 */ "bdzla+ \0" + /* 24 */ "bdnzla+ \0" + /* 33 */ "bdza+ \0" + /* 40 */ "bdnza+ \0" + /* 48 */ "bdzl+ \0" + /* 55 */ "bdnzl+ \0" + /* 63 */ "bdz+ \0" + /* 69 */ "bdnz+ \0" + /* 76 */ "bcl 20, 31, \0" + /* 89 */ "bctrl\n\tld 2, \0" + /* 103 */ "bctrl\n\tlwz 2, \0" + /* 118 */ "bc 12, \0" + /* 126 */ "bcl 12, \0" + /* 135 */ "bclrl 12, \0" + /* 146 */ "bcctrl 12, \0" + /* 158 */ "bclr 12, \0" + /* 168 */ "bcctr 12, \0" + /* 179 */ "bc 4, \0" + /* 186 */ "bcl 4, \0" + /* 194 */ "bclrl 4, \0" + /* 204 */ "bcctrl 4, \0" + /* 215 */ "bclr 4, \0" + /* 224 */ "bcctr 4, \0" + /* 234 */ "mtspr 256, \0" + /* 246 */ "bdzla- \0" + /* 254 */ "bdnzla- \0" + /* 263 */ "bdza- \0" + /* 270 */ "bdnza- \0" + /* 278 */ "bdzl- \0" + /* 285 */ "bdnzl- \0" + /* 293 */ "bdz- \0" + /* 299 */ "bdnz- \0" + /* 306 */ "vcmpneb. \0" + /* 316 */ "vcmpgtsb. \0" + /* 327 */ "extsb. \0" + /* 335 */ "vcmpequb. \0" + /* 346 */ "fsub. \0" + /* 353 */ "fmsub. \0" + /* 361 */ "fnmsub. \0" + /* 370 */ "vcmpgtub. \0" + /* 381 */ "vcmpnezb. \0" + /* 392 */ "addc. \0" + /* 399 */ "andc. \0" + /* 406 */ "tabortdc. \0" + /* 417 */ "subfc. \0" + /* 425 */ "subic. \0" + /* 433 */ "addic. \0" + /* 441 */ "rldic. \0" + /* 449 */ "bcdtrunc. \0" + /* 460 */ "bcdutrunc. \0" + /* 472 */ "orc. \0" + /* 478 */ "tabortwc. \0" + /* 489 */ "srad. \0" + /* 496 */ "fadd. \0" + /* 503 */ "fmadd. \0" + /* 511 */ "fnmadd. \0" + /* 520 */ "mulhd. \0" + /* 528 */ "fcfid. \0" + /* 536 */ "fctid. \0" + /* 544 */ "mulld. \0" + /* 552 */ "sld. \0" + /* 558 */ "nand. \0" + /* 565 */ "tend. \0" + /* 572 */ "srd. \0" + /* 578 */ "vcmpgtsd. \0" + /* 589 */ "vcmpequd. \0" + /* 600 */ "vcmpgtud. \0" + /* 611 */ "divd. \0" + /* 618 */ "cntlzd. \0" + /* 627 */ "cnttzd. \0" + /* 636 */ "adde. \0" + /* 643 */ "divde. \0" + /* 651 */ "slbfee. \0" + /* 660 */ "subfe. \0" + /* 668 */ "addme. \0" + /* 676 */ "subfme. \0" + /* 685 */ "fre. \0" + /* 691 */ "frsqrte. \0" + /* 701 */ "paste. \0" + /* 709 */ "divwe. \0" + /* 717 */ "addze. \0" + /* 725 */ "subfze. \0" + /* 734 */ "subf. \0" + /* 741 */ "mtfsf. \0" + /* 749 */ "fneg. \0" + /* 756 */ "vcmpneh. \0" + /* 766 */ "vcmpgtsh. \0" + /* 777 */ "extsh. \0" + /* 785 */ "vcmpequh. \0" + /* 796 */ "vcmpgtuh. \0" + /* 807 */ "vcmpnezh. \0" + /* 818 */ "tabortdci. \0" + /* 830 */ "tabortwci. \0" + /* 842 */ "sradi. \0" + /* 850 */ "clrlsldi. \0" + /* 861 */ "extldi. \0" + /* 870 */ "andi. \0" + /* 877 */ "clrrdi. \0" + /* 886 */ "insrdi. \0" + /* 895 */ "rotrdi. \0" + /* 904 */ "extrdi. \0" + /* 913 */ "mtfsfi. \0" + /* 922 */ "extswsli. \0" + /* 933 */ "rldimi. \0" + /* 942 */ "rlwimi. \0" + /* 951 */ "srawi. \0" + /* 959 */ "clrlslwi. \0" + /* 970 */ "inslwi. \0" + /* 979 */ "extlwi. \0" + /* 988 */ "clrrwi. \0" + /* 997 */ "insrwi. \0" + /* 1006 */ "rotrwi. \0" + /* 1015 */ "extrwi. \0" + /* 1024 */ "vstribl. \0" + /* 1034 */ "rldcl. \0" + /* 1042 */ "rldicl. \0" + /* 1051 */ "fsel. \0" + /* 1058 */ "vstrihl. \0" + /* 1068 */ "fmul. \0" + /* 1075 */ "treclaim. \0" + /* 1086 */ "frim. \0" + /* 1093 */ "rlwinm. \0" + /* 1102 */ "rlwnm. \0" + /* 1110 */ "bcdcfn. \0" + /* 1119 */ "bcdcpsgn. \0" + /* 1130 */ "fcpsgn. \0" + /* 1139 */ "bcdsetsgn. \0" + /* 1151 */ "tbegin. \0" + /* 1160 */ "frin. \0" + /* 1167 */ "bcdctn. \0" + /* 1176 */ "addco. \0" + /* 1184 */ "subfco. \0" + /* 1193 */ "addo. \0" + /* 1200 */ "mulldo. \0" + /* 1209 */ "divdo. \0" + /* 1217 */ "addeo. \0" + /* 1225 */ "divdeo. \0" + /* 1234 */ "subfeo. \0" + /* 1243 */ "addmeo. \0" + /* 1252 */ "subfmeo. \0" + /* 1262 */ "divweo. \0" + /* 1271 */ "addzeo. \0" + /* 1280 */ "subfzeo. \0" + /* 1290 */ "subfo. \0" + /* 1298 */ "nego. \0" + /* 1305 */ "divduo. \0" + /* 1314 */ "divdeuo. \0" + /* 1324 */ "divweuo. \0" + /* 1334 */ "divwuo. \0" + /* 1343 */ "mullwo. \0" + /* 1352 */ "divwo. \0" + /* 1360 */ "xvcmpgedp. \0" + /* 1372 */ "xvcmpeqdp. \0" + /* 1384 */ "xvcmpgtdp. \0" + /* 1396 */ "vcmpbfp. \0" + /* 1406 */ "vcmpgefp. \0" + /* 1417 */ "vcmpeqfp. \0" + /* 1428 */ "vcmpgtfp. \0" + /* 1439 */ "frip. \0" + /* 1446 */ "xvcmpgesp. \0" + /* 1458 */ "xvcmpeqsp. \0" + /* 1470 */ "frsp. \0" + /* 1477 */ "xvcmpgtsp. \0" + /* 1489 */ "icblq. \0" + /* 1497 */ "bcdcfsq. \0" + /* 1507 */ "bcdctsq. \0" + /* 1517 */ "vcmpgtsq. \0" + /* 1528 */ "vcmpequq. \0" + /* 1539 */ "vcmpgtuq. \0" + /* 1550 */ "vstribr. \0" + /* 1560 */ "rldcr. \0" + /* 1568 */ "rldicr. \0" + /* 1577 */ "vstrihr. \0" + /* 1587 */ "fmr. \0" + /* 1593 */ "nor. \0" + /* 1599 */ "xor. \0" + /* 1605 */ "bcdsr. \0" + /* 1613 */ "tsr. \0" + /* 1619 */ "fabs. \0" + /* 1626 */ "fnabs. \0" + /* 1634 */ "fsubs. \0" + /* 1642 */ "fmsubs. \0" + /* 1651 */ "fnmsubs. \0" + /* 1661 */ "bcds. \0" + /* 1668 */ "fadds. \0" + /* 1676 */ "fmadds. \0" + /* 1685 */ "fnmadds. \0" + /* 1695 */ "fcfids. \0" + /* 1704 */ "fres. \0" + /* 1711 */ "frsqrtes. \0" + /* 1722 */ "mffs. \0" + /* 1729 */ "andis. \0" + /* 1737 */ "fmuls. \0" + /* 1745 */ "fsqrts. \0" + /* 1754 */ "bcdus. \0" + /* 1762 */ "fcfidus. \0" + /* 1772 */ "fdivs. \0" + /* 1780 */ "tabort. \0" + /* 1789 */ "fsqrt. \0" + /* 1797 */ "mulhdu. \0" + /* 1806 */ "fcfidu. \0" + /* 1815 */ "fctidu. \0" + /* 1824 */ "divdu. \0" + /* 1832 */ "divdeu. \0" + /* 1841 */ "divweu. \0" + /* 1850 */ "mulhwu. \0" + /* 1859 */ "fctiwu. \0" + /* 1868 */ "divwu. \0" + /* 1876 */ "fdiv. \0" + /* 1883 */ "eqv. \0" + /* 1889 */ "sraw. \0" + /* 1896 */ "vcmpnew. \0" + /* 1906 */ "mulhw. \0" + /* 1914 */ "fctiw. \0" + /* 1922 */ "mullw. \0" + /* 1930 */ "slw. \0" + /* 1936 */ "srw. \0" + /* 1942 */ "vcmpgtsw. \0" + /* 1953 */ "extsw. \0" + /* 1961 */ "vcmpequw. \0" + /* 1972 */ "vcmpgtuw. \0" + /* 1983 */ "divw. \0" + /* 1990 */ "vcmpnezw. \0" + /* 2001 */ "cntlzw. \0" + /* 2010 */ "cnttzw. \0" + /* 2019 */ "stbcx. \0" + /* 2027 */ "stdcx. \0" + /* 2035 */ "sthcx. \0" + /* 2043 */ "stqcx. \0" + /* 2051 */ "stwcx. \0" + /* 2059 */ "tlbsx. \0" + /* 2067 */ "fctidz. \0" + /* 2076 */ "bcdcfz. \0" + /* 2085 */ "friz. \0" + /* 2092 */ "bcdctz. \0" + /* 2101 */ "fctiduz. \0" + /* 2111 */ "fctiwuz. \0" + /* 2121 */ "fctiwz. \0" + /* 2130 */ "mtfsb0 \0" + /* 2138 */ "mtfsb1 \0" + /* 2146 */ "#ATOMIC_CMP_SWAP_I32 \0" + /* 2168 */ "pmxvbf16ger2 \0" + /* 2182 */ "pmxvf16ger2 \0" + /* 2195 */ "pmxvi16ger2 \0" + /* 2208 */ "pmxvi8ger4 \0" + /* 2220 */ "#ATOMIC_CMP_SWAP_I16 \0" + /* 2242 */ "xvcvspbf16 \0" + /* 2254 */ "#TC_RETURNa8 \0" + /* 2268 */ "#TC_RETURNd8 \0" + /* 2282 */ "#TC_RETURNr8 \0" + /* 2296 */ "pmxvi4ger8 \0" + /* 2308 */ "#BUILD_UACC \0" + /* 2321 */ "#ADJCALLSTACKDOWN \0" + /* 2340 */ "#ADJCALLSTACKUP \0" + /* 2357 */ "#TC_RETURNa \0" + /* 2370 */ "evmhegsmfaa \0" + /* 2383 */ "evmhogsmfaa \0" + /* 2396 */ "evmwsmfaa \0" + /* 2407 */ "evmwssfaa \0" + /* 2418 */ "evmhegsmiaa \0" + /* 2431 */ "evmhogsmiaa \0" + /* 2444 */ "evmwsmiaa \0" + /* 2455 */ "evmhegumiaa \0" + /* 2468 */ "evmhogumiaa \0" + /* 2481 */ "evmwumiaa \0" + /* 2492 */ "dcba \0" + /* 2498 */ "bca \0" + /* 2503 */ "evmhesmfa \0" + /* 2514 */ "evmwhsmfa \0" + /* 2525 */ "evmhosmfa \0" + /* 2536 */ "evmwsmfa \0" + /* 2546 */ "evmhessfa \0" + /* 2557 */ "evmwhssfa \0" + /* 2568 */ "evmhossfa \0" + /* 2579 */ "evmwssfa \0" + /* 2589 */ "plha \0" + /* 2595 */ "evmhesmia \0" + /* 2606 */ "evmwhsmia \0" + /* 2617 */ "evmhosmia \0" + /* 2628 */ "evmwsmia \0" + /* 2638 */ "evmheumia \0" + /* 2649 */ "evmwhumia \0" + /* 2660 */ "evmwlumia \0" + /* 2671 */ "evmhoumia \0" + /* 2682 */ "evmwumia \0" + /* 2692 */ "bla \0" + /* 2697 */ "bcla \0" + /* 2703 */ "bdzla \0" + /* 2710 */ "bdnzla \0" + /* 2718 */ "evmra \0" + /* 2725 */ "plwa \0" + /* 2731 */ "mtvsrwa \0" + /* 2740 */ "bdza \0" + /* 2746 */ "bdnza \0" + /* 2753 */ "vsrab \0" + /* 2760 */ "rfebb \0" + /* 2767 */ "vcntmbb \0" + /* 2776 */ "xvtlsbb \0" + /* 2785 */ "vclzlsbb \0" + /* 2795 */ "vctzlsbb \0" + /* 2805 */ "vcmpneb \0" + /* 2814 */ "vmrghb \0" + /* 2822 */ "xxspltib \0" + /* 2832 */ "vmrglb \0" + /* 2840 */ "vclrlb \0" + /* 2848 */ "vrlb \0" + /* 2854 */ "vslb \0" + /* 2860 */ "vpmsumb \0" + /* 2869 */ "vgnb \0" + /* 2875 */ "cmpb \0" + /* 2881 */ "cmpeqb \0" + /* 2889 */ "cmprb \0" + /* 2896 */ "vclrrb \0" + /* 2904 */ "vsrb \0" + /* 2910 */ "vmulesb \0" + /* 2919 */ "vavgsb \0" + /* 2927 */ "vupkhsb \0" + /* 2936 */ "vspltisb \0" + /* 2946 */ "vupklsb \0" + /* 2955 */ "vminsb \0" + /* 2963 */ "vmulosb \0" + /* 2972 */ "vcmpgtsb \0" + /* 2982 */ "evextsb \0" + /* 2991 */ "vmaxsb \0" + /* 2999 */ "setb \0" + /* 3005 */ "mftb \0" + /* 3011 */ "vspltb \0" + /* 3019 */ "vpopcntb \0" + /* 3029 */ "vinsertb \0" + /* 3039 */ "pstb \0" + /* 3045 */ "vabsdub \0" + /* 3054 */ "vmuleub \0" + /* 3063 */ "vavgub \0" + /* 3071 */ "vminub \0" + /* 3079 */ "vmuloub \0" + /* 3088 */ "vcmpequb \0" + /* 3098 */ "efdsub \0" + /* 3106 */ "fsub \0" + /* 3112 */ "fmsub \0" + /* 3119 */ "fnmsub \0" + /* 3127 */ "efssub \0" + /* 3135 */ "evfssub \0" + /* 3144 */ "vextractub \0" + /* 3156 */ "vcmpgtub \0" + /* 3166 */ "vmaxub \0" + /* 3174 */ "xxblendvb \0" + /* 3185 */ "vcmpnezb \0" + /* 3195 */ "vclzb \0" + /* 3202 */ "vctzb \0" + /* 3209 */ "setnbc \0" + /* 3217 */ "setbc \0" + /* 3224 */ "xxmfacc \0" + /* 3233 */ "xxmtacc \0" + /* 3242 */ "addc \0" + /* 3248 */ "xxlandc \0" + /* 3257 */ "crandc \0" + /* 3265 */ "evandc \0" + /* 3273 */ "subfc \0" + /* 3280 */ "subic \0" + /* 3287 */ "addic \0" + /* 3294 */ "rldic \0" + /* 3301 */ "subfic \0" + /* 3309 */ "xsrdpic \0" + /* 3318 */ "xvrdpic \0" + /* 3327 */ "xvrspic \0" + /* 3336 */ "icblc \0" + /* 3343 */ "brinc \0" + /* 3350 */ "sync \0" + /* 3356 */ "xxlorc \0" + /* 3364 */ "crorc \0" + /* 3371 */ "evorc \0" + /* 3378 */ "sc \0" + /* 3382 */ "vextsb2d \0" + /* 3392 */ "vextsh2d \0" + /* 3402 */ "vextsw2d \0" + /* 3412 */ "#TC_RETURNd \0" + /* 3425 */ "vshasigmad \0" + /* 3437 */ "vsrad \0" + /* 3444 */ "vgbbd \0" + /* 3451 */ "vcntmbd \0" + /* 3460 */ "vprtybd \0" + /* 3469 */ "efdadd \0" + /* 3477 */ "fadd \0" + /* 3483 */ "fmadd \0" + /* 3490 */ "fnmadd \0" + /* 3498 */ "efsadd \0" + /* 3506 */ "evfsadd \0" + /* 3515 */ "evldd \0" + /* 3522 */ "mtvsrdd \0" + /* 3531 */ "evstdd \0" + /* 3539 */ "vcfuged \0" + /* 3548 */ "efscfd \0" + /* 3556 */ "plfd \0" + /* 3562 */ "pstfd \0" + /* 3569 */ "vnegd \0" + /* 3576 */ "maddhd \0" + /* 3584 */ "mulhd \0" + /* 3591 */ "fcfid \0" + /* 3598 */ "efdcfsid \0" + /* 3608 */ "fctid \0" + /* 3615 */ "efdcfuid \0" + /* 3625 */ "tlbld \0" + /* 3632 */ "maddld \0" + /* 3640 */ "vmulld \0" + /* 3648 */ "cmpld \0" + /* 3655 */ "mfvsrld \0" + /* 3664 */ "vrld \0" + /* 3670 */ "vsld \0" + /* 3676 */ "vbpermd \0" + /* 3685 */ "vpmsumd \0" + /* 3694 */ "xxland \0" + /* 3702 */ "xxlnand \0" + /* 3711 */ "crnand \0" + /* 3719 */ "evnand \0" + /* 3727 */ "crand \0" + /* 3734 */ "evand \0" + /* 3741 */ "vpdepd \0" + /* 3749 */ "cmpd \0" + /* 3755 */ "xxbrd \0" + /* 3762 */ "mtmsrd \0" + /* 3770 */ "mfvsrd \0" + /* 3778 */ "mtvsrd \0" + /* 3786 */ "vmodsd \0" + /* 3794 */ "vmulesd \0" + /* 3803 */ "vdivesd \0" + /* 3812 */ "vmulhsd \0" + /* 3821 */ "vminsd \0" + /* 3829 */ "vinsd \0" + /* 3836 */ "vmulosd \0" + /* 3845 */ "vcmpgtsd \0" + /* 3855 */ "vdivsd \0" + /* 3863 */ "vmaxsd \0" + /* 3871 */ "plxsd \0" + /* 3878 */ "pstxsd \0" + /* 3886 */ "vextractd \0" + /* 3897 */ "vpopcntd \0" + /* 3907 */ "vinsertd \0" + /* 3917 */ "pstd \0" + /* 3923 */ "vpextd \0" + /* 3931 */ "vmsumcud \0" + /* 3941 */ "vmodud \0" + /* 3949 */ "vmuleud \0" + /* 3958 */ "vdiveud \0" + /* 3967 */ "vmulhud \0" + /* 3976 */ "vminud \0" + /* 3984 */ "vmuloud \0" + /* 3993 */ "vcmpequd \0" + /* 4003 */ "vcmpgtud \0" + /* 4013 */ "vdivud \0" + /* 4021 */ "vmaxud \0" + /* 4029 */ "xxblendvd \0" + /* 4040 */ "divd \0" + /* 4046 */ "vclzd \0" + /* 4053 */ "cntlzd \0" + /* 4061 */ "vctzd \0" + /* 4068 */ "cnttzd \0" + /* 4076 */ "mfbhrbe \0" + /* 4085 */ "mffsce \0" + /* 4093 */ "adde \0" + /* 4099 */ "divde \0" + /* 4106 */ "slbmfee \0" + /* 4115 */ "wrtee \0" + /* 4122 */ "subfe \0" + /* 4129 */ "evlwhe \0" + /* 4137 */ "evstwhe \0" + /* 4146 */ "slbie \0" + /* 4153 */ "tlbie \0" + /* 4160 */ "addme \0" + /* 4167 */ "subfme \0" + /* 4175 */ "tlbre \0" + /* 4182 */ "fre \0" + /* 4187 */ "slbmte \0" + /* 4195 */ "frsqrte \0" + /* 4204 */ "tlbwe \0" + /* 4211 */ "divwe \0" + /* 4218 */ "evstwwe \0" + /* 4227 */ "addze \0" + /* 4234 */ "subfze \0" + /* 4242 */ "dcbf \0" + /* 4248 */ "subf \0" + /* 4254 */ "evmhesmf \0" + /* 4264 */ "evmwhsmf \0" + /* 4274 */ "evmhosmf \0" + /* 4284 */ "evmwsmf \0" + /* 4293 */ "mcrf \0" + /* 4299 */ "mfocrf \0" + /* 4307 */ "mtocrf \0" + /* 4315 */ "mtcrf \0" + /* 4322 */ "efdcfsf \0" + /* 4331 */ "efscfsf \0" + /* 4340 */ "evfscfsf \0" + /* 4350 */ "mtfsf \0" + /* 4357 */ "evmhessf \0" + /* 4367 */ "evmwhssf \0" + /* 4377 */ "evmhossf \0" + /* 4387 */ "evmwssf \0" + /* 4396 */ "efdctsf \0" + /* 4405 */ "efsctsf \0" + /* 4414 */ "evfsctsf \0" + /* 4424 */ "efdcfuf \0" + /* 4433 */ "efscfuf \0" + /* 4442 */ "evfscfuf \0" + /* 4452 */ "efdctuf \0" + /* 4461 */ "efsctuf \0" + /* 4470 */ "slbieg \0" + /* 4478 */ "efdneg \0" + /* 4486 */ "fneg \0" + /* 4492 */ "efsneg \0" + /* 4500 */ "evfsneg \0" + /* 4509 */ "evneg \0" + /* 4516 */ "vsrah \0" + /* 4523 */ "vcntmbh \0" + /* 4532 */ "evldh \0" + /* 4539 */ "evstdh \0" + /* 4547 */ "vcmpneh \0" + /* 4556 */ "vmrghh \0" + /* 4564 */ "vmrglh \0" + /* 4572 */ "vrlh \0" + /* 4578 */ "vslh \0" + /* 4584 */ "vpmsumh \0" + /* 4593 */ "xxbrh \0" + /* 4600 */ "vsrh \0" + /* 4606 */ "vmulesh \0" + /* 4615 */ "vavgsh \0" + /* 4623 */ "vupkhsh \0" + /* 4632 */ "vspltish \0" + /* 4642 */ "vupklsh \0" + /* 4651 */ "vminsh \0" + /* 4659 */ "vmulosh \0" + /* 4668 */ "vcmpgtsh \0" + /* 4678 */ "evextsh \0" + /* 4687 */ "vmaxsh \0" + /* 4695 */ "vsplth \0" + /* 4703 */ "vpopcnth \0" + /* 4713 */ "vinserth \0" + /* 4723 */ "psth \0" + /* 4729 */ "vabsduh \0" + /* 4738 */ "vmuleuh \0" + /* 4747 */ "vavguh \0" + /* 4755 */ "vminuh \0" + /* 4763 */ "vmulouh \0" + /* 4772 */ "vcmpequh \0" + /* 4782 */ "vextractuh \0" + /* 4794 */ "vcmpgtuh \0" + /* 4804 */ "vmaxuh \0" + /* 4812 */ "xxblendvh \0" + /* 4823 */ "vcmpnezh \0" + /* 4833 */ "vclzh \0" + /* 4840 */ "vctzh \0" + /* 4847 */ "dcbi \0" + /* 4853 */ "icbi \0" + /* 4859 */ "vsldbi \0" + /* 4867 */ "vsrdbi \0" + /* 4875 */ "subi \0" + /* 4881 */ "dccci \0" + /* 4888 */ "iccci \0" + /* 4895 */ "sradi \0" + /* 4902 */ "paddi \0" + /* 4909 */ "cmpldi \0" + /* 4917 */ "clrlsldi \0" + /* 4927 */ "extldi \0" + /* 4935 */ "xxpermdi \0" + /* 4945 */ "cmpdi \0" + /* 4952 */ "clrrdi \0" + /* 4960 */ "insrdi \0" + /* 4968 */ "rotrdi \0" + /* 4976 */ "extrdi \0" + /* 4984 */ "tdi \0" + /* 4989 */ "wrteei \0" + /* 4997 */ "mtfsfi \0" + /* 5005 */ "evsplatfi \0" + /* 5016 */ "evmergehi \0" + /* 5027 */ "evmergelohi \0" + /* 5040 */ "tlbli \0" + /* 5047 */ "mulli \0" + /* 5054 */ "pli \0" + /* 5059 */ "extswsli \0" + /* 5069 */ "mtvsrbmi \0" + /* 5079 */ "vrldmi \0" + /* 5087 */ "rldimi \0" + /* 5095 */ "rlwimi \0" + /* 5103 */ "vrlqmi \0" + /* 5111 */ "evmhesmi \0" + /* 5121 */ "evmwhsmi \0" + /* 5131 */ "evmhosmi \0" + /* 5141 */ "evmwsmi \0" + /* 5150 */ "evmheumi \0" + /* 5160 */ "evmwhumi \0" + /* 5170 */ "evmwlumi \0" + /* 5180 */ "evmhoumi \0" + /* 5190 */ "evmwumi \0" + /* 5199 */ "vrlwmi \0" + /* 5207 */ "mffscrni \0" + /* 5217 */ "mffscdrni \0" + /* 5228 */ "vsldoi \0" + /* 5236 */ "xsrdpi \0" + /* 5244 */ "xvrdpi \0" + /* 5252 */ "xsrqpi \0" + /* 5260 */ "xvrspi \0" + /* 5268 */ "xori \0" + /* 5274 */ "efdcfsi \0" + /* 5283 */ "efscfsi \0" + /* 5292 */ "evfscfsi \0" + /* 5302 */ "efdctsi \0" + /* 5311 */ "efsctsi \0" + /* 5320 */ "evfsctsi \0" + /* 5330 */ "evsplati \0" + /* 5340 */ "efdcfui \0" + /* 5349 */ "efscfui \0" + /* 5358 */ "evfscfui \0" + /* 5368 */ "efdctui \0" + /* 5377 */ "efsctui \0" + /* 5386 */ "evfsctui \0" + /* 5396 */ "srawi \0" + /* 5403 */ "xxsldwi \0" + /* 5412 */ "cmplwi \0" + /* 5420 */ "evrlwi \0" + /* 5428 */ "clrlslwi \0" + /* 5438 */ "inslwi \0" + /* 5446 */ "evslwi \0" + /* 5454 */ "extlwi \0" + /* 5462 */ "cmpwi \0" + /* 5469 */ "clrrwi \0" + /* 5477 */ "insrwi \0" + /* 5485 */ "rotrwi \0" + /* 5493 */ "extrwi \0" + /* 5501 */ "lswi \0" + /* 5507 */ "stswi \0" + /* 5514 */ "twi \0" + /* 5519 */ "tcheck \0" + /* 5527 */ "hashchk \0" + /* 5536 */ "xxeval \0" + /* 5544 */ "vstribl \0" + /* 5553 */ "bcl \0" + /* 5558 */ "rldcl \0" + /* 5565 */ "rldicl \0" + /* 5573 */ "tlbiel \0" + /* 5581 */ "fsel \0" + /* 5587 */ "isel \0" + /* 5593 */ "vsel \0" + /* 5599 */ "xxsel \0" + /* 5606 */ "dcbfl \0" + /* 5613 */ "vstrihl \0" + /* 5622 */ "lxvll \0" + /* 5629 */ "stxvll \0" + /* 5637 */ "bclrl \0" + /* 5644 */ "bcctrl \0" + /* 5652 */ "mffsl \0" + /* 5659 */ "lvsl \0" + /* 5665 */ "efdmul \0" + /* 5673 */ "fmul \0" + /* 5679 */ "efsmul \0" + /* 5687 */ "evfsmul \0" + /* 5696 */ "lxvl \0" + /* 5702 */ "stxvl \0" + /* 5709 */ "lvxl \0" + /* 5715 */ "stvxl \0" + /* 5722 */ "dcbzl \0" + /* 5729 */ "bdzl \0" + /* 5735 */ "bdnzl \0" + /* 5742 */ "vexpandbm \0" + /* 5753 */ "vmsummbm \0" + /* 5763 */ "mtvsrbm \0" + /* 5772 */ "vextractbm \0" + /* 5784 */ "vsububm \0" + /* 5793 */ "vaddubm \0" + /* 5802 */ "vmsumubm \0" + /* 5812 */ "xxgenpcvbm \0" + /* 5824 */ "vexpanddm \0" + /* 5835 */ "mtvsrdm \0" + /* 5844 */ "vextractdm \0" + /* 5856 */ "vsubudm \0" + /* 5865 */ "vaddudm \0" + /* 5874 */ "vmsumudm \0" + /* 5884 */ "xxgenpcvdm \0" + /* 5896 */ "vclzdm \0" + /* 5904 */ "cntlzdm \0" + /* 5913 */ "vctzdm \0" + /* 5921 */ "cnttzdm \0" + /* 5930 */ "vexpandhm \0" + /* 5941 */ "mtvsrhm \0" + /* 5950 */ "vmsumshm \0" + /* 5960 */ "vextracthm \0" + /* 5972 */ "vsubuhm \0" + /* 5981 */ "vmladduhm \0" + /* 5992 */ "vadduhm \0" + /* 6001 */ "vmsumuhm \0" + /* 6011 */ "xxgenpcvhm \0" + /* 6023 */ "vrfim \0" + /* 6030 */ "xsrdpim \0" + /* 6039 */ "xvrdpim \0" + /* 6048 */ "xvrspim \0" + /* 6057 */ "frim \0" + /* 6063 */ "vrldnm \0" + /* 6071 */ "rlwinm \0" + /* 6079 */ "vrlqnm \0" + /* 6087 */ "vrlwnm \0" + /* 6095 */ "vexpandqm \0" + /* 6106 */ "mtvsrqm \0" + /* 6115 */ "vextractqm \0" + /* 6127 */ "vsubuqm \0" + /* 6136 */ "vadduqm \0" + /* 6145 */ "vsubeuqm \0" + /* 6155 */ "vaddeuqm \0" + /* 6165 */ "vperm \0" + /* 6172 */ "xxperm \0" + /* 6180 */ "vpkudum \0" + /* 6189 */ "vpkuhum \0" + /* 6198 */ "vpkuwum \0" + /* 6207 */ "vexpandwm \0" + /* 6218 */ "mtvsrwm \0" + /* 6227 */ "vextractwm \0" + /* 6239 */ "vsubuwm \0" + /* 6248 */ "vadduwm \0" + /* 6257 */ "vmuluwm \0" + /* 6266 */ "xxgenpcvwm \0" + /* 6278 */ "evmhegsmfan \0" + /* 6291 */ "evmhogsmfan \0" + /* 6304 */ "evmwsmfan \0" + /* 6315 */ "evmwssfan \0" + /* 6326 */ "evmhegsmian \0" + /* 6339 */ "evmhogsmian \0" + /* 6352 */ "evmwsmian \0" + /* 6363 */ "evmhegumian \0" + /* 6376 */ "evmhogumian \0" + /* 6389 */ "evmwumian \0" + /* 6400 */ "fcpsgn \0" + /* 6408 */ "vrfin \0" + /* 6415 */ "frin \0" + /* 6421 */ "mfsrin \0" + /* 6429 */ "mtsrin \0" + /* 6437 */ "pmxvbf16ger2nn \0" + /* 6453 */ "pmxvf16ger2nn \0" + /* 6468 */ "pmxvf32gernn \0" + /* 6482 */ "pmxvf64gernn \0" + /* 6496 */ "pmxvbf16ger2pn \0" + /* 6512 */ "pmxvf16ger2pn \0" + /* 6527 */ "xscvspdpn \0" + /* 6538 */ "pmxvf32gerpn \0" + /* 6552 */ "pmxvf64gerpn \0" + /* 6566 */ "xvcvbf16spn \0" + /* 6579 */ "xscvdpspn \0" + /* 6590 */ "darn \0" + /* 6596 */ "mffscrn \0" + /* 6605 */ "mffscdrn \0" + /* 6615 */ "addco \0" + /* 6622 */ "subfco \0" + /* 6630 */ "addo \0" + /* 6636 */ "mulldo \0" + /* 6644 */ "divdo \0" + /* 6651 */ "addeo \0" + /* 6658 */ "divdeo \0" + /* 6666 */ "subfeo \0" + /* 6674 */ "addmeo \0" + /* 6682 */ "subfmeo \0" + /* 6691 */ "divweo \0" + /* 6699 */ "addzeo \0" + /* 6707 */ "subfzeo \0" + /* 6716 */ "subfo \0" + /* 6723 */ "nego \0" + /* 6729 */ "evstwho \0" + /* 6738 */ "evmergelo \0" + /* 6749 */ "evmergehilo \0" + /* 6762 */ "vslo \0" + /* 6768 */ "xscvqpdpo \0" + /* 6779 */ "fcmpo \0" + /* 6786 */ "xsnmsubqpo \0" + /* 6798 */ "xsmsubqpo \0" + /* 6809 */ "xssubqpo \0" + /* 6819 */ "xsnmaddqpo \0" + /* 6831 */ "xsmaddqpo \0" + /* 6842 */ "xsaddqpo \0" + /* 6852 */ "xsmulqpo \0" + /* 6862 */ "xssqrtqpo \0" + /* 6873 */ "xsdivqpo \0" + /* 6883 */ "vsro \0" + /* 6889 */ "divduo \0" + /* 6897 */ "divdeuo \0" + /* 6906 */ "divweuo \0" + /* 6915 */ "divwuo \0" + /* 6923 */ "mullwo \0" + /* 6931 */ "divwo \0" + /* 6938 */ "evstwwo \0" + /* 6947 */ "xsnmsubadp \0" + /* 6959 */ "xvnmsubadp \0" + /* 6971 */ "xsmsubadp \0" + /* 6982 */ "xvmsubadp \0" + /* 6993 */ "xsnmaddadp \0" + /* 7005 */ "xvnmaddadp \0" + /* 7017 */ "xsmaddadp \0" + /* 7028 */ "xvmaddadp \0" + /* 7039 */ "xssubdp \0" + /* 7048 */ "xvsubdp \0" + /* 7057 */ "xststdcdp \0" + /* 7068 */ "xvtstdcdp \0" + /* 7079 */ "xsmincdp \0" + /* 7089 */ "xsmaxcdp \0" + /* 7099 */ "xsadddp \0" + /* 7108 */ "xvadddp \0" + /* 7117 */ "xscvsxddp \0" + /* 7128 */ "xvcvsxddp \0" + /* 7139 */ "xscvuxddp \0" + /* 7150 */ "xvcvuxddp \0" + /* 7161 */ "xscmpgedp \0" + /* 7172 */ "xvcmpgedp \0" + /* 7183 */ "xsredp \0" + /* 7191 */ "xvredp \0" + /* 7199 */ "xsrsqrtedp \0" + /* 7211 */ "xvrsqrtedp \0" + /* 7223 */ "xsnegdp \0" + /* 7232 */ "xvnegdp \0" + /* 7241 */ "xsxsigdp \0" + /* 7251 */ "xvxsigdp \0" + /* 7261 */ "xxspltidp \0" + /* 7272 */ "xsminjdp \0" + /* 7282 */ "xsmaxjdp \0" + /* 7292 */ "xsmuldp \0" + /* 7301 */ "xvmuldp \0" + /* 7310 */ "xsnmsubmdp \0" + /* 7322 */ "xvnmsubmdp \0" + /* 7334 */ "xsmsubmdp \0" + /* 7345 */ "xvmsubmdp \0" + /* 7356 */ "xsnmaddmdp \0" + /* 7368 */ "xvnmaddmdp \0" + /* 7380 */ "xsmaddmdp \0" + /* 7391 */ "xvmaddmdp \0" + /* 7402 */ "xscpsgndp \0" + /* 7413 */ "xvcpsgndp \0" + /* 7424 */ "xsmindp \0" + /* 7433 */ "xvmindp \0" + /* 7442 */ "xscmpodp \0" + /* 7452 */ "xscvhpdp \0" + /* 7462 */ "xscvqpdp \0" + /* 7472 */ "xscvspdp \0" + /* 7482 */ "xvcvspdp \0" + /* 7492 */ "xsiexpdp \0" + /* 7502 */ "xviexpdp \0" + /* 7512 */ "xscmpexpdp \0" + /* 7524 */ "xsxexpdp \0" + /* 7534 */ "xvxexpdp \0" + /* 7544 */ "xscmpeqdp \0" + /* 7555 */ "xvcmpeqdp \0" + /* 7566 */ "xsnabsdp \0" + /* 7576 */ "xvnabsdp \0" + /* 7586 */ "xsabsdp \0" + /* 7595 */ "xvabsdp \0" + /* 7604 */ "xscmpgtdp \0" + /* 7615 */ "xvcmpgtdp \0" + /* 7626 */ "xssqrtdp \0" + /* 7636 */ "xstsqrtdp \0" + /* 7647 */ "xvtsqrtdp \0" + /* 7658 */ "xvsqrtdp \0" + /* 7668 */ "xscmpudp \0" + /* 7678 */ "xsdivdp \0" + /* 7687 */ "xstdivdp \0" + /* 7697 */ "xvtdivdp \0" + /* 7707 */ "xvdivdp \0" + /* 7716 */ "xvcvsxwdp \0" + /* 7727 */ "xvcvuxwdp \0" + /* 7738 */ "xsmaxdp \0" + /* 7747 */ "xvmaxdp \0" + /* 7756 */ "dcbfep \0" + /* 7764 */ "icbiep \0" + /* 7772 */ "dcbzlep \0" + /* 7781 */ "dcbtep \0" + /* 7789 */ "dcbstep \0" + /* 7798 */ "dcbtstep \0" + /* 7808 */ "dcbzep \0" + /* 7816 */ "vcmpbfp \0" + /* 7825 */ "vnmsubfp \0" + /* 7835 */ "vsubfp \0" + /* 7843 */ "vmaddfp \0" + /* 7852 */ "vaddfp \0" + /* 7860 */ "vlogefp \0" + /* 7869 */ "vcmpgefp \0" + /* 7879 */ "vrefp \0" + /* 7886 */ "vexptefp \0" + /* 7896 */ "vrsqrtefp \0" + /* 7907 */ "vminfp \0" + /* 7915 */ "vcmpeqfp \0" + /* 7925 */ "vcmpgtfp \0" + /* 7935 */ "vmaxfp \0" + /* 7943 */ "xscvdphp \0" + /* 7953 */ "xvcvsphp \0" + /* 7963 */ "vrfip \0" + /* 7970 */ "xsrdpip \0" + /* 7979 */ "xvrdpip \0" + /* 7988 */ "xvrspip \0" + /* 7997 */ "frip \0" + /* 8003 */ "hashchkp \0" + /* 8013 */ "dcbflp \0" + /* 8021 */ "pmxvbf16ger2np \0" + /* 8037 */ "pmxvf16ger2np \0" + /* 8052 */ "pmxvf32gernp \0" + /* 8066 */ "pmxvf64gernp \0" + /* 8080 */ "pmxvbf16ger2pp \0" + /* 8096 */ "pmxvf16ger2pp \0" + /* 8111 */ "pmxvi16ger2pp \0" + /* 8126 */ "pmxvi8ger4pp \0" + /* 8140 */ "pmxvi4ger8pp \0" + /* 8154 */ "pmxvf32gerpp \0" + /* 8168 */ "pmxvf64gerpp \0" + /* 8182 */ "pmxvi16ger2spp \0" + /* 8198 */ "pmxvi8ger4spp \0" + /* 8213 */ "xsnmsubqp \0" + /* 8224 */ "xsmsubqp \0" + /* 8234 */ "xssubqp \0" + /* 8243 */ "xststdcqp \0" + /* 8254 */ "xsnmaddqp \0" + /* 8265 */ "xsmaddqp \0" + /* 8275 */ "xsaddqp \0" + /* 8284 */ "xscvsdqp \0" + /* 8294 */ "xscvudqp \0" + /* 8304 */ "xsnegqp \0" + /* 8313 */ "xsxsigqp \0" + /* 8323 */ "xsmulqp \0" + /* 8332 */ "xscpsgnqp \0" + /* 8343 */ "xscmpoqp \0" + /* 8353 */ "xscvdpqp \0" + /* 8363 */ "xsiexpqp \0" + /* 8373 */ "xscmpexpqp \0" + /* 8385 */ "xsxexpqp \0" + /* 8395 */ "xscvsqqp \0" + /* 8405 */ "xscvuqqp \0" + /* 8415 */ "xsnabsqp \0" + /* 8425 */ "xsabsqp \0" + /* 8434 */ "xssqrtqp \0" + /* 8444 */ "xscmpuqp \0" + /* 8454 */ "xsdivqp \0" + /* 8463 */ "xsnmsubasp \0" + /* 8475 */ "xvnmsubasp \0" + /* 8487 */ "xsmsubasp \0" + /* 8498 */ "xvmsubasp \0" + /* 8509 */ "xsnmaddasp \0" + /* 8521 */ "xvnmaddasp \0" + /* 8533 */ "xsmaddasp \0" + /* 8544 */ "xvmaddasp \0" + /* 8555 */ "xssubsp \0" + /* 8564 */ "xvsubsp \0" + /* 8573 */ "xststdcsp \0" + /* 8584 */ "xvtstdcsp \0" + /* 8595 */ "xsaddsp \0" + /* 8604 */ "xvaddsp \0" + /* 8613 */ "xscvsxdsp \0" + /* 8624 */ "xvcvsxdsp \0" + /* 8635 */ "xscvuxdsp \0" + /* 8646 */ "xvcvuxdsp \0" + /* 8657 */ "xvcmpgesp \0" + /* 8668 */ "xsresp \0" + /* 8676 */ "xvresp \0" + /* 8684 */ "xsrsqrtesp \0" + /* 8696 */ "xvrsqrtesp \0" + /* 8708 */ "xvnegsp \0" + /* 8717 */ "xvxsigsp \0" + /* 8727 */ "xsmulsp \0" + /* 8736 */ "xvmulsp \0" + /* 8745 */ "xsnmsubmsp \0" + /* 8757 */ "xvnmsubmsp \0" + /* 8769 */ "xsmsubmsp \0" + /* 8780 */ "xvmsubmsp \0" + /* 8791 */ "xsnmaddmsp \0" + /* 8803 */ "xvnmaddmsp \0" + /* 8815 */ "xsmaddmsp \0" + /* 8826 */ "xvmaddmsp \0" + /* 8837 */ "xvcpsgnsp \0" + /* 8848 */ "xvminsp \0" + /* 8857 */ "xscvdpsp \0" + /* 8867 */ "xvcvdpsp \0" + /* 8877 */ "xvcvhpsp \0" + /* 8887 */ "xviexpsp \0" + /* 8897 */ "xvxexpsp \0" + /* 8907 */ "xvcmpeqsp \0" + /* 8918 */ "frsp \0" + /* 8924 */ "xsrsp \0" + /* 8931 */ "xvnabssp \0" + /* 8941 */ "xvabssp \0" + /* 8950 */ "plxssp \0" + /* 8958 */ "pstxssp \0" + /* 8967 */ "xvcmpgtsp \0" + /* 8978 */ "xssqrtsp \0" + /* 8988 */ "xvtsqrtsp \0" + /* 8999 */ "xvsqrtsp \0" + /* 9009 */ "xsdivsp \0" + /* 9018 */ "xvtdivsp \0" + /* 9028 */ "xvdivsp \0" + /* 9037 */ "xvcvsxwsp \0" + /* 9048 */ "xvcvuxwsp \0" + /* 9059 */ "xvmaxsp \0" + /* 9068 */ "hashstp \0" + /* 9077 */ "plxvp \0" + /* 9084 */ "pstxvp \0" + /* 9092 */ "xsrqpxp \0" + /* 9101 */ "vextsd2q \0" + /* 9111 */ "vsraq \0" + /* 9118 */ "vprtybq \0" + /* 9127 */ "efdcmpeq \0" + /* 9137 */ "efscmpeq \0" + /* 9147 */ "evfscmpeq \0" + /* 9158 */ "evcmpeq \0" + /* 9167 */ "efdtsteq \0" + /* 9177 */ "efststeq \0" + /* 9187 */ "evfststeq \0" + /* 9198 */ "vrlq \0" + /* 9204 */ "vslq \0" + /* 9210 */ "vbpermq \0" + /* 9219 */ "xxbrq \0" + /* 9226 */ "vsrq \0" + /* 9232 */ "vmodsq \0" + /* 9240 */ "vdivesq \0" + /* 9249 */ "vcmpsq \0" + /* 9257 */ "vcmpgtsq \0" + /* 9267 */ "vdivsq \0" + /* 9275 */ "stq \0" + /* 9280 */ "vmul10uq \0" + /* 9290 */ "vmul10cuq \0" + /* 9301 */ "vsubcuq \0" + /* 9310 */ "vaddcuq \0" + /* 9319 */ "vmul10ecuq \0" + /* 9331 */ "vsubecuq \0" + /* 9341 */ "vaddecuq \0" + /* 9351 */ "vmoduq \0" + /* 9359 */ "vmul10euq \0" + /* 9370 */ "vdiveuq \0" + /* 9379 */ "vcmpuq \0" + /* 9387 */ "vcmpequq \0" + /* 9397 */ "vcmpgtuq \0" + /* 9407 */ "vdivuq \0" + /* 9415 */ "#TC_RETURNr \0" + /* 9428 */ "mbar \0" + /* 9434 */ "vstribr \0" + /* 9443 */ "setnbcr \0" + /* 9452 */ "setbcr \0" + /* 9460 */ "mfdcr \0" + /* 9467 */ "rldcr \0" + /* 9474 */ "mtdcr \0" + /* 9481 */ "mfcr \0" + /* 9487 */ "rldicr \0" + /* 9495 */ "mfvscr \0" + /* 9503 */ "mtvscr \0" + /* 9511 */ "pmxvf32ger \0" + /* 9523 */ "pmxvf64ger \0" + /* 9535 */ "vncipher \0" + /* 9545 */ "vcipher \0" + /* 9554 */ "vstrihr \0" + /* 9563 */ "bclr \0" + /* 9569 */ "mflr \0" + /* 9575 */ "mtlr \0" + /* 9581 */ "fmr \0" + /* 9586 */ "mfpmr \0" + /* 9593 */ "mtpmr \0" + /* 9600 */ "vpermr \0" + /* 9608 */ "xxpermr \0" + /* 9617 */ "xxlor \0" + /* 9624 */ "xxlnor \0" + /* 9632 */ "crnor \0" + /* 9639 */ "evnor \0" + /* 9646 */ "cror \0" + /* 9652 */ "evor \0" + /* 9658 */ "xxlxor \0" + /* 9666 */ "vpermxor \0" + /* 9676 */ "crxor \0" + /* 9683 */ "evxor \0" + /* 9690 */ "mfspr \0" + /* 9697 */ "mtspr \0" + /* 9704 */ "mfsr \0" + /* 9710 */ "mfmsr \0" + /* 9717 */ "mtmsr \0" + /* 9724 */ "mtsr \0" + /* 9730 */ "lvsr \0" + /* 9736 */ "bcctr \0" + /* 9743 */ "mfctr \0" + /* 9750 */ "mtctr \0" + /* 9757 */ "pmxvi16ger2s \0" + /* 9771 */ "efdabs \0" + /* 9779 */ "fabs \0" + /* 9785 */ "efdnabs \0" + /* 9794 */ "fnabs \0" + /* 9801 */ "efsnabs \0" + /* 9810 */ "evfsnabs \0" + /* 9820 */ "efsabs \0" + /* 9828 */ "evfsabs \0" + /* 9837 */ "evabs \0" + /* 9844 */ "vsum4sbs \0" + /* 9854 */ "vsubsbs \0" + /* 9863 */ "vaddsbs \0" + /* 9872 */ "vsum4ubs \0" + /* 9882 */ "vsububs \0" + /* 9891 */ "vaddubs \0" + /* 9900 */ "fsubs \0" + /* 9907 */ "fmsubs \0" + /* 9915 */ "fnmsubs \0" + /* 9924 */ "fadds \0" + /* 9931 */ "fmadds \0" + /* 9939 */ "fnmadds \0" + /* 9948 */ "fcfids \0" + /* 9956 */ "dcbtds \0" + /* 9964 */ "dcbtstds \0" + /* 9974 */ "xscvdpsxds \0" + /* 9986 */ "xvcvdpsxds \0" + /* 9998 */ "xvcvspsxds \0" + /* 10010 */ "xscvdpuxds \0" + /* 10022 */ "xvcvdpuxds \0" + /* 10034 */ "xvcvspuxds \0" + /* 10046 */ "fres \0" + /* 10052 */ "frsqrtes \0" + /* 10062 */ "efdcfs \0" + /* 10070 */ "mffs \0" + /* 10076 */ "plfs \0" + /* 10082 */ "mcrfs \0" + /* 10089 */ "pstfs \0" + /* 10096 */ "vsum4shs \0" + /* 10106 */ "vsubshs \0" + /* 10115 */ "vmhaddshs \0" + /* 10126 */ "vmhraddshs \0" + /* 10138 */ "vaddshs \0" + /* 10147 */ "vmsumshs \0" + /* 10157 */ "vsubuhs \0" + /* 10166 */ "vadduhs \0" + /* 10175 */ "vmsumuhs \0" + /* 10185 */ "subis \0" + /* 10192 */ "subpcis \0" + /* 10201 */ "addpcis \0" + /* 10210 */ "addis \0" + /* 10217 */ "lis \0" + /* 10222 */ "xoris \0" + /* 10229 */ "evsrwis \0" + /* 10238 */ "icbtls \0" + /* 10246 */ "fmuls \0" + /* 10253 */ "evlwhos \0" + /* 10262 */ "dcbfps \0" + /* 10270 */ "dcbstps \0" + /* 10279 */ "vpksdss \0" + /* 10288 */ "vpkshss \0" + /* 10297 */ "vpkswss \0" + /* 10306 */ "evcmpgts \0" + /* 10316 */ "evcmplts \0" + /* 10326 */ "fsqrts \0" + /* 10334 */ "fcfidus \0" + /* 10343 */ "vpksdus \0" + /* 10352 */ "vpkudus \0" + /* 10361 */ "vpkshus \0" + /* 10370 */ "vpkuhus \0" + /* 10379 */ "vpkswus \0" + /* 10388 */ "vpkuwus \0" + /* 10397 */ "fdivs \0" + /* 10404 */ "evsrws \0" + /* 10412 */ "mtvsrws \0" + /* 10421 */ "vsum2sws \0" + /* 10431 */ "vsubsws \0" + /* 10440 */ "vaddsws \0" + /* 10449 */ "vsumsws \0" + /* 10458 */ "vsubuws \0" + /* 10467 */ "vadduws \0" + /* 10476 */ "evdivws \0" + /* 10485 */ "xscvdpsxws \0" + /* 10497 */ "xvcvdpsxws \0" + /* 10509 */ "xvcvspsxws \0" + /* 10521 */ "xscvdpuxws \0" + /* 10533 */ "xvcvdpuxws \0" + /* 10545 */ "xvcvspuxws \0" + /* 10557 */ "vctsxs \0" + /* 10565 */ "vctuxs \0" + /* 10573 */ "ldat \0" + /* 10579 */ "stdat \0" + /* 10586 */ "evlhhesplat \0" + /* 10599 */ "evlwhsplat \0" + /* 10611 */ "evlhhossplat \0" + /* 10625 */ "evlhhousplat \0" + /* 10639 */ "evlwwsplat \0" + /* 10651 */ "lwat \0" + /* 10657 */ "stwat \0" + /* 10664 */ "dcbt \0" + /* 10670 */ "icbt \0" + /* 10676 */ "dcbtct \0" + /* 10684 */ "dcbtstct \0" + /* 10694 */ "efdcmpgt \0" + /* 10704 */ "efscmpgt \0" + /* 10714 */ "evfscmpgt \0" + /* 10725 */ "efdtstgt \0" + /* 10735 */ "efststgt \0" + /* 10745 */ "evfststgt \0" + /* 10756 */ "wait \0" + /* 10762 */ "efdcmplt \0" + /* 10772 */ "efscmplt \0" + /* 10782 */ "evfscmplt \0" + /* 10793 */ "efdtstlt \0" + /* 10803 */ "efststlt \0" + /* 10813 */ "evfststlt \0" + /* 10824 */ "fsqrt \0" + /* 10831 */ "ftsqrt \0" + /* 10839 */ "vncipherlast \0" + /* 10853 */ "vcipherlast \0" + /* 10866 */ "dcbst \0" + /* 10873 */ "dst \0" + /* 10878 */ "hashst \0" + /* 10886 */ "dcbtst \0" + /* 10894 */ "dstst \0" + /* 10901 */ "dcbtt \0" + /* 10908 */ "dstt \0" + /* 10914 */ "dcbtstt \0" + /* 10923 */ "dststt \0" + /* 10931 */ "lhau \0" + /* 10937 */ "stbu \0" + /* 10943 */ "lfdu \0" + /* 10949 */ "stfdu \0" + /* 10956 */ "maddhdu \0" + /* 10965 */ "mulhdu \0" + /* 10973 */ "fcfidu \0" + /* 10981 */ "fctidu \0" + /* 10989 */ "ldu \0" + /* 10994 */ "stdu \0" + /* 11000 */ "divdu \0" + /* 11007 */ "divdeu \0" + /* 11015 */ "divweu \0" + /* 11023 */ "sthu \0" + /* 11029 */ "evsrwiu \0" + /* 11038 */ "evlwhou \0" + /* 11047 */ "fcmpu \0" + /* 11054 */ "lfsu \0" + /* 11060 */ "stfsu \0" + /* 11067 */ "evcmpgtu \0" + /* 11077 */ "evcmpltu \0" + /* 11087 */ "mulhwu \0" + /* 11095 */ "fctiwu \0" + /* 11103 */ "evsrwu \0" + /* 11111 */ "stwu \0" + /* 11117 */ "evdivwu \0" + /* 11126 */ "lbzu \0" + /* 11132 */ "lhzu \0" + /* 11138 */ "lwzu \0" + /* 11144 */ "slbmfev \0" + /* 11153 */ "efddiv \0" + /* 11161 */ "fdiv \0" + /* 11167 */ "efsdiv \0" + /* 11175 */ "evfsdiv \0" + /* 11184 */ "ftdiv \0" + /* 11191 */ "vslv \0" + /* 11197 */ "xxleqv \0" + /* 11205 */ "creqv \0" + /* 11212 */ "eveqv \0" + /* 11219 */ "vsrv \0" + /* 11225 */ "plxv \0" + /* 11231 */ "pstxv \0" + /* 11238 */ "vextsb2w \0" + /* 11248 */ "vextsh2w \0" + /* 11258 */ "evmhesmfaaw \0" + /* 11271 */ "evmhosmfaaw \0" + /* 11284 */ "evmhessfaaw \0" + /* 11297 */ "evmhossfaaw \0" + /* 11310 */ "evaddsmiaaw \0" + /* 11323 */ "evmhesmiaaw \0" + /* 11336 */ "evsubfsmiaaw \0" + /* 11350 */ "evmwlsmiaaw \0" + /* 11363 */ "evmhosmiaaw \0" + /* 11376 */ "evaddumiaaw \0" + /* 11389 */ "evmheumiaaw \0" + /* 11402 */ "evsubfumiaaw \0" + /* 11416 */ "evmwlumiaaw \0" + /* 11429 */ "evmhoumiaaw \0" + /* 11442 */ "evaddssiaaw \0" + /* 11455 */ "evmhessiaaw \0" + /* 11468 */ "evsubfssiaaw \0" + /* 11482 */ "evmwlssiaaw \0" + /* 11495 */ "evmhossiaaw \0" + /* 11508 */ "evaddusiaaw \0" + /* 11521 */ "evmheusiaaw \0" + /* 11534 */ "evsubfusiaaw \0" + /* 11548 */ "evmwlusiaaw \0" + /* 11561 */ "evmhousiaaw \0" + /* 11574 */ "vshasigmaw \0" + /* 11586 */ "vsraw \0" + /* 11593 */ "vcntmbw \0" + /* 11602 */ "vprtybw \0" + /* 11611 */ "evaddw \0" + /* 11619 */ "evldw \0" + /* 11626 */ "evrndw \0" + /* 11634 */ "evstdw \0" + /* 11642 */ "vmrgew \0" + /* 11650 */ "vcmpnew \0" + /* 11659 */ "evsubfw \0" + /* 11668 */ "evsubifw \0" + /* 11678 */ "vnegw \0" + /* 11685 */ "vmrghw \0" + /* 11693 */ "xxmrghw \0" + /* 11702 */ "mulhw \0" + /* 11709 */ "evaddiw \0" + /* 11718 */ "fctiw \0" + /* 11725 */ "xxspltiw \0" + /* 11735 */ "vmrglw \0" + /* 11743 */ "xxmrglw \0" + /* 11752 */ "mullw \0" + /* 11759 */ "cmplw \0" + /* 11766 */ "evrlw \0" + /* 11773 */ "evslw \0" + /* 11780 */ "lmw \0" + /* 11785 */ "stmw \0" + /* 11791 */ "vpmsumw \0" + /* 11800 */ "evmhesmfanw \0" + /* 11813 */ "evmhosmfanw \0" + /* 11826 */ "evmhessfanw \0" + /* 11839 */ "evmhossfanw \0" + /* 11852 */ "evmhesmianw \0" + /* 11865 */ "evmwlsmianw \0" + /* 11878 */ "evmhosmianw \0" + /* 11891 */ "evmheumianw \0" + /* 11904 */ "evmwlumianw \0" + /* 11917 */ "evmhoumianw \0" + /* 11930 */ "evmhessianw \0" + /* 11943 */ "evmwlssianw \0" + /* 11956 */ "evmhossianw \0" + /* 11969 */ "evmheusianw \0" + /* 11982 */ "evmwlusianw \0" + /* 11995 */ "evmhousianw \0" + /* 12008 */ "vmrgow \0" + /* 12016 */ "cmpw \0" + /* 12022 */ "xxbrw \0" + /* 12029 */ "vsrw \0" + /* 12035 */ "vmodsw \0" + /* 12043 */ "vmulesw \0" + /* 12052 */ "vdivesw \0" + /* 12061 */ "vavgsw \0" + /* 12069 */ "vupkhsw \0" + /* 12078 */ "vmulhsw \0" + /* 12087 */ "vspltisw \0" + /* 12097 */ "vupklsw \0" + /* 12106 */ "evcntlsw \0" + /* 12116 */ "vminsw \0" + /* 12124 */ "vinsw \0" + /* 12131 */ "vmulosw \0" + /* 12140 */ "vcmpgtsw \0" + /* 12150 */ "extsw \0" + /* 12157 */ "vdivsw \0" + /* 12165 */ "vmaxsw \0" + /* 12173 */ "vspltw \0" + /* 12181 */ "xxspltw \0" + /* 12190 */ "vpopcntw \0" + /* 12200 */ "vinsertw \0" + /* 12210 */ "xxinsertw \0" + /* 12221 */ "pstw \0" + /* 12227 */ "vsubcuw \0" + /* 12236 */ "vaddcuw \0" + /* 12245 */ "vmoduw \0" + /* 12253 */ "vabsduw \0" + /* 12262 */ "vmuleuw \0" + /* 12271 */ "vdiveuw \0" + /* 12280 */ "vavguw \0" + /* 12288 */ "vmulhuw \0" + /* 12297 */ "vminuw \0" + /* 12305 */ "vmulouw \0" + /* 12314 */ "vcmpequw \0" + /* 12324 */ "vextractuw \0" + /* 12336 */ "xxextractuw \0" + /* 12349 */ "vcmpgtuw \0" + /* 12359 */ "vdivuw \0" + /* 12367 */ "vmaxuw \0" + /* 12375 */ "xxblendvw \0" + /* 12386 */ "divw \0" + /* 12392 */ "vcmpnezw \0" + /* 12402 */ "vclzw \0" + /* 12409 */ "evcntlzw \0" + /* 12419 */ "vctzw \0" + /* 12426 */ "cnttzw \0" + /* 12434 */ "lxvd2x \0" + /* 12442 */ "stxvd2x \0" + /* 12451 */ "lxvw4x \0" + /* 12459 */ "stxvw4x \0" + /* 12468 */ "lxvb16x \0" + /* 12477 */ "stxvb16x \0" + /* 12487 */ "lxvh8x \0" + /* 12495 */ "stxvh8x \0" + /* 12504 */ "lhax \0" + /* 12510 */ "tlbivax \0" + /* 12519 */ "lfiwax \0" + /* 12527 */ "lxsiwax \0" + /* 12536 */ "lwax \0" + /* 12542 */ "lvebx \0" + /* 12549 */ "stvebx \0" + /* 12557 */ "stxsibx \0" + /* 12566 */ "lxvrbx \0" + /* 12574 */ "stxvrbx \0" + /* 12583 */ "stbx \0" + /* 12589 */ "xxsplti32dx \0" + /* 12602 */ "evlddx \0" + /* 12610 */ "evstddx \0" + /* 12619 */ "lfdx \0" + /* 12625 */ "stfdx \0" + /* 12632 */ "ldx \0" + /* 12637 */ "lxvrdx \0" + /* 12645 */ "stxvrdx \0" + /* 12654 */ "lxsdx \0" + /* 12661 */ "stxsdx \0" + /* 12669 */ "stdx \0" + /* 12675 */ "addex \0" + /* 12682 */ "evlwhex \0" + /* 12691 */ "evstwhex \0" + /* 12701 */ "evstwwex \0" + /* 12711 */ "evldhx \0" + /* 12719 */ "evstdhx \0" + /* 12728 */ "lvehx \0" + /* 12735 */ "stvehx \0" + /* 12743 */ "stxsihx \0" + /* 12752 */ "lxvrhx \0" + /* 12760 */ "stxvrhx \0" + /* 12769 */ "sthx \0" + /* 12775 */ "stbcix \0" + /* 12783 */ "ldcix \0" + /* 12790 */ "stdcix \0" + /* 12798 */ "sthcix \0" + /* 12806 */ "stwcix \0" + /* 12814 */ "lbzcix \0" + /* 12822 */ "lhzcix \0" + /* 12830 */ "lwzcix \0" + /* 12838 */ "xsrqpix \0" + /* 12847 */ "vinsblx \0" + /* 12856 */ "vextublx \0" + /* 12866 */ "vinsdlx \0" + /* 12875 */ "vinshlx \0" + /* 12884 */ "vextuhlx \0" + /* 12894 */ "vinsbvlx \0" + /* 12904 */ "vextdubvlx \0" + /* 12916 */ "vextddvlx \0" + /* 12927 */ "vinshvlx \0" + /* 12937 */ "vextduhvlx \0" + /* 12949 */ "vinswvlx \0" + /* 12959 */ "vextduwvlx \0" + /* 12971 */ "vinswlx \0" + /* 12980 */ "vextuwlx \0" + /* 12990 */ "ldmx \0" + /* 12996 */ "xxpermx \0" + /* 13005 */ "vsbox \0" + /* 13012 */ "evstwhox \0" + /* 13022 */ "evstwwox \0" + /* 13032 */ "lbepx \0" + /* 13039 */ "stbepx \0" + /* 13047 */ "lfdepx \0" + /* 13055 */ "stfdepx \0" + /* 13064 */ "lhepx \0" + /* 13071 */ "sthepx \0" + /* 13079 */ "lwepx \0" + /* 13086 */ "stwepx \0" + /* 13094 */ "vupkhpx \0" + /* 13103 */ "vpkpx \0" + /* 13110 */ "vupklpx \0" + /* 13119 */ "lxsspx \0" + /* 13127 */ "stxsspx \0" + /* 13136 */ "lxvpx \0" + /* 13143 */ "stxvpx \0" + /* 13151 */ "lbarx \0" + /* 13158 */ "ldarx \0" + /* 13165 */ "lharx \0" + /* 13172 */ "lqarx \0" + /* 13179 */ "lwarx \0" + /* 13186 */ "ldbrx \0" + /* 13193 */ "stdbrx \0" + /* 13201 */ "lhbrx \0" + /* 13208 */ "sthbrx \0" + /* 13216 */ "vinsbrx \0" + /* 13225 */ "vextubrx \0" + /* 13235 */ "lwbrx \0" + /* 13242 */ "stwbrx \0" + /* 13250 */ "vinsdrx \0" + /* 13259 */ "vinshrx \0" + /* 13268 */ "vextuhrx \0" + /* 13278 */ "vinsbvrx \0" + /* 13288 */ "vextdubvrx \0" + /* 13300 */ "vextddvrx \0" + /* 13311 */ "vinshvrx \0" + /* 13321 */ "vextduhvrx \0" + /* 13333 */ "vinswvrx \0" + /* 13343 */ "vextduwvrx \0" + /* 13355 */ "vinswrx \0" + /* 13364 */ "vextuwrx \0" + /* 13374 */ "mcrxrx \0" + /* 13382 */ "tlbsx \0" + /* 13389 */ "lxvdsx \0" + /* 13397 */ "vcfsx \0" + /* 13404 */ "lfsx \0" + /* 13410 */ "stfsx \0" + /* 13417 */ "evlwhosx \0" + /* 13427 */ "lxvwsx \0" + /* 13435 */ "evlhhesplatx \0" + /* 13449 */ "evlwhsplatx \0" + /* 13462 */ "evlhhossplatx \0" + /* 13477 */ "evlhhousplatx \0" + /* 13492 */ "evlwwsplatx \0" + /* 13505 */ "lhaux \0" + /* 13512 */ "lwaux \0" + /* 13519 */ "stbux \0" + /* 13526 */ "lfdux \0" + /* 13533 */ "stfdux \0" + /* 13541 */ "ldux \0" + /* 13547 */ "stdux \0" + /* 13554 */ "vcfux \0" + /* 13561 */ "sthux \0" + /* 13568 */ "evlwhoux \0" + /* 13578 */ "lfsux \0" + /* 13585 */ "stfsux \0" + /* 13593 */ "stwux \0" + /* 13600 */ "lbzux \0" + /* 13607 */ "lhzux \0" + /* 13614 */ "lwzux \0" + /* 13621 */ "lvx \0" + /* 13626 */ "stvx \0" + /* 13632 */ "lxvx \0" + /* 13638 */ "stxvx \0" + /* 13645 */ "evldwx \0" + /* 13653 */ "evstdwx \0" + /* 13662 */ "lvewx \0" + /* 13669 */ "stvewx \0" + /* 13677 */ "stfiwx \0" + /* 13685 */ "stxsiwx \0" + /* 13694 */ "lxvrwx \0" + /* 13702 */ "stxvrwx \0" + /* 13711 */ "stwx \0" + /* 13717 */ "lxsibzx \0" + /* 13726 */ "lbzx \0" + /* 13732 */ "lxsihzx \0" + /* 13741 */ "lhzx \0" + /* 13747 */ "lfiwzx \0" + /* 13755 */ "lxsiwzx \0" + /* 13764 */ "lwzx \0" + /* 13770 */ "copy \0" + /* 13776 */ "dcbz \0" + /* 13782 */ "plbz \0" + /* 13788 */ "xxsetaccz \0" + /* 13799 */ "bdz \0" + /* 13804 */ "efdctsidz \0" + /* 13815 */ "fctidz \0" + /* 13823 */ "efdctuidz \0" + /* 13834 */ "xscvqpsdz \0" + /* 13845 */ "xscvqpudz \0" + /* 13856 */ "plhz \0" + /* 13862 */ "vrfiz \0" + /* 13869 */ "xsrdpiz \0" + /* 13878 */ "xvrdpiz \0" + /* 13887 */ "xvrspiz \0" + /* 13896 */ "friz \0" + /* 13902 */ "efdctsiz \0" + /* 13912 */ "efsctsiz \0" + /* 13922 */ "evfsctsiz \0" + /* 13933 */ "efdctuiz \0" + /* 13943 */ "efsctuiz \0" + /* 13953 */ "bdnz \0" + /* 13959 */ "xscvqpsqz \0" + /* 13970 */ "xscvqpuqz \0" + /* 13981 */ "fctiduz \0" + /* 13990 */ "fctiwuz \0" + /* 13999 */ "fctiwz \0" + /* 14007 */ "plwz \0" + /* 14013 */ "mfvsrwz \0" + /* 14022 */ "mtvsrwz \0" + /* 14031 */ "xscvqpswz \0" + /* 14042 */ "xscvqpuwz \0" + /* 14053 */ "bdzlrl+\0" + /* 14061 */ "bdnzlrl+\0" + /* 14070 */ "bdzlr+\0" + /* 14077 */ "bdnzlr+\0" + /* 14085 */ "evsel crD,\0" + /* 14096 */ "bdzlrl-\0" + /* 14104 */ "bdnzlrl-\0" + /* 14113 */ "bdzlr-\0" + /* 14120 */ "bdnzlr-\0" + /* 14128 */ "# XRay Function Patchable RET.\0" + /* 14159 */ "# XRay Typed Event Log.\0" + /* 14183 */ "# XRay Custom Event Log.\0" + /* 14208 */ "# XRay Function Enter.\0" + /* 14231 */ "# XRay Tail Call Exit.\0" + /* 14254 */ "# XRay Function Exit.\0" + /* 14276 */ "trechkpt.\0" + /* 14286 */ "ori 1, 1, 0\0" + /* 14298 */ "ori 2, 2, 0\0" + /* 14310 */ "#ADDISdtprelHA32\0" + /* 14327 */ "#ATOMIC_LOAD_SUB_I32\0" + /* 14348 */ "#ATOMIC_LOAD_ADD_I32\0" + /* 14369 */ "#ATOMIC_LOAD_NAND_I32\0" + /* 14391 */ "#ATOMIC_LOAD_AND_I32\0" + /* 14412 */ "#ATOMIC_LOAD_UMIN_I32\0" + /* 14434 */ "#ATOMIC_LOAD_MIN_I32\0" + /* 14455 */ "#ATOMIC_SWAP_I32\0" + /* 14472 */ "#ATOMIC_LOAD_XOR_I32\0" + /* 14493 */ "#ATOMIC_LOAD_OR_I32\0" + /* 14513 */ "#ATOMIC_LOAD_UMAX_I32\0" + /* 14535 */ "#ATOMIC_LOAD_MAX_I32\0" + /* 14556 */ "#ADDItlsgdL32\0" + /* 14570 */ "#ADDItlsldL32\0" + /* 14584 */ "#LDgotTprelL32\0" + /* 14599 */ "#ADDIdtprelL32\0" + /* 14614 */ "#EH_SJLJ_LONGJMP32\0" + /* 14633 */ "#EH_SJLJ_SETJMP32\0" + /* 14651 */ "#ADDItlsgdLADDR32\0" + /* 14669 */ "#ADDItlsldLADDR32\0" + /* 14687 */ "GETtlsldADDR32\0" + /* 14702 */ "GETtlsADDR32\0" + /* 14715 */ "#PROBED_ALLOCA_32\0" + /* 14733 */ "#PREPARE_PROBED_ALLOCA_32\0" + /* 14759 */ "#PROBED_STACKALLOC_32\0" + /* 14781 */ "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32\0" + /* 14824 */ "#DFLOADf32\0" + /* 14835 */ "#XFLOADf32\0" + /* 14846 */ "#DFSTOREf32\0" + /* 14858 */ "#XFSTOREf32\0" + /* 14870 */ "#ATOMIC_LOAD_SUB_I64\0" + /* 14891 */ "#ATOMIC_LOAD_ADD_I64\0" + /* 14912 */ "#ATOMIC_LOAD_NAND_I64\0" + /* 14934 */ "#ATOMIC_LOAD_UMIN_I64\0" + /* 14956 */ "#ATOMIC_LOAD_MIN_I64\0" + /* 14977 */ "#ATOMIC_SWAP_I64\0" + /* 14994 */ "#ATOMIC_CMP_SWAP_I64\0" + /* 15015 */ "#ATOMIC_LOAD_XOR_I64\0" + /* 15036 */ "#ATOMIC_LOAD_OR_I64\0" + /* 15056 */ "#ATOMIC_LOAD_UMAX_I64\0" + /* 15078 */ "#ATOMIC_LOAD_MAX_I64\0" + /* 15099 */ "#EH_SJLJ_LONGJMP64\0" + /* 15118 */ "#EH_SJLJ_SETJMP64\0" + /* 15136 */ "#PROBED_ALLOCA_64\0" + /* 15154 */ "#PREPARE_PROBED_ALLOCA_64\0" + /* 15180 */ "#PROBED_STACKALLOC_64\0" + /* 15202 */ "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64\0" + /* 15245 */ "#DFLOADf64\0" + /* 15256 */ "#XFLOADf64\0" + /* 15267 */ "#DFSTOREf64\0" + /* 15279 */ "#XFSTOREf64\0" + /* 15291 */ "#ATOMIC_LOAD_AND_i64\0" + /* 15312 */ "#SELECT_CC_SPE4\0" + /* 15328 */ "#SELECT_SPE4\0" + /* 15341 */ "#SELECT_CC_F4\0" + /* 15355 */ "#SELECT_F4\0" + /* 15366 */ "#SELECT_CC_I4\0" + /* 15380 */ "#SELECT_I4\0" + /* 15391 */ "crxor 6, 6, 6\0" + /* 15405 */ "creqv 6, 6, 6\0" + /* 15419 */ "#SELECT_CC_F16\0" + /* 15434 */ "#SELECT_F16\0" + /* 15446 */ "#ATOMIC_LOAD_SUB_I16\0" + /* 15467 */ "#ATOMIC_LOAD_ADD_I16\0" + /* 15488 */ "#ATOMIC_LOAD_NAND_I16\0" + /* 15510 */ "#ATOMIC_LOAD_AND_I16\0" + /* 15531 */ "#ATOMIC_LOAD_UMIN_I16\0" + /* 15553 */ "#ATOMIC_LOAD_MIN_I16\0" + /* 15574 */ "#ATOMIC_SWAP_I16\0" + /* 15591 */ "#ATOMIC_LOAD_XOR_I16\0" + /* 15612 */ "#ATOMIC_LOAD_OR_I16\0" + /* 15632 */ "#ATOMIC_LOAD_UMAX_I16\0" + /* 15654 */ "#ATOMIC_LOAD_MAX_I16\0" + /* 15675 */ "#ATOMIC_LOAD_SUB_I128\0" + /* 15697 */ "#ATOMIC_LOAD_ADD_I128\0" + /* 15719 */ "#ATOMIC_LOAD_NAND_I128\0" + /* 15742 */ "#ATOMIC_LOAD_AND_I128\0" + /* 15764 */ "#ATOMIC_SWAP_I128\0" + /* 15782 */ "#ATOMIC_CMP_SWAP_I128\0" + /* 15804 */ "#ATOMIC_LOAD_XOR_I128\0" + /* 15826 */ "#ATOMIC_LOAD_OR_I128\0" + /* 15847 */ "#ADDIStocHA8\0" + /* 15860 */ "#DYNALLOC8\0" + /* 15871 */ "#CFENCE8\0" + /* 15880 */ "#SELECT_CC_F8\0" + /* 15894 */ "#SELECT_F8\0" + /* 15905 */ "#ATOMIC_LOAD_SUB_I8\0" + /* 15925 */ "#SELECT_CC_I8\0" + /* 15939 */ "#ATOMIC_LOAD_ADD_I8\0" + /* 15959 */ "#ATOMIC_LOAD_NAND_I8\0" + /* 15980 */ "#ATOMIC_LOAD_AND_I8\0" + /* 16000 */ "#ATOMIC_LOAD_UMIN_I8\0" + /* 16021 */ "#ATOMIC_LOAD_MIN_I8\0" + /* 16041 */ "#ATOMIC_CMP_SWAP_I8\0" + /* 16061 */ "ATOMIC_LOAD_XOR_I8\0" + /* 16080 */ "#ATOMIC_LOAD_OR_I8\0" + /* 16099 */ "#SELECT_I8\0" + /* 16110 */ "#ATOMIC_LOAD_UMAX_I8\0" + /* 16131 */ "#ATOMIC_LOAD_MAX_I8\0" + /* 16151 */ "#MovePCtoLR8\0" + /* 16164 */ "#DYNAREAOFFSET8\0" + /* 16180 */ "#ANDI_rec_1_EQ_BIT8\0" + /* 16200 */ "#ANDI_rec_1_GT_BIT8\0" + /* 16220 */ "#TLSGDAIX8\0" + /* 16231 */ "#ATOMIC_SWAP_i8\0" + /* 16247 */ "#ADDIStocHA\0" + /* 16259 */ "#ADDIStlsgdHA\0" + /* 16273 */ "#ADDIStlsldHA\0" + /* 16287 */ "#ADDISgotTprelHA\0" + /* 16304 */ "#ADDISdtprelHA\0" + /* 16319 */ "#ReadTB\0" + /* 16327 */ "#RESTORE_UACC\0" + /* 16341 */ "#SPILL_UACC\0" + /* 16353 */ "#RESTORE_ACC\0" + /* 16366 */ "#SPILL_ACC\0" + /* 16377 */ "#DYNALLOC\0" + /* 16387 */ "#SELECT_CC_VSFRC\0" + /* 16404 */ "#SELECT_VSFRC\0" + /* 16418 */ "#SELECT_CC_VRRC\0" + /* 16434 */ "#SELECT_VRRC\0" + /* 16447 */ "#SELECT_CC_VSSRC\0" + /* 16464 */ "#SELECT_VSSRC\0" + /* 16478 */ "#SELECT_CC_VSRC\0" + /* 16494 */ "#SELECT_VSRC\0" + /* 16507 */ "#SPILLTOVSR_LD\0" + /* 16522 */ "LIFETIME_END\0" + /* 16535 */ "#SETRND\0" + /* 16543 */ "#BUILD_QUADWORD\0" + /* 16559 */ "#RESTORE_QUADWORD\0" + /* 16577 */ "#SPILL_QUADWORD\0" + /* 16593 */ "#SPLIT_QUADWORD\0" + /* 16609 */ "PSEUDO_PROBE\0" + /* 16622 */ "BUNDLE\0" + /* 16629 */ "#SELECT_CC_SPE\0" + /* 16644 */ "#SELECT_SPE\0" + /* 16656 */ "DBG_VALUE\0" + /* 16666 */ "DBG_INSTR_REF\0" + /* 16680 */ "DBG_PHI\0" + /* 16688 */ "#LDtocJTI\0" + /* 16698 */ "DBG_LABEL\0" + /* 16708 */ "#GETtlsldADDRPCREL\0" + /* 16727 */ "#GETtlsADDRPCREL\0" + /* 16744 */ "#LDtocL\0" + /* 16752 */ "#ADDItocL\0" + /* 16762 */ "#LWZtocL\0" + /* 16771 */ "#ADDItlsgdL\0" + /* 16783 */ "#ADDItlsldL\0" + /* 16795 */ "#LDgotTprelL\0" + /* 16808 */ "#ADDIdtprelL\0" + /* 16821 */ "#SETFLM\0" + /* 16829 */ "#LQX_PSEUDO\0" + /* 16841 */ "#STQX_PSEUDO\0" + /* 16854 */ "#PPCEIEIO\0" + /* 16864 */ "#UNENCODED_NOP\0" + /* 16879 */ "#UpdateGBR\0" + /* 16890 */ "#RESTORE_CR\0" + /* 16902 */ "#SPILL_CR\0" + /* 16912 */ "#ADDItlsgdLADDR\0" + /* 16928 */ "#ADDItlsldLADDR\0" + /* 16944 */ "#GETtlsldADDR\0" + /* 16958 */ "#GETtlsADDR\0" + /* 16970 */ "#KILL_PAIR\0" + /* 16981 */ "#MovePCtoLR\0" + /* 16993 */ "#MoveGOTtoLR\0" + /* 17006 */ "#TCHECK_RET\0" + /* 17018 */ "#TBEGIN_RET\0" + /* 17030 */ "#DYNAREAOFFSET\0" + /* 17045 */ "#RESTORE_CRBIT\0" + /* 17060 */ "#SPILL_CRBIT\0" + /* 17073 */ "#ANDI_rec_1_EQ_BIT\0" + /* 17092 */ "#ANDI_rec_1_GT_BIT\0" + /* 17111 */ "#PPC32GOT\0" + /* 17121 */ "#PPC32PICGOT\0" + /* 17134 */ "#LDtocCPT\0" + /* 17144 */ "LIFETIME_START\0" + /* 17159 */ "DBG_VALUE_LIST\0" + /* 17174 */ "#SPILLTOVSR_ST\0" + /* 17189 */ "#LIWAX\0" + /* 17196 */ "#SPILLTOVSR_LDX\0" + /* 17212 */ "GETtlsADDR32AIX\0" + /* 17228 */ "GETtlsADDR64AIX\0" + /* 17244 */ "#TLSGDAIX\0" + /* 17254 */ "#SPILLTOVSR_STX\0" + /* 17270 */ "#STIWX\0" + /* 17277 */ "#LIWZX\0" + /* 17284 */ "bca\0" + /* 17288 */ "slbia\0" + /* 17294 */ "tlbia\0" + /* 17300 */ "bcla\0" + /* 17305 */ "clrbhrb\0" + /* 17313 */ "bc\0" + /* 17316 */ "slbsync\0" + /* 17324 */ "tlbsync\0" + /* 17332 */ "msgsync\0" + /* 17340 */ "isync\0" + /* 17346 */ "msync\0" + /* 17352 */ "#LDtoc\0" + /* 17359 */ "#ADDItoc\0" + /* 17368 */ "#LWZtoc\0" + /* 17376 */ "hrfid\0" + /* 17382 */ "tlbre\0" + /* 17388 */ "tlbwe\0" + /* 17394 */ "#SETRNDi\0" + /* 17403 */ "rfci\0" + /* 17408 */ "rfmci\0" + /* 17414 */ "rfdi\0" + /* 17419 */ "rfi\0" + /* 17423 */ "bcl\0" + /* 17427 */ "#PADDIdtprel\0" + /* 17440 */ "# FEntry call\0" + /* 17454 */ "dssall\0" + /* 17461 */ "blrl\0" + /* 17466 */ "bdzlrl\0" + /* 17473 */ "bdnzlrl\0" + /* 17481 */ "bctrl\0" + /* 17487 */ "attn\0" + /* 17492 */ "eieio\0" + /* 17498 */ "nap\0" + /* 17502 */ "trap\0" + /* 17507 */ "nop\0" + /* 17511 */ "stop\0" + /* 17516 */ "blr\0" + /* 17520 */ "bdzlr\0" + /* 17526 */ "bdnzlr\0" + /* 17533 */ "bctr\0" + /* 17538 */ "cpabort\0" +}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 16657U, // DBG_VALUE + 17160U, // DBG_VALUE_LIST + 16667U, // DBG_INSTR_REF + 16681U, // DBG_PHI + 16699U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 16623U, // BUNDLE + 17145U, // LIFETIME_START + 16523U, // LIFETIME_END + 16610U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 17441U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 14209U, // PATCHABLE_FUNCTION_ENTER + 14129U, // PATCHABLE_RET + 14255U, // PATCHABLE_FUNCTION_EXIT + 14232U, // PATCHABLE_TAIL_CALL + 14184U, // PATCHABLE_EVENT_CALL + 14160U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 15783U, // ATOMIC_CMP_SWAP_I128 + 15698U, // ATOMIC_LOAD_ADD_I128 + 15743U, // ATOMIC_LOAD_AND_I128 + 15720U, // ATOMIC_LOAD_NAND_I128 + 15827U, // ATOMIC_LOAD_OR_I128 + 15676U, // ATOMIC_LOAD_SUB_I128 + 15805U, // ATOMIC_LOAD_XOR_I128 + 15765U, // ATOMIC_SWAP_I128 + 16544U, // BUILD_QUADWORD + 35077U, // BUILD_UACC + 15872U, // CFENCE8 + 1073779510U, // CLRLSLDI + 1073775443U, // CLRLSLDI_rec + 1073780021U, // CLRLSLWI + 1073775552U, // CLRLSLWI_rec + 1073779545U, // CLRRDI + 1073775470U, // CLRRDI_rec + 1073780062U, // CLRRWI + 1073775581U, // CLRRWI_rec + 1119719U, // DCBFL + 1122126U, // DCBFLP + 1124375U, // DCBFPS + 1118355U, // DCBFx + 1124383U, // DCBSTPS + 33630645U, // DCBTCT + 33629925U, // DCBTDS + 33630653U, // DCBTSTCT + 33629933U, // DCBTSTDS + 1125027U, // DCBTSTT + 1124999U, // DCBTSTx + 1125014U, // DCBTT + 1124777U, // DCBTx + 14825U, // DFLOADf32 + 15246U, // DFLOADf64 + 14847U, // DFSTOREf32 + 15268U, // DFSTOREf64 + 1073779520U, // EXTLDI + 1073775454U, // EXTLDI_rec + 1073780047U, // EXTLWI + 1073775572U, // EXTLWI_rec + 1073779569U, // EXTRDI + 1073775497U, // EXTRDI_rec + 1073780086U, // EXTRWI + 1073775608U, // EXTRWI_rec + 1073780031U, // INSLWI + 1073775563U, // INSLWI_rec + 1073779553U, // INSRDI + 1073775479U, // INSRDI_rec + 1073780070U, // INSRWI + 1073775590U, // INSRWI_rec + 16971U, // KILL_PAIR + 67144326U, // LAx + 17190U, // LIWAX + 17278U, // LIWZX + 1073779688U, // RLWIMIbm + 1073775535U, // RLWIMIbm_rec + 1073780664U, // RLWINMbm + 1073775686U, // RLWINMbm_rec + 1073780681U, // RLWNMbm + 1073775695U, // RLWNMbm_rec + 1073779561U, // ROTRDI + 1073775488U, // ROTRDI_rec + 1073780078U, // ROTRWI + 1073775599U, // ROTRWI_rec + 1073779514U, // SLDI + 1073775447U, // SLDI_rec + 1073780025U, // SLWI + 1073775556U, // SLWI_rec + 16508U, // SPILLTOVSR_LD + 17197U, // SPILLTOVSR_LDX + 17175U, // SPILLTOVSR_ST + 17255U, // SPILLTOVSR_STX + 1073779555U, // SRDI + 1073775481U, // SRDI_rec + 1073780072U, // SRWI + 1073775592U, // SRWI_rec + 17271U, // STIWX + 1073779468U, // SUBI + 1073777873U, // SUBIC + 1073775018U, // SUBIC_rec + 1073784778U, // SUBIS + 100706257U, // SUBPCIS + 14836U, // XFLOADf32 + 15257U, // XFLOADf64 + 14859U, // XFSTOREf32 + 15280U, // XFSTOREf64 + 1073778065U, // ADD4 + 1073781223U, // ADD4O + 1073775786U, // ADD4O_rec + 1073778065U, // ADD4TLS + 1073775090U, // ADD4_rec + 1073778065U, // ADD8 + 1073781223U, // ADD8O + 1073775786U, // ADD8O_rec + 1073778065U, // ADD8TLS + 1073778065U, // ADD8TLS_ + 1073775090U, // ADD8_rec + 1073777835U, // ADDC + 1073777835U, // ADDC8 + 1073781208U, // ADDC8O + 1073775769U, // ADDC8O_rec + 1073774985U, // ADDC8_rec + 1073781208U, // ADDCO + 1073775769U, // ADDCO_rec + 1073774985U, // ADDC_rec + 1073778686U, // ADDE + 1073778686U, // ADDE8 + 1073781244U, // ADDE8O + 1073775810U, // ADDE8O_rec + 1073775229U, // ADDE8_rec + 1073781244U, // ADDEO + 1073775810U, // ADDEO_rec + 1073787268U, // ADDEX + 1073787268U, // ADDEX8 + 1073775229U, // ADDE_rec + 1073779496U, // ADDI + 1073779496U, // ADDI8 + 1073777880U, // ADDIC + 1073777880U, // ADDIC8 + 1073775026U, // ADDIC_rec + 1073784803U, // ADDIS + 1073784803U, // ADDIS8 + 16305U, // ADDISdtprelHA + 14311U, // ADDISdtprelHA32 + 16288U, // ADDISgotTprelHA + 16260U, // ADDIStlsgdHA + 16274U, // ADDIStlsldHA + 16248U, // ADDIStocHA + 15848U, // ADDIStocHA8 + 16809U, // ADDIdtprelL + 14600U, // ADDIdtprelL32 + 16772U, // ADDItlsgdL + 14557U, // ADDItlsgdL32 + 16913U, // ADDItlsgdLADDR + 14652U, // ADDItlsgdLADDR32 + 16784U, // ADDItlsldL + 14571U, // ADDItlsldL32 + 16929U, // ADDItlsldLADDR + 14670U, // ADDItlsldLADDR32 + 17360U, // ADDItoc + 16753U, // ADDItocL + 36929U, // ADDME + 36929U, // ADDME8 + 39443U, // ADDME8O + 34012U, // ADDME8O_rec + 33437U, // ADDME8_rec + 39443U, // ADDMEO + 34012U, // ADDMEO_rec + 33437U, // ADDME_rec + 42970U, // ADDPCIS + 36996U, // ADDZE + 36996U, // ADDZE8 + 39468U, // ADDZE8O + 34040U, // ADDZE8O_rec + 33486U, // ADDZE8_rec + 39468U, // ADDZEO + 34040U, // ADDZEO_rec + 33486U, // ADDZE_rec + 100626U, // ADJCALLSTACKDOWN + 100645U, // ADJCALLSTACKUP + 1073778290U, // AND + 1073778290U, // AND8 + 1073775152U, // AND8_rec + 1073777844U, // ANDC + 1073777844U, // ANDC8 + 1073774992U, // ANDC8_rec + 1073774992U, // ANDC_rec + 1073775463U, // ANDI8_rec + 1073776322U, // ANDIS8_rec + 1073776322U, // ANDIS_rec + 1073775463U, // ANDI_rec + 17074U, // ANDI_rec_1_EQ_BIT + 16181U, // ANDI_rec_1_EQ_BIT8 + 17093U, // ANDI_rec_1_GT_BIT + 16201U, // ANDI_rec_1_GT_BIT8 + 1073775152U, // AND_rec + 2283833517U, // ATOMIC_CMP_SWAP_I16 + 2283833443U, // ATOMIC_CMP_SWAP_I32 + 14995U, // ATOMIC_CMP_SWAP_I64 + 16042U, // ATOMIC_CMP_SWAP_I8 + 15468U, // ATOMIC_LOAD_ADD_I16 + 14349U, // ATOMIC_LOAD_ADD_I32 + 14892U, // ATOMIC_LOAD_ADD_I64 + 15940U, // ATOMIC_LOAD_ADD_I8 + 15511U, // ATOMIC_LOAD_AND_I16 + 14392U, // ATOMIC_LOAD_AND_I32 + 15292U, // ATOMIC_LOAD_AND_I64 + 15981U, // ATOMIC_LOAD_AND_I8 + 15655U, // ATOMIC_LOAD_MAX_I16 + 14536U, // ATOMIC_LOAD_MAX_I32 + 15079U, // ATOMIC_LOAD_MAX_I64 + 16132U, // ATOMIC_LOAD_MAX_I8 + 15554U, // ATOMIC_LOAD_MIN_I16 + 14435U, // ATOMIC_LOAD_MIN_I32 + 14957U, // ATOMIC_LOAD_MIN_I64 + 16022U, // ATOMIC_LOAD_MIN_I8 + 15489U, // ATOMIC_LOAD_NAND_I16 + 14370U, // ATOMIC_LOAD_NAND_I32 + 14913U, // ATOMIC_LOAD_NAND_I64 + 15960U, // ATOMIC_LOAD_NAND_I8 + 15613U, // ATOMIC_LOAD_OR_I16 + 14494U, // ATOMIC_LOAD_OR_I32 + 15037U, // ATOMIC_LOAD_OR_I64 + 16081U, // ATOMIC_LOAD_OR_I8 + 15447U, // ATOMIC_LOAD_SUB_I16 + 14328U, // ATOMIC_LOAD_SUB_I32 + 14871U, // ATOMIC_LOAD_SUB_I64 + 15906U, // ATOMIC_LOAD_SUB_I8 + 15633U, // ATOMIC_LOAD_UMAX_I16 + 14514U, // ATOMIC_LOAD_UMAX_I32 + 15057U, // ATOMIC_LOAD_UMAX_I64 + 16111U, // ATOMIC_LOAD_UMAX_I8 + 15532U, // ATOMIC_LOAD_UMIN_I16 + 14413U, // ATOMIC_LOAD_UMIN_I32 + 14935U, // ATOMIC_LOAD_UMIN_I64 + 16001U, // ATOMIC_LOAD_UMIN_I8 + 15592U, // ATOMIC_LOAD_XOR_I16 + 14473U, // ATOMIC_LOAD_XOR_I32 + 15016U, // ATOMIC_LOAD_XOR_I64 + 16062U, // ATOMIC_LOAD_XOR_I8 + 15575U, // ATOMIC_SWAP_I16 + 14456U, // ATOMIC_SWAP_I32 + 14978U, // ATOMIC_SWAP_I64 + 16232U, // ATOMIC_SWAP_I8 + 17488U, // ATTN + 1182406U, // B + 1214911U, // BA + 167805047U, // BC + 3359648U, // BCC + 4408224U, // BCCA + 5456800U, // BCCCTR + 5456800U, // BCCCTR8 + 6505376U, // BCCCTRL + 6505376U, // BCCCTRL8 + 7553952U, // BCCL + 8602528U, // BCCLA + 9651104U, // BCCLR + 10699680U, // BCCLRL + 11567273U, // BCCTR + 11567273U, // BCCTR8 + 11567329U, // BCCTR8n + 11567251U, // BCCTRL + 11567251U, // BCCTRL8 + 11567309U, // BCCTRL8n + 11567309U, // BCCTRLn + 11567329U, // BCCTRn + 1073775703U, // BCDCFN_rec + 1073776090U, // BCDCFSQ_rec + 1073776669U, // BCDCFZ_rec + 1073775712U, // BCDCPSGN_rec + 33936U, // BCDCTN_rec + 34276U, // BCDCTSQ_rec + 1073776685U, // BCDCTZ_rec + 1073775732U, // BCDSETSGN_rec + 1073776198U, // BCDSR_rec + 1073776254U, // BCDS_rec + 1073775042U, // BCDTRUNC_rec + 1073776347U, // BCDUS_rec + 1073775053U, // BCDUTRUNC_rec + 167805055U, // BCL + 11567263U, // BCLR + 11567240U, // BCLRL + 11567299U, // BCLRLn + 11567320U, // BCLRn + 1179725U, // BCLalways + 167805115U, // BCLn + 17534U, // BCTR + 17534U, // BCTR8 + 17482U, // BCTRL + 17482U, // BCTRL8 + 229466U, // BCTRL8_LDinto_toc + 229466U, // BCTRL8_LDinto_toc_RM + 17482U, // BCTRL8_RM + 229480U, // BCTRL_LWZinto_toc + 229480U, // BCTRL_LWZinto_toc_RM + 17482U, // BCTRL_RM + 167805108U, // BCn + 1193602U, // BDNZ + 1193602U, // BDNZ8 + 1215163U, // BDNZA + 1212687U, // BDNZAm + 1212457U, // BDNZAp + 1185384U, // BDNZL + 1215127U, // BDNZLA + 1212671U, // BDNZLAm + 1212441U, // BDNZLAp + 17527U, // BDNZLR + 17527U, // BDNZLR8 + 17474U, // BDNZLRL + 14105U, // BDNZLRLm + 14062U, // BDNZLRLp + 14121U, // BDNZLRm + 14078U, // BDNZLRp + 1179934U, // BDNZLm + 1179704U, // BDNZLp + 1179948U, // BDNZm + 1179718U, // BDNZp + 1193448U, // BDZ + 1193448U, // BDZ8 + 1215157U, // BDZA + 1212680U, // BDZAm + 1212450U, // BDZAp + 1185378U, // BDZL + 1215120U, // BDZLA + 1212663U, // BDZLAm + 1212433U, // BDZLAp + 17521U, // BDZLR + 17521U, // BDZLR8 + 17467U, // BDZLRL + 14097U, // BDZLRLm + 14054U, // BDZLRLp + 14114U, // BDZLRm + 14071U, // BDZLRp + 1179927U, // BDZLm + 1179697U, // BDZLp + 1179942U, // BDZm + 1179712U, // BDZp + 1185198U, // BL + 1185198U, // BL8 + 12719534U, // BL8_NOP + 12719534U, // BL8_NOP_RM + 12850606U, // BL8_NOP_TLS + 1185198U, // BL8_NOTOC + 1185198U, // BL8_NOTOC_RM + 1316270U, // BL8_NOTOC_TLS + 1185198U, // BL8_RM + 1316270U, // BL8_TLS + 1316270U, // BL8_TLS_ + 1215109U, // BLA + 1215109U, // BLA8 + 12749445U, // BLA8_NOP + 12749445U, // BLA8_NOP_RM + 1215109U, // BLA8_RM + 1215109U, // BLA_RM + 17517U, // BLR + 17517U, // BLR8 + 17462U, // BLRL + 12719534U, // BL_NOP + 12719534U, // BL_NOP_RM + 1185198U, // BL_RM + 1316270U, // BL_TLS + 1073778270U, // BPERMD + 1073777936U, // BRINC + 1073778133U, // CFUGED + 17306U, // CLRBHRB + 1073777468U, // CMPB + 1073777468U, // CMPB8 + 1073778342U, // CMPD + 1073779538U, // CMPDI + 1073777474U, // CMPEQB + 1073778241U, // CMPLD + 1073779502U, // CMPLDI + 1073786352U, // CMPLW + 1073780005U, // CMPLWI + 1275104074U, // CMPRB + 1275104074U, // CMPRB8 + 1073786609U, // CMPW + 1073780055U, // CMPWI + 36822U, // CNTLZD + 1073780497U, // CNTLZDM + 33387U, // CNTLZD_rec + 45180U, // CNTLZW + 45180U, // CNTLZW8 + 34770U, // CNTLZW8_rec + 34770U, // CNTLZW_rec + 36837U, // CNTTZD + 1073780514U, // CNTTZDM + 33396U, // CNTTZD_rec + 45195U, // CNTTZW + 45195U, // CNTTZW8 + 34779U, // CNTTZW8_rec + 34779U, // CNTTZW_rec + 17539U, // CP_ABORT + 46539U, // CP_COPY + 46539U, // CP_COPY8 + 1073775294U, // CP_PASTE8_rec + 1073775294U, // CP_PASTE_rec + 15406U, // CR6SET + 15392U, // CR6UNSET + 1073778320U, // CRAND + 1073777850U, // CRANDC + 1073785798U, // CREQV + 1073778304U, // CRNAND + 1073784225U, // CRNOR + 1073784239U, // CROR + 1073777957U, // CRORC + 1308666822U, // CRSET + 1308665293U, // CRUNSET + 1073784269U, // CRXOR + 3359648U, // CTRL_DEP + 268474815U, // DARN + 1116605U, // DCBA + 13930643U, // DCBF + 1121869U, // DCBFEP + 1118960U, // DCBI + 1124979U, // DCBST + 1121902U, // DCBSTEP + 14985641U, // DCBT + 335462U, // DCBTEP + 14985863U, // DCBTST + 335479U, // DCBTSTEP + 1127889U, // DCBZ + 1121921U, // DCBZEP + 1119835U, // DCBZL + 1121885U, // DCBZLEP + 37650U, // DCCCI + 1073778633U, // DIVD + 1073778692U, // DIVDE + 1073781251U, // DIVDEO + 1073775818U, // DIVDEO_rec + 1073785600U, // DIVDEU + 1073781490U, // DIVDEUO + 1073775907U, // DIVDEUO_rec + 1073776425U, // DIVDEU_rec + 1073775236U, // DIVDE_rec + 1073781237U, // DIVDO + 1073775802U, // DIVDO_rec + 1073785593U, // DIVDU + 1073781482U, // DIVDUO + 1073775898U, // DIVDUO_rec + 1073776417U, // DIVDU_rec + 1073775204U, // DIVD_rec + 1073786979U, // DIVW + 1073778804U, // DIVWE + 1073781284U, // DIVWEO + 1073775855U, // DIVWEO_rec + 1073785608U, // DIVWEU + 1073781499U, // DIVWEUO + 1073775917U, // DIVWEUO_rec + 1073776434U, // DIVWEU_rec + 1073775302U, // DIVWE_rec + 1073781524U, // DIVWO + 1073775945U, // DIVWO_rec + 1073785712U, // DIVWU + 1073781508U, // DIVWUO + 1073775927U, // DIVWUO_rec + 1073776461U, // DIVWU_rec + 1073776576U, // DIVW_rec + 1419308U, // DSS + 17455U, // DSSALL + 1376135802U, // DST + 1376135802U, // DST64 + 1376135823U, // DSTST + 1376135823U, // DSTST64 + 1376135852U, // DSTSTT + 1376135852U, // DSTSTT64 + 1376135837U, // DSTT + 1376135837U, // DSTT64 + 16378U, // DYNALLOC + 15861U, // DYNALLOC8 + 17031U, // DYNAREAOFFSET + 16165U, // DYNAREAOFFSET8 + 42540U, // EFDABS + 1073778062U, // EFDADD + 42831U, // EFDCFS + 37091U, // EFDCFSF + 38043U, // EFDCFSI + 36367U, // EFDCFSID + 37193U, // EFDCFUF + 38109U, // EFDCFUI + 36384U, // EFDCFUID + 1073783720U, // EFDCMPEQ + 1073785287U, // EFDCMPGT + 1073785355U, // EFDCMPLT + 37165U, // EFDCTSF + 38071U, // EFDCTSI + 46573U, // EFDCTSIDZ + 46671U, // EFDCTSIZ + 37221U, // EFDCTUF + 38137U, // EFDCTUI + 46592U, // EFDCTUIDZ + 46702U, // EFDCTUIZ + 1073785746U, // EFDDIV + 1073780258U, // EFDMUL + 42554U, // EFDNABS + 37247U, // EFDNEG + 1073777691U, // EFDSUB + 1073783760U, // EFDTSTEQ + 1073785318U, // EFDTSTGT + 1073785386U, // EFDTSTLT + 42589U, // EFSABS + 1073778091U, // EFSADD + 36317U, // EFSCFD + 37100U, // EFSCFSF + 38052U, // EFSCFSI + 37202U, // EFSCFUF + 38118U, // EFSCFUI + 1073783730U, // EFSCMPEQ + 1073785297U, // EFSCMPGT + 1073785365U, // EFSCMPLT + 37174U, // EFSCTSF + 38080U, // EFSCTSI + 46681U, // EFSCTSIZ + 37230U, // EFSCTUF + 38146U, // EFSCTUI + 46712U, // EFSCTUIZ + 1073785760U, // EFSDIV + 1073780272U, // EFSMUL + 42570U, // EFSNABS + 37261U, // EFSNEG + 1073777720U, // EFSSUB + 1073783770U, // EFSTSTEQ + 1073785328U, // EFSTSTGT + 1073785396U, // EFSTSTLT + 14615U, // EH_SjLj_LongJmp32 + 15100U, // EH_SjLj_LongJmp64 + 14634U, // EH_SjLj_SetJmp32 + 15119U, // EH_SjLj_SetJmp64 + 1179649U, // EH_SjLj_Setup + 1073785793U, // EQV + 1073785793U, // EQV8 + 1073776476U, // EQV8_rec + 1073776476U, // EQV_rec + 42606U, // EVABS + 1107340734U, // EVADDIW + 44079U, // EVADDSMIAAW + 44211U, // EVADDSSIAAW + 44145U, // EVADDUMIAAW + 44277U, // EVADDUSIAAW + 1073786204U, // EVADDW + 1073778327U, // EVAND + 1073777858U, // EVANDC + 1073783751U, // EVCMPEQ + 1073784899U, // EVCMPGTS + 1073785660U, // EVCMPGTU + 1073784909U, // EVCMPLTS + 1073785670U, // EVCMPLTU + 44875U, // EVCNTLSW + 45178U, // EVCNTLZW + 1073785069U, // EVDIVWS + 1073785710U, // EVDIVWU + 1073785805U, // EVEQV + 35751U, // EVEXTSB + 37447U, // EVEXTSH + 42597U, // EVFSABS + 1073778099U, // EVFSADD + 37109U, // EVFSCFSF + 38061U, // EVFSCFSI + 37211U, // EVFSCFUF + 38127U, // EVFSCFUI + 1073783740U, // EVFSCMPEQ + 1073785307U, // EVFSCMPGT + 1073785375U, // EVFSCMPLT + 37183U, // EVFSCTSF + 38089U, // EVFSCTSI + 46691U, // EVFSCTSIZ + 37183U, // EVFSCTUF + 38155U, // EVFSCTUI + 46691U, // EVFSCTUIZ + 1073785768U, // EVFSDIV + 1073780280U, // EVFSMUL + 42579U, // EVFSNABS + 37269U, // EVFSNEG + 1073777728U, // EVFSSUB + 1073783780U, // EVFSTSTEQ + 1073785338U, // EVFSTSTGT + 1073785406U, // EVFSTSTLT + 67145148U, // EVLDD + 134263099U, // EVLDDX + 67146165U, // EVLDH + 134263208U, // EVLDHX + 67153252U, // EVLDW + 134264142U, // EVLDWX + 67152219U, // EVLHHESPLAT + 134263932U, // EVLHHESPLATX + 67152244U, // EVLHHOSSPLAT + 134263959U, // EVLHHOSSPLATX + 67152258U, // EVLHHOUSPLAT + 134263974U, // EVLHHOUSPLATX + 67145762U, // EVLWHE + 134263179U, // EVLWHEX + 67151886U, // EVLWHOS + 134263914U, // EVLWHOSX + 67152671U, // EVLWHOU + 134264065U, // EVLWHOUX + 67152232U, // EVLWHSPLAT + 134263946U, // EVLWHSPLATX + 67152272U, // EVLWWSPLAT + 134263989U, // EVLWWSPLATX + 1073779609U, // EVMERGEHI + 1073781342U, // EVMERGEHILO + 1073781331U, // EVMERGELO + 1073779620U, // EVMERGELOHI + 1073776963U, // EVMHEGSMFAA + 1073780871U, // EVMHEGSMFAN + 1073777011U, // EVMHEGSMIAA + 1073780919U, // EVMHEGSMIAN + 1073777048U, // EVMHEGUMIAA + 1073780956U, // EVMHEGUMIAN + 1073778847U, // EVMHESMF + 1073777096U, // EVMHESMFA + 1073785851U, // EVMHESMFAAW + 1073786393U, // EVMHESMFANW + 1073779704U, // EVMHESMI + 1073777188U, // EVMHESMIA + 1073785916U, // EVMHESMIAAW + 1073786445U, // EVMHESMIANW + 1073778950U, // EVMHESSF + 1073777139U, // EVMHESSFA + 1073785877U, // EVMHESSFAAW + 1073786419U, // EVMHESSFANW + 1073786048U, // EVMHESSIAAW + 1073786523U, // EVMHESSIANW + 1073779743U, // EVMHEUMI + 1073777231U, // EVMHEUMIA + 1073785982U, // EVMHEUMIAAW + 1073786484U, // EVMHEUMIANW + 1073786114U, // EVMHEUSIAAW + 1073786562U, // EVMHEUSIANW + 1073776976U, // EVMHOGSMFAA + 1073780884U, // EVMHOGSMFAN + 1073777024U, // EVMHOGSMIAA + 1073780932U, // EVMHOGSMIAN + 1073777061U, // EVMHOGUMIAA + 1073780969U, // EVMHOGUMIAN + 1073778867U, // EVMHOSMF + 1073777118U, // EVMHOSMFA + 1073785864U, // EVMHOSMFAAW + 1073786406U, // EVMHOSMFANW + 1073779724U, // EVMHOSMI + 1073777210U, // EVMHOSMIA + 1073785956U, // EVMHOSMIAAW + 1073786471U, // EVMHOSMIANW + 1073778970U, // EVMHOSSF + 1073777161U, // EVMHOSSFA + 1073785890U, // EVMHOSSFAAW + 1073786432U, // EVMHOSSFANW + 1073786088U, // EVMHOSSIAAW + 1073786549U, // EVMHOSSIANW + 1073779773U, // EVMHOUMI + 1073777264U, // EVMHOUMIA + 1073786022U, // EVMHOUMIAAW + 1073786510U, // EVMHOUMIANW + 1073786154U, // EVMHOUSIAAW + 1073786588U, // EVMHOUSIANW + 35487U, // EVMRA + 1073778857U, // EVMWHSMF + 1073777107U, // EVMWHSMFA + 1073779714U, // EVMWHSMI + 1073777199U, // EVMWHSMIA + 1073778960U, // EVMWHSSF + 1073777150U, // EVMWHSSFA + 1073779753U, // EVMWHUMI + 1073777242U, // EVMWHUMIA + 1073785943U, // EVMWLSMIAAW + 1073786458U, // EVMWLSMIANW + 1073786075U, // EVMWLSSIAAW + 1073786536U, // EVMWLSSIANW + 1073779763U, // EVMWLUMI + 1073777253U, // EVMWLUMIA + 1073786009U, // EVMWLUMIAAW + 1073786497U, // EVMWLUMIANW + 1073786141U, // EVMWLUSIAAW + 1073786575U, // EVMWLUSIANW + 1073778877U, // EVMWSMF + 1073777129U, // EVMWSMFA + 1073776989U, // EVMWSMFAA + 1073780897U, // EVMWSMFAN + 1073779734U, // EVMWSMI + 1073777221U, // EVMWSMIA + 1073777037U, // EVMWSMIAA + 1073780945U, // EVMWSMIAN + 1073778980U, // EVMWSSF + 1073777172U, // EVMWSSFA + 1073777000U, // EVMWSSFAA + 1073780908U, // EVMWSSFAN + 1073779783U, // EVMWUMI + 1073777275U, // EVMWUMIA + 1073777074U, // EVMWUMIAA + 1073780982U, // EVMWUMIAN + 1073778312U, // EVNAND + 37278U, // EVNEG + 1073784232U, // EVNOR + 1073784245U, // EVOR + 1073777964U, // EVORC + 1073786359U, // EVRLW + 1073780013U, // EVRLWI + 44395U, // EVRNDW + 3237000966U, // EVSEL + 1073786366U, // EVSLW + 1073780039U, // EVSLWI + 335582094U, // EVSPLATFI + 335582419U, // EVSPLATI + 1073784822U, // EVSRWIS + 1073785622U, // EVSRWIU + 1073784997U, // EVSRWS + 1073785696U, // EVSRWU + 67145164U, // EVSTDD + 134263107U, // EVSTDDX + 67146172U, // EVSTDH + 134263216U, // EVSTDHX + 67153267U, // EVSTDW + 134264150U, // EVSTDWX + 67145770U, // EVSTWHE + 134263188U, // EVSTWHEX + 67148362U, // EVSTWHO + 134263509U, // EVSTWHOX + 67145851U, // EVSTWWE + 134263198U, // EVSTWWEX + 67148571U, // EVSTWWO + 134263519U, // EVSTWWOX + 44105U, // EVSUBFSMIAAW + 44237U, // EVSUBFSSIAAW + 44171U, // EVSUBFUMIAAW + 44303U, // EVSUBFUSIAAW + 1073786252U, // EVSUBFW + 369143189U, // EVSUBIFW + 1073784276U, // EVXOR + 35753U, // EXTSB + 35753U, // EXTSB8 + 35753U, // EXTSB8_32_64 + 33096U, // EXTSB8_rec + 33096U, // EXTSB_rec + 37449U, // EXTSH + 37449U, // EXTSH8 + 37449U, // EXTSH8_32_64 + 33546U, // EXTSH8_rec + 33546U, // EXTSH_rec + 44919U, // EXTSW + 1073779652U, // EXTSWSLI + 1073779652U, // EXTSWSLI_32_64 + 1073775515U, // EXTSWSLI_32_64_rec + 1073775515U, // EXTSWSLI_rec + 44919U, // EXTSW_32 + 44919U, // EXTSW_32_64 + 34722U, // EXTSW_32_64_rec + 34722U, // EXTSW_rec + 17493U, // EnforceIEIO + 42548U, // FABSD + 34388U, // FABSD_rec + 42548U, // FABSS + 34388U, // FABSS_rec + 1073778070U, // FADD + 1073784517U, // FADDS + 1073776261U, // FADDS_rec + 1073775089U, // FADD_rec + 0U, // FADDrtz + 36360U, // FCFID + 42717U, // FCFIDS + 34464U, // FCFIDS_rec + 43742U, // FCFIDU + 43103U, // FCFIDUS + 34531U, // FCFIDUS_rec + 34575U, // FCFIDU_rec + 33297U, // FCFID_rec + 1073781372U, // FCMPOD + 1073781372U, // FCMPOS + 1073785640U, // FCMPUD + 1073785640U, // FCMPUS + 1073780993U, // FCPSGND + 1073775723U, // FCPSGND_rec + 1073780993U, // FCPSGNS + 1073775723U, // FCPSGNS_rec + 36377U, // FCTID + 43750U, // FCTIDU + 46750U, // FCTIDUZ + 34870U, // FCTIDUZ_rec + 34584U, // FCTIDU_rec + 46584U, // FCTIDZ + 34836U, // FCTIDZ_rec + 33305U, // FCTID_rec + 44487U, // FCTIW + 43864U, // FCTIWU + 46759U, // FCTIWUZ + 34880U, // FCTIWUZ_rec + 34628U, // FCTIWU_rec + 46768U, // FCTIWZ + 34890U, // FCTIWZ_rec + 34683U, // FCTIW_rec + 1073785754U, // FDIV + 1073784990U, // FDIVS + 1073776365U, // FDIVS_rec + 1073776469U, // FDIV_rec + 1073778076U, // FMADD + 1073784524U, // FMADDS + 1073776269U, // FMADDS_rec + 1073775096U, // FMADD_rec + 42350U, // FMR + 34356U, // FMR_rec + 1073777705U, // FMSUB + 1073784500U, // FMSUBS + 1073776235U, // FMSUBS_rec + 1073774946U, // FMSUB_rec + 1073780266U, // FMUL + 1073784839U, // FMULS + 1073776330U, // FMULS_rec + 1073775661U, // FMUL_rec + 42563U, // FNABSD + 34395U, // FNABSD_rec + 42563U, // FNABSS + 34395U, // FNABSS_rec + 37255U, // FNEGD + 33518U, // FNEGD_rec + 37255U, // FNEGS + 33518U, // FNEGS_rec + 1073778083U, // FNMADD + 1073784532U, // FNMADDS + 1073776278U, // FNMADDS_rec + 1073775104U, // FNMADD_rec + 1073777712U, // FNMSUB + 1073784508U, // FNMSUBS + 1073776244U, // FNMSUBS_rec + 1073774954U, // FNMSUB_rec + 36951U, // FRE + 42815U, // FRES + 34473U, // FRES_rec + 33454U, // FRE_rec + 38826U, // FRIMD + 33855U, // FRIMD_rec + 38826U, // FRIMS + 33855U, // FRIMS_rec + 39184U, // FRIND + 33929U, // FRIND_rec + 39184U, // FRINS + 33929U, // FRINS_rec + 40766U, // FRIPD + 34208U, // FRIPD_rec + 40766U, // FRIPS + 34208U, // FRIPS_rec + 46665U, // FRIZD + 34854U, // FRIZD_rec + 46665U, // FRIZS + 34854U, // FRIZS_rec + 41687U, // FRSP + 34239U, // FRSP_rec + 36964U, // FRSQRTE + 42821U, // FRSQRTES + 34480U, // FRSQRTES_rec + 33460U, // FRSQRTE_rec + 1073780174U, // FSELD + 1073775644U, // FSELD_rec + 1073780174U, // FSELS + 1073775644U, // FSELS_rec + 43593U, // FSQRT + 43095U, // FSQRTS + 34514U, // FSQRTS_rec + 34558U, // FSQRT_rec + 1073777699U, // FSUB + 1073784493U, // FSUBS + 1073776227U, // FSUBS_rec + 1073774939U, // FSUB_rec + 1073785777U, // FTDIV + 43600U, // FTSQRT + 16959U, // GETtlsADDR + 14703U, // GETtlsADDR32 + 17213U, // GETtlsADDR32AIX + 17229U, // GETtlsADDR64AIX + 16728U, // GETtlsADDRPCREL + 16945U, // GETtlsldADDR + 14688U, // GETtlsldADDR32 + 16709U, // GETtlsldADDRPCREL + 402691480U, // HASHCHK + 402693956U, // HASHCHKP + 402696831U, // HASHST + 402695021U, // HASHSTP + 17377U, // HRFID + 1118966U, // ICBI + 1121877U, // ICBIEP + 429321U, // ICBLC + 427474U, // ICBLQ + 436655U, // ICBT + 436223U, // ICBTLS + 37657U, // ICCCI + 1073780180U, // ISEL + 1073780180U, // ISEL8 + 17341U, // ISYNC + 436243078U, // LA + 134263648U, // LBARX + 134263648U, // LBARXL + 134263529U, // LBEPX + 67155416U, // LBZ + 67155416U, // LBZ8 + 1073787407U, // LBZCIX + 469805943U, // LBZU + 469805943U, // LBZU8 + 503362849U, // LBZUX + 503362849U, // LBZUX8 + 134264223U, // LBZX + 134264223U, // LBZX8 + 1073788319U, // LBZXTLS + 1073788319U, // LBZXTLS_ + 1073788319U, // LBZXTLS_32 + 67145261U, // LD + 134263655U, // LDARX + 134263655U, // LDARXL + 1073785166U, // LDAT + 134263683U, // LDBRX + 1073787376U, // LDCIX + 134263487U, // LDMX + 469805806U, // LDU + 503362790U, // LDUX + 134263129U, // LDX + 1073787225U, // LDXTLS + 1073787225U, // LDXTLS_ + 16796U, // LDgotTprelL + 14585U, // LDgotTprelL32 + 17353U, // LDtoc + 17135U, // LDtocBA + 17135U, // LDtocCPT + 16689U, // LDtocJTI + 16745U, // LDtocL + 67145190U, // LFD + 134263544U, // LFDEPX + 469805760U, // LFDU + 503362775U, // LFDUX + 134263116U, // LFDX + 134263016U, // LFIWAX + 134264244U, // LFIWZX + 67151710U, // LFS + 469805871U, // LFSU + 503362827U, // LFSUX + 134263901U, // LFSX + 67144223U, // LHA + 67144223U, // LHA8 + 134263662U, // LHARX + 134263662U, // LHARXL + 469805748U, // LHAU + 469805748U, // LHAU8 + 503362754U, // LHAUX + 503362754U, // LHAUX8 + 134263001U, // LHAX + 134263001U, // LHAX8 + 134263698U, // LHBRX + 134263698U, // LHBRX8 + 134263561U, // LHEPX + 67155490U, // LHZ + 67155490U, // LHZ8 + 1073787415U, // LHZCIX + 469805949U, // LHZU + 469805949U, // LHZU8 + 503362856U, // LHZUX + 503362856U, // LHZUX8 + 134264238U, // LHZX + 134264238U, // LHZX8 + 1073788334U, // LHZXTLS + 1073788334U, // LHZXTLS_ + 1073788334U, // LHZXTLS_32 + 100701108U, // LI + 100701108U, // LI8 + 100706282U, // LIS + 100706282U, // LIS8 + 67153413U, // LMW + 67150833U, // LQ + 134263669U, // LQARX + 134263669U, // LQARXL + 16830U, // LQX_PSEUDO + 1073780094U, // LSWI + 134263039U, // LVEBX + 134263225U, // LVEHX + 134264159U, // LVEWX + 134256156U, // LVSL + 134260227U, // LVSR + 134264118U, // LVX + 134256206U, // LVXL + 67144359U, // LWA + 134263676U, // LWARX + 134263676U, // LWARXL + 1073785244U, // LWAT + 503362761U, // LWAUX + 134263033U, // LWAX + 134263033U, // LWAX_32 + 67144359U, // LWA_32 + 134263732U, // LWBRX + 134263732U, // LWBRX8 + 134263576U, // LWEPX + 67155641U, // LWZ + 67155641U, // LWZ8 + 1073787423U, // LWZCIX + 469805955U, // LWZU + 469805955U, // LWZU8 + 503362863U, // LWZUX + 503362863U, // LWZUX8 + 134264261U, // LWZX + 134264261U, // LWZX8 + 1073788357U, // LWZXTLS + 1073788357U, // LWZXTLS_ + 1073788357U, // LWZXTLS_32 + 17369U, // LWZtoc + 16763U, // LWZtocL + 67145505U, // LXSD + 134263151U, // LXSDX + 134264214U, // LXSIBZX + 134264229U, // LXSIHZX + 134263024U, // LXSIWAX + 134264252U, // LXSIWZX + 67150584U, // LXSSP + 134263616U, // LXSSPX + 67152859U, // LXV + 134262965U, // LXVB16X + 134262931U, // LXVD2X + 134263886U, // LXVDSX + 134262984U, // LXVH8X + 1073780289U, // LXVL + 1073780215U, // LXVLL + 67150711U, // LXVP + 134263633U, // LXVPX + 134263063U, // LXVRBX + 134263134U, // LXVRDX + 134263249U, // LXVRHX + 134264191U, // LXVRWX + 134262948U, // LXVW4X + 134263924U, // LXVWSX + 134264129U, // LXVX + 1073778169U, // MADDHD + 1073785549U, // MADDHDU + 1073778225U, // MADDLD + 1073778225U, // MADDLD8 + 1418453U, // MBAR + 37062U, // MCRF + 42851U, // MCRFS + 1094719U, // MCRXRX + 536907757U, // MFBHRBE + 1090826U, // MFCR + 1090826U, // MFCR8 + 1091088U, // MFCTR + 1091088U, // MFCTR8 + 42229U, // MFDCR + 1091415U, // MFFS + 39374U, // MFFSCDRN + 570463330U, // MFFSCDRNI + 1085430U, // MFFSCE + 39365U, // MFFSCRN + 268473432U, // MFFSCRNI + 1086997U, // MFFSL + 1083067U, // MFFS_rec + 1090914U, // MFLR + 1090914U, // MFLR8 + 1091055U, // MFMSR + 604016844U, // MFOCRF + 604016844U, // MFOCRF8 + 42355U, // MFPMR + 42459U, // MFSPR + 42459U, // MFSPR8 + 637576681U, // MFSR + 39190U, // MFSRIN + 35774U, // MFTB + 16819675U, // MFTB8 + 36539U, // MFVRD + 17868251U, // MFVRSAVE + 17868251U, // MFVRSAVEv + 46782U, // MFVRWZ + 1090840U, // MFVSCR + 36539U, // MFVSRD + 36424U, // MFVSRLD + 46782U, // MFVSRWZ + 1073778380U, // MODSD + 1073786629U, // MODSW + 1073778535U, // MODUD + 1073786839U, // MODUW + 17333U, // MSGSYNC + 17347U, // MSYNC + 37084U, // MTCRF + 37084U, // MTCRF8 + 1091095U, // MTCTR + 1091095U, // MTCTR8 + 1091095U, // MTCTR8loop + 1091095U, // MTCTRloop + 235283715U, // MTDCR + 1411155U, // MTFSB0 + 1411163U, // MTFSB1 + 1073778943U, // MTFSF + 302453638U, // MTFSFI + 671548306U, // MTFSFI_rec + 1512326U, // MTFSFIb + 1073775334U, // MTFSF_rec + 37119U, // MTFSFb + 1090920U, // MTLR + 1090920U, // MTLR8 + 201369078U, // MTMSR + 201363123U, // MTMSRD + 495828U, // MTOCRF + 495828U, // MTOCRF8 + 42362U, // MTPMR + 42466U, // MTSPR + 42466U, // MTSPR8 + 534013U, // MTSR + 39198U, // MTSRIN + 36547U, // MTVRD + 1081579U, // MTVRSAVE + 1442027U, // MTVRSAVEv + 35500U, // MTVRWA + 46791U, // MTVRWZ + 1090848U, // MTVSCR + 38532U, // MTVSRBM + 704680910U, // MTVSRBMI + 36547U, // MTVSRD + 1073778115U, // MTVSRDD + 38604U, // MTVSRDM + 38710U, // MTVSRHM + 38875U, // MTVSRQM + 35500U, // MTVSRWA + 38987U, // MTVSRWM + 43181U, // MTVSRWS + 46791U, // MTVSRWZ + 1073778177U, // MULHD + 1073785558U, // MULHDU + 1073776390U, // MULHDU_rec + 1073775113U, // MULHD_rec + 1073786295U, // MULHW + 1073785680U, // MULHWU + 1073776443U, // MULHWU_rec + 1073776499U, // MULHW_rec + 1073778234U, // MULLD + 1073781229U, // MULLDO + 1073775793U, // MULLDO_rec + 1073775137U, // MULLD_rec + 1073779640U, // MULLI + 1073779640U, // MULLI8 + 1073786345U, // MULLW + 1073781516U, // MULLWO + 1073775936U, // MULLWO_rec + 1073776515U, // MULLW_rec + 16994U, // MoveGOTtoLR + 16982U, // MovePCtoLR + 16152U, // MovePCtoLR8 + 1073778298U, // NAND + 1073778298U, // NAND8 + 1073775151U, // NAND8_rec + 1073775151U, // NAND_rec + 17499U, // NAP + 37250U, // NEG + 37250U, // NEG8 + 39492U, // NEG8O + 34067U, // NEG8O_rec + 33519U, // NEG8_rec + 39492U, // NEGO + 34067U, // NEGO_rec + 33519U, // NEG_rec + 17508U, // NOP + 14287U, // NOP_GT_PWR6 + 14299U, // NOP_GT_PWR7 + 1073784220U, // NOR + 1073784220U, // NOR8 + 1073776186U, // NOR8_rec + 1073776186U, // NOR_rec + 1073784213U, // OR + 1073784213U, // OR8 + 1073776187U, // OR8_rec + 1073777952U, // ORC + 1073777952U, // ORC8 + 1073775065U, // ORC8_rec + 1073775065U, // ORC_rec + 1073779862U, // ORI + 1073779862U, // ORI8 + 1073784816U, // ORIS + 1073784816U, // ORIS8 + 1073776187U, // OR_rec + 1073779495U, // PADDI + 1073779495U, // PADDI8 + 738235175U, // PADDI8pc + 17428U, // PADDIdtprel + 738235175U, // PADDIpc + 1073778335U, // PDEPD + 1073778517U, // PEXTD + 771798487U, // PLBZ + 771798487U, // PLBZ8 + 805352919U, // PLBZ8pc + 805352919U, // PLBZpc + 771788355U, // PLD + 805342787U, // PLDpc + 771788261U, // PLFD + 805342693U, // PLFDpc + 771794781U, // PLFS + 805349213U, // PLFSpc + 771787294U, // PLHA + 771787294U, // PLHA8 + 805341726U, // PLHA8pc + 805341726U, // PLHApc + 771798561U, // PLHZ + 771798561U, // PLHZ8 + 805352993U, // PLHZ8pc + 805352993U, // PLHZpc + 838898623U, // PLI + 838898623U, // PLI8 + 771787430U, // PLWA + 771787430U, // PLWA8 + 805341862U, // PLWA8pc + 805341862U, // PLWApc + 771798712U, // PLWZ + 771798712U, // PLWZ8 + 805353144U, // PLWZ8pc + 805353144U, // PLWZpc + 771788576U, // PLXSD + 805343008U, // PLXSDpc + 771793655U, // PLXSSP + 805348087U, // PLXSSPpc + 771795930U, // PLXV + 771793782U, // PLXVP + 805348214U, // PLXVPpc + 805350362U, // PLXVpc + 1073776761U, // PMXVBF16GER2 + 1375770918U, // PMXVBF16GER2NN + 1375772502U, // PMXVBF16GER2NP + 1375770977U, // PMXVBF16GER2PN + 1375772561U, // PMXVBF16GER2PP + 1073776775U, // PMXVF16GER2 + 1375770934U, // PMXVF16GER2NN + 1375772518U, // PMXVF16GER2NP + 1375770993U, // PMXVF16GER2PN + 1375772577U, // PMXVF16GER2PP + 1073784104U, // PMXVF32GER + 1375770949U, // PMXVF32GERNN + 1375772533U, // PMXVF32GERNP + 1375771019U, // PMXVF32GERPN + 1375772635U, // PMXVF32GERPP + 1073784116U, // PMXVF64GER + 1375770963U, // PMXVF64GERNN + 1375772547U, // PMXVF64GERNP + 1375771033U, // PMXVF64GERPN + 1375772649U, // PMXVF64GERPP + 1073776788U, // PMXVI16GER2 + 1375772592U, // PMXVI16GER2PP + 1073784350U, // PMXVI16GER2S + 1375772663U, // PMXVI16GER2SPP + 1073776889U, // PMXVI4GER8 + 1375772621U, // PMXVI4GER8PP + 1073776801U, // PMXVI8GER4 + 1375772607U, // PMXVI8GER4PP + 1375772679U, // PMXVI8GER4SPP + 35789U, // POPCNTB + 35789U, // POPCNTB8 + 36667U, // POPCNTD + 44960U, // POPCNTW + 17112U, // PPC32GOT + 17122U, // PPC32PICGOT + 14734U, // PREPARE_PROBED_ALLOCA_32 + 15155U, // PREPARE_PROBED_ALLOCA_64 + 14782U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 + 15203U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 + 14716U, // PROBED_ALLOCA_32 + 15137U, // PROBED_ALLOCA_64 + 14760U, // PROBED_STACKALLOC_32 + 15181U, // PROBED_STACKALLOC_64 + 771787744U, // PSTB + 771787744U, // PSTB8 + 805342176U, // PSTB8pc + 805342176U, // PSTBpc + 771788622U, // PSTD + 805343054U, // PSTDpc + 771788267U, // PSTFD + 805342699U, // PSTFDpc + 771794794U, // PSTFS + 805349226U, // PSTFSpc + 771789428U, // PSTH + 771789428U, // PSTH8 + 805343860U, // PSTH8pc + 805343860U, // PSTHpc + 771796926U, // PSTW + 771796926U, // PSTW8 + 805351358U, // PSTW8pc + 805351358U, // PSTWpc + 771788583U, // PSTXSD + 805343015U, // PSTXSDpc + 771793663U, // PSTXSSP + 805348095U, // PSTXSSPpc + 771795936U, // PSTXV + 771793789U, // PSTXVP + 805348221U, // PSTXVPpc + 805350368U, // PSTXVpc + 16855U, // PseudoEIEIO + 16354U, // RESTORE_ACC + 16891U, // RESTORE_CR + 17046U, // RESTORE_CRBIT + 16560U, // RESTORE_QUADWORD + 16328U, // RESTORE_UACC + 17404U, // RFCI + 17415U, // RFDI + 559817U, // RFEBB + 17420U, // RFI + 17378U, // RFID + 17409U, // RFMCI + 1073780151U, // RLDCL + 1073775627U, // RLDCL_rec + 1073784060U, // RLDCR + 1073776153U, // RLDCR_rec + 1073777887U, // RLDIC + 1073780158U, // RLDICL + 1073780158U, // RLDICL_32 + 1073780158U, // RLDICL_32_64 + 1073775635U, // RLDICL_32_rec + 1073775635U, // RLDICL_rec + 1073784080U, // RLDICR + 1073784080U, // RLDICR_32 + 1073776161U, // RLDICR_rec + 1073775034U, // RLDIC_rec + 1375769568U, // RLDIMI + 1375765414U, // RLDIMI_rec + 1375769576U, // RLWIMI + 1375769576U, // RLWIMI8 + 1375765423U, // RLWIMI8_rec + 1375765423U, // RLWIMI_rec + 1073780664U, // RLWINM + 1073780664U, // RLWINM8 + 1073775686U, // RLWINM8_rec + 1073775686U, // RLWINM_rec + 1073780681U, // RLWNM + 1073780681U, // RLWNM8 + 1073775695U, // RLWNM8_rec + 1073775695U, // RLWNM_rec + 16320U, // ReadTB + 1084723U, // SC + 15420U, // SELECT_CC_F16 + 15342U, // SELECT_CC_F4 + 15881U, // SELECT_CC_F8 + 15367U, // SELECT_CC_I4 + 15926U, // SELECT_CC_I8 + 16630U, // SELECT_CC_SPE + 15313U, // SELECT_CC_SPE4 + 16419U, // SELECT_CC_VRRC + 16388U, // SELECT_CC_VSFRC + 16479U, // SELECT_CC_VSRC + 16448U, // SELECT_CC_VSSRC + 15435U, // SELECT_F16 + 15356U, // SELECT_F4 + 15895U, // SELECT_F8 + 15381U, // SELECT_I4 + 16100U, // SELECT_I8 + 16645U, // SELECT_SPE + 15329U, // SELECT_SPE4 + 16435U, // SELECT_VRRC + 16405U, // SELECT_VSFRC + 16495U, // SELECT_VSRC + 16465U, // SELECT_VSSRC + 35768U, // SETB + 35768U, // SETB8 + 35986U, // SETBC + 35986U, // SETBC8 + 42221U, // SETBCR + 42221U, // SETBCR8 + 16822U, // SETFLM + 35978U, // SETNBC + 35978U, // SETNBC8 + 42212U, // SETNBCR + 42212U, // SETNBCR8 + 16536U, // SETRND + 17395U, // SETRNDi + 33420U, // SLBFEE_rec + 17289U, // SLBIA + 1085491U, // SLBIE + 37239U, // SLBIEG + 36875U, // SLBMFEE + 43913U, // SLBMFEV + 36956U, // SLBMTE + 17317U, // SLBSYNC + 1073778264U, // SLD + 1073775145U, // SLD_rec + 1073786368U, // SLW + 1073786368U, // SLW8 + 1073776523U, // SLW8_rec + 1073776523U, // SLW_rec + 67155641U, // SPELWZ + 134264261U, // SPELWZX + 67153855U, // SPESTW + 134264208U, // SPESTWX + 16367U, // SPILL_ACC + 16903U, // SPILL_CR + 17061U, // SPILL_CRBIT + 16578U, // SPILL_QUADWORD + 16342U, // SPILL_UACC + 16594U, // SPLIT_QUADWORD + 1073778031U, // SRAD + 1073779488U, // SRADI + 1073779488U, // SRADI_32 + 1073775435U, // SRADI_rec + 1073775082U, // SRAD_rec + 1073786180U, // SRAW + 1073779989U, // SRAWI + 1073775544U, // SRAWI_rec + 1073776482U, // SRAW_rec + 1073778358U, // SRD + 1073775165U, // SRD_rec + 1073786623U, // SRW + 1073786623U, // SRW8 + 1073776529U, // SRW8_rec + 1073776529U, // SRW_rec + 67144673U, // STB + 67144673U, // STB8 + 1073787368U, // STBCIX + 134252516U, // STBCX + 134263536U, // STBEPX + 470166202U, // STBU + 470166202U, // STBU8 + 503723216U, // STBUX + 503723216U, // STBUX8 + 134263080U, // STBX + 134263080U, // STBX8 + 1073787176U, // STBXTLS + 1073787176U, // STBXTLS_ + 1073787176U, // STBXTLS_32 + 67145551U, // STD + 1073785172U, // STDAT + 134263690U, // STDBRX + 1073787383U, // STDCIX + 134252524U, // STDCX + 470166259U, // STDU + 503723244U, // STDUX + 134263166U, // STDX + 1073787262U, // STDXTLS + 1073787262U, // STDXTLS_ + 67145196U, // STFD + 134263552U, // STFDEPX + 470166214U, // STFDU + 503723230U, // STFDUX + 134263122U, // STFDX + 134264174U, // STFIWX + 67151723U, // STFS + 470166325U, // STFSU + 503723282U, // STFSUX + 134263907U, // STFSX + 67146357U, // STH + 67146357U, // STH8 + 134263705U, // STHBRX + 1073787391U, // STHCIX + 134252532U, // STHCX + 134263568U, // STHEPX + 470166288U, // STHU + 470166288U, // STHU8 + 503723258U, // STHUX + 503723258U, // STHUX8 + 134263266U, // STHX + 134263266U, // STHX8 + 1073787362U, // STHXTLS + 1073787362U, // STHXTLS_ + 1073787362U, // STHXTLS_32 + 67153418U, // STMW + 17512U, // STOP + 67150908U, // STQ + 134252540U, // STQCX + 16842U, // STQX_PSEUDO + 1073780100U, // STSWI + 134263046U, // STVEBX + 134263232U, // STVEHX + 134264166U, // STVEWX + 134264123U, // STVX + 134256212U, // STVXL + 67153855U, // STW + 67153855U, // STW8 + 1073785250U, // STWAT + 134263739U, // STWBRX + 1073787399U, // STWCIX + 134252548U, // STWCX + 134263583U, // STWEPX + 470166376U, // STWU + 470166376U, // STWU8 + 503723290U, // STWUX + 503723290U, // STWUX8 + 134264208U, // STWX + 134264208U, // STWX8 + 1073788304U, // STWXTLS + 1073788304U, // STWXTLS_ + 1073788304U, // STWXTLS_32 + 67145512U, // STXSD + 134263158U, // STXSDX + 134263054U, // STXSIBX + 134263054U, // STXSIBXv + 134263240U, // STXSIHX + 134263240U, // STXSIHXv + 134264182U, // STXSIWX + 67150592U, // STXSSP + 134263624U, // STXSSPX + 67152865U, // STXV + 134262974U, // STXVB16X + 134262939U, // STXVD2X + 134262992U, // STXVH8X + 1073780295U, // STXVL + 1073780222U, // STXVLL + 67150718U, // STXVP + 134263640U, // STXVPX + 134263071U, // STXVRBX + 134263142U, // STXVRDX + 134263257U, // STXVRHX + 134264199U, // STXVRWX + 134262956U, // STXVW4X + 134264135U, // STXVX + 1073778841U, // SUBF + 1073778841U, // SUBF8 + 1073781309U, // SUBF8O + 1073775883U, // SUBF8O_rec + 1073775327U, // SUBF8_rec + 1073777866U, // SUBFC + 1073777866U, // SUBFC8 + 1073781215U, // SUBFC8O + 1073775777U, // SUBFC8O_rec + 1073775010U, // SUBFC8_rec + 1073781215U, // SUBFCO + 1073775777U, // SUBFCO_rec + 1073775010U, // SUBFC_rec + 1073778715U, // SUBFE + 1073778715U, // SUBFE8 + 1073781259U, // SUBFE8O + 1073775827U, // SUBFE8O_rec + 1073775253U, // SUBFE8_rec + 1073781259U, // SUBFEO + 1073775827U, // SUBFEO_rec + 1073775253U, // SUBFE_rec + 1073777894U, // SUBFIC + 1073777894U, // SUBFIC8 + 36936U, // SUBFME + 36936U, // SUBFME8 + 39451U, // SUBFME8O + 34021U, // SUBFME8O_rec + 33445U, // SUBFME8_rec + 39451U, // SUBFMEO + 34021U, // SUBFMEO_rec + 33445U, // SUBFME_rec + 1073781309U, // SUBFO + 1073775883U, // SUBFO_rec + 37003U, // SUBFZE + 37003U, // SUBFZE8 + 39476U, // SUBFZE8O + 34049U, // SUBFZE8O_rec + 33494U, // SUBFZE8_rec + 39476U, // SUBFZEO + 34049U, // SUBFZEO_rec + 33494U, // SUBFZE_rec + 1073775327U, // SUBF_rec + 593175U, // SYNC + 1083125U, // TABORT + 1074102679U, // TABORTDC + 1074103091U, // TABORTDCI + 1074102751U, // TABORTWC + 1074103103U, // TABORTWCI + 1182406U, // TAILB + 1182406U, // TAILB8 + 1214911U, // TAILBA + 1214911U, // TAILBA8 + 17534U, // TAILBCTR + 17534U, // TAILBCTR8 + 558208U, // TBEGIN + 17019U, // TBEGIN_RET + 1086864U, // TCHECK + 17007U, // TCHECK_RET + 2263350U, // TCRETURNai + 2263247U, // TCRETURNai8 + 2231637U, // TCRETURNdi + 2230493U, // TCRETURNdi8 + 2139336U, // TCRETURNri + 2132203U, // TCRETURNri8 + 1074106166U, // TD + 1074107257U, // TDI + 557622U, // TEND + 17295U, // TLBIA + 251007034U, // TLBIE + 1086918U, // TLBIEL + 45279U, // TLBIVAX + 1084970U, // TLBLD + 1086385U, // TLBLI + 17383U, // TLBRE + 1073778768U, // TLBRE2 + 46151U, // TLBSX + 1073787975U, // TLBSX2 + 1073776652U, // TLBSX2D + 17325U, // TLBSYNC + 17389U, // TLBWE + 1073778797U, // TLBWE2 + 17245U, // TLSGDAIX + 16221U, // TLSGDAIX8 + 17503U, // TRAP + 14277U, // TRECHKPT + 1082420U, // TRECLAIM + 558670U, // TSR + 1074114450U, // TW + 1074107787U, // TWI + 16865U, // UNENCODED_NOP + 16880U, // UpdateGBR + 1073777638U, // VABSDUB + 1073779322U, // VABSDUH + 1073786846U, // VABSDUW + 1073783903U, // VADDCUQ + 1073786829U, // VADDCUW + 1073783934U, // VADDECUQ + 1073780748U, // VADDEUQM + 1073782445U, // VADDFP + 1073784456U, // VADDSBS + 1073784731U, // VADDSHS + 1073785033U, // VADDSWS + 1073780386U, // VADDUBM + 1073784484U, // VADDUBS + 1073780458U, // VADDUDM + 1073780585U, // VADDUHM + 1073784759U, // VADDUHS + 1073780729U, // VADDUQM + 1073780841U, // VADDUWM + 1073785060U, // VADDUWS + 1073778328U, // VAND + 1073777859U, // VANDC + 1073777512U, // VAVGSB + 1073779208U, // VAVGSH + 1073786654U, // VAVGSW + 1073777656U, // VAVGUB + 1073779340U, // VAVGUH + 1073786873U, // VAVGUW + 1073778269U, // VBPERMD + 1073783803U, // VBPERMQ + 1375777878U, // VCFSX + 1073787990U, // VCFSX_0 + 1073778132U, // VCFUGED + 1375778035U, // VCFUX + 1073788147U, // VCFUX_0 + 1073784138U, // VCIPHER + 1073785446U, // VCIPHERLAST + 1073777433U, // VCLRLB + 1073777489U, // VCLRRB + 35964U, // VCLZB + 36815U, // VCLZD + 1073780489U, // VCLZDM + 37602U, // VCLZH + 35554U, // VCLZLSBB + 45171U, // VCLZW + 1073782409U, // VCMPBFP + 1073775989U, // VCMPBFP_rec + 1073782508U, // VCMPEQFP + 1073776010U, // VCMPEQFP_rec + 1073777681U, // VCMPEQUB + 1073774928U, // VCMPEQUB_rec + 1073778586U, // VCMPEQUD + 1073775182U, // VCMPEQUD_rec + 1073779365U, // VCMPEQUH + 1073775378U, // VCMPEQUH_rec + 1073783980U, // VCMPEQUQ + 1073776121U, // VCMPEQUQ_rec + 1073786907U, // VCMPEQUW + 1073776554U, // VCMPEQUW_rec + 1073782462U, // VCMPGEFP + 1073775999U, // VCMPGEFP_rec + 1073782518U, // VCMPGTFP + 1073776021U, // VCMPGTFP_rec + 1073777565U, // VCMPGTSB + 1073774909U, // VCMPGTSB_rec + 1073778438U, // VCMPGTSD + 1073775171U, // VCMPGTSD_rec + 1073779261U, // VCMPGTSH + 1073775359U, // VCMPGTSH_rec + 1073783850U, // VCMPGTSQ + 1073776110U, // VCMPGTSQ_rec + 1073786733U, // VCMPGTSW + 1073776535U, // VCMPGTSW_rec + 1073777749U, // VCMPGTUB + 1073774963U, // VCMPGTUB_rec + 1073778596U, // VCMPGTUD + 1073775193U, // VCMPGTUD_rec + 1073779387U, // VCMPGTUH + 1073775389U, // VCMPGTUH_rec + 1073783990U, // VCMPGTUQ + 1073776132U, // VCMPGTUQ_rec + 1073786942U, // VCMPGTUW + 1073776565U, // VCMPGTUW_rec + 1073777398U, // VCMPNEB + 1073774899U, // VCMPNEB_rec + 1073779140U, // VCMPNEH + 1073775349U, // VCMPNEH_rec + 1073786243U, // VCMPNEW + 1073776489U, // VCMPNEW_rec + 1073777778U, // VCMPNEZB + 1073774974U, // VCMPNEZB_rec + 1073779416U, // VCMPNEZH + 1073775400U, // VCMPNEZH_rec + 1073786985U, // VCMPNEZW + 1073776583U, // VCMPNEZW_rec + 1073783842U, // VCMPSQ + 1073783972U, // VCMPUQ + 1073777360U, // VCNTMBB + 1073778044U, // VCNTMBD + 1073779116U, // VCNTMBH + 1073786186U, // VCNTMBW + 1375775038U, // VCTSXS + 1073785150U, // VCTSXS_0 + 1375775046U, // VCTUXS + 1073785158U, // VCTUXS_0 + 35971U, // VCTZB + 36830U, // VCTZD + 1073780506U, // VCTZDM + 37609U, // VCTZH + 35564U, // VCTZLSBB + 45188U, // VCTZW + 1073778396U, // VDIVESD + 1073783833U, // VDIVESQ + 1073786645U, // VDIVESW + 1073778551U, // VDIVEUD + 1073783963U, // VDIVEUQ + 1073786864U, // VDIVEUW + 1073778448U, // VDIVSD + 1073783860U, // VDIVSQ + 1073786750U, // VDIVSW + 1073778606U, // VDIVUD + 1073784000U, // VDIVUQ + 1073786952U, // VDIVUW + 1073785806U, // VEQV + 38511U, // VEXPANDBM + 38593U, // VEXPANDDM + 38699U, // VEXPANDHM + 38864U, // VEXPANDQM + 38976U, // VEXPANDWM + 40655U, // VEXPTEFP + 1073787509U, // VEXTDDVLX + 1073787893U, // VEXTDDVRX + 1073787497U, // VEXTDUBVLX + 1073787881U, // VEXTDUBVRX + 1073787530U, // VEXTDUHVLX + 1073787914U, // VEXTDUHVRX + 1073787552U, // VEXTDUWVLX + 1073787936U, // VEXTDUWVRX + 38541U, // VEXTRACTBM + 1375768367U, // VEXTRACTD + 38613U, // VEXTRACTDM + 38729U, // VEXTRACTHM + 38884U, // VEXTRACTQM + 1375767625U, // VEXTRACTUB + 1375769263U, // VEXTRACTUH + 1375776805U, // VEXTRACTUW + 38996U, // VEXTRACTWM + 36151U, // VEXTSB2D + 36151U, // VEXTSB2Ds + 44007U, // VEXTSB2W + 44007U, // VEXTSB2Ws + 41870U, // VEXTSD2Q + 36161U, // VEXTSH2D + 36161U, // VEXTSH2Ds + 44017U, // VEXTSH2W + 44017U, // VEXTSH2Ws + 36171U, // VEXTSW2D + 36171U, // VEXTSW2Ds + 1073787449U, // VEXTUBLX + 1073787818U, // VEXTUBRX + 1073787477U, // VEXTUHLX + 1073787861U, // VEXTUHRX + 1073787573U, // VEXTUWLX + 1073787957U, // VEXTUWRX + 36213U, // VGBBD + 1073777462U, // VGNB + 1375777328U, // VINSBLX + 1375777697U, // VINSBRX + 1375777375U, // VINSBVLX + 1375777759U, // VINSBVRX + 872451830U, // VINSD + 1375777347U, // VINSDLX + 1375777731U, // VINSDRX + 872451030U, // VINSERTB + 1375768388U, // VINSERTD + 872452714U, // VINSERTH + 1375776681U, // VINSERTW + 1375777356U, // VINSHLX + 1375777740U, // VINSHRX + 1375777408U, // VINSHVLX + 1375777792U, // VINSHVRX + 872460125U, // VINSW + 1375777452U, // VINSWLX + 1375777836U, // VINSWRX + 1375777430U, // VINSWVLX + 1375777814U, // VINSWVRX + 40629U, // VLOGEFP + 1073782436U, // VMADDFP + 1073782528U, // VMAXFP + 1073777584U, // VMAXSB + 1073778456U, // VMAXSD + 1073779280U, // VMAXSH + 1073786758U, // VMAXSW + 1073777759U, // VMAXUB + 1073778614U, // VMAXUD + 1073779397U, // VMAXUH + 1073786960U, // VMAXUW + 1073784708U, // VMHADDSHS + 1073784719U, // VMHRADDSHS + 1073782500U, // VMINFP + 1073777548U, // VMINSB + 1073778414U, // VMINSD + 1073779244U, // VMINSH + 1073786709U, // VMINSW + 1073777664U, // VMINUB + 1073778569U, // VMINUD + 1073779348U, // VMINUH + 1073786890U, // VMINUW + 1073780574U, // VMLADDUHM + 1073778379U, // VMODSD + 1073783825U, // VMODSQ + 1073786628U, // VMODSW + 1073778534U, // VMODUD + 1073783944U, // VMODUQ + 1073786838U, // VMODUW + 1073786235U, // VMRGEW + 1073777407U, // VMRGHB + 1073779149U, // VMRGHH + 1073786278U, // VMRGHW + 1073777425U, // VMRGLB + 1073779157U, // VMRGLH + 1073786328U, // VMRGLW + 1073786601U, // VMRGOW + 1073778524U, // VMSUMCUD + 1073780346U, // VMSUMMBM + 1073780543U, // VMSUMSHM + 1073784740U, // VMSUMSHS + 1073780395U, // VMSUMUBM + 1073780467U, // VMSUMUDM + 1073780594U, // VMSUMUHM + 1073784768U, // VMSUMUHS + 42059U, // VMUL10CUQ + 1073783912U, // VMUL10ECUQ + 1073783952U, // VMUL10EUQ + 42049U, // VMUL10UQ + 1073777503U, // VMULESB + 1073778387U, // VMULESD + 1073779199U, // VMULESH + 1073786636U, // VMULESW + 1073777647U, // VMULEUB + 1073778542U, // VMULEUD + 1073779331U, // VMULEUH + 1073786855U, // VMULEUW + 1073778405U, // VMULHSD + 1073786671U, // VMULHSW + 1073778560U, // VMULHUD + 1073786881U, // VMULHUW + 1073778233U, // VMULLD + 1073777556U, // VMULOSB + 1073778429U, // VMULOSD + 1073779252U, // VMULOSH + 1073786724U, // VMULOSW + 1073777672U, // VMULOUB + 1073778577U, // VMULOUD + 1073779356U, // VMULOUH + 1073786898U, // VMULOUW + 1073780850U, // VMULUWM + 1073778313U, // VNAND + 1073784128U, // VNCIPHER + 1073785432U, // VNCIPHERLAST + 36338U, // VNEGD + 44447U, // VNEGW + 1073782418U, // VNMSUBFP + 1073784233U, // VNOR + 1073784246U, // VOR + 1073777965U, // VORC + 1073778334U, // VPDEPD + 1073780758U, // VPERM + 1073784193U, // VPERMR + 1073784259U, // VPERMXOR + 1073778516U, // VPEXTD + 1073787696U, // VPKPX + 1073784872U, // VPKSDSS + 1073784936U, // VPKSDUS + 1073784881U, // VPKSHSS + 1073784954U, // VPKSHUS + 1073784890U, // VPKSWSS + 1073784972U, // VPKSWUS + 1073780773U, // VPKUDUM + 1073784945U, // VPKUDUS + 1073780782U, // VPKUHUM + 1073784963U, // VPKUHUS + 1073780791U, // VPKUWUM + 1073784981U, // VPKUWUS + 1073777453U, // VPMSUMB + 1073778278U, // VPMSUMD + 1073779177U, // VPMSUMH + 1073786384U, // VPMSUMW + 35788U, // VPOPCNTB + 36666U, // VPOPCNTD + 37472U, // VPOPCNTH + 44959U, // VPOPCNTW + 36229U, // VPRTYBD + 41887U, // VPRTYBQ + 44371U, // VPRTYBW + 40648U, // VREFP + 38792U, // VRFIM + 39177U, // VRFIN + 40732U, // VRFIP + 46631U, // VRFIZ + 1073777441U, // VRLB + 1073778257U, // VRLD + 1073779672U, // VRLDMI + 1073780656U, // VRLDNM + 1073779165U, // VRLH + 1073783791U, // VRLQ + 1073779696U, // VRLQMI + 1073780672U, // VRLQNM + 1073786360U, // VRLW + 1073779792U, // VRLWMI + 1073780680U, // VRLWNM + 40665U, // VRSQRTEFP + 45774U, // VSBOX + 1073780186U, // VSEL + 1073778018U, // VSHASIGMAD + 1073786167U, // VSHASIGMAW + 1073780253U, // VSL + 1073777447U, // VSLB + 1073778263U, // VSLD + 1073779452U, // VSLDBI + 1073779821U, // VSLDOI + 1073779171U, // VSLH + 1073781355U, // VSLO + 1073783797U, // VSLQ + 1073785784U, // VSLV + 1073786367U, // VSLW + 1375767492U, // VSPLTB + 1375767492U, // VSPLTBs + 1375769176U, // VSPLTH + 1375769176U, // VSPLTHs + 335580025U, // VSPLTISB + 335581721U, // VSPLTISH + 335589176U, // VSPLTISW + 1375776654U, // VSPLTW + 1073784324U, // VSR + 1073777346U, // VSRAB + 1073778030U, // VSRAD + 1073779109U, // VSRAH + 1073783704U, // VSRAQ + 1073786179U, // VSRAW + 1073777497U, // VSRB + 1073778365U, // VSRD + 1073779460U, // VSRDBI + 1073779193U, // VSRH + 1073781476U, // VSRO + 1073783819U, // VSRQ + 1073785812U, // VSRV + 1073786622U, // VSRW + 38313U, // VSTRIBL + 33793U, // VSTRIBL_rec + 42203U, // VSTRIBR + 34319U, // VSTRIBR_rec + 38382U, // VSTRIHL + 33827U, // VSTRIHL_rec + 42323U, // VSTRIHR + 34346U, // VSTRIHR_rec + 1073783894U, // VSUBCUQ + 1073786820U, // VSUBCUW + 1073783924U, // VSUBECUQ + 1073780738U, // VSUBEUQM + 1073782428U, // VSUBFP + 1073784447U, // VSUBSBS + 1073784699U, // VSUBSHS + 1073785024U, // VSUBSWS + 1073780377U, // VSUBUBM + 1073784475U, // VSUBUBS + 1073780449U, // VSUBUDM + 1073780565U, // VSUBUHM + 1073784750U, // VSUBUHS + 1073780720U, // VSUBUQM + 1073780832U, // VSUBUWM + 1073785051U, // VSUBUWS + 1073785014U, // VSUM2SWS + 1073784437U, // VSUM4SBS + 1073784689U, // VSUM4SHS + 1073784465U, // VSUM4UBS + 1073785042U, // VSUMSWS + 45863U, // VUPKHPX + 35696U, // VUPKHSB + 37392U, // VUPKHSH + 44838U, // VUPKHSW + 45879U, // VUPKLPX + 35715U, // VUPKLSB + 37411U, // VUPKLSH + 44866U, // VUPKLSW + 1073784277U, // VXOR + 1308665301U, // V_SET0 + 1308665301U, // V_SET0B + 1308665301U, // V_SET0H + 18919224U, // V_SETALLONES + 18919224U, // V_SETALLONESB + 18919224U, // V_SETALLONESH + 600581U, // WAIT + 1085460U, // WRTEE + 1086334U, // WRTEEI + 1073784254U, // XOR + 1073784254U, // XOR8 + 1073776192U, // XOR8_rec + 1073779861U, // XORI + 1073779861U, // XORI8 + 1073784815U, // XORIS + 1073784815U, // XORIS8 + 1073776192U, // XOR_rec + 40355U, // XSABSDP + 41194U, // XSABSQP + 1073781692U, // XSADDDP + 1073782868U, // XSADDQP + 1073781435U, // XSADDQPO + 1073783188U, // XSADDSP + 1073782137U, // XSCMPEQDP + 1073782105U, // XSCMPEXPDP + 1073782966U, // XSCMPEXPQP + 1073781754U, // XSCMPGEDP + 1073782197U, // XSCMPGTDP + 1073782035U, // XSCMPODP + 1073782936U, // XSCMPOQP + 1073782261U, // XSCMPUDP + 1073783037U, // XSCMPUQP + 1073781995U, // XSCPSGNDP + 1073782925U, // XSCPSGNQP + 40712U, // XSCVDPHP + 41122U, // XSCVDPQP + 41626U, // XSCVDPSP + 39348U, // XSCVDPSPN + 42743U, // XSCVDPSXDS + 42743U, // XSCVDPSXDSs + 43254U, // XSCVDPSXWS + 43254U, // XSCVDPSXWSs + 42779U, // XSCVDPUXDS + 42779U, // XSCVDPUXDSs + 43290U, // XSCVDPUXWS + 43290U, // XSCVDPUXWSs + 40221U, // XSCVHPDP + 40231U, // XSCVQPDP + 39537U, // XSCVQPDPO + 46603U, // XSCVQPSDZ + 46728U, // XSCVQPSQZ + 46800U, // XSCVQPSWZ + 46614U, // XSCVQPUDZ + 46739U, // XSCVQPUQZ + 46811U, // XSCVQPUWZ + 41053U, // XSCVSDQP + 40241U, // XSCVSPDP + 39296U, // XSCVSPDPN + 41164U, // XSCVSQQP + 39886U, // XSCVSXDDP + 41382U, // XSCVSXDSP + 41063U, // XSCVUDQP + 41174U, // XSCVUQQP + 39908U, // XSCVUXDDP + 41404U, // XSCVUXDSP + 1073782271U, // XSDIVDP + 1073783047U, // XSDIVQP + 1073781466U, // XSDIVQPO + 1073783602U, // XSDIVSP + 1073782085U, // XSIEXPDP + 1073782956U, // XSIEXPQP + 1375771498U, // XSMADDADP + 1375773014U, // XSMADDASP + 1375771861U, // XSMADDMDP + 1375773296U, // XSMADDMSP + 1375772746U, // XSMADDQP + 1375771312U, // XSMADDQPO + 1073781682U, // XSMAXCDP + 1073782331U, // XSMAXDP + 1073781875U, // XSMAXJDP + 1073781672U, // XSMINCDP + 1073782017U, // XSMINDP + 1073781865U, // XSMINJDP + 1375771452U, // XSMSUBADP + 1375772968U, // XSMSUBASP + 1375771815U, // XSMSUBMDP + 1375773250U, // XSMSUBMSP + 1375772705U, // XSMSUBQP + 1375771279U, // XSMSUBQPO + 1073781885U, // XSMULDP + 1073782916U, // XSMULQP + 1073781445U, // XSMULQPO + 1073783320U, // XSMULSP + 40335U, // XSNABSDP + 41184U, // XSNABSQP + 39992U, // XSNEGDP + 41073U, // XSNEGQP + 1375771474U, // XSNMADDADP + 1375772990U, // XSNMADDASP + 1375771837U, // XSNMADDMDP + 1375773272U, // XSNMADDMSP + 1375772735U, // XSNMADDQP + 1375771300U, // XSNMADDQPO + 1375771428U, // XSNMSUBADP + 1375772944U, // XSNMSUBASP + 1375771791U, // XSNMSUBMDP + 1375773226U, // XSNMSUBMSP + 1375772694U, // XSNMSUBQP + 1375771267U, // XSNMSUBQPO + 38005U, // XSRDPI + 36078U, // XSRDPIC + 38799U, // XSRDPIM + 40739U, // XSRDPIP + 46638U, // XSRDPIZ + 39952U, // XSREDP + 41437U, // XSRESP + 627845U, // XSRQPI + 635431U, // XSRQPIX + 631685U, // XSRQPXP + 41693U, // XSRSP + 39968U, // XSRSQRTEDP + 41453U, // XSRSQRTESP + 40395U, // XSSQRTDP + 41203U, // XSSQRTQP + 39631U, // XSSQRTQPO + 41747U, // XSSQRTSP + 1073781632U, // XSSUBDP + 1073782827U, // XSSUBQP + 1073781402U, // XSSUBQPO + 1073783148U, // XSSUBSP + 1073782280U, // XSTDIVDP + 40405U, // XSTSQRTDP + 1375771538U, // XSTSTDCDP + 1375772724U, // XSTSTDCQP + 1375773054U, // XSTSTDCSP + 40293U, // XSXEXPDP + 41154U, // XSXEXPQP + 40010U, // XSXSIGDP + 41082U, // XSXSIGQP + 40364U, // XVABSDP + 41710U, // XVABSSP + 1073781701U, // XVADDDP + 1073783197U, // XVADDSP + 1073776763U, // XVBF16GER2 + 1375770920U, // XVBF16GER2NN + 1375772504U, // XVBF16GER2NP + 1375770979U, // XVBF16GER2PN + 1375772563U, // XVBF16GER2PP + 1073782148U, // XVCMPEQDP + 1073775965U, // XVCMPEQDP_rec + 1073783500U, // XVCMPEQSP + 1073776051U, // XVCMPEQSP_rec + 1073781765U, // XVCMPGEDP + 1073775953U, // XVCMPGEDP_rec + 1073783250U, // XVCMPGESP + 1073776039U, // XVCMPGESP_rec + 1073782208U, // XVCMPGTDP + 1073775977U, // XVCMPGTDP_rec + 1073783560U, // XVCMPGTSP + 1073776070U, // XVCMPGTSP_rec + 1073782006U, // XVCPSGNDP + 1073783430U, // XVCPSGNSP + 39335U, // XVCVBF16SPN + 41636U, // XVCVDPSP + 42755U, // XVCVDPSXDS + 43266U, // XVCVDPSXWS + 42791U, // XVCVDPUXDS + 43302U, // XVCVDPUXWS + 41646U, // XVCVHPSP + 35011U, // XVCVSPBF16 + 40251U, // XVCVSPDP + 40722U, // XVCVSPHP + 42767U, // XVCVSPSXDS + 43278U, // XVCVSPSXWS + 42803U, // XVCVSPUXDS + 43314U, // XVCVSPUXWS + 39897U, // XVCVSXDDP + 41393U, // XVCVSXDSP + 40485U, // XVCVSXWDP + 41806U, // XVCVSXWSP + 39919U, // XVCVUXDDP + 41415U, // XVCVUXDSP + 40496U, // XVCVUXWDP + 41817U, // XVCVUXWSP + 1073782300U, // XVDIVDP + 1073783621U, // XVDIVSP + 1073776777U, // XVF16GER2 + 1375770936U, // XVF16GER2NN + 1375772520U, // XVF16GER2NP + 1375770995U, // XVF16GER2PN + 1375772579U, // XVF16GER2PP + 1073784106U, // XVF32GER + 1375770951U, // XVF32GERNN + 1375772535U, // XVF32GERNP + 1375771021U, // XVF32GERPN + 1375772637U, // XVF32GERPP + 1073784118U, // XVF64GER + 1375770965U, // XVF64GERNN + 1375772549U, // XVF64GERNP + 1375771035U, // XVF64GERPN + 1375772651U, // XVF64GERPP + 1073776790U, // XVI16GER2 + 1375772594U, // XVI16GER2PP + 1073784352U, // XVI16GER2S + 1375772665U, // XVI16GER2SPP + 1073776891U, // XVI4GER8 + 1375772623U, // XVI4GER8PP + 1073776803U, // XVI8GER4 + 1375772609U, // XVI8GER4PP + 1375772681U, // XVI8GER4SPP + 1073782095U, // XVIEXPDP + 1073783480U, // XVIEXPSP + 1375771509U, // XVMADDADP + 1375773025U, // XVMADDASP + 1375771872U, // XVMADDMDP + 1375773307U, // XVMADDMSP + 1073782340U, // XVMAXDP + 1073783652U, // XVMAXSP + 1073782026U, // XVMINDP + 1073783441U, // XVMINSP + 1375771463U, // XVMSUBADP + 1375772979U, // XVMSUBASP + 1375771826U, // XVMSUBMDP + 1375773261U, // XVMSUBMSP + 1073781894U, // XVMULDP + 1073783329U, // XVMULSP + 40345U, // XVNABSDP + 41700U, // XVNABSSP + 40001U, // XVNEGDP + 41477U, // XVNEGSP + 1375771486U, // XVNMADDADP + 1375773002U, // XVNMADDASP + 1375771849U, // XVNMADDMDP + 1375773284U, // XVNMADDMSP + 1375771440U, // XVNMSUBADP + 1375772956U, // XVNMSUBASP + 1375771803U, // XVNMSUBMDP + 1375773238U, // XVNMSUBMSP + 38013U, // XVRDPI + 36087U, // XVRDPIC + 38808U, // XVRDPIM + 40748U, // XVRDPIP + 46647U, // XVRDPIZ + 39960U, // XVREDP + 41445U, // XVRESP + 38029U, // XVRSPI + 36096U, // XVRSPIC + 38817U, // XVRSPIM + 40757U, // XVRSPIP + 46656U, // XVRSPIZ + 39980U, // XVRSQRTEDP + 41465U, // XVRSQRTESP + 40427U, // XVSQRTDP + 41768U, // XVSQRTSP + 1073781641U, // XVSUBDP + 1073783157U, // XVSUBSP + 1073782290U, // XVTDIVDP + 1073783611U, // XVTDIVSP + 35545U, // XVTLSBB + 40416U, // XVTSQRTDP + 41757U, // XVTSQRTSP + 1375771549U, // XVTSTDCDP + 1375773065U, // XVTSTDCSP + 40303U, // XVXEXPDP + 41666U, // XVXEXPSP + 40020U, // XVXSIGDP + 41486U, // XVXSIGSP + 1073777767U, // XXBLENDVB + 1073778622U, // XXBLENDVD + 1073779405U, // XXBLENDVH + 1073786968U, // XXBLENDVW + 36524U, // XXBRD + 37362U, // XXBRH + 41988U, // XXBRQ + 44791U, // XXBRW + 1073780129U, // XXEVAL + 1073786929U, // XXEXTRACTUW + 1073780405U, // XXGENPCVBM + 1073780477U, // XXGENPCVDM + 1073780604U, // XXGENPCVHM + 1073780859U, // XXGENPCVWM + 1375776691U, // XXINSERTW + 1073778287U, // XXLAND + 1073777841U, // XXLANDC + 1073785790U, // XXLEQV + 1308666814U, // XXLEQVOnes + 1073778295U, // XXLNAND + 1073784217U, // XXLNOR + 1073784210U, // XXLOR + 1073777949U, // XXLORC + 1073784210U, // XXLORf + 1073784251U, // XXLXOR + 1308665275U, // XXLXORdpz + 1308665275U, // XXLXORspz + 1308665275U, // XXLXORz + 1445017U, // XXMFACC + 1073786286U, // XXMRGHW + 1073786336U, // XXMRGLW + 1084578U, // XXMTACC + 1073780765U, // XXPERM + 1073779528U, // XXPERMDI + 1073779528U, // XXPERMDIs + 1073784201U, // XXPERMR + 1073787589U, // XXPERMX + 1073780192U, // XXSEL + 1095133U, // XXSETACCZ + 1073779996U, // XXSLDWI + 1073779996U, // XXSLDWIs + 1744875822U, // XXSPLTI32DX + 906005255U, // XXSPLTIB + 40030U, // XXSPLTIDP + 44494U, // XXSPLTIW + 1073786774U, // XXSPLTW + 1073786774U, // XXSPLTWs + 1074105486U, // gBC + 1074104771U, // gBCA + 20595589U, // gBCAat + 1074112009U, // gBCCTR + 1074107917U, // gBCCTRL + 1074107826U, // gBCL + 1074104970U, // gBCLA + 20595605U, // gBCLAat + 1074111836U, // gBCLR + 1074107910U, // gBCLRL + 21644304U, // gBCLat + 21644194U, // gBCat + }; + + static const uint16_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ATOMIC_CMP_SWAP_I128 + 0U, // ATOMIC_LOAD_ADD_I128 + 0U, // ATOMIC_LOAD_AND_I128 + 0U, // ATOMIC_LOAD_NAND_I128 + 0U, // ATOMIC_LOAD_OR_I128 + 0U, // ATOMIC_LOAD_SUB_I128 + 0U, // ATOMIC_LOAD_XOR_I128 + 0U, // ATOMIC_SWAP_I128 + 0U, // BUILD_QUADWORD + 0U, // BUILD_UACC + 0U, // CFENCE8 + 0U, // CLRLSLDI + 0U, // CLRLSLDI_rec + 130U, // CLRLSLWI + 130U, // CLRLSLWI_rec + 64U, // CLRRDI + 64U, // CLRRDI_rec + 66U, // CLRRWI + 66U, // CLRRWI_rec + 0U, // DCBFL + 0U, // DCBFLP + 0U, // DCBFPS + 0U, // DCBFx + 0U, // DCBSTPS + 0U, // DCBTCT + 0U, // DCBTDS + 0U, // DCBTSTCT + 0U, // DCBTSTDS + 0U, // DCBTSTT + 0U, // DCBTSTx + 0U, // DCBTT + 0U, // DCBTx + 0U, // DFLOADf32 + 0U, // DFLOADf64 + 0U, // DFSTOREf32 + 0U, // DFSTOREf64 + 0U, // EXTLDI + 0U, // EXTLDI_rec + 130U, // EXTLWI + 130U, // EXTLWI_rec + 0U, // EXTRDI + 0U, // EXTRDI_rec + 130U, // EXTRWI + 130U, // EXTRWI_rec + 130U, // INSLWI + 130U, // INSLWI_rec + 0U, // INSRDI + 0U, // INSRDI_rec + 130U, // INSRWI + 130U, // INSRWI_rec + 0U, // KILL_PAIR + 0U, // LAx + 0U, // LIWAX + 0U, // LIWZX + 258U, // RLWIMIbm + 258U, // RLWIMIbm_rec + 258U, // RLWINMbm + 258U, // RLWINMbm_rec + 258U, // RLWNMbm + 258U, // RLWNMbm_rec + 64U, // ROTRDI + 64U, // ROTRDI_rec + 66U, // ROTRWI + 66U, // ROTRWI_rec + 64U, // SLDI + 64U, // SLDI_rec + 66U, // SLWI + 66U, // SLWI_rec + 0U, // SPILLTOVSR_LD + 0U, // SPILLTOVSR_LDX + 0U, // SPILLTOVSR_ST + 0U, // SPILLTOVSR_STX + 64U, // SRDI + 64U, // SRDI_rec + 66U, // SRWI + 66U, // SRWI_rec + 0U, // STIWX + 4U, // SUBI + 4U, // SUBIC + 4U, // SUBIC_rec + 4U, // SUBIS + 0U, // SUBPCIS + 0U, // XFLOADf32 + 0U, // XFLOADf64 + 0U, // XFSTOREf32 + 0U, // XFSTOREf64 + 70U, // ADD4 + 70U, // ADD4O + 70U, // ADD4O_rec + 70U, // ADD4TLS + 70U, // ADD4_rec + 70U, // ADD8 + 70U, // ADD8O + 70U, // ADD8O_rec + 70U, // ADD8TLS + 70U, // ADD8TLS_ + 70U, // ADD8_rec + 70U, // ADDC + 70U, // ADDC8 + 70U, // ADDC8O + 70U, // ADDC8O_rec + 70U, // ADDC8_rec + 70U, // ADDCO + 70U, // ADDCO_rec + 70U, // ADDC_rec + 70U, // ADDE + 70U, // ADDE8 + 70U, // ADDE8O + 70U, // ADDE8O_rec + 70U, // ADDE8_rec + 70U, // ADDEO + 70U, // ADDEO_rec + 390U, // ADDEX + 390U, // ADDEX8 + 70U, // ADDE_rec + 4U, // ADDI + 4U, // ADDI8 + 4U, // ADDIC + 4U, // ADDIC8 + 4U, // ADDIC_rec + 4U, // ADDIS + 4U, // ADDIS8 + 0U, // ADDISdtprelHA + 0U, // ADDISdtprelHA32 + 0U, // ADDISgotTprelHA + 0U, // ADDIStlsgdHA + 0U, // ADDIStlsldHA + 0U, // ADDIStocHA + 0U, // ADDIStocHA8 + 0U, // ADDIdtprelL + 0U, // ADDIdtprelL32 + 0U, // ADDItlsgdL + 0U, // ADDItlsgdL32 + 0U, // ADDItlsgdLADDR + 0U, // ADDItlsgdLADDR32 + 0U, // ADDItlsldL + 0U, // ADDItlsldL32 + 0U, // ADDItlsldLADDR + 0U, // ADDItlsldLADDR32 + 0U, // ADDItoc + 0U, // ADDItocL + 0U, // ADDME + 0U, // ADDME8 + 0U, // ADDME8O + 0U, // ADDME8O_rec + 0U, // ADDME8_rec + 0U, // ADDMEO + 0U, // ADDMEO_rec + 0U, // ADDME_rec + 0U, // ADDPCIS + 0U, // ADDZE + 0U, // ADDZE8 + 0U, // ADDZE8O + 0U, // ADDZE8O_rec + 0U, // ADDZE8_rec + 0U, // ADDZEO + 0U, // ADDZEO_rec + 0U, // ADDZE_rec + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 70U, // AND + 70U, // AND8 + 70U, // AND8_rec + 70U, // ANDC + 70U, // ANDC8 + 70U, // ANDC8_rec + 70U, // ANDC_rec + 8U, // ANDI8_rec + 8U, // ANDIS8_rec + 8U, // ANDIS_rec + 8U, // ANDI_rec + 0U, // ANDI_rec_1_EQ_BIT + 0U, // ANDI_rec_1_EQ_BIT8 + 0U, // ANDI_rec_1_GT_BIT + 0U, // ANDI_rec_1_GT_BIT8 + 70U, // AND_rec + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 0U, // ATTN + 0U, // B + 0U, // BA + 0U, // BC + 0U, // BCC + 0U, // BCCA + 0U, // BCCCTR + 0U, // BCCCTR8 + 0U, // BCCCTRL + 0U, // BCCCTRL8 + 0U, // BCCL + 0U, // BCCLA + 0U, // BCCLR + 0U, // BCCLRL + 0U, // BCCTR + 0U, // BCCTR8 + 0U, // BCCTR8n + 0U, // BCCTRL + 0U, // BCCTRL8 + 0U, // BCCTRL8n + 0U, // BCCTRLn + 0U, // BCCTRn + 74U, // BCDCFN_rec + 74U, // BCDCFSQ_rec + 74U, // BCDCFZ_rec + 70U, // BCDCPSGN_rec + 0U, // BCDCTN_rec + 0U, // BCDCTSQ_rec + 74U, // BCDCTZ_rec + 74U, // BCDSETSGN_rec + 518U, // BCDSR_rec + 518U, // BCDS_rec + 518U, // BCDTRUNC_rec + 70U, // BCDUS_rec + 70U, // BCDUTRUNC_rec + 0U, // BCL + 0U, // BCLR + 0U, // BCLRL + 0U, // BCLRLn + 0U, // BCLRn + 0U, // BCLalways + 0U, // BCLn + 0U, // BCTR + 0U, // BCTR8 + 0U, // BCTRL + 0U, // BCTRL8 + 0U, // BCTRL8_LDinto_toc + 0U, // BCTRL8_LDinto_toc_RM + 0U, // BCTRL8_RM + 0U, // BCTRL_LWZinto_toc + 0U, // BCTRL_LWZinto_toc_RM + 0U, // BCTRL_RM + 0U, // BCn + 0U, // BDNZ + 0U, // BDNZ8 + 0U, // BDNZA + 0U, // BDNZAm + 0U, // BDNZAp + 0U, // BDNZL + 0U, // BDNZLA + 0U, // BDNZLAm + 0U, // BDNZLAp + 0U, // BDNZLR + 0U, // BDNZLR8 + 0U, // BDNZLRL + 0U, // BDNZLRLm + 0U, // BDNZLRLp + 0U, // BDNZLRm + 0U, // BDNZLRp + 0U, // BDNZLm + 0U, // BDNZLp + 0U, // BDNZm + 0U, // BDNZp + 0U, // BDZ + 0U, // BDZ8 + 0U, // BDZA + 0U, // BDZAm + 0U, // BDZAp + 0U, // BDZL + 0U, // BDZLA + 0U, // BDZLAm + 0U, // BDZLAp + 0U, // BDZLR + 0U, // BDZLR8 + 0U, // BDZLRL + 0U, // BDZLRLm + 0U, // BDZLRLp + 0U, // BDZLRm + 0U, // BDZLRp + 0U, // BDZLm + 0U, // BDZLp + 0U, // BDZm + 0U, // BDZp + 0U, // BL + 0U, // BL8 + 0U, // BL8_NOP + 0U, // BL8_NOP_RM + 0U, // BL8_NOP_TLS + 0U, // BL8_NOTOC + 0U, // BL8_NOTOC_RM + 0U, // BL8_NOTOC_TLS + 0U, // BL8_RM + 0U, // BL8_TLS + 0U, // BL8_TLS_ + 0U, // BLA + 0U, // BLA8 + 0U, // BLA8_NOP + 0U, // BLA8_NOP_RM + 0U, // BLA8_RM + 0U, // BLA_RM + 0U, // BLR + 0U, // BLR8 + 0U, // BLRL + 0U, // BL_NOP + 0U, // BL_NOP_RM + 0U, // BL_RM + 0U, // BL_TLS + 70U, // BPERMD + 70U, // BRINC + 70U, // CFUGED + 0U, // CLRBHRB + 70U, // CMPB + 70U, // CMPB8 + 70U, // CMPD + 4U, // CMPDI + 70U, // CMPEQB + 70U, // CMPLD + 8U, // CMPLDI + 70U, // CMPLW + 8U, // CMPLWI + 262U, // CMPRB + 262U, // CMPRB8 + 70U, // CMPW + 4U, // CMPWI + 0U, // CNTLZD + 70U, // CNTLZDM + 0U, // CNTLZD_rec + 0U, // CNTLZW + 0U, // CNTLZW8 + 0U, // CNTLZW8_rec + 0U, // CNTLZW_rec + 0U, // CNTTZD + 70U, // CNTTZDM + 0U, // CNTTZD_rec + 0U, // CNTTZW + 0U, // CNTTZW8 + 0U, // CNTTZW8_rec + 0U, // CNTTZW_rec + 0U, // CP_ABORT + 0U, // CP_COPY + 0U, // CP_COPY8 + 74U, // CP_PASTE8_rec + 74U, // CP_PASTE_rec + 0U, // CR6SET + 0U, // CR6UNSET + 70U, // CRAND + 70U, // CRANDC + 70U, // CREQV + 70U, // CRNAND + 70U, // CRNOR + 70U, // CROR + 70U, // CRORC + 12U, // CRSET + 12U, // CRUNSET + 70U, // CRXOR + 0U, // CTRL_DEP + 0U, // DARN + 0U, // DCBA + 0U, // DCBF + 0U, // DCBFEP + 0U, // DCBI + 0U, // DCBST + 0U, // DCBSTEP + 0U, // DCBT + 0U, // DCBTEP + 0U, // DCBTST + 0U, // DCBTSTEP + 0U, // DCBZ + 0U, // DCBZEP + 0U, // DCBZL + 0U, // DCBZLEP + 0U, // DCCCI + 70U, // DIVD + 70U, // DIVDE + 70U, // DIVDEO + 70U, // DIVDEO_rec + 70U, // DIVDEU + 70U, // DIVDEUO + 70U, // DIVDEUO_rec + 70U, // DIVDEU_rec + 70U, // DIVDE_rec + 70U, // DIVDO + 70U, // DIVDO_rec + 70U, // DIVDU + 70U, // DIVDUO + 70U, // DIVDUO_rec + 70U, // DIVDU_rec + 70U, // DIVD_rec + 70U, // DIVW + 70U, // DIVWE + 70U, // DIVWEO + 70U, // DIVWEO_rec + 70U, // DIVWEU + 70U, // DIVWEUO + 70U, // DIVWEUO_rec + 70U, // DIVWEU_rec + 70U, // DIVWE_rec + 70U, // DIVWO + 70U, // DIVWO_rec + 70U, // DIVWU + 70U, // DIVWUO + 70U, // DIVWUO_rec + 70U, // DIVWU_rec + 70U, // DIVW_rec + 0U, // DSS + 0U, // DSSALL + 14U, // DST + 14U, // DST64 + 14U, // DSTST + 14U, // DSTST64 + 14U, // DSTSTT + 14U, // DSTSTT64 + 14U, // DSTT + 14U, // DSTT64 + 0U, // DYNALLOC + 0U, // DYNALLOC8 + 0U, // DYNAREAOFFSET + 0U, // DYNAREAOFFSET8 + 0U, // EFDABS + 70U, // EFDADD + 0U, // EFDCFS + 0U, // EFDCFSF + 0U, // EFDCFSI + 0U, // EFDCFSID + 0U, // EFDCFUF + 0U, // EFDCFUI + 0U, // EFDCFUID + 70U, // EFDCMPEQ + 70U, // EFDCMPGT + 70U, // EFDCMPLT + 0U, // EFDCTSF + 0U, // EFDCTSI + 0U, // EFDCTSIDZ + 0U, // EFDCTSIZ + 0U, // EFDCTUF + 0U, // EFDCTUI + 0U, // EFDCTUIDZ + 0U, // EFDCTUIZ + 70U, // EFDDIV + 70U, // EFDMUL + 0U, // EFDNABS + 0U, // EFDNEG + 70U, // EFDSUB + 70U, // EFDTSTEQ + 70U, // EFDTSTGT + 70U, // EFDTSTLT + 0U, // EFSABS + 70U, // EFSADD + 0U, // EFSCFD + 0U, // EFSCFSF + 0U, // EFSCFSI + 0U, // EFSCFUF + 0U, // EFSCFUI + 70U, // EFSCMPEQ + 70U, // EFSCMPGT + 70U, // EFSCMPLT + 0U, // EFSCTSF + 0U, // EFSCTSI + 0U, // EFSCTSIZ + 0U, // EFSCTUF + 0U, // EFSCTUI + 0U, // EFSCTUIZ + 70U, // EFSDIV + 70U, // EFSMUL + 0U, // EFSNABS + 0U, // EFSNEG + 70U, // EFSSUB + 70U, // EFSTSTEQ + 70U, // EFSTSTGT + 70U, // EFSTSTLT + 0U, // EH_SjLj_LongJmp32 + 0U, // EH_SjLj_LongJmp64 + 0U, // EH_SjLj_SetJmp32 + 0U, // EH_SjLj_SetJmp64 + 0U, // EH_SjLj_Setup + 70U, // EQV + 70U, // EQV8 + 70U, // EQV8_rec + 70U, // EQV_rec + 0U, // EVABS + 80U, // EVADDIW + 0U, // EVADDSMIAAW + 0U, // EVADDSSIAAW + 0U, // EVADDUMIAAW + 0U, // EVADDUSIAAW + 70U, // EVADDW + 70U, // EVAND + 70U, // EVANDC + 70U, // EVCMPEQ + 70U, // EVCMPGTS + 70U, // EVCMPGTU + 70U, // EVCMPLTS + 70U, // EVCMPLTU + 0U, // EVCNTLSW + 0U, // EVCNTLZW + 70U, // EVDIVWS + 70U, // EVDIVWU + 70U, // EVEQV + 0U, // EVEXTSB + 0U, // EVEXTSH + 0U, // EVFSABS + 70U, // EVFSADD + 0U, // EVFSCFSF + 0U, // EVFSCFSI + 0U, // EVFSCFUF + 0U, // EVFSCFUI + 70U, // EVFSCMPEQ + 70U, // EVFSCMPGT + 70U, // EVFSCMPLT + 0U, // EVFSCTSF + 0U, // EVFSCTSI + 0U, // EVFSCTSIZ + 0U, // EVFSCTUF + 0U, // EVFSCTUI + 0U, // EVFSCTUIZ + 70U, // EVFSDIV + 70U, // EVFSMUL + 0U, // EVFSNABS + 0U, // EVFSNEG + 70U, // EVFSSUB + 70U, // EVFSTSTEQ + 70U, // EVFSTSTGT + 70U, // EVFSTSTLT + 0U, // EVLDD + 0U, // EVLDDX + 0U, // EVLDH + 0U, // EVLDHX + 0U, // EVLDW + 0U, // EVLDWX + 0U, // EVLHHESPLAT + 0U, // EVLHHESPLATX + 0U, // EVLHHOSSPLAT + 0U, // EVLHHOSSPLATX + 0U, // EVLHHOUSPLAT + 0U, // EVLHHOUSPLATX + 0U, // EVLWHE + 0U, // EVLWHEX + 0U, // EVLWHOS + 0U, // EVLWHOSX + 0U, // EVLWHOU + 0U, // EVLWHOUX + 0U, // EVLWHSPLAT + 0U, // EVLWHSPLATX + 0U, // EVLWWSPLAT + 0U, // EVLWWSPLATX + 70U, // EVMERGEHI + 70U, // EVMERGEHILO + 70U, // EVMERGELO + 70U, // EVMERGELOHI + 70U, // EVMHEGSMFAA + 70U, // EVMHEGSMFAN + 70U, // EVMHEGSMIAA + 70U, // EVMHEGSMIAN + 70U, // EVMHEGUMIAA + 70U, // EVMHEGUMIAN + 70U, // EVMHESMF + 70U, // EVMHESMFA + 70U, // EVMHESMFAAW + 70U, // EVMHESMFANW + 70U, // EVMHESMI + 70U, // EVMHESMIA + 70U, // EVMHESMIAAW + 70U, // EVMHESMIANW + 70U, // EVMHESSF + 70U, // EVMHESSFA + 70U, // EVMHESSFAAW + 70U, // EVMHESSFANW + 70U, // EVMHESSIAAW + 70U, // EVMHESSIANW + 70U, // EVMHEUMI + 70U, // EVMHEUMIA + 70U, // EVMHEUMIAAW + 70U, // EVMHEUMIANW + 70U, // EVMHEUSIAAW + 70U, // EVMHEUSIANW + 70U, // EVMHOGSMFAA + 70U, // EVMHOGSMFAN + 70U, // EVMHOGSMIAA + 70U, // EVMHOGSMIAN + 70U, // EVMHOGUMIAA + 70U, // EVMHOGUMIAN + 70U, // EVMHOSMF + 70U, // EVMHOSMFA + 70U, // EVMHOSMFAAW + 70U, // EVMHOSMFANW + 70U, // EVMHOSMI + 70U, // EVMHOSMIA + 70U, // EVMHOSMIAAW + 70U, // EVMHOSMIANW + 70U, // EVMHOSSF + 70U, // EVMHOSSFA + 70U, // EVMHOSSFAAW + 70U, // EVMHOSSFANW + 70U, // EVMHOSSIAAW + 70U, // EVMHOSSIANW + 70U, // EVMHOUMI + 70U, // EVMHOUMIA + 70U, // EVMHOUMIAAW + 70U, // EVMHOUMIANW + 70U, // EVMHOUSIAAW + 70U, // EVMHOUSIANW + 0U, // EVMRA + 70U, // EVMWHSMF + 70U, // EVMWHSMFA + 70U, // EVMWHSMI + 70U, // EVMWHSMIA + 70U, // EVMWHSSF + 70U, // EVMWHSSFA + 70U, // EVMWHUMI + 70U, // EVMWHUMIA + 70U, // EVMWLSMIAAW + 70U, // EVMWLSMIANW + 70U, // EVMWLSSIAAW + 70U, // EVMWLSSIANW + 70U, // EVMWLUMI + 70U, // EVMWLUMIA + 70U, // EVMWLUMIAAW + 70U, // EVMWLUMIANW + 70U, // EVMWLUSIAAW + 70U, // EVMWLUSIANW + 70U, // EVMWSMF + 70U, // EVMWSMFA + 70U, // EVMWSMFAA + 70U, // EVMWSMFAN + 70U, // EVMWSMI + 70U, // EVMWSMIA + 70U, // EVMWSMIAA + 70U, // EVMWSMIAN + 70U, // EVMWSSF + 70U, // EVMWSSFA + 70U, // EVMWSSFAA + 70U, // EVMWSSFAN + 70U, // EVMWUMI + 70U, // EVMWUMIA + 70U, // EVMWUMIAA + 70U, // EVMWUMIAN + 70U, // EVNAND + 0U, // EVNEG + 70U, // EVNOR + 70U, // EVOR + 70U, // EVORC + 70U, // EVRLW + 66U, // EVRLWI + 0U, // EVRNDW + 0U, // EVSEL + 70U, // EVSLW + 66U, // EVSLWI + 0U, // EVSPLATFI + 0U, // EVSPLATI + 66U, // EVSRWIS + 66U, // EVSRWIU + 70U, // EVSRWS + 70U, // EVSRWU + 0U, // EVSTDD + 0U, // EVSTDDX + 0U, // EVSTDH + 0U, // EVSTDHX + 0U, // EVSTDW + 0U, // EVSTDWX + 0U, // EVSTWHE + 0U, // EVSTWHEX + 0U, // EVSTWHO + 0U, // EVSTWHOX + 0U, // EVSTWWE + 0U, // EVSTWWEX + 0U, // EVSTWWO + 0U, // EVSTWWOX + 0U, // EVSUBFSMIAAW + 0U, // EVSUBFSSIAAW + 0U, // EVSUBFUMIAAW + 0U, // EVSUBFUSIAAW + 70U, // EVSUBFW + 0U, // EVSUBIFW + 70U, // EVXOR + 0U, // EXTSB + 0U, // EXTSB8 + 0U, // EXTSB8_32_64 + 0U, // EXTSB8_rec + 0U, // EXTSB_rec + 0U, // EXTSH + 0U, // EXTSH8 + 0U, // EXTSH8_32_64 + 0U, // EXTSH8_rec + 0U, // EXTSH_rec + 0U, // EXTSW + 64U, // EXTSWSLI + 64U, // EXTSWSLI_32_64 + 64U, // EXTSWSLI_32_64_rec + 64U, // EXTSWSLI_rec + 0U, // EXTSW_32 + 0U, // EXTSW_32_64 + 0U, // EXTSW_32_64_rec + 0U, // EXTSW_rec + 0U, // EnforceIEIO + 0U, // FABSD + 0U, // FABSD_rec + 0U, // FABSS + 0U, // FABSS_rec + 70U, // FADD + 70U, // FADDS + 70U, // FADDS_rec + 70U, // FADD_rec + 0U, // FADDrtz + 0U, // FCFID + 0U, // FCFIDS + 0U, // FCFIDS_rec + 0U, // FCFIDU + 0U, // FCFIDUS + 0U, // FCFIDUS_rec + 0U, // FCFIDU_rec + 0U, // FCFID_rec + 70U, // FCMPOD + 70U, // FCMPOS + 70U, // FCMPUD + 70U, // FCMPUS + 70U, // FCPSGND + 70U, // FCPSGND_rec + 70U, // FCPSGNS + 70U, // FCPSGNS_rec + 0U, // FCTID + 0U, // FCTIDU + 0U, // FCTIDUZ + 0U, // FCTIDUZ_rec + 0U, // FCTIDU_rec + 0U, // FCTIDZ + 0U, // FCTIDZ_rec + 0U, // FCTID_rec + 0U, // FCTIW + 0U, // FCTIWU + 0U, // FCTIWUZ + 0U, // FCTIWUZ_rec + 0U, // FCTIWU_rec + 0U, // FCTIWZ + 0U, // FCTIWZ_rec + 0U, // FCTIW_rec + 70U, // FDIV + 70U, // FDIVS + 70U, // FDIVS_rec + 70U, // FDIV_rec + 262U, // FMADD + 262U, // FMADDS + 262U, // FMADDS_rec + 262U, // FMADD_rec + 0U, // FMR + 0U, // FMR_rec + 262U, // FMSUB + 262U, // FMSUBS + 262U, // FMSUBS_rec + 262U, // FMSUB_rec + 70U, // FMUL + 70U, // FMULS + 70U, // FMULS_rec + 70U, // FMUL_rec + 0U, // FNABSD + 0U, // FNABSD_rec + 0U, // FNABSS + 0U, // FNABSS_rec + 0U, // FNEGD + 0U, // FNEGD_rec + 0U, // FNEGS + 0U, // FNEGS_rec + 262U, // FNMADD + 262U, // FNMADDS + 262U, // FNMADDS_rec + 262U, // FNMADD_rec + 262U, // FNMSUB + 262U, // FNMSUBS + 262U, // FNMSUBS_rec + 262U, // FNMSUB_rec + 0U, // FRE + 0U, // FRES + 0U, // FRES_rec + 0U, // FRE_rec + 0U, // FRIMD + 0U, // FRIMD_rec + 0U, // FRIMS + 0U, // FRIMS_rec + 0U, // FRIND + 0U, // FRIND_rec + 0U, // FRINS + 0U, // FRINS_rec + 0U, // FRIPD + 0U, // FRIPD_rec + 0U, // FRIPS + 0U, // FRIPS_rec + 0U, // FRIZD + 0U, // FRIZD_rec + 0U, // FRIZS + 0U, // FRIZS_rec + 0U, // FRSP + 0U, // FRSP_rec + 0U, // FRSQRTE + 0U, // FRSQRTES + 0U, // FRSQRTES_rec + 0U, // FRSQRTE_rec + 262U, // FSELD + 262U, // FSELD_rec + 262U, // FSELS + 262U, // FSELS_rec + 0U, // FSQRT + 0U, // FSQRTS + 0U, // FSQRTS_rec + 0U, // FSQRT_rec + 70U, // FSUB + 70U, // FSUBS + 70U, // FSUBS_rec + 70U, // FSUB_rec + 70U, // FTDIV + 0U, // FTSQRT + 0U, // GETtlsADDR + 0U, // GETtlsADDR32 + 0U, // GETtlsADDR32AIX + 0U, // GETtlsADDR64AIX + 0U, // GETtlsADDRPCREL + 0U, // GETtlsldADDR + 0U, // GETtlsldADDR32 + 0U, // GETtlsldADDRPCREL + 0U, // HASHCHK + 0U, // HASHCHKP + 0U, // HASHST + 0U, // HASHSTP + 0U, // HRFID + 0U, // ICBI + 0U, // ICBIEP + 0U, // ICBLC + 0U, // ICBLQ + 0U, // ICBT + 0U, // ICBTLS + 0U, // ICCCI + 262U, // ISEL + 262U, // ISEL8 + 0U, // ISYNC + 0U, // LA + 0U, // LBARX + 1U, // LBARXL + 0U, // LBEPX + 0U, // LBZ + 0U, // LBZ8 + 70U, // LBZCIX + 0U, // LBZU + 0U, // LBZU8 + 0U, // LBZUX + 0U, // LBZUX8 + 0U, // LBZX + 0U, // LBZX8 + 70U, // LBZXTLS + 70U, // LBZXTLS_ + 70U, // LBZXTLS_32 + 0U, // LD + 0U, // LDARX + 1U, // LDARXL + 66U, // LDAT + 0U, // LDBRX + 70U, // LDCIX + 0U, // LDMX + 0U, // LDU + 0U, // LDUX + 0U, // LDX + 70U, // LDXTLS + 70U, // LDXTLS_ + 0U, // LDgotTprelL + 0U, // LDgotTprelL32 + 0U, // LDtoc + 0U, // LDtocBA + 0U, // LDtocCPT + 0U, // LDtocJTI + 0U, // LDtocL + 0U, // LFD + 0U, // LFDEPX + 0U, // LFDU + 0U, // LFDUX + 0U, // LFDX + 0U, // LFIWAX + 0U, // LFIWZX + 0U, // LFS + 0U, // LFSU + 0U, // LFSUX + 0U, // LFSX + 0U, // LHA + 0U, // LHA8 + 0U, // LHARX + 1U, // LHARXL + 0U, // LHAU + 0U, // LHAU8 + 0U, // LHAUX + 0U, // LHAUX8 + 0U, // LHAX + 0U, // LHAX8 + 0U, // LHBRX + 0U, // LHBRX8 + 0U, // LHEPX + 0U, // LHZ + 0U, // LHZ8 + 70U, // LHZCIX + 0U, // LHZU + 0U, // LHZU8 + 0U, // LHZUX + 0U, // LHZUX8 + 0U, // LHZX + 0U, // LHZX8 + 70U, // LHZXTLS + 70U, // LHZXTLS_ + 70U, // LHZXTLS_32 + 0U, // LI + 0U, // LI8 + 0U, // LIS + 0U, // LIS8 + 0U, // LMW + 0U, // LQ + 0U, // LQARX + 1U, // LQARXL + 0U, // LQX_PSEUDO + 66U, // LSWI + 0U, // LVEBX + 0U, // LVEHX + 0U, // LVEWX + 0U, // LVSL + 0U, // LVSR + 0U, // LVX + 0U, // LVXL + 0U, // LWA + 0U, // LWARX + 1U, // LWARXL + 66U, // LWAT + 0U, // LWAUX + 0U, // LWAX + 0U, // LWAX_32 + 0U, // LWA_32 + 0U, // LWBRX + 0U, // LWBRX8 + 0U, // LWEPX + 0U, // LWZ + 0U, // LWZ8 + 70U, // LWZCIX + 0U, // LWZU + 0U, // LWZU8 + 0U, // LWZUX + 0U, // LWZUX8 + 0U, // LWZX + 0U, // LWZX8 + 70U, // LWZXTLS + 70U, // LWZXTLS_ + 70U, // LWZXTLS_32 + 0U, // LWZtoc + 0U, // LWZtocL + 0U, // LXSD + 0U, // LXSDX + 0U, // LXSIBZX + 0U, // LXSIHZX + 0U, // LXSIWAX + 0U, // LXSIWZX + 0U, // LXSSP + 0U, // LXSSPX + 0U, // LXV + 0U, // LXVB16X + 0U, // LXVD2X + 0U, // LXVDSX + 0U, // LXVH8X + 70U, // LXVL + 70U, // LXVLL + 0U, // LXVP + 0U, // LXVPX + 0U, // LXVRBX + 0U, // LXVRDX + 0U, // LXVRHX + 0U, // LXVRWX + 0U, // LXVW4X + 0U, // LXVWSX + 0U, // LXVX + 262U, // MADDHD + 262U, // MADDHDU + 262U, // MADDLD + 262U, // MADDLD8 + 0U, // MBAR + 0U, // MCRF + 0U, // MCRFS + 0U, // MCRXRX + 0U, // MFBHRBE + 0U, // MFCR + 0U, // MFCR8 + 0U, // MFCTR + 0U, // MFCTR8 + 0U, // MFDCR + 0U, // MFFS + 0U, // MFFSCDRN + 0U, // MFFSCDRNI + 0U, // MFFSCE + 0U, // MFFSCRN + 0U, // MFFSCRNI + 0U, // MFFSL + 0U, // MFFS_rec + 0U, // MFLR + 0U, // MFLR8 + 0U, // MFMSR + 0U, // MFOCRF + 0U, // MFOCRF8 + 0U, // MFPMR + 0U, // MFSPR + 0U, // MFSPR8 + 0U, // MFSR + 0U, // MFSRIN + 0U, // MFTB + 0U, // MFTB8 + 0U, // MFVRD + 0U, // MFVRSAVE + 0U, // MFVRSAVEv + 0U, // MFVRWZ + 0U, // MFVSCR + 0U, // MFVSRD + 0U, // MFVSRLD + 0U, // MFVSRWZ + 70U, // MODSD + 70U, // MODSW + 70U, // MODUD + 70U, // MODUW + 0U, // MSGSYNC + 0U, // MSYNC + 0U, // MTCRF + 0U, // MTCRF8 + 0U, // MTCTR + 0U, // MTCTR8 + 0U, // MTCTR8loop + 0U, // MTCTRloop + 0U, // MTDCR + 0U, // MTFSB0 + 0U, // MTFSB1 + 266U, // MTFSF + 0U, // MTFSFI + 0U, // MTFSFI_rec + 0U, // MTFSFIb + 266U, // MTFSF_rec + 0U, // MTFSFb + 0U, // MTLR + 0U, // MTLR8 + 0U, // MTMSR + 0U, // MTMSRD + 0U, // MTOCRF + 0U, // MTOCRF8 + 0U, // MTPMR + 0U, // MTSPR + 0U, // MTSPR8 + 0U, // MTSR + 0U, // MTSRIN + 0U, // MTVRD + 0U, // MTVRSAVE + 0U, // MTVRSAVEv + 0U, // MTVRWA + 0U, // MTVRWZ + 0U, // MTVSCR + 0U, // MTVSRBM + 0U, // MTVSRBMI + 0U, // MTVSRD + 70U, // MTVSRDD + 0U, // MTVSRDM + 0U, // MTVSRHM + 0U, // MTVSRQM + 0U, // MTVSRWA + 0U, // MTVSRWM + 0U, // MTVSRWS + 0U, // MTVSRWZ + 70U, // MULHD + 70U, // MULHDU + 70U, // MULHDU_rec + 70U, // MULHD_rec + 70U, // MULHW + 70U, // MULHWU + 70U, // MULHWU_rec + 70U, // MULHW_rec + 70U, // MULLD + 70U, // MULLDO + 70U, // MULLDO_rec + 70U, // MULLD_rec + 4U, // MULLI + 4U, // MULLI8 + 70U, // MULLW + 70U, // MULLWO + 70U, // MULLWO_rec + 70U, // MULLW_rec + 0U, // MoveGOTtoLR + 0U, // MovePCtoLR + 0U, // MovePCtoLR8 + 70U, // NAND + 70U, // NAND8 + 70U, // NAND8_rec + 70U, // NAND_rec + 0U, // NAP + 0U, // NEG + 0U, // NEG8 + 0U, // NEG8O + 0U, // NEG8O_rec + 0U, // NEG8_rec + 0U, // NEGO + 0U, // NEGO_rec + 0U, // NEG_rec + 0U, // NOP + 0U, // NOP_GT_PWR6 + 0U, // NOP_GT_PWR7 + 70U, // NOR + 70U, // NOR8 + 70U, // NOR8_rec + 70U, // NOR_rec + 70U, // OR + 70U, // OR8 + 70U, // OR8_rec + 70U, // ORC + 70U, // ORC8 + 70U, // ORC8_rec + 70U, // ORC_rec + 8U, // ORI + 8U, // ORI8 + 8U, // ORIS + 8U, // ORIS8 + 70U, // OR_rec + 18U, // PADDI + 18U, // PADDI8 + 0U, // PADDI8pc + 0U, // PADDIdtprel + 0U, // PADDIpc + 70U, // PDEPD + 70U, // PEXTD + 0U, // PLBZ + 0U, // PLBZ8 + 0U, // PLBZ8pc + 0U, // PLBZpc + 0U, // PLD + 0U, // PLDpc + 0U, // PLFD + 0U, // PLFDpc + 0U, // PLFS + 0U, // PLFSpc + 0U, // PLHA + 0U, // PLHA8 + 0U, // PLHA8pc + 0U, // PLHApc + 0U, // PLHZ + 0U, // PLHZ8 + 0U, // PLHZ8pc + 0U, // PLHZpc + 0U, // PLI + 0U, // PLI8 + 0U, // PLWA + 0U, // PLWA8 + 0U, // PLWA8pc + 0U, // PLWApc + 0U, // PLWZ + 0U, // PLWZ8 + 0U, // PLWZ8pc + 0U, // PLWZpc + 0U, // PLXSD + 0U, // PLXSDpc + 0U, // PLXSSP + 0U, // PLXSSPpc + 0U, // PLXV + 0U, // PLXVP + 0U, // PLXVPpc + 0U, // PLXVpc + 2694U, // PMXVBF16GER2 + 13076U, // PMXVBF16GER2NN + 13076U, // PMXVBF16GER2NP + 13076U, // PMXVBF16GER2PN + 13076U, // PMXVBF16GER2PP + 2694U, // PMXVF16GER2 + 13076U, // PMXVF16GER2NN + 13076U, // PMXVF16GER2NP + 13076U, // PMXVF16GER2PN + 13076U, // PMXVF16GER2PP + 2694U, // PMXVF32GER + 21268U, // PMXVF32GERNN + 21268U, // PMXVF32GERNP + 21268U, // PMXVF32GERPN + 21268U, // PMXVF32GERPP + 27270U, // PMXVF64GER + 6932U, // PMXVF64GERNN + 6932U, // PMXVF64GERNP + 6932U, // PMXVF64GERPN + 6932U, // PMXVF64GERPP + 2694U, // PMXVI16GER2 + 13076U, // PMXVI16GER2PP + 2694U, // PMXVI16GER2S + 13076U, // PMXVI16GER2SPP + 2694U, // PMXVI4GER8 + 13076U, // PMXVI4GER8PP + 2694U, // PMXVI8GER4 + 13076U, // PMXVI8GER4PP + 13076U, // PMXVI8GER4SPP + 0U, // POPCNTB + 0U, // POPCNTB8 + 0U, // POPCNTD + 0U, // POPCNTW + 0U, // PPC32GOT + 0U, // PPC32PICGOT + 0U, // PREPARE_PROBED_ALLOCA_32 + 0U, // PREPARE_PROBED_ALLOCA_64 + 0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 + 0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 + 0U, // PROBED_ALLOCA_32 + 0U, // PROBED_ALLOCA_64 + 0U, // PROBED_STACKALLOC_32 + 0U, // PROBED_STACKALLOC_64 + 0U, // PSTB + 0U, // PSTB8 + 0U, // PSTB8pc + 0U, // PSTBpc + 0U, // PSTD + 0U, // PSTDpc + 0U, // PSTFD + 0U, // PSTFDpc + 0U, // PSTFS + 0U, // PSTFSpc + 0U, // PSTH + 0U, // PSTH8 + 0U, // PSTH8pc + 0U, // PSTHpc + 0U, // PSTW + 0U, // PSTW8 + 0U, // PSTW8pc + 0U, // PSTWpc + 0U, // PSTXSD + 0U, // PSTXSDpc + 0U, // PSTXSSP + 0U, // PSTXSSPpc + 0U, // PSTXV + 0U, // PSTXVP + 0U, // PSTXVPpc + 0U, // PSTXVpc + 0U, // PseudoEIEIO + 0U, // RESTORE_ACC + 0U, // RESTORE_CR + 0U, // RESTORE_CRBIT + 0U, // RESTORE_QUADWORD + 0U, // RESTORE_UACC + 0U, // RFCI + 0U, // RFDI + 0U, // RFEBB + 0U, // RFI + 0U, // RFID + 0U, // RFMCI + 6U, // RLDCL + 6U, // RLDCL_rec + 6U, // RLDCR + 6U, // RLDCR_rec + 0U, // RLDIC + 0U, // RLDICL + 0U, // RLDICL_32 + 0U, // RLDICL_32_64 + 0U, // RLDICL_32_rec + 0U, // RLDICL_rec + 0U, // RLDICR + 0U, // RLDICR_32 + 0U, // RLDICR_rec + 0U, // RLDIC_rec + 22U, // RLDIMI + 22U, // RLDIMI_rec + 24U, // RLWIMI + 24U, // RLWIMI8 + 24U, // RLWIMI8_rec + 24U, // RLWIMI_rec + 34946U, // RLWINM + 34946U, // RLWINM8 + 34946U, // RLWINM8_rec + 34946U, // RLWINM_rec + 34950U, // RLWNM + 34950U, // RLWNM8 + 34950U, // RLWNM8_rec + 34950U, // RLWNM_rec + 0U, // ReadTB + 0U, // SC + 0U, // SELECT_CC_F16 + 0U, // SELECT_CC_F4 + 0U, // SELECT_CC_F8 + 0U, // SELECT_CC_I4 + 0U, // SELECT_CC_I8 + 0U, // SELECT_CC_SPE + 0U, // SELECT_CC_SPE4 + 0U, // SELECT_CC_VRRC + 0U, // SELECT_CC_VSFRC + 0U, // SELECT_CC_VSRC + 0U, // SELECT_CC_VSSRC + 0U, // SELECT_F16 + 0U, // SELECT_F4 + 0U, // SELECT_F8 + 0U, // SELECT_I4 + 0U, // SELECT_I8 + 0U, // SELECT_SPE + 0U, // SELECT_SPE4 + 0U, // SELECT_VRRC + 0U, // SELECT_VSFRC + 0U, // SELECT_VSRC + 0U, // SELECT_VSSRC + 0U, // SETB + 0U, // SETB8 + 0U, // SETBC + 0U, // SETBC8 + 0U, // SETBCR + 0U, // SETBCR8 + 0U, // SETFLM + 0U, // SETNBC + 0U, // SETNBC8 + 0U, // SETNBCR + 0U, // SETNBCR8 + 0U, // SETRND + 0U, // SETRNDi + 0U, // SLBFEE_rec + 0U, // SLBIA + 0U, // SLBIE + 0U, // SLBIEG + 0U, // SLBMFEE + 0U, // SLBMFEV + 0U, // SLBMTE + 0U, // SLBSYNC + 70U, // SLD + 70U, // SLD_rec + 70U, // SLW + 70U, // SLW8 + 70U, // SLW8_rec + 70U, // SLW_rec + 0U, // SPELWZ + 0U, // SPELWZX + 0U, // SPESTW + 0U, // SPESTWX + 0U, // SPILL_ACC + 0U, // SPILL_CR + 0U, // SPILL_CRBIT + 0U, // SPILL_QUADWORD + 0U, // SPILL_UACC + 0U, // SPLIT_QUADWORD + 70U, // SRAD + 64U, // SRADI + 64U, // SRADI_32 + 64U, // SRADI_rec + 70U, // SRAD_rec + 70U, // SRAW + 66U, // SRAWI + 66U, // SRAWI_rec + 70U, // SRAW_rec + 70U, // SRD + 70U, // SRD_rec + 70U, // SRW + 70U, // SRW8 + 70U, // SRW8_rec + 70U, // SRW_rec + 0U, // STB + 0U, // STB8 + 70U, // STBCIX + 0U, // STBCX + 0U, // STBEPX + 0U, // STBU + 0U, // STBU8 + 0U, // STBUX + 0U, // STBUX8 + 0U, // STBX + 0U, // STBX8 + 70U, // STBXTLS + 70U, // STBXTLS_ + 70U, // STBXTLS_32 + 0U, // STD + 66U, // STDAT + 0U, // STDBRX + 70U, // STDCIX + 0U, // STDCX + 0U, // STDU + 0U, // STDUX + 0U, // STDX + 70U, // STDXTLS + 70U, // STDXTLS_ + 0U, // STFD + 0U, // STFDEPX + 0U, // STFDU + 0U, // STFDUX + 0U, // STFDX + 0U, // STFIWX + 0U, // STFS + 0U, // STFSU + 0U, // STFSUX + 0U, // STFSX + 0U, // STH + 0U, // STH8 + 0U, // STHBRX + 70U, // STHCIX + 0U, // STHCX + 0U, // STHEPX + 0U, // STHU + 0U, // STHU8 + 0U, // STHUX + 0U, // STHUX8 + 0U, // STHX + 0U, // STHX8 + 70U, // STHXTLS + 70U, // STHXTLS_ + 70U, // STHXTLS_32 + 0U, // STMW + 0U, // STOP + 0U, // STQ + 0U, // STQCX + 0U, // STQX_PSEUDO + 66U, // STSWI + 0U, // STVEBX + 0U, // STVEHX + 0U, // STVEWX + 0U, // STVX + 0U, // STVXL + 0U, // STW + 0U, // STW8 + 66U, // STWAT + 0U, // STWBRX + 70U, // STWCIX + 0U, // STWCX + 0U, // STWEPX + 0U, // STWU + 0U, // STWU8 + 0U, // STWUX + 0U, // STWUX8 + 0U, // STWX + 0U, // STWX8 + 70U, // STWXTLS + 70U, // STWXTLS_ + 70U, // STWXTLS_32 + 0U, // STXSD + 0U, // STXSDX + 0U, // STXSIBX + 0U, // STXSIBXv + 0U, // STXSIHX + 0U, // STXSIHXv + 0U, // STXSIWX + 0U, // STXSSP + 0U, // STXSSPX + 0U, // STXV + 0U, // STXVB16X + 0U, // STXVD2X + 0U, // STXVH8X + 70U, // STXVL + 70U, // STXVLL + 0U, // STXVP + 0U, // STXVPX + 0U, // STXVRBX + 0U, // STXVRDX + 0U, // STXVRHX + 0U, // STXVRWX + 0U, // STXVW4X + 0U, // STXVX + 70U, // SUBF + 70U, // SUBF8 + 70U, // SUBF8O + 70U, // SUBF8O_rec + 70U, // SUBF8_rec + 70U, // SUBFC + 70U, // SUBFC8 + 70U, // SUBFC8O + 70U, // SUBFC8O_rec + 70U, // SUBFC8_rec + 70U, // SUBFCO + 70U, // SUBFCO_rec + 70U, // SUBFC_rec + 70U, // SUBFE + 70U, // SUBFE8 + 70U, // SUBFE8O + 70U, // SUBFE8O_rec + 70U, // SUBFE8_rec + 70U, // SUBFEO + 70U, // SUBFEO_rec + 70U, // SUBFE_rec + 4U, // SUBFIC + 4U, // SUBFIC8 + 0U, // SUBFME + 0U, // SUBFME8 + 0U, // SUBFME8O + 0U, // SUBFME8O_rec + 0U, // SUBFME8_rec + 0U, // SUBFMEO + 0U, // SUBFMEO_rec + 0U, // SUBFME_rec + 70U, // SUBFO + 70U, // SUBFO_rec + 0U, // SUBFZE + 0U, // SUBFZE8 + 0U, // SUBFZE8O + 0U, // SUBFZE8O_rec + 0U, // SUBFZE8_rec + 0U, // SUBFZEO + 0U, // SUBFZEO_rec + 0U, // SUBFZE_rec + 70U, // SUBF_rec + 0U, // SYNC + 0U, // TABORT + 70U, // TABORTDC + 66U, // TABORTDCI + 70U, // TABORTWC + 66U, // TABORTWCI + 0U, // TAILB + 0U, // TAILB8 + 0U, // TAILBA + 0U, // TAILBA8 + 0U, // TAILBCTR + 0U, // TAILBCTR8 + 0U, // TBEGIN + 0U, // TBEGIN_RET + 0U, // TCHECK + 0U, // TCHECK_RET + 0U, // TCRETURNai + 0U, // TCRETURNai8 + 0U, // TCRETURNdi + 0U, // TCRETURNdi8 + 0U, // TCRETURNri + 0U, // TCRETURNri8 + 70U, // TD + 4U, // TDI + 0U, // TEND + 0U, // TLBIA + 0U, // TLBIE + 0U, // TLBIEL + 0U, // TLBIVAX + 0U, // TLBLD + 0U, // TLBLI + 0U, // TLBRE + 70U, // TLBRE2 + 0U, // TLBSX + 70U, // TLBSX2 + 70U, // TLBSX2D + 0U, // TLBSYNC + 0U, // TLBWE + 70U, // TLBWE2 + 0U, // TLSGDAIX + 0U, // TLSGDAIX8 + 0U, // TRAP + 0U, // TRECHKPT + 0U, // TRECLAIM + 0U, // TSR + 70U, // TW + 4U, // TWI + 0U, // UNENCODED_NOP + 0U, // UpdateGBR + 70U, // VABSDUB + 70U, // VABSDUH + 70U, // VABSDUW + 70U, // VADDCUQ + 70U, // VADDCUW + 262U, // VADDECUQ + 262U, // VADDEUQM + 70U, // VADDFP + 70U, // VADDSBS + 70U, // VADDSHS + 70U, // VADDSWS + 70U, // VADDUBM + 70U, // VADDUBS + 70U, // VADDUDM + 70U, // VADDUHM + 70U, // VADDUHS + 70U, // VADDUQM + 70U, // VADDUWM + 70U, // VADDUWS + 70U, // VAND + 70U, // VANDC + 70U, // VAVGSB + 70U, // VAVGSH + 70U, // VAVGSW + 70U, // VAVGUB + 70U, // VAVGUH + 70U, // VAVGUW + 70U, // VBPERMD + 70U, // VBPERMQ + 26U, // VCFSX + 1U, // VCFSX_0 + 70U, // VCFUGED + 26U, // VCFUX + 1U, // VCFUX_0 + 70U, // VCIPHER + 70U, // VCIPHERLAST + 70U, // VCLRLB + 70U, // VCLRRB + 0U, // VCLZB + 0U, // VCLZD + 70U, // VCLZDM + 0U, // VCLZH + 0U, // VCLZLSBB + 0U, // VCLZW + 70U, // VCMPBFP + 70U, // VCMPBFP_rec + 70U, // VCMPEQFP + 70U, // VCMPEQFP_rec + 70U, // VCMPEQUB + 70U, // VCMPEQUB_rec + 70U, // VCMPEQUD + 70U, // VCMPEQUD_rec + 70U, // VCMPEQUH + 70U, // VCMPEQUH_rec + 70U, // VCMPEQUQ + 70U, // VCMPEQUQ_rec + 70U, // VCMPEQUW + 70U, // VCMPEQUW_rec + 70U, // VCMPGEFP + 70U, // VCMPGEFP_rec + 70U, // VCMPGTFP + 70U, // VCMPGTFP_rec + 70U, // VCMPGTSB + 70U, // VCMPGTSB_rec + 70U, // VCMPGTSD + 70U, // VCMPGTSD_rec + 70U, // VCMPGTSH + 70U, // VCMPGTSH_rec + 70U, // VCMPGTSQ + 70U, // VCMPGTSQ_rec + 70U, // VCMPGTSW + 70U, // VCMPGTSW_rec + 70U, // VCMPGTUB + 70U, // VCMPGTUB_rec + 70U, // VCMPGTUD + 70U, // VCMPGTUD_rec + 70U, // VCMPGTUH + 70U, // VCMPGTUH_rec + 70U, // VCMPGTUQ + 70U, // VCMPGTUQ_rec + 70U, // VCMPGTUW + 70U, // VCMPGTUW_rec + 70U, // VCMPNEB + 70U, // VCMPNEB_rec + 70U, // VCMPNEH + 70U, // VCMPNEH_rec + 70U, // VCMPNEW + 70U, // VCMPNEW_rec + 70U, // VCMPNEZB + 70U, // VCMPNEZB_rec + 70U, // VCMPNEZH + 70U, // VCMPNEZH_rec + 70U, // VCMPNEZW + 70U, // VCMPNEZW_rec + 70U, // VCMPSQ + 70U, // VCMPUQ + 74U, // VCNTMBB + 74U, // VCNTMBD + 74U, // VCNTMBH + 74U, // VCNTMBW + 26U, // VCTSXS + 1U, // VCTSXS_0 + 26U, // VCTUXS + 1U, // VCTUXS_0 + 0U, // VCTZB + 0U, // VCTZD + 70U, // VCTZDM + 0U, // VCTZH + 0U, // VCTZLSBB + 0U, // VCTZW + 70U, // VDIVESD + 70U, // VDIVESQ + 70U, // VDIVESW + 70U, // VDIVEUD + 70U, // VDIVEUQ + 70U, // VDIVEUW + 70U, // VDIVSD + 70U, // VDIVSQ + 70U, // VDIVSW + 70U, // VDIVUD + 70U, // VDIVUQ + 70U, // VDIVUW + 70U, // VEQV + 0U, // VEXPANDBM + 0U, // VEXPANDDM + 0U, // VEXPANDHM + 0U, // VEXPANDQM + 0U, // VEXPANDWM + 0U, // VEXPTEFP + 262U, // VEXTDDVLX + 262U, // VEXTDDVRX + 262U, // VEXTDUBVLX + 262U, // VEXTDUBVRX + 262U, // VEXTDUHVLX + 262U, // VEXTDUHVRX + 262U, // VEXTDUWVLX + 262U, // VEXTDUWVRX + 0U, // VEXTRACTBM + 28U, // VEXTRACTD + 0U, // VEXTRACTDM + 0U, // VEXTRACTHM + 0U, // VEXTRACTQM + 28U, // VEXTRACTUB + 28U, // VEXTRACTUH + 28U, // VEXTRACTUW + 0U, // VEXTRACTWM + 0U, // VEXTSB2D + 0U, // VEXTSB2Ds + 0U, // VEXTSB2W + 0U, // VEXTSB2Ws + 0U, // VEXTSD2Q + 0U, // VEXTSH2D + 0U, // VEXTSH2Ds + 0U, // VEXTSH2W + 0U, // VEXTSH2Ws + 0U, // VEXTSW2D + 0U, // VEXTSW2Ds + 70U, // VEXTUBLX + 70U, // VEXTUBRX + 70U, // VEXTUHLX + 70U, // VEXTUHRX + 70U, // VEXTUWLX + 70U, // VEXTUWRX + 0U, // VGBBD + 30U, // VGNB + 84U, // VINSBLX + 84U, // VINSBRX + 84U, // VINSBVLX + 84U, // VINSBVRX + 0U, // VINSD + 84U, // VINSDLX + 84U, // VINSDRX + 0U, // VINSERTB + 28U, // VINSERTD + 0U, // VINSERTH + 28U, // VINSERTW + 84U, // VINSHLX + 84U, // VINSHRX + 84U, // VINSHVLX + 84U, // VINSHVRX + 0U, // VINSW + 84U, // VINSWLX + 84U, // VINSWRX + 84U, // VINSWVLX + 84U, // VINSWVRX + 0U, // VLOGEFP + 262U, // VMADDFP + 70U, // VMAXFP + 70U, // VMAXSB + 70U, // VMAXSD + 70U, // VMAXSH + 70U, // VMAXSW + 70U, // VMAXUB + 70U, // VMAXUD + 70U, // VMAXUH + 70U, // VMAXUW + 262U, // VMHADDSHS + 262U, // VMHRADDSHS + 70U, // VMINFP + 70U, // VMINSB + 70U, // VMINSD + 70U, // VMINSH + 70U, // VMINSW + 70U, // VMINUB + 70U, // VMINUD + 70U, // VMINUH + 70U, // VMINUW + 262U, // VMLADDUHM + 70U, // VMODSD + 70U, // VMODSQ + 70U, // VMODSW + 70U, // VMODUD + 70U, // VMODUQ + 70U, // VMODUW + 70U, // VMRGEW + 70U, // VMRGHB + 70U, // VMRGHH + 70U, // VMRGHW + 70U, // VMRGLB + 70U, // VMRGLH + 70U, // VMRGLW + 70U, // VMRGOW + 262U, // VMSUMCUD + 262U, // VMSUMMBM + 262U, // VMSUMSHM + 262U, // VMSUMSHS + 262U, // VMSUMUBM + 262U, // VMSUMUDM + 262U, // VMSUMUHM + 262U, // VMSUMUHS + 0U, // VMUL10CUQ + 70U, // VMUL10ECUQ + 70U, // VMUL10EUQ + 0U, // VMUL10UQ + 70U, // VMULESB + 70U, // VMULESD + 70U, // VMULESH + 70U, // VMULESW + 70U, // VMULEUB + 70U, // VMULEUD + 70U, // VMULEUH + 70U, // VMULEUW + 70U, // VMULHSD + 70U, // VMULHSW + 70U, // VMULHUD + 70U, // VMULHUW + 70U, // VMULLD + 70U, // VMULOSB + 70U, // VMULOSD + 70U, // VMULOSH + 70U, // VMULOSW + 70U, // VMULOUB + 70U, // VMULOUD + 70U, // VMULOUH + 70U, // VMULOUW + 70U, // VMULUWM + 70U, // VNAND + 70U, // VNCIPHER + 70U, // VNCIPHERLAST + 0U, // VNEGD + 0U, // VNEGW + 262U, // VNMSUBFP + 70U, // VNOR + 70U, // VOR + 70U, // VORC + 70U, // VPDEPD + 262U, // VPERM + 262U, // VPERMR + 262U, // VPERMXOR + 70U, // VPEXTD + 70U, // VPKPX + 70U, // VPKSDSS + 70U, // VPKSDUS + 70U, // VPKSHSS + 70U, // VPKSHUS + 70U, // VPKSWSS + 70U, // VPKSWUS + 70U, // VPKUDUM + 70U, // VPKUDUS + 70U, // VPKUHUM + 70U, // VPKUHUS + 70U, // VPKUWUM + 70U, // VPKUWUS + 70U, // VPMSUMB + 70U, // VPMSUMD + 70U, // VPMSUMH + 70U, // VPMSUMW + 0U, // VPOPCNTB + 0U, // VPOPCNTD + 0U, // VPOPCNTH + 0U, // VPOPCNTW + 0U, // VPRTYBD + 0U, // VPRTYBQ + 0U, // VPRTYBW + 0U, // VREFP + 0U, // VRFIM + 0U, // VRFIN + 0U, // VRFIP + 0U, // VRFIZ + 70U, // VRLB + 70U, // VRLD + 70U, // VRLDMI + 70U, // VRLDNM + 70U, // VRLH + 70U, // VRLQ + 70U, // VRLQMI + 70U, // VRLQNM + 70U, // VRLW + 70U, // VRLWMI + 70U, // VRLWNM + 0U, // VRSQRTEFP + 0U, // VSBOX + 262U, // VSEL + 650U, // VSHASIGMAD + 650U, // VSHASIGMAW + 70U, // VSL + 70U, // VSLB + 70U, // VSLD + 902U, // VSLDBI + 646U, // VSLDOI + 70U, // VSLH + 70U, // VSLO + 70U, // VSLQ + 70U, // VSLV + 70U, // VSLW + 26U, // VSPLTB + 26U, // VSPLTBs + 26U, // VSPLTH + 26U, // VSPLTHs + 0U, // VSPLTISB + 0U, // VSPLTISH + 0U, // VSPLTISW + 26U, // VSPLTW + 70U, // VSR + 70U, // VSRAB + 70U, // VSRAD + 70U, // VSRAH + 70U, // VSRAQ + 70U, // VSRAW + 70U, // VSRB + 70U, // VSRD + 902U, // VSRDBI + 70U, // VSRH + 70U, // VSRO + 70U, // VSRQ + 70U, // VSRV + 70U, // VSRW + 0U, // VSTRIBL + 0U, // VSTRIBL_rec + 0U, // VSTRIBR + 0U, // VSTRIBR_rec + 0U, // VSTRIHL + 0U, // VSTRIHL_rec + 0U, // VSTRIHR + 0U, // VSTRIHR_rec + 70U, // VSUBCUQ + 70U, // VSUBCUW + 262U, // VSUBECUQ + 262U, // VSUBEUQM + 70U, // VSUBFP + 70U, // VSUBSBS + 70U, // VSUBSHS + 70U, // VSUBSWS + 70U, // VSUBUBM + 70U, // VSUBUBS + 70U, // VSUBUDM + 70U, // VSUBUHM + 70U, // VSUBUHS + 70U, // VSUBUQM + 70U, // VSUBUWM + 70U, // VSUBUWS + 70U, // VSUM2SWS + 70U, // VSUM4SBS + 70U, // VSUM4SHS + 70U, // VSUM4UBS + 70U, // VSUMSWS + 0U, // VUPKHPX + 0U, // VUPKHSB + 0U, // VUPKHSH + 0U, // VUPKHSW + 0U, // VUPKLPX + 0U, // VUPKLSB + 0U, // VUPKLSH + 0U, // VUPKLSW + 70U, // VXOR + 12U, // V_SET0 + 12U, // V_SET0B + 12U, // V_SET0H + 0U, // V_SETALLONES + 0U, // V_SETALLONESB + 0U, // V_SETALLONESH + 0U, // WAIT + 0U, // WRTEE + 0U, // WRTEEI + 70U, // XOR + 70U, // XOR8 + 70U, // XOR8_rec + 8U, // XORI + 8U, // XORI8 + 8U, // XORIS + 8U, // XORIS8 + 70U, // XOR_rec + 0U, // XSABSDP + 0U, // XSABSQP + 70U, // XSADDDP + 70U, // XSADDQP + 70U, // XSADDQPO + 70U, // XSADDSP + 70U, // XSCMPEQDP + 70U, // XSCMPEXPDP + 70U, // XSCMPEXPQP + 70U, // XSCMPGEDP + 70U, // XSCMPGTDP + 70U, // XSCMPODP + 70U, // XSCMPOQP + 70U, // XSCMPUDP + 70U, // XSCMPUQP + 70U, // XSCPSGNDP + 70U, // XSCPSGNQP + 0U, // XSCVDPHP + 0U, // XSCVDPQP + 0U, // XSCVDPSP + 0U, // XSCVDPSPN + 0U, // XSCVDPSXDS + 0U, // XSCVDPSXDSs + 0U, // XSCVDPSXWS + 0U, // XSCVDPSXWSs + 0U, // XSCVDPUXDS + 0U, // XSCVDPUXDSs + 0U, // XSCVDPUXWS + 0U, // XSCVDPUXWSs + 0U, // XSCVHPDP + 0U, // XSCVQPDP + 0U, // XSCVQPDPO + 0U, // XSCVQPSDZ + 0U, // XSCVQPSQZ + 0U, // XSCVQPSWZ + 0U, // XSCVQPUDZ + 0U, // XSCVQPUQZ + 0U, // XSCVQPUWZ + 0U, // XSCVSDQP + 0U, // XSCVSPDP + 0U, // XSCVSPDPN + 0U, // XSCVSQQP + 0U, // XSCVSXDDP + 0U, // XSCVSXDSP + 0U, // XSCVUDQP + 0U, // XSCVUQQP + 0U, // XSCVUXDDP + 0U, // XSCVUXDSP + 70U, // XSDIVDP + 70U, // XSDIVQP + 70U, // XSDIVQPO + 70U, // XSDIVSP + 70U, // XSIEXPDP + 70U, // XSIEXPQP + 84U, // XSMADDADP + 84U, // XSMADDASP + 84U, // XSMADDMDP + 84U, // XSMADDMSP + 84U, // XSMADDQP + 84U, // XSMADDQPO + 70U, // XSMAXCDP + 70U, // XSMAXDP + 70U, // XSMAXJDP + 70U, // XSMINCDP + 70U, // XSMINDP + 70U, // XSMINJDP + 84U, // XSMSUBADP + 84U, // XSMSUBASP + 84U, // XSMSUBMDP + 84U, // XSMSUBMSP + 84U, // XSMSUBQP + 84U, // XSMSUBQPO + 70U, // XSMULDP + 70U, // XSMULQP + 70U, // XSMULQPO + 70U, // XSMULSP + 0U, // XSNABSDP + 0U, // XSNABSQP + 0U, // XSNEGDP + 0U, // XSNEGQP + 84U, // XSNMADDADP + 84U, // XSNMADDASP + 84U, // XSNMADDMDP + 84U, // XSNMADDMSP + 84U, // XSNMADDQP + 84U, // XSNMADDQPO + 84U, // XSNMSUBADP + 84U, // XSNMSUBASP + 84U, // XSNMSUBMDP + 84U, // XSNMSUBMSP + 84U, // XSNMSUBQP + 84U, // XSNMSUBQPO + 0U, // XSRDPI + 0U, // XSRDPIC + 0U, // XSRDPIM + 0U, // XSRDPIP + 0U, // XSRDPIZ + 0U, // XSREDP + 0U, // XSRESP + 0U, // XSRQPI + 0U, // XSRQPIX + 0U, // XSRQPXP + 0U, // XSRSP + 0U, // XSRSQRTEDP + 0U, // XSRSQRTESP + 0U, // XSSQRTDP + 0U, // XSSQRTQP + 0U, // XSSQRTQPO + 0U, // XSSQRTSP + 70U, // XSSUBDP + 70U, // XSSUBQP + 70U, // XSSUBQPO + 70U, // XSSUBSP + 70U, // XSTDIVDP + 0U, // XSTSQRTDP + 32U, // XSTSTDCDP + 32U, // XSTSTDCQP + 32U, // XSTSTDCSP + 0U, // XSXEXPDP + 0U, // XSXEXPQP + 0U, // XSXSIGDP + 0U, // XSXSIGQP + 0U, // XVABSDP + 0U, // XVABSSP + 70U, // XVADDDP + 70U, // XVADDSP + 70U, // XVBF16GER2 + 84U, // XVBF16GER2NN + 84U, // XVBF16GER2NP + 84U, // XVBF16GER2PN + 84U, // XVBF16GER2PP + 70U, // XVCMPEQDP + 70U, // XVCMPEQDP_rec + 70U, // XVCMPEQSP + 70U, // XVCMPEQSP_rec + 70U, // XVCMPGEDP + 70U, // XVCMPGEDP_rec + 70U, // XVCMPGESP + 70U, // XVCMPGESP_rec + 70U, // XVCMPGTDP + 70U, // XVCMPGTDP_rec + 70U, // XVCMPGTSP + 70U, // XVCMPGTSP_rec + 70U, // XVCPSGNDP + 70U, // XVCPSGNSP + 0U, // XVCVBF16SPN + 0U, // XVCVDPSP + 0U, // XVCVDPSXDS + 0U, // XVCVDPSXWS + 0U, // XVCVDPUXDS + 0U, // XVCVDPUXWS + 0U, // XVCVHPSP + 0U, // XVCVSPBF16 + 0U, // XVCVSPDP + 0U, // XVCVSPHP + 0U, // XVCVSPSXDS + 0U, // XVCVSPSXWS + 0U, // XVCVSPUXDS + 0U, // XVCVSPUXWS + 0U, // XVCVSXDDP + 0U, // XVCVSXDSP + 0U, // XVCVSXWDP + 0U, // XVCVSXWSP + 0U, // XVCVUXDDP + 0U, // XVCVUXDSP + 0U, // XVCVUXWDP + 0U, // XVCVUXWSP + 70U, // XVDIVDP + 70U, // XVDIVSP + 70U, // XVF16GER2 + 84U, // XVF16GER2NN + 84U, // XVF16GER2NP + 84U, // XVF16GER2PN + 84U, // XVF16GER2PP + 70U, // XVF32GER + 84U, // XVF32GERNN + 84U, // XVF32GERNP + 84U, // XVF32GERPN + 84U, // XVF32GERPP + 70U, // XVF64GER + 84U, // XVF64GERNN + 84U, // XVF64GERNP + 84U, // XVF64GERPN + 84U, // XVF64GERPP + 70U, // XVI16GER2 + 84U, // XVI16GER2PP + 70U, // XVI16GER2S + 84U, // XVI16GER2SPP + 70U, // XVI4GER8 + 84U, // XVI4GER8PP + 70U, // XVI8GER4 + 84U, // XVI8GER4PP + 84U, // XVI8GER4SPP + 70U, // XVIEXPDP + 70U, // XVIEXPSP + 84U, // XVMADDADP + 84U, // XVMADDASP + 84U, // XVMADDMDP + 84U, // XVMADDMSP + 70U, // XVMAXDP + 70U, // XVMAXSP + 70U, // XVMINDP + 70U, // XVMINSP + 84U, // XVMSUBADP + 84U, // XVMSUBASP + 84U, // XVMSUBMDP + 84U, // XVMSUBMSP + 70U, // XVMULDP + 70U, // XVMULSP + 0U, // XVNABSDP + 0U, // XVNABSSP + 0U, // XVNEGDP + 0U, // XVNEGSP + 84U, // XVNMADDADP + 84U, // XVNMADDASP + 84U, // XVNMADDMDP + 84U, // XVNMADDMSP + 84U, // XVNMSUBADP + 84U, // XVNMSUBASP + 84U, // XVNMSUBMDP + 84U, // XVNMSUBMSP + 0U, // XVRDPI + 0U, // XVRDPIC + 0U, // XVRDPIM + 0U, // XVRDPIP + 0U, // XVRDPIZ + 0U, // XVREDP + 0U, // XVRESP + 0U, // XVRSPI + 0U, // XVRSPIC + 0U, // XVRSPIM + 0U, // XVRSPIP + 0U, // XVRSPIZ + 0U, // XVRSQRTEDP + 0U, // XVRSQRTESP + 0U, // XVSQRTDP + 0U, // XVSQRTSP + 70U, // XVSUBDP + 70U, // XVSUBSP + 70U, // XVTDIVDP + 70U, // XVTDIVSP + 0U, // XVTLSBB + 0U, // XVTSQRTDP + 0U, // XVTSQRTSP + 32U, // XVTSTDCDP + 32U, // XVTSTDCSP + 0U, // XVXEXPDP + 0U, // XVXEXPSP + 0U, // XVXSIGDP + 0U, // XVXSIGSP + 262U, // XXBLENDVB + 262U, // XXBLENDVD + 262U, // XXBLENDVH + 262U, // XXBLENDVW + 0U, // XXBRD + 0U, // XXBRH + 0U, // XXBRQ + 0U, // XXBRW + 43270U, // XXEVAL + 34U, // XXEXTRACTUW + 36U, // XXGENPCVBM + 36U, // XXGENPCVDM + 36U, // XXGENPCVHM + 36U, // XXGENPCVWM + 38U, // XXINSERTW + 70U, // XXLAND + 70U, // XXLANDC + 70U, // XXLEQV + 12U, // XXLEQVOnes + 70U, // XXLNAND + 70U, // XXLNOR + 70U, // XXLOR + 70U, // XXLORC + 70U, // XXLORf + 70U, // XXLXOR + 12U, // XXLXORdpz + 12U, // XXLXORspz + 12U, // XXLXORz + 0U, // XXMFACC + 70U, // XXMRGHW + 70U, // XXMRGLW + 0U, // XXMTACC + 70U, // XXPERM + 390U, // XXPERMDI + 1040U, // XXPERMDIs + 70U, // XXPERMR + 51462U, // XXPERMX + 262U, // XXSEL + 0U, // XXSETACCZ + 390U, // XXSLDWI + 1040U, // XXSLDWIs + 84U, // XXSPLTI32DX + 0U, // XXSPLTIB + 0U, // XXSPLTIDP + 0U, // XXSPLTIW + 40U, // XXSPLTW + 40U, // XXSPLTWs + 42U, // gBC + 44U, // gBCA + 0U, // gBCAat + 70U, // gBCCTR + 70U, // gBCCTRL + 42U, // gBCL + 44U, // gBCLA + 0U, // gBCLAat + 70U, // gBCLR + 70U, // gBCLRL + 0U, // gBCLat + 0U, // gBCat + }; + + static const uint8_t OpInfo2[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ATOMIC_CMP_SWAP_I128 + 0U, // ATOMIC_LOAD_ADD_I128 + 0U, // ATOMIC_LOAD_AND_I128 + 0U, // ATOMIC_LOAD_NAND_I128 + 0U, // ATOMIC_LOAD_OR_I128 + 0U, // ATOMIC_LOAD_SUB_I128 + 0U, // ATOMIC_LOAD_XOR_I128 + 0U, // ATOMIC_SWAP_I128 + 0U, // BUILD_QUADWORD + 0U, // BUILD_UACC + 0U, // CFENCE8 + 0U, // CLRLSLDI + 0U, // CLRLSLDI_rec + 0U, // CLRLSLWI + 0U, // CLRLSLWI_rec + 0U, // CLRRDI + 0U, // CLRRDI_rec + 0U, // CLRRWI + 0U, // CLRRWI_rec + 0U, // DCBFL + 0U, // DCBFLP + 0U, // DCBFPS + 0U, // DCBFx + 0U, // DCBSTPS + 0U, // DCBTCT + 0U, // DCBTDS + 0U, // DCBTSTCT + 0U, // DCBTSTDS + 0U, // DCBTSTT + 0U, // DCBTSTx + 0U, // DCBTT + 0U, // DCBTx + 0U, // DFLOADf32 + 0U, // DFLOADf64 + 0U, // DFSTOREf32 + 0U, // DFSTOREf64 + 0U, // EXTLDI + 0U, // EXTLDI_rec + 0U, // EXTLWI + 0U, // EXTLWI_rec + 0U, // EXTRDI + 0U, // EXTRDI_rec + 0U, // EXTRWI + 0U, // EXTRWI_rec + 0U, // INSLWI + 0U, // INSLWI_rec + 0U, // INSRDI + 0U, // INSRDI_rec + 0U, // INSRWI + 0U, // INSRWI_rec + 0U, // KILL_PAIR + 0U, // LAx + 0U, // LIWAX + 0U, // LIWZX + 0U, // RLWIMIbm + 0U, // RLWIMIbm_rec + 0U, // RLWINMbm + 0U, // RLWINMbm_rec + 0U, // RLWNMbm + 0U, // RLWNMbm_rec + 0U, // ROTRDI + 0U, // ROTRDI_rec + 0U, // ROTRWI + 0U, // ROTRWI_rec + 0U, // SLDI + 0U, // SLDI_rec + 0U, // SLWI + 0U, // SLWI_rec + 0U, // SPILLTOVSR_LD + 0U, // SPILLTOVSR_LDX + 0U, // SPILLTOVSR_ST + 0U, // SPILLTOVSR_STX + 0U, // SRDI + 0U, // SRDI_rec + 0U, // SRWI + 0U, // SRWI_rec + 0U, // STIWX + 0U, // SUBI + 0U, // SUBIC + 0U, // SUBIC_rec + 0U, // SUBIS + 0U, // SUBPCIS + 0U, // XFLOADf32 + 0U, // XFLOADf64 + 0U, // XFSTOREf32 + 0U, // XFSTOREf64 + 0U, // ADD4 + 0U, // ADD4O + 0U, // ADD4O_rec + 0U, // ADD4TLS + 0U, // ADD4_rec + 0U, // ADD8 + 0U, // ADD8O + 0U, // ADD8O_rec + 0U, // ADD8TLS + 0U, // ADD8TLS_ + 0U, // ADD8_rec + 0U, // ADDC + 0U, // ADDC8 + 0U, // ADDC8O + 0U, // ADDC8O_rec + 0U, // ADDC8_rec + 0U, // ADDCO + 0U, // ADDCO_rec + 0U, // ADDC_rec + 0U, // ADDE + 0U, // ADDE8 + 0U, // ADDE8O + 0U, // ADDE8O_rec + 0U, // ADDE8_rec + 0U, // ADDEO + 0U, // ADDEO_rec + 0U, // ADDEX + 0U, // ADDEX8 + 0U, // ADDE_rec + 0U, // ADDI + 0U, // ADDI8 + 0U, // ADDIC + 0U, // ADDIC8 + 0U, // ADDIC_rec + 0U, // ADDIS + 0U, // ADDIS8 + 0U, // ADDISdtprelHA + 0U, // ADDISdtprelHA32 + 0U, // ADDISgotTprelHA + 0U, // ADDIStlsgdHA + 0U, // ADDIStlsldHA + 0U, // ADDIStocHA + 0U, // ADDIStocHA8 + 0U, // ADDIdtprelL + 0U, // ADDIdtprelL32 + 0U, // ADDItlsgdL + 0U, // ADDItlsgdL32 + 0U, // ADDItlsgdLADDR + 0U, // ADDItlsgdLADDR32 + 0U, // ADDItlsldL + 0U, // ADDItlsldL32 + 0U, // ADDItlsldLADDR + 0U, // ADDItlsldLADDR32 + 0U, // ADDItoc + 0U, // ADDItocL + 0U, // ADDME + 0U, // ADDME8 + 0U, // ADDME8O + 0U, // ADDME8O_rec + 0U, // ADDME8_rec + 0U, // ADDMEO + 0U, // ADDMEO_rec + 0U, // ADDME_rec + 0U, // ADDPCIS + 0U, // ADDZE + 0U, // ADDZE8 + 0U, // ADDZE8O + 0U, // ADDZE8O_rec + 0U, // ADDZE8_rec + 0U, // ADDZEO + 0U, // ADDZEO_rec + 0U, // ADDZE_rec + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // AND + 0U, // AND8 + 0U, // AND8_rec + 0U, // ANDC + 0U, // ANDC8 + 0U, // ANDC8_rec + 0U, // ANDC_rec + 0U, // ANDI8_rec + 0U, // ANDIS8_rec + 0U, // ANDIS_rec + 0U, // ANDI_rec + 0U, // ANDI_rec_1_EQ_BIT + 0U, // ANDI_rec_1_EQ_BIT8 + 0U, // ANDI_rec_1_GT_BIT + 0U, // ANDI_rec_1_GT_BIT8 + 0U, // AND_rec + 0U, // ATOMIC_CMP_SWAP_I16 + 0U, // ATOMIC_CMP_SWAP_I32 + 0U, // ATOMIC_CMP_SWAP_I64 + 0U, // ATOMIC_CMP_SWAP_I8 + 0U, // ATOMIC_LOAD_ADD_I16 + 0U, // ATOMIC_LOAD_ADD_I32 + 0U, // ATOMIC_LOAD_ADD_I64 + 0U, // ATOMIC_LOAD_ADD_I8 + 0U, // ATOMIC_LOAD_AND_I16 + 0U, // ATOMIC_LOAD_AND_I32 + 0U, // ATOMIC_LOAD_AND_I64 + 0U, // ATOMIC_LOAD_AND_I8 + 0U, // ATOMIC_LOAD_MAX_I16 + 0U, // ATOMIC_LOAD_MAX_I32 + 0U, // ATOMIC_LOAD_MAX_I64 + 0U, // ATOMIC_LOAD_MAX_I8 + 0U, // ATOMIC_LOAD_MIN_I16 + 0U, // ATOMIC_LOAD_MIN_I32 + 0U, // ATOMIC_LOAD_MIN_I64 + 0U, // ATOMIC_LOAD_MIN_I8 + 0U, // ATOMIC_LOAD_NAND_I16 + 0U, // ATOMIC_LOAD_NAND_I32 + 0U, // ATOMIC_LOAD_NAND_I64 + 0U, // ATOMIC_LOAD_NAND_I8 + 0U, // ATOMIC_LOAD_OR_I16 + 0U, // ATOMIC_LOAD_OR_I32 + 0U, // ATOMIC_LOAD_OR_I64 + 0U, // ATOMIC_LOAD_OR_I8 + 0U, // ATOMIC_LOAD_SUB_I16 + 0U, // ATOMIC_LOAD_SUB_I32 + 0U, // ATOMIC_LOAD_SUB_I64 + 0U, // ATOMIC_LOAD_SUB_I8 + 0U, // ATOMIC_LOAD_UMAX_I16 + 0U, // ATOMIC_LOAD_UMAX_I32 + 0U, // ATOMIC_LOAD_UMAX_I64 + 0U, // ATOMIC_LOAD_UMAX_I8 + 0U, // ATOMIC_LOAD_UMIN_I16 + 0U, // ATOMIC_LOAD_UMIN_I32 + 0U, // ATOMIC_LOAD_UMIN_I64 + 0U, // ATOMIC_LOAD_UMIN_I8 + 0U, // ATOMIC_LOAD_XOR_I16 + 0U, // ATOMIC_LOAD_XOR_I32 + 0U, // ATOMIC_LOAD_XOR_I64 + 0U, // ATOMIC_LOAD_XOR_I8 + 0U, // ATOMIC_SWAP_I16 + 0U, // ATOMIC_SWAP_I32 + 0U, // ATOMIC_SWAP_I64 + 0U, // ATOMIC_SWAP_I8 + 0U, // ATTN + 0U, // B + 0U, // BA + 0U, // BC + 0U, // BCC + 0U, // BCCA + 0U, // BCCCTR + 0U, // BCCCTR8 + 0U, // BCCCTRL + 0U, // BCCCTRL8 + 0U, // BCCL + 0U, // BCCLA + 0U, // BCCLR + 0U, // BCCLRL + 0U, // BCCTR + 0U, // BCCTR8 + 0U, // BCCTR8n + 0U, // BCCTRL + 0U, // BCCTRL8 + 0U, // BCCTRL8n + 0U, // BCCTRLn + 0U, // BCCTRn + 0U, // BCDCFN_rec + 0U, // BCDCFSQ_rec + 0U, // BCDCFZ_rec + 0U, // BCDCPSGN_rec + 0U, // BCDCTN_rec + 0U, // BCDCTSQ_rec + 0U, // BCDCTZ_rec + 0U, // BCDSETSGN_rec + 0U, // BCDSR_rec + 0U, // BCDS_rec + 0U, // BCDTRUNC_rec + 0U, // BCDUS_rec + 0U, // BCDUTRUNC_rec + 0U, // BCL + 0U, // BCLR + 0U, // BCLRL + 0U, // BCLRLn + 0U, // BCLRn + 0U, // BCLalways + 0U, // BCLn + 0U, // BCTR + 0U, // BCTR8 + 0U, // BCTRL + 0U, // BCTRL8 + 0U, // BCTRL8_LDinto_toc + 0U, // BCTRL8_LDinto_toc_RM + 0U, // BCTRL8_RM + 0U, // BCTRL_LWZinto_toc + 0U, // BCTRL_LWZinto_toc_RM + 0U, // BCTRL_RM + 0U, // BCn + 0U, // BDNZ + 0U, // BDNZ8 + 0U, // BDNZA + 0U, // BDNZAm + 0U, // BDNZAp + 0U, // BDNZL + 0U, // BDNZLA + 0U, // BDNZLAm + 0U, // BDNZLAp + 0U, // BDNZLR + 0U, // BDNZLR8 + 0U, // BDNZLRL + 0U, // BDNZLRLm + 0U, // BDNZLRLp + 0U, // BDNZLRm + 0U, // BDNZLRp + 0U, // BDNZLm + 0U, // BDNZLp + 0U, // BDNZm + 0U, // BDNZp + 0U, // BDZ + 0U, // BDZ8 + 0U, // BDZA + 0U, // BDZAm + 0U, // BDZAp + 0U, // BDZL + 0U, // BDZLA + 0U, // BDZLAm + 0U, // BDZLAp + 0U, // BDZLR + 0U, // BDZLR8 + 0U, // BDZLRL + 0U, // BDZLRLm + 0U, // BDZLRLp + 0U, // BDZLRm + 0U, // BDZLRp + 0U, // BDZLm + 0U, // BDZLp + 0U, // BDZm + 0U, // BDZp + 0U, // BL + 0U, // BL8 + 0U, // BL8_NOP + 0U, // BL8_NOP_RM + 0U, // BL8_NOP_TLS + 0U, // BL8_NOTOC + 0U, // BL8_NOTOC_RM + 0U, // BL8_NOTOC_TLS + 0U, // BL8_RM + 0U, // BL8_TLS + 0U, // BL8_TLS_ + 0U, // BLA + 0U, // BLA8 + 0U, // BLA8_NOP + 0U, // BLA8_NOP_RM + 0U, // BLA8_RM + 0U, // BLA_RM + 0U, // BLR + 0U, // BLR8 + 0U, // BLRL + 0U, // BL_NOP + 0U, // BL_NOP_RM + 0U, // BL_RM + 0U, // BL_TLS + 0U, // BPERMD + 0U, // BRINC + 0U, // CFUGED + 0U, // CLRBHRB + 0U, // CMPB + 0U, // CMPB8 + 0U, // CMPD + 0U, // CMPDI + 0U, // CMPEQB + 0U, // CMPLD + 0U, // CMPLDI + 0U, // CMPLW + 0U, // CMPLWI + 0U, // CMPRB + 0U, // CMPRB8 + 0U, // CMPW + 0U, // CMPWI + 0U, // CNTLZD + 0U, // CNTLZDM + 0U, // CNTLZD_rec + 0U, // CNTLZW + 0U, // CNTLZW8 + 0U, // CNTLZW8_rec + 0U, // CNTLZW_rec + 0U, // CNTTZD + 0U, // CNTTZDM + 0U, // CNTTZD_rec + 0U, // CNTTZW + 0U, // CNTTZW8 + 0U, // CNTTZW8_rec + 0U, // CNTTZW_rec + 0U, // CP_ABORT + 0U, // CP_COPY + 0U, // CP_COPY8 + 0U, // CP_PASTE8_rec + 0U, // CP_PASTE_rec + 0U, // CR6SET + 0U, // CR6UNSET + 0U, // CRAND + 0U, // CRANDC + 0U, // CREQV + 0U, // CRNAND + 0U, // CRNOR + 0U, // CROR + 0U, // CRORC + 0U, // CRSET + 0U, // CRUNSET + 0U, // CRXOR + 0U, // CTRL_DEP + 0U, // DARN + 0U, // DCBA + 0U, // DCBF + 0U, // DCBFEP + 0U, // DCBI + 0U, // DCBST + 0U, // DCBSTEP + 0U, // DCBT + 0U, // DCBTEP + 0U, // DCBTST + 0U, // DCBTSTEP + 0U, // DCBZ + 0U, // DCBZEP + 0U, // DCBZL + 0U, // DCBZLEP + 0U, // DCCCI + 0U, // DIVD + 0U, // DIVDE + 0U, // DIVDEO + 0U, // DIVDEO_rec + 0U, // DIVDEU + 0U, // DIVDEUO + 0U, // DIVDEUO_rec + 0U, // DIVDEU_rec + 0U, // DIVDE_rec + 0U, // DIVDO + 0U, // DIVDO_rec + 0U, // DIVDU + 0U, // DIVDUO + 0U, // DIVDUO_rec + 0U, // DIVDU_rec + 0U, // DIVD_rec + 0U, // DIVW + 0U, // DIVWE + 0U, // DIVWEO + 0U, // DIVWEO_rec + 0U, // DIVWEU + 0U, // DIVWEUO + 0U, // DIVWEUO_rec + 0U, // DIVWEU_rec + 0U, // DIVWE_rec + 0U, // DIVWO + 0U, // DIVWO_rec + 0U, // DIVWU + 0U, // DIVWUO + 0U, // DIVWUO_rec + 0U, // DIVWU_rec + 0U, // DIVW_rec + 0U, // DSS + 0U, // DSSALL + 0U, // DST + 0U, // DST64 + 0U, // DSTST + 0U, // DSTST64 + 0U, // DSTSTT + 0U, // DSTSTT64 + 0U, // DSTT + 0U, // DSTT64 + 0U, // DYNALLOC + 0U, // DYNALLOC8 + 0U, // DYNAREAOFFSET + 0U, // DYNAREAOFFSET8 + 0U, // EFDABS + 0U, // EFDADD + 0U, // EFDCFS + 0U, // EFDCFSF + 0U, // EFDCFSI + 0U, // EFDCFSID + 0U, // EFDCFUF + 0U, // EFDCFUI + 0U, // EFDCFUID + 0U, // EFDCMPEQ + 0U, // EFDCMPGT + 0U, // EFDCMPLT + 0U, // EFDCTSF + 0U, // EFDCTSI + 0U, // EFDCTSIDZ + 0U, // EFDCTSIZ + 0U, // EFDCTUF + 0U, // EFDCTUI + 0U, // EFDCTUIDZ + 0U, // EFDCTUIZ + 0U, // EFDDIV + 0U, // EFDMUL + 0U, // EFDNABS + 0U, // EFDNEG + 0U, // EFDSUB + 0U, // EFDTSTEQ + 0U, // EFDTSTGT + 0U, // EFDTSTLT + 0U, // EFSABS + 0U, // EFSADD + 0U, // EFSCFD + 0U, // EFSCFSF + 0U, // EFSCFSI + 0U, // EFSCFUF + 0U, // EFSCFUI + 0U, // EFSCMPEQ + 0U, // EFSCMPGT + 0U, // EFSCMPLT + 0U, // EFSCTSF + 0U, // EFSCTSI + 0U, // EFSCTSIZ + 0U, // EFSCTUF + 0U, // EFSCTUI + 0U, // EFSCTUIZ + 0U, // EFSDIV + 0U, // EFSMUL + 0U, // EFSNABS + 0U, // EFSNEG + 0U, // EFSSUB + 0U, // EFSTSTEQ + 0U, // EFSTSTGT + 0U, // EFSTSTLT + 0U, // EH_SjLj_LongJmp32 + 0U, // EH_SjLj_LongJmp64 + 0U, // EH_SjLj_SetJmp32 + 0U, // EH_SjLj_SetJmp64 + 0U, // EH_SjLj_Setup + 0U, // EQV + 0U, // EQV8 + 0U, // EQV8_rec + 0U, // EQV_rec + 0U, // EVABS + 0U, // EVADDIW + 0U, // EVADDSMIAAW + 0U, // EVADDSSIAAW + 0U, // EVADDUMIAAW + 0U, // EVADDUSIAAW + 0U, // EVADDW + 0U, // EVAND + 0U, // EVANDC + 0U, // EVCMPEQ + 0U, // EVCMPGTS + 0U, // EVCMPGTU + 0U, // EVCMPLTS + 0U, // EVCMPLTU + 0U, // EVCNTLSW + 0U, // EVCNTLZW + 0U, // EVDIVWS + 0U, // EVDIVWU + 0U, // EVEQV + 0U, // EVEXTSB + 0U, // EVEXTSH + 0U, // EVFSABS + 0U, // EVFSADD + 0U, // EVFSCFSF + 0U, // EVFSCFSI + 0U, // EVFSCFUF + 0U, // EVFSCFUI + 0U, // EVFSCMPEQ + 0U, // EVFSCMPGT + 0U, // EVFSCMPLT + 0U, // EVFSCTSF + 0U, // EVFSCTSI + 0U, // EVFSCTSIZ + 0U, // EVFSCTUF + 0U, // EVFSCTUI + 0U, // EVFSCTUIZ + 0U, // EVFSDIV + 0U, // EVFSMUL + 0U, // EVFSNABS + 0U, // EVFSNEG + 0U, // EVFSSUB + 0U, // EVFSTSTEQ + 0U, // EVFSTSTGT + 0U, // EVFSTSTLT + 0U, // EVLDD + 0U, // EVLDDX + 0U, // EVLDH + 0U, // EVLDHX + 0U, // EVLDW + 0U, // EVLDWX + 0U, // EVLHHESPLAT + 0U, // EVLHHESPLATX + 0U, // EVLHHOSSPLAT + 0U, // EVLHHOSSPLATX + 0U, // EVLHHOUSPLAT + 0U, // EVLHHOUSPLATX + 0U, // EVLWHE + 0U, // EVLWHEX + 0U, // EVLWHOS + 0U, // EVLWHOSX + 0U, // EVLWHOU + 0U, // EVLWHOUX + 0U, // EVLWHSPLAT + 0U, // EVLWHSPLATX + 0U, // EVLWWSPLAT + 0U, // EVLWWSPLATX + 0U, // EVMERGEHI + 0U, // EVMERGEHILO + 0U, // EVMERGELO + 0U, // EVMERGELOHI + 0U, // EVMHEGSMFAA + 0U, // EVMHEGSMFAN + 0U, // EVMHEGSMIAA + 0U, // EVMHEGSMIAN + 0U, // EVMHEGUMIAA + 0U, // EVMHEGUMIAN + 0U, // EVMHESMF + 0U, // EVMHESMFA + 0U, // EVMHESMFAAW + 0U, // EVMHESMFANW + 0U, // EVMHESMI + 0U, // EVMHESMIA + 0U, // EVMHESMIAAW + 0U, // EVMHESMIANW + 0U, // EVMHESSF + 0U, // EVMHESSFA + 0U, // EVMHESSFAAW + 0U, // EVMHESSFANW + 0U, // EVMHESSIAAW + 0U, // EVMHESSIANW + 0U, // EVMHEUMI + 0U, // EVMHEUMIA + 0U, // EVMHEUMIAAW + 0U, // EVMHEUMIANW + 0U, // EVMHEUSIAAW + 0U, // EVMHEUSIANW + 0U, // EVMHOGSMFAA + 0U, // EVMHOGSMFAN + 0U, // EVMHOGSMIAA + 0U, // EVMHOGSMIAN + 0U, // EVMHOGUMIAA + 0U, // EVMHOGUMIAN + 0U, // EVMHOSMF + 0U, // EVMHOSMFA + 0U, // EVMHOSMFAAW + 0U, // EVMHOSMFANW + 0U, // EVMHOSMI + 0U, // EVMHOSMIA + 0U, // EVMHOSMIAAW + 0U, // EVMHOSMIANW + 0U, // EVMHOSSF + 0U, // EVMHOSSFA + 0U, // EVMHOSSFAAW + 0U, // EVMHOSSFANW + 0U, // EVMHOSSIAAW + 0U, // EVMHOSSIANW + 0U, // EVMHOUMI + 0U, // EVMHOUMIA + 0U, // EVMHOUMIAAW + 0U, // EVMHOUMIANW + 0U, // EVMHOUSIAAW + 0U, // EVMHOUSIANW + 0U, // EVMRA + 0U, // EVMWHSMF + 0U, // EVMWHSMFA + 0U, // EVMWHSMI + 0U, // EVMWHSMIA + 0U, // EVMWHSSF + 0U, // EVMWHSSFA + 0U, // EVMWHUMI + 0U, // EVMWHUMIA + 0U, // EVMWLSMIAAW + 0U, // EVMWLSMIANW + 0U, // EVMWLSSIAAW + 0U, // EVMWLSSIANW + 0U, // EVMWLUMI + 0U, // EVMWLUMIA + 0U, // EVMWLUMIAAW + 0U, // EVMWLUMIANW + 0U, // EVMWLUSIAAW + 0U, // EVMWLUSIANW + 0U, // EVMWSMF + 0U, // EVMWSMFA + 0U, // EVMWSMFAA + 0U, // EVMWSMFAN + 0U, // EVMWSMI + 0U, // EVMWSMIA + 0U, // EVMWSMIAA + 0U, // EVMWSMIAN + 0U, // EVMWSSF + 0U, // EVMWSSFA + 0U, // EVMWSSFAA + 0U, // EVMWSSFAN + 0U, // EVMWUMI + 0U, // EVMWUMIA + 0U, // EVMWUMIAA + 0U, // EVMWUMIAN + 0U, // EVNAND + 0U, // EVNEG + 0U, // EVNOR + 0U, // EVOR + 0U, // EVORC + 0U, // EVRLW + 0U, // EVRLWI + 0U, // EVRNDW + 0U, // EVSEL + 0U, // EVSLW + 0U, // EVSLWI + 0U, // EVSPLATFI + 0U, // EVSPLATI + 0U, // EVSRWIS + 0U, // EVSRWIU + 0U, // EVSRWS + 0U, // EVSRWU + 0U, // EVSTDD + 0U, // EVSTDDX + 0U, // EVSTDH + 0U, // EVSTDHX + 0U, // EVSTDW + 0U, // EVSTDWX + 0U, // EVSTWHE + 0U, // EVSTWHEX + 0U, // EVSTWHO + 0U, // EVSTWHOX + 0U, // EVSTWWE + 0U, // EVSTWWEX + 0U, // EVSTWWO + 0U, // EVSTWWOX + 0U, // EVSUBFSMIAAW + 0U, // EVSUBFSSIAAW + 0U, // EVSUBFUMIAAW + 0U, // EVSUBFUSIAAW + 0U, // EVSUBFW + 0U, // EVSUBIFW + 0U, // EVXOR + 0U, // EXTSB + 0U, // EXTSB8 + 0U, // EXTSB8_32_64 + 0U, // EXTSB8_rec + 0U, // EXTSB_rec + 0U, // EXTSH + 0U, // EXTSH8 + 0U, // EXTSH8_32_64 + 0U, // EXTSH8_rec + 0U, // EXTSH_rec + 0U, // EXTSW + 0U, // EXTSWSLI + 0U, // EXTSWSLI_32_64 + 0U, // EXTSWSLI_32_64_rec + 0U, // EXTSWSLI_rec + 0U, // EXTSW_32 + 0U, // EXTSW_32_64 + 0U, // EXTSW_32_64_rec + 0U, // EXTSW_rec + 0U, // EnforceIEIO + 0U, // FABSD + 0U, // FABSD_rec + 0U, // FABSS + 0U, // FABSS_rec + 0U, // FADD + 0U, // FADDS + 0U, // FADDS_rec + 0U, // FADD_rec + 0U, // FADDrtz + 0U, // FCFID + 0U, // FCFIDS + 0U, // FCFIDS_rec + 0U, // FCFIDU + 0U, // FCFIDUS + 0U, // FCFIDUS_rec + 0U, // FCFIDU_rec + 0U, // FCFID_rec + 0U, // FCMPOD + 0U, // FCMPOS + 0U, // FCMPUD + 0U, // FCMPUS + 0U, // FCPSGND + 0U, // FCPSGND_rec + 0U, // FCPSGNS + 0U, // FCPSGNS_rec + 0U, // FCTID + 0U, // FCTIDU + 0U, // FCTIDUZ + 0U, // FCTIDUZ_rec + 0U, // FCTIDU_rec + 0U, // FCTIDZ + 0U, // FCTIDZ_rec + 0U, // FCTID_rec + 0U, // FCTIW + 0U, // FCTIWU + 0U, // FCTIWUZ + 0U, // FCTIWUZ_rec + 0U, // FCTIWU_rec + 0U, // FCTIWZ + 0U, // FCTIWZ_rec + 0U, // FCTIW_rec + 0U, // FDIV + 0U, // FDIVS + 0U, // FDIVS_rec + 0U, // FDIV_rec + 0U, // FMADD + 0U, // FMADDS + 0U, // FMADDS_rec + 0U, // FMADD_rec + 0U, // FMR + 0U, // FMR_rec + 0U, // FMSUB + 0U, // FMSUBS + 0U, // FMSUBS_rec + 0U, // FMSUB_rec + 0U, // FMUL + 0U, // FMULS + 0U, // FMULS_rec + 0U, // FMUL_rec + 0U, // FNABSD + 0U, // FNABSD_rec + 0U, // FNABSS + 0U, // FNABSS_rec + 0U, // FNEGD + 0U, // FNEGD_rec + 0U, // FNEGS + 0U, // FNEGS_rec + 0U, // FNMADD + 0U, // FNMADDS + 0U, // FNMADDS_rec + 0U, // FNMADD_rec + 0U, // FNMSUB + 0U, // FNMSUBS + 0U, // FNMSUBS_rec + 0U, // FNMSUB_rec + 0U, // FRE + 0U, // FRES + 0U, // FRES_rec + 0U, // FRE_rec + 0U, // FRIMD + 0U, // FRIMD_rec + 0U, // FRIMS + 0U, // FRIMS_rec + 0U, // FRIND + 0U, // FRIND_rec + 0U, // FRINS + 0U, // FRINS_rec + 0U, // FRIPD + 0U, // FRIPD_rec + 0U, // FRIPS + 0U, // FRIPS_rec + 0U, // FRIZD + 0U, // FRIZD_rec + 0U, // FRIZS + 0U, // FRIZS_rec + 0U, // FRSP + 0U, // FRSP_rec + 0U, // FRSQRTE + 0U, // FRSQRTES + 0U, // FRSQRTES_rec + 0U, // FRSQRTE_rec + 0U, // FSELD + 0U, // FSELD_rec + 0U, // FSELS + 0U, // FSELS_rec + 0U, // FSQRT + 0U, // FSQRTS + 0U, // FSQRTS_rec + 0U, // FSQRT_rec + 0U, // FSUB + 0U, // FSUBS + 0U, // FSUBS_rec + 0U, // FSUB_rec + 0U, // FTDIV + 0U, // FTSQRT + 0U, // GETtlsADDR + 0U, // GETtlsADDR32 + 0U, // GETtlsADDR32AIX + 0U, // GETtlsADDR64AIX + 0U, // GETtlsADDRPCREL + 0U, // GETtlsldADDR + 0U, // GETtlsldADDR32 + 0U, // GETtlsldADDRPCREL + 0U, // HASHCHK + 0U, // HASHCHKP + 0U, // HASHST + 0U, // HASHSTP + 0U, // HRFID + 0U, // ICBI + 0U, // ICBIEP + 0U, // ICBLC + 0U, // ICBLQ + 0U, // ICBT + 0U, // ICBTLS + 0U, // ICCCI + 0U, // ISEL + 0U, // ISEL8 + 0U, // ISYNC + 0U, // LA + 0U, // LBARX + 0U, // LBARXL + 0U, // LBEPX + 0U, // LBZ + 0U, // LBZ8 + 0U, // LBZCIX + 0U, // LBZU + 0U, // LBZU8 + 0U, // LBZUX + 0U, // LBZUX8 + 0U, // LBZX + 0U, // LBZX8 + 0U, // LBZXTLS + 0U, // LBZXTLS_ + 0U, // LBZXTLS_32 + 0U, // LD + 0U, // LDARX + 0U, // LDARXL + 0U, // LDAT + 0U, // LDBRX + 0U, // LDCIX + 0U, // LDMX + 0U, // LDU + 0U, // LDUX + 0U, // LDX + 0U, // LDXTLS + 0U, // LDXTLS_ + 0U, // LDgotTprelL + 0U, // LDgotTprelL32 + 0U, // LDtoc + 0U, // LDtocBA + 0U, // LDtocCPT + 0U, // LDtocJTI + 0U, // LDtocL + 0U, // LFD + 0U, // LFDEPX + 0U, // LFDU + 0U, // LFDUX + 0U, // LFDX + 0U, // LFIWAX + 0U, // LFIWZX + 0U, // LFS + 0U, // LFSU + 0U, // LFSUX + 0U, // LFSX + 0U, // LHA + 0U, // LHA8 + 0U, // LHARX + 0U, // LHARXL + 0U, // LHAU + 0U, // LHAU8 + 0U, // LHAUX + 0U, // LHAUX8 + 0U, // LHAX + 0U, // LHAX8 + 0U, // LHBRX + 0U, // LHBRX8 + 0U, // LHEPX + 0U, // LHZ + 0U, // LHZ8 + 0U, // LHZCIX + 0U, // LHZU + 0U, // LHZU8 + 0U, // LHZUX + 0U, // LHZUX8 + 0U, // LHZX + 0U, // LHZX8 + 0U, // LHZXTLS + 0U, // LHZXTLS_ + 0U, // LHZXTLS_32 + 0U, // LI + 0U, // LI8 + 0U, // LIS + 0U, // LIS8 + 0U, // LMW + 0U, // LQ + 0U, // LQARX + 0U, // LQARXL + 0U, // LQX_PSEUDO + 0U, // LSWI + 0U, // LVEBX + 0U, // LVEHX + 0U, // LVEWX + 0U, // LVSL + 0U, // LVSR + 0U, // LVX + 0U, // LVXL + 0U, // LWA + 0U, // LWARX + 0U, // LWARXL + 0U, // LWAT + 0U, // LWAUX + 0U, // LWAX + 0U, // LWAX_32 + 0U, // LWA_32 + 0U, // LWBRX + 0U, // LWBRX8 + 0U, // LWEPX + 0U, // LWZ + 0U, // LWZ8 + 0U, // LWZCIX + 0U, // LWZU + 0U, // LWZU8 + 0U, // LWZUX + 0U, // LWZUX8 + 0U, // LWZX + 0U, // LWZX8 + 0U, // LWZXTLS + 0U, // LWZXTLS_ + 0U, // LWZXTLS_32 + 0U, // LWZtoc + 0U, // LWZtocL + 0U, // LXSD + 0U, // LXSDX + 0U, // LXSIBZX + 0U, // LXSIHZX + 0U, // LXSIWAX + 0U, // LXSIWZX + 0U, // LXSSP + 0U, // LXSSPX + 0U, // LXV + 0U, // LXVB16X + 0U, // LXVD2X + 0U, // LXVDSX + 0U, // LXVH8X + 0U, // LXVL + 0U, // LXVLL + 0U, // LXVP + 0U, // LXVPX + 0U, // LXVRBX + 0U, // LXVRDX + 0U, // LXVRHX + 0U, // LXVRWX + 0U, // LXVW4X + 0U, // LXVWSX + 0U, // LXVX + 0U, // MADDHD + 0U, // MADDHDU + 0U, // MADDLD + 0U, // MADDLD8 + 0U, // MBAR + 0U, // MCRF + 0U, // MCRFS + 0U, // MCRXRX + 0U, // MFBHRBE + 0U, // MFCR + 0U, // MFCR8 + 0U, // MFCTR + 0U, // MFCTR8 + 0U, // MFDCR + 0U, // MFFS + 0U, // MFFSCDRN + 0U, // MFFSCDRNI + 0U, // MFFSCE + 0U, // MFFSCRN + 0U, // MFFSCRNI + 0U, // MFFSL + 0U, // MFFS_rec + 0U, // MFLR + 0U, // MFLR8 + 0U, // MFMSR + 0U, // MFOCRF + 0U, // MFOCRF8 + 0U, // MFPMR + 0U, // MFSPR + 0U, // MFSPR8 + 0U, // MFSR + 0U, // MFSRIN + 0U, // MFTB + 0U, // MFTB8 + 0U, // MFVRD + 0U, // MFVRSAVE + 0U, // MFVRSAVEv + 0U, // MFVRWZ + 0U, // MFVSCR + 0U, // MFVSRD + 0U, // MFVSRLD + 0U, // MFVSRWZ + 0U, // MODSD + 0U, // MODSW + 0U, // MODUD + 0U, // MODUW + 0U, // MSGSYNC + 0U, // MSYNC + 0U, // MTCRF + 0U, // MTCRF8 + 0U, // MTCTR + 0U, // MTCTR8 + 0U, // MTCTR8loop + 0U, // MTCTRloop + 0U, // MTDCR + 0U, // MTFSB0 + 0U, // MTFSB1 + 0U, // MTFSF + 0U, // MTFSFI + 0U, // MTFSFI_rec + 0U, // MTFSFIb + 0U, // MTFSF_rec + 0U, // MTFSFb + 0U, // MTLR + 0U, // MTLR8 + 0U, // MTMSR + 0U, // MTMSRD + 0U, // MTOCRF + 0U, // MTOCRF8 + 0U, // MTPMR + 0U, // MTSPR + 0U, // MTSPR8 + 0U, // MTSR + 0U, // MTSRIN + 0U, // MTVRD + 0U, // MTVRSAVE + 0U, // MTVRSAVEv + 0U, // MTVRWA + 0U, // MTVRWZ + 0U, // MTVSCR + 0U, // MTVSRBM + 0U, // MTVSRBMI + 0U, // MTVSRD + 0U, // MTVSRDD + 0U, // MTVSRDM + 0U, // MTVSRHM + 0U, // MTVSRQM + 0U, // MTVSRWA + 0U, // MTVSRWM + 0U, // MTVSRWS + 0U, // MTVSRWZ + 0U, // MULHD + 0U, // MULHDU + 0U, // MULHDU_rec + 0U, // MULHD_rec + 0U, // MULHW + 0U, // MULHWU + 0U, // MULHWU_rec + 0U, // MULHW_rec + 0U, // MULLD + 0U, // MULLDO + 0U, // MULLDO_rec + 0U, // MULLD_rec + 0U, // MULLI + 0U, // MULLI8 + 0U, // MULLW + 0U, // MULLWO + 0U, // MULLWO_rec + 0U, // MULLW_rec + 0U, // MoveGOTtoLR + 0U, // MovePCtoLR + 0U, // MovePCtoLR8 + 0U, // NAND + 0U, // NAND8 + 0U, // NAND8_rec + 0U, // NAND_rec + 0U, // NAP + 0U, // NEG + 0U, // NEG8 + 0U, // NEG8O + 0U, // NEG8O_rec + 0U, // NEG8_rec + 0U, // NEGO + 0U, // NEGO_rec + 0U, // NEG_rec + 0U, // NOP + 0U, // NOP_GT_PWR6 + 0U, // NOP_GT_PWR7 + 0U, // NOR + 0U, // NOR8 + 0U, // NOR8_rec + 0U, // NOR_rec + 0U, // OR + 0U, // OR8 + 0U, // OR8_rec + 0U, // ORC + 0U, // ORC8 + 0U, // ORC8_rec + 0U, // ORC_rec + 0U, // ORI + 0U, // ORI8 + 0U, // ORIS + 0U, // ORIS8 + 0U, // OR_rec + 0U, // PADDI + 0U, // PADDI8 + 0U, // PADDI8pc + 0U, // PADDIdtprel + 0U, // PADDIpc + 0U, // PDEPD + 0U, // PEXTD + 0U, // PLBZ + 0U, // PLBZ8 + 0U, // PLBZ8pc + 0U, // PLBZpc + 0U, // PLD + 0U, // PLDpc + 0U, // PLFD + 0U, // PLFDpc + 0U, // PLFS + 0U, // PLFSpc + 0U, // PLHA + 0U, // PLHA8 + 0U, // PLHA8pc + 0U, // PLHApc + 0U, // PLHZ + 0U, // PLHZ8 + 0U, // PLHZ8pc + 0U, // PLHZpc + 0U, // PLI + 0U, // PLI8 + 0U, // PLWA + 0U, // PLWA8 + 0U, // PLWA8pc + 0U, // PLWApc + 0U, // PLWZ + 0U, // PLWZ8 + 0U, // PLWZ8pc + 0U, // PLWZpc + 0U, // PLXSD + 0U, // PLXSDpc + 0U, // PLXSSP + 0U, // PLXSSPpc + 0U, // PLXV + 0U, // PLXVP + 0U, // PLXVPpc + 0U, // PLXVpc + 0U, // PMXVBF16GER2 + 1U, // PMXVBF16GER2NN + 1U, // PMXVBF16GER2NP + 1U, // PMXVBF16GER2PN + 1U, // PMXVBF16GER2PP + 0U, // PMXVF16GER2 + 1U, // PMXVF16GER2NN + 1U, // PMXVF16GER2NP + 1U, // PMXVF16GER2PN + 1U, // PMXVF16GER2PP + 2U, // PMXVF32GER + 0U, // PMXVF32GERNN + 0U, // PMXVF32GERNP + 0U, // PMXVF32GERPN + 0U, // PMXVF32GERPP + 0U, // PMXVF64GER + 0U, // PMXVF64GERNN + 0U, // PMXVF64GERNP + 0U, // PMXVF64GERPN + 0U, // PMXVF64GERPP + 0U, // PMXVI16GER2 + 1U, // PMXVI16GER2PP + 0U, // PMXVI16GER2S + 1U, // PMXVI16GER2SPP + 8U, // PMXVI4GER8 + 3U, // PMXVI4GER8PP + 16U, // PMXVI8GER4 + 4U, // PMXVI8GER4PP + 4U, // PMXVI8GER4SPP + 0U, // POPCNTB + 0U, // POPCNTB8 + 0U, // POPCNTD + 0U, // POPCNTW + 0U, // PPC32GOT + 0U, // PPC32PICGOT + 0U, // PREPARE_PROBED_ALLOCA_32 + 0U, // PREPARE_PROBED_ALLOCA_64 + 0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 + 0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 + 0U, // PROBED_ALLOCA_32 + 0U, // PROBED_ALLOCA_64 + 0U, // PROBED_STACKALLOC_32 + 0U, // PROBED_STACKALLOC_64 + 0U, // PSTB + 0U, // PSTB8 + 0U, // PSTB8pc + 0U, // PSTBpc + 0U, // PSTD + 0U, // PSTDpc + 0U, // PSTFD + 0U, // PSTFDpc + 0U, // PSTFS + 0U, // PSTFSpc + 0U, // PSTH + 0U, // PSTH8 + 0U, // PSTH8pc + 0U, // PSTHpc + 0U, // PSTW + 0U, // PSTW8 + 0U, // PSTW8pc + 0U, // PSTWpc + 0U, // PSTXSD + 0U, // PSTXSDpc + 0U, // PSTXSSP + 0U, // PSTXSSPpc + 0U, // PSTXV + 0U, // PSTXVP + 0U, // PSTXVPpc + 0U, // PSTXVpc + 0U, // PseudoEIEIO + 0U, // RESTORE_ACC + 0U, // RESTORE_CR + 0U, // RESTORE_CRBIT + 0U, // RESTORE_QUADWORD + 0U, // RESTORE_UACC + 0U, // RFCI + 0U, // RFDI + 0U, // RFEBB + 0U, // RFI + 0U, // RFID + 0U, // RFMCI + 0U, // RLDCL + 0U, // RLDCL_rec + 0U, // RLDCR + 0U, // RLDCR_rec + 0U, // RLDIC + 0U, // RLDICL + 0U, // RLDICL_32 + 0U, // RLDICL_32_64 + 0U, // RLDICL_32_rec + 0U, // RLDICL_rec + 0U, // RLDICR + 0U, // RLDICR_32 + 0U, // RLDICR_rec + 0U, // RLDIC_rec + 0U, // RLDIMI + 0U, // RLDIMI_rec + 0U, // RLWIMI + 0U, // RLWIMI8 + 0U, // RLWIMI8_rec + 0U, // RLWIMI_rec + 0U, // RLWINM + 0U, // RLWINM8 + 0U, // RLWINM8_rec + 0U, // RLWINM_rec + 0U, // RLWNM + 0U, // RLWNM8 + 0U, // RLWNM8_rec + 0U, // RLWNM_rec + 0U, // ReadTB + 0U, // SC + 0U, // SELECT_CC_F16 + 0U, // SELECT_CC_F4 + 0U, // SELECT_CC_F8 + 0U, // SELECT_CC_I4 + 0U, // SELECT_CC_I8 + 0U, // SELECT_CC_SPE + 0U, // SELECT_CC_SPE4 + 0U, // SELECT_CC_VRRC + 0U, // SELECT_CC_VSFRC + 0U, // SELECT_CC_VSRC + 0U, // SELECT_CC_VSSRC + 0U, // SELECT_F16 + 0U, // SELECT_F4 + 0U, // SELECT_F8 + 0U, // SELECT_I4 + 0U, // SELECT_I8 + 0U, // SELECT_SPE + 0U, // SELECT_SPE4 + 0U, // SELECT_VRRC + 0U, // SELECT_VSFRC + 0U, // SELECT_VSRC + 0U, // SELECT_VSSRC + 0U, // SETB + 0U, // SETB8 + 0U, // SETBC + 0U, // SETBC8 + 0U, // SETBCR + 0U, // SETBCR8 + 0U, // SETFLM + 0U, // SETNBC + 0U, // SETNBC8 + 0U, // SETNBCR + 0U, // SETNBCR8 + 0U, // SETRND + 0U, // SETRNDi + 0U, // SLBFEE_rec + 0U, // SLBIA + 0U, // SLBIE + 0U, // SLBIEG + 0U, // SLBMFEE + 0U, // SLBMFEV + 0U, // SLBMTE + 0U, // SLBSYNC + 0U, // SLD + 0U, // SLD_rec + 0U, // SLW + 0U, // SLW8 + 0U, // SLW8_rec + 0U, // SLW_rec + 0U, // SPELWZ + 0U, // SPELWZX + 0U, // SPESTW + 0U, // SPESTWX + 0U, // SPILL_ACC + 0U, // SPILL_CR + 0U, // SPILL_CRBIT + 0U, // SPILL_QUADWORD + 0U, // SPILL_UACC + 0U, // SPLIT_QUADWORD + 0U, // SRAD + 0U, // SRADI + 0U, // SRADI_32 + 0U, // SRADI_rec + 0U, // SRAD_rec + 0U, // SRAW + 0U, // SRAWI + 0U, // SRAWI_rec + 0U, // SRAW_rec + 0U, // SRD + 0U, // SRD_rec + 0U, // SRW + 0U, // SRW8 + 0U, // SRW8_rec + 0U, // SRW_rec + 0U, // STB + 0U, // STB8 + 0U, // STBCIX + 0U, // STBCX + 0U, // STBEPX + 0U, // STBU + 0U, // STBU8 + 0U, // STBUX + 0U, // STBUX8 + 0U, // STBX + 0U, // STBX8 + 0U, // STBXTLS + 0U, // STBXTLS_ + 0U, // STBXTLS_32 + 0U, // STD + 0U, // STDAT + 0U, // STDBRX + 0U, // STDCIX + 0U, // STDCX + 0U, // STDU + 0U, // STDUX + 0U, // STDX + 0U, // STDXTLS + 0U, // STDXTLS_ + 0U, // STFD + 0U, // STFDEPX + 0U, // STFDU + 0U, // STFDUX + 0U, // STFDX + 0U, // STFIWX + 0U, // STFS + 0U, // STFSU + 0U, // STFSUX + 0U, // STFSX + 0U, // STH + 0U, // STH8 + 0U, // STHBRX + 0U, // STHCIX + 0U, // STHCX + 0U, // STHEPX + 0U, // STHU + 0U, // STHU8 + 0U, // STHUX + 0U, // STHUX8 + 0U, // STHX + 0U, // STHX8 + 0U, // STHXTLS + 0U, // STHXTLS_ + 0U, // STHXTLS_32 + 0U, // STMW + 0U, // STOP + 0U, // STQ + 0U, // STQCX + 0U, // STQX_PSEUDO + 0U, // STSWI + 0U, // STVEBX + 0U, // STVEHX + 0U, // STVEWX + 0U, // STVX + 0U, // STVXL + 0U, // STW + 0U, // STW8 + 0U, // STWAT + 0U, // STWBRX + 0U, // STWCIX + 0U, // STWCX + 0U, // STWEPX + 0U, // STWU + 0U, // STWU8 + 0U, // STWUX + 0U, // STWUX8 + 0U, // STWX + 0U, // STWX8 + 0U, // STWXTLS + 0U, // STWXTLS_ + 0U, // STWXTLS_32 + 0U, // STXSD + 0U, // STXSDX + 0U, // STXSIBX + 0U, // STXSIBXv + 0U, // STXSIHX + 0U, // STXSIHXv + 0U, // STXSIWX + 0U, // STXSSP + 0U, // STXSSPX + 0U, // STXV + 0U, // STXVB16X + 0U, // STXVD2X + 0U, // STXVH8X + 0U, // STXVL + 0U, // STXVLL + 0U, // STXVP + 0U, // STXVPX + 0U, // STXVRBX + 0U, // STXVRDX + 0U, // STXVRHX + 0U, // STXVRWX + 0U, // STXVW4X + 0U, // STXVX + 0U, // SUBF + 0U, // SUBF8 + 0U, // SUBF8O + 0U, // SUBF8O_rec + 0U, // SUBF8_rec + 0U, // SUBFC + 0U, // SUBFC8 + 0U, // SUBFC8O + 0U, // SUBFC8O_rec + 0U, // SUBFC8_rec + 0U, // SUBFCO + 0U, // SUBFCO_rec + 0U, // SUBFC_rec + 0U, // SUBFE + 0U, // SUBFE8 + 0U, // SUBFE8O + 0U, // SUBFE8O_rec + 0U, // SUBFE8_rec + 0U, // SUBFEO + 0U, // SUBFEO_rec + 0U, // SUBFE_rec + 0U, // SUBFIC + 0U, // SUBFIC8 + 0U, // SUBFME + 0U, // SUBFME8 + 0U, // SUBFME8O + 0U, // SUBFME8O_rec + 0U, // SUBFME8_rec + 0U, // SUBFMEO + 0U, // SUBFMEO_rec + 0U, // SUBFME_rec + 0U, // SUBFO + 0U, // SUBFO_rec + 0U, // SUBFZE + 0U, // SUBFZE8 + 0U, // SUBFZE8O + 0U, // SUBFZE8O_rec + 0U, // SUBFZE8_rec + 0U, // SUBFZEO + 0U, // SUBFZEO_rec + 0U, // SUBFZE_rec + 0U, // SUBF_rec + 0U, // SYNC + 0U, // TABORT + 0U, // TABORTDC + 0U, // TABORTDCI + 0U, // TABORTWC + 0U, // TABORTWCI + 0U, // TAILB + 0U, // TAILB8 + 0U, // TAILBA + 0U, // TAILBA8 + 0U, // TAILBCTR + 0U, // TAILBCTR8 + 0U, // TBEGIN + 0U, // TBEGIN_RET + 0U, // TCHECK + 0U, // TCHECK_RET + 0U, // TCRETURNai + 0U, // TCRETURNai8 + 0U, // TCRETURNdi + 0U, // TCRETURNdi8 + 0U, // TCRETURNri + 0U, // TCRETURNri8 + 0U, // TD + 0U, // TDI + 0U, // TEND + 0U, // TLBIA + 0U, // TLBIE + 0U, // TLBIEL + 0U, // TLBIVAX + 0U, // TLBLD + 0U, // TLBLI + 0U, // TLBRE + 0U, // TLBRE2 + 0U, // TLBSX + 0U, // TLBSX2 + 0U, // TLBSX2D + 0U, // TLBSYNC + 0U, // TLBWE + 0U, // TLBWE2 + 0U, // TLSGDAIX + 0U, // TLSGDAIX8 + 0U, // TRAP + 0U, // TRECHKPT + 0U, // TRECLAIM + 0U, // TSR + 0U, // TW + 0U, // TWI + 0U, // UNENCODED_NOP + 0U, // UpdateGBR + 0U, // VABSDUB + 0U, // VABSDUH + 0U, // VABSDUW + 0U, // VADDCUQ + 0U, // VADDCUW + 0U, // VADDECUQ + 0U, // VADDEUQM + 0U, // VADDFP + 0U, // VADDSBS + 0U, // VADDSHS + 0U, // VADDSWS + 0U, // VADDUBM + 0U, // VADDUBS + 0U, // VADDUDM + 0U, // VADDUHM + 0U, // VADDUHS + 0U, // VADDUQM + 0U, // VADDUWM + 0U, // VADDUWS + 0U, // VAND + 0U, // VANDC + 0U, // VAVGSB + 0U, // VAVGSH + 0U, // VAVGSW + 0U, // VAVGUB + 0U, // VAVGUH + 0U, // VAVGUW + 0U, // VBPERMD + 0U, // VBPERMQ + 0U, // VCFSX + 0U, // VCFSX_0 + 0U, // VCFUGED + 0U, // VCFUX + 0U, // VCFUX_0 + 0U, // VCIPHER + 0U, // VCIPHERLAST + 0U, // VCLRLB + 0U, // VCLRRB + 0U, // VCLZB + 0U, // VCLZD + 0U, // VCLZDM + 0U, // VCLZH + 0U, // VCLZLSBB + 0U, // VCLZW + 0U, // VCMPBFP + 0U, // VCMPBFP_rec + 0U, // VCMPEQFP + 0U, // VCMPEQFP_rec + 0U, // VCMPEQUB + 0U, // VCMPEQUB_rec + 0U, // VCMPEQUD + 0U, // VCMPEQUD_rec + 0U, // VCMPEQUH + 0U, // VCMPEQUH_rec + 0U, // VCMPEQUQ + 0U, // VCMPEQUQ_rec + 0U, // VCMPEQUW + 0U, // VCMPEQUW_rec + 0U, // VCMPGEFP + 0U, // VCMPGEFP_rec + 0U, // VCMPGTFP + 0U, // VCMPGTFP_rec + 0U, // VCMPGTSB + 0U, // VCMPGTSB_rec + 0U, // VCMPGTSD + 0U, // VCMPGTSD_rec + 0U, // VCMPGTSH + 0U, // VCMPGTSH_rec + 0U, // VCMPGTSQ + 0U, // VCMPGTSQ_rec + 0U, // VCMPGTSW + 0U, // VCMPGTSW_rec + 0U, // VCMPGTUB + 0U, // VCMPGTUB_rec + 0U, // VCMPGTUD + 0U, // VCMPGTUD_rec + 0U, // VCMPGTUH + 0U, // VCMPGTUH_rec + 0U, // VCMPGTUQ + 0U, // VCMPGTUQ_rec + 0U, // VCMPGTUW + 0U, // VCMPGTUW_rec + 0U, // VCMPNEB + 0U, // VCMPNEB_rec + 0U, // VCMPNEH + 0U, // VCMPNEH_rec + 0U, // VCMPNEW + 0U, // VCMPNEW_rec + 0U, // VCMPNEZB + 0U, // VCMPNEZB_rec + 0U, // VCMPNEZH + 0U, // VCMPNEZH_rec + 0U, // VCMPNEZW + 0U, // VCMPNEZW_rec + 0U, // VCMPSQ + 0U, // VCMPUQ + 0U, // VCNTMBB + 0U, // VCNTMBD + 0U, // VCNTMBH + 0U, // VCNTMBW + 0U, // VCTSXS + 0U, // VCTSXS_0 + 0U, // VCTUXS + 0U, // VCTUXS_0 + 0U, // VCTZB + 0U, // VCTZD + 0U, // VCTZDM + 0U, // VCTZH + 0U, // VCTZLSBB + 0U, // VCTZW + 0U, // VDIVESD + 0U, // VDIVESQ + 0U, // VDIVESW + 0U, // VDIVEUD + 0U, // VDIVEUQ + 0U, // VDIVEUW + 0U, // VDIVSD + 0U, // VDIVSQ + 0U, // VDIVSW + 0U, // VDIVUD + 0U, // VDIVUQ + 0U, // VDIVUW + 0U, // VEQV + 0U, // VEXPANDBM + 0U, // VEXPANDDM + 0U, // VEXPANDHM + 0U, // VEXPANDQM + 0U, // VEXPANDWM + 0U, // VEXPTEFP + 0U, // VEXTDDVLX + 0U, // VEXTDDVRX + 0U, // VEXTDUBVLX + 0U, // VEXTDUBVRX + 0U, // VEXTDUHVLX + 0U, // VEXTDUHVRX + 0U, // VEXTDUWVLX + 0U, // VEXTDUWVRX + 0U, // VEXTRACTBM + 0U, // VEXTRACTD + 0U, // VEXTRACTDM + 0U, // VEXTRACTHM + 0U, // VEXTRACTQM + 0U, // VEXTRACTUB + 0U, // VEXTRACTUH + 0U, // VEXTRACTUW + 0U, // VEXTRACTWM + 0U, // VEXTSB2D + 0U, // VEXTSB2Ds + 0U, // VEXTSB2W + 0U, // VEXTSB2Ws + 0U, // VEXTSD2Q + 0U, // VEXTSH2D + 0U, // VEXTSH2Ds + 0U, // VEXTSH2W + 0U, // VEXTSH2Ws + 0U, // VEXTSW2D + 0U, // VEXTSW2Ds + 0U, // VEXTUBLX + 0U, // VEXTUBRX + 0U, // VEXTUHLX + 0U, // VEXTUHRX + 0U, // VEXTUWLX + 0U, // VEXTUWRX + 0U, // VGBBD + 0U, // VGNB + 0U, // VINSBLX + 0U, // VINSBRX + 0U, // VINSBVLX + 0U, // VINSBVRX + 0U, // VINSD + 0U, // VINSDLX + 0U, // VINSDRX + 0U, // VINSERTB + 0U, // VINSERTD + 0U, // VINSERTH + 0U, // VINSERTW + 0U, // VINSHLX + 0U, // VINSHRX + 0U, // VINSHVLX + 0U, // VINSHVRX + 0U, // VINSW + 0U, // VINSWLX + 0U, // VINSWRX + 0U, // VINSWVLX + 0U, // VINSWVRX + 0U, // VLOGEFP + 0U, // VMADDFP + 0U, // VMAXFP + 0U, // VMAXSB + 0U, // VMAXSD + 0U, // VMAXSH + 0U, // VMAXSW + 0U, // VMAXUB + 0U, // VMAXUD + 0U, // VMAXUH + 0U, // VMAXUW + 0U, // VMHADDSHS + 0U, // VMHRADDSHS + 0U, // VMINFP + 0U, // VMINSB + 0U, // VMINSD + 0U, // VMINSH + 0U, // VMINSW + 0U, // VMINUB + 0U, // VMINUD + 0U, // VMINUH + 0U, // VMINUW + 0U, // VMLADDUHM + 0U, // VMODSD + 0U, // VMODSQ + 0U, // VMODSW + 0U, // VMODUD + 0U, // VMODUQ + 0U, // VMODUW + 0U, // VMRGEW + 0U, // VMRGHB + 0U, // VMRGHH + 0U, // VMRGHW + 0U, // VMRGLB + 0U, // VMRGLH + 0U, // VMRGLW + 0U, // VMRGOW + 0U, // VMSUMCUD + 0U, // VMSUMMBM + 0U, // VMSUMSHM + 0U, // VMSUMSHS + 0U, // VMSUMUBM + 0U, // VMSUMUDM + 0U, // VMSUMUHM + 0U, // VMSUMUHS + 0U, // VMUL10CUQ + 0U, // VMUL10ECUQ + 0U, // VMUL10EUQ + 0U, // VMUL10UQ + 0U, // VMULESB + 0U, // VMULESD + 0U, // VMULESH + 0U, // VMULESW + 0U, // VMULEUB + 0U, // VMULEUD + 0U, // VMULEUH + 0U, // VMULEUW + 0U, // VMULHSD + 0U, // VMULHSW + 0U, // VMULHUD + 0U, // VMULHUW + 0U, // VMULLD + 0U, // VMULOSB + 0U, // VMULOSD + 0U, // VMULOSH + 0U, // VMULOSW + 0U, // VMULOUB + 0U, // VMULOUD + 0U, // VMULOUH + 0U, // VMULOUW + 0U, // VMULUWM + 0U, // VNAND + 0U, // VNCIPHER + 0U, // VNCIPHERLAST + 0U, // VNEGD + 0U, // VNEGW + 0U, // VNMSUBFP + 0U, // VNOR + 0U, // VOR + 0U, // VORC + 0U, // VPDEPD + 0U, // VPERM + 0U, // VPERMR + 0U, // VPERMXOR + 0U, // VPEXTD + 0U, // VPKPX + 0U, // VPKSDSS + 0U, // VPKSDUS + 0U, // VPKSHSS + 0U, // VPKSHUS + 0U, // VPKSWSS + 0U, // VPKSWUS + 0U, // VPKUDUM + 0U, // VPKUDUS + 0U, // VPKUHUM + 0U, // VPKUHUS + 0U, // VPKUWUM + 0U, // VPKUWUS + 0U, // VPMSUMB + 0U, // VPMSUMD + 0U, // VPMSUMH + 0U, // VPMSUMW + 0U, // VPOPCNTB + 0U, // VPOPCNTD + 0U, // VPOPCNTH + 0U, // VPOPCNTW + 0U, // VPRTYBD + 0U, // VPRTYBQ + 0U, // VPRTYBW + 0U, // VREFP + 0U, // VRFIM + 0U, // VRFIN + 0U, // VRFIP + 0U, // VRFIZ + 0U, // VRLB + 0U, // VRLD + 0U, // VRLDMI + 0U, // VRLDNM + 0U, // VRLH + 0U, // VRLQ + 0U, // VRLQMI + 0U, // VRLQNM + 0U, // VRLW + 0U, // VRLWMI + 0U, // VRLWNM + 0U, // VRSQRTEFP + 0U, // VSBOX + 0U, // VSEL + 0U, // VSHASIGMAD + 0U, // VSHASIGMAW + 0U, // VSL + 0U, // VSLB + 0U, // VSLD + 0U, // VSLDBI + 0U, // VSLDOI + 0U, // VSLH + 0U, // VSLO + 0U, // VSLQ + 0U, // VSLV + 0U, // VSLW + 0U, // VSPLTB + 0U, // VSPLTBs + 0U, // VSPLTH + 0U, // VSPLTHs + 0U, // VSPLTISB + 0U, // VSPLTISH + 0U, // VSPLTISW + 0U, // VSPLTW + 0U, // VSR + 0U, // VSRAB + 0U, // VSRAD + 0U, // VSRAH + 0U, // VSRAQ + 0U, // VSRAW + 0U, // VSRB + 0U, // VSRD + 0U, // VSRDBI + 0U, // VSRH + 0U, // VSRO + 0U, // VSRQ + 0U, // VSRV + 0U, // VSRW + 0U, // VSTRIBL + 0U, // VSTRIBL_rec + 0U, // VSTRIBR + 0U, // VSTRIBR_rec + 0U, // VSTRIHL + 0U, // VSTRIHL_rec + 0U, // VSTRIHR + 0U, // VSTRIHR_rec + 0U, // VSUBCUQ + 0U, // VSUBCUW + 0U, // VSUBECUQ + 0U, // VSUBEUQM + 0U, // VSUBFP + 0U, // VSUBSBS + 0U, // VSUBSHS + 0U, // VSUBSWS + 0U, // VSUBUBM + 0U, // VSUBUBS + 0U, // VSUBUDM + 0U, // VSUBUHM + 0U, // VSUBUHS + 0U, // VSUBUQM + 0U, // VSUBUWM + 0U, // VSUBUWS + 0U, // VSUM2SWS + 0U, // VSUM4SBS + 0U, // VSUM4SHS + 0U, // VSUM4UBS + 0U, // VSUMSWS + 0U, // VUPKHPX + 0U, // VUPKHSB + 0U, // VUPKHSH + 0U, // VUPKHSW + 0U, // VUPKLPX + 0U, // VUPKLSB + 0U, // VUPKLSH + 0U, // VUPKLSW + 0U, // VXOR + 0U, // V_SET0 + 0U, // V_SET0B + 0U, // V_SET0H + 0U, // V_SETALLONES + 0U, // V_SETALLONESB + 0U, // V_SETALLONESH + 0U, // WAIT + 0U, // WRTEE + 0U, // WRTEEI + 0U, // XOR + 0U, // XOR8 + 0U, // XOR8_rec + 0U, // XORI + 0U, // XORI8 + 0U, // XORIS + 0U, // XORIS8 + 0U, // XOR_rec + 0U, // XSABSDP + 0U, // XSABSQP + 0U, // XSADDDP + 0U, // XSADDQP + 0U, // XSADDQPO + 0U, // XSADDSP + 0U, // XSCMPEQDP + 0U, // XSCMPEXPDP + 0U, // XSCMPEXPQP + 0U, // XSCMPGEDP + 0U, // XSCMPGTDP + 0U, // XSCMPODP + 0U, // XSCMPOQP + 0U, // XSCMPUDP + 0U, // XSCMPUQP + 0U, // XSCPSGNDP + 0U, // XSCPSGNQP + 0U, // XSCVDPHP + 0U, // XSCVDPQP + 0U, // XSCVDPSP + 0U, // XSCVDPSPN + 0U, // XSCVDPSXDS + 0U, // XSCVDPSXDSs + 0U, // XSCVDPSXWS + 0U, // XSCVDPSXWSs + 0U, // XSCVDPUXDS + 0U, // XSCVDPUXDSs + 0U, // XSCVDPUXWS + 0U, // XSCVDPUXWSs + 0U, // XSCVHPDP + 0U, // XSCVQPDP + 0U, // XSCVQPDPO + 0U, // XSCVQPSDZ + 0U, // XSCVQPSQZ + 0U, // XSCVQPSWZ + 0U, // XSCVQPUDZ + 0U, // XSCVQPUQZ + 0U, // XSCVQPUWZ + 0U, // XSCVSDQP + 0U, // XSCVSPDP + 0U, // XSCVSPDPN + 0U, // XSCVSQQP + 0U, // XSCVSXDDP + 0U, // XSCVSXDSP + 0U, // XSCVUDQP + 0U, // XSCVUQQP + 0U, // XSCVUXDDP + 0U, // XSCVUXDSP + 0U, // XSDIVDP + 0U, // XSDIVQP + 0U, // XSDIVQPO + 0U, // XSDIVSP + 0U, // XSIEXPDP + 0U, // XSIEXPQP + 0U, // XSMADDADP + 0U, // XSMADDASP + 0U, // XSMADDMDP + 0U, // XSMADDMSP + 0U, // XSMADDQP + 0U, // XSMADDQPO + 0U, // XSMAXCDP + 0U, // XSMAXDP + 0U, // XSMAXJDP + 0U, // XSMINCDP + 0U, // XSMINDP + 0U, // XSMINJDP + 0U, // XSMSUBADP + 0U, // XSMSUBASP + 0U, // XSMSUBMDP + 0U, // XSMSUBMSP + 0U, // XSMSUBQP + 0U, // XSMSUBQPO + 0U, // XSMULDP + 0U, // XSMULQP + 0U, // XSMULQPO + 0U, // XSMULSP + 0U, // XSNABSDP + 0U, // XSNABSQP + 0U, // XSNEGDP + 0U, // XSNEGQP + 0U, // XSNMADDADP + 0U, // XSNMADDASP + 0U, // XSNMADDMDP + 0U, // XSNMADDMSP + 0U, // XSNMADDQP + 0U, // XSNMADDQPO + 0U, // XSNMSUBADP + 0U, // XSNMSUBASP + 0U, // XSNMSUBMDP + 0U, // XSNMSUBMSP + 0U, // XSNMSUBQP + 0U, // XSNMSUBQPO + 0U, // XSRDPI + 0U, // XSRDPIC + 0U, // XSRDPIM + 0U, // XSRDPIP + 0U, // XSRDPIZ + 0U, // XSREDP + 0U, // XSRESP + 0U, // XSRQPI + 0U, // XSRQPIX + 0U, // XSRQPXP + 0U, // XSRSP + 0U, // XSRSQRTEDP + 0U, // XSRSQRTESP + 0U, // XSSQRTDP + 0U, // XSSQRTQP + 0U, // XSSQRTQPO + 0U, // XSSQRTSP + 0U, // XSSUBDP + 0U, // XSSUBQP + 0U, // XSSUBQPO + 0U, // XSSUBSP + 0U, // XSTDIVDP + 0U, // XSTSQRTDP + 0U, // XSTSTDCDP + 0U, // XSTSTDCQP + 0U, // XSTSTDCSP + 0U, // XSXEXPDP + 0U, // XSXEXPQP + 0U, // XSXSIGDP + 0U, // XSXSIGQP + 0U, // XVABSDP + 0U, // XVABSSP + 0U, // XVADDDP + 0U, // XVADDSP + 0U, // XVBF16GER2 + 0U, // XVBF16GER2NN + 0U, // XVBF16GER2NP + 0U, // XVBF16GER2PN + 0U, // XVBF16GER2PP + 0U, // XVCMPEQDP + 0U, // XVCMPEQDP_rec + 0U, // XVCMPEQSP + 0U, // XVCMPEQSP_rec + 0U, // XVCMPGEDP + 0U, // XVCMPGEDP_rec + 0U, // XVCMPGESP + 0U, // XVCMPGESP_rec + 0U, // XVCMPGTDP + 0U, // XVCMPGTDP_rec + 0U, // XVCMPGTSP + 0U, // XVCMPGTSP_rec + 0U, // XVCPSGNDP + 0U, // XVCPSGNSP + 0U, // XVCVBF16SPN + 0U, // XVCVDPSP + 0U, // XVCVDPSXDS + 0U, // XVCVDPSXWS + 0U, // XVCVDPUXDS + 0U, // XVCVDPUXWS + 0U, // XVCVHPSP + 0U, // XVCVSPBF16 + 0U, // XVCVSPDP + 0U, // XVCVSPHP + 0U, // XVCVSPSXDS + 0U, // XVCVSPSXWS + 0U, // XVCVSPUXDS + 0U, // XVCVSPUXWS + 0U, // XVCVSXDDP + 0U, // XVCVSXDSP + 0U, // XVCVSXWDP + 0U, // XVCVSXWSP + 0U, // XVCVUXDDP + 0U, // XVCVUXDSP + 0U, // XVCVUXWDP + 0U, // XVCVUXWSP + 0U, // XVDIVDP + 0U, // XVDIVSP + 0U, // XVF16GER2 + 0U, // XVF16GER2NN + 0U, // XVF16GER2NP + 0U, // XVF16GER2PN + 0U, // XVF16GER2PP + 0U, // XVF32GER + 0U, // XVF32GERNN + 0U, // XVF32GERNP + 0U, // XVF32GERPN + 0U, // XVF32GERPP + 0U, // XVF64GER + 0U, // XVF64GERNN + 0U, // XVF64GERNP + 0U, // XVF64GERPN + 0U, // XVF64GERPP + 0U, // XVI16GER2 + 0U, // XVI16GER2PP + 0U, // XVI16GER2S + 0U, // XVI16GER2SPP + 0U, // XVI4GER8 + 0U, // XVI4GER8PP + 0U, // XVI8GER4 + 0U, // XVI8GER4PP + 0U, // XVI8GER4SPP + 0U, // XVIEXPDP + 0U, // XVIEXPSP + 0U, // XVMADDADP + 0U, // XVMADDASP + 0U, // XVMADDMDP + 0U, // XVMADDMSP + 0U, // XVMAXDP + 0U, // XVMAXSP + 0U, // XVMINDP + 0U, // XVMINSP + 0U, // XVMSUBADP + 0U, // XVMSUBASP + 0U, // XVMSUBMDP + 0U, // XVMSUBMSP + 0U, // XVMULDP + 0U, // XVMULSP + 0U, // XVNABSDP + 0U, // XVNABSSP + 0U, // XVNEGDP + 0U, // XVNEGSP + 0U, // XVNMADDADP + 0U, // XVNMADDASP + 0U, // XVNMADDMDP + 0U, // XVNMADDMSP + 0U, // XVNMSUBADP + 0U, // XVNMSUBASP + 0U, // XVNMSUBMDP + 0U, // XVNMSUBMSP + 0U, // XVRDPI + 0U, // XVRDPIC + 0U, // XVRDPIM + 0U, // XVRDPIP + 0U, // XVRDPIZ + 0U, // XVREDP + 0U, // XVRESP + 0U, // XVRSPI + 0U, // XVRSPIC + 0U, // XVRSPIM + 0U, // XVRSPIP + 0U, // XVRSPIZ + 0U, // XVRSQRTEDP + 0U, // XVRSQRTESP + 0U, // XVSQRTDP + 0U, // XVSQRTSP + 0U, // XVSUBDP + 0U, // XVSUBSP + 0U, // XVTDIVDP + 0U, // XVTDIVSP + 0U, // XVTLSBB + 0U, // XVTSQRTDP + 0U, // XVTSQRTSP + 0U, // XVTSTDCDP + 0U, // XVTSTDCSP + 0U, // XVXEXPDP + 0U, // XVXEXPSP + 0U, // XVXSIGDP + 0U, // XVXSIGSP + 0U, // XXBLENDVB + 0U, // XXBLENDVD + 0U, // XXBLENDVH + 0U, // XXBLENDVW + 0U, // XXBRD + 0U, // XXBRH + 0U, // XXBRQ + 0U, // XXBRW + 0U, // XXEVAL + 0U, // XXEXTRACTUW + 0U, // XXGENPCVBM + 0U, // XXGENPCVDM + 0U, // XXGENPCVHM + 0U, // XXGENPCVWM + 0U, // XXINSERTW + 0U, // XXLAND + 0U, // XXLANDC + 0U, // XXLEQV + 0U, // XXLEQVOnes + 0U, // XXLNAND + 0U, // XXLNOR + 0U, // XXLOR + 0U, // XXLORC + 0U, // XXLORf + 0U, // XXLXOR + 0U, // XXLXORdpz + 0U, // XXLXORspz + 0U, // XXLXORz + 0U, // XXMFACC + 0U, // XXMRGHW + 0U, // XXMRGLW + 0U, // XXMTACC + 0U, // XXPERM + 0U, // XXPERMDI + 0U, // XXPERMDIs + 0U, // XXPERMR + 0U, // XXPERMX + 0U, // XXSEL + 0U, // XXSETACCZ + 0U, // XXSLDWI + 0U, // XXSLDWIs + 0U, // XXSPLTI32DX + 0U, // XXSPLTIB + 0U, // XXSPLTIDP + 0U, // XXSPLTIW + 0U, // XXSPLTW + 0U, // XXSPLTWs + 0U, // gBC + 0U, // gBCA + 0U, // gBCAat + 0U, // gBCCTR + 0U, // gBCCTRL + 0U, // gBCL + 0U, // gBCLA + 0U, // gBCLAat + 0U, // gBCLR + 0U, // gBCLRL + 0U, // gBCLat + 0U, // gBCat + }; + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + Bits |= (uint64_t)OpInfo2[MCInst_getOpcode(MI)] << 48; + return createMnemonic(AsmStrs+(Bits & 32767)-1, Bits); + +} +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) { + MCMnemonic MnemonicInfo =PPC_getMnemonic(MI); + +#ifndef CAPSTONE_DIET + + SStream_concat0(O, MnemonicInfo.first); +#endif + + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 5 bits for 21 unique commands. + switch ((Bits >> 15) & 31) { + default: llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL... + printOperand/* printOperand (+ ) */(MI, 0, O); + break; + case 2: + // DCBFL, DCBFLP, DCBFPS, DCBFx, DCBSTPS, DCBTCT, DCBTDS, DCBTSTCT, DCBTS... + printMemRegReg/* printMemRegReg (+ ) */(MI, 0, O); + break; + case 3: + // ADJCALLSTACKDOWN, ADJCALLSTACKUP + printU16ImmOperand/* printU16ImmOperand (+ ) */(MI, 0, O); + SStream_concat0(O, " "); + printU16ImmOperand/* printU16ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 4: + // B, BCLalways, BDNZ, BDNZ8, BDNZL, BDNZLm, BDNZLp, BDNZm, BDNZp, BDZ, B... + printBranchOperand/* printBranchOperand (+ ) */(MI, 0, O); + break; + case 5: + // BA, BDNZA, BDNZAm, BDNZAp, BDNZLA, BDNZLAm, BDNZLAp, BDZA, BDZAm, BDZA... + printAbsBranchOperand/* printAbsBranchOperand (+ ) */(MI, 0, O); + break; + case 6: + // BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCC... + printPredicateOperand/* printPredicateOperand (+ cc) */(MI, 0, O, "cc"); + break; + case 7: + // BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL_LWZinto_toc, BCTRL_LWZi... + printMemRegImm/* printMemRegImm (+ ) */(MI, 0, O); + return; + break; + case 8: + // BL8_NOP_TLS, BL8_NOTOC_TLS, BL8_TLS, BL8_TLS_, BL_TLS + printTLSCall/* printTLSCall (+ ) */(MI, 0, O); + break; + case 9: + // DCBF, DCBT, DCBTST + printMemRegReg/* printMemRegReg (+ ) */(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 10: + // DCBTEP, DCBTSTEP + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 2, O); + SStream_concat0(O, ", "); + printMemRegReg/* printMemRegReg (+ ) */(MI, 0, O); + return; + break; + case 11: + // DSS, MBAR, MTFSB0, MTFSB1, TABORTDC, TABORTDCI, TABORTWC, TABORTWCI, T... + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 0, O); + break; + case 12: + // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, MTDCR, MTV... + printOperand/* printOperand (+ ) */(MI, 1, O); + break; + case 13: + // ICBLC, ICBLQ, ICBT, ICBTLS + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 0, O); + SStream_concat0(O, ", "); + printMemRegReg/* printMemRegReg (+ ) */(MI, 1, O); + return; + break; + case 14: + // MTFSFI, MTFSFI_rec, MTFSFIb + printU3ImmOperand/* printU3ImmOperand (+ ) */(MI, 0, O); + SStream_concat0(O, ", "); + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 1, O); + break; + case 15: + // MTOCRF, MTOCRF8 + printcrbitm/* printcrbitm (+ ) */(MI, 0, O); + SStream_concat0(O, ", "); + printOperand/* printOperand (+ ) */(MI, 1, O); + return; + break; + case 16: + // MTSR + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 1, O); + SStream_concat0(O, ", "); + printOperand/* printOperand (+ ) */(MI, 0, O); + return; + break; + case 17: + // RFEBB, TBEGIN, TEND, TSR + printU1ImmOperand/* printU1ImmOperand (+ ) */(MI, 0, O); + return; + break; + case 18: + // SYNC, WAIT + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 0, O); + return; + break; + case 19: + // XSRQPI, XSRQPIX, XSRQPXP + printU1ImmOperand/* printU1ImmOperand (+ ) */(MI, 1, O); + SStream_concat0(O, ", "); + printOperand/* printOperand (+ ) */(MI, 0, O); + SStream_concat0(O, ", "); + printOperand/* printOperand (+ ) */(MI, 2, O); + SStream_concat0(O, ", "); + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 3, O); + return; + break; + case 20: + // gBCAat, gBCLAat, gBCLat, gBCat + printATBitsAsHint/* printATBitsAsHint (+ ) */(MI, 1, O); + SStream_concat0(O, " "); + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 0, O); + SStream_concat0(O, ", "); + printOperand/* printOperand (+ ) */(MI, 2, O); + SStream_concat0(O, ", "); + break; + } + + + // Fragment 1 encoded into 5 bits for 21 unique commands. + switch ((Bits >> 20) & 31) { + default: llvm_unreachable("Invalid command number."); + case 0: + // BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL... + SStream_concat0(O, ", "); + break; + case 1: + // DCBFL, DCBFLP, DCBFPS, DCBFx, DCBSTPS, DCBTSTT, DCBTSTx, DCBTT, DCBTx,... + return; + break; + case 2: + // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, TCRETURNai, TCRETURNai8, TCR... + SStream_concat0(O, " "); + break; + case 3: + // BCC, CTRL_DEP + printPredicateOperand/* printPredicateOperand (+ pm) */(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand/* printPredicateOperand (+ reg) */(MI, 0, O, "reg"); + SStream_concat0(O, ", "); + printBranchOperand/* printBranchOperand (+ ) */(MI, 2, O); + return; + break; + case 4: + // BCCA + SStream_concat0(O, "a"); + printPredicateOperand/* printPredicateOperand (+ pm) */(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand/* printPredicateOperand (+ reg) */(MI, 0, O, "reg"); + SStream_concat0(O, ", "); + printAbsBranchOperand/* printAbsBranchOperand (+ ) */(MI, 2, O); + return; + break; + case 5: + // BCCCTR, BCCCTR8 + SStream_concat0(O, "ctr"); + printPredicateOperand/* printPredicateOperand (+ pm) */(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand/* printPredicateOperand (+ reg) */(MI, 0, O, "reg"); + return; + break; + case 6: + // BCCCTRL, BCCCTRL8 + SStream_concat0(O, "ctrl"); + printPredicateOperand/* printPredicateOperand (+ pm) */(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand/* printPredicateOperand (+ reg) */(MI, 0, O, "reg"); + return; + break; + case 7: + // BCCL + SStream_concat0(O, "l"); + printPredicateOperand/* printPredicateOperand (+ pm) */(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand/* printPredicateOperand (+ reg) */(MI, 0, O, "reg"); + SStream_concat0(O, ", "); + printBranchOperand/* printBranchOperand (+ ) */(MI, 2, O); + return; + break; + case 8: + // BCCLA + SStream_concat0(O, "la"); + printPredicateOperand/* printPredicateOperand (+ pm) */(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand/* printPredicateOperand (+ reg) */(MI, 0, O, "reg"); + SStream_concat0(O, ", "); + printAbsBranchOperand/* printAbsBranchOperand (+ ) */(MI, 2, O); + return; + break; + case 9: + // BCCLR + SStream_concat0(O, "lr"); + printPredicateOperand/* printPredicateOperand (+ pm) */(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand/* printPredicateOperand (+ reg) */(MI, 0, O, "reg"); + return; + break; + case 10: + // BCCLRL + SStream_concat0(O, "lrl"); + printPredicateOperand/* printPredicateOperand (+ pm) */(MI, 0, O, "pm"); + SStream_concat0(O, " "); + printPredicateOperand/* printPredicateOperand (+ reg) */(MI, 0, O, "reg"); + return; + break; + case 11: + // BCCTR, BCCTR8, BCCTR8n, BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, BCCTRn, BC... + SStream_concat0(O, ", 0"); + return; + break; + case 12: + // BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BLA8_NOP, BLA8_NOP_RM, BL_NOP, BL_NO... + SStream_concat0(O, "\n\tnop"); + return; + break; + case 13: + // DCBF + printU3ImmOperand/* printU3ImmOperand (+ ) */(MI, 0, O); + return; + break; + case 14: + // DCBT, DCBTST + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 0, O); + return; + break; + case 15: + // EVSEL, TLBIE + SStream_concat0(O, ","); + break; + case 16: + // MFTB8 + SStream_concat0(O, ", 268"); + return; + break; + case 17: + // MFVRSAVE, MFVRSAVEv + SStream_concat0(O, ", 256"); + return; + break; + case 18: + // V_SETALLONES, V_SETALLONESB, V_SETALLONESH + SStream_concat0(O, ", -1"); + return; + break; + case 19: + // gBCAat, gBCLAat + printAbsBranchOperand/* printAbsBranchOperand (+ ) */(MI, 3, O); + return; + break; + case 20: + // gBCLat, gBCat + printBranchOperand/* printBranchOperand (+ ) */(MI, 3, O); + return; + break; + } + + + // Fragment 2 encoded into 5 bits for 28 unique commands. + switch ((Bits >> 25) & 31) { + default: llvm_unreachable("Invalid command number."); + case 0: + // BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL... + printOperand/* printOperand (+ ) */(MI, 1, O); + break; + case 1: + // DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, EVADDIW + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 2, O); + break; + case 2: + // LAx, EVLDD, EVLDH, EVLDW, EVLHHESPLAT, EVLHHOSSPLAT, EVLHHOUSPLAT, EVL... + printMemRegImm/* printMemRegImm (+ ) */(MI, 1, O); + return; + break; + case 3: + // SUBPCIS, LI, LI8, LIS, LIS8 + printS16ImmOperand/* printS16ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 4: + // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, EVLDDX, EVLDHX, EVLDWX, EVLH... + printMemRegReg/* printMemRegReg (+ ) */(MI, 1, O); + break; + case 5: + // BC, BCL, BCLn, BCn + printBranchOperand/* printBranchOperand (+ ) */(MI, 1, O); + return; + break; + case 6: + // CMPRB, CMPRB8, MTMSR, MTMSRD + printU1ImmOperand/* printU1ImmOperand (+ ) */(MI, 1, O); + break; + case 7: + // CRSET, CRUNSET, MTDCR, TLBIE, V_SET0, V_SET0B, V_SET0H, XXLEQVOnes, XX... + printOperand/* printOperand (+ ) */(MI, 0, O); + break; + case 8: + // DARN, MFFSCRNI + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 9: + // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, MTFSFI, PM... + printOperand/* printOperand (+ ) */(MI, 2, O); + break; + case 10: + // EVSPLATFI, EVSPLATI, VSPLTISB, VSPLTISH, VSPLTISW + printS5ImmOperand/* printS5ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 11: + // EVSUBIFW + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 1, O); + SStream_concat0(O, ", "); + printOperand/* printOperand (+ ) */(MI, 2, O); + return; + break; + case 12: + // HASHCHK, HASHCHKP, HASHST, HASHSTP + printMemRegImmHash/* printMemRegImmHash (+ ) */(MI, 1, O); + return; + break; + case 13: + // LA + printS16ImmOperand/* printS16ImmOperand (+ ) */(MI, 2, O); + SStream_concat0(O, "("); + printOperand/* printOperand (+ ) */(MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + case 14: + // LBZU, LBZU8, LDU, LFDU, LFSU, LHAU, LHAU8, LHZU, LHZU8, LWZU, LWZU8, S... + printMemRegImm/* printMemRegImm (+ ) */(MI, 2, O); + return; + break; + case 15: + // LBZUX, LBZUX8, LDUX, LFDUX, LFSUX, LHAUX, LHAUX8, LHZUX, LHZUX8, LWAUX... + printMemRegReg/* printMemRegReg (+ ) */(MI, 2, O); + return; + break; + case 16: + // MFBHRBE + printU10ImmOperand/* printU10ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 17: + // MFFSCDRNI + printU3ImmOperand/* printU3ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 18: + // MFOCRF, MFOCRF8 + printcrbitm/* printcrbitm (+ ) */(MI, 1, O); + return; + break; + case 19: + // MFSR + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 20: + // MTFSFI_rec, XXSPLTI32DX + printU1ImmOperand/* printU1ImmOperand (+ ) */(MI, 2, O); + break; + case 21: + // MTVSRBMI + printU16ImmOperand/* printU16ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 22: + // PADDI8pc, PADDIpc + printImmZeroOperand/* printImmZeroOperand (+ ) */(MI, 1, O); + SStream_concat0(O, ", "); + printS34ImmOperand/* printS34ImmOperand (+ ) */(MI, 2, O); + SStream_concat0(O, ", 1"); + return; + break; + case 23: + // PLBZ, PLBZ8, PLD, PLFD, PLFS, PLHA, PLHA8, PLHZ, PLHZ8, PLWA, PLWA8, P... + printMemRegImm34/* printMemRegImm34 (+ ) */(MI, 1, O); + SStream_concat0(O, ", 0"); + return; + break; + case 24: + // PLBZ8pc, PLBZpc, PLDpc, PLFDpc, PLFSpc, PLHA8pc, PLHApc, PLHZ8pc, PLHZ... + printMemRegImm34PCRel/* printMemRegImm34PCRel (+ ) */(MI, 1, O); + SStream_concat0(O, ", 1"); + return; + break; + case 25: + // PLI, PLI8 + printS34ImmOperand/* printS34ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 26: + // VINSD, VINSERTB, VINSERTH, VINSW + printOperand/* printOperand (+ ) */(MI, 3, O); + SStream_concat0(O, ", "); + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 2, O); + return; + break; + case 27: + // XXSPLTIB + printU8ImmOperand/* printU8ImmOperand (+ ) */(MI, 1, O); + return; + break; + } + + + // Fragment 3 encoded into 3 bits for 6 unique commands. + switch ((Bits >> 30) & 7) { + default: llvm_unreachable("Invalid command number."); + case 0: + // BUILD_UACC, DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, ADDME, ADDME8, ADDME8O... + return; + break; + case 1: + // CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CLRRDI_rec, CL... + SStream_concat0(O, ", "); + break; + case 2: + // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32 + SStream_concat0(O, " "); + printOperand/* printOperand (+ ) */(MI, 3, O); + SStream_concat0(O, " "); + printOperand/* printOperand (+ ) */(MI, 4, O); + return; + break; + case 3: + // EVSEL + SStream_concat0(O, ","); + printOperand/* printOperand (+ ) */(MI, 2, O); + return; + break; + case 4: + // LBARXL, LDARXL, LHARXL, LQARXL, LWARXL + SStream_concat0(O, ", 1"); + return; + break; + case 5: + // VCFSX_0, VCFUX_0, VCTSXS_0, VCTUXS_0 + SStream_concat0(O, ", 0"); + return; + break; + } + + + // Fragment 4 encoded into 5 bits for 23 unique commands. + switch ((Bits >> 33) & 31) { + default: llvm_unreachable("Invalid command number."); + case 0: + // CLRLSLDI, CLRLSLDI_rec, CLRRDI, CLRRDI_rec, EXTLDI, EXTLDI_rec, EXTRDI... + printU6ImmOperand/* printU6ImmOperand (+ ) */(MI, 2, O); + break; + case 1: + // CLRLSLWI, CLRLSLWI_rec, CLRRWI, CLRRWI_rec, EXTLWI, EXTLWI_rec, EXTRWI... + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 2, O); + break; + case 2: + // SUBI, SUBIC, SUBIC_rec, SUBIS, ADDI, ADDI8, ADDIC, ADDIC8, ADDIC_rec, ... + printS16ImmOperand/* printS16ImmOperand (+ ) */(MI, 2, O); + return; + break; + case 3: + // ADD4, ADD4O, ADD4O_rec, ADD4TLS, ADD4_rec, ADD8, ADD8O, ADD8O_rec, ADD... + printOperand/* printOperand (+ ) */(MI, 2, O); + break; + case 4: + // ANDI8_rec, ANDIS8_rec, ANDIS_rec, ANDI_rec, CMPLDI, CMPLWI, ORI, ORI8,... + printU16ImmOperand/* printU16ImmOperand (+ ) */(MI, 2, O); + return; + break; + case 5: + // BCDCFN_rec, BCDCFSQ_rec, BCDCFZ_rec, BCDCTZ_rec, BCDSETSGN_rec, CP_PAS... + printU1ImmOperand/* printU1ImmOperand (+ ) */(MI, 2, O); + break; + case 6: + // CRSET, CRUNSET, V_SET0, V_SET0B, V_SET0H, XXLEQVOnes, XXLXORdpz, XXLXO... + printOperand/* printOperand (+ ) */(MI, 0, O); + return; + break; + case 7: + // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64 + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 0, O); + return; + break; + case 8: + // EVADDIW, XXPERMDIs, XXSLDWIs + printOperand/* printOperand (+ ) */(MI, 1, O); + break; + case 9: + // PADDI, PADDI8 + printS34ImmOperand/* printS34ImmOperand (+ ) */(MI, 2, O); + SStream_concat0(O, ", 0"); + return; + break; + case 10: + // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVF1... + printOperand/* printOperand (+ ) */(MI, 3, O); + break; + case 11: + // RLDIMI, RLDIMI_rec + printU6ImmOperand/* printU6ImmOperand (+ ) */(MI, 3, O); + SStream_concat0(O, ", "); + printU6ImmOperand/* printU6ImmOperand (+ ) */(MI, 4, O); + return; + break; + case 12: + // RLWIMI, RLWIMI8, RLWIMI8_rec, RLWIMI_rec + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 3, O); + SStream_concat0(O, ", "); + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 4, O); + SStream_concat0(O, ", "); + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 5, O); + return; + break; + case 13: + // VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTBs, VSPLTH, VSPLTHs, VSPLTW + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 14: + // VEXTRACTD, VEXTRACTUB, VEXTRACTUH, VEXTRACTUW, VINSERTD, VINSERTW + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 15: + // VGNB + printU3ImmOperand/* printU3ImmOperand (+ ) */(MI, 2, O); + return; + break; + case 16: + // XSTSTDCDP, XSTSTDCQP, XSTSTDCSP, XVTSTDCDP, XVTSTDCSP + printU7ImmOperand/* printU7ImmOperand (+ ) */(MI, 1, O); + return; + break; + case 17: + // XXEXTRACTUW + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 2, O); + return; + break; + case 18: + // XXGENPCVBM, XXGENPCVDM, XXGENPCVHM, XXGENPCVWM + printS5ImmOperand/* printS5ImmOperand (+ ) */(MI, 2, O); + return; + break; + case 19: + // XXINSERTW + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 3, O); + return; + break; + case 20: + // XXSPLTW, XXSPLTWs + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 2, O); + return; + break; + case 21: + // gBC, gBCL + printBranchOperand/* printBranchOperand (+ ) */(MI, 2, O); + return; + break; + case 22: + // gBCA, gBCLA + printAbsBranchOperand/* printAbsBranchOperand (+ ) */(MI, 2, O); + return; + break; + } + + + // Fragment 5 encoded into 1 bits for 2 unique commands. + if ((Bits >> 38) & 1) { + // CLRRDI, CLRRDI_rec, CLRRWI, CLRRWI_rec, ROTRDI, ROTRDI_rec, ROTRWI, RO... + return; + } else { + // CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, EXTLDI, EXTLDI_rec, EX... + SStream_concat0(O, ", "); + } + + + // Fragment 6 encoded into 4 bits for 9 unique commands. + switch ((Bits >> 39) & 15) { + default: llvm_unreachable("Invalid command number."); + case 0: + // CLRLSLDI, CLRLSLDI_rec, EXTLDI, EXTLDI_rec, EXTRDI, EXTRDI_rec, INSRDI... + printU6ImmOperand/* printU6ImmOperand (+ ) */(MI, 3, O); + return; + break; + case 1: + // CLRLSLWI, CLRLSLWI_rec, EXTLWI, EXTLWI_rec, EXTRWI, EXTRWI_rec, INSLWI... + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 3, O); + break; + case 2: + // RLWIMIbm, RLWIMIbm_rec, RLWINMbm, RLWINMbm_rec, RLWNMbm, RLWNMbm_rec, ... + printOperand/* printOperand (+ ) */(MI, 3, O); + break; + case 3: + // ADDEX, ADDEX8, XXPERMDI, XXSLDWI + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 3, O); + return; + break; + case 4: + // BCDSR_rec, BCDS_rec, BCDTRUNC_rec + printU1ImmOperand/* printU1ImmOperand (+ ) */(MI, 3, O); + return; + break; + case 5: + // PMXVBF16GER2, PMXVF16GER2, PMXVF32GER, PMXVF64GER, PMXVI16GER2, PMXVI1... + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 3, O); + break; + case 6: + // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVF1... + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 4, O); + SStream_concat0(O, ", "); + break; + case 7: + // VSLDBI, VSRDBI + printU3ImmOperand/* printU3ImmOperand (+ ) */(MI, 3, O); + return; + break; + case 8: + // XXPERMDIs, XXSLDWIs + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 2, O); + return; + break; + } + + + // Fragment 7 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 43) & 3) { + default: llvm_unreachable("Invalid command number."); + case 0: + // CLRLSLWI, CLRLSLWI_rec, EXTLWI, EXTLWI_rec, EXTRWI, EXTRWI_rec, INSLWI... + return; + break; + case 1: + // PMXVBF16GER2, PMXVF16GER2, PMXVF32GER, PMXVF64GER, PMXVI16GER2, PMXVI1... + SStream_concat0(O, ", "); + break; + case 2: + // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVF1... + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 5, O); + break; + case 3: + // PMXVF64GERNN, PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 5, O); + return; + break; + } + + + // Fragment 8 encoded into 3 bits for 7 unique commands. + switch ((Bits >> 45) & 7) { + default: llvm_unreachable("Invalid command number."); + case 0: + // PMXVBF16GER2, PMXVF16GER2, PMXVF32GER, PMXVI16GER2, PMXVI16GER2S, PMXV... + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 4, O); + break; + case 1: + // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVF1... + SStream_concat0(O, ", "); + break; + case 2: + // PMXVF32GERNN, PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP + return; + break; + case 3: + // PMXVF64GER + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 4, O); + return; + break; + case 4: + // RLWINM, RLWINM8, RLWINM8_rec, RLWINM_rec, RLWNM, RLWNM8, RLWNM8_rec, R... + printU5ImmOperand/* printU5ImmOperand (+ ) */(MI, 4, O); + return; + break; + case 5: + // XXEVAL + printU8ImmOperand/* printU8ImmOperand (+ ) */(MI, 4, O); + return; + break; + case 6: + // XXPERMX + printU3ImmOperand/* printU3ImmOperand (+ ) */(MI, 4, O); + return; + break; + } + + + // Fragment 9 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 48) & 7) { + default: llvm_unreachable("Invalid command number."); + case 0: + // PMXVBF16GER2, PMXVF16GER2, PMXVI16GER2, PMXVI16GER2S, PMXVI4GER8, PMXV... + SStream_concat0(O, ", "); + break; + case 1: + // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVF1... + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 6, O); + return; + break; + case 2: + // PMXVF32GER + return; + break; + case 3: + // PMXVI4GER8PP + printU8ImmOperand/* printU8ImmOperand (+ ) */(MI, 6, O); + return; + break; + case 4: + // PMXVI8GER4PP, PMXVI8GER4SPP + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 6, O); + return; + break; + } + + + // Fragment 10 encoded into 2 bits for 3 unique commands. + switch ((Bits >> 51) & 3) { + default: llvm_unreachable("Invalid command number."); + case 0: + // PMXVBF16GER2, PMXVF16GER2, PMXVI16GER2, PMXVI16GER2S + printU2ImmOperand/* printU2ImmOperand (+ ) */(MI, 5, O); + return; + break; + case 1: + // PMXVI4GER8 + printU8ImmOperand/* printU8ImmOperand (+ ) */(MI, 5, O); + return; + break; + case 2: + // PMXVI8GER4 + printU4ImmOperand/* printU4ImmOperand (+ ) */(MI, 5, O); + return; + break; + } + +} + + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo) { + assert(RegNo && RegNo < 376 && "Invalid register number!"); + + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "**ROUNDING MODE**\0" + /* 18 */ "**FRAME POINTER**\0" + /* 36 */ "**BASE POINTER**\0" + /* 53 */ "f10\0" + /* 57 */ "vsp10\0" + /* 63 */ "r10\0" + /* 67 */ "vs10\0" + /* 72 */ "v10\0" + /* 76 */ "f20\0" + /* 80 */ "vsp20\0" + /* 86 */ "r20\0" + /* 90 */ "vs20\0" + /* 95 */ "v20\0" + /* 99 */ "f30\0" + /* 103 */ "vsp30\0" + /* 109 */ "r30\0" + /* 113 */ "vs30\0" + /* 118 */ "v30\0" + /* 122 */ "vsp40\0" + /* 128 */ "vs40\0" + /* 133 */ "vsp50\0" + /* 139 */ "vs50\0" + /* 144 */ "vsp60\0" + /* 150 */ "vs60\0" + /* 155 */ "acc0\0" + /* 160 */ "f0\0" + /* 163 */ "vsp0\0" + /* 168 */ "cr0\0" + /* 172 */ "vs0\0" + /* 176 */ "v0\0" + /* 179 */ "f11\0" + /* 183 */ "r11\0" + /* 187 */ "vs11\0" + /* 192 */ "v11\0" + /* 196 */ "f21\0" + /* 200 */ "r21\0" + /* 204 */ "vs21\0" + /* 209 */ "v21\0" + /* 213 */ "f31\0" + /* 217 */ "r31\0" + /* 221 */ "vs31\0" + /* 226 */ "v31\0" + /* 230 */ "vs41\0" + /* 235 */ "vs51\0" + /* 240 */ "vs61\0" + /* 245 */ "acc1\0" + /* 250 */ "f1\0" + /* 253 */ "cr1\0" + /* 257 */ "vs1\0" + /* 261 */ "v1\0" + /* 264 */ "f12\0" + /* 268 */ "vsp12\0" + /* 274 */ "r12\0" + /* 278 */ "vs12\0" + /* 283 */ "v12\0" + /* 287 */ "f22\0" + /* 291 */ "vsp22\0" + /* 297 */ "r22\0" + /* 301 */ "vs22\0" + /* 306 */ "v22\0" + /* 310 */ "vsp32\0" + /* 316 */ "vs32\0" + /* 321 */ "vsp42\0" + /* 327 */ "vs42\0" + /* 332 */ "vsp52\0" + /* 338 */ "vs52\0" + /* 343 */ "vsp62\0" + /* 349 */ "vs62\0" + /* 354 */ "acc2\0" + /* 359 */ "f2\0" + /* 362 */ "vsp2\0" + /* 367 */ "cr2\0" + /* 371 */ "vs2\0" + /* 375 */ "v2\0" + /* 378 */ "f13\0" + /* 382 */ "r13\0" + /* 386 */ "vs13\0" + /* 391 */ "v13\0" + /* 395 */ "f23\0" + /* 399 */ "r23\0" + /* 403 */ "vs23\0" + /* 408 */ "v23\0" + /* 412 */ "vs33\0" + /* 417 */ "vs43\0" + /* 422 */ "vs53\0" + /* 427 */ "vs63\0" + /* 432 */ "acc3\0" + /* 437 */ "f3\0" + /* 440 */ "cr3\0" + /* 444 */ "vs3\0" + /* 448 */ "v3\0" + /* 451 */ "f14\0" + /* 455 */ "vsp14\0" + /* 461 */ "r14\0" + /* 465 */ "vs14\0" + /* 470 */ "v14\0" + /* 474 */ "f24\0" + /* 478 */ "vsp24\0" + /* 484 */ "r24\0" + /* 488 */ "vs24\0" + /* 493 */ "v24\0" + /* 497 */ "vsp34\0" + /* 503 */ "vs34\0" + /* 508 */ "vsp44\0" + /* 514 */ "vs44\0" + /* 519 */ "vsp54\0" + /* 525 */ "vs54\0" + /* 530 */ "acc4\0" + /* 535 */ "f4\0" + /* 538 */ "vsp4\0" + /* 543 */ "cr4\0" + /* 547 */ "vs4\0" + /* 551 */ "v4\0" + /* 554 */ "f15\0" + /* 558 */ "r15\0" + /* 562 */ "vs15\0" + /* 567 */ "v15\0" + /* 571 */ "f25\0" + /* 575 */ "r25\0" + /* 579 */ "vs25\0" + /* 584 */ "v25\0" + /* 588 */ "vs35\0" + /* 593 */ "vs45\0" + /* 598 */ "vs55\0" + /* 603 */ "acc5\0" + /* 608 */ "f5\0" + /* 611 */ "cr5\0" + /* 615 */ "vs5\0" + /* 619 */ "v5\0" + /* 622 */ "f16\0" + /* 626 */ "vsp16\0" + /* 632 */ "r16\0" + /* 636 */ "vs16\0" + /* 641 */ "v16\0" + /* 645 */ "f26\0" + /* 649 */ "vsp26\0" + /* 655 */ "r26\0" + /* 659 */ "vs26\0" + /* 664 */ "v26\0" + /* 668 */ "vsp36\0" + /* 674 */ "vs36\0" + /* 679 */ "vsp46\0" + /* 685 */ "vs46\0" + /* 690 */ "vsp56\0" + /* 696 */ "vs56\0" + /* 701 */ "acc6\0" + /* 706 */ "f6\0" + /* 709 */ "vsp6\0" + /* 714 */ "cr6\0" + /* 718 */ "vs6\0" + /* 722 */ "v6\0" + /* 725 */ "f17\0" + /* 729 */ "r17\0" + /* 733 */ "vs17\0" + /* 738 */ "v17\0" + /* 742 */ "f27\0" + /* 746 */ "r27\0" + /* 750 */ "vs27\0" + /* 755 */ "v27\0" + /* 759 */ "vs37\0" + /* 764 */ "vs47\0" + /* 769 */ "vs57\0" + /* 774 */ "acc7\0" + /* 779 */ "f7\0" + /* 782 */ "cr7\0" + /* 786 */ "vs7\0" + /* 790 */ "v7\0" + /* 793 */ "f18\0" + /* 797 */ "vsp18\0" + /* 803 */ "r18\0" + /* 807 */ "vs18\0" + /* 812 */ "v18\0" + /* 816 */ "f28\0" + /* 820 */ "vsp28\0" + /* 826 */ "r28\0" + /* 830 */ "vs28\0" + /* 835 */ "v28\0" + /* 839 */ "vsp38\0" + /* 845 */ "vs38\0" + /* 850 */ "vsp48\0" + /* 856 */ "vs48\0" + /* 861 */ "vsp58\0" + /* 867 */ "vs58\0" + /* 872 */ "f8\0" + /* 875 */ "vsp8\0" + /* 880 */ "r8\0" + /* 883 */ "vs8\0" + /* 887 */ "v8\0" + /* 890 */ "f19\0" + /* 894 */ "r19\0" + /* 898 */ "vs19\0" + /* 903 */ "v19\0" + /* 907 */ "f29\0" + /* 911 */ "r29\0" + /* 915 */ "vs29\0" + /* 920 */ "v29\0" + /* 924 */ "vs39\0" + /* 929 */ "vs49\0" + /* 934 */ "vs59\0" + /* 939 */ "f9\0" + /* 942 */ "r9\0" + /* 945 */ "vs9\0" + /* 949 */ "v9\0" + /* 952 */ "vrsave\0" + /* 959 */ "spefscr\0" + /* 967 */ "xer\0" + /* 971 */ "lr\0" + /* 974 */ "ctr\0" +}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint16_t RegAsmOffset[] = { + 36, 967, 974, 18, 971, 0, 959, 952, 967, 55, 155, 245, 354, 432, + 530, 603, 701, 774, 36, 168, 253, 367, 440, 543, 611, 714, 782, 974, + 160, 250, 359, 437, 535, 608, 706, 779, 872, 939, 53, 179, 264, 378, + 451, 554, 622, 725, 793, 890, 76, 196, 287, 395, 474, 571, 645, 742, + 816, 907, 99, 213, 18, 971, 169, 254, 368, 441, 544, 612, 715, 783, + 880, 942, 63, 183, 274, 382, 461, 558, 632, 729, 803, 894, 86, 200, + 297, 399, 484, 575, 655, 746, 826, 911, 109, 217, 169, 254, 368, 441, + 544, 612, 715, 783, 880, 942, 63, 183, 274, 382, 461, 558, 632, 729, + 803, 894, 86, 200, 297, 399, 484, 575, 655, 746, 826, 911, 109, 217, + 155, 245, 354, 432, 530, 603, 701, 774, 176, 261, 375, 448, 551, 619, + 722, 790, 887, 949, 72, 192, 283, 391, 470, 567, 641, 738, 812, 903, + 95, 209, 306, 408, 493, 584, 664, 755, 835, 920, 118, 226, 176, 261, + 375, 448, 551, 619, 722, 790, 887, 949, 72, 192, 283, 391, 470, 567, + 641, 738, 812, 903, 95, 209, 306, 408, 493, 584, 664, 755, 835, 920, + 118, 226, 172, 257, 371, 444, 547, 615, 718, 786, 883, 945, 67, 187, + 278, 386, 465, 562, 636, 733, 807, 898, 90, 204, 301, 403, 488, 579, + 659, 750, 830, 915, 113, 221, 163, 362, 538, 709, 875, 57, 268, 455, + 626, 797, 80, 291, 478, 649, 820, 103, 310, 497, 668, 839, 122, 321, + 508, 679, 850, 133, 332, 519, 690, 861, 144, 343, 316, 412, 503, 588, + 674, 759, 845, 924, 128, 230, 327, 417, 514, 593, 685, 764, 856, 929, + 139, 235, 338, 422, 525, 598, 696, 769, 867, 934, 150, 240, 349, 427, + 169, 254, 368, 441, 544, 612, 715, 783, 880, 942, 63, 183, 274, 382, + 461, 558, 632, 729, 803, 894, 86, 200, 297, 399, 484, 575, 655, 746, + 826, 911, 109, 217, 55, 266, 624, 54, 452, 794, 288, 646, 100, 181, + 556, 892, 379, 726, 197, 572, 908, 55, 453, 795, 265, 623, 77, 475, + 817, 380, 727, 180, 555, 891, 396, 743, 214, 169, 368, 544, 715, 880, + 63, 274, 461, 632, 803, 86, 297, 484, 655, 826, 109, + }; + + assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && + "Invalid alt name index for register!"); + return AsmStrs+RegAsmOffset[RegNo-1]; +} +#endif +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +void printCustomAliasOperand( + const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, + SStream *OS); + +static char* printAliasInstr(MCInst *MI, SStream *OS) { + static const PatternsForOpcode OpToPatterns[] = { + {PPC_ADDI, 0, 1 }, + {PPC_ADDI8, 1, 1 }, + {PPC_ADDIS, 2, 1 }, + {PPC_ADDIS8, 3, 1 }, + {PPC_ADDPCIS, 4, 1 }, + {PPC_BCC, 5, 24 }, + {PPC_BCCA, 29, 24 }, + {PPC_BCCCTR, 53, 24 }, + {PPC_BCCCTRL, 77, 24 }, + {PPC_BCCL, 101, 24 }, + {PPC_BCCLA, 125, 24 }, + {PPC_BCCLR, 149, 24 }, + {PPC_BCCLRL, 173, 24 }, + {PPC_CMPD, 197, 1 }, + {PPC_CMPDI, 198, 1 }, + {PPC_CMPLD, 199, 1 }, + {PPC_CMPLDI, 200, 1 }, + {PPC_CMPLW, 201, 1 }, + {PPC_CMPLWI, 202, 1 }, + {PPC_CMPW, 203, 1 }, + {PPC_CMPWI, 204, 1 }, + {PPC_CNTLZW, 205, 1 }, + {PPC_CNTLZW8, 206, 1 }, + {PPC_CNTLZW8_rec, 207, 1 }, + {PPC_CNTLZW_rec, 208, 1 }, + {PPC_CP_PASTE_rec, 209, 1 }, + {PPC_CREQV, 210, 1 }, + {PPC_CRNOR, 211, 1 }, + {PPC_CROR, 212, 1 }, + {PPC_CRXOR, 213, 1 }, + {PPC_ISEL, 214, 3 }, + {PPC_ISEL8, 217, 3 }, + {PPC_MBAR, 220, 1 }, + {PPC_MFDCR, 221, 8 }, + {PPC_MFSPR, 229, 46 }, + {PPC_MFSPR8, 275, 19 }, + {PPC_MFTB, 294, 1 }, + {PPC_MFVRSAVE, 295, 1 }, + {PPC_MFVSRD, 296, 1 }, + {PPC_MFVSRWZ, 297, 1 }, + {PPC_MTCRF, 298, 1 }, + {PPC_MTCRF8, 299, 1 }, + {PPC_MTDCR, 300, 8 }, + {PPC_MTFSF, 308, 1 }, + {PPC_MTFSFI, 309, 1 }, + {PPC_MTFSFI_rec, 310, 1 }, + {PPC_MTFSF_rec, 311, 1 }, + {PPC_MTMSR, 312, 1 }, + {PPC_MTMSRD, 313, 1 }, + {PPC_MTSPR, 314, 45 }, + {PPC_MTSPR8, 359, 18 }, + {PPC_MTVRSAVE, 377, 1 }, + {PPC_MTVSRD, 378, 1 }, + {PPC_MTVSRWA, 379, 1 }, + {PPC_MTVSRWZ, 380, 1 }, + {PPC_NOR, 381, 1 }, + {PPC_NOR8, 382, 1 }, + {PPC_NOR8_rec, 383, 1 }, + {PPC_NOR_rec, 384, 1 }, + {PPC_OR, 385, 1 }, + {PPC_OR8, 386, 1 }, + {PPC_OR8_rec, 387, 1 }, + {PPC_ORI, 388, 1 }, + {PPC_ORI8, 389, 1 }, + {PPC_OR_rec, 390, 1 }, + {PPC_RFEBB, 391, 1 }, + {PPC_RLDCL, 392, 1 }, + {PPC_RLDCL_rec, 393, 1 }, + {PPC_RLDICL, 394, 2 }, + {PPC_RLDICL_32_64, 396, 2 }, + {PPC_RLDICL_rec, 398, 2 }, + {PPC_RLWINM, 400, 2 }, + {PPC_RLWINM8, 402, 2 }, + {PPC_RLWINM8_rec, 404, 2 }, + {PPC_RLWINM_rec, 406, 2 }, + {PPC_RLWNM, 408, 1 }, + {PPC_RLWNM8, 409, 1 }, + {PPC_RLWNM8_rec, 410, 1 }, + {PPC_RLWNM_rec, 411, 1 }, + {PPC_SC, 412, 1 }, + {PPC_SUBF, 413, 1 }, + {PPC_SUBF8, 414, 1 }, + {PPC_SUBF8_rec, 415, 1 }, + {PPC_SUBFC, 416, 1 }, + {PPC_SUBFC8, 417, 1 }, + {PPC_SUBFC8_rec, 418, 1 }, + {PPC_SUBFC_rec, 419, 1 }, + {PPC_SUBF_rec, 420, 1 }, + {PPC_SYNC, 421, 3 }, + {PPC_TD, 424, 7 }, + {PPC_TDI, 431, 7 }, + {PPC_TEND, 438, 2 }, + {PPC_TLBIE, 440, 1 }, + {PPC_TLBRE2, 441, 2 }, + {PPC_TLBWE2, 443, 2 }, + {PPC_TSR, 445, 2 }, + {PPC_TW, 447, 8 }, + {PPC_TWI, 455, 7 }, + {PPC_VNOR, 462, 1 }, + {PPC_VOR, 463, 1 }, + {PPC_WAIT, 464, 3 }, + {PPC_XORI, 467, 1 }, + {PPC_XORI8, 468, 1 }, + {PPC_XVCPSGNDP, 469, 1 }, + {PPC_XVCPSGNSP, 470, 1 }, + {PPC_XXPERMDI, 471, 5 }, + {PPC_XXPERMDIs, 476, 3 }, + {PPC_gBC, 479, 10 }, + {PPC_gBCA, 489, 10 }, + {PPC_gBCAat, 499, 2 }, + {PPC_gBCCTR, 501, 7 }, + {PPC_gBCCTRL, 508, 7 }, + {PPC_gBCL, 515, 10 }, + {PPC_gBCLA, 525, 10 }, + {PPC_gBCLAat, 535, 2 }, + {PPC_gBCLR, 537, 11 }, + {PPC_gBCLRL, 548, 11 }, + {PPC_gBCLat, 559, 2 }, + {PPC_gBCat, 561, 2 }, + }; + + static const AliasPattern Patterns[] = { + // PPC::ADDI - 0 + {0, 0, 3, 2 }, + // PPC::ADDI8 - 1 + {0, 2, 3, 2 }, + // PPC::ADDIS - 2 + {12, 4, 3, 2 }, + // PPC::ADDIS8 - 3 + {12, 6, 3, 2 }, + // PPC::ADDPCIS - 4 + {25, 8, 2, 2 }, + // PPC::BCC - 5 + {33, 10, 3, 2 }, + {46, 12, 3, 2 }, + {55, 14, 3, 2 }, + {69, 16, 3, 2 }, + {79, 18, 3, 2 }, + {93, 20, 3, 2 }, + {103, 22, 3, 2 }, + {116, 24, 3, 2 }, + {125, 26, 3, 2 }, + {139, 28, 3, 2 }, + {149, 30, 3, 2 }, + {163, 32, 3, 2 }, + {173, 34, 3, 2 }, + {186, 36, 3, 2 }, + {195, 38, 3, 2 }, + {209, 40, 3, 2 }, + {219, 42, 3, 2 }, + {233, 44, 3, 2 }, + {243, 46, 3, 2 }, + {256, 48, 3, 2 }, + {265, 50, 3, 2 }, + {279, 52, 3, 2 }, + {289, 54, 3, 2 }, + {303, 56, 3, 2 }, + // PPC::BCCA - 29 + {313, 58, 3, 2 }, + {327, 60, 3, 2 }, + {337, 62, 3, 2 }, + {352, 64, 3, 2 }, + {363, 66, 3, 2 }, + {378, 68, 3, 2 }, + {389, 70, 3, 2 }, + {403, 72, 3, 2 }, + {413, 74, 3, 2 }, + {428, 76, 3, 2 }, + {439, 78, 3, 2 }, + {454, 80, 3, 2 }, + {465, 82, 3, 2 }, + {479, 84, 3, 2 }, + {489, 86, 3, 2 }, + {504, 88, 3, 2 }, + {515, 90, 3, 2 }, + {530, 92, 3, 2 }, + {541, 94, 3, 2 }, + {555, 96, 3, 2 }, + {565, 98, 3, 2 }, + {580, 100, 3, 2 }, + {591, 102, 3, 2 }, + {606, 104, 3, 2 }, + // PPC::BCCCTR - 53 + {617, 106, 2, 2 }, + {627, 108, 2, 2 }, + {634, 110, 2, 2 }, + {645, 112, 2, 2 }, + {653, 114, 2, 2 }, + {664, 116, 2, 2 }, + {672, 118, 2, 2 }, + {682, 120, 2, 2 }, + {689, 122, 2, 2 }, + {700, 124, 2, 2 }, + {708, 126, 2, 2 }, + {719, 128, 2, 2 }, + {727, 130, 2, 2 }, + {737, 132, 2, 2 }, + {744, 134, 2, 2 }, + {755, 136, 2, 2 }, + {763, 138, 2, 2 }, + {774, 140, 2, 2 }, + {782, 142, 2, 2 }, + {792, 144, 2, 2 }, + {799, 146, 2, 2 }, + {810, 148, 2, 2 }, + {818, 150, 2, 2 }, + {829, 152, 2, 2 }, + // PPC::BCCCTRL - 77 + {837, 154, 2, 2 }, + {848, 156, 2, 2 }, + {856, 158, 2, 2 }, + {868, 160, 2, 2 }, + {877, 162, 2, 2 }, + {889, 164, 2, 2 }, + {898, 166, 2, 2 }, + {909, 168, 2, 2 }, + {917, 170, 2, 2 }, + {929, 172, 2, 2 }, + {938, 174, 2, 2 }, + {950, 176, 2, 2 }, + {959, 178, 2, 2 }, + {970, 180, 2, 2 }, + {978, 182, 2, 2 }, + {990, 184, 2, 2 }, + {999, 186, 2, 2 }, + {1011, 188, 2, 2 }, + {1020, 190, 2, 2 }, + {1031, 192, 2, 2 }, + {1039, 194, 2, 2 }, + {1051, 196, 2, 2 }, + {1060, 198, 2, 2 }, + {1072, 200, 2, 2 }, + // PPC::BCCL - 101 + {1081, 202, 3, 2 }, + {1095, 204, 3, 2 }, + {1105, 206, 3, 2 }, + {1120, 208, 3, 2 }, + {1131, 210, 3, 2 }, + {1146, 212, 3, 2 }, + {1157, 214, 3, 2 }, + {1171, 216, 3, 2 }, + {1181, 218, 3, 2 }, + {1196, 220, 3, 2 }, + {1207, 222, 3, 2 }, + {1222, 224, 3, 2 }, + {1233, 226, 3, 2 }, + {1247, 228, 3, 2 }, + {1257, 230, 3, 2 }, + {1272, 232, 3, 2 }, + {1283, 234, 3, 2 }, + {1298, 236, 3, 2 }, + {1309, 238, 3, 2 }, + {1323, 240, 3, 2 }, + {1333, 242, 3, 2 }, + {1348, 244, 3, 2 }, + {1359, 246, 3, 2 }, + {1374, 248, 3, 2 }, + // PPC::BCCLA - 125 + {1385, 250, 3, 2 }, + {1400, 252, 3, 2 }, + {1411, 254, 3, 2 }, + {1427, 256, 3, 2 }, + {1439, 258, 3, 2 }, + {1455, 260, 3, 2 }, + {1467, 262, 3, 2 }, + {1482, 264, 3, 2 }, + {1493, 266, 3, 2 }, + {1509, 268, 3, 2 }, + {1521, 270, 3, 2 }, + {1537, 272, 3, 2 }, + {1549, 274, 3, 2 }, + {1564, 276, 3, 2 }, + {1575, 278, 3, 2 }, + {1591, 280, 3, 2 }, + {1603, 282, 3, 2 }, + {1619, 284, 3, 2 }, + {1631, 286, 3, 2 }, + {1646, 288, 3, 2 }, + {1657, 290, 3, 2 }, + {1673, 292, 3, 2 }, + {1685, 294, 3, 2 }, + {1701, 296, 3, 2 }, + // PPC::BCCLR - 149 + {1713, 298, 2, 2 }, + {1722, 300, 2, 2 }, + {1728, 302, 2, 2 }, + {1738, 304, 2, 2 }, + {1745, 306, 2, 2 }, + {1755, 308, 2, 2 }, + {1762, 310, 2, 2 }, + {1771, 312, 2, 2 }, + {1777, 314, 2, 2 }, + {1787, 316, 2, 2 }, + {1794, 318, 2, 2 }, + {1804, 320, 2, 2 }, + {1811, 322, 2, 2 }, + {1820, 324, 2, 2 }, + {1826, 326, 2, 2 }, + {1836, 328, 2, 2 }, + {1843, 330, 2, 2 }, + {1853, 332, 2, 2 }, + {1860, 334, 2, 2 }, + {1869, 336, 2, 2 }, + {1875, 338, 2, 2 }, + {1885, 340, 2, 2 }, + {1892, 342, 2, 2 }, + {1902, 344, 2, 2 }, + // PPC::BCCLRL - 173 + {1909, 346, 2, 2 }, + {1919, 348, 2, 2 }, + {1926, 350, 2, 2 }, + {1937, 352, 2, 2 }, + {1945, 354, 2, 2 }, + {1956, 356, 2, 2 }, + {1964, 358, 2, 2 }, + {1974, 360, 2, 2 }, + {1981, 362, 2, 2 }, + {1992, 364, 2, 2 }, + {2000, 366, 2, 2 }, + {2011, 368, 2, 2 }, + {2019, 370, 2, 2 }, + {2029, 372, 2, 2 }, + {2036, 374, 2, 2 }, + {2047, 376, 2, 2 }, + {2055, 378, 2, 2 }, + {2066, 380, 2, 2 }, + {2074, 382, 2, 2 }, + {2084, 384, 2, 2 }, + {2091, 386, 2, 2 }, + {2102, 388, 2, 2 }, + {2110, 390, 2, 2 }, + {2121, 392, 2, 2 }, + // PPC::CMPD - 197 + {2129, 394, 3, 3 }, + // PPC::CMPDI - 198 + {2141, 397, 3, 2 }, + // PPC::CMPLD - 199 + {2156, 399, 3, 3 }, + // PPC::CMPLDI - 200 + {2169, 402, 3, 2 }, + // PPC::CMPLW - 201 + {2185, 404, 3, 3 }, + // PPC::CMPLWI - 202 + {2198, 407, 3, 2 }, + // PPC::CMPW - 203 + {2214, 409, 3, 3 }, + // PPC::CMPWI - 204 + {2226, 412, 3, 2 }, + // PPC::CNTLZW - 205 + {2241, 414, 2, 2 }, + // PPC::CNTLZW8 - 206 + {2241, 416, 2, 2 }, + // PPC::CNTLZW8_rec - 207 + {2255, 418, 2, 2 }, + // PPC::CNTLZW_rec - 208 + {2255, 420, 2, 2 }, + // PPC::CP_PASTE_rec - 209 + {2270, 422, 3, 3 }, + // PPC::CREQV - 210 + {2284, 425, 3, 3 }, + // PPC::CRNOR - 211 + {2293, 428, 3, 3 }, + // PPC::CROR - 212 + {2306, 431, 3, 3 }, + // PPC::CRXOR - 213 + {2320, 434, 3, 3 }, + // PPC::ISEL - 214 + {2329, 437, 4, 4 }, + {2347, 441, 4, 4 }, + {2365, 445, 4, 4 }, + // PPC::ISEL8 - 217 + {2329, 449, 4, 4 }, + {2347, 453, 4, 4 }, + {2365, 457, 4, 4 }, + // PPC::MBAR - 220 + {2383, 461, 1, 1 }, + // PPC::MFDCR - 221 + {2388, 462, 2, 5 }, + {2397, 467, 2, 5 }, + {2406, 472, 2, 5 }, + {2415, 477, 2, 5 }, + {2424, 482, 2, 5 }, + {2433, 487, 2, 5 }, + {2442, 492, 2, 5 }, + {2451, 497, 2, 5 }, + // PPC::MFSPR - 229 + {2460, 502, 2, 2 }, + {2469, 504, 2, 5 }, + {2480, 509, 2, 5 }, + {2490, 514, 2, 5 }, + {2500, 519, 2, 5 }, + {2508, 524, 2, 5 }, + {2517, 529, 2, 5 }, + {2527, 534, 2, 5 }, + {2537, 539, 2, 5 }, + {2548, 544, 2, 5 }, + {2557, 549, 2, 5 }, + {2566, 554, 2, 5 }, + {2576, 559, 2, 5 }, + {2586, 564, 2, 5 }, + {2596, 569, 2, 5 }, + {2606, 574, 2, 5 }, + {2615, 579, 2, 5 }, + {2624, 584, 2, 5 }, + {2633, 589, 2, 5 }, + {2642, 594, 2, 5 }, + {2655, 599, 2, 5 }, + {2669, 604, 2, 5 }, + {2683, 609, 2, 5 }, + {2697, 614, 2, 5 }, + {2711, 619, 2, 5 }, + {2725, 624, 2, 5 }, + {2739, 629, 2, 5 }, + {2753, 634, 2, 5 }, + {2767, 639, 2, 5 }, + {2781, 644, 2, 5 }, + {2795, 649, 2, 5 }, + {2809, 654, 2, 5 }, + {2823, 659, 2, 5 }, + {2837, 664, 2, 5 }, + {2851, 669, 2, 5 }, + {2865, 674, 2, 5 }, + {2879, 679, 2, 5 }, + {2888, 684, 2, 5 }, + {2897, 689, 2, 5 }, + {2907, 694, 2, 5 }, + {2916, 699, 2, 5 }, + {2926, 704, 2, 5 }, + {2936, 709, 2, 5 }, + {2946, 714, 2, 5 }, + {2956, 719, 2, 5 }, + {2966, 724, 2, 5 }, + // PPC::MFSPR8 - 275 + {2460, 729, 2, 2 }, + {2469, 731, 2, 5 }, + {2480, 736, 2, 5 }, + {2490, 741, 2, 5 }, + {2500, 746, 2, 5 }, + {2508, 751, 2, 5 }, + {2517, 756, 2, 5 }, + {2527, 761, 2, 5 }, + {2537, 766, 2, 5 }, + {2548, 771, 2, 5 }, + {2557, 776, 2, 5 }, + {2566, 781, 2, 5 }, + {2576, 786, 2, 5 }, + {2586, 791, 2, 5 }, + {2596, 796, 2, 5 }, + {2606, 801, 2, 5 }, + {2624, 806, 2, 5 }, + {2633, 811, 2, 5 }, + {2642, 816, 2, 5 }, + // PPC::MFTB - 294 + {2976, 821, 2, 2 }, + // PPC::MFVRSAVE - 295 + {2985, 823, 1, 1 }, + // PPC::MFVSRD - 296 + {2997, 824, 2, 2 }, + // PPC::MFVSRWZ - 297 + {3011, 826, 2, 2 }, + // PPC::MTCRF - 298 + {3026, 828, 2, 2 }, + // PPC::MTCRF8 - 299 + {3026, 830, 2, 2 }, + // PPC::MTDCR - 300 + {3034, 832, 2, 5 }, + {3043, 837, 2, 5 }, + {3052, 842, 2, 5 }, + {3061, 847, 2, 5 }, + {3070, 852, 2, 5 }, + {3079, 857, 2, 5 }, + {3088, 862, 2, 5 }, + {3097, 867, 2, 5 }, + // PPC::MTFSF - 308 + {3106, 872, 4, 4 }, + // PPC::MTFSFI - 309 + {3119, 876, 3, 3 }, + // PPC::MTFSFI_rec - 310 + {3137, 879, 3, 3 }, + // PPC::MTFSF_rec - 311 + {3156, 882, 4, 4 }, + // PPC::MTMSR - 312 + {3170, 886, 2, 5 }, + // PPC::MTMSRD - 313 + {3179, 891, 2, 5 }, + // PPC::MTSPR - 314 + {3189, 896, 2, 2 }, + {3198, 898, 2, 5 }, + {3209, 903, 2, 5 }, + {3217, 908, 2, 5 }, + {3226, 913, 2, 5 }, + {3236, 918, 2, 5 }, + {3246, 923, 2, 5 }, + {3257, 928, 2, 5 }, + {3266, 933, 2, 5 }, + {3275, 938, 2, 5 }, + {3285, 943, 2, 5 }, + {3295, 948, 2, 5 }, + {3305, 953, 2, 5 }, + {3315, 958, 2, 5 }, + {3324, 963, 2, 5 }, + {3333, 968, 2, 5 }, + {3342, 973, 2, 5 }, + {3351, 978, 2, 5 }, + {3360, 983, 2, 5 }, + {3373, 988, 2, 5 }, + {3387, 993, 2, 5 }, + {3401, 998, 2, 5 }, + {3415, 1003, 2, 5 }, + {3429, 1008, 2, 5 }, + {3443, 1013, 2, 5 }, + {3457, 1018, 2, 5 }, + {3471, 1023, 2, 5 }, + {3485, 1028, 2, 5 }, + {3499, 1033, 2, 5 }, + {3513, 1038, 2, 5 }, + {3527, 1043, 2, 5 }, + {3541, 1048, 2, 5 }, + {3555, 1053, 2, 5 }, + {3569, 1058, 2, 5 }, + {3583, 1063, 2, 5 }, + {3597, 1068, 2, 5 }, + {3606, 1073, 2, 5 }, + {3615, 1078, 2, 5 }, + {3625, 1083, 2, 5 }, + {3634, 1088, 2, 5 }, + {3644, 1093, 2, 5 }, + {3654, 1098, 2, 5 }, + {3664, 1103, 2, 5 }, + {3674, 1108, 2, 5 }, + {3684, 1113, 2, 5 }, + // PPC::MTSPR8 - 359 + {3189, 1118, 2, 2 }, + {3198, 1120, 2, 5 }, + {3209, 1125, 2, 5 }, + {3217, 1130, 2, 5 }, + {3226, 1135, 2, 5 }, + {3236, 1140, 2, 5 }, + {3246, 1145, 2, 5 }, + {3257, 1150, 2, 5 }, + {3266, 1155, 2, 5 }, + {3275, 1160, 2, 5 }, + {3285, 1165, 2, 5 }, + {3295, 1170, 2, 5 }, + {3305, 1175, 2, 5 }, + {3315, 1180, 2, 5 }, + {3333, 1185, 2, 5 }, + {3342, 1190, 2, 5 }, + {3351, 1195, 2, 5 }, + {3360, 1200, 2, 5 }, + // PPC::MTVRSAVE - 377 + {3694, 1205, 1, 1 }, + // PPC::MTVSRD - 378 + {3706, 1206, 2, 2 }, + // PPC::MTVSRWA - 379 + {3720, 1208, 2, 2 }, + // PPC::MTVSRWZ - 380 + {3735, 1210, 2, 2 }, + // PPC::NOR - 381 + {3750, 1212, 3, 3 }, + // PPC::NOR8 - 382 + {3750, 1215, 3, 3 }, + // PPC::NOR8_rec - 383 + {3761, 1218, 3, 3 }, + // PPC::NOR_rec - 384 + {3761, 1221, 3, 3 }, + // PPC::OR - 385 + {3773, 1224, 3, 3 }, + // PPC::OR8 - 386 + {3773, 1227, 3, 3 }, + // PPC::OR8_rec - 387 + {3783, 1230, 3, 3 }, + // PPC::ORI - 388 + {3794, 1233, 3, 3 }, + // PPC::ORI8 - 389 + {3794, 1236, 3, 3 }, + // PPC::OR_rec - 390 + {3783, 1239, 3, 3 }, + // PPC::RFEBB - 391 + {3798, 1242, 1, 1 }, + // PPC::RLDCL - 392 + {3804, 1243, 4, 4 }, + // PPC::RLDCL_rec - 393 + {3821, 1247, 4, 4 }, + // PPC::RLDICL - 394 + {3839, 1251, 4, 4 }, + {3859, 1255, 4, 3 }, + // PPC::RLDICL_32_64 - 396 + {3839, 1258, 4, 4 }, + {3859, 1262, 4, 3 }, + // PPC::RLDICL_rec - 398 + {3879, 1265, 4, 4 }, + {3900, 1269, 4, 3 }, + // PPC::RLWINM - 400 + {3921, 1272, 5, 5 }, + {3941, 1277, 5, 5 }, + // PPC::RLWINM8 - 402 + {3921, 1282, 5, 5 }, + {3941, 1287, 5, 5 }, + // PPC::RLWINM8_rec - 404 + {3961, 1292, 5, 5 }, + {3982, 1297, 5, 5 }, + // PPC::RLWINM_rec - 406 + {3961, 1302, 5, 5 }, + {3982, 1307, 5, 5 }, + // PPC::RLWNM - 408 + {4003, 1312, 5, 5 }, + // PPC::RLWNM8 - 409 + {4003, 1317, 5, 5 }, + // PPC::RLWNM8_rec - 410 + {4020, 1322, 5, 5 }, + // PPC::RLWNM_rec - 411 + {4020, 1327, 5, 5 }, + // PPC::SC - 412 + {4038, 1332, 1, 1 }, + // PPC::SUBF - 413 + {4041, 1333, 3, 3 }, + // PPC::SUBF8 - 414 + {4041, 1336, 3, 3 }, + // PPC::SUBF8_rec - 415 + {4056, 1339, 3, 3 }, + // PPC::SUBFC - 416 + {4072, 1342, 3, 3 }, + // PPC::SUBFC8 - 417 + {4072, 1345, 3, 3 }, + // PPC::SUBFC8_rec - 418 + {4088, 1348, 3, 3 }, + // PPC::SUBFC_rec - 419 + {4088, 1351, 3, 3 }, + // PPC::SUBF_rec - 420 + {4056, 1354, 3, 3 }, + // PPC::SYNC - 421 + {4105, 1357, 1, 1 }, + {4110, 1358, 1, 1 }, + {4117, 1359, 1, 1 }, + // PPC::TD - 424 + {4125, 1360, 3, 3 }, + {4137, 1363, 3, 3 }, + {4149, 1366, 3, 3 }, + {4161, 1369, 3, 3 }, + {4173, 1372, 3, 3 }, + {4186, 1375, 3, 3 }, + {4199, 1378, 3, 3 }, + // PPC::TDI - 431 + {4210, 1381, 3, 2 }, + {4225, 1383, 3, 2 }, + {4240, 1385, 3, 2 }, + {4255, 1387, 3, 2 }, + {4270, 1389, 3, 2 }, + {4286, 1391, 3, 2 }, + {4302, 1393, 3, 2 }, + // PPC::TEND - 438 + {4316, 1395, 1, 1 }, + {4322, 1396, 1, 1 }, + // PPC::TLBIE - 440 + {4331, 1397, 2, 2 }, + // PPC::TLBRE2 - 441 + {4340, 1399, 3, 3 }, + {4355, 1402, 3, 3 }, + // PPC::TLBWE2 - 443 + {4370, 1405, 3, 3 }, + {4385, 1408, 3, 3 }, + // PPC::TSR - 445 + {4400, 1411, 1, 1 }, + {4410, 1412, 1, 1 }, + // PPC::TW - 447 + {4419, 1413, 3, 3 }, + {4424, 1416, 3, 3 }, + {4436, 1419, 3, 3 }, + {4448, 1422, 3, 3 }, + {4460, 1425, 3, 3 }, + {4472, 1428, 3, 3 }, + {4485, 1431, 3, 3 }, + {4498, 1434, 3, 3 }, + // PPC::TWI - 455 + {4509, 1437, 3, 2 }, + {4524, 1439, 3, 2 }, + {4539, 1441, 3, 2 }, + {4554, 1443, 3, 2 }, + {4569, 1445, 3, 2 }, + {4585, 1447, 3, 2 }, + {4601, 1449, 3, 2 }, + // PPC::VNOR - 462 + {4615, 1451, 3, 3 }, + // PPC::VOR - 463 + {4627, 1454, 3, 3 }, + // PPC::WAIT - 464 + {4638, 1457, 1, 1 }, + {4643, 1458, 1, 1 }, + {4651, 1459, 1, 1 }, + // PPC::XORI - 467 + {4660, 1460, 3, 3 }, + // PPC::XORI8 - 468 + {4660, 1463, 3, 3 }, + // PPC::XVCPSGNDP - 469 + {4665, 1466, 3, 3 }, + // PPC::XVCPSGNSP - 470 + {4680, 1469, 3, 3 }, + // PPC::XXPERMDI - 471 + {4695, 1472, 4, 7 }, + {4713, 1479, 4, 7 }, + {4731, 1486, 4, 4 }, + {4750, 1490, 4, 4 }, + {4769, 1494, 4, 4 }, + // PPC::XXPERMDIs - 476 + {4695, 1498, 3, 6 }, + {4713, 1504, 3, 6 }, + {4769, 1510, 3, 3 }, + // PPC::gBC - 479 + {4784, 1513, 3, 2 }, + {4796, 1515, 3, 2 }, + {4808, 1517, 3, 2 }, + {4821, 1519, 3, 2 }, + {4834, 1521, 3, 2 }, + {4847, 1523, 3, 2 }, + {4860, 1525, 3, 2 }, + {4875, 1527, 3, 2 }, + {4890, 1529, 3, 2 }, + {4904, 1531, 3, 2 }, + // PPC::gBCA - 489 + {4918, 1533, 3, 2 }, + {4931, 1535, 3, 2 }, + {4944, 1537, 3, 2 }, + {4958, 1539, 3, 2 }, + {4972, 1541, 3, 2 }, + {4986, 1543, 3, 2 }, + {5000, 1545, 3, 2 }, + {5016, 1547, 3, 2 }, + {5032, 1549, 3, 2 }, + {5047, 1551, 3, 2 }, + // PPC::gBCAat - 499 + {5062, 1553, 4, 3 }, + {5082, 1556, 4, 3 }, + // PPC::gBCCTR - 501 + {5102, 1559, 3, 3 }, + {5117, 1562, 3, 3 }, + {5126, 1565, 3, 3 }, + {5135, 1568, 3, 3 }, + {5145, 1571, 3, 3 }, + {5155, 1574, 3, 3 }, + {5165, 1577, 3, 3 }, + // PPC::gBCCTRL - 508 + {5175, 1580, 3, 3 }, + {5191, 1583, 3, 3 }, + {5201, 1586, 3, 3 }, + {5211, 1589, 3, 3 }, + {5222, 1592, 3, 3 }, + {5233, 1595, 3, 3 }, + {5244, 1598, 3, 3 }, + // PPC::gBCL - 515 + {5255, 1601, 3, 2 }, + {5268, 1603, 3, 2 }, + {5281, 1605, 3, 2 }, + {5295, 1607, 3, 2 }, + {5309, 1609, 3, 2 }, + {5323, 1611, 3, 2 }, + {5337, 1613, 3, 2 }, + {5353, 1615, 3, 2 }, + {5369, 1617, 3, 2 }, + {5384, 1619, 3, 2 }, + // PPC::gBCLA - 525 + {5399, 1621, 3, 2 }, + {5413, 1623, 3, 2 }, + {5427, 1625, 3, 2 }, + {5442, 1627, 3, 2 }, + {5457, 1629, 3, 2 }, + {5472, 1631, 3, 2 }, + {5487, 1633, 3, 2 }, + {5504, 1635, 3, 2 }, + {5521, 1637, 3, 2 }, + {5537, 1639, 3, 2 }, + // PPC::gBCLAat - 535 + {5553, 1641, 4, 3 }, + {5574, 1644, 4, 3 }, + // PPC::gBCLR - 537 + {5595, 1647, 3, 3 }, + {5609, 1650, 3, 3 }, + {5617, 1653, 3, 3 }, + {5625, 1656, 3, 3 }, + {5634, 1659, 3, 3 }, + {5643, 1662, 3, 3 }, + {5652, 1665, 3, 3 }, + {5661, 1668, 3, 3 }, + {5672, 1671, 3, 3 }, + {5683, 1674, 3, 3 }, + {5693, 1677, 3, 3 }, + // PPC::gBCLRL - 548 + {5703, 1680, 3, 3 }, + {5718, 1683, 3, 3 }, + {5727, 1686, 3, 3 }, + {5736, 1689, 3, 3 }, + {5746, 1692, 3, 3 }, + {5756, 1695, 3, 3 }, + {5766, 1698, 3, 3 }, + {5776, 1701, 3, 3 }, + {5788, 1704, 3, 3 }, + {5800, 1707, 3, 3 }, + {5811, 1710, 3, 3 }, + // PPC::gBCLat - 559 + {5822, 1713, 4, 3 }, + {5842, 1716, 4, 3 }, + // PPC::gBCat - 561 + {5862, 1719, 4, 3 }, + {5881, 1722, 4, 3 }, + }; + + static const AliasPatternCond Conds[] = { + // (ADDI gprc:$rD, ZERO, s16imm:$imm) - 0 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Reg, PPC_ZERO}, + // (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm) - 2 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Reg, PPC_ZERO8}, + // (ADDIS gprc:$rD, ZERO, s17imm:$imm) - 4 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Reg, PPC_ZERO}, + // (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm) - 6 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Reg, PPC_ZERO8}, + // (ADDPCIS g8rc:$RT, 0) - 8 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BCC 12, crrc:$cc, condbrtarget:$dst) - 10 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 12, CR0, condbrtarget:$dst) - 12 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 14, crrc:$cc, condbrtarget:$dst) - 14 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 14, CR0, condbrtarget:$dst) - 16 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 15, crrc:$cc, condbrtarget:$dst) - 18 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 15, CR0, condbrtarget:$dst) - 20 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 44, crrc:$cc, condbrtarget:$dst) - 22 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 44, CR0, condbrtarget:$dst) - 24 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 46, crrc:$cc, condbrtarget:$dst) - 26 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 46, CR0, condbrtarget:$dst) - 28 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 47, crrc:$cc, condbrtarget:$dst) - 30 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 47, CR0, condbrtarget:$dst) - 32 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 76, crrc:$cc, condbrtarget:$dst) - 34 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 76, CR0, condbrtarget:$dst) - 36 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 78, crrc:$cc, condbrtarget:$dst) - 38 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 78, CR0, condbrtarget:$dst) - 40 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 79, crrc:$cc, condbrtarget:$dst) - 42 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 79, CR0, condbrtarget:$dst) - 44 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 68, crrc:$cc, condbrtarget:$dst) - 46 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 68, CR0, condbrtarget:$dst) - 48 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 70, crrc:$cc, condbrtarget:$dst) - 50 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 70, CR0, condbrtarget:$dst) - 52 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCC 71, crrc:$cc, condbrtarget:$dst) - 54 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCC 71, CR0, condbrtarget:$dst) - 56 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 12, crrc:$cc, abscondbrtarget:$dst) - 58 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 12, CR0, abscondbrtarget:$dst) - 60 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 14, crrc:$cc, abscondbrtarget:$dst) - 62 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 14, CR0, abscondbrtarget:$dst) - 64 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 15, crrc:$cc, abscondbrtarget:$dst) - 66 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 15, CR0, abscondbrtarget:$dst) - 68 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 44, crrc:$cc, abscondbrtarget:$dst) - 70 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 44, CR0, abscondbrtarget:$dst) - 72 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 46, crrc:$cc, abscondbrtarget:$dst) - 74 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 46, CR0, abscondbrtarget:$dst) - 76 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 47, crrc:$cc, abscondbrtarget:$dst) - 78 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 47, CR0, abscondbrtarget:$dst) - 80 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 76, crrc:$cc, abscondbrtarget:$dst) - 82 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 76, CR0, abscondbrtarget:$dst) - 84 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 78, crrc:$cc, abscondbrtarget:$dst) - 86 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 78, CR0, abscondbrtarget:$dst) - 88 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 79, crrc:$cc, abscondbrtarget:$dst) - 90 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 79, CR0, abscondbrtarget:$dst) - 92 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 68, crrc:$cc, abscondbrtarget:$dst) - 94 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 68, CR0, abscondbrtarget:$dst) - 96 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 70, crrc:$cc, abscondbrtarget:$dst) - 98 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 70, CR0, abscondbrtarget:$dst) - 100 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCA 71, crrc:$cc, abscondbrtarget:$dst) - 102 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCA 71, CR0, abscondbrtarget:$dst) - 104 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 12, crrc:$cc) - 106 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 12, CR0) - 108 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 14, crrc:$cc) - 110 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 14, CR0) - 112 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 15, crrc:$cc) - 114 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 15, CR0) - 116 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 44, crrc:$cc) - 118 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 44, CR0) - 120 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 46, crrc:$cc) - 122 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 46, CR0) - 124 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 47, crrc:$cc) - 126 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 47, CR0) - 128 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 76, crrc:$cc) - 130 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 76, CR0) - 132 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 78, crrc:$cc) - 134 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 78, CR0) - 136 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 79, crrc:$cc) - 138 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 79, CR0) - 140 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 68, crrc:$cc) - 142 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 68, CR0) - 144 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 70, crrc:$cc) - 146 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 70, CR0) - 148 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTR 71, crrc:$cc) - 150 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTR 71, CR0) - 152 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 12, crrc:$cc) - 154 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 12, CR0) - 156 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 14, crrc:$cc) - 158 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 14, CR0) - 160 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 15, crrc:$cc) - 162 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 15, CR0) - 164 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 44, crrc:$cc) - 166 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 44, CR0) - 168 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 46, crrc:$cc) - 170 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 46, CR0) - 172 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 47, crrc:$cc) - 174 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 47, CR0) - 176 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 76, crrc:$cc) - 178 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 76, CR0) - 180 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 78, crrc:$cc) - 182 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 78, CR0) - 184 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 79, crrc:$cc) - 186 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 79, CR0) - 188 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 68, crrc:$cc) - 190 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 68, CR0) - 192 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 70, crrc:$cc) - 194 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 70, CR0) - 196 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCCTRL 71, crrc:$cc) - 198 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCCTRL 71, CR0) - 200 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 12, crrc:$cc, condbrtarget:$dst) - 202 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 12, CR0, condbrtarget:$dst) - 204 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 14, crrc:$cc, condbrtarget:$dst) - 206 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 14, CR0, condbrtarget:$dst) - 208 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 15, crrc:$cc, condbrtarget:$dst) - 210 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 15, CR0, condbrtarget:$dst) - 212 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 44, crrc:$cc, condbrtarget:$dst) - 214 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 44, CR0, condbrtarget:$dst) - 216 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 46, crrc:$cc, condbrtarget:$dst) - 218 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 46, CR0, condbrtarget:$dst) - 220 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 47, crrc:$cc, condbrtarget:$dst) - 222 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 47, CR0, condbrtarget:$dst) - 224 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 76, crrc:$cc, condbrtarget:$dst) - 226 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 76, CR0, condbrtarget:$dst) - 228 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 78, crrc:$cc, condbrtarget:$dst) - 230 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 78, CR0, condbrtarget:$dst) - 232 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 79, crrc:$cc, condbrtarget:$dst) - 234 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 79, CR0, condbrtarget:$dst) - 236 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 68, crrc:$cc, condbrtarget:$dst) - 238 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 68, CR0, condbrtarget:$dst) - 240 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 70, crrc:$cc, condbrtarget:$dst) - 242 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 70, CR0, condbrtarget:$dst) - 244 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCL 71, crrc:$cc, condbrtarget:$dst) - 246 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCL 71, CR0, condbrtarget:$dst) - 248 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 12, crrc:$cc, abscondbrtarget:$dst) - 250 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 12, CR0, abscondbrtarget:$dst) - 252 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 14, crrc:$cc, abscondbrtarget:$dst) - 254 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 14, CR0, abscondbrtarget:$dst) - 256 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 15, crrc:$cc, abscondbrtarget:$dst) - 258 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 15, CR0, abscondbrtarget:$dst) - 260 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 44, crrc:$cc, abscondbrtarget:$dst) - 262 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 44, CR0, abscondbrtarget:$dst) - 264 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 46, crrc:$cc, abscondbrtarget:$dst) - 266 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 46, CR0, abscondbrtarget:$dst) - 268 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 47, crrc:$cc, abscondbrtarget:$dst) - 270 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 47, CR0, abscondbrtarget:$dst) - 272 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 76, crrc:$cc, abscondbrtarget:$dst) - 274 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 76, CR0, abscondbrtarget:$dst) - 276 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 78, crrc:$cc, abscondbrtarget:$dst) - 278 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 78, CR0, abscondbrtarget:$dst) - 280 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 79, crrc:$cc, abscondbrtarget:$dst) - 282 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 79, CR0, abscondbrtarget:$dst) - 284 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 68, crrc:$cc, abscondbrtarget:$dst) - 286 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 68, CR0, abscondbrtarget:$dst) - 288 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 70, crrc:$cc, abscondbrtarget:$dst) - 290 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 70, CR0, abscondbrtarget:$dst) - 292 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLA 71, crrc:$cc, abscondbrtarget:$dst) - 294 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLA 71, CR0, abscondbrtarget:$dst) - 296 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 12, crrc:$cc) - 298 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 12, CR0) - 300 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 14, crrc:$cc) - 302 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 14, CR0) - 304 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 15, crrc:$cc) - 306 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 15, CR0) - 308 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 44, crrc:$cc) - 310 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 44, CR0) - 312 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 46, crrc:$cc) - 314 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 46, CR0) - 316 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 47, crrc:$cc) - 318 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 47, CR0) - 320 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 76, crrc:$cc) - 322 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 76, CR0) - 324 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 78, crrc:$cc) - 326 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 78, CR0) - 328 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 79, crrc:$cc) - 330 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 79, CR0) - 332 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 68, crrc:$cc) - 334 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 68, CR0) - 336 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 70, crrc:$cc) - 338 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 70, CR0) - 340 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLR 71, crrc:$cc) - 342 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLR 71, CR0) - 344 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 12, crrc:$cc) - 346 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 12, CR0) - 348 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 14, crrc:$cc) - 350 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 14, CR0) - 352 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 15, crrc:$cc) - 354 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 15, CR0) - 356 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 44, crrc:$cc) - 358 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 44, CR0) - 360 + {AliasPatternCond_K_Imm, (uint32_t)44}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 46, crrc:$cc) - 362 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 46, CR0) - 364 + {AliasPatternCond_K_Imm, (uint32_t)46}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 47, crrc:$cc) - 366 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 47, CR0) - 368 + {AliasPatternCond_K_Imm, (uint32_t)47}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 76, crrc:$cc) - 370 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 76, CR0) - 372 + {AliasPatternCond_K_Imm, (uint32_t)76}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 78, crrc:$cc) - 374 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 78, CR0) - 376 + {AliasPatternCond_K_Imm, (uint32_t)78}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 79, crrc:$cc) - 378 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 79, CR0) - 380 + {AliasPatternCond_K_Imm, (uint32_t)79}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 68, crrc:$cc) - 382 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 68, CR0) - 384 + {AliasPatternCond_K_Imm, (uint32_t)68}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 70, crrc:$cc) - 386 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 70, CR0) - 388 + {AliasPatternCond_K_Imm, (uint32_t)70}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (BCCLRL 71, crrc:$cc) - 390 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_RegClass, PPC_CRRCRegClassID}, + // (BCCLRL 71, CR0) - 392 + {AliasPatternCond_K_Imm, (uint32_t)71}, + {AliasPatternCond_K_Reg, PPC_CR0}, + // (CMPD CR0, g8rc:$rA, g8rc:$rB) - 394 + {AliasPatternCond_K_Reg, PPC_CR0}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (CMPDI CR0, g8rc:$rA, s16imm64:$imm) - 397 + {AliasPatternCond_K_Reg, PPC_CR0}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (CMPLD CR0, g8rc:$rA, g8rc:$rB) - 399 + {AliasPatternCond_K_Reg, PPC_CR0}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (CMPLDI CR0, g8rc:$rA, u16imm64:$imm) - 402 + {AliasPatternCond_K_Reg, PPC_CR0}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (CMPLW CR0, gprc:$rA, gprc:$rB) - 404 + {AliasPatternCond_K_Reg, PPC_CR0}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (CMPLWI CR0, gprc:$rA, u16imm:$imm) - 407 + {AliasPatternCond_K_Reg, PPC_CR0}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (CMPW CR0, gprc:$rA, gprc:$rB) - 409 + {AliasPatternCond_K_Reg, PPC_CR0}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (CMPWI CR0, gprc:$rA, s16imm:$imm) - 412 + {AliasPatternCond_K_Reg, PPC_CR0}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (CNTLZW gprc:$rA, gprc:$rS) - 414 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (CNTLZW8 g8rc:$rA, g8rc:$rS) - 416 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (CNTLZW8_rec g8rc:$rA, g8rc:$rS) - 418 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (CNTLZW_rec gprc:$rA, gprc:$rS) - 420 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (CP_PASTE_rec gprc:$RA, gprc:$RB, 1) - 422 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) - 425 + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_TiedReg, 0}, + // (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by) - 428 + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by) - 431 + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) - 434 + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_TiedReg, 0}, + // (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT) - 437 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRC_NOR0RegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Reg, PPC_CR0LT}, + // (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT) - 441 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRC_NOR0RegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Reg, PPC_CR0GT}, + // (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ) - 445 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRC_NOR0RegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Reg, PPC_CR0EQ}, + // (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT) - 449 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RC_NOX0RegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Reg, PPC_CR0LT}, + // (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT) - 453 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RC_NOX0RegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Reg, PPC_CR0GT}, + // (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ) - 457 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RC_NOX0RegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Reg, PPC_CR0EQ}, + // (MBAR 0) - 461 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MFDCR gprc:$Rx, 128) - 462 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)128}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFDCR gprc:$Rx, 129) - 467 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)129}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFDCR gprc:$Rx, 130) - 472 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)130}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFDCR gprc:$Rx, 131) - 477 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)131}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFDCR gprc:$Rx, 132) - 482 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)132}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFDCR gprc:$Rx, 133) - 487 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)133}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFDCR gprc:$Rx, 134) - 492 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)134}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFDCR gprc:$Rx, 135) - 497 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)135}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 1) - 502 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (MFSPR gprc:$Rx, 3) - 504 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 4) - 509 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 5) - 514 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 8) - 519 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 9) - 524 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 13) - 529 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 17) - 534 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)17}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 18) - 539 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)18}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 19) - 544 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)19}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 22) - 549 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)22}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 25) - 554 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)25}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 26) - 559 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)26}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 27) - 564 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)27}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 28) - 569 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 29) - 574 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)29}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 48) - 579 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)48}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$RT, 280) - 584 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)280}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$RT, 287) - 589 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)287}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 512) - 594 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)512}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 536) - 599 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)536}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 537) - 604 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)537}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 528) - 609 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)528}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 529) - 614 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)529}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 538) - 619 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)538}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 539) - 624 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)539}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 530) - 629 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)530}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 531) - 634 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)531}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 540) - 639 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)540}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 541) - 644 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)541}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 532) - 649 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)532}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 533) - 654 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)533}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 542) - 659 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)542}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 543) - 664 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)543}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 534) - 669 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)534}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 535) - 674 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)535}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$RT, 896) - 679 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)896}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 980) - 684 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)980}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 981) - 689 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)981}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 986) - 694 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)986}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 988) - 699 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)988}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 989) - 704 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)989}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 990) - 709 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)990}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 991) - 714 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)991}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 1018) - 719 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1018}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR gprc:$Rx, 1019) - 724 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1019}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 1) - 729 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (MFSPR8 g8rc:$Rx, 3) - 731 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 4) - 736 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 5) - 741 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 8) - 746 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 9) - 751 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 13) - 756 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 17) - 761 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)17}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 18) - 766 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)18}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 19) - 771 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)19}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 22) - 776 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)22}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 25) - 781 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)25}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 26) - 786 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)26}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 27) - 791 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)27}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 28) - 796 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 29) - 801 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)29}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$RT, 280) - 806 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)280}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$RT, 287) - 811 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)287}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFSPR8 g8rc:$Rx, 512) - 816 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)512}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MFTB gprc:$Rx, 269) - 821 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)269}, + // (MFVRSAVE gprc:$rS) - 823 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (MFVSRD g8rc:$rA, f8rc:$src) - 824 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_F8RCRegClassID}, + // (MFVSRWZ gprc:$rA, f8rc:$src) - 826 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_F8RCRegClassID}, + // (MTCRF 255, gprc:$rA) - 828 + {AliasPatternCond_K_Imm, (uint32_t)255}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (MTCRF8 255, g8rc:$rA) - 830 + {AliasPatternCond_K_Imm, (uint32_t)255}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (MTDCR gprc:$Rx, 128) - 832 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)128}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTDCR gprc:$Rx, 129) - 837 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)129}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTDCR gprc:$Rx, 130) - 842 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)130}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTDCR gprc:$Rx, 131) - 847 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)131}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTDCR gprc:$Rx, 132) - 852 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)132}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTDCR gprc:$Rx, 133) - 857 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)133}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTDCR gprc:$Rx, 134) - 862 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)134}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTDCR gprc:$Rx, 135) - 867 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)135}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0) - 872 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, PPC_F8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MTFSFI u3imm:$BF, u4imm:$U, 0) - 876 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MTFSFI_rec u3imm:$BF, u4imm:$U, 0) - 879 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0) - 882 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, PPC_F8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MTMSR gprc:$RS, 0) - 886 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTMSRD gprc:$RS, 0) - 891 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 1, gprc:$Rx) - 896 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (MTSPR 3, gprc:$Rx) - 898 + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 8, gprc:$Rx) - 903 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 9, gprc:$Rx) - 908 + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 13, gprc:$Rx) - 913 + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 17, gprc:$Rx) - 918 + {AliasPatternCond_K_Imm, (uint32_t)17}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 18, gprc:$Rx) - 923 + {AliasPatternCond_K_Imm, (uint32_t)18}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 19, gprc:$Rx) - 928 + {AliasPatternCond_K_Imm, (uint32_t)19}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 22, gprc:$Rx) - 933 + {AliasPatternCond_K_Imm, (uint32_t)22}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 25, gprc:$Rx) - 938 + {AliasPatternCond_K_Imm, (uint32_t)25}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 26, gprc:$Rx) - 943 + {AliasPatternCond_K_Imm, (uint32_t)26}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 27, gprc:$Rx) - 948 + {AliasPatternCond_K_Imm, (uint32_t)27}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 28, gprc:$Rx) - 953 + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 29, gprc:$Rx) - 958 + {AliasPatternCond_K_Imm, (uint32_t)29}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 48, gprc:$Rx) - 963 + {AliasPatternCond_K_Imm, (uint32_t)48}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 280, gprc:$RT) - 968 + {AliasPatternCond_K_Imm, (uint32_t)280}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 284, gprc:$Rx) - 973 + {AliasPatternCond_K_Imm, (uint32_t)284}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 285, gprc:$Rx) - 978 + {AliasPatternCond_K_Imm, (uint32_t)285}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 512, gprc:$Rx) - 983 + {AliasPatternCond_K_Imm, (uint32_t)512}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 536, gprc:$Rx) - 988 + {AliasPatternCond_K_Imm, (uint32_t)536}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 537, gprc:$Rx) - 993 + {AliasPatternCond_K_Imm, (uint32_t)537}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 528, gprc:$Rx) - 998 + {AliasPatternCond_K_Imm, (uint32_t)528}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 529, gprc:$Rx) - 1003 + {AliasPatternCond_K_Imm, (uint32_t)529}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 538, gprc:$Rx) - 1008 + {AliasPatternCond_K_Imm, (uint32_t)538}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 539, gprc:$Rx) - 1013 + {AliasPatternCond_K_Imm, (uint32_t)539}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 530, gprc:$Rx) - 1018 + {AliasPatternCond_K_Imm, (uint32_t)530}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 531, gprc:$Rx) - 1023 + {AliasPatternCond_K_Imm, (uint32_t)531}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 540, gprc:$Rx) - 1028 + {AliasPatternCond_K_Imm, (uint32_t)540}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 541, gprc:$Rx) - 1033 + {AliasPatternCond_K_Imm, (uint32_t)541}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 532, gprc:$Rx) - 1038 + {AliasPatternCond_K_Imm, (uint32_t)532}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 533, gprc:$Rx) - 1043 + {AliasPatternCond_K_Imm, (uint32_t)533}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 542, gprc:$Rx) - 1048 + {AliasPatternCond_K_Imm, (uint32_t)542}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 543, gprc:$Rx) - 1053 + {AliasPatternCond_K_Imm, (uint32_t)543}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 534, gprc:$Rx) - 1058 + {AliasPatternCond_K_Imm, (uint32_t)534}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 535, gprc:$Rx) - 1063 + {AliasPatternCond_K_Imm, (uint32_t)535}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 896, gprc:$RT) - 1068 + {AliasPatternCond_K_Imm, (uint32_t)896}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 980, gprc:$Rx) - 1073 + {AliasPatternCond_K_Imm, (uint32_t)980}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 981, gprc:$Rx) - 1078 + {AliasPatternCond_K_Imm, (uint32_t)981}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 986, gprc:$Rx) - 1083 + {AliasPatternCond_K_Imm, (uint32_t)986}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 988, gprc:$Rx) - 1088 + {AliasPatternCond_K_Imm, (uint32_t)988}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 989, gprc:$Rx) - 1093 + {AliasPatternCond_K_Imm, (uint32_t)989}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 990, gprc:$Rx) - 1098 + {AliasPatternCond_K_Imm, (uint32_t)990}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 991, gprc:$Rx) - 1103 + {AliasPatternCond_K_Imm, (uint32_t)991}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 1018, gprc:$Rx) - 1108 + {AliasPatternCond_K_Imm, (uint32_t)1018}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR 1019, gprc:$Rx) - 1113 + {AliasPatternCond_K_Imm, (uint32_t)1019}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 1, g8rc:$Rx) - 1118 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (MTSPR8 3, g8rc:$Rx) - 1120 + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 8, g8rc:$Rx) - 1125 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 9, g8rc:$Rx) - 1130 + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 13, g8rc:$Rx) - 1135 + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 17, g8rc:$Rx) - 1140 + {AliasPatternCond_K_Imm, (uint32_t)17}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 18, g8rc:$Rx) - 1145 + {AliasPatternCond_K_Imm, (uint32_t)18}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 19, g8rc:$Rx) - 1150 + {AliasPatternCond_K_Imm, (uint32_t)19}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 22, g8rc:$Rx) - 1155 + {AliasPatternCond_K_Imm, (uint32_t)22}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 25, g8rc:$Rx) - 1160 + {AliasPatternCond_K_Imm, (uint32_t)25}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 26, g8rc:$Rx) - 1165 + {AliasPatternCond_K_Imm, (uint32_t)26}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 27, g8rc:$Rx) - 1170 + {AliasPatternCond_K_Imm, (uint32_t)27}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 28, g8rc:$Rx) - 1175 + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 29, g8rc:$Rx) - 1180 + {AliasPatternCond_K_Imm, (uint32_t)29}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 280, g8rc:$RT) - 1185 + {AliasPatternCond_K_Imm, (uint32_t)280}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 284, g8rc:$Rx) - 1190 + {AliasPatternCond_K_Imm, (uint32_t)284}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 285, g8rc:$Rx) - 1195 + {AliasPatternCond_K_Imm, (uint32_t)285}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTSPR8 512, g8rc:$Rx) - 1200 + {AliasPatternCond_K_Imm, (uint32_t)512}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (MTVRSAVE gprc:$rS) - 1205 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (MTVSRD f8rc:$dst, g8rc:$rA) - 1206 + {AliasPatternCond_K_RegClass, PPC_F8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (MTVSRWA f8rc:$dst, gprc:$rA) - 1208 + {AliasPatternCond_K_RegClass, PPC_F8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (MTVSRWZ f8rc:$dst, gprc:$rA) - 1210 + {AliasPatternCond_K_RegClass, PPC_F8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (NOR gprc:$rA, gprc:$rS, gprc:$rS) - 1212 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1215 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1218 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS) - 1221 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (OR gprc:$rA, gprc:$rB, gprc:$rB) - 1224 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1227 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1230 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (ORI R0, R0, 0) - 1233 + {AliasPatternCond_K_Reg, PPC_R0}, + {AliasPatternCond_K_Reg, PPC_R0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ORI8 X0, X0, 0) - 1236 + {AliasPatternCond_K_Reg, PPC_X0}, + {AliasPatternCond_K_Reg, PPC_X0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (OR_rec gprc:$rA, gprc:$rB, gprc:$rB) - 1239 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (RFEBB 1) - 1242 + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0) - 1243 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0) - 1247 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0) - 1251 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n) - 1255 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0) - 1258 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n) - 1262 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0) - 1265 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n) - 1269 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) - 1272 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) - 1277 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31) - 1282 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31) - 1287 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31) - 1292 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31) - 1297 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) - 1302 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) - 1307 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) - 1312 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31) - 1317 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31) - 1322 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) - 1327 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + // (SC 0) - 1332 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SUBF gprc:$rA, gprc:$rC, gprc:$rB) - 1333 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1336 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1339 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (SUBFC gprc:$rA, gprc:$rC, gprc:$rB) - 1342 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1345 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1348 + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB) - 1351 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB) - 1354 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (SYNC 0) - 1357 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (SYNC 1) - 1358 + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (SYNC 2) - 1359 + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (TD 16, g8rc:$rA, g8rc:$rB) - 1360 + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TD 4, g8rc:$rA, g8rc:$rB) - 1363 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TD 8, g8rc:$rA, g8rc:$rB) - 1366 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TD 24, g8rc:$rA, g8rc:$rB) - 1369 + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TD 2, g8rc:$rA, g8rc:$rB) - 1372 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TD 1, g8rc:$rA, g8rc:$rB) - 1375 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TD 31, g8rc:$rA, g8rc:$rB) - 1378 + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TDI 16, g8rc:$rA, s16imm:$imm) - 1381 + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TDI 4, g8rc:$rA, s16imm:$imm) - 1383 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TDI 8, g8rc:$rA, s16imm:$imm) - 1385 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TDI 24, g8rc:$rA, s16imm:$imm) - 1387 + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TDI 2, g8rc:$rA, s16imm:$imm) - 1389 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TDI 1, g8rc:$rA, s16imm:$imm) - 1391 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TDI 31, g8rc:$rA, s16imm:$imm) - 1393 + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_RegClass, PPC_G8RCRegClassID}, + // (TEND 0) - 1395 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TEND 1) - 1396 + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (TLBIE R0, gprc:$RB) - 1397 + {AliasPatternCond_K_Reg, PPC_R0}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TLBRE2 gprc:$RS, gprc:$A, 0) - 1399 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLBRE2 gprc:$RS, gprc:$A, 1) - 1402 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (TLBWE2 gprc:$RS, gprc:$A, 0) - 1405 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TLBWE2 gprc:$RS, gprc:$A, 1) - 1408 + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (TSR 0) - 1411 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TSR 1) - 1412 + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (TW 31, R0, R0) - 1413 + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Reg, PPC_R0}, + {AliasPatternCond_K_Reg, PPC_R0}, + // (TW 16, gprc:$rA, gprc:$rB) - 1416 + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TW 4, gprc:$rA, gprc:$rB) - 1419 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TW 8, gprc:$rA, gprc:$rB) - 1422 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TW 24, gprc:$rA, gprc:$rB) - 1425 + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TW 2, gprc:$rA, gprc:$rB) - 1428 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TW 1, gprc:$rA, gprc:$rB) - 1431 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TW 31, gprc:$rA, gprc:$rB) - 1434 + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TWI 16, gprc:$rA, s16imm:$imm) - 1437 + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TWI 4, gprc:$rA, s16imm:$imm) - 1439 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TWI 8, gprc:$rA, s16imm:$imm) - 1441 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TWI 24, gprc:$rA, s16imm:$imm) - 1443 + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TWI 2, gprc:$rA, s16imm:$imm) - 1445 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TWI 1, gprc:$rA, s16imm:$imm) - 1447 + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (TWI 31, gprc:$rA, s16imm:$imm) - 1449 + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_RegClass, PPC_GPRCRegClassID}, + // (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA) - 1451 + {AliasPatternCond_K_RegClass, PPC_VRRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VRRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA) - 1454 + {AliasPatternCond_K_RegClass, PPC_VRRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VRRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (WAIT 0) - 1457 + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (WAIT 1) - 1458 + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (WAIT 2) - 1459 + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (XORI R0, R0, 0) - 1460 + {AliasPatternCond_K_Reg, PPC_R0}, + {AliasPatternCond_K_Reg, PPC_R0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (XORI8 X0, X0, 0) - 1463 + {AliasPatternCond_K_Reg, PPC_X0}, + {AliasPatternCond_K_Reg, PPC_X0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB) - 1466 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB) - 1469 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0) - 1472 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3) - 1479 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0) - 1486 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3) - 1490 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2) - 1494 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0) - 1498 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSFRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3) - 1504 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSFRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_OrNegFeature, PPC_AIXOS}, + {AliasPatternCond_K_OrFeature, PPC_FeatureModernAIXAs}, + {AliasPatternCond_K_EndOrFeatures, 0}, + // (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2) - 1510 + {AliasPatternCond_K_RegClass, PPC_VSRCRegClassID}, + {AliasPatternCond_K_RegClass, PPC_VSFRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (gBC 12, crbitrc:$bi, condbrtarget:$dst) - 1513 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBC 4, crbitrc:$bi, condbrtarget:$dst) - 1515 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBC 14, crbitrc:$bi, condbrtarget:$dst) - 1517 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBC 6, crbitrc:$bi, condbrtarget:$dst) - 1519 + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBC 15, crbitrc:$bi, condbrtarget:$dst) - 1521 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBC 7, crbitrc:$bi, condbrtarget:$dst) - 1523 + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBC 8, crbitrc:$bi, condbrtarget:$dst) - 1525 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBC 0, crbitrc:$bi, condbrtarget:$dst) - 1527 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBC 10, crbitrc:$bi, condbrtarget:$dst) - 1529 + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBC 2, crbitrc:$bi, condbrtarget:$dst) - 1531 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 12, crbitrc:$bi, abscondbrtarget:$dst) - 1533 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 4, crbitrc:$bi, abscondbrtarget:$dst) - 1535 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 14, crbitrc:$bi, abscondbrtarget:$dst) - 1537 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 6, crbitrc:$bi, abscondbrtarget:$dst) - 1539 + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 15, crbitrc:$bi, abscondbrtarget:$dst) - 1541 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 7, crbitrc:$bi, abscondbrtarget:$dst) - 1543 + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 8, crbitrc:$bi, abscondbrtarget:$dst) - 1545 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 0, crbitrc:$bi, abscondbrtarget:$dst) - 1547 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 10, crbitrc:$bi, abscondbrtarget:$dst) - 1549 + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCA 2, crbitrc:$bi, abscondbrtarget:$dst) - 1551 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1553 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1556 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCCTR u5imm:$bo, crbitrc:$bi, 0) - 1559 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTR 12, crbitrc:$bi, 0) - 1562 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTR 4, crbitrc:$bi, 0) - 1565 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTR 14, crbitrc:$bi, 0) - 1568 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTR 6, crbitrc:$bi, 0) - 1571 + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTR 15, crbitrc:$bi, 0) - 1574 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTR 7, crbitrc:$bi, 0) - 1577 + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTRL u5imm:$bo, crbitrc:$bi, 0) - 1580 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTRL 12, crbitrc:$bi, 0) - 1583 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTRL 4, crbitrc:$bi, 0) - 1586 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTRL 14, crbitrc:$bi, 0) - 1589 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTRL 6, crbitrc:$bi, 0) - 1592 + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTRL 15, crbitrc:$bi, 0) - 1595 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCCTRL 7, crbitrc:$bi, 0) - 1598 + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCL 12, crbitrc:$bi, condbrtarget:$dst) - 1601 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCL 4, crbitrc:$bi, condbrtarget:$dst) - 1603 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCL 14, crbitrc:$bi, condbrtarget:$dst) - 1605 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCL 6, crbitrc:$bi, condbrtarget:$dst) - 1607 + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCL 15, crbitrc:$bi, condbrtarget:$dst) - 1609 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCL 7, crbitrc:$bi, condbrtarget:$dst) - 1611 + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCL 8, crbitrc:$bi, condbrtarget:$dst) - 1613 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCL 0, crbitrc:$bi, condbrtarget:$dst) - 1615 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCL 10, crbitrc:$bi, condbrtarget:$dst) - 1617 + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCL 2, crbitrc:$bi, condbrtarget:$dst) - 1619 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 12, crbitrc:$bi, abscondbrtarget:$dst) - 1621 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 4, crbitrc:$bi, abscondbrtarget:$dst) - 1623 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 14, crbitrc:$bi, abscondbrtarget:$dst) - 1625 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 6, crbitrc:$bi, abscondbrtarget:$dst) - 1627 + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 15, crbitrc:$bi, abscondbrtarget:$dst) - 1629 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 7, crbitrc:$bi, abscondbrtarget:$dst) - 1631 + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 8, crbitrc:$bi, abscondbrtarget:$dst) - 1633 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 0, crbitrc:$bi, abscondbrtarget:$dst) - 1635 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 10, crbitrc:$bi, abscondbrtarget:$dst) - 1637 + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLA 2, crbitrc:$bi, abscondbrtarget:$dst) - 1639 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1641 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1644 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLR u5imm:$bo, crbitrc:$bi, 0) - 1647 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 12, crbitrc:$bi, 0) - 1650 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 4, crbitrc:$bi, 0) - 1653 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 14, crbitrc:$bi, 0) - 1656 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 6, crbitrc:$bi, 0) - 1659 + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 15, crbitrc:$bi, 0) - 1662 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 7, crbitrc:$bi, 0) - 1665 + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 8, crbitrc:$bi, 0) - 1668 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 0, crbitrc:$bi, 0) - 1671 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 10, crbitrc:$bi, 0) - 1674 + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLR 2, crbitrc:$bi, 0) - 1677 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL u5imm:$bo, crbitrc:$bi, 0) - 1680 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 12, crbitrc:$bi, 0) - 1683 + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 4, crbitrc:$bi, 0) - 1686 + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 14, crbitrc:$bi, 0) - 1689 + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 6, crbitrc:$bi, 0) - 1692 + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 15, crbitrc:$bi, 0) - 1695 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 7, crbitrc:$bi, 0) - 1698 + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 8, crbitrc:$bi, 0) - 1701 + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 0, crbitrc:$bi, 0) - 1704 + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 10, crbitrc:$bi, 0) - 1707 + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLRL 2, crbitrc:$bi, 0) - 1710 + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (gBCLat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1713 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCLat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1716 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1719 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + // (gBCat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1722 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, PPC_CRBITRCRegClassID}, + }; + + static const char *AsmStrings[] = { + /* 0 */ "li $\x01, $\xFF\x03\x01\0" + /* 12 */ "lis $\x01, $\xFF\x03\x01\0" + /* 25 */ "lnia $\x01\0" + /* 33 */ "blt $\x02, $\xFF\x03\x02\0" + /* 46 */ "blt $\xFF\x03\x02\0" + /* 55 */ "blt- $\x02, $\xFF\x03\x02\0" + /* 69 */ "blt- $\xFF\x03\x02\0" + /* 79 */ "blt+ $\x02, $\xFF\x03\x02\0" + /* 93 */ "blt+ $\xFF\x03\x02\0" + /* 103 */ "bgt $\x02, $\xFF\x03\x02\0" + /* 116 */ "bgt $\xFF\x03\x02\0" + /* 125 */ "bgt- $\x02, $\xFF\x03\x02\0" + /* 139 */ "bgt- $\xFF\x03\x02\0" + /* 149 */ "bgt+ $\x02, $\xFF\x03\x02\0" + /* 163 */ "bgt+ $\xFF\x03\x02\0" + /* 173 */ "beq $\x02, $\xFF\x03\x02\0" + /* 186 */ "beq $\xFF\x03\x02\0" + /* 195 */ "beq- $\x02, $\xFF\x03\x02\0" + /* 209 */ "beq- $\xFF\x03\x02\0" + /* 219 */ "beq+ $\x02, $\xFF\x03\x02\0" + /* 233 */ "beq+ $\xFF\x03\x02\0" + /* 243 */ "bne $\x02, $\xFF\x03\x02\0" + /* 256 */ "bne $\xFF\x03\x02\0" + /* 265 */ "bne- $\x02, $\xFF\x03\x02\0" + /* 279 */ "bne- $\xFF\x03\x02\0" + /* 289 */ "bne+ $\x02, $\xFF\x03\x02\0" + /* 303 */ "bne+ $\xFF\x03\x02\0" + /* 313 */ "blta $\x02, $\xFF\x03\x03\0" + /* 327 */ "blta $\xFF\x03\x03\0" + /* 337 */ "blta- $\x02, $\xFF\x03\x03\0" + /* 352 */ "blta- $\xFF\x03\x03\0" + /* 363 */ "blta+ $\x02, $\xFF\x03\x03\0" + /* 378 */ "blta+ $\xFF\x03\x03\0" + /* 389 */ "bgta $\x02, $\xFF\x03\x03\0" + /* 403 */ "bgta $\xFF\x03\x03\0" + /* 413 */ "bgta- $\x02, $\xFF\x03\x03\0" + /* 428 */ "bgta- $\xFF\x03\x03\0" + /* 439 */ "bgta+ $\x02, $\xFF\x03\x03\0" + /* 454 */ "bgta+ $\xFF\x03\x03\0" + /* 465 */ "beqa $\x02, $\xFF\x03\x03\0" + /* 479 */ "beqa $\xFF\x03\x03\0" + /* 489 */ "beqa- $\x02, $\xFF\x03\x03\0" + /* 504 */ "beqa- $\xFF\x03\x03\0" + /* 515 */ "beqa+ $\x02, $\xFF\x03\x03\0" + /* 530 */ "beqa+ $\xFF\x03\x03\0" + /* 541 */ "bnea $\x02, $\xFF\x03\x03\0" + /* 555 */ "bnea $\xFF\x03\x03\0" + /* 565 */ "bnea- $\x02, $\xFF\x03\x03\0" + /* 580 */ "bnea- $\xFF\x03\x03\0" + /* 591 */ "bnea+ $\x02, $\xFF\x03\x03\0" + /* 606 */ "bnea+ $\xFF\x03\x03\0" + /* 617 */ "bltctr $\x02\0" + /* 627 */ "bltctr\0" + /* 634 */ "bltctr- $\x02\0" + /* 645 */ "bltctr-\0" + /* 653 */ "bltctr+ $\x02\0" + /* 664 */ "bltctr+\0" + /* 672 */ "bgtctr $\x02\0" + /* 682 */ "bgtctr\0" + /* 689 */ "bgtctr- $\x02\0" + /* 700 */ "bgtctr-\0" + /* 708 */ "bgtctr+ $\x02\0" + /* 719 */ "bgtctr+\0" + /* 727 */ "beqctr $\x02\0" + /* 737 */ "beqctr\0" + /* 744 */ "beqctr- $\x02\0" + /* 755 */ "beqctr-\0" + /* 763 */ "beqctr+ $\x02\0" + /* 774 */ "beqctr+\0" + /* 782 */ "bnectr $\x02\0" + /* 792 */ "bnectr\0" + /* 799 */ "bnectr- $\x02\0" + /* 810 */ "bnectr-\0" + /* 818 */ "bnectr+ $\x02\0" + /* 829 */ "bnectr+\0" + /* 837 */ "bltctrl $\x02\0" + /* 848 */ "bltctrl\0" + /* 856 */ "bltctrl- $\x02\0" + /* 868 */ "bltctrl-\0" + /* 877 */ "bltctrl+ $\x02\0" + /* 889 */ "bltctrl+\0" + /* 898 */ "bgtctrl $\x02\0" + /* 909 */ "bgtctrl\0" + /* 917 */ "bgtctrl- $\x02\0" + /* 929 */ "bgtctrl-\0" + /* 938 */ "bgtctrl+ $\x02\0" + /* 950 */ "bgtctrl+\0" + /* 959 */ "beqctrl $\x02\0" + /* 970 */ "beqctrl\0" + /* 978 */ "beqctrl- $\x02\0" + /* 990 */ "beqctrl-\0" + /* 999 */ "beqctrl+ $\x02\0" + /* 1011 */ "beqctrl+\0" + /* 1020 */ "bnectrl $\x02\0" + /* 1031 */ "bnectrl\0" + /* 1039 */ "bnectrl- $\x02\0" + /* 1051 */ "bnectrl-\0" + /* 1060 */ "bnectrl+ $\x02\0" + /* 1072 */ "bnectrl+\0" + /* 1081 */ "bltl $\x02, $\xFF\x03\x02\0" + /* 1095 */ "bltl $\xFF\x03\x02\0" + /* 1105 */ "bltl- $\x02, $\xFF\x03\x02\0" + /* 1120 */ "bltl- $\xFF\x03\x02\0" + /* 1131 */ "bltl+ $\x02, $\xFF\x03\x02\0" + /* 1146 */ "bltl+ $\xFF\x03\x02\0" + /* 1157 */ "bgtl $\x02, $\xFF\x03\x02\0" + /* 1171 */ "bgtl $\xFF\x03\x02\0" + /* 1181 */ "bgtl- $\x02, $\xFF\x03\x02\0" + /* 1196 */ "bgtl- $\xFF\x03\x02\0" + /* 1207 */ "bgtl+ $\x02, $\xFF\x03\x02\0" + /* 1222 */ "bgtl+ $\xFF\x03\x02\0" + /* 1233 */ "beql $\x02, $\xFF\x03\x02\0" + /* 1247 */ "beql $\xFF\x03\x02\0" + /* 1257 */ "beql- $\x02, $\xFF\x03\x02\0" + /* 1272 */ "beql- $\xFF\x03\x02\0" + /* 1283 */ "beql+ $\x02, $\xFF\x03\x02\0" + /* 1298 */ "beql+ $\xFF\x03\x02\0" + /* 1309 */ "bnel $\x02, $\xFF\x03\x02\0" + /* 1323 */ "bnel $\xFF\x03\x02\0" + /* 1333 */ "bnel- $\x02, $\xFF\x03\x02\0" + /* 1348 */ "bnel- $\xFF\x03\x02\0" + /* 1359 */ "bnel+ $\x02, $\xFF\x03\x02\0" + /* 1374 */ "bnel+ $\xFF\x03\x02\0" + /* 1385 */ "bltla $\x02, $\xFF\x03\x03\0" + /* 1400 */ "bltla $\xFF\x03\x03\0" + /* 1411 */ "bltla- $\x02, $\xFF\x03\x03\0" + /* 1427 */ "bltla- $\xFF\x03\x03\0" + /* 1439 */ "bltla+ $\x02, $\xFF\x03\x03\0" + /* 1455 */ "bltla+ $\xFF\x03\x03\0" + /* 1467 */ "bgtla $\x02, $\xFF\x03\x03\0" + /* 1482 */ "bgtla $\xFF\x03\x03\0" + /* 1493 */ "bgtla- $\x02, $\xFF\x03\x03\0" + /* 1509 */ "bgtla- $\xFF\x03\x03\0" + /* 1521 */ "bgtla+ $\x02, $\xFF\x03\x03\0" + /* 1537 */ "bgtla+ $\xFF\x03\x03\0" + /* 1549 */ "beqla $\x02, $\xFF\x03\x03\0" + /* 1564 */ "beqla $\xFF\x03\x03\0" + /* 1575 */ "beqla- $\x02, $\xFF\x03\x03\0" + /* 1591 */ "beqla- $\xFF\x03\x03\0" + /* 1603 */ "beqla+ $\x02, $\xFF\x03\x03\0" + /* 1619 */ "beqla+ $\xFF\x03\x03\0" + /* 1631 */ "bnela $\x02, $\xFF\x03\x03\0" + /* 1646 */ "bnela $\xFF\x03\x03\0" + /* 1657 */ "bnela- $\x02, $\xFF\x03\x03\0" + /* 1673 */ "bnela- $\xFF\x03\x03\0" + /* 1685 */ "bnela+ $\x02, $\xFF\x03\x03\0" + /* 1701 */ "bnela+ $\xFF\x03\x03\0" + /* 1713 */ "bltlr $\x02\0" + /* 1722 */ "bltlr\0" + /* 1728 */ "bltlr- $\x02\0" + /* 1738 */ "bltlr-\0" + /* 1745 */ "bltlr+ $\x02\0" + /* 1755 */ "bltlr+\0" + /* 1762 */ "bgtlr $\x02\0" + /* 1771 */ "bgtlr\0" + /* 1777 */ "bgtlr- $\x02\0" + /* 1787 */ "bgtlr-\0" + /* 1794 */ "bgtlr+ $\x02\0" + /* 1804 */ "bgtlr+\0" + /* 1811 */ "beqlr $\x02\0" + /* 1820 */ "beqlr\0" + /* 1826 */ "beqlr- $\x02\0" + /* 1836 */ "beqlr-\0" + /* 1843 */ "beqlr+ $\x02\0" + /* 1853 */ "beqlr+\0" + /* 1860 */ "bnelr $\x02\0" + /* 1869 */ "bnelr\0" + /* 1875 */ "bnelr- $\x02\0" + /* 1885 */ "bnelr-\0" + /* 1892 */ "bnelr+ $\x02\0" + /* 1902 */ "bnelr+\0" + /* 1909 */ "bltlrl $\x02\0" + /* 1919 */ "bltlrl\0" + /* 1926 */ "bltlrl- $\x02\0" + /* 1937 */ "bltlrl-\0" + /* 1945 */ "bltlrl+ $\x02\0" + /* 1956 */ "bltlrl+\0" + /* 1964 */ "bgtlrl $\x02\0" + /* 1974 */ "bgtlrl\0" + /* 1981 */ "bgtlrl- $\x02\0" + /* 1992 */ "bgtlrl-\0" + /* 2000 */ "bgtlrl+ $\x02\0" + /* 2011 */ "bgtlrl+\0" + /* 2019 */ "beqlrl $\x02\0" + /* 2029 */ "beqlrl\0" + /* 2036 */ "beqlrl- $\x02\0" + /* 2047 */ "beqlrl-\0" + /* 2055 */ "beqlrl+ $\x02\0" + /* 2066 */ "beqlrl+\0" + /* 2074 */ "bnelrl $\x02\0" + /* 2084 */ "bnelrl\0" + /* 2091 */ "bnelrl- $\x02\0" + /* 2102 */ "bnelrl-\0" + /* 2110 */ "bnelrl+ $\x02\0" + /* 2121 */ "bnelrl+\0" + /* 2129 */ "cmpd $\x02, $\x03\0" + /* 2141 */ "cmpdi $\x02, $\xFF\x03\x01\0" + /* 2156 */ "cmpld $\x02, $\x03\0" + /* 2169 */ "cmpldi $\x02, $\xFF\x03\x04\0" + /* 2185 */ "cmplw $\x02, $\x03\0" + /* 2198 */ "cmplwi $\x02, $\xFF\x03\x04\0" + /* 2214 */ "cmpw $\x02, $\x03\0" + /* 2226 */ "cmpwi $\x02, $\xFF\x03\x01\0" + /* 2241 */ "cntlzw $\x01, $\x02\0" + /* 2255 */ "cntlzw. $\x01, $\x02\0" + /* 2270 */ "paste. $\x01, $\x02\0" + /* 2284 */ "crset $\x01\0" + /* 2293 */ "crnot $\x01, $\x02\0" + /* 2306 */ "crmove $\x01, $\x02\0" + /* 2320 */ "crclr $\x01\0" + /* 2329 */ "isellt $\x01, $\x02, $\x03\0" + /* 2347 */ "iselgt $\x01, $\x02, $\x03\0" + /* 2365 */ "iseleq $\x01, $\x02, $\x03\0" + /* 2383 */ "mbar\0" + /* 2388 */ "mfbr0 $\x01\0" + /* 2397 */ "mfbr1 $\x01\0" + /* 2406 */ "mfbr2 $\x01\0" + /* 2415 */ "mfbr3 $\x01\0" + /* 2424 */ "mfbr4 $\x01\0" + /* 2433 */ "mfbr5 $\x01\0" + /* 2442 */ "mfbr6 $\x01\0" + /* 2451 */ "mfbr7 $\x01\0" + /* 2460 */ "mfxer $\x01\0" + /* 2469 */ "mfudscr $\x01\0" + /* 2480 */ "mfrtcu $\x01\0" + /* 2490 */ "mfrtcl $\x01\0" + /* 2500 */ "mflr $\x01\0" + /* 2508 */ "mfctr $\x01\0" + /* 2517 */ "mfuamr $\x01\0" + /* 2527 */ "mfdscr $\x01\0" + /* 2537 */ "mfdsisr $\x01\0" + /* 2548 */ "mfdar $\x01\0" + /* 2557 */ "mfdec $\x01\0" + /* 2566 */ "mfsdr1 $\x01\0" + /* 2576 */ "mfsrr0 $\x01\0" + /* 2586 */ "mfsrr1 $\x01\0" + /* 2596 */ "mfcfar $\x01\0" + /* 2606 */ "mfamr $\x01\0" + /* 2615 */ "mfpid $\x01\0" + /* 2624 */ "mfasr $\x01\0" + /* 2633 */ "mfpvr $\x01\0" + /* 2642 */ "mfspefscr $\x01\0" + /* 2655 */ "mfdbatu $\x01, 0\0" + /* 2669 */ "mfdbatl $\x01, 0\0" + /* 2683 */ "mfibatu $\x01, 0\0" + /* 2697 */ "mfibatl $\x01, 0\0" + /* 2711 */ "mfdbatu $\x01, 1\0" + /* 2725 */ "mfdbatl $\x01, 1\0" + /* 2739 */ "mfibatu $\x01, 1\0" + /* 2753 */ "mfibatl $\x01, 1\0" + /* 2767 */ "mfdbatu $\x01, 2\0" + /* 2781 */ "mfdbatl $\x01, 2\0" + /* 2795 */ "mfibatu $\x01, 2\0" + /* 2809 */ "mfibatl $\x01, 2\0" + /* 2823 */ "mfdbatu $\x01, 3\0" + /* 2837 */ "mfdbatl $\x01, 3\0" + /* 2851 */ "mfibatu $\x01, 3\0" + /* 2865 */ "mfibatl $\x01, 3\0" + /* 2879 */ "mfppr $\x01\0" + /* 2888 */ "mfesr $\x01\0" + /* 2897 */ "mfdear $\x01\0" + /* 2907 */ "mftcr $\x01\0" + /* 2916 */ "mftbhi $\x01\0" + /* 2926 */ "mftblo $\x01\0" + /* 2936 */ "mfsrr2 $\x01\0" + /* 2946 */ "mfsrr3 $\x01\0" + /* 2956 */ "mfdccr $\x01\0" + /* 2966 */ "mficcr $\x01\0" + /* 2976 */ "mftbu $\x01\0" + /* 2985 */ "mfvrsave $\x01\0" + /* 2997 */ "mffprd $\x01, $\x02\0" + /* 3011 */ "mffprwz $\x01, $\x02\0" + /* 3026 */ "mtcr $\x02\0" + /* 3034 */ "mtbr0 $\x01\0" + /* 3043 */ "mtbr1 $\x01\0" + /* 3052 */ "mtbr2 $\x01\0" + /* 3061 */ "mtbr3 $\x01\0" + /* 3070 */ "mtbr4 $\x01\0" + /* 3079 */ "mtbr5 $\x01\0" + /* 3088 */ "mtbr6 $\x01\0" + /* 3097 */ "mtbr7 $\x01\0" + /* 3106 */ "mtfsf $\x01, $\x02\0" + /* 3119 */ "mtfsfi $\xFF\x01\x05, $\xFF\x02\x06\0" + /* 3137 */ "mtfsfi. $\xFF\x01\x05, $\xFF\x02\x06\0" + /* 3156 */ "mtfsf. $\x01, $\x02\0" + /* 3170 */ "mtmsr $\x01\0" + /* 3179 */ "mtmsrd $\x01\0" + /* 3189 */ "mtxer $\x02\0" + /* 3198 */ "mtudscr $\x02\0" + /* 3209 */ "mtlr $\x02\0" + /* 3217 */ "mtctr $\x02\0" + /* 3226 */ "mtuamr $\x02\0" + /* 3236 */ "mtdscr $\x02\0" + /* 3246 */ "mtdsisr $\x02\0" + /* 3257 */ "mtdar $\x02\0" + /* 3266 */ "mtdec $\x02\0" + /* 3275 */ "mtsdr1 $\x02\0" + /* 3285 */ "mtsrr0 $\x02\0" + /* 3295 */ "mtsrr1 $\x02\0" + /* 3305 */ "mtcfar $\x02\0" + /* 3315 */ "mtamr $\x02\0" + /* 3324 */ "mtpid $\x02\0" + /* 3333 */ "mtasr $\x02\0" + /* 3342 */ "mttbl $\x02\0" + /* 3351 */ "mttbu $\x02\0" + /* 3360 */ "mtspefscr $\x02\0" + /* 3373 */ "mtdbatu 0, $\x02\0" + /* 3387 */ "mtdbatl 0, $\x02\0" + /* 3401 */ "mtibatu 0, $\x02\0" + /* 3415 */ "mtibatl 0, $\x02\0" + /* 3429 */ "mtdbatu 1, $\x02\0" + /* 3443 */ "mtdbatl 1, $\x02\0" + /* 3457 */ "mtibatu 1, $\x02\0" + /* 3471 */ "mtibatl 1, $\x02\0" + /* 3485 */ "mtdbatu 2, $\x02\0" + /* 3499 */ "mtdbatl 2, $\x02\0" + /* 3513 */ "mtibatu 2, $\x02\0" + /* 3527 */ "mtibatl 2, $\x02\0" + /* 3541 */ "mtdbatu 3, $\x02\0" + /* 3555 */ "mtdbatl 3, $\x02\0" + /* 3569 */ "mtibatu 3, $\x02\0" + /* 3583 */ "mtibatl 3, $\x02\0" + /* 3597 */ "mtppr $\x02\0" + /* 3606 */ "mtesr $\x02\0" + /* 3615 */ "mtdear $\x02\0" + /* 3625 */ "mttcr $\x02\0" + /* 3634 */ "mttbhi $\x02\0" + /* 3644 */ "mttblo $\x02\0" + /* 3654 */ "mtsrr2 $\x02\0" + /* 3664 */ "mtsrr3 $\x02\0" + /* 3674 */ "mtdccr $\x02\0" + /* 3684 */ "mticcr $\x02\0" + /* 3694 */ "mtvrsave $\x01\0" + /* 3706 */ "mtfprd $\x01, $\x02\0" + /* 3720 */ "mtfprwa $\x01, $\x02\0" + /* 3735 */ "mtfprwz $\x01, $\x02\0" + /* 3750 */ "not $\x01, $\x02\0" + /* 3761 */ "not. $\x01, $\x02\0" + /* 3773 */ "mr $\x01, $\x02\0" + /* 3783 */ "mr. $\x01, $\x02\0" + /* 3794 */ "nop\0" + /* 3798 */ "rfebb\0" + /* 3804 */ "rotld $\x01, $\x02, $\x03\0" + /* 3821 */ "rotld. $\x01, $\x02, $\x03\0" + /* 3839 */ "rotldi $\x01, $\x02, $\xFF\x03\x07\0" + /* 3859 */ "clrldi $\x01, $\x02, $\xFF\x04\x07\0" + /* 3879 */ "rotldi. $\x01, $\x02, $\xFF\x03\x07\0" + /* 3900 */ "clrldi. $\x01, $\x02, $\xFF\x04\x07\0" + /* 3921 */ "rotlwi $\x01, $\x02, $\xFF\x03\x08\0" + /* 3941 */ "clrlwi $\x01, $\x02, $\xFF\x04\x08\0" + /* 3961 */ "rotlwi. $\x01, $\x02, $\xFF\x03\x08\0" + /* 3982 */ "clrlwi. $\x01, $\x02, $\xFF\x04\x08\0" + /* 4003 */ "rotlw $\x01, $\x02, $\x03\0" + /* 4020 */ "rotlw. $\x01, $\x02, $\x03\0" + /* 4038 */ "sc\0" + /* 4041 */ "sub $\x01, $\x03, $\x02\0" + /* 4056 */ "sub. $\x01, $\x03, $\x02\0" + /* 4072 */ "subc $\x01, $\x03, $\x02\0" + /* 4088 */ "subc. $\x01, $\x03, $\x02\0" + /* 4105 */ "sync\0" + /* 4110 */ "lwsync\0" + /* 4117 */ "ptesync\0" + /* 4125 */ "tdlt $\x02, $\x03\0" + /* 4137 */ "tdeq $\x02, $\x03\0" + /* 4149 */ "tdgt $\x02, $\x03\0" + /* 4161 */ "tdne $\x02, $\x03\0" + /* 4173 */ "tdllt $\x02, $\x03\0" + /* 4186 */ "tdlgt $\x02, $\x03\0" + /* 4199 */ "tdu $\x02, $\x03\0" + /* 4210 */ "tdlti $\x02, $\xFF\x03\x01\0" + /* 4225 */ "tdeqi $\x02, $\xFF\x03\x01\0" + /* 4240 */ "tdgti $\x02, $\xFF\x03\x01\0" + /* 4255 */ "tdnei $\x02, $\xFF\x03\x01\0" + /* 4270 */ "tdllti $\x02, $\xFF\x03\x01\0" + /* 4286 */ "tdlgti $\x02, $\xFF\x03\x01\0" + /* 4302 */ "tdui $\x02, $\xFF\x03\x01\0" + /* 4316 */ "tend.\0" + /* 4322 */ "tendall.\0" + /* 4331 */ "tlbie $\x02\0" + /* 4340 */ "tlbrehi $\x01, $\x02\0" + /* 4355 */ "tlbrelo $\x01, $\x02\0" + /* 4370 */ "tlbwehi $\x01, $\x02\0" + /* 4385 */ "tlbwelo $\x01, $\x02\0" + /* 4400 */ "tsuspend.\0" + /* 4410 */ "tresume.\0" + /* 4419 */ "trap\0" + /* 4424 */ "twlt $\x02, $\x03\0" + /* 4436 */ "tweq $\x02, $\x03\0" + /* 4448 */ "twgt $\x02, $\x03\0" + /* 4460 */ "twne $\x02, $\x03\0" + /* 4472 */ "twllt $\x02, $\x03\0" + /* 4485 */ "twlgt $\x02, $\x03\0" + /* 4498 */ "twu $\x02, $\x03\0" + /* 4509 */ "twlti $\x02, $\xFF\x03\x01\0" + /* 4524 */ "tweqi $\x02, $\xFF\x03\x01\0" + /* 4539 */ "twgti $\x02, $\xFF\x03\x01\0" + /* 4554 */ "twnei $\x02, $\xFF\x03\x01\0" + /* 4569 */ "twllti $\x02, $\xFF\x03\x01\0" + /* 4585 */ "twlgti $\x02, $\xFF\x03\x01\0" + /* 4601 */ "twui $\x02, $\xFF\x03\x01\0" + /* 4615 */ "vnot $\x01, $\x02\0" + /* 4627 */ "vmr $\x01, $\x02\0" + /* 4638 */ "wait\0" + /* 4643 */ "waitrsv\0" + /* 4651 */ "waitimpl\0" + /* 4660 */ "xnop\0" + /* 4665 */ "xvmovdp $\x01, $\x02\0" + /* 4680 */ "xvmovsp $\x01, $\x02\0" + /* 4695 */ "xxspltd $\x01, $\x02, 0\0" + /* 4713 */ "xxspltd $\x01, $\x02, 1\0" + /* 4731 */ "xxmrghd $\x01, $\x02, $\x03\0" + /* 4750 */ "xxmrgld $\x01, $\x02, $\x03\0" + /* 4769 */ "xxswapd $\x01, $\x02\0" + /* 4784 */ "bt $\x02, $\xFF\x03\x02\0" + /* 4796 */ "bf $\x02, $\xFF\x03\x02\0" + /* 4808 */ "bt- $\x02, $\xFF\x03\x02\0" + /* 4821 */ "bf- $\x02, $\xFF\x03\x02\0" + /* 4834 */ "bt+ $\x02, $\xFF\x03\x02\0" + /* 4847 */ "bf+ $\x02, $\xFF\x03\x02\0" + /* 4860 */ "bdnzt $\x02, $\xFF\x03\x02\0" + /* 4875 */ "bdnzf $\x02, $\xFF\x03\x02\0" + /* 4890 */ "bdzt $\x02, $\xFF\x03\x02\0" + /* 4904 */ "bdzf $\x02, $\xFF\x03\x02\0" + /* 4918 */ "bta $\x02, $\xFF\x03\x03\0" + /* 4931 */ "bfa $\x02, $\xFF\x03\x03\0" + /* 4944 */ "bta- $\x02, $\xFF\x03\x03\0" + /* 4958 */ "bfa- $\x02, $\xFF\x03\x03\0" + /* 4972 */ "bta+ $\x02, $\xFF\x03\x03\0" + /* 4986 */ "bfa+ $\x02, $\xFF\x03\x03\0" + /* 5000 */ "bdnzta $\x02, $\xFF\x03\x03\0" + /* 5016 */ "bdnzfa $\x02, $\xFF\x03\x03\0" + /* 5032 */ "bdzta $\x02, $\xFF\x03\x03\0" + /* 5047 */ "bdzfa $\x02, $\xFF\x03\x03\0" + /* 5062 */ "bca+ $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" + /* 5082 */ "bca- $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" + /* 5102 */ "bcctr $\xFF\x01\x08, $\x02\0" + /* 5117 */ "btctr $\x02\0" + /* 5126 */ "bfctr $\x02\0" + /* 5135 */ "btctr- $\x02\0" + /* 5145 */ "bfctr- $\x02\0" + /* 5155 */ "btctr+ $\x02\0" + /* 5165 */ "bfctr+ $\x02\0" + /* 5175 */ "bcctrl $\xFF\x01\x08, $\x02\0" + /* 5191 */ "btctrl $\x02\0" + /* 5201 */ "bfctrl $\x02\0" + /* 5211 */ "btctrl- $\x02\0" + /* 5222 */ "bfctrl- $\x02\0" + /* 5233 */ "btctrl+ $\x02\0" + /* 5244 */ "bfctrl+ $\x02\0" + /* 5255 */ "btl $\x02, $\xFF\x03\x02\0" + /* 5268 */ "bfl $\x02, $\xFF\x03\x02\0" + /* 5281 */ "btl- $\x02, $\xFF\x03\x02\0" + /* 5295 */ "bfl- $\x02, $\xFF\x03\x02\0" + /* 5309 */ "btl+ $\x02, $\xFF\x03\x02\0" + /* 5323 */ "bfl+ $\x02, $\xFF\x03\x02\0" + /* 5337 */ "bdnztl $\x02, $\xFF\x03\x02\0" + /* 5353 */ "bdnzfl $\x02, $\xFF\x03\x02\0" + /* 5369 */ "bdztl $\x02, $\xFF\x03\x02\0" + /* 5384 */ "bdzfl $\x02, $\xFF\x03\x02\0" + /* 5399 */ "btla $\x02, $\xFF\x03\x03\0" + /* 5413 */ "bfla $\x02, $\xFF\x03\x03\0" + /* 5427 */ "btla- $\x02, $\xFF\x03\x03\0" + /* 5442 */ "bfla- $\x02, $\xFF\x03\x03\0" + /* 5457 */ "btla+ $\x02, $\xFF\x03\x03\0" + /* 5472 */ "bfla+ $\x02, $\xFF\x03\x03\0" + /* 5487 */ "bdnztla $\x02, $\xFF\x03\x03\0" + /* 5504 */ "bdnzfla $\x02, $\xFF\x03\x03\0" + /* 5521 */ "bdztla $\x02, $\xFF\x03\x03\0" + /* 5537 */ "bdzfla $\x02, $\xFF\x03\x03\0" + /* 5553 */ "bcla+ $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" + /* 5574 */ "bcla- $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" + /* 5595 */ "bclr $\xFF\x01\x08, $\x02\0" + /* 5609 */ "btlr $\x02\0" + /* 5617 */ "bflr $\x02\0" + /* 5625 */ "btlr- $\x02\0" + /* 5634 */ "bflr- $\x02\0" + /* 5643 */ "btlr+ $\x02\0" + /* 5652 */ "bflr+ $\x02\0" + /* 5661 */ "bdnztlr $\x02\0" + /* 5672 */ "bdnzflr $\x02\0" + /* 5683 */ "bdztlr $\x02\0" + /* 5693 */ "bdzflr $\x02\0" + /* 5703 */ "bclrl $\xFF\x01\x08, $\x02\0" + /* 5718 */ "btlrl $\x02\0" + /* 5727 */ "bflrl $\x02\0" + /* 5736 */ "btlrl- $\x02\0" + /* 5746 */ "bflrl- $\x02\0" + /* 5756 */ "btlrl+ $\x02\0" + /* 5766 */ "bflrl+ $\x02\0" + /* 5776 */ "bdnztlrl $\x02\0" + /* 5788 */ "bdnzflrl $\x02\0" + /* 5800 */ "bdztlrl $\x02\0" + /* 5811 */ "bdzflrl $\x02\0" + /* 5822 */ "bcl+ $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" + /* 5842 */ "bcl- $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" + /* 5862 */ "bc+ $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" + /* 5881 */ "bc- $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" + }; + + const char *AsmString = MCInstPrinter_matchAliasPatterns(MI, OpToPatterns, Patterns, Conds, AsmStrings, 119); + if (!AsmString) return false; + + char* tmpString = cs_strdup(AsmString); + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && + AsmString[I] != '$' && AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, "\t"); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, *(tmpString + (I++))); + } + } while (AsmString[I] != '\0'); + } + + return tmpString; +} + +void printCustomAliasOperand( + const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, + SStream *OS) { + switch (PrintMethodIdx) { + default: + llvm_unreachable("Unknown PrintMethod kind"); + break; +// printS16ImmOperand + case 0: + printS16ImmOperand(MI, OpIdx, OS); + break; +// printBranchOperand + case 1: + printBranchOperand(MI, OpIdx, OS); + break; +// printAbsBranchOperand + case 2: + printAbsBranchOperand(MI, OpIdx, OS); + break; +// printU16ImmOperand + case 3: + printU16ImmOperand(MI, OpIdx, OS); + break; +// printU3ImmOperand + case 4: + printU3ImmOperand(MI, OpIdx, OS); + break; +// printU4ImmOperand + case 5: + printU4ImmOperand(MI, OpIdx, OS); + break; +// printU6ImmOperand + case 6: + printU6ImmOperand(MI, OpIdx, OS); + break; +// printU5ImmOperand + case 7: + printU5ImmOperand(MI, OpIdx, OS); + break; + } +} + +#endif // PRINT_ALIAS_INSTR +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO/*0*/ }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO/*0*/ }, }; +static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<, 2013-2019 */ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +/*===- TableGen'erated file -------------------------------------*- C++ +-*-===*|* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| @@ -13,2162 +14,2162 @@ #undef GET_INSTRINFO_ENUM enum { - PPC_PHI = 0, - PPC_INLINEASM = 1, - PPC_CFI_INSTRUCTION = 2, - PPC_EH_LABEL = 3, - PPC_GC_LABEL = 4, - PPC_ANNOTATION_LABEL = 5, - PPC_KILL = 6, - PPC_EXTRACT_SUBREG = 7, - PPC_INSERT_SUBREG = 8, - PPC_IMPLICIT_DEF = 9, - PPC_SUBREG_TO_REG = 10, - PPC_COPY_TO_REGCLASS = 11, - PPC_DBG_VALUE = 12, - PPC_DBG_LABEL = 13, - PPC_REG_SEQUENCE = 14, - PPC_COPY = 15, - PPC_BUNDLE = 16, - PPC_LIFETIME_START = 17, - PPC_LIFETIME_END = 18, - PPC_STACKMAP = 19, - PPC_FENTRY_CALL = 20, - PPC_PATCHPOINT = 21, - PPC_LOAD_STACK_GUARD = 22, - PPC_STATEPOINT = 23, - PPC_LOCAL_ESCAPE = 24, - PPC_FAULTING_OP = 25, - PPC_PATCHABLE_OP = 26, - PPC_PATCHABLE_FUNCTION_ENTER = 27, - PPC_PATCHABLE_RET = 28, - PPC_PATCHABLE_FUNCTION_EXIT = 29, - PPC_PATCHABLE_TAIL_CALL = 30, - PPC_PATCHABLE_EVENT_CALL = 31, - PPC_PATCHABLE_TYPED_EVENT_CALL = 32, - PPC_ICALL_BRANCH_FUNNEL = 33, - PPC_G_ADD = 34, - PPC_G_SUB = 35, - PPC_G_MUL = 36, - PPC_G_SDIV = 37, - PPC_G_UDIV = 38, - PPC_G_SREM = 39, - PPC_G_UREM = 40, - PPC_G_AND = 41, - PPC_G_OR = 42, - PPC_G_XOR = 43, - PPC_G_IMPLICIT_DEF = 44, - PPC_G_PHI = 45, - PPC_G_FRAME_INDEX = 46, - PPC_G_GLOBAL_VALUE = 47, - PPC_G_EXTRACT = 48, - PPC_G_UNMERGE_VALUES = 49, - PPC_G_INSERT = 50, - PPC_G_MERGE_VALUES = 51, - PPC_G_PTRTOINT = 52, - PPC_G_INTTOPTR = 53, - PPC_G_BITCAST = 54, - PPC_G_LOAD = 55, - PPC_G_SEXTLOAD = 56, - PPC_G_ZEXTLOAD = 57, - PPC_G_STORE = 58, - PPC_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, - PPC_G_ATOMIC_CMPXCHG = 60, - PPC_G_ATOMICRMW_XCHG = 61, - PPC_G_ATOMICRMW_ADD = 62, - PPC_G_ATOMICRMW_SUB = 63, - PPC_G_ATOMICRMW_AND = 64, - PPC_G_ATOMICRMW_NAND = 65, - PPC_G_ATOMICRMW_OR = 66, - PPC_G_ATOMICRMW_XOR = 67, - PPC_G_ATOMICRMW_MAX = 68, - PPC_G_ATOMICRMW_MIN = 69, - PPC_G_ATOMICRMW_UMAX = 70, - PPC_G_ATOMICRMW_UMIN = 71, - PPC_G_BRCOND = 72, - PPC_G_BRINDIRECT = 73, - PPC_G_INTRINSIC = 74, - PPC_G_INTRINSIC_W_SIDE_EFFECTS = 75, - PPC_G_ANYEXT = 76, - PPC_G_TRUNC = 77, - PPC_G_CONSTANT = 78, - PPC_G_FCONSTANT = 79, - PPC_G_VASTART = 80, - PPC_G_VAARG = 81, - PPC_G_SEXT = 82, - PPC_G_ZEXT = 83, - PPC_G_SHL = 84, - PPC_G_LSHR = 85, - PPC_G_ASHR = 86, - PPC_G_ICMP = 87, - PPC_G_FCMP = 88, - PPC_G_SELECT = 89, - PPC_G_UADDE = 90, - PPC_G_USUBE = 91, - PPC_G_SADDO = 92, - PPC_G_SSUBO = 93, - PPC_G_UMULO = 94, - PPC_G_SMULO = 95, - PPC_G_UMULH = 96, - PPC_G_SMULH = 97, - PPC_G_FADD = 98, - PPC_G_FSUB = 99, - PPC_G_FMUL = 100, - PPC_G_FMA = 101, - PPC_G_FDIV = 102, - PPC_G_FREM = 103, - PPC_G_FPOW = 104, - PPC_G_FEXP = 105, - PPC_G_FEXP2 = 106, - PPC_G_FLOG = 107, - PPC_G_FLOG2 = 108, - PPC_G_FNEG = 109, - PPC_G_FPEXT = 110, - PPC_G_FPTRUNC = 111, - PPC_G_FPTOSI = 112, - PPC_G_FPTOUI = 113, - PPC_G_SITOFP = 114, - PPC_G_UITOFP = 115, - PPC_G_FABS = 116, - PPC_G_GEP = 117, - PPC_G_PTR_MASK = 118, - PPC_G_BR = 119, - PPC_G_INSERT_VECTOR_ELT = 120, - PPC_G_EXTRACT_VECTOR_ELT = 121, - PPC_G_SHUFFLE_VECTOR = 122, - PPC_G_BSWAP = 123, - PPC_G_ADDRSPACE_CAST = 124, - PPC_G_BLOCK_ADDR = 125, - PPC_CFENCE8 = 126, - PPC_CLRLSLDI = 127, - PPC_CLRLSLDIo = 128, - PPC_CLRLSLWI = 129, - PPC_CLRLSLWIo = 130, - PPC_CLRRDI = 131, - PPC_CLRRDIo = 132, - PPC_CLRRWI = 133, - PPC_CLRRWIo = 134, - PPC_CP_COPY_FIRST = 135, - PPC_CP_COPYx = 136, - PPC_CP_PASTE_LAST = 137, - PPC_CP_PASTEx = 138, - PPC_DCBFL = 139, - PPC_DCBFLP = 140, - PPC_DCBFx = 141, - PPC_DCBTCT = 142, - PPC_DCBTDS = 143, - PPC_DCBTSTCT = 144, - PPC_DCBTSTDS = 145, - PPC_DCBTSTT = 146, - PPC_DCBTSTx = 147, - PPC_DCBTT = 148, - PPC_DCBTx = 149, - PPC_DFLOADf32 = 150, - PPC_DFLOADf64 = 151, - PPC_DFSTOREf32 = 152, - PPC_DFSTOREf64 = 153, - PPC_EXTLDI = 154, - PPC_EXTLDIo = 155, - PPC_EXTLWI = 156, - PPC_EXTLWIo = 157, - PPC_EXTRDI = 158, - PPC_EXTRDIo = 159, - PPC_EXTRWI = 160, - PPC_EXTRWIo = 161, - PPC_INSLWI = 162, - PPC_INSLWIo = 163, - PPC_INSRDI = 164, - PPC_INSRDIo = 165, - PPC_INSRWI = 166, - PPC_INSRWIo = 167, - PPC_LAx = 168, - PPC_LIWAX = 169, - PPC_LIWZX = 170, - PPC_RLWIMIbm = 171, - PPC_RLWIMIobm = 172, - PPC_RLWINMbm = 173, - PPC_RLWINMobm = 174, - PPC_RLWNMbm = 175, - PPC_RLWNMobm = 176, - PPC_ROTRDI = 177, - PPC_ROTRDIo = 178, - PPC_ROTRWI = 179, - PPC_ROTRWIo = 180, - PPC_SLDI = 181, - PPC_SLDIo = 182, - PPC_SLWI = 183, - PPC_SLWIo = 184, - PPC_SPILLTOVSR_LD = 185, - PPC_SPILLTOVSR_LDX = 186, - PPC_SPILLTOVSR_ST = 187, - PPC_SPILLTOVSR_STX = 188, - PPC_SRDI = 189, - PPC_SRDIo = 190, - PPC_SRWI = 191, - PPC_SRWIo = 192, - PPC_STIWX = 193, - PPC_SUBI = 194, - PPC_SUBIC = 195, - PPC_SUBICo = 196, - PPC_SUBIS = 197, - PPC_SUBPCIS = 198, - PPC_XFLOADf32 = 199, - PPC_XFLOADf64 = 200, - PPC_XFSTOREf32 = 201, - PPC_XFSTOREf64 = 202, - PPC_ADD4 = 203, - PPC_ADD4TLS = 204, - PPC_ADD4o = 205, - PPC_ADD8 = 206, - PPC_ADD8TLS = 207, - PPC_ADD8TLS_ = 208, - PPC_ADD8o = 209, - PPC_ADDC = 210, - PPC_ADDC8 = 211, - PPC_ADDC8o = 212, - PPC_ADDCo = 213, - PPC_ADDE = 214, - PPC_ADDE8 = 215, - PPC_ADDE8o = 216, - PPC_ADDEo = 217, - PPC_ADDI = 218, - PPC_ADDI8 = 219, - PPC_ADDIC = 220, - PPC_ADDIC8 = 221, - PPC_ADDICo = 222, - PPC_ADDIS = 223, - PPC_ADDIS8 = 224, - PPC_ADDISdtprelHA = 225, - PPC_ADDISdtprelHA32 = 226, - PPC_ADDISgotTprelHA = 227, - PPC_ADDIStlsgdHA = 228, - PPC_ADDIStlsldHA = 229, - PPC_ADDIStocHA = 230, - PPC_ADDIdtprelL = 231, - PPC_ADDIdtprelL32 = 232, - PPC_ADDItlsgdL = 233, - PPC_ADDItlsgdL32 = 234, - PPC_ADDItlsgdLADDR = 235, - PPC_ADDItlsgdLADDR32 = 236, - PPC_ADDItlsldL = 237, - PPC_ADDItlsldL32 = 238, - PPC_ADDItlsldLADDR = 239, - PPC_ADDItlsldLADDR32 = 240, - PPC_ADDItocL = 241, - PPC_ADDME = 242, - PPC_ADDME8 = 243, - PPC_ADDME8o = 244, - PPC_ADDMEo = 245, - PPC_ADDPCIS = 246, - PPC_ADDZE = 247, - PPC_ADDZE8 = 248, - PPC_ADDZE8o = 249, - PPC_ADDZEo = 250, - PPC_ADJCALLSTACKDOWN = 251, - PPC_ADJCALLSTACKUP = 252, - PPC_AND = 253, - PPC_AND8 = 254, - PPC_AND8o = 255, - PPC_ANDC = 256, - PPC_ANDC8 = 257, - PPC_ANDC8o = 258, - PPC_ANDCo = 259, - PPC_ANDISo = 260, - PPC_ANDISo8 = 261, - PPC_ANDIo = 262, - PPC_ANDIo8 = 263, - PPC_ANDIo_1_EQ_BIT = 264, - PPC_ANDIo_1_EQ_BIT8 = 265, - PPC_ANDIo_1_GT_BIT = 266, - PPC_ANDIo_1_GT_BIT8 = 267, - PPC_ANDo = 268, - PPC_ATOMIC_CMP_SWAP_I16 = 269, - PPC_ATOMIC_CMP_SWAP_I32 = 270, - PPC_ATOMIC_CMP_SWAP_I64 = 271, - PPC_ATOMIC_CMP_SWAP_I8 = 272, - PPC_ATOMIC_LOAD_ADD_I16 = 273, - PPC_ATOMIC_LOAD_ADD_I32 = 274, - PPC_ATOMIC_LOAD_ADD_I64 = 275, - PPC_ATOMIC_LOAD_ADD_I8 = 276, - PPC_ATOMIC_LOAD_AND_I16 = 277, - PPC_ATOMIC_LOAD_AND_I32 = 278, - PPC_ATOMIC_LOAD_AND_I64 = 279, - PPC_ATOMIC_LOAD_AND_I8 = 280, - PPC_ATOMIC_LOAD_MAX_I16 = 281, - PPC_ATOMIC_LOAD_MAX_I32 = 282, - PPC_ATOMIC_LOAD_MAX_I64 = 283, - PPC_ATOMIC_LOAD_MAX_I8 = 284, - PPC_ATOMIC_LOAD_MIN_I16 = 285, - PPC_ATOMIC_LOAD_MIN_I32 = 286, - PPC_ATOMIC_LOAD_MIN_I64 = 287, - PPC_ATOMIC_LOAD_MIN_I8 = 288, - PPC_ATOMIC_LOAD_NAND_I16 = 289, - PPC_ATOMIC_LOAD_NAND_I32 = 290, - PPC_ATOMIC_LOAD_NAND_I64 = 291, - PPC_ATOMIC_LOAD_NAND_I8 = 292, - PPC_ATOMIC_LOAD_OR_I16 = 293, - PPC_ATOMIC_LOAD_OR_I32 = 294, - PPC_ATOMIC_LOAD_OR_I64 = 295, - PPC_ATOMIC_LOAD_OR_I8 = 296, - PPC_ATOMIC_LOAD_SUB_I16 = 297, - PPC_ATOMIC_LOAD_SUB_I32 = 298, - PPC_ATOMIC_LOAD_SUB_I64 = 299, - PPC_ATOMIC_LOAD_SUB_I8 = 300, - PPC_ATOMIC_LOAD_UMAX_I16 = 301, - PPC_ATOMIC_LOAD_UMAX_I32 = 302, - PPC_ATOMIC_LOAD_UMAX_I64 = 303, - PPC_ATOMIC_LOAD_UMAX_I8 = 304, - PPC_ATOMIC_LOAD_UMIN_I16 = 305, - PPC_ATOMIC_LOAD_UMIN_I32 = 306, - PPC_ATOMIC_LOAD_UMIN_I64 = 307, - PPC_ATOMIC_LOAD_UMIN_I8 = 308, - PPC_ATOMIC_LOAD_XOR_I16 = 309, - PPC_ATOMIC_LOAD_XOR_I32 = 310, - PPC_ATOMIC_LOAD_XOR_I64 = 311, - PPC_ATOMIC_LOAD_XOR_I8 = 312, - PPC_ATOMIC_SWAP_I16 = 313, - PPC_ATOMIC_SWAP_I32 = 314, - PPC_ATOMIC_SWAP_I64 = 315, - PPC_ATOMIC_SWAP_I8 = 316, - PPC_ATTN = 317, - PPC_B = 318, - PPC_BA = 319, - PPC_BC = 320, - PPC_BCC = 321, - PPC_BCCA = 322, - PPC_BCCCTR = 323, - PPC_BCCCTR8 = 324, - PPC_BCCCTRL = 325, - PPC_BCCCTRL8 = 326, - PPC_BCCL = 327, - PPC_BCCLA = 328, - PPC_BCCLR = 329, - PPC_BCCLRL = 330, - PPC_BCCTR = 331, - PPC_BCCTR8 = 332, - PPC_BCCTR8n = 333, - PPC_BCCTRL = 334, - PPC_BCCTRL8 = 335, - PPC_BCCTRL8n = 336, - PPC_BCCTRLn = 337, - PPC_BCCTRn = 338, - PPC_BCDCFNo = 339, - PPC_BCDCFSQo = 340, - PPC_BCDCFZo = 341, - PPC_BCDCPSGNo = 342, - PPC_BCDCTNo = 343, - PPC_BCDCTSQo = 344, - PPC_BCDCTZo = 345, - PPC_BCDSETSGNo = 346, - PPC_BCDSRo = 347, - PPC_BCDSo = 348, - PPC_BCDTRUNCo = 349, - PPC_BCDUSo = 350, - PPC_BCDUTRUNCo = 351, - PPC_BCL = 352, - PPC_BCLR = 353, - PPC_BCLRL = 354, - PPC_BCLRLn = 355, - PPC_BCLRn = 356, - PPC_BCLalways = 357, - PPC_BCLn = 358, - PPC_BCTR = 359, - PPC_BCTR8 = 360, - PPC_BCTRL = 361, - PPC_BCTRL8 = 362, - PPC_BCTRL8_LDinto_toc = 363, - PPC_BCn = 364, - PPC_BDNZ = 365, - PPC_BDNZ8 = 366, - PPC_BDNZA = 367, - PPC_BDNZAm = 368, - PPC_BDNZAp = 369, - PPC_BDNZL = 370, - PPC_BDNZLA = 371, - PPC_BDNZLAm = 372, - PPC_BDNZLAp = 373, - PPC_BDNZLR = 374, - PPC_BDNZLR8 = 375, - PPC_BDNZLRL = 376, - PPC_BDNZLRLm = 377, - PPC_BDNZLRLp = 378, - PPC_BDNZLRm = 379, - PPC_BDNZLRp = 380, - PPC_BDNZLm = 381, - PPC_BDNZLp = 382, - PPC_BDNZm = 383, - PPC_BDNZp = 384, - PPC_BDZ = 385, - PPC_BDZ8 = 386, - PPC_BDZA = 387, - PPC_BDZAm = 388, - PPC_BDZAp = 389, - PPC_BDZL = 390, - PPC_BDZLA = 391, - PPC_BDZLAm = 392, - PPC_BDZLAp = 393, - PPC_BDZLR = 394, - PPC_BDZLR8 = 395, - PPC_BDZLRL = 396, - PPC_BDZLRLm = 397, - PPC_BDZLRLp = 398, - PPC_BDZLRm = 399, - PPC_BDZLRp = 400, - PPC_BDZLm = 401, - PPC_BDZLp = 402, - PPC_BDZm = 403, - PPC_BDZp = 404, - PPC_BL = 405, - PPC_BL8 = 406, - PPC_BL8_NOP = 407, - PPC_BL8_NOP_TLS = 408, - PPC_BL8_TLS = 409, - PPC_BL8_TLS_ = 410, - PPC_BLA = 411, - PPC_BLA8 = 412, - PPC_BLA8_NOP = 413, - PPC_BLR = 414, - PPC_BLR8 = 415, - PPC_BLRL = 416, - PPC_BL_TLS = 417, - PPC_BPERMD = 418, - PPC_BRINC = 419, - PPC_CLRBHRB = 420, - PPC_CMPB = 421, - PPC_CMPB8 = 422, - PPC_CMPD = 423, - PPC_CMPDI = 424, - PPC_CMPEQB = 425, - PPC_CMPLD = 426, - PPC_CMPLDI = 427, - PPC_CMPLW = 428, - PPC_CMPLWI = 429, - PPC_CMPRB = 430, - PPC_CMPRB8 = 431, - PPC_CMPW = 432, - PPC_CMPWI = 433, - PPC_CNTLZD = 434, - PPC_CNTLZDo = 435, - PPC_CNTLZW = 436, - PPC_CNTLZW8 = 437, - PPC_CNTLZW8o = 438, - PPC_CNTLZWo = 439, - PPC_CNTTZD = 440, - PPC_CNTTZDo = 441, - PPC_CNTTZW = 442, - PPC_CNTTZW8 = 443, - PPC_CNTTZW8o = 444, - PPC_CNTTZWo = 445, - PPC_CP_ABORT = 446, - PPC_CP_COPY = 447, - PPC_CP_COPY8 = 448, - PPC_CP_PASTE = 449, - PPC_CP_PASTE8 = 450, - PPC_CP_PASTE8o = 451, - PPC_CP_PASTEo = 452, - PPC_CR6SET = 453, - PPC_CR6UNSET = 454, - PPC_CRAND = 455, - PPC_CRANDC = 456, - PPC_CREQV = 457, - PPC_CRNAND = 458, - PPC_CRNOR = 459, - PPC_CROR = 460, - PPC_CRORC = 461, - PPC_CRSET = 462, - PPC_CRUNSET = 463, - PPC_CRXOR = 464, - PPC_CTRL_DEP = 465, - PPC_DARN = 466, - PPC_DCBA = 467, - PPC_DCBF = 468, - PPC_DCBFEP = 469, - PPC_DCBI = 470, - PPC_DCBST = 471, - PPC_DCBSTEP = 472, - PPC_DCBT = 473, - PPC_DCBTEP = 474, - PPC_DCBTST = 475, - PPC_DCBTSTEP = 476, - PPC_DCBZ = 477, - PPC_DCBZEP = 478, - PPC_DCBZL = 479, - PPC_DCBZLEP = 480, - PPC_DCCCI = 481, - PPC_DIVD = 482, - PPC_DIVDE = 483, - PPC_DIVDEU = 484, - PPC_DIVDEUo = 485, - PPC_DIVDEo = 486, - PPC_DIVDU = 487, - PPC_DIVDUo = 488, - PPC_DIVDo = 489, - PPC_DIVW = 490, - PPC_DIVWE = 491, - PPC_DIVWEU = 492, - PPC_DIVWEUo = 493, - PPC_DIVWEo = 494, - PPC_DIVWU = 495, - PPC_DIVWUo = 496, - PPC_DIVWo = 497, - PPC_DSS = 498, - PPC_DSSALL = 499, - PPC_DST = 500, - PPC_DST64 = 501, - PPC_DSTST = 502, - PPC_DSTST64 = 503, - PPC_DSTSTT = 504, - PPC_DSTSTT64 = 505, - PPC_DSTT = 506, - PPC_DSTT64 = 507, - PPC_DYNALLOC = 508, - PPC_DYNALLOC8 = 509, - PPC_DYNAREAOFFSET = 510, - PPC_DYNAREAOFFSET8 = 511, - PPC_EFDABS = 512, - PPC_EFDADD = 513, - PPC_EFDCFS = 514, - PPC_EFDCFSF = 515, - PPC_EFDCFSI = 516, - PPC_EFDCFSID = 517, - PPC_EFDCFUF = 518, - PPC_EFDCFUI = 519, - PPC_EFDCFUID = 520, - PPC_EFDCMPEQ = 521, - PPC_EFDCMPGT = 522, - PPC_EFDCMPLT = 523, - PPC_EFDCTSF = 524, - PPC_EFDCTSI = 525, - PPC_EFDCTSIDZ = 526, - PPC_EFDCTSIZ = 527, - PPC_EFDCTUF = 528, - PPC_EFDCTUI = 529, - PPC_EFDCTUIDZ = 530, - PPC_EFDCTUIZ = 531, - PPC_EFDDIV = 532, - PPC_EFDMUL = 533, - PPC_EFDNABS = 534, - PPC_EFDNEG = 535, - PPC_EFDSUB = 536, - PPC_EFDTSTEQ = 537, - PPC_EFDTSTGT = 538, - PPC_EFDTSTLT = 539, - PPC_EFSABS = 540, - PPC_EFSADD = 541, - PPC_EFSCFD = 542, - PPC_EFSCFSF = 543, - PPC_EFSCFSI = 544, - PPC_EFSCFUF = 545, - PPC_EFSCFUI = 546, - PPC_EFSCMPEQ = 547, - PPC_EFSCMPGT = 548, - PPC_EFSCMPLT = 549, - PPC_EFSCTSF = 550, - PPC_EFSCTSI = 551, - PPC_EFSCTSIZ = 552, - PPC_EFSCTUF = 553, - PPC_EFSCTUI = 554, - PPC_EFSCTUIZ = 555, - PPC_EFSDIV = 556, - PPC_EFSMUL = 557, - PPC_EFSNABS = 558, - PPC_EFSNEG = 559, - PPC_EFSSUB = 560, - PPC_EFSTSTEQ = 561, - PPC_EFSTSTGT = 562, - PPC_EFSTSTLT = 563, - PPC_EH_SjLj_LongJmp32 = 564, - PPC_EH_SjLj_LongJmp64 = 565, - PPC_EH_SjLj_SetJmp32 = 566, - PPC_EH_SjLj_SetJmp64 = 567, - PPC_EH_SjLj_Setup = 568, - PPC_EQV = 569, - PPC_EQV8 = 570, - PPC_EQV8o = 571, - PPC_EQVo = 572, - PPC_EVABS = 573, - PPC_EVADDIW = 574, - PPC_EVADDSMIAAW = 575, - PPC_EVADDSSIAAW = 576, - PPC_EVADDUMIAAW = 577, - PPC_EVADDUSIAAW = 578, - PPC_EVADDW = 579, - PPC_EVAND = 580, - PPC_EVANDC = 581, - PPC_EVCMPEQ = 582, - PPC_EVCMPGTS = 583, - PPC_EVCMPGTU = 584, - PPC_EVCMPLTS = 585, - PPC_EVCMPLTU = 586, - PPC_EVCNTLSW = 587, - PPC_EVCNTLZW = 588, - PPC_EVDIVWS = 589, - PPC_EVDIVWU = 590, - PPC_EVEQV = 591, - PPC_EVEXTSB = 592, - PPC_EVEXTSH = 593, - PPC_EVFSABS = 594, - PPC_EVFSADD = 595, - PPC_EVFSCFSF = 596, - PPC_EVFSCFSI = 597, - PPC_EVFSCFUF = 598, - PPC_EVFSCFUI = 599, - PPC_EVFSCMPEQ = 600, - PPC_EVFSCMPGT = 601, - PPC_EVFSCMPLT = 602, - PPC_EVFSCTSF = 603, - PPC_EVFSCTSI = 604, - PPC_EVFSCTSIZ = 605, - PPC_EVFSCTUF = 606, - PPC_EVFSCTUI = 607, - PPC_EVFSCTUIZ = 608, - PPC_EVFSDIV = 609, - PPC_EVFSMUL = 610, - PPC_EVFSNABS = 611, - PPC_EVFSNEG = 612, - PPC_EVFSSUB = 613, - PPC_EVFSTSTEQ = 614, - PPC_EVFSTSTGT = 615, - PPC_EVFSTSTLT = 616, - PPC_EVLDD = 617, - PPC_EVLDDX = 618, - PPC_EVLDH = 619, - PPC_EVLDHX = 620, - PPC_EVLDW = 621, - PPC_EVLDWX = 622, - PPC_EVLHHESPLAT = 623, - PPC_EVLHHESPLATX = 624, - PPC_EVLHHOSSPLAT = 625, - PPC_EVLHHOSSPLATX = 626, - PPC_EVLHHOUSPLAT = 627, - PPC_EVLHHOUSPLATX = 628, - PPC_EVLWHE = 629, - PPC_EVLWHEX = 630, - PPC_EVLWHOS = 631, - PPC_EVLWHOSX = 632, - PPC_EVLWHOU = 633, - PPC_EVLWHOUX = 634, - PPC_EVLWHSPLAT = 635, - PPC_EVLWHSPLATX = 636, - PPC_EVLWWSPLAT = 637, - PPC_EVLWWSPLATX = 638, - PPC_EVMERGEHI = 639, - PPC_EVMERGEHILO = 640, - PPC_EVMERGELO = 641, - PPC_EVMERGELOHI = 642, - PPC_EVMHEGSMFAA = 643, - PPC_EVMHEGSMFAN = 644, - PPC_EVMHEGSMIAA = 645, - PPC_EVMHEGSMIAN = 646, - PPC_EVMHEGUMIAA = 647, - PPC_EVMHEGUMIAN = 648, - PPC_EVMHESMF = 649, - PPC_EVMHESMFA = 650, - PPC_EVMHESMFAAW = 651, - PPC_EVMHESMFANW = 652, - PPC_EVMHESMI = 653, - PPC_EVMHESMIA = 654, - PPC_EVMHESMIAAW = 655, - PPC_EVMHESMIANW = 656, - PPC_EVMHESSF = 657, - PPC_EVMHESSFA = 658, - PPC_EVMHESSFAAW = 659, - PPC_EVMHESSFANW = 660, - PPC_EVMHESSIAAW = 661, - PPC_EVMHESSIANW = 662, - PPC_EVMHEUMI = 663, - PPC_EVMHEUMIA = 664, - PPC_EVMHEUMIAAW = 665, - PPC_EVMHEUMIANW = 666, - PPC_EVMHEUSIAAW = 667, - PPC_EVMHEUSIANW = 668, - PPC_EVMHOGSMFAA = 669, - PPC_EVMHOGSMFAN = 670, - PPC_EVMHOGSMIAA = 671, - PPC_EVMHOGSMIAN = 672, - PPC_EVMHOGUMIAA = 673, - PPC_EVMHOGUMIAN = 674, - PPC_EVMHOSMF = 675, - PPC_EVMHOSMFA = 676, - PPC_EVMHOSMFAAW = 677, - PPC_EVMHOSMFANW = 678, - PPC_EVMHOSMI = 679, - PPC_EVMHOSMIA = 680, - PPC_EVMHOSMIAAW = 681, - PPC_EVMHOSMIANW = 682, - PPC_EVMHOSSF = 683, - PPC_EVMHOSSFA = 684, - PPC_EVMHOSSFAAW = 685, - PPC_EVMHOSSFANW = 686, - PPC_EVMHOSSIAAW = 687, - PPC_EVMHOSSIANW = 688, - PPC_EVMHOUMI = 689, - PPC_EVMHOUMIA = 690, - PPC_EVMHOUMIAAW = 691, - PPC_EVMHOUMIANW = 692, - PPC_EVMHOUSIAAW = 693, - PPC_EVMHOUSIANW = 694, - PPC_EVMRA = 695, - PPC_EVMWHSMF = 696, - PPC_EVMWHSMFA = 697, - PPC_EVMWHSMI = 698, - PPC_EVMWHSMIA = 699, - PPC_EVMWHSSF = 700, - PPC_EVMWHSSFA = 701, - PPC_EVMWHUMI = 702, - PPC_EVMWHUMIA = 703, - PPC_EVMWLSMIAAW = 704, - PPC_EVMWLSMIANW = 705, - PPC_EVMWLSSIAAW = 706, - PPC_EVMWLSSIANW = 707, - PPC_EVMWLUMI = 708, - PPC_EVMWLUMIA = 709, - PPC_EVMWLUMIAAW = 710, - PPC_EVMWLUMIANW = 711, - PPC_EVMWLUSIAAW = 712, - PPC_EVMWLUSIANW = 713, - PPC_EVMWSMF = 714, - PPC_EVMWSMFA = 715, - PPC_EVMWSMFAA = 716, - PPC_EVMWSMFAN = 717, - PPC_EVMWSMI = 718, - PPC_EVMWSMIA = 719, - PPC_EVMWSMIAA = 720, - PPC_EVMWSMIAN = 721, - PPC_EVMWSSF = 722, - PPC_EVMWSSFA = 723, - PPC_EVMWSSFAA = 724, - PPC_EVMWSSFAN = 725, - PPC_EVMWUMI = 726, - PPC_EVMWUMIA = 727, - PPC_EVMWUMIAA = 728, - PPC_EVMWUMIAN = 729, - PPC_EVNAND = 730, - PPC_EVNEG = 731, - PPC_EVNOR = 732, - PPC_EVOR = 733, - PPC_EVORC = 734, - PPC_EVRLW = 735, - PPC_EVRLWI = 736, - PPC_EVRNDW = 737, - PPC_EVSEL = 738, - PPC_EVSLW = 739, - PPC_EVSLWI = 740, - PPC_EVSPLATFI = 741, - PPC_EVSPLATI = 742, - PPC_EVSRWIS = 743, - PPC_EVSRWIU = 744, - PPC_EVSRWS = 745, - PPC_EVSRWU = 746, - PPC_EVSTDD = 747, - PPC_EVSTDDX = 748, - PPC_EVSTDH = 749, - PPC_EVSTDHX = 750, - PPC_EVSTDW = 751, - PPC_EVSTDWX = 752, - PPC_EVSTWHE = 753, - PPC_EVSTWHEX = 754, - PPC_EVSTWHO = 755, - PPC_EVSTWHOX = 756, - PPC_EVSTWWE = 757, - PPC_EVSTWWEX = 758, - PPC_EVSTWWO = 759, - PPC_EVSTWWOX = 760, - PPC_EVSUBFSMIAAW = 761, - PPC_EVSUBFSSIAAW = 762, - PPC_EVSUBFUMIAAW = 763, - PPC_EVSUBFUSIAAW = 764, - PPC_EVSUBFW = 765, - PPC_EVSUBIFW = 766, - PPC_EVXOR = 767, - PPC_EXTSB = 768, - PPC_EXTSB8 = 769, - PPC_EXTSB8_32_64 = 770, - PPC_EXTSB8o = 771, - PPC_EXTSBo = 772, - PPC_EXTSH = 773, - PPC_EXTSH8 = 774, - PPC_EXTSH8_32_64 = 775, - PPC_EXTSH8o = 776, - PPC_EXTSHo = 777, - PPC_EXTSW = 778, - PPC_EXTSWSLI = 779, - PPC_EXTSWSLIo = 780, - PPC_EXTSW_32 = 781, - PPC_EXTSW_32_64 = 782, - PPC_EXTSW_32_64o = 783, - PPC_EXTSWo = 784, - PPC_EnforceIEIO = 785, - PPC_FABSD = 786, - PPC_FABSDo = 787, - PPC_FABSS = 788, - PPC_FABSSo = 789, - PPC_FADD = 790, - PPC_FADDS = 791, - PPC_FADDSo = 792, - PPC_FADDo = 793, - PPC_FADDrtz = 794, - PPC_FCFID = 795, - PPC_FCFIDS = 796, - PPC_FCFIDSo = 797, - PPC_FCFIDU = 798, - PPC_FCFIDUS = 799, - PPC_FCFIDUSo = 800, - PPC_FCFIDUo = 801, - PPC_FCFIDo = 802, - PPC_FCMPUD = 803, - PPC_FCMPUS = 804, - PPC_FCPSGND = 805, - PPC_FCPSGNDo = 806, - PPC_FCPSGNS = 807, - PPC_FCPSGNSo = 808, - PPC_FCTID = 809, - PPC_FCTIDU = 810, - PPC_FCTIDUZ = 811, - PPC_FCTIDUZo = 812, - PPC_FCTIDUo = 813, - PPC_FCTIDZ = 814, - PPC_FCTIDZo = 815, - PPC_FCTIDo = 816, - PPC_FCTIW = 817, - PPC_FCTIWU = 818, - PPC_FCTIWUZ = 819, - PPC_FCTIWUZo = 820, - PPC_FCTIWUo = 821, - PPC_FCTIWZ = 822, - PPC_FCTIWZo = 823, - PPC_FCTIWo = 824, - PPC_FDIV = 825, - PPC_FDIVS = 826, - PPC_FDIVSo = 827, - PPC_FDIVo = 828, - PPC_FMADD = 829, - PPC_FMADDS = 830, - PPC_FMADDSo = 831, - PPC_FMADDo = 832, - PPC_FMR = 833, - PPC_FMRo = 834, - PPC_FMSUB = 835, - PPC_FMSUBS = 836, - PPC_FMSUBSo = 837, - PPC_FMSUBo = 838, - PPC_FMUL = 839, - PPC_FMULS = 840, - PPC_FMULSo = 841, - PPC_FMULo = 842, - PPC_FNABSD = 843, - PPC_FNABSDo = 844, - PPC_FNABSS = 845, - PPC_FNABSSo = 846, - PPC_FNEGD = 847, - PPC_FNEGDo = 848, - PPC_FNEGS = 849, - PPC_FNEGSo = 850, - PPC_FNMADD = 851, - PPC_FNMADDS = 852, - PPC_FNMADDSo = 853, - PPC_FNMADDo = 854, - PPC_FNMSUB = 855, - PPC_FNMSUBS = 856, - PPC_FNMSUBSo = 857, - PPC_FNMSUBo = 858, - PPC_FRE = 859, - PPC_FRES = 860, - PPC_FRESo = 861, - PPC_FREo = 862, - PPC_FRIMD = 863, - PPC_FRIMDo = 864, - PPC_FRIMS = 865, - PPC_FRIMSo = 866, - PPC_FRIND = 867, - PPC_FRINDo = 868, - PPC_FRINS = 869, - PPC_FRINSo = 870, - PPC_FRIPD = 871, - PPC_FRIPDo = 872, - PPC_FRIPS = 873, - PPC_FRIPSo = 874, - PPC_FRIZD = 875, - PPC_FRIZDo = 876, - PPC_FRIZS = 877, - PPC_FRIZSo = 878, - PPC_FRSP = 879, - PPC_FRSPo = 880, - PPC_FRSQRTE = 881, - PPC_FRSQRTES = 882, - PPC_FRSQRTESo = 883, - PPC_FRSQRTEo = 884, - PPC_FSELD = 885, - PPC_FSELDo = 886, - PPC_FSELS = 887, - PPC_FSELSo = 888, - PPC_FSQRT = 889, - PPC_FSQRTS = 890, - PPC_FSQRTSo = 891, - PPC_FSQRTo = 892, - PPC_FSUB = 893, - PPC_FSUBS = 894, - PPC_FSUBSo = 895, - PPC_FSUBo = 896, - PPC_FTDIV = 897, - PPC_FTSQRT = 898, - PPC_GETtlsADDR = 899, - PPC_GETtlsADDR32 = 900, - PPC_GETtlsldADDR = 901, - PPC_GETtlsldADDR32 = 902, - PPC_HRFID = 903, - PPC_ICBI = 904, - PPC_ICBIEP = 905, - PPC_ICBLC = 906, - PPC_ICBLQ = 907, - PPC_ICBT = 908, - PPC_ICBTLS = 909, - PPC_ICCCI = 910, - PPC_ISEL = 911, - PPC_ISEL8 = 912, - PPC_ISYNC = 913, - PPC_LA = 914, - PPC_LBARX = 915, - PPC_LBARXL = 916, - PPC_LBEPX = 917, - PPC_LBZ = 918, - PPC_LBZ8 = 919, - PPC_LBZCIX = 920, - PPC_LBZU = 921, - PPC_LBZU8 = 922, - PPC_LBZUX = 923, - PPC_LBZUX8 = 924, - PPC_LBZX = 925, - PPC_LBZX8 = 926, - PPC_LBZXTLS = 927, - PPC_LBZXTLS_ = 928, - PPC_LBZXTLS_32 = 929, - PPC_LD = 930, - PPC_LDARX = 931, - PPC_LDARXL = 932, - PPC_LDAT = 933, - PPC_LDBRX = 934, - PPC_LDCIX = 935, - PPC_LDMX = 936, - PPC_LDU = 937, - PPC_LDUX = 938, - PPC_LDX = 939, - PPC_LDXTLS = 940, - PPC_LDXTLS_ = 941, - PPC_LDgotTprelL = 942, - PPC_LDgotTprelL32 = 943, - PPC_LDtoc = 944, - PPC_LDtocBA = 945, - PPC_LDtocCPT = 946, - PPC_LDtocJTI = 947, - PPC_LDtocL = 948, - PPC_LFD = 949, - PPC_LFDEPX = 950, - PPC_LFDU = 951, - PPC_LFDUX = 952, - PPC_LFDX = 953, - PPC_LFIWAX = 954, - PPC_LFIWZX = 955, - PPC_LFS = 956, - PPC_LFSU = 957, - PPC_LFSUX = 958, - PPC_LFSX = 959, - PPC_LHA = 960, - PPC_LHA8 = 961, - PPC_LHARX = 962, - PPC_LHARXL = 963, - PPC_LHAU = 964, - PPC_LHAU8 = 965, - PPC_LHAUX = 966, - PPC_LHAUX8 = 967, - PPC_LHAX = 968, - PPC_LHAX8 = 969, - PPC_LHBRX = 970, - PPC_LHBRX8 = 971, - PPC_LHEPX = 972, - PPC_LHZ = 973, - PPC_LHZ8 = 974, - PPC_LHZCIX = 975, - PPC_LHZU = 976, - PPC_LHZU8 = 977, - PPC_LHZUX = 978, - PPC_LHZUX8 = 979, - PPC_LHZX = 980, - PPC_LHZX8 = 981, - PPC_LHZXTLS = 982, - PPC_LHZXTLS_ = 983, - PPC_LHZXTLS_32 = 984, - PPC_LI = 985, - PPC_LI8 = 986, - PPC_LIS = 987, - PPC_LIS8 = 988, - PPC_LMW = 989, - PPC_LSWI = 990, - PPC_LVEBX = 991, - PPC_LVEHX = 992, - PPC_LVEWX = 993, - PPC_LVSL = 994, - PPC_LVSR = 995, - PPC_LVX = 996, - PPC_LVXL = 997, - PPC_LWA = 998, - PPC_LWARX = 999, - PPC_LWARXL = 1000, - PPC_LWAT = 1001, - PPC_LWAUX = 1002, - PPC_LWAX = 1003, - PPC_LWAX_32 = 1004, - PPC_LWA_32 = 1005, - PPC_LWBRX = 1006, - PPC_LWBRX8 = 1007, - PPC_LWEPX = 1008, - PPC_LWZ = 1009, - PPC_LWZ8 = 1010, - PPC_LWZCIX = 1011, - PPC_LWZU = 1012, - PPC_LWZU8 = 1013, - PPC_LWZUX = 1014, - PPC_LWZUX8 = 1015, - PPC_LWZX = 1016, - PPC_LWZX8 = 1017, - PPC_LWZXTLS = 1018, - PPC_LWZXTLS_ = 1019, - PPC_LWZXTLS_32 = 1020, - PPC_LWZtoc = 1021, - PPC_LXSD = 1022, - PPC_LXSDX = 1023, - PPC_LXSIBZX = 1024, - PPC_LXSIHZX = 1025, - PPC_LXSIWAX = 1026, - PPC_LXSIWZX = 1027, - PPC_LXSSP = 1028, - PPC_LXSSPX = 1029, - PPC_LXV = 1030, - PPC_LXVB16X = 1031, - PPC_LXVD2X = 1032, - PPC_LXVDSX = 1033, - PPC_LXVH8X = 1034, - PPC_LXVL = 1035, - PPC_LXVLL = 1036, - PPC_LXVW4X = 1037, - PPC_LXVWSX = 1038, - PPC_LXVX = 1039, - PPC_MADDHD = 1040, - PPC_MADDHDU = 1041, - PPC_MADDLD = 1042, - PPC_MBAR = 1043, - PPC_MCRF = 1044, - PPC_MCRFS = 1045, - PPC_MCRXRX = 1046, - PPC_MFBHRBE = 1047, - PPC_MFCR = 1048, - PPC_MFCR8 = 1049, - PPC_MFCTR = 1050, - PPC_MFCTR8 = 1051, - PPC_MFDCR = 1052, - PPC_MFFS = 1053, - PPC_MFFSCDRN = 1054, - PPC_MFFSCDRNI = 1055, - PPC_MFFSCE = 1056, - PPC_MFFSCRN = 1057, - PPC_MFFSCRNI = 1058, - PPC_MFFSL = 1059, - PPC_MFFSo = 1060, - PPC_MFLR = 1061, - PPC_MFLR8 = 1062, - PPC_MFMSR = 1063, - PPC_MFOCRF = 1064, - PPC_MFOCRF8 = 1065, - PPC_MFPMR = 1066, - PPC_MFSPR = 1067, - PPC_MFSPR8 = 1068, - PPC_MFSR = 1069, - PPC_MFSRIN = 1070, - PPC_MFTB = 1071, - PPC_MFTB8 = 1072, - PPC_MFVRD = 1073, - PPC_MFVRSAVE = 1074, - PPC_MFVRSAVEv = 1075, - PPC_MFVSCR = 1076, - PPC_MFVSRD = 1077, - PPC_MFVSRLD = 1078, - PPC_MFVSRWZ = 1079, - PPC_MODSD = 1080, - PPC_MODSW = 1081, - PPC_MODUD = 1082, - PPC_MODUW = 1083, - PPC_MSGSYNC = 1084, - PPC_MSYNC = 1085, - PPC_MTCRF = 1086, - PPC_MTCRF8 = 1087, - PPC_MTCTR = 1088, - PPC_MTCTR8 = 1089, - PPC_MTCTR8loop = 1090, - PPC_MTCTRloop = 1091, - PPC_MTDCR = 1092, - PPC_MTFSB0 = 1093, - PPC_MTFSB1 = 1094, - PPC_MTFSF = 1095, - PPC_MTFSFI = 1096, - PPC_MTFSFIo = 1097, - PPC_MTFSFb = 1098, - PPC_MTFSFo = 1099, - PPC_MTLR = 1100, - PPC_MTLR8 = 1101, - PPC_MTMSR = 1102, - PPC_MTMSRD = 1103, - PPC_MTOCRF = 1104, - PPC_MTOCRF8 = 1105, - PPC_MTPMR = 1106, - PPC_MTSPR = 1107, - PPC_MTSPR8 = 1108, - PPC_MTSR = 1109, - PPC_MTSRIN = 1110, - PPC_MTVRSAVE = 1111, - PPC_MTVRSAVEv = 1112, - PPC_MTVSCR = 1113, - PPC_MTVSRD = 1114, - PPC_MTVSRDD = 1115, - PPC_MTVSRWA = 1116, - PPC_MTVSRWS = 1117, - PPC_MTVSRWZ = 1118, - PPC_MULHD = 1119, - PPC_MULHDU = 1120, - PPC_MULHDUo = 1121, - PPC_MULHDo = 1122, - PPC_MULHW = 1123, - PPC_MULHWU = 1124, - PPC_MULHWUo = 1125, - PPC_MULHWo = 1126, - PPC_MULLD = 1127, - PPC_MULLDo = 1128, - PPC_MULLI = 1129, - PPC_MULLI8 = 1130, - PPC_MULLW = 1131, - PPC_MULLWo = 1132, - PPC_MoveGOTtoLR = 1133, - PPC_MovePCtoLR = 1134, - PPC_MovePCtoLR8 = 1135, - PPC_NAND = 1136, - PPC_NAND8 = 1137, - PPC_NAND8o = 1138, - PPC_NANDo = 1139, - PPC_NAP = 1140, - PPC_NEG = 1141, - PPC_NEG8 = 1142, - PPC_NEG8o = 1143, - PPC_NEGo = 1144, - PPC_NOP = 1145, - PPC_NOP_GT_PWR6 = 1146, - PPC_NOP_GT_PWR7 = 1147, - PPC_NOR = 1148, - PPC_NOR8 = 1149, - PPC_NOR8o = 1150, - PPC_NORo = 1151, - PPC_OR = 1152, - PPC_OR8 = 1153, - PPC_OR8o = 1154, - PPC_ORC = 1155, - PPC_ORC8 = 1156, - PPC_ORC8o = 1157, - PPC_ORCo = 1158, - PPC_ORI = 1159, - PPC_ORI8 = 1160, - PPC_ORIS = 1161, - PPC_ORIS8 = 1162, - PPC_ORo = 1163, - PPC_POPCNTB = 1164, - PPC_POPCNTD = 1165, - PPC_POPCNTW = 1166, - PPC_PPC32GOT = 1167, - PPC_PPC32PICGOT = 1168, - PPC_QVALIGNI = 1169, - PPC_QVALIGNIb = 1170, - PPC_QVALIGNIs = 1171, - PPC_QVESPLATI = 1172, - PPC_QVESPLATIb = 1173, - PPC_QVESPLATIs = 1174, - PPC_QVFABS = 1175, - PPC_QVFABSs = 1176, - PPC_QVFADD = 1177, - PPC_QVFADDS = 1178, - PPC_QVFADDSs = 1179, - PPC_QVFCFID = 1180, - PPC_QVFCFIDS = 1181, - PPC_QVFCFIDU = 1182, - PPC_QVFCFIDUS = 1183, - PPC_QVFCFIDb = 1184, - PPC_QVFCMPEQ = 1185, - PPC_QVFCMPEQb = 1186, - PPC_QVFCMPEQbs = 1187, - PPC_QVFCMPGT = 1188, - PPC_QVFCMPGTb = 1189, - PPC_QVFCMPGTbs = 1190, - PPC_QVFCMPLT = 1191, - PPC_QVFCMPLTb = 1192, - PPC_QVFCMPLTbs = 1193, - PPC_QVFCPSGN = 1194, - PPC_QVFCPSGNs = 1195, - PPC_QVFCTID = 1196, - PPC_QVFCTIDU = 1197, - PPC_QVFCTIDUZ = 1198, - PPC_QVFCTIDZ = 1199, - PPC_QVFCTIDb = 1200, - PPC_QVFCTIW = 1201, - PPC_QVFCTIWU = 1202, - PPC_QVFCTIWUZ = 1203, - PPC_QVFCTIWZ = 1204, - PPC_QVFLOGICAL = 1205, - PPC_QVFLOGICALb = 1206, - PPC_QVFLOGICALs = 1207, - PPC_QVFMADD = 1208, - PPC_QVFMADDS = 1209, - PPC_QVFMADDSs = 1210, - PPC_QVFMR = 1211, - PPC_QVFMRb = 1212, - PPC_QVFMRs = 1213, - PPC_QVFMSUB = 1214, - PPC_QVFMSUBS = 1215, - PPC_QVFMSUBSs = 1216, - PPC_QVFMUL = 1217, - PPC_QVFMULS = 1218, - PPC_QVFMULSs = 1219, - PPC_QVFNABS = 1220, - PPC_QVFNABSs = 1221, - PPC_QVFNEG = 1222, - PPC_QVFNEGs = 1223, - PPC_QVFNMADD = 1224, - PPC_QVFNMADDS = 1225, - PPC_QVFNMADDSs = 1226, - PPC_QVFNMSUB = 1227, - PPC_QVFNMSUBS = 1228, - PPC_QVFNMSUBSs = 1229, - PPC_QVFPERM = 1230, - PPC_QVFPERMs = 1231, - PPC_QVFRE = 1232, - PPC_QVFRES = 1233, - PPC_QVFRESs = 1234, - PPC_QVFRIM = 1235, - PPC_QVFRIMs = 1236, - PPC_QVFRIN = 1237, - PPC_QVFRINs = 1238, - PPC_QVFRIP = 1239, - PPC_QVFRIPs = 1240, - PPC_QVFRIZ = 1241, - PPC_QVFRIZs = 1242, - PPC_QVFRSP = 1243, - PPC_QVFRSPs = 1244, - PPC_QVFRSQRTE = 1245, - PPC_QVFRSQRTES = 1246, - PPC_QVFRSQRTESs = 1247, - PPC_QVFSEL = 1248, - PPC_QVFSELb = 1249, - PPC_QVFSELbb = 1250, - PPC_QVFSELbs = 1251, - PPC_QVFSUB = 1252, - PPC_QVFSUBS = 1253, - PPC_QVFSUBSs = 1254, - PPC_QVFTSTNAN = 1255, - PPC_QVFTSTNANb = 1256, - PPC_QVFTSTNANbs = 1257, - PPC_QVFXMADD = 1258, - PPC_QVFXMADDS = 1259, - PPC_QVFXMUL = 1260, - PPC_QVFXMULS = 1261, - PPC_QVFXXCPNMADD = 1262, - PPC_QVFXXCPNMADDS = 1263, - PPC_QVFXXMADD = 1264, - PPC_QVFXXMADDS = 1265, - PPC_QVFXXNPMADD = 1266, - PPC_QVFXXNPMADDS = 1267, - PPC_QVGPCI = 1268, - PPC_QVLFCDUX = 1269, - PPC_QVLFCDUXA = 1270, - PPC_QVLFCDX = 1271, - PPC_QVLFCDXA = 1272, - PPC_QVLFCSUX = 1273, - PPC_QVLFCSUXA = 1274, - PPC_QVLFCSX = 1275, - PPC_QVLFCSXA = 1276, - PPC_QVLFCSXs = 1277, - PPC_QVLFDUX = 1278, - PPC_QVLFDUXA = 1279, - PPC_QVLFDX = 1280, - PPC_QVLFDXA = 1281, - PPC_QVLFDXb = 1282, - PPC_QVLFIWAX = 1283, - PPC_QVLFIWAXA = 1284, - PPC_QVLFIWZX = 1285, - PPC_QVLFIWZXA = 1286, - PPC_QVLFSUX = 1287, - PPC_QVLFSUXA = 1288, - PPC_QVLFSX = 1289, - PPC_QVLFSXA = 1290, - PPC_QVLFSXb = 1291, - PPC_QVLFSXs = 1292, - PPC_QVLPCLDX = 1293, - PPC_QVLPCLSX = 1294, - PPC_QVLPCLSXint = 1295, - PPC_QVLPCRDX = 1296, - PPC_QVLPCRSX = 1297, - PPC_QVSTFCDUX = 1298, - PPC_QVSTFCDUXA = 1299, - PPC_QVSTFCDUXI = 1300, - PPC_QVSTFCDUXIA = 1301, - PPC_QVSTFCDX = 1302, - PPC_QVSTFCDXA = 1303, - PPC_QVSTFCDXI = 1304, - PPC_QVSTFCDXIA = 1305, - PPC_QVSTFCSUX = 1306, - PPC_QVSTFCSUXA = 1307, - PPC_QVSTFCSUXI = 1308, - PPC_QVSTFCSUXIA = 1309, - PPC_QVSTFCSX = 1310, - PPC_QVSTFCSXA = 1311, - PPC_QVSTFCSXI = 1312, - PPC_QVSTFCSXIA = 1313, - PPC_QVSTFCSXs = 1314, - PPC_QVSTFDUX = 1315, - PPC_QVSTFDUXA = 1316, - PPC_QVSTFDUXI = 1317, - PPC_QVSTFDUXIA = 1318, - PPC_QVSTFDX = 1319, - PPC_QVSTFDXA = 1320, - PPC_QVSTFDXI = 1321, - PPC_QVSTFDXIA = 1322, - PPC_QVSTFDXb = 1323, - PPC_QVSTFIWX = 1324, - PPC_QVSTFIWXA = 1325, - PPC_QVSTFSUX = 1326, - PPC_QVSTFSUXA = 1327, - PPC_QVSTFSUXI = 1328, - PPC_QVSTFSUXIA = 1329, - PPC_QVSTFSUXs = 1330, - PPC_QVSTFSX = 1331, - PPC_QVSTFSXA = 1332, - PPC_QVSTFSXI = 1333, - PPC_QVSTFSXIA = 1334, - PPC_QVSTFSXs = 1335, - PPC_RESTORE_CR = 1336, - PPC_RESTORE_CRBIT = 1337, - PPC_RESTORE_VRSAVE = 1338, - PPC_RFCI = 1339, - PPC_RFDI = 1340, - PPC_RFEBB = 1341, - PPC_RFI = 1342, - PPC_RFID = 1343, - PPC_RFMCI = 1344, - PPC_RLDCL = 1345, - PPC_RLDCLo = 1346, - PPC_RLDCR = 1347, - PPC_RLDCRo = 1348, - PPC_RLDIC = 1349, - PPC_RLDICL = 1350, - PPC_RLDICL_32 = 1351, - PPC_RLDICL_32_64 = 1352, - PPC_RLDICL_32o = 1353, - PPC_RLDICLo = 1354, - PPC_RLDICR = 1355, - PPC_RLDICR_32 = 1356, - PPC_RLDICRo = 1357, - PPC_RLDICo = 1358, - PPC_RLDIMI = 1359, - PPC_RLDIMIo = 1360, - PPC_RLWIMI = 1361, - PPC_RLWIMI8 = 1362, - PPC_RLWIMI8o = 1363, - PPC_RLWIMIo = 1364, - PPC_RLWINM = 1365, - PPC_RLWINM8 = 1366, - PPC_RLWINM8o = 1367, - PPC_RLWINMo = 1368, - PPC_RLWNM = 1369, - PPC_RLWNM8 = 1370, - PPC_RLWNM8o = 1371, - PPC_RLWNMo = 1372, - PPC_ReadTB = 1373, - PPC_SC = 1374, - PPC_SELECT_CC_F16 = 1375, - PPC_SELECT_CC_F4 = 1376, - PPC_SELECT_CC_F8 = 1377, - PPC_SELECT_CC_I4 = 1378, - PPC_SELECT_CC_I8 = 1379, - PPC_SELECT_CC_QBRC = 1380, - PPC_SELECT_CC_QFRC = 1381, - PPC_SELECT_CC_QSRC = 1382, - PPC_SELECT_CC_SPE = 1383, - PPC_SELECT_CC_SPE4 = 1384, - PPC_SELECT_CC_VRRC = 1385, - PPC_SELECT_CC_VSFRC = 1386, - PPC_SELECT_CC_VSRC = 1387, - PPC_SELECT_CC_VSSRC = 1388, - PPC_SELECT_F16 = 1389, - PPC_SELECT_F4 = 1390, - PPC_SELECT_F8 = 1391, - PPC_SELECT_I4 = 1392, - PPC_SELECT_I8 = 1393, - PPC_SELECT_QBRC = 1394, - PPC_SELECT_QFRC = 1395, - PPC_SELECT_QSRC = 1396, - PPC_SELECT_SPE = 1397, - PPC_SELECT_SPE4 = 1398, - PPC_SELECT_VRRC = 1399, - PPC_SELECT_VSFRC = 1400, - PPC_SELECT_VSRC = 1401, - PPC_SELECT_VSSRC = 1402, - PPC_SETB = 1403, - PPC_SLBIA = 1404, - PPC_SLBIE = 1405, - PPC_SLBIEG = 1406, - PPC_SLBMFEE = 1407, - PPC_SLBMFEV = 1408, - PPC_SLBMTE = 1409, - PPC_SLBSYNC = 1410, - PPC_SLD = 1411, - PPC_SLDo = 1412, - PPC_SLW = 1413, - PPC_SLW8 = 1414, - PPC_SLW8o = 1415, - PPC_SLWo = 1416, - PPC_SPELWZ = 1417, - PPC_SPELWZX = 1418, - PPC_SPESTW = 1419, - PPC_SPESTWX = 1420, - PPC_SPILL_CR = 1421, - PPC_SPILL_CRBIT = 1422, - PPC_SPILL_VRSAVE = 1423, - PPC_SRAD = 1424, - PPC_SRADI = 1425, - PPC_SRADI_32 = 1426, - PPC_SRADIo = 1427, - PPC_SRADo = 1428, - PPC_SRAW = 1429, - PPC_SRAWI = 1430, - PPC_SRAWIo = 1431, - PPC_SRAWo = 1432, - PPC_SRD = 1433, - PPC_SRDo = 1434, - PPC_SRW = 1435, - PPC_SRW8 = 1436, - PPC_SRW8o = 1437, - PPC_SRWo = 1438, - PPC_STB = 1439, - PPC_STB8 = 1440, - PPC_STBCIX = 1441, - PPC_STBCX = 1442, - PPC_STBEPX = 1443, - PPC_STBU = 1444, - PPC_STBU8 = 1445, - PPC_STBUX = 1446, - PPC_STBUX8 = 1447, - PPC_STBX = 1448, - PPC_STBX8 = 1449, - PPC_STBXTLS = 1450, - PPC_STBXTLS_ = 1451, - PPC_STBXTLS_32 = 1452, - PPC_STD = 1453, - PPC_STDAT = 1454, - PPC_STDBRX = 1455, - PPC_STDCIX = 1456, - PPC_STDCX = 1457, - PPC_STDU = 1458, - PPC_STDUX = 1459, - PPC_STDX = 1460, - PPC_STDXTLS = 1461, - PPC_STDXTLS_ = 1462, - PPC_STFD = 1463, - PPC_STFDEPX = 1464, - PPC_STFDU = 1465, - PPC_STFDUX = 1466, - PPC_STFDX = 1467, - PPC_STFIWX = 1468, - PPC_STFS = 1469, - PPC_STFSU = 1470, - PPC_STFSUX = 1471, - PPC_STFSX = 1472, - PPC_STH = 1473, - PPC_STH8 = 1474, - PPC_STHBRX = 1475, - PPC_STHCIX = 1476, - PPC_STHCX = 1477, - PPC_STHEPX = 1478, - PPC_STHU = 1479, - PPC_STHU8 = 1480, - PPC_STHUX = 1481, - PPC_STHUX8 = 1482, - PPC_STHX = 1483, - PPC_STHX8 = 1484, - PPC_STHXTLS = 1485, - PPC_STHXTLS_ = 1486, - PPC_STHXTLS_32 = 1487, - PPC_STMW = 1488, - PPC_STOP = 1489, - PPC_STSWI = 1490, - PPC_STVEBX = 1491, - PPC_STVEHX = 1492, - PPC_STVEWX = 1493, - PPC_STVX = 1494, - PPC_STVXL = 1495, - PPC_STW = 1496, - PPC_STW8 = 1497, - PPC_STWAT = 1498, - PPC_STWBRX = 1499, - PPC_STWCIX = 1500, - PPC_STWCX = 1501, - PPC_STWEPX = 1502, - PPC_STWU = 1503, - PPC_STWU8 = 1504, - PPC_STWUX = 1505, - PPC_STWUX8 = 1506, - PPC_STWX = 1507, - PPC_STWX8 = 1508, - PPC_STWXTLS = 1509, - PPC_STWXTLS_ = 1510, - PPC_STWXTLS_32 = 1511, - PPC_STXSD = 1512, - PPC_STXSDX = 1513, - PPC_STXSIBX = 1514, - PPC_STXSIBXv = 1515, - PPC_STXSIHX = 1516, - PPC_STXSIHXv = 1517, - PPC_STXSIWX = 1518, - PPC_STXSSP = 1519, - PPC_STXSSPX = 1520, - PPC_STXV = 1521, - PPC_STXVB16X = 1522, - PPC_STXVD2X = 1523, - PPC_STXVH8X = 1524, - PPC_STXVL = 1525, - PPC_STXVLL = 1526, - PPC_STXVW4X = 1527, - PPC_STXVX = 1528, - PPC_SUBF = 1529, - PPC_SUBF8 = 1530, - PPC_SUBF8o = 1531, - PPC_SUBFC = 1532, - PPC_SUBFC8 = 1533, - PPC_SUBFC8o = 1534, - PPC_SUBFCo = 1535, - PPC_SUBFE = 1536, - PPC_SUBFE8 = 1537, - PPC_SUBFE8o = 1538, - PPC_SUBFEo = 1539, - PPC_SUBFIC = 1540, - PPC_SUBFIC8 = 1541, - PPC_SUBFME = 1542, - PPC_SUBFME8 = 1543, - PPC_SUBFME8o = 1544, - PPC_SUBFMEo = 1545, - PPC_SUBFZE = 1546, - PPC_SUBFZE8 = 1547, - PPC_SUBFZE8o = 1548, - PPC_SUBFZEo = 1549, - PPC_SUBFo = 1550, - PPC_SYNC = 1551, - PPC_TABORT = 1552, - PPC_TABORTDC = 1553, - PPC_TABORTDCI = 1554, - PPC_TABORTWC = 1555, - PPC_TABORTWCI = 1556, - PPC_TAILB = 1557, - PPC_TAILB8 = 1558, - PPC_TAILBA = 1559, - PPC_TAILBA8 = 1560, - PPC_TAILBCTR = 1561, - PPC_TAILBCTR8 = 1562, - PPC_TBEGIN = 1563, - PPC_TCHECK = 1564, - PPC_TCHECK_RET = 1565, - PPC_TCRETURNai = 1566, - PPC_TCRETURNai8 = 1567, - PPC_TCRETURNdi = 1568, - PPC_TCRETURNdi8 = 1569, - PPC_TCRETURNri = 1570, - PPC_TCRETURNri8 = 1571, - PPC_TD = 1572, - PPC_TDI = 1573, - PPC_TEND = 1574, - PPC_TLBIA = 1575, - PPC_TLBIE = 1576, - PPC_TLBIEL = 1577, - PPC_TLBIVAX = 1578, - PPC_TLBLD = 1579, - PPC_TLBLI = 1580, - PPC_TLBRE = 1581, - PPC_TLBRE2 = 1582, - PPC_TLBSX = 1583, - PPC_TLBSX2 = 1584, - PPC_TLBSX2D = 1585, - PPC_TLBSYNC = 1586, - PPC_TLBWE = 1587, - PPC_TLBWE2 = 1588, - PPC_TRAP = 1589, - PPC_TRECHKPT = 1590, - PPC_TRECLAIM = 1591, - PPC_TSR = 1592, - PPC_TW = 1593, - PPC_TWI = 1594, - PPC_UPDATE_VRSAVE = 1595, - PPC_UpdateGBR = 1596, - PPC_VABSDUB = 1597, - PPC_VABSDUH = 1598, - PPC_VABSDUW = 1599, - PPC_VADDCUQ = 1600, - PPC_VADDCUW = 1601, - PPC_VADDECUQ = 1602, - PPC_VADDEUQM = 1603, - PPC_VADDFP = 1604, - PPC_VADDSBS = 1605, - PPC_VADDSHS = 1606, - PPC_VADDSWS = 1607, - PPC_VADDUBM = 1608, - PPC_VADDUBS = 1609, - PPC_VADDUDM = 1610, - PPC_VADDUHM = 1611, - PPC_VADDUHS = 1612, - PPC_VADDUQM = 1613, - PPC_VADDUWM = 1614, - PPC_VADDUWS = 1615, - PPC_VAND = 1616, - PPC_VANDC = 1617, - PPC_VAVGSB = 1618, - PPC_VAVGSH = 1619, - PPC_VAVGSW = 1620, - PPC_VAVGUB = 1621, - PPC_VAVGUH = 1622, - PPC_VAVGUW = 1623, - PPC_VBPERMD = 1624, - PPC_VBPERMQ = 1625, - PPC_VCFSX = 1626, - PPC_VCFSX_0 = 1627, - PPC_VCFUX = 1628, - PPC_VCFUX_0 = 1629, - PPC_VCIPHER = 1630, - PPC_VCIPHERLAST = 1631, - PPC_VCLZB = 1632, - PPC_VCLZD = 1633, - PPC_VCLZH = 1634, - PPC_VCLZLSBB = 1635, - PPC_VCLZW = 1636, - PPC_VCMPBFP = 1637, - PPC_VCMPBFPo = 1638, - PPC_VCMPEQFP = 1639, - PPC_VCMPEQFPo = 1640, - PPC_VCMPEQUB = 1641, - PPC_VCMPEQUBo = 1642, - PPC_VCMPEQUD = 1643, - PPC_VCMPEQUDo = 1644, - PPC_VCMPEQUH = 1645, - PPC_VCMPEQUHo = 1646, - PPC_VCMPEQUW = 1647, - PPC_VCMPEQUWo = 1648, - PPC_VCMPGEFP = 1649, - PPC_VCMPGEFPo = 1650, - PPC_VCMPGTFP = 1651, - PPC_VCMPGTFPo = 1652, - PPC_VCMPGTSB = 1653, - PPC_VCMPGTSBo = 1654, - PPC_VCMPGTSD = 1655, - PPC_VCMPGTSDo = 1656, - PPC_VCMPGTSH = 1657, - PPC_VCMPGTSHo = 1658, - PPC_VCMPGTSW = 1659, - PPC_VCMPGTSWo = 1660, - PPC_VCMPGTUB = 1661, - PPC_VCMPGTUBo = 1662, - PPC_VCMPGTUD = 1663, - PPC_VCMPGTUDo = 1664, - PPC_VCMPGTUH = 1665, - PPC_VCMPGTUHo = 1666, - PPC_VCMPGTUW = 1667, - PPC_VCMPGTUWo = 1668, - PPC_VCMPNEB = 1669, - PPC_VCMPNEBo = 1670, - PPC_VCMPNEH = 1671, - PPC_VCMPNEHo = 1672, - PPC_VCMPNEW = 1673, - PPC_VCMPNEWo = 1674, - PPC_VCMPNEZB = 1675, - PPC_VCMPNEZBo = 1676, - PPC_VCMPNEZH = 1677, - PPC_VCMPNEZHo = 1678, - PPC_VCMPNEZW = 1679, - PPC_VCMPNEZWo = 1680, - PPC_VCTSXS = 1681, - PPC_VCTSXS_0 = 1682, - PPC_VCTUXS = 1683, - PPC_VCTUXS_0 = 1684, - PPC_VCTZB = 1685, - PPC_VCTZD = 1686, - PPC_VCTZH = 1687, - PPC_VCTZLSBB = 1688, - PPC_VCTZW = 1689, - PPC_VEQV = 1690, - PPC_VEXPTEFP = 1691, - PPC_VEXTRACTD = 1692, - PPC_VEXTRACTUB = 1693, - PPC_VEXTRACTUH = 1694, - PPC_VEXTRACTUW = 1695, - PPC_VEXTSB2D = 1696, - PPC_VEXTSB2Ds = 1697, - PPC_VEXTSB2W = 1698, - PPC_VEXTSB2Ws = 1699, - PPC_VEXTSH2D = 1700, - PPC_VEXTSH2Ds = 1701, - PPC_VEXTSH2W = 1702, - PPC_VEXTSH2Ws = 1703, - PPC_VEXTSW2D = 1704, - PPC_VEXTSW2Ds = 1705, - PPC_VEXTUBLX = 1706, - PPC_VEXTUBRX = 1707, - PPC_VEXTUHLX = 1708, - PPC_VEXTUHRX = 1709, - PPC_VEXTUWLX = 1710, - PPC_VEXTUWRX = 1711, - PPC_VGBBD = 1712, - PPC_VINSERTB = 1713, - PPC_VINSERTD = 1714, - PPC_VINSERTH = 1715, - PPC_VINSERTW = 1716, - PPC_VLOGEFP = 1717, - PPC_VMADDFP = 1718, - PPC_VMAXFP = 1719, - PPC_VMAXSB = 1720, - PPC_VMAXSD = 1721, - PPC_VMAXSH = 1722, - PPC_VMAXSW = 1723, - PPC_VMAXUB = 1724, - PPC_VMAXUD = 1725, - PPC_VMAXUH = 1726, - PPC_VMAXUW = 1727, - PPC_VMHADDSHS = 1728, - PPC_VMHRADDSHS = 1729, - PPC_VMINFP = 1730, - PPC_VMINSB = 1731, - PPC_VMINSD = 1732, - PPC_VMINSH = 1733, - PPC_VMINSW = 1734, - PPC_VMINUB = 1735, - PPC_VMINUD = 1736, - PPC_VMINUH = 1737, - PPC_VMINUW = 1738, - PPC_VMLADDUHM = 1739, - PPC_VMRGEW = 1740, - PPC_VMRGHB = 1741, - PPC_VMRGHH = 1742, - PPC_VMRGHW = 1743, - PPC_VMRGLB = 1744, - PPC_VMRGLH = 1745, - PPC_VMRGLW = 1746, - PPC_VMRGOW = 1747, - PPC_VMSUMMBM = 1748, - PPC_VMSUMSHM = 1749, - PPC_VMSUMSHS = 1750, - PPC_VMSUMUBM = 1751, - PPC_VMSUMUHM = 1752, - PPC_VMSUMUHS = 1753, - PPC_VMUL10CUQ = 1754, - PPC_VMUL10ECUQ = 1755, - PPC_VMUL10EUQ = 1756, - PPC_VMUL10UQ = 1757, - PPC_VMULESB = 1758, - PPC_VMULESH = 1759, - PPC_VMULESW = 1760, - PPC_VMULEUB = 1761, - PPC_VMULEUH = 1762, - PPC_VMULEUW = 1763, - PPC_VMULOSB = 1764, - PPC_VMULOSH = 1765, - PPC_VMULOSW = 1766, - PPC_VMULOUB = 1767, - PPC_VMULOUH = 1768, - PPC_VMULOUW = 1769, - PPC_VMULUWM = 1770, - PPC_VNAND = 1771, - PPC_VNCIPHER = 1772, - PPC_VNCIPHERLAST = 1773, - PPC_VNEGD = 1774, - PPC_VNEGW = 1775, - PPC_VNMSUBFP = 1776, - PPC_VNOR = 1777, - PPC_VOR = 1778, - PPC_VORC = 1779, - PPC_VPERM = 1780, - PPC_VPERMR = 1781, - PPC_VPERMXOR = 1782, - PPC_VPKPX = 1783, - PPC_VPKSDSS = 1784, - PPC_VPKSDUS = 1785, - PPC_VPKSHSS = 1786, - PPC_VPKSHUS = 1787, - PPC_VPKSWSS = 1788, - PPC_VPKSWUS = 1789, - PPC_VPKUDUM = 1790, - PPC_VPKUDUS = 1791, - PPC_VPKUHUM = 1792, - PPC_VPKUHUS = 1793, - PPC_VPKUWUM = 1794, - PPC_VPKUWUS = 1795, - PPC_VPMSUMB = 1796, - PPC_VPMSUMD = 1797, - PPC_VPMSUMH = 1798, - PPC_VPMSUMW = 1799, - PPC_VPOPCNTB = 1800, - PPC_VPOPCNTD = 1801, - PPC_VPOPCNTH = 1802, - PPC_VPOPCNTW = 1803, - PPC_VPRTYBD = 1804, - PPC_VPRTYBQ = 1805, - PPC_VPRTYBW = 1806, - PPC_VREFP = 1807, - PPC_VRFIM = 1808, - PPC_VRFIN = 1809, - PPC_VRFIP = 1810, - PPC_VRFIZ = 1811, - PPC_VRLB = 1812, - PPC_VRLD = 1813, - PPC_VRLDMI = 1814, - PPC_VRLDNM = 1815, - PPC_VRLH = 1816, - PPC_VRLW = 1817, - PPC_VRLWMI = 1818, - PPC_VRLWNM = 1819, - PPC_VRSQRTEFP = 1820, - PPC_VSBOX = 1821, - PPC_VSEL = 1822, - PPC_VSHASIGMAD = 1823, - PPC_VSHASIGMAW = 1824, - PPC_VSL = 1825, - PPC_VSLB = 1826, - PPC_VSLD = 1827, - PPC_VSLDOI = 1828, - PPC_VSLH = 1829, - PPC_VSLO = 1830, - PPC_VSLV = 1831, - PPC_VSLW = 1832, - PPC_VSPLTB = 1833, - PPC_VSPLTBs = 1834, - PPC_VSPLTH = 1835, - PPC_VSPLTHs = 1836, - PPC_VSPLTISB = 1837, - PPC_VSPLTISH = 1838, - PPC_VSPLTISW = 1839, - PPC_VSPLTW = 1840, - PPC_VSR = 1841, - PPC_VSRAB = 1842, - PPC_VSRAD = 1843, - PPC_VSRAH = 1844, - PPC_VSRAW = 1845, - PPC_VSRB = 1846, - PPC_VSRD = 1847, - PPC_VSRH = 1848, - PPC_VSRO = 1849, - PPC_VSRV = 1850, - PPC_VSRW = 1851, - PPC_VSUBCUQ = 1852, - PPC_VSUBCUW = 1853, - PPC_VSUBECUQ = 1854, - PPC_VSUBEUQM = 1855, - PPC_VSUBFP = 1856, - PPC_VSUBSBS = 1857, - PPC_VSUBSHS = 1858, - PPC_VSUBSWS = 1859, - PPC_VSUBUBM = 1860, - PPC_VSUBUBS = 1861, - PPC_VSUBUDM = 1862, - PPC_VSUBUHM = 1863, - PPC_VSUBUHS = 1864, - PPC_VSUBUQM = 1865, - PPC_VSUBUWM = 1866, - PPC_VSUBUWS = 1867, - PPC_VSUM2SWS = 1868, - PPC_VSUM4SBS = 1869, - PPC_VSUM4SHS = 1870, - PPC_VSUM4UBS = 1871, - PPC_VSUMSWS = 1872, - PPC_VUPKHPX = 1873, - PPC_VUPKHSB = 1874, - PPC_VUPKHSH = 1875, - PPC_VUPKHSW = 1876, - PPC_VUPKLPX = 1877, - PPC_VUPKLSB = 1878, - PPC_VUPKLSH = 1879, - PPC_VUPKLSW = 1880, - PPC_VXOR = 1881, - PPC_V_SET0 = 1882, - PPC_V_SET0B = 1883, - PPC_V_SET0H = 1884, - PPC_V_SETALLONES = 1885, - PPC_V_SETALLONESB = 1886, - PPC_V_SETALLONESH = 1887, - PPC_WAIT = 1888, - PPC_WRTEE = 1889, - PPC_WRTEEI = 1890, - PPC_XOR = 1891, - PPC_XOR8 = 1892, - PPC_XOR8o = 1893, - PPC_XORI = 1894, - PPC_XORI8 = 1895, - PPC_XORIS = 1896, - PPC_XORIS8 = 1897, - PPC_XORo = 1898, - PPC_XSABSDP = 1899, - PPC_XSABSQP = 1900, - PPC_XSADDDP = 1901, - PPC_XSADDQP = 1902, - PPC_XSADDQPO = 1903, - PPC_XSADDSP = 1904, - PPC_XSCMPEQDP = 1905, - PPC_XSCMPEXPDP = 1906, - PPC_XSCMPEXPQP = 1907, - PPC_XSCMPGEDP = 1908, - PPC_XSCMPGTDP = 1909, - PPC_XSCMPODP = 1910, - PPC_XSCMPOQP = 1911, - PPC_XSCMPUDP = 1912, - PPC_XSCMPUQP = 1913, - PPC_XSCPSGNDP = 1914, - PPC_XSCPSGNQP = 1915, - PPC_XSCVDPHP = 1916, - PPC_XSCVDPQP = 1917, - PPC_XSCVDPSP = 1918, - PPC_XSCVDPSPN = 1919, - PPC_XSCVDPSXDS = 1920, - PPC_XSCVDPSXDSs = 1921, - PPC_XSCVDPSXWS = 1922, - PPC_XSCVDPSXWSs = 1923, - PPC_XSCVDPUXDS = 1924, - PPC_XSCVDPUXDSs = 1925, - PPC_XSCVDPUXWS = 1926, - PPC_XSCVDPUXWSs = 1927, - PPC_XSCVHPDP = 1928, - PPC_XSCVQPDP = 1929, - PPC_XSCVQPDPO = 1930, - PPC_XSCVQPSDZ = 1931, - PPC_XSCVQPSWZ = 1932, - PPC_XSCVQPUDZ = 1933, - PPC_XSCVQPUWZ = 1934, - PPC_XSCVSDQP = 1935, - PPC_XSCVSPDP = 1936, - PPC_XSCVSPDPN = 1937, - PPC_XSCVSXDDP = 1938, - PPC_XSCVSXDSP = 1939, - PPC_XSCVUDQP = 1940, - PPC_XSCVUXDDP = 1941, - PPC_XSCVUXDSP = 1942, - PPC_XSDIVDP = 1943, - PPC_XSDIVQP = 1944, - PPC_XSDIVQPO = 1945, - PPC_XSDIVSP = 1946, - PPC_XSIEXPDP = 1947, - PPC_XSIEXPQP = 1948, - PPC_XSMADDADP = 1949, - PPC_XSMADDASP = 1950, - PPC_XSMADDMDP = 1951, - PPC_XSMADDMSP = 1952, - PPC_XSMADDQP = 1953, - PPC_XSMADDQPO = 1954, - PPC_XSMAXCDP = 1955, - PPC_XSMAXDP = 1956, - PPC_XSMAXJDP = 1957, - PPC_XSMINCDP = 1958, - PPC_XSMINDP = 1959, - PPC_XSMINJDP = 1960, - PPC_XSMSUBADP = 1961, - PPC_XSMSUBASP = 1962, - PPC_XSMSUBMDP = 1963, - PPC_XSMSUBMSP = 1964, - PPC_XSMSUBQP = 1965, - PPC_XSMSUBQPO = 1966, - PPC_XSMULDP = 1967, - PPC_XSMULQP = 1968, - PPC_XSMULQPO = 1969, - PPC_XSMULSP = 1970, - PPC_XSNABSDP = 1971, - PPC_XSNABSQP = 1972, - PPC_XSNEGDP = 1973, - PPC_XSNEGQP = 1974, - PPC_XSNMADDADP = 1975, - PPC_XSNMADDASP = 1976, - PPC_XSNMADDMDP = 1977, - PPC_XSNMADDMSP = 1978, - PPC_XSNMADDQP = 1979, - PPC_XSNMADDQPO = 1980, - PPC_XSNMSUBADP = 1981, - PPC_XSNMSUBASP = 1982, - PPC_XSNMSUBMDP = 1983, - PPC_XSNMSUBMSP = 1984, - PPC_XSNMSUBQP = 1985, - PPC_XSNMSUBQPO = 1986, - PPC_XSRDPI = 1987, - PPC_XSRDPIC = 1988, - PPC_XSRDPIM = 1989, - PPC_XSRDPIP = 1990, - PPC_XSRDPIZ = 1991, - PPC_XSREDP = 1992, - PPC_XSRESP = 1993, - PPC_XSRQPI = 1994, - PPC_XSRQPIX = 1995, - PPC_XSRQPXP = 1996, - PPC_XSRSP = 1997, - PPC_XSRSQRTEDP = 1998, - PPC_XSRSQRTESP = 1999, - PPC_XSSQRTDP = 2000, - PPC_XSSQRTQP = 2001, - PPC_XSSQRTQPO = 2002, - PPC_XSSQRTSP = 2003, - PPC_XSSUBDP = 2004, - PPC_XSSUBQP = 2005, - PPC_XSSUBQPO = 2006, - PPC_XSSUBSP = 2007, - PPC_XSTDIVDP = 2008, - PPC_XSTSQRTDP = 2009, - PPC_XSTSTDCDP = 2010, - PPC_XSTSTDCQP = 2011, - PPC_XSTSTDCSP = 2012, - PPC_XSXEXPDP = 2013, - PPC_XSXEXPQP = 2014, - PPC_XSXSIGDP = 2015, - PPC_XSXSIGQP = 2016, - PPC_XVABSDP = 2017, - PPC_XVABSSP = 2018, - PPC_XVADDDP = 2019, - PPC_XVADDSP = 2020, - PPC_XVCMPEQDP = 2021, - PPC_XVCMPEQDPo = 2022, - PPC_XVCMPEQSP = 2023, - PPC_XVCMPEQSPo = 2024, - PPC_XVCMPGEDP = 2025, - PPC_XVCMPGEDPo = 2026, - PPC_XVCMPGESP = 2027, - PPC_XVCMPGESPo = 2028, - PPC_XVCMPGTDP = 2029, - PPC_XVCMPGTDPo = 2030, - PPC_XVCMPGTSP = 2031, - PPC_XVCMPGTSPo = 2032, - PPC_XVCPSGNDP = 2033, - PPC_XVCPSGNSP = 2034, - PPC_XVCVDPSP = 2035, - PPC_XVCVDPSXDS = 2036, - PPC_XVCVDPSXWS = 2037, - PPC_XVCVDPUXDS = 2038, - PPC_XVCVDPUXWS = 2039, - PPC_XVCVHPSP = 2040, - PPC_XVCVSPDP = 2041, - PPC_XVCVSPHP = 2042, - PPC_XVCVSPSXDS = 2043, - PPC_XVCVSPSXWS = 2044, - PPC_XVCVSPUXDS = 2045, - PPC_XVCVSPUXWS = 2046, - PPC_XVCVSXDDP = 2047, - PPC_XVCVSXDSP = 2048, - PPC_XVCVSXWDP = 2049, - PPC_XVCVSXWSP = 2050, - PPC_XVCVUXDDP = 2051, - PPC_XVCVUXDSP = 2052, - PPC_XVCVUXWDP = 2053, - PPC_XVCVUXWSP = 2054, - PPC_XVDIVDP = 2055, - PPC_XVDIVSP = 2056, - PPC_XVIEXPDP = 2057, - PPC_XVIEXPSP = 2058, - PPC_XVMADDADP = 2059, - PPC_XVMADDASP = 2060, - PPC_XVMADDMDP = 2061, - PPC_XVMADDMSP = 2062, - PPC_XVMAXDP = 2063, - PPC_XVMAXSP = 2064, - PPC_XVMINDP = 2065, - PPC_XVMINSP = 2066, - PPC_XVMSUBADP = 2067, - PPC_XVMSUBASP = 2068, - PPC_XVMSUBMDP = 2069, - PPC_XVMSUBMSP = 2070, - PPC_XVMULDP = 2071, - PPC_XVMULSP = 2072, - PPC_XVNABSDP = 2073, - PPC_XVNABSSP = 2074, - PPC_XVNEGDP = 2075, - PPC_XVNEGSP = 2076, - PPC_XVNMADDADP = 2077, - PPC_XVNMADDASP = 2078, - PPC_XVNMADDMDP = 2079, - PPC_XVNMADDMSP = 2080, - PPC_XVNMSUBADP = 2081, - PPC_XVNMSUBASP = 2082, - PPC_XVNMSUBMDP = 2083, - PPC_XVNMSUBMSP = 2084, - PPC_XVRDPI = 2085, - PPC_XVRDPIC = 2086, - PPC_XVRDPIM = 2087, - PPC_XVRDPIP = 2088, - PPC_XVRDPIZ = 2089, - PPC_XVREDP = 2090, - PPC_XVRESP = 2091, - PPC_XVRSPI = 2092, - PPC_XVRSPIC = 2093, - PPC_XVRSPIM = 2094, - PPC_XVRSPIP = 2095, - PPC_XVRSPIZ = 2096, - PPC_XVRSQRTEDP = 2097, - PPC_XVRSQRTESP = 2098, - PPC_XVSQRTDP = 2099, - PPC_XVSQRTSP = 2100, - PPC_XVSUBDP = 2101, - PPC_XVSUBSP = 2102, - PPC_XVTDIVDP = 2103, - PPC_XVTDIVSP = 2104, - PPC_XVTSQRTDP = 2105, - PPC_XVTSQRTSP = 2106, - PPC_XVTSTDCDP = 2107, - PPC_XVTSTDCSP = 2108, - PPC_XVXEXPDP = 2109, - PPC_XVXEXPSP = 2110, - PPC_XVXSIGDP = 2111, - PPC_XVXSIGSP = 2112, - PPC_XXBRD = 2113, - PPC_XXBRH = 2114, - PPC_XXBRQ = 2115, - PPC_XXBRW = 2116, - PPC_XXEXTRACTUW = 2117, - PPC_XXINSERTW = 2118, - PPC_XXLAND = 2119, - PPC_XXLANDC = 2120, - PPC_XXLEQV = 2121, - PPC_XXLNAND = 2122, - PPC_XXLNOR = 2123, - PPC_XXLOR = 2124, - PPC_XXLORC = 2125, - PPC_XXLORf = 2126, - PPC_XXLXOR = 2127, - PPC_XXLXORdpz = 2128, - PPC_XXLXORspz = 2129, - PPC_XXLXORz = 2130, - PPC_XXMRGHW = 2131, - PPC_XXMRGLW = 2132, - PPC_XXPERM = 2133, - PPC_XXPERMDI = 2134, - PPC_XXPERMDIs = 2135, - PPC_XXPERMR = 2136, - PPC_XXSEL = 2137, - PPC_XXSLDWI = 2138, - PPC_XXSLDWIs = 2139, - PPC_XXSPLTIB = 2140, - PPC_XXSPLTW = 2141, - PPC_XXSPLTWs = 2142, - PPC_gBC = 2143, - PPC_gBCA = 2144, - PPC_gBCAat = 2145, - PPC_gBCCTR = 2146, - PPC_gBCCTRL = 2147, - PPC_gBCL = 2148, - PPC_gBCLA = 2149, - PPC_gBCLAat = 2150, - PPC_gBCLR = 2151, - PPC_gBCLRL = 2152, - PPC_gBCLat = 2153, - PPC_gBCat = 2154, - PPC_INSTRUCTION_LIST_END = 2155 + PPC_PHI = 0, + PPC_INLINEASM = 1, + PPC_CFI_INSTRUCTION = 2, + PPC_EH_LABEL = 3, + PPC_GC_LABEL = 4, + PPC_ANNOTATION_LABEL = 5, + PPC_KILL = 6, + PPC_EXTRACT_SUBREG = 7, + PPC_INSERT_SUBREG = 8, + PPC_IMPLICIT_DEF = 9, + PPC_SUBREG_TO_REG = 10, + PPC_COPY_TO_REGCLASS = 11, + PPC_DBG_VALUE = 12, + PPC_DBG_LABEL = 13, + PPC_REG_SEQUENCE = 14, + PPC_COPY = 15, + PPC_BUNDLE = 16, + PPC_LIFETIME_START = 17, + PPC_LIFETIME_END = 18, + PPC_STACKMAP = 19, + PPC_FENTRY_CALL = 20, + PPC_PATCHPOINT = 21, + PPC_LOAD_STACK_GUARD = 22, + PPC_STATEPOINT = 23, + PPC_LOCAL_ESCAPE = 24, + PPC_FAULTING_OP = 25, + PPC_PATCHABLE_OP = 26, + PPC_PATCHABLE_FUNCTION_ENTER = 27, + PPC_PATCHABLE_RET = 28, + PPC_PATCHABLE_FUNCTION_EXIT = 29, + PPC_PATCHABLE_TAIL_CALL = 30, + PPC_PATCHABLE_EVENT_CALL = 31, + PPC_PATCHABLE_TYPED_EVENT_CALL = 32, + PPC_ICALL_BRANCH_FUNNEL = 33, + PPC_G_ADD = 34, + PPC_G_SUB = 35, + PPC_G_MUL = 36, + PPC_G_SDIV = 37, + PPC_G_UDIV = 38, + PPC_G_SREM = 39, + PPC_G_UREM = 40, + PPC_G_AND = 41, + PPC_G_OR = 42, + PPC_G_XOR = 43, + PPC_G_IMPLICIT_DEF = 44, + PPC_G_PHI = 45, + PPC_G_FRAME_INDEX = 46, + PPC_G_GLOBAL_VALUE = 47, + PPC_G_EXTRACT = 48, + PPC_G_UNMERGE_VALUES = 49, + PPC_G_INSERT = 50, + PPC_G_MERGE_VALUES = 51, + PPC_G_PTRTOINT = 52, + PPC_G_INTTOPTR = 53, + PPC_G_BITCAST = 54, + PPC_G_LOAD = 55, + PPC_G_SEXTLOAD = 56, + PPC_G_ZEXTLOAD = 57, + PPC_G_STORE = 58, + PPC_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, + PPC_G_ATOMIC_CMPXCHG = 60, + PPC_G_ATOMICRMW_XCHG = 61, + PPC_G_ATOMICRMW_ADD = 62, + PPC_G_ATOMICRMW_SUB = 63, + PPC_G_ATOMICRMW_AND = 64, + PPC_G_ATOMICRMW_NAND = 65, + PPC_G_ATOMICRMW_OR = 66, + PPC_G_ATOMICRMW_XOR = 67, + PPC_G_ATOMICRMW_MAX = 68, + PPC_G_ATOMICRMW_MIN = 69, + PPC_G_ATOMICRMW_UMAX = 70, + PPC_G_ATOMICRMW_UMIN = 71, + PPC_G_BRCOND = 72, + PPC_G_BRINDIRECT = 73, + PPC_G_INTRINSIC = 74, + PPC_G_INTRINSIC_W_SIDE_EFFECTS = 75, + PPC_G_ANYEXT = 76, + PPC_G_TRUNC = 77, + PPC_G_CONSTANT = 78, + PPC_G_FCONSTANT = 79, + PPC_G_VASTART = 80, + PPC_G_VAARG = 81, + PPC_G_SEXT = 82, + PPC_G_ZEXT = 83, + PPC_G_SHL = 84, + PPC_G_LSHR = 85, + PPC_G_ASHR = 86, + PPC_G_ICMP = 87, + PPC_G_FCMP = 88, + PPC_G_SELECT = 89, + PPC_G_UADDE = 90, + PPC_G_USUBE = 91, + PPC_G_SADDO = 92, + PPC_G_SSUBO = 93, + PPC_G_UMULO = 94, + PPC_G_SMULO = 95, + PPC_G_UMULH = 96, + PPC_G_SMULH = 97, + PPC_G_FADD = 98, + PPC_G_FSUB = 99, + PPC_G_FMUL = 100, + PPC_G_FMA = 101, + PPC_G_FDIV = 102, + PPC_G_FREM = 103, + PPC_G_FPOW = 104, + PPC_G_FEXP = 105, + PPC_G_FEXP2 = 106, + PPC_G_FLOG = 107, + PPC_G_FLOG2 = 108, + PPC_G_FNEG = 109, + PPC_G_FPEXT = 110, + PPC_G_FPTRUNC = 111, + PPC_G_FPTOSI = 112, + PPC_G_FPTOUI = 113, + PPC_G_SITOFP = 114, + PPC_G_UITOFP = 115, + PPC_G_FABS = 116, + PPC_G_GEP = 117, + PPC_G_PTR_MASK = 118, + PPC_G_BR = 119, + PPC_G_INSERT_VECTOR_ELT = 120, + PPC_G_EXTRACT_VECTOR_ELT = 121, + PPC_G_SHUFFLE_VECTOR = 122, + PPC_G_BSWAP = 123, + PPC_G_ADDRSPACE_CAST = 124, + PPC_G_BLOCK_ADDR = 125, + PPC_CFENCE8 = 126, + PPC_CLRLSLDI = 127, + PPC_CLRLSLDIo = 128, + PPC_CLRLSLWI = 129, + PPC_CLRLSLWIo = 130, + PPC_CLRRDI = 131, + PPC_CLRRDIo = 132, + PPC_CLRRWI = 133, + PPC_CLRRWIo = 134, + PPC_CP_COPY_FIRST = 135, + PPC_CP_COPYx = 136, + PPC_CP_PASTE_LAST = 137, + PPC_CP_PASTEx = 138, + PPC_DCBFL = 139, + PPC_DCBFLP = 140, + PPC_DCBFx = 141, + PPC_DCBTCT = 142, + PPC_DCBTDS = 143, + PPC_DCBTSTCT = 144, + PPC_DCBTSTDS = 145, + PPC_DCBTSTT = 146, + PPC_DCBTSTx = 147, + PPC_DCBTT = 148, + PPC_DCBTx = 149, + PPC_DFLOADf32 = 150, + PPC_DFLOADf64 = 151, + PPC_DFSTOREf32 = 152, + PPC_DFSTOREf64 = 153, + PPC_EXTLDI = 154, + PPC_EXTLDIo = 155, + PPC_EXTLWI = 156, + PPC_EXTLWIo = 157, + PPC_EXTRDI = 158, + PPC_EXTRDIo = 159, + PPC_EXTRWI = 160, + PPC_EXTRWIo = 161, + PPC_INSLWI = 162, + PPC_INSLWIo = 163, + PPC_INSRDI = 164, + PPC_INSRDIo = 165, + PPC_INSRWI = 166, + PPC_INSRWIo = 167, + PPC_LAx = 168, + PPC_LIWAX = 169, + PPC_LIWZX = 170, + PPC_RLWIMIbm = 171, + PPC_RLWIMIobm = 172, + PPC_RLWINMbm = 173, + PPC_RLWINMobm = 174, + PPC_RLWNMbm = 175, + PPC_RLWNMobm = 176, + PPC_ROTRDI = 177, + PPC_ROTRDIo = 178, + PPC_ROTRWI = 179, + PPC_ROTRWIo = 180, + PPC_SLDI = 181, + PPC_SLDIo = 182, + PPC_SLWI = 183, + PPC_SLWIo = 184, + PPC_SPILLTOVSR_LD = 185, + PPC_SPILLTOVSR_LDX = 186, + PPC_SPILLTOVSR_ST = 187, + PPC_SPILLTOVSR_STX = 188, + PPC_SRDI = 189, + PPC_SRDIo = 190, + PPC_SRWI = 191, + PPC_SRWIo = 192, + PPC_STIWX = 193, + PPC_SUBI = 194, + PPC_SUBIC = 195, + PPC_SUBICo = 196, + PPC_SUBIS = 197, + PPC_SUBPCIS = 198, + PPC_XFLOADf32 = 199, + PPC_XFLOADf64 = 200, + PPC_XFSTOREf32 = 201, + PPC_XFSTOREf64 = 202, + PPC_ADD4 = 203, + PPC_ADD4TLS = 204, + PPC_ADD4o = 205, + PPC_ADD8 = 206, + PPC_ADD8TLS = 207, + PPC_ADD8TLS_ = 208, + PPC_ADD8o = 209, + PPC_ADDC = 210, + PPC_ADDC8 = 211, + PPC_ADDC8o = 212, + PPC_ADDCo = 213, + PPC_ADDE = 214, + PPC_ADDE8 = 215, + PPC_ADDE8o = 216, + PPC_ADDEo = 217, + PPC_ADDI = 218, + PPC_ADDI8 = 219, + PPC_ADDIC = 220, + PPC_ADDIC8 = 221, + PPC_ADDICo = 222, + PPC_ADDIS = 223, + PPC_ADDIS8 = 224, + PPC_ADDISdtprelHA = 225, + PPC_ADDISdtprelHA32 = 226, + PPC_ADDISgotTprelHA = 227, + PPC_ADDIStlsgdHA = 228, + PPC_ADDIStlsldHA = 229, + PPC_ADDIStocHA = 230, + PPC_ADDIdtprelL = 231, + PPC_ADDIdtprelL32 = 232, + PPC_ADDItlsgdL = 233, + PPC_ADDItlsgdL32 = 234, + PPC_ADDItlsgdLADDR = 235, + PPC_ADDItlsgdLADDR32 = 236, + PPC_ADDItlsldL = 237, + PPC_ADDItlsldL32 = 238, + PPC_ADDItlsldLADDR = 239, + PPC_ADDItlsldLADDR32 = 240, + PPC_ADDItocL = 241, + PPC_ADDME = 242, + PPC_ADDME8 = 243, + PPC_ADDME8o = 244, + PPC_ADDMEo = 245, + PPC_ADDPCIS = 246, + PPC_ADDZE = 247, + PPC_ADDZE8 = 248, + PPC_ADDZE8o = 249, + PPC_ADDZEo = 250, + PPC_ADJCALLSTACKDOWN = 251, + PPC_ADJCALLSTACKUP = 252, + PPC_AND = 253, + PPC_AND8 = 254, + PPC_AND8o = 255, + PPC_ANDC = 256, + PPC_ANDC8 = 257, + PPC_ANDC8o = 258, + PPC_ANDCo = 259, + PPC_ANDISo = 260, + PPC_ANDISo8 = 261, + PPC_ANDIo = 262, + PPC_ANDIo8 = 263, + PPC_ANDIo_1_EQ_BIT = 264, + PPC_ANDIo_1_EQ_BIT8 = 265, + PPC_ANDIo_1_GT_BIT = 266, + PPC_ANDIo_1_GT_BIT8 = 267, + PPC_ANDo = 268, + PPC_ATOMIC_CMP_SWAP_I16 = 269, + PPC_ATOMIC_CMP_SWAP_I32 = 270, + PPC_ATOMIC_CMP_SWAP_I64 = 271, + PPC_ATOMIC_CMP_SWAP_I8 = 272, + PPC_ATOMIC_LOAD_ADD_I16 = 273, + PPC_ATOMIC_LOAD_ADD_I32 = 274, + PPC_ATOMIC_LOAD_ADD_I64 = 275, + PPC_ATOMIC_LOAD_ADD_I8 = 276, + PPC_ATOMIC_LOAD_AND_I16 = 277, + PPC_ATOMIC_LOAD_AND_I32 = 278, + PPC_ATOMIC_LOAD_AND_I64 = 279, + PPC_ATOMIC_LOAD_AND_I8 = 280, + PPC_ATOMIC_LOAD_MAX_I16 = 281, + PPC_ATOMIC_LOAD_MAX_I32 = 282, + PPC_ATOMIC_LOAD_MAX_I64 = 283, + PPC_ATOMIC_LOAD_MAX_I8 = 284, + PPC_ATOMIC_LOAD_MIN_I16 = 285, + PPC_ATOMIC_LOAD_MIN_I32 = 286, + PPC_ATOMIC_LOAD_MIN_I64 = 287, + PPC_ATOMIC_LOAD_MIN_I8 = 288, + PPC_ATOMIC_LOAD_NAND_I16 = 289, + PPC_ATOMIC_LOAD_NAND_I32 = 290, + PPC_ATOMIC_LOAD_NAND_I64 = 291, + PPC_ATOMIC_LOAD_NAND_I8 = 292, + PPC_ATOMIC_LOAD_OR_I16 = 293, + PPC_ATOMIC_LOAD_OR_I32 = 294, + PPC_ATOMIC_LOAD_OR_I64 = 295, + PPC_ATOMIC_LOAD_OR_I8 = 296, + PPC_ATOMIC_LOAD_SUB_I16 = 297, + PPC_ATOMIC_LOAD_SUB_I32 = 298, + PPC_ATOMIC_LOAD_SUB_I64 = 299, + PPC_ATOMIC_LOAD_SUB_I8 = 300, + PPC_ATOMIC_LOAD_UMAX_I16 = 301, + PPC_ATOMIC_LOAD_UMAX_I32 = 302, + PPC_ATOMIC_LOAD_UMAX_I64 = 303, + PPC_ATOMIC_LOAD_UMAX_I8 = 304, + PPC_ATOMIC_LOAD_UMIN_I16 = 305, + PPC_ATOMIC_LOAD_UMIN_I32 = 306, + PPC_ATOMIC_LOAD_UMIN_I64 = 307, + PPC_ATOMIC_LOAD_UMIN_I8 = 308, + PPC_ATOMIC_LOAD_XOR_I16 = 309, + PPC_ATOMIC_LOAD_XOR_I32 = 310, + PPC_ATOMIC_LOAD_XOR_I64 = 311, + PPC_ATOMIC_LOAD_XOR_I8 = 312, + PPC_ATOMIC_SWAP_I16 = 313, + PPC_ATOMIC_SWAP_I32 = 314, + PPC_ATOMIC_SWAP_I64 = 315, + PPC_ATOMIC_SWAP_I8 = 316, + PPC_ATTN = 317, + PPC_B = 318, + PPC_BA = 319, + PPC_BC = 320, + PPC_BCC = 321, + PPC_BCCA = 322, + PPC_BCCCTR = 323, + PPC_BCCCTR8 = 324, + PPC_BCCCTRL = 325, + PPC_BCCCTRL8 = 326, + PPC_BCCL = 327, + PPC_BCCLA = 328, + PPC_BCCLR = 329, + PPC_BCCLRL = 330, + PPC_BCCTR = 331, + PPC_BCCTR8 = 332, + PPC_BCCTR8n = 333, + PPC_BCCTRL = 334, + PPC_BCCTRL8 = 335, + PPC_BCCTRL8n = 336, + PPC_BCCTRLn = 337, + PPC_BCCTRn = 338, + PPC_BCDCFNo = 339, + PPC_BCDCFSQo = 340, + PPC_BCDCFZo = 341, + PPC_BCDCPSGNo = 342, + PPC_BCDCTNo = 343, + PPC_BCDCTSQo = 344, + PPC_BCDCTZo = 345, + PPC_BCDSETSGNo = 346, + PPC_BCDSRo = 347, + PPC_BCDSo = 348, + PPC_BCDTRUNCo = 349, + PPC_BCDUSo = 350, + PPC_BCDUTRUNCo = 351, + PPC_BCL = 352, + PPC_BCLR = 353, + PPC_BCLRL = 354, + PPC_BCLRLn = 355, + PPC_BCLRn = 356, + PPC_BCLalways = 357, + PPC_BCLn = 358, + PPC_BCTR = 359, + PPC_BCTR8 = 360, + PPC_BCTRL = 361, + PPC_BCTRL8 = 362, + PPC_BCTRL8_LDinto_toc = 363, + PPC_BCn = 364, + PPC_BDNZ = 365, + PPC_BDNZ8 = 366, + PPC_BDNZA = 367, + PPC_BDNZAm = 368, + PPC_BDNZAp = 369, + PPC_BDNZL = 370, + PPC_BDNZLA = 371, + PPC_BDNZLAm = 372, + PPC_BDNZLAp = 373, + PPC_BDNZLR = 374, + PPC_BDNZLR8 = 375, + PPC_BDNZLRL = 376, + PPC_BDNZLRLm = 377, + PPC_BDNZLRLp = 378, + PPC_BDNZLRm = 379, + PPC_BDNZLRp = 380, + PPC_BDNZLm = 381, + PPC_BDNZLp = 382, + PPC_BDNZm = 383, + PPC_BDNZp = 384, + PPC_BDZ = 385, + PPC_BDZ8 = 386, + PPC_BDZA = 387, + PPC_BDZAm = 388, + PPC_BDZAp = 389, + PPC_BDZL = 390, + PPC_BDZLA = 391, + PPC_BDZLAm = 392, + PPC_BDZLAp = 393, + PPC_BDZLR = 394, + PPC_BDZLR8 = 395, + PPC_BDZLRL = 396, + PPC_BDZLRLm = 397, + PPC_BDZLRLp = 398, + PPC_BDZLRm = 399, + PPC_BDZLRp = 400, + PPC_BDZLm = 401, + PPC_BDZLp = 402, + PPC_BDZm = 403, + PPC_BDZp = 404, + PPC_BL = 405, + PPC_BL8 = 406, + PPC_BL8_NOP = 407, + PPC_BL8_NOP_TLS = 408, + PPC_BL8_TLS = 409, + PPC_BL8_TLS_ = 410, + PPC_BLA = 411, + PPC_BLA8 = 412, + PPC_BLA8_NOP = 413, + PPC_BLR = 414, + PPC_BLR8 = 415, + PPC_BLRL = 416, + PPC_BL_TLS = 417, + PPC_BPERMD = 418, + PPC_BRINC = 419, + PPC_CLRBHRB = 420, + PPC_CMPB = 421, + PPC_CMPB8 = 422, + PPC_CMPD = 423, + PPC_CMPDI = 424, + PPC_CMPEQB = 425, + PPC_CMPLD = 426, + PPC_CMPLDI = 427, + PPC_CMPLW = 428, + PPC_CMPLWI = 429, + PPC_CMPRB = 430, + PPC_CMPRB8 = 431, + PPC_CMPW = 432, + PPC_CMPWI = 433, + PPC_CNTLZD = 434, + PPC_CNTLZDo = 435, + PPC_CNTLZW = 436, + PPC_CNTLZW8 = 437, + PPC_CNTLZW8o = 438, + PPC_CNTLZWo = 439, + PPC_CNTTZD = 440, + PPC_CNTTZDo = 441, + PPC_CNTTZW = 442, + PPC_CNTTZW8 = 443, + PPC_CNTTZW8o = 444, + PPC_CNTTZWo = 445, + PPC_CP_ABORT = 446, + PPC_CP_COPY = 447, + PPC_CP_COPY8 = 448, + PPC_CP_PASTE = 449, + PPC_CP_PASTE8 = 450, + PPC_CP_PASTE8o = 451, + PPC_CP_PASTEo = 452, + PPC_CR6SET = 453, + PPC_CR6UNSET = 454, + PPC_CRAND = 455, + PPC_CRANDC = 456, + PPC_CREQV = 457, + PPC_CRNAND = 458, + PPC_CRNOR = 459, + PPC_CROR = 460, + PPC_CRORC = 461, + PPC_CRSET = 462, + PPC_CRUNSET = 463, + PPC_CRXOR = 464, + PPC_CTRL_DEP = 465, + PPC_DARN = 466, + PPC_DCBA = 467, + PPC_DCBF = 468, + PPC_DCBFEP = 469, + PPC_DCBI = 470, + PPC_DCBST = 471, + PPC_DCBSTEP = 472, + PPC_DCBT = 473, + PPC_DCBTEP = 474, + PPC_DCBTST = 475, + PPC_DCBTSTEP = 476, + PPC_DCBZ = 477, + PPC_DCBZEP = 478, + PPC_DCBZL = 479, + PPC_DCBZLEP = 480, + PPC_DCCCI = 481, + PPC_DIVD = 482, + PPC_DIVDE = 483, + PPC_DIVDEU = 484, + PPC_DIVDEUo = 485, + PPC_DIVDEo = 486, + PPC_DIVDU = 487, + PPC_DIVDUo = 488, + PPC_DIVDo = 489, + PPC_DIVW = 490, + PPC_DIVWE = 491, + PPC_DIVWEU = 492, + PPC_DIVWEUo = 493, + PPC_DIVWEo = 494, + PPC_DIVWU = 495, + PPC_DIVWUo = 496, + PPC_DIVWo = 497, + PPC_DSS = 498, + PPC_DSSALL = 499, + PPC_DST = 500, + PPC_DST64 = 501, + PPC_DSTST = 502, + PPC_DSTST64 = 503, + PPC_DSTSTT = 504, + PPC_DSTSTT64 = 505, + PPC_DSTT = 506, + PPC_DSTT64 = 507, + PPC_DYNALLOC = 508, + PPC_DYNALLOC8 = 509, + PPC_DYNAREAOFFSET = 510, + PPC_DYNAREAOFFSET8 = 511, + PPC_EFDABS = 512, + PPC_EFDADD = 513, + PPC_EFDCFS = 514, + PPC_EFDCFSF = 515, + PPC_EFDCFSI = 516, + PPC_EFDCFSID = 517, + PPC_EFDCFUF = 518, + PPC_EFDCFUI = 519, + PPC_EFDCFUID = 520, + PPC_EFDCMPEQ = 521, + PPC_EFDCMPGT = 522, + PPC_EFDCMPLT = 523, + PPC_EFDCTSF = 524, + PPC_EFDCTSI = 525, + PPC_EFDCTSIDZ = 526, + PPC_EFDCTSIZ = 527, + PPC_EFDCTUF = 528, + PPC_EFDCTUI = 529, + PPC_EFDCTUIDZ = 530, + PPC_EFDCTUIZ = 531, + PPC_EFDDIV = 532, + PPC_EFDMUL = 533, + PPC_EFDNABS = 534, + PPC_EFDNEG = 535, + PPC_EFDSUB = 536, + PPC_EFDTSTEQ = 537, + PPC_EFDTSTGT = 538, + PPC_EFDTSTLT = 539, + PPC_EFSABS = 540, + PPC_EFSADD = 541, + PPC_EFSCFD = 542, + PPC_EFSCFSF = 543, + PPC_EFSCFSI = 544, + PPC_EFSCFUF = 545, + PPC_EFSCFUI = 546, + PPC_EFSCMPEQ = 547, + PPC_EFSCMPGT = 548, + PPC_EFSCMPLT = 549, + PPC_EFSCTSF = 550, + PPC_EFSCTSI = 551, + PPC_EFSCTSIZ = 552, + PPC_EFSCTUF = 553, + PPC_EFSCTUI = 554, + PPC_EFSCTUIZ = 555, + PPC_EFSDIV = 556, + PPC_EFSMUL = 557, + PPC_EFSNABS = 558, + PPC_EFSNEG = 559, + PPC_EFSSUB = 560, + PPC_EFSTSTEQ = 561, + PPC_EFSTSTGT = 562, + PPC_EFSTSTLT = 563, + PPC_EH_SjLj_LongJmp32 = 564, + PPC_EH_SjLj_LongJmp64 = 565, + PPC_EH_SjLj_SetJmp32 = 566, + PPC_EH_SjLj_SetJmp64 = 567, + PPC_EH_SjLj_Setup = 568, + PPC_EQV = 569, + PPC_EQV8 = 570, + PPC_EQV8o = 571, + PPC_EQVo = 572, + PPC_EVABS = 573, + PPC_EVADDIW = 574, + PPC_EVADDSMIAAW = 575, + PPC_EVADDSSIAAW = 576, + PPC_EVADDUMIAAW = 577, + PPC_EVADDUSIAAW = 578, + PPC_EVADDW = 579, + PPC_EVAND = 580, + PPC_EVANDC = 581, + PPC_EVCMPEQ = 582, + PPC_EVCMPGTS = 583, + PPC_EVCMPGTU = 584, + PPC_EVCMPLTS = 585, + PPC_EVCMPLTU = 586, + PPC_EVCNTLSW = 587, + PPC_EVCNTLZW = 588, + PPC_EVDIVWS = 589, + PPC_EVDIVWU = 590, + PPC_EVEQV = 591, + PPC_EVEXTSB = 592, + PPC_EVEXTSH = 593, + PPC_EVFSABS = 594, + PPC_EVFSADD = 595, + PPC_EVFSCFSF = 596, + PPC_EVFSCFSI = 597, + PPC_EVFSCFUF = 598, + PPC_EVFSCFUI = 599, + PPC_EVFSCMPEQ = 600, + PPC_EVFSCMPGT = 601, + PPC_EVFSCMPLT = 602, + PPC_EVFSCTSF = 603, + PPC_EVFSCTSI = 604, + PPC_EVFSCTSIZ = 605, + PPC_EVFSCTUF = 606, + PPC_EVFSCTUI = 607, + PPC_EVFSCTUIZ = 608, + PPC_EVFSDIV = 609, + PPC_EVFSMUL = 610, + PPC_EVFSNABS = 611, + PPC_EVFSNEG = 612, + PPC_EVFSSUB = 613, + PPC_EVFSTSTEQ = 614, + PPC_EVFSTSTGT = 615, + PPC_EVFSTSTLT = 616, + PPC_EVLDD = 617, + PPC_EVLDDX = 618, + PPC_EVLDH = 619, + PPC_EVLDHX = 620, + PPC_EVLDW = 621, + PPC_EVLDWX = 622, + PPC_EVLHHESPLAT = 623, + PPC_EVLHHESPLATX = 624, + PPC_EVLHHOSSPLAT = 625, + PPC_EVLHHOSSPLATX = 626, + PPC_EVLHHOUSPLAT = 627, + PPC_EVLHHOUSPLATX = 628, + PPC_EVLWHE = 629, + PPC_EVLWHEX = 630, + PPC_EVLWHOS = 631, + PPC_EVLWHOSX = 632, + PPC_EVLWHOU = 633, + PPC_EVLWHOUX = 634, + PPC_EVLWHSPLAT = 635, + PPC_EVLWHSPLATX = 636, + PPC_EVLWWSPLAT = 637, + PPC_EVLWWSPLATX = 638, + PPC_EVMERGEHI = 639, + PPC_EVMERGEHILO = 640, + PPC_EVMERGELO = 641, + PPC_EVMERGELOHI = 642, + PPC_EVMHEGSMFAA = 643, + PPC_EVMHEGSMFAN = 644, + PPC_EVMHEGSMIAA = 645, + PPC_EVMHEGSMIAN = 646, + PPC_EVMHEGUMIAA = 647, + PPC_EVMHEGUMIAN = 648, + PPC_EVMHESMF = 649, + PPC_EVMHESMFA = 650, + PPC_EVMHESMFAAW = 651, + PPC_EVMHESMFANW = 652, + PPC_EVMHESMI = 653, + PPC_EVMHESMIA = 654, + PPC_EVMHESMIAAW = 655, + PPC_EVMHESMIANW = 656, + PPC_EVMHESSF = 657, + PPC_EVMHESSFA = 658, + PPC_EVMHESSFAAW = 659, + PPC_EVMHESSFANW = 660, + PPC_EVMHESSIAAW = 661, + PPC_EVMHESSIANW = 662, + PPC_EVMHEUMI = 663, + PPC_EVMHEUMIA = 664, + PPC_EVMHEUMIAAW = 665, + PPC_EVMHEUMIANW = 666, + PPC_EVMHEUSIAAW = 667, + PPC_EVMHEUSIANW = 668, + PPC_EVMHOGSMFAA = 669, + PPC_EVMHOGSMFAN = 670, + PPC_EVMHOGSMIAA = 671, + PPC_EVMHOGSMIAN = 672, + PPC_EVMHOGUMIAA = 673, + PPC_EVMHOGUMIAN = 674, + PPC_EVMHOSMF = 675, + PPC_EVMHOSMFA = 676, + PPC_EVMHOSMFAAW = 677, + PPC_EVMHOSMFANW = 678, + PPC_EVMHOSMI = 679, + PPC_EVMHOSMIA = 680, + PPC_EVMHOSMIAAW = 681, + PPC_EVMHOSMIANW = 682, + PPC_EVMHOSSF = 683, + PPC_EVMHOSSFA = 684, + PPC_EVMHOSSFAAW = 685, + PPC_EVMHOSSFANW = 686, + PPC_EVMHOSSIAAW = 687, + PPC_EVMHOSSIANW = 688, + PPC_EVMHOUMI = 689, + PPC_EVMHOUMIA = 690, + PPC_EVMHOUMIAAW = 691, + PPC_EVMHOUMIANW = 692, + PPC_EVMHOUSIAAW = 693, + PPC_EVMHOUSIANW = 694, + PPC_EVMRA = 695, + PPC_EVMWHSMF = 696, + PPC_EVMWHSMFA = 697, + PPC_EVMWHSMI = 698, + PPC_EVMWHSMIA = 699, + PPC_EVMWHSSF = 700, + PPC_EVMWHSSFA = 701, + PPC_EVMWHUMI = 702, + PPC_EVMWHUMIA = 703, + PPC_EVMWLSMIAAW = 704, + PPC_EVMWLSMIANW = 705, + PPC_EVMWLSSIAAW = 706, + PPC_EVMWLSSIANW = 707, + PPC_EVMWLUMI = 708, + PPC_EVMWLUMIA = 709, + PPC_EVMWLUMIAAW = 710, + PPC_EVMWLUMIANW = 711, + PPC_EVMWLUSIAAW = 712, + PPC_EVMWLUSIANW = 713, + PPC_EVMWSMF = 714, + PPC_EVMWSMFA = 715, + PPC_EVMWSMFAA = 716, + PPC_EVMWSMFAN = 717, + PPC_EVMWSMI = 718, + PPC_EVMWSMIA = 719, + PPC_EVMWSMIAA = 720, + PPC_EVMWSMIAN = 721, + PPC_EVMWSSF = 722, + PPC_EVMWSSFA = 723, + PPC_EVMWSSFAA = 724, + PPC_EVMWSSFAN = 725, + PPC_EVMWUMI = 726, + PPC_EVMWUMIA = 727, + PPC_EVMWUMIAA = 728, + PPC_EVMWUMIAN = 729, + PPC_EVNAND = 730, + PPC_EVNEG = 731, + PPC_EVNOR = 732, + PPC_EVOR = 733, + PPC_EVORC = 734, + PPC_EVRLW = 735, + PPC_EVRLWI = 736, + PPC_EVRNDW = 737, + PPC_EVSEL = 738, + PPC_EVSLW = 739, + PPC_EVSLWI = 740, + PPC_EVSPLATFI = 741, + PPC_EVSPLATI = 742, + PPC_EVSRWIS = 743, + PPC_EVSRWIU = 744, + PPC_EVSRWS = 745, + PPC_EVSRWU = 746, + PPC_EVSTDD = 747, + PPC_EVSTDDX = 748, + PPC_EVSTDH = 749, + PPC_EVSTDHX = 750, + PPC_EVSTDW = 751, + PPC_EVSTDWX = 752, + PPC_EVSTWHE = 753, + PPC_EVSTWHEX = 754, + PPC_EVSTWHO = 755, + PPC_EVSTWHOX = 756, + PPC_EVSTWWE = 757, + PPC_EVSTWWEX = 758, + PPC_EVSTWWO = 759, + PPC_EVSTWWOX = 760, + PPC_EVSUBFSMIAAW = 761, + PPC_EVSUBFSSIAAW = 762, + PPC_EVSUBFUMIAAW = 763, + PPC_EVSUBFUSIAAW = 764, + PPC_EVSUBFW = 765, + PPC_EVSUBIFW = 766, + PPC_EVXOR = 767, + PPC_EXTSB = 768, + PPC_EXTSB8 = 769, + PPC_EXTSB8_32_64 = 770, + PPC_EXTSB8o = 771, + PPC_EXTSBo = 772, + PPC_EXTSH = 773, + PPC_EXTSH8 = 774, + PPC_EXTSH8_32_64 = 775, + PPC_EXTSH8o = 776, + PPC_EXTSHo = 777, + PPC_EXTSW = 778, + PPC_EXTSWSLI = 779, + PPC_EXTSWSLIo = 780, + PPC_EXTSW_32 = 781, + PPC_EXTSW_32_64 = 782, + PPC_EXTSW_32_64o = 783, + PPC_EXTSWo = 784, + PPC_EnforceIEIO = 785, + PPC_FABSD = 786, + PPC_FABSDo = 787, + PPC_FABSS = 788, + PPC_FABSSo = 789, + PPC_FADD = 790, + PPC_FADDS = 791, + PPC_FADDSo = 792, + PPC_FADDo = 793, + PPC_FADDrtz = 794, + PPC_FCFID = 795, + PPC_FCFIDS = 796, + PPC_FCFIDSo = 797, + PPC_FCFIDU = 798, + PPC_FCFIDUS = 799, + PPC_FCFIDUSo = 800, + PPC_FCFIDUo = 801, + PPC_FCFIDo = 802, + PPC_FCMPUD = 803, + PPC_FCMPUS = 804, + PPC_FCPSGND = 805, + PPC_FCPSGNDo = 806, + PPC_FCPSGNS = 807, + PPC_FCPSGNSo = 808, + PPC_FCTID = 809, + PPC_FCTIDU = 810, + PPC_FCTIDUZ = 811, + PPC_FCTIDUZo = 812, + PPC_FCTIDUo = 813, + PPC_FCTIDZ = 814, + PPC_FCTIDZo = 815, + PPC_FCTIDo = 816, + PPC_FCTIW = 817, + PPC_FCTIWU = 818, + PPC_FCTIWUZ = 819, + PPC_FCTIWUZo = 820, + PPC_FCTIWUo = 821, + PPC_FCTIWZ = 822, + PPC_FCTIWZo = 823, + PPC_FCTIWo = 824, + PPC_FDIV = 825, + PPC_FDIVS = 826, + PPC_FDIVSo = 827, + PPC_FDIVo = 828, + PPC_FMADD = 829, + PPC_FMADDS = 830, + PPC_FMADDSo = 831, + PPC_FMADDo = 832, + PPC_FMR = 833, + PPC_FMRo = 834, + PPC_FMSUB = 835, + PPC_FMSUBS = 836, + PPC_FMSUBSo = 837, + PPC_FMSUBo = 838, + PPC_FMUL = 839, + PPC_FMULS = 840, + PPC_FMULSo = 841, + PPC_FMULo = 842, + PPC_FNABSD = 843, + PPC_FNABSDo = 844, + PPC_FNABSS = 845, + PPC_FNABSSo = 846, + PPC_FNEGD = 847, + PPC_FNEGDo = 848, + PPC_FNEGS = 849, + PPC_FNEGSo = 850, + PPC_FNMADD = 851, + PPC_FNMADDS = 852, + PPC_FNMADDSo = 853, + PPC_FNMADDo = 854, + PPC_FNMSUB = 855, + PPC_FNMSUBS = 856, + PPC_FNMSUBSo = 857, + PPC_FNMSUBo = 858, + PPC_FRE = 859, + PPC_FRES = 860, + PPC_FRESo = 861, + PPC_FREo = 862, + PPC_FRIMD = 863, + PPC_FRIMDo = 864, + PPC_FRIMS = 865, + PPC_FRIMSo = 866, + PPC_FRIND = 867, + PPC_FRINDo = 868, + PPC_FRINS = 869, + PPC_FRINSo = 870, + PPC_FRIPD = 871, + PPC_FRIPDo = 872, + PPC_FRIPS = 873, + PPC_FRIPSo = 874, + PPC_FRIZD = 875, + PPC_FRIZDo = 876, + PPC_FRIZS = 877, + PPC_FRIZSo = 878, + PPC_FRSP = 879, + PPC_FRSPo = 880, + PPC_FRSQRTE = 881, + PPC_FRSQRTES = 882, + PPC_FRSQRTESo = 883, + PPC_FRSQRTEo = 884, + PPC_FSELD = 885, + PPC_FSELDo = 886, + PPC_FSELS = 887, + PPC_FSELSo = 888, + PPC_FSQRT = 889, + PPC_FSQRTS = 890, + PPC_FSQRTSo = 891, + PPC_FSQRTo = 892, + PPC_FSUB = 893, + PPC_FSUBS = 894, + PPC_FSUBSo = 895, + PPC_FSUBo = 896, + PPC_FTDIV = 897, + PPC_FTSQRT = 898, + PPC_GETtlsADDR = 899, + PPC_GETtlsADDR32 = 900, + PPC_GETtlsldADDR = 901, + PPC_GETtlsldADDR32 = 902, + PPC_HRFID = 903, + PPC_ICBI = 904, + PPC_ICBIEP = 905, + PPC_ICBLC = 906, + PPC_ICBLQ = 907, + PPC_ICBT = 908, + PPC_ICBTLS = 909, + PPC_ICCCI = 910, + PPC_ISEL = 911, + PPC_ISEL8 = 912, + PPC_ISYNC = 913, + PPC_LA = 914, + PPC_LBARX = 915, + PPC_LBARXL = 916, + PPC_LBEPX = 917, + PPC_LBZ = 918, + PPC_LBZ8 = 919, + PPC_LBZCIX = 920, + PPC_LBZU = 921, + PPC_LBZU8 = 922, + PPC_LBZUX = 923, + PPC_LBZUX8 = 924, + PPC_LBZX = 925, + PPC_LBZX8 = 926, + PPC_LBZXTLS = 927, + PPC_LBZXTLS_ = 928, + PPC_LBZXTLS_32 = 929, + PPC_LD = 930, + PPC_LDARX = 931, + PPC_LDARXL = 932, + PPC_LDAT = 933, + PPC_LDBRX = 934, + PPC_LDCIX = 935, + PPC_LDMX = 936, + PPC_LDU = 937, + PPC_LDUX = 938, + PPC_LDX = 939, + PPC_LDXTLS = 940, + PPC_LDXTLS_ = 941, + PPC_LDgotTprelL = 942, + PPC_LDgotTprelL32 = 943, + PPC_LDtoc = 944, + PPC_LDtocBA = 945, + PPC_LDtocCPT = 946, + PPC_LDtocJTI = 947, + PPC_LDtocL = 948, + PPC_LFD = 949, + PPC_LFDEPX = 950, + PPC_LFDU = 951, + PPC_LFDUX = 952, + PPC_LFDX = 953, + PPC_LFIWAX = 954, + PPC_LFIWZX = 955, + PPC_LFS = 956, + PPC_LFSU = 957, + PPC_LFSUX = 958, + PPC_LFSX = 959, + PPC_LHA = 960, + PPC_LHA8 = 961, + PPC_LHARX = 962, + PPC_LHARXL = 963, + PPC_LHAU = 964, + PPC_LHAU8 = 965, + PPC_LHAUX = 966, + PPC_LHAUX8 = 967, + PPC_LHAX = 968, + PPC_LHAX8 = 969, + PPC_LHBRX = 970, + PPC_LHBRX8 = 971, + PPC_LHEPX = 972, + PPC_LHZ = 973, + PPC_LHZ8 = 974, + PPC_LHZCIX = 975, + PPC_LHZU = 976, + PPC_LHZU8 = 977, + PPC_LHZUX = 978, + PPC_LHZUX8 = 979, + PPC_LHZX = 980, + PPC_LHZX8 = 981, + PPC_LHZXTLS = 982, + PPC_LHZXTLS_ = 983, + PPC_LHZXTLS_32 = 984, + PPC_LI = 985, + PPC_LI8 = 986, + PPC_LIS = 987, + PPC_LIS8 = 988, + PPC_LMW = 989, + PPC_LSWI = 990, + PPC_LVEBX = 991, + PPC_LVEHX = 992, + PPC_LVEWX = 993, + PPC_LVSL = 994, + PPC_LVSR = 995, + PPC_LVX = 996, + PPC_LVXL = 997, + PPC_LWA = 998, + PPC_LWARX = 999, + PPC_LWARXL = 1000, + PPC_LWAT = 1001, + PPC_LWAUX = 1002, + PPC_LWAX = 1003, + PPC_LWAX_32 = 1004, + PPC_LWA_32 = 1005, + PPC_LWBRX = 1006, + PPC_LWBRX8 = 1007, + PPC_LWEPX = 1008, + PPC_LWZ = 1009, + PPC_LWZ8 = 1010, + PPC_LWZCIX = 1011, + PPC_LWZU = 1012, + PPC_LWZU8 = 1013, + PPC_LWZUX = 1014, + PPC_LWZUX8 = 1015, + PPC_LWZX = 1016, + PPC_LWZX8 = 1017, + PPC_LWZXTLS = 1018, + PPC_LWZXTLS_ = 1019, + PPC_LWZXTLS_32 = 1020, + PPC_LWZtoc = 1021, + PPC_LXSD = 1022, + PPC_LXSDX = 1023, + PPC_LXSIBZX = 1024, + PPC_LXSIHZX = 1025, + PPC_LXSIWAX = 1026, + PPC_LXSIWZX = 1027, + PPC_LXSSP = 1028, + PPC_LXSSPX = 1029, + PPC_LXV = 1030, + PPC_LXVB16X = 1031, + PPC_LXVD2X = 1032, + PPC_LXVDSX = 1033, + PPC_LXVH8X = 1034, + PPC_LXVL = 1035, + PPC_LXVLL = 1036, + PPC_LXVW4X = 1037, + PPC_LXVWSX = 1038, + PPC_LXVX = 1039, + PPC_MADDHD = 1040, + PPC_MADDHDU = 1041, + PPC_MADDLD = 1042, + PPC_MBAR = 1043, + PPC_MCRF = 1044, + PPC_MCRFS = 1045, + PPC_MCRXRX = 1046, + PPC_MFBHRBE = 1047, + PPC_MFCR = 1048, + PPC_MFCR8 = 1049, + PPC_MFCTR = 1050, + PPC_MFCTR8 = 1051, + PPC_MFDCR = 1052, + PPC_MFFS = 1053, + PPC_MFFSCDRN = 1054, + PPC_MFFSCDRNI = 1055, + PPC_MFFSCE = 1056, + PPC_MFFSCRN = 1057, + PPC_MFFSCRNI = 1058, + PPC_MFFSL = 1059, + PPC_MFFSo = 1060, + PPC_MFLR = 1061, + PPC_MFLR8 = 1062, + PPC_MFMSR = 1063, + PPC_MFOCRF = 1064, + PPC_MFOCRF8 = 1065, + PPC_MFPMR = 1066, + PPC_MFSPR = 1067, + PPC_MFSPR8 = 1068, + PPC_MFSR = 1069, + PPC_MFSRIN = 1070, + PPC_MFTB = 1071, + PPC_MFTB8 = 1072, + PPC_MFVRD = 1073, + PPC_MFVRSAVE = 1074, + PPC_MFVRSAVEv = 1075, + PPC_MFVSCR = 1076, + PPC_MFVSRD = 1077, + PPC_MFVSRLD = 1078, + PPC_MFVSRWZ = 1079, + PPC_MODSD = 1080, + PPC_MODSW = 1081, + PPC_MODUD = 1082, + PPC_MODUW = 1083, + PPC_MSGSYNC = 1084, + PPC_MSYNC = 1085, + PPC_MTCRF = 1086, + PPC_MTCRF8 = 1087, + PPC_MTCTR = 1088, + PPC_MTCTR8 = 1089, + PPC_MTCTR8loop = 1090, + PPC_MTCTRloop = 1091, + PPC_MTDCR = 1092, + PPC_MTFSB0 = 1093, + PPC_MTFSB1 = 1094, + PPC_MTFSF = 1095, + PPC_MTFSFI = 1096, + PPC_MTFSFIo = 1097, + PPC_MTFSFb = 1098, + PPC_MTFSFo = 1099, + PPC_MTLR = 1100, + PPC_MTLR8 = 1101, + PPC_MTMSR = 1102, + PPC_MTMSRD = 1103, + PPC_MTOCRF = 1104, + PPC_MTOCRF8 = 1105, + PPC_MTPMR = 1106, + PPC_MTSPR = 1107, + PPC_MTSPR8 = 1108, + PPC_MTSR = 1109, + PPC_MTSRIN = 1110, + PPC_MTVRSAVE = 1111, + PPC_MTVRSAVEv = 1112, + PPC_MTVSCR = 1113, + PPC_MTVSRD = 1114, + PPC_MTVSRDD = 1115, + PPC_MTVSRWA = 1116, + PPC_MTVSRWS = 1117, + PPC_MTVSRWZ = 1118, + PPC_MULHD = 1119, + PPC_MULHDU = 1120, + PPC_MULHDUo = 1121, + PPC_MULHDo = 1122, + PPC_MULHW = 1123, + PPC_MULHWU = 1124, + PPC_MULHWUo = 1125, + PPC_MULHWo = 1126, + PPC_MULLD = 1127, + PPC_MULLDo = 1128, + PPC_MULLI = 1129, + PPC_MULLI8 = 1130, + PPC_MULLW = 1131, + PPC_MULLWo = 1132, + PPC_MoveGOTtoLR = 1133, + PPC_MovePCtoLR = 1134, + PPC_MovePCtoLR8 = 1135, + PPC_NAND = 1136, + PPC_NAND8 = 1137, + PPC_NAND8o = 1138, + PPC_NANDo = 1139, + PPC_NAP = 1140, + PPC_NEG = 1141, + PPC_NEG8 = 1142, + PPC_NEG8o = 1143, + PPC_NEGo = 1144, + PPC_NOP = 1145, + PPC_NOP_GT_PWR6 = 1146, + PPC_NOP_GT_PWR7 = 1147, + PPC_NOR = 1148, + PPC_NOR8 = 1149, + PPC_NOR8o = 1150, + PPC_NORo = 1151, + PPC_OR = 1152, + PPC_OR8 = 1153, + PPC_OR8o = 1154, + PPC_ORC = 1155, + PPC_ORC8 = 1156, + PPC_ORC8o = 1157, + PPC_ORCo = 1158, + PPC_ORI = 1159, + PPC_ORI8 = 1160, + PPC_ORIS = 1161, + PPC_ORIS8 = 1162, + PPC_ORo = 1163, + PPC_POPCNTB = 1164, + PPC_POPCNTD = 1165, + PPC_POPCNTW = 1166, + PPC_PPC32GOT = 1167, + PPC_PPC32PICGOT = 1168, + PPC_QVALIGNI = 1169, + PPC_QVALIGNIb = 1170, + PPC_QVALIGNIs = 1171, + PPC_QVESPLATI = 1172, + PPC_QVESPLATIb = 1173, + PPC_QVESPLATIs = 1174, + PPC_QVFABS = 1175, + PPC_QVFABSs = 1176, + PPC_QVFADD = 1177, + PPC_QVFADDS = 1178, + PPC_QVFADDSs = 1179, + PPC_QVFCFID = 1180, + PPC_QVFCFIDS = 1181, + PPC_QVFCFIDU = 1182, + PPC_QVFCFIDUS = 1183, + PPC_QVFCFIDb = 1184, + PPC_QVFCMPEQ = 1185, + PPC_QVFCMPEQb = 1186, + PPC_QVFCMPEQbs = 1187, + PPC_QVFCMPGT = 1188, + PPC_QVFCMPGTb = 1189, + PPC_QVFCMPGTbs = 1190, + PPC_QVFCMPLT = 1191, + PPC_QVFCMPLTb = 1192, + PPC_QVFCMPLTbs = 1193, + PPC_QVFCPSGN = 1194, + PPC_QVFCPSGNs = 1195, + PPC_QVFCTID = 1196, + PPC_QVFCTIDU = 1197, + PPC_QVFCTIDUZ = 1198, + PPC_QVFCTIDZ = 1199, + PPC_QVFCTIDb = 1200, + PPC_QVFCTIW = 1201, + PPC_QVFCTIWU = 1202, + PPC_QVFCTIWUZ = 1203, + PPC_QVFCTIWZ = 1204, + PPC_QVFLOGICAL = 1205, + PPC_QVFLOGICALb = 1206, + PPC_QVFLOGICALs = 1207, + PPC_QVFMADD = 1208, + PPC_QVFMADDS = 1209, + PPC_QVFMADDSs = 1210, + PPC_QVFMR = 1211, + PPC_QVFMRb = 1212, + PPC_QVFMRs = 1213, + PPC_QVFMSUB = 1214, + PPC_QVFMSUBS = 1215, + PPC_QVFMSUBSs = 1216, + PPC_QVFMUL = 1217, + PPC_QVFMULS = 1218, + PPC_QVFMULSs = 1219, + PPC_QVFNABS = 1220, + PPC_QVFNABSs = 1221, + PPC_QVFNEG = 1222, + PPC_QVFNEGs = 1223, + PPC_QVFNMADD = 1224, + PPC_QVFNMADDS = 1225, + PPC_QVFNMADDSs = 1226, + PPC_QVFNMSUB = 1227, + PPC_QVFNMSUBS = 1228, + PPC_QVFNMSUBSs = 1229, + PPC_QVFPERM = 1230, + PPC_QVFPERMs = 1231, + PPC_QVFRE = 1232, + PPC_QVFRES = 1233, + PPC_QVFRESs = 1234, + PPC_QVFRIM = 1235, + PPC_QVFRIMs = 1236, + PPC_QVFRIN = 1237, + PPC_QVFRINs = 1238, + PPC_QVFRIP = 1239, + PPC_QVFRIPs = 1240, + PPC_QVFRIZ = 1241, + PPC_QVFRIZs = 1242, + PPC_QVFRSP = 1243, + PPC_QVFRSPs = 1244, + PPC_QVFRSQRTE = 1245, + PPC_QVFRSQRTES = 1246, + PPC_QVFRSQRTESs = 1247, + PPC_QVFSEL = 1248, + PPC_QVFSELb = 1249, + PPC_QVFSELbb = 1250, + PPC_QVFSELbs = 1251, + PPC_QVFSUB = 1252, + PPC_QVFSUBS = 1253, + PPC_QVFSUBSs = 1254, + PPC_QVFTSTNAN = 1255, + PPC_QVFTSTNANb = 1256, + PPC_QVFTSTNANbs = 1257, + PPC_QVFXMADD = 1258, + PPC_QVFXMADDS = 1259, + PPC_QVFXMUL = 1260, + PPC_QVFXMULS = 1261, + PPC_QVFXXCPNMADD = 1262, + PPC_QVFXXCPNMADDS = 1263, + PPC_QVFXXMADD = 1264, + PPC_QVFXXMADDS = 1265, + PPC_QVFXXNPMADD = 1266, + PPC_QVFXXNPMADDS = 1267, + PPC_QVGPCI = 1268, + PPC_QVLFCDUX = 1269, + PPC_QVLFCDUXA = 1270, + PPC_QVLFCDX = 1271, + PPC_QVLFCDXA = 1272, + PPC_QVLFCSUX = 1273, + PPC_QVLFCSUXA = 1274, + PPC_QVLFCSX = 1275, + PPC_QVLFCSXA = 1276, + PPC_QVLFCSXs = 1277, + PPC_QVLFDUX = 1278, + PPC_QVLFDUXA = 1279, + PPC_QVLFDX = 1280, + PPC_QVLFDXA = 1281, + PPC_QVLFDXb = 1282, + PPC_QVLFIWAX = 1283, + PPC_QVLFIWAXA = 1284, + PPC_QVLFIWZX = 1285, + PPC_QVLFIWZXA = 1286, + PPC_QVLFSUX = 1287, + PPC_QVLFSUXA = 1288, + PPC_QVLFSX = 1289, + PPC_QVLFSXA = 1290, + PPC_QVLFSXb = 1291, + PPC_QVLFSXs = 1292, + PPC_QVLPCLDX = 1293, + PPC_QVLPCLSX = 1294, + PPC_QVLPCLSXint = 1295, + PPC_QVLPCRDX = 1296, + PPC_QVLPCRSX = 1297, + PPC_QVSTFCDUX = 1298, + PPC_QVSTFCDUXA = 1299, + PPC_QVSTFCDUXI = 1300, + PPC_QVSTFCDUXIA = 1301, + PPC_QVSTFCDX = 1302, + PPC_QVSTFCDXA = 1303, + PPC_QVSTFCDXI = 1304, + PPC_QVSTFCDXIA = 1305, + PPC_QVSTFCSUX = 1306, + PPC_QVSTFCSUXA = 1307, + PPC_QVSTFCSUXI = 1308, + PPC_QVSTFCSUXIA = 1309, + PPC_QVSTFCSX = 1310, + PPC_QVSTFCSXA = 1311, + PPC_QVSTFCSXI = 1312, + PPC_QVSTFCSXIA = 1313, + PPC_QVSTFCSXs = 1314, + PPC_QVSTFDUX = 1315, + PPC_QVSTFDUXA = 1316, + PPC_QVSTFDUXI = 1317, + PPC_QVSTFDUXIA = 1318, + PPC_QVSTFDX = 1319, + PPC_QVSTFDXA = 1320, + PPC_QVSTFDXI = 1321, + PPC_QVSTFDXIA = 1322, + PPC_QVSTFDXb = 1323, + PPC_QVSTFIWX = 1324, + PPC_QVSTFIWXA = 1325, + PPC_QVSTFSUX = 1326, + PPC_QVSTFSUXA = 1327, + PPC_QVSTFSUXI = 1328, + PPC_QVSTFSUXIA = 1329, + PPC_QVSTFSUXs = 1330, + PPC_QVSTFSX = 1331, + PPC_QVSTFSXA = 1332, + PPC_QVSTFSXI = 1333, + PPC_QVSTFSXIA = 1334, + PPC_QVSTFSXs = 1335, + PPC_RESTORE_CR = 1336, + PPC_RESTORE_CRBIT = 1337, + PPC_RESTORE_VRSAVE = 1338, + PPC_RFCI = 1339, + PPC_RFDI = 1340, + PPC_RFEBB = 1341, + PPC_RFI = 1342, + PPC_RFID = 1343, + PPC_RFMCI = 1344, + PPC_RLDCL = 1345, + PPC_RLDCLo = 1346, + PPC_RLDCR = 1347, + PPC_RLDCRo = 1348, + PPC_RLDIC = 1349, + PPC_RLDICL = 1350, + PPC_RLDICL_32 = 1351, + PPC_RLDICL_32_64 = 1352, + PPC_RLDICL_32o = 1353, + PPC_RLDICLo = 1354, + PPC_RLDICR = 1355, + PPC_RLDICR_32 = 1356, + PPC_RLDICRo = 1357, + PPC_RLDICo = 1358, + PPC_RLDIMI = 1359, + PPC_RLDIMIo = 1360, + PPC_RLWIMI = 1361, + PPC_RLWIMI8 = 1362, + PPC_RLWIMI8o = 1363, + PPC_RLWIMIo = 1364, + PPC_RLWINM = 1365, + PPC_RLWINM8 = 1366, + PPC_RLWINM8o = 1367, + PPC_RLWINMo = 1368, + PPC_RLWNM = 1369, + PPC_RLWNM8 = 1370, + PPC_RLWNM8o = 1371, + PPC_RLWNMo = 1372, + PPC_ReadTB = 1373, + PPC_SC = 1374, + PPC_SELECT_CC_F16 = 1375, + PPC_SELECT_CC_F4 = 1376, + PPC_SELECT_CC_F8 = 1377, + PPC_SELECT_CC_I4 = 1378, + PPC_SELECT_CC_I8 = 1379, + PPC_SELECT_CC_QBRC = 1380, + PPC_SELECT_CC_QFRC = 1381, + PPC_SELECT_CC_QSRC = 1382, + PPC_SELECT_CC_SPE = 1383, + PPC_SELECT_CC_SPE4 = 1384, + PPC_SELECT_CC_VRRC = 1385, + PPC_SELECT_CC_VSFRC = 1386, + PPC_SELECT_CC_VSRC = 1387, + PPC_SELECT_CC_VSSRC = 1388, + PPC_SELECT_F16 = 1389, + PPC_SELECT_F4 = 1390, + PPC_SELECT_F8 = 1391, + PPC_SELECT_I4 = 1392, + PPC_SELECT_I8 = 1393, + PPC_SELECT_QBRC = 1394, + PPC_SELECT_QFRC = 1395, + PPC_SELECT_QSRC = 1396, + PPC_SELECT_SPE = 1397, + PPC_SELECT_SPE4 = 1398, + PPC_SELECT_VRRC = 1399, + PPC_SELECT_VSFRC = 1400, + PPC_SELECT_VSRC = 1401, + PPC_SELECT_VSSRC = 1402, + PPC_SETB = 1403, + PPC_SLBIA = 1404, + PPC_SLBIE = 1405, + PPC_SLBIEG = 1406, + PPC_SLBMFEE = 1407, + PPC_SLBMFEV = 1408, + PPC_SLBMTE = 1409, + PPC_SLBSYNC = 1410, + PPC_SLD = 1411, + PPC_SLDo = 1412, + PPC_SLW = 1413, + PPC_SLW8 = 1414, + PPC_SLW8o = 1415, + PPC_SLWo = 1416, + PPC_SPELWZ = 1417, + PPC_SPELWZX = 1418, + PPC_SPESTW = 1419, + PPC_SPESTWX = 1420, + PPC_SPILL_CR = 1421, + PPC_SPILL_CRBIT = 1422, + PPC_SPILL_VRSAVE = 1423, + PPC_SRAD = 1424, + PPC_SRADI = 1425, + PPC_SRADI_32 = 1426, + PPC_SRADIo = 1427, + PPC_SRADo = 1428, + PPC_SRAW = 1429, + PPC_SRAWI = 1430, + PPC_SRAWIo = 1431, + PPC_SRAWo = 1432, + PPC_SRD = 1433, + PPC_SRDo = 1434, + PPC_SRW = 1435, + PPC_SRW8 = 1436, + PPC_SRW8o = 1437, + PPC_SRWo = 1438, + PPC_STB = 1439, + PPC_STB8 = 1440, + PPC_STBCIX = 1441, + PPC_STBCX = 1442, + PPC_STBEPX = 1443, + PPC_STBU = 1444, + PPC_STBU8 = 1445, + PPC_STBUX = 1446, + PPC_STBUX8 = 1447, + PPC_STBX = 1448, + PPC_STBX8 = 1449, + PPC_STBXTLS = 1450, + PPC_STBXTLS_ = 1451, + PPC_STBXTLS_32 = 1452, + PPC_STD = 1453, + PPC_STDAT = 1454, + PPC_STDBRX = 1455, + PPC_STDCIX = 1456, + PPC_STDCX = 1457, + PPC_STDU = 1458, + PPC_STDUX = 1459, + PPC_STDX = 1460, + PPC_STDXTLS = 1461, + PPC_STDXTLS_ = 1462, + PPC_STFD = 1463, + PPC_STFDEPX = 1464, + PPC_STFDU = 1465, + PPC_STFDUX = 1466, + PPC_STFDX = 1467, + PPC_STFIWX = 1468, + PPC_STFS = 1469, + PPC_STFSU = 1470, + PPC_STFSUX = 1471, + PPC_STFSX = 1472, + PPC_STH = 1473, + PPC_STH8 = 1474, + PPC_STHBRX = 1475, + PPC_STHCIX = 1476, + PPC_STHCX = 1477, + PPC_STHEPX = 1478, + PPC_STHU = 1479, + PPC_STHU8 = 1480, + PPC_STHUX = 1481, + PPC_STHUX8 = 1482, + PPC_STHX = 1483, + PPC_STHX8 = 1484, + PPC_STHXTLS = 1485, + PPC_STHXTLS_ = 1486, + PPC_STHXTLS_32 = 1487, + PPC_STMW = 1488, + PPC_STOP = 1489, + PPC_STSWI = 1490, + PPC_STVEBX = 1491, + PPC_STVEHX = 1492, + PPC_STVEWX = 1493, + PPC_STVX = 1494, + PPC_STVXL = 1495, + PPC_STW = 1496, + PPC_STW8 = 1497, + PPC_STWAT = 1498, + PPC_STWBRX = 1499, + PPC_STWCIX = 1500, + PPC_STWCX = 1501, + PPC_STWEPX = 1502, + PPC_STWU = 1503, + PPC_STWU8 = 1504, + PPC_STWUX = 1505, + PPC_STWUX8 = 1506, + PPC_STWX = 1507, + PPC_STWX8 = 1508, + PPC_STWXTLS = 1509, + PPC_STWXTLS_ = 1510, + PPC_STWXTLS_32 = 1511, + PPC_STXSD = 1512, + PPC_STXSDX = 1513, + PPC_STXSIBX = 1514, + PPC_STXSIBXv = 1515, + PPC_STXSIHX = 1516, + PPC_STXSIHXv = 1517, + PPC_STXSIWX = 1518, + PPC_STXSSP = 1519, + PPC_STXSSPX = 1520, + PPC_STXV = 1521, + PPC_STXVB16X = 1522, + PPC_STXVD2X = 1523, + PPC_STXVH8X = 1524, + PPC_STXVL = 1525, + PPC_STXVLL = 1526, + PPC_STXVW4X = 1527, + PPC_STXVX = 1528, + PPC_SUBF = 1529, + PPC_SUBF8 = 1530, + PPC_SUBF8o = 1531, + PPC_SUBFC = 1532, + PPC_SUBFC8 = 1533, + PPC_SUBFC8o = 1534, + PPC_SUBFCo = 1535, + PPC_SUBFE = 1536, + PPC_SUBFE8 = 1537, + PPC_SUBFE8o = 1538, + PPC_SUBFEo = 1539, + PPC_SUBFIC = 1540, + PPC_SUBFIC8 = 1541, + PPC_SUBFME = 1542, + PPC_SUBFME8 = 1543, + PPC_SUBFME8o = 1544, + PPC_SUBFMEo = 1545, + PPC_SUBFZE = 1546, + PPC_SUBFZE8 = 1547, + PPC_SUBFZE8o = 1548, + PPC_SUBFZEo = 1549, + PPC_SUBFo = 1550, + PPC_SYNC = 1551, + PPC_TABORT = 1552, + PPC_TABORTDC = 1553, + PPC_TABORTDCI = 1554, + PPC_TABORTWC = 1555, + PPC_TABORTWCI = 1556, + PPC_TAILB = 1557, + PPC_TAILB8 = 1558, + PPC_TAILBA = 1559, + PPC_TAILBA8 = 1560, + PPC_TAILBCTR = 1561, + PPC_TAILBCTR8 = 1562, + PPC_TBEGIN = 1563, + PPC_TCHECK = 1564, + PPC_TCHECK_RET = 1565, + PPC_TCRETURNai = 1566, + PPC_TCRETURNai8 = 1567, + PPC_TCRETURNdi = 1568, + PPC_TCRETURNdi8 = 1569, + PPC_TCRETURNri = 1570, + PPC_TCRETURNri8 = 1571, + PPC_TD = 1572, + PPC_TDI = 1573, + PPC_TEND = 1574, + PPC_TLBIA = 1575, + PPC_TLBIE = 1576, + PPC_TLBIEL = 1577, + PPC_TLBIVAX = 1578, + PPC_TLBLD = 1579, + PPC_TLBLI = 1580, + PPC_TLBRE = 1581, + PPC_TLBRE2 = 1582, + PPC_TLBSX = 1583, + PPC_TLBSX2 = 1584, + PPC_TLBSX2D = 1585, + PPC_TLBSYNC = 1586, + PPC_TLBWE = 1587, + PPC_TLBWE2 = 1588, + PPC_TRAP = 1589, + PPC_TRECHKPT = 1590, + PPC_TRECLAIM = 1591, + PPC_TSR = 1592, + PPC_TW = 1593, + PPC_TWI = 1594, + PPC_UPDATE_VRSAVE = 1595, + PPC_UpdateGBR = 1596, + PPC_VABSDUB = 1597, + PPC_VABSDUH = 1598, + PPC_VABSDUW = 1599, + PPC_VADDCUQ = 1600, + PPC_VADDCUW = 1601, + PPC_VADDECUQ = 1602, + PPC_VADDEUQM = 1603, + PPC_VADDFP = 1604, + PPC_VADDSBS = 1605, + PPC_VADDSHS = 1606, + PPC_VADDSWS = 1607, + PPC_VADDUBM = 1608, + PPC_VADDUBS = 1609, + PPC_VADDUDM = 1610, + PPC_VADDUHM = 1611, + PPC_VADDUHS = 1612, + PPC_VADDUQM = 1613, + PPC_VADDUWM = 1614, + PPC_VADDUWS = 1615, + PPC_VAND = 1616, + PPC_VANDC = 1617, + PPC_VAVGSB = 1618, + PPC_VAVGSH = 1619, + PPC_VAVGSW = 1620, + PPC_VAVGUB = 1621, + PPC_VAVGUH = 1622, + PPC_VAVGUW = 1623, + PPC_VBPERMD = 1624, + PPC_VBPERMQ = 1625, + PPC_VCFSX = 1626, + PPC_VCFSX_0 = 1627, + PPC_VCFUX = 1628, + PPC_VCFUX_0 = 1629, + PPC_VCIPHER = 1630, + PPC_VCIPHERLAST = 1631, + PPC_VCLZB = 1632, + PPC_VCLZD = 1633, + PPC_VCLZH = 1634, + PPC_VCLZLSBB = 1635, + PPC_VCLZW = 1636, + PPC_VCMPBFP = 1637, + PPC_VCMPBFPo = 1638, + PPC_VCMPEQFP = 1639, + PPC_VCMPEQFPo = 1640, + PPC_VCMPEQUB = 1641, + PPC_VCMPEQUBo = 1642, + PPC_VCMPEQUD = 1643, + PPC_VCMPEQUDo = 1644, + PPC_VCMPEQUH = 1645, + PPC_VCMPEQUHo = 1646, + PPC_VCMPEQUW = 1647, + PPC_VCMPEQUWo = 1648, + PPC_VCMPGEFP = 1649, + PPC_VCMPGEFPo = 1650, + PPC_VCMPGTFP = 1651, + PPC_VCMPGTFPo = 1652, + PPC_VCMPGTSB = 1653, + PPC_VCMPGTSBo = 1654, + PPC_VCMPGTSD = 1655, + PPC_VCMPGTSDo = 1656, + PPC_VCMPGTSH = 1657, + PPC_VCMPGTSHo = 1658, + PPC_VCMPGTSW = 1659, + PPC_VCMPGTSWo = 1660, + PPC_VCMPGTUB = 1661, + PPC_VCMPGTUBo = 1662, + PPC_VCMPGTUD = 1663, + PPC_VCMPGTUDo = 1664, + PPC_VCMPGTUH = 1665, + PPC_VCMPGTUHo = 1666, + PPC_VCMPGTUW = 1667, + PPC_VCMPGTUWo = 1668, + PPC_VCMPNEB = 1669, + PPC_VCMPNEBo = 1670, + PPC_VCMPNEH = 1671, + PPC_VCMPNEHo = 1672, + PPC_VCMPNEW = 1673, + PPC_VCMPNEWo = 1674, + PPC_VCMPNEZB = 1675, + PPC_VCMPNEZBo = 1676, + PPC_VCMPNEZH = 1677, + PPC_VCMPNEZHo = 1678, + PPC_VCMPNEZW = 1679, + PPC_VCMPNEZWo = 1680, + PPC_VCTSXS = 1681, + PPC_VCTSXS_0 = 1682, + PPC_VCTUXS = 1683, + PPC_VCTUXS_0 = 1684, + PPC_VCTZB = 1685, + PPC_VCTZD = 1686, + PPC_VCTZH = 1687, + PPC_VCTZLSBB = 1688, + PPC_VCTZW = 1689, + PPC_VEQV = 1690, + PPC_VEXPTEFP = 1691, + PPC_VEXTRACTD = 1692, + PPC_VEXTRACTUB = 1693, + PPC_VEXTRACTUH = 1694, + PPC_VEXTRACTUW = 1695, + PPC_VEXTSB2D = 1696, + PPC_VEXTSB2Ds = 1697, + PPC_VEXTSB2W = 1698, + PPC_VEXTSB2Ws = 1699, + PPC_VEXTSH2D = 1700, + PPC_VEXTSH2Ds = 1701, + PPC_VEXTSH2W = 1702, + PPC_VEXTSH2Ws = 1703, + PPC_VEXTSW2D = 1704, + PPC_VEXTSW2Ds = 1705, + PPC_VEXTUBLX = 1706, + PPC_VEXTUBRX = 1707, + PPC_VEXTUHLX = 1708, + PPC_VEXTUHRX = 1709, + PPC_VEXTUWLX = 1710, + PPC_VEXTUWRX = 1711, + PPC_VGBBD = 1712, + PPC_VINSERTB = 1713, + PPC_VINSERTD = 1714, + PPC_VINSERTH = 1715, + PPC_VINSERTW = 1716, + PPC_VLOGEFP = 1717, + PPC_VMADDFP = 1718, + PPC_VMAXFP = 1719, + PPC_VMAXSB = 1720, + PPC_VMAXSD = 1721, + PPC_VMAXSH = 1722, + PPC_VMAXSW = 1723, + PPC_VMAXUB = 1724, + PPC_VMAXUD = 1725, + PPC_VMAXUH = 1726, + PPC_VMAXUW = 1727, + PPC_VMHADDSHS = 1728, + PPC_VMHRADDSHS = 1729, + PPC_VMINFP = 1730, + PPC_VMINSB = 1731, + PPC_VMINSD = 1732, + PPC_VMINSH = 1733, + PPC_VMINSW = 1734, + PPC_VMINUB = 1735, + PPC_VMINUD = 1736, + PPC_VMINUH = 1737, + PPC_VMINUW = 1738, + PPC_VMLADDUHM = 1739, + PPC_VMRGEW = 1740, + PPC_VMRGHB = 1741, + PPC_VMRGHH = 1742, + PPC_VMRGHW = 1743, + PPC_VMRGLB = 1744, + PPC_VMRGLH = 1745, + PPC_VMRGLW = 1746, + PPC_VMRGOW = 1747, + PPC_VMSUMMBM = 1748, + PPC_VMSUMSHM = 1749, + PPC_VMSUMSHS = 1750, + PPC_VMSUMUBM = 1751, + PPC_VMSUMUHM = 1752, + PPC_VMSUMUHS = 1753, + PPC_VMUL10CUQ = 1754, + PPC_VMUL10ECUQ = 1755, + PPC_VMUL10EUQ = 1756, + PPC_VMUL10UQ = 1757, + PPC_VMULESB = 1758, + PPC_VMULESH = 1759, + PPC_VMULESW = 1760, + PPC_VMULEUB = 1761, + PPC_VMULEUH = 1762, + PPC_VMULEUW = 1763, + PPC_VMULOSB = 1764, + PPC_VMULOSH = 1765, + PPC_VMULOSW = 1766, + PPC_VMULOUB = 1767, + PPC_VMULOUH = 1768, + PPC_VMULOUW = 1769, + PPC_VMULUWM = 1770, + PPC_VNAND = 1771, + PPC_VNCIPHER = 1772, + PPC_VNCIPHERLAST = 1773, + PPC_VNEGD = 1774, + PPC_VNEGW = 1775, + PPC_VNMSUBFP = 1776, + PPC_VNOR = 1777, + PPC_VOR = 1778, + PPC_VORC = 1779, + PPC_VPERM = 1780, + PPC_VPERMR = 1781, + PPC_VPERMXOR = 1782, + PPC_VPKPX = 1783, + PPC_VPKSDSS = 1784, + PPC_VPKSDUS = 1785, + PPC_VPKSHSS = 1786, + PPC_VPKSHUS = 1787, + PPC_VPKSWSS = 1788, + PPC_VPKSWUS = 1789, + PPC_VPKUDUM = 1790, + PPC_VPKUDUS = 1791, + PPC_VPKUHUM = 1792, + PPC_VPKUHUS = 1793, + PPC_VPKUWUM = 1794, + PPC_VPKUWUS = 1795, + PPC_VPMSUMB = 1796, + PPC_VPMSUMD = 1797, + PPC_VPMSUMH = 1798, + PPC_VPMSUMW = 1799, + PPC_VPOPCNTB = 1800, + PPC_VPOPCNTD = 1801, + PPC_VPOPCNTH = 1802, + PPC_VPOPCNTW = 1803, + PPC_VPRTYBD = 1804, + PPC_VPRTYBQ = 1805, + PPC_VPRTYBW = 1806, + PPC_VREFP = 1807, + PPC_VRFIM = 1808, + PPC_VRFIN = 1809, + PPC_VRFIP = 1810, + PPC_VRFIZ = 1811, + PPC_VRLB = 1812, + PPC_VRLD = 1813, + PPC_VRLDMI = 1814, + PPC_VRLDNM = 1815, + PPC_VRLH = 1816, + PPC_VRLW = 1817, + PPC_VRLWMI = 1818, + PPC_VRLWNM = 1819, + PPC_VRSQRTEFP = 1820, + PPC_VSBOX = 1821, + PPC_VSEL = 1822, + PPC_VSHASIGMAD = 1823, + PPC_VSHASIGMAW = 1824, + PPC_VSL = 1825, + PPC_VSLB = 1826, + PPC_VSLD = 1827, + PPC_VSLDOI = 1828, + PPC_VSLH = 1829, + PPC_VSLO = 1830, + PPC_VSLV = 1831, + PPC_VSLW = 1832, + PPC_VSPLTB = 1833, + PPC_VSPLTBs = 1834, + PPC_VSPLTH = 1835, + PPC_VSPLTHs = 1836, + PPC_VSPLTISB = 1837, + PPC_VSPLTISH = 1838, + PPC_VSPLTISW = 1839, + PPC_VSPLTW = 1840, + PPC_VSR = 1841, + PPC_VSRAB = 1842, + PPC_VSRAD = 1843, + PPC_VSRAH = 1844, + PPC_VSRAW = 1845, + PPC_VSRB = 1846, + PPC_VSRD = 1847, + PPC_VSRH = 1848, + PPC_VSRO = 1849, + PPC_VSRV = 1850, + PPC_VSRW = 1851, + PPC_VSUBCUQ = 1852, + PPC_VSUBCUW = 1853, + PPC_VSUBECUQ = 1854, + PPC_VSUBEUQM = 1855, + PPC_VSUBFP = 1856, + PPC_VSUBSBS = 1857, + PPC_VSUBSHS = 1858, + PPC_VSUBSWS = 1859, + PPC_VSUBUBM = 1860, + PPC_VSUBUBS = 1861, + PPC_VSUBUDM = 1862, + PPC_VSUBUHM = 1863, + PPC_VSUBUHS = 1864, + PPC_VSUBUQM = 1865, + PPC_VSUBUWM = 1866, + PPC_VSUBUWS = 1867, + PPC_VSUM2SWS = 1868, + PPC_VSUM4SBS = 1869, + PPC_VSUM4SHS = 1870, + PPC_VSUM4UBS = 1871, + PPC_VSUMSWS = 1872, + PPC_VUPKHPX = 1873, + PPC_VUPKHSB = 1874, + PPC_VUPKHSH = 1875, + PPC_VUPKHSW = 1876, + PPC_VUPKLPX = 1877, + PPC_VUPKLSB = 1878, + PPC_VUPKLSH = 1879, + PPC_VUPKLSW = 1880, + PPC_VXOR = 1881, + PPC_V_SET0 = 1882, + PPC_V_SET0B = 1883, + PPC_V_SET0H = 1884, + PPC_V_SETALLONES = 1885, + PPC_V_SETALLONESB = 1886, + PPC_V_SETALLONESH = 1887, + PPC_WAIT = 1888, + PPC_WRTEE = 1889, + PPC_WRTEEI = 1890, + PPC_XOR = 1891, + PPC_XOR8 = 1892, + PPC_XOR8o = 1893, + PPC_XORI = 1894, + PPC_XORI8 = 1895, + PPC_XORIS = 1896, + PPC_XORIS8 = 1897, + PPC_XORo = 1898, + PPC_XSABSDP = 1899, + PPC_XSABSQP = 1900, + PPC_XSADDDP = 1901, + PPC_XSADDQP = 1902, + PPC_XSADDQPO = 1903, + PPC_XSADDSP = 1904, + PPC_XSCMPEQDP = 1905, + PPC_XSCMPEXPDP = 1906, + PPC_XSCMPEXPQP = 1907, + PPC_XSCMPGEDP = 1908, + PPC_XSCMPGTDP = 1909, + PPC_XSCMPODP = 1910, + PPC_XSCMPOQP = 1911, + PPC_XSCMPUDP = 1912, + PPC_XSCMPUQP = 1913, + PPC_XSCPSGNDP = 1914, + PPC_XSCPSGNQP = 1915, + PPC_XSCVDPHP = 1916, + PPC_XSCVDPQP = 1917, + PPC_XSCVDPSP = 1918, + PPC_XSCVDPSPN = 1919, + PPC_XSCVDPSXDS = 1920, + PPC_XSCVDPSXDSs = 1921, + PPC_XSCVDPSXWS = 1922, + PPC_XSCVDPSXWSs = 1923, + PPC_XSCVDPUXDS = 1924, + PPC_XSCVDPUXDSs = 1925, + PPC_XSCVDPUXWS = 1926, + PPC_XSCVDPUXWSs = 1927, + PPC_XSCVHPDP = 1928, + PPC_XSCVQPDP = 1929, + PPC_XSCVQPDPO = 1930, + PPC_XSCVQPSDZ = 1931, + PPC_XSCVQPSWZ = 1932, + PPC_XSCVQPUDZ = 1933, + PPC_XSCVQPUWZ = 1934, + PPC_XSCVSDQP = 1935, + PPC_XSCVSPDP = 1936, + PPC_XSCVSPDPN = 1937, + PPC_XSCVSXDDP = 1938, + PPC_XSCVSXDSP = 1939, + PPC_XSCVUDQP = 1940, + PPC_XSCVUXDDP = 1941, + PPC_XSCVUXDSP = 1942, + PPC_XSDIVDP = 1943, + PPC_XSDIVQP = 1944, + PPC_XSDIVQPO = 1945, + PPC_XSDIVSP = 1946, + PPC_XSIEXPDP = 1947, + PPC_XSIEXPQP = 1948, + PPC_XSMADDADP = 1949, + PPC_XSMADDASP = 1950, + PPC_XSMADDMDP = 1951, + PPC_XSMADDMSP = 1952, + PPC_XSMADDQP = 1953, + PPC_XSMADDQPO = 1954, + PPC_XSMAXCDP = 1955, + PPC_XSMAXDP = 1956, + PPC_XSMAXJDP = 1957, + PPC_XSMINCDP = 1958, + PPC_XSMINDP = 1959, + PPC_XSMINJDP = 1960, + PPC_XSMSUBADP = 1961, + PPC_XSMSUBASP = 1962, + PPC_XSMSUBMDP = 1963, + PPC_XSMSUBMSP = 1964, + PPC_XSMSUBQP = 1965, + PPC_XSMSUBQPO = 1966, + PPC_XSMULDP = 1967, + PPC_XSMULQP = 1968, + PPC_XSMULQPO = 1969, + PPC_XSMULSP = 1970, + PPC_XSNABSDP = 1971, + PPC_XSNABSQP = 1972, + PPC_XSNEGDP = 1973, + PPC_XSNEGQP = 1974, + PPC_XSNMADDADP = 1975, + PPC_XSNMADDASP = 1976, + PPC_XSNMADDMDP = 1977, + PPC_XSNMADDMSP = 1978, + PPC_XSNMADDQP = 1979, + PPC_XSNMADDQPO = 1980, + PPC_XSNMSUBADP = 1981, + PPC_XSNMSUBASP = 1982, + PPC_XSNMSUBMDP = 1983, + PPC_XSNMSUBMSP = 1984, + PPC_XSNMSUBQP = 1985, + PPC_XSNMSUBQPO = 1986, + PPC_XSRDPI = 1987, + PPC_XSRDPIC = 1988, + PPC_XSRDPIM = 1989, + PPC_XSRDPIP = 1990, + PPC_XSRDPIZ = 1991, + PPC_XSREDP = 1992, + PPC_XSRESP = 1993, + PPC_XSRQPI = 1994, + PPC_XSRQPIX = 1995, + PPC_XSRQPXP = 1996, + PPC_XSRSP = 1997, + PPC_XSRSQRTEDP = 1998, + PPC_XSRSQRTESP = 1999, + PPC_XSSQRTDP = 2000, + PPC_XSSQRTQP = 2001, + PPC_XSSQRTQPO = 2002, + PPC_XSSQRTSP = 2003, + PPC_XSSUBDP = 2004, + PPC_XSSUBQP = 2005, + PPC_XSSUBQPO = 2006, + PPC_XSSUBSP = 2007, + PPC_XSTDIVDP = 2008, + PPC_XSTSQRTDP = 2009, + PPC_XSTSTDCDP = 2010, + PPC_XSTSTDCQP = 2011, + PPC_XSTSTDCSP = 2012, + PPC_XSXEXPDP = 2013, + PPC_XSXEXPQP = 2014, + PPC_XSXSIGDP = 2015, + PPC_XSXSIGQP = 2016, + PPC_XVABSDP = 2017, + PPC_XVABSSP = 2018, + PPC_XVADDDP = 2019, + PPC_XVADDSP = 2020, + PPC_XVCMPEQDP = 2021, + PPC_XVCMPEQDPo = 2022, + PPC_XVCMPEQSP = 2023, + PPC_XVCMPEQSPo = 2024, + PPC_XVCMPGEDP = 2025, + PPC_XVCMPGEDPo = 2026, + PPC_XVCMPGESP = 2027, + PPC_XVCMPGESPo = 2028, + PPC_XVCMPGTDP = 2029, + PPC_XVCMPGTDPo = 2030, + PPC_XVCMPGTSP = 2031, + PPC_XVCMPGTSPo = 2032, + PPC_XVCPSGNDP = 2033, + PPC_XVCPSGNSP = 2034, + PPC_XVCVDPSP = 2035, + PPC_XVCVDPSXDS = 2036, + PPC_XVCVDPSXWS = 2037, + PPC_XVCVDPUXDS = 2038, + PPC_XVCVDPUXWS = 2039, + PPC_XVCVHPSP = 2040, + PPC_XVCVSPDP = 2041, + PPC_XVCVSPHP = 2042, + PPC_XVCVSPSXDS = 2043, + PPC_XVCVSPSXWS = 2044, + PPC_XVCVSPUXDS = 2045, + PPC_XVCVSPUXWS = 2046, + PPC_XVCVSXDDP = 2047, + PPC_XVCVSXDSP = 2048, + PPC_XVCVSXWDP = 2049, + PPC_XVCVSXWSP = 2050, + PPC_XVCVUXDDP = 2051, + PPC_XVCVUXDSP = 2052, + PPC_XVCVUXWDP = 2053, + PPC_XVCVUXWSP = 2054, + PPC_XVDIVDP = 2055, + PPC_XVDIVSP = 2056, + PPC_XVIEXPDP = 2057, + PPC_XVIEXPSP = 2058, + PPC_XVMADDADP = 2059, + PPC_XVMADDASP = 2060, + PPC_XVMADDMDP = 2061, + PPC_XVMADDMSP = 2062, + PPC_XVMAXDP = 2063, + PPC_XVMAXSP = 2064, + PPC_XVMINDP = 2065, + PPC_XVMINSP = 2066, + PPC_XVMSUBADP = 2067, + PPC_XVMSUBASP = 2068, + PPC_XVMSUBMDP = 2069, + PPC_XVMSUBMSP = 2070, + PPC_XVMULDP = 2071, + PPC_XVMULSP = 2072, + PPC_XVNABSDP = 2073, + PPC_XVNABSSP = 2074, + PPC_XVNEGDP = 2075, + PPC_XVNEGSP = 2076, + PPC_XVNMADDADP = 2077, + PPC_XVNMADDASP = 2078, + PPC_XVNMADDMDP = 2079, + PPC_XVNMADDMSP = 2080, + PPC_XVNMSUBADP = 2081, + PPC_XVNMSUBASP = 2082, + PPC_XVNMSUBMDP = 2083, + PPC_XVNMSUBMSP = 2084, + PPC_XVRDPI = 2085, + PPC_XVRDPIC = 2086, + PPC_XVRDPIM = 2087, + PPC_XVRDPIP = 2088, + PPC_XVRDPIZ = 2089, + PPC_XVREDP = 2090, + PPC_XVRESP = 2091, + PPC_XVRSPI = 2092, + PPC_XVRSPIC = 2093, + PPC_XVRSPIM = 2094, + PPC_XVRSPIP = 2095, + PPC_XVRSPIZ = 2096, + PPC_XVRSQRTEDP = 2097, + PPC_XVRSQRTESP = 2098, + PPC_XVSQRTDP = 2099, + PPC_XVSQRTSP = 2100, + PPC_XVSUBDP = 2101, + PPC_XVSUBSP = 2102, + PPC_XVTDIVDP = 2103, + PPC_XVTDIVSP = 2104, + PPC_XVTSQRTDP = 2105, + PPC_XVTSQRTSP = 2106, + PPC_XVTSTDCDP = 2107, + PPC_XVTSTDCSP = 2108, + PPC_XVXEXPDP = 2109, + PPC_XVXEXPSP = 2110, + PPC_XVXSIGDP = 2111, + PPC_XVXSIGSP = 2112, + PPC_XXBRD = 2113, + PPC_XXBRH = 2114, + PPC_XXBRQ = 2115, + PPC_XXBRW = 2116, + PPC_XXEXTRACTUW = 2117, + PPC_XXINSERTW = 2118, + PPC_XXLAND = 2119, + PPC_XXLANDC = 2120, + PPC_XXLEQV = 2121, + PPC_XXLNAND = 2122, + PPC_XXLNOR = 2123, + PPC_XXLOR = 2124, + PPC_XXLORC = 2125, + PPC_XXLORf = 2126, + PPC_XXLXOR = 2127, + PPC_XXLXORdpz = 2128, + PPC_XXLXORspz = 2129, + PPC_XXLXORz = 2130, + PPC_XXMRGHW = 2131, + PPC_XXMRGLW = 2132, + PPC_XXPERM = 2133, + PPC_XXPERMDI = 2134, + PPC_XXPERMDIs = 2135, + PPC_XXPERMR = 2136, + PPC_XXSEL = 2137, + PPC_XXSLDWI = 2138, + PPC_XXSLDWIs = 2139, + PPC_XXSPLTIB = 2140, + PPC_XXSPLTW = 2141, + PPC_XXSPLTWs = 2142, + PPC_gBC = 2143, + PPC_gBCA = 2144, + PPC_gBCAat = 2145, + PPC_gBCCTR = 2146, + PPC_gBCCTRL = 2147, + PPC_gBCL = 2148, + PPC_gBCLA = 2149, + PPC_gBCLAat = 2150, + PPC_gBCLR = 2151, + PPC_gBCLRL = 2152, + PPC_gBCLat = 2153, + PPC_gBCat = 2154, + PPC_INSTRUCTION_LIST_END = 2155 }; #endif // GET_INSTRINFO_ENUM @@ -2178,2470 +2179,2313 @@ enum { #define nullptr 0 -static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<, 2013-2019 */ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +/*===- TableGen'erated file -------------------------------------*- C++ +-*-===*|* *| |* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ - enum { PPC_DeprecatedDST = 0, PPC_Directive32 = 1, @@ -86,4 +86,3 @@ enum { PPC_FeatureSlowPOPCNTD = 72, PPC_FeatureVSX = 73, }; - diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c index 22eef4ee1c..8b5e2ab70e 100644 --- a/arch/PowerPC/PPCInstPrinter.c +++ b/arch/PowerPC/PPCInstPrinter.c @@ -20,14 +20,15 @@ #include #include -#include "PPCInstPrinter.h" -#include "PPCPredicates.h" #include "../../MCInst.h" -#include "../../utils.h" -#include "../../SStream.h" +#include "../../MCInstPrinter.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" +#include "../../SStream.h" +#include "../../utils.h" +#include "PPCInstPrinter.h" #include "PPCMapping.h" +#include "PPCPredicates.h" #ifndef CAPSTONE_DIET static const char *getRegisterName(unsigned RegNo); @@ -36,10 +37,39 @@ static const char *getRegisterName(unsigned RegNo); static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printInstruction(MCInst *MI, SStream *O); static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O); -static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI); +static char *printAliasInstr(MCInst *MI, SStream *OS); static char *printAliasBcc(MCInst *MI, SStream *OS, void *info); -static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, SStream *OS); +static void printPredicateOperand(MCInst *MI, unsigned OpNo, SStream *O, + const char *Modifier); +static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O); + +static void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O); +static void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); + +static void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O); +static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O); +static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O); +static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O); + +void printMemRegImmHash(MCInst *MI, unsigned OpNo, SStream *O); +void printImmZeroOperand(MCInst *MI, unsigned OpNo, SStream *O); +void printS34ImmOperand(const MCInst *MI, unsigned OpNo, SStream *O); +void printMemRegImm34(MCInst *MI, unsigned OpNo, SStream *O); +void printMemRegImm34PCRel(MCInst *MI, unsigned OpNo, SStream *O); + +static void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); #if 0 static void printRegName(SStream *OS, unsigned RegNo) @@ -57,51 +87,51 @@ static void printRegName(SStream *OS, unsigned RegNo) } #endif -static void set_mem_access(MCInst *MI, bool status) -{ - if (MI->csh->detail != CS_OPT_ON) - return; - - MI->csh->doing_mem = status; - - if (status) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0; - } else { - // done, create the next operand slot - MI->flat_insn->detail->ppc.op_count++; - } +static void set_mem_access(MCInst *MI, bool status) { + if (MI->csh->detail != CS_OPT_ON) + return; + + MI->csh->doing_mem = status; + + if (status) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_MEM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .mem.base = PPC_REG_INVALID; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .mem.disp = 0; + } else { + // done, create the next operand slot + MI->flat_insn->detail->ppc.op_count++; + } } -void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) -{ - if (((cs_struct *)ud)->detail != CS_OPT_ON) - return; - - // check if this insn has branch hint - if (strrchr(insn_asm, '+') != NULL && !strstr(insn_asm, ".+")) { - insn->detail->ppc.bh = PPC_BH_PLUS; - } else if (strrchr(insn_asm, '-') != NULL) { - insn->detail->ppc.bh = PPC_BH_MINUS; - } +void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; - if (strrchr(insn_asm, '.') != NULL) { - insn->detail->ppc.update_cr0 = true; - } + // check if this insn has branch hint + if (strrchr(insn_asm, '+') != NULL && !strstr(insn_asm, ".+")) { + insn->detail->ppc.bh = PPC_BH_PLUS; + } else if (strrchr(insn_asm, '-') != NULL) { + insn->detail->ppc.bh = PPC_BH_MINUS; + } + + if (strrchr(insn_asm, '.') != NULL) { + insn->detail->ppc.update_cr0 = true; + } } #define GET_INSTRINFO_ENUM -#include "PPCGenInstrInfo.inc" - +#define PRINT_ALIAS_INSTR #define GET_REGINFO_ENUM -#include "PPCGenRegisterInfo.inc" +#define GET_ASM_WRITER +#include "PPCGenDisassemblerTables.inc" -static void op_addBC(MCInst *MI, unsigned int bc) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.bc = (ppc_bc)bc; - } +static void op_addBC(MCInst *MI, unsigned int bc) { + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.bc = (ppc_bc)bc; + } } #define CREQ (0) @@ -109,1084 +139,1179 @@ static void op_addBC(MCInst *MI, unsigned int bc) #define CRLT (2) #define CRUN (3) -static int getBICRCond(int bi) -{ - return (bi - PPC_CR0EQ) >> 3; -} +static int getBICRCond(int bi) { return (bi - PPC_CR0EQ) >> 3; } -static int getBICR(int bi) -{ - return ((bi - PPC_CR0EQ) & 7) + PPC_CR0; -} +static int getBICR(int bi) { return ((bi - PPC_CR0EQ) & 7) + PPC_CR0; } -static void op_addReg(MCInst *MI, unsigned int reg) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg; - MI->flat_insn->detail->ppc.op_count++; - } +static void op_addReg(MCInst *MI, unsigned int reg) { + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_REG; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .reg = reg; + MI->flat_insn->detail->ppc.op_count++; + } } -static void add_CRxx(MCInst *MI, ppc_reg reg) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg; - MI->flat_insn->detail->ppc.op_count++; - } +static void add_CRxx(MCInst *MI, ppc_reg reg) { + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_REG; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .reg = reg; + MI->flat_insn->detail->ppc.op_count++; + } } -static char *printAliasBcc(MCInst *MI, SStream *OS, void *info) -{ -#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) - SStream ss; - const char *opCode; - char *tmp, *AsmMnem, *AsmOps, *c; - int OpIdx, PrintMethodIdx; - int decCtr = false, needComma = false; - MCRegisterInfo *MRI = (MCRegisterInfo *)info; - - SStream_Init(&ss); - - switch (MCInst_getOpcode(MI)) { - default: return NULL; - case PPC_gBC: - opCode = "b%s"; - break; - case PPC_gBCA: - opCode = "b%sa"; - break; - case PPC_gBCCTR: - opCode = "b%sctr"; - break; - case PPC_gBCCTRL: - opCode = "b%sctrl"; - break; - case PPC_gBCL: - opCode = "b%sl"; - break; - case PPC_gBCLA: - opCode = "b%sla"; - break; - case PPC_gBCLR: - opCode = "b%slr"; - break; - case PPC_gBCLRL: - opCode = "b%slrl"; - break; - } - - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) { - SStream_concat(&ss, opCode, "dnzf"); - decCtr = true; - } - - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) { - SStream_concat(&ss, opCode, "dzf"); - decCtr = true; - } - - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { - int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); - - switch(cr) { - case CREQ: - SStream_concat(&ss, opCode, "ne"); - break; - case CRGT: - SStream_concat(&ss, opCode, "le"); - break; - case CRLT: - SStream_concat(&ss, opCode, "ge"); - break; - case CRUN: - SStream_concat(&ss, opCode, "ns"); - break; - } - - if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6) - SStream_concat0(&ss, "-"); - - if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7) - SStream_concat0(&ss, "+"); - - decCtr = false; - } - - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) { - SStream_concat(&ss, opCode, "dnzt"); - decCtr = true; - } - - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) { - SStream_concat(&ss, opCode, "dzt"); - decCtr = true; - } - - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { - int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); - - switch(cr) { - case CREQ: - SStream_concat(&ss, opCode, "eq"); - break; - case CRGT: - SStream_concat(&ss, opCode, "gt"); - break; - case CRLT: - SStream_concat(&ss, opCode, "lt"); - break; - case CRUN: - SStream_concat(&ss, opCode, "so"); - break; - } - - if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14) - SStream_concat0(&ss, "-"); - - if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) - SStream_concat0(&ss, "+"); - - decCtr = false; - } - - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 16)) { - SStream_concat(&ss, opCode, "dnz"); - - if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24) - SStream_concat0(&ss, "-"); - - if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25) - SStream_concat0(&ss, "+"); - - needComma = false; - } - - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 18)) { - SStream_concat(&ss, opCode, "dz"); - - if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26) - SStream_concat0(&ss, "-"); - - if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27) - SStream_concat0(&ss, "+"); - - needComma = false; - } - - if (MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - (MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) { - int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1))); - - if (decCtr) { - int cd; - needComma = true; - SStream_concat0(&ss, " "); - - if (cr > PPC_CR0) { - SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0); - } - - cd = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); - switch(cd) { - case CREQ: - SStream_concat0(&ss, "eq"); - if (cr <= PPC_CR0) - add_CRxx(MI, PPC_REG_CR0EQ); - op_addBC(MI, PPC_BC_EQ); - break; - case CRGT: - SStream_concat0(&ss, "gt"); - if (cr <= PPC_CR0) - add_CRxx(MI, PPC_REG_CR0GT); - op_addBC(MI, PPC_BC_GT); - break; - case CRLT: - SStream_concat0(&ss, "lt"); - if (cr <= PPC_CR0) - add_CRxx(MI, PPC_REG_CR0LT); - op_addBC(MI, PPC_BC_LT); - break; - case CRUN: - SStream_concat0(&ss, "so"); - if (cr <= PPC_CR0) - add_CRxx(MI, PPC_REG_CR0UN); - op_addBC(MI, PPC_BC_SO); - break; - } - - if (cr > PPC_CR0) { - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); - MI->flat_insn->detail->ppc.op_count++; - } - } - } else { - if (cr > PPC_CR0) { - needComma = true; - SStream_concat(&ss, " cr%d", cr - PPC_CR0); - op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0); - } - } - } - - if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) { - if (needComma) - SStream_concat0(&ss, ","); - - SStream_concat0(&ss, " $\xFF\x03\x01"); - } - - tmp = cs_strdup(ss.buffer); - AsmMnem = tmp; - for(AsmOps = tmp; *AsmOps; AsmOps++) { - if (*AsmOps == ' ' || *AsmOps == '\t') { - *AsmOps = '\0'; - AsmOps++; - break; - } - } - - SStream_concat0(OS, AsmMnem); - if (*AsmOps) { - SStream_concat0(OS, "\t"); - for (c = AsmOps; *c; c++) { - if (*c == '$') { - c += 1; - if (*c == (char)0xff) { - c += 1; - OpIdx = *c - 1; - c += 1; - PrintMethodIdx = *c - 1; - printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); - } else - printOperand(MI, *c - 1, OS); - } else { - SStream_concat1(OS, *c); - } - } - } - - return tmp; +static char *printAliasBcc(MCInst *MI, SStream *OS, void *info) { +#define GETREGCLASS_CONTAIN(_class, _reg) \ + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), \ + MCOperand_getReg(MCInst_getOperand(MI, _reg))) + SStream ss; + const char *opCode; + char *tmp, *AsmMnem, *AsmOps, *c; + int OpIdx, PrintMethodIdx; + int decCtr = false, needComma = false; + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + + SStream_Init(&ss); + + switch (MCInst_getOpcode(MI)) { + default: + return NULL; + case PPC_gBC: + opCode = "b%s"; + break; + case PPC_gBCA: + opCode = "b%sa"; + break; + case PPC_gBCCTR: + opCode = "b%sctr"; + break; + case PPC_gBCCTRL: + opCode = "b%sctrl"; + break; + case PPC_gBCL: + opCode = "b%sl"; + break; + case PPC_gBCLA: + opCode = "b%sla"; + break; + case PPC_gBCLR: + opCode = "b%slr"; + break; + case PPC_gBCLRL: + opCode = "b%slrl"; + break; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) { + SStream_concat(&ss, opCode, "dnzf"); + decCtr = true; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) { + SStream_concat(&ss, opCode, "dzf"); + decCtr = true; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); + + switch (cr) { + case CREQ: + SStream_concat(&ss, opCode, "ne"); + break; + case CRGT: + SStream_concat(&ss, opCode, "le"); + break; + case CRLT: + SStream_concat(&ss, opCode, "ge"); + break; + case CRUN: + SStream_concat(&ss, opCode, "ns"); + break; + } + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6) + SStream_concat0(&ss, "-"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7) + SStream_concat0(&ss, "+"); + + decCtr = false; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) { + SStream_concat(&ss, opCode, "dnzt"); + decCtr = true; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) { + SStream_concat(&ss, opCode, "dzt"); + decCtr = true; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { + int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); + + switch (cr) { + case CREQ: + SStream_concat(&ss, opCode, "eq"); + break; + case CRGT: + SStream_concat(&ss, opCode, "gt"); + break; + case CRLT: + SStream_concat(&ss, opCode, "lt"); + break; + case CRUN: + SStream_concat(&ss, opCode, "so"); + break; + } + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14) + SStream_concat0(&ss, "-"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) + SStream_concat0(&ss, "+"); + + decCtr = false; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12) == 16)) { + SStream_concat(&ss, opCode, "dnz"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24) + SStream_concat0(&ss, "-"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25) + SStream_concat0(&ss, "+"); + + needComma = false; + } + + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12) == 18)) { + SStream_concat(&ss, opCode, "dz"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26) + SStream_concat0(&ss, "-"); + + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27) + SStream_concat0(&ss, "+"); + + needComma = false; + } + + if (MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + (MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) { + int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1))); + + if (decCtr) { + int cd; + needComma = true; + SStream_concat0(&ss, " "); + + if (cr > PPC_CR0) { + SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0); + } + + cd = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); + switch (cd) { + case CREQ: + SStream_concat0(&ss, "eq"); + if (cr <= PPC_CR0) + add_CRxx(MI, PPC_REG_CR0EQ); + op_addBC(MI, PPC_BC_EQ); + break; + case CRGT: + SStream_concat0(&ss, "gt"); + if (cr <= PPC_CR0) + add_CRxx(MI, PPC_REG_CR0GT); + op_addBC(MI, PPC_BC_GT); + break; + case CRLT: + SStream_concat0(&ss, "lt"); + if (cr <= PPC_CR0) + add_CRxx(MI, PPC_REG_CR0LT); + op_addBC(MI, PPC_BC_LT); + break; + case CRUN: + SStream_concat0(&ss, "so"); + if (cr <= PPC_CR0) + add_CRxx(MI, PPC_REG_CR0UN); + op_addBC(MI, PPC_BC_SO); + break; + } + + if (cr > PPC_CR0) { + if (MI->csh->detail) { + MI->flat_insn->detail->ppc + .operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_REG; + MI->flat_insn->detail->ppc + .operands[MI->flat_insn->detail->ppc.op_count] + .reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); + MI->flat_insn->detail->ppc.op_count++; + } + } + } else { + if (cr > PPC_CR0) { + needComma = true; + SStream_concat(&ss, " cr%d", cr - PPC_CR0); + op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0); + } + } + } + + if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) { + if (needComma) + SStream_concat0(&ss, ","); + + SStream_concat0(&ss, " $\xFF\x03\x01"); + } + + tmp = cs_strdup(ss.buffer); + AsmMnem = tmp; + for (AsmOps = tmp; *AsmOps; AsmOps++) { + if (*AsmOps == ' ' || *AsmOps == '\t') { + *AsmOps = '\0'; + AsmOps++; + break; + } + } + + SStream_concat0(OS, AsmMnem); + if (*AsmOps) { + SStream_concat0(OS, "\t"); + for (c = AsmOps; *c; c++) { + if (*c == '$') { + c += 1; + if (*c == (char)0xff) { + c += 1; + OpIdx = *c - 1; + c += 1; + PrintMethodIdx = *c - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, *c - 1, OS); + } else { + SStream_concat1(OS, *c); + } + } + } + + return tmp; } -static bool isBOCTRBranch(unsigned int op) -{ - return ((op >= PPC_BDNZ) && (op <= PPC_BDZp)); +static bool isBOCTRBranch(unsigned int op) { + return ((op >= PPC_BDNZ) && (op <= PPC_BDZp)); } -void PPC_printInst(MCInst *MI, SStream *O, void *Info) -{ - char *mnem; - unsigned int opcode = MCInst_getOpcode(MI); - - // printf("opcode = %u\n", opcode); - - // Check for slwi/srwi mnemonics. - if (opcode == PPC_RLWINM) { - unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2)); - unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3)); - unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4)); - bool useSubstituteMnemonic = false; - - if (SH <= 31 && MB == 0 && ME == (31 - SH)) { - SStream_concat0(O, "slwi\t"); - MCInst_setOpcodePub(MI, PPC_INS_SLWI); - useSubstituteMnemonic = true; - } - - if (SH <= 31 && MB == (32 - SH) && ME == 31) { - SStream_concat0(O, "srwi\t"); - MCInst_setOpcodePub(MI, PPC_INS_SRWI); - useSubstituteMnemonic = true; - SH = 32 - SH; - } - - if (useSubstituteMnemonic) { - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); - - if (SH > HEX_THRESHOLD) - SStream_concat(O, ", 0x%x", (unsigned int)SH); - else - SStream_concat(O, ", %u", (unsigned int)SH); - - if (MI->csh->detail) { - cs_ppc *ppc = &MI->flat_insn->detail->ppc; - - ppc->operands[ppc->op_count].type = PPC_OP_IMM; - ppc->operands[ppc->op_count].imm = SH; - ++ppc->op_count; - } - - return; - } - } - - if ((opcode == PPC_OR || opcode == PPC_OR8) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2))) { - SStream_concat0(O, "mr\t"); - MCInst_setOpcodePub(MI, PPC_INS_MR); - - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); - - return; - } - - if (opcode == PPC_RLDICR || - opcode == PPC_RLDICR_32) { - unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2)); - unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3)); - - // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH - if (63 - SH == ME) { - SStream_concat0(O, "sldi\t"); - MCInst_setOpcodePub(MI, PPC_INS_SLDI); - - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); - - if (SH > HEX_THRESHOLD) - SStream_concat(O, ", 0x%x", (unsigned int)SH); - else - SStream_concat(O, ", %u", (unsigned int)SH); - - if (MI->csh->detail) { - cs_ppc *ppc = &MI->flat_insn->detail->ppc; - - ppc->operands[ppc->op_count].type = PPC_OP_IMM; - ppc->operands[ppc->op_count].imm = SH; - ++ppc->op_count; - } - - - return; - } - } - - // dcbt[st] is printed manually here because: - // 1. The assembly syntax is different between embedded and server targets - // 2. We must print the short mnemonics for TH == 0 because the - // embedded/server syntax default will not be stable across assemblers - // The syntax for dcbt is: - // dcbt ra, rb, th [server] - // dcbt th, ra, rb [embedded] - // where th can be omitted when it is 0. dcbtst is the same. - if (opcode == PPC_DCBT || opcode == PPC_DCBTST) { - unsigned char TH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0)); - - SStream_concat0(O, "dcbt"); - MCInst_setOpcodePub(MI, PPC_INS_DCBT); - - if (opcode == PPC_DCBTST) { - SStream_concat0(O, "st"); - MCInst_setOpcodePub(MI, PPC_INS_DCBTST); - } - - if (TH == 16) { - SStream_concat0(O, "t"); - MCInst_setOpcodePub(MI, PPC_INS_DCBTSTT); - } - - SStream_concat0(O, "\t"); - - if (MI->csh->mode & CS_MODE_BOOKE && TH != 0 && TH != 16) { - if (TH > HEX_THRESHOLD) - SStream_concat(O, "0x%x, ", (unsigned int)TH); - else - SStream_concat(O, "%u, ", (unsigned int)TH); - - if (MI->csh->detail) { - cs_ppc *ppc = &MI->flat_insn->detail->ppc; - - ppc->operands[ppc->op_count].type = PPC_OP_IMM; - ppc->operands[ppc->op_count].imm = TH; - ++ppc->op_count; - } - } - - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); - - if (!(MI->csh->mode & CS_MODE_BOOKE) && TH != 0 && TH != 16) { - if (TH > HEX_THRESHOLD) - SStream_concat(O, ", 0x%x", (unsigned int)TH); - else - SStream_concat(O, ", %u", (unsigned int)TH); - - if (MI->csh->detail) { - cs_ppc *ppc = &MI->flat_insn->detail->ppc; - - ppc->operands[ppc->op_count].type = PPC_OP_IMM; - ppc->operands[ppc->op_count].imm = TH; - ++ppc->op_count; - } - } - - return; - } - - if (opcode == PPC_DCBF) { - unsigned char L = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0)); - - if (!L || L == 1 || L == 3) { - SStream_concat0(O, "dcbf"); - MCInst_setOpcodePub(MI, PPC_INS_DCBF); - - if (L == 1 || L == 3) { - SStream_concat0(O, "l"); - MCInst_setOpcodePub(MI, PPC_INS_DCBFL); - } - - if (L == 3) { - SStream_concat0(O, "p"); - MCInst_setOpcodePub(MI, PPC_INS_DCBFLP); - } - - SStream_concat0(O, "\t"); - - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); - - return; - } - } - - if (opcode == PPC_B || opcode == PPC_BA || opcode == PPC_BL || - opcode == PPC_BLA) { - int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0)); - bd = SignExtend64(bd, 24); - MCOperand_setImm(MCInst_getOperand(MI, 0), bd); - } - - if (opcode == PPC_gBC || opcode == PPC_gBCA || opcode == PPC_gBCL || - opcode == PPC_gBCLA) { - int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2)); - bd = SignExtend64(bd, 14); - MCOperand_setImm(MCInst_getOperand(MI, 2), bd); - } - - if (isBOCTRBranch(MCInst_getOpcode(MI))) { - if (MCOperand_isImm(MCInst_getOperand(MI,0))) { - int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0)); - bd = SignExtend64(bd, 14); - MCOperand_setImm(MCInst_getOperand(MI, 0), bd); - } - } - - mnem = printAliasBcc(MI, O, Info); - if (!mnem) - mnem = printAliasInstr(MI, O, Info); - - if (mnem != NULL) { - if (strlen(mnem) > 0) { - // check to remove the last letter of ('.', '-', '+') - if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || mnem[strlen(mnem) - 1] == '.') - mnem[strlen(mnem) - 1] = '\0'; - - MCInst_setOpcodePub(MI, PPC_map_insn(mnem)); - - if (MI->csh->detail) { - struct ppc_alias alias; - - if (PPC_alias_insn(mnem, &alias)) { - MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc; - } - } - } - - cs_mem_free(mnem); - } else - printInstruction(MI, O); +void PPC_printInst(MCInst *MI, SStream *O, void *Info) { + MRI = MI->MRI = Info; + char *mnem; + unsigned int opcode = MCInst_getOpcode(MI); + + // printf("opcode = %u\n", opcode); + + // Check for slwi/srwi mnemonics. + if (opcode == PPC_RLWINM) { + unsigned char SH = + (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2)); + unsigned char MB = + (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3)); + unsigned char ME = + (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4)); + bool useSubstituteMnemonic = false; + + if (SH <= 31 && MB == 0 && ME == (31 - SH)) { + SStream_concat0(O, "slwi\t"); + MCInst_setOpcodePub(MI, PPC_INS_SLWI); + useSubstituteMnemonic = true; + } + + if (SH <= 31 && MB == (32 - SH) && ME == 31) { + SStream_concat0(O, "srwi\t"); + MCInst_setOpcodePub(MI, PPC_INS_SRWI); + useSubstituteMnemonic = true; + SH = 32 - SH; + } + + if (useSubstituteMnemonic) { + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + + if (SH > HEX_THRESHOLD) + SStream_concat(O, ", 0x%x", (unsigned int)SH); + else + SStream_concat(O, ", %u", (unsigned int)SH); + + if (MI->csh->detail) { + cs_ppc *ppc = &MI->flat_insn->detail->ppc; + + ppc->operands[ppc->op_count].type = PPC_OP_IMM; + ppc->operands[ppc->op_count].imm = SH; + ++ppc->op_count; + } + + return; + } + } + + if ((opcode == PPC_OR || opcode == PPC_OR8) && + MCOperand_getReg(MCInst_getOperand(MI, 1)) == + MCOperand_getReg(MCInst_getOperand(MI, 2))) { + SStream_concat0(O, "mr\t"); + MCInst_setOpcodePub(MI, PPC_INS_MR); + + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + + return; + } + + if (opcode == PPC_RLDICR || opcode == PPC_RLDICR_32) { + unsigned char SH = + (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2)); + unsigned char ME = + (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3)); + + // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH + if (63 - SH == ME) { + SStream_concat0(O, "sldi\t"); + MCInst_setOpcodePub(MI, PPC_INS_SLDI); + + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + + if (SH > HEX_THRESHOLD) + SStream_concat(O, ", 0x%x", (unsigned int)SH); + else + SStream_concat(O, ", %u", (unsigned int)SH); + + if (MI->csh->detail) { + cs_ppc *ppc = &MI->flat_insn->detail->ppc; + + ppc->operands[ppc->op_count].type = PPC_OP_IMM; + ppc->operands[ppc->op_count].imm = SH; + ++ppc->op_count; + } + + return; + } + } + + // dcbt[st] is printed manually here because: + // 1. The assembly syntax is different between embedded and server targets + // 2. We must print the short mnemonics for TH == 0 because the + // embedded/server syntax default will not be stable across assemblers + // The syntax for dcbt is: + // dcbt ra, rb, th [server] + // dcbt th, ra, rb [embedded] + // where th can be omitted when it is 0. dcbtst is the same. + if (opcode == PPC_DCBT || opcode == PPC_DCBTST) { + unsigned char TH = + (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0)); + + SStream_concat0(O, "dcbt"); + MCInst_setOpcodePub(MI, PPC_INS_DCBT); + + if (opcode == PPC_DCBTST) { + SStream_concat0(O, "st"); + MCInst_setOpcodePub(MI, PPC_INS_DCBTST); + } + + if (TH == 16) { + SStream_concat0(O, "t"); + MCInst_setOpcodePub(MI, PPC_INS_DCBTSTT); + } + + SStream_concat0(O, "\t"); + + if (MI->csh->mode & CS_MODE_BOOKE && TH != 0 && TH != 16) { + if (TH > HEX_THRESHOLD) + SStream_concat(O, "0x%x, ", (unsigned int)TH); + else + SStream_concat(O, "%u, ", (unsigned int)TH); + + if (MI->csh->detail) { + cs_ppc *ppc = &MI->flat_insn->detail->ppc; + + ppc->operands[ppc->op_count].type = PPC_OP_IMM; + ppc->operands[ppc->op_count].imm = TH; + ++ppc->op_count; + } + } + + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + + if (!(MI->csh->mode & CS_MODE_BOOKE) && TH != 0 && TH != 16) { + if (TH > HEX_THRESHOLD) + SStream_concat(O, ", 0x%x", (unsigned int)TH); + else + SStream_concat(O, ", %u", (unsigned int)TH); + + if (MI->csh->detail) { + cs_ppc *ppc = &MI->flat_insn->detail->ppc; + + ppc->operands[ppc->op_count].type = PPC_OP_IMM; + ppc->operands[ppc->op_count].imm = TH; + ++ppc->op_count; + } + } + + return; + } + + if (opcode == PPC_DCBF) { + unsigned char L = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0)); + + if (!L || L == 1 || L == 3) { + SStream_concat0(O, "dcbf"); + MCInst_setOpcodePub(MI, PPC_INS_DCBF); + + if (L == 1 || L == 3) { + SStream_concat0(O, "l"); + MCInst_setOpcodePub(MI, PPC_INS_DCBFL); + } + + if (L == 3) { + SStream_concat0(O, "p"); + MCInst_setOpcodePub(MI, PPC_INS_DCBFLP); + } + + SStream_concat0(O, "\t"); + + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + + return; + } + } + + if (opcode == PPC_B || opcode == PPC_BA || opcode == PPC_BL || + opcode == PPC_BLA) { + int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0)); + bd = SignExtend64(bd, 24); + MCOperand_setImm(MCInst_getOperand(MI, 0), bd); + } + + if (opcode == PPC_gBC || opcode == PPC_gBCA || opcode == PPC_gBCL || + opcode == PPC_gBCLA) { + int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2)); + bd = SignExtend64(bd, 14); + MCOperand_setImm(MCInst_getOperand(MI, 2), bd); + } + + if (isBOCTRBranch(MCInst_getOpcode(MI))) { + if (MCOperand_isImm(MCInst_getOperand(MI, 0))) { + int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0)); + bd = SignExtend64(bd, 14); + MCOperand_setImm(MCInst_getOperand(MI, 0), bd); + } + } + + mnem = printAliasBcc(MI, O, Info); + if (!mnem) + mnem = printAliasInstr(MI, O); + + if (mnem != NULL) { + if (strlen(mnem) > 0) { + // check to remove the last letter of ('.', '-', '+') + if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || + mnem[strlen(mnem) - 1] == '.') + mnem[strlen(mnem) - 1] = '\0'; + + MCInst_setOpcodePub(MI, PPC_map_insn(mnem)); + + if (MI->csh->detail) { + struct ppc_alias alias; + + if (PPC_alias_insn(mnem, &alias)) { + MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc; + } + } + } + + cs_mem_free(mnem); + } else + printInstruction(MI, O); } // FIXME enum ppc_bc_hint { - PPC_BC_LT_MINUS = (0 << 5) | 14, - PPC_BC_LE_MINUS = (1 << 5) | 6, - PPC_BC_EQ_MINUS = (2 << 5) | 14, - PPC_BC_GE_MINUS = (0 << 5) | 6, - PPC_BC_GT_MINUS = (1 << 5) | 14, - PPC_BC_NE_MINUS = (2 << 5) | 6, - PPC_BC_UN_MINUS = (3 << 5) | 14, - PPC_BC_NU_MINUS = (3 << 5) | 6, - PPC_BC_LT_PLUS = (0 << 5) | 15, - PPC_BC_LE_PLUS = (1 << 5) | 7, - PPC_BC_EQ_PLUS = (2 << 5) | 15, - PPC_BC_GE_PLUS = (0 << 5) | 7, - PPC_BC_GT_PLUS = (1 << 5) | 15, - PPC_BC_NE_PLUS = (2 << 5) | 7, - PPC_BC_UN_PLUS = (3 << 5) | 15, - PPC_BC_NU_PLUS = (3 << 5) | 7, + PPC_BC_LT_MINUS = (0 << 5) | 14, + PPC_BC_LE_MINUS = (1 << 5) | 6, + PPC_BC_EQ_MINUS = (2 << 5) | 14, + PPC_BC_GE_MINUS = (0 << 5) | 6, + PPC_BC_GT_MINUS = (1 << 5) | 14, + PPC_BC_NE_MINUS = (2 << 5) | 6, + PPC_BC_UN_MINUS = (3 << 5) | 14, + PPC_BC_NU_MINUS = (3 << 5) | 6, + PPC_BC_LT_PLUS = (0 << 5) | 15, + PPC_BC_LE_PLUS = (1 << 5) | 7, + PPC_BC_EQ_PLUS = (2 << 5) | 15, + PPC_BC_GE_PLUS = (0 << 5) | 7, + PPC_BC_GT_PLUS = (1 << 5) | 15, + PPC_BC_NE_PLUS = (2 << 5) | 7, + PPC_BC_UN_PLUS = (3 << 5) | 15, + PPC_BC_NU_PLUS = (3 << 5) | 7, }; // FIXME // normalize CC to remove _MINUS & _PLUS -static int cc_normalize(int cc) -{ - switch(cc) { - default: return cc; - case PPC_BC_LT_MINUS: return PPC_BC_LT; - case PPC_BC_LE_MINUS: return PPC_BC_LE; - case PPC_BC_EQ_MINUS: return PPC_BC_EQ; - case PPC_BC_GE_MINUS: return PPC_BC_GE; - case PPC_BC_GT_MINUS: return PPC_BC_GT; - case PPC_BC_NE_MINUS: return PPC_BC_NE; - case PPC_BC_UN_MINUS: return PPC_BC_UN; - case PPC_BC_NU_MINUS: return PPC_BC_NU; - case PPC_BC_LT_PLUS : return PPC_BC_LT; - case PPC_BC_LE_PLUS : return PPC_BC_LE; - case PPC_BC_EQ_PLUS : return PPC_BC_EQ; - case PPC_BC_GE_PLUS : return PPC_BC_GE; - case PPC_BC_GT_PLUS : return PPC_BC_GT; - case PPC_BC_NE_PLUS : return PPC_BC_NE; - case PPC_BC_UN_PLUS : return PPC_BC_UN; - case PPC_BC_NU_PLUS : return PPC_BC_NU; - } +static int cc_normalize(int cc) { + switch (cc) { + default: + return cc; + case PPC_BC_LT_MINUS: + return PPC_BC_LT; + case PPC_BC_LE_MINUS: + return PPC_BC_LE; + case PPC_BC_EQ_MINUS: + return PPC_BC_EQ; + case PPC_BC_GE_MINUS: + return PPC_BC_GE; + case PPC_BC_GT_MINUS: + return PPC_BC_GT; + case PPC_BC_NE_MINUS: + return PPC_BC_NE; + case PPC_BC_UN_MINUS: + return PPC_BC_UN; + case PPC_BC_NU_MINUS: + return PPC_BC_NU; + case PPC_BC_LT_PLUS: + return PPC_BC_LT; + case PPC_BC_LE_PLUS: + return PPC_BC_LE; + case PPC_BC_EQ_PLUS: + return PPC_BC_EQ; + case PPC_BC_GE_PLUS: + return PPC_BC_GE; + case PPC_BC_GT_PLUS: + return PPC_BC_GT; + case PPC_BC_NE_PLUS: + return PPC_BC_NE; + case PPC_BC_UN_PLUS: + return PPC_BC_UN; + case PPC_BC_NU_PLUS: + return PPC_BC_NU; + } } -static void printPredicateOperand(MCInst *MI, unsigned OpNo, - SStream *O, const char *Modifier) -{ - unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - - MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code); - - if (!strcmp(Modifier, "cc")) { - switch ((ppc_predicate)Code) { - default: // unreachable - case PPC_PRED_LT_MINUS: - case PPC_PRED_LT_PLUS: - case PPC_PRED_LT: - SStream_concat0(O, "lt"); - return; - case PPC_PRED_LE_MINUS: - case PPC_PRED_LE_PLUS: - case PPC_PRED_LE: - SStream_concat0(O, "le"); - return; - case PPC_PRED_EQ_MINUS: - case PPC_PRED_EQ_PLUS: - case PPC_PRED_EQ: - SStream_concat0(O, "eq"); - return; - case PPC_PRED_GE_MINUS: - case PPC_PRED_GE_PLUS: - case PPC_PRED_GE: - SStream_concat0(O, "ge"); - return; - case PPC_PRED_GT_MINUS: - case PPC_PRED_GT_PLUS: - case PPC_PRED_GT: - SStream_concat0(O, "gt"); - return; - case PPC_PRED_NE_MINUS: - case PPC_PRED_NE_PLUS: - case PPC_PRED_NE: - SStream_concat0(O, "ne"); - return; - case PPC_PRED_UN_MINUS: - case PPC_PRED_UN_PLUS: - case PPC_PRED_UN: - SStream_concat0(O, "un"); - return; - case PPC_PRED_NU_MINUS: - case PPC_PRED_NU_PLUS: - case PPC_PRED_NU: - SStream_concat0(O, "nu"); - return; - case PPC_PRED_BIT_SET: - case PPC_PRED_BIT_UNSET: - // llvm_unreachable("Invalid use of bit predicate code"); - SStream_concat0(O, "invalid-predicate"); - return; - } - } - - if (!strcmp(Modifier, "pm")) { - switch ((ppc_predicate)Code) { - case PPC_PRED_LT: - case PPC_PRED_LE: - case PPC_PRED_EQ: - case PPC_PRED_GE: - case PPC_PRED_GT: - case PPC_PRED_NE: - case PPC_PRED_UN: - case PPC_PRED_NU: - return; - case PPC_PRED_LT_MINUS: - case PPC_PRED_LE_MINUS: - case PPC_PRED_EQ_MINUS: - case PPC_PRED_GE_MINUS: - case PPC_PRED_GT_MINUS: - case PPC_PRED_NE_MINUS: - case PPC_PRED_UN_MINUS: - case PPC_PRED_NU_MINUS: - SStream_concat0(O, "-"); - return; - case PPC_PRED_LT_PLUS: - case PPC_PRED_LE_PLUS: - case PPC_PRED_EQ_PLUS: - case PPC_PRED_GE_PLUS: - case PPC_PRED_GT_PLUS: - case PPC_PRED_NE_PLUS: - case PPC_PRED_UN_PLUS: - case PPC_PRED_NU_PLUS: - SStream_concat0(O, "+"); - return; - case PPC_PRED_BIT_SET: - case PPC_PRED_BIT_UNSET: - // llvm_unreachable("Invalid use of bit predicate code"); - SStream_concat0(O, "invalid-predicate"); - return; - default: // unreachable - return; - } - // llvm_unreachable("Invalid predicate code"); - } - - //assert(StringRef(Modifier) == "reg" && - // "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!"); - printOperand(MI, OpNo + 1, O); +static void printPredicateOperand(MCInst *MI, unsigned OpNo, SStream *O, + const char *Modifier) { + unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + + MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code); + + if (!strcmp(Modifier, "cc")) { + switch ((ppc_predicate)Code) { + default: // unreachable + case PPC_PRED_LT_MINUS: + case PPC_PRED_LT_PLUS: + case PPC_PRED_LT: + SStream_concat0(O, "lt"); + return; + case PPC_PRED_LE_MINUS: + case PPC_PRED_LE_PLUS: + case PPC_PRED_LE: + SStream_concat0(O, "le"); + return; + case PPC_PRED_EQ_MINUS: + case PPC_PRED_EQ_PLUS: + case PPC_PRED_EQ: + SStream_concat0(O, "eq"); + return; + case PPC_PRED_GE_MINUS: + case PPC_PRED_GE_PLUS: + case PPC_PRED_GE: + SStream_concat0(O, "ge"); + return; + case PPC_PRED_GT_MINUS: + case PPC_PRED_GT_PLUS: + case PPC_PRED_GT: + SStream_concat0(O, "gt"); + return; + case PPC_PRED_NE_MINUS: + case PPC_PRED_NE_PLUS: + case PPC_PRED_NE: + SStream_concat0(O, "ne"); + return; + case PPC_PRED_UN_MINUS: + case PPC_PRED_UN_PLUS: + case PPC_PRED_UN: + SStream_concat0(O, "un"); + return; + case PPC_PRED_NU_MINUS: + case PPC_PRED_NU_PLUS: + case PPC_PRED_NU: + SStream_concat0(O, "nu"); + return; + case PPC_PRED_BIT_SET: + case PPC_PRED_BIT_UNSET: + // llvm_unreachable("Invalid use of bit predicate code"); + SStream_concat0(O, "invalid-predicate"); + return; + } + } + + if (!strcmp(Modifier, "pm")) { + switch ((ppc_predicate)Code) { + case PPC_PRED_LT: + case PPC_PRED_LE: + case PPC_PRED_EQ: + case PPC_PRED_GE: + case PPC_PRED_GT: + case PPC_PRED_NE: + case PPC_PRED_UN: + case PPC_PRED_NU: + return; + case PPC_PRED_LT_MINUS: + case PPC_PRED_LE_MINUS: + case PPC_PRED_EQ_MINUS: + case PPC_PRED_GE_MINUS: + case PPC_PRED_GT_MINUS: + case PPC_PRED_NE_MINUS: + case PPC_PRED_UN_MINUS: + case PPC_PRED_NU_MINUS: + SStream_concat0(O, "-"); + return; + case PPC_PRED_LT_PLUS: + case PPC_PRED_LE_PLUS: + case PPC_PRED_EQ_PLUS: + case PPC_PRED_GE_PLUS: + case PPC_PRED_GT_PLUS: + case PPC_PRED_NE_PLUS: + case PPC_PRED_UN_PLUS: + case PPC_PRED_NU_PLUS: + SStream_concat0(O, "+"); + return; + case PPC_PRED_BIT_SET: + case PPC_PRED_BIT_UNSET: + // llvm_unreachable("Invalid use of bit predicate code"); + SStream_concat0(O, "invalid-predicate"); + return; + default: // unreachable + return; + } + // llvm_unreachable("Invalid predicate code"); + } + + // assert(StringRef(Modifier) == "reg" && + // "Need to specify 'cc', 'pm' or 'reg' as predicate op + // modifier!"); + printOperand(MI, OpNo + 1, O); } -static void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); +static void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - if (Code == 2) { - SStream_concat0(O, "-"); - } else if (Code == 3) { - SStream_concat0(O, "+"); - } + if (Code == 2) { + SStream_concat0(O, "-"); + } else if (Code == 3) { + SStream_concat0(O, "+"); + } } -static void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); +static void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - // assert(Value <= 1 && "Invalid u1imm argument!"); + // assert(Value <= 1 && "Invalid u1imm argument!"); - printUInt32(O, Value); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //assert(Value <= 3 && "Invalid u2imm argument!"); +static void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + // assert(Value <= 3 && "Invalid u2imm argument!"); - printUInt32(O, Value); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //assert(Value <= 8 && "Invalid u3imm argument!"); +static void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + // assert(Value <= 8 && "Invalid u3imm argument!"); - printUInt32(O, Value); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //assert(Value <= 15 && "Invalid u4imm argument!"); +static void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + // assert(Value <= 15 && "Invalid u4imm argument!"); - printUInt32(O, Value); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - Value = SignExtend32(Value, 5); +static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + Value = SignExtend32(Value, 5); - printInt32(O, Value); + printInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); +static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //assert(Value <= 31 && "Invalid u5imm argument!"); - printUInt32(O, Value); + // assert(Value <= 31 && "Invalid u5imm argument!"); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); +static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //assert(Value <= 63 && "Invalid u6imm argument!"); - printUInt32(O, Value); + // assert(Value <= 63 && "Invalid u6imm argument!"); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); +static void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //assert(Value <= 127 && "Invalid u7imm argument!"); - printUInt32(O, Value); + // assert(Value <= 127 && "Invalid u7imm argument!"); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } // Operands of BUILD_VECTOR are signed and we use this to print operands // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and // print as unsigned. -static void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - - printUInt32(O, Value); - - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } +static void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + + printUInt32(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); +static void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = + (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //assert(Value <= 1023 && "Invalid u10imm argument!"); - printUInt32(O, Value); + // assert(Value <= 1023 && "Invalid u10imm argument!"); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned short Value = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); +static void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned short Value = + (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - // assert(Value <= 4095 && "Invalid u12imm argument!"); + // assert(Value <= 4095 && "Invalid u12imm argument!"); - printUInt32(O, Value); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Value; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { - short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - printInt32(O, Imm); - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm; - } else { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm; - MI->flat_insn->detail->ppc.op_count++; - } - } - } else - printOperand(MI, OpNo, O); +static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { + short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + printInt32(O, Imm); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .mem.disp = Imm; + } else { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Imm; + MI->flat_insn->detail->ppc.op_count++; + } + } + } else + printOperand(MI, OpNo, O); } -static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { - unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - printUInt32(O, Imm); - - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm; - MI->flat_insn->detail->ppc.op_count++; - } - } else - printOperand(MI, OpNo, O); +static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { + if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { + unsigned short Imm = + (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + printUInt32(O, Imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = Imm; + MI->flat_insn->detail->ppc.op_count++; + } + } else + printOperand(MI, OpNo, O); } -static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { - printOperand(MI, OpNo, O); +static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O) { + if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { + printOperand(MI, OpNo, O); - return; - } + return; + } - // Branches can take an immediate operand. This is used by the branch - // selection pass to print .+8, an eight byte displacement from the PC. - // O << ".+"; - printAbsBranchOperand(MI, OpNo, O); + // Branches can take an immediate operand. This is used by the branch + // selection pass to print .+8, an eight byte displacement from the PC. + // O << ".+"; + printAbsBranchOperand(MI, OpNo, O); } -static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - int64_t imm; +static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O) { + int64_t imm; - if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { - printOperand(MI, OpNo, O); + if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { + printOperand(MI, OpNo, O); - return; - } + return; + } - imm = SignExtend32(MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4, 32); - //imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4; + imm = SignExtend32(MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4, 32); + // imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4; - if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) { - imm += MI->address; - } + if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) { + imm += MI->address; + } - printUInt64(O, imm); + printUInt64(O, imm); - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm; - MI->flat_insn->detail->ppc.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = imm; + MI->flat_insn->detail->ppc.op_count++; + } } -static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned RegNo; - unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, OpNo)); - - switch (CCReg) { - default: // llvm_unreachable("Unknown CR register"); - case PPC_CR0: RegNo = 0; break; - case PPC_CR1: RegNo = 1; break; - case PPC_CR2: RegNo = 2; break; - case PPC_CR3: RegNo = 3; break; - case PPC_CR4: RegNo = 4; break; - case PPC_CR5: RegNo = 5; break; - case PPC_CR6: RegNo = 6; break; - case PPC_CR7: RegNo = 7; break; - } - - printUInt32(O, 0x80 >> RegNo); +static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned RegNo; + unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, OpNo)); + + switch (CCReg) { + default: // llvm_unreachable("Unknown CR register"); + case PPC_CR0: + RegNo = 0; + break; + case PPC_CR1: + RegNo = 1; + break; + case PPC_CR2: + RegNo = 2; + break; + case PPC_CR3: + RegNo = 3; + break; + case PPC_CR4: + RegNo = 4; + break; + case PPC_CR5: + RegNo = 5; + break; + case PPC_CR6: + RegNo = 6; + break; + case PPC_CR7: + RegNo = 7; + break; + } + + printUInt32(O, 0x80 >> RegNo); } -static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O) -{ - set_mem_access(MI, true); +static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O) { + set_mem_access(MI, true); - printS16ImmOperand(MI, OpNo, O); + printS16ImmOperand(MI, OpNo, O); - SStream_concat0(O, "("); + SStream_concat0(O, "("); - if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0) - SStream_concat0(O, "0"); - else - printOperand(MI, OpNo + 1, O); + if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0) + SStream_concat0(O, "0"); + else + printOperand(MI, OpNo + 1, O); - SStream_concat0(O, ")"); + SStream_concat0(O, ")"); - set_mem_access(MI, false); + set_mem_access(MI, false); } -static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O) -{ - // When used as the base register, r0 reads constant zero rather than - // the value contained in the register. For this reason, the darwin - // assembler requires that we print r0 as 0 (no r) when used as the base. - if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0) - SStream_concat0(O, "0"); - else - printOperand(MI, OpNo, O); - SStream_concat0(O, ", "); - - printOperand(MI, OpNo + 1, O); +static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O) { + // When used as the base register, r0 reads constant zero rather than + // the value contained in the register. For this reason, the darwin + // assembler requires that we print r0 as 0 (no r) when used as the base. + if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0) + SStream_concat0(O, "0"); + else + printOperand(MI, OpNo, O); + SStream_concat0(O, ", "); + + printOperand(MI, OpNo + 1, O); } -static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O) -{ - set_mem_access(MI, true); - //printBranchOperand(MI, OpNo, O); +static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O) { + set_mem_access(MI, true); + // printBranchOperand(MI, OpNo, O); - // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must - // come at the _end_ of the expression. + // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must + // come at the _end_ of the expression. - SStream_concat0(O, "("); - printOperand(MI, OpNo + 1, O); - SStream_concat0(O, ")"); + SStream_concat0(O, "("); + printOperand(MI, OpNo + 1, O); + SStream_concat0(O, ")"); + + set_mem_access(MI, false); +} - set_mem_access(MI, false); +void printMemRegImmHash(MCInst *MI, unsigned OpNo, SStream *O) { + SStream_concat(O, "%u", MCOperand_getImm(MCInst_getOperand(MI, OpNo))); + SStream_concat(O, "("); + printOperand(MI, OpNo + 1, O); + SStream_concat(O, ")"); +} + +void printImmZeroOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + assert(Value == 0 && "Operand must be zero"); + SStream_concat(O, "%u", Value); +} + +void printS34ImmOperand(const MCInst *MI, unsigned OpNo, SStream *O) { + if (MCOperand_getImm(MCInst_getOperand(MI, OpNo))) { + long long Value = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + SStream_concat(O, "%u", Value); + } else + printOperand(MI, OpNo, O); +} + +void printMemRegImm34(MCInst *MI, unsigned OpNo, SStream *O) { + printS34ImmOperand(MI, OpNo, O); + SStream_concat(O, "("); + printOperand(MI, OpNo + 1, O); + SStream_concat(O, ")"); +} + +void printMemRegImm34PCRel(MCInst *MI, unsigned OpNo, SStream *O) { + printS34ImmOperand(MI, OpNo, O); + SStream_concat(O, "("); + printOperand(MI, OpNo + 1, O); + SStream_concat(O, ")"); } /// stripRegisterPrefix - This method strips the character prefix from a /// register name so that only the number is left. Used by for linux asm. -static char *stripRegisterPrefix(const char *RegName) -{ - switch (RegName[0]) { - case 'r': - case 'f': - case 'q': // for QPX - case 'v': - if (RegName[1] == 's') - return cs_strdup(RegName + 2); - - return cs_strdup(RegName + 1); - case 'c': - if (RegName[1] == 'r') { - // skip the first 2 letters "cr" - char *name = cs_strdup(RegName + 2); - - // also strip the last 2 letters - name[strlen(name) - 2] = '\0'; - - return name; - } - } - - return cs_strdup(RegName); +static char *stripRegisterPrefix(const char *RegName) { + switch (RegName[0]) { + case 'r': + case 'f': + case 'q': // for QPX + case 'v': + if (RegName[1] == 's') + return cs_strdup(RegName + 2); + + return cs_strdup(RegName + 1); + case 'c': + if (RegName[1] == 'r') { + // skip the first 2 letters "cr" + char *name = cs_strdup(RegName + 2); + + // also strip the last 2 letters + name[strlen(name) - 2] = '\0'; + + return name; + } + } + + return cs_strdup(RegName); } -static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - MCOperand *Op = MCInst_getOperand(MI, OpNo); - if (MCOperand_isReg(Op)) { - unsigned reg = MCOperand_getReg(Op); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { + MCOperand *Op = MCInst_getOperand(MI, OpNo); + if (MCOperand_isReg(Op)) { + unsigned reg = MCOperand_getReg(Op); #ifndef CAPSTONE_DIET - const char *RegName = getRegisterName(reg); - // printf("reg = %u (%s)\n", reg, RegName); + const char *RegName = PPC_reg_name(0, reg); + if (!RegName) + RegName = getRegisterName(reg); - // convert internal register ID to public register ID - reg = PPC_name_reg(RegName); + // printf("reg = %u (%s)\n", reg, RegName); - // The linux and AIX assembler does not take register prefixes. - if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME) { - char *name = stripRegisterPrefix(RegName); - SStream_concat0(O, name); - cs_mem_free(name); - } else - SStream_concat0(O, RegName); -#endif + // convert internal register ID to public register ID + reg = PPC_name_reg(RegName); - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg; - } else { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg; - MI->flat_insn->detail->ppc.op_count++; - } - } - - return; - } + // The linux and AIX assembler does not take register prefixes. + if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME) { + char *name = stripRegisterPrefix(RegName); + SStream_concat0(O, name); + cs_mem_free(name); + } else + SStream_concat0(O, RegName); +#endif - if (MCOperand_isImm(Op)) { - int32_t imm = (int32_t)MCOperand_getImm(Op); - printInt32(O, imm); - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = (int32_t)imm; - } else { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm; - MI->flat_insn->detail->ppc.op_count++; - } - } - } + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .mem.base = reg; + } else { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_REG; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .reg = reg; + MI->flat_insn->detail->ppc.op_count++; + } + } + + return; + } + + if (MCOperand_isImm(Op)) { + int32_t imm = (int32_t)MCOperand_getImm(Op); + printInt32(O, imm); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .mem.disp = (int32_t)imm; + } else { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = imm; + MI->flat_insn->detail->ppc.op_count++; + } + } + } } -static void op_addImm(MCInst *MI, int v) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; - MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = v; - MI->flat_insn->detail->ppc.op_count++; - } +static void op_addImm(MCInst *MI, int v) { + if (MI->csh->detail) { + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .type = PPC_OP_IMM; + MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count] + .imm = v; + MI->flat_insn->detail->ppc.op_count++; + } } -#define PRINT_ALIAS_INSTR -#include "PPCGenRegisterName.inc" -#include "PPCGenAsmWriter.inc" - #endif diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c index 1ed84738c5..a6a1cee955 100644 --- a/arch/PowerPC/PPCMapping.c +++ b/arch/PowerPC/PPCMapping.c @@ -3,7 +3,7 @@ #ifdef CAPSTONE_HAS_POWERPC -#include // debug +#include // debug #include #include "../../utils.h" @@ -11,559 +11,494 @@ #include "PPCMapping.h" #define GET_INSTRINFO_ENUM -#include "PPCGenInstrInfo.inc" +#define GET_REGINFO_ENUM +#include "PPCGenDisassemblerTables.inc" // NOTE: this reg_name_maps[] reflects the order of registers in ppc_reg static const name_map reg_name_maps[] = { - { PPC_REG_INVALID, NULL }, - - { PPC_REG_CARRY, "ca" }, - { PPC_REG_CTR, "ctr" }, - { PPC_REG_LR, "lr" }, - { PPC_REG_RM, "rm" }, - { PPC_REG_VRSAVE, "vrsave" }, - { PPC_REG_XER, "xer" }, - { PPC_REG_ZERO, "zero" }, - { PPC_REG_CR0, "cr0" }, - { PPC_REG_CR1, "cr1" }, - { PPC_REG_CR2, "cr2" }, - { PPC_REG_CR3, "cr3" }, - { PPC_REG_CR4, "cr4" }, - { PPC_REG_CR5, "cr5" }, - { PPC_REG_CR6, "cr6" }, - { PPC_REG_CR7, "cr7" }, - { PPC_REG_CTR8, "ctr8" }, - { PPC_REG_F0, "f0" }, - { PPC_REG_F1, "f1" }, - { PPC_REG_F2, "f2" }, - { PPC_REG_F3, "f3" }, - { PPC_REG_F4, "f4" }, - { PPC_REG_F5, "f5" }, - { PPC_REG_F6, "f6" }, - { PPC_REG_F7, "f7" }, - { PPC_REG_F8, "f8" }, - { PPC_REG_F9, "f9" }, - { PPC_REG_F10, "f10" }, - { PPC_REG_F11, "f11" }, - { PPC_REG_F12, "f12" }, - { PPC_REG_F13, "f13" }, - { PPC_REG_F14, "f14" }, - { PPC_REG_F15, "f15" }, - { PPC_REG_F16, "f16" }, - { PPC_REG_F17, "f17" }, - { PPC_REG_F18, "f18" }, - { PPC_REG_F19, "f19" }, - { PPC_REG_F20, "f20" }, - { PPC_REG_F21, "f21" }, - { PPC_REG_F22, "f22" }, - { PPC_REG_F23, "f23" }, - { PPC_REG_F24, "f24" }, - { PPC_REG_F25, "f25" }, - { PPC_REG_F26, "f26" }, - { PPC_REG_F27, "f27" }, - { PPC_REG_F28, "f28" }, - { PPC_REG_F29, "f29" }, - { PPC_REG_F30, "f30" }, - { PPC_REG_F31, "f31" }, - { PPC_REG_LR8, "lr8" }, - - { PPC_REG_Q0, "q0" }, - { PPC_REG_Q1, "q1" }, - { PPC_REG_Q2, "q2" }, - { PPC_REG_Q3, "q3" }, - { PPC_REG_Q4, "q4" }, - { PPC_REG_Q5, "q5" }, - { PPC_REG_Q6, "q6" }, - { PPC_REG_Q7, "q7" }, - { PPC_REG_Q8, "q8" }, - { PPC_REG_Q9, "q9" }, - { PPC_REG_Q10, "q10" }, - { PPC_REG_Q11, "q11" }, - { PPC_REG_Q12, "q12" }, - { PPC_REG_Q13, "q13" }, - { PPC_REG_Q14, "q14" }, - { PPC_REG_Q15, "q15" }, - { PPC_REG_Q16, "q16" }, - { PPC_REG_Q17, "q17" }, - { PPC_REG_Q18, "q18" }, - { PPC_REG_Q19, "q19" }, - { PPC_REG_Q20, "q20" }, - { PPC_REG_Q21, "q21" }, - { PPC_REG_Q22, "q22" }, - { PPC_REG_Q23, "q23" }, - { PPC_REG_Q24, "q24" }, - { PPC_REG_Q25, "q25" }, - { PPC_REG_Q26, "q26" }, - { PPC_REG_Q27, "q27" }, - { PPC_REG_Q28, "q28" }, - { PPC_REG_Q29, "q29" }, - { PPC_REG_Q30, "q30" }, - { PPC_REG_Q31, "q31" }, - { PPC_REG_R0, "r0" }, - { PPC_REG_R1, "r1" }, - { PPC_REG_R2, "r2" }, - { PPC_REG_R3, "r3" }, - { PPC_REG_R4, "r4" }, - { PPC_REG_R5, "r5" }, - { PPC_REG_R6, "r6" }, - { PPC_REG_R7, "r7" }, - { PPC_REG_R8, "r8" }, - { PPC_REG_R9, "r9" }, - { PPC_REG_R10, "r10" }, - { PPC_REG_R11, "r11" }, - { PPC_REG_R12, "r12" }, - { PPC_REG_R13, "r13" }, - { PPC_REG_R14, "r14" }, - { PPC_REG_R15, "r15" }, - { PPC_REG_R16, "r16" }, - { PPC_REG_R17, "r17" }, - { PPC_REG_R18, "r18" }, - { PPC_REG_R19, "r19" }, - { PPC_REG_R20, "r20" }, - { PPC_REG_R21, "r21" }, - { PPC_REG_R22, "r22" }, - { PPC_REG_R23, "r23" }, - { PPC_REG_R24, "r24" }, - { PPC_REG_R25, "r25" }, - { PPC_REG_R26, "r26" }, - { PPC_REG_R27, "r27" }, - { PPC_REG_R28, "r28" }, - { PPC_REG_R29, "r29" }, - { PPC_REG_R30, "r30" }, - { PPC_REG_R31, "r31" }, - { PPC_REG_V0, "v0" }, - { PPC_REG_V1, "v1" }, - { PPC_REG_V2, "v2" }, - { PPC_REG_V3, "v3" }, - { PPC_REG_V4, "v4" }, - { PPC_REG_V5, "v5" }, - { PPC_REG_V6, "v6" }, - { PPC_REG_V7, "v7" }, - { PPC_REG_V8, "v8" }, - { PPC_REG_V9, "v9" }, - { PPC_REG_V10, "v10" }, - { PPC_REG_V11, "v11" }, - { PPC_REG_V12, "v12" }, - { PPC_REG_V13, "v13" }, - { PPC_REG_V14, "v14" }, - { PPC_REG_V15, "v15" }, - { PPC_REG_V16, "v16" }, - { PPC_REG_V17, "v17" }, - { PPC_REG_V18, "v18" }, - { PPC_REG_V19, "v19" }, - { PPC_REG_V20, "v20" }, - { PPC_REG_V21, "v21" }, - { PPC_REG_V22, "v22" }, - { PPC_REG_V23, "v23" }, - { PPC_REG_V24, "v24" }, - { PPC_REG_V25, "v25" }, - { PPC_REG_V26, "v26" }, - { PPC_REG_V27, "v27" }, - { PPC_REG_V28, "v28" }, - { PPC_REG_V29, "v29" }, - { PPC_REG_V30, "v30" }, - { PPC_REG_V31, "v31" }, - { PPC_REG_VS0, "vs0" }, - { PPC_REG_VS1, "vs1" }, - { PPC_REG_VS2, "vs2" }, - { PPC_REG_VS3, "vs3" }, - { PPC_REG_VS4, "vs4" }, - { PPC_REG_VS5, "vs5" }, - { PPC_REG_VS6, "vs6" }, - { PPC_REG_VS7, "vs7" }, - { PPC_REG_VS8, "vs8" }, - { PPC_REG_VS9, "vs9" }, - { PPC_REG_VS10, "vs10" }, - { PPC_REG_VS11, "vs11" }, - { PPC_REG_VS12, "vs12" }, - { PPC_REG_VS13, "vs13" }, - { PPC_REG_VS14, "vs14" }, - { PPC_REG_VS15, "vs15" }, - { PPC_REG_VS16, "vs16" }, - { PPC_REG_VS17, "vs17" }, - { PPC_REG_VS18, "vs18" }, - { PPC_REG_VS19, "vs19" }, - { PPC_REG_VS20, "vs20" }, - { PPC_REG_VS21, "vs21" }, - { PPC_REG_VS22, "vs22" }, - { PPC_REG_VS23, "vs23" }, - { PPC_REG_VS24, "vs24" }, - { PPC_REG_VS25, "vs25" }, - { PPC_REG_VS26, "vs26" }, - { PPC_REG_VS27, "vs27" }, - { PPC_REG_VS28, "vs28" }, - { PPC_REG_VS29, "vs29" }, - { PPC_REG_VS30, "vs30" }, - { PPC_REG_VS31, "vs31" }, - - { PPC_REG_VS32, "vs32" }, - { PPC_REG_VS33, "vs33" }, - { PPC_REG_VS34, "vs34" }, - { PPC_REG_VS35, "vs35" }, - { PPC_REG_VS36, "vs36" }, - { PPC_REG_VS37, "vs37" }, - { PPC_REG_VS38, "vs38" }, - { PPC_REG_VS39, "vs39" }, - { PPC_REG_VS40, "vs40" }, - { PPC_REG_VS41, "vs41" }, - { PPC_REG_VS42, "vs42" }, - { PPC_REG_VS43, "vs43" }, - { PPC_REG_VS44, "vs44" }, - { PPC_REG_VS45, "vs45" }, - { PPC_REG_VS46, "vs46" }, - { PPC_REG_VS47, "vs47" }, - { PPC_REG_VS48, "vs48" }, - { PPC_REG_VS49, "vs49" }, - { PPC_REG_VS50, "vs50" }, - { PPC_REG_VS51, "vs51" }, - { PPC_REG_VS52, "vs52" }, - { PPC_REG_VS53, "vs53" }, - { PPC_REG_VS54, "vs54" }, - { PPC_REG_VS55, "vs55" }, - { PPC_REG_VS56, "vs56" }, - { PPC_REG_VS57, "vs57" }, - { PPC_REG_VS58, "vs58" }, - { PPC_REG_VS59, "vs59" }, - { PPC_REG_VS60, "vs60" }, - { PPC_REG_VS61, "vs61" }, - { PPC_REG_VS62, "vs62" }, - { PPC_REG_VS63, "vs63" }, - - { PPC_REG_CR0EQ, "cr0eq" }, - { PPC_REG_CR1EQ, "cr1eq" }, - { PPC_REG_CR2EQ, "cr2eq" }, - { PPC_REG_CR3EQ, "cr3eq" }, - { PPC_REG_CR4EQ, "cr4eq" }, - { PPC_REG_CR5EQ, "cr5eq" }, - { PPC_REG_CR6EQ, "cr6eq" }, - { PPC_REG_CR7EQ, "cr7eq" }, - { PPC_REG_CR0GT, "cr0gt" }, - { PPC_REG_CR1GT, "cr1gt" }, - { PPC_REG_CR2GT, "cr2gt" }, - { PPC_REG_CR3GT, "cr3gt" }, - { PPC_REG_CR4GT, "cr4gt" }, - { PPC_REG_CR5GT, "cr5gt" }, - { PPC_REG_CR6GT, "cr6gt" }, - { PPC_REG_CR7GT, "cr7gt" }, - { PPC_REG_CR0LT, "cr0lt" }, - { PPC_REG_CR1LT, "cr1lt" }, - { PPC_REG_CR2LT, "cr2lt" }, - { PPC_REG_CR3LT, "cr3lt" }, - { PPC_REG_CR4LT, "cr4lt" }, - { PPC_REG_CR5LT, "cr5lt" }, - { PPC_REG_CR6LT, "cr6lt" }, - { PPC_REG_CR7LT, "cr7lt" }, - { PPC_REG_CR0UN, "cr0un" }, - { PPC_REG_CR1UN, "cr1un" }, - { PPC_REG_CR2UN, "cr2un" }, - { PPC_REG_CR3UN, "cr3un" }, - { PPC_REG_CR4UN, "cr4un" }, - { PPC_REG_CR5UN, "cr5un" }, - { PPC_REG_CR6UN, "cr6un" }, - { PPC_REG_CR7UN, "cr7un" }, + {PPC_REG_INVALID, NULL}, + + {PPC_CARRY, "ca"}, + {PPC_CTR, "ctr"}, + {PPC_LR, "lr"}, + {PPC_RM, "rm"}, + {PPC_VRSAVE, "vrsave"}, + {PPC_XER, "xer"}, + {PPC_ZERO, "zero"}, + {PPC_CR0, "cr0"}, + {PPC_CR1, "cr1"}, + {PPC_CR2, "cr2"}, + {PPC_CR3, "cr3"}, + {PPC_CR4, "cr4"}, + {PPC_CR5, "cr5"}, + {PPC_CR6, "cr6"}, + {PPC_CR7, "cr7"}, + {PPC_CTR8, "ctr8"}, + {PPC_F0, "f0"}, + {PPC_F1, "f1"}, + {PPC_F2, "f2"}, + {PPC_F3, "f3"}, + {PPC_F4, "f4"}, + {PPC_F5, "f5"}, + {PPC_F6, "f6"}, + {PPC_F7, "f7"}, + {PPC_F8, "f8"}, + {PPC_F9, "f9"}, + {PPC_F10, "f10"}, + {PPC_F11, "f11"}, + {PPC_F12, "f12"}, + {PPC_F13, "f13"}, + {PPC_F14, "f14"}, + {PPC_F15, "f15"}, + {PPC_F16, "f16"}, + {PPC_F17, "f17"}, + {PPC_F18, "f18"}, + {PPC_F19, "f19"}, + {PPC_F20, "f20"}, + {PPC_F21, "f21"}, + {PPC_F22, "f22"}, + {PPC_F23, "f23"}, + {PPC_F24, "f24"}, + {PPC_F25, "f25"}, + {PPC_F26, "f26"}, + {PPC_F27, "f27"}, + {PPC_F28, "f28"}, + {PPC_F29, "f29"}, + {PPC_F30, "f30"}, + {PPC_F31, "f31"}, + {PPC_LR8, "lr8"}, + /* {PPC_Q0, "q0"}, {PPC_Q1, "q1"}, + {PPC_Q2, "q2"}, {PPC_Q3, "q3"}, + {PPC_Q4, "q4"}, {PPC_Q5, "q5"}, + {PPC_Q6, "q6"}, {PPC_Q7, "q7"}, + {PPC_Q8, "q8"}, {PPC_Q9, "q9"}, + {PPC_Q10, "q10"}, {PPC_Q11, "q11"}, + {PPC_Q12, "q12"}, {PPC_Q13, "q13"}, + {PPC_Q14, "q14"}, {PPC_Q15, "q15"}, + {PPC_Q16, "q16"}, {PPC_Q17, "q17"}, + {PPC_Q18, "q18"}, {PPC_Q19, "q19"}, + {PPC_Q20, "q20"}, {PPC_Q21, "q21"}, + {PPC_Q22, "q22"}, {PPC_Q23, "q23"}, + {PPC_Q24, "q24"}, {PPC_Q25, "q25"}, + {PPC_Q26, "q26"}, {PPC_Q27, "q27"}, + {PPC_Q28, "q28"}, {PPC_Q29, "q29"}, + {PPC_Q30, "q30"}, {PPC_Q31, "q31"}, */ + {PPC_R0, "r0"}, + {PPC_R1, "r1"}, + {PPC_R2, "r2"}, + {PPC_R3, "r3"}, + {PPC_R4, "r4"}, + {PPC_R5, "r5"}, + {PPC_R6, "r6"}, + {PPC_R7, "r7"}, + {PPC_R8, "r8"}, + {PPC_R9, "r9"}, + {PPC_R10, "r10"}, + {PPC_R11, "r11"}, + {PPC_R12, "r12"}, + {PPC_R13, "r13"}, + {PPC_R14, "r14"}, + {PPC_R15, "r15"}, + {PPC_R16, "r16"}, + {PPC_R17, "r17"}, + {PPC_R18, "r18"}, + {PPC_R19, "r19"}, + {PPC_R20, "r20"}, + {PPC_R21, "r21"}, + {PPC_R22, "r22"}, + {PPC_R23, "r23"}, + {PPC_R24, "r24"}, + {PPC_R25, "r25"}, + {PPC_R26, "r26"}, + {PPC_R27, "r27"}, + {PPC_R28, "r28"}, + {PPC_R29, "r29"}, + {PPC_R30, "r30"}, + {PPC_R31, "r31"}, + {PPC_V0, "v0"}, + {PPC_V1, "v1"}, + {PPC_V2, "v2"}, + {PPC_V3, "v3"}, + {PPC_V4, "v4"}, + {PPC_V5, "v5"}, + {PPC_V6, "v6"}, + {PPC_V7, "v7"}, + {PPC_V8, "v8"}, + {PPC_V9, "v9"}, + {PPC_V10, "v10"}, + {PPC_V11, "v11"}, + {PPC_V12, "v12"}, + {PPC_V13, "v13"}, + {PPC_V14, "v14"}, + {PPC_V15, "v15"}, + {PPC_V16, "v16"}, + {PPC_V17, "v17"}, + {PPC_V18, "v18"}, + {PPC_V19, "v19"}, + {PPC_V20, "v20"}, + {PPC_V21, "v21"}, + {PPC_V22, "v22"}, + {PPC_V23, "v23"}, + {PPC_V24, "v24"}, + {PPC_V25, "v25"}, + {PPC_V26, "v26"}, + {PPC_V27, "v27"}, + {PPC_V28, "v28"}, + {PPC_V29, "v29"}, + {PPC_V30, "v30"}, + {PPC_V31, "v31"}, + /* {PPC_VS0, "vs0"}, {PPC_VS1, "vs1"}, + {PPC_VS2, "vs2"}, {PPC_VS3, "vs3"}, + {PPC_VS4, "vs4"}, {PPC_VS5, "vs5"}, + {PPC_VS6, "vs6"}, {PPC_VS7, "vs7"}, + {PPC_VS8, "vs8"}, {PPC_VS9, "vs9"}, + {PPC_VS10, "vs10"}, {PPC_VS11, "vs11"}, + {PPC_VS12, "vs12"}, {PPC_VS13, "vs13"}, + {PPC_VS14, "vs14"}, {PPC_VS15, "vs15"}, + {PPC_VS16, "vs16"}, {PPC_VS17, "vs17"}, + {PPC_VS18, "vs18"}, {PPC_VS19, "vs19"}, + {PPC_VS20, "vs20"}, {PPC_VS21, "vs21"}, + {PPC_VS22, "vs22"}, {PPC_VS23, "vs23"}, + {PPC_VS24, "vs24"}, {PPC_VS25, "vs25"}, + {PPC_VS26, "vs26"}, {PPC_VS27, "vs27"}, + {PPC_VS28, "vs28"}, {PPC_VS29, "vs29"}, + {PPC_VS30, "vs30"}, {PPC_VS31, "vs31"}, + {PPC_VS32, "vs32"}, {PPC_VS33, "vs33"}, + {PPC_VS34, "vs34"}, {PPC_VS35, "vs35"}, + {PPC_VS36, "vs36"}, {PPC_VS37, "vs37"}, + {PPC_VS38, "vs38"}, {PPC_VS39, "vs39"}, + {PPC_VS40, "vs40"}, {PPC_VS41, "vs41"}, + {PPC_VS42, "vs42"}, {PPC_VS43, "vs43"}, + {PPC_VS44, "vs44"}, {PPC_VS45, "vs45"}, + {PPC_VS46, "vs46"}, {PPC_VS47, "vs47"}, + {PPC_VS48, "vs48"}, {PPC_VS49, "vs49"}, + {PPC_VS50, "vs50"}, {PPC_VS51, "vs51"}, + {PPC_VS52, "vs52"}, {PPC_VS53, "vs53"}, + {PPC_VS54, "vs54"}, {PPC_VS55, "vs55"}, + {PPC_VS56, "vs56"}, {PPC_VS57, "vs57"}, + {PPC_VS58, "vs58"}, {PPC_VS59, "vs59"}, + {PPC_VS60, "vs60"}, {PPC_VS61, "vs61"}, + {PPC_VS62, "vs62"}, {PPC_VS63, "vs63"}, */ + {PPC_CR0EQ, "cr0eq"}, + {PPC_CR1EQ, "cr1eq"}, + {PPC_CR2EQ, "cr2eq"}, + {PPC_CR3EQ, "cr3eq"}, + {PPC_CR4EQ, "cr4eq"}, + {PPC_CR5EQ, "cr5eq"}, + {PPC_CR6EQ, "cr6eq"}, + {PPC_CR7EQ, "cr7eq"}, + {PPC_CR0GT, "cr0gt"}, + {PPC_CR1GT, "cr1gt"}, + {PPC_CR2GT, "cr2gt"}, + {PPC_CR3GT, "cr3gt"}, + {PPC_CR4GT, "cr4gt"}, + {PPC_CR5GT, "cr5gt"}, + {PPC_CR6GT, "cr6gt"}, + {PPC_CR7GT, "cr7gt"}, + {PPC_CR0LT, "cr0lt"}, + {PPC_CR1LT, "cr1lt"}, + {PPC_CR2LT, "cr2lt"}, + {PPC_CR3LT, "cr3lt"}, + {PPC_CR4LT, "cr4lt"}, + {PPC_CR5LT, "cr5lt"}, + {PPC_CR6LT, "cr6lt"}, + {PPC_CR7LT, "cr7lt"}, + {PPC_CR0UN, "cr0un"}, + {PPC_CR1UN, "cr1un"}, + {PPC_CR2UN, "cr2un"}, + {PPC_CR3UN, "cr3un"}, + {PPC_CR4UN, "cr4un"}, + {PPC_CR5UN, "cr5un"}, + {PPC_CR6UN, "cr6un"}, + {PPC_CR7UN, "cr7un"}, }; -const char *PPC_reg_name(csh handle, unsigned int reg) -{ - // binary searching since the IDs are sorted in order - unsigned int left, right, m; - unsigned int max = ARR_SIZE(reg_name_maps); +const char *PPC_reg_name(csh handle, unsigned int reg) { + // binary searching since the IDs are sorted in order + unsigned int left, right, m; + unsigned int max = ARR_SIZE(reg_name_maps); - right = max - 1; + right = max - 1; - if (reg < reg_name_maps[0].id || reg > reg_name_maps[right].id) - // not found - return NULL; - - left = 0; + if (reg < reg_name_maps[0].id || reg > reg_name_maps[right].id) + // not found + return NULL; - while(left <= right) { - m = (left + right) / 2; - if (reg == reg_name_maps[m].id) { - return reg_name_maps[m].name; - } + left = 0; - if (reg < reg_name_maps[m].id) - right = m - 1; - else - left = m + 1; + while (left <= right) { + m = (left + right) / 2; + if (reg == reg_name_maps[m].id) { + return reg_name_maps[m].name; } - // not found - return NULL; + if (reg < reg_name_maps[m].id) + right = m - 1; + else + left = m + 1; + } + + // not found + return NULL; } -ppc_reg PPC_name_reg(const char *name) -{ - unsigned int i; +ppc_reg PPC_name_reg(const char *name) { + unsigned int i; - for(i = 1; i < ARR_SIZE(reg_name_maps); i++) { - if (!strcmp(name, reg_name_maps[i].name)) - return reg_name_maps[i].id; - } + for (i = 1; i < ARR_SIZE(reg_name_maps); i++) { + if (!strcmp(name, reg_name_maps[i].name)) + return reg_name_maps[i].id; + } - // not found - return 0; + // not found + return 0; } static const insn_map insns[] = { - // dummy item - { - 0, 0, + // dummy item + {0, + 0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif - }, + }, #include "PPCMappingInsn.inc" }; // given internal insn id, return public instruction info -void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) -{ - int i; +void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { + int i; - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; - if (h->detail) { + if (h->detail) { #ifndef CAPSTONE_DIET - cs_struct handle; - handle.detail = h->detail; - - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); - - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); - - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = PPC_GRP_JUMP; - insn->detail->groups_count++; - } - - insn->detail->ppc.update_cr0 = cs_reg_write((csh)&handle, insn, PPC_REG_CR0); + cs_struct handle; + handle.detail = h->detail; + + memcpy(insn->detail->regs_read, insns[i].regs_use, + sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = + (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, + sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = + (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = PPC_GRP_JUMP; + insn->detail->groups_count++; + } + + insn->detail->ppc.update_cr0 = + cs_reg_write((csh)&handle, insn, PPC_REG_CR0); #endif - } - } + } + } } -static const char * const insn_name_maps[] = { +static const char *const insn_name_maps[] = { NULL, // PPC_INS_BCT #include "PPCMappingInsnName.inc" }; -const char *PPC_insn_name(csh handle, unsigned int id) -{ +const char *PPC_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - if (id >= PPC_INS_ENDING) - return NULL; + if (id >= PPC_INS_ENDING) + return NULL; - return insn_name_maps[id]; + return insn_name_maps[id]; #else - return NULL; + return NULL; #endif } // map instruction name to public instruction ID -ppc_insn PPC_map_insn(const char *name) -{ - unsigned int i; +ppc_insn PPC_map_insn(const char *name) { + unsigned int i; - for(i = 1; i < ARR_SIZE(insn_name_maps); i++) { - if (!strcmp(name, insn_name_maps[i])) - return i; - } + for (i = 1; i < ARR_SIZE(insn_name_maps); i++) { + if (!strcmp(name, insn_name_maps[i])) + return i; + } - // not found - return PPC_INS_INVALID; + // not found + return PPC_INS_INVALID; } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { - // generic groups - { PPC_GRP_INVALID, NULL }, - { PPC_GRP_JUMP, "jump" }, - - // architecture-specific groups - { PPC_GRP_ALTIVEC, "altivec" }, - { PPC_GRP_MODE32, "mode32" }, - { PPC_GRP_MODE64, "mode64" }, - { PPC_GRP_BOOKE, "booke" }, - { PPC_GRP_NOTBOOKE, "notbooke" }, - { PPC_GRP_SPE, "spe" }, - { PPC_GRP_VSX, "vsx" }, - { PPC_GRP_E500, "e500" }, - { PPC_GRP_PPC4XX, "ppc4xx" }, - { PPC_GRP_PPC6XX, "ppc6xx" }, - { PPC_GRP_ICBT, "icbt" }, - { PPC_GRP_P8ALTIVEC, "p8altivec" }, - { PPC_GRP_P8VECTOR, "p8vector" }, - { PPC_GRP_QPX, "qpx" }, + // generic groups + {PPC_GRP_INVALID, NULL}, + {PPC_GRP_JUMP, "jump"}, + + // architecture-specific groups + {PPC_GRP_ALTIVEC, "altivec"}, + {PPC_GRP_MODE32, "mode32"}, + {PPC_GRP_MODE64, "mode64"}, + {PPC_GRP_BOOKE, "booke"}, + {PPC_GRP_NOTBOOKE, "notbooke"}, + {PPC_GRP_SPE, "spe"}, + {PPC_GRP_VSX, "vsx"}, + {PPC_GRP_E500, "e500"}, + {PPC_GRP_PPC4XX, "ppc4xx"}, + {PPC_GRP_PPC6XX, "ppc6xx"}, + {PPC_GRP_ICBT, "icbt"}, + {PPC_GRP_P8ALTIVEC, "p8altivec"}, + {PPC_GRP_P8VECTOR, "p8vector"}, + {PPC_GRP_QPX, "qpx"}, }; #endif -const char *PPC_group_name(csh handle, unsigned int id) -{ +const char *PPC_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else - return NULL; + return NULL; #endif } static const struct ppc_alias alias_insn_name_maps[] = { - //{ PPC_INS_BTA, "bta" }, - { PPC_INS_B, PPC_BC_LT, "blt" }, - { PPC_INS_B, PPC_BC_LE, "ble" }, - { PPC_INS_B, PPC_BC_EQ, "beq" }, - { PPC_INS_B, PPC_BC_GE, "bge" }, - { PPC_INS_B, PPC_BC_GT, "bgt" }, - { PPC_INS_B, PPC_BC_NE, "bne" }, - { PPC_INS_B, PPC_BC_UN, "bun" }, - { PPC_INS_B, PPC_BC_NU, "bnu" }, - { PPC_INS_B, PPC_BC_SO, "bso" }, - { PPC_INS_B, PPC_BC_NS, "bns" }, - - { PPC_INS_BA, PPC_BC_LT, "blta" }, - { PPC_INS_BA, PPC_BC_LE, "blea" }, - { PPC_INS_BA, PPC_BC_EQ, "beqa" }, - { PPC_INS_BA, PPC_BC_GE, "bgea" }, - { PPC_INS_BA, PPC_BC_GT, "bgta" }, - { PPC_INS_BA, PPC_BC_NE, "bnea" }, - { PPC_INS_BA, PPC_BC_UN, "buna" }, - { PPC_INS_BA, PPC_BC_NU, "bnua" }, - { PPC_INS_BA, PPC_BC_SO, "bsoa" }, - { PPC_INS_BA, PPC_BC_NS, "bnsa" }, - - { PPC_INS_BCTR, PPC_BC_LT, "bltctr" }, - { PPC_INS_BCTR, PPC_BC_LE, "blectr" }, - { PPC_INS_BCTR, PPC_BC_EQ, "beqctr" }, - { PPC_INS_BCTR, PPC_BC_GE, "bgectr" }, - { PPC_INS_BCTR, PPC_BC_GT, "bgtctr" }, - { PPC_INS_BCTR, PPC_BC_NE, "bnectr" }, - { PPC_INS_BCTR, PPC_BC_UN, "bunctr" }, - { PPC_INS_BCTR, PPC_BC_NU, "bnuctr" }, - { PPC_INS_BCTR, PPC_BC_SO, "bsoctr" }, - { PPC_INS_BCTR, PPC_BC_NS, "bnsctr" }, - - { PPC_INS_BCTRL, PPC_BC_LT, "bltctrl" }, - { PPC_INS_BCTRL, PPC_BC_LE, "blectrl" }, - { PPC_INS_BCTRL, PPC_BC_EQ, "beqctrl" }, - { PPC_INS_BCTRL, PPC_BC_GE, "bgectrl" }, - { PPC_INS_BCTRL, PPC_BC_GT, "bgtctrl" }, - { PPC_INS_BCTRL, PPC_BC_NE, "bnectrl" }, - { PPC_INS_BCTRL, PPC_BC_UN, "bunctrl" }, - { PPC_INS_BCTRL, PPC_BC_NU, "bnuctrl" }, - { PPC_INS_BCTRL, PPC_BC_SO, "bsoctrl" }, - { PPC_INS_BCTRL, PPC_BC_NS, "bnsctrl" }, - - { PPC_INS_BL, PPC_BC_LT, "bltl" }, - { PPC_INS_BL, PPC_BC_LE, "blel" }, - { PPC_INS_BL, PPC_BC_EQ, "beql" }, - { PPC_INS_BL, PPC_BC_GE, "bgel" }, - { PPC_INS_BL, PPC_BC_GT, "bgtl" }, - { PPC_INS_BL, PPC_BC_NE, "bnel" }, - { PPC_INS_BL, PPC_BC_UN, "bunl" }, - { PPC_INS_BL, PPC_BC_NU, "bnul" }, - { PPC_INS_BL, PPC_BC_SO, "bsol" }, - { PPC_INS_BL, PPC_BC_NS, "bnsl" }, - - { PPC_INS_BLA, PPC_BC_LT, "bltla" }, - { PPC_INS_BLA, PPC_BC_LE, "blela" }, - { PPC_INS_BLA, PPC_BC_EQ, "beqla" }, - { PPC_INS_BLA, PPC_BC_GE, "bgela" }, - { PPC_INS_BLA, PPC_BC_GT, "bgtla" }, - { PPC_INS_BLA, PPC_BC_NE, "bnela" }, - { PPC_INS_BLA, PPC_BC_UN, "bunla" }, - { PPC_INS_BLA, PPC_BC_NU, "bnula" }, - { PPC_INS_BLA, PPC_BC_SO, "bsola" }, - { PPC_INS_BLA, PPC_BC_NS, "bnsla" }, - - { PPC_INS_BLR, PPC_BC_LT, "bltlr" }, - { PPC_INS_BLR, PPC_BC_LE, "blelr" }, - { PPC_INS_BLR, PPC_BC_EQ, "beqlr" }, - { PPC_INS_BLR, PPC_BC_GE, "bgelr" }, - { PPC_INS_BLR, PPC_BC_GT, "bgtlr" }, - { PPC_INS_BLR, PPC_BC_NE, "bnelr" }, - { PPC_INS_BLR, PPC_BC_UN, "bunlr" }, - { PPC_INS_BLR, PPC_BC_NU, "bnulr" }, - { PPC_INS_BLR, PPC_BC_SO, "bsolr" }, - { PPC_INS_BLR, PPC_BC_NS, "bnslr" }, - - { PPC_INS_BLRL, PPC_BC_LT, "bltlrl" }, - { PPC_INS_BLRL, PPC_BC_LE, "blelrl" }, - { PPC_INS_BLRL, PPC_BC_EQ, "beqlrl" }, - { PPC_INS_BLRL, PPC_BC_GE, "bgelrl" }, - { PPC_INS_BLRL, PPC_BC_GT, "bgtlrl" }, - { PPC_INS_BLRL, PPC_BC_NE, "bnelrl" }, - { PPC_INS_BLRL, PPC_BC_UN, "bunlrl" }, - { PPC_INS_BLRL, PPC_BC_NU, "bnulrl" }, - { PPC_INS_BLRL, PPC_BC_SO, "bsolrl" }, - { PPC_INS_BLRL, PPC_BC_NS, "bnslrl" }, + //{ PPC_INS_BTA, "bta" }, + {PPC_INS_B, PPC_BC_LT, "blt"}, + {PPC_INS_B, PPC_BC_LE, "ble"}, + {PPC_INS_B, PPC_BC_EQ, "beq"}, + {PPC_INS_B, PPC_BC_GE, "bge"}, + {PPC_INS_B, PPC_BC_GT, "bgt"}, + {PPC_INS_B, PPC_BC_NE, "bne"}, + {PPC_INS_B, PPC_BC_UN, "bun"}, + {PPC_INS_B, PPC_BC_NU, "bnu"}, + {PPC_INS_B, PPC_BC_SO, "bso"}, + {PPC_INS_B, PPC_BC_NS, "bns"}, + + {PPC_INS_BA, PPC_BC_LT, "blta"}, + {PPC_INS_BA, PPC_BC_LE, "blea"}, + {PPC_INS_BA, PPC_BC_EQ, "beqa"}, + {PPC_INS_BA, PPC_BC_GE, "bgea"}, + {PPC_INS_BA, PPC_BC_GT, "bgta"}, + {PPC_INS_BA, PPC_BC_NE, "bnea"}, + {PPC_INS_BA, PPC_BC_UN, "buna"}, + {PPC_INS_BA, PPC_BC_NU, "bnua"}, + {PPC_INS_BA, PPC_BC_SO, "bsoa"}, + {PPC_INS_BA, PPC_BC_NS, "bnsa"}, + + {PPC_INS_BCTR, PPC_BC_LT, "bltctr"}, + {PPC_INS_BCTR, PPC_BC_LE, "blectr"}, + {PPC_INS_BCTR, PPC_BC_EQ, "beqctr"}, + {PPC_INS_BCTR, PPC_BC_GE, "bgectr"}, + {PPC_INS_BCTR, PPC_BC_GT, "bgtctr"}, + {PPC_INS_BCTR, PPC_BC_NE, "bnectr"}, + {PPC_INS_BCTR, PPC_BC_UN, "bunctr"}, + {PPC_INS_BCTR, PPC_BC_NU, "bnuctr"}, + {PPC_INS_BCTR, PPC_BC_SO, "bsoctr"}, + {PPC_INS_BCTR, PPC_BC_NS, "bnsctr"}, + + {PPC_INS_BCTRL, PPC_BC_LT, "bltctrl"}, + {PPC_INS_BCTRL, PPC_BC_LE, "blectrl"}, + {PPC_INS_BCTRL, PPC_BC_EQ, "beqctrl"}, + {PPC_INS_BCTRL, PPC_BC_GE, "bgectrl"}, + {PPC_INS_BCTRL, PPC_BC_GT, "bgtctrl"}, + {PPC_INS_BCTRL, PPC_BC_NE, "bnectrl"}, + {PPC_INS_BCTRL, PPC_BC_UN, "bunctrl"}, + {PPC_INS_BCTRL, PPC_BC_NU, "bnuctrl"}, + {PPC_INS_BCTRL, PPC_BC_SO, "bsoctrl"}, + {PPC_INS_BCTRL, PPC_BC_NS, "bnsctrl"}, + + {PPC_INS_BL, PPC_BC_LT, "bltl"}, + {PPC_INS_BL, PPC_BC_LE, "blel"}, + {PPC_INS_BL, PPC_BC_EQ, "beql"}, + {PPC_INS_BL, PPC_BC_GE, "bgel"}, + {PPC_INS_BL, PPC_BC_GT, "bgtl"}, + {PPC_INS_BL, PPC_BC_NE, "bnel"}, + {PPC_INS_BL, PPC_BC_UN, "bunl"}, + {PPC_INS_BL, PPC_BC_NU, "bnul"}, + {PPC_INS_BL, PPC_BC_SO, "bsol"}, + {PPC_INS_BL, PPC_BC_NS, "bnsl"}, + + {PPC_INS_BLA, PPC_BC_LT, "bltla"}, + {PPC_INS_BLA, PPC_BC_LE, "blela"}, + {PPC_INS_BLA, PPC_BC_EQ, "beqla"}, + {PPC_INS_BLA, PPC_BC_GE, "bgela"}, + {PPC_INS_BLA, PPC_BC_GT, "bgtla"}, + {PPC_INS_BLA, PPC_BC_NE, "bnela"}, + {PPC_INS_BLA, PPC_BC_UN, "bunla"}, + {PPC_INS_BLA, PPC_BC_NU, "bnula"}, + {PPC_INS_BLA, PPC_BC_SO, "bsola"}, + {PPC_INS_BLA, PPC_BC_NS, "bnsla"}, + + {PPC_INS_BLR, PPC_BC_LT, "bltlr"}, + {PPC_INS_BLR, PPC_BC_LE, "blelr"}, + {PPC_INS_BLR, PPC_BC_EQ, "beqlr"}, + {PPC_INS_BLR, PPC_BC_GE, "bgelr"}, + {PPC_INS_BLR, PPC_BC_GT, "bgtlr"}, + {PPC_INS_BLR, PPC_BC_NE, "bnelr"}, + {PPC_INS_BLR, PPC_BC_UN, "bunlr"}, + {PPC_INS_BLR, PPC_BC_NU, "bnulr"}, + {PPC_INS_BLR, PPC_BC_SO, "bsolr"}, + {PPC_INS_BLR, PPC_BC_NS, "bnslr"}, + + {PPC_INS_BLRL, PPC_BC_LT, "bltlrl"}, + {PPC_INS_BLRL, PPC_BC_LE, "blelrl"}, + {PPC_INS_BLRL, PPC_BC_EQ, "beqlrl"}, + {PPC_INS_BLRL, PPC_BC_GE, "bgelrl"}, + {PPC_INS_BLRL, PPC_BC_GT, "bgtlrl"}, + {PPC_INS_BLRL, PPC_BC_NE, "bnelrl"}, + {PPC_INS_BLRL, PPC_BC_UN, "bunlrl"}, + {PPC_INS_BLRL, PPC_BC_NU, "bnulrl"}, + {PPC_INS_BLRL, PPC_BC_SO, "bsolrl"}, + {PPC_INS_BLRL, PPC_BC_NS, "bnslrl"}, }; // given alias mnemonic, return instruction ID & CC -bool PPC_alias_insn(const char *name, struct ppc_alias *alias) -{ - size_t i; - - alias->cc = PPC_BC_INVALID; - - for(i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { - if (!strcmp(name, alias_insn_name_maps[i].mnem)) { - // alias->id = alias_insn_name_maps[i].id; - alias->cc = alias_insn_name_maps[i].cc; - return true; - } - } - - // not found - return false; +bool PPC_alias_insn(const char *name, struct ppc_alias *alias) { + size_t i; + + alias->cc = PPC_BC_INVALID; + + for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { + if (!strcmp(name, alias_insn_name_maps[i].mnem)) { + // alias->id = alias_insn_name_maps[i].id; + alias->cc = alias_insn_name_maps[i].cc; + return true; + } + } + + // not found + return false; } // check if this insn is relative branch -bool PPC_abs_branch(cs_struct *h, unsigned int id) -{ - unsigned int i; - // list all absolute branch instructions - static const unsigned int insn_abs[] = { - PPC_BA, - PPC_BCCA, - PPC_BCCLA, - PPC_BDNZA, - PPC_BDNZAm, - PPC_BDNZAp, - PPC_BDNZLA, - PPC_BDNZLAm, - PPC_BDNZLAp, - PPC_BDZA, - PPC_BDZAm, - PPC_BDZAp, - PPC_BDZLAm, - PPC_BDZLAp, - PPC_BLA, - PPC_gBCA, - PPC_gBCLA, - PPC_BDZLA, - 0 - }; - - // printf("opcode: %u\n", id); - - for (i = 0; insn_abs[i]; i++) { - if (id == insn_abs[i]) { - return true; - } - } - - // not found - return false; +bool PPC_abs_branch(cs_struct *h, unsigned int id) { + unsigned int i; + // list all absolute branch instructions + static const unsigned int insn_abs[] = { + PPC_BA, PPC_BCCA, PPC_BCCLA, PPC_BDNZA, PPC_BDNZAm, PPC_BDNZAp, + PPC_BDNZLA, PPC_BDNZLAm, PPC_BDNZLAp, PPC_BDZA, PPC_BDZAm, PPC_BDZAp, + PPC_BDZLAm, PPC_BDZLAp, PPC_BLA, PPC_gBCA, PPC_gBCLA, PPC_BDZLA, + 0}; + + // printf("opcode: %u\n", id); + + for (i = 0; insn_abs[i]; i++) { + if (id == insn_abs[i]) { + return true; + } + } + + // not found + return false; } #endif diff --git a/arch/PowerPC/PPCMapping.h b/arch/PowerPC/PPCMapping.h index a0d4331834..f79fa0be47 100644 --- a/arch/PowerPC/PPCMapping.h +++ b/arch/PowerPC/PPCMapping.h @@ -19,9 +19,9 @@ const char *PPC_insn_name(csh handle, unsigned int id); const char *PPC_group_name(csh handle, unsigned int id); struct ppc_alias { - unsigned int id; // instruction id - int cc; // code condition - const char *mnem; + unsigned int id; // instruction id + int cc; // code condition + const char *mnem; }; // map instruction name to public instruction ID @@ -37,4 +37,3 @@ ppc_reg PPC_map_register(unsigned int r); bool PPC_alias_insn(const char *name, struct ppc_alias *alias); #endif - diff --git a/arch/PowerPC/PPCMappingInsn.inc b/arch/PowerPC/PPCMappingInsn.inc index f62981d7e1..6658bcb886 100644 --- a/arch/PowerPC/PPCMappingInsn.inc +++ b/arch/PowerPC/PPCMappingInsn.inc @@ -1,12779 +1,16166 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* This is auto-gen data for Capstone disassembly engine + * (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ - -{ - PPC_CLRLSLDI, PPC_INS_CLRLSLDI, +{PPC_CLRLSLDI, + PPC_INS_CLRLSLDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif }, -{ - PPC_CLRLSLDIo, PPC_INS_CLRLSLDI, + {PPC_CLRLSLDI_rec, + PPC_INS_CLRLSLDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CLRLSLWI, PPC_INS_CLRLSLWI, + {PPC_CLRLSLWI, + PPC_INS_CLRLSLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CLRLSLWIo, PPC_INS_CLRLSLWI, + {PPC_CLRLSLWI_rec, + PPC_INS_CLRLSLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CLRRDI, PPC_INS_CLRRDI, + {PPC_CLRRDI, PPC_INS_CLRRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CLRRDIo, PPC_INS_CLRRDI, + {PPC_CLRRDI_rec, + PPC_INS_CLRRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CLRRWI, PPC_INS_CLRRWI, + {PPC_CLRRWI, PPC_INS_CLRRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CLRRWIo, PPC_INS_CLRRWI, + {PPC_CLRRWI_rec, + PPC_INS_CLRRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CP_COPY_FIRST, PPC_INS_COPY_FIRST, + {PPC_CP_COPY8, + PPC_INS_COPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CP_COPYx, PPC_INS_COPY, + {PPC_CP_PASTE8_rec, + PPC_INS_PASTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CP_PASTE_LAST, PPC_INS_PASTE_LAST, + {PPC_DCBFL, PPC_INS_DCBFL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CP_PASTEx, PPC_INS_PASTE, + {PPC_DCBFLP, PPC_INS_DCBFLP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBFL, PPC_INS_DCBFL, + {PPC_DCBFx, PPC_INS_DCBF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBFLP, PPC_INS_DCBFLP, + {PPC_DCBTCT, PPC_INS_DCBTCT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBFx, PPC_INS_DCBF, + {PPC_DCBTDS, PPC_INS_DCBTDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBTCT, PPC_INS_DCBTCT, + {PPC_DCBTSTCT, + PPC_INS_DCBTSTCT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_DCBTDS, PPC_INS_DCBTDS, + {PPC_DCBTSTDS, + PPC_INS_DCBTSTDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_DCBTSTCT, PPC_INS_DCBTSTCT, + {PPC_DCBTSTT, + PPC_INS_DCBTSTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_DCBTSTDS, PPC_INS_DCBTSTDS, + {PPC_DCBTSTx, + PPC_INS_DCBTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_DCBTSTT, PPC_INS_DCBTSTT, + {PPC_DCBTT, PPC_INS_DCBTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBTSTx, PPC_INS_DCBTST, + {PPC_DCBTx, PPC_INS_DCBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBTT, PPC_INS_DCBTT, + {PPC_EXTLDI, PPC_INS_EXTLDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBTx, PPC_INS_DCBT, + {PPC_EXTLDI_rec, + PPC_INS_EXTLDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTLDI, PPC_INS_EXTLDI, + {PPC_EXTLWI, PPC_INS_EXTLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EXTLDIo, PPC_INS_EXTLDI, + {PPC_EXTLWI_rec, + PPC_INS_EXTLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTLWI, PPC_INS_EXTLWI, + {PPC_EXTRDI, PPC_INS_EXTRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EXTLWIo, PPC_INS_EXTLWI, + {PPC_EXTRDI_rec, + PPC_INS_EXTRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTRDI, PPC_INS_EXTRDI, + {PPC_EXTRWI, PPC_INS_EXTRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EXTRDIo, PPC_INS_EXTRDI, + {PPC_EXTRWI_rec, + PPC_INS_EXTRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTRWI, PPC_INS_EXTRWI, + {PPC_INSLWI, PPC_INS_INSLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EXTRWIo, PPC_INS_EXTRWI, + {PPC_INSLWI_rec, + PPC_INS_INSLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_INSLWI, PPC_INS_INSLWI, + {PPC_INSRDI, PPC_INS_INSRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_INSLWIo, PPC_INS_INSLWI, + {PPC_INSRDI_rec, + PPC_INS_INSRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_INSRDI, PPC_INS_INSRDI, + {PPC_INSRWI, PPC_INS_INSRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_INSRDIo, PPC_INS_INSRDI, + {PPC_INSRWI_rec, + PPC_INS_INSRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_INSRWI, PPC_INS_INSRWI, + {PPC_LAx, PPC_INS_LA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_INSRWIo, PPC_INS_INSRWI, + {PPC_RLWIMI8, + PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LAx, PPC_INS_LA, + {PPC_RLWIMI8_rec, + PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWIMIbm, PPC_INS_RLWIMI, + {PPC_RLWINM8, + PPC_INS_RLWINM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWIMIobm, PPC_INS_RLWIMI, + {PPC_RLWINM8_rec, + PPC_INS_RLWINM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWINMbm, PPC_INS_RLWINM, + {PPC_RLWNM8, PPC_INS_RLWNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLWINMobm, PPC_INS_RLWINM, + {PPC_RLWNM8_rec, + PPC_INS_RLWNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWNMbm, PPC_INS_RLWNM, + {PPC_ROTRDI, PPC_INS_ROTRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLWNMobm, PPC_INS_RLWNM, + {PPC_ROTRDI_rec, + PPC_INS_ROTRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ROTRDI, PPC_INS_ROTRDI, + {PPC_ROTRWI, PPC_INS_ROTRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_ROTRDIo, PPC_INS_ROTRDI, + {PPC_ROTRWI_rec, + PPC_INS_ROTRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ROTRWI, PPC_INS_ROTRWI, + {PPC_SLDI, PPC_INS_SLDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ROTRWIo, PPC_INS_ROTRWI, + {PPC_SLDI_rec, + PPC_INS_SLDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SLDI, PPC_INS_SLDI, + {PPC_SLWI, PPC_INS_SLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLDIo, PPC_INS_SLDI, + {PPC_SLWI_rec, + PPC_INS_SLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SLWI, PPC_INS_SLWI, + {PPC_SRDI, PPC_INS_SRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLWIo, PPC_INS_SLWI, + {PPC_SRDI_rec, + PPC_INS_SRDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SRDI, PPC_INS_SRDI, + {PPC_SRWI, PPC_INS_SRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SRDIo, PPC_INS_SRDI, + {PPC_SRWI_rec, + PPC_INS_SRWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SRWI, PPC_INS_SRWI, + {PPC_SUBI, PPC_INS_SUBI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SRWIo, PPC_INS_SRWI, + {PPC_SUBIC, PPC_INS_SUBIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SUBI, PPC_INS_SUBI, + {PPC_SUBIC_rec, + PPC_INS_SUBIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBIC, PPC_INS_SUBIC, + {PPC_SUBIS, PPC_INS_SUBIS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SUBICo, PPC_INS_SUBIC, + {PPC_SUBPCIS, + PPC_INS_SUBPCIS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBIS, PPC_INS_SUBIS, + {PPC_ADD4, PPC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SUBPCIS, PPC_INS_SUBPCIS, + {PPC_ADD4TLS, + PPC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADD4, PPC_INS_ADD, + {PPC_ADD4_rec, + PPC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADD4TLS, PPC_INS_ADD, + {PPC_ADD8, PPC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADD4o, PPC_INS_ADD, + {PPC_ADD8TLS, + PPC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADD8, PPC_INS_ADD, + {PPC_ADD8TLS_, + PPC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADD8TLS, PPC_INS_ADD, + {PPC_ADD8_rec, + PPC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADD8TLS_, PPC_INS_ADD, + {PPC_ADDC, PPC_INS_ADDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADD8o, PPC_INS_ADD, + {PPC_ADDC8, PPC_INS_ADDC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADDC, PPC_INS_ADDC, + {PPC_ADDC8_rec, + PPC_INS_ADDC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDC8, PPC_INS_ADDC, + {PPC_ADDC_rec, + PPC_INS_ADDC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDC8o, PPC_INS_ADDC, + {PPC_ADDE, + PPC_INS_ADDE, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDCo, PPC_INS_ADDC, + {PPC_ADDE8, + PPC_INS_ADDE, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDE, PPC_INS_ADDE, + {PPC_ADDE8_rec, + PPC_INS_ADDE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDE8, PPC_INS_ADDE, + {PPC_ADDE_rec, + PPC_INS_ADDE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDE8o, PPC_INS_ADDE, + {PPC_ADDI, PPC_INS_ADDI, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADDEo, PPC_INS_ADDE, + {PPC_ADDI8, PPC_INS_ADDI, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADDI, PPC_INS_ADDI, + {PPC_ADDIC, PPC_INS_ADDIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADDI8, PPC_INS_ADDI, + {PPC_ADDIC8, PPC_INS_ADDIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADDIC, PPC_INS_ADDIC, + {PPC_ADDIC_rec, + PPC_INS_ADDIC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDIC8, PPC_INS_ADDIC, + {PPC_ADDIS, PPC_INS_ADDIS, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADDICo, PPC_INS_ADDIC, + {PPC_ADDIS8, PPC_INS_ADDIS, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADDIS, PPC_INS_ADDIS, + {PPC_ADDME, + PPC_INS_ADDME, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDIS8, PPC_INS_ADDIS, + {PPC_ADDME8, + PPC_INS_ADDME, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDME, PPC_INS_ADDME, + {PPC_ADDME8_rec, + PPC_INS_ADDME, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDME8, PPC_INS_ADDME, + {PPC_ADDME_rec, + PPC_INS_ADDME, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDME8o, PPC_INS_ADDME, + {PPC_ADDPCIS, + PPC_INS_ADDPCIS, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDMEo, PPC_INS_ADDME, + {PPC_ADDZE, + PPC_INS_ADDZE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDPCIS, PPC_INS_ADDPCIS, + {PPC_ADDZE8, + PPC_INS_ADDZE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDZE, PPC_INS_ADDZE, + {PPC_ADDZE8_rec, + PPC_INS_ADDZE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDZE8, PPC_INS_ADDZE, + {PPC_ADDZE_rec, + PPC_INS_ADDZE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ADDZE8o, PPC_INS_ADDZE, + {PPC_AND, PPC_INS_AND, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ADDZEo, PPC_INS_ADDZE, + {PPC_AND8, PPC_INS_AND, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_AND, PPC_INS_AND, + {PPC_AND8_rec, + PPC_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_AND8, PPC_INS_AND, + {PPC_ANDC, PPC_INS_ANDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_AND8o, PPC_INS_AND, + {PPC_ANDC8, PPC_INS_ANDC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ANDC, PPC_INS_ANDC, + {PPC_ANDC8_rec, + PPC_INS_ANDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ANDC8, PPC_INS_ANDC, + {PPC_ANDC_rec, + PPC_INS_ANDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ANDC8o, PPC_INS_ANDC, + {PPC_ANDIS_rec, + PPC_INS_ANDIS, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ANDCo, PPC_INS_ANDC, + {PPC_ANDIS8_rec, + PPC_INS_ANDIS, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ANDISo, PPC_INS_ANDIS, + {PPC_ANDI_rec, + PPC_INS_ANDI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ANDISo8, PPC_INS_ANDIS, + {PPC_ANDI8_rec, + PPC_INS_ANDI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ANDIo, PPC_INS_ANDI, + {PPC_AND_rec, + PPC_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ANDIo8, PPC_INS_ANDI, + {PPC_ATTN, PPC_INS_ATTN, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ANDo, PPC_INS_AND, + {PPC_B, PPC_INS_B, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 1, 0 #endif -}, + }, -{ - PPC_ATTN, PPC_INS_ATTN, + {PPC_BA, PPC_INS_BA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 1, 0 #endif -}, + }, -{ - PPC_B, PPC_INS_B, + {PPC_BC, PPC_INS_BC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {0}, {0}, {0}, + 1, 0 #endif -}, + }, -{ - PPC_BA, PPC_INS_BA, + {PPC_BCC, PPC_INS_BEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {0}, {0}, {0}, 1, + 0 #endif -}, + }, -{ - PPC_BC, PPC_INS_BC, + {PPC_BCCA, PPC_INS_BEQA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {0}, {0}, {0}, 1, + 0 #endif -}, + }, -{ - PPC_BCC, PPC_INS_BEQ, + {PPC_BCCCTR, + PPC_INS_BEQCTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {0}, + {0}, + 1, + 1 #endif -}, + }, -{ - PPC_BCCA, PPC_INS_BEQA, + {PPC_BCCCTR8, + PPC_INS_BCTR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_CTR8, 0}, + {0}, + {PPC_GRP_MODE64, 0}, + 1, + 1 #endif -}, + }, -{ - PPC_BCCCTR, PPC_INS_BEQCTR, + {PPC_BCCCTRL, + PPC_INS_BEQCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCCTR8, PPC_INS_BCTR, + {PPC_BCCCTRL8, + PPC_INS_BCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 + {PPC_REG_CTR8, PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {PPC_GRP_MODE64, 0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCCTRL, PPC_INS_BEQCTRL, + {PPC_BCCL, + PPC_INS_BEQL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCCTRL8, PPC_INS_BCTRL, + {PPC_BCCLA, + PPC_INS_BEQLA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCL, PPC_INS_BEQL, + {PPC_BCCLR, + PPC_INS_BEQLR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_LR, PPC_REG_RM, 0}, + {0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCLA, PPC_INS_BEQLA, + {PPC_BCCLRL, + PPC_INS_BEQLRL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCLR, PPC_INS_BEQLR, + {PPC_BCCTR, + PPC_INS_BCCTR, #ifndef CAPSTONE_DIET - { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {0}, + {0}, + 1, + 1 #endif -}, + }, -{ - PPC_BCCLRL, PPC_INS_BEQLRL, + {PPC_BCCTR8, + PPC_INS_BCCTR, #ifndef CAPSTONE_DIET - { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR8, 0}, + {0}, + {PPC_GRP_MODE64, 0}, + 1, + 1 #endif -}, + }, -{ - PPC_BCCTR, PPC_INS_BCCTR, + {PPC_BCCTR8n, + PPC_INS_BCCTR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 + {PPC_REG_CTR8, 0}, + {0}, + {PPC_GRP_MODE64, 0}, + 1, + 1 #endif -}, + }, -{ - PPC_BCCTR8, PPC_INS_BCCTR, + {PPC_BCCTRL, + PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCTR8n, PPC_INS_BCCTR, + {PPC_BCCTRL8, + PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 + {PPC_REG_CTR8, PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {PPC_GRP_MODE64, 0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCTRL, PPC_INS_BCCTRL, + {PPC_BCCTRL8n, + PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR8, PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {PPC_GRP_MODE64, 0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCTRL8, PPC_INS_BCCTRL, + {PPC_BCCTRLn, + PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCCTRL8n, PPC_INS_BCCTRL, + {PPC_BCCTRn, + PPC_INS_BCCTR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {0}, + {0}, + 1, + 1 #endif -}, + }, -{ - PPC_BCCTRLn, PPC_INS_BCCTRL, + {PPC_BCDCFN_rec, + PPC_INS_BCDCFN, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCCTRn, PPC_INS_BCCTR, + {PPC_BCDCFSQ_rec, + PPC_INS_BCDCFSQ, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDCFNo, PPC_INS_BCDCFN, + {PPC_BCDCFZ_rec, + PPC_INS_BCDCFZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDCFSQo, PPC_INS_BCDCFSQ, + {PPC_BCDCPSGN_rec, + PPC_INS_BCDCPSGN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDCFZo, PPC_INS_BCDCFZ, + {PPC_BCDCTN_rec, + PPC_INS_BCDCTN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDCPSGNo, PPC_INS_BCDCPSGN, + {PPC_BCDCTSQ_rec, + PPC_INS_BCDCTSQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDCTNo, PPC_INS_BCDCTN, + {PPC_BCDCTZ_rec, + PPC_INS_BCDCTZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDCTSQo, PPC_INS_BCDCTSQ, + {PPC_BCDSETSGN_rec, + PPC_INS_BCDSETSGN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDCTZo, PPC_INS_BCDCTZ, + {PPC_BCDSR_rec, + PPC_INS_BCDSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDSETSGNo, PPC_INS_BCDSETSGN, + {PPC_BCDS_rec, + PPC_INS_BCDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDSRo, PPC_INS_BCDSR, + {PPC_BCDTRUNC_rec, + PPC_INS_BCDTRUNC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDSo, PPC_INS_BCDS, + {PPC_BCDUS_rec, + PPC_INS_BCDUS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDTRUNCo, PPC_INS_BCDTRUNC, + {PPC_BCDUTRUNC_rec, + PPC_INS_BCDUTRUNC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDUSo, PPC_INS_BCDUS, + {PPC_BCL, + PPC_INS_BCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BCDUTRUNCo, PPC_INS_BCDUTRUNC, + {PPC_BCLR, + PPC_INS_BCLR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_LR, PPC_REG_RM, 0}, + {0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCL, PPC_INS_BCL, + {PPC_BCLRL, + PPC_INS_BCLRL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 + {PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCLR, PPC_INS_BCLR, + {PPC_BCLRLn, + PPC_INS_BCLRL, #ifndef CAPSTONE_DIET - { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCLRL, PPC_INS_BCLRL, + {PPC_BCLRn, PPC_INS_BCLR, #ifndef CAPSTONE_DIET - { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {0}, {0}, {0}, 1, + 0 #endif -}, + }, -{ - PPC_BCLRLn, PPC_INS_BCLRL, + {PPC_BCLalways, + PPC_INS_BCL, #ifndef CAPSTONE_DIET - { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCLRn, PPC_INS_BCLR, + {PPC_BCLn, + PPC_INS_BCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCLalways, PPC_INS_BCL, + {PPC_BCTR, + PPC_INS_BCTR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {0}, + {0}, + 1, + 1 #endif -}, + }, -{ - PPC_BCLn, PPC_INS_BCL, + {PPC_BCTR8, + PPC_INS_BCTR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR8, 0}, + {0}, + {PPC_GRP_MODE64, 0}, + 1, + 1 #endif -}, + }, -{ - PPC_BCTR, PPC_INS_BCTR, + {PPC_BCTRL, + PPC_INS_BCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {PPC_GRP_MODE32, 0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCTR8, PPC_INS_BCTR, + {PPC_BCTRL8, + PPC_INS_BCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 + {PPC_REG_CTR8, PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {PPC_GRP_MODE64, 0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCTRL, PPC_INS_BCTRL, + {PPC_BCTRL8_LDinto_toc, + PPC_INS_BCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { PPC_GRP_MODE32, 0 }, 1, 0 + {PPC_REG_CTR8, PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {PPC_GRP_MODE64, 0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCTRL8, PPC_INS_BCTRL, + {PPC_BCn, PPC_INS_BC, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 + {0}, {0}, {0}, + 1, 0 #endif -}, + }, -{ - PPC_BCTRL8_LDinto_toc, PPC_INS_BCTRL, + {PPC_BDNZ, + PPC_INS_BDNZ, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BCn, PPC_INS_BC, + {PPC_BDNZ8, + PPC_INS_BDNZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_CTR8, 0}, + {PPC_REG_CTR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZ, PPC_INS_BDNZ, + {PPC_BDNZA, + PPC_INS_BDNZA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZ8, PPC_INS_BDNZ, + {PPC_BDNZAm, + PPC_INS_BDNZA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZA, PPC_INS_BDNZA, + {PPC_BDNZAp, + PPC_INS_BDNZA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZAm, PPC_INS_BDNZA, + {PPC_BDNZL, + PPC_INS_BDNZL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZAp, PPC_INS_BDNZA, + {PPC_BDNZLA, + PPC_INS_BDNZLA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZL, PPC_INS_BDNZL, + {PPC_BDNZLAm, + PPC_INS_BDNZLA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLA, PPC_INS_BDNZLA, + {PPC_BDNZLAp, + PPC_INS_BDNZLA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLAm, PPC_INS_BDNZLA, + {PPC_BDNZLR, + PPC_INS_BDNZLR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLAp, PPC_INS_BDNZLA, + {PPC_BDNZLR8, + PPC_INS_BDNZLR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0}, + {PPC_REG_CTR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLR, PPC_INS_BDNZLR, + {PPC_BDNZLRL, + PPC_INS_BDNZLRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLR8, PPC_INS_BDNZLR, + {PPC_BDNZLRLm, + PPC_INS_BDNZLRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLRL, PPC_INS_BDNZLRL, + {PPC_BDNZLRLp, + PPC_INS_BDNZLRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLRLm, PPC_INS_BDNZLRL, + {PPC_BDNZLRm, + PPC_INS_BDNZLR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLRLp, PPC_INS_BDNZLRL, + {PPC_BDNZLRp, + PPC_INS_BDNZLR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLRm, PPC_INS_BDNZLR, + {PPC_BDNZLm, + PPC_INS_BDNZL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLRp, PPC_INS_BDNZLR, + {PPC_BDNZLp, + PPC_INS_BDNZL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLm, PPC_INS_BDNZL, + {PPC_BDNZm, + PPC_INS_BDNZ, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZLp, PPC_INS_BDNZL, + {PPC_BDNZp, + PPC_INS_BDNZ, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZm, PPC_INS_BDNZ, + {PPC_BDZ, + PPC_INS_BDZ, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDNZp, PPC_INS_BDNZ, + {PPC_BDZ8, + PPC_INS_BDZ, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR8, 0}, + {PPC_REG_CTR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZ, PPC_INS_BDZ, + {PPC_BDZA, + PPC_INS_BDZA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZ8, PPC_INS_BDZ, + {PPC_BDZAm, + PPC_INS_BDZA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZA, PPC_INS_BDZA, + {PPC_BDZAp, + PPC_INS_BDZA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZAm, PPC_INS_BDZA, + {PPC_BDZL, + PPC_INS_BDZL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZAp, PPC_INS_BDZA, + {PPC_BDZLA, + PPC_INS_BDZLA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZL, PPC_INS_BDZL, + {PPC_BDZLAm, + PPC_INS_BDZLA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLA, PPC_INS_BDZLA, + {PPC_BDZLAp, + PPC_INS_BDZLA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLAm, PPC_INS_BDZLA, + {PPC_BDZLR, + PPC_INS_BDZLR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLAp, PPC_INS_BDZLA, + {PPC_BDZLR8, + PPC_INS_BDZLR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0}, + {PPC_REG_CTR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLR, PPC_INS_BDZLR, + {PPC_BDZLRL, + PPC_INS_BDZLRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLR8, PPC_INS_BDZLR, + {PPC_BDZLRLm, + PPC_INS_BDZLRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLRL, PPC_INS_BDZLRL, + {PPC_BDZLRLp, + PPC_INS_BDZLRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLRLm, PPC_INS_BDZLRL, + {PPC_BDZLRm, + PPC_INS_BDZLR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLRLp, PPC_INS_BDZLRL, + {PPC_BDZLRp, + PPC_INS_BDZLR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLRm, PPC_INS_BDZLR, + {PPC_BDZLm, + PPC_INS_BDZL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLRp, PPC_INS_BDZLR, + {PPC_BDZLp, + PPC_INS_BDZL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLm, PPC_INS_BDZL, + {PPC_BDZm, + PPC_INS_BDZ, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZLp, PPC_INS_BDZL, + {PPC_BDZp, + PPC_INS_BDZ, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZm, PPC_INS_BDZ, + {PPC_BL, + PPC_INS_BL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BDZp, PPC_INS_BDZ, + {PPC_BL8, + PPC_INS_BL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BL, PPC_INS_BL, + {PPC_BL8_NOP, + PPC_INS_BL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BL8, PPC_INS_BL, + {PPC_BL8_NOP_TLS, + PPC_INS_BL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BL8_NOP, PPC_INS_BL, + {PPC_BL8_TLS, + PPC_INS_BL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BL8_NOP_TLS, PPC_INS_BL, + {PPC_BL8_TLS_, + PPC_INS_BL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BL8_TLS, PPC_INS_BL, + {PPC_BLA, + PPC_INS_BLA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BL8_TLS_, PPC_INS_BL, + {PPC_BLA8, + PPC_INS_BLA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BLA, PPC_INS_BLA, + {PPC_BLA8_NOP, + PPC_INS_BLA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR8, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BLA8, PPC_INS_BLA, + {PPC_BLR, + PPC_INS_BLR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 + {PPC_REG_LR, PPC_REG_RM, 0}, + {0}, + {PPC_GRP_MODE32, 0}, + 1, + 0 #endif -}, + }, -{ - PPC_BLA8_NOP, PPC_INS_BLA, + {PPC_BLR8, + PPC_INS_BLR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 + {PPC_REG_LR8, PPC_REG_RM, 0}, + {0}, + {PPC_GRP_MODE64, 0}, + 1, + 0 #endif -}, + }, -{ - PPC_BLR, PPC_INS_BLR, + {PPC_BLRL, + PPC_INS_BLRL, #ifndef CAPSTONE_DIET - { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE32, 0 }, 1, 0 + {PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BLR8, PPC_INS_BLR, + {PPC_BL_TLS, + PPC_INS_BL, #ifndef CAPSTONE_DIET - { PPC_REG_LR8, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 + {PPC_REG_RM, 0}, + {PPC_REG_LR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_BLRL, PPC_INS_BLRL, + {PPC_BPERMD, PPC_INS_BPERMD, #ifndef CAPSTONE_DIET - { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_BL_TLS, PPC_INS_BL, + {PPC_BRINC, PPC_INS_BRINC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_BPERMD, PPC_INS_BPERMD, + {PPC_CLRBHRB, + PPC_INS_CLRBHRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_BRINC, PPC_INS_BRINC, + {PPC_CMPB, PPC_INS_CMPB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CLRBHRB, PPC_INS_CLRBHRB, + {PPC_CMPB8, PPC_INS_CMPB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPB, PPC_INS_CMPB, + {PPC_CMPD, PPC_INS_CMPD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPB8, PPC_INS_CMPB, + {PPC_CMPDI, PPC_INS_CMPDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPD, PPC_INS_CMPD, + {PPC_CMPEQB, PPC_INS_CMPEQB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPDI, PPC_INS_CMPDI, + {PPC_CMPLD, PPC_INS_CMPL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPEQB, PPC_INS_CMPEQB, + {PPC_CMPLDI, PPC_INS_CMPLDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPLD, PPC_INS_CMPL, + {PPC_CMPLW, PPC_INS_CMPL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPLDI, PPC_INS_CMPLDI, + {PPC_CMPLWI, PPC_INS_CMPLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPLW, PPC_INS_CMPL, + {PPC_CMPRB, PPC_INS_CMPRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPLWI, PPC_INS_CMPLWI, + {PPC_CMPW, PPC_INS_CMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPRB, PPC_INS_CMPRB, + {PPC_CMPWI, PPC_INS_CMPWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPW, PPC_INS_CMP, + {PPC_CNTLZD, PPC_INS_CNTLZD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CMPWI, PPC_INS_CMPWI, + {PPC_CNTLZD_rec, + PPC_INS_CNTLZD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CNTLZD, PPC_INS_CNTLZD, + {PPC_CNTLZW, PPC_INS_CNTLZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CNTLZDo, PPC_INS_CNTLZD, + {PPC_CNTLZW8, + PPC_INS_CNTLZW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CNTLZW, PPC_INS_CNTLZW, + {PPC_CNTLZW8_rec, + PPC_INS_CNTLZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CNTLZW8, PPC_INS_CNTLZW, + {PPC_CNTLZW_rec, + PPC_INS_CNTLZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CNTLZW8o, PPC_INS_CNTLZW, + {PPC_CNTTZD, PPC_INS_CNTTZD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CNTLZWo, PPC_INS_CNTLZW, + {PPC_CNTTZD_rec, + PPC_INS_CNTTZD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CNTTZD, PPC_INS_CNTTZD, + {PPC_CNTTZW, PPC_INS_CNTTZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CNTTZDo, PPC_INS_CNTTZD, + {PPC_CNTTZW_rec, + PPC_INS_CNTTZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CNTTZW, PPC_INS_CNTTZW, + {PPC_CP_ABORT, + PPC_INS_CP_ABORT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CNTTZWo, PPC_INS_CNTTZW, + {PPC_CP_COPY, + PPC_INS_COPY, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CP_ABORT, PPC_INS_CP_ABORT, + {PPC_CP_PASTE_rec, + PPC_INS_PASTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CP_COPY, PPC_INS_COPY, + {PPC_CP_PASTE_rec, + PPC_INS_PASTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CP_PASTE, PPC_INS_PASTE, + {PPC_CR6SET, PPC_INS_CREQV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CR1EQ, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CP_PASTEo, PPC_INS_PASTE, + {PPC_CR6UNSET, + PPC_INS_CRXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1EQ, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CR6SET, PPC_INS_CREQV, + {PPC_CRAND, PPC_INS_CRAND, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CR6UNSET, PPC_INS_CRXOR, + {PPC_CRANDC, PPC_INS_CRANDC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CRAND, PPC_INS_CRAND, + {PPC_CREQV, PPC_INS_CREQV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CRANDC, PPC_INS_CRANDC, + {PPC_CRNAND, PPC_INS_CRNAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_CREQV, PPC_INS_CREQV, + {PPC_CRNOR, PPC_INS_CRNOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CRNAND, PPC_INS_CRNAND, + {PPC_CROR, PPC_INS_CROR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CRNOR, PPC_INS_CRNOR, + {PPC_CRORC, PPC_INS_CRORC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CROR, PPC_INS_CROR, + {PPC_CRSET, PPC_INS_CRSET, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CRORC, PPC_INS_CRORC, + {PPC_CRUNSET, + PPC_INS_CRXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_CRSET, PPC_INS_CRSET, + {PPC_CRXOR, PPC_INS_CRXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CRUNSET, PPC_INS_CRXOR, + {PPC_DARN, PPC_INS_DARN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_CRXOR, PPC_INS_CRXOR, + {PPC_DCBA, PPC_INS_DCBA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_DARN, PPC_INS_DARN, + {PPC_DCBF, PPC_INS_DCBF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBA, PPC_INS_DCBA, + {PPC_DCBFEP, PPC_INS_DCBFEP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBF, PPC_INS_DCBF, + {PPC_DCBI, PPC_INS_DCBI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBFEP, PPC_INS_DCBFEP, + {PPC_DCBST, PPC_INS_DCBST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBI, PPC_INS_DCBI, + {PPC_DCBSTEP, + PPC_INS_DCBSTEP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_DCBST, PPC_INS_DCBST, + {PPC_DCBT, PPC_INS_DCBT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBSTEP, PPC_INS_DCBSTEP, + {PPC_DCBTEP, PPC_INS_DCBTEP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBT, PPC_INS_DCBT, + {PPC_DCBTST, PPC_INS_DCBTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBTEP, PPC_INS_DCBTEP, + {PPC_DCBTSTEP, + PPC_INS_DCBTSTEP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_DCBTST, PPC_INS_DCBTST, + {PPC_DCBZ, PPC_INS_DCBZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_DCBTSTEP, PPC_INS_DCBTSTEP, + {PPC_DCBZEP, PPC_INS_DCBZEP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, - -{ - PPC_DCBZ, PPC_INS_DCBZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DCBZEP, PPC_INS_DCBZEP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DCBZL, PPC_INS_DCBZL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DCBZLEP, PPC_INS_DCBZLEP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DCCCI, PPC_INS_DCCCI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVD, PPC_INS_DIVD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVDE, PPC_INS_DIVDE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVDEU, PPC_INS_DIVDEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVDEUo, PPC_INS_DIVDEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVDEo, PPC_INS_DIVDE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVDU, PPC_INS_DIVDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVDUo, PPC_INS_DIVDU, -#ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVDo, PPC_INS_DIVD, -#ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVW, PPC_INS_DIVW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVWE, PPC_INS_DIVWE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVWEU, PPC_INS_DIVWEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVWEUo, PPC_INS_DIVWEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVWEo, PPC_INS_DIVWE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVWU, PPC_INS_DIVWU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVWUo, PPC_INS_DIVWU, -#ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DIVWo, PPC_INS_DIVW, -#ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_DSS, PPC_INS_DSS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_DSSALL, PPC_INS_DSSALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_DST, PPC_INS_DST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_DST64, PPC_INS_DST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_DSTST, PPC_INS_DSTST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_DSTST64, PPC_INS_DSTST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_DSTSTT, PPC_INS_DSTSTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_DSTSTT64, PPC_INS_DSTSTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_DSTT, PPC_INS_DSTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_DSTT64, PPC_INS_DSTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDABS, PPC_INS_EFDABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDADD, PPC_INS_EFDADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCFS, PPC_INS_EFDCFS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCFSF, PPC_INS_EFDCFSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCFSI, PPC_INS_EFDCFSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCFSID, PPC_INS_EFDCFSID, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCFUF, PPC_INS_EFDCFUF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCFUI, PPC_INS_EFDCFUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCFUID, PPC_INS_EFDCFUID, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCMPEQ, PPC_INS_EFDCMPEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCMPGT, PPC_INS_EFDCMPGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCMPLT, PPC_INS_EFDCMPLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCTSF, PPC_INS_EFDCTSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCTSI, PPC_INS_EFDCTSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCTSIDZ, PPC_INS_EFDCTSIDZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCTSIZ, PPC_INS_EFDCTSIZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCTUF, PPC_INS_EFDCTUF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCTUI, PPC_INS_EFDCTUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCTUIDZ, PPC_INS_EFDCTUIDZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDCTUIZ, PPC_INS_EFDCTUIZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDDIV, PPC_INS_EFDDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDMUL, PPC_INS_EFDMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDNABS, PPC_INS_EFDNABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDNEG, PPC_INS_EFDNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDSUB, PPC_INS_EFDSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDTSTEQ, PPC_INS_EFDTSTEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDTSTGT, PPC_INS_EFDTSTGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFDTSTLT, PPC_INS_EFDTSTLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSABS, PPC_INS_EFSABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSADD, PPC_INS_EFSADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCFD, PPC_INS_EFSCFD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCFSF, PPC_INS_EFSCFSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCFSI, PPC_INS_EFSCFSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCFUF, PPC_INS_EFSCFUF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCFUI, PPC_INS_EFSCFUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCMPEQ, PPC_INS_EFSCMPEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCMPGT, PPC_INS_EFSCMPGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCMPLT, PPC_INS_EFSCMPLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCTSF, PPC_INS_EFSCTSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCTSI, PPC_INS_EFSCTSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCTSIZ, PPC_INS_EFSCTSIZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCTUF, PPC_INS_EFSCTUF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCTUI, PPC_INS_EFSCTUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSCTUIZ, PPC_INS_EFSCTUIZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSDIV, PPC_INS_EFSDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSMUL, PPC_INS_EFSMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSNABS, PPC_INS_EFSNABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSNEG, PPC_INS_EFSNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSSUB, PPC_INS_EFSSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSTSTEQ, PPC_INS_EFSTSTEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSTSTGT, PPC_INS_EFSTSTGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EFSTSTLT, PPC_INS_EFSTSTLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EQV, PPC_INS_EQV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EQV8, PPC_INS_EQV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EQV8o, PPC_INS_EQV, -#ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EQVo, PPC_INS_EQV, -#ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVABS, PPC_INS_EVABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVADDIW, PPC_INS_EVADDIW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVADDSMIAAW, PPC_INS_EVADDSMIAAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVADDSSIAAW, PPC_INS_EVADDSSIAAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVADDUMIAAW, PPC_INS_EVADDUMIAAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVADDUSIAAW, PPC_INS_EVADDUSIAAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVADDW, PPC_INS_EVADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVAND, PPC_INS_EVAND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVANDC, PPC_INS_EVANDC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVCMPEQ, PPC_INS_EVCMPEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVCMPGTS, PPC_INS_EVCMPGTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVCMPGTU, PPC_INS_EVCMPGTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVCMPLTS, PPC_INS_EVCMPLTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVCMPLTU, PPC_INS_EVCMPLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVCNTLSW, PPC_INS_EVCNTLSW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVCNTLZW, PPC_INS_EVCNTLZW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVDIVWS, PPC_INS_EVDIVWS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVDIVWU, PPC_INS_EVDIVWU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVEQV, PPC_INS_EVEQV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVEXTSB, PPC_INS_EVEXTSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVEXTSH, PPC_INS_EVEXTSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSABS, PPC_INS_EVFSABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSADD, PPC_INS_EVFSADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCFSF, PPC_INS_EVFSCFSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCFSI, PPC_INS_EVFSCFSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCFUF, PPC_INS_EVFSCFUF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCFUI, PPC_INS_EVFSCFUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCMPEQ, PPC_INS_EVFSCMPEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCMPGT, PPC_INS_EVFSCMPGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCMPLT, PPC_INS_EVFSCMPLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCTSF, PPC_INS_EVFSCTSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCTSI, PPC_INS_EVFSCTSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCTSIZ, PPC_INS_EVFSCTSIZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCTUF, PPC_INS_EVFSCTSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCTUI, PPC_INS_EVFSCTUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSCTUIZ, PPC_INS_EVFSCTSIZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSDIV, PPC_INS_EVFSDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSMUL, PPC_INS_EVFSMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSNABS, PPC_INS_EVFSNABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSNEG, PPC_INS_EVFSNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSSUB, PPC_INS_EVFSSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSTSTEQ, PPC_INS_EVFSTSTEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSTSTGT, PPC_INS_EVFSTSTGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVFSTSTLT, PPC_INS_EVFSTSTLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLDD, PPC_INS_EVLDD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLDDX, PPC_INS_EVLDDX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLDH, PPC_INS_EVLDH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLDHX, PPC_INS_EVLDHX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLDW, PPC_INS_EVLDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLDWX, PPC_INS_EVLDWX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLHHESPLAT, PPC_INS_EVLHHESPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLHHESPLATX, PPC_INS_EVLHHESPLATX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLHHOSSPLAT, PPC_INS_EVLHHOSSPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLHHOSSPLATX, PPC_INS_EVLHHOSSPLATX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLHHOUSPLAT, PPC_INS_EVLHHOUSPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLHHOUSPLATX, PPC_INS_EVLHHOUSPLATX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWHE, PPC_INS_EVLWHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWHEX, PPC_INS_EVLWHEX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWHOS, PPC_INS_EVLWHOS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWHOSX, PPC_INS_EVLWHOSX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWHOU, PPC_INS_EVLWHOU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWHOUX, PPC_INS_EVLWHOUX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWHSPLAT, PPC_INS_EVLWHSPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWHSPLATX, PPC_INS_EVLWHSPLATX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWWSPLAT, PPC_INS_EVLWWSPLAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVLWWSPLATX, PPC_INS_EVLWWSPLATX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMERGEHI, PPC_INS_EVMERGEHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMERGEHILO, PPC_INS_EVMERGEHILO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMERGELO, PPC_INS_EVMERGELO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMERGELOHI, PPC_INS_EVMERGELOHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHEGSMFAA, PPC_INS_EVMHEGSMFAA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHEGSMFAN, PPC_INS_EVMHEGSMFAN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHEGSMIAA, PPC_INS_EVMHEGSMIAA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHEGSMIAN, PPC_INS_EVMHEGSMIAN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHEGUMIAA, PPC_INS_EVMHEGUMIAA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHEGUMIAN, PPC_INS_EVMHEGUMIAN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHESMF, PPC_INS_EVMHESMF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHESMFA, PPC_INS_EVMHESMFA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHESMFAAW, PPC_INS_EVMHESMFAAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHESMFANW, PPC_INS_EVMHESMFANW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHESMI, PPC_INS_EVMHESMI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, - -{ - PPC_EVMHESMIA, PPC_INS_EVMHESMIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 -#endif -}, + }, -{ - PPC_EVMHESMIAAW, PPC_INS_EVMHESMIAAW, + {PPC_DCBZL, PPC_INS_DCBZL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHESMIANW, PPC_INS_EVMHESMIANW, + {PPC_DCBZLEP, + PPC_INS_DCBZLEP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHESSF, PPC_INS_EVMHESSF, + {PPC_DCCCI, PPC_INS_DCCCI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_PPC4XX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHESSFA, PPC_INS_EVMHESSFA, + {PPC_DIVD, PPC_INS_DIVD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHESSFAAW, PPC_INS_EVMHESSFAAW, + {PPC_DIVDE, PPC_INS_DIVDE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHESSFANW, PPC_INS_EVMHESSFANW, + {PPC_DIVDEU, PPC_INS_DIVDEU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHESSIAAW, PPC_INS_EVMHESSIAAW, + {PPC_DIVDEU_rec, + PPC_INS_DIVDEU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHESSIANW, PPC_INS_EVMHESSIANW, + {PPC_DIVDE_rec, + PPC_INS_DIVDE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHEUMI, PPC_INS_EVMHEUMI, + {PPC_DIVDU, PPC_INS_DIVDU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHEUMIA, PPC_INS_EVMHEUMIA, + {PPC_DIVDU_rec, + PPC_INS_DIVDU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHEUMIAAW, PPC_INS_EVMHEUMIAAW, + {PPC_DIVD_rec, + PPC_INS_DIVD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHEUMIANW, PPC_INS_EVMHEUMIANW, + {PPC_DIVW, PPC_INS_DIVW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHEUSIAAW, PPC_INS_EVMHEUSIAAW, + {PPC_DIVWE, PPC_INS_DIVWE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHEUSIANW, PPC_INS_EVMHEUSIANW, + {PPC_DIVWEU, PPC_INS_DIVWEU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOGSMFAA, PPC_INS_EVMHOGSMFAA, + {PPC_DIVWEU_rec, + PPC_INS_DIVWEU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOGSMFAN, PPC_INS_EVMHOGSMFAN, + {PPC_DIVWE_rec, + PPC_INS_DIVWE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOGSMIAA, PPC_INS_EVMHOGSMIAA, + {PPC_DIVWU, PPC_INS_DIVWU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOGSMIAN, PPC_INS_EVMHOGSMIAN, + {PPC_DIVWU_rec, + PPC_INS_DIVWU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOGUMIAA, PPC_INS_EVMHOGUMIAA, + {PPC_DIVW_rec, + PPC_INS_DIVW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOGUMIAN, PPC_INS_EVMHOGUMIAN, + {PPC_DSS, PPC_INS_DSS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSMF, PPC_INS_EVMHOSMF, + {PPC_DSSALL, + PPC_INS_DSSALL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSMFA, PPC_INS_EVMHOSMFA, + {PPC_DST, PPC_INS_DST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSMFAAW, PPC_INS_EVMHOSMFAAW, + {PPC_DST64, PPC_INS_DST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSMFANW, PPC_INS_EVMHOSMFANW, + {PPC_DSTST, PPC_INS_DSTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSMI, PPC_INS_EVMHOSMI, + {PPC_DSTST64, + PPC_INS_DSTST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSMIA, PPC_INS_EVMHOSMIA, + {PPC_DSTSTT, + PPC_INS_DSTSTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSMIAAW, PPC_INS_EVMHOSMIAAW, + {PPC_DSTSTT64, + PPC_INS_DSTSTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSMIANW, PPC_INS_EVMHOSMIANW, + {PPC_DSTT, PPC_INS_DSTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSSF, PPC_INS_EVMHOSSF, + {PPC_DSTT64, PPC_INS_DSTT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSSFA, PPC_INS_EVMHOSSFA, + {PPC_EFDABS, PPC_INS_EFDABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSSFAAW, PPC_INS_EVMHOSSFAAW, + {PPC_EFDADD, PPC_INS_EFDADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSSFANW, PPC_INS_EVMHOSSFANW, + {PPC_EFDCFS, PPC_INS_EFDCFS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSSIAAW, PPC_INS_EVMHOSSIAAW, + {PPC_EFDCFSF, + PPC_INS_EFDCFSF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOSSIANW, PPC_INS_EVMHOSSIANW, + {PPC_EFDCFSI, + PPC_INS_EFDCFSI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOUMI, PPC_INS_EVMHOUMI, + {PPC_EFDCFSID, + PPC_INS_EFDCFSID, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOUMIA, PPC_INS_EVMHOUMIA, + {PPC_EFDCFUF, + PPC_INS_EFDCFUF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOUMIAAW, PPC_INS_EVMHOUMIAAW, + {PPC_EFDCFUI, + PPC_INS_EFDCFUI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOUMIANW, PPC_INS_EVMHOUMIANW, + {PPC_EFDCFUID, + PPC_INS_EFDCFUID, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOUSIAAW, PPC_INS_EVMHOUSIAAW, + {PPC_EFDCMPEQ, + PPC_INS_EFDCMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMHOUSIANW, PPC_INS_EVMHOUSIANW, + {PPC_EFDCMPGT, + PPC_INS_EFDCMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMRA, PPC_INS_EVMRA, + {PPC_EFDCMPLT, + PPC_INS_EFDCMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWHSMF, PPC_INS_EVMWHSMF, + {PPC_EFDCTSF, + PPC_INS_EFDCTSF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWHSMFA, PPC_INS_EVMWHSMFA, + {PPC_EFDCTSI, + PPC_INS_EFDCTSI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWHSMI, PPC_INS_EVMWHSMI, + {PPC_EFDCTSIDZ, + PPC_INS_EFDCTSIDZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWHSMIA, PPC_INS_EVMWHSMIA, + {PPC_EFDCTSIZ, + PPC_INS_EFDCTSIZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWHSSF, PPC_INS_EVMWHSSF, + {PPC_EFDCTUF, + PPC_INS_EFDCTUF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWHSSFA, PPC_INS_EVMWHSSFA, + {PPC_EFDCTUI, + PPC_INS_EFDCTUI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWHUMI, PPC_INS_EVMWHUMI, + {PPC_EFDCTUIDZ, + PPC_INS_EFDCTUIDZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWHUMIA, PPC_INS_EVMWHUMIA, + {PPC_EFDCTUIZ, + PPC_INS_EFDCTUIZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWLSMIAAW, PPC_INS_EVMWLSMIAAW, + {PPC_EFDDIV, PPC_INS_EFDDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMWLSMIANW, PPC_INS_EVMWLSMIANW, + {PPC_EFDMUL, PPC_INS_EFDMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMWLSSIAAW, PPC_INS_EVMWLSSIAAW, + {PPC_EFDNABS, + PPC_INS_EFDNABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWLSSIANW, PPC_INS_EVMWLSSIANW, + {PPC_EFDNEG, PPC_INS_EFDNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMWLUMI, PPC_INS_EVMWLUMI, + {PPC_EFDSUB, PPC_INS_EFDSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMWLUMIA, PPC_INS_EVMWLUMIA, + {PPC_EFDTSTEQ, + PPC_INS_EFDTSTEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWLUMIAAW, PPC_INS_EVMWLUMIAAW, + {PPC_EFDTSTGT, + PPC_INS_EFDTSTGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWLUMIANW, PPC_INS_EVMWLUMIANW, + {PPC_EFDTSTLT, + PPC_INS_EFDTSTLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWLUSIAAW, PPC_INS_EVMWLUSIAAW, + {PPC_EFSABS, PPC_INS_EFSABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMWLUSIANW, PPC_INS_EVMWLUSIANW, + {PPC_EFSADD, PPC_INS_EFSADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMWSMF, PPC_INS_EVMWSMF, + {PPC_EFSCFD, PPC_INS_EFSCFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMWSMFA, PPC_INS_EVMWSMFA, + {PPC_EFSCFSF, + PPC_INS_EFSCFSF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSMFAA, PPC_INS_EVMWSMFAA, + {PPC_EFSCFSI, + PPC_INS_EFSCFSI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSMFAN, PPC_INS_EVMWSMFAN, + {PPC_EFSCFUF, + PPC_INS_EFSCFUF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSMI, PPC_INS_EVMWSMI, + {PPC_EFSCFUI, + PPC_INS_EFSCFUI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSMIA, PPC_INS_EVMWSMIA, + {PPC_EFSCMPEQ, + PPC_INS_EFSCMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSMIAA, PPC_INS_EVMWSMIAA, + {PPC_EFSCMPGT, + PPC_INS_EFSCMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSMIAN, PPC_INS_EVMWSMIAN, + {PPC_EFSCMPLT, + PPC_INS_EFSCMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSSF, PPC_INS_EVMWSSF, + {PPC_EFSCTSF, + PPC_INS_EFSCTSF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSSFA, PPC_INS_EVMWSSFA, + {PPC_EFSCTSI, + PPC_INS_EFSCTSI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSSFAA, PPC_INS_EVMWSSFAA, + {PPC_EFSCTSIZ, + PPC_INS_EFSCTSIZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWSSFAN, PPC_INS_EVMWSSFAN, + {PPC_EFSCTUF, + PPC_INS_EFSCTUF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWUMI, PPC_INS_EVMWUMI, + {PPC_EFSCTUI, + PPC_INS_EFSCTUI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWUMIA, PPC_INS_EVMWUMIA, + {PPC_EFSCTUIZ, + PPC_INS_EFSCTUIZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVMWUMIAA, PPC_INS_EVMWUMIAA, + {PPC_EFSDIV, PPC_INS_EFSDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVMWUMIAN, PPC_INS_EVMWUMIAN, + {PPC_EFSMUL, PPC_INS_EFSMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVNAND, PPC_INS_EVNAND, + {PPC_EFSNABS, + PPC_INS_EFSNABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVNEG, PPC_INS_EVNEG, + {PPC_EFSNEG, PPC_INS_EFSNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVNOR, PPC_INS_EVNOR, + {PPC_EFSSUB, PPC_INS_EFSSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVOR, PPC_INS_EVOR, + {PPC_EFSTSTEQ, + PPC_INS_EFSTSTEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVORC, PPC_INS_EVORC, + {PPC_EFSTSTGT, + PPC_INS_EFSTSTGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVRLW, PPC_INS_EVRLW, + {PPC_EFSTSTLT, + PPC_INS_EFSTSTLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVRLWI, PPC_INS_EVRLWI, + {PPC_EQV, PPC_INS_EQV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVRNDW, PPC_INS_EVRNDW, + {PPC_EQV8, PPC_INS_EQV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_EVSEL, PPC_INS_EVSEL, + {PPC_EQV8_rec, + PPC_INS_EQV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSLW, PPC_INS_EVSLW, + {PPC_EQV_rec, + PPC_INS_EQV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSLWI, PPC_INS_EVSLWI, + {PPC_EVABS, PPC_INS_EVABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVSPLATFI, PPC_INS_EVSPLATFI, + {PPC_EVADDIW, + PPC_INS_EVADDIW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSPLATI, PPC_INS_EVSPLATI, + {PPC_EVADDSMIAAW, + PPC_INS_EVADDSMIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSRWIS, PPC_INS_EVSRWIS, + {PPC_EVADDSSIAAW, + PPC_INS_EVADDSSIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSRWIU, PPC_INS_EVSRWIU, + {PPC_EVADDUMIAAW, + PPC_INS_EVADDUMIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSRWS, PPC_INS_EVSRWS, + {PPC_EVADDUSIAAW, + PPC_INS_EVADDUSIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSRWU, PPC_INS_EVSRWU, + {PPC_EVADDW, + PPC_INS_EVADDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTDD, PPC_INS_EVSTDD, + {PPC_EVAND, PPC_INS_EVAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVSTDDX, PPC_INS_EVSTDDX, + {PPC_EVANDC, + PPC_INS_EVANDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTDH, PPC_INS_EVSTDH, + {PPC_EVCMPEQ, + PPC_INS_EVCMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTDHX, PPC_INS_EVSTDHX, + {PPC_EVCMPGTS, + PPC_INS_EVCMPGTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTDW, PPC_INS_EVSTDW, + {PPC_EVCMPGTU, + PPC_INS_EVCMPGTU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTDWX, PPC_INS_EVSTDWX, + {PPC_EVCMPLTS, + PPC_INS_EVCMPLTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTWHE, PPC_INS_EVSTWHE, + {PPC_EVCMPLTU, + PPC_INS_EVCMPLTU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTWHEX, PPC_INS_EVSTWHEX, + {PPC_EVCNTLSW, + PPC_INS_EVCNTLSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTWHO, PPC_INS_EVSTWHO, + {PPC_EVCNTLZW, + PPC_INS_EVCNTLZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTWHOX, PPC_INS_EVSTWHOX, + {PPC_EVDIVWS, + PPC_INS_EVDIVWS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTWWE, PPC_INS_EVSTWWE, + {PPC_EVDIVWU, + PPC_INS_EVDIVWU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTWWEX, PPC_INS_EVSTWWEX, + {PPC_EVEQV, PPC_INS_EVEQV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_EVSTWWO, PPC_INS_EVSTWWO, + {PPC_EVEXTSB, + PPC_INS_EVEXTSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSTWWOX, PPC_INS_EVSTWWOX, + {PPC_EVEXTSH, + PPC_INS_EVEXTSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSUBFSMIAAW, PPC_INS_EVSUBFSMIAAW, + {PPC_EVFSABS, + PPC_INS_EVFSABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSUBFSSIAAW, PPC_INS_EVSUBFSSIAAW, + {PPC_EVFSADD, + PPC_INS_EVFSADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSUBFUMIAAW, PPC_INS_EVSUBFUMIAAW, + {PPC_EVFSCFSF, + PPC_INS_EVFSCFSF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSUBFUSIAAW, PPC_INS_EVSUBFUSIAAW, + {PPC_EVFSCFSI, + PPC_INS_EVFSCFSI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSUBFW, PPC_INS_EVSUBFW, + {PPC_EVFSCFUF, + PPC_INS_EVFSCFUF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVSUBIFW, PPC_INS_EVSUBIFW, + {PPC_EVFSCFUI, + PPC_INS_EVFSCFUI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EVXOR, PPC_INS_EVXOR, + {PPC_EVFSCMPEQ, + PPC_INS_EVFSCMPEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSB, PPC_INS_EXTSB, + {PPC_EVFSCMPGT, + PPC_INS_EVFSCMPGT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSB8, PPC_INS_EXTSB, + {PPC_EVFSCMPLT, + PPC_INS_EVFSCMPLT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSB8_32_64, PPC_INS_EXTSB, + {PPC_EVFSCTSF, + PPC_INS_EVFSCTSF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSB8o, PPC_INS_EXTSB, + {PPC_EVFSCTSI, + PPC_INS_EVFSCTSI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSBo, PPC_INS_EXTSB, + {PPC_EVFSCTSIZ, + PPC_INS_EVFSCTSIZ, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSH, PPC_INS_EXTSH, + {PPC_EVFSCTUF, + PPC_INS_EVFSCTSF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSH8, PPC_INS_EXTSH, + {PPC_EVFSCTUI, + PPC_INS_EVFSCTUI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSH8_32_64, PPC_INS_EXTSH, + {PPC_EVFSCTUIZ, + PPC_INS_EVFSCTSIZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSH8o, PPC_INS_EXTSH, + {PPC_EVFSDIV, + PPC_INS_EVFSDIV, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSHo, PPC_INS_EXTSH, + {PPC_EVFSMUL, + PPC_INS_EVFSMUL, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSW, PPC_INS_EXTSW, + {PPC_EVFSNABS, + PPC_INS_EVFSNABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSWSLI, PPC_INS_EXTSWSLI, + {PPC_EVFSNEG, + PPC_INS_EVFSNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSWSLIo, PPC_INS_EXTSWSLI, + {PPC_EVFSSUB, + PPC_INS_EVFSSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSW_32_64, PPC_INS_EXTSW, + {PPC_EVFSTSTEQ, + PPC_INS_EVFSTSTEQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSW_32_64o, PPC_INS_EXTSW, + {PPC_EVFSTSTGT, + PPC_INS_EVFSTSTGT, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EXTSWo, PPC_INS_EXTSW, + {PPC_EVFSTSTLT, + PPC_INS_EVFSTSTLT, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_EnforceIEIO, PPC_INS_EIEIO, + {PPC_EVLDD, PPC_INS_EVLDD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_FABSD, PPC_INS_FABS, + {PPC_EVLDDX, + PPC_INS_EVLDDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FABSDo, PPC_INS_FABS, + {PPC_EVLDH, PPC_INS_EVLDH, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_FABSS, PPC_INS_FABS, + {PPC_EVLDHX, + PPC_INS_EVLDHX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FABSSo, PPC_INS_FABS, + {PPC_EVLDW, PPC_INS_EVLDW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_FADD, PPC_INS_FADD, + {PPC_EVLDWX, + PPC_INS_EVLDWX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FADDS, PPC_INS_FADDS, + {PPC_EVLHHESPLAT, + PPC_INS_EVLHHESPLAT, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FADDSo, PPC_INS_FADDS, + {PPC_EVLHHESPLATX, + PPC_INS_EVLHHESPLATX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FADDo, PPC_INS_FADD, + {PPC_EVLHHOSSPLAT, + PPC_INS_EVLHHOSSPLAT, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCFID, PPC_INS_FCFID, + {PPC_EVLHHOSSPLATX, + PPC_INS_EVLHHOSSPLATX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCFIDS, PPC_INS_FCFIDS, + {PPC_EVLHHOUSPLAT, + PPC_INS_EVLHHOUSPLAT, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCFIDSo, PPC_INS_FCFIDS, + {PPC_EVLHHOUSPLATX, + PPC_INS_EVLHHOUSPLATX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCFIDU, PPC_INS_FCFIDU, + {PPC_EVLWHE, + PPC_INS_EVLWHE, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCFIDUS, PPC_INS_FCFIDUS, + {PPC_EVLWHEX, + PPC_INS_EVLWHEX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCFIDUSo, PPC_INS_FCFIDUS, + {PPC_EVLWHOS, + PPC_INS_EVLWHOS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCFIDUo, PPC_INS_FCFIDU, + {PPC_EVLWHOSX, + PPC_INS_EVLWHOSX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCFIDo, PPC_INS_FCFID, + {PPC_EVLWHOU, + PPC_INS_EVLWHOU, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCMPUD, PPC_INS_FCMPU, + {PPC_EVLWHOUX, + PPC_INS_EVLWHOUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCMPUS, PPC_INS_FCMPU, + {PPC_EVLWHSPLAT, + PPC_INS_EVLWHSPLAT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCPSGND, PPC_INS_FCPSGN, + {PPC_EVLWHSPLATX, + PPC_INS_EVLWHSPLATX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCPSGNDo, PPC_INS_FCPSGN, + {PPC_EVLWWSPLAT, + PPC_INS_EVLWWSPLAT, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCPSGNS, PPC_INS_FCPSGN, + {PPC_EVLWWSPLATX, + PPC_INS_EVLWWSPLATX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCPSGNSo, PPC_INS_FCPSGN, + {PPC_EVMERGEHI, + PPC_INS_EVMERGEHI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTID, PPC_INS_FCTID, + {PPC_EVMERGEHILO, + PPC_INS_EVMERGEHILO, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIDU, PPC_INS_FCTIDU, + {PPC_EVMERGELO, + PPC_INS_EVMERGELO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIDUZ, PPC_INS_FCTIDUZ, + {PPC_EVMERGELOHI, + PPC_INS_EVMERGELOHI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIDUZo, PPC_INS_FCTIDUZ, + {PPC_EVMHEGSMFAA, + PPC_INS_EVMHEGSMFAA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIDUo, PPC_INS_FCTIDU, + {PPC_EVMHEGSMFAN, + PPC_INS_EVMHEGSMFAN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIDZ, PPC_INS_FCTIDZ, + {PPC_EVMHEGSMIAA, + PPC_INS_EVMHEGSMIAA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIDZo, PPC_INS_FCTIDZ, + {PPC_EVMHEGSMIAN, + PPC_INS_EVMHEGSMIAN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIDo, PPC_INS_FCTID, + {PPC_EVMHEGUMIAA, + PPC_INS_EVMHEGUMIAA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIW, PPC_INS_FCTIW, + {PPC_EVMHEGUMIAN, + PPC_INS_EVMHEGUMIAN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIWU, PPC_INS_FCTIWU, + {PPC_EVMHESMF, + PPC_INS_EVMHESMF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIWUZ, PPC_INS_FCTIWUZ, + {PPC_EVMHESMFA, + PPC_INS_EVMHESMFA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIWUZo, PPC_INS_FCTIWUZ, + {PPC_EVMHESMFAAW, + PPC_INS_EVMHESMFAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIWUo, PPC_INS_FCTIWU, + {PPC_EVMHESMFANW, + PPC_INS_EVMHESMFANW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIWZ, PPC_INS_FCTIWZ, + {PPC_EVMHESMI, + PPC_INS_EVMHESMI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIWZo, PPC_INS_FCTIWZ, + {PPC_EVMHESMIA, + PPC_INS_EVMHESMIA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FCTIWo, PPC_INS_FCTIW, + {PPC_EVMHESMIAAW, + PPC_INS_EVMHESMIAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FDIV, PPC_INS_FDIV, + {PPC_EVMHESMIANW, + PPC_INS_EVMHESMIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FDIVS, PPC_INS_FDIVS, + {PPC_EVMHESSF, + PPC_INS_EVMHESSF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FDIVSo, PPC_INS_FDIVS, + {PPC_EVMHESSFA, + PPC_INS_EVMHESSFA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FDIVo, PPC_INS_FDIV, + {PPC_EVMHESSFAAW, + PPC_INS_EVMHESSFAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMADD, PPC_INS_FMADD, + {PPC_EVMHESSFANW, + PPC_INS_EVMHESSFANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMADDS, PPC_INS_FMADDS, + {PPC_EVMHESSIAAW, + PPC_INS_EVMHESSIAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMADDSo, PPC_INS_FMADDS, + {PPC_EVMHESSIANW, + PPC_INS_EVMHESSIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMADDo, PPC_INS_FMADD, + {PPC_EVMHEUMI, + PPC_INS_EVMHEUMI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMR, PPC_INS_FMR, + {PPC_EVMHEUMIA, + PPC_INS_EVMHEUMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMRo, PPC_INS_FMR, + {PPC_EVMHEUMIAAW, + PPC_INS_EVMHEUMIAAW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMSUB, PPC_INS_FMSUB, + {PPC_EVMHEUMIANW, + PPC_INS_EVMHEUMIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMSUBS, PPC_INS_FMSUBS, + {PPC_EVMHEUSIAAW, + PPC_INS_EVMHEUSIAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMSUBSo, PPC_INS_FMSUBS, + {PPC_EVMHEUSIANW, + PPC_INS_EVMHEUSIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMSUBo, PPC_INS_FMSUB, + {PPC_EVMHOGSMFAA, + PPC_INS_EVMHOGSMFAA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMUL, PPC_INS_FMUL, + {PPC_EVMHOGSMFAN, + PPC_INS_EVMHOGSMFAN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMULS, PPC_INS_FMULS, + {PPC_EVMHOGSMIAA, + PPC_INS_EVMHOGSMIAA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMULSo, PPC_INS_FMULS, + {PPC_EVMHOGSMIAN, + PPC_INS_EVMHOGSMIAN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FMULo, PPC_INS_FMUL, + {PPC_EVMHOGUMIAA, + PPC_INS_EVMHOGUMIAA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNABSD, PPC_INS_FNABS, + {PPC_EVMHOGUMIAN, + PPC_INS_EVMHOGUMIAN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNABSDo, PPC_INS_FNABS, + {PPC_EVMHOSMF, + PPC_INS_EVMHOSMF, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNABSS, PPC_INS_FNABS, + {PPC_EVMHOSMFA, + PPC_INS_EVMHOSMFA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNABSSo, PPC_INS_FNABS, + {PPC_EVMHOSMFAAW, + PPC_INS_EVMHOSMFAAW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNEGD, PPC_INS_FNEG, + {PPC_EVMHOSMFANW, + PPC_INS_EVMHOSMFANW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNEGDo, PPC_INS_FNEG, + {PPC_EVMHOSMI, + PPC_INS_EVMHOSMI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNEGS, PPC_INS_FNEG, + {PPC_EVMHOSMIA, + PPC_INS_EVMHOSMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNEGSo, PPC_INS_FNEG, + {PPC_EVMHOSMIAAW, + PPC_INS_EVMHOSMIAAW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNMADD, PPC_INS_FNMADD, + {PPC_EVMHOSMIANW, + PPC_INS_EVMHOSMIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNMADDS, PPC_INS_FNMADDS, + {PPC_EVMHOSSF, + PPC_INS_EVMHOSSF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNMADDSo, PPC_INS_FNMADDS, + {PPC_EVMHOSSFA, + PPC_INS_EVMHOSSFA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNMADDo, PPC_INS_FNMADD, + {PPC_EVMHOSSFAAW, + PPC_INS_EVMHOSSFAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNMSUB, PPC_INS_FNMSUB, + {PPC_EVMHOSSFANW, + PPC_INS_EVMHOSSFANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNMSUBS, PPC_INS_FNMSUBS, + {PPC_EVMHOSSIAAW, + PPC_INS_EVMHOSSIAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNMSUBSo, PPC_INS_FNMSUBS, + {PPC_EVMHOSSIANW, + PPC_INS_EVMHOSSIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FNMSUBo, PPC_INS_FNMSUB, + {PPC_EVMHOUMI, + PPC_INS_EVMHOUMI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRE, PPC_INS_FRE, + {PPC_EVMHOUMIA, + PPC_INS_EVMHOUMIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRES, PPC_INS_FRES, + {PPC_EVMHOUMIAAW, + PPC_INS_EVMHOUMIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRESo, PPC_INS_FRES, + {PPC_EVMHOUMIANW, + PPC_INS_EVMHOUMIANW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FREo, PPC_INS_FRE, + {PPC_EVMHOUSIAAW, + PPC_INS_EVMHOUSIAAW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIMD, PPC_INS_FRIM, + {PPC_EVMHOUSIANW, + PPC_INS_EVMHOUSIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIMDo, PPC_INS_FRIM, + {PPC_EVMRA, PPC_INS_EVMRA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_FRIMS, PPC_INS_FRIM, + {PPC_EVMWHSMF, + PPC_INS_EVMWHSMF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIMSo, PPC_INS_FRIM, + {PPC_EVMWHSMFA, + PPC_INS_EVMWHSMFA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIND, PPC_INS_FRIN, + {PPC_EVMWHSMI, + PPC_INS_EVMWHSMI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRINDo, PPC_INS_FRIN, + {PPC_EVMWHSMIA, + PPC_INS_EVMWHSMIA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRINS, PPC_INS_FRIN, + {PPC_EVMWHSSF, + PPC_INS_EVMWHSSF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRINSo, PPC_INS_FRIN, + {PPC_EVMWHSSFA, + PPC_INS_EVMWHSSFA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIPD, PPC_INS_FRIP, + {PPC_EVMWHUMI, + PPC_INS_EVMWHUMI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIPDo, PPC_INS_FRIP, + {PPC_EVMWHUMIA, + PPC_INS_EVMWHUMIA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIPS, PPC_INS_FRIP, + {PPC_EVMWLSMIAAW, + PPC_INS_EVMWLSMIAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIPSo, PPC_INS_FRIP, + {PPC_EVMWLSMIANW, + PPC_INS_EVMWLSMIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIZD, PPC_INS_FRIZ, + {PPC_EVMWLSSIAAW, + PPC_INS_EVMWLSSIAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIZDo, PPC_INS_FRIZ, + {PPC_EVMWLSSIANW, + PPC_INS_EVMWLSSIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIZS, PPC_INS_FRIZ, + {PPC_EVMWLUMI, + PPC_INS_EVMWLUMI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRIZSo, PPC_INS_FRIZ, + {PPC_EVMWLUMIA, + PPC_INS_EVMWLUMIA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRSP, PPC_INS_FRSP, + {PPC_EVMWLUMIAAW, + PPC_INS_EVMWLUMIAAW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRSPo, PPC_INS_FRSP, + {PPC_EVMWLUMIANW, + PPC_INS_EVMWLUMIANW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRSQRTE, PPC_INS_FRSQRTE, + {PPC_EVMWLUSIAAW, + PPC_INS_EVMWLUSIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRSQRTES, PPC_INS_FRSQRTES, + {PPC_EVMWLUSIANW, + PPC_INS_EVMWLUSIANW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRSQRTESo, PPC_INS_FRSQRTES, + {PPC_EVMWSMF, + PPC_INS_EVMWSMF, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FRSQRTEo, PPC_INS_FRSQRTE, + {PPC_EVMWSMFA, + PPC_INS_EVMWSMFA, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSELD, PPC_INS_FSEL, + {PPC_EVMWSMFAA, + PPC_INS_EVMWSMFAA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSELDo, PPC_INS_FSEL, + {PPC_EVMWSMFAN, + PPC_INS_EVMWSMFAN, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSELS, PPC_INS_FSEL, + {PPC_EVMWSMI, + PPC_INS_EVMWSMI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSELSo, PPC_INS_FSEL, + {PPC_EVMWSMIA, + PPC_INS_EVMWSMIA, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSQRT, PPC_INS_FSQRT, + {PPC_EVMWSMIAA, + PPC_INS_EVMWSMIAA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSQRTS, PPC_INS_FSQRTS, + {PPC_EVMWSMIAN, + PPC_INS_EVMWSMIAN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSQRTSo, PPC_INS_FSQRTS, + {PPC_EVMWSSF, + PPC_INS_EVMWSSF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSQRTo, PPC_INS_FSQRT, + {PPC_EVMWSSFA, + PPC_INS_EVMWSSFA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSUB, PPC_INS_FSUB, + {PPC_EVMWSSFAA, + PPC_INS_EVMWSSFAA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSUBS, PPC_INS_FSUBS, + {PPC_EVMWSSFAN, + PPC_INS_EVMWSSFAN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSUBSo, PPC_INS_FSUBS, + {PPC_EVMWUMI, + PPC_INS_EVMWUMI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FSUBo, PPC_INS_FSUB, + {PPC_EVMWUMIA, + PPC_INS_EVMWUMIA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FTDIV, PPC_INS_FTDIV, + {PPC_EVMWUMIAA, + PPC_INS_EVMWUMIAA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_FTSQRT, PPC_INS_FTSQRT, + {PPC_EVMWUMIAN, + PPC_INS_EVMWUMIAN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_HRFID, PPC_INS_HRFID, + {PPC_EVNAND, + PPC_INS_EVNAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_ICBI, PPC_INS_ICBI, + {PPC_EVNEG, PPC_INS_EVNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_ICBIEP, PPC_INS_ICBIEP, + {PPC_EVNOR, PPC_INS_EVNOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_ICBLC, PPC_INS_ICBLC, + {PPC_EVOR, PPC_INS_EVOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_ICBLQ, PPC_INS_ICBLQ, + {PPC_EVORC, PPC_INS_EVORC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_ICBT, PPC_INS_ICBT, + {PPC_EVRLW, PPC_INS_EVRLW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ICBT, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_ICBTLS, PPC_INS_ICBTLS, + {PPC_EVRLWI, + PPC_INS_EVRLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_ICCCI, PPC_INS_ICCCI, + {PPC_EVRNDW, + PPC_INS_EVRNDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_ISEL, PPC_INS_ISEL, + {PPC_EVSEL, PPC_INS_EVSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ISEL8, PPC_INS_ISEL, + {PPC_EVSLW, PPC_INS_EVSLW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_ISYNC, PPC_INS_ISYNC, + {PPC_EVSLWI, + PPC_INS_EVSLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LA, PPC_INS_LA, + {PPC_EVSPLATFI, + PPC_INS_EVSPLATFI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBARX, PPC_INS_LBARX, + {PPC_EVSPLATI, + PPC_INS_EVSPLATI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBARXL, PPC_INS_LBARX, + {PPC_EVSRWIS, + PPC_INS_EVSRWIS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBEPX, PPC_INS_LBEPX, + {PPC_EVSRWIU, + PPC_INS_EVSRWIU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZ, PPC_INS_LBZ, + {PPC_EVSRWS, + PPC_INS_EVSRWS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZ8, PPC_INS_LBZ, + {PPC_EVSRWU, + PPC_INS_EVSRWU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZCIX, PPC_INS_LBZCIX, + {PPC_EVSTDD, + PPC_INS_EVSTDD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZU, PPC_INS_LBZU, + {PPC_EVSTDDX, + PPC_INS_EVSTDDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZU8, PPC_INS_LBZU, + {PPC_EVSTDH, + PPC_INS_EVSTDH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZUX, PPC_INS_LBZUX, + {PPC_EVSTDHX, + PPC_INS_EVSTDHX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZUX8, PPC_INS_LBZUX, + {PPC_EVSTDW, + PPC_INS_EVSTDW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZX, PPC_INS_LBZX, + {PPC_EVSTDWX, + PPC_INS_EVSTDWX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZX8, PPC_INS_LBZX, + {PPC_EVSTWHE, + PPC_INS_EVSTWHE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LBZXTLS_, PPC_INS_LBZX, + {PPC_EVSTWHEX, + PPC_INS_EVSTWHEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LD, PPC_INS_LD, + {PPC_EVSTWHO, + PPC_INS_EVSTWHO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDARX, PPC_INS_LDARX, + {PPC_EVSTWHOX, + PPC_INS_EVSTWHOX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDARXL, PPC_INS_LDARX, + {PPC_EVSTWWE, + PPC_INS_EVSTWWE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDAT, PPC_INS_LDAT, + {PPC_EVSTWWEX, + PPC_INS_EVSTWWEX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDBRX, PPC_INS_LDBRX, + {PPC_EVSTWWO, + PPC_INS_EVSTWWO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDCIX, PPC_INS_LDCIX, + {PPC_EVSTWWOX, + PPC_INS_EVSTWWOX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDMX, PPC_INS_LDMX, + {PPC_EVSUBFSMIAAW, + PPC_INS_EVSUBFSMIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDU, PPC_INS_LDU, + {PPC_EVSUBFSSIAAW, + PPC_INS_EVSUBFSSIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDUX, PPC_INS_LDUX, + {PPC_EVSUBFUMIAAW, + PPC_INS_EVSUBFUMIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDX, PPC_INS_LDX, + {PPC_EVSUBFUSIAAW, + PPC_INS_EVSUBFUSIAAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LDXTLS_, PPC_INS_LDX, + {PPC_EVSUBFW, + PPC_INS_EVSUBFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LFD, PPC_INS_LFD, + {PPC_EVSUBIFW, + PPC_INS_EVSUBIFW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_SPE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_LFDEPX, PPC_INS_LFDEPX, + {PPC_EVXOR, PPC_INS_EVXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_SPE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_LFDU, PPC_INS_LFDU, + {PPC_EXTSB, PPC_INS_EXTSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LFDUX, PPC_INS_LFDUX, + {PPC_EXTSB8, PPC_INS_EXTSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LFDX, PPC_INS_LFDX, + {PPC_EXTSB8_32_64, + PPC_INS_EXTSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LFIWAX, PPC_INS_LFIWAX, + {PPC_EXTSB8_rec, + PPC_INS_EXTSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LFIWZX, PPC_INS_LFIWZX, + {PPC_EXTSB_rec, + PPC_INS_EXTSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LFS, PPC_INS_LFS, + {PPC_EXTSH, PPC_INS_EXTSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LFSU, PPC_INS_LFSU, + {PPC_EXTSH8, PPC_INS_EXTSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LFSUX, PPC_INS_LFSUX, + {PPC_EXTSH8_32_64, + PPC_INS_EXTSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LFSX, PPC_INS_LFSX, + {PPC_EXTSH8_rec, + PPC_INS_EXTSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHA, PPC_INS_LHA, + {PPC_EXTSH_rec, + PPC_INS_EXTSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHA8, PPC_INS_LHA, + {PPC_EXTSW, PPC_INS_EXTSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LHARX, PPC_INS_LHARX, + {PPC_EXTSWSLI, + PPC_INS_EXTSWSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHARXL, PPC_INS_LHARX, + {PPC_EXTSWSLI_rec, + PPC_INS_EXTSWSLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHAU, PPC_INS_LHAU, + {PPC_EXTSW_32_64, + PPC_INS_EXTSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHAU8, PPC_INS_LHAU, + {PPC_EXTSW_32_64_rec, + PPC_INS_EXTSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHAUX, PPC_INS_LHAUX, + {PPC_EXTSW_rec, + PPC_INS_EXTSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHAUX8, PPC_INS_LHAUX, + {PPC_EnforceIEIO, + PPC_INS_EIEIO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHAX, PPC_INS_LHAX, + {PPC_FABSD, PPC_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LHAX8, PPC_INS_LHAX, + {PPC_FABSD_rec, + PPC_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHBRX, PPC_INS_LHBRX, + {PPC_FABSS, PPC_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LHBRX8, PPC_INS_LHBRX, + {PPC_FABSS_rec, + PPC_INS_FABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHEPX, PPC_INS_LHEPX, + {PPC_FADD, + PPC_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZ, PPC_INS_LHZ, + {PPC_FADDS, + PPC_INS_FADDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZ8, PPC_INS_LHZ, + {PPC_FADDS_rec, + PPC_INS_FADDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZCIX, PPC_INS_LHZCIX, + {PPC_FADD_rec, + PPC_INS_FADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZU, PPC_INS_LHZU, + {PPC_FCFID, + PPC_INS_FCFID, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZU8, PPC_INS_LHZU, + {PPC_FCFIDS, + PPC_INS_FCFIDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZUX, PPC_INS_LHZUX, + {PPC_FCFIDS_rec, + PPC_INS_FCFIDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZUX8, PPC_INS_LHZUX, + {PPC_FCFIDU, + PPC_INS_FCFIDU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZX, PPC_INS_LHZX, + {PPC_FCFIDUS, + PPC_INS_FCFIDUS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZX8, PPC_INS_LHZX, + {PPC_FCFIDUS_rec, + PPC_INS_FCFIDUS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LHZXTLS_, PPC_INS_LHZX, + {PPC_FCFIDU_rec, + PPC_INS_FCFIDU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LI, PPC_INS_LI, + {PPC_FCFID_rec, + PPC_INS_FCFID, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LI8, PPC_INS_LI, + {PPC_FCMPUD, PPC_INS_FCMPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LIS, PPC_INS_LIS, + {PPC_FCMPUS, PPC_INS_FCMPU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LIS8, PPC_INS_LIS, + {PPC_FCPSGND, + PPC_INS_FCPSGN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LMW, PPC_INS_LMW, + {PPC_FCPSGND_rec, + PPC_INS_FCPSGN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LSWI, PPC_INS_LSWI, + {PPC_FCPSGNS, + PPC_INS_FCPSGN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LVEBX, PPC_INS_LVEBX, + {PPC_FCPSGNS_rec, + PPC_INS_FCPSGN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LVEHX, PPC_INS_LVEHX, + {PPC_FCTID, + PPC_INS_FCTID, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LVEWX, PPC_INS_LVEWX, + {PPC_FCTIDU, PPC_INS_FCTIDU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_LVSL, PPC_INS_LVSL, + {PPC_FCTIDUZ, + PPC_INS_FCTIDUZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LVSR, PPC_INS_LVSR, + {PPC_FCTIDUZ_rec, + PPC_INS_FCTIDUZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LVX, PPC_INS_LVX, + {PPC_FCTIDU_rec, + PPC_INS_FCTIDU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LVXL, PPC_INS_LVXL, + {PPC_FCTIDZ, + PPC_INS_FCTIDZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWA, PPC_INS_LWA, + {PPC_FCTIDZ_rec, + PPC_INS_FCTIDZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWARX, PPC_INS_LWARX, + {PPC_FCTID_rec, + PPC_INS_FCTID, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWARXL, PPC_INS_LWARX, + {PPC_FCTIW, + PPC_INS_FCTIW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWAT, PPC_INS_LWAT, + {PPC_FCTIWU, PPC_INS_FCTIWU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_LWAUX, PPC_INS_LWAUX, + {PPC_FCTIWUZ, + PPC_INS_FCTIWUZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWAX, PPC_INS_LWAX, + {PPC_FCTIWUZ_rec, + PPC_INS_FCTIWUZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWAX_32, PPC_INS_LWAX, + {PPC_FCTIWU_rec, + PPC_INS_FCTIWU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWA_32, PPC_INS_LWA, + {PPC_FCTIWZ, + PPC_INS_FCTIWZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWBRX, PPC_INS_LWBRX, + {PPC_FCTIWZ_rec, + PPC_INS_FCTIWZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWBRX8, PPC_INS_LWBRX, + {PPC_FCTIW_rec, + PPC_INS_FCTIW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWEPX, PPC_INS_LWEPX, + {PPC_FDIV, + PPC_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWZ, PPC_INS_LWZ, + {PPC_FDIVS, + PPC_INS_FDIVS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWZ8, PPC_INS_LWZ, + {PPC_FDIVS_rec, + PPC_INS_FDIVS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWZCIX, PPC_INS_LWZCIX, + {PPC_FDIV_rec, + PPC_INS_FDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWZU, PPC_INS_LWZU, + {PPC_FMADD, + PPC_INS_FMADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWZU8, PPC_INS_LWZU, + {PPC_FMADDS, + PPC_INS_FMADDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWZUX, PPC_INS_LWZUX, + {PPC_FMADDS_rec, + PPC_INS_FMADDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWZUX8, PPC_INS_LWZUX, + {PPC_FMADD_rec, + PPC_INS_FMADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWZX, PPC_INS_LWZX, + {PPC_FMR, PPC_INS_FMR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LWZX8, PPC_INS_LWZX, + {PPC_FMR_rec, + PPC_INS_FMR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LWZXTLS_, PPC_INS_LWZX, + {PPC_FMSUB, + PPC_INS_FMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXSD, PPC_INS_LXSD, + {PPC_FMSUBS, + PPC_INS_FMSUBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXSDX, PPC_INS_LXSDX, + {PPC_FMSUBS_rec, + PPC_INS_FMSUBS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXSIBZX, PPC_INS_LXSIBZX, + {PPC_FMSUB_rec, + PPC_INS_FMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXSIHZX, PPC_INS_LXSIHZX, + {PPC_FMUL, + PPC_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXSIWAX, PPC_INS_LXSIWAX, + {PPC_FMULS, + PPC_INS_FMULS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXSIWZX, PPC_INS_LXSIWZX, + {PPC_FMULS_rec, + PPC_INS_FMULS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXSSP, PPC_INS_LXSSP, + {PPC_FMUL_rec, + PPC_INS_FMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXSSPX, PPC_INS_LXSSPX, + {PPC_FNABSD, PPC_INS_FNABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LXV, PPC_INS_LXV, + {PPC_FNABSD_rec, + PPC_INS_FNABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXVB16X, PPC_INS_LXVB16X, + {PPC_FNABSS, PPC_INS_FNABS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LXVD2X, PPC_INS_LXVD2X, + {PPC_FNABSS_rec, + PPC_INS_FNABS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXVDSX, PPC_INS_LXVDSX, + {PPC_FNEGD, PPC_INS_FNEG, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LXVH8X, PPC_INS_LXVH8X, + {PPC_FNEGD_rec, + PPC_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXVL, PPC_INS_LXVL, + {PPC_FNEGS, PPC_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_LXVLL, PPC_INS_LXVLL, + {PPC_FNEGS_rec, + PPC_INS_FNEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXVW4X, PPC_INS_LXVW4X, + {PPC_FNMADD, + PPC_INS_FNMADD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXVWSX, PPC_INS_LXVWSX, + {PPC_FNMADDS, + PPC_INS_FNMADDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_LXVX, PPC_INS_LXVX, + {PPC_FNMADDS_rec, + PPC_INS_FNMADDS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MADDHD, PPC_INS_MADDHD, + {PPC_FNMADD_rec, + PPC_INS_FNMADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MADDHDU, PPC_INS_MADDHDU, + {PPC_FNMSUB, + PPC_INS_FNMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MADDLD, PPC_INS_MADDLD, + {PPC_FNMSUBS, + PPC_INS_FNMSUBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MBAR, PPC_INS_MBAR, + {PPC_FNMSUBS_rec, + PPC_INS_FNMSUBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MCRF, PPC_INS_MCRF, + {PPC_FNMSUB_rec, + PPC_INS_FNMSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MCRFS, PPC_INS_MCRFS, + {PPC_FRE, PPC_INS_FRE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MCRXRX, PPC_INS_MCRXRX, + {PPC_FRES, PPC_INS_FRES, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MFBHRBE, PPC_INS_MFBHRBE, + {PPC_FRES_rec, + PPC_INS_FRES, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFCR, PPC_INS_MFCR, + {PPC_FRE_rec, + PPC_INS_FRE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFCR8, PPC_INS_MFCR, + {PPC_FRIMD, + PPC_INS_FRIM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFCTR, PPC_INS_MFCTR, + {PPC_FRIMD_rec, + PPC_INS_FRIM, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFCTR8, PPC_INS_MFCTR, + {PPC_FRIMS, + PPC_INS_FRIM, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFDCR, PPC_INS_MFBR0, + {PPC_FRIMS_rec, + PPC_INS_FRIM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFFS, PPC_INS_MFFS, + {PPC_FRIND, + PPC_INS_FRIN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFFSCDRN, PPC_INS_MFFSCDRN, + {PPC_FRIND_rec, + PPC_INS_FRIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFFSCDRNI, PPC_INS_MFFSCDRNI, + {PPC_FRINS, + PPC_INS_FRIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFFSCE, PPC_INS_MFFSCE, + {PPC_FRINS_rec, + PPC_INS_FRIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFFSCRN, PPC_INS_MFFSCRN, + {PPC_FRIPD, + PPC_INS_FRIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFFSCRNI, PPC_INS_MFFSCRNI, + {PPC_FRIPD_rec, + PPC_INS_FRIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFFSL, PPC_INS_MFFSL, + {PPC_FRIPS, + PPC_INS_FRIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFFSo, PPC_INS_MFFS, + {PPC_FRIPS_rec, + PPC_INS_FRIP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFLR, PPC_INS_MFLR, + {PPC_FRIZD, + PPC_INS_FRIZ, #ifndef CAPSTONE_DIET - { PPC_REG_LR, 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFLR8, PPC_INS_MFLR, + {PPC_FRIZD_rec, + PPC_INS_FRIZ, #ifndef CAPSTONE_DIET - { PPC_REG_LR8, 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFMSR, PPC_INS_MFMSR, + {PPC_FRIZS, + PPC_INS_FRIZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFOCRF, PPC_INS_MFOCRF, + {PPC_FRIZS_rec, + PPC_INS_FRIZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFOCRF8, PPC_INS_MFOCRF, + {PPC_FRSP, + PPC_INS_FRSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFPMR, PPC_INS_MFPMR, + {PPC_FRSP_rec, + PPC_INS_FRSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFSPR, PPC_INS_MFAMR, + {PPC_FRSQRTE, + PPC_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFSR, PPC_INS_MFSR, + {PPC_FRSQRTES, + PPC_INS_FRSQRTES, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFSRIN, PPC_INS_MFSRIN, + {PPC_FRSQRTES_rec, + PPC_INS_FRSQRTES, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFTB, PPC_INS_MFTB, + {PPC_FRSQRTE_rec, + PPC_INS_FRSQRTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFTB8, PPC_INS_MFSPR, + {PPC_FSELD, PPC_INS_FSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MFVRD, PPC_INS_MFVRD, + {PPC_FSELD_rec, + PPC_INS_FSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFVRSAVE, PPC_INS_MFVRSAVE, + {PPC_FSELS, PPC_INS_FSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MFVRSAVEv, PPC_INS_MFSPR, + {PPC_FSELS_rec, + PPC_INS_FSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFVSCR, PPC_INS_MFVSCR, + {PPC_FSQRT, + PPC_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFVSRD, PPC_INS_MFFPRD, + {PPC_FSQRTS, + PPC_INS_FSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFVSRLD, PPC_INS_MFVSRLD, + {PPC_FSQRTS_rec, + PPC_INS_FSQRTS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MFVSRWZ, PPC_INS_MFVSRWZ, + {PPC_FSQRT_rec, + PPC_INS_FSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MODSD, PPC_INS_MODSD, + {PPC_FSUB, + PPC_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MODSW, PPC_INS_MODSW, + {PPC_FSUBS, + PPC_INS_FSUBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MODUD, PPC_INS_MODUD, + {PPC_FSUBS_rec, + PPC_INS_FSUBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MODUW, PPC_INS_MODUW, + {PPC_FSUB_rec, + PPC_INS_FSUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MSGSYNC, PPC_INS_MSGSYNC, + {PPC_FTDIV, PPC_INS_FTDIV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MSYNC, PPC_INS_MSYNC, + {PPC_FTSQRT, PPC_INS_FTSQRT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTCRF, PPC_INS_MTCRF, + {PPC_HRFID, PPC_INS_HRFID, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTCRF8, PPC_INS_MTCR, + {PPC_ICBI, PPC_INS_ICBI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTCTR, PPC_INS_MTCTR, + {PPC_ICBIEP, PPC_INS_ICBIEP, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTCTR8, PPC_INS_MTCTR, + {PPC_ICBLC, PPC_INS_ICBLC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTCTR8loop, PPC_INS_MTCTR, + {PPC_ICBLQ, PPC_INS_ICBLQ, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTCTRloop, PPC_INS_MTCTR, + {PPC_ICBT, PPC_INS_ICBT, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ICBT, 0}, 0, + 0 #endif -}, + }, -{ - PPC_MTDCR, PPC_INS_MTBR0, + {PPC_ICBTLS, PPC_INS_ICBTLS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTFSB0, PPC_INS_MTFSB0, + {PPC_ICCCI, PPC_INS_ICCCI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_PPC4XX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_MTFSB1, PPC_INS_MTFSB1, + {PPC_ISEL, PPC_INS_ISEL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTFSF, PPC_INS_MTFSF, + {PPC_ISEL8, PPC_INS_ISEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTFSFI, PPC_INS_MTFSFI, + {PPC_ISYNC, PPC_INS_ISYNC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTFSFIo, PPC_INS_MTFSFI, + {PPC_LA, PPC_INS_LA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_MTFSFb, PPC_INS_MTFSF, + {PPC_LBARX, PPC_INS_LBARX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTFSFo, PPC_INS_MTFSF, + {PPC_LBARXL, PPC_INS_LBARX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTLR, PPC_INS_MTLR, + {PPC_LBEPX, PPC_INS_LBEPX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTLR8, PPC_INS_MTLR, + {PPC_LBZ, PPC_INS_LBZ, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTMSR, PPC_INS_MTMSR, + {PPC_LBZ8, PPC_INS_LBZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTMSRD, PPC_INS_MTMSRD, + {PPC_LBZCIX, PPC_INS_LBZCIX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTOCRF, PPC_INS_MTOCRF, + {PPC_LBZU, PPC_INS_LBZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTOCRF8, PPC_INS_MTOCRF, + {PPC_LBZU8, PPC_INS_LBZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTPMR, PPC_INS_MTPMR, + {PPC_LBZUX, PPC_INS_LBZUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTSPR, PPC_INS_MTAMR, + {PPC_LBZUX8, PPC_INS_LBZUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTSR, PPC_INS_MTSR, + {PPC_LBZX, PPC_INS_LBZX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTSRIN, PPC_INS_MTSRIN, + {PPC_LBZX8, PPC_INS_LBZX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTVRSAVE, PPC_INS_MTVRSAVE, + {PPC_LBZXTLS_, + PPC_INS_LBZX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MTVRSAVEv, PPC_INS_MTSPR, + {PPC_LD, PPC_INS_LD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_MTVSCR, PPC_INS_MTVSCR, + {PPC_LDARX, PPC_INS_LDARX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTVSRD, PPC_INS_MTVSRD, + {PPC_LDARXL, PPC_INS_LDARX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTVSRDD, PPC_INS_MTVSRDD, + {PPC_LDAT, PPC_INS_LDAT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTVSRWA, PPC_INS_MTVSRWA, + {PPC_LDBRX, PPC_INS_LDBRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTVSRWS, PPC_INS_MTVSRWS, + {PPC_LDCIX, PPC_INS_LDCIX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MTVSRWZ, PPC_INS_MTVSRWZ, + {PPC_LDMX, PPC_INS_LDMX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULHD, PPC_INS_MULHD, + {PPC_LDU, PPC_INS_LDU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULHDU, PPC_INS_MULHDU, + {PPC_LDUX, PPC_INS_LDUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULHDUo, PPC_INS_MULHDU, + {PPC_LDX, PPC_INS_LDX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULHDo, PPC_INS_MULHD, + {PPC_LDXTLS_, + PPC_INS_LDX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_MULHW, PPC_INS_MULHW, + {PPC_LFD, PPC_INS_LFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULHWU, PPC_INS_MULHWU, + {PPC_LFDEPX, PPC_INS_LFDEPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULHWUo, PPC_INS_MULHWU, + {PPC_LFDU, PPC_INS_LFDU, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULHWo, PPC_INS_MULHW, + {PPC_LFDUX, PPC_INS_LFDUX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULLD, PPC_INS_MULLD, + {PPC_LFDX, PPC_INS_LFDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULLDo, PPC_INS_MULLD, + {PPC_LFIWAX, PPC_INS_LFIWAX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULLI, PPC_INS_MULLI, + {PPC_LFIWZX, PPC_INS_LFIWZX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULLI8, PPC_INS_MULLI, + {PPC_LFS, PPC_INS_LFS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULLW, PPC_INS_MULLW, + {PPC_LFSU, PPC_INS_LFSU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_MULLWo, PPC_INS_MULLW, + {PPC_LFSUX, PPC_INS_LFSUX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NAND, PPC_INS_NAND, + {PPC_LFSX, PPC_INS_LFSX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NAND8, PPC_INS_NAND, + {PPC_LHA, PPC_INS_LHA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NAND8o, PPC_INS_NAND, + {PPC_LHA8, PPC_INS_LHA, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NANDo, PPC_INS_NAND, + {PPC_LHARX, PPC_INS_LHARX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NAP, PPC_INS_NAP, + {PPC_LHARXL, PPC_INS_LHARX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NEG, PPC_INS_NEG, + {PPC_LHAU, PPC_INS_LHAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NEG8, PPC_INS_NEG, + {PPC_LHAU8, PPC_INS_LHAU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NEG8o, PPC_INS_NEG, + {PPC_LHAUX, PPC_INS_LHAUX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NEGo, PPC_INS_NEG, + {PPC_LHAUX8, PPC_INS_LHAUX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NOP, PPC_INS_NOP, + {PPC_LHAX, PPC_INS_LHAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NOP_GT_PWR6, PPC_INS_ORI, + {PPC_LHAX8, PPC_INS_LHAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NOP_GT_PWR7, PPC_INS_ORI, + {PPC_LHBRX, PPC_INS_LHBRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NOR, PPC_INS_NOR, + {PPC_LHBRX8, PPC_INS_LHBRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NOR8, PPC_INS_NOT, + {PPC_LHEPX, PPC_INS_LHEPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NOR8o, PPC_INS_NOT, + {PPC_LHZ, PPC_INS_LHZ, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_NORo, PPC_INS_NOR, + {PPC_LHZ8, PPC_INS_LHZ, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_OR, PPC_INS_OR, + {PPC_LHZCIX, PPC_INS_LHZCIX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_OR8, PPC_INS_MR, + {PPC_LHZU, PPC_INS_LHZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_OR8o, PPC_INS_MR, + {PPC_LHZU8, PPC_INS_LHZU, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ORC, PPC_INS_ORC, + {PPC_LHZUX, PPC_INS_LHZUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ORC8, PPC_INS_ORC, + {PPC_LHZUX8, PPC_INS_LHZUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ORC8o, PPC_INS_ORC, + {PPC_LHZX, PPC_INS_LHZX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ORCo, PPC_INS_ORC, + {PPC_LHZX8, PPC_INS_LHZX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ORI, PPC_INS_ORI, + {PPC_LHZXTLS_, + PPC_INS_LHZX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_ORI8, PPC_INS_ORI, + {PPC_LI, PPC_INS_LI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_ORIS, PPC_INS_ORIS, + {PPC_LI8, PPC_INS_LI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_ORIS8, PPC_INS_ORIS, + {PPC_LIS, PPC_INS_LIS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_ORo, PPC_INS_OR, + {PPC_LIS8, PPC_INS_LIS, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_POPCNTB, PPC_INS_POPCNTB, + {PPC_LMW, PPC_INS_LMW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_POPCNTD, PPC_INS_POPCNTD, + {PPC_LSWI, PPC_INS_LSWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_POPCNTW, PPC_INS_POPCNTW, + {PPC_LVEBX, PPC_INS_LVEBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVALIGNI, PPC_INS_QVALIGNI, + {PPC_LVEHX, PPC_INS_LVEHX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVALIGNIb, PPC_INS_QVALIGNI, + {PPC_LVEWX, PPC_INS_LVEWX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVALIGNIs, PPC_INS_QVALIGNI, + {PPC_LVSL, PPC_INS_LVSL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVESPLATI, PPC_INS_QVESPLATI, + {PPC_LVSR, PPC_INS_LVSR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVESPLATIb, PPC_INS_QVESPLATI, + {PPC_LVX, PPC_INS_LVX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVESPLATIs, PPC_INS_QVESPLATI, + {PPC_LVXL, PPC_INS_LVXL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFABS, PPC_INS_QVFABS, + {PPC_LWA, PPC_INS_LWA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFABSs, PPC_INS_QVFABS, + {PPC_LWARX, PPC_INS_LWARX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFADD, PPC_INS_QVFADD, + {PPC_LWARXL, PPC_INS_LWARX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFADDS, PPC_INS_QVFADDS, + {PPC_LWAT, PPC_INS_LWAT, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFADDSs, PPC_INS_QVFADDS, + {PPC_LWAUX, PPC_INS_LWAUX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCFID, PPC_INS_QVFCFID, + {PPC_LWAX, PPC_INS_LWAX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCFIDS, PPC_INS_QVFCFIDS, + {PPC_LWAX_32, + PPC_INS_LWAX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFCFIDU, PPC_INS_QVFCFIDU, + {PPC_LWA_32, PPC_INS_LWA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCFIDUS, PPC_INS_QVFCFIDUS, + {PPC_LWBRX, PPC_INS_LWBRX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCFIDb, PPC_INS_QVFCFID, + {PPC_LWBRX8, PPC_INS_LWBRX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCMPEQ, PPC_INS_QVFCMPEQ, + {PPC_LWEPX, PPC_INS_LWEPX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCMPEQb, PPC_INS_QVFCMPEQ, + {PPC_LWZ, PPC_INS_LWZ, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCMPEQbs, PPC_INS_QVFCMPEQ, + {PPC_LWZ8, PPC_INS_LWZ, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCMPGT, PPC_INS_QVFCMPGT, + {PPC_LWZCIX, PPC_INS_LWZCIX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCMPGTb, PPC_INS_QVFCMPGT, + {PPC_LWZU, PPC_INS_LWZU, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCMPGTbs, PPC_INS_QVFCMPGT, + {PPC_LWZU8, PPC_INS_LWZU, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCMPLT, PPC_INS_QVFCMPLT, + {PPC_LWZUX, PPC_INS_LWZUX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCMPLTb, PPC_INS_QVFCMPLT, + {PPC_LWZUX8, PPC_INS_LWZUX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCMPLTbs, PPC_INS_QVFCMPLT, + {PPC_LWZX, PPC_INS_LWZX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCPSGN, PPC_INS_QVFCPSGN, + {PPC_LWZX8, PPC_INS_LWZX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCPSGNs, PPC_INS_QVFCPSGN, + {PPC_LWZXTLS_, + PPC_INS_LWZX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFCTID, PPC_INS_QVFCTID, + {PPC_LXSD, PPC_INS_LXSD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCTIDU, PPC_INS_QVFCTIDU, + {PPC_LXSDX, + PPC_INS_LXSDX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFCTIDUZ, PPC_INS_QVFCTIDUZ, + {PPC_LXSIBZX, + PPC_INS_LXSIBZX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFCTIDZ, PPC_INS_QVFCTIDZ, + {PPC_LXSIHZX, + PPC_INS_LXSIHZX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFCTIDb, PPC_INS_QVFCTID, + {PPC_LXSIWAX, + PPC_INS_LXSIWAX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFCTIW, PPC_INS_QVFCTIW, + {PPC_LXSIWZX, + PPC_INS_LXSIWZX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFCTIWU, PPC_INS_QVFCTIWU, + {PPC_LXSSP, PPC_INS_LXSSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCTIWUZ, PPC_INS_QVFCTIWUZ, + {PPC_LXSSPX, PPC_INS_LXSSPX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFCTIWZ, PPC_INS_QVFCTIWZ, + {PPC_LXV, PPC_INS_LXV, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFLOGICAL, PPC_INS_QVFLOGICAL, + {PPC_LXVB16X, + PPC_INS_LXVB16X, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFLOGICALb, PPC_INS_QVFAND, + {PPC_LXVD2X, + PPC_INS_LXVD2X, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFLOGICALs, PPC_INS_QVFLOGICAL, + {PPC_LXVDSX, + PPC_INS_LXVDSX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFMADD, PPC_INS_QVFMADD, + {PPC_LXVH8X, PPC_INS_LXVH8X, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFMADDS, PPC_INS_QVFMADDS, + {PPC_LXVL, PPC_INS_LXVL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFMADDSs, PPC_INS_QVFMADDS, + {PPC_LXVLL, PPC_INS_LXVLL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFMR, PPC_INS_QVFMR, + {PPC_LXVW4X, + PPC_INS_LXVW4X, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFMRb, PPC_INS_QVFMR, + {PPC_LXVWSX, PPC_INS_LXVWSX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFMRs, PPC_INS_QVFMR, + {PPC_LXVX, PPC_INS_LXVX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFMSUB, PPC_INS_QVFMSUB, + {PPC_MADDHD, PPC_INS_MADDHD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFMSUBS, PPC_INS_QVFMSUBS, + {PPC_MADDHDU, + PPC_INS_MADDHDU, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFMSUBSs, PPC_INS_QVFMSUBS, + {PPC_MADDLD, PPC_INS_MADDLD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFMUL, PPC_INS_QVFMUL, + {PPC_MBAR, PPC_INS_MBAR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_BOOKE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFMULS, PPC_INS_QVFMULS, + {PPC_MCRF, PPC_INS_MCRF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFMULSs, PPC_INS_QVFMULS, + {PPC_MCRFS, PPC_INS_MCRFS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFNABS, PPC_INS_QVFNABS, + {PPC_MCRXRX, PPC_INS_MCRXRX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFNABSs, PPC_INS_QVFNABS, + {PPC_MFBHRBE, + PPC_INS_MFBHRBE, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFNEG, PPC_INS_QVFNEG, + {PPC_MFCR, PPC_INS_MFCR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFNEGs, PPC_INS_QVFNEG, + {PPC_MFCR8, PPC_INS_MFCR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFNMADD, PPC_INS_QVFNMADD, + {PPC_MFCTR, + PPC_INS_MFCTR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_CTR, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFNMADDS, PPC_INS_QVFNMADDS, + {PPC_MFCTR8, + PPC_INS_MFCTR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_CTR8, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFNMADDSs, PPC_INS_QVFNMADDS, + {PPC_MFDCR, PPC_INS_MFBR0, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_PPC4XX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFNMSUB, PPC_INS_QVFNMSUB, + {PPC_MFFS, + PPC_INS_MFFS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFNMSUBS, PPC_INS_QVFNMSUBS, + {PPC_MFFSCDRN, + PPC_INS_MFFSCDRN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFNMSUBSs, PPC_INS_QVFNMSUBS, + {PPC_MFFSCDRNI, + PPC_INS_MFFSCDRNI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFPERM, PPC_INS_QVFPERM, + {PPC_MFFSCE, PPC_INS_MFFSCE, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFPERMs, PPC_INS_QVFPERM, + {PPC_MFFSCRN, + PPC_INS_MFFSCRN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFRE, PPC_INS_QVFRE, + {PPC_MFFSCRNI, + PPC_INS_MFFSCRNI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFRES, PPC_INS_QVFRES, + {PPC_MFFSL, PPC_INS_MFFSL, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRESs, PPC_INS_QVFRES, + {PPC_MFFS_rec, + PPC_INS_MFFS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR1, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFRIM, PPC_INS_QVFRIM, + {PPC_MFLR, + PPC_INS_MFLR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_LR, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFRIMs, PPC_INS_QVFRIM, + {PPC_MFLR8, + PPC_INS_MFLR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_LR8, 0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFRIN, PPC_INS_QVFRIN, + {PPC_MFMSR, PPC_INS_MFMSR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRINs, PPC_INS_QVFRIN, + {PPC_MFOCRF, PPC_INS_MFOCRF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRIP, PPC_INS_QVFRIP, + {PPC_MFOCRF8, + PPC_INS_MFOCRF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFRIPs, PPC_INS_QVFRIP, + {PPC_MFPMR, PPC_INS_MFPMR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRIZ, PPC_INS_QVFRIZ, + {PPC_MFSPR, PPC_INS_MFAMR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRIZs, PPC_INS_QVFRIZ, + {PPC_MFSR, PPC_INS_MFSR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRSP, PPC_INS_QVFRSP, + {PPC_MFSRIN, PPC_INS_MFSRIN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRSPs, PPC_INS_QVFRSP, + {PPC_MFTB, PPC_INS_MFTB, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRSQRTE, PPC_INS_QVFRSQRTE, + {PPC_MFTB8, PPC_INS_MFSPR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRSQRTES, PPC_INS_QVFRSQRTES, + {PPC_MFVRD, PPC_INS_MFVRD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFRSQRTESs, PPC_INS_QVFRSQRTES, + {PPC_MFVRSAVE, + PPC_INS_MFVRSAVE, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFSEL, PPC_INS_QVFSEL, + {PPC_MFVRSAVEv, + PPC_INS_MFSPR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFSELb, PPC_INS_QVFSEL, + {PPC_MFVSCR, + PPC_INS_MFVSCR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFSELbb, PPC_INS_QVFSEL, + {PPC_MFVSRD, PPC_INS_MFFPRD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFSELbs, PPC_INS_QVFSEL, + {PPC_MFVSRLD, + PPC_INS_MFVSRLD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFSUB, PPC_INS_QVFSUB, + {PPC_MFVSRWZ, + PPC_INS_MFVSRWZ, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFSUBS, PPC_INS_QVFSUBS, + {PPC_MODSD, PPC_INS_MODSD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFSUBSs, PPC_INS_QVFSUBS, + {PPC_MODSW, PPC_INS_MODSW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFTSTNAN, PPC_INS_QVFTSTNAN, + {PPC_MODUD, PPC_INS_MODUD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFTSTNANb, PPC_INS_QVFTSTNAN, + {PPC_MODUW, PPC_INS_MODUW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFTSTNANbs, PPC_INS_QVFTSTNAN, + {PPC_MSGSYNC, + PPC_INS_MSGSYNC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFXMADD, PPC_INS_QVFXMADD, + {PPC_MSYNC, PPC_INS_MSYNC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFXMADDS, PPC_INS_QVFXMADDS, + {PPC_MTCRF, PPC_INS_MTCRF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFXMUL, PPC_INS_QVFXMUL, + {PPC_MTCRF8, PPC_INS_MTCR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFXMULS, PPC_INS_QVFXMULS, + {PPC_MTCTR, PPC_INS_MTCTR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {PPC_REG_CTR, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFXXCPNMADD, PPC_INS_QVFXXCPNMADD, + {PPC_MTCTR8, PPC_INS_MTCTR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {PPC_REG_CTR8, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFXXCPNMADDS, PPC_INS_QVFXXCPNMADDS, + {PPC_MTCTR8loop, + PPC_INS_MTCTR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CTR8, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFXXMADD, PPC_INS_QVFXXMADD, + {PPC_MTCTRloop, + PPC_INS_MTCTR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CTR, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFXXMADDS, PPC_INS_QVFXXMADDS, + {PPC_MTDCR, PPC_INS_MTBR0, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_PPC4XX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_QVFXXNPMADD, PPC_INS_QVFXXNPMADD, + {PPC_MTFSB0, + PPC_INS_MTFSB0, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_RM, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVFXXNPMADDS, PPC_INS_QVFXXNPMADDS, + {PPC_MTFSB1, + PPC_INS_MTFSB1, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_RM, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVGPCI, PPC_INS_QVGPCI, + {PPC_MTFSF, PPC_INS_MTFSF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFCDUX, PPC_INS_QVLFCDUX, + {PPC_MTFSFI, PPC_INS_MTFSFI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFCDUXA, PPC_INS_QVLFCDUXA, + {PPC_MTFSFI_rec, + PPC_INS_MTFSFI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFCDX, PPC_INS_QVLFCDX, + {PPC_MTFSFb, + PPC_INS_MTFSF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_RM, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFCDXA, PPC_INS_QVLFCDXA, + {PPC_MTFSF_rec, + PPC_INS_MTFSF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFCSUX, PPC_INS_QVLFCSUX, + {PPC_MTLR, PPC_INS_MTLR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {PPC_REG_LR, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFCSUXA, PPC_INS_QVLFCSUXA, + {PPC_MTLR8, PPC_INS_MTLR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {PPC_REG_LR8, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFCSX, PPC_INS_QVLFCSX, + {PPC_MTMSR, PPC_INS_MTMSR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFCSXA, PPC_INS_QVLFCSXA, + {PPC_MTMSRD, PPC_INS_MTMSRD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFCSXs, PPC_INS_QVLFCSX, + {PPC_MTOCRF, PPC_INS_MTOCRF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFDUX, PPC_INS_QVLFDUX, + {PPC_MTOCRF8, + PPC_INS_MTOCRF, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFDUXA, PPC_INS_QVLFDUXA, + {PPC_MTPMR, PPC_INS_MTPMR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFDX, PPC_INS_QVLFDX, + {PPC_MTSPR, PPC_INS_MTAMR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFDXA, PPC_INS_QVLFDXA, + {PPC_MTSR, PPC_INS_MTSR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFDXb, PPC_INS_QVLFDX, + {PPC_MTSRIN, PPC_INS_MTSRIN, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFIWAX, PPC_INS_QVLFIWAX, + {PPC_MTVRSAVE, + PPC_INS_MTVRSAVE, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFIWAXA, PPC_INS_QVLFIWAXA, + {PPC_MTVRSAVEv, + PPC_INS_MTSPR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFIWZX, PPC_INS_QVLFIWZX, + {PPC_MTVSCR, + PPC_INS_MTVSCR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFIWZXA, PPC_INS_QVLFIWZXA, + {PPC_MTVSRD, PPC_INS_MTVSRD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFSUX, PPC_INS_QVLFSUX, + {PPC_MTVSRDD, + PPC_INS_MTVSRDD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFSUXA, PPC_INS_QVLFSUXA, + {PPC_MTVSRWA, + PPC_INS_MTVSRWA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFSX, PPC_INS_QVLFSX, + {PPC_MTVSRWS, + PPC_INS_MTVSRWS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFSXA, PPC_INS_QVLFSXA, + {PPC_MTVSRWZ, + PPC_INS_MTVSRWZ, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLFSXb, PPC_INS_QVLFSX, + {PPC_MULHD, PPC_INS_MULHD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLFSXs, PPC_INS_QVLFSX, + {PPC_MULHDU, PPC_INS_MULHDU, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLPCLDX, PPC_INS_QVLPCLDX, + {PPC_MULHDU_rec, + PPC_INS_MULHDU, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLPCLSX, PPC_INS_QVLPCLSX, + {PPC_MULHD_rec, + PPC_INS_MULHD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVLPCLSXint, PPC_INS_QVLPCLSX, + {PPC_MULHW, PPC_INS_MULHW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLPCRDX, PPC_INS_QVLPCRDX, + {PPC_MULHWU, PPC_INS_MULHWU, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVLPCRSX, PPC_INS_QVLPCRSX, + {PPC_MULHWU_rec, + PPC_INS_MULHWU, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCDUX, PPC_INS_QVSTFCDUX, + {PPC_MULHW_rec, + PPC_INS_MULHW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCDUXA, PPC_INS_QVSTFCDUXA, + {PPC_MULLD, PPC_INS_MULLD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCDUXI, PPC_INS_QVSTFCDUXI, + {PPC_MULLD_rec, + PPC_INS_MULLD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCDUXIA, PPC_INS_QVSTFCDUXIA, + {PPC_MULLI, PPC_INS_MULLI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCDX, PPC_INS_QVSTFCDX, + {PPC_MULLI8, PPC_INS_MULLI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCDXA, PPC_INS_QVSTFCDXA, + {PPC_MULLW, PPC_INS_MULLW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCDXI, PPC_INS_QVSTFCDXI, + {PPC_MULLW_rec, + PPC_INS_MULLW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCDXIA, PPC_INS_QVSTFCDXIA, + {PPC_NAND, PPC_INS_NAND, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCSUX, PPC_INS_QVSTFCSUX, + {PPC_NAND8, PPC_INS_NAND, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCSUXA, PPC_INS_QVSTFCSUXA, + {PPC_NAND8_rec, + PPC_INS_NAND, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCSUXI, PPC_INS_QVSTFCSUXI, + {PPC_NAND_rec, + PPC_INS_NAND, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCSUXIA, PPC_INS_QVSTFCSUXIA, + {PPC_NAP, PPC_INS_NAP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCSX, PPC_INS_QVSTFCSX, + {PPC_NEG, PPC_INS_NEG, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCSXA, PPC_INS_QVSTFCSXA, + {PPC_NEG8, PPC_INS_NEG, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCSXI, PPC_INS_QVSTFCSXI, + {PPC_NEG8_rec, + PPC_INS_NEG, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCSXIA, PPC_INS_QVSTFCSXIA, + {PPC_NEG_rec, + PPC_INS_NEG, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFCSXs, PPC_INS_QVSTFCSX, + {PPC_NOP, PPC_INS_NOP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFDUX, PPC_INS_QVSTFDUX, + {PPC_NOP_GT_PWR6, + PPC_INS_ORI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFDUXA, PPC_INS_QVSTFDUXA, + {PPC_NOP_GT_PWR7, + PPC_INS_ORI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFDUXI, PPC_INS_QVSTFDUXI, + {PPC_NOR, PPC_INS_NOR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFDUXIA, PPC_INS_QVSTFDUXIA, + {PPC_NOR8, PPC_INS_NOT, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFDX, PPC_INS_QVSTFDX, + {PPC_NOR8_rec, + PPC_INS_NOT, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFDXA, PPC_INS_QVSTFDXA, + {PPC_NOR_rec, + PPC_INS_NOR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFDXI, PPC_INS_QVSTFDXI, + {PPC_OR, PPC_INS_OR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_QVSTFDXIA, PPC_INS_QVSTFDXIA, + {PPC_OR8, PPC_INS_MR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_QVSTFDXb, PPC_INS_QVSTFDX, + {PPC_OR8_rec, + PPC_INS_MR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFIWX, PPC_INS_QVSTFIWX, + {PPC_ORC, PPC_INS_ORC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFIWXA, PPC_INS_QVSTFIWXA, + {PPC_ORC8, PPC_INS_ORC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSUX, PPC_INS_QVSTFSUX, + {PPC_ORC8_rec, + PPC_INS_ORC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSUXA, PPC_INS_QVSTFSUXA, + {PPC_ORC_rec, + PPC_INS_ORC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSUXI, PPC_INS_QVSTFSUXI, + {PPC_ORI, PPC_INS_ORI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSUXIA, PPC_INS_QVSTFSUXIA, + {PPC_ORI8, PPC_INS_ORI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSUXs, PPC_INS_QVSTFSUX, + {PPC_ORIS, PPC_INS_ORIS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSX, PPC_INS_QVSTFSX, + {PPC_ORIS8, PPC_INS_ORIS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSXA, PPC_INS_QVSTFSXA, + {PPC_OR_rec, PPC_INS_OR, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, {PPC_REG_CR0, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSXI, PPC_INS_QVSTFSXI, + {PPC_POPCNTB, + PPC_INS_POPCNTB, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSXIA, PPC_INS_QVSTFSXIA, + {PPC_POPCNTD, + PPC_INS_POPCNTD, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_QVSTFSXs, PPC_INS_QVSTFSX, + {PPC_POPCNTW, + PPC_INS_POPCNTW, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RFCI, PPC_INS_RFCI, + {PPC_RFCI, PPC_INS_RFCI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_BOOKE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_RFDI, PPC_INS_RFDI, + {PPC_RFDI, PPC_INS_RFDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_E500, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_E500, 0}, 0, + 0 #endif -}, + }, -{ - PPC_RFEBB, PPC_INS_RFEBB, + {PPC_RFEBB, PPC_INS_RFEBB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_RFI, PPC_INS_RFI, + {PPC_RFI, PPC_INS_RFI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_BOOKE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_RFID, PPC_INS_RFID, + {PPC_RFID, PPC_INS_RFID, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_RFMCI, PPC_INS_RFMCI, + {PPC_RFMCI, PPC_INS_RFMCI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_E500, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_E500, 0}, 0, + 0 #endif -}, + }, -{ - PPC_RLDCL, PPC_INS_RLDCL, + {PPC_RLDCL, PPC_INS_RLDCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLDCLo, PPC_INS_RLDCL, + {PPC_RLDCL_rec, + PPC_INS_RLDCL, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLDCR, PPC_INS_RLDCR, + {PPC_RLDCR, PPC_INS_RLDCR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLDCRo, PPC_INS_RLDCR, + {PPC_RLDCR_rec, + PPC_INS_RLDCR, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLDIC, PPC_INS_RLDIC, + {PPC_RLDIC, PPC_INS_RLDIC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLDICL, PPC_INS_CLRLDI, + {PPC_RLDICL, PPC_INS_CLRLDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLDICL_32_64, PPC_INS_CLRLDI, + {PPC_RLDICL_32_64, + PPC_INS_CLRLDI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLDICLo, PPC_INS_CLRLDI, + {PPC_RLDICL_rec, + PPC_INS_CLRLDI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLDICR, PPC_INS_RLDICR, + {PPC_RLDICR, PPC_INS_RLDICR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLDICRo, PPC_INS_RLDICR, + {PPC_RLDICR_rec, + PPC_INS_RLDICR, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLDICo, PPC_INS_RLDIC, + {PPC_RLDIC_rec, + PPC_INS_RLDIC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLDIMI, PPC_INS_RLDIMI, + {PPC_RLDIMI, PPC_INS_RLDIMI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLDIMIo, PPC_INS_RLDIMI, + {PPC_RLDIMI_rec, + PPC_INS_RLDIMI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWIMI, PPC_INS_RLWIMI, + {PPC_RLWIMI, PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLWIMI8, PPC_INS_RLWIMI, + {PPC_RLWIMI8, + PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWIMI8o, PPC_INS_RLWIMI, + {PPC_RLWIMI8_rec, + PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWIMIo, PPC_INS_RLWIMI, + {PPC_RLWIMI_rec, + PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWINM, PPC_INS_CLRLWI, + {PPC_RLWINM, PPC_INS_CLRLWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLWINM8, PPC_INS_RLWINM, + {PPC_RLWINM8, + PPC_INS_RLWINM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWINM8o, PPC_INS_RLWINM, + {PPC_RLWINM8_rec, + PPC_INS_RLWINM, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWINMo, PPC_INS_CLRLWI, + {PPC_RLWINM_rec, + PPC_INS_CLRLWI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWNM, PPC_INS_RLWNM, + {PPC_RLWNM, PPC_INS_RLWNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLWNM8, PPC_INS_RLWNM, + {PPC_RLWNM8, PPC_INS_RLWNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_RLWNM8o, PPC_INS_RLWNM, + {PPC_RLWNM8_rec, + PPC_INS_RLWNM, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_RLWNMo, PPC_INS_RLWNM, + {PPC_RLWNM_rec, + PPC_INS_RLWNM, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SC, PPC_INS_SC, + {PPC_SC, PPC_INS_SC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_SETB, PPC_INS_SETB, + {PPC_SETB, PPC_INS_SETB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLBIA, PPC_INS_SLBIA, + {PPC_SLBIA, PPC_INS_SLBIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLBIE, PPC_INS_SLBIE, + {PPC_SLBIE, PPC_INS_SLBIE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLBIEG, PPC_INS_SLBIEG, + {PPC_SLBIEG, PPC_INS_SLBIEG, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLBMFEE, PPC_INS_SLBMFEE, + {PPC_SLBMFEE, + PPC_INS_SLBMFEE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SLBMFEV, PPC_INS_SLBMFEV, + {PPC_SLBMFEV, + PPC_INS_SLBMFEV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SLBMTE, PPC_INS_SLBMTE, + {PPC_SLBMTE, PPC_INS_SLBMTE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLBSYNC, PPC_INS_SLBSYNC, + {PPC_SLBSYNC, + PPC_INS_SLBSYNC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SLD, PPC_INS_SLD, + {PPC_SLD, PPC_INS_SLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLDo, PPC_INS_SLD, + {PPC_SLD_rec, + PPC_INS_SLD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SLW, PPC_INS_SLW, + {PPC_SLW, PPC_INS_SLW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLW8, PPC_INS_SLW, + {PPC_SLW8, PPC_INS_SLW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SLW8o, PPC_INS_SLW, + {PPC_SLW8_rec, + PPC_INS_SLW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SLWo, PPC_INS_SLW, + {PPC_SLW_rec, + PPC_INS_SLW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SPELWZ, PPC_INS_LWZ, + {PPC_SPELWZ, PPC_INS_LWZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SPELWZX, PPC_INS_LWZX, + {PPC_SPELWZX, + PPC_INS_LWZX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SPESTW, PPC_INS_STW, + {PPC_SPESTW, PPC_INS_STW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SPESTWX, PPC_INS_STWX, + {PPC_SPESTWX, + PPC_INS_STWX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SRAD, PPC_INS_SRAD, + {PPC_SRAD, PPC_INS_SRAD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SRADI, PPC_INS_SRADI, + {PPC_SRADI, PPC_INS_SRADI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SRADIo, PPC_INS_SRADI, + {PPC_SRADI_rec, + PPC_INS_SRADI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SRADo, PPC_INS_SRAD, + {PPC_SRAD_rec, + PPC_INS_SRAD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SRAW, PPC_INS_SRAW, + {PPC_SRAW, PPC_INS_SRAW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SRAWI, PPC_INS_SRAWI, + {PPC_SRAWI, PPC_INS_SRAWI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SRAWIo, PPC_INS_SRAWI, + {PPC_SRAWI_rec, + PPC_INS_SRAWI, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SRAWo, PPC_INS_SRAW, + {PPC_SRAW_rec, + PPC_INS_SRAW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SRD, PPC_INS_SRD, + {PPC_SRD, PPC_INS_SRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SRDo, PPC_INS_SRD, + {PPC_SRD_rec, + PPC_INS_SRD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SRW, PPC_INS_SRW, + {PPC_SRW, PPC_INS_SRW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SRW8, PPC_INS_SRW, + {PPC_SRW8, PPC_INS_SRW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SRW8o, PPC_INS_SRW, + {PPC_SRW8_rec, + PPC_INS_SRW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SRWo, PPC_INS_SRW, + {PPC_SRW_rec, + PPC_INS_SRW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STB, PPC_INS_STB, + {PPC_STB, PPC_INS_STB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STB8, PPC_INS_STB, + {PPC_STB8, PPC_INS_STB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBCIX, PPC_INS_STBCIX, + {PPC_STBCIX, PPC_INS_STBCIX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBCX, PPC_INS_STBCX, + {PPC_STBCX, PPC_INS_STBCX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBEPX, PPC_INS_STBEPX, + {PPC_STBEPX, PPC_INS_STBEPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBU, PPC_INS_STBU, + {PPC_STBU, PPC_INS_STBU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBU8, PPC_INS_STBU, + {PPC_STBU8, PPC_INS_STBU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBUX, PPC_INS_STBUX, + {PPC_STBUX, PPC_INS_STBUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBUX8, PPC_INS_STBUX, + {PPC_STBUX8, PPC_INS_STBUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBX, PPC_INS_STBX, + {PPC_STBX, PPC_INS_STBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBX8, PPC_INS_STBX, + {PPC_STBX8, PPC_INS_STBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STBXTLS_, PPC_INS_STBX, + {PPC_STBXTLS_, + PPC_INS_STBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STD, PPC_INS_STD, + {PPC_STD, PPC_INS_STD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STDAT, PPC_INS_STDAT, + {PPC_STDAT, PPC_INS_STDAT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STDBRX, PPC_INS_STDBRX, + {PPC_STDBRX, PPC_INS_STDBRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STDCIX, PPC_INS_STDCIX, + {PPC_STDCIX, PPC_INS_STDCIX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STDCX, PPC_INS_STDCX, + {PPC_STDCX, PPC_INS_STDCX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CR0, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STDU, PPC_INS_STDU, + {PPC_STDU, PPC_INS_STDU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STDUX, PPC_INS_STDUX, + {PPC_STDUX, PPC_INS_STDUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STDX, PPC_INS_STDX, + {PPC_STDX, PPC_INS_STDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STDXTLS_, PPC_INS_STDX, + {PPC_STDXTLS_, + PPC_INS_STDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STFD, PPC_INS_STFD, + {PPC_STFD, PPC_INS_STFD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STFDEPX, PPC_INS_STFDEPX, + {PPC_STFDEPX, + PPC_INS_STFDEPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STFDU, PPC_INS_STFDU, + {PPC_STFDU, PPC_INS_STFDU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STFDUX, PPC_INS_STFDUX, + {PPC_STFDUX, PPC_INS_STFDUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STFDX, PPC_INS_STFDX, + {PPC_STFDX, PPC_INS_STFDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STFIWX, PPC_INS_STFIWX, + {PPC_STFIWX, PPC_INS_STFIWX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STFS, PPC_INS_STFS, + {PPC_STFS, PPC_INS_STFS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STFSU, PPC_INS_STFSU, + {PPC_STFSU, PPC_INS_STFSU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STFSUX, PPC_INS_STFSUX, + {PPC_STFSUX, PPC_INS_STFSUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STFSX, PPC_INS_STFSX, + {PPC_STFSX, PPC_INS_STFSX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STH, PPC_INS_STH, + {PPC_STH, PPC_INS_STH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STH8, PPC_INS_STH, + {PPC_STH8, PPC_INS_STH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHBRX, PPC_INS_STHBRX, + {PPC_STHBRX, PPC_INS_STHBRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHCIX, PPC_INS_STHCIX, + {PPC_STHCIX, PPC_INS_STHCIX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHCX, PPC_INS_STHCX, + {PPC_STHCX, PPC_INS_STHCX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHEPX, PPC_INS_STHEPX, + {PPC_STHEPX, PPC_INS_STHEPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHU, PPC_INS_STHU, + {PPC_STHU, PPC_INS_STHU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHU8, PPC_INS_STHU, + {PPC_STHU8, PPC_INS_STHU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHUX, PPC_INS_STHUX, + {PPC_STHUX, PPC_INS_STHUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHUX8, PPC_INS_STHUX, + {PPC_STHUX8, PPC_INS_STHUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHX, PPC_INS_STHX, + {PPC_STHX, PPC_INS_STHX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHX8, PPC_INS_STHX, + {PPC_STHX8, PPC_INS_STHX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STHXTLS_, PPC_INS_STHX, + {PPC_STHXTLS_, + PPC_INS_STHX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STMW, PPC_INS_STMW, + {PPC_STMW, PPC_INS_STMW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STOP, PPC_INS_STOP, + {PPC_STOP, PPC_INS_STOP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STSWI, PPC_INS_STSWI, + {PPC_STSWI, PPC_INS_STSWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STVEBX, PPC_INS_STVEBX, + {PPC_STVEBX, + PPC_INS_STVEBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_STVEHX, PPC_INS_STVEHX, + {PPC_STVEHX, + PPC_INS_STVEHX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_STVEWX, PPC_INS_STVEWX, + {PPC_STVEWX, + PPC_INS_STVEWX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_STVX, PPC_INS_STVX, + {PPC_STVX, PPC_INS_STVX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_STVXL, PPC_INS_STVXL, + {PPC_STVXL, PPC_INS_STVXL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_STW, PPC_INS_STW, + {PPC_STW, PPC_INS_STW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STW8, PPC_INS_STW, + {PPC_STW8, PPC_INS_STW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWAT, PPC_INS_STWAT, + {PPC_STWAT, PPC_INS_STWAT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWBRX, PPC_INS_STWBRX, + {PPC_STWBRX, PPC_INS_STWBRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWCIX, PPC_INS_STWCIX, + {PPC_STWCIX, PPC_INS_STWCIX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWCX, PPC_INS_STWCX, + {PPC_STWCX, PPC_INS_STWCX, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CR0, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWEPX, PPC_INS_STWEPX, + {PPC_STWEPX, PPC_INS_STWEPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWU, PPC_INS_STWU, + {PPC_STWU, PPC_INS_STWU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWU8, PPC_INS_STWU, + {PPC_STWU8, PPC_INS_STWU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWUX, PPC_INS_STWUX, + {PPC_STWUX, PPC_INS_STWUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWUX8, PPC_INS_STWUX, + {PPC_STWUX8, PPC_INS_STWUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWX, PPC_INS_STWX, + {PPC_STWX, PPC_INS_STWX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWX8, PPC_INS_STWX, + {PPC_STWX8, PPC_INS_STWX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STWXTLS_, PPC_INS_STWX, + {PPC_STWXTLS_, + PPC_INS_STWX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXSD, PPC_INS_STXSD, + {PPC_STXSD, PPC_INS_STXSD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STXSDX, PPC_INS_STXSDX, + {PPC_STXSDX, + PPC_INS_STXSDX, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXSIBX, PPC_INS_STXSIBX, + {PPC_STXSIBX, + PPC_INS_STXSIBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXSIHX, PPC_INS_STXSIHX, + {PPC_STXSIHX, + PPC_INS_STXSIHX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXSIWX, PPC_INS_STXSIWX, + {PPC_STXSIWX, + PPC_INS_STXSIWX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXSSP, PPC_INS_STXSSP, + {PPC_STXSSP, PPC_INS_STXSSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STXSSPX, PPC_INS_STXSSPX, + {PPC_STXSSPX, + PPC_INS_STXSSPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXV, PPC_INS_STXV, + {PPC_STXV, PPC_INS_STXV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STXVB16X, PPC_INS_STXVB16X, + {PPC_STXVB16X, + PPC_INS_STXVB16X, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXVD2X, PPC_INS_STXVD2X, + {PPC_STXVD2X, + PPC_INS_STXVD2X, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXVH8X, PPC_INS_STXVH8X, + {PPC_STXVH8X, + PPC_INS_STXVH8X, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXVL, PPC_INS_STXVL, + {PPC_STXVL, PPC_INS_STXVL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_STXVLL, PPC_INS_STXVLL, + {PPC_STXVLL, PPC_INS_STXVLL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_STXVW4X, PPC_INS_STXVW4X, + {PPC_STXVW4X, + PPC_INS_STXVW4X, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_STXVX, PPC_INS_STXVX, + {PPC_STXVX, PPC_INS_STXVX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SUBF, PPC_INS_SUBF, + {PPC_SUBF, PPC_INS_SUBF, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SUBF8, PPC_INS_SUB, + {PPC_SUBF8, PPC_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SUBF8o, PPC_INS_SUB, + {PPC_SUBF8_rec, + PPC_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFC, PPC_INS_SUBFC, + {PPC_SUBFC, PPC_INS_SUBFC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SUBFC8, PPC_INS_SUBC, + {PPC_SUBFC8, PPC_INS_SUBC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SUBFC8o, PPC_INS_SUBC, + {PPC_SUBFC8_rec, + PPC_INS_SUBC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFCo, PPC_INS_SUBFC, + {PPC_SUBFC_rec, + PPC_INS_SUBFC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFE, PPC_INS_SUBFE, + {PPC_SUBFE, + PPC_INS_SUBFE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFE8, PPC_INS_SUBFE, + {PPC_SUBFE8, + PPC_INS_SUBFE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFE8o, PPC_INS_SUBFE, + {PPC_SUBFE8_rec, + PPC_INS_SUBFE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFEo, PPC_INS_SUBFE, + {PPC_SUBFE_rec, + PPC_INS_SUBFE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFIC, PPC_INS_SUBFIC, + {PPC_SUBFIC, PPC_INS_SUBFIC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, {PPC_REG_CARRY, 0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_SUBFIC8, PPC_INS_SUBFIC, + {PPC_SUBFIC8, + PPC_INS_SUBFIC, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFME, PPC_INS_SUBFME, + {PPC_SUBFME, + PPC_INS_SUBFME, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFME8, PPC_INS_SUBFME, + {PPC_SUBFME8, + PPC_INS_SUBFME, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFME8o, PPC_INS_SUBFME, + {PPC_SUBFME8_rec, + PPC_INS_SUBFME, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFMEo, PPC_INS_SUBFME, + {PPC_SUBFME_rec, + PPC_INS_SUBFME, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFZE, PPC_INS_SUBFZE, + {PPC_SUBFZE, + PPC_INS_SUBFZE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFZE8, PPC_INS_SUBFZE, + {PPC_SUBFZE8, + PPC_INS_SUBFZE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFZE8o, PPC_INS_SUBFZE, + {PPC_SUBFZE8_rec, + PPC_INS_SUBFZE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFZEo, PPC_INS_SUBFZE, + {PPC_SUBFZE_rec, + PPC_INS_SUBFZE, #ifndef CAPSTONE_DIET - { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {PPC_REG_CARRY, 0}, + {PPC_REG_CARRY, PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SUBFo, PPC_INS_SUBF, + {PPC_SUBF_rec, + PPC_INS_SUBF, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_SYNC, PPC_INS_LWSYNC, + {PPC_SYNC, PPC_INS_LWSYNC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_TABORT, PPC_INS_TABORT, + {PPC_TABORT, PPC_INS_TABORT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_TABORTDC, PPC_INS_TABORTDC, + {PPC_TABORTDC, + PPC_INS_TABORTDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_TABORTDCI, PPC_INS_TABORTDCI, + {PPC_TABORTDCI, + PPC_INS_TABORTDCI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_TABORTWC, PPC_INS_TABORTWC, + {PPC_TABORTWC, + PPC_INS_TABORTWC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_TABORTWCI, PPC_INS_TABORTWCI, + {PPC_TABORTWCI, + PPC_INS_TABORTWCI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_TAILB, PPC_INS_B, + {PPC_TAILB, + PPC_INS_B, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_TAILB8, PPC_INS_B, + {PPC_TAILB8, + PPC_INS_B, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_TAILBA, PPC_INS_BA, + {PPC_TAILBA, + PPC_INS_BA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_TAILBA8, PPC_INS_BA, + {PPC_TAILBA8, + PPC_INS_BA, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 + {PPC_REG_RM, 0}, + {0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_TAILBCTR, PPC_INS_BCTR, + {PPC_TAILBCTR, + PPC_INS_BCTR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE32, 0 }, 1, 1 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {0}, + {PPC_GRP_MODE32, 0}, + 1, + 1 #endif -}, + }, -{ - PPC_TAILBCTR8, PPC_INS_BCTR, + {PPC_TAILBCTR8, + PPC_INS_BCTR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR8, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 + {PPC_REG_CTR8, PPC_REG_RM, 0}, + {0}, + {PPC_GRP_MODE64, 0}, + 1, + 1 #endif -}, + }, -{ - PPC_TBEGIN, PPC_INS_TBEGIN, + {PPC_TBEGIN, PPC_INS_TBEGIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_TCHECK, PPC_INS_TCHECK, + {PPC_TCHECK, PPC_INS_TCHECK, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_TD, PPC_INS_TD, + {PPC_TD, PPC_INS_TD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_TDI, PPC_INS_TDEQI, + {PPC_TDI, PPC_INS_TDEQI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_TEND, PPC_INS_TEND, + {PPC_TEND, PPC_INS_TEND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBIA, PPC_INS_TLBIA, + {PPC_TLBIA, PPC_INS_TLBIA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBIE, PPC_INS_TLBIE, + {PPC_TLBIE, PPC_INS_TLBIE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBIEL, PPC_INS_TLBIEL, + {PPC_TLBIEL, PPC_INS_TLBIEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBIVAX, PPC_INS_TLBIVAX, + {PPC_TLBIVAX, + PPC_INS_TLBIVAX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_BOOKE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_TLBLD, PPC_INS_TLBLD, + {PPC_TLBLD, PPC_INS_TLBLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC6XX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_PPC6XX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBLI, PPC_INS_TLBLI, + {PPC_TLBLI, PPC_INS_TLBLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC6XX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_PPC6XX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBRE, PPC_INS_TLBRE, + {PPC_TLBRE, PPC_INS_TLBRE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_BOOKE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBRE2, PPC_INS_TLBRE, + {PPC_TLBRE2, PPC_INS_TLBRE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_PPC4XX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBSX, PPC_INS_TLBSX, + {PPC_TLBSX, PPC_INS_TLBSX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_BOOKE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBSX2, PPC_INS_TLBSX, + {PPC_TLBSX2, PPC_INS_TLBSX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_PPC4XX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBSX2D, PPC_INS_TLBSX, + {PPC_TLBSX2D, + PPC_INS_TLBSX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_PPC4XX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_TLBSYNC, PPC_INS_TLBSYNC, + {PPC_TLBSYNC, + PPC_INS_TLBSYNC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_TLBWE, PPC_INS_TLBWE, + {PPC_TLBWE, PPC_INS_TLBWE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_BOOKE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_TLBWE2, PPC_INS_TLBWE, + {PPC_TLBWE2, PPC_INS_TLBWE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_PPC4XX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_TRAP, PPC_INS_TRAP, + {PPC_TRAP, PPC_INS_TRAP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_TRECHKPT, PPC_INS_TRECHKPT, + {PPC_TRECHKPT, + PPC_INS_TRECHKPT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_TRECLAIM, PPC_INS_TRECLAIM, + {PPC_TRECLAIM, + PPC_INS_TRECLAIM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_TSR, PPC_INS_TSR, + {PPC_TSR, PPC_INS_TSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_TW, PPC_INS_TW, + {PPC_TW, PPC_INS_TW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, + 0, 0 #endif -}, + }, -{ - PPC_TWI, PPC_INS_TWEQI, + {PPC_TWI, PPC_INS_TWEQI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VABSDUB, PPC_INS_VABSDUB, + {PPC_VABSDUB, + PPC_INS_VABSDUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VABSDUH, PPC_INS_VABSDUH, + {PPC_VABSDUH, + PPC_INS_VABSDUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VABSDUW, PPC_INS_VABSDUW, + {PPC_VABSDUW, + PPC_INS_VABSDUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDCUQ, PPC_INS_VADDCUQ, + {PPC_VADDCUQ, + PPC_INS_VADDCUQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDCUW, PPC_INS_VADDCUW, + {PPC_VADDCUW, + PPC_INS_VADDCUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDECUQ, PPC_INS_VADDECUQ, + {PPC_VADDECUQ, + PPC_INS_VADDECUQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDEUQM, PPC_INS_VADDEUQM, + {PPC_VADDEUQM, + PPC_INS_VADDEUQM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDFP, PPC_INS_VADDFP, + {PPC_VADDFP, + PPC_INS_VADDFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDSBS, PPC_INS_VADDSBS, + {PPC_VADDSBS, + PPC_INS_VADDSBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDSHS, PPC_INS_VADDSHS, + {PPC_VADDSHS, + PPC_INS_VADDSHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDSWS, PPC_INS_VADDSWS, + {PPC_VADDSWS, + PPC_INS_VADDSWS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDUBM, PPC_INS_VADDUBM, + {PPC_VADDUBM, + PPC_INS_VADDUBM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDUBS, PPC_INS_VADDUBS, + {PPC_VADDUBS, + PPC_INS_VADDUBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDUDM, PPC_INS_VADDUDM, + {PPC_VADDUDM, + PPC_INS_VADDUDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDUHM, PPC_INS_VADDUHM, + {PPC_VADDUHM, + PPC_INS_VADDUHM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDUHS, PPC_INS_VADDUHS, + {PPC_VADDUHS, + PPC_INS_VADDUHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDUQM, PPC_INS_VADDUQM, + {PPC_VADDUQM, + PPC_INS_VADDUQM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDUWM, PPC_INS_VADDUWM, + {PPC_VADDUWM, + PPC_INS_VADDUWM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VADDUWS, PPC_INS_VADDUWS, + {PPC_VADDUWS, + PPC_INS_VADDUWS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VAND, PPC_INS_VAND, + {PPC_VAND, PPC_INS_VAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VANDC, PPC_INS_VANDC, + {PPC_VANDC, PPC_INS_VANDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VAVGSB, PPC_INS_VAVGSB, + {PPC_VAVGSB, + PPC_INS_VAVGSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VAVGSH, PPC_INS_VAVGSH, + {PPC_VAVGSH, + PPC_INS_VAVGSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VAVGSW, PPC_INS_VAVGSW, + {PPC_VAVGSW, + PPC_INS_VAVGSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VAVGUB, PPC_INS_VAVGUB, + {PPC_VAVGUB, + PPC_INS_VAVGUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VAVGUH, PPC_INS_VAVGUH, + {PPC_VAVGUH, + PPC_INS_VAVGUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VAVGUW, PPC_INS_VAVGUW, + {PPC_VAVGUW, + PPC_INS_VAVGUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VBPERMD, PPC_INS_VBPERMD, + {PPC_VBPERMD, + PPC_INS_VBPERMD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VBPERMQ, PPC_INS_VBPERMQ, + {PPC_VBPERMQ, + PPC_INS_VBPERMQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCFSX, PPC_INS_VCFSX, + {PPC_VCFSX, PPC_INS_VCFSX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VCFSX_0, PPC_INS_VCFSX, + {PPC_VCFSX_0, + PPC_INS_VCFSX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCFUX, PPC_INS_VCFUX, + {PPC_VCFUX, PPC_INS_VCFUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VCFUX_0, PPC_INS_VCFUX, + {PPC_VCFUX_0, + PPC_INS_VCFUX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCIPHER, PPC_INS_VCIPHER, + {PPC_VCIPHER, + PPC_INS_VCIPHER, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCIPHERLAST, PPC_INS_VCIPHERLAST, + {PPC_VCIPHERLAST, + PPC_INS_VCIPHERLAST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCLZB, PPC_INS_VCLZB, + {PPC_VCLZB, PPC_INS_VCLZB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VCLZD, PPC_INS_VCLZD, + {PPC_VCLZD, PPC_INS_VCLZD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VCLZH, PPC_INS_VCLZH, + {PPC_VCLZH, PPC_INS_VCLZH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VCLZLSBB, PPC_INS_VCLZLSBB, + {PPC_VCLZLSBB, + PPC_INS_VCLZLSBB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCLZW, PPC_INS_VCLZW, + {PPC_VCLZW, PPC_INS_VCLZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VCMPBFP, PPC_INS_VCMPBFP, + {PPC_VCMPBFP, + PPC_INS_VCMPBFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPBFPo, PPC_INS_VCMPBFP, + {PPC_VCMPBFP_rec, + PPC_INS_VCMPBFP, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQFP, PPC_INS_VCMPEQFP, + {PPC_VCMPEQFP, + PPC_INS_VCMPEQFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQFPo, PPC_INS_VCMPEQFP, + {PPC_VCMPEQFP_rec, + PPC_INS_VCMPEQFP, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQUB, PPC_INS_VCMPEQUB, + {PPC_VCMPEQUB, + PPC_INS_VCMPEQUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQUBo, PPC_INS_VCMPEQUB, + {PPC_VCMPEQUB_rec, + PPC_INS_VCMPEQUB, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQUD, PPC_INS_VCMPEQUD, + {PPC_VCMPEQUD, + PPC_INS_VCMPEQUD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQUDo, PPC_INS_VCMPEQUD, + {PPC_VCMPEQUD_rec, + PPC_INS_VCMPEQUD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQUH, PPC_INS_VCMPEQUH, + {PPC_VCMPEQUH, + PPC_INS_VCMPEQUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQUHo, PPC_INS_VCMPEQUH, + {PPC_VCMPEQUH_rec, + PPC_INS_VCMPEQUH, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQUW, PPC_INS_VCMPEQUW, + {PPC_VCMPEQUW, + PPC_INS_VCMPEQUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPEQUWo, PPC_INS_VCMPEQUW, + {PPC_VCMPEQUW_rec, + PPC_INS_VCMPEQUW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGEFP, PPC_INS_VCMPGEFP, + {PPC_VCMPGEFP, + PPC_INS_VCMPGEFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGEFPo, PPC_INS_VCMPGEFP, + {PPC_VCMPGEFP_rec, + PPC_INS_VCMPGEFP, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTFP, PPC_INS_VCMPGTFP, + {PPC_VCMPGTFP, + PPC_INS_VCMPGTFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTFPo, PPC_INS_VCMPGTFP, + {PPC_VCMPGTFP_rec, + PPC_INS_VCMPGTFP, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTSB, PPC_INS_VCMPGTSB, + {PPC_VCMPGTSB, + PPC_INS_VCMPGTSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTSBo, PPC_INS_VCMPGTSB, + {PPC_VCMPGTSB_rec, + PPC_INS_VCMPGTSB, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTSD, PPC_INS_VCMPGTSD, + {PPC_VCMPGTSD, + PPC_INS_VCMPGTSD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTSDo, PPC_INS_VCMPGTSD, + {PPC_VCMPGTSD_rec, + PPC_INS_VCMPGTSD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTSH, PPC_INS_VCMPGTSH, + {PPC_VCMPGTSH, + PPC_INS_VCMPGTSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTSHo, PPC_INS_VCMPGTSH, + {PPC_VCMPGTSH_rec, + PPC_INS_VCMPGTSH, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTSW, PPC_INS_VCMPGTSW, + {PPC_VCMPGTSW, + PPC_INS_VCMPGTSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTSWo, PPC_INS_VCMPGTSW, + {PPC_VCMPGTSW_rec, + PPC_INS_VCMPGTSW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTUB, PPC_INS_VCMPGTUB, + {PPC_VCMPGTUB, + PPC_INS_VCMPGTUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTUBo, PPC_INS_VCMPGTUB, + {PPC_VCMPGTUB_rec, + PPC_INS_VCMPGTUB, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTUD, PPC_INS_VCMPGTUD, + {PPC_VCMPGTUD, + PPC_INS_VCMPGTUD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTUDo, PPC_INS_VCMPGTUD, + {PPC_VCMPGTUD_rec, + PPC_INS_VCMPGTUD, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTUH, PPC_INS_VCMPGTUH, + {PPC_VCMPGTUH, + PPC_INS_VCMPGTUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTUHo, PPC_INS_VCMPGTUH, + {PPC_VCMPGTUH_rec, + PPC_INS_VCMPGTUH, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTUW, PPC_INS_VCMPGTUW, + {PPC_VCMPGTUW, + PPC_INS_VCMPGTUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPGTUWo, PPC_INS_VCMPGTUW, + {PPC_VCMPGTUW_rec, + PPC_INS_VCMPGTUW, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEB, PPC_INS_VCMPNEB, + {PPC_VCMPNEB, + PPC_INS_VCMPNEB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEBo, PPC_INS_VCMPNEB, + {PPC_VCMPNEB_rec, + PPC_INS_VCMPNEB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEH, PPC_INS_VCMPNEH, + {PPC_VCMPNEH, + PPC_INS_VCMPNEH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEHo, PPC_INS_VCMPNEH, + {PPC_VCMPNEH_rec, + PPC_INS_VCMPNEH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEW, PPC_INS_VCMPNEW, + {PPC_VCMPNEW, + PPC_INS_VCMPNEW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEWo, PPC_INS_VCMPNEW, + {PPC_VCMPNEW_rec, + PPC_INS_VCMPNEW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEZB, PPC_INS_VCMPNEZB, + {PPC_VCMPNEZB, + PPC_INS_VCMPNEZB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEZBo, PPC_INS_VCMPNEZB, + {PPC_VCMPNEZB_rec, + PPC_INS_VCMPNEZB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEZH, PPC_INS_VCMPNEZH, + {PPC_VCMPNEZH, + PPC_INS_VCMPNEZH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEZHo, PPC_INS_VCMPNEZH, + {PPC_VCMPNEZH_rec, + PPC_INS_VCMPNEZH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEZW, PPC_INS_VCMPNEZW, + {PPC_VCMPNEZW, + PPC_INS_VCMPNEZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCMPNEZWo, PPC_INS_VCMPNEZW, + {PPC_VCMPNEZW_rec, + PPC_INS_VCMPNEZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCTSXS, PPC_INS_VCTSXS, + {PPC_VCTSXS, + PPC_INS_VCTSXS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCTSXS_0, PPC_INS_VCTSXS, + {PPC_VCTSXS_0, + PPC_INS_VCTSXS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCTUXS, PPC_INS_VCTUXS, + {PPC_VCTUXS, + PPC_INS_VCTUXS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCTUXS_0, PPC_INS_VCTUXS, + {PPC_VCTUXS_0, + PPC_INS_VCTUXS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCTZB, PPC_INS_VCTZB, + {PPC_VCTZB, PPC_INS_VCTZB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VCTZD, PPC_INS_VCTZD, + {PPC_VCTZD, PPC_INS_VCTZD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VCTZH, PPC_INS_VCTZH, + {PPC_VCTZH, PPC_INS_VCTZH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VCTZLSBB, PPC_INS_VCTZLSBB, + {PPC_VCTZLSBB, + PPC_INS_VCTZLSBB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VCTZW, PPC_INS_VCTZW, + {PPC_VCTZW, PPC_INS_VCTZW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VEQV, PPC_INS_VEQV, + {PPC_VEQV, PPC_INS_VEQV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VEXPTEFP, PPC_INS_VEXPTEFP, + {PPC_VEXPTEFP, + PPC_INS_VEXPTEFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTRACTD, PPC_INS_VEXTRACTD, + {PPC_VEXTRACTD, + PPC_INS_VEXTRACTD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTRACTUB, PPC_INS_VEXTRACTUB, + {PPC_VEXTRACTUB, + PPC_INS_VEXTRACTUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTRACTUH, PPC_INS_VEXTRACTUH, + {PPC_VEXTRACTUH, + PPC_INS_VEXTRACTUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTRACTUW, PPC_INS_VEXTRACTUW, + {PPC_VEXTRACTUW, + PPC_INS_VEXTRACTUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTSB2D, PPC_INS_VEXTSB2D, + {PPC_VEXTSB2D, + PPC_INS_VEXTSB2D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTSB2W, PPC_INS_VEXTSB2W, + {PPC_VEXTSB2W, + PPC_INS_VEXTSB2W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTSH2D, PPC_INS_VEXTSH2D, + {PPC_VEXTSH2D, + PPC_INS_VEXTSH2D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTSH2W, PPC_INS_VEXTSH2W, + {PPC_VEXTSH2W, + PPC_INS_VEXTSH2W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTSW2D, PPC_INS_VEXTSW2D, + {PPC_VEXTSW2D, + PPC_INS_VEXTSW2D, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTUBLX, PPC_INS_VEXTUBLX, + {PPC_VEXTUBLX, + PPC_INS_VEXTUBLX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTUBRX, PPC_INS_VEXTUBRX, + {PPC_VEXTUBRX, + PPC_INS_VEXTUBRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTUHLX, PPC_INS_VEXTUHLX, + {PPC_VEXTUHLX, + PPC_INS_VEXTUHLX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTUHRX, PPC_INS_VEXTUHRX, + {PPC_VEXTUHRX, + PPC_INS_VEXTUHRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTUWLX, PPC_INS_VEXTUWLX, + {PPC_VEXTUWLX, + PPC_INS_VEXTUWLX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VEXTUWRX, PPC_INS_VEXTUWRX, + {PPC_VEXTUWRX, + PPC_INS_VEXTUWRX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VGBBD, PPC_INS_VGBBD, + {PPC_VGBBD, PPC_INS_VGBBD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VINSERTB, PPC_INS_VINSERTB, + {PPC_VINSERTB, + PPC_INS_VINSERTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VINSERTD, PPC_INS_VINSERTD, + {PPC_VINSERTD, + PPC_INS_VINSERTD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VINSERTH, PPC_INS_VINSERTH, + {PPC_VINSERTH, + PPC_INS_VINSERTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VINSERTW, PPC_INS_VINSERTW, + {PPC_VINSERTW, + PPC_INS_VINSERTW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VLOGEFP, PPC_INS_VLOGEFP, + {PPC_VLOGEFP, + PPC_INS_VLOGEFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMADDFP, PPC_INS_VMADDFP, + {PPC_VMADDFP, + PPC_INS_VMADDFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMAXFP, PPC_INS_VMAXFP, + {PPC_VMAXFP, + PPC_INS_VMAXFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMAXSB, PPC_INS_VMAXSB, + {PPC_VMAXSB, + PPC_INS_VMAXSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMAXSD, PPC_INS_VMAXSD, + {PPC_VMAXSD, + PPC_INS_VMAXSD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMAXSH, PPC_INS_VMAXSH, + {PPC_VMAXSH, + PPC_INS_VMAXSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMAXSW, PPC_INS_VMAXSW, + {PPC_VMAXSW, + PPC_INS_VMAXSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMAXUB, PPC_INS_VMAXUB, + {PPC_VMAXUB, + PPC_INS_VMAXUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMAXUD, PPC_INS_VMAXUD, + {PPC_VMAXUD, + PPC_INS_VMAXUD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMAXUH, PPC_INS_VMAXUH, + {PPC_VMAXUH, + PPC_INS_VMAXUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMAXUW, PPC_INS_VMAXUW, + {PPC_VMAXUW, + PPC_INS_VMAXUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMHADDSHS, PPC_INS_VMHADDSHS, + {PPC_VMHADDSHS, + PPC_INS_VMHADDSHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMHRADDSHS, PPC_INS_VMHRADDSHS, + {PPC_VMHRADDSHS, + PPC_INS_VMHRADDSHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMINFP, PPC_INS_VMINFP, + {PPC_VMINFP, + PPC_INS_VMINFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMINSB, PPC_INS_VMINSB, + {PPC_VMINSB, + PPC_INS_VMINSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMINSD, PPC_INS_VMINSD, + {PPC_VMINSD, + PPC_INS_VMINSD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMINSH, PPC_INS_VMINSH, + {PPC_VMINSH, + PPC_INS_VMINSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMINSW, PPC_INS_VMINSW, + {PPC_VMINSW, + PPC_INS_VMINSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMINUB, PPC_INS_VMINUB, + {PPC_VMINUB, + PPC_INS_VMINUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMINUD, PPC_INS_VMINUD, + {PPC_VMINUD, PPC_INS_VMINUD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_VMINUH, PPC_INS_VMINUH, + {PPC_VMINUH, + PPC_INS_VMINUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMINUW, PPC_INS_VMINUW, + {PPC_VMINUW, + PPC_INS_VMINUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMLADDUHM, PPC_INS_VMLADDUHM, + {PPC_VMLADDUHM, + PPC_INS_VMLADDUHM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMRGEW, PPC_INS_VMRGEW, + {PPC_VMRGEW, PPC_INS_VMRGEW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_VMRGHB, PPC_INS_VMRGHB, + {PPC_VMRGHB, + PPC_INS_VMRGHB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMRGHH, PPC_INS_VMRGHH, + {PPC_VMRGHH, + PPC_INS_VMRGHH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMRGHW, PPC_INS_VMRGHW, + {PPC_VMRGHW, + PPC_INS_VMRGHW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMRGLB, PPC_INS_VMRGLB, + {PPC_VMRGLB, + PPC_INS_VMRGLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMRGLH, PPC_INS_VMRGLH, + {PPC_VMRGLH, + PPC_INS_VMRGLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMRGLW, PPC_INS_VMRGLW, + {PPC_VMRGLW, + PPC_INS_VMRGLW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMRGOW, PPC_INS_VMRGOW, + {PPC_VMRGOW, PPC_INS_VMRGOW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_VMSUMMBM, PPC_INS_VMSUMMBM, + {PPC_VMSUMMBM, + PPC_INS_VMSUMMBM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMSUMSHM, PPC_INS_VMSUMSHM, + {PPC_VMSUMSHM, + PPC_INS_VMSUMSHM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMSUMSHS, PPC_INS_VMSUMSHS, + {PPC_VMSUMSHS, + PPC_INS_VMSUMSHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMSUMUBM, PPC_INS_VMSUMUBM, + {PPC_VMSUMUBM, + PPC_INS_VMSUMUBM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMSUMUHM, PPC_INS_VMSUMUHM, + {PPC_VMSUMUHM, + PPC_INS_VMSUMUHM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMSUMUHS, PPC_INS_VMSUMUHS, + {PPC_VMSUMUHS, + PPC_INS_VMSUMUHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMUL10CUQ, PPC_INS_VMUL10CUQ, + {PPC_VMUL10CUQ, + PPC_INS_VMUL10CUQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMUL10ECUQ, PPC_INS_VMUL10ECUQ, + {PPC_VMUL10ECUQ, + PPC_INS_VMUL10ECUQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMUL10EUQ, PPC_INS_VMUL10EUQ, + {PPC_VMUL10EUQ, + PPC_INS_VMUL10EUQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMUL10UQ, PPC_INS_VMUL10UQ, + {PPC_VMUL10UQ, + PPC_INS_VMUL10UQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULESB, PPC_INS_VMULESB, + {PPC_VMULESB, + PPC_INS_VMULESB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULESH, PPC_INS_VMULESH, + {PPC_VMULESH, + PPC_INS_VMULESH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULESW, PPC_INS_VMULESW, + {PPC_VMULESW, + PPC_INS_VMULESW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULEUB, PPC_INS_VMULEUB, + {PPC_VMULEUB, + PPC_INS_VMULEUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULEUH, PPC_INS_VMULEUH, + {PPC_VMULEUH, + PPC_INS_VMULEUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULEUW, PPC_INS_VMULEUW, + {PPC_VMULEUW, + PPC_INS_VMULEUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULOSB, PPC_INS_VMULOSB, + {PPC_VMULOSB, + PPC_INS_VMULOSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULOSH, PPC_INS_VMULOSH, + {PPC_VMULOSH, + PPC_INS_VMULOSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULOSW, PPC_INS_VMULOSW, + {PPC_VMULOSW, + PPC_INS_VMULOSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULOUB, PPC_INS_VMULOUB, + {PPC_VMULOUB, + PPC_INS_VMULOUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULOUH, PPC_INS_VMULOUH, + {PPC_VMULOUH, + PPC_INS_VMULOUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULOUW, PPC_INS_VMULOUW, + {PPC_VMULOUW, + PPC_INS_VMULOUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VMULUWM, PPC_INS_VMULUWM, + {PPC_VMULUWM, + PPC_INS_VMULUWM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VNAND, PPC_INS_VNAND, + {PPC_VNAND, PPC_INS_VNAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VNCIPHER, PPC_INS_VNCIPHER, + {PPC_VNCIPHER, + PPC_INS_VNCIPHER, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VNCIPHERLAST, PPC_INS_VNCIPHERLAST, + {PPC_VNCIPHERLAST, + PPC_INS_VNCIPHERLAST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VNEGD, PPC_INS_VNEGD, + {PPC_VNEGD, PPC_INS_VNEGD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VNEGW, PPC_INS_VNEGW, + {PPC_VNEGW, PPC_INS_VNEGW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VNMSUBFP, PPC_INS_VNMSUBFP, + {PPC_VNMSUBFP, + PPC_INS_VNMSUBFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VNOR, PPC_INS_VNOR, + {PPC_VNOR, PPC_INS_VNOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VOR, PPC_INS_VOR, + {PPC_VOR, PPC_INS_VOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VORC, PPC_INS_VORC, + {PPC_VORC, PPC_INS_VORC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VPERM, PPC_INS_VPERM, + {PPC_VPERM, PPC_INS_VPERM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VPERMR, PPC_INS_VPERMR, + {PPC_VPERMR, PPC_INS_VPERMR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_VPERMXOR, PPC_INS_VPERMXOR, + {PPC_VPERMXOR, + PPC_INS_VPERMXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKPX, PPC_INS_VPKPX, + {PPC_VPKPX, PPC_INS_VPKPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VPKSDSS, PPC_INS_VPKSDSS, + {PPC_VPKSDSS, + PPC_INS_VPKSDSS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKSDUS, PPC_INS_VPKSDUS, + {PPC_VPKSDUS, + PPC_INS_VPKSDUS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKSHSS, PPC_INS_VPKSHSS, + {PPC_VPKSHSS, + PPC_INS_VPKSHSS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKSHUS, PPC_INS_VPKSHUS, + {PPC_VPKSHUS, + PPC_INS_VPKSHUS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKSWSS, PPC_INS_VPKSWSS, + {PPC_VPKSWSS, + PPC_INS_VPKSWSS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKSWUS, PPC_INS_VPKSWUS, + {PPC_VPKSWUS, + PPC_INS_VPKSWUS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKUDUM, PPC_INS_VPKUDUM, + {PPC_VPKUDUM, + PPC_INS_VPKUDUM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKUDUS, PPC_INS_VPKUDUS, + {PPC_VPKUDUS, + PPC_INS_VPKUDUS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKUHUM, PPC_INS_VPKUHUM, + {PPC_VPKUHUM, + PPC_INS_VPKUHUM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKUHUS, PPC_INS_VPKUHUS, + {PPC_VPKUHUS, + PPC_INS_VPKUHUS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKUWUM, PPC_INS_VPKUWUM, + {PPC_VPKUWUM, + PPC_INS_VPKUWUM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPKUWUS, PPC_INS_VPKUWUS, + {PPC_VPKUWUS, + PPC_INS_VPKUWUS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPMSUMB, PPC_INS_VPMSUMB, + {PPC_VPMSUMB, + PPC_INS_VPMSUMB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPMSUMD, PPC_INS_VPMSUMD, + {PPC_VPMSUMD, + PPC_INS_VPMSUMD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPMSUMH, PPC_INS_VPMSUMH, + {PPC_VPMSUMH, + PPC_INS_VPMSUMH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPMSUMW, PPC_INS_VPMSUMW, + {PPC_VPMSUMW, + PPC_INS_VPMSUMW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPOPCNTB, PPC_INS_VPOPCNTB, + {PPC_VPOPCNTB, + PPC_INS_VPOPCNTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPOPCNTD, PPC_INS_VPOPCNTD, + {PPC_VPOPCNTD, + PPC_INS_VPOPCNTD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPOPCNTH, PPC_INS_VPOPCNTH, + {PPC_VPOPCNTH, + PPC_INS_VPOPCNTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPOPCNTW, PPC_INS_VPOPCNTW, + {PPC_VPOPCNTW, + PPC_INS_VPOPCNTW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPRTYBD, PPC_INS_VPRTYBD, + {PPC_VPRTYBD, + PPC_INS_VPRTYBD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPRTYBQ, PPC_INS_VPRTYBQ, + {PPC_VPRTYBQ, + PPC_INS_VPRTYBQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VPRTYBW, PPC_INS_VPRTYBW, + {PPC_VPRTYBW, + PPC_INS_VPRTYBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VREFP, PPC_INS_VREFP, + {PPC_VREFP, PPC_INS_VREFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VRFIM, PPC_INS_VRFIM, + {PPC_VRFIM, PPC_INS_VRFIM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VRFIN, PPC_INS_VRFIN, + {PPC_VRFIN, PPC_INS_VRFIN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VRFIP, PPC_INS_VRFIP, + {PPC_VRFIP, PPC_INS_VRFIP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VRFIZ, PPC_INS_VRFIZ, + {PPC_VRFIZ, PPC_INS_VRFIZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VRLB, PPC_INS_VRLB, + {PPC_VRLB, PPC_INS_VRLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VRLD, PPC_INS_VRLD, + {PPC_VRLD, PPC_INS_VRLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VRLDMI, PPC_INS_VRLDMI, + {PPC_VRLDMI, PPC_INS_VRLDMI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_VRLDNM, PPC_INS_VRLDNM, + {PPC_VRLDNM, PPC_INS_VRLDNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_VRLH, PPC_INS_VRLH, + {PPC_VRLH, PPC_INS_VRLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VRLW, PPC_INS_VRLW, + {PPC_VRLW, PPC_INS_VRLW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VRLWMI, PPC_INS_VRLWMI, + {PPC_VRLWMI, PPC_INS_VRLWMI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_VRLWNM, PPC_INS_VRLWNM, + {PPC_VRLWNM, PPC_INS_VRLWNM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_VRSQRTEFP, PPC_INS_VRSQRTEFP, + {PPC_VRSQRTEFP, + PPC_INS_VRSQRTEFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSBOX, PPC_INS_VSBOX, + {PPC_VSBOX, PPC_INS_VSBOX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VSEL, PPC_INS_VSEL, + {PPC_VSEL, PPC_INS_VSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSHASIGMAD, PPC_INS_VSHASIGMAD, + {PPC_VSHASIGMAD, + PPC_INS_VSHASIGMAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSHASIGMAW, PPC_INS_VSHASIGMAW, + {PPC_VSHASIGMAW, + PPC_INS_VSHASIGMAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSL, PPC_INS_VSL, + {PPC_VSL, PPC_INS_VSL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSLB, PPC_INS_VSLB, + {PPC_VSLB, PPC_INS_VSLB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSLD, PPC_INS_VSLD, + {PPC_VSLD, PPC_INS_VSLD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSLDOI, PPC_INS_VSLDOI, + {PPC_VSLDOI, + PPC_INS_VSLDOI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSLH, PPC_INS_VSLH, + {PPC_VSLH, PPC_INS_VSLH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSLO, PPC_INS_VSLO, + {PPC_VSLO, PPC_INS_VSLO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSLV, PPC_INS_VSLV, + {PPC_VSLV, PPC_INS_VSLV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VSLW, PPC_INS_VSLW, + {PPC_VSLW, PPC_INS_VSLW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSPLTB, PPC_INS_VSPLTB, + {PPC_VSPLTB, + PPC_INS_VSPLTB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSPLTH, PPC_INS_VSPLTH, + {PPC_VSPLTH, + PPC_INS_VSPLTH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSPLTISB, PPC_INS_VSPLTISB, + {PPC_VSPLTISB, + PPC_INS_VSPLTISB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSPLTISH, PPC_INS_VSPLTISH, + {PPC_VSPLTISH, + PPC_INS_VSPLTISH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSPLTISW, PPC_INS_VSPLTISW, + {PPC_VSPLTISW, + PPC_INS_VSPLTISW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSPLTW, PPC_INS_VSPLTW, + {PPC_VSPLTW, + PPC_INS_VSPLTW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSR, PPC_INS_VSR, + {PPC_VSR, PPC_INS_VSR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRAB, PPC_INS_VSRAB, + {PPC_VSRAB, PPC_INS_VSRAB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRAD, PPC_INS_VSRAD, + {PPC_VSRAD, PPC_INS_VSRAD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRAH, PPC_INS_VSRAH, + {PPC_VSRAH, PPC_INS_VSRAH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRAW, PPC_INS_VSRAW, + {PPC_VSRAW, PPC_INS_VSRAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRB, PPC_INS_VSRB, + {PPC_VSRB, PPC_INS_VSRB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRD, PPC_INS_VSRD, + {PPC_VSRD, PPC_INS_VSRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_P8ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRH, PPC_INS_VSRH, + {PPC_VSRH, PPC_INS_VSRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRO, PPC_INS_VSRO, + {PPC_VSRO, PPC_INS_VSRO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRV, PPC_INS_VSRV, + {PPC_VSRV, PPC_INS_VSRV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_VSRW, PPC_INS_VSRW, + {PPC_VSRW, PPC_INS_VSRW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_VSUBCUQ, PPC_INS_VSUBCUQ, + {PPC_VSUBCUQ, + PPC_INS_VSUBCUQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBCUW, PPC_INS_VSUBCUW, + {PPC_VSUBCUW, + PPC_INS_VSUBCUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBECUQ, PPC_INS_VSUBECUQ, + {PPC_VSUBECUQ, + PPC_INS_VSUBECUQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBEUQM, PPC_INS_VSUBEUQM, + {PPC_VSUBEUQM, + PPC_INS_VSUBEUQM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBFP, PPC_INS_VSUBFP, + {PPC_VSUBFP, + PPC_INS_VSUBFP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBSBS, PPC_INS_VSUBSBS, + {PPC_VSUBSBS, + PPC_INS_VSUBSBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBSHS, PPC_INS_VSUBSHS, + {PPC_VSUBSHS, + PPC_INS_VSUBSHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBSWS, PPC_INS_VSUBSWS, + {PPC_VSUBSWS, + PPC_INS_VSUBSWS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBUBM, PPC_INS_VSUBUBM, + {PPC_VSUBUBM, + PPC_INS_VSUBUBM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBUBS, PPC_INS_VSUBUBS, + {PPC_VSUBUBS, + PPC_INS_VSUBUBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBUDM, PPC_INS_VSUBUDM, + {PPC_VSUBUDM, + PPC_INS_VSUBUDM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBUHM, PPC_INS_VSUBUHM, + {PPC_VSUBUHM, + PPC_INS_VSUBUHM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBUHS, PPC_INS_VSUBUHS, + {PPC_VSUBUHS, + PPC_INS_VSUBUHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBUQM, PPC_INS_VSUBUQM, + {PPC_VSUBUQM, + PPC_INS_VSUBUQM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBUWM, PPC_INS_VSUBUWM, + {PPC_VSUBUWM, + PPC_INS_VSUBUWM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUBUWS, PPC_INS_VSUBUWS, + {PPC_VSUBUWS, + PPC_INS_VSUBUWS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUM2SWS, PPC_INS_VSUM2SWS, + {PPC_VSUM2SWS, + PPC_INS_VSUM2SWS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUM4SBS, PPC_INS_VSUM4SBS, + {PPC_VSUM4SBS, + PPC_INS_VSUM4SBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUM4SHS, PPC_INS_VSUM4SHS, + {PPC_VSUM4SHS, + PPC_INS_VSUM4SHS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUM4UBS, PPC_INS_VSUM4UBS, + {PPC_VSUM4UBS, + PPC_INS_VSUM4UBS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VSUMSWS, PPC_INS_VSUMSWS, + {PPC_VSUMSWS, + PPC_INS_VSUMSWS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VUPKHPX, PPC_INS_VUPKHPX, + {PPC_VUPKHPX, + PPC_INS_VUPKHPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VUPKHSB, PPC_INS_VUPKHSB, + {PPC_VUPKHSB, + PPC_INS_VUPKHSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VUPKHSH, PPC_INS_VUPKHSH, + {PPC_VUPKHSH, + PPC_INS_VUPKHSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VUPKHSW, PPC_INS_VUPKHSW, + {PPC_VUPKHSW, + PPC_INS_VUPKHSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VUPKLPX, PPC_INS_VUPKLPX, + {PPC_VUPKLPX, + PPC_INS_VUPKLPX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VUPKLSB, PPC_INS_VUPKLSB, + {PPC_VUPKLSB, + PPC_INS_VUPKLSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VUPKLSH, PPC_INS_VUPKLSH, + {PPC_VUPKLSH, + PPC_INS_VUPKLSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_VUPKLSW, PPC_INS_VUPKLSW, + {PPC_VUPKLSW, + PPC_INS_VUPKLSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_VXOR, PPC_INS_VXOR, + {PPC_VXOR, PPC_INS_VXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_V_SET0, PPC_INS_VXOR, + {PPC_V_SET0, PPC_INS_VXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_ALTIVEC, 0}, 0, + 0 #endif -}, + }, -{ - PPC_V_SET0B, PPC_INS_VXOR, + {PPC_V_SET0B, + PPC_INS_VXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_V_SET0H, PPC_INS_VXOR, + {PPC_V_SET0H, + PPC_INS_VXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_V_SETALLONES, PPC_INS_VSPLTISW, + {PPC_V_SETALLONES, + PPC_INS_VSPLTISW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_V_SETALLONESB, PPC_INS_VSPLTISW, + {PPC_V_SETALLONESB, + PPC_INS_VSPLTISW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_V_SETALLONESH, PPC_INS_VSPLTISW, + {PPC_V_SETALLONESH, + PPC_INS_VSPLTISW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_ALTIVEC, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_WAIT, PPC_INS_WAIT, + {PPC_WAIT, PPC_INS_WAIT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_WRTEE, PPC_INS_WRTEE, + {PPC_WRTEE, PPC_INS_WRTEE, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_BOOKE, 0}, 0, + 0 #endif -}, + }, -{ - PPC_WRTEEI, PPC_INS_WRTEEI, + {PPC_WRTEEI, + PPC_INS_WRTEEI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_BOOKE, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XOR, PPC_INS_XOR, + {PPC_XOR, PPC_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XOR8, PPC_INS_XOR, + {PPC_XOR8, PPC_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XOR8o, PPC_INS_XOR, + {PPC_XOR8_rec, + PPC_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XORI, PPC_INS_XORI, + {PPC_XORI, PPC_INS_XORI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XORI8, PPC_INS_XORI, + {PPC_XORI8, PPC_INS_XORI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XORIS, PPC_INS_XORIS, + {PPC_XORIS, PPC_INS_XORIS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XORIS8, PPC_INS_XORIS, + {PPC_XORIS8, PPC_INS_XORIS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XORo, PPC_INS_XOR, + {PPC_XOR_rec, + PPC_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 + {0}, + {PPC_REG_CR0, 0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSABSDP, PPC_INS_XSABSDP, + {PPC_XSABSDP, + PPC_INS_XSABSDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSABSQP, PPC_INS_XSABSQP, + {PPC_XSABSQP, + PPC_INS_XSABSQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSADDDP, PPC_INS_XSADDDP, + {PPC_XSADDDP, + PPC_INS_XSADDDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSADDQP, PPC_INS_XSADDQP, + {PPC_XSADDQP, + PPC_INS_XSADDQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSADDQPO, PPC_INS_XSADDQPO, + {PPC_XSADDQPO, + PPC_INS_XSADDQPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSADDSP, PPC_INS_XSADDSP, + {PPC_XSADDSP, + PPC_INS_XSADDSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCMPEQDP, PPC_INS_XSCMPEQDP, + {PPC_XSCMPEQDP, + PPC_INS_XSCMPEQDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCMPEXPDP, PPC_INS_XSCMPEXPDP, + {PPC_XSCMPEXPDP, + PPC_INS_XSCMPEXPDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCMPEXPQP, PPC_INS_XSCMPEXPQP, + {PPC_XSCMPEXPQP, + PPC_INS_XSCMPEXPQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCMPGEDP, PPC_INS_XSCMPGEDP, + {PPC_XSCMPGEDP, + PPC_INS_XSCMPGEDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCMPGTDP, PPC_INS_XSCMPGTDP, + {PPC_XSCMPGTDP, + PPC_INS_XSCMPGTDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCMPODP, PPC_INS_XSCMPODP, + {PPC_XSCMPODP, + PPC_INS_XSCMPODP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCMPOQP, PPC_INS_XSCMPOQP, + {PPC_XSCMPOQP, + PPC_INS_XSCMPOQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCMPUDP, PPC_INS_XSCMPUDP, + {PPC_XSCMPUDP, + PPC_INS_XSCMPUDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCMPUQP, PPC_INS_XSCMPUQP, + {PPC_XSCMPUQP, + PPC_INS_XSCMPUQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCPSGNDP, PPC_INS_XSCPSGNDP, + {PPC_XSCPSGNDP, + PPC_INS_XSCPSGNDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCPSGNQP, PPC_INS_XSCPSGNQP, + {PPC_XSCPSGNQP, + PPC_INS_XSCPSGNQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVDPHP, PPC_INS_XSCVDPHP, + {PPC_XSCVDPHP, + PPC_INS_XSCVDPHP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVDPQP, PPC_INS_XSCVDPQP, + {PPC_XSCVDPQP, + PPC_INS_XSCVDPQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVDPSP, PPC_INS_XSCVDPSP, + {PPC_XSCVDPSP, + PPC_INS_XSCVDPSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVDPSPN, PPC_INS_XSCVDPSPN, + {PPC_XSCVDPSPN, + PPC_INS_XSCVDPSPN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVDPSXDS, PPC_INS_XSCVDPSXDS, + {PPC_XSCVDPSXDS, + PPC_INS_XSCVDPSXDS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVDPSXWS, PPC_INS_XSCVDPSXWS, + {PPC_XSCVDPSXWS, + PPC_INS_XSCVDPSXWS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVDPUXDS, PPC_INS_XSCVDPUXDS, + {PPC_XSCVDPUXDS, + PPC_INS_XSCVDPUXDS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVDPUXWS, PPC_INS_XSCVDPUXWS, + {PPC_XSCVDPUXWS, + PPC_INS_XSCVDPUXWS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVHPDP, PPC_INS_XSCVHPDP, + {PPC_XSCVHPDP, + PPC_INS_XSCVHPDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVQPDP, PPC_INS_XSCVQPDP, + {PPC_XSCVQPDP, + PPC_INS_XSCVQPDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVQPDPO, PPC_INS_XSCVQPDPO, + {PPC_XSCVQPDPO, + PPC_INS_XSCVQPDPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVQPSDZ, PPC_INS_XSCVQPSDZ, + {PPC_XSCVQPSDZ, + PPC_INS_XSCVQPSDZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVQPSWZ, PPC_INS_XSCVQPSWZ, + {PPC_XSCVQPSWZ, + PPC_INS_XSCVQPSWZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVQPUDZ, PPC_INS_XSCVQPUDZ, + {PPC_XSCVQPUDZ, + PPC_INS_XSCVQPUDZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVQPUWZ, PPC_INS_XSCVQPUWZ, + {PPC_XSCVQPUWZ, + PPC_INS_XSCVQPUWZ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVSDQP, PPC_INS_XSCVSDQP, + {PPC_XSCVSDQP, + PPC_INS_XSCVSDQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVSPDP, PPC_INS_XSCVSPDP, + {PPC_XSCVSPDP, + PPC_INS_XSCVSPDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVSPDPN, PPC_INS_XSCVSPDPN, + {PPC_XSCVSPDPN, + PPC_INS_XSCVSPDPN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVSXDDP, PPC_INS_XSCVSXDDP, + {PPC_XSCVSXDDP, + PPC_INS_XSCVSXDDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVSXDSP, PPC_INS_XSCVSXDSP, + {PPC_XSCVSXDSP, + PPC_INS_XSCVSXDSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVUDQP, PPC_INS_XSCVUDQP, + {PPC_XSCVUDQP, + PPC_INS_XSCVUDQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVUXDDP, PPC_INS_XSCVUXDDP, + {PPC_XSCVUXDDP, + PPC_INS_XSCVUXDDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSCVUXDSP, PPC_INS_XSCVUXDSP, + {PPC_XSCVUXDSP, + PPC_INS_XSCVUXDSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSDIVDP, PPC_INS_XSDIVDP, + {PPC_XSDIVDP, + PPC_INS_XSDIVDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSDIVQP, PPC_INS_XSDIVQP, + {PPC_XSDIVQP, + PPC_INS_XSDIVQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSDIVQPO, PPC_INS_XSDIVQPO, + {PPC_XSDIVQPO, + PPC_INS_XSDIVQPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSDIVSP, PPC_INS_XSDIVSP, + {PPC_XSDIVSP, + PPC_INS_XSDIVSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSIEXPDP, PPC_INS_XSIEXPDP, + {PPC_XSIEXPDP, + PPC_INS_XSIEXPDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSIEXPQP, PPC_INS_XSIEXPQP, + {PPC_XSIEXPQP, + PPC_INS_XSIEXPQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMADDADP, PPC_INS_XSMADDADP, + {PPC_XSMADDADP, + PPC_INS_XSMADDADP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMADDASP, PPC_INS_XSMADDASP, + {PPC_XSMADDASP, + PPC_INS_XSMADDASP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMADDMDP, PPC_INS_XSMADDMDP, + {PPC_XSMADDMDP, + PPC_INS_XSMADDMDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMADDMSP, PPC_INS_XSMADDMSP, + {PPC_XSMADDMSP, + PPC_INS_XSMADDMSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMADDQP, PPC_INS_XSMADDQP, + {PPC_XSMADDQP, + PPC_INS_XSMADDQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMADDQPO, PPC_INS_XSMADDQPO, + {PPC_XSMADDQPO, + PPC_INS_XSMADDQPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMAXCDP, PPC_INS_XSMAXCDP, + {PPC_XSMAXCDP, + PPC_INS_XSMAXCDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMAXDP, PPC_INS_XSMAXDP, + {PPC_XSMAXDP, + PPC_INS_XSMAXDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMAXJDP, PPC_INS_XSMAXJDP, + {PPC_XSMAXJDP, + PPC_INS_XSMAXJDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMINCDP, PPC_INS_XSMINCDP, + {PPC_XSMINCDP, + PPC_INS_XSMINCDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMINDP, PPC_INS_XSMINDP, + {PPC_XSMINDP, + PPC_INS_XSMINDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMINJDP, PPC_INS_XSMINJDP, + {PPC_XSMINJDP, + PPC_INS_XSMINJDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMSUBADP, PPC_INS_XSMSUBADP, + {PPC_XSMSUBADP, + PPC_INS_XSMSUBADP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMSUBASP, PPC_INS_XSMSUBASP, + {PPC_XSMSUBASP, + PPC_INS_XSMSUBASP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMSUBMDP, PPC_INS_XSMSUBMDP, + {PPC_XSMSUBMDP, + PPC_INS_XSMSUBMDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMSUBMSP, PPC_INS_XSMSUBMSP, + {PPC_XSMSUBMSP, + PPC_INS_XSMSUBMSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMSUBQP, PPC_INS_XSMSUBQP, + {PPC_XSMSUBQP, + PPC_INS_XSMSUBQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMSUBQPO, PPC_INS_XSMSUBQPO, + {PPC_XSMSUBQPO, + PPC_INS_XSMSUBQPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMULDP, PPC_INS_XSMULDP, + {PPC_XSMULDP, + PPC_INS_XSMULDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMULQP, PPC_INS_XSMULQP, + {PPC_XSMULQP, + PPC_INS_XSMULQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMULQPO, PPC_INS_XSMULQPO, + {PPC_XSMULQPO, + PPC_INS_XSMULQPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSMULSP, PPC_INS_XSMULSP, + {PPC_XSMULSP, + PPC_INS_XSMULSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNABSDP, PPC_INS_XSNABSDP, + {PPC_XSNABSDP, + PPC_INS_XSNABSDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNABSQP, PPC_INS_XSNABSQP, + {PPC_XSNABSQP, + PPC_INS_XSNABSQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNEGDP, PPC_INS_XSNEGDP, + {PPC_XSNEGDP, + PPC_INS_XSNEGDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNEGQP, PPC_INS_XSNEGQP, + {PPC_XSNEGQP, + PPC_INS_XSNEGQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMADDADP, PPC_INS_XSNMADDADP, + {PPC_XSNMADDADP, + PPC_INS_XSNMADDADP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMADDASP, PPC_INS_XSNMADDASP, + {PPC_XSNMADDASP, + PPC_INS_XSNMADDASP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMADDMDP, PPC_INS_XSNMADDMDP, + {PPC_XSNMADDMDP, + PPC_INS_XSNMADDMDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMADDMSP, PPC_INS_XSNMADDMSP, + {PPC_XSNMADDMSP, + PPC_INS_XSNMADDMSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMADDQP, PPC_INS_XSNMADDQP, + {PPC_XSNMADDQP, + PPC_INS_XSNMADDQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMADDQPO, PPC_INS_XSNMADDQPO, + {PPC_XSNMADDQPO, + PPC_INS_XSNMADDQPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMSUBADP, PPC_INS_XSNMSUBADP, + {PPC_XSNMSUBADP, + PPC_INS_XSNMSUBADP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMSUBASP, PPC_INS_XSNMSUBASP, + {PPC_XSNMSUBASP, + PPC_INS_XSNMSUBASP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMSUBMDP, PPC_INS_XSNMSUBMDP, + {PPC_XSNMSUBMDP, + PPC_INS_XSNMSUBMDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMSUBMSP, PPC_INS_XSNMSUBMSP, + {PPC_XSNMSUBMSP, + PPC_INS_XSNMSUBMSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMSUBQP, PPC_INS_XSNMSUBQP, + {PPC_XSNMSUBQP, + PPC_INS_XSNMSUBQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSNMSUBQPO, PPC_INS_XSNMSUBQPO, + {PPC_XSNMSUBQPO, + PPC_INS_XSNMSUBQPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSRDPI, PPC_INS_XSRDPI, + {PPC_XSRDPI, + PPC_INS_XSRDPI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSRDPIC, PPC_INS_XSRDPIC, + {PPC_XSRDPIC, + PPC_INS_XSRDPIC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSRDPIM, PPC_INS_XSRDPIM, + {PPC_XSRDPIM, + PPC_INS_XSRDPIM, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSRDPIP, PPC_INS_XSRDPIP, + {PPC_XSRDPIP, + PPC_INS_XSRDPIP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSRDPIZ, PPC_INS_XSRDPIZ, + {PPC_XSRDPIZ, + PPC_INS_XSRDPIZ, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSREDP, PPC_INS_XSREDP, + {PPC_XSREDP, + PPC_INS_XSREDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSRESP, PPC_INS_XSRESP, + {PPC_XSRESP, PPC_INS_XSRESP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_XSRQPI, PPC_INS_XSRQPI, + {PPC_XSRQPI, PPC_INS_XSRQPI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_XSRQPIX, PPC_INS_XSRQPIX, + {PPC_XSRQPIX, + PPC_INS_XSRQPIX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSRQPXP, PPC_INS_XSRQPXP, + {PPC_XSRQPXP, + PPC_INS_XSRQPXP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSRSP, PPC_INS_XSRSP, + {PPC_XSRSP, PPC_INS_XSRSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XSRSQRTEDP, PPC_INS_XSRSQRTEDP, + {PPC_XSRSQRTEDP, + PPC_INS_XSRSQRTEDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSRSQRTESP, PPC_INS_XSRSQRTESP, + {PPC_XSRSQRTESP, + PPC_INS_XSRSQRTESP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSSQRTDP, PPC_INS_XSSQRTDP, + {PPC_XSSQRTDP, + PPC_INS_XSSQRTDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSSQRTQP, PPC_INS_XSSQRTQP, + {PPC_XSSQRTQP, + PPC_INS_XSSQRTQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSSQRTQPO, PPC_INS_XSSQRTQPO, + {PPC_XSSQRTQPO, + PPC_INS_XSSQRTQPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSSQRTSP, PPC_INS_XSSQRTSP, + {PPC_XSSQRTSP, + PPC_INS_XSSQRTSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSSUBDP, PPC_INS_XSSUBDP, + {PPC_XSSUBDP, + PPC_INS_XSSUBDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSSUBQP, PPC_INS_XSSUBQP, + {PPC_XSSUBQP, + PPC_INS_XSSUBQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSSUBQPO, PPC_INS_XSSUBQPO, + {PPC_XSSUBQPO, + PPC_INS_XSSUBQPO, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSSUBSP, PPC_INS_XSSUBSP, + {PPC_XSSUBSP, + PPC_INS_XSSUBSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSTDIVDP, PPC_INS_XSTDIVDP, + {PPC_XSTDIVDP, + PPC_INS_XSTDIVDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSTSQRTDP, PPC_INS_XSTSQRTDP, + {PPC_XSTSQRTDP, + PPC_INS_XSTSQRTDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSTSTDCDP, PPC_INS_XSTSTDCDP, + {PPC_XSTSTDCDP, + PPC_INS_XSTSTDCDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSTSTDCQP, PPC_INS_XSTSTDCQP, + {PPC_XSTSTDCQP, + PPC_INS_XSTSTDCQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSTSTDCSP, PPC_INS_XSTSTDCSP, + {PPC_XSTSTDCSP, + PPC_INS_XSTSTDCSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSXEXPDP, PPC_INS_XSXEXPDP, + {PPC_XSXEXPDP, + PPC_INS_XSXEXPDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSXEXPQP, PPC_INS_XSXEXPQP, + {PPC_XSXEXPQP, + PPC_INS_XSXEXPQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSXSIGDP, PPC_INS_XSXSIGDP, + {PPC_XSXSIGDP, + PPC_INS_XSXSIGDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XSXSIGQP, PPC_INS_XSXSIGQP, + {PPC_XSXSIGQP, + PPC_INS_XSXSIGQP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVABSDP, PPC_INS_XVABSDP, + {PPC_XVABSDP, + PPC_INS_XVABSDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVABSSP, PPC_INS_XVABSSP, + {PPC_XVABSSP, + PPC_INS_XVABSSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVADDDP, PPC_INS_XVADDDP, + {PPC_XVADDDP, + PPC_INS_XVADDDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVADDSP, PPC_INS_XVADDSP, + {PPC_XVADDSP, + PPC_INS_XVADDSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPEQDP, PPC_INS_XVCMPEQDP, + {PPC_XVCMPEQDP, + PPC_INS_XVCMPEQDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPEQDPo, PPC_INS_XVCMPEQDP, + {PPC_XVCMPEQDP_rec, + PPC_INS_XVCMPEQDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPEQSP, PPC_INS_XVCMPEQSP, + {PPC_XVCMPEQSP, + PPC_INS_XVCMPEQSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPEQSPo, PPC_INS_XVCMPEQSP, + {PPC_XVCMPEQSP_rec, + PPC_INS_XVCMPEQSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPGEDP, PPC_INS_XVCMPGEDP, + {PPC_XVCMPGEDP, + PPC_INS_XVCMPGEDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPGEDPo, PPC_INS_XVCMPGEDP, + {PPC_XVCMPGEDP_rec, + PPC_INS_XVCMPGEDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPGESP, PPC_INS_XVCMPGESP, + {PPC_XVCMPGESP, + PPC_INS_XVCMPGESP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPGESPo, PPC_INS_XVCMPGESP, + {PPC_XVCMPGESP_rec, + PPC_INS_XVCMPGESP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPGTDP, PPC_INS_XVCMPGTDP, + {PPC_XVCMPGTDP, + PPC_INS_XVCMPGTDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPGTDPo, PPC_INS_XVCMPGTDP, + {PPC_XVCMPGTDP_rec, + PPC_INS_XVCMPGTDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPGTSP, PPC_INS_XVCMPGTSP, + {PPC_XVCMPGTSP, + PPC_INS_XVCMPGTSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCMPGTSPo, PPC_INS_XVCMPGTSP, + {PPC_XVCMPGTSP_rec, + PPC_INS_XVCMPGTSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {PPC_REG_CR6, 0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCPSGNDP, PPC_INS_XVCPSGNDP, + {PPC_XVCPSGNDP, + PPC_INS_XVCPSGNDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCPSGNSP, PPC_INS_XVCPSGNSP, + {PPC_XVCPSGNSP, + PPC_INS_XVCPSGNSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVDPSP, PPC_INS_XVCVDPSP, + {PPC_XVCVDPSP, + PPC_INS_XVCVDPSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVDPSXDS, PPC_INS_XVCVDPSXDS, + {PPC_XVCVDPSXDS, + PPC_INS_XVCVDPSXDS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVDPSXWS, PPC_INS_XVCVDPSXWS, + {PPC_XVCVDPSXWS, + PPC_INS_XVCVDPSXWS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVDPUXDS, PPC_INS_XVCVDPUXDS, + {PPC_XVCVDPUXDS, + PPC_INS_XVCVDPUXDS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVDPUXWS, PPC_INS_XVCVDPUXWS, + {PPC_XVCVDPUXWS, + PPC_INS_XVCVDPUXWS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVHPSP, PPC_INS_XVCVHPSP, + {PPC_XVCVHPSP, + PPC_INS_XVCVHPSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSPDP, PPC_INS_XVCVSPDP, + {PPC_XVCVSPDP, + PPC_INS_XVCVSPDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSPHP, PPC_INS_XVCVSPHP, + {PPC_XVCVSPHP, + PPC_INS_XVCVSPHP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSPSXDS, PPC_INS_XVCVSPSXDS, + {PPC_XVCVSPSXDS, + PPC_INS_XVCVSPSXDS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSPSXWS, PPC_INS_XVCVSPSXWS, + {PPC_XVCVSPSXWS, + PPC_INS_XVCVSPSXWS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSPUXDS, PPC_INS_XVCVSPUXDS, + {PPC_XVCVSPUXDS, + PPC_INS_XVCVSPUXDS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSPUXWS, PPC_INS_XVCVSPUXWS, + {PPC_XVCVSPUXWS, + PPC_INS_XVCVSPUXWS, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSXDDP, PPC_INS_XVCVSXDDP, + {PPC_XVCVSXDDP, + PPC_INS_XVCVSXDDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSXDSP, PPC_INS_XVCVSXDSP, + {PPC_XVCVSXDSP, + PPC_INS_XVCVSXDSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSXWDP, PPC_INS_XVCVSXWDP, + {PPC_XVCVSXWDP, + PPC_INS_XVCVSXWDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVSXWSP, PPC_INS_XVCVSXWSP, + {PPC_XVCVSXWSP, + PPC_INS_XVCVSXWSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVUXDDP, PPC_INS_XVCVUXDDP, + {PPC_XVCVUXDDP, + PPC_INS_XVCVUXDDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVUXDSP, PPC_INS_XVCVUXDSP, + {PPC_XVCVUXDSP, + PPC_INS_XVCVUXDSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVUXWDP, PPC_INS_XVCVUXWDP, + {PPC_XVCVUXWDP, + PPC_INS_XVCVUXWDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVCVUXWSP, PPC_INS_XVCVUXWSP, + {PPC_XVCVUXWSP, + PPC_INS_XVCVUXWSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVDIVDP, PPC_INS_XVDIVDP, + {PPC_XVDIVDP, + PPC_INS_XVDIVDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVDIVSP, PPC_INS_XVDIVSP, + {PPC_XVDIVSP, + PPC_INS_XVDIVSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVIEXPDP, PPC_INS_XVIEXPDP, + {PPC_XVIEXPDP, + PPC_INS_XVIEXPDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVIEXPSP, PPC_INS_XVIEXPSP, + {PPC_XVIEXPSP, + PPC_INS_XVIEXPSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMADDADP, PPC_INS_XVMADDADP, + {PPC_XVMADDADP, + PPC_INS_XVMADDADP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMADDASP, PPC_INS_XVMADDASP, + {PPC_XVMADDASP, + PPC_INS_XVMADDASP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMADDMDP, PPC_INS_XVMADDMDP, + {PPC_XVMADDMDP, + PPC_INS_XVMADDMDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMADDMSP, PPC_INS_XVMADDMSP, + {PPC_XVMADDMSP, + PPC_INS_XVMADDMSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMAXDP, PPC_INS_XVMAXDP, + {PPC_XVMAXDP, + PPC_INS_XVMAXDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMAXSP, PPC_INS_XVMAXSP, + {PPC_XVMAXSP, + PPC_INS_XVMAXSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMINDP, PPC_INS_XVMINDP, + {PPC_XVMINDP, + PPC_INS_XVMINDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMINSP, PPC_INS_XVMINSP, + {PPC_XVMINSP, + PPC_INS_XVMINSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMSUBADP, PPC_INS_XVMSUBADP, + {PPC_XVMSUBADP, + PPC_INS_XVMSUBADP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMSUBASP, PPC_INS_XVMSUBASP, + {PPC_XVMSUBASP, + PPC_INS_XVMSUBASP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMSUBMDP, PPC_INS_XVMSUBMDP, + {PPC_XVMSUBMDP, + PPC_INS_XVMSUBMDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMSUBMSP, PPC_INS_XVMSUBMSP, + {PPC_XVMSUBMSP, + PPC_INS_XVMSUBMSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMULDP, PPC_INS_XVMULDP, + {PPC_XVMULDP, + PPC_INS_XVMULDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVMULSP, PPC_INS_XVMULSP, + {PPC_XVMULSP, + PPC_INS_XVMULSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNABSDP, PPC_INS_XVNABSDP, + {PPC_XVNABSDP, + PPC_INS_XVNABSDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNABSSP, PPC_INS_XVNABSSP, + {PPC_XVNABSSP, + PPC_INS_XVNABSSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNEGDP, PPC_INS_XVNEGDP, + {PPC_XVNEGDP, + PPC_INS_XVNEGDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNEGSP, PPC_INS_XVNEGSP, + {PPC_XVNEGSP, + PPC_INS_XVNEGSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNMADDADP, PPC_INS_XVNMADDADP, + {PPC_XVNMADDADP, + PPC_INS_XVNMADDADP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNMADDASP, PPC_INS_XVNMADDASP, + {PPC_XVNMADDASP, + PPC_INS_XVNMADDASP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNMADDMDP, PPC_INS_XVNMADDMDP, + {PPC_XVNMADDMDP, + PPC_INS_XVNMADDMDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNMADDMSP, PPC_INS_XVNMADDMSP, + {PPC_XVNMADDMSP, + PPC_INS_XVNMADDMSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNMSUBADP, PPC_INS_XVNMSUBADP, + {PPC_XVNMSUBADP, + PPC_INS_XVNMSUBADP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNMSUBASP, PPC_INS_XVNMSUBASP, + {PPC_XVNMSUBASP, + PPC_INS_XVNMSUBASP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNMSUBMDP, PPC_INS_XVNMSUBMDP, + {PPC_XVNMSUBMDP, + PPC_INS_XVNMSUBMDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVNMSUBMSP, PPC_INS_XVNMSUBMSP, + {PPC_XVNMSUBMSP, + PPC_INS_XVNMSUBMSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRDPI, PPC_INS_XVRDPI, + {PPC_XVRDPI, + PPC_INS_XVRDPI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRDPIC, PPC_INS_XVRDPIC, + {PPC_XVRDPIC, + PPC_INS_XVRDPIC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRDPIM, PPC_INS_XVRDPIM, + {PPC_XVRDPIM, + PPC_INS_XVRDPIM, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRDPIP, PPC_INS_XVRDPIP, + {PPC_XVRDPIP, + PPC_INS_XVRDPIP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRDPIZ, PPC_INS_XVRDPIZ, + {PPC_XVRDPIZ, + PPC_INS_XVRDPIZ, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVREDP, PPC_INS_XVREDP, + {PPC_XVREDP, + PPC_INS_XVREDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRESP, PPC_INS_XVRESP, + {PPC_XVRESP, + PPC_INS_XVRESP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRSPI, PPC_INS_XVRSPI, + {PPC_XVRSPI, + PPC_INS_XVRSPI, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRSPIC, PPC_INS_XVRSPIC, + {PPC_XVRSPIC, + PPC_INS_XVRSPIC, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRSPIM, PPC_INS_XVRSPIM, + {PPC_XVRSPIM, + PPC_INS_XVRSPIM, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRSPIP, PPC_INS_XVRSPIP, + {PPC_XVRSPIP, + PPC_INS_XVRSPIP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRSPIZ, PPC_INS_XVRSPIZ, + {PPC_XVRSPIZ, + PPC_INS_XVRSPIZ, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRSQRTEDP, PPC_INS_XVRSQRTEDP, + {PPC_XVRSQRTEDP, + PPC_INS_XVRSQRTEDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVRSQRTESP, PPC_INS_XVRSQRTESP, + {PPC_XVRSQRTESP, + PPC_INS_XVRSQRTESP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVSQRTDP, PPC_INS_XVSQRTDP, + {PPC_XVSQRTDP, + PPC_INS_XVSQRTDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVSQRTSP, PPC_INS_XVSQRTSP, + {PPC_XVSQRTSP, + PPC_INS_XVSQRTSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVSUBDP, PPC_INS_XVSUBDP, + {PPC_XVSUBDP, + PPC_INS_XVSUBDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVSUBSP, PPC_INS_XVSUBSP, + {PPC_XVSUBSP, + PPC_INS_XVSUBSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVTDIVDP, PPC_INS_XVTDIVDP, + {PPC_XVTDIVDP, + PPC_INS_XVTDIVDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVTDIVSP, PPC_INS_XVTDIVSP, + {PPC_XVTDIVSP, + PPC_INS_XVTDIVSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVTSQRTDP, PPC_INS_XVTSQRTDP, + {PPC_XVTSQRTDP, + PPC_INS_XVTSQRTDP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVTSQRTSP, PPC_INS_XVTSQRTSP, + {PPC_XVTSQRTSP, + PPC_INS_XVTSQRTSP, #ifndef CAPSTONE_DIET - { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {PPC_REG_RM, 0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVTSTDCDP, PPC_INS_XVTSTDCDP, + {PPC_XVTSTDCDP, + PPC_INS_XVTSTDCDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVTSTDCSP, PPC_INS_XVTSTDCSP, + {PPC_XVTSTDCSP, + PPC_INS_XVTSTDCSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVXEXPDP, PPC_INS_XVXEXPDP, + {PPC_XVXEXPDP, + PPC_INS_XVXEXPDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVXEXPSP, PPC_INS_XVXEXPSP, + {PPC_XVXEXPSP, + PPC_INS_XVXEXPSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVXSIGDP, PPC_INS_XVXSIGDP, + {PPC_XVXSIGDP, + PPC_INS_XVXSIGDP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XVXSIGSP, PPC_INS_XVXSIGSP, + {PPC_XVXSIGSP, + PPC_INS_XVXSIGSP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXBRD, PPC_INS_XXBRD, + {PPC_XXBRD, PPC_INS_XXBRD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XXBRH, PPC_INS_XXBRH, + {PPC_XXBRH, PPC_INS_XXBRH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XXBRQ, PPC_INS_XXBRQ, + {PPC_XXBRQ, PPC_INS_XXBRQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XXBRW, PPC_INS_XXBRW, + {PPC_XXBRW, PPC_INS_XXBRW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, -{ - PPC_XXEXTRACTUW, PPC_INS_XXEXTRACTUW, + {PPC_XXEXTRACTUW, + PPC_INS_XXEXTRACTUW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXINSERTW, PPC_INS_XXINSERTW, + {PPC_XXINSERTW, + PPC_INS_XXINSERTW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXLAND, PPC_INS_XXLAND, + {PPC_XXLAND, + PPC_INS_XXLAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXLANDC, PPC_INS_XXLANDC, + {PPC_XXLANDC, + PPC_INS_XXLANDC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXLEQV, PPC_INS_XXLEQV, + {PPC_XXLEQV, + PPC_INS_XXLEQV, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8VECTOR, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8VECTOR, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXLNAND, PPC_INS_XXLNAND, + {PPC_XXLNAND, + PPC_INS_XXLNAND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8VECTOR, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8VECTOR, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXLNOR, PPC_INS_XXLNOR, + {PPC_XXLNOR, + PPC_INS_XXLNOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXLOR, PPC_INS_XXLOR, + {PPC_XXLOR, PPC_INS_XXLOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_VSX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_XXLORC, PPC_INS_XXLORC, + {PPC_XXLORC, + PPC_INS_XXLORC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_P8VECTOR, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_P8VECTOR, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXLORf, PPC_INS_XXLOR, + {PPC_XXLORf, PPC_INS_XXLOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_VSX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_XXLXOR, PPC_INS_XXLXOR, + {PPC_XXLXOR, + PPC_INS_XXLXOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXMRGHW, PPC_INS_XXMRGHW, + {PPC_XXMRGHW, + PPC_INS_XXMRGHW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXMRGLW, PPC_INS_XXMRGLW, + {PPC_XXMRGLW, + PPC_INS_XXMRGLW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXPERM, PPC_INS_XXPERM, + {PPC_XXPERM, PPC_INS_XXPERM, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, -{ - PPC_XXPERMDI, PPC_INS_XXMRGHD, + {PPC_XXPERMDI, + PPC_INS_XXMRGHD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXPERMDIs, PPC_INS_XXSPLTD, + {PPC_XXPERMDIs, + PPC_INS_XXSPLTD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXPERMR, PPC_INS_XXPERMR, + {PPC_XXPERMR, + PPC_INS_XXPERMR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXSEL, PPC_INS_XXSEL, + {PPC_XXSEL, PPC_INS_XXSEL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, {0}, {PPC_GRP_VSX, 0}, 0, + 0 #endif -}, + }, -{ - PPC_XXSLDWI, PPC_INS_XXSLDWI, + {PPC_XXSLDWI, + PPC_INS_XXSLDWI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXSPLTIB, PPC_INS_XXSPLTIB, + {PPC_XXSPLTIB, + PPC_INS_XXSPLTIB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, + }, -{ - PPC_XXSPLTW, PPC_INS_XXSPLTW, + {PPC_XXSPLTW, + PPC_INS_XXSPLTW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 + {0}, + {0}, + {PPC_GRP_VSX, 0}, + 0, + 0 #endif -}, + }, -{ - PPC_gBC, PPC_INS_BC, + {PPC_gBC, + PPC_INS_BC, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_gBCA, PPC_INS_BCA, + {PPC_gBCA, + PPC_INS_BCA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_gBCAat, PPC_INS_BCA, + {PPC_gBCAat, PPC_INS_BCA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {0}, {0}, {0}, 1, + 0 #endif -}, + }, -{ - PPC_gBCCTR, PPC_INS_BCCTR, + {PPC_gBCCTR, + PPC_INS_BCCTR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_gBCCTRL, PPC_INS_BCCTRL, + {PPC_gBCCTRL, + PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_LR, PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_gBCL, PPC_INS_BCL, + {PPC_gBCL, + PPC_INS_BCL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_LR, PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_gBCLA, PPC_INS_BCLA, + {PPC_gBCLA, + PPC_INS_BCLA, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_RM, 0}, + {PPC_REG_LR, PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_gBCLAat, PPC_INS_BCLA, + {PPC_gBCLAat, + PPC_INS_BCLA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {0}, + {0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_gBCLR, PPC_INS_BCLR, + {PPC_gBCLR, + PPC_INS_BCLR, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_gBCLRL, PPC_INS_BCLRL, + {PPC_gBCLRL, + PPC_INS_BCLRL, #ifndef CAPSTONE_DIET - { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 1, 0 + {PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0}, + {PPC_REG_LR, PPC_REG_CTR, 0}, + {0}, + 1, + 0 #endif -}, + }, -{ - PPC_gBCLat, PPC_INS_BCL, + {PPC_gBCLat, PPC_INS_BCL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {0}, {0}, {0}, 1, + 0 #endif -}, + }, -{ - PPC_gBCat, PPC_INS_BC, + {PPC_gBCat, PPC_INS_BC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 + {0}, {0}, {0}, + 1, 0 #endif -}, + }, diff --git a/arch/PowerPC/PPCMappingInsnName.inc b/arch/PowerPC/PPCMappingInsnName.inc index 732b8ca363..06bb7c42e4 100644 --- a/arch/PowerPC/PPCMappingInsnName.inc +++ b/arch/PowerPC/PPCMappingInsnName.inc @@ -1,1692 +1,1693 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* This is auto-gen data for Capstone disassembly engine + * (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ - "add", // PPC_INS_ADD, - "addc", // PPC_INS_ADDC, - "adde", // PPC_INS_ADDE, - "addi", // PPC_INS_ADDI, - "addic", // PPC_INS_ADDIC, - "addis", // PPC_INS_ADDIS, - "addme", // PPC_INS_ADDME, - "addpcis", // PPC_INS_ADDPCIS, - "addze", // PPC_INS_ADDZE, - "and", // PPC_INS_AND, - "andc", // PPC_INS_ANDC, - "andi", // PPC_INS_ANDI, - "andis", // PPC_INS_ANDIS, - "attn", // PPC_INS_ATTN, - "b", // PPC_INS_B, - "ba", // PPC_INS_BA, - "bc", // PPC_INS_BC, - "bca", // PPC_INS_BCA, - "bcctr", // PPC_INS_BCCTR, - "bcctrl", // PPC_INS_BCCTRL, - "bcdcfn", // PPC_INS_BCDCFN, - "bcdcfsq", // PPC_INS_BCDCFSQ, - "bcdcfz", // PPC_INS_BCDCFZ, - "bcdcpsgn", // PPC_INS_BCDCPSGN, - "bcdctn", // PPC_INS_BCDCTN, - "bcdctsq", // PPC_INS_BCDCTSQ, - "bcdctz", // PPC_INS_BCDCTZ, - "bcds", // PPC_INS_BCDS, - "bcdsetsgn", // PPC_INS_BCDSETSGN, - "bcdsr", // PPC_INS_BCDSR, - "bcdtrunc", // PPC_INS_BCDTRUNC, - "bcdus", // PPC_INS_BCDUS, - "bcdutrunc", // PPC_INS_BCDUTRUNC, - "bcl", // PPC_INS_BCL, - "bcla", // PPC_INS_BCLA, - "bclr", // PPC_INS_BCLR, - "bclrl", // PPC_INS_BCLRL, - "bctr", // PPC_INS_BCTR, - "bctrl", // PPC_INS_BCTRL, - "bdnz", // PPC_INS_BDNZ, - "bdnza", // PPC_INS_BDNZA, - "bdnzf", // PPC_INS_BDNZF, - "bdnzfa", // PPC_INS_BDNZFA, - "bdnzfl", // PPC_INS_BDNZFL, - "bdnzfla", // PPC_INS_BDNZFLA, - "bdnzflr", // PPC_INS_BDNZFLR, - "bdnzflrl", // PPC_INS_BDNZFLRL, - "bdnzl", // PPC_INS_BDNZL, - "bdnzla", // PPC_INS_BDNZLA, - "bdnzlr", // PPC_INS_BDNZLR, - "bdnzlrl", // PPC_INS_BDNZLRL, - "bdnzt", // PPC_INS_BDNZT, - "bdnzta", // PPC_INS_BDNZTA, - "bdnztl", // PPC_INS_BDNZTL, - "bdnztla", // PPC_INS_BDNZTLA, - "bdnztlr", // PPC_INS_BDNZTLR, - "bdnztlrl", // PPC_INS_BDNZTLRL, - "bdz", // PPC_INS_BDZ, - "bdza", // PPC_INS_BDZA, - "bdzf", // PPC_INS_BDZF, - "bdzfa", // PPC_INS_BDZFA, - "bdzfl", // PPC_INS_BDZFL, - "bdzfla", // PPC_INS_BDZFLA, - "bdzflr", // PPC_INS_BDZFLR, - "bdzflrl", // PPC_INS_BDZFLRL, - "bdzl", // PPC_INS_BDZL, - "bdzla", // PPC_INS_BDZLA, - "bdzlr", // PPC_INS_BDZLR, - "bdzlrl", // PPC_INS_BDZLRL, - "bdzt", // PPC_INS_BDZT, - "bdzta", // PPC_INS_BDZTA, - "bdztl", // PPC_INS_BDZTL, - "bdztla", // PPC_INS_BDZTLA, - "bdztlr", // PPC_INS_BDZTLR, - "bdztlrl", // PPC_INS_BDZTLRL, - "beq", // PPC_INS_BEQ, - "beqa", // PPC_INS_BEQA, - "beqctr", // PPC_INS_BEQCTR, - "beqctrl", // PPC_INS_BEQCTRL, - "beql", // PPC_INS_BEQL, - "beqla", // PPC_INS_BEQLA, - "beqlr", // PPC_INS_BEQLR, - "beqlrl", // PPC_INS_BEQLRL, - "bf", // PPC_INS_BF, - "bfa", // PPC_INS_BFA, - "bfctr", // PPC_INS_BFCTR, - "bfctrl", // PPC_INS_BFCTRL, - "bfl", // PPC_INS_BFL, - "bfla", // PPC_INS_BFLA, - "bflr", // PPC_INS_BFLR, - "bflrl", // PPC_INS_BFLRL, - "bge", // PPC_INS_BGE, - "bgea", // PPC_INS_BGEA, - "bgectr", // PPC_INS_BGECTR, - "bgectrl", // PPC_INS_BGECTRL, - "bgel", // PPC_INS_BGEL, - "bgela", // PPC_INS_BGELA, - "bgelr", // PPC_INS_BGELR, - "bgelrl", // PPC_INS_BGELRL, - "bgt", // PPC_INS_BGT, - "bgta", // PPC_INS_BGTA, - "bgtctr", // PPC_INS_BGTCTR, - "bgtctrl", // PPC_INS_BGTCTRL, - "bgtl", // PPC_INS_BGTL, - "bgtla", // PPC_INS_BGTLA, - "bgtlr", // PPC_INS_BGTLR, - "bgtlrl", // PPC_INS_BGTLRL, - "bl", // PPC_INS_BL, - "bla", // PPC_INS_BLA, - "ble", // PPC_INS_BLE, - "blea", // PPC_INS_BLEA, - "blectr", // PPC_INS_BLECTR, - "blectrl", // PPC_INS_BLECTRL, - "blel", // PPC_INS_BLEL, - "blela", // PPC_INS_BLELA, - "blelr", // PPC_INS_BLELR, - "blelrl", // PPC_INS_BLELRL, - "blr", // PPC_INS_BLR, - "blrl", // PPC_INS_BLRL, - "blt", // PPC_INS_BLT, - "blta", // PPC_INS_BLTA, - "bltctr", // PPC_INS_BLTCTR, - "bltctrl", // PPC_INS_BLTCTRL, - "bltl", // PPC_INS_BLTL, - "bltla", // PPC_INS_BLTLA, - "bltlr", // PPC_INS_BLTLR, - "bltlrl", // PPC_INS_BLTLRL, - "bne", // PPC_INS_BNE, - "bnea", // PPC_INS_BNEA, - "bnectr", // PPC_INS_BNECTR, - "bnectrl", // PPC_INS_BNECTRL, - "bnel", // PPC_INS_BNEL, - "bnela", // PPC_INS_BNELA, - "bnelr", // PPC_INS_BNELR, - "bnelrl", // PPC_INS_BNELRL, - "bng", // PPC_INS_BNG, - "bnga", // PPC_INS_BNGA, - "bngctr", // PPC_INS_BNGCTR, - "bngctrl", // PPC_INS_BNGCTRL, - "bngl", // PPC_INS_BNGL, - "bngla", // PPC_INS_BNGLA, - "bnglr", // PPC_INS_BNGLR, - "bnglrl", // PPC_INS_BNGLRL, - "bnl", // PPC_INS_BNL, - "bnla", // PPC_INS_BNLA, - "bnlctr", // PPC_INS_BNLCTR, - "bnlctrl", // PPC_INS_BNLCTRL, - "bnll", // PPC_INS_BNLL, - "bnlla", // PPC_INS_BNLLA, - "bnllr", // PPC_INS_BNLLR, - "bnllrl", // PPC_INS_BNLLRL, - "bns", // PPC_INS_BNS, - "bnsa", // PPC_INS_BNSA, - "bnsctr", // PPC_INS_BNSCTR, - "bnsctrl", // PPC_INS_BNSCTRL, - "bnsl", // PPC_INS_BNSL, - "bnsla", // PPC_INS_BNSLA, - "bnslr", // PPC_INS_BNSLR, - "bnslrl", // PPC_INS_BNSLRL, - "bnu", // PPC_INS_BNU, - "bnua", // PPC_INS_BNUA, - "bnuctr", // PPC_INS_BNUCTR, - "bnuctrl", // PPC_INS_BNUCTRL, - "bnul", // PPC_INS_BNUL, - "bnula", // PPC_INS_BNULA, - "bnulr", // PPC_INS_BNULR, - "bnulrl", // PPC_INS_BNULRL, - "bpermd", // PPC_INS_BPERMD, - "brinc", // PPC_INS_BRINC, - "bso", // PPC_INS_BSO, - "bsoa", // PPC_INS_BSOA, - "bsoctr", // PPC_INS_BSOCTR, - "bsoctrl", // PPC_INS_BSOCTRL, - "bsol", // PPC_INS_BSOL, - "bsola", // PPC_INS_BSOLA, - "bsolr", // PPC_INS_BSOLR, - "bsolrl", // PPC_INS_BSOLRL, - "bt", // PPC_INS_BT, - "bta", // PPC_INS_BTA, - "btctr", // PPC_INS_BTCTR, - "btctrl", // PPC_INS_BTCTRL, - "btl", // PPC_INS_BTL, - "btla", // PPC_INS_BTLA, - "btlr", // PPC_INS_BTLR, - "btlrl", // PPC_INS_BTLRL, - "bun", // PPC_INS_BUN, - "buna", // PPC_INS_BUNA, - "bunctr", // PPC_INS_BUNCTR, - "bunctrl", // PPC_INS_BUNCTRL, - "bunl", // PPC_INS_BUNL, - "bunla", // PPC_INS_BUNLA, - "bunlr", // PPC_INS_BUNLR, - "bunlrl", // PPC_INS_BUNLRL, - "clrbhrb", // PPC_INS_CLRBHRB, - "clrldi", // PPC_INS_CLRLDI, - "clrlsldi", // PPC_INS_CLRLSLDI, - "clrlslwi", // PPC_INS_CLRLSLWI, - "clrlwi", // PPC_INS_CLRLWI, - "clrrdi", // PPC_INS_CLRRDI, - "clrrwi", // PPC_INS_CLRRWI, - "cmp", // PPC_INS_CMP, - "cmpb", // PPC_INS_CMPB, - "cmpd", // PPC_INS_CMPD, - "cmpdi", // PPC_INS_CMPDI, - "cmpeqb", // PPC_INS_CMPEQB, - "cmpi", // PPC_INS_CMPI, - "cmpl", // PPC_INS_CMPL, - "cmpld", // PPC_INS_CMPLD, - "cmpldi", // PPC_INS_CMPLDI, - "cmpli", // PPC_INS_CMPLI, - "cmplw", // PPC_INS_CMPLW, - "cmplwi", // PPC_INS_CMPLWI, - "cmprb", // PPC_INS_CMPRB, - "cmpw", // PPC_INS_CMPW, - "cmpwi", // PPC_INS_CMPWI, - "cntlzd", // PPC_INS_CNTLZD, - "cntlzw", // PPC_INS_CNTLZW, - "cnttzd", // PPC_INS_CNTTZD, - "cnttzw", // PPC_INS_CNTTZW, - "copy", // PPC_INS_COPY, - "copy_first", // PPC_INS_COPY_FIRST, - "cp_abort", // PPC_INS_CP_ABORT, - "crand", // PPC_INS_CRAND, - "crandc", // PPC_INS_CRANDC, - "crclr", // PPC_INS_CRCLR, - "creqv", // PPC_INS_CREQV, - "crmove", // PPC_INS_CRMOVE, - "crnand", // PPC_INS_CRNAND, - "crnor", // PPC_INS_CRNOR, - "crnot", // PPC_INS_CRNOT, - "cror", // PPC_INS_CROR, - "crorc", // PPC_INS_CRORC, - "crset", // PPC_INS_CRSET, - "crxor", // PPC_INS_CRXOR, - "darn", // PPC_INS_DARN, - "dcba", // PPC_INS_DCBA, - "dcbf", // PPC_INS_DCBF, - "dcbfep", // PPC_INS_DCBFEP, - "dcbfl", // PPC_INS_DCBFL, - "dcbflp", // PPC_INS_DCBFLP, - "dcbi", // PPC_INS_DCBI, - "dcbst", // PPC_INS_DCBST, - "dcbstep", // PPC_INS_DCBSTEP, - "dcbt", // PPC_INS_DCBT, - "dcbtct", // PPC_INS_DCBTCT, - "dcbtds", // PPC_INS_DCBTDS, - "dcbtep", // PPC_INS_DCBTEP, - "dcbtst", // PPC_INS_DCBTST, - "dcbtstct", // PPC_INS_DCBTSTCT, - "dcbtstds", // PPC_INS_DCBTSTDS, - "dcbtstep", // PPC_INS_DCBTSTEP, - "dcbtstt", // PPC_INS_DCBTSTT, - "dcbtt", // PPC_INS_DCBTT, - "dcbz", // PPC_INS_DCBZ, - "dcbzep", // PPC_INS_DCBZEP, - "dcbzl", // PPC_INS_DCBZL, - "dcbzlep", // PPC_INS_DCBZLEP, - "dccci", // PPC_INS_DCCCI, - "dci", // PPC_INS_DCI, - "divd", // PPC_INS_DIVD, - "divde", // PPC_INS_DIVDE, - "divdeu", // PPC_INS_DIVDEU, - "divdu", // PPC_INS_DIVDU, - "divw", // PPC_INS_DIVW, - "divwe", // PPC_INS_DIVWE, - "divweu", // PPC_INS_DIVWEU, - "divwu", // PPC_INS_DIVWU, - "dss", // PPC_INS_DSS, - "dssall", // PPC_INS_DSSALL, - "dst", // PPC_INS_DST, - "dstst", // PPC_INS_DSTST, - "dststt", // PPC_INS_DSTSTT, - "dstt", // PPC_INS_DSTT, - "efdabs", // PPC_INS_EFDABS, - "efdadd", // PPC_INS_EFDADD, - "efdcfs", // PPC_INS_EFDCFS, - "efdcfsf", // PPC_INS_EFDCFSF, - "efdcfsi", // PPC_INS_EFDCFSI, - "efdcfsid", // PPC_INS_EFDCFSID, - "efdcfuf", // PPC_INS_EFDCFUF, - "efdcfui", // PPC_INS_EFDCFUI, - "efdcfuid", // PPC_INS_EFDCFUID, - "efdcmpeq", // PPC_INS_EFDCMPEQ, - "efdcmpgt", // PPC_INS_EFDCMPGT, - "efdcmplt", // PPC_INS_EFDCMPLT, - "efdctsf", // PPC_INS_EFDCTSF, - "efdctsi", // PPC_INS_EFDCTSI, - "efdctsidz", // PPC_INS_EFDCTSIDZ, - "efdctsiz", // PPC_INS_EFDCTSIZ, - "efdctuf", // PPC_INS_EFDCTUF, - "efdctui", // PPC_INS_EFDCTUI, - "efdctuidz", // PPC_INS_EFDCTUIDZ, - "efdctuiz", // PPC_INS_EFDCTUIZ, - "efddiv", // PPC_INS_EFDDIV, - "efdmul", // PPC_INS_EFDMUL, - "efdnabs", // PPC_INS_EFDNABS, - "efdneg", // PPC_INS_EFDNEG, - "efdsub", // PPC_INS_EFDSUB, - "efdtsteq", // PPC_INS_EFDTSTEQ, - "efdtstgt", // PPC_INS_EFDTSTGT, - "efdtstlt", // PPC_INS_EFDTSTLT, - "efsabs", // PPC_INS_EFSABS, - "efsadd", // PPC_INS_EFSADD, - "efscfd", // PPC_INS_EFSCFD, - "efscfsf", // PPC_INS_EFSCFSF, - "efscfsi", // PPC_INS_EFSCFSI, - "efscfuf", // PPC_INS_EFSCFUF, - "efscfui", // PPC_INS_EFSCFUI, - "efscmpeq", // PPC_INS_EFSCMPEQ, - "efscmpgt", // PPC_INS_EFSCMPGT, - "efscmplt", // PPC_INS_EFSCMPLT, - "efsctsf", // PPC_INS_EFSCTSF, - "efsctsi", // PPC_INS_EFSCTSI, - "efsctsiz", // PPC_INS_EFSCTSIZ, - "efsctuf", // PPC_INS_EFSCTUF, - "efsctui", // PPC_INS_EFSCTUI, - "efsctuiz", // PPC_INS_EFSCTUIZ, - "efsdiv", // PPC_INS_EFSDIV, - "efsmul", // PPC_INS_EFSMUL, - "efsnabs", // PPC_INS_EFSNABS, - "efsneg", // PPC_INS_EFSNEG, - "efssub", // PPC_INS_EFSSUB, - "efststeq", // PPC_INS_EFSTSTEQ, - "efststgt", // PPC_INS_EFSTSTGT, - "efststlt", // PPC_INS_EFSTSTLT, - "eieio", // PPC_INS_EIEIO, - "eqv", // PPC_INS_EQV, - "evabs", // PPC_INS_EVABS, - "evaddiw", // PPC_INS_EVADDIW, - "evaddsmiaaw", // PPC_INS_EVADDSMIAAW, - "evaddssiaaw", // PPC_INS_EVADDSSIAAW, - "evaddumiaaw", // PPC_INS_EVADDUMIAAW, - "evaddusiaaw", // PPC_INS_EVADDUSIAAW, - "evaddw", // PPC_INS_EVADDW, - "evand", // PPC_INS_EVAND, - "evandc", // PPC_INS_EVANDC, - "evcmpeq", // PPC_INS_EVCMPEQ, - "evcmpgts", // PPC_INS_EVCMPGTS, - "evcmpgtu", // PPC_INS_EVCMPGTU, - "evcmplts", // PPC_INS_EVCMPLTS, - "evcmpltu", // PPC_INS_EVCMPLTU, - "evcntlsw", // PPC_INS_EVCNTLSW, - "evcntlzw", // PPC_INS_EVCNTLZW, - "evdivws", // PPC_INS_EVDIVWS, - "evdivwu", // PPC_INS_EVDIVWU, - "eveqv", // PPC_INS_EVEQV, - "evextsb", // PPC_INS_EVEXTSB, - "evextsh", // PPC_INS_EVEXTSH, - "evfsabs", // PPC_INS_EVFSABS, - "evfsadd", // PPC_INS_EVFSADD, - "evfscfsf", // PPC_INS_EVFSCFSF, - "evfscfsi", // PPC_INS_EVFSCFSI, - "evfscfuf", // PPC_INS_EVFSCFUF, - "evfscfui", // PPC_INS_EVFSCFUI, - "evfscmpeq", // PPC_INS_EVFSCMPEQ, - "evfscmpgt", // PPC_INS_EVFSCMPGT, - "evfscmplt", // PPC_INS_EVFSCMPLT, - "evfsctsf", // PPC_INS_EVFSCTSF, - "evfsctsi", // PPC_INS_EVFSCTSI, - "evfsctsiz", // PPC_INS_EVFSCTSIZ, - "evfsctui", // PPC_INS_EVFSCTUI, - "evfsdiv", // PPC_INS_EVFSDIV, - "evfsmul", // PPC_INS_EVFSMUL, - "evfsnabs", // PPC_INS_EVFSNABS, - "evfsneg", // PPC_INS_EVFSNEG, - "evfssub", // PPC_INS_EVFSSUB, - "evfststeq", // PPC_INS_EVFSTSTEQ, - "evfststgt", // PPC_INS_EVFSTSTGT, - "evfststlt", // PPC_INS_EVFSTSTLT, - "evldd", // PPC_INS_EVLDD, - "evlddx", // PPC_INS_EVLDDX, - "evldh", // PPC_INS_EVLDH, - "evldhx", // PPC_INS_EVLDHX, - "evldw", // PPC_INS_EVLDW, - "evldwx", // PPC_INS_EVLDWX, - "evlhhesplat", // PPC_INS_EVLHHESPLAT, - "evlhhesplatx", // PPC_INS_EVLHHESPLATX, - "evlhhossplat", // PPC_INS_EVLHHOSSPLAT, - "evlhhossplatx", // PPC_INS_EVLHHOSSPLATX, - "evlhhousplat", // PPC_INS_EVLHHOUSPLAT, - "evlhhousplatx", // PPC_INS_EVLHHOUSPLATX, - "evlwhe", // PPC_INS_EVLWHE, - "evlwhex", // PPC_INS_EVLWHEX, - "evlwhos", // PPC_INS_EVLWHOS, - "evlwhosx", // PPC_INS_EVLWHOSX, - "evlwhou", // PPC_INS_EVLWHOU, - "evlwhoux", // PPC_INS_EVLWHOUX, - "evlwhsplat", // PPC_INS_EVLWHSPLAT, - "evlwhsplatx", // PPC_INS_EVLWHSPLATX, - "evlwwsplat", // PPC_INS_EVLWWSPLAT, - "evlwwsplatx", // PPC_INS_EVLWWSPLATX, - "evmergehi", // PPC_INS_EVMERGEHI, - "evmergehilo", // PPC_INS_EVMERGEHILO, - "evmergelo", // PPC_INS_EVMERGELO, - "evmergelohi", // PPC_INS_EVMERGELOHI, - "evmhegsmfaa", // PPC_INS_EVMHEGSMFAA, - "evmhegsmfan", // PPC_INS_EVMHEGSMFAN, - "evmhegsmiaa", // PPC_INS_EVMHEGSMIAA, - "evmhegsmian", // PPC_INS_EVMHEGSMIAN, - "evmhegumiaa", // PPC_INS_EVMHEGUMIAA, - "evmhegumian", // PPC_INS_EVMHEGUMIAN, - "evmhesmf", // PPC_INS_EVMHESMF, - "evmhesmfa", // PPC_INS_EVMHESMFA, - "evmhesmfaaw", // PPC_INS_EVMHESMFAAW, - "evmhesmfanw", // PPC_INS_EVMHESMFANW, - "evmhesmi", // PPC_INS_EVMHESMI, - "evmhesmia", // PPC_INS_EVMHESMIA, - "evmhesmiaaw", // PPC_INS_EVMHESMIAAW, - "evmhesmianw", // PPC_INS_EVMHESMIANW, - "evmhessf", // PPC_INS_EVMHESSF, - "evmhessfa", // PPC_INS_EVMHESSFA, - "evmhessfaaw", // PPC_INS_EVMHESSFAAW, - "evmhessfanw", // PPC_INS_EVMHESSFANW, - "evmhessiaaw", // PPC_INS_EVMHESSIAAW, - "evmhessianw", // PPC_INS_EVMHESSIANW, - "evmheumi", // PPC_INS_EVMHEUMI, - "evmheumia", // PPC_INS_EVMHEUMIA, - "evmheumiaaw", // PPC_INS_EVMHEUMIAAW, - "evmheumianw", // PPC_INS_EVMHEUMIANW, - "evmheusiaaw", // PPC_INS_EVMHEUSIAAW, - "evmheusianw", // PPC_INS_EVMHEUSIANW, - "evmhogsmfaa", // PPC_INS_EVMHOGSMFAA, - "evmhogsmfan", // PPC_INS_EVMHOGSMFAN, - "evmhogsmiaa", // PPC_INS_EVMHOGSMIAA, - "evmhogsmian", // PPC_INS_EVMHOGSMIAN, - "evmhogumiaa", // PPC_INS_EVMHOGUMIAA, - "evmhogumian", // PPC_INS_EVMHOGUMIAN, - "evmhosmf", // PPC_INS_EVMHOSMF, - "evmhosmfa", // PPC_INS_EVMHOSMFA, - "evmhosmfaaw", // PPC_INS_EVMHOSMFAAW, - "evmhosmfanw", // PPC_INS_EVMHOSMFANW, - "evmhosmi", // PPC_INS_EVMHOSMI, - "evmhosmia", // PPC_INS_EVMHOSMIA, - "evmhosmiaaw", // PPC_INS_EVMHOSMIAAW, - "evmhosmianw", // PPC_INS_EVMHOSMIANW, - "evmhossf", // PPC_INS_EVMHOSSF, - "evmhossfa", // PPC_INS_EVMHOSSFA, - "evmhossfaaw", // PPC_INS_EVMHOSSFAAW, - "evmhossfanw", // PPC_INS_EVMHOSSFANW, - "evmhossiaaw", // PPC_INS_EVMHOSSIAAW, - "evmhossianw", // PPC_INS_EVMHOSSIANW, - "evmhoumi", // PPC_INS_EVMHOUMI, - "evmhoumia", // PPC_INS_EVMHOUMIA, - "evmhoumiaaw", // PPC_INS_EVMHOUMIAAW, - "evmhoumianw", // PPC_INS_EVMHOUMIANW, - "evmhousiaaw", // PPC_INS_EVMHOUSIAAW, - "evmhousianw", // PPC_INS_EVMHOUSIANW, - "evmra", // PPC_INS_EVMRA, - "evmwhsmf", // PPC_INS_EVMWHSMF, - "evmwhsmfa", // PPC_INS_EVMWHSMFA, - "evmwhsmi", // PPC_INS_EVMWHSMI, - "evmwhsmia", // PPC_INS_EVMWHSMIA, - "evmwhssf", // PPC_INS_EVMWHSSF, - "evmwhssfa", // PPC_INS_EVMWHSSFA, - "evmwhumi", // PPC_INS_EVMWHUMI, - "evmwhumia", // PPC_INS_EVMWHUMIA, - "evmwlsmiaaw", // PPC_INS_EVMWLSMIAAW, - "evmwlsmianw", // PPC_INS_EVMWLSMIANW, - "evmwlssiaaw", // PPC_INS_EVMWLSSIAAW, - "evmwlssianw", // PPC_INS_EVMWLSSIANW, - "evmwlumi", // PPC_INS_EVMWLUMI, - "evmwlumia", // PPC_INS_EVMWLUMIA, - "evmwlumiaaw", // PPC_INS_EVMWLUMIAAW, - "evmwlumianw", // PPC_INS_EVMWLUMIANW, - "evmwlusiaaw", // PPC_INS_EVMWLUSIAAW, - "evmwlusianw", // PPC_INS_EVMWLUSIANW, - "evmwsmf", // PPC_INS_EVMWSMF, - "evmwsmfa", // PPC_INS_EVMWSMFA, - "evmwsmfaa", // PPC_INS_EVMWSMFAA, - "evmwsmfan", // PPC_INS_EVMWSMFAN, - "evmwsmi", // PPC_INS_EVMWSMI, - "evmwsmia", // PPC_INS_EVMWSMIA, - "evmwsmiaa", // PPC_INS_EVMWSMIAA, - "evmwsmian", // PPC_INS_EVMWSMIAN, - "evmwssf", // PPC_INS_EVMWSSF, - "evmwssfa", // PPC_INS_EVMWSSFA, - "evmwssfaa", // PPC_INS_EVMWSSFAA, - "evmwssfan", // PPC_INS_EVMWSSFAN, - "evmwumi", // PPC_INS_EVMWUMI, - "evmwumia", // PPC_INS_EVMWUMIA, - "evmwumiaa", // PPC_INS_EVMWUMIAA, - "evmwumian", // PPC_INS_EVMWUMIAN, - "evnand", // PPC_INS_EVNAND, - "evneg", // PPC_INS_EVNEG, - "evnor", // PPC_INS_EVNOR, - "evor", // PPC_INS_EVOR, - "evorc", // PPC_INS_EVORC, - "evrlw", // PPC_INS_EVRLW, - "evrlwi", // PPC_INS_EVRLWI, - "evrndw", // PPC_INS_EVRNDW, - "evsel", // PPC_INS_EVSEL, - "evslw", // PPC_INS_EVSLW, - "evslwi", // PPC_INS_EVSLWI, - "evsplatfi", // PPC_INS_EVSPLATFI, - "evsplati", // PPC_INS_EVSPLATI, - "evsrwis", // PPC_INS_EVSRWIS, - "evsrwiu", // PPC_INS_EVSRWIU, - "evsrws", // PPC_INS_EVSRWS, - "evsrwu", // PPC_INS_EVSRWU, - "evstdd", // PPC_INS_EVSTDD, - "evstddx", // PPC_INS_EVSTDDX, - "evstdh", // PPC_INS_EVSTDH, - "evstdhx", // PPC_INS_EVSTDHX, - "evstdw", // PPC_INS_EVSTDW, - "evstdwx", // PPC_INS_EVSTDWX, - "evstwhe", // PPC_INS_EVSTWHE, - "evstwhex", // PPC_INS_EVSTWHEX, - "evstwho", // PPC_INS_EVSTWHO, - "evstwhox", // PPC_INS_EVSTWHOX, - "evstwwe", // PPC_INS_EVSTWWE, - "evstwwex", // PPC_INS_EVSTWWEX, - "evstwwo", // PPC_INS_EVSTWWO, - "evstwwox", // PPC_INS_EVSTWWOX, - "evsubfsmiaaw", // PPC_INS_EVSUBFSMIAAW, - "evsubfssiaaw", // PPC_INS_EVSUBFSSIAAW, - "evsubfumiaaw", // PPC_INS_EVSUBFUMIAAW, - "evsubfusiaaw", // PPC_INS_EVSUBFUSIAAW, - "evsubfw", // PPC_INS_EVSUBFW, - "evsubifw", // PPC_INS_EVSUBIFW, - "evxor", // PPC_INS_EVXOR, - "extldi", // PPC_INS_EXTLDI, - "extlwi", // PPC_INS_EXTLWI, - "extrdi", // PPC_INS_EXTRDI, - "extrwi", // PPC_INS_EXTRWI, - "extsb", // PPC_INS_EXTSB, - "extsh", // PPC_INS_EXTSH, - "extsw", // PPC_INS_EXTSW, - "extswsli", // PPC_INS_EXTSWSLI, - "fabs", // PPC_INS_FABS, - "fadd", // PPC_INS_FADD, - "fadds", // PPC_INS_FADDS, - "fcfid", // PPC_INS_FCFID, - "fcfids", // PPC_INS_FCFIDS, - "fcfidu", // PPC_INS_FCFIDU, - "fcfidus", // PPC_INS_FCFIDUS, - "fcmpu", // PPC_INS_FCMPU, - "fcpsgn", // PPC_INS_FCPSGN, - "fctid", // PPC_INS_FCTID, - "fctidu", // PPC_INS_FCTIDU, - "fctiduz", // PPC_INS_FCTIDUZ, - "fctidz", // PPC_INS_FCTIDZ, - "fctiw", // PPC_INS_FCTIW, - "fctiwu", // PPC_INS_FCTIWU, - "fctiwuz", // PPC_INS_FCTIWUZ, - "fctiwz", // PPC_INS_FCTIWZ, - "fdiv", // PPC_INS_FDIV, - "fdivs", // PPC_INS_FDIVS, - "fmadd", // PPC_INS_FMADD, - "fmadds", // PPC_INS_FMADDS, - "fmr", // PPC_INS_FMR, - "fmsub", // PPC_INS_FMSUB, - "fmsubs", // PPC_INS_FMSUBS, - "fmul", // PPC_INS_FMUL, - "fmuls", // PPC_INS_FMULS, - "fnabs", // PPC_INS_FNABS, - "fneg", // PPC_INS_FNEG, - "fnmadd", // PPC_INS_FNMADD, - "fnmadds", // PPC_INS_FNMADDS, - "fnmsub", // PPC_INS_FNMSUB, - "fnmsubs", // PPC_INS_FNMSUBS, - "fre", // PPC_INS_FRE, - "fres", // PPC_INS_FRES, - "frim", // PPC_INS_FRIM, - "frin", // PPC_INS_FRIN, - "frip", // PPC_INS_FRIP, - "friz", // PPC_INS_FRIZ, - "frsp", // PPC_INS_FRSP, - "frsqrte", // PPC_INS_FRSQRTE, - "frsqrtes", // PPC_INS_FRSQRTES, - "fsel", // PPC_INS_FSEL, - "fsqrt", // PPC_INS_FSQRT, - "fsqrts", // PPC_INS_FSQRTS, - "fsub", // PPC_INS_FSUB, - "fsubs", // PPC_INS_FSUBS, - "ftdiv", // PPC_INS_FTDIV, - "ftsqrt", // PPC_INS_FTSQRT, - "hrfid", // PPC_INS_HRFID, - "icbi", // PPC_INS_ICBI, - "icbiep", // PPC_INS_ICBIEP, - "icblc", // PPC_INS_ICBLC, - "icblq", // PPC_INS_ICBLQ, - "icbt", // PPC_INS_ICBT, - "icbtls", // PPC_INS_ICBTLS, - "iccci", // PPC_INS_ICCCI, - "ici", // PPC_INS_ICI, - "inslwi", // PPC_INS_INSLWI, - "insrdi", // PPC_INS_INSRDI, - "insrwi", // PPC_INS_INSRWI, - "isel", // PPC_INS_ISEL, - "isync", // PPC_INS_ISYNC, - "la", // PPC_INS_LA, - "lbarx", // PPC_INS_LBARX, - "lbepx", // PPC_INS_LBEPX, - "lbz", // PPC_INS_LBZ, - "lbzcix", // PPC_INS_LBZCIX, - "lbzu", // PPC_INS_LBZU, - "lbzux", // PPC_INS_LBZUX, - "lbzx", // PPC_INS_LBZX, - "ld", // PPC_INS_LD, - "ldarx", // PPC_INS_LDARX, - "ldat", // PPC_INS_LDAT, - "ldbrx", // PPC_INS_LDBRX, - "ldcix", // PPC_INS_LDCIX, - "ldmx", // PPC_INS_LDMX, - "ldu", // PPC_INS_LDU, - "ldux", // PPC_INS_LDUX, - "ldx", // PPC_INS_LDX, - "lfd", // PPC_INS_LFD, - "lfdepx", // PPC_INS_LFDEPX, - "lfdu", // PPC_INS_LFDU, - "lfdux", // PPC_INS_LFDUX, - "lfdx", // PPC_INS_LFDX, - "lfiwax", // PPC_INS_LFIWAX, - "lfiwzx", // PPC_INS_LFIWZX, - "lfs", // PPC_INS_LFS, - "lfsu", // PPC_INS_LFSU, - "lfsux", // PPC_INS_LFSUX, - "lfsx", // PPC_INS_LFSX, - "lha", // PPC_INS_LHA, - "lharx", // PPC_INS_LHARX, - "lhau", // PPC_INS_LHAU, - "lhaux", // PPC_INS_LHAUX, - "lhax", // PPC_INS_LHAX, - "lhbrx", // PPC_INS_LHBRX, - "lhepx", // PPC_INS_LHEPX, - "lhz", // PPC_INS_LHZ, - "lhzcix", // PPC_INS_LHZCIX, - "lhzu", // PPC_INS_LHZU, - "lhzux", // PPC_INS_LHZUX, - "lhzx", // PPC_INS_LHZX, - "li", // PPC_INS_LI, - "lis", // PPC_INS_LIS, - "lmw", // PPC_INS_LMW, - "lnia", // PPC_INS_LNIA, - "lswi", // PPC_INS_LSWI, - "lvebx", // PPC_INS_LVEBX, - "lvehx", // PPC_INS_LVEHX, - "lvewx", // PPC_INS_LVEWX, - "lvsl", // PPC_INS_LVSL, - "lvsr", // PPC_INS_LVSR, - "lvx", // PPC_INS_LVX, - "lvxl", // PPC_INS_LVXL, - "lwa", // PPC_INS_LWA, - "lwarx", // PPC_INS_LWARX, - "lwat", // PPC_INS_LWAT, - "lwaux", // PPC_INS_LWAUX, - "lwax", // PPC_INS_LWAX, - "lwbrx", // PPC_INS_LWBRX, - "lwepx", // PPC_INS_LWEPX, - "lwsync", // PPC_INS_LWSYNC, - "lwz", // PPC_INS_LWZ, - "lwzcix", // PPC_INS_LWZCIX, - "lwzu", // PPC_INS_LWZU, - "lwzux", // PPC_INS_LWZUX, - "lwzx", // PPC_INS_LWZX, - "lxsd", // PPC_INS_LXSD, - "lxsdx", // PPC_INS_LXSDX, - "lxsibzx", // PPC_INS_LXSIBZX, - "lxsihzx", // PPC_INS_LXSIHZX, - "lxsiwax", // PPC_INS_LXSIWAX, - "lxsiwzx", // PPC_INS_LXSIWZX, - "lxssp", // PPC_INS_LXSSP, - "lxsspx", // PPC_INS_LXSSPX, - "lxv", // PPC_INS_LXV, - "lxvb16x", // PPC_INS_LXVB16X, - "lxvd2x", // PPC_INS_LXVD2X, - "lxvdsx", // PPC_INS_LXVDSX, - "lxvh8x", // PPC_INS_LXVH8X, - "lxvl", // PPC_INS_LXVL, - "lxvll", // PPC_INS_LXVLL, - "lxvw4x", // PPC_INS_LXVW4X, - "lxvwsx", // PPC_INS_LXVWSX, - "lxvx", // PPC_INS_LXVX, - "maddhd", // PPC_INS_MADDHD, - "maddhdu", // PPC_INS_MADDHDU, - "maddld", // PPC_INS_MADDLD, - "mbar", // PPC_INS_MBAR, - "mcrf", // PPC_INS_MCRF, - "mcrfs", // PPC_INS_MCRFS, - "mcrxrx", // PPC_INS_MCRXRX, - "mfamr", // PPC_INS_MFAMR, - "mfasr", // PPC_INS_MFASR, - "mfbhrbe", // PPC_INS_MFBHRBE, - "mfbr0", // PPC_INS_MFBR0, - "mfbr1", // PPC_INS_MFBR1, - "mfbr2", // PPC_INS_MFBR2, - "mfbr3", // PPC_INS_MFBR3, - "mfbr4", // PPC_INS_MFBR4, - "mfbr5", // PPC_INS_MFBR5, - "mfbr6", // PPC_INS_MFBR6, - "mfbr7", // PPC_INS_MFBR7, - "mfcfar", // PPC_INS_MFCFAR, - "mfcr", // PPC_INS_MFCR, - "mfctr", // PPC_INS_MFCTR, - "mfdar", // PPC_INS_MFDAR, - "mfdbatl", // PPC_INS_MFDBATL, - "mfdbatu", // PPC_INS_MFDBATU, - "mfdccr", // PPC_INS_MFDCCR, - "mfdcr", // PPC_INS_MFDCR, - "mfdear", // PPC_INS_MFDEAR, - "mfdec", // PPC_INS_MFDEC, - "mfdscr", // PPC_INS_MFDSCR, - "mfdsisr", // PPC_INS_MFDSISR, - "mfesr", // PPC_INS_MFESR, - "mffprd", // PPC_INS_MFFPRD, - "mffs", // PPC_INS_MFFS, - "mffscdrn", // PPC_INS_MFFSCDRN, - "mffscdrni", // PPC_INS_MFFSCDRNI, - "mffsce", // PPC_INS_MFFSCE, - "mffscrn", // PPC_INS_MFFSCRN, - "mffscrni", // PPC_INS_MFFSCRNI, - "mffsl", // PPC_INS_MFFSL, - "mfibatl", // PPC_INS_MFIBATL, - "mfibatu", // PPC_INS_MFIBATU, - "mficcr", // PPC_INS_MFICCR, - "mflr", // PPC_INS_MFLR, - "mfmsr", // PPC_INS_MFMSR, - "mfocrf", // PPC_INS_MFOCRF, - "mfpid", // PPC_INS_MFPID, - "mfpmr", // PPC_INS_MFPMR, - "mfpvr", // PPC_INS_MFPVR, - "mfrtcl", // PPC_INS_MFRTCL, - "mfrtcu", // PPC_INS_MFRTCU, - "mfsdr1", // PPC_INS_MFSDR1, - "mfspefscr", // PPC_INS_MFSPEFSCR, - "mfspr", // PPC_INS_MFSPR, - "mfsprg", // PPC_INS_MFSPRG, - "mfsprg0", // PPC_INS_MFSPRG0, - "mfsprg1", // PPC_INS_MFSPRG1, - "mfsprg2", // PPC_INS_MFSPRG2, - "mfsprg3", // PPC_INS_MFSPRG3, - "mfsprg4", // PPC_INS_MFSPRG4, - "mfsprg5", // PPC_INS_MFSPRG5, - "mfsprg6", // PPC_INS_MFSPRG6, - "mfsprg7", // PPC_INS_MFSPRG7, - "mfsr", // PPC_INS_MFSR, - "mfsrin", // PPC_INS_MFSRIN, - "mfsrr0", // PPC_INS_MFSRR0, - "mfsrr1", // PPC_INS_MFSRR1, - "mfsrr2", // PPC_INS_MFSRR2, - "mfsrr3", // PPC_INS_MFSRR3, - "mftb", // PPC_INS_MFTB, - "mftbhi", // PPC_INS_MFTBHI, - "mftbl", // PPC_INS_MFTBL, - "mftblo", // PPC_INS_MFTBLO, - "mftbu", // PPC_INS_MFTBU, - "mftcr", // PPC_INS_MFTCR, - "mfvrd", // PPC_INS_MFVRD, - "mfvrsave", // PPC_INS_MFVRSAVE, - "mfvscr", // PPC_INS_MFVSCR, - "mfvsrd", // PPC_INS_MFVSRD, - "mfvsrld", // PPC_INS_MFVSRLD, - "mfvsrwz", // PPC_INS_MFVSRWZ, - "mfxer", // PPC_INS_MFXER, - "modsd", // PPC_INS_MODSD, - "modsw", // PPC_INS_MODSW, - "modud", // PPC_INS_MODUD, - "moduw", // PPC_INS_MODUW, - "mr", // PPC_INS_MR, - "msgsync", // PPC_INS_MSGSYNC, - "msync", // PPC_INS_MSYNC, - "mtamr", // PPC_INS_MTAMR, - "mtasr", // PPC_INS_MTASR, - "mtbr0", // PPC_INS_MTBR0, - "mtbr1", // PPC_INS_MTBR1, - "mtbr2", // PPC_INS_MTBR2, - "mtbr3", // PPC_INS_MTBR3, - "mtbr4", // PPC_INS_MTBR4, - "mtbr5", // PPC_INS_MTBR5, - "mtbr6", // PPC_INS_MTBR6, - "mtbr7", // PPC_INS_MTBR7, - "mtcfar", // PPC_INS_MTCFAR, - "mtcr", // PPC_INS_MTCR, - "mtcrf", // PPC_INS_MTCRF, - "mtctr", // PPC_INS_MTCTR, - "mtdar", // PPC_INS_MTDAR, - "mtdbatl", // PPC_INS_MTDBATL, - "mtdbatu", // PPC_INS_MTDBATU, - "mtdccr", // PPC_INS_MTDCCR, - "mtdcr", // PPC_INS_MTDCR, - "mtdear", // PPC_INS_MTDEAR, - "mtdec", // PPC_INS_MTDEC, - "mtdscr", // PPC_INS_MTDSCR, - "mtdsisr", // PPC_INS_MTDSISR, - "mtesr", // PPC_INS_MTESR, - "mtfsb0", // PPC_INS_MTFSB0, - "mtfsb1", // PPC_INS_MTFSB1, - "mtfsf", // PPC_INS_MTFSF, - "mtfsfi", // PPC_INS_MTFSFI, - "mtibatl", // PPC_INS_MTIBATL, - "mtibatu", // PPC_INS_MTIBATU, - "mticcr", // PPC_INS_MTICCR, - "mtlr", // PPC_INS_MTLR, - "mtmsr", // PPC_INS_MTMSR, - "mtmsrd", // PPC_INS_MTMSRD, - "mtocrf", // PPC_INS_MTOCRF, - "mtpid", // PPC_INS_MTPID, - "mtpmr", // PPC_INS_MTPMR, - "mtsdr1", // PPC_INS_MTSDR1, - "mtspefscr", // PPC_INS_MTSPEFSCR, - "mtspr", // PPC_INS_MTSPR, - "mtsprg", // PPC_INS_MTSPRG, - "mtsprg0", // PPC_INS_MTSPRG0, - "mtsprg1", // PPC_INS_MTSPRG1, - "mtsprg2", // PPC_INS_MTSPRG2, - "mtsprg3", // PPC_INS_MTSPRG3, - "mtsprg4", // PPC_INS_MTSPRG4, - "mtsprg5", // PPC_INS_MTSPRG5, - "mtsprg6", // PPC_INS_MTSPRG6, - "mtsprg7", // PPC_INS_MTSPRG7, - "mtsr", // PPC_INS_MTSR, - "mtsrin", // PPC_INS_MTSRIN, - "mtsrr0", // PPC_INS_MTSRR0, - "mtsrr1", // PPC_INS_MTSRR1, - "mtsrr2", // PPC_INS_MTSRR2, - "mtsrr3", // PPC_INS_MTSRR3, - "mttbhi", // PPC_INS_MTTBHI, - "mttbl", // PPC_INS_MTTBL, - "mttblo", // PPC_INS_MTTBLO, - "mttbu", // PPC_INS_MTTBU, - "mttcr", // PPC_INS_MTTCR, - "mtvrsave", // PPC_INS_MTVRSAVE, - "mtvscr", // PPC_INS_MTVSCR, - "mtvsrd", // PPC_INS_MTVSRD, - "mtvsrdd", // PPC_INS_MTVSRDD, - "mtvsrwa", // PPC_INS_MTVSRWA, - "mtvsrws", // PPC_INS_MTVSRWS, - "mtvsrwz", // PPC_INS_MTVSRWZ, - "mtxer", // PPC_INS_MTXER, - "mulhd", // PPC_INS_MULHD, - "mulhdu", // PPC_INS_MULHDU, - "mulhw", // PPC_INS_MULHW, - "mulhwu", // PPC_INS_MULHWU, - "mulld", // PPC_INS_MULLD, - "mulli", // PPC_INS_MULLI, - "mullw", // PPC_INS_MULLW, - "nand", // PPC_INS_NAND, - "nap", // PPC_INS_NAP, - "neg", // PPC_INS_NEG, - "nop", // PPC_INS_NOP, - "nor", // PPC_INS_NOR, - "not", // PPC_INS_NOT, - "or", // PPC_INS_OR, - "orc", // PPC_INS_ORC, - "ori", // PPC_INS_ORI, - "oris", // PPC_INS_ORIS, - "paste", // PPC_INS_PASTE, - "paste_last", // PPC_INS_PASTE_LAST, - "popcntb", // PPC_INS_POPCNTB, - "popcntd", // PPC_INS_POPCNTD, - "popcntw", // PPC_INS_POPCNTW, - "ptesync", // PPC_INS_PTESYNC, - "qvaligni", // PPC_INS_QVALIGNI, - "qvesplati", // PPC_INS_QVESPLATI, - "qvfabs", // PPC_INS_QVFABS, - "qvfadd", // PPC_INS_QVFADD, - "qvfadds", // PPC_INS_QVFADDS, - "qvfand", // PPC_INS_QVFAND, - "qvfandc", // PPC_INS_QVFANDC, - "qvfcfid", // PPC_INS_QVFCFID, - "qvfcfids", // PPC_INS_QVFCFIDS, - "qvfcfidu", // PPC_INS_QVFCFIDU, - "qvfcfidus", // PPC_INS_QVFCFIDUS, - "qvfclr", // PPC_INS_QVFCLR, - "qvfcmpeq", // PPC_INS_QVFCMPEQ, - "qvfcmpgt", // PPC_INS_QVFCMPGT, - "qvfcmplt", // PPC_INS_QVFCMPLT, - "qvfcpsgn", // PPC_INS_QVFCPSGN, - "qvfctfb", // PPC_INS_QVFCTFB, - "qvfctid", // PPC_INS_QVFCTID, - "qvfctidu", // PPC_INS_QVFCTIDU, - "qvfctiduz", // PPC_INS_QVFCTIDUZ, - "qvfctidz", // PPC_INS_QVFCTIDZ, - "qvfctiw", // PPC_INS_QVFCTIW, - "qvfctiwu", // PPC_INS_QVFCTIWU, - "qvfctiwuz", // PPC_INS_QVFCTIWUZ, - "qvfctiwz", // PPC_INS_QVFCTIWZ, - "qvfequ", // PPC_INS_QVFEQU, - "qvflogical", // PPC_INS_QVFLOGICAL, - "qvfmadd", // PPC_INS_QVFMADD, - "qvfmadds", // PPC_INS_QVFMADDS, - "qvfmr", // PPC_INS_QVFMR, - "qvfmsub", // PPC_INS_QVFMSUB, - "qvfmsubs", // PPC_INS_QVFMSUBS, - "qvfmul", // PPC_INS_QVFMUL, - "qvfmuls", // PPC_INS_QVFMULS, - "qvfnabs", // PPC_INS_QVFNABS, - "qvfnand", // PPC_INS_QVFNAND, - "qvfneg", // PPC_INS_QVFNEG, - "qvfnmadd", // PPC_INS_QVFNMADD, - "qvfnmadds", // PPC_INS_QVFNMADDS, - "qvfnmsub", // PPC_INS_QVFNMSUB, - "qvfnmsubs", // PPC_INS_QVFNMSUBS, - "qvfnor", // PPC_INS_QVFNOR, - "qvfnot", // PPC_INS_QVFNOT, - "qvfor", // PPC_INS_QVFOR, - "qvforc", // PPC_INS_QVFORC, - "qvfperm", // PPC_INS_QVFPERM, - "qvfre", // PPC_INS_QVFRE, - "qvfres", // PPC_INS_QVFRES, - "qvfrim", // PPC_INS_QVFRIM, - "qvfrin", // PPC_INS_QVFRIN, - "qvfrip", // PPC_INS_QVFRIP, - "qvfriz", // PPC_INS_QVFRIZ, - "qvfrsp", // PPC_INS_QVFRSP, - "qvfrsqrte", // PPC_INS_QVFRSQRTE, - "qvfrsqrtes", // PPC_INS_QVFRSQRTES, - "qvfsel", // PPC_INS_QVFSEL, - "qvfset", // PPC_INS_QVFSET, - "qvfsub", // PPC_INS_QVFSUB, - "qvfsubs", // PPC_INS_QVFSUBS, - "qvftstnan", // PPC_INS_QVFTSTNAN, - "qvfxmadd", // PPC_INS_QVFXMADD, - "qvfxmadds", // PPC_INS_QVFXMADDS, - "qvfxmul", // PPC_INS_QVFXMUL, - "qvfxmuls", // PPC_INS_QVFXMULS, - "qvfxor", // PPC_INS_QVFXOR, - "qvfxxcpnmadd", // PPC_INS_QVFXXCPNMADD, - "qvfxxcpnmadds", // PPC_INS_QVFXXCPNMADDS, - "qvfxxmadd", // PPC_INS_QVFXXMADD, - "qvfxxmadds", // PPC_INS_QVFXXMADDS, - "qvfxxnpmadd", // PPC_INS_QVFXXNPMADD, - "qvfxxnpmadds", // PPC_INS_QVFXXNPMADDS, - "qvgpci", // PPC_INS_QVGPCI, - "qvlfcdux", // PPC_INS_QVLFCDUX, - "qvlfcduxa", // PPC_INS_QVLFCDUXA, - "qvlfcdx", // PPC_INS_QVLFCDX, - "qvlfcdxa", // PPC_INS_QVLFCDXA, - "qvlfcsux", // PPC_INS_QVLFCSUX, - "qvlfcsuxa", // PPC_INS_QVLFCSUXA, - "qvlfcsx", // PPC_INS_QVLFCSX, - "qvlfcsxa", // PPC_INS_QVLFCSXA, - "qvlfdux", // PPC_INS_QVLFDUX, - "qvlfduxa", // PPC_INS_QVLFDUXA, - "qvlfdx", // PPC_INS_QVLFDX, - "qvlfdxa", // PPC_INS_QVLFDXA, - "qvlfiwax", // PPC_INS_QVLFIWAX, - "qvlfiwaxa", // PPC_INS_QVLFIWAXA, - "qvlfiwzx", // PPC_INS_QVLFIWZX, - "qvlfiwzxa", // PPC_INS_QVLFIWZXA, - "qvlfsux", // PPC_INS_QVLFSUX, - "qvlfsuxa", // PPC_INS_QVLFSUXA, - "qvlfsx", // PPC_INS_QVLFSX, - "qvlfsxa", // PPC_INS_QVLFSXA, - "qvlpcldx", // PPC_INS_QVLPCLDX, - "qvlpclsx", // PPC_INS_QVLPCLSX, - "qvlpcrdx", // PPC_INS_QVLPCRDX, - "qvlpcrsx", // PPC_INS_QVLPCRSX, - "qvstfcdux", // PPC_INS_QVSTFCDUX, - "qvstfcduxa", // PPC_INS_QVSTFCDUXA, - "qvstfcduxi", // PPC_INS_QVSTFCDUXI, - "qvstfcduxia", // PPC_INS_QVSTFCDUXIA, - "qvstfcdx", // PPC_INS_QVSTFCDX, - "qvstfcdxa", // PPC_INS_QVSTFCDXA, - "qvstfcdxi", // PPC_INS_QVSTFCDXI, - "qvstfcdxia", // PPC_INS_QVSTFCDXIA, - "qvstfcsux", // PPC_INS_QVSTFCSUX, - "qvstfcsuxa", // PPC_INS_QVSTFCSUXA, - "qvstfcsuxi", // PPC_INS_QVSTFCSUXI, - "qvstfcsuxia", // PPC_INS_QVSTFCSUXIA, - "qvstfcsx", // PPC_INS_QVSTFCSX, - "qvstfcsxa", // PPC_INS_QVSTFCSXA, - "qvstfcsxi", // PPC_INS_QVSTFCSXI, - "qvstfcsxia", // PPC_INS_QVSTFCSXIA, - "qvstfdux", // PPC_INS_QVSTFDUX, - "qvstfduxa", // PPC_INS_QVSTFDUXA, - "qvstfduxi", // PPC_INS_QVSTFDUXI, - "qvstfduxia", // PPC_INS_QVSTFDUXIA, - "qvstfdx", // PPC_INS_QVSTFDX, - "qvstfdxa", // PPC_INS_QVSTFDXA, - "qvstfdxi", // PPC_INS_QVSTFDXI, - "qvstfdxia", // PPC_INS_QVSTFDXIA, - "qvstfiwx", // PPC_INS_QVSTFIWX, - "qvstfiwxa", // PPC_INS_QVSTFIWXA, - "qvstfsux", // PPC_INS_QVSTFSUX, - "qvstfsuxa", // PPC_INS_QVSTFSUXA, - "qvstfsuxi", // PPC_INS_QVSTFSUXI, - "qvstfsuxia", // PPC_INS_QVSTFSUXIA, - "qvstfsx", // PPC_INS_QVSTFSX, - "qvstfsxa", // PPC_INS_QVSTFSXA, - "qvstfsxi", // PPC_INS_QVSTFSXI, - "qvstfsxia", // PPC_INS_QVSTFSXIA, - "rfci", // PPC_INS_RFCI, - "rfdi", // PPC_INS_RFDI, - "rfebb", // PPC_INS_RFEBB, - "rfi", // PPC_INS_RFI, - "rfid", // PPC_INS_RFID, - "rfmci", // PPC_INS_RFMCI, - "rldcl", // PPC_INS_RLDCL, - "rldcr", // PPC_INS_RLDCR, - "rldic", // PPC_INS_RLDIC, - "rldicl", // PPC_INS_RLDICL, - "rldicr", // PPC_INS_RLDICR, - "rldimi", // PPC_INS_RLDIMI, - "rlwimi", // PPC_INS_RLWIMI, - "rlwinm", // PPC_INS_RLWINM, - "rlwnm", // PPC_INS_RLWNM, - "rotld", // PPC_INS_ROTLD, - "rotldi", // PPC_INS_ROTLDI, - "rotlw", // PPC_INS_ROTLW, - "rotlwi", // PPC_INS_ROTLWI, - "rotrdi", // PPC_INS_ROTRDI, - "rotrwi", // PPC_INS_ROTRWI, - "sc", // PPC_INS_SC, - "setb", // PPC_INS_SETB, - "slbia", // PPC_INS_SLBIA, - "slbie", // PPC_INS_SLBIE, - "slbieg", // PPC_INS_SLBIEG, - "slbmfee", // PPC_INS_SLBMFEE, - "slbmfev", // PPC_INS_SLBMFEV, - "slbmte", // PPC_INS_SLBMTE, - "slbsync", // PPC_INS_SLBSYNC, - "sld", // PPC_INS_SLD, - "sldi", // PPC_INS_SLDI, - "slw", // PPC_INS_SLW, - "slwi", // PPC_INS_SLWI, - "srad", // PPC_INS_SRAD, - "sradi", // PPC_INS_SRADI, - "sraw", // PPC_INS_SRAW, - "srawi", // PPC_INS_SRAWI, - "srd", // PPC_INS_SRD, - "srdi", // PPC_INS_SRDI, - "srw", // PPC_INS_SRW, - "srwi", // PPC_INS_SRWI, - "stb", // PPC_INS_STB, - "stbcix", // PPC_INS_STBCIX, - "stbcx", // PPC_INS_STBCX, - "stbepx", // PPC_INS_STBEPX, - "stbu", // PPC_INS_STBU, - "stbux", // PPC_INS_STBUX, - "stbx", // PPC_INS_STBX, - "std", // PPC_INS_STD, - "stdat", // PPC_INS_STDAT, - "stdbrx", // PPC_INS_STDBRX, - "stdcix", // PPC_INS_STDCIX, - "stdcx", // PPC_INS_STDCX, - "stdu", // PPC_INS_STDU, - "stdux", // PPC_INS_STDUX, - "stdx", // PPC_INS_STDX, - "stfd", // PPC_INS_STFD, - "stfdepx", // PPC_INS_STFDEPX, - "stfdu", // PPC_INS_STFDU, - "stfdux", // PPC_INS_STFDUX, - "stfdx", // PPC_INS_STFDX, - "stfiwx", // PPC_INS_STFIWX, - "stfs", // PPC_INS_STFS, - "stfsu", // PPC_INS_STFSU, - "stfsux", // PPC_INS_STFSUX, - "stfsx", // PPC_INS_STFSX, - "sth", // PPC_INS_STH, - "sthbrx", // PPC_INS_STHBRX, - "sthcix", // PPC_INS_STHCIX, - "sthcx", // PPC_INS_STHCX, - "sthepx", // PPC_INS_STHEPX, - "sthu", // PPC_INS_STHU, - "sthux", // PPC_INS_STHUX, - "sthx", // PPC_INS_STHX, - "stmw", // PPC_INS_STMW, - "stop", // PPC_INS_STOP, - "stswi", // PPC_INS_STSWI, - "stvebx", // PPC_INS_STVEBX, - "stvehx", // PPC_INS_STVEHX, - "stvewx", // PPC_INS_STVEWX, - "stvx", // PPC_INS_STVX, - "stvxl", // PPC_INS_STVXL, - "stw", // PPC_INS_STW, - "stwat", // PPC_INS_STWAT, - "stwbrx", // PPC_INS_STWBRX, - "stwcix", // PPC_INS_STWCIX, - "stwcx", // PPC_INS_STWCX, - "stwepx", // PPC_INS_STWEPX, - "stwu", // PPC_INS_STWU, - "stwux", // PPC_INS_STWUX, - "stwx", // PPC_INS_STWX, - "stxsd", // PPC_INS_STXSD, - "stxsdx", // PPC_INS_STXSDX, - "stxsibx", // PPC_INS_STXSIBX, - "stxsihx", // PPC_INS_STXSIHX, - "stxsiwx", // PPC_INS_STXSIWX, - "stxssp", // PPC_INS_STXSSP, - "stxsspx", // PPC_INS_STXSSPX, - "stxv", // PPC_INS_STXV, - "stxvb16x", // PPC_INS_STXVB16X, - "stxvd2x", // PPC_INS_STXVD2X, - "stxvh8x", // PPC_INS_STXVH8X, - "stxvl", // PPC_INS_STXVL, - "stxvll", // PPC_INS_STXVLL, - "stxvw4x", // PPC_INS_STXVW4X, - "stxvx", // PPC_INS_STXVX, - "sub", // PPC_INS_SUB, - "subc", // PPC_INS_SUBC, - "subf", // PPC_INS_SUBF, - "subfc", // PPC_INS_SUBFC, - "subfe", // PPC_INS_SUBFE, - "subfic", // PPC_INS_SUBFIC, - "subfme", // PPC_INS_SUBFME, - "subfze", // PPC_INS_SUBFZE, - "subi", // PPC_INS_SUBI, - "subic", // PPC_INS_SUBIC, - "subis", // PPC_INS_SUBIS, - "subpcis", // PPC_INS_SUBPCIS, - "sync", // PPC_INS_SYNC, - "tabort", // PPC_INS_TABORT, - "tabortdc", // PPC_INS_TABORTDC, - "tabortdci", // PPC_INS_TABORTDCI, - "tabortwc", // PPC_INS_TABORTWC, - "tabortwci", // PPC_INS_TABORTWCI, - "tbegin", // PPC_INS_TBEGIN, - "tcheck", // PPC_INS_TCHECK, - "td", // PPC_INS_TD, - "tdeq", // PPC_INS_TDEQ, - "tdeqi", // PPC_INS_TDEQI, - "tdge", // PPC_INS_TDGE, - "tdgei", // PPC_INS_TDGEI, - "tdgt", // PPC_INS_TDGT, - "tdgti", // PPC_INS_TDGTI, - "tdi", // PPC_INS_TDI, - "tdle", // PPC_INS_TDLE, - "tdlei", // PPC_INS_TDLEI, - "tdlge", // PPC_INS_TDLGE, - "tdlgei", // PPC_INS_TDLGEI, - "tdlgt", // PPC_INS_TDLGT, - "tdlgti", // PPC_INS_TDLGTI, - "tdlle", // PPC_INS_TDLLE, - "tdllei", // PPC_INS_TDLLEI, - "tdllt", // PPC_INS_TDLLT, - "tdllti", // PPC_INS_TDLLTI, - "tdlng", // PPC_INS_TDLNG, - "tdlngi", // PPC_INS_TDLNGI, - "tdlnl", // PPC_INS_TDLNL, - "tdlnli", // PPC_INS_TDLNLI, - "tdlt", // PPC_INS_TDLT, - "tdlti", // PPC_INS_TDLTI, - "tdne", // PPC_INS_TDNE, - "tdnei", // PPC_INS_TDNEI, - "tdng", // PPC_INS_TDNG, - "tdngi", // PPC_INS_TDNGI, - "tdnl", // PPC_INS_TDNL, - "tdnli", // PPC_INS_TDNLI, - "tdu", // PPC_INS_TDU, - "tdui", // PPC_INS_TDUI, - "tend", // PPC_INS_TEND, - "tlbia", // PPC_INS_TLBIA, - "tlbie", // PPC_INS_TLBIE, - "tlbiel", // PPC_INS_TLBIEL, - "tlbivax", // PPC_INS_TLBIVAX, - "tlbld", // PPC_INS_TLBLD, - "tlbli", // PPC_INS_TLBLI, - "tlbre", // PPC_INS_TLBRE, - "tlbrehi", // PPC_INS_TLBREHI, - "tlbrelo", // PPC_INS_TLBRELO, - "tlbsx", // PPC_INS_TLBSX, - "tlbsync", // PPC_INS_TLBSYNC, - "tlbwe", // PPC_INS_TLBWE, - "tlbwehi", // PPC_INS_TLBWEHI, - "tlbwelo", // PPC_INS_TLBWELO, - "trap", // PPC_INS_TRAP, - "trechkpt", // PPC_INS_TRECHKPT, - "treclaim", // PPC_INS_TRECLAIM, - "tsr", // PPC_INS_TSR, - "tw", // PPC_INS_TW, - "tweq", // PPC_INS_TWEQ, - "tweqi", // PPC_INS_TWEQI, - "twge", // PPC_INS_TWGE, - "twgei", // PPC_INS_TWGEI, - "twgt", // PPC_INS_TWGT, - "twgti", // PPC_INS_TWGTI, - "twi", // PPC_INS_TWI, - "twle", // PPC_INS_TWLE, - "twlei", // PPC_INS_TWLEI, - "twlge", // PPC_INS_TWLGE, - "twlgei", // PPC_INS_TWLGEI, - "twlgt", // PPC_INS_TWLGT, - "twlgti", // PPC_INS_TWLGTI, - "twlle", // PPC_INS_TWLLE, - "twllei", // PPC_INS_TWLLEI, - "twllt", // PPC_INS_TWLLT, - "twllti", // PPC_INS_TWLLTI, - "twlng", // PPC_INS_TWLNG, - "twlngi", // PPC_INS_TWLNGI, - "twlnl", // PPC_INS_TWLNL, - "twlnli", // PPC_INS_TWLNLI, - "twlt", // PPC_INS_TWLT, - "twlti", // PPC_INS_TWLTI, - "twne", // PPC_INS_TWNE, - "twnei", // PPC_INS_TWNEI, - "twng", // PPC_INS_TWNG, - "twngi", // PPC_INS_TWNGI, - "twnl", // PPC_INS_TWNL, - "twnli", // PPC_INS_TWNLI, - "twu", // PPC_INS_TWU, - "twui", // PPC_INS_TWUI, - "vabsdub", // PPC_INS_VABSDUB, - "vabsduh", // PPC_INS_VABSDUH, - "vabsduw", // PPC_INS_VABSDUW, - "vaddcuq", // PPC_INS_VADDCUQ, - "vaddcuw", // PPC_INS_VADDCUW, - "vaddecuq", // PPC_INS_VADDECUQ, - "vaddeuqm", // PPC_INS_VADDEUQM, - "vaddfp", // PPC_INS_VADDFP, - "vaddsbs", // PPC_INS_VADDSBS, - "vaddshs", // PPC_INS_VADDSHS, - "vaddsws", // PPC_INS_VADDSWS, - "vaddubm", // PPC_INS_VADDUBM, - "vaddubs", // PPC_INS_VADDUBS, - "vaddudm", // PPC_INS_VADDUDM, - "vadduhm", // PPC_INS_VADDUHM, - "vadduhs", // PPC_INS_VADDUHS, - "vadduqm", // PPC_INS_VADDUQM, - "vadduwm", // PPC_INS_VADDUWM, - "vadduws", // PPC_INS_VADDUWS, - "vand", // PPC_INS_VAND, - "vandc", // PPC_INS_VANDC, - "vavgsb", // PPC_INS_VAVGSB, - "vavgsh", // PPC_INS_VAVGSH, - "vavgsw", // PPC_INS_VAVGSW, - "vavgub", // PPC_INS_VAVGUB, - "vavguh", // PPC_INS_VAVGUH, - "vavguw", // PPC_INS_VAVGUW, - "vbpermd", // PPC_INS_VBPERMD, - "vbpermq", // PPC_INS_VBPERMQ, - "vcfsx", // PPC_INS_VCFSX, - "vcfux", // PPC_INS_VCFUX, - "vcipher", // PPC_INS_VCIPHER, - "vcipherlast", // PPC_INS_VCIPHERLAST, - "vclzb", // PPC_INS_VCLZB, - "vclzd", // PPC_INS_VCLZD, - "vclzh", // PPC_INS_VCLZH, - "vclzlsbb", // PPC_INS_VCLZLSBB, - "vclzw", // PPC_INS_VCLZW, - "vcmpbfp", // PPC_INS_VCMPBFP, - "vcmpeqfp", // PPC_INS_VCMPEQFP, - "vcmpequb", // PPC_INS_VCMPEQUB, - "vcmpequd", // PPC_INS_VCMPEQUD, - "vcmpequh", // PPC_INS_VCMPEQUH, - "vcmpequw", // PPC_INS_VCMPEQUW, - "vcmpgefp", // PPC_INS_VCMPGEFP, - "vcmpgtfp", // PPC_INS_VCMPGTFP, - "vcmpgtsb", // PPC_INS_VCMPGTSB, - "vcmpgtsd", // PPC_INS_VCMPGTSD, - "vcmpgtsh", // PPC_INS_VCMPGTSH, - "vcmpgtsw", // PPC_INS_VCMPGTSW, - "vcmpgtub", // PPC_INS_VCMPGTUB, - "vcmpgtud", // PPC_INS_VCMPGTUD, - "vcmpgtuh", // PPC_INS_VCMPGTUH, - "vcmpgtuw", // PPC_INS_VCMPGTUW, - "vcmpneb", // PPC_INS_VCMPNEB, - "vcmpneh", // PPC_INS_VCMPNEH, - "vcmpnew", // PPC_INS_VCMPNEW, - "vcmpnezb", // PPC_INS_VCMPNEZB, - "vcmpnezh", // PPC_INS_VCMPNEZH, - "vcmpnezw", // PPC_INS_VCMPNEZW, - "vctsxs", // PPC_INS_VCTSXS, - "vctuxs", // PPC_INS_VCTUXS, - "vctzb", // PPC_INS_VCTZB, - "vctzd", // PPC_INS_VCTZD, - "vctzh", // PPC_INS_VCTZH, - "vctzlsbb", // PPC_INS_VCTZLSBB, - "vctzw", // PPC_INS_VCTZW, - "veqv", // PPC_INS_VEQV, - "vexptefp", // PPC_INS_VEXPTEFP, - "vextractd", // PPC_INS_VEXTRACTD, - "vextractub", // PPC_INS_VEXTRACTUB, - "vextractuh", // PPC_INS_VEXTRACTUH, - "vextractuw", // PPC_INS_VEXTRACTUW, - "vextsb2d", // PPC_INS_VEXTSB2D, - "vextsb2w", // PPC_INS_VEXTSB2W, - "vextsh2d", // PPC_INS_VEXTSH2D, - "vextsh2w", // PPC_INS_VEXTSH2W, - "vextsw2d", // PPC_INS_VEXTSW2D, - "vextublx", // PPC_INS_VEXTUBLX, - "vextubrx", // PPC_INS_VEXTUBRX, - "vextuhlx", // PPC_INS_VEXTUHLX, - "vextuhrx", // PPC_INS_VEXTUHRX, - "vextuwlx", // PPC_INS_VEXTUWLX, - "vextuwrx", // PPC_INS_VEXTUWRX, - "vgbbd", // PPC_INS_VGBBD, - "vinsertb", // PPC_INS_VINSERTB, - "vinsertd", // PPC_INS_VINSERTD, - "vinserth", // PPC_INS_VINSERTH, - "vinsertw", // PPC_INS_VINSERTW, - "vlogefp", // PPC_INS_VLOGEFP, - "vmaddfp", // PPC_INS_VMADDFP, - "vmaxfp", // PPC_INS_VMAXFP, - "vmaxsb", // PPC_INS_VMAXSB, - "vmaxsd", // PPC_INS_VMAXSD, - "vmaxsh", // PPC_INS_VMAXSH, - "vmaxsw", // PPC_INS_VMAXSW, - "vmaxub", // PPC_INS_VMAXUB, - "vmaxud", // PPC_INS_VMAXUD, - "vmaxuh", // PPC_INS_VMAXUH, - "vmaxuw", // PPC_INS_VMAXUW, - "vmhaddshs", // PPC_INS_VMHADDSHS, - "vmhraddshs", // PPC_INS_VMHRADDSHS, - "vminfp", // PPC_INS_VMINFP, - "vminsb", // PPC_INS_VMINSB, - "vminsd", // PPC_INS_VMINSD, - "vminsh", // PPC_INS_VMINSH, - "vminsw", // PPC_INS_VMINSW, - "vminub", // PPC_INS_VMINUB, - "vminud", // PPC_INS_VMINUD, - "vminuh", // PPC_INS_VMINUH, - "vminuw", // PPC_INS_VMINUW, - "vmladduhm", // PPC_INS_VMLADDUHM, - "vmr", // PPC_INS_VMR, - "vmrgew", // PPC_INS_VMRGEW, - "vmrghb", // PPC_INS_VMRGHB, - "vmrghh", // PPC_INS_VMRGHH, - "vmrghw", // PPC_INS_VMRGHW, - "vmrglb", // PPC_INS_VMRGLB, - "vmrglh", // PPC_INS_VMRGLH, - "vmrglw", // PPC_INS_VMRGLW, - "vmrgow", // PPC_INS_VMRGOW, - "vmsummbm", // PPC_INS_VMSUMMBM, - "vmsumshm", // PPC_INS_VMSUMSHM, - "vmsumshs", // PPC_INS_VMSUMSHS, - "vmsumubm", // PPC_INS_VMSUMUBM, - "vmsumuhm", // PPC_INS_VMSUMUHM, - "vmsumuhs", // PPC_INS_VMSUMUHS, - "vmul10cuq", // PPC_INS_VMUL10CUQ, - "vmul10ecuq", // PPC_INS_VMUL10ECUQ, - "vmul10euq", // PPC_INS_VMUL10EUQ, - "vmul10uq", // PPC_INS_VMUL10UQ, - "vmulesb", // PPC_INS_VMULESB, - "vmulesh", // PPC_INS_VMULESH, - "vmulesw", // PPC_INS_VMULESW, - "vmuleub", // PPC_INS_VMULEUB, - "vmuleuh", // PPC_INS_VMULEUH, - "vmuleuw", // PPC_INS_VMULEUW, - "vmulosb", // PPC_INS_VMULOSB, - "vmulosh", // PPC_INS_VMULOSH, - "vmulosw", // PPC_INS_VMULOSW, - "vmuloub", // PPC_INS_VMULOUB, - "vmulouh", // PPC_INS_VMULOUH, - "vmulouw", // PPC_INS_VMULOUW, - "vmuluwm", // PPC_INS_VMULUWM, - "vnand", // PPC_INS_VNAND, - "vncipher", // PPC_INS_VNCIPHER, - "vncipherlast", // PPC_INS_VNCIPHERLAST, - "vnegd", // PPC_INS_VNEGD, - "vnegw", // PPC_INS_VNEGW, - "vnmsubfp", // PPC_INS_VNMSUBFP, - "vnor", // PPC_INS_VNOR, - "vnot", // PPC_INS_VNOT, - "vor", // PPC_INS_VOR, - "vorc", // PPC_INS_VORC, - "vperm", // PPC_INS_VPERM, - "vpermr", // PPC_INS_VPERMR, - "vpermxor", // PPC_INS_VPERMXOR, - "vpkpx", // PPC_INS_VPKPX, - "vpksdss", // PPC_INS_VPKSDSS, - "vpksdus", // PPC_INS_VPKSDUS, - "vpkshss", // PPC_INS_VPKSHSS, - "vpkshus", // PPC_INS_VPKSHUS, - "vpkswss", // PPC_INS_VPKSWSS, - "vpkswus", // PPC_INS_VPKSWUS, - "vpkudum", // PPC_INS_VPKUDUM, - "vpkudus", // PPC_INS_VPKUDUS, - "vpkuhum", // PPC_INS_VPKUHUM, - "vpkuhus", // PPC_INS_VPKUHUS, - "vpkuwum", // PPC_INS_VPKUWUM, - "vpkuwus", // PPC_INS_VPKUWUS, - "vpmsumb", // PPC_INS_VPMSUMB, - "vpmsumd", // PPC_INS_VPMSUMD, - "vpmsumh", // PPC_INS_VPMSUMH, - "vpmsumw", // PPC_INS_VPMSUMW, - "vpopcntb", // PPC_INS_VPOPCNTB, - "vpopcntd", // PPC_INS_VPOPCNTD, - "vpopcnth", // PPC_INS_VPOPCNTH, - "vpopcntw", // PPC_INS_VPOPCNTW, - "vprtybd", // PPC_INS_VPRTYBD, - "vprtybq", // PPC_INS_VPRTYBQ, - "vprtybw", // PPC_INS_VPRTYBW, - "vrefp", // PPC_INS_VREFP, - "vrfim", // PPC_INS_VRFIM, - "vrfin", // PPC_INS_VRFIN, - "vrfip", // PPC_INS_VRFIP, - "vrfiz", // PPC_INS_VRFIZ, - "vrlb", // PPC_INS_VRLB, - "vrld", // PPC_INS_VRLD, - "vrldmi", // PPC_INS_VRLDMI, - "vrldnm", // PPC_INS_VRLDNM, - "vrlh", // PPC_INS_VRLH, - "vrlw", // PPC_INS_VRLW, - "vrlwmi", // PPC_INS_VRLWMI, - "vrlwnm", // PPC_INS_VRLWNM, - "vrsqrtefp", // PPC_INS_VRSQRTEFP, - "vsbox", // PPC_INS_VSBOX, - "vsel", // PPC_INS_VSEL, - "vshasigmad", // PPC_INS_VSHASIGMAD, - "vshasigmaw", // PPC_INS_VSHASIGMAW, - "vsl", // PPC_INS_VSL, - "vslb", // PPC_INS_VSLB, - "vsld", // PPC_INS_VSLD, - "vsldoi", // PPC_INS_VSLDOI, - "vslh", // PPC_INS_VSLH, - "vslo", // PPC_INS_VSLO, - "vslv", // PPC_INS_VSLV, - "vslw", // PPC_INS_VSLW, - "vspltb", // PPC_INS_VSPLTB, - "vsplth", // PPC_INS_VSPLTH, - "vspltisb", // PPC_INS_VSPLTISB, - "vspltish", // PPC_INS_VSPLTISH, - "vspltisw", // PPC_INS_VSPLTISW, - "vspltw", // PPC_INS_VSPLTW, - "vsr", // PPC_INS_VSR, - "vsrab", // PPC_INS_VSRAB, - "vsrad", // PPC_INS_VSRAD, - "vsrah", // PPC_INS_VSRAH, - "vsraw", // PPC_INS_VSRAW, - "vsrb", // PPC_INS_VSRB, - "vsrd", // PPC_INS_VSRD, - "vsrh", // PPC_INS_VSRH, - "vsro", // PPC_INS_VSRO, - "vsrv", // PPC_INS_VSRV, - "vsrw", // PPC_INS_VSRW, - "vsubcuq", // PPC_INS_VSUBCUQ, - "vsubcuw", // PPC_INS_VSUBCUW, - "vsubecuq", // PPC_INS_VSUBECUQ, - "vsubeuqm", // PPC_INS_VSUBEUQM, - "vsubfp", // PPC_INS_VSUBFP, - "vsubsbs", // PPC_INS_VSUBSBS, - "vsubshs", // PPC_INS_VSUBSHS, - "vsubsws", // PPC_INS_VSUBSWS, - "vsububm", // PPC_INS_VSUBUBM, - "vsububs", // PPC_INS_VSUBUBS, - "vsubudm", // PPC_INS_VSUBUDM, - "vsubuhm", // PPC_INS_VSUBUHM, - "vsubuhs", // PPC_INS_VSUBUHS, - "vsubuqm", // PPC_INS_VSUBUQM, - "vsubuwm", // PPC_INS_VSUBUWM, - "vsubuws", // PPC_INS_VSUBUWS, - "vsum2sws", // PPC_INS_VSUM2SWS, - "vsum4sbs", // PPC_INS_VSUM4SBS, - "vsum4shs", // PPC_INS_VSUM4SHS, - "vsum4ubs", // PPC_INS_VSUM4UBS, - "vsumsws", // PPC_INS_VSUMSWS, - "vupkhpx", // PPC_INS_VUPKHPX, - "vupkhsb", // PPC_INS_VUPKHSB, - "vupkhsh", // PPC_INS_VUPKHSH, - "vupkhsw", // PPC_INS_VUPKHSW, - "vupklpx", // PPC_INS_VUPKLPX, - "vupklsb", // PPC_INS_VUPKLSB, - "vupklsh", // PPC_INS_VUPKLSH, - "vupklsw", // PPC_INS_VUPKLSW, - "vxor", // PPC_INS_VXOR, - "wait", // PPC_INS_WAIT, - "waitimpl", // PPC_INS_WAITIMPL, - "waitrsv", // PPC_INS_WAITRSV, - "wrtee", // PPC_INS_WRTEE, - "wrteei", // PPC_INS_WRTEEI, - "xnop", // PPC_INS_XNOP, - "xor", // PPC_INS_XOR, - "xori", // PPC_INS_XORI, - "xoris", // PPC_INS_XORIS, - "xsabsdp", // PPC_INS_XSABSDP, - "xsabsqp", // PPC_INS_XSABSQP, - "xsadddp", // PPC_INS_XSADDDP, - "xsaddqp", // PPC_INS_XSADDQP, - "xsaddqpo", // PPC_INS_XSADDQPO, - "xsaddsp", // PPC_INS_XSADDSP, - "xscmpeqdp", // PPC_INS_XSCMPEQDP, - "xscmpexpdp", // PPC_INS_XSCMPEXPDP, - "xscmpexpqp", // PPC_INS_XSCMPEXPQP, - "xscmpgedp", // PPC_INS_XSCMPGEDP, - "xscmpgtdp", // PPC_INS_XSCMPGTDP, - "xscmpodp", // PPC_INS_XSCMPODP, - "xscmpoqp", // PPC_INS_XSCMPOQP, - "xscmpudp", // PPC_INS_XSCMPUDP, - "xscmpuqp", // PPC_INS_XSCMPUQP, - "xscpsgndp", // PPC_INS_XSCPSGNDP, - "xscpsgnqp", // PPC_INS_XSCPSGNQP, - "xscvdphp", // PPC_INS_XSCVDPHP, - "xscvdpqp", // PPC_INS_XSCVDPQP, - "xscvdpsp", // PPC_INS_XSCVDPSP, - "xscvdpspn", // PPC_INS_XSCVDPSPN, - "xscvdpsxds", // PPC_INS_XSCVDPSXDS, - "xscvdpsxws", // PPC_INS_XSCVDPSXWS, - "xscvdpuxds", // PPC_INS_XSCVDPUXDS, - "xscvdpuxws", // PPC_INS_XSCVDPUXWS, - "xscvhpdp", // PPC_INS_XSCVHPDP, - "xscvqpdp", // PPC_INS_XSCVQPDP, - "xscvqpdpo", // PPC_INS_XSCVQPDPO, - "xscvqpsdz", // PPC_INS_XSCVQPSDZ, - "xscvqpswz", // PPC_INS_XSCVQPSWZ, - "xscvqpudz", // PPC_INS_XSCVQPUDZ, - "xscvqpuwz", // PPC_INS_XSCVQPUWZ, - "xscvsdqp", // PPC_INS_XSCVSDQP, - "xscvspdp", // PPC_INS_XSCVSPDP, - "xscvspdpn", // PPC_INS_XSCVSPDPN, - "xscvsxddp", // PPC_INS_XSCVSXDDP, - "xscvsxdsp", // PPC_INS_XSCVSXDSP, - "xscvudqp", // PPC_INS_XSCVUDQP, - "xscvuxddp", // PPC_INS_XSCVUXDDP, - "xscvuxdsp", // PPC_INS_XSCVUXDSP, - "xsdivdp", // PPC_INS_XSDIVDP, - "xsdivqp", // PPC_INS_XSDIVQP, - "xsdivqpo", // PPC_INS_XSDIVQPO, - "xsdivsp", // PPC_INS_XSDIVSP, - "xsiexpdp", // PPC_INS_XSIEXPDP, - "xsiexpqp", // PPC_INS_XSIEXPQP, - "xsmaddadp", // PPC_INS_XSMADDADP, - "xsmaddasp", // PPC_INS_XSMADDASP, - "xsmaddmdp", // PPC_INS_XSMADDMDP, - "xsmaddmsp", // PPC_INS_XSMADDMSP, - "xsmaddqp", // PPC_INS_XSMADDQP, - "xsmaddqpo", // PPC_INS_XSMADDQPO, - "xsmaxcdp", // PPC_INS_XSMAXCDP, - "xsmaxdp", // PPC_INS_XSMAXDP, - "xsmaxjdp", // PPC_INS_XSMAXJDP, - "xsmincdp", // PPC_INS_XSMINCDP, - "xsmindp", // PPC_INS_XSMINDP, - "xsminjdp", // PPC_INS_XSMINJDP, - "xsmsubadp", // PPC_INS_XSMSUBADP, - "xsmsubasp", // PPC_INS_XSMSUBASP, - "xsmsubmdp", // PPC_INS_XSMSUBMDP, - "xsmsubmsp", // PPC_INS_XSMSUBMSP, - "xsmsubqp", // PPC_INS_XSMSUBQP, - "xsmsubqpo", // PPC_INS_XSMSUBQPO, - "xsmuldp", // PPC_INS_XSMULDP, - "xsmulqp", // PPC_INS_XSMULQP, - "xsmulqpo", // PPC_INS_XSMULQPO, - "xsmulsp", // PPC_INS_XSMULSP, - "xsnabsdp", // PPC_INS_XSNABSDP, - "xsnabsqp", // PPC_INS_XSNABSQP, - "xsnegdp", // PPC_INS_XSNEGDP, - "xsnegqp", // PPC_INS_XSNEGQP, - "xsnmaddadp", // PPC_INS_XSNMADDADP, - "xsnmaddasp", // PPC_INS_XSNMADDASP, - "xsnmaddmdp", // PPC_INS_XSNMADDMDP, - "xsnmaddmsp", // PPC_INS_XSNMADDMSP, - "xsnmaddqp", // PPC_INS_XSNMADDQP, - "xsnmaddqpo", // PPC_INS_XSNMADDQPO, - "xsnmsubadp", // PPC_INS_XSNMSUBADP, - "xsnmsubasp", // PPC_INS_XSNMSUBASP, - "xsnmsubmdp", // PPC_INS_XSNMSUBMDP, - "xsnmsubmsp", // PPC_INS_XSNMSUBMSP, - "xsnmsubqp", // PPC_INS_XSNMSUBQP, - "xsnmsubqpo", // PPC_INS_XSNMSUBQPO, - "xsrdpi", // PPC_INS_XSRDPI, - "xsrdpic", // PPC_INS_XSRDPIC, - "xsrdpim", // PPC_INS_XSRDPIM, - "xsrdpip", // PPC_INS_XSRDPIP, - "xsrdpiz", // PPC_INS_XSRDPIZ, - "xsredp", // PPC_INS_XSREDP, - "xsresp", // PPC_INS_XSRESP, - "xsrqpi", // PPC_INS_XSRQPI, - "xsrqpix", // PPC_INS_XSRQPIX, - "xsrqpxp", // PPC_INS_XSRQPXP, - "xsrsp", // PPC_INS_XSRSP, - "xsrsqrtedp", // PPC_INS_XSRSQRTEDP, - "xsrsqrtesp", // PPC_INS_XSRSQRTESP, - "xssqrtdp", // PPC_INS_XSSQRTDP, - "xssqrtqp", // PPC_INS_XSSQRTQP, - "xssqrtqpo", // PPC_INS_XSSQRTQPO, - "xssqrtsp", // PPC_INS_XSSQRTSP, - "xssubdp", // PPC_INS_XSSUBDP, - "xssubqp", // PPC_INS_XSSUBQP, - "xssubqpo", // PPC_INS_XSSUBQPO, - "xssubsp", // PPC_INS_XSSUBSP, - "xstdivdp", // PPC_INS_XSTDIVDP, - "xstsqrtdp", // PPC_INS_XSTSQRTDP, - "xststdcdp", // PPC_INS_XSTSTDCDP, - "xststdcqp", // PPC_INS_XSTSTDCQP, - "xststdcsp", // PPC_INS_XSTSTDCSP, - "xsxexpdp", // PPC_INS_XSXEXPDP, - "xsxexpqp", // PPC_INS_XSXEXPQP, - "xsxsigdp", // PPC_INS_XSXSIGDP, - "xsxsigqp", // PPC_INS_XSXSIGQP, - "xvabsdp", // PPC_INS_XVABSDP, - "xvabssp", // PPC_INS_XVABSSP, - "xvadddp", // PPC_INS_XVADDDP, - "xvaddsp", // PPC_INS_XVADDSP, - "xvcmpeqdp", // PPC_INS_XVCMPEQDP, - "xvcmpeqsp", // PPC_INS_XVCMPEQSP, - "xvcmpgedp", // PPC_INS_XVCMPGEDP, - "xvcmpgesp", // PPC_INS_XVCMPGESP, - "xvcmpgtdp", // PPC_INS_XVCMPGTDP, - "xvcmpgtsp", // PPC_INS_XVCMPGTSP, - "xvcpsgndp", // PPC_INS_XVCPSGNDP, - "xvcpsgnsp", // PPC_INS_XVCPSGNSP, - "xvcvdpsp", // PPC_INS_XVCVDPSP, - "xvcvdpsxds", // PPC_INS_XVCVDPSXDS, - "xvcvdpsxws", // PPC_INS_XVCVDPSXWS, - "xvcvdpuxds", // PPC_INS_XVCVDPUXDS, - "xvcvdpuxws", // PPC_INS_XVCVDPUXWS, - "xvcvhpsp", // PPC_INS_XVCVHPSP, - "xvcvspdp", // PPC_INS_XVCVSPDP, - "xvcvsphp", // PPC_INS_XVCVSPHP, - "xvcvspsxds", // PPC_INS_XVCVSPSXDS, - "xvcvspsxws", // PPC_INS_XVCVSPSXWS, - "xvcvspuxds", // PPC_INS_XVCVSPUXDS, - "xvcvspuxws", // PPC_INS_XVCVSPUXWS, - "xvcvsxddp", // PPC_INS_XVCVSXDDP, - "xvcvsxdsp", // PPC_INS_XVCVSXDSP, - "xvcvsxwdp", // PPC_INS_XVCVSXWDP, - "xvcvsxwsp", // PPC_INS_XVCVSXWSP, - "xvcvuxddp", // PPC_INS_XVCVUXDDP, - "xvcvuxdsp", // PPC_INS_XVCVUXDSP, - "xvcvuxwdp", // PPC_INS_XVCVUXWDP, - "xvcvuxwsp", // PPC_INS_XVCVUXWSP, - "xvdivdp", // PPC_INS_XVDIVDP, - "xvdivsp", // PPC_INS_XVDIVSP, - "xviexpdp", // PPC_INS_XVIEXPDP, - "xviexpsp", // PPC_INS_XVIEXPSP, - "xvmaddadp", // PPC_INS_XVMADDADP, - "xvmaddasp", // PPC_INS_XVMADDASP, - "xvmaddmdp", // PPC_INS_XVMADDMDP, - "xvmaddmsp", // PPC_INS_XVMADDMSP, - "xvmaxdp", // PPC_INS_XVMAXDP, - "xvmaxsp", // PPC_INS_XVMAXSP, - "xvmindp", // PPC_INS_XVMINDP, - "xvminsp", // PPC_INS_XVMINSP, - "xvmovdp", // PPC_INS_XVMOVDP, - "xvmovsp", // PPC_INS_XVMOVSP, - "xvmsubadp", // PPC_INS_XVMSUBADP, - "xvmsubasp", // PPC_INS_XVMSUBASP, - "xvmsubmdp", // PPC_INS_XVMSUBMDP, - "xvmsubmsp", // PPC_INS_XVMSUBMSP, - "xvmuldp", // PPC_INS_XVMULDP, - "xvmulsp", // PPC_INS_XVMULSP, - "xvnabsdp", // PPC_INS_XVNABSDP, - "xvnabssp", // PPC_INS_XVNABSSP, - "xvnegdp", // PPC_INS_XVNEGDP, - "xvnegsp", // PPC_INS_XVNEGSP, - "xvnmaddadp", // PPC_INS_XVNMADDADP, - "xvnmaddasp", // PPC_INS_XVNMADDASP, - "xvnmaddmdp", // PPC_INS_XVNMADDMDP, - "xvnmaddmsp", // PPC_INS_XVNMADDMSP, - "xvnmsubadp", // PPC_INS_XVNMSUBADP, - "xvnmsubasp", // PPC_INS_XVNMSUBASP, - "xvnmsubmdp", // PPC_INS_XVNMSUBMDP, - "xvnmsubmsp", // PPC_INS_XVNMSUBMSP, - "xvrdpi", // PPC_INS_XVRDPI, - "xvrdpic", // PPC_INS_XVRDPIC, - "xvrdpim", // PPC_INS_XVRDPIM, - "xvrdpip", // PPC_INS_XVRDPIP, - "xvrdpiz", // PPC_INS_XVRDPIZ, - "xvredp", // PPC_INS_XVREDP, - "xvresp", // PPC_INS_XVRESP, - "xvrspi", // PPC_INS_XVRSPI, - "xvrspic", // PPC_INS_XVRSPIC, - "xvrspim", // PPC_INS_XVRSPIM, - "xvrspip", // PPC_INS_XVRSPIP, - "xvrspiz", // PPC_INS_XVRSPIZ, - "xvrsqrtedp", // PPC_INS_XVRSQRTEDP, - "xvrsqrtesp", // PPC_INS_XVRSQRTESP, - "xvsqrtdp", // PPC_INS_XVSQRTDP, - "xvsqrtsp", // PPC_INS_XVSQRTSP, - "xvsubdp", // PPC_INS_XVSUBDP, - "xvsubsp", // PPC_INS_XVSUBSP, - "xvtdivdp", // PPC_INS_XVTDIVDP, - "xvtdivsp", // PPC_INS_XVTDIVSP, - "xvtsqrtdp", // PPC_INS_XVTSQRTDP, - "xvtsqrtsp", // PPC_INS_XVTSQRTSP, - "xvtstdcdp", // PPC_INS_XVTSTDCDP, - "xvtstdcsp", // PPC_INS_XVTSTDCSP, - "xvxexpdp", // PPC_INS_XVXEXPDP, - "xvxexpsp", // PPC_INS_XVXEXPSP, - "xvxsigdp", // PPC_INS_XVXSIGDP, - "xvxsigsp", // PPC_INS_XVXSIGSP, - "xxbrd", // PPC_INS_XXBRD, - "xxbrh", // PPC_INS_XXBRH, - "xxbrq", // PPC_INS_XXBRQ, - "xxbrw", // PPC_INS_XXBRW, - "xxextractuw", // PPC_INS_XXEXTRACTUW, - "xxinsertw", // PPC_INS_XXINSERTW, - "xxland", // PPC_INS_XXLAND, - "xxlandc", // PPC_INS_XXLANDC, - "xxleqv", // PPC_INS_XXLEQV, - "xxlnand", // PPC_INS_XXLNAND, - "xxlnor", // PPC_INS_XXLNOR, - "xxlor", // PPC_INS_XXLOR, - "xxlorc", // PPC_INS_XXLORC, - "xxlxor", // PPC_INS_XXLXOR, - "xxmrghd", // PPC_INS_XXMRGHD, - "xxmrghw", // PPC_INS_XXMRGHW, - "xxmrgld", // PPC_INS_XXMRGLD, - "xxmrglw", // PPC_INS_XXMRGLW, - "xxperm", // PPC_INS_XXPERM, - "xxpermdi", // PPC_INS_XXPERMDI, - "xxpermr", // PPC_INS_XXPERMR, - "xxsel", // PPC_INS_XXSEL, - "xxsldwi", // PPC_INS_XXSLDWI, - "xxspltd", // PPC_INS_XXSPLTD, - "xxspltib", // PPC_INS_XXSPLTIB, - "xxspltw", // PPC_INS_XXSPLTW, - "xxswapd", // PPC_INS_XXSWAPD, +"add", // PPC_INS_ADD, + "addc", // PPC_INS_ADDC, + "adde", // PPC_INS_ADDE, + "addi", // PPC_INS_ADDI, + "addic", // PPC_INS_ADDIC, + "addis", // PPC_INS_ADDIS, + "addme", // PPC_INS_ADDME, + "addpcis", // PPC_INS_ADDPCIS, + "addze", // PPC_INS_ADDZE, + "and", // PPC_INS_AND, + "andc", // PPC_INS_ANDC, + "andi", // PPC_INS_ANDI, + "andis", // PPC_INS_ANDIS, + "attn", // PPC_INS_ATTN, + "b", // PPC_INS_B, + "ba", // PPC_INS_BA, + "bc", // PPC_INS_BC, + "bca", // PPC_INS_BCA, + "bcctr", // PPC_INS_BCCTR, + "bcctrl", // PPC_INS_BCCTRL, + "bcdcfn", // PPC_INS_BCDCFN, + "bcdcfsq", // PPC_INS_BCDCFSQ, + "bcdcfz", // PPC_INS_BCDCFZ, + "bcdcpsgn", // PPC_INS_BCDCPSGN, + "bcdctn", // PPC_INS_BCDCTN, + "bcdctsq", // PPC_INS_BCDCTSQ, + "bcdctz", // PPC_INS_BCDCTZ, + "bcds", // PPC_INS_BCDS, + "bcdsetsgn", // PPC_INS_BCDSETSGN, + "bcdsr", // PPC_INS_BCDSR, + "bcdtrunc", // PPC_INS_BCDTRUNC, + "bcdus", // PPC_INS_BCDUS, + "bcdutrunc", // PPC_INS_BCDUTRUNC, + "bcl", // PPC_INS_BCL, + "bcla", // PPC_INS_BCLA, + "bclr", // PPC_INS_BCLR, + "bclrl", // PPC_INS_BCLRL, + "bctr", // PPC_INS_BCTR, + "bctrl", // PPC_INS_BCTRL, + "bdnz", // PPC_INS_BDNZ, + "bdnza", // PPC_INS_BDNZA, + "bdnzf", // PPC_INS_BDNZF, + "bdnzfa", // PPC_INS_BDNZFA, + "bdnzfl", // PPC_INS_BDNZFL, + "bdnzfla", // PPC_INS_BDNZFLA, + "bdnzflr", // PPC_INS_BDNZFLR, + "bdnzflrl", // PPC_INS_BDNZFLRL, + "bdnzl", // PPC_INS_BDNZL, + "bdnzla", // PPC_INS_BDNZLA, + "bdnzlr", // PPC_INS_BDNZLR, + "bdnzlrl", // PPC_INS_BDNZLRL, + "bdnzt", // PPC_INS_BDNZT, + "bdnzta", // PPC_INS_BDNZTA, + "bdnztl", // PPC_INS_BDNZTL, + "bdnztla", // PPC_INS_BDNZTLA, + "bdnztlr", // PPC_INS_BDNZTLR, + "bdnztlrl", // PPC_INS_BDNZTLRL, + "bdz", // PPC_INS_BDZ, + "bdza", // PPC_INS_BDZA, + "bdzf", // PPC_INS_BDZF, + "bdzfa", // PPC_INS_BDZFA, + "bdzfl", // PPC_INS_BDZFL, + "bdzfla", // PPC_INS_BDZFLA, + "bdzflr", // PPC_INS_BDZFLR, + "bdzflrl", // PPC_INS_BDZFLRL, + "bdzl", // PPC_INS_BDZL, + "bdzla", // PPC_INS_BDZLA, + "bdzlr", // PPC_INS_BDZLR, + "bdzlrl", // PPC_INS_BDZLRL, + "bdzt", // PPC_INS_BDZT, + "bdzta", // PPC_INS_BDZTA, + "bdztl", // PPC_INS_BDZTL, + "bdztla", // PPC_INS_BDZTLA, + "bdztlr", // PPC_INS_BDZTLR, + "bdztlrl", // PPC_INS_BDZTLRL, + "beq", // PPC_INS_BEQ, + "beqa", // PPC_INS_BEQA, + "beqctr", // PPC_INS_BEQCTR, + "beqctrl", // PPC_INS_BEQCTRL, + "beql", // PPC_INS_BEQL, + "beqla", // PPC_INS_BEQLA, + "beqlr", // PPC_INS_BEQLR, + "beqlrl", // PPC_INS_BEQLRL, + "bf", // PPC_INS_BF, + "bfa", // PPC_INS_BFA, + "bfctr", // PPC_INS_BFCTR, + "bfctrl", // PPC_INS_BFCTRL, + "bfl", // PPC_INS_BFL, + "bfla", // PPC_INS_BFLA, + "bflr", // PPC_INS_BFLR, + "bflrl", // PPC_INS_BFLRL, + "bge", // PPC_INS_BGE, + "bgea", // PPC_INS_BGEA, + "bgectr", // PPC_INS_BGECTR, + "bgectrl", // PPC_INS_BGECTRL, + "bgel", // PPC_INS_BGEL, + "bgela", // PPC_INS_BGELA, + "bgelr", // PPC_INS_BGELR, + "bgelrl", // PPC_INS_BGELRL, + "bgt", // PPC_INS_BGT, + "bgta", // PPC_INS_BGTA, + "bgtctr", // PPC_INS_BGTCTR, + "bgtctrl", // PPC_INS_BGTCTRL, + "bgtl", // PPC_INS_BGTL, + "bgtla", // PPC_INS_BGTLA, + "bgtlr", // PPC_INS_BGTLR, + "bgtlrl", // PPC_INS_BGTLRL, + "bl", // PPC_INS_BL, + "bla", // PPC_INS_BLA, + "ble", // PPC_INS_BLE, + "blea", // PPC_INS_BLEA, + "blectr", // PPC_INS_BLECTR, + "blectrl", // PPC_INS_BLECTRL, + "blel", // PPC_INS_BLEL, + "blela", // PPC_INS_BLELA, + "blelr", // PPC_INS_BLELR, + "blelrl", // PPC_INS_BLELRL, + "blr", // PPC_INS_BLR, + "blrl", // PPC_INS_BLRL, + "blt", // PPC_INS_BLT, + "blta", // PPC_INS_BLTA, + "bltctr", // PPC_INS_BLTCTR, + "bltctrl", // PPC_INS_BLTCTRL, + "bltl", // PPC_INS_BLTL, + "bltla", // PPC_INS_BLTLA, + "bltlr", // PPC_INS_BLTLR, + "bltlrl", // PPC_INS_BLTLRL, + "bne", // PPC_INS_BNE, + "bnea", // PPC_INS_BNEA, + "bnectr", // PPC_INS_BNECTR, + "bnectrl", // PPC_INS_BNECTRL, + "bnel", // PPC_INS_BNEL, + "bnela", // PPC_INS_BNELA, + "bnelr", // PPC_INS_BNELR, + "bnelrl", // PPC_INS_BNELRL, + "bng", // PPC_INS_BNG, + "bnga", // PPC_INS_BNGA, + "bngctr", // PPC_INS_BNGCTR, + "bngctrl", // PPC_INS_BNGCTRL, + "bngl", // PPC_INS_BNGL, + "bngla", // PPC_INS_BNGLA, + "bnglr", // PPC_INS_BNGLR, + "bnglrl", // PPC_INS_BNGLRL, + "bnl", // PPC_INS_BNL, + "bnla", // PPC_INS_BNLA, + "bnlctr", // PPC_INS_BNLCTR, + "bnlctrl", // PPC_INS_BNLCTRL, + "bnll", // PPC_INS_BNLL, + "bnlla", // PPC_INS_BNLLA, + "bnllr", // PPC_INS_BNLLR, + "bnllrl", // PPC_INS_BNLLRL, + "bns", // PPC_INS_BNS, + "bnsa", // PPC_INS_BNSA, + "bnsctr", // PPC_INS_BNSCTR, + "bnsctrl", // PPC_INS_BNSCTRL, + "bnsl", // PPC_INS_BNSL, + "bnsla", // PPC_INS_BNSLA, + "bnslr", // PPC_INS_BNSLR, + "bnslrl", // PPC_INS_BNSLRL, + "bnu", // PPC_INS_BNU, + "bnua", // PPC_INS_BNUA, + "bnuctr", // PPC_INS_BNUCTR, + "bnuctrl", // PPC_INS_BNUCTRL, + "bnul", // PPC_INS_BNUL, + "bnula", // PPC_INS_BNULA, + "bnulr", // PPC_INS_BNULR, + "bnulrl", // PPC_INS_BNULRL, + "bpermd", // PPC_INS_BPERMD, + "brinc", // PPC_INS_BRINC, + "bso", // PPC_INS_BSO, + "bsoa", // PPC_INS_BSOA, + "bsoctr", // PPC_INS_BSOCTR, + "bsoctrl", // PPC_INS_BSOCTRL, + "bsol", // PPC_INS_BSOL, + "bsola", // PPC_INS_BSOLA, + "bsolr", // PPC_INS_BSOLR, + "bsolrl", // PPC_INS_BSOLRL, + "bt", // PPC_INS_BT, + "bta", // PPC_INS_BTA, + "btctr", // PPC_INS_BTCTR, + "btctrl", // PPC_INS_BTCTRL, + "btl", // PPC_INS_BTL, + "btla", // PPC_INS_BTLA, + "btlr", // PPC_INS_BTLR, + "btlrl", // PPC_INS_BTLRL, + "bun", // PPC_INS_BUN, + "buna", // PPC_INS_BUNA, + "bunctr", // PPC_INS_BUNCTR, + "bunctrl", // PPC_INS_BUNCTRL, + "bunl", // PPC_INS_BUNL, + "bunla", // PPC_INS_BUNLA, + "bunlr", // PPC_INS_BUNLR, + "bunlrl", // PPC_INS_BUNLRL, + "clrbhrb", // PPC_INS_CLRBHRB, + "clrldi", // PPC_INS_CLRLDI, + "clrlsldi", // PPC_INS_CLRLSLDI, + "clrlslwi", // PPC_INS_CLRLSLWI, + "clrlwi", // PPC_INS_CLRLWI, + "clrrdi", // PPC_INS_CLRRDI, + "clrrwi", // PPC_INS_CLRRWI, + "cmp", // PPC_INS_CMP, + "cmpb", // PPC_INS_CMPB, + "cmpd", // PPC_INS_CMPD, + "cmpdi", // PPC_INS_CMPDI, + "cmpeqb", // PPC_INS_CMPEQB, + "cmpi", // PPC_INS_CMPI, + "cmpl", // PPC_INS_CMPL, + "cmpld", // PPC_INS_CMPLD, + "cmpldi", // PPC_INS_CMPLDI, + "cmpli", // PPC_INS_CMPLI, + "cmplw", // PPC_INS_CMPLW, + "cmplwi", // PPC_INS_CMPLWI, + "cmprb", // PPC_INS_CMPRB, + "cmpw", // PPC_INS_CMPW, + "cmpwi", // PPC_INS_CMPWI, + "cntlzd", // PPC_INS_CNTLZD, + "cntlzw", // PPC_INS_CNTLZW, + "cnttzd", // PPC_INS_CNTTZD, + "cnttzw", // PPC_INS_CNTTZW, + "copy", // PPC_INS_COPY, + "copy_first", // PPC_INS_COPY_FIRST, + "cp_abort", // PPC_INS_CP_ABORT, + "crand", // PPC_INS_CRAND, + "crandc", // PPC_INS_CRANDC, + "crclr", // PPC_INS_CRCLR, + "creqv", // PPC_INS_CREQV, + "crmove", // PPC_INS_CRMOVE, + "crnand", // PPC_INS_CRNAND, + "crnor", // PPC_INS_CRNOR, + "crnot", // PPC_INS_CRNOT, + "cror", // PPC_INS_CROR, + "crorc", // PPC_INS_CRORC, + "crset", // PPC_INS_CRSET, + "crxor", // PPC_INS_CRXOR, + "darn", // PPC_INS_DARN, + "dcba", // PPC_INS_DCBA, + "dcbf", // PPC_INS_DCBF, + "dcbfep", // PPC_INS_DCBFEP, + "dcbfl", // PPC_INS_DCBFL, + "dcbflp", // PPC_INS_DCBFLP, + "dcbi", // PPC_INS_DCBI, + "dcbst", // PPC_INS_DCBST, + "dcbstep", // PPC_INS_DCBSTEP, + "dcbt", // PPC_INS_DCBT, + "dcbtct", // PPC_INS_DCBTCT, + "dcbtds", // PPC_INS_DCBTDS, + "dcbtep", // PPC_INS_DCBTEP, + "dcbtst", // PPC_INS_DCBTST, + "dcbtstct", // PPC_INS_DCBTSTCT, + "dcbtstds", // PPC_INS_DCBTSTDS, + "dcbtstep", // PPC_INS_DCBTSTEP, + "dcbtstt", // PPC_INS_DCBTSTT, + "dcbtt", // PPC_INS_DCBTT, + "dcbz", // PPC_INS_DCBZ, + "dcbzep", // PPC_INS_DCBZEP, + "dcbzl", // PPC_INS_DCBZL, + "dcbzlep", // PPC_INS_DCBZLEP, + "dccci", // PPC_INS_DCCCI, + "dci", // PPC_INS_DCI, + "divd", // PPC_INS_DIVD, + "divde", // PPC_INS_DIVDE, + "divdeu", // PPC_INS_DIVDEU, + "divdu", // PPC_INS_DIVDU, + "divw", // PPC_INS_DIVW, + "divwe", // PPC_INS_DIVWE, + "divweu", // PPC_INS_DIVWEU, + "divwu", // PPC_INS_DIVWU, + "dss", // PPC_INS_DSS, + "dssall", // PPC_INS_DSSALL, + "dst", // PPC_INS_DST, + "dstst", // PPC_INS_DSTST, + "dststt", // PPC_INS_DSTSTT, + "dstt", // PPC_INS_DSTT, + "efdabs", // PPC_INS_EFDABS, + "efdadd", // PPC_INS_EFDADD, + "efdcfs", // PPC_INS_EFDCFS, + "efdcfsf", // PPC_INS_EFDCFSF, + "efdcfsi", // PPC_INS_EFDCFSI, + "efdcfsid", // PPC_INS_EFDCFSID, + "efdcfuf", // PPC_INS_EFDCFUF, + "efdcfui", // PPC_INS_EFDCFUI, + "efdcfuid", // PPC_INS_EFDCFUID, + "efdcmpeq", // PPC_INS_EFDCMPEQ, + "efdcmpgt", // PPC_INS_EFDCMPGT, + "efdcmplt", // PPC_INS_EFDCMPLT, + "efdctsf", // PPC_INS_EFDCTSF, + "efdctsi", // PPC_INS_EFDCTSI, + "efdctsidz", // PPC_INS_EFDCTSIDZ, + "efdctsiz", // PPC_INS_EFDCTSIZ, + "efdctuf", // PPC_INS_EFDCTUF, + "efdctui", // PPC_INS_EFDCTUI, + "efdctuidz", // PPC_INS_EFDCTUIDZ, + "efdctuiz", // PPC_INS_EFDCTUIZ, + "efddiv", // PPC_INS_EFDDIV, + "efdmul", // PPC_INS_EFDMUL, + "efdnabs", // PPC_INS_EFDNABS, + "efdneg", // PPC_INS_EFDNEG, + "efdsub", // PPC_INS_EFDSUB, + "efdtsteq", // PPC_INS_EFDTSTEQ, + "efdtstgt", // PPC_INS_EFDTSTGT, + "efdtstlt", // PPC_INS_EFDTSTLT, + "efsabs", // PPC_INS_EFSABS, + "efsadd", // PPC_INS_EFSADD, + "efscfd", // PPC_INS_EFSCFD, + "efscfsf", // PPC_INS_EFSCFSF, + "efscfsi", // PPC_INS_EFSCFSI, + "efscfuf", // PPC_INS_EFSCFUF, + "efscfui", // PPC_INS_EFSCFUI, + "efscmpeq", // PPC_INS_EFSCMPEQ, + "efscmpgt", // PPC_INS_EFSCMPGT, + "efscmplt", // PPC_INS_EFSCMPLT, + "efsctsf", // PPC_INS_EFSCTSF, + "efsctsi", // PPC_INS_EFSCTSI, + "efsctsiz", // PPC_INS_EFSCTSIZ, + "efsctuf", // PPC_INS_EFSCTUF, + "efsctui", // PPC_INS_EFSCTUI, + "efsctuiz", // PPC_INS_EFSCTUIZ, + "efsdiv", // PPC_INS_EFSDIV, + "efsmul", // PPC_INS_EFSMUL, + "efsnabs", // PPC_INS_EFSNABS, + "efsneg", // PPC_INS_EFSNEG, + "efssub", // PPC_INS_EFSSUB, + "efststeq", // PPC_INS_EFSTSTEQ, + "efststgt", // PPC_INS_EFSTSTGT, + "efststlt", // PPC_INS_EFSTSTLT, + "eieio", // PPC_INS_EIEIO, + "eqv", // PPC_INS_EQV, + "evabs", // PPC_INS_EVABS, + "evaddiw", // PPC_INS_EVADDIW, + "evaddsmiaaw", // PPC_INS_EVADDSMIAAW, + "evaddssiaaw", // PPC_INS_EVADDSSIAAW, + "evaddumiaaw", // PPC_INS_EVADDUMIAAW, + "evaddusiaaw", // PPC_INS_EVADDUSIAAW, + "evaddw", // PPC_INS_EVADDW, + "evand", // PPC_INS_EVAND, + "evandc", // PPC_INS_EVANDC, + "evcmpeq", // PPC_INS_EVCMPEQ, + "evcmpgts", // PPC_INS_EVCMPGTS, + "evcmpgtu", // PPC_INS_EVCMPGTU, + "evcmplts", // PPC_INS_EVCMPLTS, + "evcmpltu", // PPC_INS_EVCMPLTU, + "evcntlsw", // PPC_INS_EVCNTLSW, + "evcntlzw", // PPC_INS_EVCNTLZW, + "evdivws", // PPC_INS_EVDIVWS, + "evdivwu", // PPC_INS_EVDIVWU, + "eveqv", // PPC_INS_EVEQV, + "evextsb", // PPC_INS_EVEXTSB, + "evextsh", // PPC_INS_EVEXTSH, + "evfsabs", // PPC_INS_EVFSABS, + "evfsadd", // PPC_INS_EVFSADD, + "evfscfsf", // PPC_INS_EVFSCFSF, + "evfscfsi", // PPC_INS_EVFSCFSI, + "evfscfuf", // PPC_INS_EVFSCFUF, + "evfscfui", // PPC_INS_EVFSCFUI, + "evfscmpeq", // PPC_INS_EVFSCMPEQ, + "evfscmpgt", // PPC_INS_EVFSCMPGT, + "evfscmplt", // PPC_INS_EVFSCMPLT, + "evfsctsf", // PPC_INS_EVFSCTSF, + "evfsctsi", // PPC_INS_EVFSCTSI, + "evfsctsiz", // PPC_INS_EVFSCTSIZ, + "evfsctui", // PPC_INS_EVFSCTUI, + "evfsdiv", // PPC_INS_EVFSDIV, + "evfsmul", // PPC_INS_EVFSMUL, + "evfsnabs", // PPC_INS_EVFSNABS, + "evfsneg", // PPC_INS_EVFSNEG, + "evfssub", // PPC_INS_EVFSSUB, + "evfststeq", // PPC_INS_EVFSTSTEQ, + "evfststgt", // PPC_INS_EVFSTSTGT, + "evfststlt", // PPC_INS_EVFSTSTLT, + "evldd", // PPC_INS_EVLDD, + "evlddx", // PPC_INS_EVLDDX, + "evldh", // PPC_INS_EVLDH, + "evldhx", // PPC_INS_EVLDHX, + "evldw", // PPC_INS_EVLDW, + "evldwx", // PPC_INS_EVLDWX, + "evlhhesplat", // PPC_INS_EVLHHESPLAT, + "evlhhesplatx", // PPC_INS_EVLHHESPLATX, + "evlhhossplat", // PPC_INS_EVLHHOSSPLAT, + "evlhhossplatx", // PPC_INS_EVLHHOSSPLATX, + "evlhhousplat", // PPC_INS_EVLHHOUSPLAT, + "evlhhousplatx", // PPC_INS_EVLHHOUSPLATX, + "evlwhe", // PPC_INS_EVLWHE, + "evlwhex", // PPC_INS_EVLWHEX, + "evlwhos", // PPC_INS_EVLWHOS, + "evlwhosx", // PPC_INS_EVLWHOSX, + "evlwhou", // PPC_INS_EVLWHOU, + "evlwhoux", // PPC_INS_EVLWHOUX, + "evlwhsplat", // PPC_INS_EVLWHSPLAT, + "evlwhsplatx", // PPC_INS_EVLWHSPLATX, + "evlwwsplat", // PPC_INS_EVLWWSPLAT, + "evlwwsplatx", // PPC_INS_EVLWWSPLATX, + "evmergehi", // PPC_INS_EVMERGEHI, + "evmergehilo", // PPC_INS_EVMERGEHILO, + "evmergelo", // PPC_INS_EVMERGELO, + "evmergelohi", // PPC_INS_EVMERGELOHI, + "evmhegsmfaa", // PPC_INS_EVMHEGSMFAA, + "evmhegsmfan", // PPC_INS_EVMHEGSMFAN, + "evmhegsmiaa", // PPC_INS_EVMHEGSMIAA, + "evmhegsmian", // PPC_INS_EVMHEGSMIAN, + "evmhegumiaa", // PPC_INS_EVMHEGUMIAA, + "evmhegumian", // PPC_INS_EVMHEGUMIAN, + "evmhesmf", // PPC_INS_EVMHESMF, + "evmhesmfa", // PPC_INS_EVMHESMFA, + "evmhesmfaaw", // PPC_INS_EVMHESMFAAW, + "evmhesmfanw", // PPC_INS_EVMHESMFANW, + "evmhesmi", // PPC_INS_EVMHESMI, + "evmhesmia", // PPC_INS_EVMHESMIA, + "evmhesmiaaw", // PPC_INS_EVMHESMIAAW, + "evmhesmianw", // PPC_INS_EVMHESMIANW, + "evmhessf", // PPC_INS_EVMHESSF, + "evmhessfa", // PPC_INS_EVMHESSFA, + "evmhessfaaw", // PPC_INS_EVMHESSFAAW, + "evmhessfanw", // PPC_INS_EVMHESSFANW, + "evmhessiaaw", // PPC_INS_EVMHESSIAAW, + "evmhessianw", // PPC_INS_EVMHESSIANW, + "evmheumi", // PPC_INS_EVMHEUMI, + "evmheumia", // PPC_INS_EVMHEUMIA, + "evmheumiaaw", // PPC_INS_EVMHEUMIAAW, + "evmheumianw", // PPC_INS_EVMHEUMIANW, + "evmheusiaaw", // PPC_INS_EVMHEUSIAAW, + "evmheusianw", // PPC_INS_EVMHEUSIANW, + "evmhogsmfaa", // PPC_INS_EVMHOGSMFAA, + "evmhogsmfan", // PPC_INS_EVMHOGSMFAN, + "evmhogsmiaa", // PPC_INS_EVMHOGSMIAA, + "evmhogsmian", // PPC_INS_EVMHOGSMIAN, + "evmhogumiaa", // PPC_INS_EVMHOGUMIAA, + "evmhogumian", // PPC_INS_EVMHOGUMIAN, + "evmhosmf", // PPC_INS_EVMHOSMF, + "evmhosmfa", // PPC_INS_EVMHOSMFA, + "evmhosmfaaw", // PPC_INS_EVMHOSMFAAW, + "evmhosmfanw", // PPC_INS_EVMHOSMFANW, + "evmhosmi", // PPC_INS_EVMHOSMI, + "evmhosmia", // PPC_INS_EVMHOSMIA, + "evmhosmiaaw", // PPC_INS_EVMHOSMIAAW, + "evmhosmianw", // PPC_INS_EVMHOSMIANW, + "evmhossf", // PPC_INS_EVMHOSSF, + "evmhossfa", // PPC_INS_EVMHOSSFA, + "evmhossfaaw", // PPC_INS_EVMHOSSFAAW, + "evmhossfanw", // PPC_INS_EVMHOSSFANW, + "evmhossiaaw", // PPC_INS_EVMHOSSIAAW, + "evmhossianw", // PPC_INS_EVMHOSSIANW, + "evmhoumi", // PPC_INS_EVMHOUMI, + "evmhoumia", // PPC_INS_EVMHOUMIA, + "evmhoumiaaw", // PPC_INS_EVMHOUMIAAW, + "evmhoumianw", // PPC_INS_EVMHOUMIANW, + "evmhousiaaw", // PPC_INS_EVMHOUSIAAW, + "evmhousianw", // PPC_INS_EVMHOUSIANW, + "evmra", // PPC_INS_EVMRA, + "evmwhsmf", // PPC_INS_EVMWHSMF, + "evmwhsmfa", // PPC_INS_EVMWHSMFA, + "evmwhsmi", // PPC_INS_EVMWHSMI, + "evmwhsmia", // PPC_INS_EVMWHSMIA, + "evmwhssf", // PPC_INS_EVMWHSSF, + "evmwhssfa", // PPC_INS_EVMWHSSFA, + "evmwhumi", // PPC_INS_EVMWHUMI, + "evmwhumia", // PPC_INS_EVMWHUMIA, + "evmwlsmiaaw", // PPC_INS_EVMWLSMIAAW, + "evmwlsmianw", // PPC_INS_EVMWLSMIANW, + "evmwlssiaaw", // PPC_INS_EVMWLSSIAAW, + "evmwlssianw", // PPC_INS_EVMWLSSIANW, + "evmwlumi", // PPC_INS_EVMWLUMI, + "evmwlumia", // PPC_INS_EVMWLUMIA, + "evmwlumiaaw", // PPC_INS_EVMWLUMIAAW, + "evmwlumianw", // PPC_INS_EVMWLUMIANW, + "evmwlusiaaw", // PPC_INS_EVMWLUSIAAW, + "evmwlusianw", // PPC_INS_EVMWLUSIANW, + "evmwsmf", // PPC_INS_EVMWSMF, + "evmwsmfa", // PPC_INS_EVMWSMFA, + "evmwsmfaa", // PPC_INS_EVMWSMFAA, + "evmwsmfan", // PPC_INS_EVMWSMFAN, + "evmwsmi", // PPC_INS_EVMWSMI, + "evmwsmia", // PPC_INS_EVMWSMIA, + "evmwsmiaa", // PPC_INS_EVMWSMIAA, + "evmwsmian", // PPC_INS_EVMWSMIAN, + "evmwssf", // PPC_INS_EVMWSSF, + "evmwssfa", // PPC_INS_EVMWSSFA, + "evmwssfaa", // PPC_INS_EVMWSSFAA, + "evmwssfan", // PPC_INS_EVMWSSFAN, + "evmwumi", // PPC_INS_EVMWUMI, + "evmwumia", // PPC_INS_EVMWUMIA, + "evmwumiaa", // PPC_INS_EVMWUMIAA, + "evmwumian", // PPC_INS_EVMWUMIAN, + "evnand", // PPC_INS_EVNAND, + "evneg", // PPC_INS_EVNEG, + "evnor", // PPC_INS_EVNOR, + "evor", // PPC_INS_EVOR, + "evorc", // PPC_INS_EVORC, + "evrlw", // PPC_INS_EVRLW, + "evrlwi", // PPC_INS_EVRLWI, + "evrndw", // PPC_INS_EVRNDW, + "evsel", // PPC_INS_EVSEL, + "evslw", // PPC_INS_EVSLW, + "evslwi", // PPC_INS_EVSLWI, + "evsplatfi", // PPC_INS_EVSPLATFI, + "evsplati", // PPC_INS_EVSPLATI, + "evsrwis", // PPC_INS_EVSRWIS, + "evsrwiu", // PPC_INS_EVSRWIU, + "evsrws", // PPC_INS_EVSRWS, + "evsrwu", // PPC_INS_EVSRWU, + "evstdd", // PPC_INS_EVSTDD, + "evstddx", // PPC_INS_EVSTDDX, + "evstdh", // PPC_INS_EVSTDH, + "evstdhx", // PPC_INS_EVSTDHX, + "evstdw", // PPC_INS_EVSTDW, + "evstdwx", // PPC_INS_EVSTDWX, + "evstwhe", // PPC_INS_EVSTWHE, + "evstwhex", // PPC_INS_EVSTWHEX, + "evstwho", // PPC_INS_EVSTWHO, + "evstwhox", // PPC_INS_EVSTWHOX, + "evstwwe", // PPC_INS_EVSTWWE, + "evstwwex", // PPC_INS_EVSTWWEX, + "evstwwo", // PPC_INS_EVSTWWO, + "evstwwox", // PPC_INS_EVSTWWOX, + "evsubfsmiaaw", // PPC_INS_EVSUBFSMIAAW, + "evsubfssiaaw", // PPC_INS_EVSUBFSSIAAW, + "evsubfumiaaw", // PPC_INS_EVSUBFUMIAAW, + "evsubfusiaaw", // PPC_INS_EVSUBFUSIAAW, + "evsubfw", // PPC_INS_EVSUBFW, + "evsubifw", // PPC_INS_EVSUBIFW, + "evxor", // PPC_INS_EVXOR, + "extldi", // PPC_INS_EXTLDI, + "extlwi", // PPC_INS_EXTLWI, + "extrdi", // PPC_INS_EXTRDI, + "extrwi", // PPC_INS_EXTRWI, + "extsb", // PPC_INS_EXTSB, + "extsh", // PPC_INS_EXTSH, + "extsw", // PPC_INS_EXTSW, + "extswsli", // PPC_INS_EXTSWSLI, + "fabs", // PPC_INS_FABS, + "fadd", // PPC_INS_FADD, + "fadds", // PPC_INS_FADDS, + "fcfid", // PPC_INS_FCFID, + "fcfids", // PPC_INS_FCFIDS, + "fcfidu", // PPC_INS_FCFIDU, + "fcfidus", // PPC_INS_FCFIDUS, + "fcmpu", // PPC_INS_FCMPU, + "fcpsgn", // PPC_INS_FCPSGN, + "fctid", // PPC_INS_FCTID, + "fctidu", // PPC_INS_FCTIDU, + "fctiduz", // PPC_INS_FCTIDUZ, + "fctidz", // PPC_INS_FCTIDZ, + "fctiw", // PPC_INS_FCTIW, + "fctiwu", // PPC_INS_FCTIWU, + "fctiwuz", // PPC_INS_FCTIWUZ, + "fctiwz", // PPC_INS_FCTIWZ, + "fdiv", // PPC_INS_FDIV, + "fdivs", // PPC_INS_FDIVS, + "fmadd", // PPC_INS_FMADD, + "fmadds", // PPC_INS_FMADDS, + "fmr", // PPC_INS_FMR, + "fmsub", // PPC_INS_FMSUB, + "fmsubs", // PPC_INS_FMSUBS, + "fmul", // PPC_INS_FMUL, + "fmuls", // PPC_INS_FMULS, + "fnabs", // PPC_INS_FNABS, + "fneg", // PPC_INS_FNEG, + "fnmadd", // PPC_INS_FNMADD, + "fnmadds", // PPC_INS_FNMADDS, + "fnmsub", // PPC_INS_FNMSUB, + "fnmsubs", // PPC_INS_FNMSUBS, + "fre", // PPC_INS_FRE, + "fres", // PPC_INS_FRES, + "frim", // PPC_INS_FRIM, + "frin", // PPC_INS_FRIN, + "frip", // PPC_INS_FRIP, + "friz", // PPC_INS_FRIZ, + "frsp", // PPC_INS_FRSP, + "frsqrte", // PPC_INS_FRSQRTE, + "frsqrtes", // PPC_INS_FRSQRTES, + "fsel", // PPC_INS_FSEL, + "fsqrt", // PPC_INS_FSQRT, + "fsqrts", // PPC_INS_FSQRTS, + "fsub", // PPC_INS_FSUB, + "fsubs", // PPC_INS_FSUBS, + "ftdiv", // PPC_INS_FTDIV, + "ftsqrt", // PPC_INS_FTSQRT, + "hrfid", // PPC_INS_HRFID, + "icbi", // PPC_INS_ICBI, + "icbiep", // PPC_INS_ICBIEP, + "icblc", // PPC_INS_ICBLC, + "icblq", // PPC_INS_ICBLQ, + "icbt", // PPC_INS_ICBT, + "icbtls", // PPC_INS_ICBTLS, + "iccci", // PPC_INS_ICCCI, + "ici", // PPC_INS_ICI, + "inslwi", // PPC_INS_INSLWI, + "insrdi", // PPC_INS_INSRDI, + "insrwi", // PPC_INS_INSRWI, + "isel", // PPC_INS_ISEL, + "isync", // PPC_INS_ISYNC, + "la", // PPC_INS_LA, + "lbarx", // PPC_INS_LBARX, + "lbepx", // PPC_INS_LBEPX, + "lbz", // PPC_INS_LBZ, + "lbzcix", // PPC_INS_LBZCIX, + "lbzu", // PPC_INS_LBZU, + "lbzux", // PPC_INS_LBZUX, + "lbzx", // PPC_INS_LBZX, + "ld", // PPC_INS_LD, + "ldarx", // PPC_INS_LDARX, + "ldat", // PPC_INS_LDAT, + "ldbrx", // PPC_INS_LDBRX, + "ldcix", // PPC_INS_LDCIX, + "ldmx", // PPC_INS_LDMX, + "ldu", // PPC_INS_LDU, + "ldux", // PPC_INS_LDUX, + "ldx", // PPC_INS_LDX, + "lfd", // PPC_INS_LFD, + "lfdepx", // PPC_INS_LFDEPX, + "lfdu", // PPC_INS_LFDU, + "lfdux", // PPC_INS_LFDUX, + "lfdx", // PPC_INS_LFDX, + "lfiwax", // PPC_INS_LFIWAX, + "lfiwzx", // PPC_INS_LFIWZX, + "lfs", // PPC_INS_LFS, + "lfsu", // PPC_INS_LFSU, + "lfsux", // PPC_INS_LFSUX, + "lfsx", // PPC_INS_LFSX, + "lha", // PPC_INS_LHA, + "lharx", // PPC_INS_LHARX, + "lhau", // PPC_INS_LHAU, + "lhaux", // PPC_INS_LHAUX, + "lhax", // PPC_INS_LHAX, + "lhbrx", // PPC_INS_LHBRX, + "lhepx", // PPC_INS_LHEPX, + "lhz", // PPC_INS_LHZ, + "lhzcix", // PPC_INS_LHZCIX, + "lhzu", // PPC_INS_LHZU, + "lhzux", // PPC_INS_LHZUX, + "lhzx", // PPC_INS_LHZX, + "li", // PPC_INS_LI, + "lis", // PPC_INS_LIS, + "lmw", // PPC_INS_LMW, + "lnia", // PPC_INS_LNIA, + "lswi", // PPC_INS_LSWI, + "lvebx", // PPC_INS_LVEBX, + "lvehx", // PPC_INS_LVEHX, + "lvewx", // PPC_INS_LVEWX, + "lvsl", // PPC_INS_LVSL, + "lvsr", // PPC_INS_LVSR, + "lvx", // PPC_INS_LVX, + "lvxl", // PPC_INS_LVXL, + "lwa", // PPC_INS_LWA, + "lwarx", // PPC_INS_LWARX, + "lwat", // PPC_INS_LWAT, + "lwaux", // PPC_INS_LWAUX, + "lwax", // PPC_INS_LWAX, + "lwbrx", // PPC_INS_LWBRX, + "lwepx", // PPC_INS_LWEPX, + "lwsync", // PPC_INS_LWSYNC, + "lwz", // PPC_INS_LWZ, + "lwzcix", // PPC_INS_LWZCIX, + "lwzu", // PPC_INS_LWZU, + "lwzux", // PPC_INS_LWZUX, + "lwzx", // PPC_INS_LWZX, + "lxsd", // PPC_INS_LXSD, + "lxsdx", // PPC_INS_LXSDX, + "lxsibzx", // PPC_INS_LXSIBZX, + "lxsihzx", // PPC_INS_LXSIHZX, + "lxsiwax", // PPC_INS_LXSIWAX, + "lxsiwzx", // PPC_INS_LXSIWZX, + "lxssp", // PPC_INS_LXSSP, + "lxsspx", // PPC_INS_LXSSPX, + "lxv", // PPC_INS_LXV, + "lxvb16x", // PPC_INS_LXVB16X, + "lxvd2x", // PPC_INS_LXVD2X, + "lxvdsx", // PPC_INS_LXVDSX, + "lxvh8x", // PPC_INS_LXVH8X, + "lxvl", // PPC_INS_LXVL, + "lxvll", // PPC_INS_LXVLL, + "lxvw4x", // PPC_INS_LXVW4X, + "lxvwsx", // PPC_INS_LXVWSX, + "lxvx", // PPC_INS_LXVX, + "maddhd", // PPC_INS_MADDHD, + "maddhdu", // PPC_INS_MADDHDU, + "maddld", // PPC_INS_MADDLD, + "mbar", // PPC_INS_MBAR, + "mcrf", // PPC_INS_MCRF, + "mcrfs", // PPC_INS_MCRFS, + "mcrxrx", // PPC_INS_MCRXRX, + "mfamr", // PPC_INS_MFAMR, + "mfasr", // PPC_INS_MFASR, + "mfbhrbe", // PPC_INS_MFBHRBE, + "mfbr0", // PPC_INS_MFBR0, + "mfbr1", // PPC_INS_MFBR1, + "mfbr2", // PPC_INS_MFBR2, + "mfbr3", // PPC_INS_MFBR3, + "mfbr4", // PPC_INS_MFBR4, + "mfbr5", // PPC_INS_MFBR5, + "mfbr6", // PPC_INS_MFBR6, + "mfbr7", // PPC_INS_MFBR7, + "mfcfar", // PPC_INS_MFCFAR, + "mfcr", // PPC_INS_MFCR, + "mfctr", // PPC_INS_MFCTR, + "mfdar", // PPC_INS_MFDAR, + "mfdbatl", // PPC_INS_MFDBATL, + "mfdbatu", // PPC_INS_MFDBATU, + "mfdccr", // PPC_INS_MFDCCR, + "mfdcr", // PPC_INS_MFDCR, + "mfdear", // PPC_INS_MFDEAR, + "mfdec", // PPC_INS_MFDEC, + "mfdscr", // PPC_INS_MFDSCR, + "mfdsisr", // PPC_INS_MFDSISR, + "mfesr", // PPC_INS_MFESR, + "mffprd", // PPC_INS_MFFPRD, + "mffs", // PPC_INS_MFFS, + "mffscdrn", // PPC_INS_MFFSCDRN, + "mffscdrni", // PPC_INS_MFFSCDRNI, + "mffsce", // PPC_INS_MFFSCE, + "mffscrn", // PPC_INS_MFFSCRN, + "mffscrni", // PPC_INS_MFFSCRNI, + "mffsl", // PPC_INS_MFFSL, + "mfibatl", // PPC_INS_MFIBATL, + "mfibatu", // PPC_INS_MFIBATU, + "mficcr", // PPC_INS_MFICCR, + "mflr", // PPC_INS_MFLR, + "mfmsr", // PPC_INS_MFMSR, + "mfocrf", // PPC_INS_MFOCRF, + "mfpid", // PPC_INS_MFPID, + "mfpmr", // PPC_INS_MFPMR, + "mfpvr", // PPC_INS_MFPVR, + "mfrtcl", // PPC_INS_MFRTCL, + "mfrtcu", // PPC_INS_MFRTCU, + "mfsdr1", // PPC_INS_MFSDR1, + "mfspefscr", // PPC_INS_MFSPEFSCR, + "mfspr", // PPC_INS_MFSPR, + "mfsprg", // PPC_INS_MFSPRG, + "mfsprg0", // PPC_INS_MFSPRG0, + "mfsprg1", // PPC_INS_MFSPRG1, + "mfsprg2", // PPC_INS_MFSPRG2, + "mfsprg3", // PPC_INS_MFSPRG3, + "mfsprg4", // PPC_INS_MFSPRG4, + "mfsprg5", // PPC_INS_MFSPRG5, + "mfsprg6", // PPC_INS_MFSPRG6, + "mfsprg7", // PPC_INS_MFSPRG7, + "mfsr", // PPC_INS_MFSR, + "mfsrin", // PPC_INS_MFSRIN, + "mfsrr0", // PPC_INS_MFSRR0, + "mfsrr1", // PPC_INS_MFSRR1, + "mfsrr2", // PPC_INS_MFSRR2, + "mfsrr3", // PPC_INS_MFSRR3, + "mftb", // PPC_INS_MFTB, + "mftbhi", // PPC_INS_MFTBHI, + "mftbl", // PPC_INS_MFTBL, + "mftblo", // PPC_INS_MFTBLO, + "mftbu", // PPC_INS_MFTBU, + "mftcr", // PPC_INS_MFTCR, + "mfvrd", // PPC_INS_MFVRD, + "mfvrsave", // PPC_INS_MFVRSAVE, + "mfvscr", // PPC_INS_MFVSCR, + "mfvsrd", // PPC_INS_MFVSRD, + "mfvsrld", // PPC_INS_MFVSRLD, + "mfvsrwz", // PPC_INS_MFVSRWZ, + "mfxer", // PPC_INS_MFXER, + "modsd", // PPC_INS_MODSD, + "modsw", // PPC_INS_MODSW, + "modud", // PPC_INS_MODUD, + "moduw", // PPC_INS_MODUW, + "mr", // PPC_INS_MR, + "msgsync", // PPC_INS_MSGSYNC, + "msync", // PPC_INS_MSYNC, + "mtamr", // PPC_INS_MTAMR, + "mtasr", // PPC_INS_MTASR, + "mtbr0", // PPC_INS_MTBR0, + "mtbr1", // PPC_INS_MTBR1, + "mtbr2", // PPC_INS_MTBR2, + "mtbr3", // PPC_INS_MTBR3, + "mtbr4", // PPC_INS_MTBR4, + "mtbr5", // PPC_INS_MTBR5, + "mtbr6", // PPC_INS_MTBR6, + "mtbr7", // PPC_INS_MTBR7, + "mtcfar", // PPC_INS_MTCFAR, + "mtcr", // PPC_INS_MTCR, + "mtcrf", // PPC_INS_MTCRF, + "mtctr", // PPC_INS_MTCTR, + "mtdar", // PPC_INS_MTDAR, + "mtdbatl", // PPC_INS_MTDBATL, + "mtdbatu", // PPC_INS_MTDBATU, + "mtdccr", // PPC_INS_MTDCCR, + "mtdcr", // PPC_INS_MTDCR, + "mtdear", // PPC_INS_MTDEAR, + "mtdec", // PPC_INS_MTDEC, + "mtdscr", // PPC_INS_MTDSCR, + "mtdsisr", // PPC_INS_MTDSISR, + "mtesr", // PPC_INS_MTESR, + "mtfsb0", // PPC_INS_MTFSB0, + "mtfsb1", // PPC_INS_MTFSB1, + "mtfsf", // PPC_INS_MTFSF, + "mtfsfi", // PPC_INS_MTFSFI, + "mtibatl", // PPC_INS_MTIBATL, + "mtibatu", // PPC_INS_MTIBATU, + "mticcr", // PPC_INS_MTICCR, + "mtlr", // PPC_INS_MTLR, + "mtmsr", // PPC_INS_MTMSR, + "mtmsrd", // PPC_INS_MTMSRD, + "mtocrf", // PPC_INS_MTOCRF, + "mtpid", // PPC_INS_MTPID, + "mtpmr", // PPC_INS_MTPMR, + "mtsdr1", // PPC_INS_MTSDR1, + "mtspefscr", // PPC_INS_MTSPEFSCR, + "mtspr", // PPC_INS_MTSPR, + "mtsprg", // PPC_INS_MTSPRG, + "mtsprg0", // PPC_INS_MTSPRG0, + "mtsprg1", // PPC_INS_MTSPRG1, + "mtsprg2", // PPC_INS_MTSPRG2, + "mtsprg3", // PPC_INS_MTSPRG3, + "mtsprg4", // PPC_INS_MTSPRG4, + "mtsprg5", // PPC_INS_MTSPRG5, + "mtsprg6", // PPC_INS_MTSPRG6, + "mtsprg7", // PPC_INS_MTSPRG7, + "mtsr", // PPC_INS_MTSR, + "mtsrin", // PPC_INS_MTSRIN, + "mtsrr0", // PPC_INS_MTSRR0, + "mtsrr1", // PPC_INS_MTSRR1, + "mtsrr2", // PPC_INS_MTSRR2, + "mtsrr3", // PPC_INS_MTSRR3, + "mttbhi", // PPC_INS_MTTBHI, + "mttbl", // PPC_INS_MTTBL, + "mttblo", // PPC_INS_MTTBLO, + "mttbu", // PPC_INS_MTTBU, + "mttcr", // PPC_INS_MTTCR, + "mtvrsave", // PPC_INS_MTVRSAVE, + "mtvscr", // PPC_INS_MTVSCR, + "mtvsrd", // PPC_INS_MTVSRD, + "mtvsrdd", // PPC_INS_MTVSRDD, + "mtvsrwa", // PPC_INS_MTVSRWA, + "mtvsrws", // PPC_INS_MTVSRWS, + "mtvsrwz", // PPC_INS_MTVSRWZ, + "mtxer", // PPC_INS_MTXER, + "mulhd", // PPC_INS_MULHD, + "mulhdu", // PPC_INS_MULHDU, + "mulhw", // PPC_INS_MULHW, + "mulhwu", // PPC_INS_MULHWU, + "mulld", // PPC_INS_MULLD, + "mulli", // PPC_INS_MULLI, + "mullw", // PPC_INS_MULLW, + "nand", // PPC_INS_NAND, + "nap", // PPC_INS_NAP, + "neg", // PPC_INS_NEG, + "nop", // PPC_INS_NOP, + "nor", // PPC_INS_NOR, + "not", // PPC_INS_NOT, + "or", // PPC_INS_OR, + "orc", // PPC_INS_ORC, + "ori", // PPC_INS_ORI, + "oris", // PPC_INS_ORIS, + "paste", // PPC_INS_PASTE, + "paste_last", // PPC_INS_PASTE_LAST, + "popcntb", // PPC_INS_POPCNTB, + "popcntd", // PPC_INS_POPCNTD, + "popcntw", // PPC_INS_POPCNTW, + "ptesync", // PPC_INS_PTESYNC, + "qvaligni", // PPC_INS_QVALIGNI, + "qvesplati", // PPC_INS_QVESPLATI, + "qvfabs", // PPC_INS_QVFABS, + "qvfadd", // PPC_INS_QVFADD, + "qvfadds", // PPC_INS_QVFADDS, + "qvfand", // PPC_INS_QVFAND, + "qvfandc", // PPC_INS_QVFANDC, + "qvfcfid", // PPC_INS_QVFCFID, + "qvfcfids", // PPC_INS_QVFCFIDS, + "qvfcfidu", // PPC_INS_QVFCFIDU, + "qvfcfidus", // PPC_INS_QVFCFIDUS, + "qvfclr", // PPC_INS_QVFCLR, + "qvfcmpeq", // PPC_INS_QVFCMPEQ, + "qvfcmpgt", // PPC_INS_QVFCMPGT, + "qvfcmplt", // PPC_INS_QVFCMPLT, + "qvfcpsgn", // PPC_INS_QVFCPSGN, + "qvfctfb", // PPC_INS_QVFCTFB, + "qvfctid", // PPC_INS_QVFCTID, + "qvfctidu", // PPC_INS_QVFCTIDU, + "qvfctiduz", // PPC_INS_QVFCTIDUZ, + "qvfctidz", // PPC_INS_QVFCTIDZ, + "qvfctiw", // PPC_INS_QVFCTIW, + "qvfctiwu", // PPC_INS_QVFCTIWU, + "qvfctiwuz", // PPC_INS_QVFCTIWUZ, + "qvfctiwz", // PPC_INS_QVFCTIWZ, + "qvfequ", // PPC_INS_QVFEQU, + "qvflogical", // PPC_INS_QVFLOGICAL, + "qvfmadd", // PPC_INS_QVFMADD, + "qvfmadds", // PPC_INS_QVFMADDS, + "qvfmr", // PPC_INS_QVFMR, + "qvfmsub", // PPC_INS_QVFMSUB, + "qvfmsubs", // PPC_INS_QVFMSUBS, + "qvfmul", // PPC_INS_QVFMUL, + "qvfmuls", // PPC_INS_QVFMULS, + "qvfnabs", // PPC_INS_QVFNABS, + "qvfnand", // PPC_INS_QVFNAND, + "qvfneg", // PPC_INS_QVFNEG, + "qvfnmadd", // PPC_INS_QVFNMADD, + "qvfnmadds", // PPC_INS_QVFNMADDS, + "qvfnmsub", // PPC_INS_QVFNMSUB, + "qvfnmsubs", // PPC_INS_QVFNMSUBS, + "qvfnor", // PPC_INS_QVFNOR, + "qvfnot", // PPC_INS_QVFNOT, + "qvfor", // PPC_INS_QVFOR, + "qvforc", // PPC_INS_QVFORC, + "qvfperm", // PPC_INS_QVFPERM, + "qvfre", // PPC_INS_QVFRE, + "qvfres", // PPC_INS_QVFRES, + "qvfrim", // PPC_INS_QVFRIM, + "qvfrin", // PPC_INS_QVFRIN, + "qvfrip", // PPC_INS_QVFRIP, + "qvfriz", // PPC_INS_QVFRIZ, + "qvfrsp", // PPC_INS_QVFRSP, + "qvfrsqrte", // PPC_INS_QVFRSQRTE, + "qvfrsqrtes", // PPC_INS_QVFRSQRTES, + "qvfsel", // PPC_INS_QVFSEL, + "qvfset", // PPC_INS_QVFSET, + "qvfsub", // PPC_INS_QVFSUB, + "qvfsubs", // PPC_INS_QVFSUBS, + "qvftstnan", // PPC_INS_QVFTSTNAN, + "qvfxmadd", // PPC_INS_QVFXMADD, + "qvfxmadds", // PPC_INS_QVFXMADDS, + "qvfxmul", // PPC_INS_QVFXMUL, + "qvfxmuls", // PPC_INS_QVFXMULS, + "qvfxor", // PPC_INS_QVFXOR, + "qvfxxcpnmadd", // PPC_INS_QVFXXCPNMADD, + "qvfxxcpnmadds", // PPC_INS_QVFXXCPNMADDS, + "qvfxxmadd", // PPC_INS_QVFXXMADD, + "qvfxxmadds", // PPC_INS_QVFXXMADDS, + "qvfxxnpmadd", // PPC_INS_QVFXXNPMADD, + "qvfxxnpmadds", // PPC_INS_QVFXXNPMADDS, + "qvgpci", // PPC_INS_QVGPCI, + "qvlfcdux", // PPC_INS_QVLFCDUX, + "qvlfcduxa", // PPC_INS_QVLFCDUXA, + "qvlfcdx", // PPC_INS_QVLFCDX, + "qvlfcdxa", // PPC_INS_QVLFCDXA, + "qvlfcsux", // PPC_INS_QVLFCSUX, + "qvlfcsuxa", // PPC_INS_QVLFCSUXA, + "qvlfcsx", // PPC_INS_QVLFCSX, + "qvlfcsxa", // PPC_INS_QVLFCSXA, + "qvlfdux", // PPC_INS_QVLFDUX, + "qvlfduxa", // PPC_INS_QVLFDUXA, + "qvlfdx", // PPC_INS_QVLFDX, + "qvlfdxa", // PPC_INS_QVLFDXA, + "qvlfiwax", // PPC_INS_QVLFIWAX, + "qvlfiwaxa", // PPC_INS_QVLFIWAXA, + "qvlfiwzx", // PPC_INS_QVLFIWZX, + "qvlfiwzxa", // PPC_INS_QVLFIWZXA, + "qvlfsux", // PPC_INS_QVLFSUX, + "qvlfsuxa", // PPC_INS_QVLFSUXA, + "qvlfsx", // PPC_INS_QVLFSX, + "qvlfsxa", // PPC_INS_QVLFSXA, + "qvlpcldx", // PPC_INS_QVLPCLDX, + "qvlpclsx", // PPC_INS_QVLPCLSX, + "qvlpcrdx", // PPC_INS_QVLPCRDX, + "qvlpcrsx", // PPC_INS_QVLPCRSX, + "qvstfcdux", // PPC_INS_QVSTFCDUX, + "qvstfcduxa", // PPC_INS_QVSTFCDUXA, + "qvstfcduxi", // PPC_INS_QVSTFCDUXI, + "qvstfcduxia", // PPC_INS_QVSTFCDUXIA, + "qvstfcdx", // PPC_INS_QVSTFCDX, + "qvstfcdxa", // PPC_INS_QVSTFCDXA, + "qvstfcdxi", // PPC_INS_QVSTFCDXI, + "qvstfcdxia", // PPC_INS_QVSTFCDXIA, + "qvstfcsux", // PPC_INS_QVSTFCSUX, + "qvstfcsuxa", // PPC_INS_QVSTFCSUXA, + "qvstfcsuxi", // PPC_INS_QVSTFCSUXI, + "qvstfcsuxia", // PPC_INS_QVSTFCSUXIA, + "qvstfcsx", // PPC_INS_QVSTFCSX, + "qvstfcsxa", // PPC_INS_QVSTFCSXA, + "qvstfcsxi", // PPC_INS_QVSTFCSXI, + "qvstfcsxia", // PPC_INS_QVSTFCSXIA, + "qvstfdux", // PPC_INS_QVSTFDUX, + "qvstfduxa", // PPC_INS_QVSTFDUXA, + "qvstfduxi", // PPC_INS_QVSTFDUXI, + "qvstfduxia", // PPC_INS_QVSTFDUXIA, + "qvstfdx", // PPC_INS_QVSTFDX, + "qvstfdxa", // PPC_INS_QVSTFDXA, + "qvstfdxi", // PPC_INS_QVSTFDXI, + "qvstfdxia", // PPC_INS_QVSTFDXIA, + "qvstfiwx", // PPC_INS_QVSTFIWX, + "qvstfiwxa", // PPC_INS_QVSTFIWXA, + "qvstfsux", // PPC_INS_QVSTFSUX, + "qvstfsuxa", // PPC_INS_QVSTFSUXA, + "qvstfsuxi", // PPC_INS_QVSTFSUXI, + "qvstfsuxia", // PPC_INS_QVSTFSUXIA, + "qvstfsx", // PPC_INS_QVSTFSX, + "qvstfsxa", // PPC_INS_QVSTFSXA, + "qvstfsxi", // PPC_INS_QVSTFSXI, + "qvstfsxia", // PPC_INS_QVSTFSXIA, + "rfci", // PPC_INS_RFCI, + "rfdi", // PPC_INS_RFDI, + "rfebb", // PPC_INS_RFEBB, + "rfi", // PPC_INS_RFI, + "rfid", // PPC_INS_RFID, + "rfmci", // PPC_INS_RFMCI, + "rldcl", // PPC_INS_RLDCL, + "rldcr", // PPC_INS_RLDCR, + "rldic", // PPC_INS_RLDIC, + "rldicl", // PPC_INS_RLDICL, + "rldicr", // PPC_INS_RLDICR, + "rldimi", // PPC_INS_RLDIMI, + "rlwimi", // PPC_INS_RLWIMI, + "rlwinm", // PPC_INS_RLWINM, + "rlwnm", // PPC_INS_RLWNM, + "rotld", // PPC_INS_ROTLD, + "rotldi", // PPC_INS_ROTLDI, + "rotlw", // PPC_INS_ROTLW, + "rotlwi", // PPC_INS_ROTLWI, + "rotrdi", // PPC_INS_ROTRDI, + "rotrwi", // PPC_INS_ROTRWI, + "sc", // PPC_INS_SC, + "setb", // PPC_INS_SETB, + "slbia", // PPC_INS_SLBIA, + "slbie", // PPC_INS_SLBIE, + "slbieg", // PPC_INS_SLBIEG, + "slbmfee", // PPC_INS_SLBMFEE, + "slbmfev", // PPC_INS_SLBMFEV, + "slbmte", // PPC_INS_SLBMTE, + "slbsync", // PPC_INS_SLBSYNC, + "sld", // PPC_INS_SLD, + "sldi", // PPC_INS_SLDI, + "slw", // PPC_INS_SLW, + "slwi", // PPC_INS_SLWI, + "srad", // PPC_INS_SRAD, + "sradi", // PPC_INS_SRADI, + "sraw", // PPC_INS_SRAW, + "srawi", // PPC_INS_SRAWI, + "srd", // PPC_INS_SRD, + "srdi", // PPC_INS_SRDI, + "srw", // PPC_INS_SRW, + "srwi", // PPC_INS_SRWI, + "stb", // PPC_INS_STB, + "stbcix", // PPC_INS_STBCIX, + "stbcx", // PPC_INS_STBCX, + "stbepx", // PPC_INS_STBEPX, + "stbu", // PPC_INS_STBU, + "stbux", // PPC_INS_STBUX, + "stbx", // PPC_INS_STBX, + "std", // PPC_INS_STD, + "stdat", // PPC_INS_STDAT, + "stdbrx", // PPC_INS_STDBRX, + "stdcix", // PPC_INS_STDCIX, + "stdcx", // PPC_INS_STDCX, + "stdu", // PPC_INS_STDU, + "stdux", // PPC_INS_STDUX, + "stdx", // PPC_INS_STDX, + "stfd", // PPC_INS_STFD, + "stfdepx", // PPC_INS_STFDEPX, + "stfdu", // PPC_INS_STFDU, + "stfdux", // PPC_INS_STFDUX, + "stfdx", // PPC_INS_STFDX, + "stfiwx", // PPC_INS_STFIWX, + "stfs", // PPC_INS_STFS, + "stfsu", // PPC_INS_STFSU, + "stfsux", // PPC_INS_STFSUX, + "stfsx", // PPC_INS_STFSX, + "sth", // PPC_INS_STH, + "sthbrx", // PPC_INS_STHBRX, + "sthcix", // PPC_INS_STHCIX, + "sthcx", // PPC_INS_STHCX, + "sthepx", // PPC_INS_STHEPX, + "sthu", // PPC_INS_STHU, + "sthux", // PPC_INS_STHUX, + "sthx", // PPC_INS_STHX, + "stmw", // PPC_INS_STMW, + "stop", // PPC_INS_STOP, + "stswi", // PPC_INS_STSWI, + "stvebx", // PPC_INS_STVEBX, + "stvehx", // PPC_INS_STVEHX, + "stvewx", // PPC_INS_STVEWX, + "stvx", // PPC_INS_STVX, + "stvxl", // PPC_INS_STVXL, + "stw", // PPC_INS_STW, + "stwat", // PPC_INS_STWAT, + "stwbrx", // PPC_INS_STWBRX, + "stwcix", // PPC_INS_STWCIX, + "stwcx", // PPC_INS_STWCX, + "stwepx", // PPC_INS_STWEPX, + "stwu", // PPC_INS_STWU, + "stwux", // PPC_INS_STWUX, + "stwx", // PPC_INS_STWX, + "stxsd", // PPC_INS_STXSD, + "stxsdx", // PPC_INS_STXSDX, + "stxsibx", // PPC_INS_STXSIBX, + "stxsihx", // PPC_INS_STXSIHX, + "stxsiwx", // PPC_INS_STXSIWX, + "stxssp", // PPC_INS_STXSSP, + "stxsspx", // PPC_INS_STXSSPX, + "stxv", // PPC_INS_STXV, + "stxvb16x", // PPC_INS_STXVB16X, + "stxvd2x", // PPC_INS_STXVD2X, + "stxvh8x", // PPC_INS_STXVH8X, + "stxvl", // PPC_INS_STXVL, + "stxvll", // PPC_INS_STXVLL, + "stxvw4x", // PPC_INS_STXVW4X, + "stxvx", // PPC_INS_STXVX, + "sub", // PPC_INS_SUB, + "subc", // PPC_INS_SUBC, + "subf", // PPC_INS_SUBF, + "subfc", // PPC_INS_SUBFC, + "subfe", // PPC_INS_SUBFE, + "subfic", // PPC_INS_SUBFIC, + "subfme", // PPC_INS_SUBFME, + "subfze", // PPC_INS_SUBFZE, + "subi", // PPC_INS_SUBI, + "subic", // PPC_INS_SUBIC, + "subis", // PPC_INS_SUBIS, + "subpcis", // PPC_INS_SUBPCIS, + "sync", // PPC_INS_SYNC, + "tabort", // PPC_INS_TABORT, + "tabortdc", // PPC_INS_TABORTDC, + "tabortdci", // PPC_INS_TABORTDCI, + "tabortwc", // PPC_INS_TABORTWC, + "tabortwci", // PPC_INS_TABORTWCI, + "tbegin", // PPC_INS_TBEGIN, + "tcheck", // PPC_INS_TCHECK, + "td", // PPC_INS_TD, + "tdeq", // PPC_INS_TDEQ, + "tdeqi", // PPC_INS_TDEQI, + "tdge", // PPC_INS_TDGE, + "tdgei", // PPC_INS_TDGEI, + "tdgt", // PPC_INS_TDGT, + "tdgti", // PPC_INS_TDGTI, + "tdi", // PPC_INS_TDI, + "tdle", // PPC_INS_TDLE, + "tdlei", // PPC_INS_TDLEI, + "tdlge", // PPC_INS_TDLGE, + "tdlgei", // PPC_INS_TDLGEI, + "tdlgt", // PPC_INS_TDLGT, + "tdlgti", // PPC_INS_TDLGTI, + "tdlle", // PPC_INS_TDLLE, + "tdllei", // PPC_INS_TDLLEI, + "tdllt", // PPC_INS_TDLLT, + "tdllti", // PPC_INS_TDLLTI, + "tdlng", // PPC_INS_TDLNG, + "tdlngi", // PPC_INS_TDLNGI, + "tdlnl", // PPC_INS_TDLNL, + "tdlnli", // PPC_INS_TDLNLI, + "tdlt", // PPC_INS_TDLT, + "tdlti", // PPC_INS_TDLTI, + "tdne", // PPC_INS_TDNE, + "tdnei", // PPC_INS_TDNEI, + "tdng", // PPC_INS_TDNG, + "tdngi", // PPC_INS_TDNGI, + "tdnl", // PPC_INS_TDNL, + "tdnli", // PPC_INS_TDNLI, + "tdu", // PPC_INS_TDU, + "tdui", // PPC_INS_TDUI, + "tend", // PPC_INS_TEND, + "tlbia", // PPC_INS_TLBIA, + "tlbie", // PPC_INS_TLBIE, + "tlbiel", // PPC_INS_TLBIEL, + "tlbivax", // PPC_INS_TLBIVAX, + "tlbld", // PPC_INS_TLBLD, + "tlbli", // PPC_INS_TLBLI, + "tlbre", // PPC_INS_TLBRE, + "tlbrehi", // PPC_INS_TLBREHI, + "tlbrelo", // PPC_INS_TLBRELO, + "tlbsx", // PPC_INS_TLBSX, + "tlbsync", // PPC_INS_TLBSYNC, + "tlbwe", // PPC_INS_TLBWE, + "tlbwehi", // PPC_INS_TLBWEHI, + "tlbwelo", // PPC_INS_TLBWELO, + "trap", // PPC_INS_TRAP, + "trechkpt", // PPC_INS_TRECHKPT, + "treclaim", // PPC_INS_TRECLAIM, + "tsr", // PPC_INS_TSR, + "tw", // PPC_INS_TW, + "tweq", // PPC_INS_TWEQ, + "tweqi", // PPC_INS_TWEQI, + "twge", // PPC_INS_TWGE, + "twgei", // PPC_INS_TWGEI, + "twgt", // PPC_INS_TWGT, + "twgti", // PPC_INS_TWGTI, + "twi", // PPC_INS_TWI, + "twle", // PPC_INS_TWLE, + "twlei", // PPC_INS_TWLEI, + "twlge", // PPC_INS_TWLGE, + "twlgei", // PPC_INS_TWLGEI, + "twlgt", // PPC_INS_TWLGT, + "twlgti", // PPC_INS_TWLGTI, + "twlle", // PPC_INS_TWLLE, + "twllei", // PPC_INS_TWLLEI, + "twllt", // PPC_INS_TWLLT, + "twllti", // PPC_INS_TWLLTI, + "twlng", // PPC_INS_TWLNG, + "twlngi", // PPC_INS_TWLNGI, + "twlnl", // PPC_INS_TWLNL, + "twlnli", // PPC_INS_TWLNLI, + "twlt", // PPC_INS_TWLT, + "twlti", // PPC_INS_TWLTI, + "twne", // PPC_INS_TWNE, + "twnei", // PPC_INS_TWNEI, + "twng", // PPC_INS_TWNG, + "twngi", // PPC_INS_TWNGI, + "twnl", // PPC_INS_TWNL, + "twnli", // PPC_INS_TWNLI, + "twu", // PPC_INS_TWU, + "twui", // PPC_INS_TWUI, + "vabsdub", // PPC_INS_VABSDUB, + "vabsduh", // PPC_INS_VABSDUH, + "vabsduw", // PPC_INS_VABSDUW, + "vaddcuq", // PPC_INS_VADDCUQ, + "vaddcuw", // PPC_INS_VADDCUW, + "vaddecuq", // PPC_INS_VADDECUQ, + "vaddeuqm", // PPC_INS_VADDEUQM, + "vaddfp", // PPC_INS_VADDFP, + "vaddsbs", // PPC_INS_VADDSBS, + "vaddshs", // PPC_INS_VADDSHS, + "vaddsws", // PPC_INS_VADDSWS, + "vaddubm", // PPC_INS_VADDUBM, + "vaddubs", // PPC_INS_VADDUBS, + "vaddudm", // PPC_INS_VADDUDM, + "vadduhm", // PPC_INS_VADDUHM, + "vadduhs", // PPC_INS_VADDUHS, + "vadduqm", // PPC_INS_VADDUQM, + "vadduwm", // PPC_INS_VADDUWM, + "vadduws", // PPC_INS_VADDUWS, + "vand", // PPC_INS_VAND, + "vandc", // PPC_INS_VANDC, + "vavgsb", // PPC_INS_VAVGSB, + "vavgsh", // PPC_INS_VAVGSH, + "vavgsw", // PPC_INS_VAVGSW, + "vavgub", // PPC_INS_VAVGUB, + "vavguh", // PPC_INS_VAVGUH, + "vavguw", // PPC_INS_VAVGUW, + "vbpermd", // PPC_INS_VBPERMD, + "vbpermq", // PPC_INS_VBPERMQ, + "vcfsx", // PPC_INS_VCFSX, + "vcfux", // PPC_INS_VCFUX, + "vcipher", // PPC_INS_VCIPHER, + "vcipherlast", // PPC_INS_VCIPHERLAST, + "vclzb", // PPC_INS_VCLZB, + "vclzd", // PPC_INS_VCLZD, + "vclzh", // PPC_INS_VCLZH, + "vclzlsbb", // PPC_INS_VCLZLSBB, + "vclzw", // PPC_INS_VCLZW, + "vcmpbfp", // PPC_INS_VCMPBFP, + "vcmpeqfp", // PPC_INS_VCMPEQFP, + "vcmpequb", // PPC_INS_VCMPEQUB, + "vcmpequd", // PPC_INS_VCMPEQUD, + "vcmpequh", // PPC_INS_VCMPEQUH, + "vcmpequw", // PPC_INS_VCMPEQUW, + "vcmpgefp", // PPC_INS_VCMPGEFP, + "vcmpgtfp", // PPC_INS_VCMPGTFP, + "vcmpgtsb", // PPC_INS_VCMPGTSB, + "vcmpgtsd", // PPC_INS_VCMPGTSD, + "vcmpgtsh", // PPC_INS_VCMPGTSH, + "vcmpgtsw", // PPC_INS_VCMPGTSW, + "vcmpgtub", // PPC_INS_VCMPGTUB, + "vcmpgtud", // PPC_INS_VCMPGTUD, + "vcmpgtuh", // PPC_INS_VCMPGTUH, + "vcmpgtuw", // PPC_INS_VCMPGTUW, + "vcmpneb", // PPC_INS_VCMPNEB, + "vcmpneh", // PPC_INS_VCMPNEH, + "vcmpnew", // PPC_INS_VCMPNEW, + "vcmpnezb", // PPC_INS_VCMPNEZB, + "vcmpnezh", // PPC_INS_VCMPNEZH, + "vcmpnezw", // PPC_INS_VCMPNEZW, + "vctsxs", // PPC_INS_VCTSXS, + "vctuxs", // PPC_INS_VCTUXS, + "vctzb", // PPC_INS_VCTZB, + "vctzd", // PPC_INS_VCTZD, + "vctzh", // PPC_INS_VCTZH, + "vctzlsbb", // PPC_INS_VCTZLSBB, + "vctzw", // PPC_INS_VCTZW, + "veqv", // PPC_INS_VEQV, + "vexptefp", // PPC_INS_VEXPTEFP, + "vextractd", // PPC_INS_VEXTRACTD, + "vextractub", // PPC_INS_VEXTRACTUB, + "vextractuh", // PPC_INS_VEXTRACTUH, + "vextractuw", // PPC_INS_VEXTRACTUW, + "vextsb2d", // PPC_INS_VEXTSB2D, + "vextsb2w", // PPC_INS_VEXTSB2W, + "vextsh2d", // PPC_INS_VEXTSH2D, + "vextsh2w", // PPC_INS_VEXTSH2W, + "vextsw2d", // PPC_INS_VEXTSW2D, + "vextublx", // PPC_INS_VEXTUBLX, + "vextubrx", // PPC_INS_VEXTUBRX, + "vextuhlx", // PPC_INS_VEXTUHLX, + "vextuhrx", // PPC_INS_VEXTUHRX, + "vextuwlx", // PPC_INS_VEXTUWLX, + "vextuwrx", // PPC_INS_VEXTUWRX, + "vgbbd", // PPC_INS_VGBBD, + "vinsertb", // PPC_INS_VINSERTB, + "vinsertd", // PPC_INS_VINSERTD, + "vinserth", // PPC_INS_VINSERTH, + "vinsertw", // PPC_INS_VINSERTW, + "vlogefp", // PPC_INS_VLOGEFP, + "vmaddfp", // PPC_INS_VMADDFP, + "vmaxfp", // PPC_INS_VMAXFP, + "vmaxsb", // PPC_INS_VMAXSB, + "vmaxsd", // PPC_INS_VMAXSD, + "vmaxsh", // PPC_INS_VMAXSH, + "vmaxsw", // PPC_INS_VMAXSW, + "vmaxub", // PPC_INS_VMAXUB, + "vmaxud", // PPC_INS_VMAXUD, + "vmaxuh", // PPC_INS_VMAXUH, + "vmaxuw", // PPC_INS_VMAXUW, + "vmhaddshs", // PPC_INS_VMHADDSHS, + "vmhraddshs", // PPC_INS_VMHRADDSHS, + "vminfp", // PPC_INS_VMINFP, + "vminsb", // PPC_INS_VMINSB, + "vminsd", // PPC_INS_VMINSD, + "vminsh", // PPC_INS_VMINSH, + "vminsw", // PPC_INS_VMINSW, + "vminub", // PPC_INS_VMINUB, + "vminud", // PPC_INS_VMINUD, + "vminuh", // PPC_INS_VMINUH, + "vminuw", // PPC_INS_VMINUW, + "vmladduhm", // PPC_INS_VMLADDUHM, + "vmr", // PPC_INS_VMR, + "vmrgew", // PPC_INS_VMRGEW, + "vmrghb", // PPC_INS_VMRGHB, + "vmrghh", // PPC_INS_VMRGHH, + "vmrghw", // PPC_INS_VMRGHW, + "vmrglb", // PPC_INS_VMRGLB, + "vmrglh", // PPC_INS_VMRGLH, + "vmrglw", // PPC_INS_VMRGLW, + "vmrgow", // PPC_INS_VMRGOW, + "vmsummbm", // PPC_INS_VMSUMMBM, + "vmsumshm", // PPC_INS_VMSUMSHM, + "vmsumshs", // PPC_INS_VMSUMSHS, + "vmsumubm", // PPC_INS_VMSUMUBM, + "vmsumuhm", // PPC_INS_VMSUMUHM, + "vmsumuhs", // PPC_INS_VMSUMUHS, + "vmul10cuq", // PPC_INS_VMUL10CUQ, + "vmul10ecuq", // PPC_INS_VMUL10ECUQ, + "vmul10euq", // PPC_INS_VMUL10EUQ, + "vmul10uq", // PPC_INS_VMUL10UQ, + "vmulesb", // PPC_INS_VMULESB, + "vmulesh", // PPC_INS_VMULESH, + "vmulesw", // PPC_INS_VMULESW, + "vmuleub", // PPC_INS_VMULEUB, + "vmuleuh", // PPC_INS_VMULEUH, + "vmuleuw", // PPC_INS_VMULEUW, + "vmulosb", // PPC_INS_VMULOSB, + "vmulosh", // PPC_INS_VMULOSH, + "vmulosw", // PPC_INS_VMULOSW, + "vmuloub", // PPC_INS_VMULOUB, + "vmulouh", // PPC_INS_VMULOUH, + "vmulouw", // PPC_INS_VMULOUW, + "vmuluwm", // PPC_INS_VMULUWM, + "vnand", // PPC_INS_VNAND, + "vncipher", // PPC_INS_VNCIPHER, + "vncipherlast", // PPC_INS_VNCIPHERLAST, + "vnegd", // PPC_INS_VNEGD, + "vnegw", // PPC_INS_VNEGW, + "vnmsubfp", // PPC_INS_VNMSUBFP, + "vnor", // PPC_INS_VNOR, + "vnot", // PPC_INS_VNOT, + "vor", // PPC_INS_VOR, + "vorc", // PPC_INS_VORC, + "vperm", // PPC_INS_VPERM, + "vpermr", // PPC_INS_VPERMR, + "vpermxor", // PPC_INS_VPERMXOR, + "vpkpx", // PPC_INS_VPKPX, + "vpksdss", // PPC_INS_VPKSDSS, + "vpksdus", // PPC_INS_VPKSDUS, + "vpkshss", // PPC_INS_VPKSHSS, + "vpkshus", // PPC_INS_VPKSHUS, + "vpkswss", // PPC_INS_VPKSWSS, + "vpkswus", // PPC_INS_VPKSWUS, + "vpkudum", // PPC_INS_VPKUDUM, + "vpkudus", // PPC_INS_VPKUDUS, + "vpkuhum", // PPC_INS_VPKUHUM, + "vpkuhus", // PPC_INS_VPKUHUS, + "vpkuwum", // PPC_INS_VPKUWUM, + "vpkuwus", // PPC_INS_VPKUWUS, + "vpmsumb", // PPC_INS_VPMSUMB, + "vpmsumd", // PPC_INS_VPMSUMD, + "vpmsumh", // PPC_INS_VPMSUMH, + "vpmsumw", // PPC_INS_VPMSUMW, + "vpopcntb", // PPC_INS_VPOPCNTB, + "vpopcntd", // PPC_INS_VPOPCNTD, + "vpopcnth", // PPC_INS_VPOPCNTH, + "vpopcntw", // PPC_INS_VPOPCNTW, + "vprtybd", // PPC_INS_VPRTYBD, + "vprtybq", // PPC_INS_VPRTYBQ, + "vprtybw", // PPC_INS_VPRTYBW, + "vrefp", // PPC_INS_VREFP, + "vrfim", // PPC_INS_VRFIM, + "vrfin", // PPC_INS_VRFIN, + "vrfip", // PPC_INS_VRFIP, + "vrfiz", // PPC_INS_VRFIZ, + "vrlb", // PPC_INS_VRLB, + "vrld", // PPC_INS_VRLD, + "vrldmi", // PPC_INS_VRLDMI, + "vrldnm", // PPC_INS_VRLDNM, + "vrlh", // PPC_INS_VRLH, + "vrlw", // PPC_INS_VRLW, + "vrlwmi", // PPC_INS_VRLWMI, + "vrlwnm", // PPC_INS_VRLWNM, + "vrsqrtefp", // PPC_INS_VRSQRTEFP, + "vsbox", // PPC_INS_VSBOX, + "vsel", // PPC_INS_VSEL, + "vshasigmad", // PPC_INS_VSHASIGMAD, + "vshasigmaw", // PPC_INS_VSHASIGMAW, + "vsl", // PPC_INS_VSL, + "vslb", // PPC_INS_VSLB, + "vsld", // PPC_INS_VSLD, + "vsldoi", // PPC_INS_VSLDOI, + "vslh", // PPC_INS_VSLH, + "vslo", // PPC_INS_VSLO, + "vslv", // PPC_INS_VSLV, + "vslw", // PPC_INS_VSLW, + "vspltb", // PPC_INS_VSPLTB, + "vsplth", // PPC_INS_VSPLTH, + "vspltisb", // PPC_INS_VSPLTISB, + "vspltish", // PPC_INS_VSPLTISH, + "vspltisw", // PPC_INS_VSPLTISW, + "vspltw", // PPC_INS_VSPLTW, + "vsr", // PPC_INS_VSR, + "vsrab", // PPC_INS_VSRAB, + "vsrad", // PPC_INS_VSRAD, + "vsrah", // PPC_INS_VSRAH, + "vsraw", // PPC_INS_VSRAW, + "vsrb", // PPC_INS_VSRB, + "vsrd", // PPC_INS_VSRD, + "vsrh", // PPC_INS_VSRH, + "vsro", // PPC_INS_VSRO, + "vsrv", // PPC_INS_VSRV, + "vsrw", // PPC_INS_VSRW, + "vsubcuq", // PPC_INS_VSUBCUQ, + "vsubcuw", // PPC_INS_VSUBCUW, + "vsubecuq", // PPC_INS_VSUBECUQ, + "vsubeuqm", // PPC_INS_VSUBEUQM, + "vsubfp", // PPC_INS_VSUBFP, + "vsubsbs", // PPC_INS_VSUBSBS, + "vsubshs", // PPC_INS_VSUBSHS, + "vsubsws", // PPC_INS_VSUBSWS, + "vsububm", // PPC_INS_VSUBUBM, + "vsububs", // PPC_INS_VSUBUBS, + "vsubudm", // PPC_INS_VSUBUDM, + "vsubuhm", // PPC_INS_VSUBUHM, + "vsubuhs", // PPC_INS_VSUBUHS, + "vsubuqm", // PPC_INS_VSUBUQM, + "vsubuwm", // PPC_INS_VSUBUWM, + "vsubuws", // PPC_INS_VSUBUWS, + "vsum2sws", // PPC_INS_VSUM2SWS, + "vsum4sbs", // PPC_INS_VSUM4SBS, + "vsum4shs", // PPC_INS_VSUM4SHS, + "vsum4ubs", // PPC_INS_VSUM4UBS, + "vsumsws", // PPC_INS_VSUMSWS, + "vupkhpx", // PPC_INS_VUPKHPX, + "vupkhsb", // PPC_INS_VUPKHSB, + "vupkhsh", // PPC_INS_VUPKHSH, + "vupkhsw", // PPC_INS_VUPKHSW, + "vupklpx", // PPC_INS_VUPKLPX, + "vupklsb", // PPC_INS_VUPKLSB, + "vupklsh", // PPC_INS_VUPKLSH, + "vupklsw", // PPC_INS_VUPKLSW, + "vxor", // PPC_INS_VXOR, + "wait", // PPC_INS_WAIT, + "waitimpl", // PPC_INS_WAITIMPL, + "waitrsv", // PPC_INS_WAITRSV, + "wrtee", // PPC_INS_WRTEE, + "wrteei", // PPC_INS_WRTEEI, + "xnop", // PPC_INS_XNOP, + "xor", // PPC_INS_XOR, + "xori", // PPC_INS_XORI, + "xoris", // PPC_INS_XORIS, + "xsabsdp", // PPC_INS_XSABSDP, + "xsabsqp", // PPC_INS_XSABSQP, + "xsadddp", // PPC_INS_XSADDDP, + "xsaddqp", // PPC_INS_XSADDQP, + "xsaddqpo", // PPC_INS_XSADDQPO, + "xsaddsp", // PPC_INS_XSADDSP, + "xscmpeqdp", // PPC_INS_XSCMPEQDP, + "xscmpexpdp", // PPC_INS_XSCMPEXPDP, + "xscmpexpqp", // PPC_INS_XSCMPEXPQP, + "xscmpgedp", // PPC_INS_XSCMPGEDP, + "xscmpgtdp", // PPC_INS_XSCMPGTDP, + "xscmpodp", // PPC_INS_XSCMPODP, + "xscmpoqp", // PPC_INS_XSCMPOQP, + "xscmpudp", // PPC_INS_XSCMPUDP, + "xscmpuqp", // PPC_INS_XSCMPUQP, + "xscpsgndp", // PPC_INS_XSCPSGNDP, + "xscpsgnqp", // PPC_INS_XSCPSGNQP, + "xscvdphp", // PPC_INS_XSCVDPHP, + "xscvdpqp", // PPC_INS_XSCVDPQP, + "xscvdpsp", // PPC_INS_XSCVDPSP, + "xscvdpspn", // PPC_INS_XSCVDPSPN, + "xscvdpsxds", // PPC_INS_XSCVDPSXDS, + "xscvdpsxws", // PPC_INS_XSCVDPSXWS, + "xscvdpuxds", // PPC_INS_XSCVDPUXDS, + "xscvdpuxws", // PPC_INS_XSCVDPUXWS, + "xscvhpdp", // PPC_INS_XSCVHPDP, + "xscvqpdp", // PPC_INS_XSCVQPDP, + "xscvqpdpo", // PPC_INS_XSCVQPDPO, + "xscvqpsdz", // PPC_INS_XSCVQPSDZ, + "xscvqpswz", // PPC_INS_XSCVQPSWZ, + "xscvqpudz", // PPC_INS_XSCVQPUDZ, + "xscvqpuwz", // PPC_INS_XSCVQPUWZ, + "xscvsdqp", // PPC_INS_XSCVSDQP, + "xscvspdp", // PPC_INS_XSCVSPDP, + "xscvspdpn", // PPC_INS_XSCVSPDPN, + "xscvsxddp", // PPC_INS_XSCVSXDDP, + "xscvsxdsp", // PPC_INS_XSCVSXDSP, + "xscvudqp", // PPC_INS_XSCVUDQP, + "xscvuxddp", // PPC_INS_XSCVUXDDP, + "xscvuxdsp", // PPC_INS_XSCVUXDSP, + "xsdivdp", // PPC_INS_XSDIVDP, + "xsdivqp", // PPC_INS_XSDIVQP, + "xsdivqpo", // PPC_INS_XSDIVQPO, + "xsdivsp", // PPC_INS_XSDIVSP, + "xsiexpdp", // PPC_INS_XSIEXPDP, + "xsiexpqp", // PPC_INS_XSIEXPQP, + "xsmaddadp", // PPC_INS_XSMADDADP, + "xsmaddasp", // PPC_INS_XSMADDASP, + "xsmaddmdp", // PPC_INS_XSMADDMDP, + "xsmaddmsp", // PPC_INS_XSMADDMSP, + "xsmaddqp", // PPC_INS_XSMADDQP, + "xsmaddqpo", // PPC_INS_XSMADDQPO, + "xsmaxcdp", // PPC_INS_XSMAXCDP, + "xsmaxdp", // PPC_INS_XSMAXDP, + "xsmaxjdp", // PPC_INS_XSMAXJDP, + "xsmincdp", // PPC_INS_XSMINCDP, + "xsmindp", // PPC_INS_XSMINDP, + "xsminjdp", // PPC_INS_XSMINJDP, + "xsmsubadp", // PPC_INS_XSMSUBADP, + "xsmsubasp", // PPC_INS_XSMSUBASP, + "xsmsubmdp", // PPC_INS_XSMSUBMDP, + "xsmsubmsp", // PPC_INS_XSMSUBMSP, + "xsmsubqp", // PPC_INS_XSMSUBQP, + "xsmsubqpo", // PPC_INS_XSMSUBQPO, + "xsmuldp", // PPC_INS_XSMULDP, + "xsmulqp", // PPC_INS_XSMULQP, + "xsmulqpo", // PPC_INS_XSMULQPO, + "xsmulsp", // PPC_INS_XSMULSP, + "xsnabsdp", // PPC_INS_XSNABSDP, + "xsnabsqp", // PPC_INS_XSNABSQP, + "xsnegdp", // PPC_INS_XSNEGDP, + "xsnegqp", // PPC_INS_XSNEGQP, + "xsnmaddadp", // PPC_INS_XSNMADDADP, + "xsnmaddasp", // PPC_INS_XSNMADDASP, + "xsnmaddmdp", // PPC_INS_XSNMADDMDP, + "xsnmaddmsp", // PPC_INS_XSNMADDMSP, + "xsnmaddqp", // PPC_INS_XSNMADDQP, + "xsnmaddqpo", // PPC_INS_XSNMADDQPO, + "xsnmsubadp", // PPC_INS_XSNMSUBADP, + "xsnmsubasp", // PPC_INS_XSNMSUBASP, + "xsnmsubmdp", // PPC_INS_XSNMSUBMDP, + "xsnmsubmsp", // PPC_INS_XSNMSUBMSP, + "xsnmsubqp", // PPC_INS_XSNMSUBQP, + "xsnmsubqpo", // PPC_INS_XSNMSUBQPO, + "xsrdpi", // PPC_INS_XSRDPI, + "xsrdpic", // PPC_INS_XSRDPIC, + "xsrdpim", // PPC_INS_XSRDPIM, + "xsrdpip", // PPC_INS_XSRDPIP, + "xsrdpiz", // PPC_INS_XSRDPIZ, + "xsredp", // PPC_INS_XSREDP, + "xsresp", // PPC_INS_XSRESP, + "xsrqpi", // PPC_INS_XSRQPI, + "xsrqpix", // PPC_INS_XSRQPIX, + "xsrqpxp", // PPC_INS_XSRQPXP, + "xsrsp", // PPC_INS_XSRSP, + "xsrsqrtedp", // PPC_INS_XSRSQRTEDP, + "xsrsqrtesp", // PPC_INS_XSRSQRTESP, + "xssqrtdp", // PPC_INS_XSSQRTDP, + "xssqrtqp", // PPC_INS_XSSQRTQP, + "xssqrtqpo", // PPC_INS_XSSQRTQPO, + "xssqrtsp", // PPC_INS_XSSQRTSP, + "xssubdp", // PPC_INS_XSSUBDP, + "xssubqp", // PPC_INS_XSSUBQP, + "xssubqpo", // PPC_INS_XSSUBQPO, + "xssubsp", // PPC_INS_XSSUBSP, + "xstdivdp", // PPC_INS_XSTDIVDP, + "xstsqrtdp", // PPC_INS_XSTSQRTDP, + "xststdcdp", // PPC_INS_XSTSTDCDP, + "xststdcqp", // PPC_INS_XSTSTDCQP, + "xststdcsp", // PPC_INS_XSTSTDCSP, + "xsxexpdp", // PPC_INS_XSXEXPDP, + "xsxexpqp", // PPC_INS_XSXEXPQP, + "xsxsigdp", // PPC_INS_XSXSIGDP, + "xsxsigqp", // PPC_INS_XSXSIGQP, + "xvabsdp", // PPC_INS_XVABSDP, + "xvabssp", // PPC_INS_XVABSSP, + "xvadddp", // PPC_INS_XVADDDP, + "xvaddsp", // PPC_INS_XVADDSP, + "xvcmpeqdp", // PPC_INS_XVCMPEQDP, + "xvcmpeqsp", // PPC_INS_XVCMPEQSP, + "xvcmpgedp", // PPC_INS_XVCMPGEDP, + "xvcmpgesp", // PPC_INS_XVCMPGESP, + "xvcmpgtdp", // PPC_INS_XVCMPGTDP, + "xvcmpgtsp", // PPC_INS_XVCMPGTSP, + "xvcpsgndp", // PPC_INS_XVCPSGNDP, + "xvcpsgnsp", // PPC_INS_XVCPSGNSP, + "xvcvdpsp", // PPC_INS_XVCVDPSP, + "xvcvdpsxds", // PPC_INS_XVCVDPSXDS, + "xvcvdpsxws", // PPC_INS_XVCVDPSXWS, + "xvcvdpuxds", // PPC_INS_XVCVDPUXDS, + "xvcvdpuxws", // PPC_INS_XVCVDPUXWS, + "xvcvhpsp", // PPC_INS_XVCVHPSP, + "xvcvspdp", // PPC_INS_XVCVSPDP, + "xvcvsphp", // PPC_INS_XVCVSPHP, + "xvcvspsxds", // PPC_INS_XVCVSPSXDS, + "xvcvspsxws", // PPC_INS_XVCVSPSXWS, + "xvcvspuxds", // PPC_INS_XVCVSPUXDS, + "xvcvspuxws", // PPC_INS_XVCVSPUXWS, + "xvcvsxddp", // PPC_INS_XVCVSXDDP, + "xvcvsxdsp", // PPC_INS_XVCVSXDSP, + "xvcvsxwdp", // PPC_INS_XVCVSXWDP, + "xvcvsxwsp", // PPC_INS_XVCVSXWSP, + "xvcvuxddp", // PPC_INS_XVCVUXDDP, + "xvcvuxdsp", // PPC_INS_XVCVUXDSP, + "xvcvuxwdp", // PPC_INS_XVCVUXWDP, + "xvcvuxwsp", // PPC_INS_XVCVUXWSP, + "xvdivdp", // PPC_INS_XVDIVDP, + "xvdivsp", // PPC_INS_XVDIVSP, + "xviexpdp", // PPC_INS_XVIEXPDP, + "xviexpsp", // PPC_INS_XVIEXPSP, + "xvmaddadp", // PPC_INS_XVMADDADP, + "xvmaddasp", // PPC_INS_XVMADDASP, + "xvmaddmdp", // PPC_INS_XVMADDMDP, + "xvmaddmsp", // PPC_INS_XVMADDMSP, + "xvmaxdp", // PPC_INS_XVMAXDP, + "xvmaxsp", // PPC_INS_XVMAXSP, + "xvmindp", // PPC_INS_XVMINDP, + "xvminsp", // PPC_INS_XVMINSP, + "xvmovdp", // PPC_INS_XVMOVDP, + "xvmovsp", // PPC_INS_XVMOVSP, + "xvmsubadp", // PPC_INS_XVMSUBADP, + "xvmsubasp", // PPC_INS_XVMSUBASP, + "xvmsubmdp", // PPC_INS_XVMSUBMDP, + "xvmsubmsp", // PPC_INS_XVMSUBMSP, + "xvmuldp", // PPC_INS_XVMULDP, + "xvmulsp", // PPC_INS_XVMULSP, + "xvnabsdp", // PPC_INS_XVNABSDP, + "xvnabssp", // PPC_INS_XVNABSSP, + "xvnegdp", // PPC_INS_XVNEGDP, + "xvnegsp", // PPC_INS_XVNEGSP, + "xvnmaddadp", // PPC_INS_XVNMADDADP, + "xvnmaddasp", // PPC_INS_XVNMADDASP, + "xvnmaddmdp", // PPC_INS_XVNMADDMDP, + "xvnmaddmsp", // PPC_INS_XVNMADDMSP, + "xvnmsubadp", // PPC_INS_XVNMSUBADP, + "xvnmsubasp", // PPC_INS_XVNMSUBASP, + "xvnmsubmdp", // PPC_INS_XVNMSUBMDP, + "xvnmsubmsp", // PPC_INS_XVNMSUBMSP, + "xvrdpi", // PPC_INS_XVRDPI, + "xvrdpic", // PPC_INS_XVRDPIC, + "xvrdpim", // PPC_INS_XVRDPIM, + "xvrdpip", // PPC_INS_XVRDPIP, + "xvrdpiz", // PPC_INS_XVRDPIZ, + "xvredp", // PPC_INS_XVREDP, + "xvresp", // PPC_INS_XVRESP, + "xvrspi", // PPC_INS_XVRSPI, + "xvrspic", // PPC_INS_XVRSPIC, + "xvrspim", // PPC_INS_XVRSPIM, + "xvrspip", // PPC_INS_XVRSPIP, + "xvrspiz", // PPC_INS_XVRSPIZ, + "xvrsqrtedp", // PPC_INS_XVRSQRTEDP, + "xvrsqrtesp", // PPC_INS_XVRSQRTESP, + "xvsqrtdp", // PPC_INS_XVSQRTDP, + "xvsqrtsp", // PPC_INS_XVSQRTSP, + "xvsubdp", // PPC_INS_XVSUBDP, + "xvsubsp", // PPC_INS_XVSUBSP, + "xvtdivdp", // PPC_INS_XVTDIVDP, + "xvtdivsp", // PPC_INS_XVTDIVSP, + "xvtsqrtdp", // PPC_INS_XVTSQRTDP, + "xvtsqrtsp", // PPC_INS_XVTSQRTSP, + "xvtstdcdp", // PPC_INS_XVTSTDCDP, + "xvtstdcsp", // PPC_INS_XVTSTDCSP, + "xvxexpdp", // PPC_INS_XVXEXPDP, + "xvxexpsp", // PPC_INS_XVXEXPSP, + "xvxsigdp", // PPC_INS_XVXSIGDP, + "xvxsigsp", // PPC_INS_XVXSIGSP, + "xxbrd", // PPC_INS_XXBRD, + "xxbrh", // PPC_INS_XXBRH, + "xxbrq", // PPC_INS_XXBRQ, + "xxbrw", // PPC_INS_XXBRW, + "xxextractuw", // PPC_INS_XXEXTRACTUW, + "xxinsertw", // PPC_INS_XXINSERTW, + "xxland", // PPC_INS_XXLAND, + "xxlandc", // PPC_INS_XXLANDC, + "xxleqv", // PPC_INS_XXLEQV, + "xxlnand", // PPC_INS_XXLNAND, + "xxlnor", // PPC_INS_XXLNOR, + "xxlor", // PPC_INS_XXLOR, + "xxlorc", // PPC_INS_XXLORC, + "xxlxor", // PPC_INS_XXLXOR, + "xxmrghd", // PPC_INS_XXMRGHD, + "xxmrghw", // PPC_INS_XXMRGHW, + "xxmrgld", // PPC_INS_XXMRGLD, + "xxmrglw", // PPC_INS_XXMRGLW, + "xxperm", // PPC_INS_XXPERM, + "xxpermdi", // PPC_INS_XXPERMDI, + "xxpermr", // PPC_INS_XXPERMR, + "xxsel", // PPC_INS_XXSEL, + "xxsldwi", // PPC_INS_XXSLDWI, + "xxspltd", // PPC_INS_XXSPLTD, + "xxspltib", // PPC_INS_XXSPLTIB, + "xxspltw", // PPC_INS_XXSPLTW, + "xxswapd", // PPC_INS_XXSWAPD, diff --git a/arch/PowerPC/PPCModule.c b/arch/PowerPC/PPCModule.c index 794b9a8194..de6620522b 100644 --- a/arch/PowerPC/PPCModule.c +++ b/arch/PowerPC/PPCModule.c @@ -3,43 +3,41 @@ #ifdef CAPSTONE_HAS_POWERPC -#include "../../utils.h" +#include "PPCModule.h" #include "../../MCRegisterInfo.h" +#include "../../utils.h" #include "PPCDisassembler.h" #include "PPCInstPrinter.h" #include "PPCMapping.h" -#include "PPCModule.h" -cs_err PPC_global_init(cs_struct *ud) -{ - MCRegisterInfo *mri; - mri = (MCRegisterInfo *) cs_mem_malloc(sizeof(*mri)); +cs_err PPC_global_init(cs_struct *ud) { + MCRegisterInfo *mri; + mri = (MCRegisterInfo *)cs_mem_malloc(sizeof(*mri)); - PPC_init(mri); - ud->printer = PPC_printInst; - ud->printer_info = mri; - ud->getinsn_info = mri; - ud->disasm = PPC_getInstruction; - ud->post_printer = PPC_post_printer; + PPC_init(mri); + ud->printer = PPC_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = PPC_getInstruction; + ud->post_printer = PPC_post_printer; - ud->reg_name = PPC_reg_name; - ud->insn_id = PPC_get_insn_id; - ud->insn_name = PPC_insn_name; - ud->group_name = PPC_group_name; + ud->reg_name = PPC_reg_name; + ud->insn_id = PPC_get_insn_id; + ud->insn_name = PPC_insn_name; + ud->group_name = PPC_group_name; - return CS_ERR_OK; + return CS_ERR_OK; } -cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value) -{ - if (type == CS_OPT_SYNTAX) - handle->syntax = (int) value; +cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value) { + if (type == CS_OPT_SYNTAX) + handle->syntax = (int)value; - if (type == CS_OPT_MODE) { - handle->mode = (cs_mode)value; - } + if (type == CS_OPT_MODE) { + handle->mode = (cs_mode)value; + } - return CS_ERR_OK; + return CS_ERR_OK; } #endif diff --git a/arch/PowerPC/PPCPredicates.h b/arch/PowerPC/PPCPredicates.h index 03d55666f0..adf4517667 100644 --- a/arch/PowerPC/PPCPredicates.h +++ b/arch/PowerPC/PPCPredicates.h @@ -21,34 +21,34 @@ // NOTE: duplicate of ppc_bc in ppc.h to maitain code compatibility with LLVM typedef enum ppc_predicate { - PPC_PRED_LT = (0 << 5) | 12, - PPC_PRED_LE = (1 << 5) | 4, - PPC_PRED_EQ = (2 << 5) | 12, - PPC_PRED_GE = (0 << 5) | 4, - PPC_PRED_GT = (1 << 5) | 12, - PPC_PRED_NE = (2 << 5) | 4, - PPC_PRED_UN = (3 << 5) | 12, - PPC_PRED_NU = (3 << 5) | 4, + PPC_PRED_LT = (0 << 5) | 12, + PPC_PRED_LE = (1 << 5) | 4, + PPC_PRED_EQ = (2 << 5) | 12, + PPC_PRED_GE = (0 << 5) | 4, + PPC_PRED_GT = (1 << 5) | 12, + PPC_PRED_NE = (2 << 5) | 4, + PPC_PRED_UN = (3 << 5) | 12, + PPC_PRED_NU = (3 << 5) | 4, PPC_PRED_LT_MINUS = (0 << 5) | 14, - PPC_PRED_LE_MINUS = (1 << 5) | 6, + PPC_PRED_LE_MINUS = (1 << 5) | 6, PPC_PRED_EQ_MINUS = (2 << 5) | 14, - PPC_PRED_GE_MINUS = (0 << 5) | 6, + PPC_PRED_GE_MINUS = (0 << 5) | 6, PPC_PRED_GT_MINUS = (1 << 5) | 14, - PPC_PRED_NE_MINUS = (2 << 5) | 6, + PPC_PRED_NE_MINUS = (2 << 5) | 6, PPC_PRED_UN_MINUS = (3 << 5) | 14, - PPC_PRED_NU_MINUS = (3 << 5) | 6, - PPC_PRED_LT_PLUS = (0 << 5) | 15, - PPC_PRED_LE_PLUS = (1 << 5) | 7, - PPC_PRED_EQ_PLUS = (2 << 5) | 15, - PPC_PRED_GE_PLUS = (0 << 5) | 7, - PPC_PRED_GT_PLUS = (1 << 5) | 15, - PPC_PRED_NE_PLUS = (2 << 5) | 7, - PPC_PRED_UN_PLUS = (3 << 5) | 15, - PPC_PRED_NU_PLUS = (3 << 5) | 7, + PPC_PRED_NU_MINUS = (3 << 5) | 6, + PPC_PRED_LT_PLUS = (0 << 5) | 15, + PPC_PRED_LE_PLUS = (1 << 5) | 7, + PPC_PRED_EQ_PLUS = (2 << 5) | 15, + PPC_PRED_GE_PLUS = (0 << 5) | 7, + PPC_PRED_GT_PLUS = (1 << 5) | 15, + PPC_PRED_NE_PLUS = (2 << 5) | 7, + PPC_PRED_UN_PLUS = (3 << 5) | 15, + PPC_PRED_NU_PLUS = (3 << 5) | 7, // When dealing with individual condition-register bits, we have simple set // and unset predicates. - PPC_PRED_BIT_SET = 1024, + PPC_PRED_BIT_SET = 1024, PPC_PRED_BIT_UNSET = 1025 } ppc_predicate; diff --git a/arch/RISCV/CapstoneRISCVModule.h b/arch/RISCV/CapstoneRISCVModule.h new file mode 100644 index 0000000000..999f52e846 --- /dev/null +++ b/arch/RISCV/CapstoneRISCVModule.h @@ -0,0 +1,492 @@ +// +// Created by Phosphorus15 on 2021/7/7. +// + +#ifndef CAPSTONE_CAPSTONERISCVMODULE_H +#define CAPSTONE_CAPSTONERISCVMODULE_H + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} + +static DecodeStatus DecodeVRRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVRM2RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVRM4RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeVRM8RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeVMaskReg(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeRVCInstrSImm(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeRVCInstrRdSImm(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeRVCInstrRdRs2(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFPR32CRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFPR64CRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder, + unsigned N); + +static DecodeStatus decodeUImmNonZeroOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder, unsigned N); + +static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder, + unsigned N); + +static DecodeStatus decodeSImmNonZeroOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder, unsigned N); + +static DecodeStatus decodeSImmOperandAndLsl1(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder, unsigned N); + +static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder); + +static DecodeStatus decodeFRMArg(MCInst *Inst, uint64_t Imm, int64_t Address, + const void *Decoder); + +#define GET_REGINFO_ENUM +#define GET_INSTRINFO_ENUM +#define MIPS_GET_DISASSEMBLER +#define GET_REGINFO_MC_DESC +#include "RISCVGenDisassemblerTables.inc" + +static const unsigned GPRDecoderTable[] = { + RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, RISCV_X5, RISCV_X6, + RISCV_X7, RISCV_X8, RISCV_X9, RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, + RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X18, RISCV_X19, RISCV_X20, + RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, + RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31}; + +static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + unsigned Reg = 0; + + if (RegNo > sizeof(GPRDecoderTable)) + return MCDisassembler_Fail; + + // We must define our own mapping from RegNo to register identifier. + // Accessing index RegNo in the register class will work in the case that + // registers were added in ascending order, but not in general. + Reg = GPRDecoderTable[RegNo]; + // Inst.addOperand(MCOperand::createReg(Reg)); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static const unsigned FPR32DecoderTable[] = { + RISCV_F0_F, RISCV_F1_F, RISCV_F2_F, RISCV_F3_F, RISCV_F4_F, + RISCV_F5_F, RISCV_F6_F, RISCV_F7_F, RISCV_F8_F, RISCV_F9_F, + RISCV_F10_F, RISCV_F11_F, RISCV_F12_F, RISCV_F13_F, RISCV_F14_F, + RISCV_F15_F, RISCV_F16_F, RISCV_F17_F, RISCV_F18_F, RISCV_F19_F, + RISCV_F20_F, RISCV_F21_F, RISCV_F22_F, RISCV_F23_F, RISCV_F24_F, + RISCV_F25_F, RISCV_F26_F, RISCV_F27_F, RISCV_F28_F, RISCV_F29_F, + RISCV_F30_F, RISCV_F31_F}; + +static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + unsigned Reg = 0; + + if (RegNo > sizeof(FPR32DecoderTable)) + return MCDisassembler_Fail; + + // We must define our own mapping from RegNo to register identifier. + // Accessing index RegNo in the register class will work in the case that + // registers were added in ascending order, but not in general. + Reg = FPR32DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFPR32CRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + unsigned Reg = 0; + + if (RegNo > 8) + return MCDisassembler_Fail; + Reg = FPR32DecoderTable[RegNo + 8]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static const unsigned FPR64DecoderTable[] = { + RISCV_F0_D, RISCV_F1_D, RISCV_F2_D, RISCV_F3_D, RISCV_F4_D, + RISCV_F5_D, RISCV_F6_D, RISCV_F7_D, RISCV_F8_D, RISCV_F9_D, + RISCV_F10_D, RISCV_F11_D, RISCV_F12_D, RISCV_F13_D, RISCV_F14_D, + RISCV_F15_D, RISCV_F16_D, RISCV_F17_D, RISCV_F18_D, RISCV_F19_D, + RISCV_F20_D, RISCV_F21_D, RISCV_F22_D, RISCV_F23_D, RISCV_F24_D, + RISCV_F25_D, RISCV_F26_D, RISCV_F27_D, RISCV_F28_D, RISCV_F29_D, + RISCV_F30_D, RISCV_F31_D}; + +static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + unsigned Reg = 0; + + if (RegNo > sizeof(FPR64DecoderTable)) + return MCDisassembler_Fail; + + // We must define our own mapping from RegNo to register identifier. + // Accessing index RegNo in the register class will work in the case that + // registers were added in ascending order, but not in general. + Reg = FPR64DecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFPR64CRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + unsigned Reg = 0; + + if (RegNo > 8) + return MCDisassembler_Fail; + Reg = FPR64DecoderTable[RegNo + 8]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo == 0) + return MCDisassembler_Fail; + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo == 2) + return MCDisassembler_Fail; + return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + unsigned Reg = 0; + + if (RegNo > 8) + return MCDisassembler_Fail; + + Reg = GPRDecoderTable[RegNo + 8]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +// Add implied SP operand for instructions *SP compressed instructions. The SP +// operand isn't explicitly encoded in the instruction. +static void addImplySP(MCInst *Inst, int64_t Address, const void *Decoder) { + if (MCInst_getOpcode(Inst) == RISCV_C_LWSP || + MCInst_getOpcode(Inst) == RISCV_C_SWSP || + MCInst_getOpcode(Inst) == RISCV_C_LDSP || + MCInst_getOpcode(Inst) == RISCV_C_SDSP || + MCInst_getOpcode(Inst) == RISCV_C_FLWSP || + MCInst_getOpcode(Inst) == RISCV_C_FSWSP || + MCInst_getOpcode(Inst) == RISCV_C_FLDSP || + MCInst_getOpcode(Inst) == RISCV_C_FSDSP || + MCInst_getOpcode(Inst) == RISCV_C_ADDI4SPN) { + DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + } + + if (MCInst_getOpcode(Inst) == RISCV_C_ADDI16SP) { + DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + } +} + +static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder, + unsigned N) { + // CS_ASSERT(isUInt(Imm) && "Invalid immediate"); + addImplySP(Inst, Address, Decoder); + // Inst.addOperand(MCOperand::createImm(Imm)); + MCOperand_CreateImm0(Inst, Imm); + return MCDisassembler_Success; +} + +static DecodeStatus decodeUImmNonZeroOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder, unsigned N) { + if (Imm == 0) + return MCDisassembler_Fail; + return decodeUImmOperand(Inst, Imm, Address, Decoder, N); +} + +static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder, + unsigned N) { + // CS_ASSERT(isUInt(Imm) && "Invalid immediate"); + addImplySP(Inst, Address, Decoder); + // Sign-extend the number in the bottom N bits of Imm + // Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); + MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSImmNonZeroOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder, unsigned N) { + if (Imm == 0) + return MCDisassembler_Fail; + return decodeSImmOperand(Inst, Imm, Address, Decoder, N); +} + +static DecodeStatus decodeSImmOperandAndLsl1(MCInst *Inst, uint64_t Imm, + int64_t Address, + const void *Decoder, unsigned N) { + // CS_ASSERT(isUInt(Imm) && "Invalid immediate"); + // Sign-extend the number in the bottom N bits of Imm after accounting for + // the fact that the N bit immediate is stored in N-1 bits (the LSB is + // always zero) + // Inst.addOperand(MCOperand::createImm(SignExtend64(Imm << 1))); + MCOperand_CreateImm0(Inst, SignExtend64(Imm << 1, N)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + // CS_ASSERT(isUInt<6>(Imm) && "Invalid immediate"); + if (Imm > 31) { + Imm = (SignExtend64(Imm, 6) & 0xfffff); + } + // Inst.addOperand(MCOperand::createImm(Imm)); + MCOperand_CreateImm0(Inst, Imm); + return MCDisassembler_Success; +} + +static DecodeStatus decodeFRMArg(MCInst *Inst, uint64_t Imm, int64_t Address, + const void *Decoder) { + // CS_ASSERT(isUInt<3>(Imm) && "Invalid immediate"); + if (!RISCVFPRndMode_isValidRoundingMode(Imm)) + return MCDisassembler_Fail; + + // Inst.addOperand(MCOperand::createImm(Imm)); + MCOperand_CreateImm0(Inst, Imm); + return MCDisassembler_Success; +} + +static DecodeStatus decodeRVCInstrSImm(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + uint64_t SImm6 = + fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + DecodeStatus Result = decodeSImmOperand(Inst, SImm6, Address, Decoder, 6); + (void)Result; + assert(Result == MCDisassembler_Success && "Invalid immediate"); + return MCDisassembler_Success; +} + +static DecodeStatus decodeRVCInstrRdSImm(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + uint64_t SImm6 = + fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + DecodeStatus Result = decodeSImmOperand(Inst, SImm6, Address, Decoder, 6); + (void)Result; + assert(Result == MCDisassembler_Success && "Invalid immediate"); + return MCDisassembler_Success; +} + +static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0)); + uint64_t UImm6 = + fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + DecodeStatus Result = decodeUImmOperand(Inst, UImm6, Address, Decoder, 6); + (void)Result; + assert(Result == MCDisassembler_Success && "Invalid immediate"); + return MCDisassembler_Success; +} + +static DecodeStatus decodeRVCInstrRdRs2(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Rd = fieldFromInstruction(Insn, 7, 5); + unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); + DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); + DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); + return MCDisassembler_Success; +} + +static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Rd = fieldFromInstruction(Insn, 7, 5); + unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); + DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); + MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0)); + DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeVRRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= 32) + return MCDisassembler_Fail; + + unsigned Reg = RISCV_V0 + RegNo; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +// fixme super reg + +static DecodeStatus DecodeVRM2RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + // if (RegNo >= 32) + // return MCDisassembler_Fail; + // + // if (RegNo % 2) + // return MCDisassembler_Fail; + // + // const RISCVDisassembler *Dis = + // static_cast(Decoder, const RISCVDisassembler *); + // const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo(); + // MCRegister Reg = + // RI->getMatchingSuperReg(RISCV_V0 + RegNo, RISCV_sub_vrm1_0, + // &RISCVMCRegisterClasses[RISCV_VRM2RegClassID]); + // + // MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeVRM4RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + // if (RegNo >= 32) + // return MCDisassembler_Fail; + // + // if (RegNo % 4) + // return MCDisassembler_Fail; + // + // const RISCVDisassembler *Dis = + // static_cast(Decoder, const RISCVDisassembler *); + // const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo(); + // MCRegister Reg = + // RI->getMatchingSuperReg(RISCV_V0 + RegNo, RISCV_sub_vrm1_0, + // &RISCVMCRegisterClasses[RISCV_VRM4RegClassID]); + // + // MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeVRM8RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= 32) + return MCDisassembler_Fail; + + if (RegNo % 8) + return MCDisassembler_Fail; + // + // const RISCVDisassembler *Dis = + // static_cast(Decoder, const RISCVDisassembler *); + // const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo(); + // MCRegister Reg = + // RI->getMatchingSuperReg(RISCV_V0 + RegNo, RISCV_sub_vrm1_0, + // &RISCVMCRegisterClasses[RISCV_VRM8RegClassID]); + // + // MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus decodeVMaskReg(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *Decoder) { + switch (RegNo) { + default: + return MCDisassembler_Fail; + case 0: + MCOperand_CreateReg0(Inst, RISCV_V0); + break; + case 1: + break; + } + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= 32) + return MCDisassembler_Fail; + + unsigned Reg = RISCV_F0_H + RegNo; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +#endif // CAPSTONE_CAPSTONERISCVMODULE_H diff --git a/arch/RISCV/RISCVBaseInfo.h b/arch/RISCV/RISCVBaseInfo.h index e6ae1fcb57..5f33dac69f 100644 --- a/arch/RISCV/RISCVBaseInfo.h +++ b/arch/RISCV/RISCVBaseInfo.h @@ -20,87 +20,114 @@ // RISCVII - This namespace holds all of the target specific flags that // instruction info tracks. All definitions must match RISCVInstrFormats.td. enum { - IRISCVII_InstFormatPseudo = 0, - IRISCVII_InstFormatR = 1, - IRISCVII_InstFormatR4 = 2, - IRISCVII_InstFormatI = 3, - IRISCVII_InstFormatS = 4, - IRISCVII_InstFormatB = 5, - IRISCVII_InstFormatU = 6, - IRISCVII_InstFormatJ = 7, - IRISCVII_InstFormatCR = 8, - IRISCVII_InstFormatCI = 9, - IRISCVII_InstFormatCSS = 10, - IRISCVII_InstFormatCIW = 11, - IRISCVII_InstFormatCL = 12, - IRISCVII_InstFormatCS = 13, - IRISCVII_InstFormatCA = 14, - IRISCVII_InstFormatCB = 15, - IRISCVII_InstFormatCJ = 16, - IRISCVII_InstFormatOther = 17, + IRISCVII_InstFormatPseudo = 0, + IRISCVII_InstFormatR = 1, + IRISCVII_InstFormatR4 = 2, + IRISCVII_InstFormatI = 3, + IRISCVII_InstFormatS = 4, + IRISCVII_InstFormatB = 5, + IRISCVII_InstFormatU = 6, + IRISCVII_InstFormatJ = 7, + IRISCVII_InstFormatCR = 8, + IRISCVII_InstFormatCI = 9, + IRISCVII_InstFormatCSS = 10, + IRISCVII_InstFormatCIW = 11, + IRISCVII_InstFormatCL = 12, + IRISCVII_InstFormatCS = 13, + IRISCVII_InstFormatCA = 14, + IRISCVII_InstFormatCB = 15, + IRISCVII_InstFormatCJ = 16, + IRISCVII_InstFormatOther = 17, - IRISCVII_InstFormatMask = 31 + IRISCVII_InstFormatMask = 31 }; enum { - RISCVII_MO_None, - RISCVII_MO_LO, - RISCVII_MO_HI, - RISCVII_MO_PCREL_HI, + RISCVII_MO_None, + RISCVII_MO_LO, + RISCVII_MO_HI, + RISCVII_MO_PCREL_HI, }; // Describes the predecessor/successor bits used in the FENCE instruction. enum FenceField { - RISCVFenceField_I = 8, - RISCVFenceField_O = 4, - RISCVFenceField_R = 2, - RISCVFenceField_W = 1 + RISCVFenceField_I = 8, + RISCVFenceField_O = 4, + RISCVFenceField_R = 2, + RISCVFenceField_W = 1 }; // Describes the supported floating point rounding mode encodings. enum RoundingMode { - RISCVFPRndMode_RNE = 0, - RISCVFPRndMode_RTZ = 1, - RISCVFPRndMode_RDN = 2, - RISCVFPRndMode_RUP = 3, - RISCVFPRndMode_RMM = 4, - RISCVFPRndMode_DYN = 7, - RISCVFPRndMode_Invalid + RISCVFPRndMode_RNE = 0, + RISCVFPRndMode_RTZ = 1, + RISCVFPRndMode_RDN = 2, + RISCVFPRndMode_RUP = 3, + RISCVFPRndMode_RMM = 4, + RISCVFPRndMode_DYN = 7, + RISCVFPRndMode_Invalid }; -inline static const char *roundingModeToString(enum RoundingMode RndMode) -{ - switch (RndMode) { - default: - CS_ASSERT(0 && "Unknown floating point rounding mode"); - case RISCVFPRndMode_RNE: - return "rne"; - case RISCVFPRndMode_RTZ: - return "rtz"; - case RISCVFPRndMode_RDN: - return "rdn"; - case RISCVFPRndMode_RUP: - return "rup"; - case RISCVFPRndMode_RMM: - return "rmm"; - case RISCVFPRndMode_DYN: - return "dyn"; - } +enum { + RISCVVLMUL_LMUL_1 = 0, + RISCVVLMUL_LMUL_2, + RISCVVLMUL_LMUL_4, + RISCVVLMUL_LMUL_8, + RISCVVLMUL_LMUL_RESERVED, + RISCVVLMUL_LMUL_F8, + RISCVVLMUL_LMUL_F4, + RISCVVLMUL_LMUL_F2 +}; + +// Register alternate name indices + +enum { + RISCV_ABIRegAltName, // 0 + RISCV_NoRegAltName, // 1 + RISCV_NUM_TARGET_REG_ALT_NAMES = 2 +}; + +inline static const char *roundingModeToString(enum RoundingMode RndMode) { + switch (RndMode) { + default: + CS_ASSERT(0 && "Unknown floating point rounding mode"); + case RISCVFPRndMode_RNE: + return "rne"; + case RISCVFPRndMode_RTZ: + return "rtz"; + case RISCVFPRndMode_RDN: + return "rdn"; + case RISCVFPRndMode_RUP: + return "rup"; + case RISCVFPRndMode_RMM: + return "rmm"; + case RISCVFPRndMode_DYN: + return "dyn"; + } +} + +inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode) { + switch (Mode) { + default: + return false; + case RISCVFPRndMode_RNE: + case RISCVFPRndMode_RTZ: + case RISCVFPRndMode_RDN: + case RISCVFPRndMode_RUP: + case RISCVFPRndMode_RMM: + case RISCVFPRndMode_DYN: + return true; + } +} + +inline static unsigned getVLMUL(unsigned VType) { + unsigned VLMUL = VType & 0x7; + return VLMUL; } -inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode) -{ - switch (Mode) { - default: - return false; - case RISCVFPRndMode_RNE: - case RISCVFPRndMode_RTZ: - case RISCVFPRndMode_RDN: - case RISCVFPRndMode_RUP: - case RISCVFPRndMode_RMM: - case RISCVFPRndMode_DYN: - return true; - } +inline static unsigned getVSEW(unsigned VType) { + unsigned VSEW = (VType >> 3) & 0x7; + return VSEW; } #endif diff --git a/arch/RISCV/RISCVDisassembler.c b/arch/RISCV/RISCVDisassembler.c index 893bf3735d..e3a82ee2e3 100644 --- a/arch/RISCV/RISCVDisassembler.c +++ b/arch/RISCV/RISCVDisassembler.c @@ -8,426 +8,187 @@ //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ -/* RISC-V Backend By Rodrigo Cortes Porto & +/* RISC-V Backend By Rodrigo Cortes Porto & Shawn Chang , HardenedLinux@2018 */ - + #ifdef CAPSTONE_HAS_RISCV -#include // DEBUG +#include // DEBUG #include #include #include "../../cs_priv.h" #include "../../utils.h" +#include "../../MCDisassembler.h" +#include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" -#include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" -#include "../../MCDisassembler.h" #include "../../MathExtras.h" #include "RISCVBaseInfo.h" #include "RISCVDisassembler.h" - -/* Need the feature infos define in +/* Need the feature infos define in RISCVGenSubtargetInfo.inc. */ #define GET_SUBTARGETINFO_ENUM #include "RISCVGenSubtargetInfo.inc" /* When we specify the RISCV64 mode, It means It is RV64IMAFD. Similar, RISCV32 means RV32IMAFD. -*/ -static uint64_t getFeatureBits(int mode) -{ - uint64_t ret = RISCV_FeatureStdExtM | RISCV_FeatureStdExtA | - RISCV_FeatureStdExtF | RISCV_FeatureStdExtD ; - - if (mode & CS_MODE_RISCV64) - ret |= RISCV_Feature64Bit; - if (mode & CS_MODE_RISCVC) - ret |= RISCV_FeatureStdExtC; - - return ret; -} - -#define GET_REGINFO_ENUM -#define GET_REGINFO_MC_DESC -#include "RISCVGenRegisterInfo.inc" -#define GET_INSTRINFO_ENUM -#include "RISCVGenInstrInfo.inc" - -static const unsigned GPRDecoderTable[] = { - RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, - RISCV_X4, RISCV_X5, RISCV_X6, RISCV_X7, - RISCV_X8, RISCV_X9, RISCV_X10, RISCV_X11, - RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, - RISCV_X16, RISCV_X17, RISCV_X18, RISCV_X19, - RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, - RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, - RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31 -}; - -static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo > sizeof(GPRDecoderTable)) - return MCDisassembler_Fail; - - // We must define our own mapping from RegNo to register identifier. - // Accessing index RegNo in the register class will work in the case that - // registers were added in ascending order, but not in general. - Reg = GPRDecoderTable[RegNo]; - //Inst.addOperand(MCOperand::createReg(Reg)); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static const unsigned FPR32DecoderTable[] = { - RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32, - RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32, - RISCV_F8_32, RISCV_F9_32, RISCV_F10_32, RISCV_F11_32, - RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, - RISCV_F16_32, RISCV_F17_32, RISCV_F18_32, RISCV_F19_32, - RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32, - RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32, - RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32 -}; - -static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo > sizeof(FPR32DecoderTable)) - return MCDisassembler_Fail; - - // We must define our own mapping from RegNo to register identifier. - // Accessing index RegNo in the register class will work in the case that - // registers were added in ascending order, but not in general. - Reg = FPR32DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFPR32CRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo > 8) - return MCDisassembler_Fail; - Reg = FPR32DecoderTable[RegNo + 8]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static const unsigned FPR64DecoderTable[] = { - RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64, - RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64, - RISCV_F8_64, RISCV_F9_64, RISCV_F10_64, RISCV_F11_64, - RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, - RISCV_F16_64, RISCV_F17_64, RISCV_F18_64, RISCV_F19_64, - RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64, - RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64, - RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64 -}; - -static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo > sizeof(FPR64DecoderTable)) - return MCDisassembler_Fail; - - // We must define our own mapping from RegNo to register identifier. - // Accessing index RegNo in the register class will work in the case that - // registers were added in ascending order, but not in general. - Reg = FPR64DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFPR64CRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo > 8) - return MCDisassembler_Fail; - Reg = FPR64DecoderTable[RegNo + 8]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - if (RegNo == 0) - return MCDisassembler_Fail; - return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - if (RegNo == 2) - return MCDisassembler_Fail; - return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo > 8) - return MCDisassembler_Fail; - - Reg = GPRDecoderTable[RegNo + 8]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -// Add implied SP operand for instructions *SP compressed instructions. The SP -// operand isn't explicitly encoded in the instruction. -static void addImplySP(MCInst *Inst, int64_t Address, const void *Decoder) -{ - if (MCInst_getOpcode(Inst) == RISCV_C_LWSP || - MCInst_getOpcode(Inst) == RISCV_C_SWSP || - MCInst_getOpcode(Inst) == RISCV_C_LDSP || - MCInst_getOpcode(Inst) == RISCV_C_SDSP || - MCInst_getOpcode(Inst) == RISCV_C_FLWSP || - MCInst_getOpcode(Inst) == RISCV_C_FSWSP || - MCInst_getOpcode(Inst) == RISCV_C_FLDSP || - MCInst_getOpcode(Inst) == RISCV_C_FSDSP || - MCInst_getOpcode(Inst) == RISCV_C_ADDI4SPN) { - DecodeGPRRegisterClass(Inst, 2, Address, Decoder); - } - - if (MCInst_getOpcode(Inst) == RISCV_C_ADDI16SP) { - DecodeGPRRegisterClass(Inst, 2, Address, Decoder); - DecodeGPRRegisterClass(Inst, 2, Address, Decoder); - } -} - -static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder, - unsigned N) -{ - //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); - addImplySP(Inst, Address, Decoder); - //Inst.addOperand(MCOperand::createImm(Imm)); - MCOperand_CreateImm0(Inst, Imm); - return MCDisassembler_Success; -} - -static DecodeStatus decodeUImmNonZeroOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder, - unsigned N) -{ - if (Imm == 0) - return MCDisassembler_Fail; - return decodeUImmOperand(Inst, Imm, Address, Decoder, N); -} - -static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder, - unsigned N) -{ - //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); - addImplySP(Inst, Address, Decoder); - // Sign-extend the number in the bottom N bits of Imm - //Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); - MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); - return MCDisassembler_Success; -} - -static DecodeStatus decodeSImmNonZeroOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder, - unsigned N) -{ - if (Imm == 0) - return MCDisassembler_Fail; - return decodeSImmOperand(Inst, Imm, Address, Decoder, N); -} - -static DecodeStatus decodeSImmOperandAndLsl1(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder, - unsigned N) -{ - //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); - // Sign-extend the number in the bottom N bits of Imm after accounting for - // the fact that the N bit immediate is stored in N-1 bits (the LSB is - // always zero) - //Inst.addOperand(MCOperand::createImm(SignExtend64(Imm << 1))); - MCOperand_CreateImm0(Inst, SignExtend64(Imm << 1, N)); - return MCDisassembler_Success; -} - -static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder) -{ - //CS_ASSERT(isUInt<6>(Imm) && "Invalid immediate"); - if (Imm > 31) { - Imm = (SignExtend64(Imm, 6) & 0xfffff); - } - //Inst.addOperand(MCOperand::createImm(Imm)); - MCOperand_CreateImm0(Inst, Imm); - return MCDisassembler_Success; -} - -static DecodeStatus decodeFRMArg(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder) -{ - //CS_ASSERT(isUInt<3>(Imm) && "Invalid immediate"); - if (!RISCVFPRndMode_isValidRoundingMode(Imm)) - return MCDisassembler_Fail; - - //Inst.addOperand(MCOperand::createImm(Imm)); - MCOperand_CreateImm0(Inst, Imm); - return MCDisassembler_Success; -} - - -#include "RISCVGenDisassemblerTables.inc" - -static void init_MI_insn_detail(MCInst *MI) -{ - if (MI->flat_insn->detail) { - memset(MI->flat_insn->detail, 0, sizeof(cs_detail)); - } - - return; +//*/ +static uint64_t getFeatureBits(int mode) { + uint64_t ret = RISCV_FeatureStdExtM | RISCV_FeatureStdExtA | + RISCV_FeatureStdExtF | RISCV_FeatureStdExtD; + + if (mode & CS_MODE_RISCV64) + ret |= RISCV_Feature64Bit; + if (mode & CS_MODE_RISCVC) + ret |= RISCV_FeatureStdExtC; + + return ret; +} + +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require); + +#include "CapstoneRISCVModule.h" + +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require) { + switch (Feature) { + case RISCV_FeatureStdExtM: + case RISCV_FeatureStdExtA: + case RISCV_FeatureStdExtF: + case RISCV_FeatureStdExtD: + return Require; + case RISCV_Feature64Bit: // In no case should we simplify this branch, since + // 'bool' here is a dummy macro + if (Bits & CS_MODE_RISCV64) + return Require; + else + return !Require; + case RISCV_FeatureStdExtC: + if (Bits & CS_MODE_RISCVC) + return Require; + else + return !Require; + } + return Require; // return true for all other conds +} + +static void init_MI_insn_detail(MCInst *MI) { + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, sizeof(cs_detail)); + } + + return; } // mark the load/store instructions through the opcode. -static void markLSInsn(MCInst *MI, uint32_t in) -{ - /* - I ld 0000011 = 0x03 - st 0100011 = 0x23 - F/D ld 0000111 = 0x07 - st 0100111 = 0x27 - */ +static void markLSInsn(MCInst *MI, uint32_t in) { + /* + I ld 0000011 = 0x03 + st 0100011 = 0x23 + F/D ld 0000111 = 0x07 + st 0100111 = 0x27 + */ #define MASK_LS_INSN 0x0000007f - uint32_t opcode = in & MASK_LS_INSN; - if (0 == (opcode ^ 0x03) || 0 == (opcode ^ 0x07) || - 0 == (opcode ^ 0x23) || 0 == (opcode ^ 0x27)) - MI->flat_insn->detail->riscv.need_effective_addr = true; + uint32_t opcode = in & MASK_LS_INSN; + if (0 == (opcode ^ 0x03) || 0 == (opcode ^ 0x07) || 0 == (opcode ^ 0x23) || + 0 == (opcode ^ 0x27)) + MI->flat_insn->detail->riscv.need_effective_addr = true; #undef MASK_LS_INSN - return; -} - -static DecodeStatus RISCVDisassembler_getInstruction(int mode, MCInst *MI, - const uint8_t *code, size_t code_len, - uint16_t *Size, uint64_t Address, - MCRegisterInfo *MRI) -{ - // TODO: This will need modification when supporting instruction set - // extensions with instructions > 32-bits (up to 176 bits wide). - uint32_t Inst = 0; - DecodeStatus Result; - - // It's a 32 bit instruction if bit 0 and 1 are 1. - if ((code[0] & 0x3) == 0x3) { - if (code_len < 4) { - *Size = 0; - return MCDisassembler_Fail; - } - - *Size = 4; - // Get the four bytes of the instruction. - //Encoded as little endian 32 bits. - Inst = code[0] | (code[1] << 8) | (code[2] << 16) | ((uint32_t)code[3] << 24); - init_MI_insn_detail(MI); - // Now we need mark what instruction need fix effective address output. - if (MI->csh->detail) - markLSInsn(MI, Inst); - Result = decodeInstruction(DecoderTable32, MI, Inst, Address, MRI, mode); - } else { - if (code_len < 2) { - *Size = 0; - return MCDisassembler_Fail; - } - - // If not b4bit. - if (! (getFeatureBits(mode) & ((uint64_t)RISCV_Feature64Bit))) { - // Trying RISCV32Only_16 table (16-bit Instruction) - Inst = code[0] | (code[1] << 8); - init_MI_insn_detail(MI); - Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Inst, Address, - MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 2; - return Result; - } - } - - // Trying RISCV_C table (16-bit Instruction) - Inst = code[0] | (code[1] << 8); - init_MI_insn_detail(MI); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTable16, MI, Inst, Address, MRI, mode); - *Size = 2; - } - - return Result; + return; +} + +static DecodeStatus +RISCVDisassembler_getInstruction(int mode, MCInst *MI, const uint8_t *code, + size_t code_len, uint16_t *Size, + uint64_t Address, MCRegisterInfo *MRI) { + MI->MRI = MRI; + // TODO: This will need modification when supporting instruction set + // extensions with instructions > 32-bits (up to 176 bits wide). + uint32_t Inst = 0; + DecodeStatus Result; + + // It's a 32 bit instruction if bit 0 and 1 are 1. + if ((code[0] & 0x3) == 0x3) { + if (code_len < 4) { + *Size = 0; + return MCDisassembler_Fail; + } + + *Size = 4; + // Get the four bytes of the instruction. + // Encoded as little endian 32 bits. + Inst = + code[0] | (code[1] << 8) | (code[2] << 16) | ((uint32_t)code[3] << 24); + init_MI_insn_detail(MI); + // Now we need mark what instruction need fix effective address output. + if (MI->csh->detail) + markLSInsn(MI, Inst); + Result = decodeInstruction(DecoderTable32, MI, Inst, Address, MRI, mode); + } else { + if (code_len < 2) { + *Size = 0; + return MCDisassembler_Fail; + } + + // If not b4bit. + if (!(getFeatureBits(mode) & ((uint64_t)RISCV_Feature64Bit))) { + // Trying RISCV32Only_16 table (16-bit Instruction) + Inst = code[0] | (code[1] << 8); + init_MI_insn_detail(MI); + Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Inst, Address, + MRI, mode); + if (Result != MCDisassembler_Fail) { + *Size = 2; + return Result; + } + } + + // Trying RISCV_C table (16-bit Instruction) + Inst = code[0] | (code[1] << 8); + init_MI_insn_detail(MI); + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTable16, MI, Inst, Address, MRI, mode); + *Size = 2; + } + + return Result; } bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, - void *info) -{ - cs_struct *handle = (cs_struct *)(uintptr_t)ud; - - return MCDisassembler_Success == - RISCVDisassembler_getInstruction(handle->mode, instr, - code, code_len, - size, address, - (MCRegisterInfo *)info); - -} - -void RISCV_init(MCRegisterInfo * MRI) -{ - /* - InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC, - RISCVMCRegisterClasses, 11, - RISCVRegUnitRoots, - 64, - RISCVRegDiffLists, - RISCVLaneMaskLists, - RISCVRegStrings, - RISCVRegClassStrings, - RISCVSubRegIdxLists, - 2, - RISCVSubRegIdxRanges, - RISCVRegEncodingTable); - */ - - MCRegisterInfo_InitMCRegisterInfo(MRI, RISCVRegDesc, 97, 0, 0, - RISCVMCRegisterClasses, 11, - 0, - 0, - RISCVRegDiffLists, - 0, - RISCVSubRegIdxLists, - 2, - 0); + MCInst *instr, uint16_t *size, uint64_t address, + void *info) { + cs_struct *handle = (cs_struct *)(uintptr_t)ud; + + return MCDisassembler_Success == RISCVDisassembler_getInstruction( + handle->mode, instr, code, code_len, + size, address, (MCRegisterInfo *)info); +} + +void RISCV_init(MCRegisterInfo *MRI) { + /* + InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC, + RISCVMCRegisterClasses, 11, + RISCVRegUnitRoots, + 64, + RISCVRegDiffLists, + RISCVLaneMaskLists, + RISCVRegStrings, + RISCVRegClassStrings, + RISCVSubRegIdxLists, + 2, + RISCVSubRegIdxRanges, + RISCVRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo( + MRI, RISCVRegDesc, ARR_SIZE(RISCVRegDesc), 0, 0, RISCVMCRegisterClasses, + ARR_SIZE(RISCVMCRegisterClasses), 0, 0, RISCVRegDiffLists, 0, + RISCVSubRegIdxLists, ARR_SIZE(RISCVSubRegIdxLists), 0); } #endif diff --git a/arch/RISCV/RISCVDisassembler.h b/arch/RISCV/RISCVDisassembler.h index 1cb70ea7c5..b7c66114f8 100644 --- a/arch/RISCV/RISCVDisassembler.h +++ b/arch/RISCV/RISCVDisassembler.h @@ -1,18 +1,18 @@ /* Capstone Disassembly Engine */ -/* RISC-V Backend By Rodrigo Cortes Porto & +/* RISC-V Backend By Rodrigo Cortes Porto & Shawn Chang , HardenedLinux@2018 */ - + #ifndef CS_RISCVDISASSEMBLER_H #define CS_RISCVDISASSEMBLER_H -#include "../../include/capstone/capstone.h" -#include "../../MCRegisterInfo.h" #include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../include/capstone/capstone.h" void RISCV_init(MCRegisterInfo *MRI); bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, - void *info); + MCInst *instr, uint16_t *size, uint64_t address, + void *info); #endif diff --git a/arch/RISCV/RISCVGenAsmWriter.inc b/arch/RISCV/RISCVGenAsmWriter.inc index c89d7d5cf3..1bb48a2d48 100644 --- a/arch/RISCV/RISCVGenAsmWriter.inc +++ b/arch/RISCV/RISCVGenAsmWriter.inc @@ -9,1181 +9,3427 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ -#include // debug -#include #include - +#include +#include // debug /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) -{ +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'l', 'l', 'a', 9, 0, - /* 5 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0, - /* 17 */ 's', 'r', 'a', 9, 0, - /* 22 */ 'l', 'b', 9, 0, - /* 26 */ 's', 'b', 9, 0, - /* 30 */ 'c', '.', 's', 'u', 'b', 9, 0, - /* 37 */ 'a', 'u', 'i', 'p', 'c', 9, 0, - /* 44 */ 'c', 's', 'r', 'r', 'c', 9, 0, - /* 51 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, - /* 59 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 68 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 78 */ 's', 'c', '.', 'd', 9, 0, - /* 84 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 92 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 101 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 111 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 121 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0, - /* 131 */ 'f', 'l', 'e', '.', 'd', 9, 0, - /* 138 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0, - /* 147 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, - /* 157 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, - /* 165 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, - /* 173 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0, - /* 183 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0, - /* 193 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0, - /* 204 */ 'f', 'e', 'q', '.', 'd', 9, 0, - /* 211 */ 'l', 'r', '.', 'd', 9, 0, - /* 217 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', 9, 0, - /* 226 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', 9, 0, - /* 236 */ 'f', 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, - /* 246 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, - /* 256 */ 'f', 'l', 't', '.', 'd', 9, 0, - /* 263 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, - /* 272 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 'd', 9, 0, - /* 283 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', 9, 0, - /* 294 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 'd', 9, 0, - /* 305 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', 9, 0, - /* 316 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, - /* 324 */ 'f', 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, - /* 334 */ 'f', 'm', 'v', '.', 'x', '.', 'd', 9, 0, - /* 343 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, - /* 351 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', 9, 0, - /* 361 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 'd', 9, 0, - /* 371 */ 'c', '.', 'a', 'd', 'd', 9, 0, - /* 378 */ 'c', '.', 'l', 'd', 9, 0, - /* 384 */ 'c', '.', 'f', 'l', 'd', 9, 0, - /* 391 */ 'c', '.', 'a', 'n', 'd', 9, 0, - /* 398 */ 'c', '.', 's', 'd', 9, 0, - /* 404 */ 'c', '.', 'f', 's', 'd', 9, 0, - /* 411 */ 'f', 'e', 'n', 'c', 'e', 9, 0, - /* 418 */ 'b', 'g', 'e', 9, 0, - /* 423 */ 'b', 'n', 'e', 9, 0, - /* 428 */ 'm', 'u', 'l', 'h', 9, 0, - /* 434 */ 's', 'h', 9, 0, - /* 438 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0, - /* 447 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0, - /* 455 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0, - /* 463 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0, - /* 471 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0, - /* 479 */ 'w', 'f', 'i', 9, 0, - /* 484 */ 'c', '.', 'l', 'i', 9, 0, - /* 490 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0, - /* 498 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0, - /* 506 */ 'x', 'o', 'r', 'i', 9, 0, - /* 512 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0, - /* 520 */ 's', 'l', 't', 'i', 9, 0, - /* 526 */ 'c', '.', 'l', 'u', 'i', 9, 0, - /* 533 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0, - /* 541 */ 'c', '.', 'j', 9, 0, - /* 546 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0, - /* 556 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, - /* 566 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, - /* 576 */ 'c', '.', 'j', 'a', 'l', 9, 0, - /* 583 */ 't', 'a', 'i', 'l', 9, 0, - /* 589 */ 'e', 'c', 'a', 'l', 'l', 9, 0, - /* 596 */ 's', 'l', 'l', 9, 0, - /* 601 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0, - /* 610 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0, - /* 623 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0, - /* 636 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0, - /* 649 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0, - /* 663 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0, - /* 672 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, - /* 684 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, - /* 697 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'r', 'l', 9, 0, - /* 711 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'r', 'l', 9, 0, - /* 725 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'r', 'l', 9, 0, - /* 738 */ 's', 'c', '.', 'w', '.', 'r', 'l', 9, 0, - /* 747 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'r', 'l', 9, 0, - /* 760 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'r', 'l', 9, 0, - /* 773 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'r', 'l', 9, 0, - /* 786 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'r', 'l', 9, 0, - /* 800 */ 'l', 'r', '.', 'w', '.', 'r', 'l', 9, 0, - /* 809 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, - /* 821 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, - /* 834 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'r', 'l', 9, 0, - /* 848 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'r', 'l', 9, 0, - /* 862 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'r', 'l', 9, 0, - /* 875 */ 's', 'c', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 886 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 901 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 916 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 931 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 947 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 958 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 972 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 987 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1003 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1019 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1034 */ 's', 'c', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1045 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1060 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1075 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1090 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1106 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1117 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1131 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1146 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1162 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1178 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1193 */ 's', 'r', 'l', 9, 0, - /* 1198 */ 'm', 'u', 'l', 9, 0, - /* 1203 */ 'r', 'e', 'm', 9, 0, - /* 1208 */ 'c', '.', 'a', 'd', 'd', 'i', '4', 's', 'p', 'n', 9, 0, - /* 1220 */ 'f', 'e', 'n', 'c', 'e', '.', 't', 's', 'o', 9, 0, - /* 1231 */ 'c', '.', 'u', 'n', 'i', 'm', 'p', 9, 0, - /* 1240 */ 'c', '.', 'n', 'o', 'p', 9, 0, - /* 1247 */ 'c', '.', 'a', 'd', 'd', 'i', '1', '6', 's', 'p', 9, 0, - /* 1259 */ 'c', '.', 'l', 'd', 's', 'p', 9, 0, - /* 1267 */ 'c', '.', 'f', 'l', 'd', 's', 'p', 9, 0, - /* 1276 */ 'c', '.', 's', 'd', 's', 'p', 9, 0, - /* 1284 */ 'c', '.', 'f', 's', 'd', 's', 'p', 9, 0, - /* 1293 */ 'c', '.', 'l', 'w', 's', 'p', 9, 0, - /* 1301 */ 'c', '.', 'f', 'l', 'w', 's', 'p', 9, 0, - /* 1310 */ 'c', '.', 's', 'w', 's', 'p', 9, 0, - /* 1318 */ 'c', '.', 'f', 's', 'w', 's', 'p', 9, 0, - /* 1327 */ 's', 'c', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1336 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1349 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1362 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1375 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1389 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1398 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1410 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1423 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1437 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1451 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1464 */ 's', 'c', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1473 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1486 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1499 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1512 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1526 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1535 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1547 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1560 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1574 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1588 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1601 */ 'b', 'e', 'q', 9, 0, - /* 1606 */ 'c', '.', 'j', 'r', 9, 0, - /* 1612 */ 'c', '.', 'j', 'a', 'l', 'r', 9, 0, - /* 1620 */ 'c', '.', 'o', 'r', 9, 0, - /* 1626 */ 'c', '.', 'x', 'o', 'r', 9, 0, - /* 1633 */ 'f', 's', 'u', 'b', '.', 's', 9, 0, - /* 1641 */ 'f', 'm', 's', 'u', 'b', '.', 's', 9, 0, - /* 1650 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, - /* 1660 */ 'f', 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, - /* 1670 */ 'f', 'a', 'd', 'd', '.', 's', 9, 0, - /* 1678 */ 'f', 'm', 'a', 'd', 'd', '.', 's', 9, 0, - /* 1687 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, - /* 1697 */ 'f', 'l', 'e', '.', 's', 9, 0, - /* 1704 */ 'f', 's', 'g', 'n', 'j', '.', 's', 9, 0, - /* 1713 */ 'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, - /* 1723 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0, - /* 1731 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0, - /* 1739 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0, - /* 1749 */ 'f', 'e', 'q', '.', 's', 9, 0, - /* 1756 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, - /* 1766 */ 'f', 'l', 't', '.', 's', 9, 0, - /* 1773 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0, - /* 1782 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0, - /* 1793 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0, - /* 1804 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0, - /* 1812 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, - /* 1822 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0, - /* 1830 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0, - /* 1840 */ 'c', 's', 'r', 'r', 's', 9, 0, - /* 1847 */ 'm', 'r', 'e', 't', 9, 0, - /* 1853 */ 's', 'r', 'e', 't', 9, 0, - /* 1859 */ 'u', 'r', 'e', 't', 9, 0, - /* 1865 */ 'b', 'l', 't', 9, 0, - /* 1870 */ 's', 'l', 't', 9, 0, - /* 1875 */ 'l', 'b', 'u', 9, 0, - /* 1880 */ 'b', 'g', 'e', 'u', 9, 0, - /* 1886 */ 'm', 'u', 'l', 'h', 'u', 9, 0, - /* 1893 */ 's', 'l', 't', 'i', 'u', 9, 0, - /* 1900 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0, - /* 1911 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0, - /* 1922 */ 'r', 'e', 'm', 'u', 9, 0, - /* 1928 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0, - /* 1936 */ 'b', 'l', 't', 'u', 9, 0, - /* 1942 */ 's', 'l', 't', 'u', 9, 0, - /* 1948 */ 'd', 'i', 'v', 'u', 9, 0, - /* 1954 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0, - /* 1965 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0, - /* 1976 */ 'l', 'w', 'u', 9, 0, - /* 1981 */ 'd', 'i', 'v', 9, 0, - /* 1986 */ 'c', '.', 'm', 'v', 9, 0, - /* 1992 */ 's', 'c', '.', 'w', 9, 0, - /* 1998 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, - /* 2008 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0, - /* 2018 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0, - /* 2028 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0, - /* 2038 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0, - /* 2049 */ 'l', 'r', '.', 'w', 9, 0, - /* 2055 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0, - /* 2064 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0, - /* 2074 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, - /* 2084 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0, - /* 2095 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0, - /* 2106 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0, - /* 2115 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0, - /* 2125 */ 's', 'r', 'a', 'w', 9, 0, - /* 2131 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0, - /* 2139 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0, - /* 2147 */ 's', 'r', 'a', 'i', 'w', 9, 0, - /* 2154 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0, - /* 2163 */ 's', 'l', 'l', 'i', 'w', 9, 0, - /* 2170 */ 's', 'r', 'l', 'i', 'w', 9, 0, - /* 2177 */ 'c', '.', 'l', 'w', 9, 0, - /* 2183 */ 'c', '.', 'f', 'l', 'w', 9, 0, - /* 2190 */ 's', 'l', 'l', 'w', 9, 0, - /* 2196 */ 's', 'r', 'l', 'w', 9, 0, - /* 2202 */ 'm', 'u', 'l', 'w', 9, 0, - /* 2208 */ 'r', 'e', 'm', 'w', 9, 0, - /* 2214 */ 'c', 's', 'r', 'r', 'w', 9, 0, - /* 2221 */ 'c', '.', 's', 'w', 9, 0, - /* 2227 */ 'c', '.', 'f', 's', 'w', 9, 0, - /* 2234 */ 'r', 'e', 'm', 'u', 'w', 9, 0, - /* 2241 */ 'd', 'i', 'v', 'u', 'w', 9, 0, - /* 2248 */ 'd', 'i', 'v', 'w', 9, 0, - /* 2254 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0, - /* 2263 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0, - /* 2272 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0, - /* 2280 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0, - /* 2288 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, - /* 2319 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 2343 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 2368 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, - /* 2391 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, - /* 2414 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, - /* 2436 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 2449 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 2456 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 2466 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, - /* 2476 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 2491 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, + /* 0 */ 'l', + 'l', + 'a', + 9, + 0, + /* 5 */ 's', + 'f', + 'e', + 'n', + 'c', + 'e', + '.', + 'v', + 'm', + 'a', + 9, + 0, + /* 17 */ 's', + 'r', + 'a', + 9, + 0, + /* 22 */ 'l', + 'b', + 9, + 0, + /* 26 */ 's', + 'b', + 9, + 0, + /* 30 */ 'c', + '.', + 's', + 'u', + 'b', + 9, + 0, + /* 37 */ 'a', + 'u', + 'i', + 'p', + 'c', + 9, + 0, + /* 44 */ 'c', + 's', + 'r', + 'r', + 'c', + 9, + 0, + /* 51 */ 'f', + 's', + 'u', + 'b', + '.', + 'd', + 9, + 0, + /* 59 */ 'f', + 'm', + 's', + 'u', + 'b', + '.', + 'd', + 9, + 0, + /* 68 */ 'f', + 'n', + 'm', + 's', + 'u', + 'b', + '.', + 'd', + 9, + 0, + /* 78 */ 's', + 'c', + '.', + 'd', + 9, + 0, + /* 84 */ 'f', + 'a', + 'd', + 'd', + '.', + 'd', + 9, + 0, + /* 92 */ 'f', + 'm', + 'a', + 'd', + 'd', + '.', + 'd', + 9, + 0, + /* 101 */ 'f', + 'n', + 'm', + 'a', + 'd', + 'd', + '.', + 'd', + 9, + 0, + /* 111 */ 'a', + 'm', + 'o', + 'a', + 'd', + 'd', + '.', + 'd', + 9, + 0, + /* 121 */ 'a', + 'm', + 'o', + 'a', + 'n', + 'd', + '.', + 'd', + 9, + 0, + /* 131 */ 'f', + 'l', + 'e', + '.', + 'd', + 9, + 0, + /* 138 */ 'f', + 's', + 'g', + 'n', + 'j', + '.', + 'd', + 9, + 0, + /* 147 */ 'f', + 'c', + 'v', + 't', + '.', + 'l', + '.', + 'd', + 9, + 0, + /* 157 */ 'f', + 'm', + 'u', + 'l', + '.', + 'd', + 9, + 0, + /* 165 */ 'f', + 'm', + 'i', + 'n', + '.', + 'd', + 9, + 0, + /* 173 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + '.', + 'd', + 9, + 0, + /* 183 */ 'f', + 's', + 'g', + 'n', + 'j', + 'n', + '.', + 'd', + 9, + 0, + /* 193 */ 'a', + 'm', + 'o', + 's', + 'w', + 'a', + 'p', + '.', + 'd', + 9, + 0, + /* 204 */ 'f', + 'e', + 'q', + '.', + 'd', + 9, + 0, + /* 211 */ 'l', + 'r', + '.', + 'd', + 9, + 0, + /* 217 */ 'a', + 'm', + 'o', + 'o', + 'r', + '.', + 'd', + 9, + 0, + /* 226 */ 'a', + 'm', + 'o', + 'x', + 'o', + 'r', + '.', + 'd', + 9, + 0, + /* 236 */ 'f', + 'c', + 'v', + 't', + '.', + 's', + '.', + 'd', + 9, + 0, + /* 246 */ 'f', + 'c', + 'l', + 'a', + 's', + 's', + '.', + 'd', + 9, + 0, + /* 256 */ 'f', + 'l', + 't', + '.', + 'd', + 9, + 0, + /* 263 */ 'f', + 's', + 'q', + 'r', + 't', + '.', + 'd', + 9, + 0, + /* 272 */ 'f', + 'c', + 'v', + 't', + '.', + 'l', + 'u', + '.', + 'd', + 9, + 0, + /* 283 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + 'u', + '.', + 'd', + 9, + 0, + /* 294 */ 'f', + 'c', + 'v', + 't', + '.', + 'w', + 'u', + '.', + 'd', + 9, + 0, + /* 305 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + 'u', + '.', + 'd', + 9, + 0, + /* 316 */ 'f', + 'd', + 'i', + 'v', + '.', + 'd', + 9, + 0, + /* 324 */ 'f', + 'c', + 'v', + 't', + '.', + 'w', + '.', + 'd', + 9, + 0, + /* 334 */ 'f', + 'm', + 'v', + '.', + 'x', + '.', + 'd', + 9, + 0, + /* 343 */ 'f', + 'm', + 'a', + 'x', + '.', + 'd', + 9, + 0, + /* 351 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + '.', + 'd', + 9, + 0, + /* 361 */ 'f', + 's', + 'g', + 'n', + 'j', + 'x', + '.', + 'd', + 9, + 0, + /* 371 */ 'c', + '.', + 'a', + 'd', + 'd', + 9, + 0, + /* 378 */ 'c', + '.', + 'l', + 'd', + 9, + 0, + /* 384 */ 'c', + '.', + 'f', + 'l', + 'd', + 9, + 0, + /* 391 */ 'c', + '.', + 'a', + 'n', + 'd', + 9, + 0, + /* 398 */ 'c', + '.', + 's', + 'd', + 9, + 0, + /* 404 */ 'c', + '.', + 'f', + 's', + 'd', + 9, + 0, + /* 411 */ 'f', + 'e', + 'n', + 'c', + 'e', + 9, + 0, + /* 418 */ 'b', + 'g', + 'e', + 9, + 0, + /* 423 */ 'b', + 'n', + 'e', + 9, + 0, + /* 428 */ 'm', + 'u', + 'l', + 'h', + 9, + 0, + /* 434 */ 's', + 'h', + 9, + 0, + /* 438 */ 'f', + 'e', + 'n', + 'c', + 'e', + '.', + 'i', + 9, + 0, + /* 447 */ 'c', + '.', + 's', + 'r', + 'a', + 'i', + 9, + 0, + /* 455 */ 'c', + 's', + 'r', + 'r', + 'c', + 'i', + 9, + 0, + /* 463 */ 'c', + '.', + 'a', + 'd', + 'd', + 'i', + 9, + 0, + /* 471 */ 'c', + '.', + 'a', + 'n', + 'd', + 'i', + 9, + 0, + /* 479 */ 'w', + 'f', + 'i', + 9, + 0, + /* 484 */ 'c', + '.', + 'l', + 'i', + 9, + 0, + /* 490 */ 'c', + '.', + 's', + 'l', + 'l', + 'i', + 9, + 0, + /* 498 */ 'c', + '.', + 's', + 'r', + 'l', + 'i', + 9, + 0, + /* 506 */ 'x', + 'o', + 'r', + 'i', + 9, + 0, + /* 512 */ 'c', + 's', + 'r', + 'r', + 's', + 'i', + 9, + 0, + /* 520 */ 's', + 'l', + 't', + 'i', + 9, + 0, + /* 526 */ 'c', + '.', + 'l', + 'u', + 'i', + 9, + 0, + /* 533 */ 'c', + 's', + 'r', + 'r', + 'w', + 'i', + 9, + 0, + /* 541 */ 'c', + '.', + 'j', + 9, + 0, + /* 546 */ 'c', + '.', + 'e', + 'b', + 'r', + 'e', + 'a', + 'k', + 9, + 0, + /* 556 */ 'f', + 'c', + 'v', + 't', + '.', + 'd', + '.', + 'l', + 9, + 0, + /* 566 */ 'f', + 'c', + 'v', + 't', + '.', + 's', + '.', + 'l', + 9, + 0, + /* 576 */ 'c', + '.', + 'j', + 'a', + 'l', + 9, + 0, + /* 583 */ 't', + 'a', + 'i', + 'l', + 9, + 0, + /* 589 */ 'e', + 'c', + 'a', + 'l', + 'l', + 9, + 0, + /* 596 */ 's', + 'l', + 'l', + 9, + 0, + /* 601 */ 's', + 'c', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 610 */ 'a', + 'm', + 'o', + 'a', + 'd', + 'd', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 623 */ 'a', + 'm', + 'o', + 'a', + 'n', + 'd', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 636 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 649 */ 'a', + 'm', + 'o', + 's', + 'w', + 'a', + 'p', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 663 */ 'l', + 'r', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 672 */ 'a', + 'm', + 'o', + 'o', + 'r', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 684 */ 'a', + 'm', + 'o', + 'x', + 'o', + 'r', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 697 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + 'u', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 711 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + 'u', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 725 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + '.', + 'd', + '.', + 'r', + 'l', + 9, + 0, + /* 738 */ 's', + 'c', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 747 */ 'a', + 'm', + 'o', + 'a', + 'd', + 'd', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 760 */ 'a', + 'm', + 'o', + 'a', + 'n', + 'd', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 773 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 786 */ 'a', + 'm', + 'o', + 's', + 'w', + 'a', + 'p', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 800 */ 'l', + 'r', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 809 */ 'a', + 'm', + 'o', + 'o', + 'r', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 821 */ 'a', + 'm', + 'o', + 'x', + 'o', + 'r', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 834 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + 'u', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 848 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + 'u', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 862 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + '.', + 'w', + '.', + 'r', + 'l', + 9, + 0, + /* 875 */ 's', + 'c', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 886 */ 'a', + 'm', + 'o', + 'a', + 'd', + 'd', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 901 */ 'a', + 'm', + 'o', + 'a', + 'n', + 'd', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 916 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 931 */ 'a', + 'm', + 'o', + 's', + 'w', + 'a', + 'p', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 947 */ 'l', + 'r', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 958 */ 'a', + 'm', + 'o', + 'o', + 'r', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 972 */ 'a', + 'm', + 'o', + 'x', + 'o', + 'r', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 987 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + 'u', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1003 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + 'u', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1019 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + '.', + 'd', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1034 */ 's', + 'c', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1045 */ 'a', + 'm', + 'o', + 'a', + 'd', + 'd', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1060 */ 'a', + 'm', + 'o', + 'a', + 'n', + 'd', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1075 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1090 */ 'a', + 'm', + 'o', + 's', + 'w', + 'a', + 'p', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1106 */ 'l', + 'r', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1117 */ 'a', + 'm', + 'o', + 'o', + 'r', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1131 */ 'a', + 'm', + 'o', + 'x', + 'o', + 'r', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1146 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + 'u', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1162 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + 'u', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1178 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + '.', + 'w', + '.', + 'a', + 'q', + 'r', + 'l', + 9, + 0, + /* 1193 */ 's', + 'r', + 'l', + 9, + 0, + /* 1198 */ 'm', + 'u', + 'l', + 9, + 0, + /* 1203 */ 'r', + 'e', + 'm', + 9, + 0, + /* 1208 */ 'c', + '.', + 'a', + 'd', + 'd', + 'i', + '4', + 's', + 'p', + 'n', + 9, + 0, + /* 1220 */ 'f', + 'e', + 'n', + 'c', + 'e', + '.', + 't', + 's', + 'o', + 9, + 0, + /* 1231 */ 'c', + '.', + 'u', + 'n', + 'i', + 'm', + 'p', + 9, + 0, + /* 1240 */ 'c', + '.', + 'n', + 'o', + 'p', + 9, + 0, + /* 1247 */ 'c', + '.', + 'a', + 'd', + 'd', + 'i', + '1', + '6', + 's', + 'p', + 9, + 0, + /* 1259 */ 'c', + '.', + 'l', + 'd', + 's', + 'p', + 9, + 0, + /* 1267 */ 'c', + '.', + 'f', + 'l', + 'd', + 's', + 'p', + 9, + 0, + /* 1276 */ 'c', + '.', + 's', + 'd', + 's', + 'p', + 9, + 0, + /* 1284 */ 'c', + '.', + 'f', + 's', + 'd', + 's', + 'p', + 9, + 0, + /* 1293 */ 'c', + '.', + 'l', + 'w', + 's', + 'p', + 9, + 0, + /* 1301 */ 'c', + '.', + 'f', + 'l', + 'w', + 's', + 'p', + 9, + 0, + /* 1310 */ 'c', + '.', + 's', + 'w', + 's', + 'p', + 9, + 0, + /* 1318 */ 'c', + '.', + 'f', + 's', + 'w', + 's', + 'p', + 9, + 0, + /* 1327 */ 's', + 'c', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1336 */ 'a', + 'm', + 'o', + 'a', + 'd', + 'd', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1349 */ 'a', + 'm', + 'o', + 'a', + 'n', + 'd', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1362 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1375 */ 'a', + 'm', + 'o', + 's', + 'w', + 'a', + 'p', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1389 */ 'l', + 'r', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1398 */ 'a', + 'm', + 'o', + 'o', + 'r', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1410 */ 'a', + 'm', + 'o', + 'x', + 'o', + 'r', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1423 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + 'u', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1437 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + 'u', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1451 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + '.', + 'd', + '.', + 'a', + 'q', + 9, + 0, + /* 1464 */ 's', + 'c', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1473 */ 'a', + 'm', + 'o', + 'a', + 'd', + 'd', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1486 */ 'a', + 'm', + 'o', + 'a', + 'n', + 'd', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1499 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1512 */ 'a', + 'm', + 'o', + 's', + 'w', + 'a', + 'p', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1526 */ 'l', + 'r', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1535 */ 'a', + 'm', + 'o', + 'o', + 'r', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1547 */ 'a', + 'm', + 'o', + 'x', + 'o', + 'r', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1560 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + 'u', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1574 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + 'u', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1588 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + '.', + 'w', + '.', + 'a', + 'q', + 9, + 0, + /* 1601 */ 'b', + 'e', + 'q', + 9, + 0, + /* 1606 */ 'c', + '.', + 'j', + 'r', + 9, + 0, + /* 1612 */ 'c', + '.', + 'j', + 'a', + 'l', + 'r', + 9, + 0, + /* 1620 */ 'c', + '.', + 'o', + 'r', + 9, + 0, + /* 1626 */ 'c', + '.', + 'x', + 'o', + 'r', + 9, + 0, + /* 1633 */ 'f', + 's', + 'u', + 'b', + '.', + 's', + 9, + 0, + /* 1641 */ 'f', + 'm', + 's', + 'u', + 'b', + '.', + 's', + 9, + 0, + /* 1650 */ 'f', + 'n', + 'm', + 's', + 'u', + 'b', + '.', + 's', + 9, + 0, + /* 1660 */ 'f', + 'c', + 'v', + 't', + '.', + 'd', + '.', + 's', + 9, + 0, + /* 1670 */ 'f', + 'a', + 'd', + 'd', + '.', + 's', + 9, + 0, + /* 1678 */ 'f', + 'm', + 'a', + 'd', + 'd', + '.', + 's', + 9, + 0, + /* 1687 */ 'f', + 'n', + 'm', + 'a', + 'd', + 'd', + '.', + 's', + 9, + 0, + /* 1697 */ 'f', + 'l', + 'e', + '.', + 's', + 9, + 0, + /* 1704 */ 'f', + 's', + 'g', + 'n', + 'j', + '.', + 's', + 9, + 0, + /* 1713 */ 'f', + 'c', + 'v', + 't', + '.', + 'l', + '.', + 's', + 9, + 0, + /* 1723 */ 'f', + 'm', + 'u', + 'l', + '.', + 's', + 9, + 0, + /* 1731 */ 'f', + 'm', + 'i', + 'n', + '.', + 's', + 9, + 0, + /* 1739 */ 'f', + 's', + 'g', + 'n', + 'j', + 'n', + '.', + 's', + 9, + 0, + /* 1749 */ 'f', + 'e', + 'q', + '.', + 's', + 9, + 0, + /* 1756 */ 'f', + 'c', + 'l', + 'a', + 's', + 's', + '.', + 's', + 9, + 0, + /* 1766 */ 'f', + 'l', + 't', + '.', + 's', + 9, + 0, + /* 1773 */ 'f', + 's', + 'q', + 'r', + 't', + '.', + 's', + 9, + 0, + /* 1782 */ 'f', + 'c', + 'v', + 't', + '.', + 'l', + 'u', + '.', + 's', + 9, + 0, + /* 1793 */ 'f', + 'c', + 'v', + 't', + '.', + 'w', + 'u', + '.', + 's', + 9, + 0, + /* 1804 */ 'f', + 'd', + 'i', + 'v', + '.', + 's', + 9, + 0, + /* 1812 */ 'f', + 'c', + 'v', + 't', + '.', + 'w', + '.', + 's', + 9, + 0, + /* 1822 */ 'f', + 'm', + 'a', + 'x', + '.', + 's', + 9, + 0, + /* 1830 */ 'f', + 's', + 'g', + 'n', + 'j', + 'x', + '.', + 's', + 9, + 0, + /* 1840 */ 'c', + 's', + 'r', + 'r', + 's', + 9, + 0, + /* 1847 */ 'm', + 'r', + 'e', + 't', + 9, + 0, + /* 1853 */ 's', + 'r', + 'e', + 't', + 9, + 0, + /* 1859 */ 'u', + 'r', + 'e', + 't', + 9, + 0, + /* 1865 */ 'b', + 'l', + 't', + 9, + 0, + /* 1870 */ 's', + 'l', + 't', + 9, + 0, + /* 1875 */ 'l', + 'b', + 'u', + 9, + 0, + /* 1880 */ 'b', + 'g', + 'e', + 'u', + 9, + 0, + /* 1886 */ 'm', + 'u', + 'l', + 'h', + 'u', + 9, + 0, + /* 1893 */ 's', + 'l', + 't', + 'i', + 'u', + 9, + 0, + /* 1900 */ 'f', + 'c', + 'v', + 't', + '.', + 'd', + '.', + 'l', + 'u', + 9, + 0, + /* 1911 */ 'f', + 'c', + 'v', + 't', + '.', + 's', + '.', + 'l', + 'u', + 9, + 0, + /* 1922 */ 'r', + 'e', + 'm', + 'u', + 9, + 0, + /* 1928 */ 'm', + 'u', + 'l', + 'h', + 's', + 'u', + 9, + 0, + /* 1936 */ 'b', + 'l', + 't', + 'u', + 9, + 0, + /* 1942 */ 's', + 'l', + 't', + 'u', + 9, + 0, + /* 1948 */ 'd', + 'i', + 'v', + 'u', + 9, + 0, + /* 1954 */ 'f', + 'c', + 'v', + 't', + '.', + 'd', + '.', + 'w', + 'u', + 9, + 0, + /* 1965 */ 'f', + 'c', + 'v', + 't', + '.', + 's', + '.', + 'w', + 'u', + 9, + 0, + /* 1976 */ 'l', + 'w', + 'u', + 9, + 0, + /* 1981 */ 'd', + 'i', + 'v', + 9, + 0, + /* 1986 */ 'c', + '.', + 'm', + 'v', + 9, + 0, + /* 1992 */ 's', + 'c', + '.', + 'w', + 9, + 0, + /* 1998 */ 'f', + 'c', + 'v', + 't', + '.', + 'd', + '.', + 'w', + 9, + 0, + /* 2008 */ 'a', + 'm', + 'o', + 'a', + 'd', + 'd', + '.', + 'w', + 9, + 0, + /* 2018 */ 'a', + 'm', + 'o', + 'a', + 'n', + 'd', + '.', + 'w', + 9, + 0, + /* 2028 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + '.', + 'w', + 9, + 0, + /* 2038 */ 'a', + 'm', + 'o', + 's', + 'w', + 'a', + 'p', + '.', + 'w', + 9, + 0, + /* 2049 */ 'l', + 'r', + '.', + 'w', + 9, + 0, + /* 2055 */ 'a', + 'm', + 'o', + 'o', + 'r', + '.', + 'w', + 9, + 0, + /* 2064 */ 'a', + 'm', + 'o', + 'x', + 'o', + 'r', + '.', + 'w', + 9, + 0, + /* 2074 */ 'f', + 'c', + 'v', + 't', + '.', + 's', + '.', + 'w', + 9, + 0, + /* 2084 */ 'a', + 'm', + 'o', + 'm', + 'i', + 'n', + 'u', + '.', + 'w', + 9, + 0, + /* 2095 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + 'u', + '.', + 'w', + 9, + 0, + /* 2106 */ 'f', + 'm', + 'v', + '.', + 'x', + '.', + 'w', + 9, + 0, + /* 2115 */ 'a', + 'm', + 'o', + 'm', + 'a', + 'x', + '.', + 'w', + 9, + 0, + /* 2125 */ 's', + 'r', + 'a', + 'w', + 9, + 0, + /* 2131 */ 'c', + '.', + 's', + 'u', + 'b', + 'w', + 9, + 0, + /* 2139 */ 'c', + '.', + 'a', + 'd', + 'd', + 'w', + 9, + 0, + /* 2147 */ 's', + 'r', + 'a', + 'i', + 'w', + 9, + 0, + /* 2154 */ 'c', + '.', + 'a', + 'd', + 'd', + 'i', + 'w', + 9, + 0, + /* 2163 */ 's', + 'l', + 'l', + 'i', + 'w', + 9, + 0, + /* 2170 */ 's', + 'r', + 'l', + 'i', + 'w', + 9, + 0, + /* 2177 */ 'c', + '.', + 'l', + 'w', + 9, + 0, + /* 2183 */ 'c', + '.', + 'f', + 'l', + 'w', + 9, + 0, + /* 2190 */ 's', + 'l', + 'l', + 'w', + 9, + 0, + /* 2196 */ 's', + 'r', + 'l', + 'w', + 9, + 0, + /* 2202 */ 'm', + 'u', + 'l', + 'w', + 9, + 0, + /* 2208 */ 'r', + 'e', + 'm', + 'w', + 9, + 0, + /* 2214 */ 'c', + 's', + 'r', + 'r', + 'w', + 9, + 0, + /* 2221 */ 'c', + '.', + 's', + 'w', + 9, + 0, + /* 2227 */ 'c', + '.', + 'f', + 's', + 'w', + 9, + 0, + /* 2234 */ 'r', + 'e', + 'm', + 'u', + 'w', + 9, + 0, + /* 2241 */ 'd', + 'i', + 'v', + 'u', + 'w', + 9, + 0, + /* 2248 */ 'd', + 'i', + 'v', + 'w', + 9, + 0, + /* 2254 */ 'f', + 'm', + 'v', + '.', + 'd', + '.', + 'x', + 9, + 0, + /* 2263 */ 'f', + 'm', + 'v', + '.', + 'w', + '.', + 'x', + 9, + 0, + /* 2272 */ 'c', + '.', + 'b', + 'n', + 'e', + 'z', + 9, + 0, + /* 2280 */ 'c', + '.', + 'b', + 'e', + 'q', + 'z', + 9, + 0, + /* 2288 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'P', + 'a', + 't', + 'c', + 'h', + 'a', + 'b', + 'l', + 'e', + 32, + 'R', + 'E', + 'T', + '.', + 0, + /* 2319 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'y', + 'p', + 'e', + 'd', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 2343 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'C', + 'u', + 's', + 't', + 'o', + 'm', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 2368 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'n', + 't', + 'e', + 'r', + '.', + 0, + /* 2391 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'a', + 'i', + 'l', + 32, + 'C', + 'a', + 'l', + 'l', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 2414 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 2436 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'E', + 'N', + 'D', + 0, + /* 2449 */ 'B', + 'U', + 'N', + 'D', + 'L', + 'E', + 0, + /* 2456 */ 'D', + 'B', + 'G', + '_', + 'V', + 'A', + 'L', + 'U', + 'E', + 0, + /* 2466 */ 'D', + 'B', + 'G', + '_', + 'L', + 'A', + 'B', + 'E', + 'L', + 0, + /* 2476 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'S', + 'T', + 'A', + 'R', + 'T', + 0, + /* 2491 */ '#', + 32, + 'F', + 'E', + 'n', + 't', + 'r', + 'y', + 32, + 'c', + 'a', + 'l', + 'l', + 0, }; #endif static const uint16_t OpInfo0[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // INLINEASM_BR - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 2457U, // DBG_VALUE - 2467U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 2450U, // BUNDLE - 2477U, // LIFETIME_START - 2437U, // LIFETIME_END - 0U, // STACKMAP - 2492U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 2369U, // PATCHABLE_FUNCTION_ENTER - 2289U, // PATCHABLE_RET - 2415U, // PATCHABLE_FUNCTION_EXIT - 2392U, // PATCHABLE_TAIL_CALL - 2344U, // PATCHABLE_EVENT_CALL - 2320U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_BUILD_VECTOR - 0U, // G_BUILD_VECTOR_TRUNC - 0U, // G_CONCAT_VECTORS - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_INTRINSIC_TRUNC - 0U, // G_INTRINSIC_ROUND - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDO - 0U, // G_UADDE - 0U, // G_USUBO - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SADDE - 0U, // G_SSUBO - 0U, // G_SSUBE - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FLOG10 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_FCANONICALIZE - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_CTTZ - 0U, // G_CTTZ_ZERO_UNDEF - 0U, // G_CTLZ - 0U, // G_CTLZ_ZERO_UNDEF - 0U, // G_CTPOP - 0U, // G_BSWAP - 0U, // G_FCEIL - 0U, // G_FCOS - 0U, // G_FSIN - 0U, // G_FSQRT - 0U, // G_FFLOOR - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 4U, // ADJCALLSTACKDOWN - 4U, // ADJCALLSTACKUP - 4U, // BuildPairF64Pseudo - 4U, // PseudoAtomicLoadNand32 - 4U, // PseudoAtomicLoadNand64 - 4U, // PseudoBR - 4U, // PseudoBRIND - 4687U, // PseudoCALL - 4U, // PseudoCALLIndirect - 4U, // PseudoCmpXchg32 - 4U, // PseudoCmpXchg64 - 20482U, // PseudoLA - 20967U, // PseudoLI - 20481U, // PseudoLLA - 4U, // PseudoMaskedAtomicLoadAdd32 - 4U, // PseudoMaskedAtomicLoadMax32 - 4U, // PseudoMaskedAtomicLoadMin32 - 4U, // PseudoMaskedAtomicLoadNand32 - 4U, // PseudoMaskedAtomicLoadSub32 - 4U, // PseudoMaskedAtomicLoadUMax32 - 4U, // PseudoMaskedAtomicLoadUMin32 - 4U, // PseudoMaskedAtomicSwap32 - 4U, // PseudoMaskedCmpXchg32 - 4U, // PseudoRET - 4680U, // PseudoTAIL - 4U, // PseudoTAILIndirect - 4U, // Select_FPR32_Using_CC_GPR - 4U, // Select_FPR64_Using_CC_GPR - 4U, // Select_GPR_Using_CC_GPR - 4U, // SplitF64Pseudo - 20854U, // ADD - 20946U, // ADDI - 22637U, // ADDIW - 22622U, // ADDW - 20592U, // AMOADD_D - 21817U, // AMOADD_D_AQ - 21367U, // AMOADD_D_AQ_RL - 21091U, // AMOADD_D_RL - 22489U, // AMOADD_W - 21954U, // AMOADD_W_AQ - 21526U, // AMOADD_W_AQ_RL - 21228U, // AMOADD_W_RL - 20602U, // AMOAND_D - 21830U, // AMOAND_D_AQ - 21382U, // AMOAND_D_AQ_RL - 21104U, // AMOAND_D_RL - 22499U, // AMOAND_W - 21967U, // AMOAND_W_AQ - 21541U, // AMOAND_W_AQ_RL - 21241U, // AMOAND_W_RL - 20786U, // AMOMAXU_D - 21918U, // AMOMAXU_D_AQ - 21484U, // AMOMAXU_D_AQ_RL - 21192U, // AMOMAXU_D_RL - 22576U, // AMOMAXU_W - 22055U, // AMOMAXU_W_AQ - 21643U, // AMOMAXU_W_AQ_RL - 21329U, // AMOMAXU_W_RL - 20832U, // AMOMAX_D - 21932U, // AMOMAX_D_AQ - 21500U, // AMOMAX_D_AQ_RL - 21206U, // AMOMAX_D_RL - 22596U, // AMOMAX_W - 22069U, // AMOMAX_W_AQ - 21659U, // AMOMAX_W_AQ_RL - 21343U, // AMOMAX_W_RL - 20764U, // AMOMINU_D - 21904U, // AMOMINU_D_AQ - 21468U, // AMOMINU_D_AQ_RL - 21178U, // AMOMINU_D_RL - 22565U, // AMOMINU_W - 22041U, // AMOMINU_W_AQ - 21627U, // AMOMINU_W_AQ_RL - 21315U, // AMOMINU_W_RL - 20654U, // AMOMIN_D - 21843U, // AMOMIN_D_AQ - 21397U, // AMOMIN_D_AQ_RL - 21117U, // AMOMIN_D_RL - 22509U, // AMOMIN_W - 21980U, // AMOMIN_W_AQ - 21556U, // AMOMIN_W_AQ_RL - 21254U, // AMOMIN_W_RL - 20698U, // AMOOR_D - 21879U, // AMOOR_D_AQ - 21439U, // AMOOR_D_AQ_RL - 21153U, // AMOOR_D_RL - 22536U, // AMOOR_W - 22016U, // AMOOR_W_AQ - 21598U, // AMOOR_W_AQ_RL - 21290U, // AMOOR_W_RL - 20674U, // AMOSWAP_D - 21856U, // AMOSWAP_D_AQ - 21412U, // AMOSWAP_D_AQ_RL - 21130U, // AMOSWAP_D_RL - 22519U, // AMOSWAP_W - 21993U, // AMOSWAP_W_AQ - 21571U, // AMOSWAP_W_AQ_RL - 21267U, // AMOSWAP_W_RL - 20707U, // AMOXOR_D - 21891U, // AMOXOR_D_AQ - 21453U, // AMOXOR_D_AQ_RL - 21165U, // AMOXOR_D_RL - 22545U, // AMOXOR_W - 22028U, // AMOXOR_W_AQ - 21612U, // AMOXOR_W_AQ_RL - 21302U, // AMOXOR_W_RL - 20874U, // AND - 20954U, // ANDI - 20518U, // AUIPC - 22082U, // BEQ - 20899U, // BGE - 22361U, // BGEU - 22346U, // BLT - 22417U, // BLTU - 20904U, // BNE - 20525U, // CSRRC - 20936U, // CSRRCI - 22321U, // CSRRS - 20993U, // CSRRSI - 22695U, // CSRRW - 21014U, // CSRRWI - 8564U, // C_ADD - 8656U, // C_ADDI - 9440U, // C_ADDI16SP - 21689U, // C_ADDI4SPN - 10347U, // C_ADDIW - 10332U, // C_ADDW - 8584U, // C_AND - 8664U, // C_ANDI - 22761U, // C_BEQZ - 22753U, // C_BNEZ - 547U, // C_EBREAK - 20865U, // C_FLD - 21748U, // C_FLDSP - 22664U, // C_FLW - 21782U, // C_FLWSP - 20885U, // C_FSD - 21765U, // C_FSDSP - 22708U, // C_FSW - 21799U, // C_FSWSP - 4638U, // C_J - 4673U, // C_JAL - 5709U, // C_JALR - 5703U, // C_JR - 20859U, // C_LD - 21740U, // C_LDSP - 20965U, // C_LI - 21007U, // C_LUI - 22658U, // C_LW - 21774U, // C_LWSP - 22467U, // C_MV - 1241U, // C_NOP - 9813U, // C_OR - 20879U, // C_SD - 21757U, // C_SDSP - 8683U, // C_SLLI - 8640U, // C_SRAI - 8691U, // C_SRLI - 8223U, // C_SUB - 10324U, // C_SUBW - 22702U, // C_SW - 21791U, // C_SWSP - 1232U, // C_UNIMP - 9819U, // C_XOR - 22462U, // DIV - 22429U, // DIVU - 22722U, // DIVUW - 22729U, // DIVW - 549U, // EBREAK - 590U, // ECALL - 20565U, // FADD_D - 22151U, // FADD_S - 20727U, // FCLASS_D - 22237U, // FCLASS_S - 21037U, // FCVT_D_L - 22381U, // FCVT_D_LU - 22141U, // FCVT_D_S - 22479U, // FCVT_D_W - 22435U, // FCVT_D_WU - 20753U, // FCVT_LU_D - 22263U, // FCVT_LU_S - 20628U, // FCVT_L_D - 22194U, // FCVT_L_S - 20717U, // FCVT_S_D - 21047U, // FCVT_S_L - 22392U, // FCVT_S_LU - 22555U, // FCVT_S_W - 22446U, // FCVT_S_WU - 20775U, // FCVT_WU_D - 22274U, // FCVT_WU_S - 20805U, // FCVT_W_D - 22293U, // FCVT_W_S - 20797U, // FDIV_D - 22285U, // FDIV_S - 12700U, // FENCE - 439U, // FENCE_I - 1221U, // FENCE_TSO - 20685U, // FEQ_D - 22230U, // FEQ_S - 20867U, // FLD - 20612U, // FLE_D - 22178U, // FLE_S - 20737U, // FLT_D - 22247U, // FLT_S - 22666U, // FLW - 20573U, // FMADD_D - 22159U, // FMADD_S - 20824U, // FMAX_D - 22303U, // FMAX_S - 20646U, // FMIN_D - 22212U, // FMIN_S - 20540U, // FMSUB_D - 22122U, // FMSUB_S - 20638U, // FMUL_D - 22204U, // FMUL_S - 22735U, // FMV_D_X - 22744U, // FMV_W_X - 20815U, // FMV_X_D - 22587U, // FMV_X_W - 20582U, // FNMADD_D - 22168U, // FNMADD_S - 20549U, // FNMSUB_D - 22131U, // FNMSUB_S - 20887U, // FSD - 20664U, // FSGNJN_D - 22220U, // FSGNJN_S - 20842U, // FSGNJX_D - 22311U, // FSGNJX_S - 20619U, // FSGNJ_D - 22185U, // FSGNJ_S - 20744U, // FSQRT_D - 22254U, // FSQRT_S - 20532U, // FSUB_D - 22114U, // FSUB_S - 22710U, // FSW - 21059U, // JAL - 22095U, // JALR - 20503U, // LB - 22356U, // LBU - 20861U, // LD - 20911U, // LH - 22369U, // LHU - 37076U, // LR_D - 38254U, // LR_D_AQ - 37812U, // LR_D_AQ_RL - 37528U, // LR_D_RL - 38914U, // LR_W - 38391U, // LR_W_AQ - 37971U, // LR_W_AQ_RL - 37665U, // LR_W_RL - 21009U, // LUI - 22660U, // LW - 22457U, // LWU - 1848U, // MRET - 21679U, // MUL - 20909U, // MULH - 22409U, // MULHSU - 22367U, // MULHU - 22683U, // MULW - 22103U, // OR - 20988U, // ORI - 21684U, // REM - 22403U, // REMU - 22715U, // REMUW - 22689U, // REMW - 20507U, // SB - 20559U, // SC_D - 21808U, // SC_D_AQ - 21356U, // SC_D_AQ_RL - 21082U, // SC_D_RL - 22473U, // SC_W - 21945U, // SC_W_AQ - 21515U, // SC_W_AQ_RL - 21219U, // SC_W_RL - 20881U, // SD - 20486U, // SFENCE_VMA - 20915U, // SH - 21077U, // SLL - 20973U, // SLLI - 22644U, // SLLIW - 22671U, // SLLW - 22351U, // SLT - 21001U, // SLTI - 22374U, // SLTIU - 22423U, // SLTU - 20498U, // SRA - 20930U, // SRAI - 22628U, // SRAIW - 22606U, // SRAW - 1854U, // SRET - 21674U, // SRL - 20981U, // SRLI - 22651U, // SRLIW - 22677U, // SRLW - 20513U, // SUB - 22614U, // SUBW - 22704U, // SW - 1234U, // UNIMP - 1860U, // URET - 480U, // WFI - 22109U, // XOR - 20987U, // XORI + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2457U, // DBG_VALUE + 2467U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 2450U, // BUNDLE + 2477U, // LIFETIME_START + 2437U, // LIFETIME_END + 0U, // STACKMAP + 2492U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 2369U, // PATCHABLE_FUNCTION_ENTER + 2289U, // PATCHABLE_RET + 2415U, // PATCHABLE_FUNCTION_EXIT + 2392U, // PATCHABLE_TAIL_CALL + 2344U, // PATCHABLE_EVENT_CALL + 2320U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCANONICALIZE + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 4U, // ADJCALLSTACKDOWN + 4U, // ADJCALLSTACKUP + 4U, // BuildPairF64Pseudo + 4U, // PseudoAtomicLoadNand32 + 4U, // PseudoAtomicLoadNand64 + 4U, // PseudoBR + 4U, // PseudoBRIND + 4687U, // PseudoCALL + 4U, // PseudoCALLIndirect + 4U, // PseudoCmpXchg32 + 4U, // PseudoCmpXchg64 + 20482U, // PseudoLA + 20967U, // PseudoLI + 20481U, // PseudoLLA + 4U, // PseudoMaskedAtomicLoadAdd32 + 4U, // PseudoMaskedAtomicLoadMax32 + 4U, // PseudoMaskedAtomicLoadMin32 + 4U, // PseudoMaskedAtomicLoadNand32 + 4U, // PseudoMaskedAtomicLoadSub32 + 4U, // PseudoMaskedAtomicLoadUMax32 + 4U, // PseudoMaskedAtomicLoadUMin32 + 4U, // PseudoMaskedAtomicSwap32 + 4U, // PseudoMaskedCmpXchg32 + 4U, // PseudoRET + 4680U, // PseudoTAIL + 4U, // PseudoTAILIndirect + 4U, // Select_FPR32_Using_CC_GPR + 4U, // Select_FPR64_Using_CC_GPR + 4U, // Select_GPR_Using_CC_GPR + 4U, // SplitF64Pseudo + 20854U, // ADD + 20946U, // ADDI + 22637U, // ADDIW + 22622U, // ADDW + 20592U, // AMOADD_D + 21817U, // AMOADD_D_AQ + 21367U, // AMOADD_D_AQ_RL + 21091U, // AMOADD_D_RL + 22489U, // AMOADD_W + 21954U, // AMOADD_W_AQ + 21526U, // AMOADD_W_AQ_RL + 21228U, // AMOADD_W_RL + 20602U, // AMOAND_D + 21830U, // AMOAND_D_AQ + 21382U, // AMOAND_D_AQ_RL + 21104U, // AMOAND_D_RL + 22499U, // AMOAND_W + 21967U, // AMOAND_W_AQ + 21541U, // AMOAND_W_AQ_RL + 21241U, // AMOAND_W_RL + 20786U, // AMOMAXU_D + 21918U, // AMOMAXU_D_AQ + 21484U, // AMOMAXU_D_AQ_RL + 21192U, // AMOMAXU_D_RL + 22576U, // AMOMAXU_W + 22055U, // AMOMAXU_W_AQ + 21643U, // AMOMAXU_W_AQ_RL + 21329U, // AMOMAXU_W_RL + 20832U, // AMOMAX_D + 21932U, // AMOMAX_D_AQ + 21500U, // AMOMAX_D_AQ_RL + 21206U, // AMOMAX_D_RL + 22596U, // AMOMAX_W + 22069U, // AMOMAX_W_AQ + 21659U, // AMOMAX_W_AQ_RL + 21343U, // AMOMAX_W_RL + 20764U, // AMOMINU_D + 21904U, // AMOMINU_D_AQ + 21468U, // AMOMINU_D_AQ_RL + 21178U, // AMOMINU_D_RL + 22565U, // AMOMINU_W + 22041U, // AMOMINU_W_AQ + 21627U, // AMOMINU_W_AQ_RL + 21315U, // AMOMINU_W_RL + 20654U, // AMOMIN_D + 21843U, // AMOMIN_D_AQ + 21397U, // AMOMIN_D_AQ_RL + 21117U, // AMOMIN_D_RL + 22509U, // AMOMIN_W + 21980U, // AMOMIN_W_AQ + 21556U, // AMOMIN_W_AQ_RL + 21254U, // AMOMIN_W_RL + 20698U, // AMOOR_D + 21879U, // AMOOR_D_AQ + 21439U, // AMOOR_D_AQ_RL + 21153U, // AMOOR_D_RL + 22536U, // AMOOR_W + 22016U, // AMOOR_W_AQ + 21598U, // AMOOR_W_AQ_RL + 21290U, // AMOOR_W_RL + 20674U, // AMOSWAP_D + 21856U, // AMOSWAP_D_AQ + 21412U, // AMOSWAP_D_AQ_RL + 21130U, // AMOSWAP_D_RL + 22519U, // AMOSWAP_W + 21993U, // AMOSWAP_W_AQ + 21571U, // AMOSWAP_W_AQ_RL + 21267U, // AMOSWAP_W_RL + 20707U, // AMOXOR_D + 21891U, // AMOXOR_D_AQ + 21453U, // AMOXOR_D_AQ_RL + 21165U, // AMOXOR_D_RL + 22545U, // AMOXOR_W + 22028U, // AMOXOR_W_AQ + 21612U, // AMOXOR_W_AQ_RL + 21302U, // AMOXOR_W_RL + 20874U, // AND + 20954U, // ANDI + 20518U, // AUIPC + 22082U, // BEQ + 20899U, // BGE + 22361U, // BGEU + 22346U, // BLT + 22417U, // BLTU + 20904U, // BNE + 20525U, // CSRRC + 20936U, // CSRRCI + 22321U, // CSRRS + 20993U, // CSRRSI + 22695U, // CSRRW + 21014U, // CSRRWI + 8564U, // C_ADD + 8656U, // C_ADDI + 9440U, // C_ADDI16SP + 21689U, // C_ADDI4SPN + 10347U, // C_ADDIW + 10332U, // C_ADDW + 8584U, // C_AND + 8664U, // C_ANDI + 22761U, // C_BEQZ + 22753U, // C_BNEZ + 547U, // C_EBREAK + 20865U, // C_FLD + 21748U, // C_FLDSP + 22664U, // C_FLW + 21782U, // C_FLWSP + 20885U, // C_FSD + 21765U, // C_FSDSP + 22708U, // C_FSW + 21799U, // C_FSWSP + 4638U, // C_J + 4673U, // C_JAL + 5709U, // C_JALR + 5703U, // C_JR + 20859U, // C_LD + 21740U, // C_LDSP + 20965U, // C_LI + 21007U, // C_LUI + 22658U, // C_LW + 21774U, // C_LWSP + 22467U, // C_MV + 1241U, // C_NOP + 9813U, // C_OR + 20879U, // C_SD + 21757U, // C_SDSP + 8683U, // C_SLLI + 8640U, // C_SRAI + 8691U, // C_SRLI + 8223U, // C_SUB + 10324U, // C_SUBW + 22702U, // C_SW + 21791U, // C_SWSP + 1232U, // C_UNIMP + 9819U, // C_XOR + 22462U, // DIV + 22429U, // DIVU + 22722U, // DIVUW + 22729U, // DIVW + 549U, // EBREAK + 590U, // ECALL + 20565U, // FADD_D + 22151U, // FADD_S + 20727U, // FCLASS_D + 22237U, // FCLASS_S + 21037U, // FCVT_D_L + 22381U, // FCVT_D_LU + 22141U, // FCVT_D_S + 22479U, // FCVT_D_W + 22435U, // FCVT_D_WU + 20753U, // FCVT_LU_D + 22263U, // FCVT_LU_S + 20628U, // FCVT_L_D + 22194U, // FCVT_L_S + 20717U, // FCVT_S_D + 21047U, // FCVT_S_L + 22392U, // FCVT_S_LU + 22555U, // FCVT_S_W + 22446U, // FCVT_S_WU + 20775U, // FCVT_WU_D + 22274U, // FCVT_WU_S + 20805U, // FCVT_W_D + 22293U, // FCVT_W_S + 20797U, // FDIV_D + 22285U, // FDIV_S + 12700U, // FENCE + 439U, // FENCE_I + 1221U, // FENCE_TSO + 20685U, // FEQ_D + 22230U, // FEQ_S + 20867U, // FLD + 20612U, // FLE_D + 22178U, // FLE_S + 20737U, // FLT_D + 22247U, // FLT_S + 22666U, // FLW + 20573U, // FMADD_D + 22159U, // FMADD_S + 20824U, // FMAX_D + 22303U, // FMAX_S + 20646U, // FMIN_D + 22212U, // FMIN_S + 20540U, // FMSUB_D + 22122U, // FMSUB_S + 20638U, // FMUL_D + 22204U, // FMUL_S + 22735U, // FMV_D_X + 22744U, // FMV_W_X + 20815U, // FMV_X_D + 22587U, // FMV_X_W + 20582U, // FNMADD_D + 22168U, // FNMADD_S + 20549U, // FNMSUB_D + 22131U, // FNMSUB_S + 20887U, // FSD + 20664U, // FSGNJN_D + 22220U, // FSGNJN_S + 20842U, // FSGNJX_D + 22311U, // FSGNJX_S + 20619U, // FSGNJ_D + 22185U, // FSGNJ_S + 20744U, // FSQRT_D + 22254U, // FSQRT_S + 20532U, // FSUB_D + 22114U, // FSUB_S + 22710U, // FSW + 21059U, // JAL + 22095U, // JALR + 20503U, // LB + 22356U, // LBU + 20861U, // LD + 20911U, // LH + 22369U, // LHU + 37076U, // LR_D + 38254U, // LR_D_AQ + 37812U, // LR_D_AQ_RL + 37528U, // LR_D_RL + 38914U, // LR_W + 38391U, // LR_W_AQ + 37971U, // LR_W_AQ_RL + 37665U, // LR_W_RL + 21009U, // LUI + 22660U, // LW + 22457U, // LWU + 1848U, // MRET + 21679U, // MUL + 20909U, // MULH + 22409U, // MULHSU + 22367U, // MULHU + 22683U, // MULW + 22103U, // OR + 20988U, // ORI + 21684U, // REM + 22403U, // REMU + 22715U, // REMUW + 22689U, // REMW + 20507U, // SB + 20559U, // SC_D + 21808U, // SC_D_AQ + 21356U, // SC_D_AQ_RL + 21082U, // SC_D_RL + 22473U, // SC_W + 21945U, // SC_W_AQ + 21515U, // SC_W_AQ_RL + 21219U, // SC_W_RL + 20881U, // SD + 20486U, // SFENCE_VMA + 20915U, // SH + 21077U, // SLL + 20973U, // SLLI + 22644U, // SLLIW + 22671U, // SLLW + 22351U, // SLT + 21001U, // SLTI + 22374U, // SLTIU + 22423U, // SLTU + 20498U, // SRA + 20930U, // SRAI + 22628U, // SRAIW + 22606U, // SRAW + 1854U, // SRET + 21674U, // SRL + 20981U, // SRLI + 22651U, // SRLIW + 22677U, // SRLW + 20513U, // SUB + 22614U, // SUBW + 22704U, // SW + 1234U, // UNIMP + 1860U, // URET + 480U, // WFI + 22109U, // XOR + 20987U, // XORI }; static const uint8_t OpInfo1[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // INLINEASM_BR - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 0U, // DBG_VALUE - 0U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 0U, // BUNDLE - 0U, // LIFETIME_START - 0U, // LIFETIME_END - 0U, // STACKMAP - 0U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 0U, // PATCHABLE_FUNCTION_ENTER - 0U, // PATCHABLE_RET - 0U, // PATCHABLE_FUNCTION_EXIT - 0U, // PATCHABLE_TAIL_CALL - 0U, // PATCHABLE_EVENT_CALL - 0U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_BUILD_VECTOR - 0U, // G_BUILD_VECTOR_TRUNC - 0U, // G_CONCAT_VECTORS - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_INTRINSIC_TRUNC - 0U, // G_INTRINSIC_ROUND - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDO - 0U, // G_UADDE - 0U, // G_USUBO - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SADDE - 0U, // G_SSUBO - 0U, // G_SSUBE - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FLOG10 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_FCANONICALIZE - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_CTTZ - 0U, // G_CTTZ_ZERO_UNDEF - 0U, // G_CTLZ - 0U, // G_CTLZ_ZERO_UNDEF - 0U, // G_CTPOP - 0U, // G_BSWAP - 0U, // G_FCEIL - 0U, // G_FCOS - 0U, // G_FSIN - 0U, // G_FSQRT - 0U, // G_FFLOOR - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 0U, // BuildPairF64Pseudo - 0U, // PseudoAtomicLoadNand32 - 0U, // PseudoAtomicLoadNand64 - 0U, // PseudoBR - 0U, // PseudoBRIND - 0U, // PseudoCALL - 0U, // PseudoCALLIndirect - 0U, // PseudoCmpXchg32 - 0U, // PseudoCmpXchg64 - 0U, // PseudoLA - 0U, // PseudoLI - 0U, // PseudoLLA - 0U, // PseudoMaskedAtomicLoadAdd32 - 0U, // PseudoMaskedAtomicLoadMax32 - 0U, // PseudoMaskedAtomicLoadMin32 - 0U, // PseudoMaskedAtomicLoadNand32 - 0U, // PseudoMaskedAtomicLoadSub32 - 0U, // PseudoMaskedAtomicLoadUMax32 - 0U, // PseudoMaskedAtomicLoadUMin32 - 0U, // PseudoMaskedAtomicSwap32 - 0U, // PseudoMaskedCmpXchg32 - 0U, // PseudoRET - 0U, // PseudoTAIL - 0U, // PseudoTAILIndirect - 0U, // Select_FPR32_Using_CC_GPR - 0U, // Select_FPR64_Using_CC_GPR - 0U, // Select_GPR_Using_CC_GPR - 0U, // SplitF64Pseudo - 4U, // ADD - 4U, // ADDI - 4U, // ADDIW - 4U, // ADDW - 9U, // AMOADD_D - 9U, // AMOADD_D_AQ - 9U, // AMOADD_D_AQ_RL - 9U, // AMOADD_D_RL - 9U, // AMOADD_W - 9U, // AMOADD_W_AQ - 9U, // AMOADD_W_AQ_RL - 9U, // AMOADD_W_RL - 9U, // AMOAND_D - 9U, // AMOAND_D_AQ - 9U, // AMOAND_D_AQ_RL - 9U, // AMOAND_D_RL - 9U, // AMOAND_W - 9U, // AMOAND_W_AQ - 9U, // AMOAND_W_AQ_RL - 9U, // AMOAND_W_RL - 9U, // AMOMAXU_D - 9U, // AMOMAXU_D_AQ - 9U, // AMOMAXU_D_AQ_RL - 9U, // AMOMAXU_D_RL - 9U, // AMOMAXU_W - 9U, // AMOMAXU_W_AQ - 9U, // AMOMAXU_W_AQ_RL - 9U, // AMOMAXU_W_RL - 9U, // AMOMAX_D - 9U, // AMOMAX_D_AQ - 9U, // AMOMAX_D_AQ_RL - 9U, // AMOMAX_D_RL - 9U, // AMOMAX_W - 9U, // AMOMAX_W_AQ - 9U, // AMOMAX_W_AQ_RL - 9U, // AMOMAX_W_RL - 9U, // AMOMINU_D - 9U, // AMOMINU_D_AQ - 9U, // AMOMINU_D_AQ_RL - 9U, // AMOMINU_D_RL - 9U, // AMOMINU_W - 9U, // AMOMINU_W_AQ - 9U, // AMOMINU_W_AQ_RL - 9U, // AMOMINU_W_RL - 9U, // AMOMIN_D - 9U, // AMOMIN_D_AQ - 9U, // AMOMIN_D_AQ_RL - 9U, // AMOMIN_D_RL - 9U, // AMOMIN_W - 9U, // AMOMIN_W_AQ - 9U, // AMOMIN_W_AQ_RL - 9U, // AMOMIN_W_RL - 9U, // AMOOR_D - 9U, // AMOOR_D_AQ - 9U, // AMOOR_D_AQ_RL - 9U, // AMOOR_D_RL - 9U, // AMOOR_W - 9U, // AMOOR_W_AQ - 9U, // AMOOR_W_AQ_RL - 9U, // AMOOR_W_RL - 9U, // AMOSWAP_D - 9U, // AMOSWAP_D_AQ - 9U, // AMOSWAP_D_AQ_RL - 9U, // AMOSWAP_D_RL - 9U, // AMOSWAP_W - 9U, // AMOSWAP_W_AQ - 9U, // AMOSWAP_W_AQ_RL - 9U, // AMOSWAP_W_RL - 9U, // AMOXOR_D - 9U, // AMOXOR_D_AQ - 9U, // AMOXOR_D_AQ_RL - 9U, // AMOXOR_D_RL - 9U, // AMOXOR_W - 9U, // AMOXOR_W_AQ - 9U, // AMOXOR_W_AQ_RL - 9U, // AMOXOR_W_RL - 4U, // AND - 4U, // ANDI - 0U, // AUIPC - 4U, // BEQ - 4U, // BGE - 4U, // BGEU - 4U, // BLT - 4U, // BLTU - 4U, // BNE - 2U, // CSRRC - 2U, // CSRRCI - 2U, // CSRRS - 2U, // CSRRSI - 2U, // CSRRW - 2U, // CSRRWI - 0U, // C_ADD - 0U, // C_ADDI - 0U, // C_ADDI16SP - 4U, // C_ADDI4SPN - 0U, // C_ADDIW - 0U, // C_ADDW - 0U, // C_AND - 0U, // C_ANDI - 0U, // C_BEQZ - 0U, // C_BNEZ - 0U, // C_EBREAK - 13U, // C_FLD - 13U, // C_FLDSP - 13U, // C_FLW - 13U, // C_FLWSP - 13U, // C_FSD - 13U, // C_FSDSP - 13U, // C_FSW - 13U, // C_FSWSP - 0U, // C_J - 0U, // C_JAL - 0U, // C_JALR - 0U, // C_JR - 13U, // C_LD - 13U, // C_LDSP - 0U, // C_LI - 0U, // C_LUI - 13U, // C_LW - 13U, // C_LWSP - 0U, // C_MV - 0U, // C_NOP - 0U, // C_OR - 13U, // C_SD - 13U, // C_SDSP - 0U, // C_SLLI - 0U, // C_SRAI - 0U, // C_SRLI - 0U, // C_SUB - 0U, // C_SUBW - 13U, // C_SW - 13U, // C_SWSP - 0U, // C_UNIMP - 0U, // C_XOR - 4U, // DIV - 4U, // DIVU - 4U, // DIVUW - 4U, // DIVW - 0U, // EBREAK - 0U, // ECALL - 36U, // FADD_D - 36U, // FADD_S - 0U, // FCLASS_D - 0U, // FCLASS_S - 20U, // FCVT_D_L - 20U, // FCVT_D_LU - 0U, // FCVT_D_S - 0U, // FCVT_D_W - 0U, // FCVT_D_WU - 20U, // FCVT_LU_D - 20U, // FCVT_LU_S - 20U, // FCVT_L_D - 20U, // FCVT_L_S - 20U, // FCVT_S_D - 20U, // FCVT_S_L - 20U, // FCVT_S_LU - 20U, // FCVT_S_W - 20U, // FCVT_S_WU - 20U, // FCVT_WU_D - 20U, // FCVT_WU_S - 20U, // FCVT_W_D - 20U, // FCVT_W_S - 36U, // FDIV_D - 36U, // FDIV_S - 0U, // FENCE - 0U, // FENCE_I - 0U, // FENCE_TSO - 4U, // FEQ_D - 4U, // FEQ_S - 13U, // FLD - 4U, // FLE_D - 4U, // FLE_S - 4U, // FLT_D - 4U, // FLT_S - 13U, // FLW - 100U, // FMADD_D - 100U, // FMADD_S - 4U, // FMAX_D - 4U, // FMAX_S - 4U, // FMIN_D - 4U, // FMIN_S - 100U, // FMSUB_D - 100U, // FMSUB_S - 36U, // FMUL_D - 36U, // FMUL_S - 0U, // FMV_D_X - 0U, // FMV_W_X - 0U, // FMV_X_D - 0U, // FMV_X_W - 100U, // FNMADD_D - 100U, // FNMADD_S - 100U, // FNMSUB_D - 100U, // FNMSUB_S - 13U, // FSD - 4U, // FSGNJN_D - 4U, // FSGNJN_S - 4U, // FSGNJX_D - 4U, // FSGNJX_S - 4U, // FSGNJ_D - 4U, // FSGNJ_S - 20U, // FSQRT_D - 20U, // FSQRT_S - 36U, // FSUB_D - 36U, // FSUB_S - 13U, // FSW - 0U, // JAL - 4U, // JALR - 13U, // LB - 13U, // LBU - 13U, // LD - 13U, // LH - 13U, // LHU - 0U, // LR_D - 0U, // LR_D_AQ - 0U, // LR_D_AQ_RL - 0U, // LR_D_RL - 0U, // LR_W - 0U, // LR_W_AQ - 0U, // LR_W_AQ_RL - 0U, // LR_W_RL - 0U, // LUI - 13U, // LW - 13U, // LWU - 0U, // MRET - 4U, // MUL - 4U, // MULH - 4U, // MULHSU - 4U, // MULHU - 4U, // MULW - 4U, // OR - 4U, // ORI - 4U, // REM - 4U, // REMU - 4U, // REMUW - 4U, // REMW - 13U, // SB - 9U, // SC_D - 9U, // SC_D_AQ - 9U, // SC_D_AQ_RL - 9U, // SC_D_RL - 9U, // SC_W - 9U, // SC_W_AQ - 9U, // SC_W_AQ_RL - 9U, // SC_W_RL - 13U, // SD - 0U, // SFENCE_VMA - 13U, // SH - 4U, // SLL - 4U, // SLLI - 4U, // SLLIW - 4U, // SLLW - 4U, // SLT - 4U, // SLTI - 4U, // SLTIU - 4U, // SLTU - 4U, // SRA - 4U, // SRAI - 4U, // SRAIW - 4U, // SRAW - 0U, // SRET - 4U, // SRL - 4U, // SRLI - 4U, // SRLIW - 4U, // SRLW - 4U, // SUB - 4U, // SUBW - 13U, // SW - 0U, // UNIMP - 0U, // URET - 0U, // WFI - 4U, // XOR - 4U, // XORI + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCANONICALIZE + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // BuildPairF64Pseudo + 0U, // PseudoAtomicLoadNand32 + 0U, // PseudoAtomicLoadNand64 + 0U, // PseudoBR + 0U, // PseudoBRIND + 0U, // PseudoCALL + 0U, // PseudoCALLIndirect + 0U, // PseudoCmpXchg32 + 0U, // PseudoCmpXchg64 + 0U, // PseudoLA + 0U, // PseudoLI + 0U, // PseudoLLA + 0U, // PseudoMaskedAtomicLoadAdd32 + 0U, // PseudoMaskedAtomicLoadMax32 + 0U, // PseudoMaskedAtomicLoadMin32 + 0U, // PseudoMaskedAtomicLoadNand32 + 0U, // PseudoMaskedAtomicLoadSub32 + 0U, // PseudoMaskedAtomicLoadUMax32 + 0U, // PseudoMaskedAtomicLoadUMin32 + 0U, // PseudoMaskedAtomicSwap32 + 0U, // PseudoMaskedCmpXchg32 + 0U, // PseudoRET + 0U, // PseudoTAIL + 0U, // PseudoTAILIndirect + 0U, // Select_FPR32_Using_CC_GPR + 0U, // Select_FPR64_Using_CC_GPR + 0U, // Select_GPR_Using_CC_GPR + 0U, // SplitF64Pseudo + 4U, // ADD + 4U, // ADDI + 4U, // ADDIW + 4U, // ADDW + 9U, // AMOADD_D + 9U, // AMOADD_D_AQ + 9U, // AMOADD_D_AQ_RL + 9U, // AMOADD_D_RL + 9U, // AMOADD_W + 9U, // AMOADD_W_AQ + 9U, // AMOADD_W_AQ_RL + 9U, // AMOADD_W_RL + 9U, // AMOAND_D + 9U, // AMOAND_D_AQ + 9U, // AMOAND_D_AQ_RL + 9U, // AMOAND_D_RL + 9U, // AMOAND_W + 9U, // AMOAND_W_AQ + 9U, // AMOAND_W_AQ_RL + 9U, // AMOAND_W_RL + 9U, // AMOMAXU_D + 9U, // AMOMAXU_D_AQ + 9U, // AMOMAXU_D_AQ_RL + 9U, // AMOMAXU_D_RL + 9U, // AMOMAXU_W + 9U, // AMOMAXU_W_AQ + 9U, // AMOMAXU_W_AQ_RL + 9U, // AMOMAXU_W_RL + 9U, // AMOMAX_D + 9U, // AMOMAX_D_AQ + 9U, // AMOMAX_D_AQ_RL + 9U, // AMOMAX_D_RL + 9U, // AMOMAX_W + 9U, // AMOMAX_W_AQ + 9U, // AMOMAX_W_AQ_RL + 9U, // AMOMAX_W_RL + 9U, // AMOMINU_D + 9U, // AMOMINU_D_AQ + 9U, // AMOMINU_D_AQ_RL + 9U, // AMOMINU_D_RL + 9U, // AMOMINU_W + 9U, // AMOMINU_W_AQ + 9U, // AMOMINU_W_AQ_RL + 9U, // AMOMINU_W_RL + 9U, // AMOMIN_D + 9U, // AMOMIN_D_AQ + 9U, // AMOMIN_D_AQ_RL + 9U, // AMOMIN_D_RL + 9U, // AMOMIN_W + 9U, // AMOMIN_W_AQ + 9U, // AMOMIN_W_AQ_RL + 9U, // AMOMIN_W_RL + 9U, // AMOOR_D + 9U, // AMOOR_D_AQ + 9U, // AMOOR_D_AQ_RL + 9U, // AMOOR_D_RL + 9U, // AMOOR_W + 9U, // AMOOR_W_AQ + 9U, // AMOOR_W_AQ_RL + 9U, // AMOOR_W_RL + 9U, // AMOSWAP_D + 9U, // AMOSWAP_D_AQ + 9U, // AMOSWAP_D_AQ_RL + 9U, // AMOSWAP_D_RL + 9U, // AMOSWAP_W + 9U, // AMOSWAP_W_AQ + 9U, // AMOSWAP_W_AQ_RL + 9U, // AMOSWAP_W_RL + 9U, // AMOXOR_D + 9U, // AMOXOR_D_AQ + 9U, // AMOXOR_D_AQ_RL + 9U, // AMOXOR_D_RL + 9U, // AMOXOR_W + 9U, // AMOXOR_W_AQ + 9U, // AMOXOR_W_AQ_RL + 9U, // AMOXOR_W_RL + 4U, // AND + 4U, // ANDI + 0U, // AUIPC + 4U, // BEQ + 4U, // BGE + 4U, // BGEU + 4U, // BLT + 4U, // BLTU + 4U, // BNE + 2U, // CSRRC + 2U, // CSRRCI + 2U, // CSRRS + 2U, // CSRRSI + 2U, // CSRRW + 2U, // CSRRWI + 0U, // C_ADD + 0U, // C_ADDI + 0U, // C_ADDI16SP + 4U, // C_ADDI4SPN + 0U, // C_ADDIW + 0U, // C_ADDW + 0U, // C_AND + 0U, // C_ANDI + 0U, // C_BEQZ + 0U, // C_BNEZ + 0U, // C_EBREAK + 13U, // C_FLD + 13U, // C_FLDSP + 13U, // C_FLW + 13U, // C_FLWSP + 13U, // C_FSD + 13U, // C_FSDSP + 13U, // C_FSW + 13U, // C_FSWSP + 0U, // C_J + 0U, // C_JAL + 0U, // C_JALR + 0U, // C_JR + 13U, // C_LD + 13U, // C_LDSP + 0U, // C_LI + 0U, // C_LUI + 13U, // C_LW + 13U, // C_LWSP + 0U, // C_MV + 0U, // C_NOP + 0U, // C_OR + 13U, // C_SD + 13U, // C_SDSP + 0U, // C_SLLI + 0U, // C_SRAI + 0U, // C_SRLI + 0U, // C_SUB + 0U, // C_SUBW + 13U, // C_SW + 13U, // C_SWSP + 0U, // C_UNIMP + 0U, // C_XOR + 4U, // DIV + 4U, // DIVU + 4U, // DIVUW + 4U, // DIVW + 0U, // EBREAK + 0U, // ECALL + 36U, // FADD_D + 36U, // FADD_S + 0U, // FCLASS_D + 0U, // FCLASS_S + 20U, // FCVT_D_L + 20U, // FCVT_D_LU + 0U, // FCVT_D_S + 0U, // FCVT_D_W + 0U, // FCVT_D_WU + 20U, // FCVT_LU_D + 20U, // FCVT_LU_S + 20U, // FCVT_L_D + 20U, // FCVT_L_S + 20U, // FCVT_S_D + 20U, // FCVT_S_L + 20U, // FCVT_S_LU + 20U, // FCVT_S_W + 20U, // FCVT_S_WU + 20U, // FCVT_WU_D + 20U, // FCVT_WU_S + 20U, // FCVT_W_D + 20U, // FCVT_W_S + 36U, // FDIV_D + 36U, // FDIV_S + 0U, // FENCE + 0U, // FENCE_I + 0U, // FENCE_TSO + 4U, // FEQ_D + 4U, // FEQ_S + 13U, // FLD + 4U, // FLE_D + 4U, // FLE_S + 4U, // FLT_D + 4U, // FLT_S + 13U, // FLW + 100U, // FMADD_D + 100U, // FMADD_S + 4U, // FMAX_D + 4U, // FMAX_S + 4U, // FMIN_D + 4U, // FMIN_S + 100U, // FMSUB_D + 100U, // FMSUB_S + 36U, // FMUL_D + 36U, // FMUL_S + 0U, // FMV_D_X + 0U, // FMV_W_X + 0U, // FMV_X_D + 0U, // FMV_X_W + 100U, // FNMADD_D + 100U, // FNMADD_S + 100U, // FNMSUB_D + 100U, // FNMSUB_S + 13U, // FSD + 4U, // FSGNJN_D + 4U, // FSGNJN_S + 4U, // FSGNJX_D + 4U, // FSGNJX_S + 4U, // FSGNJ_D + 4U, // FSGNJ_S + 20U, // FSQRT_D + 20U, // FSQRT_S + 36U, // FSUB_D + 36U, // FSUB_S + 13U, // FSW + 0U, // JAL + 4U, // JALR + 13U, // LB + 13U, // LBU + 13U, // LD + 13U, // LH + 13U, // LHU + 0U, // LR_D + 0U, // LR_D_AQ + 0U, // LR_D_AQ_RL + 0U, // LR_D_RL + 0U, // LR_W + 0U, // LR_W_AQ + 0U, // LR_W_AQ_RL + 0U, // LR_W_RL + 0U, // LUI + 13U, // LW + 13U, // LWU + 0U, // MRET + 4U, // MUL + 4U, // MULH + 4U, // MULHSU + 4U, // MULHU + 4U, // MULW + 4U, // OR + 4U, // ORI + 4U, // REM + 4U, // REMU + 4U, // REMUW + 4U, // REMW + 13U, // SB + 9U, // SC_D + 9U, // SC_D_AQ + 9U, // SC_D_AQ_RL + 9U, // SC_D_RL + 9U, // SC_W + 9U, // SC_W_AQ + 9U, // SC_W_AQ_RL + 9U, // SC_W_RL + 13U, // SD + 0U, // SFENCE_VMA + 13U, // SH + 4U, // SLL + 4U, // SLLI + 4U, // SLLIW + 4U, // SLLW + 4U, // SLT + 4U, // SLTI + 4U, // SLTIU + 4U, // SLTU + 4U, // SRA + 4U, // SRAI + 4U, // SRAIW + 4U, // SRAW + 0U, // SRET + 4U, // SRL + 4U, // SRLI + 4U, // SRLIW + 4U, // SRLW + 4U, // SUB + 4U, // SUBW + 13U, // SW + 0U, // UNIMP + 0U, // URET + 0U, // WFI + 4U, // XOR + 4U, // XORI }; // Emit the opcode for the instruction. @@ -1192,13 +3438,13 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16; CS_ASSERT(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 4095)-1); + SStream_concat0(O, AsmStrs + (Bits & 4095) - 1); #endif - // Fragment 0 encoded into 2 bits for 4 unique commands. switch ((Bits >> 12) & 3) { - default: CS_ASSERT(0 && "Invalid command number."); + default: + CS_ASSERT(0 && "Invalid command number."); case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; @@ -1223,10 +3469,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 1 encoded into 2 bits for 3 unique commands. switch ((Bits >> 14) & 3) { - default: CS_ASSERT(0 && "Invalid command number."); + default: + CS_ASSERT(0 && "Invalid command number."); case 0: // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR return; @@ -1244,10 +3490,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 2 encoded into 2 bits for 3 unique commands. switch ((Bits >> 16) & 3) { - default: CS_ASSERT(0 && "Invalid command number."); + default: + CS_ASSERT(0 && "Invalid command number."); case 0: // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP... printOperand(MI, 1, O); @@ -1265,10 +3511,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 3 encoded into 2 bits for 4 unique commands. switch ((Bits >> 18) & 3) { - default: CS_ASSERT(0 && "Invalid command number."); + default: + CS_ASSERT(0 && "Invalid command number."); case 0: // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M... return; @@ -1293,7 +3539,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 4 encoded into 1 bits for 2 unique commands. if ((Bits >> 20) & 1) { // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_... @@ -1304,7 +3549,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) printOperand(MI, 2, O); } - // Fragment 5 encoded into 1 bits for 2 unique commands. if ((Bits >> 21) & 1) { // FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FM... @@ -1314,7 +3558,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) return; } - // Fragment 6 encoded into 1 bits for 2 unique commands. if ((Bits >> 22) & 1) { // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS... @@ -1327,156 +3570,153 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) printFRMArg(MI, 3, O); return; } - } - /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static const char * -getRegisterName(unsigned RegNo, unsigned AltIdx) -{ +static const char *getRegisterName(unsigned RegNo, unsigned AltIdx) { CS_ASSERT(RegNo && RegNo < 97 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrsABIRegAltName[] = { - /* 0 */ 'f', 's', '1', '0', 0, - /* 5 */ 'f', 't', '1', '0', 0, - /* 10 */ 'f', 'a', '0', 0, - /* 14 */ 'f', 's', '0', 0, - /* 18 */ 'f', 't', '0', 0, - /* 22 */ 'f', 's', '1', '1', 0, - /* 27 */ 'f', 't', '1', '1', 0, - /* 32 */ 'f', 'a', '1', 0, - /* 36 */ 'f', 's', '1', 0, - /* 40 */ 'f', 't', '1', 0, - /* 44 */ 'f', 'a', '2', 0, - /* 48 */ 'f', 's', '2', 0, - /* 52 */ 'f', 't', '2', 0, - /* 56 */ 'f', 'a', '3', 0, - /* 60 */ 'f', 's', '3', 0, - /* 64 */ 'f', 't', '3', 0, - /* 68 */ 'f', 'a', '4', 0, - /* 72 */ 'f', 's', '4', 0, - /* 76 */ 'f', 't', '4', 0, - /* 80 */ 'f', 'a', '5', 0, - /* 84 */ 'f', 's', '5', 0, - /* 88 */ 'f', 't', '5', 0, - /* 92 */ 'f', 'a', '6', 0, - /* 96 */ 'f', 's', '6', 0, - /* 100 */ 'f', 't', '6', 0, - /* 104 */ 'f', 'a', '7', 0, - /* 108 */ 'f', 's', '7', 0, - /* 112 */ 'f', 't', '7', 0, - /* 116 */ 'f', 's', '8', 0, - /* 120 */ 'f', 't', '8', 0, - /* 124 */ 'f', 's', '9', 0, - /* 128 */ 'f', 't', '9', 0, - /* 132 */ 'r', 'a', 0, - /* 135 */ 'z', 'e', 'r', 'o', 0, - /* 140 */ 'g', 'p', 0, - /* 143 */ 's', 'p', 0, - /* 146 */ 't', 'p', 0, + /* 0 */ 'f', 's', '1', '0', 0, + /* 5 */ 'f', 't', '1', '0', 0, + /* 10 */ 'f', 'a', '0', 0, + /* 14 */ 'f', 's', '0', 0, + /* 18 */ 'f', 't', '0', 0, + /* 22 */ 'f', 's', '1', '1', 0, + /* 27 */ 'f', 't', '1', '1', 0, + /* 32 */ 'f', 'a', '1', 0, + /* 36 */ 'f', 's', '1', 0, + /* 40 */ 'f', 't', '1', 0, + /* 44 */ 'f', 'a', '2', 0, + /* 48 */ 'f', 's', '2', 0, + /* 52 */ 'f', 't', '2', 0, + /* 56 */ 'f', 'a', '3', 0, + /* 60 */ 'f', 's', '3', 0, + /* 64 */ 'f', 't', '3', 0, + /* 68 */ 'f', 'a', '4', 0, + /* 72 */ 'f', 's', '4', 0, + /* 76 */ 'f', 't', '4', 0, + /* 80 */ 'f', 'a', '5', 0, + /* 84 */ 'f', 's', '5', 0, + /* 88 */ 'f', 't', '5', 0, + /* 92 */ 'f', 'a', '6', 0, + /* 96 */ 'f', 's', '6', 0, + /* 100 */ 'f', 't', '6', 0, + /* 104 */ 'f', 'a', '7', 0, + /* 108 */ 'f', 's', '7', 0, + /* 112 */ 'f', 't', '7', 0, + /* 116 */ 'f', 's', '8', 0, + /* 120 */ 'f', 't', '8', 0, + /* 124 */ 'f', 's', '9', 0, + /* 128 */ 'f', 't', '9', 0, + /* 132 */ 'r', 'a', 0, + /* 135 */ 'z', 'e', 'r', 'o', 0, + /* 140 */ 'g', 'p', 0, + /* 143 */ 's', 'p', 0, + /* 146 */ 't', 'p', 0, }; static const uint8_t RegAsmOffsetABIRegAltName[] = { - 135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, - 69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, - 65, 77, 89, 101, 18, 18, 40, 40, 52, 52, 64, 64, 76, 76, - 88, 88, 100, 100, 112, 112, 14, 14, 36, 36, 10, 10, 32, 32, - 44, 44, 56, 56, 68, 68, 80, 80, 92, 92, 104, 104, 48, 48, - 60, 60, 72, 72, 84, 84, 96, 96, 108, 108, 116, 116, 124, 124, - 0, 0, 22, 22, 120, 120, 128, 128, 5, 5, 27, 27, + 135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, + 69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, + 65, 77, 89, 101, 18, 18, 40, 40, 52, 52, 64, 64, 76, 76, + 88, 88, 100, 100, 112, 112, 14, 14, 36, 36, 10, 10, 32, 32, + 44, 44, 56, 56, 68, 68, 80, 80, 92, 92, 104, 104, 48, 48, + 60, 60, 72, 72, 84, 84, 96, 96, 108, 108, 116, 116, 124, 124, + 0, 0, 22, 22, 120, 120, 128, 128, 5, 5, 27, 27, }; static const char AsmStrsNoRegAltName[] = { - /* 0 */ 'f', '1', '0', 0, - /* 4 */ 'x', '1', '0', 0, - /* 8 */ 'f', '2', '0', 0, - /* 12 */ 'x', '2', '0', 0, - /* 16 */ 'f', '3', '0', 0, - /* 20 */ 'x', '3', '0', 0, - /* 24 */ 'f', '0', 0, - /* 27 */ 'x', '0', 0, - /* 30 */ 'f', '1', '1', 0, - /* 34 */ 'x', '1', '1', 0, - /* 38 */ 'f', '2', '1', 0, - /* 42 */ 'x', '2', '1', 0, - /* 46 */ 'f', '3', '1', 0, - /* 50 */ 'x', '3', '1', 0, - /* 54 */ 'f', '1', 0, - /* 57 */ 'x', '1', 0, - /* 60 */ 'f', '1', '2', 0, - /* 64 */ 'x', '1', '2', 0, - /* 68 */ 'f', '2', '2', 0, - /* 72 */ 'x', '2', '2', 0, - /* 76 */ 'f', '2', 0, - /* 79 */ 'x', '2', 0, - /* 82 */ 'f', '1', '3', 0, - /* 86 */ 'x', '1', '3', 0, - /* 90 */ 'f', '2', '3', 0, - /* 94 */ 'x', '2', '3', 0, - /* 98 */ 'f', '3', 0, - /* 101 */ 'x', '3', 0, - /* 104 */ 'f', '1', '4', 0, - /* 108 */ 'x', '1', '4', 0, - /* 112 */ 'f', '2', '4', 0, - /* 116 */ 'x', '2', '4', 0, - /* 120 */ 'f', '4', 0, - /* 123 */ 'x', '4', 0, - /* 126 */ 'f', '1', '5', 0, - /* 130 */ 'x', '1', '5', 0, - /* 134 */ 'f', '2', '5', 0, - /* 138 */ 'x', '2', '5', 0, - /* 142 */ 'f', '5', 0, - /* 145 */ 'x', '5', 0, - /* 148 */ 'f', '1', '6', 0, - /* 152 */ 'x', '1', '6', 0, - /* 156 */ 'f', '2', '6', 0, - /* 160 */ 'x', '2', '6', 0, - /* 164 */ 'f', '6', 0, - /* 167 */ 'x', '6', 0, - /* 170 */ 'f', '1', '7', 0, - /* 174 */ 'x', '1', '7', 0, - /* 178 */ 'f', '2', '7', 0, - /* 182 */ 'x', '2', '7', 0, - /* 186 */ 'f', '7', 0, - /* 189 */ 'x', '7', 0, - /* 192 */ 'f', '1', '8', 0, - /* 196 */ 'x', '1', '8', 0, - /* 200 */ 'f', '2', '8', 0, - /* 204 */ 'x', '2', '8', 0, - /* 208 */ 'f', '8', 0, - /* 211 */ 'x', '8', 0, - /* 214 */ 'f', '1', '9', 0, - /* 218 */ 'x', '1', '9', 0, - /* 222 */ 'f', '2', '9', 0, - /* 226 */ 'x', '2', '9', 0, - /* 230 */ 'f', '9', 0, - /* 233 */ 'x', '9', 0, + /* 0 */ 'f', '1', '0', 0, + /* 4 */ 'x', '1', '0', 0, + /* 8 */ 'f', '2', '0', 0, + /* 12 */ 'x', '2', '0', 0, + /* 16 */ 'f', '3', '0', 0, + /* 20 */ 'x', '3', '0', 0, + /* 24 */ 'f', '0', 0, + /* 27 */ 'x', '0', 0, + /* 30 */ 'f', '1', '1', 0, + /* 34 */ 'x', '1', '1', 0, + /* 38 */ 'f', '2', '1', 0, + /* 42 */ 'x', '2', '1', 0, + /* 46 */ 'f', '3', '1', 0, + /* 50 */ 'x', '3', '1', 0, + /* 54 */ 'f', '1', 0, + /* 57 */ 'x', '1', 0, + /* 60 */ 'f', '1', '2', 0, + /* 64 */ 'x', '1', '2', 0, + /* 68 */ 'f', '2', '2', 0, + /* 72 */ 'x', '2', '2', 0, + /* 76 */ 'f', '2', 0, + /* 79 */ 'x', '2', 0, + /* 82 */ 'f', '1', '3', 0, + /* 86 */ 'x', '1', '3', 0, + /* 90 */ 'f', '2', '3', 0, + /* 94 */ 'x', '2', '3', 0, + /* 98 */ 'f', '3', 0, + /* 101 */ 'x', '3', 0, + /* 104 */ 'f', '1', '4', 0, + /* 108 */ 'x', '1', '4', 0, + /* 112 */ 'f', '2', '4', 0, + /* 116 */ 'x', '2', '4', 0, + /* 120 */ 'f', '4', 0, + /* 123 */ 'x', '4', 0, + /* 126 */ 'f', '1', '5', 0, + /* 130 */ 'x', '1', '5', 0, + /* 134 */ 'f', '2', '5', 0, + /* 138 */ 'x', '2', '5', 0, + /* 142 */ 'f', '5', 0, + /* 145 */ 'x', '5', 0, + /* 148 */ 'f', '1', '6', 0, + /* 152 */ 'x', '1', '6', 0, + /* 156 */ 'f', '2', '6', 0, + /* 160 */ 'x', '2', '6', 0, + /* 164 */ 'f', '6', 0, + /* 167 */ 'x', '6', 0, + /* 170 */ 'f', '1', '7', 0, + /* 174 */ 'x', '1', '7', 0, + /* 178 */ 'f', '2', '7', 0, + /* 182 */ 'x', '2', '7', 0, + /* 186 */ 'f', '7', 0, + /* 189 */ 'x', '7', 0, + /* 192 */ 'f', '1', '8', 0, + /* 196 */ 'x', '1', '8', 0, + /* 200 */ 'f', '2', '8', 0, + /* 204 */ 'x', '2', '8', 0, + /* 208 */ 'f', '8', 0, + /* 211 */ 'x', '8', 0, + /* 214 */ 'f', '1', '9', 0, + /* 218 */ 'x', '1', '9', 0, + /* 222 */ 'f', '2', '9', 0, + /* 226 */ 'x', '2', '9', 0, + /* 230 */ 'f', '9', 0, + /* 233 */ 'x', '9', 0, }; static const uint8_t RegAsmOffsetNoRegAltName[] = { - 27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, - 108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, - 204, 226, 20, 50, 24, 24, 54, 54, 76, 76, 98, 98, 120, 120, - 142, 142, 164, 164, 186, 186, 208, 208, 230, 230, 0, 0, 30, 30, - 60, 60, 82, 82, 104, 104, 126, 126, 148, 148, 170, 170, 192, 192, - 214, 214, 8, 8, 38, 38, 68, 68, 90, 90, 112, 112, 134, 134, - 156, 156, 178, 178, 200, 200, 222, 222, 16, 16, 46, 46, + 27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, + 108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, + 204, 226, 20, 50, 24, 24, 54, 54, 76, 76, 98, 98, 120, 120, + 142, 142, 164, 164, 186, 186, 208, 208, 230, 230, 0, 0, 30, 30, + 60, 60, 82, 82, 104, 104, 126, 126, 148, 148, 170, 170, 192, 192, + 214, 214, 8, 8, 38, 38, 68, 68, 90, 90, 112, 112, 134, 134, + 156, 156, 178, 178, 200, 200, 222, 222, 16, 16, 46, 46, }; - switch(AltIdx) { - default: CS_ASSERT(0 && "Invalid register alt name index!"); + switch (AltIdx) { + default: + CS_ASSERT(0 && "Invalid register alt name index!"); case RISCV_ABIRegAltName: - CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && - "Invalid alt name index for register!"); - return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]; + CS_ASSERT(*(AsmStrsABIRegAltName + RegAsmOffsetABIRegAltName[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrsABIRegAltName + RegAsmOffsetABIRegAltName[RegNo - 1]; case RISCV_NoRegAltName: - CS_ASSERT(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && - "Invalid alt name index for register!"); - return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; + CS_ASSERT(*(AsmStrsNoRegAltName + RegAsmOffsetNoRegAltName[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrsNoRegAltName + RegAsmOffsetNoRegAltName[RegNo - 1]; } #else return NULL; @@ -1487,11 +3727,10 @@ getRegisterName(unsigned RegNo, unsigned AltIdx) #undef PRINT_ALIAS_INSTR static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, - unsigned PredicateIndex); + unsigned PredicateIndex); -static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) -{ - MCRegisterInfo *MRI = (MCRegisterInfo *) info; +static bool printAliasInstr(MCInst *MI, SStream *OS, void *info) { + MCRegisterInfo *MRI = (MCRegisterInfo *)info; const char *AsmString; unsigned I = 0; #define ASMSTRING_CONTAIN_SIZE 64 @@ -1499,7 +3738,8 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) char tmpString_[ASMSTRING_CONTAIN_SIZE]; char *tmpString = tmpString_; switch (MCInst_getOpcode(MI)) { - default: return false; + default: + return false; case RISCV_ADDI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && @@ -1512,9 +3752,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (ADDI GPR:$rd, GPR:$rs, 0) @@ -1525,9 +3769,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_ADDIW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (ADDIW GPR:$rd, GPR:$rs, 0) @@ -1538,7 +3786,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_BEQ: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BEQ GPR:$rs, X0, simm13_lsb0:$offset) @@ -1550,7 +3800,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BGE X0, GPR:$rs, simm13_lsb0:$offset) AsmString = "blez $\x02, $\x03"; @@ -1558,7 +3810,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BGE GPR:$rs, X0, simm13_lsb0:$offset) @@ -1569,7 +3823,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_BLT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BLT GPR:$rs, X0, simm13_lsb0:$offset) @@ -1579,7 +3835,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BLT X0, GPR:$rs, simm13_lsb0:$offset) AsmString = "bgtz $\x02, $\x03"; @@ -1589,7 +3847,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_BNE: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BNE GPR:$rs, X0, simm13_lsb0:$offset) @@ -1601,7 +3861,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRC X0, csr_sysreg:$csr, GPR:$rs) AsmString = "csrc $\xFF\x02\x01, $\x03"; break; @@ -1618,7 +3880,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_CSRRS: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { @@ -1628,7 +3892,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { @@ -1638,7 +3904,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { @@ -1648,7 +3916,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3074 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { @@ -1658,7 +3928,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3072 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { @@ -1668,7 +3940,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3073 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { @@ -1678,7 +3952,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3202 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { @@ -1688,7 +3964,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3200 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { @@ -1698,7 +3976,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3201 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { @@ -1708,7 +3988,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, csr_sysreg:$csr, X0) AsmString = "csrr $\x01, $\xFF\x02\x01"; @@ -1717,7 +3999,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRS X0, csr_sysreg:$csr, GPR:$rs) AsmString = "csrs $\xFF\x02\x01, $\x03"; break; @@ -1737,7 +4021,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW X0, 3, GPR:$rs) AsmString = "fscsr $\x03"; break; @@ -1747,7 +4033,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW X0, 2, GPR:$rs) AsmString = "fsrm $\x03"; break; @@ -1757,7 +4045,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW X0, 1, GPR:$rs) AsmString = "fsflags $\x03"; break; @@ -1765,40 +4055,54 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW X0, csr_sysreg:$csr, GPR:$rs) AsmString = "csrw $\xFF\x02\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW GPR:$rd, 3, GPR:$rs) AsmString = "fscsr $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW GPR:$rd, 2, GPR:$rs) AsmString = "fsrm $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW GPR:$rd, 1, GPR:$rs) AsmString = "fsflags $\x01, $\x03"; break; @@ -1829,7 +4133,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { // (CSRRWI GPR:$rd, 2, uimm5:$imm) @@ -1838,7 +4144,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (CSRRWI GPR:$rd, 1, uimm5:$imm) @@ -1849,11 +4157,17 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FADD_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) @@ -1864,11 +4178,17 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FADD_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) @@ -1879,9 +4199,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_D_L: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) @@ -1892,9 +4216,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_D_LU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) @@ -1905,9 +4233,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_LU_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) @@ -1918,9 +4250,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_LU_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) @@ -1931,9 +4267,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_L_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) @@ -1944,9 +4284,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_L_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) @@ -1957,9 +4301,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_S_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 }) @@ -1970,9 +4318,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_S_L: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) @@ -1983,9 +4335,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_S_LU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) @@ -1996,9 +4352,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_S_W: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) @@ -2009,9 +4369,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_S_WU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) @@ -2022,9 +4386,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_WU_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) @@ -2035,9 +4403,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_WU_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) @@ -2048,9 +4420,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_W_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) @@ -2061,9 +4437,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FCVT_W_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) @@ -2074,11 +4454,17 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FDIV_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) @@ -2089,11 +4475,17 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FDIV_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) @@ -2115,13 +4507,21 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FMADD_D: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) @@ -2132,13 +4532,21 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FMADD_S: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) @@ -2149,13 +4557,21 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FMSUB_D: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) @@ -2166,13 +4582,21 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FMSUB_S: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) @@ -2183,11 +4607,17 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FMUL_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) @@ -2198,11 +4628,17 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FMUL_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) @@ -2213,13 +4649,21 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FNMADD_D: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) @@ -2230,13 +4674,21 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FNMADD_S: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) @@ -2247,13 +4699,21 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FNMSUB_D: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) @@ -2264,13 +4724,21 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FNMSUB_S: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) @@ -2281,11 +4749,16 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSGNJN_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs) AsmString = "fneg.d $\x01, $\x02"; break; @@ -2294,11 +4767,16 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSGNJN_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs) AsmString = "fneg.s $\x01, $\x02"; break; @@ -2307,11 +4785,16 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSGNJX_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs) AsmString = "fabs.d $\x01, $\x02"; break; @@ -2320,11 +4803,16 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSGNJX_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs) AsmString = "fabs.s $\x01, $\x02"; break; @@ -2333,11 +4821,16 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSGNJ_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs) AsmString = "fmv.d $\x01, $\x02"; break; @@ -2346,11 +4839,16 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSGNJ_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { + MCOperand_getReg(MCInst_getOperand(MI, 2)) == + MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs) AsmString = "fmv.s $\x01, $\x02"; break; @@ -2359,9 +4857,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSQRT_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 }) @@ -2372,9 +4874,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSQRT_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 }) @@ -2385,11 +4891,17 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSUB_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) @@ -2400,11 +4912,17 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_FSUB_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) @@ -2441,7 +4959,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (JALR X0, GPR:$rs, 0) @@ -2451,7 +4971,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (JALR X1, GPR:$rs, 0) @@ -2469,7 +4991,9 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { // (SFENCE_VMA GPR:$rs, X0) AsmString = "sfence.vma $\x01"; @@ -2479,9 +5003,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_SLT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (SLT GPR:$rd, GPR:$rs, X0) AsmString = "sltz $\x01, $\x02"; @@ -2489,10 +5017,14 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (SLT GPR:$rd, X0, GPR:$rs) AsmString = "sgtz $\x01, $\x03"; break; @@ -2501,9 +5033,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_SLTIU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (SLTIU GPR:$rd, GPR:$rs, 1) @@ -2514,10 +5050,14 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_SLTU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (SLTU GPR:$rd, X0, GPR:$rs) AsmString = "snez $\x01, $\x03"; break; @@ -2526,10 +5066,14 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_SUB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (SUB GPR:$rd, X0, GPR:$rs) AsmString = "neg $\x01, $\x03"; break; @@ -2538,10 +5082,14 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_SUBW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (SUBW GPR:$rd, X0, GPR:$rs) AsmString = "negw $\x01, $\x03"; break; @@ -2550,9 +5098,13 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) case RISCV_XORI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && + MCRegisterClass_contains( + MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), + MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) { // (XORI GPR:$rd, GPR:$rs, -1) @@ -2568,8 +5120,8 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) else tmpString = memcpy(tmpString, AsmString, 1 + AsmStringLen); - while (AsmString[I] != ' ' && AsmString[I] != '\t' && - AsmString[I] != '$' && AsmString[I] != '\0') + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') ++I; tmpString[I] = 0; SStream_concat0(OS, tmpString); @@ -2602,10 +5154,8 @@ static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) return true; } -static void printCustomAliasOperand( - MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - SStream *OS) { +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { switch (PrintMethodIdx) { default: CS_ASSERT(0 && "Unknown PrintMethod kind"); @@ -2617,7 +5167,7 @@ static void printCustomAliasOperand( } static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, - unsigned PredicateIndex) { + unsigned PredicateIndex) { // TODO: need some constant untils operate the MCOperand, // but current CAPSTONE does't have. // So, We just return true diff --git a/arch/RISCV/RISCVGenDisassemblerTables.inc b/arch/RISCV/RISCVGenDisassemblerTables.inc index 101728d30f..8d53cee7d9 100644 --- a/arch/RISCV/RISCVGenDisassemblerTables.inc +++ b/arch/RISCV/RISCVGenDisassemblerTables.inc @@ -1,1776 +1,98918 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * RISCV Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Phosphorus15 , Year 2021 */ +/* This generator is under https://github.com/rizinorg/llvm-capstone */ +/* Automatically generated file, do not edit! */ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#include "../../MCInst.h" #include "../../LEB128.h" -#include "../../cs_priv.h" - -// Helper functions for extracting fields from encoded instructions. -// InsnType must either be integral or an APInt-like object that must: -// * Have a static const max_size_in_bits equal to the number of bits in the -// encoding. -// * be default-constructible and copy-constructible -// * be constructible from a uint64_t -// * be constructible from an APInt (this can be private) -// * Support getBitsSet(loBit, hiBit) -// * be convertible to uint64_t -// * Support the ~, &, ==, !=, and |= operators with other objects of the same type -// * Support shift (<<, >>) with signed and unsigned integers on the RHS -// * Support put (<<) to raw_ostream& -#define FieldFromInstruction(fname, InsnType) \ -static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ -{ \ - InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ - fieldMask = (InsnType)(-1LL); \ - else \ - fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ - return (insn & fieldMask) >> startBit; \ -} +#include "../../MCInst.h" + +#define RISCV_Feature64Bit 0ULL +#define RISCV_FeatureNoRVCHints 1ULL +#define RISCV_FeatureRV32E 2ULL +#define RISCV_FeatureRelax 3ULL +#define RISCV_FeatureReserveX1 4ULL +#define RISCV_FeatureReserveX2 5ULL +#define RISCV_FeatureReserveX3 6ULL +#define RISCV_FeatureReserveX4 7ULL +#define RISCV_FeatureReserveX5 8ULL +#define RISCV_FeatureReserveX6 9ULL +#define RISCV_FeatureReserveX7 10ULL +#define RISCV_FeatureReserveX8 11ULL +#define RISCV_FeatureReserveX9 12ULL +#define RISCV_FeatureReserveX10 13ULL +#define RISCV_FeatureReserveX11 14ULL +#define RISCV_FeatureReserveX12 15ULL +#define RISCV_FeatureReserveX13 16ULL +#define RISCV_FeatureReserveX14 17ULL +#define RISCV_FeatureReserveX15 18ULL +#define RISCV_FeatureReserveX16 19ULL +#define RISCV_FeatureReserveX17 20ULL +#define RISCV_FeatureReserveX18 21ULL +#define RISCV_FeatureReserveX19 22ULL +#define RISCV_FeatureReserveX20 23ULL +#define RISCV_FeatureReserveX21 24ULL +#define RISCV_FeatureReserveX22 25ULL +#define RISCV_FeatureReserveX23 26ULL +#define RISCV_FeatureReserveX24 27ULL +#define RISCV_FeatureReserveX25 28ULL +#define RISCV_FeatureReserveX26 29ULL +#define RISCV_FeatureReserveX27 30ULL +#define RISCV_FeatureReserveX28 31ULL +#define RISCV_FeatureReserveX29 32ULL +#define RISCV_FeatureReserveX30 33ULL +#define RISCV_FeatureReserveX31 34ULL +#define RISCV_FeatureSaveRestore 35ULL +#define RISCV_FeatureStdExtA 36ULL +#define RISCV_FeatureStdExtC 37ULL +#define RISCV_FeatureStdExtD 38ULL +#define RISCV_FeatureStdExtF 39ULL +#define RISCV_FeatureStdExtM 40ULL +#define RISCV_FeatureStdExtV 41ULL +#define RISCV_FeatureStdExtZba 42ULL +#define RISCV_FeatureStdExtZbb 43ULL +#define RISCV_FeatureStdExtZbc 44ULL +#define RISCV_FeatureStdExtZbe 45ULL +#define RISCV_FeatureStdExtZbf 46ULL +#define RISCV_FeatureStdExtZbm 47ULL +#define RISCV_FeatureStdExtZbp 48ULL +#define RISCV_FeatureStdExtZbr 49ULL +#define RISCV_FeatureStdExtZbs 50ULL +#define RISCV_FeatureStdExtZbt 51ULL +#define RISCV_FeatureStdExtZfh 52ULL +#define RISCV_FeatureStdExtZfhmin 53ULL +#define RISCV_FeatureStdExtZvamo 54ULL +#define RISCV_FeatureStdExtZvlsseg 55ULL +#ifdef MIPS_GET_DISASSEMBLER +#undef MIPS_GET_DISASSEMBLER + +// Helper function for extracting fields from encoded instructions. +#define FieldFromInstruction(fname, InsnType) \ + static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ + } static const uint8_t DecoderTable16[] = { -/* 0 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 85 -/* 8 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 11 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 41 -/* 16 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 32 -/* 21 */ MCD_OPC_CheckField, 2, 11, 0, 4, 0, 0, // Skip to: 32 -/* 28 */ MCD_OPC_Decode, 182, 2, 0, // Opcode: C_UNIMP -/* 32 */ MCD_OPC_CheckPredicate, 0, 116, 2, 0, // Skip to: 665 -/* 37 */ MCD_OPC_Decode, 144, 2, 1, // Opcode: C_ADDI4SPN -/* 41 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 71 -/* 46 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 62 -/* 51 */ MCD_OPC_CheckField, 7, 6, 0, 4, 0, 0, // Skip to: 62 -/* 58 */ MCD_OPC_Decode, 171, 2, 0, // Opcode: C_NOP -/* 62 */ MCD_OPC_CheckPredicate, 0, 86, 2, 0, // Skip to: 665 -/* 67 */ MCD_OPC_Decode, 142, 2, 2, // Opcode: C_ADDI -/* 71 */ MCD_OPC_FilterValue, 2, 77, 2, 0, // Skip to: 665 -/* 76 */ MCD_OPC_CheckPredicate, 0, 72, 2, 0, // Skip to: 665 -/* 81 */ MCD_OPC_Decode, 175, 2, 3, // Opcode: C_SLLI -/* 85 */ MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 135 -/* 90 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 93 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 107 -/* 98 */ MCD_OPC_CheckPredicate, 1, 50, 2, 0, // Skip to: 665 -/* 103 */ MCD_OPC_Decode, 152, 2, 4, // Opcode: C_FLD -/* 107 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 121 -/* 112 */ MCD_OPC_CheckPredicate, 2, 36, 2, 0, // Skip to: 665 -/* 117 */ MCD_OPC_Decode, 145, 2, 2, // Opcode: C_ADDIW -/* 121 */ MCD_OPC_FilterValue, 2, 27, 2, 0, // Skip to: 665 -/* 126 */ MCD_OPC_CheckPredicate, 1, 22, 2, 0, // Skip to: 665 -/* 131 */ MCD_OPC_Decode, 153, 2, 5, // Opcode: C_FLDSP -/* 135 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 185 -/* 140 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 143 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 157 -/* 148 */ MCD_OPC_CheckPredicate, 0, 0, 2, 0, // Skip to: 665 -/* 153 */ MCD_OPC_Decode, 168, 2, 6, // Opcode: C_LW -/* 157 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 171 -/* 162 */ MCD_OPC_CheckPredicate, 0, 242, 1, 0, // Skip to: 665 -/* 167 */ MCD_OPC_Decode, 166, 2, 7, // Opcode: C_LI -/* 171 */ MCD_OPC_FilterValue, 2, 233, 1, 0, // Skip to: 665 -/* 176 */ MCD_OPC_CheckPredicate, 0, 228, 1, 0, // Skip to: 665 -/* 181 */ MCD_OPC_Decode, 169, 2, 8, // Opcode: C_LWSP -/* 185 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 251 -/* 190 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 193 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 207 -/* 198 */ MCD_OPC_CheckPredicate, 2, 206, 1, 0, // Skip to: 665 -/* 203 */ MCD_OPC_Decode, 164, 2, 9, // Opcode: C_LD -/* 207 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 237 -/* 212 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 228 -/* 217 */ MCD_OPC_CheckField, 7, 5, 2, 4, 0, 0, // Skip to: 228 -/* 224 */ MCD_OPC_Decode, 143, 2, 10, // Opcode: C_ADDI16SP -/* 228 */ MCD_OPC_CheckPredicate, 0, 176, 1, 0, // Skip to: 665 -/* 233 */ MCD_OPC_Decode, 167, 2, 11, // Opcode: C_LUI -/* 237 */ MCD_OPC_FilterValue, 2, 167, 1, 0, // Skip to: 665 -/* 242 */ MCD_OPC_CheckPredicate, 2, 162, 1, 0, // Skip to: 665 -/* 247 */ MCD_OPC_Decode, 165, 2, 12, // Opcode: C_LDSP -/* 251 */ MCD_OPC_FilterValue, 4, 3, 1, 0, // Skip to: 515 -/* 256 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 259 */ MCD_OPC_FilterValue, 1, 167, 0, 0, // Skip to: 431 -/* 264 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 281 -/* 272 */ MCD_OPC_CheckPredicate, 0, 132, 1, 0, // Skip to: 665 -/* 277 */ MCD_OPC_Decode, 177, 2, 13, // Opcode: C_SRLI -/* 281 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 295 -/* 286 */ MCD_OPC_CheckPredicate, 0, 118, 1, 0, // Skip to: 665 -/* 291 */ MCD_OPC_Decode, 176, 2, 13, // Opcode: C_SRAI -/* 295 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 309 -/* 300 */ MCD_OPC_CheckPredicate, 0, 104, 1, 0, // Skip to: 665 -/* 305 */ MCD_OPC_Decode, 148, 2, 14, // Opcode: C_ANDI -/* 309 */ MCD_OPC_FilterValue, 3, 95, 1, 0, // Skip to: 665 -/* 314 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 317 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 353 -/* 322 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 325 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 339 -/* 330 */ MCD_OPC_CheckPredicate, 0, 74, 1, 0, // Skip to: 665 -/* 335 */ MCD_OPC_Decode, 178, 2, 15, // Opcode: C_SUB -/* 339 */ MCD_OPC_FilterValue, 1, 65, 1, 0, // Skip to: 665 -/* 344 */ MCD_OPC_CheckPredicate, 2, 60, 1, 0, // Skip to: 665 -/* 349 */ MCD_OPC_Decode, 179, 2, 15, // Opcode: C_SUBW -/* 353 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 389 -/* 358 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 361 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 375 -/* 366 */ MCD_OPC_CheckPredicate, 0, 38, 1, 0, // Skip to: 665 -/* 371 */ MCD_OPC_Decode, 183, 2, 15, // Opcode: C_XOR -/* 375 */ MCD_OPC_FilterValue, 1, 29, 1, 0, // Skip to: 665 -/* 380 */ MCD_OPC_CheckPredicate, 2, 24, 1, 0, // Skip to: 665 -/* 385 */ MCD_OPC_Decode, 146, 2, 15, // Opcode: C_ADDW -/* 389 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 410 -/* 394 */ MCD_OPC_CheckPredicate, 0, 10, 1, 0, // Skip to: 665 -/* 399 */ MCD_OPC_CheckField, 12, 1, 0, 3, 1, 0, // Skip to: 665 -/* 406 */ MCD_OPC_Decode, 172, 2, 15, // Opcode: C_OR -/* 410 */ MCD_OPC_FilterValue, 3, 250, 0, 0, // Skip to: 665 -/* 415 */ MCD_OPC_CheckPredicate, 0, 245, 0, 0, // Skip to: 665 -/* 420 */ MCD_OPC_CheckField, 12, 1, 0, 238, 0, 0, // Skip to: 665 -/* 427 */ MCD_OPC_Decode, 147, 2, 15, // Opcode: C_AND -/* 431 */ MCD_OPC_FilterValue, 2, 229, 0, 0, // Skip to: 665 -/* 436 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 439 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 469 -/* 444 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 460 -/* 449 */ MCD_OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 460 -/* 456 */ MCD_OPC_Decode, 163, 2, 16, // Opcode: C_JR -/* 460 */ MCD_OPC_CheckPredicate, 0, 200, 0, 0, // Skip to: 665 -/* 465 */ MCD_OPC_Decode, 170, 2, 17, // Opcode: C_MV -/* 469 */ MCD_OPC_FilterValue, 1, 191, 0, 0, // Skip to: 665 -/* 474 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 490 -/* 479 */ MCD_OPC_CheckField, 2, 10, 0, 4, 0, 0, // Skip to: 490 -/* 486 */ MCD_OPC_Decode, 151, 2, 0, // Opcode: C_EBREAK -/* 490 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 506 -/* 495 */ MCD_OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 506 -/* 502 */ MCD_OPC_Decode, 162, 2, 16, // Opcode: C_JALR -/* 506 */ MCD_OPC_CheckPredicate, 0, 154, 0, 0, // Skip to: 665 -/* 511 */ MCD_OPC_Decode, 141, 2, 18, // Opcode: C_ADD -/* 515 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 565 -/* 520 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 523 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 537 -/* 528 */ MCD_OPC_CheckPredicate, 1, 132, 0, 0, // Skip to: 665 -/* 533 */ MCD_OPC_Decode, 156, 2, 4, // Opcode: C_FSD -/* 537 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 551 -/* 542 */ MCD_OPC_CheckPredicate, 0, 118, 0, 0, // Skip to: 665 -/* 547 */ MCD_OPC_Decode, 160, 2, 19, // Opcode: C_J -/* 551 */ MCD_OPC_FilterValue, 2, 109, 0, 0, // Skip to: 665 -/* 556 */ MCD_OPC_CheckPredicate, 1, 104, 0, 0, // Skip to: 665 -/* 561 */ MCD_OPC_Decode, 157, 2, 20, // Opcode: C_FSDSP -/* 565 */ MCD_OPC_FilterValue, 6, 45, 0, 0, // Skip to: 615 -/* 570 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 573 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 587 -/* 578 */ MCD_OPC_CheckPredicate, 0, 82, 0, 0, // Skip to: 665 -/* 583 */ MCD_OPC_Decode, 180, 2, 6, // Opcode: C_SW -/* 587 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 601 -/* 592 */ MCD_OPC_CheckPredicate, 0, 68, 0, 0, // Skip to: 665 -/* 597 */ MCD_OPC_Decode, 149, 2, 21, // Opcode: C_BEQZ -/* 601 */ MCD_OPC_FilterValue, 2, 59, 0, 0, // Skip to: 665 -/* 606 */ MCD_OPC_CheckPredicate, 0, 54, 0, 0, // Skip to: 665 -/* 611 */ MCD_OPC_Decode, 181, 2, 22, // Opcode: C_SWSP -/* 615 */ MCD_OPC_FilterValue, 7, 45, 0, 0, // Skip to: 665 -/* 620 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 623 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 637 -/* 628 */ MCD_OPC_CheckPredicate, 2, 32, 0, 0, // Skip to: 665 -/* 633 */ MCD_OPC_Decode, 173, 2, 9, // Opcode: C_SD -/* 637 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 651 -/* 642 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 665 -/* 647 */ MCD_OPC_Decode, 150, 2, 21, // Opcode: C_BNEZ -/* 651 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 665 -/* 656 */ MCD_OPC_CheckPredicate, 2, 4, 0, 0, // Skip to: 665 -/* 661 */ MCD_OPC_Decode, 174, 2, 23, // Opcode: C_SDSP -/* 665 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 132, + 0, + 0, // Skip to: 140 + /* 8 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 41 + /* 16 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 32 + /* 21 */ MCD_OPC_CheckField, + 2, + 11, + 0, + 4, + 0, + 0, // Skip to: 32 + /* 28 */ MCD_OPC_Decode, + 216, + 82, + 0, // Opcode: C_UNIMP + /* 32 */ MCD_OPC_CheckPredicate, + 0, + 24, + 3, + 0, // Skip to: 829 + /* 37 */ MCD_OPC_Decode, + 166, + 82, + 1, // Opcode: C_ADDI4SPN + /* 41 */ MCD_OPC_FilterValue, + 1, + 41, + 0, + 0, // Skip to: 87 + /* 46 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 62 + /* 51 */ MCD_OPC_CheckField, + 2, + 11, + 0, + 4, + 0, + 0, // Skip to: 62 + /* 58 */ MCD_OPC_Decode, + 200, + 82, + 0, // Opcode: C_NOP + /* 62 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 78 + /* 67 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 4, + 0, + 0, // Skip to: 78 + /* 74 */ MCD_OPC_Decode, + 201, + 82, + 2, // Opcode: C_NOP_HINT + /* 78 */ MCD_OPC_CheckPredicate, + 0, + 234, + 2, + 0, // Skip to: 829 + /* 83 */ MCD_OPC_Decode, + 164, + 82, + 3, // Opcode: C_ADDI + /* 87 */ MCD_OPC_FilterValue, + 2, + 225, + 2, + 0, // Skip to: 829 + /* 92 */ MCD_OPC_CheckPredicate, + 1, + 18, + 0, + 0, // Skip to: 115 + /* 97 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 11, + 0, + 0, // Skip to: 115 + /* 104 */ MCD_OPC_CheckField, + 2, + 5, + 0, + 4, + 0, + 0, // Skip to: 115 + /* 111 */ MCD_OPC_Decode, + 206, + 82, + 4, // Opcode: C_SLLI64_HINT + /* 115 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 131 + /* 120 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 4, + 0, + 0, // Skip to: 131 + /* 127 */ MCD_OPC_Decode, + 207, + 82, + 5, // Opcode: C_SLLI_HINT + /* 131 */ MCD_OPC_CheckPredicate, + 0, + 181, + 2, + 0, // Skip to: 829 + /* 136 */ MCD_OPC_Decode, + 205, + 82, + 6, // Opcode: C_SLLI + /* 140 */ MCD_OPC_FilterValue, + 1, + 45, + 0, + 0, // Skip to: 190 + /* 145 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 148 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 162 + /* 153 */ MCD_OPC_CheckPredicate, + 2, + 159, + 2, + 0, // Skip to: 829 + /* 158 */ MCD_OPC_Decode, + 178, + 82, + 7, // Opcode: C_FLD + /* 162 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 176 + /* 167 */ MCD_OPC_CheckPredicate, + 3, + 145, + 2, + 0, // Skip to: 829 + /* 172 */ MCD_OPC_Decode, + 167, + 82, + 3, // Opcode: C_ADDIW + /* 176 */ MCD_OPC_FilterValue, + 2, + 136, + 2, + 0, // Skip to: 829 + /* 181 */ MCD_OPC_CheckPredicate, + 2, + 131, + 2, + 0, // Skip to: 829 + /* 186 */ MCD_OPC_Decode, + 179, + 82, + 8, // Opcode: C_FLDSP + /* 190 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 256 + /* 195 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 198 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 212 + /* 203 */ MCD_OPC_CheckPredicate, + 0, + 109, + 2, + 0, // Skip to: 829 + /* 208 */ MCD_OPC_Decode, + 196, + 82, + 9, // Opcode: C_LW + /* 212 */ MCD_OPC_FilterValue, + 1, + 25, + 0, + 0, // Skip to: 242 + /* 217 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 233 + /* 222 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 4, + 0, + 0, // Skip to: 233 + /* 229 */ MCD_OPC_Decode, + 193, + 82, + 10, // Opcode: C_LI_HINT + /* 233 */ MCD_OPC_CheckPredicate, + 0, + 79, + 2, + 0, // Skip to: 829 + /* 238 */ MCD_OPC_Decode, + 192, + 82, + 11, // Opcode: C_LI + /* 242 */ MCD_OPC_FilterValue, + 2, + 70, + 2, + 0, // Skip to: 829 + /* 247 */ MCD_OPC_CheckPredicate, + 0, + 65, + 2, + 0, // Skip to: 829 + /* 252 */ MCD_OPC_Decode, + 197, + 82, + 12, // Opcode: C_LWSP + /* 256 */ MCD_OPC_FilterValue, + 3, + 76, + 0, + 0, // Skip to: 337 + /* 261 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 264 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 278 + /* 269 */ MCD_OPC_CheckPredicate, + 3, + 43, + 2, + 0, // Skip to: 829 + /* 274 */ MCD_OPC_Decode, + 190, + 82, + 13, // Opcode: C_LD + /* 278 */ MCD_OPC_FilterValue, + 1, + 40, + 0, + 0, // Skip to: 323 + /* 283 */ MCD_OPC_ExtractField, + 7, + 5, // Inst{11-7} ... + /* 286 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 300 + /* 291 */ MCD_OPC_CheckPredicate, + 1, + 18, + 0, + 0, // Skip to: 314 + /* 296 */ MCD_OPC_Decode, + 195, + 82, + 10, // Opcode: C_LUI_HINT + /* 300 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 314 + /* 305 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 314 + /* 310 */ MCD_OPC_Decode, + 165, + 82, + 14, // Opcode: C_ADDI16SP + /* 314 */ MCD_OPC_CheckPredicate, + 0, + 254, + 1, + 0, // Skip to: 829 + /* 319 */ MCD_OPC_Decode, + 194, + 82, + 15, // Opcode: C_LUI + /* 323 */ MCD_OPC_FilterValue, + 2, + 245, + 1, + 0, // Skip to: 829 + /* 328 */ MCD_OPC_CheckPredicate, + 3, + 240, + 1, + 0, // Skip to: 829 + /* 333 */ MCD_OPC_Decode, + 191, + 82, + 16, // Opcode: C_LDSP + /* 337 */ MCD_OPC_FilterValue, + 4, + 81, + 1, + 0, // Skip to: 679 + /* 342 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 345 */ MCD_OPC_FilterValue, + 1, + 213, + 0, + 0, // Skip to: 563 + /* 350 */ MCD_OPC_ExtractField, + 10, + 2, // Inst{11-10} ... + /* 353 */ MCD_OPC_FilterValue, + 0, + 32, + 0, + 0, // Skip to: 390 + /* 358 */ MCD_OPC_CheckPredicate, + 1, + 18, + 0, + 0, // Skip to: 381 + /* 363 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 11, + 0, + 0, // Skip to: 381 + /* 370 */ MCD_OPC_CheckField, + 2, + 5, + 0, + 4, + 0, + 0, // Skip to: 381 + /* 377 */ MCD_OPC_Decode, + 211, + 82, + 17, // Opcode: C_SRLI64_HINT + /* 381 */ MCD_OPC_CheckPredicate, + 0, + 187, + 1, + 0, // Skip to: 829 + /* 386 */ MCD_OPC_Decode, + 210, + 82, + 18, // Opcode: C_SRLI + /* 390 */ MCD_OPC_FilterValue, + 1, + 32, + 0, + 0, // Skip to: 427 + /* 395 */ MCD_OPC_CheckPredicate, + 1, + 18, + 0, + 0, // Skip to: 418 + /* 400 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 11, + 0, + 0, // Skip to: 418 + /* 407 */ MCD_OPC_CheckField, + 2, + 5, + 0, + 4, + 0, + 0, // Skip to: 418 + /* 414 */ MCD_OPC_Decode, + 209, + 82, + 17, // Opcode: C_SRAI64_HINT + /* 418 */ MCD_OPC_CheckPredicate, + 0, + 150, + 1, + 0, // Skip to: 829 + /* 423 */ MCD_OPC_Decode, + 208, + 82, + 18, // Opcode: C_SRAI + /* 427 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 441 + /* 432 */ MCD_OPC_CheckPredicate, + 0, + 136, + 1, + 0, // Skip to: 829 + /* 437 */ MCD_OPC_Decode, + 174, + 82, + 19, // Opcode: C_ANDI + /* 441 */ MCD_OPC_FilterValue, + 3, + 127, + 1, + 0, // Skip to: 829 + /* 446 */ MCD_OPC_ExtractField, + 5, + 2, // Inst{6-5} ... + /* 449 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 485 + /* 454 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 457 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 471 + /* 462 */ MCD_OPC_CheckPredicate, + 0, + 106, + 1, + 0, // Skip to: 829 + /* 467 */ MCD_OPC_Decode, + 212, + 82, + 20, // Opcode: C_SUB + /* 471 */ MCD_OPC_FilterValue, + 1, + 97, + 1, + 0, // Skip to: 829 + /* 476 */ MCD_OPC_CheckPredicate, + 3, + 92, + 1, + 0, // Skip to: 829 + /* 481 */ MCD_OPC_Decode, + 213, + 82, + 20, // Opcode: C_SUBW + /* 485 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 521 + /* 490 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 493 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 507 + /* 498 */ MCD_OPC_CheckPredicate, + 0, + 70, + 1, + 0, // Skip to: 829 + /* 503 */ MCD_OPC_Decode, + 217, + 82, + 20, // Opcode: C_XOR + /* 507 */ MCD_OPC_FilterValue, + 1, + 61, + 1, + 0, // Skip to: 829 + /* 512 */ MCD_OPC_CheckPredicate, + 3, + 56, + 1, + 0, // Skip to: 829 + /* 517 */ MCD_OPC_Decode, + 171, + 82, + 20, // Opcode: C_ADDW + /* 521 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 542 + /* 526 */ MCD_OPC_CheckPredicate, + 0, + 42, + 1, + 0, // Skip to: 829 + /* 531 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 35, + 1, + 0, // Skip to: 829 + /* 538 */ MCD_OPC_Decode, + 202, + 82, + 20, // Opcode: C_OR + /* 542 */ MCD_OPC_FilterValue, + 3, + 26, + 1, + 0, // Skip to: 829 + /* 547 */ MCD_OPC_CheckPredicate, + 0, + 21, + 1, + 0, // Skip to: 829 + /* 552 */ MCD_OPC_CheckField, + 12, + 1, + 0, + 14, + 1, + 0, // Skip to: 829 + /* 559 */ MCD_OPC_Decode, + 173, + 82, + 20, // Opcode: C_AND + /* 563 */ MCD_OPC_FilterValue, + 2, + 5, + 1, + 0, // Skip to: 829 + /* 568 */ MCD_OPC_ExtractField, + 12, + 1, // Inst{12} ... + /* 571 */ MCD_OPC_FilterValue, + 0, + 41, + 0, + 0, // Skip to: 617 + /* 576 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 592 + /* 581 */ MCD_OPC_CheckField, + 2, + 5, + 0, + 4, + 0, + 0, // Skip to: 592 + /* 588 */ MCD_OPC_Decode, + 189, + 82, + 21, // Opcode: C_JR + /* 592 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 608 + /* 597 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 4, + 0, + 0, // Skip to: 608 + /* 604 */ MCD_OPC_Decode, + 199, + 82, + 22, // Opcode: C_MV_HINT + /* 608 */ MCD_OPC_CheckPredicate, + 0, + 216, + 0, + 0, // Skip to: 829 + /* 613 */ MCD_OPC_Decode, + 198, + 82, + 23, // Opcode: C_MV + /* 617 */ MCD_OPC_FilterValue, + 1, + 207, + 0, + 0, // Skip to: 829 + /* 622 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 638 + /* 627 */ MCD_OPC_CheckField, + 2, + 10, + 0, + 4, + 0, + 0, // Skip to: 638 + /* 634 */ MCD_OPC_Decode, + 177, + 82, + 0, // Opcode: C_EBREAK + /* 638 */ MCD_OPC_CheckPredicate, + 1, + 11, + 0, + 0, // Skip to: 654 + /* 643 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 4, + 0, + 0, // Skip to: 654 + /* 650 */ MCD_OPC_Decode, + 172, + 82, + 24, // Opcode: C_ADD_HINT + /* 654 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 670 + /* 659 */ MCD_OPC_CheckField, + 2, + 5, + 0, + 4, + 0, + 0, // Skip to: 670 + /* 666 */ MCD_OPC_Decode, + 188, + 82, + 21, // Opcode: C_JALR + /* 670 */ MCD_OPC_CheckPredicate, + 0, + 154, + 0, + 0, // Skip to: 829 + /* 675 */ MCD_OPC_Decode, + 163, + 82, + 25, // Opcode: C_ADD + /* 679 */ MCD_OPC_FilterValue, + 5, + 45, + 0, + 0, // Skip to: 729 + /* 684 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 687 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 701 + /* 692 */ MCD_OPC_CheckPredicate, + 2, + 132, + 0, + 0, // Skip to: 829 + /* 697 */ MCD_OPC_Decode, + 182, + 82, + 7, // Opcode: C_FSD + /* 701 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 715 + /* 706 */ MCD_OPC_CheckPredicate, + 0, + 118, + 0, + 0, // Skip to: 829 + /* 711 */ MCD_OPC_Decode, + 186, + 82, + 26, // Opcode: C_J + /* 715 */ MCD_OPC_FilterValue, + 2, + 109, + 0, + 0, // Skip to: 829 + /* 720 */ MCD_OPC_CheckPredicate, + 2, + 104, + 0, + 0, // Skip to: 829 + /* 725 */ MCD_OPC_Decode, + 183, + 82, + 27, // Opcode: C_FSDSP + /* 729 */ MCD_OPC_FilterValue, + 6, + 45, + 0, + 0, // Skip to: 779 + /* 734 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 737 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 751 + /* 742 */ MCD_OPC_CheckPredicate, + 0, + 82, + 0, + 0, // Skip to: 829 + /* 747 */ MCD_OPC_Decode, + 214, + 82, + 9, // Opcode: C_SW + /* 751 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 765 + /* 756 */ MCD_OPC_CheckPredicate, + 0, + 68, + 0, + 0, // Skip to: 829 + /* 761 */ MCD_OPC_Decode, + 175, + 82, + 28, // Opcode: C_BEQZ + /* 765 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 829 + /* 770 */ MCD_OPC_CheckPredicate, + 0, + 54, + 0, + 0, // Skip to: 829 + /* 775 */ MCD_OPC_Decode, + 215, + 82, + 29, // Opcode: C_SWSP + /* 779 */ MCD_OPC_FilterValue, + 7, + 45, + 0, + 0, // Skip to: 829 + /* 784 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 787 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 801 + /* 792 */ MCD_OPC_CheckPredicate, + 3, + 32, + 0, + 0, // Skip to: 829 + /* 797 */ MCD_OPC_Decode, + 203, + 82, + 13, // Opcode: C_SD + /* 801 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 815 + /* 806 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 829 + /* 811 */ MCD_OPC_Decode, + 176, + 82, + 28, // Opcode: C_BNEZ + /* 815 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 829 + /* 820 */ MCD_OPC_CheckPredicate, + 3, + 4, + 0, + 0, // Skip to: 829 + /* 825 */ MCD_OPC_Decode, + 204, + 82, + 30, // Opcode: C_SDSP + /* 829 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTable32[] = { -/* 0 */ MCD_OPC_ExtractField, 0, 7, // Inst{6-0} ... -/* 3 */ MCD_OPC_FilterValue, 3, 76, 0, 0, // Skip to: 84 -/* 8 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 11 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 20 -/* 16 */ MCD_OPC_Decode, 129, 3, 24, // Opcode: LB -/* 20 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 29 -/* 25 */ MCD_OPC_Decode, 132, 3, 24, // Opcode: LH -/* 29 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 38 -/* 34 */ MCD_OPC_Decode, 143, 3, 24, // Opcode: LW -/* 38 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 52 -/* 43 */ MCD_OPC_CheckPredicate, 3, 55, 15, 0, // Skip to: 3943 -/* 48 */ MCD_OPC_Decode, 131, 3, 24, // Opcode: LD -/* 52 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 61 -/* 57 */ MCD_OPC_Decode, 130, 3, 24, // Opcode: LBU -/* 61 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 70 -/* 66 */ MCD_OPC_Decode, 133, 3, 24, // Opcode: LHU -/* 70 */ MCD_OPC_FilterValue, 6, 28, 15, 0, // Skip to: 3943 -/* 75 */ MCD_OPC_CheckPredicate, 3, 23, 15, 0, // Skip to: 3943 -/* 80 */ MCD_OPC_Decode, 144, 3, 24, // Opcode: LWU -/* 84 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 120 -/* 89 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 92 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 106 -/* 97 */ MCD_OPC_CheckPredicate, 4, 1, 15, 0, // Skip to: 3943 -/* 102 */ MCD_OPC_Decode, 224, 2, 25, // Opcode: FLW -/* 106 */ MCD_OPC_FilterValue, 3, 248, 14, 0, // Skip to: 3943 -/* 111 */ MCD_OPC_CheckPredicate, 5, 243, 14, 0, // Skip to: 3943 -/* 116 */ MCD_OPC_Decode, 219, 2, 26, // Opcode: FLD -/* 120 */ MCD_OPC_FilterValue, 15, 52, 0, 0, // Skip to: 177 -/* 125 */ MCD_OPC_ExtractField, 7, 13, // Inst{19-7} ... -/* 128 */ MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 161 -/* 133 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... -/* 136 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 145 -/* 141 */ MCD_OPC_Decode, 214, 2, 27, // Opcode: FENCE -/* 145 */ MCD_OPC_FilterValue, 8, 209, 14, 0, // Skip to: 3943 -/* 150 */ MCD_OPC_CheckField, 20, 8, 51, 202, 14, 0, // Skip to: 3943 -/* 157 */ MCD_OPC_Decode, 216, 2, 0, // Opcode: FENCE_TSO -/* 161 */ MCD_OPC_FilterValue, 32, 193, 14, 0, // Skip to: 3943 -/* 166 */ MCD_OPC_CheckField, 20, 12, 0, 186, 14, 0, // Skip to: 3943 -/* 173 */ MCD_OPC_Decode, 215, 2, 0, // Opcode: FENCE_I -/* 177 */ MCD_OPC_FilterValue, 19, 99, 0, 0, // Skip to: 281 -/* 182 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 185 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 194 -/* 190 */ MCD_OPC_Decode, 179, 1, 24, // Opcode: ADDI -/* 194 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 210 -/* 199 */ MCD_OPC_CheckField, 26, 6, 0, 153, 14, 0, // Skip to: 3943 -/* 206 */ MCD_OPC_Decode, 170, 3, 28, // Opcode: SLLI -/* 210 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 219 -/* 215 */ MCD_OPC_Decode, 174, 3, 24, // Opcode: SLTI -/* 219 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 228 -/* 224 */ MCD_OPC_Decode, 175, 3, 24, // Opcode: SLTIU -/* 228 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 237 -/* 233 */ MCD_OPC_Decode, 193, 3, 24, // Opcode: XORI -/* 237 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 263 -/* 242 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 245 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 254 -/* 250 */ MCD_OPC_Decode, 183, 3, 28, // Opcode: SRLI -/* 254 */ MCD_OPC_FilterValue, 16, 100, 14, 0, // Skip to: 3943 -/* 259 */ MCD_OPC_Decode, 178, 3, 28, // Opcode: SRAI -/* 263 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 272 -/* 268 */ MCD_OPC_Decode, 152, 3, 24, // Opcode: ORI -/* 272 */ MCD_OPC_FilterValue, 7, 82, 14, 0, // Skip to: 3943 -/* 277 */ MCD_OPC_Decode, 255, 1, 24, // Opcode: ANDI -/* 281 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 290 -/* 286 */ MCD_OPC_Decode, 128, 2, 29, // Opcode: AUIPC -/* 290 */ MCD_OPC_FilterValue, 27, 74, 0, 0, // Skip to: 369 -/* 295 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 298 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 312 -/* 303 */ MCD_OPC_CheckPredicate, 3, 51, 14, 0, // Skip to: 3943 -/* 308 */ MCD_OPC_Decode, 180, 1, 24, // Opcode: ADDIW -/* 312 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 333 -/* 317 */ MCD_OPC_CheckPredicate, 3, 37, 14, 0, // Skip to: 3943 -/* 322 */ MCD_OPC_CheckField, 25, 7, 0, 30, 14, 0, // Skip to: 3943 -/* 329 */ MCD_OPC_Decode, 171, 3, 30, // Opcode: SLLIW -/* 333 */ MCD_OPC_FilterValue, 5, 21, 14, 0, // Skip to: 3943 -/* 338 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 341 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 355 -/* 346 */ MCD_OPC_CheckPredicate, 3, 8, 14, 0, // Skip to: 3943 -/* 351 */ MCD_OPC_Decode, 184, 3, 30, // Opcode: SRLIW -/* 355 */ MCD_OPC_FilterValue, 32, 255, 13, 0, // Skip to: 3943 -/* 360 */ MCD_OPC_CheckPredicate, 3, 250, 13, 0, // Skip to: 3943 -/* 365 */ MCD_OPC_Decode, 179, 3, 30, // Opcode: SRAIW -/* 369 */ MCD_OPC_FilterValue, 35, 44, 0, 0, // Skip to: 418 -/* 374 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 377 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 386 -/* 382 */ MCD_OPC_Decode, 157, 3, 31, // Opcode: SB -/* 386 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 395 -/* 391 */ MCD_OPC_Decode, 168, 3, 31, // Opcode: SH -/* 395 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 404 -/* 400 */ MCD_OPC_Decode, 188, 3, 31, // Opcode: SW -/* 404 */ MCD_OPC_FilterValue, 3, 206, 13, 0, // Skip to: 3943 -/* 409 */ MCD_OPC_CheckPredicate, 3, 201, 13, 0, // Skip to: 3943 -/* 414 */ MCD_OPC_Decode, 166, 3, 31, // Opcode: SD -/* 418 */ MCD_OPC_FilterValue, 39, 31, 0, 0, // Skip to: 454 -/* 423 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 426 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 440 -/* 431 */ MCD_OPC_CheckPredicate, 4, 179, 13, 0, // Skip to: 3943 -/* 436 */ MCD_OPC_Decode, 254, 2, 32, // Opcode: FSW -/* 440 */ MCD_OPC_FilterValue, 3, 170, 13, 0, // Skip to: 3943 -/* 445 */ MCD_OPC_CheckPredicate, 5, 165, 13, 0, // Skip to: 3943 -/* 450 */ MCD_OPC_Decode, 243, 2, 33, // Opcode: FSD -/* 454 */ MCD_OPC_FilterValue, 47, 107, 6, 0, // Skip to: 2102 -/* 459 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 462 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 498 -/* 467 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 470 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 484 -/* 475 */ MCD_OPC_CheckPredicate, 6, 135, 13, 0, // Skip to: 3943 -/* 480 */ MCD_OPC_Decode, 186, 1, 34, // Opcode: AMOADD_W -/* 484 */ MCD_OPC_FilterValue, 3, 126, 13, 0, // Skip to: 3943 -/* 489 */ MCD_OPC_CheckPredicate, 7, 121, 13, 0, // Skip to: 3943 -/* 494 */ MCD_OPC_Decode, 182, 1, 34, // Opcode: AMOADD_D -/* 498 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 534 -/* 503 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 506 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 520 -/* 511 */ MCD_OPC_CheckPredicate, 6, 99, 13, 0, // Skip to: 3943 -/* 516 */ MCD_OPC_Decode, 189, 1, 34, // Opcode: AMOADD_W_RL -/* 520 */ MCD_OPC_FilterValue, 3, 90, 13, 0, // Skip to: 3943 -/* 525 */ MCD_OPC_CheckPredicate, 7, 85, 13, 0, // Skip to: 3943 -/* 530 */ MCD_OPC_Decode, 185, 1, 34, // Opcode: AMOADD_D_RL -/* 534 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 570 -/* 539 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 542 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 556 -/* 547 */ MCD_OPC_CheckPredicate, 6, 63, 13, 0, // Skip to: 3943 -/* 552 */ MCD_OPC_Decode, 187, 1, 34, // Opcode: AMOADD_W_AQ -/* 556 */ MCD_OPC_FilterValue, 3, 54, 13, 0, // Skip to: 3943 -/* 561 */ MCD_OPC_CheckPredicate, 7, 49, 13, 0, // Skip to: 3943 -/* 566 */ MCD_OPC_Decode, 183, 1, 34, // Opcode: AMOADD_D_AQ -/* 570 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 606 -/* 575 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 578 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 592 -/* 583 */ MCD_OPC_CheckPredicate, 6, 27, 13, 0, // Skip to: 3943 -/* 588 */ MCD_OPC_Decode, 188, 1, 34, // Opcode: AMOADD_W_AQ_RL -/* 592 */ MCD_OPC_FilterValue, 3, 18, 13, 0, // Skip to: 3943 -/* 597 */ MCD_OPC_CheckPredicate, 7, 13, 13, 0, // Skip to: 3943 -/* 602 */ MCD_OPC_Decode, 184, 1, 34, // Opcode: AMOADD_D_AQ_RL -/* 606 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 642 -/* 611 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 614 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 628 -/* 619 */ MCD_OPC_CheckPredicate, 6, 247, 12, 0, // Skip to: 3943 -/* 624 */ MCD_OPC_Decode, 242, 1, 34, // Opcode: AMOSWAP_W -/* 628 */ MCD_OPC_FilterValue, 3, 238, 12, 0, // Skip to: 3943 -/* 633 */ MCD_OPC_CheckPredicate, 7, 233, 12, 0, // Skip to: 3943 -/* 638 */ MCD_OPC_Decode, 238, 1, 34, // Opcode: AMOSWAP_D -/* 642 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 678 -/* 647 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 650 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 664 -/* 655 */ MCD_OPC_CheckPredicate, 6, 211, 12, 0, // Skip to: 3943 -/* 660 */ MCD_OPC_Decode, 245, 1, 34, // Opcode: AMOSWAP_W_RL -/* 664 */ MCD_OPC_FilterValue, 3, 202, 12, 0, // Skip to: 3943 -/* 669 */ MCD_OPC_CheckPredicate, 7, 197, 12, 0, // Skip to: 3943 -/* 674 */ MCD_OPC_Decode, 241, 1, 34, // Opcode: AMOSWAP_D_RL -/* 678 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 714 -/* 683 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 686 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 700 -/* 691 */ MCD_OPC_CheckPredicate, 6, 175, 12, 0, // Skip to: 3943 -/* 696 */ MCD_OPC_Decode, 243, 1, 34, // Opcode: AMOSWAP_W_AQ -/* 700 */ MCD_OPC_FilterValue, 3, 166, 12, 0, // Skip to: 3943 -/* 705 */ MCD_OPC_CheckPredicate, 7, 161, 12, 0, // Skip to: 3943 -/* 710 */ MCD_OPC_Decode, 239, 1, 34, // Opcode: AMOSWAP_D_AQ -/* 714 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 750 -/* 719 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 722 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 736 -/* 727 */ MCD_OPC_CheckPredicate, 6, 139, 12, 0, // Skip to: 3943 -/* 732 */ MCD_OPC_Decode, 244, 1, 34, // Opcode: AMOSWAP_W_AQ_RL -/* 736 */ MCD_OPC_FilterValue, 3, 130, 12, 0, // Skip to: 3943 -/* 741 */ MCD_OPC_CheckPredicate, 7, 125, 12, 0, // Skip to: 3943 -/* 746 */ MCD_OPC_Decode, 240, 1, 34, // Opcode: AMOSWAP_D_AQ_RL -/* 750 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 800 -/* 755 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 758 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 779 -/* 763 */ MCD_OPC_CheckPredicate, 6, 103, 12, 0, // Skip to: 3943 -/* 768 */ MCD_OPC_CheckField, 20, 5, 0, 96, 12, 0, // Skip to: 3943 -/* 775 */ MCD_OPC_Decode, 138, 3, 35, // Opcode: LR_W -/* 779 */ MCD_OPC_FilterValue, 3, 87, 12, 0, // Skip to: 3943 -/* 784 */ MCD_OPC_CheckPredicate, 7, 82, 12, 0, // Skip to: 3943 -/* 789 */ MCD_OPC_CheckField, 20, 5, 0, 75, 12, 0, // Skip to: 3943 -/* 796 */ MCD_OPC_Decode, 134, 3, 35, // Opcode: LR_D -/* 800 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 850 -/* 805 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 808 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 829 -/* 813 */ MCD_OPC_CheckPredicate, 6, 53, 12, 0, // Skip to: 3943 -/* 818 */ MCD_OPC_CheckField, 20, 5, 0, 46, 12, 0, // Skip to: 3943 -/* 825 */ MCD_OPC_Decode, 141, 3, 35, // Opcode: LR_W_RL -/* 829 */ MCD_OPC_FilterValue, 3, 37, 12, 0, // Skip to: 3943 -/* 834 */ MCD_OPC_CheckPredicate, 7, 32, 12, 0, // Skip to: 3943 -/* 839 */ MCD_OPC_CheckField, 20, 5, 0, 25, 12, 0, // Skip to: 3943 -/* 846 */ MCD_OPC_Decode, 137, 3, 35, // Opcode: LR_D_RL -/* 850 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 900 -/* 855 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 858 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 879 -/* 863 */ MCD_OPC_CheckPredicate, 6, 3, 12, 0, // Skip to: 3943 -/* 868 */ MCD_OPC_CheckField, 20, 5, 0, 252, 11, 0, // Skip to: 3943 -/* 875 */ MCD_OPC_Decode, 139, 3, 35, // Opcode: LR_W_AQ -/* 879 */ MCD_OPC_FilterValue, 3, 243, 11, 0, // Skip to: 3943 -/* 884 */ MCD_OPC_CheckPredicate, 7, 238, 11, 0, // Skip to: 3943 -/* 889 */ MCD_OPC_CheckField, 20, 5, 0, 231, 11, 0, // Skip to: 3943 -/* 896 */ MCD_OPC_Decode, 135, 3, 35, // Opcode: LR_D_AQ -/* 900 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 950 -/* 905 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 908 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 929 -/* 913 */ MCD_OPC_CheckPredicate, 6, 209, 11, 0, // Skip to: 3943 -/* 918 */ MCD_OPC_CheckField, 20, 5, 0, 202, 11, 0, // Skip to: 3943 -/* 925 */ MCD_OPC_Decode, 140, 3, 35, // Opcode: LR_W_AQ_RL -/* 929 */ MCD_OPC_FilterValue, 3, 193, 11, 0, // Skip to: 3943 -/* 934 */ MCD_OPC_CheckPredicate, 7, 188, 11, 0, // Skip to: 3943 -/* 939 */ MCD_OPC_CheckField, 20, 5, 0, 181, 11, 0, // Skip to: 3943 -/* 946 */ MCD_OPC_Decode, 136, 3, 35, // Opcode: LR_D_AQ_RL -/* 950 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 986 -/* 955 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 958 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 972 -/* 963 */ MCD_OPC_CheckPredicate, 6, 159, 11, 0, // Skip to: 3943 -/* 968 */ MCD_OPC_Decode, 162, 3, 34, // Opcode: SC_W -/* 972 */ MCD_OPC_FilterValue, 3, 150, 11, 0, // Skip to: 3943 -/* 977 */ MCD_OPC_CheckPredicate, 7, 145, 11, 0, // Skip to: 3943 -/* 982 */ MCD_OPC_Decode, 158, 3, 34, // Opcode: SC_D -/* 986 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1022 -/* 991 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 994 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1008 -/* 999 */ MCD_OPC_CheckPredicate, 6, 123, 11, 0, // Skip to: 3943 -/* 1004 */ MCD_OPC_Decode, 165, 3, 34, // Opcode: SC_W_RL -/* 1008 */ MCD_OPC_FilterValue, 3, 114, 11, 0, // Skip to: 3943 -/* 1013 */ MCD_OPC_CheckPredicate, 7, 109, 11, 0, // Skip to: 3943 -/* 1018 */ MCD_OPC_Decode, 161, 3, 34, // Opcode: SC_D_RL -/* 1022 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 1058 -/* 1027 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1030 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1044 -/* 1035 */ MCD_OPC_CheckPredicate, 6, 87, 11, 0, // Skip to: 3943 -/* 1040 */ MCD_OPC_Decode, 163, 3, 34, // Opcode: SC_W_AQ -/* 1044 */ MCD_OPC_FilterValue, 3, 78, 11, 0, // Skip to: 3943 -/* 1049 */ MCD_OPC_CheckPredicate, 7, 73, 11, 0, // Skip to: 3943 -/* 1054 */ MCD_OPC_Decode, 159, 3, 34, // Opcode: SC_D_AQ -/* 1058 */ MCD_OPC_FilterValue, 15, 31, 0, 0, // Skip to: 1094 -/* 1063 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1066 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1080 -/* 1071 */ MCD_OPC_CheckPredicate, 6, 51, 11, 0, // Skip to: 3943 -/* 1076 */ MCD_OPC_Decode, 164, 3, 34, // Opcode: SC_W_AQ_RL -/* 1080 */ MCD_OPC_FilterValue, 3, 42, 11, 0, // Skip to: 3943 -/* 1085 */ MCD_OPC_CheckPredicate, 7, 37, 11, 0, // Skip to: 3943 -/* 1090 */ MCD_OPC_Decode, 160, 3, 34, // Opcode: SC_D_AQ_RL -/* 1094 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 1130 -/* 1099 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1102 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1116 -/* 1107 */ MCD_OPC_CheckPredicate, 6, 15, 11, 0, // Skip to: 3943 -/* 1112 */ MCD_OPC_Decode, 250, 1, 34, // Opcode: AMOXOR_W -/* 1116 */ MCD_OPC_FilterValue, 3, 6, 11, 0, // Skip to: 3943 -/* 1121 */ MCD_OPC_CheckPredicate, 7, 1, 11, 0, // Skip to: 3943 -/* 1126 */ MCD_OPC_Decode, 246, 1, 34, // Opcode: AMOXOR_D -/* 1130 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 1166 -/* 1135 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1138 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1152 -/* 1143 */ MCD_OPC_CheckPredicate, 6, 235, 10, 0, // Skip to: 3943 -/* 1148 */ MCD_OPC_Decode, 253, 1, 34, // Opcode: AMOXOR_W_RL -/* 1152 */ MCD_OPC_FilterValue, 3, 226, 10, 0, // Skip to: 3943 -/* 1157 */ MCD_OPC_CheckPredicate, 7, 221, 10, 0, // Skip to: 3943 -/* 1162 */ MCD_OPC_Decode, 249, 1, 34, // Opcode: AMOXOR_D_RL -/* 1166 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 1202 -/* 1171 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1174 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1188 -/* 1179 */ MCD_OPC_CheckPredicate, 6, 199, 10, 0, // Skip to: 3943 -/* 1184 */ MCD_OPC_Decode, 251, 1, 34, // Opcode: AMOXOR_W_AQ -/* 1188 */ MCD_OPC_FilterValue, 3, 190, 10, 0, // Skip to: 3943 -/* 1193 */ MCD_OPC_CheckPredicate, 7, 185, 10, 0, // Skip to: 3943 -/* 1198 */ MCD_OPC_Decode, 247, 1, 34, // Opcode: AMOXOR_D_AQ -/* 1202 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 1238 -/* 1207 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1210 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1224 -/* 1215 */ MCD_OPC_CheckPredicate, 6, 163, 10, 0, // Skip to: 3943 -/* 1220 */ MCD_OPC_Decode, 252, 1, 34, // Opcode: AMOXOR_W_AQ_RL -/* 1224 */ MCD_OPC_FilterValue, 3, 154, 10, 0, // Skip to: 3943 -/* 1229 */ MCD_OPC_CheckPredicate, 7, 149, 10, 0, // Skip to: 3943 -/* 1234 */ MCD_OPC_Decode, 248, 1, 34, // Opcode: AMOXOR_D_AQ_RL -/* 1238 */ MCD_OPC_FilterValue, 32, 31, 0, 0, // Skip to: 1274 -/* 1243 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1246 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1260 -/* 1251 */ MCD_OPC_CheckPredicate, 6, 127, 10, 0, // Skip to: 3943 -/* 1256 */ MCD_OPC_Decode, 234, 1, 34, // Opcode: AMOOR_W -/* 1260 */ MCD_OPC_FilterValue, 3, 118, 10, 0, // Skip to: 3943 -/* 1265 */ MCD_OPC_CheckPredicate, 7, 113, 10, 0, // Skip to: 3943 -/* 1270 */ MCD_OPC_Decode, 230, 1, 34, // Opcode: AMOOR_D -/* 1274 */ MCD_OPC_FilterValue, 33, 31, 0, 0, // Skip to: 1310 -/* 1279 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1282 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1296 -/* 1287 */ MCD_OPC_CheckPredicate, 6, 91, 10, 0, // Skip to: 3943 -/* 1292 */ MCD_OPC_Decode, 237, 1, 34, // Opcode: AMOOR_W_RL -/* 1296 */ MCD_OPC_FilterValue, 3, 82, 10, 0, // Skip to: 3943 -/* 1301 */ MCD_OPC_CheckPredicate, 7, 77, 10, 0, // Skip to: 3943 -/* 1306 */ MCD_OPC_Decode, 233, 1, 34, // Opcode: AMOOR_D_RL -/* 1310 */ MCD_OPC_FilterValue, 34, 31, 0, 0, // Skip to: 1346 -/* 1315 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1318 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1332 -/* 1323 */ MCD_OPC_CheckPredicate, 6, 55, 10, 0, // Skip to: 3943 -/* 1328 */ MCD_OPC_Decode, 235, 1, 34, // Opcode: AMOOR_W_AQ -/* 1332 */ MCD_OPC_FilterValue, 3, 46, 10, 0, // Skip to: 3943 -/* 1337 */ MCD_OPC_CheckPredicate, 7, 41, 10, 0, // Skip to: 3943 -/* 1342 */ MCD_OPC_Decode, 231, 1, 34, // Opcode: AMOOR_D_AQ -/* 1346 */ MCD_OPC_FilterValue, 35, 31, 0, 0, // Skip to: 1382 -/* 1351 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1354 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1368 -/* 1359 */ MCD_OPC_CheckPredicate, 6, 19, 10, 0, // Skip to: 3943 -/* 1364 */ MCD_OPC_Decode, 236, 1, 34, // Opcode: AMOOR_W_AQ_RL -/* 1368 */ MCD_OPC_FilterValue, 3, 10, 10, 0, // Skip to: 3943 -/* 1373 */ MCD_OPC_CheckPredicate, 7, 5, 10, 0, // Skip to: 3943 -/* 1378 */ MCD_OPC_Decode, 232, 1, 34, // Opcode: AMOOR_D_AQ_RL -/* 1382 */ MCD_OPC_FilterValue, 48, 31, 0, 0, // Skip to: 1418 -/* 1387 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1390 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1404 -/* 1395 */ MCD_OPC_CheckPredicate, 6, 239, 9, 0, // Skip to: 3943 -/* 1400 */ MCD_OPC_Decode, 194, 1, 34, // Opcode: AMOAND_W -/* 1404 */ MCD_OPC_FilterValue, 3, 230, 9, 0, // Skip to: 3943 -/* 1409 */ MCD_OPC_CheckPredicate, 7, 225, 9, 0, // Skip to: 3943 -/* 1414 */ MCD_OPC_Decode, 190, 1, 34, // Opcode: AMOAND_D -/* 1418 */ MCD_OPC_FilterValue, 49, 31, 0, 0, // Skip to: 1454 -/* 1423 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1426 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1440 -/* 1431 */ MCD_OPC_CheckPredicate, 6, 203, 9, 0, // Skip to: 3943 -/* 1436 */ MCD_OPC_Decode, 197, 1, 34, // Opcode: AMOAND_W_RL -/* 1440 */ MCD_OPC_FilterValue, 3, 194, 9, 0, // Skip to: 3943 -/* 1445 */ MCD_OPC_CheckPredicate, 7, 189, 9, 0, // Skip to: 3943 -/* 1450 */ MCD_OPC_Decode, 193, 1, 34, // Opcode: AMOAND_D_RL -/* 1454 */ MCD_OPC_FilterValue, 50, 31, 0, 0, // Skip to: 1490 -/* 1459 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1462 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1476 -/* 1467 */ MCD_OPC_CheckPredicate, 6, 167, 9, 0, // Skip to: 3943 -/* 1472 */ MCD_OPC_Decode, 195, 1, 34, // Opcode: AMOAND_W_AQ -/* 1476 */ MCD_OPC_FilterValue, 3, 158, 9, 0, // Skip to: 3943 -/* 1481 */ MCD_OPC_CheckPredicate, 7, 153, 9, 0, // Skip to: 3943 -/* 1486 */ MCD_OPC_Decode, 191, 1, 34, // Opcode: AMOAND_D_AQ -/* 1490 */ MCD_OPC_FilterValue, 51, 31, 0, 0, // Skip to: 1526 -/* 1495 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1498 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1512 -/* 1503 */ MCD_OPC_CheckPredicate, 6, 131, 9, 0, // Skip to: 3943 -/* 1508 */ MCD_OPC_Decode, 196, 1, 34, // Opcode: AMOAND_W_AQ_RL -/* 1512 */ MCD_OPC_FilterValue, 3, 122, 9, 0, // Skip to: 3943 -/* 1517 */ MCD_OPC_CheckPredicate, 7, 117, 9, 0, // Skip to: 3943 -/* 1522 */ MCD_OPC_Decode, 192, 1, 34, // Opcode: AMOAND_D_AQ_RL -/* 1526 */ MCD_OPC_FilterValue, 64, 31, 0, 0, // Skip to: 1562 -/* 1531 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1534 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1548 -/* 1539 */ MCD_OPC_CheckPredicate, 6, 95, 9, 0, // Skip to: 3943 -/* 1544 */ MCD_OPC_Decode, 226, 1, 34, // Opcode: AMOMIN_W -/* 1548 */ MCD_OPC_FilterValue, 3, 86, 9, 0, // Skip to: 3943 -/* 1553 */ MCD_OPC_CheckPredicate, 7, 81, 9, 0, // Skip to: 3943 -/* 1558 */ MCD_OPC_Decode, 222, 1, 34, // Opcode: AMOMIN_D -/* 1562 */ MCD_OPC_FilterValue, 65, 31, 0, 0, // Skip to: 1598 -/* 1567 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1570 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1584 -/* 1575 */ MCD_OPC_CheckPredicate, 6, 59, 9, 0, // Skip to: 3943 -/* 1580 */ MCD_OPC_Decode, 229, 1, 34, // Opcode: AMOMIN_W_RL -/* 1584 */ MCD_OPC_FilterValue, 3, 50, 9, 0, // Skip to: 3943 -/* 1589 */ MCD_OPC_CheckPredicate, 7, 45, 9, 0, // Skip to: 3943 -/* 1594 */ MCD_OPC_Decode, 225, 1, 34, // Opcode: AMOMIN_D_RL -/* 1598 */ MCD_OPC_FilterValue, 66, 31, 0, 0, // Skip to: 1634 -/* 1603 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1606 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1620 -/* 1611 */ MCD_OPC_CheckPredicate, 6, 23, 9, 0, // Skip to: 3943 -/* 1616 */ MCD_OPC_Decode, 227, 1, 34, // Opcode: AMOMIN_W_AQ -/* 1620 */ MCD_OPC_FilterValue, 3, 14, 9, 0, // Skip to: 3943 -/* 1625 */ MCD_OPC_CheckPredicate, 7, 9, 9, 0, // Skip to: 3943 -/* 1630 */ MCD_OPC_Decode, 223, 1, 34, // Opcode: AMOMIN_D_AQ -/* 1634 */ MCD_OPC_FilterValue, 67, 31, 0, 0, // Skip to: 1670 -/* 1639 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1642 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1656 -/* 1647 */ MCD_OPC_CheckPredicate, 6, 243, 8, 0, // Skip to: 3943 -/* 1652 */ MCD_OPC_Decode, 228, 1, 34, // Opcode: AMOMIN_W_AQ_RL -/* 1656 */ MCD_OPC_FilterValue, 3, 234, 8, 0, // Skip to: 3943 -/* 1661 */ MCD_OPC_CheckPredicate, 7, 229, 8, 0, // Skip to: 3943 -/* 1666 */ MCD_OPC_Decode, 224, 1, 34, // Opcode: AMOMIN_D_AQ_RL -/* 1670 */ MCD_OPC_FilterValue, 80, 31, 0, 0, // Skip to: 1706 -/* 1675 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1678 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1692 -/* 1683 */ MCD_OPC_CheckPredicate, 6, 207, 8, 0, // Skip to: 3943 -/* 1688 */ MCD_OPC_Decode, 210, 1, 34, // Opcode: AMOMAX_W -/* 1692 */ MCD_OPC_FilterValue, 3, 198, 8, 0, // Skip to: 3943 -/* 1697 */ MCD_OPC_CheckPredicate, 7, 193, 8, 0, // Skip to: 3943 -/* 1702 */ MCD_OPC_Decode, 206, 1, 34, // Opcode: AMOMAX_D -/* 1706 */ MCD_OPC_FilterValue, 81, 31, 0, 0, // Skip to: 1742 -/* 1711 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1714 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1728 -/* 1719 */ MCD_OPC_CheckPredicate, 6, 171, 8, 0, // Skip to: 3943 -/* 1724 */ MCD_OPC_Decode, 213, 1, 34, // Opcode: AMOMAX_W_RL -/* 1728 */ MCD_OPC_FilterValue, 3, 162, 8, 0, // Skip to: 3943 -/* 1733 */ MCD_OPC_CheckPredicate, 7, 157, 8, 0, // Skip to: 3943 -/* 1738 */ MCD_OPC_Decode, 209, 1, 34, // Opcode: AMOMAX_D_RL -/* 1742 */ MCD_OPC_FilterValue, 82, 31, 0, 0, // Skip to: 1778 -/* 1747 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1750 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1764 -/* 1755 */ MCD_OPC_CheckPredicate, 6, 135, 8, 0, // Skip to: 3943 -/* 1760 */ MCD_OPC_Decode, 211, 1, 34, // Opcode: AMOMAX_W_AQ -/* 1764 */ MCD_OPC_FilterValue, 3, 126, 8, 0, // Skip to: 3943 -/* 1769 */ MCD_OPC_CheckPredicate, 7, 121, 8, 0, // Skip to: 3943 -/* 1774 */ MCD_OPC_Decode, 207, 1, 34, // Opcode: AMOMAX_D_AQ -/* 1778 */ MCD_OPC_FilterValue, 83, 31, 0, 0, // Skip to: 1814 -/* 1783 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1786 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1800 -/* 1791 */ MCD_OPC_CheckPredicate, 6, 99, 8, 0, // Skip to: 3943 -/* 1796 */ MCD_OPC_Decode, 212, 1, 34, // Opcode: AMOMAX_W_AQ_RL -/* 1800 */ MCD_OPC_FilterValue, 3, 90, 8, 0, // Skip to: 3943 -/* 1805 */ MCD_OPC_CheckPredicate, 7, 85, 8, 0, // Skip to: 3943 -/* 1810 */ MCD_OPC_Decode, 208, 1, 34, // Opcode: AMOMAX_D_AQ_RL -/* 1814 */ MCD_OPC_FilterValue, 96, 31, 0, 0, // Skip to: 1850 -/* 1819 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1822 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1836 -/* 1827 */ MCD_OPC_CheckPredicate, 6, 63, 8, 0, // Skip to: 3943 -/* 1832 */ MCD_OPC_Decode, 218, 1, 34, // Opcode: AMOMINU_W -/* 1836 */ MCD_OPC_FilterValue, 3, 54, 8, 0, // Skip to: 3943 -/* 1841 */ MCD_OPC_CheckPredicate, 7, 49, 8, 0, // Skip to: 3943 -/* 1846 */ MCD_OPC_Decode, 214, 1, 34, // Opcode: AMOMINU_D -/* 1850 */ MCD_OPC_FilterValue, 97, 31, 0, 0, // Skip to: 1886 -/* 1855 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1858 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1872 -/* 1863 */ MCD_OPC_CheckPredicate, 6, 27, 8, 0, // Skip to: 3943 -/* 1868 */ MCD_OPC_Decode, 221, 1, 34, // Opcode: AMOMINU_W_RL -/* 1872 */ MCD_OPC_FilterValue, 3, 18, 8, 0, // Skip to: 3943 -/* 1877 */ MCD_OPC_CheckPredicate, 7, 13, 8, 0, // Skip to: 3943 -/* 1882 */ MCD_OPC_Decode, 217, 1, 34, // Opcode: AMOMINU_D_RL -/* 1886 */ MCD_OPC_FilterValue, 98, 31, 0, 0, // Skip to: 1922 -/* 1891 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1894 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1908 -/* 1899 */ MCD_OPC_CheckPredicate, 6, 247, 7, 0, // Skip to: 3943 -/* 1904 */ MCD_OPC_Decode, 219, 1, 34, // Opcode: AMOMINU_W_AQ -/* 1908 */ MCD_OPC_FilterValue, 3, 238, 7, 0, // Skip to: 3943 -/* 1913 */ MCD_OPC_CheckPredicate, 7, 233, 7, 0, // Skip to: 3943 -/* 1918 */ MCD_OPC_Decode, 215, 1, 34, // Opcode: AMOMINU_D_AQ -/* 1922 */ MCD_OPC_FilterValue, 99, 31, 0, 0, // Skip to: 1958 -/* 1927 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1930 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1944 -/* 1935 */ MCD_OPC_CheckPredicate, 6, 211, 7, 0, // Skip to: 3943 -/* 1940 */ MCD_OPC_Decode, 220, 1, 34, // Opcode: AMOMINU_W_AQ_RL -/* 1944 */ MCD_OPC_FilterValue, 3, 202, 7, 0, // Skip to: 3943 -/* 1949 */ MCD_OPC_CheckPredicate, 7, 197, 7, 0, // Skip to: 3943 -/* 1954 */ MCD_OPC_Decode, 216, 1, 34, // Opcode: AMOMINU_D_AQ_RL -/* 1958 */ MCD_OPC_FilterValue, 112, 31, 0, 0, // Skip to: 1994 -/* 1963 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1966 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1980 -/* 1971 */ MCD_OPC_CheckPredicate, 6, 175, 7, 0, // Skip to: 3943 -/* 1976 */ MCD_OPC_Decode, 202, 1, 34, // Opcode: AMOMAXU_W -/* 1980 */ MCD_OPC_FilterValue, 3, 166, 7, 0, // Skip to: 3943 -/* 1985 */ MCD_OPC_CheckPredicate, 7, 161, 7, 0, // Skip to: 3943 -/* 1990 */ MCD_OPC_Decode, 198, 1, 34, // Opcode: AMOMAXU_D -/* 1994 */ MCD_OPC_FilterValue, 113, 31, 0, 0, // Skip to: 2030 -/* 1999 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2002 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2016 -/* 2007 */ MCD_OPC_CheckPredicate, 6, 139, 7, 0, // Skip to: 3943 -/* 2012 */ MCD_OPC_Decode, 205, 1, 34, // Opcode: AMOMAXU_W_RL -/* 2016 */ MCD_OPC_FilterValue, 3, 130, 7, 0, // Skip to: 3943 -/* 2021 */ MCD_OPC_CheckPredicate, 7, 125, 7, 0, // Skip to: 3943 -/* 2026 */ MCD_OPC_Decode, 201, 1, 34, // Opcode: AMOMAXU_D_RL -/* 2030 */ MCD_OPC_FilterValue, 114, 31, 0, 0, // Skip to: 2066 -/* 2035 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2038 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2052 -/* 2043 */ MCD_OPC_CheckPredicate, 6, 103, 7, 0, // Skip to: 3943 -/* 2048 */ MCD_OPC_Decode, 203, 1, 34, // Opcode: AMOMAXU_W_AQ -/* 2052 */ MCD_OPC_FilterValue, 3, 94, 7, 0, // Skip to: 3943 -/* 2057 */ MCD_OPC_CheckPredicate, 7, 89, 7, 0, // Skip to: 3943 -/* 2062 */ MCD_OPC_Decode, 199, 1, 34, // Opcode: AMOMAXU_D_AQ -/* 2066 */ MCD_OPC_FilterValue, 115, 80, 7, 0, // Skip to: 3943 -/* 2071 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2074 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2088 -/* 2079 */ MCD_OPC_CheckPredicate, 6, 67, 7, 0, // Skip to: 3943 -/* 2084 */ MCD_OPC_Decode, 204, 1, 34, // Opcode: AMOMAXU_W_AQ_RL -/* 2088 */ MCD_OPC_FilterValue, 3, 58, 7, 0, // Skip to: 3943 -/* 2093 */ MCD_OPC_CheckPredicate, 7, 53, 7, 0, // Skip to: 3943 -/* 2098 */ MCD_OPC_Decode, 200, 1, 34, // Opcode: AMOMAXU_D_AQ_RL -/* 2102 */ MCD_OPC_FilterValue, 51, 13, 1, 0, // Skip to: 2376 -/* 2107 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2110 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2150 -/* 2115 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2118 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2127 -/* 2123 */ MCD_OPC_Decode, 178, 1, 34, // Opcode: ADD -/* 2127 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2141 -/* 2132 */ MCD_OPC_CheckPredicate, 8, 14, 7, 0, // Skip to: 3943 -/* 2137 */ MCD_OPC_Decode, 146, 3, 34, // Opcode: MUL -/* 2141 */ MCD_OPC_FilterValue, 32, 5, 7, 0, // Skip to: 3943 -/* 2146 */ MCD_OPC_Decode, 186, 3, 34, // Opcode: SUB -/* 2150 */ MCD_OPC_FilterValue, 1, 26, 0, 0, // Skip to: 2181 -/* 2155 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2158 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2167 -/* 2163 */ MCD_OPC_Decode, 169, 3, 34, // Opcode: SLL -/* 2167 */ MCD_OPC_FilterValue, 1, 235, 6, 0, // Skip to: 3943 -/* 2172 */ MCD_OPC_CheckPredicate, 8, 230, 6, 0, // Skip to: 3943 -/* 2177 */ MCD_OPC_Decode, 147, 3, 34, // Opcode: MULH -/* 2181 */ MCD_OPC_FilterValue, 2, 26, 0, 0, // Skip to: 2212 -/* 2186 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2189 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2198 -/* 2194 */ MCD_OPC_Decode, 173, 3, 34, // Opcode: SLT -/* 2198 */ MCD_OPC_FilterValue, 1, 204, 6, 0, // Skip to: 3943 -/* 2203 */ MCD_OPC_CheckPredicate, 8, 199, 6, 0, // Skip to: 3943 -/* 2208 */ MCD_OPC_Decode, 148, 3, 34, // Opcode: MULHSU -/* 2212 */ MCD_OPC_FilterValue, 3, 26, 0, 0, // Skip to: 2243 -/* 2217 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2220 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2229 -/* 2225 */ MCD_OPC_Decode, 176, 3, 34, // Opcode: SLTU -/* 2229 */ MCD_OPC_FilterValue, 1, 173, 6, 0, // Skip to: 3943 -/* 2234 */ MCD_OPC_CheckPredicate, 8, 168, 6, 0, // Skip to: 3943 -/* 2239 */ MCD_OPC_Decode, 149, 3, 34, // Opcode: MULHU -/* 2243 */ MCD_OPC_FilterValue, 4, 26, 0, 0, // Skip to: 2274 -/* 2248 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2251 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2260 -/* 2256 */ MCD_OPC_Decode, 192, 3, 34, // Opcode: XOR -/* 2260 */ MCD_OPC_FilterValue, 1, 142, 6, 0, // Skip to: 3943 -/* 2265 */ MCD_OPC_CheckPredicate, 8, 137, 6, 0, // Skip to: 3943 -/* 2270 */ MCD_OPC_Decode, 184, 2, 34, // Opcode: DIV -/* 2274 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 2314 -/* 2279 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2282 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2291 -/* 2287 */ MCD_OPC_Decode, 182, 3, 34, // Opcode: SRL -/* 2291 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2305 -/* 2296 */ MCD_OPC_CheckPredicate, 8, 106, 6, 0, // Skip to: 3943 -/* 2301 */ MCD_OPC_Decode, 185, 2, 34, // Opcode: DIVU -/* 2305 */ MCD_OPC_FilterValue, 32, 97, 6, 0, // Skip to: 3943 -/* 2310 */ MCD_OPC_Decode, 177, 3, 34, // Opcode: SRA -/* 2314 */ MCD_OPC_FilterValue, 6, 26, 0, 0, // Skip to: 2345 -/* 2319 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2322 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2331 -/* 2327 */ MCD_OPC_Decode, 151, 3, 34, // Opcode: OR -/* 2331 */ MCD_OPC_FilterValue, 1, 71, 6, 0, // Skip to: 3943 -/* 2336 */ MCD_OPC_CheckPredicate, 8, 66, 6, 0, // Skip to: 3943 -/* 2341 */ MCD_OPC_Decode, 153, 3, 34, // Opcode: REM -/* 2345 */ MCD_OPC_FilterValue, 7, 57, 6, 0, // Skip to: 3943 -/* 2350 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2353 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2362 -/* 2358 */ MCD_OPC_Decode, 254, 1, 34, // Opcode: AND -/* 2362 */ MCD_OPC_FilterValue, 1, 40, 6, 0, // Skip to: 3943 -/* 2367 */ MCD_OPC_CheckPredicate, 8, 35, 6, 0, // Skip to: 3943 -/* 2372 */ MCD_OPC_Decode, 154, 3, 34, // Opcode: REMU -/* 2376 */ MCD_OPC_FilterValue, 55, 4, 0, 0, // Skip to: 2385 -/* 2381 */ MCD_OPC_Decode, 142, 3, 29, // Opcode: LUI -/* 2385 */ MCD_OPC_FilterValue, 59, 187, 0, 0, // Skip to: 2577 -/* 2390 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2393 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2443 -/* 2398 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2401 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2415 -/* 2406 */ MCD_OPC_CheckPredicate, 3, 252, 5, 0, // Skip to: 3943 -/* 2411 */ MCD_OPC_Decode, 181, 1, 34, // Opcode: ADDW -/* 2415 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2429 -/* 2420 */ MCD_OPC_CheckPredicate, 9, 238, 5, 0, // Skip to: 3943 -/* 2425 */ MCD_OPC_Decode, 150, 3, 34, // Opcode: MULW -/* 2429 */ MCD_OPC_FilterValue, 32, 229, 5, 0, // Skip to: 3943 -/* 2434 */ MCD_OPC_CheckPredicate, 3, 224, 5, 0, // Skip to: 3943 -/* 2439 */ MCD_OPC_Decode, 187, 3, 34, // Opcode: SUBW -/* 2443 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2464 -/* 2448 */ MCD_OPC_CheckPredicate, 3, 210, 5, 0, // Skip to: 3943 -/* 2453 */ MCD_OPC_CheckField, 25, 7, 0, 203, 5, 0, // Skip to: 3943 -/* 2460 */ MCD_OPC_Decode, 172, 3, 34, // Opcode: SLLW -/* 2464 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2485 -/* 2469 */ MCD_OPC_CheckPredicate, 9, 189, 5, 0, // Skip to: 3943 -/* 2474 */ MCD_OPC_CheckField, 25, 7, 1, 182, 5, 0, // Skip to: 3943 -/* 2481 */ MCD_OPC_Decode, 187, 2, 34, // Opcode: DIVW -/* 2485 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 2535 -/* 2490 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2493 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2507 -/* 2498 */ MCD_OPC_CheckPredicate, 3, 160, 5, 0, // Skip to: 3943 -/* 2503 */ MCD_OPC_Decode, 185, 3, 34, // Opcode: SRLW -/* 2507 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2521 -/* 2512 */ MCD_OPC_CheckPredicate, 9, 146, 5, 0, // Skip to: 3943 -/* 2517 */ MCD_OPC_Decode, 186, 2, 34, // Opcode: DIVUW -/* 2521 */ MCD_OPC_FilterValue, 32, 137, 5, 0, // Skip to: 3943 -/* 2526 */ MCD_OPC_CheckPredicate, 3, 132, 5, 0, // Skip to: 3943 -/* 2531 */ MCD_OPC_Decode, 180, 3, 34, // Opcode: SRAW -/* 2535 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2556 -/* 2540 */ MCD_OPC_CheckPredicate, 9, 118, 5, 0, // Skip to: 3943 -/* 2545 */ MCD_OPC_CheckField, 25, 7, 1, 111, 5, 0, // Skip to: 3943 -/* 2552 */ MCD_OPC_Decode, 156, 3, 34, // Opcode: REMW -/* 2556 */ MCD_OPC_FilterValue, 7, 102, 5, 0, // Skip to: 3943 -/* 2561 */ MCD_OPC_CheckPredicate, 9, 97, 5, 0, // Skip to: 3943 -/* 2566 */ MCD_OPC_CheckField, 25, 7, 1, 90, 5, 0, // Skip to: 3943 -/* 2573 */ MCD_OPC_Decode, 155, 3, 34, // Opcode: REMUW -/* 2577 */ MCD_OPC_FilterValue, 67, 31, 0, 0, // Skip to: 2613 -/* 2582 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... -/* 2585 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2599 -/* 2590 */ MCD_OPC_CheckPredicate, 4, 68, 5, 0, // Skip to: 3943 -/* 2595 */ MCD_OPC_Decode, 226, 2, 36, // Opcode: FMADD_S -/* 2599 */ MCD_OPC_FilterValue, 1, 59, 5, 0, // Skip to: 3943 -/* 2604 */ MCD_OPC_CheckPredicate, 5, 54, 5, 0, // Skip to: 3943 -/* 2609 */ MCD_OPC_Decode, 225, 2, 37, // Opcode: FMADD_D -/* 2613 */ MCD_OPC_FilterValue, 71, 31, 0, 0, // Skip to: 2649 -/* 2618 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... -/* 2621 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2635 -/* 2626 */ MCD_OPC_CheckPredicate, 4, 32, 5, 0, // Skip to: 3943 -/* 2631 */ MCD_OPC_Decode, 232, 2, 36, // Opcode: FMSUB_S -/* 2635 */ MCD_OPC_FilterValue, 1, 23, 5, 0, // Skip to: 3943 -/* 2640 */ MCD_OPC_CheckPredicate, 5, 18, 5, 0, // Skip to: 3943 -/* 2645 */ MCD_OPC_Decode, 231, 2, 37, // Opcode: FMSUB_D -/* 2649 */ MCD_OPC_FilterValue, 75, 31, 0, 0, // Skip to: 2685 -/* 2654 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... -/* 2657 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2671 -/* 2662 */ MCD_OPC_CheckPredicate, 4, 252, 4, 0, // Skip to: 3943 -/* 2667 */ MCD_OPC_Decode, 242, 2, 36, // Opcode: FNMSUB_S -/* 2671 */ MCD_OPC_FilterValue, 1, 243, 4, 0, // Skip to: 3943 -/* 2676 */ MCD_OPC_CheckPredicate, 5, 238, 4, 0, // Skip to: 3943 -/* 2681 */ MCD_OPC_Decode, 241, 2, 37, // Opcode: FNMSUB_D -/* 2685 */ MCD_OPC_FilterValue, 79, 31, 0, 0, // Skip to: 2721 -/* 2690 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... -/* 2693 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2707 -/* 2698 */ MCD_OPC_CheckPredicate, 4, 216, 4, 0, // Skip to: 3943 -/* 2703 */ MCD_OPC_Decode, 240, 2, 36, // Opcode: FNMADD_S -/* 2707 */ MCD_OPC_FilterValue, 1, 207, 4, 0, // Skip to: 3943 -/* 2712 */ MCD_OPC_CheckPredicate, 5, 202, 4, 0, // Skip to: 3943 -/* 2717 */ MCD_OPC_Decode, 239, 2, 37, // Opcode: FNMADD_D -/* 2721 */ MCD_OPC_FilterValue, 83, 136, 3, 0, // Skip to: 3630 -/* 2726 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2729 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2743 -/* 2734 */ MCD_OPC_CheckPredicate, 4, 180, 4, 0, // Skip to: 3943 -/* 2739 */ MCD_OPC_Decode, 191, 2, 38, // Opcode: FADD_S -/* 2743 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2757 -/* 2748 */ MCD_OPC_CheckPredicate, 5, 166, 4, 0, // Skip to: 3943 -/* 2753 */ MCD_OPC_Decode, 190, 2, 39, // Opcode: FADD_D -/* 2757 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2771 -/* 2762 */ MCD_OPC_CheckPredicate, 4, 152, 4, 0, // Skip to: 3943 -/* 2767 */ MCD_OPC_Decode, 253, 2, 38, // Opcode: FSUB_S -/* 2771 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2785 -/* 2776 */ MCD_OPC_CheckPredicate, 5, 138, 4, 0, // Skip to: 3943 -/* 2781 */ MCD_OPC_Decode, 252, 2, 39, // Opcode: FSUB_D -/* 2785 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2799 -/* 2790 */ MCD_OPC_CheckPredicate, 4, 124, 4, 0, // Skip to: 3943 -/* 2795 */ MCD_OPC_Decode, 234, 2, 38, // Opcode: FMUL_S -/* 2799 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2813 -/* 2804 */ MCD_OPC_CheckPredicate, 5, 110, 4, 0, // Skip to: 3943 -/* 2809 */ MCD_OPC_Decode, 233, 2, 39, // Opcode: FMUL_D -/* 2813 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2827 -/* 2818 */ MCD_OPC_CheckPredicate, 4, 96, 4, 0, // Skip to: 3943 -/* 2823 */ MCD_OPC_Decode, 213, 2, 38, // Opcode: FDIV_S -/* 2827 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 2841 -/* 2832 */ MCD_OPC_CheckPredicate, 5, 82, 4, 0, // Skip to: 3943 -/* 2837 */ MCD_OPC_Decode, 212, 2, 39, // Opcode: FDIV_D -/* 2841 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 2891 -/* 2846 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2849 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2863 -/* 2854 */ MCD_OPC_CheckPredicate, 4, 60, 4, 0, // Skip to: 3943 -/* 2859 */ MCD_OPC_Decode, 249, 2, 40, // Opcode: FSGNJ_S -/* 2863 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2877 -/* 2868 */ MCD_OPC_CheckPredicate, 4, 46, 4, 0, // Skip to: 3943 -/* 2873 */ MCD_OPC_Decode, 245, 2, 40, // Opcode: FSGNJN_S -/* 2877 */ MCD_OPC_FilterValue, 2, 37, 4, 0, // Skip to: 3943 -/* 2882 */ MCD_OPC_CheckPredicate, 4, 32, 4, 0, // Skip to: 3943 -/* 2887 */ MCD_OPC_Decode, 247, 2, 40, // Opcode: FSGNJX_S -/* 2891 */ MCD_OPC_FilterValue, 17, 45, 0, 0, // Skip to: 2941 -/* 2896 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2899 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2913 -/* 2904 */ MCD_OPC_CheckPredicate, 5, 10, 4, 0, // Skip to: 3943 -/* 2909 */ MCD_OPC_Decode, 248, 2, 41, // Opcode: FSGNJ_D -/* 2913 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2927 -/* 2918 */ MCD_OPC_CheckPredicate, 5, 252, 3, 0, // Skip to: 3943 -/* 2923 */ MCD_OPC_Decode, 244, 2, 41, // Opcode: FSGNJN_D -/* 2927 */ MCD_OPC_FilterValue, 2, 243, 3, 0, // Skip to: 3943 -/* 2932 */ MCD_OPC_CheckPredicate, 5, 238, 3, 0, // Skip to: 3943 -/* 2937 */ MCD_OPC_Decode, 246, 2, 41, // Opcode: FSGNJX_D -/* 2941 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 2977 -/* 2946 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2949 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2963 -/* 2954 */ MCD_OPC_CheckPredicate, 4, 216, 3, 0, // Skip to: 3943 -/* 2959 */ MCD_OPC_Decode, 230, 2, 40, // Opcode: FMIN_S -/* 2963 */ MCD_OPC_FilterValue, 1, 207, 3, 0, // Skip to: 3943 -/* 2968 */ MCD_OPC_CheckPredicate, 4, 202, 3, 0, // Skip to: 3943 -/* 2973 */ MCD_OPC_Decode, 228, 2, 40, // Opcode: FMAX_S -/* 2977 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 3013 -/* 2982 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2985 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2999 -/* 2990 */ MCD_OPC_CheckPredicate, 5, 180, 3, 0, // Skip to: 3943 -/* 2995 */ MCD_OPC_Decode, 229, 2, 41, // Opcode: FMIN_D -/* 2999 */ MCD_OPC_FilterValue, 1, 171, 3, 0, // Skip to: 3943 -/* 3004 */ MCD_OPC_CheckPredicate, 5, 166, 3, 0, // Skip to: 3943 -/* 3009 */ MCD_OPC_Decode, 227, 2, 41, // Opcode: FMAX_D -/* 3013 */ MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 3034 -/* 3018 */ MCD_OPC_CheckPredicate, 5, 152, 3, 0, // Skip to: 3943 -/* 3023 */ MCD_OPC_CheckField, 20, 5, 1, 145, 3, 0, // Skip to: 3943 -/* 3030 */ MCD_OPC_Decode, 203, 2, 42, // Opcode: FCVT_S_D -/* 3034 */ MCD_OPC_FilterValue, 33, 23, 0, 0, // Skip to: 3062 -/* 3039 */ MCD_OPC_CheckPredicate, 5, 131, 3, 0, // Skip to: 3943 -/* 3044 */ MCD_OPC_CheckField, 20, 5, 0, 124, 3, 0, // Skip to: 3943 -/* 3051 */ MCD_OPC_CheckField, 12, 3, 0, 117, 3, 0, // Skip to: 3943 -/* 3058 */ MCD_OPC_Decode, 196, 2, 43, // Opcode: FCVT_D_S -/* 3062 */ MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 3083 -/* 3067 */ MCD_OPC_CheckPredicate, 4, 103, 3, 0, // Skip to: 3943 -/* 3072 */ MCD_OPC_CheckField, 20, 5, 0, 96, 3, 0, // Skip to: 3943 -/* 3079 */ MCD_OPC_Decode, 251, 2, 44, // Opcode: FSQRT_S -/* 3083 */ MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 3104 -/* 3088 */ MCD_OPC_CheckPredicate, 5, 82, 3, 0, // Skip to: 3943 -/* 3093 */ MCD_OPC_CheckField, 20, 5, 0, 75, 3, 0, // Skip to: 3943 -/* 3100 */ MCD_OPC_Decode, 250, 2, 45, // Opcode: FSQRT_D -/* 3104 */ MCD_OPC_FilterValue, 80, 45, 0, 0, // Skip to: 3154 -/* 3109 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3112 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3126 -/* 3117 */ MCD_OPC_CheckPredicate, 4, 53, 3, 0, // Skip to: 3943 -/* 3122 */ MCD_OPC_Decode, 221, 2, 46, // Opcode: FLE_S -/* 3126 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3140 -/* 3131 */ MCD_OPC_CheckPredicate, 4, 39, 3, 0, // Skip to: 3943 -/* 3136 */ MCD_OPC_Decode, 223, 2, 46, // Opcode: FLT_S -/* 3140 */ MCD_OPC_FilterValue, 2, 30, 3, 0, // Skip to: 3943 -/* 3145 */ MCD_OPC_CheckPredicate, 4, 25, 3, 0, // Skip to: 3943 -/* 3150 */ MCD_OPC_Decode, 218, 2, 46, // Opcode: FEQ_S -/* 3154 */ MCD_OPC_FilterValue, 81, 45, 0, 0, // Skip to: 3204 -/* 3159 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3162 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3176 -/* 3167 */ MCD_OPC_CheckPredicate, 5, 3, 3, 0, // Skip to: 3943 -/* 3172 */ MCD_OPC_Decode, 220, 2, 47, // Opcode: FLE_D -/* 3176 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3190 -/* 3181 */ MCD_OPC_CheckPredicate, 5, 245, 2, 0, // Skip to: 3943 -/* 3186 */ MCD_OPC_Decode, 222, 2, 47, // Opcode: FLT_D -/* 3190 */ MCD_OPC_FilterValue, 2, 236, 2, 0, // Skip to: 3943 -/* 3195 */ MCD_OPC_CheckPredicate, 5, 231, 2, 0, // Skip to: 3943 -/* 3200 */ MCD_OPC_Decode, 217, 2, 47, // Opcode: FEQ_D -/* 3204 */ MCD_OPC_FilterValue, 96, 59, 0, 0, // Skip to: 3268 -/* 3209 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 3212 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3226 -/* 3217 */ MCD_OPC_CheckPredicate, 4, 209, 2, 0, // Skip to: 3943 -/* 3222 */ MCD_OPC_Decode, 211, 2, 48, // Opcode: FCVT_W_S -/* 3226 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3240 -/* 3231 */ MCD_OPC_CheckPredicate, 4, 195, 2, 0, // Skip to: 3943 -/* 3236 */ MCD_OPC_Decode, 209, 2, 48, // Opcode: FCVT_WU_S -/* 3240 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3254 -/* 3245 */ MCD_OPC_CheckPredicate, 10, 181, 2, 0, // Skip to: 3943 -/* 3250 */ MCD_OPC_Decode, 202, 2, 48, // Opcode: FCVT_L_S -/* 3254 */ MCD_OPC_FilterValue, 3, 172, 2, 0, // Skip to: 3943 -/* 3259 */ MCD_OPC_CheckPredicate, 10, 167, 2, 0, // Skip to: 3943 -/* 3264 */ MCD_OPC_Decode, 200, 2, 48, // Opcode: FCVT_LU_S -/* 3268 */ MCD_OPC_FilterValue, 97, 59, 0, 0, // Skip to: 3332 -/* 3273 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 3276 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3290 -/* 3281 */ MCD_OPC_CheckPredicate, 5, 145, 2, 0, // Skip to: 3943 -/* 3286 */ MCD_OPC_Decode, 210, 2, 49, // Opcode: FCVT_W_D -/* 3290 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3304 -/* 3295 */ MCD_OPC_CheckPredicate, 5, 131, 2, 0, // Skip to: 3943 -/* 3300 */ MCD_OPC_Decode, 208, 2, 49, // Opcode: FCVT_WU_D -/* 3304 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3318 -/* 3309 */ MCD_OPC_CheckPredicate, 11, 117, 2, 0, // Skip to: 3943 -/* 3314 */ MCD_OPC_Decode, 201, 2, 49, // Opcode: FCVT_L_D -/* 3318 */ MCD_OPC_FilterValue, 3, 108, 2, 0, // Skip to: 3943 -/* 3323 */ MCD_OPC_CheckPredicate, 11, 103, 2, 0, // Skip to: 3943 -/* 3328 */ MCD_OPC_Decode, 199, 2, 49, // Opcode: FCVT_LU_D -/* 3332 */ MCD_OPC_FilterValue, 104, 59, 0, 0, // Skip to: 3396 -/* 3337 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 3340 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3354 -/* 3345 */ MCD_OPC_CheckPredicate, 4, 81, 2, 0, // Skip to: 3943 -/* 3350 */ MCD_OPC_Decode, 206, 2, 50, // Opcode: FCVT_S_W -/* 3354 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3368 -/* 3359 */ MCD_OPC_CheckPredicate, 4, 67, 2, 0, // Skip to: 3943 -/* 3364 */ MCD_OPC_Decode, 207, 2, 50, // Opcode: FCVT_S_WU -/* 3368 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3382 -/* 3373 */ MCD_OPC_CheckPredicate, 10, 53, 2, 0, // Skip to: 3943 -/* 3378 */ MCD_OPC_Decode, 204, 2, 50, // Opcode: FCVT_S_L -/* 3382 */ MCD_OPC_FilterValue, 3, 44, 2, 0, // Skip to: 3943 -/* 3387 */ MCD_OPC_CheckPredicate, 10, 39, 2, 0, // Skip to: 3943 -/* 3392 */ MCD_OPC_Decode, 205, 2, 50, // Opcode: FCVT_S_LU -/* 3396 */ MCD_OPC_FilterValue, 105, 73, 0, 0, // Skip to: 3474 -/* 3401 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 3404 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3425 -/* 3409 */ MCD_OPC_CheckPredicate, 5, 17, 2, 0, // Skip to: 3943 -/* 3414 */ MCD_OPC_CheckField, 12, 3, 0, 10, 2, 0, // Skip to: 3943 -/* 3421 */ MCD_OPC_Decode, 197, 2, 51, // Opcode: FCVT_D_W -/* 3425 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3446 -/* 3430 */ MCD_OPC_CheckPredicate, 5, 252, 1, 0, // Skip to: 3943 -/* 3435 */ MCD_OPC_CheckField, 12, 3, 0, 245, 1, 0, // Skip to: 3943 -/* 3442 */ MCD_OPC_Decode, 198, 2, 51, // Opcode: FCVT_D_WU -/* 3446 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3460 -/* 3451 */ MCD_OPC_CheckPredicate, 11, 231, 1, 0, // Skip to: 3943 -/* 3456 */ MCD_OPC_Decode, 194, 2, 52, // Opcode: FCVT_D_L -/* 3460 */ MCD_OPC_FilterValue, 3, 222, 1, 0, // Skip to: 3943 -/* 3465 */ MCD_OPC_CheckPredicate, 11, 217, 1, 0, // Skip to: 3943 -/* 3470 */ MCD_OPC_Decode, 195, 2, 52, // Opcode: FCVT_D_LU -/* 3474 */ MCD_OPC_FilterValue, 112, 45, 0, 0, // Skip to: 3524 -/* 3479 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3482 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3503 -/* 3487 */ MCD_OPC_CheckPredicate, 4, 195, 1, 0, // Skip to: 3943 -/* 3492 */ MCD_OPC_CheckField, 20, 5, 0, 188, 1, 0, // Skip to: 3943 -/* 3499 */ MCD_OPC_Decode, 238, 2, 53, // Opcode: FMV_X_W -/* 3503 */ MCD_OPC_FilterValue, 1, 179, 1, 0, // Skip to: 3943 -/* 3508 */ MCD_OPC_CheckPredicate, 4, 174, 1, 0, // Skip to: 3943 -/* 3513 */ MCD_OPC_CheckField, 20, 5, 0, 167, 1, 0, // Skip to: 3943 -/* 3520 */ MCD_OPC_Decode, 193, 2, 53, // Opcode: FCLASS_S -/* 3524 */ MCD_OPC_FilterValue, 113, 45, 0, 0, // Skip to: 3574 -/* 3529 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3532 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3553 -/* 3537 */ MCD_OPC_CheckPredicate, 11, 145, 1, 0, // Skip to: 3943 -/* 3542 */ MCD_OPC_CheckField, 20, 5, 0, 138, 1, 0, // Skip to: 3943 -/* 3549 */ MCD_OPC_Decode, 237, 2, 54, // Opcode: FMV_X_D -/* 3553 */ MCD_OPC_FilterValue, 1, 129, 1, 0, // Skip to: 3943 -/* 3558 */ MCD_OPC_CheckPredicate, 5, 124, 1, 0, // Skip to: 3943 -/* 3563 */ MCD_OPC_CheckField, 20, 5, 0, 117, 1, 0, // Skip to: 3943 -/* 3570 */ MCD_OPC_Decode, 192, 2, 54, // Opcode: FCLASS_D -/* 3574 */ MCD_OPC_FilterValue, 120, 23, 0, 0, // Skip to: 3602 -/* 3579 */ MCD_OPC_CheckPredicate, 4, 103, 1, 0, // Skip to: 3943 -/* 3584 */ MCD_OPC_CheckField, 20, 5, 0, 96, 1, 0, // Skip to: 3943 -/* 3591 */ MCD_OPC_CheckField, 12, 3, 0, 89, 1, 0, // Skip to: 3943 -/* 3598 */ MCD_OPC_Decode, 236, 2, 55, // Opcode: FMV_W_X -/* 3602 */ MCD_OPC_FilterValue, 121, 80, 1, 0, // Skip to: 3943 -/* 3607 */ MCD_OPC_CheckPredicate, 11, 75, 1, 0, // Skip to: 3943 -/* 3612 */ MCD_OPC_CheckField, 20, 5, 0, 68, 1, 0, // Skip to: 3943 -/* 3619 */ MCD_OPC_CheckField, 12, 3, 0, 61, 1, 0, // Skip to: 3943 -/* 3626 */ MCD_OPC_Decode, 235, 2, 51, // Opcode: FMV_D_X -/* 3630 */ MCD_OPC_FilterValue, 99, 57, 0, 0, // Skip to: 3692 -/* 3635 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3638 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3647 -/* 3643 */ MCD_OPC_Decode, 129, 2, 56, // Opcode: BEQ -/* 3647 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 3656 -/* 3652 */ MCD_OPC_Decode, 134, 2, 56, // Opcode: BNE -/* 3656 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 3665 -/* 3661 */ MCD_OPC_Decode, 132, 2, 56, // Opcode: BLT -/* 3665 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 3674 -/* 3670 */ MCD_OPC_Decode, 130, 2, 56, // Opcode: BGE -/* 3674 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 3683 -/* 3679 */ MCD_OPC_Decode, 133, 2, 56, // Opcode: BLTU -/* 3683 */ MCD_OPC_FilterValue, 7, 255, 0, 0, // Skip to: 3943 -/* 3688 */ MCD_OPC_Decode, 131, 2, 56, // Opcode: BGEU -/* 3692 */ MCD_OPC_FilterValue, 103, 11, 0, 0, // Skip to: 3708 -/* 3697 */ MCD_OPC_CheckField, 12, 3, 0, 239, 0, 0, // Skip to: 3943 -/* 3704 */ MCD_OPC_Decode, 128, 3, 24, // Opcode: JALR -/* 3708 */ MCD_OPC_FilterValue, 111, 4, 0, 0, // Skip to: 3717 -/* 3713 */ MCD_OPC_Decode, 255, 2, 57, // Opcode: JAL -/* 3717 */ MCD_OPC_FilterValue, 115, 221, 0, 0, // Skip to: 3943 -/* 3722 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3725 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 3869 -/* 3730 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 3733 */ MCD_OPC_FilterValue, 0, 51, 0, 0, // Skip to: 3789 -/* 3738 */ MCD_OPC_ExtractField, 15, 10, // Inst{24-15} ... -/* 3741 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3757 -/* 3746 */ MCD_OPC_CheckField, 7, 5, 0, 190, 0, 0, // Skip to: 3943 -/* 3753 */ MCD_OPC_Decode, 189, 2, 0, // Opcode: ECALL -/* 3757 */ MCD_OPC_FilterValue, 32, 11, 0, 0, // Skip to: 3773 -/* 3762 */ MCD_OPC_CheckField, 7, 5, 0, 174, 0, 0, // Skip to: 3943 -/* 3769 */ MCD_OPC_Decode, 188, 2, 0, // Opcode: EBREAK -/* 3773 */ MCD_OPC_FilterValue, 64, 165, 0, 0, // Skip to: 3943 -/* 3778 */ MCD_OPC_CheckField, 7, 5, 0, 158, 0, 0, // Skip to: 3943 -/* 3785 */ MCD_OPC_Decode, 190, 3, 0, // Opcode: URET -/* 3789 */ MCD_OPC_FilterValue, 8, 36, 0, 0, // Skip to: 3830 -/* 3794 */ MCD_OPC_ExtractField, 15, 10, // Inst{24-15} ... -/* 3797 */ MCD_OPC_FilterValue, 64, 11, 0, 0, // Skip to: 3813 -/* 3802 */ MCD_OPC_CheckField, 7, 5, 0, 134, 0, 0, // Skip to: 3943 -/* 3809 */ MCD_OPC_Decode, 181, 3, 0, // Opcode: SRET -/* 3813 */ MCD_OPC_FilterValue, 160, 1, 124, 0, 0, // Skip to: 3943 -/* 3819 */ MCD_OPC_CheckField, 7, 5, 0, 117, 0, 0, // Skip to: 3943 -/* 3826 */ MCD_OPC_Decode, 191, 3, 0, // Opcode: WFI -/* 3830 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 3846 -/* 3835 */ MCD_OPC_CheckField, 7, 5, 0, 101, 0, 0, // Skip to: 3943 -/* 3842 */ MCD_OPC_Decode, 167, 3, 58, // Opcode: SFENCE_VMA -/* 3846 */ MCD_OPC_FilterValue, 24, 92, 0, 0, // Skip to: 3943 -/* 3851 */ MCD_OPC_CheckField, 15, 10, 64, 85, 0, 0, // Skip to: 3943 -/* 3858 */ MCD_OPC_CheckField, 7, 5, 0, 78, 0, 0, // Skip to: 3943 -/* 3865 */ MCD_OPC_Decode, 145, 3, 0, // Opcode: MRET -/* 3869 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 3898 -/* 3874 */ MCD_OPC_CheckField, 15, 17, 128, 128, 6, 11, 0, 0, // Skip to: 3894 -/* 3883 */ MCD_OPC_CheckField, 7, 5, 0, 4, 0, 0, // Skip to: 3894 -/* 3890 */ MCD_OPC_Decode, 189, 3, 0, // Opcode: UNIMP -/* 3894 */ MCD_OPC_Decode, 139, 2, 59, // Opcode: CSRRW -/* 3898 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 3907 -/* 3903 */ MCD_OPC_Decode, 137, 2, 59, // Opcode: CSRRS -/* 3907 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 3916 -/* 3912 */ MCD_OPC_Decode, 135, 2, 59, // Opcode: CSRRC -/* 3916 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 3925 -/* 3921 */ MCD_OPC_Decode, 140, 2, 60, // Opcode: CSRRWI -/* 3925 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 3934 -/* 3930 */ MCD_OPC_Decode, 138, 2, 60, // Opcode: CSRRSI -/* 3934 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 3943 -/* 3939 */ MCD_OPC_Decode, 136, 2, 60, // Opcode: CSRRCI -/* 3943 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 0, + 7, // Inst{6-0} ... + /* 3 */ MCD_OPC_FilterValue, + 3, + 76, + 0, + 0, // Skip to: 84 + /* 8 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 20 + /* 16 */ MCD_OPC_Decode, + 220, + 83, + 31, // Opcode: LB + /* 20 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 29 + /* 25 */ MCD_OPC_Decode, + 223, + 83, + 31, // Opcode: LH + /* 29 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 38 + /* 34 */ MCD_OPC_Decode, + 234, + 83, + 31, // Opcode: LW + /* 38 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 52 + /* 43 */ MCD_OPC_CheckPredicate, + 4, + 145, + 65, + 0, // Skip to: 16833 + /* 48 */ MCD_OPC_Decode, + 222, + 83, + 31, // Opcode: LD + /* 52 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 61 + /* 57 */ MCD_OPC_Decode, + 221, + 83, + 31, // Opcode: LBU + /* 61 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 70 + /* 66 */ MCD_OPC_Decode, + 224, + 83, + 31, // Opcode: LHU + /* 70 */ MCD_OPC_FilterValue, + 6, + 118, + 65, + 0, // Skip to: 16833 + /* 75 */ MCD_OPC_CheckPredicate, + 4, + 113, + 65, + 0, // Skip to: 16833 + /* 80 */ MCD_OPC_Decode, + 235, + 83, + 31, // Opcode: LWU + /* 84 */ MCD_OPC_FilterValue, + 7, + 114, + 11, + 0, // Skip to: 3019 + /* 89 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 92 */ MCD_OPC_FilterValue, + 0, + 220, + 2, + 0, // Skip to: 829 + /* 97 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 100 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 178 + /* 105 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 108 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 122 + /* 113 */ MCD_OPC_CheckPredicate, + 5, + 75, + 65, + 0, // Skip to: 16833 + /* 118 */ MCD_OPC_Decode, + 144, + 86, + 32, // Opcode: VLE8_V + /* 122 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 143 + /* 127 */ MCD_OPC_CheckPredicate, + 5, + 61, + 65, + 0, // Skip to: 16833 + /* 132 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 54, + 65, + 0, // Skip to: 16833 + /* 139 */ MCD_OPC_Decode, + 252, + 85, + 33, // Opcode: VL1RE8_V + /* 143 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 164 + /* 148 */ MCD_OPC_CheckPredicate, + 5, + 40, + 65, + 0, // Skip to: 16833 + /* 153 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 33, + 65, + 0, // Skip to: 16833 + /* 160 */ MCD_OPC_Decode, + 145, + 86, + 33, // Opcode: VLM_V + /* 164 */ MCD_OPC_FilterValue, + 16, + 24, + 65, + 0, // Skip to: 16833 + /* 169 */ MCD_OPC_CheckPredicate, + 5, + 19, + 65, + 0, // Skip to: 16833 + /* 174 */ MCD_OPC_Decode, + 143, + 86, + 32, // Opcode: VLE8FF_V + /* 178 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 192 + /* 183 */ MCD_OPC_CheckPredicate, + 5, + 5, + 65, + 0, // Skip to: 16833 + /* 188 */ MCD_OPC_Decode, + 141, + 87, + 34, // Opcode: VLUXEI8_V + /* 192 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 206 + /* 197 */ MCD_OPC_CheckPredicate, + 5, + 247, + 64, + 0, // Skip to: 16833 + /* 202 */ MCD_OPC_Decode, + 181, + 86, + 35, // Opcode: VLSE8_V + /* 206 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 220 + /* 211 */ MCD_OPC_CheckPredicate, + 5, + 233, + 64, + 0, // Skip to: 16833 + /* 216 */ MCD_OPC_Decode, + 149, + 86, + 34, // Opcode: VLOXEI8_V + /* 220 */ MCD_OPC_FilterValue, + 8, + 52, + 0, + 0, // Skip to: 277 + /* 225 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 228 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 242 + /* 233 */ MCD_OPC_CheckPredicate, + 6, + 211, + 64, + 0, // Skip to: 16833 + /* 238 */ MCD_OPC_Decode, + 189, + 86, + 32, // Opcode: VLSEG2E8_V + /* 242 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 263 + /* 247 */ MCD_OPC_CheckPredicate, + 5, + 197, + 64, + 0, // Skip to: 16833 + /* 252 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 190, + 64, + 0, // Skip to: 16833 + /* 259 */ MCD_OPC_Decode, + 128, + 86, + 36, // Opcode: VL2RE8_V + /* 263 */ MCD_OPC_FilterValue, + 16, + 181, + 64, + 0, // Skip to: 16833 + /* 268 */ MCD_OPC_CheckPredicate, + 6, + 176, + 64, + 0, // Skip to: 16833 + /* 273 */ MCD_OPC_Decode, + 188, + 86, + 32, // Opcode: VLSEG2E8FF_V + /* 277 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 291 + /* 282 */ MCD_OPC_CheckPredicate, + 6, + 162, + 64, + 0, // Skip to: 16833 + /* 287 */ MCD_OPC_Decode, + 145, + 87, + 34, // Opcode: VLUXSEG2EI8_V + /* 291 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 305 + /* 296 */ MCD_OPC_CheckPredicate, + 6, + 148, + 64, + 0, // Skip to: 16833 + /* 301 */ MCD_OPC_Decode, + 241, + 86, + 35, // Opcode: VLSSEG2E8_V + /* 305 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 319 + /* 310 */ MCD_OPC_CheckPredicate, + 6, + 134, + 64, + 0, // Skip to: 16833 + /* 315 */ MCD_OPC_Decode, + 153, + 86, + 34, // Opcode: VLOXSEG2EI8_V + /* 319 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 355 + /* 324 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 327 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 341 + /* 332 */ MCD_OPC_CheckPredicate, + 6, + 112, + 64, + 0, // Skip to: 16833 + /* 337 */ MCD_OPC_Decode, + 197, + 86, + 32, // Opcode: VLSEG3E8_V + /* 341 */ MCD_OPC_FilterValue, + 16, + 103, + 64, + 0, // Skip to: 16833 + /* 346 */ MCD_OPC_CheckPredicate, + 6, + 98, + 64, + 0, // Skip to: 16833 + /* 351 */ MCD_OPC_Decode, + 196, + 86, + 32, // Opcode: VLSEG3E8FF_V + /* 355 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 369 + /* 360 */ MCD_OPC_CheckPredicate, + 6, + 84, + 64, + 0, // Skip to: 16833 + /* 365 */ MCD_OPC_Decode, + 149, + 87, + 34, // Opcode: VLUXSEG3EI8_V + /* 369 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 383 + /* 374 */ MCD_OPC_CheckPredicate, + 6, + 70, + 64, + 0, // Skip to: 16833 + /* 379 */ MCD_OPC_Decode, + 245, + 86, + 35, // Opcode: VLSSEG3E8_V + /* 383 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 397 + /* 388 */ MCD_OPC_CheckPredicate, + 6, + 56, + 64, + 0, // Skip to: 16833 + /* 393 */ MCD_OPC_Decode, + 157, + 86, + 34, // Opcode: VLOXSEG3EI8_V + /* 397 */ MCD_OPC_FilterValue, + 24, + 52, + 0, + 0, // Skip to: 454 + /* 402 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 405 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 419 + /* 410 */ MCD_OPC_CheckPredicate, + 6, + 34, + 64, + 0, // Skip to: 16833 + /* 415 */ MCD_OPC_Decode, + 205, + 86, + 32, // Opcode: VLSEG4E8_V + /* 419 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 440 + /* 424 */ MCD_OPC_CheckPredicate, + 5, + 20, + 64, + 0, // Skip to: 16833 + /* 429 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 13, + 64, + 0, // Skip to: 16833 + /* 436 */ MCD_OPC_Decode, + 132, + 86, + 37, // Opcode: VL4RE8_V + /* 440 */ MCD_OPC_FilterValue, + 16, + 4, + 64, + 0, // Skip to: 16833 + /* 445 */ MCD_OPC_CheckPredicate, + 6, + 255, + 63, + 0, // Skip to: 16833 + /* 450 */ MCD_OPC_Decode, + 204, + 86, + 32, // Opcode: VLSEG4E8FF_V + /* 454 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 468 + /* 459 */ MCD_OPC_CheckPredicate, + 6, + 241, + 63, + 0, // Skip to: 16833 + /* 464 */ MCD_OPC_Decode, + 153, + 87, + 34, // Opcode: VLUXSEG4EI8_V + /* 468 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 482 + /* 473 */ MCD_OPC_CheckPredicate, + 6, + 227, + 63, + 0, // Skip to: 16833 + /* 478 */ MCD_OPC_Decode, + 249, + 86, + 35, // Opcode: VLSSEG4E8_V + /* 482 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 496 + /* 487 */ MCD_OPC_CheckPredicate, + 6, + 213, + 63, + 0, // Skip to: 16833 + /* 492 */ MCD_OPC_Decode, + 161, + 86, + 34, // Opcode: VLOXSEG4EI8_V + /* 496 */ MCD_OPC_FilterValue, + 32, + 31, + 0, + 0, // Skip to: 532 + /* 501 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 504 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 518 + /* 509 */ MCD_OPC_CheckPredicate, + 6, + 191, + 63, + 0, // Skip to: 16833 + /* 514 */ MCD_OPC_Decode, + 213, + 86, + 32, // Opcode: VLSEG5E8_V + /* 518 */ MCD_OPC_FilterValue, + 16, + 182, + 63, + 0, // Skip to: 16833 + /* 523 */ MCD_OPC_CheckPredicate, + 6, + 177, + 63, + 0, // Skip to: 16833 + /* 528 */ MCD_OPC_Decode, + 212, + 86, + 32, // Opcode: VLSEG5E8FF_V + /* 532 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 546 + /* 537 */ MCD_OPC_CheckPredicate, + 6, + 163, + 63, + 0, // Skip to: 16833 + /* 542 */ MCD_OPC_Decode, + 157, + 87, + 34, // Opcode: VLUXSEG5EI8_V + /* 546 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 560 + /* 551 */ MCD_OPC_CheckPredicate, + 6, + 149, + 63, + 0, // Skip to: 16833 + /* 556 */ MCD_OPC_Decode, + 253, + 86, + 35, // Opcode: VLSSEG5E8_V + /* 560 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 574 + /* 565 */ MCD_OPC_CheckPredicate, + 6, + 135, + 63, + 0, // Skip to: 16833 + /* 570 */ MCD_OPC_Decode, + 165, + 86, + 34, // Opcode: VLOXSEG5EI8_V + /* 574 */ MCD_OPC_FilterValue, + 40, + 31, + 0, + 0, // Skip to: 610 + /* 579 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 582 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 596 + /* 587 */ MCD_OPC_CheckPredicate, + 6, + 113, + 63, + 0, // Skip to: 16833 + /* 592 */ MCD_OPC_Decode, + 221, + 86, + 32, // Opcode: VLSEG6E8_V + /* 596 */ MCD_OPC_FilterValue, + 16, + 104, + 63, + 0, // Skip to: 16833 + /* 601 */ MCD_OPC_CheckPredicate, + 6, + 99, + 63, + 0, // Skip to: 16833 + /* 606 */ MCD_OPC_Decode, + 220, + 86, + 32, // Opcode: VLSEG6E8FF_V + /* 610 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 624 + /* 615 */ MCD_OPC_CheckPredicate, + 6, + 85, + 63, + 0, // Skip to: 16833 + /* 620 */ MCD_OPC_Decode, + 161, + 87, + 34, // Opcode: VLUXSEG6EI8_V + /* 624 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 638 + /* 629 */ MCD_OPC_CheckPredicate, + 6, + 71, + 63, + 0, // Skip to: 16833 + /* 634 */ MCD_OPC_Decode, + 129, + 87, + 35, // Opcode: VLSSEG6E8_V + /* 638 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 652 + /* 643 */ MCD_OPC_CheckPredicate, + 6, + 57, + 63, + 0, // Skip to: 16833 + /* 648 */ MCD_OPC_Decode, + 169, + 86, + 34, // Opcode: VLOXSEG6EI8_V + /* 652 */ MCD_OPC_FilterValue, + 48, + 31, + 0, + 0, // Skip to: 688 + /* 657 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 660 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 674 + /* 665 */ MCD_OPC_CheckPredicate, + 6, + 35, + 63, + 0, // Skip to: 16833 + /* 670 */ MCD_OPC_Decode, + 229, + 86, + 32, // Opcode: VLSEG7E8_V + /* 674 */ MCD_OPC_FilterValue, + 16, + 26, + 63, + 0, // Skip to: 16833 + /* 679 */ MCD_OPC_CheckPredicate, + 6, + 21, + 63, + 0, // Skip to: 16833 + /* 684 */ MCD_OPC_Decode, + 228, + 86, + 32, // Opcode: VLSEG7E8FF_V + /* 688 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 702 + /* 693 */ MCD_OPC_CheckPredicate, + 6, + 7, + 63, + 0, // Skip to: 16833 + /* 698 */ MCD_OPC_Decode, + 165, + 87, + 34, // Opcode: VLUXSEG7EI8_V + /* 702 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 716 + /* 707 */ MCD_OPC_CheckPredicate, + 6, + 249, + 62, + 0, // Skip to: 16833 + /* 712 */ MCD_OPC_Decode, + 133, + 87, + 35, // Opcode: VLSSEG7E8_V + /* 716 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 730 + /* 721 */ MCD_OPC_CheckPredicate, + 6, + 235, + 62, + 0, // Skip to: 16833 + /* 726 */ MCD_OPC_Decode, + 173, + 86, + 34, // Opcode: VLOXSEG7EI8_V + /* 730 */ MCD_OPC_FilterValue, + 56, + 52, + 0, + 0, // Skip to: 787 + /* 735 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 738 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 752 + /* 743 */ MCD_OPC_CheckPredicate, + 6, + 213, + 62, + 0, // Skip to: 16833 + /* 748 */ MCD_OPC_Decode, + 237, + 86, + 32, // Opcode: VLSEG8E8_V + /* 752 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 773 + /* 757 */ MCD_OPC_CheckPredicate, + 5, + 199, + 62, + 0, // Skip to: 16833 + /* 762 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 192, + 62, + 0, // Skip to: 16833 + /* 769 */ MCD_OPC_Decode, + 136, + 86, + 38, // Opcode: VL8RE8_V + /* 773 */ MCD_OPC_FilterValue, + 16, + 183, + 62, + 0, // Skip to: 16833 + /* 778 */ MCD_OPC_CheckPredicate, + 6, + 178, + 62, + 0, // Skip to: 16833 + /* 783 */ MCD_OPC_Decode, + 236, + 86, + 32, // Opcode: VLSEG8E8FF_V + /* 787 */ MCD_OPC_FilterValue, + 57, + 9, + 0, + 0, // Skip to: 801 + /* 792 */ MCD_OPC_CheckPredicate, + 6, + 164, + 62, + 0, // Skip to: 16833 + /* 797 */ MCD_OPC_Decode, + 169, + 87, + 34, // Opcode: VLUXSEG8EI8_V + /* 801 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 815 + /* 806 */ MCD_OPC_CheckPredicate, + 6, + 150, + 62, + 0, // Skip to: 16833 + /* 811 */ MCD_OPC_Decode, + 137, + 87, + 35, // Opcode: VLSSEG8E8_V + /* 815 */ MCD_OPC_FilterValue, + 59, + 141, + 62, + 0, // Skip to: 16833 + /* 820 */ MCD_OPC_CheckPredicate, + 6, + 136, + 62, + 0, // Skip to: 16833 + /* 825 */ MCD_OPC_Decode, + 177, + 86, + 34, // Opcode: VLOXSEG8EI8_V + /* 829 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 843 + /* 834 */ MCD_OPC_CheckPredicate, + 7, + 122, + 62, + 0, // Skip to: 16833 + /* 839 */ MCD_OPC_Decode, + 146, + 83, + 39, // Opcode: FLH + /* 843 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 857 + /* 848 */ MCD_OPC_CheckPredicate, + 8, + 108, + 62, + 0, // Skip to: 16833 + /* 853 */ MCD_OPC_Decode, + 150, + 83, + 40, // Opcode: FLW + /* 857 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 871 + /* 862 */ MCD_OPC_CheckPredicate, + 9, + 94, + 62, + 0, // Skip to: 16833 + /* 867 */ MCD_OPC_Decode, + 142, + 83, + 41, // Opcode: FLD + /* 871 */ MCD_OPC_FilterValue, + 5, + 199, + 2, + 0, // Skip to: 1587 + /* 876 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 879 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 936 + /* 884 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 887 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 901 + /* 892 */ MCD_OPC_CheckPredicate, + 5, + 64, + 62, + 0, // Skip to: 16833 + /* 897 */ MCD_OPC_Decode, + 138, + 86, + 32, // Opcode: VLE16_V + /* 901 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 922 + /* 906 */ MCD_OPC_CheckPredicate, + 5, + 50, + 62, + 0, // Skip to: 16833 + /* 911 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 43, + 62, + 0, // Skip to: 16833 + /* 918 */ MCD_OPC_Decode, + 249, + 85, + 33, // Opcode: VL1RE16_V + /* 922 */ MCD_OPC_FilterValue, + 16, + 34, + 62, + 0, // Skip to: 16833 + /* 927 */ MCD_OPC_CheckPredicate, + 5, + 29, + 62, + 0, // Skip to: 16833 + /* 932 */ MCD_OPC_Decode, + 137, + 86, + 32, // Opcode: VLE16FF_V + /* 936 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 950 + /* 941 */ MCD_OPC_CheckPredicate, + 5, + 15, + 62, + 0, // Skip to: 16833 + /* 946 */ MCD_OPC_Decode, + 138, + 87, + 34, // Opcode: VLUXEI16_V + /* 950 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 964 + /* 955 */ MCD_OPC_CheckPredicate, + 5, + 1, + 62, + 0, // Skip to: 16833 + /* 960 */ MCD_OPC_Decode, + 178, + 86, + 35, // Opcode: VLSE16_V + /* 964 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 978 + /* 969 */ MCD_OPC_CheckPredicate, + 5, + 243, + 61, + 0, // Skip to: 16833 + /* 974 */ MCD_OPC_Decode, + 146, + 86, + 34, // Opcode: VLOXEI16_V + /* 978 */ MCD_OPC_FilterValue, + 8, + 52, + 0, + 0, // Skip to: 1035 + /* 983 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 986 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1000 + /* 991 */ MCD_OPC_CheckPredicate, + 6, + 221, + 61, + 0, // Skip to: 16833 + /* 996 */ MCD_OPC_Decode, + 183, + 86, + 32, // Opcode: VLSEG2E16_V + /* 1000 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 1021 + /* 1005 */ MCD_OPC_CheckPredicate, + 5, + 207, + 61, + 0, // Skip to: 16833 + /* 1010 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 200, + 61, + 0, // Skip to: 16833 + /* 1017 */ MCD_OPC_Decode, + 253, + 85, + 36, // Opcode: VL2RE16_V + /* 1021 */ MCD_OPC_FilterValue, + 16, + 191, + 61, + 0, // Skip to: 16833 + /* 1026 */ MCD_OPC_CheckPredicate, + 6, + 186, + 61, + 0, // Skip to: 16833 + /* 1031 */ MCD_OPC_Decode, + 182, + 86, + 32, // Opcode: VLSEG2E16FF_V + /* 1035 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 1049 + /* 1040 */ MCD_OPC_CheckPredicate, + 6, + 172, + 61, + 0, // Skip to: 16833 + /* 1045 */ MCD_OPC_Decode, + 142, + 87, + 34, // Opcode: VLUXSEG2EI16_V + /* 1049 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 1063 + /* 1054 */ MCD_OPC_CheckPredicate, + 6, + 158, + 61, + 0, // Skip to: 16833 + /* 1059 */ MCD_OPC_Decode, + 238, + 86, + 35, // Opcode: VLSSEG2E16_V + /* 1063 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 1077 + /* 1068 */ MCD_OPC_CheckPredicate, + 6, + 144, + 61, + 0, // Skip to: 16833 + /* 1073 */ MCD_OPC_Decode, + 150, + 86, + 34, // Opcode: VLOXSEG2EI16_V + /* 1077 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 1113 + /* 1082 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1085 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1099 + /* 1090 */ MCD_OPC_CheckPredicate, + 6, + 122, + 61, + 0, // Skip to: 16833 + /* 1095 */ MCD_OPC_Decode, + 191, + 86, + 32, // Opcode: VLSEG3E16_V + /* 1099 */ MCD_OPC_FilterValue, + 16, + 113, + 61, + 0, // Skip to: 16833 + /* 1104 */ MCD_OPC_CheckPredicate, + 6, + 108, + 61, + 0, // Skip to: 16833 + /* 1109 */ MCD_OPC_Decode, + 190, + 86, + 32, // Opcode: VLSEG3E16FF_V + /* 1113 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 1127 + /* 1118 */ MCD_OPC_CheckPredicate, + 6, + 94, + 61, + 0, // Skip to: 16833 + /* 1123 */ MCD_OPC_Decode, + 146, + 87, + 34, // Opcode: VLUXSEG3EI16_V + /* 1127 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 1141 + /* 1132 */ MCD_OPC_CheckPredicate, + 6, + 80, + 61, + 0, // Skip to: 16833 + /* 1137 */ MCD_OPC_Decode, + 242, + 86, + 35, // Opcode: VLSSEG3E16_V + /* 1141 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 1155 + /* 1146 */ MCD_OPC_CheckPredicate, + 6, + 66, + 61, + 0, // Skip to: 16833 + /* 1151 */ MCD_OPC_Decode, + 154, + 86, + 34, // Opcode: VLOXSEG3EI16_V + /* 1155 */ MCD_OPC_FilterValue, + 24, + 52, + 0, + 0, // Skip to: 1212 + /* 1160 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1163 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1177 + /* 1168 */ MCD_OPC_CheckPredicate, + 6, + 44, + 61, + 0, // Skip to: 16833 + /* 1173 */ MCD_OPC_Decode, + 199, + 86, + 32, // Opcode: VLSEG4E16_V + /* 1177 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 1198 + /* 1182 */ MCD_OPC_CheckPredicate, + 5, + 30, + 61, + 0, // Skip to: 16833 + /* 1187 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 23, + 61, + 0, // Skip to: 16833 + /* 1194 */ MCD_OPC_Decode, + 129, + 86, + 37, // Opcode: VL4RE16_V + /* 1198 */ MCD_OPC_FilterValue, + 16, + 14, + 61, + 0, // Skip to: 16833 + /* 1203 */ MCD_OPC_CheckPredicate, + 6, + 9, + 61, + 0, // Skip to: 16833 + /* 1208 */ MCD_OPC_Decode, + 198, + 86, + 32, // Opcode: VLSEG4E16FF_V + /* 1212 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 1226 + /* 1217 */ MCD_OPC_CheckPredicate, + 6, + 251, + 60, + 0, // Skip to: 16833 + /* 1222 */ MCD_OPC_Decode, + 150, + 87, + 34, // Opcode: VLUXSEG4EI16_V + /* 1226 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 1240 + /* 1231 */ MCD_OPC_CheckPredicate, + 6, + 237, + 60, + 0, // Skip to: 16833 + /* 1236 */ MCD_OPC_Decode, + 246, + 86, + 35, // Opcode: VLSSEG4E16_V + /* 1240 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 1254 + /* 1245 */ MCD_OPC_CheckPredicate, + 6, + 223, + 60, + 0, // Skip to: 16833 + /* 1250 */ MCD_OPC_Decode, + 158, + 86, + 34, // Opcode: VLOXSEG4EI16_V + /* 1254 */ MCD_OPC_FilterValue, + 32, + 31, + 0, + 0, // Skip to: 1290 + /* 1259 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1262 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1276 + /* 1267 */ MCD_OPC_CheckPredicate, + 6, + 201, + 60, + 0, // Skip to: 16833 + /* 1272 */ MCD_OPC_Decode, + 207, + 86, + 32, // Opcode: VLSEG5E16_V + /* 1276 */ MCD_OPC_FilterValue, + 16, + 192, + 60, + 0, // Skip to: 16833 + /* 1281 */ MCD_OPC_CheckPredicate, + 6, + 187, + 60, + 0, // Skip to: 16833 + /* 1286 */ MCD_OPC_Decode, + 206, + 86, + 32, // Opcode: VLSEG5E16FF_V + /* 1290 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 1304 + /* 1295 */ MCD_OPC_CheckPredicate, + 6, + 173, + 60, + 0, // Skip to: 16833 + /* 1300 */ MCD_OPC_Decode, + 154, + 87, + 34, // Opcode: VLUXSEG5EI16_V + /* 1304 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 1318 + /* 1309 */ MCD_OPC_CheckPredicate, + 6, + 159, + 60, + 0, // Skip to: 16833 + /* 1314 */ MCD_OPC_Decode, + 250, + 86, + 35, // Opcode: VLSSEG5E16_V + /* 1318 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 1332 + /* 1323 */ MCD_OPC_CheckPredicate, + 6, + 145, + 60, + 0, // Skip to: 16833 + /* 1328 */ MCD_OPC_Decode, + 162, + 86, + 34, // Opcode: VLOXSEG5EI16_V + /* 1332 */ MCD_OPC_FilterValue, + 40, + 31, + 0, + 0, // Skip to: 1368 + /* 1337 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1340 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1354 + /* 1345 */ MCD_OPC_CheckPredicate, + 6, + 123, + 60, + 0, // Skip to: 16833 + /* 1350 */ MCD_OPC_Decode, + 215, + 86, + 32, // Opcode: VLSEG6E16_V + /* 1354 */ MCD_OPC_FilterValue, + 16, + 114, + 60, + 0, // Skip to: 16833 + /* 1359 */ MCD_OPC_CheckPredicate, + 6, + 109, + 60, + 0, // Skip to: 16833 + /* 1364 */ MCD_OPC_Decode, + 214, + 86, + 32, // Opcode: VLSEG6E16FF_V + /* 1368 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 1382 + /* 1373 */ MCD_OPC_CheckPredicate, + 6, + 95, + 60, + 0, // Skip to: 16833 + /* 1378 */ MCD_OPC_Decode, + 158, + 87, + 34, // Opcode: VLUXSEG6EI16_V + /* 1382 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 1396 + /* 1387 */ MCD_OPC_CheckPredicate, + 6, + 81, + 60, + 0, // Skip to: 16833 + /* 1392 */ MCD_OPC_Decode, + 254, + 86, + 35, // Opcode: VLSSEG6E16_V + /* 1396 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 1410 + /* 1401 */ MCD_OPC_CheckPredicate, + 6, + 67, + 60, + 0, // Skip to: 16833 + /* 1406 */ MCD_OPC_Decode, + 166, + 86, + 34, // Opcode: VLOXSEG6EI16_V + /* 1410 */ MCD_OPC_FilterValue, + 48, + 31, + 0, + 0, // Skip to: 1446 + /* 1415 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1418 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1432 + /* 1423 */ MCD_OPC_CheckPredicate, + 6, + 45, + 60, + 0, // Skip to: 16833 + /* 1428 */ MCD_OPC_Decode, + 223, + 86, + 32, // Opcode: VLSEG7E16_V + /* 1432 */ MCD_OPC_FilterValue, + 16, + 36, + 60, + 0, // Skip to: 16833 + /* 1437 */ MCD_OPC_CheckPredicate, + 6, + 31, + 60, + 0, // Skip to: 16833 + /* 1442 */ MCD_OPC_Decode, + 222, + 86, + 32, // Opcode: VLSEG7E16FF_V + /* 1446 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 1460 + /* 1451 */ MCD_OPC_CheckPredicate, + 6, + 17, + 60, + 0, // Skip to: 16833 + /* 1456 */ MCD_OPC_Decode, + 162, + 87, + 34, // Opcode: VLUXSEG7EI16_V + /* 1460 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 1474 + /* 1465 */ MCD_OPC_CheckPredicate, + 6, + 3, + 60, + 0, // Skip to: 16833 + /* 1470 */ MCD_OPC_Decode, + 130, + 87, + 35, // Opcode: VLSSEG7E16_V + /* 1474 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 1488 + /* 1479 */ MCD_OPC_CheckPredicate, + 6, + 245, + 59, + 0, // Skip to: 16833 + /* 1484 */ MCD_OPC_Decode, + 170, + 86, + 34, // Opcode: VLOXSEG7EI16_V + /* 1488 */ MCD_OPC_FilterValue, + 56, + 52, + 0, + 0, // Skip to: 1545 + /* 1493 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1496 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1510 + /* 1501 */ MCD_OPC_CheckPredicate, + 6, + 223, + 59, + 0, // Skip to: 16833 + /* 1506 */ MCD_OPC_Decode, + 231, + 86, + 32, // Opcode: VLSEG8E16_V + /* 1510 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 1531 + /* 1515 */ MCD_OPC_CheckPredicate, + 5, + 209, + 59, + 0, // Skip to: 16833 + /* 1520 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 202, + 59, + 0, // Skip to: 16833 + /* 1527 */ MCD_OPC_Decode, + 133, + 86, + 38, // Opcode: VL8RE16_V + /* 1531 */ MCD_OPC_FilterValue, + 16, + 193, + 59, + 0, // Skip to: 16833 + /* 1536 */ MCD_OPC_CheckPredicate, + 6, + 188, + 59, + 0, // Skip to: 16833 + /* 1541 */ MCD_OPC_Decode, + 230, + 86, + 32, // Opcode: VLSEG8E16FF_V + /* 1545 */ MCD_OPC_FilterValue, + 57, + 9, + 0, + 0, // Skip to: 1559 + /* 1550 */ MCD_OPC_CheckPredicate, + 6, + 174, + 59, + 0, // Skip to: 16833 + /* 1555 */ MCD_OPC_Decode, + 166, + 87, + 34, // Opcode: VLUXSEG8EI16_V + /* 1559 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 1573 + /* 1564 */ MCD_OPC_CheckPredicate, + 6, + 160, + 59, + 0, // Skip to: 16833 + /* 1569 */ MCD_OPC_Decode, + 134, + 87, + 35, // Opcode: VLSSEG8E16_V + /* 1573 */ MCD_OPC_FilterValue, + 59, + 151, + 59, + 0, // Skip to: 16833 + /* 1578 */ MCD_OPC_CheckPredicate, + 6, + 146, + 59, + 0, // Skip to: 16833 + /* 1583 */ MCD_OPC_Decode, + 174, + 86, + 34, // Opcode: VLOXSEG8EI16_V + /* 1587 */ MCD_OPC_FilterValue, + 6, + 199, + 2, + 0, // Skip to: 2303 + /* 1592 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 1595 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 1652 + /* 1600 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1603 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1617 + /* 1608 */ MCD_OPC_CheckPredicate, + 5, + 116, + 59, + 0, // Skip to: 16833 + /* 1613 */ MCD_OPC_Decode, + 140, + 86, + 32, // Opcode: VLE32_V + /* 1617 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 1638 + /* 1622 */ MCD_OPC_CheckPredicate, + 5, + 102, + 59, + 0, // Skip to: 16833 + /* 1627 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 95, + 59, + 0, // Skip to: 16833 + /* 1634 */ MCD_OPC_Decode, + 250, + 85, + 33, // Opcode: VL1RE32_V + /* 1638 */ MCD_OPC_FilterValue, + 16, + 86, + 59, + 0, // Skip to: 16833 + /* 1643 */ MCD_OPC_CheckPredicate, + 5, + 81, + 59, + 0, // Skip to: 16833 + /* 1648 */ MCD_OPC_Decode, + 139, + 86, + 32, // Opcode: VLE32FF_V + /* 1652 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1666 + /* 1657 */ MCD_OPC_CheckPredicate, + 5, + 67, + 59, + 0, // Skip to: 16833 + /* 1662 */ MCD_OPC_Decode, + 139, + 87, + 34, // Opcode: VLUXEI32_V + /* 1666 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 1680 + /* 1671 */ MCD_OPC_CheckPredicate, + 5, + 53, + 59, + 0, // Skip to: 16833 + /* 1676 */ MCD_OPC_Decode, + 179, + 86, + 35, // Opcode: VLSE32_V + /* 1680 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 1694 + /* 1685 */ MCD_OPC_CheckPredicate, + 5, + 39, + 59, + 0, // Skip to: 16833 + /* 1690 */ MCD_OPC_Decode, + 147, + 86, + 34, // Opcode: VLOXEI32_V + /* 1694 */ MCD_OPC_FilterValue, + 8, + 52, + 0, + 0, // Skip to: 1751 + /* 1699 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1702 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1716 + /* 1707 */ MCD_OPC_CheckPredicate, + 6, + 17, + 59, + 0, // Skip to: 16833 + /* 1712 */ MCD_OPC_Decode, + 185, + 86, + 32, // Opcode: VLSEG2E32_V + /* 1716 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 1737 + /* 1721 */ MCD_OPC_CheckPredicate, + 5, + 3, + 59, + 0, // Skip to: 16833 + /* 1726 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 252, + 58, + 0, // Skip to: 16833 + /* 1733 */ MCD_OPC_Decode, + 254, + 85, + 36, // Opcode: VL2RE32_V + /* 1737 */ MCD_OPC_FilterValue, + 16, + 243, + 58, + 0, // Skip to: 16833 + /* 1742 */ MCD_OPC_CheckPredicate, + 6, + 238, + 58, + 0, // Skip to: 16833 + /* 1747 */ MCD_OPC_Decode, + 184, + 86, + 32, // Opcode: VLSEG2E32FF_V + /* 1751 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 1765 + /* 1756 */ MCD_OPC_CheckPredicate, + 6, + 224, + 58, + 0, // Skip to: 16833 + /* 1761 */ MCD_OPC_Decode, + 143, + 87, + 34, // Opcode: VLUXSEG2EI32_V + /* 1765 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 1779 + /* 1770 */ MCD_OPC_CheckPredicate, + 6, + 210, + 58, + 0, // Skip to: 16833 + /* 1775 */ MCD_OPC_Decode, + 239, + 86, + 35, // Opcode: VLSSEG2E32_V + /* 1779 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 1793 + /* 1784 */ MCD_OPC_CheckPredicate, + 6, + 196, + 58, + 0, // Skip to: 16833 + /* 1789 */ MCD_OPC_Decode, + 151, + 86, + 34, // Opcode: VLOXSEG2EI32_V + /* 1793 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 1829 + /* 1798 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1801 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1815 + /* 1806 */ MCD_OPC_CheckPredicate, + 6, + 174, + 58, + 0, // Skip to: 16833 + /* 1811 */ MCD_OPC_Decode, + 193, + 86, + 32, // Opcode: VLSEG3E32_V + /* 1815 */ MCD_OPC_FilterValue, + 16, + 165, + 58, + 0, // Skip to: 16833 + /* 1820 */ MCD_OPC_CheckPredicate, + 6, + 160, + 58, + 0, // Skip to: 16833 + /* 1825 */ MCD_OPC_Decode, + 192, + 86, + 32, // Opcode: VLSEG3E32FF_V + /* 1829 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 1843 + /* 1834 */ MCD_OPC_CheckPredicate, + 6, + 146, + 58, + 0, // Skip to: 16833 + /* 1839 */ MCD_OPC_Decode, + 147, + 87, + 34, // Opcode: VLUXSEG3EI32_V + /* 1843 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 1857 + /* 1848 */ MCD_OPC_CheckPredicate, + 6, + 132, + 58, + 0, // Skip to: 16833 + /* 1853 */ MCD_OPC_Decode, + 243, + 86, + 35, // Opcode: VLSSEG3E32_V + /* 1857 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 1871 + /* 1862 */ MCD_OPC_CheckPredicate, + 6, + 118, + 58, + 0, // Skip to: 16833 + /* 1867 */ MCD_OPC_Decode, + 155, + 86, + 34, // Opcode: VLOXSEG3EI32_V + /* 1871 */ MCD_OPC_FilterValue, + 24, + 52, + 0, + 0, // Skip to: 1928 + /* 1876 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1879 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1893 + /* 1884 */ MCD_OPC_CheckPredicate, + 6, + 96, + 58, + 0, // Skip to: 16833 + /* 1889 */ MCD_OPC_Decode, + 201, + 86, + 32, // Opcode: VLSEG4E32_V + /* 1893 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 1914 + /* 1898 */ MCD_OPC_CheckPredicate, + 5, + 82, + 58, + 0, // Skip to: 16833 + /* 1903 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 75, + 58, + 0, // Skip to: 16833 + /* 1910 */ MCD_OPC_Decode, + 130, + 86, + 37, // Opcode: VL4RE32_V + /* 1914 */ MCD_OPC_FilterValue, + 16, + 66, + 58, + 0, // Skip to: 16833 + /* 1919 */ MCD_OPC_CheckPredicate, + 6, + 61, + 58, + 0, // Skip to: 16833 + /* 1924 */ MCD_OPC_Decode, + 200, + 86, + 32, // Opcode: VLSEG4E32FF_V + /* 1928 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 1942 + /* 1933 */ MCD_OPC_CheckPredicate, + 6, + 47, + 58, + 0, // Skip to: 16833 + /* 1938 */ MCD_OPC_Decode, + 151, + 87, + 34, // Opcode: VLUXSEG4EI32_V + /* 1942 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 1956 + /* 1947 */ MCD_OPC_CheckPredicate, + 6, + 33, + 58, + 0, // Skip to: 16833 + /* 1952 */ MCD_OPC_Decode, + 247, + 86, + 35, // Opcode: VLSSEG4E32_V + /* 1956 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 1970 + /* 1961 */ MCD_OPC_CheckPredicate, + 6, + 19, + 58, + 0, // Skip to: 16833 + /* 1966 */ MCD_OPC_Decode, + 159, + 86, + 34, // Opcode: VLOXSEG4EI32_V + /* 1970 */ MCD_OPC_FilterValue, + 32, + 31, + 0, + 0, // Skip to: 2006 + /* 1975 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 1978 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1992 + /* 1983 */ MCD_OPC_CheckPredicate, + 6, + 253, + 57, + 0, // Skip to: 16833 + /* 1988 */ MCD_OPC_Decode, + 209, + 86, + 32, // Opcode: VLSEG5E32_V + /* 1992 */ MCD_OPC_FilterValue, + 16, + 244, + 57, + 0, // Skip to: 16833 + /* 1997 */ MCD_OPC_CheckPredicate, + 6, + 239, + 57, + 0, // Skip to: 16833 + /* 2002 */ MCD_OPC_Decode, + 208, + 86, + 32, // Opcode: VLSEG5E32FF_V + /* 2006 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 2020 + /* 2011 */ MCD_OPC_CheckPredicate, + 6, + 225, + 57, + 0, // Skip to: 16833 + /* 2016 */ MCD_OPC_Decode, + 155, + 87, + 34, // Opcode: VLUXSEG5EI32_V + /* 2020 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 2034 + /* 2025 */ MCD_OPC_CheckPredicate, + 6, + 211, + 57, + 0, // Skip to: 16833 + /* 2030 */ MCD_OPC_Decode, + 251, + 86, + 35, // Opcode: VLSSEG5E32_V + /* 2034 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 2048 + /* 2039 */ MCD_OPC_CheckPredicate, + 6, + 197, + 57, + 0, // Skip to: 16833 + /* 2044 */ MCD_OPC_Decode, + 163, + 86, + 34, // Opcode: VLOXSEG5EI32_V + /* 2048 */ MCD_OPC_FilterValue, + 40, + 31, + 0, + 0, // Skip to: 2084 + /* 2053 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2056 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2070 + /* 2061 */ MCD_OPC_CheckPredicate, + 6, + 175, + 57, + 0, // Skip to: 16833 + /* 2066 */ MCD_OPC_Decode, + 217, + 86, + 32, // Opcode: VLSEG6E32_V + /* 2070 */ MCD_OPC_FilterValue, + 16, + 166, + 57, + 0, // Skip to: 16833 + /* 2075 */ MCD_OPC_CheckPredicate, + 6, + 161, + 57, + 0, // Skip to: 16833 + /* 2080 */ MCD_OPC_Decode, + 216, + 86, + 32, // Opcode: VLSEG6E32FF_V + /* 2084 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 2098 + /* 2089 */ MCD_OPC_CheckPredicate, + 6, + 147, + 57, + 0, // Skip to: 16833 + /* 2094 */ MCD_OPC_Decode, + 159, + 87, + 34, // Opcode: VLUXSEG6EI32_V + /* 2098 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 2112 + /* 2103 */ MCD_OPC_CheckPredicate, + 6, + 133, + 57, + 0, // Skip to: 16833 + /* 2108 */ MCD_OPC_Decode, + 255, + 86, + 35, // Opcode: VLSSEG6E32_V + /* 2112 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 2126 + /* 2117 */ MCD_OPC_CheckPredicate, + 6, + 119, + 57, + 0, // Skip to: 16833 + /* 2122 */ MCD_OPC_Decode, + 167, + 86, + 34, // Opcode: VLOXSEG6EI32_V + /* 2126 */ MCD_OPC_FilterValue, + 48, + 31, + 0, + 0, // Skip to: 2162 + /* 2131 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2134 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2148 + /* 2139 */ MCD_OPC_CheckPredicate, + 6, + 97, + 57, + 0, // Skip to: 16833 + /* 2144 */ MCD_OPC_Decode, + 225, + 86, + 32, // Opcode: VLSEG7E32_V + /* 2148 */ MCD_OPC_FilterValue, + 16, + 88, + 57, + 0, // Skip to: 16833 + /* 2153 */ MCD_OPC_CheckPredicate, + 6, + 83, + 57, + 0, // Skip to: 16833 + /* 2158 */ MCD_OPC_Decode, + 224, + 86, + 32, // Opcode: VLSEG7E32FF_V + /* 2162 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 2176 + /* 2167 */ MCD_OPC_CheckPredicate, + 6, + 69, + 57, + 0, // Skip to: 16833 + /* 2172 */ MCD_OPC_Decode, + 163, + 87, + 34, // Opcode: VLUXSEG7EI32_V + /* 2176 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 2190 + /* 2181 */ MCD_OPC_CheckPredicate, + 6, + 55, + 57, + 0, // Skip to: 16833 + /* 2186 */ MCD_OPC_Decode, + 131, + 87, + 35, // Opcode: VLSSEG7E32_V + /* 2190 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 2204 + /* 2195 */ MCD_OPC_CheckPredicate, + 6, + 41, + 57, + 0, // Skip to: 16833 + /* 2200 */ MCD_OPC_Decode, + 171, + 86, + 34, // Opcode: VLOXSEG7EI32_V + /* 2204 */ MCD_OPC_FilterValue, + 56, + 52, + 0, + 0, // Skip to: 2261 + /* 2209 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2212 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2226 + /* 2217 */ MCD_OPC_CheckPredicate, + 6, + 19, + 57, + 0, // Skip to: 16833 + /* 2222 */ MCD_OPC_Decode, + 233, + 86, + 32, // Opcode: VLSEG8E32_V + /* 2226 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 2247 + /* 2231 */ MCD_OPC_CheckPredicate, + 5, + 5, + 57, + 0, // Skip to: 16833 + /* 2236 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 254, + 56, + 0, // Skip to: 16833 + /* 2243 */ MCD_OPC_Decode, + 134, + 86, + 38, // Opcode: VL8RE32_V + /* 2247 */ MCD_OPC_FilterValue, + 16, + 245, + 56, + 0, // Skip to: 16833 + /* 2252 */ MCD_OPC_CheckPredicate, + 6, + 240, + 56, + 0, // Skip to: 16833 + /* 2257 */ MCD_OPC_Decode, + 232, + 86, + 32, // Opcode: VLSEG8E32FF_V + /* 2261 */ MCD_OPC_FilterValue, + 57, + 9, + 0, + 0, // Skip to: 2275 + /* 2266 */ MCD_OPC_CheckPredicate, + 6, + 226, + 56, + 0, // Skip to: 16833 + /* 2271 */ MCD_OPC_Decode, + 167, + 87, + 34, // Opcode: VLUXSEG8EI32_V + /* 2275 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 2289 + /* 2280 */ MCD_OPC_CheckPredicate, + 6, + 212, + 56, + 0, // Skip to: 16833 + /* 2285 */ MCD_OPC_Decode, + 135, + 87, + 35, // Opcode: VLSSEG8E32_V + /* 2289 */ MCD_OPC_FilterValue, + 59, + 203, + 56, + 0, // Skip to: 16833 + /* 2294 */ MCD_OPC_CheckPredicate, + 6, + 198, + 56, + 0, // Skip to: 16833 + /* 2299 */ MCD_OPC_Decode, + 175, + 86, + 34, // Opcode: VLOXSEG8EI32_V + /* 2303 */ MCD_OPC_FilterValue, + 7, + 189, + 56, + 0, // Skip to: 16833 + /* 2308 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 2311 */ MCD_OPC_FilterValue, + 0, + 52, + 0, + 0, // Skip to: 2368 + /* 2316 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2319 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2333 + /* 2324 */ MCD_OPC_CheckPredicate, + 5, + 168, + 56, + 0, // Skip to: 16833 + /* 2329 */ MCD_OPC_Decode, + 142, + 86, + 32, // Opcode: VLE64_V + /* 2333 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 2354 + /* 2338 */ MCD_OPC_CheckPredicate, + 5, + 154, + 56, + 0, // Skip to: 16833 + /* 2343 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 147, + 56, + 0, // Skip to: 16833 + /* 2350 */ MCD_OPC_Decode, + 251, + 85, + 33, // Opcode: VL1RE64_V + /* 2354 */ MCD_OPC_FilterValue, + 16, + 138, + 56, + 0, // Skip to: 16833 + /* 2359 */ MCD_OPC_CheckPredicate, + 5, + 133, + 56, + 0, // Skip to: 16833 + /* 2364 */ MCD_OPC_Decode, + 141, + 86, + 32, // Opcode: VLE64FF_V + /* 2368 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 2382 + /* 2373 */ MCD_OPC_CheckPredicate, + 5, + 119, + 56, + 0, // Skip to: 16833 + /* 2378 */ MCD_OPC_Decode, + 140, + 87, + 34, // Opcode: VLUXEI64_V + /* 2382 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 2396 + /* 2387 */ MCD_OPC_CheckPredicate, + 5, + 105, + 56, + 0, // Skip to: 16833 + /* 2392 */ MCD_OPC_Decode, + 180, + 86, + 35, // Opcode: VLSE64_V + /* 2396 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 2410 + /* 2401 */ MCD_OPC_CheckPredicate, + 5, + 91, + 56, + 0, // Skip to: 16833 + /* 2406 */ MCD_OPC_Decode, + 148, + 86, + 34, // Opcode: VLOXEI64_V + /* 2410 */ MCD_OPC_FilterValue, + 8, + 52, + 0, + 0, // Skip to: 2467 + /* 2415 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2418 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2432 + /* 2423 */ MCD_OPC_CheckPredicate, + 6, + 69, + 56, + 0, // Skip to: 16833 + /* 2428 */ MCD_OPC_Decode, + 187, + 86, + 32, // Opcode: VLSEG2E64_V + /* 2432 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 2453 + /* 2437 */ MCD_OPC_CheckPredicate, + 5, + 55, + 56, + 0, // Skip to: 16833 + /* 2442 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 48, + 56, + 0, // Skip to: 16833 + /* 2449 */ MCD_OPC_Decode, + 255, + 85, + 36, // Opcode: VL2RE64_V + /* 2453 */ MCD_OPC_FilterValue, + 16, + 39, + 56, + 0, // Skip to: 16833 + /* 2458 */ MCD_OPC_CheckPredicate, + 6, + 34, + 56, + 0, // Skip to: 16833 + /* 2463 */ MCD_OPC_Decode, + 186, + 86, + 32, // Opcode: VLSEG2E64FF_V + /* 2467 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 2481 + /* 2472 */ MCD_OPC_CheckPredicate, + 6, + 20, + 56, + 0, // Skip to: 16833 + /* 2477 */ MCD_OPC_Decode, + 144, + 87, + 34, // Opcode: VLUXSEG2EI64_V + /* 2481 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 2495 + /* 2486 */ MCD_OPC_CheckPredicate, + 6, + 6, + 56, + 0, // Skip to: 16833 + /* 2491 */ MCD_OPC_Decode, + 240, + 86, + 35, // Opcode: VLSSEG2E64_V + /* 2495 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 2509 + /* 2500 */ MCD_OPC_CheckPredicate, + 6, + 248, + 55, + 0, // Skip to: 16833 + /* 2505 */ MCD_OPC_Decode, + 152, + 86, + 34, // Opcode: VLOXSEG2EI64_V + /* 2509 */ MCD_OPC_FilterValue, + 16, + 31, + 0, + 0, // Skip to: 2545 + /* 2514 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2517 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2531 + /* 2522 */ MCD_OPC_CheckPredicate, + 6, + 226, + 55, + 0, // Skip to: 16833 + /* 2527 */ MCD_OPC_Decode, + 195, + 86, + 32, // Opcode: VLSEG3E64_V + /* 2531 */ MCD_OPC_FilterValue, + 16, + 217, + 55, + 0, // Skip to: 16833 + /* 2536 */ MCD_OPC_CheckPredicate, + 6, + 212, + 55, + 0, // Skip to: 16833 + /* 2541 */ MCD_OPC_Decode, + 194, + 86, + 32, // Opcode: VLSEG3E64FF_V + /* 2545 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 2559 + /* 2550 */ MCD_OPC_CheckPredicate, + 6, + 198, + 55, + 0, // Skip to: 16833 + /* 2555 */ MCD_OPC_Decode, + 148, + 87, + 34, // Opcode: VLUXSEG3EI64_V + /* 2559 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 2573 + /* 2564 */ MCD_OPC_CheckPredicate, + 6, + 184, + 55, + 0, // Skip to: 16833 + /* 2569 */ MCD_OPC_Decode, + 244, + 86, + 35, // Opcode: VLSSEG3E64_V + /* 2573 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 2587 + /* 2578 */ MCD_OPC_CheckPredicate, + 6, + 170, + 55, + 0, // Skip to: 16833 + /* 2583 */ MCD_OPC_Decode, + 156, + 86, + 34, // Opcode: VLOXSEG3EI64_V + /* 2587 */ MCD_OPC_FilterValue, + 24, + 52, + 0, + 0, // Skip to: 2644 + /* 2592 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2595 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2609 + /* 2600 */ MCD_OPC_CheckPredicate, + 6, + 148, + 55, + 0, // Skip to: 16833 + /* 2605 */ MCD_OPC_Decode, + 203, + 86, + 32, // Opcode: VLSEG4E64_V + /* 2609 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 2630 + /* 2614 */ MCD_OPC_CheckPredicate, + 5, + 134, + 55, + 0, // Skip to: 16833 + /* 2619 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 127, + 55, + 0, // Skip to: 16833 + /* 2626 */ MCD_OPC_Decode, + 131, + 86, + 37, // Opcode: VL4RE64_V + /* 2630 */ MCD_OPC_FilterValue, + 16, + 118, + 55, + 0, // Skip to: 16833 + /* 2635 */ MCD_OPC_CheckPredicate, + 6, + 113, + 55, + 0, // Skip to: 16833 + /* 2640 */ MCD_OPC_Decode, + 202, + 86, + 32, // Opcode: VLSEG4E64FF_V + /* 2644 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 2658 + /* 2649 */ MCD_OPC_CheckPredicate, + 6, + 99, + 55, + 0, // Skip to: 16833 + /* 2654 */ MCD_OPC_Decode, + 152, + 87, + 34, // Opcode: VLUXSEG4EI64_V + /* 2658 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 2672 + /* 2663 */ MCD_OPC_CheckPredicate, + 6, + 85, + 55, + 0, // Skip to: 16833 + /* 2668 */ MCD_OPC_Decode, + 248, + 86, + 35, // Opcode: VLSSEG4E64_V + /* 2672 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 2686 + /* 2677 */ MCD_OPC_CheckPredicate, + 6, + 71, + 55, + 0, // Skip to: 16833 + /* 2682 */ MCD_OPC_Decode, + 160, + 86, + 34, // Opcode: VLOXSEG4EI64_V + /* 2686 */ MCD_OPC_FilterValue, + 32, + 31, + 0, + 0, // Skip to: 2722 + /* 2691 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2694 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2708 + /* 2699 */ MCD_OPC_CheckPredicate, + 6, + 49, + 55, + 0, // Skip to: 16833 + /* 2704 */ MCD_OPC_Decode, + 211, + 86, + 32, // Opcode: VLSEG5E64_V + /* 2708 */ MCD_OPC_FilterValue, + 16, + 40, + 55, + 0, // Skip to: 16833 + /* 2713 */ MCD_OPC_CheckPredicate, + 6, + 35, + 55, + 0, // Skip to: 16833 + /* 2718 */ MCD_OPC_Decode, + 210, + 86, + 32, // Opcode: VLSEG5E64FF_V + /* 2722 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 2736 + /* 2727 */ MCD_OPC_CheckPredicate, + 6, + 21, + 55, + 0, // Skip to: 16833 + /* 2732 */ MCD_OPC_Decode, + 156, + 87, + 34, // Opcode: VLUXSEG5EI64_V + /* 2736 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 2750 + /* 2741 */ MCD_OPC_CheckPredicate, + 6, + 7, + 55, + 0, // Skip to: 16833 + /* 2746 */ MCD_OPC_Decode, + 252, + 86, + 35, // Opcode: VLSSEG5E64_V + /* 2750 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 2764 + /* 2755 */ MCD_OPC_CheckPredicate, + 6, + 249, + 54, + 0, // Skip to: 16833 + /* 2760 */ MCD_OPC_Decode, + 164, + 86, + 34, // Opcode: VLOXSEG5EI64_V + /* 2764 */ MCD_OPC_FilterValue, + 40, + 31, + 0, + 0, // Skip to: 2800 + /* 2769 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2772 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2786 + /* 2777 */ MCD_OPC_CheckPredicate, + 6, + 227, + 54, + 0, // Skip to: 16833 + /* 2782 */ MCD_OPC_Decode, + 219, + 86, + 32, // Opcode: VLSEG6E64_V + /* 2786 */ MCD_OPC_FilterValue, + 16, + 218, + 54, + 0, // Skip to: 16833 + /* 2791 */ MCD_OPC_CheckPredicate, + 6, + 213, + 54, + 0, // Skip to: 16833 + /* 2796 */ MCD_OPC_Decode, + 218, + 86, + 32, // Opcode: VLSEG6E64FF_V + /* 2800 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 2814 + /* 2805 */ MCD_OPC_CheckPredicate, + 6, + 199, + 54, + 0, // Skip to: 16833 + /* 2810 */ MCD_OPC_Decode, + 160, + 87, + 34, // Opcode: VLUXSEG6EI64_V + /* 2814 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 2828 + /* 2819 */ MCD_OPC_CheckPredicate, + 6, + 185, + 54, + 0, // Skip to: 16833 + /* 2824 */ MCD_OPC_Decode, + 128, + 87, + 35, // Opcode: VLSSEG6E64_V + /* 2828 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 2842 + /* 2833 */ MCD_OPC_CheckPredicate, + 6, + 171, + 54, + 0, // Skip to: 16833 + /* 2838 */ MCD_OPC_Decode, + 168, + 86, + 34, // Opcode: VLOXSEG6EI64_V + /* 2842 */ MCD_OPC_FilterValue, + 48, + 31, + 0, + 0, // Skip to: 2878 + /* 2847 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2850 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2864 + /* 2855 */ MCD_OPC_CheckPredicate, + 6, + 149, + 54, + 0, // Skip to: 16833 + /* 2860 */ MCD_OPC_Decode, + 227, + 86, + 32, // Opcode: VLSEG7E64_V + /* 2864 */ MCD_OPC_FilterValue, + 16, + 140, + 54, + 0, // Skip to: 16833 + /* 2869 */ MCD_OPC_CheckPredicate, + 6, + 135, + 54, + 0, // Skip to: 16833 + /* 2874 */ MCD_OPC_Decode, + 226, + 86, + 32, // Opcode: VLSEG7E64FF_V + /* 2878 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 2892 + /* 2883 */ MCD_OPC_CheckPredicate, + 6, + 121, + 54, + 0, // Skip to: 16833 + /* 2888 */ MCD_OPC_Decode, + 164, + 87, + 34, // Opcode: VLUXSEG7EI64_V + /* 2892 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 2906 + /* 2897 */ MCD_OPC_CheckPredicate, + 6, + 107, + 54, + 0, // Skip to: 16833 + /* 2902 */ MCD_OPC_Decode, + 132, + 87, + 35, // Opcode: VLSSEG7E64_V + /* 2906 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 2920 + /* 2911 */ MCD_OPC_CheckPredicate, + 6, + 93, + 54, + 0, // Skip to: 16833 + /* 2916 */ MCD_OPC_Decode, + 172, + 86, + 34, // Opcode: VLOXSEG7EI64_V + /* 2920 */ MCD_OPC_FilterValue, + 56, + 52, + 0, + 0, // Skip to: 2977 + /* 2925 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 2928 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2942 + /* 2933 */ MCD_OPC_CheckPredicate, + 6, + 71, + 54, + 0, // Skip to: 16833 + /* 2938 */ MCD_OPC_Decode, + 235, + 86, + 32, // Opcode: VLSEG8E64_V + /* 2942 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 2963 + /* 2947 */ MCD_OPC_CheckPredicate, + 5, + 57, + 54, + 0, // Skip to: 16833 + /* 2952 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 50, + 54, + 0, // Skip to: 16833 + /* 2959 */ MCD_OPC_Decode, + 135, + 86, + 38, // Opcode: VL8RE64_V + /* 2963 */ MCD_OPC_FilterValue, + 16, + 41, + 54, + 0, // Skip to: 16833 + /* 2968 */ MCD_OPC_CheckPredicate, + 6, + 36, + 54, + 0, // Skip to: 16833 + /* 2973 */ MCD_OPC_Decode, + 234, + 86, + 32, // Opcode: VLSEG8E64FF_V + /* 2977 */ MCD_OPC_FilterValue, + 57, + 9, + 0, + 0, // Skip to: 2991 + /* 2982 */ MCD_OPC_CheckPredicate, + 6, + 22, + 54, + 0, // Skip to: 16833 + /* 2987 */ MCD_OPC_Decode, + 168, + 87, + 34, // Opcode: VLUXSEG8EI64_V + /* 2991 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 3005 + /* 2996 */ MCD_OPC_CheckPredicate, + 6, + 8, + 54, + 0, // Skip to: 16833 + /* 3001 */ MCD_OPC_Decode, + 136, + 87, + 35, // Opcode: VLSSEG8E64_V + /* 3005 */ MCD_OPC_FilterValue, + 59, + 255, + 53, + 0, // Skip to: 16833 + /* 3010 */ MCD_OPC_CheckPredicate, + 6, + 250, + 53, + 0, // Skip to: 16833 + /* 3015 */ MCD_OPC_Decode, + 176, + 86, + 34, // Opcode: VLOXSEG8EI64_V + /* 3019 */ MCD_OPC_FilterValue, + 15, + 52, + 0, + 0, // Skip to: 3076 + /* 3024 */ MCD_OPC_ExtractField, + 7, + 13, // Inst{19-7} ... + /* 3027 */ MCD_OPC_FilterValue, + 0, + 28, + 0, + 0, // Skip to: 3060 + /* 3032 */ MCD_OPC_ExtractField, + 28, + 4, // Inst{31-28} ... + /* 3035 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 3044 + /* 3040 */ MCD_OPC_Decode, + 136, + 83, + 42, // Opcode: FENCE + /* 3044 */ MCD_OPC_FilterValue, + 8, + 216, + 53, + 0, // Skip to: 16833 + /* 3049 */ MCD_OPC_CheckField, + 20, + 8, + 51, + 209, + 53, + 0, // Skip to: 16833 + /* 3056 */ MCD_OPC_Decode, + 138, + 83, + 0, // Opcode: FENCE_TSO + /* 3060 */ MCD_OPC_FilterValue, + 32, + 200, + 53, + 0, // Skip to: 16833 + /* 3065 */ MCD_OPC_CheckField, + 20, + 12, + 0, + 193, + 53, + 0, // Skip to: 16833 + /* 3072 */ MCD_OPC_Decode, + 137, + 83, + 0, // Opcode: FENCE_I + /* 3076 */ MCD_OPC_FilterValue, + 19, + 1, + 2, + 0, // Skip to: 3594 + /* 3081 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 3084 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 3093 + /* 3089 */ MCD_OPC_Decode, + 163, + 81, + 31, // Opcode: ADDI + /* 3093 */ MCD_OPC_FilterValue, + 1, + 23, + 1, + 0, // Skip to: 3377 + /* 3098 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3101 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 3110 + /* 3106 */ MCD_OPC_Decode, + 163, + 84, + 43, // Opcode: SLLI + /* 3110 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 3131 + /* 3115 */ MCD_OPC_CheckPredicate, + 10, + 145, + 53, + 0, // Skip to: 16833 + /* 3120 */ MCD_OPC_CheckField, + 25, + 1, + 0, + 138, + 53, + 0, // Skip to: 16833 + /* 3127 */ MCD_OPC_Decode, + 160, + 84, + 44, // Opcode: SHFLI + /* 3131 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 3145 + /* 3136 */ MCD_OPC_CheckPredicate, + 11, + 124, + 53, + 0, // Skip to: 16833 + /* 3141 */ MCD_OPC_Decode, + 137, + 82, + 43, // Opcode: BSETI + /* 3145 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 3159 + /* 3150 */ MCD_OPC_CheckPredicate, + 11, + 110, + 53, + 0, // Skip to: 16833 + /* 3155 */ MCD_OPC_Decode, + 244, + 81, + 43, // Opcode: BCLRI + /* 3159 */ MCD_OPC_FilterValue, + 24, + 199, + 0, + 0, // Skip to: 3363 + /* 3164 */ MCD_OPC_ExtractField, + 20, + 6, // Inst{25-20} ... + /* 3167 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3181 + /* 3172 */ MCD_OPC_CheckPredicate, + 12, + 88, + 53, + 0, // Skip to: 16833 + /* 3177 */ MCD_OPC_Decode, + 141, + 82, + 45, // Opcode: CLZ + /* 3181 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3195 + /* 3186 */ MCD_OPC_CheckPredicate, + 12, + 74, + 53, + 0, // Skip to: 16833 + /* 3191 */ MCD_OPC_Decode, + 161, + 82, + 45, // Opcode: CTZ + /* 3195 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3209 + /* 3200 */ MCD_OPC_CheckPredicate, + 12, + 60, + 53, + 0, // Skip to: 16833 + /* 3205 */ MCD_OPC_Decode, + 145, + 82, + 45, // Opcode: CPOP + /* 3209 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3223 + /* 3214 */ MCD_OPC_CheckPredicate, + 13, + 46, + 53, + 0, // Skip to: 16833 + /* 3219 */ MCD_OPC_Decode, + 132, + 82, + 45, // Opcode: BMATFLIP + /* 3223 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 3237 + /* 3228 */ MCD_OPC_CheckPredicate, + 12, + 32, + 53, + 0, // Skip to: 16833 + /* 3233 */ MCD_OPC_Decode, + 149, + 84, + 45, // Opcode: SEXTB + /* 3237 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3251 + /* 3242 */ MCD_OPC_CheckPredicate, + 12, + 18, + 53, + 0, // Skip to: 16833 + /* 3247 */ MCD_OPC_Decode, + 150, + 84, + 45, // Opcode: SEXTH + /* 3251 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 3265 + /* 3256 */ MCD_OPC_CheckPredicate, + 14, + 4, + 53, + 0, // Skip to: 16833 + /* 3261 */ MCD_OPC_Decode, + 147, + 82, + 45, // Opcode: CRC32B + /* 3265 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 3279 + /* 3270 */ MCD_OPC_CheckPredicate, + 14, + 246, + 52, + 0, // Skip to: 16833 + /* 3275 */ MCD_OPC_Decode, + 153, + 82, + 45, // Opcode: CRC32H + /* 3279 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 3293 + /* 3284 */ MCD_OPC_CheckPredicate, + 14, + 232, + 52, + 0, // Skip to: 16833 + /* 3289 */ MCD_OPC_Decode, + 154, + 82, + 45, // Opcode: CRC32W + /* 3293 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 3307 + /* 3298 */ MCD_OPC_CheckPredicate, + 15, + 218, + 52, + 0, // Skip to: 16833 + /* 3303 */ MCD_OPC_Decode, + 152, + 82, + 45, // Opcode: CRC32D + /* 3307 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 3321 + /* 3312 */ MCD_OPC_CheckPredicate, + 14, + 204, + 52, + 0, // Skip to: 16833 + /* 3317 */ MCD_OPC_Decode, + 148, + 82, + 45, // Opcode: CRC32CB + /* 3321 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 3335 + /* 3326 */ MCD_OPC_CheckPredicate, + 14, + 190, + 52, + 0, // Skip to: 16833 + /* 3331 */ MCD_OPC_Decode, + 150, + 82, + 45, // Opcode: CRC32CH + /* 3335 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 3349 + /* 3340 */ MCD_OPC_CheckPredicate, + 14, + 176, + 52, + 0, // Skip to: 16833 + /* 3345 */ MCD_OPC_Decode, + 151, + 82, + 45, // Opcode: CRC32CW + /* 3349 */ MCD_OPC_FilterValue, + 27, + 167, + 52, + 0, // Skip to: 16833 + /* 3354 */ MCD_OPC_CheckPredicate, + 15, + 162, + 52, + 0, // Skip to: 16833 + /* 3359 */ MCD_OPC_Decode, + 149, + 82, + 45, // Opcode: CRC32CD + /* 3363 */ MCD_OPC_FilterValue, + 26, + 153, + 52, + 0, // Skip to: 16833 + /* 3368 */ MCD_OPC_CheckPredicate, + 11, + 148, + 52, + 0, // Skip to: 16833 + /* 3373 */ MCD_OPC_Decode, + 129, + 82, + 43, // Opcode: BINVI + /* 3377 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 3386 + /* 3382 */ MCD_OPC_Decode, + 168, + 84, + 31, // Opcode: SLTI + /* 3386 */ MCD_OPC_FilterValue, + 3, + 4, + 0, + 0, // Skip to: 3395 + /* 3391 */ MCD_OPC_Decode, + 169, + 84, + 31, // Opcode: SLTIU + /* 3395 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 3404 + /* 3400 */ MCD_OPC_Decode, + 250, + 89, + 31, // Opcode: XORI + /* 3404 */ MCD_OPC_FilterValue, + 5, + 167, + 0, + 0, // Skip to: 3576 + /* 3409 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 3412 */ MCD_OPC_FilterValue, + 0, + 145, + 0, + 0, // Skip to: 3562 + /* 3417 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 3420 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 3429 + /* 3425 */ MCD_OPC_Decode, + 177, + 84, + 43, // Opcode: SRLI + /* 3429 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 3450 + /* 3434 */ MCD_OPC_CheckPredicate, + 10, + 82, + 52, + 0, // Skip to: 16833 + /* 3439 */ MCD_OPC_CheckField, + 25, + 1, + 0, + 75, + 52, + 0, // Skip to: 16833 + /* 3446 */ MCD_OPC_Decode, + 185, + 84, + 44, // Opcode: UNSHFLI + /* 3450 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 3480 + /* 3455 */ MCD_OPC_CheckPredicate, + 16, + 11, + 0, + 0, // Skip to: 3471 + /* 3460 */ MCD_OPC_CheckField, + 20, + 6, + 7, + 4, + 0, + 0, // Skip to: 3471 + /* 3467 */ MCD_OPC_Decode, + 247, + 83, + 45, // Opcode: ORCB + /* 3471 */ MCD_OPC_CheckPredicate, + 10, + 45, + 52, + 0, // Skip to: 16833 + /* 3476 */ MCD_OPC_Decode, + 203, + 83, + 43, // Opcode: GORCI + /* 3480 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 3489 + /* 3485 */ MCD_OPC_Decode, + 172, + 84, + 43, // Opcode: SRAI + /* 3489 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 3503 + /* 3494 */ MCD_OPC_CheckPredicate, + 11, + 22, + 52, + 0, // Skip to: 16833 + /* 3499 */ MCD_OPC_Decode, + 251, + 81, + 43, // Opcode: BEXTI + /* 3503 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 3517 + /* 3508 */ MCD_OPC_CheckPredicate, + 16, + 8, + 52, + 0, // Skip to: 16833 + /* 3513 */ MCD_OPC_Decode, + 136, + 84, + 43, // Opcode: RORI + /* 3517 */ MCD_OPC_FilterValue, + 13, + 255, + 51, + 0, // Skip to: 16833 + /* 3522 */ MCD_OPC_ExtractField, + 20, + 6, // Inst{25-20} ... + /* 3525 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 3539 + /* 3530 */ MCD_OPC_CheckPredicate, + 17, + 18, + 0, + 0, // Skip to: 3553 + /* 3535 */ MCD_OPC_Decode, + 131, + 84, + 45, // Opcode: REV8_RV32 + /* 3539 */ MCD_OPC_FilterValue, + 56, + 9, + 0, + 0, // Skip to: 3553 + /* 3544 */ MCD_OPC_CheckPredicate, + 18, + 4, + 0, + 0, // Skip to: 3553 + /* 3549 */ MCD_OPC_Decode, + 132, + 84, + 45, // Opcode: REV8_RV64 + /* 3553 */ MCD_OPC_CheckPredicate, + 10, + 219, + 51, + 0, // Skip to: 16833 + /* 3558 */ MCD_OPC_Decode, + 207, + 83, + 43, // Opcode: GREVI + /* 3562 */ MCD_OPC_FilterValue, + 1, + 210, + 51, + 0, // Skip to: 16833 + /* 3567 */ MCD_OPC_CheckPredicate, + 19, + 205, + 51, + 0, // Skip to: 16833 + /* 3572 */ MCD_OPC_Decode, + 195, + 83, + 46, // Opcode: FSRI + /* 3576 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 3585 + /* 3581 */ MCD_OPC_Decode, + 248, + 83, + 31, // Opcode: ORI + /* 3585 */ MCD_OPC_FilterValue, + 7, + 187, + 51, + 0, // Skip to: 16833 + /* 3590 */ MCD_OPC_Decode, + 240, + 81, + 31, // Opcode: ANDI + /* 3594 */ MCD_OPC_FilterValue, + 23, + 4, + 0, + 0, // Skip to: 3603 + /* 3599 */ MCD_OPC_Decode, + 242, + 81, + 47, // Opcode: AUIPC + /* 3603 */ MCD_OPC_FilterValue, + 27, + 210, + 0, + 0, // Skip to: 3818 + /* 3608 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 3611 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3625 + /* 3616 */ MCD_OPC_CheckPredicate, + 4, + 156, + 51, + 0, // Skip to: 16833 + /* 3621 */ MCD_OPC_Decode, + 164, + 81, + 31, // Opcode: ADDIW + /* 3625 */ MCD_OPC_FilterValue, + 1, + 88, + 0, + 0, // Skip to: 3718 + /* 3630 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3633 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3654 + /* 3638 */ MCD_OPC_CheckPredicate, + 4, + 134, + 51, + 0, // Skip to: 16833 + /* 3643 */ MCD_OPC_CheckField, + 25, + 1, + 0, + 127, + 51, + 0, // Skip to: 16833 + /* 3650 */ MCD_OPC_Decode, + 165, + 84, + 44, // Opcode: SLLIW + /* 3654 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3668 + /* 3659 */ MCD_OPC_CheckPredicate, + 20, + 113, + 51, + 0, // Skip to: 16833 + /* 3664 */ MCD_OPC_Decode, + 164, + 84, + 43, // Opcode: SLLIUW + /* 3668 */ MCD_OPC_FilterValue, + 24, + 104, + 51, + 0, // Skip to: 16833 + /* 3673 */ MCD_OPC_ExtractField, + 20, + 6, // Inst{25-20} ... + /* 3676 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3690 + /* 3681 */ MCD_OPC_CheckPredicate, + 21, + 91, + 51, + 0, // Skip to: 16833 + /* 3686 */ MCD_OPC_Decode, + 142, + 82, + 45, // Opcode: CLZW + /* 3690 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3704 + /* 3695 */ MCD_OPC_CheckPredicate, + 21, + 77, + 51, + 0, // Skip to: 16833 + /* 3700 */ MCD_OPC_Decode, + 162, + 82, + 45, // Opcode: CTZW + /* 3704 */ MCD_OPC_FilterValue, + 2, + 68, + 51, + 0, // Skip to: 16833 + /* 3709 */ MCD_OPC_CheckPredicate, + 21, + 63, + 51, + 0, // Skip to: 16833 + /* 3714 */ MCD_OPC_Decode, + 146, + 82, + 45, // Opcode: CPOPW + /* 3718 */ MCD_OPC_FilterValue, + 5, + 54, + 51, + 0, // Skip to: 16833 + /* 3723 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 3726 */ MCD_OPC_FilterValue, + 0, + 73, + 0, + 0, // Skip to: 3804 + /* 3731 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 3734 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3748 + /* 3739 */ MCD_OPC_CheckPredicate, + 4, + 33, + 51, + 0, // Skip to: 16833 + /* 3744 */ MCD_OPC_Decode, + 178, + 84, + 44, // Opcode: SRLIW + /* 3748 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 3762 + /* 3753 */ MCD_OPC_CheckPredicate, + 22, + 19, + 51, + 0, // Skip to: 16833 + /* 3758 */ MCD_OPC_Decode, + 204, + 83, + 44, // Opcode: GORCIW + /* 3762 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 3776 + /* 3767 */ MCD_OPC_CheckPredicate, + 4, + 5, + 51, + 0, // Skip to: 16833 + /* 3772 */ MCD_OPC_Decode, + 173, + 84, + 44, // Opcode: SRAIW + /* 3776 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 3790 + /* 3781 */ MCD_OPC_CheckPredicate, + 18, + 247, + 50, + 0, // Skip to: 16833 + /* 3786 */ MCD_OPC_Decode, + 137, + 84, + 44, // Opcode: RORIW + /* 3790 */ MCD_OPC_FilterValue, + 13, + 238, + 50, + 0, // Skip to: 16833 + /* 3795 */ MCD_OPC_CheckPredicate, + 22, + 233, + 50, + 0, // Skip to: 16833 + /* 3800 */ MCD_OPC_Decode, + 208, + 83, + 44, // Opcode: GREVIW + /* 3804 */ MCD_OPC_FilterValue, + 2, + 224, + 50, + 0, // Skip to: 16833 + /* 3809 */ MCD_OPC_CheckPredicate, + 23, + 219, + 50, + 0, // Skip to: 16833 + /* 3814 */ MCD_OPC_Decode, + 196, + 83, + 48, // Opcode: FSRIW + /* 3818 */ MCD_OPC_FilterValue, + 35, + 44, + 0, + 0, // Skip to: 3867 + /* 3823 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 3826 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 3835 + /* 3831 */ MCD_OPC_Decode, + 139, + 84, + 49, // Opcode: SB + /* 3835 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 3844 + /* 3840 */ MCD_OPC_Decode, + 152, + 84, + 49, // Opcode: SH + /* 3844 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 3853 + /* 3849 */ MCD_OPC_Decode, + 182, + 84, + 49, // Opcode: SW + /* 3853 */ MCD_OPC_FilterValue, + 3, + 175, + 50, + 0, // Skip to: 16833 + /* 3858 */ MCD_OPC_CheckPredicate, + 4, + 170, + 50, + 0, // Skip to: 16833 + /* 3863 */ MCD_OPC_Decode, + 148, + 84, + 49, // Opcode: SD + /* 3867 */ MCD_OPC_FilterValue, + 39, + 154, + 8, + 0, // Skip to: 6074 + /* 3872 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 3875 */ MCD_OPC_FilterValue, + 0, + 104, + 2, + 0, // Skip to: 4496 + /* 3880 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 3883 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 3947 + /* 3888 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 3891 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 3905 + /* 3896 */ MCD_OPC_CheckPredicate, + 5, + 132, + 50, + 0, // Skip to: 16833 + /* 3901 */ MCD_OPC_Decode, + 177, + 88, + 32, // Opcode: VSE8_V + /* 3905 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 3926 + /* 3910 */ MCD_OPC_CheckPredicate, + 5, + 118, + 50, + 0, // Skip to: 16833 + /* 3915 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 111, + 50, + 0, // Skip to: 16833 + /* 3922 */ MCD_OPC_Decode, + 162, + 88, + 33, // Opcode: VS1R_V + /* 3926 */ MCD_OPC_FilterValue, + 11, + 102, + 50, + 0, // Skip to: 16833 + /* 3931 */ MCD_OPC_CheckPredicate, + 5, + 97, + 50, + 0, // Skip to: 16833 + /* 3936 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 90, + 50, + 0, // Skip to: 16833 + /* 3943 */ MCD_OPC_Decode, + 195, + 88, + 33, // Opcode: VSM_V + /* 3947 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3961 + /* 3952 */ MCD_OPC_CheckPredicate, + 5, + 76, + 50, + 0, // Skip to: 16833 + /* 3957 */ MCD_OPC_Decode, + 181, + 89, + 34, // Opcode: VSUXEI8_V + /* 3961 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 3975 + /* 3966 */ MCD_OPC_CheckPredicate, + 5, + 62, + 50, + 0, // Skip to: 16833 + /* 3971 */ MCD_OPC_Decode, + 237, + 88, + 35, // Opcode: VSSE8_V + /* 3975 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 3989 + /* 3980 */ MCD_OPC_CheckPredicate, + 5, + 48, + 50, + 0, // Skip to: 16833 + /* 3985 */ MCD_OPC_Decode, + 199, + 88, + 34, // Opcode: VSOXEI8_V + /* 3989 */ MCD_OPC_FilterValue, + 8, + 38, + 0, + 0, // Skip to: 4032 + /* 3994 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 3997 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4011 + /* 4002 */ MCD_OPC_CheckPredicate, + 6, + 26, + 50, + 0, // Skip to: 16833 + /* 4007 */ MCD_OPC_Decode, + 241, + 88, + 32, // Opcode: VSSEG2E8_V + /* 4011 */ MCD_OPC_FilterValue, + 8, + 17, + 50, + 0, // Skip to: 16833 + /* 4016 */ MCD_OPC_CheckPredicate, + 5, + 12, + 50, + 0, // Skip to: 16833 + /* 4021 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 5, + 50, + 0, // Skip to: 16833 + /* 4028 */ MCD_OPC_Decode, + 163, + 88, + 36, // Opcode: VS2R_V + /* 4032 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 4046 + /* 4037 */ MCD_OPC_CheckPredicate, + 6, + 247, + 49, + 0, // Skip to: 16833 + /* 4042 */ MCD_OPC_Decode, + 185, + 89, + 34, // Opcode: VSUXSEG2EI8_V + /* 4046 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 4060 + /* 4051 */ MCD_OPC_CheckPredicate, + 6, + 233, + 49, + 0, // Skip to: 16833 + /* 4056 */ MCD_OPC_Decode, + 147, + 89, + 35, // Opcode: VSSSEG2E8_V + /* 4060 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 4074 + /* 4065 */ MCD_OPC_CheckPredicate, + 6, + 219, + 49, + 0, // Skip to: 16833 + /* 4070 */ MCD_OPC_Decode, + 203, + 88, + 34, // Opcode: VSOXSEG2EI8_V + /* 4074 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 4095 + /* 4079 */ MCD_OPC_CheckPredicate, + 6, + 205, + 49, + 0, // Skip to: 16833 + /* 4084 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 198, + 49, + 0, // Skip to: 16833 + /* 4091 */ MCD_OPC_Decode, + 245, + 88, + 32, // Opcode: VSSEG3E8_V + /* 4095 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 4109 + /* 4100 */ MCD_OPC_CheckPredicate, + 6, + 184, + 49, + 0, // Skip to: 16833 + /* 4105 */ MCD_OPC_Decode, + 189, + 89, + 34, // Opcode: VSUXSEG3EI8_V + /* 4109 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 4123 + /* 4114 */ MCD_OPC_CheckPredicate, + 6, + 170, + 49, + 0, // Skip to: 16833 + /* 4119 */ MCD_OPC_Decode, + 151, + 89, + 35, // Opcode: VSSSEG3E8_V + /* 4123 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 4137 + /* 4128 */ MCD_OPC_CheckPredicate, + 6, + 156, + 49, + 0, // Skip to: 16833 + /* 4133 */ MCD_OPC_Decode, + 207, + 88, + 34, // Opcode: VSOXSEG3EI8_V + /* 4137 */ MCD_OPC_FilterValue, + 24, + 38, + 0, + 0, // Skip to: 4180 + /* 4142 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 4145 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4159 + /* 4150 */ MCD_OPC_CheckPredicate, + 6, + 134, + 49, + 0, // Skip to: 16833 + /* 4155 */ MCD_OPC_Decode, + 249, + 88, + 32, // Opcode: VSSEG4E8_V + /* 4159 */ MCD_OPC_FilterValue, + 8, + 125, + 49, + 0, // Skip to: 16833 + /* 4164 */ MCD_OPC_CheckPredicate, + 5, + 120, + 49, + 0, // Skip to: 16833 + /* 4169 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 113, + 49, + 0, // Skip to: 16833 + /* 4176 */ MCD_OPC_Decode, + 164, + 88, + 37, // Opcode: VS4R_V + /* 4180 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 4194 + /* 4185 */ MCD_OPC_CheckPredicate, + 6, + 99, + 49, + 0, // Skip to: 16833 + /* 4190 */ MCD_OPC_Decode, + 193, + 89, + 34, // Opcode: VSUXSEG4EI8_V + /* 4194 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 4208 + /* 4199 */ MCD_OPC_CheckPredicate, + 6, + 85, + 49, + 0, // Skip to: 16833 + /* 4204 */ MCD_OPC_Decode, + 155, + 89, + 35, // Opcode: VSSSEG4E8_V + /* 4208 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 4222 + /* 4213 */ MCD_OPC_CheckPredicate, + 6, + 71, + 49, + 0, // Skip to: 16833 + /* 4218 */ MCD_OPC_Decode, + 211, + 88, + 34, // Opcode: VSOXSEG4EI8_V + /* 4222 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 4243 + /* 4227 */ MCD_OPC_CheckPredicate, + 6, + 57, + 49, + 0, // Skip to: 16833 + /* 4232 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 50, + 49, + 0, // Skip to: 16833 + /* 4239 */ MCD_OPC_Decode, + 253, + 88, + 32, // Opcode: VSSEG5E8_V + /* 4243 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 4257 + /* 4248 */ MCD_OPC_CheckPredicate, + 6, + 36, + 49, + 0, // Skip to: 16833 + /* 4253 */ MCD_OPC_Decode, + 197, + 89, + 34, // Opcode: VSUXSEG5EI8_V + /* 4257 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 4271 + /* 4262 */ MCD_OPC_CheckPredicate, + 6, + 22, + 49, + 0, // Skip to: 16833 + /* 4267 */ MCD_OPC_Decode, + 159, + 89, + 35, // Opcode: VSSSEG5E8_V + /* 4271 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 4285 + /* 4276 */ MCD_OPC_CheckPredicate, + 6, + 8, + 49, + 0, // Skip to: 16833 + /* 4281 */ MCD_OPC_Decode, + 215, + 88, + 34, // Opcode: VSOXSEG5EI8_V + /* 4285 */ MCD_OPC_FilterValue, + 40, + 16, + 0, + 0, // Skip to: 4306 + /* 4290 */ MCD_OPC_CheckPredicate, + 6, + 250, + 48, + 0, // Skip to: 16833 + /* 4295 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 243, + 48, + 0, // Skip to: 16833 + /* 4302 */ MCD_OPC_Decode, + 129, + 89, + 32, // Opcode: VSSEG6E8_V + /* 4306 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 4320 + /* 4311 */ MCD_OPC_CheckPredicate, + 6, + 229, + 48, + 0, // Skip to: 16833 + /* 4316 */ MCD_OPC_Decode, + 201, + 89, + 34, // Opcode: VSUXSEG6EI8_V + /* 4320 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 4334 + /* 4325 */ MCD_OPC_CheckPredicate, + 6, + 215, + 48, + 0, // Skip to: 16833 + /* 4330 */ MCD_OPC_Decode, + 163, + 89, + 35, // Opcode: VSSSEG6E8_V + /* 4334 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 4348 + /* 4339 */ MCD_OPC_CheckPredicate, + 6, + 201, + 48, + 0, // Skip to: 16833 + /* 4344 */ MCD_OPC_Decode, + 219, + 88, + 34, // Opcode: VSOXSEG6EI8_V + /* 4348 */ MCD_OPC_FilterValue, + 48, + 16, + 0, + 0, // Skip to: 4369 + /* 4353 */ MCD_OPC_CheckPredicate, + 6, + 187, + 48, + 0, // Skip to: 16833 + /* 4358 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 180, + 48, + 0, // Skip to: 16833 + /* 4365 */ MCD_OPC_Decode, + 133, + 89, + 32, // Opcode: VSSEG7E8_V + /* 4369 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 4383 + /* 4374 */ MCD_OPC_CheckPredicate, + 6, + 166, + 48, + 0, // Skip to: 16833 + /* 4379 */ MCD_OPC_Decode, + 205, + 89, + 34, // Opcode: VSUXSEG7EI8_V + /* 4383 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 4397 + /* 4388 */ MCD_OPC_CheckPredicate, + 6, + 152, + 48, + 0, // Skip to: 16833 + /* 4393 */ MCD_OPC_Decode, + 167, + 89, + 35, // Opcode: VSSSEG7E8_V + /* 4397 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 4411 + /* 4402 */ MCD_OPC_CheckPredicate, + 6, + 138, + 48, + 0, // Skip to: 16833 + /* 4407 */ MCD_OPC_Decode, + 223, + 88, + 34, // Opcode: VSOXSEG7EI8_V + /* 4411 */ MCD_OPC_FilterValue, + 56, + 38, + 0, + 0, // Skip to: 4454 + /* 4416 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 4419 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4433 + /* 4424 */ MCD_OPC_CheckPredicate, + 6, + 116, + 48, + 0, // Skip to: 16833 + /* 4429 */ MCD_OPC_Decode, + 137, + 89, + 32, // Opcode: VSSEG8E8_V + /* 4433 */ MCD_OPC_FilterValue, + 8, + 107, + 48, + 0, // Skip to: 16833 + /* 4438 */ MCD_OPC_CheckPredicate, + 5, + 102, + 48, + 0, // Skip to: 16833 + /* 4443 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 95, + 48, + 0, // Skip to: 16833 + /* 4450 */ MCD_OPC_Decode, + 165, + 88, + 38, // Opcode: VS8R_V + /* 4454 */ MCD_OPC_FilterValue, + 57, + 9, + 0, + 0, // Skip to: 4468 + /* 4459 */ MCD_OPC_CheckPredicate, + 6, + 81, + 48, + 0, // Skip to: 16833 + /* 4464 */ MCD_OPC_Decode, + 209, + 89, + 34, // Opcode: VSUXSEG8EI8_V + /* 4468 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 4482 + /* 4473 */ MCD_OPC_CheckPredicate, + 6, + 67, + 48, + 0, // Skip to: 16833 + /* 4478 */ MCD_OPC_Decode, + 171, + 89, + 35, // Opcode: VSSSEG8E8_V + /* 4482 */ MCD_OPC_FilterValue, + 59, + 58, + 48, + 0, // Skip to: 16833 + /* 4487 */ MCD_OPC_CheckPredicate, + 6, + 53, + 48, + 0, // Skip to: 16833 + /* 4492 */ MCD_OPC_Decode, + 227, + 88, + 34, // Opcode: VSOXSEG8EI8_V + /* 4496 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4510 + /* 4501 */ MCD_OPC_CheckPredicate, + 7, + 39, + 48, + 0, // Skip to: 16833 + /* 4506 */ MCD_OPC_Decode, + 188, + 83, + 50, // Opcode: FSH + /* 4510 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4524 + /* 4515 */ MCD_OPC_CheckPredicate, + 8, + 25, + 48, + 0, // Skip to: 16833 + /* 4520 */ MCD_OPC_Decode, + 201, + 83, + 51, // Opcode: FSW + /* 4524 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 4538 + /* 4529 */ MCD_OPC_CheckPredicate, + 9, + 11, + 48, + 0, // Skip to: 16833 + /* 4534 */ MCD_OPC_Decode, + 178, + 83, + 52, // Opcode: FSD + /* 4538 */ MCD_OPC_FilterValue, + 5, + 251, + 1, + 0, // Skip to: 5050 + /* 4543 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 4546 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 4567 + /* 4551 */ MCD_OPC_CheckPredicate, + 5, + 245, + 47, + 0, // Skip to: 16833 + /* 4556 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 238, + 47, + 0, // Skip to: 16833 + /* 4563 */ MCD_OPC_Decode, + 174, + 88, + 32, // Opcode: VSE16_V + /* 4567 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4581 + /* 4572 */ MCD_OPC_CheckPredicate, + 5, + 224, + 47, + 0, // Skip to: 16833 + /* 4577 */ MCD_OPC_Decode, + 178, + 89, + 34, // Opcode: VSUXEI16_V + /* 4581 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4595 + /* 4586 */ MCD_OPC_CheckPredicate, + 5, + 210, + 47, + 0, // Skip to: 16833 + /* 4591 */ MCD_OPC_Decode, + 234, + 88, + 35, // Opcode: VSSE16_V + /* 4595 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 4609 + /* 4600 */ MCD_OPC_CheckPredicate, + 5, + 196, + 47, + 0, // Skip to: 16833 + /* 4605 */ MCD_OPC_Decode, + 196, + 88, + 34, // Opcode: VSOXEI16_V + /* 4609 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 4630 + /* 4614 */ MCD_OPC_CheckPredicate, + 6, + 182, + 47, + 0, // Skip to: 16833 + /* 4619 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 175, + 47, + 0, // Skip to: 16833 + /* 4626 */ MCD_OPC_Decode, + 238, + 88, + 32, // Opcode: VSSEG2E16_V + /* 4630 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 4644 + /* 4635 */ MCD_OPC_CheckPredicate, + 6, + 161, + 47, + 0, // Skip to: 16833 + /* 4640 */ MCD_OPC_Decode, + 182, + 89, + 34, // Opcode: VSUXSEG2EI16_V + /* 4644 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 4658 + /* 4649 */ MCD_OPC_CheckPredicate, + 6, + 147, + 47, + 0, // Skip to: 16833 + /* 4654 */ MCD_OPC_Decode, + 144, + 89, + 35, // Opcode: VSSSEG2E16_V + /* 4658 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 4672 + /* 4663 */ MCD_OPC_CheckPredicate, + 6, + 133, + 47, + 0, // Skip to: 16833 + /* 4668 */ MCD_OPC_Decode, + 200, + 88, + 34, // Opcode: VSOXSEG2EI16_V + /* 4672 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 4693 + /* 4677 */ MCD_OPC_CheckPredicate, + 6, + 119, + 47, + 0, // Skip to: 16833 + /* 4682 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 112, + 47, + 0, // Skip to: 16833 + /* 4689 */ MCD_OPC_Decode, + 242, + 88, + 32, // Opcode: VSSEG3E16_V + /* 4693 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 4707 + /* 4698 */ MCD_OPC_CheckPredicate, + 6, + 98, + 47, + 0, // Skip to: 16833 + /* 4703 */ MCD_OPC_Decode, + 186, + 89, + 34, // Opcode: VSUXSEG3EI16_V + /* 4707 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 4721 + /* 4712 */ MCD_OPC_CheckPredicate, + 6, + 84, + 47, + 0, // Skip to: 16833 + /* 4717 */ MCD_OPC_Decode, + 148, + 89, + 35, // Opcode: VSSSEG3E16_V + /* 4721 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 4735 + /* 4726 */ MCD_OPC_CheckPredicate, + 6, + 70, + 47, + 0, // Skip to: 16833 + /* 4731 */ MCD_OPC_Decode, + 204, + 88, + 34, // Opcode: VSOXSEG3EI16_V + /* 4735 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 4756 + /* 4740 */ MCD_OPC_CheckPredicate, + 6, + 56, + 47, + 0, // Skip to: 16833 + /* 4745 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 49, + 47, + 0, // Skip to: 16833 + /* 4752 */ MCD_OPC_Decode, + 246, + 88, + 32, // Opcode: VSSEG4E16_V + /* 4756 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 4770 + /* 4761 */ MCD_OPC_CheckPredicate, + 6, + 35, + 47, + 0, // Skip to: 16833 + /* 4766 */ MCD_OPC_Decode, + 190, + 89, + 34, // Opcode: VSUXSEG4EI16_V + /* 4770 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 4784 + /* 4775 */ MCD_OPC_CheckPredicate, + 6, + 21, + 47, + 0, // Skip to: 16833 + /* 4780 */ MCD_OPC_Decode, + 152, + 89, + 35, // Opcode: VSSSEG4E16_V + /* 4784 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 4798 + /* 4789 */ MCD_OPC_CheckPredicate, + 6, + 7, + 47, + 0, // Skip to: 16833 + /* 4794 */ MCD_OPC_Decode, + 208, + 88, + 34, // Opcode: VSOXSEG4EI16_V + /* 4798 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 4819 + /* 4803 */ MCD_OPC_CheckPredicate, + 6, + 249, + 46, + 0, // Skip to: 16833 + /* 4808 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 242, + 46, + 0, // Skip to: 16833 + /* 4815 */ MCD_OPC_Decode, + 250, + 88, + 32, // Opcode: VSSEG5E16_V + /* 4819 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 4833 + /* 4824 */ MCD_OPC_CheckPredicate, + 6, + 228, + 46, + 0, // Skip to: 16833 + /* 4829 */ MCD_OPC_Decode, + 194, + 89, + 34, // Opcode: VSUXSEG5EI16_V + /* 4833 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 4847 + /* 4838 */ MCD_OPC_CheckPredicate, + 6, + 214, + 46, + 0, // Skip to: 16833 + /* 4843 */ MCD_OPC_Decode, + 156, + 89, + 35, // Opcode: VSSSEG5E16_V + /* 4847 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 4861 + /* 4852 */ MCD_OPC_CheckPredicate, + 6, + 200, + 46, + 0, // Skip to: 16833 + /* 4857 */ MCD_OPC_Decode, + 212, + 88, + 34, // Opcode: VSOXSEG5EI16_V + /* 4861 */ MCD_OPC_FilterValue, + 40, + 16, + 0, + 0, // Skip to: 4882 + /* 4866 */ MCD_OPC_CheckPredicate, + 6, + 186, + 46, + 0, // Skip to: 16833 + /* 4871 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 179, + 46, + 0, // Skip to: 16833 + /* 4878 */ MCD_OPC_Decode, + 254, + 88, + 32, // Opcode: VSSEG6E16_V + /* 4882 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 4896 + /* 4887 */ MCD_OPC_CheckPredicate, + 6, + 165, + 46, + 0, // Skip to: 16833 + /* 4892 */ MCD_OPC_Decode, + 198, + 89, + 34, // Opcode: VSUXSEG6EI16_V + /* 4896 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 4910 + /* 4901 */ MCD_OPC_CheckPredicate, + 6, + 151, + 46, + 0, // Skip to: 16833 + /* 4906 */ MCD_OPC_Decode, + 160, + 89, + 35, // Opcode: VSSSEG6E16_V + /* 4910 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 4924 + /* 4915 */ MCD_OPC_CheckPredicate, + 6, + 137, + 46, + 0, // Skip to: 16833 + /* 4920 */ MCD_OPC_Decode, + 216, + 88, + 34, // Opcode: VSOXSEG6EI16_V + /* 4924 */ MCD_OPC_FilterValue, + 48, + 16, + 0, + 0, // Skip to: 4945 + /* 4929 */ MCD_OPC_CheckPredicate, + 6, + 123, + 46, + 0, // Skip to: 16833 + /* 4934 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 116, + 46, + 0, // Skip to: 16833 + /* 4941 */ MCD_OPC_Decode, + 130, + 89, + 32, // Opcode: VSSEG7E16_V + /* 4945 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 4959 + /* 4950 */ MCD_OPC_CheckPredicate, + 6, + 102, + 46, + 0, // Skip to: 16833 + /* 4955 */ MCD_OPC_Decode, + 202, + 89, + 34, // Opcode: VSUXSEG7EI16_V + /* 4959 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 4973 + /* 4964 */ MCD_OPC_CheckPredicate, + 6, + 88, + 46, + 0, // Skip to: 16833 + /* 4969 */ MCD_OPC_Decode, + 164, + 89, + 35, // Opcode: VSSSEG7E16_V + /* 4973 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 4987 + /* 4978 */ MCD_OPC_CheckPredicate, + 6, + 74, + 46, + 0, // Skip to: 16833 + /* 4983 */ MCD_OPC_Decode, + 220, + 88, + 34, // Opcode: VSOXSEG7EI16_V + /* 4987 */ MCD_OPC_FilterValue, + 56, + 16, + 0, + 0, // Skip to: 5008 + /* 4992 */ MCD_OPC_CheckPredicate, + 6, + 60, + 46, + 0, // Skip to: 16833 + /* 4997 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 53, + 46, + 0, // Skip to: 16833 + /* 5004 */ MCD_OPC_Decode, + 134, + 89, + 32, // Opcode: VSSEG8E16_V + /* 5008 */ MCD_OPC_FilterValue, + 57, + 9, + 0, + 0, // Skip to: 5022 + /* 5013 */ MCD_OPC_CheckPredicate, + 6, + 39, + 46, + 0, // Skip to: 16833 + /* 5018 */ MCD_OPC_Decode, + 206, + 89, + 34, // Opcode: VSUXSEG8EI16_V + /* 5022 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 5036 + /* 5027 */ MCD_OPC_CheckPredicate, + 6, + 25, + 46, + 0, // Skip to: 16833 + /* 5032 */ MCD_OPC_Decode, + 168, + 89, + 35, // Opcode: VSSSEG8E16_V + /* 5036 */ MCD_OPC_FilterValue, + 59, + 16, + 46, + 0, // Skip to: 16833 + /* 5041 */ MCD_OPC_CheckPredicate, + 6, + 11, + 46, + 0, // Skip to: 16833 + /* 5046 */ MCD_OPC_Decode, + 224, + 88, + 34, // Opcode: VSOXSEG8EI16_V + /* 5050 */ MCD_OPC_FilterValue, + 6, + 251, + 1, + 0, // Skip to: 5562 + /* 5055 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 5058 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 5079 + /* 5063 */ MCD_OPC_CheckPredicate, + 5, + 245, + 45, + 0, // Skip to: 16833 + /* 5068 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 238, + 45, + 0, // Skip to: 16833 + /* 5075 */ MCD_OPC_Decode, + 175, + 88, + 32, // Opcode: VSE32_V + /* 5079 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5093 + /* 5084 */ MCD_OPC_CheckPredicate, + 5, + 224, + 45, + 0, // Skip to: 16833 + /* 5089 */ MCD_OPC_Decode, + 179, + 89, + 34, // Opcode: VSUXEI32_V + /* 5093 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5107 + /* 5098 */ MCD_OPC_CheckPredicate, + 5, + 210, + 45, + 0, // Skip to: 16833 + /* 5103 */ MCD_OPC_Decode, + 235, + 88, + 35, // Opcode: VSSE32_V + /* 5107 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 5121 + /* 5112 */ MCD_OPC_CheckPredicate, + 5, + 196, + 45, + 0, // Skip to: 16833 + /* 5117 */ MCD_OPC_Decode, + 197, + 88, + 34, // Opcode: VSOXEI32_V + /* 5121 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 5142 + /* 5126 */ MCD_OPC_CheckPredicate, + 6, + 182, + 45, + 0, // Skip to: 16833 + /* 5131 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 175, + 45, + 0, // Skip to: 16833 + /* 5138 */ MCD_OPC_Decode, + 239, + 88, + 32, // Opcode: VSSEG2E32_V + /* 5142 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 5156 + /* 5147 */ MCD_OPC_CheckPredicate, + 6, + 161, + 45, + 0, // Skip to: 16833 + /* 5152 */ MCD_OPC_Decode, + 183, + 89, + 34, // Opcode: VSUXSEG2EI32_V + /* 5156 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 5170 + /* 5161 */ MCD_OPC_CheckPredicate, + 6, + 147, + 45, + 0, // Skip to: 16833 + /* 5166 */ MCD_OPC_Decode, + 145, + 89, + 35, // Opcode: VSSSEG2E32_V + /* 5170 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 5184 + /* 5175 */ MCD_OPC_CheckPredicate, + 6, + 133, + 45, + 0, // Skip to: 16833 + /* 5180 */ MCD_OPC_Decode, + 201, + 88, + 34, // Opcode: VSOXSEG2EI32_V + /* 5184 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 5205 + /* 5189 */ MCD_OPC_CheckPredicate, + 6, + 119, + 45, + 0, // Skip to: 16833 + /* 5194 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 112, + 45, + 0, // Skip to: 16833 + /* 5201 */ MCD_OPC_Decode, + 243, + 88, + 32, // Opcode: VSSEG3E32_V + /* 5205 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 5219 + /* 5210 */ MCD_OPC_CheckPredicate, + 6, + 98, + 45, + 0, // Skip to: 16833 + /* 5215 */ MCD_OPC_Decode, + 187, + 89, + 34, // Opcode: VSUXSEG3EI32_V + /* 5219 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 5233 + /* 5224 */ MCD_OPC_CheckPredicate, + 6, + 84, + 45, + 0, // Skip to: 16833 + /* 5229 */ MCD_OPC_Decode, + 149, + 89, + 35, // Opcode: VSSSEG3E32_V + /* 5233 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 5247 + /* 5238 */ MCD_OPC_CheckPredicate, + 6, + 70, + 45, + 0, // Skip to: 16833 + /* 5243 */ MCD_OPC_Decode, + 205, + 88, + 34, // Opcode: VSOXSEG3EI32_V + /* 5247 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 5268 + /* 5252 */ MCD_OPC_CheckPredicate, + 6, + 56, + 45, + 0, // Skip to: 16833 + /* 5257 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 49, + 45, + 0, // Skip to: 16833 + /* 5264 */ MCD_OPC_Decode, + 247, + 88, + 32, // Opcode: VSSEG4E32_V + /* 5268 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 5282 + /* 5273 */ MCD_OPC_CheckPredicate, + 6, + 35, + 45, + 0, // Skip to: 16833 + /* 5278 */ MCD_OPC_Decode, + 191, + 89, + 34, // Opcode: VSUXSEG4EI32_V + /* 5282 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 5296 + /* 5287 */ MCD_OPC_CheckPredicate, + 6, + 21, + 45, + 0, // Skip to: 16833 + /* 5292 */ MCD_OPC_Decode, + 153, + 89, + 35, // Opcode: VSSSEG4E32_V + /* 5296 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 5310 + /* 5301 */ MCD_OPC_CheckPredicate, + 6, + 7, + 45, + 0, // Skip to: 16833 + /* 5306 */ MCD_OPC_Decode, + 209, + 88, + 34, // Opcode: VSOXSEG4EI32_V + /* 5310 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 5331 + /* 5315 */ MCD_OPC_CheckPredicate, + 6, + 249, + 44, + 0, // Skip to: 16833 + /* 5320 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 242, + 44, + 0, // Skip to: 16833 + /* 5327 */ MCD_OPC_Decode, + 251, + 88, + 32, // Opcode: VSSEG5E32_V + /* 5331 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 5345 + /* 5336 */ MCD_OPC_CheckPredicate, + 6, + 228, + 44, + 0, // Skip to: 16833 + /* 5341 */ MCD_OPC_Decode, + 195, + 89, + 34, // Opcode: VSUXSEG5EI32_V + /* 5345 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 5359 + /* 5350 */ MCD_OPC_CheckPredicate, + 6, + 214, + 44, + 0, // Skip to: 16833 + /* 5355 */ MCD_OPC_Decode, + 157, + 89, + 35, // Opcode: VSSSEG5E32_V + /* 5359 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 5373 + /* 5364 */ MCD_OPC_CheckPredicate, + 6, + 200, + 44, + 0, // Skip to: 16833 + /* 5369 */ MCD_OPC_Decode, + 213, + 88, + 34, // Opcode: VSOXSEG5EI32_V + /* 5373 */ MCD_OPC_FilterValue, + 40, + 16, + 0, + 0, // Skip to: 5394 + /* 5378 */ MCD_OPC_CheckPredicate, + 6, + 186, + 44, + 0, // Skip to: 16833 + /* 5383 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 179, + 44, + 0, // Skip to: 16833 + /* 5390 */ MCD_OPC_Decode, + 255, + 88, + 32, // Opcode: VSSEG6E32_V + /* 5394 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 5408 + /* 5399 */ MCD_OPC_CheckPredicate, + 6, + 165, + 44, + 0, // Skip to: 16833 + /* 5404 */ MCD_OPC_Decode, + 199, + 89, + 34, // Opcode: VSUXSEG6EI32_V + /* 5408 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 5422 + /* 5413 */ MCD_OPC_CheckPredicate, + 6, + 151, + 44, + 0, // Skip to: 16833 + /* 5418 */ MCD_OPC_Decode, + 161, + 89, + 35, // Opcode: VSSSEG6E32_V + /* 5422 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 5436 + /* 5427 */ MCD_OPC_CheckPredicate, + 6, + 137, + 44, + 0, // Skip to: 16833 + /* 5432 */ MCD_OPC_Decode, + 217, + 88, + 34, // Opcode: VSOXSEG6EI32_V + /* 5436 */ MCD_OPC_FilterValue, + 48, + 16, + 0, + 0, // Skip to: 5457 + /* 5441 */ MCD_OPC_CheckPredicate, + 6, + 123, + 44, + 0, // Skip to: 16833 + /* 5446 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 116, + 44, + 0, // Skip to: 16833 + /* 5453 */ MCD_OPC_Decode, + 131, + 89, + 32, // Opcode: VSSEG7E32_V + /* 5457 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 5471 + /* 5462 */ MCD_OPC_CheckPredicate, + 6, + 102, + 44, + 0, // Skip to: 16833 + /* 5467 */ MCD_OPC_Decode, + 203, + 89, + 34, // Opcode: VSUXSEG7EI32_V + /* 5471 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 5485 + /* 5476 */ MCD_OPC_CheckPredicate, + 6, + 88, + 44, + 0, // Skip to: 16833 + /* 5481 */ MCD_OPC_Decode, + 165, + 89, + 35, // Opcode: VSSSEG7E32_V + /* 5485 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 5499 + /* 5490 */ MCD_OPC_CheckPredicate, + 6, + 74, + 44, + 0, // Skip to: 16833 + /* 5495 */ MCD_OPC_Decode, + 221, + 88, + 34, // Opcode: VSOXSEG7EI32_V + /* 5499 */ MCD_OPC_FilterValue, + 56, + 16, + 0, + 0, // Skip to: 5520 + /* 5504 */ MCD_OPC_CheckPredicate, + 6, + 60, + 44, + 0, // Skip to: 16833 + /* 5509 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 53, + 44, + 0, // Skip to: 16833 + /* 5516 */ MCD_OPC_Decode, + 135, + 89, + 32, // Opcode: VSSEG8E32_V + /* 5520 */ MCD_OPC_FilterValue, + 57, + 9, + 0, + 0, // Skip to: 5534 + /* 5525 */ MCD_OPC_CheckPredicate, + 6, + 39, + 44, + 0, // Skip to: 16833 + /* 5530 */ MCD_OPC_Decode, + 207, + 89, + 34, // Opcode: VSUXSEG8EI32_V + /* 5534 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 5548 + /* 5539 */ MCD_OPC_CheckPredicate, + 6, + 25, + 44, + 0, // Skip to: 16833 + /* 5544 */ MCD_OPC_Decode, + 169, + 89, + 35, // Opcode: VSSSEG8E32_V + /* 5548 */ MCD_OPC_FilterValue, + 59, + 16, + 44, + 0, // Skip to: 16833 + /* 5553 */ MCD_OPC_CheckPredicate, + 6, + 11, + 44, + 0, // Skip to: 16833 + /* 5558 */ MCD_OPC_Decode, + 225, + 88, + 34, // Opcode: VSOXSEG8EI32_V + /* 5562 */ MCD_OPC_FilterValue, + 7, + 2, + 44, + 0, // Skip to: 16833 + /* 5567 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 5570 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 5591 + /* 5575 */ MCD_OPC_CheckPredicate, + 5, + 245, + 43, + 0, // Skip to: 16833 + /* 5580 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 238, + 43, + 0, // Skip to: 16833 + /* 5587 */ MCD_OPC_Decode, + 176, + 88, + 32, // Opcode: VSE64_V + /* 5591 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 5605 + /* 5596 */ MCD_OPC_CheckPredicate, + 5, + 224, + 43, + 0, // Skip to: 16833 + /* 5601 */ MCD_OPC_Decode, + 180, + 89, + 34, // Opcode: VSUXEI64_V + /* 5605 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 5619 + /* 5610 */ MCD_OPC_CheckPredicate, + 5, + 210, + 43, + 0, // Skip to: 16833 + /* 5615 */ MCD_OPC_Decode, + 236, + 88, + 35, // Opcode: VSSE64_V + /* 5619 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 5633 + /* 5624 */ MCD_OPC_CheckPredicate, + 5, + 196, + 43, + 0, // Skip to: 16833 + /* 5629 */ MCD_OPC_Decode, + 198, + 88, + 34, // Opcode: VSOXEI64_V + /* 5633 */ MCD_OPC_FilterValue, + 8, + 16, + 0, + 0, // Skip to: 5654 + /* 5638 */ MCD_OPC_CheckPredicate, + 6, + 182, + 43, + 0, // Skip to: 16833 + /* 5643 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 175, + 43, + 0, // Skip to: 16833 + /* 5650 */ MCD_OPC_Decode, + 240, + 88, + 32, // Opcode: VSSEG2E64_V + /* 5654 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 5668 + /* 5659 */ MCD_OPC_CheckPredicate, + 6, + 161, + 43, + 0, // Skip to: 16833 + /* 5664 */ MCD_OPC_Decode, + 184, + 89, + 34, // Opcode: VSUXSEG2EI64_V + /* 5668 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 5682 + /* 5673 */ MCD_OPC_CheckPredicate, + 6, + 147, + 43, + 0, // Skip to: 16833 + /* 5678 */ MCD_OPC_Decode, + 146, + 89, + 35, // Opcode: VSSSEG2E64_V + /* 5682 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 5696 + /* 5687 */ MCD_OPC_CheckPredicate, + 6, + 133, + 43, + 0, // Skip to: 16833 + /* 5692 */ MCD_OPC_Decode, + 202, + 88, + 34, // Opcode: VSOXSEG2EI64_V + /* 5696 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 5717 + /* 5701 */ MCD_OPC_CheckPredicate, + 6, + 119, + 43, + 0, // Skip to: 16833 + /* 5706 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 112, + 43, + 0, // Skip to: 16833 + /* 5713 */ MCD_OPC_Decode, + 244, + 88, + 32, // Opcode: VSSEG3E64_V + /* 5717 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 5731 + /* 5722 */ MCD_OPC_CheckPredicate, + 6, + 98, + 43, + 0, // Skip to: 16833 + /* 5727 */ MCD_OPC_Decode, + 188, + 89, + 34, // Opcode: VSUXSEG3EI64_V + /* 5731 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 5745 + /* 5736 */ MCD_OPC_CheckPredicate, + 6, + 84, + 43, + 0, // Skip to: 16833 + /* 5741 */ MCD_OPC_Decode, + 150, + 89, + 35, // Opcode: VSSSEG3E64_V + /* 5745 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 5759 + /* 5750 */ MCD_OPC_CheckPredicate, + 6, + 70, + 43, + 0, // Skip to: 16833 + /* 5755 */ MCD_OPC_Decode, + 206, + 88, + 34, // Opcode: VSOXSEG3EI64_V + /* 5759 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 5780 + /* 5764 */ MCD_OPC_CheckPredicate, + 6, + 56, + 43, + 0, // Skip to: 16833 + /* 5769 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 49, + 43, + 0, // Skip to: 16833 + /* 5776 */ MCD_OPC_Decode, + 248, + 88, + 32, // Opcode: VSSEG4E64_V + /* 5780 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 5794 + /* 5785 */ MCD_OPC_CheckPredicate, + 6, + 35, + 43, + 0, // Skip to: 16833 + /* 5790 */ MCD_OPC_Decode, + 192, + 89, + 34, // Opcode: VSUXSEG4EI64_V + /* 5794 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 5808 + /* 5799 */ MCD_OPC_CheckPredicate, + 6, + 21, + 43, + 0, // Skip to: 16833 + /* 5804 */ MCD_OPC_Decode, + 154, + 89, + 35, // Opcode: VSSSEG4E64_V + /* 5808 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 5822 + /* 5813 */ MCD_OPC_CheckPredicate, + 6, + 7, + 43, + 0, // Skip to: 16833 + /* 5818 */ MCD_OPC_Decode, + 210, + 88, + 34, // Opcode: VSOXSEG4EI64_V + /* 5822 */ MCD_OPC_FilterValue, + 32, + 16, + 0, + 0, // Skip to: 5843 + /* 5827 */ MCD_OPC_CheckPredicate, + 6, + 249, + 42, + 0, // Skip to: 16833 + /* 5832 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 242, + 42, + 0, // Skip to: 16833 + /* 5839 */ MCD_OPC_Decode, + 252, + 88, + 32, // Opcode: VSSEG5E64_V + /* 5843 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 5857 + /* 5848 */ MCD_OPC_CheckPredicate, + 6, + 228, + 42, + 0, // Skip to: 16833 + /* 5853 */ MCD_OPC_Decode, + 196, + 89, + 34, // Opcode: VSUXSEG5EI64_V + /* 5857 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 5871 + /* 5862 */ MCD_OPC_CheckPredicate, + 6, + 214, + 42, + 0, // Skip to: 16833 + /* 5867 */ MCD_OPC_Decode, + 158, + 89, + 35, // Opcode: VSSSEG5E64_V + /* 5871 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 5885 + /* 5876 */ MCD_OPC_CheckPredicate, + 6, + 200, + 42, + 0, // Skip to: 16833 + /* 5881 */ MCD_OPC_Decode, + 214, + 88, + 34, // Opcode: VSOXSEG5EI64_V + /* 5885 */ MCD_OPC_FilterValue, + 40, + 16, + 0, + 0, // Skip to: 5906 + /* 5890 */ MCD_OPC_CheckPredicate, + 6, + 186, + 42, + 0, // Skip to: 16833 + /* 5895 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 179, + 42, + 0, // Skip to: 16833 + /* 5902 */ MCD_OPC_Decode, + 128, + 89, + 32, // Opcode: VSSEG6E64_V + /* 5906 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 5920 + /* 5911 */ MCD_OPC_CheckPredicate, + 6, + 165, + 42, + 0, // Skip to: 16833 + /* 5916 */ MCD_OPC_Decode, + 200, + 89, + 34, // Opcode: VSUXSEG6EI64_V + /* 5920 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 5934 + /* 5925 */ MCD_OPC_CheckPredicate, + 6, + 151, + 42, + 0, // Skip to: 16833 + /* 5930 */ MCD_OPC_Decode, + 162, + 89, + 35, // Opcode: VSSSEG6E64_V + /* 5934 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 5948 + /* 5939 */ MCD_OPC_CheckPredicate, + 6, + 137, + 42, + 0, // Skip to: 16833 + /* 5944 */ MCD_OPC_Decode, + 218, + 88, + 34, // Opcode: VSOXSEG6EI64_V + /* 5948 */ MCD_OPC_FilterValue, + 48, + 16, + 0, + 0, // Skip to: 5969 + /* 5953 */ MCD_OPC_CheckPredicate, + 6, + 123, + 42, + 0, // Skip to: 16833 + /* 5958 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 116, + 42, + 0, // Skip to: 16833 + /* 5965 */ MCD_OPC_Decode, + 132, + 89, + 32, // Opcode: VSSEG7E64_V + /* 5969 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 5983 + /* 5974 */ MCD_OPC_CheckPredicate, + 6, + 102, + 42, + 0, // Skip to: 16833 + /* 5979 */ MCD_OPC_Decode, + 204, + 89, + 34, // Opcode: VSUXSEG7EI64_V + /* 5983 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 5997 + /* 5988 */ MCD_OPC_CheckPredicate, + 6, + 88, + 42, + 0, // Skip to: 16833 + /* 5993 */ MCD_OPC_Decode, + 166, + 89, + 35, // Opcode: VSSSEG7E64_V + /* 5997 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 6011 + /* 6002 */ MCD_OPC_CheckPredicate, + 6, + 74, + 42, + 0, // Skip to: 16833 + /* 6007 */ MCD_OPC_Decode, + 222, + 88, + 34, // Opcode: VSOXSEG7EI64_V + /* 6011 */ MCD_OPC_FilterValue, + 56, + 16, + 0, + 0, // Skip to: 6032 + /* 6016 */ MCD_OPC_CheckPredicate, + 6, + 60, + 42, + 0, // Skip to: 16833 + /* 6021 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 53, + 42, + 0, // Skip to: 16833 + /* 6028 */ MCD_OPC_Decode, + 136, + 89, + 32, // Opcode: VSSEG8E64_V + /* 6032 */ MCD_OPC_FilterValue, + 57, + 9, + 0, + 0, // Skip to: 6046 + /* 6037 */ MCD_OPC_CheckPredicate, + 6, + 39, + 42, + 0, // Skip to: 16833 + /* 6042 */ MCD_OPC_Decode, + 208, + 89, + 34, // Opcode: VSUXSEG8EI64_V + /* 6046 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 6060 + /* 6051 */ MCD_OPC_CheckPredicate, + 6, + 25, + 42, + 0, // Skip to: 16833 + /* 6056 */ MCD_OPC_Decode, + 170, + 89, + 35, // Opcode: VSSSEG8E64_V + /* 6060 */ MCD_OPC_FilterValue, + 59, + 16, + 42, + 0, // Skip to: 16833 + /* 6065 */ MCD_OPC_CheckPredicate, + 6, + 11, + 42, + 0, // Skip to: 16833 + /* 6070 */ MCD_OPC_Decode, + 226, + 88, + 34, // Opcode: VSOXSEG8EI64_V + /* 6074 */ MCD_OPC_FilterValue, + 47, + 51, + 10, + 0, // Skip to: 8690 + /* 6079 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 6082 */ MCD_OPC_FilterValue, + 0, + 251, + 0, + 0, // Skip to: 6338 + /* 6087 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6090 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 6120 + /* 6095 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 6111 + /* 6100 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 6111 + /* 6107 */ MCD_OPC_Decode, + 205, + 84, + 53, // Opcode: VAMOADDEI8_WD + /* 6111 */ MCD_OPC_CheckPredicate, + 24, + 221, + 41, + 0, // Skip to: 16833 + /* 6116 */ MCD_OPC_Decode, + 204, + 84, + 54, // Opcode: VAMOADDEI8_UNWD + /* 6120 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 6184 + /* 6125 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 6128 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6142 + /* 6133 */ MCD_OPC_CheckPredicate, + 25, + 199, + 41, + 0, // Skip to: 16833 + /* 6138 */ MCD_OPC_Decode, + 171, + 81, + 55, // Opcode: AMOADD_W + /* 6142 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6156 + /* 6147 */ MCD_OPC_CheckPredicate, + 25, + 185, + 41, + 0, // Skip to: 16833 + /* 6152 */ MCD_OPC_Decode, + 174, + 81, + 55, // Opcode: AMOADD_W_RL + /* 6156 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6170 + /* 6161 */ MCD_OPC_CheckPredicate, + 25, + 171, + 41, + 0, // Skip to: 16833 + /* 6166 */ MCD_OPC_Decode, + 172, + 81, + 55, // Opcode: AMOADD_W_AQ + /* 6170 */ MCD_OPC_FilterValue, + 3, + 162, + 41, + 0, // Skip to: 16833 + /* 6175 */ MCD_OPC_CheckPredicate, + 25, + 157, + 41, + 0, // Skip to: 16833 + /* 6180 */ MCD_OPC_Decode, + 173, + 81, + 55, // Opcode: AMOADD_W_AQ_RL + /* 6184 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 6248 + /* 6189 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 6192 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6206 + /* 6197 */ MCD_OPC_CheckPredicate, + 26, + 135, + 41, + 0, // Skip to: 16833 + /* 6202 */ MCD_OPC_Decode, + 167, + 81, + 55, // Opcode: AMOADD_D + /* 6206 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6220 + /* 6211 */ MCD_OPC_CheckPredicate, + 26, + 121, + 41, + 0, // Skip to: 16833 + /* 6216 */ MCD_OPC_Decode, + 170, + 81, + 55, // Opcode: AMOADD_D_RL + /* 6220 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6234 + /* 6225 */ MCD_OPC_CheckPredicate, + 26, + 107, + 41, + 0, // Skip to: 16833 + /* 6230 */ MCD_OPC_Decode, + 168, + 81, + 55, // Opcode: AMOADD_D_AQ + /* 6234 */ MCD_OPC_FilterValue, + 3, + 98, + 41, + 0, // Skip to: 16833 + /* 6239 */ MCD_OPC_CheckPredicate, + 26, + 93, + 41, + 0, // Skip to: 16833 + /* 6244 */ MCD_OPC_Decode, + 169, + 81, + 55, // Opcode: AMOADD_D_AQ_RL + /* 6248 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 6278 + /* 6253 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 6269 + /* 6258 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 6269 + /* 6265 */ MCD_OPC_Decode, + 199, + 84, + 53, // Opcode: VAMOADDEI16_WD + /* 6269 */ MCD_OPC_CheckPredicate, + 24, + 63, + 41, + 0, // Skip to: 16833 + /* 6274 */ MCD_OPC_Decode, + 198, + 84, + 54, // Opcode: VAMOADDEI16_UNWD + /* 6278 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 6308 + /* 6283 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 6299 + /* 6288 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 6299 + /* 6295 */ MCD_OPC_Decode, + 201, + 84, + 53, // Opcode: VAMOADDEI32_WD + /* 6299 */ MCD_OPC_CheckPredicate, + 24, + 33, + 41, + 0, // Skip to: 16833 + /* 6304 */ MCD_OPC_Decode, + 200, + 84, + 54, // Opcode: VAMOADDEI32_UNWD + /* 6308 */ MCD_OPC_FilterValue, + 7, + 24, + 41, + 0, // Skip to: 16833 + /* 6313 */ MCD_OPC_CheckPredicate, + 27, + 11, + 0, + 0, // Skip to: 6329 + /* 6318 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 6329 + /* 6325 */ MCD_OPC_Decode, + 203, + 84, + 53, // Opcode: VAMOADDEI64_WD + /* 6329 */ MCD_OPC_CheckPredicate, + 27, + 3, + 41, + 0, // Skip to: 16833 + /* 6334 */ MCD_OPC_Decode, + 202, + 84, + 54, // Opcode: VAMOADDEI64_UNWD + /* 6338 */ MCD_OPC_FilterValue, + 1, + 251, + 0, + 0, // Skip to: 6594 + /* 6343 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6346 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 6376 + /* 6351 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 6367 + /* 6356 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 6367 + /* 6363 */ MCD_OPC_Decode, + 133, + 85, + 53, // Opcode: VAMOSWAPEI8_WD + /* 6367 */ MCD_OPC_CheckPredicate, + 24, + 221, + 40, + 0, // Skip to: 16833 + /* 6372 */ MCD_OPC_Decode, + 132, + 85, + 54, // Opcode: VAMOSWAPEI8_UNWD + /* 6376 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 6440 + /* 6381 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 6384 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6398 + /* 6389 */ MCD_OPC_CheckPredicate, + 25, + 199, + 40, + 0, // Skip to: 16833 + /* 6394 */ MCD_OPC_Decode, + 227, + 81, + 55, // Opcode: AMOSWAP_W + /* 6398 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6412 + /* 6403 */ MCD_OPC_CheckPredicate, + 25, + 185, + 40, + 0, // Skip to: 16833 + /* 6408 */ MCD_OPC_Decode, + 230, + 81, + 55, // Opcode: AMOSWAP_W_RL + /* 6412 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6426 + /* 6417 */ MCD_OPC_CheckPredicate, + 25, + 171, + 40, + 0, // Skip to: 16833 + /* 6422 */ MCD_OPC_Decode, + 228, + 81, + 55, // Opcode: AMOSWAP_W_AQ + /* 6426 */ MCD_OPC_FilterValue, + 3, + 162, + 40, + 0, // Skip to: 16833 + /* 6431 */ MCD_OPC_CheckPredicate, + 25, + 157, + 40, + 0, // Skip to: 16833 + /* 6436 */ MCD_OPC_Decode, + 229, + 81, + 55, // Opcode: AMOSWAP_W_AQ_RL + /* 6440 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 6504 + /* 6445 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 6448 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6462 + /* 6453 */ MCD_OPC_CheckPredicate, + 26, + 135, + 40, + 0, // Skip to: 16833 + /* 6458 */ MCD_OPC_Decode, + 223, + 81, + 55, // Opcode: AMOSWAP_D + /* 6462 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6476 + /* 6467 */ MCD_OPC_CheckPredicate, + 26, + 121, + 40, + 0, // Skip to: 16833 + /* 6472 */ MCD_OPC_Decode, + 226, + 81, + 55, // Opcode: AMOSWAP_D_RL + /* 6476 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6490 + /* 6481 */ MCD_OPC_CheckPredicate, + 26, + 107, + 40, + 0, // Skip to: 16833 + /* 6486 */ MCD_OPC_Decode, + 224, + 81, + 55, // Opcode: AMOSWAP_D_AQ + /* 6490 */ MCD_OPC_FilterValue, + 3, + 98, + 40, + 0, // Skip to: 16833 + /* 6495 */ MCD_OPC_CheckPredicate, + 26, + 93, + 40, + 0, // Skip to: 16833 + /* 6500 */ MCD_OPC_Decode, + 225, + 81, + 55, // Opcode: AMOSWAP_D_AQ_RL + /* 6504 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 6534 + /* 6509 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 6525 + /* 6514 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 6525 + /* 6521 */ MCD_OPC_Decode, + 255, + 84, + 53, // Opcode: VAMOSWAPEI16_WD + /* 6525 */ MCD_OPC_CheckPredicate, + 24, + 63, + 40, + 0, // Skip to: 16833 + /* 6530 */ MCD_OPC_Decode, + 254, + 84, + 54, // Opcode: VAMOSWAPEI16_UNWD + /* 6534 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 6564 + /* 6539 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 6555 + /* 6544 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 6555 + /* 6551 */ MCD_OPC_Decode, + 129, + 85, + 53, // Opcode: VAMOSWAPEI32_WD + /* 6555 */ MCD_OPC_CheckPredicate, + 24, + 33, + 40, + 0, // Skip to: 16833 + /* 6560 */ MCD_OPC_Decode, + 128, + 85, + 54, // Opcode: VAMOSWAPEI32_UNWD + /* 6564 */ MCD_OPC_FilterValue, + 7, + 24, + 40, + 0, // Skip to: 16833 + /* 6569 */ MCD_OPC_CheckPredicate, + 27, + 11, + 0, + 0, // Skip to: 6585 + /* 6574 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 6585 + /* 6581 */ MCD_OPC_Decode, + 131, + 85, + 53, // Opcode: VAMOSWAPEI64_WD + /* 6585 */ MCD_OPC_CheckPredicate, + 27, + 3, + 40, + 0, // Skip to: 16833 + /* 6590 */ MCD_OPC_Decode, + 130, + 85, + 54, // Opcode: VAMOSWAPEI64_UNWD + /* 6594 */ MCD_OPC_FilterValue, + 2, + 147, + 0, + 0, // Skip to: 6746 + /* 6599 */ MCD_OPC_ExtractField, + 20, + 7, // Inst{26-20} ... + /* 6602 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 6638 + /* 6607 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6610 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6624 + /* 6615 */ MCD_OPC_CheckPredicate, + 25, + 229, + 39, + 0, // Skip to: 16833 + /* 6620 */ MCD_OPC_Decode, + 229, + 83, + 45, // Opcode: LR_W + /* 6624 */ MCD_OPC_FilterValue, + 3, + 220, + 39, + 0, // Skip to: 16833 + /* 6629 */ MCD_OPC_CheckPredicate, + 26, + 215, + 39, + 0, // Skip to: 16833 + /* 6634 */ MCD_OPC_Decode, + 225, + 83, + 45, // Opcode: LR_D + /* 6638 */ MCD_OPC_FilterValue, + 32, + 31, + 0, + 0, // Skip to: 6674 + /* 6643 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6646 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6660 + /* 6651 */ MCD_OPC_CheckPredicate, + 25, + 193, + 39, + 0, // Skip to: 16833 + /* 6656 */ MCD_OPC_Decode, + 232, + 83, + 45, // Opcode: LR_W_RL + /* 6660 */ MCD_OPC_FilterValue, + 3, + 184, + 39, + 0, // Skip to: 16833 + /* 6665 */ MCD_OPC_CheckPredicate, + 26, + 179, + 39, + 0, // Skip to: 16833 + /* 6670 */ MCD_OPC_Decode, + 228, + 83, + 45, // Opcode: LR_D_RL + /* 6674 */ MCD_OPC_FilterValue, + 64, + 31, + 0, + 0, // Skip to: 6710 + /* 6679 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6682 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6696 + /* 6687 */ MCD_OPC_CheckPredicate, + 25, + 157, + 39, + 0, // Skip to: 16833 + /* 6692 */ MCD_OPC_Decode, + 230, + 83, + 45, // Opcode: LR_W_AQ + /* 6696 */ MCD_OPC_FilterValue, + 3, + 148, + 39, + 0, // Skip to: 16833 + /* 6701 */ MCD_OPC_CheckPredicate, + 26, + 143, + 39, + 0, // Skip to: 16833 + /* 6706 */ MCD_OPC_Decode, + 226, + 83, + 45, // Opcode: LR_D_AQ + /* 6710 */ MCD_OPC_FilterValue, + 96, + 134, + 39, + 0, // Skip to: 16833 + /* 6715 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6718 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6732 + /* 6723 */ MCD_OPC_CheckPredicate, + 25, + 121, + 39, + 0, // Skip to: 16833 + /* 6728 */ MCD_OPC_Decode, + 231, + 83, + 45, // Opcode: LR_W_AQ_RL + /* 6732 */ MCD_OPC_FilterValue, + 3, + 112, + 39, + 0, // Skip to: 16833 + /* 6737 */ MCD_OPC_CheckPredicate, + 26, + 107, + 39, + 0, // Skip to: 16833 + /* 6742 */ MCD_OPC_Decode, + 227, + 83, + 45, // Opcode: LR_D_AQ_RL + /* 6746 */ MCD_OPC_FilterValue, + 3, + 147, + 0, + 0, // Skip to: 6898 + /* 6751 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 6754 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 6790 + /* 6759 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6762 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6776 + /* 6767 */ MCD_OPC_CheckPredicate, + 25, + 77, + 39, + 0, // Skip to: 16833 + /* 6772 */ MCD_OPC_Decode, + 144, + 84, + 55, // Opcode: SC_W + /* 6776 */ MCD_OPC_FilterValue, + 3, + 68, + 39, + 0, // Skip to: 16833 + /* 6781 */ MCD_OPC_CheckPredicate, + 26, + 63, + 39, + 0, // Skip to: 16833 + /* 6786 */ MCD_OPC_Decode, + 140, + 84, + 55, // Opcode: SC_D + /* 6790 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 6826 + /* 6795 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6798 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6812 + /* 6803 */ MCD_OPC_CheckPredicate, + 25, + 41, + 39, + 0, // Skip to: 16833 + /* 6808 */ MCD_OPC_Decode, + 147, + 84, + 55, // Opcode: SC_W_RL + /* 6812 */ MCD_OPC_FilterValue, + 3, + 32, + 39, + 0, // Skip to: 16833 + /* 6817 */ MCD_OPC_CheckPredicate, + 26, + 27, + 39, + 0, // Skip to: 16833 + /* 6822 */ MCD_OPC_Decode, + 143, + 84, + 55, // Opcode: SC_D_RL + /* 6826 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 6862 + /* 6831 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6834 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6848 + /* 6839 */ MCD_OPC_CheckPredicate, + 25, + 5, + 39, + 0, // Skip to: 16833 + /* 6844 */ MCD_OPC_Decode, + 145, + 84, + 55, // Opcode: SC_W_AQ + /* 6848 */ MCD_OPC_FilterValue, + 3, + 252, + 38, + 0, // Skip to: 16833 + /* 6853 */ MCD_OPC_CheckPredicate, + 26, + 247, + 38, + 0, // Skip to: 16833 + /* 6858 */ MCD_OPC_Decode, + 141, + 84, + 55, // Opcode: SC_D_AQ + /* 6862 */ MCD_OPC_FilterValue, + 3, + 238, + 38, + 0, // Skip to: 16833 + /* 6867 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6870 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6884 + /* 6875 */ MCD_OPC_CheckPredicate, + 25, + 225, + 38, + 0, // Skip to: 16833 + /* 6880 */ MCD_OPC_Decode, + 146, + 84, + 55, // Opcode: SC_W_AQ_RL + /* 6884 */ MCD_OPC_FilterValue, + 3, + 216, + 38, + 0, // Skip to: 16833 + /* 6889 */ MCD_OPC_CheckPredicate, + 26, + 211, + 38, + 0, // Skip to: 16833 + /* 6894 */ MCD_OPC_Decode, + 142, + 84, + 55, // Opcode: SC_D_AQ_RL + /* 6898 */ MCD_OPC_FilterValue, + 4, + 251, + 0, + 0, // Skip to: 7154 + /* 6903 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 6906 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 6936 + /* 6911 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 6927 + /* 6916 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 6927 + /* 6923 */ MCD_OPC_Decode, + 141, + 85, + 53, // Opcode: VAMOXOREI8_WD + /* 6927 */ MCD_OPC_CheckPredicate, + 24, + 173, + 38, + 0, // Skip to: 16833 + /* 6932 */ MCD_OPC_Decode, + 140, + 85, + 54, // Opcode: VAMOXOREI8_UNWD + /* 6936 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 7000 + /* 6941 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 6944 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 6958 + /* 6949 */ MCD_OPC_CheckPredicate, + 25, + 151, + 38, + 0, // Skip to: 16833 + /* 6954 */ MCD_OPC_Decode, + 235, + 81, + 55, // Opcode: AMOXOR_W + /* 6958 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 6972 + /* 6963 */ MCD_OPC_CheckPredicate, + 25, + 137, + 38, + 0, // Skip to: 16833 + /* 6968 */ MCD_OPC_Decode, + 238, + 81, + 55, // Opcode: AMOXOR_W_RL + /* 6972 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 6986 + /* 6977 */ MCD_OPC_CheckPredicate, + 25, + 123, + 38, + 0, // Skip to: 16833 + /* 6982 */ MCD_OPC_Decode, + 236, + 81, + 55, // Opcode: AMOXOR_W_AQ + /* 6986 */ MCD_OPC_FilterValue, + 3, + 114, + 38, + 0, // Skip to: 16833 + /* 6991 */ MCD_OPC_CheckPredicate, + 25, + 109, + 38, + 0, // Skip to: 16833 + /* 6996 */ MCD_OPC_Decode, + 237, + 81, + 55, // Opcode: AMOXOR_W_AQ_RL + /* 7000 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 7064 + /* 7005 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 7008 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7022 + /* 7013 */ MCD_OPC_CheckPredicate, + 26, + 87, + 38, + 0, // Skip to: 16833 + /* 7018 */ MCD_OPC_Decode, + 231, + 81, + 55, // Opcode: AMOXOR_D + /* 7022 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7036 + /* 7027 */ MCD_OPC_CheckPredicate, + 26, + 73, + 38, + 0, // Skip to: 16833 + /* 7032 */ MCD_OPC_Decode, + 234, + 81, + 55, // Opcode: AMOXOR_D_RL + /* 7036 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7050 + /* 7041 */ MCD_OPC_CheckPredicate, + 26, + 59, + 38, + 0, // Skip to: 16833 + /* 7046 */ MCD_OPC_Decode, + 232, + 81, + 55, // Opcode: AMOXOR_D_AQ + /* 7050 */ MCD_OPC_FilterValue, + 3, + 50, + 38, + 0, // Skip to: 16833 + /* 7055 */ MCD_OPC_CheckPredicate, + 26, + 45, + 38, + 0, // Skip to: 16833 + /* 7060 */ MCD_OPC_Decode, + 233, + 81, + 55, // Opcode: AMOXOR_D_AQ_RL + /* 7064 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 7094 + /* 7069 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7085 + /* 7074 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7085 + /* 7081 */ MCD_OPC_Decode, + 135, + 85, + 53, // Opcode: VAMOXOREI16_WD + /* 7085 */ MCD_OPC_CheckPredicate, + 24, + 15, + 38, + 0, // Skip to: 16833 + /* 7090 */ MCD_OPC_Decode, + 134, + 85, + 54, // Opcode: VAMOXOREI16_UNWD + /* 7094 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 7124 + /* 7099 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7115 + /* 7104 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7115 + /* 7111 */ MCD_OPC_Decode, + 137, + 85, + 53, // Opcode: VAMOXOREI32_WD + /* 7115 */ MCD_OPC_CheckPredicate, + 24, + 241, + 37, + 0, // Skip to: 16833 + /* 7120 */ MCD_OPC_Decode, + 136, + 85, + 54, // Opcode: VAMOXOREI32_UNWD + /* 7124 */ MCD_OPC_FilterValue, + 7, + 232, + 37, + 0, // Skip to: 16833 + /* 7129 */ MCD_OPC_CheckPredicate, + 27, + 11, + 0, + 0, // Skip to: 7145 + /* 7134 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7145 + /* 7141 */ MCD_OPC_Decode, + 139, + 85, + 53, // Opcode: VAMOXOREI64_WD + /* 7145 */ MCD_OPC_CheckPredicate, + 27, + 211, + 37, + 0, // Skip to: 16833 + /* 7150 */ MCD_OPC_Decode, + 138, + 85, + 54, // Opcode: VAMOXOREI64_UNWD + /* 7154 */ MCD_OPC_FilterValue, + 8, + 251, + 0, + 0, // Skip to: 7410 + /* 7159 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 7162 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 7192 + /* 7167 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7183 + /* 7172 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7183 + /* 7179 */ MCD_OPC_Decode, + 253, + 84, + 53, // Opcode: VAMOOREI8_WD + /* 7183 */ MCD_OPC_CheckPredicate, + 24, + 173, + 37, + 0, // Skip to: 16833 + /* 7188 */ MCD_OPC_Decode, + 252, + 84, + 54, // Opcode: VAMOOREI8_UNWD + /* 7192 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 7256 + /* 7197 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 7200 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7214 + /* 7205 */ MCD_OPC_CheckPredicate, + 25, + 151, + 37, + 0, // Skip to: 16833 + /* 7210 */ MCD_OPC_Decode, + 219, + 81, + 55, // Opcode: AMOOR_W + /* 7214 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7228 + /* 7219 */ MCD_OPC_CheckPredicate, + 25, + 137, + 37, + 0, // Skip to: 16833 + /* 7224 */ MCD_OPC_Decode, + 222, + 81, + 55, // Opcode: AMOOR_W_RL + /* 7228 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7242 + /* 7233 */ MCD_OPC_CheckPredicate, + 25, + 123, + 37, + 0, // Skip to: 16833 + /* 7238 */ MCD_OPC_Decode, + 220, + 81, + 55, // Opcode: AMOOR_W_AQ + /* 7242 */ MCD_OPC_FilterValue, + 3, + 114, + 37, + 0, // Skip to: 16833 + /* 7247 */ MCD_OPC_CheckPredicate, + 25, + 109, + 37, + 0, // Skip to: 16833 + /* 7252 */ MCD_OPC_Decode, + 221, + 81, + 55, // Opcode: AMOOR_W_AQ_RL + /* 7256 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 7320 + /* 7261 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 7264 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7278 + /* 7269 */ MCD_OPC_CheckPredicate, + 26, + 87, + 37, + 0, // Skip to: 16833 + /* 7274 */ MCD_OPC_Decode, + 215, + 81, + 55, // Opcode: AMOOR_D + /* 7278 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7292 + /* 7283 */ MCD_OPC_CheckPredicate, + 26, + 73, + 37, + 0, // Skip to: 16833 + /* 7288 */ MCD_OPC_Decode, + 218, + 81, + 55, // Opcode: AMOOR_D_RL + /* 7292 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7306 + /* 7297 */ MCD_OPC_CheckPredicate, + 26, + 59, + 37, + 0, // Skip to: 16833 + /* 7302 */ MCD_OPC_Decode, + 216, + 81, + 55, // Opcode: AMOOR_D_AQ + /* 7306 */ MCD_OPC_FilterValue, + 3, + 50, + 37, + 0, // Skip to: 16833 + /* 7311 */ MCD_OPC_CheckPredicate, + 26, + 45, + 37, + 0, // Skip to: 16833 + /* 7316 */ MCD_OPC_Decode, + 217, + 81, + 55, // Opcode: AMOOR_D_AQ_RL + /* 7320 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 7350 + /* 7325 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7341 + /* 7330 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7341 + /* 7337 */ MCD_OPC_Decode, + 247, + 84, + 53, // Opcode: VAMOOREI16_WD + /* 7341 */ MCD_OPC_CheckPredicate, + 24, + 15, + 37, + 0, // Skip to: 16833 + /* 7346 */ MCD_OPC_Decode, + 246, + 84, + 54, // Opcode: VAMOOREI16_UNWD + /* 7350 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 7380 + /* 7355 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7371 + /* 7360 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7371 + /* 7367 */ MCD_OPC_Decode, + 249, + 84, + 53, // Opcode: VAMOOREI32_WD + /* 7371 */ MCD_OPC_CheckPredicate, + 24, + 241, + 36, + 0, // Skip to: 16833 + /* 7376 */ MCD_OPC_Decode, + 248, + 84, + 54, // Opcode: VAMOOREI32_UNWD + /* 7380 */ MCD_OPC_FilterValue, + 7, + 232, + 36, + 0, // Skip to: 16833 + /* 7385 */ MCD_OPC_CheckPredicate, + 27, + 11, + 0, + 0, // Skip to: 7401 + /* 7390 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7401 + /* 7397 */ MCD_OPC_Decode, + 251, + 84, + 53, // Opcode: VAMOOREI64_WD + /* 7401 */ MCD_OPC_CheckPredicate, + 27, + 211, + 36, + 0, // Skip to: 16833 + /* 7406 */ MCD_OPC_Decode, + 250, + 84, + 54, // Opcode: VAMOOREI64_UNWD + /* 7410 */ MCD_OPC_FilterValue, + 12, + 251, + 0, + 0, // Skip to: 7666 + /* 7415 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 7418 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 7448 + /* 7423 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7439 + /* 7428 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7439 + /* 7435 */ MCD_OPC_Decode, + 213, + 84, + 53, // Opcode: VAMOANDEI8_WD + /* 7439 */ MCD_OPC_CheckPredicate, + 24, + 173, + 36, + 0, // Skip to: 16833 + /* 7444 */ MCD_OPC_Decode, + 212, + 84, + 54, // Opcode: VAMOANDEI8_UNWD + /* 7448 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 7512 + /* 7453 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 7456 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7470 + /* 7461 */ MCD_OPC_CheckPredicate, + 25, + 151, + 36, + 0, // Skip to: 16833 + /* 7466 */ MCD_OPC_Decode, + 179, + 81, + 55, // Opcode: AMOAND_W + /* 7470 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7484 + /* 7475 */ MCD_OPC_CheckPredicate, + 25, + 137, + 36, + 0, // Skip to: 16833 + /* 7480 */ MCD_OPC_Decode, + 182, + 81, + 55, // Opcode: AMOAND_W_RL + /* 7484 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7498 + /* 7489 */ MCD_OPC_CheckPredicate, + 25, + 123, + 36, + 0, // Skip to: 16833 + /* 7494 */ MCD_OPC_Decode, + 180, + 81, + 55, // Opcode: AMOAND_W_AQ + /* 7498 */ MCD_OPC_FilterValue, + 3, + 114, + 36, + 0, // Skip to: 16833 + /* 7503 */ MCD_OPC_CheckPredicate, + 25, + 109, + 36, + 0, // Skip to: 16833 + /* 7508 */ MCD_OPC_Decode, + 181, + 81, + 55, // Opcode: AMOAND_W_AQ_RL + /* 7512 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 7576 + /* 7517 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 7520 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7534 + /* 7525 */ MCD_OPC_CheckPredicate, + 26, + 87, + 36, + 0, // Skip to: 16833 + /* 7530 */ MCD_OPC_Decode, + 175, + 81, + 55, // Opcode: AMOAND_D + /* 7534 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7548 + /* 7539 */ MCD_OPC_CheckPredicate, + 26, + 73, + 36, + 0, // Skip to: 16833 + /* 7544 */ MCD_OPC_Decode, + 178, + 81, + 55, // Opcode: AMOAND_D_RL + /* 7548 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7562 + /* 7553 */ MCD_OPC_CheckPredicate, + 26, + 59, + 36, + 0, // Skip to: 16833 + /* 7558 */ MCD_OPC_Decode, + 176, + 81, + 55, // Opcode: AMOAND_D_AQ + /* 7562 */ MCD_OPC_FilterValue, + 3, + 50, + 36, + 0, // Skip to: 16833 + /* 7567 */ MCD_OPC_CheckPredicate, + 26, + 45, + 36, + 0, // Skip to: 16833 + /* 7572 */ MCD_OPC_Decode, + 177, + 81, + 55, // Opcode: AMOAND_D_AQ_RL + /* 7576 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 7606 + /* 7581 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7597 + /* 7586 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7597 + /* 7593 */ MCD_OPC_Decode, + 207, + 84, + 53, // Opcode: VAMOANDEI16_WD + /* 7597 */ MCD_OPC_CheckPredicate, + 24, + 15, + 36, + 0, // Skip to: 16833 + /* 7602 */ MCD_OPC_Decode, + 206, + 84, + 54, // Opcode: VAMOANDEI16_UNWD + /* 7606 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 7636 + /* 7611 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7627 + /* 7616 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7627 + /* 7623 */ MCD_OPC_Decode, + 209, + 84, + 53, // Opcode: VAMOANDEI32_WD + /* 7627 */ MCD_OPC_CheckPredicate, + 24, + 241, + 35, + 0, // Skip to: 16833 + /* 7632 */ MCD_OPC_Decode, + 208, + 84, + 54, // Opcode: VAMOANDEI32_UNWD + /* 7636 */ MCD_OPC_FilterValue, + 7, + 232, + 35, + 0, // Skip to: 16833 + /* 7641 */ MCD_OPC_CheckPredicate, + 27, + 11, + 0, + 0, // Skip to: 7657 + /* 7646 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7657 + /* 7653 */ MCD_OPC_Decode, + 211, + 84, + 53, // Opcode: VAMOANDEI64_WD + /* 7657 */ MCD_OPC_CheckPredicate, + 27, + 211, + 35, + 0, // Skip to: 16833 + /* 7662 */ MCD_OPC_Decode, + 210, + 84, + 54, // Opcode: VAMOANDEI64_UNWD + /* 7666 */ MCD_OPC_FilterValue, + 16, + 251, + 0, + 0, // Skip to: 7922 + /* 7671 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 7674 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 7704 + /* 7679 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7695 + /* 7684 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7695 + /* 7691 */ MCD_OPC_Decode, + 237, + 84, + 53, // Opcode: VAMOMINEI8_WD + /* 7695 */ MCD_OPC_CheckPredicate, + 24, + 173, + 35, + 0, // Skip to: 16833 + /* 7700 */ MCD_OPC_Decode, + 236, + 84, + 54, // Opcode: VAMOMINEI8_UNWD + /* 7704 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 7768 + /* 7709 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 7712 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7726 + /* 7717 */ MCD_OPC_CheckPredicate, + 25, + 151, + 35, + 0, // Skip to: 16833 + /* 7722 */ MCD_OPC_Decode, + 211, + 81, + 55, // Opcode: AMOMIN_W + /* 7726 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7740 + /* 7731 */ MCD_OPC_CheckPredicate, + 25, + 137, + 35, + 0, // Skip to: 16833 + /* 7736 */ MCD_OPC_Decode, + 214, + 81, + 55, // Opcode: AMOMIN_W_RL + /* 7740 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7754 + /* 7745 */ MCD_OPC_CheckPredicate, + 25, + 123, + 35, + 0, // Skip to: 16833 + /* 7750 */ MCD_OPC_Decode, + 212, + 81, + 55, // Opcode: AMOMIN_W_AQ + /* 7754 */ MCD_OPC_FilterValue, + 3, + 114, + 35, + 0, // Skip to: 16833 + /* 7759 */ MCD_OPC_CheckPredicate, + 25, + 109, + 35, + 0, // Skip to: 16833 + /* 7764 */ MCD_OPC_Decode, + 213, + 81, + 55, // Opcode: AMOMIN_W_AQ_RL + /* 7768 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 7832 + /* 7773 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 7776 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7790 + /* 7781 */ MCD_OPC_CheckPredicate, + 26, + 87, + 35, + 0, // Skip to: 16833 + /* 7786 */ MCD_OPC_Decode, + 207, + 81, + 55, // Opcode: AMOMIN_D + /* 7790 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7804 + /* 7795 */ MCD_OPC_CheckPredicate, + 26, + 73, + 35, + 0, // Skip to: 16833 + /* 7800 */ MCD_OPC_Decode, + 210, + 81, + 55, // Opcode: AMOMIN_D_RL + /* 7804 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 7818 + /* 7809 */ MCD_OPC_CheckPredicate, + 26, + 59, + 35, + 0, // Skip to: 16833 + /* 7814 */ MCD_OPC_Decode, + 208, + 81, + 55, // Opcode: AMOMIN_D_AQ + /* 7818 */ MCD_OPC_FilterValue, + 3, + 50, + 35, + 0, // Skip to: 16833 + /* 7823 */ MCD_OPC_CheckPredicate, + 26, + 45, + 35, + 0, // Skip to: 16833 + /* 7828 */ MCD_OPC_Decode, + 209, + 81, + 55, // Opcode: AMOMIN_D_AQ_RL + /* 7832 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 7862 + /* 7837 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7853 + /* 7842 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7853 + /* 7849 */ MCD_OPC_Decode, + 231, + 84, + 53, // Opcode: VAMOMINEI16_WD + /* 7853 */ MCD_OPC_CheckPredicate, + 24, + 15, + 35, + 0, // Skip to: 16833 + /* 7858 */ MCD_OPC_Decode, + 230, + 84, + 54, // Opcode: VAMOMINEI16_UNWD + /* 7862 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 7892 + /* 7867 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7883 + /* 7872 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7883 + /* 7879 */ MCD_OPC_Decode, + 233, + 84, + 53, // Opcode: VAMOMINEI32_WD + /* 7883 */ MCD_OPC_CheckPredicate, + 24, + 241, + 34, + 0, // Skip to: 16833 + /* 7888 */ MCD_OPC_Decode, + 232, + 84, + 54, // Opcode: VAMOMINEI32_UNWD + /* 7892 */ MCD_OPC_FilterValue, + 7, + 232, + 34, + 0, // Skip to: 16833 + /* 7897 */ MCD_OPC_CheckPredicate, + 27, + 11, + 0, + 0, // Skip to: 7913 + /* 7902 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7913 + /* 7909 */ MCD_OPC_Decode, + 235, + 84, + 53, // Opcode: VAMOMINEI64_WD + /* 7913 */ MCD_OPC_CheckPredicate, + 27, + 211, + 34, + 0, // Skip to: 16833 + /* 7918 */ MCD_OPC_Decode, + 234, + 84, + 54, // Opcode: VAMOMINEI64_UNWD + /* 7922 */ MCD_OPC_FilterValue, + 20, + 251, + 0, + 0, // Skip to: 8178 + /* 7927 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 7930 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 7960 + /* 7935 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 7951 + /* 7940 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 7951 + /* 7947 */ MCD_OPC_Decode, + 221, + 84, + 53, // Opcode: VAMOMAXEI8_WD + /* 7951 */ MCD_OPC_CheckPredicate, + 24, + 173, + 34, + 0, // Skip to: 16833 + /* 7956 */ MCD_OPC_Decode, + 220, + 84, + 54, // Opcode: VAMOMAXEI8_UNWD + /* 7960 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 8024 + /* 7965 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 7968 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 7982 + /* 7973 */ MCD_OPC_CheckPredicate, + 25, + 151, + 34, + 0, // Skip to: 16833 + /* 7978 */ MCD_OPC_Decode, + 195, + 81, + 55, // Opcode: AMOMAX_W + /* 7982 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 7996 + /* 7987 */ MCD_OPC_CheckPredicate, + 25, + 137, + 34, + 0, // Skip to: 16833 + /* 7992 */ MCD_OPC_Decode, + 198, + 81, + 55, // Opcode: AMOMAX_W_RL + /* 7996 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8010 + /* 8001 */ MCD_OPC_CheckPredicate, + 25, + 123, + 34, + 0, // Skip to: 16833 + /* 8006 */ MCD_OPC_Decode, + 196, + 81, + 55, // Opcode: AMOMAX_W_AQ + /* 8010 */ MCD_OPC_FilterValue, + 3, + 114, + 34, + 0, // Skip to: 16833 + /* 8015 */ MCD_OPC_CheckPredicate, + 25, + 109, + 34, + 0, // Skip to: 16833 + /* 8020 */ MCD_OPC_Decode, + 197, + 81, + 55, // Opcode: AMOMAX_W_AQ_RL + /* 8024 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 8088 + /* 8029 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 8032 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8046 + /* 8037 */ MCD_OPC_CheckPredicate, + 26, + 87, + 34, + 0, // Skip to: 16833 + /* 8042 */ MCD_OPC_Decode, + 191, + 81, + 55, // Opcode: AMOMAX_D + /* 8046 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8060 + /* 8051 */ MCD_OPC_CheckPredicate, + 26, + 73, + 34, + 0, // Skip to: 16833 + /* 8056 */ MCD_OPC_Decode, + 194, + 81, + 55, // Opcode: AMOMAX_D_RL + /* 8060 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8074 + /* 8065 */ MCD_OPC_CheckPredicate, + 26, + 59, + 34, + 0, // Skip to: 16833 + /* 8070 */ MCD_OPC_Decode, + 192, + 81, + 55, // Opcode: AMOMAX_D_AQ + /* 8074 */ MCD_OPC_FilterValue, + 3, + 50, + 34, + 0, // Skip to: 16833 + /* 8079 */ MCD_OPC_CheckPredicate, + 26, + 45, + 34, + 0, // Skip to: 16833 + /* 8084 */ MCD_OPC_Decode, + 193, + 81, + 55, // Opcode: AMOMAX_D_AQ_RL + /* 8088 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 8118 + /* 8093 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 8109 + /* 8098 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8109 + /* 8105 */ MCD_OPC_Decode, + 215, + 84, + 53, // Opcode: VAMOMAXEI16_WD + /* 8109 */ MCD_OPC_CheckPredicate, + 24, + 15, + 34, + 0, // Skip to: 16833 + /* 8114 */ MCD_OPC_Decode, + 214, + 84, + 54, // Opcode: VAMOMAXEI16_UNWD + /* 8118 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 8148 + /* 8123 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 8139 + /* 8128 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8139 + /* 8135 */ MCD_OPC_Decode, + 217, + 84, + 53, // Opcode: VAMOMAXEI32_WD + /* 8139 */ MCD_OPC_CheckPredicate, + 24, + 241, + 33, + 0, // Skip to: 16833 + /* 8144 */ MCD_OPC_Decode, + 216, + 84, + 54, // Opcode: VAMOMAXEI32_UNWD + /* 8148 */ MCD_OPC_FilterValue, + 7, + 232, + 33, + 0, // Skip to: 16833 + /* 8153 */ MCD_OPC_CheckPredicate, + 27, + 11, + 0, + 0, // Skip to: 8169 + /* 8158 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8169 + /* 8165 */ MCD_OPC_Decode, + 219, + 84, + 53, // Opcode: VAMOMAXEI64_WD + /* 8169 */ MCD_OPC_CheckPredicate, + 27, + 211, + 33, + 0, // Skip to: 16833 + /* 8174 */ MCD_OPC_Decode, + 218, + 84, + 54, // Opcode: VAMOMAXEI64_UNWD + /* 8178 */ MCD_OPC_FilterValue, + 24, + 251, + 0, + 0, // Skip to: 8434 + /* 8183 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 8186 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 8216 + /* 8191 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 8207 + /* 8196 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8207 + /* 8203 */ MCD_OPC_Decode, + 245, + 84, + 53, // Opcode: VAMOMINUEI8_WD + /* 8207 */ MCD_OPC_CheckPredicate, + 24, + 173, + 33, + 0, // Skip to: 16833 + /* 8212 */ MCD_OPC_Decode, + 244, + 84, + 54, // Opcode: VAMOMINUEI8_UNWD + /* 8216 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 8280 + /* 8221 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 8224 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8238 + /* 8229 */ MCD_OPC_CheckPredicate, + 25, + 151, + 33, + 0, // Skip to: 16833 + /* 8234 */ MCD_OPC_Decode, + 203, + 81, + 55, // Opcode: AMOMINU_W + /* 8238 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8252 + /* 8243 */ MCD_OPC_CheckPredicate, + 25, + 137, + 33, + 0, // Skip to: 16833 + /* 8248 */ MCD_OPC_Decode, + 206, + 81, + 55, // Opcode: AMOMINU_W_RL + /* 8252 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8266 + /* 8257 */ MCD_OPC_CheckPredicate, + 25, + 123, + 33, + 0, // Skip to: 16833 + /* 8262 */ MCD_OPC_Decode, + 204, + 81, + 55, // Opcode: AMOMINU_W_AQ + /* 8266 */ MCD_OPC_FilterValue, + 3, + 114, + 33, + 0, // Skip to: 16833 + /* 8271 */ MCD_OPC_CheckPredicate, + 25, + 109, + 33, + 0, // Skip to: 16833 + /* 8276 */ MCD_OPC_Decode, + 205, + 81, + 55, // Opcode: AMOMINU_W_AQ_RL + /* 8280 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 8344 + /* 8285 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 8288 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8302 + /* 8293 */ MCD_OPC_CheckPredicate, + 26, + 87, + 33, + 0, // Skip to: 16833 + /* 8298 */ MCD_OPC_Decode, + 199, + 81, + 55, // Opcode: AMOMINU_D + /* 8302 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8316 + /* 8307 */ MCD_OPC_CheckPredicate, + 26, + 73, + 33, + 0, // Skip to: 16833 + /* 8312 */ MCD_OPC_Decode, + 202, + 81, + 55, // Opcode: AMOMINU_D_RL + /* 8316 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8330 + /* 8321 */ MCD_OPC_CheckPredicate, + 26, + 59, + 33, + 0, // Skip to: 16833 + /* 8326 */ MCD_OPC_Decode, + 200, + 81, + 55, // Opcode: AMOMINU_D_AQ + /* 8330 */ MCD_OPC_FilterValue, + 3, + 50, + 33, + 0, // Skip to: 16833 + /* 8335 */ MCD_OPC_CheckPredicate, + 26, + 45, + 33, + 0, // Skip to: 16833 + /* 8340 */ MCD_OPC_Decode, + 201, + 81, + 55, // Opcode: AMOMINU_D_AQ_RL + /* 8344 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 8374 + /* 8349 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 8365 + /* 8354 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8365 + /* 8361 */ MCD_OPC_Decode, + 239, + 84, + 53, // Opcode: VAMOMINUEI16_WD + /* 8365 */ MCD_OPC_CheckPredicate, + 24, + 15, + 33, + 0, // Skip to: 16833 + /* 8370 */ MCD_OPC_Decode, + 238, + 84, + 54, // Opcode: VAMOMINUEI16_UNWD + /* 8374 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 8404 + /* 8379 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 8395 + /* 8384 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8395 + /* 8391 */ MCD_OPC_Decode, + 241, + 84, + 53, // Opcode: VAMOMINUEI32_WD + /* 8395 */ MCD_OPC_CheckPredicate, + 24, + 241, + 32, + 0, // Skip to: 16833 + /* 8400 */ MCD_OPC_Decode, + 240, + 84, + 54, // Opcode: VAMOMINUEI32_UNWD + /* 8404 */ MCD_OPC_FilterValue, + 7, + 232, + 32, + 0, // Skip to: 16833 + /* 8409 */ MCD_OPC_CheckPredicate, + 27, + 11, + 0, + 0, // Skip to: 8425 + /* 8414 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8425 + /* 8421 */ MCD_OPC_Decode, + 243, + 84, + 53, // Opcode: VAMOMINUEI64_WD + /* 8425 */ MCD_OPC_CheckPredicate, + 27, + 211, + 32, + 0, // Skip to: 16833 + /* 8430 */ MCD_OPC_Decode, + 242, + 84, + 54, // Opcode: VAMOMINUEI64_UNWD + /* 8434 */ MCD_OPC_FilterValue, + 28, + 202, + 32, + 0, // Skip to: 16833 + /* 8439 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 8442 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 8472 + /* 8447 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 8463 + /* 8452 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8463 + /* 8459 */ MCD_OPC_Decode, + 229, + 84, + 53, // Opcode: VAMOMAXUEI8_WD + /* 8463 */ MCD_OPC_CheckPredicate, + 24, + 173, + 32, + 0, // Skip to: 16833 + /* 8468 */ MCD_OPC_Decode, + 228, + 84, + 54, // Opcode: VAMOMAXUEI8_UNWD + /* 8472 */ MCD_OPC_FilterValue, + 2, + 59, + 0, + 0, // Skip to: 8536 + /* 8477 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 8480 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8494 + /* 8485 */ MCD_OPC_CheckPredicate, + 25, + 151, + 32, + 0, // Skip to: 16833 + /* 8490 */ MCD_OPC_Decode, + 187, + 81, + 55, // Opcode: AMOMAXU_W + /* 8494 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8508 + /* 8499 */ MCD_OPC_CheckPredicate, + 25, + 137, + 32, + 0, // Skip to: 16833 + /* 8504 */ MCD_OPC_Decode, + 190, + 81, + 55, // Opcode: AMOMAXU_W_RL + /* 8508 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8522 + /* 8513 */ MCD_OPC_CheckPredicate, + 25, + 123, + 32, + 0, // Skip to: 16833 + /* 8518 */ MCD_OPC_Decode, + 188, + 81, + 55, // Opcode: AMOMAXU_W_AQ + /* 8522 */ MCD_OPC_FilterValue, + 3, + 114, + 32, + 0, // Skip to: 16833 + /* 8527 */ MCD_OPC_CheckPredicate, + 25, + 109, + 32, + 0, // Skip to: 16833 + /* 8532 */ MCD_OPC_Decode, + 189, + 81, + 55, // Opcode: AMOMAXU_W_AQ_RL + /* 8536 */ MCD_OPC_FilterValue, + 3, + 59, + 0, + 0, // Skip to: 8600 + /* 8541 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 8544 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8558 + /* 8549 */ MCD_OPC_CheckPredicate, + 26, + 87, + 32, + 0, // Skip to: 16833 + /* 8554 */ MCD_OPC_Decode, + 183, + 81, + 55, // Opcode: AMOMAXU_D + /* 8558 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8572 + /* 8563 */ MCD_OPC_CheckPredicate, + 26, + 73, + 32, + 0, // Skip to: 16833 + /* 8568 */ MCD_OPC_Decode, + 186, + 81, + 55, // Opcode: AMOMAXU_D_RL + /* 8572 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8586 + /* 8577 */ MCD_OPC_CheckPredicate, + 26, + 59, + 32, + 0, // Skip to: 16833 + /* 8582 */ MCD_OPC_Decode, + 184, + 81, + 55, // Opcode: AMOMAXU_D_AQ + /* 8586 */ MCD_OPC_FilterValue, + 3, + 50, + 32, + 0, // Skip to: 16833 + /* 8591 */ MCD_OPC_CheckPredicate, + 26, + 45, + 32, + 0, // Skip to: 16833 + /* 8596 */ MCD_OPC_Decode, + 185, + 81, + 55, // Opcode: AMOMAXU_D_AQ_RL + /* 8600 */ MCD_OPC_FilterValue, + 5, + 25, + 0, + 0, // Skip to: 8630 + /* 8605 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 8621 + /* 8610 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8621 + /* 8617 */ MCD_OPC_Decode, + 223, + 84, + 53, // Opcode: VAMOMAXUEI16_WD + /* 8621 */ MCD_OPC_CheckPredicate, + 24, + 15, + 32, + 0, // Skip to: 16833 + /* 8626 */ MCD_OPC_Decode, + 222, + 84, + 54, // Opcode: VAMOMAXUEI16_UNWD + /* 8630 */ MCD_OPC_FilterValue, + 6, + 25, + 0, + 0, // Skip to: 8660 + /* 8635 */ MCD_OPC_CheckPredicate, + 24, + 11, + 0, + 0, // Skip to: 8651 + /* 8640 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8651 + /* 8647 */ MCD_OPC_Decode, + 225, + 84, + 53, // Opcode: VAMOMAXUEI32_WD + /* 8651 */ MCD_OPC_CheckPredicate, + 24, + 241, + 31, + 0, // Skip to: 16833 + /* 8656 */ MCD_OPC_Decode, + 224, + 84, + 54, // Opcode: VAMOMAXUEI32_UNWD + /* 8660 */ MCD_OPC_FilterValue, + 7, + 232, + 31, + 0, // Skip to: 16833 + /* 8665 */ MCD_OPC_CheckPredicate, + 27, + 11, + 0, + 0, // Skip to: 8681 + /* 8670 */ MCD_OPC_CheckField, + 26, + 1, + 1, + 4, + 0, + 0, // Skip to: 8681 + /* 8677 */ MCD_OPC_Decode, + 227, + 84, + 53, // Opcode: VAMOMAXUEI64_WD + /* 8681 */ MCD_OPC_CheckPredicate, + 27, + 211, + 31, + 0, // Skip to: 16833 + /* 8686 */ MCD_OPC_Decode, + 226, + 84, + 54, // Opcode: VAMOMAXUEI64_UNWD + /* 8690 */ MCD_OPC_FilterValue, + 51, + 95, + 3, + 0, // Skip to: 9558 + /* 8695 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 8698 */ MCD_OPC_FilterValue, + 0, + 49, + 0, + 0, // Skip to: 8752 + /* 8703 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 8706 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 8715 + /* 8711 */ MCD_OPC_Decode, + 162, + 81, + 55, // Opcode: ADD + /* 8715 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8729 + /* 8720 */ MCD_OPC_CheckPredicate, + 28, + 172, + 31, + 0, // Skip to: 16833 + /* 8725 */ MCD_OPC_Decode, + 241, + 83, + 55, // Opcode: MUL + /* 8729 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 8743 + /* 8734 */ MCD_OPC_CheckPredicate, + 22, + 158, + 31, + 0, // Skip to: 16833 + /* 8739 */ MCD_OPC_Decode, + 254, + 89, + 55, // Opcode: XPERMW + /* 8743 */ MCD_OPC_FilterValue, + 32, + 149, + 31, + 0, // Skip to: 16833 + /* 8748 */ MCD_OPC_Decode, + 180, + 84, + 55, // Opcode: SUB + /* 8752 */ MCD_OPC_FilterValue, + 1, + 154, + 0, + 0, // Skip to: 8911 + /* 8757 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 8760 */ MCD_OPC_FilterValue, + 0, + 82, + 0, + 0, // Skip to: 8847 + /* 8765 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 8768 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 8777 + /* 8773 */ MCD_OPC_Decode, + 162, + 84, + 55, // Opcode: SLL + /* 8777 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8791 + /* 8782 */ MCD_OPC_CheckPredicate, + 10, + 110, + 31, + 0, // Skip to: 16833 + /* 8787 */ MCD_OPC_Decode, + 159, + 84, + 55, // Opcode: SHFL + /* 8791 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 8805 + /* 8796 */ MCD_OPC_CheckPredicate, + 11, + 96, + 31, + 0, // Skip to: 16833 + /* 8801 */ MCD_OPC_Decode, + 136, + 82, + 55, // Opcode: BSET + /* 8805 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 8819 + /* 8810 */ MCD_OPC_CheckPredicate, + 11, + 82, + 31, + 0, // Skip to: 16833 + /* 8815 */ MCD_OPC_Decode, + 243, + 81, + 55, // Opcode: BCLR + /* 8819 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 8833 + /* 8824 */ MCD_OPC_CheckPredicate, + 16, + 68, + 31, + 0, // Skip to: 16833 + /* 8829 */ MCD_OPC_Decode, + 133, + 84, + 55, // Opcode: ROL + /* 8833 */ MCD_OPC_FilterValue, + 13, + 59, + 31, + 0, // Skip to: 16833 + /* 8838 */ MCD_OPC_CheckPredicate, + 11, + 54, + 31, + 0, // Skip to: 16833 + /* 8843 */ MCD_OPC_Decode, + 128, + 82, + 55, // Opcode: BINV + /* 8847 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 8883 + /* 8852 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 8855 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 8869 + /* 8860 */ MCD_OPC_CheckPredicate, + 28, + 32, + 31, + 0, // Skip to: 16833 + /* 8865 */ MCD_OPC_Decode, + 242, + 83, + 55, // Opcode: MULH + /* 8869 */ MCD_OPC_FilterValue, + 1, + 23, + 31, + 0, // Skip to: 16833 + /* 8874 */ MCD_OPC_CheckPredicate, + 29, + 18, + 31, + 0, // Skip to: 16833 + /* 8879 */ MCD_OPC_Decode, + 138, + 82, + 55, // Opcode: CLMUL + /* 8883 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 8897 + /* 8888 */ MCD_OPC_CheckPredicate, + 19, + 4, + 31, + 0, // Skip to: 16833 + /* 8893 */ MCD_OPC_Decode, + 189, + 83, + 56, // Opcode: FSL + /* 8897 */ MCD_OPC_FilterValue, + 3, + 251, + 30, + 0, // Skip to: 16833 + /* 8902 */ MCD_OPC_CheckPredicate, + 19, + 246, + 30, + 0, // Skip to: 16833 + /* 8907 */ MCD_OPC_Decode, + 143, + 82, + 56, // Opcode: CMIX + /* 8911 */ MCD_OPC_FilterValue, + 2, + 68, + 0, + 0, // Skip to: 8984 + /* 8916 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 8919 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 8928 + /* 8924 */ MCD_OPC_Decode, + 167, + 84, + 55, // Opcode: SLT + /* 8928 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 8942 + /* 8933 */ MCD_OPC_CheckPredicate, + 28, + 215, + 30, + 0, // Skip to: 16833 + /* 8938 */ MCD_OPC_Decode, + 243, + 83, + 55, // Opcode: MULHSU + /* 8942 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 8956 + /* 8947 */ MCD_OPC_CheckPredicate, + 29, + 201, + 30, + 0, // Skip to: 16833 + /* 8952 */ MCD_OPC_Decode, + 140, + 82, + 55, // Opcode: CLMULR + /* 8956 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 8970 + /* 8961 */ MCD_OPC_CheckPredicate, + 30, + 187, + 30, + 0, // Skip to: 16833 + /* 8966 */ MCD_OPC_Decode, + 153, + 84, + 55, // Opcode: SH1ADD + /* 8970 */ MCD_OPC_FilterValue, + 20, + 178, + 30, + 0, // Skip to: 16833 + /* 8975 */ MCD_OPC_CheckPredicate, + 10, + 173, + 30, + 0, // Skip to: 16833 + /* 8980 */ MCD_OPC_Decode, + 253, + 89, + 55, // Opcode: XPERMN + /* 8984 */ MCD_OPC_FilterValue, + 3, + 68, + 0, + 0, // Skip to: 9057 + /* 8989 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 8992 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 9001 + /* 8997 */ MCD_OPC_Decode, + 170, + 84, + 55, // Opcode: SLTU + /* 9001 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9015 + /* 9006 */ MCD_OPC_CheckPredicate, + 28, + 142, + 30, + 0, // Skip to: 16833 + /* 9011 */ MCD_OPC_Decode, + 244, + 83, + 55, // Opcode: MULHU + /* 9015 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 9029 + /* 9020 */ MCD_OPC_CheckPredicate, + 13, + 128, + 30, + 0, // Skip to: 16833 + /* 9025 */ MCD_OPC_Decode, + 133, + 82, + 55, // Opcode: BMATOR + /* 9029 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 9043 + /* 9034 */ MCD_OPC_CheckPredicate, + 29, + 114, + 30, + 0, // Skip to: 16833 + /* 9039 */ MCD_OPC_Decode, + 139, + 82, + 55, // Opcode: CLMULH + /* 9043 */ MCD_OPC_FilterValue, + 36, + 105, + 30, + 0, // Skip to: 16833 + /* 9048 */ MCD_OPC_CheckPredicate, + 13, + 100, + 30, + 0, // Skip to: 16833 + /* 9053 */ MCD_OPC_Decode, + 134, + 82, + 55, // Opcode: BMATXOR + /* 9057 */ MCD_OPC_FilterValue, + 4, + 126, + 0, + 0, // Skip to: 9188 + /* 9062 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 9065 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 9074 + /* 9070 */ MCD_OPC_Decode, + 249, + 89, + 55, // Opcode: XOR + /* 9074 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9088 + /* 9079 */ MCD_OPC_CheckPredicate, + 28, + 69, + 30, + 0, // Skip to: 16833 + /* 9084 */ MCD_OPC_Decode, + 218, + 82, + 55, // Opcode: DIV + /* 9088 */ MCD_OPC_FilterValue, + 4, + 25, + 0, + 0, // Skip to: 9118 + /* 9093 */ MCD_OPC_CheckPredicate, + 17, + 11, + 0, + 0, // Skip to: 9109 + /* 9098 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 4, + 0, + 0, // Skip to: 9109 + /* 9105 */ MCD_OPC_Decode, + 255, + 89, + 45, // Opcode: ZEXTH_RV32 + /* 9109 */ MCD_OPC_CheckPredicate, + 10, + 39, + 30, + 0, // Skip to: 16833 + /* 9114 */ MCD_OPC_Decode, + 250, + 83, + 55, // Opcode: PACK + /* 9118 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 9132 + /* 9123 */ MCD_OPC_CheckPredicate, + 12, + 25, + 30, + 0, // Skip to: 16833 + /* 9128 */ MCD_OPC_Decode, + 238, + 83, + 55, // Opcode: MIN + /* 9132 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 9146 + /* 9137 */ MCD_OPC_CheckPredicate, + 30, + 11, + 30, + 0, // Skip to: 16833 + /* 9142 */ MCD_OPC_Decode, + 155, + 84, + 55, // Opcode: SH2ADD + /* 9146 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 9160 + /* 9151 */ MCD_OPC_CheckPredicate, + 10, + 253, + 29, + 0, // Skip to: 16833 + /* 9156 */ MCD_OPC_Decode, + 251, + 89, + 55, // Opcode: XPERMB + /* 9160 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 9174 + /* 9165 */ MCD_OPC_CheckPredicate, + 16, + 239, + 29, + 0, // Skip to: 16833 + /* 9170 */ MCD_OPC_Decode, + 248, + 89, + 55, // Opcode: XNOR + /* 9174 */ MCD_OPC_FilterValue, + 36, + 230, + 29, + 0, // Skip to: 16833 + /* 9179 */ MCD_OPC_CheckPredicate, + 10, + 225, + 29, + 0, // Skip to: 16833 + /* 9184 */ MCD_OPC_Decode, + 252, + 83, + 55, // Opcode: PACKU + /* 9188 */ MCD_OPC_FilterValue, + 5, + 163, + 0, + 0, // Skip to: 9356 + /* 9193 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 9196 */ MCD_OPC_FilterValue, + 0, + 91, + 0, + 0, // Skip to: 9292 + /* 9201 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 9204 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 9213 + /* 9209 */ MCD_OPC_Decode, + 176, + 84, + 55, // Opcode: SRL + /* 9213 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9227 + /* 9218 */ MCD_OPC_CheckPredicate, + 10, + 186, + 29, + 0, // Skip to: 16833 + /* 9223 */ MCD_OPC_Decode, + 184, + 84, + 55, // Opcode: UNSHFL + /* 9227 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 9241 + /* 9232 */ MCD_OPC_CheckPredicate, + 10, + 172, + 29, + 0, // Skip to: 16833 + /* 9237 */ MCD_OPC_Decode, + 202, + 83, + 55, // Opcode: GORC + /* 9241 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 9250 + /* 9246 */ MCD_OPC_Decode, + 171, + 84, + 55, // Opcode: SRA + /* 9250 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 9264 + /* 9255 */ MCD_OPC_CheckPredicate, + 11, + 149, + 29, + 0, // Skip to: 16833 + /* 9260 */ MCD_OPC_Decode, + 250, + 81, + 55, // Opcode: BEXT + /* 9264 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 9278 + /* 9269 */ MCD_OPC_CheckPredicate, + 16, + 135, + 29, + 0, // Skip to: 16833 + /* 9274 */ MCD_OPC_Decode, + 135, + 84, + 55, // Opcode: ROR + /* 9278 */ MCD_OPC_FilterValue, + 13, + 126, + 29, + 0, // Skip to: 16833 + /* 9283 */ MCD_OPC_CheckPredicate, + 10, + 121, + 29, + 0, // Skip to: 16833 + /* 9288 */ MCD_OPC_Decode, + 206, + 83, + 55, // Opcode: GREV + /* 9292 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 9328 + /* 9297 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 9300 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 9314 + /* 9305 */ MCD_OPC_CheckPredicate, + 28, + 99, + 29, + 0, // Skip to: 16833 + /* 9310 */ MCD_OPC_Decode, + 219, + 82, + 55, // Opcode: DIVU + /* 9314 */ MCD_OPC_FilterValue, + 1, + 90, + 29, + 0, // Skip to: 16833 + /* 9319 */ MCD_OPC_CheckPredicate, + 12, + 85, + 29, + 0, // Skip to: 16833 + /* 9324 */ MCD_OPC_Decode, + 239, + 83, + 55, // Opcode: MINU + /* 9328 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 9342 + /* 9333 */ MCD_OPC_CheckPredicate, + 19, + 71, + 29, + 0, // Skip to: 16833 + /* 9338 */ MCD_OPC_Decode, + 194, + 83, + 56, // Opcode: FSR + /* 9342 */ MCD_OPC_FilterValue, + 3, + 62, + 29, + 0, // Skip to: 16833 + /* 9347 */ MCD_OPC_CheckPredicate, + 19, + 57, + 29, + 0, // Skip to: 16833 + /* 9352 */ MCD_OPC_Decode, + 144, + 82, + 56, // Opcode: CMOV + /* 9356 */ MCD_OPC_FilterValue, + 6, + 110, + 0, + 0, // Skip to: 9471 + /* 9361 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 9364 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 9373 + /* 9369 */ MCD_OPC_Decode, + 246, + 83, + 55, // Opcode: OR + /* 9373 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9387 + /* 9378 */ MCD_OPC_CheckPredicate, + 28, + 26, + 29, + 0, // Skip to: 16833 + /* 9383 */ MCD_OPC_Decode, + 255, + 83, + 55, // Opcode: REM + /* 9387 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 9401 + /* 9392 */ MCD_OPC_CheckPredicate, + 31, + 12, + 29, + 0, // Skip to: 16833 + /* 9397 */ MCD_OPC_Decode, + 245, + 81, + 55, // Opcode: BCOMPRESS + /* 9401 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 9415 + /* 9406 */ MCD_OPC_CheckPredicate, + 12, + 254, + 28, + 0, // Skip to: 16833 + /* 9411 */ MCD_OPC_Decode, + 236, + 83, + 55, // Opcode: MAX + /* 9415 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 9429 + /* 9420 */ MCD_OPC_CheckPredicate, + 30, + 240, + 28, + 0, // Skip to: 16833 + /* 9425 */ MCD_OPC_Decode, + 157, + 84, + 55, // Opcode: SH3ADD + /* 9429 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 9443 + /* 9434 */ MCD_OPC_CheckPredicate, + 10, + 226, + 28, + 0, // Skip to: 16833 + /* 9439 */ MCD_OPC_Decode, + 252, + 89, + 55, // Opcode: XPERMH + /* 9443 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 9457 + /* 9448 */ MCD_OPC_CheckPredicate, + 16, + 212, + 28, + 0, // Skip to: 16833 + /* 9453 */ MCD_OPC_Decode, + 249, + 83, + 55, // Opcode: ORN + /* 9457 */ MCD_OPC_FilterValue, + 36, + 203, + 28, + 0, // Skip to: 16833 + /* 9462 */ MCD_OPC_CheckPredicate, + 31, + 198, + 28, + 0, // Skip to: 16833 + /* 9467 */ MCD_OPC_Decode, + 247, + 81, + 55, // Opcode: BDECOMPRESS + /* 9471 */ MCD_OPC_FilterValue, + 7, + 189, + 28, + 0, // Skip to: 16833 + /* 9476 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 9479 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 9488 + /* 9484 */ MCD_OPC_Decode, + 239, + 81, + 55, // Opcode: AND + /* 9488 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9502 + /* 9493 */ MCD_OPC_CheckPredicate, + 28, + 167, + 28, + 0, // Skip to: 16833 + /* 9498 */ MCD_OPC_Decode, + 128, + 84, + 55, // Opcode: REMU + /* 9502 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 9516 + /* 9507 */ MCD_OPC_CheckPredicate, + 10, + 153, + 28, + 0, // Skip to: 16833 + /* 9512 */ MCD_OPC_Decode, + 251, + 83, + 55, // Opcode: PACKH + /* 9516 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 9530 + /* 9521 */ MCD_OPC_CheckPredicate, + 12, + 139, + 28, + 0, // Skip to: 16833 + /* 9526 */ MCD_OPC_Decode, + 237, + 83, + 55, // Opcode: MAXU + /* 9530 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 9544 + /* 9535 */ MCD_OPC_CheckPredicate, + 16, + 125, + 28, + 0, // Skip to: 16833 + /* 9540 */ MCD_OPC_Decode, + 241, + 81, + 55, // Opcode: ANDN + /* 9544 */ MCD_OPC_FilterValue, + 36, + 116, + 28, + 0, // Skip to: 16833 + /* 9549 */ MCD_OPC_CheckPredicate, + 32, + 111, + 28, + 0, // Skip to: 16833 + /* 9554 */ MCD_OPC_Decode, + 252, + 81, + 55, // Opcode: BFP + /* 9558 */ MCD_OPC_FilterValue, + 55, + 4, + 0, + 0, // Skip to: 9567 + /* 9563 */ MCD_OPC_Decode, + 233, + 83, + 47, // Opcode: LUI + /* 9567 */ MCD_OPC_FilterValue, + 59, + 219, + 1, + 0, // Skip to: 10047 + /* 9572 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 9575 */ MCD_OPC_FilterValue, + 0, + 59, + 0, + 0, // Skip to: 9639 + /* 9580 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 9583 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 9597 + /* 9588 */ MCD_OPC_CheckPredicate, + 4, + 72, + 28, + 0, // Skip to: 16833 + /* 9593 */ MCD_OPC_Decode, + 166, + 81, + 55, // Opcode: ADDW + /* 9597 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9611 + /* 9602 */ MCD_OPC_CheckPredicate, + 33, + 58, + 28, + 0, // Skip to: 16833 + /* 9607 */ MCD_OPC_Decode, + 245, + 83, + 55, // Opcode: MULW + /* 9611 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 9625 + /* 9616 */ MCD_OPC_CheckPredicate, + 20, + 44, + 28, + 0, // Skip to: 16833 + /* 9621 */ MCD_OPC_Decode, + 165, + 81, + 55, // Opcode: ADDUW + /* 9625 */ MCD_OPC_FilterValue, + 32, + 35, + 28, + 0, // Skip to: 16833 + /* 9630 */ MCD_OPC_CheckPredicate, + 4, + 30, + 28, + 0, // Skip to: 16833 + /* 9635 */ MCD_OPC_Decode, + 181, + 84, + 55, // Opcode: SUBW + /* 9639 */ MCD_OPC_FilterValue, + 1, + 67, + 0, + 0, // Skip to: 9711 + /* 9644 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 9647 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 9697 + /* 9652 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 9655 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 9669 + /* 9660 */ MCD_OPC_CheckPredicate, + 4, + 0, + 28, + 0, // Skip to: 16833 + /* 9665 */ MCD_OPC_Decode, + 166, + 84, + 55, // Opcode: SLLW + /* 9669 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9683 + /* 9674 */ MCD_OPC_CheckPredicate, + 22, + 242, + 27, + 0, // Skip to: 16833 + /* 9679 */ MCD_OPC_Decode, + 161, + 84, + 55, // Opcode: SHFLW + /* 9683 */ MCD_OPC_FilterValue, + 12, + 233, + 27, + 0, // Skip to: 16833 + /* 9688 */ MCD_OPC_CheckPredicate, + 18, + 228, + 27, + 0, // Skip to: 16833 + /* 9693 */ MCD_OPC_Decode, + 134, + 84, + 55, // Opcode: ROLW + /* 9697 */ MCD_OPC_FilterValue, + 2, + 219, + 27, + 0, // Skip to: 16833 + /* 9702 */ MCD_OPC_CheckPredicate, + 23, + 214, + 27, + 0, // Skip to: 16833 + /* 9707 */ MCD_OPC_Decode, + 190, + 83, + 56, // Opcode: FSLW + /* 9711 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 9732 + /* 9716 */ MCD_OPC_CheckPredicate, + 20, + 200, + 27, + 0, // Skip to: 16833 + /* 9721 */ MCD_OPC_CheckField, + 25, + 7, + 16, + 193, + 27, + 0, // Skip to: 16833 + /* 9728 */ MCD_OPC_Decode, + 154, + 84, + 55, // Opcode: SH1ADDUW + /* 9732 */ MCD_OPC_FilterValue, + 4, + 75, + 0, + 0, // Skip to: 9812 + /* 9737 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 9740 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9754 + /* 9745 */ MCD_OPC_CheckPredicate, + 33, + 171, + 27, + 0, // Skip to: 16833 + /* 9750 */ MCD_OPC_Decode, + 221, + 82, + 55, // Opcode: DIVW + /* 9754 */ MCD_OPC_FilterValue, + 4, + 25, + 0, + 0, // Skip to: 9784 + /* 9759 */ MCD_OPC_CheckPredicate, + 18, + 11, + 0, + 0, // Skip to: 9775 + /* 9764 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 4, + 0, + 0, // Skip to: 9775 + /* 9771 */ MCD_OPC_Decode, + 128, + 90, + 45, // Opcode: ZEXTH_RV64 + /* 9775 */ MCD_OPC_CheckPredicate, + 22, + 141, + 27, + 0, // Skip to: 16833 + /* 9780 */ MCD_OPC_Decode, + 254, + 83, + 55, // Opcode: PACKW + /* 9784 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 9798 + /* 9789 */ MCD_OPC_CheckPredicate, + 20, + 127, + 27, + 0, // Skip to: 16833 + /* 9794 */ MCD_OPC_Decode, + 156, + 84, + 55, // Opcode: SH2ADDUW + /* 9798 */ MCD_OPC_FilterValue, + 36, + 118, + 27, + 0, // Skip to: 16833 + /* 9803 */ MCD_OPC_CheckPredicate, + 22, + 113, + 27, + 0, // Skip to: 16833 + /* 9808 */ MCD_OPC_Decode, + 253, + 83, + 55, // Opcode: PACKUW + /* 9812 */ MCD_OPC_FilterValue, + 5, + 130, + 0, + 0, // Skip to: 9947 + /* 9817 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 9820 */ MCD_OPC_FilterValue, + 0, + 87, + 0, + 0, // Skip to: 9912 + /* 9825 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 9828 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 9842 + /* 9833 */ MCD_OPC_CheckPredicate, + 4, + 83, + 27, + 0, // Skip to: 16833 + /* 9838 */ MCD_OPC_Decode, + 179, + 84, + 55, // Opcode: SRLW + /* 9842 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9856 + /* 9847 */ MCD_OPC_CheckPredicate, + 22, + 69, + 27, + 0, // Skip to: 16833 + /* 9852 */ MCD_OPC_Decode, + 186, + 84, + 55, // Opcode: UNSHFLW + /* 9856 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 9870 + /* 9861 */ MCD_OPC_CheckPredicate, + 22, + 55, + 27, + 0, // Skip to: 16833 + /* 9866 */ MCD_OPC_Decode, + 205, + 83, + 55, // Opcode: GORCW + /* 9870 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 9884 + /* 9875 */ MCD_OPC_CheckPredicate, + 4, + 41, + 27, + 0, // Skip to: 16833 + /* 9880 */ MCD_OPC_Decode, + 174, + 84, + 55, // Opcode: SRAW + /* 9884 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 9898 + /* 9889 */ MCD_OPC_CheckPredicate, + 18, + 27, + 27, + 0, // Skip to: 16833 + /* 9894 */ MCD_OPC_Decode, + 138, + 84, + 55, // Opcode: RORW + /* 9898 */ MCD_OPC_FilterValue, + 13, + 18, + 27, + 0, // Skip to: 16833 + /* 9903 */ MCD_OPC_CheckPredicate, + 22, + 13, + 27, + 0, // Skip to: 16833 + /* 9908 */ MCD_OPC_Decode, + 209, + 83, + 55, // Opcode: GREVW + /* 9912 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 9933 + /* 9917 */ MCD_OPC_CheckPredicate, + 33, + 255, + 26, + 0, // Skip to: 16833 + /* 9922 */ MCD_OPC_CheckField, + 27, + 5, + 0, + 248, + 26, + 0, // Skip to: 16833 + /* 9929 */ MCD_OPC_Decode, + 220, + 82, + 55, // Opcode: DIVUW + /* 9933 */ MCD_OPC_FilterValue, + 2, + 239, + 26, + 0, // Skip to: 16833 + /* 9938 */ MCD_OPC_CheckPredicate, + 23, + 234, + 26, + 0, // Skip to: 16833 + /* 9943 */ MCD_OPC_Decode, + 197, + 83, + 56, // Opcode: FSRW + /* 9947 */ MCD_OPC_FilterValue, + 6, + 59, + 0, + 0, // Skip to: 10011 + /* 9952 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 9955 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 9969 + /* 9960 */ MCD_OPC_CheckPredicate, + 33, + 212, + 26, + 0, // Skip to: 16833 + /* 9965 */ MCD_OPC_Decode, + 130, + 84, + 55, // Opcode: REMW + /* 9969 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 9983 + /* 9974 */ MCD_OPC_CheckPredicate, + 34, + 198, + 26, + 0, // Skip to: 16833 + /* 9979 */ MCD_OPC_Decode, + 246, + 81, + 55, // Opcode: BCOMPRESSW + /* 9983 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 9997 + /* 9988 */ MCD_OPC_CheckPredicate, + 20, + 184, + 26, + 0, // Skip to: 16833 + /* 9993 */ MCD_OPC_Decode, + 158, + 84, + 55, // Opcode: SH3ADDUW + /* 9997 */ MCD_OPC_FilterValue, + 36, + 175, + 26, + 0, // Skip to: 16833 + /* 10002 */ MCD_OPC_CheckPredicate, + 34, + 170, + 26, + 0, // Skip to: 16833 + /* 10007 */ MCD_OPC_Decode, + 248, + 81, + 55, // Opcode: BDECOMPRESSW + /* 10011 */ MCD_OPC_FilterValue, + 7, + 161, + 26, + 0, // Skip to: 16833 + /* 10016 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 10019 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10033 + /* 10024 */ MCD_OPC_CheckPredicate, + 33, + 148, + 26, + 0, // Skip to: 16833 + /* 10029 */ MCD_OPC_Decode, + 129, + 84, + 55, // Opcode: REMUW + /* 10033 */ MCD_OPC_FilterValue, + 36, + 139, + 26, + 0, // Skip to: 16833 + /* 10038 */ MCD_OPC_CheckPredicate, + 35, + 134, + 26, + 0, // Skip to: 16833 + /* 10043 */ MCD_OPC_Decode, + 253, + 81, + 55, // Opcode: BFPW + /* 10047 */ MCD_OPC_FilterValue, + 67, + 45, + 0, + 0, // Skip to: 10097 + /* 10052 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 10055 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10069 + /* 10060 */ MCD_OPC_CheckPredicate, + 8, + 112, + 26, + 0, // Skip to: 16833 + /* 10065 */ MCD_OPC_Decode, + 153, + 83, + 57, // Opcode: FMADD_S + /* 10069 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10083 + /* 10074 */ MCD_OPC_CheckPredicate, + 9, + 98, + 26, + 0, // Skip to: 16833 + /* 10079 */ MCD_OPC_Decode, + 151, + 83, + 58, // Opcode: FMADD_D + /* 10083 */ MCD_OPC_FilterValue, + 2, + 89, + 26, + 0, // Skip to: 16833 + /* 10088 */ MCD_OPC_CheckPredicate, + 36, + 84, + 26, + 0, // Skip to: 16833 + /* 10093 */ MCD_OPC_Decode, + 152, + 83, + 59, // Opcode: FMADD_H + /* 10097 */ MCD_OPC_FilterValue, + 71, + 45, + 0, + 0, // Skip to: 10147 + /* 10102 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 10105 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10119 + /* 10110 */ MCD_OPC_CheckPredicate, + 8, + 62, + 26, + 0, // Skip to: 16833 + /* 10115 */ MCD_OPC_Decode, + 162, + 83, + 57, // Opcode: FMSUB_S + /* 10119 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10133 + /* 10124 */ MCD_OPC_CheckPredicate, + 9, + 48, + 26, + 0, // Skip to: 16833 + /* 10129 */ MCD_OPC_Decode, + 160, + 83, + 58, // Opcode: FMSUB_D + /* 10133 */ MCD_OPC_FilterValue, + 2, + 39, + 26, + 0, // Skip to: 16833 + /* 10138 */ MCD_OPC_CheckPredicate, + 36, + 34, + 26, + 0, // Skip to: 16833 + /* 10143 */ MCD_OPC_Decode, + 161, + 83, + 59, // Opcode: FMSUB_H + /* 10147 */ MCD_OPC_FilterValue, + 75, + 45, + 0, + 0, // Skip to: 10197 + /* 10152 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 10155 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10169 + /* 10160 */ MCD_OPC_CheckPredicate, + 8, + 12, + 26, + 0, // Skip to: 16833 + /* 10165 */ MCD_OPC_Decode, + 177, + 83, + 57, // Opcode: FNMSUB_S + /* 10169 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10183 + /* 10174 */ MCD_OPC_CheckPredicate, + 9, + 254, + 25, + 0, // Skip to: 16833 + /* 10179 */ MCD_OPC_Decode, + 175, + 83, + 58, // Opcode: FNMSUB_D + /* 10183 */ MCD_OPC_FilterValue, + 2, + 245, + 25, + 0, // Skip to: 16833 + /* 10188 */ MCD_OPC_CheckPredicate, + 36, + 240, + 25, + 0, // Skip to: 16833 + /* 10193 */ MCD_OPC_Decode, + 176, + 83, + 59, // Opcode: FNMSUB_H + /* 10197 */ MCD_OPC_FilterValue, + 79, + 45, + 0, + 0, // Skip to: 10247 + /* 10202 */ MCD_OPC_ExtractField, + 25, + 2, // Inst{26-25} ... + /* 10205 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10219 + /* 10210 */ MCD_OPC_CheckPredicate, + 8, + 218, + 25, + 0, // Skip to: 16833 + /* 10215 */ MCD_OPC_Decode, + 174, + 83, + 57, // Opcode: FNMADD_S + /* 10219 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10233 + /* 10224 */ MCD_OPC_CheckPredicate, + 9, + 204, + 25, + 0, // Skip to: 16833 + /* 10229 */ MCD_OPC_Decode, + 172, + 83, + 58, // Opcode: FNMADD_D + /* 10233 */ MCD_OPC_FilterValue, + 2, + 195, + 25, + 0, // Skip to: 16833 + /* 10238 */ MCD_OPC_CheckPredicate, + 36, + 190, + 25, + 0, // Skip to: 16833 + /* 10243 */ MCD_OPC_Decode, + 173, + 83, + 59, // Opcode: FNMADD_H + /* 10247 */ MCD_OPC_FilterValue, + 83, + 123, + 5, + 0, // Skip to: 11655 + /* 10252 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 10255 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10269 + /* 10260 */ MCD_OPC_CheckPredicate, + 8, + 168, + 25, + 0, // Skip to: 16833 + /* 10265 */ MCD_OPC_Decode, + 227, + 82, + 60, // Opcode: FADD_S + /* 10269 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10283 + /* 10274 */ MCD_OPC_CheckPredicate, + 9, + 154, + 25, + 0, // Skip to: 16833 + /* 10279 */ MCD_OPC_Decode, + 225, + 82, + 61, // Opcode: FADD_D + /* 10283 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 10297 + /* 10288 */ MCD_OPC_CheckPredicate, + 36, + 140, + 25, + 0, // Skip to: 16833 + /* 10293 */ MCD_OPC_Decode, + 226, + 82, + 62, // Opcode: FADD_H + /* 10297 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 10311 + /* 10302 */ MCD_OPC_CheckPredicate, + 8, + 126, + 25, + 0, // Skip to: 16833 + /* 10307 */ MCD_OPC_Decode, + 200, + 83, + 60, // Opcode: FSUB_S + /* 10311 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 10325 + /* 10316 */ MCD_OPC_CheckPredicate, + 9, + 112, + 25, + 0, // Skip to: 16833 + /* 10321 */ MCD_OPC_Decode, + 198, + 83, + 61, // Opcode: FSUB_D + /* 10325 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 10339 + /* 10330 */ MCD_OPC_CheckPredicate, + 36, + 98, + 25, + 0, // Skip to: 16833 + /* 10335 */ MCD_OPC_Decode, + 199, + 83, + 62, // Opcode: FSUB_H + /* 10339 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 10353 + /* 10344 */ MCD_OPC_CheckPredicate, + 8, + 84, + 25, + 0, // Skip to: 16833 + /* 10349 */ MCD_OPC_Decode, + 165, + 83, + 60, // Opcode: FMUL_S + /* 10353 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 10367 + /* 10358 */ MCD_OPC_CheckPredicate, + 9, + 70, + 25, + 0, // Skip to: 16833 + /* 10363 */ MCD_OPC_Decode, + 163, + 83, + 61, // Opcode: FMUL_D + /* 10367 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 10381 + /* 10372 */ MCD_OPC_CheckPredicate, + 36, + 56, + 25, + 0, // Skip to: 16833 + /* 10377 */ MCD_OPC_Decode, + 164, + 83, + 62, // Opcode: FMUL_H + /* 10381 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 10395 + /* 10386 */ MCD_OPC_CheckPredicate, + 8, + 42, + 25, + 0, // Skip to: 16833 + /* 10391 */ MCD_OPC_Decode, + 135, + 83, + 60, // Opcode: FDIV_S + /* 10395 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 10409 + /* 10400 */ MCD_OPC_CheckPredicate, + 9, + 28, + 25, + 0, // Skip to: 16833 + /* 10405 */ MCD_OPC_Decode, + 133, + 83, + 61, // Opcode: FDIV_D + /* 10409 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 10423 + /* 10414 */ MCD_OPC_CheckPredicate, + 36, + 14, + 25, + 0, // Skip to: 16833 + /* 10419 */ MCD_OPC_Decode, + 134, + 83, + 62, // Opcode: FDIV_H + /* 10423 */ MCD_OPC_FilterValue, + 16, + 45, + 0, + 0, // Skip to: 10473 + /* 10428 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 10431 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10445 + /* 10436 */ MCD_OPC_CheckPredicate, + 8, + 248, + 24, + 0, // Skip to: 16833 + /* 10441 */ MCD_OPC_Decode, + 187, + 83, + 63, // Opcode: FSGNJ_S + /* 10445 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10459 + /* 10450 */ MCD_OPC_CheckPredicate, + 8, + 234, + 24, + 0, // Skip to: 16833 + /* 10455 */ MCD_OPC_Decode, + 181, + 83, + 63, // Opcode: FSGNJN_S + /* 10459 */ MCD_OPC_FilterValue, + 2, + 225, + 24, + 0, // Skip to: 16833 + /* 10464 */ MCD_OPC_CheckPredicate, + 8, + 220, + 24, + 0, // Skip to: 16833 + /* 10469 */ MCD_OPC_Decode, + 184, + 83, + 63, // Opcode: FSGNJX_S + /* 10473 */ MCD_OPC_FilterValue, + 17, + 45, + 0, + 0, // Skip to: 10523 + /* 10478 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 10481 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10495 + /* 10486 */ MCD_OPC_CheckPredicate, + 9, + 198, + 24, + 0, // Skip to: 16833 + /* 10491 */ MCD_OPC_Decode, + 185, + 83, + 64, // Opcode: FSGNJ_D + /* 10495 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10509 + /* 10500 */ MCD_OPC_CheckPredicate, + 9, + 184, + 24, + 0, // Skip to: 16833 + /* 10505 */ MCD_OPC_Decode, + 179, + 83, + 64, // Opcode: FSGNJN_D + /* 10509 */ MCD_OPC_FilterValue, + 2, + 175, + 24, + 0, // Skip to: 16833 + /* 10514 */ MCD_OPC_CheckPredicate, + 9, + 170, + 24, + 0, // Skip to: 16833 + /* 10519 */ MCD_OPC_Decode, + 182, + 83, + 64, // Opcode: FSGNJX_D + /* 10523 */ MCD_OPC_FilterValue, + 18, + 45, + 0, + 0, // Skip to: 10573 + /* 10528 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 10531 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10545 + /* 10536 */ MCD_OPC_CheckPredicate, + 36, + 148, + 24, + 0, // Skip to: 16833 + /* 10541 */ MCD_OPC_Decode, + 186, + 83, + 65, // Opcode: FSGNJ_H + /* 10545 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10559 + /* 10550 */ MCD_OPC_CheckPredicate, + 36, + 134, + 24, + 0, // Skip to: 16833 + /* 10555 */ MCD_OPC_Decode, + 180, + 83, + 65, // Opcode: FSGNJN_H + /* 10559 */ MCD_OPC_FilterValue, + 2, + 125, + 24, + 0, // Skip to: 16833 + /* 10564 */ MCD_OPC_CheckPredicate, + 36, + 120, + 24, + 0, // Skip to: 16833 + /* 10569 */ MCD_OPC_Decode, + 183, + 83, + 65, // Opcode: FSGNJX_H + /* 10573 */ MCD_OPC_FilterValue, + 20, + 31, + 0, + 0, // Skip to: 10609 + /* 10578 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 10581 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10595 + /* 10586 */ MCD_OPC_CheckPredicate, + 8, + 98, + 24, + 0, // Skip to: 16833 + /* 10591 */ MCD_OPC_Decode, + 159, + 83, + 63, // Opcode: FMIN_S + /* 10595 */ MCD_OPC_FilterValue, + 1, + 89, + 24, + 0, // Skip to: 16833 + /* 10600 */ MCD_OPC_CheckPredicate, + 8, + 84, + 24, + 0, // Skip to: 16833 + /* 10605 */ MCD_OPC_Decode, + 156, + 83, + 63, // Opcode: FMAX_S + /* 10609 */ MCD_OPC_FilterValue, + 21, + 31, + 0, + 0, // Skip to: 10645 + /* 10614 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 10617 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10631 + /* 10622 */ MCD_OPC_CheckPredicate, + 9, + 62, + 24, + 0, // Skip to: 16833 + /* 10627 */ MCD_OPC_Decode, + 157, + 83, + 64, // Opcode: FMIN_D + /* 10631 */ MCD_OPC_FilterValue, + 1, + 53, + 24, + 0, // Skip to: 16833 + /* 10636 */ MCD_OPC_CheckPredicate, + 9, + 48, + 24, + 0, // Skip to: 16833 + /* 10641 */ MCD_OPC_Decode, + 154, + 83, + 64, // Opcode: FMAX_D + /* 10645 */ MCD_OPC_FilterValue, + 22, + 31, + 0, + 0, // Skip to: 10681 + /* 10650 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 10653 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10667 + /* 10658 */ MCD_OPC_CheckPredicate, + 36, + 26, + 24, + 0, // Skip to: 16833 + /* 10663 */ MCD_OPC_Decode, + 158, + 83, + 65, // Opcode: FMIN_H + /* 10667 */ MCD_OPC_FilterValue, + 1, + 17, + 24, + 0, // Skip to: 16833 + /* 10672 */ MCD_OPC_CheckPredicate, + 36, + 12, + 24, + 0, // Skip to: 16833 + /* 10677 */ MCD_OPC_Decode, + 155, + 83, + 65, // Opcode: FMAX_H + /* 10681 */ MCD_OPC_FilterValue, + 32, + 38, + 0, + 0, // Skip to: 10724 + /* 10686 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 10689 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10703 + /* 10694 */ MCD_OPC_CheckPredicate, + 9, + 246, + 23, + 0, // Skip to: 16833 + /* 10699 */ MCD_OPC_Decode, + 249, + 82, + 66, // Opcode: FCVT_S_D + /* 10703 */ MCD_OPC_FilterValue, + 2, + 237, + 23, + 0, // Skip to: 16833 + /* 10708 */ MCD_OPC_CheckPredicate, + 7, + 232, + 23, + 0, // Skip to: 16833 + /* 10713 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 225, + 23, + 0, // Skip to: 16833 + /* 10720 */ MCD_OPC_Decode, + 250, + 82, + 67, // Opcode: FCVT_S_H + /* 10724 */ MCD_OPC_FilterValue, + 33, + 45, + 0, + 0, // Skip to: 10774 + /* 10729 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 10732 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 10753 + /* 10737 */ MCD_OPC_CheckPredicate, + 9, + 203, + 23, + 0, // Skip to: 16833 + /* 10742 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 196, + 23, + 0, // Skip to: 16833 + /* 10749 */ MCD_OPC_Decode, + 234, + 82, + 68, // Opcode: FCVT_D_S + /* 10753 */ MCD_OPC_FilterValue, + 2, + 187, + 23, + 0, // Skip to: 16833 + /* 10758 */ MCD_OPC_CheckPredicate, + 37, + 182, + 23, + 0, // Skip to: 16833 + /* 10763 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 175, + 23, + 0, // Skip to: 16833 + /* 10770 */ MCD_OPC_Decode, + 231, + 82, + 69, // Opcode: FCVT_D_H + /* 10774 */ MCD_OPC_FilterValue, + 34, + 31, + 0, + 0, // Skip to: 10810 + /* 10779 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 10782 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10796 + /* 10787 */ MCD_OPC_CheckPredicate, + 7, + 153, + 23, + 0, // Skip to: 16833 + /* 10792 */ MCD_OPC_Decode, + 240, + 82, + 70, // Opcode: FCVT_H_S + /* 10796 */ MCD_OPC_FilterValue, + 1, + 144, + 23, + 0, // Skip to: 16833 + /* 10801 */ MCD_OPC_CheckPredicate, + 37, + 139, + 23, + 0, // Skip to: 16833 + /* 10806 */ MCD_OPC_Decode, + 237, + 82, + 71, // Opcode: FCVT_H_D + /* 10810 */ MCD_OPC_FilterValue, + 44, + 16, + 0, + 0, // Skip to: 10831 + /* 10815 */ MCD_OPC_CheckPredicate, + 8, + 125, + 23, + 0, // Skip to: 16833 + /* 10820 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 118, + 23, + 0, // Skip to: 16833 + /* 10827 */ MCD_OPC_Decode, + 193, + 83, + 72, // Opcode: FSQRT_S + /* 10831 */ MCD_OPC_FilterValue, + 45, + 16, + 0, + 0, // Skip to: 10852 + /* 10836 */ MCD_OPC_CheckPredicate, + 9, + 104, + 23, + 0, // Skip to: 16833 + /* 10841 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 97, + 23, + 0, // Skip to: 16833 + /* 10848 */ MCD_OPC_Decode, + 191, + 83, + 73, // Opcode: FSQRT_D + /* 10852 */ MCD_OPC_FilterValue, + 46, + 16, + 0, + 0, // Skip to: 10873 + /* 10857 */ MCD_OPC_CheckPredicate, + 36, + 83, + 23, + 0, // Skip to: 16833 + /* 10862 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 76, + 23, + 0, // Skip to: 16833 + /* 10869 */ MCD_OPC_Decode, + 192, + 83, + 74, // Opcode: FSQRT_H + /* 10873 */ MCD_OPC_FilterValue, + 80, + 45, + 0, + 0, // Skip to: 10923 + /* 10878 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 10881 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10895 + /* 10886 */ MCD_OPC_CheckPredicate, + 8, + 54, + 23, + 0, // Skip to: 16833 + /* 10891 */ MCD_OPC_Decode, + 145, + 83, + 75, // Opcode: FLE_S + /* 10895 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10909 + /* 10900 */ MCD_OPC_CheckPredicate, + 8, + 40, + 23, + 0, // Skip to: 16833 + /* 10905 */ MCD_OPC_Decode, + 149, + 83, + 75, // Opcode: FLT_S + /* 10909 */ MCD_OPC_FilterValue, + 2, + 31, + 23, + 0, // Skip to: 16833 + /* 10914 */ MCD_OPC_CheckPredicate, + 8, + 26, + 23, + 0, // Skip to: 16833 + /* 10919 */ MCD_OPC_Decode, + 141, + 83, + 75, // Opcode: FEQ_S + /* 10923 */ MCD_OPC_FilterValue, + 81, + 45, + 0, + 0, // Skip to: 10973 + /* 10928 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 10931 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10945 + /* 10936 */ MCD_OPC_CheckPredicate, + 9, + 4, + 23, + 0, // Skip to: 16833 + /* 10941 */ MCD_OPC_Decode, + 143, + 83, + 76, // Opcode: FLE_D + /* 10945 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10959 + /* 10950 */ MCD_OPC_CheckPredicate, + 9, + 246, + 22, + 0, // Skip to: 16833 + /* 10955 */ MCD_OPC_Decode, + 147, + 83, + 76, // Opcode: FLT_D + /* 10959 */ MCD_OPC_FilterValue, + 2, + 237, + 22, + 0, // Skip to: 16833 + /* 10964 */ MCD_OPC_CheckPredicate, + 9, + 232, + 22, + 0, // Skip to: 16833 + /* 10969 */ MCD_OPC_Decode, + 139, + 83, + 76, // Opcode: FEQ_D + /* 10973 */ MCD_OPC_FilterValue, + 82, + 45, + 0, + 0, // Skip to: 11023 + /* 10978 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 10981 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 10995 + /* 10986 */ MCD_OPC_CheckPredicate, + 36, + 210, + 22, + 0, // Skip to: 16833 + /* 10991 */ MCD_OPC_Decode, + 144, + 83, + 77, // Opcode: FLE_H + /* 10995 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 11009 + /* 11000 */ MCD_OPC_CheckPredicate, + 36, + 196, + 22, + 0, // Skip to: 16833 + /* 11005 */ MCD_OPC_Decode, + 148, + 83, + 77, // Opcode: FLT_H + /* 11009 */ MCD_OPC_FilterValue, + 2, + 187, + 22, + 0, // Skip to: 16833 + /* 11014 */ MCD_OPC_CheckPredicate, + 36, + 182, + 22, + 0, // Skip to: 16833 + /* 11019 */ MCD_OPC_Decode, + 140, + 83, + 77, // Opcode: FEQ_H + /* 11023 */ MCD_OPC_FilterValue, + 96, + 59, + 0, + 0, // Skip to: 11087 + /* 11028 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 11031 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11045 + /* 11036 */ MCD_OPC_CheckPredicate, + 8, + 160, + 22, + 0, // Skip to: 16833 + /* 11041 */ MCD_OPC_Decode, + 132, + 83, + 78, // Opcode: FCVT_W_S + /* 11045 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 11059 + /* 11050 */ MCD_OPC_CheckPredicate, + 8, + 146, + 22, + 0, // Skip to: 16833 + /* 11055 */ MCD_OPC_Decode, + 129, + 83, + 78, // Opcode: FCVT_WU_S + /* 11059 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 11073 + /* 11064 */ MCD_OPC_CheckPredicate, + 38, + 132, + 22, + 0, // Skip to: 16833 + /* 11069 */ MCD_OPC_Decode, + 248, + 82, + 78, // Opcode: FCVT_L_S + /* 11073 */ MCD_OPC_FilterValue, + 3, + 123, + 22, + 0, // Skip to: 16833 + /* 11078 */ MCD_OPC_CheckPredicate, + 38, + 118, + 22, + 0, // Skip to: 16833 + /* 11083 */ MCD_OPC_Decode, + 245, + 82, + 78, // Opcode: FCVT_LU_S + /* 11087 */ MCD_OPC_FilterValue, + 97, + 59, + 0, + 0, // Skip to: 11151 + /* 11092 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 11095 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11109 + /* 11100 */ MCD_OPC_CheckPredicate, + 9, + 96, + 22, + 0, // Skip to: 16833 + /* 11105 */ MCD_OPC_Decode, + 130, + 83, + 79, // Opcode: FCVT_W_D + /* 11109 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 11123 + /* 11114 */ MCD_OPC_CheckPredicate, + 9, + 82, + 22, + 0, // Skip to: 16833 + /* 11119 */ MCD_OPC_Decode, + 255, + 82, + 79, // Opcode: FCVT_WU_D + /* 11123 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 11137 + /* 11128 */ MCD_OPC_CheckPredicate, + 39, + 68, + 22, + 0, // Skip to: 16833 + /* 11133 */ MCD_OPC_Decode, + 246, + 82, + 79, // Opcode: FCVT_L_D + /* 11137 */ MCD_OPC_FilterValue, + 3, + 59, + 22, + 0, // Skip to: 16833 + /* 11142 */ MCD_OPC_CheckPredicate, + 39, + 54, + 22, + 0, // Skip to: 16833 + /* 11147 */ MCD_OPC_Decode, + 243, + 82, + 79, // Opcode: FCVT_LU_D + /* 11151 */ MCD_OPC_FilterValue, + 98, + 59, + 0, + 0, // Skip to: 11215 + /* 11156 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 11159 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11173 + /* 11164 */ MCD_OPC_CheckPredicate, + 36, + 32, + 22, + 0, // Skip to: 16833 + /* 11169 */ MCD_OPC_Decode, + 131, + 83, + 80, // Opcode: FCVT_W_H + /* 11173 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 11187 + /* 11178 */ MCD_OPC_CheckPredicate, + 36, + 18, + 22, + 0, // Skip to: 16833 + /* 11183 */ MCD_OPC_Decode, + 128, + 83, + 80, // Opcode: FCVT_WU_H + /* 11187 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 11201 + /* 11192 */ MCD_OPC_CheckPredicate, + 40, + 4, + 22, + 0, // Skip to: 16833 + /* 11197 */ MCD_OPC_Decode, + 247, + 82, + 80, // Opcode: FCVT_L_H + /* 11201 */ MCD_OPC_FilterValue, + 3, + 251, + 21, + 0, // Skip to: 16833 + /* 11206 */ MCD_OPC_CheckPredicate, + 40, + 246, + 21, + 0, // Skip to: 16833 + /* 11211 */ MCD_OPC_Decode, + 244, + 82, + 80, // Opcode: FCVT_LU_H + /* 11215 */ MCD_OPC_FilterValue, + 104, + 59, + 0, + 0, // Skip to: 11279 + /* 11220 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 11223 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11237 + /* 11228 */ MCD_OPC_CheckPredicate, + 8, + 224, + 21, + 0, // Skip to: 16833 + /* 11233 */ MCD_OPC_Decode, + 253, + 82, + 81, // Opcode: FCVT_S_W + /* 11237 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 11251 + /* 11242 */ MCD_OPC_CheckPredicate, + 8, + 210, + 21, + 0, // Skip to: 16833 + /* 11247 */ MCD_OPC_Decode, + 254, + 82, + 81, // Opcode: FCVT_S_WU + /* 11251 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 11265 + /* 11256 */ MCD_OPC_CheckPredicate, + 38, + 196, + 21, + 0, // Skip to: 16833 + /* 11261 */ MCD_OPC_Decode, + 251, + 82, + 81, // Opcode: FCVT_S_L + /* 11265 */ MCD_OPC_FilterValue, + 3, + 187, + 21, + 0, // Skip to: 16833 + /* 11270 */ MCD_OPC_CheckPredicate, + 38, + 182, + 21, + 0, // Skip to: 16833 + /* 11275 */ MCD_OPC_Decode, + 252, + 82, + 81, // Opcode: FCVT_S_LU + /* 11279 */ MCD_OPC_FilterValue, + 105, + 73, + 0, + 0, // Skip to: 11357 + /* 11284 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 11287 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11308 + /* 11292 */ MCD_OPC_CheckPredicate, + 9, + 160, + 21, + 0, // Skip to: 16833 + /* 11297 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 153, + 21, + 0, // Skip to: 16833 + /* 11304 */ MCD_OPC_Decode, + 235, + 82, + 82, // Opcode: FCVT_D_W + /* 11308 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 11329 + /* 11313 */ MCD_OPC_CheckPredicate, + 9, + 139, + 21, + 0, // Skip to: 16833 + /* 11318 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 132, + 21, + 0, // Skip to: 16833 + /* 11325 */ MCD_OPC_Decode, + 236, + 82, + 82, // Opcode: FCVT_D_WU + /* 11329 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 11343 + /* 11334 */ MCD_OPC_CheckPredicate, + 39, + 118, + 21, + 0, // Skip to: 16833 + /* 11339 */ MCD_OPC_Decode, + 232, + 82, + 83, // Opcode: FCVT_D_L + /* 11343 */ MCD_OPC_FilterValue, + 3, + 109, + 21, + 0, // Skip to: 16833 + /* 11348 */ MCD_OPC_CheckPredicate, + 39, + 104, + 21, + 0, // Skip to: 16833 + /* 11353 */ MCD_OPC_Decode, + 233, + 82, + 83, // Opcode: FCVT_D_LU + /* 11357 */ MCD_OPC_FilterValue, + 106, + 59, + 0, + 0, // Skip to: 11421 + /* 11362 */ MCD_OPC_ExtractField, + 20, + 5, // Inst{24-20} ... + /* 11365 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11379 + /* 11370 */ MCD_OPC_CheckPredicate, + 36, + 82, + 21, + 0, // Skip to: 16833 + /* 11375 */ MCD_OPC_Decode, + 241, + 82, + 84, // Opcode: FCVT_H_W + /* 11379 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 11393 + /* 11384 */ MCD_OPC_CheckPredicate, + 36, + 68, + 21, + 0, // Skip to: 16833 + /* 11389 */ MCD_OPC_Decode, + 242, + 82, + 84, // Opcode: FCVT_H_WU + /* 11393 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 11407 + /* 11398 */ MCD_OPC_CheckPredicate, + 40, + 54, + 21, + 0, // Skip to: 16833 + /* 11403 */ MCD_OPC_Decode, + 238, + 82, + 84, // Opcode: FCVT_H_L + /* 11407 */ MCD_OPC_FilterValue, + 3, + 45, + 21, + 0, // Skip to: 16833 + /* 11412 */ MCD_OPC_CheckPredicate, + 40, + 40, + 21, + 0, // Skip to: 16833 + /* 11417 */ MCD_OPC_Decode, + 239, + 82, + 84, // Opcode: FCVT_H_LU + /* 11421 */ MCD_OPC_FilterValue, + 112, + 45, + 0, + 0, // Skip to: 11471 + /* 11426 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 11429 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11450 + /* 11434 */ MCD_OPC_CheckPredicate, + 8, + 18, + 21, + 0, // Skip to: 16833 + /* 11439 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 11, + 21, + 0, // Skip to: 16833 + /* 11446 */ MCD_OPC_Decode, + 171, + 83, + 85, // Opcode: FMV_X_W + /* 11450 */ MCD_OPC_FilterValue, + 1, + 2, + 21, + 0, // Skip to: 16833 + /* 11455 */ MCD_OPC_CheckPredicate, + 8, + 253, + 20, + 0, // Skip to: 16833 + /* 11460 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 246, + 20, + 0, // Skip to: 16833 + /* 11467 */ MCD_OPC_Decode, + 230, + 82, + 85, // Opcode: FCLASS_S + /* 11471 */ MCD_OPC_FilterValue, + 113, + 45, + 0, + 0, // Skip to: 11521 + /* 11476 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 11479 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11500 + /* 11484 */ MCD_OPC_CheckPredicate, + 39, + 224, + 20, + 0, // Skip to: 16833 + /* 11489 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 217, + 20, + 0, // Skip to: 16833 + /* 11496 */ MCD_OPC_Decode, + 169, + 83, + 86, // Opcode: FMV_X_D + /* 11500 */ MCD_OPC_FilterValue, + 1, + 208, + 20, + 0, // Skip to: 16833 + /* 11505 */ MCD_OPC_CheckPredicate, + 9, + 203, + 20, + 0, // Skip to: 16833 + /* 11510 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 196, + 20, + 0, // Skip to: 16833 + /* 11517 */ MCD_OPC_Decode, + 228, + 82, + 86, // Opcode: FCLASS_D + /* 11521 */ MCD_OPC_FilterValue, + 114, + 45, + 0, + 0, // Skip to: 11571 + /* 11526 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 11529 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 11550 + /* 11534 */ MCD_OPC_CheckPredicate, + 7, + 174, + 20, + 0, // Skip to: 16833 + /* 11539 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 167, + 20, + 0, // Skip to: 16833 + /* 11546 */ MCD_OPC_Decode, + 170, + 83, + 87, // Opcode: FMV_X_H + /* 11550 */ MCD_OPC_FilterValue, + 1, + 158, + 20, + 0, // Skip to: 16833 + /* 11555 */ MCD_OPC_CheckPredicate, + 36, + 153, + 20, + 0, // Skip to: 16833 + /* 11560 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 146, + 20, + 0, // Skip to: 16833 + /* 11567 */ MCD_OPC_Decode, + 229, + 82, + 87, // Opcode: FCLASS_H + /* 11571 */ MCD_OPC_FilterValue, + 120, + 23, + 0, + 0, // Skip to: 11599 + /* 11576 */ MCD_OPC_CheckPredicate, + 8, + 132, + 20, + 0, // Skip to: 16833 + /* 11581 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 125, + 20, + 0, // Skip to: 16833 + /* 11588 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 118, + 20, + 0, // Skip to: 16833 + /* 11595 */ MCD_OPC_Decode, + 168, + 83, + 88, // Opcode: FMV_W_X + /* 11599 */ MCD_OPC_FilterValue, + 121, + 23, + 0, + 0, // Skip to: 11627 + /* 11604 */ MCD_OPC_CheckPredicate, + 39, + 104, + 20, + 0, // Skip to: 16833 + /* 11609 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 97, + 20, + 0, // Skip to: 16833 + /* 11616 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 90, + 20, + 0, // Skip to: 16833 + /* 11623 */ MCD_OPC_Decode, + 166, + 83, + 82, // Opcode: FMV_D_X + /* 11627 */ MCD_OPC_FilterValue, + 122, + 81, + 20, + 0, // Skip to: 16833 + /* 11632 */ MCD_OPC_CheckPredicate, + 7, + 76, + 20, + 0, // Skip to: 16833 + /* 11637 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 69, + 20, + 0, // Skip to: 16833 + /* 11644 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 62, + 20, + 0, // Skip to: 16833 + /* 11651 */ MCD_OPC_Decode, + 167, + 83, + 89, // Opcode: FMV_H_X + /* 11655 */ MCD_OPC_FilterValue, + 87, + 228, + 18, + 0, // Skip to: 16496 + /* 11660 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 11663 */ MCD_OPC_FilterValue, + 0, + 110, + 2, + 0, // Skip to: 12290 + /* 11668 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 11671 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11685 + /* 11676 */ MCD_OPC_CheckPredicate, + 5, + 32, + 20, + 0, // Skip to: 16833 + /* 11681 */ MCD_OPC_Decode, + 196, + 84, + 90, // Opcode: VADD_VV + /* 11685 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 11699 + /* 11690 */ MCD_OPC_CheckPredicate, + 5, + 18, + 20, + 0, // Skip to: 16833 + /* 11695 */ MCD_OPC_Decode, + 176, + 89, + 90, // Opcode: VSUB_VV + /* 11699 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 11713 + /* 11704 */ MCD_OPC_CheckPredicate, + 5, + 4, + 20, + 0, // Skip to: 16833 + /* 11709 */ MCD_OPC_Decode, + 199, + 87, + 90, // Opcode: VMINU_VV + /* 11713 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 11727 + /* 11718 */ MCD_OPC_CheckPredicate, + 5, + 246, + 19, + 0, // Skip to: 16833 + /* 11723 */ MCD_OPC_Decode, + 201, + 87, + 90, // Opcode: VMIN_VV + /* 11727 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 11741 + /* 11732 */ MCD_OPC_CheckPredicate, + 5, + 232, + 19, + 0, // Skip to: 16833 + /* 11737 */ MCD_OPC_Decode, + 182, + 87, + 90, // Opcode: VMAXU_VV + /* 11741 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 11755 + /* 11746 */ MCD_OPC_CheckPredicate, + 5, + 218, + 19, + 0, // Skip to: 16833 + /* 11751 */ MCD_OPC_Decode, + 184, + 87, + 90, // Opcode: VMAX_VV + /* 11755 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 11769 + /* 11760 */ MCD_OPC_CheckPredicate, + 5, + 204, + 19, + 0, // Skip to: 16833 + /* 11765 */ MCD_OPC_Decode, + 143, + 85, + 90, // Opcode: VAND_VV + /* 11769 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 11783 + /* 11774 */ MCD_OPC_CheckPredicate, + 5, + 190, + 19, + 0, // Skip to: 16833 + /* 11779 */ MCD_OPC_Decode, + 142, + 88, + 90, // Opcode: VOR_VV + /* 11783 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 11797 + /* 11788 */ MCD_OPC_CheckPredicate, + 5, + 176, + 19, + 0, // Skip to: 16833 + /* 11793 */ MCD_OPC_Decode, + 242, + 89, + 90, // Opcode: VXOR_VV + /* 11797 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 11811 + /* 11802 */ MCD_OPC_CheckPredicate, + 5, + 162, + 19, + 0, // Skip to: 16833 + /* 11807 */ MCD_OPC_Decode, + 158, + 88, + 90, // Opcode: VRGATHER_VV + /* 11811 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 11825 + /* 11816 */ MCD_OPC_CheckPredicate, + 5, + 148, + 19, + 0, // Skip to: 16833 + /* 11821 */ MCD_OPC_Decode, + 156, + 88, + 90, // Opcode: VRGATHEREI16_VV + /* 11825 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 11846 + /* 11830 */ MCD_OPC_CheckPredicate, + 5, + 134, + 19, + 0, // Skip to: 16833 + /* 11835 */ MCD_OPC_CheckField, + 25, + 1, + 0, + 127, + 19, + 0, // Skip to: 16833 + /* 11842 */ MCD_OPC_Decode, + 193, + 84, + 91, // Opcode: VADC_VVM + /* 11846 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 11882 + /* 11851 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 11854 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11868 + /* 11859 */ MCD_OPC_CheckPredicate, + 5, + 105, + 19, + 0, // Skip to: 16833 + /* 11864 */ MCD_OPC_Decode, + 175, + 87, + 91, // Opcode: VMADC_VVM + /* 11868 */ MCD_OPC_FilterValue, + 1, + 96, + 19, + 0, // Skip to: 16833 + /* 11873 */ MCD_OPC_CheckPredicate, + 5, + 91, + 19, + 0, // Skip to: 16833 + /* 11878 */ MCD_OPC_Decode, + 174, + 87, + 91, // Opcode: VMADC_VV + /* 11882 */ MCD_OPC_FilterValue, + 18, + 16, + 0, + 0, // Skip to: 11903 + /* 11887 */ MCD_OPC_CheckPredicate, + 5, + 77, + 19, + 0, // Skip to: 16833 + /* 11892 */ MCD_OPC_CheckField, + 25, + 1, + 0, + 70, + 19, + 0, // Skip to: 16833 + /* 11899 */ MCD_OPC_Decode, + 172, + 88, + 91, // Opcode: VSBC_VVM + /* 11903 */ MCD_OPC_FilterValue, + 19, + 31, + 0, + 0, // Skip to: 11939 + /* 11908 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 11911 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11925 + /* 11916 */ MCD_OPC_CheckPredicate, + 5, + 48, + 19, + 0, // Skip to: 16833 + /* 11921 */ MCD_OPC_Decode, + 208, + 87, + 91, // Opcode: VMSBC_VVM + /* 11925 */ MCD_OPC_FilterValue, + 1, + 39, + 19, + 0, // Skip to: 16833 + /* 11930 */ MCD_OPC_CheckPredicate, + 5, + 34, + 19, + 0, // Skip to: 16833 + /* 11935 */ MCD_OPC_Decode, + 207, + 87, + 91, // Opcode: VMSBC_VV + /* 11939 */ MCD_OPC_FilterValue, + 23, + 38, + 0, + 0, // Skip to: 11982 + /* 11944 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 11947 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 11961 + /* 11952 */ MCD_OPC_CheckPredicate, + 5, + 12, + 19, + 0, // Skip to: 16833 + /* 11957 */ MCD_OPC_Decode, + 187, + 87, + 91, // Opcode: VMERGE_VVM + /* 11961 */ MCD_OPC_FilterValue, + 1, + 3, + 19, + 0, // Skip to: 16833 + /* 11966 */ MCD_OPC_CheckPredicate, + 5, + 254, + 18, + 0, // Skip to: 16833 + /* 11971 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 247, + 18, + 0, // Skip to: 16833 + /* 11978 */ MCD_OPC_Decode, + 248, + 87, + 92, // Opcode: VMV_V_V + /* 11982 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 11996 + /* 11987 */ MCD_OPC_CheckPredicate, + 5, + 233, + 18, + 0, // Skip to: 16833 + /* 11992 */ MCD_OPC_Decode, + 213, + 87, + 90, // Opcode: VMSEQ_VV + /* 11996 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 12010 + /* 12001 */ MCD_OPC_CheckPredicate, + 5, + 219, + 18, + 0, // Skip to: 16833 + /* 12006 */ MCD_OPC_Decode, + 231, + 87, + 90, // Opcode: VMSNE_VV + /* 12010 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 12024 + /* 12015 */ MCD_OPC_CheckPredicate, + 5, + 205, + 18, + 0, // Skip to: 16833 + /* 12020 */ MCD_OPC_Decode, + 226, + 87, + 90, // Opcode: VMSLTU_VV + /* 12024 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 12038 + /* 12029 */ MCD_OPC_CheckPredicate, + 5, + 191, + 18, + 0, // Skip to: 16833 + /* 12034 */ MCD_OPC_Decode, + 228, + 87, + 90, // Opcode: VMSLT_VV + /* 12038 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 12052 + /* 12043 */ MCD_OPC_CheckPredicate, + 5, + 177, + 18, + 0, // Skip to: 16833 + /* 12048 */ MCD_OPC_Decode, + 221, + 87, + 90, // Opcode: VMSLEU_VV + /* 12052 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 12066 + /* 12057 */ MCD_OPC_CheckPredicate, + 5, + 163, + 18, + 0, // Skip to: 16833 + /* 12062 */ MCD_OPC_Decode, + 224, + 87, + 90, // Opcode: VMSLE_VV + /* 12066 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 12080 + /* 12071 */ MCD_OPC_CheckPredicate, + 5, + 149, + 18, + 0, // Skip to: 16833 + /* 12076 */ MCD_OPC_Decode, + 167, + 88, + 90, // Opcode: VSADDU_VV + /* 12080 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 12094 + /* 12085 */ MCD_OPC_CheckPredicate, + 5, + 135, + 18, + 0, // Skip to: 16833 + /* 12090 */ MCD_OPC_Decode, + 170, + 88, + 90, // Opcode: VSADD_VV + /* 12094 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 12108 + /* 12099 */ MCD_OPC_CheckPredicate, + 5, + 121, + 18, + 0, // Skip to: 16833 + /* 12104 */ MCD_OPC_Decode, + 172, + 89, + 90, // Opcode: VSSUBU_VV + /* 12108 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 12122 + /* 12113 */ MCD_OPC_CheckPredicate, + 5, + 107, + 18, + 0, // Skip to: 16833 + /* 12118 */ MCD_OPC_Decode, + 174, + 89, + 90, // Opcode: VSSUB_VV + /* 12122 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 12136 + /* 12127 */ MCD_OPC_CheckPredicate, + 5, + 93, + 18, + 0, // Skip to: 16833 + /* 12132 */ MCD_OPC_Decode, + 191, + 88, + 90, // Opcode: VSLL_VV + /* 12136 */ MCD_OPC_FilterValue, + 39, + 9, + 0, + 0, // Skip to: 12150 + /* 12141 */ MCD_OPC_CheckPredicate, + 5, + 79, + 18, + 0, // Skip to: 16833 + /* 12146 */ MCD_OPC_Decode, + 193, + 88, + 90, // Opcode: VSMUL_VV + /* 12150 */ MCD_OPC_FilterValue, + 40, + 9, + 0, + 0, // Skip to: 12164 + /* 12155 */ MCD_OPC_CheckPredicate, + 5, + 65, + 18, + 0, // Skip to: 16833 + /* 12160 */ MCD_OPC_Decode, + 232, + 88, + 90, // Opcode: VSRL_VV + /* 12164 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 12178 + /* 12169 */ MCD_OPC_CheckPredicate, + 5, + 51, + 18, + 0, // Skip to: 16833 + /* 12174 */ MCD_OPC_Decode, + 229, + 88, + 90, // Opcode: VSRA_VV + /* 12178 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 12192 + /* 12183 */ MCD_OPC_CheckPredicate, + 5, + 37, + 18, + 0, // Skip to: 16833 + /* 12188 */ MCD_OPC_Decode, + 142, + 89, + 90, // Opcode: VSSRL_VV + /* 12192 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 12206 + /* 12197 */ MCD_OPC_CheckPredicate, + 5, + 23, + 18, + 0, // Skip to: 16833 + /* 12202 */ MCD_OPC_Decode, + 139, + 89, + 90, // Opcode: VSSRA_VV + /* 12206 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 12220 + /* 12211 */ MCD_OPC_CheckPredicate, + 5, + 9, + 18, + 0, // Skip to: 16833 + /* 12216 */ MCD_OPC_Decode, + 139, + 88, + 90, // Opcode: VNSRL_WV + /* 12220 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 12234 + /* 12225 */ MCD_OPC_CheckPredicate, + 5, + 251, + 17, + 0, // Skip to: 16833 + /* 12230 */ MCD_OPC_Decode, + 136, + 88, + 90, // Opcode: VNSRA_WV + /* 12234 */ MCD_OPC_FilterValue, + 46, + 9, + 0, + 0, // Skip to: 12248 + /* 12239 */ MCD_OPC_CheckPredicate, + 5, + 237, + 17, + 0, // Skip to: 16833 + /* 12244 */ MCD_OPC_Decode, + 254, + 87, + 90, // Opcode: VNCLIPU_WV + /* 12248 */ MCD_OPC_FilterValue, + 47, + 9, + 0, + 0, // Skip to: 12262 + /* 12253 */ MCD_OPC_CheckPredicate, + 5, + 223, + 17, + 0, // Skip to: 16833 + /* 12258 */ MCD_OPC_Decode, + 129, + 88, + 90, // Opcode: VNCLIP_WV + /* 12262 */ MCD_OPC_FilterValue, + 48, + 9, + 0, + 0, // Skip to: 12276 + /* 12267 */ MCD_OPC_CheckPredicate, + 5, + 209, + 17, + 0, // Skip to: 16833 + /* 12272 */ MCD_OPC_Decode, + 231, + 89, + 90, // Opcode: VWREDSUMU_VS + /* 12276 */ MCD_OPC_FilterValue, + 49, + 200, + 17, + 0, // Skip to: 16833 + /* 12281 */ MCD_OPC_CheckPredicate, + 5, + 195, + 17, + 0, // Skip to: 16833 + /* 12286 */ MCD_OPC_Decode, + 232, + 89, + 90, // Opcode: VWREDSUM_VS + /* 12290 */ MCD_OPC_FilterValue, + 1, + 133, + 3, + 0, // Skip to: 13196 + /* 12295 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 12298 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 12312 + /* 12303 */ MCD_OPC_CheckPredicate, + 41, + 173, + 17, + 0, // Skip to: 16833 + /* 12308 */ MCD_OPC_Decode, + 156, + 85, + 90, // Opcode: VFADD_VV + /* 12312 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 12326 + /* 12317 */ MCD_OPC_CheckPredicate, + 41, + 159, + 17, + 0, // Skip to: 16833 + /* 12322 */ MCD_OPC_Decode, + 206, + 85, + 90, // Opcode: VFREDUSUM_VS + /* 12326 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 12340 + /* 12331 */ MCD_OPC_CheckPredicate, + 41, + 145, + 17, + 0, // Skip to: 16833 + /* 12336 */ MCD_OPC_Decode, + 219, + 85, + 90, // Opcode: VFSUB_VV + /* 12340 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 12354 + /* 12345 */ MCD_OPC_CheckPredicate, + 41, + 131, + 17, + 0, // Skip to: 16833 + /* 12350 */ MCD_OPC_Decode, + 205, + 85, + 90, // Opcode: VFREDOSUM_VS + /* 12354 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 12368 + /* 12359 */ MCD_OPC_CheckPredicate, + 41, + 117, + 17, + 0, // Skip to: 16833 + /* 12364 */ MCD_OPC_Decode, + 175, + 85, + 90, // Opcode: VFMIN_VV + /* 12368 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 12382 + /* 12373 */ MCD_OPC_CheckPredicate, + 41, + 103, + 17, + 0, // Skip to: 16833 + /* 12378 */ MCD_OPC_Decode, + 204, + 85, + 90, // Opcode: VFREDMIN_VS + /* 12382 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 12396 + /* 12387 */ MCD_OPC_CheckPredicate, + 41, + 89, + 17, + 0, // Skip to: 16833 + /* 12392 */ MCD_OPC_Decode, + 172, + 85, + 90, // Opcode: VFMAX_VV + /* 12396 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 12410 + /* 12401 */ MCD_OPC_CheckPredicate, + 41, + 75, + 17, + 0, // Skip to: 16833 + /* 12406 */ MCD_OPC_Decode, + 203, + 85, + 90, // Opcode: VFREDMAX_VS + /* 12410 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 12424 + /* 12415 */ MCD_OPC_CheckPredicate, + 41, + 61, + 17, + 0, // Skip to: 16833 + /* 12420 */ MCD_OPC_Decode, + 214, + 85, + 90, // Opcode: VFSGNJ_VV + /* 12424 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 12438 + /* 12429 */ MCD_OPC_CheckPredicate, + 41, + 47, + 17, + 0, // Skip to: 16833 + /* 12434 */ MCD_OPC_Decode, + 210, + 85, + 90, // Opcode: VFSGNJN_VV + /* 12438 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 12452 + /* 12443 */ MCD_OPC_CheckPredicate, + 41, + 33, + 17, + 0, // Skip to: 16833 + /* 12448 */ MCD_OPC_Decode, + 212, + 85, + 90, // Opcode: VFSGNJX_VV + /* 12452 */ MCD_OPC_FilterValue, + 16, + 23, + 0, + 0, // Skip to: 12480 + /* 12457 */ MCD_OPC_CheckPredicate, + 41, + 19, + 17, + 0, // Skip to: 16833 + /* 12462 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 12, + 17, + 0, // Skip to: 16833 + /* 12469 */ MCD_OPC_CheckField, + 15, + 5, + 0, + 5, + 17, + 0, // Skip to: 16833 + /* 12476 */ MCD_OPC_Decode, + 182, + 85, + 93, // Opcode: VFMV_F_S + /* 12480 */ MCD_OPC_FilterValue, + 18, + 41, + 1, + 0, // Skip to: 12782 + /* 12485 */ MCD_OPC_ExtractField, + 15, + 5, // Inst{19-15} ... + /* 12488 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 12502 + /* 12493 */ MCD_OPC_CheckPredicate, + 41, + 239, + 16, + 0, // Skip to: 16833 + /* 12498 */ MCD_OPC_Decode, + 162, + 85, + 94, // Opcode: VFCVT_XU_F_V + /* 12502 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 12516 + /* 12507 */ MCD_OPC_CheckPredicate, + 41, + 225, + 16, + 0, // Skip to: 16833 + /* 12512 */ MCD_OPC_Decode, + 163, + 85, + 94, // Opcode: VFCVT_X_F_V + /* 12516 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 12530 + /* 12521 */ MCD_OPC_CheckPredicate, + 41, + 211, + 16, + 0, // Skip to: 16833 + /* 12526 */ MCD_OPC_Decode, + 158, + 85, + 94, // Opcode: VFCVT_F_XU_V + /* 12530 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 12544 + /* 12535 */ MCD_OPC_CheckPredicate, + 41, + 197, + 16, + 0, // Skip to: 16833 + /* 12540 */ MCD_OPC_Decode, + 159, + 85, + 94, // Opcode: VFCVT_F_X_V + /* 12544 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 12558 + /* 12549 */ MCD_OPC_CheckPredicate, + 41, + 183, + 16, + 0, // Skip to: 16833 + /* 12554 */ MCD_OPC_Decode, + 160, + 85, + 94, // Opcode: VFCVT_RTZ_XU_F_V + /* 12558 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 12572 + /* 12563 */ MCD_OPC_CheckPredicate, + 41, + 169, + 16, + 0, // Skip to: 16833 + /* 12568 */ MCD_OPC_Decode, + 161, + 85, + 94, // Opcode: VFCVT_RTZ_X_F_V + /* 12572 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 12586 + /* 12577 */ MCD_OPC_CheckPredicate, + 41, + 155, + 16, + 0, // Skip to: 16833 + /* 12582 */ MCD_OPC_Decode, + 229, + 85, + 94, // Opcode: VFWCVT_XU_F_V + /* 12586 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 12600 + /* 12591 */ MCD_OPC_CheckPredicate, + 41, + 141, + 16, + 0, // Skip to: 16833 + /* 12596 */ MCD_OPC_Decode, + 230, + 85, + 94, // Opcode: VFWCVT_X_F_V + /* 12600 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 12614 + /* 12605 */ MCD_OPC_CheckPredicate, + 41, + 127, + 16, + 0, // Skip to: 16833 + /* 12610 */ MCD_OPC_Decode, + 225, + 85, + 94, // Opcode: VFWCVT_F_XU_V + /* 12614 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 12628 + /* 12619 */ MCD_OPC_CheckPredicate, + 41, + 113, + 16, + 0, // Skip to: 16833 + /* 12624 */ MCD_OPC_Decode, + 226, + 85, + 94, // Opcode: VFWCVT_F_X_V + /* 12628 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 12642 + /* 12633 */ MCD_OPC_CheckPredicate, + 41, + 99, + 16, + 0, // Skip to: 16833 + /* 12638 */ MCD_OPC_Decode, + 224, + 85, + 94, // Opcode: VFWCVT_F_F_V + /* 12642 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 12656 + /* 12647 */ MCD_OPC_CheckPredicate, + 41, + 85, + 16, + 0, // Skip to: 16833 + /* 12652 */ MCD_OPC_Decode, + 227, + 85, + 94, // Opcode: VFWCVT_RTZ_XU_F_V + /* 12656 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 12670 + /* 12661 */ MCD_OPC_CheckPredicate, + 41, + 71, + 16, + 0, // Skip to: 16833 + /* 12666 */ MCD_OPC_Decode, + 228, + 85, + 94, // Opcode: VFWCVT_RTZ_X_F_V + /* 12670 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 12684 + /* 12675 */ MCD_OPC_CheckPredicate, + 41, + 57, + 16, + 0, // Skip to: 16833 + /* 12680 */ MCD_OPC_Decode, + 191, + 85, + 94, // Opcode: VFNCVT_XU_F_W + /* 12684 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 12698 + /* 12689 */ MCD_OPC_CheckPredicate, + 41, + 43, + 16, + 0, // Skip to: 16833 + /* 12694 */ MCD_OPC_Decode, + 192, + 85, + 94, // Opcode: VFNCVT_X_F_W + /* 12698 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 12712 + /* 12703 */ MCD_OPC_CheckPredicate, + 41, + 29, + 16, + 0, // Skip to: 16833 + /* 12708 */ MCD_OPC_Decode, + 186, + 85, + 94, // Opcode: VFNCVT_F_XU_W + /* 12712 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 12726 + /* 12717 */ MCD_OPC_CheckPredicate, + 41, + 15, + 16, + 0, // Skip to: 16833 + /* 12722 */ MCD_OPC_Decode, + 187, + 85, + 94, // Opcode: VFNCVT_F_X_W + /* 12726 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 12740 + /* 12731 */ MCD_OPC_CheckPredicate, + 41, + 1, + 16, + 0, // Skip to: 16833 + /* 12736 */ MCD_OPC_Decode, + 185, + 85, + 94, // Opcode: VFNCVT_F_F_W + /* 12740 */ MCD_OPC_FilterValue, + 21, + 9, + 0, + 0, // Skip to: 12754 + /* 12745 */ MCD_OPC_CheckPredicate, + 41, + 243, + 15, + 0, // Skip to: 16833 + /* 12750 */ MCD_OPC_Decode, + 188, + 85, + 94, // Opcode: VFNCVT_ROD_F_F_W + /* 12754 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 12768 + /* 12759 */ MCD_OPC_CheckPredicate, + 41, + 229, + 15, + 0, // Skip to: 16833 + /* 12764 */ MCD_OPC_Decode, + 189, + 85, + 94, // Opcode: VFNCVT_RTZ_XU_F_W + /* 12768 */ MCD_OPC_FilterValue, + 23, + 220, + 15, + 0, // Skip to: 16833 + /* 12773 */ MCD_OPC_CheckPredicate, + 41, + 215, + 15, + 0, // Skip to: 16833 + /* 12778 */ MCD_OPC_Decode, + 190, + 85, + 94, // Opcode: VFNCVT_RTZ_X_F_W + /* 12782 */ MCD_OPC_FilterValue, + 19, + 59, + 0, + 0, // Skip to: 12846 + /* 12787 */ MCD_OPC_ExtractField, + 15, + 5, // Inst{19-15} ... + /* 12790 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 12804 + /* 12795 */ MCD_OPC_CheckPredicate, + 41, + 193, + 15, + 0, // Skip to: 16833 + /* 12800 */ MCD_OPC_Decode, + 217, + 85, + 94, // Opcode: VFSQRT_V + /* 12804 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 12818 + /* 12809 */ MCD_OPC_CheckPredicate, + 41, + 179, + 15, + 0, // Skip to: 16833 + /* 12814 */ MCD_OPC_Decode, + 207, + 85, + 94, // Opcode: VFRSQRT7_V + /* 12818 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 12832 + /* 12823 */ MCD_OPC_CheckPredicate, + 41, + 165, + 15, + 0, // Skip to: 16833 + /* 12828 */ MCD_OPC_Decode, + 202, + 85, + 94, // Opcode: VFREC7_V + /* 12832 */ MCD_OPC_FilterValue, + 16, + 156, + 15, + 0, // Skip to: 16833 + /* 12837 */ MCD_OPC_CheckPredicate, + 41, + 151, + 15, + 0, // Skip to: 16833 + /* 12842 */ MCD_OPC_Decode, + 157, + 85, + 94, // Opcode: VFCLASS_V + /* 12846 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 12860 + /* 12851 */ MCD_OPC_CheckPredicate, + 41, + 137, + 15, + 0, // Skip to: 16833 + /* 12856 */ MCD_OPC_Decode, + 190, + 87, + 90, // Opcode: VMFEQ_VV + /* 12860 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 12874 + /* 12865 */ MCD_OPC_CheckPredicate, + 41, + 123, + 15, + 0, // Skip to: 16833 + /* 12870 */ MCD_OPC_Decode, + 194, + 87, + 90, // Opcode: VMFLE_VV + /* 12874 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 12888 + /* 12879 */ MCD_OPC_CheckPredicate, + 41, + 109, + 15, + 0, // Skip to: 16833 + /* 12884 */ MCD_OPC_Decode, + 196, + 87, + 90, // Opcode: VMFLT_VV + /* 12888 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 12902 + /* 12893 */ MCD_OPC_CheckPredicate, + 41, + 95, + 15, + 0, // Skip to: 16833 + /* 12898 */ MCD_OPC_Decode, + 198, + 87, + 90, // Opcode: VMFNE_VV + /* 12902 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 12916 + /* 12907 */ MCD_OPC_CheckPredicate, + 41, + 81, + 15, + 0, // Skip to: 16833 + /* 12912 */ MCD_OPC_Decode, + 165, + 85, + 90, // Opcode: VFDIV_VV + /* 12916 */ MCD_OPC_FilterValue, + 36, + 9, + 0, + 0, // Skip to: 12930 + /* 12921 */ MCD_OPC_CheckPredicate, + 41, + 67, + 15, + 0, // Skip to: 16833 + /* 12926 */ MCD_OPC_Decode, + 181, + 85, + 90, // Opcode: VFMUL_VV + /* 12930 */ MCD_OPC_FilterValue, + 40, + 9, + 0, + 0, // Skip to: 12944 + /* 12935 */ MCD_OPC_CheckPredicate, + 41, + 53, + 15, + 0, // Skip to: 16833 + /* 12940 */ MCD_OPC_Decode, + 170, + 85, + 95, // Opcode: VFMADD_VV + /* 12944 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 12958 + /* 12949 */ MCD_OPC_CheckPredicate, + 41, + 39, + 15, + 0, // Skip to: 16833 + /* 12954 */ MCD_OPC_Decode, + 196, + 85, + 95, // Opcode: VFNMADD_VV + /* 12958 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 12972 + /* 12963 */ MCD_OPC_CheckPredicate, + 41, + 25, + 15, + 0, // Skip to: 16833 + /* 12968 */ MCD_OPC_Decode, + 179, + 85, + 95, // Opcode: VFMSUB_VV + /* 12972 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 12986 + /* 12977 */ MCD_OPC_CheckPredicate, + 41, + 11, + 15, + 0, // Skip to: 16833 + /* 12982 */ MCD_OPC_Decode, + 200, + 85, + 95, // Opcode: VFNMSUB_VV + /* 12986 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 13000 + /* 12991 */ MCD_OPC_CheckPredicate, + 41, + 253, + 14, + 0, // Skip to: 16833 + /* 12996 */ MCD_OPC_Decode, + 168, + 85, + 95, // Opcode: VFMACC_VV + /* 13000 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 13014 + /* 13005 */ MCD_OPC_CheckPredicate, + 41, + 239, + 14, + 0, // Skip to: 16833 + /* 13010 */ MCD_OPC_Decode, + 194, + 85, + 95, // Opcode: VFNMACC_VV + /* 13014 */ MCD_OPC_FilterValue, + 46, + 9, + 0, + 0, // Skip to: 13028 + /* 13019 */ MCD_OPC_CheckPredicate, + 41, + 225, + 14, + 0, // Skip to: 16833 + /* 13024 */ MCD_OPC_Decode, + 177, + 85, + 95, // Opcode: VFMSAC_VV + /* 13028 */ MCD_OPC_FilterValue, + 47, + 9, + 0, + 0, // Skip to: 13042 + /* 13033 */ MCD_OPC_CheckPredicate, + 41, + 211, + 14, + 0, // Skip to: 16833 + /* 13038 */ MCD_OPC_Decode, + 198, + 85, + 95, // Opcode: VFNMSAC_VV + /* 13042 */ MCD_OPC_FilterValue, + 48, + 9, + 0, + 0, // Skip to: 13056 + /* 13047 */ MCD_OPC_CheckPredicate, + 41, + 197, + 14, + 0, // Skip to: 16833 + /* 13052 */ MCD_OPC_Decode, + 221, + 85, + 90, // Opcode: VFWADD_VV + /* 13056 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 13070 + /* 13061 */ MCD_OPC_CheckPredicate, + 41, + 183, + 14, + 0, // Skip to: 16833 + /* 13066 */ MCD_OPC_Decode, + 242, + 85, + 90, // Opcode: VFWREDUSUM_VS + /* 13070 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 13084 + /* 13075 */ MCD_OPC_CheckPredicate, + 41, + 169, + 14, + 0, // Skip to: 16833 + /* 13080 */ MCD_OPC_Decode, + 244, + 85, + 90, // Opcode: VFWSUB_VV + /* 13084 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 13098 + /* 13089 */ MCD_OPC_CheckPredicate, + 41, + 155, + 14, + 0, // Skip to: 16833 + /* 13094 */ MCD_OPC_Decode, + 241, + 85, + 90, // Opcode: VFWREDOSUM_VS + /* 13098 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 13112 + /* 13103 */ MCD_OPC_CheckPredicate, + 41, + 141, + 14, + 0, // Skip to: 16833 + /* 13108 */ MCD_OPC_Decode, + 223, + 85, + 90, // Opcode: VFWADD_WV + /* 13112 */ MCD_OPC_FilterValue, + 54, + 9, + 0, + 0, // Skip to: 13126 + /* 13117 */ MCD_OPC_CheckPredicate, + 41, + 127, + 14, + 0, // Skip to: 16833 + /* 13122 */ MCD_OPC_Decode, + 246, + 85, + 90, // Opcode: VFWSUB_WV + /* 13126 */ MCD_OPC_FilterValue, + 56, + 9, + 0, + 0, // Skip to: 13140 + /* 13131 */ MCD_OPC_CheckPredicate, + 41, + 113, + 14, + 0, // Skip to: 16833 + /* 13136 */ MCD_OPC_Decode, + 236, + 85, + 90, // Opcode: VFWMUL_VV + /* 13140 */ MCD_OPC_FilterValue, + 60, + 9, + 0, + 0, // Skip to: 13154 + /* 13145 */ MCD_OPC_CheckPredicate, + 41, + 99, + 14, + 0, // Skip to: 16833 + /* 13150 */ MCD_OPC_Decode, + 232, + 85, + 95, // Opcode: VFWMACC_VV + /* 13154 */ MCD_OPC_FilterValue, + 61, + 9, + 0, + 0, // Skip to: 13168 + /* 13159 */ MCD_OPC_CheckPredicate, + 41, + 85, + 14, + 0, // Skip to: 16833 + /* 13164 */ MCD_OPC_Decode, + 238, + 85, + 95, // Opcode: VFWNMACC_VV + /* 13168 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 13182 + /* 13173 */ MCD_OPC_CheckPredicate, + 41, + 71, + 14, + 0, // Skip to: 16833 + /* 13178 */ MCD_OPC_Decode, + 234, + 85, + 95, // Opcode: VFWMSAC_VV + /* 13182 */ MCD_OPC_FilterValue, + 63, + 62, + 14, + 0, // Skip to: 16833 + /* 13187 */ MCD_OPC_CheckPredicate, + 41, + 57, + 14, + 0, // Skip to: 16833 + /* 13192 */ MCD_OPC_Decode, + 240, + 85, + 95, // Opcode: VFWNMSAC_VV + /* 13196 */ MCD_OPC_FilterValue, + 2, + 190, + 3, + 0, // Skip to: 14159 + /* 13201 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 13204 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 13218 + /* 13209 */ MCD_OPC_CheckPredicate, + 5, + 35, + 14, + 0, // Skip to: 16833 + /* 13214 */ MCD_OPC_Decode, + 150, + 88, + 90, // Opcode: VREDSUM_VS + /* 13218 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 13232 + /* 13223 */ MCD_OPC_CheckPredicate, + 5, + 21, + 14, + 0, // Skip to: 16833 + /* 13228 */ MCD_OPC_Decode, + 144, + 88, + 90, // Opcode: VREDAND_VS + /* 13232 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 13246 + /* 13237 */ MCD_OPC_CheckPredicate, + 5, + 7, + 14, + 0, // Skip to: 16833 + /* 13242 */ MCD_OPC_Decode, + 149, + 88, + 90, // Opcode: VREDOR_VS + /* 13246 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 13260 + /* 13251 */ MCD_OPC_CheckPredicate, + 5, + 249, + 13, + 0, // Skip to: 16833 + /* 13256 */ MCD_OPC_Decode, + 151, + 88, + 90, // Opcode: VREDXOR_VS + /* 13260 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 13274 + /* 13265 */ MCD_OPC_CheckPredicate, + 5, + 235, + 13, + 0, // Skip to: 16833 + /* 13270 */ MCD_OPC_Decode, + 147, + 88, + 90, // Opcode: VREDMINU_VS + /* 13274 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 13288 + /* 13279 */ MCD_OPC_CheckPredicate, + 5, + 221, + 13, + 0, // Skip to: 16833 + /* 13284 */ MCD_OPC_Decode, + 148, + 88, + 90, // Opcode: VREDMIN_VS + /* 13288 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 13302 + /* 13293 */ MCD_OPC_CheckPredicate, + 5, + 207, + 13, + 0, // Skip to: 16833 + /* 13298 */ MCD_OPC_Decode, + 145, + 88, + 90, // Opcode: VREDMAXU_VS + /* 13302 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 13316 + /* 13307 */ MCD_OPC_CheckPredicate, + 5, + 193, + 13, + 0, // Skip to: 16833 + /* 13312 */ MCD_OPC_Decode, + 146, + 88, + 90, // Opcode: VREDMAX_VS + /* 13316 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 13330 + /* 13321 */ MCD_OPC_CheckPredicate, + 5, + 179, + 13, + 0, // Skip to: 16833 + /* 13326 */ MCD_OPC_Decode, + 188, + 84, + 90, // Opcode: VAADDU_VV + /* 13330 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 13344 + /* 13335 */ MCD_OPC_CheckPredicate, + 5, + 165, + 13, + 0, // Skip to: 16833 + /* 13340 */ MCD_OPC_Decode, + 190, + 84, + 90, // Opcode: VAADD_VV + /* 13344 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 13358 + /* 13349 */ MCD_OPC_CheckPredicate, + 5, + 151, + 13, + 0, // Skip to: 16833 + /* 13354 */ MCD_OPC_Decode, + 145, + 85, + 90, // Opcode: VASUBU_VV + /* 13358 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 13372 + /* 13363 */ MCD_OPC_CheckPredicate, + 5, + 137, + 13, + 0, // Skip to: 16833 + /* 13368 */ MCD_OPC_Decode, + 147, + 85, + 90, // Opcode: VASUB_VV + /* 13372 */ MCD_OPC_FilterValue, + 16, + 52, + 0, + 0, // Skip to: 13429 + /* 13377 */ MCD_OPC_ExtractField, + 15, + 5, // Inst{19-15} ... + /* 13380 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 13401 + /* 13385 */ MCD_OPC_CheckPredicate, + 5, + 115, + 13, + 0, // Skip to: 16833 + /* 13390 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 108, + 13, + 0, // Skip to: 16833 + /* 13397 */ MCD_OPC_Decode, + 250, + 87, + 96, // Opcode: VMV_X_S + /* 13401 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 13415 + /* 13406 */ MCD_OPC_CheckPredicate, + 5, + 94, + 13, + 0, // Skip to: 16833 + /* 13411 */ MCD_OPC_Decode, + 150, + 85, + 97, // Opcode: VCPOP_M + /* 13415 */ MCD_OPC_FilterValue, + 17, + 85, + 13, + 0, // Skip to: 16833 + /* 13420 */ MCD_OPC_CheckPredicate, + 5, + 80, + 13, + 0, // Skip to: 16833 + /* 13425 */ MCD_OPC_Decode, + 166, + 85, + 97, // Opcode: VFIRST_M + /* 13429 */ MCD_OPC_FilterValue, + 18, + 87, + 0, + 0, // Skip to: 13521 + /* 13434 */ MCD_OPC_ExtractField, + 15, + 5, // Inst{19-15} ... + /* 13437 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 13451 + /* 13442 */ MCD_OPC_CheckPredicate, + 5, + 58, + 13, + 0, // Skip to: 16833 + /* 13447 */ MCD_OPC_Decode, + 246, + 89, + 94, // Opcode: VZEXT_VF8 + /* 13451 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 13465 + /* 13456 */ MCD_OPC_CheckPredicate, + 5, + 44, + 13, + 0, // Skip to: 16833 + /* 13461 */ MCD_OPC_Decode, + 183, + 88, + 94, // Opcode: VSEXT_VF8 + /* 13465 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 13479 + /* 13470 */ MCD_OPC_CheckPredicate, + 5, + 30, + 13, + 0, // Skip to: 16833 + /* 13475 */ MCD_OPC_Decode, + 245, + 89, + 94, // Opcode: VZEXT_VF4 + /* 13479 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 13493 + /* 13484 */ MCD_OPC_CheckPredicate, + 5, + 16, + 13, + 0, // Skip to: 16833 + /* 13489 */ MCD_OPC_Decode, + 182, + 88, + 94, // Opcode: VSEXT_VF4 + /* 13493 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 13507 + /* 13498 */ MCD_OPC_CheckPredicate, + 5, + 2, + 13, + 0, // Skip to: 16833 + /* 13503 */ MCD_OPC_Decode, + 244, + 89, + 94, // Opcode: VZEXT_VF2 + /* 13507 */ MCD_OPC_FilterValue, + 7, + 249, + 12, + 0, // Skip to: 16833 + /* 13512 */ MCD_OPC_CheckPredicate, + 5, + 244, + 12, + 0, // Skip to: 16833 + /* 13517 */ MCD_OPC_Decode, + 181, + 88, + 94, // Opcode: VSEXT_VF2 + /* 13521 */ MCD_OPC_FilterValue, + 20, + 80, + 0, + 0, // Skip to: 13606 + /* 13526 */ MCD_OPC_ExtractField, + 15, + 5, // Inst{19-15} ... + /* 13529 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 13543 + /* 13534 */ MCD_OPC_CheckPredicate, + 5, + 222, + 12, + 0, // Skip to: 16833 + /* 13539 */ MCD_OPC_Decode, + 211, + 87, + 94, // Opcode: VMSBF_M + /* 13543 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 13557 + /* 13548 */ MCD_OPC_CheckPredicate, + 5, + 208, + 12, + 0, // Skip to: 16833 + /* 13553 */ MCD_OPC_Decode, + 233, + 87, + 94, // Opcode: VMSOF_M + /* 13557 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 13571 + /* 13562 */ MCD_OPC_CheckPredicate, + 5, + 194, + 12, + 0, // Skip to: 16833 + /* 13567 */ MCD_OPC_Decode, + 219, + 87, + 94, // Opcode: VMSIF_M + /* 13571 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 13585 + /* 13576 */ MCD_OPC_CheckPredicate, + 5, + 180, + 12, + 0, // Skip to: 16833 + /* 13581 */ MCD_OPC_Decode, + 248, + 85, + 94, // Opcode: VIOTA_M + /* 13585 */ MCD_OPC_FilterValue, + 17, + 171, + 12, + 0, // Skip to: 16833 + /* 13590 */ MCD_OPC_CheckPredicate, + 5, + 166, + 12, + 0, // Skip to: 16833 + /* 13595 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 159, + 12, + 0, // Skip to: 16833 + /* 13602 */ MCD_OPC_Decode, + 247, + 85, + 98, // Opcode: VID_V + /* 13606 */ MCD_OPC_FilterValue, + 23, + 16, + 0, + 0, // Skip to: 13627 + /* 13611 */ MCD_OPC_CheckPredicate, + 5, + 145, + 12, + 0, // Skip to: 16833 + /* 13616 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 138, + 12, + 0, // Skip to: 16833 + /* 13623 */ MCD_OPC_Decode, + 149, + 85, + 91, // Opcode: VCOMPRESS_VM + /* 13627 */ MCD_OPC_FilterValue, + 24, + 16, + 0, + 0, // Skip to: 13648 + /* 13632 */ MCD_OPC_CheckPredicate, + 5, + 124, + 12, + 0, // Skip to: 16833 + /* 13637 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 117, + 12, + 0, // Skip to: 16833 + /* 13644 */ MCD_OPC_Decode, + 180, + 87, + 91, // Opcode: VMANDN_MM + /* 13648 */ MCD_OPC_FilterValue, + 25, + 16, + 0, + 0, // Skip to: 13669 + /* 13653 */ MCD_OPC_CheckPredicate, + 5, + 103, + 12, + 0, // Skip to: 16833 + /* 13658 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 96, + 12, + 0, // Skip to: 16833 + /* 13665 */ MCD_OPC_Decode, + 181, + 87, + 91, // Opcode: VMAND_MM + /* 13669 */ MCD_OPC_FilterValue, + 26, + 16, + 0, + 0, // Skip to: 13690 + /* 13674 */ MCD_OPC_CheckPredicate, + 5, + 82, + 12, + 0, // Skip to: 16833 + /* 13679 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 75, + 12, + 0, // Skip to: 16833 + /* 13686 */ MCD_OPC_Decode, + 206, + 87, + 91, // Opcode: VMOR_MM + /* 13690 */ MCD_OPC_FilterValue, + 27, + 16, + 0, + 0, // Skip to: 13711 + /* 13695 */ MCD_OPC_CheckPredicate, + 5, + 61, + 12, + 0, // Skip to: 16833 + /* 13700 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 54, + 12, + 0, // Skip to: 16833 + /* 13707 */ MCD_OPC_Decode, + 252, + 87, + 91, // Opcode: VMXOR_MM + /* 13711 */ MCD_OPC_FilterValue, + 28, + 16, + 0, + 0, // Skip to: 13732 + /* 13716 */ MCD_OPC_CheckPredicate, + 5, + 40, + 12, + 0, // Skip to: 16833 + /* 13721 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 33, + 12, + 0, // Skip to: 16833 + /* 13728 */ MCD_OPC_Decode, + 205, + 87, + 91, // Opcode: VMORN_MM + /* 13732 */ MCD_OPC_FilterValue, + 29, + 16, + 0, + 0, // Skip to: 13753 + /* 13737 */ MCD_OPC_CheckPredicate, + 5, + 19, + 12, + 0, // Skip to: 16833 + /* 13742 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 12, + 12, + 0, // Skip to: 16833 + /* 13749 */ MCD_OPC_Decode, + 203, + 87, + 91, // Opcode: VMNAND_MM + /* 13753 */ MCD_OPC_FilterValue, + 30, + 16, + 0, + 0, // Skip to: 13774 + /* 13758 */ MCD_OPC_CheckPredicate, + 5, + 254, + 11, + 0, // Skip to: 16833 + /* 13763 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 247, + 11, + 0, // Skip to: 16833 + /* 13770 */ MCD_OPC_Decode, + 204, + 87, + 91, // Opcode: VMNOR_MM + /* 13774 */ MCD_OPC_FilterValue, + 31, + 16, + 0, + 0, // Skip to: 13795 + /* 13779 */ MCD_OPC_CheckPredicate, + 5, + 233, + 11, + 0, // Skip to: 16833 + /* 13784 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 226, + 11, + 0, // Skip to: 16833 + /* 13791 */ MCD_OPC_Decode, + 251, + 87, + 91, // Opcode: VMXNOR_MM + /* 13795 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 13809 + /* 13800 */ MCD_OPC_CheckPredicate, + 5, + 212, + 11, + 0, // Skip to: 16833 + /* 13805 */ MCD_OPC_Decode, + 151, + 85, + 90, // Opcode: VDIVU_VV + /* 13809 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 13823 + /* 13814 */ MCD_OPC_CheckPredicate, + 5, + 198, + 11, + 0, // Skip to: 16833 + /* 13819 */ MCD_OPC_Decode, + 153, + 85, + 90, // Opcode: VDIV_VV + /* 13823 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 13837 + /* 13828 */ MCD_OPC_CheckPredicate, + 5, + 184, + 11, + 0, // Skip to: 16833 + /* 13833 */ MCD_OPC_Decode, + 152, + 88, + 90, // Opcode: VREMU_VV + /* 13837 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 13851 + /* 13842 */ MCD_OPC_CheckPredicate, + 5, + 170, + 11, + 0, // Skip to: 16833 + /* 13847 */ MCD_OPC_Decode, + 154, + 88, + 90, // Opcode: VREM_VV + /* 13851 */ MCD_OPC_FilterValue, + 36, + 9, + 0, + 0, // Skip to: 13865 + /* 13856 */ MCD_OPC_CheckPredicate, + 5, + 156, + 11, + 0, // Skip to: 16833 + /* 13861 */ MCD_OPC_Decode, + 236, + 87, + 90, // Opcode: VMULHU_VV + /* 13865 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 13879 + /* 13870 */ MCD_OPC_CheckPredicate, + 5, + 142, + 11, + 0, // Skip to: 16833 + /* 13875 */ MCD_OPC_Decode, + 240, + 87, + 90, // Opcode: VMUL_VV + /* 13879 */ MCD_OPC_FilterValue, + 38, + 9, + 0, + 0, // Skip to: 13893 + /* 13884 */ MCD_OPC_CheckPredicate, + 5, + 128, + 11, + 0, // Skip to: 16833 + /* 13889 */ MCD_OPC_Decode, + 234, + 87, + 90, // Opcode: VMULHSU_VV + /* 13893 */ MCD_OPC_FilterValue, + 39, + 9, + 0, + 0, // Skip to: 13907 + /* 13898 */ MCD_OPC_CheckPredicate, + 5, + 114, + 11, + 0, // Skip to: 16833 + /* 13903 */ MCD_OPC_Decode, + 238, + 87, + 90, // Opcode: VMULH_VV + /* 13907 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 13921 + /* 13912 */ MCD_OPC_CheckPredicate, + 5, + 100, + 11, + 0, // Skip to: 16833 + /* 13917 */ MCD_OPC_Decode, + 178, + 87, + 95, // Opcode: VMADD_VV + /* 13921 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 13935 + /* 13926 */ MCD_OPC_CheckPredicate, + 5, + 86, + 11, + 0, // Skip to: 16833 + /* 13931 */ MCD_OPC_Decode, + 133, + 88, + 95, // Opcode: VNMSUB_VV + /* 13935 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 13949 + /* 13940 */ MCD_OPC_CheckPredicate, + 5, + 72, + 11, + 0, // Skip to: 16833 + /* 13945 */ MCD_OPC_Decode, + 170, + 87, + 95, // Opcode: VMACC_VV + /* 13949 */ MCD_OPC_FilterValue, + 47, + 9, + 0, + 0, // Skip to: 13963 + /* 13954 */ MCD_OPC_CheckPredicate, + 5, + 58, + 11, + 0, // Skip to: 16833 + /* 13959 */ MCD_OPC_Decode, + 131, + 88, + 95, // Opcode: VNMSAC_VV + /* 13963 */ MCD_OPC_FilterValue, + 48, + 9, + 0, + 0, // Skip to: 13977 + /* 13968 */ MCD_OPC_CheckPredicate, + 5, + 44, + 11, + 0, // Skip to: 16833 + /* 13973 */ MCD_OPC_Decode, + 210, + 89, + 90, // Opcode: VWADDU_VV + /* 13977 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 13991 + /* 13982 */ MCD_OPC_CheckPredicate, + 5, + 30, + 11, + 0, // Skip to: 16833 + /* 13987 */ MCD_OPC_Decode, + 214, + 89, + 90, // Opcode: VWADD_VV + /* 13991 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 14005 + /* 13996 */ MCD_OPC_CheckPredicate, + 5, + 16, + 11, + 0, // Skip to: 16833 + /* 14001 */ MCD_OPC_Decode, + 233, + 89, + 90, // Opcode: VWSUBU_VV + /* 14005 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 14019 + /* 14010 */ MCD_OPC_CheckPredicate, + 5, + 2, + 11, + 0, // Skip to: 16833 + /* 14015 */ MCD_OPC_Decode, + 237, + 89, + 90, // Opcode: VWSUB_VV + /* 14019 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 14033 + /* 14024 */ MCD_OPC_CheckPredicate, + 5, + 244, + 10, + 0, // Skip to: 16833 + /* 14029 */ MCD_OPC_Decode, + 212, + 89, + 90, // Opcode: VWADDU_WV + /* 14033 */ MCD_OPC_FilterValue, + 53, + 9, + 0, + 0, // Skip to: 14047 + /* 14038 */ MCD_OPC_CheckPredicate, + 5, + 230, + 10, + 0, // Skip to: 16833 + /* 14043 */ MCD_OPC_Decode, + 216, + 89, + 90, // Opcode: VWADD_WV + /* 14047 */ MCD_OPC_FilterValue, + 54, + 9, + 0, + 0, // Skip to: 14061 + /* 14052 */ MCD_OPC_CheckPredicate, + 5, + 216, + 10, + 0, // Skip to: 16833 + /* 14057 */ MCD_OPC_Decode, + 235, + 89, + 90, // Opcode: VWSUBU_WV + /* 14061 */ MCD_OPC_FilterValue, + 55, + 9, + 0, + 0, // Skip to: 14075 + /* 14066 */ MCD_OPC_CheckPredicate, + 5, + 202, + 10, + 0, // Skip to: 16833 + /* 14071 */ MCD_OPC_Decode, + 239, + 89, + 90, // Opcode: VWSUB_WV + /* 14075 */ MCD_OPC_FilterValue, + 56, + 9, + 0, + 0, // Skip to: 14089 + /* 14080 */ MCD_OPC_CheckPredicate, + 5, + 188, + 10, + 0, // Skip to: 16833 + /* 14085 */ MCD_OPC_Decode, + 227, + 89, + 90, // Opcode: VWMULU_VV + /* 14089 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 14103 + /* 14094 */ MCD_OPC_CheckPredicate, + 5, + 174, + 10, + 0, // Skip to: 16833 + /* 14099 */ MCD_OPC_Decode, + 225, + 89, + 90, // Opcode: VWMULSU_VV + /* 14103 */ MCD_OPC_FilterValue, + 59, + 9, + 0, + 0, // Skip to: 14117 + /* 14108 */ MCD_OPC_CheckPredicate, + 5, + 160, + 10, + 0, // Skip to: 16833 + /* 14113 */ MCD_OPC_Decode, + 229, + 89, + 90, // Opcode: VWMUL_VV + /* 14117 */ MCD_OPC_FilterValue, + 60, + 9, + 0, + 0, // Skip to: 14131 + /* 14122 */ MCD_OPC_CheckPredicate, + 5, + 146, + 10, + 0, // Skip to: 16833 + /* 14127 */ MCD_OPC_Decode, + 221, + 89, + 95, // Opcode: VWMACCU_VV + /* 14131 */ MCD_OPC_FilterValue, + 61, + 9, + 0, + 0, // Skip to: 14145 + /* 14136 */ MCD_OPC_CheckPredicate, + 5, + 132, + 10, + 0, // Skip to: 16833 + /* 14141 */ MCD_OPC_Decode, + 223, + 89, + 95, // Opcode: VWMACC_VV + /* 14145 */ MCD_OPC_FilterValue, + 63, + 123, + 10, + 0, // Skip to: 16833 + /* 14150 */ MCD_OPC_CheckPredicate, + 5, + 118, + 10, + 0, // Skip to: 16833 + /* 14155 */ MCD_OPC_Decode, + 218, + 89, + 95, // Opcode: VWMACCSU_VV + /* 14159 */ MCD_OPC_FilterValue, + 3, + 33, + 2, + 0, // Skip to: 14709 + /* 14164 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 14167 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14181 + /* 14172 */ MCD_OPC_CheckPredicate, + 5, + 96, + 10, + 0, // Skip to: 16833 + /* 14177 */ MCD_OPC_Decode, + 195, + 84, + 99, // Opcode: VADD_VI + /* 14181 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 14195 + /* 14186 */ MCD_OPC_CheckPredicate, + 5, + 82, + 10, + 0, // Skip to: 16833 + /* 14191 */ MCD_OPC_Decode, + 160, + 88, + 99, // Opcode: VRSUB_VI + /* 14195 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 14209 + /* 14200 */ MCD_OPC_CheckPredicate, + 5, + 68, + 10, + 0, // Skip to: 16833 + /* 14205 */ MCD_OPC_Decode, + 142, + 85, + 99, // Opcode: VAND_VI + /* 14209 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 14223 + /* 14214 */ MCD_OPC_CheckPredicate, + 5, + 54, + 10, + 0, // Skip to: 16833 + /* 14219 */ MCD_OPC_Decode, + 141, + 88, + 99, // Opcode: VOR_VI + /* 14223 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 14237 + /* 14228 */ MCD_OPC_CheckPredicate, + 5, + 40, + 10, + 0, // Skip to: 16833 + /* 14233 */ MCD_OPC_Decode, + 241, + 89, + 99, // Opcode: VXOR_VI + /* 14237 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 14251 + /* 14242 */ MCD_OPC_CheckPredicate, + 5, + 26, + 10, + 0, // Skip to: 16833 + /* 14247 */ MCD_OPC_Decode, + 157, + 88, + 100, // Opcode: VRGATHER_VI + /* 14251 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 14265 + /* 14256 */ MCD_OPC_CheckPredicate, + 5, + 12, + 10, + 0, // Skip to: 16833 + /* 14261 */ MCD_OPC_Decode, + 188, + 88, + 100, // Opcode: VSLIDEUP_VI + /* 14265 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 14279 + /* 14270 */ MCD_OPC_CheckPredicate, + 5, + 254, + 9, + 0, // Skip to: 16833 + /* 14275 */ MCD_OPC_Decode, + 186, + 88, + 100, // Opcode: VSLIDEDOWN_VI + /* 14279 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 14300 + /* 14284 */ MCD_OPC_CheckPredicate, + 5, + 240, + 9, + 0, // Skip to: 16833 + /* 14289 */ MCD_OPC_CheckField, + 25, + 1, + 0, + 233, + 9, + 0, // Skip to: 16833 + /* 14296 */ MCD_OPC_Decode, + 192, + 84, + 101, // Opcode: VADC_VIM + /* 14300 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 14336 + /* 14305 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 14308 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14322 + /* 14313 */ MCD_OPC_CheckPredicate, + 5, + 211, + 9, + 0, // Skip to: 16833 + /* 14318 */ MCD_OPC_Decode, + 173, + 87, + 101, // Opcode: VMADC_VIM + /* 14322 */ MCD_OPC_FilterValue, + 1, + 202, + 9, + 0, // Skip to: 16833 + /* 14327 */ MCD_OPC_CheckPredicate, + 5, + 197, + 9, + 0, // Skip to: 16833 + /* 14332 */ MCD_OPC_Decode, + 172, + 87, + 101, // Opcode: VMADC_VI + /* 14336 */ MCD_OPC_FilterValue, + 23, + 38, + 0, + 0, // Skip to: 14379 + /* 14341 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 14344 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14358 + /* 14349 */ MCD_OPC_CheckPredicate, + 5, + 175, + 9, + 0, // Skip to: 16833 + /* 14354 */ MCD_OPC_Decode, + 186, + 87, + 101, // Opcode: VMERGE_VIM + /* 14358 */ MCD_OPC_FilterValue, + 1, + 166, + 9, + 0, // Skip to: 16833 + /* 14363 */ MCD_OPC_CheckPredicate, + 5, + 161, + 9, + 0, // Skip to: 16833 + /* 14368 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 154, + 9, + 0, // Skip to: 16833 + /* 14375 */ MCD_OPC_Decode, + 247, + 87, + 102, // Opcode: VMV_V_I + /* 14379 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 14393 + /* 14384 */ MCD_OPC_CheckPredicate, + 5, + 140, + 9, + 0, // Skip to: 16833 + /* 14389 */ MCD_OPC_Decode, + 212, + 87, + 99, // Opcode: VMSEQ_VI + /* 14393 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 14407 + /* 14398 */ MCD_OPC_CheckPredicate, + 5, + 126, + 9, + 0, // Skip to: 16833 + /* 14403 */ MCD_OPC_Decode, + 230, + 87, + 99, // Opcode: VMSNE_VI + /* 14407 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 14421 + /* 14412 */ MCD_OPC_CheckPredicate, + 5, + 112, + 9, + 0, // Skip to: 16833 + /* 14417 */ MCD_OPC_Decode, + 220, + 87, + 99, // Opcode: VMSLEU_VI + /* 14421 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 14435 + /* 14426 */ MCD_OPC_CheckPredicate, + 5, + 98, + 9, + 0, // Skip to: 16833 + /* 14431 */ MCD_OPC_Decode, + 223, + 87, + 99, // Opcode: VMSLE_VI + /* 14435 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 14449 + /* 14440 */ MCD_OPC_CheckPredicate, + 5, + 84, + 9, + 0, // Skip to: 16833 + /* 14445 */ MCD_OPC_Decode, + 215, + 87, + 99, // Opcode: VMSGTU_VI + /* 14449 */ MCD_OPC_FilterValue, + 31, + 9, + 0, + 0, // Skip to: 14463 + /* 14454 */ MCD_OPC_CheckPredicate, + 5, + 70, + 9, + 0, // Skip to: 16833 + /* 14459 */ MCD_OPC_Decode, + 217, + 87, + 99, // Opcode: VMSGT_VI + /* 14463 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 14477 + /* 14468 */ MCD_OPC_CheckPredicate, + 5, + 56, + 9, + 0, // Skip to: 16833 + /* 14473 */ MCD_OPC_Decode, + 166, + 88, + 99, // Opcode: VSADDU_VI + /* 14477 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 14491 + /* 14482 */ MCD_OPC_CheckPredicate, + 5, + 42, + 9, + 0, // Skip to: 16833 + /* 14487 */ MCD_OPC_Decode, + 169, + 88, + 99, // Opcode: VSADD_VI + /* 14491 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 14505 + /* 14496 */ MCD_OPC_CheckPredicate, + 5, + 28, + 9, + 0, // Skip to: 16833 + /* 14501 */ MCD_OPC_Decode, + 190, + 88, + 100, // Opcode: VSLL_VI + /* 14505 */ MCD_OPC_FilterValue, + 39, + 87, + 0, + 0, // Skip to: 14597 + /* 14510 */ MCD_OPC_ExtractField, + 15, + 5, // Inst{19-15} ... + /* 14513 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 14534 + /* 14518 */ MCD_OPC_CheckPredicate, + 5, + 6, + 9, + 0, // Skip to: 16833 + /* 14523 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 255, + 8, + 0, // Skip to: 16833 + /* 14530 */ MCD_OPC_Decode, + 242, + 87, + 103, // Opcode: VMV1R_V + /* 14534 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 14555 + /* 14539 */ MCD_OPC_CheckPredicate, + 5, + 241, + 8, + 0, // Skip to: 16833 + /* 14544 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 234, + 8, + 0, // Skip to: 16833 + /* 14551 */ MCD_OPC_Decode, + 243, + 87, + 103, // Opcode: VMV2R_V + /* 14555 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 14576 + /* 14560 */ MCD_OPC_CheckPredicate, + 5, + 220, + 8, + 0, // Skip to: 16833 + /* 14565 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 213, + 8, + 0, // Skip to: 16833 + /* 14572 */ MCD_OPC_Decode, + 244, + 87, + 103, // Opcode: VMV4R_V + /* 14576 */ MCD_OPC_FilterValue, + 7, + 204, + 8, + 0, // Skip to: 16833 + /* 14581 */ MCD_OPC_CheckPredicate, + 5, + 199, + 8, + 0, // Skip to: 16833 + /* 14586 */ MCD_OPC_CheckField, + 25, + 1, + 1, + 192, + 8, + 0, // Skip to: 16833 + /* 14593 */ MCD_OPC_Decode, + 245, + 87, + 103, // Opcode: VMV8R_V + /* 14597 */ MCD_OPC_FilterValue, + 40, + 9, + 0, + 0, // Skip to: 14611 + /* 14602 */ MCD_OPC_CheckPredicate, + 5, + 178, + 8, + 0, // Skip to: 16833 + /* 14607 */ MCD_OPC_Decode, + 231, + 88, + 100, // Opcode: VSRL_VI + /* 14611 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 14625 + /* 14616 */ MCD_OPC_CheckPredicate, + 5, + 164, + 8, + 0, // Skip to: 16833 + /* 14621 */ MCD_OPC_Decode, + 228, + 88, + 100, // Opcode: VSRA_VI + /* 14625 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 14639 + /* 14630 */ MCD_OPC_CheckPredicate, + 5, + 150, + 8, + 0, // Skip to: 16833 + /* 14635 */ MCD_OPC_Decode, + 141, + 89, + 100, // Opcode: VSSRL_VI + /* 14639 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 14653 + /* 14644 */ MCD_OPC_CheckPredicate, + 5, + 136, + 8, + 0, // Skip to: 16833 + /* 14649 */ MCD_OPC_Decode, + 138, + 89, + 100, // Opcode: VSSRA_VI + /* 14653 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 14667 + /* 14658 */ MCD_OPC_CheckPredicate, + 5, + 122, + 8, + 0, // Skip to: 16833 + /* 14663 */ MCD_OPC_Decode, + 138, + 88, + 100, // Opcode: VNSRL_WI + /* 14667 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 14681 + /* 14672 */ MCD_OPC_CheckPredicate, + 5, + 108, + 8, + 0, // Skip to: 16833 + /* 14677 */ MCD_OPC_Decode, + 135, + 88, + 100, // Opcode: VNSRA_WI + /* 14681 */ MCD_OPC_FilterValue, + 46, + 9, + 0, + 0, // Skip to: 14695 + /* 14686 */ MCD_OPC_CheckPredicate, + 5, + 94, + 8, + 0, // Skip to: 16833 + /* 14691 */ MCD_OPC_Decode, + 253, + 87, + 100, // Opcode: VNCLIPU_WI + /* 14695 */ MCD_OPC_FilterValue, + 47, + 85, + 8, + 0, // Skip to: 16833 + /* 14700 */ MCD_OPC_CheckPredicate, + 5, + 80, + 8, + 0, // Skip to: 16833 + /* 14705 */ MCD_OPC_Decode, + 128, + 88, + 100, // Opcode: VNCLIP_WI + /* 14709 */ MCD_OPC_FilterValue, + 4, + 138, + 2, + 0, // Skip to: 15364 + /* 14714 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 14717 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14731 + /* 14722 */ MCD_OPC_CheckPredicate, + 5, + 58, + 8, + 0, // Skip to: 16833 + /* 14727 */ MCD_OPC_Decode, + 197, + 84, + 104, // Opcode: VADD_VX + /* 14731 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 14745 + /* 14736 */ MCD_OPC_CheckPredicate, + 5, + 44, + 8, + 0, // Skip to: 16833 + /* 14741 */ MCD_OPC_Decode, + 177, + 89, + 104, // Opcode: VSUB_VX + /* 14745 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 14759 + /* 14750 */ MCD_OPC_CheckPredicate, + 5, + 30, + 8, + 0, // Skip to: 16833 + /* 14755 */ MCD_OPC_Decode, + 161, + 88, + 104, // Opcode: VRSUB_VX + /* 14759 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 14773 + /* 14764 */ MCD_OPC_CheckPredicate, + 5, + 16, + 8, + 0, // Skip to: 16833 + /* 14769 */ MCD_OPC_Decode, + 200, + 87, + 104, // Opcode: VMINU_VX + /* 14773 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 14787 + /* 14778 */ MCD_OPC_CheckPredicate, + 5, + 2, + 8, + 0, // Skip to: 16833 + /* 14783 */ MCD_OPC_Decode, + 202, + 87, + 104, // Opcode: VMIN_VX + /* 14787 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 14801 + /* 14792 */ MCD_OPC_CheckPredicate, + 5, + 244, + 7, + 0, // Skip to: 16833 + /* 14797 */ MCD_OPC_Decode, + 183, + 87, + 104, // Opcode: VMAXU_VX + /* 14801 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 14815 + /* 14806 */ MCD_OPC_CheckPredicate, + 5, + 230, + 7, + 0, // Skip to: 16833 + /* 14811 */ MCD_OPC_Decode, + 185, + 87, + 104, // Opcode: VMAX_VX + /* 14815 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 14829 + /* 14820 */ MCD_OPC_CheckPredicate, + 5, + 216, + 7, + 0, // Skip to: 16833 + /* 14825 */ MCD_OPC_Decode, + 144, + 85, + 104, // Opcode: VAND_VX + /* 14829 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 14843 + /* 14834 */ MCD_OPC_CheckPredicate, + 5, + 202, + 7, + 0, // Skip to: 16833 + /* 14839 */ MCD_OPC_Decode, + 143, + 88, + 104, // Opcode: VOR_VX + /* 14843 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 14857 + /* 14848 */ MCD_OPC_CheckPredicate, + 5, + 188, + 7, + 0, // Skip to: 16833 + /* 14853 */ MCD_OPC_Decode, + 243, + 89, + 104, // Opcode: VXOR_VX + /* 14857 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 14871 + /* 14862 */ MCD_OPC_CheckPredicate, + 5, + 174, + 7, + 0, // Skip to: 16833 + /* 14867 */ MCD_OPC_Decode, + 159, + 88, + 104, // Opcode: VRGATHER_VX + /* 14871 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 14885 + /* 14876 */ MCD_OPC_CheckPredicate, + 5, + 160, + 7, + 0, // Skip to: 16833 + /* 14881 */ MCD_OPC_Decode, + 189, + 88, + 104, // Opcode: VSLIDEUP_VX + /* 14885 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 14899 + /* 14890 */ MCD_OPC_CheckPredicate, + 5, + 146, + 7, + 0, // Skip to: 16833 + /* 14895 */ MCD_OPC_Decode, + 187, + 88, + 104, // Opcode: VSLIDEDOWN_VX + /* 14899 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 14920 + /* 14904 */ MCD_OPC_CheckPredicate, + 5, + 132, + 7, + 0, // Skip to: 16833 + /* 14909 */ MCD_OPC_CheckField, + 25, + 1, + 0, + 125, + 7, + 0, // Skip to: 16833 + /* 14916 */ MCD_OPC_Decode, + 194, + 84, + 105, // Opcode: VADC_VXM + /* 14920 */ MCD_OPC_FilterValue, + 17, + 31, + 0, + 0, // Skip to: 14956 + /* 14925 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 14928 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14942 + /* 14933 */ MCD_OPC_CheckPredicate, + 5, + 103, + 7, + 0, // Skip to: 16833 + /* 14938 */ MCD_OPC_Decode, + 177, + 87, + 105, // Opcode: VMADC_VXM + /* 14942 */ MCD_OPC_FilterValue, + 1, + 94, + 7, + 0, // Skip to: 16833 + /* 14947 */ MCD_OPC_CheckPredicate, + 5, + 89, + 7, + 0, // Skip to: 16833 + /* 14952 */ MCD_OPC_Decode, + 176, + 87, + 105, // Opcode: VMADC_VX + /* 14956 */ MCD_OPC_FilterValue, + 18, + 16, + 0, + 0, // Skip to: 14977 + /* 14961 */ MCD_OPC_CheckPredicate, + 5, + 75, + 7, + 0, // Skip to: 16833 + /* 14966 */ MCD_OPC_CheckField, + 25, + 1, + 0, + 68, + 7, + 0, // Skip to: 16833 + /* 14973 */ MCD_OPC_Decode, + 173, + 88, + 105, // Opcode: VSBC_VXM + /* 14977 */ MCD_OPC_FilterValue, + 19, + 31, + 0, + 0, // Skip to: 15013 + /* 14982 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 14985 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 14999 + /* 14990 */ MCD_OPC_CheckPredicate, + 5, + 46, + 7, + 0, // Skip to: 16833 + /* 14995 */ MCD_OPC_Decode, + 210, + 87, + 105, // Opcode: VMSBC_VXM + /* 14999 */ MCD_OPC_FilterValue, + 1, + 37, + 7, + 0, // Skip to: 16833 + /* 15004 */ MCD_OPC_CheckPredicate, + 5, + 32, + 7, + 0, // Skip to: 16833 + /* 15009 */ MCD_OPC_Decode, + 209, + 87, + 105, // Opcode: VMSBC_VX + /* 15013 */ MCD_OPC_FilterValue, + 23, + 38, + 0, + 0, // Skip to: 15056 + /* 15018 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 15021 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15035 + /* 15026 */ MCD_OPC_CheckPredicate, + 5, + 10, + 7, + 0, // Skip to: 16833 + /* 15031 */ MCD_OPC_Decode, + 188, + 87, + 105, // Opcode: VMERGE_VXM + /* 15035 */ MCD_OPC_FilterValue, + 1, + 1, + 7, + 0, // Skip to: 16833 + /* 15040 */ MCD_OPC_CheckPredicate, + 5, + 252, + 6, + 0, // Skip to: 16833 + /* 15045 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 245, + 6, + 0, // Skip to: 16833 + /* 15052 */ MCD_OPC_Decode, + 249, + 87, + 33, // Opcode: VMV_V_X + /* 15056 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 15070 + /* 15061 */ MCD_OPC_CheckPredicate, + 5, + 231, + 6, + 0, // Skip to: 16833 + /* 15066 */ MCD_OPC_Decode, + 214, + 87, + 104, // Opcode: VMSEQ_VX + /* 15070 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 15084 + /* 15075 */ MCD_OPC_CheckPredicate, + 5, + 217, + 6, + 0, // Skip to: 16833 + /* 15080 */ MCD_OPC_Decode, + 232, + 87, + 104, // Opcode: VMSNE_VX + /* 15084 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 15098 + /* 15089 */ MCD_OPC_CheckPredicate, + 5, + 203, + 6, + 0, // Skip to: 16833 + /* 15094 */ MCD_OPC_Decode, + 227, + 87, + 104, // Opcode: VMSLTU_VX + /* 15098 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 15112 + /* 15103 */ MCD_OPC_CheckPredicate, + 5, + 189, + 6, + 0, // Skip to: 16833 + /* 15108 */ MCD_OPC_Decode, + 229, + 87, + 104, // Opcode: VMSLT_VX + /* 15112 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 15126 + /* 15117 */ MCD_OPC_CheckPredicate, + 5, + 175, + 6, + 0, // Skip to: 16833 + /* 15122 */ MCD_OPC_Decode, + 222, + 87, + 104, // Opcode: VMSLEU_VX + /* 15126 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 15140 + /* 15131 */ MCD_OPC_CheckPredicate, + 5, + 161, + 6, + 0, // Skip to: 16833 + /* 15136 */ MCD_OPC_Decode, + 225, + 87, + 104, // Opcode: VMSLE_VX + /* 15140 */ MCD_OPC_FilterValue, + 30, + 9, + 0, + 0, // Skip to: 15154 + /* 15145 */ MCD_OPC_CheckPredicate, + 5, + 147, + 6, + 0, // Skip to: 16833 + /* 15150 */ MCD_OPC_Decode, + 216, + 87, + 104, // Opcode: VMSGTU_VX + /* 15154 */ MCD_OPC_FilterValue, + 31, + 9, + 0, + 0, // Skip to: 15168 + /* 15159 */ MCD_OPC_CheckPredicate, + 5, + 133, + 6, + 0, // Skip to: 16833 + /* 15164 */ MCD_OPC_Decode, + 218, + 87, + 104, // Opcode: VMSGT_VX + /* 15168 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 15182 + /* 15173 */ MCD_OPC_CheckPredicate, + 5, + 119, + 6, + 0, // Skip to: 16833 + /* 15178 */ MCD_OPC_Decode, + 168, + 88, + 104, // Opcode: VSADDU_VX + /* 15182 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 15196 + /* 15187 */ MCD_OPC_CheckPredicate, + 5, + 105, + 6, + 0, // Skip to: 16833 + /* 15192 */ MCD_OPC_Decode, + 171, + 88, + 104, // Opcode: VSADD_VX + /* 15196 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 15210 + /* 15201 */ MCD_OPC_CheckPredicate, + 5, + 91, + 6, + 0, // Skip to: 16833 + /* 15206 */ MCD_OPC_Decode, + 173, + 89, + 104, // Opcode: VSSUBU_VX + /* 15210 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 15224 + /* 15215 */ MCD_OPC_CheckPredicate, + 5, + 77, + 6, + 0, // Skip to: 16833 + /* 15220 */ MCD_OPC_Decode, + 175, + 89, + 104, // Opcode: VSSUB_VX + /* 15224 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 15238 + /* 15229 */ MCD_OPC_CheckPredicate, + 5, + 63, + 6, + 0, // Skip to: 16833 + /* 15234 */ MCD_OPC_Decode, + 192, + 88, + 104, // Opcode: VSLL_VX + /* 15238 */ MCD_OPC_FilterValue, + 39, + 9, + 0, + 0, // Skip to: 15252 + /* 15243 */ MCD_OPC_CheckPredicate, + 5, + 49, + 6, + 0, // Skip to: 16833 + /* 15248 */ MCD_OPC_Decode, + 194, + 88, + 104, // Opcode: VSMUL_VX + /* 15252 */ MCD_OPC_FilterValue, + 40, + 9, + 0, + 0, // Skip to: 15266 + /* 15257 */ MCD_OPC_CheckPredicate, + 5, + 35, + 6, + 0, // Skip to: 16833 + /* 15262 */ MCD_OPC_Decode, + 233, + 88, + 104, // Opcode: VSRL_VX + /* 15266 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 15280 + /* 15271 */ MCD_OPC_CheckPredicate, + 5, + 21, + 6, + 0, // Skip to: 16833 + /* 15276 */ MCD_OPC_Decode, + 230, + 88, + 104, // Opcode: VSRA_VX + /* 15280 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 15294 + /* 15285 */ MCD_OPC_CheckPredicate, + 5, + 7, + 6, + 0, // Skip to: 16833 + /* 15290 */ MCD_OPC_Decode, + 143, + 89, + 104, // Opcode: VSSRL_VX + /* 15294 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 15308 + /* 15299 */ MCD_OPC_CheckPredicate, + 5, + 249, + 5, + 0, // Skip to: 16833 + /* 15304 */ MCD_OPC_Decode, + 140, + 89, + 104, // Opcode: VSSRA_VX + /* 15308 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 15322 + /* 15313 */ MCD_OPC_CheckPredicate, + 5, + 235, + 5, + 0, // Skip to: 16833 + /* 15318 */ MCD_OPC_Decode, + 140, + 88, + 104, // Opcode: VNSRL_WX + /* 15322 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 15336 + /* 15327 */ MCD_OPC_CheckPredicate, + 5, + 221, + 5, + 0, // Skip to: 16833 + /* 15332 */ MCD_OPC_Decode, + 137, + 88, + 104, // Opcode: VNSRA_WX + /* 15336 */ MCD_OPC_FilterValue, + 46, + 9, + 0, + 0, // Skip to: 15350 + /* 15341 */ MCD_OPC_CheckPredicate, + 5, + 207, + 5, + 0, // Skip to: 16833 + /* 15346 */ MCD_OPC_Decode, + 255, + 87, + 104, // Opcode: VNCLIPU_WX + /* 15350 */ MCD_OPC_FilterValue, + 47, + 198, + 5, + 0, // Skip to: 16833 + /* 15355 */ MCD_OPC_CheckPredicate, + 5, + 193, + 5, + 0, // Skip to: 16833 + /* 15360 */ MCD_OPC_Decode, + 130, + 88, + 104, // Opcode: VNCLIP_WX + /* 15364 */ MCD_OPC_FilterValue, + 5, + 59, + 2, + 0, // Skip to: 15940 + /* 15369 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 15372 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15386 + /* 15377 */ MCD_OPC_CheckPredicate, + 41, + 171, + 5, + 0, // Skip to: 16833 + /* 15382 */ MCD_OPC_Decode, + 155, + 85, + 106, // Opcode: VFADD_VF + /* 15386 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 15400 + /* 15391 */ MCD_OPC_CheckPredicate, + 41, + 157, + 5, + 0, // Skip to: 16833 + /* 15396 */ MCD_OPC_Decode, + 218, + 85, + 106, // Opcode: VFSUB_VF + /* 15400 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 15414 + /* 15405 */ MCD_OPC_CheckPredicate, + 41, + 143, + 5, + 0, // Skip to: 16833 + /* 15410 */ MCD_OPC_Decode, + 174, + 85, + 106, // Opcode: VFMIN_VF + /* 15414 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 15428 + /* 15419 */ MCD_OPC_CheckPredicate, + 41, + 129, + 5, + 0, // Skip to: 16833 + /* 15424 */ MCD_OPC_Decode, + 171, + 85, + 106, // Opcode: VFMAX_VF + /* 15428 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 15442 + /* 15433 */ MCD_OPC_CheckPredicate, + 41, + 115, + 5, + 0, // Skip to: 16833 + /* 15438 */ MCD_OPC_Decode, + 213, + 85, + 106, // Opcode: VFSGNJ_VF + /* 15442 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 15456 + /* 15447 */ MCD_OPC_CheckPredicate, + 41, + 101, + 5, + 0, // Skip to: 16833 + /* 15452 */ MCD_OPC_Decode, + 209, + 85, + 106, // Opcode: VFSGNJN_VF + /* 15456 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 15470 + /* 15461 */ MCD_OPC_CheckPredicate, + 41, + 87, + 5, + 0, // Skip to: 16833 + /* 15466 */ MCD_OPC_Decode, + 211, + 85, + 106, // Opcode: VFSGNJX_VF + /* 15470 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 15484 + /* 15475 */ MCD_OPC_CheckPredicate, + 41, + 73, + 5, + 0, // Skip to: 16833 + /* 15480 */ MCD_OPC_Decode, + 216, + 85, + 106, // Opcode: VFSLIDE1UP_VF + /* 15484 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 15498 + /* 15489 */ MCD_OPC_CheckPredicate, + 41, + 59, + 5, + 0, // Skip to: 16833 + /* 15494 */ MCD_OPC_Decode, + 215, + 85, + 106, // Opcode: VFSLIDE1DOWN_VF + /* 15498 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 15519 + /* 15503 */ MCD_OPC_CheckPredicate, + 41, + 45, + 5, + 0, // Skip to: 16833 + /* 15508 */ MCD_OPC_CheckField, + 20, + 6, + 32, + 38, + 5, + 0, // Skip to: 16833 + /* 15515 */ MCD_OPC_Decode, + 183, + 85, + 107, // Opcode: VFMV_S_F + /* 15519 */ MCD_OPC_FilterValue, + 23, + 38, + 0, + 0, // Skip to: 15562 + /* 15524 */ MCD_OPC_ExtractField, + 25, + 1, // Inst{25} ... + /* 15527 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 15541 + /* 15532 */ MCD_OPC_CheckPredicate, + 41, + 16, + 5, + 0, // Skip to: 16833 + /* 15537 */ MCD_OPC_Decode, + 173, + 85, + 108, // Opcode: VFMERGE_VFM + /* 15541 */ MCD_OPC_FilterValue, + 1, + 7, + 5, + 0, // Skip to: 16833 + /* 15546 */ MCD_OPC_CheckPredicate, + 41, + 2, + 5, + 0, // Skip to: 16833 + /* 15551 */ MCD_OPC_CheckField, + 20, + 5, + 0, + 251, + 4, + 0, // Skip to: 16833 + /* 15558 */ MCD_OPC_Decode, + 184, + 85, + 109, // Opcode: VFMV_V_F + /* 15562 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 15576 + /* 15567 */ MCD_OPC_CheckPredicate, + 41, + 237, + 4, + 0, // Skip to: 16833 + /* 15572 */ MCD_OPC_Decode, + 189, + 87, + 106, // Opcode: VMFEQ_VF + /* 15576 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 15590 + /* 15581 */ MCD_OPC_CheckPredicate, + 41, + 223, + 4, + 0, // Skip to: 16833 + /* 15586 */ MCD_OPC_Decode, + 193, + 87, + 106, // Opcode: VMFLE_VF + /* 15590 */ MCD_OPC_FilterValue, + 27, + 9, + 0, + 0, // Skip to: 15604 + /* 15595 */ MCD_OPC_CheckPredicate, + 41, + 209, + 4, + 0, // Skip to: 16833 + /* 15600 */ MCD_OPC_Decode, + 195, + 87, + 106, // Opcode: VMFLT_VF + /* 15604 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 15618 + /* 15609 */ MCD_OPC_CheckPredicate, + 41, + 195, + 4, + 0, // Skip to: 16833 + /* 15614 */ MCD_OPC_Decode, + 197, + 87, + 106, // Opcode: VMFNE_VF + /* 15618 */ MCD_OPC_FilterValue, + 29, + 9, + 0, + 0, // Skip to: 15632 + /* 15623 */ MCD_OPC_CheckPredicate, + 41, + 181, + 4, + 0, // Skip to: 16833 + /* 15628 */ MCD_OPC_Decode, + 192, + 87, + 106, // Opcode: VMFGT_VF + /* 15632 */ MCD_OPC_FilterValue, + 31, + 9, + 0, + 0, // Skip to: 15646 + /* 15637 */ MCD_OPC_CheckPredicate, + 41, + 167, + 4, + 0, // Skip to: 16833 + /* 15642 */ MCD_OPC_Decode, + 191, + 87, + 106, // Opcode: VMFGE_VF + /* 15646 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 15660 + /* 15651 */ MCD_OPC_CheckPredicate, + 41, + 153, + 4, + 0, // Skip to: 16833 + /* 15656 */ MCD_OPC_Decode, + 164, + 85, + 106, // Opcode: VFDIV_VF + /* 15660 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 15674 + /* 15665 */ MCD_OPC_CheckPredicate, + 41, + 139, + 4, + 0, // Skip to: 16833 + /* 15670 */ MCD_OPC_Decode, + 201, + 85, + 106, // Opcode: VFRDIV_VF + /* 15674 */ MCD_OPC_FilterValue, + 36, + 9, + 0, + 0, // Skip to: 15688 + /* 15679 */ MCD_OPC_CheckPredicate, + 41, + 125, + 4, + 0, // Skip to: 16833 + /* 15684 */ MCD_OPC_Decode, + 180, + 85, + 106, // Opcode: VFMUL_VF + /* 15688 */ MCD_OPC_FilterValue, + 39, + 9, + 0, + 0, // Skip to: 15702 + /* 15693 */ MCD_OPC_CheckPredicate, + 41, + 111, + 4, + 0, // Skip to: 16833 + /* 15698 */ MCD_OPC_Decode, + 208, + 85, + 106, // Opcode: VFRSUB_VF + /* 15702 */ MCD_OPC_FilterValue, + 40, + 9, + 0, + 0, // Skip to: 15716 + /* 15707 */ MCD_OPC_CheckPredicate, + 41, + 97, + 4, + 0, // Skip to: 16833 + /* 15712 */ MCD_OPC_Decode, + 169, + 85, + 110, // Opcode: VFMADD_VF + /* 15716 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 15730 + /* 15721 */ MCD_OPC_CheckPredicate, + 41, + 83, + 4, + 0, // Skip to: 16833 + /* 15726 */ MCD_OPC_Decode, + 195, + 85, + 110, // Opcode: VFNMADD_VF + /* 15730 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 15744 + /* 15735 */ MCD_OPC_CheckPredicate, + 41, + 69, + 4, + 0, // Skip to: 16833 + /* 15740 */ MCD_OPC_Decode, + 178, + 85, + 110, // Opcode: VFMSUB_VF + /* 15744 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 15758 + /* 15749 */ MCD_OPC_CheckPredicate, + 41, + 55, + 4, + 0, // Skip to: 16833 + /* 15754 */ MCD_OPC_Decode, + 199, + 85, + 110, // Opcode: VFNMSUB_VF + /* 15758 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 15772 + /* 15763 */ MCD_OPC_CheckPredicate, + 41, + 41, + 4, + 0, // Skip to: 16833 + /* 15768 */ MCD_OPC_Decode, + 167, + 85, + 110, // Opcode: VFMACC_VF + /* 15772 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 15786 + /* 15777 */ MCD_OPC_CheckPredicate, + 41, + 27, + 4, + 0, // Skip to: 16833 + /* 15782 */ MCD_OPC_Decode, + 193, + 85, + 110, // Opcode: VFNMACC_VF + /* 15786 */ MCD_OPC_FilterValue, + 46, + 9, + 0, + 0, // Skip to: 15800 + /* 15791 */ MCD_OPC_CheckPredicate, + 41, + 13, + 4, + 0, // Skip to: 16833 + /* 15796 */ MCD_OPC_Decode, + 176, + 85, + 110, // Opcode: VFMSAC_VF + /* 15800 */ MCD_OPC_FilterValue, + 47, + 9, + 0, + 0, // Skip to: 15814 + /* 15805 */ MCD_OPC_CheckPredicate, + 41, + 255, + 3, + 0, // Skip to: 16833 + /* 15810 */ MCD_OPC_Decode, + 197, + 85, + 110, // Opcode: VFNMSAC_VF + /* 15814 */ MCD_OPC_FilterValue, + 48, + 9, + 0, + 0, // Skip to: 15828 + /* 15819 */ MCD_OPC_CheckPredicate, + 41, + 241, + 3, + 0, // Skip to: 16833 + /* 15824 */ MCD_OPC_Decode, + 220, + 85, + 106, // Opcode: VFWADD_VF + /* 15828 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 15842 + /* 15833 */ MCD_OPC_CheckPredicate, + 41, + 227, + 3, + 0, // Skip to: 16833 + /* 15838 */ MCD_OPC_Decode, + 243, + 85, + 106, // Opcode: VFWSUB_VF + /* 15842 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 15856 + /* 15847 */ MCD_OPC_CheckPredicate, + 41, + 213, + 3, + 0, // Skip to: 16833 + /* 15852 */ MCD_OPC_Decode, + 222, + 85, + 106, // Opcode: VFWADD_WF + /* 15856 */ MCD_OPC_FilterValue, + 54, + 9, + 0, + 0, // Skip to: 15870 + /* 15861 */ MCD_OPC_CheckPredicate, + 41, + 199, + 3, + 0, // Skip to: 16833 + /* 15866 */ MCD_OPC_Decode, + 245, + 85, + 106, // Opcode: VFWSUB_WF + /* 15870 */ MCD_OPC_FilterValue, + 56, + 9, + 0, + 0, // Skip to: 15884 + /* 15875 */ MCD_OPC_CheckPredicate, + 41, + 185, + 3, + 0, // Skip to: 16833 + /* 15880 */ MCD_OPC_Decode, + 235, + 85, + 106, // Opcode: VFWMUL_VF + /* 15884 */ MCD_OPC_FilterValue, + 60, + 9, + 0, + 0, // Skip to: 15898 + /* 15889 */ MCD_OPC_CheckPredicate, + 41, + 171, + 3, + 0, // Skip to: 16833 + /* 15894 */ MCD_OPC_Decode, + 231, + 85, + 110, // Opcode: VFWMACC_VF + /* 15898 */ MCD_OPC_FilterValue, + 61, + 9, + 0, + 0, // Skip to: 15912 + /* 15903 */ MCD_OPC_CheckPredicate, + 41, + 157, + 3, + 0, // Skip to: 16833 + /* 15908 */ MCD_OPC_Decode, + 237, + 85, + 110, // Opcode: VFWNMACC_VF + /* 15912 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 15926 + /* 15917 */ MCD_OPC_CheckPredicate, + 41, + 143, + 3, + 0, // Skip to: 16833 + /* 15922 */ MCD_OPC_Decode, + 233, + 85, + 110, // Opcode: VFWMSAC_VF + /* 15926 */ MCD_OPC_FilterValue, + 63, + 134, + 3, + 0, // Skip to: 16833 + /* 15931 */ MCD_OPC_CheckPredicate, + 41, + 129, + 3, + 0, // Skip to: 16833 + /* 15936 */ MCD_OPC_Decode, + 239, + 85, + 110, // Opcode: VFWNMSAC_VF + /* 15940 */ MCD_OPC_FilterValue, + 6, + 230, + 1, + 0, // Skip to: 16431 + /* 15945 */ MCD_OPC_ExtractField, + 26, + 6, // Inst{31-26} ... + /* 15948 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 15962 + /* 15953 */ MCD_OPC_CheckPredicate, + 5, + 107, + 3, + 0, // Skip to: 16833 + /* 15958 */ MCD_OPC_Decode, + 189, + 84, + 104, // Opcode: VAADDU_VX + /* 15962 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 15976 + /* 15967 */ MCD_OPC_CheckPredicate, + 5, + 93, + 3, + 0, // Skip to: 16833 + /* 15972 */ MCD_OPC_Decode, + 191, + 84, + 104, // Opcode: VAADD_VX + /* 15976 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 15990 + /* 15981 */ MCD_OPC_CheckPredicate, + 5, + 79, + 3, + 0, // Skip to: 16833 + /* 15986 */ MCD_OPC_Decode, + 146, + 85, + 104, // Opcode: VASUBU_VX + /* 15990 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 16004 + /* 15995 */ MCD_OPC_CheckPredicate, + 5, + 65, + 3, + 0, // Skip to: 16833 + /* 16000 */ MCD_OPC_Decode, + 148, + 85, + 104, // Opcode: VASUB_VX + /* 16004 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 16018 + /* 16009 */ MCD_OPC_CheckPredicate, + 5, + 51, + 3, + 0, // Skip to: 16833 + /* 16014 */ MCD_OPC_Decode, + 185, + 88, + 104, // Opcode: VSLIDE1UP_VX + /* 16018 */ MCD_OPC_FilterValue, + 15, + 9, + 0, + 0, // Skip to: 16032 + /* 16023 */ MCD_OPC_CheckPredicate, + 5, + 37, + 3, + 0, // Skip to: 16833 + /* 16028 */ MCD_OPC_Decode, + 184, + 88, + 104, // Opcode: VSLIDE1DOWN_VX + /* 16032 */ MCD_OPC_FilterValue, + 16, + 16, + 0, + 0, // Skip to: 16053 + /* 16037 */ MCD_OPC_CheckPredicate, + 5, + 23, + 3, + 0, // Skip to: 16833 + /* 16042 */ MCD_OPC_CheckField, + 20, + 6, + 32, + 16, + 3, + 0, // Skip to: 16833 + /* 16049 */ MCD_OPC_Decode, + 246, + 87, + 111, // Opcode: VMV_S_X + /* 16053 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 16067 + /* 16058 */ MCD_OPC_CheckPredicate, + 5, + 2, + 3, + 0, // Skip to: 16833 + /* 16063 */ MCD_OPC_Decode, + 152, + 85, + 104, // Opcode: VDIVU_VX + /* 16067 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 16081 + /* 16072 */ MCD_OPC_CheckPredicate, + 5, + 244, + 2, + 0, // Skip to: 16833 + /* 16077 */ MCD_OPC_Decode, + 154, + 85, + 104, // Opcode: VDIV_VX + /* 16081 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 16095 + /* 16086 */ MCD_OPC_CheckPredicate, + 5, + 230, + 2, + 0, // Skip to: 16833 + /* 16091 */ MCD_OPC_Decode, + 153, + 88, + 104, // Opcode: VREMU_VX + /* 16095 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 16109 + /* 16100 */ MCD_OPC_CheckPredicate, + 5, + 216, + 2, + 0, // Skip to: 16833 + /* 16105 */ MCD_OPC_Decode, + 155, + 88, + 104, // Opcode: VREM_VX + /* 16109 */ MCD_OPC_FilterValue, + 36, + 9, + 0, + 0, // Skip to: 16123 + /* 16114 */ MCD_OPC_CheckPredicate, + 5, + 202, + 2, + 0, // Skip to: 16833 + /* 16119 */ MCD_OPC_Decode, + 237, + 87, + 104, // Opcode: VMULHU_VX + /* 16123 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 16137 + /* 16128 */ MCD_OPC_CheckPredicate, + 5, + 188, + 2, + 0, // Skip to: 16833 + /* 16133 */ MCD_OPC_Decode, + 241, + 87, + 104, // Opcode: VMUL_VX + /* 16137 */ MCD_OPC_FilterValue, + 38, + 9, + 0, + 0, // Skip to: 16151 + /* 16142 */ MCD_OPC_CheckPredicate, + 5, + 174, + 2, + 0, // Skip to: 16833 + /* 16147 */ MCD_OPC_Decode, + 235, + 87, + 104, // Opcode: VMULHSU_VX + /* 16151 */ MCD_OPC_FilterValue, + 39, + 9, + 0, + 0, // Skip to: 16165 + /* 16156 */ MCD_OPC_CheckPredicate, + 5, + 160, + 2, + 0, // Skip to: 16833 + /* 16161 */ MCD_OPC_Decode, + 239, + 87, + 104, // Opcode: VMULH_VX + /* 16165 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 16179 + /* 16170 */ MCD_OPC_CheckPredicate, + 5, + 146, + 2, + 0, // Skip to: 16833 + /* 16175 */ MCD_OPC_Decode, + 179, + 87, + 34, // Opcode: VMADD_VX + /* 16179 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 16193 + /* 16184 */ MCD_OPC_CheckPredicate, + 5, + 132, + 2, + 0, // Skip to: 16833 + /* 16189 */ MCD_OPC_Decode, + 134, + 88, + 34, // Opcode: VNMSUB_VX + /* 16193 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 16207 + /* 16198 */ MCD_OPC_CheckPredicate, + 5, + 118, + 2, + 0, // Skip to: 16833 + /* 16203 */ MCD_OPC_Decode, + 171, + 87, + 34, // Opcode: VMACC_VX + /* 16207 */ MCD_OPC_FilterValue, + 47, + 9, + 0, + 0, // Skip to: 16221 + /* 16212 */ MCD_OPC_CheckPredicate, + 5, + 104, + 2, + 0, // Skip to: 16833 + /* 16217 */ MCD_OPC_Decode, + 132, + 88, + 34, // Opcode: VNMSAC_VX + /* 16221 */ MCD_OPC_FilterValue, + 48, + 9, + 0, + 0, // Skip to: 16235 + /* 16226 */ MCD_OPC_CheckPredicate, + 5, + 90, + 2, + 0, // Skip to: 16833 + /* 16231 */ MCD_OPC_Decode, + 211, + 89, + 104, // Opcode: VWADDU_VX + /* 16235 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 16249 + /* 16240 */ MCD_OPC_CheckPredicate, + 5, + 76, + 2, + 0, // Skip to: 16833 + /* 16245 */ MCD_OPC_Decode, + 215, + 89, + 104, // Opcode: VWADD_VX + /* 16249 */ MCD_OPC_FilterValue, + 50, + 9, + 0, + 0, // Skip to: 16263 + /* 16254 */ MCD_OPC_CheckPredicate, + 5, + 62, + 2, + 0, // Skip to: 16833 + /* 16259 */ MCD_OPC_Decode, + 234, + 89, + 104, // Opcode: VWSUBU_VX + /* 16263 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 16277 + /* 16268 */ MCD_OPC_CheckPredicate, + 5, + 48, + 2, + 0, // Skip to: 16833 + /* 16273 */ MCD_OPC_Decode, + 238, + 89, + 104, // Opcode: VWSUB_VX + /* 16277 */ MCD_OPC_FilterValue, + 52, + 9, + 0, + 0, // Skip to: 16291 + /* 16282 */ MCD_OPC_CheckPredicate, + 5, + 34, + 2, + 0, // Skip to: 16833 + /* 16287 */ MCD_OPC_Decode, + 213, + 89, + 104, // Opcode: VWADDU_WX + /* 16291 */ MCD_OPC_FilterValue, + 53, + 9, + 0, + 0, // Skip to: 16305 + /* 16296 */ MCD_OPC_CheckPredicate, + 5, + 20, + 2, + 0, // Skip to: 16833 + /* 16301 */ MCD_OPC_Decode, + 217, + 89, + 104, // Opcode: VWADD_WX + /* 16305 */ MCD_OPC_FilterValue, + 54, + 9, + 0, + 0, // Skip to: 16319 + /* 16310 */ MCD_OPC_CheckPredicate, + 5, + 6, + 2, + 0, // Skip to: 16833 + /* 16315 */ MCD_OPC_Decode, + 236, + 89, + 104, // Opcode: VWSUBU_WX + /* 16319 */ MCD_OPC_FilterValue, + 55, + 9, + 0, + 0, // Skip to: 16333 + /* 16324 */ MCD_OPC_CheckPredicate, + 5, + 248, + 1, + 0, // Skip to: 16833 + /* 16329 */ MCD_OPC_Decode, + 240, + 89, + 104, // Opcode: VWSUB_WX + /* 16333 */ MCD_OPC_FilterValue, + 56, + 9, + 0, + 0, // Skip to: 16347 + /* 16338 */ MCD_OPC_CheckPredicate, + 5, + 234, + 1, + 0, // Skip to: 16833 + /* 16343 */ MCD_OPC_Decode, + 228, + 89, + 104, // Opcode: VWMULU_VX + /* 16347 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 16361 + /* 16352 */ MCD_OPC_CheckPredicate, + 5, + 220, + 1, + 0, // Skip to: 16833 + /* 16357 */ MCD_OPC_Decode, + 226, + 89, + 104, // Opcode: VWMULSU_VX + /* 16361 */ MCD_OPC_FilterValue, + 59, + 9, + 0, + 0, // Skip to: 16375 + /* 16366 */ MCD_OPC_CheckPredicate, + 5, + 206, + 1, + 0, // Skip to: 16833 + /* 16371 */ MCD_OPC_Decode, + 230, + 89, + 104, // Opcode: VWMUL_VX + /* 16375 */ MCD_OPC_FilterValue, + 60, + 9, + 0, + 0, // Skip to: 16389 + /* 16380 */ MCD_OPC_CheckPredicate, + 5, + 192, + 1, + 0, // Skip to: 16833 + /* 16385 */ MCD_OPC_Decode, + 222, + 89, + 34, // Opcode: VWMACCU_VX + /* 16389 */ MCD_OPC_FilterValue, + 61, + 9, + 0, + 0, // Skip to: 16403 + /* 16394 */ MCD_OPC_CheckPredicate, + 5, + 178, + 1, + 0, // Skip to: 16833 + /* 16399 */ MCD_OPC_Decode, + 224, + 89, + 34, // Opcode: VWMACC_VX + /* 16403 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 16417 + /* 16408 */ MCD_OPC_CheckPredicate, + 5, + 164, + 1, + 0, // Skip to: 16833 + /* 16413 */ MCD_OPC_Decode, + 220, + 89, + 34, // Opcode: VWMACCUS_VX + /* 16417 */ MCD_OPC_FilterValue, + 63, + 155, + 1, + 0, // Skip to: 16833 + /* 16422 */ MCD_OPC_CheckPredicate, + 5, + 150, + 1, + 0, // Skip to: 16833 + /* 16427 */ MCD_OPC_Decode, + 219, + 89, + 34, // Opcode: VWMACCSU_VX + /* 16431 */ MCD_OPC_FilterValue, + 7, + 141, + 1, + 0, // Skip to: 16833 + /* 16436 */ MCD_OPC_ExtractField, + 31, + 1, // Inst{31} ... + /* 16439 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 16453 + /* 16444 */ MCD_OPC_CheckPredicate, + 5, + 128, + 1, + 0, // Skip to: 16833 + /* 16449 */ MCD_OPC_Decode, + 180, + 88, + 112, // Opcode: VSETVLI + /* 16453 */ MCD_OPC_FilterValue, + 1, + 119, + 1, + 0, // Skip to: 16833 + /* 16458 */ MCD_OPC_ExtractField, + 30, + 1, // Inst{30} ... + /* 16461 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 16482 + /* 16466 */ MCD_OPC_CheckPredicate, + 5, + 106, + 1, + 0, // Skip to: 16833 + /* 16471 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 99, + 1, + 0, // Skip to: 16833 + /* 16478 */ MCD_OPC_Decode, + 179, + 88, + 55, // Opcode: VSETVL + /* 16482 */ MCD_OPC_FilterValue, + 1, + 90, + 1, + 0, // Skip to: 16833 + /* 16487 */ MCD_OPC_CheckPredicate, + 5, + 85, + 1, + 0, // Skip to: 16833 + /* 16492 */ MCD_OPC_Decode, + 178, + 88, + 113, // Opcode: VSETIVLI + /* 16496 */ MCD_OPC_FilterValue, + 99, + 57, + 0, + 0, // Skip to: 16558 + /* 16501 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 16504 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 16513 + /* 16509 */ MCD_OPC_Decode, + 249, + 81, + 114, // Opcode: BEQ + /* 16513 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 16522 + /* 16518 */ MCD_OPC_Decode, + 135, + 82, + 114, // Opcode: BNE + /* 16522 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 16531 + /* 16527 */ MCD_OPC_Decode, + 130, + 82, + 114, // Opcode: BLT + /* 16531 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 16540 + /* 16536 */ MCD_OPC_Decode, + 254, + 81, + 114, // Opcode: BGE + /* 16540 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 16549 + /* 16545 */ MCD_OPC_Decode, + 131, + 82, + 114, // Opcode: BLTU + /* 16549 */ MCD_OPC_FilterValue, + 7, + 23, + 1, + 0, // Skip to: 16833 + /* 16554 */ MCD_OPC_Decode, + 255, + 81, + 114, // Opcode: BGEU + /* 16558 */ MCD_OPC_FilterValue, + 103, + 11, + 0, + 0, // Skip to: 16574 + /* 16563 */ MCD_OPC_CheckField, + 12, + 3, + 0, + 7, + 1, + 0, // Skip to: 16833 + /* 16570 */ MCD_OPC_Decode, + 219, + 83, + 31, // Opcode: JALR + /* 16574 */ MCD_OPC_FilterValue, + 111, + 4, + 0, + 0, // Skip to: 16583 + /* 16579 */ MCD_OPC_Decode, + 218, + 83, + 115, // Opcode: JAL + /* 16583 */ MCD_OPC_FilterValue, + 115, + 245, + 0, + 0, // Skip to: 16833 + /* 16588 */ MCD_OPC_ExtractField, + 12, + 3, // Inst{14-12} ... + /* 16591 */ MCD_OPC_FilterValue, + 0, + 163, + 0, + 0, // Skip to: 16759 + /* 16596 */ MCD_OPC_ExtractField, + 25, + 7, // Inst{31-25} ... + /* 16599 */ MCD_OPC_FilterValue, + 0, + 51, + 0, + 0, // Skip to: 16655 + /* 16604 */ MCD_OPC_ExtractField, + 15, + 10, // Inst{24-15} ... + /* 16607 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 16623 + /* 16612 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 214, + 0, + 0, // Skip to: 16833 + /* 16619 */ MCD_OPC_Decode, + 224, + 82, + 0, // Opcode: ECALL + /* 16623 */ MCD_OPC_FilterValue, + 32, + 11, + 0, + 0, // Skip to: 16639 + /* 16628 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 198, + 0, + 0, // Skip to: 16833 + /* 16635 */ MCD_OPC_Decode, + 223, + 82, + 0, // Opcode: EBREAK + /* 16639 */ MCD_OPC_FilterValue, + 64, + 189, + 0, + 0, // Skip to: 16833 + /* 16644 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 182, + 0, + 0, // Skip to: 16833 + /* 16651 */ MCD_OPC_Decode, + 187, + 84, + 0, // Opcode: URET + /* 16655 */ MCD_OPC_FilterValue, + 8, + 36, + 0, + 0, // Skip to: 16696 + /* 16660 */ MCD_OPC_ExtractField, + 15, + 10, // Inst{24-15} ... + /* 16663 */ MCD_OPC_FilterValue, + 64, + 11, + 0, + 0, // Skip to: 16679 + /* 16668 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 158, + 0, + 0, // Skip to: 16833 + /* 16675 */ MCD_OPC_Decode, + 175, + 84, + 0, // Opcode: SRET + /* 16679 */ MCD_OPC_FilterValue, + 160, + 1, + 148, + 0, + 0, // Skip to: 16833 + /* 16685 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 141, + 0, + 0, // Skip to: 16833 + /* 16692 */ MCD_OPC_Decode, + 247, + 89, + 0, // Opcode: WFI + /* 16696 */ MCD_OPC_FilterValue, + 9, + 11, + 0, + 0, // Skip to: 16712 + /* 16701 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 125, + 0, + 0, // Skip to: 16833 + /* 16708 */ MCD_OPC_Decode, + 151, + 84, + 116, // Opcode: SFENCE_VMA + /* 16712 */ MCD_OPC_FilterValue, + 24, + 18, + 0, + 0, // Skip to: 16735 + /* 16717 */ MCD_OPC_CheckField, + 15, + 10, + 64, + 109, + 0, + 0, // Skip to: 16833 + /* 16724 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 102, + 0, + 0, // Skip to: 16833 + /* 16731 */ MCD_OPC_Decode, + 240, + 83, + 0, // Opcode: MRET + /* 16735 */ MCD_OPC_FilterValue, + 61, + 93, + 0, + 0, // Skip to: 16833 + /* 16740 */ MCD_OPC_CheckField, + 15, + 10, + 192, + 4, + 85, + 0, + 0, // Skip to: 16833 + /* 16748 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 78, + 0, + 0, // Skip to: 16833 + /* 16755 */ MCD_OPC_Decode, + 222, + 82, + 0, // Opcode: DRET + /* 16759 */ MCD_OPC_FilterValue, + 1, + 24, + 0, + 0, // Skip to: 16788 + /* 16764 */ MCD_OPC_CheckField, + 15, + 17, + 128, + 128, + 6, + 11, + 0, + 0, // Skip to: 16784 + /* 16773 */ MCD_OPC_CheckField, + 7, + 5, + 0, + 4, + 0, + 0, // Skip to: 16784 + /* 16780 */ MCD_OPC_Decode, + 183, + 84, + 0, // Opcode: UNIMP + /* 16784 */ MCD_OPC_Decode, + 159, + 82, + 117, // Opcode: CSRRW + /* 16788 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 16797 + /* 16793 */ MCD_OPC_Decode, + 157, + 82, + 117, // Opcode: CSRRS + /* 16797 */ MCD_OPC_FilterValue, + 3, + 4, + 0, + 0, // Skip to: 16806 + /* 16802 */ MCD_OPC_Decode, + 155, + 82, + 117, // Opcode: CSRRC + /* 16806 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 16815 + /* 16811 */ MCD_OPC_Decode, + 160, + 82, + 118, // Opcode: CSRRWI + /* 16815 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 16824 + /* 16820 */ MCD_OPC_Decode, + 158, + 82, + 118, // Opcode: CSRRSI + /* 16824 */ MCD_OPC_FilterValue, + 7, + 4, + 0, + 0, // Skip to: 16833 + /* 16829 */ MCD_OPC_Decode, + 156, + 82, + 118, // Opcode: CSRRCI + /* 16833 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTableRISCV32Only_16[] = { -/* 0 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 3 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 39 -/* 8 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 11 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25 -/* 16 */ MCD_OPC_CheckPredicate, 12, 75, 0, 0, // Skip to: 96 -/* 21 */ MCD_OPC_Decode, 154, 2, 61, // Opcode: C_FLW -/* 25 */ MCD_OPC_FilterValue, 7, 66, 0, 0, // Skip to: 96 -/* 30 */ MCD_OPC_CheckPredicate, 12, 61, 0, 0, // Skip to: 96 -/* 35 */ MCD_OPC_Decode, 158, 2, 61, // Opcode: C_FSW -/* 39 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 60 -/* 44 */ MCD_OPC_CheckPredicate, 13, 47, 0, 0, // Skip to: 96 -/* 49 */ MCD_OPC_CheckField, 13, 3, 1, 40, 0, 0, // Skip to: 96 -/* 56 */ MCD_OPC_Decode, 161, 2, 19, // Opcode: C_JAL -/* 60 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 96 -/* 65 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 68 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 82 -/* 73 */ MCD_OPC_CheckPredicate, 12, 18, 0, 0, // Skip to: 96 -/* 78 */ MCD_OPC_Decode, 155, 2, 62, // Opcode: C_FLWSP -/* 82 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 96 -/* 87 */ MCD_OPC_CheckPredicate, 12, 4, 0, 0, // Skip to: 96 -/* 92 */ MCD_OPC_Decode, 159, 2, 63, // Opcode: C_FSWSP -/* 96 */ MCD_OPC_Fail, - 0 -}; - -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ + /* 0 */ MCD_OPC_ExtractField, + 0, + 2, // Inst{1-0} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 39 + /* 8 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 11 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 25 + /* 16 */ MCD_OPC_CheckPredicate, + 42, + 75, + 0, + 0, // Skip to: 96 + /* 21 */ MCD_OPC_Decode, + 180, + 82, + 119, // Opcode: C_FLW + /* 25 */ MCD_OPC_FilterValue, + 7, + 66, + 0, + 0, // Skip to: 96 + /* 30 */ MCD_OPC_CheckPredicate, + 42, + 61, + 0, + 0, // Skip to: 96 + /* 35 */ MCD_OPC_Decode, + 184, + 82, + 119, // Opcode: C_FSW + /* 39 */ MCD_OPC_FilterValue, + 1, + 16, + 0, + 0, // Skip to: 60 + /* 44 */ MCD_OPC_CheckPredicate, + 43, + 47, + 0, + 0, // Skip to: 96 + /* 49 */ MCD_OPC_CheckField, + 13, + 3, + 1, + 40, + 0, + 0, // Skip to: 96 + /* 56 */ MCD_OPC_Decode, + 187, + 82, + 26, // Opcode: C_JAL + /* 60 */ MCD_OPC_FilterValue, + 2, + 31, + 0, + 0, // Skip to: 96 + /* 65 */ MCD_OPC_ExtractField, + 13, + 3, // Inst{15-13} ... + /* 68 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 82 + /* 73 */ MCD_OPC_CheckPredicate, + 42, + 18, + 0, + 0, // Skip to: 96 + /* 78 */ MCD_OPC_Decode, + 181, + 82, + 120, // Opcode: C_FLWSP + /* 82 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 96 + /* 87 */ MCD_OPC_CheckPredicate, + 42, + 4, + 0, + 0, // Skip to: 96 + /* 92 */ MCD_OPC_Decode, + 185, + 82, + 121, // Opcode: C_FSWSP + /* 96 */ MCD_OPC_Fail, + 0}; + +static bool getbool(uint64_t b) { return b != 0; } +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { - default: CS_ASSERT(0 && "Invalid index!"); + default: + llvm_unreachable("Invalid index!"); case 0: - return (Bits & RISCV_FeatureStdExtC); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtC, 1)); case 1: - return (Bits & RISCV_FeatureStdExtC) && (Bits & RISCV_FeatureStdExtD); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtC, 1) && + checkFeatureRequired(Bits, RISCV_FeatureNoRVCHints, 0)); case 2: - return (Bits & RISCV_FeatureStdExtC) && (Bits & RISCV_Feature64Bit); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtC, 1) && + checkFeatureRequired(Bits, RISCV_FeatureStdExtD, 1)); case 3: - return (Bits & RISCV_Feature64Bit); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtC, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); case 4: - return (Bits & RISCV_FeatureStdExtF); + return getbool(checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); case 5: - return (Bits & RISCV_FeatureStdExtD); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtV, 1)); case 6: - return (Bits & RISCV_FeatureStdExtA); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZvlsseg, 1)); case 7: - return (Bits & RISCV_FeatureStdExtA) && (Bits & RISCV_Feature64Bit); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZfhmin, 1)); case 8: - return (Bits & RISCV_FeatureStdExtM); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtF, 1)); case 9: - return (Bits & RISCV_FeatureStdExtM) && (Bits & RISCV_Feature64Bit); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtD, 1)); case 10: - return (Bits & RISCV_FeatureStdExtF) && (Bits & RISCV_Feature64Bit); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbp, 1)); case 11: - return (Bits & RISCV_FeatureStdExtD) && (Bits & RISCV_Feature64Bit); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbs, 1)); case 12: - return (Bits & RISCV_FeatureStdExtC) && (Bits & RISCV_FeatureStdExtF) && !(Bits & RISCV_Feature64Bit); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbb, 1)); case 13: - return (Bits & RISCV_FeatureStdExtC) && !(Bits & RISCV_Feature64Bit); + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbm, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 14: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbr, 1)); + case 15: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbr, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 16: + return getbool((checkFeatureRequired(Bits, RISCV_FeatureStdExtZbb, 1) || + checkFeatureRequired(Bits, RISCV_FeatureStdExtZbp, 1))); + case 17: + return getbool((checkFeatureRequired(Bits, RISCV_FeatureStdExtZbb, 1) || + checkFeatureRequired(Bits, RISCV_FeatureStdExtZbp, 1)) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 0)); + case 18: + return getbool((checkFeatureRequired(Bits, RISCV_FeatureStdExtZbb, 1) || + checkFeatureRequired(Bits, RISCV_FeatureStdExtZbp, 1)) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 19: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbt, 1)); + case 20: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZba, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 21: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbb, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 22: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbp, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 23: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbt, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 24: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZvamo, 1) && + checkFeatureRequired(Bits, RISCV_FeatureStdExtA, 1)); + case 25: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtA, 1)); + case 26: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtA, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 27: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZvamo, 1) && + checkFeatureRequired(Bits, RISCV_FeatureStdExtA, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 28: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtM, 1)); + case 29: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbc, 1)); + case 30: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZba, 1)); + case 31: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbe, 1)); + case 32: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbf, 1)); + case 33: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtM, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 34: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbe, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 35: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZbf, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 36: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZfh, 1)); + case 37: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZfhmin, 1) && + checkFeatureRequired(Bits, RISCV_FeatureStdExtD, 1)); + case 38: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtF, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 39: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtD, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 40: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtZfh, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 1)); + case 41: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtV, 1) && + checkFeatureRequired(Bits, RISCV_FeatureStdExtF, 1)); + case 42: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtC, 1) && + checkFeatureRequired(Bits, RISCV_FeatureStdExtF, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 0)); + case 43: + return getbool(checkFeatureRequired(Bits, RISCV_FeatureStdExtC, 1) && + checkFeatureRequired(Bits, RISCV_Feature64Bit, 0)); } } -#define DecodeToMCInst(fname, fieldname, InsnType) \ -static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, const void *Decoder,\ - bool *DecodeComplete) {\ - *DecodeComplete = true;\ - InsnType tmp; \ - switch (Idx) { \ - default: CS_ASSERT(0 && "Invalid index!");\ - case 0: \ - return S; \ - case 1: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 1) << 3; \ - tmp |= fieldname(insn, 6, 1) << 2; \ - tmp |= fieldname(insn, 7, 4) << 6; \ - tmp |= fieldname(insn, 11, 2) << 4; \ - if (decodeUImmNonZeroOperand(MI, tmp, Address, Decoder, 10) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 2: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 3: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 4: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeFPR64CRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 2) << 6; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 5: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 3) << 6; \ - tmp |= fieldname(insn, 5, 2) << 3; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 6: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 1) << 6; \ - tmp |= fieldname(insn, 6, 1) << 2; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 7: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 8: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 2) << 6; \ - tmp |= fieldname(insn, 4, 3) << 2; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 9: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 2) << 6; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 10: \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 3, 2) << 7; \ - tmp |= fieldname(insn, 5, 1) << 6; \ - tmp |= fieldname(insn, 6, 1) << 4; \ - tmp |= fieldname(insn, 12, 1) << 9; \ - if (decodeSImmNonZeroOperand(MI, tmp, Address, Decoder, 10) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 11: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0X2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeCLUIImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 12: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 3) << 6; \ - tmp |= fieldname(insn, 5, 2) << 3; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 13: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 14: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 15: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 16: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 17: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 18: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 19: \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 4; \ - tmp |= fieldname(insn, 3, 3) << 0; \ - tmp |= fieldname(insn, 6, 1) << 6; \ - tmp |= fieldname(insn, 7, 1) << 5; \ - tmp |= fieldname(insn, 8, 1) << 9; \ - tmp |= fieldname(insn, 9, 2) << 7; \ - tmp |= fieldname(insn, 11, 1) << 3; \ - tmp |= fieldname(insn, 12, 1) << 10; \ - if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 20: \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 3) << 6; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 21: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 4; \ - tmp |= fieldname(insn, 3, 2) << 0; \ - tmp |= fieldname(insn, 5, 2) << 5; \ - tmp |= fieldname(insn, 10, 2) << 2; \ - tmp |= fieldname(insn, 12, 1) << 7; \ - if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 22: \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 2) << 6; \ - tmp |= fieldname(insn, 9, 4) << 2; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 23: \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 3) << 6; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 24: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 25: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 26: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 27: \ - tmp = fieldname(insn, 24, 4); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 28: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 6); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 29: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 20); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 20) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 30: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 31: \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 5) << 0; \ - tmp |= fieldname(insn, 25, 7) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 32: \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 5) << 0; \ - tmp |= fieldname(insn, 25, 7) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 33: \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 5) << 0; \ - tmp |= fieldname(insn, 25, 7) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 34: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 35: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 36: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 27, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 37: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 27, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 38: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 39: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 40: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 41: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 42: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 43: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 44: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 45: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 46: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 47: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 48: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 49: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 50: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 51: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 52: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 53: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 54: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 55: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 56: \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 10; \ - tmp |= fieldname(insn, 8, 4) << 0; \ - tmp |= fieldname(insn, 25, 6) << 4; \ - tmp |= fieldname(insn, 31, 1) << 11; \ - if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 13) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 57: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 8) << 11; \ - tmp |= fieldname(insn, 20, 1) << 10; \ - tmp |= fieldname(insn, 21, 10) << 0; \ - tmp |= fieldname(insn, 31, 1) << 19; \ - if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 21) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 58: \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 59: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 60: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 61: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeFPR32CRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 1) << 6; \ - tmp |= fieldname(insn, 6, 1) << 2; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 62: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 2) << 6; \ - tmp |= fieldname(insn, 4, 3) << 2; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 63: \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 2) << 6; \ - tmp |= fieldname(insn, 9, 4) << 2; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - } \ -} +#define DecodeToMCInst(fname, fieldname, InsnType) \ + static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, \ + MCInst *MI, uint64_t Address, bool *Decoder) { \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + llvm_unreachable("Invalid index!"); \ + case 0: \ + return S; \ + case 1: \ + tmp = fieldname(insn, 2, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 3; \ + tmp |= fieldname(insn, 6, 1) << 2; \ + tmp |= fieldname(insn, 7, 4) << 6; \ + tmp |= fieldname(insn, 11, 2) << 4; \ + if (decodeUImmNonZeroOperand(MI, tmp, Address, Decoder, 10) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 2: \ + if (decodeRVCInstrSImm(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 3: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 5) << 0; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 5: \ + if (decodeRVCInstrRdRs1UImm(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 6: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 5) << 0; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 7: \ + tmp = fieldname(insn, 2, 3); \ + if (DecodeFPR64CRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 6; \ + tmp |= fieldname(insn, 10, 3) << 3; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 8: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 3) << 6; \ + tmp |= fieldname(insn, 5, 2) << 3; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 9: \ + tmp = fieldname(insn, 2, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 6; \ + tmp |= fieldname(insn, 6, 1) << 2; \ + tmp |= fieldname(insn, 10, 3) << 3; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 10: \ + if (decodeRVCInstrRdSImm(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 11: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 5) << 0; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 12: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 2) << 6; \ + tmp |= fieldname(insn, 4, 3) << 2; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 13: \ + tmp = fieldname(insn, 2, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 2) << 6; \ + tmp |= fieldname(insn, 10, 3) << 3; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 14: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 1) << 5; \ + tmp |= fieldname(insn, 3, 2) << 7; \ + tmp |= fieldname(insn, 5, 1) << 6; \ + tmp |= fieldname(insn, 6, 1) << 4; \ + tmp |= fieldname(insn, 12, 1) << 9; \ + if (decodeSImmNonZeroOperand(MI, tmp, Address, Decoder, 10) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 15: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0X2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 5) << 0; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeCLUIImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 16: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 3) << 6; \ + tmp |= fieldname(insn, 5, 2) << 3; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 5) << 0; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 5) << 0; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 2, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 21: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 22: \ + if (decodeRVCInstrRdRs2(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 2, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 24: \ + if (decodeRVCInstrRdRs1Rs2(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 2, 5); \ + if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 26: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 1) << 4; \ + tmp |= fieldname(insn, 3, 3) << 0; \ + tmp |= fieldname(insn, 6, 1) << 6; \ + tmp |= fieldname(insn, 7, 1) << 5; \ + tmp |= fieldname(insn, 8, 1) << 9; \ + tmp |= fieldname(insn, 9, 2) << 7; \ + tmp |= fieldname(insn, 11, 1) << 3; \ + tmp |= fieldname(insn, 12, 1) << 10; \ + if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 27: \ + tmp = fieldname(insn, 2, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 3) << 6; \ + tmp |= fieldname(insn, 10, 3) << 3; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 1) << 4; \ + tmp |= fieldname(insn, 3, 2) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 10, 2) << 2; \ + tmp |= fieldname(insn, 12, 1) << 7; \ + if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 9) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 2, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 2) << 6; \ + tmp |= fieldname(insn, 9, 4) << 2; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 2, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 3) << 6; \ + tmp |= fieldname(insn, 10, 3) << 3; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 31: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 34: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 35: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRM2RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 37: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRM4RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRM8RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 41: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 42: \ + tmp = fieldname(insn, 24, 4); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 4) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 6); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 45: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 46: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 27, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 6); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 47: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 20); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 20) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 48: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 27, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 49: \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 25, 7) << 5; \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 50: \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 25, 7) << 5; \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 51: \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 25, 7) << 5; \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 52: \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 25, 7) << 5; \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 53: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 55: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 27, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 57: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 27, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 58: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 27, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 59: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 27, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 60: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 61: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 62: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 64: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 65: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 66: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 68: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 69: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 70: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 72: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 73: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 74: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 75: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 76: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 77: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 78: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 79: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 80: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 82: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 83: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 84: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 3); \ + if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 85: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 86: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 87: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 88: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 89: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR16RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 90: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 91: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 92: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 93: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 94: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 95: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 96: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 97: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 98: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 99: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 100: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 101: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 102: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 103: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 104: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 105: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 106: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 107: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 108: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 109: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 110: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 1); \ + if (decodeVMaskReg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 111: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeVRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 112: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 11); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 11) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 113: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 10); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 11) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 114: \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 1) << 10; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 25, 6) << 4; \ + tmp |= fieldname(insn, 31, 1) << 11; \ + if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 13) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 115: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 12, 8) << 11; \ + tmp |= fieldname(insn, 20, 1) << 10; \ + tmp |= fieldname(insn, 21, 10) << 0; \ + tmp |= fieldname(insn, 31, 1) << 19; \ + if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 21) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 116: \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 117: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 118: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 15, 5); \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 119: \ + tmp = fieldname(insn, 2, 3); \ + if (DecodeFPR32CRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 7, 3); \ + if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 5, 1) << 6; \ + tmp |= fieldname(insn, 6, 1) << 2; \ + tmp |= fieldname(insn, 10, 3) << 3; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 120: \ + tmp = fieldname(insn, 7, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 2, 2) << 6; \ + tmp |= fieldname(insn, 4, 3) << 2; \ + tmp |= fieldname(insn, 12, 1) << 5; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 121: \ + tmp = fieldname(insn, 2, 5); \ + if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 7, 2) << 6; \ + tmp |= fieldname(insn, 9, 4) << 2; \ + if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + } \ + } -#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI,\ - InsnType insn, uint64_t Address,\ - const void *DisAsm, int feature) {\ - uint64_t Bits = getFeatureBits(feature);\ -\ - const uint8_t *Ptr = DecodeTable;\ - uint32_t CurFieldValue = 0;\ - DecodeStatus S = MCDisassembler_Success;\ - while (true) {\ - switch (*Ptr) {\ - default:\ - return MCDisassembler_Fail;\ - case MCD_OPC_ExtractField: {\ - unsigned Start = *++Ptr;\ - unsigned Len = *++Ptr;\ - ++Ptr;\ - CurFieldValue = fieldname(insn, Start, Len);\ - break;\ - }\ - case MCD_OPC_FilterValue: {\ - unsigned Len;\ - InsnType Val = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned NumToSkip = *Ptr++;\ - NumToSkip |= (*Ptr++) << 8;\ - NumToSkip |= (*Ptr++) << 16;\ -\ - if (Val != CurFieldValue)\ - Ptr += NumToSkip;\ - break;\ - }\ - case MCD_OPC_CheckField: {\ - unsigned Start = *++Ptr;\ - unsigned Len = *++Ptr;\ - InsnType FieldValue = fieldname(insn, Start, Len);\ - uint32_t ExpectedValue = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned NumToSkip = *Ptr++;\ - NumToSkip |= (*Ptr++) << 8;\ - NumToSkip |= (*Ptr++) << 16;\ -\ - if (ExpectedValue != FieldValue)\ - Ptr += NumToSkip;\ - break;\ - }\ - case MCD_OPC_CheckPredicate: {\ - unsigned Len;\ - unsigned PIdx = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned NumToSkip = *Ptr++;\ - NumToSkip |= (*Ptr++) << 8;\ - NumToSkip |= (*Ptr++) << 16;\ - bool Pred;\ - if (!(Pred = checkDecoderPredicate(PIdx, Bits)))\ - Ptr += NumToSkip;\ - (void)Pred;\ - break;\ - }\ - case MCD_OPC_Decode: {\ - unsigned Len;\ - unsigned Opc = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned DecodeIdx = decodeULEB128(Ptr, &Len);\ - Ptr += Len;\ -\ - MCInst_clear(MI);\ - MCInst_setOpcode(MI, Opc);\ - bool DecodeComplete;\ - S = decoder(S, DecodeIdx, insn, MI, Address, DisAsm, &DecodeComplete);\ - CS_ASSERT(DecodeComplete);\ -\ - return S;\ - }\ - case MCD_OPC_TryDecode: {\ - unsigned Len;\ - unsigned Opc = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned DecodeIdx = decodeULEB128(Ptr, &Len);\ - Ptr += Len;\ - unsigned NumToSkip = *Ptr++;\ - NumToSkip |= (*Ptr++) << 8;\ - NumToSkip |= (*Ptr++) << 16;\ -\ - MCInst TmpMI;\ - MCInst_setOpcode(&TmpMI, Opc);\ - bool DecodeComplete;\ - S = decoder(S, DecodeIdx, insn, &TmpMI, Address, DisAsm, &DecodeComplete);\ -\ - if (DecodeComplete) {\ - *MI = TmpMI;\ - return S;\ - } else {\ - CS_ASSERT(S == MCDisassembler_Fail);\ - Ptr += NumToSkip;\ - S = MCDisassembler_Success;\ - }\ - break;\ - }\ - case MCD_OPC_SoftFail: {\ - unsigned Len;\ - InsnType PositiveMask = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - InsnType NegativeMask = decodeULEB128(Ptr, &Len);\ - Ptr += Len;\ - bool Fail = (insn & PositiveMask) || (~insn & NegativeMask);\ - if (Fail)\ - S = MCDisassembler_SoftFail;\ - break;\ - }\ - case MCD_OPC_Fail: {\ - return MCDisassembler_Fail;\ - }\ - }\ - }\ - CS_ASSERT(0 && "bogosity detected in disassembler state machine!");\ -} +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ + static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + MCRegisterInfo *MRI, int feature) { \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, feature))) \ + Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could \ + * be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ + } -// For RISCV instruction is 32 bits. FieldFromInstruction(fieldFromInstruction, uint32_t) -DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) -DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) + DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) + DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) + +#endif // MIPS_GET_DISASSEMBLER +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +#define RISCV_FCSR 1 +#define RISCV_FFLAGS 2 +#define RISCV_FRM 3 +#define RISCV_VL 4 +#define RISCV_VTYPE 5 +#define RISCV_VXRM 6 +#define RISCV_VXSAT 7 +#define RISCV_V0 8 +#define RISCV_V1 9 +#define RISCV_V2 10 +#define RISCV_V3 11 +#define RISCV_V4 12 +#define RISCV_V5 13 +#define RISCV_V6 14 +#define RISCV_V7 15 +#define RISCV_V8 16 +#define RISCV_V9 17 +#define RISCV_V10 18 +#define RISCV_V11 19 +#define RISCV_V12 20 +#define RISCV_V13 21 +#define RISCV_V14 22 +#define RISCV_V15 23 +#define RISCV_V16 24 +#define RISCV_V17 25 +#define RISCV_V18 26 +#define RISCV_V19 27 +#define RISCV_V20 28 +#define RISCV_V21 29 +#define RISCV_V22 30 +#define RISCV_V23 31 +#define RISCV_V24 32 +#define RISCV_V25 33 +#define RISCV_V26 34 +#define RISCV_V27 35 +#define RISCV_V28 36 +#define RISCV_V29 37 +#define RISCV_V30 38 +#define RISCV_V31 39 +#define RISCV_X0 40 +#define RISCV_X1 41 +#define RISCV_X2 42 +#define RISCV_X3 43 +#define RISCV_X4 44 +#define RISCV_X5 45 +#define RISCV_X6 46 +#define RISCV_X7 47 +#define RISCV_X8 48 +#define RISCV_X9 49 +#define RISCV_X10 50 +#define RISCV_X11 51 +#define RISCV_X12 52 +#define RISCV_X13 53 +#define RISCV_X14 54 +#define RISCV_X15 55 +#define RISCV_X16 56 +#define RISCV_X17 57 +#define RISCV_X18 58 +#define RISCV_X19 59 +#define RISCV_X20 60 +#define RISCV_X21 61 +#define RISCV_X22 62 +#define RISCV_X23 63 +#define RISCV_X24 64 +#define RISCV_X25 65 +#define RISCV_X26 66 +#define RISCV_X27 67 +#define RISCV_X28 68 +#define RISCV_X29 69 +#define RISCV_X30 70 +#define RISCV_X31 71 +#define RISCV_F0_D 72 +#define RISCV_F1_D 73 +#define RISCV_F2_D 74 +#define RISCV_F3_D 75 +#define RISCV_F4_D 76 +#define RISCV_F5_D 77 +#define RISCV_F6_D 78 +#define RISCV_F7_D 79 +#define RISCV_F8_D 80 +#define RISCV_F9_D 81 +#define RISCV_F10_D 82 +#define RISCV_F11_D 83 +#define RISCV_F12_D 84 +#define RISCV_F13_D 85 +#define RISCV_F14_D 86 +#define RISCV_F15_D 87 +#define RISCV_F16_D 88 +#define RISCV_F17_D 89 +#define RISCV_F18_D 90 +#define RISCV_F19_D 91 +#define RISCV_F20_D 92 +#define RISCV_F21_D 93 +#define RISCV_F22_D 94 +#define RISCV_F23_D 95 +#define RISCV_F24_D 96 +#define RISCV_F25_D 97 +#define RISCV_F26_D 98 +#define RISCV_F27_D 99 +#define RISCV_F28_D 100 +#define RISCV_F29_D 101 +#define RISCV_F30_D 102 +#define RISCV_F31_D 103 +#define RISCV_F0_F 104 +#define RISCV_F1_F 105 +#define RISCV_F2_F 106 +#define RISCV_F3_F 107 +#define RISCV_F4_F 108 +#define RISCV_F5_F 109 +#define RISCV_F6_F 110 +#define RISCV_F7_F 111 +#define RISCV_F8_F 112 +#define RISCV_F9_F 113 +#define RISCV_F10_F 114 +#define RISCV_F11_F 115 +#define RISCV_F12_F 116 +#define RISCV_F13_F 117 +#define RISCV_F14_F 118 +#define RISCV_F15_F 119 +#define RISCV_F16_F 120 +#define RISCV_F17_F 121 +#define RISCV_F18_F 122 +#define RISCV_F19_F 123 +#define RISCV_F20_F 124 +#define RISCV_F21_F 125 +#define RISCV_F22_F 126 +#define RISCV_F23_F 127 +#define RISCV_F24_F 128 +#define RISCV_F25_F 129 +#define RISCV_F26_F 130 +#define RISCV_F27_F 131 +#define RISCV_F28_F 132 +#define RISCV_F29_F 133 +#define RISCV_F30_F 134 +#define RISCV_F31_F 135 +#define RISCV_F0_H 136 +#define RISCV_F1_H 137 +#define RISCV_F2_H 138 +#define RISCV_F3_H 139 +#define RISCV_F4_H 140 +#define RISCV_F5_H 141 +#define RISCV_F6_H 142 +#define RISCV_F7_H 143 +#define RISCV_F8_H 144 +#define RISCV_F9_H 145 +#define RISCV_F10_H 146 +#define RISCV_F11_H 147 +#define RISCV_F12_H 148 +#define RISCV_F13_H 149 +#define RISCV_F14_H 150 +#define RISCV_F15_H 151 +#define RISCV_F16_H 152 +#define RISCV_F17_H 153 +#define RISCV_F18_H 154 +#define RISCV_F19_H 155 +#define RISCV_F20_H 156 +#define RISCV_F21_H 157 +#define RISCV_F22_H 158 +#define RISCV_F23_H 159 +#define RISCV_F24_H 160 +#define RISCV_F25_H 161 +#define RISCV_F26_H 162 +#define RISCV_F27_H 163 +#define RISCV_F28_H 164 +#define RISCV_F29_H 165 +#define RISCV_F30_H 166 +#define RISCV_F31_H 167 +#define RISCV_V0M2 168 +#define RISCV_V0M4 169 +#define RISCV_V0M8 170 +#define RISCV_V2M2 171 +#define RISCV_V4M2 172 +#define RISCV_V4M4 173 +#define RISCV_V6M2 174 +#define RISCV_V8M2 175 +#define RISCV_V8M4 176 +#define RISCV_V8M8 177 +#define RISCV_V10M2 178 +#define RISCV_V12M2 179 +#define RISCV_V12M4 180 +#define RISCV_V14M2 181 +#define RISCV_V16M2 182 +#define RISCV_V16M4 183 +#define RISCV_V16M8 184 +#define RISCV_V18M2 185 +#define RISCV_V20M2 186 +#define RISCV_V20M4 187 +#define RISCV_V22M2 188 +#define RISCV_V24M2 189 +#define RISCV_V24M4 190 +#define RISCV_V24M8 191 +#define RISCV_V26M2 192 +#define RISCV_V28M2 193 +#define RISCV_V28M4 194 +#define RISCV_V30M2 195 +#define RISCV_V1_V2 196 +#define RISCV_V2_V3 197 +#define RISCV_V3_V4 198 +#define RISCV_V4_V5 199 +#define RISCV_V5_V6 200 +#define RISCV_V6_V7 201 +#define RISCV_V7_V8 202 +#define RISCV_V8_V9 203 +#define RISCV_V9_V10 204 +#define RISCV_V10_V11 205 +#define RISCV_V11_V12 206 +#define RISCV_V12_V13 207 +#define RISCV_V13_V14 208 +#define RISCV_V14_V15 209 +#define RISCV_V15_V16 210 +#define RISCV_V16_V17 211 +#define RISCV_V17_V18 212 +#define RISCV_V18_V19 213 +#define RISCV_V19_V20 214 +#define RISCV_V20_V21 215 +#define RISCV_V21_V22 216 +#define RISCV_V22_V23 217 +#define RISCV_V23_V24 218 +#define RISCV_V24_V25 219 +#define RISCV_V25_V26 220 +#define RISCV_V26_V27 221 +#define RISCV_V27_V28 222 +#define RISCV_V28_V29 223 +#define RISCV_V29_V30 224 +#define RISCV_V30_V31 225 +#define RISCV_V0_V1 226 +#define RISCV_V2M2_V4M2 227 +#define RISCV_V4M2_V6M2 228 +#define RISCV_V6M2_V8M2 229 +#define RISCV_V8M2_V10M2 230 +#define RISCV_V10M2_V12M2 231 +#define RISCV_V12M2_V14M2 232 +#define RISCV_V14M2_V16M2 233 +#define RISCV_V16M2_V18M2 234 +#define RISCV_V18M2_V20M2 235 +#define RISCV_V20M2_V22M2 236 +#define RISCV_V22M2_V24M2 237 +#define RISCV_V24M2_V26M2 238 +#define RISCV_V26M2_V28M2 239 +#define RISCV_V28M2_V30M2 240 +#define RISCV_V0M2_V2M2 241 +#define RISCV_V4M4_V8M4 242 +#define RISCV_V8M4_V12M4 243 +#define RISCV_V12M4_V16M4 244 +#define RISCV_V16M4_V20M4 245 +#define RISCV_V20M4_V24M4 246 +#define RISCV_V24M4_V28M4 247 +#define RISCV_V0M4_V4M4 248 +#define RISCV_V1_V2_V3 249 +#define RISCV_V2_V3_V4 250 +#define RISCV_V3_V4_V5 251 +#define RISCV_V4_V5_V6 252 +#define RISCV_V5_V6_V7 253 +#define RISCV_V6_V7_V8 254 +#define RISCV_V7_V8_V9 255 +#define RISCV_V8_V9_V10 256 +#define RISCV_V9_V10_V11 257 +#define RISCV_V10_V11_V12 258 +#define RISCV_V11_V12_V13 259 +#define RISCV_V12_V13_V14 260 +#define RISCV_V13_V14_V15 261 +#define RISCV_V14_V15_V16 262 +#define RISCV_V15_V16_V17 263 +#define RISCV_V16_V17_V18 264 +#define RISCV_V17_V18_V19 265 +#define RISCV_V18_V19_V20 266 +#define RISCV_V19_V20_V21 267 +#define RISCV_V20_V21_V22 268 +#define RISCV_V21_V22_V23 269 +#define RISCV_V22_V23_V24 270 +#define RISCV_V23_V24_V25 271 +#define RISCV_V24_V25_V26 272 +#define RISCV_V25_V26_V27 273 +#define RISCV_V26_V27_V28 274 +#define RISCV_V27_V28_V29 275 +#define RISCV_V28_V29_V30 276 +#define RISCV_V29_V30_V31 277 +#define RISCV_V0_V1_V2 278 +#define RISCV_V2M2_V4M2_V6M2 279 +#define RISCV_V4M2_V6M2_V8M2 280 +#define RISCV_V6M2_V8M2_V10M2 281 +#define RISCV_V8M2_V10M2_V12M2 282 +#define RISCV_V10M2_V12M2_V14M2 283 +#define RISCV_V12M2_V14M2_V16M2 284 +#define RISCV_V14M2_V16M2_V18M2 285 +#define RISCV_V16M2_V18M2_V20M2 286 +#define RISCV_V18M2_V20M2_V22M2 287 +#define RISCV_V20M2_V22M2_V24M2 288 +#define RISCV_V22M2_V24M2_V26M2 289 +#define RISCV_V24M2_V26M2_V28M2 290 +#define RISCV_V26M2_V28M2_V30M2 291 +#define RISCV_V0M2_V2M2_V4M2 292 +#define RISCV_V1_V2_V3_V4 293 +#define RISCV_V2_V3_V4_V5 294 +#define RISCV_V3_V4_V5_V6 295 +#define RISCV_V4_V5_V6_V7 296 +#define RISCV_V5_V6_V7_V8 297 +#define RISCV_V6_V7_V8_V9 298 +#define RISCV_V7_V8_V9_V10 299 +#define RISCV_V8_V9_V10_V11 300 +#define RISCV_V9_V10_V11_V12 301 +#define RISCV_V10_V11_V12_V13 302 +#define RISCV_V11_V12_V13_V14 303 +#define RISCV_V12_V13_V14_V15 304 +#define RISCV_V13_V14_V15_V16 305 +#define RISCV_V14_V15_V16_V17 306 +#define RISCV_V15_V16_V17_V18 307 +#define RISCV_V16_V17_V18_V19 308 +#define RISCV_V17_V18_V19_V20 309 +#define RISCV_V18_V19_V20_V21 310 +#define RISCV_V19_V20_V21_V22 311 +#define RISCV_V20_V21_V22_V23 312 +#define RISCV_V21_V22_V23_V24 313 +#define RISCV_V22_V23_V24_V25 314 +#define RISCV_V23_V24_V25_V26 315 +#define RISCV_V24_V25_V26_V27 316 +#define RISCV_V25_V26_V27_V28 317 +#define RISCV_V26_V27_V28_V29 318 +#define RISCV_V27_V28_V29_V30 319 +#define RISCV_V28_V29_V30_V31 320 +#define RISCV_V0_V1_V2_V3 321 +#define RISCV_V2M2_V4M2_V6M2_V8M2 322 +#define RISCV_V4M2_V6M2_V8M2_V10M2 323 +#define RISCV_V6M2_V8M2_V10M2_V12M2 324 +#define RISCV_V8M2_V10M2_V12M2_V14M2 325 +#define RISCV_V10M2_V12M2_V14M2_V16M2 326 +#define RISCV_V12M2_V14M2_V16M2_V18M2 327 +#define RISCV_V14M2_V16M2_V18M2_V20M2 328 +#define RISCV_V16M2_V18M2_V20M2_V22M2 329 +#define RISCV_V18M2_V20M2_V22M2_V24M2 330 +#define RISCV_V20M2_V22M2_V24M2_V26M2 331 +#define RISCV_V22M2_V24M2_V26M2_V28M2 332 +#define RISCV_V24M2_V26M2_V28M2_V30M2 333 +#define RISCV_V0M2_V2M2_V4M2_V6M2 334 +#define RISCV_V1_V2_V3_V4_V5 335 +#define RISCV_V2_V3_V4_V5_V6 336 +#define RISCV_V3_V4_V5_V6_V7 337 +#define RISCV_V4_V5_V6_V7_V8 338 +#define RISCV_V5_V6_V7_V8_V9 339 +#define RISCV_V6_V7_V8_V9_V10 340 +#define RISCV_V7_V8_V9_V10_V11 341 +#define RISCV_V8_V9_V10_V11_V12 342 +#define RISCV_V9_V10_V11_V12_V13 343 +#define RISCV_V10_V11_V12_V13_V14 344 +#define RISCV_V11_V12_V13_V14_V15 345 +#define RISCV_V12_V13_V14_V15_V16 346 +#define RISCV_V13_V14_V15_V16_V17 347 +#define RISCV_V14_V15_V16_V17_V18 348 +#define RISCV_V15_V16_V17_V18_V19 349 +#define RISCV_V16_V17_V18_V19_V20 350 +#define RISCV_V17_V18_V19_V20_V21 351 +#define RISCV_V18_V19_V20_V21_V22 352 +#define RISCV_V19_V20_V21_V22_V23 353 +#define RISCV_V20_V21_V22_V23_V24 354 +#define RISCV_V21_V22_V23_V24_V25 355 +#define RISCV_V22_V23_V24_V25_V26 356 +#define RISCV_V23_V24_V25_V26_V27 357 +#define RISCV_V24_V25_V26_V27_V28 358 +#define RISCV_V25_V26_V27_V28_V29 359 +#define RISCV_V26_V27_V28_V29_V30 360 +#define RISCV_V27_V28_V29_V30_V31 361 +#define RISCV_V0_V1_V2_V3_V4 362 +#define RISCV_V1_V2_V3_V4_V5_V6 363 +#define RISCV_V2_V3_V4_V5_V6_V7 364 +#define RISCV_V3_V4_V5_V6_V7_V8 365 +#define RISCV_V4_V5_V6_V7_V8_V9 366 +#define RISCV_V5_V6_V7_V8_V9_V10 367 +#define RISCV_V6_V7_V8_V9_V10_V11 368 +#define RISCV_V7_V8_V9_V10_V11_V12 369 +#define RISCV_V8_V9_V10_V11_V12_V13 370 +#define RISCV_V9_V10_V11_V12_V13_V14 371 +#define RISCV_V10_V11_V12_V13_V14_V15 372 +#define RISCV_V11_V12_V13_V14_V15_V16 373 +#define RISCV_V12_V13_V14_V15_V16_V17 374 +#define RISCV_V13_V14_V15_V16_V17_V18 375 +#define RISCV_V14_V15_V16_V17_V18_V19 376 +#define RISCV_V15_V16_V17_V18_V19_V20 377 +#define RISCV_V16_V17_V18_V19_V20_V21 378 +#define RISCV_V17_V18_V19_V20_V21_V22 379 +#define RISCV_V18_V19_V20_V21_V22_V23 380 +#define RISCV_V19_V20_V21_V22_V23_V24 381 +#define RISCV_V20_V21_V22_V23_V24_V25 382 +#define RISCV_V21_V22_V23_V24_V25_V26 383 +#define RISCV_V22_V23_V24_V25_V26_V27 384 +#define RISCV_V23_V24_V25_V26_V27_V28 385 +#define RISCV_V24_V25_V26_V27_V28_V29 386 +#define RISCV_V25_V26_V27_V28_V29_V30 387 +#define RISCV_V26_V27_V28_V29_V30_V31 388 +#define RISCV_V0_V1_V2_V3_V4_V5 389 +#define RISCV_V1_V2_V3_V4_V5_V6_V7 390 +#define RISCV_V2_V3_V4_V5_V6_V7_V8 391 +#define RISCV_V3_V4_V5_V6_V7_V8_V9 392 +#define RISCV_V4_V5_V6_V7_V8_V9_V10 393 +#define RISCV_V5_V6_V7_V8_V9_V10_V11 394 +#define RISCV_V6_V7_V8_V9_V10_V11_V12 395 +#define RISCV_V7_V8_V9_V10_V11_V12_V13 396 +#define RISCV_V8_V9_V10_V11_V12_V13_V14 397 +#define RISCV_V9_V10_V11_V12_V13_V14_V15 398 +#define RISCV_V10_V11_V12_V13_V14_V15_V16 399 +#define RISCV_V11_V12_V13_V14_V15_V16_V17 400 +#define RISCV_V12_V13_V14_V15_V16_V17_V18 401 +#define RISCV_V13_V14_V15_V16_V17_V18_V19 402 +#define RISCV_V14_V15_V16_V17_V18_V19_V20 403 +#define RISCV_V15_V16_V17_V18_V19_V20_V21 404 +#define RISCV_V16_V17_V18_V19_V20_V21_V22 405 +#define RISCV_V17_V18_V19_V20_V21_V22_V23 406 +#define RISCV_V18_V19_V20_V21_V22_V23_V24 407 +#define RISCV_V19_V20_V21_V22_V23_V24_V25 408 +#define RISCV_V20_V21_V22_V23_V24_V25_V26 409 +#define RISCV_V21_V22_V23_V24_V25_V26_V27 410 +#define RISCV_V22_V23_V24_V25_V26_V27_V28 411 +#define RISCV_V23_V24_V25_V26_V27_V28_V29 412 +#define RISCV_V24_V25_V26_V27_V28_V29_V30 413 +#define RISCV_V25_V26_V27_V28_V29_V30_V31 414 +#define RISCV_V0_V1_V2_V3_V4_V5_V6 415 +#define RISCV_V1_V2_V3_V4_V5_V6_V7_V8 416 +#define RISCV_V2_V3_V4_V5_V6_V7_V8_V9 417 +#define RISCV_V3_V4_V5_V6_V7_V8_V9_V10 418 +#define RISCV_V4_V5_V6_V7_V8_V9_V10_V11 419 +#define RISCV_V5_V6_V7_V8_V9_V10_V11_V12 420 +#define RISCV_V6_V7_V8_V9_V10_V11_V12_V13 421 +#define RISCV_V7_V8_V9_V10_V11_V12_V13_V14 422 +#define RISCV_V8_V9_V10_V11_V12_V13_V14_V15 423 +#define RISCV_V9_V10_V11_V12_V13_V14_V15_V16 424 +#define RISCV_V10_V11_V12_V13_V14_V15_V16_V17 425 +#define RISCV_V11_V12_V13_V14_V15_V16_V17_V18 426 +#define RISCV_V12_V13_V14_V15_V16_V17_V18_V19 427 +#define RISCV_V13_V14_V15_V16_V17_V18_V19_V20 428 +#define RISCV_V14_V15_V16_V17_V18_V19_V20_V21 429 +#define RISCV_V15_V16_V17_V18_V19_V20_V21_V22 430 +#define RISCV_V16_V17_V18_V19_V20_V21_V22_V23 431 +#define RISCV_V17_V18_V19_V20_V21_V22_V23_V24 432 +#define RISCV_V18_V19_V20_V21_V22_V23_V24_V25 433 +#define RISCV_V19_V20_V21_V22_V23_V24_V25_V26 434 +#define RISCV_V20_V21_V22_V23_V24_V25_V26_V27 435 +#define RISCV_V21_V22_V23_V24_V25_V26_V27_V28 436 +#define RISCV_V22_V23_V24_V25_V26_V27_V28_V29 437 +#define RISCV_V23_V24_V25_V26_V27_V28_V29_V30 438 +#define RISCV_V24_V25_V26_V27_V28_V29_V30_V31 439 +#define RISCV_V0_V1_V2_V3_V4_V5_V6_V7 440 +#define RISCV_NUM_TARGET_REGS 441 + +// Register classes + +#define RISCV_FPR16RegClassID 0 +#define RISCV_AnyRegRegClassID 1 +#define RISCV_AnyReg_with_sub_16RegClassID 2 +#define RISCV_FPR32RegClassID 3 +#define RISCV_GPRRegClassID 4 +#define RISCV_GPRNoX0RegClassID 5 +#define RISCV_GPRNoX0X2RegClassID 6 +#define RISCV_GPRJALRRegClassID 7 +#define RISCV_GPRTCRegClassID 8 +#define RISCV_AnyReg_with_sub_16_with_sub_32_in_FPR32CRegClassID 9 +#define RISCV_FPR32CRegClassID 10 +#define RISCV_GPRCRegClassID 11 +#define RISCV_GPRC_and_GPRTCRegClassID 12 +#define RISCV_GPRX0RegClassID 13 +#define RISCV_SPRegClassID 14 +#define RISCV_FPR64RegClassID 15 +#define RISCV_VMRegClassID 16 +#define RISCV_VRRegClassID 17 +#define RISCV_VRNoV0RegClassID 18 +#define RISCV_FPR64CRegClassID 19 +#define RISCV_VMV0RegClassID 20 +#define RISCV_VRN2M1RegClassID 21 +#define RISCV_VRN2M1NoV0RegClassID 22 +#define RISCV_VRM2RegClassID 23 +#define RISCV_VRM2NoV0RegClassID 24 +#define RISCV_VRM2_with_sub_vrm1_0_in_VMV0RegClassID 25 +#define RISCV_VRN2M1_with_sub_vrm1_0_in_VMV0RegClassID 26 +#define RISCV_VRN3M1RegClassID 27 +#define RISCV_VRN3M1NoV0RegClassID 28 +#define RISCV_VRN3M1_with_sub_vrm1_0_in_VMV0RegClassID 29 +#define RISCV_VRN4M1RegClassID 30 +#define RISCV_VRN4M1NoV0RegClassID 31 +#define RISCV_VRN2M2RegClassID 32 +#define RISCV_VRN2M2NoV0RegClassID 33 +#define RISCV_VRM4RegClassID 34 +#define RISCV_VRM4NoV0RegClassID 35 +#define RISCV_VRM4_with_sub_vrm1_0_in_VMV0RegClassID 36 +#define RISCV_VRN2M2_with_sub_vrm1_0_in_VMV0RegClassID 37 +#define RISCV_VRN4M1_with_sub_vrm1_0_in_VMV0RegClassID 38 +#define RISCV_VRN5M1RegClassID 39 +#define RISCV_VRN5M1NoV0RegClassID 40 +#define RISCV_VRN5M1_with_sub_vrm1_0_in_VMV0RegClassID 41 +#define RISCV_VRN6M1RegClassID 42 +#define RISCV_VRN6M1NoV0RegClassID 43 +#define RISCV_VRN3M2RegClassID 44 +#define RISCV_VRN3M2NoV0RegClassID 45 +#define RISCV_VRN3M2_with_sub_vrm1_0_in_VMV0RegClassID 46 +#define RISCV_VRN6M1_with_sub_vrm1_0_in_VMV0RegClassID 47 +#define RISCV_VRN7M1RegClassID 48 +#define RISCV_VRN7M1NoV0RegClassID 49 +#define RISCV_VRN7M1_with_sub_vrm1_0_in_VMV0RegClassID 50 +#define RISCV_VRN8M1RegClassID 51 +#define RISCV_VRN8M1NoV0RegClassID 52 +#define RISCV_VRN4M2RegClassID 53 +#define RISCV_VRN4M2NoV0RegClassID 54 +#define RISCV_VRN2M4RegClassID 55 +#define RISCV_VRN2M4NoV0RegClassID 56 +#define RISCV_VRM8RegClassID 57 +#define RISCV_VRM8NoV0RegClassID 58 +#define RISCV_VRM8_with_sub_vrm1_0_in_VMV0RegClassID 59 +#define RISCV_VRN2M4_with_sub_vrm1_0_in_VMV0RegClassID 60 +#define RISCV_VRN4M2_with_sub_vrm1_0_in_VMV0RegClassID 61 +#define RISCV_VRN8M1_with_sub_vrm1_0_in_VMV0RegClassID 62 + +#endif // GET_REGINFO_ENUM + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +#define RISCV_PHI 0 +#define RISCV_INLINEASM 1 +#define RISCV_INLINEASM_BR 2 +#define RISCV_CFI_INSTRUCTION 3 +#define RISCV_EH_LABEL 4 +#define RISCV_GC_LABEL 5 +#define RISCV_ANNOTATION_LABEL 6 +#define RISCV_KILL 7 +#define RISCV_EXTRACT_SUBREG 8 +#define RISCV_INSERT_SUBREG 9 +#define RISCV_IMPLICIT_DEF 10 +#define RISCV_SUBREG_TO_REG 11 +#define RISCV_COPY_TO_REGCLASS 12 +#define RISCV_DBG_VALUE 13 +#define RISCV_DBG_VALUE_LIST 14 +#define RISCV_DBG_INSTR_REF 15 +#define RISCV_DBG_PHI 16 +#define RISCV_DBG_LABEL 17 +#define RISCV_REG_SEQUENCE 18 +#define RISCV_COPY 19 +#define RISCV_BUNDLE 20 +#define RISCV_LIFETIME_START 21 +#define RISCV_LIFETIME_END 22 +#define RISCV_PSEUDO_PROBE 23 +#define RISCV_ARITH_FENCE 24 +#define RISCV_STACKMAP 25 +#define RISCV_FENTRY_CALL 26 +#define RISCV_PATCHPOINT 27 +#define RISCV_LOAD_STACK_GUARD 28 +#define RISCV_PREALLOCATED_SETUP 29 +#define RISCV_PREALLOCATED_ARG 30 +#define RISCV_STATEPOINT 31 +#define RISCV_LOCAL_ESCAPE 32 +#define RISCV_FAULTING_OP 33 +#define RISCV_PATCHABLE_OP 34 +#define RISCV_PATCHABLE_FUNCTION_ENTER 35 +#define RISCV_PATCHABLE_RET 36 +#define RISCV_PATCHABLE_FUNCTION_EXIT 37 +#define RISCV_PATCHABLE_TAIL_CALL 38 +#define RISCV_PATCHABLE_EVENT_CALL 39 +#define RISCV_PATCHABLE_TYPED_EVENT_CALL 40 +#define RISCV_ICALL_BRANCH_FUNNEL 41 +#define RISCV_G_ASSERT_SEXT 42 +#define RISCV_G_ASSERT_ZEXT 43 +#define RISCV_G_ADD 44 +#define RISCV_G_SUB 45 +#define RISCV_G_MUL 46 +#define RISCV_G_SDIV 47 +#define RISCV_G_UDIV 48 +#define RISCV_G_SREM 49 +#define RISCV_G_UREM 50 +#define RISCV_G_SDIVREM 51 +#define RISCV_G_UDIVREM 52 +#define RISCV_G_AND 53 +#define RISCV_G_OR 54 +#define RISCV_G_XOR 55 +#define RISCV_G_IMPLICIT_DEF 56 +#define RISCV_G_PHI 57 +#define RISCV_G_FRAME_INDEX 58 +#define RISCV_G_GLOBAL_VALUE 59 +#define RISCV_G_EXTRACT 60 +#define RISCV_G_UNMERGE_VALUES 61 +#define RISCV_G_INSERT 62 +#define RISCV_G_MERGE_VALUES 63 +#define RISCV_G_BUILD_VECTOR 64 +#define RISCV_G_BUILD_VECTOR_TRUNC 65 +#define RISCV_G_CONCAT_VECTORS 66 +#define RISCV_G_PTRTOINT 67 +#define RISCV_G_INTTOPTR 68 +#define RISCV_G_BITCAST 69 +#define RISCV_G_FREEZE 70 +#define RISCV_G_INTRINSIC_TRUNC 71 +#define RISCV_G_INTRINSIC_ROUND 72 +#define RISCV_G_INTRINSIC_LRINT 73 +#define RISCV_G_INTRINSIC_ROUNDEVEN 74 +#define RISCV_G_READCYCLECOUNTER 75 +#define RISCV_G_LOAD 76 +#define RISCV_G_SEXTLOAD 77 +#define RISCV_G_ZEXTLOAD 78 +#define RISCV_G_INDEXED_LOAD 79 +#define RISCV_G_INDEXED_SEXTLOAD 80 +#define RISCV_G_INDEXED_ZEXTLOAD 81 +#define RISCV_G_STORE 82 +#define RISCV_G_INDEXED_STORE 83 +#define RISCV_G_ATOMIC_CMPXCHG_WITH_SUCCESS 84 +#define RISCV_G_ATOMIC_CMPXCHG 85 +#define RISCV_G_ATOMICRMW_XCHG 86 +#define RISCV_G_ATOMICRMW_ADD 87 +#define RISCV_G_ATOMICRMW_SUB 88 +#define RISCV_G_ATOMICRMW_AND 89 +#define RISCV_G_ATOMICRMW_NAND 90 +#define RISCV_G_ATOMICRMW_OR 91 +#define RISCV_G_ATOMICRMW_XOR 92 +#define RISCV_G_ATOMICRMW_MAX 93 +#define RISCV_G_ATOMICRMW_MIN 94 +#define RISCV_G_ATOMICRMW_UMAX 95 +#define RISCV_G_ATOMICRMW_UMIN 96 +#define RISCV_G_ATOMICRMW_FADD 97 +#define RISCV_G_ATOMICRMW_FSUB 98 +#define RISCV_G_FENCE 99 +#define RISCV_G_BRCOND 100 +#define RISCV_G_BRINDIRECT 101 +#define RISCV_G_INTRINSIC 102 +#define RISCV_G_INTRINSIC_W_SIDE_EFFECTS 103 +#define RISCV_G_ANYEXT 104 +#define RISCV_G_TRUNC 105 +#define RISCV_G_CONSTANT 106 +#define RISCV_G_FCONSTANT 107 +#define RISCV_G_VASTART 108 +#define RISCV_G_VAARG 109 +#define RISCV_G_SEXT 110 +#define RISCV_G_SEXT_INREG 111 +#define RISCV_G_ZEXT 112 +#define RISCV_G_SHL 113 +#define RISCV_G_LSHR 114 +#define RISCV_G_ASHR 115 +#define RISCV_G_FSHL 116 +#define RISCV_G_FSHR 117 +#define RISCV_G_ROTR 118 +#define RISCV_G_ROTL 119 +#define RISCV_G_ICMP 120 +#define RISCV_G_FCMP 121 +#define RISCV_G_SELECT 122 +#define RISCV_G_UADDO 123 +#define RISCV_G_UADDE 124 +#define RISCV_G_USUBO 125 +#define RISCV_G_USUBE 126 +#define RISCV_G_SADDO 127 +#define RISCV_G_SADDE 128 +#define RISCV_G_SSUBO 129 +#define RISCV_G_SSUBE 130 +#define RISCV_G_UMULO 131 +#define RISCV_G_SMULO 132 +#define RISCV_G_UMULH 133 +#define RISCV_G_SMULH 134 +#define RISCV_G_UADDSAT 135 +#define RISCV_G_SADDSAT 136 +#define RISCV_G_USUBSAT 137 +#define RISCV_G_SSUBSAT 138 +#define RISCV_G_USHLSAT 139 +#define RISCV_G_SSHLSAT 140 +#define RISCV_G_SMULFIX 141 +#define RISCV_G_UMULFIX 142 +#define RISCV_G_SMULFIXSAT 143 +#define RISCV_G_UMULFIXSAT 144 +#define RISCV_G_SDIVFIX 145 +#define RISCV_G_UDIVFIX 146 +#define RISCV_G_SDIVFIXSAT 147 +#define RISCV_G_UDIVFIXSAT 148 +#define RISCV_G_FADD 149 +#define RISCV_G_FSUB 150 +#define RISCV_G_FMUL 151 +#define RISCV_G_FMA 152 +#define RISCV_G_FMAD 153 +#define RISCV_G_FDIV 154 +#define RISCV_G_FREM 155 +#define RISCV_G_FPOW 156 +#define RISCV_G_FPOWI 157 +#define RISCV_G_FEXP 158 +#define RISCV_G_FEXP2 159 +#define RISCV_G_FLOG 160 +#define RISCV_G_FLOG2 161 +#define RISCV_G_FLOG10 162 +#define RISCV_G_FNEG 163 +#define RISCV_G_FPEXT 164 +#define RISCV_G_FPTRUNC 165 +#define RISCV_G_FPTOSI 166 +#define RISCV_G_FPTOUI 167 +#define RISCV_G_SITOFP 168 +#define RISCV_G_UITOFP 169 +#define RISCV_G_FABS 170 +#define RISCV_G_FCOPYSIGN 171 +#define RISCV_G_FCANONICALIZE 172 +#define RISCV_G_FMINNUM 173 +#define RISCV_G_FMAXNUM 174 +#define RISCV_G_FMINNUM_IEEE 175 +#define RISCV_G_FMAXNUM_IEEE 176 +#define RISCV_G_FMINIMUM 177 +#define RISCV_G_FMAXIMUM 178 +#define RISCV_G_PTR_ADD 179 +#define RISCV_G_PTRMASK 180 +#define RISCV_G_SMIN 181 +#define RISCV_G_SMAX 182 +#define RISCV_G_UMIN 183 +#define RISCV_G_UMAX 184 +#define RISCV_G_ABS 185 +#define RISCV_G_LROUND 186 +#define RISCV_G_LLROUND 187 +#define RISCV_G_BR 188 +#define RISCV_G_BRJT 189 +#define RISCV_G_INSERT_VECTOR_ELT 190 +#define RISCV_G_EXTRACT_VECTOR_ELT 191 +#define RISCV_G_SHUFFLE_VECTOR 192 +#define RISCV_G_CTTZ 193 +#define RISCV_G_CTTZ_ZERO_UNDEF 194 +#define RISCV_G_CTLZ 195 +#define RISCV_G_CTLZ_ZERO_UNDEF 196 +#define RISCV_G_CTPOP 197 +#define RISCV_G_BSWAP 198 +#define RISCV_G_BITREVERSE 199 +#define RISCV_G_FCEIL 200 +#define RISCV_G_FCOS 201 +#define RISCV_G_FSIN 202 +#define RISCV_G_FSQRT 203 +#define RISCV_G_FFLOOR 204 +#define RISCV_G_FRINT 205 +#define RISCV_G_FNEARBYINT 206 +#define RISCV_G_ADDRSPACE_CAST 207 +#define RISCV_G_BLOCK_ADDR 208 +#define RISCV_G_JUMP_TABLE 209 +#define RISCV_G_DYN_STACKALLOC 210 +#define RISCV_G_STRICT_FADD 211 +#define RISCV_G_STRICT_FSUB 212 +#define RISCV_G_STRICT_FMUL 213 +#define RISCV_G_STRICT_FDIV 214 +#define RISCV_G_STRICT_FREM 215 +#define RISCV_G_STRICT_FMA 216 +#define RISCV_G_STRICT_FSQRT 217 +#define RISCV_G_READ_REGISTER 218 +#define RISCV_G_WRITE_REGISTER 219 +#define RISCV_G_MEMCPY 220 +#define RISCV_G_MEMCPY_INLINE 221 +#define RISCV_G_MEMMOVE 222 +#define RISCV_G_MEMSET 223 +#define RISCV_G_BZERO 224 +#define RISCV_G_VECREDUCE_SEQ_FADD 225 +#define RISCV_G_VECREDUCE_SEQ_FMUL 226 +#define RISCV_G_VECREDUCE_FADD 227 +#define RISCV_G_VECREDUCE_FMUL 228 +#define RISCV_G_VECREDUCE_FMAX 229 +#define RISCV_G_VECREDUCE_FMIN 230 +#define RISCV_G_VECREDUCE_ADD 231 +#define RISCV_G_VECREDUCE_MUL 232 +#define RISCV_G_VECREDUCE_AND 233 +#define RISCV_G_VECREDUCE_OR 234 +#define RISCV_G_VECREDUCE_XOR 235 +#define RISCV_G_VECREDUCE_SMAX 236 +#define RISCV_G_VECREDUCE_SMIN 237 +#define RISCV_G_VECREDUCE_UMAX 238 +#define RISCV_G_VECREDUCE_UMIN 239 +#define RISCV_G_SBFX 240 +#define RISCV_G_UBFX 241 +#define RISCV_ADJCALLSTACKDOWN 242 +#define RISCV_ADJCALLSTACKUP 243 +#define RISCV_BuildPairF64Pseudo 244 +#define RISCV_PseudoAddTPRel 245 +#define RISCV_PseudoAtomicLoadNand32 246 +#define RISCV_PseudoAtomicLoadNand64 247 +#define RISCV_PseudoBR 248 +#define RISCV_PseudoBRIND 249 +#define RISCV_PseudoCALL 250 +#define RISCV_PseudoCALLIndirect 251 +#define RISCV_PseudoCALLReg 252 +#define RISCV_PseudoCmpXchg32 253 +#define RISCV_PseudoCmpXchg64 254 +#define RISCV_PseudoFLD 255 +#define RISCV_PseudoFLH 256 +#define RISCV_PseudoFLW 257 +#define RISCV_PseudoFSD 258 +#define RISCV_PseudoFSH 259 +#define RISCV_PseudoFSW 260 +#define RISCV_PseudoJump 261 +#define RISCV_PseudoLA 262 +#define RISCV_PseudoLA_TLS_GD 263 +#define RISCV_PseudoLA_TLS_IE 264 +#define RISCV_PseudoLB 265 +#define RISCV_PseudoLBU 266 +#define RISCV_PseudoLD 267 +#define RISCV_PseudoLH 268 +#define RISCV_PseudoLHU 269 +#define RISCV_PseudoLI 270 +#define RISCV_PseudoLLA 271 +#define RISCV_PseudoLW 272 +#define RISCV_PseudoLWU 273 +#define RISCV_PseudoMaskedAtomicLoadAdd32 274 +#define RISCV_PseudoMaskedAtomicLoadMax32 275 +#define RISCV_PseudoMaskedAtomicLoadMin32 276 +#define RISCV_PseudoMaskedAtomicLoadNand32 277 +#define RISCV_PseudoMaskedAtomicLoadSub32 278 +#define RISCV_PseudoMaskedAtomicLoadUMax32 279 +#define RISCV_PseudoMaskedAtomicLoadUMin32 280 +#define RISCV_PseudoMaskedAtomicSwap32 281 +#define RISCV_PseudoMaskedCmpXchg32 282 +#define RISCV_PseudoRET 283 +#define RISCV_PseudoReadVL 284 +#define RISCV_PseudoReadVLENB 285 +#define RISCV_PseudoSB 286 +#define RISCV_PseudoSD 287 +#define RISCV_PseudoSEXT_B 288 +#define RISCV_PseudoSEXT_H 289 +#define RISCV_PseudoSH 290 +#define RISCV_PseudoSW 291 +#define RISCV_PseudoTAIL 292 +#define RISCV_PseudoTAILIndirect 293 +#define RISCV_PseudoVAADDU_VV_M1 294 +#define RISCV_PseudoVAADDU_VV_M1_MASK 295 +#define RISCV_PseudoVAADDU_VV_M2 296 +#define RISCV_PseudoVAADDU_VV_M2_MASK 297 +#define RISCV_PseudoVAADDU_VV_M4 298 +#define RISCV_PseudoVAADDU_VV_M4_MASK 299 +#define RISCV_PseudoVAADDU_VV_M8 300 +#define RISCV_PseudoVAADDU_VV_M8_MASK 301 +#define RISCV_PseudoVAADDU_VV_MF2 302 +#define RISCV_PseudoVAADDU_VV_MF2_MASK 303 +#define RISCV_PseudoVAADDU_VV_MF4 304 +#define RISCV_PseudoVAADDU_VV_MF4_MASK 305 +#define RISCV_PseudoVAADDU_VV_MF8 306 +#define RISCV_PseudoVAADDU_VV_MF8_MASK 307 +#define RISCV_PseudoVAADDU_VX_M1 308 +#define RISCV_PseudoVAADDU_VX_M1_MASK 309 +#define RISCV_PseudoVAADDU_VX_M2 310 +#define RISCV_PseudoVAADDU_VX_M2_MASK 311 +#define RISCV_PseudoVAADDU_VX_M4 312 +#define RISCV_PseudoVAADDU_VX_M4_MASK 313 +#define RISCV_PseudoVAADDU_VX_M8 314 +#define RISCV_PseudoVAADDU_VX_M8_MASK 315 +#define RISCV_PseudoVAADDU_VX_MF2 316 +#define RISCV_PseudoVAADDU_VX_MF2_MASK 317 +#define RISCV_PseudoVAADDU_VX_MF4 318 +#define RISCV_PseudoVAADDU_VX_MF4_MASK 319 +#define RISCV_PseudoVAADDU_VX_MF8 320 +#define RISCV_PseudoVAADDU_VX_MF8_MASK 321 +#define RISCV_PseudoVAADD_VV_M1 322 +#define RISCV_PseudoVAADD_VV_M1_MASK 323 +#define RISCV_PseudoVAADD_VV_M2 324 +#define RISCV_PseudoVAADD_VV_M2_MASK 325 +#define RISCV_PseudoVAADD_VV_M4 326 +#define RISCV_PseudoVAADD_VV_M4_MASK 327 +#define RISCV_PseudoVAADD_VV_M8 328 +#define RISCV_PseudoVAADD_VV_M8_MASK 329 +#define RISCV_PseudoVAADD_VV_MF2 330 +#define RISCV_PseudoVAADD_VV_MF2_MASK 331 +#define RISCV_PseudoVAADD_VV_MF4 332 +#define RISCV_PseudoVAADD_VV_MF4_MASK 333 +#define RISCV_PseudoVAADD_VV_MF8 334 +#define RISCV_PseudoVAADD_VV_MF8_MASK 335 +#define RISCV_PseudoVAADD_VX_M1 336 +#define RISCV_PseudoVAADD_VX_M1_MASK 337 +#define RISCV_PseudoVAADD_VX_M2 338 +#define RISCV_PseudoVAADD_VX_M2_MASK 339 +#define RISCV_PseudoVAADD_VX_M4 340 +#define RISCV_PseudoVAADD_VX_M4_MASK 341 +#define RISCV_PseudoVAADD_VX_M8 342 +#define RISCV_PseudoVAADD_VX_M8_MASK 343 +#define RISCV_PseudoVAADD_VX_MF2 344 +#define RISCV_PseudoVAADD_VX_MF2_MASK 345 +#define RISCV_PseudoVAADD_VX_MF4 346 +#define RISCV_PseudoVAADD_VX_MF4_MASK 347 +#define RISCV_PseudoVAADD_VX_MF8 348 +#define RISCV_PseudoVAADD_VX_MF8_MASK 349 +#define RISCV_PseudoVADC_VIM_M1 350 +#define RISCV_PseudoVADC_VIM_M2 351 +#define RISCV_PseudoVADC_VIM_M4 352 +#define RISCV_PseudoVADC_VIM_M8 353 +#define RISCV_PseudoVADC_VIM_MF2 354 +#define RISCV_PseudoVADC_VIM_MF4 355 +#define RISCV_PseudoVADC_VIM_MF8 356 +#define RISCV_PseudoVADC_VVM_M1 357 +#define RISCV_PseudoVADC_VVM_M2 358 +#define RISCV_PseudoVADC_VVM_M4 359 +#define RISCV_PseudoVADC_VVM_M8 360 +#define RISCV_PseudoVADC_VVM_MF2 361 +#define RISCV_PseudoVADC_VVM_MF4 362 +#define RISCV_PseudoVADC_VVM_MF8 363 +#define RISCV_PseudoVADC_VXM_M1 364 +#define RISCV_PseudoVADC_VXM_M2 365 +#define RISCV_PseudoVADC_VXM_M4 366 +#define RISCV_PseudoVADC_VXM_M8 367 +#define RISCV_PseudoVADC_VXM_MF2 368 +#define RISCV_PseudoVADC_VXM_MF4 369 +#define RISCV_PseudoVADC_VXM_MF8 370 +#define RISCV_PseudoVADD_VI_M1 371 +#define RISCV_PseudoVADD_VI_M1_MASK 372 +#define RISCV_PseudoVADD_VI_M2 373 +#define RISCV_PseudoVADD_VI_M2_MASK 374 +#define RISCV_PseudoVADD_VI_M4 375 +#define RISCV_PseudoVADD_VI_M4_MASK 376 +#define RISCV_PseudoVADD_VI_M8 377 +#define RISCV_PseudoVADD_VI_M8_MASK 378 +#define RISCV_PseudoVADD_VI_MF2 379 +#define RISCV_PseudoVADD_VI_MF2_MASK 380 +#define RISCV_PseudoVADD_VI_MF4 381 +#define RISCV_PseudoVADD_VI_MF4_MASK 382 +#define RISCV_PseudoVADD_VI_MF8 383 +#define RISCV_PseudoVADD_VI_MF8_MASK 384 +#define RISCV_PseudoVADD_VV_M1 385 +#define RISCV_PseudoVADD_VV_M1_MASK 386 +#define RISCV_PseudoVADD_VV_M2 387 +#define RISCV_PseudoVADD_VV_M2_MASK 388 +#define RISCV_PseudoVADD_VV_M4 389 +#define RISCV_PseudoVADD_VV_M4_MASK 390 +#define RISCV_PseudoVADD_VV_M8 391 +#define RISCV_PseudoVADD_VV_M8_MASK 392 +#define RISCV_PseudoVADD_VV_MF2 393 +#define RISCV_PseudoVADD_VV_MF2_MASK 394 +#define RISCV_PseudoVADD_VV_MF4 395 +#define RISCV_PseudoVADD_VV_MF4_MASK 396 +#define RISCV_PseudoVADD_VV_MF8 397 +#define RISCV_PseudoVADD_VV_MF8_MASK 398 +#define RISCV_PseudoVADD_VX_M1 399 +#define RISCV_PseudoVADD_VX_M1_MASK 400 +#define RISCV_PseudoVADD_VX_M2 401 +#define RISCV_PseudoVADD_VX_M2_MASK 402 +#define RISCV_PseudoVADD_VX_M4 403 +#define RISCV_PseudoVADD_VX_M4_MASK 404 +#define RISCV_PseudoVADD_VX_M8 405 +#define RISCV_PseudoVADD_VX_M8_MASK 406 +#define RISCV_PseudoVADD_VX_MF2 407 +#define RISCV_PseudoVADD_VX_MF2_MASK 408 +#define RISCV_PseudoVADD_VX_MF4 409 +#define RISCV_PseudoVADD_VX_MF4_MASK 410 +#define RISCV_PseudoVADD_VX_MF8 411 +#define RISCV_PseudoVADD_VX_MF8_MASK 412 +#define RISCV_PseudoVAMOADDEI16_WD_M1_MF2 413 +#define RISCV_PseudoVAMOADDEI16_WD_M1_MF2_MASK 414 +#define RISCV_PseudoVAMOADDEI16_WD_M1_MF4 415 +#define RISCV_PseudoVAMOADDEI16_WD_M1_MF4_MASK 416 +#define RISCV_PseudoVAMOADDEI16_WD_M2_M1 417 +#define RISCV_PseudoVAMOADDEI16_WD_M2_M1_MASK 418 +#define RISCV_PseudoVAMOADDEI16_WD_M2_MF2 419 +#define RISCV_PseudoVAMOADDEI16_WD_M2_MF2_MASK 420 +#define RISCV_PseudoVAMOADDEI16_WD_M4_M1 421 +#define RISCV_PseudoVAMOADDEI16_WD_M4_M1_MASK 422 +#define RISCV_PseudoVAMOADDEI16_WD_M4_M2 423 +#define RISCV_PseudoVAMOADDEI16_WD_M4_M2_MASK 424 +#define RISCV_PseudoVAMOADDEI16_WD_M8_M2 425 +#define RISCV_PseudoVAMOADDEI16_WD_M8_M2_MASK 426 +#define RISCV_PseudoVAMOADDEI16_WD_M8_M4 427 +#define RISCV_PseudoVAMOADDEI16_WD_M8_M4_MASK 428 +#define RISCV_PseudoVAMOADDEI16_WD_MF2_MF4 429 +#define RISCV_PseudoVAMOADDEI16_WD_MF2_MF4_MASK 430 +#define RISCV_PseudoVAMOADDEI32_WD_M1_M1 431 +#define RISCV_PseudoVAMOADDEI32_WD_M1_M1_MASK 432 +#define RISCV_PseudoVAMOADDEI32_WD_M1_MF2 433 +#define RISCV_PseudoVAMOADDEI32_WD_M1_MF2_MASK 434 +#define RISCV_PseudoVAMOADDEI32_WD_M2_M1 435 +#define RISCV_PseudoVAMOADDEI32_WD_M2_M1_MASK 436 +#define RISCV_PseudoVAMOADDEI32_WD_M2_M2 437 +#define RISCV_PseudoVAMOADDEI32_WD_M2_M2_MASK 438 +#define RISCV_PseudoVAMOADDEI32_WD_M4_M2 439 +#define RISCV_PseudoVAMOADDEI32_WD_M4_M2_MASK 440 +#define RISCV_PseudoVAMOADDEI32_WD_M4_M4 441 +#define RISCV_PseudoVAMOADDEI32_WD_M4_M4_MASK 442 +#define RISCV_PseudoVAMOADDEI32_WD_M8_M4 443 +#define RISCV_PseudoVAMOADDEI32_WD_M8_M4_MASK 444 +#define RISCV_PseudoVAMOADDEI32_WD_M8_M8 445 +#define RISCV_PseudoVAMOADDEI32_WD_M8_M8_MASK 446 +#define RISCV_PseudoVAMOADDEI32_WD_MF2_MF2 447 +#define RISCV_PseudoVAMOADDEI32_WD_MF2_MF2_MASK 448 +#define RISCV_PseudoVAMOADDEI64_WD_M1_M1 449 +#define RISCV_PseudoVAMOADDEI64_WD_M1_M1_MASK 450 +#define RISCV_PseudoVAMOADDEI64_WD_M1_M2 451 +#define RISCV_PseudoVAMOADDEI64_WD_M1_M2_MASK 452 +#define RISCV_PseudoVAMOADDEI64_WD_M2_M2 453 +#define RISCV_PseudoVAMOADDEI64_WD_M2_M2_MASK 454 +#define RISCV_PseudoVAMOADDEI64_WD_M2_M4 455 +#define RISCV_PseudoVAMOADDEI64_WD_M2_M4_MASK 456 +#define RISCV_PseudoVAMOADDEI64_WD_M4_M4 457 +#define RISCV_PseudoVAMOADDEI64_WD_M4_M4_MASK 458 +#define RISCV_PseudoVAMOADDEI64_WD_M4_M8 459 +#define RISCV_PseudoVAMOADDEI64_WD_M4_M8_MASK 460 +#define RISCV_PseudoVAMOADDEI64_WD_M8_M8 461 +#define RISCV_PseudoVAMOADDEI64_WD_M8_M8_MASK 462 +#define RISCV_PseudoVAMOADDEI64_WD_MF2_M1 463 +#define RISCV_PseudoVAMOADDEI64_WD_MF2_M1_MASK 464 +#define RISCV_PseudoVAMOADDEI8_WD_M1_MF4 465 +#define RISCV_PseudoVAMOADDEI8_WD_M1_MF4_MASK 466 +#define RISCV_PseudoVAMOADDEI8_WD_M1_MF8 467 +#define RISCV_PseudoVAMOADDEI8_WD_M1_MF8_MASK 468 +#define RISCV_PseudoVAMOADDEI8_WD_M2_MF2 469 +#define RISCV_PseudoVAMOADDEI8_WD_M2_MF2_MASK 470 +#define RISCV_PseudoVAMOADDEI8_WD_M2_MF4 471 +#define RISCV_PseudoVAMOADDEI8_WD_M2_MF4_MASK 472 +#define RISCV_PseudoVAMOADDEI8_WD_M4_M1 473 +#define RISCV_PseudoVAMOADDEI8_WD_M4_M1_MASK 474 +#define RISCV_PseudoVAMOADDEI8_WD_M4_MF2 475 +#define RISCV_PseudoVAMOADDEI8_WD_M4_MF2_MASK 476 +#define RISCV_PseudoVAMOADDEI8_WD_M8_M1 477 +#define RISCV_PseudoVAMOADDEI8_WD_M8_M1_MASK 478 +#define RISCV_PseudoVAMOADDEI8_WD_M8_M2 479 +#define RISCV_PseudoVAMOADDEI8_WD_M8_M2_MASK 480 +#define RISCV_PseudoVAMOADDEI8_WD_MF2_MF8 481 +#define RISCV_PseudoVAMOADDEI8_WD_MF2_MF8_MASK 482 +#define RISCV_PseudoVAMOANDEI16_WD_M1_MF2 483 +#define RISCV_PseudoVAMOANDEI16_WD_M1_MF2_MASK 484 +#define RISCV_PseudoVAMOANDEI16_WD_M1_MF4 485 +#define RISCV_PseudoVAMOANDEI16_WD_M1_MF4_MASK 486 +#define RISCV_PseudoVAMOANDEI16_WD_M2_M1 487 +#define RISCV_PseudoVAMOANDEI16_WD_M2_M1_MASK 488 +#define RISCV_PseudoVAMOANDEI16_WD_M2_MF2 489 +#define RISCV_PseudoVAMOANDEI16_WD_M2_MF2_MASK 490 +#define RISCV_PseudoVAMOANDEI16_WD_M4_M1 491 +#define RISCV_PseudoVAMOANDEI16_WD_M4_M1_MASK 492 +#define RISCV_PseudoVAMOANDEI16_WD_M4_M2 493 +#define RISCV_PseudoVAMOANDEI16_WD_M4_M2_MASK 494 +#define RISCV_PseudoVAMOANDEI16_WD_M8_M2 495 +#define RISCV_PseudoVAMOANDEI16_WD_M8_M2_MASK 496 +#define RISCV_PseudoVAMOANDEI16_WD_M8_M4 497 +#define RISCV_PseudoVAMOANDEI16_WD_M8_M4_MASK 498 +#define RISCV_PseudoVAMOANDEI16_WD_MF2_MF4 499 +#define RISCV_PseudoVAMOANDEI16_WD_MF2_MF4_MASK 500 +#define RISCV_PseudoVAMOANDEI32_WD_M1_M1 501 +#define RISCV_PseudoVAMOANDEI32_WD_M1_M1_MASK 502 +#define RISCV_PseudoVAMOANDEI32_WD_M1_MF2 503 +#define RISCV_PseudoVAMOANDEI32_WD_M1_MF2_MASK 504 +#define RISCV_PseudoVAMOANDEI32_WD_M2_M1 505 +#define RISCV_PseudoVAMOANDEI32_WD_M2_M1_MASK 506 +#define RISCV_PseudoVAMOANDEI32_WD_M2_M2 507 +#define RISCV_PseudoVAMOANDEI32_WD_M2_M2_MASK 508 +#define RISCV_PseudoVAMOANDEI32_WD_M4_M2 509 +#define RISCV_PseudoVAMOANDEI32_WD_M4_M2_MASK 510 +#define RISCV_PseudoVAMOANDEI32_WD_M4_M4 511 +#define RISCV_PseudoVAMOANDEI32_WD_M4_M4_MASK 512 +#define RISCV_PseudoVAMOANDEI32_WD_M8_M4 513 +#define RISCV_PseudoVAMOANDEI32_WD_M8_M4_MASK 514 +#define RISCV_PseudoVAMOANDEI32_WD_M8_M8 515 +#define RISCV_PseudoVAMOANDEI32_WD_M8_M8_MASK 516 +#define RISCV_PseudoVAMOANDEI32_WD_MF2_MF2 517 +#define RISCV_PseudoVAMOANDEI32_WD_MF2_MF2_MASK 518 +#define RISCV_PseudoVAMOANDEI64_WD_M1_M1 519 +#define RISCV_PseudoVAMOANDEI64_WD_M1_M1_MASK 520 +#define RISCV_PseudoVAMOANDEI64_WD_M1_M2 521 +#define RISCV_PseudoVAMOANDEI64_WD_M1_M2_MASK 522 +#define RISCV_PseudoVAMOANDEI64_WD_M2_M2 523 +#define RISCV_PseudoVAMOANDEI64_WD_M2_M2_MASK 524 +#define RISCV_PseudoVAMOANDEI64_WD_M2_M4 525 +#define RISCV_PseudoVAMOANDEI64_WD_M2_M4_MASK 526 +#define RISCV_PseudoVAMOANDEI64_WD_M4_M4 527 +#define RISCV_PseudoVAMOANDEI64_WD_M4_M4_MASK 528 +#define RISCV_PseudoVAMOANDEI64_WD_M4_M8 529 +#define RISCV_PseudoVAMOANDEI64_WD_M4_M8_MASK 530 +#define RISCV_PseudoVAMOANDEI64_WD_M8_M8 531 +#define RISCV_PseudoVAMOANDEI64_WD_M8_M8_MASK 532 +#define RISCV_PseudoVAMOANDEI64_WD_MF2_M1 533 +#define RISCV_PseudoVAMOANDEI64_WD_MF2_M1_MASK 534 +#define RISCV_PseudoVAMOANDEI8_WD_M1_MF4 535 +#define RISCV_PseudoVAMOANDEI8_WD_M1_MF4_MASK 536 +#define RISCV_PseudoVAMOANDEI8_WD_M1_MF8 537 +#define RISCV_PseudoVAMOANDEI8_WD_M1_MF8_MASK 538 +#define RISCV_PseudoVAMOANDEI8_WD_M2_MF2 539 +#define RISCV_PseudoVAMOANDEI8_WD_M2_MF2_MASK 540 +#define RISCV_PseudoVAMOANDEI8_WD_M2_MF4 541 +#define RISCV_PseudoVAMOANDEI8_WD_M2_MF4_MASK 542 +#define RISCV_PseudoVAMOANDEI8_WD_M4_M1 543 +#define RISCV_PseudoVAMOANDEI8_WD_M4_M1_MASK 544 +#define RISCV_PseudoVAMOANDEI8_WD_M4_MF2 545 +#define RISCV_PseudoVAMOANDEI8_WD_M4_MF2_MASK 546 +#define RISCV_PseudoVAMOANDEI8_WD_M8_M1 547 +#define RISCV_PseudoVAMOANDEI8_WD_M8_M1_MASK 548 +#define RISCV_PseudoVAMOANDEI8_WD_M8_M2 549 +#define RISCV_PseudoVAMOANDEI8_WD_M8_M2_MASK 550 +#define RISCV_PseudoVAMOANDEI8_WD_MF2_MF8 551 +#define RISCV_PseudoVAMOANDEI8_WD_MF2_MF8_MASK 552 +#define RISCV_PseudoVAMOMAXEI16_WD_M1_MF2 553 +#define RISCV_PseudoVAMOMAXEI16_WD_M1_MF2_MASK 554 +#define RISCV_PseudoVAMOMAXEI16_WD_M1_MF4 555 +#define RISCV_PseudoVAMOMAXEI16_WD_M1_MF4_MASK 556 +#define RISCV_PseudoVAMOMAXEI16_WD_M2_M1 557 +#define RISCV_PseudoVAMOMAXEI16_WD_M2_M1_MASK 558 +#define RISCV_PseudoVAMOMAXEI16_WD_M2_MF2 559 +#define RISCV_PseudoVAMOMAXEI16_WD_M2_MF2_MASK 560 +#define RISCV_PseudoVAMOMAXEI16_WD_M4_M1 561 +#define RISCV_PseudoVAMOMAXEI16_WD_M4_M1_MASK 562 +#define RISCV_PseudoVAMOMAXEI16_WD_M4_M2 563 +#define RISCV_PseudoVAMOMAXEI16_WD_M4_M2_MASK 564 +#define RISCV_PseudoVAMOMAXEI16_WD_M8_M2 565 +#define RISCV_PseudoVAMOMAXEI16_WD_M8_M2_MASK 566 +#define RISCV_PseudoVAMOMAXEI16_WD_M8_M4 567 +#define RISCV_PseudoVAMOMAXEI16_WD_M8_M4_MASK 568 +#define RISCV_PseudoVAMOMAXEI16_WD_MF2_MF4 569 +#define RISCV_PseudoVAMOMAXEI16_WD_MF2_MF4_MASK 570 +#define RISCV_PseudoVAMOMAXEI32_WD_M1_M1 571 +#define RISCV_PseudoVAMOMAXEI32_WD_M1_M1_MASK 572 +#define RISCV_PseudoVAMOMAXEI32_WD_M1_MF2 573 +#define RISCV_PseudoVAMOMAXEI32_WD_M1_MF2_MASK 574 +#define RISCV_PseudoVAMOMAXEI32_WD_M2_M1 575 +#define RISCV_PseudoVAMOMAXEI32_WD_M2_M1_MASK 576 +#define RISCV_PseudoVAMOMAXEI32_WD_M2_M2 577 +#define RISCV_PseudoVAMOMAXEI32_WD_M2_M2_MASK 578 +#define RISCV_PseudoVAMOMAXEI32_WD_M4_M2 579 +#define RISCV_PseudoVAMOMAXEI32_WD_M4_M2_MASK 580 +#define RISCV_PseudoVAMOMAXEI32_WD_M4_M4 581 +#define RISCV_PseudoVAMOMAXEI32_WD_M4_M4_MASK 582 +#define RISCV_PseudoVAMOMAXEI32_WD_M8_M4 583 +#define RISCV_PseudoVAMOMAXEI32_WD_M8_M4_MASK 584 +#define RISCV_PseudoVAMOMAXEI32_WD_M8_M8 585 +#define RISCV_PseudoVAMOMAXEI32_WD_M8_M8_MASK 586 +#define RISCV_PseudoVAMOMAXEI32_WD_MF2_MF2 587 +#define RISCV_PseudoVAMOMAXEI32_WD_MF2_MF2_MASK 588 +#define RISCV_PseudoVAMOMAXEI64_WD_M1_M1 589 +#define RISCV_PseudoVAMOMAXEI64_WD_M1_M1_MASK 590 +#define RISCV_PseudoVAMOMAXEI64_WD_M1_M2 591 +#define RISCV_PseudoVAMOMAXEI64_WD_M1_M2_MASK 592 +#define RISCV_PseudoVAMOMAXEI64_WD_M2_M2 593 +#define RISCV_PseudoVAMOMAXEI64_WD_M2_M2_MASK 594 +#define RISCV_PseudoVAMOMAXEI64_WD_M2_M4 595 +#define RISCV_PseudoVAMOMAXEI64_WD_M2_M4_MASK 596 +#define RISCV_PseudoVAMOMAXEI64_WD_M4_M4 597 +#define RISCV_PseudoVAMOMAXEI64_WD_M4_M4_MASK 598 +#define RISCV_PseudoVAMOMAXEI64_WD_M4_M8 599 +#define RISCV_PseudoVAMOMAXEI64_WD_M4_M8_MASK 600 +#define RISCV_PseudoVAMOMAXEI64_WD_M8_M8 601 +#define RISCV_PseudoVAMOMAXEI64_WD_M8_M8_MASK 602 +#define RISCV_PseudoVAMOMAXEI64_WD_MF2_M1 603 +#define RISCV_PseudoVAMOMAXEI64_WD_MF2_M1_MASK 604 +#define RISCV_PseudoVAMOMAXEI8_WD_M1_MF4 605 +#define RISCV_PseudoVAMOMAXEI8_WD_M1_MF4_MASK 606 +#define RISCV_PseudoVAMOMAXEI8_WD_M1_MF8 607 +#define RISCV_PseudoVAMOMAXEI8_WD_M1_MF8_MASK 608 +#define RISCV_PseudoVAMOMAXEI8_WD_M2_MF2 609 +#define RISCV_PseudoVAMOMAXEI8_WD_M2_MF2_MASK 610 +#define RISCV_PseudoVAMOMAXEI8_WD_M2_MF4 611 +#define RISCV_PseudoVAMOMAXEI8_WD_M2_MF4_MASK 612 +#define RISCV_PseudoVAMOMAXEI8_WD_M4_M1 613 +#define RISCV_PseudoVAMOMAXEI8_WD_M4_M1_MASK 614 +#define RISCV_PseudoVAMOMAXEI8_WD_M4_MF2 615 +#define RISCV_PseudoVAMOMAXEI8_WD_M4_MF2_MASK 616 +#define RISCV_PseudoVAMOMAXEI8_WD_M8_M1 617 +#define RISCV_PseudoVAMOMAXEI8_WD_M8_M1_MASK 618 +#define RISCV_PseudoVAMOMAXEI8_WD_M8_M2 619 +#define RISCV_PseudoVAMOMAXEI8_WD_M8_M2_MASK 620 +#define RISCV_PseudoVAMOMAXEI8_WD_MF2_MF8 621 +#define RISCV_PseudoVAMOMAXEI8_WD_MF2_MF8_MASK 622 +#define RISCV_PseudoVAMOMAXUEI16_WD_M1_MF2 623 +#define RISCV_PseudoVAMOMAXUEI16_WD_M1_MF2_MASK 624 +#define RISCV_PseudoVAMOMAXUEI16_WD_M1_MF4 625 +#define RISCV_PseudoVAMOMAXUEI16_WD_M1_MF4_MASK 626 +#define RISCV_PseudoVAMOMAXUEI16_WD_M2_M1 627 +#define RISCV_PseudoVAMOMAXUEI16_WD_M2_M1_MASK 628 +#define RISCV_PseudoVAMOMAXUEI16_WD_M2_MF2 629 +#define RISCV_PseudoVAMOMAXUEI16_WD_M2_MF2_MASK 630 +#define RISCV_PseudoVAMOMAXUEI16_WD_M4_M1 631 +#define RISCV_PseudoVAMOMAXUEI16_WD_M4_M1_MASK 632 +#define RISCV_PseudoVAMOMAXUEI16_WD_M4_M2 633 +#define RISCV_PseudoVAMOMAXUEI16_WD_M4_M2_MASK 634 +#define RISCV_PseudoVAMOMAXUEI16_WD_M8_M2 635 +#define RISCV_PseudoVAMOMAXUEI16_WD_M8_M2_MASK 636 +#define RISCV_PseudoVAMOMAXUEI16_WD_M8_M4 637 +#define RISCV_PseudoVAMOMAXUEI16_WD_M8_M4_MASK 638 +#define RISCV_PseudoVAMOMAXUEI16_WD_MF2_MF4 639 +#define RISCV_PseudoVAMOMAXUEI16_WD_MF2_MF4_MASK 640 +#define RISCV_PseudoVAMOMAXUEI32_WD_M1_M1 641 +#define RISCV_PseudoVAMOMAXUEI32_WD_M1_M1_MASK 642 +#define RISCV_PseudoVAMOMAXUEI32_WD_M1_MF2 643 +#define RISCV_PseudoVAMOMAXUEI32_WD_M1_MF2_MASK 644 +#define RISCV_PseudoVAMOMAXUEI32_WD_M2_M1 645 +#define RISCV_PseudoVAMOMAXUEI32_WD_M2_M1_MASK 646 +#define RISCV_PseudoVAMOMAXUEI32_WD_M2_M2 647 +#define RISCV_PseudoVAMOMAXUEI32_WD_M2_M2_MASK 648 +#define RISCV_PseudoVAMOMAXUEI32_WD_M4_M2 649 +#define RISCV_PseudoVAMOMAXUEI32_WD_M4_M2_MASK 650 +#define RISCV_PseudoVAMOMAXUEI32_WD_M4_M4 651 +#define RISCV_PseudoVAMOMAXUEI32_WD_M4_M4_MASK 652 +#define RISCV_PseudoVAMOMAXUEI32_WD_M8_M4 653 +#define RISCV_PseudoVAMOMAXUEI32_WD_M8_M4_MASK 654 +#define RISCV_PseudoVAMOMAXUEI32_WD_M8_M8 655 +#define RISCV_PseudoVAMOMAXUEI32_WD_M8_M8_MASK 656 +#define RISCV_PseudoVAMOMAXUEI32_WD_MF2_MF2 657 +#define RISCV_PseudoVAMOMAXUEI32_WD_MF2_MF2_MASK 658 +#define RISCV_PseudoVAMOMAXUEI64_WD_M1_M1 659 +#define RISCV_PseudoVAMOMAXUEI64_WD_M1_M1_MASK 660 +#define RISCV_PseudoVAMOMAXUEI64_WD_M1_M2 661 +#define RISCV_PseudoVAMOMAXUEI64_WD_M1_M2_MASK 662 +#define RISCV_PseudoVAMOMAXUEI64_WD_M2_M2 663 +#define RISCV_PseudoVAMOMAXUEI64_WD_M2_M2_MASK 664 +#define RISCV_PseudoVAMOMAXUEI64_WD_M2_M4 665 +#define RISCV_PseudoVAMOMAXUEI64_WD_M2_M4_MASK 666 +#define RISCV_PseudoVAMOMAXUEI64_WD_M4_M4 667 +#define RISCV_PseudoVAMOMAXUEI64_WD_M4_M4_MASK 668 +#define RISCV_PseudoVAMOMAXUEI64_WD_M4_M8 669 +#define RISCV_PseudoVAMOMAXUEI64_WD_M4_M8_MASK 670 +#define RISCV_PseudoVAMOMAXUEI64_WD_M8_M8 671 +#define RISCV_PseudoVAMOMAXUEI64_WD_M8_M8_MASK 672 +#define RISCV_PseudoVAMOMAXUEI64_WD_MF2_M1 673 +#define RISCV_PseudoVAMOMAXUEI64_WD_MF2_M1_MASK 674 +#define RISCV_PseudoVAMOMAXUEI8_WD_M1_MF4 675 +#define RISCV_PseudoVAMOMAXUEI8_WD_M1_MF4_MASK 676 +#define RISCV_PseudoVAMOMAXUEI8_WD_M1_MF8 677 +#define RISCV_PseudoVAMOMAXUEI8_WD_M1_MF8_MASK 678 +#define RISCV_PseudoVAMOMAXUEI8_WD_M2_MF2 679 +#define RISCV_PseudoVAMOMAXUEI8_WD_M2_MF2_MASK 680 +#define RISCV_PseudoVAMOMAXUEI8_WD_M2_MF4 681 +#define RISCV_PseudoVAMOMAXUEI8_WD_M2_MF4_MASK 682 +#define RISCV_PseudoVAMOMAXUEI8_WD_M4_M1 683 +#define RISCV_PseudoVAMOMAXUEI8_WD_M4_M1_MASK 684 +#define RISCV_PseudoVAMOMAXUEI8_WD_M4_MF2 685 +#define RISCV_PseudoVAMOMAXUEI8_WD_M4_MF2_MASK 686 +#define RISCV_PseudoVAMOMAXUEI8_WD_M8_M1 687 +#define RISCV_PseudoVAMOMAXUEI8_WD_M8_M1_MASK 688 +#define RISCV_PseudoVAMOMAXUEI8_WD_M8_M2 689 +#define RISCV_PseudoVAMOMAXUEI8_WD_M8_M2_MASK 690 +#define RISCV_PseudoVAMOMAXUEI8_WD_MF2_MF8 691 +#define RISCV_PseudoVAMOMAXUEI8_WD_MF2_MF8_MASK 692 +#define RISCV_PseudoVAMOMINEI16_WD_M1_MF2 693 +#define RISCV_PseudoVAMOMINEI16_WD_M1_MF2_MASK 694 +#define RISCV_PseudoVAMOMINEI16_WD_M1_MF4 695 +#define RISCV_PseudoVAMOMINEI16_WD_M1_MF4_MASK 696 +#define RISCV_PseudoVAMOMINEI16_WD_M2_M1 697 +#define RISCV_PseudoVAMOMINEI16_WD_M2_M1_MASK 698 +#define RISCV_PseudoVAMOMINEI16_WD_M2_MF2 699 +#define RISCV_PseudoVAMOMINEI16_WD_M2_MF2_MASK 700 +#define RISCV_PseudoVAMOMINEI16_WD_M4_M1 701 +#define RISCV_PseudoVAMOMINEI16_WD_M4_M1_MASK 702 +#define RISCV_PseudoVAMOMINEI16_WD_M4_M2 703 +#define RISCV_PseudoVAMOMINEI16_WD_M4_M2_MASK 704 +#define RISCV_PseudoVAMOMINEI16_WD_M8_M2 705 +#define RISCV_PseudoVAMOMINEI16_WD_M8_M2_MASK 706 +#define RISCV_PseudoVAMOMINEI16_WD_M8_M4 707 +#define RISCV_PseudoVAMOMINEI16_WD_M8_M4_MASK 708 +#define RISCV_PseudoVAMOMINEI16_WD_MF2_MF4 709 +#define RISCV_PseudoVAMOMINEI16_WD_MF2_MF4_MASK 710 +#define RISCV_PseudoVAMOMINEI32_WD_M1_M1 711 +#define RISCV_PseudoVAMOMINEI32_WD_M1_M1_MASK 712 +#define RISCV_PseudoVAMOMINEI32_WD_M1_MF2 713 +#define RISCV_PseudoVAMOMINEI32_WD_M1_MF2_MASK 714 +#define RISCV_PseudoVAMOMINEI32_WD_M2_M1 715 +#define RISCV_PseudoVAMOMINEI32_WD_M2_M1_MASK 716 +#define RISCV_PseudoVAMOMINEI32_WD_M2_M2 717 +#define RISCV_PseudoVAMOMINEI32_WD_M2_M2_MASK 718 +#define RISCV_PseudoVAMOMINEI32_WD_M4_M2 719 +#define RISCV_PseudoVAMOMINEI32_WD_M4_M2_MASK 720 +#define RISCV_PseudoVAMOMINEI32_WD_M4_M4 721 +#define RISCV_PseudoVAMOMINEI32_WD_M4_M4_MASK 722 +#define RISCV_PseudoVAMOMINEI32_WD_M8_M4 723 +#define RISCV_PseudoVAMOMINEI32_WD_M8_M4_MASK 724 +#define RISCV_PseudoVAMOMINEI32_WD_M8_M8 725 +#define RISCV_PseudoVAMOMINEI32_WD_M8_M8_MASK 726 +#define RISCV_PseudoVAMOMINEI32_WD_MF2_MF2 727 +#define RISCV_PseudoVAMOMINEI32_WD_MF2_MF2_MASK 728 +#define RISCV_PseudoVAMOMINEI64_WD_M1_M1 729 +#define RISCV_PseudoVAMOMINEI64_WD_M1_M1_MASK 730 +#define RISCV_PseudoVAMOMINEI64_WD_M1_M2 731 +#define RISCV_PseudoVAMOMINEI64_WD_M1_M2_MASK 732 +#define RISCV_PseudoVAMOMINEI64_WD_M2_M2 733 +#define RISCV_PseudoVAMOMINEI64_WD_M2_M2_MASK 734 +#define RISCV_PseudoVAMOMINEI64_WD_M2_M4 735 +#define RISCV_PseudoVAMOMINEI64_WD_M2_M4_MASK 736 +#define RISCV_PseudoVAMOMINEI64_WD_M4_M4 737 +#define RISCV_PseudoVAMOMINEI64_WD_M4_M4_MASK 738 +#define RISCV_PseudoVAMOMINEI64_WD_M4_M8 739 +#define RISCV_PseudoVAMOMINEI64_WD_M4_M8_MASK 740 +#define RISCV_PseudoVAMOMINEI64_WD_M8_M8 741 +#define RISCV_PseudoVAMOMINEI64_WD_M8_M8_MASK 742 +#define RISCV_PseudoVAMOMINEI64_WD_MF2_M1 743 +#define RISCV_PseudoVAMOMINEI64_WD_MF2_M1_MASK 744 +#define RISCV_PseudoVAMOMINEI8_WD_M1_MF4 745 +#define RISCV_PseudoVAMOMINEI8_WD_M1_MF4_MASK 746 +#define RISCV_PseudoVAMOMINEI8_WD_M1_MF8 747 +#define RISCV_PseudoVAMOMINEI8_WD_M1_MF8_MASK 748 +#define RISCV_PseudoVAMOMINEI8_WD_M2_MF2 749 +#define RISCV_PseudoVAMOMINEI8_WD_M2_MF2_MASK 750 +#define RISCV_PseudoVAMOMINEI8_WD_M2_MF4 751 +#define RISCV_PseudoVAMOMINEI8_WD_M2_MF4_MASK 752 +#define RISCV_PseudoVAMOMINEI8_WD_M4_M1 753 +#define RISCV_PseudoVAMOMINEI8_WD_M4_M1_MASK 754 +#define RISCV_PseudoVAMOMINEI8_WD_M4_MF2 755 +#define RISCV_PseudoVAMOMINEI8_WD_M4_MF2_MASK 756 +#define RISCV_PseudoVAMOMINEI8_WD_M8_M1 757 +#define RISCV_PseudoVAMOMINEI8_WD_M8_M1_MASK 758 +#define RISCV_PseudoVAMOMINEI8_WD_M8_M2 759 +#define RISCV_PseudoVAMOMINEI8_WD_M8_M2_MASK 760 +#define RISCV_PseudoVAMOMINEI8_WD_MF2_MF8 761 +#define RISCV_PseudoVAMOMINEI8_WD_MF2_MF8_MASK 762 +#define RISCV_PseudoVAMOMINUEI16_WD_M1_MF2 763 +#define RISCV_PseudoVAMOMINUEI16_WD_M1_MF2_MASK 764 +#define RISCV_PseudoVAMOMINUEI16_WD_M1_MF4 765 +#define RISCV_PseudoVAMOMINUEI16_WD_M1_MF4_MASK 766 +#define RISCV_PseudoVAMOMINUEI16_WD_M2_M1 767 +#define RISCV_PseudoVAMOMINUEI16_WD_M2_M1_MASK 768 +#define RISCV_PseudoVAMOMINUEI16_WD_M2_MF2 769 +#define RISCV_PseudoVAMOMINUEI16_WD_M2_MF2_MASK 770 +#define RISCV_PseudoVAMOMINUEI16_WD_M4_M1 771 +#define RISCV_PseudoVAMOMINUEI16_WD_M4_M1_MASK 772 +#define RISCV_PseudoVAMOMINUEI16_WD_M4_M2 773 +#define RISCV_PseudoVAMOMINUEI16_WD_M4_M2_MASK 774 +#define RISCV_PseudoVAMOMINUEI16_WD_M8_M2 775 +#define RISCV_PseudoVAMOMINUEI16_WD_M8_M2_MASK 776 +#define RISCV_PseudoVAMOMINUEI16_WD_M8_M4 777 +#define RISCV_PseudoVAMOMINUEI16_WD_M8_M4_MASK 778 +#define RISCV_PseudoVAMOMINUEI16_WD_MF2_MF4 779 +#define RISCV_PseudoVAMOMINUEI16_WD_MF2_MF4_MASK 780 +#define RISCV_PseudoVAMOMINUEI32_WD_M1_M1 781 +#define RISCV_PseudoVAMOMINUEI32_WD_M1_M1_MASK 782 +#define RISCV_PseudoVAMOMINUEI32_WD_M1_MF2 783 +#define RISCV_PseudoVAMOMINUEI32_WD_M1_MF2_MASK 784 +#define RISCV_PseudoVAMOMINUEI32_WD_M2_M1 785 +#define RISCV_PseudoVAMOMINUEI32_WD_M2_M1_MASK 786 +#define RISCV_PseudoVAMOMINUEI32_WD_M2_M2 787 +#define RISCV_PseudoVAMOMINUEI32_WD_M2_M2_MASK 788 +#define RISCV_PseudoVAMOMINUEI32_WD_M4_M2 789 +#define RISCV_PseudoVAMOMINUEI32_WD_M4_M2_MASK 790 +#define RISCV_PseudoVAMOMINUEI32_WD_M4_M4 791 +#define RISCV_PseudoVAMOMINUEI32_WD_M4_M4_MASK 792 +#define RISCV_PseudoVAMOMINUEI32_WD_M8_M4 793 +#define RISCV_PseudoVAMOMINUEI32_WD_M8_M4_MASK 794 +#define RISCV_PseudoVAMOMINUEI32_WD_M8_M8 795 +#define RISCV_PseudoVAMOMINUEI32_WD_M8_M8_MASK 796 +#define RISCV_PseudoVAMOMINUEI32_WD_MF2_MF2 797 +#define RISCV_PseudoVAMOMINUEI32_WD_MF2_MF2_MASK 798 +#define RISCV_PseudoVAMOMINUEI64_WD_M1_M1 799 +#define RISCV_PseudoVAMOMINUEI64_WD_M1_M1_MASK 800 +#define RISCV_PseudoVAMOMINUEI64_WD_M1_M2 801 +#define RISCV_PseudoVAMOMINUEI64_WD_M1_M2_MASK 802 +#define RISCV_PseudoVAMOMINUEI64_WD_M2_M2 803 +#define RISCV_PseudoVAMOMINUEI64_WD_M2_M2_MASK 804 +#define RISCV_PseudoVAMOMINUEI64_WD_M2_M4 805 +#define RISCV_PseudoVAMOMINUEI64_WD_M2_M4_MASK 806 +#define RISCV_PseudoVAMOMINUEI64_WD_M4_M4 807 +#define RISCV_PseudoVAMOMINUEI64_WD_M4_M4_MASK 808 +#define RISCV_PseudoVAMOMINUEI64_WD_M4_M8 809 +#define RISCV_PseudoVAMOMINUEI64_WD_M4_M8_MASK 810 +#define RISCV_PseudoVAMOMINUEI64_WD_M8_M8 811 +#define RISCV_PseudoVAMOMINUEI64_WD_M8_M8_MASK 812 +#define RISCV_PseudoVAMOMINUEI64_WD_MF2_M1 813 +#define RISCV_PseudoVAMOMINUEI64_WD_MF2_M1_MASK 814 +#define RISCV_PseudoVAMOMINUEI8_WD_M1_MF4 815 +#define RISCV_PseudoVAMOMINUEI8_WD_M1_MF4_MASK 816 +#define RISCV_PseudoVAMOMINUEI8_WD_M1_MF8 817 +#define RISCV_PseudoVAMOMINUEI8_WD_M1_MF8_MASK 818 +#define RISCV_PseudoVAMOMINUEI8_WD_M2_MF2 819 +#define RISCV_PseudoVAMOMINUEI8_WD_M2_MF2_MASK 820 +#define RISCV_PseudoVAMOMINUEI8_WD_M2_MF4 821 +#define RISCV_PseudoVAMOMINUEI8_WD_M2_MF4_MASK 822 +#define RISCV_PseudoVAMOMINUEI8_WD_M4_M1 823 +#define RISCV_PseudoVAMOMINUEI8_WD_M4_M1_MASK 824 +#define RISCV_PseudoVAMOMINUEI8_WD_M4_MF2 825 +#define RISCV_PseudoVAMOMINUEI8_WD_M4_MF2_MASK 826 +#define RISCV_PseudoVAMOMINUEI8_WD_M8_M1 827 +#define RISCV_PseudoVAMOMINUEI8_WD_M8_M1_MASK 828 +#define RISCV_PseudoVAMOMINUEI8_WD_M8_M2 829 +#define RISCV_PseudoVAMOMINUEI8_WD_M8_M2_MASK 830 +#define RISCV_PseudoVAMOMINUEI8_WD_MF2_MF8 831 +#define RISCV_PseudoVAMOMINUEI8_WD_MF2_MF8_MASK 832 +#define RISCV_PseudoVAMOOREI16_WD_M1_MF2 833 +#define RISCV_PseudoVAMOOREI16_WD_M1_MF2_MASK 834 +#define RISCV_PseudoVAMOOREI16_WD_M1_MF4 835 +#define RISCV_PseudoVAMOOREI16_WD_M1_MF4_MASK 836 +#define RISCV_PseudoVAMOOREI16_WD_M2_M1 837 +#define RISCV_PseudoVAMOOREI16_WD_M2_M1_MASK 838 +#define RISCV_PseudoVAMOOREI16_WD_M2_MF2 839 +#define RISCV_PseudoVAMOOREI16_WD_M2_MF2_MASK 840 +#define RISCV_PseudoVAMOOREI16_WD_M4_M1 841 +#define RISCV_PseudoVAMOOREI16_WD_M4_M1_MASK 842 +#define RISCV_PseudoVAMOOREI16_WD_M4_M2 843 +#define RISCV_PseudoVAMOOREI16_WD_M4_M2_MASK 844 +#define RISCV_PseudoVAMOOREI16_WD_M8_M2 845 +#define RISCV_PseudoVAMOOREI16_WD_M8_M2_MASK 846 +#define RISCV_PseudoVAMOOREI16_WD_M8_M4 847 +#define RISCV_PseudoVAMOOREI16_WD_M8_M4_MASK 848 +#define RISCV_PseudoVAMOOREI16_WD_MF2_MF4 849 +#define RISCV_PseudoVAMOOREI16_WD_MF2_MF4_MASK 850 +#define RISCV_PseudoVAMOOREI32_WD_M1_M1 851 +#define RISCV_PseudoVAMOOREI32_WD_M1_M1_MASK 852 +#define RISCV_PseudoVAMOOREI32_WD_M1_MF2 853 +#define RISCV_PseudoVAMOOREI32_WD_M1_MF2_MASK 854 +#define RISCV_PseudoVAMOOREI32_WD_M2_M1 855 +#define RISCV_PseudoVAMOOREI32_WD_M2_M1_MASK 856 +#define RISCV_PseudoVAMOOREI32_WD_M2_M2 857 +#define RISCV_PseudoVAMOOREI32_WD_M2_M2_MASK 858 +#define RISCV_PseudoVAMOOREI32_WD_M4_M2 859 +#define RISCV_PseudoVAMOOREI32_WD_M4_M2_MASK 860 +#define RISCV_PseudoVAMOOREI32_WD_M4_M4 861 +#define RISCV_PseudoVAMOOREI32_WD_M4_M4_MASK 862 +#define RISCV_PseudoVAMOOREI32_WD_M8_M4 863 +#define RISCV_PseudoVAMOOREI32_WD_M8_M4_MASK 864 +#define RISCV_PseudoVAMOOREI32_WD_M8_M8 865 +#define RISCV_PseudoVAMOOREI32_WD_M8_M8_MASK 866 +#define RISCV_PseudoVAMOOREI32_WD_MF2_MF2 867 +#define RISCV_PseudoVAMOOREI32_WD_MF2_MF2_MASK 868 +#define RISCV_PseudoVAMOOREI64_WD_M1_M1 869 +#define RISCV_PseudoVAMOOREI64_WD_M1_M1_MASK 870 +#define RISCV_PseudoVAMOOREI64_WD_M1_M2 871 +#define RISCV_PseudoVAMOOREI64_WD_M1_M2_MASK 872 +#define RISCV_PseudoVAMOOREI64_WD_M2_M2 873 +#define RISCV_PseudoVAMOOREI64_WD_M2_M2_MASK 874 +#define RISCV_PseudoVAMOOREI64_WD_M2_M4 875 +#define RISCV_PseudoVAMOOREI64_WD_M2_M4_MASK 876 +#define RISCV_PseudoVAMOOREI64_WD_M4_M4 877 +#define RISCV_PseudoVAMOOREI64_WD_M4_M4_MASK 878 +#define RISCV_PseudoVAMOOREI64_WD_M4_M8 879 +#define RISCV_PseudoVAMOOREI64_WD_M4_M8_MASK 880 +#define RISCV_PseudoVAMOOREI64_WD_M8_M8 881 +#define RISCV_PseudoVAMOOREI64_WD_M8_M8_MASK 882 +#define RISCV_PseudoVAMOOREI64_WD_MF2_M1 883 +#define RISCV_PseudoVAMOOREI64_WD_MF2_M1_MASK 884 +#define RISCV_PseudoVAMOOREI8_WD_M1_MF4 885 +#define RISCV_PseudoVAMOOREI8_WD_M1_MF4_MASK 886 +#define RISCV_PseudoVAMOOREI8_WD_M1_MF8 887 +#define RISCV_PseudoVAMOOREI8_WD_M1_MF8_MASK 888 +#define RISCV_PseudoVAMOOREI8_WD_M2_MF2 889 +#define RISCV_PseudoVAMOOREI8_WD_M2_MF2_MASK 890 +#define RISCV_PseudoVAMOOREI8_WD_M2_MF4 891 +#define RISCV_PseudoVAMOOREI8_WD_M2_MF4_MASK 892 +#define RISCV_PseudoVAMOOREI8_WD_M4_M1 893 +#define RISCV_PseudoVAMOOREI8_WD_M4_M1_MASK 894 +#define RISCV_PseudoVAMOOREI8_WD_M4_MF2 895 +#define RISCV_PseudoVAMOOREI8_WD_M4_MF2_MASK 896 +#define RISCV_PseudoVAMOOREI8_WD_M8_M1 897 +#define RISCV_PseudoVAMOOREI8_WD_M8_M1_MASK 898 +#define RISCV_PseudoVAMOOREI8_WD_M8_M2 899 +#define RISCV_PseudoVAMOOREI8_WD_M8_M2_MASK 900 +#define RISCV_PseudoVAMOOREI8_WD_MF2_MF8 901 +#define RISCV_PseudoVAMOOREI8_WD_MF2_MF8_MASK 902 +#define RISCV_PseudoVAMOSWAPEI16_WD_M1_MF2 903 +#define RISCV_PseudoVAMOSWAPEI16_WD_M1_MF2_MASK 904 +#define RISCV_PseudoVAMOSWAPEI16_WD_M1_MF4 905 +#define RISCV_PseudoVAMOSWAPEI16_WD_M1_MF4_MASK 906 +#define RISCV_PseudoVAMOSWAPEI16_WD_M2_M1 907 +#define RISCV_PseudoVAMOSWAPEI16_WD_M2_M1_MASK 908 +#define RISCV_PseudoVAMOSWAPEI16_WD_M2_MF2 909 +#define RISCV_PseudoVAMOSWAPEI16_WD_M2_MF2_MASK 910 +#define RISCV_PseudoVAMOSWAPEI16_WD_M4_M1 911 +#define RISCV_PseudoVAMOSWAPEI16_WD_M4_M1_MASK 912 +#define RISCV_PseudoVAMOSWAPEI16_WD_M4_M2 913 +#define RISCV_PseudoVAMOSWAPEI16_WD_M4_M2_MASK 914 +#define RISCV_PseudoVAMOSWAPEI16_WD_M8_M2 915 +#define RISCV_PseudoVAMOSWAPEI16_WD_M8_M2_MASK 916 +#define RISCV_PseudoVAMOSWAPEI16_WD_M8_M4 917 +#define RISCV_PseudoVAMOSWAPEI16_WD_M8_M4_MASK 918 +#define RISCV_PseudoVAMOSWAPEI16_WD_MF2_MF4 919 +#define RISCV_PseudoVAMOSWAPEI16_WD_MF2_MF4_MASK 920 +#define RISCV_PseudoVAMOSWAPEI32_WD_M1_M1 921 +#define RISCV_PseudoVAMOSWAPEI32_WD_M1_M1_MASK 922 +#define RISCV_PseudoVAMOSWAPEI32_WD_M1_MF2 923 +#define RISCV_PseudoVAMOSWAPEI32_WD_M1_MF2_MASK 924 +#define RISCV_PseudoVAMOSWAPEI32_WD_M2_M1 925 +#define RISCV_PseudoVAMOSWAPEI32_WD_M2_M1_MASK 926 +#define RISCV_PseudoVAMOSWAPEI32_WD_M2_M2 927 +#define RISCV_PseudoVAMOSWAPEI32_WD_M2_M2_MASK 928 +#define RISCV_PseudoVAMOSWAPEI32_WD_M4_M2 929 +#define RISCV_PseudoVAMOSWAPEI32_WD_M4_M2_MASK 930 +#define RISCV_PseudoVAMOSWAPEI32_WD_M4_M4 931 +#define RISCV_PseudoVAMOSWAPEI32_WD_M4_M4_MASK 932 +#define RISCV_PseudoVAMOSWAPEI32_WD_M8_M4 933 +#define RISCV_PseudoVAMOSWAPEI32_WD_M8_M4_MASK 934 +#define RISCV_PseudoVAMOSWAPEI32_WD_M8_M8 935 +#define RISCV_PseudoVAMOSWAPEI32_WD_M8_M8_MASK 936 +#define RISCV_PseudoVAMOSWAPEI32_WD_MF2_MF2 937 +#define RISCV_PseudoVAMOSWAPEI32_WD_MF2_MF2_MASK 938 +#define RISCV_PseudoVAMOSWAPEI64_WD_M1_M1 939 +#define RISCV_PseudoVAMOSWAPEI64_WD_M1_M1_MASK 940 +#define RISCV_PseudoVAMOSWAPEI64_WD_M1_M2 941 +#define RISCV_PseudoVAMOSWAPEI64_WD_M1_M2_MASK 942 +#define RISCV_PseudoVAMOSWAPEI64_WD_M2_M2 943 +#define RISCV_PseudoVAMOSWAPEI64_WD_M2_M2_MASK 944 +#define RISCV_PseudoVAMOSWAPEI64_WD_M2_M4 945 +#define RISCV_PseudoVAMOSWAPEI64_WD_M2_M4_MASK 946 +#define RISCV_PseudoVAMOSWAPEI64_WD_M4_M4 947 +#define RISCV_PseudoVAMOSWAPEI64_WD_M4_M4_MASK 948 +#define RISCV_PseudoVAMOSWAPEI64_WD_M4_M8 949 +#define RISCV_PseudoVAMOSWAPEI64_WD_M4_M8_MASK 950 +#define RISCV_PseudoVAMOSWAPEI64_WD_M8_M8 951 +#define RISCV_PseudoVAMOSWAPEI64_WD_M8_M8_MASK 952 +#define RISCV_PseudoVAMOSWAPEI64_WD_MF2_M1 953 +#define RISCV_PseudoVAMOSWAPEI64_WD_MF2_M1_MASK 954 +#define RISCV_PseudoVAMOSWAPEI8_WD_M1_MF4 955 +#define RISCV_PseudoVAMOSWAPEI8_WD_M1_MF4_MASK 956 +#define RISCV_PseudoVAMOSWAPEI8_WD_M1_MF8 957 +#define RISCV_PseudoVAMOSWAPEI8_WD_M1_MF8_MASK 958 +#define RISCV_PseudoVAMOSWAPEI8_WD_M2_MF2 959 +#define RISCV_PseudoVAMOSWAPEI8_WD_M2_MF2_MASK 960 +#define RISCV_PseudoVAMOSWAPEI8_WD_M2_MF4 961 +#define RISCV_PseudoVAMOSWAPEI8_WD_M2_MF4_MASK 962 +#define RISCV_PseudoVAMOSWAPEI8_WD_M4_M1 963 +#define RISCV_PseudoVAMOSWAPEI8_WD_M4_M1_MASK 964 +#define RISCV_PseudoVAMOSWAPEI8_WD_M4_MF2 965 +#define RISCV_PseudoVAMOSWAPEI8_WD_M4_MF2_MASK 966 +#define RISCV_PseudoVAMOSWAPEI8_WD_M8_M1 967 +#define RISCV_PseudoVAMOSWAPEI8_WD_M8_M1_MASK 968 +#define RISCV_PseudoVAMOSWAPEI8_WD_M8_M2 969 +#define RISCV_PseudoVAMOSWAPEI8_WD_M8_M2_MASK 970 +#define RISCV_PseudoVAMOSWAPEI8_WD_MF2_MF8 971 +#define RISCV_PseudoVAMOSWAPEI8_WD_MF2_MF8_MASK 972 +#define RISCV_PseudoVAMOXOREI16_WD_M1_MF2 973 +#define RISCV_PseudoVAMOXOREI16_WD_M1_MF2_MASK 974 +#define RISCV_PseudoVAMOXOREI16_WD_M1_MF4 975 +#define RISCV_PseudoVAMOXOREI16_WD_M1_MF4_MASK 976 +#define RISCV_PseudoVAMOXOREI16_WD_M2_M1 977 +#define RISCV_PseudoVAMOXOREI16_WD_M2_M1_MASK 978 +#define RISCV_PseudoVAMOXOREI16_WD_M2_MF2 979 +#define RISCV_PseudoVAMOXOREI16_WD_M2_MF2_MASK 980 +#define RISCV_PseudoVAMOXOREI16_WD_M4_M1 981 +#define RISCV_PseudoVAMOXOREI16_WD_M4_M1_MASK 982 +#define RISCV_PseudoVAMOXOREI16_WD_M4_M2 983 +#define RISCV_PseudoVAMOXOREI16_WD_M4_M2_MASK 984 +#define RISCV_PseudoVAMOXOREI16_WD_M8_M2 985 +#define RISCV_PseudoVAMOXOREI16_WD_M8_M2_MASK 986 +#define RISCV_PseudoVAMOXOREI16_WD_M8_M4 987 +#define RISCV_PseudoVAMOXOREI16_WD_M8_M4_MASK 988 +#define RISCV_PseudoVAMOXOREI16_WD_MF2_MF4 989 +#define RISCV_PseudoVAMOXOREI16_WD_MF2_MF4_MASK 990 +#define RISCV_PseudoVAMOXOREI32_WD_M1_M1 991 +#define RISCV_PseudoVAMOXOREI32_WD_M1_M1_MASK 992 +#define RISCV_PseudoVAMOXOREI32_WD_M1_MF2 993 +#define RISCV_PseudoVAMOXOREI32_WD_M1_MF2_MASK 994 +#define RISCV_PseudoVAMOXOREI32_WD_M2_M1 995 +#define RISCV_PseudoVAMOXOREI32_WD_M2_M1_MASK 996 +#define RISCV_PseudoVAMOXOREI32_WD_M2_M2 997 +#define RISCV_PseudoVAMOXOREI32_WD_M2_M2_MASK 998 +#define RISCV_PseudoVAMOXOREI32_WD_M4_M2 999 +#define RISCV_PseudoVAMOXOREI32_WD_M4_M2_MASK 1000 +#define RISCV_PseudoVAMOXOREI32_WD_M4_M4 1001 +#define RISCV_PseudoVAMOXOREI32_WD_M4_M4_MASK 1002 +#define RISCV_PseudoVAMOXOREI32_WD_M8_M4 1003 +#define RISCV_PseudoVAMOXOREI32_WD_M8_M4_MASK 1004 +#define RISCV_PseudoVAMOXOREI32_WD_M8_M8 1005 +#define RISCV_PseudoVAMOXOREI32_WD_M8_M8_MASK 1006 +#define RISCV_PseudoVAMOXOREI32_WD_MF2_MF2 1007 +#define RISCV_PseudoVAMOXOREI32_WD_MF2_MF2_MASK 1008 +#define RISCV_PseudoVAMOXOREI64_WD_M1_M1 1009 +#define RISCV_PseudoVAMOXOREI64_WD_M1_M1_MASK 1010 +#define RISCV_PseudoVAMOXOREI64_WD_M1_M2 1011 +#define RISCV_PseudoVAMOXOREI64_WD_M1_M2_MASK 1012 +#define RISCV_PseudoVAMOXOREI64_WD_M2_M2 1013 +#define RISCV_PseudoVAMOXOREI64_WD_M2_M2_MASK 1014 +#define RISCV_PseudoVAMOXOREI64_WD_M2_M4 1015 +#define RISCV_PseudoVAMOXOREI64_WD_M2_M4_MASK 1016 +#define RISCV_PseudoVAMOXOREI64_WD_M4_M4 1017 +#define RISCV_PseudoVAMOXOREI64_WD_M4_M4_MASK 1018 +#define RISCV_PseudoVAMOXOREI64_WD_M4_M8 1019 +#define RISCV_PseudoVAMOXOREI64_WD_M4_M8_MASK 1020 +#define RISCV_PseudoVAMOXOREI64_WD_M8_M8 1021 +#define RISCV_PseudoVAMOXOREI64_WD_M8_M8_MASK 1022 +#define RISCV_PseudoVAMOXOREI64_WD_MF2_M1 1023 +#define RISCV_PseudoVAMOXOREI64_WD_MF2_M1_MASK 1024 +#define RISCV_PseudoVAMOXOREI8_WD_M1_MF4 1025 +#define RISCV_PseudoVAMOXOREI8_WD_M1_MF4_MASK 1026 +#define RISCV_PseudoVAMOXOREI8_WD_M1_MF8 1027 +#define RISCV_PseudoVAMOXOREI8_WD_M1_MF8_MASK 1028 +#define RISCV_PseudoVAMOXOREI8_WD_M2_MF2 1029 +#define RISCV_PseudoVAMOXOREI8_WD_M2_MF2_MASK 1030 +#define RISCV_PseudoVAMOXOREI8_WD_M2_MF4 1031 +#define RISCV_PseudoVAMOXOREI8_WD_M2_MF4_MASK 1032 +#define RISCV_PseudoVAMOXOREI8_WD_M4_M1 1033 +#define RISCV_PseudoVAMOXOREI8_WD_M4_M1_MASK 1034 +#define RISCV_PseudoVAMOXOREI8_WD_M4_MF2 1035 +#define RISCV_PseudoVAMOXOREI8_WD_M4_MF2_MASK 1036 +#define RISCV_PseudoVAMOXOREI8_WD_M8_M1 1037 +#define RISCV_PseudoVAMOXOREI8_WD_M8_M1_MASK 1038 +#define RISCV_PseudoVAMOXOREI8_WD_M8_M2 1039 +#define RISCV_PseudoVAMOXOREI8_WD_M8_M2_MASK 1040 +#define RISCV_PseudoVAMOXOREI8_WD_MF2_MF8 1041 +#define RISCV_PseudoVAMOXOREI8_WD_MF2_MF8_MASK 1042 +#define RISCV_PseudoVAND_VI_M1 1043 +#define RISCV_PseudoVAND_VI_M1_MASK 1044 +#define RISCV_PseudoVAND_VI_M2 1045 +#define RISCV_PseudoVAND_VI_M2_MASK 1046 +#define RISCV_PseudoVAND_VI_M4 1047 +#define RISCV_PseudoVAND_VI_M4_MASK 1048 +#define RISCV_PseudoVAND_VI_M8 1049 +#define RISCV_PseudoVAND_VI_M8_MASK 1050 +#define RISCV_PseudoVAND_VI_MF2 1051 +#define RISCV_PseudoVAND_VI_MF2_MASK 1052 +#define RISCV_PseudoVAND_VI_MF4 1053 +#define RISCV_PseudoVAND_VI_MF4_MASK 1054 +#define RISCV_PseudoVAND_VI_MF8 1055 +#define RISCV_PseudoVAND_VI_MF8_MASK 1056 +#define RISCV_PseudoVAND_VV_M1 1057 +#define RISCV_PseudoVAND_VV_M1_MASK 1058 +#define RISCV_PseudoVAND_VV_M2 1059 +#define RISCV_PseudoVAND_VV_M2_MASK 1060 +#define RISCV_PseudoVAND_VV_M4 1061 +#define RISCV_PseudoVAND_VV_M4_MASK 1062 +#define RISCV_PseudoVAND_VV_M8 1063 +#define RISCV_PseudoVAND_VV_M8_MASK 1064 +#define RISCV_PseudoVAND_VV_MF2 1065 +#define RISCV_PseudoVAND_VV_MF2_MASK 1066 +#define RISCV_PseudoVAND_VV_MF4 1067 +#define RISCV_PseudoVAND_VV_MF4_MASK 1068 +#define RISCV_PseudoVAND_VV_MF8 1069 +#define RISCV_PseudoVAND_VV_MF8_MASK 1070 +#define RISCV_PseudoVAND_VX_M1 1071 +#define RISCV_PseudoVAND_VX_M1_MASK 1072 +#define RISCV_PseudoVAND_VX_M2 1073 +#define RISCV_PseudoVAND_VX_M2_MASK 1074 +#define RISCV_PseudoVAND_VX_M4 1075 +#define RISCV_PseudoVAND_VX_M4_MASK 1076 +#define RISCV_PseudoVAND_VX_M8 1077 +#define RISCV_PseudoVAND_VX_M8_MASK 1078 +#define RISCV_PseudoVAND_VX_MF2 1079 +#define RISCV_PseudoVAND_VX_MF2_MASK 1080 +#define RISCV_PseudoVAND_VX_MF4 1081 +#define RISCV_PseudoVAND_VX_MF4_MASK 1082 +#define RISCV_PseudoVAND_VX_MF8 1083 +#define RISCV_PseudoVAND_VX_MF8_MASK 1084 +#define RISCV_PseudoVASUBU_VV_M1 1085 +#define RISCV_PseudoVASUBU_VV_M1_MASK 1086 +#define RISCV_PseudoVASUBU_VV_M2 1087 +#define RISCV_PseudoVASUBU_VV_M2_MASK 1088 +#define RISCV_PseudoVASUBU_VV_M4 1089 +#define RISCV_PseudoVASUBU_VV_M4_MASK 1090 +#define RISCV_PseudoVASUBU_VV_M8 1091 +#define RISCV_PseudoVASUBU_VV_M8_MASK 1092 +#define RISCV_PseudoVASUBU_VV_MF2 1093 +#define RISCV_PseudoVASUBU_VV_MF2_MASK 1094 +#define RISCV_PseudoVASUBU_VV_MF4 1095 +#define RISCV_PseudoVASUBU_VV_MF4_MASK 1096 +#define RISCV_PseudoVASUBU_VV_MF8 1097 +#define RISCV_PseudoVASUBU_VV_MF8_MASK 1098 +#define RISCV_PseudoVASUBU_VX_M1 1099 +#define RISCV_PseudoVASUBU_VX_M1_MASK 1100 +#define RISCV_PseudoVASUBU_VX_M2 1101 +#define RISCV_PseudoVASUBU_VX_M2_MASK 1102 +#define RISCV_PseudoVASUBU_VX_M4 1103 +#define RISCV_PseudoVASUBU_VX_M4_MASK 1104 +#define RISCV_PseudoVASUBU_VX_M8 1105 +#define RISCV_PseudoVASUBU_VX_M8_MASK 1106 +#define RISCV_PseudoVASUBU_VX_MF2 1107 +#define RISCV_PseudoVASUBU_VX_MF2_MASK 1108 +#define RISCV_PseudoVASUBU_VX_MF4 1109 +#define RISCV_PseudoVASUBU_VX_MF4_MASK 1110 +#define RISCV_PseudoVASUBU_VX_MF8 1111 +#define RISCV_PseudoVASUBU_VX_MF8_MASK 1112 +#define RISCV_PseudoVASUB_VV_M1 1113 +#define RISCV_PseudoVASUB_VV_M1_MASK 1114 +#define RISCV_PseudoVASUB_VV_M2 1115 +#define RISCV_PseudoVASUB_VV_M2_MASK 1116 +#define RISCV_PseudoVASUB_VV_M4 1117 +#define RISCV_PseudoVASUB_VV_M4_MASK 1118 +#define RISCV_PseudoVASUB_VV_M8 1119 +#define RISCV_PseudoVASUB_VV_M8_MASK 1120 +#define RISCV_PseudoVASUB_VV_MF2 1121 +#define RISCV_PseudoVASUB_VV_MF2_MASK 1122 +#define RISCV_PseudoVASUB_VV_MF4 1123 +#define RISCV_PseudoVASUB_VV_MF4_MASK 1124 +#define RISCV_PseudoVASUB_VV_MF8 1125 +#define RISCV_PseudoVASUB_VV_MF8_MASK 1126 +#define RISCV_PseudoVASUB_VX_M1 1127 +#define RISCV_PseudoVASUB_VX_M1_MASK 1128 +#define RISCV_PseudoVASUB_VX_M2 1129 +#define RISCV_PseudoVASUB_VX_M2_MASK 1130 +#define RISCV_PseudoVASUB_VX_M4 1131 +#define RISCV_PseudoVASUB_VX_M4_MASK 1132 +#define RISCV_PseudoVASUB_VX_M8 1133 +#define RISCV_PseudoVASUB_VX_M8_MASK 1134 +#define RISCV_PseudoVASUB_VX_MF2 1135 +#define RISCV_PseudoVASUB_VX_MF2_MASK 1136 +#define RISCV_PseudoVASUB_VX_MF4 1137 +#define RISCV_PseudoVASUB_VX_MF4_MASK 1138 +#define RISCV_PseudoVASUB_VX_MF8 1139 +#define RISCV_PseudoVASUB_VX_MF8_MASK 1140 +#define RISCV_PseudoVCOMPRESS_VM_M1 1141 +#define RISCV_PseudoVCOMPRESS_VM_M2 1142 +#define RISCV_PseudoVCOMPRESS_VM_M4 1143 +#define RISCV_PseudoVCOMPRESS_VM_M8 1144 +#define RISCV_PseudoVCOMPRESS_VM_MF2 1145 +#define RISCV_PseudoVCOMPRESS_VM_MF4 1146 +#define RISCV_PseudoVCOMPRESS_VM_MF8 1147 +#define RISCV_PseudoVCPOP_M_B1 1148 +#define RISCV_PseudoVCPOP_M_B16 1149 +#define RISCV_PseudoVCPOP_M_B16_MASK 1150 +#define RISCV_PseudoVCPOP_M_B1_MASK 1151 +#define RISCV_PseudoVCPOP_M_B2 1152 +#define RISCV_PseudoVCPOP_M_B2_MASK 1153 +#define RISCV_PseudoVCPOP_M_B32 1154 +#define RISCV_PseudoVCPOP_M_B32_MASK 1155 +#define RISCV_PseudoVCPOP_M_B4 1156 +#define RISCV_PseudoVCPOP_M_B4_MASK 1157 +#define RISCV_PseudoVCPOP_M_B64 1158 +#define RISCV_PseudoVCPOP_M_B64_MASK 1159 +#define RISCV_PseudoVCPOP_M_B8 1160 +#define RISCV_PseudoVCPOP_M_B8_MASK 1161 +#define RISCV_PseudoVDIVU_VV_M1 1162 +#define RISCV_PseudoVDIVU_VV_M1_MASK 1163 +#define RISCV_PseudoVDIVU_VV_M2 1164 +#define RISCV_PseudoVDIVU_VV_M2_MASK 1165 +#define RISCV_PseudoVDIVU_VV_M4 1166 +#define RISCV_PseudoVDIVU_VV_M4_MASK 1167 +#define RISCV_PseudoVDIVU_VV_M8 1168 +#define RISCV_PseudoVDIVU_VV_M8_MASK 1169 +#define RISCV_PseudoVDIVU_VV_MF2 1170 +#define RISCV_PseudoVDIVU_VV_MF2_MASK 1171 +#define RISCV_PseudoVDIVU_VV_MF4 1172 +#define RISCV_PseudoVDIVU_VV_MF4_MASK 1173 +#define RISCV_PseudoVDIVU_VV_MF8 1174 +#define RISCV_PseudoVDIVU_VV_MF8_MASK 1175 +#define RISCV_PseudoVDIVU_VX_M1 1176 +#define RISCV_PseudoVDIVU_VX_M1_MASK 1177 +#define RISCV_PseudoVDIVU_VX_M2 1178 +#define RISCV_PseudoVDIVU_VX_M2_MASK 1179 +#define RISCV_PseudoVDIVU_VX_M4 1180 +#define RISCV_PseudoVDIVU_VX_M4_MASK 1181 +#define RISCV_PseudoVDIVU_VX_M8 1182 +#define RISCV_PseudoVDIVU_VX_M8_MASK 1183 +#define RISCV_PseudoVDIVU_VX_MF2 1184 +#define RISCV_PseudoVDIVU_VX_MF2_MASK 1185 +#define RISCV_PseudoVDIVU_VX_MF4 1186 +#define RISCV_PseudoVDIVU_VX_MF4_MASK 1187 +#define RISCV_PseudoVDIVU_VX_MF8 1188 +#define RISCV_PseudoVDIVU_VX_MF8_MASK 1189 +#define RISCV_PseudoVDIV_VV_M1 1190 +#define RISCV_PseudoVDIV_VV_M1_MASK 1191 +#define RISCV_PseudoVDIV_VV_M2 1192 +#define RISCV_PseudoVDIV_VV_M2_MASK 1193 +#define RISCV_PseudoVDIV_VV_M4 1194 +#define RISCV_PseudoVDIV_VV_M4_MASK 1195 +#define RISCV_PseudoVDIV_VV_M8 1196 +#define RISCV_PseudoVDIV_VV_M8_MASK 1197 +#define RISCV_PseudoVDIV_VV_MF2 1198 +#define RISCV_PseudoVDIV_VV_MF2_MASK 1199 +#define RISCV_PseudoVDIV_VV_MF4 1200 +#define RISCV_PseudoVDIV_VV_MF4_MASK 1201 +#define RISCV_PseudoVDIV_VV_MF8 1202 +#define RISCV_PseudoVDIV_VV_MF8_MASK 1203 +#define RISCV_PseudoVDIV_VX_M1 1204 +#define RISCV_PseudoVDIV_VX_M1_MASK 1205 +#define RISCV_PseudoVDIV_VX_M2 1206 +#define RISCV_PseudoVDIV_VX_M2_MASK 1207 +#define RISCV_PseudoVDIV_VX_M4 1208 +#define RISCV_PseudoVDIV_VX_M4_MASK 1209 +#define RISCV_PseudoVDIV_VX_M8 1210 +#define RISCV_PseudoVDIV_VX_M8_MASK 1211 +#define RISCV_PseudoVDIV_VX_MF2 1212 +#define RISCV_PseudoVDIV_VX_MF2_MASK 1213 +#define RISCV_PseudoVDIV_VX_MF4 1214 +#define RISCV_PseudoVDIV_VX_MF4_MASK 1215 +#define RISCV_PseudoVDIV_VX_MF8 1216 +#define RISCV_PseudoVDIV_VX_MF8_MASK 1217 +#define RISCV_PseudoVFADD_VF16_M1 1218 +#define RISCV_PseudoVFADD_VF16_M1_MASK 1219 +#define RISCV_PseudoVFADD_VF16_M2 1220 +#define RISCV_PseudoVFADD_VF16_M2_MASK 1221 +#define RISCV_PseudoVFADD_VF16_M4 1222 +#define RISCV_PseudoVFADD_VF16_M4_MASK 1223 +#define RISCV_PseudoVFADD_VF16_M8 1224 +#define RISCV_PseudoVFADD_VF16_M8_MASK 1225 +#define RISCV_PseudoVFADD_VF16_MF2 1226 +#define RISCV_PseudoVFADD_VF16_MF2_MASK 1227 +#define RISCV_PseudoVFADD_VF16_MF4 1228 +#define RISCV_PseudoVFADD_VF16_MF4_MASK 1229 +#define RISCV_PseudoVFADD_VF16_MF8 1230 +#define RISCV_PseudoVFADD_VF16_MF8_MASK 1231 +#define RISCV_PseudoVFADD_VF32_M1 1232 +#define RISCV_PseudoVFADD_VF32_M1_MASK 1233 +#define RISCV_PseudoVFADD_VF32_M2 1234 +#define RISCV_PseudoVFADD_VF32_M2_MASK 1235 +#define RISCV_PseudoVFADD_VF32_M4 1236 +#define RISCV_PseudoVFADD_VF32_M4_MASK 1237 +#define RISCV_PseudoVFADD_VF32_M8 1238 +#define RISCV_PseudoVFADD_VF32_M8_MASK 1239 +#define RISCV_PseudoVFADD_VF32_MF2 1240 +#define RISCV_PseudoVFADD_VF32_MF2_MASK 1241 +#define RISCV_PseudoVFADD_VF32_MF4 1242 +#define RISCV_PseudoVFADD_VF32_MF4_MASK 1243 +#define RISCV_PseudoVFADD_VF32_MF8 1244 +#define RISCV_PseudoVFADD_VF32_MF8_MASK 1245 +#define RISCV_PseudoVFADD_VF64_M1 1246 +#define RISCV_PseudoVFADD_VF64_M1_MASK 1247 +#define RISCV_PseudoVFADD_VF64_M2 1248 +#define RISCV_PseudoVFADD_VF64_M2_MASK 1249 +#define RISCV_PseudoVFADD_VF64_M4 1250 +#define RISCV_PseudoVFADD_VF64_M4_MASK 1251 +#define RISCV_PseudoVFADD_VF64_M8 1252 +#define RISCV_PseudoVFADD_VF64_M8_MASK 1253 +#define RISCV_PseudoVFADD_VF64_MF2 1254 +#define RISCV_PseudoVFADD_VF64_MF2_MASK 1255 +#define RISCV_PseudoVFADD_VF64_MF4 1256 +#define RISCV_PseudoVFADD_VF64_MF4_MASK 1257 +#define RISCV_PseudoVFADD_VF64_MF8 1258 +#define RISCV_PseudoVFADD_VF64_MF8_MASK 1259 +#define RISCV_PseudoVFADD_VV_M1 1260 +#define RISCV_PseudoVFADD_VV_M1_MASK 1261 +#define RISCV_PseudoVFADD_VV_M2 1262 +#define RISCV_PseudoVFADD_VV_M2_MASK 1263 +#define RISCV_PseudoVFADD_VV_M4 1264 +#define RISCV_PseudoVFADD_VV_M4_MASK 1265 +#define RISCV_PseudoVFADD_VV_M8 1266 +#define RISCV_PseudoVFADD_VV_M8_MASK 1267 +#define RISCV_PseudoVFADD_VV_MF2 1268 +#define RISCV_PseudoVFADD_VV_MF2_MASK 1269 +#define RISCV_PseudoVFADD_VV_MF4 1270 +#define RISCV_PseudoVFADD_VV_MF4_MASK 1271 +#define RISCV_PseudoVFADD_VV_MF8 1272 +#define RISCV_PseudoVFADD_VV_MF8_MASK 1273 +#define RISCV_PseudoVFCLASS_V_M1 1274 +#define RISCV_PseudoVFCLASS_V_M1_MASK 1275 +#define RISCV_PseudoVFCLASS_V_M2 1276 +#define RISCV_PseudoVFCLASS_V_M2_MASK 1277 +#define RISCV_PseudoVFCLASS_V_M4 1278 +#define RISCV_PseudoVFCLASS_V_M4_MASK 1279 +#define RISCV_PseudoVFCLASS_V_M8 1280 +#define RISCV_PseudoVFCLASS_V_M8_MASK 1281 +#define RISCV_PseudoVFCLASS_V_MF2 1282 +#define RISCV_PseudoVFCLASS_V_MF2_MASK 1283 +#define RISCV_PseudoVFCLASS_V_MF4 1284 +#define RISCV_PseudoVFCLASS_V_MF4_MASK 1285 +#define RISCV_PseudoVFCLASS_V_MF8 1286 +#define RISCV_PseudoVFCLASS_V_MF8_MASK 1287 +#define RISCV_PseudoVFCVT_F_XU_V_M1 1288 +#define RISCV_PseudoVFCVT_F_XU_V_M1_MASK 1289 +#define RISCV_PseudoVFCVT_F_XU_V_M2 1290 +#define RISCV_PseudoVFCVT_F_XU_V_M2_MASK 1291 +#define RISCV_PseudoVFCVT_F_XU_V_M4 1292 +#define RISCV_PseudoVFCVT_F_XU_V_M4_MASK 1293 +#define RISCV_PseudoVFCVT_F_XU_V_M8 1294 +#define RISCV_PseudoVFCVT_F_XU_V_M8_MASK 1295 +#define RISCV_PseudoVFCVT_F_XU_V_MF2 1296 +#define RISCV_PseudoVFCVT_F_XU_V_MF2_MASK 1297 +#define RISCV_PseudoVFCVT_F_XU_V_MF4 1298 +#define RISCV_PseudoVFCVT_F_XU_V_MF4_MASK 1299 +#define RISCV_PseudoVFCVT_F_XU_V_MF8 1300 +#define RISCV_PseudoVFCVT_F_XU_V_MF8_MASK 1301 +#define RISCV_PseudoVFCVT_F_X_V_M1 1302 +#define RISCV_PseudoVFCVT_F_X_V_M1_MASK 1303 +#define RISCV_PseudoVFCVT_F_X_V_M2 1304 +#define RISCV_PseudoVFCVT_F_X_V_M2_MASK 1305 +#define RISCV_PseudoVFCVT_F_X_V_M4 1306 +#define RISCV_PseudoVFCVT_F_X_V_M4_MASK 1307 +#define RISCV_PseudoVFCVT_F_X_V_M8 1308 +#define RISCV_PseudoVFCVT_F_X_V_M8_MASK 1309 +#define RISCV_PseudoVFCVT_F_X_V_MF2 1310 +#define RISCV_PseudoVFCVT_F_X_V_MF2_MASK 1311 +#define RISCV_PseudoVFCVT_F_X_V_MF4 1312 +#define RISCV_PseudoVFCVT_F_X_V_MF4_MASK 1313 +#define RISCV_PseudoVFCVT_F_X_V_MF8 1314 +#define RISCV_PseudoVFCVT_F_X_V_MF8_MASK 1315 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_M1 1316 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_M1_MASK 1317 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_M2 1318 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_M2_MASK 1319 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_M4 1320 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_M4_MASK 1321 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_M8 1322 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_M8_MASK 1323 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_MF2 1324 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_MF2_MASK 1325 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_MF4 1326 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_MF4_MASK 1327 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_MF8 1328 +#define RISCV_PseudoVFCVT_RTZ_XU_F_V_MF8_MASK 1329 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_M1 1330 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_M1_MASK 1331 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_M2 1332 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_M2_MASK 1333 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_M4 1334 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_M4_MASK 1335 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_M8 1336 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_M8_MASK 1337 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_MF2 1338 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_MF2_MASK 1339 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_MF4 1340 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_MF4_MASK 1341 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_MF8 1342 +#define RISCV_PseudoVFCVT_RTZ_X_F_V_MF8_MASK 1343 +#define RISCV_PseudoVFCVT_XU_F_V_M1 1344 +#define RISCV_PseudoVFCVT_XU_F_V_M1_MASK 1345 +#define RISCV_PseudoVFCVT_XU_F_V_M2 1346 +#define RISCV_PseudoVFCVT_XU_F_V_M2_MASK 1347 +#define RISCV_PseudoVFCVT_XU_F_V_M4 1348 +#define RISCV_PseudoVFCVT_XU_F_V_M4_MASK 1349 +#define RISCV_PseudoVFCVT_XU_F_V_M8 1350 +#define RISCV_PseudoVFCVT_XU_F_V_M8_MASK 1351 +#define RISCV_PseudoVFCVT_XU_F_V_MF2 1352 +#define RISCV_PseudoVFCVT_XU_F_V_MF2_MASK 1353 +#define RISCV_PseudoVFCVT_XU_F_V_MF4 1354 +#define RISCV_PseudoVFCVT_XU_F_V_MF4_MASK 1355 +#define RISCV_PseudoVFCVT_XU_F_V_MF8 1356 +#define RISCV_PseudoVFCVT_XU_F_V_MF8_MASK 1357 +#define RISCV_PseudoVFCVT_X_F_V_M1 1358 +#define RISCV_PseudoVFCVT_X_F_V_M1_MASK 1359 +#define RISCV_PseudoVFCVT_X_F_V_M2 1360 +#define RISCV_PseudoVFCVT_X_F_V_M2_MASK 1361 +#define RISCV_PseudoVFCVT_X_F_V_M4 1362 +#define RISCV_PseudoVFCVT_X_F_V_M4_MASK 1363 +#define RISCV_PseudoVFCVT_X_F_V_M8 1364 +#define RISCV_PseudoVFCVT_X_F_V_M8_MASK 1365 +#define RISCV_PseudoVFCVT_X_F_V_MF2 1366 +#define RISCV_PseudoVFCVT_X_F_V_MF2_MASK 1367 +#define RISCV_PseudoVFCVT_X_F_V_MF4 1368 +#define RISCV_PseudoVFCVT_X_F_V_MF4_MASK 1369 +#define RISCV_PseudoVFCVT_X_F_V_MF8 1370 +#define RISCV_PseudoVFCVT_X_F_V_MF8_MASK 1371 +#define RISCV_PseudoVFDIV_VF16_M1 1372 +#define RISCV_PseudoVFDIV_VF16_M1_MASK 1373 +#define RISCV_PseudoVFDIV_VF16_M2 1374 +#define RISCV_PseudoVFDIV_VF16_M2_MASK 1375 +#define RISCV_PseudoVFDIV_VF16_M4 1376 +#define RISCV_PseudoVFDIV_VF16_M4_MASK 1377 +#define RISCV_PseudoVFDIV_VF16_M8 1378 +#define RISCV_PseudoVFDIV_VF16_M8_MASK 1379 +#define RISCV_PseudoVFDIV_VF16_MF2 1380 +#define RISCV_PseudoVFDIV_VF16_MF2_MASK 1381 +#define RISCV_PseudoVFDIV_VF16_MF4 1382 +#define RISCV_PseudoVFDIV_VF16_MF4_MASK 1383 +#define RISCV_PseudoVFDIV_VF16_MF8 1384 +#define RISCV_PseudoVFDIV_VF16_MF8_MASK 1385 +#define RISCV_PseudoVFDIV_VF32_M1 1386 +#define RISCV_PseudoVFDIV_VF32_M1_MASK 1387 +#define RISCV_PseudoVFDIV_VF32_M2 1388 +#define RISCV_PseudoVFDIV_VF32_M2_MASK 1389 +#define RISCV_PseudoVFDIV_VF32_M4 1390 +#define RISCV_PseudoVFDIV_VF32_M4_MASK 1391 +#define RISCV_PseudoVFDIV_VF32_M8 1392 +#define RISCV_PseudoVFDIV_VF32_M8_MASK 1393 +#define RISCV_PseudoVFDIV_VF32_MF2 1394 +#define RISCV_PseudoVFDIV_VF32_MF2_MASK 1395 +#define RISCV_PseudoVFDIV_VF32_MF4 1396 +#define RISCV_PseudoVFDIV_VF32_MF4_MASK 1397 +#define RISCV_PseudoVFDIV_VF32_MF8 1398 +#define RISCV_PseudoVFDIV_VF32_MF8_MASK 1399 +#define RISCV_PseudoVFDIV_VF64_M1 1400 +#define RISCV_PseudoVFDIV_VF64_M1_MASK 1401 +#define RISCV_PseudoVFDIV_VF64_M2 1402 +#define RISCV_PseudoVFDIV_VF64_M2_MASK 1403 +#define RISCV_PseudoVFDIV_VF64_M4 1404 +#define RISCV_PseudoVFDIV_VF64_M4_MASK 1405 +#define RISCV_PseudoVFDIV_VF64_M8 1406 +#define RISCV_PseudoVFDIV_VF64_M8_MASK 1407 +#define RISCV_PseudoVFDIV_VF64_MF2 1408 +#define RISCV_PseudoVFDIV_VF64_MF2_MASK 1409 +#define RISCV_PseudoVFDIV_VF64_MF4 1410 +#define RISCV_PseudoVFDIV_VF64_MF4_MASK 1411 +#define RISCV_PseudoVFDIV_VF64_MF8 1412 +#define RISCV_PseudoVFDIV_VF64_MF8_MASK 1413 +#define RISCV_PseudoVFDIV_VV_M1 1414 +#define RISCV_PseudoVFDIV_VV_M1_MASK 1415 +#define RISCV_PseudoVFDIV_VV_M2 1416 +#define RISCV_PseudoVFDIV_VV_M2_MASK 1417 +#define RISCV_PseudoVFDIV_VV_M4 1418 +#define RISCV_PseudoVFDIV_VV_M4_MASK 1419 +#define RISCV_PseudoVFDIV_VV_M8 1420 +#define RISCV_PseudoVFDIV_VV_M8_MASK 1421 +#define RISCV_PseudoVFDIV_VV_MF2 1422 +#define RISCV_PseudoVFDIV_VV_MF2_MASK 1423 +#define RISCV_PseudoVFDIV_VV_MF4 1424 +#define RISCV_PseudoVFDIV_VV_MF4_MASK 1425 +#define RISCV_PseudoVFDIV_VV_MF8 1426 +#define RISCV_PseudoVFDIV_VV_MF8_MASK 1427 +#define RISCV_PseudoVFIRST_M_B1 1428 +#define RISCV_PseudoVFIRST_M_B16 1429 +#define RISCV_PseudoVFIRST_M_B16_MASK 1430 +#define RISCV_PseudoVFIRST_M_B1_MASK 1431 +#define RISCV_PseudoVFIRST_M_B2 1432 +#define RISCV_PseudoVFIRST_M_B2_MASK 1433 +#define RISCV_PseudoVFIRST_M_B32 1434 +#define RISCV_PseudoVFIRST_M_B32_MASK 1435 +#define RISCV_PseudoVFIRST_M_B4 1436 +#define RISCV_PseudoVFIRST_M_B4_MASK 1437 +#define RISCV_PseudoVFIRST_M_B64 1438 +#define RISCV_PseudoVFIRST_M_B64_MASK 1439 +#define RISCV_PseudoVFIRST_M_B8 1440 +#define RISCV_PseudoVFIRST_M_B8_MASK 1441 +#define RISCV_PseudoVFMACC_VF16_M1 1442 +#define RISCV_PseudoVFMACC_VF16_M1_MASK 1443 +#define RISCV_PseudoVFMACC_VF16_M2 1444 +#define RISCV_PseudoVFMACC_VF16_M2_MASK 1445 +#define RISCV_PseudoVFMACC_VF16_M4 1446 +#define RISCV_PseudoVFMACC_VF16_M4_MASK 1447 +#define RISCV_PseudoVFMACC_VF16_M8 1448 +#define RISCV_PseudoVFMACC_VF16_M8_MASK 1449 +#define RISCV_PseudoVFMACC_VF16_MF2 1450 +#define RISCV_PseudoVFMACC_VF16_MF2_MASK 1451 +#define RISCV_PseudoVFMACC_VF16_MF4 1452 +#define RISCV_PseudoVFMACC_VF16_MF4_MASK 1453 +#define RISCV_PseudoVFMACC_VF16_MF8 1454 +#define RISCV_PseudoVFMACC_VF16_MF8_MASK 1455 +#define RISCV_PseudoVFMACC_VF32_M1 1456 +#define RISCV_PseudoVFMACC_VF32_M1_MASK 1457 +#define RISCV_PseudoVFMACC_VF32_M2 1458 +#define RISCV_PseudoVFMACC_VF32_M2_MASK 1459 +#define RISCV_PseudoVFMACC_VF32_M4 1460 +#define RISCV_PseudoVFMACC_VF32_M4_MASK 1461 +#define RISCV_PseudoVFMACC_VF32_M8 1462 +#define RISCV_PseudoVFMACC_VF32_M8_MASK 1463 +#define RISCV_PseudoVFMACC_VF32_MF2 1464 +#define RISCV_PseudoVFMACC_VF32_MF2_MASK 1465 +#define RISCV_PseudoVFMACC_VF32_MF4 1466 +#define RISCV_PseudoVFMACC_VF32_MF4_MASK 1467 +#define RISCV_PseudoVFMACC_VF32_MF8 1468 +#define RISCV_PseudoVFMACC_VF32_MF8_MASK 1469 +#define RISCV_PseudoVFMACC_VF64_M1 1470 +#define RISCV_PseudoVFMACC_VF64_M1_MASK 1471 +#define RISCV_PseudoVFMACC_VF64_M2 1472 +#define RISCV_PseudoVFMACC_VF64_M2_MASK 1473 +#define RISCV_PseudoVFMACC_VF64_M4 1474 +#define RISCV_PseudoVFMACC_VF64_M4_MASK 1475 +#define RISCV_PseudoVFMACC_VF64_M8 1476 +#define RISCV_PseudoVFMACC_VF64_M8_MASK 1477 +#define RISCV_PseudoVFMACC_VF64_MF2 1478 +#define RISCV_PseudoVFMACC_VF64_MF2_MASK 1479 +#define RISCV_PseudoVFMACC_VF64_MF4 1480 +#define RISCV_PseudoVFMACC_VF64_MF4_MASK 1481 +#define RISCV_PseudoVFMACC_VF64_MF8 1482 +#define RISCV_PseudoVFMACC_VF64_MF8_MASK 1483 +#define RISCV_PseudoVFMACC_VV_M1 1484 +#define RISCV_PseudoVFMACC_VV_M1_MASK 1485 +#define RISCV_PseudoVFMACC_VV_M2 1486 +#define RISCV_PseudoVFMACC_VV_M2_MASK 1487 +#define RISCV_PseudoVFMACC_VV_M4 1488 +#define RISCV_PseudoVFMACC_VV_M4_MASK 1489 +#define RISCV_PseudoVFMACC_VV_M8 1490 +#define RISCV_PseudoVFMACC_VV_M8_MASK 1491 +#define RISCV_PseudoVFMACC_VV_MF2 1492 +#define RISCV_PseudoVFMACC_VV_MF2_MASK 1493 +#define RISCV_PseudoVFMACC_VV_MF4 1494 +#define RISCV_PseudoVFMACC_VV_MF4_MASK 1495 +#define RISCV_PseudoVFMACC_VV_MF8 1496 +#define RISCV_PseudoVFMACC_VV_MF8_MASK 1497 +#define RISCV_PseudoVFMADD_VF16_M1 1498 +#define RISCV_PseudoVFMADD_VF16_M1_MASK 1499 +#define RISCV_PseudoVFMADD_VF16_M2 1500 +#define RISCV_PseudoVFMADD_VF16_M2_MASK 1501 +#define RISCV_PseudoVFMADD_VF16_M4 1502 +#define RISCV_PseudoVFMADD_VF16_M4_MASK 1503 +#define RISCV_PseudoVFMADD_VF16_M8 1504 +#define RISCV_PseudoVFMADD_VF16_M8_MASK 1505 +#define RISCV_PseudoVFMADD_VF16_MF2 1506 +#define RISCV_PseudoVFMADD_VF16_MF2_MASK 1507 +#define RISCV_PseudoVFMADD_VF16_MF4 1508 +#define RISCV_PseudoVFMADD_VF16_MF4_MASK 1509 +#define RISCV_PseudoVFMADD_VF16_MF8 1510 +#define RISCV_PseudoVFMADD_VF16_MF8_MASK 1511 +#define RISCV_PseudoVFMADD_VF32_M1 1512 +#define RISCV_PseudoVFMADD_VF32_M1_MASK 1513 +#define RISCV_PseudoVFMADD_VF32_M2 1514 +#define RISCV_PseudoVFMADD_VF32_M2_MASK 1515 +#define RISCV_PseudoVFMADD_VF32_M4 1516 +#define RISCV_PseudoVFMADD_VF32_M4_MASK 1517 +#define RISCV_PseudoVFMADD_VF32_M8 1518 +#define RISCV_PseudoVFMADD_VF32_M8_MASK 1519 +#define RISCV_PseudoVFMADD_VF32_MF2 1520 +#define RISCV_PseudoVFMADD_VF32_MF2_MASK 1521 +#define RISCV_PseudoVFMADD_VF32_MF4 1522 +#define RISCV_PseudoVFMADD_VF32_MF4_MASK 1523 +#define RISCV_PseudoVFMADD_VF32_MF8 1524 +#define RISCV_PseudoVFMADD_VF32_MF8_MASK 1525 +#define RISCV_PseudoVFMADD_VF64_M1 1526 +#define RISCV_PseudoVFMADD_VF64_M1_MASK 1527 +#define RISCV_PseudoVFMADD_VF64_M2 1528 +#define RISCV_PseudoVFMADD_VF64_M2_MASK 1529 +#define RISCV_PseudoVFMADD_VF64_M4 1530 +#define RISCV_PseudoVFMADD_VF64_M4_MASK 1531 +#define RISCV_PseudoVFMADD_VF64_M8 1532 +#define RISCV_PseudoVFMADD_VF64_M8_MASK 1533 +#define RISCV_PseudoVFMADD_VF64_MF2 1534 +#define RISCV_PseudoVFMADD_VF64_MF2_MASK 1535 +#define RISCV_PseudoVFMADD_VF64_MF4 1536 +#define RISCV_PseudoVFMADD_VF64_MF4_MASK 1537 +#define RISCV_PseudoVFMADD_VF64_MF8 1538 +#define RISCV_PseudoVFMADD_VF64_MF8_MASK 1539 +#define RISCV_PseudoVFMADD_VV_M1 1540 +#define RISCV_PseudoVFMADD_VV_M1_MASK 1541 +#define RISCV_PseudoVFMADD_VV_M2 1542 +#define RISCV_PseudoVFMADD_VV_M2_MASK 1543 +#define RISCV_PseudoVFMADD_VV_M4 1544 +#define RISCV_PseudoVFMADD_VV_M4_MASK 1545 +#define RISCV_PseudoVFMADD_VV_M8 1546 +#define RISCV_PseudoVFMADD_VV_M8_MASK 1547 +#define RISCV_PseudoVFMADD_VV_MF2 1548 +#define RISCV_PseudoVFMADD_VV_MF2_MASK 1549 +#define RISCV_PseudoVFMADD_VV_MF4 1550 +#define RISCV_PseudoVFMADD_VV_MF4_MASK 1551 +#define RISCV_PseudoVFMADD_VV_MF8 1552 +#define RISCV_PseudoVFMADD_VV_MF8_MASK 1553 +#define RISCV_PseudoVFMAX_VF16_M1 1554 +#define RISCV_PseudoVFMAX_VF16_M1_MASK 1555 +#define RISCV_PseudoVFMAX_VF16_M2 1556 +#define RISCV_PseudoVFMAX_VF16_M2_MASK 1557 +#define RISCV_PseudoVFMAX_VF16_M4 1558 +#define RISCV_PseudoVFMAX_VF16_M4_MASK 1559 +#define RISCV_PseudoVFMAX_VF16_M8 1560 +#define RISCV_PseudoVFMAX_VF16_M8_MASK 1561 +#define RISCV_PseudoVFMAX_VF16_MF2 1562 +#define RISCV_PseudoVFMAX_VF16_MF2_MASK 1563 +#define RISCV_PseudoVFMAX_VF16_MF4 1564 +#define RISCV_PseudoVFMAX_VF16_MF4_MASK 1565 +#define RISCV_PseudoVFMAX_VF16_MF8 1566 +#define RISCV_PseudoVFMAX_VF16_MF8_MASK 1567 +#define RISCV_PseudoVFMAX_VF32_M1 1568 +#define RISCV_PseudoVFMAX_VF32_M1_MASK 1569 +#define RISCV_PseudoVFMAX_VF32_M2 1570 +#define RISCV_PseudoVFMAX_VF32_M2_MASK 1571 +#define RISCV_PseudoVFMAX_VF32_M4 1572 +#define RISCV_PseudoVFMAX_VF32_M4_MASK 1573 +#define RISCV_PseudoVFMAX_VF32_M8 1574 +#define RISCV_PseudoVFMAX_VF32_M8_MASK 1575 +#define RISCV_PseudoVFMAX_VF32_MF2 1576 +#define RISCV_PseudoVFMAX_VF32_MF2_MASK 1577 +#define RISCV_PseudoVFMAX_VF32_MF4 1578 +#define RISCV_PseudoVFMAX_VF32_MF4_MASK 1579 +#define RISCV_PseudoVFMAX_VF32_MF8 1580 +#define RISCV_PseudoVFMAX_VF32_MF8_MASK 1581 +#define RISCV_PseudoVFMAX_VF64_M1 1582 +#define RISCV_PseudoVFMAX_VF64_M1_MASK 1583 +#define RISCV_PseudoVFMAX_VF64_M2 1584 +#define RISCV_PseudoVFMAX_VF64_M2_MASK 1585 +#define RISCV_PseudoVFMAX_VF64_M4 1586 +#define RISCV_PseudoVFMAX_VF64_M4_MASK 1587 +#define RISCV_PseudoVFMAX_VF64_M8 1588 +#define RISCV_PseudoVFMAX_VF64_M8_MASK 1589 +#define RISCV_PseudoVFMAX_VF64_MF2 1590 +#define RISCV_PseudoVFMAX_VF64_MF2_MASK 1591 +#define RISCV_PseudoVFMAX_VF64_MF4 1592 +#define RISCV_PseudoVFMAX_VF64_MF4_MASK 1593 +#define RISCV_PseudoVFMAX_VF64_MF8 1594 +#define RISCV_PseudoVFMAX_VF64_MF8_MASK 1595 +#define RISCV_PseudoVFMAX_VV_M1 1596 +#define RISCV_PseudoVFMAX_VV_M1_MASK 1597 +#define RISCV_PseudoVFMAX_VV_M2 1598 +#define RISCV_PseudoVFMAX_VV_M2_MASK 1599 +#define RISCV_PseudoVFMAX_VV_M4 1600 +#define RISCV_PseudoVFMAX_VV_M4_MASK 1601 +#define RISCV_PseudoVFMAX_VV_M8 1602 +#define RISCV_PseudoVFMAX_VV_M8_MASK 1603 +#define RISCV_PseudoVFMAX_VV_MF2 1604 +#define RISCV_PseudoVFMAX_VV_MF2_MASK 1605 +#define RISCV_PseudoVFMAX_VV_MF4 1606 +#define RISCV_PseudoVFMAX_VV_MF4_MASK 1607 +#define RISCV_PseudoVFMAX_VV_MF8 1608 +#define RISCV_PseudoVFMAX_VV_MF8_MASK 1609 +#define RISCV_PseudoVFMERGE_VF16M_M1 1610 +#define RISCV_PseudoVFMERGE_VF16M_M2 1611 +#define RISCV_PseudoVFMERGE_VF16M_M4 1612 +#define RISCV_PseudoVFMERGE_VF16M_M8 1613 +#define RISCV_PseudoVFMERGE_VF16M_MF2 1614 +#define RISCV_PseudoVFMERGE_VF16M_MF4 1615 +#define RISCV_PseudoVFMERGE_VF16M_MF8 1616 +#define RISCV_PseudoVFMERGE_VF32M_M1 1617 +#define RISCV_PseudoVFMERGE_VF32M_M2 1618 +#define RISCV_PseudoVFMERGE_VF32M_M4 1619 +#define RISCV_PseudoVFMERGE_VF32M_M8 1620 +#define RISCV_PseudoVFMERGE_VF32M_MF2 1621 +#define RISCV_PseudoVFMERGE_VF32M_MF4 1622 +#define RISCV_PseudoVFMERGE_VF32M_MF8 1623 +#define RISCV_PseudoVFMERGE_VF64M_M1 1624 +#define RISCV_PseudoVFMERGE_VF64M_M2 1625 +#define RISCV_PseudoVFMERGE_VF64M_M4 1626 +#define RISCV_PseudoVFMERGE_VF64M_M8 1627 +#define RISCV_PseudoVFMERGE_VF64M_MF2 1628 +#define RISCV_PseudoVFMERGE_VF64M_MF4 1629 +#define RISCV_PseudoVFMERGE_VF64M_MF8 1630 +#define RISCV_PseudoVFMIN_VF16_M1 1631 +#define RISCV_PseudoVFMIN_VF16_M1_MASK 1632 +#define RISCV_PseudoVFMIN_VF16_M2 1633 +#define RISCV_PseudoVFMIN_VF16_M2_MASK 1634 +#define RISCV_PseudoVFMIN_VF16_M4 1635 +#define RISCV_PseudoVFMIN_VF16_M4_MASK 1636 +#define RISCV_PseudoVFMIN_VF16_M8 1637 +#define RISCV_PseudoVFMIN_VF16_M8_MASK 1638 +#define RISCV_PseudoVFMIN_VF16_MF2 1639 +#define RISCV_PseudoVFMIN_VF16_MF2_MASK 1640 +#define RISCV_PseudoVFMIN_VF16_MF4 1641 +#define RISCV_PseudoVFMIN_VF16_MF4_MASK 1642 +#define RISCV_PseudoVFMIN_VF16_MF8 1643 +#define RISCV_PseudoVFMIN_VF16_MF8_MASK 1644 +#define RISCV_PseudoVFMIN_VF32_M1 1645 +#define RISCV_PseudoVFMIN_VF32_M1_MASK 1646 +#define RISCV_PseudoVFMIN_VF32_M2 1647 +#define RISCV_PseudoVFMIN_VF32_M2_MASK 1648 +#define RISCV_PseudoVFMIN_VF32_M4 1649 +#define RISCV_PseudoVFMIN_VF32_M4_MASK 1650 +#define RISCV_PseudoVFMIN_VF32_M8 1651 +#define RISCV_PseudoVFMIN_VF32_M8_MASK 1652 +#define RISCV_PseudoVFMIN_VF32_MF2 1653 +#define RISCV_PseudoVFMIN_VF32_MF2_MASK 1654 +#define RISCV_PseudoVFMIN_VF32_MF4 1655 +#define RISCV_PseudoVFMIN_VF32_MF4_MASK 1656 +#define RISCV_PseudoVFMIN_VF32_MF8 1657 +#define RISCV_PseudoVFMIN_VF32_MF8_MASK 1658 +#define RISCV_PseudoVFMIN_VF64_M1 1659 +#define RISCV_PseudoVFMIN_VF64_M1_MASK 1660 +#define RISCV_PseudoVFMIN_VF64_M2 1661 +#define RISCV_PseudoVFMIN_VF64_M2_MASK 1662 +#define RISCV_PseudoVFMIN_VF64_M4 1663 +#define RISCV_PseudoVFMIN_VF64_M4_MASK 1664 +#define RISCV_PseudoVFMIN_VF64_M8 1665 +#define RISCV_PseudoVFMIN_VF64_M8_MASK 1666 +#define RISCV_PseudoVFMIN_VF64_MF2 1667 +#define RISCV_PseudoVFMIN_VF64_MF2_MASK 1668 +#define RISCV_PseudoVFMIN_VF64_MF4 1669 +#define RISCV_PseudoVFMIN_VF64_MF4_MASK 1670 +#define RISCV_PseudoVFMIN_VF64_MF8 1671 +#define RISCV_PseudoVFMIN_VF64_MF8_MASK 1672 +#define RISCV_PseudoVFMIN_VV_M1 1673 +#define RISCV_PseudoVFMIN_VV_M1_MASK 1674 +#define RISCV_PseudoVFMIN_VV_M2 1675 +#define RISCV_PseudoVFMIN_VV_M2_MASK 1676 +#define RISCV_PseudoVFMIN_VV_M4 1677 +#define RISCV_PseudoVFMIN_VV_M4_MASK 1678 +#define RISCV_PseudoVFMIN_VV_M8 1679 +#define RISCV_PseudoVFMIN_VV_M8_MASK 1680 +#define RISCV_PseudoVFMIN_VV_MF2 1681 +#define RISCV_PseudoVFMIN_VV_MF2_MASK 1682 +#define RISCV_PseudoVFMIN_VV_MF4 1683 +#define RISCV_PseudoVFMIN_VV_MF4_MASK 1684 +#define RISCV_PseudoVFMIN_VV_MF8 1685 +#define RISCV_PseudoVFMIN_VV_MF8_MASK 1686 +#define RISCV_PseudoVFMSAC_VF16_M1 1687 +#define RISCV_PseudoVFMSAC_VF16_M1_MASK 1688 +#define RISCV_PseudoVFMSAC_VF16_M2 1689 +#define RISCV_PseudoVFMSAC_VF16_M2_MASK 1690 +#define RISCV_PseudoVFMSAC_VF16_M4 1691 +#define RISCV_PseudoVFMSAC_VF16_M4_MASK 1692 +#define RISCV_PseudoVFMSAC_VF16_M8 1693 +#define RISCV_PseudoVFMSAC_VF16_M8_MASK 1694 +#define RISCV_PseudoVFMSAC_VF16_MF2 1695 +#define RISCV_PseudoVFMSAC_VF16_MF2_MASK 1696 +#define RISCV_PseudoVFMSAC_VF16_MF4 1697 +#define RISCV_PseudoVFMSAC_VF16_MF4_MASK 1698 +#define RISCV_PseudoVFMSAC_VF16_MF8 1699 +#define RISCV_PseudoVFMSAC_VF16_MF8_MASK 1700 +#define RISCV_PseudoVFMSAC_VF32_M1 1701 +#define RISCV_PseudoVFMSAC_VF32_M1_MASK 1702 +#define RISCV_PseudoVFMSAC_VF32_M2 1703 +#define RISCV_PseudoVFMSAC_VF32_M2_MASK 1704 +#define RISCV_PseudoVFMSAC_VF32_M4 1705 +#define RISCV_PseudoVFMSAC_VF32_M4_MASK 1706 +#define RISCV_PseudoVFMSAC_VF32_M8 1707 +#define RISCV_PseudoVFMSAC_VF32_M8_MASK 1708 +#define RISCV_PseudoVFMSAC_VF32_MF2 1709 +#define RISCV_PseudoVFMSAC_VF32_MF2_MASK 1710 +#define RISCV_PseudoVFMSAC_VF32_MF4 1711 +#define RISCV_PseudoVFMSAC_VF32_MF4_MASK 1712 +#define RISCV_PseudoVFMSAC_VF32_MF8 1713 +#define RISCV_PseudoVFMSAC_VF32_MF8_MASK 1714 +#define RISCV_PseudoVFMSAC_VF64_M1 1715 +#define RISCV_PseudoVFMSAC_VF64_M1_MASK 1716 +#define RISCV_PseudoVFMSAC_VF64_M2 1717 +#define RISCV_PseudoVFMSAC_VF64_M2_MASK 1718 +#define RISCV_PseudoVFMSAC_VF64_M4 1719 +#define RISCV_PseudoVFMSAC_VF64_M4_MASK 1720 +#define RISCV_PseudoVFMSAC_VF64_M8 1721 +#define RISCV_PseudoVFMSAC_VF64_M8_MASK 1722 +#define RISCV_PseudoVFMSAC_VF64_MF2 1723 +#define RISCV_PseudoVFMSAC_VF64_MF2_MASK 1724 +#define RISCV_PseudoVFMSAC_VF64_MF4 1725 +#define RISCV_PseudoVFMSAC_VF64_MF4_MASK 1726 +#define RISCV_PseudoVFMSAC_VF64_MF8 1727 +#define RISCV_PseudoVFMSAC_VF64_MF8_MASK 1728 +#define RISCV_PseudoVFMSAC_VV_M1 1729 +#define RISCV_PseudoVFMSAC_VV_M1_MASK 1730 +#define RISCV_PseudoVFMSAC_VV_M2 1731 +#define RISCV_PseudoVFMSAC_VV_M2_MASK 1732 +#define RISCV_PseudoVFMSAC_VV_M4 1733 +#define RISCV_PseudoVFMSAC_VV_M4_MASK 1734 +#define RISCV_PseudoVFMSAC_VV_M8 1735 +#define RISCV_PseudoVFMSAC_VV_M8_MASK 1736 +#define RISCV_PseudoVFMSAC_VV_MF2 1737 +#define RISCV_PseudoVFMSAC_VV_MF2_MASK 1738 +#define RISCV_PseudoVFMSAC_VV_MF4 1739 +#define RISCV_PseudoVFMSAC_VV_MF4_MASK 1740 +#define RISCV_PseudoVFMSAC_VV_MF8 1741 +#define RISCV_PseudoVFMSAC_VV_MF8_MASK 1742 +#define RISCV_PseudoVFMSUB_VF16_M1 1743 +#define RISCV_PseudoVFMSUB_VF16_M1_MASK 1744 +#define RISCV_PseudoVFMSUB_VF16_M2 1745 +#define RISCV_PseudoVFMSUB_VF16_M2_MASK 1746 +#define RISCV_PseudoVFMSUB_VF16_M4 1747 +#define RISCV_PseudoVFMSUB_VF16_M4_MASK 1748 +#define RISCV_PseudoVFMSUB_VF16_M8 1749 +#define RISCV_PseudoVFMSUB_VF16_M8_MASK 1750 +#define RISCV_PseudoVFMSUB_VF16_MF2 1751 +#define RISCV_PseudoVFMSUB_VF16_MF2_MASK 1752 +#define RISCV_PseudoVFMSUB_VF16_MF4 1753 +#define RISCV_PseudoVFMSUB_VF16_MF4_MASK 1754 +#define RISCV_PseudoVFMSUB_VF16_MF8 1755 +#define RISCV_PseudoVFMSUB_VF16_MF8_MASK 1756 +#define RISCV_PseudoVFMSUB_VF32_M1 1757 +#define RISCV_PseudoVFMSUB_VF32_M1_MASK 1758 +#define RISCV_PseudoVFMSUB_VF32_M2 1759 +#define RISCV_PseudoVFMSUB_VF32_M2_MASK 1760 +#define RISCV_PseudoVFMSUB_VF32_M4 1761 +#define RISCV_PseudoVFMSUB_VF32_M4_MASK 1762 +#define RISCV_PseudoVFMSUB_VF32_M8 1763 +#define RISCV_PseudoVFMSUB_VF32_M8_MASK 1764 +#define RISCV_PseudoVFMSUB_VF32_MF2 1765 +#define RISCV_PseudoVFMSUB_VF32_MF2_MASK 1766 +#define RISCV_PseudoVFMSUB_VF32_MF4 1767 +#define RISCV_PseudoVFMSUB_VF32_MF4_MASK 1768 +#define RISCV_PseudoVFMSUB_VF32_MF8 1769 +#define RISCV_PseudoVFMSUB_VF32_MF8_MASK 1770 +#define RISCV_PseudoVFMSUB_VF64_M1 1771 +#define RISCV_PseudoVFMSUB_VF64_M1_MASK 1772 +#define RISCV_PseudoVFMSUB_VF64_M2 1773 +#define RISCV_PseudoVFMSUB_VF64_M2_MASK 1774 +#define RISCV_PseudoVFMSUB_VF64_M4 1775 +#define RISCV_PseudoVFMSUB_VF64_M4_MASK 1776 +#define RISCV_PseudoVFMSUB_VF64_M8 1777 +#define RISCV_PseudoVFMSUB_VF64_M8_MASK 1778 +#define RISCV_PseudoVFMSUB_VF64_MF2 1779 +#define RISCV_PseudoVFMSUB_VF64_MF2_MASK 1780 +#define RISCV_PseudoVFMSUB_VF64_MF4 1781 +#define RISCV_PseudoVFMSUB_VF64_MF4_MASK 1782 +#define RISCV_PseudoVFMSUB_VF64_MF8 1783 +#define RISCV_PseudoVFMSUB_VF64_MF8_MASK 1784 +#define RISCV_PseudoVFMSUB_VV_M1 1785 +#define RISCV_PseudoVFMSUB_VV_M1_MASK 1786 +#define RISCV_PseudoVFMSUB_VV_M2 1787 +#define RISCV_PseudoVFMSUB_VV_M2_MASK 1788 +#define RISCV_PseudoVFMSUB_VV_M4 1789 +#define RISCV_PseudoVFMSUB_VV_M4_MASK 1790 +#define RISCV_PseudoVFMSUB_VV_M8 1791 +#define RISCV_PseudoVFMSUB_VV_M8_MASK 1792 +#define RISCV_PseudoVFMSUB_VV_MF2 1793 +#define RISCV_PseudoVFMSUB_VV_MF2_MASK 1794 +#define RISCV_PseudoVFMSUB_VV_MF4 1795 +#define RISCV_PseudoVFMSUB_VV_MF4_MASK 1796 +#define RISCV_PseudoVFMSUB_VV_MF8 1797 +#define RISCV_PseudoVFMSUB_VV_MF8_MASK 1798 +#define RISCV_PseudoVFMUL_VF16_M1 1799 +#define RISCV_PseudoVFMUL_VF16_M1_MASK 1800 +#define RISCV_PseudoVFMUL_VF16_M2 1801 +#define RISCV_PseudoVFMUL_VF16_M2_MASK 1802 +#define RISCV_PseudoVFMUL_VF16_M4 1803 +#define RISCV_PseudoVFMUL_VF16_M4_MASK 1804 +#define RISCV_PseudoVFMUL_VF16_M8 1805 +#define RISCV_PseudoVFMUL_VF16_M8_MASK 1806 +#define RISCV_PseudoVFMUL_VF16_MF2 1807 +#define RISCV_PseudoVFMUL_VF16_MF2_MASK 1808 +#define RISCV_PseudoVFMUL_VF16_MF4 1809 +#define RISCV_PseudoVFMUL_VF16_MF4_MASK 1810 +#define RISCV_PseudoVFMUL_VF16_MF8 1811 +#define RISCV_PseudoVFMUL_VF16_MF8_MASK 1812 +#define RISCV_PseudoVFMUL_VF32_M1 1813 +#define RISCV_PseudoVFMUL_VF32_M1_MASK 1814 +#define RISCV_PseudoVFMUL_VF32_M2 1815 +#define RISCV_PseudoVFMUL_VF32_M2_MASK 1816 +#define RISCV_PseudoVFMUL_VF32_M4 1817 +#define RISCV_PseudoVFMUL_VF32_M4_MASK 1818 +#define RISCV_PseudoVFMUL_VF32_M8 1819 +#define RISCV_PseudoVFMUL_VF32_M8_MASK 1820 +#define RISCV_PseudoVFMUL_VF32_MF2 1821 +#define RISCV_PseudoVFMUL_VF32_MF2_MASK 1822 +#define RISCV_PseudoVFMUL_VF32_MF4 1823 +#define RISCV_PseudoVFMUL_VF32_MF4_MASK 1824 +#define RISCV_PseudoVFMUL_VF32_MF8 1825 +#define RISCV_PseudoVFMUL_VF32_MF8_MASK 1826 +#define RISCV_PseudoVFMUL_VF64_M1 1827 +#define RISCV_PseudoVFMUL_VF64_M1_MASK 1828 +#define RISCV_PseudoVFMUL_VF64_M2 1829 +#define RISCV_PseudoVFMUL_VF64_M2_MASK 1830 +#define RISCV_PseudoVFMUL_VF64_M4 1831 +#define RISCV_PseudoVFMUL_VF64_M4_MASK 1832 +#define RISCV_PseudoVFMUL_VF64_M8 1833 +#define RISCV_PseudoVFMUL_VF64_M8_MASK 1834 +#define RISCV_PseudoVFMUL_VF64_MF2 1835 +#define RISCV_PseudoVFMUL_VF64_MF2_MASK 1836 +#define RISCV_PseudoVFMUL_VF64_MF4 1837 +#define RISCV_PseudoVFMUL_VF64_MF4_MASK 1838 +#define RISCV_PseudoVFMUL_VF64_MF8 1839 +#define RISCV_PseudoVFMUL_VF64_MF8_MASK 1840 +#define RISCV_PseudoVFMUL_VV_M1 1841 +#define RISCV_PseudoVFMUL_VV_M1_MASK 1842 +#define RISCV_PseudoVFMUL_VV_M2 1843 +#define RISCV_PseudoVFMUL_VV_M2_MASK 1844 +#define RISCV_PseudoVFMUL_VV_M4 1845 +#define RISCV_PseudoVFMUL_VV_M4_MASK 1846 +#define RISCV_PseudoVFMUL_VV_M8 1847 +#define RISCV_PseudoVFMUL_VV_M8_MASK 1848 +#define RISCV_PseudoVFMUL_VV_MF2 1849 +#define RISCV_PseudoVFMUL_VV_MF2_MASK 1850 +#define RISCV_PseudoVFMUL_VV_MF4 1851 +#define RISCV_PseudoVFMUL_VV_MF4_MASK 1852 +#define RISCV_PseudoVFMUL_VV_MF8 1853 +#define RISCV_PseudoVFMUL_VV_MF8_MASK 1854 +#define RISCV_PseudoVFMV_F16_S_M1 1855 +#define RISCV_PseudoVFMV_F16_S_M2 1856 +#define RISCV_PseudoVFMV_F16_S_M4 1857 +#define RISCV_PseudoVFMV_F16_S_M8 1858 +#define RISCV_PseudoVFMV_F16_S_MF2 1859 +#define RISCV_PseudoVFMV_F16_S_MF4 1860 +#define RISCV_PseudoVFMV_F16_S_MF8 1861 +#define RISCV_PseudoVFMV_F32_S_M1 1862 +#define RISCV_PseudoVFMV_F32_S_M2 1863 +#define RISCV_PseudoVFMV_F32_S_M4 1864 +#define RISCV_PseudoVFMV_F32_S_M8 1865 +#define RISCV_PseudoVFMV_F32_S_MF2 1866 +#define RISCV_PseudoVFMV_F32_S_MF4 1867 +#define RISCV_PseudoVFMV_F32_S_MF8 1868 +#define RISCV_PseudoVFMV_F64_S_M1 1869 +#define RISCV_PseudoVFMV_F64_S_M2 1870 +#define RISCV_PseudoVFMV_F64_S_M4 1871 +#define RISCV_PseudoVFMV_F64_S_M8 1872 +#define RISCV_PseudoVFMV_F64_S_MF2 1873 +#define RISCV_PseudoVFMV_F64_S_MF4 1874 +#define RISCV_PseudoVFMV_F64_S_MF8 1875 +#define RISCV_PseudoVFMV_S_F16_M1 1876 +#define RISCV_PseudoVFMV_S_F16_M2 1877 +#define RISCV_PseudoVFMV_S_F16_M4 1878 +#define RISCV_PseudoVFMV_S_F16_M8 1879 +#define RISCV_PseudoVFMV_S_F16_MF2 1880 +#define RISCV_PseudoVFMV_S_F16_MF4 1881 +#define RISCV_PseudoVFMV_S_F16_MF8 1882 +#define RISCV_PseudoVFMV_S_F32_M1 1883 +#define RISCV_PseudoVFMV_S_F32_M2 1884 +#define RISCV_PseudoVFMV_S_F32_M4 1885 +#define RISCV_PseudoVFMV_S_F32_M8 1886 +#define RISCV_PseudoVFMV_S_F32_MF2 1887 +#define RISCV_PseudoVFMV_S_F32_MF4 1888 +#define RISCV_PseudoVFMV_S_F32_MF8 1889 +#define RISCV_PseudoVFMV_S_F64_M1 1890 +#define RISCV_PseudoVFMV_S_F64_M2 1891 +#define RISCV_PseudoVFMV_S_F64_M4 1892 +#define RISCV_PseudoVFMV_S_F64_M8 1893 +#define RISCV_PseudoVFMV_S_F64_MF2 1894 +#define RISCV_PseudoVFMV_S_F64_MF4 1895 +#define RISCV_PseudoVFMV_S_F64_MF8 1896 +#define RISCV_PseudoVFMV_V_F16_M1 1897 +#define RISCV_PseudoVFMV_V_F16_M2 1898 +#define RISCV_PseudoVFMV_V_F16_M4 1899 +#define RISCV_PseudoVFMV_V_F16_M8 1900 +#define RISCV_PseudoVFMV_V_F16_MF2 1901 +#define RISCV_PseudoVFMV_V_F16_MF4 1902 +#define RISCV_PseudoVFMV_V_F16_MF8 1903 +#define RISCV_PseudoVFMV_V_F32_M1 1904 +#define RISCV_PseudoVFMV_V_F32_M2 1905 +#define RISCV_PseudoVFMV_V_F32_M4 1906 +#define RISCV_PseudoVFMV_V_F32_M8 1907 +#define RISCV_PseudoVFMV_V_F32_MF2 1908 +#define RISCV_PseudoVFMV_V_F32_MF4 1909 +#define RISCV_PseudoVFMV_V_F32_MF8 1910 +#define RISCV_PseudoVFMV_V_F64_M1 1911 +#define RISCV_PseudoVFMV_V_F64_M2 1912 +#define RISCV_PseudoVFMV_V_F64_M4 1913 +#define RISCV_PseudoVFMV_V_F64_M8 1914 +#define RISCV_PseudoVFMV_V_F64_MF2 1915 +#define RISCV_PseudoVFMV_V_F64_MF4 1916 +#define RISCV_PseudoVFMV_V_F64_MF8 1917 +#define RISCV_PseudoVFNCVT_F_F_W_M1 1918 +#define RISCV_PseudoVFNCVT_F_F_W_M1_MASK 1919 +#define RISCV_PseudoVFNCVT_F_F_W_M2 1920 +#define RISCV_PseudoVFNCVT_F_F_W_M2_MASK 1921 +#define RISCV_PseudoVFNCVT_F_F_W_M4 1922 +#define RISCV_PseudoVFNCVT_F_F_W_M4_MASK 1923 +#define RISCV_PseudoVFNCVT_F_F_W_MF2 1924 +#define RISCV_PseudoVFNCVT_F_F_W_MF2_MASK 1925 +#define RISCV_PseudoVFNCVT_F_F_W_MF4 1926 +#define RISCV_PseudoVFNCVT_F_F_W_MF4_MASK 1927 +#define RISCV_PseudoVFNCVT_F_F_W_MF8 1928 +#define RISCV_PseudoVFNCVT_F_F_W_MF8_MASK 1929 +#define RISCV_PseudoVFNCVT_F_XU_W_M1 1930 +#define RISCV_PseudoVFNCVT_F_XU_W_M1_MASK 1931 +#define RISCV_PseudoVFNCVT_F_XU_W_M2 1932 +#define RISCV_PseudoVFNCVT_F_XU_W_M2_MASK 1933 +#define RISCV_PseudoVFNCVT_F_XU_W_M4 1934 +#define RISCV_PseudoVFNCVT_F_XU_W_M4_MASK 1935 +#define RISCV_PseudoVFNCVT_F_XU_W_MF2 1936 +#define RISCV_PseudoVFNCVT_F_XU_W_MF2_MASK 1937 +#define RISCV_PseudoVFNCVT_F_XU_W_MF4 1938 +#define RISCV_PseudoVFNCVT_F_XU_W_MF4_MASK 1939 +#define RISCV_PseudoVFNCVT_F_XU_W_MF8 1940 +#define RISCV_PseudoVFNCVT_F_XU_W_MF8_MASK 1941 +#define RISCV_PseudoVFNCVT_F_X_W_M1 1942 +#define RISCV_PseudoVFNCVT_F_X_W_M1_MASK 1943 +#define RISCV_PseudoVFNCVT_F_X_W_M2 1944 +#define RISCV_PseudoVFNCVT_F_X_W_M2_MASK 1945 +#define RISCV_PseudoVFNCVT_F_X_W_M4 1946 +#define RISCV_PseudoVFNCVT_F_X_W_M4_MASK 1947 +#define RISCV_PseudoVFNCVT_F_X_W_MF2 1948 +#define RISCV_PseudoVFNCVT_F_X_W_MF2_MASK 1949 +#define RISCV_PseudoVFNCVT_F_X_W_MF4 1950 +#define RISCV_PseudoVFNCVT_F_X_W_MF4_MASK 1951 +#define RISCV_PseudoVFNCVT_F_X_W_MF8 1952 +#define RISCV_PseudoVFNCVT_F_X_W_MF8_MASK 1953 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_M1 1954 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_M1_MASK 1955 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_M2 1956 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_M2_MASK 1957 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_M4 1958 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_M4_MASK 1959 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_MF2 1960 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_MF2_MASK 1961 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_MF4 1962 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_MF4_MASK 1963 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_MF8 1964 +#define RISCV_PseudoVFNCVT_ROD_F_F_W_MF8_MASK 1965 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_M1 1966 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_M1_MASK 1967 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_M2 1968 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_M2_MASK 1969 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_M4 1970 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_M4_MASK 1971 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_MF2 1972 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK 1973 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_MF4 1974 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK 1975 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_MF8 1976 +#define RISCV_PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK 1977 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_M1 1978 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_M1_MASK 1979 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_M2 1980 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_M2_MASK 1981 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_M4 1982 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_M4_MASK 1983 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_MF2 1984 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_MF2_MASK 1985 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_MF4 1986 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_MF4_MASK 1987 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_MF8 1988 +#define RISCV_PseudoVFNCVT_RTZ_X_F_W_MF8_MASK 1989 +#define RISCV_PseudoVFNCVT_XU_F_W_M1 1990 +#define RISCV_PseudoVFNCVT_XU_F_W_M1_MASK 1991 +#define RISCV_PseudoVFNCVT_XU_F_W_M2 1992 +#define RISCV_PseudoVFNCVT_XU_F_W_M2_MASK 1993 +#define RISCV_PseudoVFNCVT_XU_F_W_M4 1994 +#define RISCV_PseudoVFNCVT_XU_F_W_M4_MASK 1995 +#define RISCV_PseudoVFNCVT_XU_F_W_MF2 1996 +#define RISCV_PseudoVFNCVT_XU_F_W_MF2_MASK 1997 +#define RISCV_PseudoVFNCVT_XU_F_W_MF4 1998 +#define RISCV_PseudoVFNCVT_XU_F_W_MF4_MASK 1999 +#define RISCV_PseudoVFNCVT_XU_F_W_MF8 2000 +#define RISCV_PseudoVFNCVT_XU_F_W_MF8_MASK 2001 +#define RISCV_PseudoVFNCVT_X_F_W_M1 2002 +#define RISCV_PseudoVFNCVT_X_F_W_M1_MASK 2003 +#define RISCV_PseudoVFNCVT_X_F_W_M2 2004 +#define RISCV_PseudoVFNCVT_X_F_W_M2_MASK 2005 +#define RISCV_PseudoVFNCVT_X_F_W_M4 2006 +#define RISCV_PseudoVFNCVT_X_F_W_M4_MASK 2007 +#define RISCV_PseudoVFNCVT_X_F_W_MF2 2008 +#define RISCV_PseudoVFNCVT_X_F_W_MF2_MASK 2009 +#define RISCV_PseudoVFNCVT_X_F_W_MF4 2010 +#define RISCV_PseudoVFNCVT_X_F_W_MF4_MASK 2011 +#define RISCV_PseudoVFNCVT_X_F_W_MF8 2012 +#define RISCV_PseudoVFNCVT_X_F_W_MF8_MASK 2013 +#define RISCV_PseudoVFNMACC_VF16_M1 2014 +#define RISCV_PseudoVFNMACC_VF16_M1_MASK 2015 +#define RISCV_PseudoVFNMACC_VF16_M2 2016 +#define RISCV_PseudoVFNMACC_VF16_M2_MASK 2017 +#define RISCV_PseudoVFNMACC_VF16_M4 2018 +#define RISCV_PseudoVFNMACC_VF16_M4_MASK 2019 +#define RISCV_PseudoVFNMACC_VF16_M8 2020 +#define RISCV_PseudoVFNMACC_VF16_M8_MASK 2021 +#define RISCV_PseudoVFNMACC_VF16_MF2 2022 +#define RISCV_PseudoVFNMACC_VF16_MF2_MASK 2023 +#define RISCV_PseudoVFNMACC_VF16_MF4 2024 +#define RISCV_PseudoVFNMACC_VF16_MF4_MASK 2025 +#define RISCV_PseudoVFNMACC_VF16_MF8 2026 +#define RISCV_PseudoVFNMACC_VF16_MF8_MASK 2027 +#define RISCV_PseudoVFNMACC_VF32_M1 2028 +#define RISCV_PseudoVFNMACC_VF32_M1_MASK 2029 +#define RISCV_PseudoVFNMACC_VF32_M2 2030 +#define RISCV_PseudoVFNMACC_VF32_M2_MASK 2031 +#define RISCV_PseudoVFNMACC_VF32_M4 2032 +#define RISCV_PseudoVFNMACC_VF32_M4_MASK 2033 +#define RISCV_PseudoVFNMACC_VF32_M8 2034 +#define RISCV_PseudoVFNMACC_VF32_M8_MASK 2035 +#define RISCV_PseudoVFNMACC_VF32_MF2 2036 +#define RISCV_PseudoVFNMACC_VF32_MF2_MASK 2037 +#define RISCV_PseudoVFNMACC_VF32_MF4 2038 +#define RISCV_PseudoVFNMACC_VF32_MF4_MASK 2039 +#define RISCV_PseudoVFNMACC_VF32_MF8 2040 +#define RISCV_PseudoVFNMACC_VF32_MF8_MASK 2041 +#define RISCV_PseudoVFNMACC_VF64_M1 2042 +#define RISCV_PseudoVFNMACC_VF64_M1_MASK 2043 +#define RISCV_PseudoVFNMACC_VF64_M2 2044 +#define RISCV_PseudoVFNMACC_VF64_M2_MASK 2045 +#define RISCV_PseudoVFNMACC_VF64_M4 2046 +#define RISCV_PseudoVFNMACC_VF64_M4_MASK 2047 +#define RISCV_PseudoVFNMACC_VF64_M8 2048 +#define RISCV_PseudoVFNMACC_VF64_M8_MASK 2049 +#define RISCV_PseudoVFNMACC_VF64_MF2 2050 +#define RISCV_PseudoVFNMACC_VF64_MF2_MASK 2051 +#define RISCV_PseudoVFNMACC_VF64_MF4 2052 +#define RISCV_PseudoVFNMACC_VF64_MF4_MASK 2053 +#define RISCV_PseudoVFNMACC_VF64_MF8 2054 +#define RISCV_PseudoVFNMACC_VF64_MF8_MASK 2055 +#define RISCV_PseudoVFNMACC_VV_M1 2056 +#define RISCV_PseudoVFNMACC_VV_M1_MASK 2057 +#define RISCV_PseudoVFNMACC_VV_M2 2058 +#define RISCV_PseudoVFNMACC_VV_M2_MASK 2059 +#define RISCV_PseudoVFNMACC_VV_M4 2060 +#define RISCV_PseudoVFNMACC_VV_M4_MASK 2061 +#define RISCV_PseudoVFNMACC_VV_M8 2062 +#define RISCV_PseudoVFNMACC_VV_M8_MASK 2063 +#define RISCV_PseudoVFNMACC_VV_MF2 2064 +#define RISCV_PseudoVFNMACC_VV_MF2_MASK 2065 +#define RISCV_PseudoVFNMACC_VV_MF4 2066 +#define RISCV_PseudoVFNMACC_VV_MF4_MASK 2067 +#define RISCV_PseudoVFNMACC_VV_MF8 2068 +#define RISCV_PseudoVFNMACC_VV_MF8_MASK 2069 +#define RISCV_PseudoVFNMADD_VF16_M1 2070 +#define RISCV_PseudoVFNMADD_VF16_M1_MASK 2071 +#define RISCV_PseudoVFNMADD_VF16_M2 2072 +#define RISCV_PseudoVFNMADD_VF16_M2_MASK 2073 +#define RISCV_PseudoVFNMADD_VF16_M4 2074 +#define RISCV_PseudoVFNMADD_VF16_M4_MASK 2075 +#define RISCV_PseudoVFNMADD_VF16_M8 2076 +#define RISCV_PseudoVFNMADD_VF16_M8_MASK 2077 +#define RISCV_PseudoVFNMADD_VF16_MF2 2078 +#define RISCV_PseudoVFNMADD_VF16_MF2_MASK 2079 +#define RISCV_PseudoVFNMADD_VF16_MF4 2080 +#define RISCV_PseudoVFNMADD_VF16_MF4_MASK 2081 +#define RISCV_PseudoVFNMADD_VF16_MF8 2082 +#define RISCV_PseudoVFNMADD_VF16_MF8_MASK 2083 +#define RISCV_PseudoVFNMADD_VF32_M1 2084 +#define RISCV_PseudoVFNMADD_VF32_M1_MASK 2085 +#define RISCV_PseudoVFNMADD_VF32_M2 2086 +#define RISCV_PseudoVFNMADD_VF32_M2_MASK 2087 +#define RISCV_PseudoVFNMADD_VF32_M4 2088 +#define RISCV_PseudoVFNMADD_VF32_M4_MASK 2089 +#define RISCV_PseudoVFNMADD_VF32_M8 2090 +#define RISCV_PseudoVFNMADD_VF32_M8_MASK 2091 +#define RISCV_PseudoVFNMADD_VF32_MF2 2092 +#define RISCV_PseudoVFNMADD_VF32_MF2_MASK 2093 +#define RISCV_PseudoVFNMADD_VF32_MF4 2094 +#define RISCV_PseudoVFNMADD_VF32_MF4_MASK 2095 +#define RISCV_PseudoVFNMADD_VF32_MF8 2096 +#define RISCV_PseudoVFNMADD_VF32_MF8_MASK 2097 +#define RISCV_PseudoVFNMADD_VF64_M1 2098 +#define RISCV_PseudoVFNMADD_VF64_M1_MASK 2099 +#define RISCV_PseudoVFNMADD_VF64_M2 2100 +#define RISCV_PseudoVFNMADD_VF64_M2_MASK 2101 +#define RISCV_PseudoVFNMADD_VF64_M4 2102 +#define RISCV_PseudoVFNMADD_VF64_M4_MASK 2103 +#define RISCV_PseudoVFNMADD_VF64_M8 2104 +#define RISCV_PseudoVFNMADD_VF64_M8_MASK 2105 +#define RISCV_PseudoVFNMADD_VF64_MF2 2106 +#define RISCV_PseudoVFNMADD_VF64_MF2_MASK 2107 +#define RISCV_PseudoVFNMADD_VF64_MF4 2108 +#define RISCV_PseudoVFNMADD_VF64_MF4_MASK 2109 +#define RISCV_PseudoVFNMADD_VF64_MF8 2110 +#define RISCV_PseudoVFNMADD_VF64_MF8_MASK 2111 +#define RISCV_PseudoVFNMADD_VV_M1 2112 +#define RISCV_PseudoVFNMADD_VV_M1_MASK 2113 +#define RISCV_PseudoVFNMADD_VV_M2 2114 +#define RISCV_PseudoVFNMADD_VV_M2_MASK 2115 +#define RISCV_PseudoVFNMADD_VV_M4 2116 +#define RISCV_PseudoVFNMADD_VV_M4_MASK 2117 +#define RISCV_PseudoVFNMADD_VV_M8 2118 +#define RISCV_PseudoVFNMADD_VV_M8_MASK 2119 +#define RISCV_PseudoVFNMADD_VV_MF2 2120 +#define RISCV_PseudoVFNMADD_VV_MF2_MASK 2121 +#define RISCV_PseudoVFNMADD_VV_MF4 2122 +#define RISCV_PseudoVFNMADD_VV_MF4_MASK 2123 +#define RISCV_PseudoVFNMADD_VV_MF8 2124 +#define RISCV_PseudoVFNMADD_VV_MF8_MASK 2125 +#define RISCV_PseudoVFNMSAC_VF16_M1 2126 +#define RISCV_PseudoVFNMSAC_VF16_M1_MASK 2127 +#define RISCV_PseudoVFNMSAC_VF16_M2 2128 +#define RISCV_PseudoVFNMSAC_VF16_M2_MASK 2129 +#define RISCV_PseudoVFNMSAC_VF16_M4 2130 +#define RISCV_PseudoVFNMSAC_VF16_M4_MASK 2131 +#define RISCV_PseudoVFNMSAC_VF16_M8 2132 +#define RISCV_PseudoVFNMSAC_VF16_M8_MASK 2133 +#define RISCV_PseudoVFNMSAC_VF16_MF2 2134 +#define RISCV_PseudoVFNMSAC_VF16_MF2_MASK 2135 +#define RISCV_PseudoVFNMSAC_VF16_MF4 2136 +#define RISCV_PseudoVFNMSAC_VF16_MF4_MASK 2137 +#define RISCV_PseudoVFNMSAC_VF16_MF8 2138 +#define RISCV_PseudoVFNMSAC_VF16_MF8_MASK 2139 +#define RISCV_PseudoVFNMSAC_VF32_M1 2140 +#define RISCV_PseudoVFNMSAC_VF32_M1_MASK 2141 +#define RISCV_PseudoVFNMSAC_VF32_M2 2142 +#define RISCV_PseudoVFNMSAC_VF32_M2_MASK 2143 +#define RISCV_PseudoVFNMSAC_VF32_M4 2144 +#define RISCV_PseudoVFNMSAC_VF32_M4_MASK 2145 +#define RISCV_PseudoVFNMSAC_VF32_M8 2146 +#define RISCV_PseudoVFNMSAC_VF32_M8_MASK 2147 +#define RISCV_PseudoVFNMSAC_VF32_MF2 2148 +#define RISCV_PseudoVFNMSAC_VF32_MF2_MASK 2149 +#define RISCV_PseudoVFNMSAC_VF32_MF4 2150 +#define RISCV_PseudoVFNMSAC_VF32_MF4_MASK 2151 +#define RISCV_PseudoVFNMSAC_VF32_MF8 2152 +#define RISCV_PseudoVFNMSAC_VF32_MF8_MASK 2153 +#define RISCV_PseudoVFNMSAC_VF64_M1 2154 +#define RISCV_PseudoVFNMSAC_VF64_M1_MASK 2155 +#define RISCV_PseudoVFNMSAC_VF64_M2 2156 +#define RISCV_PseudoVFNMSAC_VF64_M2_MASK 2157 +#define RISCV_PseudoVFNMSAC_VF64_M4 2158 +#define RISCV_PseudoVFNMSAC_VF64_M4_MASK 2159 +#define RISCV_PseudoVFNMSAC_VF64_M8 2160 +#define RISCV_PseudoVFNMSAC_VF64_M8_MASK 2161 +#define RISCV_PseudoVFNMSAC_VF64_MF2 2162 +#define RISCV_PseudoVFNMSAC_VF64_MF2_MASK 2163 +#define RISCV_PseudoVFNMSAC_VF64_MF4 2164 +#define RISCV_PseudoVFNMSAC_VF64_MF4_MASK 2165 +#define RISCV_PseudoVFNMSAC_VF64_MF8 2166 +#define RISCV_PseudoVFNMSAC_VF64_MF8_MASK 2167 +#define RISCV_PseudoVFNMSAC_VV_M1 2168 +#define RISCV_PseudoVFNMSAC_VV_M1_MASK 2169 +#define RISCV_PseudoVFNMSAC_VV_M2 2170 +#define RISCV_PseudoVFNMSAC_VV_M2_MASK 2171 +#define RISCV_PseudoVFNMSAC_VV_M4 2172 +#define RISCV_PseudoVFNMSAC_VV_M4_MASK 2173 +#define RISCV_PseudoVFNMSAC_VV_M8 2174 +#define RISCV_PseudoVFNMSAC_VV_M8_MASK 2175 +#define RISCV_PseudoVFNMSAC_VV_MF2 2176 +#define RISCV_PseudoVFNMSAC_VV_MF2_MASK 2177 +#define RISCV_PseudoVFNMSAC_VV_MF4 2178 +#define RISCV_PseudoVFNMSAC_VV_MF4_MASK 2179 +#define RISCV_PseudoVFNMSAC_VV_MF8 2180 +#define RISCV_PseudoVFNMSAC_VV_MF8_MASK 2181 +#define RISCV_PseudoVFNMSUB_VF16_M1 2182 +#define RISCV_PseudoVFNMSUB_VF16_M1_MASK 2183 +#define RISCV_PseudoVFNMSUB_VF16_M2 2184 +#define RISCV_PseudoVFNMSUB_VF16_M2_MASK 2185 +#define RISCV_PseudoVFNMSUB_VF16_M4 2186 +#define RISCV_PseudoVFNMSUB_VF16_M4_MASK 2187 +#define RISCV_PseudoVFNMSUB_VF16_M8 2188 +#define RISCV_PseudoVFNMSUB_VF16_M8_MASK 2189 +#define RISCV_PseudoVFNMSUB_VF16_MF2 2190 +#define RISCV_PseudoVFNMSUB_VF16_MF2_MASK 2191 +#define RISCV_PseudoVFNMSUB_VF16_MF4 2192 +#define RISCV_PseudoVFNMSUB_VF16_MF4_MASK 2193 +#define RISCV_PseudoVFNMSUB_VF16_MF8 2194 +#define RISCV_PseudoVFNMSUB_VF16_MF8_MASK 2195 +#define RISCV_PseudoVFNMSUB_VF32_M1 2196 +#define RISCV_PseudoVFNMSUB_VF32_M1_MASK 2197 +#define RISCV_PseudoVFNMSUB_VF32_M2 2198 +#define RISCV_PseudoVFNMSUB_VF32_M2_MASK 2199 +#define RISCV_PseudoVFNMSUB_VF32_M4 2200 +#define RISCV_PseudoVFNMSUB_VF32_M4_MASK 2201 +#define RISCV_PseudoVFNMSUB_VF32_M8 2202 +#define RISCV_PseudoVFNMSUB_VF32_M8_MASK 2203 +#define RISCV_PseudoVFNMSUB_VF32_MF2 2204 +#define RISCV_PseudoVFNMSUB_VF32_MF2_MASK 2205 +#define RISCV_PseudoVFNMSUB_VF32_MF4 2206 +#define RISCV_PseudoVFNMSUB_VF32_MF4_MASK 2207 +#define RISCV_PseudoVFNMSUB_VF32_MF8 2208 +#define RISCV_PseudoVFNMSUB_VF32_MF8_MASK 2209 +#define RISCV_PseudoVFNMSUB_VF64_M1 2210 +#define RISCV_PseudoVFNMSUB_VF64_M1_MASK 2211 +#define RISCV_PseudoVFNMSUB_VF64_M2 2212 +#define RISCV_PseudoVFNMSUB_VF64_M2_MASK 2213 +#define RISCV_PseudoVFNMSUB_VF64_M4 2214 +#define RISCV_PseudoVFNMSUB_VF64_M4_MASK 2215 +#define RISCV_PseudoVFNMSUB_VF64_M8 2216 +#define RISCV_PseudoVFNMSUB_VF64_M8_MASK 2217 +#define RISCV_PseudoVFNMSUB_VF64_MF2 2218 +#define RISCV_PseudoVFNMSUB_VF64_MF2_MASK 2219 +#define RISCV_PseudoVFNMSUB_VF64_MF4 2220 +#define RISCV_PseudoVFNMSUB_VF64_MF4_MASK 2221 +#define RISCV_PseudoVFNMSUB_VF64_MF8 2222 +#define RISCV_PseudoVFNMSUB_VF64_MF8_MASK 2223 +#define RISCV_PseudoVFNMSUB_VV_M1 2224 +#define RISCV_PseudoVFNMSUB_VV_M1_MASK 2225 +#define RISCV_PseudoVFNMSUB_VV_M2 2226 +#define RISCV_PseudoVFNMSUB_VV_M2_MASK 2227 +#define RISCV_PseudoVFNMSUB_VV_M4 2228 +#define RISCV_PseudoVFNMSUB_VV_M4_MASK 2229 +#define RISCV_PseudoVFNMSUB_VV_M8 2230 +#define RISCV_PseudoVFNMSUB_VV_M8_MASK 2231 +#define RISCV_PseudoVFNMSUB_VV_MF2 2232 +#define RISCV_PseudoVFNMSUB_VV_MF2_MASK 2233 +#define RISCV_PseudoVFNMSUB_VV_MF4 2234 +#define RISCV_PseudoVFNMSUB_VV_MF4_MASK 2235 +#define RISCV_PseudoVFNMSUB_VV_MF8 2236 +#define RISCV_PseudoVFNMSUB_VV_MF8_MASK 2237 +#define RISCV_PseudoVFRDIV_VF16_M1 2238 +#define RISCV_PseudoVFRDIV_VF16_M1_MASK 2239 +#define RISCV_PseudoVFRDIV_VF16_M2 2240 +#define RISCV_PseudoVFRDIV_VF16_M2_MASK 2241 +#define RISCV_PseudoVFRDIV_VF16_M4 2242 +#define RISCV_PseudoVFRDIV_VF16_M4_MASK 2243 +#define RISCV_PseudoVFRDIV_VF16_M8 2244 +#define RISCV_PseudoVFRDIV_VF16_M8_MASK 2245 +#define RISCV_PseudoVFRDIV_VF16_MF2 2246 +#define RISCV_PseudoVFRDIV_VF16_MF2_MASK 2247 +#define RISCV_PseudoVFRDIV_VF16_MF4 2248 +#define RISCV_PseudoVFRDIV_VF16_MF4_MASK 2249 +#define RISCV_PseudoVFRDIV_VF16_MF8 2250 +#define RISCV_PseudoVFRDIV_VF16_MF8_MASK 2251 +#define RISCV_PseudoVFRDIV_VF32_M1 2252 +#define RISCV_PseudoVFRDIV_VF32_M1_MASK 2253 +#define RISCV_PseudoVFRDIV_VF32_M2 2254 +#define RISCV_PseudoVFRDIV_VF32_M2_MASK 2255 +#define RISCV_PseudoVFRDIV_VF32_M4 2256 +#define RISCV_PseudoVFRDIV_VF32_M4_MASK 2257 +#define RISCV_PseudoVFRDIV_VF32_M8 2258 +#define RISCV_PseudoVFRDIV_VF32_M8_MASK 2259 +#define RISCV_PseudoVFRDIV_VF32_MF2 2260 +#define RISCV_PseudoVFRDIV_VF32_MF2_MASK 2261 +#define RISCV_PseudoVFRDIV_VF32_MF4 2262 +#define RISCV_PseudoVFRDIV_VF32_MF4_MASK 2263 +#define RISCV_PseudoVFRDIV_VF32_MF8 2264 +#define RISCV_PseudoVFRDIV_VF32_MF8_MASK 2265 +#define RISCV_PseudoVFRDIV_VF64_M1 2266 +#define RISCV_PseudoVFRDIV_VF64_M1_MASK 2267 +#define RISCV_PseudoVFRDIV_VF64_M2 2268 +#define RISCV_PseudoVFRDIV_VF64_M2_MASK 2269 +#define RISCV_PseudoVFRDIV_VF64_M4 2270 +#define RISCV_PseudoVFRDIV_VF64_M4_MASK 2271 +#define RISCV_PseudoVFRDIV_VF64_M8 2272 +#define RISCV_PseudoVFRDIV_VF64_M8_MASK 2273 +#define RISCV_PseudoVFRDIV_VF64_MF2 2274 +#define RISCV_PseudoVFRDIV_VF64_MF2_MASK 2275 +#define RISCV_PseudoVFRDIV_VF64_MF4 2276 +#define RISCV_PseudoVFRDIV_VF64_MF4_MASK 2277 +#define RISCV_PseudoVFRDIV_VF64_MF8 2278 +#define RISCV_PseudoVFRDIV_VF64_MF8_MASK 2279 +#define RISCV_PseudoVFREC7_V_M1 2280 +#define RISCV_PseudoVFREC7_V_M1_MASK 2281 +#define RISCV_PseudoVFREC7_V_M2 2282 +#define RISCV_PseudoVFREC7_V_M2_MASK 2283 +#define RISCV_PseudoVFREC7_V_M4 2284 +#define RISCV_PseudoVFREC7_V_M4_MASK 2285 +#define RISCV_PseudoVFREC7_V_M8 2286 +#define RISCV_PseudoVFREC7_V_M8_MASK 2287 +#define RISCV_PseudoVFREC7_V_MF2 2288 +#define RISCV_PseudoVFREC7_V_MF2_MASK 2289 +#define RISCV_PseudoVFREC7_V_MF4 2290 +#define RISCV_PseudoVFREC7_V_MF4_MASK 2291 +#define RISCV_PseudoVFREC7_V_MF8 2292 +#define RISCV_PseudoVFREC7_V_MF8_MASK 2293 +#define RISCV_PseudoVFREDMAX_VS_M1 2294 +#define RISCV_PseudoVFREDMAX_VS_M1_MASK 2295 +#define RISCV_PseudoVFREDMAX_VS_M2 2296 +#define RISCV_PseudoVFREDMAX_VS_M2_MASK 2297 +#define RISCV_PseudoVFREDMAX_VS_M4 2298 +#define RISCV_PseudoVFREDMAX_VS_M4_MASK 2299 +#define RISCV_PseudoVFREDMAX_VS_M8 2300 +#define RISCV_PseudoVFREDMAX_VS_M8_MASK 2301 +#define RISCV_PseudoVFREDMAX_VS_MF2 2302 +#define RISCV_PseudoVFREDMAX_VS_MF2_MASK 2303 +#define RISCV_PseudoVFREDMAX_VS_MF4 2304 +#define RISCV_PseudoVFREDMAX_VS_MF4_MASK 2305 +#define RISCV_PseudoVFREDMAX_VS_MF8 2306 +#define RISCV_PseudoVFREDMAX_VS_MF8_MASK 2307 +#define RISCV_PseudoVFREDMIN_VS_M1 2308 +#define RISCV_PseudoVFREDMIN_VS_M1_MASK 2309 +#define RISCV_PseudoVFREDMIN_VS_M2 2310 +#define RISCV_PseudoVFREDMIN_VS_M2_MASK 2311 +#define RISCV_PseudoVFREDMIN_VS_M4 2312 +#define RISCV_PseudoVFREDMIN_VS_M4_MASK 2313 +#define RISCV_PseudoVFREDMIN_VS_M8 2314 +#define RISCV_PseudoVFREDMIN_VS_M8_MASK 2315 +#define RISCV_PseudoVFREDMIN_VS_MF2 2316 +#define RISCV_PseudoVFREDMIN_VS_MF2_MASK 2317 +#define RISCV_PseudoVFREDMIN_VS_MF4 2318 +#define RISCV_PseudoVFREDMIN_VS_MF4_MASK 2319 +#define RISCV_PseudoVFREDMIN_VS_MF8 2320 +#define RISCV_PseudoVFREDMIN_VS_MF8_MASK 2321 +#define RISCV_PseudoVFREDOSUM_VS_M1 2322 +#define RISCV_PseudoVFREDOSUM_VS_M1_MASK 2323 +#define RISCV_PseudoVFREDOSUM_VS_M2 2324 +#define RISCV_PseudoVFREDOSUM_VS_M2_MASK 2325 +#define RISCV_PseudoVFREDOSUM_VS_M4 2326 +#define RISCV_PseudoVFREDOSUM_VS_M4_MASK 2327 +#define RISCV_PseudoVFREDOSUM_VS_M8 2328 +#define RISCV_PseudoVFREDOSUM_VS_M8_MASK 2329 +#define RISCV_PseudoVFREDOSUM_VS_MF2 2330 +#define RISCV_PseudoVFREDOSUM_VS_MF2_MASK 2331 +#define RISCV_PseudoVFREDOSUM_VS_MF4 2332 +#define RISCV_PseudoVFREDOSUM_VS_MF4_MASK 2333 +#define RISCV_PseudoVFREDOSUM_VS_MF8 2334 +#define RISCV_PseudoVFREDOSUM_VS_MF8_MASK 2335 +#define RISCV_PseudoVFREDUSUM_VS_M1 2336 +#define RISCV_PseudoVFREDUSUM_VS_M1_MASK 2337 +#define RISCV_PseudoVFREDUSUM_VS_M2 2338 +#define RISCV_PseudoVFREDUSUM_VS_M2_MASK 2339 +#define RISCV_PseudoVFREDUSUM_VS_M4 2340 +#define RISCV_PseudoVFREDUSUM_VS_M4_MASK 2341 +#define RISCV_PseudoVFREDUSUM_VS_M8 2342 +#define RISCV_PseudoVFREDUSUM_VS_M8_MASK 2343 +#define RISCV_PseudoVFREDUSUM_VS_MF2 2344 +#define RISCV_PseudoVFREDUSUM_VS_MF2_MASK 2345 +#define RISCV_PseudoVFREDUSUM_VS_MF4 2346 +#define RISCV_PseudoVFREDUSUM_VS_MF4_MASK 2347 +#define RISCV_PseudoVFREDUSUM_VS_MF8 2348 +#define RISCV_PseudoVFREDUSUM_VS_MF8_MASK 2349 +#define RISCV_PseudoVFRSQRT7_V_M1 2350 +#define RISCV_PseudoVFRSQRT7_V_M1_MASK 2351 +#define RISCV_PseudoVFRSQRT7_V_M2 2352 +#define RISCV_PseudoVFRSQRT7_V_M2_MASK 2353 +#define RISCV_PseudoVFRSQRT7_V_M4 2354 +#define RISCV_PseudoVFRSQRT7_V_M4_MASK 2355 +#define RISCV_PseudoVFRSQRT7_V_M8 2356 +#define RISCV_PseudoVFRSQRT7_V_M8_MASK 2357 +#define RISCV_PseudoVFRSQRT7_V_MF2 2358 +#define RISCV_PseudoVFRSQRT7_V_MF2_MASK 2359 +#define RISCV_PseudoVFRSQRT7_V_MF4 2360 +#define RISCV_PseudoVFRSQRT7_V_MF4_MASK 2361 +#define RISCV_PseudoVFRSQRT7_V_MF8 2362 +#define RISCV_PseudoVFRSQRT7_V_MF8_MASK 2363 +#define RISCV_PseudoVFRSUB_VF16_M1 2364 +#define RISCV_PseudoVFRSUB_VF16_M1_MASK 2365 +#define RISCV_PseudoVFRSUB_VF16_M2 2366 +#define RISCV_PseudoVFRSUB_VF16_M2_MASK 2367 +#define RISCV_PseudoVFRSUB_VF16_M4 2368 +#define RISCV_PseudoVFRSUB_VF16_M4_MASK 2369 +#define RISCV_PseudoVFRSUB_VF16_M8 2370 +#define RISCV_PseudoVFRSUB_VF16_M8_MASK 2371 +#define RISCV_PseudoVFRSUB_VF16_MF2 2372 +#define RISCV_PseudoVFRSUB_VF16_MF2_MASK 2373 +#define RISCV_PseudoVFRSUB_VF16_MF4 2374 +#define RISCV_PseudoVFRSUB_VF16_MF4_MASK 2375 +#define RISCV_PseudoVFRSUB_VF16_MF8 2376 +#define RISCV_PseudoVFRSUB_VF16_MF8_MASK 2377 +#define RISCV_PseudoVFRSUB_VF32_M1 2378 +#define RISCV_PseudoVFRSUB_VF32_M1_MASK 2379 +#define RISCV_PseudoVFRSUB_VF32_M2 2380 +#define RISCV_PseudoVFRSUB_VF32_M2_MASK 2381 +#define RISCV_PseudoVFRSUB_VF32_M4 2382 +#define RISCV_PseudoVFRSUB_VF32_M4_MASK 2383 +#define RISCV_PseudoVFRSUB_VF32_M8 2384 +#define RISCV_PseudoVFRSUB_VF32_M8_MASK 2385 +#define RISCV_PseudoVFRSUB_VF32_MF2 2386 +#define RISCV_PseudoVFRSUB_VF32_MF2_MASK 2387 +#define RISCV_PseudoVFRSUB_VF32_MF4 2388 +#define RISCV_PseudoVFRSUB_VF32_MF4_MASK 2389 +#define RISCV_PseudoVFRSUB_VF32_MF8 2390 +#define RISCV_PseudoVFRSUB_VF32_MF8_MASK 2391 +#define RISCV_PseudoVFRSUB_VF64_M1 2392 +#define RISCV_PseudoVFRSUB_VF64_M1_MASK 2393 +#define RISCV_PseudoVFRSUB_VF64_M2 2394 +#define RISCV_PseudoVFRSUB_VF64_M2_MASK 2395 +#define RISCV_PseudoVFRSUB_VF64_M4 2396 +#define RISCV_PseudoVFRSUB_VF64_M4_MASK 2397 +#define RISCV_PseudoVFRSUB_VF64_M8 2398 +#define RISCV_PseudoVFRSUB_VF64_M8_MASK 2399 +#define RISCV_PseudoVFRSUB_VF64_MF2 2400 +#define RISCV_PseudoVFRSUB_VF64_MF2_MASK 2401 +#define RISCV_PseudoVFRSUB_VF64_MF4 2402 +#define RISCV_PseudoVFRSUB_VF64_MF4_MASK 2403 +#define RISCV_PseudoVFRSUB_VF64_MF8 2404 +#define RISCV_PseudoVFRSUB_VF64_MF8_MASK 2405 +#define RISCV_PseudoVFSGNJN_VF16_M1 2406 +#define RISCV_PseudoVFSGNJN_VF16_M1_MASK 2407 +#define RISCV_PseudoVFSGNJN_VF16_M2 2408 +#define RISCV_PseudoVFSGNJN_VF16_M2_MASK 2409 +#define RISCV_PseudoVFSGNJN_VF16_M4 2410 +#define RISCV_PseudoVFSGNJN_VF16_M4_MASK 2411 +#define RISCV_PseudoVFSGNJN_VF16_M8 2412 +#define RISCV_PseudoVFSGNJN_VF16_M8_MASK 2413 +#define RISCV_PseudoVFSGNJN_VF16_MF2 2414 +#define RISCV_PseudoVFSGNJN_VF16_MF2_MASK 2415 +#define RISCV_PseudoVFSGNJN_VF16_MF4 2416 +#define RISCV_PseudoVFSGNJN_VF16_MF4_MASK 2417 +#define RISCV_PseudoVFSGNJN_VF16_MF8 2418 +#define RISCV_PseudoVFSGNJN_VF16_MF8_MASK 2419 +#define RISCV_PseudoVFSGNJN_VF32_M1 2420 +#define RISCV_PseudoVFSGNJN_VF32_M1_MASK 2421 +#define RISCV_PseudoVFSGNJN_VF32_M2 2422 +#define RISCV_PseudoVFSGNJN_VF32_M2_MASK 2423 +#define RISCV_PseudoVFSGNJN_VF32_M4 2424 +#define RISCV_PseudoVFSGNJN_VF32_M4_MASK 2425 +#define RISCV_PseudoVFSGNJN_VF32_M8 2426 +#define RISCV_PseudoVFSGNJN_VF32_M8_MASK 2427 +#define RISCV_PseudoVFSGNJN_VF32_MF2 2428 +#define RISCV_PseudoVFSGNJN_VF32_MF2_MASK 2429 +#define RISCV_PseudoVFSGNJN_VF32_MF4 2430 +#define RISCV_PseudoVFSGNJN_VF32_MF4_MASK 2431 +#define RISCV_PseudoVFSGNJN_VF32_MF8 2432 +#define RISCV_PseudoVFSGNJN_VF32_MF8_MASK 2433 +#define RISCV_PseudoVFSGNJN_VF64_M1 2434 +#define RISCV_PseudoVFSGNJN_VF64_M1_MASK 2435 +#define RISCV_PseudoVFSGNJN_VF64_M2 2436 +#define RISCV_PseudoVFSGNJN_VF64_M2_MASK 2437 +#define RISCV_PseudoVFSGNJN_VF64_M4 2438 +#define RISCV_PseudoVFSGNJN_VF64_M4_MASK 2439 +#define RISCV_PseudoVFSGNJN_VF64_M8 2440 +#define RISCV_PseudoVFSGNJN_VF64_M8_MASK 2441 +#define RISCV_PseudoVFSGNJN_VF64_MF2 2442 +#define RISCV_PseudoVFSGNJN_VF64_MF2_MASK 2443 +#define RISCV_PseudoVFSGNJN_VF64_MF4 2444 +#define RISCV_PseudoVFSGNJN_VF64_MF4_MASK 2445 +#define RISCV_PseudoVFSGNJN_VF64_MF8 2446 +#define RISCV_PseudoVFSGNJN_VF64_MF8_MASK 2447 +#define RISCV_PseudoVFSGNJN_VV_M1 2448 +#define RISCV_PseudoVFSGNJN_VV_M1_MASK 2449 +#define RISCV_PseudoVFSGNJN_VV_M2 2450 +#define RISCV_PseudoVFSGNJN_VV_M2_MASK 2451 +#define RISCV_PseudoVFSGNJN_VV_M4 2452 +#define RISCV_PseudoVFSGNJN_VV_M4_MASK 2453 +#define RISCV_PseudoVFSGNJN_VV_M8 2454 +#define RISCV_PseudoVFSGNJN_VV_M8_MASK 2455 +#define RISCV_PseudoVFSGNJN_VV_MF2 2456 +#define RISCV_PseudoVFSGNJN_VV_MF2_MASK 2457 +#define RISCV_PseudoVFSGNJN_VV_MF4 2458 +#define RISCV_PseudoVFSGNJN_VV_MF4_MASK 2459 +#define RISCV_PseudoVFSGNJN_VV_MF8 2460 +#define RISCV_PseudoVFSGNJN_VV_MF8_MASK 2461 +#define RISCV_PseudoVFSGNJX_VF16_M1 2462 +#define RISCV_PseudoVFSGNJX_VF16_M1_MASK 2463 +#define RISCV_PseudoVFSGNJX_VF16_M2 2464 +#define RISCV_PseudoVFSGNJX_VF16_M2_MASK 2465 +#define RISCV_PseudoVFSGNJX_VF16_M4 2466 +#define RISCV_PseudoVFSGNJX_VF16_M4_MASK 2467 +#define RISCV_PseudoVFSGNJX_VF16_M8 2468 +#define RISCV_PseudoVFSGNJX_VF16_M8_MASK 2469 +#define RISCV_PseudoVFSGNJX_VF16_MF2 2470 +#define RISCV_PseudoVFSGNJX_VF16_MF2_MASK 2471 +#define RISCV_PseudoVFSGNJX_VF16_MF4 2472 +#define RISCV_PseudoVFSGNJX_VF16_MF4_MASK 2473 +#define RISCV_PseudoVFSGNJX_VF16_MF8 2474 +#define RISCV_PseudoVFSGNJX_VF16_MF8_MASK 2475 +#define RISCV_PseudoVFSGNJX_VF32_M1 2476 +#define RISCV_PseudoVFSGNJX_VF32_M1_MASK 2477 +#define RISCV_PseudoVFSGNJX_VF32_M2 2478 +#define RISCV_PseudoVFSGNJX_VF32_M2_MASK 2479 +#define RISCV_PseudoVFSGNJX_VF32_M4 2480 +#define RISCV_PseudoVFSGNJX_VF32_M4_MASK 2481 +#define RISCV_PseudoVFSGNJX_VF32_M8 2482 +#define RISCV_PseudoVFSGNJX_VF32_M8_MASK 2483 +#define RISCV_PseudoVFSGNJX_VF32_MF2 2484 +#define RISCV_PseudoVFSGNJX_VF32_MF2_MASK 2485 +#define RISCV_PseudoVFSGNJX_VF32_MF4 2486 +#define RISCV_PseudoVFSGNJX_VF32_MF4_MASK 2487 +#define RISCV_PseudoVFSGNJX_VF32_MF8 2488 +#define RISCV_PseudoVFSGNJX_VF32_MF8_MASK 2489 +#define RISCV_PseudoVFSGNJX_VF64_M1 2490 +#define RISCV_PseudoVFSGNJX_VF64_M1_MASK 2491 +#define RISCV_PseudoVFSGNJX_VF64_M2 2492 +#define RISCV_PseudoVFSGNJX_VF64_M2_MASK 2493 +#define RISCV_PseudoVFSGNJX_VF64_M4 2494 +#define RISCV_PseudoVFSGNJX_VF64_M4_MASK 2495 +#define RISCV_PseudoVFSGNJX_VF64_M8 2496 +#define RISCV_PseudoVFSGNJX_VF64_M8_MASK 2497 +#define RISCV_PseudoVFSGNJX_VF64_MF2 2498 +#define RISCV_PseudoVFSGNJX_VF64_MF2_MASK 2499 +#define RISCV_PseudoVFSGNJX_VF64_MF4 2500 +#define RISCV_PseudoVFSGNJX_VF64_MF4_MASK 2501 +#define RISCV_PseudoVFSGNJX_VF64_MF8 2502 +#define RISCV_PseudoVFSGNJX_VF64_MF8_MASK 2503 +#define RISCV_PseudoVFSGNJX_VV_M1 2504 +#define RISCV_PseudoVFSGNJX_VV_M1_MASK 2505 +#define RISCV_PseudoVFSGNJX_VV_M2 2506 +#define RISCV_PseudoVFSGNJX_VV_M2_MASK 2507 +#define RISCV_PseudoVFSGNJX_VV_M4 2508 +#define RISCV_PseudoVFSGNJX_VV_M4_MASK 2509 +#define RISCV_PseudoVFSGNJX_VV_M8 2510 +#define RISCV_PseudoVFSGNJX_VV_M8_MASK 2511 +#define RISCV_PseudoVFSGNJX_VV_MF2 2512 +#define RISCV_PseudoVFSGNJX_VV_MF2_MASK 2513 +#define RISCV_PseudoVFSGNJX_VV_MF4 2514 +#define RISCV_PseudoVFSGNJX_VV_MF4_MASK 2515 +#define RISCV_PseudoVFSGNJX_VV_MF8 2516 +#define RISCV_PseudoVFSGNJX_VV_MF8_MASK 2517 +#define RISCV_PseudoVFSGNJ_VF16_M1 2518 +#define RISCV_PseudoVFSGNJ_VF16_M1_MASK 2519 +#define RISCV_PseudoVFSGNJ_VF16_M2 2520 +#define RISCV_PseudoVFSGNJ_VF16_M2_MASK 2521 +#define RISCV_PseudoVFSGNJ_VF16_M4 2522 +#define RISCV_PseudoVFSGNJ_VF16_M4_MASK 2523 +#define RISCV_PseudoVFSGNJ_VF16_M8 2524 +#define RISCV_PseudoVFSGNJ_VF16_M8_MASK 2525 +#define RISCV_PseudoVFSGNJ_VF16_MF2 2526 +#define RISCV_PseudoVFSGNJ_VF16_MF2_MASK 2527 +#define RISCV_PseudoVFSGNJ_VF16_MF4 2528 +#define RISCV_PseudoVFSGNJ_VF16_MF4_MASK 2529 +#define RISCV_PseudoVFSGNJ_VF16_MF8 2530 +#define RISCV_PseudoVFSGNJ_VF16_MF8_MASK 2531 +#define RISCV_PseudoVFSGNJ_VF32_M1 2532 +#define RISCV_PseudoVFSGNJ_VF32_M1_MASK 2533 +#define RISCV_PseudoVFSGNJ_VF32_M2 2534 +#define RISCV_PseudoVFSGNJ_VF32_M2_MASK 2535 +#define RISCV_PseudoVFSGNJ_VF32_M4 2536 +#define RISCV_PseudoVFSGNJ_VF32_M4_MASK 2537 +#define RISCV_PseudoVFSGNJ_VF32_M8 2538 +#define RISCV_PseudoVFSGNJ_VF32_M8_MASK 2539 +#define RISCV_PseudoVFSGNJ_VF32_MF2 2540 +#define RISCV_PseudoVFSGNJ_VF32_MF2_MASK 2541 +#define RISCV_PseudoVFSGNJ_VF32_MF4 2542 +#define RISCV_PseudoVFSGNJ_VF32_MF4_MASK 2543 +#define RISCV_PseudoVFSGNJ_VF32_MF8 2544 +#define RISCV_PseudoVFSGNJ_VF32_MF8_MASK 2545 +#define RISCV_PseudoVFSGNJ_VF64_M1 2546 +#define RISCV_PseudoVFSGNJ_VF64_M1_MASK 2547 +#define RISCV_PseudoVFSGNJ_VF64_M2 2548 +#define RISCV_PseudoVFSGNJ_VF64_M2_MASK 2549 +#define RISCV_PseudoVFSGNJ_VF64_M4 2550 +#define RISCV_PseudoVFSGNJ_VF64_M4_MASK 2551 +#define RISCV_PseudoVFSGNJ_VF64_M8 2552 +#define RISCV_PseudoVFSGNJ_VF64_M8_MASK 2553 +#define RISCV_PseudoVFSGNJ_VF64_MF2 2554 +#define RISCV_PseudoVFSGNJ_VF64_MF2_MASK 2555 +#define RISCV_PseudoVFSGNJ_VF64_MF4 2556 +#define RISCV_PseudoVFSGNJ_VF64_MF4_MASK 2557 +#define RISCV_PseudoVFSGNJ_VF64_MF8 2558 +#define RISCV_PseudoVFSGNJ_VF64_MF8_MASK 2559 +#define RISCV_PseudoVFSGNJ_VV_M1 2560 +#define RISCV_PseudoVFSGNJ_VV_M1_MASK 2561 +#define RISCV_PseudoVFSGNJ_VV_M2 2562 +#define RISCV_PseudoVFSGNJ_VV_M2_MASK 2563 +#define RISCV_PseudoVFSGNJ_VV_M4 2564 +#define RISCV_PseudoVFSGNJ_VV_M4_MASK 2565 +#define RISCV_PseudoVFSGNJ_VV_M8 2566 +#define RISCV_PseudoVFSGNJ_VV_M8_MASK 2567 +#define RISCV_PseudoVFSGNJ_VV_MF2 2568 +#define RISCV_PseudoVFSGNJ_VV_MF2_MASK 2569 +#define RISCV_PseudoVFSGNJ_VV_MF4 2570 +#define RISCV_PseudoVFSGNJ_VV_MF4_MASK 2571 +#define RISCV_PseudoVFSGNJ_VV_MF8 2572 +#define RISCV_PseudoVFSGNJ_VV_MF8_MASK 2573 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_M1 2574 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_M1_MASK 2575 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_M2 2576 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_M2_MASK 2577 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_M4 2578 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_M4_MASK 2579 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_M8 2580 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_M8_MASK 2581 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_MF2 2582 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_MF2_MASK 2583 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_MF4 2584 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_MF4_MASK 2585 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_MF8 2586 +#define RISCV_PseudoVFSLIDE1DOWN_VF16_MF8_MASK 2587 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_M1 2588 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_M1_MASK 2589 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_M2 2590 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_M2_MASK 2591 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_M4 2592 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_M4_MASK 2593 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_M8 2594 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_M8_MASK 2595 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_MF2 2596 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_MF2_MASK 2597 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_MF4 2598 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_MF4_MASK 2599 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_MF8 2600 +#define RISCV_PseudoVFSLIDE1DOWN_VF32_MF8_MASK 2601 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_M1 2602 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_M1_MASK 2603 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_M2 2604 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_M2_MASK 2605 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_M4 2606 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_M4_MASK 2607 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_M8 2608 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_M8_MASK 2609 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_MF2 2610 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_MF2_MASK 2611 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_MF4 2612 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_MF4_MASK 2613 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_MF8 2614 +#define RISCV_PseudoVFSLIDE1DOWN_VF64_MF8_MASK 2615 +#define RISCV_PseudoVFSLIDE1UP_VF16_M1 2616 +#define RISCV_PseudoVFSLIDE1UP_VF16_M1_MASK 2617 +#define RISCV_PseudoVFSLIDE1UP_VF16_M2 2618 +#define RISCV_PseudoVFSLIDE1UP_VF16_M2_MASK 2619 +#define RISCV_PseudoVFSLIDE1UP_VF16_M4 2620 +#define RISCV_PseudoVFSLIDE1UP_VF16_M4_MASK 2621 +#define RISCV_PseudoVFSLIDE1UP_VF16_M8 2622 +#define RISCV_PseudoVFSLIDE1UP_VF16_M8_MASK 2623 +#define RISCV_PseudoVFSLIDE1UP_VF16_MF2 2624 +#define RISCV_PseudoVFSLIDE1UP_VF16_MF2_MASK 2625 +#define RISCV_PseudoVFSLIDE1UP_VF16_MF4 2626 +#define RISCV_PseudoVFSLIDE1UP_VF16_MF4_MASK 2627 +#define RISCV_PseudoVFSLIDE1UP_VF16_MF8 2628 +#define RISCV_PseudoVFSLIDE1UP_VF16_MF8_MASK 2629 +#define RISCV_PseudoVFSLIDE1UP_VF32_M1 2630 +#define RISCV_PseudoVFSLIDE1UP_VF32_M1_MASK 2631 +#define RISCV_PseudoVFSLIDE1UP_VF32_M2 2632 +#define RISCV_PseudoVFSLIDE1UP_VF32_M2_MASK 2633 +#define RISCV_PseudoVFSLIDE1UP_VF32_M4 2634 +#define RISCV_PseudoVFSLIDE1UP_VF32_M4_MASK 2635 +#define RISCV_PseudoVFSLIDE1UP_VF32_M8 2636 +#define RISCV_PseudoVFSLIDE1UP_VF32_M8_MASK 2637 +#define RISCV_PseudoVFSLIDE1UP_VF32_MF2 2638 +#define RISCV_PseudoVFSLIDE1UP_VF32_MF2_MASK 2639 +#define RISCV_PseudoVFSLIDE1UP_VF32_MF4 2640 +#define RISCV_PseudoVFSLIDE1UP_VF32_MF4_MASK 2641 +#define RISCV_PseudoVFSLIDE1UP_VF32_MF8 2642 +#define RISCV_PseudoVFSLIDE1UP_VF32_MF8_MASK 2643 +#define RISCV_PseudoVFSLIDE1UP_VF64_M1 2644 +#define RISCV_PseudoVFSLIDE1UP_VF64_M1_MASK 2645 +#define RISCV_PseudoVFSLIDE1UP_VF64_M2 2646 +#define RISCV_PseudoVFSLIDE1UP_VF64_M2_MASK 2647 +#define RISCV_PseudoVFSLIDE1UP_VF64_M4 2648 +#define RISCV_PseudoVFSLIDE1UP_VF64_M4_MASK 2649 +#define RISCV_PseudoVFSLIDE1UP_VF64_M8 2650 +#define RISCV_PseudoVFSLIDE1UP_VF64_M8_MASK 2651 +#define RISCV_PseudoVFSLIDE1UP_VF64_MF2 2652 +#define RISCV_PseudoVFSLIDE1UP_VF64_MF2_MASK 2653 +#define RISCV_PseudoVFSLIDE1UP_VF64_MF4 2654 +#define RISCV_PseudoVFSLIDE1UP_VF64_MF4_MASK 2655 +#define RISCV_PseudoVFSLIDE1UP_VF64_MF8 2656 +#define RISCV_PseudoVFSLIDE1UP_VF64_MF8_MASK 2657 +#define RISCV_PseudoVFSQRT_V_M1 2658 +#define RISCV_PseudoVFSQRT_V_M1_MASK 2659 +#define RISCV_PseudoVFSQRT_V_M2 2660 +#define RISCV_PseudoVFSQRT_V_M2_MASK 2661 +#define RISCV_PseudoVFSQRT_V_M4 2662 +#define RISCV_PseudoVFSQRT_V_M4_MASK 2663 +#define RISCV_PseudoVFSQRT_V_M8 2664 +#define RISCV_PseudoVFSQRT_V_M8_MASK 2665 +#define RISCV_PseudoVFSQRT_V_MF2 2666 +#define RISCV_PseudoVFSQRT_V_MF2_MASK 2667 +#define RISCV_PseudoVFSQRT_V_MF4 2668 +#define RISCV_PseudoVFSQRT_V_MF4_MASK 2669 +#define RISCV_PseudoVFSQRT_V_MF8 2670 +#define RISCV_PseudoVFSQRT_V_MF8_MASK 2671 +#define RISCV_PseudoVFSUB_VF16_M1 2672 +#define RISCV_PseudoVFSUB_VF16_M1_MASK 2673 +#define RISCV_PseudoVFSUB_VF16_M2 2674 +#define RISCV_PseudoVFSUB_VF16_M2_MASK 2675 +#define RISCV_PseudoVFSUB_VF16_M4 2676 +#define RISCV_PseudoVFSUB_VF16_M4_MASK 2677 +#define RISCV_PseudoVFSUB_VF16_M8 2678 +#define RISCV_PseudoVFSUB_VF16_M8_MASK 2679 +#define RISCV_PseudoVFSUB_VF16_MF2 2680 +#define RISCV_PseudoVFSUB_VF16_MF2_MASK 2681 +#define RISCV_PseudoVFSUB_VF16_MF4 2682 +#define RISCV_PseudoVFSUB_VF16_MF4_MASK 2683 +#define RISCV_PseudoVFSUB_VF16_MF8 2684 +#define RISCV_PseudoVFSUB_VF16_MF8_MASK 2685 +#define RISCV_PseudoVFSUB_VF32_M1 2686 +#define RISCV_PseudoVFSUB_VF32_M1_MASK 2687 +#define RISCV_PseudoVFSUB_VF32_M2 2688 +#define RISCV_PseudoVFSUB_VF32_M2_MASK 2689 +#define RISCV_PseudoVFSUB_VF32_M4 2690 +#define RISCV_PseudoVFSUB_VF32_M4_MASK 2691 +#define RISCV_PseudoVFSUB_VF32_M8 2692 +#define RISCV_PseudoVFSUB_VF32_M8_MASK 2693 +#define RISCV_PseudoVFSUB_VF32_MF2 2694 +#define RISCV_PseudoVFSUB_VF32_MF2_MASK 2695 +#define RISCV_PseudoVFSUB_VF32_MF4 2696 +#define RISCV_PseudoVFSUB_VF32_MF4_MASK 2697 +#define RISCV_PseudoVFSUB_VF32_MF8 2698 +#define RISCV_PseudoVFSUB_VF32_MF8_MASK 2699 +#define RISCV_PseudoVFSUB_VF64_M1 2700 +#define RISCV_PseudoVFSUB_VF64_M1_MASK 2701 +#define RISCV_PseudoVFSUB_VF64_M2 2702 +#define RISCV_PseudoVFSUB_VF64_M2_MASK 2703 +#define RISCV_PseudoVFSUB_VF64_M4 2704 +#define RISCV_PseudoVFSUB_VF64_M4_MASK 2705 +#define RISCV_PseudoVFSUB_VF64_M8 2706 +#define RISCV_PseudoVFSUB_VF64_M8_MASK 2707 +#define RISCV_PseudoVFSUB_VF64_MF2 2708 +#define RISCV_PseudoVFSUB_VF64_MF2_MASK 2709 +#define RISCV_PseudoVFSUB_VF64_MF4 2710 +#define RISCV_PseudoVFSUB_VF64_MF4_MASK 2711 +#define RISCV_PseudoVFSUB_VF64_MF8 2712 +#define RISCV_PseudoVFSUB_VF64_MF8_MASK 2713 +#define RISCV_PseudoVFSUB_VV_M1 2714 +#define RISCV_PseudoVFSUB_VV_M1_MASK 2715 +#define RISCV_PseudoVFSUB_VV_M2 2716 +#define RISCV_PseudoVFSUB_VV_M2_MASK 2717 +#define RISCV_PseudoVFSUB_VV_M4 2718 +#define RISCV_PseudoVFSUB_VV_M4_MASK 2719 +#define RISCV_PseudoVFSUB_VV_M8 2720 +#define RISCV_PseudoVFSUB_VV_M8_MASK 2721 +#define RISCV_PseudoVFSUB_VV_MF2 2722 +#define RISCV_PseudoVFSUB_VV_MF2_MASK 2723 +#define RISCV_PseudoVFSUB_VV_MF4 2724 +#define RISCV_PseudoVFSUB_VV_MF4_MASK 2725 +#define RISCV_PseudoVFSUB_VV_MF8 2726 +#define RISCV_PseudoVFSUB_VV_MF8_MASK 2727 +#define RISCV_PseudoVFWADD_VF16_M1 2728 +#define RISCV_PseudoVFWADD_VF16_M1_MASK 2729 +#define RISCV_PseudoVFWADD_VF16_M2 2730 +#define RISCV_PseudoVFWADD_VF16_M2_MASK 2731 +#define RISCV_PseudoVFWADD_VF16_M4 2732 +#define RISCV_PseudoVFWADD_VF16_M4_MASK 2733 +#define RISCV_PseudoVFWADD_VF16_MF2 2734 +#define RISCV_PseudoVFWADD_VF16_MF2_MASK 2735 +#define RISCV_PseudoVFWADD_VF16_MF4 2736 +#define RISCV_PseudoVFWADD_VF16_MF4_MASK 2737 +#define RISCV_PseudoVFWADD_VF16_MF8 2738 +#define RISCV_PseudoVFWADD_VF16_MF8_MASK 2739 +#define RISCV_PseudoVFWADD_VF32_M1 2740 +#define RISCV_PseudoVFWADD_VF32_M1_MASK 2741 +#define RISCV_PseudoVFWADD_VF32_M2 2742 +#define RISCV_PseudoVFWADD_VF32_M2_MASK 2743 +#define RISCV_PseudoVFWADD_VF32_M4 2744 +#define RISCV_PseudoVFWADD_VF32_M4_MASK 2745 +#define RISCV_PseudoVFWADD_VF32_MF2 2746 +#define RISCV_PseudoVFWADD_VF32_MF2_MASK 2747 +#define RISCV_PseudoVFWADD_VF32_MF4 2748 +#define RISCV_PseudoVFWADD_VF32_MF4_MASK 2749 +#define RISCV_PseudoVFWADD_VF32_MF8 2750 +#define RISCV_PseudoVFWADD_VF32_MF8_MASK 2751 +#define RISCV_PseudoVFWADD_VV_M1 2752 +#define RISCV_PseudoVFWADD_VV_M1_MASK 2753 +#define RISCV_PseudoVFWADD_VV_M2 2754 +#define RISCV_PseudoVFWADD_VV_M2_MASK 2755 +#define RISCV_PseudoVFWADD_VV_M4 2756 +#define RISCV_PseudoVFWADD_VV_M4_MASK 2757 +#define RISCV_PseudoVFWADD_VV_MF2 2758 +#define RISCV_PseudoVFWADD_VV_MF2_MASK 2759 +#define RISCV_PseudoVFWADD_VV_MF4 2760 +#define RISCV_PseudoVFWADD_VV_MF4_MASK 2761 +#define RISCV_PseudoVFWADD_VV_MF8 2762 +#define RISCV_PseudoVFWADD_VV_MF8_MASK 2763 +#define RISCV_PseudoVFWADD_WF16_M1 2764 +#define RISCV_PseudoVFWADD_WF16_M1_MASK 2765 +#define RISCV_PseudoVFWADD_WF16_M2 2766 +#define RISCV_PseudoVFWADD_WF16_M2_MASK 2767 +#define RISCV_PseudoVFWADD_WF16_M4 2768 +#define RISCV_PseudoVFWADD_WF16_M4_MASK 2769 +#define RISCV_PseudoVFWADD_WF16_MF2 2770 +#define RISCV_PseudoVFWADD_WF16_MF2_MASK 2771 +#define RISCV_PseudoVFWADD_WF16_MF4 2772 +#define RISCV_PseudoVFWADD_WF16_MF4_MASK 2773 +#define RISCV_PseudoVFWADD_WF16_MF8 2774 +#define RISCV_PseudoVFWADD_WF16_MF8_MASK 2775 +#define RISCV_PseudoVFWADD_WF32_M1 2776 +#define RISCV_PseudoVFWADD_WF32_M1_MASK 2777 +#define RISCV_PseudoVFWADD_WF32_M2 2778 +#define RISCV_PseudoVFWADD_WF32_M2_MASK 2779 +#define RISCV_PseudoVFWADD_WF32_M4 2780 +#define RISCV_PseudoVFWADD_WF32_M4_MASK 2781 +#define RISCV_PseudoVFWADD_WF32_MF2 2782 +#define RISCV_PseudoVFWADD_WF32_MF2_MASK 2783 +#define RISCV_PseudoVFWADD_WF32_MF4 2784 +#define RISCV_PseudoVFWADD_WF32_MF4_MASK 2785 +#define RISCV_PseudoVFWADD_WF32_MF8 2786 +#define RISCV_PseudoVFWADD_WF32_MF8_MASK 2787 +#define RISCV_PseudoVFWADD_WV_M1 2788 +#define RISCV_PseudoVFWADD_WV_M1_MASK 2789 +#define RISCV_PseudoVFWADD_WV_M1_MASK_TIED 2790 +#define RISCV_PseudoVFWADD_WV_M1_TIED 2791 +#define RISCV_PseudoVFWADD_WV_M2 2792 +#define RISCV_PseudoVFWADD_WV_M2_MASK 2793 +#define RISCV_PseudoVFWADD_WV_M2_MASK_TIED 2794 +#define RISCV_PseudoVFWADD_WV_M2_TIED 2795 +#define RISCV_PseudoVFWADD_WV_M4 2796 +#define RISCV_PseudoVFWADD_WV_M4_MASK 2797 +#define RISCV_PseudoVFWADD_WV_M4_MASK_TIED 2798 +#define RISCV_PseudoVFWADD_WV_M4_TIED 2799 +#define RISCV_PseudoVFWADD_WV_MF2 2800 +#define RISCV_PseudoVFWADD_WV_MF2_MASK 2801 +#define RISCV_PseudoVFWADD_WV_MF2_MASK_TIED 2802 +#define RISCV_PseudoVFWADD_WV_MF2_TIED 2803 +#define RISCV_PseudoVFWADD_WV_MF4 2804 +#define RISCV_PseudoVFWADD_WV_MF4_MASK 2805 +#define RISCV_PseudoVFWADD_WV_MF4_MASK_TIED 2806 +#define RISCV_PseudoVFWADD_WV_MF4_TIED 2807 +#define RISCV_PseudoVFWADD_WV_MF8 2808 +#define RISCV_PseudoVFWADD_WV_MF8_MASK 2809 +#define RISCV_PseudoVFWADD_WV_MF8_MASK_TIED 2810 +#define RISCV_PseudoVFWADD_WV_MF8_TIED 2811 +#define RISCV_PseudoVFWCVT_F_F_V_M1 2812 +#define RISCV_PseudoVFWCVT_F_F_V_M1_MASK 2813 +#define RISCV_PseudoVFWCVT_F_F_V_M2 2814 +#define RISCV_PseudoVFWCVT_F_F_V_M2_MASK 2815 +#define RISCV_PseudoVFWCVT_F_F_V_M4 2816 +#define RISCV_PseudoVFWCVT_F_F_V_M4_MASK 2817 +#define RISCV_PseudoVFWCVT_F_F_V_MF2 2818 +#define RISCV_PseudoVFWCVT_F_F_V_MF2_MASK 2819 +#define RISCV_PseudoVFWCVT_F_F_V_MF4 2820 +#define RISCV_PseudoVFWCVT_F_F_V_MF4_MASK 2821 +#define RISCV_PseudoVFWCVT_F_F_V_MF8 2822 +#define RISCV_PseudoVFWCVT_F_F_V_MF8_MASK 2823 +#define RISCV_PseudoVFWCVT_F_XU_V_M1 2824 +#define RISCV_PseudoVFWCVT_F_XU_V_M1_MASK 2825 +#define RISCV_PseudoVFWCVT_F_XU_V_M2 2826 +#define RISCV_PseudoVFWCVT_F_XU_V_M2_MASK 2827 +#define RISCV_PseudoVFWCVT_F_XU_V_M4 2828 +#define RISCV_PseudoVFWCVT_F_XU_V_M4_MASK 2829 +#define RISCV_PseudoVFWCVT_F_XU_V_MF2 2830 +#define RISCV_PseudoVFWCVT_F_XU_V_MF2_MASK 2831 +#define RISCV_PseudoVFWCVT_F_XU_V_MF4 2832 +#define RISCV_PseudoVFWCVT_F_XU_V_MF4_MASK 2833 +#define RISCV_PseudoVFWCVT_F_XU_V_MF8 2834 +#define RISCV_PseudoVFWCVT_F_XU_V_MF8_MASK 2835 +#define RISCV_PseudoVFWCVT_F_X_V_M1 2836 +#define RISCV_PseudoVFWCVT_F_X_V_M1_MASK 2837 +#define RISCV_PseudoVFWCVT_F_X_V_M2 2838 +#define RISCV_PseudoVFWCVT_F_X_V_M2_MASK 2839 +#define RISCV_PseudoVFWCVT_F_X_V_M4 2840 +#define RISCV_PseudoVFWCVT_F_X_V_M4_MASK 2841 +#define RISCV_PseudoVFWCVT_F_X_V_MF2 2842 +#define RISCV_PseudoVFWCVT_F_X_V_MF2_MASK 2843 +#define RISCV_PseudoVFWCVT_F_X_V_MF4 2844 +#define RISCV_PseudoVFWCVT_F_X_V_MF4_MASK 2845 +#define RISCV_PseudoVFWCVT_F_X_V_MF8 2846 +#define RISCV_PseudoVFWCVT_F_X_V_MF8_MASK 2847 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_M1 2848 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_M1_MASK 2849 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_M2 2850 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_M2_MASK 2851 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_M4 2852 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_M4_MASK 2853 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_MF2 2854 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK 2855 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_MF4 2856 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK 2857 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_MF8 2858 +#define RISCV_PseudoVFWCVT_RTZ_XU_F_V_MF8_MASK 2859 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_M1 2860 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_M1_MASK 2861 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_M2 2862 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_M2_MASK 2863 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_M4 2864 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_M4_MASK 2865 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_MF2 2866 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_MF2_MASK 2867 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_MF4 2868 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_MF4_MASK 2869 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_MF8 2870 +#define RISCV_PseudoVFWCVT_RTZ_X_F_V_MF8_MASK 2871 +#define RISCV_PseudoVFWCVT_XU_F_V_M1 2872 +#define RISCV_PseudoVFWCVT_XU_F_V_M1_MASK 2873 +#define RISCV_PseudoVFWCVT_XU_F_V_M2 2874 +#define RISCV_PseudoVFWCVT_XU_F_V_M2_MASK 2875 +#define RISCV_PseudoVFWCVT_XU_F_V_M4 2876 +#define RISCV_PseudoVFWCVT_XU_F_V_M4_MASK 2877 +#define RISCV_PseudoVFWCVT_XU_F_V_MF2 2878 +#define RISCV_PseudoVFWCVT_XU_F_V_MF2_MASK 2879 +#define RISCV_PseudoVFWCVT_XU_F_V_MF4 2880 +#define RISCV_PseudoVFWCVT_XU_F_V_MF4_MASK 2881 +#define RISCV_PseudoVFWCVT_XU_F_V_MF8 2882 +#define RISCV_PseudoVFWCVT_XU_F_V_MF8_MASK 2883 +#define RISCV_PseudoVFWCVT_X_F_V_M1 2884 +#define RISCV_PseudoVFWCVT_X_F_V_M1_MASK 2885 +#define RISCV_PseudoVFWCVT_X_F_V_M2 2886 +#define RISCV_PseudoVFWCVT_X_F_V_M2_MASK 2887 +#define RISCV_PseudoVFWCVT_X_F_V_M4 2888 +#define RISCV_PseudoVFWCVT_X_F_V_M4_MASK 2889 +#define RISCV_PseudoVFWCVT_X_F_V_MF2 2890 +#define RISCV_PseudoVFWCVT_X_F_V_MF2_MASK 2891 +#define RISCV_PseudoVFWCVT_X_F_V_MF4 2892 +#define RISCV_PseudoVFWCVT_X_F_V_MF4_MASK 2893 +#define RISCV_PseudoVFWCVT_X_F_V_MF8 2894 +#define RISCV_PseudoVFWCVT_X_F_V_MF8_MASK 2895 +#define RISCV_PseudoVFWMACC_VF16_M1 2896 +#define RISCV_PseudoVFWMACC_VF16_M1_MASK 2897 +#define RISCV_PseudoVFWMACC_VF16_M2 2898 +#define RISCV_PseudoVFWMACC_VF16_M2_MASK 2899 +#define RISCV_PseudoVFWMACC_VF16_M4 2900 +#define RISCV_PseudoVFWMACC_VF16_M4_MASK 2901 +#define RISCV_PseudoVFWMACC_VF16_MF2 2902 +#define RISCV_PseudoVFWMACC_VF16_MF2_MASK 2903 +#define RISCV_PseudoVFWMACC_VF16_MF4 2904 +#define RISCV_PseudoVFWMACC_VF16_MF4_MASK 2905 +#define RISCV_PseudoVFWMACC_VF16_MF8 2906 +#define RISCV_PseudoVFWMACC_VF16_MF8_MASK 2907 +#define RISCV_PseudoVFWMACC_VF32_M1 2908 +#define RISCV_PseudoVFWMACC_VF32_M1_MASK 2909 +#define RISCV_PseudoVFWMACC_VF32_M2 2910 +#define RISCV_PseudoVFWMACC_VF32_M2_MASK 2911 +#define RISCV_PseudoVFWMACC_VF32_M4 2912 +#define RISCV_PseudoVFWMACC_VF32_M4_MASK 2913 +#define RISCV_PseudoVFWMACC_VF32_MF2 2914 +#define RISCV_PseudoVFWMACC_VF32_MF2_MASK 2915 +#define RISCV_PseudoVFWMACC_VF32_MF4 2916 +#define RISCV_PseudoVFWMACC_VF32_MF4_MASK 2917 +#define RISCV_PseudoVFWMACC_VF32_MF8 2918 +#define RISCV_PseudoVFWMACC_VF32_MF8_MASK 2919 +#define RISCV_PseudoVFWMACC_VV_M1 2920 +#define RISCV_PseudoVFWMACC_VV_M1_MASK 2921 +#define RISCV_PseudoVFWMACC_VV_M2 2922 +#define RISCV_PseudoVFWMACC_VV_M2_MASK 2923 +#define RISCV_PseudoVFWMACC_VV_M4 2924 +#define RISCV_PseudoVFWMACC_VV_M4_MASK 2925 +#define RISCV_PseudoVFWMACC_VV_MF2 2926 +#define RISCV_PseudoVFWMACC_VV_MF2_MASK 2927 +#define RISCV_PseudoVFWMACC_VV_MF4 2928 +#define RISCV_PseudoVFWMACC_VV_MF4_MASK 2929 +#define RISCV_PseudoVFWMACC_VV_MF8 2930 +#define RISCV_PseudoVFWMACC_VV_MF8_MASK 2931 +#define RISCV_PseudoVFWMSAC_VF16_M1 2932 +#define RISCV_PseudoVFWMSAC_VF16_M1_MASK 2933 +#define RISCV_PseudoVFWMSAC_VF16_M2 2934 +#define RISCV_PseudoVFWMSAC_VF16_M2_MASK 2935 +#define RISCV_PseudoVFWMSAC_VF16_M4 2936 +#define RISCV_PseudoVFWMSAC_VF16_M4_MASK 2937 +#define RISCV_PseudoVFWMSAC_VF16_MF2 2938 +#define RISCV_PseudoVFWMSAC_VF16_MF2_MASK 2939 +#define RISCV_PseudoVFWMSAC_VF16_MF4 2940 +#define RISCV_PseudoVFWMSAC_VF16_MF4_MASK 2941 +#define RISCV_PseudoVFWMSAC_VF16_MF8 2942 +#define RISCV_PseudoVFWMSAC_VF16_MF8_MASK 2943 +#define RISCV_PseudoVFWMSAC_VF32_M1 2944 +#define RISCV_PseudoVFWMSAC_VF32_M1_MASK 2945 +#define RISCV_PseudoVFWMSAC_VF32_M2 2946 +#define RISCV_PseudoVFWMSAC_VF32_M2_MASK 2947 +#define RISCV_PseudoVFWMSAC_VF32_M4 2948 +#define RISCV_PseudoVFWMSAC_VF32_M4_MASK 2949 +#define RISCV_PseudoVFWMSAC_VF32_MF2 2950 +#define RISCV_PseudoVFWMSAC_VF32_MF2_MASK 2951 +#define RISCV_PseudoVFWMSAC_VF32_MF4 2952 +#define RISCV_PseudoVFWMSAC_VF32_MF4_MASK 2953 +#define RISCV_PseudoVFWMSAC_VF32_MF8 2954 +#define RISCV_PseudoVFWMSAC_VF32_MF8_MASK 2955 +#define RISCV_PseudoVFWMSAC_VV_M1 2956 +#define RISCV_PseudoVFWMSAC_VV_M1_MASK 2957 +#define RISCV_PseudoVFWMSAC_VV_M2 2958 +#define RISCV_PseudoVFWMSAC_VV_M2_MASK 2959 +#define RISCV_PseudoVFWMSAC_VV_M4 2960 +#define RISCV_PseudoVFWMSAC_VV_M4_MASK 2961 +#define RISCV_PseudoVFWMSAC_VV_MF2 2962 +#define RISCV_PseudoVFWMSAC_VV_MF2_MASK 2963 +#define RISCV_PseudoVFWMSAC_VV_MF4 2964 +#define RISCV_PseudoVFWMSAC_VV_MF4_MASK 2965 +#define RISCV_PseudoVFWMSAC_VV_MF8 2966 +#define RISCV_PseudoVFWMSAC_VV_MF8_MASK 2967 +#define RISCV_PseudoVFWMUL_VF16_M1 2968 +#define RISCV_PseudoVFWMUL_VF16_M1_MASK 2969 +#define RISCV_PseudoVFWMUL_VF16_M2 2970 +#define RISCV_PseudoVFWMUL_VF16_M2_MASK 2971 +#define RISCV_PseudoVFWMUL_VF16_M4 2972 +#define RISCV_PseudoVFWMUL_VF16_M4_MASK 2973 +#define RISCV_PseudoVFWMUL_VF16_MF2 2974 +#define RISCV_PseudoVFWMUL_VF16_MF2_MASK 2975 +#define RISCV_PseudoVFWMUL_VF16_MF4 2976 +#define RISCV_PseudoVFWMUL_VF16_MF4_MASK 2977 +#define RISCV_PseudoVFWMUL_VF16_MF8 2978 +#define RISCV_PseudoVFWMUL_VF16_MF8_MASK 2979 +#define RISCV_PseudoVFWMUL_VF32_M1 2980 +#define RISCV_PseudoVFWMUL_VF32_M1_MASK 2981 +#define RISCV_PseudoVFWMUL_VF32_M2 2982 +#define RISCV_PseudoVFWMUL_VF32_M2_MASK 2983 +#define RISCV_PseudoVFWMUL_VF32_M4 2984 +#define RISCV_PseudoVFWMUL_VF32_M4_MASK 2985 +#define RISCV_PseudoVFWMUL_VF32_MF2 2986 +#define RISCV_PseudoVFWMUL_VF32_MF2_MASK 2987 +#define RISCV_PseudoVFWMUL_VF32_MF4 2988 +#define RISCV_PseudoVFWMUL_VF32_MF4_MASK 2989 +#define RISCV_PseudoVFWMUL_VF32_MF8 2990 +#define RISCV_PseudoVFWMUL_VF32_MF8_MASK 2991 +#define RISCV_PseudoVFWMUL_VV_M1 2992 +#define RISCV_PseudoVFWMUL_VV_M1_MASK 2993 +#define RISCV_PseudoVFWMUL_VV_M2 2994 +#define RISCV_PseudoVFWMUL_VV_M2_MASK 2995 +#define RISCV_PseudoVFWMUL_VV_M4 2996 +#define RISCV_PseudoVFWMUL_VV_M4_MASK 2997 +#define RISCV_PseudoVFWMUL_VV_MF2 2998 +#define RISCV_PseudoVFWMUL_VV_MF2_MASK 2999 +#define RISCV_PseudoVFWMUL_VV_MF4 3000 +#define RISCV_PseudoVFWMUL_VV_MF4_MASK 3001 +#define RISCV_PseudoVFWMUL_VV_MF8 3002 +#define RISCV_PseudoVFWMUL_VV_MF8_MASK 3003 +#define RISCV_PseudoVFWNMACC_VF16_M1 3004 +#define RISCV_PseudoVFWNMACC_VF16_M1_MASK 3005 +#define RISCV_PseudoVFWNMACC_VF16_M2 3006 +#define RISCV_PseudoVFWNMACC_VF16_M2_MASK 3007 +#define RISCV_PseudoVFWNMACC_VF16_M4 3008 +#define RISCV_PseudoVFWNMACC_VF16_M4_MASK 3009 +#define RISCV_PseudoVFWNMACC_VF16_MF2 3010 +#define RISCV_PseudoVFWNMACC_VF16_MF2_MASK 3011 +#define RISCV_PseudoVFWNMACC_VF16_MF4 3012 +#define RISCV_PseudoVFWNMACC_VF16_MF4_MASK 3013 +#define RISCV_PseudoVFWNMACC_VF16_MF8 3014 +#define RISCV_PseudoVFWNMACC_VF16_MF8_MASK 3015 +#define RISCV_PseudoVFWNMACC_VF32_M1 3016 +#define RISCV_PseudoVFWNMACC_VF32_M1_MASK 3017 +#define RISCV_PseudoVFWNMACC_VF32_M2 3018 +#define RISCV_PseudoVFWNMACC_VF32_M2_MASK 3019 +#define RISCV_PseudoVFWNMACC_VF32_M4 3020 +#define RISCV_PseudoVFWNMACC_VF32_M4_MASK 3021 +#define RISCV_PseudoVFWNMACC_VF32_MF2 3022 +#define RISCV_PseudoVFWNMACC_VF32_MF2_MASK 3023 +#define RISCV_PseudoVFWNMACC_VF32_MF4 3024 +#define RISCV_PseudoVFWNMACC_VF32_MF4_MASK 3025 +#define RISCV_PseudoVFWNMACC_VF32_MF8 3026 +#define RISCV_PseudoVFWNMACC_VF32_MF8_MASK 3027 +#define RISCV_PseudoVFWNMACC_VV_M1 3028 +#define RISCV_PseudoVFWNMACC_VV_M1_MASK 3029 +#define RISCV_PseudoVFWNMACC_VV_M2 3030 +#define RISCV_PseudoVFWNMACC_VV_M2_MASK 3031 +#define RISCV_PseudoVFWNMACC_VV_M4 3032 +#define RISCV_PseudoVFWNMACC_VV_M4_MASK 3033 +#define RISCV_PseudoVFWNMACC_VV_MF2 3034 +#define RISCV_PseudoVFWNMACC_VV_MF2_MASK 3035 +#define RISCV_PseudoVFWNMACC_VV_MF4 3036 +#define RISCV_PseudoVFWNMACC_VV_MF4_MASK 3037 +#define RISCV_PseudoVFWNMACC_VV_MF8 3038 +#define RISCV_PseudoVFWNMACC_VV_MF8_MASK 3039 +#define RISCV_PseudoVFWNMSAC_VF16_M1 3040 +#define RISCV_PseudoVFWNMSAC_VF16_M1_MASK 3041 +#define RISCV_PseudoVFWNMSAC_VF16_M2 3042 +#define RISCV_PseudoVFWNMSAC_VF16_M2_MASK 3043 +#define RISCV_PseudoVFWNMSAC_VF16_M4 3044 +#define RISCV_PseudoVFWNMSAC_VF16_M4_MASK 3045 +#define RISCV_PseudoVFWNMSAC_VF16_MF2 3046 +#define RISCV_PseudoVFWNMSAC_VF16_MF2_MASK 3047 +#define RISCV_PseudoVFWNMSAC_VF16_MF4 3048 +#define RISCV_PseudoVFWNMSAC_VF16_MF4_MASK 3049 +#define RISCV_PseudoVFWNMSAC_VF16_MF8 3050 +#define RISCV_PseudoVFWNMSAC_VF16_MF8_MASK 3051 +#define RISCV_PseudoVFWNMSAC_VF32_M1 3052 +#define RISCV_PseudoVFWNMSAC_VF32_M1_MASK 3053 +#define RISCV_PseudoVFWNMSAC_VF32_M2 3054 +#define RISCV_PseudoVFWNMSAC_VF32_M2_MASK 3055 +#define RISCV_PseudoVFWNMSAC_VF32_M4 3056 +#define RISCV_PseudoVFWNMSAC_VF32_M4_MASK 3057 +#define RISCV_PseudoVFWNMSAC_VF32_MF2 3058 +#define RISCV_PseudoVFWNMSAC_VF32_MF2_MASK 3059 +#define RISCV_PseudoVFWNMSAC_VF32_MF4 3060 +#define RISCV_PseudoVFWNMSAC_VF32_MF4_MASK 3061 +#define RISCV_PseudoVFWNMSAC_VF32_MF8 3062 +#define RISCV_PseudoVFWNMSAC_VF32_MF8_MASK 3063 +#define RISCV_PseudoVFWNMSAC_VV_M1 3064 +#define RISCV_PseudoVFWNMSAC_VV_M1_MASK 3065 +#define RISCV_PseudoVFWNMSAC_VV_M2 3066 +#define RISCV_PseudoVFWNMSAC_VV_M2_MASK 3067 +#define RISCV_PseudoVFWNMSAC_VV_M4 3068 +#define RISCV_PseudoVFWNMSAC_VV_M4_MASK 3069 +#define RISCV_PseudoVFWNMSAC_VV_MF2 3070 +#define RISCV_PseudoVFWNMSAC_VV_MF2_MASK 3071 +#define RISCV_PseudoVFWNMSAC_VV_MF4 3072 +#define RISCV_PseudoVFWNMSAC_VV_MF4_MASK 3073 +#define RISCV_PseudoVFWNMSAC_VV_MF8 3074 +#define RISCV_PseudoVFWNMSAC_VV_MF8_MASK 3075 +#define RISCV_PseudoVFWREDOSUM_VS_M1 3076 +#define RISCV_PseudoVFWREDOSUM_VS_M1_MASK 3077 +#define RISCV_PseudoVFWREDOSUM_VS_M2 3078 +#define RISCV_PseudoVFWREDOSUM_VS_M2_MASK 3079 +#define RISCV_PseudoVFWREDOSUM_VS_M4 3080 +#define RISCV_PseudoVFWREDOSUM_VS_M4_MASK 3081 +#define RISCV_PseudoVFWREDOSUM_VS_M8 3082 +#define RISCV_PseudoVFWREDOSUM_VS_M8_MASK 3083 +#define RISCV_PseudoVFWREDOSUM_VS_MF2 3084 +#define RISCV_PseudoVFWREDOSUM_VS_MF2_MASK 3085 +#define RISCV_PseudoVFWREDOSUM_VS_MF4 3086 +#define RISCV_PseudoVFWREDOSUM_VS_MF4_MASK 3087 +#define RISCV_PseudoVFWREDOSUM_VS_MF8 3088 +#define RISCV_PseudoVFWREDOSUM_VS_MF8_MASK 3089 +#define RISCV_PseudoVFWREDUSUM_VS_M1 3090 +#define RISCV_PseudoVFWREDUSUM_VS_M1_MASK 3091 +#define RISCV_PseudoVFWREDUSUM_VS_M2 3092 +#define RISCV_PseudoVFWREDUSUM_VS_M2_MASK 3093 +#define RISCV_PseudoVFWREDUSUM_VS_M4 3094 +#define RISCV_PseudoVFWREDUSUM_VS_M4_MASK 3095 +#define RISCV_PseudoVFWREDUSUM_VS_M8 3096 +#define RISCV_PseudoVFWREDUSUM_VS_M8_MASK 3097 +#define RISCV_PseudoVFWREDUSUM_VS_MF2 3098 +#define RISCV_PseudoVFWREDUSUM_VS_MF2_MASK 3099 +#define RISCV_PseudoVFWREDUSUM_VS_MF4 3100 +#define RISCV_PseudoVFWREDUSUM_VS_MF4_MASK 3101 +#define RISCV_PseudoVFWREDUSUM_VS_MF8 3102 +#define RISCV_PseudoVFWREDUSUM_VS_MF8_MASK 3103 +#define RISCV_PseudoVFWSUB_VF16_M1 3104 +#define RISCV_PseudoVFWSUB_VF16_M1_MASK 3105 +#define RISCV_PseudoVFWSUB_VF16_M2 3106 +#define RISCV_PseudoVFWSUB_VF16_M2_MASK 3107 +#define RISCV_PseudoVFWSUB_VF16_M4 3108 +#define RISCV_PseudoVFWSUB_VF16_M4_MASK 3109 +#define RISCV_PseudoVFWSUB_VF16_MF2 3110 +#define RISCV_PseudoVFWSUB_VF16_MF2_MASK 3111 +#define RISCV_PseudoVFWSUB_VF16_MF4 3112 +#define RISCV_PseudoVFWSUB_VF16_MF4_MASK 3113 +#define RISCV_PseudoVFWSUB_VF16_MF8 3114 +#define RISCV_PseudoVFWSUB_VF16_MF8_MASK 3115 +#define RISCV_PseudoVFWSUB_VF32_M1 3116 +#define RISCV_PseudoVFWSUB_VF32_M1_MASK 3117 +#define RISCV_PseudoVFWSUB_VF32_M2 3118 +#define RISCV_PseudoVFWSUB_VF32_M2_MASK 3119 +#define RISCV_PseudoVFWSUB_VF32_M4 3120 +#define RISCV_PseudoVFWSUB_VF32_M4_MASK 3121 +#define RISCV_PseudoVFWSUB_VF32_MF2 3122 +#define RISCV_PseudoVFWSUB_VF32_MF2_MASK 3123 +#define RISCV_PseudoVFWSUB_VF32_MF4 3124 +#define RISCV_PseudoVFWSUB_VF32_MF4_MASK 3125 +#define RISCV_PseudoVFWSUB_VF32_MF8 3126 +#define RISCV_PseudoVFWSUB_VF32_MF8_MASK 3127 +#define RISCV_PseudoVFWSUB_VV_M1 3128 +#define RISCV_PseudoVFWSUB_VV_M1_MASK 3129 +#define RISCV_PseudoVFWSUB_VV_M2 3130 +#define RISCV_PseudoVFWSUB_VV_M2_MASK 3131 +#define RISCV_PseudoVFWSUB_VV_M4 3132 +#define RISCV_PseudoVFWSUB_VV_M4_MASK 3133 +#define RISCV_PseudoVFWSUB_VV_MF2 3134 +#define RISCV_PseudoVFWSUB_VV_MF2_MASK 3135 +#define RISCV_PseudoVFWSUB_VV_MF4 3136 +#define RISCV_PseudoVFWSUB_VV_MF4_MASK 3137 +#define RISCV_PseudoVFWSUB_VV_MF8 3138 +#define RISCV_PseudoVFWSUB_VV_MF8_MASK 3139 +#define RISCV_PseudoVFWSUB_WF16_M1 3140 +#define RISCV_PseudoVFWSUB_WF16_M1_MASK 3141 +#define RISCV_PseudoVFWSUB_WF16_M2 3142 +#define RISCV_PseudoVFWSUB_WF16_M2_MASK 3143 +#define RISCV_PseudoVFWSUB_WF16_M4 3144 +#define RISCV_PseudoVFWSUB_WF16_M4_MASK 3145 +#define RISCV_PseudoVFWSUB_WF16_MF2 3146 +#define RISCV_PseudoVFWSUB_WF16_MF2_MASK 3147 +#define RISCV_PseudoVFWSUB_WF16_MF4 3148 +#define RISCV_PseudoVFWSUB_WF16_MF4_MASK 3149 +#define RISCV_PseudoVFWSUB_WF16_MF8 3150 +#define RISCV_PseudoVFWSUB_WF16_MF8_MASK 3151 +#define RISCV_PseudoVFWSUB_WF32_M1 3152 +#define RISCV_PseudoVFWSUB_WF32_M1_MASK 3153 +#define RISCV_PseudoVFWSUB_WF32_M2 3154 +#define RISCV_PseudoVFWSUB_WF32_M2_MASK 3155 +#define RISCV_PseudoVFWSUB_WF32_M4 3156 +#define RISCV_PseudoVFWSUB_WF32_M4_MASK 3157 +#define RISCV_PseudoVFWSUB_WF32_MF2 3158 +#define RISCV_PseudoVFWSUB_WF32_MF2_MASK 3159 +#define RISCV_PseudoVFWSUB_WF32_MF4 3160 +#define RISCV_PseudoVFWSUB_WF32_MF4_MASK 3161 +#define RISCV_PseudoVFWSUB_WF32_MF8 3162 +#define RISCV_PseudoVFWSUB_WF32_MF8_MASK 3163 +#define RISCV_PseudoVFWSUB_WV_M1 3164 +#define RISCV_PseudoVFWSUB_WV_M1_MASK 3165 +#define RISCV_PseudoVFWSUB_WV_M1_MASK_TIED 3166 +#define RISCV_PseudoVFWSUB_WV_M1_TIED 3167 +#define RISCV_PseudoVFWSUB_WV_M2 3168 +#define RISCV_PseudoVFWSUB_WV_M2_MASK 3169 +#define RISCV_PseudoVFWSUB_WV_M2_MASK_TIED 3170 +#define RISCV_PseudoVFWSUB_WV_M2_TIED 3171 +#define RISCV_PseudoVFWSUB_WV_M4 3172 +#define RISCV_PseudoVFWSUB_WV_M4_MASK 3173 +#define RISCV_PseudoVFWSUB_WV_M4_MASK_TIED 3174 +#define RISCV_PseudoVFWSUB_WV_M4_TIED 3175 +#define RISCV_PseudoVFWSUB_WV_MF2 3176 +#define RISCV_PseudoVFWSUB_WV_MF2_MASK 3177 +#define RISCV_PseudoVFWSUB_WV_MF2_MASK_TIED 3178 +#define RISCV_PseudoVFWSUB_WV_MF2_TIED 3179 +#define RISCV_PseudoVFWSUB_WV_MF4 3180 +#define RISCV_PseudoVFWSUB_WV_MF4_MASK 3181 +#define RISCV_PseudoVFWSUB_WV_MF4_MASK_TIED 3182 +#define RISCV_PseudoVFWSUB_WV_MF4_TIED 3183 +#define RISCV_PseudoVFWSUB_WV_MF8 3184 +#define RISCV_PseudoVFWSUB_WV_MF8_MASK 3185 +#define RISCV_PseudoVFWSUB_WV_MF8_MASK_TIED 3186 +#define RISCV_PseudoVFWSUB_WV_MF8_TIED 3187 +#define RISCV_PseudoVID_V_M1 3188 +#define RISCV_PseudoVID_V_M1_MASK 3189 +#define RISCV_PseudoVID_V_M2 3190 +#define RISCV_PseudoVID_V_M2_MASK 3191 +#define RISCV_PseudoVID_V_M4 3192 +#define RISCV_PseudoVID_V_M4_MASK 3193 +#define RISCV_PseudoVID_V_M8 3194 +#define RISCV_PseudoVID_V_M8_MASK 3195 +#define RISCV_PseudoVID_V_MF2 3196 +#define RISCV_PseudoVID_V_MF2_MASK 3197 +#define RISCV_PseudoVID_V_MF4 3198 +#define RISCV_PseudoVID_V_MF4_MASK 3199 +#define RISCV_PseudoVID_V_MF8 3200 +#define RISCV_PseudoVID_V_MF8_MASK 3201 +#define RISCV_PseudoVIOTA_M_M1 3202 +#define RISCV_PseudoVIOTA_M_M1_MASK 3203 +#define RISCV_PseudoVIOTA_M_M2 3204 +#define RISCV_PseudoVIOTA_M_M2_MASK 3205 +#define RISCV_PseudoVIOTA_M_M4 3206 +#define RISCV_PseudoVIOTA_M_M4_MASK 3207 +#define RISCV_PseudoVIOTA_M_M8 3208 +#define RISCV_PseudoVIOTA_M_M8_MASK 3209 +#define RISCV_PseudoVIOTA_M_MF2 3210 +#define RISCV_PseudoVIOTA_M_MF2_MASK 3211 +#define RISCV_PseudoVIOTA_M_MF4 3212 +#define RISCV_PseudoVIOTA_M_MF4_MASK 3213 +#define RISCV_PseudoVIOTA_M_MF8 3214 +#define RISCV_PseudoVIOTA_M_MF8_MASK 3215 +#define RISCV_PseudoVLE16FF_V_M1 3216 +#define RISCV_PseudoVLE16FF_V_M1_MASK 3217 +#define RISCV_PseudoVLE16FF_V_M2 3218 +#define RISCV_PseudoVLE16FF_V_M2_MASK 3219 +#define RISCV_PseudoVLE16FF_V_M4 3220 +#define RISCV_PseudoVLE16FF_V_M4_MASK 3221 +#define RISCV_PseudoVLE16FF_V_M8 3222 +#define RISCV_PseudoVLE16FF_V_M8_MASK 3223 +#define RISCV_PseudoVLE16FF_V_MF2 3224 +#define RISCV_PseudoVLE16FF_V_MF2_MASK 3225 +#define RISCV_PseudoVLE16FF_V_MF4 3226 +#define RISCV_PseudoVLE16FF_V_MF4_MASK 3227 +#define RISCV_PseudoVLE16_V_M1 3228 +#define RISCV_PseudoVLE16_V_M1_MASK 3229 +#define RISCV_PseudoVLE16_V_M2 3230 +#define RISCV_PseudoVLE16_V_M2_MASK 3231 +#define RISCV_PseudoVLE16_V_M4 3232 +#define RISCV_PseudoVLE16_V_M4_MASK 3233 +#define RISCV_PseudoVLE16_V_M8 3234 +#define RISCV_PseudoVLE16_V_M8_MASK 3235 +#define RISCV_PseudoVLE16_V_MF2 3236 +#define RISCV_PseudoVLE16_V_MF2_MASK 3237 +#define RISCV_PseudoVLE16_V_MF4 3238 +#define RISCV_PseudoVLE16_V_MF4_MASK 3239 +#define RISCV_PseudoVLE32FF_V_M1 3240 +#define RISCV_PseudoVLE32FF_V_M1_MASK 3241 +#define RISCV_PseudoVLE32FF_V_M2 3242 +#define RISCV_PseudoVLE32FF_V_M2_MASK 3243 +#define RISCV_PseudoVLE32FF_V_M4 3244 +#define RISCV_PseudoVLE32FF_V_M4_MASK 3245 +#define RISCV_PseudoVLE32FF_V_M8 3246 +#define RISCV_PseudoVLE32FF_V_M8_MASK 3247 +#define RISCV_PseudoVLE32FF_V_MF2 3248 +#define RISCV_PseudoVLE32FF_V_MF2_MASK 3249 +#define RISCV_PseudoVLE32_V_M1 3250 +#define RISCV_PseudoVLE32_V_M1_MASK 3251 +#define RISCV_PseudoVLE32_V_M2 3252 +#define RISCV_PseudoVLE32_V_M2_MASK 3253 +#define RISCV_PseudoVLE32_V_M4 3254 +#define RISCV_PseudoVLE32_V_M4_MASK 3255 +#define RISCV_PseudoVLE32_V_M8 3256 +#define RISCV_PseudoVLE32_V_M8_MASK 3257 +#define RISCV_PseudoVLE32_V_MF2 3258 +#define RISCV_PseudoVLE32_V_MF2_MASK 3259 +#define RISCV_PseudoVLE64FF_V_M1 3260 +#define RISCV_PseudoVLE64FF_V_M1_MASK 3261 +#define RISCV_PseudoVLE64FF_V_M2 3262 +#define RISCV_PseudoVLE64FF_V_M2_MASK 3263 +#define RISCV_PseudoVLE64FF_V_M4 3264 +#define RISCV_PseudoVLE64FF_V_M4_MASK 3265 +#define RISCV_PseudoVLE64FF_V_M8 3266 +#define RISCV_PseudoVLE64FF_V_M8_MASK 3267 +#define RISCV_PseudoVLE64_V_M1 3268 +#define RISCV_PseudoVLE64_V_M1_MASK 3269 +#define RISCV_PseudoVLE64_V_M2 3270 +#define RISCV_PseudoVLE64_V_M2_MASK 3271 +#define RISCV_PseudoVLE64_V_M4 3272 +#define RISCV_PseudoVLE64_V_M4_MASK 3273 +#define RISCV_PseudoVLE64_V_M8 3274 +#define RISCV_PseudoVLE64_V_M8_MASK 3275 +#define RISCV_PseudoVLE8FF_V_M1 3276 +#define RISCV_PseudoVLE8FF_V_M1_MASK 3277 +#define RISCV_PseudoVLE8FF_V_M2 3278 +#define RISCV_PseudoVLE8FF_V_M2_MASK 3279 +#define RISCV_PseudoVLE8FF_V_M4 3280 +#define RISCV_PseudoVLE8FF_V_M4_MASK 3281 +#define RISCV_PseudoVLE8FF_V_M8 3282 +#define RISCV_PseudoVLE8FF_V_M8_MASK 3283 +#define RISCV_PseudoVLE8FF_V_MF2 3284 +#define RISCV_PseudoVLE8FF_V_MF2_MASK 3285 +#define RISCV_PseudoVLE8FF_V_MF4 3286 +#define RISCV_PseudoVLE8FF_V_MF4_MASK 3287 +#define RISCV_PseudoVLE8FF_V_MF8 3288 +#define RISCV_PseudoVLE8FF_V_MF8_MASK 3289 +#define RISCV_PseudoVLE8_V_M1 3290 +#define RISCV_PseudoVLE8_V_M1_MASK 3291 +#define RISCV_PseudoVLE8_V_M2 3292 +#define RISCV_PseudoVLE8_V_M2_MASK 3293 +#define RISCV_PseudoVLE8_V_M4 3294 +#define RISCV_PseudoVLE8_V_M4_MASK 3295 +#define RISCV_PseudoVLE8_V_M8 3296 +#define RISCV_PseudoVLE8_V_M8_MASK 3297 +#define RISCV_PseudoVLE8_V_MF2 3298 +#define RISCV_PseudoVLE8_V_MF2_MASK 3299 +#define RISCV_PseudoVLE8_V_MF4 3300 +#define RISCV_PseudoVLE8_V_MF4_MASK 3301 +#define RISCV_PseudoVLE8_V_MF8 3302 +#define RISCV_PseudoVLE8_V_MF8_MASK 3303 +#define RISCV_PseudoVLM_V_B1 3304 +#define RISCV_PseudoVLM_V_B16 3305 +#define RISCV_PseudoVLM_V_B2 3306 +#define RISCV_PseudoVLM_V_B32 3307 +#define RISCV_PseudoVLM_V_B4 3308 +#define RISCV_PseudoVLM_V_B64 3309 +#define RISCV_PseudoVLM_V_B8 3310 +#define RISCV_PseudoVLOXEI16_V_M1_M1 3311 +#define RISCV_PseudoVLOXEI16_V_M1_M1_MASK 3312 +#define RISCV_PseudoVLOXEI16_V_M1_M2 3313 +#define RISCV_PseudoVLOXEI16_V_M1_M2_MASK 3314 +#define RISCV_PseudoVLOXEI16_V_M1_M4 3315 +#define RISCV_PseudoVLOXEI16_V_M1_M4_MASK 3316 +#define RISCV_PseudoVLOXEI16_V_M1_MF2 3317 +#define RISCV_PseudoVLOXEI16_V_M1_MF2_MASK 3318 +#define RISCV_PseudoVLOXEI16_V_M2_M1 3319 +#define RISCV_PseudoVLOXEI16_V_M2_M1_MASK 3320 +#define RISCV_PseudoVLOXEI16_V_M2_M2 3321 +#define RISCV_PseudoVLOXEI16_V_M2_M2_MASK 3322 +#define RISCV_PseudoVLOXEI16_V_M2_M4 3323 +#define RISCV_PseudoVLOXEI16_V_M2_M4_MASK 3324 +#define RISCV_PseudoVLOXEI16_V_M2_M8 3325 +#define RISCV_PseudoVLOXEI16_V_M2_M8_MASK 3326 +#define RISCV_PseudoVLOXEI16_V_M4_M2 3327 +#define RISCV_PseudoVLOXEI16_V_M4_M2_MASK 3328 +#define RISCV_PseudoVLOXEI16_V_M4_M4 3329 +#define RISCV_PseudoVLOXEI16_V_M4_M4_MASK 3330 +#define RISCV_PseudoVLOXEI16_V_M4_M8 3331 +#define RISCV_PseudoVLOXEI16_V_M4_M8_MASK 3332 +#define RISCV_PseudoVLOXEI16_V_M8_M4 3333 +#define RISCV_PseudoVLOXEI16_V_M8_M4_MASK 3334 +#define RISCV_PseudoVLOXEI16_V_M8_M8 3335 +#define RISCV_PseudoVLOXEI16_V_M8_M8_MASK 3336 +#define RISCV_PseudoVLOXEI16_V_MF2_M1 3337 +#define RISCV_PseudoVLOXEI16_V_MF2_M1_MASK 3338 +#define RISCV_PseudoVLOXEI16_V_MF2_M2 3339 +#define RISCV_PseudoVLOXEI16_V_MF2_M2_MASK 3340 +#define RISCV_PseudoVLOXEI16_V_MF2_MF2 3341 +#define RISCV_PseudoVLOXEI16_V_MF2_MF2_MASK 3342 +#define RISCV_PseudoVLOXEI16_V_MF2_MF4 3343 +#define RISCV_PseudoVLOXEI16_V_MF2_MF4_MASK 3344 +#define RISCV_PseudoVLOXEI16_V_MF4_M1 3345 +#define RISCV_PseudoVLOXEI16_V_MF4_M1_MASK 3346 +#define RISCV_PseudoVLOXEI16_V_MF4_MF2 3347 +#define RISCV_PseudoVLOXEI16_V_MF4_MF2_MASK 3348 +#define RISCV_PseudoVLOXEI16_V_MF4_MF4 3349 +#define RISCV_PseudoVLOXEI16_V_MF4_MF4_MASK 3350 +#define RISCV_PseudoVLOXEI16_V_MF4_MF8 3351 +#define RISCV_PseudoVLOXEI16_V_MF4_MF8_MASK 3352 +#define RISCV_PseudoVLOXEI32_V_M1_M1 3353 +#define RISCV_PseudoVLOXEI32_V_M1_M1_MASK 3354 +#define RISCV_PseudoVLOXEI32_V_M1_M2 3355 +#define RISCV_PseudoVLOXEI32_V_M1_M2_MASK 3356 +#define RISCV_PseudoVLOXEI32_V_M1_MF2 3357 +#define RISCV_PseudoVLOXEI32_V_M1_MF2_MASK 3358 +#define RISCV_PseudoVLOXEI32_V_M1_MF4 3359 +#define RISCV_PseudoVLOXEI32_V_M1_MF4_MASK 3360 +#define RISCV_PseudoVLOXEI32_V_M2_M1 3361 +#define RISCV_PseudoVLOXEI32_V_M2_M1_MASK 3362 +#define RISCV_PseudoVLOXEI32_V_M2_M2 3363 +#define RISCV_PseudoVLOXEI32_V_M2_M2_MASK 3364 +#define RISCV_PseudoVLOXEI32_V_M2_M4 3365 +#define RISCV_PseudoVLOXEI32_V_M2_M4_MASK 3366 +#define RISCV_PseudoVLOXEI32_V_M2_MF2 3367 +#define RISCV_PseudoVLOXEI32_V_M2_MF2_MASK 3368 +#define RISCV_PseudoVLOXEI32_V_M4_M1 3369 +#define RISCV_PseudoVLOXEI32_V_M4_M1_MASK 3370 +#define RISCV_PseudoVLOXEI32_V_M4_M2 3371 +#define RISCV_PseudoVLOXEI32_V_M4_M2_MASK 3372 +#define RISCV_PseudoVLOXEI32_V_M4_M4 3373 +#define RISCV_PseudoVLOXEI32_V_M4_M4_MASK 3374 +#define RISCV_PseudoVLOXEI32_V_M4_M8 3375 +#define RISCV_PseudoVLOXEI32_V_M4_M8_MASK 3376 +#define RISCV_PseudoVLOXEI32_V_M8_M2 3377 +#define RISCV_PseudoVLOXEI32_V_M8_M2_MASK 3378 +#define RISCV_PseudoVLOXEI32_V_M8_M4 3379 +#define RISCV_PseudoVLOXEI32_V_M8_M4_MASK 3380 +#define RISCV_PseudoVLOXEI32_V_M8_M8 3381 +#define RISCV_PseudoVLOXEI32_V_M8_M8_MASK 3382 +#define RISCV_PseudoVLOXEI32_V_MF2_M1 3383 +#define RISCV_PseudoVLOXEI32_V_MF2_M1_MASK 3384 +#define RISCV_PseudoVLOXEI32_V_MF2_MF2 3385 +#define RISCV_PseudoVLOXEI32_V_MF2_MF2_MASK 3386 +#define RISCV_PseudoVLOXEI32_V_MF2_MF4 3387 +#define RISCV_PseudoVLOXEI32_V_MF2_MF4_MASK 3388 +#define RISCV_PseudoVLOXEI32_V_MF2_MF8 3389 +#define RISCV_PseudoVLOXEI32_V_MF2_MF8_MASK 3390 +#define RISCV_PseudoVLOXEI64_V_M1_M1 3391 +#define RISCV_PseudoVLOXEI64_V_M1_M1_MASK 3392 +#define RISCV_PseudoVLOXEI64_V_M1_MF2 3393 +#define RISCV_PseudoVLOXEI64_V_M1_MF2_MASK 3394 +#define RISCV_PseudoVLOXEI64_V_M1_MF4 3395 +#define RISCV_PseudoVLOXEI64_V_M1_MF4_MASK 3396 +#define RISCV_PseudoVLOXEI64_V_M1_MF8 3397 +#define RISCV_PseudoVLOXEI64_V_M1_MF8_MASK 3398 +#define RISCV_PseudoVLOXEI64_V_M2_M1 3399 +#define RISCV_PseudoVLOXEI64_V_M2_M1_MASK 3400 +#define RISCV_PseudoVLOXEI64_V_M2_M2 3401 +#define RISCV_PseudoVLOXEI64_V_M2_M2_MASK 3402 +#define RISCV_PseudoVLOXEI64_V_M2_MF2 3403 +#define RISCV_PseudoVLOXEI64_V_M2_MF2_MASK 3404 +#define RISCV_PseudoVLOXEI64_V_M2_MF4 3405 +#define RISCV_PseudoVLOXEI64_V_M2_MF4_MASK 3406 +#define RISCV_PseudoVLOXEI64_V_M4_M1 3407 +#define RISCV_PseudoVLOXEI64_V_M4_M1_MASK 3408 +#define RISCV_PseudoVLOXEI64_V_M4_M2 3409 +#define RISCV_PseudoVLOXEI64_V_M4_M2_MASK 3410 +#define RISCV_PseudoVLOXEI64_V_M4_M4 3411 +#define RISCV_PseudoVLOXEI64_V_M4_M4_MASK 3412 +#define RISCV_PseudoVLOXEI64_V_M4_MF2 3413 +#define RISCV_PseudoVLOXEI64_V_M4_MF2_MASK 3414 +#define RISCV_PseudoVLOXEI64_V_M8_M1 3415 +#define RISCV_PseudoVLOXEI64_V_M8_M1_MASK 3416 +#define RISCV_PseudoVLOXEI64_V_M8_M2 3417 +#define RISCV_PseudoVLOXEI64_V_M8_M2_MASK 3418 +#define RISCV_PseudoVLOXEI64_V_M8_M4 3419 +#define RISCV_PseudoVLOXEI64_V_M8_M4_MASK 3420 +#define RISCV_PseudoVLOXEI64_V_M8_M8 3421 +#define RISCV_PseudoVLOXEI64_V_M8_M8_MASK 3422 +#define RISCV_PseudoVLOXEI8_V_M1_M1 3423 +#define RISCV_PseudoVLOXEI8_V_M1_M1_MASK 3424 +#define RISCV_PseudoVLOXEI8_V_M1_M2 3425 +#define RISCV_PseudoVLOXEI8_V_M1_M2_MASK 3426 +#define RISCV_PseudoVLOXEI8_V_M1_M4 3427 +#define RISCV_PseudoVLOXEI8_V_M1_M4_MASK 3428 +#define RISCV_PseudoVLOXEI8_V_M1_M8 3429 +#define RISCV_PseudoVLOXEI8_V_M1_M8_MASK 3430 +#define RISCV_PseudoVLOXEI8_V_M2_M2 3431 +#define RISCV_PseudoVLOXEI8_V_M2_M2_MASK 3432 +#define RISCV_PseudoVLOXEI8_V_M2_M4 3433 +#define RISCV_PseudoVLOXEI8_V_M2_M4_MASK 3434 +#define RISCV_PseudoVLOXEI8_V_M2_M8 3435 +#define RISCV_PseudoVLOXEI8_V_M2_M8_MASK 3436 +#define RISCV_PseudoVLOXEI8_V_M4_M4 3437 +#define RISCV_PseudoVLOXEI8_V_M4_M4_MASK 3438 +#define RISCV_PseudoVLOXEI8_V_M4_M8 3439 +#define RISCV_PseudoVLOXEI8_V_M4_M8_MASK 3440 +#define RISCV_PseudoVLOXEI8_V_M8_M8 3441 +#define RISCV_PseudoVLOXEI8_V_M8_M8_MASK 3442 +#define RISCV_PseudoVLOXEI8_V_MF2_M1 3443 +#define RISCV_PseudoVLOXEI8_V_MF2_M1_MASK 3444 +#define RISCV_PseudoVLOXEI8_V_MF2_M2 3445 +#define RISCV_PseudoVLOXEI8_V_MF2_M2_MASK 3446 +#define RISCV_PseudoVLOXEI8_V_MF2_M4 3447 +#define RISCV_PseudoVLOXEI8_V_MF2_M4_MASK 3448 +#define RISCV_PseudoVLOXEI8_V_MF2_MF2 3449 +#define RISCV_PseudoVLOXEI8_V_MF2_MF2_MASK 3450 +#define RISCV_PseudoVLOXEI8_V_MF4_M1 3451 +#define RISCV_PseudoVLOXEI8_V_MF4_M1_MASK 3452 +#define RISCV_PseudoVLOXEI8_V_MF4_M2 3453 +#define RISCV_PseudoVLOXEI8_V_MF4_M2_MASK 3454 +#define RISCV_PseudoVLOXEI8_V_MF4_MF2 3455 +#define RISCV_PseudoVLOXEI8_V_MF4_MF2_MASK 3456 +#define RISCV_PseudoVLOXEI8_V_MF4_MF4 3457 +#define RISCV_PseudoVLOXEI8_V_MF4_MF4_MASK 3458 +#define RISCV_PseudoVLOXEI8_V_MF8_M1 3459 +#define RISCV_PseudoVLOXEI8_V_MF8_M1_MASK 3460 +#define RISCV_PseudoVLOXEI8_V_MF8_MF2 3461 +#define RISCV_PseudoVLOXEI8_V_MF8_MF2_MASK 3462 +#define RISCV_PseudoVLOXEI8_V_MF8_MF4 3463 +#define RISCV_PseudoVLOXEI8_V_MF8_MF4_MASK 3464 +#define RISCV_PseudoVLOXEI8_V_MF8_MF8 3465 +#define RISCV_PseudoVLOXEI8_V_MF8_MF8_MASK 3466 +#define RISCV_PseudoVLOXSEG2EI16_V_M1_M1 3467 +#define RISCV_PseudoVLOXSEG2EI16_V_M1_M1_MASK 3468 +#define RISCV_PseudoVLOXSEG2EI16_V_M1_M2 3469 +#define RISCV_PseudoVLOXSEG2EI16_V_M1_M2_MASK 3470 +#define RISCV_PseudoVLOXSEG2EI16_V_M1_M4 3471 +#define RISCV_PseudoVLOXSEG2EI16_V_M1_M4_MASK 3472 +#define RISCV_PseudoVLOXSEG2EI16_V_M1_MF2 3473 +#define RISCV_PseudoVLOXSEG2EI16_V_M1_MF2_MASK 3474 +#define RISCV_PseudoVLOXSEG2EI16_V_M2_M1 3475 +#define RISCV_PseudoVLOXSEG2EI16_V_M2_M1_MASK 3476 +#define RISCV_PseudoVLOXSEG2EI16_V_M2_M2 3477 +#define RISCV_PseudoVLOXSEG2EI16_V_M2_M2_MASK 3478 +#define RISCV_PseudoVLOXSEG2EI16_V_M2_M4 3479 +#define RISCV_PseudoVLOXSEG2EI16_V_M2_M4_MASK 3480 +#define RISCV_PseudoVLOXSEG2EI16_V_M4_M2 3481 +#define RISCV_PseudoVLOXSEG2EI16_V_M4_M2_MASK 3482 +#define RISCV_PseudoVLOXSEG2EI16_V_M4_M4 3483 +#define RISCV_PseudoVLOXSEG2EI16_V_M4_M4_MASK 3484 +#define RISCV_PseudoVLOXSEG2EI16_V_M8_M4 3485 +#define RISCV_PseudoVLOXSEG2EI16_V_M8_M4_MASK 3486 +#define RISCV_PseudoVLOXSEG2EI16_V_MF2_M1 3487 +#define RISCV_PseudoVLOXSEG2EI16_V_MF2_M1_MASK 3488 +#define RISCV_PseudoVLOXSEG2EI16_V_MF2_M2 3489 +#define RISCV_PseudoVLOXSEG2EI16_V_MF2_M2_MASK 3490 +#define RISCV_PseudoVLOXSEG2EI16_V_MF2_MF2 3491 +#define RISCV_PseudoVLOXSEG2EI16_V_MF2_MF2_MASK 3492 +#define RISCV_PseudoVLOXSEG2EI16_V_MF2_MF4 3493 +#define RISCV_PseudoVLOXSEG2EI16_V_MF2_MF4_MASK 3494 +#define RISCV_PseudoVLOXSEG2EI16_V_MF4_M1 3495 +#define RISCV_PseudoVLOXSEG2EI16_V_MF4_M1_MASK 3496 +#define RISCV_PseudoVLOXSEG2EI16_V_MF4_MF2 3497 +#define RISCV_PseudoVLOXSEG2EI16_V_MF4_MF2_MASK 3498 +#define RISCV_PseudoVLOXSEG2EI16_V_MF4_MF4 3499 +#define RISCV_PseudoVLOXSEG2EI16_V_MF4_MF4_MASK 3500 +#define RISCV_PseudoVLOXSEG2EI16_V_MF4_MF8 3501 +#define RISCV_PseudoVLOXSEG2EI16_V_MF4_MF8_MASK 3502 +#define RISCV_PseudoVLOXSEG2EI32_V_M1_M1 3503 +#define RISCV_PseudoVLOXSEG2EI32_V_M1_M1_MASK 3504 +#define RISCV_PseudoVLOXSEG2EI32_V_M1_M2 3505 +#define RISCV_PseudoVLOXSEG2EI32_V_M1_M2_MASK 3506 +#define RISCV_PseudoVLOXSEG2EI32_V_M1_MF2 3507 +#define RISCV_PseudoVLOXSEG2EI32_V_M1_MF2_MASK 3508 +#define RISCV_PseudoVLOXSEG2EI32_V_M1_MF4 3509 +#define RISCV_PseudoVLOXSEG2EI32_V_M1_MF4_MASK 3510 +#define RISCV_PseudoVLOXSEG2EI32_V_M2_M1 3511 +#define RISCV_PseudoVLOXSEG2EI32_V_M2_M1_MASK 3512 +#define RISCV_PseudoVLOXSEG2EI32_V_M2_M2 3513 +#define RISCV_PseudoVLOXSEG2EI32_V_M2_M2_MASK 3514 +#define RISCV_PseudoVLOXSEG2EI32_V_M2_M4 3515 +#define RISCV_PseudoVLOXSEG2EI32_V_M2_M4_MASK 3516 +#define RISCV_PseudoVLOXSEG2EI32_V_M2_MF2 3517 +#define RISCV_PseudoVLOXSEG2EI32_V_M2_MF2_MASK 3518 +#define RISCV_PseudoVLOXSEG2EI32_V_M4_M1 3519 +#define RISCV_PseudoVLOXSEG2EI32_V_M4_M1_MASK 3520 +#define RISCV_PseudoVLOXSEG2EI32_V_M4_M2 3521 +#define RISCV_PseudoVLOXSEG2EI32_V_M4_M2_MASK 3522 +#define RISCV_PseudoVLOXSEG2EI32_V_M4_M4 3523 +#define RISCV_PseudoVLOXSEG2EI32_V_M4_M4_MASK 3524 +#define RISCV_PseudoVLOXSEG2EI32_V_M8_M2 3525 +#define RISCV_PseudoVLOXSEG2EI32_V_M8_M2_MASK 3526 +#define RISCV_PseudoVLOXSEG2EI32_V_M8_M4 3527 +#define RISCV_PseudoVLOXSEG2EI32_V_M8_M4_MASK 3528 +#define RISCV_PseudoVLOXSEG2EI32_V_MF2_M1 3529 +#define RISCV_PseudoVLOXSEG2EI32_V_MF2_M1_MASK 3530 +#define RISCV_PseudoVLOXSEG2EI32_V_MF2_MF2 3531 +#define RISCV_PseudoVLOXSEG2EI32_V_MF2_MF2_MASK 3532 +#define RISCV_PseudoVLOXSEG2EI32_V_MF2_MF4 3533 +#define RISCV_PseudoVLOXSEG2EI32_V_MF2_MF4_MASK 3534 +#define RISCV_PseudoVLOXSEG2EI32_V_MF2_MF8 3535 +#define RISCV_PseudoVLOXSEG2EI32_V_MF2_MF8_MASK 3536 +#define RISCV_PseudoVLOXSEG2EI64_V_M1_M1 3537 +#define RISCV_PseudoVLOXSEG2EI64_V_M1_M1_MASK 3538 +#define RISCV_PseudoVLOXSEG2EI64_V_M1_MF2 3539 +#define RISCV_PseudoVLOXSEG2EI64_V_M1_MF2_MASK 3540 +#define RISCV_PseudoVLOXSEG2EI64_V_M1_MF4 3541 +#define RISCV_PseudoVLOXSEG2EI64_V_M1_MF4_MASK 3542 +#define RISCV_PseudoVLOXSEG2EI64_V_M1_MF8 3543 +#define RISCV_PseudoVLOXSEG2EI64_V_M1_MF8_MASK 3544 +#define RISCV_PseudoVLOXSEG2EI64_V_M2_M1 3545 +#define RISCV_PseudoVLOXSEG2EI64_V_M2_M1_MASK 3546 +#define RISCV_PseudoVLOXSEG2EI64_V_M2_M2 3547 +#define RISCV_PseudoVLOXSEG2EI64_V_M2_M2_MASK 3548 +#define RISCV_PseudoVLOXSEG2EI64_V_M2_MF2 3549 +#define RISCV_PseudoVLOXSEG2EI64_V_M2_MF2_MASK 3550 +#define RISCV_PseudoVLOXSEG2EI64_V_M2_MF4 3551 +#define RISCV_PseudoVLOXSEG2EI64_V_M2_MF4_MASK 3552 +#define RISCV_PseudoVLOXSEG2EI64_V_M4_M1 3553 +#define RISCV_PseudoVLOXSEG2EI64_V_M4_M1_MASK 3554 +#define RISCV_PseudoVLOXSEG2EI64_V_M4_M2 3555 +#define RISCV_PseudoVLOXSEG2EI64_V_M4_M2_MASK 3556 +#define RISCV_PseudoVLOXSEG2EI64_V_M4_M4 3557 +#define RISCV_PseudoVLOXSEG2EI64_V_M4_M4_MASK 3558 +#define RISCV_PseudoVLOXSEG2EI64_V_M4_MF2 3559 +#define RISCV_PseudoVLOXSEG2EI64_V_M4_MF2_MASK 3560 +#define RISCV_PseudoVLOXSEG2EI64_V_M8_M1 3561 +#define RISCV_PseudoVLOXSEG2EI64_V_M8_M1_MASK 3562 +#define RISCV_PseudoVLOXSEG2EI64_V_M8_M2 3563 +#define RISCV_PseudoVLOXSEG2EI64_V_M8_M2_MASK 3564 +#define RISCV_PseudoVLOXSEG2EI64_V_M8_M4 3565 +#define RISCV_PseudoVLOXSEG2EI64_V_M8_M4_MASK 3566 +#define RISCV_PseudoVLOXSEG2EI8_V_M1_M1 3567 +#define RISCV_PseudoVLOXSEG2EI8_V_M1_M1_MASK 3568 +#define RISCV_PseudoVLOXSEG2EI8_V_M1_M2 3569 +#define RISCV_PseudoVLOXSEG2EI8_V_M1_M2_MASK 3570 +#define RISCV_PseudoVLOXSEG2EI8_V_M1_M4 3571 +#define RISCV_PseudoVLOXSEG2EI8_V_M1_M4_MASK 3572 +#define RISCV_PseudoVLOXSEG2EI8_V_M2_M2 3573 +#define RISCV_PseudoVLOXSEG2EI8_V_M2_M2_MASK 3574 +#define RISCV_PseudoVLOXSEG2EI8_V_M2_M4 3575 +#define RISCV_PseudoVLOXSEG2EI8_V_M2_M4_MASK 3576 +#define RISCV_PseudoVLOXSEG2EI8_V_M4_M4 3577 +#define RISCV_PseudoVLOXSEG2EI8_V_M4_M4_MASK 3578 +#define RISCV_PseudoVLOXSEG2EI8_V_MF2_M1 3579 +#define RISCV_PseudoVLOXSEG2EI8_V_MF2_M1_MASK 3580 +#define RISCV_PseudoVLOXSEG2EI8_V_MF2_M2 3581 +#define RISCV_PseudoVLOXSEG2EI8_V_MF2_M2_MASK 3582 +#define RISCV_PseudoVLOXSEG2EI8_V_MF2_M4 3583 +#define RISCV_PseudoVLOXSEG2EI8_V_MF2_M4_MASK 3584 +#define RISCV_PseudoVLOXSEG2EI8_V_MF2_MF2 3585 +#define RISCV_PseudoVLOXSEG2EI8_V_MF2_MF2_MASK 3586 +#define RISCV_PseudoVLOXSEG2EI8_V_MF4_M1 3587 +#define RISCV_PseudoVLOXSEG2EI8_V_MF4_M1_MASK 3588 +#define RISCV_PseudoVLOXSEG2EI8_V_MF4_M2 3589 +#define RISCV_PseudoVLOXSEG2EI8_V_MF4_M2_MASK 3590 +#define RISCV_PseudoVLOXSEG2EI8_V_MF4_MF2 3591 +#define RISCV_PseudoVLOXSEG2EI8_V_MF4_MF2_MASK 3592 +#define RISCV_PseudoVLOXSEG2EI8_V_MF4_MF4 3593 +#define RISCV_PseudoVLOXSEG2EI8_V_MF4_MF4_MASK 3594 +#define RISCV_PseudoVLOXSEG2EI8_V_MF8_M1 3595 +#define RISCV_PseudoVLOXSEG2EI8_V_MF8_M1_MASK 3596 +#define RISCV_PseudoVLOXSEG2EI8_V_MF8_MF2 3597 +#define RISCV_PseudoVLOXSEG2EI8_V_MF8_MF2_MASK 3598 +#define RISCV_PseudoVLOXSEG2EI8_V_MF8_MF4 3599 +#define RISCV_PseudoVLOXSEG2EI8_V_MF8_MF4_MASK 3600 +#define RISCV_PseudoVLOXSEG2EI8_V_MF8_MF8 3601 +#define RISCV_PseudoVLOXSEG2EI8_V_MF8_MF8_MASK 3602 +#define RISCV_PseudoVLOXSEG3EI16_V_M1_M1 3603 +#define RISCV_PseudoVLOXSEG3EI16_V_M1_M1_MASK 3604 +#define RISCV_PseudoVLOXSEG3EI16_V_M1_M2 3605 +#define RISCV_PseudoVLOXSEG3EI16_V_M1_M2_MASK 3606 +#define RISCV_PseudoVLOXSEG3EI16_V_M1_MF2 3607 +#define RISCV_PseudoVLOXSEG3EI16_V_M1_MF2_MASK 3608 +#define RISCV_PseudoVLOXSEG3EI16_V_M2_M1 3609 +#define RISCV_PseudoVLOXSEG3EI16_V_M2_M1_MASK 3610 +#define RISCV_PseudoVLOXSEG3EI16_V_M2_M2 3611 +#define RISCV_PseudoVLOXSEG3EI16_V_M2_M2_MASK 3612 +#define RISCV_PseudoVLOXSEG3EI16_V_M4_M2 3613 +#define RISCV_PseudoVLOXSEG3EI16_V_M4_M2_MASK 3614 +#define RISCV_PseudoVLOXSEG3EI16_V_MF2_M1 3615 +#define RISCV_PseudoVLOXSEG3EI16_V_MF2_M1_MASK 3616 +#define RISCV_PseudoVLOXSEG3EI16_V_MF2_M2 3617 +#define RISCV_PseudoVLOXSEG3EI16_V_MF2_M2_MASK 3618 +#define RISCV_PseudoVLOXSEG3EI16_V_MF2_MF2 3619 +#define RISCV_PseudoVLOXSEG3EI16_V_MF2_MF2_MASK 3620 +#define RISCV_PseudoVLOXSEG3EI16_V_MF2_MF4 3621 +#define RISCV_PseudoVLOXSEG3EI16_V_MF2_MF4_MASK 3622 +#define RISCV_PseudoVLOXSEG3EI16_V_MF4_M1 3623 +#define RISCV_PseudoVLOXSEG3EI16_V_MF4_M1_MASK 3624 +#define RISCV_PseudoVLOXSEG3EI16_V_MF4_MF2 3625 +#define RISCV_PseudoVLOXSEG3EI16_V_MF4_MF2_MASK 3626 +#define RISCV_PseudoVLOXSEG3EI16_V_MF4_MF4 3627 +#define RISCV_PseudoVLOXSEG3EI16_V_MF4_MF4_MASK 3628 +#define RISCV_PseudoVLOXSEG3EI16_V_MF4_MF8 3629 +#define RISCV_PseudoVLOXSEG3EI16_V_MF4_MF8_MASK 3630 +#define RISCV_PseudoVLOXSEG3EI32_V_M1_M1 3631 +#define RISCV_PseudoVLOXSEG3EI32_V_M1_M1_MASK 3632 +#define RISCV_PseudoVLOXSEG3EI32_V_M1_M2 3633 +#define RISCV_PseudoVLOXSEG3EI32_V_M1_M2_MASK 3634 +#define RISCV_PseudoVLOXSEG3EI32_V_M1_MF2 3635 +#define RISCV_PseudoVLOXSEG3EI32_V_M1_MF2_MASK 3636 +#define RISCV_PseudoVLOXSEG3EI32_V_M1_MF4 3637 +#define RISCV_PseudoVLOXSEG3EI32_V_M1_MF4_MASK 3638 +#define RISCV_PseudoVLOXSEG3EI32_V_M2_M1 3639 +#define RISCV_PseudoVLOXSEG3EI32_V_M2_M1_MASK 3640 +#define RISCV_PseudoVLOXSEG3EI32_V_M2_M2 3641 +#define RISCV_PseudoVLOXSEG3EI32_V_M2_M2_MASK 3642 +#define RISCV_PseudoVLOXSEG3EI32_V_M2_MF2 3643 +#define RISCV_PseudoVLOXSEG3EI32_V_M2_MF2_MASK 3644 +#define RISCV_PseudoVLOXSEG3EI32_V_M4_M1 3645 +#define RISCV_PseudoVLOXSEG3EI32_V_M4_M1_MASK 3646 +#define RISCV_PseudoVLOXSEG3EI32_V_M4_M2 3647 +#define RISCV_PseudoVLOXSEG3EI32_V_M4_M2_MASK 3648 +#define RISCV_PseudoVLOXSEG3EI32_V_M8_M2 3649 +#define RISCV_PseudoVLOXSEG3EI32_V_M8_M2_MASK 3650 +#define RISCV_PseudoVLOXSEG3EI32_V_MF2_M1 3651 +#define RISCV_PseudoVLOXSEG3EI32_V_MF2_M1_MASK 3652 +#define RISCV_PseudoVLOXSEG3EI32_V_MF2_MF2 3653 +#define RISCV_PseudoVLOXSEG3EI32_V_MF2_MF2_MASK 3654 +#define RISCV_PseudoVLOXSEG3EI32_V_MF2_MF4 3655 +#define RISCV_PseudoVLOXSEG3EI32_V_MF2_MF4_MASK 3656 +#define RISCV_PseudoVLOXSEG3EI32_V_MF2_MF8 3657 +#define RISCV_PseudoVLOXSEG3EI32_V_MF2_MF8_MASK 3658 +#define RISCV_PseudoVLOXSEG3EI64_V_M1_M1 3659 +#define RISCV_PseudoVLOXSEG3EI64_V_M1_M1_MASK 3660 +#define RISCV_PseudoVLOXSEG3EI64_V_M1_MF2 3661 +#define RISCV_PseudoVLOXSEG3EI64_V_M1_MF2_MASK 3662 +#define RISCV_PseudoVLOXSEG3EI64_V_M1_MF4 3663 +#define RISCV_PseudoVLOXSEG3EI64_V_M1_MF4_MASK 3664 +#define RISCV_PseudoVLOXSEG3EI64_V_M1_MF8 3665 +#define RISCV_PseudoVLOXSEG3EI64_V_M1_MF8_MASK 3666 +#define RISCV_PseudoVLOXSEG3EI64_V_M2_M1 3667 +#define RISCV_PseudoVLOXSEG3EI64_V_M2_M1_MASK 3668 +#define RISCV_PseudoVLOXSEG3EI64_V_M2_M2 3669 +#define RISCV_PseudoVLOXSEG3EI64_V_M2_M2_MASK 3670 +#define RISCV_PseudoVLOXSEG3EI64_V_M2_MF2 3671 +#define RISCV_PseudoVLOXSEG3EI64_V_M2_MF2_MASK 3672 +#define RISCV_PseudoVLOXSEG3EI64_V_M2_MF4 3673 +#define RISCV_PseudoVLOXSEG3EI64_V_M2_MF4_MASK 3674 +#define RISCV_PseudoVLOXSEG3EI64_V_M4_M1 3675 +#define RISCV_PseudoVLOXSEG3EI64_V_M4_M1_MASK 3676 +#define RISCV_PseudoVLOXSEG3EI64_V_M4_M2 3677 +#define RISCV_PseudoVLOXSEG3EI64_V_M4_M2_MASK 3678 +#define RISCV_PseudoVLOXSEG3EI64_V_M4_MF2 3679 +#define RISCV_PseudoVLOXSEG3EI64_V_M4_MF2_MASK 3680 +#define RISCV_PseudoVLOXSEG3EI64_V_M8_M1 3681 +#define RISCV_PseudoVLOXSEG3EI64_V_M8_M1_MASK 3682 +#define RISCV_PseudoVLOXSEG3EI64_V_M8_M2 3683 +#define RISCV_PseudoVLOXSEG3EI64_V_M8_M2_MASK 3684 +#define RISCV_PseudoVLOXSEG3EI8_V_M1_M1 3685 +#define RISCV_PseudoVLOXSEG3EI8_V_M1_M1_MASK 3686 +#define RISCV_PseudoVLOXSEG3EI8_V_M1_M2 3687 +#define RISCV_PseudoVLOXSEG3EI8_V_M1_M2_MASK 3688 +#define RISCV_PseudoVLOXSEG3EI8_V_M2_M2 3689 +#define RISCV_PseudoVLOXSEG3EI8_V_M2_M2_MASK 3690 +#define RISCV_PseudoVLOXSEG3EI8_V_MF2_M1 3691 +#define RISCV_PseudoVLOXSEG3EI8_V_MF2_M1_MASK 3692 +#define RISCV_PseudoVLOXSEG3EI8_V_MF2_M2 3693 +#define RISCV_PseudoVLOXSEG3EI8_V_MF2_M2_MASK 3694 +#define RISCV_PseudoVLOXSEG3EI8_V_MF2_MF2 3695 +#define RISCV_PseudoVLOXSEG3EI8_V_MF2_MF2_MASK 3696 +#define RISCV_PseudoVLOXSEG3EI8_V_MF4_M1 3697 +#define RISCV_PseudoVLOXSEG3EI8_V_MF4_M1_MASK 3698 +#define RISCV_PseudoVLOXSEG3EI8_V_MF4_M2 3699 +#define RISCV_PseudoVLOXSEG3EI8_V_MF4_M2_MASK 3700 +#define RISCV_PseudoVLOXSEG3EI8_V_MF4_MF2 3701 +#define RISCV_PseudoVLOXSEG3EI8_V_MF4_MF2_MASK 3702 +#define RISCV_PseudoVLOXSEG3EI8_V_MF4_MF4 3703 +#define RISCV_PseudoVLOXSEG3EI8_V_MF4_MF4_MASK 3704 +#define RISCV_PseudoVLOXSEG3EI8_V_MF8_M1 3705 +#define RISCV_PseudoVLOXSEG3EI8_V_MF8_M1_MASK 3706 +#define RISCV_PseudoVLOXSEG3EI8_V_MF8_MF2 3707 +#define RISCV_PseudoVLOXSEG3EI8_V_MF8_MF2_MASK 3708 +#define RISCV_PseudoVLOXSEG3EI8_V_MF8_MF4 3709 +#define RISCV_PseudoVLOXSEG3EI8_V_MF8_MF4_MASK 3710 +#define RISCV_PseudoVLOXSEG3EI8_V_MF8_MF8 3711 +#define RISCV_PseudoVLOXSEG3EI8_V_MF8_MF8_MASK 3712 +#define RISCV_PseudoVLOXSEG4EI16_V_M1_M1 3713 +#define RISCV_PseudoVLOXSEG4EI16_V_M1_M1_MASK 3714 +#define RISCV_PseudoVLOXSEG4EI16_V_M1_M2 3715 +#define RISCV_PseudoVLOXSEG4EI16_V_M1_M2_MASK 3716 +#define RISCV_PseudoVLOXSEG4EI16_V_M1_MF2 3717 +#define RISCV_PseudoVLOXSEG4EI16_V_M1_MF2_MASK 3718 +#define RISCV_PseudoVLOXSEG4EI16_V_M2_M1 3719 +#define RISCV_PseudoVLOXSEG4EI16_V_M2_M1_MASK 3720 +#define RISCV_PseudoVLOXSEG4EI16_V_M2_M2 3721 +#define RISCV_PseudoVLOXSEG4EI16_V_M2_M2_MASK 3722 +#define RISCV_PseudoVLOXSEG4EI16_V_M4_M2 3723 +#define RISCV_PseudoVLOXSEG4EI16_V_M4_M2_MASK 3724 +#define RISCV_PseudoVLOXSEG4EI16_V_MF2_M1 3725 +#define RISCV_PseudoVLOXSEG4EI16_V_MF2_M1_MASK 3726 +#define RISCV_PseudoVLOXSEG4EI16_V_MF2_M2 3727 +#define RISCV_PseudoVLOXSEG4EI16_V_MF2_M2_MASK 3728 +#define RISCV_PseudoVLOXSEG4EI16_V_MF2_MF2 3729 +#define RISCV_PseudoVLOXSEG4EI16_V_MF2_MF2_MASK 3730 +#define RISCV_PseudoVLOXSEG4EI16_V_MF2_MF4 3731 +#define RISCV_PseudoVLOXSEG4EI16_V_MF2_MF4_MASK 3732 +#define RISCV_PseudoVLOXSEG4EI16_V_MF4_M1 3733 +#define RISCV_PseudoVLOXSEG4EI16_V_MF4_M1_MASK 3734 +#define RISCV_PseudoVLOXSEG4EI16_V_MF4_MF2 3735 +#define RISCV_PseudoVLOXSEG4EI16_V_MF4_MF2_MASK 3736 +#define RISCV_PseudoVLOXSEG4EI16_V_MF4_MF4 3737 +#define RISCV_PseudoVLOXSEG4EI16_V_MF4_MF4_MASK 3738 +#define RISCV_PseudoVLOXSEG4EI16_V_MF4_MF8 3739 +#define RISCV_PseudoVLOXSEG4EI16_V_MF4_MF8_MASK 3740 +#define RISCV_PseudoVLOXSEG4EI32_V_M1_M1 3741 +#define RISCV_PseudoVLOXSEG4EI32_V_M1_M1_MASK 3742 +#define RISCV_PseudoVLOXSEG4EI32_V_M1_M2 3743 +#define RISCV_PseudoVLOXSEG4EI32_V_M1_M2_MASK 3744 +#define RISCV_PseudoVLOXSEG4EI32_V_M1_MF2 3745 +#define RISCV_PseudoVLOXSEG4EI32_V_M1_MF2_MASK 3746 +#define RISCV_PseudoVLOXSEG4EI32_V_M1_MF4 3747 +#define RISCV_PseudoVLOXSEG4EI32_V_M1_MF4_MASK 3748 +#define RISCV_PseudoVLOXSEG4EI32_V_M2_M1 3749 +#define RISCV_PseudoVLOXSEG4EI32_V_M2_M1_MASK 3750 +#define RISCV_PseudoVLOXSEG4EI32_V_M2_M2 3751 +#define RISCV_PseudoVLOXSEG4EI32_V_M2_M2_MASK 3752 +#define RISCV_PseudoVLOXSEG4EI32_V_M2_MF2 3753 +#define RISCV_PseudoVLOXSEG4EI32_V_M2_MF2_MASK 3754 +#define RISCV_PseudoVLOXSEG4EI32_V_M4_M1 3755 +#define RISCV_PseudoVLOXSEG4EI32_V_M4_M1_MASK 3756 +#define RISCV_PseudoVLOXSEG4EI32_V_M4_M2 3757 +#define RISCV_PseudoVLOXSEG4EI32_V_M4_M2_MASK 3758 +#define RISCV_PseudoVLOXSEG4EI32_V_M8_M2 3759 +#define RISCV_PseudoVLOXSEG4EI32_V_M8_M2_MASK 3760 +#define RISCV_PseudoVLOXSEG4EI32_V_MF2_M1 3761 +#define RISCV_PseudoVLOXSEG4EI32_V_MF2_M1_MASK 3762 +#define RISCV_PseudoVLOXSEG4EI32_V_MF2_MF2 3763 +#define RISCV_PseudoVLOXSEG4EI32_V_MF2_MF2_MASK 3764 +#define RISCV_PseudoVLOXSEG4EI32_V_MF2_MF4 3765 +#define RISCV_PseudoVLOXSEG4EI32_V_MF2_MF4_MASK 3766 +#define RISCV_PseudoVLOXSEG4EI32_V_MF2_MF8 3767 +#define RISCV_PseudoVLOXSEG4EI32_V_MF2_MF8_MASK 3768 +#define RISCV_PseudoVLOXSEG4EI64_V_M1_M1 3769 +#define RISCV_PseudoVLOXSEG4EI64_V_M1_M1_MASK 3770 +#define RISCV_PseudoVLOXSEG4EI64_V_M1_MF2 3771 +#define RISCV_PseudoVLOXSEG4EI64_V_M1_MF2_MASK 3772 +#define RISCV_PseudoVLOXSEG4EI64_V_M1_MF4 3773 +#define RISCV_PseudoVLOXSEG4EI64_V_M1_MF4_MASK 3774 +#define RISCV_PseudoVLOXSEG4EI64_V_M1_MF8 3775 +#define RISCV_PseudoVLOXSEG4EI64_V_M1_MF8_MASK 3776 +#define RISCV_PseudoVLOXSEG4EI64_V_M2_M1 3777 +#define RISCV_PseudoVLOXSEG4EI64_V_M2_M1_MASK 3778 +#define RISCV_PseudoVLOXSEG4EI64_V_M2_M2 3779 +#define RISCV_PseudoVLOXSEG4EI64_V_M2_M2_MASK 3780 +#define RISCV_PseudoVLOXSEG4EI64_V_M2_MF2 3781 +#define RISCV_PseudoVLOXSEG4EI64_V_M2_MF2_MASK 3782 +#define RISCV_PseudoVLOXSEG4EI64_V_M2_MF4 3783 +#define RISCV_PseudoVLOXSEG4EI64_V_M2_MF4_MASK 3784 +#define RISCV_PseudoVLOXSEG4EI64_V_M4_M1 3785 +#define RISCV_PseudoVLOXSEG4EI64_V_M4_M1_MASK 3786 +#define RISCV_PseudoVLOXSEG4EI64_V_M4_M2 3787 +#define RISCV_PseudoVLOXSEG4EI64_V_M4_M2_MASK 3788 +#define RISCV_PseudoVLOXSEG4EI64_V_M4_MF2 3789 +#define RISCV_PseudoVLOXSEG4EI64_V_M4_MF2_MASK 3790 +#define RISCV_PseudoVLOXSEG4EI64_V_M8_M1 3791 +#define RISCV_PseudoVLOXSEG4EI64_V_M8_M1_MASK 3792 +#define RISCV_PseudoVLOXSEG4EI64_V_M8_M2 3793 +#define RISCV_PseudoVLOXSEG4EI64_V_M8_M2_MASK 3794 +#define RISCV_PseudoVLOXSEG4EI8_V_M1_M1 3795 +#define RISCV_PseudoVLOXSEG4EI8_V_M1_M1_MASK 3796 +#define RISCV_PseudoVLOXSEG4EI8_V_M1_M2 3797 +#define RISCV_PseudoVLOXSEG4EI8_V_M1_M2_MASK 3798 +#define RISCV_PseudoVLOXSEG4EI8_V_M2_M2 3799 +#define RISCV_PseudoVLOXSEG4EI8_V_M2_M2_MASK 3800 +#define RISCV_PseudoVLOXSEG4EI8_V_MF2_M1 3801 +#define RISCV_PseudoVLOXSEG4EI8_V_MF2_M1_MASK 3802 +#define RISCV_PseudoVLOXSEG4EI8_V_MF2_M2 3803 +#define RISCV_PseudoVLOXSEG4EI8_V_MF2_M2_MASK 3804 +#define RISCV_PseudoVLOXSEG4EI8_V_MF2_MF2 3805 +#define RISCV_PseudoVLOXSEG4EI8_V_MF2_MF2_MASK 3806 +#define RISCV_PseudoVLOXSEG4EI8_V_MF4_M1 3807 +#define RISCV_PseudoVLOXSEG4EI8_V_MF4_M1_MASK 3808 +#define RISCV_PseudoVLOXSEG4EI8_V_MF4_M2 3809 +#define RISCV_PseudoVLOXSEG4EI8_V_MF4_M2_MASK 3810 +#define RISCV_PseudoVLOXSEG4EI8_V_MF4_MF2 3811 +#define RISCV_PseudoVLOXSEG4EI8_V_MF4_MF2_MASK 3812 +#define RISCV_PseudoVLOXSEG4EI8_V_MF4_MF4 3813 +#define RISCV_PseudoVLOXSEG4EI8_V_MF4_MF4_MASK 3814 +#define RISCV_PseudoVLOXSEG4EI8_V_MF8_M1 3815 +#define RISCV_PseudoVLOXSEG4EI8_V_MF8_M1_MASK 3816 +#define RISCV_PseudoVLOXSEG4EI8_V_MF8_MF2 3817 +#define RISCV_PseudoVLOXSEG4EI8_V_MF8_MF2_MASK 3818 +#define RISCV_PseudoVLOXSEG4EI8_V_MF8_MF4 3819 +#define RISCV_PseudoVLOXSEG4EI8_V_MF8_MF4_MASK 3820 +#define RISCV_PseudoVLOXSEG4EI8_V_MF8_MF8 3821 +#define RISCV_PseudoVLOXSEG4EI8_V_MF8_MF8_MASK 3822 +#define RISCV_PseudoVLOXSEG5EI16_V_M1_M1 3823 +#define RISCV_PseudoVLOXSEG5EI16_V_M1_M1_MASK 3824 +#define RISCV_PseudoVLOXSEG5EI16_V_M1_MF2 3825 +#define RISCV_PseudoVLOXSEG5EI16_V_M1_MF2_MASK 3826 +#define RISCV_PseudoVLOXSEG5EI16_V_M2_M1 3827 +#define RISCV_PseudoVLOXSEG5EI16_V_M2_M1_MASK 3828 +#define RISCV_PseudoVLOXSEG5EI16_V_MF2_M1 3829 +#define RISCV_PseudoVLOXSEG5EI16_V_MF2_M1_MASK 3830 +#define RISCV_PseudoVLOXSEG5EI16_V_MF2_MF2 3831 +#define RISCV_PseudoVLOXSEG5EI16_V_MF2_MF2_MASK 3832 +#define RISCV_PseudoVLOXSEG5EI16_V_MF2_MF4 3833 +#define RISCV_PseudoVLOXSEG5EI16_V_MF2_MF4_MASK 3834 +#define RISCV_PseudoVLOXSEG5EI16_V_MF4_M1 3835 +#define RISCV_PseudoVLOXSEG5EI16_V_MF4_M1_MASK 3836 +#define RISCV_PseudoVLOXSEG5EI16_V_MF4_MF2 3837 +#define RISCV_PseudoVLOXSEG5EI16_V_MF4_MF2_MASK 3838 +#define RISCV_PseudoVLOXSEG5EI16_V_MF4_MF4 3839 +#define RISCV_PseudoVLOXSEG5EI16_V_MF4_MF4_MASK 3840 +#define RISCV_PseudoVLOXSEG5EI16_V_MF4_MF8 3841 +#define RISCV_PseudoVLOXSEG5EI16_V_MF4_MF8_MASK 3842 +#define RISCV_PseudoVLOXSEG5EI32_V_M1_M1 3843 +#define RISCV_PseudoVLOXSEG5EI32_V_M1_M1_MASK 3844 +#define RISCV_PseudoVLOXSEG5EI32_V_M1_MF2 3845 +#define RISCV_PseudoVLOXSEG5EI32_V_M1_MF2_MASK 3846 +#define RISCV_PseudoVLOXSEG5EI32_V_M1_MF4 3847 +#define RISCV_PseudoVLOXSEG5EI32_V_M1_MF4_MASK 3848 +#define RISCV_PseudoVLOXSEG5EI32_V_M2_M1 3849 +#define RISCV_PseudoVLOXSEG5EI32_V_M2_M1_MASK 3850 +#define RISCV_PseudoVLOXSEG5EI32_V_M2_MF2 3851 +#define RISCV_PseudoVLOXSEG5EI32_V_M2_MF2_MASK 3852 +#define RISCV_PseudoVLOXSEG5EI32_V_M4_M1 3853 +#define RISCV_PseudoVLOXSEG5EI32_V_M4_M1_MASK 3854 +#define RISCV_PseudoVLOXSEG5EI32_V_MF2_M1 3855 +#define RISCV_PseudoVLOXSEG5EI32_V_MF2_M1_MASK 3856 +#define RISCV_PseudoVLOXSEG5EI32_V_MF2_MF2 3857 +#define RISCV_PseudoVLOXSEG5EI32_V_MF2_MF2_MASK 3858 +#define RISCV_PseudoVLOXSEG5EI32_V_MF2_MF4 3859 +#define RISCV_PseudoVLOXSEG5EI32_V_MF2_MF4_MASK 3860 +#define RISCV_PseudoVLOXSEG5EI32_V_MF2_MF8 3861 +#define RISCV_PseudoVLOXSEG5EI32_V_MF2_MF8_MASK 3862 +#define RISCV_PseudoVLOXSEG5EI64_V_M1_M1 3863 +#define RISCV_PseudoVLOXSEG5EI64_V_M1_M1_MASK 3864 +#define RISCV_PseudoVLOXSEG5EI64_V_M1_MF2 3865 +#define RISCV_PseudoVLOXSEG5EI64_V_M1_MF2_MASK 3866 +#define RISCV_PseudoVLOXSEG5EI64_V_M1_MF4 3867 +#define RISCV_PseudoVLOXSEG5EI64_V_M1_MF4_MASK 3868 +#define RISCV_PseudoVLOXSEG5EI64_V_M1_MF8 3869 +#define RISCV_PseudoVLOXSEG5EI64_V_M1_MF8_MASK 3870 +#define RISCV_PseudoVLOXSEG5EI64_V_M2_M1 3871 +#define RISCV_PseudoVLOXSEG5EI64_V_M2_M1_MASK 3872 +#define RISCV_PseudoVLOXSEG5EI64_V_M2_MF2 3873 +#define RISCV_PseudoVLOXSEG5EI64_V_M2_MF2_MASK 3874 +#define RISCV_PseudoVLOXSEG5EI64_V_M2_MF4 3875 +#define RISCV_PseudoVLOXSEG5EI64_V_M2_MF4_MASK 3876 +#define RISCV_PseudoVLOXSEG5EI64_V_M4_M1 3877 +#define RISCV_PseudoVLOXSEG5EI64_V_M4_M1_MASK 3878 +#define RISCV_PseudoVLOXSEG5EI64_V_M4_MF2 3879 +#define RISCV_PseudoVLOXSEG5EI64_V_M4_MF2_MASK 3880 +#define RISCV_PseudoVLOXSEG5EI64_V_M8_M1 3881 +#define RISCV_PseudoVLOXSEG5EI64_V_M8_M1_MASK 3882 +#define RISCV_PseudoVLOXSEG5EI8_V_M1_M1 3883 +#define RISCV_PseudoVLOXSEG5EI8_V_M1_M1_MASK 3884 +#define RISCV_PseudoVLOXSEG5EI8_V_MF2_M1 3885 +#define RISCV_PseudoVLOXSEG5EI8_V_MF2_M1_MASK 3886 +#define RISCV_PseudoVLOXSEG5EI8_V_MF2_MF2 3887 +#define RISCV_PseudoVLOXSEG5EI8_V_MF2_MF2_MASK 3888 +#define RISCV_PseudoVLOXSEG5EI8_V_MF4_M1 3889 +#define RISCV_PseudoVLOXSEG5EI8_V_MF4_M1_MASK 3890 +#define RISCV_PseudoVLOXSEG5EI8_V_MF4_MF2 3891 +#define RISCV_PseudoVLOXSEG5EI8_V_MF4_MF2_MASK 3892 +#define RISCV_PseudoVLOXSEG5EI8_V_MF4_MF4 3893 +#define RISCV_PseudoVLOXSEG5EI8_V_MF4_MF4_MASK 3894 +#define RISCV_PseudoVLOXSEG5EI8_V_MF8_M1 3895 +#define RISCV_PseudoVLOXSEG5EI8_V_MF8_M1_MASK 3896 +#define RISCV_PseudoVLOXSEG5EI8_V_MF8_MF2 3897 +#define RISCV_PseudoVLOXSEG5EI8_V_MF8_MF2_MASK 3898 +#define RISCV_PseudoVLOXSEG5EI8_V_MF8_MF4 3899 +#define RISCV_PseudoVLOXSEG5EI8_V_MF8_MF4_MASK 3900 +#define RISCV_PseudoVLOXSEG5EI8_V_MF8_MF8 3901 +#define RISCV_PseudoVLOXSEG5EI8_V_MF8_MF8_MASK 3902 +#define RISCV_PseudoVLOXSEG6EI16_V_M1_M1 3903 +#define RISCV_PseudoVLOXSEG6EI16_V_M1_M1_MASK 3904 +#define RISCV_PseudoVLOXSEG6EI16_V_M1_MF2 3905 +#define RISCV_PseudoVLOXSEG6EI16_V_M1_MF2_MASK 3906 +#define RISCV_PseudoVLOXSEG6EI16_V_M2_M1 3907 +#define RISCV_PseudoVLOXSEG6EI16_V_M2_M1_MASK 3908 +#define RISCV_PseudoVLOXSEG6EI16_V_MF2_M1 3909 +#define RISCV_PseudoVLOXSEG6EI16_V_MF2_M1_MASK 3910 +#define RISCV_PseudoVLOXSEG6EI16_V_MF2_MF2 3911 +#define RISCV_PseudoVLOXSEG6EI16_V_MF2_MF2_MASK 3912 +#define RISCV_PseudoVLOXSEG6EI16_V_MF2_MF4 3913 +#define RISCV_PseudoVLOXSEG6EI16_V_MF2_MF4_MASK 3914 +#define RISCV_PseudoVLOXSEG6EI16_V_MF4_M1 3915 +#define RISCV_PseudoVLOXSEG6EI16_V_MF4_M1_MASK 3916 +#define RISCV_PseudoVLOXSEG6EI16_V_MF4_MF2 3917 +#define RISCV_PseudoVLOXSEG6EI16_V_MF4_MF2_MASK 3918 +#define RISCV_PseudoVLOXSEG6EI16_V_MF4_MF4 3919 +#define RISCV_PseudoVLOXSEG6EI16_V_MF4_MF4_MASK 3920 +#define RISCV_PseudoVLOXSEG6EI16_V_MF4_MF8 3921 +#define RISCV_PseudoVLOXSEG6EI16_V_MF4_MF8_MASK 3922 +#define RISCV_PseudoVLOXSEG6EI32_V_M1_M1 3923 +#define RISCV_PseudoVLOXSEG6EI32_V_M1_M1_MASK 3924 +#define RISCV_PseudoVLOXSEG6EI32_V_M1_MF2 3925 +#define RISCV_PseudoVLOXSEG6EI32_V_M1_MF2_MASK 3926 +#define RISCV_PseudoVLOXSEG6EI32_V_M1_MF4 3927 +#define RISCV_PseudoVLOXSEG6EI32_V_M1_MF4_MASK 3928 +#define RISCV_PseudoVLOXSEG6EI32_V_M2_M1 3929 +#define RISCV_PseudoVLOXSEG6EI32_V_M2_M1_MASK 3930 +#define RISCV_PseudoVLOXSEG6EI32_V_M2_MF2 3931 +#define RISCV_PseudoVLOXSEG6EI32_V_M2_MF2_MASK 3932 +#define RISCV_PseudoVLOXSEG6EI32_V_M4_M1 3933 +#define RISCV_PseudoVLOXSEG6EI32_V_M4_M1_MASK 3934 +#define RISCV_PseudoVLOXSEG6EI32_V_MF2_M1 3935 +#define RISCV_PseudoVLOXSEG6EI32_V_MF2_M1_MASK 3936 +#define RISCV_PseudoVLOXSEG6EI32_V_MF2_MF2 3937 +#define RISCV_PseudoVLOXSEG6EI32_V_MF2_MF2_MASK 3938 +#define RISCV_PseudoVLOXSEG6EI32_V_MF2_MF4 3939 +#define RISCV_PseudoVLOXSEG6EI32_V_MF2_MF4_MASK 3940 +#define RISCV_PseudoVLOXSEG6EI32_V_MF2_MF8 3941 +#define RISCV_PseudoVLOXSEG6EI32_V_MF2_MF8_MASK 3942 +#define RISCV_PseudoVLOXSEG6EI64_V_M1_M1 3943 +#define RISCV_PseudoVLOXSEG6EI64_V_M1_M1_MASK 3944 +#define RISCV_PseudoVLOXSEG6EI64_V_M1_MF2 3945 +#define RISCV_PseudoVLOXSEG6EI64_V_M1_MF2_MASK 3946 +#define RISCV_PseudoVLOXSEG6EI64_V_M1_MF4 3947 +#define RISCV_PseudoVLOXSEG6EI64_V_M1_MF4_MASK 3948 +#define RISCV_PseudoVLOXSEG6EI64_V_M1_MF8 3949 +#define RISCV_PseudoVLOXSEG6EI64_V_M1_MF8_MASK 3950 +#define RISCV_PseudoVLOXSEG6EI64_V_M2_M1 3951 +#define RISCV_PseudoVLOXSEG6EI64_V_M2_M1_MASK 3952 +#define RISCV_PseudoVLOXSEG6EI64_V_M2_MF2 3953 +#define RISCV_PseudoVLOXSEG6EI64_V_M2_MF2_MASK 3954 +#define RISCV_PseudoVLOXSEG6EI64_V_M2_MF4 3955 +#define RISCV_PseudoVLOXSEG6EI64_V_M2_MF4_MASK 3956 +#define RISCV_PseudoVLOXSEG6EI64_V_M4_M1 3957 +#define RISCV_PseudoVLOXSEG6EI64_V_M4_M1_MASK 3958 +#define RISCV_PseudoVLOXSEG6EI64_V_M4_MF2 3959 +#define RISCV_PseudoVLOXSEG6EI64_V_M4_MF2_MASK 3960 +#define RISCV_PseudoVLOXSEG6EI64_V_M8_M1 3961 +#define RISCV_PseudoVLOXSEG6EI64_V_M8_M1_MASK 3962 +#define RISCV_PseudoVLOXSEG6EI8_V_M1_M1 3963 +#define RISCV_PseudoVLOXSEG6EI8_V_M1_M1_MASK 3964 +#define RISCV_PseudoVLOXSEG6EI8_V_MF2_M1 3965 +#define RISCV_PseudoVLOXSEG6EI8_V_MF2_M1_MASK 3966 +#define RISCV_PseudoVLOXSEG6EI8_V_MF2_MF2 3967 +#define RISCV_PseudoVLOXSEG6EI8_V_MF2_MF2_MASK 3968 +#define RISCV_PseudoVLOXSEG6EI8_V_MF4_M1 3969 +#define RISCV_PseudoVLOXSEG6EI8_V_MF4_M1_MASK 3970 +#define RISCV_PseudoVLOXSEG6EI8_V_MF4_MF2 3971 +#define RISCV_PseudoVLOXSEG6EI8_V_MF4_MF2_MASK 3972 +#define RISCV_PseudoVLOXSEG6EI8_V_MF4_MF4 3973 +#define RISCV_PseudoVLOXSEG6EI8_V_MF4_MF4_MASK 3974 +#define RISCV_PseudoVLOXSEG6EI8_V_MF8_M1 3975 +#define RISCV_PseudoVLOXSEG6EI8_V_MF8_M1_MASK 3976 +#define RISCV_PseudoVLOXSEG6EI8_V_MF8_MF2 3977 +#define RISCV_PseudoVLOXSEG6EI8_V_MF8_MF2_MASK 3978 +#define RISCV_PseudoVLOXSEG6EI8_V_MF8_MF4 3979 +#define RISCV_PseudoVLOXSEG6EI8_V_MF8_MF4_MASK 3980 +#define RISCV_PseudoVLOXSEG6EI8_V_MF8_MF8 3981 +#define RISCV_PseudoVLOXSEG6EI8_V_MF8_MF8_MASK 3982 +#define RISCV_PseudoVLOXSEG7EI16_V_M1_M1 3983 +#define RISCV_PseudoVLOXSEG7EI16_V_M1_M1_MASK 3984 +#define RISCV_PseudoVLOXSEG7EI16_V_M1_MF2 3985 +#define RISCV_PseudoVLOXSEG7EI16_V_M1_MF2_MASK 3986 +#define RISCV_PseudoVLOXSEG7EI16_V_M2_M1 3987 +#define RISCV_PseudoVLOXSEG7EI16_V_M2_M1_MASK 3988 +#define RISCV_PseudoVLOXSEG7EI16_V_MF2_M1 3989 +#define RISCV_PseudoVLOXSEG7EI16_V_MF2_M1_MASK 3990 +#define RISCV_PseudoVLOXSEG7EI16_V_MF2_MF2 3991 +#define RISCV_PseudoVLOXSEG7EI16_V_MF2_MF2_MASK 3992 +#define RISCV_PseudoVLOXSEG7EI16_V_MF2_MF4 3993 +#define RISCV_PseudoVLOXSEG7EI16_V_MF2_MF4_MASK 3994 +#define RISCV_PseudoVLOXSEG7EI16_V_MF4_M1 3995 +#define RISCV_PseudoVLOXSEG7EI16_V_MF4_M1_MASK 3996 +#define RISCV_PseudoVLOXSEG7EI16_V_MF4_MF2 3997 +#define RISCV_PseudoVLOXSEG7EI16_V_MF4_MF2_MASK 3998 +#define RISCV_PseudoVLOXSEG7EI16_V_MF4_MF4 3999 +#define RISCV_PseudoVLOXSEG7EI16_V_MF4_MF4_MASK 4000 +#define RISCV_PseudoVLOXSEG7EI16_V_MF4_MF8 4001 +#define RISCV_PseudoVLOXSEG7EI16_V_MF4_MF8_MASK 4002 +#define RISCV_PseudoVLOXSEG7EI32_V_M1_M1 4003 +#define RISCV_PseudoVLOXSEG7EI32_V_M1_M1_MASK 4004 +#define RISCV_PseudoVLOXSEG7EI32_V_M1_MF2 4005 +#define RISCV_PseudoVLOXSEG7EI32_V_M1_MF2_MASK 4006 +#define RISCV_PseudoVLOXSEG7EI32_V_M1_MF4 4007 +#define RISCV_PseudoVLOXSEG7EI32_V_M1_MF4_MASK 4008 +#define RISCV_PseudoVLOXSEG7EI32_V_M2_M1 4009 +#define RISCV_PseudoVLOXSEG7EI32_V_M2_M1_MASK 4010 +#define RISCV_PseudoVLOXSEG7EI32_V_M2_MF2 4011 +#define RISCV_PseudoVLOXSEG7EI32_V_M2_MF2_MASK 4012 +#define RISCV_PseudoVLOXSEG7EI32_V_M4_M1 4013 +#define RISCV_PseudoVLOXSEG7EI32_V_M4_M1_MASK 4014 +#define RISCV_PseudoVLOXSEG7EI32_V_MF2_M1 4015 +#define RISCV_PseudoVLOXSEG7EI32_V_MF2_M1_MASK 4016 +#define RISCV_PseudoVLOXSEG7EI32_V_MF2_MF2 4017 +#define RISCV_PseudoVLOXSEG7EI32_V_MF2_MF2_MASK 4018 +#define RISCV_PseudoVLOXSEG7EI32_V_MF2_MF4 4019 +#define RISCV_PseudoVLOXSEG7EI32_V_MF2_MF4_MASK 4020 +#define RISCV_PseudoVLOXSEG7EI32_V_MF2_MF8 4021 +#define RISCV_PseudoVLOXSEG7EI32_V_MF2_MF8_MASK 4022 +#define RISCV_PseudoVLOXSEG7EI64_V_M1_M1 4023 +#define RISCV_PseudoVLOXSEG7EI64_V_M1_M1_MASK 4024 +#define RISCV_PseudoVLOXSEG7EI64_V_M1_MF2 4025 +#define RISCV_PseudoVLOXSEG7EI64_V_M1_MF2_MASK 4026 +#define RISCV_PseudoVLOXSEG7EI64_V_M1_MF4 4027 +#define RISCV_PseudoVLOXSEG7EI64_V_M1_MF4_MASK 4028 +#define RISCV_PseudoVLOXSEG7EI64_V_M1_MF8 4029 +#define RISCV_PseudoVLOXSEG7EI64_V_M1_MF8_MASK 4030 +#define RISCV_PseudoVLOXSEG7EI64_V_M2_M1 4031 +#define RISCV_PseudoVLOXSEG7EI64_V_M2_M1_MASK 4032 +#define RISCV_PseudoVLOXSEG7EI64_V_M2_MF2 4033 +#define RISCV_PseudoVLOXSEG7EI64_V_M2_MF2_MASK 4034 +#define RISCV_PseudoVLOXSEG7EI64_V_M2_MF4 4035 +#define RISCV_PseudoVLOXSEG7EI64_V_M2_MF4_MASK 4036 +#define RISCV_PseudoVLOXSEG7EI64_V_M4_M1 4037 +#define RISCV_PseudoVLOXSEG7EI64_V_M4_M1_MASK 4038 +#define RISCV_PseudoVLOXSEG7EI64_V_M4_MF2 4039 +#define RISCV_PseudoVLOXSEG7EI64_V_M4_MF2_MASK 4040 +#define RISCV_PseudoVLOXSEG7EI64_V_M8_M1 4041 +#define RISCV_PseudoVLOXSEG7EI64_V_M8_M1_MASK 4042 +#define RISCV_PseudoVLOXSEG7EI8_V_M1_M1 4043 +#define RISCV_PseudoVLOXSEG7EI8_V_M1_M1_MASK 4044 +#define RISCV_PseudoVLOXSEG7EI8_V_MF2_M1 4045 +#define RISCV_PseudoVLOXSEG7EI8_V_MF2_M1_MASK 4046 +#define RISCV_PseudoVLOXSEG7EI8_V_MF2_MF2 4047 +#define RISCV_PseudoVLOXSEG7EI8_V_MF2_MF2_MASK 4048 +#define RISCV_PseudoVLOXSEG7EI8_V_MF4_M1 4049 +#define RISCV_PseudoVLOXSEG7EI8_V_MF4_M1_MASK 4050 +#define RISCV_PseudoVLOXSEG7EI8_V_MF4_MF2 4051 +#define RISCV_PseudoVLOXSEG7EI8_V_MF4_MF2_MASK 4052 +#define RISCV_PseudoVLOXSEG7EI8_V_MF4_MF4 4053 +#define RISCV_PseudoVLOXSEG7EI8_V_MF4_MF4_MASK 4054 +#define RISCV_PseudoVLOXSEG7EI8_V_MF8_M1 4055 +#define RISCV_PseudoVLOXSEG7EI8_V_MF8_M1_MASK 4056 +#define RISCV_PseudoVLOXSEG7EI8_V_MF8_MF2 4057 +#define RISCV_PseudoVLOXSEG7EI8_V_MF8_MF2_MASK 4058 +#define RISCV_PseudoVLOXSEG7EI8_V_MF8_MF4 4059 +#define RISCV_PseudoVLOXSEG7EI8_V_MF8_MF4_MASK 4060 +#define RISCV_PseudoVLOXSEG7EI8_V_MF8_MF8 4061 +#define RISCV_PseudoVLOXSEG7EI8_V_MF8_MF8_MASK 4062 +#define RISCV_PseudoVLOXSEG8EI16_V_M1_M1 4063 +#define RISCV_PseudoVLOXSEG8EI16_V_M1_M1_MASK 4064 +#define RISCV_PseudoVLOXSEG8EI16_V_M1_MF2 4065 +#define RISCV_PseudoVLOXSEG8EI16_V_M1_MF2_MASK 4066 +#define RISCV_PseudoVLOXSEG8EI16_V_M2_M1 4067 +#define RISCV_PseudoVLOXSEG8EI16_V_M2_M1_MASK 4068 +#define RISCV_PseudoVLOXSEG8EI16_V_MF2_M1 4069 +#define RISCV_PseudoVLOXSEG8EI16_V_MF2_M1_MASK 4070 +#define RISCV_PseudoVLOXSEG8EI16_V_MF2_MF2 4071 +#define RISCV_PseudoVLOXSEG8EI16_V_MF2_MF2_MASK 4072 +#define RISCV_PseudoVLOXSEG8EI16_V_MF2_MF4 4073 +#define RISCV_PseudoVLOXSEG8EI16_V_MF2_MF4_MASK 4074 +#define RISCV_PseudoVLOXSEG8EI16_V_MF4_M1 4075 +#define RISCV_PseudoVLOXSEG8EI16_V_MF4_M1_MASK 4076 +#define RISCV_PseudoVLOXSEG8EI16_V_MF4_MF2 4077 +#define RISCV_PseudoVLOXSEG8EI16_V_MF4_MF2_MASK 4078 +#define RISCV_PseudoVLOXSEG8EI16_V_MF4_MF4 4079 +#define RISCV_PseudoVLOXSEG8EI16_V_MF4_MF4_MASK 4080 +#define RISCV_PseudoVLOXSEG8EI16_V_MF4_MF8 4081 +#define RISCV_PseudoVLOXSEG8EI16_V_MF4_MF8_MASK 4082 +#define RISCV_PseudoVLOXSEG8EI32_V_M1_M1 4083 +#define RISCV_PseudoVLOXSEG8EI32_V_M1_M1_MASK 4084 +#define RISCV_PseudoVLOXSEG8EI32_V_M1_MF2 4085 +#define RISCV_PseudoVLOXSEG8EI32_V_M1_MF2_MASK 4086 +#define RISCV_PseudoVLOXSEG8EI32_V_M1_MF4 4087 +#define RISCV_PseudoVLOXSEG8EI32_V_M1_MF4_MASK 4088 +#define RISCV_PseudoVLOXSEG8EI32_V_M2_M1 4089 +#define RISCV_PseudoVLOXSEG8EI32_V_M2_M1_MASK 4090 +#define RISCV_PseudoVLOXSEG8EI32_V_M2_MF2 4091 +#define RISCV_PseudoVLOXSEG8EI32_V_M2_MF2_MASK 4092 +#define RISCV_PseudoVLOXSEG8EI32_V_M4_M1 4093 +#define RISCV_PseudoVLOXSEG8EI32_V_M4_M1_MASK 4094 +#define RISCV_PseudoVLOXSEG8EI32_V_MF2_M1 4095 +#define RISCV_PseudoVLOXSEG8EI32_V_MF2_M1_MASK 4096 +#define RISCV_PseudoVLOXSEG8EI32_V_MF2_MF2 4097 +#define RISCV_PseudoVLOXSEG8EI32_V_MF2_MF2_MASK 4098 +#define RISCV_PseudoVLOXSEG8EI32_V_MF2_MF4 4099 +#define RISCV_PseudoVLOXSEG8EI32_V_MF2_MF4_MASK 4100 +#define RISCV_PseudoVLOXSEG8EI32_V_MF2_MF8 4101 +#define RISCV_PseudoVLOXSEG8EI32_V_MF2_MF8_MASK 4102 +#define RISCV_PseudoVLOXSEG8EI64_V_M1_M1 4103 +#define RISCV_PseudoVLOXSEG8EI64_V_M1_M1_MASK 4104 +#define RISCV_PseudoVLOXSEG8EI64_V_M1_MF2 4105 +#define RISCV_PseudoVLOXSEG8EI64_V_M1_MF2_MASK 4106 +#define RISCV_PseudoVLOXSEG8EI64_V_M1_MF4 4107 +#define RISCV_PseudoVLOXSEG8EI64_V_M1_MF4_MASK 4108 +#define RISCV_PseudoVLOXSEG8EI64_V_M1_MF8 4109 +#define RISCV_PseudoVLOXSEG8EI64_V_M1_MF8_MASK 4110 +#define RISCV_PseudoVLOXSEG8EI64_V_M2_M1 4111 +#define RISCV_PseudoVLOXSEG8EI64_V_M2_M1_MASK 4112 +#define RISCV_PseudoVLOXSEG8EI64_V_M2_MF2 4113 +#define RISCV_PseudoVLOXSEG8EI64_V_M2_MF2_MASK 4114 +#define RISCV_PseudoVLOXSEG8EI64_V_M2_MF4 4115 +#define RISCV_PseudoVLOXSEG8EI64_V_M2_MF4_MASK 4116 +#define RISCV_PseudoVLOXSEG8EI64_V_M4_M1 4117 +#define RISCV_PseudoVLOXSEG8EI64_V_M4_M1_MASK 4118 +#define RISCV_PseudoVLOXSEG8EI64_V_M4_MF2 4119 +#define RISCV_PseudoVLOXSEG8EI64_V_M4_MF2_MASK 4120 +#define RISCV_PseudoVLOXSEG8EI64_V_M8_M1 4121 +#define RISCV_PseudoVLOXSEG8EI64_V_M8_M1_MASK 4122 +#define RISCV_PseudoVLOXSEG8EI8_V_M1_M1 4123 +#define RISCV_PseudoVLOXSEG8EI8_V_M1_M1_MASK 4124 +#define RISCV_PseudoVLOXSEG8EI8_V_MF2_M1 4125 +#define RISCV_PseudoVLOXSEG8EI8_V_MF2_M1_MASK 4126 +#define RISCV_PseudoVLOXSEG8EI8_V_MF2_MF2 4127 +#define RISCV_PseudoVLOXSEG8EI8_V_MF2_MF2_MASK 4128 +#define RISCV_PseudoVLOXSEG8EI8_V_MF4_M1 4129 +#define RISCV_PseudoVLOXSEG8EI8_V_MF4_M1_MASK 4130 +#define RISCV_PseudoVLOXSEG8EI8_V_MF4_MF2 4131 +#define RISCV_PseudoVLOXSEG8EI8_V_MF4_MF2_MASK 4132 +#define RISCV_PseudoVLOXSEG8EI8_V_MF4_MF4 4133 +#define RISCV_PseudoVLOXSEG8EI8_V_MF4_MF4_MASK 4134 +#define RISCV_PseudoVLOXSEG8EI8_V_MF8_M1 4135 +#define RISCV_PseudoVLOXSEG8EI8_V_MF8_M1_MASK 4136 +#define RISCV_PseudoVLOXSEG8EI8_V_MF8_MF2 4137 +#define RISCV_PseudoVLOXSEG8EI8_V_MF8_MF2_MASK 4138 +#define RISCV_PseudoVLOXSEG8EI8_V_MF8_MF4 4139 +#define RISCV_PseudoVLOXSEG8EI8_V_MF8_MF4_MASK 4140 +#define RISCV_PseudoVLOXSEG8EI8_V_MF8_MF8 4141 +#define RISCV_PseudoVLOXSEG8EI8_V_MF8_MF8_MASK 4142 +#define RISCV_PseudoVLSE16_V_M1 4143 +#define RISCV_PseudoVLSE16_V_M1_MASK 4144 +#define RISCV_PseudoVLSE16_V_M2 4145 +#define RISCV_PseudoVLSE16_V_M2_MASK 4146 +#define RISCV_PseudoVLSE16_V_M4 4147 +#define RISCV_PseudoVLSE16_V_M4_MASK 4148 +#define RISCV_PseudoVLSE16_V_M8 4149 +#define RISCV_PseudoVLSE16_V_M8_MASK 4150 +#define RISCV_PseudoVLSE16_V_MF2 4151 +#define RISCV_PseudoVLSE16_V_MF2_MASK 4152 +#define RISCV_PseudoVLSE16_V_MF4 4153 +#define RISCV_PseudoVLSE16_V_MF4_MASK 4154 +#define RISCV_PseudoVLSE32_V_M1 4155 +#define RISCV_PseudoVLSE32_V_M1_MASK 4156 +#define RISCV_PseudoVLSE32_V_M2 4157 +#define RISCV_PseudoVLSE32_V_M2_MASK 4158 +#define RISCV_PseudoVLSE32_V_M4 4159 +#define RISCV_PseudoVLSE32_V_M4_MASK 4160 +#define RISCV_PseudoVLSE32_V_M8 4161 +#define RISCV_PseudoVLSE32_V_M8_MASK 4162 +#define RISCV_PseudoVLSE32_V_MF2 4163 +#define RISCV_PseudoVLSE32_V_MF2_MASK 4164 +#define RISCV_PseudoVLSE64_V_M1 4165 +#define RISCV_PseudoVLSE64_V_M1_MASK 4166 +#define RISCV_PseudoVLSE64_V_M2 4167 +#define RISCV_PseudoVLSE64_V_M2_MASK 4168 +#define RISCV_PseudoVLSE64_V_M4 4169 +#define RISCV_PseudoVLSE64_V_M4_MASK 4170 +#define RISCV_PseudoVLSE64_V_M8 4171 +#define RISCV_PseudoVLSE64_V_M8_MASK 4172 +#define RISCV_PseudoVLSE8_V_M1 4173 +#define RISCV_PseudoVLSE8_V_M1_MASK 4174 +#define RISCV_PseudoVLSE8_V_M2 4175 +#define RISCV_PseudoVLSE8_V_M2_MASK 4176 +#define RISCV_PseudoVLSE8_V_M4 4177 +#define RISCV_PseudoVLSE8_V_M4_MASK 4178 +#define RISCV_PseudoVLSE8_V_M8 4179 +#define RISCV_PseudoVLSE8_V_M8_MASK 4180 +#define RISCV_PseudoVLSE8_V_MF2 4181 +#define RISCV_PseudoVLSE8_V_MF2_MASK 4182 +#define RISCV_PseudoVLSE8_V_MF4 4183 +#define RISCV_PseudoVLSE8_V_MF4_MASK 4184 +#define RISCV_PseudoVLSE8_V_MF8 4185 +#define RISCV_PseudoVLSE8_V_MF8_MASK 4186 +#define RISCV_PseudoVLSEG2E16FF_V_M1 4187 +#define RISCV_PseudoVLSEG2E16FF_V_M1_MASK 4188 +#define RISCV_PseudoVLSEG2E16FF_V_M2 4189 +#define RISCV_PseudoVLSEG2E16FF_V_M2_MASK 4190 +#define RISCV_PseudoVLSEG2E16FF_V_M4 4191 +#define RISCV_PseudoVLSEG2E16FF_V_M4_MASK 4192 +#define RISCV_PseudoVLSEG2E16FF_V_MF2 4193 +#define RISCV_PseudoVLSEG2E16FF_V_MF2_MASK 4194 +#define RISCV_PseudoVLSEG2E16FF_V_MF4 4195 +#define RISCV_PseudoVLSEG2E16FF_V_MF4_MASK 4196 +#define RISCV_PseudoVLSEG2E16_V_M1 4197 +#define RISCV_PseudoVLSEG2E16_V_M1_MASK 4198 +#define RISCV_PseudoVLSEG2E16_V_M2 4199 +#define RISCV_PseudoVLSEG2E16_V_M2_MASK 4200 +#define RISCV_PseudoVLSEG2E16_V_M4 4201 +#define RISCV_PseudoVLSEG2E16_V_M4_MASK 4202 +#define RISCV_PseudoVLSEG2E16_V_MF2 4203 +#define RISCV_PseudoVLSEG2E16_V_MF2_MASK 4204 +#define RISCV_PseudoVLSEG2E16_V_MF4 4205 +#define RISCV_PseudoVLSEG2E16_V_MF4_MASK 4206 +#define RISCV_PseudoVLSEG2E32FF_V_M1 4207 +#define RISCV_PseudoVLSEG2E32FF_V_M1_MASK 4208 +#define RISCV_PseudoVLSEG2E32FF_V_M2 4209 +#define RISCV_PseudoVLSEG2E32FF_V_M2_MASK 4210 +#define RISCV_PseudoVLSEG2E32FF_V_M4 4211 +#define RISCV_PseudoVLSEG2E32FF_V_M4_MASK 4212 +#define RISCV_PseudoVLSEG2E32FF_V_MF2 4213 +#define RISCV_PseudoVLSEG2E32FF_V_MF2_MASK 4214 +#define RISCV_PseudoVLSEG2E32_V_M1 4215 +#define RISCV_PseudoVLSEG2E32_V_M1_MASK 4216 +#define RISCV_PseudoVLSEG2E32_V_M2 4217 +#define RISCV_PseudoVLSEG2E32_V_M2_MASK 4218 +#define RISCV_PseudoVLSEG2E32_V_M4 4219 +#define RISCV_PseudoVLSEG2E32_V_M4_MASK 4220 +#define RISCV_PseudoVLSEG2E32_V_MF2 4221 +#define RISCV_PseudoVLSEG2E32_V_MF2_MASK 4222 +#define RISCV_PseudoVLSEG2E64FF_V_M1 4223 +#define RISCV_PseudoVLSEG2E64FF_V_M1_MASK 4224 +#define RISCV_PseudoVLSEG2E64FF_V_M2 4225 +#define RISCV_PseudoVLSEG2E64FF_V_M2_MASK 4226 +#define RISCV_PseudoVLSEG2E64FF_V_M4 4227 +#define RISCV_PseudoVLSEG2E64FF_V_M4_MASK 4228 +#define RISCV_PseudoVLSEG2E64_V_M1 4229 +#define RISCV_PseudoVLSEG2E64_V_M1_MASK 4230 +#define RISCV_PseudoVLSEG2E64_V_M2 4231 +#define RISCV_PseudoVLSEG2E64_V_M2_MASK 4232 +#define RISCV_PseudoVLSEG2E64_V_M4 4233 +#define RISCV_PseudoVLSEG2E64_V_M4_MASK 4234 +#define RISCV_PseudoVLSEG2E8FF_V_M1 4235 +#define RISCV_PseudoVLSEG2E8FF_V_M1_MASK 4236 +#define RISCV_PseudoVLSEG2E8FF_V_M2 4237 +#define RISCV_PseudoVLSEG2E8FF_V_M2_MASK 4238 +#define RISCV_PseudoVLSEG2E8FF_V_M4 4239 +#define RISCV_PseudoVLSEG2E8FF_V_M4_MASK 4240 +#define RISCV_PseudoVLSEG2E8FF_V_MF2 4241 +#define RISCV_PseudoVLSEG2E8FF_V_MF2_MASK 4242 +#define RISCV_PseudoVLSEG2E8FF_V_MF4 4243 +#define RISCV_PseudoVLSEG2E8FF_V_MF4_MASK 4244 +#define RISCV_PseudoVLSEG2E8FF_V_MF8 4245 +#define RISCV_PseudoVLSEG2E8FF_V_MF8_MASK 4246 +#define RISCV_PseudoVLSEG2E8_V_M1 4247 +#define RISCV_PseudoVLSEG2E8_V_M1_MASK 4248 +#define RISCV_PseudoVLSEG2E8_V_M2 4249 +#define RISCV_PseudoVLSEG2E8_V_M2_MASK 4250 +#define RISCV_PseudoVLSEG2E8_V_M4 4251 +#define RISCV_PseudoVLSEG2E8_V_M4_MASK 4252 +#define RISCV_PseudoVLSEG2E8_V_MF2 4253 +#define RISCV_PseudoVLSEG2E8_V_MF2_MASK 4254 +#define RISCV_PseudoVLSEG2E8_V_MF4 4255 +#define RISCV_PseudoVLSEG2E8_V_MF4_MASK 4256 +#define RISCV_PseudoVLSEG2E8_V_MF8 4257 +#define RISCV_PseudoVLSEG2E8_V_MF8_MASK 4258 +#define RISCV_PseudoVLSEG3E16FF_V_M1 4259 +#define RISCV_PseudoVLSEG3E16FF_V_M1_MASK 4260 +#define RISCV_PseudoVLSEG3E16FF_V_M2 4261 +#define RISCV_PseudoVLSEG3E16FF_V_M2_MASK 4262 +#define RISCV_PseudoVLSEG3E16FF_V_MF2 4263 +#define RISCV_PseudoVLSEG3E16FF_V_MF2_MASK 4264 +#define RISCV_PseudoVLSEG3E16FF_V_MF4 4265 +#define RISCV_PseudoVLSEG3E16FF_V_MF4_MASK 4266 +#define RISCV_PseudoVLSEG3E16_V_M1 4267 +#define RISCV_PseudoVLSEG3E16_V_M1_MASK 4268 +#define RISCV_PseudoVLSEG3E16_V_M2 4269 +#define RISCV_PseudoVLSEG3E16_V_M2_MASK 4270 +#define RISCV_PseudoVLSEG3E16_V_MF2 4271 +#define RISCV_PseudoVLSEG3E16_V_MF2_MASK 4272 +#define RISCV_PseudoVLSEG3E16_V_MF4 4273 +#define RISCV_PseudoVLSEG3E16_V_MF4_MASK 4274 +#define RISCV_PseudoVLSEG3E32FF_V_M1 4275 +#define RISCV_PseudoVLSEG3E32FF_V_M1_MASK 4276 +#define RISCV_PseudoVLSEG3E32FF_V_M2 4277 +#define RISCV_PseudoVLSEG3E32FF_V_M2_MASK 4278 +#define RISCV_PseudoVLSEG3E32FF_V_MF2 4279 +#define RISCV_PseudoVLSEG3E32FF_V_MF2_MASK 4280 +#define RISCV_PseudoVLSEG3E32_V_M1 4281 +#define RISCV_PseudoVLSEG3E32_V_M1_MASK 4282 +#define RISCV_PseudoVLSEG3E32_V_M2 4283 +#define RISCV_PseudoVLSEG3E32_V_M2_MASK 4284 +#define RISCV_PseudoVLSEG3E32_V_MF2 4285 +#define RISCV_PseudoVLSEG3E32_V_MF2_MASK 4286 +#define RISCV_PseudoVLSEG3E64FF_V_M1 4287 +#define RISCV_PseudoVLSEG3E64FF_V_M1_MASK 4288 +#define RISCV_PseudoVLSEG3E64FF_V_M2 4289 +#define RISCV_PseudoVLSEG3E64FF_V_M2_MASK 4290 +#define RISCV_PseudoVLSEG3E64_V_M1 4291 +#define RISCV_PseudoVLSEG3E64_V_M1_MASK 4292 +#define RISCV_PseudoVLSEG3E64_V_M2 4293 +#define RISCV_PseudoVLSEG3E64_V_M2_MASK 4294 +#define RISCV_PseudoVLSEG3E8FF_V_M1 4295 +#define RISCV_PseudoVLSEG3E8FF_V_M1_MASK 4296 +#define RISCV_PseudoVLSEG3E8FF_V_M2 4297 +#define RISCV_PseudoVLSEG3E8FF_V_M2_MASK 4298 +#define RISCV_PseudoVLSEG3E8FF_V_MF2 4299 +#define RISCV_PseudoVLSEG3E8FF_V_MF2_MASK 4300 +#define RISCV_PseudoVLSEG3E8FF_V_MF4 4301 +#define RISCV_PseudoVLSEG3E8FF_V_MF4_MASK 4302 +#define RISCV_PseudoVLSEG3E8FF_V_MF8 4303 +#define RISCV_PseudoVLSEG3E8FF_V_MF8_MASK 4304 +#define RISCV_PseudoVLSEG3E8_V_M1 4305 +#define RISCV_PseudoVLSEG3E8_V_M1_MASK 4306 +#define RISCV_PseudoVLSEG3E8_V_M2 4307 +#define RISCV_PseudoVLSEG3E8_V_M2_MASK 4308 +#define RISCV_PseudoVLSEG3E8_V_MF2 4309 +#define RISCV_PseudoVLSEG3E8_V_MF2_MASK 4310 +#define RISCV_PseudoVLSEG3E8_V_MF4 4311 +#define RISCV_PseudoVLSEG3E8_V_MF4_MASK 4312 +#define RISCV_PseudoVLSEG3E8_V_MF8 4313 +#define RISCV_PseudoVLSEG3E8_V_MF8_MASK 4314 +#define RISCV_PseudoVLSEG4E16FF_V_M1 4315 +#define RISCV_PseudoVLSEG4E16FF_V_M1_MASK 4316 +#define RISCV_PseudoVLSEG4E16FF_V_M2 4317 +#define RISCV_PseudoVLSEG4E16FF_V_M2_MASK 4318 +#define RISCV_PseudoVLSEG4E16FF_V_MF2 4319 +#define RISCV_PseudoVLSEG4E16FF_V_MF2_MASK 4320 +#define RISCV_PseudoVLSEG4E16FF_V_MF4 4321 +#define RISCV_PseudoVLSEG4E16FF_V_MF4_MASK 4322 +#define RISCV_PseudoVLSEG4E16_V_M1 4323 +#define RISCV_PseudoVLSEG4E16_V_M1_MASK 4324 +#define RISCV_PseudoVLSEG4E16_V_M2 4325 +#define RISCV_PseudoVLSEG4E16_V_M2_MASK 4326 +#define RISCV_PseudoVLSEG4E16_V_MF2 4327 +#define RISCV_PseudoVLSEG4E16_V_MF2_MASK 4328 +#define RISCV_PseudoVLSEG4E16_V_MF4 4329 +#define RISCV_PseudoVLSEG4E16_V_MF4_MASK 4330 +#define RISCV_PseudoVLSEG4E32FF_V_M1 4331 +#define RISCV_PseudoVLSEG4E32FF_V_M1_MASK 4332 +#define RISCV_PseudoVLSEG4E32FF_V_M2 4333 +#define RISCV_PseudoVLSEG4E32FF_V_M2_MASK 4334 +#define RISCV_PseudoVLSEG4E32FF_V_MF2 4335 +#define RISCV_PseudoVLSEG4E32FF_V_MF2_MASK 4336 +#define RISCV_PseudoVLSEG4E32_V_M1 4337 +#define RISCV_PseudoVLSEG4E32_V_M1_MASK 4338 +#define RISCV_PseudoVLSEG4E32_V_M2 4339 +#define RISCV_PseudoVLSEG4E32_V_M2_MASK 4340 +#define RISCV_PseudoVLSEG4E32_V_MF2 4341 +#define RISCV_PseudoVLSEG4E32_V_MF2_MASK 4342 +#define RISCV_PseudoVLSEG4E64FF_V_M1 4343 +#define RISCV_PseudoVLSEG4E64FF_V_M1_MASK 4344 +#define RISCV_PseudoVLSEG4E64FF_V_M2 4345 +#define RISCV_PseudoVLSEG4E64FF_V_M2_MASK 4346 +#define RISCV_PseudoVLSEG4E64_V_M1 4347 +#define RISCV_PseudoVLSEG4E64_V_M1_MASK 4348 +#define RISCV_PseudoVLSEG4E64_V_M2 4349 +#define RISCV_PseudoVLSEG4E64_V_M2_MASK 4350 +#define RISCV_PseudoVLSEG4E8FF_V_M1 4351 +#define RISCV_PseudoVLSEG4E8FF_V_M1_MASK 4352 +#define RISCV_PseudoVLSEG4E8FF_V_M2 4353 +#define RISCV_PseudoVLSEG4E8FF_V_M2_MASK 4354 +#define RISCV_PseudoVLSEG4E8FF_V_MF2 4355 +#define RISCV_PseudoVLSEG4E8FF_V_MF2_MASK 4356 +#define RISCV_PseudoVLSEG4E8FF_V_MF4 4357 +#define RISCV_PseudoVLSEG4E8FF_V_MF4_MASK 4358 +#define RISCV_PseudoVLSEG4E8FF_V_MF8 4359 +#define RISCV_PseudoVLSEG4E8FF_V_MF8_MASK 4360 +#define RISCV_PseudoVLSEG4E8_V_M1 4361 +#define RISCV_PseudoVLSEG4E8_V_M1_MASK 4362 +#define RISCV_PseudoVLSEG4E8_V_M2 4363 +#define RISCV_PseudoVLSEG4E8_V_M2_MASK 4364 +#define RISCV_PseudoVLSEG4E8_V_MF2 4365 +#define RISCV_PseudoVLSEG4E8_V_MF2_MASK 4366 +#define RISCV_PseudoVLSEG4E8_V_MF4 4367 +#define RISCV_PseudoVLSEG4E8_V_MF4_MASK 4368 +#define RISCV_PseudoVLSEG4E8_V_MF8 4369 +#define RISCV_PseudoVLSEG4E8_V_MF8_MASK 4370 +#define RISCV_PseudoVLSEG5E16FF_V_M1 4371 +#define RISCV_PseudoVLSEG5E16FF_V_M1_MASK 4372 +#define RISCV_PseudoVLSEG5E16FF_V_MF2 4373 +#define RISCV_PseudoVLSEG5E16FF_V_MF2_MASK 4374 +#define RISCV_PseudoVLSEG5E16FF_V_MF4 4375 +#define RISCV_PseudoVLSEG5E16FF_V_MF4_MASK 4376 +#define RISCV_PseudoVLSEG5E16_V_M1 4377 +#define RISCV_PseudoVLSEG5E16_V_M1_MASK 4378 +#define RISCV_PseudoVLSEG5E16_V_MF2 4379 +#define RISCV_PseudoVLSEG5E16_V_MF2_MASK 4380 +#define RISCV_PseudoVLSEG5E16_V_MF4 4381 +#define RISCV_PseudoVLSEG5E16_V_MF4_MASK 4382 +#define RISCV_PseudoVLSEG5E32FF_V_M1 4383 +#define RISCV_PseudoVLSEG5E32FF_V_M1_MASK 4384 +#define RISCV_PseudoVLSEG5E32FF_V_MF2 4385 +#define RISCV_PseudoVLSEG5E32FF_V_MF2_MASK 4386 +#define RISCV_PseudoVLSEG5E32_V_M1 4387 +#define RISCV_PseudoVLSEG5E32_V_M1_MASK 4388 +#define RISCV_PseudoVLSEG5E32_V_MF2 4389 +#define RISCV_PseudoVLSEG5E32_V_MF2_MASK 4390 +#define RISCV_PseudoVLSEG5E64FF_V_M1 4391 +#define RISCV_PseudoVLSEG5E64FF_V_M1_MASK 4392 +#define RISCV_PseudoVLSEG5E64_V_M1 4393 +#define RISCV_PseudoVLSEG5E64_V_M1_MASK 4394 +#define RISCV_PseudoVLSEG5E8FF_V_M1 4395 +#define RISCV_PseudoVLSEG5E8FF_V_M1_MASK 4396 +#define RISCV_PseudoVLSEG5E8FF_V_MF2 4397 +#define RISCV_PseudoVLSEG5E8FF_V_MF2_MASK 4398 +#define RISCV_PseudoVLSEG5E8FF_V_MF4 4399 +#define RISCV_PseudoVLSEG5E8FF_V_MF4_MASK 4400 +#define RISCV_PseudoVLSEG5E8FF_V_MF8 4401 +#define RISCV_PseudoVLSEG5E8FF_V_MF8_MASK 4402 +#define RISCV_PseudoVLSEG5E8_V_M1 4403 +#define RISCV_PseudoVLSEG5E8_V_M1_MASK 4404 +#define RISCV_PseudoVLSEG5E8_V_MF2 4405 +#define RISCV_PseudoVLSEG5E8_V_MF2_MASK 4406 +#define RISCV_PseudoVLSEG5E8_V_MF4 4407 +#define RISCV_PseudoVLSEG5E8_V_MF4_MASK 4408 +#define RISCV_PseudoVLSEG5E8_V_MF8 4409 +#define RISCV_PseudoVLSEG5E8_V_MF8_MASK 4410 +#define RISCV_PseudoVLSEG6E16FF_V_M1 4411 +#define RISCV_PseudoVLSEG6E16FF_V_M1_MASK 4412 +#define RISCV_PseudoVLSEG6E16FF_V_MF2 4413 +#define RISCV_PseudoVLSEG6E16FF_V_MF2_MASK 4414 +#define RISCV_PseudoVLSEG6E16FF_V_MF4 4415 +#define RISCV_PseudoVLSEG6E16FF_V_MF4_MASK 4416 +#define RISCV_PseudoVLSEG6E16_V_M1 4417 +#define RISCV_PseudoVLSEG6E16_V_M1_MASK 4418 +#define RISCV_PseudoVLSEG6E16_V_MF2 4419 +#define RISCV_PseudoVLSEG6E16_V_MF2_MASK 4420 +#define RISCV_PseudoVLSEG6E16_V_MF4 4421 +#define RISCV_PseudoVLSEG6E16_V_MF4_MASK 4422 +#define RISCV_PseudoVLSEG6E32FF_V_M1 4423 +#define RISCV_PseudoVLSEG6E32FF_V_M1_MASK 4424 +#define RISCV_PseudoVLSEG6E32FF_V_MF2 4425 +#define RISCV_PseudoVLSEG6E32FF_V_MF2_MASK 4426 +#define RISCV_PseudoVLSEG6E32_V_M1 4427 +#define RISCV_PseudoVLSEG6E32_V_M1_MASK 4428 +#define RISCV_PseudoVLSEG6E32_V_MF2 4429 +#define RISCV_PseudoVLSEG6E32_V_MF2_MASK 4430 +#define RISCV_PseudoVLSEG6E64FF_V_M1 4431 +#define RISCV_PseudoVLSEG6E64FF_V_M1_MASK 4432 +#define RISCV_PseudoVLSEG6E64_V_M1 4433 +#define RISCV_PseudoVLSEG6E64_V_M1_MASK 4434 +#define RISCV_PseudoVLSEG6E8FF_V_M1 4435 +#define RISCV_PseudoVLSEG6E8FF_V_M1_MASK 4436 +#define RISCV_PseudoVLSEG6E8FF_V_MF2 4437 +#define RISCV_PseudoVLSEG6E8FF_V_MF2_MASK 4438 +#define RISCV_PseudoVLSEG6E8FF_V_MF4 4439 +#define RISCV_PseudoVLSEG6E8FF_V_MF4_MASK 4440 +#define RISCV_PseudoVLSEG6E8FF_V_MF8 4441 +#define RISCV_PseudoVLSEG6E8FF_V_MF8_MASK 4442 +#define RISCV_PseudoVLSEG6E8_V_M1 4443 +#define RISCV_PseudoVLSEG6E8_V_M1_MASK 4444 +#define RISCV_PseudoVLSEG6E8_V_MF2 4445 +#define RISCV_PseudoVLSEG6E8_V_MF2_MASK 4446 +#define RISCV_PseudoVLSEG6E8_V_MF4 4447 +#define RISCV_PseudoVLSEG6E8_V_MF4_MASK 4448 +#define RISCV_PseudoVLSEG6E8_V_MF8 4449 +#define RISCV_PseudoVLSEG6E8_V_MF8_MASK 4450 +#define RISCV_PseudoVLSEG7E16FF_V_M1 4451 +#define RISCV_PseudoVLSEG7E16FF_V_M1_MASK 4452 +#define RISCV_PseudoVLSEG7E16FF_V_MF2 4453 +#define RISCV_PseudoVLSEG7E16FF_V_MF2_MASK 4454 +#define RISCV_PseudoVLSEG7E16FF_V_MF4 4455 +#define RISCV_PseudoVLSEG7E16FF_V_MF4_MASK 4456 +#define RISCV_PseudoVLSEG7E16_V_M1 4457 +#define RISCV_PseudoVLSEG7E16_V_M1_MASK 4458 +#define RISCV_PseudoVLSEG7E16_V_MF2 4459 +#define RISCV_PseudoVLSEG7E16_V_MF2_MASK 4460 +#define RISCV_PseudoVLSEG7E16_V_MF4 4461 +#define RISCV_PseudoVLSEG7E16_V_MF4_MASK 4462 +#define RISCV_PseudoVLSEG7E32FF_V_M1 4463 +#define RISCV_PseudoVLSEG7E32FF_V_M1_MASK 4464 +#define RISCV_PseudoVLSEG7E32FF_V_MF2 4465 +#define RISCV_PseudoVLSEG7E32FF_V_MF2_MASK 4466 +#define RISCV_PseudoVLSEG7E32_V_M1 4467 +#define RISCV_PseudoVLSEG7E32_V_M1_MASK 4468 +#define RISCV_PseudoVLSEG7E32_V_MF2 4469 +#define RISCV_PseudoVLSEG7E32_V_MF2_MASK 4470 +#define RISCV_PseudoVLSEG7E64FF_V_M1 4471 +#define RISCV_PseudoVLSEG7E64FF_V_M1_MASK 4472 +#define RISCV_PseudoVLSEG7E64_V_M1 4473 +#define RISCV_PseudoVLSEG7E64_V_M1_MASK 4474 +#define RISCV_PseudoVLSEG7E8FF_V_M1 4475 +#define RISCV_PseudoVLSEG7E8FF_V_M1_MASK 4476 +#define RISCV_PseudoVLSEG7E8FF_V_MF2 4477 +#define RISCV_PseudoVLSEG7E8FF_V_MF2_MASK 4478 +#define RISCV_PseudoVLSEG7E8FF_V_MF4 4479 +#define RISCV_PseudoVLSEG7E8FF_V_MF4_MASK 4480 +#define RISCV_PseudoVLSEG7E8FF_V_MF8 4481 +#define RISCV_PseudoVLSEG7E8FF_V_MF8_MASK 4482 +#define RISCV_PseudoVLSEG7E8_V_M1 4483 +#define RISCV_PseudoVLSEG7E8_V_M1_MASK 4484 +#define RISCV_PseudoVLSEG7E8_V_MF2 4485 +#define RISCV_PseudoVLSEG7E8_V_MF2_MASK 4486 +#define RISCV_PseudoVLSEG7E8_V_MF4 4487 +#define RISCV_PseudoVLSEG7E8_V_MF4_MASK 4488 +#define RISCV_PseudoVLSEG7E8_V_MF8 4489 +#define RISCV_PseudoVLSEG7E8_V_MF8_MASK 4490 +#define RISCV_PseudoVLSEG8E16FF_V_M1 4491 +#define RISCV_PseudoVLSEG8E16FF_V_M1_MASK 4492 +#define RISCV_PseudoVLSEG8E16FF_V_MF2 4493 +#define RISCV_PseudoVLSEG8E16FF_V_MF2_MASK 4494 +#define RISCV_PseudoVLSEG8E16FF_V_MF4 4495 +#define RISCV_PseudoVLSEG8E16FF_V_MF4_MASK 4496 +#define RISCV_PseudoVLSEG8E16_V_M1 4497 +#define RISCV_PseudoVLSEG8E16_V_M1_MASK 4498 +#define RISCV_PseudoVLSEG8E16_V_MF2 4499 +#define RISCV_PseudoVLSEG8E16_V_MF2_MASK 4500 +#define RISCV_PseudoVLSEG8E16_V_MF4 4501 +#define RISCV_PseudoVLSEG8E16_V_MF4_MASK 4502 +#define RISCV_PseudoVLSEG8E32FF_V_M1 4503 +#define RISCV_PseudoVLSEG8E32FF_V_M1_MASK 4504 +#define RISCV_PseudoVLSEG8E32FF_V_MF2 4505 +#define RISCV_PseudoVLSEG8E32FF_V_MF2_MASK 4506 +#define RISCV_PseudoVLSEG8E32_V_M1 4507 +#define RISCV_PseudoVLSEG8E32_V_M1_MASK 4508 +#define RISCV_PseudoVLSEG8E32_V_MF2 4509 +#define RISCV_PseudoVLSEG8E32_V_MF2_MASK 4510 +#define RISCV_PseudoVLSEG8E64FF_V_M1 4511 +#define RISCV_PseudoVLSEG8E64FF_V_M1_MASK 4512 +#define RISCV_PseudoVLSEG8E64_V_M1 4513 +#define RISCV_PseudoVLSEG8E64_V_M1_MASK 4514 +#define RISCV_PseudoVLSEG8E8FF_V_M1 4515 +#define RISCV_PseudoVLSEG8E8FF_V_M1_MASK 4516 +#define RISCV_PseudoVLSEG8E8FF_V_MF2 4517 +#define RISCV_PseudoVLSEG8E8FF_V_MF2_MASK 4518 +#define RISCV_PseudoVLSEG8E8FF_V_MF4 4519 +#define RISCV_PseudoVLSEG8E8FF_V_MF4_MASK 4520 +#define RISCV_PseudoVLSEG8E8FF_V_MF8 4521 +#define RISCV_PseudoVLSEG8E8FF_V_MF8_MASK 4522 +#define RISCV_PseudoVLSEG8E8_V_M1 4523 +#define RISCV_PseudoVLSEG8E8_V_M1_MASK 4524 +#define RISCV_PseudoVLSEG8E8_V_MF2 4525 +#define RISCV_PseudoVLSEG8E8_V_MF2_MASK 4526 +#define RISCV_PseudoVLSEG8E8_V_MF4 4527 +#define RISCV_PseudoVLSEG8E8_V_MF4_MASK 4528 +#define RISCV_PseudoVLSEG8E8_V_MF8 4529 +#define RISCV_PseudoVLSEG8E8_V_MF8_MASK 4530 +#define RISCV_PseudoVLSSEG2E16_V_M1 4531 +#define RISCV_PseudoVLSSEG2E16_V_M1_MASK 4532 +#define RISCV_PseudoVLSSEG2E16_V_M2 4533 +#define RISCV_PseudoVLSSEG2E16_V_M2_MASK 4534 +#define RISCV_PseudoVLSSEG2E16_V_M4 4535 +#define RISCV_PseudoVLSSEG2E16_V_M4_MASK 4536 +#define RISCV_PseudoVLSSEG2E16_V_MF2 4537 +#define RISCV_PseudoVLSSEG2E16_V_MF2_MASK 4538 +#define RISCV_PseudoVLSSEG2E16_V_MF4 4539 +#define RISCV_PseudoVLSSEG2E16_V_MF4_MASK 4540 +#define RISCV_PseudoVLSSEG2E32_V_M1 4541 +#define RISCV_PseudoVLSSEG2E32_V_M1_MASK 4542 +#define RISCV_PseudoVLSSEG2E32_V_M2 4543 +#define RISCV_PseudoVLSSEG2E32_V_M2_MASK 4544 +#define RISCV_PseudoVLSSEG2E32_V_M4 4545 +#define RISCV_PseudoVLSSEG2E32_V_M4_MASK 4546 +#define RISCV_PseudoVLSSEG2E32_V_MF2 4547 +#define RISCV_PseudoVLSSEG2E32_V_MF2_MASK 4548 +#define RISCV_PseudoVLSSEG2E64_V_M1 4549 +#define RISCV_PseudoVLSSEG2E64_V_M1_MASK 4550 +#define RISCV_PseudoVLSSEG2E64_V_M2 4551 +#define RISCV_PseudoVLSSEG2E64_V_M2_MASK 4552 +#define RISCV_PseudoVLSSEG2E64_V_M4 4553 +#define RISCV_PseudoVLSSEG2E64_V_M4_MASK 4554 +#define RISCV_PseudoVLSSEG2E8_V_M1 4555 +#define RISCV_PseudoVLSSEG2E8_V_M1_MASK 4556 +#define RISCV_PseudoVLSSEG2E8_V_M2 4557 +#define RISCV_PseudoVLSSEG2E8_V_M2_MASK 4558 +#define RISCV_PseudoVLSSEG2E8_V_M4 4559 +#define RISCV_PseudoVLSSEG2E8_V_M4_MASK 4560 +#define RISCV_PseudoVLSSEG2E8_V_MF2 4561 +#define RISCV_PseudoVLSSEG2E8_V_MF2_MASK 4562 +#define RISCV_PseudoVLSSEG2E8_V_MF4 4563 +#define RISCV_PseudoVLSSEG2E8_V_MF4_MASK 4564 +#define RISCV_PseudoVLSSEG2E8_V_MF8 4565 +#define RISCV_PseudoVLSSEG2E8_V_MF8_MASK 4566 +#define RISCV_PseudoVLSSEG3E16_V_M1 4567 +#define RISCV_PseudoVLSSEG3E16_V_M1_MASK 4568 +#define RISCV_PseudoVLSSEG3E16_V_M2 4569 +#define RISCV_PseudoVLSSEG3E16_V_M2_MASK 4570 +#define RISCV_PseudoVLSSEG3E16_V_MF2 4571 +#define RISCV_PseudoVLSSEG3E16_V_MF2_MASK 4572 +#define RISCV_PseudoVLSSEG3E16_V_MF4 4573 +#define RISCV_PseudoVLSSEG3E16_V_MF4_MASK 4574 +#define RISCV_PseudoVLSSEG3E32_V_M1 4575 +#define RISCV_PseudoVLSSEG3E32_V_M1_MASK 4576 +#define RISCV_PseudoVLSSEG3E32_V_M2 4577 +#define RISCV_PseudoVLSSEG3E32_V_M2_MASK 4578 +#define RISCV_PseudoVLSSEG3E32_V_MF2 4579 +#define RISCV_PseudoVLSSEG3E32_V_MF2_MASK 4580 +#define RISCV_PseudoVLSSEG3E64_V_M1 4581 +#define RISCV_PseudoVLSSEG3E64_V_M1_MASK 4582 +#define RISCV_PseudoVLSSEG3E64_V_M2 4583 +#define RISCV_PseudoVLSSEG3E64_V_M2_MASK 4584 +#define RISCV_PseudoVLSSEG3E8_V_M1 4585 +#define RISCV_PseudoVLSSEG3E8_V_M1_MASK 4586 +#define RISCV_PseudoVLSSEG3E8_V_M2 4587 +#define RISCV_PseudoVLSSEG3E8_V_M2_MASK 4588 +#define RISCV_PseudoVLSSEG3E8_V_MF2 4589 +#define RISCV_PseudoVLSSEG3E8_V_MF2_MASK 4590 +#define RISCV_PseudoVLSSEG3E8_V_MF4 4591 +#define RISCV_PseudoVLSSEG3E8_V_MF4_MASK 4592 +#define RISCV_PseudoVLSSEG3E8_V_MF8 4593 +#define RISCV_PseudoVLSSEG3E8_V_MF8_MASK 4594 +#define RISCV_PseudoVLSSEG4E16_V_M1 4595 +#define RISCV_PseudoVLSSEG4E16_V_M1_MASK 4596 +#define RISCV_PseudoVLSSEG4E16_V_M2 4597 +#define RISCV_PseudoVLSSEG4E16_V_M2_MASK 4598 +#define RISCV_PseudoVLSSEG4E16_V_MF2 4599 +#define RISCV_PseudoVLSSEG4E16_V_MF2_MASK 4600 +#define RISCV_PseudoVLSSEG4E16_V_MF4 4601 +#define RISCV_PseudoVLSSEG4E16_V_MF4_MASK 4602 +#define RISCV_PseudoVLSSEG4E32_V_M1 4603 +#define RISCV_PseudoVLSSEG4E32_V_M1_MASK 4604 +#define RISCV_PseudoVLSSEG4E32_V_M2 4605 +#define RISCV_PseudoVLSSEG4E32_V_M2_MASK 4606 +#define RISCV_PseudoVLSSEG4E32_V_MF2 4607 +#define RISCV_PseudoVLSSEG4E32_V_MF2_MASK 4608 +#define RISCV_PseudoVLSSEG4E64_V_M1 4609 +#define RISCV_PseudoVLSSEG4E64_V_M1_MASK 4610 +#define RISCV_PseudoVLSSEG4E64_V_M2 4611 +#define RISCV_PseudoVLSSEG4E64_V_M2_MASK 4612 +#define RISCV_PseudoVLSSEG4E8_V_M1 4613 +#define RISCV_PseudoVLSSEG4E8_V_M1_MASK 4614 +#define RISCV_PseudoVLSSEG4E8_V_M2 4615 +#define RISCV_PseudoVLSSEG4E8_V_M2_MASK 4616 +#define RISCV_PseudoVLSSEG4E8_V_MF2 4617 +#define RISCV_PseudoVLSSEG4E8_V_MF2_MASK 4618 +#define RISCV_PseudoVLSSEG4E8_V_MF4 4619 +#define RISCV_PseudoVLSSEG4E8_V_MF4_MASK 4620 +#define RISCV_PseudoVLSSEG4E8_V_MF8 4621 +#define RISCV_PseudoVLSSEG4E8_V_MF8_MASK 4622 +#define RISCV_PseudoVLSSEG5E16_V_M1 4623 +#define RISCV_PseudoVLSSEG5E16_V_M1_MASK 4624 +#define RISCV_PseudoVLSSEG5E16_V_MF2 4625 +#define RISCV_PseudoVLSSEG5E16_V_MF2_MASK 4626 +#define RISCV_PseudoVLSSEG5E16_V_MF4 4627 +#define RISCV_PseudoVLSSEG5E16_V_MF4_MASK 4628 +#define RISCV_PseudoVLSSEG5E32_V_M1 4629 +#define RISCV_PseudoVLSSEG5E32_V_M1_MASK 4630 +#define RISCV_PseudoVLSSEG5E32_V_MF2 4631 +#define RISCV_PseudoVLSSEG5E32_V_MF2_MASK 4632 +#define RISCV_PseudoVLSSEG5E64_V_M1 4633 +#define RISCV_PseudoVLSSEG5E64_V_M1_MASK 4634 +#define RISCV_PseudoVLSSEG5E8_V_M1 4635 +#define RISCV_PseudoVLSSEG5E8_V_M1_MASK 4636 +#define RISCV_PseudoVLSSEG5E8_V_MF2 4637 +#define RISCV_PseudoVLSSEG5E8_V_MF2_MASK 4638 +#define RISCV_PseudoVLSSEG5E8_V_MF4 4639 +#define RISCV_PseudoVLSSEG5E8_V_MF4_MASK 4640 +#define RISCV_PseudoVLSSEG5E8_V_MF8 4641 +#define RISCV_PseudoVLSSEG5E8_V_MF8_MASK 4642 +#define RISCV_PseudoVLSSEG6E16_V_M1 4643 +#define RISCV_PseudoVLSSEG6E16_V_M1_MASK 4644 +#define RISCV_PseudoVLSSEG6E16_V_MF2 4645 +#define RISCV_PseudoVLSSEG6E16_V_MF2_MASK 4646 +#define RISCV_PseudoVLSSEG6E16_V_MF4 4647 +#define RISCV_PseudoVLSSEG6E16_V_MF4_MASK 4648 +#define RISCV_PseudoVLSSEG6E32_V_M1 4649 +#define RISCV_PseudoVLSSEG6E32_V_M1_MASK 4650 +#define RISCV_PseudoVLSSEG6E32_V_MF2 4651 +#define RISCV_PseudoVLSSEG6E32_V_MF2_MASK 4652 +#define RISCV_PseudoVLSSEG6E64_V_M1 4653 +#define RISCV_PseudoVLSSEG6E64_V_M1_MASK 4654 +#define RISCV_PseudoVLSSEG6E8_V_M1 4655 +#define RISCV_PseudoVLSSEG6E8_V_M1_MASK 4656 +#define RISCV_PseudoVLSSEG6E8_V_MF2 4657 +#define RISCV_PseudoVLSSEG6E8_V_MF2_MASK 4658 +#define RISCV_PseudoVLSSEG6E8_V_MF4 4659 +#define RISCV_PseudoVLSSEG6E8_V_MF4_MASK 4660 +#define RISCV_PseudoVLSSEG6E8_V_MF8 4661 +#define RISCV_PseudoVLSSEG6E8_V_MF8_MASK 4662 +#define RISCV_PseudoVLSSEG7E16_V_M1 4663 +#define RISCV_PseudoVLSSEG7E16_V_M1_MASK 4664 +#define RISCV_PseudoVLSSEG7E16_V_MF2 4665 +#define RISCV_PseudoVLSSEG7E16_V_MF2_MASK 4666 +#define RISCV_PseudoVLSSEG7E16_V_MF4 4667 +#define RISCV_PseudoVLSSEG7E16_V_MF4_MASK 4668 +#define RISCV_PseudoVLSSEG7E32_V_M1 4669 +#define RISCV_PseudoVLSSEG7E32_V_M1_MASK 4670 +#define RISCV_PseudoVLSSEG7E32_V_MF2 4671 +#define RISCV_PseudoVLSSEG7E32_V_MF2_MASK 4672 +#define RISCV_PseudoVLSSEG7E64_V_M1 4673 +#define RISCV_PseudoVLSSEG7E64_V_M1_MASK 4674 +#define RISCV_PseudoVLSSEG7E8_V_M1 4675 +#define RISCV_PseudoVLSSEG7E8_V_M1_MASK 4676 +#define RISCV_PseudoVLSSEG7E8_V_MF2 4677 +#define RISCV_PseudoVLSSEG7E8_V_MF2_MASK 4678 +#define RISCV_PseudoVLSSEG7E8_V_MF4 4679 +#define RISCV_PseudoVLSSEG7E8_V_MF4_MASK 4680 +#define RISCV_PseudoVLSSEG7E8_V_MF8 4681 +#define RISCV_PseudoVLSSEG7E8_V_MF8_MASK 4682 +#define RISCV_PseudoVLSSEG8E16_V_M1 4683 +#define RISCV_PseudoVLSSEG8E16_V_M1_MASK 4684 +#define RISCV_PseudoVLSSEG8E16_V_MF2 4685 +#define RISCV_PseudoVLSSEG8E16_V_MF2_MASK 4686 +#define RISCV_PseudoVLSSEG8E16_V_MF4 4687 +#define RISCV_PseudoVLSSEG8E16_V_MF4_MASK 4688 +#define RISCV_PseudoVLSSEG8E32_V_M1 4689 +#define RISCV_PseudoVLSSEG8E32_V_M1_MASK 4690 +#define RISCV_PseudoVLSSEG8E32_V_MF2 4691 +#define RISCV_PseudoVLSSEG8E32_V_MF2_MASK 4692 +#define RISCV_PseudoVLSSEG8E64_V_M1 4693 +#define RISCV_PseudoVLSSEG8E64_V_M1_MASK 4694 +#define RISCV_PseudoVLSSEG8E8_V_M1 4695 +#define RISCV_PseudoVLSSEG8E8_V_M1_MASK 4696 +#define RISCV_PseudoVLSSEG8E8_V_MF2 4697 +#define RISCV_PseudoVLSSEG8E8_V_MF2_MASK 4698 +#define RISCV_PseudoVLSSEG8E8_V_MF4 4699 +#define RISCV_PseudoVLSSEG8E8_V_MF4_MASK 4700 +#define RISCV_PseudoVLSSEG8E8_V_MF8 4701 +#define RISCV_PseudoVLSSEG8E8_V_MF8_MASK 4702 +#define RISCV_PseudoVLUXEI16_V_M1_M1 4703 +#define RISCV_PseudoVLUXEI16_V_M1_M1_MASK 4704 +#define RISCV_PseudoVLUXEI16_V_M1_M2 4705 +#define RISCV_PseudoVLUXEI16_V_M1_M2_MASK 4706 +#define RISCV_PseudoVLUXEI16_V_M1_M4 4707 +#define RISCV_PseudoVLUXEI16_V_M1_M4_MASK 4708 +#define RISCV_PseudoVLUXEI16_V_M1_MF2 4709 +#define RISCV_PseudoVLUXEI16_V_M1_MF2_MASK 4710 +#define RISCV_PseudoVLUXEI16_V_M2_M1 4711 +#define RISCV_PseudoVLUXEI16_V_M2_M1_MASK 4712 +#define RISCV_PseudoVLUXEI16_V_M2_M2 4713 +#define RISCV_PseudoVLUXEI16_V_M2_M2_MASK 4714 +#define RISCV_PseudoVLUXEI16_V_M2_M4 4715 +#define RISCV_PseudoVLUXEI16_V_M2_M4_MASK 4716 +#define RISCV_PseudoVLUXEI16_V_M2_M8 4717 +#define RISCV_PseudoVLUXEI16_V_M2_M8_MASK 4718 +#define RISCV_PseudoVLUXEI16_V_M4_M2 4719 +#define RISCV_PseudoVLUXEI16_V_M4_M2_MASK 4720 +#define RISCV_PseudoVLUXEI16_V_M4_M4 4721 +#define RISCV_PseudoVLUXEI16_V_M4_M4_MASK 4722 +#define RISCV_PseudoVLUXEI16_V_M4_M8 4723 +#define RISCV_PseudoVLUXEI16_V_M4_M8_MASK 4724 +#define RISCV_PseudoVLUXEI16_V_M8_M4 4725 +#define RISCV_PseudoVLUXEI16_V_M8_M4_MASK 4726 +#define RISCV_PseudoVLUXEI16_V_M8_M8 4727 +#define RISCV_PseudoVLUXEI16_V_M8_M8_MASK 4728 +#define RISCV_PseudoVLUXEI16_V_MF2_M1 4729 +#define RISCV_PseudoVLUXEI16_V_MF2_M1_MASK 4730 +#define RISCV_PseudoVLUXEI16_V_MF2_M2 4731 +#define RISCV_PseudoVLUXEI16_V_MF2_M2_MASK 4732 +#define RISCV_PseudoVLUXEI16_V_MF2_MF2 4733 +#define RISCV_PseudoVLUXEI16_V_MF2_MF2_MASK 4734 +#define RISCV_PseudoVLUXEI16_V_MF2_MF4 4735 +#define RISCV_PseudoVLUXEI16_V_MF2_MF4_MASK 4736 +#define RISCV_PseudoVLUXEI16_V_MF4_M1 4737 +#define RISCV_PseudoVLUXEI16_V_MF4_M1_MASK 4738 +#define RISCV_PseudoVLUXEI16_V_MF4_MF2 4739 +#define RISCV_PseudoVLUXEI16_V_MF4_MF2_MASK 4740 +#define RISCV_PseudoVLUXEI16_V_MF4_MF4 4741 +#define RISCV_PseudoVLUXEI16_V_MF4_MF4_MASK 4742 +#define RISCV_PseudoVLUXEI16_V_MF4_MF8 4743 +#define RISCV_PseudoVLUXEI16_V_MF4_MF8_MASK 4744 +#define RISCV_PseudoVLUXEI32_V_M1_M1 4745 +#define RISCV_PseudoVLUXEI32_V_M1_M1_MASK 4746 +#define RISCV_PseudoVLUXEI32_V_M1_M2 4747 +#define RISCV_PseudoVLUXEI32_V_M1_M2_MASK 4748 +#define RISCV_PseudoVLUXEI32_V_M1_MF2 4749 +#define RISCV_PseudoVLUXEI32_V_M1_MF2_MASK 4750 +#define RISCV_PseudoVLUXEI32_V_M1_MF4 4751 +#define RISCV_PseudoVLUXEI32_V_M1_MF4_MASK 4752 +#define RISCV_PseudoVLUXEI32_V_M2_M1 4753 +#define RISCV_PseudoVLUXEI32_V_M2_M1_MASK 4754 +#define RISCV_PseudoVLUXEI32_V_M2_M2 4755 +#define RISCV_PseudoVLUXEI32_V_M2_M2_MASK 4756 +#define RISCV_PseudoVLUXEI32_V_M2_M4 4757 +#define RISCV_PseudoVLUXEI32_V_M2_M4_MASK 4758 +#define RISCV_PseudoVLUXEI32_V_M2_MF2 4759 +#define RISCV_PseudoVLUXEI32_V_M2_MF2_MASK 4760 +#define RISCV_PseudoVLUXEI32_V_M4_M1 4761 +#define RISCV_PseudoVLUXEI32_V_M4_M1_MASK 4762 +#define RISCV_PseudoVLUXEI32_V_M4_M2 4763 +#define RISCV_PseudoVLUXEI32_V_M4_M2_MASK 4764 +#define RISCV_PseudoVLUXEI32_V_M4_M4 4765 +#define RISCV_PseudoVLUXEI32_V_M4_M4_MASK 4766 +#define RISCV_PseudoVLUXEI32_V_M4_M8 4767 +#define RISCV_PseudoVLUXEI32_V_M4_M8_MASK 4768 +#define RISCV_PseudoVLUXEI32_V_M8_M2 4769 +#define RISCV_PseudoVLUXEI32_V_M8_M2_MASK 4770 +#define RISCV_PseudoVLUXEI32_V_M8_M4 4771 +#define RISCV_PseudoVLUXEI32_V_M8_M4_MASK 4772 +#define RISCV_PseudoVLUXEI32_V_M8_M8 4773 +#define RISCV_PseudoVLUXEI32_V_M8_M8_MASK 4774 +#define RISCV_PseudoVLUXEI32_V_MF2_M1 4775 +#define RISCV_PseudoVLUXEI32_V_MF2_M1_MASK 4776 +#define RISCV_PseudoVLUXEI32_V_MF2_MF2 4777 +#define RISCV_PseudoVLUXEI32_V_MF2_MF2_MASK 4778 +#define RISCV_PseudoVLUXEI32_V_MF2_MF4 4779 +#define RISCV_PseudoVLUXEI32_V_MF2_MF4_MASK 4780 +#define RISCV_PseudoVLUXEI32_V_MF2_MF8 4781 +#define RISCV_PseudoVLUXEI32_V_MF2_MF8_MASK 4782 +#define RISCV_PseudoVLUXEI64_V_M1_M1 4783 +#define RISCV_PseudoVLUXEI64_V_M1_M1_MASK 4784 +#define RISCV_PseudoVLUXEI64_V_M1_MF2 4785 +#define RISCV_PseudoVLUXEI64_V_M1_MF2_MASK 4786 +#define RISCV_PseudoVLUXEI64_V_M1_MF4 4787 +#define RISCV_PseudoVLUXEI64_V_M1_MF4_MASK 4788 +#define RISCV_PseudoVLUXEI64_V_M1_MF8 4789 +#define RISCV_PseudoVLUXEI64_V_M1_MF8_MASK 4790 +#define RISCV_PseudoVLUXEI64_V_M2_M1 4791 +#define RISCV_PseudoVLUXEI64_V_M2_M1_MASK 4792 +#define RISCV_PseudoVLUXEI64_V_M2_M2 4793 +#define RISCV_PseudoVLUXEI64_V_M2_M2_MASK 4794 +#define RISCV_PseudoVLUXEI64_V_M2_MF2 4795 +#define RISCV_PseudoVLUXEI64_V_M2_MF2_MASK 4796 +#define RISCV_PseudoVLUXEI64_V_M2_MF4 4797 +#define RISCV_PseudoVLUXEI64_V_M2_MF4_MASK 4798 +#define RISCV_PseudoVLUXEI64_V_M4_M1 4799 +#define RISCV_PseudoVLUXEI64_V_M4_M1_MASK 4800 +#define RISCV_PseudoVLUXEI64_V_M4_M2 4801 +#define RISCV_PseudoVLUXEI64_V_M4_M2_MASK 4802 +#define RISCV_PseudoVLUXEI64_V_M4_M4 4803 +#define RISCV_PseudoVLUXEI64_V_M4_M4_MASK 4804 +#define RISCV_PseudoVLUXEI64_V_M4_MF2 4805 +#define RISCV_PseudoVLUXEI64_V_M4_MF2_MASK 4806 +#define RISCV_PseudoVLUXEI64_V_M8_M1 4807 +#define RISCV_PseudoVLUXEI64_V_M8_M1_MASK 4808 +#define RISCV_PseudoVLUXEI64_V_M8_M2 4809 +#define RISCV_PseudoVLUXEI64_V_M8_M2_MASK 4810 +#define RISCV_PseudoVLUXEI64_V_M8_M4 4811 +#define RISCV_PseudoVLUXEI64_V_M8_M4_MASK 4812 +#define RISCV_PseudoVLUXEI64_V_M8_M8 4813 +#define RISCV_PseudoVLUXEI64_V_M8_M8_MASK 4814 +#define RISCV_PseudoVLUXEI8_V_M1_M1 4815 +#define RISCV_PseudoVLUXEI8_V_M1_M1_MASK 4816 +#define RISCV_PseudoVLUXEI8_V_M1_M2 4817 +#define RISCV_PseudoVLUXEI8_V_M1_M2_MASK 4818 +#define RISCV_PseudoVLUXEI8_V_M1_M4 4819 +#define RISCV_PseudoVLUXEI8_V_M1_M4_MASK 4820 +#define RISCV_PseudoVLUXEI8_V_M1_M8 4821 +#define RISCV_PseudoVLUXEI8_V_M1_M8_MASK 4822 +#define RISCV_PseudoVLUXEI8_V_M2_M2 4823 +#define RISCV_PseudoVLUXEI8_V_M2_M2_MASK 4824 +#define RISCV_PseudoVLUXEI8_V_M2_M4 4825 +#define RISCV_PseudoVLUXEI8_V_M2_M4_MASK 4826 +#define RISCV_PseudoVLUXEI8_V_M2_M8 4827 +#define RISCV_PseudoVLUXEI8_V_M2_M8_MASK 4828 +#define RISCV_PseudoVLUXEI8_V_M4_M4 4829 +#define RISCV_PseudoVLUXEI8_V_M4_M4_MASK 4830 +#define RISCV_PseudoVLUXEI8_V_M4_M8 4831 +#define RISCV_PseudoVLUXEI8_V_M4_M8_MASK 4832 +#define RISCV_PseudoVLUXEI8_V_M8_M8 4833 +#define RISCV_PseudoVLUXEI8_V_M8_M8_MASK 4834 +#define RISCV_PseudoVLUXEI8_V_MF2_M1 4835 +#define RISCV_PseudoVLUXEI8_V_MF2_M1_MASK 4836 +#define RISCV_PseudoVLUXEI8_V_MF2_M2 4837 +#define RISCV_PseudoVLUXEI8_V_MF2_M2_MASK 4838 +#define RISCV_PseudoVLUXEI8_V_MF2_M4 4839 +#define RISCV_PseudoVLUXEI8_V_MF2_M4_MASK 4840 +#define RISCV_PseudoVLUXEI8_V_MF2_MF2 4841 +#define RISCV_PseudoVLUXEI8_V_MF2_MF2_MASK 4842 +#define RISCV_PseudoVLUXEI8_V_MF4_M1 4843 +#define RISCV_PseudoVLUXEI8_V_MF4_M1_MASK 4844 +#define RISCV_PseudoVLUXEI8_V_MF4_M2 4845 +#define RISCV_PseudoVLUXEI8_V_MF4_M2_MASK 4846 +#define RISCV_PseudoVLUXEI8_V_MF4_MF2 4847 +#define RISCV_PseudoVLUXEI8_V_MF4_MF2_MASK 4848 +#define RISCV_PseudoVLUXEI8_V_MF4_MF4 4849 +#define RISCV_PseudoVLUXEI8_V_MF4_MF4_MASK 4850 +#define RISCV_PseudoVLUXEI8_V_MF8_M1 4851 +#define RISCV_PseudoVLUXEI8_V_MF8_M1_MASK 4852 +#define RISCV_PseudoVLUXEI8_V_MF8_MF2 4853 +#define RISCV_PseudoVLUXEI8_V_MF8_MF2_MASK 4854 +#define RISCV_PseudoVLUXEI8_V_MF8_MF4 4855 +#define RISCV_PseudoVLUXEI8_V_MF8_MF4_MASK 4856 +#define RISCV_PseudoVLUXEI8_V_MF8_MF8 4857 +#define RISCV_PseudoVLUXEI8_V_MF8_MF8_MASK 4858 +#define RISCV_PseudoVLUXSEG2EI16_V_M1_M1 4859 +#define RISCV_PseudoVLUXSEG2EI16_V_M1_M1_MASK 4860 +#define RISCV_PseudoVLUXSEG2EI16_V_M1_M2 4861 +#define RISCV_PseudoVLUXSEG2EI16_V_M1_M2_MASK 4862 +#define RISCV_PseudoVLUXSEG2EI16_V_M1_M4 4863 +#define RISCV_PseudoVLUXSEG2EI16_V_M1_M4_MASK 4864 +#define RISCV_PseudoVLUXSEG2EI16_V_M1_MF2 4865 +#define RISCV_PseudoVLUXSEG2EI16_V_M1_MF2_MASK 4866 +#define RISCV_PseudoVLUXSEG2EI16_V_M2_M1 4867 +#define RISCV_PseudoVLUXSEG2EI16_V_M2_M1_MASK 4868 +#define RISCV_PseudoVLUXSEG2EI16_V_M2_M2 4869 +#define RISCV_PseudoVLUXSEG2EI16_V_M2_M2_MASK 4870 +#define RISCV_PseudoVLUXSEG2EI16_V_M2_M4 4871 +#define RISCV_PseudoVLUXSEG2EI16_V_M2_M4_MASK 4872 +#define RISCV_PseudoVLUXSEG2EI16_V_M4_M2 4873 +#define RISCV_PseudoVLUXSEG2EI16_V_M4_M2_MASK 4874 +#define RISCV_PseudoVLUXSEG2EI16_V_M4_M4 4875 +#define RISCV_PseudoVLUXSEG2EI16_V_M4_M4_MASK 4876 +#define RISCV_PseudoVLUXSEG2EI16_V_M8_M4 4877 +#define RISCV_PseudoVLUXSEG2EI16_V_M8_M4_MASK 4878 +#define RISCV_PseudoVLUXSEG2EI16_V_MF2_M1 4879 +#define RISCV_PseudoVLUXSEG2EI16_V_MF2_M1_MASK 4880 +#define RISCV_PseudoVLUXSEG2EI16_V_MF2_M2 4881 +#define RISCV_PseudoVLUXSEG2EI16_V_MF2_M2_MASK 4882 +#define RISCV_PseudoVLUXSEG2EI16_V_MF2_MF2 4883 +#define RISCV_PseudoVLUXSEG2EI16_V_MF2_MF2_MASK 4884 +#define RISCV_PseudoVLUXSEG2EI16_V_MF2_MF4 4885 +#define RISCV_PseudoVLUXSEG2EI16_V_MF2_MF4_MASK 4886 +#define RISCV_PseudoVLUXSEG2EI16_V_MF4_M1 4887 +#define RISCV_PseudoVLUXSEG2EI16_V_MF4_M1_MASK 4888 +#define RISCV_PseudoVLUXSEG2EI16_V_MF4_MF2 4889 +#define RISCV_PseudoVLUXSEG2EI16_V_MF4_MF2_MASK 4890 +#define RISCV_PseudoVLUXSEG2EI16_V_MF4_MF4 4891 +#define RISCV_PseudoVLUXSEG2EI16_V_MF4_MF4_MASK 4892 +#define RISCV_PseudoVLUXSEG2EI16_V_MF4_MF8 4893 +#define RISCV_PseudoVLUXSEG2EI16_V_MF4_MF8_MASK 4894 +#define RISCV_PseudoVLUXSEG2EI32_V_M1_M1 4895 +#define RISCV_PseudoVLUXSEG2EI32_V_M1_M1_MASK 4896 +#define RISCV_PseudoVLUXSEG2EI32_V_M1_M2 4897 +#define RISCV_PseudoVLUXSEG2EI32_V_M1_M2_MASK 4898 +#define RISCV_PseudoVLUXSEG2EI32_V_M1_MF2 4899 +#define RISCV_PseudoVLUXSEG2EI32_V_M1_MF2_MASK 4900 +#define RISCV_PseudoVLUXSEG2EI32_V_M1_MF4 4901 +#define RISCV_PseudoVLUXSEG2EI32_V_M1_MF4_MASK 4902 +#define RISCV_PseudoVLUXSEG2EI32_V_M2_M1 4903 +#define RISCV_PseudoVLUXSEG2EI32_V_M2_M1_MASK 4904 +#define RISCV_PseudoVLUXSEG2EI32_V_M2_M2 4905 +#define RISCV_PseudoVLUXSEG2EI32_V_M2_M2_MASK 4906 +#define RISCV_PseudoVLUXSEG2EI32_V_M2_M4 4907 +#define RISCV_PseudoVLUXSEG2EI32_V_M2_M4_MASK 4908 +#define RISCV_PseudoVLUXSEG2EI32_V_M2_MF2 4909 +#define RISCV_PseudoVLUXSEG2EI32_V_M2_MF2_MASK 4910 +#define RISCV_PseudoVLUXSEG2EI32_V_M4_M1 4911 +#define RISCV_PseudoVLUXSEG2EI32_V_M4_M1_MASK 4912 +#define RISCV_PseudoVLUXSEG2EI32_V_M4_M2 4913 +#define RISCV_PseudoVLUXSEG2EI32_V_M4_M2_MASK 4914 +#define RISCV_PseudoVLUXSEG2EI32_V_M4_M4 4915 +#define RISCV_PseudoVLUXSEG2EI32_V_M4_M4_MASK 4916 +#define RISCV_PseudoVLUXSEG2EI32_V_M8_M2 4917 +#define RISCV_PseudoVLUXSEG2EI32_V_M8_M2_MASK 4918 +#define RISCV_PseudoVLUXSEG2EI32_V_M8_M4 4919 +#define RISCV_PseudoVLUXSEG2EI32_V_M8_M4_MASK 4920 +#define RISCV_PseudoVLUXSEG2EI32_V_MF2_M1 4921 +#define RISCV_PseudoVLUXSEG2EI32_V_MF2_M1_MASK 4922 +#define RISCV_PseudoVLUXSEG2EI32_V_MF2_MF2 4923 +#define RISCV_PseudoVLUXSEG2EI32_V_MF2_MF2_MASK 4924 +#define RISCV_PseudoVLUXSEG2EI32_V_MF2_MF4 4925 +#define RISCV_PseudoVLUXSEG2EI32_V_MF2_MF4_MASK 4926 +#define RISCV_PseudoVLUXSEG2EI32_V_MF2_MF8 4927 +#define RISCV_PseudoVLUXSEG2EI32_V_MF2_MF8_MASK 4928 +#define RISCV_PseudoVLUXSEG2EI64_V_M1_M1 4929 +#define RISCV_PseudoVLUXSEG2EI64_V_M1_M1_MASK 4930 +#define RISCV_PseudoVLUXSEG2EI64_V_M1_MF2 4931 +#define RISCV_PseudoVLUXSEG2EI64_V_M1_MF2_MASK 4932 +#define RISCV_PseudoVLUXSEG2EI64_V_M1_MF4 4933 +#define RISCV_PseudoVLUXSEG2EI64_V_M1_MF4_MASK 4934 +#define RISCV_PseudoVLUXSEG2EI64_V_M1_MF8 4935 +#define RISCV_PseudoVLUXSEG2EI64_V_M1_MF8_MASK 4936 +#define RISCV_PseudoVLUXSEG2EI64_V_M2_M1 4937 +#define RISCV_PseudoVLUXSEG2EI64_V_M2_M1_MASK 4938 +#define RISCV_PseudoVLUXSEG2EI64_V_M2_M2 4939 +#define RISCV_PseudoVLUXSEG2EI64_V_M2_M2_MASK 4940 +#define RISCV_PseudoVLUXSEG2EI64_V_M2_MF2 4941 +#define RISCV_PseudoVLUXSEG2EI64_V_M2_MF2_MASK 4942 +#define RISCV_PseudoVLUXSEG2EI64_V_M2_MF4 4943 +#define RISCV_PseudoVLUXSEG2EI64_V_M2_MF4_MASK 4944 +#define RISCV_PseudoVLUXSEG2EI64_V_M4_M1 4945 +#define RISCV_PseudoVLUXSEG2EI64_V_M4_M1_MASK 4946 +#define RISCV_PseudoVLUXSEG2EI64_V_M4_M2 4947 +#define RISCV_PseudoVLUXSEG2EI64_V_M4_M2_MASK 4948 +#define RISCV_PseudoVLUXSEG2EI64_V_M4_M4 4949 +#define RISCV_PseudoVLUXSEG2EI64_V_M4_M4_MASK 4950 +#define RISCV_PseudoVLUXSEG2EI64_V_M4_MF2 4951 +#define RISCV_PseudoVLUXSEG2EI64_V_M4_MF2_MASK 4952 +#define RISCV_PseudoVLUXSEG2EI64_V_M8_M1 4953 +#define RISCV_PseudoVLUXSEG2EI64_V_M8_M1_MASK 4954 +#define RISCV_PseudoVLUXSEG2EI64_V_M8_M2 4955 +#define RISCV_PseudoVLUXSEG2EI64_V_M8_M2_MASK 4956 +#define RISCV_PseudoVLUXSEG2EI64_V_M8_M4 4957 +#define RISCV_PseudoVLUXSEG2EI64_V_M8_M4_MASK 4958 +#define RISCV_PseudoVLUXSEG2EI8_V_M1_M1 4959 +#define RISCV_PseudoVLUXSEG2EI8_V_M1_M1_MASK 4960 +#define RISCV_PseudoVLUXSEG2EI8_V_M1_M2 4961 +#define RISCV_PseudoVLUXSEG2EI8_V_M1_M2_MASK 4962 +#define RISCV_PseudoVLUXSEG2EI8_V_M1_M4 4963 +#define RISCV_PseudoVLUXSEG2EI8_V_M1_M4_MASK 4964 +#define RISCV_PseudoVLUXSEG2EI8_V_M2_M2 4965 +#define RISCV_PseudoVLUXSEG2EI8_V_M2_M2_MASK 4966 +#define RISCV_PseudoVLUXSEG2EI8_V_M2_M4 4967 +#define RISCV_PseudoVLUXSEG2EI8_V_M2_M4_MASK 4968 +#define RISCV_PseudoVLUXSEG2EI8_V_M4_M4 4969 +#define RISCV_PseudoVLUXSEG2EI8_V_M4_M4_MASK 4970 +#define RISCV_PseudoVLUXSEG2EI8_V_MF2_M1 4971 +#define RISCV_PseudoVLUXSEG2EI8_V_MF2_M1_MASK 4972 +#define RISCV_PseudoVLUXSEG2EI8_V_MF2_M2 4973 +#define RISCV_PseudoVLUXSEG2EI8_V_MF2_M2_MASK 4974 +#define RISCV_PseudoVLUXSEG2EI8_V_MF2_M4 4975 +#define RISCV_PseudoVLUXSEG2EI8_V_MF2_M4_MASK 4976 +#define RISCV_PseudoVLUXSEG2EI8_V_MF2_MF2 4977 +#define RISCV_PseudoVLUXSEG2EI8_V_MF2_MF2_MASK 4978 +#define RISCV_PseudoVLUXSEG2EI8_V_MF4_M1 4979 +#define RISCV_PseudoVLUXSEG2EI8_V_MF4_M1_MASK 4980 +#define RISCV_PseudoVLUXSEG2EI8_V_MF4_M2 4981 +#define RISCV_PseudoVLUXSEG2EI8_V_MF4_M2_MASK 4982 +#define RISCV_PseudoVLUXSEG2EI8_V_MF4_MF2 4983 +#define RISCV_PseudoVLUXSEG2EI8_V_MF4_MF2_MASK 4984 +#define RISCV_PseudoVLUXSEG2EI8_V_MF4_MF4 4985 +#define RISCV_PseudoVLUXSEG2EI8_V_MF4_MF4_MASK 4986 +#define RISCV_PseudoVLUXSEG2EI8_V_MF8_M1 4987 +#define RISCV_PseudoVLUXSEG2EI8_V_MF8_M1_MASK 4988 +#define RISCV_PseudoVLUXSEG2EI8_V_MF8_MF2 4989 +#define RISCV_PseudoVLUXSEG2EI8_V_MF8_MF2_MASK 4990 +#define RISCV_PseudoVLUXSEG2EI8_V_MF8_MF4 4991 +#define RISCV_PseudoVLUXSEG2EI8_V_MF8_MF4_MASK 4992 +#define RISCV_PseudoVLUXSEG2EI8_V_MF8_MF8 4993 +#define RISCV_PseudoVLUXSEG2EI8_V_MF8_MF8_MASK 4994 +#define RISCV_PseudoVLUXSEG3EI16_V_M1_M1 4995 +#define RISCV_PseudoVLUXSEG3EI16_V_M1_M1_MASK 4996 +#define RISCV_PseudoVLUXSEG3EI16_V_M1_M2 4997 +#define RISCV_PseudoVLUXSEG3EI16_V_M1_M2_MASK 4998 +#define RISCV_PseudoVLUXSEG3EI16_V_M1_MF2 4999 +#define RISCV_PseudoVLUXSEG3EI16_V_M1_MF2_MASK 5000 +#define RISCV_PseudoVLUXSEG3EI16_V_M2_M1 5001 +#define RISCV_PseudoVLUXSEG3EI16_V_M2_M1_MASK 5002 +#define RISCV_PseudoVLUXSEG3EI16_V_M2_M2 5003 +#define RISCV_PseudoVLUXSEG3EI16_V_M2_M2_MASK 5004 +#define RISCV_PseudoVLUXSEG3EI16_V_M4_M2 5005 +#define RISCV_PseudoVLUXSEG3EI16_V_M4_M2_MASK 5006 +#define RISCV_PseudoVLUXSEG3EI16_V_MF2_M1 5007 +#define RISCV_PseudoVLUXSEG3EI16_V_MF2_M1_MASK 5008 +#define RISCV_PseudoVLUXSEG3EI16_V_MF2_M2 5009 +#define RISCV_PseudoVLUXSEG3EI16_V_MF2_M2_MASK 5010 +#define RISCV_PseudoVLUXSEG3EI16_V_MF2_MF2 5011 +#define RISCV_PseudoVLUXSEG3EI16_V_MF2_MF2_MASK 5012 +#define RISCV_PseudoVLUXSEG3EI16_V_MF2_MF4 5013 +#define RISCV_PseudoVLUXSEG3EI16_V_MF2_MF4_MASK 5014 +#define RISCV_PseudoVLUXSEG3EI16_V_MF4_M1 5015 +#define RISCV_PseudoVLUXSEG3EI16_V_MF4_M1_MASK 5016 +#define RISCV_PseudoVLUXSEG3EI16_V_MF4_MF2 5017 +#define RISCV_PseudoVLUXSEG3EI16_V_MF4_MF2_MASK 5018 +#define RISCV_PseudoVLUXSEG3EI16_V_MF4_MF4 5019 +#define RISCV_PseudoVLUXSEG3EI16_V_MF4_MF4_MASK 5020 +#define RISCV_PseudoVLUXSEG3EI16_V_MF4_MF8 5021 +#define RISCV_PseudoVLUXSEG3EI16_V_MF4_MF8_MASK 5022 +#define RISCV_PseudoVLUXSEG3EI32_V_M1_M1 5023 +#define RISCV_PseudoVLUXSEG3EI32_V_M1_M1_MASK 5024 +#define RISCV_PseudoVLUXSEG3EI32_V_M1_M2 5025 +#define RISCV_PseudoVLUXSEG3EI32_V_M1_M2_MASK 5026 +#define RISCV_PseudoVLUXSEG3EI32_V_M1_MF2 5027 +#define RISCV_PseudoVLUXSEG3EI32_V_M1_MF2_MASK 5028 +#define RISCV_PseudoVLUXSEG3EI32_V_M1_MF4 5029 +#define RISCV_PseudoVLUXSEG3EI32_V_M1_MF4_MASK 5030 +#define RISCV_PseudoVLUXSEG3EI32_V_M2_M1 5031 +#define RISCV_PseudoVLUXSEG3EI32_V_M2_M1_MASK 5032 +#define RISCV_PseudoVLUXSEG3EI32_V_M2_M2 5033 +#define RISCV_PseudoVLUXSEG3EI32_V_M2_M2_MASK 5034 +#define RISCV_PseudoVLUXSEG3EI32_V_M2_MF2 5035 +#define RISCV_PseudoVLUXSEG3EI32_V_M2_MF2_MASK 5036 +#define RISCV_PseudoVLUXSEG3EI32_V_M4_M1 5037 +#define RISCV_PseudoVLUXSEG3EI32_V_M4_M1_MASK 5038 +#define RISCV_PseudoVLUXSEG3EI32_V_M4_M2 5039 +#define RISCV_PseudoVLUXSEG3EI32_V_M4_M2_MASK 5040 +#define RISCV_PseudoVLUXSEG3EI32_V_M8_M2 5041 +#define RISCV_PseudoVLUXSEG3EI32_V_M8_M2_MASK 5042 +#define RISCV_PseudoVLUXSEG3EI32_V_MF2_M1 5043 +#define RISCV_PseudoVLUXSEG3EI32_V_MF2_M1_MASK 5044 +#define RISCV_PseudoVLUXSEG3EI32_V_MF2_MF2 5045 +#define RISCV_PseudoVLUXSEG3EI32_V_MF2_MF2_MASK 5046 +#define RISCV_PseudoVLUXSEG3EI32_V_MF2_MF4 5047 +#define RISCV_PseudoVLUXSEG3EI32_V_MF2_MF4_MASK 5048 +#define RISCV_PseudoVLUXSEG3EI32_V_MF2_MF8 5049 +#define RISCV_PseudoVLUXSEG3EI32_V_MF2_MF8_MASK 5050 +#define RISCV_PseudoVLUXSEG3EI64_V_M1_M1 5051 +#define RISCV_PseudoVLUXSEG3EI64_V_M1_M1_MASK 5052 +#define RISCV_PseudoVLUXSEG3EI64_V_M1_MF2 5053 +#define RISCV_PseudoVLUXSEG3EI64_V_M1_MF2_MASK 5054 +#define RISCV_PseudoVLUXSEG3EI64_V_M1_MF4 5055 +#define RISCV_PseudoVLUXSEG3EI64_V_M1_MF4_MASK 5056 +#define RISCV_PseudoVLUXSEG3EI64_V_M1_MF8 5057 +#define RISCV_PseudoVLUXSEG3EI64_V_M1_MF8_MASK 5058 +#define RISCV_PseudoVLUXSEG3EI64_V_M2_M1 5059 +#define RISCV_PseudoVLUXSEG3EI64_V_M2_M1_MASK 5060 +#define RISCV_PseudoVLUXSEG3EI64_V_M2_M2 5061 +#define RISCV_PseudoVLUXSEG3EI64_V_M2_M2_MASK 5062 +#define RISCV_PseudoVLUXSEG3EI64_V_M2_MF2 5063 +#define RISCV_PseudoVLUXSEG3EI64_V_M2_MF2_MASK 5064 +#define RISCV_PseudoVLUXSEG3EI64_V_M2_MF4 5065 +#define RISCV_PseudoVLUXSEG3EI64_V_M2_MF4_MASK 5066 +#define RISCV_PseudoVLUXSEG3EI64_V_M4_M1 5067 +#define RISCV_PseudoVLUXSEG3EI64_V_M4_M1_MASK 5068 +#define RISCV_PseudoVLUXSEG3EI64_V_M4_M2 5069 +#define RISCV_PseudoVLUXSEG3EI64_V_M4_M2_MASK 5070 +#define RISCV_PseudoVLUXSEG3EI64_V_M4_MF2 5071 +#define RISCV_PseudoVLUXSEG3EI64_V_M4_MF2_MASK 5072 +#define RISCV_PseudoVLUXSEG3EI64_V_M8_M1 5073 +#define RISCV_PseudoVLUXSEG3EI64_V_M8_M1_MASK 5074 +#define RISCV_PseudoVLUXSEG3EI64_V_M8_M2 5075 +#define RISCV_PseudoVLUXSEG3EI64_V_M8_M2_MASK 5076 +#define RISCV_PseudoVLUXSEG3EI8_V_M1_M1 5077 +#define RISCV_PseudoVLUXSEG3EI8_V_M1_M1_MASK 5078 +#define RISCV_PseudoVLUXSEG3EI8_V_M1_M2 5079 +#define RISCV_PseudoVLUXSEG3EI8_V_M1_M2_MASK 5080 +#define RISCV_PseudoVLUXSEG3EI8_V_M2_M2 5081 +#define RISCV_PseudoVLUXSEG3EI8_V_M2_M2_MASK 5082 +#define RISCV_PseudoVLUXSEG3EI8_V_MF2_M1 5083 +#define RISCV_PseudoVLUXSEG3EI8_V_MF2_M1_MASK 5084 +#define RISCV_PseudoVLUXSEG3EI8_V_MF2_M2 5085 +#define RISCV_PseudoVLUXSEG3EI8_V_MF2_M2_MASK 5086 +#define RISCV_PseudoVLUXSEG3EI8_V_MF2_MF2 5087 +#define RISCV_PseudoVLUXSEG3EI8_V_MF2_MF2_MASK 5088 +#define RISCV_PseudoVLUXSEG3EI8_V_MF4_M1 5089 +#define RISCV_PseudoVLUXSEG3EI8_V_MF4_M1_MASK 5090 +#define RISCV_PseudoVLUXSEG3EI8_V_MF4_M2 5091 +#define RISCV_PseudoVLUXSEG3EI8_V_MF4_M2_MASK 5092 +#define RISCV_PseudoVLUXSEG3EI8_V_MF4_MF2 5093 +#define RISCV_PseudoVLUXSEG3EI8_V_MF4_MF2_MASK 5094 +#define RISCV_PseudoVLUXSEG3EI8_V_MF4_MF4 5095 +#define RISCV_PseudoVLUXSEG3EI8_V_MF4_MF4_MASK 5096 +#define RISCV_PseudoVLUXSEG3EI8_V_MF8_M1 5097 +#define RISCV_PseudoVLUXSEG3EI8_V_MF8_M1_MASK 5098 +#define RISCV_PseudoVLUXSEG3EI8_V_MF8_MF2 5099 +#define RISCV_PseudoVLUXSEG3EI8_V_MF8_MF2_MASK 5100 +#define RISCV_PseudoVLUXSEG3EI8_V_MF8_MF4 5101 +#define RISCV_PseudoVLUXSEG3EI8_V_MF8_MF4_MASK 5102 +#define RISCV_PseudoVLUXSEG3EI8_V_MF8_MF8 5103 +#define RISCV_PseudoVLUXSEG3EI8_V_MF8_MF8_MASK 5104 +#define RISCV_PseudoVLUXSEG4EI16_V_M1_M1 5105 +#define RISCV_PseudoVLUXSEG4EI16_V_M1_M1_MASK 5106 +#define RISCV_PseudoVLUXSEG4EI16_V_M1_M2 5107 +#define RISCV_PseudoVLUXSEG4EI16_V_M1_M2_MASK 5108 +#define RISCV_PseudoVLUXSEG4EI16_V_M1_MF2 5109 +#define RISCV_PseudoVLUXSEG4EI16_V_M1_MF2_MASK 5110 +#define RISCV_PseudoVLUXSEG4EI16_V_M2_M1 5111 +#define RISCV_PseudoVLUXSEG4EI16_V_M2_M1_MASK 5112 +#define RISCV_PseudoVLUXSEG4EI16_V_M2_M2 5113 +#define RISCV_PseudoVLUXSEG4EI16_V_M2_M2_MASK 5114 +#define RISCV_PseudoVLUXSEG4EI16_V_M4_M2 5115 +#define RISCV_PseudoVLUXSEG4EI16_V_M4_M2_MASK 5116 +#define RISCV_PseudoVLUXSEG4EI16_V_MF2_M1 5117 +#define RISCV_PseudoVLUXSEG4EI16_V_MF2_M1_MASK 5118 +#define RISCV_PseudoVLUXSEG4EI16_V_MF2_M2 5119 +#define RISCV_PseudoVLUXSEG4EI16_V_MF2_M2_MASK 5120 +#define RISCV_PseudoVLUXSEG4EI16_V_MF2_MF2 5121 +#define RISCV_PseudoVLUXSEG4EI16_V_MF2_MF2_MASK 5122 +#define RISCV_PseudoVLUXSEG4EI16_V_MF2_MF4 5123 +#define RISCV_PseudoVLUXSEG4EI16_V_MF2_MF4_MASK 5124 +#define RISCV_PseudoVLUXSEG4EI16_V_MF4_M1 5125 +#define RISCV_PseudoVLUXSEG4EI16_V_MF4_M1_MASK 5126 +#define RISCV_PseudoVLUXSEG4EI16_V_MF4_MF2 5127 +#define RISCV_PseudoVLUXSEG4EI16_V_MF4_MF2_MASK 5128 +#define RISCV_PseudoVLUXSEG4EI16_V_MF4_MF4 5129 +#define RISCV_PseudoVLUXSEG4EI16_V_MF4_MF4_MASK 5130 +#define RISCV_PseudoVLUXSEG4EI16_V_MF4_MF8 5131 +#define RISCV_PseudoVLUXSEG4EI16_V_MF4_MF8_MASK 5132 +#define RISCV_PseudoVLUXSEG4EI32_V_M1_M1 5133 +#define RISCV_PseudoVLUXSEG4EI32_V_M1_M1_MASK 5134 +#define RISCV_PseudoVLUXSEG4EI32_V_M1_M2 5135 +#define RISCV_PseudoVLUXSEG4EI32_V_M1_M2_MASK 5136 +#define RISCV_PseudoVLUXSEG4EI32_V_M1_MF2 5137 +#define RISCV_PseudoVLUXSEG4EI32_V_M1_MF2_MASK 5138 +#define RISCV_PseudoVLUXSEG4EI32_V_M1_MF4 5139 +#define RISCV_PseudoVLUXSEG4EI32_V_M1_MF4_MASK 5140 +#define RISCV_PseudoVLUXSEG4EI32_V_M2_M1 5141 +#define RISCV_PseudoVLUXSEG4EI32_V_M2_M1_MASK 5142 +#define RISCV_PseudoVLUXSEG4EI32_V_M2_M2 5143 +#define RISCV_PseudoVLUXSEG4EI32_V_M2_M2_MASK 5144 +#define RISCV_PseudoVLUXSEG4EI32_V_M2_MF2 5145 +#define RISCV_PseudoVLUXSEG4EI32_V_M2_MF2_MASK 5146 +#define RISCV_PseudoVLUXSEG4EI32_V_M4_M1 5147 +#define RISCV_PseudoVLUXSEG4EI32_V_M4_M1_MASK 5148 +#define RISCV_PseudoVLUXSEG4EI32_V_M4_M2 5149 +#define RISCV_PseudoVLUXSEG4EI32_V_M4_M2_MASK 5150 +#define RISCV_PseudoVLUXSEG4EI32_V_M8_M2 5151 +#define RISCV_PseudoVLUXSEG4EI32_V_M8_M2_MASK 5152 +#define RISCV_PseudoVLUXSEG4EI32_V_MF2_M1 5153 +#define RISCV_PseudoVLUXSEG4EI32_V_MF2_M1_MASK 5154 +#define RISCV_PseudoVLUXSEG4EI32_V_MF2_MF2 5155 +#define RISCV_PseudoVLUXSEG4EI32_V_MF2_MF2_MASK 5156 +#define RISCV_PseudoVLUXSEG4EI32_V_MF2_MF4 5157 +#define RISCV_PseudoVLUXSEG4EI32_V_MF2_MF4_MASK 5158 +#define RISCV_PseudoVLUXSEG4EI32_V_MF2_MF8 5159 +#define RISCV_PseudoVLUXSEG4EI32_V_MF2_MF8_MASK 5160 +#define RISCV_PseudoVLUXSEG4EI64_V_M1_M1 5161 +#define RISCV_PseudoVLUXSEG4EI64_V_M1_M1_MASK 5162 +#define RISCV_PseudoVLUXSEG4EI64_V_M1_MF2 5163 +#define RISCV_PseudoVLUXSEG4EI64_V_M1_MF2_MASK 5164 +#define RISCV_PseudoVLUXSEG4EI64_V_M1_MF4 5165 +#define RISCV_PseudoVLUXSEG4EI64_V_M1_MF4_MASK 5166 +#define RISCV_PseudoVLUXSEG4EI64_V_M1_MF8 5167 +#define RISCV_PseudoVLUXSEG4EI64_V_M1_MF8_MASK 5168 +#define RISCV_PseudoVLUXSEG4EI64_V_M2_M1 5169 +#define RISCV_PseudoVLUXSEG4EI64_V_M2_M1_MASK 5170 +#define RISCV_PseudoVLUXSEG4EI64_V_M2_M2 5171 +#define RISCV_PseudoVLUXSEG4EI64_V_M2_M2_MASK 5172 +#define RISCV_PseudoVLUXSEG4EI64_V_M2_MF2 5173 +#define RISCV_PseudoVLUXSEG4EI64_V_M2_MF2_MASK 5174 +#define RISCV_PseudoVLUXSEG4EI64_V_M2_MF4 5175 +#define RISCV_PseudoVLUXSEG4EI64_V_M2_MF4_MASK 5176 +#define RISCV_PseudoVLUXSEG4EI64_V_M4_M1 5177 +#define RISCV_PseudoVLUXSEG4EI64_V_M4_M1_MASK 5178 +#define RISCV_PseudoVLUXSEG4EI64_V_M4_M2 5179 +#define RISCV_PseudoVLUXSEG4EI64_V_M4_M2_MASK 5180 +#define RISCV_PseudoVLUXSEG4EI64_V_M4_MF2 5181 +#define RISCV_PseudoVLUXSEG4EI64_V_M4_MF2_MASK 5182 +#define RISCV_PseudoVLUXSEG4EI64_V_M8_M1 5183 +#define RISCV_PseudoVLUXSEG4EI64_V_M8_M1_MASK 5184 +#define RISCV_PseudoVLUXSEG4EI64_V_M8_M2 5185 +#define RISCV_PseudoVLUXSEG4EI64_V_M8_M2_MASK 5186 +#define RISCV_PseudoVLUXSEG4EI8_V_M1_M1 5187 +#define RISCV_PseudoVLUXSEG4EI8_V_M1_M1_MASK 5188 +#define RISCV_PseudoVLUXSEG4EI8_V_M1_M2 5189 +#define RISCV_PseudoVLUXSEG4EI8_V_M1_M2_MASK 5190 +#define RISCV_PseudoVLUXSEG4EI8_V_M2_M2 5191 +#define RISCV_PseudoVLUXSEG4EI8_V_M2_M2_MASK 5192 +#define RISCV_PseudoVLUXSEG4EI8_V_MF2_M1 5193 +#define RISCV_PseudoVLUXSEG4EI8_V_MF2_M1_MASK 5194 +#define RISCV_PseudoVLUXSEG4EI8_V_MF2_M2 5195 +#define RISCV_PseudoVLUXSEG4EI8_V_MF2_M2_MASK 5196 +#define RISCV_PseudoVLUXSEG4EI8_V_MF2_MF2 5197 +#define RISCV_PseudoVLUXSEG4EI8_V_MF2_MF2_MASK 5198 +#define RISCV_PseudoVLUXSEG4EI8_V_MF4_M1 5199 +#define RISCV_PseudoVLUXSEG4EI8_V_MF4_M1_MASK 5200 +#define RISCV_PseudoVLUXSEG4EI8_V_MF4_M2 5201 +#define RISCV_PseudoVLUXSEG4EI8_V_MF4_M2_MASK 5202 +#define RISCV_PseudoVLUXSEG4EI8_V_MF4_MF2 5203 +#define RISCV_PseudoVLUXSEG4EI8_V_MF4_MF2_MASK 5204 +#define RISCV_PseudoVLUXSEG4EI8_V_MF4_MF4 5205 +#define RISCV_PseudoVLUXSEG4EI8_V_MF4_MF4_MASK 5206 +#define RISCV_PseudoVLUXSEG4EI8_V_MF8_M1 5207 +#define RISCV_PseudoVLUXSEG4EI8_V_MF8_M1_MASK 5208 +#define RISCV_PseudoVLUXSEG4EI8_V_MF8_MF2 5209 +#define RISCV_PseudoVLUXSEG4EI8_V_MF8_MF2_MASK 5210 +#define RISCV_PseudoVLUXSEG4EI8_V_MF8_MF4 5211 +#define RISCV_PseudoVLUXSEG4EI8_V_MF8_MF4_MASK 5212 +#define RISCV_PseudoVLUXSEG4EI8_V_MF8_MF8 5213 +#define RISCV_PseudoVLUXSEG4EI8_V_MF8_MF8_MASK 5214 +#define RISCV_PseudoVLUXSEG5EI16_V_M1_M1 5215 +#define RISCV_PseudoVLUXSEG5EI16_V_M1_M1_MASK 5216 +#define RISCV_PseudoVLUXSEG5EI16_V_M1_MF2 5217 +#define RISCV_PseudoVLUXSEG5EI16_V_M1_MF2_MASK 5218 +#define RISCV_PseudoVLUXSEG5EI16_V_M2_M1 5219 +#define RISCV_PseudoVLUXSEG5EI16_V_M2_M1_MASK 5220 +#define RISCV_PseudoVLUXSEG5EI16_V_MF2_M1 5221 +#define RISCV_PseudoVLUXSEG5EI16_V_MF2_M1_MASK 5222 +#define RISCV_PseudoVLUXSEG5EI16_V_MF2_MF2 5223 +#define RISCV_PseudoVLUXSEG5EI16_V_MF2_MF2_MASK 5224 +#define RISCV_PseudoVLUXSEG5EI16_V_MF2_MF4 5225 +#define RISCV_PseudoVLUXSEG5EI16_V_MF2_MF4_MASK 5226 +#define RISCV_PseudoVLUXSEG5EI16_V_MF4_M1 5227 +#define RISCV_PseudoVLUXSEG5EI16_V_MF4_M1_MASK 5228 +#define RISCV_PseudoVLUXSEG5EI16_V_MF4_MF2 5229 +#define RISCV_PseudoVLUXSEG5EI16_V_MF4_MF2_MASK 5230 +#define RISCV_PseudoVLUXSEG5EI16_V_MF4_MF4 5231 +#define RISCV_PseudoVLUXSEG5EI16_V_MF4_MF4_MASK 5232 +#define RISCV_PseudoVLUXSEG5EI16_V_MF4_MF8 5233 +#define RISCV_PseudoVLUXSEG5EI16_V_MF4_MF8_MASK 5234 +#define RISCV_PseudoVLUXSEG5EI32_V_M1_M1 5235 +#define RISCV_PseudoVLUXSEG5EI32_V_M1_M1_MASK 5236 +#define RISCV_PseudoVLUXSEG5EI32_V_M1_MF2 5237 +#define RISCV_PseudoVLUXSEG5EI32_V_M1_MF2_MASK 5238 +#define RISCV_PseudoVLUXSEG5EI32_V_M1_MF4 5239 +#define RISCV_PseudoVLUXSEG5EI32_V_M1_MF4_MASK 5240 +#define RISCV_PseudoVLUXSEG5EI32_V_M2_M1 5241 +#define RISCV_PseudoVLUXSEG5EI32_V_M2_M1_MASK 5242 +#define RISCV_PseudoVLUXSEG5EI32_V_M2_MF2 5243 +#define RISCV_PseudoVLUXSEG5EI32_V_M2_MF2_MASK 5244 +#define RISCV_PseudoVLUXSEG5EI32_V_M4_M1 5245 +#define RISCV_PseudoVLUXSEG5EI32_V_M4_M1_MASK 5246 +#define RISCV_PseudoVLUXSEG5EI32_V_MF2_M1 5247 +#define RISCV_PseudoVLUXSEG5EI32_V_MF2_M1_MASK 5248 +#define RISCV_PseudoVLUXSEG5EI32_V_MF2_MF2 5249 +#define RISCV_PseudoVLUXSEG5EI32_V_MF2_MF2_MASK 5250 +#define RISCV_PseudoVLUXSEG5EI32_V_MF2_MF4 5251 +#define RISCV_PseudoVLUXSEG5EI32_V_MF2_MF4_MASK 5252 +#define RISCV_PseudoVLUXSEG5EI32_V_MF2_MF8 5253 +#define RISCV_PseudoVLUXSEG5EI32_V_MF2_MF8_MASK 5254 +#define RISCV_PseudoVLUXSEG5EI64_V_M1_M1 5255 +#define RISCV_PseudoVLUXSEG5EI64_V_M1_M1_MASK 5256 +#define RISCV_PseudoVLUXSEG5EI64_V_M1_MF2 5257 +#define RISCV_PseudoVLUXSEG5EI64_V_M1_MF2_MASK 5258 +#define RISCV_PseudoVLUXSEG5EI64_V_M1_MF4 5259 +#define RISCV_PseudoVLUXSEG5EI64_V_M1_MF4_MASK 5260 +#define RISCV_PseudoVLUXSEG5EI64_V_M1_MF8 5261 +#define RISCV_PseudoVLUXSEG5EI64_V_M1_MF8_MASK 5262 +#define RISCV_PseudoVLUXSEG5EI64_V_M2_M1 5263 +#define RISCV_PseudoVLUXSEG5EI64_V_M2_M1_MASK 5264 +#define RISCV_PseudoVLUXSEG5EI64_V_M2_MF2 5265 +#define RISCV_PseudoVLUXSEG5EI64_V_M2_MF2_MASK 5266 +#define RISCV_PseudoVLUXSEG5EI64_V_M2_MF4 5267 +#define RISCV_PseudoVLUXSEG5EI64_V_M2_MF4_MASK 5268 +#define RISCV_PseudoVLUXSEG5EI64_V_M4_M1 5269 +#define RISCV_PseudoVLUXSEG5EI64_V_M4_M1_MASK 5270 +#define RISCV_PseudoVLUXSEG5EI64_V_M4_MF2 5271 +#define RISCV_PseudoVLUXSEG5EI64_V_M4_MF2_MASK 5272 +#define RISCV_PseudoVLUXSEG5EI64_V_M8_M1 5273 +#define RISCV_PseudoVLUXSEG5EI64_V_M8_M1_MASK 5274 +#define RISCV_PseudoVLUXSEG5EI8_V_M1_M1 5275 +#define RISCV_PseudoVLUXSEG5EI8_V_M1_M1_MASK 5276 +#define RISCV_PseudoVLUXSEG5EI8_V_MF2_M1 5277 +#define RISCV_PseudoVLUXSEG5EI8_V_MF2_M1_MASK 5278 +#define RISCV_PseudoVLUXSEG5EI8_V_MF2_MF2 5279 +#define RISCV_PseudoVLUXSEG5EI8_V_MF2_MF2_MASK 5280 +#define RISCV_PseudoVLUXSEG5EI8_V_MF4_M1 5281 +#define RISCV_PseudoVLUXSEG5EI8_V_MF4_M1_MASK 5282 +#define RISCV_PseudoVLUXSEG5EI8_V_MF4_MF2 5283 +#define RISCV_PseudoVLUXSEG5EI8_V_MF4_MF2_MASK 5284 +#define RISCV_PseudoVLUXSEG5EI8_V_MF4_MF4 5285 +#define RISCV_PseudoVLUXSEG5EI8_V_MF4_MF4_MASK 5286 +#define RISCV_PseudoVLUXSEG5EI8_V_MF8_M1 5287 +#define RISCV_PseudoVLUXSEG5EI8_V_MF8_M1_MASK 5288 +#define RISCV_PseudoVLUXSEG5EI8_V_MF8_MF2 5289 +#define RISCV_PseudoVLUXSEG5EI8_V_MF8_MF2_MASK 5290 +#define RISCV_PseudoVLUXSEG5EI8_V_MF8_MF4 5291 +#define RISCV_PseudoVLUXSEG5EI8_V_MF8_MF4_MASK 5292 +#define RISCV_PseudoVLUXSEG5EI8_V_MF8_MF8 5293 +#define RISCV_PseudoVLUXSEG5EI8_V_MF8_MF8_MASK 5294 +#define RISCV_PseudoVLUXSEG6EI16_V_M1_M1 5295 +#define RISCV_PseudoVLUXSEG6EI16_V_M1_M1_MASK 5296 +#define RISCV_PseudoVLUXSEG6EI16_V_M1_MF2 5297 +#define RISCV_PseudoVLUXSEG6EI16_V_M1_MF2_MASK 5298 +#define RISCV_PseudoVLUXSEG6EI16_V_M2_M1 5299 +#define RISCV_PseudoVLUXSEG6EI16_V_M2_M1_MASK 5300 +#define RISCV_PseudoVLUXSEG6EI16_V_MF2_M1 5301 +#define RISCV_PseudoVLUXSEG6EI16_V_MF2_M1_MASK 5302 +#define RISCV_PseudoVLUXSEG6EI16_V_MF2_MF2 5303 +#define RISCV_PseudoVLUXSEG6EI16_V_MF2_MF2_MASK 5304 +#define RISCV_PseudoVLUXSEG6EI16_V_MF2_MF4 5305 +#define RISCV_PseudoVLUXSEG6EI16_V_MF2_MF4_MASK 5306 +#define RISCV_PseudoVLUXSEG6EI16_V_MF4_M1 5307 +#define RISCV_PseudoVLUXSEG6EI16_V_MF4_M1_MASK 5308 +#define RISCV_PseudoVLUXSEG6EI16_V_MF4_MF2 5309 +#define RISCV_PseudoVLUXSEG6EI16_V_MF4_MF2_MASK 5310 +#define RISCV_PseudoVLUXSEG6EI16_V_MF4_MF4 5311 +#define RISCV_PseudoVLUXSEG6EI16_V_MF4_MF4_MASK 5312 +#define RISCV_PseudoVLUXSEG6EI16_V_MF4_MF8 5313 +#define RISCV_PseudoVLUXSEG6EI16_V_MF4_MF8_MASK 5314 +#define RISCV_PseudoVLUXSEG6EI32_V_M1_M1 5315 +#define RISCV_PseudoVLUXSEG6EI32_V_M1_M1_MASK 5316 +#define RISCV_PseudoVLUXSEG6EI32_V_M1_MF2 5317 +#define RISCV_PseudoVLUXSEG6EI32_V_M1_MF2_MASK 5318 +#define RISCV_PseudoVLUXSEG6EI32_V_M1_MF4 5319 +#define RISCV_PseudoVLUXSEG6EI32_V_M1_MF4_MASK 5320 +#define RISCV_PseudoVLUXSEG6EI32_V_M2_M1 5321 +#define RISCV_PseudoVLUXSEG6EI32_V_M2_M1_MASK 5322 +#define RISCV_PseudoVLUXSEG6EI32_V_M2_MF2 5323 +#define RISCV_PseudoVLUXSEG6EI32_V_M2_MF2_MASK 5324 +#define RISCV_PseudoVLUXSEG6EI32_V_M4_M1 5325 +#define RISCV_PseudoVLUXSEG6EI32_V_M4_M1_MASK 5326 +#define RISCV_PseudoVLUXSEG6EI32_V_MF2_M1 5327 +#define RISCV_PseudoVLUXSEG6EI32_V_MF2_M1_MASK 5328 +#define RISCV_PseudoVLUXSEG6EI32_V_MF2_MF2 5329 +#define RISCV_PseudoVLUXSEG6EI32_V_MF2_MF2_MASK 5330 +#define RISCV_PseudoVLUXSEG6EI32_V_MF2_MF4 5331 +#define RISCV_PseudoVLUXSEG6EI32_V_MF2_MF4_MASK 5332 +#define RISCV_PseudoVLUXSEG6EI32_V_MF2_MF8 5333 +#define RISCV_PseudoVLUXSEG6EI32_V_MF2_MF8_MASK 5334 +#define RISCV_PseudoVLUXSEG6EI64_V_M1_M1 5335 +#define RISCV_PseudoVLUXSEG6EI64_V_M1_M1_MASK 5336 +#define RISCV_PseudoVLUXSEG6EI64_V_M1_MF2 5337 +#define RISCV_PseudoVLUXSEG6EI64_V_M1_MF2_MASK 5338 +#define RISCV_PseudoVLUXSEG6EI64_V_M1_MF4 5339 +#define RISCV_PseudoVLUXSEG6EI64_V_M1_MF4_MASK 5340 +#define RISCV_PseudoVLUXSEG6EI64_V_M1_MF8 5341 +#define RISCV_PseudoVLUXSEG6EI64_V_M1_MF8_MASK 5342 +#define RISCV_PseudoVLUXSEG6EI64_V_M2_M1 5343 +#define RISCV_PseudoVLUXSEG6EI64_V_M2_M1_MASK 5344 +#define RISCV_PseudoVLUXSEG6EI64_V_M2_MF2 5345 +#define RISCV_PseudoVLUXSEG6EI64_V_M2_MF2_MASK 5346 +#define RISCV_PseudoVLUXSEG6EI64_V_M2_MF4 5347 +#define RISCV_PseudoVLUXSEG6EI64_V_M2_MF4_MASK 5348 +#define RISCV_PseudoVLUXSEG6EI64_V_M4_M1 5349 +#define RISCV_PseudoVLUXSEG6EI64_V_M4_M1_MASK 5350 +#define RISCV_PseudoVLUXSEG6EI64_V_M4_MF2 5351 +#define RISCV_PseudoVLUXSEG6EI64_V_M4_MF2_MASK 5352 +#define RISCV_PseudoVLUXSEG6EI64_V_M8_M1 5353 +#define RISCV_PseudoVLUXSEG6EI64_V_M8_M1_MASK 5354 +#define RISCV_PseudoVLUXSEG6EI8_V_M1_M1 5355 +#define RISCV_PseudoVLUXSEG6EI8_V_M1_M1_MASK 5356 +#define RISCV_PseudoVLUXSEG6EI8_V_MF2_M1 5357 +#define RISCV_PseudoVLUXSEG6EI8_V_MF2_M1_MASK 5358 +#define RISCV_PseudoVLUXSEG6EI8_V_MF2_MF2 5359 +#define RISCV_PseudoVLUXSEG6EI8_V_MF2_MF2_MASK 5360 +#define RISCV_PseudoVLUXSEG6EI8_V_MF4_M1 5361 +#define RISCV_PseudoVLUXSEG6EI8_V_MF4_M1_MASK 5362 +#define RISCV_PseudoVLUXSEG6EI8_V_MF4_MF2 5363 +#define RISCV_PseudoVLUXSEG6EI8_V_MF4_MF2_MASK 5364 +#define RISCV_PseudoVLUXSEG6EI8_V_MF4_MF4 5365 +#define RISCV_PseudoVLUXSEG6EI8_V_MF4_MF4_MASK 5366 +#define RISCV_PseudoVLUXSEG6EI8_V_MF8_M1 5367 +#define RISCV_PseudoVLUXSEG6EI8_V_MF8_M1_MASK 5368 +#define RISCV_PseudoVLUXSEG6EI8_V_MF8_MF2 5369 +#define RISCV_PseudoVLUXSEG6EI8_V_MF8_MF2_MASK 5370 +#define RISCV_PseudoVLUXSEG6EI8_V_MF8_MF4 5371 +#define RISCV_PseudoVLUXSEG6EI8_V_MF8_MF4_MASK 5372 +#define RISCV_PseudoVLUXSEG6EI8_V_MF8_MF8 5373 +#define RISCV_PseudoVLUXSEG6EI8_V_MF8_MF8_MASK 5374 +#define RISCV_PseudoVLUXSEG7EI16_V_M1_M1 5375 +#define RISCV_PseudoVLUXSEG7EI16_V_M1_M1_MASK 5376 +#define RISCV_PseudoVLUXSEG7EI16_V_M1_MF2 5377 +#define RISCV_PseudoVLUXSEG7EI16_V_M1_MF2_MASK 5378 +#define RISCV_PseudoVLUXSEG7EI16_V_M2_M1 5379 +#define RISCV_PseudoVLUXSEG7EI16_V_M2_M1_MASK 5380 +#define RISCV_PseudoVLUXSEG7EI16_V_MF2_M1 5381 +#define RISCV_PseudoVLUXSEG7EI16_V_MF2_M1_MASK 5382 +#define RISCV_PseudoVLUXSEG7EI16_V_MF2_MF2 5383 +#define RISCV_PseudoVLUXSEG7EI16_V_MF2_MF2_MASK 5384 +#define RISCV_PseudoVLUXSEG7EI16_V_MF2_MF4 5385 +#define RISCV_PseudoVLUXSEG7EI16_V_MF2_MF4_MASK 5386 +#define RISCV_PseudoVLUXSEG7EI16_V_MF4_M1 5387 +#define RISCV_PseudoVLUXSEG7EI16_V_MF4_M1_MASK 5388 +#define RISCV_PseudoVLUXSEG7EI16_V_MF4_MF2 5389 +#define RISCV_PseudoVLUXSEG7EI16_V_MF4_MF2_MASK 5390 +#define RISCV_PseudoVLUXSEG7EI16_V_MF4_MF4 5391 +#define RISCV_PseudoVLUXSEG7EI16_V_MF4_MF4_MASK 5392 +#define RISCV_PseudoVLUXSEG7EI16_V_MF4_MF8 5393 +#define RISCV_PseudoVLUXSEG7EI16_V_MF4_MF8_MASK 5394 +#define RISCV_PseudoVLUXSEG7EI32_V_M1_M1 5395 +#define RISCV_PseudoVLUXSEG7EI32_V_M1_M1_MASK 5396 +#define RISCV_PseudoVLUXSEG7EI32_V_M1_MF2 5397 +#define RISCV_PseudoVLUXSEG7EI32_V_M1_MF2_MASK 5398 +#define RISCV_PseudoVLUXSEG7EI32_V_M1_MF4 5399 +#define RISCV_PseudoVLUXSEG7EI32_V_M1_MF4_MASK 5400 +#define RISCV_PseudoVLUXSEG7EI32_V_M2_M1 5401 +#define RISCV_PseudoVLUXSEG7EI32_V_M2_M1_MASK 5402 +#define RISCV_PseudoVLUXSEG7EI32_V_M2_MF2 5403 +#define RISCV_PseudoVLUXSEG7EI32_V_M2_MF2_MASK 5404 +#define RISCV_PseudoVLUXSEG7EI32_V_M4_M1 5405 +#define RISCV_PseudoVLUXSEG7EI32_V_M4_M1_MASK 5406 +#define RISCV_PseudoVLUXSEG7EI32_V_MF2_M1 5407 +#define RISCV_PseudoVLUXSEG7EI32_V_MF2_M1_MASK 5408 +#define RISCV_PseudoVLUXSEG7EI32_V_MF2_MF2 5409 +#define RISCV_PseudoVLUXSEG7EI32_V_MF2_MF2_MASK 5410 +#define RISCV_PseudoVLUXSEG7EI32_V_MF2_MF4 5411 +#define RISCV_PseudoVLUXSEG7EI32_V_MF2_MF4_MASK 5412 +#define RISCV_PseudoVLUXSEG7EI32_V_MF2_MF8 5413 +#define RISCV_PseudoVLUXSEG7EI32_V_MF2_MF8_MASK 5414 +#define RISCV_PseudoVLUXSEG7EI64_V_M1_M1 5415 +#define RISCV_PseudoVLUXSEG7EI64_V_M1_M1_MASK 5416 +#define RISCV_PseudoVLUXSEG7EI64_V_M1_MF2 5417 +#define RISCV_PseudoVLUXSEG7EI64_V_M1_MF2_MASK 5418 +#define RISCV_PseudoVLUXSEG7EI64_V_M1_MF4 5419 +#define RISCV_PseudoVLUXSEG7EI64_V_M1_MF4_MASK 5420 +#define RISCV_PseudoVLUXSEG7EI64_V_M1_MF8 5421 +#define RISCV_PseudoVLUXSEG7EI64_V_M1_MF8_MASK 5422 +#define RISCV_PseudoVLUXSEG7EI64_V_M2_M1 5423 +#define RISCV_PseudoVLUXSEG7EI64_V_M2_M1_MASK 5424 +#define RISCV_PseudoVLUXSEG7EI64_V_M2_MF2 5425 +#define RISCV_PseudoVLUXSEG7EI64_V_M2_MF2_MASK 5426 +#define RISCV_PseudoVLUXSEG7EI64_V_M2_MF4 5427 +#define RISCV_PseudoVLUXSEG7EI64_V_M2_MF4_MASK 5428 +#define RISCV_PseudoVLUXSEG7EI64_V_M4_M1 5429 +#define RISCV_PseudoVLUXSEG7EI64_V_M4_M1_MASK 5430 +#define RISCV_PseudoVLUXSEG7EI64_V_M4_MF2 5431 +#define RISCV_PseudoVLUXSEG7EI64_V_M4_MF2_MASK 5432 +#define RISCV_PseudoVLUXSEG7EI64_V_M8_M1 5433 +#define RISCV_PseudoVLUXSEG7EI64_V_M8_M1_MASK 5434 +#define RISCV_PseudoVLUXSEG7EI8_V_M1_M1 5435 +#define RISCV_PseudoVLUXSEG7EI8_V_M1_M1_MASK 5436 +#define RISCV_PseudoVLUXSEG7EI8_V_MF2_M1 5437 +#define RISCV_PseudoVLUXSEG7EI8_V_MF2_M1_MASK 5438 +#define RISCV_PseudoVLUXSEG7EI8_V_MF2_MF2 5439 +#define RISCV_PseudoVLUXSEG7EI8_V_MF2_MF2_MASK 5440 +#define RISCV_PseudoVLUXSEG7EI8_V_MF4_M1 5441 +#define RISCV_PseudoVLUXSEG7EI8_V_MF4_M1_MASK 5442 +#define RISCV_PseudoVLUXSEG7EI8_V_MF4_MF2 5443 +#define RISCV_PseudoVLUXSEG7EI8_V_MF4_MF2_MASK 5444 +#define RISCV_PseudoVLUXSEG7EI8_V_MF4_MF4 5445 +#define RISCV_PseudoVLUXSEG7EI8_V_MF4_MF4_MASK 5446 +#define RISCV_PseudoVLUXSEG7EI8_V_MF8_M1 5447 +#define RISCV_PseudoVLUXSEG7EI8_V_MF8_M1_MASK 5448 +#define RISCV_PseudoVLUXSEG7EI8_V_MF8_MF2 5449 +#define RISCV_PseudoVLUXSEG7EI8_V_MF8_MF2_MASK 5450 +#define RISCV_PseudoVLUXSEG7EI8_V_MF8_MF4 5451 +#define RISCV_PseudoVLUXSEG7EI8_V_MF8_MF4_MASK 5452 +#define RISCV_PseudoVLUXSEG7EI8_V_MF8_MF8 5453 +#define RISCV_PseudoVLUXSEG7EI8_V_MF8_MF8_MASK 5454 +#define RISCV_PseudoVLUXSEG8EI16_V_M1_M1 5455 +#define RISCV_PseudoVLUXSEG8EI16_V_M1_M1_MASK 5456 +#define RISCV_PseudoVLUXSEG8EI16_V_M1_MF2 5457 +#define RISCV_PseudoVLUXSEG8EI16_V_M1_MF2_MASK 5458 +#define RISCV_PseudoVLUXSEG8EI16_V_M2_M1 5459 +#define RISCV_PseudoVLUXSEG8EI16_V_M2_M1_MASK 5460 +#define RISCV_PseudoVLUXSEG8EI16_V_MF2_M1 5461 +#define RISCV_PseudoVLUXSEG8EI16_V_MF2_M1_MASK 5462 +#define RISCV_PseudoVLUXSEG8EI16_V_MF2_MF2 5463 +#define RISCV_PseudoVLUXSEG8EI16_V_MF2_MF2_MASK 5464 +#define RISCV_PseudoVLUXSEG8EI16_V_MF2_MF4 5465 +#define RISCV_PseudoVLUXSEG8EI16_V_MF2_MF4_MASK 5466 +#define RISCV_PseudoVLUXSEG8EI16_V_MF4_M1 5467 +#define RISCV_PseudoVLUXSEG8EI16_V_MF4_M1_MASK 5468 +#define RISCV_PseudoVLUXSEG8EI16_V_MF4_MF2 5469 +#define RISCV_PseudoVLUXSEG8EI16_V_MF4_MF2_MASK 5470 +#define RISCV_PseudoVLUXSEG8EI16_V_MF4_MF4 5471 +#define RISCV_PseudoVLUXSEG8EI16_V_MF4_MF4_MASK 5472 +#define RISCV_PseudoVLUXSEG8EI16_V_MF4_MF8 5473 +#define RISCV_PseudoVLUXSEG8EI16_V_MF4_MF8_MASK 5474 +#define RISCV_PseudoVLUXSEG8EI32_V_M1_M1 5475 +#define RISCV_PseudoVLUXSEG8EI32_V_M1_M1_MASK 5476 +#define RISCV_PseudoVLUXSEG8EI32_V_M1_MF2 5477 +#define RISCV_PseudoVLUXSEG8EI32_V_M1_MF2_MASK 5478 +#define RISCV_PseudoVLUXSEG8EI32_V_M1_MF4 5479 +#define RISCV_PseudoVLUXSEG8EI32_V_M1_MF4_MASK 5480 +#define RISCV_PseudoVLUXSEG8EI32_V_M2_M1 5481 +#define RISCV_PseudoVLUXSEG8EI32_V_M2_M1_MASK 5482 +#define RISCV_PseudoVLUXSEG8EI32_V_M2_MF2 5483 +#define RISCV_PseudoVLUXSEG8EI32_V_M2_MF2_MASK 5484 +#define RISCV_PseudoVLUXSEG8EI32_V_M4_M1 5485 +#define RISCV_PseudoVLUXSEG8EI32_V_M4_M1_MASK 5486 +#define RISCV_PseudoVLUXSEG8EI32_V_MF2_M1 5487 +#define RISCV_PseudoVLUXSEG8EI32_V_MF2_M1_MASK 5488 +#define RISCV_PseudoVLUXSEG8EI32_V_MF2_MF2 5489 +#define RISCV_PseudoVLUXSEG8EI32_V_MF2_MF2_MASK 5490 +#define RISCV_PseudoVLUXSEG8EI32_V_MF2_MF4 5491 +#define RISCV_PseudoVLUXSEG8EI32_V_MF2_MF4_MASK 5492 +#define RISCV_PseudoVLUXSEG8EI32_V_MF2_MF8 5493 +#define RISCV_PseudoVLUXSEG8EI32_V_MF2_MF8_MASK 5494 +#define RISCV_PseudoVLUXSEG8EI64_V_M1_M1 5495 +#define RISCV_PseudoVLUXSEG8EI64_V_M1_M1_MASK 5496 +#define RISCV_PseudoVLUXSEG8EI64_V_M1_MF2 5497 +#define RISCV_PseudoVLUXSEG8EI64_V_M1_MF2_MASK 5498 +#define RISCV_PseudoVLUXSEG8EI64_V_M1_MF4 5499 +#define RISCV_PseudoVLUXSEG8EI64_V_M1_MF4_MASK 5500 +#define RISCV_PseudoVLUXSEG8EI64_V_M1_MF8 5501 +#define RISCV_PseudoVLUXSEG8EI64_V_M1_MF8_MASK 5502 +#define RISCV_PseudoVLUXSEG8EI64_V_M2_M1 5503 +#define RISCV_PseudoVLUXSEG8EI64_V_M2_M1_MASK 5504 +#define RISCV_PseudoVLUXSEG8EI64_V_M2_MF2 5505 +#define RISCV_PseudoVLUXSEG8EI64_V_M2_MF2_MASK 5506 +#define RISCV_PseudoVLUXSEG8EI64_V_M2_MF4 5507 +#define RISCV_PseudoVLUXSEG8EI64_V_M2_MF4_MASK 5508 +#define RISCV_PseudoVLUXSEG8EI64_V_M4_M1 5509 +#define RISCV_PseudoVLUXSEG8EI64_V_M4_M1_MASK 5510 +#define RISCV_PseudoVLUXSEG8EI64_V_M4_MF2 5511 +#define RISCV_PseudoVLUXSEG8EI64_V_M4_MF2_MASK 5512 +#define RISCV_PseudoVLUXSEG8EI64_V_M8_M1 5513 +#define RISCV_PseudoVLUXSEG8EI64_V_M8_M1_MASK 5514 +#define RISCV_PseudoVLUXSEG8EI8_V_M1_M1 5515 +#define RISCV_PseudoVLUXSEG8EI8_V_M1_M1_MASK 5516 +#define RISCV_PseudoVLUXSEG8EI8_V_MF2_M1 5517 +#define RISCV_PseudoVLUXSEG8EI8_V_MF2_M1_MASK 5518 +#define RISCV_PseudoVLUXSEG8EI8_V_MF2_MF2 5519 +#define RISCV_PseudoVLUXSEG8EI8_V_MF2_MF2_MASK 5520 +#define RISCV_PseudoVLUXSEG8EI8_V_MF4_M1 5521 +#define RISCV_PseudoVLUXSEG8EI8_V_MF4_M1_MASK 5522 +#define RISCV_PseudoVLUXSEG8EI8_V_MF4_MF2 5523 +#define RISCV_PseudoVLUXSEG8EI8_V_MF4_MF2_MASK 5524 +#define RISCV_PseudoVLUXSEG8EI8_V_MF4_MF4 5525 +#define RISCV_PseudoVLUXSEG8EI8_V_MF4_MF4_MASK 5526 +#define RISCV_PseudoVLUXSEG8EI8_V_MF8_M1 5527 +#define RISCV_PseudoVLUXSEG8EI8_V_MF8_M1_MASK 5528 +#define RISCV_PseudoVLUXSEG8EI8_V_MF8_MF2 5529 +#define RISCV_PseudoVLUXSEG8EI8_V_MF8_MF2_MASK 5530 +#define RISCV_PseudoVLUXSEG8EI8_V_MF8_MF4 5531 +#define RISCV_PseudoVLUXSEG8EI8_V_MF8_MF4_MASK 5532 +#define RISCV_PseudoVLUXSEG8EI8_V_MF8_MF8 5533 +#define RISCV_PseudoVLUXSEG8EI8_V_MF8_MF8_MASK 5534 +#define RISCV_PseudoVMACC_VV_M1 5535 +#define RISCV_PseudoVMACC_VV_M1_MASK 5536 +#define RISCV_PseudoVMACC_VV_M2 5537 +#define RISCV_PseudoVMACC_VV_M2_MASK 5538 +#define RISCV_PseudoVMACC_VV_M4 5539 +#define RISCV_PseudoVMACC_VV_M4_MASK 5540 +#define RISCV_PseudoVMACC_VV_M8 5541 +#define RISCV_PseudoVMACC_VV_M8_MASK 5542 +#define RISCV_PseudoVMACC_VV_MF2 5543 +#define RISCV_PseudoVMACC_VV_MF2_MASK 5544 +#define RISCV_PseudoVMACC_VV_MF4 5545 +#define RISCV_PseudoVMACC_VV_MF4_MASK 5546 +#define RISCV_PseudoVMACC_VV_MF8 5547 +#define RISCV_PseudoVMACC_VV_MF8_MASK 5548 +#define RISCV_PseudoVMACC_VX_M1 5549 +#define RISCV_PseudoVMACC_VX_M1_MASK 5550 +#define RISCV_PseudoVMACC_VX_M2 5551 +#define RISCV_PseudoVMACC_VX_M2_MASK 5552 +#define RISCV_PseudoVMACC_VX_M4 5553 +#define RISCV_PseudoVMACC_VX_M4_MASK 5554 +#define RISCV_PseudoVMACC_VX_M8 5555 +#define RISCV_PseudoVMACC_VX_M8_MASK 5556 +#define RISCV_PseudoVMACC_VX_MF2 5557 +#define RISCV_PseudoVMACC_VX_MF2_MASK 5558 +#define RISCV_PseudoVMACC_VX_MF4 5559 +#define RISCV_PseudoVMACC_VX_MF4_MASK 5560 +#define RISCV_PseudoVMACC_VX_MF8 5561 +#define RISCV_PseudoVMACC_VX_MF8_MASK 5562 +#define RISCV_PseudoVMADC_VIM_M1 5563 +#define RISCV_PseudoVMADC_VIM_M2 5564 +#define RISCV_PseudoVMADC_VIM_M4 5565 +#define RISCV_PseudoVMADC_VIM_M8 5566 +#define RISCV_PseudoVMADC_VIM_MF2 5567 +#define RISCV_PseudoVMADC_VIM_MF4 5568 +#define RISCV_PseudoVMADC_VIM_MF8 5569 +#define RISCV_PseudoVMADC_VI_M1 5570 +#define RISCV_PseudoVMADC_VI_M2 5571 +#define RISCV_PseudoVMADC_VI_M4 5572 +#define RISCV_PseudoVMADC_VI_M8 5573 +#define RISCV_PseudoVMADC_VI_MF2 5574 +#define RISCV_PseudoVMADC_VI_MF4 5575 +#define RISCV_PseudoVMADC_VI_MF8 5576 +#define RISCV_PseudoVMADC_VVM_M1 5577 +#define RISCV_PseudoVMADC_VVM_M2 5578 +#define RISCV_PseudoVMADC_VVM_M4 5579 +#define RISCV_PseudoVMADC_VVM_M8 5580 +#define RISCV_PseudoVMADC_VVM_MF2 5581 +#define RISCV_PseudoVMADC_VVM_MF4 5582 +#define RISCV_PseudoVMADC_VVM_MF8 5583 +#define RISCV_PseudoVMADC_VV_M1 5584 +#define RISCV_PseudoVMADC_VV_M2 5585 +#define RISCV_PseudoVMADC_VV_M4 5586 +#define RISCV_PseudoVMADC_VV_M8 5587 +#define RISCV_PseudoVMADC_VV_MF2 5588 +#define RISCV_PseudoVMADC_VV_MF4 5589 +#define RISCV_PseudoVMADC_VV_MF8 5590 +#define RISCV_PseudoVMADC_VXM_M1 5591 +#define RISCV_PseudoVMADC_VXM_M2 5592 +#define RISCV_PseudoVMADC_VXM_M4 5593 +#define RISCV_PseudoVMADC_VXM_M8 5594 +#define RISCV_PseudoVMADC_VXM_MF2 5595 +#define RISCV_PseudoVMADC_VXM_MF4 5596 +#define RISCV_PseudoVMADC_VXM_MF8 5597 +#define RISCV_PseudoVMADC_VX_M1 5598 +#define RISCV_PseudoVMADC_VX_M2 5599 +#define RISCV_PseudoVMADC_VX_M4 5600 +#define RISCV_PseudoVMADC_VX_M8 5601 +#define RISCV_PseudoVMADC_VX_MF2 5602 +#define RISCV_PseudoVMADC_VX_MF4 5603 +#define RISCV_PseudoVMADC_VX_MF8 5604 +#define RISCV_PseudoVMADD_VV_M1 5605 +#define RISCV_PseudoVMADD_VV_M1_MASK 5606 +#define RISCV_PseudoVMADD_VV_M2 5607 +#define RISCV_PseudoVMADD_VV_M2_MASK 5608 +#define RISCV_PseudoVMADD_VV_M4 5609 +#define RISCV_PseudoVMADD_VV_M4_MASK 5610 +#define RISCV_PseudoVMADD_VV_M8 5611 +#define RISCV_PseudoVMADD_VV_M8_MASK 5612 +#define RISCV_PseudoVMADD_VV_MF2 5613 +#define RISCV_PseudoVMADD_VV_MF2_MASK 5614 +#define RISCV_PseudoVMADD_VV_MF4 5615 +#define RISCV_PseudoVMADD_VV_MF4_MASK 5616 +#define RISCV_PseudoVMADD_VV_MF8 5617 +#define RISCV_PseudoVMADD_VV_MF8_MASK 5618 +#define RISCV_PseudoVMADD_VX_M1 5619 +#define RISCV_PseudoVMADD_VX_M1_MASK 5620 +#define RISCV_PseudoVMADD_VX_M2 5621 +#define RISCV_PseudoVMADD_VX_M2_MASK 5622 +#define RISCV_PseudoVMADD_VX_M4 5623 +#define RISCV_PseudoVMADD_VX_M4_MASK 5624 +#define RISCV_PseudoVMADD_VX_M8 5625 +#define RISCV_PseudoVMADD_VX_M8_MASK 5626 +#define RISCV_PseudoVMADD_VX_MF2 5627 +#define RISCV_PseudoVMADD_VX_MF2_MASK 5628 +#define RISCV_PseudoVMADD_VX_MF4 5629 +#define RISCV_PseudoVMADD_VX_MF4_MASK 5630 +#define RISCV_PseudoVMADD_VX_MF8 5631 +#define RISCV_PseudoVMADD_VX_MF8_MASK 5632 +#define RISCV_PseudoVMANDN_MM_M1 5633 +#define RISCV_PseudoVMANDN_MM_M2 5634 +#define RISCV_PseudoVMANDN_MM_M4 5635 +#define RISCV_PseudoVMANDN_MM_M8 5636 +#define RISCV_PseudoVMANDN_MM_MF2 5637 +#define RISCV_PseudoVMANDN_MM_MF4 5638 +#define RISCV_PseudoVMANDN_MM_MF8 5639 +#define RISCV_PseudoVMAND_MM_M1 5640 +#define RISCV_PseudoVMAND_MM_M2 5641 +#define RISCV_PseudoVMAND_MM_M4 5642 +#define RISCV_PseudoVMAND_MM_M8 5643 +#define RISCV_PseudoVMAND_MM_MF2 5644 +#define RISCV_PseudoVMAND_MM_MF4 5645 +#define RISCV_PseudoVMAND_MM_MF8 5646 +#define RISCV_PseudoVMAXU_VV_M1 5647 +#define RISCV_PseudoVMAXU_VV_M1_MASK 5648 +#define RISCV_PseudoVMAXU_VV_M2 5649 +#define RISCV_PseudoVMAXU_VV_M2_MASK 5650 +#define RISCV_PseudoVMAXU_VV_M4 5651 +#define RISCV_PseudoVMAXU_VV_M4_MASK 5652 +#define RISCV_PseudoVMAXU_VV_M8 5653 +#define RISCV_PseudoVMAXU_VV_M8_MASK 5654 +#define RISCV_PseudoVMAXU_VV_MF2 5655 +#define RISCV_PseudoVMAXU_VV_MF2_MASK 5656 +#define RISCV_PseudoVMAXU_VV_MF4 5657 +#define RISCV_PseudoVMAXU_VV_MF4_MASK 5658 +#define RISCV_PseudoVMAXU_VV_MF8 5659 +#define RISCV_PseudoVMAXU_VV_MF8_MASK 5660 +#define RISCV_PseudoVMAXU_VX_M1 5661 +#define RISCV_PseudoVMAXU_VX_M1_MASK 5662 +#define RISCV_PseudoVMAXU_VX_M2 5663 +#define RISCV_PseudoVMAXU_VX_M2_MASK 5664 +#define RISCV_PseudoVMAXU_VX_M4 5665 +#define RISCV_PseudoVMAXU_VX_M4_MASK 5666 +#define RISCV_PseudoVMAXU_VX_M8 5667 +#define RISCV_PseudoVMAXU_VX_M8_MASK 5668 +#define RISCV_PseudoVMAXU_VX_MF2 5669 +#define RISCV_PseudoVMAXU_VX_MF2_MASK 5670 +#define RISCV_PseudoVMAXU_VX_MF4 5671 +#define RISCV_PseudoVMAXU_VX_MF4_MASK 5672 +#define RISCV_PseudoVMAXU_VX_MF8 5673 +#define RISCV_PseudoVMAXU_VX_MF8_MASK 5674 +#define RISCV_PseudoVMAX_VV_M1 5675 +#define RISCV_PseudoVMAX_VV_M1_MASK 5676 +#define RISCV_PseudoVMAX_VV_M2 5677 +#define RISCV_PseudoVMAX_VV_M2_MASK 5678 +#define RISCV_PseudoVMAX_VV_M4 5679 +#define RISCV_PseudoVMAX_VV_M4_MASK 5680 +#define RISCV_PseudoVMAX_VV_M8 5681 +#define RISCV_PseudoVMAX_VV_M8_MASK 5682 +#define RISCV_PseudoVMAX_VV_MF2 5683 +#define RISCV_PseudoVMAX_VV_MF2_MASK 5684 +#define RISCV_PseudoVMAX_VV_MF4 5685 +#define RISCV_PseudoVMAX_VV_MF4_MASK 5686 +#define RISCV_PseudoVMAX_VV_MF8 5687 +#define RISCV_PseudoVMAX_VV_MF8_MASK 5688 +#define RISCV_PseudoVMAX_VX_M1 5689 +#define RISCV_PseudoVMAX_VX_M1_MASK 5690 +#define RISCV_PseudoVMAX_VX_M2 5691 +#define RISCV_PseudoVMAX_VX_M2_MASK 5692 +#define RISCV_PseudoVMAX_VX_M4 5693 +#define RISCV_PseudoVMAX_VX_M4_MASK 5694 +#define RISCV_PseudoVMAX_VX_M8 5695 +#define RISCV_PseudoVMAX_VX_M8_MASK 5696 +#define RISCV_PseudoVMAX_VX_MF2 5697 +#define RISCV_PseudoVMAX_VX_MF2_MASK 5698 +#define RISCV_PseudoVMAX_VX_MF4 5699 +#define RISCV_PseudoVMAX_VX_MF4_MASK 5700 +#define RISCV_PseudoVMAX_VX_MF8 5701 +#define RISCV_PseudoVMAX_VX_MF8_MASK 5702 +#define RISCV_PseudoVMCLR_M_B1 5703 +#define RISCV_PseudoVMCLR_M_B16 5704 +#define RISCV_PseudoVMCLR_M_B2 5705 +#define RISCV_PseudoVMCLR_M_B32 5706 +#define RISCV_PseudoVMCLR_M_B4 5707 +#define RISCV_PseudoVMCLR_M_B64 5708 +#define RISCV_PseudoVMCLR_M_B8 5709 +#define RISCV_PseudoVMERGE_VIM_M1 5710 +#define RISCV_PseudoVMERGE_VIM_M2 5711 +#define RISCV_PseudoVMERGE_VIM_M4 5712 +#define RISCV_PseudoVMERGE_VIM_M8 5713 +#define RISCV_PseudoVMERGE_VIM_MF2 5714 +#define RISCV_PseudoVMERGE_VIM_MF4 5715 +#define RISCV_PseudoVMERGE_VIM_MF8 5716 +#define RISCV_PseudoVMERGE_VVM_M1 5717 +#define RISCV_PseudoVMERGE_VVM_M2 5718 +#define RISCV_PseudoVMERGE_VVM_M4 5719 +#define RISCV_PseudoVMERGE_VVM_M8 5720 +#define RISCV_PseudoVMERGE_VVM_MF2 5721 +#define RISCV_PseudoVMERGE_VVM_MF4 5722 +#define RISCV_PseudoVMERGE_VVM_MF8 5723 +#define RISCV_PseudoVMERGE_VXM_M1 5724 +#define RISCV_PseudoVMERGE_VXM_M2 5725 +#define RISCV_PseudoVMERGE_VXM_M4 5726 +#define RISCV_PseudoVMERGE_VXM_M8 5727 +#define RISCV_PseudoVMERGE_VXM_MF2 5728 +#define RISCV_PseudoVMERGE_VXM_MF4 5729 +#define RISCV_PseudoVMERGE_VXM_MF8 5730 +#define RISCV_PseudoVMFEQ_VF16_M1 5731 +#define RISCV_PseudoVMFEQ_VF16_M1_MASK 5732 +#define RISCV_PseudoVMFEQ_VF16_M2 5733 +#define RISCV_PseudoVMFEQ_VF16_M2_MASK 5734 +#define RISCV_PseudoVMFEQ_VF16_M4 5735 +#define RISCV_PseudoVMFEQ_VF16_M4_MASK 5736 +#define RISCV_PseudoVMFEQ_VF16_M8 5737 +#define RISCV_PseudoVMFEQ_VF16_M8_MASK 5738 +#define RISCV_PseudoVMFEQ_VF16_MF2 5739 +#define RISCV_PseudoVMFEQ_VF16_MF2_MASK 5740 +#define RISCV_PseudoVMFEQ_VF16_MF4 5741 +#define RISCV_PseudoVMFEQ_VF16_MF4_MASK 5742 +#define RISCV_PseudoVMFEQ_VF16_MF8 5743 +#define RISCV_PseudoVMFEQ_VF16_MF8_MASK 5744 +#define RISCV_PseudoVMFEQ_VF32_M1 5745 +#define RISCV_PseudoVMFEQ_VF32_M1_MASK 5746 +#define RISCV_PseudoVMFEQ_VF32_M2 5747 +#define RISCV_PseudoVMFEQ_VF32_M2_MASK 5748 +#define RISCV_PseudoVMFEQ_VF32_M4 5749 +#define RISCV_PseudoVMFEQ_VF32_M4_MASK 5750 +#define RISCV_PseudoVMFEQ_VF32_M8 5751 +#define RISCV_PseudoVMFEQ_VF32_M8_MASK 5752 +#define RISCV_PseudoVMFEQ_VF32_MF2 5753 +#define RISCV_PseudoVMFEQ_VF32_MF2_MASK 5754 +#define RISCV_PseudoVMFEQ_VF32_MF4 5755 +#define RISCV_PseudoVMFEQ_VF32_MF4_MASK 5756 +#define RISCV_PseudoVMFEQ_VF32_MF8 5757 +#define RISCV_PseudoVMFEQ_VF32_MF8_MASK 5758 +#define RISCV_PseudoVMFEQ_VF64_M1 5759 +#define RISCV_PseudoVMFEQ_VF64_M1_MASK 5760 +#define RISCV_PseudoVMFEQ_VF64_M2 5761 +#define RISCV_PseudoVMFEQ_VF64_M2_MASK 5762 +#define RISCV_PseudoVMFEQ_VF64_M4 5763 +#define RISCV_PseudoVMFEQ_VF64_M4_MASK 5764 +#define RISCV_PseudoVMFEQ_VF64_M8 5765 +#define RISCV_PseudoVMFEQ_VF64_M8_MASK 5766 +#define RISCV_PseudoVMFEQ_VF64_MF2 5767 +#define RISCV_PseudoVMFEQ_VF64_MF2_MASK 5768 +#define RISCV_PseudoVMFEQ_VF64_MF4 5769 +#define RISCV_PseudoVMFEQ_VF64_MF4_MASK 5770 +#define RISCV_PseudoVMFEQ_VF64_MF8 5771 +#define RISCV_PseudoVMFEQ_VF64_MF8_MASK 5772 +#define RISCV_PseudoVMFEQ_VV_M1 5773 +#define RISCV_PseudoVMFEQ_VV_M1_MASK 5774 +#define RISCV_PseudoVMFEQ_VV_M2 5775 +#define RISCV_PseudoVMFEQ_VV_M2_MASK 5776 +#define RISCV_PseudoVMFEQ_VV_M4 5777 +#define RISCV_PseudoVMFEQ_VV_M4_MASK 5778 +#define RISCV_PseudoVMFEQ_VV_M8 5779 +#define RISCV_PseudoVMFEQ_VV_M8_MASK 5780 +#define RISCV_PseudoVMFEQ_VV_MF2 5781 +#define RISCV_PseudoVMFEQ_VV_MF2_MASK 5782 +#define RISCV_PseudoVMFEQ_VV_MF4 5783 +#define RISCV_PseudoVMFEQ_VV_MF4_MASK 5784 +#define RISCV_PseudoVMFEQ_VV_MF8 5785 +#define RISCV_PseudoVMFEQ_VV_MF8_MASK 5786 +#define RISCV_PseudoVMFGE_VF16_M1 5787 +#define RISCV_PseudoVMFGE_VF16_M1_MASK 5788 +#define RISCV_PseudoVMFGE_VF16_M2 5789 +#define RISCV_PseudoVMFGE_VF16_M2_MASK 5790 +#define RISCV_PseudoVMFGE_VF16_M4 5791 +#define RISCV_PseudoVMFGE_VF16_M4_MASK 5792 +#define RISCV_PseudoVMFGE_VF16_M8 5793 +#define RISCV_PseudoVMFGE_VF16_M8_MASK 5794 +#define RISCV_PseudoVMFGE_VF16_MF2 5795 +#define RISCV_PseudoVMFGE_VF16_MF2_MASK 5796 +#define RISCV_PseudoVMFGE_VF16_MF4 5797 +#define RISCV_PseudoVMFGE_VF16_MF4_MASK 5798 +#define RISCV_PseudoVMFGE_VF16_MF8 5799 +#define RISCV_PseudoVMFGE_VF16_MF8_MASK 5800 +#define RISCV_PseudoVMFGE_VF32_M1 5801 +#define RISCV_PseudoVMFGE_VF32_M1_MASK 5802 +#define RISCV_PseudoVMFGE_VF32_M2 5803 +#define RISCV_PseudoVMFGE_VF32_M2_MASK 5804 +#define RISCV_PseudoVMFGE_VF32_M4 5805 +#define RISCV_PseudoVMFGE_VF32_M4_MASK 5806 +#define RISCV_PseudoVMFGE_VF32_M8 5807 +#define RISCV_PseudoVMFGE_VF32_M8_MASK 5808 +#define RISCV_PseudoVMFGE_VF32_MF2 5809 +#define RISCV_PseudoVMFGE_VF32_MF2_MASK 5810 +#define RISCV_PseudoVMFGE_VF32_MF4 5811 +#define RISCV_PseudoVMFGE_VF32_MF4_MASK 5812 +#define RISCV_PseudoVMFGE_VF32_MF8 5813 +#define RISCV_PseudoVMFGE_VF32_MF8_MASK 5814 +#define RISCV_PseudoVMFGE_VF64_M1 5815 +#define RISCV_PseudoVMFGE_VF64_M1_MASK 5816 +#define RISCV_PseudoVMFGE_VF64_M2 5817 +#define RISCV_PseudoVMFGE_VF64_M2_MASK 5818 +#define RISCV_PseudoVMFGE_VF64_M4 5819 +#define RISCV_PseudoVMFGE_VF64_M4_MASK 5820 +#define RISCV_PseudoVMFGE_VF64_M8 5821 +#define RISCV_PseudoVMFGE_VF64_M8_MASK 5822 +#define RISCV_PseudoVMFGE_VF64_MF2 5823 +#define RISCV_PseudoVMFGE_VF64_MF2_MASK 5824 +#define RISCV_PseudoVMFGE_VF64_MF4 5825 +#define RISCV_PseudoVMFGE_VF64_MF4_MASK 5826 +#define RISCV_PseudoVMFGE_VF64_MF8 5827 +#define RISCV_PseudoVMFGE_VF64_MF8_MASK 5828 +#define RISCV_PseudoVMFGT_VF16_M1 5829 +#define RISCV_PseudoVMFGT_VF16_M1_MASK 5830 +#define RISCV_PseudoVMFGT_VF16_M2 5831 +#define RISCV_PseudoVMFGT_VF16_M2_MASK 5832 +#define RISCV_PseudoVMFGT_VF16_M4 5833 +#define RISCV_PseudoVMFGT_VF16_M4_MASK 5834 +#define RISCV_PseudoVMFGT_VF16_M8 5835 +#define RISCV_PseudoVMFGT_VF16_M8_MASK 5836 +#define RISCV_PseudoVMFGT_VF16_MF2 5837 +#define RISCV_PseudoVMFGT_VF16_MF2_MASK 5838 +#define RISCV_PseudoVMFGT_VF16_MF4 5839 +#define RISCV_PseudoVMFGT_VF16_MF4_MASK 5840 +#define RISCV_PseudoVMFGT_VF16_MF8 5841 +#define RISCV_PseudoVMFGT_VF16_MF8_MASK 5842 +#define RISCV_PseudoVMFGT_VF32_M1 5843 +#define RISCV_PseudoVMFGT_VF32_M1_MASK 5844 +#define RISCV_PseudoVMFGT_VF32_M2 5845 +#define RISCV_PseudoVMFGT_VF32_M2_MASK 5846 +#define RISCV_PseudoVMFGT_VF32_M4 5847 +#define RISCV_PseudoVMFGT_VF32_M4_MASK 5848 +#define RISCV_PseudoVMFGT_VF32_M8 5849 +#define RISCV_PseudoVMFGT_VF32_M8_MASK 5850 +#define RISCV_PseudoVMFGT_VF32_MF2 5851 +#define RISCV_PseudoVMFGT_VF32_MF2_MASK 5852 +#define RISCV_PseudoVMFGT_VF32_MF4 5853 +#define RISCV_PseudoVMFGT_VF32_MF4_MASK 5854 +#define RISCV_PseudoVMFGT_VF32_MF8 5855 +#define RISCV_PseudoVMFGT_VF32_MF8_MASK 5856 +#define RISCV_PseudoVMFGT_VF64_M1 5857 +#define RISCV_PseudoVMFGT_VF64_M1_MASK 5858 +#define RISCV_PseudoVMFGT_VF64_M2 5859 +#define RISCV_PseudoVMFGT_VF64_M2_MASK 5860 +#define RISCV_PseudoVMFGT_VF64_M4 5861 +#define RISCV_PseudoVMFGT_VF64_M4_MASK 5862 +#define RISCV_PseudoVMFGT_VF64_M8 5863 +#define RISCV_PseudoVMFGT_VF64_M8_MASK 5864 +#define RISCV_PseudoVMFGT_VF64_MF2 5865 +#define RISCV_PseudoVMFGT_VF64_MF2_MASK 5866 +#define RISCV_PseudoVMFGT_VF64_MF4 5867 +#define RISCV_PseudoVMFGT_VF64_MF4_MASK 5868 +#define RISCV_PseudoVMFGT_VF64_MF8 5869 +#define RISCV_PseudoVMFGT_VF64_MF8_MASK 5870 +#define RISCV_PseudoVMFLE_VF16_M1 5871 +#define RISCV_PseudoVMFLE_VF16_M1_MASK 5872 +#define RISCV_PseudoVMFLE_VF16_M2 5873 +#define RISCV_PseudoVMFLE_VF16_M2_MASK 5874 +#define RISCV_PseudoVMFLE_VF16_M4 5875 +#define RISCV_PseudoVMFLE_VF16_M4_MASK 5876 +#define RISCV_PseudoVMFLE_VF16_M8 5877 +#define RISCV_PseudoVMFLE_VF16_M8_MASK 5878 +#define RISCV_PseudoVMFLE_VF16_MF2 5879 +#define RISCV_PseudoVMFLE_VF16_MF2_MASK 5880 +#define RISCV_PseudoVMFLE_VF16_MF4 5881 +#define RISCV_PseudoVMFLE_VF16_MF4_MASK 5882 +#define RISCV_PseudoVMFLE_VF16_MF8 5883 +#define RISCV_PseudoVMFLE_VF16_MF8_MASK 5884 +#define RISCV_PseudoVMFLE_VF32_M1 5885 +#define RISCV_PseudoVMFLE_VF32_M1_MASK 5886 +#define RISCV_PseudoVMFLE_VF32_M2 5887 +#define RISCV_PseudoVMFLE_VF32_M2_MASK 5888 +#define RISCV_PseudoVMFLE_VF32_M4 5889 +#define RISCV_PseudoVMFLE_VF32_M4_MASK 5890 +#define RISCV_PseudoVMFLE_VF32_M8 5891 +#define RISCV_PseudoVMFLE_VF32_M8_MASK 5892 +#define RISCV_PseudoVMFLE_VF32_MF2 5893 +#define RISCV_PseudoVMFLE_VF32_MF2_MASK 5894 +#define RISCV_PseudoVMFLE_VF32_MF4 5895 +#define RISCV_PseudoVMFLE_VF32_MF4_MASK 5896 +#define RISCV_PseudoVMFLE_VF32_MF8 5897 +#define RISCV_PseudoVMFLE_VF32_MF8_MASK 5898 +#define RISCV_PseudoVMFLE_VF64_M1 5899 +#define RISCV_PseudoVMFLE_VF64_M1_MASK 5900 +#define RISCV_PseudoVMFLE_VF64_M2 5901 +#define RISCV_PseudoVMFLE_VF64_M2_MASK 5902 +#define RISCV_PseudoVMFLE_VF64_M4 5903 +#define RISCV_PseudoVMFLE_VF64_M4_MASK 5904 +#define RISCV_PseudoVMFLE_VF64_M8 5905 +#define RISCV_PseudoVMFLE_VF64_M8_MASK 5906 +#define RISCV_PseudoVMFLE_VF64_MF2 5907 +#define RISCV_PseudoVMFLE_VF64_MF2_MASK 5908 +#define RISCV_PseudoVMFLE_VF64_MF4 5909 +#define RISCV_PseudoVMFLE_VF64_MF4_MASK 5910 +#define RISCV_PseudoVMFLE_VF64_MF8 5911 +#define RISCV_PseudoVMFLE_VF64_MF8_MASK 5912 +#define RISCV_PseudoVMFLE_VV_M1 5913 +#define RISCV_PseudoVMFLE_VV_M1_MASK 5914 +#define RISCV_PseudoVMFLE_VV_M2 5915 +#define RISCV_PseudoVMFLE_VV_M2_MASK 5916 +#define RISCV_PseudoVMFLE_VV_M4 5917 +#define RISCV_PseudoVMFLE_VV_M4_MASK 5918 +#define RISCV_PseudoVMFLE_VV_M8 5919 +#define RISCV_PseudoVMFLE_VV_M8_MASK 5920 +#define RISCV_PseudoVMFLE_VV_MF2 5921 +#define RISCV_PseudoVMFLE_VV_MF2_MASK 5922 +#define RISCV_PseudoVMFLE_VV_MF4 5923 +#define RISCV_PseudoVMFLE_VV_MF4_MASK 5924 +#define RISCV_PseudoVMFLE_VV_MF8 5925 +#define RISCV_PseudoVMFLE_VV_MF8_MASK 5926 +#define RISCV_PseudoVMFLT_VF16_M1 5927 +#define RISCV_PseudoVMFLT_VF16_M1_MASK 5928 +#define RISCV_PseudoVMFLT_VF16_M2 5929 +#define RISCV_PseudoVMFLT_VF16_M2_MASK 5930 +#define RISCV_PseudoVMFLT_VF16_M4 5931 +#define RISCV_PseudoVMFLT_VF16_M4_MASK 5932 +#define RISCV_PseudoVMFLT_VF16_M8 5933 +#define RISCV_PseudoVMFLT_VF16_M8_MASK 5934 +#define RISCV_PseudoVMFLT_VF16_MF2 5935 +#define RISCV_PseudoVMFLT_VF16_MF2_MASK 5936 +#define RISCV_PseudoVMFLT_VF16_MF4 5937 +#define RISCV_PseudoVMFLT_VF16_MF4_MASK 5938 +#define RISCV_PseudoVMFLT_VF16_MF8 5939 +#define RISCV_PseudoVMFLT_VF16_MF8_MASK 5940 +#define RISCV_PseudoVMFLT_VF32_M1 5941 +#define RISCV_PseudoVMFLT_VF32_M1_MASK 5942 +#define RISCV_PseudoVMFLT_VF32_M2 5943 +#define RISCV_PseudoVMFLT_VF32_M2_MASK 5944 +#define RISCV_PseudoVMFLT_VF32_M4 5945 +#define RISCV_PseudoVMFLT_VF32_M4_MASK 5946 +#define RISCV_PseudoVMFLT_VF32_M8 5947 +#define RISCV_PseudoVMFLT_VF32_M8_MASK 5948 +#define RISCV_PseudoVMFLT_VF32_MF2 5949 +#define RISCV_PseudoVMFLT_VF32_MF2_MASK 5950 +#define RISCV_PseudoVMFLT_VF32_MF4 5951 +#define RISCV_PseudoVMFLT_VF32_MF4_MASK 5952 +#define RISCV_PseudoVMFLT_VF32_MF8 5953 +#define RISCV_PseudoVMFLT_VF32_MF8_MASK 5954 +#define RISCV_PseudoVMFLT_VF64_M1 5955 +#define RISCV_PseudoVMFLT_VF64_M1_MASK 5956 +#define RISCV_PseudoVMFLT_VF64_M2 5957 +#define RISCV_PseudoVMFLT_VF64_M2_MASK 5958 +#define RISCV_PseudoVMFLT_VF64_M4 5959 +#define RISCV_PseudoVMFLT_VF64_M4_MASK 5960 +#define RISCV_PseudoVMFLT_VF64_M8 5961 +#define RISCV_PseudoVMFLT_VF64_M8_MASK 5962 +#define RISCV_PseudoVMFLT_VF64_MF2 5963 +#define RISCV_PseudoVMFLT_VF64_MF2_MASK 5964 +#define RISCV_PseudoVMFLT_VF64_MF4 5965 +#define RISCV_PseudoVMFLT_VF64_MF4_MASK 5966 +#define RISCV_PseudoVMFLT_VF64_MF8 5967 +#define RISCV_PseudoVMFLT_VF64_MF8_MASK 5968 +#define RISCV_PseudoVMFLT_VV_M1 5969 +#define RISCV_PseudoVMFLT_VV_M1_MASK 5970 +#define RISCV_PseudoVMFLT_VV_M2 5971 +#define RISCV_PseudoVMFLT_VV_M2_MASK 5972 +#define RISCV_PseudoVMFLT_VV_M4 5973 +#define RISCV_PseudoVMFLT_VV_M4_MASK 5974 +#define RISCV_PseudoVMFLT_VV_M8 5975 +#define RISCV_PseudoVMFLT_VV_M8_MASK 5976 +#define RISCV_PseudoVMFLT_VV_MF2 5977 +#define RISCV_PseudoVMFLT_VV_MF2_MASK 5978 +#define RISCV_PseudoVMFLT_VV_MF4 5979 +#define RISCV_PseudoVMFLT_VV_MF4_MASK 5980 +#define RISCV_PseudoVMFLT_VV_MF8 5981 +#define RISCV_PseudoVMFLT_VV_MF8_MASK 5982 +#define RISCV_PseudoVMFNE_VF16_M1 5983 +#define RISCV_PseudoVMFNE_VF16_M1_MASK 5984 +#define RISCV_PseudoVMFNE_VF16_M2 5985 +#define RISCV_PseudoVMFNE_VF16_M2_MASK 5986 +#define RISCV_PseudoVMFNE_VF16_M4 5987 +#define RISCV_PseudoVMFNE_VF16_M4_MASK 5988 +#define RISCV_PseudoVMFNE_VF16_M8 5989 +#define RISCV_PseudoVMFNE_VF16_M8_MASK 5990 +#define RISCV_PseudoVMFNE_VF16_MF2 5991 +#define RISCV_PseudoVMFNE_VF16_MF2_MASK 5992 +#define RISCV_PseudoVMFNE_VF16_MF4 5993 +#define RISCV_PseudoVMFNE_VF16_MF4_MASK 5994 +#define RISCV_PseudoVMFNE_VF16_MF8 5995 +#define RISCV_PseudoVMFNE_VF16_MF8_MASK 5996 +#define RISCV_PseudoVMFNE_VF32_M1 5997 +#define RISCV_PseudoVMFNE_VF32_M1_MASK 5998 +#define RISCV_PseudoVMFNE_VF32_M2 5999 +#define RISCV_PseudoVMFNE_VF32_M2_MASK 6000 +#define RISCV_PseudoVMFNE_VF32_M4 6001 +#define RISCV_PseudoVMFNE_VF32_M4_MASK 6002 +#define RISCV_PseudoVMFNE_VF32_M8 6003 +#define RISCV_PseudoVMFNE_VF32_M8_MASK 6004 +#define RISCV_PseudoVMFNE_VF32_MF2 6005 +#define RISCV_PseudoVMFNE_VF32_MF2_MASK 6006 +#define RISCV_PseudoVMFNE_VF32_MF4 6007 +#define RISCV_PseudoVMFNE_VF32_MF4_MASK 6008 +#define RISCV_PseudoVMFNE_VF32_MF8 6009 +#define RISCV_PseudoVMFNE_VF32_MF8_MASK 6010 +#define RISCV_PseudoVMFNE_VF64_M1 6011 +#define RISCV_PseudoVMFNE_VF64_M1_MASK 6012 +#define RISCV_PseudoVMFNE_VF64_M2 6013 +#define RISCV_PseudoVMFNE_VF64_M2_MASK 6014 +#define RISCV_PseudoVMFNE_VF64_M4 6015 +#define RISCV_PseudoVMFNE_VF64_M4_MASK 6016 +#define RISCV_PseudoVMFNE_VF64_M8 6017 +#define RISCV_PseudoVMFNE_VF64_M8_MASK 6018 +#define RISCV_PseudoVMFNE_VF64_MF2 6019 +#define RISCV_PseudoVMFNE_VF64_MF2_MASK 6020 +#define RISCV_PseudoVMFNE_VF64_MF4 6021 +#define RISCV_PseudoVMFNE_VF64_MF4_MASK 6022 +#define RISCV_PseudoVMFNE_VF64_MF8 6023 +#define RISCV_PseudoVMFNE_VF64_MF8_MASK 6024 +#define RISCV_PseudoVMFNE_VV_M1 6025 +#define RISCV_PseudoVMFNE_VV_M1_MASK 6026 +#define RISCV_PseudoVMFNE_VV_M2 6027 +#define RISCV_PseudoVMFNE_VV_M2_MASK 6028 +#define RISCV_PseudoVMFNE_VV_M4 6029 +#define RISCV_PseudoVMFNE_VV_M4_MASK 6030 +#define RISCV_PseudoVMFNE_VV_M8 6031 +#define RISCV_PseudoVMFNE_VV_M8_MASK 6032 +#define RISCV_PseudoVMFNE_VV_MF2 6033 +#define RISCV_PseudoVMFNE_VV_MF2_MASK 6034 +#define RISCV_PseudoVMFNE_VV_MF4 6035 +#define RISCV_PseudoVMFNE_VV_MF4_MASK 6036 +#define RISCV_PseudoVMFNE_VV_MF8 6037 +#define RISCV_PseudoVMFNE_VV_MF8_MASK 6038 +#define RISCV_PseudoVMINU_VV_M1 6039 +#define RISCV_PseudoVMINU_VV_M1_MASK 6040 +#define RISCV_PseudoVMINU_VV_M2 6041 +#define RISCV_PseudoVMINU_VV_M2_MASK 6042 +#define RISCV_PseudoVMINU_VV_M4 6043 +#define RISCV_PseudoVMINU_VV_M4_MASK 6044 +#define RISCV_PseudoVMINU_VV_M8 6045 +#define RISCV_PseudoVMINU_VV_M8_MASK 6046 +#define RISCV_PseudoVMINU_VV_MF2 6047 +#define RISCV_PseudoVMINU_VV_MF2_MASK 6048 +#define RISCV_PseudoVMINU_VV_MF4 6049 +#define RISCV_PseudoVMINU_VV_MF4_MASK 6050 +#define RISCV_PseudoVMINU_VV_MF8 6051 +#define RISCV_PseudoVMINU_VV_MF8_MASK 6052 +#define RISCV_PseudoVMINU_VX_M1 6053 +#define RISCV_PseudoVMINU_VX_M1_MASK 6054 +#define RISCV_PseudoVMINU_VX_M2 6055 +#define RISCV_PseudoVMINU_VX_M2_MASK 6056 +#define RISCV_PseudoVMINU_VX_M4 6057 +#define RISCV_PseudoVMINU_VX_M4_MASK 6058 +#define RISCV_PseudoVMINU_VX_M8 6059 +#define RISCV_PseudoVMINU_VX_M8_MASK 6060 +#define RISCV_PseudoVMINU_VX_MF2 6061 +#define RISCV_PseudoVMINU_VX_MF2_MASK 6062 +#define RISCV_PseudoVMINU_VX_MF4 6063 +#define RISCV_PseudoVMINU_VX_MF4_MASK 6064 +#define RISCV_PseudoVMINU_VX_MF8 6065 +#define RISCV_PseudoVMINU_VX_MF8_MASK 6066 +#define RISCV_PseudoVMIN_VV_M1 6067 +#define RISCV_PseudoVMIN_VV_M1_MASK 6068 +#define RISCV_PseudoVMIN_VV_M2 6069 +#define RISCV_PseudoVMIN_VV_M2_MASK 6070 +#define RISCV_PseudoVMIN_VV_M4 6071 +#define RISCV_PseudoVMIN_VV_M4_MASK 6072 +#define RISCV_PseudoVMIN_VV_M8 6073 +#define RISCV_PseudoVMIN_VV_M8_MASK 6074 +#define RISCV_PseudoVMIN_VV_MF2 6075 +#define RISCV_PseudoVMIN_VV_MF2_MASK 6076 +#define RISCV_PseudoVMIN_VV_MF4 6077 +#define RISCV_PseudoVMIN_VV_MF4_MASK 6078 +#define RISCV_PseudoVMIN_VV_MF8 6079 +#define RISCV_PseudoVMIN_VV_MF8_MASK 6080 +#define RISCV_PseudoVMIN_VX_M1 6081 +#define RISCV_PseudoVMIN_VX_M1_MASK 6082 +#define RISCV_PseudoVMIN_VX_M2 6083 +#define RISCV_PseudoVMIN_VX_M2_MASK 6084 +#define RISCV_PseudoVMIN_VX_M4 6085 +#define RISCV_PseudoVMIN_VX_M4_MASK 6086 +#define RISCV_PseudoVMIN_VX_M8 6087 +#define RISCV_PseudoVMIN_VX_M8_MASK 6088 +#define RISCV_PseudoVMIN_VX_MF2 6089 +#define RISCV_PseudoVMIN_VX_MF2_MASK 6090 +#define RISCV_PseudoVMIN_VX_MF4 6091 +#define RISCV_PseudoVMIN_VX_MF4_MASK 6092 +#define RISCV_PseudoVMIN_VX_MF8 6093 +#define RISCV_PseudoVMIN_VX_MF8_MASK 6094 +#define RISCV_PseudoVMNAND_MM_M1 6095 +#define RISCV_PseudoVMNAND_MM_M2 6096 +#define RISCV_PseudoVMNAND_MM_M4 6097 +#define RISCV_PseudoVMNAND_MM_M8 6098 +#define RISCV_PseudoVMNAND_MM_MF2 6099 +#define RISCV_PseudoVMNAND_MM_MF4 6100 +#define RISCV_PseudoVMNAND_MM_MF8 6101 +#define RISCV_PseudoVMNOR_MM_M1 6102 +#define RISCV_PseudoVMNOR_MM_M2 6103 +#define RISCV_PseudoVMNOR_MM_M4 6104 +#define RISCV_PseudoVMNOR_MM_M8 6105 +#define RISCV_PseudoVMNOR_MM_MF2 6106 +#define RISCV_PseudoVMNOR_MM_MF4 6107 +#define RISCV_PseudoVMNOR_MM_MF8 6108 +#define RISCV_PseudoVMORN_MM_M1 6109 +#define RISCV_PseudoVMORN_MM_M2 6110 +#define RISCV_PseudoVMORN_MM_M4 6111 +#define RISCV_PseudoVMORN_MM_M8 6112 +#define RISCV_PseudoVMORN_MM_MF2 6113 +#define RISCV_PseudoVMORN_MM_MF4 6114 +#define RISCV_PseudoVMORN_MM_MF8 6115 +#define RISCV_PseudoVMOR_MM_M1 6116 +#define RISCV_PseudoVMOR_MM_M2 6117 +#define RISCV_PseudoVMOR_MM_M4 6118 +#define RISCV_PseudoVMOR_MM_M8 6119 +#define RISCV_PseudoVMOR_MM_MF2 6120 +#define RISCV_PseudoVMOR_MM_MF4 6121 +#define RISCV_PseudoVMOR_MM_MF8 6122 +#define RISCV_PseudoVMSBC_VVM_M1 6123 +#define RISCV_PseudoVMSBC_VVM_M2 6124 +#define RISCV_PseudoVMSBC_VVM_M4 6125 +#define RISCV_PseudoVMSBC_VVM_M8 6126 +#define RISCV_PseudoVMSBC_VVM_MF2 6127 +#define RISCV_PseudoVMSBC_VVM_MF4 6128 +#define RISCV_PseudoVMSBC_VVM_MF8 6129 +#define RISCV_PseudoVMSBC_VV_M1 6130 +#define RISCV_PseudoVMSBC_VV_M2 6131 +#define RISCV_PseudoVMSBC_VV_M4 6132 +#define RISCV_PseudoVMSBC_VV_M8 6133 +#define RISCV_PseudoVMSBC_VV_MF2 6134 +#define RISCV_PseudoVMSBC_VV_MF4 6135 +#define RISCV_PseudoVMSBC_VV_MF8 6136 +#define RISCV_PseudoVMSBC_VXM_M1 6137 +#define RISCV_PseudoVMSBC_VXM_M2 6138 +#define RISCV_PseudoVMSBC_VXM_M4 6139 +#define RISCV_PseudoVMSBC_VXM_M8 6140 +#define RISCV_PseudoVMSBC_VXM_MF2 6141 +#define RISCV_PseudoVMSBC_VXM_MF4 6142 +#define RISCV_PseudoVMSBC_VXM_MF8 6143 +#define RISCV_PseudoVMSBC_VX_M1 6144 +#define RISCV_PseudoVMSBC_VX_M2 6145 +#define RISCV_PseudoVMSBC_VX_M4 6146 +#define RISCV_PseudoVMSBC_VX_M8 6147 +#define RISCV_PseudoVMSBC_VX_MF2 6148 +#define RISCV_PseudoVMSBC_VX_MF4 6149 +#define RISCV_PseudoVMSBC_VX_MF8 6150 +#define RISCV_PseudoVMSBF_M_B1 6151 +#define RISCV_PseudoVMSBF_M_B16 6152 +#define RISCV_PseudoVMSBF_M_B16_MASK 6153 +#define RISCV_PseudoVMSBF_M_B1_MASK 6154 +#define RISCV_PseudoVMSBF_M_B2 6155 +#define RISCV_PseudoVMSBF_M_B2_MASK 6156 +#define RISCV_PseudoVMSBF_M_B32 6157 +#define RISCV_PseudoVMSBF_M_B32_MASK 6158 +#define RISCV_PseudoVMSBF_M_B4 6159 +#define RISCV_PseudoVMSBF_M_B4_MASK 6160 +#define RISCV_PseudoVMSBF_M_B64 6161 +#define RISCV_PseudoVMSBF_M_B64_MASK 6162 +#define RISCV_PseudoVMSBF_M_B8 6163 +#define RISCV_PseudoVMSBF_M_B8_MASK 6164 +#define RISCV_PseudoVMSEQ_VI_M1 6165 +#define RISCV_PseudoVMSEQ_VI_M1_MASK 6166 +#define RISCV_PseudoVMSEQ_VI_M2 6167 +#define RISCV_PseudoVMSEQ_VI_M2_MASK 6168 +#define RISCV_PseudoVMSEQ_VI_M4 6169 +#define RISCV_PseudoVMSEQ_VI_M4_MASK 6170 +#define RISCV_PseudoVMSEQ_VI_M8 6171 +#define RISCV_PseudoVMSEQ_VI_M8_MASK 6172 +#define RISCV_PseudoVMSEQ_VI_MF2 6173 +#define RISCV_PseudoVMSEQ_VI_MF2_MASK 6174 +#define RISCV_PseudoVMSEQ_VI_MF4 6175 +#define RISCV_PseudoVMSEQ_VI_MF4_MASK 6176 +#define RISCV_PseudoVMSEQ_VI_MF8 6177 +#define RISCV_PseudoVMSEQ_VI_MF8_MASK 6178 +#define RISCV_PseudoVMSEQ_VV_M1 6179 +#define RISCV_PseudoVMSEQ_VV_M1_MASK 6180 +#define RISCV_PseudoVMSEQ_VV_M2 6181 +#define RISCV_PseudoVMSEQ_VV_M2_MASK 6182 +#define RISCV_PseudoVMSEQ_VV_M4 6183 +#define RISCV_PseudoVMSEQ_VV_M4_MASK 6184 +#define RISCV_PseudoVMSEQ_VV_M8 6185 +#define RISCV_PseudoVMSEQ_VV_M8_MASK 6186 +#define RISCV_PseudoVMSEQ_VV_MF2 6187 +#define RISCV_PseudoVMSEQ_VV_MF2_MASK 6188 +#define RISCV_PseudoVMSEQ_VV_MF4 6189 +#define RISCV_PseudoVMSEQ_VV_MF4_MASK 6190 +#define RISCV_PseudoVMSEQ_VV_MF8 6191 +#define RISCV_PseudoVMSEQ_VV_MF8_MASK 6192 +#define RISCV_PseudoVMSEQ_VX_M1 6193 +#define RISCV_PseudoVMSEQ_VX_M1_MASK 6194 +#define RISCV_PseudoVMSEQ_VX_M2 6195 +#define RISCV_PseudoVMSEQ_VX_M2_MASK 6196 +#define RISCV_PseudoVMSEQ_VX_M4 6197 +#define RISCV_PseudoVMSEQ_VX_M4_MASK 6198 +#define RISCV_PseudoVMSEQ_VX_M8 6199 +#define RISCV_PseudoVMSEQ_VX_M8_MASK 6200 +#define RISCV_PseudoVMSEQ_VX_MF2 6201 +#define RISCV_PseudoVMSEQ_VX_MF2_MASK 6202 +#define RISCV_PseudoVMSEQ_VX_MF4 6203 +#define RISCV_PseudoVMSEQ_VX_MF4_MASK 6204 +#define RISCV_PseudoVMSEQ_VX_MF8 6205 +#define RISCV_PseudoVMSEQ_VX_MF8_MASK 6206 +#define RISCV_PseudoVMSET_M_B1 6207 +#define RISCV_PseudoVMSET_M_B16 6208 +#define RISCV_PseudoVMSET_M_B2 6209 +#define RISCV_PseudoVMSET_M_B32 6210 +#define RISCV_PseudoVMSET_M_B4 6211 +#define RISCV_PseudoVMSET_M_B64 6212 +#define RISCV_PseudoVMSET_M_B8 6213 +#define RISCV_PseudoVMSGEU_VI 6214 +#define RISCV_PseudoVMSGEU_VX 6215 +#define RISCV_PseudoVMSGEU_VX_M 6216 +#define RISCV_PseudoVMSGEU_VX_M_T 6217 +#define RISCV_PseudoVMSGE_VI 6218 +#define RISCV_PseudoVMSGE_VX 6219 +#define RISCV_PseudoVMSGE_VX_M 6220 +#define RISCV_PseudoVMSGE_VX_M_T 6221 +#define RISCV_PseudoVMSGTU_VI_M1 6222 +#define RISCV_PseudoVMSGTU_VI_M1_MASK 6223 +#define RISCV_PseudoVMSGTU_VI_M2 6224 +#define RISCV_PseudoVMSGTU_VI_M2_MASK 6225 +#define RISCV_PseudoVMSGTU_VI_M4 6226 +#define RISCV_PseudoVMSGTU_VI_M4_MASK 6227 +#define RISCV_PseudoVMSGTU_VI_M8 6228 +#define RISCV_PseudoVMSGTU_VI_M8_MASK 6229 +#define RISCV_PseudoVMSGTU_VI_MF2 6230 +#define RISCV_PseudoVMSGTU_VI_MF2_MASK 6231 +#define RISCV_PseudoVMSGTU_VI_MF4 6232 +#define RISCV_PseudoVMSGTU_VI_MF4_MASK 6233 +#define RISCV_PseudoVMSGTU_VI_MF8 6234 +#define RISCV_PseudoVMSGTU_VI_MF8_MASK 6235 +#define RISCV_PseudoVMSGTU_VX_M1 6236 +#define RISCV_PseudoVMSGTU_VX_M1_MASK 6237 +#define RISCV_PseudoVMSGTU_VX_M2 6238 +#define RISCV_PseudoVMSGTU_VX_M2_MASK 6239 +#define RISCV_PseudoVMSGTU_VX_M4 6240 +#define RISCV_PseudoVMSGTU_VX_M4_MASK 6241 +#define RISCV_PseudoVMSGTU_VX_M8 6242 +#define RISCV_PseudoVMSGTU_VX_M8_MASK 6243 +#define RISCV_PseudoVMSGTU_VX_MF2 6244 +#define RISCV_PseudoVMSGTU_VX_MF2_MASK 6245 +#define RISCV_PseudoVMSGTU_VX_MF4 6246 +#define RISCV_PseudoVMSGTU_VX_MF4_MASK 6247 +#define RISCV_PseudoVMSGTU_VX_MF8 6248 +#define RISCV_PseudoVMSGTU_VX_MF8_MASK 6249 +#define RISCV_PseudoVMSGT_VI_M1 6250 +#define RISCV_PseudoVMSGT_VI_M1_MASK 6251 +#define RISCV_PseudoVMSGT_VI_M2 6252 +#define RISCV_PseudoVMSGT_VI_M2_MASK 6253 +#define RISCV_PseudoVMSGT_VI_M4 6254 +#define RISCV_PseudoVMSGT_VI_M4_MASK 6255 +#define RISCV_PseudoVMSGT_VI_M8 6256 +#define RISCV_PseudoVMSGT_VI_M8_MASK 6257 +#define RISCV_PseudoVMSGT_VI_MF2 6258 +#define RISCV_PseudoVMSGT_VI_MF2_MASK 6259 +#define RISCV_PseudoVMSGT_VI_MF4 6260 +#define RISCV_PseudoVMSGT_VI_MF4_MASK 6261 +#define RISCV_PseudoVMSGT_VI_MF8 6262 +#define RISCV_PseudoVMSGT_VI_MF8_MASK 6263 +#define RISCV_PseudoVMSGT_VX_M1 6264 +#define RISCV_PseudoVMSGT_VX_M1_MASK 6265 +#define RISCV_PseudoVMSGT_VX_M2 6266 +#define RISCV_PseudoVMSGT_VX_M2_MASK 6267 +#define RISCV_PseudoVMSGT_VX_M4 6268 +#define RISCV_PseudoVMSGT_VX_M4_MASK 6269 +#define RISCV_PseudoVMSGT_VX_M8 6270 +#define RISCV_PseudoVMSGT_VX_M8_MASK 6271 +#define RISCV_PseudoVMSGT_VX_MF2 6272 +#define RISCV_PseudoVMSGT_VX_MF2_MASK 6273 +#define RISCV_PseudoVMSGT_VX_MF4 6274 +#define RISCV_PseudoVMSGT_VX_MF4_MASK 6275 +#define RISCV_PseudoVMSGT_VX_MF8 6276 +#define RISCV_PseudoVMSGT_VX_MF8_MASK 6277 +#define RISCV_PseudoVMSIF_M_B1 6278 +#define RISCV_PseudoVMSIF_M_B16 6279 +#define RISCV_PseudoVMSIF_M_B16_MASK 6280 +#define RISCV_PseudoVMSIF_M_B1_MASK 6281 +#define RISCV_PseudoVMSIF_M_B2 6282 +#define RISCV_PseudoVMSIF_M_B2_MASK 6283 +#define RISCV_PseudoVMSIF_M_B32 6284 +#define RISCV_PseudoVMSIF_M_B32_MASK 6285 +#define RISCV_PseudoVMSIF_M_B4 6286 +#define RISCV_PseudoVMSIF_M_B4_MASK 6287 +#define RISCV_PseudoVMSIF_M_B64 6288 +#define RISCV_PseudoVMSIF_M_B64_MASK 6289 +#define RISCV_PseudoVMSIF_M_B8 6290 +#define RISCV_PseudoVMSIF_M_B8_MASK 6291 +#define RISCV_PseudoVMSLEU_VI_M1 6292 +#define RISCV_PseudoVMSLEU_VI_M1_MASK 6293 +#define RISCV_PseudoVMSLEU_VI_M2 6294 +#define RISCV_PseudoVMSLEU_VI_M2_MASK 6295 +#define RISCV_PseudoVMSLEU_VI_M4 6296 +#define RISCV_PseudoVMSLEU_VI_M4_MASK 6297 +#define RISCV_PseudoVMSLEU_VI_M8 6298 +#define RISCV_PseudoVMSLEU_VI_M8_MASK 6299 +#define RISCV_PseudoVMSLEU_VI_MF2 6300 +#define RISCV_PseudoVMSLEU_VI_MF2_MASK 6301 +#define RISCV_PseudoVMSLEU_VI_MF4 6302 +#define RISCV_PseudoVMSLEU_VI_MF4_MASK 6303 +#define RISCV_PseudoVMSLEU_VI_MF8 6304 +#define RISCV_PseudoVMSLEU_VI_MF8_MASK 6305 +#define RISCV_PseudoVMSLEU_VV_M1 6306 +#define RISCV_PseudoVMSLEU_VV_M1_MASK 6307 +#define RISCV_PseudoVMSLEU_VV_M2 6308 +#define RISCV_PseudoVMSLEU_VV_M2_MASK 6309 +#define RISCV_PseudoVMSLEU_VV_M4 6310 +#define RISCV_PseudoVMSLEU_VV_M4_MASK 6311 +#define RISCV_PseudoVMSLEU_VV_M8 6312 +#define RISCV_PseudoVMSLEU_VV_M8_MASK 6313 +#define RISCV_PseudoVMSLEU_VV_MF2 6314 +#define RISCV_PseudoVMSLEU_VV_MF2_MASK 6315 +#define RISCV_PseudoVMSLEU_VV_MF4 6316 +#define RISCV_PseudoVMSLEU_VV_MF4_MASK 6317 +#define RISCV_PseudoVMSLEU_VV_MF8 6318 +#define RISCV_PseudoVMSLEU_VV_MF8_MASK 6319 +#define RISCV_PseudoVMSLEU_VX_M1 6320 +#define RISCV_PseudoVMSLEU_VX_M1_MASK 6321 +#define RISCV_PseudoVMSLEU_VX_M2 6322 +#define RISCV_PseudoVMSLEU_VX_M2_MASK 6323 +#define RISCV_PseudoVMSLEU_VX_M4 6324 +#define RISCV_PseudoVMSLEU_VX_M4_MASK 6325 +#define RISCV_PseudoVMSLEU_VX_M8 6326 +#define RISCV_PseudoVMSLEU_VX_M8_MASK 6327 +#define RISCV_PseudoVMSLEU_VX_MF2 6328 +#define RISCV_PseudoVMSLEU_VX_MF2_MASK 6329 +#define RISCV_PseudoVMSLEU_VX_MF4 6330 +#define RISCV_PseudoVMSLEU_VX_MF4_MASK 6331 +#define RISCV_PseudoVMSLEU_VX_MF8 6332 +#define RISCV_PseudoVMSLEU_VX_MF8_MASK 6333 +#define RISCV_PseudoVMSLE_VI_M1 6334 +#define RISCV_PseudoVMSLE_VI_M1_MASK 6335 +#define RISCV_PseudoVMSLE_VI_M2 6336 +#define RISCV_PseudoVMSLE_VI_M2_MASK 6337 +#define RISCV_PseudoVMSLE_VI_M4 6338 +#define RISCV_PseudoVMSLE_VI_M4_MASK 6339 +#define RISCV_PseudoVMSLE_VI_M8 6340 +#define RISCV_PseudoVMSLE_VI_M8_MASK 6341 +#define RISCV_PseudoVMSLE_VI_MF2 6342 +#define RISCV_PseudoVMSLE_VI_MF2_MASK 6343 +#define RISCV_PseudoVMSLE_VI_MF4 6344 +#define RISCV_PseudoVMSLE_VI_MF4_MASK 6345 +#define RISCV_PseudoVMSLE_VI_MF8 6346 +#define RISCV_PseudoVMSLE_VI_MF8_MASK 6347 +#define RISCV_PseudoVMSLE_VV_M1 6348 +#define RISCV_PseudoVMSLE_VV_M1_MASK 6349 +#define RISCV_PseudoVMSLE_VV_M2 6350 +#define RISCV_PseudoVMSLE_VV_M2_MASK 6351 +#define RISCV_PseudoVMSLE_VV_M4 6352 +#define RISCV_PseudoVMSLE_VV_M4_MASK 6353 +#define RISCV_PseudoVMSLE_VV_M8 6354 +#define RISCV_PseudoVMSLE_VV_M8_MASK 6355 +#define RISCV_PseudoVMSLE_VV_MF2 6356 +#define RISCV_PseudoVMSLE_VV_MF2_MASK 6357 +#define RISCV_PseudoVMSLE_VV_MF4 6358 +#define RISCV_PseudoVMSLE_VV_MF4_MASK 6359 +#define RISCV_PseudoVMSLE_VV_MF8 6360 +#define RISCV_PseudoVMSLE_VV_MF8_MASK 6361 +#define RISCV_PseudoVMSLE_VX_M1 6362 +#define RISCV_PseudoVMSLE_VX_M1_MASK 6363 +#define RISCV_PseudoVMSLE_VX_M2 6364 +#define RISCV_PseudoVMSLE_VX_M2_MASK 6365 +#define RISCV_PseudoVMSLE_VX_M4 6366 +#define RISCV_PseudoVMSLE_VX_M4_MASK 6367 +#define RISCV_PseudoVMSLE_VX_M8 6368 +#define RISCV_PseudoVMSLE_VX_M8_MASK 6369 +#define RISCV_PseudoVMSLE_VX_MF2 6370 +#define RISCV_PseudoVMSLE_VX_MF2_MASK 6371 +#define RISCV_PseudoVMSLE_VX_MF4 6372 +#define RISCV_PseudoVMSLE_VX_MF4_MASK 6373 +#define RISCV_PseudoVMSLE_VX_MF8 6374 +#define RISCV_PseudoVMSLE_VX_MF8_MASK 6375 +#define RISCV_PseudoVMSLTU_VI 6376 +#define RISCV_PseudoVMSLTU_VV_M1 6377 +#define RISCV_PseudoVMSLTU_VV_M1_MASK 6378 +#define RISCV_PseudoVMSLTU_VV_M2 6379 +#define RISCV_PseudoVMSLTU_VV_M2_MASK 6380 +#define RISCV_PseudoVMSLTU_VV_M4 6381 +#define RISCV_PseudoVMSLTU_VV_M4_MASK 6382 +#define RISCV_PseudoVMSLTU_VV_M8 6383 +#define RISCV_PseudoVMSLTU_VV_M8_MASK 6384 +#define RISCV_PseudoVMSLTU_VV_MF2 6385 +#define RISCV_PseudoVMSLTU_VV_MF2_MASK 6386 +#define RISCV_PseudoVMSLTU_VV_MF4 6387 +#define RISCV_PseudoVMSLTU_VV_MF4_MASK 6388 +#define RISCV_PseudoVMSLTU_VV_MF8 6389 +#define RISCV_PseudoVMSLTU_VV_MF8_MASK 6390 +#define RISCV_PseudoVMSLTU_VX_M1 6391 +#define RISCV_PseudoVMSLTU_VX_M1_MASK 6392 +#define RISCV_PseudoVMSLTU_VX_M2 6393 +#define RISCV_PseudoVMSLTU_VX_M2_MASK 6394 +#define RISCV_PseudoVMSLTU_VX_M4 6395 +#define RISCV_PseudoVMSLTU_VX_M4_MASK 6396 +#define RISCV_PseudoVMSLTU_VX_M8 6397 +#define RISCV_PseudoVMSLTU_VX_M8_MASK 6398 +#define RISCV_PseudoVMSLTU_VX_MF2 6399 +#define RISCV_PseudoVMSLTU_VX_MF2_MASK 6400 +#define RISCV_PseudoVMSLTU_VX_MF4 6401 +#define RISCV_PseudoVMSLTU_VX_MF4_MASK 6402 +#define RISCV_PseudoVMSLTU_VX_MF8 6403 +#define RISCV_PseudoVMSLTU_VX_MF8_MASK 6404 +#define RISCV_PseudoVMSLT_VI 6405 +#define RISCV_PseudoVMSLT_VV_M1 6406 +#define RISCV_PseudoVMSLT_VV_M1_MASK 6407 +#define RISCV_PseudoVMSLT_VV_M2 6408 +#define RISCV_PseudoVMSLT_VV_M2_MASK 6409 +#define RISCV_PseudoVMSLT_VV_M4 6410 +#define RISCV_PseudoVMSLT_VV_M4_MASK 6411 +#define RISCV_PseudoVMSLT_VV_M8 6412 +#define RISCV_PseudoVMSLT_VV_M8_MASK 6413 +#define RISCV_PseudoVMSLT_VV_MF2 6414 +#define RISCV_PseudoVMSLT_VV_MF2_MASK 6415 +#define RISCV_PseudoVMSLT_VV_MF4 6416 +#define RISCV_PseudoVMSLT_VV_MF4_MASK 6417 +#define RISCV_PseudoVMSLT_VV_MF8 6418 +#define RISCV_PseudoVMSLT_VV_MF8_MASK 6419 +#define RISCV_PseudoVMSLT_VX_M1 6420 +#define RISCV_PseudoVMSLT_VX_M1_MASK 6421 +#define RISCV_PseudoVMSLT_VX_M2 6422 +#define RISCV_PseudoVMSLT_VX_M2_MASK 6423 +#define RISCV_PseudoVMSLT_VX_M4 6424 +#define RISCV_PseudoVMSLT_VX_M4_MASK 6425 +#define RISCV_PseudoVMSLT_VX_M8 6426 +#define RISCV_PseudoVMSLT_VX_M8_MASK 6427 +#define RISCV_PseudoVMSLT_VX_MF2 6428 +#define RISCV_PseudoVMSLT_VX_MF2_MASK 6429 +#define RISCV_PseudoVMSLT_VX_MF4 6430 +#define RISCV_PseudoVMSLT_VX_MF4_MASK 6431 +#define RISCV_PseudoVMSLT_VX_MF8 6432 +#define RISCV_PseudoVMSLT_VX_MF8_MASK 6433 +#define RISCV_PseudoVMSNE_VI_M1 6434 +#define RISCV_PseudoVMSNE_VI_M1_MASK 6435 +#define RISCV_PseudoVMSNE_VI_M2 6436 +#define RISCV_PseudoVMSNE_VI_M2_MASK 6437 +#define RISCV_PseudoVMSNE_VI_M4 6438 +#define RISCV_PseudoVMSNE_VI_M4_MASK 6439 +#define RISCV_PseudoVMSNE_VI_M8 6440 +#define RISCV_PseudoVMSNE_VI_M8_MASK 6441 +#define RISCV_PseudoVMSNE_VI_MF2 6442 +#define RISCV_PseudoVMSNE_VI_MF2_MASK 6443 +#define RISCV_PseudoVMSNE_VI_MF4 6444 +#define RISCV_PseudoVMSNE_VI_MF4_MASK 6445 +#define RISCV_PseudoVMSNE_VI_MF8 6446 +#define RISCV_PseudoVMSNE_VI_MF8_MASK 6447 +#define RISCV_PseudoVMSNE_VV_M1 6448 +#define RISCV_PseudoVMSNE_VV_M1_MASK 6449 +#define RISCV_PseudoVMSNE_VV_M2 6450 +#define RISCV_PseudoVMSNE_VV_M2_MASK 6451 +#define RISCV_PseudoVMSNE_VV_M4 6452 +#define RISCV_PseudoVMSNE_VV_M4_MASK 6453 +#define RISCV_PseudoVMSNE_VV_M8 6454 +#define RISCV_PseudoVMSNE_VV_M8_MASK 6455 +#define RISCV_PseudoVMSNE_VV_MF2 6456 +#define RISCV_PseudoVMSNE_VV_MF2_MASK 6457 +#define RISCV_PseudoVMSNE_VV_MF4 6458 +#define RISCV_PseudoVMSNE_VV_MF4_MASK 6459 +#define RISCV_PseudoVMSNE_VV_MF8 6460 +#define RISCV_PseudoVMSNE_VV_MF8_MASK 6461 +#define RISCV_PseudoVMSNE_VX_M1 6462 +#define RISCV_PseudoVMSNE_VX_M1_MASK 6463 +#define RISCV_PseudoVMSNE_VX_M2 6464 +#define RISCV_PseudoVMSNE_VX_M2_MASK 6465 +#define RISCV_PseudoVMSNE_VX_M4 6466 +#define RISCV_PseudoVMSNE_VX_M4_MASK 6467 +#define RISCV_PseudoVMSNE_VX_M8 6468 +#define RISCV_PseudoVMSNE_VX_M8_MASK 6469 +#define RISCV_PseudoVMSNE_VX_MF2 6470 +#define RISCV_PseudoVMSNE_VX_MF2_MASK 6471 +#define RISCV_PseudoVMSNE_VX_MF4 6472 +#define RISCV_PseudoVMSNE_VX_MF4_MASK 6473 +#define RISCV_PseudoVMSNE_VX_MF8 6474 +#define RISCV_PseudoVMSNE_VX_MF8_MASK 6475 +#define RISCV_PseudoVMSOF_M_B1 6476 +#define RISCV_PseudoVMSOF_M_B16 6477 +#define RISCV_PseudoVMSOF_M_B16_MASK 6478 +#define RISCV_PseudoVMSOF_M_B1_MASK 6479 +#define RISCV_PseudoVMSOF_M_B2 6480 +#define RISCV_PseudoVMSOF_M_B2_MASK 6481 +#define RISCV_PseudoVMSOF_M_B32 6482 +#define RISCV_PseudoVMSOF_M_B32_MASK 6483 +#define RISCV_PseudoVMSOF_M_B4 6484 +#define RISCV_PseudoVMSOF_M_B4_MASK 6485 +#define RISCV_PseudoVMSOF_M_B64 6486 +#define RISCV_PseudoVMSOF_M_B64_MASK 6487 +#define RISCV_PseudoVMSOF_M_B8 6488 +#define RISCV_PseudoVMSOF_M_B8_MASK 6489 +#define RISCV_PseudoVMULHSU_VV_M1 6490 +#define RISCV_PseudoVMULHSU_VV_M1_MASK 6491 +#define RISCV_PseudoVMULHSU_VV_M2 6492 +#define RISCV_PseudoVMULHSU_VV_M2_MASK 6493 +#define RISCV_PseudoVMULHSU_VV_M4 6494 +#define RISCV_PseudoVMULHSU_VV_M4_MASK 6495 +#define RISCV_PseudoVMULHSU_VV_M8 6496 +#define RISCV_PseudoVMULHSU_VV_M8_MASK 6497 +#define RISCV_PseudoVMULHSU_VV_MF2 6498 +#define RISCV_PseudoVMULHSU_VV_MF2_MASK 6499 +#define RISCV_PseudoVMULHSU_VV_MF4 6500 +#define RISCV_PseudoVMULHSU_VV_MF4_MASK 6501 +#define RISCV_PseudoVMULHSU_VV_MF8 6502 +#define RISCV_PseudoVMULHSU_VV_MF8_MASK 6503 +#define RISCV_PseudoVMULHSU_VX_M1 6504 +#define RISCV_PseudoVMULHSU_VX_M1_MASK 6505 +#define RISCV_PseudoVMULHSU_VX_M2 6506 +#define RISCV_PseudoVMULHSU_VX_M2_MASK 6507 +#define RISCV_PseudoVMULHSU_VX_M4 6508 +#define RISCV_PseudoVMULHSU_VX_M4_MASK 6509 +#define RISCV_PseudoVMULHSU_VX_M8 6510 +#define RISCV_PseudoVMULHSU_VX_M8_MASK 6511 +#define RISCV_PseudoVMULHSU_VX_MF2 6512 +#define RISCV_PseudoVMULHSU_VX_MF2_MASK 6513 +#define RISCV_PseudoVMULHSU_VX_MF4 6514 +#define RISCV_PseudoVMULHSU_VX_MF4_MASK 6515 +#define RISCV_PseudoVMULHSU_VX_MF8 6516 +#define RISCV_PseudoVMULHSU_VX_MF8_MASK 6517 +#define RISCV_PseudoVMULHU_VV_M1 6518 +#define RISCV_PseudoVMULHU_VV_M1_MASK 6519 +#define RISCV_PseudoVMULHU_VV_M2 6520 +#define RISCV_PseudoVMULHU_VV_M2_MASK 6521 +#define RISCV_PseudoVMULHU_VV_M4 6522 +#define RISCV_PseudoVMULHU_VV_M4_MASK 6523 +#define RISCV_PseudoVMULHU_VV_M8 6524 +#define RISCV_PseudoVMULHU_VV_M8_MASK 6525 +#define RISCV_PseudoVMULHU_VV_MF2 6526 +#define RISCV_PseudoVMULHU_VV_MF2_MASK 6527 +#define RISCV_PseudoVMULHU_VV_MF4 6528 +#define RISCV_PseudoVMULHU_VV_MF4_MASK 6529 +#define RISCV_PseudoVMULHU_VV_MF8 6530 +#define RISCV_PseudoVMULHU_VV_MF8_MASK 6531 +#define RISCV_PseudoVMULHU_VX_M1 6532 +#define RISCV_PseudoVMULHU_VX_M1_MASK 6533 +#define RISCV_PseudoVMULHU_VX_M2 6534 +#define RISCV_PseudoVMULHU_VX_M2_MASK 6535 +#define RISCV_PseudoVMULHU_VX_M4 6536 +#define RISCV_PseudoVMULHU_VX_M4_MASK 6537 +#define RISCV_PseudoVMULHU_VX_M8 6538 +#define RISCV_PseudoVMULHU_VX_M8_MASK 6539 +#define RISCV_PseudoVMULHU_VX_MF2 6540 +#define RISCV_PseudoVMULHU_VX_MF2_MASK 6541 +#define RISCV_PseudoVMULHU_VX_MF4 6542 +#define RISCV_PseudoVMULHU_VX_MF4_MASK 6543 +#define RISCV_PseudoVMULHU_VX_MF8 6544 +#define RISCV_PseudoVMULHU_VX_MF8_MASK 6545 +#define RISCV_PseudoVMULH_VV_M1 6546 +#define RISCV_PseudoVMULH_VV_M1_MASK 6547 +#define RISCV_PseudoVMULH_VV_M2 6548 +#define RISCV_PseudoVMULH_VV_M2_MASK 6549 +#define RISCV_PseudoVMULH_VV_M4 6550 +#define RISCV_PseudoVMULH_VV_M4_MASK 6551 +#define RISCV_PseudoVMULH_VV_M8 6552 +#define RISCV_PseudoVMULH_VV_M8_MASK 6553 +#define RISCV_PseudoVMULH_VV_MF2 6554 +#define RISCV_PseudoVMULH_VV_MF2_MASK 6555 +#define RISCV_PseudoVMULH_VV_MF4 6556 +#define RISCV_PseudoVMULH_VV_MF4_MASK 6557 +#define RISCV_PseudoVMULH_VV_MF8 6558 +#define RISCV_PseudoVMULH_VV_MF8_MASK 6559 +#define RISCV_PseudoVMULH_VX_M1 6560 +#define RISCV_PseudoVMULH_VX_M1_MASK 6561 +#define RISCV_PseudoVMULH_VX_M2 6562 +#define RISCV_PseudoVMULH_VX_M2_MASK 6563 +#define RISCV_PseudoVMULH_VX_M4 6564 +#define RISCV_PseudoVMULH_VX_M4_MASK 6565 +#define RISCV_PseudoVMULH_VX_M8 6566 +#define RISCV_PseudoVMULH_VX_M8_MASK 6567 +#define RISCV_PseudoVMULH_VX_MF2 6568 +#define RISCV_PseudoVMULH_VX_MF2_MASK 6569 +#define RISCV_PseudoVMULH_VX_MF4 6570 +#define RISCV_PseudoVMULH_VX_MF4_MASK 6571 +#define RISCV_PseudoVMULH_VX_MF8 6572 +#define RISCV_PseudoVMULH_VX_MF8_MASK 6573 +#define RISCV_PseudoVMUL_VV_M1 6574 +#define RISCV_PseudoVMUL_VV_M1_MASK 6575 +#define RISCV_PseudoVMUL_VV_M2 6576 +#define RISCV_PseudoVMUL_VV_M2_MASK 6577 +#define RISCV_PseudoVMUL_VV_M4 6578 +#define RISCV_PseudoVMUL_VV_M4_MASK 6579 +#define RISCV_PseudoVMUL_VV_M8 6580 +#define RISCV_PseudoVMUL_VV_M8_MASK 6581 +#define RISCV_PseudoVMUL_VV_MF2 6582 +#define RISCV_PseudoVMUL_VV_MF2_MASK 6583 +#define RISCV_PseudoVMUL_VV_MF4 6584 +#define RISCV_PseudoVMUL_VV_MF4_MASK 6585 +#define RISCV_PseudoVMUL_VV_MF8 6586 +#define RISCV_PseudoVMUL_VV_MF8_MASK 6587 +#define RISCV_PseudoVMUL_VX_M1 6588 +#define RISCV_PseudoVMUL_VX_M1_MASK 6589 +#define RISCV_PseudoVMUL_VX_M2 6590 +#define RISCV_PseudoVMUL_VX_M2_MASK 6591 +#define RISCV_PseudoVMUL_VX_M4 6592 +#define RISCV_PseudoVMUL_VX_M4_MASK 6593 +#define RISCV_PseudoVMUL_VX_M8 6594 +#define RISCV_PseudoVMUL_VX_M8_MASK 6595 +#define RISCV_PseudoVMUL_VX_MF2 6596 +#define RISCV_PseudoVMUL_VX_MF2_MASK 6597 +#define RISCV_PseudoVMUL_VX_MF4 6598 +#define RISCV_PseudoVMUL_VX_MF4_MASK 6599 +#define RISCV_PseudoVMUL_VX_MF8 6600 +#define RISCV_PseudoVMUL_VX_MF8_MASK 6601 +#define RISCV_PseudoVMV1R_V 6602 +#define RISCV_PseudoVMV2R_V 6603 +#define RISCV_PseudoVMV4R_V 6604 +#define RISCV_PseudoVMV8R_V 6605 +#define RISCV_PseudoVMV_S_X_M1 6606 +#define RISCV_PseudoVMV_S_X_M2 6607 +#define RISCV_PseudoVMV_S_X_M4 6608 +#define RISCV_PseudoVMV_S_X_M8 6609 +#define RISCV_PseudoVMV_S_X_MF2 6610 +#define RISCV_PseudoVMV_S_X_MF4 6611 +#define RISCV_PseudoVMV_S_X_MF8 6612 +#define RISCV_PseudoVMV_V_I_M1 6613 +#define RISCV_PseudoVMV_V_I_M2 6614 +#define RISCV_PseudoVMV_V_I_M4 6615 +#define RISCV_PseudoVMV_V_I_M8 6616 +#define RISCV_PseudoVMV_V_I_MF2 6617 +#define RISCV_PseudoVMV_V_I_MF4 6618 +#define RISCV_PseudoVMV_V_I_MF8 6619 +#define RISCV_PseudoVMV_V_V_M1 6620 +#define RISCV_PseudoVMV_V_V_M2 6621 +#define RISCV_PseudoVMV_V_V_M4 6622 +#define RISCV_PseudoVMV_V_V_M8 6623 +#define RISCV_PseudoVMV_V_V_MF2 6624 +#define RISCV_PseudoVMV_V_V_MF4 6625 +#define RISCV_PseudoVMV_V_V_MF8 6626 +#define RISCV_PseudoVMV_V_X_M1 6627 +#define RISCV_PseudoVMV_V_X_M2 6628 +#define RISCV_PseudoVMV_V_X_M4 6629 +#define RISCV_PseudoVMV_V_X_M8 6630 +#define RISCV_PseudoVMV_V_X_MF2 6631 +#define RISCV_PseudoVMV_V_X_MF4 6632 +#define RISCV_PseudoVMV_V_X_MF8 6633 +#define RISCV_PseudoVMV_X_S_M1 6634 +#define RISCV_PseudoVMV_X_S_M2 6635 +#define RISCV_PseudoVMV_X_S_M4 6636 +#define RISCV_PseudoVMV_X_S_M8 6637 +#define RISCV_PseudoVMV_X_S_MF2 6638 +#define RISCV_PseudoVMV_X_S_MF4 6639 +#define RISCV_PseudoVMV_X_S_MF8 6640 +#define RISCV_PseudoVMXNOR_MM_M1 6641 +#define RISCV_PseudoVMXNOR_MM_M2 6642 +#define RISCV_PseudoVMXNOR_MM_M4 6643 +#define RISCV_PseudoVMXNOR_MM_M8 6644 +#define RISCV_PseudoVMXNOR_MM_MF2 6645 +#define RISCV_PseudoVMXNOR_MM_MF4 6646 +#define RISCV_PseudoVMXNOR_MM_MF8 6647 +#define RISCV_PseudoVMXOR_MM_M1 6648 +#define RISCV_PseudoVMXOR_MM_M2 6649 +#define RISCV_PseudoVMXOR_MM_M4 6650 +#define RISCV_PseudoVMXOR_MM_M8 6651 +#define RISCV_PseudoVMXOR_MM_MF2 6652 +#define RISCV_PseudoVMXOR_MM_MF4 6653 +#define RISCV_PseudoVMXOR_MM_MF8 6654 +#define RISCV_PseudoVNCLIPU_WI_M1 6655 +#define RISCV_PseudoVNCLIPU_WI_M1_MASK 6656 +#define RISCV_PseudoVNCLIPU_WI_M2 6657 +#define RISCV_PseudoVNCLIPU_WI_M2_MASK 6658 +#define RISCV_PseudoVNCLIPU_WI_M4 6659 +#define RISCV_PseudoVNCLIPU_WI_M4_MASK 6660 +#define RISCV_PseudoVNCLIPU_WI_MF2 6661 +#define RISCV_PseudoVNCLIPU_WI_MF2_MASK 6662 +#define RISCV_PseudoVNCLIPU_WI_MF4 6663 +#define RISCV_PseudoVNCLIPU_WI_MF4_MASK 6664 +#define RISCV_PseudoVNCLIPU_WI_MF8 6665 +#define RISCV_PseudoVNCLIPU_WI_MF8_MASK 6666 +#define RISCV_PseudoVNCLIPU_WV_M1 6667 +#define RISCV_PseudoVNCLIPU_WV_M1_MASK 6668 +#define RISCV_PseudoVNCLIPU_WV_M2 6669 +#define RISCV_PseudoVNCLIPU_WV_M2_MASK 6670 +#define RISCV_PseudoVNCLIPU_WV_M4 6671 +#define RISCV_PseudoVNCLIPU_WV_M4_MASK 6672 +#define RISCV_PseudoVNCLIPU_WV_MF2 6673 +#define RISCV_PseudoVNCLIPU_WV_MF2_MASK 6674 +#define RISCV_PseudoVNCLIPU_WV_MF4 6675 +#define RISCV_PseudoVNCLIPU_WV_MF4_MASK 6676 +#define RISCV_PseudoVNCLIPU_WV_MF8 6677 +#define RISCV_PseudoVNCLIPU_WV_MF8_MASK 6678 +#define RISCV_PseudoVNCLIPU_WX_M1 6679 +#define RISCV_PseudoVNCLIPU_WX_M1_MASK 6680 +#define RISCV_PseudoVNCLIPU_WX_M2 6681 +#define RISCV_PseudoVNCLIPU_WX_M2_MASK 6682 +#define RISCV_PseudoVNCLIPU_WX_M4 6683 +#define RISCV_PseudoVNCLIPU_WX_M4_MASK 6684 +#define RISCV_PseudoVNCLIPU_WX_MF2 6685 +#define RISCV_PseudoVNCLIPU_WX_MF2_MASK 6686 +#define RISCV_PseudoVNCLIPU_WX_MF4 6687 +#define RISCV_PseudoVNCLIPU_WX_MF4_MASK 6688 +#define RISCV_PseudoVNCLIPU_WX_MF8 6689 +#define RISCV_PseudoVNCLIPU_WX_MF8_MASK 6690 +#define RISCV_PseudoVNCLIP_WI_M1 6691 +#define RISCV_PseudoVNCLIP_WI_M1_MASK 6692 +#define RISCV_PseudoVNCLIP_WI_M2 6693 +#define RISCV_PseudoVNCLIP_WI_M2_MASK 6694 +#define RISCV_PseudoVNCLIP_WI_M4 6695 +#define RISCV_PseudoVNCLIP_WI_M4_MASK 6696 +#define RISCV_PseudoVNCLIP_WI_MF2 6697 +#define RISCV_PseudoVNCLIP_WI_MF2_MASK 6698 +#define RISCV_PseudoVNCLIP_WI_MF4 6699 +#define RISCV_PseudoVNCLIP_WI_MF4_MASK 6700 +#define RISCV_PseudoVNCLIP_WI_MF8 6701 +#define RISCV_PseudoVNCLIP_WI_MF8_MASK 6702 +#define RISCV_PseudoVNCLIP_WV_M1 6703 +#define RISCV_PseudoVNCLIP_WV_M1_MASK 6704 +#define RISCV_PseudoVNCLIP_WV_M2 6705 +#define RISCV_PseudoVNCLIP_WV_M2_MASK 6706 +#define RISCV_PseudoVNCLIP_WV_M4 6707 +#define RISCV_PseudoVNCLIP_WV_M4_MASK 6708 +#define RISCV_PseudoVNCLIP_WV_MF2 6709 +#define RISCV_PseudoVNCLIP_WV_MF2_MASK 6710 +#define RISCV_PseudoVNCLIP_WV_MF4 6711 +#define RISCV_PseudoVNCLIP_WV_MF4_MASK 6712 +#define RISCV_PseudoVNCLIP_WV_MF8 6713 +#define RISCV_PseudoVNCLIP_WV_MF8_MASK 6714 +#define RISCV_PseudoVNCLIP_WX_M1 6715 +#define RISCV_PseudoVNCLIP_WX_M1_MASK 6716 +#define RISCV_PseudoVNCLIP_WX_M2 6717 +#define RISCV_PseudoVNCLIP_WX_M2_MASK 6718 +#define RISCV_PseudoVNCLIP_WX_M4 6719 +#define RISCV_PseudoVNCLIP_WX_M4_MASK 6720 +#define RISCV_PseudoVNCLIP_WX_MF2 6721 +#define RISCV_PseudoVNCLIP_WX_MF2_MASK 6722 +#define RISCV_PseudoVNCLIP_WX_MF4 6723 +#define RISCV_PseudoVNCLIP_WX_MF4_MASK 6724 +#define RISCV_PseudoVNCLIP_WX_MF8 6725 +#define RISCV_PseudoVNCLIP_WX_MF8_MASK 6726 +#define RISCV_PseudoVNMSAC_VV_M1 6727 +#define RISCV_PseudoVNMSAC_VV_M1_MASK 6728 +#define RISCV_PseudoVNMSAC_VV_M2 6729 +#define RISCV_PseudoVNMSAC_VV_M2_MASK 6730 +#define RISCV_PseudoVNMSAC_VV_M4 6731 +#define RISCV_PseudoVNMSAC_VV_M4_MASK 6732 +#define RISCV_PseudoVNMSAC_VV_M8 6733 +#define RISCV_PseudoVNMSAC_VV_M8_MASK 6734 +#define RISCV_PseudoVNMSAC_VV_MF2 6735 +#define RISCV_PseudoVNMSAC_VV_MF2_MASK 6736 +#define RISCV_PseudoVNMSAC_VV_MF4 6737 +#define RISCV_PseudoVNMSAC_VV_MF4_MASK 6738 +#define RISCV_PseudoVNMSAC_VV_MF8 6739 +#define RISCV_PseudoVNMSAC_VV_MF8_MASK 6740 +#define RISCV_PseudoVNMSAC_VX_M1 6741 +#define RISCV_PseudoVNMSAC_VX_M1_MASK 6742 +#define RISCV_PseudoVNMSAC_VX_M2 6743 +#define RISCV_PseudoVNMSAC_VX_M2_MASK 6744 +#define RISCV_PseudoVNMSAC_VX_M4 6745 +#define RISCV_PseudoVNMSAC_VX_M4_MASK 6746 +#define RISCV_PseudoVNMSAC_VX_M8 6747 +#define RISCV_PseudoVNMSAC_VX_M8_MASK 6748 +#define RISCV_PseudoVNMSAC_VX_MF2 6749 +#define RISCV_PseudoVNMSAC_VX_MF2_MASK 6750 +#define RISCV_PseudoVNMSAC_VX_MF4 6751 +#define RISCV_PseudoVNMSAC_VX_MF4_MASK 6752 +#define RISCV_PseudoVNMSAC_VX_MF8 6753 +#define RISCV_PseudoVNMSAC_VX_MF8_MASK 6754 +#define RISCV_PseudoVNMSUB_VV_M1 6755 +#define RISCV_PseudoVNMSUB_VV_M1_MASK 6756 +#define RISCV_PseudoVNMSUB_VV_M2 6757 +#define RISCV_PseudoVNMSUB_VV_M2_MASK 6758 +#define RISCV_PseudoVNMSUB_VV_M4 6759 +#define RISCV_PseudoVNMSUB_VV_M4_MASK 6760 +#define RISCV_PseudoVNMSUB_VV_M8 6761 +#define RISCV_PseudoVNMSUB_VV_M8_MASK 6762 +#define RISCV_PseudoVNMSUB_VV_MF2 6763 +#define RISCV_PseudoVNMSUB_VV_MF2_MASK 6764 +#define RISCV_PseudoVNMSUB_VV_MF4 6765 +#define RISCV_PseudoVNMSUB_VV_MF4_MASK 6766 +#define RISCV_PseudoVNMSUB_VV_MF8 6767 +#define RISCV_PseudoVNMSUB_VV_MF8_MASK 6768 +#define RISCV_PseudoVNMSUB_VX_M1 6769 +#define RISCV_PseudoVNMSUB_VX_M1_MASK 6770 +#define RISCV_PseudoVNMSUB_VX_M2 6771 +#define RISCV_PseudoVNMSUB_VX_M2_MASK 6772 +#define RISCV_PseudoVNMSUB_VX_M4 6773 +#define RISCV_PseudoVNMSUB_VX_M4_MASK 6774 +#define RISCV_PseudoVNMSUB_VX_M8 6775 +#define RISCV_PseudoVNMSUB_VX_M8_MASK 6776 +#define RISCV_PseudoVNMSUB_VX_MF2 6777 +#define RISCV_PseudoVNMSUB_VX_MF2_MASK 6778 +#define RISCV_PseudoVNMSUB_VX_MF4 6779 +#define RISCV_PseudoVNMSUB_VX_MF4_MASK 6780 +#define RISCV_PseudoVNMSUB_VX_MF8 6781 +#define RISCV_PseudoVNMSUB_VX_MF8_MASK 6782 +#define RISCV_PseudoVNSRA_WI_M1 6783 +#define RISCV_PseudoVNSRA_WI_M1_MASK 6784 +#define RISCV_PseudoVNSRA_WI_M2 6785 +#define RISCV_PseudoVNSRA_WI_M2_MASK 6786 +#define RISCV_PseudoVNSRA_WI_M4 6787 +#define RISCV_PseudoVNSRA_WI_M4_MASK 6788 +#define RISCV_PseudoVNSRA_WI_MF2 6789 +#define RISCV_PseudoVNSRA_WI_MF2_MASK 6790 +#define RISCV_PseudoVNSRA_WI_MF4 6791 +#define RISCV_PseudoVNSRA_WI_MF4_MASK 6792 +#define RISCV_PseudoVNSRA_WI_MF8 6793 +#define RISCV_PseudoVNSRA_WI_MF8_MASK 6794 +#define RISCV_PseudoVNSRA_WV_M1 6795 +#define RISCV_PseudoVNSRA_WV_M1_MASK 6796 +#define RISCV_PseudoVNSRA_WV_M2 6797 +#define RISCV_PseudoVNSRA_WV_M2_MASK 6798 +#define RISCV_PseudoVNSRA_WV_M4 6799 +#define RISCV_PseudoVNSRA_WV_M4_MASK 6800 +#define RISCV_PseudoVNSRA_WV_MF2 6801 +#define RISCV_PseudoVNSRA_WV_MF2_MASK 6802 +#define RISCV_PseudoVNSRA_WV_MF4 6803 +#define RISCV_PseudoVNSRA_WV_MF4_MASK 6804 +#define RISCV_PseudoVNSRA_WV_MF8 6805 +#define RISCV_PseudoVNSRA_WV_MF8_MASK 6806 +#define RISCV_PseudoVNSRA_WX_M1 6807 +#define RISCV_PseudoVNSRA_WX_M1_MASK 6808 +#define RISCV_PseudoVNSRA_WX_M2 6809 +#define RISCV_PseudoVNSRA_WX_M2_MASK 6810 +#define RISCV_PseudoVNSRA_WX_M4 6811 +#define RISCV_PseudoVNSRA_WX_M4_MASK 6812 +#define RISCV_PseudoVNSRA_WX_MF2 6813 +#define RISCV_PseudoVNSRA_WX_MF2_MASK 6814 +#define RISCV_PseudoVNSRA_WX_MF4 6815 +#define RISCV_PseudoVNSRA_WX_MF4_MASK 6816 +#define RISCV_PseudoVNSRA_WX_MF8 6817 +#define RISCV_PseudoVNSRA_WX_MF8_MASK 6818 +#define RISCV_PseudoVNSRL_WI_M1 6819 +#define RISCV_PseudoVNSRL_WI_M1_MASK 6820 +#define RISCV_PseudoVNSRL_WI_M2 6821 +#define RISCV_PseudoVNSRL_WI_M2_MASK 6822 +#define RISCV_PseudoVNSRL_WI_M4 6823 +#define RISCV_PseudoVNSRL_WI_M4_MASK 6824 +#define RISCV_PseudoVNSRL_WI_MF2 6825 +#define RISCV_PseudoVNSRL_WI_MF2_MASK 6826 +#define RISCV_PseudoVNSRL_WI_MF4 6827 +#define RISCV_PseudoVNSRL_WI_MF4_MASK 6828 +#define RISCV_PseudoVNSRL_WI_MF8 6829 +#define RISCV_PseudoVNSRL_WI_MF8_MASK 6830 +#define RISCV_PseudoVNSRL_WV_M1 6831 +#define RISCV_PseudoVNSRL_WV_M1_MASK 6832 +#define RISCV_PseudoVNSRL_WV_M2 6833 +#define RISCV_PseudoVNSRL_WV_M2_MASK 6834 +#define RISCV_PseudoVNSRL_WV_M4 6835 +#define RISCV_PseudoVNSRL_WV_M4_MASK 6836 +#define RISCV_PseudoVNSRL_WV_MF2 6837 +#define RISCV_PseudoVNSRL_WV_MF2_MASK 6838 +#define RISCV_PseudoVNSRL_WV_MF4 6839 +#define RISCV_PseudoVNSRL_WV_MF4_MASK 6840 +#define RISCV_PseudoVNSRL_WV_MF8 6841 +#define RISCV_PseudoVNSRL_WV_MF8_MASK 6842 +#define RISCV_PseudoVNSRL_WX_M1 6843 +#define RISCV_PseudoVNSRL_WX_M1_MASK 6844 +#define RISCV_PseudoVNSRL_WX_M2 6845 +#define RISCV_PseudoVNSRL_WX_M2_MASK 6846 +#define RISCV_PseudoVNSRL_WX_M4 6847 +#define RISCV_PseudoVNSRL_WX_M4_MASK 6848 +#define RISCV_PseudoVNSRL_WX_MF2 6849 +#define RISCV_PseudoVNSRL_WX_MF2_MASK 6850 +#define RISCV_PseudoVNSRL_WX_MF4 6851 +#define RISCV_PseudoVNSRL_WX_MF4_MASK 6852 +#define RISCV_PseudoVNSRL_WX_MF8 6853 +#define RISCV_PseudoVNSRL_WX_MF8_MASK 6854 +#define RISCV_PseudoVOR_VI_M1 6855 +#define RISCV_PseudoVOR_VI_M1_MASK 6856 +#define RISCV_PseudoVOR_VI_M2 6857 +#define RISCV_PseudoVOR_VI_M2_MASK 6858 +#define RISCV_PseudoVOR_VI_M4 6859 +#define RISCV_PseudoVOR_VI_M4_MASK 6860 +#define RISCV_PseudoVOR_VI_M8 6861 +#define RISCV_PseudoVOR_VI_M8_MASK 6862 +#define RISCV_PseudoVOR_VI_MF2 6863 +#define RISCV_PseudoVOR_VI_MF2_MASK 6864 +#define RISCV_PseudoVOR_VI_MF4 6865 +#define RISCV_PseudoVOR_VI_MF4_MASK 6866 +#define RISCV_PseudoVOR_VI_MF8 6867 +#define RISCV_PseudoVOR_VI_MF8_MASK 6868 +#define RISCV_PseudoVOR_VV_M1 6869 +#define RISCV_PseudoVOR_VV_M1_MASK 6870 +#define RISCV_PseudoVOR_VV_M2 6871 +#define RISCV_PseudoVOR_VV_M2_MASK 6872 +#define RISCV_PseudoVOR_VV_M4 6873 +#define RISCV_PseudoVOR_VV_M4_MASK 6874 +#define RISCV_PseudoVOR_VV_M8 6875 +#define RISCV_PseudoVOR_VV_M8_MASK 6876 +#define RISCV_PseudoVOR_VV_MF2 6877 +#define RISCV_PseudoVOR_VV_MF2_MASK 6878 +#define RISCV_PseudoVOR_VV_MF4 6879 +#define RISCV_PseudoVOR_VV_MF4_MASK 6880 +#define RISCV_PseudoVOR_VV_MF8 6881 +#define RISCV_PseudoVOR_VV_MF8_MASK 6882 +#define RISCV_PseudoVOR_VX_M1 6883 +#define RISCV_PseudoVOR_VX_M1_MASK 6884 +#define RISCV_PseudoVOR_VX_M2 6885 +#define RISCV_PseudoVOR_VX_M2_MASK 6886 +#define RISCV_PseudoVOR_VX_M4 6887 +#define RISCV_PseudoVOR_VX_M4_MASK 6888 +#define RISCV_PseudoVOR_VX_M8 6889 +#define RISCV_PseudoVOR_VX_M8_MASK 6890 +#define RISCV_PseudoVOR_VX_MF2 6891 +#define RISCV_PseudoVOR_VX_MF2_MASK 6892 +#define RISCV_PseudoVOR_VX_MF4 6893 +#define RISCV_PseudoVOR_VX_MF4_MASK 6894 +#define RISCV_PseudoVOR_VX_MF8 6895 +#define RISCV_PseudoVOR_VX_MF8_MASK 6896 +#define RISCV_PseudoVREDAND_VS_M1 6897 +#define RISCV_PseudoVREDAND_VS_M1_MASK 6898 +#define RISCV_PseudoVREDAND_VS_M2 6899 +#define RISCV_PseudoVREDAND_VS_M2_MASK 6900 +#define RISCV_PseudoVREDAND_VS_M4 6901 +#define RISCV_PseudoVREDAND_VS_M4_MASK 6902 +#define RISCV_PseudoVREDAND_VS_M8 6903 +#define RISCV_PseudoVREDAND_VS_M8_MASK 6904 +#define RISCV_PseudoVREDAND_VS_MF2 6905 +#define RISCV_PseudoVREDAND_VS_MF2_MASK 6906 +#define RISCV_PseudoVREDAND_VS_MF4 6907 +#define RISCV_PseudoVREDAND_VS_MF4_MASK 6908 +#define RISCV_PseudoVREDAND_VS_MF8 6909 +#define RISCV_PseudoVREDAND_VS_MF8_MASK 6910 +#define RISCV_PseudoVREDMAXU_VS_M1 6911 +#define RISCV_PseudoVREDMAXU_VS_M1_MASK 6912 +#define RISCV_PseudoVREDMAXU_VS_M2 6913 +#define RISCV_PseudoVREDMAXU_VS_M2_MASK 6914 +#define RISCV_PseudoVREDMAXU_VS_M4 6915 +#define RISCV_PseudoVREDMAXU_VS_M4_MASK 6916 +#define RISCV_PseudoVREDMAXU_VS_M8 6917 +#define RISCV_PseudoVREDMAXU_VS_M8_MASK 6918 +#define RISCV_PseudoVREDMAXU_VS_MF2 6919 +#define RISCV_PseudoVREDMAXU_VS_MF2_MASK 6920 +#define RISCV_PseudoVREDMAXU_VS_MF4 6921 +#define RISCV_PseudoVREDMAXU_VS_MF4_MASK 6922 +#define RISCV_PseudoVREDMAXU_VS_MF8 6923 +#define RISCV_PseudoVREDMAXU_VS_MF8_MASK 6924 +#define RISCV_PseudoVREDMAX_VS_M1 6925 +#define RISCV_PseudoVREDMAX_VS_M1_MASK 6926 +#define RISCV_PseudoVREDMAX_VS_M2 6927 +#define RISCV_PseudoVREDMAX_VS_M2_MASK 6928 +#define RISCV_PseudoVREDMAX_VS_M4 6929 +#define RISCV_PseudoVREDMAX_VS_M4_MASK 6930 +#define RISCV_PseudoVREDMAX_VS_M8 6931 +#define RISCV_PseudoVREDMAX_VS_M8_MASK 6932 +#define RISCV_PseudoVREDMAX_VS_MF2 6933 +#define RISCV_PseudoVREDMAX_VS_MF2_MASK 6934 +#define RISCV_PseudoVREDMAX_VS_MF4 6935 +#define RISCV_PseudoVREDMAX_VS_MF4_MASK 6936 +#define RISCV_PseudoVREDMAX_VS_MF8 6937 +#define RISCV_PseudoVREDMAX_VS_MF8_MASK 6938 +#define RISCV_PseudoVREDMINU_VS_M1 6939 +#define RISCV_PseudoVREDMINU_VS_M1_MASK 6940 +#define RISCV_PseudoVREDMINU_VS_M2 6941 +#define RISCV_PseudoVREDMINU_VS_M2_MASK 6942 +#define RISCV_PseudoVREDMINU_VS_M4 6943 +#define RISCV_PseudoVREDMINU_VS_M4_MASK 6944 +#define RISCV_PseudoVREDMINU_VS_M8 6945 +#define RISCV_PseudoVREDMINU_VS_M8_MASK 6946 +#define RISCV_PseudoVREDMINU_VS_MF2 6947 +#define RISCV_PseudoVREDMINU_VS_MF2_MASK 6948 +#define RISCV_PseudoVREDMINU_VS_MF4 6949 +#define RISCV_PseudoVREDMINU_VS_MF4_MASK 6950 +#define RISCV_PseudoVREDMINU_VS_MF8 6951 +#define RISCV_PseudoVREDMINU_VS_MF8_MASK 6952 +#define RISCV_PseudoVREDMIN_VS_M1 6953 +#define RISCV_PseudoVREDMIN_VS_M1_MASK 6954 +#define RISCV_PseudoVREDMIN_VS_M2 6955 +#define RISCV_PseudoVREDMIN_VS_M2_MASK 6956 +#define RISCV_PseudoVREDMIN_VS_M4 6957 +#define RISCV_PseudoVREDMIN_VS_M4_MASK 6958 +#define RISCV_PseudoVREDMIN_VS_M8 6959 +#define RISCV_PseudoVREDMIN_VS_M8_MASK 6960 +#define RISCV_PseudoVREDMIN_VS_MF2 6961 +#define RISCV_PseudoVREDMIN_VS_MF2_MASK 6962 +#define RISCV_PseudoVREDMIN_VS_MF4 6963 +#define RISCV_PseudoVREDMIN_VS_MF4_MASK 6964 +#define RISCV_PseudoVREDMIN_VS_MF8 6965 +#define RISCV_PseudoVREDMIN_VS_MF8_MASK 6966 +#define RISCV_PseudoVREDOR_VS_M1 6967 +#define RISCV_PseudoVREDOR_VS_M1_MASK 6968 +#define RISCV_PseudoVREDOR_VS_M2 6969 +#define RISCV_PseudoVREDOR_VS_M2_MASK 6970 +#define RISCV_PseudoVREDOR_VS_M4 6971 +#define RISCV_PseudoVREDOR_VS_M4_MASK 6972 +#define RISCV_PseudoVREDOR_VS_M8 6973 +#define RISCV_PseudoVREDOR_VS_M8_MASK 6974 +#define RISCV_PseudoVREDOR_VS_MF2 6975 +#define RISCV_PseudoVREDOR_VS_MF2_MASK 6976 +#define RISCV_PseudoVREDOR_VS_MF4 6977 +#define RISCV_PseudoVREDOR_VS_MF4_MASK 6978 +#define RISCV_PseudoVREDOR_VS_MF8 6979 +#define RISCV_PseudoVREDOR_VS_MF8_MASK 6980 +#define RISCV_PseudoVREDSUM_VS_M1 6981 +#define RISCV_PseudoVREDSUM_VS_M1_MASK 6982 +#define RISCV_PseudoVREDSUM_VS_M2 6983 +#define RISCV_PseudoVREDSUM_VS_M2_MASK 6984 +#define RISCV_PseudoVREDSUM_VS_M4 6985 +#define RISCV_PseudoVREDSUM_VS_M4_MASK 6986 +#define RISCV_PseudoVREDSUM_VS_M8 6987 +#define RISCV_PseudoVREDSUM_VS_M8_MASK 6988 +#define RISCV_PseudoVREDSUM_VS_MF2 6989 +#define RISCV_PseudoVREDSUM_VS_MF2_MASK 6990 +#define RISCV_PseudoVREDSUM_VS_MF4 6991 +#define RISCV_PseudoVREDSUM_VS_MF4_MASK 6992 +#define RISCV_PseudoVREDSUM_VS_MF8 6993 +#define RISCV_PseudoVREDSUM_VS_MF8_MASK 6994 +#define RISCV_PseudoVREDXOR_VS_M1 6995 +#define RISCV_PseudoVREDXOR_VS_M1_MASK 6996 +#define RISCV_PseudoVREDXOR_VS_M2 6997 +#define RISCV_PseudoVREDXOR_VS_M2_MASK 6998 +#define RISCV_PseudoVREDXOR_VS_M4 6999 +#define RISCV_PseudoVREDXOR_VS_M4_MASK 7000 +#define RISCV_PseudoVREDXOR_VS_M8 7001 +#define RISCV_PseudoVREDXOR_VS_M8_MASK 7002 +#define RISCV_PseudoVREDXOR_VS_MF2 7003 +#define RISCV_PseudoVREDXOR_VS_MF2_MASK 7004 +#define RISCV_PseudoVREDXOR_VS_MF4 7005 +#define RISCV_PseudoVREDXOR_VS_MF4_MASK 7006 +#define RISCV_PseudoVREDXOR_VS_MF8 7007 +#define RISCV_PseudoVREDXOR_VS_MF8_MASK 7008 +#define RISCV_PseudoVRELOAD2_M1 7009 +#define RISCV_PseudoVRELOAD2_M2 7010 +#define RISCV_PseudoVRELOAD2_M4 7011 +#define RISCV_PseudoVRELOAD2_MF2 7012 +#define RISCV_PseudoVRELOAD2_MF4 7013 +#define RISCV_PseudoVRELOAD2_MF8 7014 +#define RISCV_PseudoVRELOAD3_M1 7015 +#define RISCV_PseudoVRELOAD3_M2 7016 +#define RISCV_PseudoVRELOAD3_MF2 7017 +#define RISCV_PseudoVRELOAD3_MF4 7018 +#define RISCV_PseudoVRELOAD3_MF8 7019 +#define RISCV_PseudoVRELOAD4_M1 7020 +#define RISCV_PseudoVRELOAD4_M2 7021 +#define RISCV_PseudoVRELOAD4_MF2 7022 +#define RISCV_PseudoVRELOAD4_MF4 7023 +#define RISCV_PseudoVRELOAD4_MF8 7024 +#define RISCV_PseudoVRELOAD5_M1 7025 +#define RISCV_PseudoVRELOAD5_MF2 7026 +#define RISCV_PseudoVRELOAD5_MF4 7027 +#define RISCV_PseudoVRELOAD5_MF8 7028 +#define RISCV_PseudoVRELOAD6_M1 7029 +#define RISCV_PseudoVRELOAD6_MF2 7030 +#define RISCV_PseudoVRELOAD6_MF4 7031 +#define RISCV_PseudoVRELOAD6_MF8 7032 +#define RISCV_PseudoVRELOAD7_M1 7033 +#define RISCV_PseudoVRELOAD7_MF2 7034 +#define RISCV_PseudoVRELOAD7_MF4 7035 +#define RISCV_PseudoVRELOAD7_MF8 7036 +#define RISCV_PseudoVRELOAD8_M1 7037 +#define RISCV_PseudoVRELOAD8_MF2 7038 +#define RISCV_PseudoVRELOAD8_MF4 7039 +#define RISCV_PseudoVRELOAD8_MF8 7040 +#define RISCV_PseudoVRELOAD_M1 7041 +#define RISCV_PseudoVRELOAD_M2 7042 +#define RISCV_PseudoVRELOAD_M4 7043 +#define RISCV_PseudoVRELOAD_M8 7044 +#define RISCV_PseudoVREMU_VV_M1 7045 +#define RISCV_PseudoVREMU_VV_M1_MASK 7046 +#define RISCV_PseudoVREMU_VV_M2 7047 +#define RISCV_PseudoVREMU_VV_M2_MASK 7048 +#define RISCV_PseudoVREMU_VV_M4 7049 +#define RISCV_PseudoVREMU_VV_M4_MASK 7050 +#define RISCV_PseudoVREMU_VV_M8 7051 +#define RISCV_PseudoVREMU_VV_M8_MASK 7052 +#define RISCV_PseudoVREMU_VV_MF2 7053 +#define RISCV_PseudoVREMU_VV_MF2_MASK 7054 +#define RISCV_PseudoVREMU_VV_MF4 7055 +#define RISCV_PseudoVREMU_VV_MF4_MASK 7056 +#define RISCV_PseudoVREMU_VV_MF8 7057 +#define RISCV_PseudoVREMU_VV_MF8_MASK 7058 +#define RISCV_PseudoVREMU_VX_M1 7059 +#define RISCV_PseudoVREMU_VX_M1_MASK 7060 +#define RISCV_PseudoVREMU_VX_M2 7061 +#define RISCV_PseudoVREMU_VX_M2_MASK 7062 +#define RISCV_PseudoVREMU_VX_M4 7063 +#define RISCV_PseudoVREMU_VX_M4_MASK 7064 +#define RISCV_PseudoVREMU_VX_M8 7065 +#define RISCV_PseudoVREMU_VX_M8_MASK 7066 +#define RISCV_PseudoVREMU_VX_MF2 7067 +#define RISCV_PseudoVREMU_VX_MF2_MASK 7068 +#define RISCV_PseudoVREMU_VX_MF4 7069 +#define RISCV_PseudoVREMU_VX_MF4_MASK 7070 +#define RISCV_PseudoVREMU_VX_MF8 7071 +#define RISCV_PseudoVREMU_VX_MF8_MASK 7072 +#define RISCV_PseudoVREM_VV_M1 7073 +#define RISCV_PseudoVREM_VV_M1_MASK 7074 +#define RISCV_PseudoVREM_VV_M2 7075 +#define RISCV_PseudoVREM_VV_M2_MASK 7076 +#define RISCV_PseudoVREM_VV_M4 7077 +#define RISCV_PseudoVREM_VV_M4_MASK 7078 +#define RISCV_PseudoVREM_VV_M8 7079 +#define RISCV_PseudoVREM_VV_M8_MASK 7080 +#define RISCV_PseudoVREM_VV_MF2 7081 +#define RISCV_PseudoVREM_VV_MF2_MASK 7082 +#define RISCV_PseudoVREM_VV_MF4 7083 +#define RISCV_PseudoVREM_VV_MF4_MASK 7084 +#define RISCV_PseudoVREM_VV_MF8 7085 +#define RISCV_PseudoVREM_VV_MF8_MASK 7086 +#define RISCV_PseudoVREM_VX_M1 7087 +#define RISCV_PseudoVREM_VX_M1_MASK 7088 +#define RISCV_PseudoVREM_VX_M2 7089 +#define RISCV_PseudoVREM_VX_M2_MASK 7090 +#define RISCV_PseudoVREM_VX_M4 7091 +#define RISCV_PseudoVREM_VX_M4_MASK 7092 +#define RISCV_PseudoVREM_VX_M8 7093 +#define RISCV_PseudoVREM_VX_M8_MASK 7094 +#define RISCV_PseudoVREM_VX_MF2 7095 +#define RISCV_PseudoVREM_VX_MF2_MASK 7096 +#define RISCV_PseudoVREM_VX_MF4 7097 +#define RISCV_PseudoVREM_VX_MF4_MASK 7098 +#define RISCV_PseudoVREM_VX_MF8 7099 +#define RISCV_PseudoVREM_VX_MF8_MASK 7100 +#define RISCV_PseudoVRGATHEREI16_VV_M1_M1 7101 +#define RISCV_PseudoVRGATHEREI16_VV_M1_M1_MASK 7102 +#define RISCV_PseudoVRGATHEREI16_VV_M1_M2 7103 +#define RISCV_PseudoVRGATHEREI16_VV_M1_M2_MASK 7104 +#define RISCV_PseudoVRGATHEREI16_VV_M1_MF2 7105 +#define RISCV_PseudoVRGATHEREI16_VV_M1_MF2_MASK 7106 +#define RISCV_PseudoVRGATHEREI16_VV_M1_MF4 7107 +#define RISCV_PseudoVRGATHEREI16_VV_M1_MF4_MASK 7108 +#define RISCV_PseudoVRGATHEREI16_VV_M2_M1 7109 +#define RISCV_PseudoVRGATHEREI16_VV_M2_M1_MASK 7110 +#define RISCV_PseudoVRGATHEREI16_VV_M2_M2 7111 +#define RISCV_PseudoVRGATHEREI16_VV_M2_M2_MASK 7112 +#define RISCV_PseudoVRGATHEREI16_VV_M2_M4 7113 +#define RISCV_PseudoVRGATHEREI16_VV_M2_M4_MASK 7114 +#define RISCV_PseudoVRGATHEREI16_VV_M2_MF2 7115 +#define RISCV_PseudoVRGATHEREI16_VV_M2_MF2_MASK 7116 +#define RISCV_PseudoVRGATHEREI16_VV_M4_M1 7117 +#define RISCV_PseudoVRGATHEREI16_VV_M4_M1_MASK 7118 +#define RISCV_PseudoVRGATHEREI16_VV_M4_M2 7119 +#define RISCV_PseudoVRGATHEREI16_VV_M4_M2_MASK 7120 +#define RISCV_PseudoVRGATHEREI16_VV_M4_M4 7121 +#define RISCV_PseudoVRGATHEREI16_VV_M4_M4_MASK 7122 +#define RISCV_PseudoVRGATHEREI16_VV_M4_M8 7123 +#define RISCV_PseudoVRGATHEREI16_VV_M4_M8_MASK 7124 +#define RISCV_PseudoVRGATHEREI16_VV_M8_M2 7125 +#define RISCV_PseudoVRGATHEREI16_VV_M8_M2_MASK 7126 +#define RISCV_PseudoVRGATHEREI16_VV_M8_M4 7127 +#define RISCV_PseudoVRGATHEREI16_VV_M8_M4_MASK 7128 +#define RISCV_PseudoVRGATHEREI16_VV_M8_M8 7129 +#define RISCV_PseudoVRGATHEREI16_VV_M8_M8_MASK 7130 +#define RISCV_PseudoVRGATHEREI16_VV_MF2_M1 7131 +#define RISCV_PseudoVRGATHEREI16_VV_MF2_M1_MASK 7132 +#define RISCV_PseudoVRGATHEREI16_VV_MF2_MF2 7133 +#define RISCV_PseudoVRGATHEREI16_VV_MF2_MF2_MASK 7134 +#define RISCV_PseudoVRGATHEREI16_VV_MF2_MF4 7135 +#define RISCV_PseudoVRGATHEREI16_VV_MF2_MF4_MASK 7136 +#define RISCV_PseudoVRGATHEREI16_VV_MF2_MF8 7137 +#define RISCV_PseudoVRGATHEREI16_VV_MF2_MF8_MASK 7138 +#define RISCV_PseudoVRGATHEREI16_VV_MF4_MF2 7139 +#define RISCV_PseudoVRGATHEREI16_VV_MF4_MF2_MASK 7140 +#define RISCV_PseudoVRGATHEREI16_VV_MF4_MF4 7141 +#define RISCV_PseudoVRGATHEREI16_VV_MF4_MF4_MASK 7142 +#define RISCV_PseudoVRGATHEREI16_VV_MF4_MF8 7143 +#define RISCV_PseudoVRGATHEREI16_VV_MF4_MF8_MASK 7144 +#define RISCV_PseudoVRGATHEREI16_VV_MF8_MF4 7145 +#define RISCV_PseudoVRGATHEREI16_VV_MF8_MF4_MASK 7146 +#define RISCV_PseudoVRGATHEREI16_VV_MF8_MF8 7147 +#define RISCV_PseudoVRGATHEREI16_VV_MF8_MF8_MASK 7148 +#define RISCV_PseudoVRGATHER_VI_M1 7149 +#define RISCV_PseudoVRGATHER_VI_M1_MASK 7150 +#define RISCV_PseudoVRGATHER_VI_M2 7151 +#define RISCV_PseudoVRGATHER_VI_M2_MASK 7152 +#define RISCV_PseudoVRGATHER_VI_M4 7153 +#define RISCV_PseudoVRGATHER_VI_M4_MASK 7154 +#define RISCV_PseudoVRGATHER_VI_M8 7155 +#define RISCV_PseudoVRGATHER_VI_M8_MASK 7156 +#define RISCV_PseudoVRGATHER_VI_MF2 7157 +#define RISCV_PseudoVRGATHER_VI_MF2_MASK 7158 +#define RISCV_PseudoVRGATHER_VI_MF4 7159 +#define RISCV_PseudoVRGATHER_VI_MF4_MASK 7160 +#define RISCV_PseudoVRGATHER_VI_MF8 7161 +#define RISCV_PseudoVRGATHER_VI_MF8_MASK 7162 +#define RISCV_PseudoVRGATHER_VV_M1 7163 +#define RISCV_PseudoVRGATHER_VV_M1_MASK 7164 +#define RISCV_PseudoVRGATHER_VV_M2 7165 +#define RISCV_PseudoVRGATHER_VV_M2_MASK 7166 +#define RISCV_PseudoVRGATHER_VV_M4 7167 +#define RISCV_PseudoVRGATHER_VV_M4_MASK 7168 +#define RISCV_PseudoVRGATHER_VV_M8 7169 +#define RISCV_PseudoVRGATHER_VV_M8_MASK 7170 +#define RISCV_PseudoVRGATHER_VV_MF2 7171 +#define RISCV_PseudoVRGATHER_VV_MF2_MASK 7172 +#define RISCV_PseudoVRGATHER_VV_MF4 7173 +#define RISCV_PseudoVRGATHER_VV_MF4_MASK 7174 +#define RISCV_PseudoVRGATHER_VV_MF8 7175 +#define RISCV_PseudoVRGATHER_VV_MF8_MASK 7176 +#define RISCV_PseudoVRGATHER_VX_M1 7177 +#define RISCV_PseudoVRGATHER_VX_M1_MASK 7178 +#define RISCV_PseudoVRGATHER_VX_M2 7179 +#define RISCV_PseudoVRGATHER_VX_M2_MASK 7180 +#define RISCV_PseudoVRGATHER_VX_M4 7181 +#define RISCV_PseudoVRGATHER_VX_M4_MASK 7182 +#define RISCV_PseudoVRGATHER_VX_M8 7183 +#define RISCV_PseudoVRGATHER_VX_M8_MASK 7184 +#define RISCV_PseudoVRGATHER_VX_MF2 7185 +#define RISCV_PseudoVRGATHER_VX_MF2_MASK 7186 +#define RISCV_PseudoVRGATHER_VX_MF4 7187 +#define RISCV_PseudoVRGATHER_VX_MF4_MASK 7188 +#define RISCV_PseudoVRGATHER_VX_MF8 7189 +#define RISCV_PseudoVRGATHER_VX_MF8_MASK 7190 +#define RISCV_PseudoVRSUB_VI_M1 7191 +#define RISCV_PseudoVRSUB_VI_M1_MASK 7192 +#define RISCV_PseudoVRSUB_VI_M2 7193 +#define RISCV_PseudoVRSUB_VI_M2_MASK 7194 +#define RISCV_PseudoVRSUB_VI_M4 7195 +#define RISCV_PseudoVRSUB_VI_M4_MASK 7196 +#define RISCV_PseudoVRSUB_VI_M8 7197 +#define RISCV_PseudoVRSUB_VI_M8_MASK 7198 +#define RISCV_PseudoVRSUB_VI_MF2 7199 +#define RISCV_PseudoVRSUB_VI_MF2_MASK 7200 +#define RISCV_PseudoVRSUB_VI_MF4 7201 +#define RISCV_PseudoVRSUB_VI_MF4_MASK 7202 +#define RISCV_PseudoVRSUB_VI_MF8 7203 +#define RISCV_PseudoVRSUB_VI_MF8_MASK 7204 +#define RISCV_PseudoVRSUB_VX_M1 7205 +#define RISCV_PseudoVRSUB_VX_M1_MASK 7206 +#define RISCV_PseudoVRSUB_VX_M2 7207 +#define RISCV_PseudoVRSUB_VX_M2_MASK 7208 +#define RISCV_PseudoVRSUB_VX_M4 7209 +#define RISCV_PseudoVRSUB_VX_M4_MASK 7210 +#define RISCV_PseudoVRSUB_VX_M8 7211 +#define RISCV_PseudoVRSUB_VX_M8_MASK 7212 +#define RISCV_PseudoVRSUB_VX_MF2 7213 +#define RISCV_PseudoVRSUB_VX_MF2_MASK 7214 +#define RISCV_PseudoVRSUB_VX_MF4 7215 +#define RISCV_PseudoVRSUB_VX_MF4_MASK 7216 +#define RISCV_PseudoVRSUB_VX_MF8 7217 +#define RISCV_PseudoVRSUB_VX_MF8_MASK 7218 +#define RISCV_PseudoVSADDU_VI_M1 7219 +#define RISCV_PseudoVSADDU_VI_M1_MASK 7220 +#define RISCV_PseudoVSADDU_VI_M2 7221 +#define RISCV_PseudoVSADDU_VI_M2_MASK 7222 +#define RISCV_PseudoVSADDU_VI_M4 7223 +#define RISCV_PseudoVSADDU_VI_M4_MASK 7224 +#define RISCV_PseudoVSADDU_VI_M8 7225 +#define RISCV_PseudoVSADDU_VI_M8_MASK 7226 +#define RISCV_PseudoVSADDU_VI_MF2 7227 +#define RISCV_PseudoVSADDU_VI_MF2_MASK 7228 +#define RISCV_PseudoVSADDU_VI_MF4 7229 +#define RISCV_PseudoVSADDU_VI_MF4_MASK 7230 +#define RISCV_PseudoVSADDU_VI_MF8 7231 +#define RISCV_PseudoVSADDU_VI_MF8_MASK 7232 +#define RISCV_PseudoVSADDU_VV_M1 7233 +#define RISCV_PseudoVSADDU_VV_M1_MASK 7234 +#define RISCV_PseudoVSADDU_VV_M2 7235 +#define RISCV_PseudoVSADDU_VV_M2_MASK 7236 +#define RISCV_PseudoVSADDU_VV_M4 7237 +#define RISCV_PseudoVSADDU_VV_M4_MASK 7238 +#define RISCV_PseudoVSADDU_VV_M8 7239 +#define RISCV_PseudoVSADDU_VV_M8_MASK 7240 +#define RISCV_PseudoVSADDU_VV_MF2 7241 +#define RISCV_PseudoVSADDU_VV_MF2_MASK 7242 +#define RISCV_PseudoVSADDU_VV_MF4 7243 +#define RISCV_PseudoVSADDU_VV_MF4_MASK 7244 +#define RISCV_PseudoVSADDU_VV_MF8 7245 +#define RISCV_PseudoVSADDU_VV_MF8_MASK 7246 +#define RISCV_PseudoVSADDU_VX_M1 7247 +#define RISCV_PseudoVSADDU_VX_M1_MASK 7248 +#define RISCV_PseudoVSADDU_VX_M2 7249 +#define RISCV_PseudoVSADDU_VX_M2_MASK 7250 +#define RISCV_PseudoVSADDU_VX_M4 7251 +#define RISCV_PseudoVSADDU_VX_M4_MASK 7252 +#define RISCV_PseudoVSADDU_VX_M8 7253 +#define RISCV_PseudoVSADDU_VX_M8_MASK 7254 +#define RISCV_PseudoVSADDU_VX_MF2 7255 +#define RISCV_PseudoVSADDU_VX_MF2_MASK 7256 +#define RISCV_PseudoVSADDU_VX_MF4 7257 +#define RISCV_PseudoVSADDU_VX_MF4_MASK 7258 +#define RISCV_PseudoVSADDU_VX_MF8 7259 +#define RISCV_PseudoVSADDU_VX_MF8_MASK 7260 +#define RISCV_PseudoVSADD_VI_M1 7261 +#define RISCV_PseudoVSADD_VI_M1_MASK 7262 +#define RISCV_PseudoVSADD_VI_M2 7263 +#define RISCV_PseudoVSADD_VI_M2_MASK 7264 +#define RISCV_PseudoVSADD_VI_M4 7265 +#define RISCV_PseudoVSADD_VI_M4_MASK 7266 +#define RISCV_PseudoVSADD_VI_M8 7267 +#define RISCV_PseudoVSADD_VI_M8_MASK 7268 +#define RISCV_PseudoVSADD_VI_MF2 7269 +#define RISCV_PseudoVSADD_VI_MF2_MASK 7270 +#define RISCV_PseudoVSADD_VI_MF4 7271 +#define RISCV_PseudoVSADD_VI_MF4_MASK 7272 +#define RISCV_PseudoVSADD_VI_MF8 7273 +#define RISCV_PseudoVSADD_VI_MF8_MASK 7274 +#define RISCV_PseudoVSADD_VV_M1 7275 +#define RISCV_PseudoVSADD_VV_M1_MASK 7276 +#define RISCV_PseudoVSADD_VV_M2 7277 +#define RISCV_PseudoVSADD_VV_M2_MASK 7278 +#define RISCV_PseudoVSADD_VV_M4 7279 +#define RISCV_PseudoVSADD_VV_M4_MASK 7280 +#define RISCV_PseudoVSADD_VV_M8 7281 +#define RISCV_PseudoVSADD_VV_M8_MASK 7282 +#define RISCV_PseudoVSADD_VV_MF2 7283 +#define RISCV_PseudoVSADD_VV_MF2_MASK 7284 +#define RISCV_PseudoVSADD_VV_MF4 7285 +#define RISCV_PseudoVSADD_VV_MF4_MASK 7286 +#define RISCV_PseudoVSADD_VV_MF8 7287 +#define RISCV_PseudoVSADD_VV_MF8_MASK 7288 +#define RISCV_PseudoVSADD_VX_M1 7289 +#define RISCV_PseudoVSADD_VX_M1_MASK 7290 +#define RISCV_PseudoVSADD_VX_M2 7291 +#define RISCV_PseudoVSADD_VX_M2_MASK 7292 +#define RISCV_PseudoVSADD_VX_M4 7293 +#define RISCV_PseudoVSADD_VX_M4_MASK 7294 +#define RISCV_PseudoVSADD_VX_M8 7295 +#define RISCV_PseudoVSADD_VX_M8_MASK 7296 +#define RISCV_PseudoVSADD_VX_MF2 7297 +#define RISCV_PseudoVSADD_VX_MF2_MASK 7298 +#define RISCV_PseudoVSADD_VX_MF4 7299 +#define RISCV_PseudoVSADD_VX_MF4_MASK 7300 +#define RISCV_PseudoVSADD_VX_MF8 7301 +#define RISCV_PseudoVSADD_VX_MF8_MASK 7302 +#define RISCV_PseudoVSBC_VVM_M1 7303 +#define RISCV_PseudoVSBC_VVM_M2 7304 +#define RISCV_PseudoVSBC_VVM_M4 7305 +#define RISCV_PseudoVSBC_VVM_M8 7306 +#define RISCV_PseudoVSBC_VVM_MF2 7307 +#define RISCV_PseudoVSBC_VVM_MF4 7308 +#define RISCV_PseudoVSBC_VVM_MF8 7309 +#define RISCV_PseudoVSBC_VXM_M1 7310 +#define RISCV_PseudoVSBC_VXM_M2 7311 +#define RISCV_PseudoVSBC_VXM_M4 7312 +#define RISCV_PseudoVSBC_VXM_M8 7313 +#define RISCV_PseudoVSBC_VXM_MF2 7314 +#define RISCV_PseudoVSBC_VXM_MF4 7315 +#define RISCV_PseudoVSBC_VXM_MF8 7316 +#define RISCV_PseudoVSE16_V_M1 7317 +#define RISCV_PseudoVSE16_V_M1_MASK 7318 +#define RISCV_PseudoVSE16_V_M2 7319 +#define RISCV_PseudoVSE16_V_M2_MASK 7320 +#define RISCV_PseudoVSE16_V_M4 7321 +#define RISCV_PseudoVSE16_V_M4_MASK 7322 +#define RISCV_PseudoVSE16_V_M8 7323 +#define RISCV_PseudoVSE16_V_M8_MASK 7324 +#define RISCV_PseudoVSE16_V_MF2 7325 +#define RISCV_PseudoVSE16_V_MF2_MASK 7326 +#define RISCV_PseudoVSE16_V_MF4 7327 +#define RISCV_PseudoVSE16_V_MF4_MASK 7328 +#define RISCV_PseudoVSE32_V_M1 7329 +#define RISCV_PseudoVSE32_V_M1_MASK 7330 +#define RISCV_PseudoVSE32_V_M2 7331 +#define RISCV_PseudoVSE32_V_M2_MASK 7332 +#define RISCV_PseudoVSE32_V_M4 7333 +#define RISCV_PseudoVSE32_V_M4_MASK 7334 +#define RISCV_PseudoVSE32_V_M8 7335 +#define RISCV_PseudoVSE32_V_M8_MASK 7336 +#define RISCV_PseudoVSE32_V_MF2 7337 +#define RISCV_PseudoVSE32_V_MF2_MASK 7338 +#define RISCV_PseudoVSE64_V_M1 7339 +#define RISCV_PseudoVSE64_V_M1_MASK 7340 +#define RISCV_PseudoVSE64_V_M2 7341 +#define RISCV_PseudoVSE64_V_M2_MASK 7342 +#define RISCV_PseudoVSE64_V_M4 7343 +#define RISCV_PseudoVSE64_V_M4_MASK 7344 +#define RISCV_PseudoVSE64_V_M8 7345 +#define RISCV_PseudoVSE64_V_M8_MASK 7346 +#define RISCV_PseudoVSE8_V_M1 7347 +#define RISCV_PseudoVSE8_V_M1_MASK 7348 +#define RISCV_PseudoVSE8_V_M2 7349 +#define RISCV_PseudoVSE8_V_M2_MASK 7350 +#define RISCV_PseudoVSE8_V_M4 7351 +#define RISCV_PseudoVSE8_V_M4_MASK 7352 +#define RISCV_PseudoVSE8_V_M8 7353 +#define RISCV_PseudoVSE8_V_M8_MASK 7354 +#define RISCV_PseudoVSE8_V_MF2 7355 +#define RISCV_PseudoVSE8_V_MF2_MASK 7356 +#define RISCV_PseudoVSE8_V_MF4 7357 +#define RISCV_PseudoVSE8_V_MF4_MASK 7358 +#define RISCV_PseudoVSE8_V_MF8 7359 +#define RISCV_PseudoVSE8_V_MF8_MASK 7360 +#define RISCV_PseudoVSETIVLI 7361 +#define RISCV_PseudoVSETVLI 7362 +#define RISCV_PseudoVSETVLIX0 7363 +#define RISCV_PseudoVSEXT_VF2_M1 7364 +#define RISCV_PseudoVSEXT_VF2_M1_MASK 7365 +#define RISCV_PseudoVSEXT_VF2_M2 7366 +#define RISCV_PseudoVSEXT_VF2_M2_MASK 7367 +#define RISCV_PseudoVSEXT_VF2_M4 7368 +#define RISCV_PseudoVSEXT_VF2_M4_MASK 7369 +#define RISCV_PseudoVSEXT_VF2_M8 7370 +#define RISCV_PseudoVSEXT_VF2_M8_MASK 7371 +#define RISCV_PseudoVSEXT_VF2_MF2 7372 +#define RISCV_PseudoVSEXT_VF2_MF2_MASK 7373 +#define RISCV_PseudoVSEXT_VF2_MF4 7374 +#define RISCV_PseudoVSEXT_VF2_MF4_MASK 7375 +#define RISCV_PseudoVSEXT_VF4_M1 7376 +#define RISCV_PseudoVSEXT_VF4_M1_MASK 7377 +#define RISCV_PseudoVSEXT_VF4_M2 7378 +#define RISCV_PseudoVSEXT_VF4_M2_MASK 7379 +#define RISCV_PseudoVSEXT_VF4_M4 7380 +#define RISCV_PseudoVSEXT_VF4_M4_MASK 7381 +#define RISCV_PseudoVSEXT_VF4_M8 7382 +#define RISCV_PseudoVSEXT_VF4_M8_MASK 7383 +#define RISCV_PseudoVSEXT_VF4_MF2 7384 +#define RISCV_PseudoVSEXT_VF4_MF2_MASK 7385 +#define RISCV_PseudoVSEXT_VF8_M1 7386 +#define RISCV_PseudoVSEXT_VF8_M1_MASK 7387 +#define RISCV_PseudoVSEXT_VF8_M2 7388 +#define RISCV_PseudoVSEXT_VF8_M2_MASK 7389 +#define RISCV_PseudoVSEXT_VF8_M4 7390 +#define RISCV_PseudoVSEXT_VF8_M4_MASK 7391 +#define RISCV_PseudoVSEXT_VF8_M8 7392 +#define RISCV_PseudoVSEXT_VF8_M8_MASK 7393 +#define RISCV_PseudoVSLIDE1DOWN_VX_M1 7394 +#define RISCV_PseudoVSLIDE1DOWN_VX_M1_MASK 7395 +#define RISCV_PseudoVSLIDE1DOWN_VX_M2 7396 +#define RISCV_PseudoVSLIDE1DOWN_VX_M2_MASK 7397 +#define RISCV_PseudoVSLIDE1DOWN_VX_M4 7398 +#define RISCV_PseudoVSLIDE1DOWN_VX_M4_MASK 7399 +#define RISCV_PseudoVSLIDE1DOWN_VX_M8 7400 +#define RISCV_PseudoVSLIDE1DOWN_VX_M8_MASK 7401 +#define RISCV_PseudoVSLIDE1DOWN_VX_MF2 7402 +#define RISCV_PseudoVSLIDE1DOWN_VX_MF2_MASK 7403 +#define RISCV_PseudoVSLIDE1DOWN_VX_MF4 7404 +#define RISCV_PseudoVSLIDE1DOWN_VX_MF4_MASK 7405 +#define RISCV_PseudoVSLIDE1DOWN_VX_MF8 7406 +#define RISCV_PseudoVSLIDE1DOWN_VX_MF8_MASK 7407 +#define RISCV_PseudoVSLIDE1UP_VX_M1 7408 +#define RISCV_PseudoVSLIDE1UP_VX_M1_MASK 7409 +#define RISCV_PseudoVSLIDE1UP_VX_M2 7410 +#define RISCV_PseudoVSLIDE1UP_VX_M2_MASK 7411 +#define RISCV_PseudoVSLIDE1UP_VX_M4 7412 +#define RISCV_PseudoVSLIDE1UP_VX_M4_MASK 7413 +#define RISCV_PseudoVSLIDE1UP_VX_M8 7414 +#define RISCV_PseudoVSLIDE1UP_VX_M8_MASK 7415 +#define RISCV_PseudoVSLIDE1UP_VX_MF2 7416 +#define RISCV_PseudoVSLIDE1UP_VX_MF2_MASK 7417 +#define RISCV_PseudoVSLIDE1UP_VX_MF4 7418 +#define RISCV_PseudoVSLIDE1UP_VX_MF4_MASK 7419 +#define RISCV_PseudoVSLIDE1UP_VX_MF8 7420 +#define RISCV_PseudoVSLIDE1UP_VX_MF8_MASK 7421 +#define RISCV_PseudoVSLIDEDOWN_VI_M1 7422 +#define RISCV_PseudoVSLIDEDOWN_VI_M1_MASK 7423 +#define RISCV_PseudoVSLIDEDOWN_VI_M2 7424 +#define RISCV_PseudoVSLIDEDOWN_VI_M2_MASK 7425 +#define RISCV_PseudoVSLIDEDOWN_VI_M4 7426 +#define RISCV_PseudoVSLIDEDOWN_VI_M4_MASK 7427 +#define RISCV_PseudoVSLIDEDOWN_VI_M8 7428 +#define RISCV_PseudoVSLIDEDOWN_VI_M8_MASK 7429 +#define RISCV_PseudoVSLIDEDOWN_VI_MF2 7430 +#define RISCV_PseudoVSLIDEDOWN_VI_MF2_MASK 7431 +#define RISCV_PseudoVSLIDEDOWN_VI_MF4 7432 +#define RISCV_PseudoVSLIDEDOWN_VI_MF4_MASK 7433 +#define RISCV_PseudoVSLIDEDOWN_VI_MF8 7434 +#define RISCV_PseudoVSLIDEDOWN_VI_MF8_MASK 7435 +#define RISCV_PseudoVSLIDEDOWN_VX_M1 7436 +#define RISCV_PseudoVSLIDEDOWN_VX_M1_MASK 7437 +#define RISCV_PseudoVSLIDEDOWN_VX_M2 7438 +#define RISCV_PseudoVSLIDEDOWN_VX_M2_MASK 7439 +#define RISCV_PseudoVSLIDEDOWN_VX_M4 7440 +#define RISCV_PseudoVSLIDEDOWN_VX_M4_MASK 7441 +#define RISCV_PseudoVSLIDEDOWN_VX_M8 7442 +#define RISCV_PseudoVSLIDEDOWN_VX_M8_MASK 7443 +#define RISCV_PseudoVSLIDEDOWN_VX_MF2 7444 +#define RISCV_PseudoVSLIDEDOWN_VX_MF2_MASK 7445 +#define RISCV_PseudoVSLIDEDOWN_VX_MF4 7446 +#define RISCV_PseudoVSLIDEDOWN_VX_MF4_MASK 7447 +#define RISCV_PseudoVSLIDEDOWN_VX_MF8 7448 +#define RISCV_PseudoVSLIDEDOWN_VX_MF8_MASK 7449 +#define RISCV_PseudoVSLIDEUP_VI_M1 7450 +#define RISCV_PseudoVSLIDEUP_VI_M1_MASK 7451 +#define RISCV_PseudoVSLIDEUP_VI_M2 7452 +#define RISCV_PseudoVSLIDEUP_VI_M2_MASK 7453 +#define RISCV_PseudoVSLIDEUP_VI_M4 7454 +#define RISCV_PseudoVSLIDEUP_VI_M4_MASK 7455 +#define RISCV_PseudoVSLIDEUP_VI_M8 7456 +#define RISCV_PseudoVSLIDEUP_VI_M8_MASK 7457 +#define RISCV_PseudoVSLIDEUP_VI_MF2 7458 +#define RISCV_PseudoVSLIDEUP_VI_MF2_MASK 7459 +#define RISCV_PseudoVSLIDEUP_VI_MF4 7460 +#define RISCV_PseudoVSLIDEUP_VI_MF4_MASK 7461 +#define RISCV_PseudoVSLIDEUP_VI_MF8 7462 +#define RISCV_PseudoVSLIDEUP_VI_MF8_MASK 7463 +#define RISCV_PseudoVSLIDEUP_VX_M1 7464 +#define RISCV_PseudoVSLIDEUP_VX_M1_MASK 7465 +#define RISCV_PseudoVSLIDEUP_VX_M2 7466 +#define RISCV_PseudoVSLIDEUP_VX_M2_MASK 7467 +#define RISCV_PseudoVSLIDEUP_VX_M4 7468 +#define RISCV_PseudoVSLIDEUP_VX_M4_MASK 7469 +#define RISCV_PseudoVSLIDEUP_VX_M8 7470 +#define RISCV_PseudoVSLIDEUP_VX_M8_MASK 7471 +#define RISCV_PseudoVSLIDEUP_VX_MF2 7472 +#define RISCV_PseudoVSLIDEUP_VX_MF2_MASK 7473 +#define RISCV_PseudoVSLIDEUP_VX_MF4 7474 +#define RISCV_PseudoVSLIDEUP_VX_MF4_MASK 7475 +#define RISCV_PseudoVSLIDEUP_VX_MF8 7476 +#define RISCV_PseudoVSLIDEUP_VX_MF8_MASK 7477 +#define RISCV_PseudoVSLL_VI_M1 7478 +#define RISCV_PseudoVSLL_VI_M1_MASK 7479 +#define RISCV_PseudoVSLL_VI_M2 7480 +#define RISCV_PseudoVSLL_VI_M2_MASK 7481 +#define RISCV_PseudoVSLL_VI_M4 7482 +#define RISCV_PseudoVSLL_VI_M4_MASK 7483 +#define RISCV_PseudoVSLL_VI_M8 7484 +#define RISCV_PseudoVSLL_VI_M8_MASK 7485 +#define RISCV_PseudoVSLL_VI_MF2 7486 +#define RISCV_PseudoVSLL_VI_MF2_MASK 7487 +#define RISCV_PseudoVSLL_VI_MF4 7488 +#define RISCV_PseudoVSLL_VI_MF4_MASK 7489 +#define RISCV_PseudoVSLL_VI_MF8 7490 +#define RISCV_PseudoVSLL_VI_MF8_MASK 7491 +#define RISCV_PseudoVSLL_VV_M1 7492 +#define RISCV_PseudoVSLL_VV_M1_MASK 7493 +#define RISCV_PseudoVSLL_VV_M2 7494 +#define RISCV_PseudoVSLL_VV_M2_MASK 7495 +#define RISCV_PseudoVSLL_VV_M4 7496 +#define RISCV_PseudoVSLL_VV_M4_MASK 7497 +#define RISCV_PseudoVSLL_VV_M8 7498 +#define RISCV_PseudoVSLL_VV_M8_MASK 7499 +#define RISCV_PseudoVSLL_VV_MF2 7500 +#define RISCV_PseudoVSLL_VV_MF2_MASK 7501 +#define RISCV_PseudoVSLL_VV_MF4 7502 +#define RISCV_PseudoVSLL_VV_MF4_MASK 7503 +#define RISCV_PseudoVSLL_VV_MF8 7504 +#define RISCV_PseudoVSLL_VV_MF8_MASK 7505 +#define RISCV_PseudoVSLL_VX_M1 7506 +#define RISCV_PseudoVSLL_VX_M1_MASK 7507 +#define RISCV_PseudoVSLL_VX_M2 7508 +#define RISCV_PseudoVSLL_VX_M2_MASK 7509 +#define RISCV_PseudoVSLL_VX_M4 7510 +#define RISCV_PseudoVSLL_VX_M4_MASK 7511 +#define RISCV_PseudoVSLL_VX_M8 7512 +#define RISCV_PseudoVSLL_VX_M8_MASK 7513 +#define RISCV_PseudoVSLL_VX_MF2 7514 +#define RISCV_PseudoVSLL_VX_MF2_MASK 7515 +#define RISCV_PseudoVSLL_VX_MF4 7516 +#define RISCV_PseudoVSLL_VX_MF4_MASK 7517 +#define RISCV_PseudoVSLL_VX_MF8 7518 +#define RISCV_PseudoVSLL_VX_MF8_MASK 7519 +#define RISCV_PseudoVSMUL_VV_M1 7520 +#define RISCV_PseudoVSMUL_VV_M1_MASK 7521 +#define RISCV_PseudoVSMUL_VV_M2 7522 +#define RISCV_PseudoVSMUL_VV_M2_MASK 7523 +#define RISCV_PseudoVSMUL_VV_M4 7524 +#define RISCV_PseudoVSMUL_VV_M4_MASK 7525 +#define RISCV_PseudoVSMUL_VV_M8 7526 +#define RISCV_PseudoVSMUL_VV_M8_MASK 7527 +#define RISCV_PseudoVSMUL_VV_MF2 7528 +#define RISCV_PseudoVSMUL_VV_MF2_MASK 7529 +#define RISCV_PseudoVSMUL_VV_MF4 7530 +#define RISCV_PseudoVSMUL_VV_MF4_MASK 7531 +#define RISCV_PseudoVSMUL_VV_MF8 7532 +#define RISCV_PseudoVSMUL_VV_MF8_MASK 7533 +#define RISCV_PseudoVSMUL_VX_M1 7534 +#define RISCV_PseudoVSMUL_VX_M1_MASK 7535 +#define RISCV_PseudoVSMUL_VX_M2 7536 +#define RISCV_PseudoVSMUL_VX_M2_MASK 7537 +#define RISCV_PseudoVSMUL_VX_M4 7538 +#define RISCV_PseudoVSMUL_VX_M4_MASK 7539 +#define RISCV_PseudoVSMUL_VX_M8 7540 +#define RISCV_PseudoVSMUL_VX_M8_MASK 7541 +#define RISCV_PseudoVSMUL_VX_MF2 7542 +#define RISCV_PseudoVSMUL_VX_MF2_MASK 7543 +#define RISCV_PseudoVSMUL_VX_MF4 7544 +#define RISCV_PseudoVSMUL_VX_MF4_MASK 7545 +#define RISCV_PseudoVSMUL_VX_MF8 7546 +#define RISCV_PseudoVSMUL_VX_MF8_MASK 7547 +#define RISCV_PseudoVSM_V_B1 7548 +#define RISCV_PseudoVSM_V_B16 7549 +#define RISCV_PseudoVSM_V_B2 7550 +#define RISCV_PseudoVSM_V_B32 7551 +#define RISCV_PseudoVSM_V_B4 7552 +#define RISCV_PseudoVSM_V_B64 7553 +#define RISCV_PseudoVSM_V_B8 7554 +#define RISCV_PseudoVSOXEI16_V_M1_M1 7555 +#define RISCV_PseudoVSOXEI16_V_M1_M1_MASK 7556 +#define RISCV_PseudoVSOXEI16_V_M1_M2 7557 +#define RISCV_PseudoVSOXEI16_V_M1_M2_MASK 7558 +#define RISCV_PseudoVSOXEI16_V_M1_M4 7559 +#define RISCV_PseudoVSOXEI16_V_M1_M4_MASK 7560 +#define RISCV_PseudoVSOXEI16_V_M1_MF2 7561 +#define RISCV_PseudoVSOXEI16_V_M1_MF2_MASK 7562 +#define RISCV_PseudoVSOXEI16_V_M2_M1 7563 +#define RISCV_PseudoVSOXEI16_V_M2_M1_MASK 7564 +#define RISCV_PseudoVSOXEI16_V_M2_M2 7565 +#define RISCV_PseudoVSOXEI16_V_M2_M2_MASK 7566 +#define RISCV_PseudoVSOXEI16_V_M2_M4 7567 +#define RISCV_PseudoVSOXEI16_V_M2_M4_MASK 7568 +#define RISCV_PseudoVSOXEI16_V_M2_M8 7569 +#define RISCV_PseudoVSOXEI16_V_M2_M8_MASK 7570 +#define RISCV_PseudoVSOXEI16_V_M4_M2 7571 +#define RISCV_PseudoVSOXEI16_V_M4_M2_MASK 7572 +#define RISCV_PseudoVSOXEI16_V_M4_M4 7573 +#define RISCV_PseudoVSOXEI16_V_M4_M4_MASK 7574 +#define RISCV_PseudoVSOXEI16_V_M4_M8 7575 +#define RISCV_PseudoVSOXEI16_V_M4_M8_MASK 7576 +#define RISCV_PseudoVSOXEI16_V_M8_M4 7577 +#define RISCV_PseudoVSOXEI16_V_M8_M4_MASK 7578 +#define RISCV_PseudoVSOXEI16_V_M8_M8 7579 +#define RISCV_PseudoVSOXEI16_V_M8_M8_MASK 7580 +#define RISCV_PseudoVSOXEI16_V_MF2_M1 7581 +#define RISCV_PseudoVSOXEI16_V_MF2_M1_MASK 7582 +#define RISCV_PseudoVSOXEI16_V_MF2_M2 7583 +#define RISCV_PseudoVSOXEI16_V_MF2_M2_MASK 7584 +#define RISCV_PseudoVSOXEI16_V_MF2_MF2 7585 +#define RISCV_PseudoVSOXEI16_V_MF2_MF2_MASK 7586 +#define RISCV_PseudoVSOXEI16_V_MF2_MF4 7587 +#define RISCV_PseudoVSOXEI16_V_MF2_MF4_MASK 7588 +#define RISCV_PseudoVSOXEI16_V_MF4_M1 7589 +#define RISCV_PseudoVSOXEI16_V_MF4_M1_MASK 7590 +#define RISCV_PseudoVSOXEI16_V_MF4_MF2 7591 +#define RISCV_PseudoVSOXEI16_V_MF4_MF2_MASK 7592 +#define RISCV_PseudoVSOXEI16_V_MF4_MF4 7593 +#define RISCV_PseudoVSOXEI16_V_MF4_MF4_MASK 7594 +#define RISCV_PseudoVSOXEI16_V_MF4_MF8 7595 +#define RISCV_PseudoVSOXEI16_V_MF4_MF8_MASK 7596 +#define RISCV_PseudoVSOXEI32_V_M1_M1 7597 +#define RISCV_PseudoVSOXEI32_V_M1_M1_MASK 7598 +#define RISCV_PseudoVSOXEI32_V_M1_M2 7599 +#define RISCV_PseudoVSOXEI32_V_M1_M2_MASK 7600 +#define RISCV_PseudoVSOXEI32_V_M1_MF2 7601 +#define RISCV_PseudoVSOXEI32_V_M1_MF2_MASK 7602 +#define RISCV_PseudoVSOXEI32_V_M1_MF4 7603 +#define RISCV_PseudoVSOXEI32_V_M1_MF4_MASK 7604 +#define RISCV_PseudoVSOXEI32_V_M2_M1 7605 +#define RISCV_PseudoVSOXEI32_V_M2_M1_MASK 7606 +#define RISCV_PseudoVSOXEI32_V_M2_M2 7607 +#define RISCV_PseudoVSOXEI32_V_M2_M2_MASK 7608 +#define RISCV_PseudoVSOXEI32_V_M2_M4 7609 +#define RISCV_PseudoVSOXEI32_V_M2_M4_MASK 7610 +#define RISCV_PseudoVSOXEI32_V_M2_MF2 7611 +#define RISCV_PseudoVSOXEI32_V_M2_MF2_MASK 7612 +#define RISCV_PseudoVSOXEI32_V_M4_M1 7613 +#define RISCV_PseudoVSOXEI32_V_M4_M1_MASK 7614 +#define RISCV_PseudoVSOXEI32_V_M4_M2 7615 +#define RISCV_PseudoVSOXEI32_V_M4_M2_MASK 7616 +#define RISCV_PseudoVSOXEI32_V_M4_M4 7617 +#define RISCV_PseudoVSOXEI32_V_M4_M4_MASK 7618 +#define RISCV_PseudoVSOXEI32_V_M4_M8 7619 +#define RISCV_PseudoVSOXEI32_V_M4_M8_MASK 7620 +#define RISCV_PseudoVSOXEI32_V_M8_M2 7621 +#define RISCV_PseudoVSOXEI32_V_M8_M2_MASK 7622 +#define RISCV_PseudoVSOXEI32_V_M8_M4 7623 +#define RISCV_PseudoVSOXEI32_V_M8_M4_MASK 7624 +#define RISCV_PseudoVSOXEI32_V_M8_M8 7625 +#define RISCV_PseudoVSOXEI32_V_M8_M8_MASK 7626 +#define RISCV_PseudoVSOXEI32_V_MF2_M1 7627 +#define RISCV_PseudoVSOXEI32_V_MF2_M1_MASK 7628 +#define RISCV_PseudoVSOXEI32_V_MF2_MF2 7629 +#define RISCV_PseudoVSOXEI32_V_MF2_MF2_MASK 7630 +#define RISCV_PseudoVSOXEI32_V_MF2_MF4 7631 +#define RISCV_PseudoVSOXEI32_V_MF2_MF4_MASK 7632 +#define RISCV_PseudoVSOXEI32_V_MF2_MF8 7633 +#define RISCV_PseudoVSOXEI32_V_MF2_MF8_MASK 7634 +#define RISCV_PseudoVSOXEI64_V_M1_M1 7635 +#define RISCV_PseudoVSOXEI64_V_M1_M1_MASK 7636 +#define RISCV_PseudoVSOXEI64_V_M1_MF2 7637 +#define RISCV_PseudoVSOXEI64_V_M1_MF2_MASK 7638 +#define RISCV_PseudoVSOXEI64_V_M1_MF4 7639 +#define RISCV_PseudoVSOXEI64_V_M1_MF4_MASK 7640 +#define RISCV_PseudoVSOXEI64_V_M1_MF8 7641 +#define RISCV_PseudoVSOXEI64_V_M1_MF8_MASK 7642 +#define RISCV_PseudoVSOXEI64_V_M2_M1 7643 +#define RISCV_PseudoVSOXEI64_V_M2_M1_MASK 7644 +#define RISCV_PseudoVSOXEI64_V_M2_M2 7645 +#define RISCV_PseudoVSOXEI64_V_M2_M2_MASK 7646 +#define RISCV_PseudoVSOXEI64_V_M2_MF2 7647 +#define RISCV_PseudoVSOXEI64_V_M2_MF2_MASK 7648 +#define RISCV_PseudoVSOXEI64_V_M2_MF4 7649 +#define RISCV_PseudoVSOXEI64_V_M2_MF4_MASK 7650 +#define RISCV_PseudoVSOXEI64_V_M4_M1 7651 +#define RISCV_PseudoVSOXEI64_V_M4_M1_MASK 7652 +#define RISCV_PseudoVSOXEI64_V_M4_M2 7653 +#define RISCV_PseudoVSOXEI64_V_M4_M2_MASK 7654 +#define RISCV_PseudoVSOXEI64_V_M4_M4 7655 +#define RISCV_PseudoVSOXEI64_V_M4_M4_MASK 7656 +#define RISCV_PseudoVSOXEI64_V_M4_MF2 7657 +#define RISCV_PseudoVSOXEI64_V_M4_MF2_MASK 7658 +#define RISCV_PseudoVSOXEI64_V_M8_M1 7659 +#define RISCV_PseudoVSOXEI64_V_M8_M1_MASK 7660 +#define RISCV_PseudoVSOXEI64_V_M8_M2 7661 +#define RISCV_PseudoVSOXEI64_V_M8_M2_MASK 7662 +#define RISCV_PseudoVSOXEI64_V_M8_M4 7663 +#define RISCV_PseudoVSOXEI64_V_M8_M4_MASK 7664 +#define RISCV_PseudoVSOXEI64_V_M8_M8 7665 +#define RISCV_PseudoVSOXEI64_V_M8_M8_MASK 7666 +#define RISCV_PseudoVSOXEI8_V_M1_M1 7667 +#define RISCV_PseudoVSOXEI8_V_M1_M1_MASK 7668 +#define RISCV_PseudoVSOXEI8_V_M1_M2 7669 +#define RISCV_PseudoVSOXEI8_V_M1_M2_MASK 7670 +#define RISCV_PseudoVSOXEI8_V_M1_M4 7671 +#define RISCV_PseudoVSOXEI8_V_M1_M4_MASK 7672 +#define RISCV_PseudoVSOXEI8_V_M1_M8 7673 +#define RISCV_PseudoVSOXEI8_V_M1_M8_MASK 7674 +#define RISCV_PseudoVSOXEI8_V_M2_M2 7675 +#define RISCV_PseudoVSOXEI8_V_M2_M2_MASK 7676 +#define RISCV_PseudoVSOXEI8_V_M2_M4 7677 +#define RISCV_PseudoVSOXEI8_V_M2_M4_MASK 7678 +#define RISCV_PseudoVSOXEI8_V_M2_M8 7679 +#define RISCV_PseudoVSOXEI8_V_M2_M8_MASK 7680 +#define RISCV_PseudoVSOXEI8_V_M4_M4 7681 +#define RISCV_PseudoVSOXEI8_V_M4_M4_MASK 7682 +#define RISCV_PseudoVSOXEI8_V_M4_M8 7683 +#define RISCV_PseudoVSOXEI8_V_M4_M8_MASK 7684 +#define RISCV_PseudoVSOXEI8_V_M8_M8 7685 +#define RISCV_PseudoVSOXEI8_V_M8_M8_MASK 7686 +#define RISCV_PseudoVSOXEI8_V_MF2_M1 7687 +#define RISCV_PseudoVSOXEI8_V_MF2_M1_MASK 7688 +#define RISCV_PseudoVSOXEI8_V_MF2_M2 7689 +#define RISCV_PseudoVSOXEI8_V_MF2_M2_MASK 7690 +#define RISCV_PseudoVSOXEI8_V_MF2_M4 7691 +#define RISCV_PseudoVSOXEI8_V_MF2_M4_MASK 7692 +#define RISCV_PseudoVSOXEI8_V_MF2_MF2 7693 +#define RISCV_PseudoVSOXEI8_V_MF2_MF2_MASK 7694 +#define RISCV_PseudoVSOXEI8_V_MF4_M1 7695 +#define RISCV_PseudoVSOXEI8_V_MF4_M1_MASK 7696 +#define RISCV_PseudoVSOXEI8_V_MF4_M2 7697 +#define RISCV_PseudoVSOXEI8_V_MF4_M2_MASK 7698 +#define RISCV_PseudoVSOXEI8_V_MF4_MF2 7699 +#define RISCV_PseudoVSOXEI8_V_MF4_MF2_MASK 7700 +#define RISCV_PseudoVSOXEI8_V_MF4_MF4 7701 +#define RISCV_PseudoVSOXEI8_V_MF4_MF4_MASK 7702 +#define RISCV_PseudoVSOXEI8_V_MF8_M1 7703 +#define RISCV_PseudoVSOXEI8_V_MF8_M1_MASK 7704 +#define RISCV_PseudoVSOXEI8_V_MF8_MF2 7705 +#define RISCV_PseudoVSOXEI8_V_MF8_MF2_MASK 7706 +#define RISCV_PseudoVSOXEI8_V_MF8_MF4 7707 +#define RISCV_PseudoVSOXEI8_V_MF8_MF4_MASK 7708 +#define RISCV_PseudoVSOXEI8_V_MF8_MF8 7709 +#define RISCV_PseudoVSOXEI8_V_MF8_MF8_MASK 7710 +#define RISCV_PseudoVSOXSEG2EI16_V_M1_M1 7711 +#define RISCV_PseudoVSOXSEG2EI16_V_M1_M1_MASK 7712 +#define RISCV_PseudoVSOXSEG2EI16_V_M1_M2 7713 +#define RISCV_PseudoVSOXSEG2EI16_V_M1_M2_MASK 7714 +#define RISCV_PseudoVSOXSEG2EI16_V_M1_M4 7715 +#define RISCV_PseudoVSOXSEG2EI16_V_M1_M4_MASK 7716 +#define RISCV_PseudoVSOXSEG2EI16_V_M1_MF2 7717 +#define RISCV_PseudoVSOXSEG2EI16_V_M1_MF2_MASK 7718 +#define RISCV_PseudoVSOXSEG2EI16_V_M2_M1 7719 +#define RISCV_PseudoVSOXSEG2EI16_V_M2_M1_MASK 7720 +#define RISCV_PseudoVSOXSEG2EI16_V_M2_M2 7721 +#define RISCV_PseudoVSOXSEG2EI16_V_M2_M2_MASK 7722 +#define RISCV_PseudoVSOXSEG2EI16_V_M2_M4 7723 +#define RISCV_PseudoVSOXSEG2EI16_V_M2_M4_MASK 7724 +#define RISCV_PseudoVSOXSEG2EI16_V_M4_M2 7725 +#define RISCV_PseudoVSOXSEG2EI16_V_M4_M2_MASK 7726 +#define RISCV_PseudoVSOXSEG2EI16_V_M4_M4 7727 +#define RISCV_PseudoVSOXSEG2EI16_V_M4_M4_MASK 7728 +#define RISCV_PseudoVSOXSEG2EI16_V_M8_M4 7729 +#define RISCV_PseudoVSOXSEG2EI16_V_M8_M4_MASK 7730 +#define RISCV_PseudoVSOXSEG2EI16_V_MF2_M1 7731 +#define RISCV_PseudoVSOXSEG2EI16_V_MF2_M1_MASK 7732 +#define RISCV_PseudoVSOXSEG2EI16_V_MF2_M2 7733 +#define RISCV_PseudoVSOXSEG2EI16_V_MF2_M2_MASK 7734 +#define RISCV_PseudoVSOXSEG2EI16_V_MF2_MF2 7735 +#define RISCV_PseudoVSOXSEG2EI16_V_MF2_MF2_MASK 7736 +#define RISCV_PseudoVSOXSEG2EI16_V_MF2_MF4 7737 +#define RISCV_PseudoVSOXSEG2EI16_V_MF2_MF4_MASK 7738 +#define RISCV_PseudoVSOXSEG2EI16_V_MF4_M1 7739 +#define RISCV_PseudoVSOXSEG2EI16_V_MF4_M1_MASK 7740 +#define RISCV_PseudoVSOXSEG2EI16_V_MF4_MF2 7741 +#define RISCV_PseudoVSOXSEG2EI16_V_MF4_MF2_MASK 7742 +#define RISCV_PseudoVSOXSEG2EI16_V_MF4_MF4 7743 +#define RISCV_PseudoVSOXSEG2EI16_V_MF4_MF4_MASK 7744 +#define RISCV_PseudoVSOXSEG2EI16_V_MF4_MF8 7745 +#define RISCV_PseudoVSOXSEG2EI16_V_MF4_MF8_MASK 7746 +#define RISCV_PseudoVSOXSEG2EI32_V_M1_M1 7747 +#define RISCV_PseudoVSOXSEG2EI32_V_M1_M1_MASK 7748 +#define RISCV_PseudoVSOXSEG2EI32_V_M1_M2 7749 +#define RISCV_PseudoVSOXSEG2EI32_V_M1_M2_MASK 7750 +#define RISCV_PseudoVSOXSEG2EI32_V_M1_MF2 7751 +#define RISCV_PseudoVSOXSEG2EI32_V_M1_MF2_MASK 7752 +#define RISCV_PseudoVSOXSEG2EI32_V_M1_MF4 7753 +#define RISCV_PseudoVSOXSEG2EI32_V_M1_MF4_MASK 7754 +#define RISCV_PseudoVSOXSEG2EI32_V_M2_M1 7755 +#define RISCV_PseudoVSOXSEG2EI32_V_M2_M1_MASK 7756 +#define RISCV_PseudoVSOXSEG2EI32_V_M2_M2 7757 +#define RISCV_PseudoVSOXSEG2EI32_V_M2_M2_MASK 7758 +#define RISCV_PseudoVSOXSEG2EI32_V_M2_M4 7759 +#define RISCV_PseudoVSOXSEG2EI32_V_M2_M4_MASK 7760 +#define RISCV_PseudoVSOXSEG2EI32_V_M2_MF2 7761 +#define RISCV_PseudoVSOXSEG2EI32_V_M2_MF2_MASK 7762 +#define RISCV_PseudoVSOXSEG2EI32_V_M4_M1 7763 +#define RISCV_PseudoVSOXSEG2EI32_V_M4_M1_MASK 7764 +#define RISCV_PseudoVSOXSEG2EI32_V_M4_M2 7765 +#define RISCV_PseudoVSOXSEG2EI32_V_M4_M2_MASK 7766 +#define RISCV_PseudoVSOXSEG2EI32_V_M4_M4 7767 +#define RISCV_PseudoVSOXSEG2EI32_V_M4_M4_MASK 7768 +#define RISCV_PseudoVSOXSEG2EI32_V_M8_M2 7769 +#define RISCV_PseudoVSOXSEG2EI32_V_M8_M2_MASK 7770 +#define RISCV_PseudoVSOXSEG2EI32_V_M8_M4 7771 +#define RISCV_PseudoVSOXSEG2EI32_V_M8_M4_MASK 7772 +#define RISCV_PseudoVSOXSEG2EI32_V_MF2_M1 7773 +#define RISCV_PseudoVSOXSEG2EI32_V_MF2_M1_MASK 7774 +#define RISCV_PseudoVSOXSEG2EI32_V_MF2_MF2 7775 +#define RISCV_PseudoVSOXSEG2EI32_V_MF2_MF2_MASK 7776 +#define RISCV_PseudoVSOXSEG2EI32_V_MF2_MF4 7777 +#define RISCV_PseudoVSOXSEG2EI32_V_MF2_MF4_MASK 7778 +#define RISCV_PseudoVSOXSEG2EI32_V_MF2_MF8 7779 +#define RISCV_PseudoVSOXSEG2EI32_V_MF2_MF8_MASK 7780 +#define RISCV_PseudoVSOXSEG2EI64_V_M1_M1 7781 +#define RISCV_PseudoVSOXSEG2EI64_V_M1_M1_MASK 7782 +#define RISCV_PseudoVSOXSEG2EI64_V_M1_MF2 7783 +#define RISCV_PseudoVSOXSEG2EI64_V_M1_MF2_MASK 7784 +#define RISCV_PseudoVSOXSEG2EI64_V_M1_MF4 7785 +#define RISCV_PseudoVSOXSEG2EI64_V_M1_MF4_MASK 7786 +#define RISCV_PseudoVSOXSEG2EI64_V_M1_MF8 7787 +#define RISCV_PseudoVSOXSEG2EI64_V_M1_MF8_MASK 7788 +#define RISCV_PseudoVSOXSEG2EI64_V_M2_M1 7789 +#define RISCV_PseudoVSOXSEG2EI64_V_M2_M1_MASK 7790 +#define RISCV_PseudoVSOXSEG2EI64_V_M2_M2 7791 +#define RISCV_PseudoVSOXSEG2EI64_V_M2_M2_MASK 7792 +#define RISCV_PseudoVSOXSEG2EI64_V_M2_MF2 7793 +#define RISCV_PseudoVSOXSEG2EI64_V_M2_MF2_MASK 7794 +#define RISCV_PseudoVSOXSEG2EI64_V_M2_MF4 7795 +#define RISCV_PseudoVSOXSEG2EI64_V_M2_MF4_MASK 7796 +#define RISCV_PseudoVSOXSEG2EI64_V_M4_M1 7797 +#define RISCV_PseudoVSOXSEG2EI64_V_M4_M1_MASK 7798 +#define RISCV_PseudoVSOXSEG2EI64_V_M4_M2 7799 +#define RISCV_PseudoVSOXSEG2EI64_V_M4_M2_MASK 7800 +#define RISCV_PseudoVSOXSEG2EI64_V_M4_M4 7801 +#define RISCV_PseudoVSOXSEG2EI64_V_M4_M4_MASK 7802 +#define RISCV_PseudoVSOXSEG2EI64_V_M4_MF2 7803 +#define RISCV_PseudoVSOXSEG2EI64_V_M4_MF2_MASK 7804 +#define RISCV_PseudoVSOXSEG2EI64_V_M8_M1 7805 +#define RISCV_PseudoVSOXSEG2EI64_V_M8_M1_MASK 7806 +#define RISCV_PseudoVSOXSEG2EI64_V_M8_M2 7807 +#define RISCV_PseudoVSOXSEG2EI64_V_M8_M2_MASK 7808 +#define RISCV_PseudoVSOXSEG2EI64_V_M8_M4 7809 +#define RISCV_PseudoVSOXSEG2EI64_V_M8_M4_MASK 7810 +#define RISCV_PseudoVSOXSEG2EI8_V_M1_M1 7811 +#define RISCV_PseudoVSOXSEG2EI8_V_M1_M1_MASK 7812 +#define RISCV_PseudoVSOXSEG2EI8_V_M1_M2 7813 +#define RISCV_PseudoVSOXSEG2EI8_V_M1_M2_MASK 7814 +#define RISCV_PseudoVSOXSEG2EI8_V_M1_M4 7815 +#define RISCV_PseudoVSOXSEG2EI8_V_M1_M4_MASK 7816 +#define RISCV_PseudoVSOXSEG2EI8_V_M2_M2 7817 +#define RISCV_PseudoVSOXSEG2EI8_V_M2_M2_MASK 7818 +#define RISCV_PseudoVSOXSEG2EI8_V_M2_M4 7819 +#define RISCV_PseudoVSOXSEG2EI8_V_M2_M4_MASK 7820 +#define RISCV_PseudoVSOXSEG2EI8_V_M4_M4 7821 +#define RISCV_PseudoVSOXSEG2EI8_V_M4_M4_MASK 7822 +#define RISCV_PseudoVSOXSEG2EI8_V_MF2_M1 7823 +#define RISCV_PseudoVSOXSEG2EI8_V_MF2_M1_MASK 7824 +#define RISCV_PseudoVSOXSEG2EI8_V_MF2_M2 7825 +#define RISCV_PseudoVSOXSEG2EI8_V_MF2_M2_MASK 7826 +#define RISCV_PseudoVSOXSEG2EI8_V_MF2_M4 7827 +#define RISCV_PseudoVSOXSEG2EI8_V_MF2_M4_MASK 7828 +#define RISCV_PseudoVSOXSEG2EI8_V_MF2_MF2 7829 +#define RISCV_PseudoVSOXSEG2EI8_V_MF2_MF2_MASK 7830 +#define RISCV_PseudoVSOXSEG2EI8_V_MF4_M1 7831 +#define RISCV_PseudoVSOXSEG2EI8_V_MF4_M1_MASK 7832 +#define RISCV_PseudoVSOXSEG2EI8_V_MF4_M2 7833 +#define RISCV_PseudoVSOXSEG2EI8_V_MF4_M2_MASK 7834 +#define RISCV_PseudoVSOXSEG2EI8_V_MF4_MF2 7835 +#define RISCV_PseudoVSOXSEG2EI8_V_MF4_MF2_MASK 7836 +#define RISCV_PseudoVSOXSEG2EI8_V_MF4_MF4 7837 +#define RISCV_PseudoVSOXSEG2EI8_V_MF4_MF4_MASK 7838 +#define RISCV_PseudoVSOXSEG2EI8_V_MF8_M1 7839 +#define RISCV_PseudoVSOXSEG2EI8_V_MF8_M1_MASK 7840 +#define RISCV_PseudoVSOXSEG2EI8_V_MF8_MF2 7841 +#define RISCV_PseudoVSOXSEG2EI8_V_MF8_MF2_MASK 7842 +#define RISCV_PseudoVSOXSEG2EI8_V_MF8_MF4 7843 +#define RISCV_PseudoVSOXSEG2EI8_V_MF8_MF4_MASK 7844 +#define RISCV_PseudoVSOXSEG2EI8_V_MF8_MF8 7845 +#define RISCV_PseudoVSOXSEG2EI8_V_MF8_MF8_MASK 7846 +#define RISCV_PseudoVSOXSEG3EI16_V_M1_M1 7847 +#define RISCV_PseudoVSOXSEG3EI16_V_M1_M1_MASK 7848 +#define RISCV_PseudoVSOXSEG3EI16_V_M1_M2 7849 +#define RISCV_PseudoVSOXSEG3EI16_V_M1_M2_MASK 7850 +#define RISCV_PseudoVSOXSEG3EI16_V_M1_MF2 7851 +#define RISCV_PseudoVSOXSEG3EI16_V_M1_MF2_MASK 7852 +#define RISCV_PseudoVSOXSEG3EI16_V_M2_M1 7853 +#define RISCV_PseudoVSOXSEG3EI16_V_M2_M1_MASK 7854 +#define RISCV_PseudoVSOXSEG3EI16_V_M2_M2 7855 +#define RISCV_PseudoVSOXSEG3EI16_V_M2_M2_MASK 7856 +#define RISCV_PseudoVSOXSEG3EI16_V_M4_M2 7857 +#define RISCV_PseudoVSOXSEG3EI16_V_M4_M2_MASK 7858 +#define RISCV_PseudoVSOXSEG3EI16_V_MF2_M1 7859 +#define RISCV_PseudoVSOXSEG3EI16_V_MF2_M1_MASK 7860 +#define RISCV_PseudoVSOXSEG3EI16_V_MF2_M2 7861 +#define RISCV_PseudoVSOXSEG3EI16_V_MF2_M2_MASK 7862 +#define RISCV_PseudoVSOXSEG3EI16_V_MF2_MF2 7863 +#define RISCV_PseudoVSOXSEG3EI16_V_MF2_MF2_MASK 7864 +#define RISCV_PseudoVSOXSEG3EI16_V_MF2_MF4 7865 +#define RISCV_PseudoVSOXSEG3EI16_V_MF2_MF4_MASK 7866 +#define RISCV_PseudoVSOXSEG3EI16_V_MF4_M1 7867 +#define RISCV_PseudoVSOXSEG3EI16_V_MF4_M1_MASK 7868 +#define RISCV_PseudoVSOXSEG3EI16_V_MF4_MF2 7869 +#define RISCV_PseudoVSOXSEG3EI16_V_MF4_MF2_MASK 7870 +#define RISCV_PseudoVSOXSEG3EI16_V_MF4_MF4 7871 +#define RISCV_PseudoVSOXSEG3EI16_V_MF4_MF4_MASK 7872 +#define RISCV_PseudoVSOXSEG3EI16_V_MF4_MF8 7873 +#define RISCV_PseudoVSOXSEG3EI16_V_MF4_MF8_MASK 7874 +#define RISCV_PseudoVSOXSEG3EI32_V_M1_M1 7875 +#define RISCV_PseudoVSOXSEG3EI32_V_M1_M1_MASK 7876 +#define RISCV_PseudoVSOXSEG3EI32_V_M1_M2 7877 +#define RISCV_PseudoVSOXSEG3EI32_V_M1_M2_MASK 7878 +#define RISCV_PseudoVSOXSEG3EI32_V_M1_MF2 7879 +#define RISCV_PseudoVSOXSEG3EI32_V_M1_MF2_MASK 7880 +#define RISCV_PseudoVSOXSEG3EI32_V_M1_MF4 7881 +#define RISCV_PseudoVSOXSEG3EI32_V_M1_MF4_MASK 7882 +#define RISCV_PseudoVSOXSEG3EI32_V_M2_M1 7883 +#define RISCV_PseudoVSOXSEG3EI32_V_M2_M1_MASK 7884 +#define RISCV_PseudoVSOXSEG3EI32_V_M2_M2 7885 +#define RISCV_PseudoVSOXSEG3EI32_V_M2_M2_MASK 7886 +#define RISCV_PseudoVSOXSEG3EI32_V_M2_MF2 7887 +#define RISCV_PseudoVSOXSEG3EI32_V_M2_MF2_MASK 7888 +#define RISCV_PseudoVSOXSEG3EI32_V_M4_M1 7889 +#define RISCV_PseudoVSOXSEG3EI32_V_M4_M1_MASK 7890 +#define RISCV_PseudoVSOXSEG3EI32_V_M4_M2 7891 +#define RISCV_PseudoVSOXSEG3EI32_V_M4_M2_MASK 7892 +#define RISCV_PseudoVSOXSEG3EI32_V_M8_M2 7893 +#define RISCV_PseudoVSOXSEG3EI32_V_M8_M2_MASK 7894 +#define RISCV_PseudoVSOXSEG3EI32_V_MF2_M1 7895 +#define RISCV_PseudoVSOXSEG3EI32_V_MF2_M1_MASK 7896 +#define RISCV_PseudoVSOXSEG3EI32_V_MF2_MF2 7897 +#define RISCV_PseudoVSOXSEG3EI32_V_MF2_MF2_MASK 7898 +#define RISCV_PseudoVSOXSEG3EI32_V_MF2_MF4 7899 +#define RISCV_PseudoVSOXSEG3EI32_V_MF2_MF4_MASK 7900 +#define RISCV_PseudoVSOXSEG3EI32_V_MF2_MF8 7901 +#define RISCV_PseudoVSOXSEG3EI32_V_MF2_MF8_MASK 7902 +#define RISCV_PseudoVSOXSEG3EI64_V_M1_M1 7903 +#define RISCV_PseudoVSOXSEG3EI64_V_M1_M1_MASK 7904 +#define RISCV_PseudoVSOXSEG3EI64_V_M1_MF2 7905 +#define RISCV_PseudoVSOXSEG3EI64_V_M1_MF2_MASK 7906 +#define RISCV_PseudoVSOXSEG3EI64_V_M1_MF4 7907 +#define RISCV_PseudoVSOXSEG3EI64_V_M1_MF4_MASK 7908 +#define RISCV_PseudoVSOXSEG3EI64_V_M1_MF8 7909 +#define RISCV_PseudoVSOXSEG3EI64_V_M1_MF8_MASK 7910 +#define RISCV_PseudoVSOXSEG3EI64_V_M2_M1 7911 +#define RISCV_PseudoVSOXSEG3EI64_V_M2_M1_MASK 7912 +#define RISCV_PseudoVSOXSEG3EI64_V_M2_M2 7913 +#define RISCV_PseudoVSOXSEG3EI64_V_M2_M2_MASK 7914 +#define RISCV_PseudoVSOXSEG3EI64_V_M2_MF2 7915 +#define RISCV_PseudoVSOXSEG3EI64_V_M2_MF2_MASK 7916 +#define RISCV_PseudoVSOXSEG3EI64_V_M2_MF4 7917 +#define RISCV_PseudoVSOXSEG3EI64_V_M2_MF4_MASK 7918 +#define RISCV_PseudoVSOXSEG3EI64_V_M4_M1 7919 +#define RISCV_PseudoVSOXSEG3EI64_V_M4_M1_MASK 7920 +#define RISCV_PseudoVSOXSEG3EI64_V_M4_M2 7921 +#define RISCV_PseudoVSOXSEG3EI64_V_M4_M2_MASK 7922 +#define RISCV_PseudoVSOXSEG3EI64_V_M4_MF2 7923 +#define RISCV_PseudoVSOXSEG3EI64_V_M4_MF2_MASK 7924 +#define RISCV_PseudoVSOXSEG3EI64_V_M8_M1 7925 +#define RISCV_PseudoVSOXSEG3EI64_V_M8_M1_MASK 7926 +#define RISCV_PseudoVSOXSEG3EI64_V_M8_M2 7927 +#define RISCV_PseudoVSOXSEG3EI64_V_M8_M2_MASK 7928 +#define RISCV_PseudoVSOXSEG3EI8_V_M1_M1 7929 +#define RISCV_PseudoVSOXSEG3EI8_V_M1_M1_MASK 7930 +#define RISCV_PseudoVSOXSEG3EI8_V_M1_M2 7931 +#define RISCV_PseudoVSOXSEG3EI8_V_M1_M2_MASK 7932 +#define RISCV_PseudoVSOXSEG3EI8_V_M2_M2 7933 +#define RISCV_PseudoVSOXSEG3EI8_V_M2_M2_MASK 7934 +#define RISCV_PseudoVSOXSEG3EI8_V_MF2_M1 7935 +#define RISCV_PseudoVSOXSEG3EI8_V_MF2_M1_MASK 7936 +#define RISCV_PseudoVSOXSEG3EI8_V_MF2_M2 7937 +#define RISCV_PseudoVSOXSEG3EI8_V_MF2_M2_MASK 7938 +#define RISCV_PseudoVSOXSEG3EI8_V_MF2_MF2 7939 +#define RISCV_PseudoVSOXSEG3EI8_V_MF2_MF2_MASK 7940 +#define RISCV_PseudoVSOXSEG3EI8_V_MF4_M1 7941 +#define RISCV_PseudoVSOXSEG3EI8_V_MF4_M1_MASK 7942 +#define RISCV_PseudoVSOXSEG3EI8_V_MF4_M2 7943 +#define RISCV_PseudoVSOXSEG3EI8_V_MF4_M2_MASK 7944 +#define RISCV_PseudoVSOXSEG3EI8_V_MF4_MF2 7945 +#define RISCV_PseudoVSOXSEG3EI8_V_MF4_MF2_MASK 7946 +#define RISCV_PseudoVSOXSEG3EI8_V_MF4_MF4 7947 +#define RISCV_PseudoVSOXSEG3EI8_V_MF4_MF4_MASK 7948 +#define RISCV_PseudoVSOXSEG3EI8_V_MF8_M1 7949 +#define RISCV_PseudoVSOXSEG3EI8_V_MF8_M1_MASK 7950 +#define RISCV_PseudoVSOXSEG3EI8_V_MF8_MF2 7951 +#define RISCV_PseudoVSOXSEG3EI8_V_MF8_MF2_MASK 7952 +#define RISCV_PseudoVSOXSEG3EI8_V_MF8_MF4 7953 +#define RISCV_PseudoVSOXSEG3EI8_V_MF8_MF4_MASK 7954 +#define RISCV_PseudoVSOXSEG3EI8_V_MF8_MF8 7955 +#define RISCV_PseudoVSOXSEG3EI8_V_MF8_MF8_MASK 7956 +#define RISCV_PseudoVSOXSEG4EI16_V_M1_M1 7957 +#define RISCV_PseudoVSOXSEG4EI16_V_M1_M1_MASK 7958 +#define RISCV_PseudoVSOXSEG4EI16_V_M1_M2 7959 +#define RISCV_PseudoVSOXSEG4EI16_V_M1_M2_MASK 7960 +#define RISCV_PseudoVSOXSEG4EI16_V_M1_MF2 7961 +#define RISCV_PseudoVSOXSEG4EI16_V_M1_MF2_MASK 7962 +#define RISCV_PseudoVSOXSEG4EI16_V_M2_M1 7963 +#define RISCV_PseudoVSOXSEG4EI16_V_M2_M1_MASK 7964 +#define RISCV_PseudoVSOXSEG4EI16_V_M2_M2 7965 +#define RISCV_PseudoVSOXSEG4EI16_V_M2_M2_MASK 7966 +#define RISCV_PseudoVSOXSEG4EI16_V_M4_M2 7967 +#define RISCV_PseudoVSOXSEG4EI16_V_M4_M2_MASK 7968 +#define RISCV_PseudoVSOXSEG4EI16_V_MF2_M1 7969 +#define RISCV_PseudoVSOXSEG4EI16_V_MF2_M1_MASK 7970 +#define RISCV_PseudoVSOXSEG4EI16_V_MF2_M2 7971 +#define RISCV_PseudoVSOXSEG4EI16_V_MF2_M2_MASK 7972 +#define RISCV_PseudoVSOXSEG4EI16_V_MF2_MF2 7973 +#define RISCV_PseudoVSOXSEG4EI16_V_MF2_MF2_MASK 7974 +#define RISCV_PseudoVSOXSEG4EI16_V_MF2_MF4 7975 +#define RISCV_PseudoVSOXSEG4EI16_V_MF2_MF4_MASK 7976 +#define RISCV_PseudoVSOXSEG4EI16_V_MF4_M1 7977 +#define RISCV_PseudoVSOXSEG4EI16_V_MF4_M1_MASK 7978 +#define RISCV_PseudoVSOXSEG4EI16_V_MF4_MF2 7979 +#define RISCV_PseudoVSOXSEG4EI16_V_MF4_MF2_MASK 7980 +#define RISCV_PseudoVSOXSEG4EI16_V_MF4_MF4 7981 +#define RISCV_PseudoVSOXSEG4EI16_V_MF4_MF4_MASK 7982 +#define RISCV_PseudoVSOXSEG4EI16_V_MF4_MF8 7983 +#define RISCV_PseudoVSOXSEG4EI16_V_MF4_MF8_MASK 7984 +#define RISCV_PseudoVSOXSEG4EI32_V_M1_M1 7985 +#define RISCV_PseudoVSOXSEG4EI32_V_M1_M1_MASK 7986 +#define RISCV_PseudoVSOXSEG4EI32_V_M1_M2 7987 +#define RISCV_PseudoVSOXSEG4EI32_V_M1_M2_MASK 7988 +#define RISCV_PseudoVSOXSEG4EI32_V_M1_MF2 7989 +#define RISCV_PseudoVSOXSEG4EI32_V_M1_MF2_MASK 7990 +#define RISCV_PseudoVSOXSEG4EI32_V_M1_MF4 7991 +#define RISCV_PseudoVSOXSEG4EI32_V_M1_MF4_MASK 7992 +#define RISCV_PseudoVSOXSEG4EI32_V_M2_M1 7993 +#define RISCV_PseudoVSOXSEG4EI32_V_M2_M1_MASK 7994 +#define RISCV_PseudoVSOXSEG4EI32_V_M2_M2 7995 +#define RISCV_PseudoVSOXSEG4EI32_V_M2_M2_MASK 7996 +#define RISCV_PseudoVSOXSEG4EI32_V_M2_MF2 7997 +#define RISCV_PseudoVSOXSEG4EI32_V_M2_MF2_MASK 7998 +#define RISCV_PseudoVSOXSEG4EI32_V_M4_M1 7999 +#define RISCV_PseudoVSOXSEG4EI32_V_M4_M1_MASK 8000 +#define RISCV_PseudoVSOXSEG4EI32_V_M4_M2 8001 +#define RISCV_PseudoVSOXSEG4EI32_V_M4_M2_MASK 8002 +#define RISCV_PseudoVSOXSEG4EI32_V_M8_M2 8003 +#define RISCV_PseudoVSOXSEG4EI32_V_M8_M2_MASK 8004 +#define RISCV_PseudoVSOXSEG4EI32_V_MF2_M1 8005 +#define RISCV_PseudoVSOXSEG4EI32_V_MF2_M1_MASK 8006 +#define RISCV_PseudoVSOXSEG4EI32_V_MF2_MF2 8007 +#define RISCV_PseudoVSOXSEG4EI32_V_MF2_MF2_MASK 8008 +#define RISCV_PseudoVSOXSEG4EI32_V_MF2_MF4 8009 +#define RISCV_PseudoVSOXSEG4EI32_V_MF2_MF4_MASK 8010 +#define RISCV_PseudoVSOXSEG4EI32_V_MF2_MF8 8011 +#define RISCV_PseudoVSOXSEG4EI32_V_MF2_MF8_MASK 8012 +#define RISCV_PseudoVSOXSEG4EI64_V_M1_M1 8013 +#define RISCV_PseudoVSOXSEG4EI64_V_M1_M1_MASK 8014 +#define RISCV_PseudoVSOXSEG4EI64_V_M1_MF2 8015 +#define RISCV_PseudoVSOXSEG4EI64_V_M1_MF2_MASK 8016 +#define RISCV_PseudoVSOXSEG4EI64_V_M1_MF4 8017 +#define RISCV_PseudoVSOXSEG4EI64_V_M1_MF4_MASK 8018 +#define RISCV_PseudoVSOXSEG4EI64_V_M1_MF8 8019 +#define RISCV_PseudoVSOXSEG4EI64_V_M1_MF8_MASK 8020 +#define RISCV_PseudoVSOXSEG4EI64_V_M2_M1 8021 +#define RISCV_PseudoVSOXSEG4EI64_V_M2_M1_MASK 8022 +#define RISCV_PseudoVSOXSEG4EI64_V_M2_M2 8023 +#define RISCV_PseudoVSOXSEG4EI64_V_M2_M2_MASK 8024 +#define RISCV_PseudoVSOXSEG4EI64_V_M2_MF2 8025 +#define RISCV_PseudoVSOXSEG4EI64_V_M2_MF2_MASK 8026 +#define RISCV_PseudoVSOXSEG4EI64_V_M2_MF4 8027 +#define RISCV_PseudoVSOXSEG4EI64_V_M2_MF4_MASK 8028 +#define RISCV_PseudoVSOXSEG4EI64_V_M4_M1 8029 +#define RISCV_PseudoVSOXSEG4EI64_V_M4_M1_MASK 8030 +#define RISCV_PseudoVSOXSEG4EI64_V_M4_M2 8031 +#define RISCV_PseudoVSOXSEG4EI64_V_M4_M2_MASK 8032 +#define RISCV_PseudoVSOXSEG4EI64_V_M4_MF2 8033 +#define RISCV_PseudoVSOXSEG4EI64_V_M4_MF2_MASK 8034 +#define RISCV_PseudoVSOXSEG4EI64_V_M8_M1 8035 +#define RISCV_PseudoVSOXSEG4EI64_V_M8_M1_MASK 8036 +#define RISCV_PseudoVSOXSEG4EI64_V_M8_M2 8037 +#define RISCV_PseudoVSOXSEG4EI64_V_M8_M2_MASK 8038 +#define RISCV_PseudoVSOXSEG4EI8_V_M1_M1 8039 +#define RISCV_PseudoVSOXSEG4EI8_V_M1_M1_MASK 8040 +#define RISCV_PseudoVSOXSEG4EI8_V_M1_M2 8041 +#define RISCV_PseudoVSOXSEG4EI8_V_M1_M2_MASK 8042 +#define RISCV_PseudoVSOXSEG4EI8_V_M2_M2 8043 +#define RISCV_PseudoVSOXSEG4EI8_V_M2_M2_MASK 8044 +#define RISCV_PseudoVSOXSEG4EI8_V_MF2_M1 8045 +#define RISCV_PseudoVSOXSEG4EI8_V_MF2_M1_MASK 8046 +#define RISCV_PseudoVSOXSEG4EI8_V_MF2_M2 8047 +#define RISCV_PseudoVSOXSEG4EI8_V_MF2_M2_MASK 8048 +#define RISCV_PseudoVSOXSEG4EI8_V_MF2_MF2 8049 +#define RISCV_PseudoVSOXSEG4EI8_V_MF2_MF2_MASK 8050 +#define RISCV_PseudoVSOXSEG4EI8_V_MF4_M1 8051 +#define RISCV_PseudoVSOXSEG4EI8_V_MF4_M1_MASK 8052 +#define RISCV_PseudoVSOXSEG4EI8_V_MF4_M2 8053 +#define RISCV_PseudoVSOXSEG4EI8_V_MF4_M2_MASK 8054 +#define RISCV_PseudoVSOXSEG4EI8_V_MF4_MF2 8055 +#define RISCV_PseudoVSOXSEG4EI8_V_MF4_MF2_MASK 8056 +#define RISCV_PseudoVSOXSEG4EI8_V_MF4_MF4 8057 +#define RISCV_PseudoVSOXSEG4EI8_V_MF4_MF4_MASK 8058 +#define RISCV_PseudoVSOXSEG4EI8_V_MF8_M1 8059 +#define RISCV_PseudoVSOXSEG4EI8_V_MF8_M1_MASK 8060 +#define RISCV_PseudoVSOXSEG4EI8_V_MF8_MF2 8061 +#define RISCV_PseudoVSOXSEG4EI8_V_MF8_MF2_MASK 8062 +#define RISCV_PseudoVSOXSEG4EI8_V_MF8_MF4 8063 +#define RISCV_PseudoVSOXSEG4EI8_V_MF8_MF4_MASK 8064 +#define RISCV_PseudoVSOXSEG4EI8_V_MF8_MF8 8065 +#define RISCV_PseudoVSOXSEG4EI8_V_MF8_MF8_MASK 8066 +#define RISCV_PseudoVSOXSEG5EI16_V_M1_M1 8067 +#define RISCV_PseudoVSOXSEG5EI16_V_M1_M1_MASK 8068 +#define RISCV_PseudoVSOXSEG5EI16_V_M1_MF2 8069 +#define RISCV_PseudoVSOXSEG5EI16_V_M1_MF2_MASK 8070 +#define RISCV_PseudoVSOXSEG5EI16_V_M2_M1 8071 +#define RISCV_PseudoVSOXSEG5EI16_V_M2_M1_MASK 8072 +#define RISCV_PseudoVSOXSEG5EI16_V_MF2_M1 8073 +#define RISCV_PseudoVSOXSEG5EI16_V_MF2_M1_MASK 8074 +#define RISCV_PseudoVSOXSEG5EI16_V_MF2_MF2 8075 +#define RISCV_PseudoVSOXSEG5EI16_V_MF2_MF2_MASK 8076 +#define RISCV_PseudoVSOXSEG5EI16_V_MF2_MF4 8077 +#define RISCV_PseudoVSOXSEG5EI16_V_MF2_MF4_MASK 8078 +#define RISCV_PseudoVSOXSEG5EI16_V_MF4_M1 8079 +#define RISCV_PseudoVSOXSEG5EI16_V_MF4_M1_MASK 8080 +#define RISCV_PseudoVSOXSEG5EI16_V_MF4_MF2 8081 +#define RISCV_PseudoVSOXSEG5EI16_V_MF4_MF2_MASK 8082 +#define RISCV_PseudoVSOXSEG5EI16_V_MF4_MF4 8083 +#define RISCV_PseudoVSOXSEG5EI16_V_MF4_MF4_MASK 8084 +#define RISCV_PseudoVSOXSEG5EI16_V_MF4_MF8 8085 +#define RISCV_PseudoVSOXSEG5EI16_V_MF4_MF8_MASK 8086 +#define RISCV_PseudoVSOXSEG5EI32_V_M1_M1 8087 +#define RISCV_PseudoVSOXSEG5EI32_V_M1_M1_MASK 8088 +#define RISCV_PseudoVSOXSEG5EI32_V_M1_MF2 8089 +#define RISCV_PseudoVSOXSEG5EI32_V_M1_MF2_MASK 8090 +#define RISCV_PseudoVSOXSEG5EI32_V_M1_MF4 8091 +#define RISCV_PseudoVSOXSEG5EI32_V_M1_MF4_MASK 8092 +#define RISCV_PseudoVSOXSEG5EI32_V_M2_M1 8093 +#define RISCV_PseudoVSOXSEG5EI32_V_M2_M1_MASK 8094 +#define RISCV_PseudoVSOXSEG5EI32_V_M2_MF2 8095 +#define RISCV_PseudoVSOXSEG5EI32_V_M2_MF2_MASK 8096 +#define RISCV_PseudoVSOXSEG5EI32_V_M4_M1 8097 +#define RISCV_PseudoVSOXSEG5EI32_V_M4_M1_MASK 8098 +#define RISCV_PseudoVSOXSEG5EI32_V_MF2_M1 8099 +#define RISCV_PseudoVSOXSEG5EI32_V_MF2_M1_MASK 8100 +#define RISCV_PseudoVSOXSEG5EI32_V_MF2_MF2 8101 +#define RISCV_PseudoVSOXSEG5EI32_V_MF2_MF2_MASK 8102 +#define RISCV_PseudoVSOXSEG5EI32_V_MF2_MF4 8103 +#define RISCV_PseudoVSOXSEG5EI32_V_MF2_MF4_MASK 8104 +#define RISCV_PseudoVSOXSEG5EI32_V_MF2_MF8 8105 +#define RISCV_PseudoVSOXSEG5EI32_V_MF2_MF8_MASK 8106 +#define RISCV_PseudoVSOXSEG5EI64_V_M1_M1 8107 +#define RISCV_PseudoVSOXSEG5EI64_V_M1_M1_MASK 8108 +#define RISCV_PseudoVSOXSEG5EI64_V_M1_MF2 8109 +#define RISCV_PseudoVSOXSEG5EI64_V_M1_MF2_MASK 8110 +#define RISCV_PseudoVSOXSEG5EI64_V_M1_MF4 8111 +#define RISCV_PseudoVSOXSEG5EI64_V_M1_MF4_MASK 8112 +#define RISCV_PseudoVSOXSEG5EI64_V_M1_MF8 8113 +#define RISCV_PseudoVSOXSEG5EI64_V_M1_MF8_MASK 8114 +#define RISCV_PseudoVSOXSEG5EI64_V_M2_M1 8115 +#define RISCV_PseudoVSOXSEG5EI64_V_M2_M1_MASK 8116 +#define RISCV_PseudoVSOXSEG5EI64_V_M2_MF2 8117 +#define RISCV_PseudoVSOXSEG5EI64_V_M2_MF2_MASK 8118 +#define RISCV_PseudoVSOXSEG5EI64_V_M2_MF4 8119 +#define RISCV_PseudoVSOXSEG5EI64_V_M2_MF4_MASK 8120 +#define RISCV_PseudoVSOXSEG5EI64_V_M4_M1 8121 +#define RISCV_PseudoVSOXSEG5EI64_V_M4_M1_MASK 8122 +#define RISCV_PseudoVSOXSEG5EI64_V_M4_MF2 8123 +#define RISCV_PseudoVSOXSEG5EI64_V_M4_MF2_MASK 8124 +#define RISCV_PseudoVSOXSEG5EI64_V_M8_M1 8125 +#define RISCV_PseudoVSOXSEG5EI64_V_M8_M1_MASK 8126 +#define RISCV_PseudoVSOXSEG5EI8_V_M1_M1 8127 +#define RISCV_PseudoVSOXSEG5EI8_V_M1_M1_MASK 8128 +#define RISCV_PseudoVSOXSEG5EI8_V_MF2_M1 8129 +#define RISCV_PseudoVSOXSEG5EI8_V_MF2_M1_MASK 8130 +#define RISCV_PseudoVSOXSEG5EI8_V_MF2_MF2 8131 +#define RISCV_PseudoVSOXSEG5EI8_V_MF2_MF2_MASK 8132 +#define RISCV_PseudoVSOXSEG5EI8_V_MF4_M1 8133 +#define RISCV_PseudoVSOXSEG5EI8_V_MF4_M1_MASK 8134 +#define RISCV_PseudoVSOXSEG5EI8_V_MF4_MF2 8135 +#define RISCV_PseudoVSOXSEG5EI8_V_MF4_MF2_MASK 8136 +#define RISCV_PseudoVSOXSEG5EI8_V_MF4_MF4 8137 +#define RISCV_PseudoVSOXSEG5EI8_V_MF4_MF4_MASK 8138 +#define RISCV_PseudoVSOXSEG5EI8_V_MF8_M1 8139 +#define RISCV_PseudoVSOXSEG5EI8_V_MF8_M1_MASK 8140 +#define RISCV_PseudoVSOXSEG5EI8_V_MF8_MF2 8141 +#define RISCV_PseudoVSOXSEG5EI8_V_MF8_MF2_MASK 8142 +#define RISCV_PseudoVSOXSEG5EI8_V_MF8_MF4 8143 +#define RISCV_PseudoVSOXSEG5EI8_V_MF8_MF4_MASK 8144 +#define RISCV_PseudoVSOXSEG5EI8_V_MF8_MF8 8145 +#define RISCV_PseudoVSOXSEG5EI8_V_MF8_MF8_MASK 8146 +#define RISCV_PseudoVSOXSEG6EI16_V_M1_M1 8147 +#define RISCV_PseudoVSOXSEG6EI16_V_M1_M1_MASK 8148 +#define RISCV_PseudoVSOXSEG6EI16_V_M1_MF2 8149 +#define RISCV_PseudoVSOXSEG6EI16_V_M1_MF2_MASK 8150 +#define RISCV_PseudoVSOXSEG6EI16_V_M2_M1 8151 +#define RISCV_PseudoVSOXSEG6EI16_V_M2_M1_MASK 8152 +#define RISCV_PseudoVSOXSEG6EI16_V_MF2_M1 8153 +#define RISCV_PseudoVSOXSEG6EI16_V_MF2_M1_MASK 8154 +#define RISCV_PseudoVSOXSEG6EI16_V_MF2_MF2 8155 +#define RISCV_PseudoVSOXSEG6EI16_V_MF2_MF2_MASK 8156 +#define RISCV_PseudoVSOXSEG6EI16_V_MF2_MF4 8157 +#define RISCV_PseudoVSOXSEG6EI16_V_MF2_MF4_MASK 8158 +#define RISCV_PseudoVSOXSEG6EI16_V_MF4_M1 8159 +#define RISCV_PseudoVSOXSEG6EI16_V_MF4_M1_MASK 8160 +#define RISCV_PseudoVSOXSEG6EI16_V_MF4_MF2 8161 +#define RISCV_PseudoVSOXSEG6EI16_V_MF4_MF2_MASK 8162 +#define RISCV_PseudoVSOXSEG6EI16_V_MF4_MF4 8163 +#define RISCV_PseudoVSOXSEG6EI16_V_MF4_MF4_MASK 8164 +#define RISCV_PseudoVSOXSEG6EI16_V_MF4_MF8 8165 +#define RISCV_PseudoVSOXSEG6EI16_V_MF4_MF8_MASK 8166 +#define RISCV_PseudoVSOXSEG6EI32_V_M1_M1 8167 +#define RISCV_PseudoVSOXSEG6EI32_V_M1_M1_MASK 8168 +#define RISCV_PseudoVSOXSEG6EI32_V_M1_MF2 8169 +#define RISCV_PseudoVSOXSEG6EI32_V_M1_MF2_MASK 8170 +#define RISCV_PseudoVSOXSEG6EI32_V_M1_MF4 8171 +#define RISCV_PseudoVSOXSEG6EI32_V_M1_MF4_MASK 8172 +#define RISCV_PseudoVSOXSEG6EI32_V_M2_M1 8173 +#define RISCV_PseudoVSOXSEG6EI32_V_M2_M1_MASK 8174 +#define RISCV_PseudoVSOXSEG6EI32_V_M2_MF2 8175 +#define RISCV_PseudoVSOXSEG6EI32_V_M2_MF2_MASK 8176 +#define RISCV_PseudoVSOXSEG6EI32_V_M4_M1 8177 +#define RISCV_PseudoVSOXSEG6EI32_V_M4_M1_MASK 8178 +#define RISCV_PseudoVSOXSEG6EI32_V_MF2_M1 8179 +#define RISCV_PseudoVSOXSEG6EI32_V_MF2_M1_MASK 8180 +#define RISCV_PseudoVSOXSEG6EI32_V_MF2_MF2 8181 +#define RISCV_PseudoVSOXSEG6EI32_V_MF2_MF2_MASK 8182 +#define RISCV_PseudoVSOXSEG6EI32_V_MF2_MF4 8183 +#define RISCV_PseudoVSOXSEG6EI32_V_MF2_MF4_MASK 8184 +#define RISCV_PseudoVSOXSEG6EI32_V_MF2_MF8 8185 +#define RISCV_PseudoVSOXSEG6EI32_V_MF2_MF8_MASK 8186 +#define RISCV_PseudoVSOXSEG6EI64_V_M1_M1 8187 +#define RISCV_PseudoVSOXSEG6EI64_V_M1_M1_MASK 8188 +#define RISCV_PseudoVSOXSEG6EI64_V_M1_MF2 8189 +#define RISCV_PseudoVSOXSEG6EI64_V_M1_MF2_MASK 8190 +#define RISCV_PseudoVSOXSEG6EI64_V_M1_MF4 8191 +#define RISCV_PseudoVSOXSEG6EI64_V_M1_MF4_MASK 8192 +#define RISCV_PseudoVSOXSEG6EI64_V_M1_MF8 8193 +#define RISCV_PseudoVSOXSEG6EI64_V_M1_MF8_MASK 8194 +#define RISCV_PseudoVSOXSEG6EI64_V_M2_M1 8195 +#define RISCV_PseudoVSOXSEG6EI64_V_M2_M1_MASK 8196 +#define RISCV_PseudoVSOXSEG6EI64_V_M2_MF2 8197 +#define RISCV_PseudoVSOXSEG6EI64_V_M2_MF2_MASK 8198 +#define RISCV_PseudoVSOXSEG6EI64_V_M2_MF4 8199 +#define RISCV_PseudoVSOXSEG6EI64_V_M2_MF4_MASK 8200 +#define RISCV_PseudoVSOXSEG6EI64_V_M4_M1 8201 +#define RISCV_PseudoVSOXSEG6EI64_V_M4_M1_MASK 8202 +#define RISCV_PseudoVSOXSEG6EI64_V_M4_MF2 8203 +#define RISCV_PseudoVSOXSEG6EI64_V_M4_MF2_MASK 8204 +#define RISCV_PseudoVSOXSEG6EI64_V_M8_M1 8205 +#define RISCV_PseudoVSOXSEG6EI64_V_M8_M1_MASK 8206 +#define RISCV_PseudoVSOXSEG6EI8_V_M1_M1 8207 +#define RISCV_PseudoVSOXSEG6EI8_V_M1_M1_MASK 8208 +#define RISCV_PseudoVSOXSEG6EI8_V_MF2_M1 8209 +#define RISCV_PseudoVSOXSEG6EI8_V_MF2_M1_MASK 8210 +#define RISCV_PseudoVSOXSEG6EI8_V_MF2_MF2 8211 +#define RISCV_PseudoVSOXSEG6EI8_V_MF2_MF2_MASK 8212 +#define RISCV_PseudoVSOXSEG6EI8_V_MF4_M1 8213 +#define RISCV_PseudoVSOXSEG6EI8_V_MF4_M1_MASK 8214 +#define RISCV_PseudoVSOXSEG6EI8_V_MF4_MF2 8215 +#define RISCV_PseudoVSOXSEG6EI8_V_MF4_MF2_MASK 8216 +#define RISCV_PseudoVSOXSEG6EI8_V_MF4_MF4 8217 +#define RISCV_PseudoVSOXSEG6EI8_V_MF4_MF4_MASK 8218 +#define RISCV_PseudoVSOXSEG6EI8_V_MF8_M1 8219 +#define RISCV_PseudoVSOXSEG6EI8_V_MF8_M1_MASK 8220 +#define RISCV_PseudoVSOXSEG6EI8_V_MF8_MF2 8221 +#define RISCV_PseudoVSOXSEG6EI8_V_MF8_MF2_MASK 8222 +#define RISCV_PseudoVSOXSEG6EI8_V_MF8_MF4 8223 +#define RISCV_PseudoVSOXSEG6EI8_V_MF8_MF4_MASK 8224 +#define RISCV_PseudoVSOXSEG6EI8_V_MF8_MF8 8225 +#define RISCV_PseudoVSOXSEG6EI8_V_MF8_MF8_MASK 8226 +#define RISCV_PseudoVSOXSEG7EI16_V_M1_M1 8227 +#define RISCV_PseudoVSOXSEG7EI16_V_M1_M1_MASK 8228 +#define RISCV_PseudoVSOXSEG7EI16_V_M1_MF2 8229 +#define RISCV_PseudoVSOXSEG7EI16_V_M1_MF2_MASK 8230 +#define RISCV_PseudoVSOXSEG7EI16_V_M2_M1 8231 +#define RISCV_PseudoVSOXSEG7EI16_V_M2_M1_MASK 8232 +#define RISCV_PseudoVSOXSEG7EI16_V_MF2_M1 8233 +#define RISCV_PseudoVSOXSEG7EI16_V_MF2_M1_MASK 8234 +#define RISCV_PseudoVSOXSEG7EI16_V_MF2_MF2 8235 +#define RISCV_PseudoVSOXSEG7EI16_V_MF2_MF2_MASK 8236 +#define RISCV_PseudoVSOXSEG7EI16_V_MF2_MF4 8237 +#define RISCV_PseudoVSOXSEG7EI16_V_MF2_MF4_MASK 8238 +#define RISCV_PseudoVSOXSEG7EI16_V_MF4_M1 8239 +#define RISCV_PseudoVSOXSEG7EI16_V_MF4_M1_MASK 8240 +#define RISCV_PseudoVSOXSEG7EI16_V_MF4_MF2 8241 +#define RISCV_PseudoVSOXSEG7EI16_V_MF4_MF2_MASK 8242 +#define RISCV_PseudoVSOXSEG7EI16_V_MF4_MF4 8243 +#define RISCV_PseudoVSOXSEG7EI16_V_MF4_MF4_MASK 8244 +#define RISCV_PseudoVSOXSEG7EI16_V_MF4_MF8 8245 +#define RISCV_PseudoVSOXSEG7EI16_V_MF4_MF8_MASK 8246 +#define RISCV_PseudoVSOXSEG7EI32_V_M1_M1 8247 +#define RISCV_PseudoVSOXSEG7EI32_V_M1_M1_MASK 8248 +#define RISCV_PseudoVSOXSEG7EI32_V_M1_MF2 8249 +#define RISCV_PseudoVSOXSEG7EI32_V_M1_MF2_MASK 8250 +#define RISCV_PseudoVSOXSEG7EI32_V_M1_MF4 8251 +#define RISCV_PseudoVSOXSEG7EI32_V_M1_MF4_MASK 8252 +#define RISCV_PseudoVSOXSEG7EI32_V_M2_M1 8253 +#define RISCV_PseudoVSOXSEG7EI32_V_M2_M1_MASK 8254 +#define RISCV_PseudoVSOXSEG7EI32_V_M2_MF2 8255 +#define RISCV_PseudoVSOXSEG7EI32_V_M2_MF2_MASK 8256 +#define RISCV_PseudoVSOXSEG7EI32_V_M4_M1 8257 +#define RISCV_PseudoVSOXSEG7EI32_V_M4_M1_MASK 8258 +#define RISCV_PseudoVSOXSEG7EI32_V_MF2_M1 8259 +#define RISCV_PseudoVSOXSEG7EI32_V_MF2_M1_MASK 8260 +#define RISCV_PseudoVSOXSEG7EI32_V_MF2_MF2 8261 +#define RISCV_PseudoVSOXSEG7EI32_V_MF2_MF2_MASK 8262 +#define RISCV_PseudoVSOXSEG7EI32_V_MF2_MF4 8263 +#define RISCV_PseudoVSOXSEG7EI32_V_MF2_MF4_MASK 8264 +#define RISCV_PseudoVSOXSEG7EI32_V_MF2_MF8 8265 +#define RISCV_PseudoVSOXSEG7EI32_V_MF2_MF8_MASK 8266 +#define RISCV_PseudoVSOXSEG7EI64_V_M1_M1 8267 +#define RISCV_PseudoVSOXSEG7EI64_V_M1_M1_MASK 8268 +#define RISCV_PseudoVSOXSEG7EI64_V_M1_MF2 8269 +#define RISCV_PseudoVSOXSEG7EI64_V_M1_MF2_MASK 8270 +#define RISCV_PseudoVSOXSEG7EI64_V_M1_MF4 8271 +#define RISCV_PseudoVSOXSEG7EI64_V_M1_MF4_MASK 8272 +#define RISCV_PseudoVSOXSEG7EI64_V_M1_MF8 8273 +#define RISCV_PseudoVSOXSEG7EI64_V_M1_MF8_MASK 8274 +#define RISCV_PseudoVSOXSEG7EI64_V_M2_M1 8275 +#define RISCV_PseudoVSOXSEG7EI64_V_M2_M1_MASK 8276 +#define RISCV_PseudoVSOXSEG7EI64_V_M2_MF2 8277 +#define RISCV_PseudoVSOXSEG7EI64_V_M2_MF2_MASK 8278 +#define RISCV_PseudoVSOXSEG7EI64_V_M2_MF4 8279 +#define RISCV_PseudoVSOXSEG7EI64_V_M2_MF4_MASK 8280 +#define RISCV_PseudoVSOXSEG7EI64_V_M4_M1 8281 +#define RISCV_PseudoVSOXSEG7EI64_V_M4_M1_MASK 8282 +#define RISCV_PseudoVSOXSEG7EI64_V_M4_MF2 8283 +#define RISCV_PseudoVSOXSEG7EI64_V_M4_MF2_MASK 8284 +#define RISCV_PseudoVSOXSEG7EI64_V_M8_M1 8285 +#define RISCV_PseudoVSOXSEG7EI64_V_M8_M1_MASK 8286 +#define RISCV_PseudoVSOXSEG7EI8_V_M1_M1 8287 +#define RISCV_PseudoVSOXSEG7EI8_V_M1_M1_MASK 8288 +#define RISCV_PseudoVSOXSEG7EI8_V_MF2_M1 8289 +#define RISCV_PseudoVSOXSEG7EI8_V_MF2_M1_MASK 8290 +#define RISCV_PseudoVSOXSEG7EI8_V_MF2_MF2 8291 +#define RISCV_PseudoVSOXSEG7EI8_V_MF2_MF2_MASK 8292 +#define RISCV_PseudoVSOXSEG7EI8_V_MF4_M1 8293 +#define RISCV_PseudoVSOXSEG7EI8_V_MF4_M1_MASK 8294 +#define RISCV_PseudoVSOXSEG7EI8_V_MF4_MF2 8295 +#define RISCV_PseudoVSOXSEG7EI8_V_MF4_MF2_MASK 8296 +#define RISCV_PseudoVSOXSEG7EI8_V_MF4_MF4 8297 +#define RISCV_PseudoVSOXSEG7EI8_V_MF4_MF4_MASK 8298 +#define RISCV_PseudoVSOXSEG7EI8_V_MF8_M1 8299 +#define RISCV_PseudoVSOXSEG7EI8_V_MF8_M1_MASK 8300 +#define RISCV_PseudoVSOXSEG7EI8_V_MF8_MF2 8301 +#define RISCV_PseudoVSOXSEG7EI8_V_MF8_MF2_MASK 8302 +#define RISCV_PseudoVSOXSEG7EI8_V_MF8_MF4 8303 +#define RISCV_PseudoVSOXSEG7EI8_V_MF8_MF4_MASK 8304 +#define RISCV_PseudoVSOXSEG7EI8_V_MF8_MF8 8305 +#define RISCV_PseudoVSOXSEG7EI8_V_MF8_MF8_MASK 8306 +#define RISCV_PseudoVSOXSEG8EI16_V_M1_M1 8307 +#define RISCV_PseudoVSOXSEG8EI16_V_M1_M1_MASK 8308 +#define RISCV_PseudoVSOXSEG8EI16_V_M1_MF2 8309 +#define RISCV_PseudoVSOXSEG8EI16_V_M1_MF2_MASK 8310 +#define RISCV_PseudoVSOXSEG8EI16_V_M2_M1 8311 +#define RISCV_PseudoVSOXSEG8EI16_V_M2_M1_MASK 8312 +#define RISCV_PseudoVSOXSEG8EI16_V_MF2_M1 8313 +#define RISCV_PseudoVSOXSEG8EI16_V_MF2_M1_MASK 8314 +#define RISCV_PseudoVSOXSEG8EI16_V_MF2_MF2 8315 +#define RISCV_PseudoVSOXSEG8EI16_V_MF2_MF2_MASK 8316 +#define RISCV_PseudoVSOXSEG8EI16_V_MF2_MF4 8317 +#define RISCV_PseudoVSOXSEG8EI16_V_MF2_MF4_MASK 8318 +#define RISCV_PseudoVSOXSEG8EI16_V_MF4_M1 8319 +#define RISCV_PseudoVSOXSEG8EI16_V_MF4_M1_MASK 8320 +#define RISCV_PseudoVSOXSEG8EI16_V_MF4_MF2 8321 +#define RISCV_PseudoVSOXSEG8EI16_V_MF4_MF2_MASK 8322 +#define RISCV_PseudoVSOXSEG8EI16_V_MF4_MF4 8323 +#define RISCV_PseudoVSOXSEG8EI16_V_MF4_MF4_MASK 8324 +#define RISCV_PseudoVSOXSEG8EI16_V_MF4_MF8 8325 +#define RISCV_PseudoVSOXSEG8EI16_V_MF4_MF8_MASK 8326 +#define RISCV_PseudoVSOXSEG8EI32_V_M1_M1 8327 +#define RISCV_PseudoVSOXSEG8EI32_V_M1_M1_MASK 8328 +#define RISCV_PseudoVSOXSEG8EI32_V_M1_MF2 8329 +#define RISCV_PseudoVSOXSEG8EI32_V_M1_MF2_MASK 8330 +#define RISCV_PseudoVSOXSEG8EI32_V_M1_MF4 8331 +#define RISCV_PseudoVSOXSEG8EI32_V_M1_MF4_MASK 8332 +#define RISCV_PseudoVSOXSEG8EI32_V_M2_M1 8333 +#define RISCV_PseudoVSOXSEG8EI32_V_M2_M1_MASK 8334 +#define RISCV_PseudoVSOXSEG8EI32_V_M2_MF2 8335 +#define RISCV_PseudoVSOXSEG8EI32_V_M2_MF2_MASK 8336 +#define RISCV_PseudoVSOXSEG8EI32_V_M4_M1 8337 +#define RISCV_PseudoVSOXSEG8EI32_V_M4_M1_MASK 8338 +#define RISCV_PseudoVSOXSEG8EI32_V_MF2_M1 8339 +#define RISCV_PseudoVSOXSEG8EI32_V_MF2_M1_MASK 8340 +#define RISCV_PseudoVSOXSEG8EI32_V_MF2_MF2 8341 +#define RISCV_PseudoVSOXSEG8EI32_V_MF2_MF2_MASK 8342 +#define RISCV_PseudoVSOXSEG8EI32_V_MF2_MF4 8343 +#define RISCV_PseudoVSOXSEG8EI32_V_MF2_MF4_MASK 8344 +#define RISCV_PseudoVSOXSEG8EI32_V_MF2_MF8 8345 +#define RISCV_PseudoVSOXSEG8EI32_V_MF2_MF8_MASK 8346 +#define RISCV_PseudoVSOXSEG8EI64_V_M1_M1 8347 +#define RISCV_PseudoVSOXSEG8EI64_V_M1_M1_MASK 8348 +#define RISCV_PseudoVSOXSEG8EI64_V_M1_MF2 8349 +#define RISCV_PseudoVSOXSEG8EI64_V_M1_MF2_MASK 8350 +#define RISCV_PseudoVSOXSEG8EI64_V_M1_MF4 8351 +#define RISCV_PseudoVSOXSEG8EI64_V_M1_MF4_MASK 8352 +#define RISCV_PseudoVSOXSEG8EI64_V_M1_MF8 8353 +#define RISCV_PseudoVSOXSEG8EI64_V_M1_MF8_MASK 8354 +#define RISCV_PseudoVSOXSEG8EI64_V_M2_M1 8355 +#define RISCV_PseudoVSOXSEG8EI64_V_M2_M1_MASK 8356 +#define RISCV_PseudoVSOXSEG8EI64_V_M2_MF2 8357 +#define RISCV_PseudoVSOXSEG8EI64_V_M2_MF2_MASK 8358 +#define RISCV_PseudoVSOXSEG8EI64_V_M2_MF4 8359 +#define RISCV_PseudoVSOXSEG8EI64_V_M2_MF4_MASK 8360 +#define RISCV_PseudoVSOXSEG8EI64_V_M4_M1 8361 +#define RISCV_PseudoVSOXSEG8EI64_V_M4_M1_MASK 8362 +#define RISCV_PseudoVSOXSEG8EI64_V_M4_MF2 8363 +#define RISCV_PseudoVSOXSEG8EI64_V_M4_MF2_MASK 8364 +#define RISCV_PseudoVSOXSEG8EI64_V_M8_M1 8365 +#define RISCV_PseudoVSOXSEG8EI64_V_M8_M1_MASK 8366 +#define RISCV_PseudoVSOXSEG8EI8_V_M1_M1 8367 +#define RISCV_PseudoVSOXSEG8EI8_V_M1_M1_MASK 8368 +#define RISCV_PseudoVSOXSEG8EI8_V_MF2_M1 8369 +#define RISCV_PseudoVSOXSEG8EI8_V_MF2_M1_MASK 8370 +#define RISCV_PseudoVSOXSEG8EI8_V_MF2_MF2 8371 +#define RISCV_PseudoVSOXSEG8EI8_V_MF2_MF2_MASK 8372 +#define RISCV_PseudoVSOXSEG8EI8_V_MF4_M1 8373 +#define RISCV_PseudoVSOXSEG8EI8_V_MF4_M1_MASK 8374 +#define RISCV_PseudoVSOXSEG8EI8_V_MF4_MF2 8375 +#define RISCV_PseudoVSOXSEG8EI8_V_MF4_MF2_MASK 8376 +#define RISCV_PseudoVSOXSEG8EI8_V_MF4_MF4 8377 +#define RISCV_PseudoVSOXSEG8EI8_V_MF4_MF4_MASK 8378 +#define RISCV_PseudoVSOXSEG8EI8_V_MF8_M1 8379 +#define RISCV_PseudoVSOXSEG8EI8_V_MF8_M1_MASK 8380 +#define RISCV_PseudoVSOXSEG8EI8_V_MF8_MF2 8381 +#define RISCV_PseudoVSOXSEG8EI8_V_MF8_MF2_MASK 8382 +#define RISCV_PseudoVSOXSEG8EI8_V_MF8_MF4 8383 +#define RISCV_PseudoVSOXSEG8EI8_V_MF8_MF4_MASK 8384 +#define RISCV_PseudoVSOXSEG8EI8_V_MF8_MF8 8385 +#define RISCV_PseudoVSOXSEG8EI8_V_MF8_MF8_MASK 8386 +#define RISCV_PseudoVSPILL2_M1 8387 +#define RISCV_PseudoVSPILL2_M2 8388 +#define RISCV_PseudoVSPILL2_M4 8389 +#define RISCV_PseudoVSPILL2_MF2 8390 +#define RISCV_PseudoVSPILL2_MF4 8391 +#define RISCV_PseudoVSPILL2_MF8 8392 +#define RISCV_PseudoVSPILL3_M1 8393 +#define RISCV_PseudoVSPILL3_M2 8394 +#define RISCV_PseudoVSPILL3_MF2 8395 +#define RISCV_PseudoVSPILL3_MF4 8396 +#define RISCV_PseudoVSPILL3_MF8 8397 +#define RISCV_PseudoVSPILL4_M1 8398 +#define RISCV_PseudoVSPILL4_M2 8399 +#define RISCV_PseudoVSPILL4_MF2 8400 +#define RISCV_PseudoVSPILL4_MF4 8401 +#define RISCV_PseudoVSPILL4_MF8 8402 +#define RISCV_PseudoVSPILL5_M1 8403 +#define RISCV_PseudoVSPILL5_MF2 8404 +#define RISCV_PseudoVSPILL5_MF4 8405 +#define RISCV_PseudoVSPILL5_MF8 8406 +#define RISCV_PseudoVSPILL6_M1 8407 +#define RISCV_PseudoVSPILL6_MF2 8408 +#define RISCV_PseudoVSPILL6_MF4 8409 +#define RISCV_PseudoVSPILL6_MF8 8410 +#define RISCV_PseudoVSPILL7_M1 8411 +#define RISCV_PseudoVSPILL7_MF2 8412 +#define RISCV_PseudoVSPILL7_MF4 8413 +#define RISCV_PseudoVSPILL7_MF8 8414 +#define RISCV_PseudoVSPILL8_M1 8415 +#define RISCV_PseudoVSPILL8_MF2 8416 +#define RISCV_PseudoVSPILL8_MF4 8417 +#define RISCV_PseudoVSPILL8_MF8 8418 +#define RISCV_PseudoVSPILL_M1 8419 +#define RISCV_PseudoVSPILL_M2 8420 +#define RISCV_PseudoVSPILL_M4 8421 +#define RISCV_PseudoVSPILL_M8 8422 +#define RISCV_PseudoVSRA_VI_M1 8423 +#define RISCV_PseudoVSRA_VI_M1_MASK 8424 +#define RISCV_PseudoVSRA_VI_M2 8425 +#define RISCV_PseudoVSRA_VI_M2_MASK 8426 +#define RISCV_PseudoVSRA_VI_M4 8427 +#define RISCV_PseudoVSRA_VI_M4_MASK 8428 +#define RISCV_PseudoVSRA_VI_M8 8429 +#define RISCV_PseudoVSRA_VI_M8_MASK 8430 +#define RISCV_PseudoVSRA_VI_MF2 8431 +#define RISCV_PseudoVSRA_VI_MF2_MASK 8432 +#define RISCV_PseudoVSRA_VI_MF4 8433 +#define RISCV_PseudoVSRA_VI_MF4_MASK 8434 +#define RISCV_PseudoVSRA_VI_MF8 8435 +#define RISCV_PseudoVSRA_VI_MF8_MASK 8436 +#define RISCV_PseudoVSRA_VV_M1 8437 +#define RISCV_PseudoVSRA_VV_M1_MASK 8438 +#define RISCV_PseudoVSRA_VV_M2 8439 +#define RISCV_PseudoVSRA_VV_M2_MASK 8440 +#define RISCV_PseudoVSRA_VV_M4 8441 +#define RISCV_PseudoVSRA_VV_M4_MASK 8442 +#define RISCV_PseudoVSRA_VV_M8 8443 +#define RISCV_PseudoVSRA_VV_M8_MASK 8444 +#define RISCV_PseudoVSRA_VV_MF2 8445 +#define RISCV_PseudoVSRA_VV_MF2_MASK 8446 +#define RISCV_PseudoVSRA_VV_MF4 8447 +#define RISCV_PseudoVSRA_VV_MF4_MASK 8448 +#define RISCV_PseudoVSRA_VV_MF8 8449 +#define RISCV_PseudoVSRA_VV_MF8_MASK 8450 +#define RISCV_PseudoVSRA_VX_M1 8451 +#define RISCV_PseudoVSRA_VX_M1_MASK 8452 +#define RISCV_PseudoVSRA_VX_M2 8453 +#define RISCV_PseudoVSRA_VX_M2_MASK 8454 +#define RISCV_PseudoVSRA_VX_M4 8455 +#define RISCV_PseudoVSRA_VX_M4_MASK 8456 +#define RISCV_PseudoVSRA_VX_M8 8457 +#define RISCV_PseudoVSRA_VX_M8_MASK 8458 +#define RISCV_PseudoVSRA_VX_MF2 8459 +#define RISCV_PseudoVSRA_VX_MF2_MASK 8460 +#define RISCV_PseudoVSRA_VX_MF4 8461 +#define RISCV_PseudoVSRA_VX_MF4_MASK 8462 +#define RISCV_PseudoVSRA_VX_MF8 8463 +#define RISCV_PseudoVSRA_VX_MF8_MASK 8464 +#define RISCV_PseudoVSRL_VI_M1 8465 +#define RISCV_PseudoVSRL_VI_M1_MASK 8466 +#define RISCV_PseudoVSRL_VI_M2 8467 +#define RISCV_PseudoVSRL_VI_M2_MASK 8468 +#define RISCV_PseudoVSRL_VI_M4 8469 +#define RISCV_PseudoVSRL_VI_M4_MASK 8470 +#define RISCV_PseudoVSRL_VI_M8 8471 +#define RISCV_PseudoVSRL_VI_M8_MASK 8472 +#define RISCV_PseudoVSRL_VI_MF2 8473 +#define RISCV_PseudoVSRL_VI_MF2_MASK 8474 +#define RISCV_PseudoVSRL_VI_MF4 8475 +#define RISCV_PseudoVSRL_VI_MF4_MASK 8476 +#define RISCV_PseudoVSRL_VI_MF8 8477 +#define RISCV_PseudoVSRL_VI_MF8_MASK 8478 +#define RISCV_PseudoVSRL_VV_M1 8479 +#define RISCV_PseudoVSRL_VV_M1_MASK 8480 +#define RISCV_PseudoVSRL_VV_M2 8481 +#define RISCV_PseudoVSRL_VV_M2_MASK 8482 +#define RISCV_PseudoVSRL_VV_M4 8483 +#define RISCV_PseudoVSRL_VV_M4_MASK 8484 +#define RISCV_PseudoVSRL_VV_M8 8485 +#define RISCV_PseudoVSRL_VV_M8_MASK 8486 +#define RISCV_PseudoVSRL_VV_MF2 8487 +#define RISCV_PseudoVSRL_VV_MF2_MASK 8488 +#define RISCV_PseudoVSRL_VV_MF4 8489 +#define RISCV_PseudoVSRL_VV_MF4_MASK 8490 +#define RISCV_PseudoVSRL_VV_MF8 8491 +#define RISCV_PseudoVSRL_VV_MF8_MASK 8492 +#define RISCV_PseudoVSRL_VX_M1 8493 +#define RISCV_PseudoVSRL_VX_M1_MASK 8494 +#define RISCV_PseudoVSRL_VX_M2 8495 +#define RISCV_PseudoVSRL_VX_M2_MASK 8496 +#define RISCV_PseudoVSRL_VX_M4 8497 +#define RISCV_PseudoVSRL_VX_M4_MASK 8498 +#define RISCV_PseudoVSRL_VX_M8 8499 +#define RISCV_PseudoVSRL_VX_M8_MASK 8500 +#define RISCV_PseudoVSRL_VX_MF2 8501 +#define RISCV_PseudoVSRL_VX_MF2_MASK 8502 +#define RISCV_PseudoVSRL_VX_MF4 8503 +#define RISCV_PseudoVSRL_VX_MF4_MASK 8504 +#define RISCV_PseudoVSRL_VX_MF8 8505 +#define RISCV_PseudoVSRL_VX_MF8_MASK 8506 +#define RISCV_PseudoVSSE16_V_M1 8507 +#define RISCV_PseudoVSSE16_V_M1_MASK 8508 +#define RISCV_PseudoVSSE16_V_M2 8509 +#define RISCV_PseudoVSSE16_V_M2_MASK 8510 +#define RISCV_PseudoVSSE16_V_M4 8511 +#define RISCV_PseudoVSSE16_V_M4_MASK 8512 +#define RISCV_PseudoVSSE16_V_M8 8513 +#define RISCV_PseudoVSSE16_V_M8_MASK 8514 +#define RISCV_PseudoVSSE16_V_MF2 8515 +#define RISCV_PseudoVSSE16_V_MF2_MASK 8516 +#define RISCV_PseudoVSSE16_V_MF4 8517 +#define RISCV_PseudoVSSE16_V_MF4_MASK 8518 +#define RISCV_PseudoVSSE32_V_M1 8519 +#define RISCV_PseudoVSSE32_V_M1_MASK 8520 +#define RISCV_PseudoVSSE32_V_M2 8521 +#define RISCV_PseudoVSSE32_V_M2_MASK 8522 +#define RISCV_PseudoVSSE32_V_M4 8523 +#define RISCV_PseudoVSSE32_V_M4_MASK 8524 +#define RISCV_PseudoVSSE32_V_M8 8525 +#define RISCV_PseudoVSSE32_V_M8_MASK 8526 +#define RISCV_PseudoVSSE32_V_MF2 8527 +#define RISCV_PseudoVSSE32_V_MF2_MASK 8528 +#define RISCV_PseudoVSSE64_V_M1 8529 +#define RISCV_PseudoVSSE64_V_M1_MASK 8530 +#define RISCV_PseudoVSSE64_V_M2 8531 +#define RISCV_PseudoVSSE64_V_M2_MASK 8532 +#define RISCV_PseudoVSSE64_V_M4 8533 +#define RISCV_PseudoVSSE64_V_M4_MASK 8534 +#define RISCV_PseudoVSSE64_V_M8 8535 +#define RISCV_PseudoVSSE64_V_M8_MASK 8536 +#define RISCV_PseudoVSSE8_V_M1 8537 +#define RISCV_PseudoVSSE8_V_M1_MASK 8538 +#define RISCV_PseudoVSSE8_V_M2 8539 +#define RISCV_PseudoVSSE8_V_M2_MASK 8540 +#define RISCV_PseudoVSSE8_V_M4 8541 +#define RISCV_PseudoVSSE8_V_M4_MASK 8542 +#define RISCV_PseudoVSSE8_V_M8 8543 +#define RISCV_PseudoVSSE8_V_M8_MASK 8544 +#define RISCV_PseudoVSSE8_V_MF2 8545 +#define RISCV_PseudoVSSE8_V_MF2_MASK 8546 +#define RISCV_PseudoVSSE8_V_MF4 8547 +#define RISCV_PseudoVSSE8_V_MF4_MASK 8548 +#define RISCV_PseudoVSSE8_V_MF8 8549 +#define RISCV_PseudoVSSE8_V_MF8_MASK 8550 +#define RISCV_PseudoVSSEG2E16_V_M1 8551 +#define RISCV_PseudoVSSEG2E16_V_M1_MASK 8552 +#define RISCV_PseudoVSSEG2E16_V_M2 8553 +#define RISCV_PseudoVSSEG2E16_V_M2_MASK 8554 +#define RISCV_PseudoVSSEG2E16_V_M4 8555 +#define RISCV_PseudoVSSEG2E16_V_M4_MASK 8556 +#define RISCV_PseudoVSSEG2E16_V_MF2 8557 +#define RISCV_PseudoVSSEG2E16_V_MF2_MASK 8558 +#define RISCV_PseudoVSSEG2E16_V_MF4 8559 +#define RISCV_PseudoVSSEG2E16_V_MF4_MASK 8560 +#define RISCV_PseudoVSSEG2E32_V_M1 8561 +#define RISCV_PseudoVSSEG2E32_V_M1_MASK 8562 +#define RISCV_PseudoVSSEG2E32_V_M2 8563 +#define RISCV_PseudoVSSEG2E32_V_M2_MASK 8564 +#define RISCV_PseudoVSSEG2E32_V_M4 8565 +#define RISCV_PseudoVSSEG2E32_V_M4_MASK 8566 +#define RISCV_PseudoVSSEG2E32_V_MF2 8567 +#define RISCV_PseudoVSSEG2E32_V_MF2_MASK 8568 +#define RISCV_PseudoVSSEG2E64_V_M1 8569 +#define RISCV_PseudoVSSEG2E64_V_M1_MASK 8570 +#define RISCV_PseudoVSSEG2E64_V_M2 8571 +#define RISCV_PseudoVSSEG2E64_V_M2_MASK 8572 +#define RISCV_PseudoVSSEG2E64_V_M4 8573 +#define RISCV_PseudoVSSEG2E64_V_M4_MASK 8574 +#define RISCV_PseudoVSSEG2E8_V_M1 8575 +#define RISCV_PseudoVSSEG2E8_V_M1_MASK 8576 +#define RISCV_PseudoVSSEG2E8_V_M2 8577 +#define RISCV_PseudoVSSEG2E8_V_M2_MASK 8578 +#define RISCV_PseudoVSSEG2E8_V_M4 8579 +#define RISCV_PseudoVSSEG2E8_V_M4_MASK 8580 +#define RISCV_PseudoVSSEG2E8_V_MF2 8581 +#define RISCV_PseudoVSSEG2E8_V_MF2_MASK 8582 +#define RISCV_PseudoVSSEG2E8_V_MF4 8583 +#define RISCV_PseudoVSSEG2E8_V_MF4_MASK 8584 +#define RISCV_PseudoVSSEG2E8_V_MF8 8585 +#define RISCV_PseudoVSSEG2E8_V_MF8_MASK 8586 +#define RISCV_PseudoVSSEG3E16_V_M1 8587 +#define RISCV_PseudoVSSEG3E16_V_M1_MASK 8588 +#define RISCV_PseudoVSSEG3E16_V_M2 8589 +#define RISCV_PseudoVSSEG3E16_V_M2_MASK 8590 +#define RISCV_PseudoVSSEG3E16_V_MF2 8591 +#define RISCV_PseudoVSSEG3E16_V_MF2_MASK 8592 +#define RISCV_PseudoVSSEG3E16_V_MF4 8593 +#define RISCV_PseudoVSSEG3E16_V_MF4_MASK 8594 +#define RISCV_PseudoVSSEG3E32_V_M1 8595 +#define RISCV_PseudoVSSEG3E32_V_M1_MASK 8596 +#define RISCV_PseudoVSSEG3E32_V_M2 8597 +#define RISCV_PseudoVSSEG3E32_V_M2_MASK 8598 +#define RISCV_PseudoVSSEG3E32_V_MF2 8599 +#define RISCV_PseudoVSSEG3E32_V_MF2_MASK 8600 +#define RISCV_PseudoVSSEG3E64_V_M1 8601 +#define RISCV_PseudoVSSEG3E64_V_M1_MASK 8602 +#define RISCV_PseudoVSSEG3E64_V_M2 8603 +#define RISCV_PseudoVSSEG3E64_V_M2_MASK 8604 +#define RISCV_PseudoVSSEG3E8_V_M1 8605 +#define RISCV_PseudoVSSEG3E8_V_M1_MASK 8606 +#define RISCV_PseudoVSSEG3E8_V_M2 8607 +#define RISCV_PseudoVSSEG3E8_V_M2_MASK 8608 +#define RISCV_PseudoVSSEG3E8_V_MF2 8609 +#define RISCV_PseudoVSSEG3E8_V_MF2_MASK 8610 +#define RISCV_PseudoVSSEG3E8_V_MF4 8611 +#define RISCV_PseudoVSSEG3E8_V_MF4_MASK 8612 +#define RISCV_PseudoVSSEG3E8_V_MF8 8613 +#define RISCV_PseudoVSSEG3E8_V_MF8_MASK 8614 +#define RISCV_PseudoVSSEG4E16_V_M1 8615 +#define RISCV_PseudoVSSEG4E16_V_M1_MASK 8616 +#define RISCV_PseudoVSSEG4E16_V_M2 8617 +#define RISCV_PseudoVSSEG4E16_V_M2_MASK 8618 +#define RISCV_PseudoVSSEG4E16_V_MF2 8619 +#define RISCV_PseudoVSSEG4E16_V_MF2_MASK 8620 +#define RISCV_PseudoVSSEG4E16_V_MF4 8621 +#define RISCV_PseudoVSSEG4E16_V_MF4_MASK 8622 +#define RISCV_PseudoVSSEG4E32_V_M1 8623 +#define RISCV_PseudoVSSEG4E32_V_M1_MASK 8624 +#define RISCV_PseudoVSSEG4E32_V_M2 8625 +#define RISCV_PseudoVSSEG4E32_V_M2_MASK 8626 +#define RISCV_PseudoVSSEG4E32_V_MF2 8627 +#define RISCV_PseudoVSSEG4E32_V_MF2_MASK 8628 +#define RISCV_PseudoVSSEG4E64_V_M1 8629 +#define RISCV_PseudoVSSEG4E64_V_M1_MASK 8630 +#define RISCV_PseudoVSSEG4E64_V_M2 8631 +#define RISCV_PseudoVSSEG4E64_V_M2_MASK 8632 +#define RISCV_PseudoVSSEG4E8_V_M1 8633 +#define RISCV_PseudoVSSEG4E8_V_M1_MASK 8634 +#define RISCV_PseudoVSSEG4E8_V_M2 8635 +#define RISCV_PseudoVSSEG4E8_V_M2_MASK 8636 +#define RISCV_PseudoVSSEG4E8_V_MF2 8637 +#define RISCV_PseudoVSSEG4E8_V_MF2_MASK 8638 +#define RISCV_PseudoVSSEG4E8_V_MF4 8639 +#define RISCV_PseudoVSSEG4E8_V_MF4_MASK 8640 +#define RISCV_PseudoVSSEG4E8_V_MF8 8641 +#define RISCV_PseudoVSSEG4E8_V_MF8_MASK 8642 +#define RISCV_PseudoVSSEG5E16_V_M1 8643 +#define RISCV_PseudoVSSEG5E16_V_M1_MASK 8644 +#define RISCV_PseudoVSSEG5E16_V_MF2 8645 +#define RISCV_PseudoVSSEG5E16_V_MF2_MASK 8646 +#define RISCV_PseudoVSSEG5E16_V_MF4 8647 +#define RISCV_PseudoVSSEG5E16_V_MF4_MASK 8648 +#define RISCV_PseudoVSSEG5E32_V_M1 8649 +#define RISCV_PseudoVSSEG5E32_V_M1_MASK 8650 +#define RISCV_PseudoVSSEG5E32_V_MF2 8651 +#define RISCV_PseudoVSSEG5E32_V_MF2_MASK 8652 +#define RISCV_PseudoVSSEG5E64_V_M1 8653 +#define RISCV_PseudoVSSEG5E64_V_M1_MASK 8654 +#define RISCV_PseudoVSSEG5E8_V_M1 8655 +#define RISCV_PseudoVSSEG5E8_V_M1_MASK 8656 +#define RISCV_PseudoVSSEG5E8_V_MF2 8657 +#define RISCV_PseudoVSSEG5E8_V_MF2_MASK 8658 +#define RISCV_PseudoVSSEG5E8_V_MF4 8659 +#define RISCV_PseudoVSSEG5E8_V_MF4_MASK 8660 +#define RISCV_PseudoVSSEG5E8_V_MF8 8661 +#define RISCV_PseudoVSSEG5E8_V_MF8_MASK 8662 +#define RISCV_PseudoVSSEG6E16_V_M1 8663 +#define RISCV_PseudoVSSEG6E16_V_M1_MASK 8664 +#define RISCV_PseudoVSSEG6E16_V_MF2 8665 +#define RISCV_PseudoVSSEG6E16_V_MF2_MASK 8666 +#define RISCV_PseudoVSSEG6E16_V_MF4 8667 +#define RISCV_PseudoVSSEG6E16_V_MF4_MASK 8668 +#define RISCV_PseudoVSSEG6E32_V_M1 8669 +#define RISCV_PseudoVSSEG6E32_V_M1_MASK 8670 +#define RISCV_PseudoVSSEG6E32_V_MF2 8671 +#define RISCV_PseudoVSSEG6E32_V_MF2_MASK 8672 +#define RISCV_PseudoVSSEG6E64_V_M1 8673 +#define RISCV_PseudoVSSEG6E64_V_M1_MASK 8674 +#define RISCV_PseudoVSSEG6E8_V_M1 8675 +#define RISCV_PseudoVSSEG6E8_V_M1_MASK 8676 +#define RISCV_PseudoVSSEG6E8_V_MF2 8677 +#define RISCV_PseudoVSSEG6E8_V_MF2_MASK 8678 +#define RISCV_PseudoVSSEG6E8_V_MF4 8679 +#define RISCV_PseudoVSSEG6E8_V_MF4_MASK 8680 +#define RISCV_PseudoVSSEG6E8_V_MF8 8681 +#define RISCV_PseudoVSSEG6E8_V_MF8_MASK 8682 +#define RISCV_PseudoVSSEG7E16_V_M1 8683 +#define RISCV_PseudoVSSEG7E16_V_M1_MASK 8684 +#define RISCV_PseudoVSSEG7E16_V_MF2 8685 +#define RISCV_PseudoVSSEG7E16_V_MF2_MASK 8686 +#define RISCV_PseudoVSSEG7E16_V_MF4 8687 +#define RISCV_PseudoVSSEG7E16_V_MF4_MASK 8688 +#define RISCV_PseudoVSSEG7E32_V_M1 8689 +#define RISCV_PseudoVSSEG7E32_V_M1_MASK 8690 +#define RISCV_PseudoVSSEG7E32_V_MF2 8691 +#define RISCV_PseudoVSSEG7E32_V_MF2_MASK 8692 +#define RISCV_PseudoVSSEG7E64_V_M1 8693 +#define RISCV_PseudoVSSEG7E64_V_M1_MASK 8694 +#define RISCV_PseudoVSSEG7E8_V_M1 8695 +#define RISCV_PseudoVSSEG7E8_V_M1_MASK 8696 +#define RISCV_PseudoVSSEG7E8_V_MF2 8697 +#define RISCV_PseudoVSSEG7E8_V_MF2_MASK 8698 +#define RISCV_PseudoVSSEG7E8_V_MF4 8699 +#define RISCV_PseudoVSSEG7E8_V_MF4_MASK 8700 +#define RISCV_PseudoVSSEG7E8_V_MF8 8701 +#define RISCV_PseudoVSSEG7E8_V_MF8_MASK 8702 +#define RISCV_PseudoVSSEG8E16_V_M1 8703 +#define RISCV_PseudoVSSEG8E16_V_M1_MASK 8704 +#define RISCV_PseudoVSSEG8E16_V_MF2 8705 +#define RISCV_PseudoVSSEG8E16_V_MF2_MASK 8706 +#define RISCV_PseudoVSSEG8E16_V_MF4 8707 +#define RISCV_PseudoVSSEG8E16_V_MF4_MASK 8708 +#define RISCV_PseudoVSSEG8E32_V_M1 8709 +#define RISCV_PseudoVSSEG8E32_V_M1_MASK 8710 +#define RISCV_PseudoVSSEG8E32_V_MF2 8711 +#define RISCV_PseudoVSSEG8E32_V_MF2_MASK 8712 +#define RISCV_PseudoVSSEG8E64_V_M1 8713 +#define RISCV_PseudoVSSEG8E64_V_M1_MASK 8714 +#define RISCV_PseudoVSSEG8E8_V_M1 8715 +#define RISCV_PseudoVSSEG8E8_V_M1_MASK 8716 +#define RISCV_PseudoVSSEG8E8_V_MF2 8717 +#define RISCV_PseudoVSSEG8E8_V_MF2_MASK 8718 +#define RISCV_PseudoVSSEG8E8_V_MF4 8719 +#define RISCV_PseudoVSSEG8E8_V_MF4_MASK 8720 +#define RISCV_PseudoVSSEG8E8_V_MF8 8721 +#define RISCV_PseudoVSSEG8E8_V_MF8_MASK 8722 +#define RISCV_PseudoVSSRA_VI_M1 8723 +#define RISCV_PseudoVSSRA_VI_M1_MASK 8724 +#define RISCV_PseudoVSSRA_VI_M2 8725 +#define RISCV_PseudoVSSRA_VI_M2_MASK 8726 +#define RISCV_PseudoVSSRA_VI_M4 8727 +#define RISCV_PseudoVSSRA_VI_M4_MASK 8728 +#define RISCV_PseudoVSSRA_VI_M8 8729 +#define RISCV_PseudoVSSRA_VI_M8_MASK 8730 +#define RISCV_PseudoVSSRA_VI_MF2 8731 +#define RISCV_PseudoVSSRA_VI_MF2_MASK 8732 +#define RISCV_PseudoVSSRA_VI_MF4 8733 +#define RISCV_PseudoVSSRA_VI_MF4_MASK 8734 +#define RISCV_PseudoVSSRA_VI_MF8 8735 +#define RISCV_PseudoVSSRA_VI_MF8_MASK 8736 +#define RISCV_PseudoVSSRA_VV_M1 8737 +#define RISCV_PseudoVSSRA_VV_M1_MASK 8738 +#define RISCV_PseudoVSSRA_VV_M2 8739 +#define RISCV_PseudoVSSRA_VV_M2_MASK 8740 +#define RISCV_PseudoVSSRA_VV_M4 8741 +#define RISCV_PseudoVSSRA_VV_M4_MASK 8742 +#define RISCV_PseudoVSSRA_VV_M8 8743 +#define RISCV_PseudoVSSRA_VV_M8_MASK 8744 +#define RISCV_PseudoVSSRA_VV_MF2 8745 +#define RISCV_PseudoVSSRA_VV_MF2_MASK 8746 +#define RISCV_PseudoVSSRA_VV_MF4 8747 +#define RISCV_PseudoVSSRA_VV_MF4_MASK 8748 +#define RISCV_PseudoVSSRA_VV_MF8 8749 +#define RISCV_PseudoVSSRA_VV_MF8_MASK 8750 +#define RISCV_PseudoVSSRA_VX_M1 8751 +#define RISCV_PseudoVSSRA_VX_M1_MASK 8752 +#define RISCV_PseudoVSSRA_VX_M2 8753 +#define RISCV_PseudoVSSRA_VX_M2_MASK 8754 +#define RISCV_PseudoVSSRA_VX_M4 8755 +#define RISCV_PseudoVSSRA_VX_M4_MASK 8756 +#define RISCV_PseudoVSSRA_VX_M8 8757 +#define RISCV_PseudoVSSRA_VX_M8_MASK 8758 +#define RISCV_PseudoVSSRA_VX_MF2 8759 +#define RISCV_PseudoVSSRA_VX_MF2_MASK 8760 +#define RISCV_PseudoVSSRA_VX_MF4 8761 +#define RISCV_PseudoVSSRA_VX_MF4_MASK 8762 +#define RISCV_PseudoVSSRA_VX_MF8 8763 +#define RISCV_PseudoVSSRA_VX_MF8_MASK 8764 +#define RISCV_PseudoVSSRL_VI_M1 8765 +#define RISCV_PseudoVSSRL_VI_M1_MASK 8766 +#define RISCV_PseudoVSSRL_VI_M2 8767 +#define RISCV_PseudoVSSRL_VI_M2_MASK 8768 +#define RISCV_PseudoVSSRL_VI_M4 8769 +#define RISCV_PseudoVSSRL_VI_M4_MASK 8770 +#define RISCV_PseudoVSSRL_VI_M8 8771 +#define RISCV_PseudoVSSRL_VI_M8_MASK 8772 +#define RISCV_PseudoVSSRL_VI_MF2 8773 +#define RISCV_PseudoVSSRL_VI_MF2_MASK 8774 +#define RISCV_PseudoVSSRL_VI_MF4 8775 +#define RISCV_PseudoVSSRL_VI_MF4_MASK 8776 +#define RISCV_PseudoVSSRL_VI_MF8 8777 +#define RISCV_PseudoVSSRL_VI_MF8_MASK 8778 +#define RISCV_PseudoVSSRL_VV_M1 8779 +#define RISCV_PseudoVSSRL_VV_M1_MASK 8780 +#define RISCV_PseudoVSSRL_VV_M2 8781 +#define RISCV_PseudoVSSRL_VV_M2_MASK 8782 +#define RISCV_PseudoVSSRL_VV_M4 8783 +#define RISCV_PseudoVSSRL_VV_M4_MASK 8784 +#define RISCV_PseudoVSSRL_VV_M8 8785 +#define RISCV_PseudoVSSRL_VV_M8_MASK 8786 +#define RISCV_PseudoVSSRL_VV_MF2 8787 +#define RISCV_PseudoVSSRL_VV_MF2_MASK 8788 +#define RISCV_PseudoVSSRL_VV_MF4 8789 +#define RISCV_PseudoVSSRL_VV_MF4_MASK 8790 +#define RISCV_PseudoVSSRL_VV_MF8 8791 +#define RISCV_PseudoVSSRL_VV_MF8_MASK 8792 +#define RISCV_PseudoVSSRL_VX_M1 8793 +#define RISCV_PseudoVSSRL_VX_M1_MASK 8794 +#define RISCV_PseudoVSSRL_VX_M2 8795 +#define RISCV_PseudoVSSRL_VX_M2_MASK 8796 +#define RISCV_PseudoVSSRL_VX_M4 8797 +#define RISCV_PseudoVSSRL_VX_M4_MASK 8798 +#define RISCV_PseudoVSSRL_VX_M8 8799 +#define RISCV_PseudoVSSRL_VX_M8_MASK 8800 +#define RISCV_PseudoVSSRL_VX_MF2 8801 +#define RISCV_PseudoVSSRL_VX_MF2_MASK 8802 +#define RISCV_PseudoVSSRL_VX_MF4 8803 +#define RISCV_PseudoVSSRL_VX_MF4_MASK 8804 +#define RISCV_PseudoVSSRL_VX_MF8 8805 +#define RISCV_PseudoVSSRL_VX_MF8_MASK 8806 +#define RISCV_PseudoVSSSEG2E16_V_M1 8807 +#define RISCV_PseudoVSSSEG2E16_V_M1_MASK 8808 +#define RISCV_PseudoVSSSEG2E16_V_M2 8809 +#define RISCV_PseudoVSSSEG2E16_V_M2_MASK 8810 +#define RISCV_PseudoVSSSEG2E16_V_M4 8811 +#define RISCV_PseudoVSSSEG2E16_V_M4_MASK 8812 +#define RISCV_PseudoVSSSEG2E16_V_MF2 8813 +#define RISCV_PseudoVSSSEG2E16_V_MF2_MASK 8814 +#define RISCV_PseudoVSSSEG2E16_V_MF4 8815 +#define RISCV_PseudoVSSSEG2E16_V_MF4_MASK 8816 +#define RISCV_PseudoVSSSEG2E32_V_M1 8817 +#define RISCV_PseudoVSSSEG2E32_V_M1_MASK 8818 +#define RISCV_PseudoVSSSEG2E32_V_M2 8819 +#define RISCV_PseudoVSSSEG2E32_V_M2_MASK 8820 +#define RISCV_PseudoVSSSEG2E32_V_M4 8821 +#define RISCV_PseudoVSSSEG2E32_V_M4_MASK 8822 +#define RISCV_PseudoVSSSEG2E32_V_MF2 8823 +#define RISCV_PseudoVSSSEG2E32_V_MF2_MASK 8824 +#define RISCV_PseudoVSSSEG2E64_V_M1 8825 +#define RISCV_PseudoVSSSEG2E64_V_M1_MASK 8826 +#define RISCV_PseudoVSSSEG2E64_V_M2 8827 +#define RISCV_PseudoVSSSEG2E64_V_M2_MASK 8828 +#define RISCV_PseudoVSSSEG2E64_V_M4 8829 +#define RISCV_PseudoVSSSEG2E64_V_M4_MASK 8830 +#define RISCV_PseudoVSSSEG2E8_V_M1 8831 +#define RISCV_PseudoVSSSEG2E8_V_M1_MASK 8832 +#define RISCV_PseudoVSSSEG2E8_V_M2 8833 +#define RISCV_PseudoVSSSEG2E8_V_M2_MASK 8834 +#define RISCV_PseudoVSSSEG2E8_V_M4 8835 +#define RISCV_PseudoVSSSEG2E8_V_M4_MASK 8836 +#define RISCV_PseudoVSSSEG2E8_V_MF2 8837 +#define RISCV_PseudoVSSSEG2E8_V_MF2_MASK 8838 +#define RISCV_PseudoVSSSEG2E8_V_MF4 8839 +#define RISCV_PseudoVSSSEG2E8_V_MF4_MASK 8840 +#define RISCV_PseudoVSSSEG2E8_V_MF8 8841 +#define RISCV_PseudoVSSSEG2E8_V_MF8_MASK 8842 +#define RISCV_PseudoVSSSEG3E16_V_M1 8843 +#define RISCV_PseudoVSSSEG3E16_V_M1_MASK 8844 +#define RISCV_PseudoVSSSEG3E16_V_M2 8845 +#define RISCV_PseudoVSSSEG3E16_V_M2_MASK 8846 +#define RISCV_PseudoVSSSEG3E16_V_MF2 8847 +#define RISCV_PseudoVSSSEG3E16_V_MF2_MASK 8848 +#define RISCV_PseudoVSSSEG3E16_V_MF4 8849 +#define RISCV_PseudoVSSSEG3E16_V_MF4_MASK 8850 +#define RISCV_PseudoVSSSEG3E32_V_M1 8851 +#define RISCV_PseudoVSSSEG3E32_V_M1_MASK 8852 +#define RISCV_PseudoVSSSEG3E32_V_M2 8853 +#define RISCV_PseudoVSSSEG3E32_V_M2_MASK 8854 +#define RISCV_PseudoVSSSEG3E32_V_MF2 8855 +#define RISCV_PseudoVSSSEG3E32_V_MF2_MASK 8856 +#define RISCV_PseudoVSSSEG3E64_V_M1 8857 +#define RISCV_PseudoVSSSEG3E64_V_M1_MASK 8858 +#define RISCV_PseudoVSSSEG3E64_V_M2 8859 +#define RISCV_PseudoVSSSEG3E64_V_M2_MASK 8860 +#define RISCV_PseudoVSSSEG3E8_V_M1 8861 +#define RISCV_PseudoVSSSEG3E8_V_M1_MASK 8862 +#define RISCV_PseudoVSSSEG3E8_V_M2 8863 +#define RISCV_PseudoVSSSEG3E8_V_M2_MASK 8864 +#define RISCV_PseudoVSSSEG3E8_V_MF2 8865 +#define RISCV_PseudoVSSSEG3E8_V_MF2_MASK 8866 +#define RISCV_PseudoVSSSEG3E8_V_MF4 8867 +#define RISCV_PseudoVSSSEG3E8_V_MF4_MASK 8868 +#define RISCV_PseudoVSSSEG3E8_V_MF8 8869 +#define RISCV_PseudoVSSSEG3E8_V_MF8_MASK 8870 +#define RISCV_PseudoVSSSEG4E16_V_M1 8871 +#define RISCV_PseudoVSSSEG4E16_V_M1_MASK 8872 +#define RISCV_PseudoVSSSEG4E16_V_M2 8873 +#define RISCV_PseudoVSSSEG4E16_V_M2_MASK 8874 +#define RISCV_PseudoVSSSEG4E16_V_MF2 8875 +#define RISCV_PseudoVSSSEG4E16_V_MF2_MASK 8876 +#define RISCV_PseudoVSSSEG4E16_V_MF4 8877 +#define RISCV_PseudoVSSSEG4E16_V_MF4_MASK 8878 +#define RISCV_PseudoVSSSEG4E32_V_M1 8879 +#define RISCV_PseudoVSSSEG4E32_V_M1_MASK 8880 +#define RISCV_PseudoVSSSEG4E32_V_M2 8881 +#define RISCV_PseudoVSSSEG4E32_V_M2_MASK 8882 +#define RISCV_PseudoVSSSEG4E32_V_MF2 8883 +#define RISCV_PseudoVSSSEG4E32_V_MF2_MASK 8884 +#define RISCV_PseudoVSSSEG4E64_V_M1 8885 +#define RISCV_PseudoVSSSEG4E64_V_M1_MASK 8886 +#define RISCV_PseudoVSSSEG4E64_V_M2 8887 +#define RISCV_PseudoVSSSEG4E64_V_M2_MASK 8888 +#define RISCV_PseudoVSSSEG4E8_V_M1 8889 +#define RISCV_PseudoVSSSEG4E8_V_M1_MASK 8890 +#define RISCV_PseudoVSSSEG4E8_V_M2 8891 +#define RISCV_PseudoVSSSEG4E8_V_M2_MASK 8892 +#define RISCV_PseudoVSSSEG4E8_V_MF2 8893 +#define RISCV_PseudoVSSSEG4E8_V_MF2_MASK 8894 +#define RISCV_PseudoVSSSEG4E8_V_MF4 8895 +#define RISCV_PseudoVSSSEG4E8_V_MF4_MASK 8896 +#define RISCV_PseudoVSSSEG4E8_V_MF8 8897 +#define RISCV_PseudoVSSSEG4E8_V_MF8_MASK 8898 +#define RISCV_PseudoVSSSEG5E16_V_M1 8899 +#define RISCV_PseudoVSSSEG5E16_V_M1_MASK 8900 +#define RISCV_PseudoVSSSEG5E16_V_MF2 8901 +#define RISCV_PseudoVSSSEG5E16_V_MF2_MASK 8902 +#define RISCV_PseudoVSSSEG5E16_V_MF4 8903 +#define RISCV_PseudoVSSSEG5E16_V_MF4_MASK 8904 +#define RISCV_PseudoVSSSEG5E32_V_M1 8905 +#define RISCV_PseudoVSSSEG5E32_V_M1_MASK 8906 +#define RISCV_PseudoVSSSEG5E32_V_MF2 8907 +#define RISCV_PseudoVSSSEG5E32_V_MF2_MASK 8908 +#define RISCV_PseudoVSSSEG5E64_V_M1 8909 +#define RISCV_PseudoVSSSEG5E64_V_M1_MASK 8910 +#define RISCV_PseudoVSSSEG5E8_V_M1 8911 +#define RISCV_PseudoVSSSEG5E8_V_M1_MASK 8912 +#define RISCV_PseudoVSSSEG5E8_V_MF2 8913 +#define RISCV_PseudoVSSSEG5E8_V_MF2_MASK 8914 +#define RISCV_PseudoVSSSEG5E8_V_MF4 8915 +#define RISCV_PseudoVSSSEG5E8_V_MF4_MASK 8916 +#define RISCV_PseudoVSSSEG5E8_V_MF8 8917 +#define RISCV_PseudoVSSSEG5E8_V_MF8_MASK 8918 +#define RISCV_PseudoVSSSEG6E16_V_M1 8919 +#define RISCV_PseudoVSSSEG6E16_V_M1_MASK 8920 +#define RISCV_PseudoVSSSEG6E16_V_MF2 8921 +#define RISCV_PseudoVSSSEG6E16_V_MF2_MASK 8922 +#define RISCV_PseudoVSSSEG6E16_V_MF4 8923 +#define RISCV_PseudoVSSSEG6E16_V_MF4_MASK 8924 +#define RISCV_PseudoVSSSEG6E32_V_M1 8925 +#define RISCV_PseudoVSSSEG6E32_V_M1_MASK 8926 +#define RISCV_PseudoVSSSEG6E32_V_MF2 8927 +#define RISCV_PseudoVSSSEG6E32_V_MF2_MASK 8928 +#define RISCV_PseudoVSSSEG6E64_V_M1 8929 +#define RISCV_PseudoVSSSEG6E64_V_M1_MASK 8930 +#define RISCV_PseudoVSSSEG6E8_V_M1 8931 +#define RISCV_PseudoVSSSEG6E8_V_M1_MASK 8932 +#define RISCV_PseudoVSSSEG6E8_V_MF2 8933 +#define RISCV_PseudoVSSSEG6E8_V_MF2_MASK 8934 +#define RISCV_PseudoVSSSEG6E8_V_MF4 8935 +#define RISCV_PseudoVSSSEG6E8_V_MF4_MASK 8936 +#define RISCV_PseudoVSSSEG6E8_V_MF8 8937 +#define RISCV_PseudoVSSSEG6E8_V_MF8_MASK 8938 +#define RISCV_PseudoVSSSEG7E16_V_M1 8939 +#define RISCV_PseudoVSSSEG7E16_V_M1_MASK 8940 +#define RISCV_PseudoVSSSEG7E16_V_MF2 8941 +#define RISCV_PseudoVSSSEG7E16_V_MF2_MASK 8942 +#define RISCV_PseudoVSSSEG7E16_V_MF4 8943 +#define RISCV_PseudoVSSSEG7E16_V_MF4_MASK 8944 +#define RISCV_PseudoVSSSEG7E32_V_M1 8945 +#define RISCV_PseudoVSSSEG7E32_V_M1_MASK 8946 +#define RISCV_PseudoVSSSEG7E32_V_MF2 8947 +#define RISCV_PseudoVSSSEG7E32_V_MF2_MASK 8948 +#define RISCV_PseudoVSSSEG7E64_V_M1 8949 +#define RISCV_PseudoVSSSEG7E64_V_M1_MASK 8950 +#define RISCV_PseudoVSSSEG7E8_V_M1 8951 +#define RISCV_PseudoVSSSEG7E8_V_M1_MASK 8952 +#define RISCV_PseudoVSSSEG7E8_V_MF2 8953 +#define RISCV_PseudoVSSSEG7E8_V_MF2_MASK 8954 +#define RISCV_PseudoVSSSEG7E8_V_MF4 8955 +#define RISCV_PseudoVSSSEG7E8_V_MF4_MASK 8956 +#define RISCV_PseudoVSSSEG7E8_V_MF8 8957 +#define RISCV_PseudoVSSSEG7E8_V_MF8_MASK 8958 +#define RISCV_PseudoVSSSEG8E16_V_M1 8959 +#define RISCV_PseudoVSSSEG8E16_V_M1_MASK 8960 +#define RISCV_PseudoVSSSEG8E16_V_MF2 8961 +#define RISCV_PseudoVSSSEG8E16_V_MF2_MASK 8962 +#define RISCV_PseudoVSSSEG8E16_V_MF4 8963 +#define RISCV_PseudoVSSSEG8E16_V_MF4_MASK 8964 +#define RISCV_PseudoVSSSEG8E32_V_M1 8965 +#define RISCV_PseudoVSSSEG8E32_V_M1_MASK 8966 +#define RISCV_PseudoVSSSEG8E32_V_MF2 8967 +#define RISCV_PseudoVSSSEG8E32_V_MF2_MASK 8968 +#define RISCV_PseudoVSSSEG8E64_V_M1 8969 +#define RISCV_PseudoVSSSEG8E64_V_M1_MASK 8970 +#define RISCV_PseudoVSSSEG8E8_V_M1 8971 +#define RISCV_PseudoVSSSEG8E8_V_M1_MASK 8972 +#define RISCV_PseudoVSSSEG8E8_V_MF2 8973 +#define RISCV_PseudoVSSSEG8E8_V_MF2_MASK 8974 +#define RISCV_PseudoVSSSEG8E8_V_MF4 8975 +#define RISCV_PseudoVSSSEG8E8_V_MF4_MASK 8976 +#define RISCV_PseudoVSSSEG8E8_V_MF8 8977 +#define RISCV_PseudoVSSSEG8E8_V_MF8_MASK 8978 +#define RISCV_PseudoVSSUBU_VV_M1 8979 +#define RISCV_PseudoVSSUBU_VV_M1_MASK 8980 +#define RISCV_PseudoVSSUBU_VV_M2 8981 +#define RISCV_PseudoVSSUBU_VV_M2_MASK 8982 +#define RISCV_PseudoVSSUBU_VV_M4 8983 +#define RISCV_PseudoVSSUBU_VV_M4_MASK 8984 +#define RISCV_PseudoVSSUBU_VV_M8 8985 +#define RISCV_PseudoVSSUBU_VV_M8_MASK 8986 +#define RISCV_PseudoVSSUBU_VV_MF2 8987 +#define RISCV_PseudoVSSUBU_VV_MF2_MASK 8988 +#define RISCV_PseudoVSSUBU_VV_MF4 8989 +#define RISCV_PseudoVSSUBU_VV_MF4_MASK 8990 +#define RISCV_PseudoVSSUBU_VV_MF8 8991 +#define RISCV_PseudoVSSUBU_VV_MF8_MASK 8992 +#define RISCV_PseudoVSSUBU_VX_M1 8993 +#define RISCV_PseudoVSSUBU_VX_M1_MASK 8994 +#define RISCV_PseudoVSSUBU_VX_M2 8995 +#define RISCV_PseudoVSSUBU_VX_M2_MASK 8996 +#define RISCV_PseudoVSSUBU_VX_M4 8997 +#define RISCV_PseudoVSSUBU_VX_M4_MASK 8998 +#define RISCV_PseudoVSSUBU_VX_M8 8999 +#define RISCV_PseudoVSSUBU_VX_M8_MASK 9000 +#define RISCV_PseudoVSSUBU_VX_MF2 9001 +#define RISCV_PseudoVSSUBU_VX_MF2_MASK 9002 +#define RISCV_PseudoVSSUBU_VX_MF4 9003 +#define RISCV_PseudoVSSUBU_VX_MF4_MASK 9004 +#define RISCV_PseudoVSSUBU_VX_MF8 9005 +#define RISCV_PseudoVSSUBU_VX_MF8_MASK 9006 +#define RISCV_PseudoVSSUB_VV_M1 9007 +#define RISCV_PseudoVSSUB_VV_M1_MASK 9008 +#define RISCV_PseudoVSSUB_VV_M2 9009 +#define RISCV_PseudoVSSUB_VV_M2_MASK 9010 +#define RISCV_PseudoVSSUB_VV_M4 9011 +#define RISCV_PseudoVSSUB_VV_M4_MASK 9012 +#define RISCV_PseudoVSSUB_VV_M8 9013 +#define RISCV_PseudoVSSUB_VV_M8_MASK 9014 +#define RISCV_PseudoVSSUB_VV_MF2 9015 +#define RISCV_PseudoVSSUB_VV_MF2_MASK 9016 +#define RISCV_PseudoVSSUB_VV_MF4 9017 +#define RISCV_PseudoVSSUB_VV_MF4_MASK 9018 +#define RISCV_PseudoVSSUB_VV_MF8 9019 +#define RISCV_PseudoVSSUB_VV_MF8_MASK 9020 +#define RISCV_PseudoVSSUB_VX_M1 9021 +#define RISCV_PseudoVSSUB_VX_M1_MASK 9022 +#define RISCV_PseudoVSSUB_VX_M2 9023 +#define RISCV_PseudoVSSUB_VX_M2_MASK 9024 +#define RISCV_PseudoVSSUB_VX_M4 9025 +#define RISCV_PseudoVSSUB_VX_M4_MASK 9026 +#define RISCV_PseudoVSSUB_VX_M8 9027 +#define RISCV_PseudoVSSUB_VX_M8_MASK 9028 +#define RISCV_PseudoVSSUB_VX_MF2 9029 +#define RISCV_PseudoVSSUB_VX_MF2_MASK 9030 +#define RISCV_PseudoVSSUB_VX_MF4 9031 +#define RISCV_PseudoVSSUB_VX_MF4_MASK 9032 +#define RISCV_PseudoVSSUB_VX_MF8 9033 +#define RISCV_PseudoVSSUB_VX_MF8_MASK 9034 +#define RISCV_PseudoVSUB_VV_M1 9035 +#define RISCV_PseudoVSUB_VV_M1_MASK 9036 +#define RISCV_PseudoVSUB_VV_M2 9037 +#define RISCV_PseudoVSUB_VV_M2_MASK 9038 +#define RISCV_PseudoVSUB_VV_M4 9039 +#define RISCV_PseudoVSUB_VV_M4_MASK 9040 +#define RISCV_PseudoVSUB_VV_M8 9041 +#define RISCV_PseudoVSUB_VV_M8_MASK 9042 +#define RISCV_PseudoVSUB_VV_MF2 9043 +#define RISCV_PseudoVSUB_VV_MF2_MASK 9044 +#define RISCV_PseudoVSUB_VV_MF4 9045 +#define RISCV_PseudoVSUB_VV_MF4_MASK 9046 +#define RISCV_PseudoVSUB_VV_MF8 9047 +#define RISCV_PseudoVSUB_VV_MF8_MASK 9048 +#define RISCV_PseudoVSUB_VX_M1 9049 +#define RISCV_PseudoVSUB_VX_M1_MASK 9050 +#define RISCV_PseudoVSUB_VX_M2 9051 +#define RISCV_PseudoVSUB_VX_M2_MASK 9052 +#define RISCV_PseudoVSUB_VX_M4 9053 +#define RISCV_PseudoVSUB_VX_M4_MASK 9054 +#define RISCV_PseudoVSUB_VX_M8 9055 +#define RISCV_PseudoVSUB_VX_M8_MASK 9056 +#define RISCV_PseudoVSUB_VX_MF2 9057 +#define RISCV_PseudoVSUB_VX_MF2_MASK 9058 +#define RISCV_PseudoVSUB_VX_MF4 9059 +#define RISCV_PseudoVSUB_VX_MF4_MASK 9060 +#define RISCV_PseudoVSUB_VX_MF8 9061 +#define RISCV_PseudoVSUB_VX_MF8_MASK 9062 +#define RISCV_PseudoVSUXEI16_V_M1_M1 9063 +#define RISCV_PseudoVSUXEI16_V_M1_M1_MASK 9064 +#define RISCV_PseudoVSUXEI16_V_M1_M2 9065 +#define RISCV_PseudoVSUXEI16_V_M1_M2_MASK 9066 +#define RISCV_PseudoVSUXEI16_V_M1_M4 9067 +#define RISCV_PseudoVSUXEI16_V_M1_M4_MASK 9068 +#define RISCV_PseudoVSUXEI16_V_M1_MF2 9069 +#define RISCV_PseudoVSUXEI16_V_M1_MF2_MASK 9070 +#define RISCV_PseudoVSUXEI16_V_M2_M1 9071 +#define RISCV_PseudoVSUXEI16_V_M2_M1_MASK 9072 +#define RISCV_PseudoVSUXEI16_V_M2_M2 9073 +#define RISCV_PseudoVSUXEI16_V_M2_M2_MASK 9074 +#define RISCV_PseudoVSUXEI16_V_M2_M4 9075 +#define RISCV_PseudoVSUXEI16_V_M2_M4_MASK 9076 +#define RISCV_PseudoVSUXEI16_V_M2_M8 9077 +#define RISCV_PseudoVSUXEI16_V_M2_M8_MASK 9078 +#define RISCV_PseudoVSUXEI16_V_M4_M2 9079 +#define RISCV_PseudoVSUXEI16_V_M4_M2_MASK 9080 +#define RISCV_PseudoVSUXEI16_V_M4_M4 9081 +#define RISCV_PseudoVSUXEI16_V_M4_M4_MASK 9082 +#define RISCV_PseudoVSUXEI16_V_M4_M8 9083 +#define RISCV_PseudoVSUXEI16_V_M4_M8_MASK 9084 +#define RISCV_PseudoVSUXEI16_V_M8_M4 9085 +#define RISCV_PseudoVSUXEI16_V_M8_M4_MASK 9086 +#define RISCV_PseudoVSUXEI16_V_M8_M8 9087 +#define RISCV_PseudoVSUXEI16_V_M8_M8_MASK 9088 +#define RISCV_PseudoVSUXEI16_V_MF2_M1 9089 +#define RISCV_PseudoVSUXEI16_V_MF2_M1_MASK 9090 +#define RISCV_PseudoVSUXEI16_V_MF2_M2 9091 +#define RISCV_PseudoVSUXEI16_V_MF2_M2_MASK 9092 +#define RISCV_PseudoVSUXEI16_V_MF2_MF2 9093 +#define RISCV_PseudoVSUXEI16_V_MF2_MF2_MASK 9094 +#define RISCV_PseudoVSUXEI16_V_MF2_MF4 9095 +#define RISCV_PseudoVSUXEI16_V_MF2_MF4_MASK 9096 +#define RISCV_PseudoVSUXEI16_V_MF4_M1 9097 +#define RISCV_PseudoVSUXEI16_V_MF4_M1_MASK 9098 +#define RISCV_PseudoVSUXEI16_V_MF4_MF2 9099 +#define RISCV_PseudoVSUXEI16_V_MF4_MF2_MASK 9100 +#define RISCV_PseudoVSUXEI16_V_MF4_MF4 9101 +#define RISCV_PseudoVSUXEI16_V_MF4_MF4_MASK 9102 +#define RISCV_PseudoVSUXEI16_V_MF4_MF8 9103 +#define RISCV_PseudoVSUXEI16_V_MF4_MF8_MASK 9104 +#define RISCV_PseudoVSUXEI32_V_M1_M1 9105 +#define RISCV_PseudoVSUXEI32_V_M1_M1_MASK 9106 +#define RISCV_PseudoVSUXEI32_V_M1_M2 9107 +#define RISCV_PseudoVSUXEI32_V_M1_M2_MASK 9108 +#define RISCV_PseudoVSUXEI32_V_M1_MF2 9109 +#define RISCV_PseudoVSUXEI32_V_M1_MF2_MASK 9110 +#define RISCV_PseudoVSUXEI32_V_M1_MF4 9111 +#define RISCV_PseudoVSUXEI32_V_M1_MF4_MASK 9112 +#define RISCV_PseudoVSUXEI32_V_M2_M1 9113 +#define RISCV_PseudoVSUXEI32_V_M2_M1_MASK 9114 +#define RISCV_PseudoVSUXEI32_V_M2_M2 9115 +#define RISCV_PseudoVSUXEI32_V_M2_M2_MASK 9116 +#define RISCV_PseudoVSUXEI32_V_M2_M4 9117 +#define RISCV_PseudoVSUXEI32_V_M2_M4_MASK 9118 +#define RISCV_PseudoVSUXEI32_V_M2_MF2 9119 +#define RISCV_PseudoVSUXEI32_V_M2_MF2_MASK 9120 +#define RISCV_PseudoVSUXEI32_V_M4_M1 9121 +#define RISCV_PseudoVSUXEI32_V_M4_M1_MASK 9122 +#define RISCV_PseudoVSUXEI32_V_M4_M2 9123 +#define RISCV_PseudoVSUXEI32_V_M4_M2_MASK 9124 +#define RISCV_PseudoVSUXEI32_V_M4_M4 9125 +#define RISCV_PseudoVSUXEI32_V_M4_M4_MASK 9126 +#define RISCV_PseudoVSUXEI32_V_M4_M8 9127 +#define RISCV_PseudoVSUXEI32_V_M4_M8_MASK 9128 +#define RISCV_PseudoVSUXEI32_V_M8_M2 9129 +#define RISCV_PseudoVSUXEI32_V_M8_M2_MASK 9130 +#define RISCV_PseudoVSUXEI32_V_M8_M4 9131 +#define RISCV_PseudoVSUXEI32_V_M8_M4_MASK 9132 +#define RISCV_PseudoVSUXEI32_V_M8_M8 9133 +#define RISCV_PseudoVSUXEI32_V_M8_M8_MASK 9134 +#define RISCV_PseudoVSUXEI32_V_MF2_M1 9135 +#define RISCV_PseudoVSUXEI32_V_MF2_M1_MASK 9136 +#define RISCV_PseudoVSUXEI32_V_MF2_MF2 9137 +#define RISCV_PseudoVSUXEI32_V_MF2_MF2_MASK 9138 +#define RISCV_PseudoVSUXEI32_V_MF2_MF4 9139 +#define RISCV_PseudoVSUXEI32_V_MF2_MF4_MASK 9140 +#define RISCV_PseudoVSUXEI32_V_MF2_MF8 9141 +#define RISCV_PseudoVSUXEI32_V_MF2_MF8_MASK 9142 +#define RISCV_PseudoVSUXEI64_V_M1_M1 9143 +#define RISCV_PseudoVSUXEI64_V_M1_M1_MASK 9144 +#define RISCV_PseudoVSUXEI64_V_M1_MF2 9145 +#define RISCV_PseudoVSUXEI64_V_M1_MF2_MASK 9146 +#define RISCV_PseudoVSUXEI64_V_M1_MF4 9147 +#define RISCV_PseudoVSUXEI64_V_M1_MF4_MASK 9148 +#define RISCV_PseudoVSUXEI64_V_M1_MF8 9149 +#define RISCV_PseudoVSUXEI64_V_M1_MF8_MASK 9150 +#define RISCV_PseudoVSUXEI64_V_M2_M1 9151 +#define RISCV_PseudoVSUXEI64_V_M2_M1_MASK 9152 +#define RISCV_PseudoVSUXEI64_V_M2_M2 9153 +#define RISCV_PseudoVSUXEI64_V_M2_M2_MASK 9154 +#define RISCV_PseudoVSUXEI64_V_M2_MF2 9155 +#define RISCV_PseudoVSUXEI64_V_M2_MF2_MASK 9156 +#define RISCV_PseudoVSUXEI64_V_M2_MF4 9157 +#define RISCV_PseudoVSUXEI64_V_M2_MF4_MASK 9158 +#define RISCV_PseudoVSUXEI64_V_M4_M1 9159 +#define RISCV_PseudoVSUXEI64_V_M4_M1_MASK 9160 +#define RISCV_PseudoVSUXEI64_V_M4_M2 9161 +#define RISCV_PseudoVSUXEI64_V_M4_M2_MASK 9162 +#define RISCV_PseudoVSUXEI64_V_M4_M4 9163 +#define RISCV_PseudoVSUXEI64_V_M4_M4_MASK 9164 +#define RISCV_PseudoVSUXEI64_V_M4_MF2 9165 +#define RISCV_PseudoVSUXEI64_V_M4_MF2_MASK 9166 +#define RISCV_PseudoVSUXEI64_V_M8_M1 9167 +#define RISCV_PseudoVSUXEI64_V_M8_M1_MASK 9168 +#define RISCV_PseudoVSUXEI64_V_M8_M2 9169 +#define RISCV_PseudoVSUXEI64_V_M8_M2_MASK 9170 +#define RISCV_PseudoVSUXEI64_V_M8_M4 9171 +#define RISCV_PseudoVSUXEI64_V_M8_M4_MASK 9172 +#define RISCV_PseudoVSUXEI64_V_M8_M8 9173 +#define RISCV_PseudoVSUXEI64_V_M8_M8_MASK 9174 +#define RISCV_PseudoVSUXEI8_V_M1_M1 9175 +#define RISCV_PseudoVSUXEI8_V_M1_M1_MASK 9176 +#define RISCV_PseudoVSUXEI8_V_M1_M2 9177 +#define RISCV_PseudoVSUXEI8_V_M1_M2_MASK 9178 +#define RISCV_PseudoVSUXEI8_V_M1_M4 9179 +#define RISCV_PseudoVSUXEI8_V_M1_M4_MASK 9180 +#define RISCV_PseudoVSUXEI8_V_M1_M8 9181 +#define RISCV_PseudoVSUXEI8_V_M1_M8_MASK 9182 +#define RISCV_PseudoVSUXEI8_V_M2_M2 9183 +#define RISCV_PseudoVSUXEI8_V_M2_M2_MASK 9184 +#define RISCV_PseudoVSUXEI8_V_M2_M4 9185 +#define RISCV_PseudoVSUXEI8_V_M2_M4_MASK 9186 +#define RISCV_PseudoVSUXEI8_V_M2_M8 9187 +#define RISCV_PseudoVSUXEI8_V_M2_M8_MASK 9188 +#define RISCV_PseudoVSUXEI8_V_M4_M4 9189 +#define RISCV_PseudoVSUXEI8_V_M4_M4_MASK 9190 +#define RISCV_PseudoVSUXEI8_V_M4_M8 9191 +#define RISCV_PseudoVSUXEI8_V_M4_M8_MASK 9192 +#define RISCV_PseudoVSUXEI8_V_M8_M8 9193 +#define RISCV_PseudoVSUXEI8_V_M8_M8_MASK 9194 +#define RISCV_PseudoVSUXEI8_V_MF2_M1 9195 +#define RISCV_PseudoVSUXEI8_V_MF2_M1_MASK 9196 +#define RISCV_PseudoVSUXEI8_V_MF2_M2 9197 +#define RISCV_PseudoVSUXEI8_V_MF2_M2_MASK 9198 +#define RISCV_PseudoVSUXEI8_V_MF2_M4 9199 +#define RISCV_PseudoVSUXEI8_V_MF2_M4_MASK 9200 +#define RISCV_PseudoVSUXEI8_V_MF2_MF2 9201 +#define RISCV_PseudoVSUXEI8_V_MF2_MF2_MASK 9202 +#define RISCV_PseudoVSUXEI8_V_MF4_M1 9203 +#define RISCV_PseudoVSUXEI8_V_MF4_M1_MASK 9204 +#define RISCV_PseudoVSUXEI8_V_MF4_M2 9205 +#define RISCV_PseudoVSUXEI8_V_MF4_M2_MASK 9206 +#define RISCV_PseudoVSUXEI8_V_MF4_MF2 9207 +#define RISCV_PseudoVSUXEI8_V_MF4_MF2_MASK 9208 +#define RISCV_PseudoVSUXEI8_V_MF4_MF4 9209 +#define RISCV_PseudoVSUXEI8_V_MF4_MF4_MASK 9210 +#define RISCV_PseudoVSUXEI8_V_MF8_M1 9211 +#define RISCV_PseudoVSUXEI8_V_MF8_M1_MASK 9212 +#define RISCV_PseudoVSUXEI8_V_MF8_MF2 9213 +#define RISCV_PseudoVSUXEI8_V_MF8_MF2_MASK 9214 +#define RISCV_PseudoVSUXEI8_V_MF8_MF4 9215 +#define RISCV_PseudoVSUXEI8_V_MF8_MF4_MASK 9216 +#define RISCV_PseudoVSUXEI8_V_MF8_MF8 9217 +#define RISCV_PseudoVSUXEI8_V_MF8_MF8_MASK 9218 +#define RISCV_PseudoVSUXSEG2EI16_V_M1_M1 9219 +#define RISCV_PseudoVSUXSEG2EI16_V_M1_M1_MASK 9220 +#define RISCV_PseudoVSUXSEG2EI16_V_M1_M2 9221 +#define RISCV_PseudoVSUXSEG2EI16_V_M1_M2_MASK 9222 +#define RISCV_PseudoVSUXSEG2EI16_V_M1_M4 9223 +#define RISCV_PseudoVSUXSEG2EI16_V_M1_M4_MASK 9224 +#define RISCV_PseudoVSUXSEG2EI16_V_M1_MF2 9225 +#define RISCV_PseudoVSUXSEG2EI16_V_M1_MF2_MASK 9226 +#define RISCV_PseudoVSUXSEG2EI16_V_M2_M1 9227 +#define RISCV_PseudoVSUXSEG2EI16_V_M2_M1_MASK 9228 +#define RISCV_PseudoVSUXSEG2EI16_V_M2_M2 9229 +#define RISCV_PseudoVSUXSEG2EI16_V_M2_M2_MASK 9230 +#define RISCV_PseudoVSUXSEG2EI16_V_M2_M4 9231 +#define RISCV_PseudoVSUXSEG2EI16_V_M2_M4_MASK 9232 +#define RISCV_PseudoVSUXSEG2EI16_V_M4_M2 9233 +#define RISCV_PseudoVSUXSEG2EI16_V_M4_M2_MASK 9234 +#define RISCV_PseudoVSUXSEG2EI16_V_M4_M4 9235 +#define RISCV_PseudoVSUXSEG2EI16_V_M4_M4_MASK 9236 +#define RISCV_PseudoVSUXSEG2EI16_V_M8_M4 9237 +#define RISCV_PseudoVSUXSEG2EI16_V_M8_M4_MASK 9238 +#define RISCV_PseudoVSUXSEG2EI16_V_MF2_M1 9239 +#define RISCV_PseudoVSUXSEG2EI16_V_MF2_M1_MASK 9240 +#define RISCV_PseudoVSUXSEG2EI16_V_MF2_M2 9241 +#define RISCV_PseudoVSUXSEG2EI16_V_MF2_M2_MASK 9242 +#define RISCV_PseudoVSUXSEG2EI16_V_MF2_MF2 9243 +#define RISCV_PseudoVSUXSEG2EI16_V_MF2_MF2_MASK 9244 +#define RISCV_PseudoVSUXSEG2EI16_V_MF2_MF4 9245 +#define RISCV_PseudoVSUXSEG2EI16_V_MF2_MF4_MASK 9246 +#define RISCV_PseudoVSUXSEG2EI16_V_MF4_M1 9247 +#define RISCV_PseudoVSUXSEG2EI16_V_MF4_M1_MASK 9248 +#define RISCV_PseudoVSUXSEG2EI16_V_MF4_MF2 9249 +#define RISCV_PseudoVSUXSEG2EI16_V_MF4_MF2_MASK 9250 +#define RISCV_PseudoVSUXSEG2EI16_V_MF4_MF4 9251 +#define RISCV_PseudoVSUXSEG2EI16_V_MF4_MF4_MASK 9252 +#define RISCV_PseudoVSUXSEG2EI16_V_MF4_MF8 9253 +#define RISCV_PseudoVSUXSEG2EI16_V_MF4_MF8_MASK 9254 +#define RISCV_PseudoVSUXSEG2EI32_V_M1_M1 9255 +#define RISCV_PseudoVSUXSEG2EI32_V_M1_M1_MASK 9256 +#define RISCV_PseudoVSUXSEG2EI32_V_M1_M2 9257 +#define RISCV_PseudoVSUXSEG2EI32_V_M1_M2_MASK 9258 +#define RISCV_PseudoVSUXSEG2EI32_V_M1_MF2 9259 +#define RISCV_PseudoVSUXSEG2EI32_V_M1_MF2_MASK 9260 +#define RISCV_PseudoVSUXSEG2EI32_V_M1_MF4 9261 +#define RISCV_PseudoVSUXSEG2EI32_V_M1_MF4_MASK 9262 +#define RISCV_PseudoVSUXSEG2EI32_V_M2_M1 9263 +#define RISCV_PseudoVSUXSEG2EI32_V_M2_M1_MASK 9264 +#define RISCV_PseudoVSUXSEG2EI32_V_M2_M2 9265 +#define RISCV_PseudoVSUXSEG2EI32_V_M2_M2_MASK 9266 +#define RISCV_PseudoVSUXSEG2EI32_V_M2_M4 9267 +#define RISCV_PseudoVSUXSEG2EI32_V_M2_M4_MASK 9268 +#define RISCV_PseudoVSUXSEG2EI32_V_M2_MF2 9269 +#define RISCV_PseudoVSUXSEG2EI32_V_M2_MF2_MASK 9270 +#define RISCV_PseudoVSUXSEG2EI32_V_M4_M1 9271 +#define RISCV_PseudoVSUXSEG2EI32_V_M4_M1_MASK 9272 +#define RISCV_PseudoVSUXSEG2EI32_V_M4_M2 9273 +#define RISCV_PseudoVSUXSEG2EI32_V_M4_M2_MASK 9274 +#define RISCV_PseudoVSUXSEG2EI32_V_M4_M4 9275 +#define RISCV_PseudoVSUXSEG2EI32_V_M4_M4_MASK 9276 +#define RISCV_PseudoVSUXSEG2EI32_V_M8_M2 9277 +#define RISCV_PseudoVSUXSEG2EI32_V_M8_M2_MASK 9278 +#define RISCV_PseudoVSUXSEG2EI32_V_M8_M4 9279 +#define RISCV_PseudoVSUXSEG2EI32_V_M8_M4_MASK 9280 +#define RISCV_PseudoVSUXSEG2EI32_V_MF2_M1 9281 +#define RISCV_PseudoVSUXSEG2EI32_V_MF2_M1_MASK 9282 +#define RISCV_PseudoVSUXSEG2EI32_V_MF2_MF2 9283 +#define RISCV_PseudoVSUXSEG2EI32_V_MF2_MF2_MASK 9284 +#define RISCV_PseudoVSUXSEG2EI32_V_MF2_MF4 9285 +#define RISCV_PseudoVSUXSEG2EI32_V_MF2_MF4_MASK 9286 +#define RISCV_PseudoVSUXSEG2EI32_V_MF2_MF8 9287 +#define RISCV_PseudoVSUXSEG2EI32_V_MF2_MF8_MASK 9288 +#define RISCV_PseudoVSUXSEG2EI64_V_M1_M1 9289 +#define RISCV_PseudoVSUXSEG2EI64_V_M1_M1_MASK 9290 +#define RISCV_PseudoVSUXSEG2EI64_V_M1_MF2 9291 +#define RISCV_PseudoVSUXSEG2EI64_V_M1_MF2_MASK 9292 +#define RISCV_PseudoVSUXSEG2EI64_V_M1_MF4 9293 +#define RISCV_PseudoVSUXSEG2EI64_V_M1_MF4_MASK 9294 +#define RISCV_PseudoVSUXSEG2EI64_V_M1_MF8 9295 +#define RISCV_PseudoVSUXSEG2EI64_V_M1_MF8_MASK 9296 +#define RISCV_PseudoVSUXSEG2EI64_V_M2_M1 9297 +#define RISCV_PseudoVSUXSEG2EI64_V_M2_M1_MASK 9298 +#define RISCV_PseudoVSUXSEG2EI64_V_M2_M2 9299 +#define RISCV_PseudoVSUXSEG2EI64_V_M2_M2_MASK 9300 +#define RISCV_PseudoVSUXSEG2EI64_V_M2_MF2 9301 +#define RISCV_PseudoVSUXSEG2EI64_V_M2_MF2_MASK 9302 +#define RISCV_PseudoVSUXSEG2EI64_V_M2_MF4 9303 +#define RISCV_PseudoVSUXSEG2EI64_V_M2_MF4_MASK 9304 +#define RISCV_PseudoVSUXSEG2EI64_V_M4_M1 9305 +#define RISCV_PseudoVSUXSEG2EI64_V_M4_M1_MASK 9306 +#define RISCV_PseudoVSUXSEG2EI64_V_M4_M2 9307 +#define RISCV_PseudoVSUXSEG2EI64_V_M4_M2_MASK 9308 +#define RISCV_PseudoVSUXSEG2EI64_V_M4_M4 9309 +#define RISCV_PseudoVSUXSEG2EI64_V_M4_M4_MASK 9310 +#define RISCV_PseudoVSUXSEG2EI64_V_M4_MF2 9311 +#define RISCV_PseudoVSUXSEG2EI64_V_M4_MF2_MASK 9312 +#define RISCV_PseudoVSUXSEG2EI64_V_M8_M1 9313 +#define RISCV_PseudoVSUXSEG2EI64_V_M8_M1_MASK 9314 +#define RISCV_PseudoVSUXSEG2EI64_V_M8_M2 9315 +#define RISCV_PseudoVSUXSEG2EI64_V_M8_M2_MASK 9316 +#define RISCV_PseudoVSUXSEG2EI64_V_M8_M4 9317 +#define RISCV_PseudoVSUXSEG2EI64_V_M8_M4_MASK 9318 +#define RISCV_PseudoVSUXSEG2EI8_V_M1_M1 9319 +#define RISCV_PseudoVSUXSEG2EI8_V_M1_M1_MASK 9320 +#define RISCV_PseudoVSUXSEG2EI8_V_M1_M2 9321 +#define RISCV_PseudoVSUXSEG2EI8_V_M1_M2_MASK 9322 +#define RISCV_PseudoVSUXSEG2EI8_V_M1_M4 9323 +#define RISCV_PseudoVSUXSEG2EI8_V_M1_M4_MASK 9324 +#define RISCV_PseudoVSUXSEG2EI8_V_M2_M2 9325 +#define RISCV_PseudoVSUXSEG2EI8_V_M2_M2_MASK 9326 +#define RISCV_PseudoVSUXSEG2EI8_V_M2_M4 9327 +#define RISCV_PseudoVSUXSEG2EI8_V_M2_M4_MASK 9328 +#define RISCV_PseudoVSUXSEG2EI8_V_M4_M4 9329 +#define RISCV_PseudoVSUXSEG2EI8_V_M4_M4_MASK 9330 +#define RISCV_PseudoVSUXSEG2EI8_V_MF2_M1 9331 +#define RISCV_PseudoVSUXSEG2EI8_V_MF2_M1_MASK 9332 +#define RISCV_PseudoVSUXSEG2EI8_V_MF2_M2 9333 +#define RISCV_PseudoVSUXSEG2EI8_V_MF2_M2_MASK 9334 +#define RISCV_PseudoVSUXSEG2EI8_V_MF2_M4 9335 +#define RISCV_PseudoVSUXSEG2EI8_V_MF2_M4_MASK 9336 +#define RISCV_PseudoVSUXSEG2EI8_V_MF2_MF2 9337 +#define RISCV_PseudoVSUXSEG2EI8_V_MF2_MF2_MASK 9338 +#define RISCV_PseudoVSUXSEG2EI8_V_MF4_M1 9339 +#define RISCV_PseudoVSUXSEG2EI8_V_MF4_M1_MASK 9340 +#define RISCV_PseudoVSUXSEG2EI8_V_MF4_M2 9341 +#define RISCV_PseudoVSUXSEG2EI8_V_MF4_M2_MASK 9342 +#define RISCV_PseudoVSUXSEG2EI8_V_MF4_MF2 9343 +#define RISCV_PseudoVSUXSEG2EI8_V_MF4_MF2_MASK 9344 +#define RISCV_PseudoVSUXSEG2EI8_V_MF4_MF4 9345 +#define RISCV_PseudoVSUXSEG2EI8_V_MF4_MF4_MASK 9346 +#define RISCV_PseudoVSUXSEG2EI8_V_MF8_M1 9347 +#define RISCV_PseudoVSUXSEG2EI8_V_MF8_M1_MASK 9348 +#define RISCV_PseudoVSUXSEG2EI8_V_MF8_MF2 9349 +#define RISCV_PseudoVSUXSEG2EI8_V_MF8_MF2_MASK 9350 +#define RISCV_PseudoVSUXSEG2EI8_V_MF8_MF4 9351 +#define RISCV_PseudoVSUXSEG2EI8_V_MF8_MF4_MASK 9352 +#define RISCV_PseudoVSUXSEG2EI8_V_MF8_MF8 9353 +#define RISCV_PseudoVSUXSEG2EI8_V_MF8_MF8_MASK 9354 +#define RISCV_PseudoVSUXSEG3EI16_V_M1_M1 9355 +#define RISCV_PseudoVSUXSEG3EI16_V_M1_M1_MASK 9356 +#define RISCV_PseudoVSUXSEG3EI16_V_M1_M2 9357 +#define RISCV_PseudoVSUXSEG3EI16_V_M1_M2_MASK 9358 +#define RISCV_PseudoVSUXSEG3EI16_V_M1_MF2 9359 +#define RISCV_PseudoVSUXSEG3EI16_V_M1_MF2_MASK 9360 +#define RISCV_PseudoVSUXSEG3EI16_V_M2_M1 9361 +#define RISCV_PseudoVSUXSEG3EI16_V_M2_M1_MASK 9362 +#define RISCV_PseudoVSUXSEG3EI16_V_M2_M2 9363 +#define RISCV_PseudoVSUXSEG3EI16_V_M2_M2_MASK 9364 +#define RISCV_PseudoVSUXSEG3EI16_V_M4_M2 9365 +#define RISCV_PseudoVSUXSEG3EI16_V_M4_M2_MASK 9366 +#define RISCV_PseudoVSUXSEG3EI16_V_MF2_M1 9367 +#define RISCV_PseudoVSUXSEG3EI16_V_MF2_M1_MASK 9368 +#define RISCV_PseudoVSUXSEG3EI16_V_MF2_M2 9369 +#define RISCV_PseudoVSUXSEG3EI16_V_MF2_M2_MASK 9370 +#define RISCV_PseudoVSUXSEG3EI16_V_MF2_MF2 9371 +#define RISCV_PseudoVSUXSEG3EI16_V_MF2_MF2_MASK 9372 +#define RISCV_PseudoVSUXSEG3EI16_V_MF2_MF4 9373 +#define RISCV_PseudoVSUXSEG3EI16_V_MF2_MF4_MASK 9374 +#define RISCV_PseudoVSUXSEG3EI16_V_MF4_M1 9375 +#define RISCV_PseudoVSUXSEG3EI16_V_MF4_M1_MASK 9376 +#define RISCV_PseudoVSUXSEG3EI16_V_MF4_MF2 9377 +#define RISCV_PseudoVSUXSEG3EI16_V_MF4_MF2_MASK 9378 +#define RISCV_PseudoVSUXSEG3EI16_V_MF4_MF4 9379 +#define RISCV_PseudoVSUXSEG3EI16_V_MF4_MF4_MASK 9380 +#define RISCV_PseudoVSUXSEG3EI16_V_MF4_MF8 9381 +#define RISCV_PseudoVSUXSEG3EI16_V_MF4_MF8_MASK 9382 +#define RISCV_PseudoVSUXSEG3EI32_V_M1_M1 9383 +#define RISCV_PseudoVSUXSEG3EI32_V_M1_M1_MASK 9384 +#define RISCV_PseudoVSUXSEG3EI32_V_M1_M2 9385 +#define RISCV_PseudoVSUXSEG3EI32_V_M1_M2_MASK 9386 +#define RISCV_PseudoVSUXSEG3EI32_V_M1_MF2 9387 +#define RISCV_PseudoVSUXSEG3EI32_V_M1_MF2_MASK 9388 +#define RISCV_PseudoVSUXSEG3EI32_V_M1_MF4 9389 +#define RISCV_PseudoVSUXSEG3EI32_V_M1_MF4_MASK 9390 +#define RISCV_PseudoVSUXSEG3EI32_V_M2_M1 9391 +#define RISCV_PseudoVSUXSEG3EI32_V_M2_M1_MASK 9392 +#define RISCV_PseudoVSUXSEG3EI32_V_M2_M2 9393 +#define RISCV_PseudoVSUXSEG3EI32_V_M2_M2_MASK 9394 +#define RISCV_PseudoVSUXSEG3EI32_V_M2_MF2 9395 +#define RISCV_PseudoVSUXSEG3EI32_V_M2_MF2_MASK 9396 +#define RISCV_PseudoVSUXSEG3EI32_V_M4_M1 9397 +#define RISCV_PseudoVSUXSEG3EI32_V_M4_M1_MASK 9398 +#define RISCV_PseudoVSUXSEG3EI32_V_M4_M2 9399 +#define RISCV_PseudoVSUXSEG3EI32_V_M4_M2_MASK 9400 +#define RISCV_PseudoVSUXSEG3EI32_V_M8_M2 9401 +#define RISCV_PseudoVSUXSEG3EI32_V_M8_M2_MASK 9402 +#define RISCV_PseudoVSUXSEG3EI32_V_MF2_M1 9403 +#define RISCV_PseudoVSUXSEG3EI32_V_MF2_M1_MASK 9404 +#define RISCV_PseudoVSUXSEG3EI32_V_MF2_MF2 9405 +#define RISCV_PseudoVSUXSEG3EI32_V_MF2_MF2_MASK 9406 +#define RISCV_PseudoVSUXSEG3EI32_V_MF2_MF4 9407 +#define RISCV_PseudoVSUXSEG3EI32_V_MF2_MF4_MASK 9408 +#define RISCV_PseudoVSUXSEG3EI32_V_MF2_MF8 9409 +#define RISCV_PseudoVSUXSEG3EI32_V_MF2_MF8_MASK 9410 +#define RISCV_PseudoVSUXSEG3EI64_V_M1_M1 9411 +#define RISCV_PseudoVSUXSEG3EI64_V_M1_M1_MASK 9412 +#define RISCV_PseudoVSUXSEG3EI64_V_M1_MF2 9413 +#define RISCV_PseudoVSUXSEG3EI64_V_M1_MF2_MASK 9414 +#define RISCV_PseudoVSUXSEG3EI64_V_M1_MF4 9415 +#define RISCV_PseudoVSUXSEG3EI64_V_M1_MF4_MASK 9416 +#define RISCV_PseudoVSUXSEG3EI64_V_M1_MF8 9417 +#define RISCV_PseudoVSUXSEG3EI64_V_M1_MF8_MASK 9418 +#define RISCV_PseudoVSUXSEG3EI64_V_M2_M1 9419 +#define RISCV_PseudoVSUXSEG3EI64_V_M2_M1_MASK 9420 +#define RISCV_PseudoVSUXSEG3EI64_V_M2_M2 9421 +#define RISCV_PseudoVSUXSEG3EI64_V_M2_M2_MASK 9422 +#define RISCV_PseudoVSUXSEG3EI64_V_M2_MF2 9423 +#define RISCV_PseudoVSUXSEG3EI64_V_M2_MF2_MASK 9424 +#define RISCV_PseudoVSUXSEG3EI64_V_M2_MF4 9425 +#define RISCV_PseudoVSUXSEG3EI64_V_M2_MF4_MASK 9426 +#define RISCV_PseudoVSUXSEG3EI64_V_M4_M1 9427 +#define RISCV_PseudoVSUXSEG3EI64_V_M4_M1_MASK 9428 +#define RISCV_PseudoVSUXSEG3EI64_V_M4_M2 9429 +#define RISCV_PseudoVSUXSEG3EI64_V_M4_M2_MASK 9430 +#define RISCV_PseudoVSUXSEG3EI64_V_M4_MF2 9431 +#define RISCV_PseudoVSUXSEG3EI64_V_M4_MF2_MASK 9432 +#define RISCV_PseudoVSUXSEG3EI64_V_M8_M1 9433 +#define RISCV_PseudoVSUXSEG3EI64_V_M8_M1_MASK 9434 +#define RISCV_PseudoVSUXSEG3EI64_V_M8_M2 9435 +#define RISCV_PseudoVSUXSEG3EI64_V_M8_M2_MASK 9436 +#define RISCV_PseudoVSUXSEG3EI8_V_M1_M1 9437 +#define RISCV_PseudoVSUXSEG3EI8_V_M1_M1_MASK 9438 +#define RISCV_PseudoVSUXSEG3EI8_V_M1_M2 9439 +#define RISCV_PseudoVSUXSEG3EI8_V_M1_M2_MASK 9440 +#define RISCV_PseudoVSUXSEG3EI8_V_M2_M2 9441 +#define RISCV_PseudoVSUXSEG3EI8_V_M2_M2_MASK 9442 +#define RISCV_PseudoVSUXSEG3EI8_V_MF2_M1 9443 +#define RISCV_PseudoVSUXSEG3EI8_V_MF2_M1_MASK 9444 +#define RISCV_PseudoVSUXSEG3EI8_V_MF2_M2 9445 +#define RISCV_PseudoVSUXSEG3EI8_V_MF2_M2_MASK 9446 +#define RISCV_PseudoVSUXSEG3EI8_V_MF2_MF2 9447 +#define RISCV_PseudoVSUXSEG3EI8_V_MF2_MF2_MASK 9448 +#define RISCV_PseudoVSUXSEG3EI8_V_MF4_M1 9449 +#define RISCV_PseudoVSUXSEG3EI8_V_MF4_M1_MASK 9450 +#define RISCV_PseudoVSUXSEG3EI8_V_MF4_M2 9451 +#define RISCV_PseudoVSUXSEG3EI8_V_MF4_M2_MASK 9452 +#define RISCV_PseudoVSUXSEG3EI8_V_MF4_MF2 9453 +#define RISCV_PseudoVSUXSEG3EI8_V_MF4_MF2_MASK 9454 +#define RISCV_PseudoVSUXSEG3EI8_V_MF4_MF4 9455 +#define RISCV_PseudoVSUXSEG3EI8_V_MF4_MF4_MASK 9456 +#define RISCV_PseudoVSUXSEG3EI8_V_MF8_M1 9457 +#define RISCV_PseudoVSUXSEG3EI8_V_MF8_M1_MASK 9458 +#define RISCV_PseudoVSUXSEG3EI8_V_MF8_MF2 9459 +#define RISCV_PseudoVSUXSEG3EI8_V_MF8_MF2_MASK 9460 +#define RISCV_PseudoVSUXSEG3EI8_V_MF8_MF4 9461 +#define RISCV_PseudoVSUXSEG3EI8_V_MF8_MF4_MASK 9462 +#define RISCV_PseudoVSUXSEG3EI8_V_MF8_MF8 9463 +#define RISCV_PseudoVSUXSEG3EI8_V_MF8_MF8_MASK 9464 +#define RISCV_PseudoVSUXSEG4EI16_V_M1_M1 9465 +#define RISCV_PseudoVSUXSEG4EI16_V_M1_M1_MASK 9466 +#define RISCV_PseudoVSUXSEG4EI16_V_M1_M2 9467 +#define RISCV_PseudoVSUXSEG4EI16_V_M1_M2_MASK 9468 +#define RISCV_PseudoVSUXSEG4EI16_V_M1_MF2 9469 +#define RISCV_PseudoVSUXSEG4EI16_V_M1_MF2_MASK 9470 +#define RISCV_PseudoVSUXSEG4EI16_V_M2_M1 9471 +#define RISCV_PseudoVSUXSEG4EI16_V_M2_M1_MASK 9472 +#define RISCV_PseudoVSUXSEG4EI16_V_M2_M2 9473 +#define RISCV_PseudoVSUXSEG4EI16_V_M2_M2_MASK 9474 +#define RISCV_PseudoVSUXSEG4EI16_V_M4_M2 9475 +#define RISCV_PseudoVSUXSEG4EI16_V_M4_M2_MASK 9476 +#define RISCV_PseudoVSUXSEG4EI16_V_MF2_M1 9477 +#define RISCV_PseudoVSUXSEG4EI16_V_MF2_M1_MASK 9478 +#define RISCV_PseudoVSUXSEG4EI16_V_MF2_M2 9479 +#define RISCV_PseudoVSUXSEG4EI16_V_MF2_M2_MASK 9480 +#define RISCV_PseudoVSUXSEG4EI16_V_MF2_MF2 9481 +#define RISCV_PseudoVSUXSEG4EI16_V_MF2_MF2_MASK 9482 +#define RISCV_PseudoVSUXSEG4EI16_V_MF2_MF4 9483 +#define RISCV_PseudoVSUXSEG4EI16_V_MF2_MF4_MASK 9484 +#define RISCV_PseudoVSUXSEG4EI16_V_MF4_M1 9485 +#define RISCV_PseudoVSUXSEG4EI16_V_MF4_M1_MASK 9486 +#define RISCV_PseudoVSUXSEG4EI16_V_MF4_MF2 9487 +#define RISCV_PseudoVSUXSEG4EI16_V_MF4_MF2_MASK 9488 +#define RISCV_PseudoVSUXSEG4EI16_V_MF4_MF4 9489 +#define RISCV_PseudoVSUXSEG4EI16_V_MF4_MF4_MASK 9490 +#define RISCV_PseudoVSUXSEG4EI16_V_MF4_MF8 9491 +#define RISCV_PseudoVSUXSEG4EI16_V_MF4_MF8_MASK 9492 +#define RISCV_PseudoVSUXSEG4EI32_V_M1_M1 9493 +#define RISCV_PseudoVSUXSEG4EI32_V_M1_M1_MASK 9494 +#define RISCV_PseudoVSUXSEG4EI32_V_M1_M2 9495 +#define RISCV_PseudoVSUXSEG4EI32_V_M1_M2_MASK 9496 +#define RISCV_PseudoVSUXSEG4EI32_V_M1_MF2 9497 +#define RISCV_PseudoVSUXSEG4EI32_V_M1_MF2_MASK 9498 +#define RISCV_PseudoVSUXSEG4EI32_V_M1_MF4 9499 +#define RISCV_PseudoVSUXSEG4EI32_V_M1_MF4_MASK 9500 +#define RISCV_PseudoVSUXSEG4EI32_V_M2_M1 9501 +#define RISCV_PseudoVSUXSEG4EI32_V_M2_M1_MASK 9502 +#define RISCV_PseudoVSUXSEG4EI32_V_M2_M2 9503 +#define RISCV_PseudoVSUXSEG4EI32_V_M2_M2_MASK 9504 +#define RISCV_PseudoVSUXSEG4EI32_V_M2_MF2 9505 +#define RISCV_PseudoVSUXSEG4EI32_V_M2_MF2_MASK 9506 +#define RISCV_PseudoVSUXSEG4EI32_V_M4_M1 9507 +#define RISCV_PseudoVSUXSEG4EI32_V_M4_M1_MASK 9508 +#define RISCV_PseudoVSUXSEG4EI32_V_M4_M2 9509 +#define RISCV_PseudoVSUXSEG4EI32_V_M4_M2_MASK 9510 +#define RISCV_PseudoVSUXSEG4EI32_V_M8_M2 9511 +#define RISCV_PseudoVSUXSEG4EI32_V_M8_M2_MASK 9512 +#define RISCV_PseudoVSUXSEG4EI32_V_MF2_M1 9513 +#define RISCV_PseudoVSUXSEG4EI32_V_MF2_M1_MASK 9514 +#define RISCV_PseudoVSUXSEG4EI32_V_MF2_MF2 9515 +#define RISCV_PseudoVSUXSEG4EI32_V_MF2_MF2_MASK 9516 +#define RISCV_PseudoVSUXSEG4EI32_V_MF2_MF4 9517 +#define RISCV_PseudoVSUXSEG4EI32_V_MF2_MF4_MASK 9518 +#define RISCV_PseudoVSUXSEG4EI32_V_MF2_MF8 9519 +#define RISCV_PseudoVSUXSEG4EI32_V_MF2_MF8_MASK 9520 +#define RISCV_PseudoVSUXSEG4EI64_V_M1_M1 9521 +#define RISCV_PseudoVSUXSEG4EI64_V_M1_M1_MASK 9522 +#define RISCV_PseudoVSUXSEG4EI64_V_M1_MF2 9523 +#define RISCV_PseudoVSUXSEG4EI64_V_M1_MF2_MASK 9524 +#define RISCV_PseudoVSUXSEG4EI64_V_M1_MF4 9525 +#define RISCV_PseudoVSUXSEG4EI64_V_M1_MF4_MASK 9526 +#define RISCV_PseudoVSUXSEG4EI64_V_M1_MF8 9527 +#define RISCV_PseudoVSUXSEG4EI64_V_M1_MF8_MASK 9528 +#define RISCV_PseudoVSUXSEG4EI64_V_M2_M1 9529 +#define RISCV_PseudoVSUXSEG4EI64_V_M2_M1_MASK 9530 +#define RISCV_PseudoVSUXSEG4EI64_V_M2_M2 9531 +#define RISCV_PseudoVSUXSEG4EI64_V_M2_M2_MASK 9532 +#define RISCV_PseudoVSUXSEG4EI64_V_M2_MF2 9533 +#define RISCV_PseudoVSUXSEG4EI64_V_M2_MF2_MASK 9534 +#define RISCV_PseudoVSUXSEG4EI64_V_M2_MF4 9535 +#define RISCV_PseudoVSUXSEG4EI64_V_M2_MF4_MASK 9536 +#define RISCV_PseudoVSUXSEG4EI64_V_M4_M1 9537 +#define RISCV_PseudoVSUXSEG4EI64_V_M4_M1_MASK 9538 +#define RISCV_PseudoVSUXSEG4EI64_V_M4_M2 9539 +#define RISCV_PseudoVSUXSEG4EI64_V_M4_M2_MASK 9540 +#define RISCV_PseudoVSUXSEG4EI64_V_M4_MF2 9541 +#define RISCV_PseudoVSUXSEG4EI64_V_M4_MF2_MASK 9542 +#define RISCV_PseudoVSUXSEG4EI64_V_M8_M1 9543 +#define RISCV_PseudoVSUXSEG4EI64_V_M8_M1_MASK 9544 +#define RISCV_PseudoVSUXSEG4EI64_V_M8_M2 9545 +#define RISCV_PseudoVSUXSEG4EI64_V_M8_M2_MASK 9546 +#define RISCV_PseudoVSUXSEG4EI8_V_M1_M1 9547 +#define RISCV_PseudoVSUXSEG4EI8_V_M1_M1_MASK 9548 +#define RISCV_PseudoVSUXSEG4EI8_V_M1_M2 9549 +#define RISCV_PseudoVSUXSEG4EI8_V_M1_M2_MASK 9550 +#define RISCV_PseudoVSUXSEG4EI8_V_M2_M2 9551 +#define RISCV_PseudoVSUXSEG4EI8_V_M2_M2_MASK 9552 +#define RISCV_PseudoVSUXSEG4EI8_V_MF2_M1 9553 +#define RISCV_PseudoVSUXSEG4EI8_V_MF2_M1_MASK 9554 +#define RISCV_PseudoVSUXSEG4EI8_V_MF2_M2 9555 +#define RISCV_PseudoVSUXSEG4EI8_V_MF2_M2_MASK 9556 +#define RISCV_PseudoVSUXSEG4EI8_V_MF2_MF2 9557 +#define RISCV_PseudoVSUXSEG4EI8_V_MF2_MF2_MASK 9558 +#define RISCV_PseudoVSUXSEG4EI8_V_MF4_M1 9559 +#define RISCV_PseudoVSUXSEG4EI8_V_MF4_M1_MASK 9560 +#define RISCV_PseudoVSUXSEG4EI8_V_MF4_M2 9561 +#define RISCV_PseudoVSUXSEG4EI8_V_MF4_M2_MASK 9562 +#define RISCV_PseudoVSUXSEG4EI8_V_MF4_MF2 9563 +#define RISCV_PseudoVSUXSEG4EI8_V_MF4_MF2_MASK 9564 +#define RISCV_PseudoVSUXSEG4EI8_V_MF4_MF4 9565 +#define RISCV_PseudoVSUXSEG4EI8_V_MF4_MF4_MASK 9566 +#define RISCV_PseudoVSUXSEG4EI8_V_MF8_M1 9567 +#define RISCV_PseudoVSUXSEG4EI8_V_MF8_M1_MASK 9568 +#define RISCV_PseudoVSUXSEG4EI8_V_MF8_MF2 9569 +#define RISCV_PseudoVSUXSEG4EI8_V_MF8_MF2_MASK 9570 +#define RISCV_PseudoVSUXSEG4EI8_V_MF8_MF4 9571 +#define RISCV_PseudoVSUXSEG4EI8_V_MF8_MF4_MASK 9572 +#define RISCV_PseudoVSUXSEG4EI8_V_MF8_MF8 9573 +#define RISCV_PseudoVSUXSEG4EI8_V_MF8_MF8_MASK 9574 +#define RISCV_PseudoVSUXSEG5EI16_V_M1_M1 9575 +#define RISCV_PseudoVSUXSEG5EI16_V_M1_M1_MASK 9576 +#define RISCV_PseudoVSUXSEG5EI16_V_M1_MF2 9577 +#define RISCV_PseudoVSUXSEG5EI16_V_M1_MF2_MASK 9578 +#define RISCV_PseudoVSUXSEG5EI16_V_M2_M1 9579 +#define RISCV_PseudoVSUXSEG5EI16_V_M2_M1_MASK 9580 +#define RISCV_PseudoVSUXSEG5EI16_V_MF2_M1 9581 +#define RISCV_PseudoVSUXSEG5EI16_V_MF2_M1_MASK 9582 +#define RISCV_PseudoVSUXSEG5EI16_V_MF2_MF2 9583 +#define RISCV_PseudoVSUXSEG5EI16_V_MF2_MF2_MASK 9584 +#define RISCV_PseudoVSUXSEG5EI16_V_MF2_MF4 9585 +#define RISCV_PseudoVSUXSEG5EI16_V_MF2_MF4_MASK 9586 +#define RISCV_PseudoVSUXSEG5EI16_V_MF4_M1 9587 +#define RISCV_PseudoVSUXSEG5EI16_V_MF4_M1_MASK 9588 +#define RISCV_PseudoVSUXSEG5EI16_V_MF4_MF2 9589 +#define RISCV_PseudoVSUXSEG5EI16_V_MF4_MF2_MASK 9590 +#define RISCV_PseudoVSUXSEG5EI16_V_MF4_MF4 9591 +#define RISCV_PseudoVSUXSEG5EI16_V_MF4_MF4_MASK 9592 +#define RISCV_PseudoVSUXSEG5EI16_V_MF4_MF8 9593 +#define RISCV_PseudoVSUXSEG5EI16_V_MF4_MF8_MASK 9594 +#define RISCV_PseudoVSUXSEG5EI32_V_M1_M1 9595 +#define RISCV_PseudoVSUXSEG5EI32_V_M1_M1_MASK 9596 +#define RISCV_PseudoVSUXSEG5EI32_V_M1_MF2 9597 +#define RISCV_PseudoVSUXSEG5EI32_V_M1_MF2_MASK 9598 +#define RISCV_PseudoVSUXSEG5EI32_V_M1_MF4 9599 +#define RISCV_PseudoVSUXSEG5EI32_V_M1_MF4_MASK 9600 +#define RISCV_PseudoVSUXSEG5EI32_V_M2_M1 9601 +#define RISCV_PseudoVSUXSEG5EI32_V_M2_M1_MASK 9602 +#define RISCV_PseudoVSUXSEG5EI32_V_M2_MF2 9603 +#define RISCV_PseudoVSUXSEG5EI32_V_M2_MF2_MASK 9604 +#define RISCV_PseudoVSUXSEG5EI32_V_M4_M1 9605 +#define RISCV_PseudoVSUXSEG5EI32_V_M4_M1_MASK 9606 +#define RISCV_PseudoVSUXSEG5EI32_V_MF2_M1 9607 +#define RISCV_PseudoVSUXSEG5EI32_V_MF2_M1_MASK 9608 +#define RISCV_PseudoVSUXSEG5EI32_V_MF2_MF2 9609 +#define RISCV_PseudoVSUXSEG5EI32_V_MF2_MF2_MASK 9610 +#define RISCV_PseudoVSUXSEG5EI32_V_MF2_MF4 9611 +#define RISCV_PseudoVSUXSEG5EI32_V_MF2_MF4_MASK 9612 +#define RISCV_PseudoVSUXSEG5EI32_V_MF2_MF8 9613 +#define RISCV_PseudoVSUXSEG5EI32_V_MF2_MF8_MASK 9614 +#define RISCV_PseudoVSUXSEG5EI64_V_M1_M1 9615 +#define RISCV_PseudoVSUXSEG5EI64_V_M1_M1_MASK 9616 +#define RISCV_PseudoVSUXSEG5EI64_V_M1_MF2 9617 +#define RISCV_PseudoVSUXSEG5EI64_V_M1_MF2_MASK 9618 +#define RISCV_PseudoVSUXSEG5EI64_V_M1_MF4 9619 +#define RISCV_PseudoVSUXSEG5EI64_V_M1_MF4_MASK 9620 +#define RISCV_PseudoVSUXSEG5EI64_V_M1_MF8 9621 +#define RISCV_PseudoVSUXSEG5EI64_V_M1_MF8_MASK 9622 +#define RISCV_PseudoVSUXSEG5EI64_V_M2_M1 9623 +#define RISCV_PseudoVSUXSEG5EI64_V_M2_M1_MASK 9624 +#define RISCV_PseudoVSUXSEG5EI64_V_M2_MF2 9625 +#define RISCV_PseudoVSUXSEG5EI64_V_M2_MF2_MASK 9626 +#define RISCV_PseudoVSUXSEG5EI64_V_M2_MF4 9627 +#define RISCV_PseudoVSUXSEG5EI64_V_M2_MF4_MASK 9628 +#define RISCV_PseudoVSUXSEG5EI64_V_M4_M1 9629 +#define RISCV_PseudoVSUXSEG5EI64_V_M4_M1_MASK 9630 +#define RISCV_PseudoVSUXSEG5EI64_V_M4_MF2 9631 +#define RISCV_PseudoVSUXSEG5EI64_V_M4_MF2_MASK 9632 +#define RISCV_PseudoVSUXSEG5EI64_V_M8_M1 9633 +#define RISCV_PseudoVSUXSEG5EI64_V_M8_M1_MASK 9634 +#define RISCV_PseudoVSUXSEG5EI8_V_M1_M1 9635 +#define RISCV_PseudoVSUXSEG5EI8_V_M1_M1_MASK 9636 +#define RISCV_PseudoVSUXSEG5EI8_V_MF2_M1 9637 +#define RISCV_PseudoVSUXSEG5EI8_V_MF2_M1_MASK 9638 +#define RISCV_PseudoVSUXSEG5EI8_V_MF2_MF2 9639 +#define RISCV_PseudoVSUXSEG5EI8_V_MF2_MF2_MASK 9640 +#define RISCV_PseudoVSUXSEG5EI8_V_MF4_M1 9641 +#define RISCV_PseudoVSUXSEG5EI8_V_MF4_M1_MASK 9642 +#define RISCV_PseudoVSUXSEG5EI8_V_MF4_MF2 9643 +#define RISCV_PseudoVSUXSEG5EI8_V_MF4_MF2_MASK 9644 +#define RISCV_PseudoVSUXSEG5EI8_V_MF4_MF4 9645 +#define RISCV_PseudoVSUXSEG5EI8_V_MF4_MF4_MASK 9646 +#define RISCV_PseudoVSUXSEG5EI8_V_MF8_M1 9647 +#define RISCV_PseudoVSUXSEG5EI8_V_MF8_M1_MASK 9648 +#define RISCV_PseudoVSUXSEG5EI8_V_MF8_MF2 9649 +#define RISCV_PseudoVSUXSEG5EI8_V_MF8_MF2_MASK 9650 +#define RISCV_PseudoVSUXSEG5EI8_V_MF8_MF4 9651 +#define RISCV_PseudoVSUXSEG5EI8_V_MF8_MF4_MASK 9652 +#define RISCV_PseudoVSUXSEG5EI8_V_MF8_MF8 9653 +#define RISCV_PseudoVSUXSEG5EI8_V_MF8_MF8_MASK 9654 +#define RISCV_PseudoVSUXSEG6EI16_V_M1_M1 9655 +#define RISCV_PseudoVSUXSEG6EI16_V_M1_M1_MASK 9656 +#define RISCV_PseudoVSUXSEG6EI16_V_M1_MF2 9657 +#define RISCV_PseudoVSUXSEG6EI16_V_M1_MF2_MASK 9658 +#define RISCV_PseudoVSUXSEG6EI16_V_M2_M1 9659 +#define RISCV_PseudoVSUXSEG6EI16_V_M2_M1_MASK 9660 +#define RISCV_PseudoVSUXSEG6EI16_V_MF2_M1 9661 +#define RISCV_PseudoVSUXSEG6EI16_V_MF2_M1_MASK 9662 +#define RISCV_PseudoVSUXSEG6EI16_V_MF2_MF2 9663 +#define RISCV_PseudoVSUXSEG6EI16_V_MF2_MF2_MASK 9664 +#define RISCV_PseudoVSUXSEG6EI16_V_MF2_MF4 9665 +#define RISCV_PseudoVSUXSEG6EI16_V_MF2_MF4_MASK 9666 +#define RISCV_PseudoVSUXSEG6EI16_V_MF4_M1 9667 +#define RISCV_PseudoVSUXSEG6EI16_V_MF4_M1_MASK 9668 +#define RISCV_PseudoVSUXSEG6EI16_V_MF4_MF2 9669 +#define RISCV_PseudoVSUXSEG6EI16_V_MF4_MF2_MASK 9670 +#define RISCV_PseudoVSUXSEG6EI16_V_MF4_MF4 9671 +#define RISCV_PseudoVSUXSEG6EI16_V_MF4_MF4_MASK 9672 +#define RISCV_PseudoVSUXSEG6EI16_V_MF4_MF8 9673 +#define RISCV_PseudoVSUXSEG6EI16_V_MF4_MF8_MASK 9674 +#define RISCV_PseudoVSUXSEG6EI32_V_M1_M1 9675 +#define RISCV_PseudoVSUXSEG6EI32_V_M1_M1_MASK 9676 +#define RISCV_PseudoVSUXSEG6EI32_V_M1_MF2 9677 +#define RISCV_PseudoVSUXSEG6EI32_V_M1_MF2_MASK 9678 +#define RISCV_PseudoVSUXSEG6EI32_V_M1_MF4 9679 +#define RISCV_PseudoVSUXSEG6EI32_V_M1_MF4_MASK 9680 +#define RISCV_PseudoVSUXSEG6EI32_V_M2_M1 9681 +#define RISCV_PseudoVSUXSEG6EI32_V_M2_M1_MASK 9682 +#define RISCV_PseudoVSUXSEG6EI32_V_M2_MF2 9683 +#define RISCV_PseudoVSUXSEG6EI32_V_M2_MF2_MASK 9684 +#define RISCV_PseudoVSUXSEG6EI32_V_M4_M1 9685 +#define RISCV_PseudoVSUXSEG6EI32_V_M4_M1_MASK 9686 +#define RISCV_PseudoVSUXSEG6EI32_V_MF2_M1 9687 +#define RISCV_PseudoVSUXSEG6EI32_V_MF2_M1_MASK 9688 +#define RISCV_PseudoVSUXSEG6EI32_V_MF2_MF2 9689 +#define RISCV_PseudoVSUXSEG6EI32_V_MF2_MF2_MASK 9690 +#define RISCV_PseudoVSUXSEG6EI32_V_MF2_MF4 9691 +#define RISCV_PseudoVSUXSEG6EI32_V_MF2_MF4_MASK 9692 +#define RISCV_PseudoVSUXSEG6EI32_V_MF2_MF8 9693 +#define RISCV_PseudoVSUXSEG6EI32_V_MF2_MF8_MASK 9694 +#define RISCV_PseudoVSUXSEG6EI64_V_M1_M1 9695 +#define RISCV_PseudoVSUXSEG6EI64_V_M1_M1_MASK 9696 +#define RISCV_PseudoVSUXSEG6EI64_V_M1_MF2 9697 +#define RISCV_PseudoVSUXSEG6EI64_V_M1_MF2_MASK 9698 +#define RISCV_PseudoVSUXSEG6EI64_V_M1_MF4 9699 +#define RISCV_PseudoVSUXSEG6EI64_V_M1_MF4_MASK 9700 +#define RISCV_PseudoVSUXSEG6EI64_V_M1_MF8 9701 +#define RISCV_PseudoVSUXSEG6EI64_V_M1_MF8_MASK 9702 +#define RISCV_PseudoVSUXSEG6EI64_V_M2_M1 9703 +#define RISCV_PseudoVSUXSEG6EI64_V_M2_M1_MASK 9704 +#define RISCV_PseudoVSUXSEG6EI64_V_M2_MF2 9705 +#define RISCV_PseudoVSUXSEG6EI64_V_M2_MF2_MASK 9706 +#define RISCV_PseudoVSUXSEG6EI64_V_M2_MF4 9707 +#define RISCV_PseudoVSUXSEG6EI64_V_M2_MF4_MASK 9708 +#define RISCV_PseudoVSUXSEG6EI64_V_M4_M1 9709 +#define RISCV_PseudoVSUXSEG6EI64_V_M4_M1_MASK 9710 +#define RISCV_PseudoVSUXSEG6EI64_V_M4_MF2 9711 +#define RISCV_PseudoVSUXSEG6EI64_V_M4_MF2_MASK 9712 +#define RISCV_PseudoVSUXSEG6EI64_V_M8_M1 9713 +#define RISCV_PseudoVSUXSEG6EI64_V_M8_M1_MASK 9714 +#define RISCV_PseudoVSUXSEG6EI8_V_M1_M1 9715 +#define RISCV_PseudoVSUXSEG6EI8_V_M1_M1_MASK 9716 +#define RISCV_PseudoVSUXSEG6EI8_V_MF2_M1 9717 +#define RISCV_PseudoVSUXSEG6EI8_V_MF2_M1_MASK 9718 +#define RISCV_PseudoVSUXSEG6EI8_V_MF2_MF2 9719 +#define RISCV_PseudoVSUXSEG6EI8_V_MF2_MF2_MASK 9720 +#define RISCV_PseudoVSUXSEG6EI8_V_MF4_M1 9721 +#define RISCV_PseudoVSUXSEG6EI8_V_MF4_M1_MASK 9722 +#define RISCV_PseudoVSUXSEG6EI8_V_MF4_MF2 9723 +#define RISCV_PseudoVSUXSEG6EI8_V_MF4_MF2_MASK 9724 +#define RISCV_PseudoVSUXSEG6EI8_V_MF4_MF4 9725 +#define RISCV_PseudoVSUXSEG6EI8_V_MF4_MF4_MASK 9726 +#define RISCV_PseudoVSUXSEG6EI8_V_MF8_M1 9727 +#define RISCV_PseudoVSUXSEG6EI8_V_MF8_M1_MASK 9728 +#define RISCV_PseudoVSUXSEG6EI8_V_MF8_MF2 9729 +#define RISCV_PseudoVSUXSEG6EI8_V_MF8_MF2_MASK 9730 +#define RISCV_PseudoVSUXSEG6EI8_V_MF8_MF4 9731 +#define RISCV_PseudoVSUXSEG6EI8_V_MF8_MF4_MASK 9732 +#define RISCV_PseudoVSUXSEG6EI8_V_MF8_MF8 9733 +#define RISCV_PseudoVSUXSEG6EI8_V_MF8_MF8_MASK 9734 +#define RISCV_PseudoVSUXSEG7EI16_V_M1_M1 9735 +#define RISCV_PseudoVSUXSEG7EI16_V_M1_M1_MASK 9736 +#define RISCV_PseudoVSUXSEG7EI16_V_M1_MF2 9737 +#define RISCV_PseudoVSUXSEG7EI16_V_M1_MF2_MASK 9738 +#define RISCV_PseudoVSUXSEG7EI16_V_M2_M1 9739 +#define RISCV_PseudoVSUXSEG7EI16_V_M2_M1_MASK 9740 +#define RISCV_PseudoVSUXSEG7EI16_V_MF2_M1 9741 +#define RISCV_PseudoVSUXSEG7EI16_V_MF2_M1_MASK 9742 +#define RISCV_PseudoVSUXSEG7EI16_V_MF2_MF2 9743 +#define RISCV_PseudoVSUXSEG7EI16_V_MF2_MF2_MASK 9744 +#define RISCV_PseudoVSUXSEG7EI16_V_MF2_MF4 9745 +#define RISCV_PseudoVSUXSEG7EI16_V_MF2_MF4_MASK 9746 +#define RISCV_PseudoVSUXSEG7EI16_V_MF4_M1 9747 +#define RISCV_PseudoVSUXSEG7EI16_V_MF4_M1_MASK 9748 +#define RISCV_PseudoVSUXSEG7EI16_V_MF4_MF2 9749 +#define RISCV_PseudoVSUXSEG7EI16_V_MF4_MF2_MASK 9750 +#define RISCV_PseudoVSUXSEG7EI16_V_MF4_MF4 9751 +#define RISCV_PseudoVSUXSEG7EI16_V_MF4_MF4_MASK 9752 +#define RISCV_PseudoVSUXSEG7EI16_V_MF4_MF8 9753 +#define RISCV_PseudoVSUXSEG7EI16_V_MF4_MF8_MASK 9754 +#define RISCV_PseudoVSUXSEG7EI32_V_M1_M1 9755 +#define RISCV_PseudoVSUXSEG7EI32_V_M1_M1_MASK 9756 +#define RISCV_PseudoVSUXSEG7EI32_V_M1_MF2 9757 +#define RISCV_PseudoVSUXSEG7EI32_V_M1_MF2_MASK 9758 +#define RISCV_PseudoVSUXSEG7EI32_V_M1_MF4 9759 +#define RISCV_PseudoVSUXSEG7EI32_V_M1_MF4_MASK 9760 +#define RISCV_PseudoVSUXSEG7EI32_V_M2_M1 9761 +#define RISCV_PseudoVSUXSEG7EI32_V_M2_M1_MASK 9762 +#define RISCV_PseudoVSUXSEG7EI32_V_M2_MF2 9763 +#define RISCV_PseudoVSUXSEG7EI32_V_M2_MF2_MASK 9764 +#define RISCV_PseudoVSUXSEG7EI32_V_M4_M1 9765 +#define RISCV_PseudoVSUXSEG7EI32_V_M4_M1_MASK 9766 +#define RISCV_PseudoVSUXSEG7EI32_V_MF2_M1 9767 +#define RISCV_PseudoVSUXSEG7EI32_V_MF2_M1_MASK 9768 +#define RISCV_PseudoVSUXSEG7EI32_V_MF2_MF2 9769 +#define RISCV_PseudoVSUXSEG7EI32_V_MF2_MF2_MASK 9770 +#define RISCV_PseudoVSUXSEG7EI32_V_MF2_MF4 9771 +#define RISCV_PseudoVSUXSEG7EI32_V_MF2_MF4_MASK 9772 +#define RISCV_PseudoVSUXSEG7EI32_V_MF2_MF8 9773 +#define RISCV_PseudoVSUXSEG7EI32_V_MF2_MF8_MASK 9774 +#define RISCV_PseudoVSUXSEG7EI64_V_M1_M1 9775 +#define RISCV_PseudoVSUXSEG7EI64_V_M1_M1_MASK 9776 +#define RISCV_PseudoVSUXSEG7EI64_V_M1_MF2 9777 +#define RISCV_PseudoVSUXSEG7EI64_V_M1_MF2_MASK 9778 +#define RISCV_PseudoVSUXSEG7EI64_V_M1_MF4 9779 +#define RISCV_PseudoVSUXSEG7EI64_V_M1_MF4_MASK 9780 +#define RISCV_PseudoVSUXSEG7EI64_V_M1_MF8 9781 +#define RISCV_PseudoVSUXSEG7EI64_V_M1_MF8_MASK 9782 +#define RISCV_PseudoVSUXSEG7EI64_V_M2_M1 9783 +#define RISCV_PseudoVSUXSEG7EI64_V_M2_M1_MASK 9784 +#define RISCV_PseudoVSUXSEG7EI64_V_M2_MF2 9785 +#define RISCV_PseudoVSUXSEG7EI64_V_M2_MF2_MASK 9786 +#define RISCV_PseudoVSUXSEG7EI64_V_M2_MF4 9787 +#define RISCV_PseudoVSUXSEG7EI64_V_M2_MF4_MASK 9788 +#define RISCV_PseudoVSUXSEG7EI64_V_M4_M1 9789 +#define RISCV_PseudoVSUXSEG7EI64_V_M4_M1_MASK 9790 +#define RISCV_PseudoVSUXSEG7EI64_V_M4_MF2 9791 +#define RISCV_PseudoVSUXSEG7EI64_V_M4_MF2_MASK 9792 +#define RISCV_PseudoVSUXSEG7EI64_V_M8_M1 9793 +#define RISCV_PseudoVSUXSEG7EI64_V_M8_M1_MASK 9794 +#define RISCV_PseudoVSUXSEG7EI8_V_M1_M1 9795 +#define RISCV_PseudoVSUXSEG7EI8_V_M1_M1_MASK 9796 +#define RISCV_PseudoVSUXSEG7EI8_V_MF2_M1 9797 +#define RISCV_PseudoVSUXSEG7EI8_V_MF2_M1_MASK 9798 +#define RISCV_PseudoVSUXSEG7EI8_V_MF2_MF2 9799 +#define RISCV_PseudoVSUXSEG7EI8_V_MF2_MF2_MASK 9800 +#define RISCV_PseudoVSUXSEG7EI8_V_MF4_M1 9801 +#define RISCV_PseudoVSUXSEG7EI8_V_MF4_M1_MASK 9802 +#define RISCV_PseudoVSUXSEG7EI8_V_MF4_MF2 9803 +#define RISCV_PseudoVSUXSEG7EI8_V_MF4_MF2_MASK 9804 +#define RISCV_PseudoVSUXSEG7EI8_V_MF4_MF4 9805 +#define RISCV_PseudoVSUXSEG7EI8_V_MF4_MF4_MASK 9806 +#define RISCV_PseudoVSUXSEG7EI8_V_MF8_M1 9807 +#define RISCV_PseudoVSUXSEG7EI8_V_MF8_M1_MASK 9808 +#define RISCV_PseudoVSUXSEG7EI8_V_MF8_MF2 9809 +#define RISCV_PseudoVSUXSEG7EI8_V_MF8_MF2_MASK 9810 +#define RISCV_PseudoVSUXSEG7EI8_V_MF8_MF4 9811 +#define RISCV_PseudoVSUXSEG7EI8_V_MF8_MF4_MASK 9812 +#define RISCV_PseudoVSUXSEG7EI8_V_MF8_MF8 9813 +#define RISCV_PseudoVSUXSEG7EI8_V_MF8_MF8_MASK 9814 +#define RISCV_PseudoVSUXSEG8EI16_V_M1_M1 9815 +#define RISCV_PseudoVSUXSEG8EI16_V_M1_M1_MASK 9816 +#define RISCV_PseudoVSUXSEG8EI16_V_M1_MF2 9817 +#define RISCV_PseudoVSUXSEG8EI16_V_M1_MF2_MASK 9818 +#define RISCV_PseudoVSUXSEG8EI16_V_M2_M1 9819 +#define RISCV_PseudoVSUXSEG8EI16_V_M2_M1_MASK 9820 +#define RISCV_PseudoVSUXSEG8EI16_V_MF2_M1 9821 +#define RISCV_PseudoVSUXSEG8EI16_V_MF2_M1_MASK 9822 +#define RISCV_PseudoVSUXSEG8EI16_V_MF2_MF2 9823 +#define RISCV_PseudoVSUXSEG8EI16_V_MF2_MF2_MASK 9824 +#define RISCV_PseudoVSUXSEG8EI16_V_MF2_MF4 9825 +#define RISCV_PseudoVSUXSEG8EI16_V_MF2_MF4_MASK 9826 +#define RISCV_PseudoVSUXSEG8EI16_V_MF4_M1 9827 +#define RISCV_PseudoVSUXSEG8EI16_V_MF4_M1_MASK 9828 +#define RISCV_PseudoVSUXSEG8EI16_V_MF4_MF2 9829 +#define RISCV_PseudoVSUXSEG8EI16_V_MF4_MF2_MASK 9830 +#define RISCV_PseudoVSUXSEG8EI16_V_MF4_MF4 9831 +#define RISCV_PseudoVSUXSEG8EI16_V_MF4_MF4_MASK 9832 +#define RISCV_PseudoVSUXSEG8EI16_V_MF4_MF8 9833 +#define RISCV_PseudoVSUXSEG8EI16_V_MF4_MF8_MASK 9834 +#define RISCV_PseudoVSUXSEG8EI32_V_M1_M1 9835 +#define RISCV_PseudoVSUXSEG8EI32_V_M1_M1_MASK 9836 +#define RISCV_PseudoVSUXSEG8EI32_V_M1_MF2 9837 +#define RISCV_PseudoVSUXSEG8EI32_V_M1_MF2_MASK 9838 +#define RISCV_PseudoVSUXSEG8EI32_V_M1_MF4 9839 +#define RISCV_PseudoVSUXSEG8EI32_V_M1_MF4_MASK 9840 +#define RISCV_PseudoVSUXSEG8EI32_V_M2_M1 9841 +#define RISCV_PseudoVSUXSEG8EI32_V_M2_M1_MASK 9842 +#define RISCV_PseudoVSUXSEG8EI32_V_M2_MF2 9843 +#define RISCV_PseudoVSUXSEG8EI32_V_M2_MF2_MASK 9844 +#define RISCV_PseudoVSUXSEG8EI32_V_M4_M1 9845 +#define RISCV_PseudoVSUXSEG8EI32_V_M4_M1_MASK 9846 +#define RISCV_PseudoVSUXSEG8EI32_V_MF2_M1 9847 +#define RISCV_PseudoVSUXSEG8EI32_V_MF2_M1_MASK 9848 +#define RISCV_PseudoVSUXSEG8EI32_V_MF2_MF2 9849 +#define RISCV_PseudoVSUXSEG8EI32_V_MF2_MF2_MASK 9850 +#define RISCV_PseudoVSUXSEG8EI32_V_MF2_MF4 9851 +#define RISCV_PseudoVSUXSEG8EI32_V_MF2_MF4_MASK 9852 +#define RISCV_PseudoVSUXSEG8EI32_V_MF2_MF8 9853 +#define RISCV_PseudoVSUXSEG8EI32_V_MF2_MF8_MASK 9854 +#define RISCV_PseudoVSUXSEG8EI64_V_M1_M1 9855 +#define RISCV_PseudoVSUXSEG8EI64_V_M1_M1_MASK 9856 +#define RISCV_PseudoVSUXSEG8EI64_V_M1_MF2 9857 +#define RISCV_PseudoVSUXSEG8EI64_V_M1_MF2_MASK 9858 +#define RISCV_PseudoVSUXSEG8EI64_V_M1_MF4 9859 +#define RISCV_PseudoVSUXSEG8EI64_V_M1_MF4_MASK 9860 +#define RISCV_PseudoVSUXSEG8EI64_V_M1_MF8 9861 +#define RISCV_PseudoVSUXSEG8EI64_V_M1_MF8_MASK 9862 +#define RISCV_PseudoVSUXSEG8EI64_V_M2_M1 9863 +#define RISCV_PseudoVSUXSEG8EI64_V_M2_M1_MASK 9864 +#define RISCV_PseudoVSUXSEG8EI64_V_M2_MF2 9865 +#define RISCV_PseudoVSUXSEG8EI64_V_M2_MF2_MASK 9866 +#define RISCV_PseudoVSUXSEG8EI64_V_M2_MF4 9867 +#define RISCV_PseudoVSUXSEG8EI64_V_M2_MF4_MASK 9868 +#define RISCV_PseudoVSUXSEG8EI64_V_M4_M1 9869 +#define RISCV_PseudoVSUXSEG8EI64_V_M4_M1_MASK 9870 +#define RISCV_PseudoVSUXSEG8EI64_V_M4_MF2 9871 +#define RISCV_PseudoVSUXSEG8EI64_V_M4_MF2_MASK 9872 +#define RISCV_PseudoVSUXSEG8EI64_V_M8_M1 9873 +#define RISCV_PseudoVSUXSEG8EI64_V_M8_M1_MASK 9874 +#define RISCV_PseudoVSUXSEG8EI8_V_M1_M1 9875 +#define RISCV_PseudoVSUXSEG8EI8_V_M1_M1_MASK 9876 +#define RISCV_PseudoVSUXSEG8EI8_V_MF2_M1 9877 +#define RISCV_PseudoVSUXSEG8EI8_V_MF2_M1_MASK 9878 +#define RISCV_PseudoVSUXSEG8EI8_V_MF2_MF2 9879 +#define RISCV_PseudoVSUXSEG8EI8_V_MF2_MF2_MASK 9880 +#define RISCV_PseudoVSUXSEG8EI8_V_MF4_M1 9881 +#define RISCV_PseudoVSUXSEG8EI8_V_MF4_M1_MASK 9882 +#define RISCV_PseudoVSUXSEG8EI8_V_MF4_MF2 9883 +#define RISCV_PseudoVSUXSEG8EI8_V_MF4_MF2_MASK 9884 +#define RISCV_PseudoVSUXSEG8EI8_V_MF4_MF4 9885 +#define RISCV_PseudoVSUXSEG8EI8_V_MF4_MF4_MASK 9886 +#define RISCV_PseudoVSUXSEG8EI8_V_MF8_M1 9887 +#define RISCV_PseudoVSUXSEG8EI8_V_MF8_M1_MASK 9888 +#define RISCV_PseudoVSUXSEG8EI8_V_MF8_MF2 9889 +#define RISCV_PseudoVSUXSEG8EI8_V_MF8_MF2_MASK 9890 +#define RISCV_PseudoVSUXSEG8EI8_V_MF8_MF4 9891 +#define RISCV_PseudoVSUXSEG8EI8_V_MF8_MF4_MASK 9892 +#define RISCV_PseudoVSUXSEG8EI8_V_MF8_MF8 9893 +#define RISCV_PseudoVSUXSEG8EI8_V_MF8_MF8_MASK 9894 +#define RISCV_PseudoVWADDU_VV_M1 9895 +#define RISCV_PseudoVWADDU_VV_M1_MASK 9896 +#define RISCV_PseudoVWADDU_VV_M2 9897 +#define RISCV_PseudoVWADDU_VV_M2_MASK 9898 +#define RISCV_PseudoVWADDU_VV_M4 9899 +#define RISCV_PseudoVWADDU_VV_M4_MASK 9900 +#define RISCV_PseudoVWADDU_VV_MF2 9901 +#define RISCV_PseudoVWADDU_VV_MF2_MASK 9902 +#define RISCV_PseudoVWADDU_VV_MF4 9903 +#define RISCV_PseudoVWADDU_VV_MF4_MASK 9904 +#define RISCV_PseudoVWADDU_VV_MF8 9905 +#define RISCV_PseudoVWADDU_VV_MF8_MASK 9906 +#define RISCV_PseudoVWADDU_VX_M1 9907 +#define RISCV_PseudoVWADDU_VX_M1_MASK 9908 +#define RISCV_PseudoVWADDU_VX_M2 9909 +#define RISCV_PseudoVWADDU_VX_M2_MASK 9910 +#define RISCV_PseudoVWADDU_VX_M4 9911 +#define RISCV_PseudoVWADDU_VX_M4_MASK 9912 +#define RISCV_PseudoVWADDU_VX_MF2 9913 +#define RISCV_PseudoVWADDU_VX_MF2_MASK 9914 +#define RISCV_PseudoVWADDU_VX_MF4 9915 +#define RISCV_PseudoVWADDU_VX_MF4_MASK 9916 +#define RISCV_PseudoVWADDU_VX_MF8 9917 +#define RISCV_PseudoVWADDU_VX_MF8_MASK 9918 +#define RISCV_PseudoVWADDU_WV_M1 9919 +#define RISCV_PseudoVWADDU_WV_M1_MASK 9920 +#define RISCV_PseudoVWADDU_WV_M1_MASK_TIED 9921 +#define RISCV_PseudoVWADDU_WV_M1_TIED 9922 +#define RISCV_PseudoVWADDU_WV_M2 9923 +#define RISCV_PseudoVWADDU_WV_M2_MASK 9924 +#define RISCV_PseudoVWADDU_WV_M2_MASK_TIED 9925 +#define RISCV_PseudoVWADDU_WV_M2_TIED 9926 +#define RISCV_PseudoVWADDU_WV_M4 9927 +#define RISCV_PseudoVWADDU_WV_M4_MASK 9928 +#define RISCV_PseudoVWADDU_WV_M4_MASK_TIED 9929 +#define RISCV_PseudoVWADDU_WV_M4_TIED 9930 +#define RISCV_PseudoVWADDU_WV_MF2 9931 +#define RISCV_PseudoVWADDU_WV_MF2_MASK 9932 +#define RISCV_PseudoVWADDU_WV_MF2_MASK_TIED 9933 +#define RISCV_PseudoVWADDU_WV_MF2_TIED 9934 +#define RISCV_PseudoVWADDU_WV_MF4 9935 +#define RISCV_PseudoVWADDU_WV_MF4_MASK 9936 +#define RISCV_PseudoVWADDU_WV_MF4_MASK_TIED 9937 +#define RISCV_PseudoVWADDU_WV_MF4_TIED 9938 +#define RISCV_PseudoVWADDU_WV_MF8 9939 +#define RISCV_PseudoVWADDU_WV_MF8_MASK 9940 +#define RISCV_PseudoVWADDU_WV_MF8_MASK_TIED 9941 +#define RISCV_PseudoVWADDU_WV_MF8_TIED 9942 +#define RISCV_PseudoVWADDU_WX_M1 9943 +#define RISCV_PseudoVWADDU_WX_M1_MASK 9944 +#define RISCV_PseudoVWADDU_WX_M2 9945 +#define RISCV_PseudoVWADDU_WX_M2_MASK 9946 +#define RISCV_PseudoVWADDU_WX_M4 9947 +#define RISCV_PseudoVWADDU_WX_M4_MASK 9948 +#define RISCV_PseudoVWADDU_WX_MF2 9949 +#define RISCV_PseudoVWADDU_WX_MF2_MASK 9950 +#define RISCV_PseudoVWADDU_WX_MF4 9951 +#define RISCV_PseudoVWADDU_WX_MF4_MASK 9952 +#define RISCV_PseudoVWADDU_WX_MF8 9953 +#define RISCV_PseudoVWADDU_WX_MF8_MASK 9954 +#define RISCV_PseudoVWADD_VV_M1 9955 +#define RISCV_PseudoVWADD_VV_M1_MASK 9956 +#define RISCV_PseudoVWADD_VV_M2 9957 +#define RISCV_PseudoVWADD_VV_M2_MASK 9958 +#define RISCV_PseudoVWADD_VV_M4 9959 +#define RISCV_PseudoVWADD_VV_M4_MASK 9960 +#define RISCV_PseudoVWADD_VV_MF2 9961 +#define RISCV_PseudoVWADD_VV_MF2_MASK 9962 +#define RISCV_PseudoVWADD_VV_MF4 9963 +#define RISCV_PseudoVWADD_VV_MF4_MASK 9964 +#define RISCV_PseudoVWADD_VV_MF8 9965 +#define RISCV_PseudoVWADD_VV_MF8_MASK 9966 +#define RISCV_PseudoVWADD_VX_M1 9967 +#define RISCV_PseudoVWADD_VX_M1_MASK 9968 +#define RISCV_PseudoVWADD_VX_M2 9969 +#define RISCV_PseudoVWADD_VX_M2_MASK 9970 +#define RISCV_PseudoVWADD_VX_M4 9971 +#define RISCV_PseudoVWADD_VX_M4_MASK 9972 +#define RISCV_PseudoVWADD_VX_MF2 9973 +#define RISCV_PseudoVWADD_VX_MF2_MASK 9974 +#define RISCV_PseudoVWADD_VX_MF4 9975 +#define RISCV_PseudoVWADD_VX_MF4_MASK 9976 +#define RISCV_PseudoVWADD_VX_MF8 9977 +#define RISCV_PseudoVWADD_VX_MF8_MASK 9978 +#define RISCV_PseudoVWADD_WV_M1 9979 +#define RISCV_PseudoVWADD_WV_M1_MASK 9980 +#define RISCV_PseudoVWADD_WV_M1_MASK_TIED 9981 +#define RISCV_PseudoVWADD_WV_M1_TIED 9982 +#define RISCV_PseudoVWADD_WV_M2 9983 +#define RISCV_PseudoVWADD_WV_M2_MASK 9984 +#define RISCV_PseudoVWADD_WV_M2_MASK_TIED 9985 +#define RISCV_PseudoVWADD_WV_M2_TIED 9986 +#define RISCV_PseudoVWADD_WV_M4 9987 +#define RISCV_PseudoVWADD_WV_M4_MASK 9988 +#define RISCV_PseudoVWADD_WV_M4_MASK_TIED 9989 +#define RISCV_PseudoVWADD_WV_M4_TIED 9990 +#define RISCV_PseudoVWADD_WV_MF2 9991 +#define RISCV_PseudoVWADD_WV_MF2_MASK 9992 +#define RISCV_PseudoVWADD_WV_MF2_MASK_TIED 9993 +#define RISCV_PseudoVWADD_WV_MF2_TIED 9994 +#define RISCV_PseudoVWADD_WV_MF4 9995 +#define RISCV_PseudoVWADD_WV_MF4_MASK 9996 +#define RISCV_PseudoVWADD_WV_MF4_MASK_TIED 9997 +#define RISCV_PseudoVWADD_WV_MF4_TIED 9998 +#define RISCV_PseudoVWADD_WV_MF8 9999 +#define RISCV_PseudoVWADD_WV_MF8_MASK 10000 +#define RISCV_PseudoVWADD_WV_MF8_MASK_TIED 10001 +#define RISCV_PseudoVWADD_WV_MF8_TIED 10002 +#define RISCV_PseudoVWADD_WX_M1 10003 +#define RISCV_PseudoVWADD_WX_M1_MASK 10004 +#define RISCV_PseudoVWADD_WX_M2 10005 +#define RISCV_PseudoVWADD_WX_M2_MASK 10006 +#define RISCV_PseudoVWADD_WX_M4 10007 +#define RISCV_PseudoVWADD_WX_M4_MASK 10008 +#define RISCV_PseudoVWADD_WX_MF2 10009 +#define RISCV_PseudoVWADD_WX_MF2_MASK 10010 +#define RISCV_PseudoVWADD_WX_MF4 10011 +#define RISCV_PseudoVWADD_WX_MF4_MASK 10012 +#define RISCV_PseudoVWADD_WX_MF8 10013 +#define RISCV_PseudoVWADD_WX_MF8_MASK 10014 +#define RISCV_PseudoVWMACCSU_VV_M1 10015 +#define RISCV_PseudoVWMACCSU_VV_M1_MASK 10016 +#define RISCV_PseudoVWMACCSU_VV_M2 10017 +#define RISCV_PseudoVWMACCSU_VV_M2_MASK 10018 +#define RISCV_PseudoVWMACCSU_VV_M4 10019 +#define RISCV_PseudoVWMACCSU_VV_M4_MASK 10020 +#define RISCV_PseudoVWMACCSU_VV_MF2 10021 +#define RISCV_PseudoVWMACCSU_VV_MF2_MASK 10022 +#define RISCV_PseudoVWMACCSU_VV_MF4 10023 +#define RISCV_PseudoVWMACCSU_VV_MF4_MASK 10024 +#define RISCV_PseudoVWMACCSU_VV_MF8 10025 +#define RISCV_PseudoVWMACCSU_VV_MF8_MASK 10026 +#define RISCV_PseudoVWMACCSU_VX_M1 10027 +#define RISCV_PseudoVWMACCSU_VX_M1_MASK 10028 +#define RISCV_PseudoVWMACCSU_VX_M2 10029 +#define RISCV_PseudoVWMACCSU_VX_M2_MASK 10030 +#define RISCV_PseudoVWMACCSU_VX_M4 10031 +#define RISCV_PseudoVWMACCSU_VX_M4_MASK 10032 +#define RISCV_PseudoVWMACCSU_VX_MF2 10033 +#define RISCV_PseudoVWMACCSU_VX_MF2_MASK 10034 +#define RISCV_PseudoVWMACCSU_VX_MF4 10035 +#define RISCV_PseudoVWMACCSU_VX_MF4_MASK 10036 +#define RISCV_PseudoVWMACCSU_VX_MF8 10037 +#define RISCV_PseudoVWMACCSU_VX_MF8_MASK 10038 +#define RISCV_PseudoVWMACCUS_VX_M1 10039 +#define RISCV_PseudoVWMACCUS_VX_M1_MASK 10040 +#define RISCV_PseudoVWMACCUS_VX_M2 10041 +#define RISCV_PseudoVWMACCUS_VX_M2_MASK 10042 +#define RISCV_PseudoVWMACCUS_VX_M4 10043 +#define RISCV_PseudoVWMACCUS_VX_M4_MASK 10044 +#define RISCV_PseudoVWMACCUS_VX_MF2 10045 +#define RISCV_PseudoVWMACCUS_VX_MF2_MASK 10046 +#define RISCV_PseudoVWMACCUS_VX_MF4 10047 +#define RISCV_PseudoVWMACCUS_VX_MF4_MASK 10048 +#define RISCV_PseudoVWMACCUS_VX_MF8 10049 +#define RISCV_PseudoVWMACCUS_VX_MF8_MASK 10050 +#define RISCV_PseudoVWMACCU_VV_M1 10051 +#define RISCV_PseudoVWMACCU_VV_M1_MASK 10052 +#define RISCV_PseudoVWMACCU_VV_M2 10053 +#define RISCV_PseudoVWMACCU_VV_M2_MASK 10054 +#define RISCV_PseudoVWMACCU_VV_M4 10055 +#define RISCV_PseudoVWMACCU_VV_M4_MASK 10056 +#define RISCV_PseudoVWMACCU_VV_MF2 10057 +#define RISCV_PseudoVWMACCU_VV_MF2_MASK 10058 +#define RISCV_PseudoVWMACCU_VV_MF4 10059 +#define RISCV_PseudoVWMACCU_VV_MF4_MASK 10060 +#define RISCV_PseudoVWMACCU_VV_MF8 10061 +#define RISCV_PseudoVWMACCU_VV_MF8_MASK 10062 +#define RISCV_PseudoVWMACCU_VX_M1 10063 +#define RISCV_PseudoVWMACCU_VX_M1_MASK 10064 +#define RISCV_PseudoVWMACCU_VX_M2 10065 +#define RISCV_PseudoVWMACCU_VX_M2_MASK 10066 +#define RISCV_PseudoVWMACCU_VX_M4 10067 +#define RISCV_PseudoVWMACCU_VX_M4_MASK 10068 +#define RISCV_PseudoVWMACCU_VX_MF2 10069 +#define RISCV_PseudoVWMACCU_VX_MF2_MASK 10070 +#define RISCV_PseudoVWMACCU_VX_MF4 10071 +#define RISCV_PseudoVWMACCU_VX_MF4_MASK 10072 +#define RISCV_PseudoVWMACCU_VX_MF8 10073 +#define RISCV_PseudoVWMACCU_VX_MF8_MASK 10074 +#define RISCV_PseudoVWMACC_VV_M1 10075 +#define RISCV_PseudoVWMACC_VV_M1_MASK 10076 +#define RISCV_PseudoVWMACC_VV_M2 10077 +#define RISCV_PseudoVWMACC_VV_M2_MASK 10078 +#define RISCV_PseudoVWMACC_VV_M4 10079 +#define RISCV_PseudoVWMACC_VV_M4_MASK 10080 +#define RISCV_PseudoVWMACC_VV_MF2 10081 +#define RISCV_PseudoVWMACC_VV_MF2_MASK 10082 +#define RISCV_PseudoVWMACC_VV_MF4 10083 +#define RISCV_PseudoVWMACC_VV_MF4_MASK 10084 +#define RISCV_PseudoVWMACC_VV_MF8 10085 +#define RISCV_PseudoVWMACC_VV_MF8_MASK 10086 +#define RISCV_PseudoVWMACC_VX_M1 10087 +#define RISCV_PseudoVWMACC_VX_M1_MASK 10088 +#define RISCV_PseudoVWMACC_VX_M2 10089 +#define RISCV_PseudoVWMACC_VX_M2_MASK 10090 +#define RISCV_PseudoVWMACC_VX_M4 10091 +#define RISCV_PseudoVWMACC_VX_M4_MASK 10092 +#define RISCV_PseudoVWMACC_VX_MF2 10093 +#define RISCV_PseudoVWMACC_VX_MF2_MASK 10094 +#define RISCV_PseudoVWMACC_VX_MF4 10095 +#define RISCV_PseudoVWMACC_VX_MF4_MASK 10096 +#define RISCV_PseudoVWMACC_VX_MF8 10097 +#define RISCV_PseudoVWMACC_VX_MF8_MASK 10098 +#define RISCV_PseudoVWMULSU_VV_M1 10099 +#define RISCV_PseudoVWMULSU_VV_M1_MASK 10100 +#define RISCV_PseudoVWMULSU_VV_M2 10101 +#define RISCV_PseudoVWMULSU_VV_M2_MASK 10102 +#define RISCV_PseudoVWMULSU_VV_M4 10103 +#define RISCV_PseudoVWMULSU_VV_M4_MASK 10104 +#define RISCV_PseudoVWMULSU_VV_MF2 10105 +#define RISCV_PseudoVWMULSU_VV_MF2_MASK 10106 +#define RISCV_PseudoVWMULSU_VV_MF4 10107 +#define RISCV_PseudoVWMULSU_VV_MF4_MASK 10108 +#define RISCV_PseudoVWMULSU_VV_MF8 10109 +#define RISCV_PseudoVWMULSU_VV_MF8_MASK 10110 +#define RISCV_PseudoVWMULSU_VX_M1 10111 +#define RISCV_PseudoVWMULSU_VX_M1_MASK 10112 +#define RISCV_PseudoVWMULSU_VX_M2 10113 +#define RISCV_PseudoVWMULSU_VX_M2_MASK 10114 +#define RISCV_PseudoVWMULSU_VX_M4 10115 +#define RISCV_PseudoVWMULSU_VX_M4_MASK 10116 +#define RISCV_PseudoVWMULSU_VX_MF2 10117 +#define RISCV_PseudoVWMULSU_VX_MF2_MASK 10118 +#define RISCV_PseudoVWMULSU_VX_MF4 10119 +#define RISCV_PseudoVWMULSU_VX_MF4_MASK 10120 +#define RISCV_PseudoVWMULSU_VX_MF8 10121 +#define RISCV_PseudoVWMULSU_VX_MF8_MASK 10122 +#define RISCV_PseudoVWMULU_VV_M1 10123 +#define RISCV_PseudoVWMULU_VV_M1_MASK 10124 +#define RISCV_PseudoVWMULU_VV_M2 10125 +#define RISCV_PseudoVWMULU_VV_M2_MASK 10126 +#define RISCV_PseudoVWMULU_VV_M4 10127 +#define RISCV_PseudoVWMULU_VV_M4_MASK 10128 +#define RISCV_PseudoVWMULU_VV_MF2 10129 +#define RISCV_PseudoVWMULU_VV_MF2_MASK 10130 +#define RISCV_PseudoVWMULU_VV_MF4 10131 +#define RISCV_PseudoVWMULU_VV_MF4_MASK 10132 +#define RISCV_PseudoVWMULU_VV_MF8 10133 +#define RISCV_PseudoVWMULU_VV_MF8_MASK 10134 +#define RISCV_PseudoVWMULU_VX_M1 10135 +#define RISCV_PseudoVWMULU_VX_M1_MASK 10136 +#define RISCV_PseudoVWMULU_VX_M2 10137 +#define RISCV_PseudoVWMULU_VX_M2_MASK 10138 +#define RISCV_PseudoVWMULU_VX_M4 10139 +#define RISCV_PseudoVWMULU_VX_M4_MASK 10140 +#define RISCV_PseudoVWMULU_VX_MF2 10141 +#define RISCV_PseudoVWMULU_VX_MF2_MASK 10142 +#define RISCV_PseudoVWMULU_VX_MF4 10143 +#define RISCV_PseudoVWMULU_VX_MF4_MASK 10144 +#define RISCV_PseudoVWMULU_VX_MF8 10145 +#define RISCV_PseudoVWMULU_VX_MF8_MASK 10146 +#define RISCV_PseudoVWMUL_VV_M1 10147 +#define RISCV_PseudoVWMUL_VV_M1_MASK 10148 +#define RISCV_PseudoVWMUL_VV_M2 10149 +#define RISCV_PseudoVWMUL_VV_M2_MASK 10150 +#define RISCV_PseudoVWMUL_VV_M4 10151 +#define RISCV_PseudoVWMUL_VV_M4_MASK 10152 +#define RISCV_PseudoVWMUL_VV_MF2 10153 +#define RISCV_PseudoVWMUL_VV_MF2_MASK 10154 +#define RISCV_PseudoVWMUL_VV_MF4 10155 +#define RISCV_PseudoVWMUL_VV_MF4_MASK 10156 +#define RISCV_PseudoVWMUL_VV_MF8 10157 +#define RISCV_PseudoVWMUL_VV_MF8_MASK 10158 +#define RISCV_PseudoVWMUL_VX_M1 10159 +#define RISCV_PseudoVWMUL_VX_M1_MASK 10160 +#define RISCV_PseudoVWMUL_VX_M2 10161 +#define RISCV_PseudoVWMUL_VX_M2_MASK 10162 +#define RISCV_PseudoVWMUL_VX_M4 10163 +#define RISCV_PseudoVWMUL_VX_M4_MASK 10164 +#define RISCV_PseudoVWMUL_VX_MF2 10165 +#define RISCV_PseudoVWMUL_VX_MF2_MASK 10166 +#define RISCV_PseudoVWMUL_VX_MF4 10167 +#define RISCV_PseudoVWMUL_VX_MF4_MASK 10168 +#define RISCV_PseudoVWMUL_VX_MF8 10169 +#define RISCV_PseudoVWMUL_VX_MF8_MASK 10170 +#define RISCV_PseudoVWREDSUMU_VS_M1 10171 +#define RISCV_PseudoVWREDSUMU_VS_M1_MASK 10172 +#define RISCV_PseudoVWREDSUMU_VS_M2 10173 +#define RISCV_PseudoVWREDSUMU_VS_M2_MASK 10174 +#define RISCV_PseudoVWREDSUMU_VS_M4 10175 +#define RISCV_PseudoVWREDSUMU_VS_M4_MASK 10176 +#define RISCV_PseudoVWREDSUMU_VS_M8 10177 +#define RISCV_PseudoVWREDSUMU_VS_M8_MASK 10178 +#define RISCV_PseudoVWREDSUMU_VS_MF2 10179 +#define RISCV_PseudoVWREDSUMU_VS_MF2_MASK 10180 +#define RISCV_PseudoVWREDSUMU_VS_MF4 10181 +#define RISCV_PseudoVWREDSUMU_VS_MF4_MASK 10182 +#define RISCV_PseudoVWREDSUMU_VS_MF8 10183 +#define RISCV_PseudoVWREDSUMU_VS_MF8_MASK 10184 +#define RISCV_PseudoVWREDSUM_VS_M1 10185 +#define RISCV_PseudoVWREDSUM_VS_M1_MASK 10186 +#define RISCV_PseudoVWREDSUM_VS_M2 10187 +#define RISCV_PseudoVWREDSUM_VS_M2_MASK 10188 +#define RISCV_PseudoVWREDSUM_VS_M4 10189 +#define RISCV_PseudoVWREDSUM_VS_M4_MASK 10190 +#define RISCV_PseudoVWREDSUM_VS_M8 10191 +#define RISCV_PseudoVWREDSUM_VS_M8_MASK 10192 +#define RISCV_PseudoVWREDSUM_VS_MF2 10193 +#define RISCV_PseudoVWREDSUM_VS_MF2_MASK 10194 +#define RISCV_PseudoVWREDSUM_VS_MF4 10195 +#define RISCV_PseudoVWREDSUM_VS_MF4_MASK 10196 +#define RISCV_PseudoVWREDSUM_VS_MF8 10197 +#define RISCV_PseudoVWREDSUM_VS_MF8_MASK 10198 +#define RISCV_PseudoVWSUBU_VV_M1 10199 +#define RISCV_PseudoVWSUBU_VV_M1_MASK 10200 +#define RISCV_PseudoVWSUBU_VV_M2 10201 +#define RISCV_PseudoVWSUBU_VV_M2_MASK 10202 +#define RISCV_PseudoVWSUBU_VV_M4 10203 +#define RISCV_PseudoVWSUBU_VV_M4_MASK 10204 +#define RISCV_PseudoVWSUBU_VV_MF2 10205 +#define RISCV_PseudoVWSUBU_VV_MF2_MASK 10206 +#define RISCV_PseudoVWSUBU_VV_MF4 10207 +#define RISCV_PseudoVWSUBU_VV_MF4_MASK 10208 +#define RISCV_PseudoVWSUBU_VV_MF8 10209 +#define RISCV_PseudoVWSUBU_VV_MF8_MASK 10210 +#define RISCV_PseudoVWSUBU_VX_M1 10211 +#define RISCV_PseudoVWSUBU_VX_M1_MASK 10212 +#define RISCV_PseudoVWSUBU_VX_M2 10213 +#define RISCV_PseudoVWSUBU_VX_M2_MASK 10214 +#define RISCV_PseudoVWSUBU_VX_M4 10215 +#define RISCV_PseudoVWSUBU_VX_M4_MASK 10216 +#define RISCV_PseudoVWSUBU_VX_MF2 10217 +#define RISCV_PseudoVWSUBU_VX_MF2_MASK 10218 +#define RISCV_PseudoVWSUBU_VX_MF4 10219 +#define RISCV_PseudoVWSUBU_VX_MF4_MASK 10220 +#define RISCV_PseudoVWSUBU_VX_MF8 10221 +#define RISCV_PseudoVWSUBU_VX_MF8_MASK 10222 +#define RISCV_PseudoVWSUBU_WV_M1 10223 +#define RISCV_PseudoVWSUBU_WV_M1_MASK 10224 +#define RISCV_PseudoVWSUBU_WV_M1_MASK_TIED 10225 +#define RISCV_PseudoVWSUBU_WV_M1_TIED 10226 +#define RISCV_PseudoVWSUBU_WV_M2 10227 +#define RISCV_PseudoVWSUBU_WV_M2_MASK 10228 +#define RISCV_PseudoVWSUBU_WV_M2_MASK_TIED 10229 +#define RISCV_PseudoVWSUBU_WV_M2_TIED 10230 +#define RISCV_PseudoVWSUBU_WV_M4 10231 +#define RISCV_PseudoVWSUBU_WV_M4_MASK 10232 +#define RISCV_PseudoVWSUBU_WV_M4_MASK_TIED 10233 +#define RISCV_PseudoVWSUBU_WV_M4_TIED 10234 +#define RISCV_PseudoVWSUBU_WV_MF2 10235 +#define RISCV_PseudoVWSUBU_WV_MF2_MASK 10236 +#define RISCV_PseudoVWSUBU_WV_MF2_MASK_TIED 10237 +#define RISCV_PseudoVWSUBU_WV_MF2_TIED 10238 +#define RISCV_PseudoVWSUBU_WV_MF4 10239 +#define RISCV_PseudoVWSUBU_WV_MF4_MASK 10240 +#define RISCV_PseudoVWSUBU_WV_MF4_MASK_TIED 10241 +#define RISCV_PseudoVWSUBU_WV_MF4_TIED 10242 +#define RISCV_PseudoVWSUBU_WV_MF8 10243 +#define RISCV_PseudoVWSUBU_WV_MF8_MASK 10244 +#define RISCV_PseudoVWSUBU_WV_MF8_MASK_TIED 10245 +#define RISCV_PseudoVWSUBU_WV_MF8_TIED 10246 +#define RISCV_PseudoVWSUBU_WX_M1 10247 +#define RISCV_PseudoVWSUBU_WX_M1_MASK 10248 +#define RISCV_PseudoVWSUBU_WX_M2 10249 +#define RISCV_PseudoVWSUBU_WX_M2_MASK 10250 +#define RISCV_PseudoVWSUBU_WX_M4 10251 +#define RISCV_PseudoVWSUBU_WX_M4_MASK 10252 +#define RISCV_PseudoVWSUBU_WX_MF2 10253 +#define RISCV_PseudoVWSUBU_WX_MF2_MASK 10254 +#define RISCV_PseudoVWSUBU_WX_MF4 10255 +#define RISCV_PseudoVWSUBU_WX_MF4_MASK 10256 +#define RISCV_PseudoVWSUBU_WX_MF8 10257 +#define RISCV_PseudoVWSUBU_WX_MF8_MASK 10258 +#define RISCV_PseudoVWSUB_VV_M1 10259 +#define RISCV_PseudoVWSUB_VV_M1_MASK 10260 +#define RISCV_PseudoVWSUB_VV_M2 10261 +#define RISCV_PseudoVWSUB_VV_M2_MASK 10262 +#define RISCV_PseudoVWSUB_VV_M4 10263 +#define RISCV_PseudoVWSUB_VV_M4_MASK 10264 +#define RISCV_PseudoVWSUB_VV_MF2 10265 +#define RISCV_PseudoVWSUB_VV_MF2_MASK 10266 +#define RISCV_PseudoVWSUB_VV_MF4 10267 +#define RISCV_PseudoVWSUB_VV_MF4_MASK 10268 +#define RISCV_PseudoVWSUB_VV_MF8 10269 +#define RISCV_PseudoVWSUB_VV_MF8_MASK 10270 +#define RISCV_PseudoVWSUB_VX_M1 10271 +#define RISCV_PseudoVWSUB_VX_M1_MASK 10272 +#define RISCV_PseudoVWSUB_VX_M2 10273 +#define RISCV_PseudoVWSUB_VX_M2_MASK 10274 +#define RISCV_PseudoVWSUB_VX_M4 10275 +#define RISCV_PseudoVWSUB_VX_M4_MASK 10276 +#define RISCV_PseudoVWSUB_VX_MF2 10277 +#define RISCV_PseudoVWSUB_VX_MF2_MASK 10278 +#define RISCV_PseudoVWSUB_VX_MF4 10279 +#define RISCV_PseudoVWSUB_VX_MF4_MASK 10280 +#define RISCV_PseudoVWSUB_VX_MF8 10281 +#define RISCV_PseudoVWSUB_VX_MF8_MASK 10282 +#define RISCV_PseudoVWSUB_WV_M1 10283 +#define RISCV_PseudoVWSUB_WV_M1_MASK 10284 +#define RISCV_PseudoVWSUB_WV_M1_MASK_TIED 10285 +#define RISCV_PseudoVWSUB_WV_M1_TIED 10286 +#define RISCV_PseudoVWSUB_WV_M2 10287 +#define RISCV_PseudoVWSUB_WV_M2_MASK 10288 +#define RISCV_PseudoVWSUB_WV_M2_MASK_TIED 10289 +#define RISCV_PseudoVWSUB_WV_M2_TIED 10290 +#define RISCV_PseudoVWSUB_WV_M4 10291 +#define RISCV_PseudoVWSUB_WV_M4_MASK 10292 +#define RISCV_PseudoVWSUB_WV_M4_MASK_TIED 10293 +#define RISCV_PseudoVWSUB_WV_M4_TIED 10294 +#define RISCV_PseudoVWSUB_WV_MF2 10295 +#define RISCV_PseudoVWSUB_WV_MF2_MASK 10296 +#define RISCV_PseudoVWSUB_WV_MF2_MASK_TIED 10297 +#define RISCV_PseudoVWSUB_WV_MF2_TIED 10298 +#define RISCV_PseudoVWSUB_WV_MF4 10299 +#define RISCV_PseudoVWSUB_WV_MF4_MASK 10300 +#define RISCV_PseudoVWSUB_WV_MF4_MASK_TIED 10301 +#define RISCV_PseudoVWSUB_WV_MF4_TIED 10302 +#define RISCV_PseudoVWSUB_WV_MF8 10303 +#define RISCV_PseudoVWSUB_WV_MF8_MASK 10304 +#define RISCV_PseudoVWSUB_WV_MF8_MASK_TIED 10305 +#define RISCV_PseudoVWSUB_WV_MF8_TIED 10306 +#define RISCV_PseudoVWSUB_WX_M1 10307 +#define RISCV_PseudoVWSUB_WX_M1_MASK 10308 +#define RISCV_PseudoVWSUB_WX_M2 10309 +#define RISCV_PseudoVWSUB_WX_M2_MASK 10310 +#define RISCV_PseudoVWSUB_WX_M4 10311 +#define RISCV_PseudoVWSUB_WX_M4_MASK 10312 +#define RISCV_PseudoVWSUB_WX_MF2 10313 +#define RISCV_PseudoVWSUB_WX_MF2_MASK 10314 +#define RISCV_PseudoVWSUB_WX_MF4 10315 +#define RISCV_PseudoVWSUB_WX_MF4_MASK 10316 +#define RISCV_PseudoVWSUB_WX_MF8 10317 +#define RISCV_PseudoVWSUB_WX_MF8_MASK 10318 +#define RISCV_PseudoVXOR_VI_M1 10319 +#define RISCV_PseudoVXOR_VI_M1_MASK 10320 +#define RISCV_PseudoVXOR_VI_M2 10321 +#define RISCV_PseudoVXOR_VI_M2_MASK 10322 +#define RISCV_PseudoVXOR_VI_M4 10323 +#define RISCV_PseudoVXOR_VI_M4_MASK 10324 +#define RISCV_PseudoVXOR_VI_M8 10325 +#define RISCV_PseudoVXOR_VI_M8_MASK 10326 +#define RISCV_PseudoVXOR_VI_MF2 10327 +#define RISCV_PseudoVXOR_VI_MF2_MASK 10328 +#define RISCV_PseudoVXOR_VI_MF4 10329 +#define RISCV_PseudoVXOR_VI_MF4_MASK 10330 +#define RISCV_PseudoVXOR_VI_MF8 10331 +#define RISCV_PseudoVXOR_VI_MF8_MASK 10332 +#define RISCV_PseudoVXOR_VV_M1 10333 +#define RISCV_PseudoVXOR_VV_M1_MASK 10334 +#define RISCV_PseudoVXOR_VV_M2 10335 +#define RISCV_PseudoVXOR_VV_M2_MASK 10336 +#define RISCV_PseudoVXOR_VV_M4 10337 +#define RISCV_PseudoVXOR_VV_M4_MASK 10338 +#define RISCV_PseudoVXOR_VV_M8 10339 +#define RISCV_PseudoVXOR_VV_M8_MASK 10340 +#define RISCV_PseudoVXOR_VV_MF2 10341 +#define RISCV_PseudoVXOR_VV_MF2_MASK 10342 +#define RISCV_PseudoVXOR_VV_MF4 10343 +#define RISCV_PseudoVXOR_VV_MF4_MASK 10344 +#define RISCV_PseudoVXOR_VV_MF8 10345 +#define RISCV_PseudoVXOR_VV_MF8_MASK 10346 +#define RISCV_PseudoVXOR_VX_M1 10347 +#define RISCV_PseudoVXOR_VX_M1_MASK 10348 +#define RISCV_PseudoVXOR_VX_M2 10349 +#define RISCV_PseudoVXOR_VX_M2_MASK 10350 +#define RISCV_PseudoVXOR_VX_M4 10351 +#define RISCV_PseudoVXOR_VX_M4_MASK 10352 +#define RISCV_PseudoVXOR_VX_M8 10353 +#define RISCV_PseudoVXOR_VX_M8_MASK 10354 +#define RISCV_PseudoVXOR_VX_MF2 10355 +#define RISCV_PseudoVXOR_VX_MF2_MASK 10356 +#define RISCV_PseudoVXOR_VX_MF4 10357 +#define RISCV_PseudoVXOR_VX_MF4_MASK 10358 +#define RISCV_PseudoVXOR_VX_MF8 10359 +#define RISCV_PseudoVXOR_VX_MF8_MASK 10360 +#define RISCV_PseudoVZEXT_VF2_M1 10361 +#define RISCV_PseudoVZEXT_VF2_M1_MASK 10362 +#define RISCV_PseudoVZEXT_VF2_M2 10363 +#define RISCV_PseudoVZEXT_VF2_M2_MASK 10364 +#define RISCV_PseudoVZEXT_VF2_M4 10365 +#define RISCV_PseudoVZEXT_VF2_M4_MASK 10366 +#define RISCV_PseudoVZEXT_VF2_M8 10367 +#define RISCV_PseudoVZEXT_VF2_M8_MASK 10368 +#define RISCV_PseudoVZEXT_VF2_MF2 10369 +#define RISCV_PseudoVZEXT_VF2_MF2_MASK 10370 +#define RISCV_PseudoVZEXT_VF2_MF4 10371 +#define RISCV_PseudoVZEXT_VF2_MF4_MASK 10372 +#define RISCV_PseudoVZEXT_VF4_M1 10373 +#define RISCV_PseudoVZEXT_VF4_M1_MASK 10374 +#define RISCV_PseudoVZEXT_VF4_M2 10375 +#define RISCV_PseudoVZEXT_VF4_M2_MASK 10376 +#define RISCV_PseudoVZEXT_VF4_M4 10377 +#define RISCV_PseudoVZEXT_VF4_M4_MASK 10378 +#define RISCV_PseudoVZEXT_VF4_M8 10379 +#define RISCV_PseudoVZEXT_VF4_M8_MASK 10380 +#define RISCV_PseudoVZEXT_VF4_MF2 10381 +#define RISCV_PseudoVZEXT_VF4_MF2_MASK 10382 +#define RISCV_PseudoVZEXT_VF8_M1 10383 +#define RISCV_PseudoVZEXT_VF8_M1_MASK 10384 +#define RISCV_PseudoVZEXT_VF8_M2 10385 +#define RISCV_PseudoVZEXT_VF8_M2_MASK 10386 +#define RISCV_PseudoVZEXT_VF8_M4 10387 +#define RISCV_PseudoVZEXT_VF8_M4_MASK 10388 +#define RISCV_PseudoVZEXT_VF8_M8 10389 +#define RISCV_PseudoVZEXT_VF8_M8_MASK 10390 +#define RISCV_PseudoZEXT_H 10391 +#define RISCV_PseudoZEXT_W 10392 +#define RISCV_ReadCycleWide 10393 +#define RISCV_ReadFRM 10394 +#define RISCV_Select_FPR16_Using_CC_GPR 10395 +#define RISCV_Select_FPR32_Using_CC_GPR 10396 +#define RISCV_Select_FPR64_Using_CC_GPR 10397 +#define RISCV_Select_GPR_Using_CC_GPR 10398 +#define RISCV_SplitF64Pseudo 10399 +#define RISCV_WriteFRM 10400 +#define RISCV_WriteFRMImm 10401 +#define RISCV_ADD 10402 +#define RISCV_ADDI 10403 +#define RISCV_ADDIW 10404 +#define RISCV_ADDUW 10405 +#define RISCV_ADDW 10406 +#define RISCV_AMOADD_D 10407 +#define RISCV_AMOADD_D_AQ 10408 +#define RISCV_AMOADD_D_AQ_RL 10409 +#define RISCV_AMOADD_D_RL 10410 +#define RISCV_AMOADD_W 10411 +#define RISCV_AMOADD_W_AQ 10412 +#define RISCV_AMOADD_W_AQ_RL 10413 +#define RISCV_AMOADD_W_RL 10414 +#define RISCV_AMOAND_D 10415 +#define RISCV_AMOAND_D_AQ 10416 +#define RISCV_AMOAND_D_AQ_RL 10417 +#define RISCV_AMOAND_D_RL 10418 +#define RISCV_AMOAND_W 10419 +#define RISCV_AMOAND_W_AQ 10420 +#define RISCV_AMOAND_W_AQ_RL 10421 +#define RISCV_AMOAND_W_RL 10422 +#define RISCV_AMOMAXU_D 10423 +#define RISCV_AMOMAXU_D_AQ 10424 +#define RISCV_AMOMAXU_D_AQ_RL 10425 +#define RISCV_AMOMAXU_D_RL 10426 +#define RISCV_AMOMAXU_W 10427 +#define RISCV_AMOMAXU_W_AQ 10428 +#define RISCV_AMOMAXU_W_AQ_RL 10429 +#define RISCV_AMOMAXU_W_RL 10430 +#define RISCV_AMOMAX_D 10431 +#define RISCV_AMOMAX_D_AQ 10432 +#define RISCV_AMOMAX_D_AQ_RL 10433 +#define RISCV_AMOMAX_D_RL 10434 +#define RISCV_AMOMAX_W 10435 +#define RISCV_AMOMAX_W_AQ 10436 +#define RISCV_AMOMAX_W_AQ_RL 10437 +#define RISCV_AMOMAX_W_RL 10438 +#define RISCV_AMOMINU_D 10439 +#define RISCV_AMOMINU_D_AQ 10440 +#define RISCV_AMOMINU_D_AQ_RL 10441 +#define RISCV_AMOMINU_D_RL 10442 +#define RISCV_AMOMINU_W 10443 +#define RISCV_AMOMINU_W_AQ 10444 +#define RISCV_AMOMINU_W_AQ_RL 10445 +#define RISCV_AMOMINU_W_RL 10446 +#define RISCV_AMOMIN_D 10447 +#define RISCV_AMOMIN_D_AQ 10448 +#define RISCV_AMOMIN_D_AQ_RL 10449 +#define RISCV_AMOMIN_D_RL 10450 +#define RISCV_AMOMIN_W 10451 +#define RISCV_AMOMIN_W_AQ 10452 +#define RISCV_AMOMIN_W_AQ_RL 10453 +#define RISCV_AMOMIN_W_RL 10454 +#define RISCV_AMOOR_D 10455 +#define RISCV_AMOOR_D_AQ 10456 +#define RISCV_AMOOR_D_AQ_RL 10457 +#define RISCV_AMOOR_D_RL 10458 +#define RISCV_AMOOR_W 10459 +#define RISCV_AMOOR_W_AQ 10460 +#define RISCV_AMOOR_W_AQ_RL 10461 +#define RISCV_AMOOR_W_RL 10462 +#define RISCV_AMOSWAP_D 10463 +#define RISCV_AMOSWAP_D_AQ 10464 +#define RISCV_AMOSWAP_D_AQ_RL 10465 +#define RISCV_AMOSWAP_D_RL 10466 +#define RISCV_AMOSWAP_W 10467 +#define RISCV_AMOSWAP_W_AQ 10468 +#define RISCV_AMOSWAP_W_AQ_RL 10469 +#define RISCV_AMOSWAP_W_RL 10470 +#define RISCV_AMOXOR_D 10471 +#define RISCV_AMOXOR_D_AQ 10472 +#define RISCV_AMOXOR_D_AQ_RL 10473 +#define RISCV_AMOXOR_D_RL 10474 +#define RISCV_AMOXOR_W 10475 +#define RISCV_AMOXOR_W_AQ 10476 +#define RISCV_AMOXOR_W_AQ_RL 10477 +#define RISCV_AMOXOR_W_RL 10478 +#define RISCV_AND 10479 +#define RISCV_ANDI 10480 +#define RISCV_ANDN 10481 +#define RISCV_AUIPC 10482 +#define RISCV_BCLR 10483 +#define RISCV_BCLRI 10484 +#define RISCV_BCOMPRESS 10485 +#define RISCV_BCOMPRESSW 10486 +#define RISCV_BDECOMPRESS 10487 +#define RISCV_BDECOMPRESSW 10488 +#define RISCV_BEQ 10489 +#define RISCV_BEXT 10490 +#define RISCV_BEXTI 10491 +#define RISCV_BFP 10492 +#define RISCV_BFPW 10493 +#define RISCV_BGE 10494 +#define RISCV_BGEU 10495 +#define RISCV_BINV 10496 +#define RISCV_BINVI 10497 +#define RISCV_BLT 10498 +#define RISCV_BLTU 10499 +#define RISCV_BMATFLIP 10500 +#define RISCV_BMATOR 10501 +#define RISCV_BMATXOR 10502 +#define RISCV_BNE 10503 +#define RISCV_BSET 10504 +#define RISCV_BSETI 10505 +#define RISCV_CLMUL 10506 +#define RISCV_CLMULH 10507 +#define RISCV_CLMULR 10508 +#define RISCV_CLZ 10509 +#define RISCV_CLZW 10510 +#define RISCV_CMIX 10511 +#define RISCV_CMOV 10512 +#define RISCV_CPOP 10513 +#define RISCV_CPOPW 10514 +#define RISCV_CRC32B 10515 +#define RISCV_CRC32CB 10516 +#define RISCV_CRC32CD 10517 +#define RISCV_CRC32CH 10518 +#define RISCV_CRC32CW 10519 +#define RISCV_CRC32D 10520 +#define RISCV_CRC32H 10521 +#define RISCV_CRC32W 10522 +#define RISCV_CSRRC 10523 +#define RISCV_CSRRCI 10524 +#define RISCV_CSRRS 10525 +#define RISCV_CSRRSI 10526 +#define RISCV_CSRRW 10527 +#define RISCV_CSRRWI 10528 +#define RISCV_CTZ 10529 +#define RISCV_CTZW 10530 +#define RISCV_C_ADD 10531 +#define RISCV_C_ADDI 10532 +#define RISCV_C_ADDI16SP 10533 +#define RISCV_C_ADDI4SPN 10534 +#define RISCV_C_ADDIW 10535 +#define RISCV_C_ADDI_HINT_IMM_ZERO 10536 +#define RISCV_C_ADDI_HINT_X0 10537 +#define RISCV_C_ADDI_NOP 10538 +#define RISCV_C_ADDW 10539 +#define RISCV_C_ADD_HINT 10540 +#define RISCV_C_AND 10541 +#define RISCV_C_ANDI 10542 +#define RISCV_C_BEQZ 10543 +#define RISCV_C_BNEZ 10544 +#define RISCV_C_EBREAK 10545 +#define RISCV_C_FLD 10546 +#define RISCV_C_FLDSP 10547 +#define RISCV_C_FLW 10548 +#define RISCV_C_FLWSP 10549 +#define RISCV_C_FSD 10550 +#define RISCV_C_FSDSP 10551 +#define RISCV_C_FSW 10552 +#define RISCV_C_FSWSP 10553 +#define RISCV_C_J 10554 +#define RISCV_C_JAL 10555 +#define RISCV_C_JALR 10556 +#define RISCV_C_JR 10557 +#define RISCV_C_LD 10558 +#define RISCV_C_LDSP 10559 +#define RISCV_C_LI 10560 +#define RISCV_C_LI_HINT 10561 +#define RISCV_C_LUI 10562 +#define RISCV_C_LUI_HINT 10563 +#define RISCV_C_LW 10564 +#define RISCV_C_LWSP 10565 +#define RISCV_C_MV 10566 +#define RISCV_C_MV_HINT 10567 +#define RISCV_C_NOP 10568 +#define RISCV_C_NOP_HINT 10569 +#define RISCV_C_OR 10570 +#define RISCV_C_SD 10571 +#define RISCV_C_SDSP 10572 +#define RISCV_C_SLLI 10573 +#define RISCV_C_SLLI64_HINT 10574 +#define RISCV_C_SLLI_HINT 10575 +#define RISCV_C_SRAI 10576 +#define RISCV_C_SRAI64_HINT 10577 +#define RISCV_C_SRLI 10578 +#define RISCV_C_SRLI64_HINT 10579 +#define RISCV_C_SUB 10580 +#define RISCV_C_SUBW 10581 +#define RISCV_C_SW 10582 +#define RISCV_C_SWSP 10583 +#define RISCV_C_UNIMP 10584 +#define RISCV_C_XOR 10585 +#define RISCV_DIV 10586 +#define RISCV_DIVU 10587 +#define RISCV_DIVUW 10588 +#define RISCV_DIVW 10589 +#define RISCV_DRET 10590 +#define RISCV_EBREAK 10591 +#define RISCV_ECALL 10592 +#define RISCV_FADD_D 10593 +#define RISCV_FADD_H 10594 +#define RISCV_FADD_S 10595 +#define RISCV_FCLASS_D 10596 +#define RISCV_FCLASS_H 10597 +#define RISCV_FCLASS_S 10598 +#define RISCV_FCVT_D_H 10599 +#define RISCV_FCVT_D_L 10600 +#define RISCV_FCVT_D_LU 10601 +#define RISCV_FCVT_D_S 10602 +#define RISCV_FCVT_D_W 10603 +#define RISCV_FCVT_D_WU 10604 +#define RISCV_FCVT_H_D 10605 +#define RISCV_FCVT_H_L 10606 +#define RISCV_FCVT_H_LU 10607 +#define RISCV_FCVT_H_S 10608 +#define RISCV_FCVT_H_W 10609 +#define RISCV_FCVT_H_WU 10610 +#define RISCV_FCVT_LU_D 10611 +#define RISCV_FCVT_LU_H 10612 +#define RISCV_FCVT_LU_S 10613 +#define RISCV_FCVT_L_D 10614 +#define RISCV_FCVT_L_H 10615 +#define RISCV_FCVT_L_S 10616 +#define RISCV_FCVT_S_D 10617 +#define RISCV_FCVT_S_H 10618 +#define RISCV_FCVT_S_L 10619 +#define RISCV_FCVT_S_LU 10620 +#define RISCV_FCVT_S_W 10621 +#define RISCV_FCVT_S_WU 10622 +#define RISCV_FCVT_WU_D 10623 +#define RISCV_FCVT_WU_H 10624 +#define RISCV_FCVT_WU_S 10625 +#define RISCV_FCVT_W_D 10626 +#define RISCV_FCVT_W_H 10627 +#define RISCV_FCVT_W_S 10628 +#define RISCV_FDIV_D 10629 +#define RISCV_FDIV_H 10630 +#define RISCV_FDIV_S 10631 +#define RISCV_FENCE 10632 +#define RISCV_FENCE_I 10633 +#define RISCV_FENCE_TSO 10634 +#define RISCV_FEQ_D 10635 +#define RISCV_FEQ_H 10636 +#define RISCV_FEQ_S 10637 +#define RISCV_FLD 10638 +#define RISCV_FLE_D 10639 +#define RISCV_FLE_H 10640 +#define RISCV_FLE_S 10641 +#define RISCV_FLH 10642 +#define RISCV_FLT_D 10643 +#define RISCV_FLT_H 10644 +#define RISCV_FLT_S 10645 +#define RISCV_FLW 10646 +#define RISCV_FMADD_D 10647 +#define RISCV_FMADD_H 10648 +#define RISCV_FMADD_S 10649 +#define RISCV_FMAX_D 10650 +#define RISCV_FMAX_H 10651 +#define RISCV_FMAX_S 10652 +#define RISCV_FMIN_D 10653 +#define RISCV_FMIN_H 10654 +#define RISCV_FMIN_S 10655 +#define RISCV_FMSUB_D 10656 +#define RISCV_FMSUB_H 10657 +#define RISCV_FMSUB_S 10658 +#define RISCV_FMUL_D 10659 +#define RISCV_FMUL_H 10660 +#define RISCV_FMUL_S 10661 +#define RISCV_FMV_D_X 10662 +#define RISCV_FMV_H_X 10663 +#define RISCV_FMV_W_X 10664 +#define RISCV_FMV_X_D 10665 +#define RISCV_FMV_X_H 10666 +#define RISCV_FMV_X_W 10667 +#define RISCV_FNMADD_D 10668 +#define RISCV_FNMADD_H 10669 +#define RISCV_FNMADD_S 10670 +#define RISCV_FNMSUB_D 10671 +#define RISCV_FNMSUB_H 10672 +#define RISCV_FNMSUB_S 10673 +#define RISCV_FSD 10674 +#define RISCV_FSGNJN_D 10675 +#define RISCV_FSGNJN_H 10676 +#define RISCV_FSGNJN_S 10677 +#define RISCV_FSGNJX_D 10678 +#define RISCV_FSGNJX_H 10679 +#define RISCV_FSGNJX_S 10680 +#define RISCV_FSGNJ_D 10681 +#define RISCV_FSGNJ_H 10682 +#define RISCV_FSGNJ_S 10683 +#define RISCV_FSH 10684 +#define RISCV_FSL 10685 +#define RISCV_FSLW 10686 +#define RISCV_FSQRT_D 10687 +#define RISCV_FSQRT_H 10688 +#define RISCV_FSQRT_S 10689 +#define RISCV_FSR 10690 +#define RISCV_FSRI 10691 +#define RISCV_FSRIW 10692 +#define RISCV_FSRW 10693 +#define RISCV_FSUB_D 10694 +#define RISCV_FSUB_H 10695 +#define RISCV_FSUB_S 10696 +#define RISCV_FSW 10697 +#define RISCV_GORC 10698 +#define RISCV_GORCI 10699 +#define RISCV_GORCIW 10700 +#define RISCV_GORCW 10701 +#define RISCV_GREV 10702 +#define RISCV_GREVI 10703 +#define RISCV_GREVIW 10704 +#define RISCV_GREVW 10705 +#define RISCV_InsnB 10706 +#define RISCV_InsnI 10707 +#define RISCV_InsnI_Mem 10708 +#define RISCV_InsnJ 10709 +#define RISCV_InsnR 10710 +#define RISCV_InsnR4 10711 +#define RISCV_InsnS 10712 +#define RISCV_InsnU 10713 +#define RISCV_JAL 10714 +#define RISCV_JALR 10715 +#define RISCV_LB 10716 +#define RISCV_LBU 10717 +#define RISCV_LD 10718 +#define RISCV_LH 10719 +#define RISCV_LHU 10720 +#define RISCV_LR_D 10721 +#define RISCV_LR_D_AQ 10722 +#define RISCV_LR_D_AQ_RL 10723 +#define RISCV_LR_D_RL 10724 +#define RISCV_LR_W 10725 +#define RISCV_LR_W_AQ 10726 +#define RISCV_LR_W_AQ_RL 10727 +#define RISCV_LR_W_RL 10728 +#define RISCV_LUI 10729 +#define RISCV_LW 10730 +#define RISCV_LWU 10731 +#define RISCV_MAX 10732 +#define RISCV_MAXU 10733 +#define RISCV_MIN 10734 +#define RISCV_MINU 10735 +#define RISCV_MRET 10736 +#define RISCV_MUL 10737 +#define RISCV_MULH 10738 +#define RISCV_MULHSU 10739 +#define RISCV_MULHU 10740 +#define RISCV_MULW 10741 +#define RISCV_OR 10742 +#define RISCV_ORCB 10743 +#define RISCV_ORI 10744 +#define RISCV_ORN 10745 +#define RISCV_PACK 10746 +#define RISCV_PACKH 10747 +#define RISCV_PACKU 10748 +#define RISCV_PACKUW 10749 +#define RISCV_PACKW 10750 +#define RISCV_REM 10751 +#define RISCV_REMU 10752 +#define RISCV_REMUW 10753 +#define RISCV_REMW 10754 +#define RISCV_REV8_RV32 10755 +#define RISCV_REV8_RV64 10756 +#define RISCV_ROL 10757 +#define RISCV_ROLW 10758 +#define RISCV_ROR 10759 +#define RISCV_RORI 10760 +#define RISCV_RORIW 10761 +#define RISCV_RORW 10762 +#define RISCV_SB 10763 +#define RISCV_SC_D 10764 +#define RISCV_SC_D_AQ 10765 +#define RISCV_SC_D_AQ_RL 10766 +#define RISCV_SC_D_RL 10767 +#define RISCV_SC_W 10768 +#define RISCV_SC_W_AQ 10769 +#define RISCV_SC_W_AQ_RL 10770 +#define RISCV_SC_W_RL 10771 +#define RISCV_SD 10772 +#define RISCV_SEXTB 10773 +#define RISCV_SEXTH 10774 +#define RISCV_SFENCE_VMA 10775 +#define RISCV_SH 10776 +#define RISCV_SH1ADD 10777 +#define RISCV_SH1ADDUW 10778 +#define RISCV_SH2ADD 10779 +#define RISCV_SH2ADDUW 10780 +#define RISCV_SH3ADD 10781 +#define RISCV_SH3ADDUW 10782 +#define RISCV_SHFL 10783 +#define RISCV_SHFLI 10784 +#define RISCV_SHFLW 10785 +#define RISCV_SLL 10786 +#define RISCV_SLLI 10787 +#define RISCV_SLLIUW 10788 +#define RISCV_SLLIW 10789 +#define RISCV_SLLW 10790 +#define RISCV_SLT 10791 +#define RISCV_SLTI 10792 +#define RISCV_SLTIU 10793 +#define RISCV_SLTU 10794 +#define RISCV_SRA 10795 +#define RISCV_SRAI 10796 +#define RISCV_SRAIW 10797 +#define RISCV_SRAW 10798 +#define RISCV_SRET 10799 +#define RISCV_SRL 10800 +#define RISCV_SRLI 10801 +#define RISCV_SRLIW 10802 +#define RISCV_SRLW 10803 +#define RISCV_SUB 10804 +#define RISCV_SUBW 10805 +#define RISCV_SW 10806 +#define RISCV_UNIMP 10807 +#define RISCV_UNSHFL 10808 +#define RISCV_UNSHFLI 10809 +#define RISCV_UNSHFLW 10810 +#define RISCV_URET 10811 +#define RISCV_VAADDU_VV 10812 +#define RISCV_VAADDU_VX 10813 +#define RISCV_VAADD_VV 10814 +#define RISCV_VAADD_VX 10815 +#define RISCV_VADC_VIM 10816 +#define RISCV_VADC_VVM 10817 +#define RISCV_VADC_VXM 10818 +#define RISCV_VADD_VI 10819 +#define RISCV_VADD_VV 10820 +#define RISCV_VADD_VX 10821 +#define RISCV_VAMOADDEI16_UNWD 10822 +#define RISCV_VAMOADDEI16_WD 10823 +#define RISCV_VAMOADDEI32_UNWD 10824 +#define RISCV_VAMOADDEI32_WD 10825 +#define RISCV_VAMOADDEI64_UNWD 10826 +#define RISCV_VAMOADDEI64_WD 10827 +#define RISCV_VAMOADDEI8_UNWD 10828 +#define RISCV_VAMOADDEI8_WD 10829 +#define RISCV_VAMOANDEI16_UNWD 10830 +#define RISCV_VAMOANDEI16_WD 10831 +#define RISCV_VAMOANDEI32_UNWD 10832 +#define RISCV_VAMOANDEI32_WD 10833 +#define RISCV_VAMOANDEI64_UNWD 10834 +#define RISCV_VAMOANDEI64_WD 10835 +#define RISCV_VAMOANDEI8_UNWD 10836 +#define RISCV_VAMOANDEI8_WD 10837 +#define RISCV_VAMOMAXEI16_UNWD 10838 +#define RISCV_VAMOMAXEI16_WD 10839 +#define RISCV_VAMOMAXEI32_UNWD 10840 +#define RISCV_VAMOMAXEI32_WD 10841 +#define RISCV_VAMOMAXEI64_UNWD 10842 +#define RISCV_VAMOMAXEI64_WD 10843 +#define RISCV_VAMOMAXEI8_UNWD 10844 +#define RISCV_VAMOMAXEI8_WD 10845 +#define RISCV_VAMOMAXUEI16_UNWD 10846 +#define RISCV_VAMOMAXUEI16_WD 10847 +#define RISCV_VAMOMAXUEI32_UNWD 10848 +#define RISCV_VAMOMAXUEI32_WD 10849 +#define RISCV_VAMOMAXUEI64_UNWD 10850 +#define RISCV_VAMOMAXUEI64_WD 10851 +#define RISCV_VAMOMAXUEI8_UNWD 10852 +#define RISCV_VAMOMAXUEI8_WD 10853 +#define RISCV_VAMOMINEI16_UNWD 10854 +#define RISCV_VAMOMINEI16_WD 10855 +#define RISCV_VAMOMINEI32_UNWD 10856 +#define RISCV_VAMOMINEI32_WD 10857 +#define RISCV_VAMOMINEI64_UNWD 10858 +#define RISCV_VAMOMINEI64_WD 10859 +#define RISCV_VAMOMINEI8_UNWD 10860 +#define RISCV_VAMOMINEI8_WD 10861 +#define RISCV_VAMOMINUEI16_UNWD 10862 +#define RISCV_VAMOMINUEI16_WD 10863 +#define RISCV_VAMOMINUEI32_UNWD 10864 +#define RISCV_VAMOMINUEI32_WD 10865 +#define RISCV_VAMOMINUEI64_UNWD 10866 +#define RISCV_VAMOMINUEI64_WD 10867 +#define RISCV_VAMOMINUEI8_UNWD 10868 +#define RISCV_VAMOMINUEI8_WD 10869 +#define RISCV_VAMOOREI16_UNWD 10870 +#define RISCV_VAMOOREI16_WD 10871 +#define RISCV_VAMOOREI32_UNWD 10872 +#define RISCV_VAMOOREI32_WD 10873 +#define RISCV_VAMOOREI64_UNWD 10874 +#define RISCV_VAMOOREI64_WD 10875 +#define RISCV_VAMOOREI8_UNWD 10876 +#define RISCV_VAMOOREI8_WD 10877 +#define RISCV_VAMOSWAPEI16_UNWD 10878 +#define RISCV_VAMOSWAPEI16_WD 10879 +#define RISCV_VAMOSWAPEI32_UNWD 10880 +#define RISCV_VAMOSWAPEI32_WD 10881 +#define RISCV_VAMOSWAPEI64_UNWD 10882 +#define RISCV_VAMOSWAPEI64_WD 10883 +#define RISCV_VAMOSWAPEI8_UNWD 10884 +#define RISCV_VAMOSWAPEI8_WD 10885 +#define RISCV_VAMOXOREI16_UNWD 10886 +#define RISCV_VAMOXOREI16_WD 10887 +#define RISCV_VAMOXOREI32_UNWD 10888 +#define RISCV_VAMOXOREI32_WD 10889 +#define RISCV_VAMOXOREI64_UNWD 10890 +#define RISCV_VAMOXOREI64_WD 10891 +#define RISCV_VAMOXOREI8_UNWD 10892 +#define RISCV_VAMOXOREI8_WD 10893 +#define RISCV_VAND_VI 10894 +#define RISCV_VAND_VV 10895 +#define RISCV_VAND_VX 10896 +#define RISCV_VASUBU_VV 10897 +#define RISCV_VASUBU_VX 10898 +#define RISCV_VASUB_VV 10899 +#define RISCV_VASUB_VX 10900 +#define RISCV_VCOMPRESS_VM 10901 +#define RISCV_VCPOP_M 10902 +#define RISCV_VDIVU_VV 10903 +#define RISCV_VDIVU_VX 10904 +#define RISCV_VDIV_VV 10905 +#define RISCV_VDIV_VX 10906 +#define RISCV_VFADD_VF 10907 +#define RISCV_VFADD_VV 10908 +#define RISCV_VFCLASS_V 10909 +#define RISCV_VFCVT_F_XU_V 10910 +#define RISCV_VFCVT_F_X_V 10911 +#define RISCV_VFCVT_RTZ_XU_F_V 10912 +#define RISCV_VFCVT_RTZ_X_F_V 10913 +#define RISCV_VFCVT_XU_F_V 10914 +#define RISCV_VFCVT_X_F_V 10915 +#define RISCV_VFDIV_VF 10916 +#define RISCV_VFDIV_VV 10917 +#define RISCV_VFIRST_M 10918 +#define RISCV_VFMACC_VF 10919 +#define RISCV_VFMACC_VV 10920 +#define RISCV_VFMADD_VF 10921 +#define RISCV_VFMADD_VV 10922 +#define RISCV_VFMAX_VF 10923 +#define RISCV_VFMAX_VV 10924 +#define RISCV_VFMERGE_VFM 10925 +#define RISCV_VFMIN_VF 10926 +#define RISCV_VFMIN_VV 10927 +#define RISCV_VFMSAC_VF 10928 +#define RISCV_VFMSAC_VV 10929 +#define RISCV_VFMSUB_VF 10930 +#define RISCV_VFMSUB_VV 10931 +#define RISCV_VFMUL_VF 10932 +#define RISCV_VFMUL_VV 10933 +#define RISCV_VFMV_F_S 10934 +#define RISCV_VFMV_S_F 10935 +#define RISCV_VFMV_V_F 10936 +#define RISCV_VFNCVT_F_F_W 10937 +#define RISCV_VFNCVT_F_XU_W 10938 +#define RISCV_VFNCVT_F_X_W 10939 +#define RISCV_VFNCVT_ROD_F_F_W 10940 +#define RISCV_VFNCVT_RTZ_XU_F_W 10941 +#define RISCV_VFNCVT_RTZ_X_F_W 10942 +#define RISCV_VFNCVT_XU_F_W 10943 +#define RISCV_VFNCVT_X_F_W 10944 +#define RISCV_VFNMACC_VF 10945 +#define RISCV_VFNMACC_VV 10946 +#define RISCV_VFNMADD_VF 10947 +#define RISCV_VFNMADD_VV 10948 +#define RISCV_VFNMSAC_VF 10949 +#define RISCV_VFNMSAC_VV 10950 +#define RISCV_VFNMSUB_VF 10951 +#define RISCV_VFNMSUB_VV 10952 +#define RISCV_VFRDIV_VF 10953 +#define RISCV_VFREC7_V 10954 +#define RISCV_VFREDMAX_VS 10955 +#define RISCV_VFREDMIN_VS 10956 +#define RISCV_VFREDOSUM_VS 10957 +#define RISCV_VFREDUSUM_VS 10958 +#define RISCV_VFRSQRT7_V 10959 +#define RISCV_VFRSUB_VF 10960 +#define RISCV_VFSGNJN_VF 10961 +#define RISCV_VFSGNJN_VV 10962 +#define RISCV_VFSGNJX_VF 10963 +#define RISCV_VFSGNJX_VV 10964 +#define RISCV_VFSGNJ_VF 10965 +#define RISCV_VFSGNJ_VV 10966 +#define RISCV_VFSLIDE1DOWN_VF 10967 +#define RISCV_VFSLIDE1UP_VF 10968 +#define RISCV_VFSQRT_V 10969 +#define RISCV_VFSUB_VF 10970 +#define RISCV_VFSUB_VV 10971 +#define RISCV_VFWADD_VF 10972 +#define RISCV_VFWADD_VV 10973 +#define RISCV_VFWADD_WF 10974 +#define RISCV_VFWADD_WV 10975 +#define RISCV_VFWCVT_F_F_V 10976 +#define RISCV_VFWCVT_F_XU_V 10977 +#define RISCV_VFWCVT_F_X_V 10978 +#define RISCV_VFWCVT_RTZ_XU_F_V 10979 +#define RISCV_VFWCVT_RTZ_X_F_V 10980 +#define RISCV_VFWCVT_XU_F_V 10981 +#define RISCV_VFWCVT_X_F_V 10982 +#define RISCV_VFWMACC_VF 10983 +#define RISCV_VFWMACC_VV 10984 +#define RISCV_VFWMSAC_VF 10985 +#define RISCV_VFWMSAC_VV 10986 +#define RISCV_VFWMUL_VF 10987 +#define RISCV_VFWMUL_VV 10988 +#define RISCV_VFWNMACC_VF 10989 +#define RISCV_VFWNMACC_VV 10990 +#define RISCV_VFWNMSAC_VF 10991 +#define RISCV_VFWNMSAC_VV 10992 +#define RISCV_VFWREDOSUM_VS 10993 +#define RISCV_VFWREDUSUM_VS 10994 +#define RISCV_VFWSUB_VF 10995 +#define RISCV_VFWSUB_VV 10996 +#define RISCV_VFWSUB_WF 10997 +#define RISCV_VFWSUB_WV 10998 +#define RISCV_VID_V 10999 +#define RISCV_VIOTA_M 11000 +#define RISCV_VL1RE16_V 11001 +#define RISCV_VL1RE32_V 11002 +#define RISCV_VL1RE64_V 11003 +#define RISCV_VL1RE8_V 11004 +#define RISCV_VL2RE16_V 11005 +#define RISCV_VL2RE32_V 11006 +#define RISCV_VL2RE64_V 11007 +#define RISCV_VL2RE8_V 11008 +#define RISCV_VL4RE16_V 11009 +#define RISCV_VL4RE32_V 11010 +#define RISCV_VL4RE64_V 11011 +#define RISCV_VL4RE8_V 11012 +#define RISCV_VL8RE16_V 11013 +#define RISCV_VL8RE32_V 11014 +#define RISCV_VL8RE64_V 11015 +#define RISCV_VL8RE8_V 11016 +#define RISCV_VLE16FF_V 11017 +#define RISCV_VLE16_V 11018 +#define RISCV_VLE32FF_V 11019 +#define RISCV_VLE32_V 11020 +#define RISCV_VLE64FF_V 11021 +#define RISCV_VLE64_V 11022 +#define RISCV_VLE8FF_V 11023 +#define RISCV_VLE8_V 11024 +#define RISCV_VLM_V 11025 +#define RISCV_VLOXEI16_V 11026 +#define RISCV_VLOXEI32_V 11027 +#define RISCV_VLOXEI64_V 11028 +#define RISCV_VLOXEI8_V 11029 +#define RISCV_VLOXSEG2EI16_V 11030 +#define RISCV_VLOXSEG2EI32_V 11031 +#define RISCV_VLOXSEG2EI64_V 11032 +#define RISCV_VLOXSEG2EI8_V 11033 +#define RISCV_VLOXSEG3EI16_V 11034 +#define RISCV_VLOXSEG3EI32_V 11035 +#define RISCV_VLOXSEG3EI64_V 11036 +#define RISCV_VLOXSEG3EI8_V 11037 +#define RISCV_VLOXSEG4EI16_V 11038 +#define RISCV_VLOXSEG4EI32_V 11039 +#define RISCV_VLOXSEG4EI64_V 11040 +#define RISCV_VLOXSEG4EI8_V 11041 +#define RISCV_VLOXSEG5EI16_V 11042 +#define RISCV_VLOXSEG5EI32_V 11043 +#define RISCV_VLOXSEG5EI64_V 11044 +#define RISCV_VLOXSEG5EI8_V 11045 +#define RISCV_VLOXSEG6EI16_V 11046 +#define RISCV_VLOXSEG6EI32_V 11047 +#define RISCV_VLOXSEG6EI64_V 11048 +#define RISCV_VLOXSEG6EI8_V 11049 +#define RISCV_VLOXSEG7EI16_V 11050 +#define RISCV_VLOXSEG7EI32_V 11051 +#define RISCV_VLOXSEG7EI64_V 11052 +#define RISCV_VLOXSEG7EI8_V 11053 +#define RISCV_VLOXSEG8EI16_V 11054 +#define RISCV_VLOXSEG8EI32_V 11055 +#define RISCV_VLOXSEG8EI64_V 11056 +#define RISCV_VLOXSEG8EI8_V 11057 +#define RISCV_VLSE16_V 11058 +#define RISCV_VLSE32_V 11059 +#define RISCV_VLSE64_V 11060 +#define RISCV_VLSE8_V 11061 +#define RISCV_VLSEG2E16FF_V 11062 +#define RISCV_VLSEG2E16_V 11063 +#define RISCV_VLSEG2E32FF_V 11064 +#define RISCV_VLSEG2E32_V 11065 +#define RISCV_VLSEG2E64FF_V 11066 +#define RISCV_VLSEG2E64_V 11067 +#define RISCV_VLSEG2E8FF_V 11068 +#define RISCV_VLSEG2E8_V 11069 +#define RISCV_VLSEG3E16FF_V 11070 +#define RISCV_VLSEG3E16_V 11071 +#define RISCV_VLSEG3E32FF_V 11072 +#define RISCV_VLSEG3E32_V 11073 +#define RISCV_VLSEG3E64FF_V 11074 +#define RISCV_VLSEG3E64_V 11075 +#define RISCV_VLSEG3E8FF_V 11076 +#define RISCV_VLSEG3E8_V 11077 +#define RISCV_VLSEG4E16FF_V 11078 +#define RISCV_VLSEG4E16_V 11079 +#define RISCV_VLSEG4E32FF_V 11080 +#define RISCV_VLSEG4E32_V 11081 +#define RISCV_VLSEG4E64FF_V 11082 +#define RISCV_VLSEG4E64_V 11083 +#define RISCV_VLSEG4E8FF_V 11084 +#define RISCV_VLSEG4E8_V 11085 +#define RISCV_VLSEG5E16FF_V 11086 +#define RISCV_VLSEG5E16_V 11087 +#define RISCV_VLSEG5E32FF_V 11088 +#define RISCV_VLSEG5E32_V 11089 +#define RISCV_VLSEG5E64FF_V 11090 +#define RISCV_VLSEG5E64_V 11091 +#define RISCV_VLSEG5E8FF_V 11092 +#define RISCV_VLSEG5E8_V 11093 +#define RISCV_VLSEG6E16FF_V 11094 +#define RISCV_VLSEG6E16_V 11095 +#define RISCV_VLSEG6E32FF_V 11096 +#define RISCV_VLSEG6E32_V 11097 +#define RISCV_VLSEG6E64FF_V 11098 +#define RISCV_VLSEG6E64_V 11099 +#define RISCV_VLSEG6E8FF_V 11100 +#define RISCV_VLSEG6E8_V 11101 +#define RISCV_VLSEG7E16FF_V 11102 +#define RISCV_VLSEG7E16_V 11103 +#define RISCV_VLSEG7E32FF_V 11104 +#define RISCV_VLSEG7E32_V 11105 +#define RISCV_VLSEG7E64FF_V 11106 +#define RISCV_VLSEG7E64_V 11107 +#define RISCV_VLSEG7E8FF_V 11108 +#define RISCV_VLSEG7E8_V 11109 +#define RISCV_VLSEG8E16FF_V 11110 +#define RISCV_VLSEG8E16_V 11111 +#define RISCV_VLSEG8E32FF_V 11112 +#define RISCV_VLSEG8E32_V 11113 +#define RISCV_VLSEG8E64FF_V 11114 +#define RISCV_VLSEG8E64_V 11115 +#define RISCV_VLSEG8E8FF_V 11116 +#define RISCV_VLSEG8E8_V 11117 +#define RISCV_VLSSEG2E16_V 11118 +#define RISCV_VLSSEG2E32_V 11119 +#define RISCV_VLSSEG2E64_V 11120 +#define RISCV_VLSSEG2E8_V 11121 +#define RISCV_VLSSEG3E16_V 11122 +#define RISCV_VLSSEG3E32_V 11123 +#define RISCV_VLSSEG3E64_V 11124 +#define RISCV_VLSSEG3E8_V 11125 +#define RISCV_VLSSEG4E16_V 11126 +#define RISCV_VLSSEG4E32_V 11127 +#define RISCV_VLSSEG4E64_V 11128 +#define RISCV_VLSSEG4E8_V 11129 +#define RISCV_VLSSEG5E16_V 11130 +#define RISCV_VLSSEG5E32_V 11131 +#define RISCV_VLSSEG5E64_V 11132 +#define RISCV_VLSSEG5E8_V 11133 +#define RISCV_VLSSEG6E16_V 11134 +#define RISCV_VLSSEG6E32_V 11135 +#define RISCV_VLSSEG6E64_V 11136 +#define RISCV_VLSSEG6E8_V 11137 +#define RISCV_VLSSEG7E16_V 11138 +#define RISCV_VLSSEG7E32_V 11139 +#define RISCV_VLSSEG7E64_V 11140 +#define RISCV_VLSSEG7E8_V 11141 +#define RISCV_VLSSEG8E16_V 11142 +#define RISCV_VLSSEG8E32_V 11143 +#define RISCV_VLSSEG8E64_V 11144 +#define RISCV_VLSSEG8E8_V 11145 +#define RISCV_VLUXEI16_V 11146 +#define RISCV_VLUXEI32_V 11147 +#define RISCV_VLUXEI64_V 11148 +#define RISCV_VLUXEI8_V 11149 +#define RISCV_VLUXSEG2EI16_V 11150 +#define RISCV_VLUXSEG2EI32_V 11151 +#define RISCV_VLUXSEG2EI64_V 11152 +#define RISCV_VLUXSEG2EI8_V 11153 +#define RISCV_VLUXSEG3EI16_V 11154 +#define RISCV_VLUXSEG3EI32_V 11155 +#define RISCV_VLUXSEG3EI64_V 11156 +#define RISCV_VLUXSEG3EI8_V 11157 +#define RISCV_VLUXSEG4EI16_V 11158 +#define RISCV_VLUXSEG4EI32_V 11159 +#define RISCV_VLUXSEG4EI64_V 11160 +#define RISCV_VLUXSEG4EI8_V 11161 +#define RISCV_VLUXSEG5EI16_V 11162 +#define RISCV_VLUXSEG5EI32_V 11163 +#define RISCV_VLUXSEG5EI64_V 11164 +#define RISCV_VLUXSEG5EI8_V 11165 +#define RISCV_VLUXSEG6EI16_V 11166 +#define RISCV_VLUXSEG6EI32_V 11167 +#define RISCV_VLUXSEG6EI64_V 11168 +#define RISCV_VLUXSEG6EI8_V 11169 +#define RISCV_VLUXSEG7EI16_V 11170 +#define RISCV_VLUXSEG7EI32_V 11171 +#define RISCV_VLUXSEG7EI64_V 11172 +#define RISCV_VLUXSEG7EI8_V 11173 +#define RISCV_VLUXSEG8EI16_V 11174 +#define RISCV_VLUXSEG8EI32_V 11175 +#define RISCV_VLUXSEG8EI64_V 11176 +#define RISCV_VLUXSEG8EI8_V 11177 +#define RISCV_VMACC_VV 11178 +#define RISCV_VMACC_VX 11179 +#define RISCV_VMADC_VI 11180 +#define RISCV_VMADC_VIM 11181 +#define RISCV_VMADC_VV 11182 +#define RISCV_VMADC_VVM 11183 +#define RISCV_VMADC_VX 11184 +#define RISCV_VMADC_VXM 11185 +#define RISCV_VMADD_VV 11186 +#define RISCV_VMADD_VX 11187 +#define RISCV_VMANDN_MM 11188 +#define RISCV_VMAND_MM 11189 +#define RISCV_VMAXU_VV 11190 +#define RISCV_VMAXU_VX 11191 +#define RISCV_VMAX_VV 11192 +#define RISCV_VMAX_VX 11193 +#define RISCV_VMERGE_VIM 11194 +#define RISCV_VMERGE_VVM 11195 +#define RISCV_VMERGE_VXM 11196 +#define RISCV_VMFEQ_VF 11197 +#define RISCV_VMFEQ_VV 11198 +#define RISCV_VMFGE_VF 11199 +#define RISCV_VMFGT_VF 11200 +#define RISCV_VMFLE_VF 11201 +#define RISCV_VMFLE_VV 11202 +#define RISCV_VMFLT_VF 11203 +#define RISCV_VMFLT_VV 11204 +#define RISCV_VMFNE_VF 11205 +#define RISCV_VMFNE_VV 11206 +#define RISCV_VMINU_VV 11207 +#define RISCV_VMINU_VX 11208 +#define RISCV_VMIN_VV 11209 +#define RISCV_VMIN_VX 11210 +#define RISCV_VMNAND_MM 11211 +#define RISCV_VMNOR_MM 11212 +#define RISCV_VMORN_MM 11213 +#define RISCV_VMOR_MM 11214 +#define RISCV_VMSBC_VV 11215 +#define RISCV_VMSBC_VVM 11216 +#define RISCV_VMSBC_VX 11217 +#define RISCV_VMSBC_VXM 11218 +#define RISCV_VMSBF_M 11219 +#define RISCV_VMSEQ_VI 11220 +#define RISCV_VMSEQ_VV 11221 +#define RISCV_VMSEQ_VX 11222 +#define RISCV_VMSGTU_VI 11223 +#define RISCV_VMSGTU_VX 11224 +#define RISCV_VMSGT_VI 11225 +#define RISCV_VMSGT_VX 11226 +#define RISCV_VMSIF_M 11227 +#define RISCV_VMSLEU_VI 11228 +#define RISCV_VMSLEU_VV 11229 +#define RISCV_VMSLEU_VX 11230 +#define RISCV_VMSLE_VI 11231 +#define RISCV_VMSLE_VV 11232 +#define RISCV_VMSLE_VX 11233 +#define RISCV_VMSLTU_VV 11234 +#define RISCV_VMSLTU_VX 11235 +#define RISCV_VMSLT_VV 11236 +#define RISCV_VMSLT_VX 11237 +#define RISCV_VMSNE_VI 11238 +#define RISCV_VMSNE_VV 11239 +#define RISCV_VMSNE_VX 11240 +#define RISCV_VMSOF_M 11241 +#define RISCV_VMULHSU_VV 11242 +#define RISCV_VMULHSU_VX 11243 +#define RISCV_VMULHU_VV 11244 +#define RISCV_VMULHU_VX 11245 +#define RISCV_VMULH_VV 11246 +#define RISCV_VMULH_VX 11247 +#define RISCV_VMUL_VV 11248 +#define RISCV_VMUL_VX 11249 +#define RISCV_VMV1R_V 11250 +#define RISCV_VMV2R_V 11251 +#define RISCV_VMV4R_V 11252 +#define RISCV_VMV8R_V 11253 +#define RISCV_VMV_S_X 11254 +#define RISCV_VMV_V_I 11255 +#define RISCV_VMV_V_V 11256 +#define RISCV_VMV_V_X 11257 +#define RISCV_VMV_X_S 11258 +#define RISCV_VMXNOR_MM 11259 +#define RISCV_VMXOR_MM 11260 +#define RISCV_VNCLIPU_WI 11261 +#define RISCV_VNCLIPU_WV 11262 +#define RISCV_VNCLIPU_WX 11263 +#define RISCV_VNCLIP_WI 11264 +#define RISCV_VNCLIP_WV 11265 +#define RISCV_VNCLIP_WX 11266 +#define RISCV_VNMSAC_VV 11267 +#define RISCV_VNMSAC_VX 11268 +#define RISCV_VNMSUB_VV 11269 +#define RISCV_VNMSUB_VX 11270 +#define RISCV_VNSRA_WI 11271 +#define RISCV_VNSRA_WV 11272 +#define RISCV_VNSRA_WX 11273 +#define RISCV_VNSRL_WI 11274 +#define RISCV_VNSRL_WV 11275 +#define RISCV_VNSRL_WX 11276 +#define RISCV_VOR_VI 11277 +#define RISCV_VOR_VV 11278 +#define RISCV_VOR_VX 11279 +#define RISCV_VREDAND_VS 11280 +#define RISCV_VREDMAXU_VS 11281 +#define RISCV_VREDMAX_VS 11282 +#define RISCV_VREDMINU_VS 11283 +#define RISCV_VREDMIN_VS 11284 +#define RISCV_VREDOR_VS 11285 +#define RISCV_VREDSUM_VS 11286 +#define RISCV_VREDXOR_VS 11287 +#define RISCV_VREMU_VV 11288 +#define RISCV_VREMU_VX 11289 +#define RISCV_VREM_VV 11290 +#define RISCV_VREM_VX 11291 +#define RISCV_VRGATHEREI16_VV 11292 +#define RISCV_VRGATHER_VI 11293 +#define RISCV_VRGATHER_VV 11294 +#define RISCV_VRGATHER_VX 11295 +#define RISCV_VRSUB_VI 11296 +#define RISCV_VRSUB_VX 11297 +#define RISCV_VS1R_V 11298 +#define RISCV_VS2R_V 11299 +#define RISCV_VS4R_V 11300 +#define RISCV_VS8R_V 11301 +#define RISCV_VSADDU_VI 11302 +#define RISCV_VSADDU_VV 11303 +#define RISCV_VSADDU_VX 11304 +#define RISCV_VSADD_VI 11305 +#define RISCV_VSADD_VV 11306 +#define RISCV_VSADD_VX 11307 +#define RISCV_VSBC_VVM 11308 +#define RISCV_VSBC_VXM 11309 +#define RISCV_VSE16_V 11310 +#define RISCV_VSE32_V 11311 +#define RISCV_VSE64_V 11312 +#define RISCV_VSE8_V 11313 +#define RISCV_VSETIVLI 11314 +#define RISCV_VSETVL 11315 +#define RISCV_VSETVLI 11316 +#define RISCV_VSEXT_VF2 11317 +#define RISCV_VSEXT_VF4 11318 +#define RISCV_VSEXT_VF8 11319 +#define RISCV_VSLIDE1DOWN_VX 11320 +#define RISCV_VSLIDE1UP_VX 11321 +#define RISCV_VSLIDEDOWN_VI 11322 +#define RISCV_VSLIDEDOWN_VX 11323 +#define RISCV_VSLIDEUP_VI 11324 +#define RISCV_VSLIDEUP_VX 11325 +#define RISCV_VSLL_VI 11326 +#define RISCV_VSLL_VV 11327 +#define RISCV_VSLL_VX 11328 +#define RISCV_VSMUL_VV 11329 +#define RISCV_VSMUL_VX 11330 +#define RISCV_VSM_V 11331 +#define RISCV_VSOXEI16_V 11332 +#define RISCV_VSOXEI32_V 11333 +#define RISCV_VSOXEI64_V 11334 +#define RISCV_VSOXEI8_V 11335 +#define RISCV_VSOXSEG2EI16_V 11336 +#define RISCV_VSOXSEG2EI32_V 11337 +#define RISCV_VSOXSEG2EI64_V 11338 +#define RISCV_VSOXSEG2EI8_V 11339 +#define RISCV_VSOXSEG3EI16_V 11340 +#define RISCV_VSOXSEG3EI32_V 11341 +#define RISCV_VSOXSEG3EI64_V 11342 +#define RISCV_VSOXSEG3EI8_V 11343 +#define RISCV_VSOXSEG4EI16_V 11344 +#define RISCV_VSOXSEG4EI32_V 11345 +#define RISCV_VSOXSEG4EI64_V 11346 +#define RISCV_VSOXSEG4EI8_V 11347 +#define RISCV_VSOXSEG5EI16_V 11348 +#define RISCV_VSOXSEG5EI32_V 11349 +#define RISCV_VSOXSEG5EI64_V 11350 +#define RISCV_VSOXSEG5EI8_V 11351 +#define RISCV_VSOXSEG6EI16_V 11352 +#define RISCV_VSOXSEG6EI32_V 11353 +#define RISCV_VSOXSEG6EI64_V 11354 +#define RISCV_VSOXSEG6EI8_V 11355 +#define RISCV_VSOXSEG7EI16_V 11356 +#define RISCV_VSOXSEG7EI32_V 11357 +#define RISCV_VSOXSEG7EI64_V 11358 +#define RISCV_VSOXSEG7EI8_V 11359 +#define RISCV_VSOXSEG8EI16_V 11360 +#define RISCV_VSOXSEG8EI32_V 11361 +#define RISCV_VSOXSEG8EI64_V 11362 +#define RISCV_VSOXSEG8EI8_V 11363 +#define RISCV_VSRA_VI 11364 +#define RISCV_VSRA_VV 11365 +#define RISCV_VSRA_VX 11366 +#define RISCV_VSRL_VI 11367 +#define RISCV_VSRL_VV 11368 +#define RISCV_VSRL_VX 11369 +#define RISCV_VSSE16_V 11370 +#define RISCV_VSSE32_V 11371 +#define RISCV_VSSE64_V 11372 +#define RISCV_VSSE8_V 11373 +#define RISCV_VSSEG2E16_V 11374 +#define RISCV_VSSEG2E32_V 11375 +#define RISCV_VSSEG2E64_V 11376 +#define RISCV_VSSEG2E8_V 11377 +#define RISCV_VSSEG3E16_V 11378 +#define RISCV_VSSEG3E32_V 11379 +#define RISCV_VSSEG3E64_V 11380 +#define RISCV_VSSEG3E8_V 11381 +#define RISCV_VSSEG4E16_V 11382 +#define RISCV_VSSEG4E32_V 11383 +#define RISCV_VSSEG4E64_V 11384 +#define RISCV_VSSEG4E8_V 11385 +#define RISCV_VSSEG5E16_V 11386 +#define RISCV_VSSEG5E32_V 11387 +#define RISCV_VSSEG5E64_V 11388 +#define RISCV_VSSEG5E8_V 11389 +#define RISCV_VSSEG6E16_V 11390 +#define RISCV_VSSEG6E32_V 11391 +#define RISCV_VSSEG6E64_V 11392 +#define RISCV_VSSEG6E8_V 11393 +#define RISCV_VSSEG7E16_V 11394 +#define RISCV_VSSEG7E32_V 11395 +#define RISCV_VSSEG7E64_V 11396 +#define RISCV_VSSEG7E8_V 11397 +#define RISCV_VSSEG8E16_V 11398 +#define RISCV_VSSEG8E32_V 11399 +#define RISCV_VSSEG8E64_V 11400 +#define RISCV_VSSEG8E8_V 11401 +#define RISCV_VSSRA_VI 11402 +#define RISCV_VSSRA_VV 11403 +#define RISCV_VSSRA_VX 11404 +#define RISCV_VSSRL_VI 11405 +#define RISCV_VSSRL_VV 11406 +#define RISCV_VSSRL_VX 11407 +#define RISCV_VSSSEG2E16_V 11408 +#define RISCV_VSSSEG2E32_V 11409 +#define RISCV_VSSSEG2E64_V 11410 +#define RISCV_VSSSEG2E8_V 11411 +#define RISCV_VSSSEG3E16_V 11412 +#define RISCV_VSSSEG3E32_V 11413 +#define RISCV_VSSSEG3E64_V 11414 +#define RISCV_VSSSEG3E8_V 11415 +#define RISCV_VSSSEG4E16_V 11416 +#define RISCV_VSSSEG4E32_V 11417 +#define RISCV_VSSSEG4E64_V 11418 +#define RISCV_VSSSEG4E8_V 11419 +#define RISCV_VSSSEG5E16_V 11420 +#define RISCV_VSSSEG5E32_V 11421 +#define RISCV_VSSSEG5E64_V 11422 +#define RISCV_VSSSEG5E8_V 11423 +#define RISCV_VSSSEG6E16_V 11424 +#define RISCV_VSSSEG6E32_V 11425 +#define RISCV_VSSSEG6E64_V 11426 +#define RISCV_VSSSEG6E8_V 11427 +#define RISCV_VSSSEG7E16_V 11428 +#define RISCV_VSSSEG7E32_V 11429 +#define RISCV_VSSSEG7E64_V 11430 +#define RISCV_VSSSEG7E8_V 11431 +#define RISCV_VSSSEG8E16_V 11432 +#define RISCV_VSSSEG8E32_V 11433 +#define RISCV_VSSSEG8E64_V 11434 +#define RISCV_VSSSEG8E8_V 11435 +#define RISCV_VSSUBU_VV 11436 +#define RISCV_VSSUBU_VX 11437 +#define RISCV_VSSUB_VV 11438 +#define RISCV_VSSUB_VX 11439 +#define RISCV_VSUB_VV 11440 +#define RISCV_VSUB_VX 11441 +#define RISCV_VSUXEI16_V 11442 +#define RISCV_VSUXEI32_V 11443 +#define RISCV_VSUXEI64_V 11444 +#define RISCV_VSUXEI8_V 11445 +#define RISCV_VSUXSEG2EI16_V 11446 +#define RISCV_VSUXSEG2EI32_V 11447 +#define RISCV_VSUXSEG2EI64_V 11448 +#define RISCV_VSUXSEG2EI8_V 11449 +#define RISCV_VSUXSEG3EI16_V 11450 +#define RISCV_VSUXSEG3EI32_V 11451 +#define RISCV_VSUXSEG3EI64_V 11452 +#define RISCV_VSUXSEG3EI8_V 11453 +#define RISCV_VSUXSEG4EI16_V 11454 +#define RISCV_VSUXSEG4EI32_V 11455 +#define RISCV_VSUXSEG4EI64_V 11456 +#define RISCV_VSUXSEG4EI8_V 11457 +#define RISCV_VSUXSEG5EI16_V 11458 +#define RISCV_VSUXSEG5EI32_V 11459 +#define RISCV_VSUXSEG5EI64_V 11460 +#define RISCV_VSUXSEG5EI8_V 11461 +#define RISCV_VSUXSEG6EI16_V 11462 +#define RISCV_VSUXSEG6EI32_V 11463 +#define RISCV_VSUXSEG6EI64_V 11464 +#define RISCV_VSUXSEG6EI8_V 11465 +#define RISCV_VSUXSEG7EI16_V 11466 +#define RISCV_VSUXSEG7EI32_V 11467 +#define RISCV_VSUXSEG7EI64_V 11468 +#define RISCV_VSUXSEG7EI8_V 11469 +#define RISCV_VSUXSEG8EI16_V 11470 +#define RISCV_VSUXSEG8EI32_V 11471 +#define RISCV_VSUXSEG8EI64_V 11472 +#define RISCV_VSUXSEG8EI8_V 11473 +#define RISCV_VWADDU_VV 11474 +#define RISCV_VWADDU_VX 11475 +#define RISCV_VWADDU_WV 11476 +#define RISCV_VWADDU_WX 11477 +#define RISCV_VWADD_VV 11478 +#define RISCV_VWADD_VX 11479 +#define RISCV_VWADD_WV 11480 +#define RISCV_VWADD_WX 11481 +#define RISCV_VWMACCSU_VV 11482 +#define RISCV_VWMACCSU_VX 11483 +#define RISCV_VWMACCUS_VX 11484 +#define RISCV_VWMACCU_VV 11485 +#define RISCV_VWMACCU_VX 11486 +#define RISCV_VWMACC_VV 11487 +#define RISCV_VWMACC_VX 11488 +#define RISCV_VWMULSU_VV 11489 +#define RISCV_VWMULSU_VX 11490 +#define RISCV_VWMULU_VV 11491 +#define RISCV_VWMULU_VX 11492 +#define RISCV_VWMUL_VV 11493 +#define RISCV_VWMUL_VX 11494 +#define RISCV_VWREDSUMU_VS 11495 +#define RISCV_VWREDSUM_VS 11496 +#define RISCV_VWSUBU_VV 11497 +#define RISCV_VWSUBU_VX 11498 +#define RISCV_VWSUBU_WV 11499 +#define RISCV_VWSUBU_WX 11500 +#define RISCV_VWSUB_VV 11501 +#define RISCV_VWSUB_VX 11502 +#define RISCV_VWSUB_WV 11503 +#define RISCV_VWSUB_WX 11504 +#define RISCV_VXOR_VI 11505 +#define RISCV_VXOR_VV 11506 +#define RISCV_VXOR_VX 11507 +#define RISCV_VZEXT_VF2 11508 +#define RISCV_VZEXT_VF4 11509 +#define RISCV_VZEXT_VF8 11510 +#define RISCV_WFI 11511 +#define RISCV_XNOR 11512 +#define RISCV_XOR 11513 +#define RISCV_XORI 11514 +#define RISCV_XPERMB 11515 +#define RISCV_XPERMH 11516 +#define RISCV_XPERMN 11517 +#define RISCV_XPERMW 11518 +#define RISCV_ZEXTH_RV32 11519 +#define RISCV_ZEXTH_RV64 11520 +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_REGINFO_EXTRA +#undef GET_REGINFO_EXTRA + + // Register alternate name indices + + enum { + RISCV_ABIRegAltName, // 0 + RISCV_NoRegAltName, // 1 + RISCV_NUM_TARGET_REG_ALT_NAMES = 2 + }; + +// Subregister indices + +enum { + NoSubRegister, + RISCV_sub_16, // 1 + RISCV_sub_32, // 2 + RISCV_sub_vrm1_0, // 3 + RISCV_sub_vrm1_1, // 4 + RISCV_sub_vrm1_2, // 5 + RISCV_sub_vrm1_3, // 6 + RISCV_sub_vrm1_4, // 7 + RISCV_sub_vrm1_5, // 8 + RISCV_sub_vrm1_6, // 9 + RISCV_sub_vrm1_7, // 10 + RISCV_sub_vrm2_0, // 11 + RISCV_sub_vrm2_1, // 12 + RISCV_sub_vrm2_2, // 13 + RISCV_sub_vrm2_3, // 14 + RISCV_sub_vrm4_0, // 15 + RISCV_sub_vrm4_1, // 16 + RISCV_sub_vrm1_0_sub_vrm1_1, // 17 + RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2, // 18 + RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3, // 19 + RISCV_sub_vrm1_1_sub_vrm1_2, // 20 + RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3, // 21 + RISCV_sub_vrm1_2_sub_vrm1_3, // 22 + RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, // 23 + RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 24 + RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 25 + RISCV_sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 26 + RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, // 27 + RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 28 + RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 29 + RISCV_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 30 + RISCV_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, // 31 + RISCV_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 32 + RISCV_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 33 + RISCV_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 34 + RISCV_sub_vrm1_3_sub_vrm1_4, // 35 + RISCV_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 36 + RISCV_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 37 + RISCV_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 38 + RISCV_sub_vrm1_4_sub_vrm1_5, // 39 + RISCV_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 40 + RISCV_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 41 + RISCV_sub_vrm1_5_sub_vrm1_6, // 42 + RISCV_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 43 + RISCV_sub_vrm1_6_sub_vrm1_7, // 44 + RISCV_sub_vrm2_0_sub_vrm2_1, // 45 + RISCV_sub_vrm2_0_sub_vrm2_1_sub_vrm2_2, // 46 + RISCV_sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3, // 47 + RISCV_sub_vrm2_1_sub_vrm2_2, // 48 + RISCV_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3, // 49 + RISCV_sub_vrm2_2_sub_vrm2_3, // 50 + RISCV_NUM_TARGET_SUBREGS +}; +#endif // GET_REGINFO_EXTRA + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg RISCVRegDiffLists[] = { + /* 0 */ 7, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 9 */ 15, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 18 */ 23, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 27 */ 31, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 36 */ 64579, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 45 */ 64901, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 54 */ 65128, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 63 */ 7, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 71 */ 65154, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + /* 79 */ 7, + 1, + 1, + 1, + 1, + 1, + 0, + /* 86 */ 64987, + 1, + 1, + 1, + 1, + 1, + 0, + /* 93 */ 65181, + 1, + 1, + 1, + 1, + 1, + 0, + /* 100 */ 7, + 1, + 1, + 1, + 1, + 0, + /* 106 */ 65209, + 1, + 1, + 1, + 1, + 0, + /* 112 */ 7, + 1, + 1, + 1, + 0, + /* 117 */ 11, + 1, + 1, + 1, + 0, + /* 122 */ 15, + 1, + 1, + 1, + 0, + /* 127 */ 19, + 1, + 1, + 1, + 0, + /* 132 */ 23, + 1, + 1, + 1, + 0, + /* 137 */ 27, + 1, + 1, + 1, + 0, + /* 142 */ 31, + 1, + 1, + 1, + 0, + /* 147 */ 35, + 1, + 1, + 1, + 0, + /* 152 */ 65091, + 1, + 1, + 1, + 0, + /* 157 */ 65251, + 1, + 1, + 1, + 0, + /* 162 */ 7, + 1, + 1, + 0, + /* 166 */ 65295, + 1, + 1, + 0, + /* 170 */ 7, + 1, + 0, + /* 173 */ 65437, + 65378, + 1, + 158, + 65379, + 1, + 158, + 65379, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 14, + 1, + 0, + /* 200 */ 65435, + 65379, + 1, + 159, + 65378, + 1, + 158, + 65379, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 15, + 1, + 0, + /* 227 */ 65435, + 65378, + 1, + 158, + 65379, + 1, + 159, + 65378, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 16, + 1, + 0, + /* 254 */ 65434, + 65378, + 1, + 159, + 65378, + 1, + 158, + 65379, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 17, + 1, + 0, + /* 281 */ 65434, + 65377, + 1, + 159, + 65378, + 1, + 159, + 65378, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 18, + 1, + 0, + /* 308 */ 65432, + 65378, + 1, + 160, + 65377, + 1, + 159, + 65378, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 19, + 1, + 0, + /* 335 */ 65432, + 65377, + 1, + 159, + 65378, + 1, + 160, + 65377, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 20, + 1, + 0, + /* 362 */ 65431, + 65377, + 1, + 160, + 65377, + 1, + 159, + 65378, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 21, + 1, + 0, + /* 389 */ 65431, + 65376, + 1, + 160, + 65377, + 1, + 160, + 65377, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 22, + 1, + 0, + /* 416 */ 65429, + 65377, + 1, + 161, + 65376, + 1, + 160, + 65377, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 23, + 1, + 0, + /* 443 */ 65429, + 65376, + 1, + 160, + 65377, + 1, + 161, + 65376, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 24, + 1, + 0, + /* 470 */ 65428, + 65376, + 1, + 161, + 65376, + 1, + 160, + 65377, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 25, + 1, + 0, + /* 497 */ 65428, + 65375, + 1, + 161, + 65376, + 1, + 161, + 65376, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 26, + 1, + 0, + /* 524 */ 37, + 1, + 0, + /* 527 */ 1, + 55, + 1, + 0, + /* 531 */ 1, + 60, + 1, + 0, + /* 535 */ 65533, + 61, + 1, + 0, + /* 539 */ 1, + 65, + 1, + 0, + /* 543 */ 65533, + 66, + 1, + 0, + /* 547 */ 65296, + 1, + 1, + 185, + 1, + 0, + /* 553 */ 65185, + 1, + 0, + /* 556 */ 65189, + 1, + 0, + /* 559 */ 65191, + 1, + 0, + /* 562 */ 65195, + 1, + 0, + /* 565 */ 65197, + 1, + 0, + /* 568 */ 65201, + 1, + 0, + /* 571 */ 65203, + 1, + 0, + /* 574 */ 65318, + 1, + 0, + /* 577 */ 65348, + 1, + 0, + /* 580 */ 65349, + 1, + 0, + /* 583 */ 65535, + 65376, + 1, + 162, + 65375, + 1, + 0, + /* 590 */ 65535, + 65535, + 65376, + 1, + 162, + 65375, + 1, + 162, + 65535, + 65376, + 1, + 161, + 65376, + 1, + 0, + /* 605 */ 65535, + 65377, + 1, + 161, + 65376, + 1, + 0, + /* 612 */ 65535, + 65535, + 65377, + 1, + 161, + 65376, + 1, + 161, + 65535, + 65377, + 1, + 160, + 65377, + 1, + 0, + /* 627 */ 65535, + 65378, + 1, + 160, + 65377, + 1, + 0, + /* 634 */ 65535, + 65535, + 65378, + 1, + 160, + 65377, + 1, + 160, + 65535, + 65378, + 1, + 159, + 65378, + 1, + 0, + /* 649 */ 65535, + 65379, + 1, + 159, + 65378, + 1, + 0, + /* 656 */ 65535, + 65535, + 65379, + 1, + 159, + 65378, + 1, + 159, + 65535, + 65379, + 1, + 158, + 65379, + 1, + 0, + /* 671 */ 160, + 65534, + 1, + 27, + 1, + 51, + 1, + 43, + 65466, + 28, + 44, + 65465, + 68, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65398, + 42, + 65455, + 59, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65395, + 1, + 42, + 65454, + 126, + 26, + 1, + 25, + 65439, + 75, + 26, + 65437, + 92, + 2, + 2, + 2, + 0, + /* 721 */ 159, + 65535, + 65533, + 31, + 1, + 51, + 43, + 65468, + 26, + 1, + 43, + 65467, + 68, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65397, + 1, + 42, + 65455, + 95, + 27, + 26, + 50, + 65375, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 47, + 26, + 1, + 25, + 65439, + 92, + 2, + 2, + 2, + 0, + /* 771 */ 159, + 1, + 1, + 25, + 1, + 51, + 1, + 43, + 65467, + 27, + 44, + 65466, + 67, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65397, + 1, + 42, + 65455, + 100, + 28, + 27, + 26, + 65395, + 43, + 65454, + 122, + 26, + 1, + 25, + 65441, + 47, + 26, + 1, + 25, + 65439, + 92, + 2, + 2, + 2, + 0, + /* 821 */ 52, + 1, + 43, + 65467, + 68, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65397, + 1, + 42, + 65455, + 123, + 26, + 1, + 25, + 65441, + 47, + 26, + 1, + 25, + 65439, + 92, + 2, + 2, + 2, + 0, + /* 856 */ 159, + 65535, + 65533, + 31, + 1, + 51, + 1, + 43, + 65464, + 30, + 44, + 65463, + 70, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65396, + 42, + 65454, + 62, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65393, + 1, + 42, + 65453, + 129, + 26, + 1, + 25, + 65437, + 77, + 26, + 65435, + 94, + 2, + 2, + 2, + 0, + /* 906 */ 159, + 1, + 65533, + 29, + 1, + 51, + 1, + 43, + 65465, + 29, + 44, + 65464, + 69, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65395, + 1, + 42, + 65454, + 103, + 28, + 27, + 26, + 65393, + 43, + 65453, + 125, + 26, + 1, + 25, + 65439, + 49, + 26, + 1, + 25, + 65437, + 94, + 2, + 2, + 2, + 0, + /* 956 */ 159, + 65534, + 1, + 28, + 1, + 51, + 43, + 65466, + 28, + 1, + 43, + 65465, + 110, + 27, + 26, + 25, + 65398, + 42, + 65455, + 59, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65395, + 1, + 42, + 65454, + 126, + 26, + 1, + 25, + 65439, + 49, + 26, + 1, + 25, + 65437, + 94, + 2, + 2, + 2, + 0, + /* 1006 */ 52, + 1, + 43, + 65465, + 70, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65395, + 1, + 42, + 65454, + 126, + 26, + 1, + 25, + 65439, + 49, + 26, + 1, + 25, + 65437, + 94, + 2, + 2, + 2, + 0, + /* 1041 */ 158, + 1, + 1, + 26, + 1, + 51, + 43, + 65467, + 27, + 1, + 43, + 65466, + 109, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65397, + 1, + 42, + 65455, + 59, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65395, + 43, + 65454, + 149, + 25, + 65441, + 47, + 26, + 1, + 25, + 65439, + 94, + 2, + 2, + 2, + 0, + /* 1091 */ 52, + 1, + 43, + 65466, + 69, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65398, + 42, + 65455, + 59, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65395, + 43, + 65454, + 126, + 26, + 1, + 25, + 65439, + 94, + 2, + 2, + 2, + 0, + /* 1127 */ 159, + 65534, + 1, + 28, + 1, + 51, + 1, + 43, + 65462, + 32, + 44, + 65461, + 72, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65394, + 42, + 65453, + 65, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65391, + 1, + 42, + 65452, + 132, + 26, + 1, + 25, + 65435, + 79, + 26, + 65433, + 96, + 2, + 2, + 2, + 0, + /* 1177 */ 158, + 1, + 1, + 26, + 1, + 51, + 1, + 43, + 65463, + 31, + 44, + 65462, + 71, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65393, + 1, + 42, + 65453, + 106, + 28, + 27, + 26, + 65391, + 43, + 65452, + 128, + 26, + 1, + 25, + 65437, + 51, + 26, + 1, + 25, + 65435, + 96, + 2, + 2, + 2, + 0, + /* 1227 */ 158, + 65535, + 65533, + 32, + 1, + 51, + 43, + 65464, + 30, + 1, + 43, + 65463, + 112, + 27, + 26, + 25, + 65396, + 42, + 65454, + 62, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65393, + 1, + 42, + 65453, + 129, + 26, + 1, + 25, + 65437, + 51, + 26, + 1, + 25, + 65435, + 96, + 2, + 2, + 2, + 0, + /* 1277 */ 52, + 1, + 43, + 65463, + 72, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65393, + 1, + 42, + 65453, + 129, + 26, + 1, + 25, + 65437, + 51, + 26, + 1, + 25, + 65435, + 96, + 2, + 2, + 2, + 0, + /* 1312 */ 158, + 1, + 65533, + 30, + 1, + 51, + 43, + 65465, + 29, + 1, + 43, + 65464, + 111, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65395, + 1, + 42, + 65454, + 62, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65393, + 43, + 65453, + 152, + 25, + 65439, + 49, + 26, + 1, + 25, + 65437, + 96, + 2, + 2, + 2, + 0, + /* 1362 */ 52, + 1, + 43, + 65464, + 71, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65396, + 42, + 65454, + 62, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65393, + 43, + 65453, + 129, + 26, + 1, + 25, + 65437, + 96, + 2, + 2, + 2, + 0, + /* 1398 */ 158, + 65535, + 65533, + 32, + 1, + 51, + 1, + 43, + 65460, + 34, + 44, + 65459, + 74, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65392, + 42, + 65452, + 68, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65389, + 1, + 42, + 65451, + 135, + 26, + 1, + 25, + 65433, + 81, + 26, + 65431, + 98, + 2, + 2, + 2, + 0, + /* 1448 */ 158, + 1, + 65533, + 30, + 1, + 51, + 1, + 43, + 65461, + 33, + 44, + 65460, + 73, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65391, + 1, + 42, + 65452, + 109, + 28, + 27, + 26, + 65389, + 43, + 65451, + 131, + 26, + 1, + 25, + 65435, + 53, + 26, + 1, + 25, + 65433, + 98, + 2, + 2, + 2, + 0, + /* 1498 */ 158, + 65534, + 1, + 29, + 1, + 51, + 43, + 65462, + 32, + 1, + 43, + 65461, + 114, + 27, + 26, + 25, + 65394, + 42, + 65453, + 65, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65391, + 1, + 42, + 65452, + 132, + 26, + 1, + 25, + 65435, + 53, + 26, + 1, + 25, + 65433, + 98, + 2, + 2, + 2, + 0, + /* 1548 */ 52, + 1, + 43, + 65461, + 74, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65391, + 1, + 42, + 65452, + 132, + 26, + 1, + 25, + 65435, + 53, + 26, + 1, + 25, + 65433, + 98, + 2, + 2, + 2, + 0, + /* 1583 */ 157, + 1, + 1, + 27, + 1, + 51, + 43, + 65463, + 31, + 1, + 43, + 65462, + 113, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65393, + 1, + 42, + 65453, + 65, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65391, + 43, + 65452, + 155, + 25, + 65437, + 51, + 26, + 1, + 25, + 65435, + 98, + 2, + 2, + 2, + 0, + /* 1633 */ 52, + 1, + 43, + 65462, + 73, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65394, + 42, + 65453, + 65, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65391, + 43, + 65452, + 132, + 26, + 1, + 25, + 65435, + 98, + 2, + 2, + 2, + 0, + /* 1669 */ 157, + 1, + 1, + 27, + 1, + 51, + 1, + 43, + 65459, + 35, + 44, + 65458, + 75, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65389, + 1, + 42, + 65451, + 112, + 28, + 27, + 26, + 65387, + 43, + 65450, + 134, + 26, + 1, + 25, + 65433, + 55, + 26, + 1, + 25, + 65431, + 100, + 2, + 2, + 2, + 0, + /* 1719 */ 157, + 65535, + 65533, + 33, + 1, + 51, + 43, + 65460, + 34, + 1, + 43, + 65459, + 116, + 27, + 26, + 25, + 65392, + 42, + 65452, + 68, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65389, + 1, + 42, + 65451, + 135, + 26, + 1, + 25, + 65433, + 55, + 26, + 1, + 25, + 65431, + 100, + 2, + 2, + 2, + 0, + /* 1769 */ 52, + 1, + 43, + 65459, + 76, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65389, + 1, + 42, + 65451, + 135, + 26, + 1, + 25, + 65433, + 55, + 26, + 1, + 25, + 65431, + 100, + 2, + 2, + 2, + 0, + /* 1804 */ 157, + 1, + 65533, + 31, + 1, + 51, + 43, + 65461, + 33, + 1, + 43, + 65460, + 115, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65391, + 1, + 42, + 65452, + 68, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65389, + 43, + 65451, + 158, + 25, + 65435, + 53, + 26, + 1, + 25, + 65433, + 100, + 2, + 2, + 2, + 0, + /* 1854 */ 52, + 1, + 43, + 65460, + 75, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65392, + 42, + 65452, + 68, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65389, + 43, + 65451, + 135, + 26, + 1, + 25, + 65433, + 100, + 2, + 2, + 2, + 0, + /* 1890 */ 52, + 43, + 65468, + 26, + 44, + 65467, + 68, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65397, + 1, + 42, + 65455, + 95, + 27, + 26, + 50, + 65375, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 73, + 26, + 65439, + 92, + 2, + 2, + 0, + /* 1929 */ 160, + 65535, + 65533, + 30, + 1, + 51, + 1, + 43, + 65468, + 26, + 44, + 65467, + 68, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65397, + 1, + 42, + 65455, + 53, + 41, + 27, + 52, + 65458, + 27, + 26, + 50, + 65375, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 73, + 26, + 65439, + 92, + 2, + 2, + 0, + /* 1978 */ 44, + 65467, + 68, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65397, + 1, + 42, + 65455, + 123, + 26, + 1, + 25, + 65441, + 73, + 26, + 65439, + 92, + 2, + 2, + 0, + /* 2006 */ 52, + 43, + 65466, + 28, + 44, + 65465, + 110, + 27, + 26, + 25, + 65398, + 42, + 65455, + 59, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65395, + 1, + 42, + 65454, + 126, + 26, + 1, + 25, + 65439, + 75, + 26, + 65437, + 94, + 2, + 2, + 0, + /* 2045 */ 44, + 65465, + 70, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65395, + 1, + 42, + 65454, + 126, + 26, + 1, + 25, + 65439, + 75, + 26, + 65437, + 94, + 2, + 2, + 0, + /* 2073 */ 52, + 43, + 65467, + 27, + 44, + 65466, + 109, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65397, + 1, + 42, + 65455, + 100, + 28, + 27, + 26, + 65395, + 43, + 65454, + 149, + 25, + 65441, + 47, + 26, + 1, + 25, + 65439, + 94, + 2, + 2, + 0, + /* 2112 */ 43, + 65467, + 110, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65397, + 1, + 42, + 65455, + 150, + 25, + 65441, + 47, + 26, + 1, + 25, + 65439, + 94, + 2, + 2, + 0, + /* 2140 */ 44, + 65466, + 69, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65398, + 42, + 65455, + 100, + 28, + 27, + 26, + 65395, + 43, + 65454, + 126, + 26, + 1, + 25, + 65439, + 94, + 2, + 2, + 0, + /* 2169 */ 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65398, + 42, + 65455, + 127, + 26, + 1, + 25, + 65439, + 94, + 2, + 2, + 0, + /* 2188 */ 43, + 65468, + 69, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65397, + 43, + 65455, + 95, + 27, + 26, + 50, + 65375, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 2, + 0, + /* 2217 */ 52, + 1, + 43, + 65468, + 69, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65397, + 43, + 65455, + 53, + 41, + 27, + 52, + 65458, + 27, + 26, + 50, + 65375, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 2, + 0, + /* 2252 */ 159, + 1, + 65533, + 29, + 1, + 51, + 43, + 65469, + 25, + 1, + 43, + 65468, + 69, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65397, + 43, + 65455, + 93, + 54, + 65442, + 41, + 27, + 52, + 65458, + 27, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 2, + 0, + /* 2298 */ 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65397, + 43, + 65455, + 123, + 26, + 1, + 25, + 65441, + 94, + 2, + 2, + 0, + /* 2317 */ 52, + 43, + 65464, + 30, + 44, + 65463, + 112, + 27, + 26, + 25, + 65396, + 42, + 65454, + 62, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65393, + 1, + 42, + 65453, + 129, + 26, + 1, + 25, + 65437, + 77, + 26, + 65435, + 96, + 2, + 2, + 0, + /* 2356 */ 44, + 65463, + 72, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65393, + 1, + 42, + 65453, + 129, + 26, + 1, + 25, + 65437, + 77, + 26, + 65435, + 96, + 2, + 2, + 0, + /* 2384 */ 52, + 43, + 65465, + 29, + 44, + 65464, + 111, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65395, + 1, + 42, + 65454, + 103, + 28, + 27, + 26, + 65393, + 43, + 65453, + 152, + 25, + 65439, + 49, + 26, + 1, + 25, + 65437, + 96, + 2, + 2, + 0, + /* 2423 */ 43, + 65465, + 112, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65395, + 1, + 42, + 65454, + 153, + 25, + 65439, + 49, + 26, + 1, + 25, + 65437, + 96, + 2, + 2, + 0, + /* 2451 */ 44, + 65464, + 71, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65396, + 42, + 65454, + 103, + 28, + 27, + 26, + 65393, + 43, + 65453, + 129, + 26, + 1, + 25, + 65437, + 96, + 2, + 2, + 0, + /* 2480 */ 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65396, + 42, + 65454, + 130, + 26, + 1, + 25, + 65437, + 96, + 2, + 2, + 0, + /* 2499 */ 43, + 65466, + 111, + 27, + 26, + 25, + 65398, + 42, + 65455, + 59, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65395, + 43, + 65454, + 126, + 26, + 1, + 25, + 65439, + 96, + 2, + 2, + 0, + /* 2528 */ 52, + 43, + 65462, + 32, + 44, + 65461, + 114, + 27, + 26, + 25, + 65394, + 42, + 65453, + 65, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65391, + 1, + 42, + 65452, + 132, + 26, + 1, + 25, + 65435, + 79, + 26, + 65433, + 98, + 2, + 2, + 0, + /* 2567 */ 44, + 65461, + 74, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65391, + 1, + 42, + 65452, + 132, + 26, + 1, + 25, + 65435, + 79, + 26, + 65433, + 98, + 2, + 2, + 0, + /* 2595 */ 52, + 43, + 65463, + 31, + 44, + 65462, + 113, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65393, + 1, + 42, + 65453, + 106, + 28, + 27, + 26, + 65391, + 43, + 65452, + 155, + 25, + 65437, + 51, + 26, + 1, + 25, + 65435, + 98, + 2, + 2, + 0, + /* 2634 */ 43, + 65463, + 114, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65393, + 1, + 42, + 65453, + 156, + 25, + 65437, + 51, + 26, + 1, + 25, + 65435, + 98, + 2, + 2, + 0, + /* 2662 */ 44, + 65462, + 73, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65394, + 42, + 65453, + 106, + 28, + 27, + 26, + 65391, + 43, + 65452, + 132, + 26, + 1, + 25, + 65435, + 98, + 2, + 2, + 0, + /* 2691 */ 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65394, + 42, + 65453, + 133, + 26, + 1, + 25, + 65435, + 98, + 2, + 2, + 0, + /* 2710 */ 43, + 65464, + 113, + 27, + 26, + 25, + 65396, + 42, + 65454, + 62, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65393, + 43, + 65453, + 129, + 26, + 1, + 25, + 65437, + 98, + 2, + 2, + 0, + /* 2739 */ 52, + 43, + 65460, + 34, + 44, + 65459, + 116, + 27, + 26, + 25, + 65392, + 42, + 65452, + 68, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65389, + 1, + 42, + 65451, + 135, + 26, + 1, + 25, + 65433, + 81, + 26, + 65431, + 100, + 2, + 2, + 0, + /* 2778 */ 44, + 65459, + 76, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65389, + 1, + 42, + 65451, + 135, + 26, + 1, + 25, + 65433, + 81, + 26, + 65431, + 100, + 2, + 2, + 0, + /* 2806 */ 52, + 43, + 65461, + 33, + 44, + 65460, + 115, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65391, + 1, + 42, + 65452, + 109, + 28, + 27, + 26, + 65389, + 43, + 65451, + 158, + 25, + 65435, + 53, + 26, + 1, + 25, + 65433, + 100, + 2, + 2, + 0, + /* 2845 */ 43, + 65461, + 116, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65391, + 1, + 42, + 65452, + 159, + 25, + 65435, + 53, + 26, + 1, + 25, + 65433, + 100, + 2, + 2, + 0, + /* 2873 */ 44, + 65460, + 75, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65392, + 42, + 65452, + 109, + 28, + 27, + 26, + 65389, + 43, + 65451, + 135, + 26, + 1, + 25, + 65433, + 100, + 2, + 2, + 0, + /* 2902 */ 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65392, + 42, + 65452, + 136, + 26, + 1, + 25, + 65433, + 100, + 2, + 2, + 0, + /* 2921 */ 43, + 65462, + 115, + 27, + 26, + 25, + 65394, + 42, + 65453, + 65, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65391, + 43, + 65452, + 132, + 26, + 1, + 25, + 65435, + 100, + 2, + 2, + 0, + /* 2950 */ 156, + 1, + 1, + 28, + 1, + 51, + 43, + 65459, + 35, + 1, + 43, + 65458, + 117, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65389, + 1, + 42, + 65451, + 71, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65387, + 43, + 65450, + 161, + 25, + 65433, + 55, + 26, + 1, + 25, + 65431, + 102, + 2, + 2, + 0, + /* 2999 */ 52, + 43, + 65459, + 35, + 44, + 65458, + 117, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65389, + 1, + 42, + 65451, + 112, + 28, + 27, + 26, + 65387, + 43, + 65450, + 161, + 25, + 65433, + 55, + 26, + 1, + 25, + 65431, + 102, + 2, + 2, + 0, + /* 3038 */ 43, + 65459, + 118, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65389, + 1, + 42, + 65451, + 162, + 25, + 65433, + 55, + 26, + 1, + 25, + 65431, + 102, + 2, + 2, + 0, + /* 3066 */ 158, + 65534, + 1, + 29, + 1, + 51, + 1, + 43, + 65458, + 36, + 44, + 65457, + 76, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65390, + 42, + 65451, + 71, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65387, + 1, + 42, + 65450, + 138, + 26, + 1, + 25, + 65431, + 102, + 2, + 2, + 0, + /* 3112 */ 52, + 1, + 43, + 65458, + 77, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65390, + 42, + 65451, + 71, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65387, + 43, + 65450, + 138, + 26, + 1, + 25, + 65431, + 102, + 2, + 2, + 0, + /* 3147 */ 44, + 65458, + 77, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65390, + 42, + 65451, + 112, + 28, + 27, + 26, + 65387, + 43, + 65450, + 138, + 26, + 1, + 25, + 65431, + 102, + 2, + 2, + 0, + /* 3176 */ 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65390, + 42, + 65451, + 139, + 26, + 1, + 25, + 65431, + 102, + 2, + 2, + 0, + /* 3195 */ 43, + 65460, + 117, + 27, + 26, + 25, + 65392, + 42, + 65452, + 68, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65389, + 43, + 65451, + 135, + 26, + 1, + 25, + 65433, + 102, + 2, + 2, + 0, + /* 3224 */ 65535, + 65533, + 58, + 1, + 51, + 1, + 42, + 65455, + 37, + 55, + 65450, + 74, + 2, + 0, + /* 3238 */ 1, + 1, + 52, + 1, + 50, + 1, + 42, + 65455, + 40, + 43, + 65454, + 79, + 2, + 0, + /* 3252 */ 1, + 65533, + 54, + 1, + 50, + 1, + 42, + 65454, + 41, + 43, + 65453, + 80, + 2, + 0, + /* 3266 */ 51, + 1, + 42, + 65455, + 80, + 2, + 0, + /* 3273 */ 1, + 1, + 49, + 1, + 50, + 1, + 42, + 65453, + 42, + 43, + 65452, + 81, + 2, + 0, + /* 3287 */ 65534, + 1, + 53, + 1, + 50, + 42, + 65455, + 40, + 1, + 42, + 65454, + 81, + 2, + 0, + /* 3301 */ 51, + 1, + 42, + 65454, + 81, + 2, + 0, + /* 3308 */ 1, + 65533, + 51, + 1, + 50, + 1, + 42, + 65452, + 43, + 43, + 65451, + 82, + 2, + 0, + /* 3322 */ 65535, + 65533, + 55, + 1, + 50, + 42, + 65454, + 41, + 1, + 42, + 65453, + 82, + 2, + 0, + /* 3336 */ 51, + 1, + 42, + 65453, + 82, + 2, + 0, + /* 3343 */ 1, + 1, + 46, + 1, + 50, + 1, + 42, + 65451, + 44, + 43, + 65450, + 83, + 2, + 0, + /* 3357 */ 65534, + 1, + 50, + 1, + 50, + 42, + 65453, + 42, + 1, + 42, + 65452, + 83, + 2, + 0, + /* 3371 */ 51, + 1, + 42, + 65452, + 83, + 2, + 0, + /* 3378 */ 65535, + 65533, + 52, + 1, + 50, + 42, + 65452, + 43, + 1, + 42, + 65451, + 84, + 2, + 0, + /* 3392 */ 51, + 1, + 42, + 65451, + 84, + 2, + 0, + /* 3399 */ 65467, + 110, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65397, + 1, + 42, + 65455, + 150, + 25, + 65441, + 73, + 26, + 65439, + 94, + 2, + 0, + /* 3421 */ 27, + 26, + 65511, + 26, + 25, + 65398, + 42, + 65455, + 153, + 26, + 65439, + 94, + 2, + 0, + /* 3435 */ 65468, + 110, + 28, + 27, + 26, + 65397, + 43, + 65455, + 95, + 27, + 26, + 50, + 65375, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 0, + /* 3458 */ 44, + 65468, + 110, + 28, + 27, + 26, + 65397, + 43, + 65455, + 53, + 41, + 27, + 52, + 65458, + 27, + 26, + 50, + 65375, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 0, + /* 3486 */ 52, + 43, + 65469, + 25, + 44, + 65468, + 110, + 28, + 27, + 26, + 65397, + 43, + 65455, + 93, + 54, + 65442, + 41, + 27, + 52, + 65458, + 27, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 0, + /* 3521 */ 43, + 65469, + 108, + 54, + 65442, + 41, + 27, + 52, + 65458, + 27, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 0, + /* 3545 */ 160, + 1, + 65533, + 28, + 1, + 51, + 1, + 43, + 65469, + 25, + 44, + 65468, + 110, + 28, + 27, + 26, + 65397, + 43, + 65455, + 51, + 69, + 65509, + 54, + 65442, + 41, + 27, + 52, + 65458, + 27, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 0, + /* 3588 */ 160, + 65534, + 1, + 27, + 1, + 52, + 1, + 43, + 65469, + 22, + 72, + 65456, + 52, + 69, + 65509, + 54, + 65442, + 41, + 27, + 52, + 65458, + 27, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 0, + /* 3624 */ 52, + 1, + 43, + 65469, + 66, + 69, + 65509, + 54, + 65442, + 41, + 27, + 52, + 65458, + 27, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 117, + 26, + 1, + 25, + 65441, + 94, + 2, + 0, + /* 3652 */ 28, + 27, + 26, + 65397, + 43, + 65455, + 123, + 26, + 1, + 25, + 65441, + 94, + 2, + 0, + /* 3666 */ 65465, + 112, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65395, + 1, + 42, + 65454, + 153, + 25, + 65439, + 75, + 26, + 65437, + 96, + 2, + 0, + /* 3688 */ 27, + 26, + 65511, + 26, + 25, + 65396, + 42, + 65454, + 156, + 26, + 65437, + 96, + 2, + 0, + /* 3702 */ 65466, + 111, + 27, + 26, + 25, + 65398, + 42, + 65455, + 100, + 28, + 27, + 26, + 65395, + 43, + 65454, + 126, + 26, + 1, + 25, + 65439, + 96, + 2, + 0, + /* 3725 */ 27, + 26, + 25, + 65398, + 42, + 65455, + 127, + 26, + 1, + 25, + 65439, + 96, + 2, + 0, + /* 3739 */ 27, + 1, + 26, + 1, + 25, + 65397, + 43, + 65455, + 150, + 25, + 65441, + 96, + 2, + 0, + /* 3753 */ 65463, + 114, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65393, + 1, + 42, + 65453, + 156, + 25, + 65437, + 77, + 26, + 65435, + 98, + 2, + 0, + /* 3775 */ 27, + 26, + 65511, + 26, + 25, + 65394, + 42, + 65453, + 159, + 26, + 65435, + 98, + 2, + 0, + /* 3789 */ 65464, + 113, + 27, + 26, + 25, + 65396, + 42, + 65454, + 103, + 28, + 27, + 26, + 65393, + 43, + 65453, + 129, + 26, + 1, + 25, + 65437, + 98, + 2, + 0, + /* 3812 */ 27, + 26, + 25, + 65396, + 42, + 65454, + 130, + 26, + 1, + 25, + 65437, + 98, + 2, + 0, + /* 3826 */ 27, + 1, + 26, + 1, + 25, + 65395, + 43, + 65454, + 153, + 25, + 65439, + 98, + 2, + 0, + /* 3840 */ 65461, + 116, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65391, + 1, + 42, + 65452, + 159, + 25, + 65435, + 79, + 26, + 65433, + 100, + 2, + 0, + /* 3862 */ 27, + 26, + 65511, + 26, + 25, + 65392, + 42, + 65452, + 162, + 26, + 65433, + 100, + 2, + 0, + /* 3876 */ 65462, + 115, + 27, + 26, + 25, + 65394, + 42, + 65453, + 106, + 28, + 27, + 26, + 65391, + 43, + 65452, + 132, + 26, + 1, + 25, + 65435, + 100, + 2, + 0, + /* 3899 */ 27, + 26, + 25, + 65394, + 42, + 65453, + 133, + 26, + 1, + 25, + 65435, + 100, + 2, + 0, + /* 3913 */ 27, + 1, + 26, + 1, + 25, + 65393, + 43, + 65453, + 156, + 25, + 65437, + 100, + 2, + 0, + /* 3927 */ 65459, + 118, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65389, + 1, + 42, + 65451, + 162, + 25, + 65433, + 81, + 26, + 65431, + 102, + 2, + 0, + /* 3949 */ 27, + 26, + 65511, + 26, + 25, + 65390, + 42, + 65451, + 165, + 26, + 65431, + 102, + 2, + 0, + /* 3963 */ 65460, + 117, + 27, + 26, + 25, + 65392, + 42, + 65452, + 109, + 28, + 27, + 26, + 65389, + 43, + 65451, + 135, + 26, + 1, + 25, + 65433, + 102, + 2, + 0, + /* 3986 */ 27, + 26, + 25, + 65392, + 42, + 65452, + 136, + 26, + 1, + 25, + 65433, + 102, + 2, + 0, + /* 4000 */ 27, + 1, + 26, + 1, + 25, + 65391, + 43, + 65452, + 159, + 25, + 65435, + 102, + 2, + 0, + /* 4014 */ 157, + 65534, + 1, + 30, + 1, + 51, + 43, + 65458, + 36, + 1, + 43, + 65457, + 118, + 27, + 26, + 25, + 65390, + 42, + 65451, + 71, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65387, + 1, + 42, + 65450, + 138, + 26, + 1, + 25, + 65431, + 104, + 2, + 0, + /* 4057 */ 157, + 1, + 65533, + 31, + 1, + 51, + 1, + 43, + 65457, + 37, + 44, + 65456, + 77, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65387, + 1, + 42, + 65450, + 138, + 26, + 1, + 25, + 65431, + 104, + 2, + 0, + /* 4093 */ 52, + 1, + 43, + 65457, + 78, + 41, + 1, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65387, + 1, + 42, + 65450, + 138, + 26, + 1, + 25, + 65431, + 104, + 2, + 0, + /* 4121 */ 52, + 43, + 65458, + 36, + 44, + 65457, + 118, + 27, + 26, + 25, + 65390, + 42, + 65451, + 71, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65387, + 1, + 42, + 65450, + 138, + 26, + 1, + 25, + 65431, + 104, + 2, + 0, + /* 4156 */ 44, + 65457, + 78, + 41, + 1, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65387, + 1, + 42, + 65450, + 138, + 26, + 1, + 25, + 65431, + 104, + 2, + 0, + /* 4180 */ 43, + 65458, + 119, + 27, + 26, + 25, + 65390, + 42, + 65451, + 71, + 41, + 1, + 27, + 1, + 26, + 1, + 25, + 65387, + 43, + 65450, + 138, + 26, + 1, + 25, + 65431, + 104, + 2, + 0, + /* 4208 */ 65458, + 119, + 27, + 26, + 25, + 65390, + 42, + 65451, + 112, + 28, + 27, + 26, + 65387, + 43, + 65450, + 138, + 26, + 1, + 25, + 65431, + 104, + 2, + 0, + /* 4231 */ 27, + 26, + 25, + 65390, + 42, + 65451, + 139, + 26, + 1, + 25, + 65431, + 104, + 2, + 0, + /* 4245 */ 27, + 1, + 26, + 1, + 25, + 65389, + 43, + 65451, + 162, + 25, + 65433, + 104, + 2, + 0, + /* 4259 */ 26, + 1, + 25, + 65440, + 65455, + 176, + 2, + 0, + /* 4267 */ 26, + 1, + 25, + 65438, + 65454, + 179, + 2, + 0, + /* 4275 */ 26, + 1, + 25, + 65436, + 65453, + 182, + 2, + 0, + /* 4283 */ 26, + 1, + 25, + 65434, + 65452, + 185, + 2, + 0, + /* 4291 */ 26, + 1, + 25, + 65432, + 65451, + 188, + 2, + 0, + /* 4299 */ 65533, + 72, + 6, + 0, + /* 4303 */ 32, + 32, + 0, + /* 4306 */ 65533, + 56, + 0, + /* 4309 */ 52, + 43, + 65455, + 37, + 55, + 65450, + 74, + 0, + /* 4317 */ 1, + 65533, + 57, + 1, + 52, + 43, + 65455, + 50, + 65523, + 55, + 65450, + 74, + 0, + /* 4330 */ 65534, + 1, + 57, + 14, + 51, + 65523, + 55, + 65450, + 74, + 0, + /* 4340 */ 65, + 65523, + 55, + 65450, + 74, + 0, + /* 4346 */ 1, + 78, + 0, + /* 4349 */ 43, + 65455, + 80, + 0, + /* 4353 */ 51, + 42, + 65455, + 40, + 43, + 65454, + 81, + 0, + /* 4361 */ 51, + 42, + 65454, + 41, + 43, + 65453, + 82, + 0, + /* 4369 */ 42, + 65455, + 82, + 0, + /* 4373 */ 51, + 42, + 65453, + 42, + 43, + 65452, + 83, + 0, + /* 4381 */ 42, + 65454, + 83, + 0, + /* 4385 */ 51, + 42, + 65452, + 43, + 43, + 65451, + 84, + 0, + /* 4393 */ 42, + 65453, + 84, + 0, + /* 4397 */ 65534, + 1, + 47, + 1, + 50, + 42, + 65451, + 44, + 1, + 42, + 65450, + 85, + 0, + /* 4410 */ 1, + 65533, + 48, + 1, + 50, + 1, + 42, + 65450, + 85, + 0, + /* 4420 */ 51, + 1, + 42, + 65450, + 85, + 0, + /* 4426 */ 51, + 42, + 65451, + 44, + 43, + 65450, + 85, + 0, + /* 4434 */ 42, + 65452, + 85, + 0, + /* 4438 */ 42, + 65451, + 86, + 0, + /* 4442 */ 27, + 52, + 65485, + 26, + 50, + 65375, + 55, + 65450, + 143, + 26, + 65441, + 94, + 0, + /* 4455 */ 65469, + 108, + 54, + 65483, + 27, + 52, + 65485, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 143, + 26, + 65441, + 94, + 0, + /* 4473 */ 53, + 44, + 65469, + 22, + 72, + 65456, + 52, + 69, + 65509, + 54, + 65483, + 27, + 52, + 65485, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 143, + 26, + 65441, + 94, + 0, + /* 4498 */ 161, + 65534, + 1, + 26, + 1, + 53, + 44, + 65469, + 51, + 65507, + 72, + 65456, + 52, + 69, + 65509, + 54, + 65483, + 27, + 52, + 65485, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 143, + 26, + 65441, + 94, + 0, + /* 4529 */ 44, + 65469, + 66, + 69, + 65509, + 54, + 65483, + 27, + 52, + 65485, + 26, + 50, + 65388, + 65523, + 55, + 65450, + 143, + 26, + 65441, + 94, + 0, + /* 4550 */ 26, + 25, + 65398, + 42, + 65455, + 153, + 26, + 65439, + 96, + 0, + /* 4560 */ 27, + 26, + 65397, + 43, + 65455, + 150, + 25, + 65441, + 96, + 0, + /* 4570 */ 26, + 25, + 65396, + 42, + 65454, + 156, + 26, + 65437, + 98, + 0, + /* 4580 */ 27, + 26, + 65395, + 43, + 65454, + 153, + 25, + 65439, + 98, + 0, + /* 4590 */ 26, + 25, + 65394, + 42, + 65453, + 159, + 26, + 65435, + 100, + 0, + /* 4600 */ 27, + 26, + 65393, + 43, + 65453, + 156, + 25, + 65437, + 100, + 0, + /* 4610 */ 26, + 25, + 65392, + 42, + 65452, + 162, + 26, + 65433, + 102, + 0, + /* 4620 */ 27, + 26, + 65391, + 43, + 65452, + 159, + 25, + 65435, + 102, + 0, + /* 4630 */ 26, + 25, + 65390, + 42, + 65451, + 165, + 26, + 65431, + 104, + 0, + /* 4640 */ 27, + 26, + 65389, + 43, + 65451, + 162, + 25, + 65433, + 104, + 0, + /* 4650 */ 156, + 1, + 65533, + 32, + 1, + 51, + 43, + 65457, + 37, + 1, + 43, + 65456, + 119, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65387, + 1, + 42, + 65450, + 165, + 25, + 65431, + 106, + 0, + /* 4681 */ 52, + 43, + 65457, + 37, + 44, + 65456, + 119, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65387, + 1, + 42, + 65450, + 165, + 25, + 65431, + 106, + 0, + /* 4706 */ 43, + 65457, + 120, + 27, + 65469, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65387, + 1, + 42, + 65450, + 165, + 25, + 65431, + 106, + 0, + /* 4727 */ 65457, + 120, + 27, + 65510, + 27, + 26, + 65511, + 26, + 25, + 65387, + 1, + 42, + 65450, + 165, + 25, + 65431, + 106, + 0, + /* 4745 */ 27, + 1, + 26, + 1, + 25, + 65387, + 43, + 65450, + 165, + 25, + 65431, + 106, + 0, + /* 4758 */ 27, + 26, + 65387, + 43, + 65450, + 165, + 25, + 65431, + 106, + 0, + /* 4768 */ 159, + 1, + 1, + 26, + 30, + 52, + 65507, + 72, + 65456, + 52, + 69, + 65509, + 54, + 65510, + 52, + 65511, + 50, + 65388, + 42, + 65450, + 168, + 0, + /* 4790 */ 82, + 65507, + 72, + 65456, + 52, + 69, + 65509, + 54, + 65510, + 52, + 65511, + 50, + 65388, + 42, + 65450, + 168, + 0, + /* 4807 */ 52, + 65511, + 50, + 65430, + 65450, + 168, + 0, + /* 4814 */ 26, + 65440, + 65455, + 176, + 0, + /* 4819 */ 25, + 65440, + 65455, + 178, + 0, + /* 4824 */ 26, + 65438, + 65454, + 179, + 0, + /* 4829 */ 25, + 65438, + 65454, + 181, + 0, + /* 4834 */ 26, + 65436, + 65453, + 182, + 0, + /* 4839 */ 25, + 65436, + 65453, + 184, + 0, + /* 4844 */ 26, + 65434, + 65452, + 185, + 0, + /* 4849 */ 25, + 65434, + 65452, + 187, + 0, + /* 4854 */ 26, + 65432, + 65451, + 188, + 0, + /* 4859 */ 25, + 65432, + 65451, + 190, + 0, + /* 4864 */ 157, + 65535, + 65533, + 33, + 1, + 51, + 1, + 43, + 65456, + 79, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65388, + 42, + 65450, + 191, + 0, + /* 4886 */ 52, + 1, + 43, + 65456, + 79, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65388, + 42, + 65450, + 191, + 0, + /* 4903 */ 44, + 65456, + 79, + 41, + 27, + 26, + 65484, + 27, + 26, + 25, + 65388, + 42, + 65450, + 191, + 0, + /* 4918 */ 27, + 26, + 65511, + 26, + 25, + 65388, + 42, + 65450, + 191, + 0, + /* 4928 */ 26, + 1, + 25, + 65430, + 65450, + 191, + 0, + /* 4935 */ 26, + 65430, + 65450, + 191, + 0, + /* 4940 */ 65431, + 0, + /* 4942 */ 65433, + 0, + /* 4944 */ 65435, + 0, + /* 4946 */ 65437, + 0, + /* 4948 */ 65439, + 0, + /* 4950 */ 65441, + 0, + /* 4952 */ 65535, + 65533, + 49, + 51, + 42, + 65450, + 0, + /* 4959 */ 1, + 1, + 71, + 51, + 42, + 65450, + 0, + /* 4966 */ 156, + 65535, + 65533, + 34, + 52, + 43, + 65456, + 121, + 27, + 26, + 25, + 65388, + 42, + 65450, + 0, + /* 4981 */ 160, + 1, + 1, + 56, + 52, + 43, + 65456, + 121, + 27, + 26, + 25, + 65388, + 42, + 65450, + 0, + /* 4996 */ 25, + 65430, + 65450, + 0, + /* 5000 */ 65432, + 65451, + 0, + /* 5003 */ 65434, + 65452, + 0, + /* 5006 */ 65436, + 65453, + 0, + /* 5009 */ 65438, + 65454, + 0, + /* 5012 */ 65440, + 65455, + 0, + /* 5015 */ 65471, + 0, + /* 5017 */ 65463, + 65376, + 1, + 162, + 65375, + 1, + 215, + 52, + 43, + 65411, + 53, + 65484, + 0, + /* 5030 */ 65480, + 65375, + 1, + 161, + 65376, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5043 */ 65480, + 65376, + 1, + 161, + 65376, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5056 */ 65481, + 65377, + 1, + 161, + 65376, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5069 */ 65481, + 65376, + 1, + 160, + 65377, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5082 */ 65483, + 65376, + 1, + 160, + 65377, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5095 */ 65483, + 65377, + 1, + 160, + 65377, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5108 */ 65484, + 65378, + 1, + 160, + 65377, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5121 */ 65484, + 65377, + 1, + 159, + 65378, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5134 */ 65486, + 65377, + 1, + 159, + 65378, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5147 */ 65486, + 65378, + 1, + 159, + 65378, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5160 */ 65487, + 65379, + 1, + 159, + 65378, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5173 */ 65487, + 65378, + 1, + 158, + 65379, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5186 */ 65489, + 65378, + 1, + 158, + 65379, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5199 */ 65489, + 65379, + 1, + 158, + 65379, + 1, + 184, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5212 */ 65104, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 211, + 52, + 43, + 65411, + 53, + 65484, + 165, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5248 */ 65129, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 65440, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5284 */ 65129, + 1, + 1, + 1, + 1, + 1, + 1, + 212, + 52, + 43, + 65411, + 53, + 65484, + 165, + 27, + 65440, + 42, + 28, + 65423, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5312 */ 65155, + 1, + 1, + 1, + 1, + 1, + 1, + 181, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 65467, + 42, + 28, + 65423, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 0, + /* 5340 */ 65155, + 1, + 1, + 1, + 1, + 1, + 213, + 52, + 43, + 65411, + 53, + 65484, + 165, + 65467, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 0, + /* 5361 */ 65182, + 1, + 1, + 1, + 1, + 1, + 182, + 53, + 44, + 65440, + 53, + 65484, + 137, + 65495, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 0, + /* 5382 */ 65223, + 1, + 1, + 1, + 215, + 52, + 65454, + 53, + 65484, + 0, + /* 5392 */ 65252, + 1, + 1, + 1, + 184, + 53, + 65484, + 53, + 65484, + 0, + /* 5402 */ 65182, + 1, + 1, + 1, + 1, + 214, + 52, + 43, + 65411, + 53, + 65484, + 96, + 65493, + 65484, + 0, + /* 5417 */ 65210, + 1, + 1, + 1, + 1, + 183, + 53, + 44, + 65440, + 53, + 65484, + 96, + 65493, + 65484, + 0, + /* 5432 */ 65457, + 65535, + 65376, + 1, + 162, + 65375, + 1, + 162, + 65535, + 65376, + 1, + 161, + 65376, + 1, + 211, + 52, + 43, + 65411, + 53, + 65484, + 165, + 27, + 26, + 25, + 65389, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 40, + 51, + 42, + 65429, + 52, + 65485, + 0, + /* 5481 */ 65479, + 65535, + 65379, + 1, + 159, + 65378, + 1, + 159, + 65535, + 65379, + 1, + 158, + 65379, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 13, + 52, + 43, + 65442, + 52, + 65485, + 0, + /* 5530 */ 65477, + 65535, + 65378, + 1, + 159, + 65378, + 1, + 159, + 65535, + 65379, + 1, + 159, + 65378, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 15, + 52, + 43, + 65442, + 52, + 65485, + 0, + /* 5579 */ 65474, + 65535, + 65378, + 1, + 160, + 65377, + 1, + 160, + 65535, + 65378, + 1, + 159, + 65378, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 17, + 52, + 43, + 65442, + 52, + 65485, + 0, + /* 5628 */ 65472, + 65535, + 65377, + 1, + 160, + 65377, + 1, + 160, + 65535, + 65378, + 1, + 160, + 65377, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 19, + 52, + 43, + 65442, + 52, + 65485, + 0, + /* 5677 */ 65469, + 65535, + 65377, + 1, + 161, + 65376, + 1, + 161, + 65535, + 65377, + 1, + 160, + 65377, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 21, + 52, + 43, + 65442, + 52, + 65485, + 0, + /* 5726 */ 65467, + 65535, + 65376, + 1, + 161, + 65376, + 1, + 161, + 65535, + 65377, + 1, + 161, + 65376, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 23, + 52, + 43, + 65442, + 52, + 65485, + 0, + /* 5775 */ 65370, + 65376, + 1, + 162, + 65375, + 1, + 161, + 65376, + 1, + 161, + 65376, + 1, + 211, + 52, + 43, + 65411, + 53, + 65484, + 165, + 27, + 26, + 25, + 65389, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 40, + 51, + 65471, + 52, + 65485, + 0, + /* 5821 */ 65392, + 65379, + 1, + 159, + 65378, + 1, + 158, + 65379, + 1, + 158, + 65379, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 13, + 52, + 65485, + 52, + 65485, + 0, + /* 5867 */ 65392, + 65378, + 1, + 158, + 65379, + 1, + 159, + 65378, + 1, + 158, + 65379, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 14, + 52, + 65485, + 52, + 65485, + 0, + /* 5913 */ 65391, + 65378, + 1, + 159, + 65378, + 1, + 158, + 65379, + 1, + 159, + 65378, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 15, + 52, + 65485, + 52, + 65485, + 0, + /* 5959 */ 65391, + 65377, + 1, + 159, + 65378, + 1, + 159, + 65378, + 1, + 158, + 65379, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 16, + 52, + 65485, + 52, + 65485, + 0, + /* 6005 */ 65389, + 65378, + 1, + 160, + 65377, + 1, + 159, + 65378, + 1, + 159, + 65378, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 17, + 52, + 65485, + 52, + 65485, + 0, + /* 6051 */ 65389, + 65377, + 1, + 159, + 65378, + 1, + 160, + 65377, + 1, + 159, + 65378, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 18, + 52, + 65485, + 52, + 65485, + 0, + /* 6097 */ 65388, + 65377, + 1, + 160, + 65377, + 1, + 159, + 65378, + 1, + 160, + 65377, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 19, + 52, + 65485, + 52, + 65485, + 0, + /* 6143 */ 65388, + 65376, + 1, + 160, + 65377, + 1, + 160, + 65377, + 1, + 159, + 65378, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 20, + 52, + 65485, + 52, + 65485, + 0, + /* 6189 */ 65386, + 65377, + 1, + 161, + 65376, + 1, + 160, + 65377, + 1, + 160, + 65377, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 21, + 52, + 65485, + 52, + 65485, + 0, + /* 6235 */ 65386, + 65376, + 1, + 160, + 65377, + 1, + 161, + 65376, + 1, + 160, + 65377, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 22, + 52, + 65485, + 52, + 65485, + 0, + /* 6281 */ 65385, + 65376, + 1, + 161, + 65376, + 1, + 160, + 65377, + 1, + 161, + 65376, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 23, + 52, + 65485, + 52, + 65485, + 0, + /* 6327 */ 65385, + 65375, + 1, + 161, + 65376, + 1, + 161, + 65376, + 1, + 160, + 65377, + 1, + 180, + 53, + 44, + 65440, + 53, + 65484, + 137, + 28, + 27, + 26, + 65414, + 42, + 28, + 27, + 65396, + 44, + 42, + 28, + 65370, + 53, + 44, + 42, + 65398, + 53, + 44, + 65440, + 53, + 65484, + 24, + 52, + 65485, + 52, + 65485, + 0, + /* 6373 */ 65503, + 0, + /* 6375 */ 65504, + 65504, + 0, + /* 6378 */ 65266, + 1, + 1, + 216, + 65506, + 0, + /* 6384 */ 65412, + 65376, + 1, + 162, + 65375, + 1, + 161, + 65376, + 1, + 213, + 52, + 43, + 65411, + 53, + 65484, + 165, + 27, + 65440, + 42, + 65451, + 44, + 65440, + 53, + 65484, + 42, + 65522, + 0, + /* 6411 */ 65535, + 0, +}; + +static const uint16_t RISCVSubRegIdxLists[] = { + /* 0 */ 2, 1, 0, + /* 3 */ 3, 4, 0, + /* 6 */ 11, 3, 4, 12, 5, 6, 0, + /* 13 */ 15, 11, 3, 4, 12, 5, 6, 16, 13, 7, 8, + 14, 9, 10, 0, + /* 28 */ 3, 4, 5, 17, 20, 0, + /* 34 */ 3, 4, 5, 6, 17, 18, 20, 21, 22, 0, + /* 44 */ 11, 3, 4, 12, 5, 6, 17, 18, 19, 20, 21, + 22, 0, + /* 57 */ 3, 4, 5, 6, 7, 17, 18, 19, 20, 21, 22, + 27, 31, 35, 0, + /* 72 */ 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, + 22, 23, 27, 28, 31, 32, 35, 36, 39, 0, + /* 93 */ 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, + 21, 22, 23, 24, 27, 28, 29, 31, 32, 33, 35, + 36, 37, 39, 40, 42, 0, + /* 121 */ 3, 4, 5, 6, 7, 8, 9, 10, 17, 18, 19, + 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, + 43, 44, 0, + /* 157 */ 11, 3, 4, 12, 5, 6, 13, 7, 8, 17, 18, + 19, 20, 21, 22, 23, 24, 27, 28, 31, 32, 35, + 36, 39, 45, 48, 0, + /* 184 */ 11, 3, 4, 12, 5, 6, 13, 7, 8, 14, 9, + 10, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, + 50, 0, + /* 230 */ 15, 11, 3, 4, 12, 5, 6, 16, 13, 7, 8, + 14, 9, 10, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, + 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, + 47, 48, 49, 50, 0, +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char RISCVRegStrings[] = { + /* 0 */ "V3_V4_V5_V6_V7_V8_V9_V10\0" + /* 25 */ "X10\0" + /* 29 */ "V13_V14_V15_V16_V17_V18_V19_V20\0" + /* 61 */ "X20\0" + /* 65 */ "V23_V24_V25_V26_V27_V28_V29_V30\0" + /* 97 */ "X30\0" + /* 101 */ "V0\0" + /* 104 */ "X0\0" + /* 107 */ "V4_V5_V6_V7_V8_V9_V10_V11\0" + /* 133 */ "X11\0" + /* 137 */ "V14_V15_V16_V17_V18_V19_V20_V21\0" + /* 169 */ "X21\0" + /* 173 */ "V24_V25_V26_V27_V28_V29_V30_V31\0" + /* 205 */ "X31\0" + /* 209 */ "V0_V1\0" + /* 215 */ "X1\0" + /* 218 */ "V5_V6_V7_V8_V9_V10_V11_V12\0" + /* 245 */ "X12\0" + /* 249 */ "V15_V16_V17_V18_V19_V20_V21_V22\0" + /* 281 */ "X22\0" + /* 285 */ "V4M2_V6M2_V8M2_V10M2\0" + /* 306 */ "V14M2_V16M2_V18M2_V20M2\0" + /* 330 */ "V24M2_V26M2_V28M2_V30M2\0" + /* 354 */ "V0M2\0" + /* 359 */ "V6M2_V8M2_V10M2_V12M2\0" + /* 381 */ "V16M2_V18M2_V20M2_V22M2\0" + /* 405 */ "V0M2_V2M2\0" + /* 415 */ "V8M2_V10M2_V12M2_V14M2\0" + /* 438 */ "V18M2_V20M2_V22M2_V24M2\0" + /* 462 */ "V0M2_V2M2_V4M2\0" + /* 477 */ "V10M2_V12M2_V14M2_V16M2\0" + /* 501 */ "V20M2_V22M2_V24M2_V26M2\0" + /* 525 */ "V0M2_V2M2_V4M2_V6M2\0" + /* 545 */ "V12M2_V14M2_V16M2_V18M2\0" + /* 569 */ "V22M2_V24M2_V26M2_V28M2\0" + /* 593 */ "V2M2_V4M2_V6M2_V8M2\0" + /* 613 */ "V0_V1_V2\0" + /* 622 */ "X2\0" + /* 625 */ "V6_V7_V8_V9_V10_V11_V12_V13\0" + /* 653 */ "X13\0" + /* 657 */ "V16_V17_V18_V19_V20_V21_V22_V23\0" + /* 689 */ "X23\0" + /* 693 */ "V0_V1_V2_V3\0" + /* 705 */ "X3\0" + /* 708 */ "V7_V8_V9_V10_V11_V12_V13_V14\0" + /* 737 */ "X14\0" + /* 741 */ "V17_V18_V19_V20_V21_V22_V23_V24\0" + /* 773 */ "X24\0" + /* 777 */ "V16M4_V20M4\0" + /* 789 */ "V0M4\0" + /* 794 */ "V8M4_V12M4\0" + /* 805 */ "V20M4_V24M4\0" + /* 817 */ "V0M4_V4M4\0" + /* 827 */ "V12M4_V16M4\0" + /* 839 */ "V24M4_V28M4\0" + /* 851 */ "V4M4_V8M4\0" + /* 861 */ "V0_V1_V2_V3_V4\0" + /* 876 */ "X4\0" + /* 879 */ "V8_V9_V10_V11_V12_V13_V14_V15\0" + /* 909 */ "X15\0" + /* 913 */ "V18_V19_V20_V21_V22_V23_V24_V25\0" + /* 945 */ "X25\0" + /* 949 */ "V0_V1_V2_V3_V4_V5\0" + /* 967 */ "X5\0" + /* 970 */ "V9_V10_V11_V12_V13_V14_V15_V16\0" + /* 1001 */ "X16\0" + /* 1005 */ "V19_V20_V21_V22_V23_V24_V25_V26\0" + /* 1037 */ "X26\0" + /* 1041 */ "V0_V1_V2_V3_V4_V5_V6\0" + /* 1062 */ "X6\0" + /* 1065 */ "V10_V11_V12_V13_V14_V15_V16_V17\0" + /* 1097 */ "X17\0" + /* 1101 */ "V20_V21_V22_V23_V24_V25_V26_V27\0" + /* 1133 */ "X27\0" + /* 1137 */ "V0_V1_V2_V3_V4_V5_V6_V7\0" + /* 1161 */ "X7\0" + /* 1164 */ "V11_V12_V13_V14_V15_V16_V17_V18\0" + /* 1196 */ "X18\0" + /* 1200 */ "V21_V22_V23_V24_V25_V26_V27_V28\0" + /* 1232 */ "X28\0" + /* 1236 */ "V0M8\0" + /* 1241 */ "V24M8\0" + /* 1247 */ "V16M8\0" + /* 1253 */ "V8M8\0" + /* 1258 */ "V1_V2_V3_V4_V5_V6_V7_V8\0" + /* 1282 */ "X8\0" + /* 1285 */ "V12_V13_V14_V15_V16_V17_V18_V19\0" + /* 1317 */ "X19\0" + /* 1321 */ "V22_V23_V24_V25_V26_V27_V28_V29\0" + /* 1353 */ "X29\0" + /* 1357 */ "V2_V3_V4_V5_V6_V7_V8_V9\0" + /* 1381 */ "X9\0" + /* 1384 */ "F10_D\0" + /* 1390 */ "F20_D\0" + /* 1396 */ "F30_D\0" + /* 1402 */ "F0_D\0" + /* 1407 */ "F11_D\0" + /* 1413 */ "F21_D\0" + /* 1419 */ "F31_D\0" + /* 1425 */ "F1_D\0" + /* 1430 */ "F12_D\0" + /* 1436 */ "F22_D\0" + /* 1442 */ "F2_D\0" + /* 1447 */ "F13_D\0" + /* 1453 */ "F23_D\0" + /* 1459 */ "F3_D\0" + /* 1464 */ "F14_D\0" + /* 1470 */ "F24_D\0" + /* 1476 */ "F4_D\0" + /* 1481 */ "F15_D\0" + /* 1487 */ "F25_D\0" + /* 1493 */ "F5_D\0" + /* 1498 */ "F16_D\0" + /* 1504 */ "F26_D\0" + /* 1510 */ "F6_D\0" + /* 1515 */ "F17_D\0" + /* 1521 */ "F27_D\0" + /* 1527 */ "F7_D\0" + /* 1532 */ "F18_D\0" + /* 1538 */ "F28_D\0" + /* 1544 */ "F8_D\0" + /* 1549 */ "F19_D\0" + /* 1555 */ "F29_D\0" + /* 1561 */ "F9_D\0" + /* 1566 */ "VTYPE\0" + /* 1572 */ "F10_F\0" + /* 1578 */ "F20_F\0" + /* 1584 */ "F30_F\0" + /* 1590 */ "F0_F\0" + /* 1595 */ "F11_F\0" + /* 1601 */ "F21_F\0" + /* 1607 */ "F31_F\0" + /* 1613 */ "F1_F\0" + /* 1618 */ "F12_F\0" + /* 1624 */ "F22_F\0" + /* 1630 */ "F2_F\0" + /* 1635 */ "F13_F\0" + /* 1641 */ "F23_F\0" + /* 1647 */ "F3_F\0" + /* 1652 */ "F14_F\0" + /* 1658 */ "F24_F\0" + /* 1664 */ "F4_F\0" + /* 1669 */ "F15_F\0" + /* 1675 */ "F25_F\0" + /* 1681 */ "F5_F\0" + /* 1686 */ "F16_F\0" + /* 1692 */ "F26_F\0" + /* 1698 */ "F6_F\0" + /* 1703 */ "F17_F\0" + /* 1709 */ "F27_F\0" + /* 1715 */ "F7_F\0" + /* 1720 */ "F18_F\0" + /* 1726 */ "F28_F\0" + /* 1732 */ "F8_F\0" + /* 1737 */ "F19_F\0" + /* 1743 */ "F29_F\0" + /* 1749 */ "F9_F\0" + /* 1754 */ "F10_H\0" + /* 1760 */ "F20_H\0" + /* 1766 */ "F30_H\0" + /* 1772 */ "F0_H\0" + /* 1777 */ "F11_H\0" + /* 1783 */ "F21_H\0" + /* 1789 */ "F31_H\0" + /* 1795 */ "F1_H\0" + /* 1800 */ "F12_H\0" + /* 1806 */ "F22_H\0" + /* 1812 */ "F2_H\0" + /* 1817 */ "F13_H\0" + /* 1823 */ "F23_H\0" + /* 1829 */ "F3_H\0" + /* 1834 */ "F14_H\0" + /* 1840 */ "F24_H\0" + /* 1846 */ "F4_H\0" + /* 1851 */ "F15_H\0" + /* 1857 */ "F25_H\0" + /* 1863 */ "F5_H\0" + /* 1868 */ "F16_H\0" + /* 1874 */ "F26_H\0" + /* 1880 */ "F6_H\0" + /* 1885 */ "F17_H\0" + /* 1891 */ "F27_H\0" + /* 1897 */ "F7_H\0" + /* 1902 */ "F18_H\0" + /* 1908 */ "F28_H\0" + /* 1914 */ "F8_H\0" + /* 1919 */ "F19_H\0" + /* 1925 */ "F29_H\0" + /* 1931 */ "F9_H\0" + /* 1936 */ "VL\0" + /* 1939 */ "FRM\0" + /* 1943 */ "VXRM\0" + /* 1948 */ "FCSR\0" + /* 1953 */ "FFLAGS\0" + /* 1960 */ "VXSAT\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterDesc RISCVRegDesc[] = { + // Descriptors + {24, 0, 0, 0, 0, 0}, + {1948, 8, 8, 2, 102577, 4}, + {1953, 8, 8, 2, 102577, 1689}, + {1939, 8, 8, 2, 102577, 1307}, + {1936, 8, 8, 2, 102577, 1315}, + {1566, 8, 8, 2, 102577, 1309}, + {1943, 8, 8, 2, 102577, 782}, + {1960, 8, 8, 2, 102577, 843}, + {101, 8, 4981, 2, 102577, 446}, + {212, 8, 4768, 2, 102577, 4}, + {619, 8, 4498, 2, 102577, 1317}, + {702, 8, 3588, 2, 102577, 1319}, + {873, 8, 3545, 2, 102577, 1313}, + {964, 8, 2252, 2, 102577, 1311}, + {1059, 8, 1929, 2, 102577, 1484}, + {1158, 8, 721, 2, 102577, 813}, + {1279, 8, 771, 2, 102577, 815}, + {1378, 8, 1041, 2, 102577, 1680}, + {21, 8, 671, 2, 102577, 1330}, + {129, 8, 956, 2, 102577, 1484}, + {241, 8, 906, 2, 102577, 817}, + {649, 8, 1312, 2, 102577, 786}, + {733, 8, 856, 2, 102577, 1353}, + {905, 8, 1227, 2, 102577, 1347}, + {997, 8, 1177, 2, 102577, 1351}, + {1093, 8, 1583, 2, 102577, 285}, + {1192, 8, 1127, 2, 102577, 1345}, + {1313, 8, 1498, 2, 102577, 819}, + {57, 8, 1448, 2, 102577, 4}, + {165, 8, 1804, 2, 102577, 928}, + {277, 8, 1398, 2, 102577, 788}, + {685, 8, 1719, 2, 102577, 477}, + {769, 8, 1669, 2, 102577, 1341}, + {941, 8, 2950, 2, 102577, 1343}, + {1033, 8, 3066, 2, 102577, 1349}, + {1129, 8, 4014, 2, 102577, 468}, + {1228, 8, 4057, 2, 102577, 648}, + {1349, 8, 4650, 2, 102577, 910}, + {93, 8, 4864, 2, 102577, 839}, + {201, 8, 4966, 2, 102577, 823}, + {104, 8, 8, 2, 102577, 832}, + {215, 8, 8, 2, 102577, 806}, + {622, 8, 8, 2, 102577, 821}, + {705, 8, 8, 2, 102577, 830}, + {876, 8, 8, 2, 102577, 841}, + {967, 8, 8, 2, 102577, 1321}, + {1062, 8, 8, 2, 102577, 648}, + {1161, 8, 8, 2, 102577, 1328}, + {1282, 8, 8, 2, 102577, 648}, + {1381, 8, 8, 2, 102577, 559}, + {25, 8, 8, 2, 102577, 1484}, + {133, 8, 8, 2, 102577, 648}, + {245, 8, 8, 2, 102577, 648}, + {653, 8, 8, 2, 102577, 648}, + {737, 8, 8, 2, 102577, 1323}, + {909, 8, 8, 2, 102577, 379}, + {1001, 8, 8, 2, 102577, 1281}, + {1097, 8, 8, 2, 102577, 488}, + {1196, 8, 8, 2, 102577, 1271}, + {1317, 8, 8, 2, 102577, 494}, + {61, 8, 8, 2, 102577, 4}, + {169, 8, 8, 2, 102577, 4}, + {281, 8, 8, 2, 102577, 4}, + {689, 8, 8, 2, 102577, 895}, + {773, 8, 8, 2, 102577, 889}, + {945, 8, 8, 2, 102577, 891}, + {1037, 8, 8, 2, 102577, 902}, + {1133, 8, 8, 2, 102577, 904}, + {1232, 8, 8, 2, 102577, 4}, + {1353, 8, 8, 2, 102577, 4}, + {97, 8, 8, 2, 102577, 893}, + {205, 8, 8, 2, 102577, 4}, + {1402, 4303, 8, 0, 102577, 4}, + {1425, 4303, 8, 0, 102577, 540}, + {1442, 4303, 8, 0, 102577, 906}, + {1459, 4303, 8, 0, 102577, 908}, + {1476, 4303, 8, 0, 102577, 4}, + {1493, 4303, 8, 0, 102577, 768}, + {1510, 4303, 8, 0, 102577, 772}, + {1527, 4303, 8, 0, 102577, 776}, + {1544, 4303, 8, 0, 102577, 780}, + {1561, 4303, 8, 0, 102577, 804}, + {1384, 4303, 8, 0, 102577, 847}, + {1407, 4303, 8, 0, 102577, 851}, + {1430, 4303, 8, 0, 102577, 1650}, + {1447, 4303, 8, 0, 102577, 745}, + {1464, 4303, 8, 0, 102577, 1581}, + {1481, 4303, 8, 0, 102577, 766}, + {1498, 4303, 8, 0, 102577, 770}, + {1515, 4303, 8, 0, 102577, 774}, + {1532, 4303, 8, 0, 102577, 778}, + {1549, 4303, 8, 0, 102577, 784}, + {1390, 4303, 8, 0, 102577, 845}, + {1413, 4303, 8, 0, 102577, 849}, + {1436, 4303, 8, 0, 102577, 853}, + {1453, 4303, 8, 0, 102577, 1583}, + {1470, 4303, 8, 0, 102577, 1592}, + {1487, 4303, 8, 0, 102577, 1712}, + {1504, 4303, 8, 0, 102577, 1720}, + {1521, 4303, 8, 0, 102577, 883}, + {1538, 4303, 8, 0, 102577, 855}, + {1555, 4303, 8, 0, 102577, 4}, + {1396, 4303, 8, 0, 102577, 486}, + {1419, 4303, 8, 0, 102577, 1285}, + {1590, 4304, 6376, 1, 101969, 4}, + {1613, 4304, 6376, 1, 101969, 1283}, + {1630, 4304, 6376, 1, 101969, 1484}, + {1647, 4304, 6376, 1, 101969, 1317}, + {1664, 4304, 6376, 1, 101969, 648}, + {1681, 4304, 6376, 1, 101969, 648}, + {1698, 4304, 6376, 1, 101969, 648}, + {1715, 4304, 6376, 1, 101969, 379}, + {1732, 4304, 6376, 1, 101969, 1305}, + {1749, 4304, 6376, 1, 101969, 261}, + {1572, 4304, 6376, 1, 101969, 1465}, + {1595, 4304, 6376, 1, 101969, 4}, + {1618, 4304, 6376, 1, 101969, 4}, + {1635, 4304, 6376, 1, 101969, 1456}, + {1652, 4304, 6376, 1, 101969, 648}, + {1669, 4304, 6376, 1, 101969, 165}, + {1686, 4304, 6376, 1, 101969, 1467}, + {1703, 4304, 6376, 1, 101969, 165}, + {1720, 4304, 6376, 1, 101969, 165}, + {1737, 4304, 6376, 1, 101969, 4}, + {1578, 4304, 6376, 1, 101969, 379}, + {1601, 4304, 6376, 1, 101969, 4}, + {1624, 4304, 6376, 1, 101969, 165}, + {1641, 4304, 6376, 1, 101969, 1469}, + {1658, 4304, 6376, 1, 101969, 4}, + {1675, 4304, 6376, 1, 101969, 559}, + {1692, 4304, 6376, 1, 101969, 496}, + {1709, 4304, 6376, 1, 101969, 4}, + {1726, 4304, 6376, 1, 101969, 648}, + {1743, 4304, 6376, 1, 101969, 1474}, + {1584, 4304, 6376, 1, 101969, 457}, + {1607, 4304, 6376, 1, 101969, 648}, + {1772, 8, 6375, 2, 80241, 648}, + {1795, 8, 6375, 2, 80241, 4}, + {1812, 8, 6375, 2, 80241, 1476}, + {1829, 8, 6375, 2, 80241, 205}, + {1846, 8, 6375, 2, 80241, 648}, + {1863, 8, 6375, 2, 80241, 225}, + {1880, 8, 6375, 2, 80241, 1478}, + {1897, 8, 6375, 2, 80241, 4}, + {1914, 8, 6375, 2, 80241, 475}, + {1931, 8, 6375, 2, 80241, 1563}, + {1754, 8, 6375, 2, 80241, 4}, + {1777, 8, 6375, 2, 80241, 484}, + {1800, 8, 6375, 2, 80241, 1167}, + {1817, 8, 6375, 2, 80241, 231}, + {1834, 8, 6375, 2, 80241, 250}, + {1851, 8, 6375, 2, 80241, 252}, + {1868, 8, 6375, 2, 80241, 240}, + {1885, 8, 6375, 2, 80241, 242}, + {1902, 8, 6375, 2, 80241, 273}, + {1919, 8, 6375, 2, 80241, 1228}, + {1760, 8, 6375, 2, 80241, 1563}, + {1783, 8, 6375, 2, 80241, 544}, + {1806, 8, 6375, 2, 80241, 559}, + {1823, 8, 6375, 2, 80241, 648}, + {1840, 8, 6375, 2, 80241, 4}, + {1857, 8, 6375, 2, 80241, 1233}, + {1874, 8, 6375, 2, 80241, 1240}, + {1891, 8, 6375, 2, 80241, 1238}, + {1908, 8, 6375, 2, 80241, 520}, + {1925, 8, 6375, 2, 80241, 165}, + {1766, 8, 6375, 2, 80241, 4}, + {1789, 8, 6375, 2, 80241, 648}, + {354, 602, 4959, 3, 2720, 1549}, + {789, 583, 4346, 6, 1792, 1242}, + {1236, 590, 8, 13, 0, 84}, + {410, 587, 4330, 3, 9138, 1546}, + {472, 602, 4317, 3, 9138, 1250}, + {822, 598, 4299, 6, 1872, 406}, + {540, 602, 3224, 3, 9090, 1253}, + {608, 624, 3238, 3, 9090, 696}, + {856, 605, 539, 6, 1952, 725}, + {1253, 612, 8, 13, 144, 1256}, + {300, 602, 3287, 3, 9042, 284}, + {375, 624, 3252, 3, 9042, 420}, + {799, 620, 543, 6, 2032, 319}, + {432, 624, 3322, 3, 8994, 1265}, + {495, 646, 3273, 3, 8994, 1268}, + {833, 627, 531, 6, 2112, 314}, + {1247, 634, 8, 13, 288, 49}, + {563, 624, 3357, 3, 8946, 1534}, + {324, 646, 3308, 3, 8946, 572}, + {783, 642, 535, 6, 2192, 58}, + {399, 646, 3378, 3, 8898, 1273}, + {456, 668, 3343, 3, 8898, 508}, + {811, 649, 527, 6, 2272, 1276}, + {1241, 656, 8, 13, 432, 690}, + {519, 646, 4397, 3, 8850, 3}, + {587, 668, 4410, 3, 8850, 1230}, + {845, 664, 4306, 6, 2352, 897}, + {348, 668, 4952, 3, 8384, 1235}, + {616, 580, 4790, 3, 9233, 1247}, + {699, 580, 4473, 3, 9233, 696}, + {870, 580, 3624, 3, 9233, 696}, + {961, 580, 3486, 3, 9233, 1075}, + {1056, 580, 2217, 3, 9233, 372}, + {1155, 580, 1890, 3, 9233, 567}, + {1276, 580, 821, 3, 9233, 558}, + {1375, 580, 2073, 3, 9233, 3}, + {18, 580, 1091, 3, 9233, 546}, + {125, 580, 2006, 3, 9233, 546}, + {237, 580, 1006, 3, 9233, 1078}, + {645, 580, 2384, 3, 9233, 324}, + {729, 580, 1362, 3, 9233, 102}, + {901, 580, 2317, 3, 9233, 102}, + {993, 580, 1277, 3, 9233, 1081}, + {1089, 580, 2595, 3, 9233, 3}, + {1188, 580, 1633, 3, 9233, 347}, + {1309, 580, 2528, 3, 9233, 696}, + {53, 580, 1548, 3, 9233, 696}, + {161, 580, 2806, 3, 9233, 1325}, + {273, 580, 1854, 3, 9233, 1471}, + {681, 580, 2739, 3, 9233, 1093}, + {765, 580, 1769, 3, 9233, 3}, + {937, 580, 2999, 3, 9233, 505}, + {1029, 580, 3112, 3, 9233, 1072}, + {1125, 580, 4121, 3, 9233, 327}, + {1224, 580, 4093, 3, 9233, 330}, + {1345, 580, 4681, 3, 9233, 755}, + {89, 580, 4886, 3, 9233, 1019}, + {197, 580, 4970, 3, 9233, 747}, + {209, 574, 4970, 3, 2720, 311}, + {467, 5030, 4340, 44, 2434, 1022}, + {535, 5043, 4309, 44, 2434, 263}, + {603, 5069, 3266, 44, 2434, 79}, + {295, 5056, 4353, 44, 2434, 708}, + {369, 5082, 3301, 44, 2434, 1027}, + {426, 5095, 4361, 44, 2434, 268}, + {489, 5121, 3336, 44, 2434, 694}, + {557, 5108, 4373, 44, 2434, 16}, + {318, 5134, 3371, 44, 2434, 300}, + {393, 5147, 4385, 44, 2434, 26}, + {450, 5173, 3392, 44, 2434, 333}, + {513, 5160, 4426, 44, 2434, 21}, + {581, 5186, 4420, 44, 2434, 1032}, + {342, 5199, 4955, 44, 2434, 1042}, + {405, 5017, 4955, 44, 1792, 1037}, + {851, 5726, 8, 230, 580, 1047}, + {794, 5677, 8, 230, 580, 795}, + {827, 5628, 8, 230, 580, 1056}, + {777, 5579, 8, 230, 580, 448}, + {805, 5530, 8, 230, 580, 397}, + {839, 5481, 8, 230, 580, 618}, + {817, 5432, 8, 230, 0, 459}, + {696, 547, 4775, 28, 2657, 1561}, + {867, 547, 4529, 28, 2657, 717}, + {958, 547, 3521, 28, 2657, 1520}, + {1053, 547, 3458, 28, 2657, 912}, + {1152, 547, 2188, 28, 2657, 916}, + {1273, 547, 1978, 28, 2657, 381}, + {1372, 547, 2112, 28, 2657, 2}, + {15, 547, 2140, 28, 2657, 542}, + {122, 547, 2499, 28, 2657, 146}, + {233, 547, 2045, 28, 2657, 2}, + {641, 547, 2423, 28, 2657, 114}, + {725, 547, 2451, 28, 2657, 490}, + {897, 547, 2710, 28, 2657, 118}, + {989, 547, 2356, 28, 2657, 924}, + {1085, 547, 2634, 28, 2657, 920}, + {1184, 547, 2662, 28, 2657, 203}, + {1305, 547, 2921, 28, 2657, 122}, + {49, 547, 2567, 28, 2657, 126}, + {157, 547, 2845, 28, 2657, 213}, + {269, 547, 2873, 28, 2657, 885}, + {677, 547, 3195, 28, 2657, 930}, + {761, 547, 2778, 28, 2657, 678}, + {933, 547, 3038, 28, 2657, 217}, + {1025, 547, 3147, 28, 2657, 174}, + {1121, 547, 4180, 28, 2657, 938}, + {1220, 547, 4156, 28, 2657, 946}, + {1341, 547, 4706, 28, 2657, 942}, + {85, 547, 4903, 28, 2657, 2}, + {193, 547, 4971, 28, 2657, 934}, + {613, 6378, 4971, 28, 2592, 1520}, + {530, 497, 4313, 157, 1378, 590}, + {598, 470, 4349, 157, 1378, 498}, + {290, 443, 4369, 157, 1378, 959}, + {364, 416, 4357, 157, 1378, 583}, + {420, 389, 4381, 157, 1378, 966}, + {483, 362, 4365, 157, 1378, 627}, + {551, 335, 4393, 157, 1378, 233}, + {312, 308, 4377, 157, 1378, 980}, + {387, 281, 4434, 157, 1378, 350}, + {444, 254, 4389, 157, 1378, 611}, + {507, 227, 4438, 157, 1378, 987}, + {575, 200, 4430, 157, 1378, 390}, + {336, 173, 4956, 157, 1378, 973}, + {462, 6384, 4956, 157, 1264, 994}, + {864, 5392, 4778, 34, 2513, 1009}, + {955, 5392, 4455, 34, 2513, 597}, + {1050, 5392, 3468, 34, 2513, 634}, + {1149, 5392, 3435, 34, 2513, 639}, + {1270, 5392, 2298, 34, 2513, 470}, + {1369, 5392, 3399, 34, 2513, 1524}, + {12, 5392, 2169, 34, 2513, 282}, + {119, 5392, 3702, 34, 2513, 6}, + {230, 5392, 2509, 34, 2513, 357}, + {637, 5392, 3666, 34, 2513, 790}, + {721, 5392, 2480, 34, 2513, 362}, + {893, 5392, 3789, 34, 2513, 750}, + {985, 5392, 2720, 34, 2513, 11}, + {1081, 5392, 3753, 34, 2513, 1014}, + {1180, 5392, 2691, 34, 2513, 1529}, + {1301, 5392, 3876, 34, 2513, 725}, + {45, 5392, 2931, 34, 2513, 808}, + {153, 5392, 3840, 34, 2513, 834}, + {265, 5392, 2902, 34, 2513, 1109}, + {673, 5392, 3963, 34, 2513, 825}, + {757, 5392, 3205, 34, 2513, 1114}, + {929, 5392, 3927, 34, 2513, 1119}, + {1021, 5392, 3176, 34, 2513, 428}, + {1117, 5392, 4208, 34, 2513, 423}, + {1216, 5392, 4190, 34, 2513, 479}, + {1337, 5392, 4727, 34, 2513, 385}, + {81, 5392, 4874, 34, 2513, 441}, + {189, 5392, 4972, 34, 2513, 367}, + {693, 5382, 4972, 34, 1792, 570}, + {593, 6327, 8, 184, 722, 287}, + {285, 6281, 5013, 184, 722, 186}, + {359, 6235, 8, 184, 722, 1124}, + {415, 6189, 5010, 184, 722, 1142}, + {477, 6143, 8, 184, 722, 305}, + {545, 6097, 5007, 184, 722, 1133}, + {306, 6051, 8, 184, 722, 31}, + {381, 6005, 5004, 184, 722, 40}, + {438, 5959, 8, 184, 722, 549}, + {501, 5913, 5001, 184, 722, 296}, + {569, 5867, 8, 184, 722, 1158}, + {330, 5821, 4957, 184, 722, 338}, + {525, 5775, 4957, 184, 0, 1537}, + {952, 5417, 4780, 57, 1697, 522}, + {1047, 5417, 4442, 57, 1697, 207}, + {1146, 5417, 3444, 57, 1697, 1722}, + {1267, 5417, 3652, 57, 1697, 1480}, + {1366, 5417, 3739, 57, 1697, 528}, + {9, 5417, 3421, 57, 1697, 1181}, + {116, 5417, 3725, 57, 1697, 0}, + {227, 5417, 3711, 57, 1697, 1169}, + {634, 5417, 3826, 57, 1697, 1103}, + {717, 5417, 3688, 57, 1697, 244}, + {889, 5417, 3812, 57, 1697, 644}, + {981, 5417, 3798, 57, 1697, 1193}, + {1077, 5417, 3913, 57, 1697, 227}, + {1176, 5417, 3775, 57, 1697, 1187}, + {1297, 5417, 3899, 57, 1697, 1492}, + {41, 5417, 3885, 57, 1697, 658}, + {149, 5417, 4000, 57, 1697, 221}, + {261, 5417, 3862, 57, 1697, 1498}, + {669, 5417, 3986, 57, 1697, 664}, + {753, 5417, 3972, 57, 1697, 561}, + {925, 5417, 4245, 57, 1697, 1486}, + {1017, 5417, 3949, 57, 1697, 670}, + {1113, 5417, 4231, 57, 1697, 676}, + {1212, 5417, 4217, 57, 1697, 732}, + {1333, 5417, 4745, 57, 1697, 375}, + {77, 5417, 4918, 57, 1697, 1199}, + {185, 5417, 4974, 57, 1697, 534}, + {861, 5402, 4974, 57, 1600, 1175}, + {1044, 5361, 4807, 72, 1489, 1214}, + {1143, 5361, 4445, 72, 1489, 167}, + {1264, 5361, 3451, 72, 1489, 275}, + {1363, 5361, 4560, 72, 1489, 1221}, + {6, 5361, 4259, 72, 1489, 72}, + {113, 5361, 4550, 72, 1489, 1673}, + {224, 5361, 3718, 72, 1489, 1698}, + {631, 5361, 4580, 72, 1489, 1691}, + {714, 5361, 4267, 72, 1489, 1666}, + {885, 5361, 4570, 72, 1489, 1622}, + {977, 5361, 3805, 72, 1489, 1705}, + {1073, 5361, 4600, 72, 1489, 1682}, + {1172, 5361, 4275, 72, 1489, 1629}, + {1293, 5361, 4590, 72, 1489, 1608}, + {37, 5361, 3892, 72, 1489, 1643}, + {145, 5361, 4620, 72, 1489, 1615}, + {257, 5361, 4283, 72, 1489, 1594}, + {665, 5361, 4610, 72, 1489, 1601}, + {749, 5361, 3979, 72, 1489, 1636}, + {921, 5361, 4640, 72, 1489, 1659}, + {1013, 5361, 4291, 72, 1489, 1652}, + {1109, 5361, 4630, 72, 1489, 1585}, + {1208, 5361, 4050, 72, 1489, 1151}, + {1329, 5361, 4758, 72, 1489, 1065}, + {73, 5361, 4928, 72, 1489, 1458}, + {181, 5361, 4975, 72, 1489, 738}, + {949, 5340, 4975, 72, 1264, 1096}, + {1140, 5312, 4809, 93, 1137, 1001}, + {1261, 5312, 4451, 93, 1137, 866}, + {1360, 5312, 4566, 93, 1137, 1714}, + {3, 5312, 4814, 93, 1137, 758}, + {110, 5312, 4819, 93, 1137, 130}, + {221, 5312, 4556, 93, 1137, 1387}, + {628, 5312, 4586, 93, 1137, 730}, + {711, 5312, 4824, 93, 1137, 138}, + {882, 5312, 4829, 93, 1137, 650}, + {973, 5312, 4576, 93, 1137, 195}, + {1069, 5312, 4606, 93, 1137, 682}, + {1168, 5312, 4834, 93, 1137, 433}, + {1289, 5312, 4839, 93, 1137, 1504}, + {33, 5312, 4596, 93, 1137, 1355}, + {141, 5312, 4626, 93, 1137, 1363}, + {253, 5312, 4844, 93, 1137, 1395}, + {661, 5312, 4849, 93, 1137, 178}, + {745, 5312, 4616, 93, 1137, 1565}, + {917, 5312, 4646, 93, 1137, 713}, + {1009, 5312, 4854, 93, 1137, 1403}, + {1105, 5312, 4859, 93, 1137, 1573}, + {1204, 5312, 4636, 93, 1137, 150}, + {1325, 5312, 4677, 93, 1137, 575}, + {69, 5312, 4935, 93, 1137, 1512}, + {177, 5312, 4996, 93, 1137, 1371}, + {1041, 5284, 4996, 93, 1008, 1379}, + {1258, 5248, 8, 121, 865, 254}, + {1357, 5248, 4950, 121, 865, 874}, + {0, 5248, 8, 121, 865, 1728}, + {107, 5248, 5012, 121, 865, 857}, + {218, 5248, 8, 121, 865, 158}, + {625, 5248, 4948, 121, 865, 1552}, + {708, 5248, 8, 121, 865, 721}, + {879, 5248, 5009, 121, 865, 1411}, + {970, 5248, 8, 121, 865, 63}, + {1065, 5248, 4946, 121, 865, 105}, + {1164, 5248, 8, 121, 865, 602}, + {1285, 5248, 5006, 121, 865, 1084}, + {29, 5248, 8, 121, 865, 699}, + {137, 5248, 4944, 121, 865, 1332}, + {249, 5248, 8, 121, 865, 1296}, + {657, 5248, 5003, 121, 865, 1287}, + {741, 5248, 8, 121, 865, 950}, + {913, 5248, 4942, 121, 865, 1205}, + {1005, 5248, 8, 121, 865, 1420}, + {1101, 5248, 5000, 121, 865, 1429}, + {1200, 5248, 8, 121, 865, 1438}, + {1321, 5248, 4940, 121, 865, 511}, + {65, 5248, 8, 121, 865, 93}, + {173, 5248, 4997, 121, 865, 1447}, + {1137, 5212, 4997, 121, 0, 411}, +}; + +// FPR16 Register Class... +static const MCPhysReg FPR16[] = { + RISCV_F0_H, RISCV_F1_H, RISCV_F2_H, RISCV_F3_H, RISCV_F4_H, + RISCV_F5_H, RISCV_F6_H, RISCV_F7_H, RISCV_F10_H, RISCV_F11_H, + RISCV_F12_H, RISCV_F13_H, RISCV_F14_H, RISCV_F15_H, RISCV_F16_H, + RISCV_F17_H, RISCV_F28_H, RISCV_F29_H, RISCV_F30_H, RISCV_F31_H, + RISCV_F8_H, RISCV_F9_H, RISCV_F18_H, RISCV_F19_H, RISCV_F20_H, + RISCV_F21_H, RISCV_F22_H, RISCV_F23_H, RISCV_F24_H, RISCV_F25_H, + RISCV_F26_H, RISCV_F27_H, +}; + +// FPR16 Bit set. +static const uint8_t FPR16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +}; + +// AnyReg Register Class... +static const MCPhysReg AnyReg[] = { + RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, + RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X8, RISCV_X9, + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, + RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X18, RISCV_X19, + RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, + RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X28, RISCV_X29, + RISCV_X30, RISCV_X31, RISCV_F0_D, RISCV_F1_D, RISCV_F2_D, + RISCV_F3_D, RISCV_F4_D, RISCV_F5_D, RISCV_F6_D, RISCV_F7_D, + RISCV_F8_D, RISCV_F9_D, RISCV_F10_D, RISCV_F11_D, RISCV_F12_D, + RISCV_F13_D, RISCV_F14_D, RISCV_F15_D, RISCV_F16_D, RISCV_F17_D, + RISCV_F18_D, RISCV_F19_D, RISCV_F20_D, RISCV_F21_D, RISCV_F22_D, + RISCV_F23_D, RISCV_F24_D, RISCV_F25_D, RISCV_F26_D, RISCV_F27_D, + RISCV_F28_D, RISCV_F29_D, RISCV_F30_D, RISCV_F31_D, RISCV_V0, + RISCV_V1, RISCV_V2, RISCV_V3, RISCV_V4, RISCV_V5, + RISCV_V6, RISCV_V7, RISCV_V8, RISCV_V9, RISCV_V10, + RISCV_V11, RISCV_V12, RISCV_V13, RISCV_V14, RISCV_V15, + RISCV_V16, RISCV_V17, RISCV_V18, RISCV_V19, RISCV_V20, + RISCV_V21, RISCV_V22, RISCV_V23, RISCV_V24, RISCV_V25, + RISCV_V26, RISCV_V27, RISCV_V28, RISCV_V29, RISCV_V30, + RISCV_V31, +}; + +// AnyReg Bit set. +static const uint8_t AnyRegBits[] = { + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +}; + +// AnyReg_with_sub_16 Register Class... +static const MCPhysReg AnyReg_with_sub_16[] = { + RISCV_F0_D, RISCV_F1_D, RISCV_F2_D, RISCV_F3_D, RISCV_F4_D, + RISCV_F5_D, RISCV_F6_D, RISCV_F7_D, RISCV_F8_D, RISCV_F9_D, + RISCV_F10_D, RISCV_F11_D, RISCV_F12_D, RISCV_F13_D, RISCV_F14_D, + RISCV_F15_D, RISCV_F16_D, RISCV_F17_D, RISCV_F18_D, RISCV_F19_D, + RISCV_F20_D, RISCV_F21_D, RISCV_F22_D, RISCV_F23_D, RISCV_F24_D, + RISCV_F25_D, RISCV_F26_D, RISCV_F27_D, RISCV_F28_D, RISCV_F29_D, + RISCV_F30_D, RISCV_F31_D, +}; + +// AnyReg_with_sub_16 Bit set. +static const uint8_t AnyReg_with_sub_16Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +}; + +// FPR32 Register Class... +static const MCPhysReg FPR32[] = { + RISCV_F0_F, RISCV_F1_F, RISCV_F2_F, RISCV_F3_F, RISCV_F4_F, + RISCV_F5_F, RISCV_F6_F, RISCV_F7_F, RISCV_F10_F, RISCV_F11_F, + RISCV_F12_F, RISCV_F13_F, RISCV_F14_F, RISCV_F15_F, RISCV_F16_F, + RISCV_F17_F, RISCV_F28_F, RISCV_F29_F, RISCV_F30_F, RISCV_F31_F, + RISCV_F8_F, RISCV_F9_F, RISCV_F18_F, RISCV_F19_F, RISCV_F20_F, + RISCV_F21_F, RISCV_F22_F, RISCV_F23_F, RISCV_F24_F, RISCV_F25_F, + RISCV_F26_F, RISCV_F27_F, +}; + +// FPR32 Bit set. +static const uint8_t FPR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +}; + +// GPR Register Class... +static const MCPhysReg GPR[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, + RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, + RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, + RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, + RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, +}; + +// GPR Bit set. +static const uint8_t GPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +}; + +// GPRNoX0 Register Class... +static const MCPhysReg GPRNoX0[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, + RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, + RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, + RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, + RISCV_X2, RISCV_X3, RISCV_X4, +}; + +// GPRNoX0 Bit set. +static const uint8_t GPRNoX0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, +}; + +// GPRNoX0X2 Register Class... +static const MCPhysReg GPRNoX0X2[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, + RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, + RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, + RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, + RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X3, RISCV_X4, +}; + +// GPRNoX0X2 Bit set. +static const uint8_t GPRNoX0X2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0xff, 0xff, 0xff, +}; + +// GPRJALR Register Class... +static const MCPhysReg GPRJALR[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, + RISCV_X17, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, + RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, + RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, +}; + +// GPRJALR Bit set. +static const uint8_t GPRJALRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, +}; + +// GPRTC Register Class... +static const MCPhysReg GPRTC[] = { + RISCV_X6, RISCV_X7, RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, + RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, +}; + +// GPRTC Bit set. +static const uint8_t GPRTCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xfc, 0x03, 0xf0, +}; + +// AnyReg_with_sub_16_with_sub_32_in_FPR32C Register Class... +static const MCPhysReg AnyReg_with_sub_16_with_sub_32_in_FPR32C[] = { + RISCV_F8_D, RISCV_F9_D, RISCV_F10_D, RISCV_F11_D, + RISCV_F12_D, RISCV_F13_D, RISCV_F14_D, RISCV_F15_D, +}; + +// AnyReg_with_sub_16_with_sub_32_in_FPR32C Bit set. +static const uint8_t AnyReg_with_sub_16_with_sub_32_in_FPR32CBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, +}; + +// FPR32C Register Class... +static const MCPhysReg FPR32C[] = { + RISCV_F10_F, RISCV_F11_F, RISCV_F12_F, RISCV_F13_F, + RISCV_F14_F, RISCV_F15_F, RISCV_F8_F, RISCV_F9_F, +}; + +// FPR32C Bit set. +static const uint8_t FPR32CBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, +}; + +// GPRC Register Class... +static const MCPhysReg GPRC[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, + RISCV_X14, RISCV_X15, RISCV_X8, RISCV_X9, +}; + +// GPRC Bit set. +static const uint8_t GPRCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, +}; + +// GPRC_and_GPRTC Register Class... +static const MCPhysReg GPRC_and_GPRTC[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, +}; + +// GPRC_and_GPRTC Bit set. +static const uint8_t GPRC_and_GPRTCBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, +}; + +// GPRX0 Register Class... +static const MCPhysReg GPRX0[] = { + RISCV_X0, +}; + +// GPRX0 Bit set. +static const uint8_t GPRX0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, +}; + +// SP Register Class... +static const MCPhysReg SP[] = { + RISCV_X2, +}; + +// SP Bit set. +static const uint8_t SPBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, +}; + +// FPR64 Register Class... +static const MCPhysReg FPR64[] = { + RISCV_F0_D, RISCV_F1_D, RISCV_F2_D, RISCV_F3_D, RISCV_F4_D, + RISCV_F5_D, RISCV_F6_D, RISCV_F7_D, RISCV_F10_D, RISCV_F11_D, + RISCV_F12_D, RISCV_F13_D, RISCV_F14_D, RISCV_F15_D, RISCV_F16_D, + RISCV_F17_D, RISCV_F28_D, RISCV_F29_D, RISCV_F30_D, RISCV_F31_D, + RISCV_F8_D, RISCV_F9_D, RISCV_F18_D, RISCV_F19_D, RISCV_F20_D, + RISCV_F21_D, RISCV_F22_D, RISCV_F23_D, RISCV_F24_D, RISCV_F25_D, + RISCV_F26_D, RISCV_F27_D, +}; + +// FPR64 Bit set. +static const uint8_t FPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +}; + +// VM Register Class... +static const MCPhysReg VM[] = { + RISCV_V8, RISCV_V9, RISCV_V10, RISCV_V11, RISCV_V12, RISCV_V13, RISCV_V14, + RISCV_V15, RISCV_V16, RISCV_V17, RISCV_V18, RISCV_V19, RISCV_V20, RISCV_V21, + RISCV_V22, RISCV_V23, RISCV_V24, RISCV_V25, RISCV_V26, RISCV_V27, RISCV_V28, + RISCV_V29, RISCV_V30, RISCV_V31, RISCV_V0, RISCV_V1, RISCV_V2, RISCV_V3, + RISCV_V4, RISCV_V5, RISCV_V6, RISCV_V7, +}; + +// VM Bit set. +static const uint8_t VMBits[] = { + 0x00, 0xff, 0xff, 0xff, 0xff, +}; + +// VR Register Class... +static const MCPhysReg VR[] = { + RISCV_V8, RISCV_V9, RISCV_V10, RISCV_V11, RISCV_V12, RISCV_V13, RISCV_V14, + RISCV_V15, RISCV_V16, RISCV_V17, RISCV_V18, RISCV_V19, RISCV_V20, RISCV_V21, + RISCV_V22, RISCV_V23, RISCV_V24, RISCV_V25, RISCV_V26, RISCV_V27, RISCV_V28, + RISCV_V29, RISCV_V30, RISCV_V31, RISCV_V0, RISCV_V1, RISCV_V2, RISCV_V3, + RISCV_V4, RISCV_V5, RISCV_V6, RISCV_V7, +}; + +// VR Bit set. +static const uint8_t VRBits[] = { + 0x00, 0xff, 0xff, 0xff, 0xff, +}; + +// VRNoV0 Register Class... +static const MCPhysReg VRNoV0[] = { + RISCV_V8, RISCV_V9, RISCV_V10, RISCV_V11, RISCV_V12, RISCV_V13, RISCV_V14, + RISCV_V15, RISCV_V16, RISCV_V17, RISCV_V18, RISCV_V19, RISCV_V20, RISCV_V21, + RISCV_V22, RISCV_V23, RISCV_V24, RISCV_V25, RISCV_V26, RISCV_V27, RISCV_V28, + RISCV_V29, RISCV_V30, RISCV_V31, RISCV_V1, RISCV_V2, RISCV_V3, RISCV_V4, + RISCV_V5, RISCV_V6, RISCV_V7, +}; + +// VRNoV0 Bit set. +static const uint8_t VRNoV0Bits[] = { + 0x00, 0xfe, 0xff, 0xff, 0xff, +}; + +// FPR64C Register Class... +static const MCPhysReg FPR64C[] = { + RISCV_F10_D, RISCV_F11_D, RISCV_F12_D, RISCV_F13_D, + RISCV_F14_D, RISCV_F15_D, RISCV_F8_D, RISCV_F9_D, +}; + +// FPR64C Bit set. +static const uint8_t FPR64CBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, +}; + +// VMV0 Register Class... +static const MCPhysReg VMV0[] = { + RISCV_V0, +}; + +// VMV0 Bit set. +static const uint8_t VMV0Bits[] = { + 0x00, + 0x01, +}; + +// VRN2M1 Register Class... +static const MCPhysReg VRN2M1[] = { + RISCV_V8_V9, RISCV_V9_V10, RISCV_V10_V11, RISCV_V11_V12, RISCV_V12_V13, + RISCV_V13_V14, RISCV_V14_V15, RISCV_V15_V16, RISCV_V16_V17, RISCV_V17_V18, + RISCV_V18_V19, RISCV_V19_V20, RISCV_V20_V21, RISCV_V21_V22, RISCV_V22_V23, + RISCV_V23_V24, RISCV_V24_V25, RISCV_V25_V26, RISCV_V26_V27, RISCV_V27_V28, + RISCV_V28_V29, RISCV_V29_V30, RISCV_V30_V31, RISCV_V1_V2, RISCV_V2_V3, + RISCV_V3_V4, RISCV_V4_V5, RISCV_V5_V6, RISCV_V6_V7, RISCV_V7_V8, + RISCV_V0_V1, +}; + +// VRN2M1 Bit set. +static const uint8_t VRN2M1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07, +}; + +// VRN2M1NoV0 Register Class... +static const MCPhysReg VRN2M1NoV0[] = { + RISCV_V8_V9, RISCV_V9_V10, RISCV_V10_V11, RISCV_V11_V12, RISCV_V12_V13, + RISCV_V13_V14, RISCV_V14_V15, RISCV_V15_V16, RISCV_V16_V17, RISCV_V17_V18, + RISCV_V18_V19, RISCV_V19_V20, RISCV_V20_V21, RISCV_V21_V22, RISCV_V22_V23, + RISCV_V23_V24, RISCV_V24_V25, RISCV_V25_V26, RISCV_V26_V27, RISCV_V27_V28, + RISCV_V28_V29, RISCV_V29_V30, RISCV_V30_V31, RISCV_V1_V2, RISCV_V2_V3, + RISCV_V3_V4, RISCV_V4_V5, RISCV_V5_V6, RISCV_V6_V7, RISCV_V7_V8, +}; + +// VRN2M1NoV0 Bit set. +static const uint8_t VRN2M1NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x03, +}; + +// VRM2 Register Class... +static const MCPhysReg VRM2[] = { + RISCV_V8M2, RISCV_V10M2, RISCV_V12M2, RISCV_V14M2, + RISCV_V16M2, RISCV_V18M2, RISCV_V20M2, RISCV_V22M2, + RISCV_V24M2, RISCV_V26M2, RISCV_V28M2, RISCV_V30M2, + RISCV_V0M2, RISCV_V2M2, RISCV_V4M2, RISCV_V6M2, +}; + +// VRM2 Bit set. +static const uint8_t VRM2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xd9, 0x6c, 0x36, 0x0b, +}; + +// VRM2NoV0 Register Class... +static const MCPhysReg VRM2NoV0[] = { + RISCV_V8M2, RISCV_V10M2, RISCV_V12M2, RISCV_V14M2, RISCV_V16M2, + RISCV_V18M2, RISCV_V20M2, RISCV_V22M2, RISCV_V24M2, RISCV_V26M2, + RISCV_V28M2, RISCV_V30M2, RISCV_V2M2, RISCV_V4M2, RISCV_V6M2, +}; + +// VRM2NoV0 Bit set. +static const uint8_t VRM2NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xd8, 0x6c, 0x36, 0x0b, +}; + +// VRM2_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRM2_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0M2, +}; + +// VRM2_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRM2_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, +}; + +// VRN2M1_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN2M1_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0_V1, +}; + +// VRN2M1_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN2M1_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, +}; + +// VRN3M1 Register Class... +static const MCPhysReg VRN3M1[] = { + RISCV_V8_V9_V10, RISCV_V9_V10_V11, RISCV_V10_V11_V12, RISCV_V11_V12_V13, + RISCV_V12_V13_V14, RISCV_V13_V14_V15, RISCV_V14_V15_V16, RISCV_V15_V16_V17, + RISCV_V16_V17_V18, RISCV_V17_V18_V19, RISCV_V18_V19_V20, RISCV_V19_V20_V21, + RISCV_V20_V21_V22, RISCV_V21_V22_V23, RISCV_V22_V23_V24, RISCV_V23_V24_V25, + RISCV_V24_V25_V26, RISCV_V25_V26_V27, RISCV_V26_V27_V28, RISCV_V27_V28_V29, + RISCV_V28_V29_V30, RISCV_V29_V30_V31, RISCV_V1_V2_V3, RISCV_V2_V3_V4, + RISCV_V3_V4_V5, RISCV_V4_V5_V6, RISCV_V5_V6_V7, RISCV_V6_V7_V8, + RISCV_V7_V8_V9, RISCV_V0_V1_V2, +}; + +// VRN3M1 Bit set. +static const uint8_t VRN3M1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x7f, +}; + +// VRN3M1NoV0 Register Class... +static const MCPhysReg VRN3M1NoV0[] = { + RISCV_V8_V9_V10, RISCV_V9_V10_V11, RISCV_V10_V11_V12, RISCV_V11_V12_V13, + RISCV_V12_V13_V14, RISCV_V13_V14_V15, RISCV_V14_V15_V16, RISCV_V15_V16_V17, + RISCV_V16_V17_V18, RISCV_V17_V18_V19, RISCV_V18_V19_V20, RISCV_V19_V20_V21, + RISCV_V20_V21_V22, RISCV_V21_V22_V23, RISCV_V22_V23_V24, RISCV_V23_V24_V25, + RISCV_V24_V25_V26, RISCV_V25_V26_V27, RISCV_V26_V27_V28, RISCV_V27_V28_V29, + RISCV_V28_V29_V30, RISCV_V29_V30_V31, RISCV_V1_V2_V3, RISCV_V2_V3_V4, + RISCV_V3_V4_V5, RISCV_V4_V5_V6, RISCV_V5_V6_V7, RISCV_V6_V7_V8, + RISCV_V7_V8_V9, +}; + +// VRN3M1NoV0 Bit set. +static const uint8_t VRN3M1NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x3f, +}; + +// VRN3M1_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN3M1_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0_V1_V2, +}; + +// VRN3M1_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN3M1_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, +}; + +// VRN4M1 Register Class... +static const MCPhysReg VRN4M1[] = { + RISCV_V8_V9_V10_V11, RISCV_V9_V10_V11_V12, RISCV_V10_V11_V12_V13, + RISCV_V11_V12_V13_V14, RISCV_V12_V13_V14_V15, RISCV_V13_V14_V15_V16, + RISCV_V14_V15_V16_V17, RISCV_V15_V16_V17_V18, RISCV_V16_V17_V18_V19, + RISCV_V17_V18_V19_V20, RISCV_V18_V19_V20_V21, RISCV_V19_V20_V21_V22, + RISCV_V20_V21_V22_V23, RISCV_V21_V22_V23_V24, RISCV_V22_V23_V24_V25, + RISCV_V23_V24_V25_V26, RISCV_V24_V25_V26_V27, RISCV_V25_V26_V27_V28, + RISCV_V26_V27_V28_V29, RISCV_V27_V28_V29_V30, RISCV_V28_V29_V30_V31, + RISCV_V1_V2_V3_V4, RISCV_V2_V3_V4_V5, RISCV_V3_V4_V5_V6, + RISCV_V4_V5_V6_V7, RISCV_V5_V6_V7_V8, RISCV_V6_V7_V8_V9, + RISCV_V7_V8_V9_V10, RISCV_V0_V1_V2_V3, +}; + +// VRN4M1 Bit set. +static const uint8_t VRN4M1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x03, +}; + +// VRN4M1NoV0 Register Class... +static const MCPhysReg VRN4M1NoV0[] = { + RISCV_V8_V9_V10_V11, RISCV_V9_V10_V11_V12, RISCV_V10_V11_V12_V13, + RISCV_V11_V12_V13_V14, RISCV_V12_V13_V14_V15, RISCV_V13_V14_V15_V16, + RISCV_V14_V15_V16_V17, RISCV_V15_V16_V17_V18, RISCV_V16_V17_V18_V19, + RISCV_V17_V18_V19_V20, RISCV_V18_V19_V20_V21, RISCV_V19_V20_V21_V22, + RISCV_V20_V21_V22_V23, RISCV_V21_V22_V23_V24, RISCV_V22_V23_V24_V25, + RISCV_V23_V24_V25_V26, RISCV_V24_V25_V26_V27, RISCV_V25_V26_V27_V28, + RISCV_V26_V27_V28_V29, RISCV_V27_V28_V29_V30, RISCV_V28_V29_V30_V31, + RISCV_V1_V2_V3_V4, RISCV_V2_V3_V4_V5, RISCV_V3_V4_V5_V6, + RISCV_V4_V5_V6_V7, RISCV_V5_V6_V7_V8, RISCV_V6_V7_V8_V9, + RISCV_V7_V8_V9_V10, +}; + +// VRN4M1NoV0 Bit set. +static const uint8_t VRN4M1NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x01, +}; + +// VRN2M2 Register Class... +static const MCPhysReg VRN2M2[] = { + RISCV_V8M2_V10M2, RISCV_V10M2_V12M2, RISCV_V12M2_V14M2, RISCV_V14M2_V16M2, + RISCV_V16M2_V18M2, RISCV_V18M2_V20M2, RISCV_V20M2_V22M2, RISCV_V22M2_V24M2, + RISCV_V24M2_V26M2, RISCV_V26M2_V28M2, RISCV_V28M2_V30M2, RISCV_V2M2_V4M2, + RISCV_V4M2_V6M2, RISCV_V6M2_V8M2, RISCV_V0M2_V2M2, +}; + +// VRN2M2 Bit set. +static const uint8_t VRN2M2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, +}; + +// VRN2M2NoV0 Register Class... +static const MCPhysReg VRN2M2NoV0[] = { + RISCV_V8M2_V10M2, RISCV_V10M2_V12M2, RISCV_V12M2_V14M2, RISCV_V14M2_V16M2, + RISCV_V16M2_V18M2, RISCV_V18M2_V20M2, RISCV_V20M2_V22M2, RISCV_V22M2_V24M2, + RISCV_V24M2_V26M2, RISCV_V26M2_V28M2, RISCV_V28M2_V30M2, RISCV_V2M2_V4M2, + RISCV_V4M2_V6M2, RISCV_V6M2_V8M2, +}; + +// VRN2M2NoV0 Bit set. +static const uint8_t VRN2M2NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, +}; + +// VRM4 Register Class... +static const MCPhysReg VRM4[] = { + RISCV_V8M4, RISCV_V12M4, RISCV_V16M4, RISCV_V20M4, + RISCV_V24M4, RISCV_V28M4, RISCV_V0M4, RISCV_V4M4, +}; + +// VRM4 Bit set. +static const uint8_t VRM4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x22, 0x91, 0x48, 0x04, +}; + +// VRM4NoV0 Register Class... +static const MCPhysReg VRM4NoV0[] = { + RISCV_V8M4, RISCV_V12M4, RISCV_V16M4, RISCV_V20M4, + RISCV_V24M4, RISCV_V28M4, RISCV_V4M4, +}; + +// VRM4NoV0 Bit set. +static const uint8_t VRM4NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x20, 0x91, 0x48, 0x04, +}; + +// VRM4_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRM4_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0M4, +}; + +// VRM4_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRM4_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, +}; + +// VRN2M2_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN2M2_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0M2_V2M2, +}; + +// VRN2M2_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN2M2_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, +}; + +// VRN4M1_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN4M1_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0_V1_V2_V3, +}; + +// VRN4M1_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN4M1_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, +}; + +// VRN5M1 Register Class... +static const MCPhysReg VRN5M1[] = { + RISCV_V8_V9_V10_V11_V12, RISCV_V9_V10_V11_V12_V13, + RISCV_V10_V11_V12_V13_V14, RISCV_V11_V12_V13_V14_V15, + RISCV_V12_V13_V14_V15_V16, RISCV_V13_V14_V15_V16_V17, + RISCV_V14_V15_V16_V17_V18, RISCV_V15_V16_V17_V18_V19, + RISCV_V16_V17_V18_V19_V20, RISCV_V17_V18_V19_V20_V21, + RISCV_V18_V19_V20_V21_V22, RISCV_V19_V20_V21_V22_V23, + RISCV_V20_V21_V22_V23_V24, RISCV_V21_V22_V23_V24_V25, + RISCV_V22_V23_V24_V25_V26, RISCV_V23_V24_V25_V26_V27, + RISCV_V24_V25_V26_V27_V28, RISCV_V25_V26_V27_V28_V29, + RISCV_V26_V27_V28_V29_V30, RISCV_V27_V28_V29_V30_V31, + RISCV_V1_V2_V3_V4_V5, RISCV_V2_V3_V4_V5_V6, + RISCV_V3_V4_V5_V6_V7, RISCV_V4_V5_V6_V7_V8, + RISCV_V5_V6_V7_V8_V9, RISCV_V6_V7_V8_V9_V10, + RISCV_V7_V8_V9_V10_V11, RISCV_V0_V1_V2_V3_V4, +}; + +// VRN5M1 Bit set. +static const uint8_t VRN5M1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x07, +}; + +// VRN5M1NoV0 Register Class... +static const MCPhysReg VRN5M1NoV0[] = { + RISCV_V8_V9_V10_V11_V12, RISCV_V9_V10_V11_V12_V13, + RISCV_V10_V11_V12_V13_V14, RISCV_V11_V12_V13_V14_V15, + RISCV_V12_V13_V14_V15_V16, RISCV_V13_V14_V15_V16_V17, + RISCV_V14_V15_V16_V17_V18, RISCV_V15_V16_V17_V18_V19, + RISCV_V16_V17_V18_V19_V20, RISCV_V17_V18_V19_V20_V21, + RISCV_V18_V19_V20_V21_V22, RISCV_V19_V20_V21_V22_V23, + RISCV_V20_V21_V22_V23_V24, RISCV_V21_V22_V23_V24_V25, + RISCV_V22_V23_V24_V25_V26, RISCV_V23_V24_V25_V26_V27, + RISCV_V24_V25_V26_V27_V28, RISCV_V25_V26_V27_V28_V29, + RISCV_V26_V27_V28_V29_V30, RISCV_V27_V28_V29_V30_V31, + RISCV_V1_V2_V3_V4_V5, RISCV_V2_V3_V4_V5_V6, + RISCV_V3_V4_V5_V6_V7, RISCV_V4_V5_V6_V7_V8, + RISCV_V5_V6_V7_V8_V9, RISCV_V6_V7_V8_V9_V10, + RISCV_V7_V8_V9_V10_V11, +}; + +// VRN5M1NoV0 Bit set. +static const uint8_t VRN5M1NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x03, +}; + +// VRN5M1_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN5M1_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0_V1_V2_V3_V4, +}; + +// VRN5M1_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN5M1_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, +}; + +// VRN6M1 Register Class... +static const MCPhysReg VRN6M1[] = { + RISCV_V8_V9_V10_V11_V12_V13, RISCV_V9_V10_V11_V12_V13_V14, + RISCV_V10_V11_V12_V13_V14_V15, RISCV_V11_V12_V13_V14_V15_V16, + RISCV_V12_V13_V14_V15_V16_V17, RISCV_V13_V14_V15_V16_V17_V18, + RISCV_V14_V15_V16_V17_V18_V19, RISCV_V15_V16_V17_V18_V19_V20, + RISCV_V16_V17_V18_V19_V20_V21, RISCV_V17_V18_V19_V20_V21_V22, + RISCV_V18_V19_V20_V21_V22_V23, RISCV_V19_V20_V21_V22_V23_V24, + RISCV_V20_V21_V22_V23_V24_V25, RISCV_V21_V22_V23_V24_V25_V26, + RISCV_V22_V23_V24_V25_V26_V27, RISCV_V23_V24_V25_V26_V27_V28, + RISCV_V24_V25_V26_V27_V28_V29, RISCV_V25_V26_V27_V28_V29_V30, + RISCV_V26_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5_V6, + RISCV_V2_V3_V4_V5_V6_V7, RISCV_V3_V4_V5_V6_V7_V8, + RISCV_V4_V5_V6_V7_V8_V9, RISCV_V5_V6_V7_V8_V9_V10, + RISCV_V6_V7_V8_V9_V10_V11, RISCV_V7_V8_V9_V10_V11_V12, + RISCV_V0_V1_V2_V3_V4_V5, +}; + +// VRN6M1 Bit set. +static const uint8_t VRN6M1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x3f, +}; + +// VRN6M1NoV0 Register Class... +static const MCPhysReg VRN6M1NoV0[] = { + RISCV_V8_V9_V10_V11_V12_V13, RISCV_V9_V10_V11_V12_V13_V14, + RISCV_V10_V11_V12_V13_V14_V15, RISCV_V11_V12_V13_V14_V15_V16, + RISCV_V12_V13_V14_V15_V16_V17, RISCV_V13_V14_V15_V16_V17_V18, + RISCV_V14_V15_V16_V17_V18_V19, RISCV_V15_V16_V17_V18_V19_V20, + RISCV_V16_V17_V18_V19_V20_V21, RISCV_V17_V18_V19_V20_V21_V22, + RISCV_V18_V19_V20_V21_V22_V23, RISCV_V19_V20_V21_V22_V23_V24, + RISCV_V20_V21_V22_V23_V24_V25, RISCV_V21_V22_V23_V24_V25_V26, + RISCV_V22_V23_V24_V25_V26_V27, RISCV_V23_V24_V25_V26_V27_V28, + RISCV_V24_V25_V26_V27_V28_V29, RISCV_V25_V26_V27_V28_V29_V30, + RISCV_V26_V27_V28_V29_V30_V31, RISCV_V1_V2_V3_V4_V5_V6, + RISCV_V2_V3_V4_V5_V6_V7, RISCV_V3_V4_V5_V6_V7_V8, + RISCV_V4_V5_V6_V7_V8_V9, RISCV_V5_V6_V7_V8_V9_V10, + RISCV_V6_V7_V8_V9_V10_V11, RISCV_V7_V8_V9_V10_V11_V12, +}; + +// VRN6M1NoV0 Bit set. +static const uint8_t VRN6M1NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x1f, +}; + +// VRN3M2 Register Class... +static const MCPhysReg VRN3M2[] = { + RISCV_V8M2_V10M2_V12M2, RISCV_V10M2_V12M2_V14M2, RISCV_V12M2_V14M2_V16M2, + RISCV_V14M2_V16M2_V18M2, RISCV_V16M2_V18M2_V20M2, RISCV_V18M2_V20M2_V22M2, + RISCV_V20M2_V22M2_V24M2, RISCV_V22M2_V24M2_V26M2, RISCV_V24M2_V26M2_V28M2, + RISCV_V26M2_V28M2_V30M2, RISCV_V2M2_V4M2_V6M2, RISCV_V4M2_V6M2_V8M2, + RISCV_V6M2_V8M2_V10M2, RISCV_V0M2_V2M2_V4M2, +}; + +// VRN3M2 Bit set. +static const uint8_t VRN3M2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, +}; + +// VRN3M2NoV0 Register Class... +static const MCPhysReg VRN3M2NoV0[] = { + RISCV_V8M2_V10M2_V12M2, RISCV_V10M2_V12M2_V14M2, RISCV_V12M2_V14M2_V16M2, + RISCV_V14M2_V16M2_V18M2, RISCV_V16M2_V18M2_V20M2, RISCV_V18M2_V20M2_V22M2, + RISCV_V20M2_V22M2_V24M2, RISCV_V22M2_V24M2_V26M2, RISCV_V24M2_V26M2_V28M2, + RISCV_V26M2_V28M2_V30M2, RISCV_V2M2_V4M2_V6M2, RISCV_V4M2_V6M2_V8M2, + RISCV_V6M2_V8M2_V10M2, +}; + +// VRN3M2NoV0 Bit set. +static const uint8_t VRN3M2NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x0f, +}; + +// VRN3M2_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN3M2_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0M2_V2M2_V4M2, +}; + +// VRN3M2_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN3M2_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, +}; + +// VRN6M1_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN6M1_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0_V1_V2_V3_V4_V5, +}; + +// VRN6M1_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN6M1_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, +}; + +// VRN7M1 Register Class... +static const MCPhysReg VRN7M1[] = { + RISCV_V8_V9_V10_V11_V12_V13_V14, RISCV_V9_V10_V11_V12_V13_V14_V15, + RISCV_V10_V11_V12_V13_V14_V15_V16, RISCV_V11_V12_V13_V14_V15_V16_V17, + RISCV_V12_V13_V14_V15_V16_V17_V18, RISCV_V13_V14_V15_V16_V17_V18_V19, + RISCV_V14_V15_V16_V17_V18_V19_V20, RISCV_V15_V16_V17_V18_V19_V20_V21, + RISCV_V16_V17_V18_V19_V20_V21_V22, RISCV_V17_V18_V19_V20_V21_V22_V23, + RISCV_V18_V19_V20_V21_V22_V23_V24, RISCV_V19_V20_V21_V22_V23_V24_V25, + RISCV_V20_V21_V22_V23_V24_V25_V26, RISCV_V21_V22_V23_V24_V25_V26_V27, + RISCV_V22_V23_V24_V25_V26_V27_V28, RISCV_V23_V24_V25_V26_V27_V28_V29, + RISCV_V24_V25_V26_V27_V28_V29_V30, RISCV_V25_V26_V27_V28_V29_V30_V31, + RISCV_V1_V2_V3_V4_V5_V6_V7, RISCV_V2_V3_V4_V5_V6_V7_V8, + RISCV_V3_V4_V5_V6_V7_V8_V9, RISCV_V4_V5_V6_V7_V8_V9_V10, + RISCV_V5_V6_V7_V8_V9_V10_V11, RISCV_V6_V7_V8_V9_V10_V11_V12, + RISCV_V7_V8_V9_V10_V11_V12_V13, RISCV_V0_V1_V2_V3_V4_V5_V6, +}; + +// VRN7M1 Bit set. +static const uint8_t VRN7M1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, +}; + +// VRN7M1NoV0 Register Class... +static const MCPhysReg VRN7M1NoV0[] = { + RISCV_V8_V9_V10_V11_V12_V13_V14, RISCV_V9_V10_V11_V12_V13_V14_V15, + RISCV_V10_V11_V12_V13_V14_V15_V16, RISCV_V11_V12_V13_V14_V15_V16_V17, + RISCV_V12_V13_V14_V15_V16_V17_V18, RISCV_V13_V14_V15_V16_V17_V18_V19, + RISCV_V14_V15_V16_V17_V18_V19_V20, RISCV_V15_V16_V17_V18_V19_V20_V21, + RISCV_V16_V17_V18_V19_V20_V21_V22, RISCV_V17_V18_V19_V20_V21_V22_V23, + RISCV_V18_V19_V20_V21_V22_V23_V24, RISCV_V19_V20_V21_V22_V23_V24_V25, + RISCV_V20_V21_V22_V23_V24_V25_V26, RISCV_V21_V22_V23_V24_V25_V26_V27, + RISCV_V22_V23_V24_V25_V26_V27_V28, RISCV_V23_V24_V25_V26_V27_V28_V29, + RISCV_V24_V25_V26_V27_V28_V29_V30, RISCV_V25_V26_V27_V28_V29_V30_V31, + RISCV_V1_V2_V3_V4_V5_V6_V7, RISCV_V2_V3_V4_V5_V6_V7_V8, + RISCV_V3_V4_V5_V6_V7_V8_V9, RISCV_V4_V5_V6_V7_V8_V9_V10, + RISCV_V5_V6_V7_V8_V9_V10_V11, RISCV_V6_V7_V8_V9_V10_V11_V12, + RISCV_V7_V8_V9_V10_V11_V12_V13, +}; + +// VRN7M1NoV0 Bit set. +static const uint8_t VRN7M1NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0x7f, +}; + +// VRN7M1_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN7M1_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0_V1_V2_V3_V4_V5_V6, +}; + +// VRN7M1_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN7M1_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, +}; + +// VRN8M1 Register Class... +static const MCPhysReg VRN8M1[] = { + RISCV_V8_V9_V10_V11_V12_V13_V14_V15, + RISCV_V9_V10_V11_V12_V13_V14_V15_V16, + RISCV_V10_V11_V12_V13_V14_V15_V16_V17, + RISCV_V11_V12_V13_V14_V15_V16_V17_V18, + RISCV_V12_V13_V14_V15_V16_V17_V18_V19, + RISCV_V13_V14_V15_V16_V17_V18_V19_V20, + RISCV_V14_V15_V16_V17_V18_V19_V20_V21, + RISCV_V15_V16_V17_V18_V19_V20_V21_V22, + RISCV_V16_V17_V18_V19_V20_V21_V22_V23, + RISCV_V17_V18_V19_V20_V21_V22_V23_V24, + RISCV_V18_V19_V20_V21_V22_V23_V24_V25, + RISCV_V19_V20_V21_V22_V23_V24_V25_V26, + RISCV_V20_V21_V22_V23_V24_V25_V26_V27, + RISCV_V21_V22_V23_V24_V25_V26_V27_V28, + RISCV_V22_V23_V24_V25_V26_V27_V28_V29, + RISCV_V23_V24_V25_V26_V27_V28_V29_V30, + RISCV_V24_V25_V26_V27_V28_V29_V30_V31, + RISCV_V1_V2_V3_V4_V5_V6_V7_V8, + RISCV_V2_V3_V4_V5_V6_V7_V8_V9, + RISCV_V3_V4_V5_V6_V7_V8_V9_V10, + RISCV_V4_V5_V6_V7_V8_V9_V10_V11, + RISCV_V5_V6_V7_V8_V9_V10_V11_V12, + RISCV_V6_V7_V8_V9_V10_V11_V12_V13, + RISCV_V7_V8_V9_V10_V11_V12_V13_V14, + RISCV_V0_V1_V2_V3_V4_V5_V6_V7, +}; + +// VRN8M1 Bit set. +static const uint8_t VRN8M1Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x01, +}; + +// VRN8M1NoV0 Register Class... +static const MCPhysReg VRN8M1NoV0[] = { + RISCV_V8_V9_V10_V11_V12_V13_V14_V15, + RISCV_V9_V10_V11_V12_V13_V14_V15_V16, + RISCV_V10_V11_V12_V13_V14_V15_V16_V17, + RISCV_V11_V12_V13_V14_V15_V16_V17_V18, + RISCV_V12_V13_V14_V15_V16_V17_V18_V19, + RISCV_V13_V14_V15_V16_V17_V18_V19_V20, + RISCV_V14_V15_V16_V17_V18_V19_V20_V21, + RISCV_V15_V16_V17_V18_V19_V20_V21_V22, + RISCV_V16_V17_V18_V19_V20_V21_V22_V23, + RISCV_V17_V18_V19_V20_V21_V22_V23_V24, + RISCV_V18_V19_V20_V21_V22_V23_V24_V25, + RISCV_V19_V20_V21_V22_V23_V24_V25_V26, + RISCV_V20_V21_V22_V23_V24_V25_V26_V27, + RISCV_V21_V22_V23_V24_V25_V26_V27_V28, + RISCV_V22_V23_V24_V25_V26_V27_V28_V29, + RISCV_V23_V24_V25_V26_V27_V28_V29_V30, + RISCV_V24_V25_V26_V27_V28_V29_V30_V31, + RISCV_V1_V2_V3_V4_V5_V6_V7_V8, + RISCV_V2_V3_V4_V5_V6_V7_V8_V9, + RISCV_V3_V4_V5_V6_V7_V8_V9_V10, + RISCV_V4_V5_V6_V7_V8_V9_V10_V11, + RISCV_V5_V6_V7_V8_V9_V10_V11_V12, + RISCV_V6_V7_V8_V9_V10_V11_V12_V13, + RISCV_V7_V8_V9_V10_V11_V12_V13_V14, +}; + +// VRN8M1NoV0 Bit set. +static const uint8_t VRN8M1NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, +}; + +// VRN4M2 Register Class... +static const MCPhysReg VRN4M2[] = { + RISCV_V8M2_V10M2_V12M2_V14M2, RISCV_V10M2_V12M2_V14M2_V16M2, + RISCV_V12M2_V14M2_V16M2_V18M2, RISCV_V14M2_V16M2_V18M2_V20M2, + RISCV_V16M2_V18M2_V20M2_V22M2, RISCV_V18M2_V20M2_V22M2_V24M2, + RISCV_V20M2_V22M2_V24M2_V26M2, RISCV_V22M2_V24M2_V26M2_V28M2, + RISCV_V24M2_V26M2_V28M2_V30M2, RISCV_V2M2_V4M2_V6M2_V8M2, + RISCV_V4M2_V6M2_V8M2_V10M2, RISCV_V6M2_V8M2_V10M2_V12M2, + RISCV_V0M2_V2M2_V4M2_V6M2, +}; + +// VRN4M2 Bit set. +static const uint8_t VRN4M2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, +}; + +// VRN4M2NoV0 Register Class... +static const MCPhysReg VRN4M2NoV0[] = { + RISCV_V8M2_V10M2_V12M2_V14M2, RISCV_V10M2_V12M2_V14M2_V16M2, + RISCV_V12M2_V14M2_V16M2_V18M2, RISCV_V14M2_V16M2_V18M2_V20M2, + RISCV_V16M2_V18M2_V20M2_V22M2, RISCV_V18M2_V20M2_V22M2_V24M2, + RISCV_V20M2_V22M2_V24M2_V26M2, RISCV_V22M2_V24M2_V26M2_V28M2, + RISCV_V24M2_V26M2_V28M2_V30M2, RISCV_V2M2_V4M2_V6M2_V8M2, + RISCV_V4M2_V6M2_V8M2_V10M2, RISCV_V6M2_V8M2_V10M2_V12M2, +}; + +// VRN4M2NoV0 Bit set. +static const uint8_t VRN4M2NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3f, +}; + +// VRN2M4 Register Class... +static const MCPhysReg VRN2M4[] = { + RISCV_V8M4_V12M4, RISCV_V12M4_V16M4, RISCV_V16M4_V20M4, RISCV_V20M4_V24M4, + RISCV_V24M4_V28M4, RISCV_V4M4_V8M4, RISCV_V0M4_V4M4, +}; + +// VRN2M4 Bit set. +static const uint8_t VRN2M4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, +}; + +// VRN2M4NoV0 Register Class... +static const MCPhysReg VRN2M4NoV0[] = { + RISCV_V8M4_V12M4, RISCV_V12M4_V16M4, RISCV_V16M4_V20M4, + RISCV_V20M4_V24M4, RISCV_V24M4_V28M4, RISCV_V4M4_V8M4, +}; + +// VRN2M4NoV0 Bit set. +static const uint8_t VRN2M4NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, +}; + +// VRM8 Register Class... +static const MCPhysReg VRM8[] = { + RISCV_V8M8, + RISCV_V16M8, + RISCV_V24M8, + RISCV_V0M8, +}; + +// VRM8 Bit set. +static const uint8_t VRM8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x02, 0x81, +}; + +// VRM8NoV0 Register Class... +static const MCPhysReg VRM8NoV0[] = { + RISCV_V8M8, + RISCV_V16M8, + RISCV_V24M8, +}; + +// VRM8NoV0 Bit set. +static const uint8_t VRM8NoV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x81, +}; + +// VRM8_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRM8_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0M8, +}; + +// VRM8_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRM8_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, +}; + +// VRN2M4_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN2M4_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0M4_V4M4, +}; + +// VRN2M4_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN2M4_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, +}; + +// VRN4M2_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN4M2_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0M2_V2M2_V4M2_V6M2, +}; + +// VRN4M2_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN4M2_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, +}; + +// VRN8M1_with_sub_vrm1_0_in_VMV0 Register Class... +static const MCPhysReg VRN8M1_with_sub_vrm1_0_in_VMV0[] = { + RISCV_V0_V1_V2_V3_V4_V5_V6_V7, +}; + +// VRN8M1_with_sub_vrm1_0_in_VMV0 Bit set. +static const uint8_t VRN8M1_with_sub_vrm1_0_in_VMV0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, +}; + +// end of register classes misc + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char RISCVRegClassStrings[] = { + /* 0 */ "VRN2M1_with_sub_vrm1_0_in_VMV0\0" + /* 31 */ "VRN3M1_with_sub_vrm1_0_in_VMV0\0" + /* 62 */ "VRN4M1_with_sub_vrm1_0_in_VMV0\0" + /* 93 */ "VRN5M1_with_sub_vrm1_0_in_VMV0\0" + /* 124 */ "VRN6M1_with_sub_vrm1_0_in_VMV0\0" + /* 155 */ "VRN7M1_with_sub_vrm1_0_in_VMV0\0" + /* 186 */ "VRN8M1_with_sub_vrm1_0_in_VMV0\0" + /* 217 */ "VRN2M2_with_sub_vrm1_0_in_VMV0\0" + /* 248 */ "VRN3M2_with_sub_vrm1_0_in_VMV0\0" + /* 279 */ "VRN4M2_with_sub_vrm1_0_in_VMV0\0" + /* 310 */ "VRM2_with_sub_vrm1_0_in_VMV0\0" + /* 339 */ "VRN2M4_with_sub_vrm1_0_in_VMV0\0" + /* 370 */ "VRM4_with_sub_vrm1_0_in_VMV0\0" + /* 399 */ "VRM8_with_sub_vrm1_0_in_VMV0\0" + /* 428 */ "VRN2M1NoV0\0" + /* 439 */ "VRN3M1NoV0\0" + /* 450 */ "VRN4M1NoV0\0" + /* 461 */ "VRN5M1NoV0\0" + /* 472 */ "VRN6M1NoV0\0" + /* 483 */ "VRN7M1NoV0\0" + /* 494 */ "VRN8M1NoV0\0" + /* 505 */ "VRN2M2NoV0\0" + /* 516 */ "VRN3M2NoV0\0" + /* 527 */ "VRN4M2NoV0\0" + /* 538 */ "VRM2NoV0\0" + /* 547 */ "VRN2M4NoV0\0" + /* 558 */ "VRM4NoV0\0" + /* 567 */ "VRM8NoV0\0" + /* 576 */ "VRNoV0\0" + /* 583 */ "GPRX0\0" + /* 589 */ "GPRNoX0\0" + /* 597 */ "VRN2M1\0" + /* 604 */ "VRN3M1\0" + /* 611 */ "VRN4M1\0" + /* 618 */ "VRN5M1\0" + /* 625 */ "VRN6M1\0" + /* 632 */ "VRN7M1\0" + /* 639 */ "VRN8M1\0" + /* 646 */ "FPR32\0" + /* 652 */ "VRN2M2\0" + /* 659 */ "VRN3M2\0" + /* 666 */ "VRN4M2\0" + /* 673 */ "VRM2\0" + /* 678 */ "GPRNoX0X2\0" + /* 688 */ "FPR64\0" + /* 694 */ "VRN2M4\0" + /* 701 */ "VRM4\0" + /* 706 */ "FPR16\0" + /* 712 */ "AnyReg_with_sub_16\0" + /* 731 */ "VRM8\0" + /* 736 */ "AnyReg_with_sub_16_with_sub_32_in_FPR32C\0" + /* 777 */ "FPR64C\0" + /* 784 */ "GPRC\0" + /* 789 */ "GPRC_and_GPRTC\0" + /* 804 */ "VM\0" + /* 807 */ "SP\0" + /* 810 */ "GPRJALR\0" + /* 818 */ "GPR\0" + /* 822 */ "VR\0" + /* 825 */ "AnyReg\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterClass RISCVMCRegisterClasses[] = { + {FPR16, FPR16Bits, sizeof(FPR16Bits)}, + {AnyReg, AnyRegBits, sizeof(AnyRegBits)}, + {AnyReg_with_sub_16, AnyReg_with_sub_16Bits, + sizeof(AnyReg_with_sub_16Bits)}, + {FPR32, FPR32Bits, sizeof(FPR32Bits)}, + {GPR, GPRBits, sizeof(GPRBits)}, + {GPRNoX0, GPRNoX0Bits, sizeof(GPRNoX0Bits)}, + {GPRNoX0X2, GPRNoX0X2Bits, sizeof(GPRNoX0X2Bits)}, + {GPRJALR, GPRJALRBits, sizeof(GPRJALRBits)}, + {GPRTC, GPRTCBits, sizeof(GPRTCBits)}, + {AnyReg_with_sub_16_with_sub_32_in_FPR32C, + AnyReg_with_sub_16_with_sub_32_in_FPR32CBits, + sizeof(AnyReg_with_sub_16_with_sub_32_in_FPR32CBits)}, + {FPR32C, FPR32CBits, sizeof(FPR32CBits)}, + {GPRC, GPRCBits, sizeof(GPRCBits)}, + {GPRC_and_GPRTC, GPRC_and_GPRTCBits, sizeof(GPRC_and_GPRTCBits)}, + {GPRX0, GPRX0Bits, sizeof(GPRX0Bits)}, + {SP, SPBits, sizeof(SPBits)}, + {FPR64, FPR64Bits, sizeof(FPR64Bits)}, + {VM, VMBits, sizeof(VMBits)}, + {VR, VRBits, sizeof(VRBits)}, + {VRNoV0, VRNoV0Bits, sizeof(VRNoV0Bits)}, + {FPR64C, FPR64CBits, sizeof(FPR64CBits)}, + {VMV0, VMV0Bits, sizeof(VMV0Bits)}, + {VRN2M1, VRN2M1Bits, sizeof(VRN2M1Bits)}, + {VRN2M1NoV0, VRN2M1NoV0Bits, sizeof(VRN2M1NoV0Bits)}, + {VRM2, VRM2Bits, sizeof(VRM2Bits)}, + {VRM2NoV0, VRM2NoV0Bits, sizeof(VRM2NoV0Bits)}, + {VRM2_with_sub_vrm1_0_in_VMV0, VRM2_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRM2_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN2M1_with_sub_vrm1_0_in_VMV0, VRN2M1_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN2M1_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN3M1, VRN3M1Bits, sizeof(VRN3M1Bits)}, + {VRN3M1NoV0, VRN3M1NoV0Bits, sizeof(VRN3M1NoV0Bits)}, + {VRN3M1_with_sub_vrm1_0_in_VMV0, VRN3M1_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN3M1_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN4M1, VRN4M1Bits, sizeof(VRN4M1Bits)}, + {VRN4M1NoV0, VRN4M1NoV0Bits, sizeof(VRN4M1NoV0Bits)}, + {VRN2M2, VRN2M2Bits, sizeof(VRN2M2Bits)}, + {VRN2M2NoV0, VRN2M2NoV0Bits, sizeof(VRN2M2NoV0Bits)}, + {VRM4, VRM4Bits, sizeof(VRM4Bits)}, + {VRM4NoV0, VRM4NoV0Bits, sizeof(VRM4NoV0Bits)}, + {VRM4_with_sub_vrm1_0_in_VMV0, VRM4_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRM4_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN2M2_with_sub_vrm1_0_in_VMV0, VRN2M2_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN2M2_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN4M1_with_sub_vrm1_0_in_VMV0, VRN4M1_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN4M1_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN5M1, VRN5M1Bits, sizeof(VRN5M1Bits)}, + {VRN5M1NoV0, VRN5M1NoV0Bits, sizeof(VRN5M1NoV0Bits)}, + {VRN5M1_with_sub_vrm1_0_in_VMV0, VRN5M1_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN5M1_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN6M1, VRN6M1Bits, sizeof(VRN6M1Bits)}, + {VRN6M1NoV0, VRN6M1NoV0Bits, sizeof(VRN6M1NoV0Bits)}, + {VRN3M2, VRN3M2Bits, sizeof(VRN3M2Bits)}, + {VRN3M2NoV0, VRN3M2NoV0Bits, sizeof(VRN3M2NoV0Bits)}, + {VRN3M2_with_sub_vrm1_0_in_VMV0, VRN3M2_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN3M2_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN6M1_with_sub_vrm1_0_in_VMV0, VRN6M1_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN6M1_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN7M1, VRN7M1Bits, sizeof(VRN7M1Bits)}, + {VRN7M1NoV0, VRN7M1NoV0Bits, sizeof(VRN7M1NoV0Bits)}, + {VRN7M1_with_sub_vrm1_0_in_VMV0, VRN7M1_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN7M1_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN8M1, VRN8M1Bits, sizeof(VRN8M1Bits)}, + {VRN8M1NoV0, VRN8M1NoV0Bits, sizeof(VRN8M1NoV0Bits)}, + {VRN4M2, VRN4M2Bits, sizeof(VRN4M2Bits)}, + {VRN4M2NoV0, VRN4M2NoV0Bits, sizeof(VRN4M2NoV0Bits)}, + {VRN2M4, VRN2M4Bits, sizeof(VRN2M4Bits)}, + {VRN2M4NoV0, VRN2M4NoV0Bits, sizeof(VRN2M4NoV0Bits)}, + {VRM8, VRM8Bits, sizeof(VRM8Bits)}, + {VRM8NoV0, VRM8NoV0Bits, sizeof(VRM8NoV0Bits)}, + {VRM8_with_sub_vrm1_0_in_VMV0, VRM8_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRM8_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN2M4_with_sub_vrm1_0_in_VMV0, VRN2M4_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN2M4_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN4M2_with_sub_vrm1_0_in_VMV0, VRN4M2_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN4M2_with_sub_vrm1_0_in_VMV0Bits)}, + {VRN8M1_with_sub_vrm1_0_in_VMV0, VRN8M1_with_sub_vrm1_0_in_VMV0Bits, + sizeof(VRN8M1_with_sub_vrm1_0_in_VMV0Bits)}, +}; + +#endif // GET_REGINFO_MC_DESC + +#ifdef GET_ASM_WRITER +#undef GET_ASM_WRITER + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +typedef struct MCMnemonic { + const char *first; + uint64_t second; +} MCMnemonic; + +static MCMnemonic createMnemonic(const char *first, uint64_t second) { + MCMnemonic mnemonic; + mnemonic.first = first; + mnemonic.second = second; + return mnemonic; +} + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +MCMnemonic RISCV_getMnemonic(const MCInst *MI) { + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "vsext.vf2\t\0" + /* 11 */ "vzext.vf2\t\0" + /* 22 */ "c.srai64\t\0" + /* 32 */ "c.slli64\t\0" + /* 42 */ "c.srli64\t\0" + /* 52 */ "vsext.vf4\t\0" + /* 63 */ "vzext.vf4\t\0" + /* 74 */ "vsext.vf8\t\0" + /* 85 */ "vzext.vf8\t\0" + /* 96 */ "rev8\t\0" + /* 102 */ "lla\t\0" + /* 107 */ "sfence.vma\t\0" + /* 119 */ "sra\t\0" + /* 124 */ "crc32.b\t\0" + /* 133 */ "crc32c.b\t\0" + /* 143 */ "orc.b\t\0" + /* 150 */ "xperm.b\t\0" + /* 159 */ "sext.b\t\0" + /* 167 */ "lb\t\0" + /* 171 */ "sb\t\0" + /* 175 */ "c.sub\t\0" + /* 182 */ "auipc\t\0" + /* 189 */ "gorc\t\0" + /* 195 */ "csrrc\t\0" + /* 202 */ "crc32.d\t\0" + /* 211 */ "fsub.d\t\0" + /* 219 */ "fmsub.d\t\0" + /* 228 */ "fnmsub.d\t\0" + /* 238 */ "crc32c.d\t\0" + /* 248 */ "sc.d\t\0" + /* 254 */ "fadd.d\t\0" + /* 262 */ "fmadd.d\t\0" + /* 271 */ "fnmadd.d\t\0" + /* 281 */ "amoadd.d\t\0" + /* 291 */ "amoand.d\t\0" + /* 301 */ "fle.d\t\0" + /* 308 */ "fcvt.h.d\t\0" + /* 318 */ "fsgnj.d\t\0" + /* 327 */ "fcvt.l.d\t\0" + /* 337 */ "fmul.d\t\0" + /* 345 */ "fmin.d\t\0" + /* 353 */ "amomin.d\t\0" + /* 363 */ "fsgnjn.d\t\0" + /* 373 */ "amoswap.d\t\0" + /* 384 */ "feq.d\t\0" + /* 391 */ "lr.d\t\0" + /* 397 */ "amoor.d\t\0" + /* 406 */ "amoxor.d\t\0" + /* 416 */ "fcvt.s.d\t\0" + /* 426 */ "fclass.d\t\0" + /* 436 */ "flt.d\t\0" + /* 443 */ "fsqrt.d\t\0" + /* 452 */ "fcvt.lu.d\t\0" + /* 463 */ "amominu.d\t\0" + /* 474 */ "fcvt.wu.d\t\0" + /* 485 */ "amomaxu.d\t\0" + /* 496 */ "fdiv.d\t\0" + /* 504 */ "fcvt.w.d\t\0" + /* 514 */ "fmv.x.d\t\0" + /* 523 */ "fmax.d\t\0" + /* 531 */ "amomax.d\t\0" + /* 541 */ "fsgnjx.d\t\0" + /* 551 */ "c.add\t\0" + /* 558 */ "sh1add\t\0" + /* 566 */ "sh2add\t\0" + /* 574 */ "sh3add\t\0" + /* 582 */ "la.tls.gd\t\0" + /* 593 */ "c.ld\t\0" + /* 599 */ "c.fld\t\0" + /* 606 */ "c.and\t\0" + /* 613 */ "c.sd\t\0" + /* 619 */ "c.fsd\t\0" + /* 626 */ "fence\t\0" + /* 633 */ "bge\t\0" + /* 638 */ "la.tls.ie\t\0" + /* 649 */ "bne\t\0" + /* 654 */ "vfmv.s.f\t\0" + /* 664 */ "vfmv.v.f\t\0" + /* 674 */ "vfsub.vf\t\0" + /* 684 */ "vfmsub.vf\t\0" + /* 695 */ "vfnmsub.vf\t\0" + /* 707 */ "vfrsub.vf\t\0" + /* 718 */ "vfwsub.vf\t\0" + /* 729 */ "vfmsac.vf\t\0" + /* 740 */ "vfnmsac.vf\t\0" + /* 752 */ "vfwnmsac.vf\t\0" + /* 765 */ "vfwmsac.vf\t\0" + /* 777 */ "vfmacc.vf\t\0" + /* 788 */ "vfnmacc.vf\t\0" + /* 800 */ "vfwnmacc.vf\t\0" + /* 813 */ "vfwmacc.vf\t\0" + /* 825 */ "vfadd.vf\t\0" + /* 835 */ "vfmadd.vf\t\0" + /* 846 */ "vfnmadd.vf\t\0" + /* 858 */ "vfwadd.vf\t\0" + /* 869 */ "vmfge.vf\t\0" + /* 879 */ "vmfle.vf\t\0" + /* 889 */ "vmfne.vf\t\0" + /* 899 */ "vfsgnj.vf\t\0" + /* 910 */ "vfmul.vf\t\0" + /* 920 */ "vfwmul.vf\t\0" + /* 931 */ "vfmin.vf\t\0" + /* 941 */ "vfsgnjn.vf\t\0" + /* 953 */ "vfslide1down.vf\t\0" + /* 970 */ "vfslide1up.vf\t\0" + /* 985 */ "vmfeq.vf\t\0" + /* 995 */ "vmfgt.vf\t\0" + /* 1005 */ "vmflt.vf\t\0" + /* 1015 */ "vfdiv.vf\t\0" + /* 1025 */ "vfrdiv.vf\t\0" + /* 1036 */ "vfmax.vf\t\0" + /* 1046 */ "vfsgnjx.vf\t\0" + /* 1058 */ "vfwsub.wf\t\0" + /* 1069 */ "vfwadd.wf\t\0" + /* 1080 */ "crc32.h\t\0" + /* 1089 */ "fsub.h\t\0" + /* 1097 */ "fmsub.h\t\0" + /* 1106 */ "fnmsub.h\t\0" + /* 1116 */ "crc32c.h\t\0" + /* 1126 */ "fcvt.d.h\t\0" + /* 1136 */ "fadd.h\t\0" + /* 1144 */ "fmadd.h\t\0" + /* 1153 */ "fnmadd.h\t\0" + /* 1163 */ "fle.h\t\0" + /* 1170 */ "fsgnj.h\t\0" + /* 1179 */ "fcvt.l.h\t\0" + /* 1189 */ "fmul.h\t\0" + /* 1197 */ "xperm.h\t\0" + /* 1206 */ "fmin.h\t\0" + /* 1214 */ "fsgnjn.h\t\0" + /* 1224 */ "feq.h\t\0" + /* 1231 */ "fcvt.s.h\t\0" + /* 1241 */ "fclass.h\t\0" + /* 1251 */ "flt.h\t\0" + /* 1258 */ "fsqrt.h\t\0" + /* 1267 */ "sext.h\t\0" + /* 1275 */ "zext.h\t\0" + /* 1283 */ "fcvt.lu.h\t\0" + /* 1294 */ "fcvt.wu.h\t\0" + /* 1305 */ "fdiv.h\t\0" + /* 1313 */ "fcvt.w.h\t\0" + /* 1323 */ "fmv.x.h\t\0" + /* 1332 */ "fmax.h\t\0" + /* 1340 */ "fsgnjx.h\t\0" + /* 1350 */ "packh\t\0" + /* 1357 */ "flh\t\0" + /* 1362 */ "clmulh\t\0" + /* 1370 */ "fsh\t\0" + /* 1375 */ "fence.i\t\0" + /* 1384 */ "vmv.v.i\t\0" + /* 1393 */ "c.srai\t\0" + /* 1401 */ "gorci\t\0" + /* 1408 */ "csrrci\t\0" + /* 1416 */ "c.addi\t\0" + /* 1424 */ "c.andi\t\0" + /* 1432 */ "wfi\t\0" + /* 1437 */ "c.li\t\0" + /* 1443 */ "unshfli\t\0" + /* 1452 */ "c.slli\t\0" + /* 1460 */ "c.srli\t\0" + /* 1468 */ "vsetivli\t\0" + /* 1478 */ "vsetvli\t\0" + /* 1487 */ "bclri\t\0" + /* 1494 */ "rori\t\0" + /* 1500 */ "xori\t\0" + /* 1506 */ "fsri\t\0" + /* 1512 */ "csrrsi\t\0" + /* 1520 */ "bseti\t\0" + /* 1527 */ "slti\t\0" + /* 1533 */ "bexti\t\0" + /* 1540 */ "c.lui\t\0" + /* 1547 */ "vssra.vi\t\0" + /* 1557 */ "vsra.vi\t\0" + /* 1566 */ "vrsub.vi\t\0" + /* 1576 */ "vmadc.vi\t\0" + /* 1586 */ "vsadd.vi\t\0" + /* 1596 */ "vadd.vi\t\0" + /* 1605 */ "vand.vi\t\0" + /* 1614 */ "vmsge.vi\t\0" + /* 1624 */ "vmsle.vi\t\0" + /* 1634 */ "vmsne.vi\t\0" + /* 1644 */ "vsll.vi\t\0" + /* 1653 */ "vssrl.vi\t\0" + /* 1663 */ "vsrl.vi\t\0" + /* 1672 */ "vslidedown.vi\t\0" + /* 1687 */ "vslideup.vi\t\0" + /* 1700 */ "vmseq.vi\t\0" + /* 1710 */ "vrgather.vi\t\0" + /* 1723 */ "vor.vi\t\0" + /* 1731 */ "vxor.vi\t\0" + /* 1740 */ "vmsgt.vi\t\0" + /* 1750 */ "vmslt.vi\t\0" + /* 1760 */ "vsaddu.vi\t\0" + /* 1771 */ "vmsgeu.vi\t\0" + /* 1782 */ "vmsleu.vi\t\0" + /* 1793 */ "vmsgtu.vi\t\0" + /* 1804 */ "vmsltu.vi\t\0" + /* 1815 */ "grevi\t\0" + /* 1822 */ "binvi\t\0" + /* 1829 */ "vnsra.wi\t\0" + /* 1839 */ "vnsrl.wi\t\0" + /* 1849 */ "vnclip.wi\t\0" + /* 1860 */ "vnclipu.wi\t\0" + /* 1872 */ "csrrwi\t\0" + /* 1880 */ "c.j\t\0" + /* 1885 */ "c.ebreak\t\0" + /* 1895 */ "pack\t\0" + /* 1901 */ "fcvt.d.l\t\0" + /* 1911 */ "fcvt.h.l\t\0" + /* 1921 */ "fcvt.s.l\t\0" + /* 1931 */ "c.jal\t\0" + /* 1938 */ "unshfl\t\0" + /* 1946 */ "tail\t\0" + /* 1952 */ "ecall\t\0" + /* 1959 */ "sll\t\0" + /* 1964 */ "rol\t\0" + /* 1969 */ "sc.d.rl\t\0" + /* 1978 */ "amoadd.d.rl\t\0" + /* 1991 */ "amoand.d.rl\t\0" + /* 2004 */ "amomin.d.rl\t\0" + /* 2017 */ "amoswap.d.rl\t\0" + /* 2031 */ "lr.d.rl\t\0" + /* 2040 */ "amoor.d.rl\t\0" + /* 2052 */ "amoxor.d.rl\t\0" + /* 2065 */ "amominu.d.rl\t\0" + /* 2079 */ "amomaxu.d.rl\t\0" + /* 2093 */ "amomax.d.rl\t\0" + /* 2106 */ "sc.w.rl\t\0" + /* 2115 */ "amoadd.w.rl\t\0" + /* 2128 */ "amoand.w.rl\t\0" + /* 2141 */ "amomin.w.rl\t\0" + /* 2154 */ "amoswap.w.rl\t\0" + /* 2168 */ "lr.w.rl\t\0" + /* 2177 */ "amoor.w.rl\t\0" + /* 2189 */ "amoxor.w.rl\t\0" + /* 2202 */ "amominu.w.rl\t\0" + /* 2216 */ "amomaxu.w.rl\t\0" + /* 2230 */ "amomax.w.rl\t\0" + /* 2243 */ "sc.d.aqrl\t\0" + /* 2254 */ "amoadd.d.aqrl\t\0" + /* 2269 */ "amoand.d.aqrl\t\0" + /* 2284 */ "amomin.d.aqrl\t\0" + /* 2299 */ "amoswap.d.aqrl\t\0" + /* 2315 */ "lr.d.aqrl\t\0" + /* 2326 */ "amoor.d.aqrl\t\0" + /* 2340 */ "amoxor.d.aqrl\t\0" + /* 2355 */ "amominu.d.aqrl\t\0" + /* 2371 */ "amomaxu.d.aqrl\t\0" + /* 2387 */ "amomax.d.aqrl\t\0" + /* 2402 */ "sc.w.aqrl\t\0" + /* 2413 */ "amoadd.w.aqrl\t\0" + /* 2428 */ "amoand.w.aqrl\t\0" + /* 2443 */ "amomin.w.aqrl\t\0" + /* 2458 */ "amoswap.w.aqrl\t\0" + /* 2474 */ "lr.w.aqrl\t\0" + /* 2485 */ "amoor.w.aqrl\t\0" + /* 2499 */ "amoxor.w.aqrl\t\0" + /* 2514 */ "amominu.w.aqrl\t\0" + /* 2530 */ "amomaxu.w.aqrl\t\0" + /* 2546 */ "amomax.w.aqrl\t\0" + /* 2561 */ "srl\t\0" + /* 2566 */ "fsl\t\0" + /* 2571 */ "clmul\t\0" + /* 2578 */ "vsetvl\t\0" + /* 2586 */ "viota.m\t\0" + /* 2595 */ "vmsbf.m\t\0" + /* 2604 */ "vmsif.m\t\0" + /* 2613 */ "vmsof.m\t\0" + /* 2622 */ "vcpop.m\t\0" + /* 2631 */ "vfirst.m\t\0" + /* 2641 */ "rem\t\0" + /* 2646 */ "vfmerge.vfm\t\0" + /* 2659 */ "vmadc.vim\t\0" + /* 2670 */ "vadc.vim\t\0" + /* 2680 */ "vmerge.vim\t\0" + /* 2692 */ "vmand.mm\t\0" + /* 2702 */ "vmnand.mm\t\0" + /* 2713 */ "vmandn.mm\t\0" + /* 2724 */ "vmorn.mm\t\0" + /* 2734 */ "vmor.mm\t\0" + /* 2743 */ "vmnor.mm\t\0" + /* 2753 */ "vmxnor.mm\t\0" + /* 2764 */ "vmxor.mm\t\0" + /* 2774 */ "vcompress.vm\t\0" + /* 2788 */ "vmsbc.vvm\t\0" + /* 2799 */ "vsbc.vvm\t\0" + /* 2809 */ "vmadc.vvm\t\0" + /* 2820 */ "vadc.vvm\t\0" + /* 2830 */ "vmerge.vvm\t\0" + /* 2842 */ "vmsbc.vxm\t\0" + /* 2853 */ "vsbc.vxm\t\0" + /* 2863 */ "vmadc.vxm\t\0" + /* 2874 */ "vadc.vxm\t\0" + /* 2884 */ "vmerge.vxm\t\0" + /* 2896 */ "xperm.n\t\0" + /* 2905 */ "andn\t\0" + /* 2911 */ "min\t\0" + /* 2916 */ "c.addi4spn\t\0" + /* 2928 */ "orn\t\0" + /* 2933 */ "fence.tso\t\0" + /* 2944 */ "bfp\t\0" + /* 2949 */ "bmatflip\t\0" + /* 2959 */ "c.unimp\t\0" + /* 2968 */ "jump\t\0" + /* 2974 */ "c.nop\t\0" + /* 2981 */ "cpop\t\0" + /* 2987 */ "c.addi16sp\t\0" + /* 2999 */ "c.ldsp\t\0" + /* 3007 */ "c.fldsp\t\0" + /* 3016 */ "c.sdsp\t\0" + /* 3024 */ "c.fsdsp\t\0" + /* 3033 */ "c.lwsp\t\0" + /* 3041 */ "c.flwsp\t\0" + /* 3050 */ "c.swsp\t\0" + /* 3058 */ "c.fswsp\t\0" + /* 3067 */ "sc.d.aq\t\0" + /* 3076 */ "amoadd.d.aq\t\0" + /* 3089 */ "amoand.d.aq\t\0" + /* 3102 */ "amomin.d.aq\t\0" + /* 3115 */ "amoswap.d.aq\t\0" + /* 3129 */ "lr.d.aq\t\0" + /* 3138 */ "amoor.d.aq\t\0" + /* 3150 */ "amoxor.d.aq\t\0" + /* 3163 */ "amominu.d.aq\t\0" + /* 3177 */ "amomaxu.d.aq\t\0" + /* 3191 */ "amomax.d.aq\t\0" + /* 3204 */ "sc.w.aq\t\0" + /* 3213 */ "amoadd.w.aq\t\0" + /* 3226 */ "amoand.w.aq\t\0" + /* 3239 */ "amomin.w.aq\t\0" + /* 3252 */ "amoswap.w.aq\t\0" + /* 3266 */ "lr.w.aq\t\0" + /* 3275 */ "amoor.w.aq\t\0" + /* 3287 */ "amoxor.w.aq\t\0" + /* 3300 */ "amominu.w.aq\t\0" + /* 3314 */ "amomaxu.w.aq\t\0" + /* 3328 */ "amomax.w.aq\t\0" + /* 3341 */ "beq\t\0" + /* 3346 */ "c.jr\t\0" + /* 3352 */ "c.jalr\t\0" + /* 3360 */ "bclr\t\0" + /* 3366 */ "clmulr\t\0" + /* 3374 */ "c.or\t\0" + /* 3380 */ "xnor\t\0" + /* 3386 */ "ror\t\0" + /* 3391 */ "bmator\t\0" + /* 3399 */ "c.xor\t\0" + /* 3406 */ "bmatxor\t\0" + /* 3415 */ "fsr\t\0" + /* 3420 */ "fsub.s\t\0" + /* 3428 */ "fmsub.s\t\0" + /* 3437 */ "fnmsub.s\t\0" + /* 3447 */ "fcvt.d.s\t\0" + /* 3457 */ "fadd.s\t\0" + /* 3465 */ "fmadd.s\t\0" + /* 3474 */ "fnmadd.s\t\0" + /* 3484 */ "fle.s\t\0" + /* 3491 */ "vfmv.f.s\t\0" + /* 3501 */ "fcvt.h.s\t\0" + /* 3511 */ "fsgnj.s\t\0" + /* 3520 */ "fcvt.l.s\t\0" + /* 3530 */ "fmul.s\t\0" + /* 3538 */ "fmin.s\t\0" + /* 3546 */ "fsgnjn.s\t\0" + /* 3556 */ "feq.s\t\0" + /* 3563 */ "fclass.s\t\0" + /* 3573 */ "flt.s\t\0" + /* 3580 */ "fsqrt.s\t\0" + /* 3589 */ "fcvt.lu.s\t\0" + /* 3600 */ "fcvt.wu.s\t\0" + /* 3611 */ "fdiv.s\t\0" + /* 3619 */ "fcvt.w.s\t\0" + /* 3629 */ "vmv.x.s\t\0" + /* 3638 */ "fmax.s\t\0" + /* 3646 */ "fsgnjx.s\t\0" + /* 3656 */ "csrrs\t\0" + /* 3663 */ "bcompress\t\0" + /* 3674 */ "bdecompress\t\0" + /* 3687 */ "vredand.vs\t\0" + /* 3699 */ "vredsum.vs\t\0" + /* 3711 */ "vwredsum.vs\t\0" + /* 3724 */ "vfredosum.vs\t\0" + /* 3738 */ "vfwredosum.vs\t\0" + /* 3753 */ "vfredusum.vs\t\0" + /* 3767 */ "vfwredusum.vs\t\0" + /* 3782 */ "vfredmin.vs\t\0" + /* 3795 */ "vredmin.vs\t\0" + /* 3807 */ "vredor.vs\t\0" + /* 3818 */ "vredxor.vs\t\0" + /* 3830 */ "vwredsumu.vs\t\0" + /* 3844 */ "vredminu.vs\t\0" + /* 3857 */ "vredmaxu.vs\t\0" + /* 3870 */ "vfredmax.vs\t\0" + /* 3883 */ "vredmax.vs\t\0" + /* 3895 */ "dret\t\0" + /* 3901 */ "mret\t\0" + /* 3907 */ "sret\t\0" + /* 3913 */ "uret\t\0" + /* 3919 */ "bset\t\0" + /* 3925 */ "blt\t\0" + /* 3930 */ "slt\t\0" + /* 3935 */ "bext\t\0" + /* 3941 */ "lbu\t\0" + /* 3946 */ "bgeu\t\0" + /* 3952 */ "mulhu\t\0" + /* 3959 */ "sltiu\t\0" + /* 3966 */ "packu\t\0" + /* 3973 */ "fcvt.d.lu\t\0" + /* 3984 */ "fcvt.h.lu\t\0" + /* 3995 */ "fcvt.s.lu\t\0" + /* 4006 */ "remu\t\0" + /* 4012 */ "minu\t\0" + /* 4018 */ "mulhsu\t\0" + /* 4026 */ "bltu\t\0" + /* 4032 */ "sltu\t\0" + /* 4038 */ "divu\t\0" + /* 4044 */ "fcvt.d.wu\t\0" + /* 4055 */ "fcvt.h.wu\t\0" + /* 4066 */ "fcvt.s.wu\t\0" + /* 4077 */ "lwu\t\0" + /* 4082 */ "maxu\t\0" + /* 4088 */ "vlseg2e32.v\t\0" + /* 4101 */ "vlsseg2e32.v\t\0" + /* 4115 */ "vssseg2e32.v\t\0" + /* 4129 */ "vsseg2e32.v\t\0" + /* 4142 */ "vlseg3e32.v\t\0" + /* 4155 */ "vlsseg3e32.v\t\0" + /* 4169 */ "vssseg3e32.v\t\0" + /* 4183 */ "vsseg3e32.v\t\0" + /* 4196 */ "vlseg4e32.v\t\0" + /* 4209 */ "vlsseg4e32.v\t\0" + /* 4223 */ "vssseg4e32.v\t\0" + /* 4237 */ "vsseg4e32.v\t\0" + /* 4250 */ "vlseg5e32.v\t\0" + /* 4263 */ "vlsseg5e32.v\t\0" + /* 4277 */ "vssseg5e32.v\t\0" + /* 4291 */ "vsseg5e32.v\t\0" + /* 4304 */ "vlseg6e32.v\t\0" + /* 4317 */ "vlsseg6e32.v\t\0" + /* 4331 */ "vssseg6e32.v\t\0" + /* 4345 */ "vsseg6e32.v\t\0" + /* 4358 */ "vlseg7e32.v\t\0" + /* 4371 */ "vlsseg7e32.v\t\0" + /* 4385 */ "vssseg7e32.v\t\0" + /* 4399 */ "vsseg7e32.v\t\0" + /* 4412 */ "vlseg8e32.v\t\0" + /* 4425 */ "vlsseg8e32.v\t\0" + /* 4439 */ "vssseg8e32.v\t\0" + /* 4453 */ "vsseg8e32.v\t\0" + /* 4466 */ "vle32.v\t\0" + /* 4475 */ "vl1re32.v\t\0" + /* 4486 */ "vl2re32.v\t\0" + /* 4497 */ "vl4re32.v\t\0" + /* 4508 */ "vl8re32.v\t\0" + /* 4519 */ "vlse32.v\t\0" + /* 4529 */ "vsse32.v\t\0" + /* 4539 */ "vse32.v\t\0" + /* 4548 */ "vloxseg2ei32.v\t\0" + /* 4564 */ "vsoxseg2ei32.v\t\0" + /* 4580 */ "vluxseg2ei32.v\t\0" + /* 4596 */ "vsuxseg2ei32.v\t\0" + /* 4612 */ "vloxseg3ei32.v\t\0" + /* 4628 */ "vsoxseg3ei32.v\t\0" + /* 4644 */ "vluxseg3ei32.v\t\0" + /* 4660 */ "vsuxseg3ei32.v\t\0" + /* 4676 */ "vloxseg4ei32.v\t\0" + /* 4692 */ "vsoxseg4ei32.v\t\0" + /* 4708 */ "vluxseg4ei32.v\t\0" + /* 4724 */ "vsuxseg4ei32.v\t\0" + /* 4740 */ "vloxseg5ei32.v\t\0" + /* 4756 */ "vsoxseg5ei32.v\t\0" + /* 4772 */ "vluxseg5ei32.v\t\0" + /* 4788 */ "vsuxseg5ei32.v\t\0" + /* 4804 */ "vloxseg6ei32.v\t\0" + /* 4820 */ "vsoxseg6ei32.v\t\0" + /* 4836 */ "vluxseg6ei32.v\t\0" + /* 4852 */ "vsuxseg6ei32.v\t\0" + /* 4868 */ "vloxseg7ei32.v\t\0" + /* 4884 */ "vsoxseg7ei32.v\t\0" + /* 4900 */ "vluxseg7ei32.v\t\0" + /* 4916 */ "vsuxseg7ei32.v\t\0" + /* 4932 */ "vloxseg8ei32.v\t\0" + /* 4948 */ "vsoxseg8ei32.v\t\0" + /* 4964 */ "vluxseg8ei32.v\t\0" + /* 4980 */ "vsuxseg8ei32.v\t\0" + /* 4996 */ "vamoaddei32.v\t\0" + /* 5011 */ "vamoandei32.v\t\0" + /* 5026 */ "vamominei32.v\t\0" + /* 5041 */ "vamoswapei32.v\t\0" + /* 5057 */ "vamoorei32.v\t\0" + /* 5071 */ "vamoxorei32.v\t\0" + /* 5086 */ "vamominuei32.v\t\0" + /* 5102 */ "vamomaxuei32.v\t\0" + /* 5118 */ "vamomaxei32.v\t\0" + /* 5133 */ "vloxei32.v\t\0" + /* 5145 */ "vsoxei32.v\t\0" + /* 5157 */ "vluxei32.v\t\0" + /* 5169 */ "vsuxei32.v\t\0" + /* 5181 */ "vlseg2e64.v\t\0" + /* 5194 */ "vlsseg2e64.v\t\0" + /* 5208 */ "vssseg2e64.v\t\0" + /* 5222 */ "vsseg2e64.v\t\0" + /* 5235 */ "vlseg3e64.v\t\0" + /* 5248 */ "vlsseg3e64.v\t\0" + /* 5262 */ "vssseg3e64.v\t\0" + /* 5276 */ "vsseg3e64.v\t\0" + /* 5289 */ "vlseg4e64.v\t\0" + /* 5302 */ "vlsseg4e64.v\t\0" + /* 5316 */ "vssseg4e64.v\t\0" + /* 5330 */ "vsseg4e64.v\t\0" + /* 5343 */ "vlseg5e64.v\t\0" + /* 5356 */ "vlsseg5e64.v\t\0" + /* 5370 */ "vssseg5e64.v\t\0" + /* 5384 */ "vsseg5e64.v\t\0" + /* 5397 */ "vlseg6e64.v\t\0" + /* 5410 */ "vlsseg6e64.v\t\0" + /* 5424 */ "vssseg6e64.v\t\0" + /* 5438 */ "vsseg6e64.v\t\0" + /* 5451 */ "vlseg7e64.v\t\0" + /* 5464 */ "vlsseg7e64.v\t\0" + /* 5478 */ "vssseg7e64.v\t\0" + /* 5492 */ "vsseg7e64.v\t\0" + /* 5505 */ "vlseg8e64.v\t\0" + /* 5518 */ "vlsseg8e64.v\t\0" + /* 5532 */ "vssseg8e64.v\t\0" + /* 5546 */ "vsseg8e64.v\t\0" + /* 5559 */ "vle64.v\t\0" + /* 5568 */ "vl1re64.v\t\0" + /* 5579 */ "vl2re64.v\t\0" + /* 5590 */ "vl4re64.v\t\0" + /* 5601 */ "vl8re64.v\t\0" + /* 5612 */ "vlse64.v\t\0" + /* 5622 */ "vsse64.v\t\0" + /* 5632 */ "vse64.v\t\0" + /* 5641 */ "vloxseg2ei64.v\t\0" + /* 5657 */ "vsoxseg2ei64.v\t\0" + /* 5673 */ "vluxseg2ei64.v\t\0" + /* 5689 */ "vsuxseg2ei64.v\t\0" + /* 5705 */ "vloxseg3ei64.v\t\0" + /* 5721 */ "vsoxseg3ei64.v\t\0" + /* 5737 */ "vluxseg3ei64.v\t\0" + /* 5753 */ "vsuxseg3ei64.v\t\0" + /* 5769 */ "vloxseg4ei64.v\t\0" + /* 5785 */ "vsoxseg4ei64.v\t\0" + /* 5801 */ "vluxseg4ei64.v\t\0" + /* 5817 */ "vsuxseg4ei64.v\t\0" + /* 5833 */ "vloxseg5ei64.v\t\0" + /* 5849 */ "vsoxseg5ei64.v\t\0" + /* 5865 */ "vluxseg5ei64.v\t\0" + /* 5881 */ "vsuxseg5ei64.v\t\0" + /* 5897 */ "vloxseg6ei64.v\t\0" + /* 5913 */ "vsoxseg6ei64.v\t\0" + /* 5929 */ "vluxseg6ei64.v\t\0" + /* 5945 */ "vsuxseg6ei64.v\t\0" + /* 5961 */ "vloxseg7ei64.v\t\0" + /* 5977 */ "vsoxseg7ei64.v\t\0" + /* 5993 */ "vluxseg7ei64.v\t\0" + /* 6009 */ "vsuxseg7ei64.v\t\0" + /* 6025 */ "vloxseg8ei64.v\t\0" + /* 6041 */ "vsoxseg8ei64.v\t\0" + /* 6057 */ "vluxseg8ei64.v\t\0" + /* 6073 */ "vsuxseg8ei64.v\t\0" + /* 6089 */ "vamoaddei64.v\t\0" + /* 6104 */ "vamoandei64.v\t\0" + /* 6119 */ "vamominei64.v\t\0" + /* 6134 */ "vamoswapei64.v\t\0" + /* 6150 */ "vamoorei64.v\t\0" + /* 6164 */ "vamoxorei64.v\t\0" + /* 6179 */ "vamominuei64.v\t\0" + /* 6195 */ "vamomaxuei64.v\t\0" + /* 6211 */ "vamomaxei64.v\t\0" + /* 6226 */ "vloxei64.v\t\0" + /* 6238 */ "vsoxei64.v\t\0" + /* 6250 */ "vluxei64.v\t\0" + /* 6262 */ "vsuxei64.v\t\0" + /* 6274 */ "vlseg2e16.v\t\0" + /* 6287 */ "vlsseg2e16.v\t\0" + /* 6301 */ "vssseg2e16.v\t\0" + /* 6315 */ "vsseg2e16.v\t\0" + /* 6328 */ "vlseg3e16.v\t\0" + /* 6341 */ "vlsseg3e16.v\t\0" + /* 6355 */ "vssseg3e16.v\t\0" + /* 6369 */ "vsseg3e16.v\t\0" + /* 6382 */ "vlseg4e16.v\t\0" + /* 6395 */ "vlsseg4e16.v\t\0" + /* 6409 */ "vssseg4e16.v\t\0" + /* 6423 */ "vsseg4e16.v\t\0" + /* 6436 */ "vlseg5e16.v\t\0" + /* 6449 */ "vlsseg5e16.v\t\0" + /* 6463 */ "vssseg5e16.v\t\0" + /* 6477 */ "vsseg5e16.v\t\0" + /* 6490 */ "vlseg6e16.v\t\0" + /* 6503 */ "vlsseg6e16.v\t\0" + /* 6517 */ "vssseg6e16.v\t\0" + /* 6531 */ "vsseg6e16.v\t\0" + /* 6544 */ "vlseg7e16.v\t\0" + /* 6557 */ "vlsseg7e16.v\t\0" + /* 6571 */ "vssseg7e16.v\t\0" + /* 6585 */ "vsseg7e16.v\t\0" + /* 6598 */ "vlseg8e16.v\t\0" + /* 6611 */ "vlsseg8e16.v\t\0" + /* 6625 */ "vssseg8e16.v\t\0" + /* 6639 */ "vsseg8e16.v\t\0" + /* 6652 */ "vle16.v\t\0" + /* 6661 */ "vl1re16.v\t\0" + /* 6672 */ "vl2re16.v\t\0" + /* 6683 */ "vl4re16.v\t\0" + /* 6694 */ "vl8re16.v\t\0" + /* 6705 */ "vlse16.v\t\0" + /* 6715 */ "vsse16.v\t\0" + /* 6725 */ "vse16.v\t\0" + /* 6734 */ "vloxseg2ei16.v\t\0" + /* 6750 */ "vsoxseg2ei16.v\t\0" + /* 6766 */ "vluxseg2ei16.v\t\0" + /* 6782 */ "vsuxseg2ei16.v\t\0" + /* 6798 */ "vloxseg3ei16.v\t\0" + /* 6814 */ "vsoxseg3ei16.v\t\0" + /* 6830 */ "vluxseg3ei16.v\t\0" + /* 6846 */ "vsuxseg3ei16.v\t\0" + /* 6862 */ "vloxseg4ei16.v\t\0" + /* 6878 */ "vsoxseg4ei16.v\t\0" + /* 6894 */ "vluxseg4ei16.v\t\0" + /* 6910 */ "vsuxseg4ei16.v\t\0" + /* 6926 */ "vloxseg5ei16.v\t\0" + /* 6942 */ "vsoxseg5ei16.v\t\0" + /* 6958 */ "vluxseg5ei16.v\t\0" + /* 6974 */ "vsuxseg5ei16.v\t\0" + /* 6990 */ "vloxseg6ei16.v\t\0" + /* 7006 */ "vsoxseg6ei16.v\t\0" + /* 7022 */ "vluxseg6ei16.v\t\0" + /* 7038 */ "vsuxseg6ei16.v\t\0" + /* 7054 */ "vloxseg7ei16.v\t\0" + /* 7070 */ "vsoxseg7ei16.v\t\0" + /* 7086 */ "vluxseg7ei16.v\t\0" + /* 7102 */ "vsuxseg7ei16.v\t\0" + /* 7118 */ "vloxseg8ei16.v\t\0" + /* 7134 */ "vsoxseg8ei16.v\t\0" + /* 7150 */ "vluxseg8ei16.v\t\0" + /* 7166 */ "vsuxseg8ei16.v\t\0" + /* 7182 */ "vamoaddei16.v\t\0" + /* 7197 */ "vamoandei16.v\t\0" + /* 7212 */ "vamominei16.v\t\0" + /* 7227 */ "vamoswapei16.v\t\0" + /* 7243 */ "vamoorei16.v\t\0" + /* 7257 */ "vamoxorei16.v\t\0" + /* 7272 */ "vamominuei16.v\t\0" + /* 7288 */ "vamomaxuei16.v\t\0" + /* 7304 */ "vamomaxei16.v\t\0" + /* 7319 */ "vloxei16.v\t\0" + /* 7331 */ "vsoxei16.v\t\0" + /* 7343 */ "vluxei16.v\t\0" + /* 7355 */ "vsuxei16.v\t\0" + /* 7367 */ "vfrec7.v\t\0" + /* 7377 */ "vfrsqrt7.v\t\0" + /* 7389 */ "vlseg2e8.v\t\0" + /* 7401 */ "vlsseg2e8.v\t\0" + /* 7414 */ "vssseg2e8.v\t\0" + /* 7427 */ "vsseg2e8.v\t\0" + /* 7439 */ "vlseg3e8.v\t\0" + /* 7451 */ "vlsseg3e8.v\t\0" + /* 7464 */ "vssseg3e8.v\t\0" + /* 7477 */ "vsseg3e8.v\t\0" + /* 7489 */ "vlseg4e8.v\t\0" + /* 7501 */ "vlsseg4e8.v\t\0" + /* 7514 */ "vssseg4e8.v\t\0" + /* 7527 */ "vsseg4e8.v\t\0" + /* 7539 */ "vlseg5e8.v\t\0" + /* 7551 */ "vlsseg5e8.v\t\0" + /* 7564 */ "vssseg5e8.v\t\0" + /* 7577 */ "vsseg5e8.v\t\0" + /* 7589 */ "vlseg6e8.v\t\0" + /* 7601 */ "vlsseg6e8.v\t\0" + /* 7614 */ "vssseg6e8.v\t\0" + /* 7627 */ "vsseg6e8.v\t\0" + /* 7639 */ "vlseg7e8.v\t\0" + /* 7651 */ "vlsseg7e8.v\t\0" + /* 7664 */ "vssseg7e8.v\t\0" + /* 7677 */ "vsseg7e8.v\t\0" + /* 7689 */ "vlseg8e8.v\t\0" + /* 7701 */ "vlsseg8e8.v\t\0" + /* 7714 */ "vssseg8e8.v\t\0" + /* 7727 */ "vsseg8e8.v\t\0" + /* 7739 */ "vle8.v\t\0" + /* 7747 */ "vl1re8.v\t\0" + /* 7757 */ "vl2re8.v\t\0" + /* 7767 */ "vl4re8.v\t\0" + /* 7777 */ "vl8re8.v\t\0" + /* 7787 */ "vlse8.v\t\0" + /* 7796 */ "vsse8.v\t\0" + /* 7805 */ "vse8.v\t\0" + /* 7813 */ "vloxseg2ei8.v\t\0" + /* 7828 */ "vsoxseg2ei8.v\t\0" + /* 7843 */ "vluxseg2ei8.v\t\0" + /* 7858 */ "vsuxseg2ei8.v\t\0" + /* 7873 */ "vloxseg3ei8.v\t\0" + /* 7888 */ "vsoxseg3ei8.v\t\0" + /* 7903 */ "vluxseg3ei8.v\t\0" + /* 7918 */ "vsuxseg3ei8.v\t\0" + /* 7933 */ "vloxseg4ei8.v\t\0" + /* 7948 */ "vsoxseg4ei8.v\t\0" + /* 7963 */ "vluxseg4ei8.v\t\0" + /* 7978 */ "vsuxseg4ei8.v\t\0" + /* 7993 */ "vloxseg5ei8.v\t\0" + /* 8008 */ "vsoxseg5ei8.v\t\0" + /* 8023 */ "vluxseg5ei8.v\t\0" + /* 8038 */ "vsuxseg5ei8.v\t\0" + /* 8053 */ "vloxseg6ei8.v\t\0" + /* 8068 */ "vsoxseg6ei8.v\t\0" + /* 8083 */ "vluxseg6ei8.v\t\0" + /* 8098 */ "vsuxseg6ei8.v\t\0" + /* 8113 */ "vloxseg7ei8.v\t\0" + /* 8128 */ "vsoxseg7ei8.v\t\0" + /* 8143 */ "vluxseg7ei8.v\t\0" + /* 8158 */ "vsuxseg7ei8.v\t\0" + /* 8173 */ "vloxseg8ei8.v\t\0" + /* 8188 */ "vsoxseg8ei8.v\t\0" + /* 8203 */ "vluxseg8ei8.v\t\0" + /* 8218 */ "vsuxseg8ei8.v\t\0" + /* 8233 */ "vamoaddei8.v\t\0" + /* 8247 */ "vamoandei8.v\t\0" + /* 8261 */ "vamominei8.v\t\0" + /* 8275 */ "vamoswapei8.v\t\0" + /* 8290 */ "vamoorei8.v\t\0" + /* 8303 */ "vamoxorei8.v\t\0" + /* 8317 */ "vamominuei8.v\t\0" + /* 8332 */ "vamomaxuei8.v\t\0" + /* 8347 */ "vamomaxei8.v\t\0" + /* 8361 */ "vloxei8.v\t\0" + /* 8372 */ "vsoxei8.v\t\0" + /* 8383 */ "vluxei8.v\t\0" + /* 8394 */ "vsuxei8.v\t\0" + /* 8405 */ "vid.v\t\0" + /* 8412 */ "vfwcvt.f.f.v\t\0" + /* 8426 */ "vfcvt.xu.f.v\t\0" + /* 8440 */ "vfwcvt.xu.f.v\t\0" + /* 8455 */ "vfcvt.rtz.xu.f.v\t\0" + /* 8473 */ "vfwcvt.rtz.xu.f.v\t\0" + /* 8492 */ "vfcvt.x.f.v\t\0" + /* 8505 */ "vfwcvt.x.f.v\t\0" + /* 8519 */ "vfcvt.rtz.x.f.v\t\0" + /* 8536 */ "vfwcvt.rtz.x.f.v\t\0" + /* 8554 */ "vlseg2e32ff.v\t\0" + /* 8569 */ "vlseg3e32ff.v\t\0" + /* 8584 */ "vlseg4e32ff.v\t\0" + /* 8599 */ "vlseg5e32ff.v\t\0" + /* 8614 */ "vlseg6e32ff.v\t\0" + /* 8629 */ "vlseg7e32ff.v\t\0" + /* 8644 */ "vlseg8e32ff.v\t\0" + /* 8659 */ "vle32ff.v\t\0" + /* 8670 */ "vlseg2e64ff.v\t\0" + /* 8685 */ "vlseg3e64ff.v\t\0" + /* 8700 */ "vlseg4e64ff.v\t\0" + /* 8715 */ "vlseg5e64ff.v\t\0" + /* 8730 */ "vlseg6e64ff.v\t\0" + /* 8745 */ "vlseg7e64ff.v\t\0" + /* 8760 */ "vlseg8e64ff.v\t\0" + /* 8775 */ "vle64ff.v\t\0" + /* 8786 */ "vlseg2e16ff.v\t\0" + /* 8801 */ "vlseg3e16ff.v\t\0" + /* 8816 */ "vlseg4e16ff.v\t\0" + /* 8831 */ "vlseg5e16ff.v\t\0" + /* 8846 */ "vlseg6e16ff.v\t\0" + /* 8861 */ "vlseg7e16ff.v\t\0" + /* 8876 */ "vlseg8e16ff.v\t\0" + /* 8891 */ "vle16ff.v\t\0" + /* 8902 */ "vlseg2e8ff.v\t\0" + /* 8916 */ "vlseg3e8ff.v\t\0" + /* 8930 */ "vlseg4e8ff.v\t\0" + /* 8944 */ "vlseg5e8ff.v\t\0" + /* 8958 */ "vlseg6e8ff.v\t\0" + /* 8972 */ "vlseg7e8ff.v\t\0" + /* 8986 */ "vlseg8e8ff.v\t\0" + /* 9000 */ "vle8ff.v\t\0" + /* 9010 */ "vlm.v\t\0" + /* 9017 */ "vsm.v\t\0" + /* 9024 */ "vs1r.v\t\0" + /* 9032 */ "vmv1r.v\t\0" + /* 9041 */ "vs2r.v\t\0" + /* 9049 */ "vmv2r.v\t\0" + /* 9058 */ "vs4r.v\t\0" + /* 9066 */ "vmv4r.v\t\0" + /* 9075 */ "vs8r.v\t\0" + /* 9083 */ "vmv8r.v\t\0" + /* 9092 */ "vfclass.v\t\0" + /* 9103 */ "vfsqrt.v\t\0" + /* 9113 */ "vfcvt.f.xu.v\t\0" + /* 9127 */ "vfwcvt.f.xu.v\t\0" + /* 9142 */ "vmv.v.v\t\0" + /* 9151 */ "vfcvt.f.x.v\t\0" + /* 9164 */ "vfwcvt.f.x.v\t\0" + /* 9178 */ "grev\t\0" + /* 9184 */ "div\t\0" + /* 9189 */ "c.mv\t\0" + /* 9195 */ "binv\t\0" + /* 9201 */ "cmov\t\0" + /* 9207 */ "vrgatherei16.vv\t\0" + /* 9224 */ "vssra.vv\t\0" + /* 9234 */ "vsra.vv\t\0" + /* 9243 */ "vasub.vv\t\0" + /* 9253 */ "vfsub.vv\t\0" + /* 9263 */ "vfmsub.vv\t\0" + /* 9274 */ "vfnmsub.vv\t\0" + /* 9286 */ "vnmsub.vv\t\0" + /* 9297 */ "vssub.vv\t\0" + /* 9307 */ "vsub.vv\t\0" + /* 9316 */ "vfwsub.vv\t\0" + /* 9327 */ "vwsub.vv\t\0" + /* 9337 */ "vfmsac.vv\t\0" + /* 9348 */ "vfnmsac.vv\t\0" + /* 9360 */ "vnmsac.vv\t\0" + /* 9371 */ "vfwnmsac.vv\t\0" + /* 9384 */ "vfwmsac.vv\t\0" + /* 9396 */ "vmsbc.vv\t\0" + /* 9406 */ "vfmacc.vv\t\0" + /* 9417 */ "vfnmacc.vv\t\0" + /* 9429 */ "vfwnmacc.vv\t\0" + /* 9442 */ "vmacc.vv\t\0" + /* 9452 */ "vfwmacc.vv\t\0" + /* 9464 */ "vwmacc.vv\t\0" + /* 9475 */ "vmadc.vv\t\0" + /* 9485 */ "vaadd.vv\t\0" + /* 9495 */ "vfadd.vv\t\0" + /* 9505 */ "vfmadd.vv\t\0" + /* 9516 */ "vfnmadd.vv\t\0" + /* 9528 */ "vmadd.vv\t\0" + /* 9538 */ "vsadd.vv\t\0" + /* 9548 */ "vadd.vv\t\0" + /* 9557 */ "vfwadd.vv\t\0" + /* 9568 */ "vwadd.vv\t\0" + /* 9578 */ "vand.vv\t\0" + /* 9587 */ "vmfle.vv\t\0" + /* 9597 */ "vmsle.vv\t\0" + /* 9607 */ "vmfne.vv\t\0" + /* 9617 */ "vmsne.vv\t\0" + /* 9627 */ "vmulh.vv\t\0" + /* 9637 */ "vfsgnj.vv\t\0" + /* 9648 */ "vsll.vv\t\0" + /* 9657 */ "vssrl.vv\t\0" + /* 9667 */ "vsrl.vv\t\0" + /* 9676 */ "vfmul.vv\t\0" + /* 9686 */ "vsmul.vv\t\0" + /* 9696 */ "vmul.vv\t\0" + /* 9705 */ "vfwmul.vv\t\0" + /* 9716 */ "vwmul.vv\t\0" + /* 9726 */ "vrem.vv\t\0" + /* 9735 */ "vfmin.vv\t\0" + /* 9745 */ "vmin.vv\t\0" + /* 9754 */ "vfsgnjn.vv\t\0" + /* 9766 */ "vmfeq.vv\t\0" + /* 9776 */ "vmseq.vv\t\0" + /* 9786 */ "vrgather.vv\t\0" + /* 9799 */ "vor.vv\t\0" + /* 9807 */ "vxor.vv\t\0" + /* 9816 */ "vmflt.vv\t\0" + /* 9826 */ "vmslt.vv\t\0" + /* 9836 */ "vasubu.vv\t\0" + /* 9847 */ "vssubu.vv\t\0" + /* 9858 */ "vwsubu.vv\t\0" + /* 9869 */ "vwmaccu.vv\t\0" + /* 9881 */ "vaaddu.vv\t\0" + /* 9892 */ "vsaddu.vv\t\0" + /* 9903 */ "vwaddu.vv\t\0" + /* 9914 */ "vmsleu.vv\t\0" + /* 9925 */ "vmulhu.vv\t\0" + /* 9936 */ "vwmulu.vv\t\0" + /* 9947 */ "vremu.vv\t\0" + /* 9957 */ "vminu.vv\t\0" + /* 9967 */ "vwmaccsu.vv\t\0" + /* 9980 */ "vmulhsu.vv\t\0" + /* 9992 */ "vwmulsu.vv\t\0" + /* 10004 */ "vmsltu.vv\t\0" + /* 10015 */ "vdivu.vv\t\0" + /* 10025 */ "vmaxu.vv\t\0" + /* 10035 */ "vfdiv.vv\t\0" + /* 10045 */ "vdiv.vv\t\0" + /* 10054 */ "vfmax.vv\t\0" + /* 10064 */ "vmax.vv\t\0" + /* 10073 */ "vfsgnjx.vv\t\0" + /* 10085 */ "vnsra.wv\t\0" + /* 10095 */ "vfwsub.wv\t\0" + /* 10106 */ "vwsub.wv\t\0" + /* 10116 */ "vfwadd.wv\t\0" + /* 10127 */ "vwadd.wv\t\0" + /* 10137 */ "vnsrl.wv\t\0" + /* 10147 */ "vnclip.wv\t\0" + /* 10158 */ "vwsubu.wv\t\0" + /* 10169 */ "vwaddu.wv\t\0" + /* 10180 */ "vnclipu.wv\t\0" + /* 10192 */ "crc32.w\t\0" + /* 10201 */ "crc32c.w\t\0" + /* 10211 */ "sc.w\t\0" + /* 10217 */ "fcvt.d.w\t\0" + /* 10227 */ "amoadd.w\t\0" + /* 10237 */ "amoand.w\t\0" + /* 10247 */ "vfncvt.rod.f.f.w\t\0" + /* 10265 */ "vfncvt.f.f.w\t\0" + /* 10279 */ "vfncvt.xu.f.w\t\0" + /* 10294 */ "vfncvt.rtz.xu.f.w\t\0" + /* 10313 */ "vfncvt.x.f.w\t\0" + /* 10327 */ "vfncvt.rtz.x.f.w\t\0" + /* 10345 */ "fcvt.h.w\t\0" + /* 10355 */ "xperm.w\t\0" + /* 10364 */ "amomin.w\t\0" + /* 10374 */ "amoswap.w\t\0" + /* 10385 */ "lr.w\t\0" + /* 10391 */ "amoor.w\t\0" + /* 10400 */ "amoxor.w\t\0" + /* 10410 */ "fcvt.s.w\t\0" + /* 10420 */ "zext.w\t\0" + /* 10428 */ "amominu.w\t\0" + /* 10439 */ "vfncvt.f.xu.w\t\0" + /* 10454 */ "amomaxu.w\t\0" + /* 10465 */ "vfncvt.f.x.w\t\0" + /* 10479 */ "fmv.x.w\t\0" + /* 10488 */ "amomax.w\t\0" + /* 10498 */ "sraw\t\0" + /* 10504 */ "c.subw\t\0" + /* 10512 */ "gorcw\t\0" + /* 10519 */ "c.addw\t\0" + /* 10527 */ "sraiw\t\0" + /* 10534 */ "gorciw\t\0" + /* 10542 */ "c.addiw\t\0" + /* 10551 */ "slliw\t\0" + /* 10558 */ "srliw\t\0" + /* 10565 */ "roriw\t\0" + /* 10572 */ "fsriw\t\0" + /* 10579 */ "greviw\t\0" + /* 10587 */ "packw\t\0" + /* 10594 */ "c.lw\t\0" + /* 10600 */ "c.flw\t\0" + /* 10607 */ "unshflw\t\0" + /* 10616 */ "sllw\t\0" + /* 10622 */ "rolw\t\0" + /* 10628 */ "srlw\t\0" + /* 10634 */ "fslw\t\0" + /* 10640 */ "mulw\t\0" + /* 10646 */ "remw\t\0" + /* 10652 */ "bfpw\t\0" + /* 10658 */ "cpopw\t\0" + /* 10665 */ "rorw\t\0" + /* 10671 */ "csrrw\t\0" + /* 10678 */ "fsrw\t\0" + /* 10684 */ "c.sw\t\0" + /* 10690 */ "c.fsw\t\0" + /* 10697 */ "bcompressw\t\0" + /* 10709 */ "bdecompressw\t\0" + /* 10723 */ "sh1add.uw\t\0" + /* 10734 */ "sh2add.uw\t\0" + /* 10745 */ "sh3add.uw\t\0" + /* 10756 */ "slli.uw\t\0" + /* 10765 */ "packuw\t\0" + /* 10773 */ "remuw\t\0" + /* 10780 */ "divuw\t\0" + /* 10787 */ "grevw\t\0" + /* 10794 */ "divw\t\0" + /* 10800 */ "clzw\t\0" + /* 10806 */ "ctzw\t\0" + /* 10812 */ "fmv.d.x\t\0" + /* 10821 */ "fmv.h.x\t\0" + /* 10830 */ "vmv.s.x\t\0" + /* 10839 */ "vmv.v.x\t\0" + /* 10848 */ "fmv.w.x\t\0" + /* 10857 */ "max\t\0" + /* 10862 */ "cmix\t\0" + /* 10868 */ "vssra.vx\t\0" + /* 10878 */ "vsra.vx\t\0" + /* 10887 */ "vasub.vx\t\0" + /* 10897 */ "vnmsub.vx\t\0" + /* 10908 */ "vrsub.vx\t\0" + /* 10918 */ "vssub.vx\t\0" + /* 10928 */ "vsub.vx\t\0" + /* 10937 */ "vwsub.vx\t\0" + /* 10947 */ "vnmsac.vx\t\0" + /* 10958 */ "vmsbc.vx\t\0" + /* 10968 */ "vmacc.vx\t\0" + /* 10978 */ "vwmacc.vx\t\0" + /* 10989 */ "vmadc.vx\t\0" + /* 10999 */ "vaadd.vx\t\0" + /* 11009 */ "vmadd.vx\t\0" + /* 11019 */ "vsadd.vx\t\0" + /* 11029 */ "vadd.vx\t\0" + /* 11038 */ "vwadd.vx\t\0" + /* 11048 */ "vand.vx\t\0" + /* 11057 */ "vmsge.vx\t\0" + /* 11067 */ "vmsle.vx\t\0" + /* 11077 */ "vmsne.vx\t\0" + /* 11087 */ "vmulh.vx\t\0" + /* 11097 */ "vsll.vx\t\0" + /* 11106 */ "vssrl.vx\t\0" + /* 11116 */ "vsrl.vx\t\0" + /* 11125 */ "vsmul.vx\t\0" + /* 11135 */ "vmul.vx\t\0" + /* 11144 */ "vwmul.vx\t\0" + /* 11154 */ "vrem.vx\t\0" + /* 11163 */ "vmin.vx\t\0" + /* 11172 */ "vslide1down.vx\t\0" + /* 11188 */ "vslidedown.vx\t\0" + /* 11203 */ "vslide1up.vx\t\0" + /* 11217 */ "vslideup.vx\t\0" + /* 11230 */ "vmseq.vx\t\0" + /* 11240 */ "vrgather.vx\t\0" + /* 11253 */ "vor.vx\t\0" + /* 11261 */ "vxor.vx\t\0" + /* 11270 */ "vwmaccus.vx\t\0" + /* 11283 */ "vmsgt.vx\t\0" + /* 11293 */ "vmslt.vx\t\0" + /* 11303 */ "vasubu.vx\t\0" + /* 11314 */ "vssubu.vx\t\0" + /* 11325 */ "vwsubu.vx\t\0" + /* 11336 */ "vwmaccu.vx\t\0" + /* 11348 */ "vaaddu.vx\t\0" + /* 11359 */ "vsaddu.vx\t\0" + /* 11370 */ "vwaddu.vx\t\0" + /* 11381 */ "vmsgeu.vx\t\0" + /* 11392 */ "vmsleu.vx\t\0" + /* 11403 */ "vmulhu.vx\t\0" + /* 11414 */ "vwmulu.vx\t\0" + /* 11425 */ "vremu.vx\t\0" + /* 11435 */ "vminu.vx\t\0" + /* 11445 */ "vwmaccsu.vx\t\0" + /* 11458 */ "vmulhsu.vx\t\0" + /* 11470 */ "vwmulsu.vx\t\0" + /* 11482 */ "vmsgtu.vx\t\0" + /* 11493 */ "vmsltu.vx\t\0" + /* 11504 */ "vdivu.vx\t\0" + /* 11514 */ "vmaxu.vx\t\0" + /* 11524 */ "vdiv.vx\t\0" + /* 11533 */ "vmax.vx\t\0" + /* 11542 */ "vnsra.wx\t\0" + /* 11552 */ "vwsub.wx\t\0" + /* 11562 */ "vwadd.wx\t\0" + /* 11572 */ "vnsrl.wx\t\0" + /* 11582 */ "vnclip.wx\t\0" + /* 11593 */ "vwsubu.wx\t\0" + /* 11604 */ "vwaddu.wx\t\0" + /* 11615 */ "vnclipu.wx\t\0" + /* 11627 */ "c.bnez\t\0" + /* 11635 */ "clz\t\0" + /* 11640 */ "c.beqz\t\0" + /* 11648 */ "ctz\t\0" + /* 11653 */ ".insn r4 \0" + /* 11663 */ ".insn b \0" + /* 11672 */ ".insn i \0" + /* 11681 */ ".insn j \0" + /* 11690 */ ".insn r \0" + /* 11699 */ ".insn s \0" + /* 11708 */ ".insn u \0" + /* 11717 */ "vamoaddei32.v\tx0, (\0" + /* 11737 */ "vamoandei32.v\tx0, (\0" + /* 11757 */ "vamominei32.v\tx0, (\0" + /* 11777 */ "vamoswapei32.v\tx0, (\0" + /* 11798 */ "vamoorei32.v\tx0, (\0" + /* 11817 */ "vamoxorei32.v\tx0, (\0" + /* 11837 */ "vamominuei32.v\tx0, (\0" + /* 11858 */ "vamomaxuei32.v\tx0, (\0" + /* 11879 */ "vamomaxei32.v\tx0, (\0" + /* 11899 */ "vamoaddei64.v\tx0, (\0" + /* 11919 */ "vamoandei64.v\tx0, (\0" + /* 11939 */ "vamominei64.v\tx0, (\0" + /* 11959 */ "vamoswapei64.v\tx0, (\0" + /* 11980 */ "vamoorei64.v\tx0, (\0" + /* 11999 */ "vamoxorei64.v\tx0, (\0" + /* 12019 */ "vamominuei64.v\tx0, (\0" + /* 12040 */ "vamomaxuei64.v\tx0, (\0" + /* 12061 */ "vamomaxei64.v\tx0, (\0" + /* 12081 */ "vamoaddei16.v\tx0, (\0" + /* 12101 */ "vamoandei16.v\tx0, (\0" + /* 12121 */ "vamominei16.v\tx0, (\0" + /* 12141 */ "vamoswapei16.v\tx0, (\0" + /* 12162 */ "vamoorei16.v\tx0, (\0" + /* 12181 */ "vamoxorei16.v\tx0, (\0" + /* 12201 */ "vamominuei16.v\tx0, (\0" + /* 12222 */ "vamomaxuei16.v\tx0, (\0" + /* 12243 */ "vamomaxei16.v\tx0, (\0" + /* 12263 */ "vamoaddei8.v\tx0, (\0" + /* 12282 */ "vamoandei8.v\tx0, (\0" + /* 12301 */ "vamominei8.v\tx0, (\0" + /* 12320 */ "vamoswapei8.v\tx0, (\0" + /* 12340 */ "vamoorei8.v\tx0, (\0" + /* 12358 */ "vamoxorei8.v\tx0, (\0" + /* 12377 */ "vamominuei8.v\tx0, (\0" + /* 12397 */ "vamomaxuei8.v\tx0, (\0" + /* 12417 */ "vamomaxei8.v\tx0, (\0" + /* 12436 */ "# XRay Function Patchable RET.\0" + /* 12467 */ "# XRay Typed Event Log.\0" + /* 12491 */ "# XRay Custom Event Log.\0" + /* 12516 */ "# XRay Function Enter.\0" + /* 12539 */ "# XRay Tail Call Exit.\0" + /* 12562 */ "# XRay Function Exit.\0" + /* 12584 */ "LIFETIME_END\0" + /* 12597 */ "PSEUDO_PROBE\0" + /* 12610 */ "BUNDLE\0" + /* 12617 */ "DBG_VALUE\0" + /* 12627 */ "DBG_INSTR_REF\0" + /* 12641 */ "DBG_PHI\0" + /* 12649 */ "DBG_LABEL\0" + /* 12659 */ "LIFETIME_START\0" + /* 12674 */ "DBG_VALUE_LIST\0" + /* 12689 */ "# FEntry call\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 12618U, // DBG_VALUE + 12675U, // DBG_VALUE_LIST + 12628U, // DBG_INSTR_REF + 12642U, // DBG_PHI + 12650U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 12611U, // BUNDLE + 12660U, // LIFETIME_START + 12585U, // LIFETIME_END + 12598U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 12690U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 12517U, // PATCHABLE_FUNCTION_ENTER + 12437U, // PATCHABLE_RET + 12563U, // PATCHABLE_FUNCTION_EXIT + 12540U, // PATCHABLE_TAIL_CALL + 12492U, // PATCHABLE_EVENT_CALL + 12468U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 10U, // ADJCALLSTACKDOWN + 10U, // ADJCALLSTACKUP + 10U, // BuildPairF64Pseudo + 16938U, // PseudoAddTPRel + 10U, // PseudoAtomicLoadNand32 + 10U, // PseudoAtomicLoadNand64 + 10U, // PseudoBR + 10U, // PseudoBRIND + 149410U, // PseudoCALL + 10U, // PseudoCALLIndirect + 8406946U, // PseudoCALLReg + 10U, // PseudoCmpXchg32 + 10U, // PseudoCmpXchg64 + 605061722U, // PseudoFLD + 605062478U, // PseudoFLH + 605071723U, // PseudoFLW + 605061742U, // PseudoFSD + 605062491U, // PseudoFSH + 605071813U, // PseudoFSW + 10521497U, // PseudoJump + 8405096U, // PseudoLA + 8405575U, // PseudoLA_TLS_GD + 8405631U, // PseudoLA_TLS_IE + 8405160U, // PseudoLB + 8408934U, // PseudoLBU + 8405588U, // PseudoLD + 8406351U, // PseudoLH + 8408947U, // PseudoLHU + 8406432U, // PseudoLI + 8405095U, // PseudoLLA + 8415589U, // PseudoLW + 8409070U, // PseudoLWU + 10U, // PseudoMaskedAtomicLoadAdd32 + 10U, // PseudoMaskedAtomicLoadMax32 + 10U, // PseudoMaskedAtomicLoadMin32 + 10U, // PseudoMaskedAtomicLoadNand32 + 10U, // PseudoMaskedAtomicLoadSub32 + 10U, // PseudoMaskedAtomicLoadUMax32 + 10U, // PseudoMaskedAtomicLoadUMin32 + 10U, // PseudoMaskedAtomicSwap32 + 10U, // PseudoMaskedCmpXchg32 + 10U, // PseudoRET + 10U, // PseudoReadVL + 10U, // PseudoReadVLENB + 605061292U, // PseudoSB + 605061736U, // PseudoSD + 8405152U, // PseudoSEXT_B + 8406260U, // PseudoSEXT_H + 605062492U, // PseudoSH + 605071807U, // PseudoSW + 149403U, // PseudoTAIL + 10U, // PseudoTAILIndirect + 10U, // PseudoVAADDU_VV_M1 + 10U, // PseudoVAADDU_VV_M1_MASK + 10U, // PseudoVAADDU_VV_M2 + 10U, // PseudoVAADDU_VV_M2_MASK + 10U, // PseudoVAADDU_VV_M4 + 10U, // PseudoVAADDU_VV_M4_MASK + 10U, // PseudoVAADDU_VV_M8 + 10U, // PseudoVAADDU_VV_M8_MASK + 10U, // PseudoVAADDU_VV_MF2 + 10U, // PseudoVAADDU_VV_MF2_MASK + 10U, // PseudoVAADDU_VV_MF4 + 10U, // PseudoVAADDU_VV_MF4_MASK + 10U, // PseudoVAADDU_VV_MF8 + 10U, // PseudoVAADDU_VV_MF8_MASK + 10U, // PseudoVAADDU_VX_M1 + 10U, // PseudoVAADDU_VX_M1_MASK + 10U, // PseudoVAADDU_VX_M2 + 10U, // PseudoVAADDU_VX_M2_MASK + 10U, // PseudoVAADDU_VX_M4 + 10U, // PseudoVAADDU_VX_M4_MASK + 10U, // PseudoVAADDU_VX_M8 + 10U, // PseudoVAADDU_VX_M8_MASK + 10U, // PseudoVAADDU_VX_MF2 + 10U, // PseudoVAADDU_VX_MF2_MASK + 10U, // PseudoVAADDU_VX_MF4 + 10U, // PseudoVAADDU_VX_MF4_MASK + 10U, // PseudoVAADDU_VX_MF8 + 10U, // PseudoVAADDU_VX_MF8_MASK + 10U, // PseudoVAADD_VV_M1 + 10U, // PseudoVAADD_VV_M1_MASK + 10U, // PseudoVAADD_VV_M2 + 10U, // PseudoVAADD_VV_M2_MASK + 10U, // PseudoVAADD_VV_M4 + 10U, // PseudoVAADD_VV_M4_MASK + 10U, // PseudoVAADD_VV_M8 + 10U, // PseudoVAADD_VV_M8_MASK + 10U, // PseudoVAADD_VV_MF2 + 10U, // PseudoVAADD_VV_MF2_MASK + 10U, // PseudoVAADD_VV_MF4 + 10U, // PseudoVAADD_VV_MF4_MASK + 10U, // PseudoVAADD_VV_MF8 + 10U, // PseudoVAADD_VV_MF8_MASK + 10U, // PseudoVAADD_VX_M1 + 10U, // PseudoVAADD_VX_M1_MASK + 10U, // PseudoVAADD_VX_M2 + 10U, // PseudoVAADD_VX_M2_MASK + 10U, // PseudoVAADD_VX_M4 + 10U, // PseudoVAADD_VX_M4_MASK + 10U, // PseudoVAADD_VX_M8 + 10U, // PseudoVAADD_VX_M8_MASK + 10U, // PseudoVAADD_VX_MF2 + 10U, // PseudoVAADD_VX_MF2_MASK + 10U, // PseudoVAADD_VX_MF4 + 10U, // PseudoVAADD_VX_MF4_MASK + 10U, // PseudoVAADD_VX_MF8 + 10U, // PseudoVAADD_VX_MF8_MASK + 10U, // PseudoVADC_VIM_M1 + 10U, // PseudoVADC_VIM_M2 + 10U, // PseudoVADC_VIM_M4 + 10U, // PseudoVADC_VIM_M8 + 10U, // PseudoVADC_VIM_MF2 + 10U, // PseudoVADC_VIM_MF4 + 10U, // PseudoVADC_VIM_MF8 + 10U, // PseudoVADC_VVM_M1 + 10U, // PseudoVADC_VVM_M2 + 10U, // PseudoVADC_VVM_M4 + 10U, // PseudoVADC_VVM_M8 + 10U, // PseudoVADC_VVM_MF2 + 10U, // PseudoVADC_VVM_MF4 + 10U, // PseudoVADC_VVM_MF8 + 10U, // PseudoVADC_VXM_M1 + 10U, // PseudoVADC_VXM_M2 + 10U, // PseudoVADC_VXM_M4 + 10U, // PseudoVADC_VXM_M8 + 10U, // PseudoVADC_VXM_MF2 + 10U, // PseudoVADC_VXM_MF4 + 10U, // PseudoVADC_VXM_MF8 + 10U, // PseudoVADD_VI_M1 + 10U, // PseudoVADD_VI_M1_MASK + 10U, // PseudoVADD_VI_M2 + 10U, // PseudoVADD_VI_M2_MASK + 10U, // PseudoVADD_VI_M4 + 10U, // PseudoVADD_VI_M4_MASK + 10U, // PseudoVADD_VI_M8 + 10U, // PseudoVADD_VI_M8_MASK + 10U, // PseudoVADD_VI_MF2 + 10U, // PseudoVADD_VI_MF2_MASK + 10U, // PseudoVADD_VI_MF4 + 10U, // PseudoVADD_VI_MF4_MASK + 10U, // PseudoVADD_VI_MF8 + 10U, // PseudoVADD_VI_MF8_MASK + 10U, // PseudoVADD_VV_M1 + 10U, // PseudoVADD_VV_M1_MASK + 10U, // PseudoVADD_VV_M2 + 10U, // PseudoVADD_VV_M2_MASK + 10U, // PseudoVADD_VV_M4 + 10U, // PseudoVADD_VV_M4_MASK + 10U, // PseudoVADD_VV_M8 + 10U, // PseudoVADD_VV_M8_MASK + 10U, // PseudoVADD_VV_MF2 + 10U, // PseudoVADD_VV_MF2_MASK + 10U, // PseudoVADD_VV_MF4 + 10U, // PseudoVADD_VV_MF4_MASK + 10U, // PseudoVADD_VV_MF8 + 10U, // PseudoVADD_VV_MF8_MASK + 10U, // PseudoVADD_VX_M1 + 10U, // PseudoVADD_VX_M1_MASK + 10U, // PseudoVADD_VX_M2 + 10U, // PseudoVADD_VX_M2_MASK + 10U, // PseudoVADD_VX_M4 + 10U, // PseudoVADD_VX_M4_MASK + 10U, // PseudoVADD_VX_M8 + 10U, // PseudoVADD_VX_M8_MASK + 10U, // PseudoVADD_VX_MF2 + 10U, // PseudoVADD_VX_MF2_MASK + 10U, // PseudoVADD_VX_MF4 + 10U, // PseudoVADD_VX_MF4_MASK + 10U, // PseudoVADD_VX_MF8 + 10U, // PseudoVADD_VX_MF8_MASK + 10U, // PseudoVAMOADDEI16_WD_M1_MF2 + 10U, // PseudoVAMOADDEI16_WD_M1_MF2_MASK + 10U, // PseudoVAMOADDEI16_WD_M1_MF4 + 10U, // PseudoVAMOADDEI16_WD_M1_MF4_MASK + 10U, // PseudoVAMOADDEI16_WD_M2_M1 + 10U, // PseudoVAMOADDEI16_WD_M2_M1_MASK + 10U, // PseudoVAMOADDEI16_WD_M2_MF2 + 10U, // PseudoVAMOADDEI16_WD_M2_MF2_MASK + 10U, // PseudoVAMOADDEI16_WD_M4_M1 + 10U, // PseudoVAMOADDEI16_WD_M4_M1_MASK + 10U, // PseudoVAMOADDEI16_WD_M4_M2 + 10U, // PseudoVAMOADDEI16_WD_M4_M2_MASK + 10U, // PseudoVAMOADDEI16_WD_M8_M2 + 10U, // PseudoVAMOADDEI16_WD_M8_M2_MASK + 10U, // PseudoVAMOADDEI16_WD_M8_M4 + 10U, // PseudoVAMOADDEI16_WD_M8_M4_MASK + 10U, // PseudoVAMOADDEI16_WD_MF2_MF4 + 10U, // PseudoVAMOADDEI16_WD_MF2_MF4_MASK + 10U, // PseudoVAMOADDEI32_WD_M1_M1 + 10U, // PseudoVAMOADDEI32_WD_M1_M1_MASK + 10U, // PseudoVAMOADDEI32_WD_M1_MF2 + 10U, // PseudoVAMOADDEI32_WD_M1_MF2_MASK + 10U, // PseudoVAMOADDEI32_WD_M2_M1 + 10U, // PseudoVAMOADDEI32_WD_M2_M1_MASK + 10U, // PseudoVAMOADDEI32_WD_M2_M2 + 10U, // PseudoVAMOADDEI32_WD_M2_M2_MASK + 10U, // PseudoVAMOADDEI32_WD_M4_M2 + 10U, // PseudoVAMOADDEI32_WD_M4_M2_MASK + 10U, // PseudoVAMOADDEI32_WD_M4_M4 + 10U, // PseudoVAMOADDEI32_WD_M4_M4_MASK + 10U, // PseudoVAMOADDEI32_WD_M8_M4 + 10U, // PseudoVAMOADDEI32_WD_M8_M4_MASK + 10U, // PseudoVAMOADDEI32_WD_M8_M8 + 10U, // PseudoVAMOADDEI32_WD_M8_M8_MASK + 10U, // PseudoVAMOADDEI32_WD_MF2_MF2 + 10U, // PseudoVAMOADDEI32_WD_MF2_MF2_MASK + 10U, // PseudoVAMOADDEI64_WD_M1_M1 + 10U, // PseudoVAMOADDEI64_WD_M1_M1_MASK + 10U, // PseudoVAMOADDEI64_WD_M1_M2 + 10U, // PseudoVAMOADDEI64_WD_M1_M2_MASK + 10U, // PseudoVAMOADDEI64_WD_M2_M2 + 10U, // PseudoVAMOADDEI64_WD_M2_M2_MASK + 10U, // PseudoVAMOADDEI64_WD_M2_M4 + 10U, // PseudoVAMOADDEI64_WD_M2_M4_MASK + 10U, // PseudoVAMOADDEI64_WD_M4_M4 + 10U, // PseudoVAMOADDEI64_WD_M4_M4_MASK + 10U, // PseudoVAMOADDEI64_WD_M4_M8 + 10U, // PseudoVAMOADDEI64_WD_M4_M8_MASK + 10U, // PseudoVAMOADDEI64_WD_M8_M8 + 10U, // PseudoVAMOADDEI64_WD_M8_M8_MASK + 10U, // PseudoVAMOADDEI64_WD_MF2_M1 + 10U, // PseudoVAMOADDEI64_WD_MF2_M1_MASK + 10U, // PseudoVAMOADDEI8_WD_M1_MF4 + 10U, // PseudoVAMOADDEI8_WD_M1_MF4_MASK + 10U, // PseudoVAMOADDEI8_WD_M1_MF8 + 10U, // PseudoVAMOADDEI8_WD_M1_MF8_MASK + 10U, // PseudoVAMOADDEI8_WD_M2_MF2 + 10U, // PseudoVAMOADDEI8_WD_M2_MF2_MASK + 10U, // PseudoVAMOADDEI8_WD_M2_MF4 + 10U, // PseudoVAMOADDEI8_WD_M2_MF4_MASK + 10U, // PseudoVAMOADDEI8_WD_M4_M1 + 10U, // PseudoVAMOADDEI8_WD_M4_M1_MASK + 10U, // PseudoVAMOADDEI8_WD_M4_MF2 + 10U, // PseudoVAMOADDEI8_WD_M4_MF2_MASK + 10U, // PseudoVAMOADDEI8_WD_M8_M1 + 10U, // PseudoVAMOADDEI8_WD_M8_M1_MASK + 10U, // PseudoVAMOADDEI8_WD_M8_M2 + 10U, // PseudoVAMOADDEI8_WD_M8_M2_MASK + 10U, // PseudoVAMOADDEI8_WD_MF2_MF8 + 10U, // PseudoVAMOADDEI8_WD_MF2_MF8_MASK + 10U, // PseudoVAMOANDEI16_WD_M1_MF2 + 10U, // PseudoVAMOANDEI16_WD_M1_MF2_MASK + 10U, // PseudoVAMOANDEI16_WD_M1_MF4 + 10U, // PseudoVAMOANDEI16_WD_M1_MF4_MASK + 10U, // PseudoVAMOANDEI16_WD_M2_M1 + 10U, // PseudoVAMOANDEI16_WD_M2_M1_MASK + 10U, // PseudoVAMOANDEI16_WD_M2_MF2 + 10U, // PseudoVAMOANDEI16_WD_M2_MF2_MASK + 10U, // PseudoVAMOANDEI16_WD_M4_M1 + 10U, // PseudoVAMOANDEI16_WD_M4_M1_MASK + 10U, // PseudoVAMOANDEI16_WD_M4_M2 + 10U, // PseudoVAMOANDEI16_WD_M4_M2_MASK + 10U, // PseudoVAMOANDEI16_WD_M8_M2 + 10U, // PseudoVAMOANDEI16_WD_M8_M2_MASK + 10U, // PseudoVAMOANDEI16_WD_M8_M4 + 10U, // PseudoVAMOANDEI16_WD_M8_M4_MASK + 10U, // PseudoVAMOANDEI16_WD_MF2_MF4 + 10U, // PseudoVAMOANDEI16_WD_MF2_MF4_MASK + 10U, // PseudoVAMOANDEI32_WD_M1_M1 + 10U, // PseudoVAMOANDEI32_WD_M1_M1_MASK + 10U, // PseudoVAMOANDEI32_WD_M1_MF2 + 10U, // PseudoVAMOANDEI32_WD_M1_MF2_MASK + 10U, // PseudoVAMOANDEI32_WD_M2_M1 + 10U, // PseudoVAMOANDEI32_WD_M2_M1_MASK + 10U, // PseudoVAMOANDEI32_WD_M2_M2 + 10U, // PseudoVAMOANDEI32_WD_M2_M2_MASK + 10U, // PseudoVAMOANDEI32_WD_M4_M2 + 10U, // PseudoVAMOANDEI32_WD_M4_M2_MASK + 10U, // PseudoVAMOANDEI32_WD_M4_M4 + 10U, // PseudoVAMOANDEI32_WD_M4_M4_MASK + 10U, // PseudoVAMOANDEI32_WD_M8_M4 + 10U, // PseudoVAMOANDEI32_WD_M8_M4_MASK + 10U, // PseudoVAMOANDEI32_WD_M8_M8 + 10U, // PseudoVAMOANDEI32_WD_M8_M8_MASK + 10U, // PseudoVAMOANDEI32_WD_MF2_MF2 + 10U, // PseudoVAMOANDEI32_WD_MF2_MF2_MASK + 10U, // PseudoVAMOANDEI64_WD_M1_M1 + 10U, // PseudoVAMOANDEI64_WD_M1_M1_MASK + 10U, // PseudoVAMOANDEI64_WD_M1_M2 + 10U, // PseudoVAMOANDEI64_WD_M1_M2_MASK + 10U, // PseudoVAMOANDEI64_WD_M2_M2 + 10U, // PseudoVAMOANDEI64_WD_M2_M2_MASK + 10U, // PseudoVAMOANDEI64_WD_M2_M4 + 10U, // PseudoVAMOANDEI64_WD_M2_M4_MASK + 10U, // PseudoVAMOANDEI64_WD_M4_M4 + 10U, // PseudoVAMOANDEI64_WD_M4_M4_MASK + 10U, // PseudoVAMOANDEI64_WD_M4_M8 + 10U, // PseudoVAMOANDEI64_WD_M4_M8_MASK + 10U, // PseudoVAMOANDEI64_WD_M8_M8 + 10U, // PseudoVAMOANDEI64_WD_M8_M8_MASK + 10U, // PseudoVAMOANDEI64_WD_MF2_M1 + 10U, // PseudoVAMOANDEI64_WD_MF2_M1_MASK + 10U, // PseudoVAMOANDEI8_WD_M1_MF4 + 10U, // PseudoVAMOANDEI8_WD_M1_MF4_MASK + 10U, // PseudoVAMOANDEI8_WD_M1_MF8 + 10U, // PseudoVAMOANDEI8_WD_M1_MF8_MASK + 10U, // PseudoVAMOANDEI8_WD_M2_MF2 + 10U, // PseudoVAMOANDEI8_WD_M2_MF2_MASK + 10U, // PseudoVAMOANDEI8_WD_M2_MF4 + 10U, // PseudoVAMOANDEI8_WD_M2_MF4_MASK + 10U, // PseudoVAMOANDEI8_WD_M4_M1 + 10U, // PseudoVAMOANDEI8_WD_M4_M1_MASK + 10U, // PseudoVAMOANDEI8_WD_M4_MF2 + 10U, // PseudoVAMOANDEI8_WD_M4_MF2_MASK + 10U, // PseudoVAMOANDEI8_WD_M8_M1 + 10U, // PseudoVAMOANDEI8_WD_M8_M1_MASK + 10U, // PseudoVAMOANDEI8_WD_M8_M2 + 10U, // PseudoVAMOANDEI8_WD_M8_M2_MASK + 10U, // PseudoVAMOANDEI8_WD_MF2_MF8 + 10U, // PseudoVAMOANDEI8_WD_MF2_MF8_MASK + 10U, // PseudoVAMOMAXEI16_WD_M1_MF2 + 10U, // PseudoVAMOMAXEI16_WD_M1_MF2_MASK + 10U, // PseudoVAMOMAXEI16_WD_M1_MF4 + 10U, // PseudoVAMOMAXEI16_WD_M1_MF4_MASK + 10U, // PseudoVAMOMAXEI16_WD_M2_M1 + 10U, // PseudoVAMOMAXEI16_WD_M2_M1_MASK + 10U, // PseudoVAMOMAXEI16_WD_M2_MF2 + 10U, // PseudoVAMOMAXEI16_WD_M2_MF2_MASK + 10U, // PseudoVAMOMAXEI16_WD_M4_M1 + 10U, // PseudoVAMOMAXEI16_WD_M4_M1_MASK + 10U, // PseudoVAMOMAXEI16_WD_M4_M2 + 10U, // PseudoVAMOMAXEI16_WD_M4_M2_MASK + 10U, // PseudoVAMOMAXEI16_WD_M8_M2 + 10U, // PseudoVAMOMAXEI16_WD_M8_M2_MASK + 10U, // PseudoVAMOMAXEI16_WD_M8_M4 + 10U, // PseudoVAMOMAXEI16_WD_M8_M4_MASK + 10U, // PseudoVAMOMAXEI16_WD_MF2_MF4 + 10U, // PseudoVAMOMAXEI16_WD_MF2_MF4_MASK + 10U, // PseudoVAMOMAXEI32_WD_M1_M1 + 10U, // PseudoVAMOMAXEI32_WD_M1_M1_MASK + 10U, // PseudoVAMOMAXEI32_WD_M1_MF2 + 10U, // PseudoVAMOMAXEI32_WD_M1_MF2_MASK + 10U, // PseudoVAMOMAXEI32_WD_M2_M1 + 10U, // PseudoVAMOMAXEI32_WD_M2_M1_MASK + 10U, // PseudoVAMOMAXEI32_WD_M2_M2 + 10U, // PseudoVAMOMAXEI32_WD_M2_M2_MASK + 10U, // PseudoVAMOMAXEI32_WD_M4_M2 + 10U, // PseudoVAMOMAXEI32_WD_M4_M2_MASK + 10U, // PseudoVAMOMAXEI32_WD_M4_M4 + 10U, // PseudoVAMOMAXEI32_WD_M4_M4_MASK + 10U, // PseudoVAMOMAXEI32_WD_M8_M4 + 10U, // PseudoVAMOMAXEI32_WD_M8_M4_MASK + 10U, // PseudoVAMOMAXEI32_WD_M8_M8 + 10U, // PseudoVAMOMAXEI32_WD_M8_M8_MASK + 10U, // PseudoVAMOMAXEI32_WD_MF2_MF2 + 10U, // PseudoVAMOMAXEI32_WD_MF2_MF2_MASK + 10U, // PseudoVAMOMAXEI64_WD_M1_M1 + 10U, // PseudoVAMOMAXEI64_WD_M1_M1_MASK + 10U, // PseudoVAMOMAXEI64_WD_M1_M2 + 10U, // PseudoVAMOMAXEI64_WD_M1_M2_MASK + 10U, // PseudoVAMOMAXEI64_WD_M2_M2 + 10U, // PseudoVAMOMAXEI64_WD_M2_M2_MASK + 10U, // PseudoVAMOMAXEI64_WD_M2_M4 + 10U, // PseudoVAMOMAXEI64_WD_M2_M4_MASK + 10U, // PseudoVAMOMAXEI64_WD_M4_M4 + 10U, // PseudoVAMOMAXEI64_WD_M4_M4_MASK + 10U, // PseudoVAMOMAXEI64_WD_M4_M8 + 10U, // PseudoVAMOMAXEI64_WD_M4_M8_MASK + 10U, // PseudoVAMOMAXEI64_WD_M8_M8 + 10U, // PseudoVAMOMAXEI64_WD_M8_M8_MASK + 10U, // PseudoVAMOMAXEI64_WD_MF2_M1 + 10U, // PseudoVAMOMAXEI64_WD_MF2_M1_MASK + 10U, // PseudoVAMOMAXEI8_WD_M1_MF4 + 10U, // PseudoVAMOMAXEI8_WD_M1_MF4_MASK + 10U, // PseudoVAMOMAXEI8_WD_M1_MF8 + 10U, // PseudoVAMOMAXEI8_WD_M1_MF8_MASK + 10U, // PseudoVAMOMAXEI8_WD_M2_MF2 + 10U, // PseudoVAMOMAXEI8_WD_M2_MF2_MASK + 10U, // PseudoVAMOMAXEI8_WD_M2_MF4 + 10U, // PseudoVAMOMAXEI8_WD_M2_MF4_MASK + 10U, // PseudoVAMOMAXEI8_WD_M4_M1 + 10U, // PseudoVAMOMAXEI8_WD_M4_M1_MASK + 10U, // PseudoVAMOMAXEI8_WD_M4_MF2 + 10U, // PseudoVAMOMAXEI8_WD_M4_MF2_MASK + 10U, // PseudoVAMOMAXEI8_WD_M8_M1 + 10U, // PseudoVAMOMAXEI8_WD_M8_M1_MASK + 10U, // PseudoVAMOMAXEI8_WD_M8_M2 + 10U, // PseudoVAMOMAXEI8_WD_M8_M2_MASK + 10U, // PseudoVAMOMAXEI8_WD_MF2_MF8 + 10U, // PseudoVAMOMAXEI8_WD_MF2_MF8_MASK + 10U, // PseudoVAMOMAXUEI16_WD_M1_MF2 + 10U, // PseudoVAMOMAXUEI16_WD_M1_MF2_MASK + 10U, // PseudoVAMOMAXUEI16_WD_M1_MF4 + 10U, // PseudoVAMOMAXUEI16_WD_M1_MF4_MASK + 10U, // PseudoVAMOMAXUEI16_WD_M2_M1 + 10U, // PseudoVAMOMAXUEI16_WD_M2_M1_MASK + 10U, // PseudoVAMOMAXUEI16_WD_M2_MF2 + 10U, // PseudoVAMOMAXUEI16_WD_M2_MF2_MASK + 10U, // PseudoVAMOMAXUEI16_WD_M4_M1 + 10U, // PseudoVAMOMAXUEI16_WD_M4_M1_MASK + 10U, // PseudoVAMOMAXUEI16_WD_M4_M2 + 10U, // PseudoVAMOMAXUEI16_WD_M4_M2_MASK + 10U, // PseudoVAMOMAXUEI16_WD_M8_M2 + 10U, // PseudoVAMOMAXUEI16_WD_M8_M2_MASK + 10U, // PseudoVAMOMAXUEI16_WD_M8_M4 + 10U, // PseudoVAMOMAXUEI16_WD_M8_M4_MASK + 10U, // PseudoVAMOMAXUEI16_WD_MF2_MF4 + 10U, // PseudoVAMOMAXUEI16_WD_MF2_MF4_MASK + 10U, // PseudoVAMOMAXUEI32_WD_M1_M1 + 10U, // PseudoVAMOMAXUEI32_WD_M1_M1_MASK + 10U, // PseudoVAMOMAXUEI32_WD_M1_MF2 + 10U, // PseudoVAMOMAXUEI32_WD_M1_MF2_MASK + 10U, // PseudoVAMOMAXUEI32_WD_M2_M1 + 10U, // PseudoVAMOMAXUEI32_WD_M2_M1_MASK + 10U, // PseudoVAMOMAXUEI32_WD_M2_M2 + 10U, // PseudoVAMOMAXUEI32_WD_M2_M2_MASK + 10U, // PseudoVAMOMAXUEI32_WD_M4_M2 + 10U, // PseudoVAMOMAXUEI32_WD_M4_M2_MASK + 10U, // PseudoVAMOMAXUEI32_WD_M4_M4 + 10U, // PseudoVAMOMAXUEI32_WD_M4_M4_MASK + 10U, // PseudoVAMOMAXUEI32_WD_M8_M4 + 10U, // PseudoVAMOMAXUEI32_WD_M8_M4_MASK + 10U, // PseudoVAMOMAXUEI32_WD_M8_M8 + 10U, // PseudoVAMOMAXUEI32_WD_M8_M8_MASK + 10U, // PseudoVAMOMAXUEI32_WD_MF2_MF2 + 10U, // PseudoVAMOMAXUEI32_WD_MF2_MF2_MASK + 10U, // PseudoVAMOMAXUEI64_WD_M1_M1 + 10U, // PseudoVAMOMAXUEI64_WD_M1_M1_MASK + 10U, // PseudoVAMOMAXUEI64_WD_M1_M2 + 10U, // PseudoVAMOMAXUEI64_WD_M1_M2_MASK + 10U, // PseudoVAMOMAXUEI64_WD_M2_M2 + 10U, // PseudoVAMOMAXUEI64_WD_M2_M2_MASK + 10U, // PseudoVAMOMAXUEI64_WD_M2_M4 + 10U, // PseudoVAMOMAXUEI64_WD_M2_M4_MASK + 10U, // PseudoVAMOMAXUEI64_WD_M4_M4 + 10U, // PseudoVAMOMAXUEI64_WD_M4_M4_MASK + 10U, // PseudoVAMOMAXUEI64_WD_M4_M8 + 10U, // PseudoVAMOMAXUEI64_WD_M4_M8_MASK + 10U, // PseudoVAMOMAXUEI64_WD_M8_M8 + 10U, // PseudoVAMOMAXUEI64_WD_M8_M8_MASK + 10U, // PseudoVAMOMAXUEI64_WD_MF2_M1 + 10U, // PseudoVAMOMAXUEI64_WD_MF2_M1_MASK + 10U, // PseudoVAMOMAXUEI8_WD_M1_MF4 + 10U, // PseudoVAMOMAXUEI8_WD_M1_MF4_MASK + 10U, // PseudoVAMOMAXUEI8_WD_M1_MF8 + 10U, // PseudoVAMOMAXUEI8_WD_M1_MF8_MASK + 10U, // PseudoVAMOMAXUEI8_WD_M2_MF2 + 10U, // PseudoVAMOMAXUEI8_WD_M2_MF2_MASK + 10U, // PseudoVAMOMAXUEI8_WD_M2_MF4 + 10U, // PseudoVAMOMAXUEI8_WD_M2_MF4_MASK + 10U, // PseudoVAMOMAXUEI8_WD_M4_M1 + 10U, // PseudoVAMOMAXUEI8_WD_M4_M1_MASK + 10U, // PseudoVAMOMAXUEI8_WD_M4_MF2 + 10U, // PseudoVAMOMAXUEI8_WD_M4_MF2_MASK + 10U, // PseudoVAMOMAXUEI8_WD_M8_M1 + 10U, // PseudoVAMOMAXUEI8_WD_M8_M1_MASK + 10U, // PseudoVAMOMAXUEI8_WD_M8_M2 + 10U, // PseudoVAMOMAXUEI8_WD_M8_M2_MASK + 10U, // PseudoVAMOMAXUEI8_WD_MF2_MF8 + 10U, // PseudoVAMOMAXUEI8_WD_MF2_MF8_MASK + 10U, // PseudoVAMOMINEI16_WD_M1_MF2 + 10U, // PseudoVAMOMINEI16_WD_M1_MF2_MASK + 10U, // PseudoVAMOMINEI16_WD_M1_MF4 + 10U, // PseudoVAMOMINEI16_WD_M1_MF4_MASK + 10U, // PseudoVAMOMINEI16_WD_M2_M1 + 10U, // PseudoVAMOMINEI16_WD_M2_M1_MASK + 10U, // PseudoVAMOMINEI16_WD_M2_MF2 + 10U, // PseudoVAMOMINEI16_WD_M2_MF2_MASK + 10U, // PseudoVAMOMINEI16_WD_M4_M1 + 10U, // PseudoVAMOMINEI16_WD_M4_M1_MASK + 10U, // PseudoVAMOMINEI16_WD_M4_M2 + 10U, // PseudoVAMOMINEI16_WD_M4_M2_MASK + 10U, // PseudoVAMOMINEI16_WD_M8_M2 + 10U, // PseudoVAMOMINEI16_WD_M8_M2_MASK + 10U, // PseudoVAMOMINEI16_WD_M8_M4 + 10U, // PseudoVAMOMINEI16_WD_M8_M4_MASK + 10U, // PseudoVAMOMINEI16_WD_MF2_MF4 + 10U, // PseudoVAMOMINEI16_WD_MF2_MF4_MASK + 10U, // PseudoVAMOMINEI32_WD_M1_M1 + 10U, // PseudoVAMOMINEI32_WD_M1_M1_MASK + 10U, // PseudoVAMOMINEI32_WD_M1_MF2 + 10U, // PseudoVAMOMINEI32_WD_M1_MF2_MASK + 10U, // PseudoVAMOMINEI32_WD_M2_M1 + 10U, // PseudoVAMOMINEI32_WD_M2_M1_MASK + 10U, // PseudoVAMOMINEI32_WD_M2_M2 + 10U, // PseudoVAMOMINEI32_WD_M2_M2_MASK + 10U, // PseudoVAMOMINEI32_WD_M4_M2 + 10U, // PseudoVAMOMINEI32_WD_M4_M2_MASK + 10U, // PseudoVAMOMINEI32_WD_M4_M4 + 10U, // PseudoVAMOMINEI32_WD_M4_M4_MASK + 10U, // PseudoVAMOMINEI32_WD_M8_M4 + 10U, // PseudoVAMOMINEI32_WD_M8_M4_MASK + 10U, // PseudoVAMOMINEI32_WD_M8_M8 + 10U, // PseudoVAMOMINEI32_WD_M8_M8_MASK + 10U, // PseudoVAMOMINEI32_WD_MF2_MF2 + 10U, // PseudoVAMOMINEI32_WD_MF2_MF2_MASK + 10U, // PseudoVAMOMINEI64_WD_M1_M1 + 10U, // PseudoVAMOMINEI64_WD_M1_M1_MASK + 10U, // PseudoVAMOMINEI64_WD_M1_M2 + 10U, // PseudoVAMOMINEI64_WD_M1_M2_MASK + 10U, // PseudoVAMOMINEI64_WD_M2_M2 + 10U, // PseudoVAMOMINEI64_WD_M2_M2_MASK + 10U, // PseudoVAMOMINEI64_WD_M2_M4 + 10U, // PseudoVAMOMINEI64_WD_M2_M4_MASK + 10U, // PseudoVAMOMINEI64_WD_M4_M4 + 10U, // PseudoVAMOMINEI64_WD_M4_M4_MASK + 10U, // PseudoVAMOMINEI64_WD_M4_M8 + 10U, // PseudoVAMOMINEI64_WD_M4_M8_MASK + 10U, // PseudoVAMOMINEI64_WD_M8_M8 + 10U, // PseudoVAMOMINEI64_WD_M8_M8_MASK + 10U, // PseudoVAMOMINEI64_WD_MF2_M1 + 10U, // PseudoVAMOMINEI64_WD_MF2_M1_MASK + 10U, // PseudoVAMOMINEI8_WD_M1_MF4 + 10U, // PseudoVAMOMINEI8_WD_M1_MF4_MASK + 10U, // PseudoVAMOMINEI8_WD_M1_MF8 + 10U, // PseudoVAMOMINEI8_WD_M1_MF8_MASK + 10U, // PseudoVAMOMINEI8_WD_M2_MF2 + 10U, // PseudoVAMOMINEI8_WD_M2_MF2_MASK + 10U, // PseudoVAMOMINEI8_WD_M2_MF4 + 10U, // PseudoVAMOMINEI8_WD_M2_MF4_MASK + 10U, // PseudoVAMOMINEI8_WD_M4_M1 + 10U, // PseudoVAMOMINEI8_WD_M4_M1_MASK + 10U, // PseudoVAMOMINEI8_WD_M4_MF2 + 10U, // PseudoVAMOMINEI8_WD_M4_MF2_MASK + 10U, // PseudoVAMOMINEI8_WD_M8_M1 + 10U, // PseudoVAMOMINEI8_WD_M8_M1_MASK + 10U, // PseudoVAMOMINEI8_WD_M8_M2 + 10U, // PseudoVAMOMINEI8_WD_M8_M2_MASK + 10U, // PseudoVAMOMINEI8_WD_MF2_MF8 + 10U, // PseudoVAMOMINEI8_WD_MF2_MF8_MASK + 10U, // PseudoVAMOMINUEI16_WD_M1_MF2 + 10U, // PseudoVAMOMINUEI16_WD_M1_MF2_MASK + 10U, // PseudoVAMOMINUEI16_WD_M1_MF4 + 10U, // PseudoVAMOMINUEI16_WD_M1_MF4_MASK + 10U, // PseudoVAMOMINUEI16_WD_M2_M1 + 10U, // PseudoVAMOMINUEI16_WD_M2_M1_MASK + 10U, // PseudoVAMOMINUEI16_WD_M2_MF2 + 10U, // PseudoVAMOMINUEI16_WD_M2_MF2_MASK + 10U, // PseudoVAMOMINUEI16_WD_M4_M1 + 10U, // PseudoVAMOMINUEI16_WD_M4_M1_MASK + 10U, // PseudoVAMOMINUEI16_WD_M4_M2 + 10U, // PseudoVAMOMINUEI16_WD_M4_M2_MASK + 10U, // PseudoVAMOMINUEI16_WD_M8_M2 + 10U, // PseudoVAMOMINUEI16_WD_M8_M2_MASK + 10U, // PseudoVAMOMINUEI16_WD_M8_M4 + 10U, // PseudoVAMOMINUEI16_WD_M8_M4_MASK + 10U, // PseudoVAMOMINUEI16_WD_MF2_MF4 + 10U, // PseudoVAMOMINUEI16_WD_MF2_MF4_MASK + 10U, // PseudoVAMOMINUEI32_WD_M1_M1 + 10U, // PseudoVAMOMINUEI32_WD_M1_M1_MASK + 10U, // PseudoVAMOMINUEI32_WD_M1_MF2 + 10U, // PseudoVAMOMINUEI32_WD_M1_MF2_MASK + 10U, // PseudoVAMOMINUEI32_WD_M2_M1 + 10U, // PseudoVAMOMINUEI32_WD_M2_M1_MASK + 10U, // PseudoVAMOMINUEI32_WD_M2_M2 + 10U, // PseudoVAMOMINUEI32_WD_M2_M2_MASK + 10U, // PseudoVAMOMINUEI32_WD_M4_M2 + 10U, // PseudoVAMOMINUEI32_WD_M4_M2_MASK + 10U, // PseudoVAMOMINUEI32_WD_M4_M4 + 10U, // PseudoVAMOMINUEI32_WD_M4_M4_MASK + 10U, // PseudoVAMOMINUEI32_WD_M8_M4 + 10U, // PseudoVAMOMINUEI32_WD_M8_M4_MASK + 10U, // PseudoVAMOMINUEI32_WD_M8_M8 + 10U, // PseudoVAMOMINUEI32_WD_M8_M8_MASK + 10U, // PseudoVAMOMINUEI32_WD_MF2_MF2 + 10U, // PseudoVAMOMINUEI32_WD_MF2_MF2_MASK + 10U, // PseudoVAMOMINUEI64_WD_M1_M1 + 10U, // PseudoVAMOMINUEI64_WD_M1_M1_MASK + 10U, // PseudoVAMOMINUEI64_WD_M1_M2 + 10U, // PseudoVAMOMINUEI64_WD_M1_M2_MASK + 10U, // PseudoVAMOMINUEI64_WD_M2_M2 + 10U, // PseudoVAMOMINUEI64_WD_M2_M2_MASK + 10U, // PseudoVAMOMINUEI64_WD_M2_M4 + 10U, // PseudoVAMOMINUEI64_WD_M2_M4_MASK + 10U, // PseudoVAMOMINUEI64_WD_M4_M4 + 10U, // PseudoVAMOMINUEI64_WD_M4_M4_MASK + 10U, // PseudoVAMOMINUEI64_WD_M4_M8 + 10U, // PseudoVAMOMINUEI64_WD_M4_M8_MASK + 10U, // PseudoVAMOMINUEI64_WD_M8_M8 + 10U, // PseudoVAMOMINUEI64_WD_M8_M8_MASK + 10U, // PseudoVAMOMINUEI64_WD_MF2_M1 + 10U, // PseudoVAMOMINUEI64_WD_MF2_M1_MASK + 10U, // PseudoVAMOMINUEI8_WD_M1_MF4 + 10U, // PseudoVAMOMINUEI8_WD_M1_MF4_MASK + 10U, // PseudoVAMOMINUEI8_WD_M1_MF8 + 10U, // PseudoVAMOMINUEI8_WD_M1_MF8_MASK + 10U, // PseudoVAMOMINUEI8_WD_M2_MF2 + 10U, // PseudoVAMOMINUEI8_WD_M2_MF2_MASK + 10U, // PseudoVAMOMINUEI8_WD_M2_MF4 + 10U, // PseudoVAMOMINUEI8_WD_M2_MF4_MASK + 10U, // PseudoVAMOMINUEI8_WD_M4_M1 + 10U, // PseudoVAMOMINUEI8_WD_M4_M1_MASK + 10U, // PseudoVAMOMINUEI8_WD_M4_MF2 + 10U, // PseudoVAMOMINUEI8_WD_M4_MF2_MASK + 10U, // PseudoVAMOMINUEI8_WD_M8_M1 + 10U, // PseudoVAMOMINUEI8_WD_M8_M1_MASK + 10U, // PseudoVAMOMINUEI8_WD_M8_M2 + 10U, // PseudoVAMOMINUEI8_WD_M8_M2_MASK + 10U, // PseudoVAMOMINUEI8_WD_MF2_MF8 + 10U, // PseudoVAMOMINUEI8_WD_MF2_MF8_MASK + 10U, // PseudoVAMOOREI16_WD_M1_MF2 + 10U, // PseudoVAMOOREI16_WD_M1_MF2_MASK + 10U, // PseudoVAMOOREI16_WD_M1_MF4 + 10U, // PseudoVAMOOREI16_WD_M1_MF4_MASK + 10U, // PseudoVAMOOREI16_WD_M2_M1 + 10U, // PseudoVAMOOREI16_WD_M2_M1_MASK + 10U, // PseudoVAMOOREI16_WD_M2_MF2 + 10U, // PseudoVAMOOREI16_WD_M2_MF2_MASK + 10U, // PseudoVAMOOREI16_WD_M4_M1 + 10U, // PseudoVAMOOREI16_WD_M4_M1_MASK + 10U, // PseudoVAMOOREI16_WD_M4_M2 + 10U, // PseudoVAMOOREI16_WD_M4_M2_MASK + 10U, // PseudoVAMOOREI16_WD_M8_M2 + 10U, // PseudoVAMOOREI16_WD_M8_M2_MASK + 10U, // PseudoVAMOOREI16_WD_M8_M4 + 10U, // PseudoVAMOOREI16_WD_M8_M4_MASK + 10U, // PseudoVAMOOREI16_WD_MF2_MF4 + 10U, // PseudoVAMOOREI16_WD_MF2_MF4_MASK + 10U, // PseudoVAMOOREI32_WD_M1_M1 + 10U, // PseudoVAMOOREI32_WD_M1_M1_MASK + 10U, // PseudoVAMOOREI32_WD_M1_MF2 + 10U, // PseudoVAMOOREI32_WD_M1_MF2_MASK + 10U, // PseudoVAMOOREI32_WD_M2_M1 + 10U, // PseudoVAMOOREI32_WD_M2_M1_MASK + 10U, // PseudoVAMOOREI32_WD_M2_M2 + 10U, // PseudoVAMOOREI32_WD_M2_M2_MASK + 10U, // PseudoVAMOOREI32_WD_M4_M2 + 10U, // PseudoVAMOOREI32_WD_M4_M2_MASK + 10U, // PseudoVAMOOREI32_WD_M4_M4 + 10U, // PseudoVAMOOREI32_WD_M4_M4_MASK + 10U, // PseudoVAMOOREI32_WD_M8_M4 + 10U, // PseudoVAMOOREI32_WD_M8_M4_MASK + 10U, // PseudoVAMOOREI32_WD_M8_M8 + 10U, // PseudoVAMOOREI32_WD_M8_M8_MASK + 10U, // PseudoVAMOOREI32_WD_MF2_MF2 + 10U, // PseudoVAMOOREI32_WD_MF2_MF2_MASK + 10U, // PseudoVAMOOREI64_WD_M1_M1 + 10U, // PseudoVAMOOREI64_WD_M1_M1_MASK + 10U, // PseudoVAMOOREI64_WD_M1_M2 + 10U, // PseudoVAMOOREI64_WD_M1_M2_MASK + 10U, // PseudoVAMOOREI64_WD_M2_M2 + 10U, // PseudoVAMOOREI64_WD_M2_M2_MASK + 10U, // PseudoVAMOOREI64_WD_M2_M4 + 10U, // PseudoVAMOOREI64_WD_M2_M4_MASK + 10U, // PseudoVAMOOREI64_WD_M4_M4 + 10U, // PseudoVAMOOREI64_WD_M4_M4_MASK + 10U, // PseudoVAMOOREI64_WD_M4_M8 + 10U, // PseudoVAMOOREI64_WD_M4_M8_MASK + 10U, // PseudoVAMOOREI64_WD_M8_M8 + 10U, // PseudoVAMOOREI64_WD_M8_M8_MASK + 10U, // PseudoVAMOOREI64_WD_MF2_M1 + 10U, // PseudoVAMOOREI64_WD_MF2_M1_MASK + 10U, // PseudoVAMOOREI8_WD_M1_MF4 + 10U, // PseudoVAMOOREI8_WD_M1_MF4_MASK + 10U, // PseudoVAMOOREI8_WD_M1_MF8 + 10U, // PseudoVAMOOREI8_WD_M1_MF8_MASK + 10U, // PseudoVAMOOREI8_WD_M2_MF2 + 10U, // PseudoVAMOOREI8_WD_M2_MF2_MASK + 10U, // PseudoVAMOOREI8_WD_M2_MF4 + 10U, // PseudoVAMOOREI8_WD_M2_MF4_MASK + 10U, // PseudoVAMOOREI8_WD_M4_M1 + 10U, // PseudoVAMOOREI8_WD_M4_M1_MASK + 10U, // PseudoVAMOOREI8_WD_M4_MF2 + 10U, // PseudoVAMOOREI8_WD_M4_MF2_MASK + 10U, // PseudoVAMOOREI8_WD_M8_M1 + 10U, // PseudoVAMOOREI8_WD_M8_M1_MASK + 10U, // PseudoVAMOOREI8_WD_M8_M2 + 10U, // PseudoVAMOOREI8_WD_M8_M2_MASK + 10U, // PseudoVAMOOREI8_WD_MF2_MF8 + 10U, // PseudoVAMOOREI8_WD_MF2_MF8_MASK + 10U, // PseudoVAMOSWAPEI16_WD_M1_MF2 + 10U, // PseudoVAMOSWAPEI16_WD_M1_MF2_MASK + 10U, // PseudoVAMOSWAPEI16_WD_M1_MF4 + 10U, // PseudoVAMOSWAPEI16_WD_M1_MF4_MASK + 10U, // PseudoVAMOSWAPEI16_WD_M2_M1 + 10U, // PseudoVAMOSWAPEI16_WD_M2_M1_MASK + 10U, // PseudoVAMOSWAPEI16_WD_M2_MF2 + 10U, // PseudoVAMOSWAPEI16_WD_M2_MF2_MASK + 10U, // PseudoVAMOSWAPEI16_WD_M4_M1 + 10U, // PseudoVAMOSWAPEI16_WD_M4_M1_MASK + 10U, // PseudoVAMOSWAPEI16_WD_M4_M2 + 10U, // PseudoVAMOSWAPEI16_WD_M4_M2_MASK + 10U, // PseudoVAMOSWAPEI16_WD_M8_M2 + 10U, // PseudoVAMOSWAPEI16_WD_M8_M2_MASK + 10U, // PseudoVAMOSWAPEI16_WD_M8_M4 + 10U, // PseudoVAMOSWAPEI16_WD_M8_M4_MASK + 10U, // PseudoVAMOSWAPEI16_WD_MF2_MF4 + 10U, // PseudoVAMOSWAPEI16_WD_MF2_MF4_MASK + 10U, // PseudoVAMOSWAPEI32_WD_M1_M1 + 10U, // PseudoVAMOSWAPEI32_WD_M1_M1_MASK + 10U, // PseudoVAMOSWAPEI32_WD_M1_MF2 + 10U, // PseudoVAMOSWAPEI32_WD_M1_MF2_MASK + 10U, // PseudoVAMOSWAPEI32_WD_M2_M1 + 10U, // PseudoVAMOSWAPEI32_WD_M2_M1_MASK + 10U, // PseudoVAMOSWAPEI32_WD_M2_M2 + 10U, // PseudoVAMOSWAPEI32_WD_M2_M2_MASK + 10U, // PseudoVAMOSWAPEI32_WD_M4_M2 + 10U, // PseudoVAMOSWAPEI32_WD_M4_M2_MASK + 10U, // PseudoVAMOSWAPEI32_WD_M4_M4 + 10U, // PseudoVAMOSWAPEI32_WD_M4_M4_MASK + 10U, // PseudoVAMOSWAPEI32_WD_M8_M4 + 10U, // PseudoVAMOSWAPEI32_WD_M8_M4_MASK + 10U, // PseudoVAMOSWAPEI32_WD_M8_M8 + 10U, // PseudoVAMOSWAPEI32_WD_M8_M8_MASK + 10U, // PseudoVAMOSWAPEI32_WD_MF2_MF2 + 10U, // PseudoVAMOSWAPEI32_WD_MF2_MF2_MASK + 10U, // PseudoVAMOSWAPEI64_WD_M1_M1 + 10U, // PseudoVAMOSWAPEI64_WD_M1_M1_MASK + 10U, // PseudoVAMOSWAPEI64_WD_M1_M2 + 10U, // PseudoVAMOSWAPEI64_WD_M1_M2_MASK + 10U, // PseudoVAMOSWAPEI64_WD_M2_M2 + 10U, // PseudoVAMOSWAPEI64_WD_M2_M2_MASK + 10U, // PseudoVAMOSWAPEI64_WD_M2_M4 + 10U, // PseudoVAMOSWAPEI64_WD_M2_M4_MASK + 10U, // PseudoVAMOSWAPEI64_WD_M4_M4 + 10U, // PseudoVAMOSWAPEI64_WD_M4_M4_MASK + 10U, // PseudoVAMOSWAPEI64_WD_M4_M8 + 10U, // PseudoVAMOSWAPEI64_WD_M4_M8_MASK + 10U, // PseudoVAMOSWAPEI64_WD_M8_M8 + 10U, // PseudoVAMOSWAPEI64_WD_M8_M8_MASK + 10U, // PseudoVAMOSWAPEI64_WD_MF2_M1 + 10U, // PseudoVAMOSWAPEI64_WD_MF2_M1_MASK + 10U, // PseudoVAMOSWAPEI8_WD_M1_MF4 + 10U, // PseudoVAMOSWAPEI8_WD_M1_MF4_MASK + 10U, // PseudoVAMOSWAPEI8_WD_M1_MF8 + 10U, // PseudoVAMOSWAPEI8_WD_M1_MF8_MASK + 10U, // PseudoVAMOSWAPEI8_WD_M2_MF2 + 10U, // PseudoVAMOSWAPEI8_WD_M2_MF2_MASK + 10U, // PseudoVAMOSWAPEI8_WD_M2_MF4 + 10U, // PseudoVAMOSWAPEI8_WD_M2_MF4_MASK + 10U, // PseudoVAMOSWAPEI8_WD_M4_M1 + 10U, // PseudoVAMOSWAPEI8_WD_M4_M1_MASK + 10U, // PseudoVAMOSWAPEI8_WD_M4_MF2 + 10U, // PseudoVAMOSWAPEI8_WD_M4_MF2_MASK + 10U, // PseudoVAMOSWAPEI8_WD_M8_M1 + 10U, // PseudoVAMOSWAPEI8_WD_M8_M1_MASK + 10U, // PseudoVAMOSWAPEI8_WD_M8_M2 + 10U, // PseudoVAMOSWAPEI8_WD_M8_M2_MASK + 10U, // PseudoVAMOSWAPEI8_WD_MF2_MF8 + 10U, // PseudoVAMOSWAPEI8_WD_MF2_MF8_MASK + 10U, // PseudoVAMOXOREI16_WD_M1_MF2 + 10U, // PseudoVAMOXOREI16_WD_M1_MF2_MASK + 10U, // PseudoVAMOXOREI16_WD_M1_MF4 + 10U, // PseudoVAMOXOREI16_WD_M1_MF4_MASK + 10U, // PseudoVAMOXOREI16_WD_M2_M1 + 10U, // PseudoVAMOXOREI16_WD_M2_M1_MASK + 10U, // PseudoVAMOXOREI16_WD_M2_MF2 + 10U, // PseudoVAMOXOREI16_WD_M2_MF2_MASK + 10U, // PseudoVAMOXOREI16_WD_M4_M1 + 10U, // PseudoVAMOXOREI16_WD_M4_M1_MASK + 10U, // PseudoVAMOXOREI16_WD_M4_M2 + 10U, // PseudoVAMOXOREI16_WD_M4_M2_MASK + 10U, // PseudoVAMOXOREI16_WD_M8_M2 + 10U, // PseudoVAMOXOREI16_WD_M8_M2_MASK + 10U, // PseudoVAMOXOREI16_WD_M8_M4 + 10U, // PseudoVAMOXOREI16_WD_M8_M4_MASK + 10U, // PseudoVAMOXOREI16_WD_MF2_MF4 + 10U, // PseudoVAMOXOREI16_WD_MF2_MF4_MASK + 10U, // PseudoVAMOXOREI32_WD_M1_M1 + 10U, // PseudoVAMOXOREI32_WD_M1_M1_MASK + 10U, // PseudoVAMOXOREI32_WD_M1_MF2 + 10U, // PseudoVAMOXOREI32_WD_M1_MF2_MASK + 10U, // PseudoVAMOXOREI32_WD_M2_M1 + 10U, // PseudoVAMOXOREI32_WD_M2_M1_MASK + 10U, // PseudoVAMOXOREI32_WD_M2_M2 + 10U, // PseudoVAMOXOREI32_WD_M2_M2_MASK + 10U, // PseudoVAMOXOREI32_WD_M4_M2 + 10U, // PseudoVAMOXOREI32_WD_M4_M2_MASK + 10U, // PseudoVAMOXOREI32_WD_M4_M4 + 10U, // PseudoVAMOXOREI32_WD_M4_M4_MASK + 10U, // PseudoVAMOXOREI32_WD_M8_M4 + 10U, // PseudoVAMOXOREI32_WD_M8_M4_MASK + 10U, // PseudoVAMOXOREI32_WD_M8_M8 + 10U, // PseudoVAMOXOREI32_WD_M8_M8_MASK + 10U, // PseudoVAMOXOREI32_WD_MF2_MF2 + 10U, // PseudoVAMOXOREI32_WD_MF2_MF2_MASK + 10U, // PseudoVAMOXOREI64_WD_M1_M1 + 10U, // PseudoVAMOXOREI64_WD_M1_M1_MASK + 10U, // PseudoVAMOXOREI64_WD_M1_M2 + 10U, // PseudoVAMOXOREI64_WD_M1_M2_MASK + 10U, // PseudoVAMOXOREI64_WD_M2_M2 + 10U, // PseudoVAMOXOREI64_WD_M2_M2_MASK + 10U, // PseudoVAMOXOREI64_WD_M2_M4 + 10U, // PseudoVAMOXOREI64_WD_M2_M4_MASK + 10U, // PseudoVAMOXOREI64_WD_M4_M4 + 10U, // PseudoVAMOXOREI64_WD_M4_M4_MASK + 10U, // PseudoVAMOXOREI64_WD_M4_M8 + 10U, // PseudoVAMOXOREI64_WD_M4_M8_MASK + 10U, // PseudoVAMOXOREI64_WD_M8_M8 + 10U, // PseudoVAMOXOREI64_WD_M8_M8_MASK + 10U, // PseudoVAMOXOREI64_WD_MF2_M1 + 10U, // PseudoVAMOXOREI64_WD_MF2_M1_MASK + 10U, // PseudoVAMOXOREI8_WD_M1_MF4 + 10U, // PseudoVAMOXOREI8_WD_M1_MF4_MASK + 10U, // PseudoVAMOXOREI8_WD_M1_MF8 + 10U, // PseudoVAMOXOREI8_WD_M1_MF8_MASK + 10U, // PseudoVAMOXOREI8_WD_M2_MF2 + 10U, // PseudoVAMOXOREI8_WD_M2_MF2_MASK + 10U, // PseudoVAMOXOREI8_WD_M2_MF4 + 10U, // PseudoVAMOXOREI8_WD_M2_MF4_MASK + 10U, // PseudoVAMOXOREI8_WD_M4_M1 + 10U, // PseudoVAMOXOREI8_WD_M4_M1_MASK + 10U, // PseudoVAMOXOREI8_WD_M4_MF2 + 10U, // PseudoVAMOXOREI8_WD_M4_MF2_MASK + 10U, // PseudoVAMOXOREI8_WD_M8_M1 + 10U, // PseudoVAMOXOREI8_WD_M8_M1_MASK + 10U, // PseudoVAMOXOREI8_WD_M8_M2 + 10U, // PseudoVAMOXOREI8_WD_M8_M2_MASK + 10U, // PseudoVAMOXOREI8_WD_MF2_MF8 + 10U, // PseudoVAMOXOREI8_WD_MF2_MF8_MASK + 10U, // PseudoVAND_VI_M1 + 10U, // PseudoVAND_VI_M1_MASK + 10U, // PseudoVAND_VI_M2 + 10U, // PseudoVAND_VI_M2_MASK + 10U, // PseudoVAND_VI_M4 + 10U, // PseudoVAND_VI_M4_MASK + 10U, // PseudoVAND_VI_M8 + 10U, // PseudoVAND_VI_M8_MASK + 10U, // PseudoVAND_VI_MF2 + 10U, // PseudoVAND_VI_MF2_MASK + 10U, // PseudoVAND_VI_MF4 + 10U, // PseudoVAND_VI_MF4_MASK + 10U, // PseudoVAND_VI_MF8 + 10U, // PseudoVAND_VI_MF8_MASK + 10U, // PseudoVAND_VV_M1 + 10U, // PseudoVAND_VV_M1_MASK + 10U, // PseudoVAND_VV_M2 + 10U, // PseudoVAND_VV_M2_MASK + 10U, // PseudoVAND_VV_M4 + 10U, // PseudoVAND_VV_M4_MASK + 10U, // PseudoVAND_VV_M8 + 10U, // PseudoVAND_VV_M8_MASK + 10U, // PseudoVAND_VV_MF2 + 10U, // PseudoVAND_VV_MF2_MASK + 10U, // PseudoVAND_VV_MF4 + 10U, // PseudoVAND_VV_MF4_MASK + 10U, // PseudoVAND_VV_MF8 + 10U, // PseudoVAND_VV_MF8_MASK + 10U, // PseudoVAND_VX_M1 + 10U, // PseudoVAND_VX_M1_MASK + 10U, // PseudoVAND_VX_M2 + 10U, // PseudoVAND_VX_M2_MASK + 10U, // PseudoVAND_VX_M4 + 10U, // PseudoVAND_VX_M4_MASK + 10U, // PseudoVAND_VX_M8 + 10U, // PseudoVAND_VX_M8_MASK + 10U, // PseudoVAND_VX_MF2 + 10U, // PseudoVAND_VX_MF2_MASK + 10U, // PseudoVAND_VX_MF4 + 10U, // PseudoVAND_VX_MF4_MASK + 10U, // PseudoVAND_VX_MF8 + 10U, // PseudoVAND_VX_MF8_MASK + 10U, // PseudoVASUBU_VV_M1 + 10U, // PseudoVASUBU_VV_M1_MASK + 10U, // PseudoVASUBU_VV_M2 + 10U, // PseudoVASUBU_VV_M2_MASK + 10U, // PseudoVASUBU_VV_M4 + 10U, // PseudoVASUBU_VV_M4_MASK + 10U, // PseudoVASUBU_VV_M8 + 10U, // PseudoVASUBU_VV_M8_MASK + 10U, // PseudoVASUBU_VV_MF2 + 10U, // PseudoVASUBU_VV_MF2_MASK + 10U, // PseudoVASUBU_VV_MF4 + 10U, // PseudoVASUBU_VV_MF4_MASK + 10U, // PseudoVASUBU_VV_MF8 + 10U, // PseudoVASUBU_VV_MF8_MASK + 10U, // PseudoVASUBU_VX_M1 + 10U, // PseudoVASUBU_VX_M1_MASK + 10U, // PseudoVASUBU_VX_M2 + 10U, // PseudoVASUBU_VX_M2_MASK + 10U, // PseudoVASUBU_VX_M4 + 10U, // PseudoVASUBU_VX_M4_MASK + 10U, // PseudoVASUBU_VX_M8 + 10U, // PseudoVASUBU_VX_M8_MASK + 10U, // PseudoVASUBU_VX_MF2 + 10U, // PseudoVASUBU_VX_MF2_MASK + 10U, // PseudoVASUBU_VX_MF4 + 10U, // PseudoVASUBU_VX_MF4_MASK + 10U, // PseudoVASUBU_VX_MF8 + 10U, // PseudoVASUBU_VX_MF8_MASK + 10U, // PseudoVASUB_VV_M1 + 10U, // PseudoVASUB_VV_M1_MASK + 10U, // PseudoVASUB_VV_M2 + 10U, // PseudoVASUB_VV_M2_MASK + 10U, // PseudoVASUB_VV_M4 + 10U, // PseudoVASUB_VV_M4_MASK + 10U, // PseudoVASUB_VV_M8 + 10U, // PseudoVASUB_VV_M8_MASK + 10U, // PseudoVASUB_VV_MF2 + 10U, // PseudoVASUB_VV_MF2_MASK + 10U, // PseudoVASUB_VV_MF4 + 10U, // PseudoVASUB_VV_MF4_MASK + 10U, // PseudoVASUB_VV_MF8 + 10U, // PseudoVASUB_VV_MF8_MASK + 10U, // PseudoVASUB_VX_M1 + 10U, // PseudoVASUB_VX_M1_MASK + 10U, // PseudoVASUB_VX_M2 + 10U, // PseudoVASUB_VX_M2_MASK + 10U, // PseudoVASUB_VX_M4 + 10U, // PseudoVASUB_VX_M4_MASK + 10U, // PseudoVASUB_VX_M8 + 10U, // PseudoVASUB_VX_M8_MASK + 10U, // PseudoVASUB_VX_MF2 + 10U, // PseudoVASUB_VX_MF2_MASK + 10U, // PseudoVASUB_VX_MF4 + 10U, // PseudoVASUB_VX_MF4_MASK + 10U, // PseudoVASUB_VX_MF8 + 10U, // PseudoVASUB_VX_MF8_MASK + 10U, // PseudoVCOMPRESS_VM_M1 + 10U, // PseudoVCOMPRESS_VM_M2 + 10U, // PseudoVCOMPRESS_VM_M4 + 10U, // PseudoVCOMPRESS_VM_M8 + 10U, // PseudoVCOMPRESS_VM_MF2 + 10U, // PseudoVCOMPRESS_VM_MF4 + 10U, // PseudoVCOMPRESS_VM_MF8 + 10U, // PseudoVCPOP_M_B1 + 10U, // PseudoVCPOP_M_B16 + 10U, // PseudoVCPOP_M_B16_MASK + 10U, // PseudoVCPOP_M_B1_MASK + 10U, // PseudoVCPOP_M_B2 + 10U, // PseudoVCPOP_M_B2_MASK + 10U, // PseudoVCPOP_M_B32 + 10U, // PseudoVCPOP_M_B32_MASK + 10U, // PseudoVCPOP_M_B4 + 10U, // PseudoVCPOP_M_B4_MASK + 10U, // PseudoVCPOP_M_B64 + 10U, // PseudoVCPOP_M_B64_MASK + 10U, // PseudoVCPOP_M_B8 + 10U, // PseudoVCPOP_M_B8_MASK + 10U, // PseudoVDIVU_VV_M1 + 10U, // PseudoVDIVU_VV_M1_MASK + 10U, // PseudoVDIVU_VV_M2 + 10U, // PseudoVDIVU_VV_M2_MASK + 10U, // PseudoVDIVU_VV_M4 + 10U, // PseudoVDIVU_VV_M4_MASK + 10U, // PseudoVDIVU_VV_M8 + 10U, // PseudoVDIVU_VV_M8_MASK + 10U, // PseudoVDIVU_VV_MF2 + 10U, // PseudoVDIVU_VV_MF2_MASK + 10U, // PseudoVDIVU_VV_MF4 + 10U, // PseudoVDIVU_VV_MF4_MASK + 10U, // PseudoVDIVU_VV_MF8 + 10U, // PseudoVDIVU_VV_MF8_MASK + 10U, // PseudoVDIVU_VX_M1 + 10U, // PseudoVDIVU_VX_M1_MASK + 10U, // PseudoVDIVU_VX_M2 + 10U, // PseudoVDIVU_VX_M2_MASK + 10U, // PseudoVDIVU_VX_M4 + 10U, // PseudoVDIVU_VX_M4_MASK + 10U, // PseudoVDIVU_VX_M8 + 10U, // PseudoVDIVU_VX_M8_MASK + 10U, // PseudoVDIVU_VX_MF2 + 10U, // PseudoVDIVU_VX_MF2_MASK + 10U, // PseudoVDIVU_VX_MF4 + 10U, // PseudoVDIVU_VX_MF4_MASK + 10U, // PseudoVDIVU_VX_MF8 + 10U, // PseudoVDIVU_VX_MF8_MASK + 10U, // PseudoVDIV_VV_M1 + 10U, // PseudoVDIV_VV_M1_MASK + 10U, // PseudoVDIV_VV_M2 + 10U, // PseudoVDIV_VV_M2_MASK + 10U, // PseudoVDIV_VV_M4 + 10U, // PseudoVDIV_VV_M4_MASK + 10U, // PseudoVDIV_VV_M8 + 10U, // PseudoVDIV_VV_M8_MASK + 10U, // PseudoVDIV_VV_MF2 + 10U, // PseudoVDIV_VV_MF2_MASK + 10U, // PseudoVDIV_VV_MF4 + 10U, // PseudoVDIV_VV_MF4_MASK + 10U, // PseudoVDIV_VV_MF8 + 10U, // PseudoVDIV_VV_MF8_MASK + 10U, // PseudoVDIV_VX_M1 + 10U, // PseudoVDIV_VX_M1_MASK + 10U, // PseudoVDIV_VX_M2 + 10U, // PseudoVDIV_VX_M2_MASK + 10U, // PseudoVDIV_VX_M4 + 10U, // PseudoVDIV_VX_M4_MASK + 10U, // PseudoVDIV_VX_M8 + 10U, // PseudoVDIV_VX_M8_MASK + 10U, // PseudoVDIV_VX_MF2 + 10U, // PseudoVDIV_VX_MF2_MASK + 10U, // PseudoVDIV_VX_MF4 + 10U, // PseudoVDIV_VX_MF4_MASK + 10U, // PseudoVDIV_VX_MF8 + 10U, // PseudoVDIV_VX_MF8_MASK + 10U, // PseudoVFADD_VF16_M1 + 10U, // PseudoVFADD_VF16_M1_MASK + 10U, // PseudoVFADD_VF16_M2 + 10U, // PseudoVFADD_VF16_M2_MASK + 10U, // PseudoVFADD_VF16_M4 + 10U, // PseudoVFADD_VF16_M4_MASK + 10U, // PseudoVFADD_VF16_M8 + 10U, // PseudoVFADD_VF16_M8_MASK + 10U, // PseudoVFADD_VF16_MF2 + 10U, // PseudoVFADD_VF16_MF2_MASK + 10U, // PseudoVFADD_VF16_MF4 + 10U, // PseudoVFADD_VF16_MF4_MASK + 10U, // PseudoVFADD_VF16_MF8 + 10U, // PseudoVFADD_VF16_MF8_MASK + 10U, // PseudoVFADD_VF32_M1 + 10U, // PseudoVFADD_VF32_M1_MASK + 10U, // PseudoVFADD_VF32_M2 + 10U, // PseudoVFADD_VF32_M2_MASK + 10U, // PseudoVFADD_VF32_M4 + 10U, // PseudoVFADD_VF32_M4_MASK + 10U, // PseudoVFADD_VF32_M8 + 10U, // PseudoVFADD_VF32_M8_MASK + 10U, // PseudoVFADD_VF32_MF2 + 10U, // PseudoVFADD_VF32_MF2_MASK + 10U, // PseudoVFADD_VF32_MF4 + 10U, // PseudoVFADD_VF32_MF4_MASK + 10U, // PseudoVFADD_VF32_MF8 + 10U, // PseudoVFADD_VF32_MF8_MASK + 10U, // PseudoVFADD_VF64_M1 + 10U, // PseudoVFADD_VF64_M1_MASK + 10U, // PseudoVFADD_VF64_M2 + 10U, // PseudoVFADD_VF64_M2_MASK + 10U, // PseudoVFADD_VF64_M4 + 10U, // PseudoVFADD_VF64_M4_MASK + 10U, // PseudoVFADD_VF64_M8 + 10U, // PseudoVFADD_VF64_M8_MASK + 10U, // PseudoVFADD_VF64_MF2 + 10U, // PseudoVFADD_VF64_MF2_MASK + 10U, // PseudoVFADD_VF64_MF4 + 10U, // PseudoVFADD_VF64_MF4_MASK + 10U, // PseudoVFADD_VF64_MF8 + 10U, // PseudoVFADD_VF64_MF8_MASK + 10U, // PseudoVFADD_VV_M1 + 10U, // PseudoVFADD_VV_M1_MASK + 10U, // PseudoVFADD_VV_M2 + 10U, // PseudoVFADD_VV_M2_MASK + 10U, // PseudoVFADD_VV_M4 + 10U, // PseudoVFADD_VV_M4_MASK + 10U, // PseudoVFADD_VV_M8 + 10U, // PseudoVFADD_VV_M8_MASK + 10U, // PseudoVFADD_VV_MF2 + 10U, // PseudoVFADD_VV_MF2_MASK + 10U, // PseudoVFADD_VV_MF4 + 10U, // PseudoVFADD_VV_MF4_MASK + 10U, // PseudoVFADD_VV_MF8 + 10U, // PseudoVFADD_VV_MF8_MASK + 10U, // PseudoVFCLASS_V_M1 + 10U, // PseudoVFCLASS_V_M1_MASK + 10U, // PseudoVFCLASS_V_M2 + 10U, // PseudoVFCLASS_V_M2_MASK + 10U, // PseudoVFCLASS_V_M4 + 10U, // PseudoVFCLASS_V_M4_MASK + 10U, // PseudoVFCLASS_V_M8 + 10U, // PseudoVFCLASS_V_M8_MASK + 10U, // PseudoVFCLASS_V_MF2 + 10U, // PseudoVFCLASS_V_MF2_MASK + 10U, // PseudoVFCLASS_V_MF4 + 10U, // PseudoVFCLASS_V_MF4_MASK + 10U, // PseudoVFCLASS_V_MF8 + 10U, // PseudoVFCLASS_V_MF8_MASK + 10U, // PseudoVFCVT_F_XU_V_M1 + 10U, // PseudoVFCVT_F_XU_V_M1_MASK + 10U, // PseudoVFCVT_F_XU_V_M2 + 10U, // PseudoVFCVT_F_XU_V_M2_MASK + 10U, // PseudoVFCVT_F_XU_V_M4 + 10U, // PseudoVFCVT_F_XU_V_M4_MASK + 10U, // PseudoVFCVT_F_XU_V_M8 + 10U, // PseudoVFCVT_F_XU_V_M8_MASK + 10U, // PseudoVFCVT_F_XU_V_MF2 + 10U, // PseudoVFCVT_F_XU_V_MF2_MASK + 10U, // PseudoVFCVT_F_XU_V_MF4 + 10U, // PseudoVFCVT_F_XU_V_MF4_MASK + 10U, // PseudoVFCVT_F_XU_V_MF8 + 10U, // PseudoVFCVT_F_XU_V_MF8_MASK + 10U, // PseudoVFCVT_F_X_V_M1 + 10U, // PseudoVFCVT_F_X_V_M1_MASK + 10U, // PseudoVFCVT_F_X_V_M2 + 10U, // PseudoVFCVT_F_X_V_M2_MASK + 10U, // PseudoVFCVT_F_X_V_M4 + 10U, // PseudoVFCVT_F_X_V_M4_MASK + 10U, // PseudoVFCVT_F_X_V_M8 + 10U, // PseudoVFCVT_F_X_V_M8_MASK + 10U, // PseudoVFCVT_F_X_V_MF2 + 10U, // PseudoVFCVT_F_X_V_MF2_MASK + 10U, // PseudoVFCVT_F_X_V_MF4 + 10U, // PseudoVFCVT_F_X_V_MF4_MASK + 10U, // PseudoVFCVT_F_X_V_MF8 + 10U, // PseudoVFCVT_F_X_V_MF8_MASK + 10U, // PseudoVFCVT_RTZ_XU_F_V_M1 + 10U, // PseudoVFCVT_RTZ_XU_F_V_M1_MASK + 10U, // PseudoVFCVT_RTZ_XU_F_V_M2 + 10U, // PseudoVFCVT_RTZ_XU_F_V_M2_MASK + 10U, // PseudoVFCVT_RTZ_XU_F_V_M4 + 10U, // PseudoVFCVT_RTZ_XU_F_V_M4_MASK + 10U, // PseudoVFCVT_RTZ_XU_F_V_M8 + 10U, // PseudoVFCVT_RTZ_XU_F_V_M8_MASK + 10U, // PseudoVFCVT_RTZ_XU_F_V_MF2 + 10U, // PseudoVFCVT_RTZ_XU_F_V_MF2_MASK + 10U, // PseudoVFCVT_RTZ_XU_F_V_MF4 + 10U, // PseudoVFCVT_RTZ_XU_F_V_MF4_MASK + 10U, // PseudoVFCVT_RTZ_XU_F_V_MF8 + 10U, // PseudoVFCVT_RTZ_XU_F_V_MF8_MASK + 10U, // PseudoVFCVT_RTZ_X_F_V_M1 + 10U, // PseudoVFCVT_RTZ_X_F_V_M1_MASK + 10U, // PseudoVFCVT_RTZ_X_F_V_M2 + 10U, // PseudoVFCVT_RTZ_X_F_V_M2_MASK + 10U, // PseudoVFCVT_RTZ_X_F_V_M4 + 10U, // PseudoVFCVT_RTZ_X_F_V_M4_MASK + 10U, // PseudoVFCVT_RTZ_X_F_V_M8 + 10U, // PseudoVFCVT_RTZ_X_F_V_M8_MASK + 10U, // PseudoVFCVT_RTZ_X_F_V_MF2 + 10U, // PseudoVFCVT_RTZ_X_F_V_MF2_MASK + 10U, // PseudoVFCVT_RTZ_X_F_V_MF4 + 10U, // PseudoVFCVT_RTZ_X_F_V_MF4_MASK + 10U, // PseudoVFCVT_RTZ_X_F_V_MF8 + 10U, // PseudoVFCVT_RTZ_X_F_V_MF8_MASK + 10U, // PseudoVFCVT_XU_F_V_M1 + 10U, // PseudoVFCVT_XU_F_V_M1_MASK + 10U, // PseudoVFCVT_XU_F_V_M2 + 10U, // PseudoVFCVT_XU_F_V_M2_MASK + 10U, // PseudoVFCVT_XU_F_V_M4 + 10U, // PseudoVFCVT_XU_F_V_M4_MASK + 10U, // PseudoVFCVT_XU_F_V_M8 + 10U, // PseudoVFCVT_XU_F_V_M8_MASK + 10U, // PseudoVFCVT_XU_F_V_MF2 + 10U, // PseudoVFCVT_XU_F_V_MF2_MASK + 10U, // PseudoVFCVT_XU_F_V_MF4 + 10U, // PseudoVFCVT_XU_F_V_MF4_MASK + 10U, // PseudoVFCVT_XU_F_V_MF8 + 10U, // PseudoVFCVT_XU_F_V_MF8_MASK + 10U, // PseudoVFCVT_X_F_V_M1 + 10U, // PseudoVFCVT_X_F_V_M1_MASK + 10U, // PseudoVFCVT_X_F_V_M2 + 10U, // PseudoVFCVT_X_F_V_M2_MASK + 10U, // PseudoVFCVT_X_F_V_M4 + 10U, // PseudoVFCVT_X_F_V_M4_MASK + 10U, // PseudoVFCVT_X_F_V_M8 + 10U, // PseudoVFCVT_X_F_V_M8_MASK + 10U, // PseudoVFCVT_X_F_V_MF2 + 10U, // PseudoVFCVT_X_F_V_MF2_MASK + 10U, // PseudoVFCVT_X_F_V_MF4 + 10U, // PseudoVFCVT_X_F_V_MF4_MASK + 10U, // PseudoVFCVT_X_F_V_MF8 + 10U, // PseudoVFCVT_X_F_V_MF8_MASK + 10U, // PseudoVFDIV_VF16_M1 + 10U, // PseudoVFDIV_VF16_M1_MASK + 10U, // PseudoVFDIV_VF16_M2 + 10U, // PseudoVFDIV_VF16_M2_MASK + 10U, // PseudoVFDIV_VF16_M4 + 10U, // PseudoVFDIV_VF16_M4_MASK + 10U, // PseudoVFDIV_VF16_M8 + 10U, // PseudoVFDIV_VF16_M8_MASK + 10U, // PseudoVFDIV_VF16_MF2 + 10U, // PseudoVFDIV_VF16_MF2_MASK + 10U, // PseudoVFDIV_VF16_MF4 + 10U, // PseudoVFDIV_VF16_MF4_MASK + 10U, // PseudoVFDIV_VF16_MF8 + 10U, // PseudoVFDIV_VF16_MF8_MASK + 10U, // PseudoVFDIV_VF32_M1 + 10U, // PseudoVFDIV_VF32_M1_MASK + 10U, // PseudoVFDIV_VF32_M2 + 10U, // PseudoVFDIV_VF32_M2_MASK + 10U, // PseudoVFDIV_VF32_M4 + 10U, // PseudoVFDIV_VF32_M4_MASK + 10U, // PseudoVFDIV_VF32_M8 + 10U, // PseudoVFDIV_VF32_M8_MASK + 10U, // PseudoVFDIV_VF32_MF2 + 10U, // PseudoVFDIV_VF32_MF2_MASK + 10U, // PseudoVFDIV_VF32_MF4 + 10U, // PseudoVFDIV_VF32_MF4_MASK + 10U, // PseudoVFDIV_VF32_MF8 + 10U, // PseudoVFDIV_VF32_MF8_MASK + 10U, // PseudoVFDIV_VF64_M1 + 10U, // PseudoVFDIV_VF64_M1_MASK + 10U, // PseudoVFDIV_VF64_M2 + 10U, // PseudoVFDIV_VF64_M2_MASK + 10U, // PseudoVFDIV_VF64_M4 + 10U, // PseudoVFDIV_VF64_M4_MASK + 10U, // PseudoVFDIV_VF64_M8 + 10U, // PseudoVFDIV_VF64_M8_MASK + 10U, // PseudoVFDIV_VF64_MF2 + 10U, // PseudoVFDIV_VF64_MF2_MASK + 10U, // PseudoVFDIV_VF64_MF4 + 10U, // PseudoVFDIV_VF64_MF4_MASK + 10U, // PseudoVFDIV_VF64_MF8 + 10U, // PseudoVFDIV_VF64_MF8_MASK + 10U, // PseudoVFDIV_VV_M1 + 10U, // PseudoVFDIV_VV_M1_MASK + 10U, // PseudoVFDIV_VV_M2 + 10U, // PseudoVFDIV_VV_M2_MASK + 10U, // PseudoVFDIV_VV_M4 + 10U, // PseudoVFDIV_VV_M4_MASK + 10U, // PseudoVFDIV_VV_M8 + 10U, // PseudoVFDIV_VV_M8_MASK + 10U, // PseudoVFDIV_VV_MF2 + 10U, // PseudoVFDIV_VV_MF2_MASK + 10U, // PseudoVFDIV_VV_MF4 + 10U, // PseudoVFDIV_VV_MF4_MASK + 10U, // PseudoVFDIV_VV_MF8 + 10U, // PseudoVFDIV_VV_MF8_MASK + 10U, // PseudoVFIRST_M_B1 + 10U, // PseudoVFIRST_M_B16 + 10U, // PseudoVFIRST_M_B16_MASK + 10U, // PseudoVFIRST_M_B1_MASK + 10U, // PseudoVFIRST_M_B2 + 10U, // PseudoVFIRST_M_B2_MASK + 10U, // PseudoVFIRST_M_B32 + 10U, // PseudoVFIRST_M_B32_MASK + 10U, // PseudoVFIRST_M_B4 + 10U, // PseudoVFIRST_M_B4_MASK + 10U, // PseudoVFIRST_M_B64 + 10U, // PseudoVFIRST_M_B64_MASK + 10U, // PseudoVFIRST_M_B8 + 10U, // PseudoVFIRST_M_B8_MASK + 10U, // PseudoVFMACC_VF16_M1 + 10U, // PseudoVFMACC_VF16_M1_MASK + 10U, // PseudoVFMACC_VF16_M2 + 10U, // PseudoVFMACC_VF16_M2_MASK + 10U, // PseudoVFMACC_VF16_M4 + 10U, // PseudoVFMACC_VF16_M4_MASK + 10U, // PseudoVFMACC_VF16_M8 + 10U, // PseudoVFMACC_VF16_M8_MASK + 10U, // PseudoVFMACC_VF16_MF2 + 10U, // PseudoVFMACC_VF16_MF2_MASK + 10U, // PseudoVFMACC_VF16_MF4 + 10U, // PseudoVFMACC_VF16_MF4_MASK + 10U, // PseudoVFMACC_VF16_MF8 + 10U, // PseudoVFMACC_VF16_MF8_MASK + 10U, // PseudoVFMACC_VF32_M1 + 10U, // PseudoVFMACC_VF32_M1_MASK + 10U, // PseudoVFMACC_VF32_M2 + 10U, // PseudoVFMACC_VF32_M2_MASK + 10U, // PseudoVFMACC_VF32_M4 + 10U, // PseudoVFMACC_VF32_M4_MASK + 10U, // PseudoVFMACC_VF32_M8 + 10U, // PseudoVFMACC_VF32_M8_MASK + 10U, // PseudoVFMACC_VF32_MF2 + 10U, // PseudoVFMACC_VF32_MF2_MASK + 10U, // PseudoVFMACC_VF32_MF4 + 10U, // PseudoVFMACC_VF32_MF4_MASK + 10U, // PseudoVFMACC_VF32_MF8 + 10U, // PseudoVFMACC_VF32_MF8_MASK + 10U, // PseudoVFMACC_VF64_M1 + 10U, // PseudoVFMACC_VF64_M1_MASK + 10U, // PseudoVFMACC_VF64_M2 + 10U, // PseudoVFMACC_VF64_M2_MASK + 10U, // PseudoVFMACC_VF64_M4 + 10U, // PseudoVFMACC_VF64_M4_MASK + 10U, // PseudoVFMACC_VF64_M8 + 10U, // PseudoVFMACC_VF64_M8_MASK + 10U, // PseudoVFMACC_VF64_MF2 + 10U, // PseudoVFMACC_VF64_MF2_MASK + 10U, // PseudoVFMACC_VF64_MF4 + 10U, // PseudoVFMACC_VF64_MF4_MASK + 10U, // PseudoVFMACC_VF64_MF8 + 10U, // PseudoVFMACC_VF64_MF8_MASK + 10U, // PseudoVFMACC_VV_M1 + 10U, // PseudoVFMACC_VV_M1_MASK + 10U, // PseudoVFMACC_VV_M2 + 10U, // PseudoVFMACC_VV_M2_MASK + 10U, // PseudoVFMACC_VV_M4 + 10U, // PseudoVFMACC_VV_M4_MASK + 10U, // PseudoVFMACC_VV_M8 + 10U, // PseudoVFMACC_VV_M8_MASK + 10U, // PseudoVFMACC_VV_MF2 + 10U, // PseudoVFMACC_VV_MF2_MASK + 10U, // PseudoVFMACC_VV_MF4 + 10U, // PseudoVFMACC_VV_MF4_MASK + 10U, // PseudoVFMACC_VV_MF8 + 10U, // PseudoVFMACC_VV_MF8_MASK + 10U, // PseudoVFMADD_VF16_M1 + 10U, // PseudoVFMADD_VF16_M1_MASK + 10U, // PseudoVFMADD_VF16_M2 + 10U, // PseudoVFMADD_VF16_M2_MASK + 10U, // PseudoVFMADD_VF16_M4 + 10U, // PseudoVFMADD_VF16_M4_MASK + 10U, // PseudoVFMADD_VF16_M8 + 10U, // PseudoVFMADD_VF16_M8_MASK + 10U, // PseudoVFMADD_VF16_MF2 + 10U, // PseudoVFMADD_VF16_MF2_MASK + 10U, // PseudoVFMADD_VF16_MF4 + 10U, // PseudoVFMADD_VF16_MF4_MASK + 10U, // PseudoVFMADD_VF16_MF8 + 10U, // PseudoVFMADD_VF16_MF8_MASK + 10U, // PseudoVFMADD_VF32_M1 + 10U, // PseudoVFMADD_VF32_M1_MASK + 10U, // PseudoVFMADD_VF32_M2 + 10U, // PseudoVFMADD_VF32_M2_MASK + 10U, // PseudoVFMADD_VF32_M4 + 10U, // PseudoVFMADD_VF32_M4_MASK + 10U, // PseudoVFMADD_VF32_M8 + 10U, // PseudoVFMADD_VF32_M8_MASK + 10U, // PseudoVFMADD_VF32_MF2 + 10U, // PseudoVFMADD_VF32_MF2_MASK + 10U, // PseudoVFMADD_VF32_MF4 + 10U, // PseudoVFMADD_VF32_MF4_MASK + 10U, // PseudoVFMADD_VF32_MF8 + 10U, // PseudoVFMADD_VF32_MF8_MASK + 10U, // PseudoVFMADD_VF64_M1 + 10U, // PseudoVFMADD_VF64_M1_MASK + 10U, // PseudoVFMADD_VF64_M2 + 10U, // PseudoVFMADD_VF64_M2_MASK + 10U, // PseudoVFMADD_VF64_M4 + 10U, // PseudoVFMADD_VF64_M4_MASK + 10U, // PseudoVFMADD_VF64_M8 + 10U, // PseudoVFMADD_VF64_M8_MASK + 10U, // PseudoVFMADD_VF64_MF2 + 10U, // PseudoVFMADD_VF64_MF2_MASK + 10U, // PseudoVFMADD_VF64_MF4 + 10U, // PseudoVFMADD_VF64_MF4_MASK + 10U, // PseudoVFMADD_VF64_MF8 + 10U, // PseudoVFMADD_VF64_MF8_MASK + 10U, // PseudoVFMADD_VV_M1 + 10U, // PseudoVFMADD_VV_M1_MASK + 10U, // PseudoVFMADD_VV_M2 + 10U, // PseudoVFMADD_VV_M2_MASK + 10U, // PseudoVFMADD_VV_M4 + 10U, // PseudoVFMADD_VV_M4_MASK + 10U, // PseudoVFMADD_VV_M8 + 10U, // PseudoVFMADD_VV_M8_MASK + 10U, // PseudoVFMADD_VV_MF2 + 10U, // PseudoVFMADD_VV_MF2_MASK + 10U, // PseudoVFMADD_VV_MF4 + 10U, // PseudoVFMADD_VV_MF4_MASK + 10U, // PseudoVFMADD_VV_MF8 + 10U, // PseudoVFMADD_VV_MF8_MASK + 10U, // PseudoVFMAX_VF16_M1 + 10U, // PseudoVFMAX_VF16_M1_MASK + 10U, // PseudoVFMAX_VF16_M2 + 10U, // PseudoVFMAX_VF16_M2_MASK + 10U, // PseudoVFMAX_VF16_M4 + 10U, // PseudoVFMAX_VF16_M4_MASK + 10U, // PseudoVFMAX_VF16_M8 + 10U, // PseudoVFMAX_VF16_M8_MASK + 10U, // PseudoVFMAX_VF16_MF2 + 10U, // PseudoVFMAX_VF16_MF2_MASK + 10U, // PseudoVFMAX_VF16_MF4 + 10U, // PseudoVFMAX_VF16_MF4_MASK + 10U, // PseudoVFMAX_VF16_MF8 + 10U, // PseudoVFMAX_VF16_MF8_MASK + 10U, // PseudoVFMAX_VF32_M1 + 10U, // PseudoVFMAX_VF32_M1_MASK + 10U, // PseudoVFMAX_VF32_M2 + 10U, // PseudoVFMAX_VF32_M2_MASK + 10U, // PseudoVFMAX_VF32_M4 + 10U, // PseudoVFMAX_VF32_M4_MASK + 10U, // PseudoVFMAX_VF32_M8 + 10U, // PseudoVFMAX_VF32_M8_MASK + 10U, // PseudoVFMAX_VF32_MF2 + 10U, // PseudoVFMAX_VF32_MF2_MASK + 10U, // PseudoVFMAX_VF32_MF4 + 10U, // PseudoVFMAX_VF32_MF4_MASK + 10U, // PseudoVFMAX_VF32_MF8 + 10U, // PseudoVFMAX_VF32_MF8_MASK + 10U, // PseudoVFMAX_VF64_M1 + 10U, // PseudoVFMAX_VF64_M1_MASK + 10U, // PseudoVFMAX_VF64_M2 + 10U, // PseudoVFMAX_VF64_M2_MASK + 10U, // PseudoVFMAX_VF64_M4 + 10U, // PseudoVFMAX_VF64_M4_MASK + 10U, // PseudoVFMAX_VF64_M8 + 10U, // PseudoVFMAX_VF64_M8_MASK + 10U, // PseudoVFMAX_VF64_MF2 + 10U, // PseudoVFMAX_VF64_MF2_MASK + 10U, // PseudoVFMAX_VF64_MF4 + 10U, // PseudoVFMAX_VF64_MF4_MASK + 10U, // PseudoVFMAX_VF64_MF8 + 10U, // PseudoVFMAX_VF64_MF8_MASK + 10U, // PseudoVFMAX_VV_M1 + 10U, // PseudoVFMAX_VV_M1_MASK + 10U, // PseudoVFMAX_VV_M2 + 10U, // PseudoVFMAX_VV_M2_MASK + 10U, // PseudoVFMAX_VV_M4 + 10U, // PseudoVFMAX_VV_M4_MASK + 10U, // PseudoVFMAX_VV_M8 + 10U, // PseudoVFMAX_VV_M8_MASK + 10U, // PseudoVFMAX_VV_MF2 + 10U, // PseudoVFMAX_VV_MF2_MASK + 10U, // PseudoVFMAX_VV_MF4 + 10U, // PseudoVFMAX_VV_MF4_MASK + 10U, // PseudoVFMAX_VV_MF8 + 10U, // PseudoVFMAX_VV_MF8_MASK + 10U, // PseudoVFMERGE_VF16M_M1 + 10U, // PseudoVFMERGE_VF16M_M2 + 10U, // PseudoVFMERGE_VF16M_M4 + 10U, // PseudoVFMERGE_VF16M_M8 + 10U, // PseudoVFMERGE_VF16M_MF2 + 10U, // PseudoVFMERGE_VF16M_MF4 + 10U, // PseudoVFMERGE_VF16M_MF8 + 10U, // PseudoVFMERGE_VF32M_M1 + 10U, // PseudoVFMERGE_VF32M_M2 + 10U, // PseudoVFMERGE_VF32M_M4 + 10U, // PseudoVFMERGE_VF32M_M8 + 10U, // PseudoVFMERGE_VF32M_MF2 + 10U, // PseudoVFMERGE_VF32M_MF4 + 10U, // PseudoVFMERGE_VF32M_MF8 + 10U, // PseudoVFMERGE_VF64M_M1 + 10U, // PseudoVFMERGE_VF64M_M2 + 10U, // PseudoVFMERGE_VF64M_M4 + 10U, // PseudoVFMERGE_VF64M_M8 + 10U, // PseudoVFMERGE_VF64M_MF2 + 10U, // PseudoVFMERGE_VF64M_MF4 + 10U, // PseudoVFMERGE_VF64M_MF8 + 10U, // PseudoVFMIN_VF16_M1 + 10U, // PseudoVFMIN_VF16_M1_MASK + 10U, // PseudoVFMIN_VF16_M2 + 10U, // PseudoVFMIN_VF16_M2_MASK + 10U, // PseudoVFMIN_VF16_M4 + 10U, // PseudoVFMIN_VF16_M4_MASK + 10U, // PseudoVFMIN_VF16_M8 + 10U, // PseudoVFMIN_VF16_M8_MASK + 10U, // PseudoVFMIN_VF16_MF2 + 10U, // PseudoVFMIN_VF16_MF2_MASK + 10U, // PseudoVFMIN_VF16_MF4 + 10U, // PseudoVFMIN_VF16_MF4_MASK + 10U, // PseudoVFMIN_VF16_MF8 + 10U, // PseudoVFMIN_VF16_MF8_MASK + 10U, // PseudoVFMIN_VF32_M1 + 10U, // PseudoVFMIN_VF32_M1_MASK + 10U, // PseudoVFMIN_VF32_M2 + 10U, // PseudoVFMIN_VF32_M2_MASK + 10U, // PseudoVFMIN_VF32_M4 + 10U, // PseudoVFMIN_VF32_M4_MASK + 10U, // PseudoVFMIN_VF32_M8 + 10U, // PseudoVFMIN_VF32_M8_MASK + 10U, // PseudoVFMIN_VF32_MF2 + 10U, // PseudoVFMIN_VF32_MF2_MASK + 10U, // PseudoVFMIN_VF32_MF4 + 10U, // PseudoVFMIN_VF32_MF4_MASK + 10U, // PseudoVFMIN_VF32_MF8 + 10U, // PseudoVFMIN_VF32_MF8_MASK + 10U, // PseudoVFMIN_VF64_M1 + 10U, // PseudoVFMIN_VF64_M1_MASK + 10U, // PseudoVFMIN_VF64_M2 + 10U, // PseudoVFMIN_VF64_M2_MASK + 10U, // PseudoVFMIN_VF64_M4 + 10U, // PseudoVFMIN_VF64_M4_MASK + 10U, // PseudoVFMIN_VF64_M8 + 10U, // PseudoVFMIN_VF64_M8_MASK + 10U, // PseudoVFMIN_VF64_MF2 + 10U, // PseudoVFMIN_VF64_MF2_MASK + 10U, // PseudoVFMIN_VF64_MF4 + 10U, // PseudoVFMIN_VF64_MF4_MASK + 10U, // PseudoVFMIN_VF64_MF8 + 10U, // PseudoVFMIN_VF64_MF8_MASK + 10U, // PseudoVFMIN_VV_M1 + 10U, // PseudoVFMIN_VV_M1_MASK + 10U, // PseudoVFMIN_VV_M2 + 10U, // PseudoVFMIN_VV_M2_MASK + 10U, // PseudoVFMIN_VV_M4 + 10U, // PseudoVFMIN_VV_M4_MASK + 10U, // PseudoVFMIN_VV_M8 + 10U, // PseudoVFMIN_VV_M8_MASK + 10U, // PseudoVFMIN_VV_MF2 + 10U, // PseudoVFMIN_VV_MF2_MASK + 10U, // PseudoVFMIN_VV_MF4 + 10U, // PseudoVFMIN_VV_MF4_MASK + 10U, // PseudoVFMIN_VV_MF8 + 10U, // PseudoVFMIN_VV_MF8_MASK + 10U, // PseudoVFMSAC_VF16_M1 + 10U, // PseudoVFMSAC_VF16_M1_MASK + 10U, // PseudoVFMSAC_VF16_M2 + 10U, // PseudoVFMSAC_VF16_M2_MASK + 10U, // PseudoVFMSAC_VF16_M4 + 10U, // PseudoVFMSAC_VF16_M4_MASK + 10U, // PseudoVFMSAC_VF16_M8 + 10U, // PseudoVFMSAC_VF16_M8_MASK + 10U, // PseudoVFMSAC_VF16_MF2 + 10U, // PseudoVFMSAC_VF16_MF2_MASK + 10U, // PseudoVFMSAC_VF16_MF4 + 10U, // PseudoVFMSAC_VF16_MF4_MASK + 10U, // PseudoVFMSAC_VF16_MF8 + 10U, // PseudoVFMSAC_VF16_MF8_MASK + 10U, // PseudoVFMSAC_VF32_M1 + 10U, // PseudoVFMSAC_VF32_M1_MASK + 10U, // PseudoVFMSAC_VF32_M2 + 10U, // PseudoVFMSAC_VF32_M2_MASK + 10U, // PseudoVFMSAC_VF32_M4 + 10U, // PseudoVFMSAC_VF32_M4_MASK + 10U, // PseudoVFMSAC_VF32_M8 + 10U, // PseudoVFMSAC_VF32_M8_MASK + 10U, // PseudoVFMSAC_VF32_MF2 + 10U, // PseudoVFMSAC_VF32_MF2_MASK + 10U, // PseudoVFMSAC_VF32_MF4 + 10U, // PseudoVFMSAC_VF32_MF4_MASK + 10U, // PseudoVFMSAC_VF32_MF8 + 10U, // PseudoVFMSAC_VF32_MF8_MASK + 10U, // PseudoVFMSAC_VF64_M1 + 10U, // PseudoVFMSAC_VF64_M1_MASK + 10U, // PseudoVFMSAC_VF64_M2 + 10U, // PseudoVFMSAC_VF64_M2_MASK + 10U, // PseudoVFMSAC_VF64_M4 + 10U, // PseudoVFMSAC_VF64_M4_MASK + 10U, // PseudoVFMSAC_VF64_M8 + 10U, // PseudoVFMSAC_VF64_M8_MASK + 10U, // PseudoVFMSAC_VF64_MF2 + 10U, // PseudoVFMSAC_VF64_MF2_MASK + 10U, // PseudoVFMSAC_VF64_MF4 + 10U, // PseudoVFMSAC_VF64_MF4_MASK + 10U, // PseudoVFMSAC_VF64_MF8 + 10U, // PseudoVFMSAC_VF64_MF8_MASK + 10U, // PseudoVFMSAC_VV_M1 + 10U, // PseudoVFMSAC_VV_M1_MASK + 10U, // PseudoVFMSAC_VV_M2 + 10U, // PseudoVFMSAC_VV_M2_MASK + 10U, // PseudoVFMSAC_VV_M4 + 10U, // PseudoVFMSAC_VV_M4_MASK + 10U, // PseudoVFMSAC_VV_M8 + 10U, // PseudoVFMSAC_VV_M8_MASK + 10U, // PseudoVFMSAC_VV_MF2 + 10U, // PseudoVFMSAC_VV_MF2_MASK + 10U, // PseudoVFMSAC_VV_MF4 + 10U, // PseudoVFMSAC_VV_MF4_MASK + 10U, // PseudoVFMSAC_VV_MF8 + 10U, // PseudoVFMSAC_VV_MF8_MASK + 10U, // PseudoVFMSUB_VF16_M1 + 10U, // PseudoVFMSUB_VF16_M1_MASK + 10U, // PseudoVFMSUB_VF16_M2 + 10U, // PseudoVFMSUB_VF16_M2_MASK + 10U, // PseudoVFMSUB_VF16_M4 + 10U, // PseudoVFMSUB_VF16_M4_MASK + 10U, // PseudoVFMSUB_VF16_M8 + 10U, // PseudoVFMSUB_VF16_M8_MASK + 10U, // PseudoVFMSUB_VF16_MF2 + 10U, // PseudoVFMSUB_VF16_MF2_MASK + 10U, // PseudoVFMSUB_VF16_MF4 + 10U, // PseudoVFMSUB_VF16_MF4_MASK + 10U, // PseudoVFMSUB_VF16_MF8 + 10U, // PseudoVFMSUB_VF16_MF8_MASK + 10U, // PseudoVFMSUB_VF32_M1 + 10U, // PseudoVFMSUB_VF32_M1_MASK + 10U, // PseudoVFMSUB_VF32_M2 + 10U, // PseudoVFMSUB_VF32_M2_MASK + 10U, // PseudoVFMSUB_VF32_M4 + 10U, // PseudoVFMSUB_VF32_M4_MASK + 10U, // PseudoVFMSUB_VF32_M8 + 10U, // PseudoVFMSUB_VF32_M8_MASK + 10U, // PseudoVFMSUB_VF32_MF2 + 10U, // PseudoVFMSUB_VF32_MF2_MASK + 10U, // PseudoVFMSUB_VF32_MF4 + 10U, // PseudoVFMSUB_VF32_MF4_MASK + 10U, // PseudoVFMSUB_VF32_MF8 + 10U, // PseudoVFMSUB_VF32_MF8_MASK + 10U, // PseudoVFMSUB_VF64_M1 + 10U, // PseudoVFMSUB_VF64_M1_MASK + 10U, // PseudoVFMSUB_VF64_M2 + 10U, // PseudoVFMSUB_VF64_M2_MASK + 10U, // PseudoVFMSUB_VF64_M4 + 10U, // PseudoVFMSUB_VF64_M4_MASK + 10U, // PseudoVFMSUB_VF64_M8 + 10U, // PseudoVFMSUB_VF64_M8_MASK + 10U, // PseudoVFMSUB_VF64_MF2 + 10U, // PseudoVFMSUB_VF64_MF2_MASK + 10U, // PseudoVFMSUB_VF64_MF4 + 10U, // PseudoVFMSUB_VF64_MF4_MASK + 10U, // PseudoVFMSUB_VF64_MF8 + 10U, // PseudoVFMSUB_VF64_MF8_MASK + 10U, // PseudoVFMSUB_VV_M1 + 10U, // PseudoVFMSUB_VV_M1_MASK + 10U, // PseudoVFMSUB_VV_M2 + 10U, // PseudoVFMSUB_VV_M2_MASK + 10U, // PseudoVFMSUB_VV_M4 + 10U, // PseudoVFMSUB_VV_M4_MASK + 10U, // PseudoVFMSUB_VV_M8 + 10U, // PseudoVFMSUB_VV_M8_MASK + 10U, // PseudoVFMSUB_VV_MF2 + 10U, // PseudoVFMSUB_VV_MF2_MASK + 10U, // PseudoVFMSUB_VV_MF4 + 10U, // PseudoVFMSUB_VV_MF4_MASK + 10U, // PseudoVFMSUB_VV_MF8 + 10U, // PseudoVFMSUB_VV_MF8_MASK + 10U, // PseudoVFMUL_VF16_M1 + 10U, // PseudoVFMUL_VF16_M1_MASK + 10U, // PseudoVFMUL_VF16_M2 + 10U, // PseudoVFMUL_VF16_M2_MASK + 10U, // PseudoVFMUL_VF16_M4 + 10U, // PseudoVFMUL_VF16_M4_MASK + 10U, // PseudoVFMUL_VF16_M8 + 10U, // PseudoVFMUL_VF16_M8_MASK + 10U, // PseudoVFMUL_VF16_MF2 + 10U, // PseudoVFMUL_VF16_MF2_MASK + 10U, // PseudoVFMUL_VF16_MF4 + 10U, // PseudoVFMUL_VF16_MF4_MASK + 10U, // PseudoVFMUL_VF16_MF8 + 10U, // PseudoVFMUL_VF16_MF8_MASK + 10U, // PseudoVFMUL_VF32_M1 + 10U, // PseudoVFMUL_VF32_M1_MASK + 10U, // PseudoVFMUL_VF32_M2 + 10U, // PseudoVFMUL_VF32_M2_MASK + 10U, // PseudoVFMUL_VF32_M4 + 10U, // PseudoVFMUL_VF32_M4_MASK + 10U, // PseudoVFMUL_VF32_M8 + 10U, // PseudoVFMUL_VF32_M8_MASK + 10U, // PseudoVFMUL_VF32_MF2 + 10U, // PseudoVFMUL_VF32_MF2_MASK + 10U, // PseudoVFMUL_VF32_MF4 + 10U, // PseudoVFMUL_VF32_MF4_MASK + 10U, // PseudoVFMUL_VF32_MF8 + 10U, // PseudoVFMUL_VF32_MF8_MASK + 10U, // PseudoVFMUL_VF64_M1 + 10U, // PseudoVFMUL_VF64_M1_MASK + 10U, // PseudoVFMUL_VF64_M2 + 10U, // PseudoVFMUL_VF64_M2_MASK + 10U, // PseudoVFMUL_VF64_M4 + 10U, // PseudoVFMUL_VF64_M4_MASK + 10U, // PseudoVFMUL_VF64_M8 + 10U, // PseudoVFMUL_VF64_M8_MASK + 10U, // PseudoVFMUL_VF64_MF2 + 10U, // PseudoVFMUL_VF64_MF2_MASK + 10U, // PseudoVFMUL_VF64_MF4 + 10U, // PseudoVFMUL_VF64_MF4_MASK + 10U, // PseudoVFMUL_VF64_MF8 + 10U, // PseudoVFMUL_VF64_MF8_MASK + 10U, // PseudoVFMUL_VV_M1 + 10U, // PseudoVFMUL_VV_M1_MASK + 10U, // PseudoVFMUL_VV_M2 + 10U, // PseudoVFMUL_VV_M2_MASK + 10U, // PseudoVFMUL_VV_M4 + 10U, // PseudoVFMUL_VV_M4_MASK + 10U, // PseudoVFMUL_VV_M8 + 10U, // PseudoVFMUL_VV_M8_MASK + 10U, // PseudoVFMUL_VV_MF2 + 10U, // PseudoVFMUL_VV_MF2_MASK + 10U, // PseudoVFMUL_VV_MF4 + 10U, // PseudoVFMUL_VV_MF4_MASK + 10U, // PseudoVFMUL_VV_MF8 + 10U, // PseudoVFMUL_VV_MF8_MASK + 10U, // PseudoVFMV_F16_S_M1 + 10U, // PseudoVFMV_F16_S_M2 + 10U, // PseudoVFMV_F16_S_M4 + 10U, // PseudoVFMV_F16_S_M8 + 10U, // PseudoVFMV_F16_S_MF2 + 10U, // PseudoVFMV_F16_S_MF4 + 10U, // PseudoVFMV_F16_S_MF8 + 10U, // PseudoVFMV_F32_S_M1 + 10U, // PseudoVFMV_F32_S_M2 + 10U, // PseudoVFMV_F32_S_M4 + 10U, // PseudoVFMV_F32_S_M8 + 10U, // PseudoVFMV_F32_S_MF2 + 10U, // PseudoVFMV_F32_S_MF4 + 10U, // PseudoVFMV_F32_S_MF8 + 10U, // PseudoVFMV_F64_S_M1 + 10U, // PseudoVFMV_F64_S_M2 + 10U, // PseudoVFMV_F64_S_M4 + 10U, // PseudoVFMV_F64_S_M8 + 10U, // PseudoVFMV_F64_S_MF2 + 10U, // PseudoVFMV_F64_S_MF4 + 10U, // PseudoVFMV_F64_S_MF8 + 10U, // PseudoVFMV_S_F16_M1 + 10U, // PseudoVFMV_S_F16_M2 + 10U, // PseudoVFMV_S_F16_M4 + 10U, // PseudoVFMV_S_F16_M8 + 10U, // PseudoVFMV_S_F16_MF2 + 10U, // PseudoVFMV_S_F16_MF4 + 10U, // PseudoVFMV_S_F16_MF8 + 10U, // PseudoVFMV_S_F32_M1 + 10U, // PseudoVFMV_S_F32_M2 + 10U, // PseudoVFMV_S_F32_M4 + 10U, // PseudoVFMV_S_F32_M8 + 10U, // PseudoVFMV_S_F32_MF2 + 10U, // PseudoVFMV_S_F32_MF4 + 10U, // PseudoVFMV_S_F32_MF8 + 10U, // PseudoVFMV_S_F64_M1 + 10U, // PseudoVFMV_S_F64_M2 + 10U, // PseudoVFMV_S_F64_M4 + 10U, // PseudoVFMV_S_F64_M8 + 10U, // PseudoVFMV_S_F64_MF2 + 10U, // PseudoVFMV_S_F64_MF4 + 10U, // PseudoVFMV_S_F64_MF8 + 10U, // PseudoVFMV_V_F16_M1 + 10U, // PseudoVFMV_V_F16_M2 + 10U, // PseudoVFMV_V_F16_M4 + 10U, // PseudoVFMV_V_F16_M8 + 10U, // PseudoVFMV_V_F16_MF2 + 10U, // PseudoVFMV_V_F16_MF4 + 10U, // PseudoVFMV_V_F16_MF8 + 10U, // PseudoVFMV_V_F32_M1 + 10U, // PseudoVFMV_V_F32_M2 + 10U, // PseudoVFMV_V_F32_M4 + 10U, // PseudoVFMV_V_F32_M8 + 10U, // PseudoVFMV_V_F32_MF2 + 10U, // PseudoVFMV_V_F32_MF4 + 10U, // PseudoVFMV_V_F32_MF8 + 10U, // PseudoVFMV_V_F64_M1 + 10U, // PseudoVFMV_V_F64_M2 + 10U, // PseudoVFMV_V_F64_M4 + 10U, // PseudoVFMV_V_F64_M8 + 10U, // PseudoVFMV_V_F64_MF2 + 10U, // PseudoVFMV_V_F64_MF4 + 10U, // PseudoVFMV_V_F64_MF8 + 10U, // PseudoVFNCVT_F_F_W_M1 + 10U, // PseudoVFNCVT_F_F_W_M1_MASK + 10U, // PseudoVFNCVT_F_F_W_M2 + 10U, // PseudoVFNCVT_F_F_W_M2_MASK + 10U, // PseudoVFNCVT_F_F_W_M4 + 10U, // PseudoVFNCVT_F_F_W_M4_MASK + 10U, // PseudoVFNCVT_F_F_W_MF2 + 10U, // PseudoVFNCVT_F_F_W_MF2_MASK + 10U, // PseudoVFNCVT_F_F_W_MF4 + 10U, // PseudoVFNCVT_F_F_W_MF4_MASK + 10U, // PseudoVFNCVT_F_F_W_MF8 + 10U, // PseudoVFNCVT_F_F_W_MF8_MASK + 10U, // PseudoVFNCVT_F_XU_W_M1 + 10U, // PseudoVFNCVT_F_XU_W_M1_MASK + 10U, // PseudoVFNCVT_F_XU_W_M2 + 10U, // PseudoVFNCVT_F_XU_W_M2_MASK + 10U, // PseudoVFNCVT_F_XU_W_M4 + 10U, // PseudoVFNCVT_F_XU_W_M4_MASK + 10U, // PseudoVFNCVT_F_XU_W_MF2 + 10U, // PseudoVFNCVT_F_XU_W_MF2_MASK + 10U, // PseudoVFNCVT_F_XU_W_MF4 + 10U, // PseudoVFNCVT_F_XU_W_MF4_MASK + 10U, // PseudoVFNCVT_F_XU_W_MF8 + 10U, // PseudoVFNCVT_F_XU_W_MF8_MASK + 10U, // PseudoVFNCVT_F_X_W_M1 + 10U, // PseudoVFNCVT_F_X_W_M1_MASK + 10U, // PseudoVFNCVT_F_X_W_M2 + 10U, // PseudoVFNCVT_F_X_W_M2_MASK + 10U, // PseudoVFNCVT_F_X_W_M4 + 10U, // PseudoVFNCVT_F_X_W_M4_MASK + 10U, // PseudoVFNCVT_F_X_W_MF2 + 10U, // PseudoVFNCVT_F_X_W_MF2_MASK + 10U, // PseudoVFNCVT_F_X_W_MF4 + 10U, // PseudoVFNCVT_F_X_W_MF4_MASK + 10U, // PseudoVFNCVT_F_X_W_MF8 + 10U, // PseudoVFNCVT_F_X_W_MF8_MASK + 10U, // PseudoVFNCVT_ROD_F_F_W_M1 + 10U, // PseudoVFNCVT_ROD_F_F_W_M1_MASK + 10U, // PseudoVFNCVT_ROD_F_F_W_M2 + 10U, // PseudoVFNCVT_ROD_F_F_W_M2_MASK + 10U, // PseudoVFNCVT_ROD_F_F_W_M4 + 10U, // PseudoVFNCVT_ROD_F_F_W_M4_MASK + 10U, // PseudoVFNCVT_ROD_F_F_W_MF2 + 10U, // PseudoVFNCVT_ROD_F_F_W_MF2_MASK + 10U, // PseudoVFNCVT_ROD_F_F_W_MF4 + 10U, // PseudoVFNCVT_ROD_F_F_W_MF4_MASK + 10U, // PseudoVFNCVT_ROD_F_F_W_MF8 + 10U, // PseudoVFNCVT_ROD_F_F_W_MF8_MASK + 10U, // PseudoVFNCVT_RTZ_XU_F_W_M1 + 10U, // PseudoVFNCVT_RTZ_XU_F_W_M1_MASK + 10U, // PseudoVFNCVT_RTZ_XU_F_W_M2 + 10U, // PseudoVFNCVT_RTZ_XU_F_W_M2_MASK + 10U, // PseudoVFNCVT_RTZ_XU_F_W_M4 + 10U, // PseudoVFNCVT_RTZ_XU_F_W_M4_MASK + 10U, // PseudoVFNCVT_RTZ_XU_F_W_MF2 + 10U, // PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK + 10U, // PseudoVFNCVT_RTZ_XU_F_W_MF4 + 10U, // PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK + 10U, // PseudoVFNCVT_RTZ_XU_F_W_MF8 + 10U, // PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK + 10U, // PseudoVFNCVT_RTZ_X_F_W_M1 + 10U, // PseudoVFNCVT_RTZ_X_F_W_M1_MASK + 10U, // PseudoVFNCVT_RTZ_X_F_W_M2 + 10U, // PseudoVFNCVT_RTZ_X_F_W_M2_MASK + 10U, // PseudoVFNCVT_RTZ_X_F_W_M4 + 10U, // PseudoVFNCVT_RTZ_X_F_W_M4_MASK + 10U, // PseudoVFNCVT_RTZ_X_F_W_MF2 + 10U, // PseudoVFNCVT_RTZ_X_F_W_MF2_MASK + 10U, // PseudoVFNCVT_RTZ_X_F_W_MF4 + 10U, // PseudoVFNCVT_RTZ_X_F_W_MF4_MASK + 10U, // PseudoVFNCVT_RTZ_X_F_W_MF8 + 10U, // PseudoVFNCVT_RTZ_X_F_W_MF8_MASK + 10U, // PseudoVFNCVT_XU_F_W_M1 + 10U, // PseudoVFNCVT_XU_F_W_M1_MASK + 10U, // PseudoVFNCVT_XU_F_W_M2 + 10U, // PseudoVFNCVT_XU_F_W_M2_MASK + 10U, // PseudoVFNCVT_XU_F_W_M4 + 10U, // PseudoVFNCVT_XU_F_W_M4_MASK + 10U, // PseudoVFNCVT_XU_F_W_MF2 + 10U, // PseudoVFNCVT_XU_F_W_MF2_MASK + 10U, // PseudoVFNCVT_XU_F_W_MF4 + 10U, // PseudoVFNCVT_XU_F_W_MF4_MASK + 10U, // PseudoVFNCVT_XU_F_W_MF8 + 10U, // PseudoVFNCVT_XU_F_W_MF8_MASK + 10U, // PseudoVFNCVT_X_F_W_M1 + 10U, // PseudoVFNCVT_X_F_W_M1_MASK + 10U, // PseudoVFNCVT_X_F_W_M2 + 10U, // PseudoVFNCVT_X_F_W_M2_MASK + 10U, // PseudoVFNCVT_X_F_W_M4 + 10U, // PseudoVFNCVT_X_F_W_M4_MASK + 10U, // PseudoVFNCVT_X_F_W_MF2 + 10U, // PseudoVFNCVT_X_F_W_MF2_MASK + 10U, // PseudoVFNCVT_X_F_W_MF4 + 10U, // PseudoVFNCVT_X_F_W_MF4_MASK + 10U, // PseudoVFNCVT_X_F_W_MF8 + 10U, // PseudoVFNCVT_X_F_W_MF8_MASK + 10U, // PseudoVFNMACC_VF16_M1 + 10U, // PseudoVFNMACC_VF16_M1_MASK + 10U, // PseudoVFNMACC_VF16_M2 + 10U, // PseudoVFNMACC_VF16_M2_MASK + 10U, // PseudoVFNMACC_VF16_M4 + 10U, // PseudoVFNMACC_VF16_M4_MASK + 10U, // PseudoVFNMACC_VF16_M8 + 10U, // PseudoVFNMACC_VF16_M8_MASK + 10U, // PseudoVFNMACC_VF16_MF2 + 10U, // PseudoVFNMACC_VF16_MF2_MASK + 10U, // PseudoVFNMACC_VF16_MF4 + 10U, // PseudoVFNMACC_VF16_MF4_MASK + 10U, // PseudoVFNMACC_VF16_MF8 + 10U, // PseudoVFNMACC_VF16_MF8_MASK + 10U, // PseudoVFNMACC_VF32_M1 + 10U, // PseudoVFNMACC_VF32_M1_MASK + 10U, // PseudoVFNMACC_VF32_M2 + 10U, // PseudoVFNMACC_VF32_M2_MASK + 10U, // PseudoVFNMACC_VF32_M4 + 10U, // PseudoVFNMACC_VF32_M4_MASK + 10U, // PseudoVFNMACC_VF32_M8 + 10U, // PseudoVFNMACC_VF32_M8_MASK + 10U, // PseudoVFNMACC_VF32_MF2 + 10U, // PseudoVFNMACC_VF32_MF2_MASK + 10U, // PseudoVFNMACC_VF32_MF4 + 10U, // PseudoVFNMACC_VF32_MF4_MASK + 10U, // PseudoVFNMACC_VF32_MF8 + 10U, // PseudoVFNMACC_VF32_MF8_MASK + 10U, // PseudoVFNMACC_VF64_M1 + 10U, // PseudoVFNMACC_VF64_M1_MASK + 10U, // PseudoVFNMACC_VF64_M2 + 10U, // PseudoVFNMACC_VF64_M2_MASK + 10U, // PseudoVFNMACC_VF64_M4 + 10U, // PseudoVFNMACC_VF64_M4_MASK + 10U, // PseudoVFNMACC_VF64_M8 + 10U, // PseudoVFNMACC_VF64_M8_MASK + 10U, // PseudoVFNMACC_VF64_MF2 + 10U, // PseudoVFNMACC_VF64_MF2_MASK + 10U, // PseudoVFNMACC_VF64_MF4 + 10U, // PseudoVFNMACC_VF64_MF4_MASK + 10U, // PseudoVFNMACC_VF64_MF8 + 10U, // PseudoVFNMACC_VF64_MF8_MASK + 10U, // PseudoVFNMACC_VV_M1 + 10U, // PseudoVFNMACC_VV_M1_MASK + 10U, // PseudoVFNMACC_VV_M2 + 10U, // PseudoVFNMACC_VV_M2_MASK + 10U, // PseudoVFNMACC_VV_M4 + 10U, // PseudoVFNMACC_VV_M4_MASK + 10U, // PseudoVFNMACC_VV_M8 + 10U, // PseudoVFNMACC_VV_M8_MASK + 10U, // PseudoVFNMACC_VV_MF2 + 10U, // PseudoVFNMACC_VV_MF2_MASK + 10U, // PseudoVFNMACC_VV_MF4 + 10U, // PseudoVFNMACC_VV_MF4_MASK + 10U, // PseudoVFNMACC_VV_MF8 + 10U, // PseudoVFNMACC_VV_MF8_MASK + 10U, // PseudoVFNMADD_VF16_M1 + 10U, // PseudoVFNMADD_VF16_M1_MASK + 10U, // PseudoVFNMADD_VF16_M2 + 10U, // PseudoVFNMADD_VF16_M2_MASK + 10U, // PseudoVFNMADD_VF16_M4 + 10U, // PseudoVFNMADD_VF16_M4_MASK + 10U, // PseudoVFNMADD_VF16_M8 + 10U, // PseudoVFNMADD_VF16_M8_MASK + 10U, // PseudoVFNMADD_VF16_MF2 + 10U, // PseudoVFNMADD_VF16_MF2_MASK + 10U, // PseudoVFNMADD_VF16_MF4 + 10U, // PseudoVFNMADD_VF16_MF4_MASK + 10U, // PseudoVFNMADD_VF16_MF8 + 10U, // PseudoVFNMADD_VF16_MF8_MASK + 10U, // PseudoVFNMADD_VF32_M1 + 10U, // PseudoVFNMADD_VF32_M1_MASK + 10U, // PseudoVFNMADD_VF32_M2 + 10U, // PseudoVFNMADD_VF32_M2_MASK + 10U, // PseudoVFNMADD_VF32_M4 + 10U, // PseudoVFNMADD_VF32_M4_MASK + 10U, // PseudoVFNMADD_VF32_M8 + 10U, // PseudoVFNMADD_VF32_M8_MASK + 10U, // PseudoVFNMADD_VF32_MF2 + 10U, // PseudoVFNMADD_VF32_MF2_MASK + 10U, // PseudoVFNMADD_VF32_MF4 + 10U, // PseudoVFNMADD_VF32_MF4_MASK + 10U, // PseudoVFNMADD_VF32_MF8 + 10U, // PseudoVFNMADD_VF32_MF8_MASK + 10U, // PseudoVFNMADD_VF64_M1 + 10U, // PseudoVFNMADD_VF64_M1_MASK + 10U, // PseudoVFNMADD_VF64_M2 + 10U, // PseudoVFNMADD_VF64_M2_MASK + 10U, // PseudoVFNMADD_VF64_M4 + 10U, // PseudoVFNMADD_VF64_M4_MASK + 10U, // PseudoVFNMADD_VF64_M8 + 10U, // PseudoVFNMADD_VF64_M8_MASK + 10U, // PseudoVFNMADD_VF64_MF2 + 10U, // PseudoVFNMADD_VF64_MF2_MASK + 10U, // PseudoVFNMADD_VF64_MF4 + 10U, // PseudoVFNMADD_VF64_MF4_MASK + 10U, // PseudoVFNMADD_VF64_MF8 + 10U, // PseudoVFNMADD_VF64_MF8_MASK + 10U, // PseudoVFNMADD_VV_M1 + 10U, // PseudoVFNMADD_VV_M1_MASK + 10U, // PseudoVFNMADD_VV_M2 + 10U, // PseudoVFNMADD_VV_M2_MASK + 10U, // PseudoVFNMADD_VV_M4 + 10U, // PseudoVFNMADD_VV_M4_MASK + 10U, // PseudoVFNMADD_VV_M8 + 10U, // PseudoVFNMADD_VV_M8_MASK + 10U, // PseudoVFNMADD_VV_MF2 + 10U, // PseudoVFNMADD_VV_MF2_MASK + 10U, // PseudoVFNMADD_VV_MF4 + 10U, // PseudoVFNMADD_VV_MF4_MASK + 10U, // PseudoVFNMADD_VV_MF8 + 10U, // PseudoVFNMADD_VV_MF8_MASK + 10U, // PseudoVFNMSAC_VF16_M1 + 10U, // PseudoVFNMSAC_VF16_M1_MASK + 10U, // PseudoVFNMSAC_VF16_M2 + 10U, // PseudoVFNMSAC_VF16_M2_MASK + 10U, // PseudoVFNMSAC_VF16_M4 + 10U, // PseudoVFNMSAC_VF16_M4_MASK + 10U, // PseudoVFNMSAC_VF16_M8 + 10U, // PseudoVFNMSAC_VF16_M8_MASK + 10U, // PseudoVFNMSAC_VF16_MF2 + 10U, // PseudoVFNMSAC_VF16_MF2_MASK + 10U, // PseudoVFNMSAC_VF16_MF4 + 10U, // PseudoVFNMSAC_VF16_MF4_MASK + 10U, // PseudoVFNMSAC_VF16_MF8 + 10U, // PseudoVFNMSAC_VF16_MF8_MASK + 10U, // PseudoVFNMSAC_VF32_M1 + 10U, // PseudoVFNMSAC_VF32_M1_MASK + 10U, // PseudoVFNMSAC_VF32_M2 + 10U, // PseudoVFNMSAC_VF32_M2_MASK + 10U, // PseudoVFNMSAC_VF32_M4 + 10U, // PseudoVFNMSAC_VF32_M4_MASK + 10U, // PseudoVFNMSAC_VF32_M8 + 10U, // PseudoVFNMSAC_VF32_M8_MASK + 10U, // PseudoVFNMSAC_VF32_MF2 + 10U, // PseudoVFNMSAC_VF32_MF2_MASK + 10U, // PseudoVFNMSAC_VF32_MF4 + 10U, // PseudoVFNMSAC_VF32_MF4_MASK + 10U, // PseudoVFNMSAC_VF32_MF8 + 10U, // PseudoVFNMSAC_VF32_MF8_MASK + 10U, // PseudoVFNMSAC_VF64_M1 + 10U, // PseudoVFNMSAC_VF64_M1_MASK + 10U, // PseudoVFNMSAC_VF64_M2 + 10U, // PseudoVFNMSAC_VF64_M2_MASK + 10U, // PseudoVFNMSAC_VF64_M4 + 10U, // PseudoVFNMSAC_VF64_M4_MASK + 10U, // PseudoVFNMSAC_VF64_M8 + 10U, // PseudoVFNMSAC_VF64_M8_MASK + 10U, // PseudoVFNMSAC_VF64_MF2 + 10U, // PseudoVFNMSAC_VF64_MF2_MASK + 10U, // PseudoVFNMSAC_VF64_MF4 + 10U, // PseudoVFNMSAC_VF64_MF4_MASK + 10U, // PseudoVFNMSAC_VF64_MF8 + 10U, // PseudoVFNMSAC_VF64_MF8_MASK + 10U, // PseudoVFNMSAC_VV_M1 + 10U, // PseudoVFNMSAC_VV_M1_MASK + 10U, // PseudoVFNMSAC_VV_M2 + 10U, // PseudoVFNMSAC_VV_M2_MASK + 10U, // PseudoVFNMSAC_VV_M4 + 10U, // PseudoVFNMSAC_VV_M4_MASK + 10U, // PseudoVFNMSAC_VV_M8 + 10U, // PseudoVFNMSAC_VV_M8_MASK + 10U, // PseudoVFNMSAC_VV_MF2 + 10U, // PseudoVFNMSAC_VV_MF2_MASK + 10U, // PseudoVFNMSAC_VV_MF4 + 10U, // PseudoVFNMSAC_VV_MF4_MASK + 10U, // PseudoVFNMSAC_VV_MF8 + 10U, // PseudoVFNMSAC_VV_MF8_MASK + 10U, // PseudoVFNMSUB_VF16_M1 + 10U, // PseudoVFNMSUB_VF16_M1_MASK + 10U, // PseudoVFNMSUB_VF16_M2 + 10U, // PseudoVFNMSUB_VF16_M2_MASK + 10U, // PseudoVFNMSUB_VF16_M4 + 10U, // PseudoVFNMSUB_VF16_M4_MASK + 10U, // PseudoVFNMSUB_VF16_M8 + 10U, // PseudoVFNMSUB_VF16_M8_MASK + 10U, // PseudoVFNMSUB_VF16_MF2 + 10U, // PseudoVFNMSUB_VF16_MF2_MASK + 10U, // PseudoVFNMSUB_VF16_MF4 + 10U, // PseudoVFNMSUB_VF16_MF4_MASK + 10U, // PseudoVFNMSUB_VF16_MF8 + 10U, // PseudoVFNMSUB_VF16_MF8_MASK + 10U, // PseudoVFNMSUB_VF32_M1 + 10U, // PseudoVFNMSUB_VF32_M1_MASK + 10U, // PseudoVFNMSUB_VF32_M2 + 10U, // PseudoVFNMSUB_VF32_M2_MASK + 10U, // PseudoVFNMSUB_VF32_M4 + 10U, // PseudoVFNMSUB_VF32_M4_MASK + 10U, // PseudoVFNMSUB_VF32_M8 + 10U, // PseudoVFNMSUB_VF32_M8_MASK + 10U, // PseudoVFNMSUB_VF32_MF2 + 10U, // PseudoVFNMSUB_VF32_MF2_MASK + 10U, // PseudoVFNMSUB_VF32_MF4 + 10U, // PseudoVFNMSUB_VF32_MF4_MASK + 10U, // PseudoVFNMSUB_VF32_MF8 + 10U, // PseudoVFNMSUB_VF32_MF8_MASK + 10U, // PseudoVFNMSUB_VF64_M1 + 10U, // PseudoVFNMSUB_VF64_M1_MASK + 10U, // PseudoVFNMSUB_VF64_M2 + 10U, // PseudoVFNMSUB_VF64_M2_MASK + 10U, // PseudoVFNMSUB_VF64_M4 + 10U, // PseudoVFNMSUB_VF64_M4_MASK + 10U, // PseudoVFNMSUB_VF64_M8 + 10U, // PseudoVFNMSUB_VF64_M8_MASK + 10U, // PseudoVFNMSUB_VF64_MF2 + 10U, // PseudoVFNMSUB_VF64_MF2_MASK + 10U, // PseudoVFNMSUB_VF64_MF4 + 10U, // PseudoVFNMSUB_VF64_MF4_MASK + 10U, // PseudoVFNMSUB_VF64_MF8 + 10U, // PseudoVFNMSUB_VF64_MF8_MASK + 10U, // PseudoVFNMSUB_VV_M1 + 10U, // PseudoVFNMSUB_VV_M1_MASK + 10U, // PseudoVFNMSUB_VV_M2 + 10U, // PseudoVFNMSUB_VV_M2_MASK + 10U, // PseudoVFNMSUB_VV_M4 + 10U, // PseudoVFNMSUB_VV_M4_MASK + 10U, // PseudoVFNMSUB_VV_M8 + 10U, // PseudoVFNMSUB_VV_M8_MASK + 10U, // PseudoVFNMSUB_VV_MF2 + 10U, // PseudoVFNMSUB_VV_MF2_MASK + 10U, // PseudoVFNMSUB_VV_MF4 + 10U, // PseudoVFNMSUB_VV_MF4_MASK + 10U, // PseudoVFNMSUB_VV_MF8 + 10U, // PseudoVFNMSUB_VV_MF8_MASK + 10U, // PseudoVFRDIV_VF16_M1 + 10U, // PseudoVFRDIV_VF16_M1_MASK + 10U, // PseudoVFRDIV_VF16_M2 + 10U, // PseudoVFRDIV_VF16_M2_MASK + 10U, // PseudoVFRDIV_VF16_M4 + 10U, // PseudoVFRDIV_VF16_M4_MASK + 10U, // PseudoVFRDIV_VF16_M8 + 10U, // PseudoVFRDIV_VF16_M8_MASK + 10U, // PseudoVFRDIV_VF16_MF2 + 10U, // PseudoVFRDIV_VF16_MF2_MASK + 10U, // PseudoVFRDIV_VF16_MF4 + 10U, // PseudoVFRDIV_VF16_MF4_MASK + 10U, // PseudoVFRDIV_VF16_MF8 + 10U, // PseudoVFRDIV_VF16_MF8_MASK + 10U, // PseudoVFRDIV_VF32_M1 + 10U, // PseudoVFRDIV_VF32_M1_MASK + 10U, // PseudoVFRDIV_VF32_M2 + 10U, // PseudoVFRDIV_VF32_M2_MASK + 10U, // PseudoVFRDIV_VF32_M4 + 10U, // PseudoVFRDIV_VF32_M4_MASK + 10U, // PseudoVFRDIV_VF32_M8 + 10U, // PseudoVFRDIV_VF32_M8_MASK + 10U, // PseudoVFRDIV_VF32_MF2 + 10U, // PseudoVFRDIV_VF32_MF2_MASK + 10U, // PseudoVFRDIV_VF32_MF4 + 10U, // PseudoVFRDIV_VF32_MF4_MASK + 10U, // PseudoVFRDIV_VF32_MF8 + 10U, // PseudoVFRDIV_VF32_MF8_MASK + 10U, // PseudoVFRDIV_VF64_M1 + 10U, // PseudoVFRDIV_VF64_M1_MASK + 10U, // PseudoVFRDIV_VF64_M2 + 10U, // PseudoVFRDIV_VF64_M2_MASK + 10U, // PseudoVFRDIV_VF64_M4 + 10U, // PseudoVFRDIV_VF64_M4_MASK + 10U, // PseudoVFRDIV_VF64_M8 + 10U, // PseudoVFRDIV_VF64_M8_MASK + 10U, // PseudoVFRDIV_VF64_MF2 + 10U, // PseudoVFRDIV_VF64_MF2_MASK + 10U, // PseudoVFRDIV_VF64_MF4 + 10U, // PseudoVFRDIV_VF64_MF4_MASK + 10U, // PseudoVFRDIV_VF64_MF8 + 10U, // PseudoVFRDIV_VF64_MF8_MASK + 10U, // PseudoVFREC7_V_M1 + 10U, // PseudoVFREC7_V_M1_MASK + 10U, // PseudoVFREC7_V_M2 + 10U, // PseudoVFREC7_V_M2_MASK + 10U, // PseudoVFREC7_V_M4 + 10U, // PseudoVFREC7_V_M4_MASK + 10U, // PseudoVFREC7_V_M8 + 10U, // PseudoVFREC7_V_M8_MASK + 10U, // PseudoVFREC7_V_MF2 + 10U, // PseudoVFREC7_V_MF2_MASK + 10U, // PseudoVFREC7_V_MF4 + 10U, // PseudoVFREC7_V_MF4_MASK + 10U, // PseudoVFREC7_V_MF8 + 10U, // PseudoVFREC7_V_MF8_MASK + 10U, // PseudoVFREDMAX_VS_M1 + 10U, // PseudoVFREDMAX_VS_M1_MASK + 10U, // PseudoVFREDMAX_VS_M2 + 10U, // PseudoVFREDMAX_VS_M2_MASK + 10U, // PseudoVFREDMAX_VS_M4 + 10U, // PseudoVFREDMAX_VS_M4_MASK + 10U, // PseudoVFREDMAX_VS_M8 + 10U, // PseudoVFREDMAX_VS_M8_MASK + 10U, // PseudoVFREDMAX_VS_MF2 + 10U, // PseudoVFREDMAX_VS_MF2_MASK + 10U, // PseudoVFREDMAX_VS_MF4 + 10U, // PseudoVFREDMAX_VS_MF4_MASK + 10U, // PseudoVFREDMAX_VS_MF8 + 10U, // PseudoVFREDMAX_VS_MF8_MASK + 10U, // PseudoVFREDMIN_VS_M1 + 10U, // PseudoVFREDMIN_VS_M1_MASK + 10U, // PseudoVFREDMIN_VS_M2 + 10U, // PseudoVFREDMIN_VS_M2_MASK + 10U, // PseudoVFREDMIN_VS_M4 + 10U, // PseudoVFREDMIN_VS_M4_MASK + 10U, // PseudoVFREDMIN_VS_M8 + 10U, // PseudoVFREDMIN_VS_M8_MASK + 10U, // PseudoVFREDMIN_VS_MF2 + 10U, // PseudoVFREDMIN_VS_MF2_MASK + 10U, // PseudoVFREDMIN_VS_MF4 + 10U, // PseudoVFREDMIN_VS_MF4_MASK + 10U, // PseudoVFREDMIN_VS_MF8 + 10U, // PseudoVFREDMIN_VS_MF8_MASK + 10U, // PseudoVFREDOSUM_VS_M1 + 10U, // PseudoVFREDOSUM_VS_M1_MASK + 10U, // PseudoVFREDOSUM_VS_M2 + 10U, // PseudoVFREDOSUM_VS_M2_MASK + 10U, // PseudoVFREDOSUM_VS_M4 + 10U, // PseudoVFREDOSUM_VS_M4_MASK + 10U, // PseudoVFREDOSUM_VS_M8 + 10U, // PseudoVFREDOSUM_VS_M8_MASK + 10U, // PseudoVFREDOSUM_VS_MF2 + 10U, // PseudoVFREDOSUM_VS_MF2_MASK + 10U, // PseudoVFREDOSUM_VS_MF4 + 10U, // PseudoVFREDOSUM_VS_MF4_MASK + 10U, // PseudoVFREDOSUM_VS_MF8 + 10U, // PseudoVFREDOSUM_VS_MF8_MASK + 10U, // PseudoVFREDUSUM_VS_M1 + 10U, // PseudoVFREDUSUM_VS_M1_MASK + 10U, // PseudoVFREDUSUM_VS_M2 + 10U, // PseudoVFREDUSUM_VS_M2_MASK + 10U, // PseudoVFREDUSUM_VS_M4 + 10U, // PseudoVFREDUSUM_VS_M4_MASK + 10U, // PseudoVFREDUSUM_VS_M8 + 10U, // PseudoVFREDUSUM_VS_M8_MASK + 10U, // PseudoVFREDUSUM_VS_MF2 + 10U, // PseudoVFREDUSUM_VS_MF2_MASK + 10U, // PseudoVFREDUSUM_VS_MF4 + 10U, // PseudoVFREDUSUM_VS_MF4_MASK + 10U, // PseudoVFREDUSUM_VS_MF8 + 10U, // PseudoVFREDUSUM_VS_MF8_MASK + 10U, // PseudoVFRSQRT7_V_M1 + 10U, // PseudoVFRSQRT7_V_M1_MASK + 10U, // PseudoVFRSQRT7_V_M2 + 10U, // PseudoVFRSQRT7_V_M2_MASK + 10U, // PseudoVFRSQRT7_V_M4 + 10U, // PseudoVFRSQRT7_V_M4_MASK + 10U, // PseudoVFRSQRT7_V_M8 + 10U, // PseudoVFRSQRT7_V_M8_MASK + 10U, // PseudoVFRSQRT7_V_MF2 + 10U, // PseudoVFRSQRT7_V_MF2_MASK + 10U, // PseudoVFRSQRT7_V_MF4 + 10U, // PseudoVFRSQRT7_V_MF4_MASK + 10U, // PseudoVFRSQRT7_V_MF8 + 10U, // PseudoVFRSQRT7_V_MF8_MASK + 10U, // PseudoVFRSUB_VF16_M1 + 10U, // PseudoVFRSUB_VF16_M1_MASK + 10U, // PseudoVFRSUB_VF16_M2 + 10U, // PseudoVFRSUB_VF16_M2_MASK + 10U, // PseudoVFRSUB_VF16_M4 + 10U, // PseudoVFRSUB_VF16_M4_MASK + 10U, // PseudoVFRSUB_VF16_M8 + 10U, // PseudoVFRSUB_VF16_M8_MASK + 10U, // PseudoVFRSUB_VF16_MF2 + 10U, // PseudoVFRSUB_VF16_MF2_MASK + 10U, // PseudoVFRSUB_VF16_MF4 + 10U, // PseudoVFRSUB_VF16_MF4_MASK + 10U, // PseudoVFRSUB_VF16_MF8 + 10U, // PseudoVFRSUB_VF16_MF8_MASK + 10U, // PseudoVFRSUB_VF32_M1 + 10U, // PseudoVFRSUB_VF32_M1_MASK + 10U, // PseudoVFRSUB_VF32_M2 + 10U, // PseudoVFRSUB_VF32_M2_MASK + 10U, // PseudoVFRSUB_VF32_M4 + 10U, // PseudoVFRSUB_VF32_M4_MASK + 10U, // PseudoVFRSUB_VF32_M8 + 10U, // PseudoVFRSUB_VF32_M8_MASK + 10U, // PseudoVFRSUB_VF32_MF2 + 10U, // PseudoVFRSUB_VF32_MF2_MASK + 10U, // PseudoVFRSUB_VF32_MF4 + 10U, // PseudoVFRSUB_VF32_MF4_MASK + 10U, // PseudoVFRSUB_VF32_MF8 + 10U, // PseudoVFRSUB_VF32_MF8_MASK + 10U, // PseudoVFRSUB_VF64_M1 + 10U, // PseudoVFRSUB_VF64_M1_MASK + 10U, // PseudoVFRSUB_VF64_M2 + 10U, // PseudoVFRSUB_VF64_M2_MASK + 10U, // PseudoVFRSUB_VF64_M4 + 10U, // PseudoVFRSUB_VF64_M4_MASK + 10U, // PseudoVFRSUB_VF64_M8 + 10U, // PseudoVFRSUB_VF64_M8_MASK + 10U, // PseudoVFRSUB_VF64_MF2 + 10U, // PseudoVFRSUB_VF64_MF2_MASK + 10U, // PseudoVFRSUB_VF64_MF4 + 10U, // PseudoVFRSUB_VF64_MF4_MASK + 10U, // PseudoVFRSUB_VF64_MF8 + 10U, // PseudoVFRSUB_VF64_MF8_MASK + 10U, // PseudoVFSGNJN_VF16_M1 + 10U, // PseudoVFSGNJN_VF16_M1_MASK + 10U, // PseudoVFSGNJN_VF16_M2 + 10U, // PseudoVFSGNJN_VF16_M2_MASK + 10U, // PseudoVFSGNJN_VF16_M4 + 10U, // PseudoVFSGNJN_VF16_M4_MASK + 10U, // PseudoVFSGNJN_VF16_M8 + 10U, // PseudoVFSGNJN_VF16_M8_MASK + 10U, // PseudoVFSGNJN_VF16_MF2 + 10U, // PseudoVFSGNJN_VF16_MF2_MASK + 10U, // PseudoVFSGNJN_VF16_MF4 + 10U, // PseudoVFSGNJN_VF16_MF4_MASK + 10U, // PseudoVFSGNJN_VF16_MF8 + 10U, // PseudoVFSGNJN_VF16_MF8_MASK + 10U, // PseudoVFSGNJN_VF32_M1 + 10U, // PseudoVFSGNJN_VF32_M1_MASK + 10U, // PseudoVFSGNJN_VF32_M2 + 10U, // PseudoVFSGNJN_VF32_M2_MASK + 10U, // PseudoVFSGNJN_VF32_M4 + 10U, // PseudoVFSGNJN_VF32_M4_MASK + 10U, // PseudoVFSGNJN_VF32_M8 + 10U, // PseudoVFSGNJN_VF32_M8_MASK + 10U, // PseudoVFSGNJN_VF32_MF2 + 10U, // PseudoVFSGNJN_VF32_MF2_MASK + 10U, // PseudoVFSGNJN_VF32_MF4 + 10U, // PseudoVFSGNJN_VF32_MF4_MASK + 10U, // PseudoVFSGNJN_VF32_MF8 + 10U, // PseudoVFSGNJN_VF32_MF8_MASK + 10U, // PseudoVFSGNJN_VF64_M1 + 10U, // PseudoVFSGNJN_VF64_M1_MASK + 10U, // PseudoVFSGNJN_VF64_M2 + 10U, // PseudoVFSGNJN_VF64_M2_MASK + 10U, // PseudoVFSGNJN_VF64_M4 + 10U, // PseudoVFSGNJN_VF64_M4_MASK + 10U, // PseudoVFSGNJN_VF64_M8 + 10U, // PseudoVFSGNJN_VF64_M8_MASK + 10U, // PseudoVFSGNJN_VF64_MF2 + 10U, // PseudoVFSGNJN_VF64_MF2_MASK + 10U, // PseudoVFSGNJN_VF64_MF4 + 10U, // PseudoVFSGNJN_VF64_MF4_MASK + 10U, // PseudoVFSGNJN_VF64_MF8 + 10U, // PseudoVFSGNJN_VF64_MF8_MASK + 10U, // PseudoVFSGNJN_VV_M1 + 10U, // PseudoVFSGNJN_VV_M1_MASK + 10U, // PseudoVFSGNJN_VV_M2 + 10U, // PseudoVFSGNJN_VV_M2_MASK + 10U, // PseudoVFSGNJN_VV_M4 + 10U, // PseudoVFSGNJN_VV_M4_MASK + 10U, // PseudoVFSGNJN_VV_M8 + 10U, // PseudoVFSGNJN_VV_M8_MASK + 10U, // PseudoVFSGNJN_VV_MF2 + 10U, // PseudoVFSGNJN_VV_MF2_MASK + 10U, // PseudoVFSGNJN_VV_MF4 + 10U, // PseudoVFSGNJN_VV_MF4_MASK + 10U, // PseudoVFSGNJN_VV_MF8 + 10U, // PseudoVFSGNJN_VV_MF8_MASK + 10U, // PseudoVFSGNJX_VF16_M1 + 10U, // PseudoVFSGNJX_VF16_M1_MASK + 10U, // PseudoVFSGNJX_VF16_M2 + 10U, // PseudoVFSGNJX_VF16_M2_MASK + 10U, // PseudoVFSGNJX_VF16_M4 + 10U, // PseudoVFSGNJX_VF16_M4_MASK + 10U, // PseudoVFSGNJX_VF16_M8 + 10U, // PseudoVFSGNJX_VF16_M8_MASK + 10U, // PseudoVFSGNJX_VF16_MF2 + 10U, // PseudoVFSGNJX_VF16_MF2_MASK + 10U, // PseudoVFSGNJX_VF16_MF4 + 10U, // PseudoVFSGNJX_VF16_MF4_MASK + 10U, // PseudoVFSGNJX_VF16_MF8 + 10U, // PseudoVFSGNJX_VF16_MF8_MASK + 10U, // PseudoVFSGNJX_VF32_M1 + 10U, // PseudoVFSGNJX_VF32_M1_MASK + 10U, // PseudoVFSGNJX_VF32_M2 + 10U, // PseudoVFSGNJX_VF32_M2_MASK + 10U, // PseudoVFSGNJX_VF32_M4 + 10U, // PseudoVFSGNJX_VF32_M4_MASK + 10U, // PseudoVFSGNJX_VF32_M8 + 10U, // PseudoVFSGNJX_VF32_M8_MASK + 10U, // PseudoVFSGNJX_VF32_MF2 + 10U, // PseudoVFSGNJX_VF32_MF2_MASK + 10U, // PseudoVFSGNJX_VF32_MF4 + 10U, // PseudoVFSGNJX_VF32_MF4_MASK + 10U, // PseudoVFSGNJX_VF32_MF8 + 10U, // PseudoVFSGNJX_VF32_MF8_MASK + 10U, // PseudoVFSGNJX_VF64_M1 + 10U, // PseudoVFSGNJX_VF64_M1_MASK + 10U, // PseudoVFSGNJX_VF64_M2 + 10U, // PseudoVFSGNJX_VF64_M2_MASK + 10U, // PseudoVFSGNJX_VF64_M4 + 10U, // PseudoVFSGNJX_VF64_M4_MASK + 10U, // PseudoVFSGNJX_VF64_M8 + 10U, // PseudoVFSGNJX_VF64_M8_MASK + 10U, // PseudoVFSGNJX_VF64_MF2 + 10U, // PseudoVFSGNJX_VF64_MF2_MASK + 10U, // PseudoVFSGNJX_VF64_MF4 + 10U, // PseudoVFSGNJX_VF64_MF4_MASK + 10U, // PseudoVFSGNJX_VF64_MF8 + 10U, // PseudoVFSGNJX_VF64_MF8_MASK + 10U, // PseudoVFSGNJX_VV_M1 + 10U, // PseudoVFSGNJX_VV_M1_MASK + 10U, // PseudoVFSGNJX_VV_M2 + 10U, // PseudoVFSGNJX_VV_M2_MASK + 10U, // PseudoVFSGNJX_VV_M4 + 10U, // PseudoVFSGNJX_VV_M4_MASK + 10U, // PseudoVFSGNJX_VV_M8 + 10U, // PseudoVFSGNJX_VV_M8_MASK + 10U, // PseudoVFSGNJX_VV_MF2 + 10U, // PseudoVFSGNJX_VV_MF2_MASK + 10U, // PseudoVFSGNJX_VV_MF4 + 10U, // PseudoVFSGNJX_VV_MF4_MASK + 10U, // PseudoVFSGNJX_VV_MF8 + 10U, // PseudoVFSGNJX_VV_MF8_MASK + 10U, // PseudoVFSGNJ_VF16_M1 + 10U, // PseudoVFSGNJ_VF16_M1_MASK + 10U, // PseudoVFSGNJ_VF16_M2 + 10U, // PseudoVFSGNJ_VF16_M2_MASK + 10U, // PseudoVFSGNJ_VF16_M4 + 10U, // PseudoVFSGNJ_VF16_M4_MASK + 10U, // PseudoVFSGNJ_VF16_M8 + 10U, // PseudoVFSGNJ_VF16_M8_MASK + 10U, // PseudoVFSGNJ_VF16_MF2 + 10U, // PseudoVFSGNJ_VF16_MF2_MASK + 10U, // PseudoVFSGNJ_VF16_MF4 + 10U, // PseudoVFSGNJ_VF16_MF4_MASK + 10U, // PseudoVFSGNJ_VF16_MF8 + 10U, // PseudoVFSGNJ_VF16_MF8_MASK + 10U, // PseudoVFSGNJ_VF32_M1 + 10U, // PseudoVFSGNJ_VF32_M1_MASK + 10U, // PseudoVFSGNJ_VF32_M2 + 10U, // PseudoVFSGNJ_VF32_M2_MASK + 10U, // PseudoVFSGNJ_VF32_M4 + 10U, // PseudoVFSGNJ_VF32_M4_MASK + 10U, // PseudoVFSGNJ_VF32_M8 + 10U, // PseudoVFSGNJ_VF32_M8_MASK + 10U, // PseudoVFSGNJ_VF32_MF2 + 10U, // PseudoVFSGNJ_VF32_MF2_MASK + 10U, // PseudoVFSGNJ_VF32_MF4 + 10U, // PseudoVFSGNJ_VF32_MF4_MASK + 10U, // PseudoVFSGNJ_VF32_MF8 + 10U, // PseudoVFSGNJ_VF32_MF8_MASK + 10U, // PseudoVFSGNJ_VF64_M1 + 10U, // PseudoVFSGNJ_VF64_M1_MASK + 10U, // PseudoVFSGNJ_VF64_M2 + 10U, // PseudoVFSGNJ_VF64_M2_MASK + 10U, // PseudoVFSGNJ_VF64_M4 + 10U, // PseudoVFSGNJ_VF64_M4_MASK + 10U, // PseudoVFSGNJ_VF64_M8 + 10U, // PseudoVFSGNJ_VF64_M8_MASK + 10U, // PseudoVFSGNJ_VF64_MF2 + 10U, // PseudoVFSGNJ_VF64_MF2_MASK + 10U, // PseudoVFSGNJ_VF64_MF4 + 10U, // PseudoVFSGNJ_VF64_MF4_MASK + 10U, // PseudoVFSGNJ_VF64_MF8 + 10U, // PseudoVFSGNJ_VF64_MF8_MASK + 10U, // PseudoVFSGNJ_VV_M1 + 10U, // PseudoVFSGNJ_VV_M1_MASK + 10U, // PseudoVFSGNJ_VV_M2 + 10U, // PseudoVFSGNJ_VV_M2_MASK + 10U, // PseudoVFSGNJ_VV_M4 + 10U, // PseudoVFSGNJ_VV_M4_MASK + 10U, // PseudoVFSGNJ_VV_M8 + 10U, // PseudoVFSGNJ_VV_M8_MASK + 10U, // PseudoVFSGNJ_VV_MF2 + 10U, // PseudoVFSGNJ_VV_MF2_MASK + 10U, // PseudoVFSGNJ_VV_MF4 + 10U, // PseudoVFSGNJ_VV_MF4_MASK + 10U, // PseudoVFSGNJ_VV_MF8 + 10U, // PseudoVFSGNJ_VV_MF8_MASK + 10U, // PseudoVFSLIDE1DOWN_VF16_M1 + 10U, // PseudoVFSLIDE1DOWN_VF16_M1_MASK + 10U, // PseudoVFSLIDE1DOWN_VF16_M2 + 10U, // PseudoVFSLIDE1DOWN_VF16_M2_MASK + 10U, // PseudoVFSLIDE1DOWN_VF16_M4 + 10U, // PseudoVFSLIDE1DOWN_VF16_M4_MASK + 10U, // PseudoVFSLIDE1DOWN_VF16_M8 + 10U, // PseudoVFSLIDE1DOWN_VF16_M8_MASK + 10U, // PseudoVFSLIDE1DOWN_VF16_MF2 + 10U, // PseudoVFSLIDE1DOWN_VF16_MF2_MASK + 10U, // PseudoVFSLIDE1DOWN_VF16_MF4 + 10U, // PseudoVFSLIDE1DOWN_VF16_MF4_MASK + 10U, // PseudoVFSLIDE1DOWN_VF16_MF8 + 10U, // PseudoVFSLIDE1DOWN_VF16_MF8_MASK + 10U, // PseudoVFSLIDE1DOWN_VF32_M1 + 10U, // PseudoVFSLIDE1DOWN_VF32_M1_MASK + 10U, // PseudoVFSLIDE1DOWN_VF32_M2 + 10U, // PseudoVFSLIDE1DOWN_VF32_M2_MASK + 10U, // PseudoVFSLIDE1DOWN_VF32_M4 + 10U, // PseudoVFSLIDE1DOWN_VF32_M4_MASK + 10U, // PseudoVFSLIDE1DOWN_VF32_M8 + 10U, // PseudoVFSLIDE1DOWN_VF32_M8_MASK + 10U, // PseudoVFSLIDE1DOWN_VF32_MF2 + 10U, // PseudoVFSLIDE1DOWN_VF32_MF2_MASK + 10U, // PseudoVFSLIDE1DOWN_VF32_MF4 + 10U, // PseudoVFSLIDE1DOWN_VF32_MF4_MASK + 10U, // PseudoVFSLIDE1DOWN_VF32_MF8 + 10U, // PseudoVFSLIDE1DOWN_VF32_MF8_MASK + 10U, // PseudoVFSLIDE1DOWN_VF64_M1 + 10U, // PseudoVFSLIDE1DOWN_VF64_M1_MASK + 10U, // PseudoVFSLIDE1DOWN_VF64_M2 + 10U, // PseudoVFSLIDE1DOWN_VF64_M2_MASK + 10U, // PseudoVFSLIDE1DOWN_VF64_M4 + 10U, // PseudoVFSLIDE1DOWN_VF64_M4_MASK + 10U, // PseudoVFSLIDE1DOWN_VF64_M8 + 10U, // PseudoVFSLIDE1DOWN_VF64_M8_MASK + 10U, // PseudoVFSLIDE1DOWN_VF64_MF2 + 10U, // PseudoVFSLIDE1DOWN_VF64_MF2_MASK + 10U, // PseudoVFSLIDE1DOWN_VF64_MF4 + 10U, // PseudoVFSLIDE1DOWN_VF64_MF4_MASK + 10U, // PseudoVFSLIDE1DOWN_VF64_MF8 + 10U, // PseudoVFSLIDE1DOWN_VF64_MF8_MASK + 10U, // PseudoVFSLIDE1UP_VF16_M1 + 10U, // PseudoVFSLIDE1UP_VF16_M1_MASK + 10U, // PseudoVFSLIDE1UP_VF16_M2 + 10U, // PseudoVFSLIDE1UP_VF16_M2_MASK + 10U, // PseudoVFSLIDE1UP_VF16_M4 + 10U, // PseudoVFSLIDE1UP_VF16_M4_MASK + 10U, // PseudoVFSLIDE1UP_VF16_M8 + 10U, // PseudoVFSLIDE1UP_VF16_M8_MASK + 10U, // PseudoVFSLIDE1UP_VF16_MF2 + 10U, // PseudoVFSLIDE1UP_VF16_MF2_MASK + 10U, // PseudoVFSLIDE1UP_VF16_MF4 + 10U, // PseudoVFSLIDE1UP_VF16_MF4_MASK + 10U, // PseudoVFSLIDE1UP_VF16_MF8 + 10U, // PseudoVFSLIDE1UP_VF16_MF8_MASK + 10U, // PseudoVFSLIDE1UP_VF32_M1 + 10U, // PseudoVFSLIDE1UP_VF32_M1_MASK + 10U, // PseudoVFSLIDE1UP_VF32_M2 + 10U, // PseudoVFSLIDE1UP_VF32_M2_MASK + 10U, // PseudoVFSLIDE1UP_VF32_M4 + 10U, // PseudoVFSLIDE1UP_VF32_M4_MASK + 10U, // PseudoVFSLIDE1UP_VF32_M8 + 10U, // PseudoVFSLIDE1UP_VF32_M8_MASK + 10U, // PseudoVFSLIDE1UP_VF32_MF2 + 10U, // PseudoVFSLIDE1UP_VF32_MF2_MASK + 10U, // PseudoVFSLIDE1UP_VF32_MF4 + 10U, // PseudoVFSLIDE1UP_VF32_MF4_MASK + 10U, // PseudoVFSLIDE1UP_VF32_MF8 + 10U, // PseudoVFSLIDE1UP_VF32_MF8_MASK + 10U, // PseudoVFSLIDE1UP_VF64_M1 + 10U, // PseudoVFSLIDE1UP_VF64_M1_MASK + 10U, // PseudoVFSLIDE1UP_VF64_M2 + 10U, // PseudoVFSLIDE1UP_VF64_M2_MASK + 10U, // PseudoVFSLIDE1UP_VF64_M4 + 10U, // PseudoVFSLIDE1UP_VF64_M4_MASK + 10U, // PseudoVFSLIDE1UP_VF64_M8 + 10U, // PseudoVFSLIDE1UP_VF64_M8_MASK + 10U, // PseudoVFSLIDE1UP_VF64_MF2 + 10U, // PseudoVFSLIDE1UP_VF64_MF2_MASK + 10U, // PseudoVFSLIDE1UP_VF64_MF4 + 10U, // PseudoVFSLIDE1UP_VF64_MF4_MASK + 10U, // PseudoVFSLIDE1UP_VF64_MF8 + 10U, // PseudoVFSLIDE1UP_VF64_MF8_MASK + 10U, // PseudoVFSQRT_V_M1 + 10U, // PseudoVFSQRT_V_M1_MASK + 10U, // PseudoVFSQRT_V_M2 + 10U, // PseudoVFSQRT_V_M2_MASK + 10U, // PseudoVFSQRT_V_M4 + 10U, // PseudoVFSQRT_V_M4_MASK + 10U, // PseudoVFSQRT_V_M8 + 10U, // PseudoVFSQRT_V_M8_MASK + 10U, // PseudoVFSQRT_V_MF2 + 10U, // PseudoVFSQRT_V_MF2_MASK + 10U, // PseudoVFSQRT_V_MF4 + 10U, // PseudoVFSQRT_V_MF4_MASK + 10U, // PseudoVFSQRT_V_MF8 + 10U, // PseudoVFSQRT_V_MF8_MASK + 10U, // PseudoVFSUB_VF16_M1 + 10U, // PseudoVFSUB_VF16_M1_MASK + 10U, // PseudoVFSUB_VF16_M2 + 10U, // PseudoVFSUB_VF16_M2_MASK + 10U, // PseudoVFSUB_VF16_M4 + 10U, // PseudoVFSUB_VF16_M4_MASK + 10U, // PseudoVFSUB_VF16_M8 + 10U, // PseudoVFSUB_VF16_M8_MASK + 10U, // PseudoVFSUB_VF16_MF2 + 10U, // PseudoVFSUB_VF16_MF2_MASK + 10U, // PseudoVFSUB_VF16_MF4 + 10U, // PseudoVFSUB_VF16_MF4_MASK + 10U, // PseudoVFSUB_VF16_MF8 + 10U, // PseudoVFSUB_VF16_MF8_MASK + 10U, // PseudoVFSUB_VF32_M1 + 10U, // PseudoVFSUB_VF32_M1_MASK + 10U, // PseudoVFSUB_VF32_M2 + 10U, // PseudoVFSUB_VF32_M2_MASK + 10U, // PseudoVFSUB_VF32_M4 + 10U, // PseudoVFSUB_VF32_M4_MASK + 10U, // PseudoVFSUB_VF32_M8 + 10U, // PseudoVFSUB_VF32_M8_MASK + 10U, // PseudoVFSUB_VF32_MF2 + 10U, // PseudoVFSUB_VF32_MF2_MASK + 10U, // PseudoVFSUB_VF32_MF4 + 10U, // PseudoVFSUB_VF32_MF4_MASK + 10U, // PseudoVFSUB_VF32_MF8 + 10U, // PseudoVFSUB_VF32_MF8_MASK + 10U, // PseudoVFSUB_VF64_M1 + 10U, // PseudoVFSUB_VF64_M1_MASK + 10U, // PseudoVFSUB_VF64_M2 + 10U, // PseudoVFSUB_VF64_M2_MASK + 10U, // PseudoVFSUB_VF64_M4 + 10U, // PseudoVFSUB_VF64_M4_MASK + 10U, // PseudoVFSUB_VF64_M8 + 10U, // PseudoVFSUB_VF64_M8_MASK + 10U, // PseudoVFSUB_VF64_MF2 + 10U, // PseudoVFSUB_VF64_MF2_MASK + 10U, // PseudoVFSUB_VF64_MF4 + 10U, // PseudoVFSUB_VF64_MF4_MASK + 10U, // PseudoVFSUB_VF64_MF8 + 10U, // PseudoVFSUB_VF64_MF8_MASK + 10U, // PseudoVFSUB_VV_M1 + 10U, // PseudoVFSUB_VV_M1_MASK + 10U, // PseudoVFSUB_VV_M2 + 10U, // PseudoVFSUB_VV_M2_MASK + 10U, // PseudoVFSUB_VV_M4 + 10U, // PseudoVFSUB_VV_M4_MASK + 10U, // PseudoVFSUB_VV_M8 + 10U, // PseudoVFSUB_VV_M8_MASK + 10U, // PseudoVFSUB_VV_MF2 + 10U, // PseudoVFSUB_VV_MF2_MASK + 10U, // PseudoVFSUB_VV_MF4 + 10U, // PseudoVFSUB_VV_MF4_MASK + 10U, // PseudoVFSUB_VV_MF8 + 10U, // PseudoVFSUB_VV_MF8_MASK + 10U, // PseudoVFWADD_VF16_M1 + 10U, // PseudoVFWADD_VF16_M1_MASK + 10U, // PseudoVFWADD_VF16_M2 + 10U, // PseudoVFWADD_VF16_M2_MASK + 10U, // PseudoVFWADD_VF16_M4 + 10U, // PseudoVFWADD_VF16_M4_MASK + 10U, // PseudoVFWADD_VF16_MF2 + 10U, // PseudoVFWADD_VF16_MF2_MASK + 10U, // PseudoVFWADD_VF16_MF4 + 10U, // PseudoVFWADD_VF16_MF4_MASK + 10U, // PseudoVFWADD_VF16_MF8 + 10U, // PseudoVFWADD_VF16_MF8_MASK + 10U, // PseudoVFWADD_VF32_M1 + 10U, // PseudoVFWADD_VF32_M1_MASK + 10U, // PseudoVFWADD_VF32_M2 + 10U, // PseudoVFWADD_VF32_M2_MASK + 10U, // PseudoVFWADD_VF32_M4 + 10U, // PseudoVFWADD_VF32_M4_MASK + 10U, // PseudoVFWADD_VF32_MF2 + 10U, // PseudoVFWADD_VF32_MF2_MASK + 10U, // PseudoVFWADD_VF32_MF4 + 10U, // PseudoVFWADD_VF32_MF4_MASK + 10U, // PseudoVFWADD_VF32_MF8 + 10U, // PseudoVFWADD_VF32_MF8_MASK + 10U, // PseudoVFWADD_VV_M1 + 10U, // PseudoVFWADD_VV_M1_MASK + 10U, // PseudoVFWADD_VV_M2 + 10U, // PseudoVFWADD_VV_M2_MASK + 10U, // PseudoVFWADD_VV_M4 + 10U, // PseudoVFWADD_VV_M4_MASK + 10U, // PseudoVFWADD_VV_MF2 + 10U, // PseudoVFWADD_VV_MF2_MASK + 10U, // PseudoVFWADD_VV_MF4 + 10U, // PseudoVFWADD_VV_MF4_MASK + 10U, // PseudoVFWADD_VV_MF8 + 10U, // PseudoVFWADD_VV_MF8_MASK + 10U, // PseudoVFWADD_WF16_M1 + 10U, // PseudoVFWADD_WF16_M1_MASK + 10U, // PseudoVFWADD_WF16_M2 + 10U, // PseudoVFWADD_WF16_M2_MASK + 10U, // PseudoVFWADD_WF16_M4 + 10U, // PseudoVFWADD_WF16_M4_MASK + 10U, // PseudoVFWADD_WF16_MF2 + 10U, // PseudoVFWADD_WF16_MF2_MASK + 10U, // PseudoVFWADD_WF16_MF4 + 10U, // PseudoVFWADD_WF16_MF4_MASK + 10U, // PseudoVFWADD_WF16_MF8 + 10U, // PseudoVFWADD_WF16_MF8_MASK + 10U, // PseudoVFWADD_WF32_M1 + 10U, // PseudoVFWADD_WF32_M1_MASK + 10U, // PseudoVFWADD_WF32_M2 + 10U, // PseudoVFWADD_WF32_M2_MASK + 10U, // PseudoVFWADD_WF32_M4 + 10U, // PseudoVFWADD_WF32_M4_MASK + 10U, // PseudoVFWADD_WF32_MF2 + 10U, // PseudoVFWADD_WF32_MF2_MASK + 10U, // PseudoVFWADD_WF32_MF4 + 10U, // PseudoVFWADD_WF32_MF4_MASK + 10U, // PseudoVFWADD_WF32_MF8 + 10U, // PseudoVFWADD_WF32_MF8_MASK + 10U, // PseudoVFWADD_WV_M1 + 10U, // PseudoVFWADD_WV_M1_MASK + 10U, // PseudoVFWADD_WV_M1_MASK_TIED + 10U, // PseudoVFWADD_WV_M1_TIED + 10U, // PseudoVFWADD_WV_M2 + 10U, // PseudoVFWADD_WV_M2_MASK + 10U, // PseudoVFWADD_WV_M2_MASK_TIED + 10U, // PseudoVFWADD_WV_M2_TIED + 10U, // PseudoVFWADD_WV_M4 + 10U, // PseudoVFWADD_WV_M4_MASK + 10U, // PseudoVFWADD_WV_M4_MASK_TIED + 10U, // PseudoVFWADD_WV_M4_TIED + 10U, // PseudoVFWADD_WV_MF2 + 10U, // PseudoVFWADD_WV_MF2_MASK + 10U, // PseudoVFWADD_WV_MF2_MASK_TIED + 10U, // PseudoVFWADD_WV_MF2_TIED + 10U, // PseudoVFWADD_WV_MF4 + 10U, // PseudoVFWADD_WV_MF4_MASK + 10U, // PseudoVFWADD_WV_MF4_MASK_TIED + 10U, // PseudoVFWADD_WV_MF4_TIED + 10U, // PseudoVFWADD_WV_MF8 + 10U, // PseudoVFWADD_WV_MF8_MASK + 10U, // PseudoVFWADD_WV_MF8_MASK_TIED + 10U, // PseudoVFWADD_WV_MF8_TIED + 10U, // PseudoVFWCVT_F_F_V_M1 + 10U, // PseudoVFWCVT_F_F_V_M1_MASK + 10U, // PseudoVFWCVT_F_F_V_M2 + 10U, // PseudoVFWCVT_F_F_V_M2_MASK + 10U, // PseudoVFWCVT_F_F_V_M4 + 10U, // PseudoVFWCVT_F_F_V_M4_MASK + 10U, // PseudoVFWCVT_F_F_V_MF2 + 10U, // PseudoVFWCVT_F_F_V_MF2_MASK + 10U, // PseudoVFWCVT_F_F_V_MF4 + 10U, // PseudoVFWCVT_F_F_V_MF4_MASK + 10U, // PseudoVFWCVT_F_F_V_MF8 + 10U, // PseudoVFWCVT_F_F_V_MF8_MASK + 10U, // PseudoVFWCVT_F_XU_V_M1 + 10U, // PseudoVFWCVT_F_XU_V_M1_MASK + 10U, // PseudoVFWCVT_F_XU_V_M2 + 10U, // PseudoVFWCVT_F_XU_V_M2_MASK + 10U, // PseudoVFWCVT_F_XU_V_M4 + 10U, // PseudoVFWCVT_F_XU_V_M4_MASK + 10U, // PseudoVFWCVT_F_XU_V_MF2 + 10U, // PseudoVFWCVT_F_XU_V_MF2_MASK + 10U, // PseudoVFWCVT_F_XU_V_MF4 + 10U, // PseudoVFWCVT_F_XU_V_MF4_MASK + 10U, // PseudoVFWCVT_F_XU_V_MF8 + 10U, // PseudoVFWCVT_F_XU_V_MF8_MASK + 10U, // PseudoVFWCVT_F_X_V_M1 + 10U, // PseudoVFWCVT_F_X_V_M1_MASK + 10U, // PseudoVFWCVT_F_X_V_M2 + 10U, // PseudoVFWCVT_F_X_V_M2_MASK + 10U, // PseudoVFWCVT_F_X_V_M4 + 10U, // PseudoVFWCVT_F_X_V_M4_MASK + 10U, // PseudoVFWCVT_F_X_V_MF2 + 10U, // PseudoVFWCVT_F_X_V_MF2_MASK + 10U, // PseudoVFWCVT_F_X_V_MF4 + 10U, // PseudoVFWCVT_F_X_V_MF4_MASK + 10U, // PseudoVFWCVT_F_X_V_MF8 + 10U, // PseudoVFWCVT_F_X_V_MF8_MASK + 10U, // PseudoVFWCVT_RTZ_XU_F_V_M1 + 10U, // PseudoVFWCVT_RTZ_XU_F_V_M1_MASK + 10U, // PseudoVFWCVT_RTZ_XU_F_V_M2 + 10U, // PseudoVFWCVT_RTZ_XU_F_V_M2_MASK + 10U, // PseudoVFWCVT_RTZ_XU_F_V_M4 + 10U, // PseudoVFWCVT_RTZ_XU_F_V_M4_MASK + 10U, // PseudoVFWCVT_RTZ_XU_F_V_MF2 + 10U, // PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK + 10U, // PseudoVFWCVT_RTZ_XU_F_V_MF4 + 10U, // PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK + 10U, // PseudoVFWCVT_RTZ_XU_F_V_MF8 + 10U, // PseudoVFWCVT_RTZ_XU_F_V_MF8_MASK + 10U, // PseudoVFWCVT_RTZ_X_F_V_M1 + 10U, // PseudoVFWCVT_RTZ_X_F_V_M1_MASK + 10U, // PseudoVFWCVT_RTZ_X_F_V_M2 + 10U, // PseudoVFWCVT_RTZ_X_F_V_M2_MASK + 10U, // PseudoVFWCVT_RTZ_X_F_V_M4 + 10U, // PseudoVFWCVT_RTZ_X_F_V_M4_MASK + 10U, // PseudoVFWCVT_RTZ_X_F_V_MF2 + 10U, // PseudoVFWCVT_RTZ_X_F_V_MF2_MASK + 10U, // PseudoVFWCVT_RTZ_X_F_V_MF4 + 10U, // PseudoVFWCVT_RTZ_X_F_V_MF4_MASK + 10U, // PseudoVFWCVT_RTZ_X_F_V_MF8 + 10U, // PseudoVFWCVT_RTZ_X_F_V_MF8_MASK + 10U, // PseudoVFWCVT_XU_F_V_M1 + 10U, // PseudoVFWCVT_XU_F_V_M1_MASK + 10U, // PseudoVFWCVT_XU_F_V_M2 + 10U, // PseudoVFWCVT_XU_F_V_M2_MASK + 10U, // PseudoVFWCVT_XU_F_V_M4 + 10U, // PseudoVFWCVT_XU_F_V_M4_MASK + 10U, // PseudoVFWCVT_XU_F_V_MF2 + 10U, // PseudoVFWCVT_XU_F_V_MF2_MASK + 10U, // PseudoVFWCVT_XU_F_V_MF4 + 10U, // PseudoVFWCVT_XU_F_V_MF4_MASK + 10U, // PseudoVFWCVT_XU_F_V_MF8 + 10U, // PseudoVFWCVT_XU_F_V_MF8_MASK + 10U, // PseudoVFWCVT_X_F_V_M1 + 10U, // PseudoVFWCVT_X_F_V_M1_MASK + 10U, // PseudoVFWCVT_X_F_V_M2 + 10U, // PseudoVFWCVT_X_F_V_M2_MASK + 10U, // PseudoVFWCVT_X_F_V_M4 + 10U, // PseudoVFWCVT_X_F_V_M4_MASK + 10U, // PseudoVFWCVT_X_F_V_MF2 + 10U, // PseudoVFWCVT_X_F_V_MF2_MASK + 10U, // PseudoVFWCVT_X_F_V_MF4 + 10U, // PseudoVFWCVT_X_F_V_MF4_MASK + 10U, // PseudoVFWCVT_X_F_V_MF8 + 10U, // PseudoVFWCVT_X_F_V_MF8_MASK + 10U, // PseudoVFWMACC_VF16_M1 + 10U, // PseudoVFWMACC_VF16_M1_MASK + 10U, // PseudoVFWMACC_VF16_M2 + 10U, // PseudoVFWMACC_VF16_M2_MASK + 10U, // PseudoVFWMACC_VF16_M4 + 10U, // PseudoVFWMACC_VF16_M4_MASK + 10U, // PseudoVFWMACC_VF16_MF2 + 10U, // PseudoVFWMACC_VF16_MF2_MASK + 10U, // PseudoVFWMACC_VF16_MF4 + 10U, // PseudoVFWMACC_VF16_MF4_MASK + 10U, // PseudoVFWMACC_VF16_MF8 + 10U, // PseudoVFWMACC_VF16_MF8_MASK + 10U, // PseudoVFWMACC_VF32_M1 + 10U, // PseudoVFWMACC_VF32_M1_MASK + 10U, // PseudoVFWMACC_VF32_M2 + 10U, // PseudoVFWMACC_VF32_M2_MASK + 10U, // PseudoVFWMACC_VF32_M4 + 10U, // PseudoVFWMACC_VF32_M4_MASK + 10U, // PseudoVFWMACC_VF32_MF2 + 10U, // PseudoVFWMACC_VF32_MF2_MASK + 10U, // PseudoVFWMACC_VF32_MF4 + 10U, // PseudoVFWMACC_VF32_MF4_MASK + 10U, // PseudoVFWMACC_VF32_MF8 + 10U, // PseudoVFWMACC_VF32_MF8_MASK + 10U, // PseudoVFWMACC_VV_M1 + 10U, // PseudoVFWMACC_VV_M1_MASK + 10U, // PseudoVFWMACC_VV_M2 + 10U, // PseudoVFWMACC_VV_M2_MASK + 10U, // PseudoVFWMACC_VV_M4 + 10U, // PseudoVFWMACC_VV_M4_MASK + 10U, // PseudoVFWMACC_VV_MF2 + 10U, // PseudoVFWMACC_VV_MF2_MASK + 10U, // PseudoVFWMACC_VV_MF4 + 10U, // PseudoVFWMACC_VV_MF4_MASK + 10U, // PseudoVFWMACC_VV_MF8 + 10U, // PseudoVFWMACC_VV_MF8_MASK + 10U, // PseudoVFWMSAC_VF16_M1 + 10U, // PseudoVFWMSAC_VF16_M1_MASK + 10U, // PseudoVFWMSAC_VF16_M2 + 10U, // PseudoVFWMSAC_VF16_M2_MASK + 10U, // PseudoVFWMSAC_VF16_M4 + 10U, // PseudoVFWMSAC_VF16_M4_MASK + 10U, // PseudoVFWMSAC_VF16_MF2 + 10U, // PseudoVFWMSAC_VF16_MF2_MASK + 10U, // PseudoVFWMSAC_VF16_MF4 + 10U, // PseudoVFWMSAC_VF16_MF4_MASK + 10U, // PseudoVFWMSAC_VF16_MF8 + 10U, // PseudoVFWMSAC_VF16_MF8_MASK + 10U, // PseudoVFWMSAC_VF32_M1 + 10U, // PseudoVFWMSAC_VF32_M1_MASK + 10U, // PseudoVFWMSAC_VF32_M2 + 10U, // PseudoVFWMSAC_VF32_M2_MASK + 10U, // PseudoVFWMSAC_VF32_M4 + 10U, // PseudoVFWMSAC_VF32_M4_MASK + 10U, // PseudoVFWMSAC_VF32_MF2 + 10U, // PseudoVFWMSAC_VF32_MF2_MASK + 10U, // PseudoVFWMSAC_VF32_MF4 + 10U, // PseudoVFWMSAC_VF32_MF4_MASK + 10U, // PseudoVFWMSAC_VF32_MF8 + 10U, // PseudoVFWMSAC_VF32_MF8_MASK + 10U, // PseudoVFWMSAC_VV_M1 + 10U, // PseudoVFWMSAC_VV_M1_MASK + 10U, // PseudoVFWMSAC_VV_M2 + 10U, // PseudoVFWMSAC_VV_M2_MASK + 10U, // PseudoVFWMSAC_VV_M4 + 10U, // PseudoVFWMSAC_VV_M4_MASK + 10U, // PseudoVFWMSAC_VV_MF2 + 10U, // PseudoVFWMSAC_VV_MF2_MASK + 10U, // PseudoVFWMSAC_VV_MF4 + 10U, // PseudoVFWMSAC_VV_MF4_MASK + 10U, // PseudoVFWMSAC_VV_MF8 + 10U, // PseudoVFWMSAC_VV_MF8_MASK + 10U, // PseudoVFWMUL_VF16_M1 + 10U, // PseudoVFWMUL_VF16_M1_MASK + 10U, // PseudoVFWMUL_VF16_M2 + 10U, // PseudoVFWMUL_VF16_M2_MASK + 10U, // PseudoVFWMUL_VF16_M4 + 10U, // PseudoVFWMUL_VF16_M4_MASK + 10U, // PseudoVFWMUL_VF16_MF2 + 10U, // PseudoVFWMUL_VF16_MF2_MASK + 10U, // PseudoVFWMUL_VF16_MF4 + 10U, // PseudoVFWMUL_VF16_MF4_MASK + 10U, // PseudoVFWMUL_VF16_MF8 + 10U, // PseudoVFWMUL_VF16_MF8_MASK + 10U, // PseudoVFWMUL_VF32_M1 + 10U, // PseudoVFWMUL_VF32_M1_MASK + 10U, // PseudoVFWMUL_VF32_M2 + 10U, // PseudoVFWMUL_VF32_M2_MASK + 10U, // PseudoVFWMUL_VF32_M4 + 10U, // PseudoVFWMUL_VF32_M4_MASK + 10U, // PseudoVFWMUL_VF32_MF2 + 10U, // PseudoVFWMUL_VF32_MF2_MASK + 10U, // PseudoVFWMUL_VF32_MF4 + 10U, // PseudoVFWMUL_VF32_MF4_MASK + 10U, // PseudoVFWMUL_VF32_MF8 + 10U, // PseudoVFWMUL_VF32_MF8_MASK + 10U, // PseudoVFWMUL_VV_M1 + 10U, // PseudoVFWMUL_VV_M1_MASK + 10U, // PseudoVFWMUL_VV_M2 + 10U, // PseudoVFWMUL_VV_M2_MASK + 10U, // PseudoVFWMUL_VV_M4 + 10U, // PseudoVFWMUL_VV_M4_MASK + 10U, // PseudoVFWMUL_VV_MF2 + 10U, // PseudoVFWMUL_VV_MF2_MASK + 10U, // PseudoVFWMUL_VV_MF4 + 10U, // PseudoVFWMUL_VV_MF4_MASK + 10U, // PseudoVFWMUL_VV_MF8 + 10U, // PseudoVFWMUL_VV_MF8_MASK + 10U, // PseudoVFWNMACC_VF16_M1 + 10U, // PseudoVFWNMACC_VF16_M1_MASK + 10U, // PseudoVFWNMACC_VF16_M2 + 10U, // PseudoVFWNMACC_VF16_M2_MASK + 10U, // PseudoVFWNMACC_VF16_M4 + 10U, // PseudoVFWNMACC_VF16_M4_MASK + 10U, // PseudoVFWNMACC_VF16_MF2 + 10U, // PseudoVFWNMACC_VF16_MF2_MASK + 10U, // PseudoVFWNMACC_VF16_MF4 + 10U, // PseudoVFWNMACC_VF16_MF4_MASK + 10U, // PseudoVFWNMACC_VF16_MF8 + 10U, // PseudoVFWNMACC_VF16_MF8_MASK + 10U, // PseudoVFWNMACC_VF32_M1 + 10U, // PseudoVFWNMACC_VF32_M1_MASK + 10U, // PseudoVFWNMACC_VF32_M2 + 10U, // PseudoVFWNMACC_VF32_M2_MASK + 10U, // PseudoVFWNMACC_VF32_M4 + 10U, // PseudoVFWNMACC_VF32_M4_MASK + 10U, // PseudoVFWNMACC_VF32_MF2 + 10U, // PseudoVFWNMACC_VF32_MF2_MASK + 10U, // PseudoVFWNMACC_VF32_MF4 + 10U, // PseudoVFWNMACC_VF32_MF4_MASK + 10U, // PseudoVFWNMACC_VF32_MF8 + 10U, // PseudoVFWNMACC_VF32_MF8_MASK + 10U, // PseudoVFWNMACC_VV_M1 + 10U, // PseudoVFWNMACC_VV_M1_MASK + 10U, // PseudoVFWNMACC_VV_M2 + 10U, // PseudoVFWNMACC_VV_M2_MASK + 10U, // PseudoVFWNMACC_VV_M4 + 10U, // PseudoVFWNMACC_VV_M4_MASK + 10U, // PseudoVFWNMACC_VV_MF2 + 10U, // PseudoVFWNMACC_VV_MF2_MASK + 10U, // PseudoVFWNMACC_VV_MF4 + 10U, // PseudoVFWNMACC_VV_MF4_MASK + 10U, // PseudoVFWNMACC_VV_MF8 + 10U, // PseudoVFWNMACC_VV_MF8_MASK + 10U, // PseudoVFWNMSAC_VF16_M1 + 10U, // PseudoVFWNMSAC_VF16_M1_MASK + 10U, // PseudoVFWNMSAC_VF16_M2 + 10U, // PseudoVFWNMSAC_VF16_M2_MASK + 10U, // PseudoVFWNMSAC_VF16_M4 + 10U, // PseudoVFWNMSAC_VF16_M4_MASK + 10U, // PseudoVFWNMSAC_VF16_MF2 + 10U, // PseudoVFWNMSAC_VF16_MF2_MASK + 10U, // PseudoVFWNMSAC_VF16_MF4 + 10U, // PseudoVFWNMSAC_VF16_MF4_MASK + 10U, // PseudoVFWNMSAC_VF16_MF8 + 10U, // PseudoVFWNMSAC_VF16_MF8_MASK + 10U, // PseudoVFWNMSAC_VF32_M1 + 10U, // PseudoVFWNMSAC_VF32_M1_MASK + 10U, // PseudoVFWNMSAC_VF32_M2 + 10U, // PseudoVFWNMSAC_VF32_M2_MASK + 10U, // PseudoVFWNMSAC_VF32_M4 + 10U, // PseudoVFWNMSAC_VF32_M4_MASK + 10U, // PseudoVFWNMSAC_VF32_MF2 + 10U, // PseudoVFWNMSAC_VF32_MF2_MASK + 10U, // PseudoVFWNMSAC_VF32_MF4 + 10U, // PseudoVFWNMSAC_VF32_MF4_MASK + 10U, // PseudoVFWNMSAC_VF32_MF8 + 10U, // PseudoVFWNMSAC_VF32_MF8_MASK + 10U, // PseudoVFWNMSAC_VV_M1 + 10U, // PseudoVFWNMSAC_VV_M1_MASK + 10U, // PseudoVFWNMSAC_VV_M2 + 10U, // PseudoVFWNMSAC_VV_M2_MASK + 10U, // PseudoVFWNMSAC_VV_M4 + 10U, // PseudoVFWNMSAC_VV_M4_MASK + 10U, // PseudoVFWNMSAC_VV_MF2 + 10U, // PseudoVFWNMSAC_VV_MF2_MASK + 10U, // PseudoVFWNMSAC_VV_MF4 + 10U, // PseudoVFWNMSAC_VV_MF4_MASK + 10U, // PseudoVFWNMSAC_VV_MF8 + 10U, // PseudoVFWNMSAC_VV_MF8_MASK + 10U, // PseudoVFWREDOSUM_VS_M1 + 10U, // PseudoVFWREDOSUM_VS_M1_MASK + 10U, // PseudoVFWREDOSUM_VS_M2 + 10U, // PseudoVFWREDOSUM_VS_M2_MASK + 10U, // PseudoVFWREDOSUM_VS_M4 + 10U, // PseudoVFWREDOSUM_VS_M4_MASK + 10U, // PseudoVFWREDOSUM_VS_M8 + 10U, // PseudoVFWREDOSUM_VS_M8_MASK + 10U, // PseudoVFWREDOSUM_VS_MF2 + 10U, // PseudoVFWREDOSUM_VS_MF2_MASK + 10U, // PseudoVFWREDOSUM_VS_MF4 + 10U, // PseudoVFWREDOSUM_VS_MF4_MASK + 10U, // PseudoVFWREDOSUM_VS_MF8 + 10U, // PseudoVFWREDOSUM_VS_MF8_MASK + 10U, // PseudoVFWREDUSUM_VS_M1 + 10U, // PseudoVFWREDUSUM_VS_M1_MASK + 10U, // PseudoVFWREDUSUM_VS_M2 + 10U, // PseudoVFWREDUSUM_VS_M2_MASK + 10U, // PseudoVFWREDUSUM_VS_M4 + 10U, // PseudoVFWREDUSUM_VS_M4_MASK + 10U, // PseudoVFWREDUSUM_VS_M8 + 10U, // PseudoVFWREDUSUM_VS_M8_MASK + 10U, // PseudoVFWREDUSUM_VS_MF2 + 10U, // PseudoVFWREDUSUM_VS_MF2_MASK + 10U, // PseudoVFWREDUSUM_VS_MF4 + 10U, // PseudoVFWREDUSUM_VS_MF4_MASK + 10U, // PseudoVFWREDUSUM_VS_MF8 + 10U, // PseudoVFWREDUSUM_VS_MF8_MASK + 10U, // PseudoVFWSUB_VF16_M1 + 10U, // PseudoVFWSUB_VF16_M1_MASK + 10U, // PseudoVFWSUB_VF16_M2 + 10U, // PseudoVFWSUB_VF16_M2_MASK + 10U, // PseudoVFWSUB_VF16_M4 + 10U, // PseudoVFWSUB_VF16_M4_MASK + 10U, // PseudoVFWSUB_VF16_MF2 + 10U, // PseudoVFWSUB_VF16_MF2_MASK + 10U, // PseudoVFWSUB_VF16_MF4 + 10U, // PseudoVFWSUB_VF16_MF4_MASK + 10U, // PseudoVFWSUB_VF16_MF8 + 10U, // PseudoVFWSUB_VF16_MF8_MASK + 10U, // PseudoVFWSUB_VF32_M1 + 10U, // PseudoVFWSUB_VF32_M1_MASK + 10U, // PseudoVFWSUB_VF32_M2 + 10U, // PseudoVFWSUB_VF32_M2_MASK + 10U, // PseudoVFWSUB_VF32_M4 + 10U, // PseudoVFWSUB_VF32_M4_MASK + 10U, // PseudoVFWSUB_VF32_MF2 + 10U, // PseudoVFWSUB_VF32_MF2_MASK + 10U, // PseudoVFWSUB_VF32_MF4 + 10U, // PseudoVFWSUB_VF32_MF4_MASK + 10U, // PseudoVFWSUB_VF32_MF8 + 10U, // PseudoVFWSUB_VF32_MF8_MASK + 10U, // PseudoVFWSUB_VV_M1 + 10U, // PseudoVFWSUB_VV_M1_MASK + 10U, // PseudoVFWSUB_VV_M2 + 10U, // PseudoVFWSUB_VV_M2_MASK + 10U, // PseudoVFWSUB_VV_M4 + 10U, // PseudoVFWSUB_VV_M4_MASK + 10U, // PseudoVFWSUB_VV_MF2 + 10U, // PseudoVFWSUB_VV_MF2_MASK + 10U, // PseudoVFWSUB_VV_MF4 + 10U, // PseudoVFWSUB_VV_MF4_MASK + 10U, // PseudoVFWSUB_VV_MF8 + 10U, // PseudoVFWSUB_VV_MF8_MASK + 10U, // PseudoVFWSUB_WF16_M1 + 10U, // PseudoVFWSUB_WF16_M1_MASK + 10U, // PseudoVFWSUB_WF16_M2 + 10U, // PseudoVFWSUB_WF16_M2_MASK + 10U, // PseudoVFWSUB_WF16_M4 + 10U, // PseudoVFWSUB_WF16_M4_MASK + 10U, // PseudoVFWSUB_WF16_MF2 + 10U, // PseudoVFWSUB_WF16_MF2_MASK + 10U, // PseudoVFWSUB_WF16_MF4 + 10U, // PseudoVFWSUB_WF16_MF4_MASK + 10U, // PseudoVFWSUB_WF16_MF8 + 10U, // PseudoVFWSUB_WF16_MF8_MASK + 10U, // PseudoVFWSUB_WF32_M1 + 10U, // PseudoVFWSUB_WF32_M1_MASK + 10U, // PseudoVFWSUB_WF32_M2 + 10U, // PseudoVFWSUB_WF32_M2_MASK + 10U, // PseudoVFWSUB_WF32_M4 + 10U, // PseudoVFWSUB_WF32_M4_MASK + 10U, // PseudoVFWSUB_WF32_MF2 + 10U, // PseudoVFWSUB_WF32_MF2_MASK + 10U, // PseudoVFWSUB_WF32_MF4 + 10U, // PseudoVFWSUB_WF32_MF4_MASK + 10U, // PseudoVFWSUB_WF32_MF8 + 10U, // PseudoVFWSUB_WF32_MF8_MASK + 10U, // PseudoVFWSUB_WV_M1 + 10U, // PseudoVFWSUB_WV_M1_MASK + 10U, // PseudoVFWSUB_WV_M1_MASK_TIED + 10U, // PseudoVFWSUB_WV_M1_TIED + 10U, // PseudoVFWSUB_WV_M2 + 10U, // PseudoVFWSUB_WV_M2_MASK + 10U, // PseudoVFWSUB_WV_M2_MASK_TIED + 10U, // PseudoVFWSUB_WV_M2_TIED + 10U, // PseudoVFWSUB_WV_M4 + 10U, // PseudoVFWSUB_WV_M4_MASK + 10U, // PseudoVFWSUB_WV_M4_MASK_TIED + 10U, // PseudoVFWSUB_WV_M4_TIED + 10U, // PseudoVFWSUB_WV_MF2 + 10U, // PseudoVFWSUB_WV_MF2_MASK + 10U, // PseudoVFWSUB_WV_MF2_MASK_TIED + 10U, // PseudoVFWSUB_WV_MF2_TIED + 10U, // PseudoVFWSUB_WV_MF4 + 10U, // PseudoVFWSUB_WV_MF4_MASK + 10U, // PseudoVFWSUB_WV_MF4_MASK_TIED + 10U, // PseudoVFWSUB_WV_MF4_TIED + 10U, // PseudoVFWSUB_WV_MF8 + 10U, // PseudoVFWSUB_WV_MF8_MASK + 10U, // PseudoVFWSUB_WV_MF8_MASK_TIED + 10U, // PseudoVFWSUB_WV_MF8_TIED + 10U, // PseudoVID_V_M1 + 10U, // PseudoVID_V_M1_MASK + 10U, // PseudoVID_V_M2 + 10U, // PseudoVID_V_M2_MASK + 10U, // PseudoVID_V_M4 + 10U, // PseudoVID_V_M4_MASK + 10U, // PseudoVID_V_M8 + 10U, // PseudoVID_V_M8_MASK + 10U, // PseudoVID_V_MF2 + 10U, // PseudoVID_V_MF2_MASK + 10U, // PseudoVID_V_MF4 + 10U, // PseudoVID_V_MF4_MASK + 10U, // PseudoVID_V_MF8 + 10U, // PseudoVID_V_MF8_MASK + 10U, // PseudoVIOTA_M_M1 + 10U, // PseudoVIOTA_M_M1_MASK + 10U, // PseudoVIOTA_M_M2 + 10U, // PseudoVIOTA_M_M2_MASK + 10U, // PseudoVIOTA_M_M4 + 10U, // PseudoVIOTA_M_M4_MASK + 10U, // PseudoVIOTA_M_M8 + 10U, // PseudoVIOTA_M_M8_MASK + 10U, // PseudoVIOTA_M_MF2 + 10U, // PseudoVIOTA_M_MF2_MASK + 10U, // PseudoVIOTA_M_MF4 + 10U, // PseudoVIOTA_M_MF4_MASK + 10U, // PseudoVIOTA_M_MF8 + 10U, // PseudoVIOTA_M_MF8_MASK + 10U, // PseudoVLE16FF_V_M1 + 10U, // PseudoVLE16FF_V_M1_MASK + 10U, // PseudoVLE16FF_V_M2 + 10U, // PseudoVLE16FF_V_M2_MASK + 10U, // PseudoVLE16FF_V_M4 + 10U, // PseudoVLE16FF_V_M4_MASK + 10U, // PseudoVLE16FF_V_M8 + 10U, // PseudoVLE16FF_V_M8_MASK + 10U, // PseudoVLE16FF_V_MF2 + 10U, // PseudoVLE16FF_V_MF2_MASK + 10U, // PseudoVLE16FF_V_MF4 + 10U, // PseudoVLE16FF_V_MF4_MASK + 10U, // PseudoVLE16_V_M1 + 10U, // PseudoVLE16_V_M1_MASK + 10U, // PseudoVLE16_V_M2 + 10U, // PseudoVLE16_V_M2_MASK + 10U, // PseudoVLE16_V_M4 + 10U, // PseudoVLE16_V_M4_MASK + 10U, // PseudoVLE16_V_M8 + 10U, // PseudoVLE16_V_M8_MASK + 10U, // PseudoVLE16_V_MF2 + 10U, // PseudoVLE16_V_MF2_MASK + 10U, // PseudoVLE16_V_MF4 + 10U, // PseudoVLE16_V_MF4_MASK + 10U, // PseudoVLE32FF_V_M1 + 10U, // PseudoVLE32FF_V_M1_MASK + 10U, // PseudoVLE32FF_V_M2 + 10U, // PseudoVLE32FF_V_M2_MASK + 10U, // PseudoVLE32FF_V_M4 + 10U, // PseudoVLE32FF_V_M4_MASK + 10U, // PseudoVLE32FF_V_M8 + 10U, // PseudoVLE32FF_V_M8_MASK + 10U, // PseudoVLE32FF_V_MF2 + 10U, // PseudoVLE32FF_V_MF2_MASK + 10U, // PseudoVLE32_V_M1 + 10U, // PseudoVLE32_V_M1_MASK + 10U, // PseudoVLE32_V_M2 + 10U, // PseudoVLE32_V_M2_MASK + 10U, // PseudoVLE32_V_M4 + 10U, // PseudoVLE32_V_M4_MASK + 10U, // PseudoVLE32_V_M8 + 10U, // PseudoVLE32_V_M8_MASK + 10U, // PseudoVLE32_V_MF2 + 10U, // PseudoVLE32_V_MF2_MASK + 10U, // PseudoVLE64FF_V_M1 + 10U, // PseudoVLE64FF_V_M1_MASK + 10U, // PseudoVLE64FF_V_M2 + 10U, // PseudoVLE64FF_V_M2_MASK + 10U, // PseudoVLE64FF_V_M4 + 10U, // PseudoVLE64FF_V_M4_MASK + 10U, // PseudoVLE64FF_V_M8 + 10U, // PseudoVLE64FF_V_M8_MASK + 10U, // PseudoVLE64_V_M1 + 10U, // PseudoVLE64_V_M1_MASK + 10U, // PseudoVLE64_V_M2 + 10U, // PseudoVLE64_V_M2_MASK + 10U, // PseudoVLE64_V_M4 + 10U, // PseudoVLE64_V_M4_MASK + 10U, // PseudoVLE64_V_M8 + 10U, // PseudoVLE64_V_M8_MASK + 10U, // PseudoVLE8FF_V_M1 + 10U, // PseudoVLE8FF_V_M1_MASK + 10U, // PseudoVLE8FF_V_M2 + 10U, // PseudoVLE8FF_V_M2_MASK + 10U, // PseudoVLE8FF_V_M4 + 10U, // PseudoVLE8FF_V_M4_MASK + 10U, // PseudoVLE8FF_V_M8 + 10U, // PseudoVLE8FF_V_M8_MASK + 10U, // PseudoVLE8FF_V_MF2 + 10U, // PseudoVLE8FF_V_MF2_MASK + 10U, // PseudoVLE8FF_V_MF4 + 10U, // PseudoVLE8FF_V_MF4_MASK + 10U, // PseudoVLE8FF_V_MF8 + 10U, // PseudoVLE8FF_V_MF8_MASK + 10U, // PseudoVLE8_V_M1 + 10U, // PseudoVLE8_V_M1_MASK + 10U, // PseudoVLE8_V_M2 + 10U, // PseudoVLE8_V_M2_MASK + 10U, // PseudoVLE8_V_M4 + 10U, // PseudoVLE8_V_M4_MASK + 10U, // PseudoVLE8_V_M8 + 10U, // PseudoVLE8_V_M8_MASK + 10U, // PseudoVLE8_V_MF2 + 10U, // PseudoVLE8_V_MF2_MASK + 10U, // PseudoVLE8_V_MF4 + 10U, // PseudoVLE8_V_MF4_MASK + 10U, // PseudoVLE8_V_MF8 + 10U, // PseudoVLE8_V_MF8_MASK + 10U, // PseudoVLM_V_B1 + 10U, // PseudoVLM_V_B16 + 10U, // PseudoVLM_V_B2 + 10U, // PseudoVLM_V_B32 + 10U, // PseudoVLM_V_B4 + 10U, // PseudoVLM_V_B64 + 10U, // PseudoVLM_V_B8 + 10U, // PseudoVLOXEI16_V_M1_M1 + 10U, // PseudoVLOXEI16_V_M1_M1_MASK + 10U, // PseudoVLOXEI16_V_M1_M2 + 10U, // PseudoVLOXEI16_V_M1_M2_MASK + 10U, // PseudoVLOXEI16_V_M1_M4 + 10U, // PseudoVLOXEI16_V_M1_M4_MASK + 10U, // PseudoVLOXEI16_V_M1_MF2 + 10U, // PseudoVLOXEI16_V_M1_MF2_MASK + 10U, // PseudoVLOXEI16_V_M2_M1 + 10U, // PseudoVLOXEI16_V_M2_M1_MASK + 10U, // PseudoVLOXEI16_V_M2_M2 + 10U, // PseudoVLOXEI16_V_M2_M2_MASK + 10U, // PseudoVLOXEI16_V_M2_M4 + 10U, // PseudoVLOXEI16_V_M2_M4_MASK + 10U, // PseudoVLOXEI16_V_M2_M8 + 10U, // PseudoVLOXEI16_V_M2_M8_MASK + 10U, // PseudoVLOXEI16_V_M4_M2 + 10U, // PseudoVLOXEI16_V_M4_M2_MASK + 10U, // PseudoVLOXEI16_V_M4_M4 + 10U, // PseudoVLOXEI16_V_M4_M4_MASK + 10U, // PseudoVLOXEI16_V_M4_M8 + 10U, // PseudoVLOXEI16_V_M4_M8_MASK + 10U, // PseudoVLOXEI16_V_M8_M4 + 10U, // PseudoVLOXEI16_V_M8_M4_MASK + 10U, // PseudoVLOXEI16_V_M8_M8 + 10U, // PseudoVLOXEI16_V_M8_M8_MASK + 10U, // PseudoVLOXEI16_V_MF2_M1 + 10U, // PseudoVLOXEI16_V_MF2_M1_MASK + 10U, // PseudoVLOXEI16_V_MF2_M2 + 10U, // PseudoVLOXEI16_V_MF2_M2_MASK + 10U, // PseudoVLOXEI16_V_MF2_MF2 + 10U, // PseudoVLOXEI16_V_MF2_MF2_MASK + 10U, // PseudoVLOXEI16_V_MF2_MF4 + 10U, // PseudoVLOXEI16_V_MF2_MF4_MASK + 10U, // PseudoVLOXEI16_V_MF4_M1 + 10U, // PseudoVLOXEI16_V_MF4_M1_MASK + 10U, // PseudoVLOXEI16_V_MF4_MF2 + 10U, // PseudoVLOXEI16_V_MF4_MF2_MASK + 10U, // PseudoVLOXEI16_V_MF4_MF4 + 10U, // PseudoVLOXEI16_V_MF4_MF4_MASK + 10U, // PseudoVLOXEI16_V_MF4_MF8 + 10U, // PseudoVLOXEI16_V_MF4_MF8_MASK + 10U, // PseudoVLOXEI32_V_M1_M1 + 10U, // PseudoVLOXEI32_V_M1_M1_MASK + 10U, // PseudoVLOXEI32_V_M1_M2 + 10U, // PseudoVLOXEI32_V_M1_M2_MASK + 10U, // PseudoVLOXEI32_V_M1_MF2 + 10U, // PseudoVLOXEI32_V_M1_MF2_MASK + 10U, // PseudoVLOXEI32_V_M1_MF4 + 10U, // PseudoVLOXEI32_V_M1_MF4_MASK + 10U, // PseudoVLOXEI32_V_M2_M1 + 10U, // PseudoVLOXEI32_V_M2_M1_MASK + 10U, // PseudoVLOXEI32_V_M2_M2 + 10U, // PseudoVLOXEI32_V_M2_M2_MASK + 10U, // PseudoVLOXEI32_V_M2_M4 + 10U, // PseudoVLOXEI32_V_M2_M4_MASK + 10U, // PseudoVLOXEI32_V_M2_MF2 + 10U, // PseudoVLOXEI32_V_M2_MF2_MASK + 10U, // PseudoVLOXEI32_V_M4_M1 + 10U, // PseudoVLOXEI32_V_M4_M1_MASK + 10U, // PseudoVLOXEI32_V_M4_M2 + 10U, // PseudoVLOXEI32_V_M4_M2_MASK + 10U, // PseudoVLOXEI32_V_M4_M4 + 10U, // PseudoVLOXEI32_V_M4_M4_MASK + 10U, // PseudoVLOXEI32_V_M4_M8 + 10U, // PseudoVLOXEI32_V_M4_M8_MASK + 10U, // PseudoVLOXEI32_V_M8_M2 + 10U, // PseudoVLOXEI32_V_M8_M2_MASK + 10U, // PseudoVLOXEI32_V_M8_M4 + 10U, // PseudoVLOXEI32_V_M8_M4_MASK + 10U, // PseudoVLOXEI32_V_M8_M8 + 10U, // PseudoVLOXEI32_V_M8_M8_MASK + 10U, // PseudoVLOXEI32_V_MF2_M1 + 10U, // PseudoVLOXEI32_V_MF2_M1_MASK + 10U, // PseudoVLOXEI32_V_MF2_MF2 + 10U, // PseudoVLOXEI32_V_MF2_MF2_MASK + 10U, // PseudoVLOXEI32_V_MF2_MF4 + 10U, // PseudoVLOXEI32_V_MF2_MF4_MASK + 10U, // PseudoVLOXEI32_V_MF2_MF8 + 10U, // PseudoVLOXEI32_V_MF2_MF8_MASK + 10U, // PseudoVLOXEI64_V_M1_M1 + 10U, // PseudoVLOXEI64_V_M1_M1_MASK + 10U, // PseudoVLOXEI64_V_M1_MF2 + 10U, // PseudoVLOXEI64_V_M1_MF2_MASK + 10U, // PseudoVLOXEI64_V_M1_MF4 + 10U, // PseudoVLOXEI64_V_M1_MF4_MASK + 10U, // PseudoVLOXEI64_V_M1_MF8 + 10U, // PseudoVLOXEI64_V_M1_MF8_MASK + 10U, // PseudoVLOXEI64_V_M2_M1 + 10U, // PseudoVLOXEI64_V_M2_M1_MASK + 10U, // PseudoVLOXEI64_V_M2_M2 + 10U, // PseudoVLOXEI64_V_M2_M2_MASK + 10U, // PseudoVLOXEI64_V_M2_MF2 + 10U, // PseudoVLOXEI64_V_M2_MF2_MASK + 10U, // PseudoVLOXEI64_V_M2_MF4 + 10U, // PseudoVLOXEI64_V_M2_MF4_MASK + 10U, // PseudoVLOXEI64_V_M4_M1 + 10U, // PseudoVLOXEI64_V_M4_M1_MASK + 10U, // PseudoVLOXEI64_V_M4_M2 + 10U, // PseudoVLOXEI64_V_M4_M2_MASK + 10U, // PseudoVLOXEI64_V_M4_M4 + 10U, // PseudoVLOXEI64_V_M4_M4_MASK + 10U, // PseudoVLOXEI64_V_M4_MF2 + 10U, // PseudoVLOXEI64_V_M4_MF2_MASK + 10U, // PseudoVLOXEI64_V_M8_M1 + 10U, // PseudoVLOXEI64_V_M8_M1_MASK + 10U, // PseudoVLOXEI64_V_M8_M2 + 10U, // PseudoVLOXEI64_V_M8_M2_MASK + 10U, // PseudoVLOXEI64_V_M8_M4 + 10U, // PseudoVLOXEI64_V_M8_M4_MASK + 10U, // PseudoVLOXEI64_V_M8_M8 + 10U, // PseudoVLOXEI64_V_M8_M8_MASK + 10U, // PseudoVLOXEI8_V_M1_M1 + 10U, // PseudoVLOXEI8_V_M1_M1_MASK + 10U, // PseudoVLOXEI8_V_M1_M2 + 10U, // PseudoVLOXEI8_V_M1_M2_MASK + 10U, // PseudoVLOXEI8_V_M1_M4 + 10U, // PseudoVLOXEI8_V_M1_M4_MASK + 10U, // PseudoVLOXEI8_V_M1_M8 + 10U, // PseudoVLOXEI8_V_M1_M8_MASK + 10U, // PseudoVLOXEI8_V_M2_M2 + 10U, // PseudoVLOXEI8_V_M2_M2_MASK + 10U, // PseudoVLOXEI8_V_M2_M4 + 10U, // PseudoVLOXEI8_V_M2_M4_MASK + 10U, // PseudoVLOXEI8_V_M2_M8 + 10U, // PseudoVLOXEI8_V_M2_M8_MASK + 10U, // PseudoVLOXEI8_V_M4_M4 + 10U, // PseudoVLOXEI8_V_M4_M4_MASK + 10U, // PseudoVLOXEI8_V_M4_M8 + 10U, // PseudoVLOXEI8_V_M4_M8_MASK + 10U, // PseudoVLOXEI8_V_M8_M8 + 10U, // PseudoVLOXEI8_V_M8_M8_MASK + 10U, // PseudoVLOXEI8_V_MF2_M1 + 10U, // PseudoVLOXEI8_V_MF2_M1_MASK + 10U, // PseudoVLOXEI8_V_MF2_M2 + 10U, // PseudoVLOXEI8_V_MF2_M2_MASK + 10U, // PseudoVLOXEI8_V_MF2_M4 + 10U, // PseudoVLOXEI8_V_MF2_M4_MASK + 10U, // PseudoVLOXEI8_V_MF2_MF2 + 10U, // PseudoVLOXEI8_V_MF2_MF2_MASK + 10U, // PseudoVLOXEI8_V_MF4_M1 + 10U, // PseudoVLOXEI8_V_MF4_M1_MASK + 10U, // PseudoVLOXEI8_V_MF4_M2 + 10U, // PseudoVLOXEI8_V_MF4_M2_MASK + 10U, // PseudoVLOXEI8_V_MF4_MF2 + 10U, // PseudoVLOXEI8_V_MF4_MF2_MASK + 10U, // PseudoVLOXEI8_V_MF4_MF4 + 10U, // PseudoVLOXEI8_V_MF4_MF4_MASK + 10U, // PseudoVLOXEI8_V_MF8_M1 + 10U, // PseudoVLOXEI8_V_MF8_M1_MASK + 10U, // PseudoVLOXEI8_V_MF8_MF2 + 10U, // PseudoVLOXEI8_V_MF8_MF2_MASK + 10U, // PseudoVLOXEI8_V_MF8_MF4 + 10U, // PseudoVLOXEI8_V_MF8_MF4_MASK + 10U, // PseudoVLOXEI8_V_MF8_MF8 + 10U, // PseudoVLOXEI8_V_MF8_MF8_MASK + 10U, // PseudoVLOXSEG2EI16_V_M1_M1 + 10U, // PseudoVLOXSEG2EI16_V_M1_M1_MASK + 10U, // PseudoVLOXSEG2EI16_V_M1_M2 + 10U, // PseudoVLOXSEG2EI16_V_M1_M2_MASK + 10U, // PseudoVLOXSEG2EI16_V_M1_M4 + 10U, // PseudoVLOXSEG2EI16_V_M1_M4_MASK + 10U, // PseudoVLOXSEG2EI16_V_M1_MF2 + 10U, // PseudoVLOXSEG2EI16_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG2EI16_V_M2_M1 + 10U, // PseudoVLOXSEG2EI16_V_M2_M1_MASK + 10U, // PseudoVLOXSEG2EI16_V_M2_M2 + 10U, // PseudoVLOXSEG2EI16_V_M2_M2_MASK + 10U, // PseudoVLOXSEG2EI16_V_M2_M4 + 10U, // PseudoVLOXSEG2EI16_V_M2_M4_MASK + 10U, // PseudoVLOXSEG2EI16_V_M4_M2 + 10U, // PseudoVLOXSEG2EI16_V_M4_M2_MASK + 10U, // PseudoVLOXSEG2EI16_V_M4_M4 + 10U, // PseudoVLOXSEG2EI16_V_M4_M4_MASK + 10U, // PseudoVLOXSEG2EI16_V_M8_M4 + 10U, // PseudoVLOXSEG2EI16_V_M8_M4_MASK + 10U, // PseudoVLOXSEG2EI16_V_MF2_M1 + 10U, // PseudoVLOXSEG2EI16_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG2EI16_V_MF2_M2 + 10U, // PseudoVLOXSEG2EI16_V_MF2_M2_MASK + 10U, // PseudoVLOXSEG2EI16_V_MF2_MF2 + 10U, // PseudoVLOXSEG2EI16_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG2EI16_V_MF2_MF4 + 10U, // PseudoVLOXSEG2EI16_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG2EI16_V_MF4_M1 + 10U, // PseudoVLOXSEG2EI16_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG2EI16_V_MF4_MF2 + 10U, // PseudoVLOXSEG2EI16_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG2EI16_V_MF4_MF4 + 10U, // PseudoVLOXSEG2EI16_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG2EI16_V_MF4_MF8 + 10U, // PseudoVLOXSEG2EI16_V_MF4_MF8_MASK + 10U, // PseudoVLOXSEG2EI32_V_M1_M1 + 10U, // PseudoVLOXSEG2EI32_V_M1_M1_MASK + 10U, // PseudoVLOXSEG2EI32_V_M1_M2 + 10U, // PseudoVLOXSEG2EI32_V_M1_M2_MASK + 10U, // PseudoVLOXSEG2EI32_V_M1_MF2 + 10U, // PseudoVLOXSEG2EI32_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG2EI32_V_M1_MF4 + 10U, // PseudoVLOXSEG2EI32_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG2EI32_V_M2_M1 + 10U, // PseudoVLOXSEG2EI32_V_M2_M1_MASK + 10U, // PseudoVLOXSEG2EI32_V_M2_M2 + 10U, // PseudoVLOXSEG2EI32_V_M2_M2_MASK + 10U, // PseudoVLOXSEG2EI32_V_M2_M4 + 10U, // PseudoVLOXSEG2EI32_V_M2_M4_MASK + 10U, // PseudoVLOXSEG2EI32_V_M2_MF2 + 10U, // PseudoVLOXSEG2EI32_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG2EI32_V_M4_M1 + 10U, // PseudoVLOXSEG2EI32_V_M4_M1_MASK + 10U, // PseudoVLOXSEG2EI32_V_M4_M2 + 10U, // PseudoVLOXSEG2EI32_V_M4_M2_MASK + 10U, // PseudoVLOXSEG2EI32_V_M4_M4 + 10U, // PseudoVLOXSEG2EI32_V_M4_M4_MASK + 10U, // PseudoVLOXSEG2EI32_V_M8_M2 + 10U, // PseudoVLOXSEG2EI32_V_M8_M2_MASK + 10U, // PseudoVLOXSEG2EI32_V_M8_M4 + 10U, // PseudoVLOXSEG2EI32_V_M8_M4_MASK + 10U, // PseudoVLOXSEG2EI32_V_MF2_M1 + 10U, // PseudoVLOXSEG2EI32_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG2EI32_V_MF2_MF2 + 10U, // PseudoVLOXSEG2EI32_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG2EI32_V_MF2_MF4 + 10U, // PseudoVLOXSEG2EI32_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG2EI32_V_MF2_MF8 + 10U, // PseudoVLOXSEG2EI32_V_MF2_MF8_MASK + 10U, // PseudoVLOXSEG2EI64_V_M1_M1 + 10U, // PseudoVLOXSEG2EI64_V_M1_M1_MASK + 10U, // PseudoVLOXSEG2EI64_V_M1_MF2 + 10U, // PseudoVLOXSEG2EI64_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG2EI64_V_M1_MF4 + 10U, // PseudoVLOXSEG2EI64_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG2EI64_V_M1_MF8 + 10U, // PseudoVLOXSEG2EI64_V_M1_MF8_MASK + 10U, // PseudoVLOXSEG2EI64_V_M2_M1 + 10U, // PseudoVLOXSEG2EI64_V_M2_M1_MASK + 10U, // PseudoVLOXSEG2EI64_V_M2_M2 + 10U, // PseudoVLOXSEG2EI64_V_M2_M2_MASK + 10U, // PseudoVLOXSEG2EI64_V_M2_MF2 + 10U, // PseudoVLOXSEG2EI64_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG2EI64_V_M2_MF4 + 10U, // PseudoVLOXSEG2EI64_V_M2_MF4_MASK + 10U, // PseudoVLOXSEG2EI64_V_M4_M1 + 10U, // PseudoVLOXSEG2EI64_V_M4_M1_MASK + 10U, // PseudoVLOXSEG2EI64_V_M4_M2 + 10U, // PseudoVLOXSEG2EI64_V_M4_M2_MASK + 10U, // PseudoVLOXSEG2EI64_V_M4_M4 + 10U, // PseudoVLOXSEG2EI64_V_M4_M4_MASK + 10U, // PseudoVLOXSEG2EI64_V_M4_MF2 + 10U, // PseudoVLOXSEG2EI64_V_M4_MF2_MASK + 10U, // PseudoVLOXSEG2EI64_V_M8_M1 + 10U, // PseudoVLOXSEG2EI64_V_M8_M1_MASK + 10U, // PseudoVLOXSEG2EI64_V_M8_M2 + 10U, // PseudoVLOXSEG2EI64_V_M8_M2_MASK + 10U, // PseudoVLOXSEG2EI64_V_M8_M4 + 10U, // PseudoVLOXSEG2EI64_V_M8_M4_MASK + 10U, // PseudoVLOXSEG2EI8_V_M1_M1 + 10U, // PseudoVLOXSEG2EI8_V_M1_M1_MASK + 10U, // PseudoVLOXSEG2EI8_V_M1_M2 + 10U, // PseudoVLOXSEG2EI8_V_M1_M2_MASK + 10U, // PseudoVLOXSEG2EI8_V_M1_M4 + 10U, // PseudoVLOXSEG2EI8_V_M1_M4_MASK + 10U, // PseudoVLOXSEG2EI8_V_M2_M2 + 10U, // PseudoVLOXSEG2EI8_V_M2_M2_MASK + 10U, // PseudoVLOXSEG2EI8_V_M2_M4 + 10U, // PseudoVLOXSEG2EI8_V_M2_M4_MASK + 10U, // PseudoVLOXSEG2EI8_V_M4_M4 + 10U, // PseudoVLOXSEG2EI8_V_M4_M4_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF2_M1 + 10U, // PseudoVLOXSEG2EI8_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF2_M2 + 10U, // PseudoVLOXSEG2EI8_V_MF2_M2_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF2_M4 + 10U, // PseudoVLOXSEG2EI8_V_MF2_M4_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF2_MF2 + 10U, // PseudoVLOXSEG2EI8_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF4_M1 + 10U, // PseudoVLOXSEG2EI8_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF4_M2 + 10U, // PseudoVLOXSEG2EI8_V_MF4_M2_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF4_MF2 + 10U, // PseudoVLOXSEG2EI8_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF4_MF4 + 10U, // PseudoVLOXSEG2EI8_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF8_M1 + 10U, // PseudoVLOXSEG2EI8_V_MF8_M1_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF8_MF2 + 10U, // PseudoVLOXSEG2EI8_V_MF8_MF2_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF8_MF4 + 10U, // PseudoVLOXSEG2EI8_V_MF8_MF4_MASK + 10U, // PseudoVLOXSEG2EI8_V_MF8_MF8 + 10U, // PseudoVLOXSEG2EI8_V_MF8_MF8_MASK + 10U, // PseudoVLOXSEG3EI16_V_M1_M1 + 10U, // PseudoVLOXSEG3EI16_V_M1_M1_MASK + 10U, // PseudoVLOXSEG3EI16_V_M1_M2 + 10U, // PseudoVLOXSEG3EI16_V_M1_M2_MASK + 10U, // PseudoVLOXSEG3EI16_V_M1_MF2 + 10U, // PseudoVLOXSEG3EI16_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG3EI16_V_M2_M1 + 10U, // PseudoVLOXSEG3EI16_V_M2_M1_MASK + 10U, // PseudoVLOXSEG3EI16_V_M2_M2 + 10U, // PseudoVLOXSEG3EI16_V_M2_M2_MASK + 10U, // PseudoVLOXSEG3EI16_V_M4_M2 + 10U, // PseudoVLOXSEG3EI16_V_M4_M2_MASK + 10U, // PseudoVLOXSEG3EI16_V_MF2_M1 + 10U, // PseudoVLOXSEG3EI16_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG3EI16_V_MF2_M2 + 10U, // PseudoVLOXSEG3EI16_V_MF2_M2_MASK + 10U, // PseudoVLOXSEG3EI16_V_MF2_MF2 + 10U, // PseudoVLOXSEG3EI16_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG3EI16_V_MF2_MF4 + 10U, // PseudoVLOXSEG3EI16_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG3EI16_V_MF4_M1 + 10U, // PseudoVLOXSEG3EI16_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG3EI16_V_MF4_MF2 + 10U, // PseudoVLOXSEG3EI16_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG3EI16_V_MF4_MF4 + 10U, // PseudoVLOXSEG3EI16_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG3EI16_V_MF4_MF8 + 10U, // PseudoVLOXSEG3EI16_V_MF4_MF8_MASK + 10U, // PseudoVLOXSEG3EI32_V_M1_M1 + 10U, // PseudoVLOXSEG3EI32_V_M1_M1_MASK + 10U, // PseudoVLOXSEG3EI32_V_M1_M2 + 10U, // PseudoVLOXSEG3EI32_V_M1_M2_MASK + 10U, // PseudoVLOXSEG3EI32_V_M1_MF2 + 10U, // PseudoVLOXSEG3EI32_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG3EI32_V_M1_MF4 + 10U, // PseudoVLOXSEG3EI32_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG3EI32_V_M2_M1 + 10U, // PseudoVLOXSEG3EI32_V_M2_M1_MASK + 10U, // PseudoVLOXSEG3EI32_V_M2_M2 + 10U, // PseudoVLOXSEG3EI32_V_M2_M2_MASK + 10U, // PseudoVLOXSEG3EI32_V_M2_MF2 + 10U, // PseudoVLOXSEG3EI32_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG3EI32_V_M4_M1 + 10U, // PseudoVLOXSEG3EI32_V_M4_M1_MASK + 10U, // PseudoVLOXSEG3EI32_V_M4_M2 + 10U, // PseudoVLOXSEG3EI32_V_M4_M2_MASK + 10U, // PseudoVLOXSEG3EI32_V_M8_M2 + 10U, // PseudoVLOXSEG3EI32_V_M8_M2_MASK + 10U, // PseudoVLOXSEG3EI32_V_MF2_M1 + 10U, // PseudoVLOXSEG3EI32_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG3EI32_V_MF2_MF2 + 10U, // PseudoVLOXSEG3EI32_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG3EI32_V_MF2_MF4 + 10U, // PseudoVLOXSEG3EI32_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG3EI32_V_MF2_MF8 + 10U, // PseudoVLOXSEG3EI32_V_MF2_MF8_MASK + 10U, // PseudoVLOXSEG3EI64_V_M1_M1 + 10U, // PseudoVLOXSEG3EI64_V_M1_M1_MASK + 10U, // PseudoVLOXSEG3EI64_V_M1_MF2 + 10U, // PseudoVLOXSEG3EI64_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG3EI64_V_M1_MF4 + 10U, // PseudoVLOXSEG3EI64_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG3EI64_V_M1_MF8 + 10U, // PseudoVLOXSEG3EI64_V_M1_MF8_MASK + 10U, // PseudoVLOXSEG3EI64_V_M2_M1 + 10U, // PseudoVLOXSEG3EI64_V_M2_M1_MASK + 10U, // PseudoVLOXSEG3EI64_V_M2_M2 + 10U, // PseudoVLOXSEG3EI64_V_M2_M2_MASK + 10U, // PseudoVLOXSEG3EI64_V_M2_MF2 + 10U, // PseudoVLOXSEG3EI64_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG3EI64_V_M2_MF4 + 10U, // PseudoVLOXSEG3EI64_V_M2_MF4_MASK + 10U, // PseudoVLOXSEG3EI64_V_M4_M1 + 10U, // PseudoVLOXSEG3EI64_V_M4_M1_MASK + 10U, // PseudoVLOXSEG3EI64_V_M4_M2 + 10U, // PseudoVLOXSEG3EI64_V_M4_M2_MASK + 10U, // PseudoVLOXSEG3EI64_V_M4_MF2 + 10U, // PseudoVLOXSEG3EI64_V_M4_MF2_MASK + 10U, // PseudoVLOXSEG3EI64_V_M8_M1 + 10U, // PseudoVLOXSEG3EI64_V_M8_M1_MASK + 10U, // PseudoVLOXSEG3EI64_V_M8_M2 + 10U, // PseudoVLOXSEG3EI64_V_M8_M2_MASK + 10U, // PseudoVLOXSEG3EI8_V_M1_M1 + 10U, // PseudoVLOXSEG3EI8_V_M1_M1_MASK + 10U, // PseudoVLOXSEG3EI8_V_M1_M2 + 10U, // PseudoVLOXSEG3EI8_V_M1_M2_MASK + 10U, // PseudoVLOXSEG3EI8_V_M2_M2 + 10U, // PseudoVLOXSEG3EI8_V_M2_M2_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF2_M1 + 10U, // PseudoVLOXSEG3EI8_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF2_M2 + 10U, // PseudoVLOXSEG3EI8_V_MF2_M2_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF2_MF2 + 10U, // PseudoVLOXSEG3EI8_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF4_M1 + 10U, // PseudoVLOXSEG3EI8_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF4_M2 + 10U, // PseudoVLOXSEG3EI8_V_MF4_M2_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF4_MF2 + 10U, // PseudoVLOXSEG3EI8_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF4_MF4 + 10U, // PseudoVLOXSEG3EI8_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF8_M1 + 10U, // PseudoVLOXSEG3EI8_V_MF8_M1_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF8_MF2 + 10U, // PseudoVLOXSEG3EI8_V_MF8_MF2_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF8_MF4 + 10U, // PseudoVLOXSEG3EI8_V_MF8_MF4_MASK + 10U, // PseudoVLOXSEG3EI8_V_MF8_MF8 + 10U, // PseudoVLOXSEG3EI8_V_MF8_MF8_MASK + 10U, // PseudoVLOXSEG4EI16_V_M1_M1 + 10U, // PseudoVLOXSEG4EI16_V_M1_M1_MASK + 10U, // PseudoVLOXSEG4EI16_V_M1_M2 + 10U, // PseudoVLOXSEG4EI16_V_M1_M2_MASK + 10U, // PseudoVLOXSEG4EI16_V_M1_MF2 + 10U, // PseudoVLOXSEG4EI16_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG4EI16_V_M2_M1 + 10U, // PseudoVLOXSEG4EI16_V_M2_M1_MASK + 10U, // PseudoVLOXSEG4EI16_V_M2_M2 + 10U, // PseudoVLOXSEG4EI16_V_M2_M2_MASK + 10U, // PseudoVLOXSEG4EI16_V_M4_M2 + 10U, // PseudoVLOXSEG4EI16_V_M4_M2_MASK + 10U, // PseudoVLOXSEG4EI16_V_MF2_M1 + 10U, // PseudoVLOXSEG4EI16_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG4EI16_V_MF2_M2 + 10U, // PseudoVLOXSEG4EI16_V_MF2_M2_MASK + 10U, // PseudoVLOXSEG4EI16_V_MF2_MF2 + 10U, // PseudoVLOXSEG4EI16_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG4EI16_V_MF2_MF4 + 10U, // PseudoVLOXSEG4EI16_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG4EI16_V_MF4_M1 + 10U, // PseudoVLOXSEG4EI16_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG4EI16_V_MF4_MF2 + 10U, // PseudoVLOXSEG4EI16_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG4EI16_V_MF4_MF4 + 10U, // PseudoVLOXSEG4EI16_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG4EI16_V_MF4_MF8 + 10U, // PseudoVLOXSEG4EI16_V_MF4_MF8_MASK + 10U, // PseudoVLOXSEG4EI32_V_M1_M1 + 10U, // PseudoVLOXSEG4EI32_V_M1_M1_MASK + 10U, // PseudoVLOXSEG4EI32_V_M1_M2 + 10U, // PseudoVLOXSEG4EI32_V_M1_M2_MASK + 10U, // PseudoVLOXSEG4EI32_V_M1_MF2 + 10U, // PseudoVLOXSEG4EI32_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG4EI32_V_M1_MF4 + 10U, // PseudoVLOXSEG4EI32_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG4EI32_V_M2_M1 + 10U, // PseudoVLOXSEG4EI32_V_M2_M1_MASK + 10U, // PseudoVLOXSEG4EI32_V_M2_M2 + 10U, // PseudoVLOXSEG4EI32_V_M2_M2_MASK + 10U, // PseudoVLOXSEG4EI32_V_M2_MF2 + 10U, // PseudoVLOXSEG4EI32_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG4EI32_V_M4_M1 + 10U, // PseudoVLOXSEG4EI32_V_M4_M1_MASK + 10U, // PseudoVLOXSEG4EI32_V_M4_M2 + 10U, // PseudoVLOXSEG4EI32_V_M4_M2_MASK + 10U, // PseudoVLOXSEG4EI32_V_M8_M2 + 10U, // PseudoVLOXSEG4EI32_V_M8_M2_MASK + 10U, // PseudoVLOXSEG4EI32_V_MF2_M1 + 10U, // PseudoVLOXSEG4EI32_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG4EI32_V_MF2_MF2 + 10U, // PseudoVLOXSEG4EI32_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG4EI32_V_MF2_MF4 + 10U, // PseudoVLOXSEG4EI32_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG4EI32_V_MF2_MF8 + 10U, // PseudoVLOXSEG4EI32_V_MF2_MF8_MASK + 10U, // PseudoVLOXSEG4EI64_V_M1_M1 + 10U, // PseudoVLOXSEG4EI64_V_M1_M1_MASK + 10U, // PseudoVLOXSEG4EI64_V_M1_MF2 + 10U, // PseudoVLOXSEG4EI64_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG4EI64_V_M1_MF4 + 10U, // PseudoVLOXSEG4EI64_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG4EI64_V_M1_MF8 + 10U, // PseudoVLOXSEG4EI64_V_M1_MF8_MASK + 10U, // PseudoVLOXSEG4EI64_V_M2_M1 + 10U, // PseudoVLOXSEG4EI64_V_M2_M1_MASK + 10U, // PseudoVLOXSEG4EI64_V_M2_M2 + 10U, // PseudoVLOXSEG4EI64_V_M2_M2_MASK + 10U, // PseudoVLOXSEG4EI64_V_M2_MF2 + 10U, // PseudoVLOXSEG4EI64_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG4EI64_V_M2_MF4 + 10U, // PseudoVLOXSEG4EI64_V_M2_MF4_MASK + 10U, // PseudoVLOXSEG4EI64_V_M4_M1 + 10U, // PseudoVLOXSEG4EI64_V_M4_M1_MASK + 10U, // PseudoVLOXSEG4EI64_V_M4_M2 + 10U, // PseudoVLOXSEG4EI64_V_M4_M2_MASK + 10U, // PseudoVLOXSEG4EI64_V_M4_MF2 + 10U, // PseudoVLOXSEG4EI64_V_M4_MF2_MASK + 10U, // PseudoVLOXSEG4EI64_V_M8_M1 + 10U, // PseudoVLOXSEG4EI64_V_M8_M1_MASK + 10U, // PseudoVLOXSEG4EI64_V_M8_M2 + 10U, // PseudoVLOXSEG4EI64_V_M8_M2_MASK + 10U, // PseudoVLOXSEG4EI8_V_M1_M1 + 10U, // PseudoVLOXSEG4EI8_V_M1_M1_MASK + 10U, // PseudoVLOXSEG4EI8_V_M1_M2 + 10U, // PseudoVLOXSEG4EI8_V_M1_M2_MASK + 10U, // PseudoVLOXSEG4EI8_V_M2_M2 + 10U, // PseudoVLOXSEG4EI8_V_M2_M2_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF2_M1 + 10U, // PseudoVLOXSEG4EI8_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF2_M2 + 10U, // PseudoVLOXSEG4EI8_V_MF2_M2_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF2_MF2 + 10U, // PseudoVLOXSEG4EI8_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF4_M1 + 10U, // PseudoVLOXSEG4EI8_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF4_M2 + 10U, // PseudoVLOXSEG4EI8_V_MF4_M2_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF4_MF2 + 10U, // PseudoVLOXSEG4EI8_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF4_MF4 + 10U, // PseudoVLOXSEG4EI8_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF8_M1 + 10U, // PseudoVLOXSEG4EI8_V_MF8_M1_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF8_MF2 + 10U, // PseudoVLOXSEG4EI8_V_MF8_MF2_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF8_MF4 + 10U, // PseudoVLOXSEG4EI8_V_MF8_MF4_MASK + 10U, // PseudoVLOXSEG4EI8_V_MF8_MF8 + 10U, // PseudoVLOXSEG4EI8_V_MF8_MF8_MASK + 10U, // PseudoVLOXSEG5EI16_V_M1_M1 + 10U, // PseudoVLOXSEG5EI16_V_M1_M1_MASK + 10U, // PseudoVLOXSEG5EI16_V_M1_MF2 + 10U, // PseudoVLOXSEG5EI16_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG5EI16_V_M2_M1 + 10U, // PseudoVLOXSEG5EI16_V_M2_M1_MASK + 10U, // PseudoVLOXSEG5EI16_V_MF2_M1 + 10U, // PseudoVLOXSEG5EI16_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG5EI16_V_MF2_MF2 + 10U, // PseudoVLOXSEG5EI16_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG5EI16_V_MF2_MF4 + 10U, // PseudoVLOXSEG5EI16_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG5EI16_V_MF4_M1 + 10U, // PseudoVLOXSEG5EI16_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG5EI16_V_MF4_MF2 + 10U, // PseudoVLOXSEG5EI16_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG5EI16_V_MF4_MF4 + 10U, // PseudoVLOXSEG5EI16_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG5EI16_V_MF4_MF8 + 10U, // PseudoVLOXSEG5EI16_V_MF4_MF8_MASK + 10U, // PseudoVLOXSEG5EI32_V_M1_M1 + 10U, // PseudoVLOXSEG5EI32_V_M1_M1_MASK + 10U, // PseudoVLOXSEG5EI32_V_M1_MF2 + 10U, // PseudoVLOXSEG5EI32_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG5EI32_V_M1_MF4 + 10U, // PseudoVLOXSEG5EI32_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG5EI32_V_M2_M1 + 10U, // PseudoVLOXSEG5EI32_V_M2_M1_MASK + 10U, // PseudoVLOXSEG5EI32_V_M2_MF2 + 10U, // PseudoVLOXSEG5EI32_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG5EI32_V_M4_M1 + 10U, // PseudoVLOXSEG5EI32_V_M4_M1_MASK + 10U, // PseudoVLOXSEG5EI32_V_MF2_M1 + 10U, // PseudoVLOXSEG5EI32_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG5EI32_V_MF2_MF2 + 10U, // PseudoVLOXSEG5EI32_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG5EI32_V_MF2_MF4 + 10U, // PseudoVLOXSEG5EI32_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG5EI32_V_MF2_MF8 + 10U, // PseudoVLOXSEG5EI32_V_MF2_MF8_MASK + 10U, // PseudoVLOXSEG5EI64_V_M1_M1 + 10U, // PseudoVLOXSEG5EI64_V_M1_M1_MASK + 10U, // PseudoVLOXSEG5EI64_V_M1_MF2 + 10U, // PseudoVLOXSEG5EI64_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG5EI64_V_M1_MF4 + 10U, // PseudoVLOXSEG5EI64_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG5EI64_V_M1_MF8 + 10U, // PseudoVLOXSEG5EI64_V_M1_MF8_MASK + 10U, // PseudoVLOXSEG5EI64_V_M2_M1 + 10U, // PseudoVLOXSEG5EI64_V_M2_M1_MASK + 10U, // PseudoVLOXSEG5EI64_V_M2_MF2 + 10U, // PseudoVLOXSEG5EI64_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG5EI64_V_M2_MF4 + 10U, // PseudoVLOXSEG5EI64_V_M2_MF4_MASK + 10U, // PseudoVLOXSEG5EI64_V_M4_M1 + 10U, // PseudoVLOXSEG5EI64_V_M4_M1_MASK + 10U, // PseudoVLOXSEG5EI64_V_M4_MF2 + 10U, // PseudoVLOXSEG5EI64_V_M4_MF2_MASK + 10U, // PseudoVLOXSEG5EI64_V_M8_M1 + 10U, // PseudoVLOXSEG5EI64_V_M8_M1_MASK + 10U, // PseudoVLOXSEG5EI8_V_M1_M1 + 10U, // PseudoVLOXSEG5EI8_V_M1_M1_MASK + 10U, // PseudoVLOXSEG5EI8_V_MF2_M1 + 10U, // PseudoVLOXSEG5EI8_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG5EI8_V_MF2_MF2 + 10U, // PseudoVLOXSEG5EI8_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG5EI8_V_MF4_M1 + 10U, // PseudoVLOXSEG5EI8_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG5EI8_V_MF4_MF2 + 10U, // PseudoVLOXSEG5EI8_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG5EI8_V_MF4_MF4 + 10U, // PseudoVLOXSEG5EI8_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG5EI8_V_MF8_M1 + 10U, // PseudoVLOXSEG5EI8_V_MF8_M1_MASK + 10U, // PseudoVLOXSEG5EI8_V_MF8_MF2 + 10U, // PseudoVLOXSEG5EI8_V_MF8_MF2_MASK + 10U, // PseudoVLOXSEG5EI8_V_MF8_MF4 + 10U, // PseudoVLOXSEG5EI8_V_MF8_MF4_MASK + 10U, // PseudoVLOXSEG5EI8_V_MF8_MF8 + 10U, // PseudoVLOXSEG5EI8_V_MF8_MF8_MASK + 10U, // PseudoVLOXSEG6EI16_V_M1_M1 + 10U, // PseudoVLOXSEG6EI16_V_M1_M1_MASK + 10U, // PseudoVLOXSEG6EI16_V_M1_MF2 + 10U, // PseudoVLOXSEG6EI16_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG6EI16_V_M2_M1 + 10U, // PseudoVLOXSEG6EI16_V_M2_M1_MASK + 10U, // PseudoVLOXSEG6EI16_V_MF2_M1 + 10U, // PseudoVLOXSEG6EI16_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG6EI16_V_MF2_MF2 + 10U, // PseudoVLOXSEG6EI16_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG6EI16_V_MF2_MF4 + 10U, // PseudoVLOXSEG6EI16_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG6EI16_V_MF4_M1 + 10U, // PseudoVLOXSEG6EI16_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG6EI16_V_MF4_MF2 + 10U, // PseudoVLOXSEG6EI16_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG6EI16_V_MF4_MF4 + 10U, // PseudoVLOXSEG6EI16_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG6EI16_V_MF4_MF8 + 10U, // PseudoVLOXSEG6EI16_V_MF4_MF8_MASK + 10U, // PseudoVLOXSEG6EI32_V_M1_M1 + 10U, // PseudoVLOXSEG6EI32_V_M1_M1_MASK + 10U, // PseudoVLOXSEG6EI32_V_M1_MF2 + 10U, // PseudoVLOXSEG6EI32_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG6EI32_V_M1_MF4 + 10U, // PseudoVLOXSEG6EI32_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG6EI32_V_M2_M1 + 10U, // PseudoVLOXSEG6EI32_V_M2_M1_MASK + 10U, // PseudoVLOXSEG6EI32_V_M2_MF2 + 10U, // PseudoVLOXSEG6EI32_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG6EI32_V_M4_M1 + 10U, // PseudoVLOXSEG6EI32_V_M4_M1_MASK + 10U, // PseudoVLOXSEG6EI32_V_MF2_M1 + 10U, // PseudoVLOXSEG6EI32_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG6EI32_V_MF2_MF2 + 10U, // PseudoVLOXSEG6EI32_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG6EI32_V_MF2_MF4 + 10U, // PseudoVLOXSEG6EI32_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG6EI32_V_MF2_MF8 + 10U, // PseudoVLOXSEG6EI32_V_MF2_MF8_MASK + 10U, // PseudoVLOXSEG6EI64_V_M1_M1 + 10U, // PseudoVLOXSEG6EI64_V_M1_M1_MASK + 10U, // PseudoVLOXSEG6EI64_V_M1_MF2 + 10U, // PseudoVLOXSEG6EI64_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG6EI64_V_M1_MF4 + 10U, // PseudoVLOXSEG6EI64_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG6EI64_V_M1_MF8 + 10U, // PseudoVLOXSEG6EI64_V_M1_MF8_MASK + 10U, // PseudoVLOXSEG6EI64_V_M2_M1 + 10U, // PseudoVLOXSEG6EI64_V_M2_M1_MASK + 10U, // PseudoVLOXSEG6EI64_V_M2_MF2 + 10U, // PseudoVLOXSEG6EI64_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG6EI64_V_M2_MF4 + 10U, // PseudoVLOXSEG6EI64_V_M2_MF4_MASK + 10U, // PseudoVLOXSEG6EI64_V_M4_M1 + 10U, // PseudoVLOXSEG6EI64_V_M4_M1_MASK + 10U, // PseudoVLOXSEG6EI64_V_M4_MF2 + 10U, // PseudoVLOXSEG6EI64_V_M4_MF2_MASK + 10U, // PseudoVLOXSEG6EI64_V_M8_M1 + 10U, // PseudoVLOXSEG6EI64_V_M8_M1_MASK + 10U, // PseudoVLOXSEG6EI8_V_M1_M1 + 10U, // PseudoVLOXSEG6EI8_V_M1_M1_MASK + 10U, // PseudoVLOXSEG6EI8_V_MF2_M1 + 10U, // PseudoVLOXSEG6EI8_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG6EI8_V_MF2_MF2 + 10U, // PseudoVLOXSEG6EI8_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG6EI8_V_MF4_M1 + 10U, // PseudoVLOXSEG6EI8_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG6EI8_V_MF4_MF2 + 10U, // PseudoVLOXSEG6EI8_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG6EI8_V_MF4_MF4 + 10U, // PseudoVLOXSEG6EI8_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG6EI8_V_MF8_M1 + 10U, // PseudoVLOXSEG6EI8_V_MF8_M1_MASK + 10U, // PseudoVLOXSEG6EI8_V_MF8_MF2 + 10U, // PseudoVLOXSEG6EI8_V_MF8_MF2_MASK + 10U, // PseudoVLOXSEG6EI8_V_MF8_MF4 + 10U, // PseudoVLOXSEG6EI8_V_MF8_MF4_MASK + 10U, // PseudoVLOXSEG6EI8_V_MF8_MF8 + 10U, // PseudoVLOXSEG6EI8_V_MF8_MF8_MASK + 10U, // PseudoVLOXSEG7EI16_V_M1_M1 + 10U, // PseudoVLOXSEG7EI16_V_M1_M1_MASK + 10U, // PseudoVLOXSEG7EI16_V_M1_MF2 + 10U, // PseudoVLOXSEG7EI16_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG7EI16_V_M2_M1 + 10U, // PseudoVLOXSEG7EI16_V_M2_M1_MASK + 10U, // PseudoVLOXSEG7EI16_V_MF2_M1 + 10U, // PseudoVLOXSEG7EI16_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG7EI16_V_MF2_MF2 + 10U, // PseudoVLOXSEG7EI16_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG7EI16_V_MF2_MF4 + 10U, // PseudoVLOXSEG7EI16_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG7EI16_V_MF4_M1 + 10U, // PseudoVLOXSEG7EI16_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG7EI16_V_MF4_MF2 + 10U, // PseudoVLOXSEG7EI16_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG7EI16_V_MF4_MF4 + 10U, // PseudoVLOXSEG7EI16_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG7EI16_V_MF4_MF8 + 10U, // PseudoVLOXSEG7EI16_V_MF4_MF8_MASK + 10U, // PseudoVLOXSEG7EI32_V_M1_M1 + 10U, // PseudoVLOXSEG7EI32_V_M1_M1_MASK + 10U, // PseudoVLOXSEG7EI32_V_M1_MF2 + 10U, // PseudoVLOXSEG7EI32_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG7EI32_V_M1_MF4 + 10U, // PseudoVLOXSEG7EI32_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG7EI32_V_M2_M1 + 10U, // PseudoVLOXSEG7EI32_V_M2_M1_MASK + 10U, // PseudoVLOXSEG7EI32_V_M2_MF2 + 10U, // PseudoVLOXSEG7EI32_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG7EI32_V_M4_M1 + 10U, // PseudoVLOXSEG7EI32_V_M4_M1_MASK + 10U, // PseudoVLOXSEG7EI32_V_MF2_M1 + 10U, // PseudoVLOXSEG7EI32_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG7EI32_V_MF2_MF2 + 10U, // PseudoVLOXSEG7EI32_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG7EI32_V_MF2_MF4 + 10U, // PseudoVLOXSEG7EI32_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG7EI32_V_MF2_MF8 + 10U, // PseudoVLOXSEG7EI32_V_MF2_MF8_MASK + 10U, // PseudoVLOXSEG7EI64_V_M1_M1 + 10U, // PseudoVLOXSEG7EI64_V_M1_M1_MASK + 10U, // PseudoVLOXSEG7EI64_V_M1_MF2 + 10U, // PseudoVLOXSEG7EI64_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG7EI64_V_M1_MF4 + 10U, // PseudoVLOXSEG7EI64_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG7EI64_V_M1_MF8 + 10U, // PseudoVLOXSEG7EI64_V_M1_MF8_MASK + 10U, // PseudoVLOXSEG7EI64_V_M2_M1 + 10U, // PseudoVLOXSEG7EI64_V_M2_M1_MASK + 10U, // PseudoVLOXSEG7EI64_V_M2_MF2 + 10U, // PseudoVLOXSEG7EI64_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG7EI64_V_M2_MF4 + 10U, // PseudoVLOXSEG7EI64_V_M2_MF4_MASK + 10U, // PseudoVLOXSEG7EI64_V_M4_M1 + 10U, // PseudoVLOXSEG7EI64_V_M4_M1_MASK + 10U, // PseudoVLOXSEG7EI64_V_M4_MF2 + 10U, // PseudoVLOXSEG7EI64_V_M4_MF2_MASK + 10U, // PseudoVLOXSEG7EI64_V_M8_M1 + 10U, // PseudoVLOXSEG7EI64_V_M8_M1_MASK + 10U, // PseudoVLOXSEG7EI8_V_M1_M1 + 10U, // PseudoVLOXSEG7EI8_V_M1_M1_MASK + 10U, // PseudoVLOXSEG7EI8_V_MF2_M1 + 10U, // PseudoVLOXSEG7EI8_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG7EI8_V_MF2_MF2 + 10U, // PseudoVLOXSEG7EI8_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG7EI8_V_MF4_M1 + 10U, // PseudoVLOXSEG7EI8_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG7EI8_V_MF4_MF2 + 10U, // PseudoVLOXSEG7EI8_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG7EI8_V_MF4_MF4 + 10U, // PseudoVLOXSEG7EI8_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG7EI8_V_MF8_M1 + 10U, // PseudoVLOXSEG7EI8_V_MF8_M1_MASK + 10U, // PseudoVLOXSEG7EI8_V_MF8_MF2 + 10U, // PseudoVLOXSEG7EI8_V_MF8_MF2_MASK + 10U, // PseudoVLOXSEG7EI8_V_MF8_MF4 + 10U, // PseudoVLOXSEG7EI8_V_MF8_MF4_MASK + 10U, // PseudoVLOXSEG7EI8_V_MF8_MF8 + 10U, // PseudoVLOXSEG7EI8_V_MF8_MF8_MASK + 10U, // PseudoVLOXSEG8EI16_V_M1_M1 + 10U, // PseudoVLOXSEG8EI16_V_M1_M1_MASK + 10U, // PseudoVLOXSEG8EI16_V_M1_MF2 + 10U, // PseudoVLOXSEG8EI16_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG8EI16_V_M2_M1 + 10U, // PseudoVLOXSEG8EI16_V_M2_M1_MASK + 10U, // PseudoVLOXSEG8EI16_V_MF2_M1 + 10U, // PseudoVLOXSEG8EI16_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG8EI16_V_MF2_MF2 + 10U, // PseudoVLOXSEG8EI16_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG8EI16_V_MF2_MF4 + 10U, // PseudoVLOXSEG8EI16_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG8EI16_V_MF4_M1 + 10U, // PseudoVLOXSEG8EI16_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG8EI16_V_MF4_MF2 + 10U, // PseudoVLOXSEG8EI16_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG8EI16_V_MF4_MF4 + 10U, // PseudoVLOXSEG8EI16_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG8EI16_V_MF4_MF8 + 10U, // PseudoVLOXSEG8EI16_V_MF4_MF8_MASK + 10U, // PseudoVLOXSEG8EI32_V_M1_M1 + 10U, // PseudoVLOXSEG8EI32_V_M1_M1_MASK + 10U, // PseudoVLOXSEG8EI32_V_M1_MF2 + 10U, // PseudoVLOXSEG8EI32_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG8EI32_V_M1_MF4 + 10U, // PseudoVLOXSEG8EI32_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG8EI32_V_M2_M1 + 10U, // PseudoVLOXSEG8EI32_V_M2_M1_MASK + 10U, // PseudoVLOXSEG8EI32_V_M2_MF2 + 10U, // PseudoVLOXSEG8EI32_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG8EI32_V_M4_M1 + 10U, // PseudoVLOXSEG8EI32_V_M4_M1_MASK + 10U, // PseudoVLOXSEG8EI32_V_MF2_M1 + 10U, // PseudoVLOXSEG8EI32_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG8EI32_V_MF2_MF2 + 10U, // PseudoVLOXSEG8EI32_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG8EI32_V_MF2_MF4 + 10U, // PseudoVLOXSEG8EI32_V_MF2_MF4_MASK + 10U, // PseudoVLOXSEG8EI32_V_MF2_MF8 + 10U, // PseudoVLOXSEG8EI32_V_MF2_MF8_MASK + 10U, // PseudoVLOXSEG8EI64_V_M1_M1 + 10U, // PseudoVLOXSEG8EI64_V_M1_M1_MASK + 10U, // PseudoVLOXSEG8EI64_V_M1_MF2 + 10U, // PseudoVLOXSEG8EI64_V_M1_MF2_MASK + 10U, // PseudoVLOXSEG8EI64_V_M1_MF4 + 10U, // PseudoVLOXSEG8EI64_V_M1_MF4_MASK + 10U, // PseudoVLOXSEG8EI64_V_M1_MF8 + 10U, // PseudoVLOXSEG8EI64_V_M1_MF8_MASK + 10U, // PseudoVLOXSEG8EI64_V_M2_M1 + 10U, // PseudoVLOXSEG8EI64_V_M2_M1_MASK + 10U, // PseudoVLOXSEG8EI64_V_M2_MF2 + 10U, // PseudoVLOXSEG8EI64_V_M2_MF2_MASK + 10U, // PseudoVLOXSEG8EI64_V_M2_MF4 + 10U, // PseudoVLOXSEG8EI64_V_M2_MF4_MASK + 10U, // PseudoVLOXSEG8EI64_V_M4_M1 + 10U, // PseudoVLOXSEG8EI64_V_M4_M1_MASK + 10U, // PseudoVLOXSEG8EI64_V_M4_MF2 + 10U, // PseudoVLOXSEG8EI64_V_M4_MF2_MASK + 10U, // PseudoVLOXSEG8EI64_V_M8_M1 + 10U, // PseudoVLOXSEG8EI64_V_M8_M1_MASK + 10U, // PseudoVLOXSEG8EI8_V_M1_M1 + 10U, // PseudoVLOXSEG8EI8_V_M1_M1_MASK + 10U, // PseudoVLOXSEG8EI8_V_MF2_M1 + 10U, // PseudoVLOXSEG8EI8_V_MF2_M1_MASK + 10U, // PseudoVLOXSEG8EI8_V_MF2_MF2 + 10U, // PseudoVLOXSEG8EI8_V_MF2_MF2_MASK + 10U, // PseudoVLOXSEG8EI8_V_MF4_M1 + 10U, // PseudoVLOXSEG8EI8_V_MF4_M1_MASK + 10U, // PseudoVLOXSEG8EI8_V_MF4_MF2 + 10U, // PseudoVLOXSEG8EI8_V_MF4_MF2_MASK + 10U, // PseudoVLOXSEG8EI8_V_MF4_MF4 + 10U, // PseudoVLOXSEG8EI8_V_MF4_MF4_MASK + 10U, // PseudoVLOXSEG8EI8_V_MF8_M1 + 10U, // PseudoVLOXSEG8EI8_V_MF8_M1_MASK + 10U, // PseudoVLOXSEG8EI8_V_MF8_MF2 + 10U, // PseudoVLOXSEG8EI8_V_MF8_MF2_MASK + 10U, // PseudoVLOXSEG8EI8_V_MF8_MF4 + 10U, // PseudoVLOXSEG8EI8_V_MF8_MF4_MASK + 10U, // PseudoVLOXSEG8EI8_V_MF8_MF8 + 10U, // PseudoVLOXSEG8EI8_V_MF8_MF8_MASK + 10U, // PseudoVLSE16_V_M1 + 10U, // PseudoVLSE16_V_M1_MASK + 10U, // PseudoVLSE16_V_M2 + 10U, // PseudoVLSE16_V_M2_MASK + 10U, // PseudoVLSE16_V_M4 + 10U, // PseudoVLSE16_V_M4_MASK + 10U, // PseudoVLSE16_V_M8 + 10U, // PseudoVLSE16_V_M8_MASK + 10U, // PseudoVLSE16_V_MF2 + 10U, // PseudoVLSE16_V_MF2_MASK + 10U, // PseudoVLSE16_V_MF4 + 10U, // PseudoVLSE16_V_MF4_MASK + 10U, // PseudoVLSE32_V_M1 + 10U, // PseudoVLSE32_V_M1_MASK + 10U, // PseudoVLSE32_V_M2 + 10U, // PseudoVLSE32_V_M2_MASK + 10U, // PseudoVLSE32_V_M4 + 10U, // PseudoVLSE32_V_M4_MASK + 10U, // PseudoVLSE32_V_M8 + 10U, // PseudoVLSE32_V_M8_MASK + 10U, // PseudoVLSE32_V_MF2 + 10U, // PseudoVLSE32_V_MF2_MASK + 10U, // PseudoVLSE64_V_M1 + 10U, // PseudoVLSE64_V_M1_MASK + 10U, // PseudoVLSE64_V_M2 + 10U, // PseudoVLSE64_V_M2_MASK + 10U, // PseudoVLSE64_V_M4 + 10U, // PseudoVLSE64_V_M4_MASK + 10U, // PseudoVLSE64_V_M8 + 10U, // PseudoVLSE64_V_M8_MASK + 10U, // PseudoVLSE8_V_M1 + 10U, // PseudoVLSE8_V_M1_MASK + 10U, // PseudoVLSE8_V_M2 + 10U, // PseudoVLSE8_V_M2_MASK + 10U, // PseudoVLSE8_V_M4 + 10U, // PseudoVLSE8_V_M4_MASK + 10U, // PseudoVLSE8_V_M8 + 10U, // PseudoVLSE8_V_M8_MASK + 10U, // PseudoVLSE8_V_MF2 + 10U, // PseudoVLSE8_V_MF2_MASK + 10U, // PseudoVLSE8_V_MF4 + 10U, // PseudoVLSE8_V_MF4_MASK + 10U, // PseudoVLSE8_V_MF8 + 10U, // PseudoVLSE8_V_MF8_MASK + 10U, // PseudoVLSEG2E16FF_V_M1 + 10U, // PseudoVLSEG2E16FF_V_M1_MASK + 10U, // PseudoVLSEG2E16FF_V_M2 + 10U, // PseudoVLSEG2E16FF_V_M2_MASK + 10U, // PseudoVLSEG2E16FF_V_M4 + 10U, // PseudoVLSEG2E16FF_V_M4_MASK + 10U, // PseudoVLSEG2E16FF_V_MF2 + 10U, // PseudoVLSEG2E16FF_V_MF2_MASK + 10U, // PseudoVLSEG2E16FF_V_MF4 + 10U, // PseudoVLSEG2E16FF_V_MF4_MASK + 10U, // PseudoVLSEG2E16_V_M1 + 10U, // PseudoVLSEG2E16_V_M1_MASK + 10U, // PseudoVLSEG2E16_V_M2 + 10U, // PseudoVLSEG2E16_V_M2_MASK + 10U, // PseudoVLSEG2E16_V_M4 + 10U, // PseudoVLSEG2E16_V_M4_MASK + 10U, // PseudoVLSEG2E16_V_MF2 + 10U, // PseudoVLSEG2E16_V_MF2_MASK + 10U, // PseudoVLSEG2E16_V_MF4 + 10U, // PseudoVLSEG2E16_V_MF4_MASK + 10U, // PseudoVLSEG2E32FF_V_M1 + 10U, // PseudoVLSEG2E32FF_V_M1_MASK + 10U, // PseudoVLSEG2E32FF_V_M2 + 10U, // PseudoVLSEG2E32FF_V_M2_MASK + 10U, // PseudoVLSEG2E32FF_V_M4 + 10U, // PseudoVLSEG2E32FF_V_M4_MASK + 10U, // PseudoVLSEG2E32FF_V_MF2 + 10U, // PseudoVLSEG2E32FF_V_MF2_MASK + 10U, // PseudoVLSEG2E32_V_M1 + 10U, // PseudoVLSEG2E32_V_M1_MASK + 10U, // PseudoVLSEG2E32_V_M2 + 10U, // PseudoVLSEG2E32_V_M2_MASK + 10U, // PseudoVLSEG2E32_V_M4 + 10U, // PseudoVLSEG2E32_V_M4_MASK + 10U, // PseudoVLSEG2E32_V_MF2 + 10U, // PseudoVLSEG2E32_V_MF2_MASK + 10U, // PseudoVLSEG2E64FF_V_M1 + 10U, // PseudoVLSEG2E64FF_V_M1_MASK + 10U, // PseudoVLSEG2E64FF_V_M2 + 10U, // PseudoVLSEG2E64FF_V_M2_MASK + 10U, // PseudoVLSEG2E64FF_V_M4 + 10U, // PseudoVLSEG2E64FF_V_M4_MASK + 10U, // PseudoVLSEG2E64_V_M1 + 10U, // PseudoVLSEG2E64_V_M1_MASK + 10U, // PseudoVLSEG2E64_V_M2 + 10U, // PseudoVLSEG2E64_V_M2_MASK + 10U, // PseudoVLSEG2E64_V_M4 + 10U, // PseudoVLSEG2E64_V_M4_MASK + 10U, // PseudoVLSEG2E8FF_V_M1 + 10U, // PseudoVLSEG2E8FF_V_M1_MASK + 10U, // PseudoVLSEG2E8FF_V_M2 + 10U, // PseudoVLSEG2E8FF_V_M2_MASK + 10U, // PseudoVLSEG2E8FF_V_M4 + 10U, // PseudoVLSEG2E8FF_V_M4_MASK + 10U, // PseudoVLSEG2E8FF_V_MF2 + 10U, // PseudoVLSEG2E8FF_V_MF2_MASK + 10U, // PseudoVLSEG2E8FF_V_MF4 + 10U, // PseudoVLSEG2E8FF_V_MF4_MASK + 10U, // PseudoVLSEG2E8FF_V_MF8 + 10U, // PseudoVLSEG2E8FF_V_MF8_MASK + 10U, // PseudoVLSEG2E8_V_M1 + 10U, // PseudoVLSEG2E8_V_M1_MASK + 10U, // PseudoVLSEG2E8_V_M2 + 10U, // PseudoVLSEG2E8_V_M2_MASK + 10U, // PseudoVLSEG2E8_V_M4 + 10U, // PseudoVLSEG2E8_V_M4_MASK + 10U, // PseudoVLSEG2E8_V_MF2 + 10U, // PseudoVLSEG2E8_V_MF2_MASK + 10U, // PseudoVLSEG2E8_V_MF4 + 10U, // PseudoVLSEG2E8_V_MF4_MASK + 10U, // PseudoVLSEG2E8_V_MF8 + 10U, // PseudoVLSEG2E8_V_MF8_MASK + 10U, // PseudoVLSEG3E16FF_V_M1 + 10U, // PseudoVLSEG3E16FF_V_M1_MASK + 10U, // PseudoVLSEG3E16FF_V_M2 + 10U, // PseudoVLSEG3E16FF_V_M2_MASK + 10U, // PseudoVLSEG3E16FF_V_MF2 + 10U, // PseudoVLSEG3E16FF_V_MF2_MASK + 10U, // PseudoVLSEG3E16FF_V_MF4 + 10U, // PseudoVLSEG3E16FF_V_MF4_MASK + 10U, // PseudoVLSEG3E16_V_M1 + 10U, // PseudoVLSEG3E16_V_M1_MASK + 10U, // PseudoVLSEG3E16_V_M2 + 10U, // PseudoVLSEG3E16_V_M2_MASK + 10U, // PseudoVLSEG3E16_V_MF2 + 10U, // PseudoVLSEG3E16_V_MF2_MASK + 10U, // PseudoVLSEG3E16_V_MF4 + 10U, // PseudoVLSEG3E16_V_MF4_MASK + 10U, // PseudoVLSEG3E32FF_V_M1 + 10U, // PseudoVLSEG3E32FF_V_M1_MASK + 10U, // PseudoVLSEG3E32FF_V_M2 + 10U, // PseudoVLSEG3E32FF_V_M2_MASK + 10U, // PseudoVLSEG3E32FF_V_MF2 + 10U, // PseudoVLSEG3E32FF_V_MF2_MASK + 10U, // PseudoVLSEG3E32_V_M1 + 10U, // PseudoVLSEG3E32_V_M1_MASK + 10U, // PseudoVLSEG3E32_V_M2 + 10U, // PseudoVLSEG3E32_V_M2_MASK + 10U, // PseudoVLSEG3E32_V_MF2 + 10U, // PseudoVLSEG3E32_V_MF2_MASK + 10U, // PseudoVLSEG3E64FF_V_M1 + 10U, // PseudoVLSEG3E64FF_V_M1_MASK + 10U, // PseudoVLSEG3E64FF_V_M2 + 10U, // PseudoVLSEG3E64FF_V_M2_MASK + 10U, // PseudoVLSEG3E64_V_M1 + 10U, // PseudoVLSEG3E64_V_M1_MASK + 10U, // PseudoVLSEG3E64_V_M2 + 10U, // PseudoVLSEG3E64_V_M2_MASK + 10U, // PseudoVLSEG3E8FF_V_M1 + 10U, // PseudoVLSEG3E8FF_V_M1_MASK + 10U, // PseudoVLSEG3E8FF_V_M2 + 10U, // PseudoVLSEG3E8FF_V_M2_MASK + 10U, // PseudoVLSEG3E8FF_V_MF2 + 10U, // PseudoVLSEG3E8FF_V_MF2_MASK + 10U, // PseudoVLSEG3E8FF_V_MF4 + 10U, // PseudoVLSEG3E8FF_V_MF4_MASK + 10U, // PseudoVLSEG3E8FF_V_MF8 + 10U, // PseudoVLSEG3E8FF_V_MF8_MASK + 10U, // PseudoVLSEG3E8_V_M1 + 10U, // PseudoVLSEG3E8_V_M1_MASK + 10U, // PseudoVLSEG3E8_V_M2 + 10U, // PseudoVLSEG3E8_V_M2_MASK + 10U, // PseudoVLSEG3E8_V_MF2 + 10U, // PseudoVLSEG3E8_V_MF2_MASK + 10U, // PseudoVLSEG3E8_V_MF4 + 10U, // PseudoVLSEG3E8_V_MF4_MASK + 10U, // PseudoVLSEG3E8_V_MF8 + 10U, // PseudoVLSEG3E8_V_MF8_MASK + 10U, // PseudoVLSEG4E16FF_V_M1 + 10U, // PseudoVLSEG4E16FF_V_M1_MASK + 10U, // PseudoVLSEG4E16FF_V_M2 + 10U, // PseudoVLSEG4E16FF_V_M2_MASK + 10U, // PseudoVLSEG4E16FF_V_MF2 + 10U, // PseudoVLSEG4E16FF_V_MF2_MASK + 10U, // PseudoVLSEG4E16FF_V_MF4 + 10U, // PseudoVLSEG4E16FF_V_MF4_MASK + 10U, // PseudoVLSEG4E16_V_M1 + 10U, // PseudoVLSEG4E16_V_M1_MASK + 10U, // PseudoVLSEG4E16_V_M2 + 10U, // PseudoVLSEG4E16_V_M2_MASK + 10U, // PseudoVLSEG4E16_V_MF2 + 10U, // PseudoVLSEG4E16_V_MF2_MASK + 10U, // PseudoVLSEG4E16_V_MF4 + 10U, // PseudoVLSEG4E16_V_MF4_MASK + 10U, // PseudoVLSEG4E32FF_V_M1 + 10U, // PseudoVLSEG4E32FF_V_M1_MASK + 10U, // PseudoVLSEG4E32FF_V_M2 + 10U, // PseudoVLSEG4E32FF_V_M2_MASK + 10U, // PseudoVLSEG4E32FF_V_MF2 + 10U, // PseudoVLSEG4E32FF_V_MF2_MASK + 10U, // PseudoVLSEG4E32_V_M1 + 10U, // PseudoVLSEG4E32_V_M1_MASK + 10U, // PseudoVLSEG4E32_V_M2 + 10U, // PseudoVLSEG4E32_V_M2_MASK + 10U, // PseudoVLSEG4E32_V_MF2 + 10U, // PseudoVLSEG4E32_V_MF2_MASK + 10U, // PseudoVLSEG4E64FF_V_M1 + 10U, // PseudoVLSEG4E64FF_V_M1_MASK + 10U, // PseudoVLSEG4E64FF_V_M2 + 10U, // PseudoVLSEG4E64FF_V_M2_MASK + 10U, // PseudoVLSEG4E64_V_M1 + 10U, // PseudoVLSEG4E64_V_M1_MASK + 10U, // PseudoVLSEG4E64_V_M2 + 10U, // PseudoVLSEG4E64_V_M2_MASK + 10U, // PseudoVLSEG4E8FF_V_M1 + 10U, // PseudoVLSEG4E8FF_V_M1_MASK + 10U, // PseudoVLSEG4E8FF_V_M2 + 10U, // PseudoVLSEG4E8FF_V_M2_MASK + 10U, // PseudoVLSEG4E8FF_V_MF2 + 10U, // PseudoVLSEG4E8FF_V_MF2_MASK + 10U, // PseudoVLSEG4E8FF_V_MF4 + 10U, // PseudoVLSEG4E8FF_V_MF4_MASK + 10U, // PseudoVLSEG4E8FF_V_MF8 + 10U, // PseudoVLSEG4E8FF_V_MF8_MASK + 10U, // PseudoVLSEG4E8_V_M1 + 10U, // PseudoVLSEG4E8_V_M1_MASK + 10U, // PseudoVLSEG4E8_V_M2 + 10U, // PseudoVLSEG4E8_V_M2_MASK + 10U, // PseudoVLSEG4E8_V_MF2 + 10U, // PseudoVLSEG4E8_V_MF2_MASK + 10U, // PseudoVLSEG4E8_V_MF4 + 10U, // PseudoVLSEG4E8_V_MF4_MASK + 10U, // PseudoVLSEG4E8_V_MF8 + 10U, // PseudoVLSEG4E8_V_MF8_MASK + 10U, // PseudoVLSEG5E16FF_V_M1 + 10U, // PseudoVLSEG5E16FF_V_M1_MASK + 10U, // PseudoVLSEG5E16FF_V_MF2 + 10U, // PseudoVLSEG5E16FF_V_MF2_MASK + 10U, // PseudoVLSEG5E16FF_V_MF4 + 10U, // PseudoVLSEG5E16FF_V_MF4_MASK + 10U, // PseudoVLSEG5E16_V_M1 + 10U, // PseudoVLSEG5E16_V_M1_MASK + 10U, // PseudoVLSEG5E16_V_MF2 + 10U, // PseudoVLSEG5E16_V_MF2_MASK + 10U, // PseudoVLSEG5E16_V_MF4 + 10U, // PseudoVLSEG5E16_V_MF4_MASK + 10U, // PseudoVLSEG5E32FF_V_M1 + 10U, // PseudoVLSEG5E32FF_V_M1_MASK + 10U, // PseudoVLSEG5E32FF_V_MF2 + 10U, // PseudoVLSEG5E32FF_V_MF2_MASK + 10U, // PseudoVLSEG5E32_V_M1 + 10U, // PseudoVLSEG5E32_V_M1_MASK + 10U, // PseudoVLSEG5E32_V_MF2 + 10U, // PseudoVLSEG5E32_V_MF2_MASK + 10U, // PseudoVLSEG5E64FF_V_M1 + 10U, // PseudoVLSEG5E64FF_V_M1_MASK + 10U, // PseudoVLSEG5E64_V_M1 + 10U, // PseudoVLSEG5E64_V_M1_MASK + 10U, // PseudoVLSEG5E8FF_V_M1 + 10U, // PseudoVLSEG5E8FF_V_M1_MASK + 10U, // PseudoVLSEG5E8FF_V_MF2 + 10U, // PseudoVLSEG5E8FF_V_MF2_MASK + 10U, // PseudoVLSEG5E8FF_V_MF4 + 10U, // PseudoVLSEG5E8FF_V_MF4_MASK + 10U, // PseudoVLSEG5E8FF_V_MF8 + 10U, // PseudoVLSEG5E8FF_V_MF8_MASK + 10U, // PseudoVLSEG5E8_V_M1 + 10U, // PseudoVLSEG5E8_V_M1_MASK + 10U, // PseudoVLSEG5E8_V_MF2 + 10U, // PseudoVLSEG5E8_V_MF2_MASK + 10U, // PseudoVLSEG5E8_V_MF4 + 10U, // PseudoVLSEG5E8_V_MF4_MASK + 10U, // PseudoVLSEG5E8_V_MF8 + 10U, // PseudoVLSEG5E8_V_MF8_MASK + 10U, // PseudoVLSEG6E16FF_V_M1 + 10U, // PseudoVLSEG6E16FF_V_M1_MASK + 10U, // PseudoVLSEG6E16FF_V_MF2 + 10U, // PseudoVLSEG6E16FF_V_MF2_MASK + 10U, // PseudoVLSEG6E16FF_V_MF4 + 10U, // PseudoVLSEG6E16FF_V_MF4_MASK + 10U, // PseudoVLSEG6E16_V_M1 + 10U, // PseudoVLSEG6E16_V_M1_MASK + 10U, // PseudoVLSEG6E16_V_MF2 + 10U, // PseudoVLSEG6E16_V_MF2_MASK + 10U, // PseudoVLSEG6E16_V_MF4 + 10U, // PseudoVLSEG6E16_V_MF4_MASK + 10U, // PseudoVLSEG6E32FF_V_M1 + 10U, // PseudoVLSEG6E32FF_V_M1_MASK + 10U, // PseudoVLSEG6E32FF_V_MF2 + 10U, // PseudoVLSEG6E32FF_V_MF2_MASK + 10U, // PseudoVLSEG6E32_V_M1 + 10U, // PseudoVLSEG6E32_V_M1_MASK + 10U, // PseudoVLSEG6E32_V_MF2 + 10U, // PseudoVLSEG6E32_V_MF2_MASK + 10U, // PseudoVLSEG6E64FF_V_M1 + 10U, // PseudoVLSEG6E64FF_V_M1_MASK + 10U, // PseudoVLSEG6E64_V_M1 + 10U, // PseudoVLSEG6E64_V_M1_MASK + 10U, // PseudoVLSEG6E8FF_V_M1 + 10U, // PseudoVLSEG6E8FF_V_M1_MASK + 10U, // PseudoVLSEG6E8FF_V_MF2 + 10U, // PseudoVLSEG6E8FF_V_MF2_MASK + 10U, // PseudoVLSEG6E8FF_V_MF4 + 10U, // PseudoVLSEG6E8FF_V_MF4_MASK + 10U, // PseudoVLSEG6E8FF_V_MF8 + 10U, // PseudoVLSEG6E8FF_V_MF8_MASK + 10U, // PseudoVLSEG6E8_V_M1 + 10U, // PseudoVLSEG6E8_V_M1_MASK + 10U, // PseudoVLSEG6E8_V_MF2 + 10U, // PseudoVLSEG6E8_V_MF2_MASK + 10U, // PseudoVLSEG6E8_V_MF4 + 10U, // PseudoVLSEG6E8_V_MF4_MASK + 10U, // PseudoVLSEG6E8_V_MF8 + 10U, // PseudoVLSEG6E8_V_MF8_MASK + 10U, // PseudoVLSEG7E16FF_V_M1 + 10U, // PseudoVLSEG7E16FF_V_M1_MASK + 10U, // PseudoVLSEG7E16FF_V_MF2 + 10U, // PseudoVLSEG7E16FF_V_MF2_MASK + 10U, // PseudoVLSEG7E16FF_V_MF4 + 10U, // PseudoVLSEG7E16FF_V_MF4_MASK + 10U, // PseudoVLSEG7E16_V_M1 + 10U, // PseudoVLSEG7E16_V_M1_MASK + 10U, // PseudoVLSEG7E16_V_MF2 + 10U, // PseudoVLSEG7E16_V_MF2_MASK + 10U, // PseudoVLSEG7E16_V_MF4 + 10U, // PseudoVLSEG7E16_V_MF4_MASK + 10U, // PseudoVLSEG7E32FF_V_M1 + 10U, // PseudoVLSEG7E32FF_V_M1_MASK + 10U, // PseudoVLSEG7E32FF_V_MF2 + 10U, // PseudoVLSEG7E32FF_V_MF2_MASK + 10U, // PseudoVLSEG7E32_V_M1 + 10U, // PseudoVLSEG7E32_V_M1_MASK + 10U, // PseudoVLSEG7E32_V_MF2 + 10U, // PseudoVLSEG7E32_V_MF2_MASK + 10U, // PseudoVLSEG7E64FF_V_M1 + 10U, // PseudoVLSEG7E64FF_V_M1_MASK + 10U, // PseudoVLSEG7E64_V_M1 + 10U, // PseudoVLSEG7E64_V_M1_MASK + 10U, // PseudoVLSEG7E8FF_V_M1 + 10U, // PseudoVLSEG7E8FF_V_M1_MASK + 10U, // PseudoVLSEG7E8FF_V_MF2 + 10U, // PseudoVLSEG7E8FF_V_MF2_MASK + 10U, // PseudoVLSEG7E8FF_V_MF4 + 10U, // PseudoVLSEG7E8FF_V_MF4_MASK + 10U, // PseudoVLSEG7E8FF_V_MF8 + 10U, // PseudoVLSEG7E8FF_V_MF8_MASK + 10U, // PseudoVLSEG7E8_V_M1 + 10U, // PseudoVLSEG7E8_V_M1_MASK + 10U, // PseudoVLSEG7E8_V_MF2 + 10U, // PseudoVLSEG7E8_V_MF2_MASK + 10U, // PseudoVLSEG7E8_V_MF4 + 10U, // PseudoVLSEG7E8_V_MF4_MASK + 10U, // PseudoVLSEG7E8_V_MF8 + 10U, // PseudoVLSEG7E8_V_MF8_MASK + 10U, // PseudoVLSEG8E16FF_V_M1 + 10U, // PseudoVLSEG8E16FF_V_M1_MASK + 10U, // PseudoVLSEG8E16FF_V_MF2 + 10U, // PseudoVLSEG8E16FF_V_MF2_MASK + 10U, // PseudoVLSEG8E16FF_V_MF4 + 10U, // PseudoVLSEG8E16FF_V_MF4_MASK + 10U, // PseudoVLSEG8E16_V_M1 + 10U, // PseudoVLSEG8E16_V_M1_MASK + 10U, // PseudoVLSEG8E16_V_MF2 + 10U, // PseudoVLSEG8E16_V_MF2_MASK + 10U, // PseudoVLSEG8E16_V_MF4 + 10U, // PseudoVLSEG8E16_V_MF4_MASK + 10U, // PseudoVLSEG8E32FF_V_M1 + 10U, // PseudoVLSEG8E32FF_V_M1_MASK + 10U, // PseudoVLSEG8E32FF_V_MF2 + 10U, // PseudoVLSEG8E32FF_V_MF2_MASK + 10U, // PseudoVLSEG8E32_V_M1 + 10U, // PseudoVLSEG8E32_V_M1_MASK + 10U, // PseudoVLSEG8E32_V_MF2 + 10U, // PseudoVLSEG8E32_V_MF2_MASK + 10U, // PseudoVLSEG8E64FF_V_M1 + 10U, // PseudoVLSEG8E64FF_V_M1_MASK + 10U, // PseudoVLSEG8E64_V_M1 + 10U, // PseudoVLSEG8E64_V_M1_MASK + 10U, // PseudoVLSEG8E8FF_V_M1 + 10U, // PseudoVLSEG8E8FF_V_M1_MASK + 10U, // PseudoVLSEG8E8FF_V_MF2 + 10U, // PseudoVLSEG8E8FF_V_MF2_MASK + 10U, // PseudoVLSEG8E8FF_V_MF4 + 10U, // PseudoVLSEG8E8FF_V_MF4_MASK + 10U, // PseudoVLSEG8E8FF_V_MF8 + 10U, // PseudoVLSEG8E8FF_V_MF8_MASK + 10U, // PseudoVLSEG8E8_V_M1 + 10U, // PseudoVLSEG8E8_V_M1_MASK + 10U, // PseudoVLSEG8E8_V_MF2 + 10U, // PseudoVLSEG8E8_V_MF2_MASK + 10U, // PseudoVLSEG8E8_V_MF4 + 10U, // PseudoVLSEG8E8_V_MF4_MASK + 10U, // PseudoVLSEG8E8_V_MF8 + 10U, // PseudoVLSEG8E8_V_MF8_MASK + 10U, // PseudoVLSSEG2E16_V_M1 + 10U, // PseudoVLSSEG2E16_V_M1_MASK + 10U, // PseudoVLSSEG2E16_V_M2 + 10U, // PseudoVLSSEG2E16_V_M2_MASK + 10U, // PseudoVLSSEG2E16_V_M4 + 10U, // PseudoVLSSEG2E16_V_M4_MASK + 10U, // PseudoVLSSEG2E16_V_MF2 + 10U, // PseudoVLSSEG2E16_V_MF2_MASK + 10U, // PseudoVLSSEG2E16_V_MF4 + 10U, // PseudoVLSSEG2E16_V_MF4_MASK + 10U, // PseudoVLSSEG2E32_V_M1 + 10U, // PseudoVLSSEG2E32_V_M1_MASK + 10U, // PseudoVLSSEG2E32_V_M2 + 10U, // PseudoVLSSEG2E32_V_M2_MASK + 10U, // PseudoVLSSEG2E32_V_M4 + 10U, // PseudoVLSSEG2E32_V_M4_MASK + 10U, // PseudoVLSSEG2E32_V_MF2 + 10U, // PseudoVLSSEG2E32_V_MF2_MASK + 10U, // PseudoVLSSEG2E64_V_M1 + 10U, // PseudoVLSSEG2E64_V_M1_MASK + 10U, // PseudoVLSSEG2E64_V_M2 + 10U, // PseudoVLSSEG2E64_V_M2_MASK + 10U, // PseudoVLSSEG2E64_V_M4 + 10U, // PseudoVLSSEG2E64_V_M4_MASK + 10U, // PseudoVLSSEG2E8_V_M1 + 10U, // PseudoVLSSEG2E8_V_M1_MASK + 10U, // PseudoVLSSEG2E8_V_M2 + 10U, // PseudoVLSSEG2E8_V_M2_MASK + 10U, // PseudoVLSSEG2E8_V_M4 + 10U, // PseudoVLSSEG2E8_V_M4_MASK + 10U, // PseudoVLSSEG2E8_V_MF2 + 10U, // PseudoVLSSEG2E8_V_MF2_MASK + 10U, // PseudoVLSSEG2E8_V_MF4 + 10U, // PseudoVLSSEG2E8_V_MF4_MASK + 10U, // PseudoVLSSEG2E8_V_MF8 + 10U, // PseudoVLSSEG2E8_V_MF8_MASK + 10U, // PseudoVLSSEG3E16_V_M1 + 10U, // PseudoVLSSEG3E16_V_M1_MASK + 10U, // PseudoVLSSEG3E16_V_M2 + 10U, // PseudoVLSSEG3E16_V_M2_MASK + 10U, // PseudoVLSSEG3E16_V_MF2 + 10U, // PseudoVLSSEG3E16_V_MF2_MASK + 10U, // PseudoVLSSEG3E16_V_MF4 + 10U, // PseudoVLSSEG3E16_V_MF4_MASK + 10U, // PseudoVLSSEG3E32_V_M1 + 10U, // PseudoVLSSEG3E32_V_M1_MASK + 10U, // PseudoVLSSEG3E32_V_M2 + 10U, // PseudoVLSSEG3E32_V_M2_MASK + 10U, // PseudoVLSSEG3E32_V_MF2 + 10U, // PseudoVLSSEG3E32_V_MF2_MASK + 10U, // PseudoVLSSEG3E64_V_M1 + 10U, // PseudoVLSSEG3E64_V_M1_MASK + 10U, // PseudoVLSSEG3E64_V_M2 + 10U, // PseudoVLSSEG3E64_V_M2_MASK + 10U, // PseudoVLSSEG3E8_V_M1 + 10U, // PseudoVLSSEG3E8_V_M1_MASK + 10U, // PseudoVLSSEG3E8_V_M2 + 10U, // PseudoVLSSEG3E8_V_M2_MASK + 10U, // PseudoVLSSEG3E8_V_MF2 + 10U, // PseudoVLSSEG3E8_V_MF2_MASK + 10U, // PseudoVLSSEG3E8_V_MF4 + 10U, // PseudoVLSSEG3E8_V_MF4_MASK + 10U, // PseudoVLSSEG3E8_V_MF8 + 10U, // PseudoVLSSEG3E8_V_MF8_MASK + 10U, // PseudoVLSSEG4E16_V_M1 + 10U, // PseudoVLSSEG4E16_V_M1_MASK + 10U, // PseudoVLSSEG4E16_V_M2 + 10U, // PseudoVLSSEG4E16_V_M2_MASK + 10U, // PseudoVLSSEG4E16_V_MF2 + 10U, // PseudoVLSSEG4E16_V_MF2_MASK + 10U, // PseudoVLSSEG4E16_V_MF4 + 10U, // PseudoVLSSEG4E16_V_MF4_MASK + 10U, // PseudoVLSSEG4E32_V_M1 + 10U, // PseudoVLSSEG4E32_V_M1_MASK + 10U, // PseudoVLSSEG4E32_V_M2 + 10U, // PseudoVLSSEG4E32_V_M2_MASK + 10U, // PseudoVLSSEG4E32_V_MF2 + 10U, // PseudoVLSSEG4E32_V_MF2_MASK + 10U, // PseudoVLSSEG4E64_V_M1 + 10U, // PseudoVLSSEG4E64_V_M1_MASK + 10U, // PseudoVLSSEG4E64_V_M2 + 10U, // PseudoVLSSEG4E64_V_M2_MASK + 10U, // PseudoVLSSEG4E8_V_M1 + 10U, // PseudoVLSSEG4E8_V_M1_MASK + 10U, // PseudoVLSSEG4E8_V_M2 + 10U, // PseudoVLSSEG4E8_V_M2_MASK + 10U, // PseudoVLSSEG4E8_V_MF2 + 10U, // PseudoVLSSEG4E8_V_MF2_MASK + 10U, // PseudoVLSSEG4E8_V_MF4 + 10U, // PseudoVLSSEG4E8_V_MF4_MASK + 10U, // PseudoVLSSEG4E8_V_MF8 + 10U, // PseudoVLSSEG4E8_V_MF8_MASK + 10U, // PseudoVLSSEG5E16_V_M1 + 10U, // PseudoVLSSEG5E16_V_M1_MASK + 10U, // PseudoVLSSEG5E16_V_MF2 + 10U, // PseudoVLSSEG5E16_V_MF2_MASK + 10U, // PseudoVLSSEG5E16_V_MF4 + 10U, // PseudoVLSSEG5E16_V_MF4_MASK + 10U, // PseudoVLSSEG5E32_V_M1 + 10U, // PseudoVLSSEG5E32_V_M1_MASK + 10U, // PseudoVLSSEG5E32_V_MF2 + 10U, // PseudoVLSSEG5E32_V_MF2_MASK + 10U, // PseudoVLSSEG5E64_V_M1 + 10U, // PseudoVLSSEG5E64_V_M1_MASK + 10U, // PseudoVLSSEG5E8_V_M1 + 10U, // PseudoVLSSEG5E8_V_M1_MASK + 10U, // PseudoVLSSEG5E8_V_MF2 + 10U, // PseudoVLSSEG5E8_V_MF2_MASK + 10U, // PseudoVLSSEG5E8_V_MF4 + 10U, // PseudoVLSSEG5E8_V_MF4_MASK + 10U, // PseudoVLSSEG5E8_V_MF8 + 10U, // PseudoVLSSEG5E8_V_MF8_MASK + 10U, // PseudoVLSSEG6E16_V_M1 + 10U, // PseudoVLSSEG6E16_V_M1_MASK + 10U, // PseudoVLSSEG6E16_V_MF2 + 10U, // PseudoVLSSEG6E16_V_MF2_MASK + 10U, // PseudoVLSSEG6E16_V_MF4 + 10U, // PseudoVLSSEG6E16_V_MF4_MASK + 10U, // PseudoVLSSEG6E32_V_M1 + 10U, // PseudoVLSSEG6E32_V_M1_MASK + 10U, // PseudoVLSSEG6E32_V_MF2 + 10U, // PseudoVLSSEG6E32_V_MF2_MASK + 10U, // PseudoVLSSEG6E64_V_M1 + 10U, // PseudoVLSSEG6E64_V_M1_MASK + 10U, // PseudoVLSSEG6E8_V_M1 + 10U, // PseudoVLSSEG6E8_V_M1_MASK + 10U, // PseudoVLSSEG6E8_V_MF2 + 10U, // PseudoVLSSEG6E8_V_MF2_MASK + 10U, // PseudoVLSSEG6E8_V_MF4 + 10U, // PseudoVLSSEG6E8_V_MF4_MASK + 10U, // PseudoVLSSEG6E8_V_MF8 + 10U, // PseudoVLSSEG6E8_V_MF8_MASK + 10U, // PseudoVLSSEG7E16_V_M1 + 10U, // PseudoVLSSEG7E16_V_M1_MASK + 10U, // PseudoVLSSEG7E16_V_MF2 + 10U, // PseudoVLSSEG7E16_V_MF2_MASK + 10U, // PseudoVLSSEG7E16_V_MF4 + 10U, // PseudoVLSSEG7E16_V_MF4_MASK + 10U, // PseudoVLSSEG7E32_V_M1 + 10U, // PseudoVLSSEG7E32_V_M1_MASK + 10U, // PseudoVLSSEG7E32_V_MF2 + 10U, // PseudoVLSSEG7E32_V_MF2_MASK + 10U, // PseudoVLSSEG7E64_V_M1 + 10U, // PseudoVLSSEG7E64_V_M1_MASK + 10U, // PseudoVLSSEG7E8_V_M1 + 10U, // PseudoVLSSEG7E8_V_M1_MASK + 10U, // PseudoVLSSEG7E8_V_MF2 + 10U, // PseudoVLSSEG7E8_V_MF2_MASK + 10U, // PseudoVLSSEG7E8_V_MF4 + 10U, // PseudoVLSSEG7E8_V_MF4_MASK + 10U, // PseudoVLSSEG7E8_V_MF8 + 10U, // PseudoVLSSEG7E8_V_MF8_MASK + 10U, // PseudoVLSSEG8E16_V_M1 + 10U, // PseudoVLSSEG8E16_V_M1_MASK + 10U, // PseudoVLSSEG8E16_V_MF2 + 10U, // PseudoVLSSEG8E16_V_MF2_MASK + 10U, // PseudoVLSSEG8E16_V_MF4 + 10U, // PseudoVLSSEG8E16_V_MF4_MASK + 10U, // PseudoVLSSEG8E32_V_M1 + 10U, // PseudoVLSSEG8E32_V_M1_MASK + 10U, // PseudoVLSSEG8E32_V_MF2 + 10U, // PseudoVLSSEG8E32_V_MF2_MASK + 10U, // PseudoVLSSEG8E64_V_M1 + 10U, // PseudoVLSSEG8E64_V_M1_MASK + 10U, // PseudoVLSSEG8E8_V_M1 + 10U, // PseudoVLSSEG8E8_V_M1_MASK + 10U, // PseudoVLSSEG8E8_V_MF2 + 10U, // PseudoVLSSEG8E8_V_MF2_MASK + 10U, // PseudoVLSSEG8E8_V_MF4 + 10U, // PseudoVLSSEG8E8_V_MF4_MASK + 10U, // PseudoVLSSEG8E8_V_MF8 + 10U, // PseudoVLSSEG8E8_V_MF8_MASK + 10U, // PseudoVLUXEI16_V_M1_M1 + 10U, // PseudoVLUXEI16_V_M1_M1_MASK + 10U, // PseudoVLUXEI16_V_M1_M2 + 10U, // PseudoVLUXEI16_V_M1_M2_MASK + 10U, // PseudoVLUXEI16_V_M1_M4 + 10U, // PseudoVLUXEI16_V_M1_M4_MASK + 10U, // PseudoVLUXEI16_V_M1_MF2 + 10U, // PseudoVLUXEI16_V_M1_MF2_MASK + 10U, // PseudoVLUXEI16_V_M2_M1 + 10U, // PseudoVLUXEI16_V_M2_M1_MASK + 10U, // PseudoVLUXEI16_V_M2_M2 + 10U, // PseudoVLUXEI16_V_M2_M2_MASK + 10U, // PseudoVLUXEI16_V_M2_M4 + 10U, // PseudoVLUXEI16_V_M2_M4_MASK + 10U, // PseudoVLUXEI16_V_M2_M8 + 10U, // PseudoVLUXEI16_V_M2_M8_MASK + 10U, // PseudoVLUXEI16_V_M4_M2 + 10U, // PseudoVLUXEI16_V_M4_M2_MASK + 10U, // PseudoVLUXEI16_V_M4_M4 + 10U, // PseudoVLUXEI16_V_M4_M4_MASK + 10U, // PseudoVLUXEI16_V_M4_M8 + 10U, // PseudoVLUXEI16_V_M4_M8_MASK + 10U, // PseudoVLUXEI16_V_M8_M4 + 10U, // PseudoVLUXEI16_V_M8_M4_MASK + 10U, // PseudoVLUXEI16_V_M8_M8 + 10U, // PseudoVLUXEI16_V_M8_M8_MASK + 10U, // PseudoVLUXEI16_V_MF2_M1 + 10U, // PseudoVLUXEI16_V_MF2_M1_MASK + 10U, // PseudoVLUXEI16_V_MF2_M2 + 10U, // PseudoVLUXEI16_V_MF2_M2_MASK + 10U, // PseudoVLUXEI16_V_MF2_MF2 + 10U, // PseudoVLUXEI16_V_MF2_MF2_MASK + 10U, // PseudoVLUXEI16_V_MF2_MF4 + 10U, // PseudoVLUXEI16_V_MF2_MF4_MASK + 10U, // PseudoVLUXEI16_V_MF4_M1 + 10U, // PseudoVLUXEI16_V_MF4_M1_MASK + 10U, // PseudoVLUXEI16_V_MF4_MF2 + 10U, // PseudoVLUXEI16_V_MF4_MF2_MASK + 10U, // PseudoVLUXEI16_V_MF4_MF4 + 10U, // PseudoVLUXEI16_V_MF4_MF4_MASK + 10U, // PseudoVLUXEI16_V_MF4_MF8 + 10U, // PseudoVLUXEI16_V_MF4_MF8_MASK + 10U, // PseudoVLUXEI32_V_M1_M1 + 10U, // PseudoVLUXEI32_V_M1_M1_MASK + 10U, // PseudoVLUXEI32_V_M1_M2 + 10U, // PseudoVLUXEI32_V_M1_M2_MASK + 10U, // PseudoVLUXEI32_V_M1_MF2 + 10U, // PseudoVLUXEI32_V_M1_MF2_MASK + 10U, // PseudoVLUXEI32_V_M1_MF4 + 10U, // PseudoVLUXEI32_V_M1_MF4_MASK + 10U, // PseudoVLUXEI32_V_M2_M1 + 10U, // PseudoVLUXEI32_V_M2_M1_MASK + 10U, // PseudoVLUXEI32_V_M2_M2 + 10U, // PseudoVLUXEI32_V_M2_M2_MASK + 10U, // PseudoVLUXEI32_V_M2_M4 + 10U, // PseudoVLUXEI32_V_M2_M4_MASK + 10U, // PseudoVLUXEI32_V_M2_MF2 + 10U, // PseudoVLUXEI32_V_M2_MF2_MASK + 10U, // PseudoVLUXEI32_V_M4_M1 + 10U, // PseudoVLUXEI32_V_M4_M1_MASK + 10U, // PseudoVLUXEI32_V_M4_M2 + 10U, // PseudoVLUXEI32_V_M4_M2_MASK + 10U, // PseudoVLUXEI32_V_M4_M4 + 10U, // PseudoVLUXEI32_V_M4_M4_MASK + 10U, // PseudoVLUXEI32_V_M4_M8 + 10U, // PseudoVLUXEI32_V_M4_M8_MASK + 10U, // PseudoVLUXEI32_V_M8_M2 + 10U, // PseudoVLUXEI32_V_M8_M2_MASK + 10U, // PseudoVLUXEI32_V_M8_M4 + 10U, // PseudoVLUXEI32_V_M8_M4_MASK + 10U, // PseudoVLUXEI32_V_M8_M8 + 10U, // PseudoVLUXEI32_V_M8_M8_MASK + 10U, // PseudoVLUXEI32_V_MF2_M1 + 10U, // PseudoVLUXEI32_V_MF2_M1_MASK + 10U, // PseudoVLUXEI32_V_MF2_MF2 + 10U, // PseudoVLUXEI32_V_MF2_MF2_MASK + 10U, // PseudoVLUXEI32_V_MF2_MF4 + 10U, // PseudoVLUXEI32_V_MF2_MF4_MASK + 10U, // PseudoVLUXEI32_V_MF2_MF8 + 10U, // PseudoVLUXEI32_V_MF2_MF8_MASK + 10U, // PseudoVLUXEI64_V_M1_M1 + 10U, // PseudoVLUXEI64_V_M1_M1_MASK + 10U, // PseudoVLUXEI64_V_M1_MF2 + 10U, // PseudoVLUXEI64_V_M1_MF2_MASK + 10U, // PseudoVLUXEI64_V_M1_MF4 + 10U, // PseudoVLUXEI64_V_M1_MF4_MASK + 10U, // PseudoVLUXEI64_V_M1_MF8 + 10U, // PseudoVLUXEI64_V_M1_MF8_MASK + 10U, // PseudoVLUXEI64_V_M2_M1 + 10U, // PseudoVLUXEI64_V_M2_M1_MASK + 10U, // PseudoVLUXEI64_V_M2_M2 + 10U, // PseudoVLUXEI64_V_M2_M2_MASK + 10U, // PseudoVLUXEI64_V_M2_MF2 + 10U, // PseudoVLUXEI64_V_M2_MF2_MASK + 10U, // PseudoVLUXEI64_V_M2_MF4 + 10U, // PseudoVLUXEI64_V_M2_MF4_MASK + 10U, // PseudoVLUXEI64_V_M4_M1 + 10U, // PseudoVLUXEI64_V_M4_M1_MASK + 10U, // PseudoVLUXEI64_V_M4_M2 + 10U, // PseudoVLUXEI64_V_M4_M2_MASK + 10U, // PseudoVLUXEI64_V_M4_M4 + 10U, // PseudoVLUXEI64_V_M4_M4_MASK + 10U, // PseudoVLUXEI64_V_M4_MF2 + 10U, // PseudoVLUXEI64_V_M4_MF2_MASK + 10U, // PseudoVLUXEI64_V_M8_M1 + 10U, // PseudoVLUXEI64_V_M8_M1_MASK + 10U, // PseudoVLUXEI64_V_M8_M2 + 10U, // PseudoVLUXEI64_V_M8_M2_MASK + 10U, // PseudoVLUXEI64_V_M8_M4 + 10U, // PseudoVLUXEI64_V_M8_M4_MASK + 10U, // PseudoVLUXEI64_V_M8_M8 + 10U, // PseudoVLUXEI64_V_M8_M8_MASK + 10U, // PseudoVLUXEI8_V_M1_M1 + 10U, // PseudoVLUXEI8_V_M1_M1_MASK + 10U, // PseudoVLUXEI8_V_M1_M2 + 10U, // PseudoVLUXEI8_V_M1_M2_MASK + 10U, // PseudoVLUXEI8_V_M1_M4 + 10U, // PseudoVLUXEI8_V_M1_M4_MASK + 10U, // PseudoVLUXEI8_V_M1_M8 + 10U, // PseudoVLUXEI8_V_M1_M8_MASK + 10U, // PseudoVLUXEI8_V_M2_M2 + 10U, // PseudoVLUXEI8_V_M2_M2_MASK + 10U, // PseudoVLUXEI8_V_M2_M4 + 10U, // PseudoVLUXEI8_V_M2_M4_MASK + 10U, // PseudoVLUXEI8_V_M2_M8 + 10U, // PseudoVLUXEI8_V_M2_M8_MASK + 10U, // PseudoVLUXEI8_V_M4_M4 + 10U, // PseudoVLUXEI8_V_M4_M4_MASK + 10U, // PseudoVLUXEI8_V_M4_M8 + 10U, // PseudoVLUXEI8_V_M4_M8_MASK + 10U, // PseudoVLUXEI8_V_M8_M8 + 10U, // PseudoVLUXEI8_V_M8_M8_MASK + 10U, // PseudoVLUXEI8_V_MF2_M1 + 10U, // PseudoVLUXEI8_V_MF2_M1_MASK + 10U, // PseudoVLUXEI8_V_MF2_M2 + 10U, // PseudoVLUXEI8_V_MF2_M2_MASK + 10U, // PseudoVLUXEI8_V_MF2_M4 + 10U, // PseudoVLUXEI8_V_MF2_M4_MASK + 10U, // PseudoVLUXEI8_V_MF2_MF2 + 10U, // PseudoVLUXEI8_V_MF2_MF2_MASK + 10U, // PseudoVLUXEI8_V_MF4_M1 + 10U, // PseudoVLUXEI8_V_MF4_M1_MASK + 10U, // PseudoVLUXEI8_V_MF4_M2 + 10U, // PseudoVLUXEI8_V_MF4_M2_MASK + 10U, // PseudoVLUXEI8_V_MF4_MF2 + 10U, // PseudoVLUXEI8_V_MF4_MF2_MASK + 10U, // PseudoVLUXEI8_V_MF4_MF4 + 10U, // PseudoVLUXEI8_V_MF4_MF4_MASK + 10U, // PseudoVLUXEI8_V_MF8_M1 + 10U, // PseudoVLUXEI8_V_MF8_M1_MASK + 10U, // PseudoVLUXEI8_V_MF8_MF2 + 10U, // PseudoVLUXEI8_V_MF8_MF2_MASK + 10U, // PseudoVLUXEI8_V_MF8_MF4 + 10U, // PseudoVLUXEI8_V_MF8_MF4_MASK + 10U, // PseudoVLUXEI8_V_MF8_MF8 + 10U, // PseudoVLUXEI8_V_MF8_MF8_MASK + 10U, // PseudoVLUXSEG2EI16_V_M1_M1 + 10U, // PseudoVLUXSEG2EI16_V_M1_M1_MASK + 10U, // PseudoVLUXSEG2EI16_V_M1_M2 + 10U, // PseudoVLUXSEG2EI16_V_M1_M2_MASK + 10U, // PseudoVLUXSEG2EI16_V_M1_M4 + 10U, // PseudoVLUXSEG2EI16_V_M1_M4_MASK + 10U, // PseudoVLUXSEG2EI16_V_M1_MF2 + 10U, // PseudoVLUXSEG2EI16_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG2EI16_V_M2_M1 + 10U, // PseudoVLUXSEG2EI16_V_M2_M1_MASK + 10U, // PseudoVLUXSEG2EI16_V_M2_M2 + 10U, // PseudoVLUXSEG2EI16_V_M2_M2_MASK + 10U, // PseudoVLUXSEG2EI16_V_M2_M4 + 10U, // PseudoVLUXSEG2EI16_V_M2_M4_MASK + 10U, // PseudoVLUXSEG2EI16_V_M4_M2 + 10U, // PseudoVLUXSEG2EI16_V_M4_M2_MASK + 10U, // PseudoVLUXSEG2EI16_V_M4_M4 + 10U, // PseudoVLUXSEG2EI16_V_M4_M4_MASK + 10U, // PseudoVLUXSEG2EI16_V_M8_M4 + 10U, // PseudoVLUXSEG2EI16_V_M8_M4_MASK + 10U, // PseudoVLUXSEG2EI16_V_MF2_M1 + 10U, // PseudoVLUXSEG2EI16_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG2EI16_V_MF2_M2 + 10U, // PseudoVLUXSEG2EI16_V_MF2_M2_MASK + 10U, // PseudoVLUXSEG2EI16_V_MF2_MF2 + 10U, // PseudoVLUXSEG2EI16_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG2EI16_V_MF2_MF4 + 10U, // PseudoVLUXSEG2EI16_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG2EI16_V_MF4_M1 + 10U, // PseudoVLUXSEG2EI16_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG2EI16_V_MF4_MF2 + 10U, // PseudoVLUXSEG2EI16_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG2EI16_V_MF4_MF4 + 10U, // PseudoVLUXSEG2EI16_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG2EI16_V_MF4_MF8 + 10U, // PseudoVLUXSEG2EI16_V_MF4_MF8_MASK + 10U, // PseudoVLUXSEG2EI32_V_M1_M1 + 10U, // PseudoVLUXSEG2EI32_V_M1_M1_MASK + 10U, // PseudoVLUXSEG2EI32_V_M1_M2 + 10U, // PseudoVLUXSEG2EI32_V_M1_M2_MASK + 10U, // PseudoVLUXSEG2EI32_V_M1_MF2 + 10U, // PseudoVLUXSEG2EI32_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG2EI32_V_M1_MF4 + 10U, // PseudoVLUXSEG2EI32_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG2EI32_V_M2_M1 + 10U, // PseudoVLUXSEG2EI32_V_M2_M1_MASK + 10U, // PseudoVLUXSEG2EI32_V_M2_M2 + 10U, // PseudoVLUXSEG2EI32_V_M2_M2_MASK + 10U, // PseudoVLUXSEG2EI32_V_M2_M4 + 10U, // PseudoVLUXSEG2EI32_V_M2_M4_MASK + 10U, // PseudoVLUXSEG2EI32_V_M2_MF2 + 10U, // PseudoVLUXSEG2EI32_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG2EI32_V_M4_M1 + 10U, // PseudoVLUXSEG2EI32_V_M4_M1_MASK + 10U, // PseudoVLUXSEG2EI32_V_M4_M2 + 10U, // PseudoVLUXSEG2EI32_V_M4_M2_MASK + 10U, // PseudoVLUXSEG2EI32_V_M4_M4 + 10U, // PseudoVLUXSEG2EI32_V_M4_M4_MASK + 10U, // PseudoVLUXSEG2EI32_V_M8_M2 + 10U, // PseudoVLUXSEG2EI32_V_M8_M2_MASK + 10U, // PseudoVLUXSEG2EI32_V_M8_M4 + 10U, // PseudoVLUXSEG2EI32_V_M8_M4_MASK + 10U, // PseudoVLUXSEG2EI32_V_MF2_M1 + 10U, // PseudoVLUXSEG2EI32_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG2EI32_V_MF2_MF2 + 10U, // PseudoVLUXSEG2EI32_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG2EI32_V_MF2_MF4 + 10U, // PseudoVLUXSEG2EI32_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG2EI32_V_MF2_MF8 + 10U, // PseudoVLUXSEG2EI32_V_MF2_MF8_MASK + 10U, // PseudoVLUXSEG2EI64_V_M1_M1 + 10U, // PseudoVLUXSEG2EI64_V_M1_M1_MASK + 10U, // PseudoVLUXSEG2EI64_V_M1_MF2 + 10U, // PseudoVLUXSEG2EI64_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG2EI64_V_M1_MF4 + 10U, // PseudoVLUXSEG2EI64_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG2EI64_V_M1_MF8 + 10U, // PseudoVLUXSEG2EI64_V_M1_MF8_MASK + 10U, // PseudoVLUXSEG2EI64_V_M2_M1 + 10U, // PseudoVLUXSEG2EI64_V_M2_M1_MASK + 10U, // PseudoVLUXSEG2EI64_V_M2_M2 + 10U, // PseudoVLUXSEG2EI64_V_M2_M2_MASK + 10U, // PseudoVLUXSEG2EI64_V_M2_MF2 + 10U, // PseudoVLUXSEG2EI64_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG2EI64_V_M2_MF4 + 10U, // PseudoVLUXSEG2EI64_V_M2_MF4_MASK + 10U, // PseudoVLUXSEG2EI64_V_M4_M1 + 10U, // PseudoVLUXSEG2EI64_V_M4_M1_MASK + 10U, // PseudoVLUXSEG2EI64_V_M4_M2 + 10U, // PseudoVLUXSEG2EI64_V_M4_M2_MASK + 10U, // PseudoVLUXSEG2EI64_V_M4_M4 + 10U, // PseudoVLUXSEG2EI64_V_M4_M4_MASK + 10U, // PseudoVLUXSEG2EI64_V_M4_MF2 + 10U, // PseudoVLUXSEG2EI64_V_M4_MF2_MASK + 10U, // PseudoVLUXSEG2EI64_V_M8_M1 + 10U, // PseudoVLUXSEG2EI64_V_M8_M1_MASK + 10U, // PseudoVLUXSEG2EI64_V_M8_M2 + 10U, // PseudoVLUXSEG2EI64_V_M8_M2_MASK + 10U, // PseudoVLUXSEG2EI64_V_M8_M4 + 10U, // PseudoVLUXSEG2EI64_V_M8_M4_MASK + 10U, // PseudoVLUXSEG2EI8_V_M1_M1 + 10U, // PseudoVLUXSEG2EI8_V_M1_M1_MASK + 10U, // PseudoVLUXSEG2EI8_V_M1_M2 + 10U, // PseudoVLUXSEG2EI8_V_M1_M2_MASK + 10U, // PseudoVLUXSEG2EI8_V_M1_M4 + 10U, // PseudoVLUXSEG2EI8_V_M1_M4_MASK + 10U, // PseudoVLUXSEG2EI8_V_M2_M2 + 10U, // PseudoVLUXSEG2EI8_V_M2_M2_MASK + 10U, // PseudoVLUXSEG2EI8_V_M2_M4 + 10U, // PseudoVLUXSEG2EI8_V_M2_M4_MASK + 10U, // PseudoVLUXSEG2EI8_V_M4_M4 + 10U, // PseudoVLUXSEG2EI8_V_M4_M4_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF2_M1 + 10U, // PseudoVLUXSEG2EI8_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF2_M2 + 10U, // PseudoVLUXSEG2EI8_V_MF2_M2_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF2_M4 + 10U, // PseudoVLUXSEG2EI8_V_MF2_M4_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF2_MF2 + 10U, // PseudoVLUXSEG2EI8_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF4_M1 + 10U, // PseudoVLUXSEG2EI8_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF4_M2 + 10U, // PseudoVLUXSEG2EI8_V_MF4_M2_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF4_MF2 + 10U, // PseudoVLUXSEG2EI8_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF4_MF4 + 10U, // PseudoVLUXSEG2EI8_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF8_M1 + 10U, // PseudoVLUXSEG2EI8_V_MF8_M1_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF8_MF2 + 10U, // PseudoVLUXSEG2EI8_V_MF8_MF2_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF8_MF4 + 10U, // PseudoVLUXSEG2EI8_V_MF8_MF4_MASK + 10U, // PseudoVLUXSEG2EI8_V_MF8_MF8 + 10U, // PseudoVLUXSEG2EI8_V_MF8_MF8_MASK + 10U, // PseudoVLUXSEG3EI16_V_M1_M1 + 10U, // PseudoVLUXSEG3EI16_V_M1_M1_MASK + 10U, // PseudoVLUXSEG3EI16_V_M1_M2 + 10U, // PseudoVLUXSEG3EI16_V_M1_M2_MASK + 10U, // PseudoVLUXSEG3EI16_V_M1_MF2 + 10U, // PseudoVLUXSEG3EI16_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG3EI16_V_M2_M1 + 10U, // PseudoVLUXSEG3EI16_V_M2_M1_MASK + 10U, // PseudoVLUXSEG3EI16_V_M2_M2 + 10U, // PseudoVLUXSEG3EI16_V_M2_M2_MASK + 10U, // PseudoVLUXSEG3EI16_V_M4_M2 + 10U, // PseudoVLUXSEG3EI16_V_M4_M2_MASK + 10U, // PseudoVLUXSEG3EI16_V_MF2_M1 + 10U, // PseudoVLUXSEG3EI16_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG3EI16_V_MF2_M2 + 10U, // PseudoVLUXSEG3EI16_V_MF2_M2_MASK + 10U, // PseudoVLUXSEG3EI16_V_MF2_MF2 + 10U, // PseudoVLUXSEG3EI16_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG3EI16_V_MF2_MF4 + 10U, // PseudoVLUXSEG3EI16_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG3EI16_V_MF4_M1 + 10U, // PseudoVLUXSEG3EI16_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG3EI16_V_MF4_MF2 + 10U, // PseudoVLUXSEG3EI16_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG3EI16_V_MF4_MF4 + 10U, // PseudoVLUXSEG3EI16_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG3EI16_V_MF4_MF8 + 10U, // PseudoVLUXSEG3EI16_V_MF4_MF8_MASK + 10U, // PseudoVLUXSEG3EI32_V_M1_M1 + 10U, // PseudoVLUXSEG3EI32_V_M1_M1_MASK + 10U, // PseudoVLUXSEG3EI32_V_M1_M2 + 10U, // PseudoVLUXSEG3EI32_V_M1_M2_MASK + 10U, // PseudoVLUXSEG3EI32_V_M1_MF2 + 10U, // PseudoVLUXSEG3EI32_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG3EI32_V_M1_MF4 + 10U, // PseudoVLUXSEG3EI32_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG3EI32_V_M2_M1 + 10U, // PseudoVLUXSEG3EI32_V_M2_M1_MASK + 10U, // PseudoVLUXSEG3EI32_V_M2_M2 + 10U, // PseudoVLUXSEG3EI32_V_M2_M2_MASK + 10U, // PseudoVLUXSEG3EI32_V_M2_MF2 + 10U, // PseudoVLUXSEG3EI32_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG3EI32_V_M4_M1 + 10U, // PseudoVLUXSEG3EI32_V_M4_M1_MASK + 10U, // PseudoVLUXSEG3EI32_V_M4_M2 + 10U, // PseudoVLUXSEG3EI32_V_M4_M2_MASK + 10U, // PseudoVLUXSEG3EI32_V_M8_M2 + 10U, // PseudoVLUXSEG3EI32_V_M8_M2_MASK + 10U, // PseudoVLUXSEG3EI32_V_MF2_M1 + 10U, // PseudoVLUXSEG3EI32_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG3EI32_V_MF2_MF2 + 10U, // PseudoVLUXSEG3EI32_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG3EI32_V_MF2_MF4 + 10U, // PseudoVLUXSEG3EI32_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG3EI32_V_MF2_MF8 + 10U, // PseudoVLUXSEG3EI32_V_MF2_MF8_MASK + 10U, // PseudoVLUXSEG3EI64_V_M1_M1 + 10U, // PseudoVLUXSEG3EI64_V_M1_M1_MASK + 10U, // PseudoVLUXSEG3EI64_V_M1_MF2 + 10U, // PseudoVLUXSEG3EI64_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG3EI64_V_M1_MF4 + 10U, // PseudoVLUXSEG3EI64_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG3EI64_V_M1_MF8 + 10U, // PseudoVLUXSEG3EI64_V_M1_MF8_MASK + 10U, // PseudoVLUXSEG3EI64_V_M2_M1 + 10U, // PseudoVLUXSEG3EI64_V_M2_M1_MASK + 10U, // PseudoVLUXSEG3EI64_V_M2_M2 + 10U, // PseudoVLUXSEG3EI64_V_M2_M2_MASK + 10U, // PseudoVLUXSEG3EI64_V_M2_MF2 + 10U, // PseudoVLUXSEG3EI64_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG3EI64_V_M2_MF4 + 10U, // PseudoVLUXSEG3EI64_V_M2_MF4_MASK + 10U, // PseudoVLUXSEG3EI64_V_M4_M1 + 10U, // PseudoVLUXSEG3EI64_V_M4_M1_MASK + 10U, // PseudoVLUXSEG3EI64_V_M4_M2 + 10U, // PseudoVLUXSEG3EI64_V_M4_M2_MASK + 10U, // PseudoVLUXSEG3EI64_V_M4_MF2 + 10U, // PseudoVLUXSEG3EI64_V_M4_MF2_MASK + 10U, // PseudoVLUXSEG3EI64_V_M8_M1 + 10U, // PseudoVLUXSEG3EI64_V_M8_M1_MASK + 10U, // PseudoVLUXSEG3EI64_V_M8_M2 + 10U, // PseudoVLUXSEG3EI64_V_M8_M2_MASK + 10U, // PseudoVLUXSEG3EI8_V_M1_M1 + 10U, // PseudoVLUXSEG3EI8_V_M1_M1_MASK + 10U, // PseudoVLUXSEG3EI8_V_M1_M2 + 10U, // PseudoVLUXSEG3EI8_V_M1_M2_MASK + 10U, // PseudoVLUXSEG3EI8_V_M2_M2 + 10U, // PseudoVLUXSEG3EI8_V_M2_M2_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF2_M1 + 10U, // PseudoVLUXSEG3EI8_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF2_M2 + 10U, // PseudoVLUXSEG3EI8_V_MF2_M2_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF2_MF2 + 10U, // PseudoVLUXSEG3EI8_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF4_M1 + 10U, // PseudoVLUXSEG3EI8_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF4_M2 + 10U, // PseudoVLUXSEG3EI8_V_MF4_M2_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF4_MF2 + 10U, // PseudoVLUXSEG3EI8_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF4_MF4 + 10U, // PseudoVLUXSEG3EI8_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF8_M1 + 10U, // PseudoVLUXSEG3EI8_V_MF8_M1_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF8_MF2 + 10U, // PseudoVLUXSEG3EI8_V_MF8_MF2_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF8_MF4 + 10U, // PseudoVLUXSEG3EI8_V_MF8_MF4_MASK + 10U, // PseudoVLUXSEG3EI8_V_MF8_MF8 + 10U, // PseudoVLUXSEG3EI8_V_MF8_MF8_MASK + 10U, // PseudoVLUXSEG4EI16_V_M1_M1 + 10U, // PseudoVLUXSEG4EI16_V_M1_M1_MASK + 10U, // PseudoVLUXSEG4EI16_V_M1_M2 + 10U, // PseudoVLUXSEG4EI16_V_M1_M2_MASK + 10U, // PseudoVLUXSEG4EI16_V_M1_MF2 + 10U, // PseudoVLUXSEG4EI16_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG4EI16_V_M2_M1 + 10U, // PseudoVLUXSEG4EI16_V_M2_M1_MASK + 10U, // PseudoVLUXSEG4EI16_V_M2_M2 + 10U, // PseudoVLUXSEG4EI16_V_M2_M2_MASK + 10U, // PseudoVLUXSEG4EI16_V_M4_M2 + 10U, // PseudoVLUXSEG4EI16_V_M4_M2_MASK + 10U, // PseudoVLUXSEG4EI16_V_MF2_M1 + 10U, // PseudoVLUXSEG4EI16_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG4EI16_V_MF2_M2 + 10U, // PseudoVLUXSEG4EI16_V_MF2_M2_MASK + 10U, // PseudoVLUXSEG4EI16_V_MF2_MF2 + 10U, // PseudoVLUXSEG4EI16_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG4EI16_V_MF2_MF4 + 10U, // PseudoVLUXSEG4EI16_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG4EI16_V_MF4_M1 + 10U, // PseudoVLUXSEG4EI16_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG4EI16_V_MF4_MF2 + 10U, // PseudoVLUXSEG4EI16_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG4EI16_V_MF4_MF4 + 10U, // PseudoVLUXSEG4EI16_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG4EI16_V_MF4_MF8 + 10U, // PseudoVLUXSEG4EI16_V_MF4_MF8_MASK + 10U, // PseudoVLUXSEG4EI32_V_M1_M1 + 10U, // PseudoVLUXSEG4EI32_V_M1_M1_MASK + 10U, // PseudoVLUXSEG4EI32_V_M1_M2 + 10U, // PseudoVLUXSEG4EI32_V_M1_M2_MASK + 10U, // PseudoVLUXSEG4EI32_V_M1_MF2 + 10U, // PseudoVLUXSEG4EI32_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG4EI32_V_M1_MF4 + 10U, // PseudoVLUXSEG4EI32_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG4EI32_V_M2_M1 + 10U, // PseudoVLUXSEG4EI32_V_M2_M1_MASK + 10U, // PseudoVLUXSEG4EI32_V_M2_M2 + 10U, // PseudoVLUXSEG4EI32_V_M2_M2_MASK + 10U, // PseudoVLUXSEG4EI32_V_M2_MF2 + 10U, // PseudoVLUXSEG4EI32_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG4EI32_V_M4_M1 + 10U, // PseudoVLUXSEG4EI32_V_M4_M1_MASK + 10U, // PseudoVLUXSEG4EI32_V_M4_M2 + 10U, // PseudoVLUXSEG4EI32_V_M4_M2_MASK + 10U, // PseudoVLUXSEG4EI32_V_M8_M2 + 10U, // PseudoVLUXSEG4EI32_V_M8_M2_MASK + 10U, // PseudoVLUXSEG4EI32_V_MF2_M1 + 10U, // PseudoVLUXSEG4EI32_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG4EI32_V_MF2_MF2 + 10U, // PseudoVLUXSEG4EI32_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG4EI32_V_MF2_MF4 + 10U, // PseudoVLUXSEG4EI32_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG4EI32_V_MF2_MF8 + 10U, // PseudoVLUXSEG4EI32_V_MF2_MF8_MASK + 10U, // PseudoVLUXSEG4EI64_V_M1_M1 + 10U, // PseudoVLUXSEG4EI64_V_M1_M1_MASK + 10U, // PseudoVLUXSEG4EI64_V_M1_MF2 + 10U, // PseudoVLUXSEG4EI64_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG4EI64_V_M1_MF4 + 10U, // PseudoVLUXSEG4EI64_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG4EI64_V_M1_MF8 + 10U, // PseudoVLUXSEG4EI64_V_M1_MF8_MASK + 10U, // PseudoVLUXSEG4EI64_V_M2_M1 + 10U, // PseudoVLUXSEG4EI64_V_M2_M1_MASK + 10U, // PseudoVLUXSEG4EI64_V_M2_M2 + 10U, // PseudoVLUXSEG4EI64_V_M2_M2_MASK + 10U, // PseudoVLUXSEG4EI64_V_M2_MF2 + 10U, // PseudoVLUXSEG4EI64_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG4EI64_V_M2_MF4 + 10U, // PseudoVLUXSEG4EI64_V_M2_MF4_MASK + 10U, // PseudoVLUXSEG4EI64_V_M4_M1 + 10U, // PseudoVLUXSEG4EI64_V_M4_M1_MASK + 10U, // PseudoVLUXSEG4EI64_V_M4_M2 + 10U, // PseudoVLUXSEG4EI64_V_M4_M2_MASK + 10U, // PseudoVLUXSEG4EI64_V_M4_MF2 + 10U, // PseudoVLUXSEG4EI64_V_M4_MF2_MASK + 10U, // PseudoVLUXSEG4EI64_V_M8_M1 + 10U, // PseudoVLUXSEG4EI64_V_M8_M1_MASK + 10U, // PseudoVLUXSEG4EI64_V_M8_M2 + 10U, // PseudoVLUXSEG4EI64_V_M8_M2_MASK + 10U, // PseudoVLUXSEG4EI8_V_M1_M1 + 10U, // PseudoVLUXSEG4EI8_V_M1_M1_MASK + 10U, // PseudoVLUXSEG4EI8_V_M1_M2 + 10U, // PseudoVLUXSEG4EI8_V_M1_M2_MASK + 10U, // PseudoVLUXSEG4EI8_V_M2_M2 + 10U, // PseudoVLUXSEG4EI8_V_M2_M2_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF2_M1 + 10U, // PseudoVLUXSEG4EI8_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF2_M2 + 10U, // PseudoVLUXSEG4EI8_V_MF2_M2_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF2_MF2 + 10U, // PseudoVLUXSEG4EI8_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF4_M1 + 10U, // PseudoVLUXSEG4EI8_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF4_M2 + 10U, // PseudoVLUXSEG4EI8_V_MF4_M2_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF4_MF2 + 10U, // PseudoVLUXSEG4EI8_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF4_MF4 + 10U, // PseudoVLUXSEG4EI8_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF8_M1 + 10U, // PseudoVLUXSEG4EI8_V_MF8_M1_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF8_MF2 + 10U, // PseudoVLUXSEG4EI8_V_MF8_MF2_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF8_MF4 + 10U, // PseudoVLUXSEG4EI8_V_MF8_MF4_MASK + 10U, // PseudoVLUXSEG4EI8_V_MF8_MF8 + 10U, // PseudoVLUXSEG4EI8_V_MF8_MF8_MASK + 10U, // PseudoVLUXSEG5EI16_V_M1_M1 + 10U, // PseudoVLUXSEG5EI16_V_M1_M1_MASK + 10U, // PseudoVLUXSEG5EI16_V_M1_MF2 + 10U, // PseudoVLUXSEG5EI16_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG5EI16_V_M2_M1 + 10U, // PseudoVLUXSEG5EI16_V_M2_M1_MASK + 10U, // PseudoVLUXSEG5EI16_V_MF2_M1 + 10U, // PseudoVLUXSEG5EI16_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG5EI16_V_MF2_MF2 + 10U, // PseudoVLUXSEG5EI16_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG5EI16_V_MF2_MF4 + 10U, // PseudoVLUXSEG5EI16_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG5EI16_V_MF4_M1 + 10U, // PseudoVLUXSEG5EI16_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG5EI16_V_MF4_MF2 + 10U, // PseudoVLUXSEG5EI16_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG5EI16_V_MF4_MF4 + 10U, // PseudoVLUXSEG5EI16_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG5EI16_V_MF4_MF8 + 10U, // PseudoVLUXSEG5EI16_V_MF4_MF8_MASK + 10U, // PseudoVLUXSEG5EI32_V_M1_M1 + 10U, // PseudoVLUXSEG5EI32_V_M1_M1_MASK + 10U, // PseudoVLUXSEG5EI32_V_M1_MF2 + 10U, // PseudoVLUXSEG5EI32_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG5EI32_V_M1_MF4 + 10U, // PseudoVLUXSEG5EI32_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG5EI32_V_M2_M1 + 10U, // PseudoVLUXSEG5EI32_V_M2_M1_MASK + 10U, // PseudoVLUXSEG5EI32_V_M2_MF2 + 10U, // PseudoVLUXSEG5EI32_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG5EI32_V_M4_M1 + 10U, // PseudoVLUXSEG5EI32_V_M4_M1_MASK + 10U, // PseudoVLUXSEG5EI32_V_MF2_M1 + 10U, // PseudoVLUXSEG5EI32_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG5EI32_V_MF2_MF2 + 10U, // PseudoVLUXSEG5EI32_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG5EI32_V_MF2_MF4 + 10U, // PseudoVLUXSEG5EI32_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG5EI32_V_MF2_MF8 + 10U, // PseudoVLUXSEG5EI32_V_MF2_MF8_MASK + 10U, // PseudoVLUXSEG5EI64_V_M1_M1 + 10U, // PseudoVLUXSEG5EI64_V_M1_M1_MASK + 10U, // PseudoVLUXSEG5EI64_V_M1_MF2 + 10U, // PseudoVLUXSEG5EI64_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG5EI64_V_M1_MF4 + 10U, // PseudoVLUXSEG5EI64_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG5EI64_V_M1_MF8 + 10U, // PseudoVLUXSEG5EI64_V_M1_MF8_MASK + 10U, // PseudoVLUXSEG5EI64_V_M2_M1 + 10U, // PseudoVLUXSEG5EI64_V_M2_M1_MASK + 10U, // PseudoVLUXSEG5EI64_V_M2_MF2 + 10U, // PseudoVLUXSEG5EI64_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG5EI64_V_M2_MF4 + 10U, // PseudoVLUXSEG5EI64_V_M2_MF4_MASK + 10U, // PseudoVLUXSEG5EI64_V_M4_M1 + 10U, // PseudoVLUXSEG5EI64_V_M4_M1_MASK + 10U, // PseudoVLUXSEG5EI64_V_M4_MF2 + 10U, // PseudoVLUXSEG5EI64_V_M4_MF2_MASK + 10U, // PseudoVLUXSEG5EI64_V_M8_M1 + 10U, // PseudoVLUXSEG5EI64_V_M8_M1_MASK + 10U, // PseudoVLUXSEG5EI8_V_M1_M1 + 10U, // PseudoVLUXSEG5EI8_V_M1_M1_MASK + 10U, // PseudoVLUXSEG5EI8_V_MF2_M1 + 10U, // PseudoVLUXSEG5EI8_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG5EI8_V_MF2_MF2 + 10U, // PseudoVLUXSEG5EI8_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG5EI8_V_MF4_M1 + 10U, // PseudoVLUXSEG5EI8_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG5EI8_V_MF4_MF2 + 10U, // PseudoVLUXSEG5EI8_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG5EI8_V_MF4_MF4 + 10U, // PseudoVLUXSEG5EI8_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG5EI8_V_MF8_M1 + 10U, // PseudoVLUXSEG5EI8_V_MF8_M1_MASK + 10U, // PseudoVLUXSEG5EI8_V_MF8_MF2 + 10U, // PseudoVLUXSEG5EI8_V_MF8_MF2_MASK + 10U, // PseudoVLUXSEG5EI8_V_MF8_MF4 + 10U, // PseudoVLUXSEG5EI8_V_MF8_MF4_MASK + 10U, // PseudoVLUXSEG5EI8_V_MF8_MF8 + 10U, // PseudoVLUXSEG5EI8_V_MF8_MF8_MASK + 10U, // PseudoVLUXSEG6EI16_V_M1_M1 + 10U, // PseudoVLUXSEG6EI16_V_M1_M1_MASK + 10U, // PseudoVLUXSEG6EI16_V_M1_MF2 + 10U, // PseudoVLUXSEG6EI16_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG6EI16_V_M2_M1 + 10U, // PseudoVLUXSEG6EI16_V_M2_M1_MASK + 10U, // PseudoVLUXSEG6EI16_V_MF2_M1 + 10U, // PseudoVLUXSEG6EI16_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG6EI16_V_MF2_MF2 + 10U, // PseudoVLUXSEG6EI16_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG6EI16_V_MF2_MF4 + 10U, // PseudoVLUXSEG6EI16_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG6EI16_V_MF4_M1 + 10U, // PseudoVLUXSEG6EI16_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG6EI16_V_MF4_MF2 + 10U, // PseudoVLUXSEG6EI16_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG6EI16_V_MF4_MF4 + 10U, // PseudoVLUXSEG6EI16_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG6EI16_V_MF4_MF8 + 10U, // PseudoVLUXSEG6EI16_V_MF4_MF8_MASK + 10U, // PseudoVLUXSEG6EI32_V_M1_M1 + 10U, // PseudoVLUXSEG6EI32_V_M1_M1_MASK + 10U, // PseudoVLUXSEG6EI32_V_M1_MF2 + 10U, // PseudoVLUXSEG6EI32_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG6EI32_V_M1_MF4 + 10U, // PseudoVLUXSEG6EI32_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG6EI32_V_M2_M1 + 10U, // PseudoVLUXSEG6EI32_V_M2_M1_MASK + 10U, // PseudoVLUXSEG6EI32_V_M2_MF2 + 10U, // PseudoVLUXSEG6EI32_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG6EI32_V_M4_M1 + 10U, // PseudoVLUXSEG6EI32_V_M4_M1_MASK + 10U, // PseudoVLUXSEG6EI32_V_MF2_M1 + 10U, // PseudoVLUXSEG6EI32_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG6EI32_V_MF2_MF2 + 10U, // PseudoVLUXSEG6EI32_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG6EI32_V_MF2_MF4 + 10U, // PseudoVLUXSEG6EI32_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG6EI32_V_MF2_MF8 + 10U, // PseudoVLUXSEG6EI32_V_MF2_MF8_MASK + 10U, // PseudoVLUXSEG6EI64_V_M1_M1 + 10U, // PseudoVLUXSEG6EI64_V_M1_M1_MASK + 10U, // PseudoVLUXSEG6EI64_V_M1_MF2 + 10U, // PseudoVLUXSEG6EI64_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG6EI64_V_M1_MF4 + 10U, // PseudoVLUXSEG6EI64_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG6EI64_V_M1_MF8 + 10U, // PseudoVLUXSEG6EI64_V_M1_MF8_MASK + 10U, // PseudoVLUXSEG6EI64_V_M2_M1 + 10U, // PseudoVLUXSEG6EI64_V_M2_M1_MASK + 10U, // PseudoVLUXSEG6EI64_V_M2_MF2 + 10U, // PseudoVLUXSEG6EI64_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG6EI64_V_M2_MF4 + 10U, // PseudoVLUXSEG6EI64_V_M2_MF4_MASK + 10U, // PseudoVLUXSEG6EI64_V_M4_M1 + 10U, // PseudoVLUXSEG6EI64_V_M4_M1_MASK + 10U, // PseudoVLUXSEG6EI64_V_M4_MF2 + 10U, // PseudoVLUXSEG6EI64_V_M4_MF2_MASK + 10U, // PseudoVLUXSEG6EI64_V_M8_M1 + 10U, // PseudoVLUXSEG6EI64_V_M8_M1_MASK + 10U, // PseudoVLUXSEG6EI8_V_M1_M1 + 10U, // PseudoVLUXSEG6EI8_V_M1_M1_MASK + 10U, // PseudoVLUXSEG6EI8_V_MF2_M1 + 10U, // PseudoVLUXSEG6EI8_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG6EI8_V_MF2_MF2 + 10U, // PseudoVLUXSEG6EI8_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG6EI8_V_MF4_M1 + 10U, // PseudoVLUXSEG6EI8_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG6EI8_V_MF4_MF2 + 10U, // PseudoVLUXSEG6EI8_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG6EI8_V_MF4_MF4 + 10U, // PseudoVLUXSEG6EI8_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG6EI8_V_MF8_M1 + 10U, // PseudoVLUXSEG6EI8_V_MF8_M1_MASK + 10U, // PseudoVLUXSEG6EI8_V_MF8_MF2 + 10U, // PseudoVLUXSEG6EI8_V_MF8_MF2_MASK + 10U, // PseudoVLUXSEG6EI8_V_MF8_MF4 + 10U, // PseudoVLUXSEG6EI8_V_MF8_MF4_MASK + 10U, // PseudoVLUXSEG6EI8_V_MF8_MF8 + 10U, // PseudoVLUXSEG6EI8_V_MF8_MF8_MASK + 10U, // PseudoVLUXSEG7EI16_V_M1_M1 + 10U, // PseudoVLUXSEG7EI16_V_M1_M1_MASK + 10U, // PseudoVLUXSEG7EI16_V_M1_MF2 + 10U, // PseudoVLUXSEG7EI16_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG7EI16_V_M2_M1 + 10U, // PseudoVLUXSEG7EI16_V_M2_M1_MASK + 10U, // PseudoVLUXSEG7EI16_V_MF2_M1 + 10U, // PseudoVLUXSEG7EI16_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG7EI16_V_MF2_MF2 + 10U, // PseudoVLUXSEG7EI16_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG7EI16_V_MF2_MF4 + 10U, // PseudoVLUXSEG7EI16_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG7EI16_V_MF4_M1 + 10U, // PseudoVLUXSEG7EI16_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG7EI16_V_MF4_MF2 + 10U, // PseudoVLUXSEG7EI16_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG7EI16_V_MF4_MF4 + 10U, // PseudoVLUXSEG7EI16_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG7EI16_V_MF4_MF8 + 10U, // PseudoVLUXSEG7EI16_V_MF4_MF8_MASK + 10U, // PseudoVLUXSEG7EI32_V_M1_M1 + 10U, // PseudoVLUXSEG7EI32_V_M1_M1_MASK + 10U, // PseudoVLUXSEG7EI32_V_M1_MF2 + 10U, // PseudoVLUXSEG7EI32_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG7EI32_V_M1_MF4 + 10U, // PseudoVLUXSEG7EI32_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG7EI32_V_M2_M1 + 10U, // PseudoVLUXSEG7EI32_V_M2_M1_MASK + 10U, // PseudoVLUXSEG7EI32_V_M2_MF2 + 10U, // PseudoVLUXSEG7EI32_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG7EI32_V_M4_M1 + 10U, // PseudoVLUXSEG7EI32_V_M4_M1_MASK + 10U, // PseudoVLUXSEG7EI32_V_MF2_M1 + 10U, // PseudoVLUXSEG7EI32_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG7EI32_V_MF2_MF2 + 10U, // PseudoVLUXSEG7EI32_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG7EI32_V_MF2_MF4 + 10U, // PseudoVLUXSEG7EI32_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG7EI32_V_MF2_MF8 + 10U, // PseudoVLUXSEG7EI32_V_MF2_MF8_MASK + 10U, // PseudoVLUXSEG7EI64_V_M1_M1 + 10U, // PseudoVLUXSEG7EI64_V_M1_M1_MASK + 10U, // PseudoVLUXSEG7EI64_V_M1_MF2 + 10U, // PseudoVLUXSEG7EI64_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG7EI64_V_M1_MF4 + 10U, // PseudoVLUXSEG7EI64_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG7EI64_V_M1_MF8 + 10U, // PseudoVLUXSEG7EI64_V_M1_MF8_MASK + 10U, // PseudoVLUXSEG7EI64_V_M2_M1 + 10U, // PseudoVLUXSEG7EI64_V_M2_M1_MASK + 10U, // PseudoVLUXSEG7EI64_V_M2_MF2 + 10U, // PseudoVLUXSEG7EI64_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG7EI64_V_M2_MF4 + 10U, // PseudoVLUXSEG7EI64_V_M2_MF4_MASK + 10U, // PseudoVLUXSEG7EI64_V_M4_M1 + 10U, // PseudoVLUXSEG7EI64_V_M4_M1_MASK + 10U, // PseudoVLUXSEG7EI64_V_M4_MF2 + 10U, // PseudoVLUXSEG7EI64_V_M4_MF2_MASK + 10U, // PseudoVLUXSEG7EI64_V_M8_M1 + 10U, // PseudoVLUXSEG7EI64_V_M8_M1_MASK + 10U, // PseudoVLUXSEG7EI8_V_M1_M1 + 10U, // PseudoVLUXSEG7EI8_V_M1_M1_MASK + 10U, // PseudoVLUXSEG7EI8_V_MF2_M1 + 10U, // PseudoVLUXSEG7EI8_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG7EI8_V_MF2_MF2 + 10U, // PseudoVLUXSEG7EI8_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG7EI8_V_MF4_M1 + 10U, // PseudoVLUXSEG7EI8_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG7EI8_V_MF4_MF2 + 10U, // PseudoVLUXSEG7EI8_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG7EI8_V_MF4_MF4 + 10U, // PseudoVLUXSEG7EI8_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG7EI8_V_MF8_M1 + 10U, // PseudoVLUXSEG7EI8_V_MF8_M1_MASK + 10U, // PseudoVLUXSEG7EI8_V_MF8_MF2 + 10U, // PseudoVLUXSEG7EI8_V_MF8_MF2_MASK + 10U, // PseudoVLUXSEG7EI8_V_MF8_MF4 + 10U, // PseudoVLUXSEG7EI8_V_MF8_MF4_MASK + 10U, // PseudoVLUXSEG7EI8_V_MF8_MF8 + 10U, // PseudoVLUXSEG7EI8_V_MF8_MF8_MASK + 10U, // PseudoVLUXSEG8EI16_V_M1_M1 + 10U, // PseudoVLUXSEG8EI16_V_M1_M1_MASK + 10U, // PseudoVLUXSEG8EI16_V_M1_MF2 + 10U, // PseudoVLUXSEG8EI16_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG8EI16_V_M2_M1 + 10U, // PseudoVLUXSEG8EI16_V_M2_M1_MASK + 10U, // PseudoVLUXSEG8EI16_V_MF2_M1 + 10U, // PseudoVLUXSEG8EI16_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG8EI16_V_MF2_MF2 + 10U, // PseudoVLUXSEG8EI16_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG8EI16_V_MF2_MF4 + 10U, // PseudoVLUXSEG8EI16_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG8EI16_V_MF4_M1 + 10U, // PseudoVLUXSEG8EI16_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG8EI16_V_MF4_MF2 + 10U, // PseudoVLUXSEG8EI16_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG8EI16_V_MF4_MF4 + 10U, // PseudoVLUXSEG8EI16_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG8EI16_V_MF4_MF8 + 10U, // PseudoVLUXSEG8EI16_V_MF4_MF8_MASK + 10U, // PseudoVLUXSEG8EI32_V_M1_M1 + 10U, // PseudoVLUXSEG8EI32_V_M1_M1_MASK + 10U, // PseudoVLUXSEG8EI32_V_M1_MF2 + 10U, // PseudoVLUXSEG8EI32_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG8EI32_V_M1_MF4 + 10U, // PseudoVLUXSEG8EI32_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG8EI32_V_M2_M1 + 10U, // PseudoVLUXSEG8EI32_V_M2_M1_MASK + 10U, // PseudoVLUXSEG8EI32_V_M2_MF2 + 10U, // PseudoVLUXSEG8EI32_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG8EI32_V_M4_M1 + 10U, // PseudoVLUXSEG8EI32_V_M4_M1_MASK + 10U, // PseudoVLUXSEG8EI32_V_MF2_M1 + 10U, // PseudoVLUXSEG8EI32_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG8EI32_V_MF2_MF2 + 10U, // PseudoVLUXSEG8EI32_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG8EI32_V_MF2_MF4 + 10U, // PseudoVLUXSEG8EI32_V_MF2_MF4_MASK + 10U, // PseudoVLUXSEG8EI32_V_MF2_MF8 + 10U, // PseudoVLUXSEG8EI32_V_MF2_MF8_MASK + 10U, // PseudoVLUXSEG8EI64_V_M1_M1 + 10U, // PseudoVLUXSEG8EI64_V_M1_M1_MASK + 10U, // PseudoVLUXSEG8EI64_V_M1_MF2 + 10U, // PseudoVLUXSEG8EI64_V_M1_MF2_MASK + 10U, // PseudoVLUXSEG8EI64_V_M1_MF4 + 10U, // PseudoVLUXSEG8EI64_V_M1_MF4_MASK + 10U, // PseudoVLUXSEG8EI64_V_M1_MF8 + 10U, // PseudoVLUXSEG8EI64_V_M1_MF8_MASK + 10U, // PseudoVLUXSEG8EI64_V_M2_M1 + 10U, // PseudoVLUXSEG8EI64_V_M2_M1_MASK + 10U, // PseudoVLUXSEG8EI64_V_M2_MF2 + 10U, // PseudoVLUXSEG8EI64_V_M2_MF2_MASK + 10U, // PseudoVLUXSEG8EI64_V_M2_MF4 + 10U, // PseudoVLUXSEG8EI64_V_M2_MF4_MASK + 10U, // PseudoVLUXSEG8EI64_V_M4_M1 + 10U, // PseudoVLUXSEG8EI64_V_M4_M1_MASK + 10U, // PseudoVLUXSEG8EI64_V_M4_MF2 + 10U, // PseudoVLUXSEG8EI64_V_M4_MF2_MASK + 10U, // PseudoVLUXSEG8EI64_V_M8_M1 + 10U, // PseudoVLUXSEG8EI64_V_M8_M1_MASK + 10U, // PseudoVLUXSEG8EI8_V_M1_M1 + 10U, // PseudoVLUXSEG8EI8_V_M1_M1_MASK + 10U, // PseudoVLUXSEG8EI8_V_MF2_M1 + 10U, // PseudoVLUXSEG8EI8_V_MF2_M1_MASK + 10U, // PseudoVLUXSEG8EI8_V_MF2_MF2 + 10U, // PseudoVLUXSEG8EI8_V_MF2_MF2_MASK + 10U, // PseudoVLUXSEG8EI8_V_MF4_M1 + 10U, // PseudoVLUXSEG8EI8_V_MF4_M1_MASK + 10U, // PseudoVLUXSEG8EI8_V_MF4_MF2 + 10U, // PseudoVLUXSEG8EI8_V_MF4_MF2_MASK + 10U, // PseudoVLUXSEG8EI8_V_MF4_MF4 + 10U, // PseudoVLUXSEG8EI8_V_MF4_MF4_MASK + 10U, // PseudoVLUXSEG8EI8_V_MF8_M1 + 10U, // PseudoVLUXSEG8EI8_V_MF8_M1_MASK + 10U, // PseudoVLUXSEG8EI8_V_MF8_MF2 + 10U, // PseudoVLUXSEG8EI8_V_MF8_MF2_MASK + 10U, // PseudoVLUXSEG8EI8_V_MF8_MF4 + 10U, // PseudoVLUXSEG8EI8_V_MF8_MF4_MASK + 10U, // PseudoVLUXSEG8EI8_V_MF8_MF8 + 10U, // PseudoVLUXSEG8EI8_V_MF8_MF8_MASK + 10U, // PseudoVMACC_VV_M1 + 10U, // PseudoVMACC_VV_M1_MASK + 10U, // PseudoVMACC_VV_M2 + 10U, // PseudoVMACC_VV_M2_MASK + 10U, // PseudoVMACC_VV_M4 + 10U, // PseudoVMACC_VV_M4_MASK + 10U, // PseudoVMACC_VV_M8 + 10U, // PseudoVMACC_VV_M8_MASK + 10U, // PseudoVMACC_VV_MF2 + 10U, // PseudoVMACC_VV_MF2_MASK + 10U, // PseudoVMACC_VV_MF4 + 10U, // PseudoVMACC_VV_MF4_MASK + 10U, // PseudoVMACC_VV_MF8 + 10U, // PseudoVMACC_VV_MF8_MASK + 10U, // PseudoVMACC_VX_M1 + 10U, // PseudoVMACC_VX_M1_MASK + 10U, // PseudoVMACC_VX_M2 + 10U, // PseudoVMACC_VX_M2_MASK + 10U, // PseudoVMACC_VX_M4 + 10U, // PseudoVMACC_VX_M4_MASK + 10U, // PseudoVMACC_VX_M8 + 10U, // PseudoVMACC_VX_M8_MASK + 10U, // PseudoVMACC_VX_MF2 + 10U, // PseudoVMACC_VX_MF2_MASK + 10U, // PseudoVMACC_VX_MF4 + 10U, // PseudoVMACC_VX_MF4_MASK + 10U, // PseudoVMACC_VX_MF8 + 10U, // PseudoVMACC_VX_MF8_MASK + 10U, // PseudoVMADC_VIM_M1 + 10U, // PseudoVMADC_VIM_M2 + 10U, // PseudoVMADC_VIM_M4 + 10U, // PseudoVMADC_VIM_M8 + 10U, // PseudoVMADC_VIM_MF2 + 10U, // PseudoVMADC_VIM_MF4 + 10U, // PseudoVMADC_VIM_MF8 + 10U, // PseudoVMADC_VI_M1 + 10U, // PseudoVMADC_VI_M2 + 10U, // PseudoVMADC_VI_M4 + 10U, // PseudoVMADC_VI_M8 + 10U, // PseudoVMADC_VI_MF2 + 10U, // PseudoVMADC_VI_MF4 + 10U, // PseudoVMADC_VI_MF8 + 10U, // PseudoVMADC_VVM_M1 + 10U, // PseudoVMADC_VVM_M2 + 10U, // PseudoVMADC_VVM_M4 + 10U, // PseudoVMADC_VVM_M8 + 10U, // PseudoVMADC_VVM_MF2 + 10U, // PseudoVMADC_VVM_MF4 + 10U, // PseudoVMADC_VVM_MF8 + 10U, // PseudoVMADC_VV_M1 + 10U, // PseudoVMADC_VV_M2 + 10U, // PseudoVMADC_VV_M4 + 10U, // PseudoVMADC_VV_M8 + 10U, // PseudoVMADC_VV_MF2 + 10U, // PseudoVMADC_VV_MF4 + 10U, // PseudoVMADC_VV_MF8 + 10U, // PseudoVMADC_VXM_M1 + 10U, // PseudoVMADC_VXM_M2 + 10U, // PseudoVMADC_VXM_M4 + 10U, // PseudoVMADC_VXM_M8 + 10U, // PseudoVMADC_VXM_MF2 + 10U, // PseudoVMADC_VXM_MF4 + 10U, // PseudoVMADC_VXM_MF8 + 10U, // PseudoVMADC_VX_M1 + 10U, // PseudoVMADC_VX_M2 + 10U, // PseudoVMADC_VX_M4 + 10U, // PseudoVMADC_VX_M8 + 10U, // PseudoVMADC_VX_MF2 + 10U, // PseudoVMADC_VX_MF4 + 10U, // PseudoVMADC_VX_MF8 + 10U, // PseudoVMADD_VV_M1 + 10U, // PseudoVMADD_VV_M1_MASK + 10U, // PseudoVMADD_VV_M2 + 10U, // PseudoVMADD_VV_M2_MASK + 10U, // PseudoVMADD_VV_M4 + 10U, // PseudoVMADD_VV_M4_MASK + 10U, // PseudoVMADD_VV_M8 + 10U, // PseudoVMADD_VV_M8_MASK + 10U, // PseudoVMADD_VV_MF2 + 10U, // PseudoVMADD_VV_MF2_MASK + 10U, // PseudoVMADD_VV_MF4 + 10U, // PseudoVMADD_VV_MF4_MASK + 10U, // PseudoVMADD_VV_MF8 + 10U, // PseudoVMADD_VV_MF8_MASK + 10U, // PseudoVMADD_VX_M1 + 10U, // PseudoVMADD_VX_M1_MASK + 10U, // PseudoVMADD_VX_M2 + 10U, // PseudoVMADD_VX_M2_MASK + 10U, // PseudoVMADD_VX_M4 + 10U, // PseudoVMADD_VX_M4_MASK + 10U, // PseudoVMADD_VX_M8 + 10U, // PseudoVMADD_VX_M8_MASK + 10U, // PseudoVMADD_VX_MF2 + 10U, // PseudoVMADD_VX_MF2_MASK + 10U, // PseudoVMADD_VX_MF4 + 10U, // PseudoVMADD_VX_MF4_MASK + 10U, // PseudoVMADD_VX_MF8 + 10U, // PseudoVMADD_VX_MF8_MASK + 10U, // PseudoVMANDN_MM_M1 + 10U, // PseudoVMANDN_MM_M2 + 10U, // PseudoVMANDN_MM_M4 + 10U, // PseudoVMANDN_MM_M8 + 10U, // PseudoVMANDN_MM_MF2 + 10U, // PseudoVMANDN_MM_MF4 + 10U, // PseudoVMANDN_MM_MF8 + 10U, // PseudoVMAND_MM_M1 + 10U, // PseudoVMAND_MM_M2 + 10U, // PseudoVMAND_MM_M4 + 10U, // PseudoVMAND_MM_M8 + 10U, // PseudoVMAND_MM_MF2 + 10U, // PseudoVMAND_MM_MF4 + 10U, // PseudoVMAND_MM_MF8 + 10U, // PseudoVMAXU_VV_M1 + 10U, // PseudoVMAXU_VV_M1_MASK + 10U, // PseudoVMAXU_VV_M2 + 10U, // PseudoVMAXU_VV_M2_MASK + 10U, // PseudoVMAXU_VV_M4 + 10U, // PseudoVMAXU_VV_M4_MASK + 10U, // PseudoVMAXU_VV_M8 + 10U, // PseudoVMAXU_VV_M8_MASK + 10U, // PseudoVMAXU_VV_MF2 + 10U, // PseudoVMAXU_VV_MF2_MASK + 10U, // PseudoVMAXU_VV_MF4 + 10U, // PseudoVMAXU_VV_MF4_MASK + 10U, // PseudoVMAXU_VV_MF8 + 10U, // PseudoVMAXU_VV_MF8_MASK + 10U, // PseudoVMAXU_VX_M1 + 10U, // PseudoVMAXU_VX_M1_MASK + 10U, // PseudoVMAXU_VX_M2 + 10U, // PseudoVMAXU_VX_M2_MASK + 10U, // PseudoVMAXU_VX_M4 + 10U, // PseudoVMAXU_VX_M4_MASK + 10U, // PseudoVMAXU_VX_M8 + 10U, // PseudoVMAXU_VX_M8_MASK + 10U, // PseudoVMAXU_VX_MF2 + 10U, // PseudoVMAXU_VX_MF2_MASK + 10U, // PseudoVMAXU_VX_MF4 + 10U, // PseudoVMAXU_VX_MF4_MASK + 10U, // PseudoVMAXU_VX_MF8 + 10U, // PseudoVMAXU_VX_MF8_MASK + 10U, // PseudoVMAX_VV_M1 + 10U, // PseudoVMAX_VV_M1_MASK + 10U, // PseudoVMAX_VV_M2 + 10U, // PseudoVMAX_VV_M2_MASK + 10U, // PseudoVMAX_VV_M4 + 10U, // PseudoVMAX_VV_M4_MASK + 10U, // PseudoVMAX_VV_M8 + 10U, // PseudoVMAX_VV_M8_MASK + 10U, // PseudoVMAX_VV_MF2 + 10U, // PseudoVMAX_VV_MF2_MASK + 10U, // PseudoVMAX_VV_MF4 + 10U, // PseudoVMAX_VV_MF4_MASK + 10U, // PseudoVMAX_VV_MF8 + 10U, // PseudoVMAX_VV_MF8_MASK + 10U, // PseudoVMAX_VX_M1 + 10U, // PseudoVMAX_VX_M1_MASK + 10U, // PseudoVMAX_VX_M2 + 10U, // PseudoVMAX_VX_M2_MASK + 10U, // PseudoVMAX_VX_M4 + 10U, // PseudoVMAX_VX_M4_MASK + 10U, // PseudoVMAX_VX_M8 + 10U, // PseudoVMAX_VX_M8_MASK + 10U, // PseudoVMAX_VX_MF2 + 10U, // PseudoVMAX_VX_MF2_MASK + 10U, // PseudoVMAX_VX_MF4 + 10U, // PseudoVMAX_VX_MF4_MASK + 10U, // PseudoVMAX_VX_MF8 + 10U, // PseudoVMAX_VX_MF8_MASK + 10U, // PseudoVMCLR_M_B1 + 10U, // PseudoVMCLR_M_B16 + 10U, // PseudoVMCLR_M_B2 + 10U, // PseudoVMCLR_M_B32 + 10U, // PseudoVMCLR_M_B4 + 10U, // PseudoVMCLR_M_B64 + 10U, // PseudoVMCLR_M_B8 + 10U, // PseudoVMERGE_VIM_M1 + 10U, // PseudoVMERGE_VIM_M2 + 10U, // PseudoVMERGE_VIM_M4 + 10U, // PseudoVMERGE_VIM_M8 + 10U, // PseudoVMERGE_VIM_MF2 + 10U, // PseudoVMERGE_VIM_MF4 + 10U, // PseudoVMERGE_VIM_MF8 + 10U, // PseudoVMERGE_VVM_M1 + 10U, // PseudoVMERGE_VVM_M2 + 10U, // PseudoVMERGE_VVM_M4 + 10U, // PseudoVMERGE_VVM_M8 + 10U, // PseudoVMERGE_VVM_MF2 + 10U, // PseudoVMERGE_VVM_MF4 + 10U, // PseudoVMERGE_VVM_MF8 + 10U, // PseudoVMERGE_VXM_M1 + 10U, // PseudoVMERGE_VXM_M2 + 10U, // PseudoVMERGE_VXM_M4 + 10U, // PseudoVMERGE_VXM_M8 + 10U, // PseudoVMERGE_VXM_MF2 + 10U, // PseudoVMERGE_VXM_MF4 + 10U, // PseudoVMERGE_VXM_MF8 + 10U, // PseudoVMFEQ_VF16_M1 + 10U, // PseudoVMFEQ_VF16_M1_MASK + 10U, // PseudoVMFEQ_VF16_M2 + 10U, // PseudoVMFEQ_VF16_M2_MASK + 10U, // PseudoVMFEQ_VF16_M4 + 10U, // PseudoVMFEQ_VF16_M4_MASK + 10U, // PseudoVMFEQ_VF16_M8 + 10U, // PseudoVMFEQ_VF16_M8_MASK + 10U, // PseudoVMFEQ_VF16_MF2 + 10U, // PseudoVMFEQ_VF16_MF2_MASK + 10U, // PseudoVMFEQ_VF16_MF4 + 10U, // PseudoVMFEQ_VF16_MF4_MASK + 10U, // PseudoVMFEQ_VF16_MF8 + 10U, // PseudoVMFEQ_VF16_MF8_MASK + 10U, // PseudoVMFEQ_VF32_M1 + 10U, // PseudoVMFEQ_VF32_M1_MASK + 10U, // PseudoVMFEQ_VF32_M2 + 10U, // PseudoVMFEQ_VF32_M2_MASK + 10U, // PseudoVMFEQ_VF32_M4 + 10U, // PseudoVMFEQ_VF32_M4_MASK + 10U, // PseudoVMFEQ_VF32_M8 + 10U, // PseudoVMFEQ_VF32_M8_MASK + 10U, // PseudoVMFEQ_VF32_MF2 + 10U, // PseudoVMFEQ_VF32_MF2_MASK + 10U, // PseudoVMFEQ_VF32_MF4 + 10U, // PseudoVMFEQ_VF32_MF4_MASK + 10U, // PseudoVMFEQ_VF32_MF8 + 10U, // PseudoVMFEQ_VF32_MF8_MASK + 10U, // PseudoVMFEQ_VF64_M1 + 10U, // PseudoVMFEQ_VF64_M1_MASK + 10U, // PseudoVMFEQ_VF64_M2 + 10U, // PseudoVMFEQ_VF64_M2_MASK + 10U, // PseudoVMFEQ_VF64_M4 + 10U, // PseudoVMFEQ_VF64_M4_MASK + 10U, // PseudoVMFEQ_VF64_M8 + 10U, // PseudoVMFEQ_VF64_M8_MASK + 10U, // PseudoVMFEQ_VF64_MF2 + 10U, // PseudoVMFEQ_VF64_MF2_MASK + 10U, // PseudoVMFEQ_VF64_MF4 + 10U, // PseudoVMFEQ_VF64_MF4_MASK + 10U, // PseudoVMFEQ_VF64_MF8 + 10U, // PseudoVMFEQ_VF64_MF8_MASK + 10U, // PseudoVMFEQ_VV_M1 + 10U, // PseudoVMFEQ_VV_M1_MASK + 10U, // PseudoVMFEQ_VV_M2 + 10U, // PseudoVMFEQ_VV_M2_MASK + 10U, // PseudoVMFEQ_VV_M4 + 10U, // PseudoVMFEQ_VV_M4_MASK + 10U, // PseudoVMFEQ_VV_M8 + 10U, // PseudoVMFEQ_VV_M8_MASK + 10U, // PseudoVMFEQ_VV_MF2 + 10U, // PseudoVMFEQ_VV_MF2_MASK + 10U, // PseudoVMFEQ_VV_MF4 + 10U, // PseudoVMFEQ_VV_MF4_MASK + 10U, // PseudoVMFEQ_VV_MF8 + 10U, // PseudoVMFEQ_VV_MF8_MASK + 10U, // PseudoVMFGE_VF16_M1 + 10U, // PseudoVMFGE_VF16_M1_MASK + 10U, // PseudoVMFGE_VF16_M2 + 10U, // PseudoVMFGE_VF16_M2_MASK + 10U, // PseudoVMFGE_VF16_M4 + 10U, // PseudoVMFGE_VF16_M4_MASK + 10U, // PseudoVMFGE_VF16_M8 + 10U, // PseudoVMFGE_VF16_M8_MASK + 10U, // PseudoVMFGE_VF16_MF2 + 10U, // PseudoVMFGE_VF16_MF2_MASK + 10U, // PseudoVMFGE_VF16_MF4 + 10U, // PseudoVMFGE_VF16_MF4_MASK + 10U, // PseudoVMFGE_VF16_MF8 + 10U, // PseudoVMFGE_VF16_MF8_MASK + 10U, // PseudoVMFGE_VF32_M1 + 10U, // PseudoVMFGE_VF32_M1_MASK + 10U, // PseudoVMFGE_VF32_M2 + 10U, // PseudoVMFGE_VF32_M2_MASK + 10U, // PseudoVMFGE_VF32_M4 + 10U, // PseudoVMFGE_VF32_M4_MASK + 10U, // PseudoVMFGE_VF32_M8 + 10U, // PseudoVMFGE_VF32_M8_MASK + 10U, // PseudoVMFGE_VF32_MF2 + 10U, // PseudoVMFGE_VF32_MF2_MASK + 10U, // PseudoVMFGE_VF32_MF4 + 10U, // PseudoVMFGE_VF32_MF4_MASK + 10U, // PseudoVMFGE_VF32_MF8 + 10U, // PseudoVMFGE_VF32_MF8_MASK + 10U, // PseudoVMFGE_VF64_M1 + 10U, // PseudoVMFGE_VF64_M1_MASK + 10U, // PseudoVMFGE_VF64_M2 + 10U, // PseudoVMFGE_VF64_M2_MASK + 10U, // PseudoVMFGE_VF64_M4 + 10U, // PseudoVMFGE_VF64_M4_MASK + 10U, // PseudoVMFGE_VF64_M8 + 10U, // PseudoVMFGE_VF64_M8_MASK + 10U, // PseudoVMFGE_VF64_MF2 + 10U, // PseudoVMFGE_VF64_MF2_MASK + 10U, // PseudoVMFGE_VF64_MF4 + 10U, // PseudoVMFGE_VF64_MF4_MASK + 10U, // PseudoVMFGE_VF64_MF8 + 10U, // PseudoVMFGE_VF64_MF8_MASK + 10U, // PseudoVMFGT_VF16_M1 + 10U, // PseudoVMFGT_VF16_M1_MASK + 10U, // PseudoVMFGT_VF16_M2 + 10U, // PseudoVMFGT_VF16_M2_MASK + 10U, // PseudoVMFGT_VF16_M4 + 10U, // PseudoVMFGT_VF16_M4_MASK + 10U, // PseudoVMFGT_VF16_M8 + 10U, // PseudoVMFGT_VF16_M8_MASK + 10U, // PseudoVMFGT_VF16_MF2 + 10U, // PseudoVMFGT_VF16_MF2_MASK + 10U, // PseudoVMFGT_VF16_MF4 + 10U, // PseudoVMFGT_VF16_MF4_MASK + 10U, // PseudoVMFGT_VF16_MF8 + 10U, // PseudoVMFGT_VF16_MF8_MASK + 10U, // PseudoVMFGT_VF32_M1 + 10U, // PseudoVMFGT_VF32_M1_MASK + 10U, // PseudoVMFGT_VF32_M2 + 10U, // PseudoVMFGT_VF32_M2_MASK + 10U, // PseudoVMFGT_VF32_M4 + 10U, // PseudoVMFGT_VF32_M4_MASK + 10U, // PseudoVMFGT_VF32_M8 + 10U, // PseudoVMFGT_VF32_M8_MASK + 10U, // PseudoVMFGT_VF32_MF2 + 10U, // PseudoVMFGT_VF32_MF2_MASK + 10U, // PseudoVMFGT_VF32_MF4 + 10U, // PseudoVMFGT_VF32_MF4_MASK + 10U, // PseudoVMFGT_VF32_MF8 + 10U, // PseudoVMFGT_VF32_MF8_MASK + 10U, // PseudoVMFGT_VF64_M1 + 10U, // PseudoVMFGT_VF64_M1_MASK + 10U, // PseudoVMFGT_VF64_M2 + 10U, // PseudoVMFGT_VF64_M2_MASK + 10U, // PseudoVMFGT_VF64_M4 + 10U, // PseudoVMFGT_VF64_M4_MASK + 10U, // PseudoVMFGT_VF64_M8 + 10U, // PseudoVMFGT_VF64_M8_MASK + 10U, // PseudoVMFGT_VF64_MF2 + 10U, // PseudoVMFGT_VF64_MF2_MASK + 10U, // PseudoVMFGT_VF64_MF4 + 10U, // PseudoVMFGT_VF64_MF4_MASK + 10U, // PseudoVMFGT_VF64_MF8 + 10U, // PseudoVMFGT_VF64_MF8_MASK + 10U, // PseudoVMFLE_VF16_M1 + 10U, // PseudoVMFLE_VF16_M1_MASK + 10U, // PseudoVMFLE_VF16_M2 + 10U, // PseudoVMFLE_VF16_M2_MASK + 10U, // PseudoVMFLE_VF16_M4 + 10U, // PseudoVMFLE_VF16_M4_MASK + 10U, // PseudoVMFLE_VF16_M8 + 10U, // PseudoVMFLE_VF16_M8_MASK + 10U, // PseudoVMFLE_VF16_MF2 + 10U, // PseudoVMFLE_VF16_MF2_MASK + 10U, // PseudoVMFLE_VF16_MF4 + 10U, // PseudoVMFLE_VF16_MF4_MASK + 10U, // PseudoVMFLE_VF16_MF8 + 10U, // PseudoVMFLE_VF16_MF8_MASK + 10U, // PseudoVMFLE_VF32_M1 + 10U, // PseudoVMFLE_VF32_M1_MASK + 10U, // PseudoVMFLE_VF32_M2 + 10U, // PseudoVMFLE_VF32_M2_MASK + 10U, // PseudoVMFLE_VF32_M4 + 10U, // PseudoVMFLE_VF32_M4_MASK + 10U, // PseudoVMFLE_VF32_M8 + 10U, // PseudoVMFLE_VF32_M8_MASK + 10U, // PseudoVMFLE_VF32_MF2 + 10U, // PseudoVMFLE_VF32_MF2_MASK + 10U, // PseudoVMFLE_VF32_MF4 + 10U, // PseudoVMFLE_VF32_MF4_MASK + 10U, // PseudoVMFLE_VF32_MF8 + 10U, // PseudoVMFLE_VF32_MF8_MASK + 10U, // PseudoVMFLE_VF64_M1 + 10U, // PseudoVMFLE_VF64_M1_MASK + 10U, // PseudoVMFLE_VF64_M2 + 10U, // PseudoVMFLE_VF64_M2_MASK + 10U, // PseudoVMFLE_VF64_M4 + 10U, // PseudoVMFLE_VF64_M4_MASK + 10U, // PseudoVMFLE_VF64_M8 + 10U, // PseudoVMFLE_VF64_M8_MASK + 10U, // PseudoVMFLE_VF64_MF2 + 10U, // PseudoVMFLE_VF64_MF2_MASK + 10U, // PseudoVMFLE_VF64_MF4 + 10U, // PseudoVMFLE_VF64_MF4_MASK + 10U, // PseudoVMFLE_VF64_MF8 + 10U, // PseudoVMFLE_VF64_MF8_MASK + 10U, // PseudoVMFLE_VV_M1 + 10U, // PseudoVMFLE_VV_M1_MASK + 10U, // PseudoVMFLE_VV_M2 + 10U, // PseudoVMFLE_VV_M2_MASK + 10U, // PseudoVMFLE_VV_M4 + 10U, // PseudoVMFLE_VV_M4_MASK + 10U, // PseudoVMFLE_VV_M8 + 10U, // PseudoVMFLE_VV_M8_MASK + 10U, // PseudoVMFLE_VV_MF2 + 10U, // PseudoVMFLE_VV_MF2_MASK + 10U, // PseudoVMFLE_VV_MF4 + 10U, // PseudoVMFLE_VV_MF4_MASK + 10U, // PseudoVMFLE_VV_MF8 + 10U, // PseudoVMFLE_VV_MF8_MASK + 10U, // PseudoVMFLT_VF16_M1 + 10U, // PseudoVMFLT_VF16_M1_MASK + 10U, // PseudoVMFLT_VF16_M2 + 10U, // PseudoVMFLT_VF16_M2_MASK + 10U, // PseudoVMFLT_VF16_M4 + 10U, // PseudoVMFLT_VF16_M4_MASK + 10U, // PseudoVMFLT_VF16_M8 + 10U, // PseudoVMFLT_VF16_M8_MASK + 10U, // PseudoVMFLT_VF16_MF2 + 10U, // PseudoVMFLT_VF16_MF2_MASK + 10U, // PseudoVMFLT_VF16_MF4 + 10U, // PseudoVMFLT_VF16_MF4_MASK + 10U, // PseudoVMFLT_VF16_MF8 + 10U, // PseudoVMFLT_VF16_MF8_MASK + 10U, // PseudoVMFLT_VF32_M1 + 10U, // PseudoVMFLT_VF32_M1_MASK + 10U, // PseudoVMFLT_VF32_M2 + 10U, // PseudoVMFLT_VF32_M2_MASK + 10U, // PseudoVMFLT_VF32_M4 + 10U, // PseudoVMFLT_VF32_M4_MASK + 10U, // PseudoVMFLT_VF32_M8 + 10U, // PseudoVMFLT_VF32_M8_MASK + 10U, // PseudoVMFLT_VF32_MF2 + 10U, // PseudoVMFLT_VF32_MF2_MASK + 10U, // PseudoVMFLT_VF32_MF4 + 10U, // PseudoVMFLT_VF32_MF4_MASK + 10U, // PseudoVMFLT_VF32_MF8 + 10U, // PseudoVMFLT_VF32_MF8_MASK + 10U, // PseudoVMFLT_VF64_M1 + 10U, // PseudoVMFLT_VF64_M1_MASK + 10U, // PseudoVMFLT_VF64_M2 + 10U, // PseudoVMFLT_VF64_M2_MASK + 10U, // PseudoVMFLT_VF64_M4 + 10U, // PseudoVMFLT_VF64_M4_MASK + 10U, // PseudoVMFLT_VF64_M8 + 10U, // PseudoVMFLT_VF64_M8_MASK + 10U, // PseudoVMFLT_VF64_MF2 + 10U, // PseudoVMFLT_VF64_MF2_MASK + 10U, // PseudoVMFLT_VF64_MF4 + 10U, // PseudoVMFLT_VF64_MF4_MASK + 10U, // PseudoVMFLT_VF64_MF8 + 10U, // PseudoVMFLT_VF64_MF8_MASK + 10U, // PseudoVMFLT_VV_M1 + 10U, // PseudoVMFLT_VV_M1_MASK + 10U, // PseudoVMFLT_VV_M2 + 10U, // PseudoVMFLT_VV_M2_MASK + 10U, // PseudoVMFLT_VV_M4 + 10U, // PseudoVMFLT_VV_M4_MASK + 10U, // PseudoVMFLT_VV_M8 + 10U, // PseudoVMFLT_VV_M8_MASK + 10U, // PseudoVMFLT_VV_MF2 + 10U, // PseudoVMFLT_VV_MF2_MASK + 10U, // PseudoVMFLT_VV_MF4 + 10U, // PseudoVMFLT_VV_MF4_MASK + 10U, // PseudoVMFLT_VV_MF8 + 10U, // PseudoVMFLT_VV_MF8_MASK + 10U, // PseudoVMFNE_VF16_M1 + 10U, // PseudoVMFNE_VF16_M1_MASK + 10U, // PseudoVMFNE_VF16_M2 + 10U, // PseudoVMFNE_VF16_M2_MASK + 10U, // PseudoVMFNE_VF16_M4 + 10U, // PseudoVMFNE_VF16_M4_MASK + 10U, // PseudoVMFNE_VF16_M8 + 10U, // PseudoVMFNE_VF16_M8_MASK + 10U, // PseudoVMFNE_VF16_MF2 + 10U, // PseudoVMFNE_VF16_MF2_MASK + 10U, // PseudoVMFNE_VF16_MF4 + 10U, // PseudoVMFNE_VF16_MF4_MASK + 10U, // PseudoVMFNE_VF16_MF8 + 10U, // PseudoVMFNE_VF16_MF8_MASK + 10U, // PseudoVMFNE_VF32_M1 + 10U, // PseudoVMFNE_VF32_M1_MASK + 10U, // PseudoVMFNE_VF32_M2 + 10U, // PseudoVMFNE_VF32_M2_MASK + 10U, // PseudoVMFNE_VF32_M4 + 10U, // PseudoVMFNE_VF32_M4_MASK + 10U, // PseudoVMFNE_VF32_M8 + 10U, // PseudoVMFNE_VF32_M8_MASK + 10U, // PseudoVMFNE_VF32_MF2 + 10U, // PseudoVMFNE_VF32_MF2_MASK + 10U, // PseudoVMFNE_VF32_MF4 + 10U, // PseudoVMFNE_VF32_MF4_MASK + 10U, // PseudoVMFNE_VF32_MF8 + 10U, // PseudoVMFNE_VF32_MF8_MASK + 10U, // PseudoVMFNE_VF64_M1 + 10U, // PseudoVMFNE_VF64_M1_MASK + 10U, // PseudoVMFNE_VF64_M2 + 10U, // PseudoVMFNE_VF64_M2_MASK + 10U, // PseudoVMFNE_VF64_M4 + 10U, // PseudoVMFNE_VF64_M4_MASK + 10U, // PseudoVMFNE_VF64_M8 + 10U, // PseudoVMFNE_VF64_M8_MASK + 10U, // PseudoVMFNE_VF64_MF2 + 10U, // PseudoVMFNE_VF64_MF2_MASK + 10U, // PseudoVMFNE_VF64_MF4 + 10U, // PseudoVMFNE_VF64_MF4_MASK + 10U, // PseudoVMFNE_VF64_MF8 + 10U, // PseudoVMFNE_VF64_MF8_MASK + 10U, // PseudoVMFNE_VV_M1 + 10U, // PseudoVMFNE_VV_M1_MASK + 10U, // PseudoVMFNE_VV_M2 + 10U, // PseudoVMFNE_VV_M2_MASK + 10U, // PseudoVMFNE_VV_M4 + 10U, // PseudoVMFNE_VV_M4_MASK + 10U, // PseudoVMFNE_VV_M8 + 10U, // PseudoVMFNE_VV_M8_MASK + 10U, // PseudoVMFNE_VV_MF2 + 10U, // PseudoVMFNE_VV_MF2_MASK + 10U, // PseudoVMFNE_VV_MF4 + 10U, // PseudoVMFNE_VV_MF4_MASK + 10U, // PseudoVMFNE_VV_MF8 + 10U, // PseudoVMFNE_VV_MF8_MASK + 10U, // PseudoVMINU_VV_M1 + 10U, // PseudoVMINU_VV_M1_MASK + 10U, // PseudoVMINU_VV_M2 + 10U, // PseudoVMINU_VV_M2_MASK + 10U, // PseudoVMINU_VV_M4 + 10U, // PseudoVMINU_VV_M4_MASK + 10U, // PseudoVMINU_VV_M8 + 10U, // PseudoVMINU_VV_M8_MASK + 10U, // PseudoVMINU_VV_MF2 + 10U, // PseudoVMINU_VV_MF2_MASK + 10U, // PseudoVMINU_VV_MF4 + 10U, // PseudoVMINU_VV_MF4_MASK + 10U, // PseudoVMINU_VV_MF8 + 10U, // PseudoVMINU_VV_MF8_MASK + 10U, // PseudoVMINU_VX_M1 + 10U, // PseudoVMINU_VX_M1_MASK + 10U, // PseudoVMINU_VX_M2 + 10U, // PseudoVMINU_VX_M2_MASK + 10U, // PseudoVMINU_VX_M4 + 10U, // PseudoVMINU_VX_M4_MASK + 10U, // PseudoVMINU_VX_M8 + 10U, // PseudoVMINU_VX_M8_MASK + 10U, // PseudoVMINU_VX_MF2 + 10U, // PseudoVMINU_VX_MF2_MASK + 10U, // PseudoVMINU_VX_MF4 + 10U, // PseudoVMINU_VX_MF4_MASK + 10U, // PseudoVMINU_VX_MF8 + 10U, // PseudoVMINU_VX_MF8_MASK + 10U, // PseudoVMIN_VV_M1 + 10U, // PseudoVMIN_VV_M1_MASK + 10U, // PseudoVMIN_VV_M2 + 10U, // PseudoVMIN_VV_M2_MASK + 10U, // PseudoVMIN_VV_M4 + 10U, // PseudoVMIN_VV_M4_MASK + 10U, // PseudoVMIN_VV_M8 + 10U, // PseudoVMIN_VV_M8_MASK + 10U, // PseudoVMIN_VV_MF2 + 10U, // PseudoVMIN_VV_MF2_MASK + 10U, // PseudoVMIN_VV_MF4 + 10U, // PseudoVMIN_VV_MF4_MASK + 10U, // PseudoVMIN_VV_MF8 + 10U, // PseudoVMIN_VV_MF8_MASK + 10U, // PseudoVMIN_VX_M1 + 10U, // PseudoVMIN_VX_M1_MASK + 10U, // PseudoVMIN_VX_M2 + 10U, // PseudoVMIN_VX_M2_MASK + 10U, // PseudoVMIN_VX_M4 + 10U, // PseudoVMIN_VX_M4_MASK + 10U, // PseudoVMIN_VX_M8 + 10U, // PseudoVMIN_VX_M8_MASK + 10U, // PseudoVMIN_VX_MF2 + 10U, // PseudoVMIN_VX_MF2_MASK + 10U, // PseudoVMIN_VX_MF4 + 10U, // PseudoVMIN_VX_MF4_MASK + 10U, // PseudoVMIN_VX_MF8 + 10U, // PseudoVMIN_VX_MF8_MASK + 10U, // PseudoVMNAND_MM_M1 + 10U, // PseudoVMNAND_MM_M2 + 10U, // PseudoVMNAND_MM_M4 + 10U, // PseudoVMNAND_MM_M8 + 10U, // PseudoVMNAND_MM_MF2 + 10U, // PseudoVMNAND_MM_MF4 + 10U, // PseudoVMNAND_MM_MF8 + 10U, // PseudoVMNOR_MM_M1 + 10U, // PseudoVMNOR_MM_M2 + 10U, // PseudoVMNOR_MM_M4 + 10U, // PseudoVMNOR_MM_M8 + 10U, // PseudoVMNOR_MM_MF2 + 10U, // PseudoVMNOR_MM_MF4 + 10U, // PseudoVMNOR_MM_MF8 + 10U, // PseudoVMORN_MM_M1 + 10U, // PseudoVMORN_MM_M2 + 10U, // PseudoVMORN_MM_M4 + 10U, // PseudoVMORN_MM_M8 + 10U, // PseudoVMORN_MM_MF2 + 10U, // PseudoVMORN_MM_MF4 + 10U, // PseudoVMORN_MM_MF8 + 10U, // PseudoVMOR_MM_M1 + 10U, // PseudoVMOR_MM_M2 + 10U, // PseudoVMOR_MM_M4 + 10U, // PseudoVMOR_MM_M8 + 10U, // PseudoVMOR_MM_MF2 + 10U, // PseudoVMOR_MM_MF4 + 10U, // PseudoVMOR_MM_MF8 + 10U, // PseudoVMSBC_VVM_M1 + 10U, // PseudoVMSBC_VVM_M2 + 10U, // PseudoVMSBC_VVM_M4 + 10U, // PseudoVMSBC_VVM_M8 + 10U, // PseudoVMSBC_VVM_MF2 + 10U, // PseudoVMSBC_VVM_MF4 + 10U, // PseudoVMSBC_VVM_MF8 + 10U, // PseudoVMSBC_VV_M1 + 10U, // PseudoVMSBC_VV_M2 + 10U, // PseudoVMSBC_VV_M4 + 10U, // PseudoVMSBC_VV_M8 + 10U, // PseudoVMSBC_VV_MF2 + 10U, // PseudoVMSBC_VV_MF4 + 10U, // PseudoVMSBC_VV_MF8 + 10U, // PseudoVMSBC_VXM_M1 + 10U, // PseudoVMSBC_VXM_M2 + 10U, // PseudoVMSBC_VXM_M4 + 10U, // PseudoVMSBC_VXM_M8 + 10U, // PseudoVMSBC_VXM_MF2 + 10U, // PseudoVMSBC_VXM_MF4 + 10U, // PseudoVMSBC_VXM_MF8 + 10U, // PseudoVMSBC_VX_M1 + 10U, // PseudoVMSBC_VX_M2 + 10U, // PseudoVMSBC_VX_M4 + 10U, // PseudoVMSBC_VX_M8 + 10U, // PseudoVMSBC_VX_MF2 + 10U, // PseudoVMSBC_VX_MF4 + 10U, // PseudoVMSBC_VX_MF8 + 10U, // PseudoVMSBF_M_B1 + 10U, // PseudoVMSBF_M_B16 + 10U, // PseudoVMSBF_M_B16_MASK + 10U, // PseudoVMSBF_M_B1_MASK + 10U, // PseudoVMSBF_M_B2 + 10U, // PseudoVMSBF_M_B2_MASK + 10U, // PseudoVMSBF_M_B32 + 10U, // PseudoVMSBF_M_B32_MASK + 10U, // PseudoVMSBF_M_B4 + 10U, // PseudoVMSBF_M_B4_MASK + 10U, // PseudoVMSBF_M_B64 + 10U, // PseudoVMSBF_M_B64_MASK + 10U, // PseudoVMSBF_M_B8 + 10U, // PseudoVMSBF_M_B8_MASK + 10U, // PseudoVMSEQ_VI_M1 + 10U, // PseudoVMSEQ_VI_M1_MASK + 10U, // PseudoVMSEQ_VI_M2 + 10U, // PseudoVMSEQ_VI_M2_MASK + 10U, // PseudoVMSEQ_VI_M4 + 10U, // PseudoVMSEQ_VI_M4_MASK + 10U, // PseudoVMSEQ_VI_M8 + 10U, // PseudoVMSEQ_VI_M8_MASK + 10U, // PseudoVMSEQ_VI_MF2 + 10U, // PseudoVMSEQ_VI_MF2_MASK + 10U, // PseudoVMSEQ_VI_MF4 + 10U, // PseudoVMSEQ_VI_MF4_MASK + 10U, // PseudoVMSEQ_VI_MF8 + 10U, // PseudoVMSEQ_VI_MF8_MASK + 10U, // PseudoVMSEQ_VV_M1 + 10U, // PseudoVMSEQ_VV_M1_MASK + 10U, // PseudoVMSEQ_VV_M2 + 10U, // PseudoVMSEQ_VV_M2_MASK + 10U, // PseudoVMSEQ_VV_M4 + 10U, // PseudoVMSEQ_VV_M4_MASK + 10U, // PseudoVMSEQ_VV_M8 + 10U, // PseudoVMSEQ_VV_M8_MASK + 10U, // PseudoVMSEQ_VV_MF2 + 10U, // PseudoVMSEQ_VV_MF2_MASK + 10U, // PseudoVMSEQ_VV_MF4 + 10U, // PseudoVMSEQ_VV_MF4_MASK + 10U, // PseudoVMSEQ_VV_MF8 + 10U, // PseudoVMSEQ_VV_MF8_MASK + 10U, // PseudoVMSEQ_VX_M1 + 10U, // PseudoVMSEQ_VX_M1_MASK + 10U, // PseudoVMSEQ_VX_M2 + 10U, // PseudoVMSEQ_VX_M2_MASK + 10U, // PseudoVMSEQ_VX_M4 + 10U, // PseudoVMSEQ_VX_M4_MASK + 10U, // PseudoVMSEQ_VX_M8 + 10U, // PseudoVMSEQ_VX_M8_MASK + 10U, // PseudoVMSEQ_VX_MF2 + 10U, // PseudoVMSEQ_VX_MF2_MASK + 10U, // PseudoVMSEQ_VX_MF4 + 10U, // PseudoVMSEQ_VX_MF4_MASK + 10U, // PseudoVMSEQ_VX_MF8 + 10U, // PseudoVMSEQ_VX_MF8_MASK + 10U, // PseudoVMSET_M_B1 + 10U, // PseudoVMSET_M_B16 + 10U, // PseudoVMSET_M_B2 + 10U, // PseudoVMSET_M_B32 + 10U, // PseudoVMSET_M_B4 + 10U, // PseudoVMSET_M_B64 + 10U, // PseudoVMSET_M_B8 + 1073759980U, // PseudoVMSGEU_VI + 536898678U, // PseudoVMSGEU_VX + 1073769590U, // PseudoVMSGEU_VX_M + 1745906806U, // PseudoVMSGEU_VX_M_T + 1073759823U, // PseudoVMSGE_VI + 536898354U, // PseudoVMSGE_VX + 1073769266U, // PseudoVMSGE_VX_M + 1745906482U, // PseudoVMSGE_VX_M_T + 10U, // PseudoVMSGTU_VI_M1 + 10U, // PseudoVMSGTU_VI_M1_MASK + 10U, // PseudoVMSGTU_VI_M2 + 10U, // PseudoVMSGTU_VI_M2_MASK + 10U, // PseudoVMSGTU_VI_M4 + 10U, // PseudoVMSGTU_VI_M4_MASK + 10U, // PseudoVMSGTU_VI_M8 + 10U, // PseudoVMSGTU_VI_M8_MASK + 10U, // PseudoVMSGTU_VI_MF2 + 10U, // PseudoVMSGTU_VI_MF2_MASK + 10U, // PseudoVMSGTU_VI_MF4 + 10U, // PseudoVMSGTU_VI_MF4_MASK + 10U, // PseudoVMSGTU_VI_MF8 + 10U, // PseudoVMSGTU_VI_MF8_MASK + 10U, // PseudoVMSGTU_VX_M1 + 10U, // PseudoVMSGTU_VX_M1_MASK + 10U, // PseudoVMSGTU_VX_M2 + 10U, // PseudoVMSGTU_VX_M2_MASK + 10U, // PseudoVMSGTU_VX_M4 + 10U, // PseudoVMSGTU_VX_M4_MASK + 10U, // PseudoVMSGTU_VX_M8 + 10U, // PseudoVMSGTU_VX_M8_MASK + 10U, // PseudoVMSGTU_VX_MF2 + 10U, // PseudoVMSGTU_VX_MF2_MASK + 10U, // PseudoVMSGTU_VX_MF4 + 10U, // PseudoVMSGTU_VX_MF4_MASK + 10U, // PseudoVMSGTU_VX_MF8 + 10U, // PseudoVMSGTU_VX_MF8_MASK + 10U, // PseudoVMSGT_VI_M1 + 10U, // PseudoVMSGT_VI_M1_MASK + 10U, // PseudoVMSGT_VI_M2 + 10U, // PseudoVMSGT_VI_M2_MASK + 10U, // PseudoVMSGT_VI_M4 + 10U, // PseudoVMSGT_VI_M4_MASK + 10U, // PseudoVMSGT_VI_M8 + 10U, // PseudoVMSGT_VI_M8_MASK + 10U, // PseudoVMSGT_VI_MF2 + 10U, // PseudoVMSGT_VI_MF2_MASK + 10U, // PseudoVMSGT_VI_MF4 + 10U, // PseudoVMSGT_VI_MF4_MASK + 10U, // PseudoVMSGT_VI_MF8 + 10U, // PseudoVMSGT_VI_MF8_MASK + 10U, // PseudoVMSGT_VX_M1 + 10U, // PseudoVMSGT_VX_M1_MASK + 10U, // PseudoVMSGT_VX_M2 + 10U, // PseudoVMSGT_VX_M2_MASK + 10U, // PseudoVMSGT_VX_M4 + 10U, // PseudoVMSGT_VX_M4_MASK + 10U, // PseudoVMSGT_VX_M8 + 10U, // PseudoVMSGT_VX_M8_MASK + 10U, // PseudoVMSGT_VX_MF2 + 10U, // PseudoVMSGT_VX_MF2_MASK + 10U, // PseudoVMSGT_VX_MF4 + 10U, // PseudoVMSGT_VX_MF4_MASK + 10U, // PseudoVMSGT_VX_MF8 + 10U, // PseudoVMSGT_VX_MF8_MASK + 10U, // PseudoVMSIF_M_B1 + 10U, // PseudoVMSIF_M_B16 + 10U, // PseudoVMSIF_M_B16_MASK + 10U, // PseudoVMSIF_M_B1_MASK + 10U, // PseudoVMSIF_M_B2 + 10U, // PseudoVMSIF_M_B2_MASK + 10U, // PseudoVMSIF_M_B32 + 10U, // PseudoVMSIF_M_B32_MASK + 10U, // PseudoVMSIF_M_B4 + 10U, // PseudoVMSIF_M_B4_MASK + 10U, // PseudoVMSIF_M_B64 + 10U, // PseudoVMSIF_M_B64_MASK + 10U, // PseudoVMSIF_M_B8 + 10U, // PseudoVMSIF_M_B8_MASK + 10U, // PseudoVMSLEU_VI_M1 + 10U, // PseudoVMSLEU_VI_M1_MASK + 10U, // PseudoVMSLEU_VI_M2 + 10U, // PseudoVMSLEU_VI_M2_MASK + 10U, // PseudoVMSLEU_VI_M4 + 10U, // PseudoVMSLEU_VI_M4_MASK + 10U, // PseudoVMSLEU_VI_M8 + 10U, // PseudoVMSLEU_VI_M8_MASK + 10U, // PseudoVMSLEU_VI_MF2 + 10U, // PseudoVMSLEU_VI_MF2_MASK + 10U, // PseudoVMSLEU_VI_MF4 + 10U, // PseudoVMSLEU_VI_MF4_MASK + 10U, // PseudoVMSLEU_VI_MF8 + 10U, // PseudoVMSLEU_VI_MF8_MASK + 10U, // PseudoVMSLEU_VV_M1 + 10U, // PseudoVMSLEU_VV_M1_MASK + 10U, // PseudoVMSLEU_VV_M2 + 10U, // PseudoVMSLEU_VV_M2_MASK + 10U, // PseudoVMSLEU_VV_M4 + 10U, // PseudoVMSLEU_VV_M4_MASK + 10U, // PseudoVMSLEU_VV_M8 + 10U, // PseudoVMSLEU_VV_M8_MASK + 10U, // PseudoVMSLEU_VV_MF2 + 10U, // PseudoVMSLEU_VV_MF2_MASK + 10U, // PseudoVMSLEU_VV_MF4 + 10U, // PseudoVMSLEU_VV_MF4_MASK + 10U, // PseudoVMSLEU_VV_MF8 + 10U, // PseudoVMSLEU_VV_MF8_MASK + 10U, // PseudoVMSLEU_VX_M1 + 10U, // PseudoVMSLEU_VX_M1_MASK + 10U, // PseudoVMSLEU_VX_M2 + 10U, // PseudoVMSLEU_VX_M2_MASK + 10U, // PseudoVMSLEU_VX_M4 + 10U, // PseudoVMSLEU_VX_M4_MASK + 10U, // PseudoVMSLEU_VX_M8 + 10U, // PseudoVMSLEU_VX_M8_MASK + 10U, // PseudoVMSLEU_VX_MF2 + 10U, // PseudoVMSLEU_VX_MF2_MASK + 10U, // PseudoVMSLEU_VX_MF4 + 10U, // PseudoVMSLEU_VX_MF4_MASK + 10U, // PseudoVMSLEU_VX_MF8 + 10U, // PseudoVMSLEU_VX_MF8_MASK + 10U, // PseudoVMSLE_VI_M1 + 10U, // PseudoVMSLE_VI_M1_MASK + 10U, // PseudoVMSLE_VI_M2 + 10U, // PseudoVMSLE_VI_M2_MASK + 10U, // PseudoVMSLE_VI_M4 + 10U, // PseudoVMSLE_VI_M4_MASK + 10U, // PseudoVMSLE_VI_M8 + 10U, // PseudoVMSLE_VI_M8_MASK + 10U, // PseudoVMSLE_VI_MF2 + 10U, // PseudoVMSLE_VI_MF2_MASK + 10U, // PseudoVMSLE_VI_MF4 + 10U, // PseudoVMSLE_VI_MF4_MASK + 10U, // PseudoVMSLE_VI_MF8 + 10U, // PseudoVMSLE_VI_MF8_MASK + 10U, // PseudoVMSLE_VV_M1 + 10U, // PseudoVMSLE_VV_M1_MASK + 10U, // PseudoVMSLE_VV_M2 + 10U, // PseudoVMSLE_VV_M2_MASK + 10U, // PseudoVMSLE_VV_M4 + 10U, // PseudoVMSLE_VV_M4_MASK + 10U, // PseudoVMSLE_VV_M8 + 10U, // PseudoVMSLE_VV_M8_MASK + 10U, // PseudoVMSLE_VV_MF2 + 10U, // PseudoVMSLE_VV_MF2_MASK + 10U, // PseudoVMSLE_VV_MF4 + 10U, // PseudoVMSLE_VV_MF4_MASK + 10U, // PseudoVMSLE_VV_MF8 + 10U, // PseudoVMSLE_VV_MF8_MASK + 10U, // PseudoVMSLE_VX_M1 + 10U, // PseudoVMSLE_VX_M1_MASK + 10U, // PseudoVMSLE_VX_M2 + 10U, // PseudoVMSLE_VX_M2_MASK + 10U, // PseudoVMSLE_VX_M4 + 10U, // PseudoVMSLE_VX_M4_MASK + 10U, // PseudoVMSLE_VX_M8 + 10U, // PseudoVMSLE_VX_M8_MASK + 10U, // PseudoVMSLE_VX_MF2 + 10U, // PseudoVMSLE_VX_MF2_MASK + 10U, // PseudoVMSLE_VX_MF4 + 10U, // PseudoVMSLE_VX_MF4_MASK + 10U, // PseudoVMSLE_VX_MF8 + 10U, // PseudoVMSLE_VX_MF8_MASK + 1073760013U, // PseudoVMSLTU_VI + 10U, // PseudoVMSLTU_VV_M1 + 10U, // PseudoVMSLTU_VV_M1_MASK + 10U, // PseudoVMSLTU_VV_M2 + 10U, // PseudoVMSLTU_VV_M2_MASK + 10U, // PseudoVMSLTU_VV_M4 + 10U, // PseudoVMSLTU_VV_M4_MASK + 10U, // PseudoVMSLTU_VV_M8 + 10U, // PseudoVMSLTU_VV_M8_MASK + 10U, // PseudoVMSLTU_VV_MF2 + 10U, // PseudoVMSLTU_VV_MF2_MASK + 10U, // PseudoVMSLTU_VV_MF4 + 10U, // PseudoVMSLTU_VV_MF4_MASK + 10U, // PseudoVMSLTU_VV_MF8 + 10U, // PseudoVMSLTU_VV_MF8_MASK + 10U, // PseudoVMSLTU_VX_M1 + 10U, // PseudoVMSLTU_VX_M1_MASK + 10U, // PseudoVMSLTU_VX_M2 + 10U, // PseudoVMSLTU_VX_M2_MASK + 10U, // PseudoVMSLTU_VX_M4 + 10U, // PseudoVMSLTU_VX_M4_MASK + 10U, // PseudoVMSLTU_VX_M8 + 10U, // PseudoVMSLTU_VX_M8_MASK + 10U, // PseudoVMSLTU_VX_MF2 + 10U, // PseudoVMSLTU_VX_MF2_MASK + 10U, // PseudoVMSLTU_VX_MF4 + 10U, // PseudoVMSLTU_VX_MF4_MASK + 10U, // PseudoVMSLTU_VX_MF8 + 10U, // PseudoVMSLTU_VX_MF8_MASK + 1073759959U, // PseudoVMSLT_VI + 10U, // PseudoVMSLT_VV_M1 + 10U, // PseudoVMSLT_VV_M1_MASK + 10U, // PseudoVMSLT_VV_M2 + 10U, // PseudoVMSLT_VV_M2_MASK + 10U, // PseudoVMSLT_VV_M4 + 10U, // PseudoVMSLT_VV_M4_MASK + 10U, // PseudoVMSLT_VV_M8 + 10U, // PseudoVMSLT_VV_M8_MASK + 10U, // PseudoVMSLT_VV_MF2 + 10U, // PseudoVMSLT_VV_MF2_MASK + 10U, // PseudoVMSLT_VV_MF4 + 10U, // PseudoVMSLT_VV_MF4_MASK + 10U, // PseudoVMSLT_VV_MF8 + 10U, // PseudoVMSLT_VV_MF8_MASK + 10U, // PseudoVMSLT_VX_M1 + 10U, // PseudoVMSLT_VX_M1_MASK + 10U, // PseudoVMSLT_VX_M2 + 10U, // PseudoVMSLT_VX_M2_MASK + 10U, // PseudoVMSLT_VX_M4 + 10U, // PseudoVMSLT_VX_M4_MASK + 10U, // PseudoVMSLT_VX_M8 + 10U, // PseudoVMSLT_VX_M8_MASK + 10U, // PseudoVMSLT_VX_MF2 + 10U, // PseudoVMSLT_VX_MF2_MASK + 10U, // PseudoVMSLT_VX_MF4 + 10U, // PseudoVMSLT_VX_MF4_MASK + 10U, // PseudoVMSLT_VX_MF8 + 10U, // PseudoVMSLT_VX_MF8_MASK + 10U, // PseudoVMSNE_VI_M1 + 10U, // PseudoVMSNE_VI_M1_MASK + 10U, // PseudoVMSNE_VI_M2 + 10U, // PseudoVMSNE_VI_M2_MASK + 10U, // PseudoVMSNE_VI_M4 + 10U, // PseudoVMSNE_VI_M4_MASK + 10U, // PseudoVMSNE_VI_M8 + 10U, // PseudoVMSNE_VI_M8_MASK + 10U, // PseudoVMSNE_VI_MF2 + 10U, // PseudoVMSNE_VI_MF2_MASK + 10U, // PseudoVMSNE_VI_MF4 + 10U, // PseudoVMSNE_VI_MF4_MASK + 10U, // PseudoVMSNE_VI_MF8 + 10U, // PseudoVMSNE_VI_MF8_MASK + 10U, // PseudoVMSNE_VV_M1 + 10U, // PseudoVMSNE_VV_M1_MASK + 10U, // PseudoVMSNE_VV_M2 + 10U, // PseudoVMSNE_VV_M2_MASK + 10U, // PseudoVMSNE_VV_M4 + 10U, // PseudoVMSNE_VV_M4_MASK + 10U, // PseudoVMSNE_VV_M8 + 10U, // PseudoVMSNE_VV_M8_MASK + 10U, // PseudoVMSNE_VV_MF2 + 10U, // PseudoVMSNE_VV_MF2_MASK + 10U, // PseudoVMSNE_VV_MF4 + 10U, // PseudoVMSNE_VV_MF4_MASK + 10U, // PseudoVMSNE_VV_MF8 + 10U, // PseudoVMSNE_VV_MF8_MASK + 10U, // PseudoVMSNE_VX_M1 + 10U, // PseudoVMSNE_VX_M1_MASK + 10U, // PseudoVMSNE_VX_M2 + 10U, // PseudoVMSNE_VX_M2_MASK + 10U, // PseudoVMSNE_VX_M4 + 10U, // PseudoVMSNE_VX_M4_MASK + 10U, // PseudoVMSNE_VX_M8 + 10U, // PseudoVMSNE_VX_M8_MASK + 10U, // PseudoVMSNE_VX_MF2 + 10U, // PseudoVMSNE_VX_MF2_MASK + 10U, // PseudoVMSNE_VX_MF4 + 10U, // PseudoVMSNE_VX_MF4_MASK + 10U, // PseudoVMSNE_VX_MF8 + 10U, // PseudoVMSNE_VX_MF8_MASK + 10U, // PseudoVMSOF_M_B1 + 10U, // PseudoVMSOF_M_B16 + 10U, // PseudoVMSOF_M_B16_MASK + 10U, // PseudoVMSOF_M_B1_MASK + 10U, // PseudoVMSOF_M_B2 + 10U, // PseudoVMSOF_M_B2_MASK + 10U, // PseudoVMSOF_M_B32 + 10U, // PseudoVMSOF_M_B32_MASK + 10U, // PseudoVMSOF_M_B4 + 10U, // PseudoVMSOF_M_B4_MASK + 10U, // PseudoVMSOF_M_B64 + 10U, // PseudoVMSOF_M_B64_MASK + 10U, // PseudoVMSOF_M_B8 + 10U, // PseudoVMSOF_M_B8_MASK + 10U, // PseudoVMULHSU_VV_M1 + 10U, // PseudoVMULHSU_VV_M1_MASK + 10U, // PseudoVMULHSU_VV_M2 + 10U, // PseudoVMULHSU_VV_M2_MASK + 10U, // PseudoVMULHSU_VV_M4 + 10U, // PseudoVMULHSU_VV_M4_MASK + 10U, // PseudoVMULHSU_VV_M8 + 10U, // PseudoVMULHSU_VV_M8_MASK + 10U, // PseudoVMULHSU_VV_MF2 + 10U, // PseudoVMULHSU_VV_MF2_MASK + 10U, // PseudoVMULHSU_VV_MF4 + 10U, // PseudoVMULHSU_VV_MF4_MASK + 10U, // PseudoVMULHSU_VV_MF8 + 10U, // PseudoVMULHSU_VV_MF8_MASK + 10U, // PseudoVMULHSU_VX_M1 + 10U, // PseudoVMULHSU_VX_M1_MASK + 10U, // PseudoVMULHSU_VX_M2 + 10U, // PseudoVMULHSU_VX_M2_MASK + 10U, // PseudoVMULHSU_VX_M4 + 10U, // PseudoVMULHSU_VX_M4_MASK + 10U, // PseudoVMULHSU_VX_M8 + 10U, // PseudoVMULHSU_VX_M8_MASK + 10U, // PseudoVMULHSU_VX_MF2 + 10U, // PseudoVMULHSU_VX_MF2_MASK + 10U, // PseudoVMULHSU_VX_MF4 + 10U, // PseudoVMULHSU_VX_MF4_MASK + 10U, // PseudoVMULHSU_VX_MF8 + 10U, // PseudoVMULHSU_VX_MF8_MASK + 10U, // PseudoVMULHU_VV_M1 + 10U, // PseudoVMULHU_VV_M1_MASK + 10U, // PseudoVMULHU_VV_M2 + 10U, // PseudoVMULHU_VV_M2_MASK + 10U, // PseudoVMULHU_VV_M4 + 10U, // PseudoVMULHU_VV_M4_MASK + 10U, // PseudoVMULHU_VV_M8 + 10U, // PseudoVMULHU_VV_M8_MASK + 10U, // PseudoVMULHU_VV_MF2 + 10U, // PseudoVMULHU_VV_MF2_MASK + 10U, // PseudoVMULHU_VV_MF4 + 10U, // PseudoVMULHU_VV_MF4_MASK + 10U, // PseudoVMULHU_VV_MF8 + 10U, // PseudoVMULHU_VV_MF8_MASK + 10U, // PseudoVMULHU_VX_M1 + 10U, // PseudoVMULHU_VX_M1_MASK + 10U, // PseudoVMULHU_VX_M2 + 10U, // PseudoVMULHU_VX_M2_MASK + 10U, // PseudoVMULHU_VX_M4 + 10U, // PseudoVMULHU_VX_M4_MASK + 10U, // PseudoVMULHU_VX_M8 + 10U, // PseudoVMULHU_VX_M8_MASK + 10U, // PseudoVMULHU_VX_MF2 + 10U, // PseudoVMULHU_VX_MF2_MASK + 10U, // PseudoVMULHU_VX_MF4 + 10U, // PseudoVMULHU_VX_MF4_MASK + 10U, // PseudoVMULHU_VX_MF8 + 10U, // PseudoVMULHU_VX_MF8_MASK + 10U, // PseudoVMULH_VV_M1 + 10U, // PseudoVMULH_VV_M1_MASK + 10U, // PseudoVMULH_VV_M2 + 10U, // PseudoVMULH_VV_M2_MASK + 10U, // PseudoVMULH_VV_M4 + 10U, // PseudoVMULH_VV_M4_MASK + 10U, // PseudoVMULH_VV_M8 + 10U, // PseudoVMULH_VV_M8_MASK + 10U, // PseudoVMULH_VV_MF2 + 10U, // PseudoVMULH_VV_MF2_MASK + 10U, // PseudoVMULH_VV_MF4 + 10U, // PseudoVMULH_VV_MF4_MASK + 10U, // PseudoVMULH_VV_MF8 + 10U, // PseudoVMULH_VV_MF8_MASK + 10U, // PseudoVMULH_VX_M1 + 10U, // PseudoVMULH_VX_M1_MASK + 10U, // PseudoVMULH_VX_M2 + 10U, // PseudoVMULH_VX_M2_MASK + 10U, // PseudoVMULH_VX_M4 + 10U, // PseudoVMULH_VX_M4_MASK + 10U, // PseudoVMULH_VX_M8 + 10U, // PseudoVMULH_VX_M8_MASK + 10U, // PseudoVMULH_VX_MF2 + 10U, // PseudoVMULH_VX_MF2_MASK + 10U, // PseudoVMULH_VX_MF4 + 10U, // PseudoVMULH_VX_MF4_MASK + 10U, // PseudoVMULH_VX_MF8 + 10U, // PseudoVMULH_VX_MF8_MASK + 10U, // PseudoVMUL_VV_M1 + 10U, // PseudoVMUL_VV_M1_MASK + 10U, // PseudoVMUL_VV_M2 + 10U, // PseudoVMUL_VV_M2_MASK + 10U, // PseudoVMUL_VV_M4 + 10U, // PseudoVMUL_VV_M4_MASK + 10U, // PseudoVMUL_VV_M8 + 10U, // PseudoVMUL_VV_M8_MASK + 10U, // PseudoVMUL_VV_MF2 + 10U, // PseudoVMUL_VV_MF2_MASK + 10U, // PseudoVMUL_VV_MF4 + 10U, // PseudoVMUL_VV_MF4_MASK + 10U, // PseudoVMUL_VV_MF8 + 10U, // PseudoVMUL_VV_MF8_MASK + 10U, // PseudoVMUL_VX_M1 + 10U, // PseudoVMUL_VX_M1_MASK + 10U, // PseudoVMUL_VX_M2 + 10U, // PseudoVMUL_VX_M2_MASK + 10U, // PseudoVMUL_VX_M4 + 10U, // PseudoVMUL_VX_M4_MASK + 10U, // PseudoVMUL_VX_M8 + 10U, // PseudoVMUL_VX_M8_MASK + 10U, // PseudoVMUL_VX_MF2 + 10U, // PseudoVMUL_VX_MF2_MASK + 10U, // PseudoVMUL_VX_MF4 + 10U, // PseudoVMUL_VX_MF4_MASK + 10U, // PseudoVMUL_VX_MF8 + 10U, // PseudoVMUL_VX_MF8_MASK + 10U, // PseudoVMV1R_V + 10U, // PseudoVMV2R_V + 10U, // PseudoVMV4R_V + 10U, // PseudoVMV8R_V + 10U, // PseudoVMV_S_X_M1 + 10U, // PseudoVMV_S_X_M2 + 10U, // PseudoVMV_S_X_M4 + 10U, // PseudoVMV_S_X_M8 + 10U, // PseudoVMV_S_X_MF2 + 10U, // PseudoVMV_S_X_MF4 + 10U, // PseudoVMV_S_X_MF8 + 10U, // PseudoVMV_V_I_M1 + 10U, // PseudoVMV_V_I_M2 + 10U, // PseudoVMV_V_I_M4 + 10U, // PseudoVMV_V_I_M8 + 10U, // PseudoVMV_V_I_MF2 + 10U, // PseudoVMV_V_I_MF4 + 10U, // PseudoVMV_V_I_MF8 + 10U, // PseudoVMV_V_V_M1 + 10U, // PseudoVMV_V_V_M2 + 10U, // PseudoVMV_V_V_M4 + 10U, // PseudoVMV_V_V_M8 + 10U, // PseudoVMV_V_V_MF2 + 10U, // PseudoVMV_V_V_MF4 + 10U, // PseudoVMV_V_V_MF8 + 10U, // PseudoVMV_V_X_M1 + 10U, // PseudoVMV_V_X_M2 + 10U, // PseudoVMV_V_X_M4 + 10U, // PseudoVMV_V_X_M8 + 10U, // PseudoVMV_V_X_MF2 + 10U, // PseudoVMV_V_X_MF4 + 10U, // PseudoVMV_V_X_MF8 + 10U, // PseudoVMV_X_S_M1 + 10U, // PseudoVMV_X_S_M2 + 10U, // PseudoVMV_X_S_M4 + 10U, // PseudoVMV_X_S_M8 + 10U, // PseudoVMV_X_S_MF2 + 10U, // PseudoVMV_X_S_MF4 + 10U, // PseudoVMV_X_S_MF8 + 10U, // PseudoVMXNOR_MM_M1 + 10U, // PseudoVMXNOR_MM_M2 + 10U, // PseudoVMXNOR_MM_M4 + 10U, // PseudoVMXNOR_MM_M8 + 10U, // PseudoVMXNOR_MM_MF2 + 10U, // PseudoVMXNOR_MM_MF4 + 10U, // PseudoVMXNOR_MM_MF8 + 10U, // PseudoVMXOR_MM_M1 + 10U, // PseudoVMXOR_MM_M2 + 10U, // PseudoVMXOR_MM_M4 + 10U, // PseudoVMXOR_MM_M8 + 10U, // PseudoVMXOR_MM_MF2 + 10U, // PseudoVMXOR_MM_MF4 + 10U, // PseudoVMXOR_MM_MF8 + 10U, // PseudoVNCLIPU_WI_M1 + 10U, // PseudoVNCLIPU_WI_M1_MASK + 10U, // PseudoVNCLIPU_WI_M2 + 10U, // PseudoVNCLIPU_WI_M2_MASK + 10U, // PseudoVNCLIPU_WI_M4 + 10U, // PseudoVNCLIPU_WI_M4_MASK + 10U, // PseudoVNCLIPU_WI_MF2 + 10U, // PseudoVNCLIPU_WI_MF2_MASK + 10U, // PseudoVNCLIPU_WI_MF4 + 10U, // PseudoVNCLIPU_WI_MF4_MASK + 10U, // PseudoVNCLIPU_WI_MF8 + 10U, // PseudoVNCLIPU_WI_MF8_MASK + 10U, // PseudoVNCLIPU_WV_M1 + 10U, // PseudoVNCLIPU_WV_M1_MASK + 10U, // PseudoVNCLIPU_WV_M2 + 10U, // PseudoVNCLIPU_WV_M2_MASK + 10U, // PseudoVNCLIPU_WV_M4 + 10U, // PseudoVNCLIPU_WV_M4_MASK + 10U, // PseudoVNCLIPU_WV_MF2 + 10U, // PseudoVNCLIPU_WV_MF2_MASK + 10U, // PseudoVNCLIPU_WV_MF4 + 10U, // PseudoVNCLIPU_WV_MF4_MASK + 10U, // PseudoVNCLIPU_WV_MF8 + 10U, // PseudoVNCLIPU_WV_MF8_MASK + 10U, // PseudoVNCLIPU_WX_M1 + 10U, // PseudoVNCLIPU_WX_M1_MASK + 10U, // PseudoVNCLIPU_WX_M2 + 10U, // PseudoVNCLIPU_WX_M2_MASK + 10U, // PseudoVNCLIPU_WX_M4 + 10U, // PseudoVNCLIPU_WX_M4_MASK + 10U, // PseudoVNCLIPU_WX_MF2 + 10U, // PseudoVNCLIPU_WX_MF2_MASK + 10U, // PseudoVNCLIPU_WX_MF4 + 10U, // PseudoVNCLIPU_WX_MF4_MASK + 10U, // PseudoVNCLIPU_WX_MF8 + 10U, // PseudoVNCLIPU_WX_MF8_MASK + 10U, // PseudoVNCLIP_WI_M1 + 10U, // PseudoVNCLIP_WI_M1_MASK + 10U, // PseudoVNCLIP_WI_M2 + 10U, // PseudoVNCLIP_WI_M2_MASK + 10U, // PseudoVNCLIP_WI_M4 + 10U, // PseudoVNCLIP_WI_M4_MASK + 10U, // PseudoVNCLIP_WI_MF2 + 10U, // PseudoVNCLIP_WI_MF2_MASK + 10U, // PseudoVNCLIP_WI_MF4 + 10U, // PseudoVNCLIP_WI_MF4_MASK + 10U, // PseudoVNCLIP_WI_MF8 + 10U, // PseudoVNCLIP_WI_MF8_MASK + 10U, // PseudoVNCLIP_WV_M1 + 10U, // PseudoVNCLIP_WV_M1_MASK + 10U, // PseudoVNCLIP_WV_M2 + 10U, // PseudoVNCLIP_WV_M2_MASK + 10U, // PseudoVNCLIP_WV_M4 + 10U, // PseudoVNCLIP_WV_M4_MASK + 10U, // PseudoVNCLIP_WV_MF2 + 10U, // PseudoVNCLIP_WV_MF2_MASK + 10U, // PseudoVNCLIP_WV_MF4 + 10U, // PseudoVNCLIP_WV_MF4_MASK + 10U, // PseudoVNCLIP_WV_MF8 + 10U, // PseudoVNCLIP_WV_MF8_MASK + 10U, // PseudoVNCLIP_WX_M1 + 10U, // PseudoVNCLIP_WX_M1_MASK + 10U, // PseudoVNCLIP_WX_M2 + 10U, // PseudoVNCLIP_WX_M2_MASK + 10U, // PseudoVNCLIP_WX_M4 + 10U, // PseudoVNCLIP_WX_M4_MASK + 10U, // PseudoVNCLIP_WX_MF2 + 10U, // PseudoVNCLIP_WX_MF2_MASK + 10U, // PseudoVNCLIP_WX_MF4 + 10U, // PseudoVNCLIP_WX_MF4_MASK + 10U, // PseudoVNCLIP_WX_MF8 + 10U, // PseudoVNCLIP_WX_MF8_MASK + 10U, // PseudoVNMSAC_VV_M1 + 10U, // PseudoVNMSAC_VV_M1_MASK + 10U, // PseudoVNMSAC_VV_M2 + 10U, // PseudoVNMSAC_VV_M2_MASK + 10U, // PseudoVNMSAC_VV_M4 + 10U, // PseudoVNMSAC_VV_M4_MASK + 10U, // PseudoVNMSAC_VV_M8 + 10U, // PseudoVNMSAC_VV_M8_MASK + 10U, // PseudoVNMSAC_VV_MF2 + 10U, // PseudoVNMSAC_VV_MF2_MASK + 10U, // PseudoVNMSAC_VV_MF4 + 10U, // PseudoVNMSAC_VV_MF4_MASK + 10U, // PseudoVNMSAC_VV_MF8 + 10U, // PseudoVNMSAC_VV_MF8_MASK + 10U, // PseudoVNMSAC_VX_M1 + 10U, // PseudoVNMSAC_VX_M1_MASK + 10U, // PseudoVNMSAC_VX_M2 + 10U, // PseudoVNMSAC_VX_M2_MASK + 10U, // PseudoVNMSAC_VX_M4 + 10U, // PseudoVNMSAC_VX_M4_MASK + 10U, // PseudoVNMSAC_VX_M8 + 10U, // PseudoVNMSAC_VX_M8_MASK + 10U, // PseudoVNMSAC_VX_MF2 + 10U, // PseudoVNMSAC_VX_MF2_MASK + 10U, // PseudoVNMSAC_VX_MF4 + 10U, // PseudoVNMSAC_VX_MF4_MASK + 10U, // PseudoVNMSAC_VX_MF8 + 10U, // PseudoVNMSAC_VX_MF8_MASK + 10U, // PseudoVNMSUB_VV_M1 + 10U, // PseudoVNMSUB_VV_M1_MASK + 10U, // PseudoVNMSUB_VV_M2 + 10U, // PseudoVNMSUB_VV_M2_MASK + 10U, // PseudoVNMSUB_VV_M4 + 10U, // PseudoVNMSUB_VV_M4_MASK + 10U, // PseudoVNMSUB_VV_M8 + 10U, // PseudoVNMSUB_VV_M8_MASK + 10U, // PseudoVNMSUB_VV_MF2 + 10U, // PseudoVNMSUB_VV_MF2_MASK + 10U, // PseudoVNMSUB_VV_MF4 + 10U, // PseudoVNMSUB_VV_MF4_MASK + 10U, // PseudoVNMSUB_VV_MF8 + 10U, // PseudoVNMSUB_VV_MF8_MASK + 10U, // PseudoVNMSUB_VX_M1 + 10U, // PseudoVNMSUB_VX_M1_MASK + 10U, // PseudoVNMSUB_VX_M2 + 10U, // PseudoVNMSUB_VX_M2_MASK + 10U, // PseudoVNMSUB_VX_M4 + 10U, // PseudoVNMSUB_VX_M4_MASK + 10U, // PseudoVNMSUB_VX_M8 + 10U, // PseudoVNMSUB_VX_M8_MASK + 10U, // PseudoVNMSUB_VX_MF2 + 10U, // PseudoVNMSUB_VX_MF2_MASK + 10U, // PseudoVNMSUB_VX_MF4 + 10U, // PseudoVNMSUB_VX_MF4_MASK + 10U, // PseudoVNMSUB_VX_MF8 + 10U, // PseudoVNMSUB_VX_MF8_MASK + 10U, // PseudoVNSRA_WI_M1 + 10U, // PseudoVNSRA_WI_M1_MASK + 10U, // PseudoVNSRA_WI_M2 + 10U, // PseudoVNSRA_WI_M2_MASK + 10U, // PseudoVNSRA_WI_M4 + 10U, // PseudoVNSRA_WI_M4_MASK + 10U, // PseudoVNSRA_WI_MF2 + 10U, // PseudoVNSRA_WI_MF2_MASK + 10U, // PseudoVNSRA_WI_MF4 + 10U, // PseudoVNSRA_WI_MF4_MASK + 10U, // PseudoVNSRA_WI_MF8 + 10U, // PseudoVNSRA_WI_MF8_MASK + 10U, // PseudoVNSRA_WV_M1 + 10U, // PseudoVNSRA_WV_M1_MASK + 10U, // PseudoVNSRA_WV_M2 + 10U, // PseudoVNSRA_WV_M2_MASK + 10U, // PseudoVNSRA_WV_M4 + 10U, // PseudoVNSRA_WV_M4_MASK + 10U, // PseudoVNSRA_WV_MF2 + 10U, // PseudoVNSRA_WV_MF2_MASK + 10U, // PseudoVNSRA_WV_MF4 + 10U, // PseudoVNSRA_WV_MF4_MASK + 10U, // PseudoVNSRA_WV_MF8 + 10U, // PseudoVNSRA_WV_MF8_MASK + 10U, // PseudoVNSRA_WX_M1 + 10U, // PseudoVNSRA_WX_M1_MASK + 10U, // PseudoVNSRA_WX_M2 + 10U, // PseudoVNSRA_WX_M2_MASK + 10U, // PseudoVNSRA_WX_M4 + 10U, // PseudoVNSRA_WX_M4_MASK + 10U, // PseudoVNSRA_WX_MF2 + 10U, // PseudoVNSRA_WX_MF2_MASK + 10U, // PseudoVNSRA_WX_MF4 + 10U, // PseudoVNSRA_WX_MF4_MASK + 10U, // PseudoVNSRA_WX_MF8 + 10U, // PseudoVNSRA_WX_MF8_MASK + 10U, // PseudoVNSRL_WI_M1 + 10U, // PseudoVNSRL_WI_M1_MASK + 10U, // PseudoVNSRL_WI_M2 + 10U, // PseudoVNSRL_WI_M2_MASK + 10U, // PseudoVNSRL_WI_M4 + 10U, // PseudoVNSRL_WI_M4_MASK + 10U, // PseudoVNSRL_WI_MF2 + 10U, // PseudoVNSRL_WI_MF2_MASK + 10U, // PseudoVNSRL_WI_MF4 + 10U, // PseudoVNSRL_WI_MF4_MASK + 10U, // PseudoVNSRL_WI_MF8 + 10U, // PseudoVNSRL_WI_MF8_MASK + 10U, // PseudoVNSRL_WV_M1 + 10U, // PseudoVNSRL_WV_M1_MASK + 10U, // PseudoVNSRL_WV_M2 + 10U, // PseudoVNSRL_WV_M2_MASK + 10U, // PseudoVNSRL_WV_M4 + 10U, // PseudoVNSRL_WV_M4_MASK + 10U, // PseudoVNSRL_WV_MF2 + 10U, // PseudoVNSRL_WV_MF2_MASK + 10U, // PseudoVNSRL_WV_MF4 + 10U, // PseudoVNSRL_WV_MF4_MASK + 10U, // PseudoVNSRL_WV_MF8 + 10U, // PseudoVNSRL_WV_MF8_MASK + 10U, // PseudoVNSRL_WX_M1 + 10U, // PseudoVNSRL_WX_M1_MASK + 10U, // PseudoVNSRL_WX_M2 + 10U, // PseudoVNSRL_WX_M2_MASK + 10U, // PseudoVNSRL_WX_M4 + 10U, // PseudoVNSRL_WX_M4_MASK + 10U, // PseudoVNSRL_WX_MF2 + 10U, // PseudoVNSRL_WX_MF2_MASK + 10U, // PseudoVNSRL_WX_MF4 + 10U, // PseudoVNSRL_WX_MF4_MASK + 10U, // PseudoVNSRL_WX_MF8 + 10U, // PseudoVNSRL_WX_MF8_MASK + 10U, // PseudoVOR_VI_M1 + 10U, // PseudoVOR_VI_M1_MASK + 10U, // PseudoVOR_VI_M2 + 10U, // PseudoVOR_VI_M2_MASK + 10U, // PseudoVOR_VI_M4 + 10U, // PseudoVOR_VI_M4_MASK + 10U, // PseudoVOR_VI_M8 + 10U, // PseudoVOR_VI_M8_MASK + 10U, // PseudoVOR_VI_MF2 + 10U, // PseudoVOR_VI_MF2_MASK + 10U, // PseudoVOR_VI_MF4 + 10U, // PseudoVOR_VI_MF4_MASK + 10U, // PseudoVOR_VI_MF8 + 10U, // PseudoVOR_VI_MF8_MASK + 10U, // PseudoVOR_VV_M1 + 10U, // PseudoVOR_VV_M1_MASK + 10U, // PseudoVOR_VV_M2 + 10U, // PseudoVOR_VV_M2_MASK + 10U, // PseudoVOR_VV_M4 + 10U, // PseudoVOR_VV_M4_MASK + 10U, // PseudoVOR_VV_M8 + 10U, // PseudoVOR_VV_M8_MASK + 10U, // PseudoVOR_VV_MF2 + 10U, // PseudoVOR_VV_MF2_MASK + 10U, // PseudoVOR_VV_MF4 + 10U, // PseudoVOR_VV_MF4_MASK + 10U, // PseudoVOR_VV_MF8 + 10U, // PseudoVOR_VV_MF8_MASK + 10U, // PseudoVOR_VX_M1 + 10U, // PseudoVOR_VX_M1_MASK + 10U, // PseudoVOR_VX_M2 + 10U, // PseudoVOR_VX_M2_MASK + 10U, // PseudoVOR_VX_M4 + 10U, // PseudoVOR_VX_M4_MASK + 10U, // PseudoVOR_VX_M8 + 10U, // PseudoVOR_VX_M8_MASK + 10U, // PseudoVOR_VX_MF2 + 10U, // PseudoVOR_VX_MF2_MASK + 10U, // PseudoVOR_VX_MF4 + 10U, // PseudoVOR_VX_MF4_MASK + 10U, // PseudoVOR_VX_MF8 + 10U, // PseudoVOR_VX_MF8_MASK + 10U, // PseudoVREDAND_VS_M1 + 10U, // PseudoVREDAND_VS_M1_MASK + 10U, // PseudoVREDAND_VS_M2 + 10U, // PseudoVREDAND_VS_M2_MASK + 10U, // PseudoVREDAND_VS_M4 + 10U, // PseudoVREDAND_VS_M4_MASK + 10U, // PseudoVREDAND_VS_M8 + 10U, // PseudoVREDAND_VS_M8_MASK + 10U, // PseudoVREDAND_VS_MF2 + 10U, // PseudoVREDAND_VS_MF2_MASK + 10U, // PseudoVREDAND_VS_MF4 + 10U, // PseudoVREDAND_VS_MF4_MASK + 10U, // PseudoVREDAND_VS_MF8 + 10U, // PseudoVREDAND_VS_MF8_MASK + 10U, // PseudoVREDMAXU_VS_M1 + 10U, // PseudoVREDMAXU_VS_M1_MASK + 10U, // PseudoVREDMAXU_VS_M2 + 10U, // PseudoVREDMAXU_VS_M2_MASK + 10U, // PseudoVREDMAXU_VS_M4 + 10U, // PseudoVREDMAXU_VS_M4_MASK + 10U, // PseudoVREDMAXU_VS_M8 + 10U, // PseudoVREDMAXU_VS_M8_MASK + 10U, // PseudoVREDMAXU_VS_MF2 + 10U, // PseudoVREDMAXU_VS_MF2_MASK + 10U, // PseudoVREDMAXU_VS_MF4 + 10U, // PseudoVREDMAXU_VS_MF4_MASK + 10U, // PseudoVREDMAXU_VS_MF8 + 10U, // PseudoVREDMAXU_VS_MF8_MASK + 10U, // PseudoVREDMAX_VS_M1 + 10U, // PseudoVREDMAX_VS_M1_MASK + 10U, // PseudoVREDMAX_VS_M2 + 10U, // PseudoVREDMAX_VS_M2_MASK + 10U, // PseudoVREDMAX_VS_M4 + 10U, // PseudoVREDMAX_VS_M4_MASK + 10U, // PseudoVREDMAX_VS_M8 + 10U, // PseudoVREDMAX_VS_M8_MASK + 10U, // PseudoVREDMAX_VS_MF2 + 10U, // PseudoVREDMAX_VS_MF2_MASK + 10U, // PseudoVREDMAX_VS_MF4 + 10U, // PseudoVREDMAX_VS_MF4_MASK + 10U, // PseudoVREDMAX_VS_MF8 + 10U, // PseudoVREDMAX_VS_MF8_MASK + 10U, // PseudoVREDMINU_VS_M1 + 10U, // PseudoVREDMINU_VS_M1_MASK + 10U, // PseudoVREDMINU_VS_M2 + 10U, // PseudoVREDMINU_VS_M2_MASK + 10U, // PseudoVREDMINU_VS_M4 + 10U, // PseudoVREDMINU_VS_M4_MASK + 10U, // PseudoVREDMINU_VS_M8 + 10U, // PseudoVREDMINU_VS_M8_MASK + 10U, // PseudoVREDMINU_VS_MF2 + 10U, // PseudoVREDMINU_VS_MF2_MASK + 10U, // PseudoVREDMINU_VS_MF4 + 10U, // PseudoVREDMINU_VS_MF4_MASK + 10U, // PseudoVREDMINU_VS_MF8 + 10U, // PseudoVREDMINU_VS_MF8_MASK + 10U, // PseudoVREDMIN_VS_M1 + 10U, // PseudoVREDMIN_VS_M1_MASK + 10U, // PseudoVREDMIN_VS_M2 + 10U, // PseudoVREDMIN_VS_M2_MASK + 10U, // PseudoVREDMIN_VS_M4 + 10U, // PseudoVREDMIN_VS_M4_MASK + 10U, // PseudoVREDMIN_VS_M8 + 10U, // PseudoVREDMIN_VS_M8_MASK + 10U, // PseudoVREDMIN_VS_MF2 + 10U, // PseudoVREDMIN_VS_MF2_MASK + 10U, // PseudoVREDMIN_VS_MF4 + 10U, // PseudoVREDMIN_VS_MF4_MASK + 10U, // PseudoVREDMIN_VS_MF8 + 10U, // PseudoVREDMIN_VS_MF8_MASK + 10U, // PseudoVREDOR_VS_M1 + 10U, // PseudoVREDOR_VS_M1_MASK + 10U, // PseudoVREDOR_VS_M2 + 10U, // PseudoVREDOR_VS_M2_MASK + 10U, // PseudoVREDOR_VS_M4 + 10U, // PseudoVREDOR_VS_M4_MASK + 10U, // PseudoVREDOR_VS_M8 + 10U, // PseudoVREDOR_VS_M8_MASK + 10U, // PseudoVREDOR_VS_MF2 + 10U, // PseudoVREDOR_VS_MF2_MASK + 10U, // PseudoVREDOR_VS_MF4 + 10U, // PseudoVREDOR_VS_MF4_MASK + 10U, // PseudoVREDOR_VS_MF8 + 10U, // PseudoVREDOR_VS_MF8_MASK + 10U, // PseudoVREDSUM_VS_M1 + 10U, // PseudoVREDSUM_VS_M1_MASK + 10U, // PseudoVREDSUM_VS_M2 + 10U, // PseudoVREDSUM_VS_M2_MASK + 10U, // PseudoVREDSUM_VS_M4 + 10U, // PseudoVREDSUM_VS_M4_MASK + 10U, // PseudoVREDSUM_VS_M8 + 10U, // PseudoVREDSUM_VS_M8_MASK + 10U, // PseudoVREDSUM_VS_MF2 + 10U, // PseudoVREDSUM_VS_MF2_MASK + 10U, // PseudoVREDSUM_VS_MF4 + 10U, // PseudoVREDSUM_VS_MF4_MASK + 10U, // PseudoVREDSUM_VS_MF8 + 10U, // PseudoVREDSUM_VS_MF8_MASK + 10U, // PseudoVREDXOR_VS_M1 + 10U, // PseudoVREDXOR_VS_M1_MASK + 10U, // PseudoVREDXOR_VS_M2 + 10U, // PseudoVREDXOR_VS_M2_MASK + 10U, // PseudoVREDXOR_VS_M4 + 10U, // PseudoVREDXOR_VS_M4_MASK + 10U, // PseudoVREDXOR_VS_M8 + 10U, // PseudoVREDXOR_VS_M8_MASK + 10U, // PseudoVREDXOR_VS_MF2 + 10U, // PseudoVREDXOR_VS_MF2_MASK + 10U, // PseudoVREDXOR_VS_MF4 + 10U, // PseudoVREDXOR_VS_MF4_MASK + 10U, // PseudoVREDXOR_VS_MF8 + 10U, // PseudoVREDXOR_VS_MF8_MASK + 10U, // PseudoVRELOAD2_M1 + 10U, // PseudoVRELOAD2_M2 + 10U, // PseudoVRELOAD2_M4 + 10U, // PseudoVRELOAD2_MF2 + 10U, // PseudoVRELOAD2_MF4 + 10U, // PseudoVRELOAD2_MF8 + 10U, // PseudoVRELOAD3_M1 + 10U, // PseudoVRELOAD3_M2 + 10U, // PseudoVRELOAD3_MF2 + 10U, // PseudoVRELOAD3_MF4 + 10U, // PseudoVRELOAD3_MF8 + 10U, // PseudoVRELOAD4_M1 + 10U, // PseudoVRELOAD4_M2 + 10U, // PseudoVRELOAD4_MF2 + 10U, // PseudoVRELOAD4_MF4 + 10U, // PseudoVRELOAD4_MF8 + 10U, // PseudoVRELOAD5_M1 + 10U, // PseudoVRELOAD5_MF2 + 10U, // PseudoVRELOAD5_MF4 + 10U, // PseudoVRELOAD5_MF8 + 10U, // PseudoVRELOAD6_M1 + 10U, // PseudoVRELOAD6_MF2 + 10U, // PseudoVRELOAD6_MF4 + 10U, // PseudoVRELOAD6_MF8 + 10U, // PseudoVRELOAD7_M1 + 10U, // PseudoVRELOAD7_MF2 + 10U, // PseudoVRELOAD7_MF4 + 10U, // PseudoVRELOAD7_MF8 + 10U, // PseudoVRELOAD8_M1 + 10U, // PseudoVRELOAD8_MF2 + 10U, // PseudoVRELOAD8_MF4 + 10U, // PseudoVRELOAD8_MF8 + 10U, // PseudoVRELOAD_M1 + 10U, // PseudoVRELOAD_M2 + 10U, // PseudoVRELOAD_M4 + 10U, // PseudoVRELOAD_M8 + 10U, // PseudoVREMU_VV_M1 + 10U, // PseudoVREMU_VV_M1_MASK + 10U, // PseudoVREMU_VV_M2 + 10U, // PseudoVREMU_VV_M2_MASK + 10U, // PseudoVREMU_VV_M4 + 10U, // PseudoVREMU_VV_M4_MASK + 10U, // PseudoVREMU_VV_M8 + 10U, // PseudoVREMU_VV_M8_MASK + 10U, // PseudoVREMU_VV_MF2 + 10U, // PseudoVREMU_VV_MF2_MASK + 10U, // PseudoVREMU_VV_MF4 + 10U, // PseudoVREMU_VV_MF4_MASK + 10U, // PseudoVREMU_VV_MF8 + 10U, // PseudoVREMU_VV_MF8_MASK + 10U, // PseudoVREMU_VX_M1 + 10U, // PseudoVREMU_VX_M1_MASK + 10U, // PseudoVREMU_VX_M2 + 10U, // PseudoVREMU_VX_M2_MASK + 10U, // PseudoVREMU_VX_M4 + 10U, // PseudoVREMU_VX_M4_MASK + 10U, // PseudoVREMU_VX_M8 + 10U, // PseudoVREMU_VX_M8_MASK + 10U, // PseudoVREMU_VX_MF2 + 10U, // PseudoVREMU_VX_MF2_MASK + 10U, // PseudoVREMU_VX_MF4 + 10U, // PseudoVREMU_VX_MF4_MASK + 10U, // PseudoVREMU_VX_MF8 + 10U, // PseudoVREMU_VX_MF8_MASK + 10U, // PseudoVREM_VV_M1 + 10U, // PseudoVREM_VV_M1_MASK + 10U, // PseudoVREM_VV_M2 + 10U, // PseudoVREM_VV_M2_MASK + 10U, // PseudoVREM_VV_M4 + 10U, // PseudoVREM_VV_M4_MASK + 10U, // PseudoVREM_VV_M8 + 10U, // PseudoVREM_VV_M8_MASK + 10U, // PseudoVREM_VV_MF2 + 10U, // PseudoVREM_VV_MF2_MASK + 10U, // PseudoVREM_VV_MF4 + 10U, // PseudoVREM_VV_MF4_MASK + 10U, // PseudoVREM_VV_MF8 + 10U, // PseudoVREM_VV_MF8_MASK + 10U, // PseudoVREM_VX_M1 + 10U, // PseudoVREM_VX_M1_MASK + 10U, // PseudoVREM_VX_M2 + 10U, // PseudoVREM_VX_M2_MASK + 10U, // PseudoVREM_VX_M4 + 10U, // PseudoVREM_VX_M4_MASK + 10U, // PseudoVREM_VX_M8 + 10U, // PseudoVREM_VX_M8_MASK + 10U, // PseudoVREM_VX_MF2 + 10U, // PseudoVREM_VX_MF2_MASK + 10U, // PseudoVREM_VX_MF4 + 10U, // PseudoVREM_VX_MF4_MASK + 10U, // PseudoVREM_VX_MF8 + 10U, // PseudoVREM_VX_MF8_MASK + 10U, // PseudoVRGATHEREI16_VV_M1_M1 + 10U, // PseudoVRGATHEREI16_VV_M1_M1_MASK + 10U, // PseudoVRGATHEREI16_VV_M1_M2 + 10U, // PseudoVRGATHEREI16_VV_M1_M2_MASK + 10U, // PseudoVRGATHEREI16_VV_M1_MF2 + 10U, // PseudoVRGATHEREI16_VV_M1_MF2_MASK + 10U, // PseudoVRGATHEREI16_VV_M1_MF4 + 10U, // PseudoVRGATHEREI16_VV_M1_MF4_MASK + 10U, // PseudoVRGATHEREI16_VV_M2_M1 + 10U, // PseudoVRGATHEREI16_VV_M2_M1_MASK + 10U, // PseudoVRGATHEREI16_VV_M2_M2 + 10U, // PseudoVRGATHEREI16_VV_M2_M2_MASK + 10U, // PseudoVRGATHEREI16_VV_M2_M4 + 10U, // PseudoVRGATHEREI16_VV_M2_M4_MASK + 10U, // PseudoVRGATHEREI16_VV_M2_MF2 + 10U, // PseudoVRGATHEREI16_VV_M2_MF2_MASK + 10U, // PseudoVRGATHEREI16_VV_M4_M1 + 10U, // PseudoVRGATHEREI16_VV_M4_M1_MASK + 10U, // PseudoVRGATHEREI16_VV_M4_M2 + 10U, // PseudoVRGATHEREI16_VV_M4_M2_MASK + 10U, // PseudoVRGATHEREI16_VV_M4_M4 + 10U, // PseudoVRGATHEREI16_VV_M4_M4_MASK + 10U, // PseudoVRGATHEREI16_VV_M4_M8 + 10U, // PseudoVRGATHEREI16_VV_M4_M8_MASK + 10U, // PseudoVRGATHEREI16_VV_M8_M2 + 10U, // PseudoVRGATHEREI16_VV_M8_M2_MASK + 10U, // PseudoVRGATHEREI16_VV_M8_M4 + 10U, // PseudoVRGATHEREI16_VV_M8_M4_MASK + 10U, // PseudoVRGATHEREI16_VV_M8_M8 + 10U, // PseudoVRGATHEREI16_VV_M8_M8_MASK + 10U, // PseudoVRGATHEREI16_VV_MF2_M1 + 10U, // PseudoVRGATHEREI16_VV_MF2_M1_MASK + 10U, // PseudoVRGATHEREI16_VV_MF2_MF2 + 10U, // PseudoVRGATHEREI16_VV_MF2_MF2_MASK + 10U, // PseudoVRGATHEREI16_VV_MF2_MF4 + 10U, // PseudoVRGATHEREI16_VV_MF2_MF4_MASK + 10U, // PseudoVRGATHEREI16_VV_MF2_MF8 + 10U, // PseudoVRGATHEREI16_VV_MF2_MF8_MASK + 10U, // PseudoVRGATHEREI16_VV_MF4_MF2 + 10U, // PseudoVRGATHEREI16_VV_MF4_MF2_MASK + 10U, // PseudoVRGATHEREI16_VV_MF4_MF4 + 10U, // PseudoVRGATHEREI16_VV_MF4_MF4_MASK + 10U, // PseudoVRGATHEREI16_VV_MF4_MF8 + 10U, // PseudoVRGATHEREI16_VV_MF4_MF8_MASK + 10U, // PseudoVRGATHEREI16_VV_MF8_MF4 + 10U, // PseudoVRGATHEREI16_VV_MF8_MF4_MASK + 10U, // PseudoVRGATHEREI16_VV_MF8_MF8 + 10U, // PseudoVRGATHEREI16_VV_MF8_MF8_MASK + 10U, // PseudoVRGATHER_VI_M1 + 10U, // PseudoVRGATHER_VI_M1_MASK + 10U, // PseudoVRGATHER_VI_M2 + 10U, // PseudoVRGATHER_VI_M2_MASK + 10U, // PseudoVRGATHER_VI_M4 + 10U, // PseudoVRGATHER_VI_M4_MASK + 10U, // PseudoVRGATHER_VI_M8 + 10U, // PseudoVRGATHER_VI_M8_MASK + 10U, // PseudoVRGATHER_VI_MF2 + 10U, // PseudoVRGATHER_VI_MF2_MASK + 10U, // PseudoVRGATHER_VI_MF4 + 10U, // PseudoVRGATHER_VI_MF4_MASK + 10U, // PseudoVRGATHER_VI_MF8 + 10U, // PseudoVRGATHER_VI_MF8_MASK + 10U, // PseudoVRGATHER_VV_M1 + 10U, // PseudoVRGATHER_VV_M1_MASK + 10U, // PseudoVRGATHER_VV_M2 + 10U, // PseudoVRGATHER_VV_M2_MASK + 10U, // PseudoVRGATHER_VV_M4 + 10U, // PseudoVRGATHER_VV_M4_MASK + 10U, // PseudoVRGATHER_VV_M8 + 10U, // PseudoVRGATHER_VV_M8_MASK + 10U, // PseudoVRGATHER_VV_MF2 + 10U, // PseudoVRGATHER_VV_MF2_MASK + 10U, // PseudoVRGATHER_VV_MF4 + 10U, // PseudoVRGATHER_VV_MF4_MASK + 10U, // PseudoVRGATHER_VV_MF8 + 10U, // PseudoVRGATHER_VV_MF8_MASK + 10U, // PseudoVRGATHER_VX_M1 + 10U, // PseudoVRGATHER_VX_M1_MASK + 10U, // PseudoVRGATHER_VX_M2 + 10U, // PseudoVRGATHER_VX_M2_MASK + 10U, // PseudoVRGATHER_VX_M4 + 10U, // PseudoVRGATHER_VX_M4_MASK + 10U, // PseudoVRGATHER_VX_M8 + 10U, // PseudoVRGATHER_VX_M8_MASK + 10U, // PseudoVRGATHER_VX_MF2 + 10U, // PseudoVRGATHER_VX_MF2_MASK + 10U, // PseudoVRGATHER_VX_MF4 + 10U, // PseudoVRGATHER_VX_MF4_MASK + 10U, // PseudoVRGATHER_VX_MF8 + 10U, // PseudoVRGATHER_VX_MF8_MASK + 10U, // PseudoVRSUB_VI_M1 + 10U, // PseudoVRSUB_VI_M1_MASK + 10U, // PseudoVRSUB_VI_M2 + 10U, // PseudoVRSUB_VI_M2_MASK + 10U, // PseudoVRSUB_VI_M4 + 10U, // PseudoVRSUB_VI_M4_MASK + 10U, // PseudoVRSUB_VI_M8 + 10U, // PseudoVRSUB_VI_M8_MASK + 10U, // PseudoVRSUB_VI_MF2 + 10U, // PseudoVRSUB_VI_MF2_MASK + 10U, // PseudoVRSUB_VI_MF4 + 10U, // PseudoVRSUB_VI_MF4_MASK + 10U, // PseudoVRSUB_VI_MF8 + 10U, // PseudoVRSUB_VI_MF8_MASK + 10U, // PseudoVRSUB_VX_M1 + 10U, // PseudoVRSUB_VX_M1_MASK + 10U, // PseudoVRSUB_VX_M2 + 10U, // PseudoVRSUB_VX_M2_MASK + 10U, // PseudoVRSUB_VX_M4 + 10U, // PseudoVRSUB_VX_M4_MASK + 10U, // PseudoVRSUB_VX_M8 + 10U, // PseudoVRSUB_VX_M8_MASK + 10U, // PseudoVRSUB_VX_MF2 + 10U, // PseudoVRSUB_VX_MF2_MASK + 10U, // PseudoVRSUB_VX_MF4 + 10U, // PseudoVRSUB_VX_MF4_MASK + 10U, // PseudoVRSUB_VX_MF8 + 10U, // PseudoVRSUB_VX_MF8_MASK + 10U, // PseudoVSADDU_VI_M1 + 10U, // PseudoVSADDU_VI_M1_MASK + 10U, // PseudoVSADDU_VI_M2 + 10U, // PseudoVSADDU_VI_M2_MASK + 10U, // PseudoVSADDU_VI_M4 + 10U, // PseudoVSADDU_VI_M4_MASK + 10U, // PseudoVSADDU_VI_M8 + 10U, // PseudoVSADDU_VI_M8_MASK + 10U, // PseudoVSADDU_VI_MF2 + 10U, // PseudoVSADDU_VI_MF2_MASK + 10U, // PseudoVSADDU_VI_MF4 + 10U, // PseudoVSADDU_VI_MF4_MASK + 10U, // PseudoVSADDU_VI_MF8 + 10U, // PseudoVSADDU_VI_MF8_MASK + 10U, // PseudoVSADDU_VV_M1 + 10U, // PseudoVSADDU_VV_M1_MASK + 10U, // PseudoVSADDU_VV_M2 + 10U, // PseudoVSADDU_VV_M2_MASK + 10U, // PseudoVSADDU_VV_M4 + 10U, // PseudoVSADDU_VV_M4_MASK + 10U, // PseudoVSADDU_VV_M8 + 10U, // PseudoVSADDU_VV_M8_MASK + 10U, // PseudoVSADDU_VV_MF2 + 10U, // PseudoVSADDU_VV_MF2_MASK + 10U, // PseudoVSADDU_VV_MF4 + 10U, // PseudoVSADDU_VV_MF4_MASK + 10U, // PseudoVSADDU_VV_MF8 + 10U, // PseudoVSADDU_VV_MF8_MASK + 10U, // PseudoVSADDU_VX_M1 + 10U, // PseudoVSADDU_VX_M1_MASK + 10U, // PseudoVSADDU_VX_M2 + 10U, // PseudoVSADDU_VX_M2_MASK + 10U, // PseudoVSADDU_VX_M4 + 10U, // PseudoVSADDU_VX_M4_MASK + 10U, // PseudoVSADDU_VX_M8 + 10U, // PseudoVSADDU_VX_M8_MASK + 10U, // PseudoVSADDU_VX_MF2 + 10U, // PseudoVSADDU_VX_MF2_MASK + 10U, // PseudoVSADDU_VX_MF4 + 10U, // PseudoVSADDU_VX_MF4_MASK + 10U, // PseudoVSADDU_VX_MF8 + 10U, // PseudoVSADDU_VX_MF8_MASK + 10U, // PseudoVSADD_VI_M1 + 10U, // PseudoVSADD_VI_M1_MASK + 10U, // PseudoVSADD_VI_M2 + 10U, // PseudoVSADD_VI_M2_MASK + 10U, // PseudoVSADD_VI_M4 + 10U, // PseudoVSADD_VI_M4_MASK + 10U, // PseudoVSADD_VI_M8 + 10U, // PseudoVSADD_VI_M8_MASK + 10U, // PseudoVSADD_VI_MF2 + 10U, // PseudoVSADD_VI_MF2_MASK + 10U, // PseudoVSADD_VI_MF4 + 10U, // PseudoVSADD_VI_MF4_MASK + 10U, // PseudoVSADD_VI_MF8 + 10U, // PseudoVSADD_VI_MF8_MASK + 10U, // PseudoVSADD_VV_M1 + 10U, // PseudoVSADD_VV_M1_MASK + 10U, // PseudoVSADD_VV_M2 + 10U, // PseudoVSADD_VV_M2_MASK + 10U, // PseudoVSADD_VV_M4 + 10U, // PseudoVSADD_VV_M4_MASK + 10U, // PseudoVSADD_VV_M8 + 10U, // PseudoVSADD_VV_M8_MASK + 10U, // PseudoVSADD_VV_MF2 + 10U, // PseudoVSADD_VV_MF2_MASK + 10U, // PseudoVSADD_VV_MF4 + 10U, // PseudoVSADD_VV_MF4_MASK + 10U, // PseudoVSADD_VV_MF8 + 10U, // PseudoVSADD_VV_MF8_MASK + 10U, // PseudoVSADD_VX_M1 + 10U, // PseudoVSADD_VX_M1_MASK + 10U, // PseudoVSADD_VX_M2 + 10U, // PseudoVSADD_VX_M2_MASK + 10U, // PseudoVSADD_VX_M4 + 10U, // PseudoVSADD_VX_M4_MASK + 10U, // PseudoVSADD_VX_M8 + 10U, // PseudoVSADD_VX_M8_MASK + 10U, // PseudoVSADD_VX_MF2 + 10U, // PseudoVSADD_VX_MF2_MASK + 10U, // PseudoVSADD_VX_MF4 + 10U, // PseudoVSADD_VX_MF4_MASK + 10U, // PseudoVSADD_VX_MF8 + 10U, // PseudoVSADD_VX_MF8_MASK + 10U, // PseudoVSBC_VVM_M1 + 10U, // PseudoVSBC_VVM_M2 + 10U, // PseudoVSBC_VVM_M4 + 10U, // PseudoVSBC_VVM_M8 + 10U, // PseudoVSBC_VVM_MF2 + 10U, // PseudoVSBC_VVM_MF4 + 10U, // PseudoVSBC_VVM_MF8 + 10U, // PseudoVSBC_VXM_M1 + 10U, // PseudoVSBC_VXM_M2 + 10U, // PseudoVSBC_VXM_M4 + 10U, // PseudoVSBC_VXM_M8 + 10U, // PseudoVSBC_VXM_MF2 + 10U, // PseudoVSBC_VXM_MF4 + 10U, // PseudoVSBC_VXM_MF8 + 10U, // PseudoVSE16_V_M1 + 10U, // PseudoVSE16_V_M1_MASK + 10U, // PseudoVSE16_V_M2 + 10U, // PseudoVSE16_V_M2_MASK + 10U, // PseudoVSE16_V_M4 + 10U, // PseudoVSE16_V_M4_MASK + 10U, // PseudoVSE16_V_M8 + 10U, // PseudoVSE16_V_M8_MASK + 10U, // PseudoVSE16_V_MF2 + 10U, // PseudoVSE16_V_MF2_MASK + 10U, // PseudoVSE16_V_MF4 + 10U, // PseudoVSE16_V_MF4_MASK + 10U, // PseudoVSE32_V_M1 + 10U, // PseudoVSE32_V_M1_MASK + 10U, // PseudoVSE32_V_M2 + 10U, // PseudoVSE32_V_M2_MASK + 10U, // PseudoVSE32_V_M4 + 10U, // PseudoVSE32_V_M4_MASK + 10U, // PseudoVSE32_V_M8 + 10U, // PseudoVSE32_V_M8_MASK + 10U, // PseudoVSE32_V_MF2 + 10U, // PseudoVSE32_V_MF2_MASK + 10U, // PseudoVSE64_V_M1 + 10U, // PseudoVSE64_V_M1_MASK + 10U, // PseudoVSE64_V_M2 + 10U, // PseudoVSE64_V_M2_MASK + 10U, // PseudoVSE64_V_M4 + 10U, // PseudoVSE64_V_M4_MASK + 10U, // PseudoVSE64_V_M8 + 10U, // PseudoVSE64_V_M8_MASK + 10U, // PseudoVSE8_V_M1 + 10U, // PseudoVSE8_V_M1_MASK + 10U, // PseudoVSE8_V_M2 + 10U, // PseudoVSE8_V_M2_MASK + 10U, // PseudoVSE8_V_M4 + 10U, // PseudoVSE8_V_M4_MASK + 10U, // PseudoVSE8_V_M8 + 10U, // PseudoVSE8_V_M8_MASK + 10U, // PseudoVSE8_V_MF2 + 10U, // PseudoVSE8_V_MF2_MASK + 10U, // PseudoVSE8_V_MF4 + 10U, // PseudoVSE8_V_MF4_MASK + 10U, // PseudoVSE8_V_MF8 + 10U, // PseudoVSE8_V_MF8_MASK + 10U, // PseudoVSETIVLI + 10U, // PseudoVSETVLI + 10U, // PseudoVSETVLIX0 + 10U, // PseudoVSEXT_VF2_M1 + 10U, // PseudoVSEXT_VF2_M1_MASK + 10U, // PseudoVSEXT_VF2_M2 + 10U, // PseudoVSEXT_VF2_M2_MASK + 10U, // PseudoVSEXT_VF2_M4 + 10U, // PseudoVSEXT_VF2_M4_MASK + 10U, // PseudoVSEXT_VF2_M8 + 10U, // PseudoVSEXT_VF2_M8_MASK + 10U, // PseudoVSEXT_VF2_MF2 + 10U, // PseudoVSEXT_VF2_MF2_MASK + 10U, // PseudoVSEXT_VF2_MF4 + 10U, // PseudoVSEXT_VF2_MF4_MASK + 10U, // PseudoVSEXT_VF4_M1 + 10U, // PseudoVSEXT_VF4_M1_MASK + 10U, // PseudoVSEXT_VF4_M2 + 10U, // PseudoVSEXT_VF4_M2_MASK + 10U, // PseudoVSEXT_VF4_M4 + 10U, // PseudoVSEXT_VF4_M4_MASK + 10U, // PseudoVSEXT_VF4_M8 + 10U, // PseudoVSEXT_VF4_M8_MASK + 10U, // PseudoVSEXT_VF4_MF2 + 10U, // PseudoVSEXT_VF4_MF2_MASK + 10U, // PseudoVSEXT_VF8_M1 + 10U, // PseudoVSEXT_VF8_M1_MASK + 10U, // PseudoVSEXT_VF8_M2 + 10U, // PseudoVSEXT_VF8_M2_MASK + 10U, // PseudoVSEXT_VF8_M4 + 10U, // PseudoVSEXT_VF8_M4_MASK + 10U, // PseudoVSEXT_VF8_M8 + 10U, // PseudoVSEXT_VF8_M8_MASK + 10U, // PseudoVSLIDE1DOWN_VX_M1 + 10U, // PseudoVSLIDE1DOWN_VX_M1_MASK + 10U, // PseudoVSLIDE1DOWN_VX_M2 + 10U, // PseudoVSLIDE1DOWN_VX_M2_MASK + 10U, // PseudoVSLIDE1DOWN_VX_M4 + 10U, // PseudoVSLIDE1DOWN_VX_M4_MASK + 10U, // PseudoVSLIDE1DOWN_VX_M8 + 10U, // PseudoVSLIDE1DOWN_VX_M8_MASK + 10U, // PseudoVSLIDE1DOWN_VX_MF2 + 10U, // PseudoVSLIDE1DOWN_VX_MF2_MASK + 10U, // PseudoVSLIDE1DOWN_VX_MF4 + 10U, // PseudoVSLIDE1DOWN_VX_MF4_MASK + 10U, // PseudoVSLIDE1DOWN_VX_MF8 + 10U, // PseudoVSLIDE1DOWN_VX_MF8_MASK + 10U, // PseudoVSLIDE1UP_VX_M1 + 10U, // PseudoVSLIDE1UP_VX_M1_MASK + 10U, // PseudoVSLIDE1UP_VX_M2 + 10U, // PseudoVSLIDE1UP_VX_M2_MASK + 10U, // PseudoVSLIDE1UP_VX_M4 + 10U, // PseudoVSLIDE1UP_VX_M4_MASK + 10U, // PseudoVSLIDE1UP_VX_M8 + 10U, // PseudoVSLIDE1UP_VX_M8_MASK + 10U, // PseudoVSLIDE1UP_VX_MF2 + 10U, // PseudoVSLIDE1UP_VX_MF2_MASK + 10U, // PseudoVSLIDE1UP_VX_MF4 + 10U, // PseudoVSLIDE1UP_VX_MF4_MASK + 10U, // PseudoVSLIDE1UP_VX_MF8 + 10U, // PseudoVSLIDE1UP_VX_MF8_MASK + 10U, // PseudoVSLIDEDOWN_VI_M1 + 10U, // PseudoVSLIDEDOWN_VI_M1_MASK + 10U, // PseudoVSLIDEDOWN_VI_M2 + 10U, // PseudoVSLIDEDOWN_VI_M2_MASK + 10U, // PseudoVSLIDEDOWN_VI_M4 + 10U, // PseudoVSLIDEDOWN_VI_M4_MASK + 10U, // PseudoVSLIDEDOWN_VI_M8 + 10U, // PseudoVSLIDEDOWN_VI_M8_MASK + 10U, // PseudoVSLIDEDOWN_VI_MF2 + 10U, // PseudoVSLIDEDOWN_VI_MF2_MASK + 10U, // PseudoVSLIDEDOWN_VI_MF4 + 10U, // PseudoVSLIDEDOWN_VI_MF4_MASK + 10U, // PseudoVSLIDEDOWN_VI_MF8 + 10U, // PseudoVSLIDEDOWN_VI_MF8_MASK + 10U, // PseudoVSLIDEDOWN_VX_M1 + 10U, // PseudoVSLIDEDOWN_VX_M1_MASK + 10U, // PseudoVSLIDEDOWN_VX_M2 + 10U, // PseudoVSLIDEDOWN_VX_M2_MASK + 10U, // PseudoVSLIDEDOWN_VX_M4 + 10U, // PseudoVSLIDEDOWN_VX_M4_MASK + 10U, // PseudoVSLIDEDOWN_VX_M8 + 10U, // PseudoVSLIDEDOWN_VX_M8_MASK + 10U, // PseudoVSLIDEDOWN_VX_MF2 + 10U, // PseudoVSLIDEDOWN_VX_MF2_MASK + 10U, // PseudoVSLIDEDOWN_VX_MF4 + 10U, // PseudoVSLIDEDOWN_VX_MF4_MASK + 10U, // PseudoVSLIDEDOWN_VX_MF8 + 10U, // PseudoVSLIDEDOWN_VX_MF8_MASK + 10U, // PseudoVSLIDEUP_VI_M1 + 10U, // PseudoVSLIDEUP_VI_M1_MASK + 10U, // PseudoVSLIDEUP_VI_M2 + 10U, // PseudoVSLIDEUP_VI_M2_MASK + 10U, // PseudoVSLIDEUP_VI_M4 + 10U, // PseudoVSLIDEUP_VI_M4_MASK + 10U, // PseudoVSLIDEUP_VI_M8 + 10U, // PseudoVSLIDEUP_VI_M8_MASK + 10U, // PseudoVSLIDEUP_VI_MF2 + 10U, // PseudoVSLIDEUP_VI_MF2_MASK + 10U, // PseudoVSLIDEUP_VI_MF4 + 10U, // PseudoVSLIDEUP_VI_MF4_MASK + 10U, // PseudoVSLIDEUP_VI_MF8 + 10U, // PseudoVSLIDEUP_VI_MF8_MASK + 10U, // PseudoVSLIDEUP_VX_M1 + 10U, // PseudoVSLIDEUP_VX_M1_MASK + 10U, // PseudoVSLIDEUP_VX_M2 + 10U, // PseudoVSLIDEUP_VX_M2_MASK + 10U, // PseudoVSLIDEUP_VX_M4 + 10U, // PseudoVSLIDEUP_VX_M4_MASK + 10U, // PseudoVSLIDEUP_VX_M8 + 10U, // PseudoVSLIDEUP_VX_M8_MASK + 10U, // PseudoVSLIDEUP_VX_MF2 + 10U, // PseudoVSLIDEUP_VX_MF2_MASK + 10U, // PseudoVSLIDEUP_VX_MF4 + 10U, // PseudoVSLIDEUP_VX_MF4_MASK + 10U, // PseudoVSLIDEUP_VX_MF8 + 10U, // PseudoVSLIDEUP_VX_MF8_MASK + 10U, // PseudoVSLL_VI_M1 + 10U, // PseudoVSLL_VI_M1_MASK + 10U, // PseudoVSLL_VI_M2 + 10U, // PseudoVSLL_VI_M2_MASK + 10U, // PseudoVSLL_VI_M4 + 10U, // PseudoVSLL_VI_M4_MASK + 10U, // PseudoVSLL_VI_M8 + 10U, // PseudoVSLL_VI_M8_MASK + 10U, // PseudoVSLL_VI_MF2 + 10U, // PseudoVSLL_VI_MF2_MASK + 10U, // PseudoVSLL_VI_MF4 + 10U, // PseudoVSLL_VI_MF4_MASK + 10U, // PseudoVSLL_VI_MF8 + 10U, // PseudoVSLL_VI_MF8_MASK + 10U, // PseudoVSLL_VV_M1 + 10U, // PseudoVSLL_VV_M1_MASK + 10U, // PseudoVSLL_VV_M2 + 10U, // PseudoVSLL_VV_M2_MASK + 10U, // PseudoVSLL_VV_M4 + 10U, // PseudoVSLL_VV_M4_MASK + 10U, // PseudoVSLL_VV_M8 + 10U, // PseudoVSLL_VV_M8_MASK + 10U, // PseudoVSLL_VV_MF2 + 10U, // PseudoVSLL_VV_MF2_MASK + 10U, // PseudoVSLL_VV_MF4 + 10U, // PseudoVSLL_VV_MF4_MASK + 10U, // PseudoVSLL_VV_MF8 + 10U, // PseudoVSLL_VV_MF8_MASK + 10U, // PseudoVSLL_VX_M1 + 10U, // PseudoVSLL_VX_M1_MASK + 10U, // PseudoVSLL_VX_M2 + 10U, // PseudoVSLL_VX_M2_MASK + 10U, // PseudoVSLL_VX_M4 + 10U, // PseudoVSLL_VX_M4_MASK + 10U, // PseudoVSLL_VX_M8 + 10U, // PseudoVSLL_VX_M8_MASK + 10U, // PseudoVSLL_VX_MF2 + 10U, // PseudoVSLL_VX_MF2_MASK + 10U, // PseudoVSLL_VX_MF4 + 10U, // PseudoVSLL_VX_MF4_MASK + 10U, // PseudoVSLL_VX_MF8 + 10U, // PseudoVSLL_VX_MF8_MASK + 10U, // PseudoVSMUL_VV_M1 + 10U, // PseudoVSMUL_VV_M1_MASK + 10U, // PseudoVSMUL_VV_M2 + 10U, // PseudoVSMUL_VV_M2_MASK + 10U, // PseudoVSMUL_VV_M4 + 10U, // PseudoVSMUL_VV_M4_MASK + 10U, // PseudoVSMUL_VV_M8 + 10U, // PseudoVSMUL_VV_M8_MASK + 10U, // PseudoVSMUL_VV_MF2 + 10U, // PseudoVSMUL_VV_MF2_MASK + 10U, // PseudoVSMUL_VV_MF4 + 10U, // PseudoVSMUL_VV_MF4_MASK + 10U, // PseudoVSMUL_VV_MF8 + 10U, // PseudoVSMUL_VV_MF8_MASK + 10U, // PseudoVSMUL_VX_M1 + 10U, // PseudoVSMUL_VX_M1_MASK + 10U, // PseudoVSMUL_VX_M2 + 10U, // PseudoVSMUL_VX_M2_MASK + 10U, // PseudoVSMUL_VX_M4 + 10U, // PseudoVSMUL_VX_M4_MASK + 10U, // PseudoVSMUL_VX_M8 + 10U, // PseudoVSMUL_VX_M8_MASK + 10U, // PseudoVSMUL_VX_MF2 + 10U, // PseudoVSMUL_VX_MF2_MASK + 10U, // PseudoVSMUL_VX_MF4 + 10U, // PseudoVSMUL_VX_MF4_MASK + 10U, // PseudoVSMUL_VX_MF8 + 10U, // PseudoVSMUL_VX_MF8_MASK + 10U, // PseudoVSM_V_B1 + 10U, // PseudoVSM_V_B16 + 10U, // PseudoVSM_V_B2 + 10U, // PseudoVSM_V_B32 + 10U, // PseudoVSM_V_B4 + 10U, // PseudoVSM_V_B64 + 10U, // PseudoVSM_V_B8 + 10U, // PseudoVSOXEI16_V_M1_M1 + 10U, // PseudoVSOXEI16_V_M1_M1_MASK + 10U, // PseudoVSOXEI16_V_M1_M2 + 10U, // PseudoVSOXEI16_V_M1_M2_MASK + 10U, // PseudoVSOXEI16_V_M1_M4 + 10U, // PseudoVSOXEI16_V_M1_M4_MASK + 10U, // PseudoVSOXEI16_V_M1_MF2 + 10U, // PseudoVSOXEI16_V_M1_MF2_MASK + 10U, // PseudoVSOXEI16_V_M2_M1 + 10U, // PseudoVSOXEI16_V_M2_M1_MASK + 10U, // PseudoVSOXEI16_V_M2_M2 + 10U, // PseudoVSOXEI16_V_M2_M2_MASK + 10U, // PseudoVSOXEI16_V_M2_M4 + 10U, // PseudoVSOXEI16_V_M2_M4_MASK + 10U, // PseudoVSOXEI16_V_M2_M8 + 10U, // PseudoVSOXEI16_V_M2_M8_MASK + 10U, // PseudoVSOXEI16_V_M4_M2 + 10U, // PseudoVSOXEI16_V_M4_M2_MASK + 10U, // PseudoVSOXEI16_V_M4_M4 + 10U, // PseudoVSOXEI16_V_M4_M4_MASK + 10U, // PseudoVSOXEI16_V_M4_M8 + 10U, // PseudoVSOXEI16_V_M4_M8_MASK + 10U, // PseudoVSOXEI16_V_M8_M4 + 10U, // PseudoVSOXEI16_V_M8_M4_MASK + 10U, // PseudoVSOXEI16_V_M8_M8 + 10U, // PseudoVSOXEI16_V_M8_M8_MASK + 10U, // PseudoVSOXEI16_V_MF2_M1 + 10U, // PseudoVSOXEI16_V_MF2_M1_MASK + 10U, // PseudoVSOXEI16_V_MF2_M2 + 10U, // PseudoVSOXEI16_V_MF2_M2_MASK + 10U, // PseudoVSOXEI16_V_MF2_MF2 + 10U, // PseudoVSOXEI16_V_MF2_MF2_MASK + 10U, // PseudoVSOXEI16_V_MF2_MF4 + 10U, // PseudoVSOXEI16_V_MF2_MF4_MASK + 10U, // PseudoVSOXEI16_V_MF4_M1 + 10U, // PseudoVSOXEI16_V_MF4_M1_MASK + 10U, // PseudoVSOXEI16_V_MF4_MF2 + 10U, // PseudoVSOXEI16_V_MF4_MF2_MASK + 10U, // PseudoVSOXEI16_V_MF4_MF4 + 10U, // PseudoVSOXEI16_V_MF4_MF4_MASK + 10U, // PseudoVSOXEI16_V_MF4_MF8 + 10U, // PseudoVSOXEI16_V_MF4_MF8_MASK + 10U, // PseudoVSOXEI32_V_M1_M1 + 10U, // PseudoVSOXEI32_V_M1_M1_MASK + 10U, // PseudoVSOXEI32_V_M1_M2 + 10U, // PseudoVSOXEI32_V_M1_M2_MASK + 10U, // PseudoVSOXEI32_V_M1_MF2 + 10U, // PseudoVSOXEI32_V_M1_MF2_MASK + 10U, // PseudoVSOXEI32_V_M1_MF4 + 10U, // PseudoVSOXEI32_V_M1_MF4_MASK + 10U, // PseudoVSOXEI32_V_M2_M1 + 10U, // PseudoVSOXEI32_V_M2_M1_MASK + 10U, // PseudoVSOXEI32_V_M2_M2 + 10U, // PseudoVSOXEI32_V_M2_M2_MASK + 10U, // PseudoVSOXEI32_V_M2_M4 + 10U, // PseudoVSOXEI32_V_M2_M4_MASK + 10U, // PseudoVSOXEI32_V_M2_MF2 + 10U, // PseudoVSOXEI32_V_M2_MF2_MASK + 10U, // PseudoVSOXEI32_V_M4_M1 + 10U, // PseudoVSOXEI32_V_M4_M1_MASK + 10U, // PseudoVSOXEI32_V_M4_M2 + 10U, // PseudoVSOXEI32_V_M4_M2_MASK + 10U, // PseudoVSOXEI32_V_M4_M4 + 10U, // PseudoVSOXEI32_V_M4_M4_MASK + 10U, // PseudoVSOXEI32_V_M4_M8 + 10U, // PseudoVSOXEI32_V_M4_M8_MASK + 10U, // PseudoVSOXEI32_V_M8_M2 + 10U, // PseudoVSOXEI32_V_M8_M2_MASK + 10U, // PseudoVSOXEI32_V_M8_M4 + 10U, // PseudoVSOXEI32_V_M8_M4_MASK + 10U, // PseudoVSOXEI32_V_M8_M8 + 10U, // PseudoVSOXEI32_V_M8_M8_MASK + 10U, // PseudoVSOXEI32_V_MF2_M1 + 10U, // PseudoVSOXEI32_V_MF2_M1_MASK + 10U, // PseudoVSOXEI32_V_MF2_MF2 + 10U, // PseudoVSOXEI32_V_MF2_MF2_MASK + 10U, // PseudoVSOXEI32_V_MF2_MF4 + 10U, // PseudoVSOXEI32_V_MF2_MF4_MASK + 10U, // PseudoVSOXEI32_V_MF2_MF8 + 10U, // PseudoVSOXEI32_V_MF2_MF8_MASK + 10U, // PseudoVSOXEI64_V_M1_M1 + 10U, // PseudoVSOXEI64_V_M1_M1_MASK + 10U, // PseudoVSOXEI64_V_M1_MF2 + 10U, // PseudoVSOXEI64_V_M1_MF2_MASK + 10U, // PseudoVSOXEI64_V_M1_MF4 + 10U, // PseudoVSOXEI64_V_M1_MF4_MASK + 10U, // PseudoVSOXEI64_V_M1_MF8 + 10U, // PseudoVSOXEI64_V_M1_MF8_MASK + 10U, // PseudoVSOXEI64_V_M2_M1 + 10U, // PseudoVSOXEI64_V_M2_M1_MASK + 10U, // PseudoVSOXEI64_V_M2_M2 + 10U, // PseudoVSOXEI64_V_M2_M2_MASK + 10U, // PseudoVSOXEI64_V_M2_MF2 + 10U, // PseudoVSOXEI64_V_M2_MF2_MASK + 10U, // PseudoVSOXEI64_V_M2_MF4 + 10U, // PseudoVSOXEI64_V_M2_MF4_MASK + 10U, // PseudoVSOXEI64_V_M4_M1 + 10U, // PseudoVSOXEI64_V_M4_M1_MASK + 10U, // PseudoVSOXEI64_V_M4_M2 + 10U, // PseudoVSOXEI64_V_M4_M2_MASK + 10U, // PseudoVSOXEI64_V_M4_M4 + 10U, // PseudoVSOXEI64_V_M4_M4_MASK + 10U, // PseudoVSOXEI64_V_M4_MF2 + 10U, // PseudoVSOXEI64_V_M4_MF2_MASK + 10U, // PseudoVSOXEI64_V_M8_M1 + 10U, // PseudoVSOXEI64_V_M8_M1_MASK + 10U, // PseudoVSOXEI64_V_M8_M2 + 10U, // PseudoVSOXEI64_V_M8_M2_MASK + 10U, // PseudoVSOXEI64_V_M8_M4 + 10U, // PseudoVSOXEI64_V_M8_M4_MASK + 10U, // PseudoVSOXEI64_V_M8_M8 + 10U, // PseudoVSOXEI64_V_M8_M8_MASK + 10U, // PseudoVSOXEI8_V_M1_M1 + 10U, // PseudoVSOXEI8_V_M1_M1_MASK + 10U, // PseudoVSOXEI8_V_M1_M2 + 10U, // PseudoVSOXEI8_V_M1_M2_MASK + 10U, // PseudoVSOXEI8_V_M1_M4 + 10U, // PseudoVSOXEI8_V_M1_M4_MASK + 10U, // PseudoVSOXEI8_V_M1_M8 + 10U, // PseudoVSOXEI8_V_M1_M8_MASK + 10U, // PseudoVSOXEI8_V_M2_M2 + 10U, // PseudoVSOXEI8_V_M2_M2_MASK + 10U, // PseudoVSOXEI8_V_M2_M4 + 10U, // PseudoVSOXEI8_V_M2_M4_MASK + 10U, // PseudoVSOXEI8_V_M2_M8 + 10U, // PseudoVSOXEI8_V_M2_M8_MASK + 10U, // PseudoVSOXEI8_V_M4_M4 + 10U, // PseudoVSOXEI8_V_M4_M4_MASK + 10U, // PseudoVSOXEI8_V_M4_M8 + 10U, // PseudoVSOXEI8_V_M4_M8_MASK + 10U, // PseudoVSOXEI8_V_M8_M8 + 10U, // PseudoVSOXEI8_V_M8_M8_MASK + 10U, // PseudoVSOXEI8_V_MF2_M1 + 10U, // PseudoVSOXEI8_V_MF2_M1_MASK + 10U, // PseudoVSOXEI8_V_MF2_M2 + 10U, // PseudoVSOXEI8_V_MF2_M2_MASK + 10U, // PseudoVSOXEI8_V_MF2_M4 + 10U, // PseudoVSOXEI8_V_MF2_M4_MASK + 10U, // PseudoVSOXEI8_V_MF2_MF2 + 10U, // PseudoVSOXEI8_V_MF2_MF2_MASK + 10U, // PseudoVSOXEI8_V_MF4_M1 + 10U, // PseudoVSOXEI8_V_MF4_M1_MASK + 10U, // PseudoVSOXEI8_V_MF4_M2 + 10U, // PseudoVSOXEI8_V_MF4_M2_MASK + 10U, // PseudoVSOXEI8_V_MF4_MF2 + 10U, // PseudoVSOXEI8_V_MF4_MF2_MASK + 10U, // PseudoVSOXEI8_V_MF4_MF4 + 10U, // PseudoVSOXEI8_V_MF4_MF4_MASK + 10U, // PseudoVSOXEI8_V_MF8_M1 + 10U, // PseudoVSOXEI8_V_MF8_M1_MASK + 10U, // PseudoVSOXEI8_V_MF8_MF2 + 10U, // PseudoVSOXEI8_V_MF8_MF2_MASK + 10U, // PseudoVSOXEI8_V_MF8_MF4 + 10U, // PseudoVSOXEI8_V_MF8_MF4_MASK + 10U, // PseudoVSOXEI8_V_MF8_MF8 + 10U, // PseudoVSOXEI8_V_MF8_MF8_MASK + 10U, // PseudoVSOXSEG2EI16_V_M1_M1 + 10U, // PseudoVSOXSEG2EI16_V_M1_M1_MASK + 10U, // PseudoVSOXSEG2EI16_V_M1_M2 + 10U, // PseudoVSOXSEG2EI16_V_M1_M2_MASK + 10U, // PseudoVSOXSEG2EI16_V_M1_M4 + 10U, // PseudoVSOXSEG2EI16_V_M1_M4_MASK + 10U, // PseudoVSOXSEG2EI16_V_M1_MF2 + 10U, // PseudoVSOXSEG2EI16_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG2EI16_V_M2_M1 + 10U, // PseudoVSOXSEG2EI16_V_M2_M1_MASK + 10U, // PseudoVSOXSEG2EI16_V_M2_M2 + 10U, // PseudoVSOXSEG2EI16_V_M2_M2_MASK + 10U, // PseudoVSOXSEG2EI16_V_M2_M4 + 10U, // PseudoVSOXSEG2EI16_V_M2_M4_MASK + 10U, // PseudoVSOXSEG2EI16_V_M4_M2 + 10U, // PseudoVSOXSEG2EI16_V_M4_M2_MASK + 10U, // PseudoVSOXSEG2EI16_V_M4_M4 + 10U, // PseudoVSOXSEG2EI16_V_M4_M4_MASK + 10U, // PseudoVSOXSEG2EI16_V_M8_M4 + 10U, // PseudoVSOXSEG2EI16_V_M8_M4_MASK + 10U, // PseudoVSOXSEG2EI16_V_MF2_M1 + 10U, // PseudoVSOXSEG2EI16_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG2EI16_V_MF2_M2 + 10U, // PseudoVSOXSEG2EI16_V_MF2_M2_MASK + 10U, // PseudoVSOXSEG2EI16_V_MF2_MF2 + 10U, // PseudoVSOXSEG2EI16_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG2EI16_V_MF2_MF4 + 10U, // PseudoVSOXSEG2EI16_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG2EI16_V_MF4_M1 + 10U, // PseudoVSOXSEG2EI16_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG2EI16_V_MF4_MF2 + 10U, // PseudoVSOXSEG2EI16_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG2EI16_V_MF4_MF4 + 10U, // PseudoVSOXSEG2EI16_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG2EI16_V_MF4_MF8 + 10U, // PseudoVSOXSEG2EI16_V_MF4_MF8_MASK + 10U, // PseudoVSOXSEG2EI32_V_M1_M1 + 10U, // PseudoVSOXSEG2EI32_V_M1_M1_MASK + 10U, // PseudoVSOXSEG2EI32_V_M1_M2 + 10U, // PseudoVSOXSEG2EI32_V_M1_M2_MASK + 10U, // PseudoVSOXSEG2EI32_V_M1_MF2 + 10U, // PseudoVSOXSEG2EI32_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG2EI32_V_M1_MF4 + 10U, // PseudoVSOXSEG2EI32_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG2EI32_V_M2_M1 + 10U, // PseudoVSOXSEG2EI32_V_M2_M1_MASK + 10U, // PseudoVSOXSEG2EI32_V_M2_M2 + 10U, // PseudoVSOXSEG2EI32_V_M2_M2_MASK + 10U, // PseudoVSOXSEG2EI32_V_M2_M4 + 10U, // PseudoVSOXSEG2EI32_V_M2_M4_MASK + 10U, // PseudoVSOXSEG2EI32_V_M2_MF2 + 10U, // PseudoVSOXSEG2EI32_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG2EI32_V_M4_M1 + 10U, // PseudoVSOXSEG2EI32_V_M4_M1_MASK + 10U, // PseudoVSOXSEG2EI32_V_M4_M2 + 10U, // PseudoVSOXSEG2EI32_V_M4_M2_MASK + 10U, // PseudoVSOXSEG2EI32_V_M4_M4 + 10U, // PseudoVSOXSEG2EI32_V_M4_M4_MASK + 10U, // PseudoVSOXSEG2EI32_V_M8_M2 + 10U, // PseudoVSOXSEG2EI32_V_M8_M2_MASK + 10U, // PseudoVSOXSEG2EI32_V_M8_M4 + 10U, // PseudoVSOXSEG2EI32_V_M8_M4_MASK + 10U, // PseudoVSOXSEG2EI32_V_MF2_M1 + 10U, // PseudoVSOXSEG2EI32_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG2EI32_V_MF2_MF2 + 10U, // PseudoVSOXSEG2EI32_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG2EI32_V_MF2_MF4 + 10U, // PseudoVSOXSEG2EI32_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG2EI32_V_MF2_MF8 + 10U, // PseudoVSOXSEG2EI32_V_MF2_MF8_MASK + 10U, // PseudoVSOXSEG2EI64_V_M1_M1 + 10U, // PseudoVSOXSEG2EI64_V_M1_M1_MASK + 10U, // PseudoVSOXSEG2EI64_V_M1_MF2 + 10U, // PseudoVSOXSEG2EI64_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG2EI64_V_M1_MF4 + 10U, // PseudoVSOXSEG2EI64_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG2EI64_V_M1_MF8 + 10U, // PseudoVSOXSEG2EI64_V_M1_MF8_MASK + 10U, // PseudoVSOXSEG2EI64_V_M2_M1 + 10U, // PseudoVSOXSEG2EI64_V_M2_M1_MASK + 10U, // PseudoVSOXSEG2EI64_V_M2_M2 + 10U, // PseudoVSOXSEG2EI64_V_M2_M2_MASK + 10U, // PseudoVSOXSEG2EI64_V_M2_MF2 + 10U, // PseudoVSOXSEG2EI64_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG2EI64_V_M2_MF4 + 10U, // PseudoVSOXSEG2EI64_V_M2_MF4_MASK + 10U, // PseudoVSOXSEG2EI64_V_M4_M1 + 10U, // PseudoVSOXSEG2EI64_V_M4_M1_MASK + 10U, // PseudoVSOXSEG2EI64_V_M4_M2 + 10U, // PseudoVSOXSEG2EI64_V_M4_M2_MASK + 10U, // PseudoVSOXSEG2EI64_V_M4_M4 + 10U, // PseudoVSOXSEG2EI64_V_M4_M4_MASK + 10U, // PseudoVSOXSEG2EI64_V_M4_MF2 + 10U, // PseudoVSOXSEG2EI64_V_M4_MF2_MASK + 10U, // PseudoVSOXSEG2EI64_V_M8_M1 + 10U, // PseudoVSOXSEG2EI64_V_M8_M1_MASK + 10U, // PseudoVSOXSEG2EI64_V_M8_M2 + 10U, // PseudoVSOXSEG2EI64_V_M8_M2_MASK + 10U, // PseudoVSOXSEG2EI64_V_M8_M4 + 10U, // PseudoVSOXSEG2EI64_V_M8_M4_MASK + 10U, // PseudoVSOXSEG2EI8_V_M1_M1 + 10U, // PseudoVSOXSEG2EI8_V_M1_M1_MASK + 10U, // PseudoVSOXSEG2EI8_V_M1_M2 + 10U, // PseudoVSOXSEG2EI8_V_M1_M2_MASK + 10U, // PseudoVSOXSEG2EI8_V_M1_M4 + 10U, // PseudoVSOXSEG2EI8_V_M1_M4_MASK + 10U, // PseudoVSOXSEG2EI8_V_M2_M2 + 10U, // PseudoVSOXSEG2EI8_V_M2_M2_MASK + 10U, // PseudoVSOXSEG2EI8_V_M2_M4 + 10U, // PseudoVSOXSEG2EI8_V_M2_M4_MASK + 10U, // PseudoVSOXSEG2EI8_V_M4_M4 + 10U, // PseudoVSOXSEG2EI8_V_M4_M4_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF2_M1 + 10U, // PseudoVSOXSEG2EI8_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF2_M2 + 10U, // PseudoVSOXSEG2EI8_V_MF2_M2_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF2_M4 + 10U, // PseudoVSOXSEG2EI8_V_MF2_M4_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF2_MF2 + 10U, // PseudoVSOXSEG2EI8_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF4_M1 + 10U, // PseudoVSOXSEG2EI8_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF4_M2 + 10U, // PseudoVSOXSEG2EI8_V_MF4_M2_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF4_MF2 + 10U, // PseudoVSOXSEG2EI8_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF4_MF4 + 10U, // PseudoVSOXSEG2EI8_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF8_M1 + 10U, // PseudoVSOXSEG2EI8_V_MF8_M1_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF8_MF2 + 10U, // PseudoVSOXSEG2EI8_V_MF8_MF2_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF8_MF4 + 10U, // PseudoVSOXSEG2EI8_V_MF8_MF4_MASK + 10U, // PseudoVSOXSEG2EI8_V_MF8_MF8 + 10U, // PseudoVSOXSEG2EI8_V_MF8_MF8_MASK + 10U, // PseudoVSOXSEG3EI16_V_M1_M1 + 10U, // PseudoVSOXSEG3EI16_V_M1_M1_MASK + 10U, // PseudoVSOXSEG3EI16_V_M1_M2 + 10U, // PseudoVSOXSEG3EI16_V_M1_M2_MASK + 10U, // PseudoVSOXSEG3EI16_V_M1_MF2 + 10U, // PseudoVSOXSEG3EI16_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG3EI16_V_M2_M1 + 10U, // PseudoVSOXSEG3EI16_V_M2_M1_MASK + 10U, // PseudoVSOXSEG3EI16_V_M2_M2 + 10U, // PseudoVSOXSEG3EI16_V_M2_M2_MASK + 10U, // PseudoVSOXSEG3EI16_V_M4_M2 + 10U, // PseudoVSOXSEG3EI16_V_M4_M2_MASK + 10U, // PseudoVSOXSEG3EI16_V_MF2_M1 + 10U, // PseudoVSOXSEG3EI16_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG3EI16_V_MF2_M2 + 10U, // PseudoVSOXSEG3EI16_V_MF2_M2_MASK + 10U, // PseudoVSOXSEG3EI16_V_MF2_MF2 + 10U, // PseudoVSOXSEG3EI16_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG3EI16_V_MF2_MF4 + 10U, // PseudoVSOXSEG3EI16_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG3EI16_V_MF4_M1 + 10U, // PseudoVSOXSEG3EI16_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG3EI16_V_MF4_MF2 + 10U, // PseudoVSOXSEG3EI16_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG3EI16_V_MF4_MF4 + 10U, // PseudoVSOXSEG3EI16_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG3EI16_V_MF4_MF8 + 10U, // PseudoVSOXSEG3EI16_V_MF4_MF8_MASK + 10U, // PseudoVSOXSEG3EI32_V_M1_M1 + 10U, // PseudoVSOXSEG3EI32_V_M1_M1_MASK + 10U, // PseudoVSOXSEG3EI32_V_M1_M2 + 10U, // PseudoVSOXSEG3EI32_V_M1_M2_MASK + 10U, // PseudoVSOXSEG3EI32_V_M1_MF2 + 10U, // PseudoVSOXSEG3EI32_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG3EI32_V_M1_MF4 + 10U, // PseudoVSOXSEG3EI32_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG3EI32_V_M2_M1 + 10U, // PseudoVSOXSEG3EI32_V_M2_M1_MASK + 10U, // PseudoVSOXSEG3EI32_V_M2_M2 + 10U, // PseudoVSOXSEG3EI32_V_M2_M2_MASK + 10U, // PseudoVSOXSEG3EI32_V_M2_MF2 + 10U, // PseudoVSOXSEG3EI32_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG3EI32_V_M4_M1 + 10U, // PseudoVSOXSEG3EI32_V_M4_M1_MASK + 10U, // PseudoVSOXSEG3EI32_V_M4_M2 + 10U, // PseudoVSOXSEG3EI32_V_M4_M2_MASK + 10U, // PseudoVSOXSEG3EI32_V_M8_M2 + 10U, // PseudoVSOXSEG3EI32_V_M8_M2_MASK + 10U, // PseudoVSOXSEG3EI32_V_MF2_M1 + 10U, // PseudoVSOXSEG3EI32_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG3EI32_V_MF2_MF2 + 10U, // PseudoVSOXSEG3EI32_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG3EI32_V_MF2_MF4 + 10U, // PseudoVSOXSEG3EI32_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG3EI32_V_MF2_MF8 + 10U, // PseudoVSOXSEG3EI32_V_MF2_MF8_MASK + 10U, // PseudoVSOXSEG3EI64_V_M1_M1 + 10U, // PseudoVSOXSEG3EI64_V_M1_M1_MASK + 10U, // PseudoVSOXSEG3EI64_V_M1_MF2 + 10U, // PseudoVSOXSEG3EI64_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG3EI64_V_M1_MF4 + 10U, // PseudoVSOXSEG3EI64_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG3EI64_V_M1_MF8 + 10U, // PseudoVSOXSEG3EI64_V_M1_MF8_MASK + 10U, // PseudoVSOXSEG3EI64_V_M2_M1 + 10U, // PseudoVSOXSEG3EI64_V_M2_M1_MASK + 10U, // PseudoVSOXSEG3EI64_V_M2_M2 + 10U, // PseudoVSOXSEG3EI64_V_M2_M2_MASK + 10U, // PseudoVSOXSEG3EI64_V_M2_MF2 + 10U, // PseudoVSOXSEG3EI64_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG3EI64_V_M2_MF4 + 10U, // PseudoVSOXSEG3EI64_V_M2_MF4_MASK + 10U, // PseudoVSOXSEG3EI64_V_M4_M1 + 10U, // PseudoVSOXSEG3EI64_V_M4_M1_MASK + 10U, // PseudoVSOXSEG3EI64_V_M4_M2 + 10U, // PseudoVSOXSEG3EI64_V_M4_M2_MASK + 10U, // PseudoVSOXSEG3EI64_V_M4_MF2 + 10U, // PseudoVSOXSEG3EI64_V_M4_MF2_MASK + 10U, // PseudoVSOXSEG3EI64_V_M8_M1 + 10U, // PseudoVSOXSEG3EI64_V_M8_M1_MASK + 10U, // PseudoVSOXSEG3EI64_V_M8_M2 + 10U, // PseudoVSOXSEG3EI64_V_M8_M2_MASK + 10U, // PseudoVSOXSEG3EI8_V_M1_M1 + 10U, // PseudoVSOXSEG3EI8_V_M1_M1_MASK + 10U, // PseudoVSOXSEG3EI8_V_M1_M2 + 10U, // PseudoVSOXSEG3EI8_V_M1_M2_MASK + 10U, // PseudoVSOXSEG3EI8_V_M2_M2 + 10U, // PseudoVSOXSEG3EI8_V_M2_M2_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF2_M1 + 10U, // PseudoVSOXSEG3EI8_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF2_M2 + 10U, // PseudoVSOXSEG3EI8_V_MF2_M2_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF2_MF2 + 10U, // PseudoVSOXSEG3EI8_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF4_M1 + 10U, // PseudoVSOXSEG3EI8_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF4_M2 + 10U, // PseudoVSOXSEG3EI8_V_MF4_M2_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF4_MF2 + 10U, // PseudoVSOXSEG3EI8_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF4_MF4 + 10U, // PseudoVSOXSEG3EI8_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF8_M1 + 10U, // PseudoVSOXSEG3EI8_V_MF8_M1_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF8_MF2 + 10U, // PseudoVSOXSEG3EI8_V_MF8_MF2_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF8_MF4 + 10U, // PseudoVSOXSEG3EI8_V_MF8_MF4_MASK + 10U, // PseudoVSOXSEG3EI8_V_MF8_MF8 + 10U, // PseudoVSOXSEG3EI8_V_MF8_MF8_MASK + 10U, // PseudoVSOXSEG4EI16_V_M1_M1 + 10U, // PseudoVSOXSEG4EI16_V_M1_M1_MASK + 10U, // PseudoVSOXSEG4EI16_V_M1_M2 + 10U, // PseudoVSOXSEG4EI16_V_M1_M2_MASK + 10U, // PseudoVSOXSEG4EI16_V_M1_MF2 + 10U, // PseudoVSOXSEG4EI16_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG4EI16_V_M2_M1 + 10U, // PseudoVSOXSEG4EI16_V_M2_M1_MASK + 10U, // PseudoVSOXSEG4EI16_V_M2_M2 + 10U, // PseudoVSOXSEG4EI16_V_M2_M2_MASK + 10U, // PseudoVSOXSEG4EI16_V_M4_M2 + 10U, // PseudoVSOXSEG4EI16_V_M4_M2_MASK + 10U, // PseudoVSOXSEG4EI16_V_MF2_M1 + 10U, // PseudoVSOXSEG4EI16_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG4EI16_V_MF2_M2 + 10U, // PseudoVSOXSEG4EI16_V_MF2_M2_MASK + 10U, // PseudoVSOXSEG4EI16_V_MF2_MF2 + 10U, // PseudoVSOXSEG4EI16_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG4EI16_V_MF2_MF4 + 10U, // PseudoVSOXSEG4EI16_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG4EI16_V_MF4_M1 + 10U, // PseudoVSOXSEG4EI16_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG4EI16_V_MF4_MF2 + 10U, // PseudoVSOXSEG4EI16_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG4EI16_V_MF4_MF4 + 10U, // PseudoVSOXSEG4EI16_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG4EI16_V_MF4_MF8 + 10U, // PseudoVSOXSEG4EI16_V_MF4_MF8_MASK + 10U, // PseudoVSOXSEG4EI32_V_M1_M1 + 10U, // PseudoVSOXSEG4EI32_V_M1_M1_MASK + 10U, // PseudoVSOXSEG4EI32_V_M1_M2 + 10U, // PseudoVSOXSEG4EI32_V_M1_M2_MASK + 10U, // PseudoVSOXSEG4EI32_V_M1_MF2 + 10U, // PseudoVSOXSEG4EI32_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG4EI32_V_M1_MF4 + 10U, // PseudoVSOXSEG4EI32_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG4EI32_V_M2_M1 + 10U, // PseudoVSOXSEG4EI32_V_M2_M1_MASK + 10U, // PseudoVSOXSEG4EI32_V_M2_M2 + 10U, // PseudoVSOXSEG4EI32_V_M2_M2_MASK + 10U, // PseudoVSOXSEG4EI32_V_M2_MF2 + 10U, // PseudoVSOXSEG4EI32_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG4EI32_V_M4_M1 + 10U, // PseudoVSOXSEG4EI32_V_M4_M1_MASK + 10U, // PseudoVSOXSEG4EI32_V_M4_M2 + 10U, // PseudoVSOXSEG4EI32_V_M4_M2_MASK + 10U, // PseudoVSOXSEG4EI32_V_M8_M2 + 10U, // PseudoVSOXSEG4EI32_V_M8_M2_MASK + 10U, // PseudoVSOXSEG4EI32_V_MF2_M1 + 10U, // PseudoVSOXSEG4EI32_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG4EI32_V_MF2_MF2 + 10U, // PseudoVSOXSEG4EI32_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG4EI32_V_MF2_MF4 + 10U, // PseudoVSOXSEG4EI32_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG4EI32_V_MF2_MF8 + 10U, // PseudoVSOXSEG4EI32_V_MF2_MF8_MASK + 10U, // PseudoVSOXSEG4EI64_V_M1_M1 + 10U, // PseudoVSOXSEG4EI64_V_M1_M1_MASK + 10U, // PseudoVSOXSEG4EI64_V_M1_MF2 + 10U, // PseudoVSOXSEG4EI64_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG4EI64_V_M1_MF4 + 10U, // PseudoVSOXSEG4EI64_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG4EI64_V_M1_MF8 + 10U, // PseudoVSOXSEG4EI64_V_M1_MF8_MASK + 10U, // PseudoVSOXSEG4EI64_V_M2_M1 + 10U, // PseudoVSOXSEG4EI64_V_M2_M1_MASK + 10U, // PseudoVSOXSEG4EI64_V_M2_M2 + 10U, // PseudoVSOXSEG4EI64_V_M2_M2_MASK + 10U, // PseudoVSOXSEG4EI64_V_M2_MF2 + 10U, // PseudoVSOXSEG4EI64_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG4EI64_V_M2_MF4 + 10U, // PseudoVSOXSEG4EI64_V_M2_MF4_MASK + 10U, // PseudoVSOXSEG4EI64_V_M4_M1 + 10U, // PseudoVSOXSEG4EI64_V_M4_M1_MASK + 10U, // PseudoVSOXSEG4EI64_V_M4_M2 + 10U, // PseudoVSOXSEG4EI64_V_M4_M2_MASK + 10U, // PseudoVSOXSEG4EI64_V_M4_MF2 + 10U, // PseudoVSOXSEG4EI64_V_M4_MF2_MASK + 10U, // PseudoVSOXSEG4EI64_V_M8_M1 + 10U, // PseudoVSOXSEG4EI64_V_M8_M1_MASK + 10U, // PseudoVSOXSEG4EI64_V_M8_M2 + 10U, // PseudoVSOXSEG4EI64_V_M8_M2_MASK + 10U, // PseudoVSOXSEG4EI8_V_M1_M1 + 10U, // PseudoVSOXSEG4EI8_V_M1_M1_MASK + 10U, // PseudoVSOXSEG4EI8_V_M1_M2 + 10U, // PseudoVSOXSEG4EI8_V_M1_M2_MASK + 10U, // PseudoVSOXSEG4EI8_V_M2_M2 + 10U, // PseudoVSOXSEG4EI8_V_M2_M2_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF2_M1 + 10U, // PseudoVSOXSEG4EI8_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF2_M2 + 10U, // PseudoVSOXSEG4EI8_V_MF2_M2_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF2_MF2 + 10U, // PseudoVSOXSEG4EI8_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF4_M1 + 10U, // PseudoVSOXSEG4EI8_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF4_M2 + 10U, // PseudoVSOXSEG4EI8_V_MF4_M2_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF4_MF2 + 10U, // PseudoVSOXSEG4EI8_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF4_MF4 + 10U, // PseudoVSOXSEG4EI8_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF8_M1 + 10U, // PseudoVSOXSEG4EI8_V_MF8_M1_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF8_MF2 + 10U, // PseudoVSOXSEG4EI8_V_MF8_MF2_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF8_MF4 + 10U, // PseudoVSOXSEG4EI8_V_MF8_MF4_MASK + 10U, // PseudoVSOXSEG4EI8_V_MF8_MF8 + 10U, // PseudoVSOXSEG4EI8_V_MF8_MF8_MASK + 10U, // PseudoVSOXSEG5EI16_V_M1_M1 + 10U, // PseudoVSOXSEG5EI16_V_M1_M1_MASK + 10U, // PseudoVSOXSEG5EI16_V_M1_MF2 + 10U, // PseudoVSOXSEG5EI16_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG5EI16_V_M2_M1 + 10U, // PseudoVSOXSEG5EI16_V_M2_M1_MASK + 10U, // PseudoVSOXSEG5EI16_V_MF2_M1 + 10U, // PseudoVSOXSEG5EI16_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG5EI16_V_MF2_MF2 + 10U, // PseudoVSOXSEG5EI16_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG5EI16_V_MF2_MF4 + 10U, // PseudoVSOXSEG5EI16_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG5EI16_V_MF4_M1 + 10U, // PseudoVSOXSEG5EI16_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG5EI16_V_MF4_MF2 + 10U, // PseudoVSOXSEG5EI16_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG5EI16_V_MF4_MF4 + 10U, // PseudoVSOXSEG5EI16_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG5EI16_V_MF4_MF8 + 10U, // PseudoVSOXSEG5EI16_V_MF4_MF8_MASK + 10U, // PseudoVSOXSEG5EI32_V_M1_M1 + 10U, // PseudoVSOXSEG5EI32_V_M1_M1_MASK + 10U, // PseudoVSOXSEG5EI32_V_M1_MF2 + 10U, // PseudoVSOXSEG5EI32_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG5EI32_V_M1_MF4 + 10U, // PseudoVSOXSEG5EI32_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG5EI32_V_M2_M1 + 10U, // PseudoVSOXSEG5EI32_V_M2_M1_MASK + 10U, // PseudoVSOXSEG5EI32_V_M2_MF2 + 10U, // PseudoVSOXSEG5EI32_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG5EI32_V_M4_M1 + 10U, // PseudoVSOXSEG5EI32_V_M4_M1_MASK + 10U, // PseudoVSOXSEG5EI32_V_MF2_M1 + 10U, // PseudoVSOXSEG5EI32_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG5EI32_V_MF2_MF2 + 10U, // PseudoVSOXSEG5EI32_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG5EI32_V_MF2_MF4 + 10U, // PseudoVSOXSEG5EI32_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG5EI32_V_MF2_MF8 + 10U, // PseudoVSOXSEG5EI32_V_MF2_MF8_MASK + 10U, // PseudoVSOXSEG5EI64_V_M1_M1 + 10U, // PseudoVSOXSEG5EI64_V_M1_M1_MASK + 10U, // PseudoVSOXSEG5EI64_V_M1_MF2 + 10U, // PseudoVSOXSEG5EI64_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG5EI64_V_M1_MF4 + 10U, // PseudoVSOXSEG5EI64_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG5EI64_V_M1_MF8 + 10U, // PseudoVSOXSEG5EI64_V_M1_MF8_MASK + 10U, // PseudoVSOXSEG5EI64_V_M2_M1 + 10U, // PseudoVSOXSEG5EI64_V_M2_M1_MASK + 10U, // PseudoVSOXSEG5EI64_V_M2_MF2 + 10U, // PseudoVSOXSEG5EI64_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG5EI64_V_M2_MF4 + 10U, // PseudoVSOXSEG5EI64_V_M2_MF4_MASK + 10U, // PseudoVSOXSEG5EI64_V_M4_M1 + 10U, // PseudoVSOXSEG5EI64_V_M4_M1_MASK + 10U, // PseudoVSOXSEG5EI64_V_M4_MF2 + 10U, // PseudoVSOXSEG5EI64_V_M4_MF2_MASK + 10U, // PseudoVSOXSEG5EI64_V_M8_M1 + 10U, // PseudoVSOXSEG5EI64_V_M8_M1_MASK + 10U, // PseudoVSOXSEG5EI8_V_M1_M1 + 10U, // PseudoVSOXSEG5EI8_V_M1_M1_MASK + 10U, // PseudoVSOXSEG5EI8_V_MF2_M1 + 10U, // PseudoVSOXSEG5EI8_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG5EI8_V_MF2_MF2 + 10U, // PseudoVSOXSEG5EI8_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG5EI8_V_MF4_M1 + 10U, // PseudoVSOXSEG5EI8_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG5EI8_V_MF4_MF2 + 10U, // PseudoVSOXSEG5EI8_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG5EI8_V_MF4_MF4 + 10U, // PseudoVSOXSEG5EI8_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG5EI8_V_MF8_M1 + 10U, // PseudoVSOXSEG5EI8_V_MF8_M1_MASK + 10U, // PseudoVSOXSEG5EI8_V_MF8_MF2 + 10U, // PseudoVSOXSEG5EI8_V_MF8_MF2_MASK + 10U, // PseudoVSOXSEG5EI8_V_MF8_MF4 + 10U, // PseudoVSOXSEG5EI8_V_MF8_MF4_MASK + 10U, // PseudoVSOXSEG5EI8_V_MF8_MF8 + 10U, // PseudoVSOXSEG5EI8_V_MF8_MF8_MASK + 10U, // PseudoVSOXSEG6EI16_V_M1_M1 + 10U, // PseudoVSOXSEG6EI16_V_M1_M1_MASK + 10U, // PseudoVSOXSEG6EI16_V_M1_MF2 + 10U, // PseudoVSOXSEG6EI16_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG6EI16_V_M2_M1 + 10U, // PseudoVSOXSEG6EI16_V_M2_M1_MASK + 10U, // PseudoVSOXSEG6EI16_V_MF2_M1 + 10U, // PseudoVSOXSEG6EI16_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG6EI16_V_MF2_MF2 + 10U, // PseudoVSOXSEG6EI16_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG6EI16_V_MF2_MF4 + 10U, // PseudoVSOXSEG6EI16_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG6EI16_V_MF4_M1 + 10U, // PseudoVSOXSEG6EI16_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG6EI16_V_MF4_MF2 + 10U, // PseudoVSOXSEG6EI16_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG6EI16_V_MF4_MF4 + 10U, // PseudoVSOXSEG6EI16_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG6EI16_V_MF4_MF8 + 10U, // PseudoVSOXSEG6EI16_V_MF4_MF8_MASK + 10U, // PseudoVSOXSEG6EI32_V_M1_M1 + 10U, // PseudoVSOXSEG6EI32_V_M1_M1_MASK + 10U, // PseudoVSOXSEG6EI32_V_M1_MF2 + 10U, // PseudoVSOXSEG6EI32_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG6EI32_V_M1_MF4 + 10U, // PseudoVSOXSEG6EI32_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG6EI32_V_M2_M1 + 10U, // PseudoVSOXSEG6EI32_V_M2_M1_MASK + 10U, // PseudoVSOXSEG6EI32_V_M2_MF2 + 10U, // PseudoVSOXSEG6EI32_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG6EI32_V_M4_M1 + 10U, // PseudoVSOXSEG6EI32_V_M4_M1_MASK + 10U, // PseudoVSOXSEG6EI32_V_MF2_M1 + 10U, // PseudoVSOXSEG6EI32_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG6EI32_V_MF2_MF2 + 10U, // PseudoVSOXSEG6EI32_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG6EI32_V_MF2_MF4 + 10U, // PseudoVSOXSEG6EI32_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG6EI32_V_MF2_MF8 + 10U, // PseudoVSOXSEG6EI32_V_MF2_MF8_MASK + 10U, // PseudoVSOXSEG6EI64_V_M1_M1 + 10U, // PseudoVSOXSEG6EI64_V_M1_M1_MASK + 10U, // PseudoVSOXSEG6EI64_V_M1_MF2 + 10U, // PseudoVSOXSEG6EI64_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG6EI64_V_M1_MF4 + 10U, // PseudoVSOXSEG6EI64_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG6EI64_V_M1_MF8 + 10U, // PseudoVSOXSEG6EI64_V_M1_MF8_MASK + 10U, // PseudoVSOXSEG6EI64_V_M2_M1 + 10U, // PseudoVSOXSEG6EI64_V_M2_M1_MASK + 10U, // PseudoVSOXSEG6EI64_V_M2_MF2 + 10U, // PseudoVSOXSEG6EI64_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG6EI64_V_M2_MF4 + 10U, // PseudoVSOXSEG6EI64_V_M2_MF4_MASK + 10U, // PseudoVSOXSEG6EI64_V_M4_M1 + 10U, // PseudoVSOXSEG6EI64_V_M4_M1_MASK + 10U, // PseudoVSOXSEG6EI64_V_M4_MF2 + 10U, // PseudoVSOXSEG6EI64_V_M4_MF2_MASK + 10U, // PseudoVSOXSEG6EI64_V_M8_M1 + 10U, // PseudoVSOXSEG6EI64_V_M8_M1_MASK + 10U, // PseudoVSOXSEG6EI8_V_M1_M1 + 10U, // PseudoVSOXSEG6EI8_V_M1_M1_MASK + 10U, // PseudoVSOXSEG6EI8_V_MF2_M1 + 10U, // PseudoVSOXSEG6EI8_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG6EI8_V_MF2_MF2 + 10U, // PseudoVSOXSEG6EI8_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG6EI8_V_MF4_M1 + 10U, // PseudoVSOXSEG6EI8_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG6EI8_V_MF4_MF2 + 10U, // PseudoVSOXSEG6EI8_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG6EI8_V_MF4_MF4 + 10U, // PseudoVSOXSEG6EI8_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG6EI8_V_MF8_M1 + 10U, // PseudoVSOXSEG6EI8_V_MF8_M1_MASK + 10U, // PseudoVSOXSEG6EI8_V_MF8_MF2 + 10U, // PseudoVSOXSEG6EI8_V_MF8_MF2_MASK + 10U, // PseudoVSOXSEG6EI8_V_MF8_MF4 + 10U, // PseudoVSOXSEG6EI8_V_MF8_MF4_MASK + 10U, // PseudoVSOXSEG6EI8_V_MF8_MF8 + 10U, // PseudoVSOXSEG6EI8_V_MF8_MF8_MASK + 10U, // PseudoVSOXSEG7EI16_V_M1_M1 + 10U, // PseudoVSOXSEG7EI16_V_M1_M1_MASK + 10U, // PseudoVSOXSEG7EI16_V_M1_MF2 + 10U, // PseudoVSOXSEG7EI16_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG7EI16_V_M2_M1 + 10U, // PseudoVSOXSEG7EI16_V_M2_M1_MASK + 10U, // PseudoVSOXSEG7EI16_V_MF2_M1 + 10U, // PseudoVSOXSEG7EI16_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG7EI16_V_MF2_MF2 + 10U, // PseudoVSOXSEG7EI16_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG7EI16_V_MF2_MF4 + 10U, // PseudoVSOXSEG7EI16_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG7EI16_V_MF4_M1 + 10U, // PseudoVSOXSEG7EI16_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG7EI16_V_MF4_MF2 + 10U, // PseudoVSOXSEG7EI16_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG7EI16_V_MF4_MF4 + 10U, // PseudoVSOXSEG7EI16_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG7EI16_V_MF4_MF8 + 10U, // PseudoVSOXSEG7EI16_V_MF4_MF8_MASK + 10U, // PseudoVSOXSEG7EI32_V_M1_M1 + 10U, // PseudoVSOXSEG7EI32_V_M1_M1_MASK + 10U, // PseudoVSOXSEG7EI32_V_M1_MF2 + 10U, // PseudoVSOXSEG7EI32_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG7EI32_V_M1_MF4 + 10U, // PseudoVSOXSEG7EI32_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG7EI32_V_M2_M1 + 10U, // PseudoVSOXSEG7EI32_V_M2_M1_MASK + 10U, // PseudoVSOXSEG7EI32_V_M2_MF2 + 10U, // PseudoVSOXSEG7EI32_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG7EI32_V_M4_M1 + 10U, // PseudoVSOXSEG7EI32_V_M4_M1_MASK + 10U, // PseudoVSOXSEG7EI32_V_MF2_M1 + 10U, // PseudoVSOXSEG7EI32_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG7EI32_V_MF2_MF2 + 10U, // PseudoVSOXSEG7EI32_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG7EI32_V_MF2_MF4 + 10U, // PseudoVSOXSEG7EI32_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG7EI32_V_MF2_MF8 + 10U, // PseudoVSOXSEG7EI32_V_MF2_MF8_MASK + 10U, // PseudoVSOXSEG7EI64_V_M1_M1 + 10U, // PseudoVSOXSEG7EI64_V_M1_M1_MASK + 10U, // PseudoVSOXSEG7EI64_V_M1_MF2 + 10U, // PseudoVSOXSEG7EI64_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG7EI64_V_M1_MF4 + 10U, // PseudoVSOXSEG7EI64_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG7EI64_V_M1_MF8 + 10U, // PseudoVSOXSEG7EI64_V_M1_MF8_MASK + 10U, // PseudoVSOXSEG7EI64_V_M2_M1 + 10U, // PseudoVSOXSEG7EI64_V_M2_M1_MASK + 10U, // PseudoVSOXSEG7EI64_V_M2_MF2 + 10U, // PseudoVSOXSEG7EI64_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG7EI64_V_M2_MF4 + 10U, // PseudoVSOXSEG7EI64_V_M2_MF4_MASK + 10U, // PseudoVSOXSEG7EI64_V_M4_M1 + 10U, // PseudoVSOXSEG7EI64_V_M4_M1_MASK + 10U, // PseudoVSOXSEG7EI64_V_M4_MF2 + 10U, // PseudoVSOXSEG7EI64_V_M4_MF2_MASK + 10U, // PseudoVSOXSEG7EI64_V_M8_M1 + 10U, // PseudoVSOXSEG7EI64_V_M8_M1_MASK + 10U, // PseudoVSOXSEG7EI8_V_M1_M1 + 10U, // PseudoVSOXSEG7EI8_V_M1_M1_MASK + 10U, // PseudoVSOXSEG7EI8_V_MF2_M1 + 10U, // PseudoVSOXSEG7EI8_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG7EI8_V_MF2_MF2 + 10U, // PseudoVSOXSEG7EI8_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG7EI8_V_MF4_M1 + 10U, // PseudoVSOXSEG7EI8_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG7EI8_V_MF4_MF2 + 10U, // PseudoVSOXSEG7EI8_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG7EI8_V_MF4_MF4 + 10U, // PseudoVSOXSEG7EI8_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG7EI8_V_MF8_M1 + 10U, // PseudoVSOXSEG7EI8_V_MF8_M1_MASK + 10U, // PseudoVSOXSEG7EI8_V_MF8_MF2 + 10U, // PseudoVSOXSEG7EI8_V_MF8_MF2_MASK + 10U, // PseudoVSOXSEG7EI8_V_MF8_MF4 + 10U, // PseudoVSOXSEG7EI8_V_MF8_MF4_MASK + 10U, // PseudoVSOXSEG7EI8_V_MF8_MF8 + 10U, // PseudoVSOXSEG7EI8_V_MF8_MF8_MASK + 10U, // PseudoVSOXSEG8EI16_V_M1_M1 + 10U, // PseudoVSOXSEG8EI16_V_M1_M1_MASK + 10U, // PseudoVSOXSEG8EI16_V_M1_MF2 + 10U, // PseudoVSOXSEG8EI16_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG8EI16_V_M2_M1 + 10U, // PseudoVSOXSEG8EI16_V_M2_M1_MASK + 10U, // PseudoVSOXSEG8EI16_V_MF2_M1 + 10U, // PseudoVSOXSEG8EI16_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG8EI16_V_MF2_MF2 + 10U, // PseudoVSOXSEG8EI16_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG8EI16_V_MF2_MF4 + 10U, // PseudoVSOXSEG8EI16_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG8EI16_V_MF4_M1 + 10U, // PseudoVSOXSEG8EI16_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG8EI16_V_MF4_MF2 + 10U, // PseudoVSOXSEG8EI16_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG8EI16_V_MF4_MF4 + 10U, // PseudoVSOXSEG8EI16_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG8EI16_V_MF4_MF8 + 10U, // PseudoVSOXSEG8EI16_V_MF4_MF8_MASK + 10U, // PseudoVSOXSEG8EI32_V_M1_M1 + 10U, // PseudoVSOXSEG8EI32_V_M1_M1_MASK + 10U, // PseudoVSOXSEG8EI32_V_M1_MF2 + 10U, // PseudoVSOXSEG8EI32_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG8EI32_V_M1_MF4 + 10U, // PseudoVSOXSEG8EI32_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG8EI32_V_M2_M1 + 10U, // PseudoVSOXSEG8EI32_V_M2_M1_MASK + 10U, // PseudoVSOXSEG8EI32_V_M2_MF2 + 10U, // PseudoVSOXSEG8EI32_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG8EI32_V_M4_M1 + 10U, // PseudoVSOXSEG8EI32_V_M4_M1_MASK + 10U, // PseudoVSOXSEG8EI32_V_MF2_M1 + 10U, // PseudoVSOXSEG8EI32_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG8EI32_V_MF2_MF2 + 10U, // PseudoVSOXSEG8EI32_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG8EI32_V_MF2_MF4 + 10U, // PseudoVSOXSEG8EI32_V_MF2_MF4_MASK + 10U, // PseudoVSOXSEG8EI32_V_MF2_MF8 + 10U, // PseudoVSOXSEG8EI32_V_MF2_MF8_MASK + 10U, // PseudoVSOXSEG8EI64_V_M1_M1 + 10U, // PseudoVSOXSEG8EI64_V_M1_M1_MASK + 10U, // PseudoVSOXSEG8EI64_V_M1_MF2 + 10U, // PseudoVSOXSEG8EI64_V_M1_MF2_MASK + 10U, // PseudoVSOXSEG8EI64_V_M1_MF4 + 10U, // PseudoVSOXSEG8EI64_V_M1_MF4_MASK + 10U, // PseudoVSOXSEG8EI64_V_M1_MF8 + 10U, // PseudoVSOXSEG8EI64_V_M1_MF8_MASK + 10U, // PseudoVSOXSEG8EI64_V_M2_M1 + 10U, // PseudoVSOXSEG8EI64_V_M2_M1_MASK + 10U, // PseudoVSOXSEG8EI64_V_M2_MF2 + 10U, // PseudoVSOXSEG8EI64_V_M2_MF2_MASK + 10U, // PseudoVSOXSEG8EI64_V_M2_MF4 + 10U, // PseudoVSOXSEG8EI64_V_M2_MF4_MASK + 10U, // PseudoVSOXSEG8EI64_V_M4_M1 + 10U, // PseudoVSOXSEG8EI64_V_M4_M1_MASK + 10U, // PseudoVSOXSEG8EI64_V_M4_MF2 + 10U, // PseudoVSOXSEG8EI64_V_M4_MF2_MASK + 10U, // PseudoVSOXSEG8EI64_V_M8_M1 + 10U, // PseudoVSOXSEG8EI64_V_M8_M1_MASK + 10U, // PseudoVSOXSEG8EI8_V_M1_M1 + 10U, // PseudoVSOXSEG8EI8_V_M1_M1_MASK + 10U, // PseudoVSOXSEG8EI8_V_MF2_M1 + 10U, // PseudoVSOXSEG8EI8_V_MF2_M1_MASK + 10U, // PseudoVSOXSEG8EI8_V_MF2_MF2 + 10U, // PseudoVSOXSEG8EI8_V_MF2_MF2_MASK + 10U, // PseudoVSOXSEG8EI8_V_MF4_M1 + 10U, // PseudoVSOXSEG8EI8_V_MF4_M1_MASK + 10U, // PseudoVSOXSEG8EI8_V_MF4_MF2 + 10U, // PseudoVSOXSEG8EI8_V_MF4_MF2_MASK + 10U, // PseudoVSOXSEG8EI8_V_MF4_MF4 + 10U, // PseudoVSOXSEG8EI8_V_MF4_MF4_MASK + 10U, // PseudoVSOXSEG8EI8_V_MF8_M1 + 10U, // PseudoVSOXSEG8EI8_V_MF8_M1_MASK + 10U, // PseudoVSOXSEG8EI8_V_MF8_MF2 + 10U, // PseudoVSOXSEG8EI8_V_MF8_MF2_MASK + 10U, // PseudoVSOXSEG8EI8_V_MF8_MF4 + 10U, // PseudoVSOXSEG8EI8_V_MF8_MF4_MASK + 10U, // PseudoVSOXSEG8EI8_V_MF8_MF8 + 10U, // PseudoVSOXSEG8EI8_V_MF8_MF8_MASK + 10U, // PseudoVSPILL2_M1 + 10U, // PseudoVSPILL2_M2 + 10U, // PseudoVSPILL2_M4 + 10U, // PseudoVSPILL2_MF2 + 10U, // PseudoVSPILL2_MF4 + 10U, // PseudoVSPILL2_MF8 + 10U, // PseudoVSPILL3_M1 + 10U, // PseudoVSPILL3_M2 + 10U, // PseudoVSPILL3_MF2 + 10U, // PseudoVSPILL3_MF4 + 10U, // PseudoVSPILL3_MF8 + 10U, // PseudoVSPILL4_M1 + 10U, // PseudoVSPILL4_M2 + 10U, // PseudoVSPILL4_MF2 + 10U, // PseudoVSPILL4_MF4 + 10U, // PseudoVSPILL4_MF8 + 10U, // PseudoVSPILL5_M1 + 10U, // PseudoVSPILL5_MF2 + 10U, // PseudoVSPILL5_MF4 + 10U, // PseudoVSPILL5_MF8 + 10U, // PseudoVSPILL6_M1 + 10U, // PseudoVSPILL6_MF2 + 10U, // PseudoVSPILL6_MF4 + 10U, // PseudoVSPILL6_MF8 + 10U, // PseudoVSPILL7_M1 + 10U, // PseudoVSPILL7_MF2 + 10U, // PseudoVSPILL7_MF4 + 10U, // PseudoVSPILL7_MF8 + 10U, // PseudoVSPILL8_M1 + 10U, // PseudoVSPILL8_MF2 + 10U, // PseudoVSPILL8_MF4 + 10U, // PseudoVSPILL8_MF8 + 10U, // PseudoVSPILL_M1 + 10U, // PseudoVSPILL_M2 + 10U, // PseudoVSPILL_M4 + 10U, // PseudoVSPILL_M8 + 10U, // PseudoVSRA_VI_M1 + 10U, // PseudoVSRA_VI_M1_MASK + 10U, // PseudoVSRA_VI_M2 + 10U, // PseudoVSRA_VI_M2_MASK + 10U, // PseudoVSRA_VI_M4 + 10U, // PseudoVSRA_VI_M4_MASK + 10U, // PseudoVSRA_VI_M8 + 10U, // PseudoVSRA_VI_M8_MASK + 10U, // PseudoVSRA_VI_MF2 + 10U, // PseudoVSRA_VI_MF2_MASK + 10U, // PseudoVSRA_VI_MF4 + 10U, // PseudoVSRA_VI_MF4_MASK + 10U, // PseudoVSRA_VI_MF8 + 10U, // PseudoVSRA_VI_MF8_MASK + 10U, // PseudoVSRA_VV_M1 + 10U, // PseudoVSRA_VV_M1_MASK + 10U, // PseudoVSRA_VV_M2 + 10U, // PseudoVSRA_VV_M2_MASK + 10U, // PseudoVSRA_VV_M4 + 10U, // PseudoVSRA_VV_M4_MASK + 10U, // PseudoVSRA_VV_M8 + 10U, // PseudoVSRA_VV_M8_MASK + 10U, // PseudoVSRA_VV_MF2 + 10U, // PseudoVSRA_VV_MF2_MASK + 10U, // PseudoVSRA_VV_MF4 + 10U, // PseudoVSRA_VV_MF4_MASK + 10U, // PseudoVSRA_VV_MF8 + 10U, // PseudoVSRA_VV_MF8_MASK + 10U, // PseudoVSRA_VX_M1 + 10U, // PseudoVSRA_VX_M1_MASK + 10U, // PseudoVSRA_VX_M2 + 10U, // PseudoVSRA_VX_M2_MASK + 10U, // PseudoVSRA_VX_M4 + 10U, // PseudoVSRA_VX_M4_MASK + 10U, // PseudoVSRA_VX_M8 + 10U, // PseudoVSRA_VX_M8_MASK + 10U, // PseudoVSRA_VX_MF2 + 10U, // PseudoVSRA_VX_MF2_MASK + 10U, // PseudoVSRA_VX_MF4 + 10U, // PseudoVSRA_VX_MF4_MASK + 10U, // PseudoVSRA_VX_MF8 + 10U, // PseudoVSRA_VX_MF8_MASK + 10U, // PseudoVSRL_VI_M1 + 10U, // PseudoVSRL_VI_M1_MASK + 10U, // PseudoVSRL_VI_M2 + 10U, // PseudoVSRL_VI_M2_MASK + 10U, // PseudoVSRL_VI_M4 + 10U, // PseudoVSRL_VI_M4_MASK + 10U, // PseudoVSRL_VI_M8 + 10U, // PseudoVSRL_VI_M8_MASK + 10U, // PseudoVSRL_VI_MF2 + 10U, // PseudoVSRL_VI_MF2_MASK + 10U, // PseudoVSRL_VI_MF4 + 10U, // PseudoVSRL_VI_MF4_MASK + 10U, // PseudoVSRL_VI_MF8 + 10U, // PseudoVSRL_VI_MF8_MASK + 10U, // PseudoVSRL_VV_M1 + 10U, // PseudoVSRL_VV_M1_MASK + 10U, // PseudoVSRL_VV_M2 + 10U, // PseudoVSRL_VV_M2_MASK + 10U, // PseudoVSRL_VV_M4 + 10U, // PseudoVSRL_VV_M4_MASK + 10U, // PseudoVSRL_VV_M8 + 10U, // PseudoVSRL_VV_M8_MASK + 10U, // PseudoVSRL_VV_MF2 + 10U, // PseudoVSRL_VV_MF2_MASK + 10U, // PseudoVSRL_VV_MF4 + 10U, // PseudoVSRL_VV_MF4_MASK + 10U, // PseudoVSRL_VV_MF8 + 10U, // PseudoVSRL_VV_MF8_MASK + 10U, // PseudoVSRL_VX_M1 + 10U, // PseudoVSRL_VX_M1_MASK + 10U, // PseudoVSRL_VX_M2 + 10U, // PseudoVSRL_VX_M2_MASK + 10U, // PseudoVSRL_VX_M4 + 10U, // PseudoVSRL_VX_M4_MASK + 10U, // PseudoVSRL_VX_M8 + 10U, // PseudoVSRL_VX_M8_MASK + 10U, // PseudoVSRL_VX_MF2 + 10U, // PseudoVSRL_VX_MF2_MASK + 10U, // PseudoVSRL_VX_MF4 + 10U, // PseudoVSRL_VX_MF4_MASK + 10U, // PseudoVSRL_VX_MF8 + 10U, // PseudoVSRL_VX_MF8_MASK + 10U, // PseudoVSSE16_V_M1 + 10U, // PseudoVSSE16_V_M1_MASK + 10U, // PseudoVSSE16_V_M2 + 10U, // PseudoVSSE16_V_M2_MASK + 10U, // PseudoVSSE16_V_M4 + 10U, // PseudoVSSE16_V_M4_MASK + 10U, // PseudoVSSE16_V_M8 + 10U, // PseudoVSSE16_V_M8_MASK + 10U, // PseudoVSSE16_V_MF2 + 10U, // PseudoVSSE16_V_MF2_MASK + 10U, // PseudoVSSE16_V_MF4 + 10U, // PseudoVSSE16_V_MF4_MASK + 10U, // PseudoVSSE32_V_M1 + 10U, // PseudoVSSE32_V_M1_MASK + 10U, // PseudoVSSE32_V_M2 + 10U, // PseudoVSSE32_V_M2_MASK + 10U, // PseudoVSSE32_V_M4 + 10U, // PseudoVSSE32_V_M4_MASK + 10U, // PseudoVSSE32_V_M8 + 10U, // PseudoVSSE32_V_M8_MASK + 10U, // PseudoVSSE32_V_MF2 + 10U, // PseudoVSSE32_V_MF2_MASK + 10U, // PseudoVSSE64_V_M1 + 10U, // PseudoVSSE64_V_M1_MASK + 10U, // PseudoVSSE64_V_M2 + 10U, // PseudoVSSE64_V_M2_MASK + 10U, // PseudoVSSE64_V_M4 + 10U, // PseudoVSSE64_V_M4_MASK + 10U, // PseudoVSSE64_V_M8 + 10U, // PseudoVSSE64_V_M8_MASK + 10U, // PseudoVSSE8_V_M1 + 10U, // PseudoVSSE8_V_M1_MASK + 10U, // PseudoVSSE8_V_M2 + 10U, // PseudoVSSE8_V_M2_MASK + 10U, // PseudoVSSE8_V_M4 + 10U, // PseudoVSSE8_V_M4_MASK + 10U, // PseudoVSSE8_V_M8 + 10U, // PseudoVSSE8_V_M8_MASK + 10U, // PseudoVSSE8_V_MF2 + 10U, // PseudoVSSE8_V_MF2_MASK + 10U, // PseudoVSSE8_V_MF4 + 10U, // PseudoVSSE8_V_MF4_MASK + 10U, // PseudoVSSE8_V_MF8 + 10U, // PseudoVSSE8_V_MF8_MASK + 10U, // PseudoVSSEG2E16_V_M1 + 10U, // PseudoVSSEG2E16_V_M1_MASK + 10U, // PseudoVSSEG2E16_V_M2 + 10U, // PseudoVSSEG2E16_V_M2_MASK + 10U, // PseudoVSSEG2E16_V_M4 + 10U, // PseudoVSSEG2E16_V_M4_MASK + 10U, // PseudoVSSEG2E16_V_MF2 + 10U, // PseudoVSSEG2E16_V_MF2_MASK + 10U, // PseudoVSSEG2E16_V_MF4 + 10U, // PseudoVSSEG2E16_V_MF4_MASK + 10U, // PseudoVSSEG2E32_V_M1 + 10U, // PseudoVSSEG2E32_V_M1_MASK + 10U, // PseudoVSSEG2E32_V_M2 + 10U, // PseudoVSSEG2E32_V_M2_MASK + 10U, // PseudoVSSEG2E32_V_M4 + 10U, // PseudoVSSEG2E32_V_M4_MASK + 10U, // PseudoVSSEG2E32_V_MF2 + 10U, // PseudoVSSEG2E32_V_MF2_MASK + 10U, // PseudoVSSEG2E64_V_M1 + 10U, // PseudoVSSEG2E64_V_M1_MASK + 10U, // PseudoVSSEG2E64_V_M2 + 10U, // PseudoVSSEG2E64_V_M2_MASK + 10U, // PseudoVSSEG2E64_V_M4 + 10U, // PseudoVSSEG2E64_V_M4_MASK + 10U, // PseudoVSSEG2E8_V_M1 + 10U, // PseudoVSSEG2E8_V_M1_MASK + 10U, // PseudoVSSEG2E8_V_M2 + 10U, // PseudoVSSEG2E8_V_M2_MASK + 10U, // PseudoVSSEG2E8_V_M4 + 10U, // PseudoVSSEG2E8_V_M4_MASK + 10U, // PseudoVSSEG2E8_V_MF2 + 10U, // PseudoVSSEG2E8_V_MF2_MASK + 10U, // PseudoVSSEG2E8_V_MF4 + 10U, // PseudoVSSEG2E8_V_MF4_MASK + 10U, // PseudoVSSEG2E8_V_MF8 + 10U, // PseudoVSSEG2E8_V_MF8_MASK + 10U, // PseudoVSSEG3E16_V_M1 + 10U, // PseudoVSSEG3E16_V_M1_MASK + 10U, // PseudoVSSEG3E16_V_M2 + 10U, // PseudoVSSEG3E16_V_M2_MASK + 10U, // PseudoVSSEG3E16_V_MF2 + 10U, // PseudoVSSEG3E16_V_MF2_MASK + 10U, // PseudoVSSEG3E16_V_MF4 + 10U, // PseudoVSSEG3E16_V_MF4_MASK + 10U, // PseudoVSSEG3E32_V_M1 + 10U, // PseudoVSSEG3E32_V_M1_MASK + 10U, // PseudoVSSEG3E32_V_M2 + 10U, // PseudoVSSEG3E32_V_M2_MASK + 10U, // PseudoVSSEG3E32_V_MF2 + 10U, // PseudoVSSEG3E32_V_MF2_MASK + 10U, // PseudoVSSEG3E64_V_M1 + 10U, // PseudoVSSEG3E64_V_M1_MASK + 10U, // PseudoVSSEG3E64_V_M2 + 10U, // PseudoVSSEG3E64_V_M2_MASK + 10U, // PseudoVSSEG3E8_V_M1 + 10U, // PseudoVSSEG3E8_V_M1_MASK + 10U, // PseudoVSSEG3E8_V_M2 + 10U, // PseudoVSSEG3E8_V_M2_MASK + 10U, // PseudoVSSEG3E8_V_MF2 + 10U, // PseudoVSSEG3E8_V_MF2_MASK + 10U, // PseudoVSSEG3E8_V_MF4 + 10U, // PseudoVSSEG3E8_V_MF4_MASK + 10U, // PseudoVSSEG3E8_V_MF8 + 10U, // PseudoVSSEG3E8_V_MF8_MASK + 10U, // PseudoVSSEG4E16_V_M1 + 10U, // PseudoVSSEG4E16_V_M1_MASK + 10U, // PseudoVSSEG4E16_V_M2 + 10U, // PseudoVSSEG4E16_V_M2_MASK + 10U, // PseudoVSSEG4E16_V_MF2 + 10U, // PseudoVSSEG4E16_V_MF2_MASK + 10U, // PseudoVSSEG4E16_V_MF4 + 10U, // PseudoVSSEG4E16_V_MF4_MASK + 10U, // PseudoVSSEG4E32_V_M1 + 10U, // PseudoVSSEG4E32_V_M1_MASK + 10U, // PseudoVSSEG4E32_V_M2 + 10U, // PseudoVSSEG4E32_V_M2_MASK + 10U, // PseudoVSSEG4E32_V_MF2 + 10U, // PseudoVSSEG4E32_V_MF2_MASK + 10U, // PseudoVSSEG4E64_V_M1 + 10U, // PseudoVSSEG4E64_V_M1_MASK + 10U, // PseudoVSSEG4E64_V_M2 + 10U, // PseudoVSSEG4E64_V_M2_MASK + 10U, // PseudoVSSEG4E8_V_M1 + 10U, // PseudoVSSEG4E8_V_M1_MASK + 10U, // PseudoVSSEG4E8_V_M2 + 10U, // PseudoVSSEG4E8_V_M2_MASK + 10U, // PseudoVSSEG4E8_V_MF2 + 10U, // PseudoVSSEG4E8_V_MF2_MASK + 10U, // PseudoVSSEG4E8_V_MF4 + 10U, // PseudoVSSEG4E8_V_MF4_MASK + 10U, // PseudoVSSEG4E8_V_MF8 + 10U, // PseudoVSSEG4E8_V_MF8_MASK + 10U, // PseudoVSSEG5E16_V_M1 + 10U, // PseudoVSSEG5E16_V_M1_MASK + 10U, // PseudoVSSEG5E16_V_MF2 + 10U, // PseudoVSSEG5E16_V_MF2_MASK + 10U, // PseudoVSSEG5E16_V_MF4 + 10U, // PseudoVSSEG5E16_V_MF4_MASK + 10U, // PseudoVSSEG5E32_V_M1 + 10U, // PseudoVSSEG5E32_V_M1_MASK + 10U, // PseudoVSSEG5E32_V_MF2 + 10U, // PseudoVSSEG5E32_V_MF2_MASK + 10U, // PseudoVSSEG5E64_V_M1 + 10U, // PseudoVSSEG5E64_V_M1_MASK + 10U, // PseudoVSSEG5E8_V_M1 + 10U, // PseudoVSSEG5E8_V_M1_MASK + 10U, // PseudoVSSEG5E8_V_MF2 + 10U, // PseudoVSSEG5E8_V_MF2_MASK + 10U, // PseudoVSSEG5E8_V_MF4 + 10U, // PseudoVSSEG5E8_V_MF4_MASK + 10U, // PseudoVSSEG5E8_V_MF8 + 10U, // PseudoVSSEG5E8_V_MF8_MASK + 10U, // PseudoVSSEG6E16_V_M1 + 10U, // PseudoVSSEG6E16_V_M1_MASK + 10U, // PseudoVSSEG6E16_V_MF2 + 10U, // PseudoVSSEG6E16_V_MF2_MASK + 10U, // PseudoVSSEG6E16_V_MF4 + 10U, // PseudoVSSEG6E16_V_MF4_MASK + 10U, // PseudoVSSEG6E32_V_M1 + 10U, // PseudoVSSEG6E32_V_M1_MASK + 10U, // PseudoVSSEG6E32_V_MF2 + 10U, // PseudoVSSEG6E32_V_MF2_MASK + 10U, // PseudoVSSEG6E64_V_M1 + 10U, // PseudoVSSEG6E64_V_M1_MASK + 10U, // PseudoVSSEG6E8_V_M1 + 10U, // PseudoVSSEG6E8_V_M1_MASK + 10U, // PseudoVSSEG6E8_V_MF2 + 10U, // PseudoVSSEG6E8_V_MF2_MASK + 10U, // PseudoVSSEG6E8_V_MF4 + 10U, // PseudoVSSEG6E8_V_MF4_MASK + 10U, // PseudoVSSEG6E8_V_MF8 + 10U, // PseudoVSSEG6E8_V_MF8_MASK + 10U, // PseudoVSSEG7E16_V_M1 + 10U, // PseudoVSSEG7E16_V_M1_MASK + 10U, // PseudoVSSEG7E16_V_MF2 + 10U, // PseudoVSSEG7E16_V_MF2_MASK + 10U, // PseudoVSSEG7E16_V_MF4 + 10U, // PseudoVSSEG7E16_V_MF4_MASK + 10U, // PseudoVSSEG7E32_V_M1 + 10U, // PseudoVSSEG7E32_V_M1_MASK + 10U, // PseudoVSSEG7E32_V_MF2 + 10U, // PseudoVSSEG7E32_V_MF2_MASK + 10U, // PseudoVSSEG7E64_V_M1 + 10U, // PseudoVSSEG7E64_V_M1_MASK + 10U, // PseudoVSSEG7E8_V_M1 + 10U, // PseudoVSSEG7E8_V_M1_MASK + 10U, // PseudoVSSEG7E8_V_MF2 + 10U, // PseudoVSSEG7E8_V_MF2_MASK + 10U, // PseudoVSSEG7E8_V_MF4 + 10U, // PseudoVSSEG7E8_V_MF4_MASK + 10U, // PseudoVSSEG7E8_V_MF8 + 10U, // PseudoVSSEG7E8_V_MF8_MASK + 10U, // PseudoVSSEG8E16_V_M1 + 10U, // PseudoVSSEG8E16_V_M1_MASK + 10U, // PseudoVSSEG8E16_V_MF2 + 10U, // PseudoVSSEG8E16_V_MF2_MASK + 10U, // PseudoVSSEG8E16_V_MF4 + 10U, // PseudoVSSEG8E16_V_MF4_MASK + 10U, // PseudoVSSEG8E32_V_M1 + 10U, // PseudoVSSEG8E32_V_M1_MASK + 10U, // PseudoVSSEG8E32_V_MF2 + 10U, // PseudoVSSEG8E32_V_MF2_MASK + 10U, // PseudoVSSEG8E64_V_M1 + 10U, // PseudoVSSEG8E64_V_M1_MASK + 10U, // PseudoVSSEG8E8_V_M1 + 10U, // PseudoVSSEG8E8_V_M1_MASK + 10U, // PseudoVSSEG8E8_V_MF2 + 10U, // PseudoVSSEG8E8_V_MF2_MASK + 10U, // PseudoVSSEG8E8_V_MF4 + 10U, // PseudoVSSEG8E8_V_MF4_MASK + 10U, // PseudoVSSEG8E8_V_MF8 + 10U, // PseudoVSSEG8E8_V_MF8_MASK + 10U, // PseudoVSSRA_VI_M1 + 10U, // PseudoVSSRA_VI_M1_MASK + 10U, // PseudoVSSRA_VI_M2 + 10U, // PseudoVSSRA_VI_M2_MASK + 10U, // PseudoVSSRA_VI_M4 + 10U, // PseudoVSSRA_VI_M4_MASK + 10U, // PseudoVSSRA_VI_M8 + 10U, // PseudoVSSRA_VI_M8_MASK + 10U, // PseudoVSSRA_VI_MF2 + 10U, // PseudoVSSRA_VI_MF2_MASK + 10U, // PseudoVSSRA_VI_MF4 + 10U, // PseudoVSSRA_VI_MF4_MASK + 10U, // PseudoVSSRA_VI_MF8 + 10U, // PseudoVSSRA_VI_MF8_MASK + 10U, // PseudoVSSRA_VV_M1 + 10U, // PseudoVSSRA_VV_M1_MASK + 10U, // PseudoVSSRA_VV_M2 + 10U, // PseudoVSSRA_VV_M2_MASK + 10U, // PseudoVSSRA_VV_M4 + 10U, // PseudoVSSRA_VV_M4_MASK + 10U, // PseudoVSSRA_VV_M8 + 10U, // PseudoVSSRA_VV_M8_MASK + 10U, // PseudoVSSRA_VV_MF2 + 10U, // PseudoVSSRA_VV_MF2_MASK + 10U, // PseudoVSSRA_VV_MF4 + 10U, // PseudoVSSRA_VV_MF4_MASK + 10U, // PseudoVSSRA_VV_MF8 + 10U, // PseudoVSSRA_VV_MF8_MASK + 10U, // PseudoVSSRA_VX_M1 + 10U, // PseudoVSSRA_VX_M1_MASK + 10U, // PseudoVSSRA_VX_M2 + 10U, // PseudoVSSRA_VX_M2_MASK + 10U, // PseudoVSSRA_VX_M4 + 10U, // PseudoVSSRA_VX_M4_MASK + 10U, // PseudoVSSRA_VX_M8 + 10U, // PseudoVSSRA_VX_M8_MASK + 10U, // PseudoVSSRA_VX_MF2 + 10U, // PseudoVSSRA_VX_MF2_MASK + 10U, // PseudoVSSRA_VX_MF4 + 10U, // PseudoVSSRA_VX_MF4_MASK + 10U, // PseudoVSSRA_VX_MF8 + 10U, // PseudoVSSRA_VX_MF8_MASK + 10U, // PseudoVSSRL_VI_M1 + 10U, // PseudoVSSRL_VI_M1_MASK + 10U, // PseudoVSSRL_VI_M2 + 10U, // PseudoVSSRL_VI_M2_MASK + 10U, // PseudoVSSRL_VI_M4 + 10U, // PseudoVSSRL_VI_M4_MASK + 10U, // PseudoVSSRL_VI_M8 + 10U, // PseudoVSSRL_VI_M8_MASK + 10U, // PseudoVSSRL_VI_MF2 + 10U, // PseudoVSSRL_VI_MF2_MASK + 10U, // PseudoVSSRL_VI_MF4 + 10U, // PseudoVSSRL_VI_MF4_MASK + 10U, // PseudoVSSRL_VI_MF8 + 10U, // PseudoVSSRL_VI_MF8_MASK + 10U, // PseudoVSSRL_VV_M1 + 10U, // PseudoVSSRL_VV_M1_MASK + 10U, // PseudoVSSRL_VV_M2 + 10U, // PseudoVSSRL_VV_M2_MASK + 10U, // PseudoVSSRL_VV_M4 + 10U, // PseudoVSSRL_VV_M4_MASK + 10U, // PseudoVSSRL_VV_M8 + 10U, // PseudoVSSRL_VV_M8_MASK + 10U, // PseudoVSSRL_VV_MF2 + 10U, // PseudoVSSRL_VV_MF2_MASK + 10U, // PseudoVSSRL_VV_MF4 + 10U, // PseudoVSSRL_VV_MF4_MASK + 10U, // PseudoVSSRL_VV_MF8 + 10U, // PseudoVSSRL_VV_MF8_MASK + 10U, // PseudoVSSRL_VX_M1 + 10U, // PseudoVSSRL_VX_M1_MASK + 10U, // PseudoVSSRL_VX_M2 + 10U, // PseudoVSSRL_VX_M2_MASK + 10U, // PseudoVSSRL_VX_M4 + 10U, // PseudoVSSRL_VX_M4_MASK + 10U, // PseudoVSSRL_VX_M8 + 10U, // PseudoVSSRL_VX_M8_MASK + 10U, // PseudoVSSRL_VX_MF2 + 10U, // PseudoVSSRL_VX_MF2_MASK + 10U, // PseudoVSSRL_VX_MF4 + 10U, // PseudoVSSRL_VX_MF4_MASK + 10U, // PseudoVSSRL_VX_MF8 + 10U, // PseudoVSSRL_VX_MF8_MASK + 10U, // PseudoVSSSEG2E16_V_M1 + 10U, // PseudoVSSSEG2E16_V_M1_MASK + 10U, // PseudoVSSSEG2E16_V_M2 + 10U, // PseudoVSSSEG2E16_V_M2_MASK + 10U, // PseudoVSSSEG2E16_V_M4 + 10U, // PseudoVSSSEG2E16_V_M4_MASK + 10U, // PseudoVSSSEG2E16_V_MF2 + 10U, // PseudoVSSSEG2E16_V_MF2_MASK + 10U, // PseudoVSSSEG2E16_V_MF4 + 10U, // PseudoVSSSEG2E16_V_MF4_MASK + 10U, // PseudoVSSSEG2E32_V_M1 + 10U, // PseudoVSSSEG2E32_V_M1_MASK + 10U, // PseudoVSSSEG2E32_V_M2 + 10U, // PseudoVSSSEG2E32_V_M2_MASK + 10U, // PseudoVSSSEG2E32_V_M4 + 10U, // PseudoVSSSEG2E32_V_M4_MASK + 10U, // PseudoVSSSEG2E32_V_MF2 + 10U, // PseudoVSSSEG2E32_V_MF2_MASK + 10U, // PseudoVSSSEG2E64_V_M1 + 10U, // PseudoVSSSEG2E64_V_M1_MASK + 10U, // PseudoVSSSEG2E64_V_M2 + 10U, // PseudoVSSSEG2E64_V_M2_MASK + 10U, // PseudoVSSSEG2E64_V_M4 + 10U, // PseudoVSSSEG2E64_V_M4_MASK + 10U, // PseudoVSSSEG2E8_V_M1 + 10U, // PseudoVSSSEG2E8_V_M1_MASK + 10U, // PseudoVSSSEG2E8_V_M2 + 10U, // PseudoVSSSEG2E8_V_M2_MASK + 10U, // PseudoVSSSEG2E8_V_M4 + 10U, // PseudoVSSSEG2E8_V_M4_MASK + 10U, // PseudoVSSSEG2E8_V_MF2 + 10U, // PseudoVSSSEG2E8_V_MF2_MASK + 10U, // PseudoVSSSEG2E8_V_MF4 + 10U, // PseudoVSSSEG2E8_V_MF4_MASK + 10U, // PseudoVSSSEG2E8_V_MF8 + 10U, // PseudoVSSSEG2E8_V_MF8_MASK + 10U, // PseudoVSSSEG3E16_V_M1 + 10U, // PseudoVSSSEG3E16_V_M1_MASK + 10U, // PseudoVSSSEG3E16_V_M2 + 10U, // PseudoVSSSEG3E16_V_M2_MASK + 10U, // PseudoVSSSEG3E16_V_MF2 + 10U, // PseudoVSSSEG3E16_V_MF2_MASK + 10U, // PseudoVSSSEG3E16_V_MF4 + 10U, // PseudoVSSSEG3E16_V_MF4_MASK + 10U, // PseudoVSSSEG3E32_V_M1 + 10U, // PseudoVSSSEG3E32_V_M1_MASK + 10U, // PseudoVSSSEG3E32_V_M2 + 10U, // PseudoVSSSEG3E32_V_M2_MASK + 10U, // PseudoVSSSEG3E32_V_MF2 + 10U, // PseudoVSSSEG3E32_V_MF2_MASK + 10U, // PseudoVSSSEG3E64_V_M1 + 10U, // PseudoVSSSEG3E64_V_M1_MASK + 10U, // PseudoVSSSEG3E64_V_M2 + 10U, // PseudoVSSSEG3E64_V_M2_MASK + 10U, // PseudoVSSSEG3E8_V_M1 + 10U, // PseudoVSSSEG3E8_V_M1_MASK + 10U, // PseudoVSSSEG3E8_V_M2 + 10U, // PseudoVSSSEG3E8_V_M2_MASK + 10U, // PseudoVSSSEG3E8_V_MF2 + 10U, // PseudoVSSSEG3E8_V_MF2_MASK + 10U, // PseudoVSSSEG3E8_V_MF4 + 10U, // PseudoVSSSEG3E8_V_MF4_MASK + 10U, // PseudoVSSSEG3E8_V_MF8 + 10U, // PseudoVSSSEG3E8_V_MF8_MASK + 10U, // PseudoVSSSEG4E16_V_M1 + 10U, // PseudoVSSSEG4E16_V_M1_MASK + 10U, // PseudoVSSSEG4E16_V_M2 + 10U, // PseudoVSSSEG4E16_V_M2_MASK + 10U, // PseudoVSSSEG4E16_V_MF2 + 10U, // PseudoVSSSEG4E16_V_MF2_MASK + 10U, // PseudoVSSSEG4E16_V_MF4 + 10U, // PseudoVSSSEG4E16_V_MF4_MASK + 10U, // PseudoVSSSEG4E32_V_M1 + 10U, // PseudoVSSSEG4E32_V_M1_MASK + 10U, // PseudoVSSSEG4E32_V_M2 + 10U, // PseudoVSSSEG4E32_V_M2_MASK + 10U, // PseudoVSSSEG4E32_V_MF2 + 10U, // PseudoVSSSEG4E32_V_MF2_MASK + 10U, // PseudoVSSSEG4E64_V_M1 + 10U, // PseudoVSSSEG4E64_V_M1_MASK + 10U, // PseudoVSSSEG4E64_V_M2 + 10U, // PseudoVSSSEG4E64_V_M2_MASK + 10U, // PseudoVSSSEG4E8_V_M1 + 10U, // PseudoVSSSEG4E8_V_M1_MASK + 10U, // PseudoVSSSEG4E8_V_M2 + 10U, // PseudoVSSSEG4E8_V_M2_MASK + 10U, // PseudoVSSSEG4E8_V_MF2 + 10U, // PseudoVSSSEG4E8_V_MF2_MASK + 10U, // PseudoVSSSEG4E8_V_MF4 + 10U, // PseudoVSSSEG4E8_V_MF4_MASK + 10U, // PseudoVSSSEG4E8_V_MF8 + 10U, // PseudoVSSSEG4E8_V_MF8_MASK + 10U, // PseudoVSSSEG5E16_V_M1 + 10U, // PseudoVSSSEG5E16_V_M1_MASK + 10U, // PseudoVSSSEG5E16_V_MF2 + 10U, // PseudoVSSSEG5E16_V_MF2_MASK + 10U, // PseudoVSSSEG5E16_V_MF4 + 10U, // PseudoVSSSEG5E16_V_MF4_MASK + 10U, // PseudoVSSSEG5E32_V_M1 + 10U, // PseudoVSSSEG5E32_V_M1_MASK + 10U, // PseudoVSSSEG5E32_V_MF2 + 10U, // PseudoVSSSEG5E32_V_MF2_MASK + 10U, // PseudoVSSSEG5E64_V_M1 + 10U, // PseudoVSSSEG5E64_V_M1_MASK + 10U, // PseudoVSSSEG5E8_V_M1 + 10U, // PseudoVSSSEG5E8_V_M1_MASK + 10U, // PseudoVSSSEG5E8_V_MF2 + 10U, // PseudoVSSSEG5E8_V_MF2_MASK + 10U, // PseudoVSSSEG5E8_V_MF4 + 10U, // PseudoVSSSEG5E8_V_MF4_MASK + 10U, // PseudoVSSSEG5E8_V_MF8 + 10U, // PseudoVSSSEG5E8_V_MF8_MASK + 10U, // PseudoVSSSEG6E16_V_M1 + 10U, // PseudoVSSSEG6E16_V_M1_MASK + 10U, // PseudoVSSSEG6E16_V_MF2 + 10U, // PseudoVSSSEG6E16_V_MF2_MASK + 10U, // PseudoVSSSEG6E16_V_MF4 + 10U, // PseudoVSSSEG6E16_V_MF4_MASK + 10U, // PseudoVSSSEG6E32_V_M1 + 10U, // PseudoVSSSEG6E32_V_M1_MASK + 10U, // PseudoVSSSEG6E32_V_MF2 + 10U, // PseudoVSSSEG6E32_V_MF2_MASK + 10U, // PseudoVSSSEG6E64_V_M1 + 10U, // PseudoVSSSEG6E64_V_M1_MASK + 10U, // PseudoVSSSEG6E8_V_M1 + 10U, // PseudoVSSSEG6E8_V_M1_MASK + 10U, // PseudoVSSSEG6E8_V_MF2 + 10U, // PseudoVSSSEG6E8_V_MF2_MASK + 10U, // PseudoVSSSEG6E8_V_MF4 + 10U, // PseudoVSSSEG6E8_V_MF4_MASK + 10U, // PseudoVSSSEG6E8_V_MF8 + 10U, // PseudoVSSSEG6E8_V_MF8_MASK + 10U, // PseudoVSSSEG7E16_V_M1 + 10U, // PseudoVSSSEG7E16_V_M1_MASK + 10U, // PseudoVSSSEG7E16_V_MF2 + 10U, // PseudoVSSSEG7E16_V_MF2_MASK + 10U, // PseudoVSSSEG7E16_V_MF4 + 10U, // PseudoVSSSEG7E16_V_MF4_MASK + 10U, // PseudoVSSSEG7E32_V_M1 + 10U, // PseudoVSSSEG7E32_V_M1_MASK + 10U, // PseudoVSSSEG7E32_V_MF2 + 10U, // PseudoVSSSEG7E32_V_MF2_MASK + 10U, // PseudoVSSSEG7E64_V_M1 + 10U, // PseudoVSSSEG7E64_V_M1_MASK + 10U, // PseudoVSSSEG7E8_V_M1 + 10U, // PseudoVSSSEG7E8_V_M1_MASK + 10U, // PseudoVSSSEG7E8_V_MF2 + 10U, // PseudoVSSSEG7E8_V_MF2_MASK + 10U, // PseudoVSSSEG7E8_V_MF4 + 10U, // PseudoVSSSEG7E8_V_MF4_MASK + 10U, // PseudoVSSSEG7E8_V_MF8 + 10U, // PseudoVSSSEG7E8_V_MF8_MASK + 10U, // PseudoVSSSEG8E16_V_M1 + 10U, // PseudoVSSSEG8E16_V_M1_MASK + 10U, // PseudoVSSSEG8E16_V_MF2 + 10U, // PseudoVSSSEG8E16_V_MF2_MASK + 10U, // PseudoVSSSEG8E16_V_MF4 + 10U, // PseudoVSSSEG8E16_V_MF4_MASK + 10U, // PseudoVSSSEG8E32_V_M1 + 10U, // PseudoVSSSEG8E32_V_M1_MASK + 10U, // PseudoVSSSEG8E32_V_MF2 + 10U, // PseudoVSSSEG8E32_V_MF2_MASK + 10U, // PseudoVSSSEG8E64_V_M1 + 10U, // PseudoVSSSEG8E64_V_M1_MASK + 10U, // PseudoVSSSEG8E8_V_M1 + 10U, // PseudoVSSSEG8E8_V_M1_MASK + 10U, // PseudoVSSSEG8E8_V_MF2 + 10U, // PseudoVSSSEG8E8_V_MF2_MASK + 10U, // PseudoVSSSEG8E8_V_MF4 + 10U, // PseudoVSSSEG8E8_V_MF4_MASK + 10U, // PseudoVSSSEG8E8_V_MF8 + 10U, // PseudoVSSSEG8E8_V_MF8_MASK + 10U, // PseudoVSSUBU_VV_M1 + 10U, // PseudoVSSUBU_VV_M1_MASK + 10U, // PseudoVSSUBU_VV_M2 + 10U, // PseudoVSSUBU_VV_M2_MASK + 10U, // PseudoVSSUBU_VV_M4 + 10U, // PseudoVSSUBU_VV_M4_MASK + 10U, // PseudoVSSUBU_VV_M8 + 10U, // PseudoVSSUBU_VV_M8_MASK + 10U, // PseudoVSSUBU_VV_MF2 + 10U, // PseudoVSSUBU_VV_MF2_MASK + 10U, // PseudoVSSUBU_VV_MF4 + 10U, // PseudoVSSUBU_VV_MF4_MASK + 10U, // PseudoVSSUBU_VV_MF8 + 10U, // PseudoVSSUBU_VV_MF8_MASK + 10U, // PseudoVSSUBU_VX_M1 + 10U, // PseudoVSSUBU_VX_M1_MASK + 10U, // PseudoVSSUBU_VX_M2 + 10U, // PseudoVSSUBU_VX_M2_MASK + 10U, // PseudoVSSUBU_VX_M4 + 10U, // PseudoVSSUBU_VX_M4_MASK + 10U, // PseudoVSSUBU_VX_M8 + 10U, // PseudoVSSUBU_VX_M8_MASK + 10U, // PseudoVSSUBU_VX_MF2 + 10U, // PseudoVSSUBU_VX_MF2_MASK + 10U, // PseudoVSSUBU_VX_MF4 + 10U, // PseudoVSSUBU_VX_MF4_MASK + 10U, // PseudoVSSUBU_VX_MF8 + 10U, // PseudoVSSUBU_VX_MF8_MASK + 10U, // PseudoVSSUB_VV_M1 + 10U, // PseudoVSSUB_VV_M1_MASK + 10U, // PseudoVSSUB_VV_M2 + 10U, // PseudoVSSUB_VV_M2_MASK + 10U, // PseudoVSSUB_VV_M4 + 10U, // PseudoVSSUB_VV_M4_MASK + 10U, // PseudoVSSUB_VV_M8 + 10U, // PseudoVSSUB_VV_M8_MASK + 10U, // PseudoVSSUB_VV_MF2 + 10U, // PseudoVSSUB_VV_MF2_MASK + 10U, // PseudoVSSUB_VV_MF4 + 10U, // PseudoVSSUB_VV_MF4_MASK + 10U, // PseudoVSSUB_VV_MF8 + 10U, // PseudoVSSUB_VV_MF8_MASK + 10U, // PseudoVSSUB_VX_M1 + 10U, // PseudoVSSUB_VX_M1_MASK + 10U, // PseudoVSSUB_VX_M2 + 10U, // PseudoVSSUB_VX_M2_MASK + 10U, // PseudoVSSUB_VX_M4 + 10U, // PseudoVSSUB_VX_M4_MASK + 10U, // PseudoVSSUB_VX_M8 + 10U, // PseudoVSSUB_VX_M8_MASK + 10U, // PseudoVSSUB_VX_MF2 + 10U, // PseudoVSSUB_VX_MF2_MASK + 10U, // PseudoVSSUB_VX_MF4 + 10U, // PseudoVSSUB_VX_MF4_MASK + 10U, // PseudoVSSUB_VX_MF8 + 10U, // PseudoVSSUB_VX_MF8_MASK + 10U, // PseudoVSUB_VV_M1 + 10U, // PseudoVSUB_VV_M1_MASK + 10U, // PseudoVSUB_VV_M2 + 10U, // PseudoVSUB_VV_M2_MASK + 10U, // PseudoVSUB_VV_M4 + 10U, // PseudoVSUB_VV_M4_MASK + 10U, // PseudoVSUB_VV_M8 + 10U, // PseudoVSUB_VV_M8_MASK + 10U, // PseudoVSUB_VV_MF2 + 10U, // PseudoVSUB_VV_MF2_MASK + 10U, // PseudoVSUB_VV_MF4 + 10U, // PseudoVSUB_VV_MF4_MASK + 10U, // PseudoVSUB_VV_MF8 + 10U, // PseudoVSUB_VV_MF8_MASK + 10U, // PseudoVSUB_VX_M1 + 10U, // PseudoVSUB_VX_M1_MASK + 10U, // PseudoVSUB_VX_M2 + 10U, // PseudoVSUB_VX_M2_MASK + 10U, // PseudoVSUB_VX_M4 + 10U, // PseudoVSUB_VX_M4_MASK + 10U, // PseudoVSUB_VX_M8 + 10U, // PseudoVSUB_VX_M8_MASK + 10U, // PseudoVSUB_VX_MF2 + 10U, // PseudoVSUB_VX_MF2_MASK + 10U, // PseudoVSUB_VX_MF4 + 10U, // PseudoVSUB_VX_MF4_MASK + 10U, // PseudoVSUB_VX_MF8 + 10U, // PseudoVSUB_VX_MF8_MASK + 10U, // PseudoVSUXEI16_V_M1_M1 + 10U, // PseudoVSUXEI16_V_M1_M1_MASK + 10U, // PseudoVSUXEI16_V_M1_M2 + 10U, // PseudoVSUXEI16_V_M1_M2_MASK + 10U, // PseudoVSUXEI16_V_M1_M4 + 10U, // PseudoVSUXEI16_V_M1_M4_MASK + 10U, // PseudoVSUXEI16_V_M1_MF2 + 10U, // PseudoVSUXEI16_V_M1_MF2_MASK + 10U, // PseudoVSUXEI16_V_M2_M1 + 10U, // PseudoVSUXEI16_V_M2_M1_MASK + 10U, // PseudoVSUXEI16_V_M2_M2 + 10U, // PseudoVSUXEI16_V_M2_M2_MASK + 10U, // PseudoVSUXEI16_V_M2_M4 + 10U, // PseudoVSUXEI16_V_M2_M4_MASK + 10U, // PseudoVSUXEI16_V_M2_M8 + 10U, // PseudoVSUXEI16_V_M2_M8_MASK + 10U, // PseudoVSUXEI16_V_M4_M2 + 10U, // PseudoVSUXEI16_V_M4_M2_MASK + 10U, // PseudoVSUXEI16_V_M4_M4 + 10U, // PseudoVSUXEI16_V_M4_M4_MASK + 10U, // PseudoVSUXEI16_V_M4_M8 + 10U, // PseudoVSUXEI16_V_M4_M8_MASK + 10U, // PseudoVSUXEI16_V_M8_M4 + 10U, // PseudoVSUXEI16_V_M8_M4_MASK + 10U, // PseudoVSUXEI16_V_M8_M8 + 10U, // PseudoVSUXEI16_V_M8_M8_MASK + 10U, // PseudoVSUXEI16_V_MF2_M1 + 10U, // PseudoVSUXEI16_V_MF2_M1_MASK + 10U, // PseudoVSUXEI16_V_MF2_M2 + 10U, // PseudoVSUXEI16_V_MF2_M2_MASK + 10U, // PseudoVSUXEI16_V_MF2_MF2 + 10U, // PseudoVSUXEI16_V_MF2_MF2_MASK + 10U, // PseudoVSUXEI16_V_MF2_MF4 + 10U, // PseudoVSUXEI16_V_MF2_MF4_MASK + 10U, // PseudoVSUXEI16_V_MF4_M1 + 10U, // PseudoVSUXEI16_V_MF4_M1_MASK + 10U, // PseudoVSUXEI16_V_MF4_MF2 + 10U, // PseudoVSUXEI16_V_MF4_MF2_MASK + 10U, // PseudoVSUXEI16_V_MF4_MF4 + 10U, // PseudoVSUXEI16_V_MF4_MF4_MASK + 10U, // PseudoVSUXEI16_V_MF4_MF8 + 10U, // PseudoVSUXEI16_V_MF4_MF8_MASK + 10U, // PseudoVSUXEI32_V_M1_M1 + 10U, // PseudoVSUXEI32_V_M1_M1_MASK + 10U, // PseudoVSUXEI32_V_M1_M2 + 10U, // PseudoVSUXEI32_V_M1_M2_MASK + 10U, // PseudoVSUXEI32_V_M1_MF2 + 10U, // PseudoVSUXEI32_V_M1_MF2_MASK + 10U, // PseudoVSUXEI32_V_M1_MF4 + 10U, // PseudoVSUXEI32_V_M1_MF4_MASK + 10U, // PseudoVSUXEI32_V_M2_M1 + 10U, // PseudoVSUXEI32_V_M2_M1_MASK + 10U, // PseudoVSUXEI32_V_M2_M2 + 10U, // PseudoVSUXEI32_V_M2_M2_MASK + 10U, // PseudoVSUXEI32_V_M2_M4 + 10U, // PseudoVSUXEI32_V_M2_M4_MASK + 10U, // PseudoVSUXEI32_V_M2_MF2 + 10U, // PseudoVSUXEI32_V_M2_MF2_MASK + 10U, // PseudoVSUXEI32_V_M4_M1 + 10U, // PseudoVSUXEI32_V_M4_M1_MASK + 10U, // PseudoVSUXEI32_V_M4_M2 + 10U, // PseudoVSUXEI32_V_M4_M2_MASK + 10U, // PseudoVSUXEI32_V_M4_M4 + 10U, // PseudoVSUXEI32_V_M4_M4_MASK + 10U, // PseudoVSUXEI32_V_M4_M8 + 10U, // PseudoVSUXEI32_V_M4_M8_MASK + 10U, // PseudoVSUXEI32_V_M8_M2 + 10U, // PseudoVSUXEI32_V_M8_M2_MASK + 10U, // PseudoVSUXEI32_V_M8_M4 + 10U, // PseudoVSUXEI32_V_M8_M4_MASK + 10U, // PseudoVSUXEI32_V_M8_M8 + 10U, // PseudoVSUXEI32_V_M8_M8_MASK + 10U, // PseudoVSUXEI32_V_MF2_M1 + 10U, // PseudoVSUXEI32_V_MF2_M1_MASK + 10U, // PseudoVSUXEI32_V_MF2_MF2 + 10U, // PseudoVSUXEI32_V_MF2_MF2_MASK + 10U, // PseudoVSUXEI32_V_MF2_MF4 + 10U, // PseudoVSUXEI32_V_MF2_MF4_MASK + 10U, // PseudoVSUXEI32_V_MF2_MF8 + 10U, // PseudoVSUXEI32_V_MF2_MF8_MASK + 10U, // PseudoVSUXEI64_V_M1_M1 + 10U, // PseudoVSUXEI64_V_M1_M1_MASK + 10U, // PseudoVSUXEI64_V_M1_MF2 + 10U, // PseudoVSUXEI64_V_M1_MF2_MASK + 10U, // PseudoVSUXEI64_V_M1_MF4 + 10U, // PseudoVSUXEI64_V_M1_MF4_MASK + 10U, // PseudoVSUXEI64_V_M1_MF8 + 10U, // PseudoVSUXEI64_V_M1_MF8_MASK + 10U, // PseudoVSUXEI64_V_M2_M1 + 10U, // PseudoVSUXEI64_V_M2_M1_MASK + 10U, // PseudoVSUXEI64_V_M2_M2 + 10U, // PseudoVSUXEI64_V_M2_M2_MASK + 10U, // PseudoVSUXEI64_V_M2_MF2 + 10U, // PseudoVSUXEI64_V_M2_MF2_MASK + 10U, // PseudoVSUXEI64_V_M2_MF4 + 10U, // PseudoVSUXEI64_V_M2_MF4_MASK + 10U, // PseudoVSUXEI64_V_M4_M1 + 10U, // PseudoVSUXEI64_V_M4_M1_MASK + 10U, // PseudoVSUXEI64_V_M4_M2 + 10U, // PseudoVSUXEI64_V_M4_M2_MASK + 10U, // PseudoVSUXEI64_V_M4_M4 + 10U, // PseudoVSUXEI64_V_M4_M4_MASK + 10U, // PseudoVSUXEI64_V_M4_MF2 + 10U, // PseudoVSUXEI64_V_M4_MF2_MASK + 10U, // PseudoVSUXEI64_V_M8_M1 + 10U, // PseudoVSUXEI64_V_M8_M1_MASK + 10U, // PseudoVSUXEI64_V_M8_M2 + 10U, // PseudoVSUXEI64_V_M8_M2_MASK + 10U, // PseudoVSUXEI64_V_M8_M4 + 10U, // PseudoVSUXEI64_V_M8_M4_MASK + 10U, // PseudoVSUXEI64_V_M8_M8 + 10U, // PseudoVSUXEI64_V_M8_M8_MASK + 10U, // PseudoVSUXEI8_V_M1_M1 + 10U, // PseudoVSUXEI8_V_M1_M1_MASK + 10U, // PseudoVSUXEI8_V_M1_M2 + 10U, // PseudoVSUXEI8_V_M1_M2_MASK + 10U, // PseudoVSUXEI8_V_M1_M4 + 10U, // PseudoVSUXEI8_V_M1_M4_MASK + 10U, // PseudoVSUXEI8_V_M1_M8 + 10U, // PseudoVSUXEI8_V_M1_M8_MASK + 10U, // PseudoVSUXEI8_V_M2_M2 + 10U, // PseudoVSUXEI8_V_M2_M2_MASK + 10U, // PseudoVSUXEI8_V_M2_M4 + 10U, // PseudoVSUXEI8_V_M2_M4_MASK + 10U, // PseudoVSUXEI8_V_M2_M8 + 10U, // PseudoVSUXEI8_V_M2_M8_MASK + 10U, // PseudoVSUXEI8_V_M4_M4 + 10U, // PseudoVSUXEI8_V_M4_M4_MASK + 10U, // PseudoVSUXEI8_V_M4_M8 + 10U, // PseudoVSUXEI8_V_M4_M8_MASK + 10U, // PseudoVSUXEI8_V_M8_M8 + 10U, // PseudoVSUXEI8_V_M8_M8_MASK + 10U, // PseudoVSUXEI8_V_MF2_M1 + 10U, // PseudoVSUXEI8_V_MF2_M1_MASK + 10U, // PseudoVSUXEI8_V_MF2_M2 + 10U, // PseudoVSUXEI8_V_MF2_M2_MASK + 10U, // PseudoVSUXEI8_V_MF2_M4 + 10U, // PseudoVSUXEI8_V_MF2_M4_MASK + 10U, // PseudoVSUXEI8_V_MF2_MF2 + 10U, // PseudoVSUXEI8_V_MF2_MF2_MASK + 10U, // PseudoVSUXEI8_V_MF4_M1 + 10U, // PseudoVSUXEI8_V_MF4_M1_MASK + 10U, // PseudoVSUXEI8_V_MF4_M2 + 10U, // PseudoVSUXEI8_V_MF4_M2_MASK + 10U, // PseudoVSUXEI8_V_MF4_MF2 + 10U, // PseudoVSUXEI8_V_MF4_MF2_MASK + 10U, // PseudoVSUXEI8_V_MF4_MF4 + 10U, // PseudoVSUXEI8_V_MF4_MF4_MASK + 10U, // PseudoVSUXEI8_V_MF8_M1 + 10U, // PseudoVSUXEI8_V_MF8_M1_MASK + 10U, // PseudoVSUXEI8_V_MF8_MF2 + 10U, // PseudoVSUXEI8_V_MF8_MF2_MASK + 10U, // PseudoVSUXEI8_V_MF8_MF4 + 10U, // PseudoVSUXEI8_V_MF8_MF4_MASK + 10U, // PseudoVSUXEI8_V_MF8_MF8 + 10U, // PseudoVSUXEI8_V_MF8_MF8_MASK + 10U, // PseudoVSUXSEG2EI16_V_M1_M1 + 10U, // PseudoVSUXSEG2EI16_V_M1_M1_MASK + 10U, // PseudoVSUXSEG2EI16_V_M1_M2 + 10U, // PseudoVSUXSEG2EI16_V_M1_M2_MASK + 10U, // PseudoVSUXSEG2EI16_V_M1_M4 + 10U, // PseudoVSUXSEG2EI16_V_M1_M4_MASK + 10U, // PseudoVSUXSEG2EI16_V_M1_MF2 + 10U, // PseudoVSUXSEG2EI16_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG2EI16_V_M2_M1 + 10U, // PseudoVSUXSEG2EI16_V_M2_M1_MASK + 10U, // PseudoVSUXSEG2EI16_V_M2_M2 + 10U, // PseudoVSUXSEG2EI16_V_M2_M2_MASK + 10U, // PseudoVSUXSEG2EI16_V_M2_M4 + 10U, // PseudoVSUXSEG2EI16_V_M2_M4_MASK + 10U, // PseudoVSUXSEG2EI16_V_M4_M2 + 10U, // PseudoVSUXSEG2EI16_V_M4_M2_MASK + 10U, // PseudoVSUXSEG2EI16_V_M4_M4 + 10U, // PseudoVSUXSEG2EI16_V_M4_M4_MASK + 10U, // PseudoVSUXSEG2EI16_V_M8_M4 + 10U, // PseudoVSUXSEG2EI16_V_M8_M4_MASK + 10U, // PseudoVSUXSEG2EI16_V_MF2_M1 + 10U, // PseudoVSUXSEG2EI16_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG2EI16_V_MF2_M2 + 10U, // PseudoVSUXSEG2EI16_V_MF2_M2_MASK + 10U, // PseudoVSUXSEG2EI16_V_MF2_MF2 + 10U, // PseudoVSUXSEG2EI16_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG2EI16_V_MF2_MF4 + 10U, // PseudoVSUXSEG2EI16_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG2EI16_V_MF4_M1 + 10U, // PseudoVSUXSEG2EI16_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG2EI16_V_MF4_MF2 + 10U, // PseudoVSUXSEG2EI16_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG2EI16_V_MF4_MF4 + 10U, // PseudoVSUXSEG2EI16_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG2EI16_V_MF4_MF8 + 10U, // PseudoVSUXSEG2EI16_V_MF4_MF8_MASK + 10U, // PseudoVSUXSEG2EI32_V_M1_M1 + 10U, // PseudoVSUXSEG2EI32_V_M1_M1_MASK + 10U, // PseudoVSUXSEG2EI32_V_M1_M2 + 10U, // PseudoVSUXSEG2EI32_V_M1_M2_MASK + 10U, // PseudoVSUXSEG2EI32_V_M1_MF2 + 10U, // PseudoVSUXSEG2EI32_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG2EI32_V_M1_MF4 + 10U, // PseudoVSUXSEG2EI32_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG2EI32_V_M2_M1 + 10U, // PseudoVSUXSEG2EI32_V_M2_M1_MASK + 10U, // PseudoVSUXSEG2EI32_V_M2_M2 + 10U, // PseudoVSUXSEG2EI32_V_M2_M2_MASK + 10U, // PseudoVSUXSEG2EI32_V_M2_M4 + 10U, // PseudoVSUXSEG2EI32_V_M2_M4_MASK + 10U, // PseudoVSUXSEG2EI32_V_M2_MF2 + 10U, // PseudoVSUXSEG2EI32_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG2EI32_V_M4_M1 + 10U, // PseudoVSUXSEG2EI32_V_M4_M1_MASK + 10U, // PseudoVSUXSEG2EI32_V_M4_M2 + 10U, // PseudoVSUXSEG2EI32_V_M4_M2_MASK + 10U, // PseudoVSUXSEG2EI32_V_M4_M4 + 10U, // PseudoVSUXSEG2EI32_V_M4_M4_MASK + 10U, // PseudoVSUXSEG2EI32_V_M8_M2 + 10U, // PseudoVSUXSEG2EI32_V_M8_M2_MASK + 10U, // PseudoVSUXSEG2EI32_V_M8_M4 + 10U, // PseudoVSUXSEG2EI32_V_M8_M4_MASK + 10U, // PseudoVSUXSEG2EI32_V_MF2_M1 + 10U, // PseudoVSUXSEG2EI32_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG2EI32_V_MF2_MF2 + 10U, // PseudoVSUXSEG2EI32_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG2EI32_V_MF2_MF4 + 10U, // PseudoVSUXSEG2EI32_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG2EI32_V_MF2_MF8 + 10U, // PseudoVSUXSEG2EI32_V_MF2_MF8_MASK + 10U, // PseudoVSUXSEG2EI64_V_M1_M1 + 10U, // PseudoVSUXSEG2EI64_V_M1_M1_MASK + 10U, // PseudoVSUXSEG2EI64_V_M1_MF2 + 10U, // PseudoVSUXSEG2EI64_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG2EI64_V_M1_MF4 + 10U, // PseudoVSUXSEG2EI64_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG2EI64_V_M1_MF8 + 10U, // PseudoVSUXSEG2EI64_V_M1_MF8_MASK + 10U, // PseudoVSUXSEG2EI64_V_M2_M1 + 10U, // PseudoVSUXSEG2EI64_V_M2_M1_MASK + 10U, // PseudoVSUXSEG2EI64_V_M2_M2 + 10U, // PseudoVSUXSEG2EI64_V_M2_M2_MASK + 10U, // PseudoVSUXSEG2EI64_V_M2_MF2 + 10U, // PseudoVSUXSEG2EI64_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG2EI64_V_M2_MF4 + 10U, // PseudoVSUXSEG2EI64_V_M2_MF4_MASK + 10U, // PseudoVSUXSEG2EI64_V_M4_M1 + 10U, // PseudoVSUXSEG2EI64_V_M4_M1_MASK + 10U, // PseudoVSUXSEG2EI64_V_M4_M2 + 10U, // PseudoVSUXSEG2EI64_V_M4_M2_MASK + 10U, // PseudoVSUXSEG2EI64_V_M4_M4 + 10U, // PseudoVSUXSEG2EI64_V_M4_M4_MASK + 10U, // PseudoVSUXSEG2EI64_V_M4_MF2 + 10U, // PseudoVSUXSEG2EI64_V_M4_MF2_MASK + 10U, // PseudoVSUXSEG2EI64_V_M8_M1 + 10U, // PseudoVSUXSEG2EI64_V_M8_M1_MASK + 10U, // PseudoVSUXSEG2EI64_V_M8_M2 + 10U, // PseudoVSUXSEG2EI64_V_M8_M2_MASK + 10U, // PseudoVSUXSEG2EI64_V_M8_M4 + 10U, // PseudoVSUXSEG2EI64_V_M8_M4_MASK + 10U, // PseudoVSUXSEG2EI8_V_M1_M1 + 10U, // PseudoVSUXSEG2EI8_V_M1_M1_MASK + 10U, // PseudoVSUXSEG2EI8_V_M1_M2 + 10U, // PseudoVSUXSEG2EI8_V_M1_M2_MASK + 10U, // PseudoVSUXSEG2EI8_V_M1_M4 + 10U, // PseudoVSUXSEG2EI8_V_M1_M4_MASK + 10U, // PseudoVSUXSEG2EI8_V_M2_M2 + 10U, // PseudoVSUXSEG2EI8_V_M2_M2_MASK + 10U, // PseudoVSUXSEG2EI8_V_M2_M4 + 10U, // PseudoVSUXSEG2EI8_V_M2_M4_MASK + 10U, // PseudoVSUXSEG2EI8_V_M4_M4 + 10U, // PseudoVSUXSEG2EI8_V_M4_M4_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF2_M1 + 10U, // PseudoVSUXSEG2EI8_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF2_M2 + 10U, // PseudoVSUXSEG2EI8_V_MF2_M2_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF2_M4 + 10U, // PseudoVSUXSEG2EI8_V_MF2_M4_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF2_MF2 + 10U, // PseudoVSUXSEG2EI8_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF4_M1 + 10U, // PseudoVSUXSEG2EI8_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF4_M2 + 10U, // PseudoVSUXSEG2EI8_V_MF4_M2_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF4_MF2 + 10U, // PseudoVSUXSEG2EI8_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF4_MF4 + 10U, // PseudoVSUXSEG2EI8_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF8_M1 + 10U, // PseudoVSUXSEG2EI8_V_MF8_M1_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF8_MF2 + 10U, // PseudoVSUXSEG2EI8_V_MF8_MF2_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF8_MF4 + 10U, // PseudoVSUXSEG2EI8_V_MF8_MF4_MASK + 10U, // PseudoVSUXSEG2EI8_V_MF8_MF8 + 10U, // PseudoVSUXSEG2EI8_V_MF8_MF8_MASK + 10U, // PseudoVSUXSEG3EI16_V_M1_M1 + 10U, // PseudoVSUXSEG3EI16_V_M1_M1_MASK + 10U, // PseudoVSUXSEG3EI16_V_M1_M2 + 10U, // PseudoVSUXSEG3EI16_V_M1_M2_MASK + 10U, // PseudoVSUXSEG3EI16_V_M1_MF2 + 10U, // PseudoVSUXSEG3EI16_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG3EI16_V_M2_M1 + 10U, // PseudoVSUXSEG3EI16_V_M2_M1_MASK + 10U, // PseudoVSUXSEG3EI16_V_M2_M2 + 10U, // PseudoVSUXSEG3EI16_V_M2_M2_MASK + 10U, // PseudoVSUXSEG3EI16_V_M4_M2 + 10U, // PseudoVSUXSEG3EI16_V_M4_M2_MASK + 10U, // PseudoVSUXSEG3EI16_V_MF2_M1 + 10U, // PseudoVSUXSEG3EI16_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG3EI16_V_MF2_M2 + 10U, // PseudoVSUXSEG3EI16_V_MF2_M2_MASK + 10U, // PseudoVSUXSEG3EI16_V_MF2_MF2 + 10U, // PseudoVSUXSEG3EI16_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG3EI16_V_MF2_MF4 + 10U, // PseudoVSUXSEG3EI16_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG3EI16_V_MF4_M1 + 10U, // PseudoVSUXSEG3EI16_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG3EI16_V_MF4_MF2 + 10U, // PseudoVSUXSEG3EI16_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG3EI16_V_MF4_MF4 + 10U, // PseudoVSUXSEG3EI16_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG3EI16_V_MF4_MF8 + 10U, // PseudoVSUXSEG3EI16_V_MF4_MF8_MASK + 10U, // PseudoVSUXSEG3EI32_V_M1_M1 + 10U, // PseudoVSUXSEG3EI32_V_M1_M1_MASK + 10U, // PseudoVSUXSEG3EI32_V_M1_M2 + 10U, // PseudoVSUXSEG3EI32_V_M1_M2_MASK + 10U, // PseudoVSUXSEG3EI32_V_M1_MF2 + 10U, // PseudoVSUXSEG3EI32_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG3EI32_V_M1_MF4 + 10U, // PseudoVSUXSEG3EI32_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG3EI32_V_M2_M1 + 10U, // PseudoVSUXSEG3EI32_V_M2_M1_MASK + 10U, // PseudoVSUXSEG3EI32_V_M2_M2 + 10U, // PseudoVSUXSEG3EI32_V_M2_M2_MASK + 10U, // PseudoVSUXSEG3EI32_V_M2_MF2 + 10U, // PseudoVSUXSEG3EI32_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG3EI32_V_M4_M1 + 10U, // PseudoVSUXSEG3EI32_V_M4_M1_MASK + 10U, // PseudoVSUXSEG3EI32_V_M4_M2 + 10U, // PseudoVSUXSEG3EI32_V_M4_M2_MASK + 10U, // PseudoVSUXSEG3EI32_V_M8_M2 + 10U, // PseudoVSUXSEG3EI32_V_M8_M2_MASK + 10U, // PseudoVSUXSEG3EI32_V_MF2_M1 + 10U, // PseudoVSUXSEG3EI32_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG3EI32_V_MF2_MF2 + 10U, // PseudoVSUXSEG3EI32_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG3EI32_V_MF2_MF4 + 10U, // PseudoVSUXSEG3EI32_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG3EI32_V_MF2_MF8 + 10U, // PseudoVSUXSEG3EI32_V_MF2_MF8_MASK + 10U, // PseudoVSUXSEG3EI64_V_M1_M1 + 10U, // PseudoVSUXSEG3EI64_V_M1_M1_MASK + 10U, // PseudoVSUXSEG3EI64_V_M1_MF2 + 10U, // PseudoVSUXSEG3EI64_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG3EI64_V_M1_MF4 + 10U, // PseudoVSUXSEG3EI64_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG3EI64_V_M1_MF8 + 10U, // PseudoVSUXSEG3EI64_V_M1_MF8_MASK + 10U, // PseudoVSUXSEG3EI64_V_M2_M1 + 10U, // PseudoVSUXSEG3EI64_V_M2_M1_MASK + 10U, // PseudoVSUXSEG3EI64_V_M2_M2 + 10U, // PseudoVSUXSEG3EI64_V_M2_M2_MASK + 10U, // PseudoVSUXSEG3EI64_V_M2_MF2 + 10U, // PseudoVSUXSEG3EI64_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG3EI64_V_M2_MF4 + 10U, // PseudoVSUXSEG3EI64_V_M2_MF4_MASK + 10U, // PseudoVSUXSEG3EI64_V_M4_M1 + 10U, // PseudoVSUXSEG3EI64_V_M4_M1_MASK + 10U, // PseudoVSUXSEG3EI64_V_M4_M2 + 10U, // PseudoVSUXSEG3EI64_V_M4_M2_MASK + 10U, // PseudoVSUXSEG3EI64_V_M4_MF2 + 10U, // PseudoVSUXSEG3EI64_V_M4_MF2_MASK + 10U, // PseudoVSUXSEG3EI64_V_M8_M1 + 10U, // PseudoVSUXSEG3EI64_V_M8_M1_MASK + 10U, // PseudoVSUXSEG3EI64_V_M8_M2 + 10U, // PseudoVSUXSEG3EI64_V_M8_M2_MASK + 10U, // PseudoVSUXSEG3EI8_V_M1_M1 + 10U, // PseudoVSUXSEG3EI8_V_M1_M1_MASK + 10U, // PseudoVSUXSEG3EI8_V_M1_M2 + 10U, // PseudoVSUXSEG3EI8_V_M1_M2_MASK + 10U, // PseudoVSUXSEG3EI8_V_M2_M2 + 10U, // PseudoVSUXSEG3EI8_V_M2_M2_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF2_M1 + 10U, // PseudoVSUXSEG3EI8_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF2_M2 + 10U, // PseudoVSUXSEG3EI8_V_MF2_M2_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF2_MF2 + 10U, // PseudoVSUXSEG3EI8_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF4_M1 + 10U, // PseudoVSUXSEG3EI8_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF4_M2 + 10U, // PseudoVSUXSEG3EI8_V_MF4_M2_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF4_MF2 + 10U, // PseudoVSUXSEG3EI8_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF4_MF4 + 10U, // PseudoVSUXSEG3EI8_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF8_M1 + 10U, // PseudoVSUXSEG3EI8_V_MF8_M1_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF8_MF2 + 10U, // PseudoVSUXSEG3EI8_V_MF8_MF2_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF8_MF4 + 10U, // PseudoVSUXSEG3EI8_V_MF8_MF4_MASK + 10U, // PseudoVSUXSEG3EI8_V_MF8_MF8 + 10U, // PseudoVSUXSEG3EI8_V_MF8_MF8_MASK + 10U, // PseudoVSUXSEG4EI16_V_M1_M1 + 10U, // PseudoVSUXSEG4EI16_V_M1_M1_MASK + 10U, // PseudoVSUXSEG4EI16_V_M1_M2 + 10U, // PseudoVSUXSEG4EI16_V_M1_M2_MASK + 10U, // PseudoVSUXSEG4EI16_V_M1_MF2 + 10U, // PseudoVSUXSEG4EI16_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG4EI16_V_M2_M1 + 10U, // PseudoVSUXSEG4EI16_V_M2_M1_MASK + 10U, // PseudoVSUXSEG4EI16_V_M2_M2 + 10U, // PseudoVSUXSEG4EI16_V_M2_M2_MASK + 10U, // PseudoVSUXSEG4EI16_V_M4_M2 + 10U, // PseudoVSUXSEG4EI16_V_M4_M2_MASK + 10U, // PseudoVSUXSEG4EI16_V_MF2_M1 + 10U, // PseudoVSUXSEG4EI16_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG4EI16_V_MF2_M2 + 10U, // PseudoVSUXSEG4EI16_V_MF2_M2_MASK + 10U, // PseudoVSUXSEG4EI16_V_MF2_MF2 + 10U, // PseudoVSUXSEG4EI16_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG4EI16_V_MF2_MF4 + 10U, // PseudoVSUXSEG4EI16_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG4EI16_V_MF4_M1 + 10U, // PseudoVSUXSEG4EI16_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG4EI16_V_MF4_MF2 + 10U, // PseudoVSUXSEG4EI16_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG4EI16_V_MF4_MF4 + 10U, // PseudoVSUXSEG4EI16_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG4EI16_V_MF4_MF8 + 10U, // PseudoVSUXSEG4EI16_V_MF4_MF8_MASK + 10U, // PseudoVSUXSEG4EI32_V_M1_M1 + 10U, // PseudoVSUXSEG4EI32_V_M1_M1_MASK + 10U, // PseudoVSUXSEG4EI32_V_M1_M2 + 10U, // PseudoVSUXSEG4EI32_V_M1_M2_MASK + 10U, // PseudoVSUXSEG4EI32_V_M1_MF2 + 10U, // PseudoVSUXSEG4EI32_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG4EI32_V_M1_MF4 + 10U, // PseudoVSUXSEG4EI32_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG4EI32_V_M2_M1 + 10U, // PseudoVSUXSEG4EI32_V_M2_M1_MASK + 10U, // PseudoVSUXSEG4EI32_V_M2_M2 + 10U, // PseudoVSUXSEG4EI32_V_M2_M2_MASK + 10U, // PseudoVSUXSEG4EI32_V_M2_MF2 + 10U, // PseudoVSUXSEG4EI32_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG4EI32_V_M4_M1 + 10U, // PseudoVSUXSEG4EI32_V_M4_M1_MASK + 10U, // PseudoVSUXSEG4EI32_V_M4_M2 + 10U, // PseudoVSUXSEG4EI32_V_M4_M2_MASK + 10U, // PseudoVSUXSEG4EI32_V_M8_M2 + 10U, // PseudoVSUXSEG4EI32_V_M8_M2_MASK + 10U, // PseudoVSUXSEG4EI32_V_MF2_M1 + 10U, // PseudoVSUXSEG4EI32_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG4EI32_V_MF2_MF2 + 10U, // PseudoVSUXSEG4EI32_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG4EI32_V_MF2_MF4 + 10U, // PseudoVSUXSEG4EI32_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG4EI32_V_MF2_MF8 + 10U, // PseudoVSUXSEG4EI32_V_MF2_MF8_MASK + 10U, // PseudoVSUXSEG4EI64_V_M1_M1 + 10U, // PseudoVSUXSEG4EI64_V_M1_M1_MASK + 10U, // PseudoVSUXSEG4EI64_V_M1_MF2 + 10U, // PseudoVSUXSEG4EI64_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG4EI64_V_M1_MF4 + 10U, // PseudoVSUXSEG4EI64_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG4EI64_V_M1_MF8 + 10U, // PseudoVSUXSEG4EI64_V_M1_MF8_MASK + 10U, // PseudoVSUXSEG4EI64_V_M2_M1 + 10U, // PseudoVSUXSEG4EI64_V_M2_M1_MASK + 10U, // PseudoVSUXSEG4EI64_V_M2_M2 + 10U, // PseudoVSUXSEG4EI64_V_M2_M2_MASK + 10U, // PseudoVSUXSEG4EI64_V_M2_MF2 + 10U, // PseudoVSUXSEG4EI64_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG4EI64_V_M2_MF4 + 10U, // PseudoVSUXSEG4EI64_V_M2_MF4_MASK + 10U, // PseudoVSUXSEG4EI64_V_M4_M1 + 10U, // PseudoVSUXSEG4EI64_V_M4_M1_MASK + 10U, // PseudoVSUXSEG4EI64_V_M4_M2 + 10U, // PseudoVSUXSEG4EI64_V_M4_M2_MASK + 10U, // PseudoVSUXSEG4EI64_V_M4_MF2 + 10U, // PseudoVSUXSEG4EI64_V_M4_MF2_MASK + 10U, // PseudoVSUXSEG4EI64_V_M8_M1 + 10U, // PseudoVSUXSEG4EI64_V_M8_M1_MASK + 10U, // PseudoVSUXSEG4EI64_V_M8_M2 + 10U, // PseudoVSUXSEG4EI64_V_M8_M2_MASK + 10U, // PseudoVSUXSEG4EI8_V_M1_M1 + 10U, // PseudoVSUXSEG4EI8_V_M1_M1_MASK + 10U, // PseudoVSUXSEG4EI8_V_M1_M2 + 10U, // PseudoVSUXSEG4EI8_V_M1_M2_MASK + 10U, // PseudoVSUXSEG4EI8_V_M2_M2 + 10U, // PseudoVSUXSEG4EI8_V_M2_M2_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF2_M1 + 10U, // PseudoVSUXSEG4EI8_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF2_M2 + 10U, // PseudoVSUXSEG4EI8_V_MF2_M2_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF2_MF2 + 10U, // PseudoVSUXSEG4EI8_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF4_M1 + 10U, // PseudoVSUXSEG4EI8_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF4_M2 + 10U, // PseudoVSUXSEG4EI8_V_MF4_M2_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF4_MF2 + 10U, // PseudoVSUXSEG4EI8_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF4_MF4 + 10U, // PseudoVSUXSEG4EI8_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF8_M1 + 10U, // PseudoVSUXSEG4EI8_V_MF8_M1_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF8_MF2 + 10U, // PseudoVSUXSEG4EI8_V_MF8_MF2_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF8_MF4 + 10U, // PseudoVSUXSEG4EI8_V_MF8_MF4_MASK + 10U, // PseudoVSUXSEG4EI8_V_MF8_MF8 + 10U, // PseudoVSUXSEG4EI8_V_MF8_MF8_MASK + 10U, // PseudoVSUXSEG5EI16_V_M1_M1 + 10U, // PseudoVSUXSEG5EI16_V_M1_M1_MASK + 10U, // PseudoVSUXSEG5EI16_V_M1_MF2 + 10U, // PseudoVSUXSEG5EI16_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG5EI16_V_M2_M1 + 10U, // PseudoVSUXSEG5EI16_V_M2_M1_MASK + 10U, // PseudoVSUXSEG5EI16_V_MF2_M1 + 10U, // PseudoVSUXSEG5EI16_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG5EI16_V_MF2_MF2 + 10U, // PseudoVSUXSEG5EI16_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG5EI16_V_MF2_MF4 + 10U, // PseudoVSUXSEG5EI16_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG5EI16_V_MF4_M1 + 10U, // PseudoVSUXSEG5EI16_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG5EI16_V_MF4_MF2 + 10U, // PseudoVSUXSEG5EI16_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG5EI16_V_MF4_MF4 + 10U, // PseudoVSUXSEG5EI16_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG5EI16_V_MF4_MF8 + 10U, // PseudoVSUXSEG5EI16_V_MF4_MF8_MASK + 10U, // PseudoVSUXSEG5EI32_V_M1_M1 + 10U, // PseudoVSUXSEG5EI32_V_M1_M1_MASK + 10U, // PseudoVSUXSEG5EI32_V_M1_MF2 + 10U, // PseudoVSUXSEG5EI32_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG5EI32_V_M1_MF4 + 10U, // PseudoVSUXSEG5EI32_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG5EI32_V_M2_M1 + 10U, // PseudoVSUXSEG5EI32_V_M2_M1_MASK + 10U, // PseudoVSUXSEG5EI32_V_M2_MF2 + 10U, // PseudoVSUXSEG5EI32_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG5EI32_V_M4_M1 + 10U, // PseudoVSUXSEG5EI32_V_M4_M1_MASK + 10U, // PseudoVSUXSEG5EI32_V_MF2_M1 + 10U, // PseudoVSUXSEG5EI32_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG5EI32_V_MF2_MF2 + 10U, // PseudoVSUXSEG5EI32_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG5EI32_V_MF2_MF4 + 10U, // PseudoVSUXSEG5EI32_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG5EI32_V_MF2_MF8 + 10U, // PseudoVSUXSEG5EI32_V_MF2_MF8_MASK + 10U, // PseudoVSUXSEG5EI64_V_M1_M1 + 10U, // PseudoVSUXSEG5EI64_V_M1_M1_MASK + 10U, // PseudoVSUXSEG5EI64_V_M1_MF2 + 10U, // PseudoVSUXSEG5EI64_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG5EI64_V_M1_MF4 + 10U, // PseudoVSUXSEG5EI64_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG5EI64_V_M1_MF8 + 10U, // PseudoVSUXSEG5EI64_V_M1_MF8_MASK + 10U, // PseudoVSUXSEG5EI64_V_M2_M1 + 10U, // PseudoVSUXSEG5EI64_V_M2_M1_MASK + 10U, // PseudoVSUXSEG5EI64_V_M2_MF2 + 10U, // PseudoVSUXSEG5EI64_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG5EI64_V_M2_MF4 + 10U, // PseudoVSUXSEG5EI64_V_M2_MF4_MASK + 10U, // PseudoVSUXSEG5EI64_V_M4_M1 + 10U, // PseudoVSUXSEG5EI64_V_M4_M1_MASK + 10U, // PseudoVSUXSEG5EI64_V_M4_MF2 + 10U, // PseudoVSUXSEG5EI64_V_M4_MF2_MASK + 10U, // PseudoVSUXSEG5EI64_V_M8_M1 + 10U, // PseudoVSUXSEG5EI64_V_M8_M1_MASK + 10U, // PseudoVSUXSEG5EI8_V_M1_M1 + 10U, // PseudoVSUXSEG5EI8_V_M1_M1_MASK + 10U, // PseudoVSUXSEG5EI8_V_MF2_M1 + 10U, // PseudoVSUXSEG5EI8_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG5EI8_V_MF2_MF2 + 10U, // PseudoVSUXSEG5EI8_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG5EI8_V_MF4_M1 + 10U, // PseudoVSUXSEG5EI8_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG5EI8_V_MF4_MF2 + 10U, // PseudoVSUXSEG5EI8_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG5EI8_V_MF4_MF4 + 10U, // PseudoVSUXSEG5EI8_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG5EI8_V_MF8_M1 + 10U, // PseudoVSUXSEG5EI8_V_MF8_M1_MASK + 10U, // PseudoVSUXSEG5EI8_V_MF8_MF2 + 10U, // PseudoVSUXSEG5EI8_V_MF8_MF2_MASK + 10U, // PseudoVSUXSEG5EI8_V_MF8_MF4 + 10U, // PseudoVSUXSEG5EI8_V_MF8_MF4_MASK + 10U, // PseudoVSUXSEG5EI8_V_MF8_MF8 + 10U, // PseudoVSUXSEG5EI8_V_MF8_MF8_MASK + 10U, // PseudoVSUXSEG6EI16_V_M1_M1 + 10U, // PseudoVSUXSEG6EI16_V_M1_M1_MASK + 10U, // PseudoVSUXSEG6EI16_V_M1_MF2 + 10U, // PseudoVSUXSEG6EI16_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG6EI16_V_M2_M1 + 10U, // PseudoVSUXSEG6EI16_V_M2_M1_MASK + 10U, // PseudoVSUXSEG6EI16_V_MF2_M1 + 10U, // PseudoVSUXSEG6EI16_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG6EI16_V_MF2_MF2 + 10U, // PseudoVSUXSEG6EI16_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG6EI16_V_MF2_MF4 + 10U, // PseudoVSUXSEG6EI16_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG6EI16_V_MF4_M1 + 10U, // PseudoVSUXSEG6EI16_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG6EI16_V_MF4_MF2 + 10U, // PseudoVSUXSEG6EI16_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG6EI16_V_MF4_MF4 + 10U, // PseudoVSUXSEG6EI16_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG6EI16_V_MF4_MF8 + 10U, // PseudoVSUXSEG6EI16_V_MF4_MF8_MASK + 10U, // PseudoVSUXSEG6EI32_V_M1_M1 + 10U, // PseudoVSUXSEG6EI32_V_M1_M1_MASK + 10U, // PseudoVSUXSEG6EI32_V_M1_MF2 + 10U, // PseudoVSUXSEG6EI32_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG6EI32_V_M1_MF4 + 10U, // PseudoVSUXSEG6EI32_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG6EI32_V_M2_M1 + 10U, // PseudoVSUXSEG6EI32_V_M2_M1_MASK + 10U, // PseudoVSUXSEG6EI32_V_M2_MF2 + 10U, // PseudoVSUXSEG6EI32_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG6EI32_V_M4_M1 + 10U, // PseudoVSUXSEG6EI32_V_M4_M1_MASK + 10U, // PseudoVSUXSEG6EI32_V_MF2_M1 + 10U, // PseudoVSUXSEG6EI32_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG6EI32_V_MF2_MF2 + 10U, // PseudoVSUXSEG6EI32_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG6EI32_V_MF2_MF4 + 10U, // PseudoVSUXSEG6EI32_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG6EI32_V_MF2_MF8 + 10U, // PseudoVSUXSEG6EI32_V_MF2_MF8_MASK + 10U, // PseudoVSUXSEG6EI64_V_M1_M1 + 10U, // PseudoVSUXSEG6EI64_V_M1_M1_MASK + 10U, // PseudoVSUXSEG6EI64_V_M1_MF2 + 10U, // PseudoVSUXSEG6EI64_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG6EI64_V_M1_MF4 + 10U, // PseudoVSUXSEG6EI64_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG6EI64_V_M1_MF8 + 10U, // PseudoVSUXSEG6EI64_V_M1_MF8_MASK + 10U, // PseudoVSUXSEG6EI64_V_M2_M1 + 10U, // PseudoVSUXSEG6EI64_V_M2_M1_MASK + 10U, // PseudoVSUXSEG6EI64_V_M2_MF2 + 10U, // PseudoVSUXSEG6EI64_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG6EI64_V_M2_MF4 + 10U, // PseudoVSUXSEG6EI64_V_M2_MF4_MASK + 10U, // PseudoVSUXSEG6EI64_V_M4_M1 + 10U, // PseudoVSUXSEG6EI64_V_M4_M1_MASK + 10U, // PseudoVSUXSEG6EI64_V_M4_MF2 + 10U, // PseudoVSUXSEG6EI64_V_M4_MF2_MASK + 10U, // PseudoVSUXSEG6EI64_V_M8_M1 + 10U, // PseudoVSUXSEG6EI64_V_M8_M1_MASK + 10U, // PseudoVSUXSEG6EI8_V_M1_M1 + 10U, // PseudoVSUXSEG6EI8_V_M1_M1_MASK + 10U, // PseudoVSUXSEG6EI8_V_MF2_M1 + 10U, // PseudoVSUXSEG6EI8_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG6EI8_V_MF2_MF2 + 10U, // PseudoVSUXSEG6EI8_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG6EI8_V_MF4_M1 + 10U, // PseudoVSUXSEG6EI8_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG6EI8_V_MF4_MF2 + 10U, // PseudoVSUXSEG6EI8_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG6EI8_V_MF4_MF4 + 10U, // PseudoVSUXSEG6EI8_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG6EI8_V_MF8_M1 + 10U, // PseudoVSUXSEG6EI8_V_MF8_M1_MASK + 10U, // PseudoVSUXSEG6EI8_V_MF8_MF2 + 10U, // PseudoVSUXSEG6EI8_V_MF8_MF2_MASK + 10U, // PseudoVSUXSEG6EI8_V_MF8_MF4 + 10U, // PseudoVSUXSEG6EI8_V_MF8_MF4_MASK + 10U, // PseudoVSUXSEG6EI8_V_MF8_MF8 + 10U, // PseudoVSUXSEG6EI8_V_MF8_MF8_MASK + 10U, // PseudoVSUXSEG7EI16_V_M1_M1 + 10U, // PseudoVSUXSEG7EI16_V_M1_M1_MASK + 10U, // PseudoVSUXSEG7EI16_V_M1_MF2 + 10U, // PseudoVSUXSEG7EI16_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG7EI16_V_M2_M1 + 10U, // PseudoVSUXSEG7EI16_V_M2_M1_MASK + 10U, // PseudoVSUXSEG7EI16_V_MF2_M1 + 10U, // PseudoVSUXSEG7EI16_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG7EI16_V_MF2_MF2 + 10U, // PseudoVSUXSEG7EI16_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG7EI16_V_MF2_MF4 + 10U, // PseudoVSUXSEG7EI16_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG7EI16_V_MF4_M1 + 10U, // PseudoVSUXSEG7EI16_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG7EI16_V_MF4_MF2 + 10U, // PseudoVSUXSEG7EI16_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG7EI16_V_MF4_MF4 + 10U, // PseudoVSUXSEG7EI16_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG7EI16_V_MF4_MF8 + 10U, // PseudoVSUXSEG7EI16_V_MF4_MF8_MASK + 10U, // PseudoVSUXSEG7EI32_V_M1_M1 + 10U, // PseudoVSUXSEG7EI32_V_M1_M1_MASK + 10U, // PseudoVSUXSEG7EI32_V_M1_MF2 + 10U, // PseudoVSUXSEG7EI32_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG7EI32_V_M1_MF4 + 10U, // PseudoVSUXSEG7EI32_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG7EI32_V_M2_M1 + 10U, // PseudoVSUXSEG7EI32_V_M2_M1_MASK + 10U, // PseudoVSUXSEG7EI32_V_M2_MF2 + 10U, // PseudoVSUXSEG7EI32_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG7EI32_V_M4_M1 + 10U, // PseudoVSUXSEG7EI32_V_M4_M1_MASK + 10U, // PseudoVSUXSEG7EI32_V_MF2_M1 + 10U, // PseudoVSUXSEG7EI32_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG7EI32_V_MF2_MF2 + 10U, // PseudoVSUXSEG7EI32_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG7EI32_V_MF2_MF4 + 10U, // PseudoVSUXSEG7EI32_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG7EI32_V_MF2_MF8 + 10U, // PseudoVSUXSEG7EI32_V_MF2_MF8_MASK + 10U, // PseudoVSUXSEG7EI64_V_M1_M1 + 10U, // PseudoVSUXSEG7EI64_V_M1_M1_MASK + 10U, // PseudoVSUXSEG7EI64_V_M1_MF2 + 10U, // PseudoVSUXSEG7EI64_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG7EI64_V_M1_MF4 + 10U, // PseudoVSUXSEG7EI64_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG7EI64_V_M1_MF8 + 10U, // PseudoVSUXSEG7EI64_V_M1_MF8_MASK + 10U, // PseudoVSUXSEG7EI64_V_M2_M1 + 10U, // PseudoVSUXSEG7EI64_V_M2_M1_MASK + 10U, // PseudoVSUXSEG7EI64_V_M2_MF2 + 10U, // PseudoVSUXSEG7EI64_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG7EI64_V_M2_MF4 + 10U, // PseudoVSUXSEG7EI64_V_M2_MF4_MASK + 10U, // PseudoVSUXSEG7EI64_V_M4_M1 + 10U, // PseudoVSUXSEG7EI64_V_M4_M1_MASK + 10U, // PseudoVSUXSEG7EI64_V_M4_MF2 + 10U, // PseudoVSUXSEG7EI64_V_M4_MF2_MASK + 10U, // PseudoVSUXSEG7EI64_V_M8_M1 + 10U, // PseudoVSUXSEG7EI64_V_M8_M1_MASK + 10U, // PseudoVSUXSEG7EI8_V_M1_M1 + 10U, // PseudoVSUXSEG7EI8_V_M1_M1_MASK + 10U, // PseudoVSUXSEG7EI8_V_MF2_M1 + 10U, // PseudoVSUXSEG7EI8_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG7EI8_V_MF2_MF2 + 10U, // PseudoVSUXSEG7EI8_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG7EI8_V_MF4_M1 + 10U, // PseudoVSUXSEG7EI8_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG7EI8_V_MF4_MF2 + 10U, // PseudoVSUXSEG7EI8_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG7EI8_V_MF4_MF4 + 10U, // PseudoVSUXSEG7EI8_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG7EI8_V_MF8_M1 + 10U, // PseudoVSUXSEG7EI8_V_MF8_M1_MASK + 10U, // PseudoVSUXSEG7EI8_V_MF8_MF2 + 10U, // PseudoVSUXSEG7EI8_V_MF8_MF2_MASK + 10U, // PseudoVSUXSEG7EI8_V_MF8_MF4 + 10U, // PseudoVSUXSEG7EI8_V_MF8_MF4_MASK + 10U, // PseudoVSUXSEG7EI8_V_MF8_MF8 + 10U, // PseudoVSUXSEG7EI8_V_MF8_MF8_MASK + 10U, // PseudoVSUXSEG8EI16_V_M1_M1 + 10U, // PseudoVSUXSEG8EI16_V_M1_M1_MASK + 10U, // PseudoVSUXSEG8EI16_V_M1_MF2 + 10U, // PseudoVSUXSEG8EI16_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG8EI16_V_M2_M1 + 10U, // PseudoVSUXSEG8EI16_V_M2_M1_MASK + 10U, // PseudoVSUXSEG8EI16_V_MF2_M1 + 10U, // PseudoVSUXSEG8EI16_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG8EI16_V_MF2_MF2 + 10U, // PseudoVSUXSEG8EI16_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG8EI16_V_MF2_MF4 + 10U, // PseudoVSUXSEG8EI16_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG8EI16_V_MF4_M1 + 10U, // PseudoVSUXSEG8EI16_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG8EI16_V_MF4_MF2 + 10U, // PseudoVSUXSEG8EI16_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG8EI16_V_MF4_MF4 + 10U, // PseudoVSUXSEG8EI16_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG8EI16_V_MF4_MF8 + 10U, // PseudoVSUXSEG8EI16_V_MF4_MF8_MASK + 10U, // PseudoVSUXSEG8EI32_V_M1_M1 + 10U, // PseudoVSUXSEG8EI32_V_M1_M1_MASK + 10U, // PseudoVSUXSEG8EI32_V_M1_MF2 + 10U, // PseudoVSUXSEG8EI32_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG8EI32_V_M1_MF4 + 10U, // PseudoVSUXSEG8EI32_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG8EI32_V_M2_M1 + 10U, // PseudoVSUXSEG8EI32_V_M2_M1_MASK + 10U, // PseudoVSUXSEG8EI32_V_M2_MF2 + 10U, // PseudoVSUXSEG8EI32_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG8EI32_V_M4_M1 + 10U, // PseudoVSUXSEG8EI32_V_M4_M1_MASK + 10U, // PseudoVSUXSEG8EI32_V_MF2_M1 + 10U, // PseudoVSUXSEG8EI32_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG8EI32_V_MF2_MF2 + 10U, // PseudoVSUXSEG8EI32_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG8EI32_V_MF2_MF4 + 10U, // PseudoVSUXSEG8EI32_V_MF2_MF4_MASK + 10U, // PseudoVSUXSEG8EI32_V_MF2_MF8 + 10U, // PseudoVSUXSEG8EI32_V_MF2_MF8_MASK + 10U, // PseudoVSUXSEG8EI64_V_M1_M1 + 10U, // PseudoVSUXSEG8EI64_V_M1_M1_MASK + 10U, // PseudoVSUXSEG8EI64_V_M1_MF2 + 10U, // PseudoVSUXSEG8EI64_V_M1_MF2_MASK + 10U, // PseudoVSUXSEG8EI64_V_M1_MF4 + 10U, // PseudoVSUXSEG8EI64_V_M1_MF4_MASK + 10U, // PseudoVSUXSEG8EI64_V_M1_MF8 + 10U, // PseudoVSUXSEG8EI64_V_M1_MF8_MASK + 10U, // PseudoVSUXSEG8EI64_V_M2_M1 + 10U, // PseudoVSUXSEG8EI64_V_M2_M1_MASK + 10U, // PseudoVSUXSEG8EI64_V_M2_MF2 + 10U, // PseudoVSUXSEG8EI64_V_M2_MF2_MASK + 10U, // PseudoVSUXSEG8EI64_V_M2_MF4 + 10U, // PseudoVSUXSEG8EI64_V_M2_MF4_MASK + 10U, // PseudoVSUXSEG8EI64_V_M4_M1 + 10U, // PseudoVSUXSEG8EI64_V_M4_M1_MASK + 10U, // PseudoVSUXSEG8EI64_V_M4_MF2 + 10U, // PseudoVSUXSEG8EI64_V_M4_MF2_MASK + 10U, // PseudoVSUXSEG8EI64_V_M8_M1 + 10U, // PseudoVSUXSEG8EI64_V_M8_M1_MASK + 10U, // PseudoVSUXSEG8EI8_V_M1_M1 + 10U, // PseudoVSUXSEG8EI8_V_M1_M1_MASK + 10U, // PseudoVSUXSEG8EI8_V_MF2_M1 + 10U, // PseudoVSUXSEG8EI8_V_MF2_M1_MASK + 10U, // PseudoVSUXSEG8EI8_V_MF2_MF2 + 10U, // PseudoVSUXSEG8EI8_V_MF2_MF2_MASK + 10U, // PseudoVSUXSEG8EI8_V_MF4_M1 + 10U, // PseudoVSUXSEG8EI8_V_MF4_M1_MASK + 10U, // PseudoVSUXSEG8EI8_V_MF4_MF2 + 10U, // PseudoVSUXSEG8EI8_V_MF4_MF2_MASK + 10U, // PseudoVSUXSEG8EI8_V_MF4_MF4 + 10U, // PseudoVSUXSEG8EI8_V_MF4_MF4_MASK + 10U, // PseudoVSUXSEG8EI8_V_MF8_M1 + 10U, // PseudoVSUXSEG8EI8_V_MF8_M1_MASK + 10U, // PseudoVSUXSEG8EI8_V_MF8_MF2 + 10U, // PseudoVSUXSEG8EI8_V_MF8_MF2_MASK + 10U, // PseudoVSUXSEG8EI8_V_MF8_MF4 + 10U, // PseudoVSUXSEG8EI8_V_MF8_MF4_MASK + 10U, // PseudoVSUXSEG8EI8_V_MF8_MF8 + 10U, // PseudoVSUXSEG8EI8_V_MF8_MF8_MASK + 10U, // PseudoVWADDU_VV_M1 + 10U, // PseudoVWADDU_VV_M1_MASK + 10U, // PseudoVWADDU_VV_M2 + 10U, // PseudoVWADDU_VV_M2_MASK + 10U, // PseudoVWADDU_VV_M4 + 10U, // PseudoVWADDU_VV_M4_MASK + 10U, // PseudoVWADDU_VV_MF2 + 10U, // PseudoVWADDU_VV_MF2_MASK + 10U, // PseudoVWADDU_VV_MF4 + 10U, // PseudoVWADDU_VV_MF4_MASK + 10U, // PseudoVWADDU_VV_MF8 + 10U, // PseudoVWADDU_VV_MF8_MASK + 10U, // PseudoVWADDU_VX_M1 + 10U, // PseudoVWADDU_VX_M1_MASK + 10U, // PseudoVWADDU_VX_M2 + 10U, // PseudoVWADDU_VX_M2_MASK + 10U, // PseudoVWADDU_VX_M4 + 10U, // PseudoVWADDU_VX_M4_MASK + 10U, // PseudoVWADDU_VX_MF2 + 10U, // PseudoVWADDU_VX_MF2_MASK + 10U, // PseudoVWADDU_VX_MF4 + 10U, // PseudoVWADDU_VX_MF4_MASK + 10U, // PseudoVWADDU_VX_MF8 + 10U, // PseudoVWADDU_VX_MF8_MASK + 10U, // PseudoVWADDU_WV_M1 + 10U, // PseudoVWADDU_WV_M1_MASK + 10U, // PseudoVWADDU_WV_M1_MASK_TIED + 10U, // PseudoVWADDU_WV_M1_TIED + 10U, // PseudoVWADDU_WV_M2 + 10U, // PseudoVWADDU_WV_M2_MASK + 10U, // PseudoVWADDU_WV_M2_MASK_TIED + 10U, // PseudoVWADDU_WV_M2_TIED + 10U, // PseudoVWADDU_WV_M4 + 10U, // PseudoVWADDU_WV_M4_MASK + 10U, // PseudoVWADDU_WV_M4_MASK_TIED + 10U, // PseudoVWADDU_WV_M4_TIED + 10U, // PseudoVWADDU_WV_MF2 + 10U, // PseudoVWADDU_WV_MF2_MASK + 10U, // PseudoVWADDU_WV_MF2_MASK_TIED + 10U, // PseudoVWADDU_WV_MF2_TIED + 10U, // PseudoVWADDU_WV_MF4 + 10U, // PseudoVWADDU_WV_MF4_MASK + 10U, // PseudoVWADDU_WV_MF4_MASK_TIED + 10U, // PseudoVWADDU_WV_MF4_TIED + 10U, // PseudoVWADDU_WV_MF8 + 10U, // PseudoVWADDU_WV_MF8_MASK + 10U, // PseudoVWADDU_WV_MF8_MASK_TIED + 10U, // PseudoVWADDU_WV_MF8_TIED + 10U, // PseudoVWADDU_WX_M1 + 10U, // PseudoVWADDU_WX_M1_MASK + 10U, // PseudoVWADDU_WX_M2 + 10U, // PseudoVWADDU_WX_M2_MASK + 10U, // PseudoVWADDU_WX_M4 + 10U, // PseudoVWADDU_WX_M4_MASK + 10U, // PseudoVWADDU_WX_MF2 + 10U, // PseudoVWADDU_WX_MF2_MASK + 10U, // PseudoVWADDU_WX_MF4 + 10U, // PseudoVWADDU_WX_MF4_MASK + 10U, // PseudoVWADDU_WX_MF8 + 10U, // PseudoVWADDU_WX_MF8_MASK + 10U, // PseudoVWADD_VV_M1 + 10U, // PseudoVWADD_VV_M1_MASK + 10U, // PseudoVWADD_VV_M2 + 10U, // PseudoVWADD_VV_M2_MASK + 10U, // PseudoVWADD_VV_M4 + 10U, // PseudoVWADD_VV_M4_MASK + 10U, // PseudoVWADD_VV_MF2 + 10U, // PseudoVWADD_VV_MF2_MASK + 10U, // PseudoVWADD_VV_MF4 + 10U, // PseudoVWADD_VV_MF4_MASK + 10U, // PseudoVWADD_VV_MF8 + 10U, // PseudoVWADD_VV_MF8_MASK + 10U, // PseudoVWADD_VX_M1 + 10U, // PseudoVWADD_VX_M1_MASK + 10U, // PseudoVWADD_VX_M2 + 10U, // PseudoVWADD_VX_M2_MASK + 10U, // PseudoVWADD_VX_M4 + 10U, // PseudoVWADD_VX_M4_MASK + 10U, // PseudoVWADD_VX_MF2 + 10U, // PseudoVWADD_VX_MF2_MASK + 10U, // PseudoVWADD_VX_MF4 + 10U, // PseudoVWADD_VX_MF4_MASK + 10U, // PseudoVWADD_VX_MF8 + 10U, // PseudoVWADD_VX_MF8_MASK + 10U, // PseudoVWADD_WV_M1 + 10U, // PseudoVWADD_WV_M1_MASK + 10U, // PseudoVWADD_WV_M1_MASK_TIED + 10U, // PseudoVWADD_WV_M1_TIED + 10U, // PseudoVWADD_WV_M2 + 10U, // PseudoVWADD_WV_M2_MASK + 10U, // PseudoVWADD_WV_M2_MASK_TIED + 10U, // PseudoVWADD_WV_M2_TIED + 10U, // PseudoVWADD_WV_M4 + 10U, // PseudoVWADD_WV_M4_MASK + 10U, // PseudoVWADD_WV_M4_MASK_TIED + 10U, // PseudoVWADD_WV_M4_TIED + 10U, // PseudoVWADD_WV_MF2 + 10U, // PseudoVWADD_WV_MF2_MASK + 10U, // PseudoVWADD_WV_MF2_MASK_TIED + 10U, // PseudoVWADD_WV_MF2_TIED + 10U, // PseudoVWADD_WV_MF4 + 10U, // PseudoVWADD_WV_MF4_MASK + 10U, // PseudoVWADD_WV_MF4_MASK_TIED + 10U, // PseudoVWADD_WV_MF4_TIED + 10U, // PseudoVWADD_WV_MF8 + 10U, // PseudoVWADD_WV_MF8_MASK + 10U, // PseudoVWADD_WV_MF8_MASK_TIED + 10U, // PseudoVWADD_WV_MF8_TIED + 10U, // PseudoVWADD_WX_M1 + 10U, // PseudoVWADD_WX_M1_MASK + 10U, // PseudoVWADD_WX_M2 + 10U, // PseudoVWADD_WX_M2_MASK + 10U, // PseudoVWADD_WX_M4 + 10U, // PseudoVWADD_WX_M4_MASK + 10U, // PseudoVWADD_WX_MF2 + 10U, // PseudoVWADD_WX_MF2_MASK + 10U, // PseudoVWADD_WX_MF4 + 10U, // PseudoVWADD_WX_MF4_MASK + 10U, // PseudoVWADD_WX_MF8 + 10U, // PseudoVWADD_WX_MF8_MASK + 10U, // PseudoVWMACCSU_VV_M1 + 10U, // PseudoVWMACCSU_VV_M1_MASK + 10U, // PseudoVWMACCSU_VV_M2 + 10U, // PseudoVWMACCSU_VV_M2_MASK + 10U, // PseudoVWMACCSU_VV_M4 + 10U, // PseudoVWMACCSU_VV_M4_MASK + 10U, // PseudoVWMACCSU_VV_MF2 + 10U, // PseudoVWMACCSU_VV_MF2_MASK + 10U, // PseudoVWMACCSU_VV_MF4 + 10U, // PseudoVWMACCSU_VV_MF4_MASK + 10U, // PseudoVWMACCSU_VV_MF8 + 10U, // PseudoVWMACCSU_VV_MF8_MASK + 10U, // PseudoVWMACCSU_VX_M1 + 10U, // PseudoVWMACCSU_VX_M1_MASK + 10U, // PseudoVWMACCSU_VX_M2 + 10U, // PseudoVWMACCSU_VX_M2_MASK + 10U, // PseudoVWMACCSU_VX_M4 + 10U, // PseudoVWMACCSU_VX_M4_MASK + 10U, // PseudoVWMACCSU_VX_MF2 + 10U, // PseudoVWMACCSU_VX_MF2_MASK + 10U, // PseudoVWMACCSU_VX_MF4 + 10U, // PseudoVWMACCSU_VX_MF4_MASK + 10U, // PseudoVWMACCSU_VX_MF8 + 10U, // PseudoVWMACCSU_VX_MF8_MASK + 10U, // PseudoVWMACCUS_VX_M1 + 10U, // PseudoVWMACCUS_VX_M1_MASK + 10U, // PseudoVWMACCUS_VX_M2 + 10U, // PseudoVWMACCUS_VX_M2_MASK + 10U, // PseudoVWMACCUS_VX_M4 + 10U, // PseudoVWMACCUS_VX_M4_MASK + 10U, // PseudoVWMACCUS_VX_MF2 + 10U, // PseudoVWMACCUS_VX_MF2_MASK + 10U, // PseudoVWMACCUS_VX_MF4 + 10U, // PseudoVWMACCUS_VX_MF4_MASK + 10U, // PseudoVWMACCUS_VX_MF8 + 10U, // PseudoVWMACCUS_VX_MF8_MASK + 10U, // PseudoVWMACCU_VV_M1 + 10U, // PseudoVWMACCU_VV_M1_MASK + 10U, // PseudoVWMACCU_VV_M2 + 10U, // PseudoVWMACCU_VV_M2_MASK + 10U, // PseudoVWMACCU_VV_M4 + 10U, // PseudoVWMACCU_VV_M4_MASK + 10U, // PseudoVWMACCU_VV_MF2 + 10U, // PseudoVWMACCU_VV_MF2_MASK + 10U, // PseudoVWMACCU_VV_MF4 + 10U, // PseudoVWMACCU_VV_MF4_MASK + 10U, // PseudoVWMACCU_VV_MF8 + 10U, // PseudoVWMACCU_VV_MF8_MASK + 10U, // PseudoVWMACCU_VX_M1 + 10U, // PseudoVWMACCU_VX_M1_MASK + 10U, // PseudoVWMACCU_VX_M2 + 10U, // PseudoVWMACCU_VX_M2_MASK + 10U, // PseudoVWMACCU_VX_M4 + 10U, // PseudoVWMACCU_VX_M4_MASK + 10U, // PseudoVWMACCU_VX_MF2 + 10U, // PseudoVWMACCU_VX_MF2_MASK + 10U, // PseudoVWMACCU_VX_MF4 + 10U, // PseudoVWMACCU_VX_MF4_MASK + 10U, // PseudoVWMACCU_VX_MF8 + 10U, // PseudoVWMACCU_VX_MF8_MASK + 10U, // PseudoVWMACC_VV_M1 + 10U, // PseudoVWMACC_VV_M1_MASK + 10U, // PseudoVWMACC_VV_M2 + 10U, // PseudoVWMACC_VV_M2_MASK + 10U, // PseudoVWMACC_VV_M4 + 10U, // PseudoVWMACC_VV_M4_MASK + 10U, // PseudoVWMACC_VV_MF2 + 10U, // PseudoVWMACC_VV_MF2_MASK + 10U, // PseudoVWMACC_VV_MF4 + 10U, // PseudoVWMACC_VV_MF4_MASK + 10U, // PseudoVWMACC_VV_MF8 + 10U, // PseudoVWMACC_VV_MF8_MASK + 10U, // PseudoVWMACC_VX_M1 + 10U, // PseudoVWMACC_VX_M1_MASK + 10U, // PseudoVWMACC_VX_M2 + 10U, // PseudoVWMACC_VX_M2_MASK + 10U, // PseudoVWMACC_VX_M4 + 10U, // PseudoVWMACC_VX_M4_MASK + 10U, // PseudoVWMACC_VX_MF2 + 10U, // PseudoVWMACC_VX_MF2_MASK + 10U, // PseudoVWMACC_VX_MF4 + 10U, // PseudoVWMACC_VX_MF4_MASK + 10U, // PseudoVWMACC_VX_MF8 + 10U, // PseudoVWMACC_VX_MF8_MASK + 10U, // PseudoVWMULSU_VV_M1 + 10U, // PseudoVWMULSU_VV_M1_MASK + 10U, // PseudoVWMULSU_VV_M2 + 10U, // PseudoVWMULSU_VV_M2_MASK + 10U, // PseudoVWMULSU_VV_M4 + 10U, // PseudoVWMULSU_VV_M4_MASK + 10U, // PseudoVWMULSU_VV_MF2 + 10U, // PseudoVWMULSU_VV_MF2_MASK + 10U, // PseudoVWMULSU_VV_MF4 + 10U, // PseudoVWMULSU_VV_MF4_MASK + 10U, // PseudoVWMULSU_VV_MF8 + 10U, // PseudoVWMULSU_VV_MF8_MASK + 10U, // PseudoVWMULSU_VX_M1 + 10U, // PseudoVWMULSU_VX_M1_MASK + 10U, // PseudoVWMULSU_VX_M2 + 10U, // PseudoVWMULSU_VX_M2_MASK + 10U, // PseudoVWMULSU_VX_M4 + 10U, // PseudoVWMULSU_VX_M4_MASK + 10U, // PseudoVWMULSU_VX_MF2 + 10U, // PseudoVWMULSU_VX_MF2_MASK + 10U, // PseudoVWMULSU_VX_MF4 + 10U, // PseudoVWMULSU_VX_MF4_MASK + 10U, // PseudoVWMULSU_VX_MF8 + 10U, // PseudoVWMULSU_VX_MF8_MASK + 10U, // PseudoVWMULU_VV_M1 + 10U, // PseudoVWMULU_VV_M1_MASK + 10U, // PseudoVWMULU_VV_M2 + 10U, // PseudoVWMULU_VV_M2_MASK + 10U, // PseudoVWMULU_VV_M4 + 10U, // PseudoVWMULU_VV_M4_MASK + 10U, // PseudoVWMULU_VV_MF2 + 10U, // PseudoVWMULU_VV_MF2_MASK + 10U, // PseudoVWMULU_VV_MF4 + 10U, // PseudoVWMULU_VV_MF4_MASK + 10U, // PseudoVWMULU_VV_MF8 + 10U, // PseudoVWMULU_VV_MF8_MASK + 10U, // PseudoVWMULU_VX_M1 + 10U, // PseudoVWMULU_VX_M1_MASK + 10U, // PseudoVWMULU_VX_M2 + 10U, // PseudoVWMULU_VX_M2_MASK + 10U, // PseudoVWMULU_VX_M4 + 10U, // PseudoVWMULU_VX_M4_MASK + 10U, // PseudoVWMULU_VX_MF2 + 10U, // PseudoVWMULU_VX_MF2_MASK + 10U, // PseudoVWMULU_VX_MF4 + 10U, // PseudoVWMULU_VX_MF4_MASK + 10U, // PseudoVWMULU_VX_MF8 + 10U, // PseudoVWMULU_VX_MF8_MASK + 10U, // PseudoVWMUL_VV_M1 + 10U, // PseudoVWMUL_VV_M1_MASK + 10U, // PseudoVWMUL_VV_M2 + 10U, // PseudoVWMUL_VV_M2_MASK + 10U, // PseudoVWMUL_VV_M4 + 10U, // PseudoVWMUL_VV_M4_MASK + 10U, // PseudoVWMUL_VV_MF2 + 10U, // PseudoVWMUL_VV_MF2_MASK + 10U, // PseudoVWMUL_VV_MF4 + 10U, // PseudoVWMUL_VV_MF4_MASK + 10U, // PseudoVWMUL_VV_MF8 + 10U, // PseudoVWMUL_VV_MF8_MASK + 10U, // PseudoVWMUL_VX_M1 + 10U, // PseudoVWMUL_VX_M1_MASK + 10U, // PseudoVWMUL_VX_M2 + 10U, // PseudoVWMUL_VX_M2_MASK + 10U, // PseudoVWMUL_VX_M4 + 10U, // PseudoVWMUL_VX_M4_MASK + 10U, // PseudoVWMUL_VX_MF2 + 10U, // PseudoVWMUL_VX_MF2_MASK + 10U, // PseudoVWMUL_VX_MF4 + 10U, // PseudoVWMUL_VX_MF4_MASK + 10U, // PseudoVWMUL_VX_MF8 + 10U, // PseudoVWMUL_VX_MF8_MASK + 10U, // PseudoVWREDSUMU_VS_M1 + 10U, // PseudoVWREDSUMU_VS_M1_MASK + 10U, // PseudoVWREDSUMU_VS_M2 + 10U, // PseudoVWREDSUMU_VS_M2_MASK + 10U, // PseudoVWREDSUMU_VS_M4 + 10U, // PseudoVWREDSUMU_VS_M4_MASK + 10U, // PseudoVWREDSUMU_VS_M8 + 10U, // PseudoVWREDSUMU_VS_M8_MASK + 10U, // PseudoVWREDSUMU_VS_MF2 + 10U, // PseudoVWREDSUMU_VS_MF2_MASK + 10U, // PseudoVWREDSUMU_VS_MF4 + 10U, // PseudoVWREDSUMU_VS_MF4_MASK + 10U, // PseudoVWREDSUMU_VS_MF8 + 10U, // PseudoVWREDSUMU_VS_MF8_MASK + 10U, // PseudoVWREDSUM_VS_M1 + 10U, // PseudoVWREDSUM_VS_M1_MASK + 10U, // PseudoVWREDSUM_VS_M2 + 10U, // PseudoVWREDSUM_VS_M2_MASK + 10U, // PseudoVWREDSUM_VS_M4 + 10U, // PseudoVWREDSUM_VS_M4_MASK + 10U, // PseudoVWREDSUM_VS_M8 + 10U, // PseudoVWREDSUM_VS_M8_MASK + 10U, // PseudoVWREDSUM_VS_MF2 + 10U, // PseudoVWREDSUM_VS_MF2_MASK + 10U, // PseudoVWREDSUM_VS_MF4 + 10U, // PseudoVWREDSUM_VS_MF4_MASK + 10U, // PseudoVWREDSUM_VS_MF8 + 10U, // PseudoVWREDSUM_VS_MF8_MASK + 10U, // PseudoVWSUBU_VV_M1 + 10U, // PseudoVWSUBU_VV_M1_MASK + 10U, // PseudoVWSUBU_VV_M2 + 10U, // PseudoVWSUBU_VV_M2_MASK + 10U, // PseudoVWSUBU_VV_M4 + 10U, // PseudoVWSUBU_VV_M4_MASK + 10U, // PseudoVWSUBU_VV_MF2 + 10U, // PseudoVWSUBU_VV_MF2_MASK + 10U, // PseudoVWSUBU_VV_MF4 + 10U, // PseudoVWSUBU_VV_MF4_MASK + 10U, // PseudoVWSUBU_VV_MF8 + 10U, // PseudoVWSUBU_VV_MF8_MASK + 10U, // PseudoVWSUBU_VX_M1 + 10U, // PseudoVWSUBU_VX_M1_MASK + 10U, // PseudoVWSUBU_VX_M2 + 10U, // PseudoVWSUBU_VX_M2_MASK + 10U, // PseudoVWSUBU_VX_M4 + 10U, // PseudoVWSUBU_VX_M4_MASK + 10U, // PseudoVWSUBU_VX_MF2 + 10U, // PseudoVWSUBU_VX_MF2_MASK + 10U, // PseudoVWSUBU_VX_MF4 + 10U, // PseudoVWSUBU_VX_MF4_MASK + 10U, // PseudoVWSUBU_VX_MF8 + 10U, // PseudoVWSUBU_VX_MF8_MASK + 10U, // PseudoVWSUBU_WV_M1 + 10U, // PseudoVWSUBU_WV_M1_MASK + 10U, // PseudoVWSUBU_WV_M1_MASK_TIED + 10U, // PseudoVWSUBU_WV_M1_TIED + 10U, // PseudoVWSUBU_WV_M2 + 10U, // PseudoVWSUBU_WV_M2_MASK + 10U, // PseudoVWSUBU_WV_M2_MASK_TIED + 10U, // PseudoVWSUBU_WV_M2_TIED + 10U, // PseudoVWSUBU_WV_M4 + 10U, // PseudoVWSUBU_WV_M4_MASK + 10U, // PseudoVWSUBU_WV_M4_MASK_TIED + 10U, // PseudoVWSUBU_WV_M4_TIED + 10U, // PseudoVWSUBU_WV_MF2 + 10U, // PseudoVWSUBU_WV_MF2_MASK + 10U, // PseudoVWSUBU_WV_MF2_MASK_TIED + 10U, // PseudoVWSUBU_WV_MF2_TIED + 10U, // PseudoVWSUBU_WV_MF4 + 10U, // PseudoVWSUBU_WV_MF4_MASK + 10U, // PseudoVWSUBU_WV_MF4_MASK_TIED + 10U, // PseudoVWSUBU_WV_MF4_TIED + 10U, // PseudoVWSUBU_WV_MF8 + 10U, // PseudoVWSUBU_WV_MF8_MASK + 10U, // PseudoVWSUBU_WV_MF8_MASK_TIED + 10U, // PseudoVWSUBU_WV_MF8_TIED + 10U, // PseudoVWSUBU_WX_M1 + 10U, // PseudoVWSUBU_WX_M1_MASK + 10U, // PseudoVWSUBU_WX_M2 + 10U, // PseudoVWSUBU_WX_M2_MASK + 10U, // PseudoVWSUBU_WX_M4 + 10U, // PseudoVWSUBU_WX_M4_MASK + 10U, // PseudoVWSUBU_WX_MF2 + 10U, // PseudoVWSUBU_WX_MF2_MASK + 10U, // PseudoVWSUBU_WX_MF4 + 10U, // PseudoVWSUBU_WX_MF4_MASK + 10U, // PseudoVWSUBU_WX_MF8 + 10U, // PseudoVWSUBU_WX_MF8_MASK + 10U, // PseudoVWSUB_VV_M1 + 10U, // PseudoVWSUB_VV_M1_MASK + 10U, // PseudoVWSUB_VV_M2 + 10U, // PseudoVWSUB_VV_M2_MASK + 10U, // PseudoVWSUB_VV_M4 + 10U, // PseudoVWSUB_VV_M4_MASK + 10U, // PseudoVWSUB_VV_MF2 + 10U, // PseudoVWSUB_VV_MF2_MASK + 10U, // PseudoVWSUB_VV_MF4 + 10U, // PseudoVWSUB_VV_MF4_MASK + 10U, // PseudoVWSUB_VV_MF8 + 10U, // PseudoVWSUB_VV_MF8_MASK + 10U, // PseudoVWSUB_VX_M1 + 10U, // PseudoVWSUB_VX_M1_MASK + 10U, // PseudoVWSUB_VX_M2 + 10U, // PseudoVWSUB_VX_M2_MASK + 10U, // PseudoVWSUB_VX_M4 + 10U, // PseudoVWSUB_VX_M4_MASK + 10U, // PseudoVWSUB_VX_MF2 + 10U, // PseudoVWSUB_VX_MF2_MASK + 10U, // PseudoVWSUB_VX_MF4 + 10U, // PseudoVWSUB_VX_MF4_MASK + 10U, // PseudoVWSUB_VX_MF8 + 10U, // PseudoVWSUB_VX_MF8_MASK + 10U, // PseudoVWSUB_WV_M1 + 10U, // PseudoVWSUB_WV_M1_MASK + 10U, // PseudoVWSUB_WV_M1_MASK_TIED + 10U, // PseudoVWSUB_WV_M1_TIED + 10U, // PseudoVWSUB_WV_M2 + 10U, // PseudoVWSUB_WV_M2_MASK + 10U, // PseudoVWSUB_WV_M2_MASK_TIED + 10U, // PseudoVWSUB_WV_M2_TIED + 10U, // PseudoVWSUB_WV_M4 + 10U, // PseudoVWSUB_WV_M4_MASK + 10U, // PseudoVWSUB_WV_M4_MASK_TIED + 10U, // PseudoVWSUB_WV_M4_TIED + 10U, // PseudoVWSUB_WV_MF2 + 10U, // PseudoVWSUB_WV_MF2_MASK + 10U, // PseudoVWSUB_WV_MF2_MASK_TIED + 10U, // PseudoVWSUB_WV_MF2_TIED + 10U, // PseudoVWSUB_WV_MF4 + 10U, // PseudoVWSUB_WV_MF4_MASK + 10U, // PseudoVWSUB_WV_MF4_MASK_TIED + 10U, // PseudoVWSUB_WV_MF4_TIED + 10U, // PseudoVWSUB_WV_MF8 + 10U, // PseudoVWSUB_WV_MF8_MASK + 10U, // PseudoVWSUB_WV_MF8_MASK_TIED + 10U, // PseudoVWSUB_WV_MF8_TIED + 10U, // PseudoVWSUB_WX_M1 + 10U, // PseudoVWSUB_WX_M1_MASK + 10U, // PseudoVWSUB_WX_M2 + 10U, // PseudoVWSUB_WX_M2_MASK + 10U, // PseudoVWSUB_WX_M4 + 10U, // PseudoVWSUB_WX_M4_MASK + 10U, // PseudoVWSUB_WX_MF2 + 10U, // PseudoVWSUB_WX_MF2_MASK + 10U, // PseudoVWSUB_WX_MF4 + 10U, // PseudoVWSUB_WX_MF4_MASK + 10U, // PseudoVWSUB_WX_MF8 + 10U, // PseudoVWSUB_WX_MF8_MASK + 10U, // PseudoVXOR_VI_M1 + 10U, // PseudoVXOR_VI_M1_MASK + 10U, // PseudoVXOR_VI_M2 + 10U, // PseudoVXOR_VI_M2_MASK + 10U, // PseudoVXOR_VI_M4 + 10U, // PseudoVXOR_VI_M4_MASK + 10U, // PseudoVXOR_VI_M8 + 10U, // PseudoVXOR_VI_M8_MASK + 10U, // PseudoVXOR_VI_MF2 + 10U, // PseudoVXOR_VI_MF2_MASK + 10U, // PseudoVXOR_VI_MF4 + 10U, // PseudoVXOR_VI_MF4_MASK + 10U, // PseudoVXOR_VI_MF8 + 10U, // PseudoVXOR_VI_MF8_MASK + 10U, // PseudoVXOR_VV_M1 + 10U, // PseudoVXOR_VV_M1_MASK + 10U, // PseudoVXOR_VV_M2 + 10U, // PseudoVXOR_VV_M2_MASK + 10U, // PseudoVXOR_VV_M4 + 10U, // PseudoVXOR_VV_M4_MASK + 10U, // PseudoVXOR_VV_M8 + 10U, // PseudoVXOR_VV_M8_MASK + 10U, // PseudoVXOR_VV_MF2 + 10U, // PseudoVXOR_VV_MF2_MASK + 10U, // PseudoVXOR_VV_MF4 + 10U, // PseudoVXOR_VV_MF4_MASK + 10U, // PseudoVXOR_VV_MF8 + 10U, // PseudoVXOR_VV_MF8_MASK + 10U, // PseudoVXOR_VX_M1 + 10U, // PseudoVXOR_VX_M1_MASK + 10U, // PseudoVXOR_VX_M2 + 10U, // PseudoVXOR_VX_M2_MASK + 10U, // PseudoVXOR_VX_M4 + 10U, // PseudoVXOR_VX_M4_MASK + 10U, // PseudoVXOR_VX_M8 + 10U, // PseudoVXOR_VX_M8_MASK + 10U, // PseudoVXOR_VX_MF2 + 10U, // PseudoVXOR_VX_MF2_MASK + 10U, // PseudoVXOR_VX_MF4 + 10U, // PseudoVXOR_VX_MF4_MASK + 10U, // PseudoVXOR_VX_MF8 + 10U, // PseudoVXOR_VX_MF8_MASK + 10U, // PseudoVZEXT_VF2_M1 + 10U, // PseudoVZEXT_VF2_M1_MASK + 10U, // PseudoVZEXT_VF2_M2 + 10U, // PseudoVZEXT_VF2_M2_MASK + 10U, // PseudoVZEXT_VF2_M4 + 10U, // PseudoVZEXT_VF2_M4_MASK + 10U, // PseudoVZEXT_VF2_M8 + 10U, // PseudoVZEXT_VF2_M8_MASK + 10U, // PseudoVZEXT_VF2_MF2 + 10U, // PseudoVZEXT_VF2_MF2_MASK + 10U, // PseudoVZEXT_VF2_MF4 + 10U, // PseudoVZEXT_VF2_MF4_MASK + 10U, // PseudoVZEXT_VF4_M1 + 10U, // PseudoVZEXT_VF4_M1_MASK + 10U, // PseudoVZEXT_VF4_M2 + 10U, // PseudoVZEXT_VF4_M2_MASK + 10U, // PseudoVZEXT_VF4_M4 + 10U, // PseudoVZEXT_VF4_M4_MASK + 10U, // PseudoVZEXT_VF4_M8 + 10U, // PseudoVZEXT_VF4_M8_MASK + 10U, // PseudoVZEXT_VF4_MF2 + 10U, // PseudoVZEXT_VF4_MF2_MASK + 10U, // PseudoVZEXT_VF8_M1 + 10U, // PseudoVZEXT_VF8_M1_MASK + 10U, // PseudoVZEXT_VF8_M2 + 10U, // PseudoVZEXT_VF8_M2_MASK + 10U, // PseudoVZEXT_VF8_M4 + 10U, // PseudoVZEXT_VF8_M4_MASK + 10U, // PseudoVZEXT_VF8_M8 + 10U, // PseudoVZEXT_VF8_M8_MASK + 8406268U, // PseudoZEXT_H + 8415413U, // PseudoZEXT_W + 10U, // ReadCycleWide + 10U, // ReadFRM + 10U, // Select_FPR16_Using_CC_GPR + 10U, // Select_FPR32_Using_CC_GPR + 10U, // Select_FPR64_Using_CC_GPR + 10U, // Select_GPR_Using_CC_GPR + 10U, // SplitF64Pseudo + 10U, // WriteFRM + 10U, // WriteFRMImm + 536887850U, // ADD + 536888715U, // ADDI + 536897841U, // ADDIW + 536898023U, // ADDUW + 536897818U, // ADDW + 202391834U, // AMOADD_D + 202394629U, // AMOADD_D_AQ + 202393807U, // AMOADD_D_AQ_RL + 202393531U, // AMOADD_D_RL + 202401780U, // AMOADD_W + 202394766U, // AMOADD_W_AQ + 202393966U, // AMOADD_W_AQ_RL + 202393668U, // AMOADD_W_RL + 202391844U, // AMOAND_D + 202394642U, // AMOAND_D_AQ + 202393822U, // AMOAND_D_AQ_RL + 202393544U, // AMOAND_D_RL + 202401790U, // AMOAND_W + 202394779U, // AMOAND_W_AQ + 202393981U, // AMOAND_W_AQ_RL + 202393681U, // AMOAND_W_RL + 202392038U, // AMOMAXU_D + 202394730U, // AMOMAXU_D_AQ + 202393924U, // AMOMAXU_D_AQ_RL + 202393632U, // AMOMAXU_D_RL + 202402007U, // AMOMAXU_W + 202394867U, // AMOMAXU_W_AQ + 202394083U, // AMOMAXU_W_AQ_RL + 202393769U, // AMOMAXU_W_RL + 202392084U, // AMOMAX_D + 202394744U, // AMOMAX_D_AQ + 202393940U, // AMOMAX_D_AQ_RL + 202393646U, // AMOMAX_D_RL + 202402041U, // AMOMAX_W + 202394881U, // AMOMAX_W_AQ + 202394099U, // AMOMAX_W_AQ_RL + 202393783U, // AMOMAX_W_RL + 202392016U, // AMOMINU_D + 202394716U, // AMOMINU_D_AQ + 202393908U, // AMOMINU_D_AQ_RL + 202393618U, // AMOMINU_D_RL + 202401981U, // AMOMINU_W + 202394853U, // AMOMINU_W_AQ + 202394067U, // AMOMINU_W_AQ_RL + 202393755U, // AMOMINU_W_RL + 202391906U, // AMOMIN_D + 202394655U, // AMOMIN_D_AQ + 202393837U, // AMOMIN_D_AQ_RL + 202393557U, // AMOMIN_D_RL + 202401917U, // AMOMIN_W + 202394792U, // AMOMIN_W_AQ + 202393996U, // AMOMIN_W_AQ_RL + 202393694U, // AMOMIN_W_RL + 202391950U, // AMOOR_D + 202394691U, // AMOOR_D_AQ + 202393879U, // AMOOR_D_AQ_RL + 202393593U, // AMOOR_D_RL + 202401944U, // AMOOR_W + 202394828U, // AMOOR_W_AQ + 202394038U, // AMOOR_W_AQ_RL + 202393730U, // AMOOR_W_RL + 202391926U, // AMOSWAP_D + 202394668U, // AMOSWAP_D_AQ + 202393852U, // AMOSWAP_D_AQ_RL + 202393570U, // AMOSWAP_D_RL + 202401927U, // AMOSWAP_W + 202394805U, // AMOSWAP_W_AQ + 202394011U, // AMOSWAP_W_AQ_RL + 202393707U, // AMOSWAP_W_RL + 202391959U, // AMOXOR_D + 202394703U, // AMOXOR_D_AQ + 202393893U, // AMOXOR_D_AQ_RL + 202393605U, // AMOXOR_D_RL + 202401953U, // AMOXOR_W + 202394840U, // AMOXOR_W_AQ + 202394052U, // AMOXOR_W_AQ_RL + 202393742U, // AMOXOR_W_RL + 536887905U, // AND + 536888723U, // ANDI + 536890202U, // ANDN + 8405175U, // AUIPC + 536890657U, // BCLR + 536888784U, // BCLRI + 536890960U, // BCOMPRESS + 536897994U, // BCOMPRESSW + 536890971U, // BDECOMPRESS + 536898006U, // BDECOMPRESSW + 268455182U, // BEQ + 536891232U, // BEXT + 536888830U, // BEXTI + 536890241U, // BFP + 536897949U, // BFPW + 268452474U, // BGE + 268455787U, // BGEU + 536896492U, // BINV + 536889119U, // BINVI + 268455766U, // BLT + 268455867U, // BLTU + 8407942U, // BMATFLIP + 536890688U, // BMATOR + 536890703U, // BMATXOR + 268452490U, // BNE + 536891216U, // BSET + 536888817U, // BSETI + 536889868U, // CLMUL + 536888659U, // CLMULH + 536890663U, // CLMULR + 8416628U, // CLZ + 8415793U, // CLZW + 336620143U, // CMIX + 336618482U, // CMOV + 8407974U, // CPOP + 8415651U, // CPOPW + 8405117U, // CRC32B + 8405126U, // CRC32CB + 8405231U, // CRC32CD + 8406109U, // CRC32CH + 8415194U, // CRC32CW + 8405195U, // CRC32D + 8406073U, // CRC32H + 8415185U, // CRC32W + 3162308U, // CSRRC + 3163521U, // CSRRCI + 3165769U, // CSRRS + 3163625U, // CSRRSI + 3172784U, // CSRRW + 3163985U, // CSRRWI + 8416641U, // CTZ + 8415799U, // CTZW + 9470504U, // C_ADD + 9471369U, // C_ADDI + 9472940U, // C_ADDI16SP + 536890213U, // C_ADDI4SPN + 9480495U, // C_ADDIW + 9471369U, // C_ADDI_HINT_IMM_ZERO + 9471369U, // C_ADDI_HINT_X0 + 9471369U, // C_ADDI_NOP + 9480472U, // C_ADDW + 9470504U, // C_ADD_HINT + 9470559U, // C_AND + 9471377U, // C_ANDI + 4222329U, // C_BEQZ + 4222316U, // C_BNEZ + 1886U, // C_EBREAK + 17842776U, // C_FLD + 17845184U, // C_FLDSP + 17852777U, // C_FLW + 17845218U, // C_FLWSP + 17842796U, // C_FSD + 17845201U, // C_FSDSP + 17852867U, // C_FSW + 17845235U, // C_FSWSP + 51033U, // C_J + 51084U, // C_JAL + 150809U, // C_JALR + 150803U, // C_JR + 17842770U, // C_LD + 17845176U, // C_LDSP + 8406430U, // C_LI + 8406430U, // C_LI_HINT + 8406533U, // C_LUI + 8406533U, // C_LUI_HINT + 17852771U, // C_LW + 17845210U, // C_LWSP + 8414182U, // C_MV + 8414182U, // C_MV_HINT + 2975U, // C_NOP + 150431U, // C_NOP_HINT + 9473327U, // C_OR + 17842790U, // C_SD + 17845193U, // C_SDSP + 9471405U, // C_SLLI + 163873U, // C_SLLI64_HINT + 9471405U, // C_SLLI_HINT + 9471346U, // C_SRAI + 163863U, // C_SRAI64_HINT + 9471413U, // C_SRLI + 163883U, // C_SRLI64_HINT + 9470128U, // C_SUB + 9480457U, // C_SUBW + 17852861U, // C_SW + 17845227U, // C_SWSP + 2960U, // C_UNIMP + 9473352U, // C_XOR + 536896481U, // DIV + 536891335U, // DIVU + 536898077U, // DIVUW + 536898091U, // DIVW + 3896U, // DRET + 1888U, // EBREAK + 1953U, // ECALL + 16639U, // FADD_D + 17521U, // FADD_H + 19842U, // FADD_S + 8405419U, // FCLASS_D + 8406234U, // FCLASS_H + 8408556U, // FCLASS_S + 8406119U, // FCVT_D_H + 402671470U, // FCVT_D_L + 402673542U, // FCVT_D_LU + 8408440U, // FCVT_D_S + 8415210U, // FCVT_D_W + 8409037U, // FCVT_D_WU + 402669877U, // FCVT_H_D + 402671480U, // FCVT_H_L + 402673553U, // FCVT_H_LU + 402673070U, // FCVT_H_S + 402679914U, // FCVT_H_W + 402673624U, // FCVT_H_WU + 402670021U, // FCVT_LU_D + 402670852U, // FCVT_LU_H + 402673158U, // FCVT_LU_S + 402669896U, // FCVT_L_D + 402670748U, // FCVT_L_H + 402673089U, // FCVT_L_S + 402669985U, // FCVT_S_D + 8406224U, // FCVT_S_H + 402671490U, // FCVT_S_L + 402673564U, // FCVT_S_LU + 402679979U, // FCVT_S_W + 402673635U, // FCVT_S_WU + 402670043U, // FCVT_WU_D + 402670863U, // FCVT_WU_H + 402673169U, // FCVT_WU_S + 402670073U, // FCVT_W_D + 402670882U, // FCVT_W_H + 402673188U, // FCVT_W_S + 16881U, // FDIV_D + 17690U, // FDIV_H + 19996U, // FDIV_S + 66163U, // FENCE + 1376U, // FENCE_I + 2934U, // FENCE_TSO + 536887681U, // FEQ_D + 536888521U, // FEQ_H + 536890853U, // FEQ_S + 17842778U, // FLD + 536887598U, // FLE_D + 536888460U, // FLE_H + 536890781U, // FLE_S + 17843534U, // FLH + 536887733U, // FLT_D + 536888548U, // FLT_H + 536890870U, // FLT_S + 17852779U, // FLW + 16647U, // FMADD_D + 17529U, // FMADD_H + 19850U, // FMADD_S + 536887820U, // FMAX_D + 536888629U, // FMAX_H + 536890935U, // FMAX_S + 536887642U, // FMIN_D + 536888503U, // FMIN_H + 536890835U, // FMIN_S + 16604U, // FMSUB_D + 17482U, // FMSUB_H + 19813U, // FMSUB_S + 16722U, // FMUL_D + 17574U, // FMUL_H + 19915U, // FMUL_S + 8415805U, // FMV_D_X + 8415814U, // FMV_H_X + 8415841U, // FMV_W_X + 8405507U, // FMV_X_D + 8406316U, // FMV_X_H + 8415472U, // FMV_X_W + 16656U, // FNMADD_D + 17538U, // FNMADD_H + 19859U, // FNMADD_S + 16613U, // FNMSUB_D + 17491U, // FNMSUB_H + 19822U, // FNMSUB_S + 17842798U, // FSD + 536887660U, // FSGNJN_D + 536888511U, // FSGNJN_H + 536890843U, // FSGNJN_S + 536887838U, // FSGNJX_D + 536888637U, // FSGNJX_H + 536890943U, // FSGNJX_S + 536887615U, // FSGNJ_D + 536888467U, // FSGNJ_H + 536890808U, // FSGNJ_S + 17843547U, // FSH + 134236679U, // FSL + 134244747U, // FSLW + 402670012U, // FSQRT_D + 402670827U, // FSQRT_H + 402673149U, // FSQRT_S + 134237528U, // FSR + 17891U, // FSRI + 26957U, // FSRIW + 134244791U, // FSRW + 16596U, // FSUB_D + 17474U, // FSUB_H + 19805U, // FSUB_S + 17852869U, // FSW + 536887486U, // GORC + 536888698U, // GORCI + 536897831U, // GORCIW + 536897809U, // GORCW + 536896475U, // GREV + 536889112U, // GREVI + 536897876U, // GREVIW + 536898084U, // GREVW + 28048U, // InsnB + 68201881U, // InsnI + 68201881U, // InsnI_Mem + 270577058U, // InsnJ + 135310763U, // InsnR + 135310726U, // InsnR4 + 28084U, // InsnS + 539012541U, // InsnU + 4212622U, // JAL + 17845531U, // JALR + 17842344U, // LB + 17846118U, // LBU + 17842772U, // LD + 17843535U, // LH + 17846131U, // LHU + 5259656U, // LR_D + 5262394U, // LR_D_AQ + 5261580U, // LR_D_AQ_RL + 5261296U, // LR_D_RL + 5269650U, // LR_W + 5262531U, // LR_W_AQ + 5261739U, // LR_W_AQ_RL + 5261433U, // LR_W_RL + 8406535U, // LUI + 17852773U, // LW + 17846254U, // LWU + 536898154U, // MAX + 536891379U, // MAXU + 536890208U, // MIN + 536891309U, // MINU + 3902U, // MRET + 536889870U, // MUL + 536888661U, // MULH + 536891315U, // MULHSU + 536891249U, // MULHU + 536897937U, // MULW + 536890673U, // OR + 8405136U, // ORCB + 536888792U, // ORI + 536890225U, // ORN + 536889192U, // PACK + 536888647U, // PACKH + 536891263U, // PACKU + 536898062U, // PACKUW + 536897884U, // PACKW + 536889938U, // REM + 536891303U, // REMU + 536898070U, // REMUW + 536897943U, // REMW + 8405089U, // REV8_RV32 + 8405089U, // REV8_RV64 + 536889261U, // ROL + 536897919U, // ROLW + 536890683U, // ROR + 536888791U, // RORI + 536897862U, // RORIW + 536897962U, // RORW + 17842348U, // SB + 202391801U, // SC_D + 202394620U, // SC_D_AQ + 202393796U, // SC_D_AQ_RL + 202393522U, // SC_D_RL + 202401764U, // SC_W + 202394757U, // SC_W_AQ + 202393955U, // SC_W_AQ_RL + 202393659U, // SC_W_RL + 17842792U, // SD + 8405152U, // SEXTB + 8406260U, // SEXTH + 8405100U, // SFENCE_VMA + 17843548U, // SH + 536887855U, // SH1ADD + 536898020U, // SH1ADDUW + 536887863U, // SH2ADD + 536898031U, // SH2ADDUW + 536887871U, // SH3ADD + 536898042U, // SH3ADDUW + 536889237U, // SHFL + 536888742U, // SHFLI + 536897906U, // SHFLW + 536889256U, // SLL + 536888751U, // SLLI + 536898053U, // SLLIUW + 536897848U, // SLLIW + 536897913U, // SLLW + 536891227U, // SLT + 536888824U, // SLTI + 536891256U, // SLTIU + 536891329U, // SLTU + 536887416U, // SRA + 536888692U, // SRAI + 536897824U, // SRAIW + 536897795U, // SRAW + 3908U, // SRET + 536889858U, // SRL + 536888759U, // SRLI + 536897855U, // SRLIW + 536897925U, // SRLW + 536887474U, // SUB + 536897803U, // SUBW + 17852863U, // SW + 2962U, // UNIMP + 536889235U, // UNSHFL + 536888740U, // UNSHFLI + 536897904U, // UNSHFLW + 3914U, // URET + 1073768090U, // VAADDU_VV + 1073769557U, // VAADDU_VX + 1073767694U, // VAADD_VV + 1073769208U, // VAADD_VX + 2147502703U, // VADC_VIM + 2147502853U, // VADC_VVM + 2147502907U, // VADC_VXM + 1073759805U, // VADD_VI + 1073767757U, // VADD_VV + 1073769238U, // VADD_VX + 290610U, // VAMOADDEI16_UNWD + 1751538703U, // VAMOADDEI16_WD + 290246U, // VAMOADDEI32_UNWD + 1751536517U, // VAMOADDEI32_WD + 290428U, // VAMOADDEI64_UNWD + 1751537610U, // VAMOADDEI64_WD + 290792U, // VAMOADDEI8_UNWD + 1751539754U, // VAMOADDEI8_WD + 290630U, // VAMOANDEI16_UNWD + 1751538718U, // VAMOANDEI16_WD + 290266U, // VAMOANDEI32_UNWD + 1751536532U, // VAMOANDEI32_WD + 290448U, // VAMOANDEI64_UNWD + 1751537625U, // VAMOANDEI64_WD + 290811U, // VAMOANDEI8_UNWD + 1751539768U, // VAMOANDEI8_WD + 290772U, // VAMOMAXEI16_UNWD + 1751538825U, // VAMOMAXEI16_WD + 290408U, // VAMOMAXEI32_UNWD + 1751536639U, // VAMOMAXEI32_WD + 290590U, // VAMOMAXEI64_UNWD + 1751537732U, // VAMOMAXEI64_WD + 290946U, // VAMOMAXEI8_UNWD + 1751539868U, // VAMOMAXEI8_WD + 290751U, // VAMOMAXUEI16_UNWD + 1751538809U, // VAMOMAXUEI16_WD + 290387U, // VAMOMAXUEI32_UNWD + 1751536623U, // VAMOMAXUEI32_WD + 290569U, // VAMOMAXUEI64_UNWD + 1751537716U, // VAMOMAXUEI64_WD + 290926U, // VAMOMAXUEI8_UNWD + 1751539853U, // VAMOMAXUEI8_WD + 290650U, // VAMOMINEI16_UNWD + 1751538733U, // VAMOMINEI16_WD + 290286U, // VAMOMINEI32_UNWD + 1751536547U, // VAMOMINEI32_WD + 290468U, // VAMOMINEI64_UNWD + 1751537640U, // VAMOMINEI64_WD + 290830U, // VAMOMINEI8_UNWD + 1751539782U, // VAMOMINEI8_WD + 290730U, // VAMOMINUEI16_UNWD + 1751538793U, // VAMOMINUEI16_WD + 290366U, // VAMOMINUEI32_UNWD + 1751536607U, // VAMOMINUEI32_WD + 290548U, // VAMOMINUEI64_UNWD + 1751537700U, // VAMOMINUEI64_WD + 290906U, // VAMOMINUEI8_UNWD + 1751539838U, // VAMOMINUEI8_WD + 290691U, // VAMOOREI16_UNWD + 1751538764U, // VAMOOREI16_WD + 290327U, // VAMOOREI32_UNWD + 1751536578U, // VAMOOREI32_WD + 290509U, // VAMOOREI64_UNWD + 1751537671U, // VAMOOREI64_WD + 290869U, // VAMOOREI8_UNWD + 1751539811U, // VAMOOREI8_WD + 290670U, // VAMOSWAPEI16_UNWD + 1751538748U, // VAMOSWAPEI16_WD + 290306U, // VAMOSWAPEI32_UNWD + 1751536562U, // VAMOSWAPEI32_WD + 290488U, // VAMOSWAPEI64_UNWD + 1751537655U, // VAMOSWAPEI64_WD + 290849U, // VAMOSWAPEI8_UNWD + 1751539796U, // VAMOSWAPEI8_WD + 290710U, // VAMOXOREI16_UNWD + 1751538778U, // VAMOXOREI16_WD + 290346U, // VAMOXOREI32_UNWD + 1751536592U, // VAMOXOREI32_WD + 290528U, // VAMOXOREI64_UNWD + 1751537685U, // VAMOXOREI64_WD + 290887U, // VAMOXOREI8_UNWD + 1751539824U, // VAMOXOREI8_WD + 1073759814U, // VAND_VI + 1073767787U, // VAND_VV + 1073769257U, // VAND_VX + 1073768045U, // VASUBU_VV + 1073769512U, // VASUBU_VX + 1073767452U, // VASUB_VV + 1073769096U, // VASUB_VX + 536890071U, // VCOMPRESS_VM + 25184831U, // VCPOP_M + 1073768224U, // VDIVU_VV + 1073769713U, // VDIVU_VX + 1073768254U, // VDIV_VV + 1073769733U, // VDIV_VX + 1073759034U, // VFADD_VF + 1073767704U, // VFADD_VV + 25191301U, // VFCLASS_V + 25191322U, // VFCVT_F_XU_V + 25191360U, // VFCVT_F_X_V + 25190664U, // VFCVT_RTZ_XU_F_V + 25190728U, // VFCVT_RTZ_X_F_V + 25190635U, // VFCVT_XU_F_V + 25190701U, // VFCVT_X_F_V + 1073759224U, // VFDIV_VF + 1073768244U, // VFDIV_VV + 25184840U, // VFIRST_M + 1073758986U, // VFMACC_VF + 1073767615U, // VFMACC_VV + 1073759044U, // VFMADD_VF + 1073767714U, // VFMADD_VV + 1073759245U, // VFMAX_VF + 1073768263U, // VFMAX_VV + 2147502679U, // VFMERGE_VFM + 1073759140U, // VFMIN_VF + 1073767944U, // VFMIN_VV + 1073758938U, // VFMSAC_VF + 1073767546U, // VFMSAC_VV + 1073758893U, // VFMSUB_VF + 1073767472U, // VFMSUB_VV + 1073759119U, // VFMUL_VF + 1073767885U, // VFMUL_VV + 8408484U, // VFMV_F_S + 9470607U, // VFMV_S_F + 8405657U, // VFMV_V_F + 25192474U, // VFNCVT_F_F_W + 25192648U, // VFNCVT_F_XU_W + 25192674U, // VFNCVT_F_X_W + 25192456U, // VFNCVT_ROD_F_F_W + 25192503U, // VFNCVT_RTZ_XU_F_W + 25192536U, // VFNCVT_RTZ_X_F_W + 25192488U, // VFNCVT_XU_F_W + 25192522U, // VFNCVT_X_F_W + 1073758997U, // VFNMACC_VF + 1073767626U, // VFNMACC_VV + 1073759055U, // VFNMADD_VF + 1073767725U, // VFNMADD_VV + 1073758949U, // VFNMSAC_VF + 1073767557U, // VFNMSAC_VV + 1073758904U, // VFNMSUB_VF + 1073767483U, // VFNMSUB_VV + 1073759234U, // VFRDIV_VF + 25189576U, // VFREC7_V + 1073762079U, // VFREDMAX_VS + 1073761991U, // VFREDMIN_VS + 1073761933U, // VFREDOSUM_VS + 1073761962U, // VFREDUSUM_VS + 25189586U, // VFRSQRT7_V + 1073758916U, // VFRSUB_VF + 1073759150U, // VFSGNJN_VF + 1073767963U, // VFSGNJN_VV + 1073759255U, // VFSGNJX_VF + 1073768282U, // VFSGNJX_VV + 1073759108U, // VFSGNJ_VF + 1073767846U, // VFSGNJ_VV + 1073759162U, // VFSLIDE1DOWN_VF + 1073759179U, // VFSLIDE1UP_VF + 25191312U, // VFSQRT_V + 1073758883U, // VFSUB_VF + 1073767462U, // VFSUB_VV + 1073759067U, // VFWADD_VF + 1073767766U, // VFWADD_VV + 1073759278U, // VFWADD_WF + 1073768325U, // VFWADD_WV + 25190621U, // VFWCVT_F_F_V + 25191336U, // VFWCVT_F_XU_V + 25191373U, // VFWCVT_F_X_V + 25190682U, // VFWCVT_RTZ_XU_F_V + 25190745U, // VFWCVT_RTZ_X_F_V + 25190649U, // VFWCVT_XU_F_V + 25190714U, // VFWCVT_X_F_V + 1073759022U, // VFWMACC_VF + 1073767661U, // VFWMACC_VV + 1073758974U, // VFWMSAC_VF + 1073767593U, // VFWMSAC_VV + 1073759129U, // VFWMUL_VF + 1073767914U, // VFWMUL_VV + 1073759009U, // VFWNMACC_VF + 1073767638U, // VFWNMACC_VV + 1073758961U, // VFWNMSAC_VF + 1073767580U, // VFWNMSAC_VV + 1073761947U, // VFWREDOSUM_VS + 1073761976U, // VFWREDUSUM_VS + 1073758927U, // VFWSUB_VF + 1073767525U, // VFWSUB_VV + 1073759267U, // VFWSUB_WF + 1073768304U, // VFWSUB_WV + 549078U, // VID_V + 25184795U, // VIOTA_M + 16144902U, // VL1RE16_V + 16142716U, // VL1RE32_V + 16143809U, // VL1RE64_V + 16145988U, // VL1RE8_V + 16144913U, // VL2RE16_V + 16142727U, // VL2RE32_V + 16143820U, // VL2RE64_V + 16145998U, // VL2RE8_V + 16144924U, // VL4RE16_V + 16142738U, // VL4RE32_V + 16143831U, // VL4RE64_V + 16146008U, // VL4RE8_V + 16144935U, // VL8RE16_V + 16142749U, // VL8RE32_V + 16143842U, // VL8RE64_V + 16146018U, // VL8RE8_V + 32924348U, // VLE16FF_V + 32922109U, // VLE16_V + 32924116U, // VLE32FF_V + 32919923U, // VLE32_V + 32924232U, // VLE64FF_V + 32921016U, // VLE64_V + 32924457U, // VLE8FF_V + 32923196U, // VLE8_V + 16147251U, // VLM_V + 40262808U, // VLOXEI16_V + 40260622U, // VLOXEI32_V + 40261715U, // VLOXEI64_V + 40263850U, // VLOXEI8_V + 40262223U, // VLOXSEG2EI16_V + 40260037U, // VLOXSEG2EI32_V + 40261130U, // VLOXSEG2EI64_V + 40263302U, // VLOXSEG2EI8_V + 40262287U, // VLOXSEG3EI16_V + 40260101U, // VLOXSEG3EI32_V + 40261194U, // VLOXSEG3EI64_V + 40263362U, // VLOXSEG3EI8_V + 40262351U, // VLOXSEG4EI16_V + 40260165U, // VLOXSEG4EI32_V + 40261258U, // VLOXSEG4EI64_V + 40263422U, // VLOXSEG4EI8_V + 40262415U, // VLOXSEG5EI16_V + 40260229U, // VLOXSEG5EI32_V + 40261322U, // VLOXSEG5EI64_V + 40263482U, // VLOXSEG5EI8_V + 40262479U, // VLOXSEG6EI16_V + 40260293U, // VLOXSEG6EI32_V + 40261386U, // VLOXSEG6EI64_V + 40263542U, // VLOXSEG6EI8_V + 40262543U, // VLOXSEG7EI16_V + 40260357U, // VLOXSEG7EI32_V + 40261450U, // VLOXSEG7EI64_V + 40263602U, // VLOXSEG7EI8_V + 40262607U, // VLOXSEG8EI16_V + 40260421U, // VLOXSEG8EI32_V + 40261514U, // VLOXSEG8EI64_V + 40263662U, // VLOXSEG8EI8_V + 40262194U, // VLSE16_V + 40260008U, // VLSE32_V + 40261101U, // VLSE64_V + 40263276U, // VLSE8_V + 32924243U, // VLSEG2E16FF_V + 32921731U, // VLSEG2E16_V + 32924011U, // VLSEG2E32FF_V + 32919545U, // VLSEG2E32_V + 32924127U, // VLSEG2E64FF_V + 32920638U, // VLSEG2E64_V + 32924359U, // VLSEG2E8FF_V + 32922846U, // VLSEG2E8_V + 32924258U, // VLSEG3E16FF_V + 32921785U, // VLSEG3E16_V + 32924026U, // VLSEG3E32FF_V + 32919599U, // VLSEG3E32_V + 32924142U, // VLSEG3E64FF_V + 32920692U, // VLSEG3E64_V + 32924373U, // VLSEG3E8FF_V + 32922896U, // VLSEG3E8_V + 32924273U, // VLSEG4E16FF_V + 32921839U, // VLSEG4E16_V + 32924041U, // VLSEG4E32FF_V + 32919653U, // VLSEG4E32_V + 32924157U, // VLSEG4E64FF_V + 32920746U, // VLSEG4E64_V + 32924387U, // VLSEG4E8FF_V + 32922946U, // VLSEG4E8_V + 32924288U, // VLSEG5E16FF_V + 32921893U, // VLSEG5E16_V + 32924056U, // VLSEG5E32FF_V + 32919707U, // VLSEG5E32_V + 32924172U, // VLSEG5E64FF_V + 32920800U, // VLSEG5E64_V + 32924401U, // VLSEG5E8FF_V + 32922996U, // VLSEG5E8_V + 32924303U, // VLSEG6E16FF_V + 32921947U, // VLSEG6E16_V + 32924071U, // VLSEG6E32FF_V + 32919761U, // VLSEG6E32_V + 32924187U, // VLSEG6E64FF_V + 32920854U, // VLSEG6E64_V + 32924415U, // VLSEG6E8FF_V + 32923046U, // VLSEG6E8_V + 32924318U, // VLSEG7E16FF_V + 32922001U, // VLSEG7E16_V + 32924086U, // VLSEG7E32FF_V + 32919815U, // VLSEG7E32_V + 32924202U, // VLSEG7E64FF_V + 32920908U, // VLSEG7E64_V + 32924429U, // VLSEG7E8FF_V + 32923096U, // VLSEG7E8_V + 32924333U, // VLSEG8E16FF_V + 32922055U, // VLSEG8E16_V + 32924101U, // VLSEG8E32FF_V + 32919869U, // VLSEG8E32_V + 32924217U, // VLSEG8E64FF_V + 32920962U, // VLSEG8E64_V + 32924443U, // VLSEG8E8FF_V + 32923146U, // VLSEG8E8_V + 40261776U, // VLSSEG2E16_V + 40259590U, // VLSSEG2E32_V + 40260683U, // VLSSEG2E64_V + 40262890U, // VLSSEG2E8_V + 40261830U, // VLSSEG3E16_V + 40259644U, // VLSSEG3E32_V + 40260737U, // VLSSEG3E64_V + 40262940U, // VLSSEG3E8_V + 40261884U, // VLSSEG4E16_V + 40259698U, // VLSSEG4E32_V + 40260791U, // VLSSEG4E64_V + 40262990U, // VLSSEG4E8_V + 40261938U, // VLSSEG5E16_V + 40259752U, // VLSSEG5E32_V + 40260845U, // VLSSEG5E64_V + 40263040U, // VLSSEG5E8_V + 40261992U, // VLSSEG6E16_V + 40259806U, // VLSSEG6E32_V + 40260899U, // VLSSEG6E64_V + 40263090U, // VLSSEG6E8_V + 40262046U, // VLSSEG7E16_V + 40259860U, // VLSSEG7E32_V + 40260953U, // VLSSEG7E64_V + 40263140U, // VLSSEG7E8_V + 40262100U, // VLSSEG8E16_V + 40259914U, // VLSSEG8E32_V + 40261007U, // VLSSEG8E64_V + 40263190U, // VLSSEG8E8_V + 40262832U, // VLUXEI16_V + 40260646U, // VLUXEI32_V + 40261739U, // VLUXEI64_V + 40263872U, // VLUXEI8_V + 40262255U, // VLUXSEG2EI16_V + 40260069U, // VLUXSEG2EI32_V + 40261162U, // VLUXSEG2EI64_V + 40263332U, // VLUXSEG2EI8_V + 40262319U, // VLUXSEG3EI16_V + 40260133U, // VLUXSEG3EI32_V + 40261226U, // VLUXSEG3EI64_V + 40263392U, // VLUXSEG3EI8_V + 40262383U, // VLUXSEG4EI16_V + 40260197U, // VLUXSEG4EI32_V + 40261290U, // VLUXSEG4EI64_V + 40263452U, // VLUXSEG4EI8_V + 40262447U, // VLUXSEG5EI16_V + 40260261U, // VLUXSEG5EI32_V + 40261354U, // VLUXSEG5EI64_V + 40263512U, // VLUXSEG5EI8_V + 40262511U, // VLUXSEG6EI16_V + 40260325U, // VLUXSEG6EI32_V + 40261418U, // VLUXSEG6EI64_V + 40263572U, // VLUXSEG6EI8_V + 40262575U, // VLUXSEG7EI16_V + 40260389U, // VLUXSEG7EI32_V + 40261482U, // VLUXSEG7EI64_V + 40263632U, // VLUXSEG7EI8_V + 40262639U, // VLUXSEG8EI16_V + 40260453U, // VLUXSEG8EI32_V + 40261546U, // VLUXSEG8EI64_V + 40263692U, // VLUXSEG8EI8_V + 1073767651U, // VMACC_VV + 1073769177U, // VMACC_VX + 536888873U, // VMADC_VI + 2147502692U, // VMADC_VIM + 536896772U, // VMADC_VV + 2147502842U, // VMADC_VVM + 536898286U, // VMADC_VX + 2147502896U, // VMADC_VXM + 1073767737U, // VMADD_VV + 1073769218U, // VMADD_VX + 536890010U, // VMANDN_MM + 536889989U, // VMAND_MM + 1073768234U, // VMAXU_VV + 1073769723U, // VMAXU_VX + 1073768273U, // VMAX_VV + 1073769742U, // VMAX_VX + 2147502713U, // VMERGE_VIM + 2147502863U, // VMERGE_VVM + 2147502917U, // VMERGE_VXM + 1073759194U, // VMFEQ_VF + 1073767975U, // VMFEQ_VV + 1073759078U, // VMFGE_VF + 1073759204U, // VMFGT_VF + 1073759088U, // VMFLE_VF + 1073767796U, // VMFLE_VV + 1073759214U, // VMFLT_VF + 1073768025U, // VMFLT_VV + 1073759098U, // VMFNE_VF + 1073767816U, // VMFNE_VV + 1073768166U, // VMINU_VV + 1073769644U, // VMINU_VX + 1073767954U, // VMIN_VV + 1073769372U, // VMIN_VX + 536889999U, // VMNAND_MM + 536890040U, // VMNOR_MM + 536890021U, // VMORN_MM + 536890031U, // VMOR_MM + 536896693U, // VMSBC_VV + 2147502821U, // VMSBC_VVM + 536898255U, // VMSBC_VX + 2147502875U, // VMSBC_VXM + 25184804U, // VMSBF_M + 1073759909U, // VMSEQ_VI + 1073767985U, // VMSEQ_VV + 1073769439U, // VMSEQ_VX + 1073760002U, // VMSGTU_VI + 1073769691U, // VMSGTU_VX + 1073759949U, // VMSGT_VI + 1073769492U, // VMSGT_VX + 25184813U, // VMSIF_M + 1073759991U, // VMSLEU_VI + 1073768123U, // VMSLEU_VV + 1073769601U, // VMSLEU_VX + 1073759833U, // VMSLE_VI + 1073767806U, // VMSLE_VV + 1073769276U, // VMSLE_VX + 1073768213U, // VMSLTU_VV + 1073769702U, // VMSLTU_VX + 1073768035U, // VMSLT_VV + 1073769502U, // VMSLT_VX + 1073759843U, // VMSNE_VI + 1073767826U, // VMSNE_VV + 1073769286U, // VMSNE_VX + 25184822U, // VMSOF_M + 1073768189U, // VMULHSU_VV + 1073769667U, // VMULHSU_VX + 1073768134U, // VMULHU_VV + 1073769612U, // VMULHU_VX + 1073767836U, // VMULH_VV + 1073769296U, // VMULH_VX + 1073767905U, // VMUL_VV + 1073769344U, // VMUL_VX + 8414025U, // VMV1R_V + 8414042U, // VMV2R_V + 8414059U, // VMV4R_V + 8414076U, // VMV8R_V + 9480783U, // VMV_S_X + 8406377U, // VMV_V_I + 8414135U, // VMV_V_V + 8415832U, // VMV_V_X + 8408622U, // VMV_X_S + 536890050U, // VMXNOR_MM + 536890061U, // VMXOR_MM + 1073760069U, // VNCLIPU_WI + 1073768389U, // VNCLIPU_WV + 1073769824U, // VNCLIPU_WX + 1073760058U, // VNCLIP_WI + 1073768356U, // VNCLIP_WV + 1073769791U, // VNCLIP_WX + 1073767569U, // VNMSAC_VV + 1073769156U, // VNMSAC_VX + 1073767495U, // VNMSUB_VV + 1073769106U, // VNMSUB_VX + 1073760038U, // VNSRA_WI + 1073768294U, // VNSRA_WV + 1073769751U, // VNSRA_WX + 1073760048U, // VNSRL_WI + 1073768346U, // VNSRL_WV + 1073769781U, // VNSRL_WX + 1073759932U, // VOR_VI + 1073768008U, // VOR_VV + 1073769462U, // VOR_VX + 1073761896U, // VREDAND_VS + 1073762066U, // VREDMAXU_VS + 1073762092U, // VREDMAX_VS + 1073762053U, // VREDMINU_VS + 1073762004U, // VREDMIN_VS + 1073762016U, // VREDOR_VS + 1073761908U, // VREDSUM_VS + 1073762027U, // VREDXOR_VS + 1073768156U, // VREMU_VV + 1073769634U, // VREMU_VX + 1073767935U, // VREM_VV + 1073769363U, // VREM_VX + 1073767416U, // VRGATHEREI16_VV + 1073759919U, // VRGATHER_VI + 1073767995U, // VRGATHER_VV + 1073769449U, // VRGATHER_VX + 1073759775U, // VRSUB_VI + 1073769117U, // VRSUB_VX + 16147265U, // VS1R_V + 16147282U, // VS2R_V + 16147299U, // VS4R_V + 16147316U, // VS8R_V + 1073759969U, // VSADDU_VI + 1073768101U, // VSADDU_VV + 1073769568U, // VSADDU_VX + 1073759795U, // VSADD_VI + 1073767747U, // VSADD_VV + 1073769228U, // VSADD_VX + 2147502832U, // VSBC_VVM + 2147502886U, // VSBC_VXM + 32922182U, // VSE16_V + 32919996U, // VSE32_V + 32921089U, // VSE64_V + 32923262U, // VSE8_V + 469779901U, // VSETIVLI + 536889875U, // VSETVL + 469779911U, // VSETVLI + 25182209U, // VSEXT_VF2 + 25182261U, // VSEXT_VF4 + 25182283U, // VSEXT_VF8 + 1073769381U, // VSLIDE1DOWN_VX + 1073769412U, // VSLIDE1UP_VX + 1073759881U, // VSLIDEDOWN_VI + 1073769397U, // VSLIDEDOWN_VX + 1073759896U, // VSLIDEUP_VI + 1073769426U, // VSLIDEUP_VX + 1073759853U, // VSLL_VI + 1073767857U, // VSLL_VV + 1073769306U, // VSLL_VX + 1073767895U, // VSMUL_VV + 1073769334U, // VSMUL_VX + 16147258U, // VSM_V + 40262820U, // VSOXEI16_V + 40260634U, // VSOXEI32_V + 40261727U, // VSOXEI64_V + 40263861U, // VSOXEI8_V + 40262239U, // VSOXSEG2EI16_V + 40260053U, // VSOXSEG2EI32_V + 40261146U, // VSOXSEG2EI64_V + 40263317U, // VSOXSEG2EI8_V + 40262303U, // VSOXSEG3EI16_V + 40260117U, // VSOXSEG3EI32_V + 40261210U, // VSOXSEG3EI64_V + 40263377U, // VSOXSEG3EI8_V + 40262367U, // VSOXSEG4EI16_V + 40260181U, // VSOXSEG4EI32_V + 40261274U, // VSOXSEG4EI64_V + 40263437U, // VSOXSEG4EI8_V + 40262431U, // VSOXSEG5EI16_V + 40260245U, // VSOXSEG5EI32_V + 40261338U, // VSOXSEG5EI64_V + 40263497U, // VSOXSEG5EI8_V + 40262495U, // VSOXSEG6EI16_V + 40260309U, // VSOXSEG6EI32_V + 40261402U, // VSOXSEG6EI64_V + 40263557U, // VSOXSEG6EI8_V + 40262559U, // VSOXSEG7EI16_V + 40260373U, // VSOXSEG7EI32_V + 40261466U, // VSOXSEG7EI64_V + 40263617U, // VSOXSEG7EI8_V + 40262623U, // VSOXSEG8EI16_V + 40260437U, // VSOXSEG8EI32_V + 40261530U, // VSOXSEG8EI64_V + 40263677U, // VSOXSEG8EI8_V + 1073759766U, // VSRA_VI + 1073767443U, // VSRA_VV + 1073769087U, // VSRA_VX + 1073759872U, // VSRL_VI + 1073767876U, // VSRL_VV + 1073769325U, // VSRL_VX + 40262204U, // VSSE16_V + 40260018U, // VSSE32_V + 40261111U, // VSSE64_V + 40263285U, // VSSE8_V + 32921772U, // VSSEG2E16_V + 32919586U, // VSSEG2E32_V + 32920679U, // VSSEG2E64_V + 32922884U, // VSSEG2E8_V + 32921826U, // VSSEG3E16_V + 32919640U, // VSSEG3E32_V + 32920733U, // VSSEG3E64_V + 32922934U, // VSSEG3E8_V + 32921880U, // VSSEG4E16_V + 32919694U, // VSSEG4E32_V + 32920787U, // VSSEG4E64_V + 32922984U, // VSSEG4E8_V + 32921934U, // VSSEG5E16_V + 32919748U, // VSSEG5E32_V + 32920841U, // VSSEG5E64_V + 32923034U, // VSSEG5E8_V + 32921988U, // VSSEG6E16_V + 32919802U, // VSSEG6E32_V + 32920895U, // VSSEG6E64_V + 32923084U, // VSSEG6E8_V + 32922042U, // VSSEG7E16_V + 32919856U, // VSSEG7E32_V + 32920949U, // VSSEG7E64_V + 32923134U, // VSSEG7E8_V + 32922096U, // VSSEG8E16_V + 32919910U, // VSSEG8E32_V + 32921003U, // VSSEG8E64_V + 32923184U, // VSSEG8E8_V + 1073759756U, // VSSRA_VI + 1073767433U, // VSSRA_VV + 1073769077U, // VSSRA_VX + 1073759862U, // VSSRL_VI + 1073767866U, // VSSRL_VV + 1073769315U, // VSSRL_VX + 40261790U, // VSSSEG2E16_V + 40259604U, // VSSSEG2E32_V + 40260697U, // VSSSEG2E64_V + 40262903U, // VSSSEG2E8_V + 40261844U, // VSSSEG3E16_V + 40259658U, // VSSSEG3E32_V + 40260751U, // VSSSEG3E64_V + 40262953U, // VSSSEG3E8_V + 40261898U, // VSSSEG4E16_V + 40259712U, // VSSSEG4E32_V + 40260805U, // VSSSEG4E64_V + 40263003U, // VSSSEG4E8_V + 40261952U, // VSSSEG5E16_V + 40259766U, // VSSSEG5E32_V + 40260859U, // VSSSEG5E64_V + 40263053U, // VSSSEG5E8_V + 40262006U, // VSSSEG6E16_V + 40259820U, // VSSSEG6E32_V + 40260913U, // VSSSEG6E64_V + 40263103U, // VSSSEG6E8_V + 40262060U, // VSSSEG7E16_V + 40259874U, // VSSSEG7E32_V + 40260967U, // VSSSEG7E64_V + 40263153U, // VSSSEG7E8_V + 40262114U, // VSSSEG8E16_V + 40259928U, // VSSSEG8E32_V + 40261021U, // VSSSEG8E64_V + 40263203U, // VSSSEG8E8_V + 1073768056U, // VSSUBU_VV + 1073769523U, // VSSUBU_VX + 1073767506U, // VSSUB_VV + 1073769127U, // VSSUB_VX + 1073767516U, // VSUB_VV + 1073769137U, // VSUB_VX + 40262844U, // VSUXEI16_V + 40260658U, // VSUXEI32_V + 40261751U, // VSUXEI64_V + 40263883U, // VSUXEI8_V + 40262271U, // VSUXSEG2EI16_V + 40260085U, // VSUXSEG2EI32_V + 40261178U, // VSUXSEG2EI64_V + 40263347U, // VSUXSEG2EI8_V + 40262335U, // VSUXSEG3EI16_V + 40260149U, // VSUXSEG3EI32_V + 40261242U, // VSUXSEG3EI64_V + 40263407U, // VSUXSEG3EI8_V + 40262399U, // VSUXSEG4EI16_V + 40260213U, // VSUXSEG4EI32_V + 40261306U, // VSUXSEG4EI64_V + 40263467U, // VSUXSEG4EI8_V + 40262463U, // VSUXSEG5EI16_V + 40260277U, // VSUXSEG5EI32_V + 40261370U, // VSUXSEG5EI64_V + 40263527U, // VSUXSEG5EI8_V + 40262527U, // VSUXSEG6EI16_V + 40260341U, // VSUXSEG6EI32_V + 40261434U, // VSUXSEG6EI64_V + 40263587U, // VSUXSEG6EI8_V + 40262591U, // VSUXSEG7EI16_V + 40260405U, // VSUXSEG7EI32_V + 40261498U, // VSUXSEG7EI64_V + 40263647U, // VSUXSEG7EI8_V + 40262655U, // VSUXSEG8EI16_V + 40260469U, // VSUXSEG8EI32_V + 40261562U, // VSUXSEG8EI64_V + 40263707U, // VSUXSEG8EI8_V + 1073768112U, // VWADDU_VV + 1073769579U, // VWADDU_VX + 1073768378U, // VWADDU_WV + 1073769813U, // VWADDU_WX + 1073767777U, // VWADD_VV + 1073769247U, // VWADD_VX + 1073768336U, // VWADD_WV + 1073769771U, // VWADD_WX + 1073768176U, // VWMACCSU_VV + 1073769654U, // VWMACCSU_VX + 1073769479U, // VWMACCUS_VX + 1073768078U, // VWMACCU_VV + 1073769545U, // VWMACCU_VX + 1073767673U, // VWMACC_VV + 1073769187U, // VWMACC_VX + 1073768201U, // VWMULSU_VV + 1073769679U, // VWMULSU_VX + 1073768145U, // VWMULU_VV + 1073769623U, // VWMULU_VX + 1073767925U, // VWMUL_VV + 1073769353U, // VWMUL_VX + 1073762039U, // VWREDSUMU_VS + 1073761920U, // VWREDSUM_VS + 1073768067U, // VWSUBU_VV + 1073769534U, // VWSUBU_VX + 1073768367U, // VWSUBU_WV + 1073769802U, // VWSUBU_WX + 1073767536U, // VWSUB_VV + 1073769146U, // VWSUB_VX + 1073768315U, // VWSUB_WV + 1073769761U, // VWSUB_WX + 1073759940U, // VXOR_VI + 1073768016U, // VXOR_VV + 1073769470U, // VXOR_VX + 25182220U, // VZEXT_VF2 + 25182272U, // VZEXT_VF4 + 25182294U, // VZEXT_VF8 + 1433U, // WFI + 536890677U, // XNOR + 536890698U, // XOR + 536888797U, // XORI + 536887447U, // XPERMB + 536888494U, // XPERMH + 536890193U, // XPERMN + 536897652U, // XPERMW + 8406268U, // ZEXTH_RV32 + 8406268U, // ZEXTH_RV64 + }; + + static const uint8_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // BuildPairF64Pseudo + 0U, // PseudoAddTPRel + 0U, // PseudoAtomicLoadNand32 + 0U, // PseudoAtomicLoadNand64 + 0U, // PseudoBR + 0U, // PseudoBRIND + 0U, // PseudoCALL + 0U, // PseudoCALLIndirect + 0U, // PseudoCALLReg + 0U, // PseudoCmpXchg32 + 0U, // PseudoCmpXchg64 + 0U, // PseudoFLD + 0U, // PseudoFLH + 0U, // PseudoFLW + 0U, // PseudoFSD + 0U, // PseudoFSH + 0U, // PseudoFSW + 0U, // PseudoJump + 0U, // PseudoLA + 0U, // PseudoLA_TLS_GD + 0U, // PseudoLA_TLS_IE + 0U, // PseudoLB + 0U, // PseudoLBU + 0U, // PseudoLD + 0U, // PseudoLH + 0U, // PseudoLHU + 0U, // PseudoLI + 0U, // PseudoLLA + 0U, // PseudoLW + 0U, // PseudoLWU + 0U, // PseudoMaskedAtomicLoadAdd32 + 0U, // PseudoMaskedAtomicLoadMax32 + 0U, // PseudoMaskedAtomicLoadMin32 + 0U, // PseudoMaskedAtomicLoadNand32 + 0U, // PseudoMaskedAtomicLoadSub32 + 0U, // PseudoMaskedAtomicLoadUMax32 + 0U, // PseudoMaskedAtomicLoadUMin32 + 0U, // PseudoMaskedAtomicSwap32 + 0U, // PseudoMaskedCmpXchg32 + 0U, // PseudoRET + 0U, // PseudoReadVL + 0U, // PseudoReadVLENB + 0U, // PseudoSB + 0U, // PseudoSD + 0U, // PseudoSEXT_B + 0U, // PseudoSEXT_H + 0U, // PseudoSH + 0U, // PseudoSW + 0U, // PseudoTAIL + 0U, // PseudoTAILIndirect + 0U, // PseudoVAADDU_VV_M1 + 0U, // PseudoVAADDU_VV_M1_MASK + 0U, // PseudoVAADDU_VV_M2 + 0U, // PseudoVAADDU_VV_M2_MASK + 0U, // PseudoVAADDU_VV_M4 + 0U, // PseudoVAADDU_VV_M4_MASK + 0U, // PseudoVAADDU_VV_M8 + 0U, // PseudoVAADDU_VV_M8_MASK + 0U, // PseudoVAADDU_VV_MF2 + 0U, // PseudoVAADDU_VV_MF2_MASK + 0U, // PseudoVAADDU_VV_MF4 + 0U, // PseudoVAADDU_VV_MF4_MASK + 0U, // PseudoVAADDU_VV_MF8 + 0U, // PseudoVAADDU_VV_MF8_MASK + 0U, // PseudoVAADDU_VX_M1 + 0U, // PseudoVAADDU_VX_M1_MASK + 0U, // PseudoVAADDU_VX_M2 + 0U, // PseudoVAADDU_VX_M2_MASK + 0U, // PseudoVAADDU_VX_M4 + 0U, // PseudoVAADDU_VX_M4_MASK + 0U, // PseudoVAADDU_VX_M8 + 0U, // PseudoVAADDU_VX_M8_MASK + 0U, // PseudoVAADDU_VX_MF2 + 0U, // PseudoVAADDU_VX_MF2_MASK + 0U, // PseudoVAADDU_VX_MF4 + 0U, // PseudoVAADDU_VX_MF4_MASK + 0U, // PseudoVAADDU_VX_MF8 + 0U, // PseudoVAADDU_VX_MF8_MASK + 0U, // PseudoVAADD_VV_M1 + 0U, // PseudoVAADD_VV_M1_MASK + 0U, // PseudoVAADD_VV_M2 + 0U, // PseudoVAADD_VV_M2_MASK + 0U, // PseudoVAADD_VV_M4 + 0U, // PseudoVAADD_VV_M4_MASK + 0U, // PseudoVAADD_VV_M8 + 0U, // PseudoVAADD_VV_M8_MASK + 0U, // PseudoVAADD_VV_MF2 + 0U, // PseudoVAADD_VV_MF2_MASK + 0U, // PseudoVAADD_VV_MF4 + 0U, // PseudoVAADD_VV_MF4_MASK + 0U, // PseudoVAADD_VV_MF8 + 0U, // PseudoVAADD_VV_MF8_MASK + 0U, // PseudoVAADD_VX_M1 + 0U, // PseudoVAADD_VX_M1_MASK + 0U, // PseudoVAADD_VX_M2 + 0U, // PseudoVAADD_VX_M2_MASK + 0U, // PseudoVAADD_VX_M4 + 0U, // PseudoVAADD_VX_M4_MASK + 0U, // PseudoVAADD_VX_M8 + 0U, // PseudoVAADD_VX_M8_MASK + 0U, // PseudoVAADD_VX_MF2 + 0U, // PseudoVAADD_VX_MF2_MASK + 0U, // PseudoVAADD_VX_MF4 + 0U, // PseudoVAADD_VX_MF4_MASK + 0U, // PseudoVAADD_VX_MF8 + 0U, // PseudoVAADD_VX_MF8_MASK + 0U, // PseudoVADC_VIM_M1 + 0U, // PseudoVADC_VIM_M2 + 0U, // PseudoVADC_VIM_M4 + 0U, // PseudoVADC_VIM_M8 + 0U, // PseudoVADC_VIM_MF2 + 0U, // PseudoVADC_VIM_MF4 + 0U, // PseudoVADC_VIM_MF8 + 0U, // PseudoVADC_VVM_M1 + 0U, // PseudoVADC_VVM_M2 + 0U, // PseudoVADC_VVM_M4 + 0U, // PseudoVADC_VVM_M8 + 0U, // PseudoVADC_VVM_MF2 + 0U, // PseudoVADC_VVM_MF4 + 0U, // PseudoVADC_VVM_MF8 + 0U, // PseudoVADC_VXM_M1 + 0U, // PseudoVADC_VXM_M2 + 0U, // PseudoVADC_VXM_M4 + 0U, // PseudoVADC_VXM_M8 + 0U, // PseudoVADC_VXM_MF2 + 0U, // PseudoVADC_VXM_MF4 + 0U, // PseudoVADC_VXM_MF8 + 0U, // PseudoVADD_VI_M1 + 0U, // PseudoVADD_VI_M1_MASK + 0U, // PseudoVADD_VI_M2 + 0U, // PseudoVADD_VI_M2_MASK + 0U, // PseudoVADD_VI_M4 + 0U, // PseudoVADD_VI_M4_MASK + 0U, // PseudoVADD_VI_M8 + 0U, // PseudoVADD_VI_M8_MASK + 0U, // PseudoVADD_VI_MF2 + 0U, // PseudoVADD_VI_MF2_MASK + 0U, // PseudoVADD_VI_MF4 + 0U, // PseudoVADD_VI_MF4_MASK + 0U, // PseudoVADD_VI_MF8 + 0U, // PseudoVADD_VI_MF8_MASK + 0U, // PseudoVADD_VV_M1 + 0U, // PseudoVADD_VV_M1_MASK + 0U, // PseudoVADD_VV_M2 + 0U, // PseudoVADD_VV_M2_MASK + 0U, // PseudoVADD_VV_M4 + 0U, // PseudoVADD_VV_M4_MASK + 0U, // PseudoVADD_VV_M8 + 0U, // PseudoVADD_VV_M8_MASK + 0U, // PseudoVADD_VV_MF2 + 0U, // PseudoVADD_VV_MF2_MASK + 0U, // PseudoVADD_VV_MF4 + 0U, // PseudoVADD_VV_MF4_MASK + 0U, // PseudoVADD_VV_MF8 + 0U, // PseudoVADD_VV_MF8_MASK + 0U, // PseudoVADD_VX_M1 + 0U, // PseudoVADD_VX_M1_MASK + 0U, // PseudoVADD_VX_M2 + 0U, // PseudoVADD_VX_M2_MASK + 0U, // PseudoVADD_VX_M4 + 0U, // PseudoVADD_VX_M4_MASK + 0U, // PseudoVADD_VX_M8 + 0U, // PseudoVADD_VX_M8_MASK + 0U, // PseudoVADD_VX_MF2 + 0U, // PseudoVADD_VX_MF2_MASK + 0U, // PseudoVADD_VX_MF4 + 0U, // PseudoVADD_VX_MF4_MASK + 0U, // PseudoVADD_VX_MF8 + 0U, // PseudoVADD_VX_MF8_MASK + 0U, // PseudoVAMOADDEI16_WD_M1_MF2 + 0U, // PseudoVAMOADDEI16_WD_M1_MF2_MASK + 0U, // PseudoVAMOADDEI16_WD_M1_MF4 + 0U, // PseudoVAMOADDEI16_WD_M1_MF4_MASK + 0U, // PseudoVAMOADDEI16_WD_M2_M1 + 0U, // PseudoVAMOADDEI16_WD_M2_M1_MASK + 0U, // PseudoVAMOADDEI16_WD_M2_MF2 + 0U, // PseudoVAMOADDEI16_WD_M2_MF2_MASK + 0U, // PseudoVAMOADDEI16_WD_M4_M1 + 0U, // PseudoVAMOADDEI16_WD_M4_M1_MASK + 0U, // PseudoVAMOADDEI16_WD_M4_M2 + 0U, // PseudoVAMOADDEI16_WD_M4_M2_MASK + 0U, // PseudoVAMOADDEI16_WD_M8_M2 + 0U, // PseudoVAMOADDEI16_WD_M8_M2_MASK + 0U, // PseudoVAMOADDEI16_WD_M8_M4 + 0U, // PseudoVAMOADDEI16_WD_M8_M4_MASK + 0U, // PseudoVAMOADDEI16_WD_MF2_MF4 + 0U, // PseudoVAMOADDEI16_WD_MF2_MF4_MASK + 0U, // PseudoVAMOADDEI32_WD_M1_M1 + 0U, // PseudoVAMOADDEI32_WD_M1_M1_MASK + 0U, // PseudoVAMOADDEI32_WD_M1_MF2 + 0U, // PseudoVAMOADDEI32_WD_M1_MF2_MASK + 0U, // PseudoVAMOADDEI32_WD_M2_M1 + 0U, // PseudoVAMOADDEI32_WD_M2_M1_MASK + 0U, // PseudoVAMOADDEI32_WD_M2_M2 + 0U, // PseudoVAMOADDEI32_WD_M2_M2_MASK + 0U, // PseudoVAMOADDEI32_WD_M4_M2 + 0U, // PseudoVAMOADDEI32_WD_M4_M2_MASK + 0U, // PseudoVAMOADDEI32_WD_M4_M4 + 0U, // PseudoVAMOADDEI32_WD_M4_M4_MASK + 0U, // PseudoVAMOADDEI32_WD_M8_M4 + 0U, // PseudoVAMOADDEI32_WD_M8_M4_MASK + 0U, // PseudoVAMOADDEI32_WD_M8_M8 + 0U, // PseudoVAMOADDEI32_WD_M8_M8_MASK + 0U, // PseudoVAMOADDEI32_WD_MF2_MF2 + 0U, // PseudoVAMOADDEI32_WD_MF2_MF2_MASK + 0U, // PseudoVAMOADDEI64_WD_M1_M1 + 0U, // PseudoVAMOADDEI64_WD_M1_M1_MASK + 0U, // PseudoVAMOADDEI64_WD_M1_M2 + 0U, // PseudoVAMOADDEI64_WD_M1_M2_MASK + 0U, // PseudoVAMOADDEI64_WD_M2_M2 + 0U, // PseudoVAMOADDEI64_WD_M2_M2_MASK + 0U, // PseudoVAMOADDEI64_WD_M2_M4 + 0U, // PseudoVAMOADDEI64_WD_M2_M4_MASK + 0U, // PseudoVAMOADDEI64_WD_M4_M4 + 0U, // PseudoVAMOADDEI64_WD_M4_M4_MASK + 0U, // PseudoVAMOADDEI64_WD_M4_M8 + 0U, // PseudoVAMOADDEI64_WD_M4_M8_MASK + 0U, // PseudoVAMOADDEI64_WD_M8_M8 + 0U, // PseudoVAMOADDEI64_WD_M8_M8_MASK + 0U, // PseudoVAMOADDEI64_WD_MF2_M1 + 0U, // PseudoVAMOADDEI64_WD_MF2_M1_MASK + 0U, // PseudoVAMOADDEI8_WD_M1_MF4 + 0U, // PseudoVAMOADDEI8_WD_M1_MF4_MASK + 0U, // PseudoVAMOADDEI8_WD_M1_MF8 + 0U, // PseudoVAMOADDEI8_WD_M1_MF8_MASK + 0U, // PseudoVAMOADDEI8_WD_M2_MF2 + 0U, // PseudoVAMOADDEI8_WD_M2_MF2_MASK + 0U, // PseudoVAMOADDEI8_WD_M2_MF4 + 0U, // PseudoVAMOADDEI8_WD_M2_MF4_MASK + 0U, // PseudoVAMOADDEI8_WD_M4_M1 + 0U, // PseudoVAMOADDEI8_WD_M4_M1_MASK + 0U, // PseudoVAMOADDEI8_WD_M4_MF2 + 0U, // PseudoVAMOADDEI8_WD_M4_MF2_MASK + 0U, // PseudoVAMOADDEI8_WD_M8_M1 + 0U, // PseudoVAMOADDEI8_WD_M8_M1_MASK + 0U, // PseudoVAMOADDEI8_WD_M8_M2 + 0U, // PseudoVAMOADDEI8_WD_M8_M2_MASK + 0U, // PseudoVAMOADDEI8_WD_MF2_MF8 + 0U, // PseudoVAMOADDEI8_WD_MF2_MF8_MASK + 0U, // PseudoVAMOANDEI16_WD_M1_MF2 + 0U, // PseudoVAMOANDEI16_WD_M1_MF2_MASK + 0U, // PseudoVAMOANDEI16_WD_M1_MF4 + 0U, // PseudoVAMOANDEI16_WD_M1_MF4_MASK + 0U, // PseudoVAMOANDEI16_WD_M2_M1 + 0U, // PseudoVAMOANDEI16_WD_M2_M1_MASK + 0U, // PseudoVAMOANDEI16_WD_M2_MF2 + 0U, // PseudoVAMOANDEI16_WD_M2_MF2_MASK + 0U, // PseudoVAMOANDEI16_WD_M4_M1 + 0U, // PseudoVAMOANDEI16_WD_M4_M1_MASK + 0U, // PseudoVAMOANDEI16_WD_M4_M2 + 0U, // PseudoVAMOANDEI16_WD_M4_M2_MASK + 0U, // PseudoVAMOANDEI16_WD_M8_M2 + 0U, // PseudoVAMOANDEI16_WD_M8_M2_MASK + 0U, // PseudoVAMOANDEI16_WD_M8_M4 + 0U, // PseudoVAMOANDEI16_WD_M8_M4_MASK + 0U, // PseudoVAMOANDEI16_WD_MF2_MF4 + 0U, // PseudoVAMOANDEI16_WD_MF2_MF4_MASK + 0U, // PseudoVAMOANDEI32_WD_M1_M1 + 0U, // PseudoVAMOANDEI32_WD_M1_M1_MASK + 0U, // PseudoVAMOANDEI32_WD_M1_MF2 + 0U, // PseudoVAMOANDEI32_WD_M1_MF2_MASK + 0U, // PseudoVAMOANDEI32_WD_M2_M1 + 0U, // PseudoVAMOANDEI32_WD_M2_M1_MASK + 0U, // PseudoVAMOANDEI32_WD_M2_M2 + 0U, // PseudoVAMOANDEI32_WD_M2_M2_MASK + 0U, // PseudoVAMOANDEI32_WD_M4_M2 + 0U, // PseudoVAMOANDEI32_WD_M4_M2_MASK + 0U, // PseudoVAMOANDEI32_WD_M4_M4 + 0U, // PseudoVAMOANDEI32_WD_M4_M4_MASK + 0U, // PseudoVAMOANDEI32_WD_M8_M4 + 0U, // PseudoVAMOANDEI32_WD_M8_M4_MASK + 0U, // PseudoVAMOANDEI32_WD_M8_M8 + 0U, // PseudoVAMOANDEI32_WD_M8_M8_MASK + 0U, // PseudoVAMOANDEI32_WD_MF2_MF2 + 0U, // PseudoVAMOANDEI32_WD_MF2_MF2_MASK + 0U, // PseudoVAMOANDEI64_WD_M1_M1 + 0U, // PseudoVAMOANDEI64_WD_M1_M1_MASK + 0U, // PseudoVAMOANDEI64_WD_M1_M2 + 0U, // PseudoVAMOANDEI64_WD_M1_M2_MASK + 0U, // PseudoVAMOANDEI64_WD_M2_M2 + 0U, // PseudoVAMOANDEI64_WD_M2_M2_MASK + 0U, // PseudoVAMOANDEI64_WD_M2_M4 + 0U, // PseudoVAMOANDEI64_WD_M2_M4_MASK + 0U, // PseudoVAMOANDEI64_WD_M4_M4 + 0U, // PseudoVAMOANDEI64_WD_M4_M4_MASK + 0U, // PseudoVAMOANDEI64_WD_M4_M8 + 0U, // PseudoVAMOANDEI64_WD_M4_M8_MASK + 0U, // PseudoVAMOANDEI64_WD_M8_M8 + 0U, // PseudoVAMOANDEI64_WD_M8_M8_MASK + 0U, // PseudoVAMOANDEI64_WD_MF2_M1 + 0U, // PseudoVAMOANDEI64_WD_MF2_M1_MASK + 0U, // PseudoVAMOANDEI8_WD_M1_MF4 + 0U, // PseudoVAMOANDEI8_WD_M1_MF4_MASK + 0U, // PseudoVAMOANDEI8_WD_M1_MF8 + 0U, // PseudoVAMOANDEI8_WD_M1_MF8_MASK + 0U, // PseudoVAMOANDEI8_WD_M2_MF2 + 0U, // PseudoVAMOANDEI8_WD_M2_MF2_MASK + 0U, // PseudoVAMOANDEI8_WD_M2_MF4 + 0U, // PseudoVAMOANDEI8_WD_M2_MF4_MASK + 0U, // PseudoVAMOANDEI8_WD_M4_M1 + 0U, // PseudoVAMOANDEI8_WD_M4_M1_MASK + 0U, // PseudoVAMOANDEI8_WD_M4_MF2 + 0U, // PseudoVAMOANDEI8_WD_M4_MF2_MASK + 0U, // PseudoVAMOANDEI8_WD_M8_M1 + 0U, // PseudoVAMOANDEI8_WD_M8_M1_MASK + 0U, // PseudoVAMOANDEI8_WD_M8_M2 + 0U, // PseudoVAMOANDEI8_WD_M8_M2_MASK + 0U, // PseudoVAMOANDEI8_WD_MF2_MF8 + 0U, // PseudoVAMOANDEI8_WD_MF2_MF8_MASK + 0U, // PseudoVAMOMAXEI16_WD_M1_MF2 + 0U, // PseudoVAMOMAXEI16_WD_M1_MF2_MASK + 0U, // PseudoVAMOMAXEI16_WD_M1_MF4 + 0U, // PseudoVAMOMAXEI16_WD_M1_MF4_MASK + 0U, // PseudoVAMOMAXEI16_WD_M2_M1 + 0U, // PseudoVAMOMAXEI16_WD_M2_M1_MASK + 0U, // PseudoVAMOMAXEI16_WD_M2_MF2 + 0U, // PseudoVAMOMAXEI16_WD_M2_MF2_MASK + 0U, // PseudoVAMOMAXEI16_WD_M4_M1 + 0U, // PseudoVAMOMAXEI16_WD_M4_M1_MASK + 0U, // PseudoVAMOMAXEI16_WD_M4_M2 + 0U, // PseudoVAMOMAXEI16_WD_M4_M2_MASK + 0U, // PseudoVAMOMAXEI16_WD_M8_M2 + 0U, // PseudoVAMOMAXEI16_WD_M8_M2_MASK + 0U, // PseudoVAMOMAXEI16_WD_M8_M4 + 0U, // PseudoVAMOMAXEI16_WD_M8_M4_MASK + 0U, // PseudoVAMOMAXEI16_WD_MF2_MF4 + 0U, // PseudoVAMOMAXEI16_WD_MF2_MF4_MASK + 0U, // PseudoVAMOMAXEI32_WD_M1_M1 + 0U, // PseudoVAMOMAXEI32_WD_M1_M1_MASK + 0U, // PseudoVAMOMAXEI32_WD_M1_MF2 + 0U, // PseudoVAMOMAXEI32_WD_M1_MF2_MASK + 0U, // PseudoVAMOMAXEI32_WD_M2_M1 + 0U, // PseudoVAMOMAXEI32_WD_M2_M1_MASK + 0U, // PseudoVAMOMAXEI32_WD_M2_M2 + 0U, // PseudoVAMOMAXEI32_WD_M2_M2_MASK + 0U, // PseudoVAMOMAXEI32_WD_M4_M2 + 0U, // PseudoVAMOMAXEI32_WD_M4_M2_MASK + 0U, // PseudoVAMOMAXEI32_WD_M4_M4 + 0U, // PseudoVAMOMAXEI32_WD_M4_M4_MASK + 0U, // PseudoVAMOMAXEI32_WD_M8_M4 + 0U, // PseudoVAMOMAXEI32_WD_M8_M4_MASK + 0U, // PseudoVAMOMAXEI32_WD_M8_M8 + 0U, // PseudoVAMOMAXEI32_WD_M8_M8_MASK + 0U, // PseudoVAMOMAXEI32_WD_MF2_MF2 + 0U, // PseudoVAMOMAXEI32_WD_MF2_MF2_MASK + 0U, // PseudoVAMOMAXEI64_WD_M1_M1 + 0U, // PseudoVAMOMAXEI64_WD_M1_M1_MASK + 0U, // PseudoVAMOMAXEI64_WD_M1_M2 + 0U, // PseudoVAMOMAXEI64_WD_M1_M2_MASK + 0U, // PseudoVAMOMAXEI64_WD_M2_M2 + 0U, // PseudoVAMOMAXEI64_WD_M2_M2_MASK + 0U, // PseudoVAMOMAXEI64_WD_M2_M4 + 0U, // PseudoVAMOMAXEI64_WD_M2_M4_MASK + 0U, // PseudoVAMOMAXEI64_WD_M4_M4 + 0U, // PseudoVAMOMAXEI64_WD_M4_M4_MASK + 0U, // PseudoVAMOMAXEI64_WD_M4_M8 + 0U, // PseudoVAMOMAXEI64_WD_M4_M8_MASK + 0U, // PseudoVAMOMAXEI64_WD_M8_M8 + 0U, // PseudoVAMOMAXEI64_WD_M8_M8_MASK + 0U, // PseudoVAMOMAXEI64_WD_MF2_M1 + 0U, // PseudoVAMOMAXEI64_WD_MF2_M1_MASK + 0U, // PseudoVAMOMAXEI8_WD_M1_MF4 + 0U, // PseudoVAMOMAXEI8_WD_M1_MF4_MASK + 0U, // PseudoVAMOMAXEI8_WD_M1_MF8 + 0U, // PseudoVAMOMAXEI8_WD_M1_MF8_MASK + 0U, // PseudoVAMOMAXEI8_WD_M2_MF2 + 0U, // PseudoVAMOMAXEI8_WD_M2_MF2_MASK + 0U, // PseudoVAMOMAXEI8_WD_M2_MF4 + 0U, // PseudoVAMOMAXEI8_WD_M2_MF4_MASK + 0U, // PseudoVAMOMAXEI8_WD_M4_M1 + 0U, // PseudoVAMOMAXEI8_WD_M4_M1_MASK + 0U, // PseudoVAMOMAXEI8_WD_M4_MF2 + 0U, // PseudoVAMOMAXEI8_WD_M4_MF2_MASK + 0U, // PseudoVAMOMAXEI8_WD_M8_M1 + 0U, // PseudoVAMOMAXEI8_WD_M8_M1_MASK + 0U, // PseudoVAMOMAXEI8_WD_M8_M2 + 0U, // PseudoVAMOMAXEI8_WD_M8_M2_MASK + 0U, // PseudoVAMOMAXEI8_WD_MF2_MF8 + 0U, // PseudoVAMOMAXEI8_WD_MF2_MF8_MASK + 0U, // PseudoVAMOMAXUEI16_WD_M1_MF2 + 0U, // PseudoVAMOMAXUEI16_WD_M1_MF2_MASK + 0U, // PseudoVAMOMAXUEI16_WD_M1_MF4 + 0U, // PseudoVAMOMAXUEI16_WD_M1_MF4_MASK + 0U, // PseudoVAMOMAXUEI16_WD_M2_M1 + 0U, // PseudoVAMOMAXUEI16_WD_M2_M1_MASK + 0U, // PseudoVAMOMAXUEI16_WD_M2_MF2 + 0U, // PseudoVAMOMAXUEI16_WD_M2_MF2_MASK + 0U, // PseudoVAMOMAXUEI16_WD_M4_M1 + 0U, // PseudoVAMOMAXUEI16_WD_M4_M1_MASK + 0U, // PseudoVAMOMAXUEI16_WD_M4_M2 + 0U, // PseudoVAMOMAXUEI16_WD_M4_M2_MASK + 0U, // PseudoVAMOMAXUEI16_WD_M8_M2 + 0U, // PseudoVAMOMAXUEI16_WD_M8_M2_MASK + 0U, // PseudoVAMOMAXUEI16_WD_M8_M4 + 0U, // PseudoVAMOMAXUEI16_WD_M8_M4_MASK + 0U, // PseudoVAMOMAXUEI16_WD_MF2_MF4 + 0U, // PseudoVAMOMAXUEI16_WD_MF2_MF4_MASK + 0U, // PseudoVAMOMAXUEI32_WD_M1_M1 + 0U, // PseudoVAMOMAXUEI32_WD_M1_M1_MASK + 0U, // PseudoVAMOMAXUEI32_WD_M1_MF2 + 0U, // PseudoVAMOMAXUEI32_WD_M1_MF2_MASK + 0U, // PseudoVAMOMAXUEI32_WD_M2_M1 + 0U, // PseudoVAMOMAXUEI32_WD_M2_M1_MASK + 0U, // PseudoVAMOMAXUEI32_WD_M2_M2 + 0U, // PseudoVAMOMAXUEI32_WD_M2_M2_MASK + 0U, // PseudoVAMOMAXUEI32_WD_M4_M2 + 0U, // PseudoVAMOMAXUEI32_WD_M4_M2_MASK + 0U, // PseudoVAMOMAXUEI32_WD_M4_M4 + 0U, // PseudoVAMOMAXUEI32_WD_M4_M4_MASK + 0U, // PseudoVAMOMAXUEI32_WD_M8_M4 + 0U, // PseudoVAMOMAXUEI32_WD_M8_M4_MASK + 0U, // PseudoVAMOMAXUEI32_WD_M8_M8 + 0U, // PseudoVAMOMAXUEI32_WD_M8_M8_MASK + 0U, // PseudoVAMOMAXUEI32_WD_MF2_MF2 + 0U, // PseudoVAMOMAXUEI32_WD_MF2_MF2_MASK + 0U, // PseudoVAMOMAXUEI64_WD_M1_M1 + 0U, // PseudoVAMOMAXUEI64_WD_M1_M1_MASK + 0U, // PseudoVAMOMAXUEI64_WD_M1_M2 + 0U, // PseudoVAMOMAXUEI64_WD_M1_M2_MASK + 0U, // PseudoVAMOMAXUEI64_WD_M2_M2 + 0U, // PseudoVAMOMAXUEI64_WD_M2_M2_MASK + 0U, // PseudoVAMOMAXUEI64_WD_M2_M4 + 0U, // PseudoVAMOMAXUEI64_WD_M2_M4_MASK + 0U, // PseudoVAMOMAXUEI64_WD_M4_M4 + 0U, // PseudoVAMOMAXUEI64_WD_M4_M4_MASK + 0U, // PseudoVAMOMAXUEI64_WD_M4_M8 + 0U, // PseudoVAMOMAXUEI64_WD_M4_M8_MASK + 0U, // PseudoVAMOMAXUEI64_WD_M8_M8 + 0U, // PseudoVAMOMAXUEI64_WD_M8_M8_MASK + 0U, // PseudoVAMOMAXUEI64_WD_MF2_M1 + 0U, // PseudoVAMOMAXUEI64_WD_MF2_M1_MASK + 0U, // PseudoVAMOMAXUEI8_WD_M1_MF4 + 0U, // PseudoVAMOMAXUEI8_WD_M1_MF4_MASK + 0U, // PseudoVAMOMAXUEI8_WD_M1_MF8 + 0U, // PseudoVAMOMAXUEI8_WD_M1_MF8_MASK + 0U, // PseudoVAMOMAXUEI8_WD_M2_MF2 + 0U, // PseudoVAMOMAXUEI8_WD_M2_MF2_MASK + 0U, // PseudoVAMOMAXUEI8_WD_M2_MF4 + 0U, // PseudoVAMOMAXUEI8_WD_M2_MF4_MASK + 0U, // PseudoVAMOMAXUEI8_WD_M4_M1 + 0U, // PseudoVAMOMAXUEI8_WD_M4_M1_MASK + 0U, // PseudoVAMOMAXUEI8_WD_M4_MF2 + 0U, // PseudoVAMOMAXUEI8_WD_M4_MF2_MASK + 0U, // PseudoVAMOMAXUEI8_WD_M8_M1 + 0U, // PseudoVAMOMAXUEI8_WD_M8_M1_MASK + 0U, // PseudoVAMOMAXUEI8_WD_M8_M2 + 0U, // PseudoVAMOMAXUEI8_WD_M8_M2_MASK + 0U, // PseudoVAMOMAXUEI8_WD_MF2_MF8 + 0U, // PseudoVAMOMAXUEI8_WD_MF2_MF8_MASK + 0U, // PseudoVAMOMINEI16_WD_M1_MF2 + 0U, // PseudoVAMOMINEI16_WD_M1_MF2_MASK + 0U, // PseudoVAMOMINEI16_WD_M1_MF4 + 0U, // PseudoVAMOMINEI16_WD_M1_MF4_MASK + 0U, // PseudoVAMOMINEI16_WD_M2_M1 + 0U, // PseudoVAMOMINEI16_WD_M2_M1_MASK + 0U, // PseudoVAMOMINEI16_WD_M2_MF2 + 0U, // PseudoVAMOMINEI16_WD_M2_MF2_MASK + 0U, // PseudoVAMOMINEI16_WD_M4_M1 + 0U, // PseudoVAMOMINEI16_WD_M4_M1_MASK + 0U, // PseudoVAMOMINEI16_WD_M4_M2 + 0U, // PseudoVAMOMINEI16_WD_M4_M2_MASK + 0U, // PseudoVAMOMINEI16_WD_M8_M2 + 0U, // PseudoVAMOMINEI16_WD_M8_M2_MASK + 0U, // PseudoVAMOMINEI16_WD_M8_M4 + 0U, // PseudoVAMOMINEI16_WD_M8_M4_MASK + 0U, // PseudoVAMOMINEI16_WD_MF2_MF4 + 0U, // PseudoVAMOMINEI16_WD_MF2_MF4_MASK + 0U, // PseudoVAMOMINEI32_WD_M1_M1 + 0U, // PseudoVAMOMINEI32_WD_M1_M1_MASK + 0U, // PseudoVAMOMINEI32_WD_M1_MF2 + 0U, // PseudoVAMOMINEI32_WD_M1_MF2_MASK + 0U, // PseudoVAMOMINEI32_WD_M2_M1 + 0U, // PseudoVAMOMINEI32_WD_M2_M1_MASK + 0U, // PseudoVAMOMINEI32_WD_M2_M2 + 0U, // PseudoVAMOMINEI32_WD_M2_M2_MASK + 0U, // PseudoVAMOMINEI32_WD_M4_M2 + 0U, // PseudoVAMOMINEI32_WD_M4_M2_MASK + 0U, // PseudoVAMOMINEI32_WD_M4_M4 + 0U, // PseudoVAMOMINEI32_WD_M4_M4_MASK + 0U, // PseudoVAMOMINEI32_WD_M8_M4 + 0U, // PseudoVAMOMINEI32_WD_M8_M4_MASK + 0U, // PseudoVAMOMINEI32_WD_M8_M8 + 0U, // PseudoVAMOMINEI32_WD_M8_M8_MASK + 0U, // PseudoVAMOMINEI32_WD_MF2_MF2 + 0U, // PseudoVAMOMINEI32_WD_MF2_MF2_MASK + 0U, // PseudoVAMOMINEI64_WD_M1_M1 + 0U, // PseudoVAMOMINEI64_WD_M1_M1_MASK + 0U, // PseudoVAMOMINEI64_WD_M1_M2 + 0U, // PseudoVAMOMINEI64_WD_M1_M2_MASK + 0U, // PseudoVAMOMINEI64_WD_M2_M2 + 0U, // PseudoVAMOMINEI64_WD_M2_M2_MASK + 0U, // PseudoVAMOMINEI64_WD_M2_M4 + 0U, // PseudoVAMOMINEI64_WD_M2_M4_MASK + 0U, // PseudoVAMOMINEI64_WD_M4_M4 + 0U, // PseudoVAMOMINEI64_WD_M4_M4_MASK + 0U, // PseudoVAMOMINEI64_WD_M4_M8 + 0U, // PseudoVAMOMINEI64_WD_M4_M8_MASK + 0U, // PseudoVAMOMINEI64_WD_M8_M8 + 0U, // PseudoVAMOMINEI64_WD_M8_M8_MASK + 0U, // PseudoVAMOMINEI64_WD_MF2_M1 + 0U, // PseudoVAMOMINEI64_WD_MF2_M1_MASK + 0U, // PseudoVAMOMINEI8_WD_M1_MF4 + 0U, // PseudoVAMOMINEI8_WD_M1_MF4_MASK + 0U, // PseudoVAMOMINEI8_WD_M1_MF8 + 0U, // PseudoVAMOMINEI8_WD_M1_MF8_MASK + 0U, // PseudoVAMOMINEI8_WD_M2_MF2 + 0U, // PseudoVAMOMINEI8_WD_M2_MF2_MASK + 0U, // PseudoVAMOMINEI8_WD_M2_MF4 + 0U, // PseudoVAMOMINEI8_WD_M2_MF4_MASK + 0U, // PseudoVAMOMINEI8_WD_M4_M1 + 0U, // PseudoVAMOMINEI8_WD_M4_M1_MASK + 0U, // PseudoVAMOMINEI8_WD_M4_MF2 + 0U, // PseudoVAMOMINEI8_WD_M4_MF2_MASK + 0U, // PseudoVAMOMINEI8_WD_M8_M1 + 0U, // PseudoVAMOMINEI8_WD_M8_M1_MASK + 0U, // PseudoVAMOMINEI8_WD_M8_M2 + 0U, // PseudoVAMOMINEI8_WD_M8_M2_MASK + 0U, // PseudoVAMOMINEI8_WD_MF2_MF8 + 0U, // PseudoVAMOMINEI8_WD_MF2_MF8_MASK + 0U, // PseudoVAMOMINUEI16_WD_M1_MF2 + 0U, // PseudoVAMOMINUEI16_WD_M1_MF2_MASK + 0U, // PseudoVAMOMINUEI16_WD_M1_MF4 + 0U, // PseudoVAMOMINUEI16_WD_M1_MF4_MASK + 0U, // PseudoVAMOMINUEI16_WD_M2_M1 + 0U, // PseudoVAMOMINUEI16_WD_M2_M1_MASK + 0U, // PseudoVAMOMINUEI16_WD_M2_MF2 + 0U, // PseudoVAMOMINUEI16_WD_M2_MF2_MASK + 0U, // PseudoVAMOMINUEI16_WD_M4_M1 + 0U, // PseudoVAMOMINUEI16_WD_M4_M1_MASK + 0U, // PseudoVAMOMINUEI16_WD_M4_M2 + 0U, // PseudoVAMOMINUEI16_WD_M4_M2_MASK + 0U, // PseudoVAMOMINUEI16_WD_M8_M2 + 0U, // PseudoVAMOMINUEI16_WD_M8_M2_MASK + 0U, // PseudoVAMOMINUEI16_WD_M8_M4 + 0U, // PseudoVAMOMINUEI16_WD_M8_M4_MASK + 0U, // PseudoVAMOMINUEI16_WD_MF2_MF4 + 0U, // PseudoVAMOMINUEI16_WD_MF2_MF4_MASK + 0U, // PseudoVAMOMINUEI32_WD_M1_M1 + 0U, // PseudoVAMOMINUEI32_WD_M1_M1_MASK + 0U, // PseudoVAMOMINUEI32_WD_M1_MF2 + 0U, // PseudoVAMOMINUEI32_WD_M1_MF2_MASK + 0U, // PseudoVAMOMINUEI32_WD_M2_M1 + 0U, // PseudoVAMOMINUEI32_WD_M2_M1_MASK + 0U, // PseudoVAMOMINUEI32_WD_M2_M2 + 0U, // PseudoVAMOMINUEI32_WD_M2_M2_MASK + 0U, // PseudoVAMOMINUEI32_WD_M4_M2 + 0U, // PseudoVAMOMINUEI32_WD_M4_M2_MASK + 0U, // PseudoVAMOMINUEI32_WD_M4_M4 + 0U, // PseudoVAMOMINUEI32_WD_M4_M4_MASK + 0U, // PseudoVAMOMINUEI32_WD_M8_M4 + 0U, // PseudoVAMOMINUEI32_WD_M8_M4_MASK + 0U, // PseudoVAMOMINUEI32_WD_M8_M8 + 0U, // PseudoVAMOMINUEI32_WD_M8_M8_MASK + 0U, // PseudoVAMOMINUEI32_WD_MF2_MF2 + 0U, // PseudoVAMOMINUEI32_WD_MF2_MF2_MASK + 0U, // PseudoVAMOMINUEI64_WD_M1_M1 + 0U, // PseudoVAMOMINUEI64_WD_M1_M1_MASK + 0U, // PseudoVAMOMINUEI64_WD_M1_M2 + 0U, // PseudoVAMOMINUEI64_WD_M1_M2_MASK + 0U, // PseudoVAMOMINUEI64_WD_M2_M2 + 0U, // PseudoVAMOMINUEI64_WD_M2_M2_MASK + 0U, // PseudoVAMOMINUEI64_WD_M2_M4 + 0U, // PseudoVAMOMINUEI64_WD_M2_M4_MASK + 0U, // PseudoVAMOMINUEI64_WD_M4_M4 + 0U, // PseudoVAMOMINUEI64_WD_M4_M4_MASK + 0U, // PseudoVAMOMINUEI64_WD_M4_M8 + 0U, // PseudoVAMOMINUEI64_WD_M4_M8_MASK + 0U, // PseudoVAMOMINUEI64_WD_M8_M8 + 0U, // PseudoVAMOMINUEI64_WD_M8_M8_MASK + 0U, // PseudoVAMOMINUEI64_WD_MF2_M1 + 0U, // PseudoVAMOMINUEI64_WD_MF2_M1_MASK + 0U, // PseudoVAMOMINUEI8_WD_M1_MF4 + 0U, // PseudoVAMOMINUEI8_WD_M1_MF4_MASK + 0U, // PseudoVAMOMINUEI8_WD_M1_MF8 + 0U, // PseudoVAMOMINUEI8_WD_M1_MF8_MASK + 0U, // PseudoVAMOMINUEI8_WD_M2_MF2 + 0U, // PseudoVAMOMINUEI8_WD_M2_MF2_MASK + 0U, // PseudoVAMOMINUEI8_WD_M2_MF4 + 0U, // PseudoVAMOMINUEI8_WD_M2_MF4_MASK + 0U, // PseudoVAMOMINUEI8_WD_M4_M1 + 0U, // PseudoVAMOMINUEI8_WD_M4_M1_MASK + 0U, // PseudoVAMOMINUEI8_WD_M4_MF2 + 0U, // PseudoVAMOMINUEI8_WD_M4_MF2_MASK + 0U, // PseudoVAMOMINUEI8_WD_M8_M1 + 0U, // PseudoVAMOMINUEI8_WD_M8_M1_MASK + 0U, // PseudoVAMOMINUEI8_WD_M8_M2 + 0U, // PseudoVAMOMINUEI8_WD_M8_M2_MASK + 0U, // PseudoVAMOMINUEI8_WD_MF2_MF8 + 0U, // PseudoVAMOMINUEI8_WD_MF2_MF8_MASK + 0U, // PseudoVAMOOREI16_WD_M1_MF2 + 0U, // PseudoVAMOOREI16_WD_M1_MF2_MASK + 0U, // PseudoVAMOOREI16_WD_M1_MF4 + 0U, // PseudoVAMOOREI16_WD_M1_MF4_MASK + 0U, // PseudoVAMOOREI16_WD_M2_M1 + 0U, // PseudoVAMOOREI16_WD_M2_M1_MASK + 0U, // PseudoVAMOOREI16_WD_M2_MF2 + 0U, // PseudoVAMOOREI16_WD_M2_MF2_MASK + 0U, // PseudoVAMOOREI16_WD_M4_M1 + 0U, // PseudoVAMOOREI16_WD_M4_M1_MASK + 0U, // PseudoVAMOOREI16_WD_M4_M2 + 0U, // PseudoVAMOOREI16_WD_M4_M2_MASK + 0U, // PseudoVAMOOREI16_WD_M8_M2 + 0U, // PseudoVAMOOREI16_WD_M8_M2_MASK + 0U, // PseudoVAMOOREI16_WD_M8_M4 + 0U, // PseudoVAMOOREI16_WD_M8_M4_MASK + 0U, // PseudoVAMOOREI16_WD_MF2_MF4 + 0U, // PseudoVAMOOREI16_WD_MF2_MF4_MASK + 0U, // PseudoVAMOOREI32_WD_M1_M1 + 0U, // PseudoVAMOOREI32_WD_M1_M1_MASK + 0U, // PseudoVAMOOREI32_WD_M1_MF2 + 0U, // PseudoVAMOOREI32_WD_M1_MF2_MASK + 0U, // PseudoVAMOOREI32_WD_M2_M1 + 0U, // PseudoVAMOOREI32_WD_M2_M1_MASK + 0U, // PseudoVAMOOREI32_WD_M2_M2 + 0U, // PseudoVAMOOREI32_WD_M2_M2_MASK + 0U, // PseudoVAMOOREI32_WD_M4_M2 + 0U, // PseudoVAMOOREI32_WD_M4_M2_MASK + 0U, // PseudoVAMOOREI32_WD_M4_M4 + 0U, // PseudoVAMOOREI32_WD_M4_M4_MASK + 0U, // PseudoVAMOOREI32_WD_M8_M4 + 0U, // PseudoVAMOOREI32_WD_M8_M4_MASK + 0U, // PseudoVAMOOREI32_WD_M8_M8 + 0U, // PseudoVAMOOREI32_WD_M8_M8_MASK + 0U, // PseudoVAMOOREI32_WD_MF2_MF2 + 0U, // PseudoVAMOOREI32_WD_MF2_MF2_MASK + 0U, // PseudoVAMOOREI64_WD_M1_M1 + 0U, // PseudoVAMOOREI64_WD_M1_M1_MASK + 0U, // PseudoVAMOOREI64_WD_M1_M2 + 0U, // PseudoVAMOOREI64_WD_M1_M2_MASK + 0U, // PseudoVAMOOREI64_WD_M2_M2 + 0U, // PseudoVAMOOREI64_WD_M2_M2_MASK + 0U, // PseudoVAMOOREI64_WD_M2_M4 + 0U, // PseudoVAMOOREI64_WD_M2_M4_MASK + 0U, // PseudoVAMOOREI64_WD_M4_M4 + 0U, // PseudoVAMOOREI64_WD_M4_M4_MASK + 0U, // PseudoVAMOOREI64_WD_M4_M8 + 0U, // PseudoVAMOOREI64_WD_M4_M8_MASK + 0U, // PseudoVAMOOREI64_WD_M8_M8 + 0U, // PseudoVAMOOREI64_WD_M8_M8_MASK + 0U, // PseudoVAMOOREI64_WD_MF2_M1 + 0U, // PseudoVAMOOREI64_WD_MF2_M1_MASK + 0U, // PseudoVAMOOREI8_WD_M1_MF4 + 0U, // PseudoVAMOOREI8_WD_M1_MF4_MASK + 0U, // PseudoVAMOOREI8_WD_M1_MF8 + 0U, // PseudoVAMOOREI8_WD_M1_MF8_MASK + 0U, // PseudoVAMOOREI8_WD_M2_MF2 + 0U, // PseudoVAMOOREI8_WD_M2_MF2_MASK + 0U, // PseudoVAMOOREI8_WD_M2_MF4 + 0U, // PseudoVAMOOREI8_WD_M2_MF4_MASK + 0U, // PseudoVAMOOREI8_WD_M4_M1 + 0U, // PseudoVAMOOREI8_WD_M4_M1_MASK + 0U, // PseudoVAMOOREI8_WD_M4_MF2 + 0U, // PseudoVAMOOREI8_WD_M4_MF2_MASK + 0U, // PseudoVAMOOREI8_WD_M8_M1 + 0U, // PseudoVAMOOREI8_WD_M8_M1_MASK + 0U, // PseudoVAMOOREI8_WD_M8_M2 + 0U, // PseudoVAMOOREI8_WD_M8_M2_MASK + 0U, // PseudoVAMOOREI8_WD_MF2_MF8 + 0U, // PseudoVAMOOREI8_WD_MF2_MF8_MASK + 0U, // PseudoVAMOSWAPEI16_WD_M1_MF2 + 0U, // PseudoVAMOSWAPEI16_WD_M1_MF2_MASK + 0U, // PseudoVAMOSWAPEI16_WD_M1_MF4 + 0U, // PseudoVAMOSWAPEI16_WD_M1_MF4_MASK + 0U, // PseudoVAMOSWAPEI16_WD_M2_M1 + 0U, // PseudoVAMOSWAPEI16_WD_M2_M1_MASK + 0U, // PseudoVAMOSWAPEI16_WD_M2_MF2 + 0U, // PseudoVAMOSWAPEI16_WD_M2_MF2_MASK + 0U, // PseudoVAMOSWAPEI16_WD_M4_M1 + 0U, // PseudoVAMOSWAPEI16_WD_M4_M1_MASK + 0U, // PseudoVAMOSWAPEI16_WD_M4_M2 + 0U, // PseudoVAMOSWAPEI16_WD_M4_M2_MASK + 0U, // PseudoVAMOSWAPEI16_WD_M8_M2 + 0U, // PseudoVAMOSWAPEI16_WD_M8_M2_MASK + 0U, // PseudoVAMOSWAPEI16_WD_M8_M4 + 0U, // PseudoVAMOSWAPEI16_WD_M8_M4_MASK + 0U, // PseudoVAMOSWAPEI16_WD_MF2_MF4 + 0U, // PseudoVAMOSWAPEI16_WD_MF2_MF4_MASK + 0U, // PseudoVAMOSWAPEI32_WD_M1_M1 + 0U, // PseudoVAMOSWAPEI32_WD_M1_M1_MASK + 0U, // PseudoVAMOSWAPEI32_WD_M1_MF2 + 0U, // PseudoVAMOSWAPEI32_WD_M1_MF2_MASK + 0U, // PseudoVAMOSWAPEI32_WD_M2_M1 + 0U, // PseudoVAMOSWAPEI32_WD_M2_M1_MASK + 0U, // PseudoVAMOSWAPEI32_WD_M2_M2 + 0U, // PseudoVAMOSWAPEI32_WD_M2_M2_MASK + 0U, // PseudoVAMOSWAPEI32_WD_M4_M2 + 0U, // PseudoVAMOSWAPEI32_WD_M4_M2_MASK + 0U, // PseudoVAMOSWAPEI32_WD_M4_M4 + 0U, // PseudoVAMOSWAPEI32_WD_M4_M4_MASK + 0U, // PseudoVAMOSWAPEI32_WD_M8_M4 + 0U, // PseudoVAMOSWAPEI32_WD_M8_M4_MASK + 0U, // PseudoVAMOSWAPEI32_WD_M8_M8 + 0U, // PseudoVAMOSWAPEI32_WD_M8_M8_MASK + 0U, // PseudoVAMOSWAPEI32_WD_MF2_MF2 + 0U, // PseudoVAMOSWAPEI32_WD_MF2_MF2_MASK + 0U, // PseudoVAMOSWAPEI64_WD_M1_M1 + 0U, // PseudoVAMOSWAPEI64_WD_M1_M1_MASK + 0U, // PseudoVAMOSWAPEI64_WD_M1_M2 + 0U, // PseudoVAMOSWAPEI64_WD_M1_M2_MASK + 0U, // PseudoVAMOSWAPEI64_WD_M2_M2 + 0U, // PseudoVAMOSWAPEI64_WD_M2_M2_MASK + 0U, // PseudoVAMOSWAPEI64_WD_M2_M4 + 0U, // PseudoVAMOSWAPEI64_WD_M2_M4_MASK + 0U, // PseudoVAMOSWAPEI64_WD_M4_M4 + 0U, // PseudoVAMOSWAPEI64_WD_M4_M4_MASK + 0U, // PseudoVAMOSWAPEI64_WD_M4_M8 + 0U, // PseudoVAMOSWAPEI64_WD_M4_M8_MASK + 0U, // PseudoVAMOSWAPEI64_WD_M8_M8 + 0U, // PseudoVAMOSWAPEI64_WD_M8_M8_MASK + 0U, // PseudoVAMOSWAPEI64_WD_MF2_M1 + 0U, // PseudoVAMOSWAPEI64_WD_MF2_M1_MASK + 0U, // PseudoVAMOSWAPEI8_WD_M1_MF4 + 0U, // PseudoVAMOSWAPEI8_WD_M1_MF4_MASK + 0U, // PseudoVAMOSWAPEI8_WD_M1_MF8 + 0U, // PseudoVAMOSWAPEI8_WD_M1_MF8_MASK + 0U, // PseudoVAMOSWAPEI8_WD_M2_MF2 + 0U, // PseudoVAMOSWAPEI8_WD_M2_MF2_MASK + 0U, // PseudoVAMOSWAPEI8_WD_M2_MF4 + 0U, // PseudoVAMOSWAPEI8_WD_M2_MF4_MASK + 0U, // PseudoVAMOSWAPEI8_WD_M4_M1 + 0U, // PseudoVAMOSWAPEI8_WD_M4_M1_MASK + 0U, // PseudoVAMOSWAPEI8_WD_M4_MF2 + 0U, // PseudoVAMOSWAPEI8_WD_M4_MF2_MASK + 0U, // PseudoVAMOSWAPEI8_WD_M8_M1 + 0U, // PseudoVAMOSWAPEI8_WD_M8_M1_MASK + 0U, // PseudoVAMOSWAPEI8_WD_M8_M2 + 0U, // PseudoVAMOSWAPEI8_WD_M8_M2_MASK + 0U, // PseudoVAMOSWAPEI8_WD_MF2_MF8 + 0U, // PseudoVAMOSWAPEI8_WD_MF2_MF8_MASK + 0U, // PseudoVAMOXOREI16_WD_M1_MF2 + 0U, // PseudoVAMOXOREI16_WD_M1_MF2_MASK + 0U, // PseudoVAMOXOREI16_WD_M1_MF4 + 0U, // PseudoVAMOXOREI16_WD_M1_MF4_MASK + 0U, // PseudoVAMOXOREI16_WD_M2_M1 + 0U, // PseudoVAMOXOREI16_WD_M2_M1_MASK + 0U, // PseudoVAMOXOREI16_WD_M2_MF2 + 0U, // PseudoVAMOXOREI16_WD_M2_MF2_MASK + 0U, // PseudoVAMOXOREI16_WD_M4_M1 + 0U, // PseudoVAMOXOREI16_WD_M4_M1_MASK + 0U, // PseudoVAMOXOREI16_WD_M4_M2 + 0U, // PseudoVAMOXOREI16_WD_M4_M2_MASK + 0U, // PseudoVAMOXOREI16_WD_M8_M2 + 0U, // PseudoVAMOXOREI16_WD_M8_M2_MASK + 0U, // PseudoVAMOXOREI16_WD_M8_M4 + 0U, // PseudoVAMOXOREI16_WD_M8_M4_MASK + 0U, // PseudoVAMOXOREI16_WD_MF2_MF4 + 0U, // PseudoVAMOXOREI16_WD_MF2_MF4_MASK + 0U, // PseudoVAMOXOREI32_WD_M1_M1 + 0U, // PseudoVAMOXOREI32_WD_M1_M1_MASK + 0U, // PseudoVAMOXOREI32_WD_M1_MF2 + 0U, // PseudoVAMOXOREI32_WD_M1_MF2_MASK + 0U, // PseudoVAMOXOREI32_WD_M2_M1 + 0U, // PseudoVAMOXOREI32_WD_M2_M1_MASK + 0U, // PseudoVAMOXOREI32_WD_M2_M2 + 0U, // PseudoVAMOXOREI32_WD_M2_M2_MASK + 0U, // PseudoVAMOXOREI32_WD_M4_M2 + 0U, // PseudoVAMOXOREI32_WD_M4_M2_MASK + 0U, // PseudoVAMOXOREI32_WD_M4_M4 + 0U, // PseudoVAMOXOREI32_WD_M4_M4_MASK + 0U, // PseudoVAMOXOREI32_WD_M8_M4 + 0U, // PseudoVAMOXOREI32_WD_M8_M4_MASK + 0U, // PseudoVAMOXOREI32_WD_M8_M8 + 0U, // PseudoVAMOXOREI32_WD_M8_M8_MASK + 0U, // PseudoVAMOXOREI32_WD_MF2_MF2 + 0U, // PseudoVAMOXOREI32_WD_MF2_MF2_MASK + 0U, // PseudoVAMOXOREI64_WD_M1_M1 + 0U, // PseudoVAMOXOREI64_WD_M1_M1_MASK + 0U, // PseudoVAMOXOREI64_WD_M1_M2 + 0U, // PseudoVAMOXOREI64_WD_M1_M2_MASK + 0U, // PseudoVAMOXOREI64_WD_M2_M2 + 0U, // PseudoVAMOXOREI64_WD_M2_M2_MASK + 0U, // PseudoVAMOXOREI64_WD_M2_M4 + 0U, // PseudoVAMOXOREI64_WD_M2_M4_MASK + 0U, // PseudoVAMOXOREI64_WD_M4_M4 + 0U, // PseudoVAMOXOREI64_WD_M4_M4_MASK + 0U, // PseudoVAMOXOREI64_WD_M4_M8 + 0U, // PseudoVAMOXOREI64_WD_M4_M8_MASK + 0U, // PseudoVAMOXOREI64_WD_M8_M8 + 0U, // PseudoVAMOXOREI64_WD_M8_M8_MASK + 0U, // PseudoVAMOXOREI64_WD_MF2_M1 + 0U, // PseudoVAMOXOREI64_WD_MF2_M1_MASK + 0U, // PseudoVAMOXOREI8_WD_M1_MF4 + 0U, // PseudoVAMOXOREI8_WD_M1_MF4_MASK + 0U, // PseudoVAMOXOREI8_WD_M1_MF8 + 0U, // PseudoVAMOXOREI8_WD_M1_MF8_MASK + 0U, // PseudoVAMOXOREI8_WD_M2_MF2 + 0U, // PseudoVAMOXOREI8_WD_M2_MF2_MASK + 0U, // PseudoVAMOXOREI8_WD_M2_MF4 + 0U, // PseudoVAMOXOREI8_WD_M2_MF4_MASK + 0U, // PseudoVAMOXOREI8_WD_M4_M1 + 0U, // PseudoVAMOXOREI8_WD_M4_M1_MASK + 0U, // PseudoVAMOXOREI8_WD_M4_MF2 + 0U, // PseudoVAMOXOREI8_WD_M4_MF2_MASK + 0U, // PseudoVAMOXOREI8_WD_M8_M1 + 0U, // PseudoVAMOXOREI8_WD_M8_M1_MASK + 0U, // PseudoVAMOXOREI8_WD_M8_M2 + 0U, // PseudoVAMOXOREI8_WD_M8_M2_MASK + 0U, // PseudoVAMOXOREI8_WD_MF2_MF8 + 0U, // PseudoVAMOXOREI8_WD_MF2_MF8_MASK + 0U, // PseudoVAND_VI_M1 + 0U, // PseudoVAND_VI_M1_MASK + 0U, // PseudoVAND_VI_M2 + 0U, // PseudoVAND_VI_M2_MASK + 0U, // PseudoVAND_VI_M4 + 0U, // PseudoVAND_VI_M4_MASK + 0U, // PseudoVAND_VI_M8 + 0U, // PseudoVAND_VI_M8_MASK + 0U, // PseudoVAND_VI_MF2 + 0U, // PseudoVAND_VI_MF2_MASK + 0U, // PseudoVAND_VI_MF4 + 0U, // PseudoVAND_VI_MF4_MASK + 0U, // PseudoVAND_VI_MF8 + 0U, // PseudoVAND_VI_MF8_MASK + 0U, // PseudoVAND_VV_M1 + 0U, // PseudoVAND_VV_M1_MASK + 0U, // PseudoVAND_VV_M2 + 0U, // PseudoVAND_VV_M2_MASK + 0U, // PseudoVAND_VV_M4 + 0U, // PseudoVAND_VV_M4_MASK + 0U, // PseudoVAND_VV_M8 + 0U, // PseudoVAND_VV_M8_MASK + 0U, // PseudoVAND_VV_MF2 + 0U, // PseudoVAND_VV_MF2_MASK + 0U, // PseudoVAND_VV_MF4 + 0U, // PseudoVAND_VV_MF4_MASK + 0U, // PseudoVAND_VV_MF8 + 0U, // PseudoVAND_VV_MF8_MASK + 0U, // PseudoVAND_VX_M1 + 0U, // PseudoVAND_VX_M1_MASK + 0U, // PseudoVAND_VX_M2 + 0U, // PseudoVAND_VX_M2_MASK + 0U, // PseudoVAND_VX_M4 + 0U, // PseudoVAND_VX_M4_MASK + 0U, // PseudoVAND_VX_M8 + 0U, // PseudoVAND_VX_M8_MASK + 0U, // PseudoVAND_VX_MF2 + 0U, // PseudoVAND_VX_MF2_MASK + 0U, // PseudoVAND_VX_MF4 + 0U, // PseudoVAND_VX_MF4_MASK + 0U, // PseudoVAND_VX_MF8 + 0U, // PseudoVAND_VX_MF8_MASK + 0U, // PseudoVASUBU_VV_M1 + 0U, // PseudoVASUBU_VV_M1_MASK + 0U, // PseudoVASUBU_VV_M2 + 0U, // PseudoVASUBU_VV_M2_MASK + 0U, // PseudoVASUBU_VV_M4 + 0U, // PseudoVASUBU_VV_M4_MASK + 0U, // PseudoVASUBU_VV_M8 + 0U, // PseudoVASUBU_VV_M8_MASK + 0U, // PseudoVASUBU_VV_MF2 + 0U, // PseudoVASUBU_VV_MF2_MASK + 0U, // PseudoVASUBU_VV_MF4 + 0U, // PseudoVASUBU_VV_MF4_MASK + 0U, // PseudoVASUBU_VV_MF8 + 0U, // PseudoVASUBU_VV_MF8_MASK + 0U, // PseudoVASUBU_VX_M1 + 0U, // PseudoVASUBU_VX_M1_MASK + 0U, // PseudoVASUBU_VX_M2 + 0U, // PseudoVASUBU_VX_M2_MASK + 0U, // PseudoVASUBU_VX_M4 + 0U, // PseudoVASUBU_VX_M4_MASK + 0U, // PseudoVASUBU_VX_M8 + 0U, // PseudoVASUBU_VX_M8_MASK + 0U, // PseudoVASUBU_VX_MF2 + 0U, // PseudoVASUBU_VX_MF2_MASK + 0U, // PseudoVASUBU_VX_MF4 + 0U, // PseudoVASUBU_VX_MF4_MASK + 0U, // PseudoVASUBU_VX_MF8 + 0U, // PseudoVASUBU_VX_MF8_MASK + 0U, // PseudoVASUB_VV_M1 + 0U, // PseudoVASUB_VV_M1_MASK + 0U, // PseudoVASUB_VV_M2 + 0U, // PseudoVASUB_VV_M2_MASK + 0U, // PseudoVASUB_VV_M4 + 0U, // PseudoVASUB_VV_M4_MASK + 0U, // PseudoVASUB_VV_M8 + 0U, // PseudoVASUB_VV_M8_MASK + 0U, // PseudoVASUB_VV_MF2 + 0U, // PseudoVASUB_VV_MF2_MASK + 0U, // PseudoVASUB_VV_MF4 + 0U, // PseudoVASUB_VV_MF4_MASK + 0U, // PseudoVASUB_VV_MF8 + 0U, // PseudoVASUB_VV_MF8_MASK + 0U, // PseudoVASUB_VX_M1 + 0U, // PseudoVASUB_VX_M1_MASK + 0U, // PseudoVASUB_VX_M2 + 0U, // PseudoVASUB_VX_M2_MASK + 0U, // PseudoVASUB_VX_M4 + 0U, // PseudoVASUB_VX_M4_MASK + 0U, // PseudoVASUB_VX_M8 + 0U, // PseudoVASUB_VX_M8_MASK + 0U, // PseudoVASUB_VX_MF2 + 0U, // PseudoVASUB_VX_MF2_MASK + 0U, // PseudoVASUB_VX_MF4 + 0U, // PseudoVASUB_VX_MF4_MASK + 0U, // PseudoVASUB_VX_MF8 + 0U, // PseudoVASUB_VX_MF8_MASK + 0U, // PseudoVCOMPRESS_VM_M1 + 0U, // PseudoVCOMPRESS_VM_M2 + 0U, // PseudoVCOMPRESS_VM_M4 + 0U, // PseudoVCOMPRESS_VM_M8 + 0U, // PseudoVCOMPRESS_VM_MF2 + 0U, // PseudoVCOMPRESS_VM_MF4 + 0U, // PseudoVCOMPRESS_VM_MF8 + 0U, // PseudoVCPOP_M_B1 + 0U, // PseudoVCPOP_M_B16 + 0U, // PseudoVCPOP_M_B16_MASK + 0U, // PseudoVCPOP_M_B1_MASK + 0U, // PseudoVCPOP_M_B2 + 0U, // PseudoVCPOP_M_B2_MASK + 0U, // PseudoVCPOP_M_B32 + 0U, // PseudoVCPOP_M_B32_MASK + 0U, // PseudoVCPOP_M_B4 + 0U, // PseudoVCPOP_M_B4_MASK + 0U, // PseudoVCPOP_M_B64 + 0U, // PseudoVCPOP_M_B64_MASK + 0U, // PseudoVCPOP_M_B8 + 0U, // PseudoVCPOP_M_B8_MASK + 0U, // PseudoVDIVU_VV_M1 + 0U, // PseudoVDIVU_VV_M1_MASK + 0U, // PseudoVDIVU_VV_M2 + 0U, // PseudoVDIVU_VV_M2_MASK + 0U, // PseudoVDIVU_VV_M4 + 0U, // PseudoVDIVU_VV_M4_MASK + 0U, // PseudoVDIVU_VV_M8 + 0U, // PseudoVDIVU_VV_M8_MASK + 0U, // PseudoVDIVU_VV_MF2 + 0U, // PseudoVDIVU_VV_MF2_MASK + 0U, // PseudoVDIVU_VV_MF4 + 0U, // PseudoVDIVU_VV_MF4_MASK + 0U, // PseudoVDIVU_VV_MF8 + 0U, // PseudoVDIVU_VV_MF8_MASK + 0U, // PseudoVDIVU_VX_M1 + 0U, // PseudoVDIVU_VX_M1_MASK + 0U, // PseudoVDIVU_VX_M2 + 0U, // PseudoVDIVU_VX_M2_MASK + 0U, // PseudoVDIVU_VX_M4 + 0U, // PseudoVDIVU_VX_M4_MASK + 0U, // PseudoVDIVU_VX_M8 + 0U, // PseudoVDIVU_VX_M8_MASK + 0U, // PseudoVDIVU_VX_MF2 + 0U, // PseudoVDIVU_VX_MF2_MASK + 0U, // PseudoVDIVU_VX_MF4 + 0U, // PseudoVDIVU_VX_MF4_MASK + 0U, // PseudoVDIVU_VX_MF8 + 0U, // PseudoVDIVU_VX_MF8_MASK + 0U, // PseudoVDIV_VV_M1 + 0U, // PseudoVDIV_VV_M1_MASK + 0U, // PseudoVDIV_VV_M2 + 0U, // PseudoVDIV_VV_M2_MASK + 0U, // PseudoVDIV_VV_M4 + 0U, // PseudoVDIV_VV_M4_MASK + 0U, // PseudoVDIV_VV_M8 + 0U, // PseudoVDIV_VV_M8_MASK + 0U, // PseudoVDIV_VV_MF2 + 0U, // PseudoVDIV_VV_MF2_MASK + 0U, // PseudoVDIV_VV_MF4 + 0U, // PseudoVDIV_VV_MF4_MASK + 0U, // PseudoVDIV_VV_MF8 + 0U, // PseudoVDIV_VV_MF8_MASK + 0U, // PseudoVDIV_VX_M1 + 0U, // PseudoVDIV_VX_M1_MASK + 0U, // PseudoVDIV_VX_M2 + 0U, // PseudoVDIV_VX_M2_MASK + 0U, // PseudoVDIV_VX_M4 + 0U, // PseudoVDIV_VX_M4_MASK + 0U, // PseudoVDIV_VX_M8 + 0U, // PseudoVDIV_VX_M8_MASK + 0U, // PseudoVDIV_VX_MF2 + 0U, // PseudoVDIV_VX_MF2_MASK + 0U, // PseudoVDIV_VX_MF4 + 0U, // PseudoVDIV_VX_MF4_MASK + 0U, // PseudoVDIV_VX_MF8 + 0U, // PseudoVDIV_VX_MF8_MASK + 0U, // PseudoVFADD_VF16_M1 + 0U, // PseudoVFADD_VF16_M1_MASK + 0U, // PseudoVFADD_VF16_M2 + 0U, // PseudoVFADD_VF16_M2_MASK + 0U, // PseudoVFADD_VF16_M4 + 0U, // PseudoVFADD_VF16_M4_MASK + 0U, // PseudoVFADD_VF16_M8 + 0U, // PseudoVFADD_VF16_M8_MASK + 0U, // PseudoVFADD_VF16_MF2 + 0U, // PseudoVFADD_VF16_MF2_MASK + 0U, // PseudoVFADD_VF16_MF4 + 0U, // PseudoVFADD_VF16_MF4_MASK + 0U, // PseudoVFADD_VF16_MF8 + 0U, // PseudoVFADD_VF16_MF8_MASK + 0U, // PseudoVFADD_VF32_M1 + 0U, // PseudoVFADD_VF32_M1_MASK + 0U, // PseudoVFADD_VF32_M2 + 0U, // PseudoVFADD_VF32_M2_MASK + 0U, // PseudoVFADD_VF32_M4 + 0U, // PseudoVFADD_VF32_M4_MASK + 0U, // PseudoVFADD_VF32_M8 + 0U, // PseudoVFADD_VF32_M8_MASK + 0U, // PseudoVFADD_VF32_MF2 + 0U, // PseudoVFADD_VF32_MF2_MASK + 0U, // PseudoVFADD_VF32_MF4 + 0U, // PseudoVFADD_VF32_MF4_MASK + 0U, // PseudoVFADD_VF32_MF8 + 0U, // PseudoVFADD_VF32_MF8_MASK + 0U, // PseudoVFADD_VF64_M1 + 0U, // PseudoVFADD_VF64_M1_MASK + 0U, // PseudoVFADD_VF64_M2 + 0U, // PseudoVFADD_VF64_M2_MASK + 0U, // PseudoVFADD_VF64_M4 + 0U, // PseudoVFADD_VF64_M4_MASK + 0U, // PseudoVFADD_VF64_M8 + 0U, // PseudoVFADD_VF64_M8_MASK + 0U, // PseudoVFADD_VF64_MF2 + 0U, // PseudoVFADD_VF64_MF2_MASK + 0U, // PseudoVFADD_VF64_MF4 + 0U, // PseudoVFADD_VF64_MF4_MASK + 0U, // PseudoVFADD_VF64_MF8 + 0U, // PseudoVFADD_VF64_MF8_MASK + 0U, // PseudoVFADD_VV_M1 + 0U, // PseudoVFADD_VV_M1_MASK + 0U, // PseudoVFADD_VV_M2 + 0U, // PseudoVFADD_VV_M2_MASK + 0U, // PseudoVFADD_VV_M4 + 0U, // PseudoVFADD_VV_M4_MASK + 0U, // PseudoVFADD_VV_M8 + 0U, // PseudoVFADD_VV_M8_MASK + 0U, // PseudoVFADD_VV_MF2 + 0U, // PseudoVFADD_VV_MF2_MASK + 0U, // PseudoVFADD_VV_MF4 + 0U, // PseudoVFADD_VV_MF4_MASK + 0U, // PseudoVFADD_VV_MF8 + 0U, // PseudoVFADD_VV_MF8_MASK + 0U, // PseudoVFCLASS_V_M1 + 0U, // PseudoVFCLASS_V_M1_MASK + 0U, // PseudoVFCLASS_V_M2 + 0U, // PseudoVFCLASS_V_M2_MASK + 0U, // PseudoVFCLASS_V_M4 + 0U, // PseudoVFCLASS_V_M4_MASK + 0U, // PseudoVFCLASS_V_M8 + 0U, // PseudoVFCLASS_V_M8_MASK + 0U, // PseudoVFCLASS_V_MF2 + 0U, // PseudoVFCLASS_V_MF2_MASK + 0U, // PseudoVFCLASS_V_MF4 + 0U, // PseudoVFCLASS_V_MF4_MASK + 0U, // PseudoVFCLASS_V_MF8 + 0U, // PseudoVFCLASS_V_MF8_MASK + 0U, // PseudoVFCVT_F_XU_V_M1 + 0U, // PseudoVFCVT_F_XU_V_M1_MASK + 0U, // PseudoVFCVT_F_XU_V_M2 + 0U, // PseudoVFCVT_F_XU_V_M2_MASK + 0U, // PseudoVFCVT_F_XU_V_M4 + 0U, // PseudoVFCVT_F_XU_V_M4_MASK + 0U, // PseudoVFCVT_F_XU_V_M8 + 0U, // PseudoVFCVT_F_XU_V_M8_MASK + 0U, // PseudoVFCVT_F_XU_V_MF2 + 0U, // PseudoVFCVT_F_XU_V_MF2_MASK + 0U, // PseudoVFCVT_F_XU_V_MF4 + 0U, // PseudoVFCVT_F_XU_V_MF4_MASK + 0U, // PseudoVFCVT_F_XU_V_MF8 + 0U, // PseudoVFCVT_F_XU_V_MF8_MASK + 0U, // PseudoVFCVT_F_X_V_M1 + 0U, // PseudoVFCVT_F_X_V_M1_MASK + 0U, // PseudoVFCVT_F_X_V_M2 + 0U, // PseudoVFCVT_F_X_V_M2_MASK + 0U, // PseudoVFCVT_F_X_V_M4 + 0U, // PseudoVFCVT_F_X_V_M4_MASK + 0U, // PseudoVFCVT_F_X_V_M8 + 0U, // PseudoVFCVT_F_X_V_M8_MASK + 0U, // PseudoVFCVT_F_X_V_MF2 + 0U, // PseudoVFCVT_F_X_V_MF2_MASK + 0U, // PseudoVFCVT_F_X_V_MF4 + 0U, // PseudoVFCVT_F_X_V_MF4_MASK + 0U, // PseudoVFCVT_F_X_V_MF8 + 0U, // PseudoVFCVT_F_X_V_MF8_MASK + 0U, // PseudoVFCVT_RTZ_XU_F_V_M1 + 0U, // PseudoVFCVT_RTZ_XU_F_V_M1_MASK + 0U, // PseudoVFCVT_RTZ_XU_F_V_M2 + 0U, // PseudoVFCVT_RTZ_XU_F_V_M2_MASK + 0U, // PseudoVFCVT_RTZ_XU_F_V_M4 + 0U, // PseudoVFCVT_RTZ_XU_F_V_M4_MASK + 0U, // PseudoVFCVT_RTZ_XU_F_V_M8 + 0U, // PseudoVFCVT_RTZ_XU_F_V_M8_MASK + 0U, // PseudoVFCVT_RTZ_XU_F_V_MF2 + 0U, // PseudoVFCVT_RTZ_XU_F_V_MF2_MASK + 0U, // PseudoVFCVT_RTZ_XU_F_V_MF4 + 0U, // PseudoVFCVT_RTZ_XU_F_V_MF4_MASK + 0U, // PseudoVFCVT_RTZ_XU_F_V_MF8 + 0U, // PseudoVFCVT_RTZ_XU_F_V_MF8_MASK + 0U, // PseudoVFCVT_RTZ_X_F_V_M1 + 0U, // PseudoVFCVT_RTZ_X_F_V_M1_MASK + 0U, // PseudoVFCVT_RTZ_X_F_V_M2 + 0U, // PseudoVFCVT_RTZ_X_F_V_M2_MASK + 0U, // PseudoVFCVT_RTZ_X_F_V_M4 + 0U, // PseudoVFCVT_RTZ_X_F_V_M4_MASK + 0U, // PseudoVFCVT_RTZ_X_F_V_M8 + 0U, // PseudoVFCVT_RTZ_X_F_V_M8_MASK + 0U, // PseudoVFCVT_RTZ_X_F_V_MF2 + 0U, // PseudoVFCVT_RTZ_X_F_V_MF2_MASK + 0U, // PseudoVFCVT_RTZ_X_F_V_MF4 + 0U, // PseudoVFCVT_RTZ_X_F_V_MF4_MASK + 0U, // PseudoVFCVT_RTZ_X_F_V_MF8 + 0U, // PseudoVFCVT_RTZ_X_F_V_MF8_MASK + 0U, // PseudoVFCVT_XU_F_V_M1 + 0U, // PseudoVFCVT_XU_F_V_M1_MASK + 0U, // PseudoVFCVT_XU_F_V_M2 + 0U, // PseudoVFCVT_XU_F_V_M2_MASK + 0U, // PseudoVFCVT_XU_F_V_M4 + 0U, // PseudoVFCVT_XU_F_V_M4_MASK + 0U, // PseudoVFCVT_XU_F_V_M8 + 0U, // PseudoVFCVT_XU_F_V_M8_MASK + 0U, // PseudoVFCVT_XU_F_V_MF2 + 0U, // PseudoVFCVT_XU_F_V_MF2_MASK + 0U, // PseudoVFCVT_XU_F_V_MF4 + 0U, // PseudoVFCVT_XU_F_V_MF4_MASK + 0U, // PseudoVFCVT_XU_F_V_MF8 + 0U, // PseudoVFCVT_XU_F_V_MF8_MASK + 0U, // PseudoVFCVT_X_F_V_M1 + 0U, // PseudoVFCVT_X_F_V_M1_MASK + 0U, // PseudoVFCVT_X_F_V_M2 + 0U, // PseudoVFCVT_X_F_V_M2_MASK + 0U, // PseudoVFCVT_X_F_V_M4 + 0U, // PseudoVFCVT_X_F_V_M4_MASK + 0U, // PseudoVFCVT_X_F_V_M8 + 0U, // PseudoVFCVT_X_F_V_M8_MASK + 0U, // PseudoVFCVT_X_F_V_MF2 + 0U, // PseudoVFCVT_X_F_V_MF2_MASK + 0U, // PseudoVFCVT_X_F_V_MF4 + 0U, // PseudoVFCVT_X_F_V_MF4_MASK + 0U, // PseudoVFCVT_X_F_V_MF8 + 0U, // PseudoVFCVT_X_F_V_MF8_MASK + 0U, // PseudoVFDIV_VF16_M1 + 0U, // PseudoVFDIV_VF16_M1_MASK + 0U, // PseudoVFDIV_VF16_M2 + 0U, // PseudoVFDIV_VF16_M2_MASK + 0U, // PseudoVFDIV_VF16_M4 + 0U, // PseudoVFDIV_VF16_M4_MASK + 0U, // PseudoVFDIV_VF16_M8 + 0U, // PseudoVFDIV_VF16_M8_MASK + 0U, // PseudoVFDIV_VF16_MF2 + 0U, // PseudoVFDIV_VF16_MF2_MASK + 0U, // PseudoVFDIV_VF16_MF4 + 0U, // PseudoVFDIV_VF16_MF4_MASK + 0U, // PseudoVFDIV_VF16_MF8 + 0U, // PseudoVFDIV_VF16_MF8_MASK + 0U, // PseudoVFDIV_VF32_M1 + 0U, // PseudoVFDIV_VF32_M1_MASK + 0U, // PseudoVFDIV_VF32_M2 + 0U, // PseudoVFDIV_VF32_M2_MASK + 0U, // PseudoVFDIV_VF32_M4 + 0U, // PseudoVFDIV_VF32_M4_MASK + 0U, // PseudoVFDIV_VF32_M8 + 0U, // PseudoVFDIV_VF32_M8_MASK + 0U, // PseudoVFDIV_VF32_MF2 + 0U, // PseudoVFDIV_VF32_MF2_MASK + 0U, // PseudoVFDIV_VF32_MF4 + 0U, // PseudoVFDIV_VF32_MF4_MASK + 0U, // PseudoVFDIV_VF32_MF8 + 0U, // PseudoVFDIV_VF32_MF8_MASK + 0U, // PseudoVFDIV_VF64_M1 + 0U, // PseudoVFDIV_VF64_M1_MASK + 0U, // PseudoVFDIV_VF64_M2 + 0U, // PseudoVFDIV_VF64_M2_MASK + 0U, // PseudoVFDIV_VF64_M4 + 0U, // PseudoVFDIV_VF64_M4_MASK + 0U, // PseudoVFDIV_VF64_M8 + 0U, // PseudoVFDIV_VF64_M8_MASK + 0U, // PseudoVFDIV_VF64_MF2 + 0U, // PseudoVFDIV_VF64_MF2_MASK + 0U, // PseudoVFDIV_VF64_MF4 + 0U, // PseudoVFDIV_VF64_MF4_MASK + 0U, // PseudoVFDIV_VF64_MF8 + 0U, // PseudoVFDIV_VF64_MF8_MASK + 0U, // PseudoVFDIV_VV_M1 + 0U, // PseudoVFDIV_VV_M1_MASK + 0U, // PseudoVFDIV_VV_M2 + 0U, // PseudoVFDIV_VV_M2_MASK + 0U, // PseudoVFDIV_VV_M4 + 0U, // PseudoVFDIV_VV_M4_MASK + 0U, // PseudoVFDIV_VV_M8 + 0U, // PseudoVFDIV_VV_M8_MASK + 0U, // PseudoVFDIV_VV_MF2 + 0U, // PseudoVFDIV_VV_MF2_MASK + 0U, // PseudoVFDIV_VV_MF4 + 0U, // PseudoVFDIV_VV_MF4_MASK + 0U, // PseudoVFDIV_VV_MF8 + 0U, // PseudoVFDIV_VV_MF8_MASK + 0U, // PseudoVFIRST_M_B1 + 0U, // PseudoVFIRST_M_B16 + 0U, // PseudoVFIRST_M_B16_MASK + 0U, // PseudoVFIRST_M_B1_MASK + 0U, // PseudoVFIRST_M_B2 + 0U, // PseudoVFIRST_M_B2_MASK + 0U, // PseudoVFIRST_M_B32 + 0U, // PseudoVFIRST_M_B32_MASK + 0U, // PseudoVFIRST_M_B4 + 0U, // PseudoVFIRST_M_B4_MASK + 0U, // PseudoVFIRST_M_B64 + 0U, // PseudoVFIRST_M_B64_MASK + 0U, // PseudoVFIRST_M_B8 + 0U, // PseudoVFIRST_M_B8_MASK + 0U, // PseudoVFMACC_VF16_M1 + 0U, // PseudoVFMACC_VF16_M1_MASK + 0U, // PseudoVFMACC_VF16_M2 + 0U, // PseudoVFMACC_VF16_M2_MASK + 0U, // PseudoVFMACC_VF16_M4 + 0U, // PseudoVFMACC_VF16_M4_MASK + 0U, // PseudoVFMACC_VF16_M8 + 0U, // PseudoVFMACC_VF16_M8_MASK + 0U, // PseudoVFMACC_VF16_MF2 + 0U, // PseudoVFMACC_VF16_MF2_MASK + 0U, // PseudoVFMACC_VF16_MF4 + 0U, // PseudoVFMACC_VF16_MF4_MASK + 0U, // PseudoVFMACC_VF16_MF8 + 0U, // PseudoVFMACC_VF16_MF8_MASK + 0U, // PseudoVFMACC_VF32_M1 + 0U, // PseudoVFMACC_VF32_M1_MASK + 0U, // PseudoVFMACC_VF32_M2 + 0U, // PseudoVFMACC_VF32_M2_MASK + 0U, // PseudoVFMACC_VF32_M4 + 0U, // PseudoVFMACC_VF32_M4_MASK + 0U, // PseudoVFMACC_VF32_M8 + 0U, // PseudoVFMACC_VF32_M8_MASK + 0U, // PseudoVFMACC_VF32_MF2 + 0U, // PseudoVFMACC_VF32_MF2_MASK + 0U, // PseudoVFMACC_VF32_MF4 + 0U, // PseudoVFMACC_VF32_MF4_MASK + 0U, // PseudoVFMACC_VF32_MF8 + 0U, // PseudoVFMACC_VF32_MF8_MASK + 0U, // PseudoVFMACC_VF64_M1 + 0U, // PseudoVFMACC_VF64_M1_MASK + 0U, // PseudoVFMACC_VF64_M2 + 0U, // PseudoVFMACC_VF64_M2_MASK + 0U, // PseudoVFMACC_VF64_M4 + 0U, // PseudoVFMACC_VF64_M4_MASK + 0U, // PseudoVFMACC_VF64_M8 + 0U, // PseudoVFMACC_VF64_M8_MASK + 0U, // PseudoVFMACC_VF64_MF2 + 0U, // PseudoVFMACC_VF64_MF2_MASK + 0U, // PseudoVFMACC_VF64_MF4 + 0U, // PseudoVFMACC_VF64_MF4_MASK + 0U, // PseudoVFMACC_VF64_MF8 + 0U, // PseudoVFMACC_VF64_MF8_MASK + 0U, // PseudoVFMACC_VV_M1 + 0U, // PseudoVFMACC_VV_M1_MASK + 0U, // PseudoVFMACC_VV_M2 + 0U, // PseudoVFMACC_VV_M2_MASK + 0U, // PseudoVFMACC_VV_M4 + 0U, // PseudoVFMACC_VV_M4_MASK + 0U, // PseudoVFMACC_VV_M8 + 0U, // PseudoVFMACC_VV_M8_MASK + 0U, // PseudoVFMACC_VV_MF2 + 0U, // PseudoVFMACC_VV_MF2_MASK + 0U, // PseudoVFMACC_VV_MF4 + 0U, // PseudoVFMACC_VV_MF4_MASK + 0U, // PseudoVFMACC_VV_MF8 + 0U, // PseudoVFMACC_VV_MF8_MASK + 0U, // PseudoVFMADD_VF16_M1 + 0U, // PseudoVFMADD_VF16_M1_MASK + 0U, // PseudoVFMADD_VF16_M2 + 0U, // PseudoVFMADD_VF16_M2_MASK + 0U, // PseudoVFMADD_VF16_M4 + 0U, // PseudoVFMADD_VF16_M4_MASK + 0U, // PseudoVFMADD_VF16_M8 + 0U, // PseudoVFMADD_VF16_M8_MASK + 0U, // PseudoVFMADD_VF16_MF2 + 0U, // PseudoVFMADD_VF16_MF2_MASK + 0U, // PseudoVFMADD_VF16_MF4 + 0U, // PseudoVFMADD_VF16_MF4_MASK + 0U, // PseudoVFMADD_VF16_MF8 + 0U, // PseudoVFMADD_VF16_MF8_MASK + 0U, // PseudoVFMADD_VF32_M1 + 0U, // PseudoVFMADD_VF32_M1_MASK + 0U, // PseudoVFMADD_VF32_M2 + 0U, // PseudoVFMADD_VF32_M2_MASK + 0U, // PseudoVFMADD_VF32_M4 + 0U, // PseudoVFMADD_VF32_M4_MASK + 0U, // PseudoVFMADD_VF32_M8 + 0U, // PseudoVFMADD_VF32_M8_MASK + 0U, // PseudoVFMADD_VF32_MF2 + 0U, // PseudoVFMADD_VF32_MF2_MASK + 0U, // PseudoVFMADD_VF32_MF4 + 0U, // PseudoVFMADD_VF32_MF4_MASK + 0U, // PseudoVFMADD_VF32_MF8 + 0U, // PseudoVFMADD_VF32_MF8_MASK + 0U, // PseudoVFMADD_VF64_M1 + 0U, // PseudoVFMADD_VF64_M1_MASK + 0U, // PseudoVFMADD_VF64_M2 + 0U, // PseudoVFMADD_VF64_M2_MASK + 0U, // PseudoVFMADD_VF64_M4 + 0U, // PseudoVFMADD_VF64_M4_MASK + 0U, // PseudoVFMADD_VF64_M8 + 0U, // PseudoVFMADD_VF64_M8_MASK + 0U, // PseudoVFMADD_VF64_MF2 + 0U, // PseudoVFMADD_VF64_MF2_MASK + 0U, // PseudoVFMADD_VF64_MF4 + 0U, // PseudoVFMADD_VF64_MF4_MASK + 0U, // PseudoVFMADD_VF64_MF8 + 0U, // PseudoVFMADD_VF64_MF8_MASK + 0U, // PseudoVFMADD_VV_M1 + 0U, // PseudoVFMADD_VV_M1_MASK + 0U, // PseudoVFMADD_VV_M2 + 0U, // PseudoVFMADD_VV_M2_MASK + 0U, // PseudoVFMADD_VV_M4 + 0U, // PseudoVFMADD_VV_M4_MASK + 0U, // PseudoVFMADD_VV_M8 + 0U, // PseudoVFMADD_VV_M8_MASK + 0U, // PseudoVFMADD_VV_MF2 + 0U, // PseudoVFMADD_VV_MF2_MASK + 0U, // PseudoVFMADD_VV_MF4 + 0U, // PseudoVFMADD_VV_MF4_MASK + 0U, // PseudoVFMADD_VV_MF8 + 0U, // PseudoVFMADD_VV_MF8_MASK + 0U, // PseudoVFMAX_VF16_M1 + 0U, // PseudoVFMAX_VF16_M1_MASK + 0U, // PseudoVFMAX_VF16_M2 + 0U, // PseudoVFMAX_VF16_M2_MASK + 0U, // PseudoVFMAX_VF16_M4 + 0U, // PseudoVFMAX_VF16_M4_MASK + 0U, // PseudoVFMAX_VF16_M8 + 0U, // PseudoVFMAX_VF16_M8_MASK + 0U, // PseudoVFMAX_VF16_MF2 + 0U, // PseudoVFMAX_VF16_MF2_MASK + 0U, // PseudoVFMAX_VF16_MF4 + 0U, // PseudoVFMAX_VF16_MF4_MASK + 0U, // PseudoVFMAX_VF16_MF8 + 0U, // PseudoVFMAX_VF16_MF8_MASK + 0U, // PseudoVFMAX_VF32_M1 + 0U, // PseudoVFMAX_VF32_M1_MASK + 0U, // PseudoVFMAX_VF32_M2 + 0U, // PseudoVFMAX_VF32_M2_MASK + 0U, // PseudoVFMAX_VF32_M4 + 0U, // PseudoVFMAX_VF32_M4_MASK + 0U, // PseudoVFMAX_VF32_M8 + 0U, // PseudoVFMAX_VF32_M8_MASK + 0U, // PseudoVFMAX_VF32_MF2 + 0U, // PseudoVFMAX_VF32_MF2_MASK + 0U, // PseudoVFMAX_VF32_MF4 + 0U, // PseudoVFMAX_VF32_MF4_MASK + 0U, // PseudoVFMAX_VF32_MF8 + 0U, // PseudoVFMAX_VF32_MF8_MASK + 0U, // PseudoVFMAX_VF64_M1 + 0U, // PseudoVFMAX_VF64_M1_MASK + 0U, // PseudoVFMAX_VF64_M2 + 0U, // PseudoVFMAX_VF64_M2_MASK + 0U, // PseudoVFMAX_VF64_M4 + 0U, // PseudoVFMAX_VF64_M4_MASK + 0U, // PseudoVFMAX_VF64_M8 + 0U, // PseudoVFMAX_VF64_M8_MASK + 0U, // PseudoVFMAX_VF64_MF2 + 0U, // PseudoVFMAX_VF64_MF2_MASK + 0U, // PseudoVFMAX_VF64_MF4 + 0U, // PseudoVFMAX_VF64_MF4_MASK + 0U, // PseudoVFMAX_VF64_MF8 + 0U, // PseudoVFMAX_VF64_MF8_MASK + 0U, // PseudoVFMAX_VV_M1 + 0U, // PseudoVFMAX_VV_M1_MASK + 0U, // PseudoVFMAX_VV_M2 + 0U, // PseudoVFMAX_VV_M2_MASK + 0U, // PseudoVFMAX_VV_M4 + 0U, // PseudoVFMAX_VV_M4_MASK + 0U, // PseudoVFMAX_VV_M8 + 0U, // PseudoVFMAX_VV_M8_MASK + 0U, // PseudoVFMAX_VV_MF2 + 0U, // PseudoVFMAX_VV_MF2_MASK + 0U, // PseudoVFMAX_VV_MF4 + 0U, // PseudoVFMAX_VV_MF4_MASK + 0U, // PseudoVFMAX_VV_MF8 + 0U, // PseudoVFMAX_VV_MF8_MASK + 0U, // PseudoVFMERGE_VF16M_M1 + 0U, // PseudoVFMERGE_VF16M_M2 + 0U, // PseudoVFMERGE_VF16M_M4 + 0U, // PseudoVFMERGE_VF16M_M8 + 0U, // PseudoVFMERGE_VF16M_MF2 + 0U, // PseudoVFMERGE_VF16M_MF4 + 0U, // PseudoVFMERGE_VF16M_MF8 + 0U, // PseudoVFMERGE_VF32M_M1 + 0U, // PseudoVFMERGE_VF32M_M2 + 0U, // PseudoVFMERGE_VF32M_M4 + 0U, // PseudoVFMERGE_VF32M_M8 + 0U, // PseudoVFMERGE_VF32M_MF2 + 0U, // PseudoVFMERGE_VF32M_MF4 + 0U, // PseudoVFMERGE_VF32M_MF8 + 0U, // PseudoVFMERGE_VF64M_M1 + 0U, // PseudoVFMERGE_VF64M_M2 + 0U, // PseudoVFMERGE_VF64M_M4 + 0U, // PseudoVFMERGE_VF64M_M8 + 0U, // PseudoVFMERGE_VF64M_MF2 + 0U, // PseudoVFMERGE_VF64M_MF4 + 0U, // PseudoVFMERGE_VF64M_MF8 + 0U, // PseudoVFMIN_VF16_M1 + 0U, // PseudoVFMIN_VF16_M1_MASK + 0U, // PseudoVFMIN_VF16_M2 + 0U, // PseudoVFMIN_VF16_M2_MASK + 0U, // PseudoVFMIN_VF16_M4 + 0U, // PseudoVFMIN_VF16_M4_MASK + 0U, // PseudoVFMIN_VF16_M8 + 0U, // PseudoVFMIN_VF16_M8_MASK + 0U, // PseudoVFMIN_VF16_MF2 + 0U, // PseudoVFMIN_VF16_MF2_MASK + 0U, // PseudoVFMIN_VF16_MF4 + 0U, // PseudoVFMIN_VF16_MF4_MASK + 0U, // PseudoVFMIN_VF16_MF8 + 0U, // PseudoVFMIN_VF16_MF8_MASK + 0U, // PseudoVFMIN_VF32_M1 + 0U, // PseudoVFMIN_VF32_M1_MASK + 0U, // PseudoVFMIN_VF32_M2 + 0U, // PseudoVFMIN_VF32_M2_MASK + 0U, // PseudoVFMIN_VF32_M4 + 0U, // PseudoVFMIN_VF32_M4_MASK + 0U, // PseudoVFMIN_VF32_M8 + 0U, // PseudoVFMIN_VF32_M8_MASK + 0U, // PseudoVFMIN_VF32_MF2 + 0U, // PseudoVFMIN_VF32_MF2_MASK + 0U, // PseudoVFMIN_VF32_MF4 + 0U, // PseudoVFMIN_VF32_MF4_MASK + 0U, // PseudoVFMIN_VF32_MF8 + 0U, // PseudoVFMIN_VF32_MF8_MASK + 0U, // PseudoVFMIN_VF64_M1 + 0U, // PseudoVFMIN_VF64_M1_MASK + 0U, // PseudoVFMIN_VF64_M2 + 0U, // PseudoVFMIN_VF64_M2_MASK + 0U, // PseudoVFMIN_VF64_M4 + 0U, // PseudoVFMIN_VF64_M4_MASK + 0U, // PseudoVFMIN_VF64_M8 + 0U, // PseudoVFMIN_VF64_M8_MASK + 0U, // PseudoVFMIN_VF64_MF2 + 0U, // PseudoVFMIN_VF64_MF2_MASK + 0U, // PseudoVFMIN_VF64_MF4 + 0U, // PseudoVFMIN_VF64_MF4_MASK + 0U, // PseudoVFMIN_VF64_MF8 + 0U, // PseudoVFMIN_VF64_MF8_MASK + 0U, // PseudoVFMIN_VV_M1 + 0U, // PseudoVFMIN_VV_M1_MASK + 0U, // PseudoVFMIN_VV_M2 + 0U, // PseudoVFMIN_VV_M2_MASK + 0U, // PseudoVFMIN_VV_M4 + 0U, // PseudoVFMIN_VV_M4_MASK + 0U, // PseudoVFMIN_VV_M8 + 0U, // PseudoVFMIN_VV_M8_MASK + 0U, // PseudoVFMIN_VV_MF2 + 0U, // PseudoVFMIN_VV_MF2_MASK + 0U, // PseudoVFMIN_VV_MF4 + 0U, // PseudoVFMIN_VV_MF4_MASK + 0U, // PseudoVFMIN_VV_MF8 + 0U, // PseudoVFMIN_VV_MF8_MASK + 0U, // PseudoVFMSAC_VF16_M1 + 0U, // PseudoVFMSAC_VF16_M1_MASK + 0U, // PseudoVFMSAC_VF16_M2 + 0U, // PseudoVFMSAC_VF16_M2_MASK + 0U, // PseudoVFMSAC_VF16_M4 + 0U, // PseudoVFMSAC_VF16_M4_MASK + 0U, // PseudoVFMSAC_VF16_M8 + 0U, // PseudoVFMSAC_VF16_M8_MASK + 0U, // PseudoVFMSAC_VF16_MF2 + 0U, // PseudoVFMSAC_VF16_MF2_MASK + 0U, // PseudoVFMSAC_VF16_MF4 + 0U, // PseudoVFMSAC_VF16_MF4_MASK + 0U, // PseudoVFMSAC_VF16_MF8 + 0U, // PseudoVFMSAC_VF16_MF8_MASK + 0U, // PseudoVFMSAC_VF32_M1 + 0U, // PseudoVFMSAC_VF32_M1_MASK + 0U, // PseudoVFMSAC_VF32_M2 + 0U, // PseudoVFMSAC_VF32_M2_MASK + 0U, // PseudoVFMSAC_VF32_M4 + 0U, // PseudoVFMSAC_VF32_M4_MASK + 0U, // PseudoVFMSAC_VF32_M8 + 0U, // PseudoVFMSAC_VF32_M8_MASK + 0U, // PseudoVFMSAC_VF32_MF2 + 0U, // PseudoVFMSAC_VF32_MF2_MASK + 0U, // PseudoVFMSAC_VF32_MF4 + 0U, // PseudoVFMSAC_VF32_MF4_MASK + 0U, // PseudoVFMSAC_VF32_MF8 + 0U, // PseudoVFMSAC_VF32_MF8_MASK + 0U, // PseudoVFMSAC_VF64_M1 + 0U, // PseudoVFMSAC_VF64_M1_MASK + 0U, // PseudoVFMSAC_VF64_M2 + 0U, // PseudoVFMSAC_VF64_M2_MASK + 0U, // PseudoVFMSAC_VF64_M4 + 0U, // PseudoVFMSAC_VF64_M4_MASK + 0U, // PseudoVFMSAC_VF64_M8 + 0U, // PseudoVFMSAC_VF64_M8_MASK + 0U, // PseudoVFMSAC_VF64_MF2 + 0U, // PseudoVFMSAC_VF64_MF2_MASK + 0U, // PseudoVFMSAC_VF64_MF4 + 0U, // PseudoVFMSAC_VF64_MF4_MASK + 0U, // PseudoVFMSAC_VF64_MF8 + 0U, // PseudoVFMSAC_VF64_MF8_MASK + 0U, // PseudoVFMSAC_VV_M1 + 0U, // PseudoVFMSAC_VV_M1_MASK + 0U, // PseudoVFMSAC_VV_M2 + 0U, // PseudoVFMSAC_VV_M2_MASK + 0U, // PseudoVFMSAC_VV_M4 + 0U, // PseudoVFMSAC_VV_M4_MASK + 0U, // PseudoVFMSAC_VV_M8 + 0U, // PseudoVFMSAC_VV_M8_MASK + 0U, // PseudoVFMSAC_VV_MF2 + 0U, // PseudoVFMSAC_VV_MF2_MASK + 0U, // PseudoVFMSAC_VV_MF4 + 0U, // PseudoVFMSAC_VV_MF4_MASK + 0U, // PseudoVFMSAC_VV_MF8 + 0U, // PseudoVFMSAC_VV_MF8_MASK + 0U, // PseudoVFMSUB_VF16_M1 + 0U, // PseudoVFMSUB_VF16_M1_MASK + 0U, // PseudoVFMSUB_VF16_M2 + 0U, // PseudoVFMSUB_VF16_M2_MASK + 0U, // PseudoVFMSUB_VF16_M4 + 0U, // PseudoVFMSUB_VF16_M4_MASK + 0U, // PseudoVFMSUB_VF16_M8 + 0U, // PseudoVFMSUB_VF16_M8_MASK + 0U, // PseudoVFMSUB_VF16_MF2 + 0U, // PseudoVFMSUB_VF16_MF2_MASK + 0U, // PseudoVFMSUB_VF16_MF4 + 0U, // PseudoVFMSUB_VF16_MF4_MASK + 0U, // PseudoVFMSUB_VF16_MF8 + 0U, // PseudoVFMSUB_VF16_MF8_MASK + 0U, // PseudoVFMSUB_VF32_M1 + 0U, // PseudoVFMSUB_VF32_M1_MASK + 0U, // PseudoVFMSUB_VF32_M2 + 0U, // PseudoVFMSUB_VF32_M2_MASK + 0U, // PseudoVFMSUB_VF32_M4 + 0U, // PseudoVFMSUB_VF32_M4_MASK + 0U, // PseudoVFMSUB_VF32_M8 + 0U, // PseudoVFMSUB_VF32_M8_MASK + 0U, // PseudoVFMSUB_VF32_MF2 + 0U, // PseudoVFMSUB_VF32_MF2_MASK + 0U, // PseudoVFMSUB_VF32_MF4 + 0U, // PseudoVFMSUB_VF32_MF4_MASK + 0U, // PseudoVFMSUB_VF32_MF8 + 0U, // PseudoVFMSUB_VF32_MF8_MASK + 0U, // PseudoVFMSUB_VF64_M1 + 0U, // PseudoVFMSUB_VF64_M1_MASK + 0U, // PseudoVFMSUB_VF64_M2 + 0U, // PseudoVFMSUB_VF64_M2_MASK + 0U, // PseudoVFMSUB_VF64_M4 + 0U, // PseudoVFMSUB_VF64_M4_MASK + 0U, // PseudoVFMSUB_VF64_M8 + 0U, // PseudoVFMSUB_VF64_M8_MASK + 0U, // PseudoVFMSUB_VF64_MF2 + 0U, // PseudoVFMSUB_VF64_MF2_MASK + 0U, // PseudoVFMSUB_VF64_MF4 + 0U, // PseudoVFMSUB_VF64_MF4_MASK + 0U, // PseudoVFMSUB_VF64_MF8 + 0U, // PseudoVFMSUB_VF64_MF8_MASK + 0U, // PseudoVFMSUB_VV_M1 + 0U, // PseudoVFMSUB_VV_M1_MASK + 0U, // PseudoVFMSUB_VV_M2 + 0U, // PseudoVFMSUB_VV_M2_MASK + 0U, // PseudoVFMSUB_VV_M4 + 0U, // PseudoVFMSUB_VV_M4_MASK + 0U, // PseudoVFMSUB_VV_M8 + 0U, // PseudoVFMSUB_VV_M8_MASK + 0U, // PseudoVFMSUB_VV_MF2 + 0U, // PseudoVFMSUB_VV_MF2_MASK + 0U, // PseudoVFMSUB_VV_MF4 + 0U, // PseudoVFMSUB_VV_MF4_MASK + 0U, // PseudoVFMSUB_VV_MF8 + 0U, // PseudoVFMSUB_VV_MF8_MASK + 0U, // PseudoVFMUL_VF16_M1 + 0U, // PseudoVFMUL_VF16_M1_MASK + 0U, // PseudoVFMUL_VF16_M2 + 0U, // PseudoVFMUL_VF16_M2_MASK + 0U, // PseudoVFMUL_VF16_M4 + 0U, // PseudoVFMUL_VF16_M4_MASK + 0U, // PseudoVFMUL_VF16_M8 + 0U, // PseudoVFMUL_VF16_M8_MASK + 0U, // PseudoVFMUL_VF16_MF2 + 0U, // PseudoVFMUL_VF16_MF2_MASK + 0U, // PseudoVFMUL_VF16_MF4 + 0U, // PseudoVFMUL_VF16_MF4_MASK + 0U, // PseudoVFMUL_VF16_MF8 + 0U, // PseudoVFMUL_VF16_MF8_MASK + 0U, // PseudoVFMUL_VF32_M1 + 0U, // PseudoVFMUL_VF32_M1_MASK + 0U, // PseudoVFMUL_VF32_M2 + 0U, // PseudoVFMUL_VF32_M2_MASK + 0U, // PseudoVFMUL_VF32_M4 + 0U, // PseudoVFMUL_VF32_M4_MASK + 0U, // PseudoVFMUL_VF32_M8 + 0U, // PseudoVFMUL_VF32_M8_MASK + 0U, // PseudoVFMUL_VF32_MF2 + 0U, // PseudoVFMUL_VF32_MF2_MASK + 0U, // PseudoVFMUL_VF32_MF4 + 0U, // PseudoVFMUL_VF32_MF4_MASK + 0U, // PseudoVFMUL_VF32_MF8 + 0U, // PseudoVFMUL_VF32_MF8_MASK + 0U, // PseudoVFMUL_VF64_M1 + 0U, // PseudoVFMUL_VF64_M1_MASK + 0U, // PseudoVFMUL_VF64_M2 + 0U, // PseudoVFMUL_VF64_M2_MASK + 0U, // PseudoVFMUL_VF64_M4 + 0U, // PseudoVFMUL_VF64_M4_MASK + 0U, // PseudoVFMUL_VF64_M8 + 0U, // PseudoVFMUL_VF64_M8_MASK + 0U, // PseudoVFMUL_VF64_MF2 + 0U, // PseudoVFMUL_VF64_MF2_MASK + 0U, // PseudoVFMUL_VF64_MF4 + 0U, // PseudoVFMUL_VF64_MF4_MASK + 0U, // PseudoVFMUL_VF64_MF8 + 0U, // PseudoVFMUL_VF64_MF8_MASK + 0U, // PseudoVFMUL_VV_M1 + 0U, // PseudoVFMUL_VV_M1_MASK + 0U, // PseudoVFMUL_VV_M2 + 0U, // PseudoVFMUL_VV_M2_MASK + 0U, // PseudoVFMUL_VV_M4 + 0U, // PseudoVFMUL_VV_M4_MASK + 0U, // PseudoVFMUL_VV_M8 + 0U, // PseudoVFMUL_VV_M8_MASK + 0U, // PseudoVFMUL_VV_MF2 + 0U, // PseudoVFMUL_VV_MF2_MASK + 0U, // PseudoVFMUL_VV_MF4 + 0U, // PseudoVFMUL_VV_MF4_MASK + 0U, // PseudoVFMUL_VV_MF8 + 0U, // PseudoVFMUL_VV_MF8_MASK + 0U, // PseudoVFMV_F16_S_M1 + 0U, // PseudoVFMV_F16_S_M2 + 0U, // PseudoVFMV_F16_S_M4 + 0U, // PseudoVFMV_F16_S_M8 + 0U, // PseudoVFMV_F16_S_MF2 + 0U, // PseudoVFMV_F16_S_MF4 + 0U, // PseudoVFMV_F16_S_MF8 + 0U, // PseudoVFMV_F32_S_M1 + 0U, // PseudoVFMV_F32_S_M2 + 0U, // PseudoVFMV_F32_S_M4 + 0U, // PseudoVFMV_F32_S_M8 + 0U, // PseudoVFMV_F32_S_MF2 + 0U, // PseudoVFMV_F32_S_MF4 + 0U, // PseudoVFMV_F32_S_MF8 + 0U, // PseudoVFMV_F64_S_M1 + 0U, // PseudoVFMV_F64_S_M2 + 0U, // PseudoVFMV_F64_S_M4 + 0U, // PseudoVFMV_F64_S_M8 + 0U, // PseudoVFMV_F64_S_MF2 + 0U, // PseudoVFMV_F64_S_MF4 + 0U, // PseudoVFMV_F64_S_MF8 + 0U, // PseudoVFMV_S_F16_M1 + 0U, // PseudoVFMV_S_F16_M2 + 0U, // PseudoVFMV_S_F16_M4 + 0U, // PseudoVFMV_S_F16_M8 + 0U, // PseudoVFMV_S_F16_MF2 + 0U, // PseudoVFMV_S_F16_MF4 + 0U, // PseudoVFMV_S_F16_MF8 + 0U, // PseudoVFMV_S_F32_M1 + 0U, // PseudoVFMV_S_F32_M2 + 0U, // PseudoVFMV_S_F32_M4 + 0U, // PseudoVFMV_S_F32_M8 + 0U, // PseudoVFMV_S_F32_MF2 + 0U, // PseudoVFMV_S_F32_MF4 + 0U, // PseudoVFMV_S_F32_MF8 + 0U, // PseudoVFMV_S_F64_M1 + 0U, // PseudoVFMV_S_F64_M2 + 0U, // PseudoVFMV_S_F64_M4 + 0U, // PseudoVFMV_S_F64_M8 + 0U, // PseudoVFMV_S_F64_MF2 + 0U, // PseudoVFMV_S_F64_MF4 + 0U, // PseudoVFMV_S_F64_MF8 + 0U, // PseudoVFMV_V_F16_M1 + 0U, // PseudoVFMV_V_F16_M2 + 0U, // PseudoVFMV_V_F16_M4 + 0U, // PseudoVFMV_V_F16_M8 + 0U, // PseudoVFMV_V_F16_MF2 + 0U, // PseudoVFMV_V_F16_MF4 + 0U, // PseudoVFMV_V_F16_MF8 + 0U, // PseudoVFMV_V_F32_M1 + 0U, // PseudoVFMV_V_F32_M2 + 0U, // PseudoVFMV_V_F32_M4 + 0U, // PseudoVFMV_V_F32_M8 + 0U, // PseudoVFMV_V_F32_MF2 + 0U, // PseudoVFMV_V_F32_MF4 + 0U, // PseudoVFMV_V_F32_MF8 + 0U, // PseudoVFMV_V_F64_M1 + 0U, // PseudoVFMV_V_F64_M2 + 0U, // PseudoVFMV_V_F64_M4 + 0U, // PseudoVFMV_V_F64_M8 + 0U, // PseudoVFMV_V_F64_MF2 + 0U, // PseudoVFMV_V_F64_MF4 + 0U, // PseudoVFMV_V_F64_MF8 + 0U, // PseudoVFNCVT_F_F_W_M1 + 0U, // PseudoVFNCVT_F_F_W_M1_MASK + 0U, // PseudoVFNCVT_F_F_W_M2 + 0U, // PseudoVFNCVT_F_F_W_M2_MASK + 0U, // PseudoVFNCVT_F_F_W_M4 + 0U, // PseudoVFNCVT_F_F_W_M4_MASK + 0U, // PseudoVFNCVT_F_F_W_MF2 + 0U, // PseudoVFNCVT_F_F_W_MF2_MASK + 0U, // PseudoVFNCVT_F_F_W_MF4 + 0U, // PseudoVFNCVT_F_F_W_MF4_MASK + 0U, // PseudoVFNCVT_F_F_W_MF8 + 0U, // PseudoVFNCVT_F_F_W_MF8_MASK + 0U, // PseudoVFNCVT_F_XU_W_M1 + 0U, // PseudoVFNCVT_F_XU_W_M1_MASK + 0U, // PseudoVFNCVT_F_XU_W_M2 + 0U, // PseudoVFNCVT_F_XU_W_M2_MASK + 0U, // PseudoVFNCVT_F_XU_W_M4 + 0U, // PseudoVFNCVT_F_XU_W_M4_MASK + 0U, // PseudoVFNCVT_F_XU_W_MF2 + 0U, // PseudoVFNCVT_F_XU_W_MF2_MASK + 0U, // PseudoVFNCVT_F_XU_W_MF4 + 0U, // PseudoVFNCVT_F_XU_W_MF4_MASK + 0U, // PseudoVFNCVT_F_XU_W_MF8 + 0U, // PseudoVFNCVT_F_XU_W_MF8_MASK + 0U, // PseudoVFNCVT_F_X_W_M1 + 0U, // PseudoVFNCVT_F_X_W_M1_MASK + 0U, // PseudoVFNCVT_F_X_W_M2 + 0U, // PseudoVFNCVT_F_X_W_M2_MASK + 0U, // PseudoVFNCVT_F_X_W_M4 + 0U, // PseudoVFNCVT_F_X_W_M4_MASK + 0U, // PseudoVFNCVT_F_X_W_MF2 + 0U, // PseudoVFNCVT_F_X_W_MF2_MASK + 0U, // PseudoVFNCVT_F_X_W_MF4 + 0U, // PseudoVFNCVT_F_X_W_MF4_MASK + 0U, // PseudoVFNCVT_F_X_W_MF8 + 0U, // PseudoVFNCVT_F_X_W_MF8_MASK + 0U, // PseudoVFNCVT_ROD_F_F_W_M1 + 0U, // PseudoVFNCVT_ROD_F_F_W_M1_MASK + 0U, // PseudoVFNCVT_ROD_F_F_W_M2 + 0U, // PseudoVFNCVT_ROD_F_F_W_M2_MASK + 0U, // PseudoVFNCVT_ROD_F_F_W_M4 + 0U, // PseudoVFNCVT_ROD_F_F_W_M4_MASK + 0U, // PseudoVFNCVT_ROD_F_F_W_MF2 + 0U, // PseudoVFNCVT_ROD_F_F_W_MF2_MASK + 0U, // PseudoVFNCVT_ROD_F_F_W_MF4 + 0U, // PseudoVFNCVT_ROD_F_F_W_MF4_MASK + 0U, // PseudoVFNCVT_ROD_F_F_W_MF8 + 0U, // PseudoVFNCVT_ROD_F_F_W_MF8_MASK + 0U, // PseudoVFNCVT_RTZ_XU_F_W_M1 + 0U, // PseudoVFNCVT_RTZ_XU_F_W_M1_MASK + 0U, // PseudoVFNCVT_RTZ_XU_F_W_M2 + 0U, // PseudoVFNCVT_RTZ_XU_F_W_M2_MASK + 0U, // PseudoVFNCVT_RTZ_XU_F_W_M4 + 0U, // PseudoVFNCVT_RTZ_XU_F_W_M4_MASK + 0U, // PseudoVFNCVT_RTZ_XU_F_W_MF2 + 0U, // PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK + 0U, // PseudoVFNCVT_RTZ_XU_F_W_MF4 + 0U, // PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK + 0U, // PseudoVFNCVT_RTZ_XU_F_W_MF8 + 0U, // PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK + 0U, // PseudoVFNCVT_RTZ_X_F_W_M1 + 0U, // PseudoVFNCVT_RTZ_X_F_W_M1_MASK + 0U, // PseudoVFNCVT_RTZ_X_F_W_M2 + 0U, // PseudoVFNCVT_RTZ_X_F_W_M2_MASK + 0U, // PseudoVFNCVT_RTZ_X_F_W_M4 + 0U, // PseudoVFNCVT_RTZ_X_F_W_M4_MASK + 0U, // PseudoVFNCVT_RTZ_X_F_W_MF2 + 0U, // PseudoVFNCVT_RTZ_X_F_W_MF2_MASK + 0U, // PseudoVFNCVT_RTZ_X_F_W_MF4 + 0U, // PseudoVFNCVT_RTZ_X_F_W_MF4_MASK + 0U, // PseudoVFNCVT_RTZ_X_F_W_MF8 + 0U, // PseudoVFNCVT_RTZ_X_F_W_MF8_MASK + 0U, // PseudoVFNCVT_XU_F_W_M1 + 0U, // PseudoVFNCVT_XU_F_W_M1_MASK + 0U, // PseudoVFNCVT_XU_F_W_M2 + 0U, // PseudoVFNCVT_XU_F_W_M2_MASK + 0U, // PseudoVFNCVT_XU_F_W_M4 + 0U, // PseudoVFNCVT_XU_F_W_M4_MASK + 0U, // PseudoVFNCVT_XU_F_W_MF2 + 0U, // PseudoVFNCVT_XU_F_W_MF2_MASK + 0U, // PseudoVFNCVT_XU_F_W_MF4 + 0U, // PseudoVFNCVT_XU_F_W_MF4_MASK + 0U, // PseudoVFNCVT_XU_F_W_MF8 + 0U, // PseudoVFNCVT_XU_F_W_MF8_MASK + 0U, // PseudoVFNCVT_X_F_W_M1 + 0U, // PseudoVFNCVT_X_F_W_M1_MASK + 0U, // PseudoVFNCVT_X_F_W_M2 + 0U, // PseudoVFNCVT_X_F_W_M2_MASK + 0U, // PseudoVFNCVT_X_F_W_M4 + 0U, // PseudoVFNCVT_X_F_W_M4_MASK + 0U, // PseudoVFNCVT_X_F_W_MF2 + 0U, // PseudoVFNCVT_X_F_W_MF2_MASK + 0U, // PseudoVFNCVT_X_F_W_MF4 + 0U, // PseudoVFNCVT_X_F_W_MF4_MASK + 0U, // PseudoVFNCVT_X_F_W_MF8 + 0U, // PseudoVFNCVT_X_F_W_MF8_MASK + 0U, // PseudoVFNMACC_VF16_M1 + 0U, // PseudoVFNMACC_VF16_M1_MASK + 0U, // PseudoVFNMACC_VF16_M2 + 0U, // PseudoVFNMACC_VF16_M2_MASK + 0U, // PseudoVFNMACC_VF16_M4 + 0U, // PseudoVFNMACC_VF16_M4_MASK + 0U, // PseudoVFNMACC_VF16_M8 + 0U, // PseudoVFNMACC_VF16_M8_MASK + 0U, // PseudoVFNMACC_VF16_MF2 + 0U, // PseudoVFNMACC_VF16_MF2_MASK + 0U, // PseudoVFNMACC_VF16_MF4 + 0U, // PseudoVFNMACC_VF16_MF4_MASK + 0U, // PseudoVFNMACC_VF16_MF8 + 0U, // PseudoVFNMACC_VF16_MF8_MASK + 0U, // PseudoVFNMACC_VF32_M1 + 0U, // PseudoVFNMACC_VF32_M1_MASK + 0U, // PseudoVFNMACC_VF32_M2 + 0U, // PseudoVFNMACC_VF32_M2_MASK + 0U, // PseudoVFNMACC_VF32_M4 + 0U, // PseudoVFNMACC_VF32_M4_MASK + 0U, // PseudoVFNMACC_VF32_M8 + 0U, // PseudoVFNMACC_VF32_M8_MASK + 0U, // PseudoVFNMACC_VF32_MF2 + 0U, // PseudoVFNMACC_VF32_MF2_MASK + 0U, // PseudoVFNMACC_VF32_MF4 + 0U, // PseudoVFNMACC_VF32_MF4_MASK + 0U, // PseudoVFNMACC_VF32_MF8 + 0U, // PseudoVFNMACC_VF32_MF8_MASK + 0U, // PseudoVFNMACC_VF64_M1 + 0U, // PseudoVFNMACC_VF64_M1_MASK + 0U, // PseudoVFNMACC_VF64_M2 + 0U, // PseudoVFNMACC_VF64_M2_MASK + 0U, // PseudoVFNMACC_VF64_M4 + 0U, // PseudoVFNMACC_VF64_M4_MASK + 0U, // PseudoVFNMACC_VF64_M8 + 0U, // PseudoVFNMACC_VF64_M8_MASK + 0U, // PseudoVFNMACC_VF64_MF2 + 0U, // PseudoVFNMACC_VF64_MF2_MASK + 0U, // PseudoVFNMACC_VF64_MF4 + 0U, // PseudoVFNMACC_VF64_MF4_MASK + 0U, // PseudoVFNMACC_VF64_MF8 + 0U, // PseudoVFNMACC_VF64_MF8_MASK + 0U, // PseudoVFNMACC_VV_M1 + 0U, // PseudoVFNMACC_VV_M1_MASK + 0U, // PseudoVFNMACC_VV_M2 + 0U, // PseudoVFNMACC_VV_M2_MASK + 0U, // PseudoVFNMACC_VV_M4 + 0U, // PseudoVFNMACC_VV_M4_MASK + 0U, // PseudoVFNMACC_VV_M8 + 0U, // PseudoVFNMACC_VV_M8_MASK + 0U, // PseudoVFNMACC_VV_MF2 + 0U, // PseudoVFNMACC_VV_MF2_MASK + 0U, // PseudoVFNMACC_VV_MF4 + 0U, // PseudoVFNMACC_VV_MF4_MASK + 0U, // PseudoVFNMACC_VV_MF8 + 0U, // PseudoVFNMACC_VV_MF8_MASK + 0U, // PseudoVFNMADD_VF16_M1 + 0U, // PseudoVFNMADD_VF16_M1_MASK + 0U, // PseudoVFNMADD_VF16_M2 + 0U, // PseudoVFNMADD_VF16_M2_MASK + 0U, // PseudoVFNMADD_VF16_M4 + 0U, // PseudoVFNMADD_VF16_M4_MASK + 0U, // PseudoVFNMADD_VF16_M8 + 0U, // PseudoVFNMADD_VF16_M8_MASK + 0U, // PseudoVFNMADD_VF16_MF2 + 0U, // PseudoVFNMADD_VF16_MF2_MASK + 0U, // PseudoVFNMADD_VF16_MF4 + 0U, // PseudoVFNMADD_VF16_MF4_MASK + 0U, // PseudoVFNMADD_VF16_MF8 + 0U, // PseudoVFNMADD_VF16_MF8_MASK + 0U, // PseudoVFNMADD_VF32_M1 + 0U, // PseudoVFNMADD_VF32_M1_MASK + 0U, // PseudoVFNMADD_VF32_M2 + 0U, // PseudoVFNMADD_VF32_M2_MASK + 0U, // PseudoVFNMADD_VF32_M4 + 0U, // PseudoVFNMADD_VF32_M4_MASK + 0U, // PseudoVFNMADD_VF32_M8 + 0U, // PseudoVFNMADD_VF32_M8_MASK + 0U, // PseudoVFNMADD_VF32_MF2 + 0U, // PseudoVFNMADD_VF32_MF2_MASK + 0U, // PseudoVFNMADD_VF32_MF4 + 0U, // PseudoVFNMADD_VF32_MF4_MASK + 0U, // PseudoVFNMADD_VF32_MF8 + 0U, // PseudoVFNMADD_VF32_MF8_MASK + 0U, // PseudoVFNMADD_VF64_M1 + 0U, // PseudoVFNMADD_VF64_M1_MASK + 0U, // PseudoVFNMADD_VF64_M2 + 0U, // PseudoVFNMADD_VF64_M2_MASK + 0U, // PseudoVFNMADD_VF64_M4 + 0U, // PseudoVFNMADD_VF64_M4_MASK + 0U, // PseudoVFNMADD_VF64_M8 + 0U, // PseudoVFNMADD_VF64_M8_MASK + 0U, // PseudoVFNMADD_VF64_MF2 + 0U, // PseudoVFNMADD_VF64_MF2_MASK + 0U, // PseudoVFNMADD_VF64_MF4 + 0U, // PseudoVFNMADD_VF64_MF4_MASK + 0U, // PseudoVFNMADD_VF64_MF8 + 0U, // PseudoVFNMADD_VF64_MF8_MASK + 0U, // PseudoVFNMADD_VV_M1 + 0U, // PseudoVFNMADD_VV_M1_MASK + 0U, // PseudoVFNMADD_VV_M2 + 0U, // PseudoVFNMADD_VV_M2_MASK + 0U, // PseudoVFNMADD_VV_M4 + 0U, // PseudoVFNMADD_VV_M4_MASK + 0U, // PseudoVFNMADD_VV_M8 + 0U, // PseudoVFNMADD_VV_M8_MASK + 0U, // PseudoVFNMADD_VV_MF2 + 0U, // PseudoVFNMADD_VV_MF2_MASK + 0U, // PseudoVFNMADD_VV_MF4 + 0U, // PseudoVFNMADD_VV_MF4_MASK + 0U, // PseudoVFNMADD_VV_MF8 + 0U, // PseudoVFNMADD_VV_MF8_MASK + 0U, // PseudoVFNMSAC_VF16_M1 + 0U, // PseudoVFNMSAC_VF16_M1_MASK + 0U, // PseudoVFNMSAC_VF16_M2 + 0U, // PseudoVFNMSAC_VF16_M2_MASK + 0U, // PseudoVFNMSAC_VF16_M4 + 0U, // PseudoVFNMSAC_VF16_M4_MASK + 0U, // PseudoVFNMSAC_VF16_M8 + 0U, // PseudoVFNMSAC_VF16_M8_MASK + 0U, // PseudoVFNMSAC_VF16_MF2 + 0U, // PseudoVFNMSAC_VF16_MF2_MASK + 0U, // PseudoVFNMSAC_VF16_MF4 + 0U, // PseudoVFNMSAC_VF16_MF4_MASK + 0U, // PseudoVFNMSAC_VF16_MF8 + 0U, // PseudoVFNMSAC_VF16_MF8_MASK + 0U, // PseudoVFNMSAC_VF32_M1 + 0U, // PseudoVFNMSAC_VF32_M1_MASK + 0U, // PseudoVFNMSAC_VF32_M2 + 0U, // PseudoVFNMSAC_VF32_M2_MASK + 0U, // PseudoVFNMSAC_VF32_M4 + 0U, // PseudoVFNMSAC_VF32_M4_MASK + 0U, // PseudoVFNMSAC_VF32_M8 + 0U, // PseudoVFNMSAC_VF32_M8_MASK + 0U, // PseudoVFNMSAC_VF32_MF2 + 0U, // PseudoVFNMSAC_VF32_MF2_MASK + 0U, // PseudoVFNMSAC_VF32_MF4 + 0U, // PseudoVFNMSAC_VF32_MF4_MASK + 0U, // PseudoVFNMSAC_VF32_MF8 + 0U, // PseudoVFNMSAC_VF32_MF8_MASK + 0U, // PseudoVFNMSAC_VF64_M1 + 0U, // PseudoVFNMSAC_VF64_M1_MASK + 0U, // PseudoVFNMSAC_VF64_M2 + 0U, // PseudoVFNMSAC_VF64_M2_MASK + 0U, // PseudoVFNMSAC_VF64_M4 + 0U, // PseudoVFNMSAC_VF64_M4_MASK + 0U, // PseudoVFNMSAC_VF64_M8 + 0U, // PseudoVFNMSAC_VF64_M8_MASK + 0U, // PseudoVFNMSAC_VF64_MF2 + 0U, // PseudoVFNMSAC_VF64_MF2_MASK + 0U, // PseudoVFNMSAC_VF64_MF4 + 0U, // PseudoVFNMSAC_VF64_MF4_MASK + 0U, // PseudoVFNMSAC_VF64_MF8 + 0U, // PseudoVFNMSAC_VF64_MF8_MASK + 0U, // PseudoVFNMSAC_VV_M1 + 0U, // PseudoVFNMSAC_VV_M1_MASK + 0U, // PseudoVFNMSAC_VV_M2 + 0U, // PseudoVFNMSAC_VV_M2_MASK + 0U, // PseudoVFNMSAC_VV_M4 + 0U, // PseudoVFNMSAC_VV_M4_MASK + 0U, // PseudoVFNMSAC_VV_M8 + 0U, // PseudoVFNMSAC_VV_M8_MASK + 0U, // PseudoVFNMSAC_VV_MF2 + 0U, // PseudoVFNMSAC_VV_MF2_MASK + 0U, // PseudoVFNMSAC_VV_MF4 + 0U, // PseudoVFNMSAC_VV_MF4_MASK + 0U, // PseudoVFNMSAC_VV_MF8 + 0U, // PseudoVFNMSAC_VV_MF8_MASK + 0U, // PseudoVFNMSUB_VF16_M1 + 0U, // PseudoVFNMSUB_VF16_M1_MASK + 0U, // PseudoVFNMSUB_VF16_M2 + 0U, // PseudoVFNMSUB_VF16_M2_MASK + 0U, // PseudoVFNMSUB_VF16_M4 + 0U, // PseudoVFNMSUB_VF16_M4_MASK + 0U, // PseudoVFNMSUB_VF16_M8 + 0U, // PseudoVFNMSUB_VF16_M8_MASK + 0U, // PseudoVFNMSUB_VF16_MF2 + 0U, // PseudoVFNMSUB_VF16_MF2_MASK + 0U, // PseudoVFNMSUB_VF16_MF4 + 0U, // PseudoVFNMSUB_VF16_MF4_MASK + 0U, // PseudoVFNMSUB_VF16_MF8 + 0U, // PseudoVFNMSUB_VF16_MF8_MASK + 0U, // PseudoVFNMSUB_VF32_M1 + 0U, // PseudoVFNMSUB_VF32_M1_MASK + 0U, // PseudoVFNMSUB_VF32_M2 + 0U, // PseudoVFNMSUB_VF32_M2_MASK + 0U, // PseudoVFNMSUB_VF32_M4 + 0U, // PseudoVFNMSUB_VF32_M4_MASK + 0U, // PseudoVFNMSUB_VF32_M8 + 0U, // PseudoVFNMSUB_VF32_M8_MASK + 0U, // PseudoVFNMSUB_VF32_MF2 + 0U, // PseudoVFNMSUB_VF32_MF2_MASK + 0U, // PseudoVFNMSUB_VF32_MF4 + 0U, // PseudoVFNMSUB_VF32_MF4_MASK + 0U, // PseudoVFNMSUB_VF32_MF8 + 0U, // PseudoVFNMSUB_VF32_MF8_MASK + 0U, // PseudoVFNMSUB_VF64_M1 + 0U, // PseudoVFNMSUB_VF64_M1_MASK + 0U, // PseudoVFNMSUB_VF64_M2 + 0U, // PseudoVFNMSUB_VF64_M2_MASK + 0U, // PseudoVFNMSUB_VF64_M4 + 0U, // PseudoVFNMSUB_VF64_M4_MASK + 0U, // PseudoVFNMSUB_VF64_M8 + 0U, // PseudoVFNMSUB_VF64_M8_MASK + 0U, // PseudoVFNMSUB_VF64_MF2 + 0U, // PseudoVFNMSUB_VF64_MF2_MASK + 0U, // PseudoVFNMSUB_VF64_MF4 + 0U, // PseudoVFNMSUB_VF64_MF4_MASK + 0U, // PseudoVFNMSUB_VF64_MF8 + 0U, // PseudoVFNMSUB_VF64_MF8_MASK + 0U, // PseudoVFNMSUB_VV_M1 + 0U, // PseudoVFNMSUB_VV_M1_MASK + 0U, // PseudoVFNMSUB_VV_M2 + 0U, // PseudoVFNMSUB_VV_M2_MASK + 0U, // PseudoVFNMSUB_VV_M4 + 0U, // PseudoVFNMSUB_VV_M4_MASK + 0U, // PseudoVFNMSUB_VV_M8 + 0U, // PseudoVFNMSUB_VV_M8_MASK + 0U, // PseudoVFNMSUB_VV_MF2 + 0U, // PseudoVFNMSUB_VV_MF2_MASK + 0U, // PseudoVFNMSUB_VV_MF4 + 0U, // PseudoVFNMSUB_VV_MF4_MASK + 0U, // PseudoVFNMSUB_VV_MF8 + 0U, // PseudoVFNMSUB_VV_MF8_MASK + 0U, // PseudoVFRDIV_VF16_M1 + 0U, // PseudoVFRDIV_VF16_M1_MASK + 0U, // PseudoVFRDIV_VF16_M2 + 0U, // PseudoVFRDIV_VF16_M2_MASK + 0U, // PseudoVFRDIV_VF16_M4 + 0U, // PseudoVFRDIV_VF16_M4_MASK + 0U, // PseudoVFRDIV_VF16_M8 + 0U, // PseudoVFRDIV_VF16_M8_MASK + 0U, // PseudoVFRDIV_VF16_MF2 + 0U, // PseudoVFRDIV_VF16_MF2_MASK + 0U, // PseudoVFRDIV_VF16_MF4 + 0U, // PseudoVFRDIV_VF16_MF4_MASK + 0U, // PseudoVFRDIV_VF16_MF8 + 0U, // PseudoVFRDIV_VF16_MF8_MASK + 0U, // PseudoVFRDIV_VF32_M1 + 0U, // PseudoVFRDIV_VF32_M1_MASK + 0U, // PseudoVFRDIV_VF32_M2 + 0U, // PseudoVFRDIV_VF32_M2_MASK + 0U, // PseudoVFRDIV_VF32_M4 + 0U, // PseudoVFRDIV_VF32_M4_MASK + 0U, // PseudoVFRDIV_VF32_M8 + 0U, // PseudoVFRDIV_VF32_M8_MASK + 0U, // PseudoVFRDIV_VF32_MF2 + 0U, // PseudoVFRDIV_VF32_MF2_MASK + 0U, // PseudoVFRDIV_VF32_MF4 + 0U, // PseudoVFRDIV_VF32_MF4_MASK + 0U, // PseudoVFRDIV_VF32_MF8 + 0U, // PseudoVFRDIV_VF32_MF8_MASK + 0U, // PseudoVFRDIV_VF64_M1 + 0U, // PseudoVFRDIV_VF64_M1_MASK + 0U, // PseudoVFRDIV_VF64_M2 + 0U, // PseudoVFRDIV_VF64_M2_MASK + 0U, // PseudoVFRDIV_VF64_M4 + 0U, // PseudoVFRDIV_VF64_M4_MASK + 0U, // PseudoVFRDIV_VF64_M8 + 0U, // PseudoVFRDIV_VF64_M8_MASK + 0U, // PseudoVFRDIV_VF64_MF2 + 0U, // PseudoVFRDIV_VF64_MF2_MASK + 0U, // PseudoVFRDIV_VF64_MF4 + 0U, // PseudoVFRDIV_VF64_MF4_MASK + 0U, // PseudoVFRDIV_VF64_MF8 + 0U, // PseudoVFRDIV_VF64_MF8_MASK + 0U, // PseudoVFREC7_V_M1 + 0U, // PseudoVFREC7_V_M1_MASK + 0U, // PseudoVFREC7_V_M2 + 0U, // PseudoVFREC7_V_M2_MASK + 0U, // PseudoVFREC7_V_M4 + 0U, // PseudoVFREC7_V_M4_MASK + 0U, // PseudoVFREC7_V_M8 + 0U, // PseudoVFREC7_V_M8_MASK + 0U, // PseudoVFREC7_V_MF2 + 0U, // PseudoVFREC7_V_MF2_MASK + 0U, // PseudoVFREC7_V_MF4 + 0U, // PseudoVFREC7_V_MF4_MASK + 0U, // PseudoVFREC7_V_MF8 + 0U, // PseudoVFREC7_V_MF8_MASK + 0U, // PseudoVFREDMAX_VS_M1 + 0U, // PseudoVFREDMAX_VS_M1_MASK + 0U, // PseudoVFREDMAX_VS_M2 + 0U, // PseudoVFREDMAX_VS_M2_MASK + 0U, // PseudoVFREDMAX_VS_M4 + 0U, // PseudoVFREDMAX_VS_M4_MASK + 0U, // PseudoVFREDMAX_VS_M8 + 0U, // PseudoVFREDMAX_VS_M8_MASK + 0U, // PseudoVFREDMAX_VS_MF2 + 0U, // PseudoVFREDMAX_VS_MF2_MASK + 0U, // PseudoVFREDMAX_VS_MF4 + 0U, // PseudoVFREDMAX_VS_MF4_MASK + 0U, // PseudoVFREDMAX_VS_MF8 + 0U, // PseudoVFREDMAX_VS_MF8_MASK + 0U, // PseudoVFREDMIN_VS_M1 + 0U, // PseudoVFREDMIN_VS_M1_MASK + 0U, // PseudoVFREDMIN_VS_M2 + 0U, // PseudoVFREDMIN_VS_M2_MASK + 0U, // PseudoVFREDMIN_VS_M4 + 0U, // PseudoVFREDMIN_VS_M4_MASK + 0U, // PseudoVFREDMIN_VS_M8 + 0U, // PseudoVFREDMIN_VS_M8_MASK + 0U, // PseudoVFREDMIN_VS_MF2 + 0U, // PseudoVFREDMIN_VS_MF2_MASK + 0U, // PseudoVFREDMIN_VS_MF4 + 0U, // PseudoVFREDMIN_VS_MF4_MASK + 0U, // PseudoVFREDMIN_VS_MF8 + 0U, // PseudoVFREDMIN_VS_MF8_MASK + 0U, // PseudoVFREDOSUM_VS_M1 + 0U, // PseudoVFREDOSUM_VS_M1_MASK + 0U, // PseudoVFREDOSUM_VS_M2 + 0U, // PseudoVFREDOSUM_VS_M2_MASK + 0U, // PseudoVFREDOSUM_VS_M4 + 0U, // PseudoVFREDOSUM_VS_M4_MASK + 0U, // PseudoVFREDOSUM_VS_M8 + 0U, // PseudoVFREDOSUM_VS_M8_MASK + 0U, // PseudoVFREDOSUM_VS_MF2 + 0U, // PseudoVFREDOSUM_VS_MF2_MASK + 0U, // PseudoVFREDOSUM_VS_MF4 + 0U, // PseudoVFREDOSUM_VS_MF4_MASK + 0U, // PseudoVFREDOSUM_VS_MF8 + 0U, // PseudoVFREDOSUM_VS_MF8_MASK + 0U, // PseudoVFREDUSUM_VS_M1 + 0U, // PseudoVFREDUSUM_VS_M1_MASK + 0U, // PseudoVFREDUSUM_VS_M2 + 0U, // PseudoVFREDUSUM_VS_M2_MASK + 0U, // PseudoVFREDUSUM_VS_M4 + 0U, // PseudoVFREDUSUM_VS_M4_MASK + 0U, // PseudoVFREDUSUM_VS_M8 + 0U, // PseudoVFREDUSUM_VS_M8_MASK + 0U, // PseudoVFREDUSUM_VS_MF2 + 0U, // PseudoVFREDUSUM_VS_MF2_MASK + 0U, // PseudoVFREDUSUM_VS_MF4 + 0U, // PseudoVFREDUSUM_VS_MF4_MASK + 0U, // PseudoVFREDUSUM_VS_MF8 + 0U, // PseudoVFREDUSUM_VS_MF8_MASK + 0U, // PseudoVFRSQRT7_V_M1 + 0U, // PseudoVFRSQRT7_V_M1_MASK + 0U, // PseudoVFRSQRT7_V_M2 + 0U, // PseudoVFRSQRT7_V_M2_MASK + 0U, // PseudoVFRSQRT7_V_M4 + 0U, // PseudoVFRSQRT7_V_M4_MASK + 0U, // PseudoVFRSQRT7_V_M8 + 0U, // PseudoVFRSQRT7_V_M8_MASK + 0U, // PseudoVFRSQRT7_V_MF2 + 0U, // PseudoVFRSQRT7_V_MF2_MASK + 0U, // PseudoVFRSQRT7_V_MF4 + 0U, // PseudoVFRSQRT7_V_MF4_MASK + 0U, // PseudoVFRSQRT7_V_MF8 + 0U, // PseudoVFRSQRT7_V_MF8_MASK + 0U, // PseudoVFRSUB_VF16_M1 + 0U, // PseudoVFRSUB_VF16_M1_MASK + 0U, // PseudoVFRSUB_VF16_M2 + 0U, // PseudoVFRSUB_VF16_M2_MASK + 0U, // PseudoVFRSUB_VF16_M4 + 0U, // PseudoVFRSUB_VF16_M4_MASK + 0U, // PseudoVFRSUB_VF16_M8 + 0U, // PseudoVFRSUB_VF16_M8_MASK + 0U, // PseudoVFRSUB_VF16_MF2 + 0U, // PseudoVFRSUB_VF16_MF2_MASK + 0U, // PseudoVFRSUB_VF16_MF4 + 0U, // PseudoVFRSUB_VF16_MF4_MASK + 0U, // PseudoVFRSUB_VF16_MF8 + 0U, // PseudoVFRSUB_VF16_MF8_MASK + 0U, // PseudoVFRSUB_VF32_M1 + 0U, // PseudoVFRSUB_VF32_M1_MASK + 0U, // PseudoVFRSUB_VF32_M2 + 0U, // PseudoVFRSUB_VF32_M2_MASK + 0U, // PseudoVFRSUB_VF32_M4 + 0U, // PseudoVFRSUB_VF32_M4_MASK + 0U, // PseudoVFRSUB_VF32_M8 + 0U, // PseudoVFRSUB_VF32_M8_MASK + 0U, // PseudoVFRSUB_VF32_MF2 + 0U, // PseudoVFRSUB_VF32_MF2_MASK + 0U, // PseudoVFRSUB_VF32_MF4 + 0U, // PseudoVFRSUB_VF32_MF4_MASK + 0U, // PseudoVFRSUB_VF32_MF8 + 0U, // PseudoVFRSUB_VF32_MF8_MASK + 0U, // PseudoVFRSUB_VF64_M1 + 0U, // PseudoVFRSUB_VF64_M1_MASK + 0U, // PseudoVFRSUB_VF64_M2 + 0U, // PseudoVFRSUB_VF64_M2_MASK + 0U, // PseudoVFRSUB_VF64_M4 + 0U, // PseudoVFRSUB_VF64_M4_MASK + 0U, // PseudoVFRSUB_VF64_M8 + 0U, // PseudoVFRSUB_VF64_M8_MASK + 0U, // PseudoVFRSUB_VF64_MF2 + 0U, // PseudoVFRSUB_VF64_MF2_MASK + 0U, // PseudoVFRSUB_VF64_MF4 + 0U, // PseudoVFRSUB_VF64_MF4_MASK + 0U, // PseudoVFRSUB_VF64_MF8 + 0U, // PseudoVFRSUB_VF64_MF8_MASK + 0U, // PseudoVFSGNJN_VF16_M1 + 0U, // PseudoVFSGNJN_VF16_M1_MASK + 0U, // PseudoVFSGNJN_VF16_M2 + 0U, // PseudoVFSGNJN_VF16_M2_MASK + 0U, // PseudoVFSGNJN_VF16_M4 + 0U, // PseudoVFSGNJN_VF16_M4_MASK + 0U, // PseudoVFSGNJN_VF16_M8 + 0U, // PseudoVFSGNJN_VF16_M8_MASK + 0U, // PseudoVFSGNJN_VF16_MF2 + 0U, // PseudoVFSGNJN_VF16_MF2_MASK + 0U, // PseudoVFSGNJN_VF16_MF4 + 0U, // PseudoVFSGNJN_VF16_MF4_MASK + 0U, // PseudoVFSGNJN_VF16_MF8 + 0U, // PseudoVFSGNJN_VF16_MF8_MASK + 0U, // PseudoVFSGNJN_VF32_M1 + 0U, // PseudoVFSGNJN_VF32_M1_MASK + 0U, // PseudoVFSGNJN_VF32_M2 + 0U, // PseudoVFSGNJN_VF32_M2_MASK + 0U, // PseudoVFSGNJN_VF32_M4 + 0U, // PseudoVFSGNJN_VF32_M4_MASK + 0U, // PseudoVFSGNJN_VF32_M8 + 0U, // PseudoVFSGNJN_VF32_M8_MASK + 0U, // PseudoVFSGNJN_VF32_MF2 + 0U, // PseudoVFSGNJN_VF32_MF2_MASK + 0U, // PseudoVFSGNJN_VF32_MF4 + 0U, // PseudoVFSGNJN_VF32_MF4_MASK + 0U, // PseudoVFSGNJN_VF32_MF8 + 0U, // PseudoVFSGNJN_VF32_MF8_MASK + 0U, // PseudoVFSGNJN_VF64_M1 + 0U, // PseudoVFSGNJN_VF64_M1_MASK + 0U, // PseudoVFSGNJN_VF64_M2 + 0U, // PseudoVFSGNJN_VF64_M2_MASK + 0U, // PseudoVFSGNJN_VF64_M4 + 0U, // PseudoVFSGNJN_VF64_M4_MASK + 0U, // PseudoVFSGNJN_VF64_M8 + 0U, // PseudoVFSGNJN_VF64_M8_MASK + 0U, // PseudoVFSGNJN_VF64_MF2 + 0U, // PseudoVFSGNJN_VF64_MF2_MASK + 0U, // PseudoVFSGNJN_VF64_MF4 + 0U, // PseudoVFSGNJN_VF64_MF4_MASK + 0U, // PseudoVFSGNJN_VF64_MF8 + 0U, // PseudoVFSGNJN_VF64_MF8_MASK + 0U, // PseudoVFSGNJN_VV_M1 + 0U, // PseudoVFSGNJN_VV_M1_MASK + 0U, // PseudoVFSGNJN_VV_M2 + 0U, // PseudoVFSGNJN_VV_M2_MASK + 0U, // PseudoVFSGNJN_VV_M4 + 0U, // PseudoVFSGNJN_VV_M4_MASK + 0U, // PseudoVFSGNJN_VV_M8 + 0U, // PseudoVFSGNJN_VV_M8_MASK + 0U, // PseudoVFSGNJN_VV_MF2 + 0U, // PseudoVFSGNJN_VV_MF2_MASK + 0U, // PseudoVFSGNJN_VV_MF4 + 0U, // PseudoVFSGNJN_VV_MF4_MASK + 0U, // PseudoVFSGNJN_VV_MF8 + 0U, // PseudoVFSGNJN_VV_MF8_MASK + 0U, // PseudoVFSGNJX_VF16_M1 + 0U, // PseudoVFSGNJX_VF16_M1_MASK + 0U, // PseudoVFSGNJX_VF16_M2 + 0U, // PseudoVFSGNJX_VF16_M2_MASK + 0U, // PseudoVFSGNJX_VF16_M4 + 0U, // PseudoVFSGNJX_VF16_M4_MASK + 0U, // PseudoVFSGNJX_VF16_M8 + 0U, // PseudoVFSGNJX_VF16_M8_MASK + 0U, // PseudoVFSGNJX_VF16_MF2 + 0U, // PseudoVFSGNJX_VF16_MF2_MASK + 0U, // PseudoVFSGNJX_VF16_MF4 + 0U, // PseudoVFSGNJX_VF16_MF4_MASK + 0U, // PseudoVFSGNJX_VF16_MF8 + 0U, // PseudoVFSGNJX_VF16_MF8_MASK + 0U, // PseudoVFSGNJX_VF32_M1 + 0U, // PseudoVFSGNJX_VF32_M1_MASK + 0U, // PseudoVFSGNJX_VF32_M2 + 0U, // PseudoVFSGNJX_VF32_M2_MASK + 0U, // PseudoVFSGNJX_VF32_M4 + 0U, // PseudoVFSGNJX_VF32_M4_MASK + 0U, // PseudoVFSGNJX_VF32_M8 + 0U, // PseudoVFSGNJX_VF32_M8_MASK + 0U, // PseudoVFSGNJX_VF32_MF2 + 0U, // PseudoVFSGNJX_VF32_MF2_MASK + 0U, // PseudoVFSGNJX_VF32_MF4 + 0U, // PseudoVFSGNJX_VF32_MF4_MASK + 0U, // PseudoVFSGNJX_VF32_MF8 + 0U, // PseudoVFSGNJX_VF32_MF8_MASK + 0U, // PseudoVFSGNJX_VF64_M1 + 0U, // PseudoVFSGNJX_VF64_M1_MASK + 0U, // PseudoVFSGNJX_VF64_M2 + 0U, // PseudoVFSGNJX_VF64_M2_MASK + 0U, // PseudoVFSGNJX_VF64_M4 + 0U, // PseudoVFSGNJX_VF64_M4_MASK + 0U, // PseudoVFSGNJX_VF64_M8 + 0U, // PseudoVFSGNJX_VF64_M8_MASK + 0U, // PseudoVFSGNJX_VF64_MF2 + 0U, // PseudoVFSGNJX_VF64_MF2_MASK + 0U, // PseudoVFSGNJX_VF64_MF4 + 0U, // PseudoVFSGNJX_VF64_MF4_MASK + 0U, // PseudoVFSGNJX_VF64_MF8 + 0U, // PseudoVFSGNJX_VF64_MF8_MASK + 0U, // PseudoVFSGNJX_VV_M1 + 0U, // PseudoVFSGNJX_VV_M1_MASK + 0U, // PseudoVFSGNJX_VV_M2 + 0U, // PseudoVFSGNJX_VV_M2_MASK + 0U, // PseudoVFSGNJX_VV_M4 + 0U, // PseudoVFSGNJX_VV_M4_MASK + 0U, // PseudoVFSGNJX_VV_M8 + 0U, // PseudoVFSGNJX_VV_M8_MASK + 0U, // PseudoVFSGNJX_VV_MF2 + 0U, // PseudoVFSGNJX_VV_MF2_MASK + 0U, // PseudoVFSGNJX_VV_MF4 + 0U, // PseudoVFSGNJX_VV_MF4_MASK + 0U, // PseudoVFSGNJX_VV_MF8 + 0U, // PseudoVFSGNJX_VV_MF8_MASK + 0U, // PseudoVFSGNJ_VF16_M1 + 0U, // PseudoVFSGNJ_VF16_M1_MASK + 0U, // PseudoVFSGNJ_VF16_M2 + 0U, // PseudoVFSGNJ_VF16_M2_MASK + 0U, // PseudoVFSGNJ_VF16_M4 + 0U, // PseudoVFSGNJ_VF16_M4_MASK + 0U, // PseudoVFSGNJ_VF16_M8 + 0U, // PseudoVFSGNJ_VF16_M8_MASK + 0U, // PseudoVFSGNJ_VF16_MF2 + 0U, // PseudoVFSGNJ_VF16_MF2_MASK + 0U, // PseudoVFSGNJ_VF16_MF4 + 0U, // PseudoVFSGNJ_VF16_MF4_MASK + 0U, // PseudoVFSGNJ_VF16_MF8 + 0U, // PseudoVFSGNJ_VF16_MF8_MASK + 0U, // PseudoVFSGNJ_VF32_M1 + 0U, // PseudoVFSGNJ_VF32_M1_MASK + 0U, // PseudoVFSGNJ_VF32_M2 + 0U, // PseudoVFSGNJ_VF32_M2_MASK + 0U, // PseudoVFSGNJ_VF32_M4 + 0U, // PseudoVFSGNJ_VF32_M4_MASK + 0U, // PseudoVFSGNJ_VF32_M8 + 0U, // PseudoVFSGNJ_VF32_M8_MASK + 0U, // PseudoVFSGNJ_VF32_MF2 + 0U, // PseudoVFSGNJ_VF32_MF2_MASK + 0U, // PseudoVFSGNJ_VF32_MF4 + 0U, // PseudoVFSGNJ_VF32_MF4_MASK + 0U, // PseudoVFSGNJ_VF32_MF8 + 0U, // PseudoVFSGNJ_VF32_MF8_MASK + 0U, // PseudoVFSGNJ_VF64_M1 + 0U, // PseudoVFSGNJ_VF64_M1_MASK + 0U, // PseudoVFSGNJ_VF64_M2 + 0U, // PseudoVFSGNJ_VF64_M2_MASK + 0U, // PseudoVFSGNJ_VF64_M4 + 0U, // PseudoVFSGNJ_VF64_M4_MASK + 0U, // PseudoVFSGNJ_VF64_M8 + 0U, // PseudoVFSGNJ_VF64_M8_MASK + 0U, // PseudoVFSGNJ_VF64_MF2 + 0U, // PseudoVFSGNJ_VF64_MF2_MASK + 0U, // PseudoVFSGNJ_VF64_MF4 + 0U, // PseudoVFSGNJ_VF64_MF4_MASK + 0U, // PseudoVFSGNJ_VF64_MF8 + 0U, // PseudoVFSGNJ_VF64_MF8_MASK + 0U, // PseudoVFSGNJ_VV_M1 + 0U, // PseudoVFSGNJ_VV_M1_MASK + 0U, // PseudoVFSGNJ_VV_M2 + 0U, // PseudoVFSGNJ_VV_M2_MASK + 0U, // PseudoVFSGNJ_VV_M4 + 0U, // PseudoVFSGNJ_VV_M4_MASK + 0U, // PseudoVFSGNJ_VV_M8 + 0U, // PseudoVFSGNJ_VV_M8_MASK + 0U, // PseudoVFSGNJ_VV_MF2 + 0U, // PseudoVFSGNJ_VV_MF2_MASK + 0U, // PseudoVFSGNJ_VV_MF4 + 0U, // PseudoVFSGNJ_VV_MF4_MASK + 0U, // PseudoVFSGNJ_VV_MF8 + 0U, // PseudoVFSGNJ_VV_MF8_MASK + 0U, // PseudoVFSLIDE1DOWN_VF16_M1 + 0U, // PseudoVFSLIDE1DOWN_VF16_M1_MASK + 0U, // PseudoVFSLIDE1DOWN_VF16_M2 + 0U, // PseudoVFSLIDE1DOWN_VF16_M2_MASK + 0U, // PseudoVFSLIDE1DOWN_VF16_M4 + 0U, // PseudoVFSLIDE1DOWN_VF16_M4_MASK + 0U, // PseudoVFSLIDE1DOWN_VF16_M8 + 0U, // PseudoVFSLIDE1DOWN_VF16_M8_MASK + 0U, // PseudoVFSLIDE1DOWN_VF16_MF2 + 0U, // PseudoVFSLIDE1DOWN_VF16_MF2_MASK + 0U, // PseudoVFSLIDE1DOWN_VF16_MF4 + 0U, // PseudoVFSLIDE1DOWN_VF16_MF4_MASK + 0U, // PseudoVFSLIDE1DOWN_VF16_MF8 + 0U, // PseudoVFSLIDE1DOWN_VF16_MF8_MASK + 0U, // PseudoVFSLIDE1DOWN_VF32_M1 + 0U, // PseudoVFSLIDE1DOWN_VF32_M1_MASK + 0U, // PseudoVFSLIDE1DOWN_VF32_M2 + 0U, // PseudoVFSLIDE1DOWN_VF32_M2_MASK + 0U, // PseudoVFSLIDE1DOWN_VF32_M4 + 0U, // PseudoVFSLIDE1DOWN_VF32_M4_MASK + 0U, // PseudoVFSLIDE1DOWN_VF32_M8 + 0U, // PseudoVFSLIDE1DOWN_VF32_M8_MASK + 0U, // PseudoVFSLIDE1DOWN_VF32_MF2 + 0U, // PseudoVFSLIDE1DOWN_VF32_MF2_MASK + 0U, // PseudoVFSLIDE1DOWN_VF32_MF4 + 0U, // PseudoVFSLIDE1DOWN_VF32_MF4_MASK + 0U, // PseudoVFSLIDE1DOWN_VF32_MF8 + 0U, // PseudoVFSLIDE1DOWN_VF32_MF8_MASK + 0U, // PseudoVFSLIDE1DOWN_VF64_M1 + 0U, // PseudoVFSLIDE1DOWN_VF64_M1_MASK + 0U, // PseudoVFSLIDE1DOWN_VF64_M2 + 0U, // PseudoVFSLIDE1DOWN_VF64_M2_MASK + 0U, // PseudoVFSLIDE1DOWN_VF64_M4 + 0U, // PseudoVFSLIDE1DOWN_VF64_M4_MASK + 0U, // PseudoVFSLIDE1DOWN_VF64_M8 + 0U, // PseudoVFSLIDE1DOWN_VF64_M8_MASK + 0U, // PseudoVFSLIDE1DOWN_VF64_MF2 + 0U, // PseudoVFSLIDE1DOWN_VF64_MF2_MASK + 0U, // PseudoVFSLIDE1DOWN_VF64_MF4 + 0U, // PseudoVFSLIDE1DOWN_VF64_MF4_MASK + 0U, // PseudoVFSLIDE1DOWN_VF64_MF8 + 0U, // PseudoVFSLIDE1DOWN_VF64_MF8_MASK + 0U, // PseudoVFSLIDE1UP_VF16_M1 + 0U, // PseudoVFSLIDE1UP_VF16_M1_MASK + 0U, // PseudoVFSLIDE1UP_VF16_M2 + 0U, // PseudoVFSLIDE1UP_VF16_M2_MASK + 0U, // PseudoVFSLIDE1UP_VF16_M4 + 0U, // PseudoVFSLIDE1UP_VF16_M4_MASK + 0U, // PseudoVFSLIDE1UP_VF16_M8 + 0U, // PseudoVFSLIDE1UP_VF16_M8_MASK + 0U, // PseudoVFSLIDE1UP_VF16_MF2 + 0U, // PseudoVFSLIDE1UP_VF16_MF2_MASK + 0U, // PseudoVFSLIDE1UP_VF16_MF4 + 0U, // PseudoVFSLIDE1UP_VF16_MF4_MASK + 0U, // PseudoVFSLIDE1UP_VF16_MF8 + 0U, // PseudoVFSLIDE1UP_VF16_MF8_MASK + 0U, // PseudoVFSLIDE1UP_VF32_M1 + 0U, // PseudoVFSLIDE1UP_VF32_M1_MASK + 0U, // PseudoVFSLIDE1UP_VF32_M2 + 0U, // PseudoVFSLIDE1UP_VF32_M2_MASK + 0U, // PseudoVFSLIDE1UP_VF32_M4 + 0U, // PseudoVFSLIDE1UP_VF32_M4_MASK + 0U, // PseudoVFSLIDE1UP_VF32_M8 + 0U, // PseudoVFSLIDE1UP_VF32_M8_MASK + 0U, // PseudoVFSLIDE1UP_VF32_MF2 + 0U, // PseudoVFSLIDE1UP_VF32_MF2_MASK + 0U, // PseudoVFSLIDE1UP_VF32_MF4 + 0U, // PseudoVFSLIDE1UP_VF32_MF4_MASK + 0U, // PseudoVFSLIDE1UP_VF32_MF8 + 0U, // PseudoVFSLIDE1UP_VF32_MF8_MASK + 0U, // PseudoVFSLIDE1UP_VF64_M1 + 0U, // PseudoVFSLIDE1UP_VF64_M1_MASK + 0U, // PseudoVFSLIDE1UP_VF64_M2 + 0U, // PseudoVFSLIDE1UP_VF64_M2_MASK + 0U, // PseudoVFSLIDE1UP_VF64_M4 + 0U, // PseudoVFSLIDE1UP_VF64_M4_MASK + 0U, // PseudoVFSLIDE1UP_VF64_M8 + 0U, // PseudoVFSLIDE1UP_VF64_M8_MASK + 0U, // PseudoVFSLIDE1UP_VF64_MF2 + 0U, // PseudoVFSLIDE1UP_VF64_MF2_MASK + 0U, // PseudoVFSLIDE1UP_VF64_MF4 + 0U, // PseudoVFSLIDE1UP_VF64_MF4_MASK + 0U, // PseudoVFSLIDE1UP_VF64_MF8 + 0U, // PseudoVFSLIDE1UP_VF64_MF8_MASK + 0U, // PseudoVFSQRT_V_M1 + 0U, // PseudoVFSQRT_V_M1_MASK + 0U, // PseudoVFSQRT_V_M2 + 0U, // PseudoVFSQRT_V_M2_MASK + 0U, // PseudoVFSQRT_V_M4 + 0U, // PseudoVFSQRT_V_M4_MASK + 0U, // PseudoVFSQRT_V_M8 + 0U, // PseudoVFSQRT_V_M8_MASK + 0U, // PseudoVFSQRT_V_MF2 + 0U, // PseudoVFSQRT_V_MF2_MASK + 0U, // PseudoVFSQRT_V_MF4 + 0U, // PseudoVFSQRT_V_MF4_MASK + 0U, // PseudoVFSQRT_V_MF8 + 0U, // PseudoVFSQRT_V_MF8_MASK + 0U, // PseudoVFSUB_VF16_M1 + 0U, // PseudoVFSUB_VF16_M1_MASK + 0U, // PseudoVFSUB_VF16_M2 + 0U, // PseudoVFSUB_VF16_M2_MASK + 0U, // PseudoVFSUB_VF16_M4 + 0U, // PseudoVFSUB_VF16_M4_MASK + 0U, // PseudoVFSUB_VF16_M8 + 0U, // PseudoVFSUB_VF16_M8_MASK + 0U, // PseudoVFSUB_VF16_MF2 + 0U, // PseudoVFSUB_VF16_MF2_MASK + 0U, // PseudoVFSUB_VF16_MF4 + 0U, // PseudoVFSUB_VF16_MF4_MASK + 0U, // PseudoVFSUB_VF16_MF8 + 0U, // PseudoVFSUB_VF16_MF8_MASK + 0U, // PseudoVFSUB_VF32_M1 + 0U, // PseudoVFSUB_VF32_M1_MASK + 0U, // PseudoVFSUB_VF32_M2 + 0U, // PseudoVFSUB_VF32_M2_MASK + 0U, // PseudoVFSUB_VF32_M4 + 0U, // PseudoVFSUB_VF32_M4_MASK + 0U, // PseudoVFSUB_VF32_M8 + 0U, // PseudoVFSUB_VF32_M8_MASK + 0U, // PseudoVFSUB_VF32_MF2 + 0U, // PseudoVFSUB_VF32_MF2_MASK + 0U, // PseudoVFSUB_VF32_MF4 + 0U, // PseudoVFSUB_VF32_MF4_MASK + 0U, // PseudoVFSUB_VF32_MF8 + 0U, // PseudoVFSUB_VF32_MF8_MASK + 0U, // PseudoVFSUB_VF64_M1 + 0U, // PseudoVFSUB_VF64_M1_MASK + 0U, // PseudoVFSUB_VF64_M2 + 0U, // PseudoVFSUB_VF64_M2_MASK + 0U, // PseudoVFSUB_VF64_M4 + 0U, // PseudoVFSUB_VF64_M4_MASK + 0U, // PseudoVFSUB_VF64_M8 + 0U, // PseudoVFSUB_VF64_M8_MASK + 0U, // PseudoVFSUB_VF64_MF2 + 0U, // PseudoVFSUB_VF64_MF2_MASK + 0U, // PseudoVFSUB_VF64_MF4 + 0U, // PseudoVFSUB_VF64_MF4_MASK + 0U, // PseudoVFSUB_VF64_MF8 + 0U, // PseudoVFSUB_VF64_MF8_MASK + 0U, // PseudoVFSUB_VV_M1 + 0U, // PseudoVFSUB_VV_M1_MASK + 0U, // PseudoVFSUB_VV_M2 + 0U, // PseudoVFSUB_VV_M2_MASK + 0U, // PseudoVFSUB_VV_M4 + 0U, // PseudoVFSUB_VV_M4_MASK + 0U, // PseudoVFSUB_VV_M8 + 0U, // PseudoVFSUB_VV_M8_MASK + 0U, // PseudoVFSUB_VV_MF2 + 0U, // PseudoVFSUB_VV_MF2_MASK + 0U, // PseudoVFSUB_VV_MF4 + 0U, // PseudoVFSUB_VV_MF4_MASK + 0U, // PseudoVFSUB_VV_MF8 + 0U, // PseudoVFSUB_VV_MF8_MASK + 0U, // PseudoVFWADD_VF16_M1 + 0U, // PseudoVFWADD_VF16_M1_MASK + 0U, // PseudoVFWADD_VF16_M2 + 0U, // PseudoVFWADD_VF16_M2_MASK + 0U, // PseudoVFWADD_VF16_M4 + 0U, // PseudoVFWADD_VF16_M4_MASK + 0U, // PseudoVFWADD_VF16_MF2 + 0U, // PseudoVFWADD_VF16_MF2_MASK + 0U, // PseudoVFWADD_VF16_MF4 + 0U, // PseudoVFWADD_VF16_MF4_MASK + 0U, // PseudoVFWADD_VF16_MF8 + 0U, // PseudoVFWADD_VF16_MF8_MASK + 0U, // PseudoVFWADD_VF32_M1 + 0U, // PseudoVFWADD_VF32_M1_MASK + 0U, // PseudoVFWADD_VF32_M2 + 0U, // PseudoVFWADD_VF32_M2_MASK + 0U, // PseudoVFWADD_VF32_M4 + 0U, // PseudoVFWADD_VF32_M4_MASK + 0U, // PseudoVFWADD_VF32_MF2 + 0U, // PseudoVFWADD_VF32_MF2_MASK + 0U, // PseudoVFWADD_VF32_MF4 + 0U, // PseudoVFWADD_VF32_MF4_MASK + 0U, // PseudoVFWADD_VF32_MF8 + 0U, // PseudoVFWADD_VF32_MF8_MASK + 0U, // PseudoVFWADD_VV_M1 + 0U, // PseudoVFWADD_VV_M1_MASK + 0U, // PseudoVFWADD_VV_M2 + 0U, // PseudoVFWADD_VV_M2_MASK + 0U, // PseudoVFWADD_VV_M4 + 0U, // PseudoVFWADD_VV_M4_MASK + 0U, // PseudoVFWADD_VV_MF2 + 0U, // PseudoVFWADD_VV_MF2_MASK + 0U, // PseudoVFWADD_VV_MF4 + 0U, // PseudoVFWADD_VV_MF4_MASK + 0U, // PseudoVFWADD_VV_MF8 + 0U, // PseudoVFWADD_VV_MF8_MASK + 0U, // PseudoVFWADD_WF16_M1 + 0U, // PseudoVFWADD_WF16_M1_MASK + 0U, // PseudoVFWADD_WF16_M2 + 0U, // PseudoVFWADD_WF16_M2_MASK + 0U, // PseudoVFWADD_WF16_M4 + 0U, // PseudoVFWADD_WF16_M4_MASK + 0U, // PseudoVFWADD_WF16_MF2 + 0U, // PseudoVFWADD_WF16_MF2_MASK + 0U, // PseudoVFWADD_WF16_MF4 + 0U, // PseudoVFWADD_WF16_MF4_MASK + 0U, // PseudoVFWADD_WF16_MF8 + 0U, // PseudoVFWADD_WF16_MF8_MASK + 0U, // PseudoVFWADD_WF32_M1 + 0U, // PseudoVFWADD_WF32_M1_MASK + 0U, // PseudoVFWADD_WF32_M2 + 0U, // PseudoVFWADD_WF32_M2_MASK + 0U, // PseudoVFWADD_WF32_M4 + 0U, // PseudoVFWADD_WF32_M4_MASK + 0U, // PseudoVFWADD_WF32_MF2 + 0U, // PseudoVFWADD_WF32_MF2_MASK + 0U, // PseudoVFWADD_WF32_MF4 + 0U, // PseudoVFWADD_WF32_MF4_MASK + 0U, // PseudoVFWADD_WF32_MF8 + 0U, // PseudoVFWADD_WF32_MF8_MASK + 0U, // PseudoVFWADD_WV_M1 + 0U, // PseudoVFWADD_WV_M1_MASK + 0U, // PseudoVFWADD_WV_M1_MASK_TIED + 0U, // PseudoVFWADD_WV_M1_TIED + 0U, // PseudoVFWADD_WV_M2 + 0U, // PseudoVFWADD_WV_M2_MASK + 0U, // PseudoVFWADD_WV_M2_MASK_TIED + 0U, // PseudoVFWADD_WV_M2_TIED + 0U, // PseudoVFWADD_WV_M4 + 0U, // PseudoVFWADD_WV_M4_MASK + 0U, // PseudoVFWADD_WV_M4_MASK_TIED + 0U, // PseudoVFWADD_WV_M4_TIED + 0U, // PseudoVFWADD_WV_MF2 + 0U, // PseudoVFWADD_WV_MF2_MASK + 0U, // PseudoVFWADD_WV_MF2_MASK_TIED + 0U, // PseudoVFWADD_WV_MF2_TIED + 0U, // PseudoVFWADD_WV_MF4 + 0U, // PseudoVFWADD_WV_MF4_MASK + 0U, // PseudoVFWADD_WV_MF4_MASK_TIED + 0U, // PseudoVFWADD_WV_MF4_TIED + 0U, // PseudoVFWADD_WV_MF8 + 0U, // PseudoVFWADD_WV_MF8_MASK + 0U, // PseudoVFWADD_WV_MF8_MASK_TIED + 0U, // PseudoVFWADD_WV_MF8_TIED + 0U, // PseudoVFWCVT_F_F_V_M1 + 0U, // PseudoVFWCVT_F_F_V_M1_MASK + 0U, // PseudoVFWCVT_F_F_V_M2 + 0U, // PseudoVFWCVT_F_F_V_M2_MASK + 0U, // PseudoVFWCVT_F_F_V_M4 + 0U, // PseudoVFWCVT_F_F_V_M4_MASK + 0U, // PseudoVFWCVT_F_F_V_MF2 + 0U, // PseudoVFWCVT_F_F_V_MF2_MASK + 0U, // PseudoVFWCVT_F_F_V_MF4 + 0U, // PseudoVFWCVT_F_F_V_MF4_MASK + 0U, // PseudoVFWCVT_F_F_V_MF8 + 0U, // PseudoVFWCVT_F_F_V_MF8_MASK + 0U, // PseudoVFWCVT_F_XU_V_M1 + 0U, // PseudoVFWCVT_F_XU_V_M1_MASK + 0U, // PseudoVFWCVT_F_XU_V_M2 + 0U, // PseudoVFWCVT_F_XU_V_M2_MASK + 0U, // PseudoVFWCVT_F_XU_V_M4 + 0U, // PseudoVFWCVT_F_XU_V_M4_MASK + 0U, // PseudoVFWCVT_F_XU_V_MF2 + 0U, // PseudoVFWCVT_F_XU_V_MF2_MASK + 0U, // PseudoVFWCVT_F_XU_V_MF4 + 0U, // PseudoVFWCVT_F_XU_V_MF4_MASK + 0U, // PseudoVFWCVT_F_XU_V_MF8 + 0U, // PseudoVFWCVT_F_XU_V_MF8_MASK + 0U, // PseudoVFWCVT_F_X_V_M1 + 0U, // PseudoVFWCVT_F_X_V_M1_MASK + 0U, // PseudoVFWCVT_F_X_V_M2 + 0U, // PseudoVFWCVT_F_X_V_M2_MASK + 0U, // PseudoVFWCVT_F_X_V_M4 + 0U, // PseudoVFWCVT_F_X_V_M4_MASK + 0U, // PseudoVFWCVT_F_X_V_MF2 + 0U, // PseudoVFWCVT_F_X_V_MF2_MASK + 0U, // PseudoVFWCVT_F_X_V_MF4 + 0U, // PseudoVFWCVT_F_X_V_MF4_MASK + 0U, // PseudoVFWCVT_F_X_V_MF8 + 0U, // PseudoVFWCVT_F_X_V_MF8_MASK + 0U, // PseudoVFWCVT_RTZ_XU_F_V_M1 + 0U, // PseudoVFWCVT_RTZ_XU_F_V_M1_MASK + 0U, // PseudoVFWCVT_RTZ_XU_F_V_M2 + 0U, // PseudoVFWCVT_RTZ_XU_F_V_M2_MASK + 0U, // PseudoVFWCVT_RTZ_XU_F_V_M4 + 0U, // PseudoVFWCVT_RTZ_XU_F_V_M4_MASK + 0U, // PseudoVFWCVT_RTZ_XU_F_V_MF2 + 0U, // PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK + 0U, // PseudoVFWCVT_RTZ_XU_F_V_MF4 + 0U, // PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK + 0U, // PseudoVFWCVT_RTZ_XU_F_V_MF8 + 0U, // PseudoVFWCVT_RTZ_XU_F_V_MF8_MASK + 0U, // PseudoVFWCVT_RTZ_X_F_V_M1 + 0U, // PseudoVFWCVT_RTZ_X_F_V_M1_MASK + 0U, // PseudoVFWCVT_RTZ_X_F_V_M2 + 0U, // PseudoVFWCVT_RTZ_X_F_V_M2_MASK + 0U, // PseudoVFWCVT_RTZ_X_F_V_M4 + 0U, // PseudoVFWCVT_RTZ_X_F_V_M4_MASK + 0U, // PseudoVFWCVT_RTZ_X_F_V_MF2 + 0U, // PseudoVFWCVT_RTZ_X_F_V_MF2_MASK + 0U, // PseudoVFWCVT_RTZ_X_F_V_MF4 + 0U, // PseudoVFWCVT_RTZ_X_F_V_MF4_MASK + 0U, // PseudoVFWCVT_RTZ_X_F_V_MF8 + 0U, // PseudoVFWCVT_RTZ_X_F_V_MF8_MASK + 0U, // PseudoVFWCVT_XU_F_V_M1 + 0U, // PseudoVFWCVT_XU_F_V_M1_MASK + 0U, // PseudoVFWCVT_XU_F_V_M2 + 0U, // PseudoVFWCVT_XU_F_V_M2_MASK + 0U, // PseudoVFWCVT_XU_F_V_M4 + 0U, // PseudoVFWCVT_XU_F_V_M4_MASK + 0U, // PseudoVFWCVT_XU_F_V_MF2 + 0U, // PseudoVFWCVT_XU_F_V_MF2_MASK + 0U, // PseudoVFWCVT_XU_F_V_MF4 + 0U, // PseudoVFWCVT_XU_F_V_MF4_MASK + 0U, // PseudoVFWCVT_XU_F_V_MF8 + 0U, // PseudoVFWCVT_XU_F_V_MF8_MASK + 0U, // PseudoVFWCVT_X_F_V_M1 + 0U, // PseudoVFWCVT_X_F_V_M1_MASK + 0U, // PseudoVFWCVT_X_F_V_M2 + 0U, // PseudoVFWCVT_X_F_V_M2_MASK + 0U, // PseudoVFWCVT_X_F_V_M4 + 0U, // PseudoVFWCVT_X_F_V_M4_MASK + 0U, // PseudoVFWCVT_X_F_V_MF2 + 0U, // PseudoVFWCVT_X_F_V_MF2_MASK + 0U, // PseudoVFWCVT_X_F_V_MF4 + 0U, // PseudoVFWCVT_X_F_V_MF4_MASK + 0U, // PseudoVFWCVT_X_F_V_MF8 + 0U, // PseudoVFWCVT_X_F_V_MF8_MASK + 0U, // PseudoVFWMACC_VF16_M1 + 0U, // PseudoVFWMACC_VF16_M1_MASK + 0U, // PseudoVFWMACC_VF16_M2 + 0U, // PseudoVFWMACC_VF16_M2_MASK + 0U, // PseudoVFWMACC_VF16_M4 + 0U, // PseudoVFWMACC_VF16_M4_MASK + 0U, // PseudoVFWMACC_VF16_MF2 + 0U, // PseudoVFWMACC_VF16_MF2_MASK + 0U, // PseudoVFWMACC_VF16_MF4 + 0U, // PseudoVFWMACC_VF16_MF4_MASK + 0U, // PseudoVFWMACC_VF16_MF8 + 0U, // PseudoVFWMACC_VF16_MF8_MASK + 0U, // PseudoVFWMACC_VF32_M1 + 0U, // PseudoVFWMACC_VF32_M1_MASK + 0U, // PseudoVFWMACC_VF32_M2 + 0U, // PseudoVFWMACC_VF32_M2_MASK + 0U, // PseudoVFWMACC_VF32_M4 + 0U, // PseudoVFWMACC_VF32_M4_MASK + 0U, // PseudoVFWMACC_VF32_MF2 + 0U, // PseudoVFWMACC_VF32_MF2_MASK + 0U, // PseudoVFWMACC_VF32_MF4 + 0U, // PseudoVFWMACC_VF32_MF4_MASK + 0U, // PseudoVFWMACC_VF32_MF8 + 0U, // PseudoVFWMACC_VF32_MF8_MASK + 0U, // PseudoVFWMACC_VV_M1 + 0U, // PseudoVFWMACC_VV_M1_MASK + 0U, // PseudoVFWMACC_VV_M2 + 0U, // PseudoVFWMACC_VV_M2_MASK + 0U, // PseudoVFWMACC_VV_M4 + 0U, // PseudoVFWMACC_VV_M4_MASK + 0U, // PseudoVFWMACC_VV_MF2 + 0U, // PseudoVFWMACC_VV_MF2_MASK + 0U, // PseudoVFWMACC_VV_MF4 + 0U, // PseudoVFWMACC_VV_MF4_MASK + 0U, // PseudoVFWMACC_VV_MF8 + 0U, // PseudoVFWMACC_VV_MF8_MASK + 0U, // PseudoVFWMSAC_VF16_M1 + 0U, // PseudoVFWMSAC_VF16_M1_MASK + 0U, // PseudoVFWMSAC_VF16_M2 + 0U, // PseudoVFWMSAC_VF16_M2_MASK + 0U, // PseudoVFWMSAC_VF16_M4 + 0U, // PseudoVFWMSAC_VF16_M4_MASK + 0U, // PseudoVFWMSAC_VF16_MF2 + 0U, // PseudoVFWMSAC_VF16_MF2_MASK + 0U, // PseudoVFWMSAC_VF16_MF4 + 0U, // PseudoVFWMSAC_VF16_MF4_MASK + 0U, // PseudoVFWMSAC_VF16_MF8 + 0U, // PseudoVFWMSAC_VF16_MF8_MASK + 0U, // PseudoVFWMSAC_VF32_M1 + 0U, // PseudoVFWMSAC_VF32_M1_MASK + 0U, // PseudoVFWMSAC_VF32_M2 + 0U, // PseudoVFWMSAC_VF32_M2_MASK + 0U, // PseudoVFWMSAC_VF32_M4 + 0U, // PseudoVFWMSAC_VF32_M4_MASK + 0U, // PseudoVFWMSAC_VF32_MF2 + 0U, // PseudoVFWMSAC_VF32_MF2_MASK + 0U, // PseudoVFWMSAC_VF32_MF4 + 0U, // PseudoVFWMSAC_VF32_MF4_MASK + 0U, // PseudoVFWMSAC_VF32_MF8 + 0U, // PseudoVFWMSAC_VF32_MF8_MASK + 0U, // PseudoVFWMSAC_VV_M1 + 0U, // PseudoVFWMSAC_VV_M1_MASK + 0U, // PseudoVFWMSAC_VV_M2 + 0U, // PseudoVFWMSAC_VV_M2_MASK + 0U, // PseudoVFWMSAC_VV_M4 + 0U, // PseudoVFWMSAC_VV_M4_MASK + 0U, // PseudoVFWMSAC_VV_MF2 + 0U, // PseudoVFWMSAC_VV_MF2_MASK + 0U, // PseudoVFWMSAC_VV_MF4 + 0U, // PseudoVFWMSAC_VV_MF4_MASK + 0U, // PseudoVFWMSAC_VV_MF8 + 0U, // PseudoVFWMSAC_VV_MF8_MASK + 0U, // PseudoVFWMUL_VF16_M1 + 0U, // PseudoVFWMUL_VF16_M1_MASK + 0U, // PseudoVFWMUL_VF16_M2 + 0U, // PseudoVFWMUL_VF16_M2_MASK + 0U, // PseudoVFWMUL_VF16_M4 + 0U, // PseudoVFWMUL_VF16_M4_MASK + 0U, // PseudoVFWMUL_VF16_MF2 + 0U, // PseudoVFWMUL_VF16_MF2_MASK + 0U, // PseudoVFWMUL_VF16_MF4 + 0U, // PseudoVFWMUL_VF16_MF4_MASK + 0U, // PseudoVFWMUL_VF16_MF8 + 0U, // PseudoVFWMUL_VF16_MF8_MASK + 0U, // PseudoVFWMUL_VF32_M1 + 0U, // PseudoVFWMUL_VF32_M1_MASK + 0U, // PseudoVFWMUL_VF32_M2 + 0U, // PseudoVFWMUL_VF32_M2_MASK + 0U, // PseudoVFWMUL_VF32_M4 + 0U, // PseudoVFWMUL_VF32_M4_MASK + 0U, // PseudoVFWMUL_VF32_MF2 + 0U, // PseudoVFWMUL_VF32_MF2_MASK + 0U, // PseudoVFWMUL_VF32_MF4 + 0U, // PseudoVFWMUL_VF32_MF4_MASK + 0U, // PseudoVFWMUL_VF32_MF8 + 0U, // PseudoVFWMUL_VF32_MF8_MASK + 0U, // PseudoVFWMUL_VV_M1 + 0U, // PseudoVFWMUL_VV_M1_MASK + 0U, // PseudoVFWMUL_VV_M2 + 0U, // PseudoVFWMUL_VV_M2_MASK + 0U, // PseudoVFWMUL_VV_M4 + 0U, // PseudoVFWMUL_VV_M4_MASK + 0U, // PseudoVFWMUL_VV_MF2 + 0U, // PseudoVFWMUL_VV_MF2_MASK + 0U, // PseudoVFWMUL_VV_MF4 + 0U, // PseudoVFWMUL_VV_MF4_MASK + 0U, // PseudoVFWMUL_VV_MF8 + 0U, // PseudoVFWMUL_VV_MF8_MASK + 0U, // PseudoVFWNMACC_VF16_M1 + 0U, // PseudoVFWNMACC_VF16_M1_MASK + 0U, // PseudoVFWNMACC_VF16_M2 + 0U, // PseudoVFWNMACC_VF16_M2_MASK + 0U, // PseudoVFWNMACC_VF16_M4 + 0U, // PseudoVFWNMACC_VF16_M4_MASK + 0U, // PseudoVFWNMACC_VF16_MF2 + 0U, // PseudoVFWNMACC_VF16_MF2_MASK + 0U, // PseudoVFWNMACC_VF16_MF4 + 0U, // PseudoVFWNMACC_VF16_MF4_MASK + 0U, // PseudoVFWNMACC_VF16_MF8 + 0U, // PseudoVFWNMACC_VF16_MF8_MASK + 0U, // PseudoVFWNMACC_VF32_M1 + 0U, // PseudoVFWNMACC_VF32_M1_MASK + 0U, // PseudoVFWNMACC_VF32_M2 + 0U, // PseudoVFWNMACC_VF32_M2_MASK + 0U, // PseudoVFWNMACC_VF32_M4 + 0U, // PseudoVFWNMACC_VF32_M4_MASK + 0U, // PseudoVFWNMACC_VF32_MF2 + 0U, // PseudoVFWNMACC_VF32_MF2_MASK + 0U, // PseudoVFWNMACC_VF32_MF4 + 0U, // PseudoVFWNMACC_VF32_MF4_MASK + 0U, // PseudoVFWNMACC_VF32_MF8 + 0U, // PseudoVFWNMACC_VF32_MF8_MASK + 0U, // PseudoVFWNMACC_VV_M1 + 0U, // PseudoVFWNMACC_VV_M1_MASK + 0U, // PseudoVFWNMACC_VV_M2 + 0U, // PseudoVFWNMACC_VV_M2_MASK + 0U, // PseudoVFWNMACC_VV_M4 + 0U, // PseudoVFWNMACC_VV_M4_MASK + 0U, // PseudoVFWNMACC_VV_MF2 + 0U, // PseudoVFWNMACC_VV_MF2_MASK + 0U, // PseudoVFWNMACC_VV_MF4 + 0U, // PseudoVFWNMACC_VV_MF4_MASK + 0U, // PseudoVFWNMACC_VV_MF8 + 0U, // PseudoVFWNMACC_VV_MF8_MASK + 0U, // PseudoVFWNMSAC_VF16_M1 + 0U, // PseudoVFWNMSAC_VF16_M1_MASK + 0U, // PseudoVFWNMSAC_VF16_M2 + 0U, // PseudoVFWNMSAC_VF16_M2_MASK + 0U, // PseudoVFWNMSAC_VF16_M4 + 0U, // PseudoVFWNMSAC_VF16_M4_MASK + 0U, // PseudoVFWNMSAC_VF16_MF2 + 0U, // PseudoVFWNMSAC_VF16_MF2_MASK + 0U, // PseudoVFWNMSAC_VF16_MF4 + 0U, // PseudoVFWNMSAC_VF16_MF4_MASK + 0U, // PseudoVFWNMSAC_VF16_MF8 + 0U, // PseudoVFWNMSAC_VF16_MF8_MASK + 0U, // PseudoVFWNMSAC_VF32_M1 + 0U, // PseudoVFWNMSAC_VF32_M1_MASK + 0U, // PseudoVFWNMSAC_VF32_M2 + 0U, // PseudoVFWNMSAC_VF32_M2_MASK + 0U, // PseudoVFWNMSAC_VF32_M4 + 0U, // PseudoVFWNMSAC_VF32_M4_MASK + 0U, // PseudoVFWNMSAC_VF32_MF2 + 0U, // PseudoVFWNMSAC_VF32_MF2_MASK + 0U, // PseudoVFWNMSAC_VF32_MF4 + 0U, // PseudoVFWNMSAC_VF32_MF4_MASK + 0U, // PseudoVFWNMSAC_VF32_MF8 + 0U, // PseudoVFWNMSAC_VF32_MF8_MASK + 0U, // PseudoVFWNMSAC_VV_M1 + 0U, // PseudoVFWNMSAC_VV_M1_MASK + 0U, // PseudoVFWNMSAC_VV_M2 + 0U, // PseudoVFWNMSAC_VV_M2_MASK + 0U, // PseudoVFWNMSAC_VV_M4 + 0U, // PseudoVFWNMSAC_VV_M4_MASK + 0U, // PseudoVFWNMSAC_VV_MF2 + 0U, // PseudoVFWNMSAC_VV_MF2_MASK + 0U, // PseudoVFWNMSAC_VV_MF4 + 0U, // PseudoVFWNMSAC_VV_MF4_MASK + 0U, // PseudoVFWNMSAC_VV_MF8 + 0U, // PseudoVFWNMSAC_VV_MF8_MASK + 0U, // PseudoVFWREDOSUM_VS_M1 + 0U, // PseudoVFWREDOSUM_VS_M1_MASK + 0U, // PseudoVFWREDOSUM_VS_M2 + 0U, // PseudoVFWREDOSUM_VS_M2_MASK + 0U, // PseudoVFWREDOSUM_VS_M4 + 0U, // PseudoVFWREDOSUM_VS_M4_MASK + 0U, // PseudoVFWREDOSUM_VS_M8 + 0U, // PseudoVFWREDOSUM_VS_M8_MASK + 0U, // PseudoVFWREDOSUM_VS_MF2 + 0U, // PseudoVFWREDOSUM_VS_MF2_MASK + 0U, // PseudoVFWREDOSUM_VS_MF4 + 0U, // PseudoVFWREDOSUM_VS_MF4_MASK + 0U, // PseudoVFWREDOSUM_VS_MF8 + 0U, // PseudoVFWREDOSUM_VS_MF8_MASK + 0U, // PseudoVFWREDUSUM_VS_M1 + 0U, // PseudoVFWREDUSUM_VS_M1_MASK + 0U, // PseudoVFWREDUSUM_VS_M2 + 0U, // PseudoVFWREDUSUM_VS_M2_MASK + 0U, // PseudoVFWREDUSUM_VS_M4 + 0U, // PseudoVFWREDUSUM_VS_M4_MASK + 0U, // PseudoVFWREDUSUM_VS_M8 + 0U, // PseudoVFWREDUSUM_VS_M8_MASK + 0U, // PseudoVFWREDUSUM_VS_MF2 + 0U, // PseudoVFWREDUSUM_VS_MF2_MASK + 0U, // PseudoVFWREDUSUM_VS_MF4 + 0U, // PseudoVFWREDUSUM_VS_MF4_MASK + 0U, // PseudoVFWREDUSUM_VS_MF8 + 0U, // PseudoVFWREDUSUM_VS_MF8_MASK + 0U, // PseudoVFWSUB_VF16_M1 + 0U, // PseudoVFWSUB_VF16_M1_MASK + 0U, // PseudoVFWSUB_VF16_M2 + 0U, // PseudoVFWSUB_VF16_M2_MASK + 0U, // PseudoVFWSUB_VF16_M4 + 0U, // PseudoVFWSUB_VF16_M4_MASK + 0U, // PseudoVFWSUB_VF16_MF2 + 0U, // PseudoVFWSUB_VF16_MF2_MASK + 0U, // PseudoVFWSUB_VF16_MF4 + 0U, // PseudoVFWSUB_VF16_MF4_MASK + 0U, // PseudoVFWSUB_VF16_MF8 + 0U, // PseudoVFWSUB_VF16_MF8_MASK + 0U, // PseudoVFWSUB_VF32_M1 + 0U, // PseudoVFWSUB_VF32_M1_MASK + 0U, // PseudoVFWSUB_VF32_M2 + 0U, // PseudoVFWSUB_VF32_M2_MASK + 0U, // PseudoVFWSUB_VF32_M4 + 0U, // PseudoVFWSUB_VF32_M4_MASK + 0U, // PseudoVFWSUB_VF32_MF2 + 0U, // PseudoVFWSUB_VF32_MF2_MASK + 0U, // PseudoVFWSUB_VF32_MF4 + 0U, // PseudoVFWSUB_VF32_MF4_MASK + 0U, // PseudoVFWSUB_VF32_MF8 + 0U, // PseudoVFWSUB_VF32_MF8_MASK + 0U, // PseudoVFWSUB_VV_M1 + 0U, // PseudoVFWSUB_VV_M1_MASK + 0U, // PseudoVFWSUB_VV_M2 + 0U, // PseudoVFWSUB_VV_M2_MASK + 0U, // PseudoVFWSUB_VV_M4 + 0U, // PseudoVFWSUB_VV_M4_MASK + 0U, // PseudoVFWSUB_VV_MF2 + 0U, // PseudoVFWSUB_VV_MF2_MASK + 0U, // PseudoVFWSUB_VV_MF4 + 0U, // PseudoVFWSUB_VV_MF4_MASK + 0U, // PseudoVFWSUB_VV_MF8 + 0U, // PseudoVFWSUB_VV_MF8_MASK + 0U, // PseudoVFWSUB_WF16_M1 + 0U, // PseudoVFWSUB_WF16_M1_MASK + 0U, // PseudoVFWSUB_WF16_M2 + 0U, // PseudoVFWSUB_WF16_M2_MASK + 0U, // PseudoVFWSUB_WF16_M4 + 0U, // PseudoVFWSUB_WF16_M4_MASK + 0U, // PseudoVFWSUB_WF16_MF2 + 0U, // PseudoVFWSUB_WF16_MF2_MASK + 0U, // PseudoVFWSUB_WF16_MF4 + 0U, // PseudoVFWSUB_WF16_MF4_MASK + 0U, // PseudoVFWSUB_WF16_MF8 + 0U, // PseudoVFWSUB_WF16_MF8_MASK + 0U, // PseudoVFWSUB_WF32_M1 + 0U, // PseudoVFWSUB_WF32_M1_MASK + 0U, // PseudoVFWSUB_WF32_M2 + 0U, // PseudoVFWSUB_WF32_M2_MASK + 0U, // PseudoVFWSUB_WF32_M4 + 0U, // PseudoVFWSUB_WF32_M4_MASK + 0U, // PseudoVFWSUB_WF32_MF2 + 0U, // PseudoVFWSUB_WF32_MF2_MASK + 0U, // PseudoVFWSUB_WF32_MF4 + 0U, // PseudoVFWSUB_WF32_MF4_MASK + 0U, // PseudoVFWSUB_WF32_MF8 + 0U, // PseudoVFWSUB_WF32_MF8_MASK + 0U, // PseudoVFWSUB_WV_M1 + 0U, // PseudoVFWSUB_WV_M1_MASK + 0U, // PseudoVFWSUB_WV_M1_MASK_TIED + 0U, // PseudoVFWSUB_WV_M1_TIED + 0U, // PseudoVFWSUB_WV_M2 + 0U, // PseudoVFWSUB_WV_M2_MASK + 0U, // PseudoVFWSUB_WV_M2_MASK_TIED + 0U, // PseudoVFWSUB_WV_M2_TIED + 0U, // PseudoVFWSUB_WV_M4 + 0U, // PseudoVFWSUB_WV_M4_MASK + 0U, // PseudoVFWSUB_WV_M4_MASK_TIED + 0U, // PseudoVFWSUB_WV_M4_TIED + 0U, // PseudoVFWSUB_WV_MF2 + 0U, // PseudoVFWSUB_WV_MF2_MASK + 0U, // PseudoVFWSUB_WV_MF2_MASK_TIED + 0U, // PseudoVFWSUB_WV_MF2_TIED + 0U, // PseudoVFWSUB_WV_MF4 + 0U, // PseudoVFWSUB_WV_MF4_MASK + 0U, // PseudoVFWSUB_WV_MF4_MASK_TIED + 0U, // PseudoVFWSUB_WV_MF4_TIED + 0U, // PseudoVFWSUB_WV_MF8 + 0U, // PseudoVFWSUB_WV_MF8_MASK + 0U, // PseudoVFWSUB_WV_MF8_MASK_TIED + 0U, // PseudoVFWSUB_WV_MF8_TIED + 0U, // PseudoVID_V_M1 + 0U, // PseudoVID_V_M1_MASK + 0U, // PseudoVID_V_M2 + 0U, // PseudoVID_V_M2_MASK + 0U, // PseudoVID_V_M4 + 0U, // PseudoVID_V_M4_MASK + 0U, // PseudoVID_V_M8 + 0U, // PseudoVID_V_M8_MASK + 0U, // PseudoVID_V_MF2 + 0U, // PseudoVID_V_MF2_MASK + 0U, // PseudoVID_V_MF4 + 0U, // PseudoVID_V_MF4_MASK + 0U, // PseudoVID_V_MF8 + 0U, // PseudoVID_V_MF8_MASK + 0U, // PseudoVIOTA_M_M1 + 0U, // PseudoVIOTA_M_M1_MASK + 0U, // PseudoVIOTA_M_M2 + 0U, // PseudoVIOTA_M_M2_MASK + 0U, // PseudoVIOTA_M_M4 + 0U, // PseudoVIOTA_M_M4_MASK + 0U, // PseudoVIOTA_M_M8 + 0U, // PseudoVIOTA_M_M8_MASK + 0U, // PseudoVIOTA_M_MF2 + 0U, // PseudoVIOTA_M_MF2_MASK + 0U, // PseudoVIOTA_M_MF4 + 0U, // PseudoVIOTA_M_MF4_MASK + 0U, // PseudoVIOTA_M_MF8 + 0U, // PseudoVIOTA_M_MF8_MASK + 0U, // PseudoVLE16FF_V_M1 + 0U, // PseudoVLE16FF_V_M1_MASK + 0U, // PseudoVLE16FF_V_M2 + 0U, // PseudoVLE16FF_V_M2_MASK + 0U, // PseudoVLE16FF_V_M4 + 0U, // PseudoVLE16FF_V_M4_MASK + 0U, // PseudoVLE16FF_V_M8 + 0U, // PseudoVLE16FF_V_M8_MASK + 0U, // PseudoVLE16FF_V_MF2 + 0U, // PseudoVLE16FF_V_MF2_MASK + 0U, // PseudoVLE16FF_V_MF4 + 0U, // PseudoVLE16FF_V_MF4_MASK + 0U, // PseudoVLE16_V_M1 + 0U, // PseudoVLE16_V_M1_MASK + 0U, // PseudoVLE16_V_M2 + 0U, // PseudoVLE16_V_M2_MASK + 0U, // PseudoVLE16_V_M4 + 0U, // PseudoVLE16_V_M4_MASK + 0U, // PseudoVLE16_V_M8 + 0U, // PseudoVLE16_V_M8_MASK + 0U, // PseudoVLE16_V_MF2 + 0U, // PseudoVLE16_V_MF2_MASK + 0U, // PseudoVLE16_V_MF4 + 0U, // PseudoVLE16_V_MF4_MASK + 0U, // PseudoVLE32FF_V_M1 + 0U, // PseudoVLE32FF_V_M1_MASK + 0U, // PseudoVLE32FF_V_M2 + 0U, // PseudoVLE32FF_V_M2_MASK + 0U, // PseudoVLE32FF_V_M4 + 0U, // PseudoVLE32FF_V_M4_MASK + 0U, // PseudoVLE32FF_V_M8 + 0U, // PseudoVLE32FF_V_M8_MASK + 0U, // PseudoVLE32FF_V_MF2 + 0U, // PseudoVLE32FF_V_MF2_MASK + 0U, // PseudoVLE32_V_M1 + 0U, // PseudoVLE32_V_M1_MASK + 0U, // PseudoVLE32_V_M2 + 0U, // PseudoVLE32_V_M2_MASK + 0U, // PseudoVLE32_V_M4 + 0U, // PseudoVLE32_V_M4_MASK + 0U, // PseudoVLE32_V_M8 + 0U, // PseudoVLE32_V_M8_MASK + 0U, // PseudoVLE32_V_MF2 + 0U, // PseudoVLE32_V_MF2_MASK + 0U, // PseudoVLE64FF_V_M1 + 0U, // PseudoVLE64FF_V_M1_MASK + 0U, // PseudoVLE64FF_V_M2 + 0U, // PseudoVLE64FF_V_M2_MASK + 0U, // PseudoVLE64FF_V_M4 + 0U, // PseudoVLE64FF_V_M4_MASK + 0U, // PseudoVLE64FF_V_M8 + 0U, // PseudoVLE64FF_V_M8_MASK + 0U, // PseudoVLE64_V_M1 + 0U, // PseudoVLE64_V_M1_MASK + 0U, // PseudoVLE64_V_M2 + 0U, // PseudoVLE64_V_M2_MASK + 0U, // PseudoVLE64_V_M4 + 0U, // PseudoVLE64_V_M4_MASK + 0U, // PseudoVLE64_V_M8 + 0U, // PseudoVLE64_V_M8_MASK + 0U, // PseudoVLE8FF_V_M1 + 0U, // PseudoVLE8FF_V_M1_MASK + 0U, // PseudoVLE8FF_V_M2 + 0U, // PseudoVLE8FF_V_M2_MASK + 0U, // PseudoVLE8FF_V_M4 + 0U, // PseudoVLE8FF_V_M4_MASK + 0U, // PseudoVLE8FF_V_M8 + 0U, // PseudoVLE8FF_V_M8_MASK + 0U, // PseudoVLE8FF_V_MF2 + 0U, // PseudoVLE8FF_V_MF2_MASK + 0U, // PseudoVLE8FF_V_MF4 + 0U, // PseudoVLE8FF_V_MF4_MASK + 0U, // PseudoVLE8FF_V_MF8 + 0U, // PseudoVLE8FF_V_MF8_MASK + 0U, // PseudoVLE8_V_M1 + 0U, // PseudoVLE8_V_M1_MASK + 0U, // PseudoVLE8_V_M2 + 0U, // PseudoVLE8_V_M2_MASK + 0U, // PseudoVLE8_V_M4 + 0U, // PseudoVLE8_V_M4_MASK + 0U, // PseudoVLE8_V_M8 + 0U, // PseudoVLE8_V_M8_MASK + 0U, // PseudoVLE8_V_MF2 + 0U, // PseudoVLE8_V_MF2_MASK + 0U, // PseudoVLE8_V_MF4 + 0U, // PseudoVLE8_V_MF4_MASK + 0U, // PseudoVLE8_V_MF8 + 0U, // PseudoVLE8_V_MF8_MASK + 0U, // PseudoVLM_V_B1 + 0U, // PseudoVLM_V_B16 + 0U, // PseudoVLM_V_B2 + 0U, // PseudoVLM_V_B32 + 0U, // PseudoVLM_V_B4 + 0U, // PseudoVLM_V_B64 + 0U, // PseudoVLM_V_B8 + 0U, // PseudoVLOXEI16_V_M1_M1 + 0U, // PseudoVLOXEI16_V_M1_M1_MASK + 0U, // PseudoVLOXEI16_V_M1_M2 + 0U, // PseudoVLOXEI16_V_M1_M2_MASK + 0U, // PseudoVLOXEI16_V_M1_M4 + 0U, // PseudoVLOXEI16_V_M1_M4_MASK + 0U, // PseudoVLOXEI16_V_M1_MF2 + 0U, // PseudoVLOXEI16_V_M1_MF2_MASK + 0U, // PseudoVLOXEI16_V_M2_M1 + 0U, // PseudoVLOXEI16_V_M2_M1_MASK + 0U, // PseudoVLOXEI16_V_M2_M2 + 0U, // PseudoVLOXEI16_V_M2_M2_MASK + 0U, // PseudoVLOXEI16_V_M2_M4 + 0U, // PseudoVLOXEI16_V_M2_M4_MASK + 0U, // PseudoVLOXEI16_V_M2_M8 + 0U, // PseudoVLOXEI16_V_M2_M8_MASK + 0U, // PseudoVLOXEI16_V_M4_M2 + 0U, // PseudoVLOXEI16_V_M4_M2_MASK + 0U, // PseudoVLOXEI16_V_M4_M4 + 0U, // PseudoVLOXEI16_V_M4_M4_MASK + 0U, // PseudoVLOXEI16_V_M4_M8 + 0U, // PseudoVLOXEI16_V_M4_M8_MASK + 0U, // PseudoVLOXEI16_V_M8_M4 + 0U, // PseudoVLOXEI16_V_M8_M4_MASK + 0U, // PseudoVLOXEI16_V_M8_M8 + 0U, // PseudoVLOXEI16_V_M8_M8_MASK + 0U, // PseudoVLOXEI16_V_MF2_M1 + 0U, // PseudoVLOXEI16_V_MF2_M1_MASK + 0U, // PseudoVLOXEI16_V_MF2_M2 + 0U, // PseudoVLOXEI16_V_MF2_M2_MASK + 0U, // PseudoVLOXEI16_V_MF2_MF2 + 0U, // PseudoVLOXEI16_V_MF2_MF2_MASK + 0U, // PseudoVLOXEI16_V_MF2_MF4 + 0U, // PseudoVLOXEI16_V_MF2_MF4_MASK + 0U, // PseudoVLOXEI16_V_MF4_M1 + 0U, // PseudoVLOXEI16_V_MF4_M1_MASK + 0U, // PseudoVLOXEI16_V_MF4_MF2 + 0U, // PseudoVLOXEI16_V_MF4_MF2_MASK + 0U, // PseudoVLOXEI16_V_MF4_MF4 + 0U, // PseudoVLOXEI16_V_MF4_MF4_MASK + 0U, // PseudoVLOXEI16_V_MF4_MF8 + 0U, // PseudoVLOXEI16_V_MF4_MF8_MASK + 0U, // PseudoVLOXEI32_V_M1_M1 + 0U, // PseudoVLOXEI32_V_M1_M1_MASK + 0U, // PseudoVLOXEI32_V_M1_M2 + 0U, // PseudoVLOXEI32_V_M1_M2_MASK + 0U, // PseudoVLOXEI32_V_M1_MF2 + 0U, // PseudoVLOXEI32_V_M1_MF2_MASK + 0U, // PseudoVLOXEI32_V_M1_MF4 + 0U, // PseudoVLOXEI32_V_M1_MF4_MASK + 0U, // PseudoVLOXEI32_V_M2_M1 + 0U, // PseudoVLOXEI32_V_M2_M1_MASK + 0U, // PseudoVLOXEI32_V_M2_M2 + 0U, // PseudoVLOXEI32_V_M2_M2_MASK + 0U, // PseudoVLOXEI32_V_M2_M4 + 0U, // PseudoVLOXEI32_V_M2_M4_MASK + 0U, // PseudoVLOXEI32_V_M2_MF2 + 0U, // PseudoVLOXEI32_V_M2_MF2_MASK + 0U, // PseudoVLOXEI32_V_M4_M1 + 0U, // PseudoVLOXEI32_V_M4_M1_MASK + 0U, // PseudoVLOXEI32_V_M4_M2 + 0U, // PseudoVLOXEI32_V_M4_M2_MASK + 0U, // PseudoVLOXEI32_V_M4_M4 + 0U, // PseudoVLOXEI32_V_M4_M4_MASK + 0U, // PseudoVLOXEI32_V_M4_M8 + 0U, // PseudoVLOXEI32_V_M4_M8_MASK + 0U, // PseudoVLOXEI32_V_M8_M2 + 0U, // PseudoVLOXEI32_V_M8_M2_MASK + 0U, // PseudoVLOXEI32_V_M8_M4 + 0U, // PseudoVLOXEI32_V_M8_M4_MASK + 0U, // PseudoVLOXEI32_V_M8_M8 + 0U, // PseudoVLOXEI32_V_M8_M8_MASK + 0U, // PseudoVLOXEI32_V_MF2_M1 + 0U, // PseudoVLOXEI32_V_MF2_M1_MASK + 0U, // PseudoVLOXEI32_V_MF2_MF2 + 0U, // PseudoVLOXEI32_V_MF2_MF2_MASK + 0U, // PseudoVLOXEI32_V_MF2_MF4 + 0U, // PseudoVLOXEI32_V_MF2_MF4_MASK + 0U, // PseudoVLOXEI32_V_MF2_MF8 + 0U, // PseudoVLOXEI32_V_MF2_MF8_MASK + 0U, // PseudoVLOXEI64_V_M1_M1 + 0U, // PseudoVLOXEI64_V_M1_M1_MASK + 0U, // PseudoVLOXEI64_V_M1_MF2 + 0U, // PseudoVLOXEI64_V_M1_MF2_MASK + 0U, // PseudoVLOXEI64_V_M1_MF4 + 0U, // PseudoVLOXEI64_V_M1_MF4_MASK + 0U, // PseudoVLOXEI64_V_M1_MF8 + 0U, // PseudoVLOXEI64_V_M1_MF8_MASK + 0U, // PseudoVLOXEI64_V_M2_M1 + 0U, // PseudoVLOXEI64_V_M2_M1_MASK + 0U, // PseudoVLOXEI64_V_M2_M2 + 0U, // PseudoVLOXEI64_V_M2_M2_MASK + 0U, // PseudoVLOXEI64_V_M2_MF2 + 0U, // PseudoVLOXEI64_V_M2_MF2_MASK + 0U, // PseudoVLOXEI64_V_M2_MF4 + 0U, // PseudoVLOXEI64_V_M2_MF4_MASK + 0U, // PseudoVLOXEI64_V_M4_M1 + 0U, // PseudoVLOXEI64_V_M4_M1_MASK + 0U, // PseudoVLOXEI64_V_M4_M2 + 0U, // PseudoVLOXEI64_V_M4_M2_MASK + 0U, // PseudoVLOXEI64_V_M4_M4 + 0U, // PseudoVLOXEI64_V_M4_M4_MASK + 0U, // PseudoVLOXEI64_V_M4_MF2 + 0U, // PseudoVLOXEI64_V_M4_MF2_MASK + 0U, // PseudoVLOXEI64_V_M8_M1 + 0U, // PseudoVLOXEI64_V_M8_M1_MASK + 0U, // PseudoVLOXEI64_V_M8_M2 + 0U, // PseudoVLOXEI64_V_M8_M2_MASK + 0U, // PseudoVLOXEI64_V_M8_M4 + 0U, // PseudoVLOXEI64_V_M8_M4_MASK + 0U, // PseudoVLOXEI64_V_M8_M8 + 0U, // PseudoVLOXEI64_V_M8_M8_MASK + 0U, // PseudoVLOXEI8_V_M1_M1 + 0U, // PseudoVLOXEI8_V_M1_M1_MASK + 0U, // PseudoVLOXEI8_V_M1_M2 + 0U, // PseudoVLOXEI8_V_M1_M2_MASK + 0U, // PseudoVLOXEI8_V_M1_M4 + 0U, // PseudoVLOXEI8_V_M1_M4_MASK + 0U, // PseudoVLOXEI8_V_M1_M8 + 0U, // PseudoVLOXEI8_V_M1_M8_MASK + 0U, // PseudoVLOXEI8_V_M2_M2 + 0U, // PseudoVLOXEI8_V_M2_M2_MASK + 0U, // PseudoVLOXEI8_V_M2_M4 + 0U, // PseudoVLOXEI8_V_M2_M4_MASK + 0U, // PseudoVLOXEI8_V_M2_M8 + 0U, // PseudoVLOXEI8_V_M2_M8_MASK + 0U, // PseudoVLOXEI8_V_M4_M4 + 0U, // PseudoVLOXEI8_V_M4_M4_MASK + 0U, // PseudoVLOXEI8_V_M4_M8 + 0U, // PseudoVLOXEI8_V_M4_M8_MASK + 0U, // PseudoVLOXEI8_V_M8_M8 + 0U, // PseudoVLOXEI8_V_M8_M8_MASK + 0U, // PseudoVLOXEI8_V_MF2_M1 + 0U, // PseudoVLOXEI8_V_MF2_M1_MASK + 0U, // PseudoVLOXEI8_V_MF2_M2 + 0U, // PseudoVLOXEI8_V_MF2_M2_MASK + 0U, // PseudoVLOXEI8_V_MF2_M4 + 0U, // PseudoVLOXEI8_V_MF2_M4_MASK + 0U, // PseudoVLOXEI8_V_MF2_MF2 + 0U, // PseudoVLOXEI8_V_MF2_MF2_MASK + 0U, // PseudoVLOXEI8_V_MF4_M1 + 0U, // PseudoVLOXEI8_V_MF4_M1_MASK + 0U, // PseudoVLOXEI8_V_MF4_M2 + 0U, // PseudoVLOXEI8_V_MF4_M2_MASK + 0U, // PseudoVLOXEI8_V_MF4_MF2 + 0U, // PseudoVLOXEI8_V_MF4_MF2_MASK + 0U, // PseudoVLOXEI8_V_MF4_MF4 + 0U, // PseudoVLOXEI8_V_MF4_MF4_MASK + 0U, // PseudoVLOXEI8_V_MF8_M1 + 0U, // PseudoVLOXEI8_V_MF8_M1_MASK + 0U, // PseudoVLOXEI8_V_MF8_MF2 + 0U, // PseudoVLOXEI8_V_MF8_MF2_MASK + 0U, // PseudoVLOXEI8_V_MF8_MF4 + 0U, // PseudoVLOXEI8_V_MF8_MF4_MASK + 0U, // PseudoVLOXEI8_V_MF8_MF8 + 0U, // PseudoVLOXEI8_V_MF8_MF8_MASK + 0U, // PseudoVLOXSEG2EI16_V_M1_M1 + 0U, // PseudoVLOXSEG2EI16_V_M1_M1_MASK + 0U, // PseudoVLOXSEG2EI16_V_M1_M2 + 0U, // PseudoVLOXSEG2EI16_V_M1_M2_MASK + 0U, // PseudoVLOXSEG2EI16_V_M1_M4 + 0U, // PseudoVLOXSEG2EI16_V_M1_M4_MASK + 0U, // PseudoVLOXSEG2EI16_V_M1_MF2 + 0U, // PseudoVLOXSEG2EI16_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG2EI16_V_M2_M1 + 0U, // PseudoVLOXSEG2EI16_V_M2_M1_MASK + 0U, // PseudoVLOXSEG2EI16_V_M2_M2 + 0U, // PseudoVLOXSEG2EI16_V_M2_M2_MASK + 0U, // PseudoVLOXSEG2EI16_V_M2_M4 + 0U, // PseudoVLOXSEG2EI16_V_M2_M4_MASK + 0U, // PseudoVLOXSEG2EI16_V_M4_M2 + 0U, // PseudoVLOXSEG2EI16_V_M4_M2_MASK + 0U, // PseudoVLOXSEG2EI16_V_M4_M4 + 0U, // PseudoVLOXSEG2EI16_V_M4_M4_MASK + 0U, // PseudoVLOXSEG2EI16_V_M8_M4 + 0U, // PseudoVLOXSEG2EI16_V_M8_M4_MASK + 0U, // PseudoVLOXSEG2EI16_V_MF2_M1 + 0U, // PseudoVLOXSEG2EI16_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG2EI16_V_MF2_M2 + 0U, // PseudoVLOXSEG2EI16_V_MF2_M2_MASK + 0U, // PseudoVLOXSEG2EI16_V_MF2_MF2 + 0U, // PseudoVLOXSEG2EI16_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG2EI16_V_MF2_MF4 + 0U, // PseudoVLOXSEG2EI16_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG2EI16_V_MF4_M1 + 0U, // PseudoVLOXSEG2EI16_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG2EI16_V_MF4_MF2 + 0U, // PseudoVLOXSEG2EI16_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG2EI16_V_MF4_MF4 + 0U, // PseudoVLOXSEG2EI16_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG2EI16_V_MF4_MF8 + 0U, // PseudoVLOXSEG2EI16_V_MF4_MF8_MASK + 0U, // PseudoVLOXSEG2EI32_V_M1_M1 + 0U, // PseudoVLOXSEG2EI32_V_M1_M1_MASK + 0U, // PseudoVLOXSEG2EI32_V_M1_M2 + 0U, // PseudoVLOXSEG2EI32_V_M1_M2_MASK + 0U, // PseudoVLOXSEG2EI32_V_M1_MF2 + 0U, // PseudoVLOXSEG2EI32_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG2EI32_V_M1_MF4 + 0U, // PseudoVLOXSEG2EI32_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG2EI32_V_M2_M1 + 0U, // PseudoVLOXSEG2EI32_V_M2_M1_MASK + 0U, // PseudoVLOXSEG2EI32_V_M2_M2 + 0U, // PseudoVLOXSEG2EI32_V_M2_M2_MASK + 0U, // PseudoVLOXSEG2EI32_V_M2_M4 + 0U, // PseudoVLOXSEG2EI32_V_M2_M4_MASK + 0U, // PseudoVLOXSEG2EI32_V_M2_MF2 + 0U, // PseudoVLOXSEG2EI32_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG2EI32_V_M4_M1 + 0U, // PseudoVLOXSEG2EI32_V_M4_M1_MASK + 0U, // PseudoVLOXSEG2EI32_V_M4_M2 + 0U, // PseudoVLOXSEG2EI32_V_M4_M2_MASK + 0U, // PseudoVLOXSEG2EI32_V_M4_M4 + 0U, // PseudoVLOXSEG2EI32_V_M4_M4_MASK + 0U, // PseudoVLOXSEG2EI32_V_M8_M2 + 0U, // PseudoVLOXSEG2EI32_V_M8_M2_MASK + 0U, // PseudoVLOXSEG2EI32_V_M8_M4 + 0U, // PseudoVLOXSEG2EI32_V_M8_M4_MASK + 0U, // PseudoVLOXSEG2EI32_V_MF2_M1 + 0U, // PseudoVLOXSEG2EI32_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG2EI32_V_MF2_MF2 + 0U, // PseudoVLOXSEG2EI32_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG2EI32_V_MF2_MF4 + 0U, // PseudoVLOXSEG2EI32_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG2EI32_V_MF2_MF8 + 0U, // PseudoVLOXSEG2EI32_V_MF2_MF8_MASK + 0U, // PseudoVLOXSEG2EI64_V_M1_M1 + 0U, // PseudoVLOXSEG2EI64_V_M1_M1_MASK + 0U, // PseudoVLOXSEG2EI64_V_M1_MF2 + 0U, // PseudoVLOXSEG2EI64_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG2EI64_V_M1_MF4 + 0U, // PseudoVLOXSEG2EI64_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG2EI64_V_M1_MF8 + 0U, // PseudoVLOXSEG2EI64_V_M1_MF8_MASK + 0U, // PseudoVLOXSEG2EI64_V_M2_M1 + 0U, // PseudoVLOXSEG2EI64_V_M2_M1_MASK + 0U, // PseudoVLOXSEG2EI64_V_M2_M2 + 0U, // PseudoVLOXSEG2EI64_V_M2_M2_MASK + 0U, // PseudoVLOXSEG2EI64_V_M2_MF2 + 0U, // PseudoVLOXSEG2EI64_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG2EI64_V_M2_MF4 + 0U, // PseudoVLOXSEG2EI64_V_M2_MF4_MASK + 0U, // PseudoVLOXSEG2EI64_V_M4_M1 + 0U, // PseudoVLOXSEG2EI64_V_M4_M1_MASK + 0U, // PseudoVLOXSEG2EI64_V_M4_M2 + 0U, // PseudoVLOXSEG2EI64_V_M4_M2_MASK + 0U, // PseudoVLOXSEG2EI64_V_M4_M4 + 0U, // PseudoVLOXSEG2EI64_V_M4_M4_MASK + 0U, // PseudoVLOXSEG2EI64_V_M4_MF2 + 0U, // PseudoVLOXSEG2EI64_V_M4_MF2_MASK + 0U, // PseudoVLOXSEG2EI64_V_M8_M1 + 0U, // PseudoVLOXSEG2EI64_V_M8_M1_MASK + 0U, // PseudoVLOXSEG2EI64_V_M8_M2 + 0U, // PseudoVLOXSEG2EI64_V_M8_M2_MASK + 0U, // PseudoVLOXSEG2EI64_V_M8_M4 + 0U, // PseudoVLOXSEG2EI64_V_M8_M4_MASK + 0U, // PseudoVLOXSEG2EI8_V_M1_M1 + 0U, // PseudoVLOXSEG2EI8_V_M1_M1_MASK + 0U, // PseudoVLOXSEG2EI8_V_M1_M2 + 0U, // PseudoVLOXSEG2EI8_V_M1_M2_MASK + 0U, // PseudoVLOXSEG2EI8_V_M1_M4 + 0U, // PseudoVLOXSEG2EI8_V_M1_M4_MASK + 0U, // PseudoVLOXSEG2EI8_V_M2_M2 + 0U, // PseudoVLOXSEG2EI8_V_M2_M2_MASK + 0U, // PseudoVLOXSEG2EI8_V_M2_M4 + 0U, // PseudoVLOXSEG2EI8_V_M2_M4_MASK + 0U, // PseudoVLOXSEG2EI8_V_M4_M4 + 0U, // PseudoVLOXSEG2EI8_V_M4_M4_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF2_M1 + 0U, // PseudoVLOXSEG2EI8_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF2_M2 + 0U, // PseudoVLOXSEG2EI8_V_MF2_M2_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF2_M4 + 0U, // PseudoVLOXSEG2EI8_V_MF2_M4_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF2_MF2 + 0U, // PseudoVLOXSEG2EI8_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF4_M1 + 0U, // PseudoVLOXSEG2EI8_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF4_M2 + 0U, // PseudoVLOXSEG2EI8_V_MF4_M2_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF4_MF2 + 0U, // PseudoVLOXSEG2EI8_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF4_MF4 + 0U, // PseudoVLOXSEG2EI8_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF8_M1 + 0U, // PseudoVLOXSEG2EI8_V_MF8_M1_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF8_MF2 + 0U, // PseudoVLOXSEG2EI8_V_MF8_MF2_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF8_MF4 + 0U, // PseudoVLOXSEG2EI8_V_MF8_MF4_MASK + 0U, // PseudoVLOXSEG2EI8_V_MF8_MF8 + 0U, // PseudoVLOXSEG2EI8_V_MF8_MF8_MASK + 0U, // PseudoVLOXSEG3EI16_V_M1_M1 + 0U, // PseudoVLOXSEG3EI16_V_M1_M1_MASK + 0U, // PseudoVLOXSEG3EI16_V_M1_M2 + 0U, // PseudoVLOXSEG3EI16_V_M1_M2_MASK + 0U, // PseudoVLOXSEG3EI16_V_M1_MF2 + 0U, // PseudoVLOXSEG3EI16_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG3EI16_V_M2_M1 + 0U, // PseudoVLOXSEG3EI16_V_M2_M1_MASK + 0U, // PseudoVLOXSEG3EI16_V_M2_M2 + 0U, // PseudoVLOXSEG3EI16_V_M2_M2_MASK + 0U, // PseudoVLOXSEG3EI16_V_M4_M2 + 0U, // PseudoVLOXSEG3EI16_V_M4_M2_MASK + 0U, // PseudoVLOXSEG3EI16_V_MF2_M1 + 0U, // PseudoVLOXSEG3EI16_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG3EI16_V_MF2_M2 + 0U, // PseudoVLOXSEG3EI16_V_MF2_M2_MASK + 0U, // PseudoVLOXSEG3EI16_V_MF2_MF2 + 0U, // PseudoVLOXSEG3EI16_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG3EI16_V_MF2_MF4 + 0U, // PseudoVLOXSEG3EI16_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG3EI16_V_MF4_M1 + 0U, // PseudoVLOXSEG3EI16_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG3EI16_V_MF4_MF2 + 0U, // PseudoVLOXSEG3EI16_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG3EI16_V_MF4_MF4 + 0U, // PseudoVLOXSEG3EI16_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG3EI16_V_MF4_MF8 + 0U, // PseudoVLOXSEG3EI16_V_MF4_MF8_MASK + 0U, // PseudoVLOXSEG3EI32_V_M1_M1 + 0U, // PseudoVLOXSEG3EI32_V_M1_M1_MASK + 0U, // PseudoVLOXSEG3EI32_V_M1_M2 + 0U, // PseudoVLOXSEG3EI32_V_M1_M2_MASK + 0U, // PseudoVLOXSEG3EI32_V_M1_MF2 + 0U, // PseudoVLOXSEG3EI32_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG3EI32_V_M1_MF4 + 0U, // PseudoVLOXSEG3EI32_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG3EI32_V_M2_M1 + 0U, // PseudoVLOXSEG3EI32_V_M2_M1_MASK + 0U, // PseudoVLOXSEG3EI32_V_M2_M2 + 0U, // PseudoVLOXSEG3EI32_V_M2_M2_MASK + 0U, // PseudoVLOXSEG3EI32_V_M2_MF2 + 0U, // PseudoVLOXSEG3EI32_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG3EI32_V_M4_M1 + 0U, // PseudoVLOXSEG3EI32_V_M4_M1_MASK + 0U, // PseudoVLOXSEG3EI32_V_M4_M2 + 0U, // PseudoVLOXSEG3EI32_V_M4_M2_MASK + 0U, // PseudoVLOXSEG3EI32_V_M8_M2 + 0U, // PseudoVLOXSEG3EI32_V_M8_M2_MASK + 0U, // PseudoVLOXSEG3EI32_V_MF2_M1 + 0U, // PseudoVLOXSEG3EI32_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG3EI32_V_MF2_MF2 + 0U, // PseudoVLOXSEG3EI32_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG3EI32_V_MF2_MF4 + 0U, // PseudoVLOXSEG3EI32_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG3EI32_V_MF2_MF8 + 0U, // PseudoVLOXSEG3EI32_V_MF2_MF8_MASK + 0U, // PseudoVLOXSEG3EI64_V_M1_M1 + 0U, // PseudoVLOXSEG3EI64_V_M1_M1_MASK + 0U, // PseudoVLOXSEG3EI64_V_M1_MF2 + 0U, // PseudoVLOXSEG3EI64_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG3EI64_V_M1_MF4 + 0U, // PseudoVLOXSEG3EI64_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG3EI64_V_M1_MF8 + 0U, // PseudoVLOXSEG3EI64_V_M1_MF8_MASK + 0U, // PseudoVLOXSEG3EI64_V_M2_M1 + 0U, // PseudoVLOXSEG3EI64_V_M2_M1_MASK + 0U, // PseudoVLOXSEG3EI64_V_M2_M2 + 0U, // PseudoVLOXSEG3EI64_V_M2_M2_MASK + 0U, // PseudoVLOXSEG3EI64_V_M2_MF2 + 0U, // PseudoVLOXSEG3EI64_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG3EI64_V_M2_MF4 + 0U, // PseudoVLOXSEG3EI64_V_M2_MF4_MASK + 0U, // PseudoVLOXSEG3EI64_V_M4_M1 + 0U, // PseudoVLOXSEG3EI64_V_M4_M1_MASK + 0U, // PseudoVLOXSEG3EI64_V_M4_M2 + 0U, // PseudoVLOXSEG3EI64_V_M4_M2_MASK + 0U, // PseudoVLOXSEG3EI64_V_M4_MF2 + 0U, // PseudoVLOXSEG3EI64_V_M4_MF2_MASK + 0U, // PseudoVLOXSEG3EI64_V_M8_M1 + 0U, // PseudoVLOXSEG3EI64_V_M8_M1_MASK + 0U, // PseudoVLOXSEG3EI64_V_M8_M2 + 0U, // PseudoVLOXSEG3EI64_V_M8_M2_MASK + 0U, // PseudoVLOXSEG3EI8_V_M1_M1 + 0U, // PseudoVLOXSEG3EI8_V_M1_M1_MASK + 0U, // PseudoVLOXSEG3EI8_V_M1_M2 + 0U, // PseudoVLOXSEG3EI8_V_M1_M2_MASK + 0U, // PseudoVLOXSEG3EI8_V_M2_M2 + 0U, // PseudoVLOXSEG3EI8_V_M2_M2_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF2_M1 + 0U, // PseudoVLOXSEG3EI8_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF2_M2 + 0U, // PseudoVLOXSEG3EI8_V_MF2_M2_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF2_MF2 + 0U, // PseudoVLOXSEG3EI8_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF4_M1 + 0U, // PseudoVLOXSEG3EI8_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF4_M2 + 0U, // PseudoVLOXSEG3EI8_V_MF4_M2_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF4_MF2 + 0U, // PseudoVLOXSEG3EI8_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF4_MF4 + 0U, // PseudoVLOXSEG3EI8_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF8_M1 + 0U, // PseudoVLOXSEG3EI8_V_MF8_M1_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF8_MF2 + 0U, // PseudoVLOXSEG3EI8_V_MF8_MF2_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF8_MF4 + 0U, // PseudoVLOXSEG3EI8_V_MF8_MF4_MASK + 0U, // PseudoVLOXSEG3EI8_V_MF8_MF8 + 0U, // PseudoVLOXSEG3EI8_V_MF8_MF8_MASK + 0U, // PseudoVLOXSEG4EI16_V_M1_M1 + 0U, // PseudoVLOXSEG4EI16_V_M1_M1_MASK + 0U, // PseudoVLOXSEG4EI16_V_M1_M2 + 0U, // PseudoVLOXSEG4EI16_V_M1_M2_MASK + 0U, // PseudoVLOXSEG4EI16_V_M1_MF2 + 0U, // PseudoVLOXSEG4EI16_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG4EI16_V_M2_M1 + 0U, // PseudoVLOXSEG4EI16_V_M2_M1_MASK + 0U, // PseudoVLOXSEG4EI16_V_M2_M2 + 0U, // PseudoVLOXSEG4EI16_V_M2_M2_MASK + 0U, // PseudoVLOXSEG4EI16_V_M4_M2 + 0U, // PseudoVLOXSEG4EI16_V_M4_M2_MASK + 0U, // PseudoVLOXSEG4EI16_V_MF2_M1 + 0U, // PseudoVLOXSEG4EI16_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG4EI16_V_MF2_M2 + 0U, // PseudoVLOXSEG4EI16_V_MF2_M2_MASK + 0U, // PseudoVLOXSEG4EI16_V_MF2_MF2 + 0U, // PseudoVLOXSEG4EI16_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG4EI16_V_MF2_MF4 + 0U, // PseudoVLOXSEG4EI16_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG4EI16_V_MF4_M1 + 0U, // PseudoVLOXSEG4EI16_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG4EI16_V_MF4_MF2 + 0U, // PseudoVLOXSEG4EI16_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG4EI16_V_MF4_MF4 + 0U, // PseudoVLOXSEG4EI16_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG4EI16_V_MF4_MF8 + 0U, // PseudoVLOXSEG4EI16_V_MF4_MF8_MASK + 0U, // PseudoVLOXSEG4EI32_V_M1_M1 + 0U, // PseudoVLOXSEG4EI32_V_M1_M1_MASK + 0U, // PseudoVLOXSEG4EI32_V_M1_M2 + 0U, // PseudoVLOXSEG4EI32_V_M1_M2_MASK + 0U, // PseudoVLOXSEG4EI32_V_M1_MF2 + 0U, // PseudoVLOXSEG4EI32_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG4EI32_V_M1_MF4 + 0U, // PseudoVLOXSEG4EI32_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG4EI32_V_M2_M1 + 0U, // PseudoVLOXSEG4EI32_V_M2_M1_MASK + 0U, // PseudoVLOXSEG4EI32_V_M2_M2 + 0U, // PseudoVLOXSEG4EI32_V_M2_M2_MASK + 0U, // PseudoVLOXSEG4EI32_V_M2_MF2 + 0U, // PseudoVLOXSEG4EI32_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG4EI32_V_M4_M1 + 0U, // PseudoVLOXSEG4EI32_V_M4_M1_MASK + 0U, // PseudoVLOXSEG4EI32_V_M4_M2 + 0U, // PseudoVLOXSEG4EI32_V_M4_M2_MASK + 0U, // PseudoVLOXSEG4EI32_V_M8_M2 + 0U, // PseudoVLOXSEG4EI32_V_M8_M2_MASK + 0U, // PseudoVLOXSEG4EI32_V_MF2_M1 + 0U, // PseudoVLOXSEG4EI32_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG4EI32_V_MF2_MF2 + 0U, // PseudoVLOXSEG4EI32_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG4EI32_V_MF2_MF4 + 0U, // PseudoVLOXSEG4EI32_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG4EI32_V_MF2_MF8 + 0U, // PseudoVLOXSEG4EI32_V_MF2_MF8_MASK + 0U, // PseudoVLOXSEG4EI64_V_M1_M1 + 0U, // PseudoVLOXSEG4EI64_V_M1_M1_MASK + 0U, // PseudoVLOXSEG4EI64_V_M1_MF2 + 0U, // PseudoVLOXSEG4EI64_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG4EI64_V_M1_MF4 + 0U, // PseudoVLOXSEG4EI64_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG4EI64_V_M1_MF8 + 0U, // PseudoVLOXSEG4EI64_V_M1_MF8_MASK + 0U, // PseudoVLOXSEG4EI64_V_M2_M1 + 0U, // PseudoVLOXSEG4EI64_V_M2_M1_MASK + 0U, // PseudoVLOXSEG4EI64_V_M2_M2 + 0U, // PseudoVLOXSEG4EI64_V_M2_M2_MASK + 0U, // PseudoVLOXSEG4EI64_V_M2_MF2 + 0U, // PseudoVLOXSEG4EI64_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG4EI64_V_M2_MF4 + 0U, // PseudoVLOXSEG4EI64_V_M2_MF4_MASK + 0U, // PseudoVLOXSEG4EI64_V_M4_M1 + 0U, // PseudoVLOXSEG4EI64_V_M4_M1_MASK + 0U, // PseudoVLOXSEG4EI64_V_M4_M2 + 0U, // PseudoVLOXSEG4EI64_V_M4_M2_MASK + 0U, // PseudoVLOXSEG4EI64_V_M4_MF2 + 0U, // PseudoVLOXSEG4EI64_V_M4_MF2_MASK + 0U, // PseudoVLOXSEG4EI64_V_M8_M1 + 0U, // PseudoVLOXSEG4EI64_V_M8_M1_MASK + 0U, // PseudoVLOXSEG4EI64_V_M8_M2 + 0U, // PseudoVLOXSEG4EI64_V_M8_M2_MASK + 0U, // PseudoVLOXSEG4EI8_V_M1_M1 + 0U, // PseudoVLOXSEG4EI8_V_M1_M1_MASK + 0U, // PseudoVLOXSEG4EI8_V_M1_M2 + 0U, // PseudoVLOXSEG4EI8_V_M1_M2_MASK + 0U, // PseudoVLOXSEG4EI8_V_M2_M2 + 0U, // PseudoVLOXSEG4EI8_V_M2_M2_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF2_M1 + 0U, // PseudoVLOXSEG4EI8_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF2_M2 + 0U, // PseudoVLOXSEG4EI8_V_MF2_M2_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF2_MF2 + 0U, // PseudoVLOXSEG4EI8_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF4_M1 + 0U, // PseudoVLOXSEG4EI8_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF4_M2 + 0U, // PseudoVLOXSEG4EI8_V_MF4_M2_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF4_MF2 + 0U, // PseudoVLOXSEG4EI8_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF4_MF4 + 0U, // PseudoVLOXSEG4EI8_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF8_M1 + 0U, // PseudoVLOXSEG4EI8_V_MF8_M1_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF8_MF2 + 0U, // PseudoVLOXSEG4EI8_V_MF8_MF2_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF8_MF4 + 0U, // PseudoVLOXSEG4EI8_V_MF8_MF4_MASK + 0U, // PseudoVLOXSEG4EI8_V_MF8_MF8 + 0U, // PseudoVLOXSEG4EI8_V_MF8_MF8_MASK + 0U, // PseudoVLOXSEG5EI16_V_M1_M1 + 0U, // PseudoVLOXSEG5EI16_V_M1_M1_MASK + 0U, // PseudoVLOXSEG5EI16_V_M1_MF2 + 0U, // PseudoVLOXSEG5EI16_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG5EI16_V_M2_M1 + 0U, // PseudoVLOXSEG5EI16_V_M2_M1_MASK + 0U, // PseudoVLOXSEG5EI16_V_MF2_M1 + 0U, // PseudoVLOXSEG5EI16_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG5EI16_V_MF2_MF2 + 0U, // PseudoVLOXSEG5EI16_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG5EI16_V_MF2_MF4 + 0U, // PseudoVLOXSEG5EI16_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG5EI16_V_MF4_M1 + 0U, // PseudoVLOXSEG5EI16_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG5EI16_V_MF4_MF2 + 0U, // PseudoVLOXSEG5EI16_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG5EI16_V_MF4_MF4 + 0U, // PseudoVLOXSEG5EI16_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG5EI16_V_MF4_MF8 + 0U, // PseudoVLOXSEG5EI16_V_MF4_MF8_MASK + 0U, // PseudoVLOXSEG5EI32_V_M1_M1 + 0U, // PseudoVLOXSEG5EI32_V_M1_M1_MASK + 0U, // PseudoVLOXSEG5EI32_V_M1_MF2 + 0U, // PseudoVLOXSEG5EI32_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG5EI32_V_M1_MF4 + 0U, // PseudoVLOXSEG5EI32_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG5EI32_V_M2_M1 + 0U, // PseudoVLOXSEG5EI32_V_M2_M1_MASK + 0U, // PseudoVLOXSEG5EI32_V_M2_MF2 + 0U, // PseudoVLOXSEG5EI32_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG5EI32_V_M4_M1 + 0U, // PseudoVLOXSEG5EI32_V_M4_M1_MASK + 0U, // PseudoVLOXSEG5EI32_V_MF2_M1 + 0U, // PseudoVLOXSEG5EI32_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG5EI32_V_MF2_MF2 + 0U, // PseudoVLOXSEG5EI32_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG5EI32_V_MF2_MF4 + 0U, // PseudoVLOXSEG5EI32_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG5EI32_V_MF2_MF8 + 0U, // PseudoVLOXSEG5EI32_V_MF2_MF8_MASK + 0U, // PseudoVLOXSEG5EI64_V_M1_M1 + 0U, // PseudoVLOXSEG5EI64_V_M1_M1_MASK + 0U, // PseudoVLOXSEG5EI64_V_M1_MF2 + 0U, // PseudoVLOXSEG5EI64_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG5EI64_V_M1_MF4 + 0U, // PseudoVLOXSEG5EI64_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG5EI64_V_M1_MF8 + 0U, // PseudoVLOXSEG5EI64_V_M1_MF8_MASK + 0U, // PseudoVLOXSEG5EI64_V_M2_M1 + 0U, // PseudoVLOXSEG5EI64_V_M2_M1_MASK + 0U, // PseudoVLOXSEG5EI64_V_M2_MF2 + 0U, // PseudoVLOXSEG5EI64_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG5EI64_V_M2_MF4 + 0U, // PseudoVLOXSEG5EI64_V_M2_MF4_MASK + 0U, // PseudoVLOXSEG5EI64_V_M4_M1 + 0U, // PseudoVLOXSEG5EI64_V_M4_M1_MASK + 0U, // PseudoVLOXSEG5EI64_V_M4_MF2 + 0U, // PseudoVLOXSEG5EI64_V_M4_MF2_MASK + 0U, // PseudoVLOXSEG5EI64_V_M8_M1 + 0U, // PseudoVLOXSEG5EI64_V_M8_M1_MASK + 0U, // PseudoVLOXSEG5EI8_V_M1_M1 + 0U, // PseudoVLOXSEG5EI8_V_M1_M1_MASK + 0U, // PseudoVLOXSEG5EI8_V_MF2_M1 + 0U, // PseudoVLOXSEG5EI8_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG5EI8_V_MF2_MF2 + 0U, // PseudoVLOXSEG5EI8_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG5EI8_V_MF4_M1 + 0U, // PseudoVLOXSEG5EI8_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG5EI8_V_MF4_MF2 + 0U, // PseudoVLOXSEG5EI8_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG5EI8_V_MF4_MF4 + 0U, // PseudoVLOXSEG5EI8_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG5EI8_V_MF8_M1 + 0U, // PseudoVLOXSEG5EI8_V_MF8_M1_MASK + 0U, // PseudoVLOXSEG5EI8_V_MF8_MF2 + 0U, // PseudoVLOXSEG5EI8_V_MF8_MF2_MASK + 0U, // PseudoVLOXSEG5EI8_V_MF8_MF4 + 0U, // PseudoVLOXSEG5EI8_V_MF8_MF4_MASK + 0U, // PseudoVLOXSEG5EI8_V_MF8_MF8 + 0U, // PseudoVLOXSEG5EI8_V_MF8_MF8_MASK + 0U, // PseudoVLOXSEG6EI16_V_M1_M1 + 0U, // PseudoVLOXSEG6EI16_V_M1_M1_MASK + 0U, // PseudoVLOXSEG6EI16_V_M1_MF2 + 0U, // PseudoVLOXSEG6EI16_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG6EI16_V_M2_M1 + 0U, // PseudoVLOXSEG6EI16_V_M2_M1_MASK + 0U, // PseudoVLOXSEG6EI16_V_MF2_M1 + 0U, // PseudoVLOXSEG6EI16_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG6EI16_V_MF2_MF2 + 0U, // PseudoVLOXSEG6EI16_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG6EI16_V_MF2_MF4 + 0U, // PseudoVLOXSEG6EI16_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG6EI16_V_MF4_M1 + 0U, // PseudoVLOXSEG6EI16_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG6EI16_V_MF4_MF2 + 0U, // PseudoVLOXSEG6EI16_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG6EI16_V_MF4_MF4 + 0U, // PseudoVLOXSEG6EI16_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG6EI16_V_MF4_MF8 + 0U, // PseudoVLOXSEG6EI16_V_MF4_MF8_MASK + 0U, // PseudoVLOXSEG6EI32_V_M1_M1 + 0U, // PseudoVLOXSEG6EI32_V_M1_M1_MASK + 0U, // PseudoVLOXSEG6EI32_V_M1_MF2 + 0U, // PseudoVLOXSEG6EI32_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG6EI32_V_M1_MF4 + 0U, // PseudoVLOXSEG6EI32_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG6EI32_V_M2_M1 + 0U, // PseudoVLOXSEG6EI32_V_M2_M1_MASK + 0U, // PseudoVLOXSEG6EI32_V_M2_MF2 + 0U, // PseudoVLOXSEG6EI32_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG6EI32_V_M4_M1 + 0U, // PseudoVLOXSEG6EI32_V_M4_M1_MASK + 0U, // PseudoVLOXSEG6EI32_V_MF2_M1 + 0U, // PseudoVLOXSEG6EI32_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG6EI32_V_MF2_MF2 + 0U, // PseudoVLOXSEG6EI32_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG6EI32_V_MF2_MF4 + 0U, // PseudoVLOXSEG6EI32_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG6EI32_V_MF2_MF8 + 0U, // PseudoVLOXSEG6EI32_V_MF2_MF8_MASK + 0U, // PseudoVLOXSEG6EI64_V_M1_M1 + 0U, // PseudoVLOXSEG6EI64_V_M1_M1_MASK + 0U, // PseudoVLOXSEG6EI64_V_M1_MF2 + 0U, // PseudoVLOXSEG6EI64_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG6EI64_V_M1_MF4 + 0U, // PseudoVLOXSEG6EI64_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG6EI64_V_M1_MF8 + 0U, // PseudoVLOXSEG6EI64_V_M1_MF8_MASK + 0U, // PseudoVLOXSEG6EI64_V_M2_M1 + 0U, // PseudoVLOXSEG6EI64_V_M2_M1_MASK + 0U, // PseudoVLOXSEG6EI64_V_M2_MF2 + 0U, // PseudoVLOXSEG6EI64_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG6EI64_V_M2_MF4 + 0U, // PseudoVLOXSEG6EI64_V_M2_MF4_MASK + 0U, // PseudoVLOXSEG6EI64_V_M4_M1 + 0U, // PseudoVLOXSEG6EI64_V_M4_M1_MASK + 0U, // PseudoVLOXSEG6EI64_V_M4_MF2 + 0U, // PseudoVLOXSEG6EI64_V_M4_MF2_MASK + 0U, // PseudoVLOXSEG6EI64_V_M8_M1 + 0U, // PseudoVLOXSEG6EI64_V_M8_M1_MASK + 0U, // PseudoVLOXSEG6EI8_V_M1_M1 + 0U, // PseudoVLOXSEG6EI8_V_M1_M1_MASK + 0U, // PseudoVLOXSEG6EI8_V_MF2_M1 + 0U, // PseudoVLOXSEG6EI8_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG6EI8_V_MF2_MF2 + 0U, // PseudoVLOXSEG6EI8_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG6EI8_V_MF4_M1 + 0U, // PseudoVLOXSEG6EI8_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG6EI8_V_MF4_MF2 + 0U, // PseudoVLOXSEG6EI8_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG6EI8_V_MF4_MF4 + 0U, // PseudoVLOXSEG6EI8_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG6EI8_V_MF8_M1 + 0U, // PseudoVLOXSEG6EI8_V_MF8_M1_MASK + 0U, // PseudoVLOXSEG6EI8_V_MF8_MF2 + 0U, // PseudoVLOXSEG6EI8_V_MF8_MF2_MASK + 0U, // PseudoVLOXSEG6EI8_V_MF8_MF4 + 0U, // PseudoVLOXSEG6EI8_V_MF8_MF4_MASK + 0U, // PseudoVLOXSEG6EI8_V_MF8_MF8 + 0U, // PseudoVLOXSEG6EI8_V_MF8_MF8_MASK + 0U, // PseudoVLOXSEG7EI16_V_M1_M1 + 0U, // PseudoVLOXSEG7EI16_V_M1_M1_MASK + 0U, // PseudoVLOXSEG7EI16_V_M1_MF2 + 0U, // PseudoVLOXSEG7EI16_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG7EI16_V_M2_M1 + 0U, // PseudoVLOXSEG7EI16_V_M2_M1_MASK + 0U, // PseudoVLOXSEG7EI16_V_MF2_M1 + 0U, // PseudoVLOXSEG7EI16_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG7EI16_V_MF2_MF2 + 0U, // PseudoVLOXSEG7EI16_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG7EI16_V_MF2_MF4 + 0U, // PseudoVLOXSEG7EI16_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG7EI16_V_MF4_M1 + 0U, // PseudoVLOXSEG7EI16_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG7EI16_V_MF4_MF2 + 0U, // PseudoVLOXSEG7EI16_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG7EI16_V_MF4_MF4 + 0U, // PseudoVLOXSEG7EI16_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG7EI16_V_MF4_MF8 + 0U, // PseudoVLOXSEG7EI16_V_MF4_MF8_MASK + 0U, // PseudoVLOXSEG7EI32_V_M1_M1 + 0U, // PseudoVLOXSEG7EI32_V_M1_M1_MASK + 0U, // PseudoVLOXSEG7EI32_V_M1_MF2 + 0U, // PseudoVLOXSEG7EI32_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG7EI32_V_M1_MF4 + 0U, // PseudoVLOXSEG7EI32_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG7EI32_V_M2_M1 + 0U, // PseudoVLOXSEG7EI32_V_M2_M1_MASK + 0U, // PseudoVLOXSEG7EI32_V_M2_MF2 + 0U, // PseudoVLOXSEG7EI32_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG7EI32_V_M4_M1 + 0U, // PseudoVLOXSEG7EI32_V_M4_M1_MASK + 0U, // PseudoVLOXSEG7EI32_V_MF2_M1 + 0U, // PseudoVLOXSEG7EI32_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG7EI32_V_MF2_MF2 + 0U, // PseudoVLOXSEG7EI32_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG7EI32_V_MF2_MF4 + 0U, // PseudoVLOXSEG7EI32_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG7EI32_V_MF2_MF8 + 0U, // PseudoVLOXSEG7EI32_V_MF2_MF8_MASK + 0U, // PseudoVLOXSEG7EI64_V_M1_M1 + 0U, // PseudoVLOXSEG7EI64_V_M1_M1_MASK + 0U, // PseudoVLOXSEG7EI64_V_M1_MF2 + 0U, // PseudoVLOXSEG7EI64_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG7EI64_V_M1_MF4 + 0U, // PseudoVLOXSEG7EI64_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG7EI64_V_M1_MF8 + 0U, // PseudoVLOXSEG7EI64_V_M1_MF8_MASK + 0U, // PseudoVLOXSEG7EI64_V_M2_M1 + 0U, // PseudoVLOXSEG7EI64_V_M2_M1_MASK + 0U, // PseudoVLOXSEG7EI64_V_M2_MF2 + 0U, // PseudoVLOXSEG7EI64_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG7EI64_V_M2_MF4 + 0U, // PseudoVLOXSEG7EI64_V_M2_MF4_MASK + 0U, // PseudoVLOXSEG7EI64_V_M4_M1 + 0U, // PseudoVLOXSEG7EI64_V_M4_M1_MASK + 0U, // PseudoVLOXSEG7EI64_V_M4_MF2 + 0U, // PseudoVLOXSEG7EI64_V_M4_MF2_MASK + 0U, // PseudoVLOXSEG7EI64_V_M8_M1 + 0U, // PseudoVLOXSEG7EI64_V_M8_M1_MASK + 0U, // PseudoVLOXSEG7EI8_V_M1_M1 + 0U, // PseudoVLOXSEG7EI8_V_M1_M1_MASK + 0U, // PseudoVLOXSEG7EI8_V_MF2_M1 + 0U, // PseudoVLOXSEG7EI8_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG7EI8_V_MF2_MF2 + 0U, // PseudoVLOXSEG7EI8_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG7EI8_V_MF4_M1 + 0U, // PseudoVLOXSEG7EI8_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG7EI8_V_MF4_MF2 + 0U, // PseudoVLOXSEG7EI8_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG7EI8_V_MF4_MF4 + 0U, // PseudoVLOXSEG7EI8_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG7EI8_V_MF8_M1 + 0U, // PseudoVLOXSEG7EI8_V_MF8_M1_MASK + 0U, // PseudoVLOXSEG7EI8_V_MF8_MF2 + 0U, // PseudoVLOXSEG7EI8_V_MF8_MF2_MASK + 0U, // PseudoVLOXSEG7EI8_V_MF8_MF4 + 0U, // PseudoVLOXSEG7EI8_V_MF8_MF4_MASK + 0U, // PseudoVLOXSEG7EI8_V_MF8_MF8 + 0U, // PseudoVLOXSEG7EI8_V_MF8_MF8_MASK + 0U, // PseudoVLOXSEG8EI16_V_M1_M1 + 0U, // PseudoVLOXSEG8EI16_V_M1_M1_MASK + 0U, // PseudoVLOXSEG8EI16_V_M1_MF2 + 0U, // PseudoVLOXSEG8EI16_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG8EI16_V_M2_M1 + 0U, // PseudoVLOXSEG8EI16_V_M2_M1_MASK + 0U, // PseudoVLOXSEG8EI16_V_MF2_M1 + 0U, // PseudoVLOXSEG8EI16_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG8EI16_V_MF2_MF2 + 0U, // PseudoVLOXSEG8EI16_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG8EI16_V_MF2_MF4 + 0U, // PseudoVLOXSEG8EI16_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG8EI16_V_MF4_M1 + 0U, // PseudoVLOXSEG8EI16_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG8EI16_V_MF4_MF2 + 0U, // PseudoVLOXSEG8EI16_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG8EI16_V_MF4_MF4 + 0U, // PseudoVLOXSEG8EI16_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG8EI16_V_MF4_MF8 + 0U, // PseudoVLOXSEG8EI16_V_MF4_MF8_MASK + 0U, // PseudoVLOXSEG8EI32_V_M1_M1 + 0U, // PseudoVLOXSEG8EI32_V_M1_M1_MASK + 0U, // PseudoVLOXSEG8EI32_V_M1_MF2 + 0U, // PseudoVLOXSEG8EI32_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG8EI32_V_M1_MF4 + 0U, // PseudoVLOXSEG8EI32_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG8EI32_V_M2_M1 + 0U, // PseudoVLOXSEG8EI32_V_M2_M1_MASK + 0U, // PseudoVLOXSEG8EI32_V_M2_MF2 + 0U, // PseudoVLOXSEG8EI32_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG8EI32_V_M4_M1 + 0U, // PseudoVLOXSEG8EI32_V_M4_M1_MASK + 0U, // PseudoVLOXSEG8EI32_V_MF2_M1 + 0U, // PseudoVLOXSEG8EI32_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG8EI32_V_MF2_MF2 + 0U, // PseudoVLOXSEG8EI32_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG8EI32_V_MF2_MF4 + 0U, // PseudoVLOXSEG8EI32_V_MF2_MF4_MASK + 0U, // PseudoVLOXSEG8EI32_V_MF2_MF8 + 0U, // PseudoVLOXSEG8EI32_V_MF2_MF8_MASK + 0U, // PseudoVLOXSEG8EI64_V_M1_M1 + 0U, // PseudoVLOXSEG8EI64_V_M1_M1_MASK + 0U, // PseudoVLOXSEG8EI64_V_M1_MF2 + 0U, // PseudoVLOXSEG8EI64_V_M1_MF2_MASK + 0U, // PseudoVLOXSEG8EI64_V_M1_MF4 + 0U, // PseudoVLOXSEG8EI64_V_M1_MF4_MASK + 0U, // PseudoVLOXSEG8EI64_V_M1_MF8 + 0U, // PseudoVLOXSEG8EI64_V_M1_MF8_MASK + 0U, // PseudoVLOXSEG8EI64_V_M2_M1 + 0U, // PseudoVLOXSEG8EI64_V_M2_M1_MASK + 0U, // PseudoVLOXSEG8EI64_V_M2_MF2 + 0U, // PseudoVLOXSEG8EI64_V_M2_MF2_MASK + 0U, // PseudoVLOXSEG8EI64_V_M2_MF4 + 0U, // PseudoVLOXSEG8EI64_V_M2_MF4_MASK + 0U, // PseudoVLOXSEG8EI64_V_M4_M1 + 0U, // PseudoVLOXSEG8EI64_V_M4_M1_MASK + 0U, // PseudoVLOXSEG8EI64_V_M4_MF2 + 0U, // PseudoVLOXSEG8EI64_V_M4_MF2_MASK + 0U, // PseudoVLOXSEG8EI64_V_M8_M1 + 0U, // PseudoVLOXSEG8EI64_V_M8_M1_MASK + 0U, // PseudoVLOXSEG8EI8_V_M1_M1 + 0U, // PseudoVLOXSEG8EI8_V_M1_M1_MASK + 0U, // PseudoVLOXSEG8EI8_V_MF2_M1 + 0U, // PseudoVLOXSEG8EI8_V_MF2_M1_MASK + 0U, // PseudoVLOXSEG8EI8_V_MF2_MF2 + 0U, // PseudoVLOXSEG8EI8_V_MF2_MF2_MASK + 0U, // PseudoVLOXSEG8EI8_V_MF4_M1 + 0U, // PseudoVLOXSEG8EI8_V_MF4_M1_MASK + 0U, // PseudoVLOXSEG8EI8_V_MF4_MF2 + 0U, // PseudoVLOXSEG8EI8_V_MF4_MF2_MASK + 0U, // PseudoVLOXSEG8EI8_V_MF4_MF4 + 0U, // PseudoVLOXSEG8EI8_V_MF4_MF4_MASK + 0U, // PseudoVLOXSEG8EI8_V_MF8_M1 + 0U, // PseudoVLOXSEG8EI8_V_MF8_M1_MASK + 0U, // PseudoVLOXSEG8EI8_V_MF8_MF2 + 0U, // PseudoVLOXSEG8EI8_V_MF8_MF2_MASK + 0U, // PseudoVLOXSEG8EI8_V_MF8_MF4 + 0U, // PseudoVLOXSEG8EI8_V_MF8_MF4_MASK + 0U, // PseudoVLOXSEG8EI8_V_MF8_MF8 + 0U, // PseudoVLOXSEG8EI8_V_MF8_MF8_MASK + 0U, // PseudoVLSE16_V_M1 + 0U, // PseudoVLSE16_V_M1_MASK + 0U, // PseudoVLSE16_V_M2 + 0U, // PseudoVLSE16_V_M2_MASK + 0U, // PseudoVLSE16_V_M4 + 0U, // PseudoVLSE16_V_M4_MASK + 0U, // PseudoVLSE16_V_M8 + 0U, // PseudoVLSE16_V_M8_MASK + 0U, // PseudoVLSE16_V_MF2 + 0U, // PseudoVLSE16_V_MF2_MASK + 0U, // PseudoVLSE16_V_MF4 + 0U, // PseudoVLSE16_V_MF4_MASK + 0U, // PseudoVLSE32_V_M1 + 0U, // PseudoVLSE32_V_M1_MASK + 0U, // PseudoVLSE32_V_M2 + 0U, // PseudoVLSE32_V_M2_MASK + 0U, // PseudoVLSE32_V_M4 + 0U, // PseudoVLSE32_V_M4_MASK + 0U, // PseudoVLSE32_V_M8 + 0U, // PseudoVLSE32_V_M8_MASK + 0U, // PseudoVLSE32_V_MF2 + 0U, // PseudoVLSE32_V_MF2_MASK + 0U, // PseudoVLSE64_V_M1 + 0U, // PseudoVLSE64_V_M1_MASK + 0U, // PseudoVLSE64_V_M2 + 0U, // PseudoVLSE64_V_M2_MASK + 0U, // PseudoVLSE64_V_M4 + 0U, // PseudoVLSE64_V_M4_MASK + 0U, // PseudoVLSE64_V_M8 + 0U, // PseudoVLSE64_V_M8_MASK + 0U, // PseudoVLSE8_V_M1 + 0U, // PseudoVLSE8_V_M1_MASK + 0U, // PseudoVLSE8_V_M2 + 0U, // PseudoVLSE8_V_M2_MASK + 0U, // PseudoVLSE8_V_M4 + 0U, // PseudoVLSE8_V_M4_MASK + 0U, // PseudoVLSE8_V_M8 + 0U, // PseudoVLSE8_V_M8_MASK + 0U, // PseudoVLSE8_V_MF2 + 0U, // PseudoVLSE8_V_MF2_MASK + 0U, // PseudoVLSE8_V_MF4 + 0U, // PseudoVLSE8_V_MF4_MASK + 0U, // PseudoVLSE8_V_MF8 + 0U, // PseudoVLSE8_V_MF8_MASK + 0U, // PseudoVLSEG2E16FF_V_M1 + 0U, // PseudoVLSEG2E16FF_V_M1_MASK + 0U, // PseudoVLSEG2E16FF_V_M2 + 0U, // PseudoVLSEG2E16FF_V_M2_MASK + 0U, // PseudoVLSEG2E16FF_V_M4 + 0U, // PseudoVLSEG2E16FF_V_M4_MASK + 0U, // PseudoVLSEG2E16FF_V_MF2 + 0U, // PseudoVLSEG2E16FF_V_MF2_MASK + 0U, // PseudoVLSEG2E16FF_V_MF4 + 0U, // PseudoVLSEG2E16FF_V_MF4_MASK + 0U, // PseudoVLSEG2E16_V_M1 + 0U, // PseudoVLSEG2E16_V_M1_MASK + 0U, // PseudoVLSEG2E16_V_M2 + 0U, // PseudoVLSEG2E16_V_M2_MASK + 0U, // PseudoVLSEG2E16_V_M4 + 0U, // PseudoVLSEG2E16_V_M4_MASK + 0U, // PseudoVLSEG2E16_V_MF2 + 0U, // PseudoVLSEG2E16_V_MF2_MASK + 0U, // PseudoVLSEG2E16_V_MF4 + 0U, // PseudoVLSEG2E16_V_MF4_MASK + 0U, // PseudoVLSEG2E32FF_V_M1 + 0U, // PseudoVLSEG2E32FF_V_M1_MASK + 0U, // PseudoVLSEG2E32FF_V_M2 + 0U, // PseudoVLSEG2E32FF_V_M2_MASK + 0U, // PseudoVLSEG2E32FF_V_M4 + 0U, // PseudoVLSEG2E32FF_V_M4_MASK + 0U, // PseudoVLSEG2E32FF_V_MF2 + 0U, // PseudoVLSEG2E32FF_V_MF2_MASK + 0U, // PseudoVLSEG2E32_V_M1 + 0U, // PseudoVLSEG2E32_V_M1_MASK + 0U, // PseudoVLSEG2E32_V_M2 + 0U, // PseudoVLSEG2E32_V_M2_MASK + 0U, // PseudoVLSEG2E32_V_M4 + 0U, // PseudoVLSEG2E32_V_M4_MASK + 0U, // PseudoVLSEG2E32_V_MF2 + 0U, // PseudoVLSEG2E32_V_MF2_MASK + 0U, // PseudoVLSEG2E64FF_V_M1 + 0U, // PseudoVLSEG2E64FF_V_M1_MASK + 0U, // PseudoVLSEG2E64FF_V_M2 + 0U, // PseudoVLSEG2E64FF_V_M2_MASK + 0U, // PseudoVLSEG2E64FF_V_M4 + 0U, // PseudoVLSEG2E64FF_V_M4_MASK + 0U, // PseudoVLSEG2E64_V_M1 + 0U, // PseudoVLSEG2E64_V_M1_MASK + 0U, // PseudoVLSEG2E64_V_M2 + 0U, // PseudoVLSEG2E64_V_M2_MASK + 0U, // PseudoVLSEG2E64_V_M4 + 0U, // PseudoVLSEG2E64_V_M4_MASK + 0U, // PseudoVLSEG2E8FF_V_M1 + 0U, // PseudoVLSEG2E8FF_V_M1_MASK + 0U, // PseudoVLSEG2E8FF_V_M2 + 0U, // PseudoVLSEG2E8FF_V_M2_MASK + 0U, // PseudoVLSEG2E8FF_V_M4 + 0U, // PseudoVLSEG2E8FF_V_M4_MASK + 0U, // PseudoVLSEG2E8FF_V_MF2 + 0U, // PseudoVLSEG2E8FF_V_MF2_MASK + 0U, // PseudoVLSEG2E8FF_V_MF4 + 0U, // PseudoVLSEG2E8FF_V_MF4_MASK + 0U, // PseudoVLSEG2E8FF_V_MF8 + 0U, // PseudoVLSEG2E8FF_V_MF8_MASK + 0U, // PseudoVLSEG2E8_V_M1 + 0U, // PseudoVLSEG2E8_V_M1_MASK + 0U, // PseudoVLSEG2E8_V_M2 + 0U, // PseudoVLSEG2E8_V_M2_MASK + 0U, // PseudoVLSEG2E8_V_M4 + 0U, // PseudoVLSEG2E8_V_M4_MASK + 0U, // PseudoVLSEG2E8_V_MF2 + 0U, // PseudoVLSEG2E8_V_MF2_MASK + 0U, // PseudoVLSEG2E8_V_MF4 + 0U, // PseudoVLSEG2E8_V_MF4_MASK + 0U, // PseudoVLSEG2E8_V_MF8 + 0U, // PseudoVLSEG2E8_V_MF8_MASK + 0U, // PseudoVLSEG3E16FF_V_M1 + 0U, // PseudoVLSEG3E16FF_V_M1_MASK + 0U, // PseudoVLSEG3E16FF_V_M2 + 0U, // PseudoVLSEG3E16FF_V_M2_MASK + 0U, // PseudoVLSEG3E16FF_V_MF2 + 0U, // PseudoVLSEG3E16FF_V_MF2_MASK + 0U, // PseudoVLSEG3E16FF_V_MF4 + 0U, // PseudoVLSEG3E16FF_V_MF4_MASK + 0U, // PseudoVLSEG3E16_V_M1 + 0U, // PseudoVLSEG3E16_V_M1_MASK + 0U, // PseudoVLSEG3E16_V_M2 + 0U, // PseudoVLSEG3E16_V_M2_MASK + 0U, // PseudoVLSEG3E16_V_MF2 + 0U, // PseudoVLSEG3E16_V_MF2_MASK + 0U, // PseudoVLSEG3E16_V_MF4 + 0U, // PseudoVLSEG3E16_V_MF4_MASK + 0U, // PseudoVLSEG3E32FF_V_M1 + 0U, // PseudoVLSEG3E32FF_V_M1_MASK + 0U, // PseudoVLSEG3E32FF_V_M2 + 0U, // PseudoVLSEG3E32FF_V_M2_MASK + 0U, // PseudoVLSEG3E32FF_V_MF2 + 0U, // PseudoVLSEG3E32FF_V_MF2_MASK + 0U, // PseudoVLSEG3E32_V_M1 + 0U, // PseudoVLSEG3E32_V_M1_MASK + 0U, // PseudoVLSEG3E32_V_M2 + 0U, // PseudoVLSEG3E32_V_M2_MASK + 0U, // PseudoVLSEG3E32_V_MF2 + 0U, // PseudoVLSEG3E32_V_MF2_MASK + 0U, // PseudoVLSEG3E64FF_V_M1 + 0U, // PseudoVLSEG3E64FF_V_M1_MASK + 0U, // PseudoVLSEG3E64FF_V_M2 + 0U, // PseudoVLSEG3E64FF_V_M2_MASK + 0U, // PseudoVLSEG3E64_V_M1 + 0U, // PseudoVLSEG3E64_V_M1_MASK + 0U, // PseudoVLSEG3E64_V_M2 + 0U, // PseudoVLSEG3E64_V_M2_MASK + 0U, // PseudoVLSEG3E8FF_V_M1 + 0U, // PseudoVLSEG3E8FF_V_M1_MASK + 0U, // PseudoVLSEG3E8FF_V_M2 + 0U, // PseudoVLSEG3E8FF_V_M2_MASK + 0U, // PseudoVLSEG3E8FF_V_MF2 + 0U, // PseudoVLSEG3E8FF_V_MF2_MASK + 0U, // PseudoVLSEG3E8FF_V_MF4 + 0U, // PseudoVLSEG3E8FF_V_MF4_MASK + 0U, // PseudoVLSEG3E8FF_V_MF8 + 0U, // PseudoVLSEG3E8FF_V_MF8_MASK + 0U, // PseudoVLSEG3E8_V_M1 + 0U, // PseudoVLSEG3E8_V_M1_MASK + 0U, // PseudoVLSEG3E8_V_M2 + 0U, // PseudoVLSEG3E8_V_M2_MASK + 0U, // PseudoVLSEG3E8_V_MF2 + 0U, // PseudoVLSEG3E8_V_MF2_MASK + 0U, // PseudoVLSEG3E8_V_MF4 + 0U, // PseudoVLSEG3E8_V_MF4_MASK + 0U, // PseudoVLSEG3E8_V_MF8 + 0U, // PseudoVLSEG3E8_V_MF8_MASK + 0U, // PseudoVLSEG4E16FF_V_M1 + 0U, // PseudoVLSEG4E16FF_V_M1_MASK + 0U, // PseudoVLSEG4E16FF_V_M2 + 0U, // PseudoVLSEG4E16FF_V_M2_MASK + 0U, // PseudoVLSEG4E16FF_V_MF2 + 0U, // PseudoVLSEG4E16FF_V_MF2_MASK + 0U, // PseudoVLSEG4E16FF_V_MF4 + 0U, // PseudoVLSEG4E16FF_V_MF4_MASK + 0U, // PseudoVLSEG4E16_V_M1 + 0U, // PseudoVLSEG4E16_V_M1_MASK + 0U, // PseudoVLSEG4E16_V_M2 + 0U, // PseudoVLSEG4E16_V_M2_MASK + 0U, // PseudoVLSEG4E16_V_MF2 + 0U, // PseudoVLSEG4E16_V_MF2_MASK + 0U, // PseudoVLSEG4E16_V_MF4 + 0U, // PseudoVLSEG4E16_V_MF4_MASK + 0U, // PseudoVLSEG4E32FF_V_M1 + 0U, // PseudoVLSEG4E32FF_V_M1_MASK + 0U, // PseudoVLSEG4E32FF_V_M2 + 0U, // PseudoVLSEG4E32FF_V_M2_MASK + 0U, // PseudoVLSEG4E32FF_V_MF2 + 0U, // PseudoVLSEG4E32FF_V_MF2_MASK + 0U, // PseudoVLSEG4E32_V_M1 + 0U, // PseudoVLSEG4E32_V_M1_MASK + 0U, // PseudoVLSEG4E32_V_M2 + 0U, // PseudoVLSEG4E32_V_M2_MASK + 0U, // PseudoVLSEG4E32_V_MF2 + 0U, // PseudoVLSEG4E32_V_MF2_MASK + 0U, // PseudoVLSEG4E64FF_V_M1 + 0U, // PseudoVLSEG4E64FF_V_M1_MASK + 0U, // PseudoVLSEG4E64FF_V_M2 + 0U, // PseudoVLSEG4E64FF_V_M2_MASK + 0U, // PseudoVLSEG4E64_V_M1 + 0U, // PseudoVLSEG4E64_V_M1_MASK + 0U, // PseudoVLSEG4E64_V_M2 + 0U, // PseudoVLSEG4E64_V_M2_MASK + 0U, // PseudoVLSEG4E8FF_V_M1 + 0U, // PseudoVLSEG4E8FF_V_M1_MASK + 0U, // PseudoVLSEG4E8FF_V_M2 + 0U, // PseudoVLSEG4E8FF_V_M2_MASK + 0U, // PseudoVLSEG4E8FF_V_MF2 + 0U, // PseudoVLSEG4E8FF_V_MF2_MASK + 0U, // PseudoVLSEG4E8FF_V_MF4 + 0U, // PseudoVLSEG4E8FF_V_MF4_MASK + 0U, // PseudoVLSEG4E8FF_V_MF8 + 0U, // PseudoVLSEG4E8FF_V_MF8_MASK + 0U, // PseudoVLSEG4E8_V_M1 + 0U, // PseudoVLSEG4E8_V_M1_MASK + 0U, // PseudoVLSEG4E8_V_M2 + 0U, // PseudoVLSEG4E8_V_M2_MASK + 0U, // PseudoVLSEG4E8_V_MF2 + 0U, // PseudoVLSEG4E8_V_MF2_MASK + 0U, // PseudoVLSEG4E8_V_MF4 + 0U, // PseudoVLSEG4E8_V_MF4_MASK + 0U, // PseudoVLSEG4E8_V_MF8 + 0U, // PseudoVLSEG4E8_V_MF8_MASK + 0U, // PseudoVLSEG5E16FF_V_M1 + 0U, // PseudoVLSEG5E16FF_V_M1_MASK + 0U, // PseudoVLSEG5E16FF_V_MF2 + 0U, // PseudoVLSEG5E16FF_V_MF2_MASK + 0U, // PseudoVLSEG5E16FF_V_MF4 + 0U, // PseudoVLSEG5E16FF_V_MF4_MASK + 0U, // PseudoVLSEG5E16_V_M1 + 0U, // PseudoVLSEG5E16_V_M1_MASK + 0U, // PseudoVLSEG5E16_V_MF2 + 0U, // PseudoVLSEG5E16_V_MF2_MASK + 0U, // PseudoVLSEG5E16_V_MF4 + 0U, // PseudoVLSEG5E16_V_MF4_MASK + 0U, // PseudoVLSEG5E32FF_V_M1 + 0U, // PseudoVLSEG5E32FF_V_M1_MASK + 0U, // PseudoVLSEG5E32FF_V_MF2 + 0U, // PseudoVLSEG5E32FF_V_MF2_MASK + 0U, // PseudoVLSEG5E32_V_M1 + 0U, // PseudoVLSEG5E32_V_M1_MASK + 0U, // PseudoVLSEG5E32_V_MF2 + 0U, // PseudoVLSEG5E32_V_MF2_MASK + 0U, // PseudoVLSEG5E64FF_V_M1 + 0U, // PseudoVLSEG5E64FF_V_M1_MASK + 0U, // PseudoVLSEG5E64_V_M1 + 0U, // PseudoVLSEG5E64_V_M1_MASK + 0U, // PseudoVLSEG5E8FF_V_M1 + 0U, // PseudoVLSEG5E8FF_V_M1_MASK + 0U, // PseudoVLSEG5E8FF_V_MF2 + 0U, // PseudoVLSEG5E8FF_V_MF2_MASK + 0U, // PseudoVLSEG5E8FF_V_MF4 + 0U, // PseudoVLSEG5E8FF_V_MF4_MASK + 0U, // PseudoVLSEG5E8FF_V_MF8 + 0U, // PseudoVLSEG5E8FF_V_MF8_MASK + 0U, // PseudoVLSEG5E8_V_M1 + 0U, // PseudoVLSEG5E8_V_M1_MASK + 0U, // PseudoVLSEG5E8_V_MF2 + 0U, // PseudoVLSEG5E8_V_MF2_MASK + 0U, // PseudoVLSEG5E8_V_MF4 + 0U, // PseudoVLSEG5E8_V_MF4_MASK + 0U, // PseudoVLSEG5E8_V_MF8 + 0U, // PseudoVLSEG5E8_V_MF8_MASK + 0U, // PseudoVLSEG6E16FF_V_M1 + 0U, // PseudoVLSEG6E16FF_V_M1_MASK + 0U, // PseudoVLSEG6E16FF_V_MF2 + 0U, // PseudoVLSEG6E16FF_V_MF2_MASK + 0U, // PseudoVLSEG6E16FF_V_MF4 + 0U, // PseudoVLSEG6E16FF_V_MF4_MASK + 0U, // PseudoVLSEG6E16_V_M1 + 0U, // PseudoVLSEG6E16_V_M1_MASK + 0U, // PseudoVLSEG6E16_V_MF2 + 0U, // PseudoVLSEG6E16_V_MF2_MASK + 0U, // PseudoVLSEG6E16_V_MF4 + 0U, // PseudoVLSEG6E16_V_MF4_MASK + 0U, // PseudoVLSEG6E32FF_V_M1 + 0U, // PseudoVLSEG6E32FF_V_M1_MASK + 0U, // PseudoVLSEG6E32FF_V_MF2 + 0U, // PseudoVLSEG6E32FF_V_MF2_MASK + 0U, // PseudoVLSEG6E32_V_M1 + 0U, // PseudoVLSEG6E32_V_M1_MASK + 0U, // PseudoVLSEG6E32_V_MF2 + 0U, // PseudoVLSEG6E32_V_MF2_MASK + 0U, // PseudoVLSEG6E64FF_V_M1 + 0U, // PseudoVLSEG6E64FF_V_M1_MASK + 0U, // PseudoVLSEG6E64_V_M1 + 0U, // PseudoVLSEG6E64_V_M1_MASK + 0U, // PseudoVLSEG6E8FF_V_M1 + 0U, // PseudoVLSEG6E8FF_V_M1_MASK + 0U, // PseudoVLSEG6E8FF_V_MF2 + 0U, // PseudoVLSEG6E8FF_V_MF2_MASK + 0U, // PseudoVLSEG6E8FF_V_MF4 + 0U, // PseudoVLSEG6E8FF_V_MF4_MASK + 0U, // PseudoVLSEG6E8FF_V_MF8 + 0U, // PseudoVLSEG6E8FF_V_MF8_MASK + 0U, // PseudoVLSEG6E8_V_M1 + 0U, // PseudoVLSEG6E8_V_M1_MASK + 0U, // PseudoVLSEG6E8_V_MF2 + 0U, // PseudoVLSEG6E8_V_MF2_MASK + 0U, // PseudoVLSEG6E8_V_MF4 + 0U, // PseudoVLSEG6E8_V_MF4_MASK + 0U, // PseudoVLSEG6E8_V_MF8 + 0U, // PseudoVLSEG6E8_V_MF8_MASK + 0U, // PseudoVLSEG7E16FF_V_M1 + 0U, // PseudoVLSEG7E16FF_V_M1_MASK + 0U, // PseudoVLSEG7E16FF_V_MF2 + 0U, // PseudoVLSEG7E16FF_V_MF2_MASK + 0U, // PseudoVLSEG7E16FF_V_MF4 + 0U, // PseudoVLSEG7E16FF_V_MF4_MASK + 0U, // PseudoVLSEG7E16_V_M1 + 0U, // PseudoVLSEG7E16_V_M1_MASK + 0U, // PseudoVLSEG7E16_V_MF2 + 0U, // PseudoVLSEG7E16_V_MF2_MASK + 0U, // PseudoVLSEG7E16_V_MF4 + 0U, // PseudoVLSEG7E16_V_MF4_MASK + 0U, // PseudoVLSEG7E32FF_V_M1 + 0U, // PseudoVLSEG7E32FF_V_M1_MASK + 0U, // PseudoVLSEG7E32FF_V_MF2 + 0U, // PseudoVLSEG7E32FF_V_MF2_MASK + 0U, // PseudoVLSEG7E32_V_M1 + 0U, // PseudoVLSEG7E32_V_M1_MASK + 0U, // PseudoVLSEG7E32_V_MF2 + 0U, // PseudoVLSEG7E32_V_MF2_MASK + 0U, // PseudoVLSEG7E64FF_V_M1 + 0U, // PseudoVLSEG7E64FF_V_M1_MASK + 0U, // PseudoVLSEG7E64_V_M1 + 0U, // PseudoVLSEG7E64_V_M1_MASK + 0U, // PseudoVLSEG7E8FF_V_M1 + 0U, // PseudoVLSEG7E8FF_V_M1_MASK + 0U, // PseudoVLSEG7E8FF_V_MF2 + 0U, // PseudoVLSEG7E8FF_V_MF2_MASK + 0U, // PseudoVLSEG7E8FF_V_MF4 + 0U, // PseudoVLSEG7E8FF_V_MF4_MASK + 0U, // PseudoVLSEG7E8FF_V_MF8 + 0U, // PseudoVLSEG7E8FF_V_MF8_MASK + 0U, // PseudoVLSEG7E8_V_M1 + 0U, // PseudoVLSEG7E8_V_M1_MASK + 0U, // PseudoVLSEG7E8_V_MF2 + 0U, // PseudoVLSEG7E8_V_MF2_MASK + 0U, // PseudoVLSEG7E8_V_MF4 + 0U, // PseudoVLSEG7E8_V_MF4_MASK + 0U, // PseudoVLSEG7E8_V_MF8 + 0U, // PseudoVLSEG7E8_V_MF8_MASK + 0U, // PseudoVLSEG8E16FF_V_M1 + 0U, // PseudoVLSEG8E16FF_V_M1_MASK + 0U, // PseudoVLSEG8E16FF_V_MF2 + 0U, // PseudoVLSEG8E16FF_V_MF2_MASK + 0U, // PseudoVLSEG8E16FF_V_MF4 + 0U, // PseudoVLSEG8E16FF_V_MF4_MASK + 0U, // PseudoVLSEG8E16_V_M1 + 0U, // PseudoVLSEG8E16_V_M1_MASK + 0U, // PseudoVLSEG8E16_V_MF2 + 0U, // PseudoVLSEG8E16_V_MF2_MASK + 0U, // PseudoVLSEG8E16_V_MF4 + 0U, // PseudoVLSEG8E16_V_MF4_MASK + 0U, // PseudoVLSEG8E32FF_V_M1 + 0U, // PseudoVLSEG8E32FF_V_M1_MASK + 0U, // PseudoVLSEG8E32FF_V_MF2 + 0U, // PseudoVLSEG8E32FF_V_MF2_MASK + 0U, // PseudoVLSEG8E32_V_M1 + 0U, // PseudoVLSEG8E32_V_M1_MASK + 0U, // PseudoVLSEG8E32_V_MF2 + 0U, // PseudoVLSEG8E32_V_MF2_MASK + 0U, // PseudoVLSEG8E64FF_V_M1 + 0U, // PseudoVLSEG8E64FF_V_M1_MASK + 0U, // PseudoVLSEG8E64_V_M1 + 0U, // PseudoVLSEG8E64_V_M1_MASK + 0U, // PseudoVLSEG8E8FF_V_M1 + 0U, // PseudoVLSEG8E8FF_V_M1_MASK + 0U, // PseudoVLSEG8E8FF_V_MF2 + 0U, // PseudoVLSEG8E8FF_V_MF2_MASK + 0U, // PseudoVLSEG8E8FF_V_MF4 + 0U, // PseudoVLSEG8E8FF_V_MF4_MASK + 0U, // PseudoVLSEG8E8FF_V_MF8 + 0U, // PseudoVLSEG8E8FF_V_MF8_MASK + 0U, // PseudoVLSEG8E8_V_M1 + 0U, // PseudoVLSEG8E8_V_M1_MASK + 0U, // PseudoVLSEG8E8_V_MF2 + 0U, // PseudoVLSEG8E8_V_MF2_MASK + 0U, // PseudoVLSEG8E8_V_MF4 + 0U, // PseudoVLSEG8E8_V_MF4_MASK + 0U, // PseudoVLSEG8E8_V_MF8 + 0U, // PseudoVLSEG8E8_V_MF8_MASK + 0U, // PseudoVLSSEG2E16_V_M1 + 0U, // PseudoVLSSEG2E16_V_M1_MASK + 0U, // PseudoVLSSEG2E16_V_M2 + 0U, // PseudoVLSSEG2E16_V_M2_MASK + 0U, // PseudoVLSSEG2E16_V_M4 + 0U, // PseudoVLSSEG2E16_V_M4_MASK + 0U, // PseudoVLSSEG2E16_V_MF2 + 0U, // PseudoVLSSEG2E16_V_MF2_MASK + 0U, // PseudoVLSSEG2E16_V_MF4 + 0U, // PseudoVLSSEG2E16_V_MF4_MASK + 0U, // PseudoVLSSEG2E32_V_M1 + 0U, // PseudoVLSSEG2E32_V_M1_MASK + 0U, // PseudoVLSSEG2E32_V_M2 + 0U, // PseudoVLSSEG2E32_V_M2_MASK + 0U, // PseudoVLSSEG2E32_V_M4 + 0U, // PseudoVLSSEG2E32_V_M4_MASK + 0U, // PseudoVLSSEG2E32_V_MF2 + 0U, // PseudoVLSSEG2E32_V_MF2_MASK + 0U, // PseudoVLSSEG2E64_V_M1 + 0U, // PseudoVLSSEG2E64_V_M1_MASK + 0U, // PseudoVLSSEG2E64_V_M2 + 0U, // PseudoVLSSEG2E64_V_M2_MASK + 0U, // PseudoVLSSEG2E64_V_M4 + 0U, // PseudoVLSSEG2E64_V_M4_MASK + 0U, // PseudoVLSSEG2E8_V_M1 + 0U, // PseudoVLSSEG2E8_V_M1_MASK + 0U, // PseudoVLSSEG2E8_V_M2 + 0U, // PseudoVLSSEG2E8_V_M2_MASK + 0U, // PseudoVLSSEG2E8_V_M4 + 0U, // PseudoVLSSEG2E8_V_M4_MASK + 0U, // PseudoVLSSEG2E8_V_MF2 + 0U, // PseudoVLSSEG2E8_V_MF2_MASK + 0U, // PseudoVLSSEG2E8_V_MF4 + 0U, // PseudoVLSSEG2E8_V_MF4_MASK + 0U, // PseudoVLSSEG2E8_V_MF8 + 0U, // PseudoVLSSEG2E8_V_MF8_MASK + 0U, // PseudoVLSSEG3E16_V_M1 + 0U, // PseudoVLSSEG3E16_V_M1_MASK + 0U, // PseudoVLSSEG3E16_V_M2 + 0U, // PseudoVLSSEG3E16_V_M2_MASK + 0U, // PseudoVLSSEG3E16_V_MF2 + 0U, // PseudoVLSSEG3E16_V_MF2_MASK + 0U, // PseudoVLSSEG3E16_V_MF4 + 0U, // PseudoVLSSEG3E16_V_MF4_MASK + 0U, // PseudoVLSSEG3E32_V_M1 + 0U, // PseudoVLSSEG3E32_V_M1_MASK + 0U, // PseudoVLSSEG3E32_V_M2 + 0U, // PseudoVLSSEG3E32_V_M2_MASK + 0U, // PseudoVLSSEG3E32_V_MF2 + 0U, // PseudoVLSSEG3E32_V_MF2_MASK + 0U, // PseudoVLSSEG3E64_V_M1 + 0U, // PseudoVLSSEG3E64_V_M1_MASK + 0U, // PseudoVLSSEG3E64_V_M2 + 0U, // PseudoVLSSEG3E64_V_M2_MASK + 0U, // PseudoVLSSEG3E8_V_M1 + 0U, // PseudoVLSSEG3E8_V_M1_MASK + 0U, // PseudoVLSSEG3E8_V_M2 + 0U, // PseudoVLSSEG3E8_V_M2_MASK + 0U, // PseudoVLSSEG3E8_V_MF2 + 0U, // PseudoVLSSEG3E8_V_MF2_MASK + 0U, // PseudoVLSSEG3E8_V_MF4 + 0U, // PseudoVLSSEG3E8_V_MF4_MASK + 0U, // PseudoVLSSEG3E8_V_MF8 + 0U, // PseudoVLSSEG3E8_V_MF8_MASK + 0U, // PseudoVLSSEG4E16_V_M1 + 0U, // PseudoVLSSEG4E16_V_M1_MASK + 0U, // PseudoVLSSEG4E16_V_M2 + 0U, // PseudoVLSSEG4E16_V_M2_MASK + 0U, // PseudoVLSSEG4E16_V_MF2 + 0U, // PseudoVLSSEG4E16_V_MF2_MASK + 0U, // PseudoVLSSEG4E16_V_MF4 + 0U, // PseudoVLSSEG4E16_V_MF4_MASK + 0U, // PseudoVLSSEG4E32_V_M1 + 0U, // PseudoVLSSEG4E32_V_M1_MASK + 0U, // PseudoVLSSEG4E32_V_M2 + 0U, // PseudoVLSSEG4E32_V_M2_MASK + 0U, // PseudoVLSSEG4E32_V_MF2 + 0U, // PseudoVLSSEG4E32_V_MF2_MASK + 0U, // PseudoVLSSEG4E64_V_M1 + 0U, // PseudoVLSSEG4E64_V_M1_MASK + 0U, // PseudoVLSSEG4E64_V_M2 + 0U, // PseudoVLSSEG4E64_V_M2_MASK + 0U, // PseudoVLSSEG4E8_V_M1 + 0U, // PseudoVLSSEG4E8_V_M1_MASK + 0U, // PseudoVLSSEG4E8_V_M2 + 0U, // PseudoVLSSEG4E8_V_M2_MASK + 0U, // PseudoVLSSEG4E8_V_MF2 + 0U, // PseudoVLSSEG4E8_V_MF2_MASK + 0U, // PseudoVLSSEG4E8_V_MF4 + 0U, // PseudoVLSSEG4E8_V_MF4_MASK + 0U, // PseudoVLSSEG4E8_V_MF8 + 0U, // PseudoVLSSEG4E8_V_MF8_MASK + 0U, // PseudoVLSSEG5E16_V_M1 + 0U, // PseudoVLSSEG5E16_V_M1_MASK + 0U, // PseudoVLSSEG5E16_V_MF2 + 0U, // PseudoVLSSEG5E16_V_MF2_MASK + 0U, // PseudoVLSSEG5E16_V_MF4 + 0U, // PseudoVLSSEG5E16_V_MF4_MASK + 0U, // PseudoVLSSEG5E32_V_M1 + 0U, // PseudoVLSSEG5E32_V_M1_MASK + 0U, // PseudoVLSSEG5E32_V_MF2 + 0U, // PseudoVLSSEG5E32_V_MF2_MASK + 0U, // PseudoVLSSEG5E64_V_M1 + 0U, // PseudoVLSSEG5E64_V_M1_MASK + 0U, // PseudoVLSSEG5E8_V_M1 + 0U, // PseudoVLSSEG5E8_V_M1_MASK + 0U, // PseudoVLSSEG5E8_V_MF2 + 0U, // PseudoVLSSEG5E8_V_MF2_MASK + 0U, // PseudoVLSSEG5E8_V_MF4 + 0U, // PseudoVLSSEG5E8_V_MF4_MASK + 0U, // PseudoVLSSEG5E8_V_MF8 + 0U, // PseudoVLSSEG5E8_V_MF8_MASK + 0U, // PseudoVLSSEG6E16_V_M1 + 0U, // PseudoVLSSEG6E16_V_M1_MASK + 0U, // PseudoVLSSEG6E16_V_MF2 + 0U, // PseudoVLSSEG6E16_V_MF2_MASK + 0U, // PseudoVLSSEG6E16_V_MF4 + 0U, // PseudoVLSSEG6E16_V_MF4_MASK + 0U, // PseudoVLSSEG6E32_V_M1 + 0U, // PseudoVLSSEG6E32_V_M1_MASK + 0U, // PseudoVLSSEG6E32_V_MF2 + 0U, // PseudoVLSSEG6E32_V_MF2_MASK + 0U, // PseudoVLSSEG6E64_V_M1 + 0U, // PseudoVLSSEG6E64_V_M1_MASK + 0U, // PseudoVLSSEG6E8_V_M1 + 0U, // PseudoVLSSEG6E8_V_M1_MASK + 0U, // PseudoVLSSEG6E8_V_MF2 + 0U, // PseudoVLSSEG6E8_V_MF2_MASK + 0U, // PseudoVLSSEG6E8_V_MF4 + 0U, // PseudoVLSSEG6E8_V_MF4_MASK + 0U, // PseudoVLSSEG6E8_V_MF8 + 0U, // PseudoVLSSEG6E8_V_MF8_MASK + 0U, // PseudoVLSSEG7E16_V_M1 + 0U, // PseudoVLSSEG7E16_V_M1_MASK + 0U, // PseudoVLSSEG7E16_V_MF2 + 0U, // PseudoVLSSEG7E16_V_MF2_MASK + 0U, // PseudoVLSSEG7E16_V_MF4 + 0U, // PseudoVLSSEG7E16_V_MF4_MASK + 0U, // PseudoVLSSEG7E32_V_M1 + 0U, // PseudoVLSSEG7E32_V_M1_MASK + 0U, // PseudoVLSSEG7E32_V_MF2 + 0U, // PseudoVLSSEG7E32_V_MF2_MASK + 0U, // PseudoVLSSEG7E64_V_M1 + 0U, // PseudoVLSSEG7E64_V_M1_MASK + 0U, // PseudoVLSSEG7E8_V_M1 + 0U, // PseudoVLSSEG7E8_V_M1_MASK + 0U, // PseudoVLSSEG7E8_V_MF2 + 0U, // PseudoVLSSEG7E8_V_MF2_MASK + 0U, // PseudoVLSSEG7E8_V_MF4 + 0U, // PseudoVLSSEG7E8_V_MF4_MASK + 0U, // PseudoVLSSEG7E8_V_MF8 + 0U, // PseudoVLSSEG7E8_V_MF8_MASK + 0U, // PseudoVLSSEG8E16_V_M1 + 0U, // PseudoVLSSEG8E16_V_M1_MASK + 0U, // PseudoVLSSEG8E16_V_MF2 + 0U, // PseudoVLSSEG8E16_V_MF2_MASK + 0U, // PseudoVLSSEG8E16_V_MF4 + 0U, // PseudoVLSSEG8E16_V_MF4_MASK + 0U, // PseudoVLSSEG8E32_V_M1 + 0U, // PseudoVLSSEG8E32_V_M1_MASK + 0U, // PseudoVLSSEG8E32_V_MF2 + 0U, // PseudoVLSSEG8E32_V_MF2_MASK + 0U, // PseudoVLSSEG8E64_V_M1 + 0U, // PseudoVLSSEG8E64_V_M1_MASK + 0U, // PseudoVLSSEG8E8_V_M1 + 0U, // PseudoVLSSEG8E8_V_M1_MASK + 0U, // PseudoVLSSEG8E8_V_MF2 + 0U, // PseudoVLSSEG8E8_V_MF2_MASK + 0U, // PseudoVLSSEG8E8_V_MF4 + 0U, // PseudoVLSSEG8E8_V_MF4_MASK + 0U, // PseudoVLSSEG8E8_V_MF8 + 0U, // PseudoVLSSEG8E8_V_MF8_MASK + 0U, // PseudoVLUXEI16_V_M1_M1 + 0U, // PseudoVLUXEI16_V_M1_M1_MASK + 0U, // PseudoVLUXEI16_V_M1_M2 + 0U, // PseudoVLUXEI16_V_M1_M2_MASK + 0U, // PseudoVLUXEI16_V_M1_M4 + 0U, // PseudoVLUXEI16_V_M1_M4_MASK + 0U, // PseudoVLUXEI16_V_M1_MF2 + 0U, // PseudoVLUXEI16_V_M1_MF2_MASK + 0U, // PseudoVLUXEI16_V_M2_M1 + 0U, // PseudoVLUXEI16_V_M2_M1_MASK + 0U, // PseudoVLUXEI16_V_M2_M2 + 0U, // PseudoVLUXEI16_V_M2_M2_MASK + 0U, // PseudoVLUXEI16_V_M2_M4 + 0U, // PseudoVLUXEI16_V_M2_M4_MASK + 0U, // PseudoVLUXEI16_V_M2_M8 + 0U, // PseudoVLUXEI16_V_M2_M8_MASK + 0U, // PseudoVLUXEI16_V_M4_M2 + 0U, // PseudoVLUXEI16_V_M4_M2_MASK + 0U, // PseudoVLUXEI16_V_M4_M4 + 0U, // PseudoVLUXEI16_V_M4_M4_MASK + 0U, // PseudoVLUXEI16_V_M4_M8 + 0U, // PseudoVLUXEI16_V_M4_M8_MASK + 0U, // PseudoVLUXEI16_V_M8_M4 + 0U, // PseudoVLUXEI16_V_M8_M4_MASK + 0U, // PseudoVLUXEI16_V_M8_M8 + 0U, // PseudoVLUXEI16_V_M8_M8_MASK + 0U, // PseudoVLUXEI16_V_MF2_M1 + 0U, // PseudoVLUXEI16_V_MF2_M1_MASK + 0U, // PseudoVLUXEI16_V_MF2_M2 + 0U, // PseudoVLUXEI16_V_MF2_M2_MASK + 0U, // PseudoVLUXEI16_V_MF2_MF2 + 0U, // PseudoVLUXEI16_V_MF2_MF2_MASK + 0U, // PseudoVLUXEI16_V_MF2_MF4 + 0U, // PseudoVLUXEI16_V_MF2_MF4_MASK + 0U, // PseudoVLUXEI16_V_MF4_M1 + 0U, // PseudoVLUXEI16_V_MF4_M1_MASK + 0U, // PseudoVLUXEI16_V_MF4_MF2 + 0U, // PseudoVLUXEI16_V_MF4_MF2_MASK + 0U, // PseudoVLUXEI16_V_MF4_MF4 + 0U, // PseudoVLUXEI16_V_MF4_MF4_MASK + 0U, // PseudoVLUXEI16_V_MF4_MF8 + 0U, // PseudoVLUXEI16_V_MF4_MF8_MASK + 0U, // PseudoVLUXEI32_V_M1_M1 + 0U, // PseudoVLUXEI32_V_M1_M1_MASK + 0U, // PseudoVLUXEI32_V_M1_M2 + 0U, // PseudoVLUXEI32_V_M1_M2_MASK + 0U, // PseudoVLUXEI32_V_M1_MF2 + 0U, // PseudoVLUXEI32_V_M1_MF2_MASK + 0U, // PseudoVLUXEI32_V_M1_MF4 + 0U, // PseudoVLUXEI32_V_M1_MF4_MASK + 0U, // PseudoVLUXEI32_V_M2_M1 + 0U, // PseudoVLUXEI32_V_M2_M1_MASK + 0U, // PseudoVLUXEI32_V_M2_M2 + 0U, // PseudoVLUXEI32_V_M2_M2_MASK + 0U, // PseudoVLUXEI32_V_M2_M4 + 0U, // PseudoVLUXEI32_V_M2_M4_MASK + 0U, // PseudoVLUXEI32_V_M2_MF2 + 0U, // PseudoVLUXEI32_V_M2_MF2_MASK + 0U, // PseudoVLUXEI32_V_M4_M1 + 0U, // PseudoVLUXEI32_V_M4_M1_MASK + 0U, // PseudoVLUXEI32_V_M4_M2 + 0U, // PseudoVLUXEI32_V_M4_M2_MASK + 0U, // PseudoVLUXEI32_V_M4_M4 + 0U, // PseudoVLUXEI32_V_M4_M4_MASK + 0U, // PseudoVLUXEI32_V_M4_M8 + 0U, // PseudoVLUXEI32_V_M4_M8_MASK + 0U, // PseudoVLUXEI32_V_M8_M2 + 0U, // PseudoVLUXEI32_V_M8_M2_MASK + 0U, // PseudoVLUXEI32_V_M8_M4 + 0U, // PseudoVLUXEI32_V_M8_M4_MASK + 0U, // PseudoVLUXEI32_V_M8_M8 + 0U, // PseudoVLUXEI32_V_M8_M8_MASK + 0U, // PseudoVLUXEI32_V_MF2_M1 + 0U, // PseudoVLUXEI32_V_MF2_M1_MASK + 0U, // PseudoVLUXEI32_V_MF2_MF2 + 0U, // PseudoVLUXEI32_V_MF2_MF2_MASK + 0U, // PseudoVLUXEI32_V_MF2_MF4 + 0U, // PseudoVLUXEI32_V_MF2_MF4_MASK + 0U, // PseudoVLUXEI32_V_MF2_MF8 + 0U, // PseudoVLUXEI32_V_MF2_MF8_MASK + 0U, // PseudoVLUXEI64_V_M1_M1 + 0U, // PseudoVLUXEI64_V_M1_M1_MASK + 0U, // PseudoVLUXEI64_V_M1_MF2 + 0U, // PseudoVLUXEI64_V_M1_MF2_MASK + 0U, // PseudoVLUXEI64_V_M1_MF4 + 0U, // PseudoVLUXEI64_V_M1_MF4_MASK + 0U, // PseudoVLUXEI64_V_M1_MF8 + 0U, // PseudoVLUXEI64_V_M1_MF8_MASK + 0U, // PseudoVLUXEI64_V_M2_M1 + 0U, // PseudoVLUXEI64_V_M2_M1_MASK + 0U, // PseudoVLUXEI64_V_M2_M2 + 0U, // PseudoVLUXEI64_V_M2_M2_MASK + 0U, // PseudoVLUXEI64_V_M2_MF2 + 0U, // PseudoVLUXEI64_V_M2_MF2_MASK + 0U, // PseudoVLUXEI64_V_M2_MF4 + 0U, // PseudoVLUXEI64_V_M2_MF4_MASK + 0U, // PseudoVLUXEI64_V_M4_M1 + 0U, // PseudoVLUXEI64_V_M4_M1_MASK + 0U, // PseudoVLUXEI64_V_M4_M2 + 0U, // PseudoVLUXEI64_V_M4_M2_MASK + 0U, // PseudoVLUXEI64_V_M4_M4 + 0U, // PseudoVLUXEI64_V_M4_M4_MASK + 0U, // PseudoVLUXEI64_V_M4_MF2 + 0U, // PseudoVLUXEI64_V_M4_MF2_MASK + 0U, // PseudoVLUXEI64_V_M8_M1 + 0U, // PseudoVLUXEI64_V_M8_M1_MASK + 0U, // PseudoVLUXEI64_V_M8_M2 + 0U, // PseudoVLUXEI64_V_M8_M2_MASK + 0U, // PseudoVLUXEI64_V_M8_M4 + 0U, // PseudoVLUXEI64_V_M8_M4_MASK + 0U, // PseudoVLUXEI64_V_M8_M8 + 0U, // PseudoVLUXEI64_V_M8_M8_MASK + 0U, // PseudoVLUXEI8_V_M1_M1 + 0U, // PseudoVLUXEI8_V_M1_M1_MASK + 0U, // PseudoVLUXEI8_V_M1_M2 + 0U, // PseudoVLUXEI8_V_M1_M2_MASK + 0U, // PseudoVLUXEI8_V_M1_M4 + 0U, // PseudoVLUXEI8_V_M1_M4_MASK + 0U, // PseudoVLUXEI8_V_M1_M8 + 0U, // PseudoVLUXEI8_V_M1_M8_MASK + 0U, // PseudoVLUXEI8_V_M2_M2 + 0U, // PseudoVLUXEI8_V_M2_M2_MASK + 0U, // PseudoVLUXEI8_V_M2_M4 + 0U, // PseudoVLUXEI8_V_M2_M4_MASK + 0U, // PseudoVLUXEI8_V_M2_M8 + 0U, // PseudoVLUXEI8_V_M2_M8_MASK + 0U, // PseudoVLUXEI8_V_M4_M4 + 0U, // PseudoVLUXEI8_V_M4_M4_MASK + 0U, // PseudoVLUXEI8_V_M4_M8 + 0U, // PseudoVLUXEI8_V_M4_M8_MASK + 0U, // PseudoVLUXEI8_V_M8_M8 + 0U, // PseudoVLUXEI8_V_M8_M8_MASK + 0U, // PseudoVLUXEI8_V_MF2_M1 + 0U, // PseudoVLUXEI8_V_MF2_M1_MASK + 0U, // PseudoVLUXEI8_V_MF2_M2 + 0U, // PseudoVLUXEI8_V_MF2_M2_MASK + 0U, // PseudoVLUXEI8_V_MF2_M4 + 0U, // PseudoVLUXEI8_V_MF2_M4_MASK + 0U, // PseudoVLUXEI8_V_MF2_MF2 + 0U, // PseudoVLUXEI8_V_MF2_MF2_MASK + 0U, // PseudoVLUXEI8_V_MF4_M1 + 0U, // PseudoVLUXEI8_V_MF4_M1_MASK + 0U, // PseudoVLUXEI8_V_MF4_M2 + 0U, // PseudoVLUXEI8_V_MF4_M2_MASK + 0U, // PseudoVLUXEI8_V_MF4_MF2 + 0U, // PseudoVLUXEI8_V_MF4_MF2_MASK + 0U, // PseudoVLUXEI8_V_MF4_MF4 + 0U, // PseudoVLUXEI8_V_MF4_MF4_MASK + 0U, // PseudoVLUXEI8_V_MF8_M1 + 0U, // PseudoVLUXEI8_V_MF8_M1_MASK + 0U, // PseudoVLUXEI8_V_MF8_MF2 + 0U, // PseudoVLUXEI8_V_MF8_MF2_MASK + 0U, // PseudoVLUXEI8_V_MF8_MF4 + 0U, // PseudoVLUXEI8_V_MF8_MF4_MASK + 0U, // PseudoVLUXEI8_V_MF8_MF8 + 0U, // PseudoVLUXEI8_V_MF8_MF8_MASK + 0U, // PseudoVLUXSEG2EI16_V_M1_M1 + 0U, // PseudoVLUXSEG2EI16_V_M1_M1_MASK + 0U, // PseudoVLUXSEG2EI16_V_M1_M2 + 0U, // PseudoVLUXSEG2EI16_V_M1_M2_MASK + 0U, // PseudoVLUXSEG2EI16_V_M1_M4 + 0U, // PseudoVLUXSEG2EI16_V_M1_M4_MASK + 0U, // PseudoVLUXSEG2EI16_V_M1_MF2 + 0U, // PseudoVLUXSEG2EI16_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG2EI16_V_M2_M1 + 0U, // PseudoVLUXSEG2EI16_V_M2_M1_MASK + 0U, // PseudoVLUXSEG2EI16_V_M2_M2 + 0U, // PseudoVLUXSEG2EI16_V_M2_M2_MASK + 0U, // PseudoVLUXSEG2EI16_V_M2_M4 + 0U, // PseudoVLUXSEG2EI16_V_M2_M4_MASK + 0U, // PseudoVLUXSEG2EI16_V_M4_M2 + 0U, // PseudoVLUXSEG2EI16_V_M4_M2_MASK + 0U, // PseudoVLUXSEG2EI16_V_M4_M4 + 0U, // PseudoVLUXSEG2EI16_V_M4_M4_MASK + 0U, // PseudoVLUXSEG2EI16_V_M8_M4 + 0U, // PseudoVLUXSEG2EI16_V_M8_M4_MASK + 0U, // PseudoVLUXSEG2EI16_V_MF2_M1 + 0U, // PseudoVLUXSEG2EI16_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG2EI16_V_MF2_M2 + 0U, // PseudoVLUXSEG2EI16_V_MF2_M2_MASK + 0U, // PseudoVLUXSEG2EI16_V_MF2_MF2 + 0U, // PseudoVLUXSEG2EI16_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG2EI16_V_MF2_MF4 + 0U, // PseudoVLUXSEG2EI16_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG2EI16_V_MF4_M1 + 0U, // PseudoVLUXSEG2EI16_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG2EI16_V_MF4_MF2 + 0U, // PseudoVLUXSEG2EI16_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG2EI16_V_MF4_MF4 + 0U, // PseudoVLUXSEG2EI16_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG2EI16_V_MF4_MF8 + 0U, // PseudoVLUXSEG2EI16_V_MF4_MF8_MASK + 0U, // PseudoVLUXSEG2EI32_V_M1_M1 + 0U, // PseudoVLUXSEG2EI32_V_M1_M1_MASK + 0U, // PseudoVLUXSEG2EI32_V_M1_M2 + 0U, // PseudoVLUXSEG2EI32_V_M1_M2_MASK + 0U, // PseudoVLUXSEG2EI32_V_M1_MF2 + 0U, // PseudoVLUXSEG2EI32_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG2EI32_V_M1_MF4 + 0U, // PseudoVLUXSEG2EI32_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG2EI32_V_M2_M1 + 0U, // PseudoVLUXSEG2EI32_V_M2_M1_MASK + 0U, // PseudoVLUXSEG2EI32_V_M2_M2 + 0U, // PseudoVLUXSEG2EI32_V_M2_M2_MASK + 0U, // PseudoVLUXSEG2EI32_V_M2_M4 + 0U, // PseudoVLUXSEG2EI32_V_M2_M4_MASK + 0U, // PseudoVLUXSEG2EI32_V_M2_MF2 + 0U, // PseudoVLUXSEG2EI32_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG2EI32_V_M4_M1 + 0U, // PseudoVLUXSEG2EI32_V_M4_M1_MASK + 0U, // PseudoVLUXSEG2EI32_V_M4_M2 + 0U, // PseudoVLUXSEG2EI32_V_M4_M2_MASK + 0U, // PseudoVLUXSEG2EI32_V_M4_M4 + 0U, // PseudoVLUXSEG2EI32_V_M4_M4_MASK + 0U, // PseudoVLUXSEG2EI32_V_M8_M2 + 0U, // PseudoVLUXSEG2EI32_V_M8_M2_MASK + 0U, // PseudoVLUXSEG2EI32_V_M8_M4 + 0U, // PseudoVLUXSEG2EI32_V_M8_M4_MASK + 0U, // PseudoVLUXSEG2EI32_V_MF2_M1 + 0U, // PseudoVLUXSEG2EI32_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG2EI32_V_MF2_MF2 + 0U, // PseudoVLUXSEG2EI32_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG2EI32_V_MF2_MF4 + 0U, // PseudoVLUXSEG2EI32_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG2EI32_V_MF2_MF8 + 0U, // PseudoVLUXSEG2EI32_V_MF2_MF8_MASK + 0U, // PseudoVLUXSEG2EI64_V_M1_M1 + 0U, // PseudoVLUXSEG2EI64_V_M1_M1_MASK + 0U, // PseudoVLUXSEG2EI64_V_M1_MF2 + 0U, // PseudoVLUXSEG2EI64_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG2EI64_V_M1_MF4 + 0U, // PseudoVLUXSEG2EI64_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG2EI64_V_M1_MF8 + 0U, // PseudoVLUXSEG2EI64_V_M1_MF8_MASK + 0U, // PseudoVLUXSEG2EI64_V_M2_M1 + 0U, // PseudoVLUXSEG2EI64_V_M2_M1_MASK + 0U, // PseudoVLUXSEG2EI64_V_M2_M2 + 0U, // PseudoVLUXSEG2EI64_V_M2_M2_MASK + 0U, // PseudoVLUXSEG2EI64_V_M2_MF2 + 0U, // PseudoVLUXSEG2EI64_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG2EI64_V_M2_MF4 + 0U, // PseudoVLUXSEG2EI64_V_M2_MF4_MASK + 0U, // PseudoVLUXSEG2EI64_V_M4_M1 + 0U, // PseudoVLUXSEG2EI64_V_M4_M1_MASK + 0U, // PseudoVLUXSEG2EI64_V_M4_M2 + 0U, // PseudoVLUXSEG2EI64_V_M4_M2_MASK + 0U, // PseudoVLUXSEG2EI64_V_M4_M4 + 0U, // PseudoVLUXSEG2EI64_V_M4_M4_MASK + 0U, // PseudoVLUXSEG2EI64_V_M4_MF2 + 0U, // PseudoVLUXSEG2EI64_V_M4_MF2_MASK + 0U, // PseudoVLUXSEG2EI64_V_M8_M1 + 0U, // PseudoVLUXSEG2EI64_V_M8_M1_MASK + 0U, // PseudoVLUXSEG2EI64_V_M8_M2 + 0U, // PseudoVLUXSEG2EI64_V_M8_M2_MASK + 0U, // PseudoVLUXSEG2EI64_V_M8_M4 + 0U, // PseudoVLUXSEG2EI64_V_M8_M4_MASK + 0U, // PseudoVLUXSEG2EI8_V_M1_M1 + 0U, // PseudoVLUXSEG2EI8_V_M1_M1_MASK + 0U, // PseudoVLUXSEG2EI8_V_M1_M2 + 0U, // PseudoVLUXSEG2EI8_V_M1_M2_MASK + 0U, // PseudoVLUXSEG2EI8_V_M1_M4 + 0U, // PseudoVLUXSEG2EI8_V_M1_M4_MASK + 0U, // PseudoVLUXSEG2EI8_V_M2_M2 + 0U, // PseudoVLUXSEG2EI8_V_M2_M2_MASK + 0U, // PseudoVLUXSEG2EI8_V_M2_M4 + 0U, // PseudoVLUXSEG2EI8_V_M2_M4_MASK + 0U, // PseudoVLUXSEG2EI8_V_M4_M4 + 0U, // PseudoVLUXSEG2EI8_V_M4_M4_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF2_M1 + 0U, // PseudoVLUXSEG2EI8_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF2_M2 + 0U, // PseudoVLUXSEG2EI8_V_MF2_M2_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF2_M4 + 0U, // PseudoVLUXSEG2EI8_V_MF2_M4_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF2_MF2 + 0U, // PseudoVLUXSEG2EI8_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF4_M1 + 0U, // PseudoVLUXSEG2EI8_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF4_M2 + 0U, // PseudoVLUXSEG2EI8_V_MF4_M2_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF4_MF2 + 0U, // PseudoVLUXSEG2EI8_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF4_MF4 + 0U, // PseudoVLUXSEG2EI8_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF8_M1 + 0U, // PseudoVLUXSEG2EI8_V_MF8_M1_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF8_MF2 + 0U, // PseudoVLUXSEG2EI8_V_MF8_MF2_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF8_MF4 + 0U, // PseudoVLUXSEG2EI8_V_MF8_MF4_MASK + 0U, // PseudoVLUXSEG2EI8_V_MF8_MF8 + 0U, // PseudoVLUXSEG2EI8_V_MF8_MF8_MASK + 0U, // PseudoVLUXSEG3EI16_V_M1_M1 + 0U, // PseudoVLUXSEG3EI16_V_M1_M1_MASK + 0U, // PseudoVLUXSEG3EI16_V_M1_M2 + 0U, // PseudoVLUXSEG3EI16_V_M1_M2_MASK + 0U, // PseudoVLUXSEG3EI16_V_M1_MF2 + 0U, // PseudoVLUXSEG3EI16_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG3EI16_V_M2_M1 + 0U, // PseudoVLUXSEG3EI16_V_M2_M1_MASK + 0U, // PseudoVLUXSEG3EI16_V_M2_M2 + 0U, // PseudoVLUXSEG3EI16_V_M2_M2_MASK + 0U, // PseudoVLUXSEG3EI16_V_M4_M2 + 0U, // PseudoVLUXSEG3EI16_V_M4_M2_MASK + 0U, // PseudoVLUXSEG3EI16_V_MF2_M1 + 0U, // PseudoVLUXSEG3EI16_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG3EI16_V_MF2_M2 + 0U, // PseudoVLUXSEG3EI16_V_MF2_M2_MASK + 0U, // PseudoVLUXSEG3EI16_V_MF2_MF2 + 0U, // PseudoVLUXSEG3EI16_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG3EI16_V_MF2_MF4 + 0U, // PseudoVLUXSEG3EI16_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG3EI16_V_MF4_M1 + 0U, // PseudoVLUXSEG3EI16_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG3EI16_V_MF4_MF2 + 0U, // PseudoVLUXSEG3EI16_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG3EI16_V_MF4_MF4 + 0U, // PseudoVLUXSEG3EI16_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG3EI16_V_MF4_MF8 + 0U, // PseudoVLUXSEG3EI16_V_MF4_MF8_MASK + 0U, // PseudoVLUXSEG3EI32_V_M1_M1 + 0U, // PseudoVLUXSEG3EI32_V_M1_M1_MASK + 0U, // PseudoVLUXSEG3EI32_V_M1_M2 + 0U, // PseudoVLUXSEG3EI32_V_M1_M2_MASK + 0U, // PseudoVLUXSEG3EI32_V_M1_MF2 + 0U, // PseudoVLUXSEG3EI32_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG3EI32_V_M1_MF4 + 0U, // PseudoVLUXSEG3EI32_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG3EI32_V_M2_M1 + 0U, // PseudoVLUXSEG3EI32_V_M2_M1_MASK + 0U, // PseudoVLUXSEG3EI32_V_M2_M2 + 0U, // PseudoVLUXSEG3EI32_V_M2_M2_MASK + 0U, // PseudoVLUXSEG3EI32_V_M2_MF2 + 0U, // PseudoVLUXSEG3EI32_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG3EI32_V_M4_M1 + 0U, // PseudoVLUXSEG3EI32_V_M4_M1_MASK + 0U, // PseudoVLUXSEG3EI32_V_M4_M2 + 0U, // PseudoVLUXSEG3EI32_V_M4_M2_MASK + 0U, // PseudoVLUXSEG3EI32_V_M8_M2 + 0U, // PseudoVLUXSEG3EI32_V_M8_M2_MASK + 0U, // PseudoVLUXSEG3EI32_V_MF2_M1 + 0U, // PseudoVLUXSEG3EI32_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG3EI32_V_MF2_MF2 + 0U, // PseudoVLUXSEG3EI32_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG3EI32_V_MF2_MF4 + 0U, // PseudoVLUXSEG3EI32_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG3EI32_V_MF2_MF8 + 0U, // PseudoVLUXSEG3EI32_V_MF2_MF8_MASK + 0U, // PseudoVLUXSEG3EI64_V_M1_M1 + 0U, // PseudoVLUXSEG3EI64_V_M1_M1_MASK + 0U, // PseudoVLUXSEG3EI64_V_M1_MF2 + 0U, // PseudoVLUXSEG3EI64_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG3EI64_V_M1_MF4 + 0U, // PseudoVLUXSEG3EI64_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG3EI64_V_M1_MF8 + 0U, // PseudoVLUXSEG3EI64_V_M1_MF8_MASK + 0U, // PseudoVLUXSEG3EI64_V_M2_M1 + 0U, // PseudoVLUXSEG3EI64_V_M2_M1_MASK + 0U, // PseudoVLUXSEG3EI64_V_M2_M2 + 0U, // PseudoVLUXSEG3EI64_V_M2_M2_MASK + 0U, // PseudoVLUXSEG3EI64_V_M2_MF2 + 0U, // PseudoVLUXSEG3EI64_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG3EI64_V_M2_MF4 + 0U, // PseudoVLUXSEG3EI64_V_M2_MF4_MASK + 0U, // PseudoVLUXSEG3EI64_V_M4_M1 + 0U, // PseudoVLUXSEG3EI64_V_M4_M1_MASK + 0U, // PseudoVLUXSEG3EI64_V_M4_M2 + 0U, // PseudoVLUXSEG3EI64_V_M4_M2_MASK + 0U, // PseudoVLUXSEG3EI64_V_M4_MF2 + 0U, // PseudoVLUXSEG3EI64_V_M4_MF2_MASK + 0U, // PseudoVLUXSEG3EI64_V_M8_M1 + 0U, // PseudoVLUXSEG3EI64_V_M8_M1_MASK + 0U, // PseudoVLUXSEG3EI64_V_M8_M2 + 0U, // PseudoVLUXSEG3EI64_V_M8_M2_MASK + 0U, // PseudoVLUXSEG3EI8_V_M1_M1 + 0U, // PseudoVLUXSEG3EI8_V_M1_M1_MASK + 0U, // PseudoVLUXSEG3EI8_V_M1_M2 + 0U, // PseudoVLUXSEG3EI8_V_M1_M2_MASK + 0U, // PseudoVLUXSEG3EI8_V_M2_M2 + 0U, // PseudoVLUXSEG3EI8_V_M2_M2_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF2_M1 + 0U, // PseudoVLUXSEG3EI8_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF2_M2 + 0U, // PseudoVLUXSEG3EI8_V_MF2_M2_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF2_MF2 + 0U, // PseudoVLUXSEG3EI8_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF4_M1 + 0U, // PseudoVLUXSEG3EI8_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF4_M2 + 0U, // PseudoVLUXSEG3EI8_V_MF4_M2_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF4_MF2 + 0U, // PseudoVLUXSEG3EI8_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF4_MF4 + 0U, // PseudoVLUXSEG3EI8_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF8_M1 + 0U, // PseudoVLUXSEG3EI8_V_MF8_M1_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF8_MF2 + 0U, // PseudoVLUXSEG3EI8_V_MF8_MF2_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF8_MF4 + 0U, // PseudoVLUXSEG3EI8_V_MF8_MF4_MASK + 0U, // PseudoVLUXSEG3EI8_V_MF8_MF8 + 0U, // PseudoVLUXSEG3EI8_V_MF8_MF8_MASK + 0U, // PseudoVLUXSEG4EI16_V_M1_M1 + 0U, // PseudoVLUXSEG4EI16_V_M1_M1_MASK + 0U, // PseudoVLUXSEG4EI16_V_M1_M2 + 0U, // PseudoVLUXSEG4EI16_V_M1_M2_MASK + 0U, // PseudoVLUXSEG4EI16_V_M1_MF2 + 0U, // PseudoVLUXSEG4EI16_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG4EI16_V_M2_M1 + 0U, // PseudoVLUXSEG4EI16_V_M2_M1_MASK + 0U, // PseudoVLUXSEG4EI16_V_M2_M2 + 0U, // PseudoVLUXSEG4EI16_V_M2_M2_MASK + 0U, // PseudoVLUXSEG4EI16_V_M4_M2 + 0U, // PseudoVLUXSEG4EI16_V_M4_M2_MASK + 0U, // PseudoVLUXSEG4EI16_V_MF2_M1 + 0U, // PseudoVLUXSEG4EI16_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG4EI16_V_MF2_M2 + 0U, // PseudoVLUXSEG4EI16_V_MF2_M2_MASK + 0U, // PseudoVLUXSEG4EI16_V_MF2_MF2 + 0U, // PseudoVLUXSEG4EI16_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG4EI16_V_MF2_MF4 + 0U, // PseudoVLUXSEG4EI16_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG4EI16_V_MF4_M1 + 0U, // PseudoVLUXSEG4EI16_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG4EI16_V_MF4_MF2 + 0U, // PseudoVLUXSEG4EI16_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG4EI16_V_MF4_MF4 + 0U, // PseudoVLUXSEG4EI16_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG4EI16_V_MF4_MF8 + 0U, // PseudoVLUXSEG4EI16_V_MF4_MF8_MASK + 0U, // PseudoVLUXSEG4EI32_V_M1_M1 + 0U, // PseudoVLUXSEG4EI32_V_M1_M1_MASK + 0U, // PseudoVLUXSEG4EI32_V_M1_M2 + 0U, // PseudoVLUXSEG4EI32_V_M1_M2_MASK + 0U, // PseudoVLUXSEG4EI32_V_M1_MF2 + 0U, // PseudoVLUXSEG4EI32_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG4EI32_V_M1_MF4 + 0U, // PseudoVLUXSEG4EI32_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG4EI32_V_M2_M1 + 0U, // PseudoVLUXSEG4EI32_V_M2_M1_MASK + 0U, // PseudoVLUXSEG4EI32_V_M2_M2 + 0U, // PseudoVLUXSEG4EI32_V_M2_M2_MASK + 0U, // PseudoVLUXSEG4EI32_V_M2_MF2 + 0U, // PseudoVLUXSEG4EI32_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG4EI32_V_M4_M1 + 0U, // PseudoVLUXSEG4EI32_V_M4_M1_MASK + 0U, // PseudoVLUXSEG4EI32_V_M4_M2 + 0U, // PseudoVLUXSEG4EI32_V_M4_M2_MASK + 0U, // PseudoVLUXSEG4EI32_V_M8_M2 + 0U, // PseudoVLUXSEG4EI32_V_M8_M2_MASK + 0U, // PseudoVLUXSEG4EI32_V_MF2_M1 + 0U, // PseudoVLUXSEG4EI32_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG4EI32_V_MF2_MF2 + 0U, // PseudoVLUXSEG4EI32_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG4EI32_V_MF2_MF4 + 0U, // PseudoVLUXSEG4EI32_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG4EI32_V_MF2_MF8 + 0U, // PseudoVLUXSEG4EI32_V_MF2_MF8_MASK + 0U, // PseudoVLUXSEG4EI64_V_M1_M1 + 0U, // PseudoVLUXSEG4EI64_V_M1_M1_MASK + 0U, // PseudoVLUXSEG4EI64_V_M1_MF2 + 0U, // PseudoVLUXSEG4EI64_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG4EI64_V_M1_MF4 + 0U, // PseudoVLUXSEG4EI64_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG4EI64_V_M1_MF8 + 0U, // PseudoVLUXSEG4EI64_V_M1_MF8_MASK + 0U, // PseudoVLUXSEG4EI64_V_M2_M1 + 0U, // PseudoVLUXSEG4EI64_V_M2_M1_MASK + 0U, // PseudoVLUXSEG4EI64_V_M2_M2 + 0U, // PseudoVLUXSEG4EI64_V_M2_M2_MASK + 0U, // PseudoVLUXSEG4EI64_V_M2_MF2 + 0U, // PseudoVLUXSEG4EI64_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG4EI64_V_M2_MF4 + 0U, // PseudoVLUXSEG4EI64_V_M2_MF4_MASK + 0U, // PseudoVLUXSEG4EI64_V_M4_M1 + 0U, // PseudoVLUXSEG4EI64_V_M4_M1_MASK + 0U, // PseudoVLUXSEG4EI64_V_M4_M2 + 0U, // PseudoVLUXSEG4EI64_V_M4_M2_MASK + 0U, // PseudoVLUXSEG4EI64_V_M4_MF2 + 0U, // PseudoVLUXSEG4EI64_V_M4_MF2_MASK + 0U, // PseudoVLUXSEG4EI64_V_M8_M1 + 0U, // PseudoVLUXSEG4EI64_V_M8_M1_MASK + 0U, // PseudoVLUXSEG4EI64_V_M8_M2 + 0U, // PseudoVLUXSEG4EI64_V_M8_M2_MASK + 0U, // PseudoVLUXSEG4EI8_V_M1_M1 + 0U, // PseudoVLUXSEG4EI8_V_M1_M1_MASK + 0U, // PseudoVLUXSEG4EI8_V_M1_M2 + 0U, // PseudoVLUXSEG4EI8_V_M1_M2_MASK + 0U, // PseudoVLUXSEG4EI8_V_M2_M2 + 0U, // PseudoVLUXSEG4EI8_V_M2_M2_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF2_M1 + 0U, // PseudoVLUXSEG4EI8_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF2_M2 + 0U, // PseudoVLUXSEG4EI8_V_MF2_M2_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF2_MF2 + 0U, // PseudoVLUXSEG4EI8_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF4_M1 + 0U, // PseudoVLUXSEG4EI8_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF4_M2 + 0U, // PseudoVLUXSEG4EI8_V_MF4_M2_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF4_MF2 + 0U, // PseudoVLUXSEG4EI8_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF4_MF4 + 0U, // PseudoVLUXSEG4EI8_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF8_M1 + 0U, // PseudoVLUXSEG4EI8_V_MF8_M1_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF8_MF2 + 0U, // PseudoVLUXSEG4EI8_V_MF8_MF2_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF8_MF4 + 0U, // PseudoVLUXSEG4EI8_V_MF8_MF4_MASK + 0U, // PseudoVLUXSEG4EI8_V_MF8_MF8 + 0U, // PseudoVLUXSEG4EI8_V_MF8_MF8_MASK + 0U, // PseudoVLUXSEG5EI16_V_M1_M1 + 0U, // PseudoVLUXSEG5EI16_V_M1_M1_MASK + 0U, // PseudoVLUXSEG5EI16_V_M1_MF2 + 0U, // PseudoVLUXSEG5EI16_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG5EI16_V_M2_M1 + 0U, // PseudoVLUXSEG5EI16_V_M2_M1_MASK + 0U, // PseudoVLUXSEG5EI16_V_MF2_M1 + 0U, // PseudoVLUXSEG5EI16_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG5EI16_V_MF2_MF2 + 0U, // PseudoVLUXSEG5EI16_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG5EI16_V_MF2_MF4 + 0U, // PseudoVLUXSEG5EI16_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG5EI16_V_MF4_M1 + 0U, // PseudoVLUXSEG5EI16_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG5EI16_V_MF4_MF2 + 0U, // PseudoVLUXSEG5EI16_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG5EI16_V_MF4_MF4 + 0U, // PseudoVLUXSEG5EI16_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG5EI16_V_MF4_MF8 + 0U, // PseudoVLUXSEG5EI16_V_MF4_MF8_MASK + 0U, // PseudoVLUXSEG5EI32_V_M1_M1 + 0U, // PseudoVLUXSEG5EI32_V_M1_M1_MASK + 0U, // PseudoVLUXSEG5EI32_V_M1_MF2 + 0U, // PseudoVLUXSEG5EI32_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG5EI32_V_M1_MF4 + 0U, // PseudoVLUXSEG5EI32_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG5EI32_V_M2_M1 + 0U, // PseudoVLUXSEG5EI32_V_M2_M1_MASK + 0U, // PseudoVLUXSEG5EI32_V_M2_MF2 + 0U, // PseudoVLUXSEG5EI32_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG5EI32_V_M4_M1 + 0U, // PseudoVLUXSEG5EI32_V_M4_M1_MASK + 0U, // PseudoVLUXSEG5EI32_V_MF2_M1 + 0U, // PseudoVLUXSEG5EI32_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG5EI32_V_MF2_MF2 + 0U, // PseudoVLUXSEG5EI32_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG5EI32_V_MF2_MF4 + 0U, // PseudoVLUXSEG5EI32_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG5EI32_V_MF2_MF8 + 0U, // PseudoVLUXSEG5EI32_V_MF2_MF8_MASK + 0U, // PseudoVLUXSEG5EI64_V_M1_M1 + 0U, // PseudoVLUXSEG5EI64_V_M1_M1_MASK + 0U, // PseudoVLUXSEG5EI64_V_M1_MF2 + 0U, // PseudoVLUXSEG5EI64_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG5EI64_V_M1_MF4 + 0U, // PseudoVLUXSEG5EI64_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG5EI64_V_M1_MF8 + 0U, // PseudoVLUXSEG5EI64_V_M1_MF8_MASK + 0U, // PseudoVLUXSEG5EI64_V_M2_M1 + 0U, // PseudoVLUXSEG5EI64_V_M2_M1_MASK + 0U, // PseudoVLUXSEG5EI64_V_M2_MF2 + 0U, // PseudoVLUXSEG5EI64_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG5EI64_V_M2_MF4 + 0U, // PseudoVLUXSEG5EI64_V_M2_MF4_MASK + 0U, // PseudoVLUXSEG5EI64_V_M4_M1 + 0U, // PseudoVLUXSEG5EI64_V_M4_M1_MASK + 0U, // PseudoVLUXSEG5EI64_V_M4_MF2 + 0U, // PseudoVLUXSEG5EI64_V_M4_MF2_MASK + 0U, // PseudoVLUXSEG5EI64_V_M8_M1 + 0U, // PseudoVLUXSEG5EI64_V_M8_M1_MASK + 0U, // PseudoVLUXSEG5EI8_V_M1_M1 + 0U, // PseudoVLUXSEG5EI8_V_M1_M1_MASK + 0U, // PseudoVLUXSEG5EI8_V_MF2_M1 + 0U, // PseudoVLUXSEG5EI8_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG5EI8_V_MF2_MF2 + 0U, // PseudoVLUXSEG5EI8_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG5EI8_V_MF4_M1 + 0U, // PseudoVLUXSEG5EI8_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG5EI8_V_MF4_MF2 + 0U, // PseudoVLUXSEG5EI8_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG5EI8_V_MF4_MF4 + 0U, // PseudoVLUXSEG5EI8_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG5EI8_V_MF8_M1 + 0U, // PseudoVLUXSEG5EI8_V_MF8_M1_MASK + 0U, // PseudoVLUXSEG5EI8_V_MF8_MF2 + 0U, // PseudoVLUXSEG5EI8_V_MF8_MF2_MASK + 0U, // PseudoVLUXSEG5EI8_V_MF8_MF4 + 0U, // PseudoVLUXSEG5EI8_V_MF8_MF4_MASK + 0U, // PseudoVLUXSEG5EI8_V_MF8_MF8 + 0U, // PseudoVLUXSEG5EI8_V_MF8_MF8_MASK + 0U, // PseudoVLUXSEG6EI16_V_M1_M1 + 0U, // PseudoVLUXSEG6EI16_V_M1_M1_MASK + 0U, // PseudoVLUXSEG6EI16_V_M1_MF2 + 0U, // PseudoVLUXSEG6EI16_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG6EI16_V_M2_M1 + 0U, // PseudoVLUXSEG6EI16_V_M2_M1_MASK + 0U, // PseudoVLUXSEG6EI16_V_MF2_M1 + 0U, // PseudoVLUXSEG6EI16_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG6EI16_V_MF2_MF2 + 0U, // PseudoVLUXSEG6EI16_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG6EI16_V_MF2_MF4 + 0U, // PseudoVLUXSEG6EI16_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG6EI16_V_MF4_M1 + 0U, // PseudoVLUXSEG6EI16_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG6EI16_V_MF4_MF2 + 0U, // PseudoVLUXSEG6EI16_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG6EI16_V_MF4_MF4 + 0U, // PseudoVLUXSEG6EI16_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG6EI16_V_MF4_MF8 + 0U, // PseudoVLUXSEG6EI16_V_MF4_MF8_MASK + 0U, // PseudoVLUXSEG6EI32_V_M1_M1 + 0U, // PseudoVLUXSEG6EI32_V_M1_M1_MASK + 0U, // PseudoVLUXSEG6EI32_V_M1_MF2 + 0U, // PseudoVLUXSEG6EI32_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG6EI32_V_M1_MF4 + 0U, // PseudoVLUXSEG6EI32_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG6EI32_V_M2_M1 + 0U, // PseudoVLUXSEG6EI32_V_M2_M1_MASK + 0U, // PseudoVLUXSEG6EI32_V_M2_MF2 + 0U, // PseudoVLUXSEG6EI32_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG6EI32_V_M4_M1 + 0U, // PseudoVLUXSEG6EI32_V_M4_M1_MASK + 0U, // PseudoVLUXSEG6EI32_V_MF2_M1 + 0U, // PseudoVLUXSEG6EI32_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG6EI32_V_MF2_MF2 + 0U, // PseudoVLUXSEG6EI32_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG6EI32_V_MF2_MF4 + 0U, // PseudoVLUXSEG6EI32_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG6EI32_V_MF2_MF8 + 0U, // PseudoVLUXSEG6EI32_V_MF2_MF8_MASK + 0U, // PseudoVLUXSEG6EI64_V_M1_M1 + 0U, // PseudoVLUXSEG6EI64_V_M1_M1_MASK + 0U, // PseudoVLUXSEG6EI64_V_M1_MF2 + 0U, // PseudoVLUXSEG6EI64_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG6EI64_V_M1_MF4 + 0U, // PseudoVLUXSEG6EI64_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG6EI64_V_M1_MF8 + 0U, // PseudoVLUXSEG6EI64_V_M1_MF8_MASK + 0U, // PseudoVLUXSEG6EI64_V_M2_M1 + 0U, // PseudoVLUXSEG6EI64_V_M2_M1_MASK + 0U, // PseudoVLUXSEG6EI64_V_M2_MF2 + 0U, // PseudoVLUXSEG6EI64_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG6EI64_V_M2_MF4 + 0U, // PseudoVLUXSEG6EI64_V_M2_MF4_MASK + 0U, // PseudoVLUXSEG6EI64_V_M4_M1 + 0U, // PseudoVLUXSEG6EI64_V_M4_M1_MASK + 0U, // PseudoVLUXSEG6EI64_V_M4_MF2 + 0U, // PseudoVLUXSEG6EI64_V_M4_MF2_MASK + 0U, // PseudoVLUXSEG6EI64_V_M8_M1 + 0U, // PseudoVLUXSEG6EI64_V_M8_M1_MASK + 0U, // PseudoVLUXSEG6EI8_V_M1_M1 + 0U, // PseudoVLUXSEG6EI8_V_M1_M1_MASK + 0U, // PseudoVLUXSEG6EI8_V_MF2_M1 + 0U, // PseudoVLUXSEG6EI8_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG6EI8_V_MF2_MF2 + 0U, // PseudoVLUXSEG6EI8_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG6EI8_V_MF4_M1 + 0U, // PseudoVLUXSEG6EI8_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG6EI8_V_MF4_MF2 + 0U, // PseudoVLUXSEG6EI8_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG6EI8_V_MF4_MF4 + 0U, // PseudoVLUXSEG6EI8_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG6EI8_V_MF8_M1 + 0U, // PseudoVLUXSEG6EI8_V_MF8_M1_MASK + 0U, // PseudoVLUXSEG6EI8_V_MF8_MF2 + 0U, // PseudoVLUXSEG6EI8_V_MF8_MF2_MASK + 0U, // PseudoVLUXSEG6EI8_V_MF8_MF4 + 0U, // PseudoVLUXSEG6EI8_V_MF8_MF4_MASK + 0U, // PseudoVLUXSEG6EI8_V_MF8_MF8 + 0U, // PseudoVLUXSEG6EI8_V_MF8_MF8_MASK + 0U, // PseudoVLUXSEG7EI16_V_M1_M1 + 0U, // PseudoVLUXSEG7EI16_V_M1_M1_MASK + 0U, // PseudoVLUXSEG7EI16_V_M1_MF2 + 0U, // PseudoVLUXSEG7EI16_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG7EI16_V_M2_M1 + 0U, // PseudoVLUXSEG7EI16_V_M2_M1_MASK + 0U, // PseudoVLUXSEG7EI16_V_MF2_M1 + 0U, // PseudoVLUXSEG7EI16_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG7EI16_V_MF2_MF2 + 0U, // PseudoVLUXSEG7EI16_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG7EI16_V_MF2_MF4 + 0U, // PseudoVLUXSEG7EI16_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG7EI16_V_MF4_M1 + 0U, // PseudoVLUXSEG7EI16_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG7EI16_V_MF4_MF2 + 0U, // PseudoVLUXSEG7EI16_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG7EI16_V_MF4_MF4 + 0U, // PseudoVLUXSEG7EI16_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG7EI16_V_MF4_MF8 + 0U, // PseudoVLUXSEG7EI16_V_MF4_MF8_MASK + 0U, // PseudoVLUXSEG7EI32_V_M1_M1 + 0U, // PseudoVLUXSEG7EI32_V_M1_M1_MASK + 0U, // PseudoVLUXSEG7EI32_V_M1_MF2 + 0U, // PseudoVLUXSEG7EI32_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG7EI32_V_M1_MF4 + 0U, // PseudoVLUXSEG7EI32_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG7EI32_V_M2_M1 + 0U, // PseudoVLUXSEG7EI32_V_M2_M1_MASK + 0U, // PseudoVLUXSEG7EI32_V_M2_MF2 + 0U, // PseudoVLUXSEG7EI32_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG7EI32_V_M4_M1 + 0U, // PseudoVLUXSEG7EI32_V_M4_M1_MASK + 0U, // PseudoVLUXSEG7EI32_V_MF2_M1 + 0U, // PseudoVLUXSEG7EI32_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG7EI32_V_MF2_MF2 + 0U, // PseudoVLUXSEG7EI32_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG7EI32_V_MF2_MF4 + 0U, // PseudoVLUXSEG7EI32_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG7EI32_V_MF2_MF8 + 0U, // PseudoVLUXSEG7EI32_V_MF2_MF8_MASK + 0U, // PseudoVLUXSEG7EI64_V_M1_M1 + 0U, // PseudoVLUXSEG7EI64_V_M1_M1_MASK + 0U, // PseudoVLUXSEG7EI64_V_M1_MF2 + 0U, // PseudoVLUXSEG7EI64_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG7EI64_V_M1_MF4 + 0U, // PseudoVLUXSEG7EI64_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG7EI64_V_M1_MF8 + 0U, // PseudoVLUXSEG7EI64_V_M1_MF8_MASK + 0U, // PseudoVLUXSEG7EI64_V_M2_M1 + 0U, // PseudoVLUXSEG7EI64_V_M2_M1_MASK + 0U, // PseudoVLUXSEG7EI64_V_M2_MF2 + 0U, // PseudoVLUXSEG7EI64_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG7EI64_V_M2_MF4 + 0U, // PseudoVLUXSEG7EI64_V_M2_MF4_MASK + 0U, // PseudoVLUXSEG7EI64_V_M4_M1 + 0U, // PseudoVLUXSEG7EI64_V_M4_M1_MASK + 0U, // PseudoVLUXSEG7EI64_V_M4_MF2 + 0U, // PseudoVLUXSEG7EI64_V_M4_MF2_MASK + 0U, // PseudoVLUXSEG7EI64_V_M8_M1 + 0U, // PseudoVLUXSEG7EI64_V_M8_M1_MASK + 0U, // PseudoVLUXSEG7EI8_V_M1_M1 + 0U, // PseudoVLUXSEG7EI8_V_M1_M1_MASK + 0U, // PseudoVLUXSEG7EI8_V_MF2_M1 + 0U, // PseudoVLUXSEG7EI8_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG7EI8_V_MF2_MF2 + 0U, // PseudoVLUXSEG7EI8_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG7EI8_V_MF4_M1 + 0U, // PseudoVLUXSEG7EI8_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG7EI8_V_MF4_MF2 + 0U, // PseudoVLUXSEG7EI8_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG7EI8_V_MF4_MF4 + 0U, // PseudoVLUXSEG7EI8_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG7EI8_V_MF8_M1 + 0U, // PseudoVLUXSEG7EI8_V_MF8_M1_MASK + 0U, // PseudoVLUXSEG7EI8_V_MF8_MF2 + 0U, // PseudoVLUXSEG7EI8_V_MF8_MF2_MASK + 0U, // PseudoVLUXSEG7EI8_V_MF8_MF4 + 0U, // PseudoVLUXSEG7EI8_V_MF8_MF4_MASK + 0U, // PseudoVLUXSEG7EI8_V_MF8_MF8 + 0U, // PseudoVLUXSEG7EI8_V_MF8_MF8_MASK + 0U, // PseudoVLUXSEG8EI16_V_M1_M1 + 0U, // PseudoVLUXSEG8EI16_V_M1_M1_MASK + 0U, // PseudoVLUXSEG8EI16_V_M1_MF2 + 0U, // PseudoVLUXSEG8EI16_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG8EI16_V_M2_M1 + 0U, // PseudoVLUXSEG8EI16_V_M2_M1_MASK + 0U, // PseudoVLUXSEG8EI16_V_MF2_M1 + 0U, // PseudoVLUXSEG8EI16_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG8EI16_V_MF2_MF2 + 0U, // PseudoVLUXSEG8EI16_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG8EI16_V_MF2_MF4 + 0U, // PseudoVLUXSEG8EI16_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG8EI16_V_MF4_M1 + 0U, // PseudoVLUXSEG8EI16_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG8EI16_V_MF4_MF2 + 0U, // PseudoVLUXSEG8EI16_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG8EI16_V_MF4_MF4 + 0U, // PseudoVLUXSEG8EI16_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG8EI16_V_MF4_MF8 + 0U, // PseudoVLUXSEG8EI16_V_MF4_MF8_MASK + 0U, // PseudoVLUXSEG8EI32_V_M1_M1 + 0U, // PseudoVLUXSEG8EI32_V_M1_M1_MASK + 0U, // PseudoVLUXSEG8EI32_V_M1_MF2 + 0U, // PseudoVLUXSEG8EI32_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG8EI32_V_M1_MF4 + 0U, // PseudoVLUXSEG8EI32_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG8EI32_V_M2_M1 + 0U, // PseudoVLUXSEG8EI32_V_M2_M1_MASK + 0U, // PseudoVLUXSEG8EI32_V_M2_MF2 + 0U, // PseudoVLUXSEG8EI32_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG8EI32_V_M4_M1 + 0U, // PseudoVLUXSEG8EI32_V_M4_M1_MASK + 0U, // PseudoVLUXSEG8EI32_V_MF2_M1 + 0U, // PseudoVLUXSEG8EI32_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG8EI32_V_MF2_MF2 + 0U, // PseudoVLUXSEG8EI32_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG8EI32_V_MF2_MF4 + 0U, // PseudoVLUXSEG8EI32_V_MF2_MF4_MASK + 0U, // PseudoVLUXSEG8EI32_V_MF2_MF8 + 0U, // PseudoVLUXSEG8EI32_V_MF2_MF8_MASK + 0U, // PseudoVLUXSEG8EI64_V_M1_M1 + 0U, // PseudoVLUXSEG8EI64_V_M1_M1_MASK + 0U, // PseudoVLUXSEG8EI64_V_M1_MF2 + 0U, // PseudoVLUXSEG8EI64_V_M1_MF2_MASK + 0U, // PseudoVLUXSEG8EI64_V_M1_MF4 + 0U, // PseudoVLUXSEG8EI64_V_M1_MF4_MASK + 0U, // PseudoVLUXSEG8EI64_V_M1_MF8 + 0U, // PseudoVLUXSEG8EI64_V_M1_MF8_MASK + 0U, // PseudoVLUXSEG8EI64_V_M2_M1 + 0U, // PseudoVLUXSEG8EI64_V_M2_M1_MASK + 0U, // PseudoVLUXSEG8EI64_V_M2_MF2 + 0U, // PseudoVLUXSEG8EI64_V_M2_MF2_MASK + 0U, // PseudoVLUXSEG8EI64_V_M2_MF4 + 0U, // PseudoVLUXSEG8EI64_V_M2_MF4_MASK + 0U, // PseudoVLUXSEG8EI64_V_M4_M1 + 0U, // PseudoVLUXSEG8EI64_V_M4_M1_MASK + 0U, // PseudoVLUXSEG8EI64_V_M4_MF2 + 0U, // PseudoVLUXSEG8EI64_V_M4_MF2_MASK + 0U, // PseudoVLUXSEG8EI64_V_M8_M1 + 0U, // PseudoVLUXSEG8EI64_V_M8_M1_MASK + 0U, // PseudoVLUXSEG8EI8_V_M1_M1 + 0U, // PseudoVLUXSEG8EI8_V_M1_M1_MASK + 0U, // PseudoVLUXSEG8EI8_V_MF2_M1 + 0U, // PseudoVLUXSEG8EI8_V_MF2_M1_MASK + 0U, // PseudoVLUXSEG8EI8_V_MF2_MF2 + 0U, // PseudoVLUXSEG8EI8_V_MF2_MF2_MASK + 0U, // PseudoVLUXSEG8EI8_V_MF4_M1 + 0U, // PseudoVLUXSEG8EI8_V_MF4_M1_MASK + 0U, // PseudoVLUXSEG8EI8_V_MF4_MF2 + 0U, // PseudoVLUXSEG8EI8_V_MF4_MF2_MASK + 0U, // PseudoVLUXSEG8EI8_V_MF4_MF4 + 0U, // PseudoVLUXSEG8EI8_V_MF4_MF4_MASK + 0U, // PseudoVLUXSEG8EI8_V_MF8_M1 + 0U, // PseudoVLUXSEG8EI8_V_MF8_M1_MASK + 0U, // PseudoVLUXSEG8EI8_V_MF8_MF2 + 0U, // PseudoVLUXSEG8EI8_V_MF8_MF2_MASK + 0U, // PseudoVLUXSEG8EI8_V_MF8_MF4 + 0U, // PseudoVLUXSEG8EI8_V_MF8_MF4_MASK + 0U, // PseudoVLUXSEG8EI8_V_MF8_MF8 + 0U, // PseudoVLUXSEG8EI8_V_MF8_MF8_MASK + 0U, // PseudoVMACC_VV_M1 + 0U, // PseudoVMACC_VV_M1_MASK + 0U, // PseudoVMACC_VV_M2 + 0U, // PseudoVMACC_VV_M2_MASK + 0U, // PseudoVMACC_VV_M4 + 0U, // PseudoVMACC_VV_M4_MASK + 0U, // PseudoVMACC_VV_M8 + 0U, // PseudoVMACC_VV_M8_MASK + 0U, // PseudoVMACC_VV_MF2 + 0U, // PseudoVMACC_VV_MF2_MASK + 0U, // PseudoVMACC_VV_MF4 + 0U, // PseudoVMACC_VV_MF4_MASK + 0U, // PseudoVMACC_VV_MF8 + 0U, // PseudoVMACC_VV_MF8_MASK + 0U, // PseudoVMACC_VX_M1 + 0U, // PseudoVMACC_VX_M1_MASK + 0U, // PseudoVMACC_VX_M2 + 0U, // PseudoVMACC_VX_M2_MASK + 0U, // PseudoVMACC_VX_M4 + 0U, // PseudoVMACC_VX_M4_MASK + 0U, // PseudoVMACC_VX_M8 + 0U, // PseudoVMACC_VX_M8_MASK + 0U, // PseudoVMACC_VX_MF2 + 0U, // PseudoVMACC_VX_MF2_MASK + 0U, // PseudoVMACC_VX_MF4 + 0U, // PseudoVMACC_VX_MF4_MASK + 0U, // PseudoVMACC_VX_MF8 + 0U, // PseudoVMACC_VX_MF8_MASK + 0U, // PseudoVMADC_VIM_M1 + 0U, // PseudoVMADC_VIM_M2 + 0U, // PseudoVMADC_VIM_M4 + 0U, // PseudoVMADC_VIM_M8 + 0U, // PseudoVMADC_VIM_MF2 + 0U, // PseudoVMADC_VIM_MF4 + 0U, // PseudoVMADC_VIM_MF8 + 0U, // PseudoVMADC_VI_M1 + 0U, // PseudoVMADC_VI_M2 + 0U, // PseudoVMADC_VI_M4 + 0U, // PseudoVMADC_VI_M8 + 0U, // PseudoVMADC_VI_MF2 + 0U, // PseudoVMADC_VI_MF4 + 0U, // PseudoVMADC_VI_MF8 + 0U, // PseudoVMADC_VVM_M1 + 0U, // PseudoVMADC_VVM_M2 + 0U, // PseudoVMADC_VVM_M4 + 0U, // PseudoVMADC_VVM_M8 + 0U, // PseudoVMADC_VVM_MF2 + 0U, // PseudoVMADC_VVM_MF4 + 0U, // PseudoVMADC_VVM_MF8 + 0U, // PseudoVMADC_VV_M1 + 0U, // PseudoVMADC_VV_M2 + 0U, // PseudoVMADC_VV_M4 + 0U, // PseudoVMADC_VV_M8 + 0U, // PseudoVMADC_VV_MF2 + 0U, // PseudoVMADC_VV_MF4 + 0U, // PseudoVMADC_VV_MF8 + 0U, // PseudoVMADC_VXM_M1 + 0U, // PseudoVMADC_VXM_M2 + 0U, // PseudoVMADC_VXM_M4 + 0U, // PseudoVMADC_VXM_M8 + 0U, // PseudoVMADC_VXM_MF2 + 0U, // PseudoVMADC_VXM_MF4 + 0U, // PseudoVMADC_VXM_MF8 + 0U, // PseudoVMADC_VX_M1 + 0U, // PseudoVMADC_VX_M2 + 0U, // PseudoVMADC_VX_M4 + 0U, // PseudoVMADC_VX_M8 + 0U, // PseudoVMADC_VX_MF2 + 0U, // PseudoVMADC_VX_MF4 + 0U, // PseudoVMADC_VX_MF8 + 0U, // PseudoVMADD_VV_M1 + 0U, // PseudoVMADD_VV_M1_MASK + 0U, // PseudoVMADD_VV_M2 + 0U, // PseudoVMADD_VV_M2_MASK + 0U, // PseudoVMADD_VV_M4 + 0U, // PseudoVMADD_VV_M4_MASK + 0U, // PseudoVMADD_VV_M8 + 0U, // PseudoVMADD_VV_M8_MASK + 0U, // PseudoVMADD_VV_MF2 + 0U, // PseudoVMADD_VV_MF2_MASK + 0U, // PseudoVMADD_VV_MF4 + 0U, // PseudoVMADD_VV_MF4_MASK + 0U, // PseudoVMADD_VV_MF8 + 0U, // PseudoVMADD_VV_MF8_MASK + 0U, // PseudoVMADD_VX_M1 + 0U, // PseudoVMADD_VX_M1_MASK + 0U, // PseudoVMADD_VX_M2 + 0U, // PseudoVMADD_VX_M2_MASK + 0U, // PseudoVMADD_VX_M4 + 0U, // PseudoVMADD_VX_M4_MASK + 0U, // PseudoVMADD_VX_M8 + 0U, // PseudoVMADD_VX_M8_MASK + 0U, // PseudoVMADD_VX_MF2 + 0U, // PseudoVMADD_VX_MF2_MASK + 0U, // PseudoVMADD_VX_MF4 + 0U, // PseudoVMADD_VX_MF4_MASK + 0U, // PseudoVMADD_VX_MF8 + 0U, // PseudoVMADD_VX_MF8_MASK + 0U, // PseudoVMANDN_MM_M1 + 0U, // PseudoVMANDN_MM_M2 + 0U, // PseudoVMANDN_MM_M4 + 0U, // PseudoVMANDN_MM_M8 + 0U, // PseudoVMANDN_MM_MF2 + 0U, // PseudoVMANDN_MM_MF4 + 0U, // PseudoVMANDN_MM_MF8 + 0U, // PseudoVMAND_MM_M1 + 0U, // PseudoVMAND_MM_M2 + 0U, // PseudoVMAND_MM_M4 + 0U, // PseudoVMAND_MM_M8 + 0U, // PseudoVMAND_MM_MF2 + 0U, // PseudoVMAND_MM_MF4 + 0U, // PseudoVMAND_MM_MF8 + 0U, // PseudoVMAXU_VV_M1 + 0U, // PseudoVMAXU_VV_M1_MASK + 0U, // PseudoVMAXU_VV_M2 + 0U, // PseudoVMAXU_VV_M2_MASK + 0U, // PseudoVMAXU_VV_M4 + 0U, // PseudoVMAXU_VV_M4_MASK + 0U, // PseudoVMAXU_VV_M8 + 0U, // PseudoVMAXU_VV_M8_MASK + 0U, // PseudoVMAXU_VV_MF2 + 0U, // PseudoVMAXU_VV_MF2_MASK + 0U, // PseudoVMAXU_VV_MF4 + 0U, // PseudoVMAXU_VV_MF4_MASK + 0U, // PseudoVMAXU_VV_MF8 + 0U, // PseudoVMAXU_VV_MF8_MASK + 0U, // PseudoVMAXU_VX_M1 + 0U, // PseudoVMAXU_VX_M1_MASK + 0U, // PseudoVMAXU_VX_M2 + 0U, // PseudoVMAXU_VX_M2_MASK + 0U, // PseudoVMAXU_VX_M4 + 0U, // PseudoVMAXU_VX_M4_MASK + 0U, // PseudoVMAXU_VX_M8 + 0U, // PseudoVMAXU_VX_M8_MASK + 0U, // PseudoVMAXU_VX_MF2 + 0U, // PseudoVMAXU_VX_MF2_MASK + 0U, // PseudoVMAXU_VX_MF4 + 0U, // PseudoVMAXU_VX_MF4_MASK + 0U, // PseudoVMAXU_VX_MF8 + 0U, // PseudoVMAXU_VX_MF8_MASK + 0U, // PseudoVMAX_VV_M1 + 0U, // PseudoVMAX_VV_M1_MASK + 0U, // PseudoVMAX_VV_M2 + 0U, // PseudoVMAX_VV_M2_MASK + 0U, // PseudoVMAX_VV_M4 + 0U, // PseudoVMAX_VV_M4_MASK + 0U, // PseudoVMAX_VV_M8 + 0U, // PseudoVMAX_VV_M8_MASK + 0U, // PseudoVMAX_VV_MF2 + 0U, // PseudoVMAX_VV_MF2_MASK + 0U, // PseudoVMAX_VV_MF4 + 0U, // PseudoVMAX_VV_MF4_MASK + 0U, // PseudoVMAX_VV_MF8 + 0U, // PseudoVMAX_VV_MF8_MASK + 0U, // PseudoVMAX_VX_M1 + 0U, // PseudoVMAX_VX_M1_MASK + 0U, // PseudoVMAX_VX_M2 + 0U, // PseudoVMAX_VX_M2_MASK + 0U, // PseudoVMAX_VX_M4 + 0U, // PseudoVMAX_VX_M4_MASK + 0U, // PseudoVMAX_VX_M8 + 0U, // PseudoVMAX_VX_M8_MASK + 0U, // PseudoVMAX_VX_MF2 + 0U, // PseudoVMAX_VX_MF2_MASK + 0U, // PseudoVMAX_VX_MF4 + 0U, // PseudoVMAX_VX_MF4_MASK + 0U, // PseudoVMAX_VX_MF8 + 0U, // PseudoVMAX_VX_MF8_MASK + 0U, // PseudoVMCLR_M_B1 + 0U, // PseudoVMCLR_M_B16 + 0U, // PseudoVMCLR_M_B2 + 0U, // PseudoVMCLR_M_B32 + 0U, // PseudoVMCLR_M_B4 + 0U, // PseudoVMCLR_M_B64 + 0U, // PseudoVMCLR_M_B8 + 0U, // PseudoVMERGE_VIM_M1 + 0U, // PseudoVMERGE_VIM_M2 + 0U, // PseudoVMERGE_VIM_M4 + 0U, // PseudoVMERGE_VIM_M8 + 0U, // PseudoVMERGE_VIM_MF2 + 0U, // PseudoVMERGE_VIM_MF4 + 0U, // PseudoVMERGE_VIM_MF8 + 0U, // PseudoVMERGE_VVM_M1 + 0U, // PseudoVMERGE_VVM_M2 + 0U, // PseudoVMERGE_VVM_M4 + 0U, // PseudoVMERGE_VVM_M8 + 0U, // PseudoVMERGE_VVM_MF2 + 0U, // PseudoVMERGE_VVM_MF4 + 0U, // PseudoVMERGE_VVM_MF8 + 0U, // PseudoVMERGE_VXM_M1 + 0U, // PseudoVMERGE_VXM_M2 + 0U, // PseudoVMERGE_VXM_M4 + 0U, // PseudoVMERGE_VXM_M8 + 0U, // PseudoVMERGE_VXM_MF2 + 0U, // PseudoVMERGE_VXM_MF4 + 0U, // PseudoVMERGE_VXM_MF8 + 0U, // PseudoVMFEQ_VF16_M1 + 0U, // PseudoVMFEQ_VF16_M1_MASK + 0U, // PseudoVMFEQ_VF16_M2 + 0U, // PseudoVMFEQ_VF16_M2_MASK + 0U, // PseudoVMFEQ_VF16_M4 + 0U, // PseudoVMFEQ_VF16_M4_MASK + 0U, // PseudoVMFEQ_VF16_M8 + 0U, // PseudoVMFEQ_VF16_M8_MASK + 0U, // PseudoVMFEQ_VF16_MF2 + 0U, // PseudoVMFEQ_VF16_MF2_MASK + 0U, // PseudoVMFEQ_VF16_MF4 + 0U, // PseudoVMFEQ_VF16_MF4_MASK + 0U, // PseudoVMFEQ_VF16_MF8 + 0U, // PseudoVMFEQ_VF16_MF8_MASK + 0U, // PseudoVMFEQ_VF32_M1 + 0U, // PseudoVMFEQ_VF32_M1_MASK + 0U, // PseudoVMFEQ_VF32_M2 + 0U, // PseudoVMFEQ_VF32_M2_MASK + 0U, // PseudoVMFEQ_VF32_M4 + 0U, // PseudoVMFEQ_VF32_M4_MASK + 0U, // PseudoVMFEQ_VF32_M8 + 0U, // PseudoVMFEQ_VF32_M8_MASK + 0U, // PseudoVMFEQ_VF32_MF2 + 0U, // PseudoVMFEQ_VF32_MF2_MASK + 0U, // PseudoVMFEQ_VF32_MF4 + 0U, // PseudoVMFEQ_VF32_MF4_MASK + 0U, // PseudoVMFEQ_VF32_MF8 + 0U, // PseudoVMFEQ_VF32_MF8_MASK + 0U, // PseudoVMFEQ_VF64_M1 + 0U, // PseudoVMFEQ_VF64_M1_MASK + 0U, // PseudoVMFEQ_VF64_M2 + 0U, // PseudoVMFEQ_VF64_M2_MASK + 0U, // PseudoVMFEQ_VF64_M4 + 0U, // PseudoVMFEQ_VF64_M4_MASK + 0U, // PseudoVMFEQ_VF64_M8 + 0U, // PseudoVMFEQ_VF64_M8_MASK + 0U, // PseudoVMFEQ_VF64_MF2 + 0U, // PseudoVMFEQ_VF64_MF2_MASK + 0U, // PseudoVMFEQ_VF64_MF4 + 0U, // PseudoVMFEQ_VF64_MF4_MASK + 0U, // PseudoVMFEQ_VF64_MF8 + 0U, // PseudoVMFEQ_VF64_MF8_MASK + 0U, // PseudoVMFEQ_VV_M1 + 0U, // PseudoVMFEQ_VV_M1_MASK + 0U, // PseudoVMFEQ_VV_M2 + 0U, // PseudoVMFEQ_VV_M2_MASK + 0U, // PseudoVMFEQ_VV_M4 + 0U, // PseudoVMFEQ_VV_M4_MASK + 0U, // PseudoVMFEQ_VV_M8 + 0U, // PseudoVMFEQ_VV_M8_MASK + 0U, // PseudoVMFEQ_VV_MF2 + 0U, // PseudoVMFEQ_VV_MF2_MASK + 0U, // PseudoVMFEQ_VV_MF4 + 0U, // PseudoVMFEQ_VV_MF4_MASK + 0U, // PseudoVMFEQ_VV_MF8 + 0U, // PseudoVMFEQ_VV_MF8_MASK + 0U, // PseudoVMFGE_VF16_M1 + 0U, // PseudoVMFGE_VF16_M1_MASK + 0U, // PseudoVMFGE_VF16_M2 + 0U, // PseudoVMFGE_VF16_M2_MASK + 0U, // PseudoVMFGE_VF16_M4 + 0U, // PseudoVMFGE_VF16_M4_MASK + 0U, // PseudoVMFGE_VF16_M8 + 0U, // PseudoVMFGE_VF16_M8_MASK + 0U, // PseudoVMFGE_VF16_MF2 + 0U, // PseudoVMFGE_VF16_MF2_MASK + 0U, // PseudoVMFGE_VF16_MF4 + 0U, // PseudoVMFGE_VF16_MF4_MASK + 0U, // PseudoVMFGE_VF16_MF8 + 0U, // PseudoVMFGE_VF16_MF8_MASK + 0U, // PseudoVMFGE_VF32_M1 + 0U, // PseudoVMFGE_VF32_M1_MASK + 0U, // PseudoVMFGE_VF32_M2 + 0U, // PseudoVMFGE_VF32_M2_MASK + 0U, // PseudoVMFGE_VF32_M4 + 0U, // PseudoVMFGE_VF32_M4_MASK + 0U, // PseudoVMFGE_VF32_M8 + 0U, // PseudoVMFGE_VF32_M8_MASK + 0U, // PseudoVMFGE_VF32_MF2 + 0U, // PseudoVMFGE_VF32_MF2_MASK + 0U, // PseudoVMFGE_VF32_MF4 + 0U, // PseudoVMFGE_VF32_MF4_MASK + 0U, // PseudoVMFGE_VF32_MF8 + 0U, // PseudoVMFGE_VF32_MF8_MASK + 0U, // PseudoVMFGE_VF64_M1 + 0U, // PseudoVMFGE_VF64_M1_MASK + 0U, // PseudoVMFGE_VF64_M2 + 0U, // PseudoVMFGE_VF64_M2_MASK + 0U, // PseudoVMFGE_VF64_M4 + 0U, // PseudoVMFGE_VF64_M4_MASK + 0U, // PseudoVMFGE_VF64_M8 + 0U, // PseudoVMFGE_VF64_M8_MASK + 0U, // PseudoVMFGE_VF64_MF2 + 0U, // PseudoVMFGE_VF64_MF2_MASK + 0U, // PseudoVMFGE_VF64_MF4 + 0U, // PseudoVMFGE_VF64_MF4_MASK + 0U, // PseudoVMFGE_VF64_MF8 + 0U, // PseudoVMFGE_VF64_MF8_MASK + 0U, // PseudoVMFGT_VF16_M1 + 0U, // PseudoVMFGT_VF16_M1_MASK + 0U, // PseudoVMFGT_VF16_M2 + 0U, // PseudoVMFGT_VF16_M2_MASK + 0U, // PseudoVMFGT_VF16_M4 + 0U, // PseudoVMFGT_VF16_M4_MASK + 0U, // PseudoVMFGT_VF16_M8 + 0U, // PseudoVMFGT_VF16_M8_MASK + 0U, // PseudoVMFGT_VF16_MF2 + 0U, // PseudoVMFGT_VF16_MF2_MASK + 0U, // PseudoVMFGT_VF16_MF4 + 0U, // PseudoVMFGT_VF16_MF4_MASK + 0U, // PseudoVMFGT_VF16_MF8 + 0U, // PseudoVMFGT_VF16_MF8_MASK + 0U, // PseudoVMFGT_VF32_M1 + 0U, // PseudoVMFGT_VF32_M1_MASK + 0U, // PseudoVMFGT_VF32_M2 + 0U, // PseudoVMFGT_VF32_M2_MASK + 0U, // PseudoVMFGT_VF32_M4 + 0U, // PseudoVMFGT_VF32_M4_MASK + 0U, // PseudoVMFGT_VF32_M8 + 0U, // PseudoVMFGT_VF32_M8_MASK + 0U, // PseudoVMFGT_VF32_MF2 + 0U, // PseudoVMFGT_VF32_MF2_MASK + 0U, // PseudoVMFGT_VF32_MF4 + 0U, // PseudoVMFGT_VF32_MF4_MASK + 0U, // PseudoVMFGT_VF32_MF8 + 0U, // PseudoVMFGT_VF32_MF8_MASK + 0U, // PseudoVMFGT_VF64_M1 + 0U, // PseudoVMFGT_VF64_M1_MASK + 0U, // PseudoVMFGT_VF64_M2 + 0U, // PseudoVMFGT_VF64_M2_MASK + 0U, // PseudoVMFGT_VF64_M4 + 0U, // PseudoVMFGT_VF64_M4_MASK + 0U, // PseudoVMFGT_VF64_M8 + 0U, // PseudoVMFGT_VF64_M8_MASK + 0U, // PseudoVMFGT_VF64_MF2 + 0U, // PseudoVMFGT_VF64_MF2_MASK + 0U, // PseudoVMFGT_VF64_MF4 + 0U, // PseudoVMFGT_VF64_MF4_MASK + 0U, // PseudoVMFGT_VF64_MF8 + 0U, // PseudoVMFGT_VF64_MF8_MASK + 0U, // PseudoVMFLE_VF16_M1 + 0U, // PseudoVMFLE_VF16_M1_MASK + 0U, // PseudoVMFLE_VF16_M2 + 0U, // PseudoVMFLE_VF16_M2_MASK + 0U, // PseudoVMFLE_VF16_M4 + 0U, // PseudoVMFLE_VF16_M4_MASK + 0U, // PseudoVMFLE_VF16_M8 + 0U, // PseudoVMFLE_VF16_M8_MASK + 0U, // PseudoVMFLE_VF16_MF2 + 0U, // PseudoVMFLE_VF16_MF2_MASK + 0U, // PseudoVMFLE_VF16_MF4 + 0U, // PseudoVMFLE_VF16_MF4_MASK + 0U, // PseudoVMFLE_VF16_MF8 + 0U, // PseudoVMFLE_VF16_MF8_MASK + 0U, // PseudoVMFLE_VF32_M1 + 0U, // PseudoVMFLE_VF32_M1_MASK + 0U, // PseudoVMFLE_VF32_M2 + 0U, // PseudoVMFLE_VF32_M2_MASK + 0U, // PseudoVMFLE_VF32_M4 + 0U, // PseudoVMFLE_VF32_M4_MASK + 0U, // PseudoVMFLE_VF32_M8 + 0U, // PseudoVMFLE_VF32_M8_MASK + 0U, // PseudoVMFLE_VF32_MF2 + 0U, // PseudoVMFLE_VF32_MF2_MASK + 0U, // PseudoVMFLE_VF32_MF4 + 0U, // PseudoVMFLE_VF32_MF4_MASK + 0U, // PseudoVMFLE_VF32_MF8 + 0U, // PseudoVMFLE_VF32_MF8_MASK + 0U, // PseudoVMFLE_VF64_M1 + 0U, // PseudoVMFLE_VF64_M1_MASK + 0U, // PseudoVMFLE_VF64_M2 + 0U, // PseudoVMFLE_VF64_M2_MASK + 0U, // PseudoVMFLE_VF64_M4 + 0U, // PseudoVMFLE_VF64_M4_MASK + 0U, // PseudoVMFLE_VF64_M8 + 0U, // PseudoVMFLE_VF64_M8_MASK + 0U, // PseudoVMFLE_VF64_MF2 + 0U, // PseudoVMFLE_VF64_MF2_MASK + 0U, // PseudoVMFLE_VF64_MF4 + 0U, // PseudoVMFLE_VF64_MF4_MASK + 0U, // PseudoVMFLE_VF64_MF8 + 0U, // PseudoVMFLE_VF64_MF8_MASK + 0U, // PseudoVMFLE_VV_M1 + 0U, // PseudoVMFLE_VV_M1_MASK + 0U, // PseudoVMFLE_VV_M2 + 0U, // PseudoVMFLE_VV_M2_MASK + 0U, // PseudoVMFLE_VV_M4 + 0U, // PseudoVMFLE_VV_M4_MASK + 0U, // PseudoVMFLE_VV_M8 + 0U, // PseudoVMFLE_VV_M8_MASK + 0U, // PseudoVMFLE_VV_MF2 + 0U, // PseudoVMFLE_VV_MF2_MASK + 0U, // PseudoVMFLE_VV_MF4 + 0U, // PseudoVMFLE_VV_MF4_MASK + 0U, // PseudoVMFLE_VV_MF8 + 0U, // PseudoVMFLE_VV_MF8_MASK + 0U, // PseudoVMFLT_VF16_M1 + 0U, // PseudoVMFLT_VF16_M1_MASK + 0U, // PseudoVMFLT_VF16_M2 + 0U, // PseudoVMFLT_VF16_M2_MASK + 0U, // PseudoVMFLT_VF16_M4 + 0U, // PseudoVMFLT_VF16_M4_MASK + 0U, // PseudoVMFLT_VF16_M8 + 0U, // PseudoVMFLT_VF16_M8_MASK + 0U, // PseudoVMFLT_VF16_MF2 + 0U, // PseudoVMFLT_VF16_MF2_MASK + 0U, // PseudoVMFLT_VF16_MF4 + 0U, // PseudoVMFLT_VF16_MF4_MASK + 0U, // PseudoVMFLT_VF16_MF8 + 0U, // PseudoVMFLT_VF16_MF8_MASK + 0U, // PseudoVMFLT_VF32_M1 + 0U, // PseudoVMFLT_VF32_M1_MASK + 0U, // PseudoVMFLT_VF32_M2 + 0U, // PseudoVMFLT_VF32_M2_MASK + 0U, // PseudoVMFLT_VF32_M4 + 0U, // PseudoVMFLT_VF32_M4_MASK + 0U, // PseudoVMFLT_VF32_M8 + 0U, // PseudoVMFLT_VF32_M8_MASK + 0U, // PseudoVMFLT_VF32_MF2 + 0U, // PseudoVMFLT_VF32_MF2_MASK + 0U, // PseudoVMFLT_VF32_MF4 + 0U, // PseudoVMFLT_VF32_MF4_MASK + 0U, // PseudoVMFLT_VF32_MF8 + 0U, // PseudoVMFLT_VF32_MF8_MASK + 0U, // PseudoVMFLT_VF64_M1 + 0U, // PseudoVMFLT_VF64_M1_MASK + 0U, // PseudoVMFLT_VF64_M2 + 0U, // PseudoVMFLT_VF64_M2_MASK + 0U, // PseudoVMFLT_VF64_M4 + 0U, // PseudoVMFLT_VF64_M4_MASK + 0U, // PseudoVMFLT_VF64_M8 + 0U, // PseudoVMFLT_VF64_M8_MASK + 0U, // PseudoVMFLT_VF64_MF2 + 0U, // PseudoVMFLT_VF64_MF2_MASK + 0U, // PseudoVMFLT_VF64_MF4 + 0U, // PseudoVMFLT_VF64_MF4_MASK + 0U, // PseudoVMFLT_VF64_MF8 + 0U, // PseudoVMFLT_VF64_MF8_MASK + 0U, // PseudoVMFLT_VV_M1 + 0U, // PseudoVMFLT_VV_M1_MASK + 0U, // PseudoVMFLT_VV_M2 + 0U, // PseudoVMFLT_VV_M2_MASK + 0U, // PseudoVMFLT_VV_M4 + 0U, // PseudoVMFLT_VV_M4_MASK + 0U, // PseudoVMFLT_VV_M8 + 0U, // PseudoVMFLT_VV_M8_MASK + 0U, // PseudoVMFLT_VV_MF2 + 0U, // PseudoVMFLT_VV_MF2_MASK + 0U, // PseudoVMFLT_VV_MF4 + 0U, // PseudoVMFLT_VV_MF4_MASK + 0U, // PseudoVMFLT_VV_MF8 + 0U, // PseudoVMFLT_VV_MF8_MASK + 0U, // PseudoVMFNE_VF16_M1 + 0U, // PseudoVMFNE_VF16_M1_MASK + 0U, // PseudoVMFNE_VF16_M2 + 0U, // PseudoVMFNE_VF16_M2_MASK + 0U, // PseudoVMFNE_VF16_M4 + 0U, // PseudoVMFNE_VF16_M4_MASK + 0U, // PseudoVMFNE_VF16_M8 + 0U, // PseudoVMFNE_VF16_M8_MASK + 0U, // PseudoVMFNE_VF16_MF2 + 0U, // PseudoVMFNE_VF16_MF2_MASK + 0U, // PseudoVMFNE_VF16_MF4 + 0U, // PseudoVMFNE_VF16_MF4_MASK + 0U, // PseudoVMFNE_VF16_MF8 + 0U, // PseudoVMFNE_VF16_MF8_MASK + 0U, // PseudoVMFNE_VF32_M1 + 0U, // PseudoVMFNE_VF32_M1_MASK + 0U, // PseudoVMFNE_VF32_M2 + 0U, // PseudoVMFNE_VF32_M2_MASK + 0U, // PseudoVMFNE_VF32_M4 + 0U, // PseudoVMFNE_VF32_M4_MASK + 0U, // PseudoVMFNE_VF32_M8 + 0U, // PseudoVMFNE_VF32_M8_MASK + 0U, // PseudoVMFNE_VF32_MF2 + 0U, // PseudoVMFNE_VF32_MF2_MASK + 0U, // PseudoVMFNE_VF32_MF4 + 0U, // PseudoVMFNE_VF32_MF4_MASK + 0U, // PseudoVMFNE_VF32_MF8 + 0U, // PseudoVMFNE_VF32_MF8_MASK + 0U, // PseudoVMFNE_VF64_M1 + 0U, // PseudoVMFNE_VF64_M1_MASK + 0U, // PseudoVMFNE_VF64_M2 + 0U, // PseudoVMFNE_VF64_M2_MASK + 0U, // PseudoVMFNE_VF64_M4 + 0U, // PseudoVMFNE_VF64_M4_MASK + 0U, // PseudoVMFNE_VF64_M8 + 0U, // PseudoVMFNE_VF64_M8_MASK + 0U, // PseudoVMFNE_VF64_MF2 + 0U, // PseudoVMFNE_VF64_MF2_MASK + 0U, // PseudoVMFNE_VF64_MF4 + 0U, // PseudoVMFNE_VF64_MF4_MASK + 0U, // PseudoVMFNE_VF64_MF8 + 0U, // PseudoVMFNE_VF64_MF8_MASK + 0U, // PseudoVMFNE_VV_M1 + 0U, // PseudoVMFNE_VV_M1_MASK + 0U, // PseudoVMFNE_VV_M2 + 0U, // PseudoVMFNE_VV_M2_MASK + 0U, // PseudoVMFNE_VV_M4 + 0U, // PseudoVMFNE_VV_M4_MASK + 0U, // PseudoVMFNE_VV_M8 + 0U, // PseudoVMFNE_VV_M8_MASK + 0U, // PseudoVMFNE_VV_MF2 + 0U, // PseudoVMFNE_VV_MF2_MASK + 0U, // PseudoVMFNE_VV_MF4 + 0U, // PseudoVMFNE_VV_MF4_MASK + 0U, // PseudoVMFNE_VV_MF8 + 0U, // PseudoVMFNE_VV_MF8_MASK + 0U, // PseudoVMINU_VV_M1 + 0U, // PseudoVMINU_VV_M1_MASK + 0U, // PseudoVMINU_VV_M2 + 0U, // PseudoVMINU_VV_M2_MASK + 0U, // PseudoVMINU_VV_M4 + 0U, // PseudoVMINU_VV_M4_MASK + 0U, // PseudoVMINU_VV_M8 + 0U, // PseudoVMINU_VV_M8_MASK + 0U, // PseudoVMINU_VV_MF2 + 0U, // PseudoVMINU_VV_MF2_MASK + 0U, // PseudoVMINU_VV_MF4 + 0U, // PseudoVMINU_VV_MF4_MASK + 0U, // PseudoVMINU_VV_MF8 + 0U, // PseudoVMINU_VV_MF8_MASK + 0U, // PseudoVMINU_VX_M1 + 0U, // PseudoVMINU_VX_M1_MASK + 0U, // PseudoVMINU_VX_M2 + 0U, // PseudoVMINU_VX_M2_MASK + 0U, // PseudoVMINU_VX_M4 + 0U, // PseudoVMINU_VX_M4_MASK + 0U, // PseudoVMINU_VX_M8 + 0U, // PseudoVMINU_VX_M8_MASK + 0U, // PseudoVMINU_VX_MF2 + 0U, // PseudoVMINU_VX_MF2_MASK + 0U, // PseudoVMINU_VX_MF4 + 0U, // PseudoVMINU_VX_MF4_MASK + 0U, // PseudoVMINU_VX_MF8 + 0U, // PseudoVMINU_VX_MF8_MASK + 0U, // PseudoVMIN_VV_M1 + 0U, // PseudoVMIN_VV_M1_MASK + 0U, // PseudoVMIN_VV_M2 + 0U, // PseudoVMIN_VV_M2_MASK + 0U, // PseudoVMIN_VV_M4 + 0U, // PseudoVMIN_VV_M4_MASK + 0U, // PseudoVMIN_VV_M8 + 0U, // PseudoVMIN_VV_M8_MASK + 0U, // PseudoVMIN_VV_MF2 + 0U, // PseudoVMIN_VV_MF2_MASK + 0U, // PseudoVMIN_VV_MF4 + 0U, // PseudoVMIN_VV_MF4_MASK + 0U, // PseudoVMIN_VV_MF8 + 0U, // PseudoVMIN_VV_MF8_MASK + 0U, // PseudoVMIN_VX_M1 + 0U, // PseudoVMIN_VX_M1_MASK + 0U, // PseudoVMIN_VX_M2 + 0U, // PseudoVMIN_VX_M2_MASK + 0U, // PseudoVMIN_VX_M4 + 0U, // PseudoVMIN_VX_M4_MASK + 0U, // PseudoVMIN_VX_M8 + 0U, // PseudoVMIN_VX_M8_MASK + 0U, // PseudoVMIN_VX_MF2 + 0U, // PseudoVMIN_VX_MF2_MASK + 0U, // PseudoVMIN_VX_MF4 + 0U, // PseudoVMIN_VX_MF4_MASK + 0U, // PseudoVMIN_VX_MF8 + 0U, // PseudoVMIN_VX_MF8_MASK + 0U, // PseudoVMNAND_MM_M1 + 0U, // PseudoVMNAND_MM_M2 + 0U, // PseudoVMNAND_MM_M4 + 0U, // PseudoVMNAND_MM_M8 + 0U, // PseudoVMNAND_MM_MF2 + 0U, // PseudoVMNAND_MM_MF4 + 0U, // PseudoVMNAND_MM_MF8 + 0U, // PseudoVMNOR_MM_M1 + 0U, // PseudoVMNOR_MM_M2 + 0U, // PseudoVMNOR_MM_M4 + 0U, // PseudoVMNOR_MM_M8 + 0U, // PseudoVMNOR_MM_MF2 + 0U, // PseudoVMNOR_MM_MF4 + 0U, // PseudoVMNOR_MM_MF8 + 0U, // PseudoVMORN_MM_M1 + 0U, // PseudoVMORN_MM_M2 + 0U, // PseudoVMORN_MM_M4 + 0U, // PseudoVMORN_MM_M8 + 0U, // PseudoVMORN_MM_MF2 + 0U, // PseudoVMORN_MM_MF4 + 0U, // PseudoVMORN_MM_MF8 + 0U, // PseudoVMOR_MM_M1 + 0U, // PseudoVMOR_MM_M2 + 0U, // PseudoVMOR_MM_M4 + 0U, // PseudoVMOR_MM_M8 + 0U, // PseudoVMOR_MM_MF2 + 0U, // PseudoVMOR_MM_MF4 + 0U, // PseudoVMOR_MM_MF8 + 0U, // PseudoVMSBC_VVM_M1 + 0U, // PseudoVMSBC_VVM_M2 + 0U, // PseudoVMSBC_VVM_M4 + 0U, // PseudoVMSBC_VVM_M8 + 0U, // PseudoVMSBC_VVM_MF2 + 0U, // PseudoVMSBC_VVM_MF4 + 0U, // PseudoVMSBC_VVM_MF8 + 0U, // PseudoVMSBC_VV_M1 + 0U, // PseudoVMSBC_VV_M2 + 0U, // PseudoVMSBC_VV_M4 + 0U, // PseudoVMSBC_VV_M8 + 0U, // PseudoVMSBC_VV_MF2 + 0U, // PseudoVMSBC_VV_MF4 + 0U, // PseudoVMSBC_VV_MF8 + 0U, // PseudoVMSBC_VXM_M1 + 0U, // PseudoVMSBC_VXM_M2 + 0U, // PseudoVMSBC_VXM_M4 + 0U, // PseudoVMSBC_VXM_M8 + 0U, // PseudoVMSBC_VXM_MF2 + 0U, // PseudoVMSBC_VXM_MF4 + 0U, // PseudoVMSBC_VXM_MF8 + 0U, // PseudoVMSBC_VX_M1 + 0U, // PseudoVMSBC_VX_M2 + 0U, // PseudoVMSBC_VX_M4 + 0U, // PseudoVMSBC_VX_M8 + 0U, // PseudoVMSBC_VX_MF2 + 0U, // PseudoVMSBC_VX_MF4 + 0U, // PseudoVMSBC_VX_MF8 + 0U, // PseudoVMSBF_M_B1 + 0U, // PseudoVMSBF_M_B16 + 0U, // PseudoVMSBF_M_B16_MASK + 0U, // PseudoVMSBF_M_B1_MASK + 0U, // PseudoVMSBF_M_B2 + 0U, // PseudoVMSBF_M_B2_MASK + 0U, // PseudoVMSBF_M_B32 + 0U, // PseudoVMSBF_M_B32_MASK + 0U, // PseudoVMSBF_M_B4 + 0U, // PseudoVMSBF_M_B4_MASK + 0U, // PseudoVMSBF_M_B64 + 0U, // PseudoVMSBF_M_B64_MASK + 0U, // PseudoVMSBF_M_B8 + 0U, // PseudoVMSBF_M_B8_MASK + 0U, // PseudoVMSEQ_VI_M1 + 0U, // PseudoVMSEQ_VI_M1_MASK + 0U, // PseudoVMSEQ_VI_M2 + 0U, // PseudoVMSEQ_VI_M2_MASK + 0U, // PseudoVMSEQ_VI_M4 + 0U, // PseudoVMSEQ_VI_M4_MASK + 0U, // PseudoVMSEQ_VI_M8 + 0U, // PseudoVMSEQ_VI_M8_MASK + 0U, // PseudoVMSEQ_VI_MF2 + 0U, // PseudoVMSEQ_VI_MF2_MASK + 0U, // PseudoVMSEQ_VI_MF4 + 0U, // PseudoVMSEQ_VI_MF4_MASK + 0U, // PseudoVMSEQ_VI_MF8 + 0U, // PseudoVMSEQ_VI_MF8_MASK + 0U, // PseudoVMSEQ_VV_M1 + 0U, // PseudoVMSEQ_VV_M1_MASK + 0U, // PseudoVMSEQ_VV_M2 + 0U, // PseudoVMSEQ_VV_M2_MASK + 0U, // PseudoVMSEQ_VV_M4 + 0U, // PseudoVMSEQ_VV_M4_MASK + 0U, // PseudoVMSEQ_VV_M8 + 0U, // PseudoVMSEQ_VV_M8_MASK + 0U, // PseudoVMSEQ_VV_MF2 + 0U, // PseudoVMSEQ_VV_MF2_MASK + 0U, // PseudoVMSEQ_VV_MF4 + 0U, // PseudoVMSEQ_VV_MF4_MASK + 0U, // PseudoVMSEQ_VV_MF8 + 0U, // PseudoVMSEQ_VV_MF8_MASK + 0U, // PseudoVMSEQ_VX_M1 + 0U, // PseudoVMSEQ_VX_M1_MASK + 0U, // PseudoVMSEQ_VX_M2 + 0U, // PseudoVMSEQ_VX_M2_MASK + 0U, // PseudoVMSEQ_VX_M4 + 0U, // PseudoVMSEQ_VX_M4_MASK + 0U, // PseudoVMSEQ_VX_M8 + 0U, // PseudoVMSEQ_VX_M8_MASK + 0U, // PseudoVMSEQ_VX_MF2 + 0U, // PseudoVMSEQ_VX_MF2_MASK + 0U, // PseudoVMSEQ_VX_MF4 + 0U, // PseudoVMSEQ_VX_MF4_MASK + 0U, // PseudoVMSEQ_VX_MF8 + 0U, // PseudoVMSEQ_VX_MF8_MASK + 0U, // PseudoVMSET_M_B1 + 0U, // PseudoVMSET_M_B16 + 0U, // PseudoVMSET_M_B2 + 0U, // PseudoVMSET_M_B32 + 0U, // PseudoVMSET_M_B4 + 0U, // PseudoVMSET_M_B64 + 0U, // PseudoVMSET_M_B8 + 0U, // PseudoVMSGEU_VI + 0U, // PseudoVMSGEU_VX + 0U, // PseudoVMSGEU_VX_M + 1U, // PseudoVMSGEU_VX_M_T + 0U, // PseudoVMSGE_VI + 0U, // PseudoVMSGE_VX + 0U, // PseudoVMSGE_VX_M + 1U, // PseudoVMSGE_VX_M_T + 0U, // PseudoVMSGTU_VI_M1 + 0U, // PseudoVMSGTU_VI_M1_MASK + 0U, // PseudoVMSGTU_VI_M2 + 0U, // PseudoVMSGTU_VI_M2_MASK + 0U, // PseudoVMSGTU_VI_M4 + 0U, // PseudoVMSGTU_VI_M4_MASK + 0U, // PseudoVMSGTU_VI_M8 + 0U, // PseudoVMSGTU_VI_M8_MASK + 0U, // PseudoVMSGTU_VI_MF2 + 0U, // PseudoVMSGTU_VI_MF2_MASK + 0U, // PseudoVMSGTU_VI_MF4 + 0U, // PseudoVMSGTU_VI_MF4_MASK + 0U, // PseudoVMSGTU_VI_MF8 + 0U, // PseudoVMSGTU_VI_MF8_MASK + 0U, // PseudoVMSGTU_VX_M1 + 0U, // PseudoVMSGTU_VX_M1_MASK + 0U, // PseudoVMSGTU_VX_M2 + 0U, // PseudoVMSGTU_VX_M2_MASK + 0U, // PseudoVMSGTU_VX_M4 + 0U, // PseudoVMSGTU_VX_M4_MASK + 0U, // PseudoVMSGTU_VX_M8 + 0U, // PseudoVMSGTU_VX_M8_MASK + 0U, // PseudoVMSGTU_VX_MF2 + 0U, // PseudoVMSGTU_VX_MF2_MASK + 0U, // PseudoVMSGTU_VX_MF4 + 0U, // PseudoVMSGTU_VX_MF4_MASK + 0U, // PseudoVMSGTU_VX_MF8 + 0U, // PseudoVMSGTU_VX_MF8_MASK + 0U, // PseudoVMSGT_VI_M1 + 0U, // PseudoVMSGT_VI_M1_MASK + 0U, // PseudoVMSGT_VI_M2 + 0U, // PseudoVMSGT_VI_M2_MASK + 0U, // PseudoVMSGT_VI_M4 + 0U, // PseudoVMSGT_VI_M4_MASK + 0U, // PseudoVMSGT_VI_M8 + 0U, // PseudoVMSGT_VI_M8_MASK + 0U, // PseudoVMSGT_VI_MF2 + 0U, // PseudoVMSGT_VI_MF2_MASK + 0U, // PseudoVMSGT_VI_MF4 + 0U, // PseudoVMSGT_VI_MF4_MASK + 0U, // PseudoVMSGT_VI_MF8 + 0U, // PseudoVMSGT_VI_MF8_MASK + 0U, // PseudoVMSGT_VX_M1 + 0U, // PseudoVMSGT_VX_M1_MASK + 0U, // PseudoVMSGT_VX_M2 + 0U, // PseudoVMSGT_VX_M2_MASK + 0U, // PseudoVMSGT_VX_M4 + 0U, // PseudoVMSGT_VX_M4_MASK + 0U, // PseudoVMSGT_VX_M8 + 0U, // PseudoVMSGT_VX_M8_MASK + 0U, // PseudoVMSGT_VX_MF2 + 0U, // PseudoVMSGT_VX_MF2_MASK + 0U, // PseudoVMSGT_VX_MF4 + 0U, // PseudoVMSGT_VX_MF4_MASK + 0U, // PseudoVMSGT_VX_MF8 + 0U, // PseudoVMSGT_VX_MF8_MASK + 0U, // PseudoVMSIF_M_B1 + 0U, // PseudoVMSIF_M_B16 + 0U, // PseudoVMSIF_M_B16_MASK + 0U, // PseudoVMSIF_M_B1_MASK + 0U, // PseudoVMSIF_M_B2 + 0U, // PseudoVMSIF_M_B2_MASK + 0U, // PseudoVMSIF_M_B32 + 0U, // PseudoVMSIF_M_B32_MASK + 0U, // PseudoVMSIF_M_B4 + 0U, // PseudoVMSIF_M_B4_MASK + 0U, // PseudoVMSIF_M_B64 + 0U, // PseudoVMSIF_M_B64_MASK + 0U, // PseudoVMSIF_M_B8 + 0U, // PseudoVMSIF_M_B8_MASK + 0U, // PseudoVMSLEU_VI_M1 + 0U, // PseudoVMSLEU_VI_M1_MASK + 0U, // PseudoVMSLEU_VI_M2 + 0U, // PseudoVMSLEU_VI_M2_MASK + 0U, // PseudoVMSLEU_VI_M4 + 0U, // PseudoVMSLEU_VI_M4_MASK + 0U, // PseudoVMSLEU_VI_M8 + 0U, // PseudoVMSLEU_VI_M8_MASK + 0U, // PseudoVMSLEU_VI_MF2 + 0U, // PseudoVMSLEU_VI_MF2_MASK + 0U, // PseudoVMSLEU_VI_MF4 + 0U, // PseudoVMSLEU_VI_MF4_MASK + 0U, // PseudoVMSLEU_VI_MF8 + 0U, // PseudoVMSLEU_VI_MF8_MASK + 0U, // PseudoVMSLEU_VV_M1 + 0U, // PseudoVMSLEU_VV_M1_MASK + 0U, // PseudoVMSLEU_VV_M2 + 0U, // PseudoVMSLEU_VV_M2_MASK + 0U, // PseudoVMSLEU_VV_M4 + 0U, // PseudoVMSLEU_VV_M4_MASK + 0U, // PseudoVMSLEU_VV_M8 + 0U, // PseudoVMSLEU_VV_M8_MASK + 0U, // PseudoVMSLEU_VV_MF2 + 0U, // PseudoVMSLEU_VV_MF2_MASK + 0U, // PseudoVMSLEU_VV_MF4 + 0U, // PseudoVMSLEU_VV_MF4_MASK + 0U, // PseudoVMSLEU_VV_MF8 + 0U, // PseudoVMSLEU_VV_MF8_MASK + 0U, // PseudoVMSLEU_VX_M1 + 0U, // PseudoVMSLEU_VX_M1_MASK + 0U, // PseudoVMSLEU_VX_M2 + 0U, // PseudoVMSLEU_VX_M2_MASK + 0U, // PseudoVMSLEU_VX_M4 + 0U, // PseudoVMSLEU_VX_M4_MASK + 0U, // PseudoVMSLEU_VX_M8 + 0U, // PseudoVMSLEU_VX_M8_MASK + 0U, // PseudoVMSLEU_VX_MF2 + 0U, // PseudoVMSLEU_VX_MF2_MASK + 0U, // PseudoVMSLEU_VX_MF4 + 0U, // PseudoVMSLEU_VX_MF4_MASK + 0U, // PseudoVMSLEU_VX_MF8 + 0U, // PseudoVMSLEU_VX_MF8_MASK + 0U, // PseudoVMSLE_VI_M1 + 0U, // PseudoVMSLE_VI_M1_MASK + 0U, // PseudoVMSLE_VI_M2 + 0U, // PseudoVMSLE_VI_M2_MASK + 0U, // PseudoVMSLE_VI_M4 + 0U, // PseudoVMSLE_VI_M4_MASK + 0U, // PseudoVMSLE_VI_M8 + 0U, // PseudoVMSLE_VI_M8_MASK + 0U, // PseudoVMSLE_VI_MF2 + 0U, // PseudoVMSLE_VI_MF2_MASK + 0U, // PseudoVMSLE_VI_MF4 + 0U, // PseudoVMSLE_VI_MF4_MASK + 0U, // PseudoVMSLE_VI_MF8 + 0U, // PseudoVMSLE_VI_MF8_MASK + 0U, // PseudoVMSLE_VV_M1 + 0U, // PseudoVMSLE_VV_M1_MASK + 0U, // PseudoVMSLE_VV_M2 + 0U, // PseudoVMSLE_VV_M2_MASK + 0U, // PseudoVMSLE_VV_M4 + 0U, // PseudoVMSLE_VV_M4_MASK + 0U, // PseudoVMSLE_VV_M8 + 0U, // PseudoVMSLE_VV_M8_MASK + 0U, // PseudoVMSLE_VV_MF2 + 0U, // PseudoVMSLE_VV_MF2_MASK + 0U, // PseudoVMSLE_VV_MF4 + 0U, // PseudoVMSLE_VV_MF4_MASK + 0U, // PseudoVMSLE_VV_MF8 + 0U, // PseudoVMSLE_VV_MF8_MASK + 0U, // PseudoVMSLE_VX_M1 + 0U, // PseudoVMSLE_VX_M1_MASK + 0U, // PseudoVMSLE_VX_M2 + 0U, // PseudoVMSLE_VX_M2_MASK + 0U, // PseudoVMSLE_VX_M4 + 0U, // PseudoVMSLE_VX_M4_MASK + 0U, // PseudoVMSLE_VX_M8 + 0U, // PseudoVMSLE_VX_M8_MASK + 0U, // PseudoVMSLE_VX_MF2 + 0U, // PseudoVMSLE_VX_MF2_MASK + 0U, // PseudoVMSLE_VX_MF4 + 0U, // PseudoVMSLE_VX_MF4_MASK + 0U, // PseudoVMSLE_VX_MF8 + 0U, // PseudoVMSLE_VX_MF8_MASK + 0U, // PseudoVMSLTU_VI + 0U, // PseudoVMSLTU_VV_M1 + 0U, // PseudoVMSLTU_VV_M1_MASK + 0U, // PseudoVMSLTU_VV_M2 + 0U, // PseudoVMSLTU_VV_M2_MASK + 0U, // PseudoVMSLTU_VV_M4 + 0U, // PseudoVMSLTU_VV_M4_MASK + 0U, // PseudoVMSLTU_VV_M8 + 0U, // PseudoVMSLTU_VV_M8_MASK + 0U, // PseudoVMSLTU_VV_MF2 + 0U, // PseudoVMSLTU_VV_MF2_MASK + 0U, // PseudoVMSLTU_VV_MF4 + 0U, // PseudoVMSLTU_VV_MF4_MASK + 0U, // PseudoVMSLTU_VV_MF8 + 0U, // PseudoVMSLTU_VV_MF8_MASK + 0U, // PseudoVMSLTU_VX_M1 + 0U, // PseudoVMSLTU_VX_M1_MASK + 0U, // PseudoVMSLTU_VX_M2 + 0U, // PseudoVMSLTU_VX_M2_MASK + 0U, // PseudoVMSLTU_VX_M4 + 0U, // PseudoVMSLTU_VX_M4_MASK + 0U, // PseudoVMSLTU_VX_M8 + 0U, // PseudoVMSLTU_VX_M8_MASK + 0U, // PseudoVMSLTU_VX_MF2 + 0U, // PseudoVMSLTU_VX_MF2_MASK + 0U, // PseudoVMSLTU_VX_MF4 + 0U, // PseudoVMSLTU_VX_MF4_MASK + 0U, // PseudoVMSLTU_VX_MF8 + 0U, // PseudoVMSLTU_VX_MF8_MASK + 0U, // PseudoVMSLT_VI + 0U, // PseudoVMSLT_VV_M1 + 0U, // PseudoVMSLT_VV_M1_MASK + 0U, // PseudoVMSLT_VV_M2 + 0U, // PseudoVMSLT_VV_M2_MASK + 0U, // PseudoVMSLT_VV_M4 + 0U, // PseudoVMSLT_VV_M4_MASK + 0U, // PseudoVMSLT_VV_M8 + 0U, // PseudoVMSLT_VV_M8_MASK + 0U, // PseudoVMSLT_VV_MF2 + 0U, // PseudoVMSLT_VV_MF2_MASK + 0U, // PseudoVMSLT_VV_MF4 + 0U, // PseudoVMSLT_VV_MF4_MASK + 0U, // PseudoVMSLT_VV_MF8 + 0U, // PseudoVMSLT_VV_MF8_MASK + 0U, // PseudoVMSLT_VX_M1 + 0U, // PseudoVMSLT_VX_M1_MASK + 0U, // PseudoVMSLT_VX_M2 + 0U, // PseudoVMSLT_VX_M2_MASK + 0U, // PseudoVMSLT_VX_M4 + 0U, // PseudoVMSLT_VX_M4_MASK + 0U, // PseudoVMSLT_VX_M8 + 0U, // PseudoVMSLT_VX_M8_MASK + 0U, // PseudoVMSLT_VX_MF2 + 0U, // PseudoVMSLT_VX_MF2_MASK + 0U, // PseudoVMSLT_VX_MF4 + 0U, // PseudoVMSLT_VX_MF4_MASK + 0U, // PseudoVMSLT_VX_MF8 + 0U, // PseudoVMSLT_VX_MF8_MASK + 0U, // PseudoVMSNE_VI_M1 + 0U, // PseudoVMSNE_VI_M1_MASK + 0U, // PseudoVMSNE_VI_M2 + 0U, // PseudoVMSNE_VI_M2_MASK + 0U, // PseudoVMSNE_VI_M4 + 0U, // PseudoVMSNE_VI_M4_MASK + 0U, // PseudoVMSNE_VI_M8 + 0U, // PseudoVMSNE_VI_M8_MASK + 0U, // PseudoVMSNE_VI_MF2 + 0U, // PseudoVMSNE_VI_MF2_MASK + 0U, // PseudoVMSNE_VI_MF4 + 0U, // PseudoVMSNE_VI_MF4_MASK + 0U, // PseudoVMSNE_VI_MF8 + 0U, // PseudoVMSNE_VI_MF8_MASK + 0U, // PseudoVMSNE_VV_M1 + 0U, // PseudoVMSNE_VV_M1_MASK + 0U, // PseudoVMSNE_VV_M2 + 0U, // PseudoVMSNE_VV_M2_MASK + 0U, // PseudoVMSNE_VV_M4 + 0U, // PseudoVMSNE_VV_M4_MASK + 0U, // PseudoVMSNE_VV_M8 + 0U, // PseudoVMSNE_VV_M8_MASK + 0U, // PseudoVMSNE_VV_MF2 + 0U, // PseudoVMSNE_VV_MF2_MASK + 0U, // PseudoVMSNE_VV_MF4 + 0U, // PseudoVMSNE_VV_MF4_MASK + 0U, // PseudoVMSNE_VV_MF8 + 0U, // PseudoVMSNE_VV_MF8_MASK + 0U, // PseudoVMSNE_VX_M1 + 0U, // PseudoVMSNE_VX_M1_MASK + 0U, // PseudoVMSNE_VX_M2 + 0U, // PseudoVMSNE_VX_M2_MASK + 0U, // PseudoVMSNE_VX_M4 + 0U, // PseudoVMSNE_VX_M4_MASK + 0U, // PseudoVMSNE_VX_M8 + 0U, // PseudoVMSNE_VX_M8_MASK + 0U, // PseudoVMSNE_VX_MF2 + 0U, // PseudoVMSNE_VX_MF2_MASK + 0U, // PseudoVMSNE_VX_MF4 + 0U, // PseudoVMSNE_VX_MF4_MASK + 0U, // PseudoVMSNE_VX_MF8 + 0U, // PseudoVMSNE_VX_MF8_MASK + 0U, // PseudoVMSOF_M_B1 + 0U, // PseudoVMSOF_M_B16 + 0U, // PseudoVMSOF_M_B16_MASK + 0U, // PseudoVMSOF_M_B1_MASK + 0U, // PseudoVMSOF_M_B2 + 0U, // PseudoVMSOF_M_B2_MASK + 0U, // PseudoVMSOF_M_B32 + 0U, // PseudoVMSOF_M_B32_MASK + 0U, // PseudoVMSOF_M_B4 + 0U, // PseudoVMSOF_M_B4_MASK + 0U, // PseudoVMSOF_M_B64 + 0U, // PseudoVMSOF_M_B64_MASK + 0U, // PseudoVMSOF_M_B8 + 0U, // PseudoVMSOF_M_B8_MASK + 0U, // PseudoVMULHSU_VV_M1 + 0U, // PseudoVMULHSU_VV_M1_MASK + 0U, // PseudoVMULHSU_VV_M2 + 0U, // PseudoVMULHSU_VV_M2_MASK + 0U, // PseudoVMULHSU_VV_M4 + 0U, // PseudoVMULHSU_VV_M4_MASK + 0U, // PseudoVMULHSU_VV_M8 + 0U, // PseudoVMULHSU_VV_M8_MASK + 0U, // PseudoVMULHSU_VV_MF2 + 0U, // PseudoVMULHSU_VV_MF2_MASK + 0U, // PseudoVMULHSU_VV_MF4 + 0U, // PseudoVMULHSU_VV_MF4_MASK + 0U, // PseudoVMULHSU_VV_MF8 + 0U, // PseudoVMULHSU_VV_MF8_MASK + 0U, // PseudoVMULHSU_VX_M1 + 0U, // PseudoVMULHSU_VX_M1_MASK + 0U, // PseudoVMULHSU_VX_M2 + 0U, // PseudoVMULHSU_VX_M2_MASK + 0U, // PseudoVMULHSU_VX_M4 + 0U, // PseudoVMULHSU_VX_M4_MASK + 0U, // PseudoVMULHSU_VX_M8 + 0U, // PseudoVMULHSU_VX_M8_MASK + 0U, // PseudoVMULHSU_VX_MF2 + 0U, // PseudoVMULHSU_VX_MF2_MASK + 0U, // PseudoVMULHSU_VX_MF4 + 0U, // PseudoVMULHSU_VX_MF4_MASK + 0U, // PseudoVMULHSU_VX_MF8 + 0U, // PseudoVMULHSU_VX_MF8_MASK + 0U, // PseudoVMULHU_VV_M1 + 0U, // PseudoVMULHU_VV_M1_MASK + 0U, // PseudoVMULHU_VV_M2 + 0U, // PseudoVMULHU_VV_M2_MASK + 0U, // PseudoVMULHU_VV_M4 + 0U, // PseudoVMULHU_VV_M4_MASK + 0U, // PseudoVMULHU_VV_M8 + 0U, // PseudoVMULHU_VV_M8_MASK + 0U, // PseudoVMULHU_VV_MF2 + 0U, // PseudoVMULHU_VV_MF2_MASK + 0U, // PseudoVMULHU_VV_MF4 + 0U, // PseudoVMULHU_VV_MF4_MASK + 0U, // PseudoVMULHU_VV_MF8 + 0U, // PseudoVMULHU_VV_MF8_MASK + 0U, // PseudoVMULHU_VX_M1 + 0U, // PseudoVMULHU_VX_M1_MASK + 0U, // PseudoVMULHU_VX_M2 + 0U, // PseudoVMULHU_VX_M2_MASK + 0U, // PseudoVMULHU_VX_M4 + 0U, // PseudoVMULHU_VX_M4_MASK + 0U, // PseudoVMULHU_VX_M8 + 0U, // PseudoVMULHU_VX_M8_MASK + 0U, // PseudoVMULHU_VX_MF2 + 0U, // PseudoVMULHU_VX_MF2_MASK + 0U, // PseudoVMULHU_VX_MF4 + 0U, // PseudoVMULHU_VX_MF4_MASK + 0U, // PseudoVMULHU_VX_MF8 + 0U, // PseudoVMULHU_VX_MF8_MASK + 0U, // PseudoVMULH_VV_M1 + 0U, // PseudoVMULH_VV_M1_MASK + 0U, // PseudoVMULH_VV_M2 + 0U, // PseudoVMULH_VV_M2_MASK + 0U, // PseudoVMULH_VV_M4 + 0U, // PseudoVMULH_VV_M4_MASK + 0U, // PseudoVMULH_VV_M8 + 0U, // PseudoVMULH_VV_M8_MASK + 0U, // PseudoVMULH_VV_MF2 + 0U, // PseudoVMULH_VV_MF2_MASK + 0U, // PseudoVMULH_VV_MF4 + 0U, // PseudoVMULH_VV_MF4_MASK + 0U, // PseudoVMULH_VV_MF8 + 0U, // PseudoVMULH_VV_MF8_MASK + 0U, // PseudoVMULH_VX_M1 + 0U, // PseudoVMULH_VX_M1_MASK + 0U, // PseudoVMULH_VX_M2 + 0U, // PseudoVMULH_VX_M2_MASK + 0U, // PseudoVMULH_VX_M4 + 0U, // PseudoVMULH_VX_M4_MASK + 0U, // PseudoVMULH_VX_M8 + 0U, // PseudoVMULH_VX_M8_MASK + 0U, // PseudoVMULH_VX_MF2 + 0U, // PseudoVMULH_VX_MF2_MASK + 0U, // PseudoVMULH_VX_MF4 + 0U, // PseudoVMULH_VX_MF4_MASK + 0U, // PseudoVMULH_VX_MF8 + 0U, // PseudoVMULH_VX_MF8_MASK + 0U, // PseudoVMUL_VV_M1 + 0U, // PseudoVMUL_VV_M1_MASK + 0U, // PseudoVMUL_VV_M2 + 0U, // PseudoVMUL_VV_M2_MASK + 0U, // PseudoVMUL_VV_M4 + 0U, // PseudoVMUL_VV_M4_MASK + 0U, // PseudoVMUL_VV_M8 + 0U, // PseudoVMUL_VV_M8_MASK + 0U, // PseudoVMUL_VV_MF2 + 0U, // PseudoVMUL_VV_MF2_MASK + 0U, // PseudoVMUL_VV_MF4 + 0U, // PseudoVMUL_VV_MF4_MASK + 0U, // PseudoVMUL_VV_MF8 + 0U, // PseudoVMUL_VV_MF8_MASK + 0U, // PseudoVMUL_VX_M1 + 0U, // PseudoVMUL_VX_M1_MASK + 0U, // PseudoVMUL_VX_M2 + 0U, // PseudoVMUL_VX_M2_MASK + 0U, // PseudoVMUL_VX_M4 + 0U, // PseudoVMUL_VX_M4_MASK + 0U, // PseudoVMUL_VX_M8 + 0U, // PseudoVMUL_VX_M8_MASK + 0U, // PseudoVMUL_VX_MF2 + 0U, // PseudoVMUL_VX_MF2_MASK + 0U, // PseudoVMUL_VX_MF4 + 0U, // PseudoVMUL_VX_MF4_MASK + 0U, // PseudoVMUL_VX_MF8 + 0U, // PseudoVMUL_VX_MF8_MASK + 0U, // PseudoVMV1R_V + 0U, // PseudoVMV2R_V + 0U, // PseudoVMV4R_V + 0U, // PseudoVMV8R_V + 0U, // PseudoVMV_S_X_M1 + 0U, // PseudoVMV_S_X_M2 + 0U, // PseudoVMV_S_X_M4 + 0U, // PseudoVMV_S_X_M8 + 0U, // PseudoVMV_S_X_MF2 + 0U, // PseudoVMV_S_X_MF4 + 0U, // PseudoVMV_S_X_MF8 + 0U, // PseudoVMV_V_I_M1 + 0U, // PseudoVMV_V_I_M2 + 0U, // PseudoVMV_V_I_M4 + 0U, // PseudoVMV_V_I_M8 + 0U, // PseudoVMV_V_I_MF2 + 0U, // PseudoVMV_V_I_MF4 + 0U, // PseudoVMV_V_I_MF8 + 0U, // PseudoVMV_V_V_M1 + 0U, // PseudoVMV_V_V_M2 + 0U, // PseudoVMV_V_V_M4 + 0U, // PseudoVMV_V_V_M8 + 0U, // PseudoVMV_V_V_MF2 + 0U, // PseudoVMV_V_V_MF4 + 0U, // PseudoVMV_V_V_MF8 + 0U, // PseudoVMV_V_X_M1 + 0U, // PseudoVMV_V_X_M2 + 0U, // PseudoVMV_V_X_M4 + 0U, // PseudoVMV_V_X_M8 + 0U, // PseudoVMV_V_X_MF2 + 0U, // PseudoVMV_V_X_MF4 + 0U, // PseudoVMV_V_X_MF8 + 0U, // PseudoVMV_X_S_M1 + 0U, // PseudoVMV_X_S_M2 + 0U, // PseudoVMV_X_S_M4 + 0U, // PseudoVMV_X_S_M8 + 0U, // PseudoVMV_X_S_MF2 + 0U, // PseudoVMV_X_S_MF4 + 0U, // PseudoVMV_X_S_MF8 + 0U, // PseudoVMXNOR_MM_M1 + 0U, // PseudoVMXNOR_MM_M2 + 0U, // PseudoVMXNOR_MM_M4 + 0U, // PseudoVMXNOR_MM_M8 + 0U, // PseudoVMXNOR_MM_MF2 + 0U, // PseudoVMXNOR_MM_MF4 + 0U, // PseudoVMXNOR_MM_MF8 + 0U, // PseudoVMXOR_MM_M1 + 0U, // PseudoVMXOR_MM_M2 + 0U, // PseudoVMXOR_MM_M4 + 0U, // PseudoVMXOR_MM_M8 + 0U, // PseudoVMXOR_MM_MF2 + 0U, // PseudoVMXOR_MM_MF4 + 0U, // PseudoVMXOR_MM_MF8 + 0U, // PseudoVNCLIPU_WI_M1 + 0U, // PseudoVNCLIPU_WI_M1_MASK + 0U, // PseudoVNCLIPU_WI_M2 + 0U, // PseudoVNCLIPU_WI_M2_MASK + 0U, // PseudoVNCLIPU_WI_M4 + 0U, // PseudoVNCLIPU_WI_M4_MASK + 0U, // PseudoVNCLIPU_WI_MF2 + 0U, // PseudoVNCLIPU_WI_MF2_MASK + 0U, // PseudoVNCLIPU_WI_MF4 + 0U, // PseudoVNCLIPU_WI_MF4_MASK + 0U, // PseudoVNCLIPU_WI_MF8 + 0U, // PseudoVNCLIPU_WI_MF8_MASK + 0U, // PseudoVNCLIPU_WV_M1 + 0U, // PseudoVNCLIPU_WV_M1_MASK + 0U, // PseudoVNCLIPU_WV_M2 + 0U, // PseudoVNCLIPU_WV_M2_MASK + 0U, // PseudoVNCLIPU_WV_M4 + 0U, // PseudoVNCLIPU_WV_M4_MASK + 0U, // PseudoVNCLIPU_WV_MF2 + 0U, // PseudoVNCLIPU_WV_MF2_MASK + 0U, // PseudoVNCLIPU_WV_MF4 + 0U, // PseudoVNCLIPU_WV_MF4_MASK + 0U, // PseudoVNCLIPU_WV_MF8 + 0U, // PseudoVNCLIPU_WV_MF8_MASK + 0U, // PseudoVNCLIPU_WX_M1 + 0U, // PseudoVNCLIPU_WX_M1_MASK + 0U, // PseudoVNCLIPU_WX_M2 + 0U, // PseudoVNCLIPU_WX_M2_MASK + 0U, // PseudoVNCLIPU_WX_M4 + 0U, // PseudoVNCLIPU_WX_M4_MASK + 0U, // PseudoVNCLIPU_WX_MF2 + 0U, // PseudoVNCLIPU_WX_MF2_MASK + 0U, // PseudoVNCLIPU_WX_MF4 + 0U, // PseudoVNCLIPU_WX_MF4_MASK + 0U, // PseudoVNCLIPU_WX_MF8 + 0U, // PseudoVNCLIPU_WX_MF8_MASK + 0U, // PseudoVNCLIP_WI_M1 + 0U, // PseudoVNCLIP_WI_M1_MASK + 0U, // PseudoVNCLIP_WI_M2 + 0U, // PseudoVNCLIP_WI_M2_MASK + 0U, // PseudoVNCLIP_WI_M4 + 0U, // PseudoVNCLIP_WI_M4_MASK + 0U, // PseudoVNCLIP_WI_MF2 + 0U, // PseudoVNCLIP_WI_MF2_MASK + 0U, // PseudoVNCLIP_WI_MF4 + 0U, // PseudoVNCLIP_WI_MF4_MASK + 0U, // PseudoVNCLIP_WI_MF8 + 0U, // PseudoVNCLIP_WI_MF8_MASK + 0U, // PseudoVNCLIP_WV_M1 + 0U, // PseudoVNCLIP_WV_M1_MASK + 0U, // PseudoVNCLIP_WV_M2 + 0U, // PseudoVNCLIP_WV_M2_MASK + 0U, // PseudoVNCLIP_WV_M4 + 0U, // PseudoVNCLIP_WV_M4_MASK + 0U, // PseudoVNCLIP_WV_MF2 + 0U, // PseudoVNCLIP_WV_MF2_MASK + 0U, // PseudoVNCLIP_WV_MF4 + 0U, // PseudoVNCLIP_WV_MF4_MASK + 0U, // PseudoVNCLIP_WV_MF8 + 0U, // PseudoVNCLIP_WV_MF8_MASK + 0U, // PseudoVNCLIP_WX_M1 + 0U, // PseudoVNCLIP_WX_M1_MASK + 0U, // PseudoVNCLIP_WX_M2 + 0U, // PseudoVNCLIP_WX_M2_MASK + 0U, // PseudoVNCLIP_WX_M4 + 0U, // PseudoVNCLIP_WX_M4_MASK + 0U, // PseudoVNCLIP_WX_MF2 + 0U, // PseudoVNCLIP_WX_MF2_MASK + 0U, // PseudoVNCLIP_WX_MF4 + 0U, // PseudoVNCLIP_WX_MF4_MASK + 0U, // PseudoVNCLIP_WX_MF8 + 0U, // PseudoVNCLIP_WX_MF8_MASK + 0U, // PseudoVNMSAC_VV_M1 + 0U, // PseudoVNMSAC_VV_M1_MASK + 0U, // PseudoVNMSAC_VV_M2 + 0U, // PseudoVNMSAC_VV_M2_MASK + 0U, // PseudoVNMSAC_VV_M4 + 0U, // PseudoVNMSAC_VV_M4_MASK + 0U, // PseudoVNMSAC_VV_M8 + 0U, // PseudoVNMSAC_VV_M8_MASK + 0U, // PseudoVNMSAC_VV_MF2 + 0U, // PseudoVNMSAC_VV_MF2_MASK + 0U, // PseudoVNMSAC_VV_MF4 + 0U, // PseudoVNMSAC_VV_MF4_MASK + 0U, // PseudoVNMSAC_VV_MF8 + 0U, // PseudoVNMSAC_VV_MF8_MASK + 0U, // PseudoVNMSAC_VX_M1 + 0U, // PseudoVNMSAC_VX_M1_MASK + 0U, // PseudoVNMSAC_VX_M2 + 0U, // PseudoVNMSAC_VX_M2_MASK + 0U, // PseudoVNMSAC_VX_M4 + 0U, // PseudoVNMSAC_VX_M4_MASK + 0U, // PseudoVNMSAC_VX_M8 + 0U, // PseudoVNMSAC_VX_M8_MASK + 0U, // PseudoVNMSAC_VX_MF2 + 0U, // PseudoVNMSAC_VX_MF2_MASK + 0U, // PseudoVNMSAC_VX_MF4 + 0U, // PseudoVNMSAC_VX_MF4_MASK + 0U, // PseudoVNMSAC_VX_MF8 + 0U, // PseudoVNMSAC_VX_MF8_MASK + 0U, // PseudoVNMSUB_VV_M1 + 0U, // PseudoVNMSUB_VV_M1_MASK + 0U, // PseudoVNMSUB_VV_M2 + 0U, // PseudoVNMSUB_VV_M2_MASK + 0U, // PseudoVNMSUB_VV_M4 + 0U, // PseudoVNMSUB_VV_M4_MASK + 0U, // PseudoVNMSUB_VV_M8 + 0U, // PseudoVNMSUB_VV_M8_MASK + 0U, // PseudoVNMSUB_VV_MF2 + 0U, // PseudoVNMSUB_VV_MF2_MASK + 0U, // PseudoVNMSUB_VV_MF4 + 0U, // PseudoVNMSUB_VV_MF4_MASK + 0U, // PseudoVNMSUB_VV_MF8 + 0U, // PseudoVNMSUB_VV_MF8_MASK + 0U, // PseudoVNMSUB_VX_M1 + 0U, // PseudoVNMSUB_VX_M1_MASK + 0U, // PseudoVNMSUB_VX_M2 + 0U, // PseudoVNMSUB_VX_M2_MASK + 0U, // PseudoVNMSUB_VX_M4 + 0U, // PseudoVNMSUB_VX_M4_MASK + 0U, // PseudoVNMSUB_VX_M8 + 0U, // PseudoVNMSUB_VX_M8_MASK + 0U, // PseudoVNMSUB_VX_MF2 + 0U, // PseudoVNMSUB_VX_MF2_MASK + 0U, // PseudoVNMSUB_VX_MF4 + 0U, // PseudoVNMSUB_VX_MF4_MASK + 0U, // PseudoVNMSUB_VX_MF8 + 0U, // PseudoVNMSUB_VX_MF8_MASK + 0U, // PseudoVNSRA_WI_M1 + 0U, // PseudoVNSRA_WI_M1_MASK + 0U, // PseudoVNSRA_WI_M2 + 0U, // PseudoVNSRA_WI_M2_MASK + 0U, // PseudoVNSRA_WI_M4 + 0U, // PseudoVNSRA_WI_M4_MASK + 0U, // PseudoVNSRA_WI_MF2 + 0U, // PseudoVNSRA_WI_MF2_MASK + 0U, // PseudoVNSRA_WI_MF4 + 0U, // PseudoVNSRA_WI_MF4_MASK + 0U, // PseudoVNSRA_WI_MF8 + 0U, // PseudoVNSRA_WI_MF8_MASK + 0U, // PseudoVNSRA_WV_M1 + 0U, // PseudoVNSRA_WV_M1_MASK + 0U, // PseudoVNSRA_WV_M2 + 0U, // PseudoVNSRA_WV_M2_MASK + 0U, // PseudoVNSRA_WV_M4 + 0U, // PseudoVNSRA_WV_M4_MASK + 0U, // PseudoVNSRA_WV_MF2 + 0U, // PseudoVNSRA_WV_MF2_MASK + 0U, // PseudoVNSRA_WV_MF4 + 0U, // PseudoVNSRA_WV_MF4_MASK + 0U, // PseudoVNSRA_WV_MF8 + 0U, // PseudoVNSRA_WV_MF8_MASK + 0U, // PseudoVNSRA_WX_M1 + 0U, // PseudoVNSRA_WX_M1_MASK + 0U, // PseudoVNSRA_WX_M2 + 0U, // PseudoVNSRA_WX_M2_MASK + 0U, // PseudoVNSRA_WX_M4 + 0U, // PseudoVNSRA_WX_M4_MASK + 0U, // PseudoVNSRA_WX_MF2 + 0U, // PseudoVNSRA_WX_MF2_MASK + 0U, // PseudoVNSRA_WX_MF4 + 0U, // PseudoVNSRA_WX_MF4_MASK + 0U, // PseudoVNSRA_WX_MF8 + 0U, // PseudoVNSRA_WX_MF8_MASK + 0U, // PseudoVNSRL_WI_M1 + 0U, // PseudoVNSRL_WI_M1_MASK + 0U, // PseudoVNSRL_WI_M2 + 0U, // PseudoVNSRL_WI_M2_MASK + 0U, // PseudoVNSRL_WI_M4 + 0U, // PseudoVNSRL_WI_M4_MASK + 0U, // PseudoVNSRL_WI_MF2 + 0U, // PseudoVNSRL_WI_MF2_MASK + 0U, // PseudoVNSRL_WI_MF4 + 0U, // PseudoVNSRL_WI_MF4_MASK + 0U, // PseudoVNSRL_WI_MF8 + 0U, // PseudoVNSRL_WI_MF8_MASK + 0U, // PseudoVNSRL_WV_M1 + 0U, // PseudoVNSRL_WV_M1_MASK + 0U, // PseudoVNSRL_WV_M2 + 0U, // PseudoVNSRL_WV_M2_MASK + 0U, // PseudoVNSRL_WV_M4 + 0U, // PseudoVNSRL_WV_M4_MASK + 0U, // PseudoVNSRL_WV_MF2 + 0U, // PseudoVNSRL_WV_MF2_MASK + 0U, // PseudoVNSRL_WV_MF4 + 0U, // PseudoVNSRL_WV_MF4_MASK + 0U, // PseudoVNSRL_WV_MF8 + 0U, // PseudoVNSRL_WV_MF8_MASK + 0U, // PseudoVNSRL_WX_M1 + 0U, // PseudoVNSRL_WX_M1_MASK + 0U, // PseudoVNSRL_WX_M2 + 0U, // PseudoVNSRL_WX_M2_MASK + 0U, // PseudoVNSRL_WX_M4 + 0U, // PseudoVNSRL_WX_M4_MASK + 0U, // PseudoVNSRL_WX_MF2 + 0U, // PseudoVNSRL_WX_MF2_MASK + 0U, // PseudoVNSRL_WX_MF4 + 0U, // PseudoVNSRL_WX_MF4_MASK + 0U, // PseudoVNSRL_WX_MF8 + 0U, // PseudoVNSRL_WX_MF8_MASK + 0U, // PseudoVOR_VI_M1 + 0U, // PseudoVOR_VI_M1_MASK + 0U, // PseudoVOR_VI_M2 + 0U, // PseudoVOR_VI_M2_MASK + 0U, // PseudoVOR_VI_M4 + 0U, // PseudoVOR_VI_M4_MASK + 0U, // PseudoVOR_VI_M8 + 0U, // PseudoVOR_VI_M8_MASK + 0U, // PseudoVOR_VI_MF2 + 0U, // PseudoVOR_VI_MF2_MASK + 0U, // PseudoVOR_VI_MF4 + 0U, // PseudoVOR_VI_MF4_MASK + 0U, // PseudoVOR_VI_MF8 + 0U, // PseudoVOR_VI_MF8_MASK + 0U, // PseudoVOR_VV_M1 + 0U, // PseudoVOR_VV_M1_MASK + 0U, // PseudoVOR_VV_M2 + 0U, // PseudoVOR_VV_M2_MASK + 0U, // PseudoVOR_VV_M4 + 0U, // PseudoVOR_VV_M4_MASK + 0U, // PseudoVOR_VV_M8 + 0U, // PseudoVOR_VV_M8_MASK + 0U, // PseudoVOR_VV_MF2 + 0U, // PseudoVOR_VV_MF2_MASK + 0U, // PseudoVOR_VV_MF4 + 0U, // PseudoVOR_VV_MF4_MASK + 0U, // PseudoVOR_VV_MF8 + 0U, // PseudoVOR_VV_MF8_MASK + 0U, // PseudoVOR_VX_M1 + 0U, // PseudoVOR_VX_M1_MASK + 0U, // PseudoVOR_VX_M2 + 0U, // PseudoVOR_VX_M2_MASK + 0U, // PseudoVOR_VX_M4 + 0U, // PseudoVOR_VX_M4_MASK + 0U, // PseudoVOR_VX_M8 + 0U, // PseudoVOR_VX_M8_MASK + 0U, // PseudoVOR_VX_MF2 + 0U, // PseudoVOR_VX_MF2_MASK + 0U, // PseudoVOR_VX_MF4 + 0U, // PseudoVOR_VX_MF4_MASK + 0U, // PseudoVOR_VX_MF8 + 0U, // PseudoVOR_VX_MF8_MASK + 0U, // PseudoVREDAND_VS_M1 + 0U, // PseudoVREDAND_VS_M1_MASK + 0U, // PseudoVREDAND_VS_M2 + 0U, // PseudoVREDAND_VS_M2_MASK + 0U, // PseudoVREDAND_VS_M4 + 0U, // PseudoVREDAND_VS_M4_MASK + 0U, // PseudoVREDAND_VS_M8 + 0U, // PseudoVREDAND_VS_M8_MASK + 0U, // PseudoVREDAND_VS_MF2 + 0U, // PseudoVREDAND_VS_MF2_MASK + 0U, // PseudoVREDAND_VS_MF4 + 0U, // PseudoVREDAND_VS_MF4_MASK + 0U, // PseudoVREDAND_VS_MF8 + 0U, // PseudoVREDAND_VS_MF8_MASK + 0U, // PseudoVREDMAXU_VS_M1 + 0U, // PseudoVREDMAXU_VS_M1_MASK + 0U, // PseudoVREDMAXU_VS_M2 + 0U, // PseudoVREDMAXU_VS_M2_MASK + 0U, // PseudoVREDMAXU_VS_M4 + 0U, // PseudoVREDMAXU_VS_M4_MASK + 0U, // PseudoVREDMAXU_VS_M8 + 0U, // PseudoVREDMAXU_VS_M8_MASK + 0U, // PseudoVREDMAXU_VS_MF2 + 0U, // PseudoVREDMAXU_VS_MF2_MASK + 0U, // PseudoVREDMAXU_VS_MF4 + 0U, // PseudoVREDMAXU_VS_MF4_MASK + 0U, // PseudoVREDMAXU_VS_MF8 + 0U, // PseudoVREDMAXU_VS_MF8_MASK + 0U, // PseudoVREDMAX_VS_M1 + 0U, // PseudoVREDMAX_VS_M1_MASK + 0U, // PseudoVREDMAX_VS_M2 + 0U, // PseudoVREDMAX_VS_M2_MASK + 0U, // PseudoVREDMAX_VS_M4 + 0U, // PseudoVREDMAX_VS_M4_MASK + 0U, // PseudoVREDMAX_VS_M8 + 0U, // PseudoVREDMAX_VS_M8_MASK + 0U, // PseudoVREDMAX_VS_MF2 + 0U, // PseudoVREDMAX_VS_MF2_MASK + 0U, // PseudoVREDMAX_VS_MF4 + 0U, // PseudoVREDMAX_VS_MF4_MASK + 0U, // PseudoVREDMAX_VS_MF8 + 0U, // PseudoVREDMAX_VS_MF8_MASK + 0U, // PseudoVREDMINU_VS_M1 + 0U, // PseudoVREDMINU_VS_M1_MASK + 0U, // PseudoVREDMINU_VS_M2 + 0U, // PseudoVREDMINU_VS_M2_MASK + 0U, // PseudoVREDMINU_VS_M4 + 0U, // PseudoVREDMINU_VS_M4_MASK + 0U, // PseudoVREDMINU_VS_M8 + 0U, // PseudoVREDMINU_VS_M8_MASK + 0U, // PseudoVREDMINU_VS_MF2 + 0U, // PseudoVREDMINU_VS_MF2_MASK + 0U, // PseudoVREDMINU_VS_MF4 + 0U, // PseudoVREDMINU_VS_MF4_MASK + 0U, // PseudoVREDMINU_VS_MF8 + 0U, // PseudoVREDMINU_VS_MF8_MASK + 0U, // PseudoVREDMIN_VS_M1 + 0U, // PseudoVREDMIN_VS_M1_MASK + 0U, // PseudoVREDMIN_VS_M2 + 0U, // PseudoVREDMIN_VS_M2_MASK + 0U, // PseudoVREDMIN_VS_M4 + 0U, // PseudoVREDMIN_VS_M4_MASK + 0U, // PseudoVREDMIN_VS_M8 + 0U, // PseudoVREDMIN_VS_M8_MASK + 0U, // PseudoVREDMIN_VS_MF2 + 0U, // PseudoVREDMIN_VS_MF2_MASK + 0U, // PseudoVREDMIN_VS_MF4 + 0U, // PseudoVREDMIN_VS_MF4_MASK + 0U, // PseudoVREDMIN_VS_MF8 + 0U, // PseudoVREDMIN_VS_MF8_MASK + 0U, // PseudoVREDOR_VS_M1 + 0U, // PseudoVREDOR_VS_M1_MASK + 0U, // PseudoVREDOR_VS_M2 + 0U, // PseudoVREDOR_VS_M2_MASK + 0U, // PseudoVREDOR_VS_M4 + 0U, // PseudoVREDOR_VS_M4_MASK + 0U, // PseudoVREDOR_VS_M8 + 0U, // PseudoVREDOR_VS_M8_MASK + 0U, // PseudoVREDOR_VS_MF2 + 0U, // PseudoVREDOR_VS_MF2_MASK + 0U, // PseudoVREDOR_VS_MF4 + 0U, // PseudoVREDOR_VS_MF4_MASK + 0U, // PseudoVREDOR_VS_MF8 + 0U, // PseudoVREDOR_VS_MF8_MASK + 0U, // PseudoVREDSUM_VS_M1 + 0U, // PseudoVREDSUM_VS_M1_MASK + 0U, // PseudoVREDSUM_VS_M2 + 0U, // PseudoVREDSUM_VS_M2_MASK + 0U, // PseudoVREDSUM_VS_M4 + 0U, // PseudoVREDSUM_VS_M4_MASK + 0U, // PseudoVREDSUM_VS_M8 + 0U, // PseudoVREDSUM_VS_M8_MASK + 0U, // PseudoVREDSUM_VS_MF2 + 0U, // PseudoVREDSUM_VS_MF2_MASK + 0U, // PseudoVREDSUM_VS_MF4 + 0U, // PseudoVREDSUM_VS_MF4_MASK + 0U, // PseudoVREDSUM_VS_MF8 + 0U, // PseudoVREDSUM_VS_MF8_MASK + 0U, // PseudoVREDXOR_VS_M1 + 0U, // PseudoVREDXOR_VS_M1_MASK + 0U, // PseudoVREDXOR_VS_M2 + 0U, // PseudoVREDXOR_VS_M2_MASK + 0U, // PseudoVREDXOR_VS_M4 + 0U, // PseudoVREDXOR_VS_M4_MASK + 0U, // PseudoVREDXOR_VS_M8 + 0U, // PseudoVREDXOR_VS_M8_MASK + 0U, // PseudoVREDXOR_VS_MF2 + 0U, // PseudoVREDXOR_VS_MF2_MASK + 0U, // PseudoVREDXOR_VS_MF4 + 0U, // PseudoVREDXOR_VS_MF4_MASK + 0U, // PseudoVREDXOR_VS_MF8 + 0U, // PseudoVREDXOR_VS_MF8_MASK + 0U, // PseudoVRELOAD2_M1 + 0U, // PseudoVRELOAD2_M2 + 0U, // PseudoVRELOAD2_M4 + 0U, // PseudoVRELOAD2_MF2 + 0U, // PseudoVRELOAD2_MF4 + 0U, // PseudoVRELOAD2_MF8 + 0U, // PseudoVRELOAD3_M1 + 0U, // PseudoVRELOAD3_M2 + 0U, // PseudoVRELOAD3_MF2 + 0U, // PseudoVRELOAD3_MF4 + 0U, // PseudoVRELOAD3_MF8 + 0U, // PseudoVRELOAD4_M1 + 0U, // PseudoVRELOAD4_M2 + 0U, // PseudoVRELOAD4_MF2 + 0U, // PseudoVRELOAD4_MF4 + 0U, // PseudoVRELOAD4_MF8 + 0U, // PseudoVRELOAD5_M1 + 0U, // PseudoVRELOAD5_MF2 + 0U, // PseudoVRELOAD5_MF4 + 0U, // PseudoVRELOAD5_MF8 + 0U, // PseudoVRELOAD6_M1 + 0U, // PseudoVRELOAD6_MF2 + 0U, // PseudoVRELOAD6_MF4 + 0U, // PseudoVRELOAD6_MF8 + 0U, // PseudoVRELOAD7_M1 + 0U, // PseudoVRELOAD7_MF2 + 0U, // PseudoVRELOAD7_MF4 + 0U, // PseudoVRELOAD7_MF8 + 0U, // PseudoVRELOAD8_M1 + 0U, // PseudoVRELOAD8_MF2 + 0U, // PseudoVRELOAD8_MF4 + 0U, // PseudoVRELOAD8_MF8 + 0U, // PseudoVRELOAD_M1 + 0U, // PseudoVRELOAD_M2 + 0U, // PseudoVRELOAD_M4 + 0U, // PseudoVRELOAD_M8 + 0U, // PseudoVREMU_VV_M1 + 0U, // PseudoVREMU_VV_M1_MASK + 0U, // PseudoVREMU_VV_M2 + 0U, // PseudoVREMU_VV_M2_MASK + 0U, // PseudoVREMU_VV_M4 + 0U, // PseudoVREMU_VV_M4_MASK + 0U, // PseudoVREMU_VV_M8 + 0U, // PseudoVREMU_VV_M8_MASK + 0U, // PseudoVREMU_VV_MF2 + 0U, // PseudoVREMU_VV_MF2_MASK + 0U, // PseudoVREMU_VV_MF4 + 0U, // PseudoVREMU_VV_MF4_MASK + 0U, // PseudoVREMU_VV_MF8 + 0U, // PseudoVREMU_VV_MF8_MASK + 0U, // PseudoVREMU_VX_M1 + 0U, // PseudoVREMU_VX_M1_MASK + 0U, // PseudoVREMU_VX_M2 + 0U, // PseudoVREMU_VX_M2_MASK + 0U, // PseudoVREMU_VX_M4 + 0U, // PseudoVREMU_VX_M4_MASK + 0U, // PseudoVREMU_VX_M8 + 0U, // PseudoVREMU_VX_M8_MASK + 0U, // PseudoVREMU_VX_MF2 + 0U, // PseudoVREMU_VX_MF2_MASK + 0U, // PseudoVREMU_VX_MF4 + 0U, // PseudoVREMU_VX_MF4_MASK + 0U, // PseudoVREMU_VX_MF8 + 0U, // PseudoVREMU_VX_MF8_MASK + 0U, // PseudoVREM_VV_M1 + 0U, // PseudoVREM_VV_M1_MASK + 0U, // PseudoVREM_VV_M2 + 0U, // PseudoVREM_VV_M2_MASK + 0U, // PseudoVREM_VV_M4 + 0U, // PseudoVREM_VV_M4_MASK + 0U, // PseudoVREM_VV_M8 + 0U, // PseudoVREM_VV_M8_MASK + 0U, // PseudoVREM_VV_MF2 + 0U, // PseudoVREM_VV_MF2_MASK + 0U, // PseudoVREM_VV_MF4 + 0U, // PseudoVREM_VV_MF4_MASK + 0U, // PseudoVREM_VV_MF8 + 0U, // PseudoVREM_VV_MF8_MASK + 0U, // PseudoVREM_VX_M1 + 0U, // PseudoVREM_VX_M1_MASK + 0U, // PseudoVREM_VX_M2 + 0U, // PseudoVREM_VX_M2_MASK + 0U, // PseudoVREM_VX_M4 + 0U, // PseudoVREM_VX_M4_MASK + 0U, // PseudoVREM_VX_M8 + 0U, // PseudoVREM_VX_M8_MASK + 0U, // PseudoVREM_VX_MF2 + 0U, // PseudoVREM_VX_MF2_MASK + 0U, // PseudoVREM_VX_MF4 + 0U, // PseudoVREM_VX_MF4_MASK + 0U, // PseudoVREM_VX_MF8 + 0U, // PseudoVREM_VX_MF8_MASK + 0U, // PseudoVRGATHEREI16_VV_M1_M1 + 0U, // PseudoVRGATHEREI16_VV_M1_M1_MASK + 0U, // PseudoVRGATHEREI16_VV_M1_M2 + 0U, // PseudoVRGATHEREI16_VV_M1_M2_MASK + 0U, // PseudoVRGATHEREI16_VV_M1_MF2 + 0U, // PseudoVRGATHEREI16_VV_M1_MF2_MASK + 0U, // PseudoVRGATHEREI16_VV_M1_MF4 + 0U, // PseudoVRGATHEREI16_VV_M1_MF4_MASK + 0U, // PseudoVRGATHEREI16_VV_M2_M1 + 0U, // PseudoVRGATHEREI16_VV_M2_M1_MASK + 0U, // PseudoVRGATHEREI16_VV_M2_M2 + 0U, // PseudoVRGATHEREI16_VV_M2_M2_MASK + 0U, // PseudoVRGATHEREI16_VV_M2_M4 + 0U, // PseudoVRGATHEREI16_VV_M2_M4_MASK + 0U, // PseudoVRGATHEREI16_VV_M2_MF2 + 0U, // PseudoVRGATHEREI16_VV_M2_MF2_MASK + 0U, // PseudoVRGATHEREI16_VV_M4_M1 + 0U, // PseudoVRGATHEREI16_VV_M4_M1_MASK + 0U, // PseudoVRGATHEREI16_VV_M4_M2 + 0U, // PseudoVRGATHEREI16_VV_M4_M2_MASK + 0U, // PseudoVRGATHEREI16_VV_M4_M4 + 0U, // PseudoVRGATHEREI16_VV_M4_M4_MASK + 0U, // PseudoVRGATHEREI16_VV_M4_M8 + 0U, // PseudoVRGATHEREI16_VV_M4_M8_MASK + 0U, // PseudoVRGATHEREI16_VV_M8_M2 + 0U, // PseudoVRGATHEREI16_VV_M8_M2_MASK + 0U, // PseudoVRGATHEREI16_VV_M8_M4 + 0U, // PseudoVRGATHEREI16_VV_M8_M4_MASK + 0U, // PseudoVRGATHEREI16_VV_M8_M8 + 0U, // PseudoVRGATHEREI16_VV_M8_M8_MASK + 0U, // PseudoVRGATHEREI16_VV_MF2_M1 + 0U, // PseudoVRGATHEREI16_VV_MF2_M1_MASK + 0U, // PseudoVRGATHEREI16_VV_MF2_MF2 + 0U, // PseudoVRGATHEREI16_VV_MF2_MF2_MASK + 0U, // PseudoVRGATHEREI16_VV_MF2_MF4 + 0U, // PseudoVRGATHEREI16_VV_MF2_MF4_MASK + 0U, // PseudoVRGATHEREI16_VV_MF2_MF8 + 0U, // PseudoVRGATHEREI16_VV_MF2_MF8_MASK + 0U, // PseudoVRGATHEREI16_VV_MF4_MF2 + 0U, // PseudoVRGATHEREI16_VV_MF4_MF2_MASK + 0U, // PseudoVRGATHEREI16_VV_MF4_MF4 + 0U, // PseudoVRGATHEREI16_VV_MF4_MF4_MASK + 0U, // PseudoVRGATHEREI16_VV_MF4_MF8 + 0U, // PseudoVRGATHEREI16_VV_MF4_MF8_MASK + 0U, // PseudoVRGATHEREI16_VV_MF8_MF4 + 0U, // PseudoVRGATHEREI16_VV_MF8_MF4_MASK + 0U, // PseudoVRGATHEREI16_VV_MF8_MF8 + 0U, // PseudoVRGATHEREI16_VV_MF8_MF8_MASK + 0U, // PseudoVRGATHER_VI_M1 + 0U, // PseudoVRGATHER_VI_M1_MASK + 0U, // PseudoVRGATHER_VI_M2 + 0U, // PseudoVRGATHER_VI_M2_MASK + 0U, // PseudoVRGATHER_VI_M4 + 0U, // PseudoVRGATHER_VI_M4_MASK + 0U, // PseudoVRGATHER_VI_M8 + 0U, // PseudoVRGATHER_VI_M8_MASK + 0U, // PseudoVRGATHER_VI_MF2 + 0U, // PseudoVRGATHER_VI_MF2_MASK + 0U, // PseudoVRGATHER_VI_MF4 + 0U, // PseudoVRGATHER_VI_MF4_MASK + 0U, // PseudoVRGATHER_VI_MF8 + 0U, // PseudoVRGATHER_VI_MF8_MASK + 0U, // PseudoVRGATHER_VV_M1 + 0U, // PseudoVRGATHER_VV_M1_MASK + 0U, // PseudoVRGATHER_VV_M2 + 0U, // PseudoVRGATHER_VV_M2_MASK + 0U, // PseudoVRGATHER_VV_M4 + 0U, // PseudoVRGATHER_VV_M4_MASK + 0U, // PseudoVRGATHER_VV_M8 + 0U, // PseudoVRGATHER_VV_M8_MASK + 0U, // PseudoVRGATHER_VV_MF2 + 0U, // PseudoVRGATHER_VV_MF2_MASK + 0U, // PseudoVRGATHER_VV_MF4 + 0U, // PseudoVRGATHER_VV_MF4_MASK + 0U, // PseudoVRGATHER_VV_MF8 + 0U, // PseudoVRGATHER_VV_MF8_MASK + 0U, // PseudoVRGATHER_VX_M1 + 0U, // PseudoVRGATHER_VX_M1_MASK + 0U, // PseudoVRGATHER_VX_M2 + 0U, // PseudoVRGATHER_VX_M2_MASK + 0U, // PseudoVRGATHER_VX_M4 + 0U, // PseudoVRGATHER_VX_M4_MASK + 0U, // PseudoVRGATHER_VX_M8 + 0U, // PseudoVRGATHER_VX_M8_MASK + 0U, // PseudoVRGATHER_VX_MF2 + 0U, // PseudoVRGATHER_VX_MF2_MASK + 0U, // PseudoVRGATHER_VX_MF4 + 0U, // PseudoVRGATHER_VX_MF4_MASK + 0U, // PseudoVRGATHER_VX_MF8 + 0U, // PseudoVRGATHER_VX_MF8_MASK + 0U, // PseudoVRSUB_VI_M1 + 0U, // PseudoVRSUB_VI_M1_MASK + 0U, // PseudoVRSUB_VI_M2 + 0U, // PseudoVRSUB_VI_M2_MASK + 0U, // PseudoVRSUB_VI_M4 + 0U, // PseudoVRSUB_VI_M4_MASK + 0U, // PseudoVRSUB_VI_M8 + 0U, // PseudoVRSUB_VI_M8_MASK + 0U, // PseudoVRSUB_VI_MF2 + 0U, // PseudoVRSUB_VI_MF2_MASK + 0U, // PseudoVRSUB_VI_MF4 + 0U, // PseudoVRSUB_VI_MF4_MASK + 0U, // PseudoVRSUB_VI_MF8 + 0U, // PseudoVRSUB_VI_MF8_MASK + 0U, // PseudoVRSUB_VX_M1 + 0U, // PseudoVRSUB_VX_M1_MASK + 0U, // PseudoVRSUB_VX_M2 + 0U, // PseudoVRSUB_VX_M2_MASK + 0U, // PseudoVRSUB_VX_M4 + 0U, // PseudoVRSUB_VX_M4_MASK + 0U, // PseudoVRSUB_VX_M8 + 0U, // PseudoVRSUB_VX_M8_MASK + 0U, // PseudoVRSUB_VX_MF2 + 0U, // PseudoVRSUB_VX_MF2_MASK + 0U, // PseudoVRSUB_VX_MF4 + 0U, // PseudoVRSUB_VX_MF4_MASK + 0U, // PseudoVRSUB_VX_MF8 + 0U, // PseudoVRSUB_VX_MF8_MASK + 0U, // PseudoVSADDU_VI_M1 + 0U, // PseudoVSADDU_VI_M1_MASK + 0U, // PseudoVSADDU_VI_M2 + 0U, // PseudoVSADDU_VI_M2_MASK + 0U, // PseudoVSADDU_VI_M4 + 0U, // PseudoVSADDU_VI_M4_MASK + 0U, // PseudoVSADDU_VI_M8 + 0U, // PseudoVSADDU_VI_M8_MASK + 0U, // PseudoVSADDU_VI_MF2 + 0U, // PseudoVSADDU_VI_MF2_MASK + 0U, // PseudoVSADDU_VI_MF4 + 0U, // PseudoVSADDU_VI_MF4_MASK + 0U, // PseudoVSADDU_VI_MF8 + 0U, // PseudoVSADDU_VI_MF8_MASK + 0U, // PseudoVSADDU_VV_M1 + 0U, // PseudoVSADDU_VV_M1_MASK + 0U, // PseudoVSADDU_VV_M2 + 0U, // PseudoVSADDU_VV_M2_MASK + 0U, // PseudoVSADDU_VV_M4 + 0U, // PseudoVSADDU_VV_M4_MASK + 0U, // PseudoVSADDU_VV_M8 + 0U, // PseudoVSADDU_VV_M8_MASK + 0U, // PseudoVSADDU_VV_MF2 + 0U, // PseudoVSADDU_VV_MF2_MASK + 0U, // PseudoVSADDU_VV_MF4 + 0U, // PseudoVSADDU_VV_MF4_MASK + 0U, // PseudoVSADDU_VV_MF8 + 0U, // PseudoVSADDU_VV_MF8_MASK + 0U, // PseudoVSADDU_VX_M1 + 0U, // PseudoVSADDU_VX_M1_MASK + 0U, // PseudoVSADDU_VX_M2 + 0U, // PseudoVSADDU_VX_M2_MASK + 0U, // PseudoVSADDU_VX_M4 + 0U, // PseudoVSADDU_VX_M4_MASK + 0U, // PseudoVSADDU_VX_M8 + 0U, // PseudoVSADDU_VX_M8_MASK + 0U, // PseudoVSADDU_VX_MF2 + 0U, // PseudoVSADDU_VX_MF2_MASK + 0U, // PseudoVSADDU_VX_MF4 + 0U, // PseudoVSADDU_VX_MF4_MASK + 0U, // PseudoVSADDU_VX_MF8 + 0U, // PseudoVSADDU_VX_MF8_MASK + 0U, // PseudoVSADD_VI_M1 + 0U, // PseudoVSADD_VI_M1_MASK + 0U, // PseudoVSADD_VI_M2 + 0U, // PseudoVSADD_VI_M2_MASK + 0U, // PseudoVSADD_VI_M4 + 0U, // PseudoVSADD_VI_M4_MASK + 0U, // PseudoVSADD_VI_M8 + 0U, // PseudoVSADD_VI_M8_MASK + 0U, // PseudoVSADD_VI_MF2 + 0U, // PseudoVSADD_VI_MF2_MASK + 0U, // PseudoVSADD_VI_MF4 + 0U, // PseudoVSADD_VI_MF4_MASK + 0U, // PseudoVSADD_VI_MF8 + 0U, // PseudoVSADD_VI_MF8_MASK + 0U, // PseudoVSADD_VV_M1 + 0U, // PseudoVSADD_VV_M1_MASK + 0U, // PseudoVSADD_VV_M2 + 0U, // PseudoVSADD_VV_M2_MASK + 0U, // PseudoVSADD_VV_M4 + 0U, // PseudoVSADD_VV_M4_MASK + 0U, // PseudoVSADD_VV_M8 + 0U, // PseudoVSADD_VV_M8_MASK + 0U, // PseudoVSADD_VV_MF2 + 0U, // PseudoVSADD_VV_MF2_MASK + 0U, // PseudoVSADD_VV_MF4 + 0U, // PseudoVSADD_VV_MF4_MASK + 0U, // PseudoVSADD_VV_MF8 + 0U, // PseudoVSADD_VV_MF8_MASK + 0U, // PseudoVSADD_VX_M1 + 0U, // PseudoVSADD_VX_M1_MASK + 0U, // PseudoVSADD_VX_M2 + 0U, // PseudoVSADD_VX_M2_MASK + 0U, // PseudoVSADD_VX_M4 + 0U, // PseudoVSADD_VX_M4_MASK + 0U, // PseudoVSADD_VX_M8 + 0U, // PseudoVSADD_VX_M8_MASK + 0U, // PseudoVSADD_VX_MF2 + 0U, // PseudoVSADD_VX_MF2_MASK + 0U, // PseudoVSADD_VX_MF4 + 0U, // PseudoVSADD_VX_MF4_MASK + 0U, // PseudoVSADD_VX_MF8 + 0U, // PseudoVSADD_VX_MF8_MASK + 0U, // PseudoVSBC_VVM_M1 + 0U, // PseudoVSBC_VVM_M2 + 0U, // PseudoVSBC_VVM_M4 + 0U, // PseudoVSBC_VVM_M8 + 0U, // PseudoVSBC_VVM_MF2 + 0U, // PseudoVSBC_VVM_MF4 + 0U, // PseudoVSBC_VVM_MF8 + 0U, // PseudoVSBC_VXM_M1 + 0U, // PseudoVSBC_VXM_M2 + 0U, // PseudoVSBC_VXM_M4 + 0U, // PseudoVSBC_VXM_M8 + 0U, // PseudoVSBC_VXM_MF2 + 0U, // PseudoVSBC_VXM_MF4 + 0U, // PseudoVSBC_VXM_MF8 + 0U, // PseudoVSE16_V_M1 + 0U, // PseudoVSE16_V_M1_MASK + 0U, // PseudoVSE16_V_M2 + 0U, // PseudoVSE16_V_M2_MASK + 0U, // PseudoVSE16_V_M4 + 0U, // PseudoVSE16_V_M4_MASK + 0U, // PseudoVSE16_V_M8 + 0U, // PseudoVSE16_V_M8_MASK + 0U, // PseudoVSE16_V_MF2 + 0U, // PseudoVSE16_V_MF2_MASK + 0U, // PseudoVSE16_V_MF4 + 0U, // PseudoVSE16_V_MF4_MASK + 0U, // PseudoVSE32_V_M1 + 0U, // PseudoVSE32_V_M1_MASK + 0U, // PseudoVSE32_V_M2 + 0U, // PseudoVSE32_V_M2_MASK + 0U, // PseudoVSE32_V_M4 + 0U, // PseudoVSE32_V_M4_MASK + 0U, // PseudoVSE32_V_M8 + 0U, // PseudoVSE32_V_M8_MASK + 0U, // PseudoVSE32_V_MF2 + 0U, // PseudoVSE32_V_MF2_MASK + 0U, // PseudoVSE64_V_M1 + 0U, // PseudoVSE64_V_M1_MASK + 0U, // PseudoVSE64_V_M2 + 0U, // PseudoVSE64_V_M2_MASK + 0U, // PseudoVSE64_V_M4 + 0U, // PseudoVSE64_V_M4_MASK + 0U, // PseudoVSE64_V_M8 + 0U, // PseudoVSE64_V_M8_MASK + 0U, // PseudoVSE8_V_M1 + 0U, // PseudoVSE8_V_M1_MASK + 0U, // PseudoVSE8_V_M2 + 0U, // PseudoVSE8_V_M2_MASK + 0U, // PseudoVSE8_V_M4 + 0U, // PseudoVSE8_V_M4_MASK + 0U, // PseudoVSE8_V_M8 + 0U, // PseudoVSE8_V_M8_MASK + 0U, // PseudoVSE8_V_MF2 + 0U, // PseudoVSE8_V_MF2_MASK + 0U, // PseudoVSE8_V_MF4 + 0U, // PseudoVSE8_V_MF4_MASK + 0U, // PseudoVSE8_V_MF8 + 0U, // PseudoVSE8_V_MF8_MASK + 0U, // PseudoVSETIVLI + 0U, // PseudoVSETVLI + 0U, // PseudoVSETVLIX0 + 0U, // PseudoVSEXT_VF2_M1 + 0U, // PseudoVSEXT_VF2_M1_MASK + 0U, // PseudoVSEXT_VF2_M2 + 0U, // PseudoVSEXT_VF2_M2_MASK + 0U, // PseudoVSEXT_VF2_M4 + 0U, // PseudoVSEXT_VF2_M4_MASK + 0U, // PseudoVSEXT_VF2_M8 + 0U, // PseudoVSEXT_VF2_M8_MASK + 0U, // PseudoVSEXT_VF2_MF2 + 0U, // PseudoVSEXT_VF2_MF2_MASK + 0U, // PseudoVSEXT_VF2_MF4 + 0U, // PseudoVSEXT_VF2_MF4_MASK + 0U, // PseudoVSEXT_VF4_M1 + 0U, // PseudoVSEXT_VF4_M1_MASK + 0U, // PseudoVSEXT_VF4_M2 + 0U, // PseudoVSEXT_VF4_M2_MASK + 0U, // PseudoVSEXT_VF4_M4 + 0U, // PseudoVSEXT_VF4_M4_MASK + 0U, // PseudoVSEXT_VF4_M8 + 0U, // PseudoVSEXT_VF4_M8_MASK + 0U, // PseudoVSEXT_VF4_MF2 + 0U, // PseudoVSEXT_VF4_MF2_MASK + 0U, // PseudoVSEXT_VF8_M1 + 0U, // PseudoVSEXT_VF8_M1_MASK + 0U, // PseudoVSEXT_VF8_M2 + 0U, // PseudoVSEXT_VF8_M2_MASK + 0U, // PseudoVSEXT_VF8_M4 + 0U, // PseudoVSEXT_VF8_M4_MASK + 0U, // PseudoVSEXT_VF8_M8 + 0U, // PseudoVSEXT_VF8_M8_MASK + 0U, // PseudoVSLIDE1DOWN_VX_M1 + 0U, // PseudoVSLIDE1DOWN_VX_M1_MASK + 0U, // PseudoVSLIDE1DOWN_VX_M2 + 0U, // PseudoVSLIDE1DOWN_VX_M2_MASK + 0U, // PseudoVSLIDE1DOWN_VX_M4 + 0U, // PseudoVSLIDE1DOWN_VX_M4_MASK + 0U, // PseudoVSLIDE1DOWN_VX_M8 + 0U, // PseudoVSLIDE1DOWN_VX_M8_MASK + 0U, // PseudoVSLIDE1DOWN_VX_MF2 + 0U, // PseudoVSLIDE1DOWN_VX_MF2_MASK + 0U, // PseudoVSLIDE1DOWN_VX_MF4 + 0U, // PseudoVSLIDE1DOWN_VX_MF4_MASK + 0U, // PseudoVSLIDE1DOWN_VX_MF8 + 0U, // PseudoVSLIDE1DOWN_VX_MF8_MASK + 0U, // PseudoVSLIDE1UP_VX_M1 + 0U, // PseudoVSLIDE1UP_VX_M1_MASK + 0U, // PseudoVSLIDE1UP_VX_M2 + 0U, // PseudoVSLIDE1UP_VX_M2_MASK + 0U, // PseudoVSLIDE1UP_VX_M4 + 0U, // PseudoVSLIDE1UP_VX_M4_MASK + 0U, // PseudoVSLIDE1UP_VX_M8 + 0U, // PseudoVSLIDE1UP_VX_M8_MASK + 0U, // PseudoVSLIDE1UP_VX_MF2 + 0U, // PseudoVSLIDE1UP_VX_MF2_MASK + 0U, // PseudoVSLIDE1UP_VX_MF4 + 0U, // PseudoVSLIDE1UP_VX_MF4_MASK + 0U, // PseudoVSLIDE1UP_VX_MF8 + 0U, // PseudoVSLIDE1UP_VX_MF8_MASK + 0U, // PseudoVSLIDEDOWN_VI_M1 + 0U, // PseudoVSLIDEDOWN_VI_M1_MASK + 0U, // PseudoVSLIDEDOWN_VI_M2 + 0U, // PseudoVSLIDEDOWN_VI_M2_MASK + 0U, // PseudoVSLIDEDOWN_VI_M4 + 0U, // PseudoVSLIDEDOWN_VI_M4_MASK + 0U, // PseudoVSLIDEDOWN_VI_M8 + 0U, // PseudoVSLIDEDOWN_VI_M8_MASK + 0U, // PseudoVSLIDEDOWN_VI_MF2 + 0U, // PseudoVSLIDEDOWN_VI_MF2_MASK + 0U, // PseudoVSLIDEDOWN_VI_MF4 + 0U, // PseudoVSLIDEDOWN_VI_MF4_MASK + 0U, // PseudoVSLIDEDOWN_VI_MF8 + 0U, // PseudoVSLIDEDOWN_VI_MF8_MASK + 0U, // PseudoVSLIDEDOWN_VX_M1 + 0U, // PseudoVSLIDEDOWN_VX_M1_MASK + 0U, // PseudoVSLIDEDOWN_VX_M2 + 0U, // PseudoVSLIDEDOWN_VX_M2_MASK + 0U, // PseudoVSLIDEDOWN_VX_M4 + 0U, // PseudoVSLIDEDOWN_VX_M4_MASK + 0U, // PseudoVSLIDEDOWN_VX_M8 + 0U, // PseudoVSLIDEDOWN_VX_M8_MASK + 0U, // PseudoVSLIDEDOWN_VX_MF2 + 0U, // PseudoVSLIDEDOWN_VX_MF2_MASK + 0U, // PseudoVSLIDEDOWN_VX_MF4 + 0U, // PseudoVSLIDEDOWN_VX_MF4_MASK + 0U, // PseudoVSLIDEDOWN_VX_MF8 + 0U, // PseudoVSLIDEDOWN_VX_MF8_MASK + 0U, // PseudoVSLIDEUP_VI_M1 + 0U, // PseudoVSLIDEUP_VI_M1_MASK + 0U, // PseudoVSLIDEUP_VI_M2 + 0U, // PseudoVSLIDEUP_VI_M2_MASK + 0U, // PseudoVSLIDEUP_VI_M4 + 0U, // PseudoVSLIDEUP_VI_M4_MASK + 0U, // PseudoVSLIDEUP_VI_M8 + 0U, // PseudoVSLIDEUP_VI_M8_MASK + 0U, // PseudoVSLIDEUP_VI_MF2 + 0U, // PseudoVSLIDEUP_VI_MF2_MASK + 0U, // PseudoVSLIDEUP_VI_MF4 + 0U, // PseudoVSLIDEUP_VI_MF4_MASK + 0U, // PseudoVSLIDEUP_VI_MF8 + 0U, // PseudoVSLIDEUP_VI_MF8_MASK + 0U, // PseudoVSLIDEUP_VX_M1 + 0U, // PseudoVSLIDEUP_VX_M1_MASK + 0U, // PseudoVSLIDEUP_VX_M2 + 0U, // PseudoVSLIDEUP_VX_M2_MASK + 0U, // PseudoVSLIDEUP_VX_M4 + 0U, // PseudoVSLIDEUP_VX_M4_MASK + 0U, // PseudoVSLIDEUP_VX_M8 + 0U, // PseudoVSLIDEUP_VX_M8_MASK + 0U, // PseudoVSLIDEUP_VX_MF2 + 0U, // PseudoVSLIDEUP_VX_MF2_MASK + 0U, // PseudoVSLIDEUP_VX_MF4 + 0U, // PseudoVSLIDEUP_VX_MF4_MASK + 0U, // PseudoVSLIDEUP_VX_MF8 + 0U, // PseudoVSLIDEUP_VX_MF8_MASK + 0U, // PseudoVSLL_VI_M1 + 0U, // PseudoVSLL_VI_M1_MASK + 0U, // PseudoVSLL_VI_M2 + 0U, // PseudoVSLL_VI_M2_MASK + 0U, // PseudoVSLL_VI_M4 + 0U, // PseudoVSLL_VI_M4_MASK + 0U, // PseudoVSLL_VI_M8 + 0U, // PseudoVSLL_VI_M8_MASK + 0U, // PseudoVSLL_VI_MF2 + 0U, // PseudoVSLL_VI_MF2_MASK + 0U, // PseudoVSLL_VI_MF4 + 0U, // PseudoVSLL_VI_MF4_MASK + 0U, // PseudoVSLL_VI_MF8 + 0U, // PseudoVSLL_VI_MF8_MASK + 0U, // PseudoVSLL_VV_M1 + 0U, // PseudoVSLL_VV_M1_MASK + 0U, // PseudoVSLL_VV_M2 + 0U, // PseudoVSLL_VV_M2_MASK + 0U, // PseudoVSLL_VV_M4 + 0U, // PseudoVSLL_VV_M4_MASK + 0U, // PseudoVSLL_VV_M8 + 0U, // PseudoVSLL_VV_M8_MASK + 0U, // PseudoVSLL_VV_MF2 + 0U, // PseudoVSLL_VV_MF2_MASK + 0U, // PseudoVSLL_VV_MF4 + 0U, // PseudoVSLL_VV_MF4_MASK + 0U, // PseudoVSLL_VV_MF8 + 0U, // PseudoVSLL_VV_MF8_MASK + 0U, // PseudoVSLL_VX_M1 + 0U, // PseudoVSLL_VX_M1_MASK + 0U, // PseudoVSLL_VX_M2 + 0U, // PseudoVSLL_VX_M2_MASK + 0U, // PseudoVSLL_VX_M4 + 0U, // PseudoVSLL_VX_M4_MASK + 0U, // PseudoVSLL_VX_M8 + 0U, // PseudoVSLL_VX_M8_MASK + 0U, // PseudoVSLL_VX_MF2 + 0U, // PseudoVSLL_VX_MF2_MASK + 0U, // PseudoVSLL_VX_MF4 + 0U, // PseudoVSLL_VX_MF4_MASK + 0U, // PseudoVSLL_VX_MF8 + 0U, // PseudoVSLL_VX_MF8_MASK + 0U, // PseudoVSMUL_VV_M1 + 0U, // PseudoVSMUL_VV_M1_MASK + 0U, // PseudoVSMUL_VV_M2 + 0U, // PseudoVSMUL_VV_M2_MASK + 0U, // PseudoVSMUL_VV_M4 + 0U, // PseudoVSMUL_VV_M4_MASK + 0U, // PseudoVSMUL_VV_M8 + 0U, // PseudoVSMUL_VV_M8_MASK + 0U, // PseudoVSMUL_VV_MF2 + 0U, // PseudoVSMUL_VV_MF2_MASK + 0U, // PseudoVSMUL_VV_MF4 + 0U, // PseudoVSMUL_VV_MF4_MASK + 0U, // PseudoVSMUL_VV_MF8 + 0U, // PseudoVSMUL_VV_MF8_MASK + 0U, // PseudoVSMUL_VX_M1 + 0U, // PseudoVSMUL_VX_M1_MASK + 0U, // PseudoVSMUL_VX_M2 + 0U, // PseudoVSMUL_VX_M2_MASK + 0U, // PseudoVSMUL_VX_M4 + 0U, // PseudoVSMUL_VX_M4_MASK + 0U, // PseudoVSMUL_VX_M8 + 0U, // PseudoVSMUL_VX_M8_MASK + 0U, // PseudoVSMUL_VX_MF2 + 0U, // PseudoVSMUL_VX_MF2_MASK + 0U, // PseudoVSMUL_VX_MF4 + 0U, // PseudoVSMUL_VX_MF4_MASK + 0U, // PseudoVSMUL_VX_MF8 + 0U, // PseudoVSMUL_VX_MF8_MASK + 0U, // PseudoVSM_V_B1 + 0U, // PseudoVSM_V_B16 + 0U, // PseudoVSM_V_B2 + 0U, // PseudoVSM_V_B32 + 0U, // PseudoVSM_V_B4 + 0U, // PseudoVSM_V_B64 + 0U, // PseudoVSM_V_B8 + 0U, // PseudoVSOXEI16_V_M1_M1 + 0U, // PseudoVSOXEI16_V_M1_M1_MASK + 0U, // PseudoVSOXEI16_V_M1_M2 + 0U, // PseudoVSOXEI16_V_M1_M2_MASK + 0U, // PseudoVSOXEI16_V_M1_M4 + 0U, // PseudoVSOXEI16_V_M1_M4_MASK + 0U, // PseudoVSOXEI16_V_M1_MF2 + 0U, // PseudoVSOXEI16_V_M1_MF2_MASK + 0U, // PseudoVSOXEI16_V_M2_M1 + 0U, // PseudoVSOXEI16_V_M2_M1_MASK + 0U, // PseudoVSOXEI16_V_M2_M2 + 0U, // PseudoVSOXEI16_V_M2_M2_MASK + 0U, // PseudoVSOXEI16_V_M2_M4 + 0U, // PseudoVSOXEI16_V_M2_M4_MASK + 0U, // PseudoVSOXEI16_V_M2_M8 + 0U, // PseudoVSOXEI16_V_M2_M8_MASK + 0U, // PseudoVSOXEI16_V_M4_M2 + 0U, // PseudoVSOXEI16_V_M4_M2_MASK + 0U, // PseudoVSOXEI16_V_M4_M4 + 0U, // PseudoVSOXEI16_V_M4_M4_MASK + 0U, // PseudoVSOXEI16_V_M4_M8 + 0U, // PseudoVSOXEI16_V_M4_M8_MASK + 0U, // PseudoVSOXEI16_V_M8_M4 + 0U, // PseudoVSOXEI16_V_M8_M4_MASK + 0U, // PseudoVSOXEI16_V_M8_M8 + 0U, // PseudoVSOXEI16_V_M8_M8_MASK + 0U, // PseudoVSOXEI16_V_MF2_M1 + 0U, // PseudoVSOXEI16_V_MF2_M1_MASK + 0U, // PseudoVSOXEI16_V_MF2_M2 + 0U, // PseudoVSOXEI16_V_MF2_M2_MASK + 0U, // PseudoVSOXEI16_V_MF2_MF2 + 0U, // PseudoVSOXEI16_V_MF2_MF2_MASK + 0U, // PseudoVSOXEI16_V_MF2_MF4 + 0U, // PseudoVSOXEI16_V_MF2_MF4_MASK + 0U, // PseudoVSOXEI16_V_MF4_M1 + 0U, // PseudoVSOXEI16_V_MF4_M1_MASK + 0U, // PseudoVSOXEI16_V_MF4_MF2 + 0U, // PseudoVSOXEI16_V_MF4_MF2_MASK + 0U, // PseudoVSOXEI16_V_MF4_MF4 + 0U, // PseudoVSOXEI16_V_MF4_MF4_MASK + 0U, // PseudoVSOXEI16_V_MF4_MF8 + 0U, // PseudoVSOXEI16_V_MF4_MF8_MASK + 0U, // PseudoVSOXEI32_V_M1_M1 + 0U, // PseudoVSOXEI32_V_M1_M1_MASK + 0U, // PseudoVSOXEI32_V_M1_M2 + 0U, // PseudoVSOXEI32_V_M1_M2_MASK + 0U, // PseudoVSOXEI32_V_M1_MF2 + 0U, // PseudoVSOXEI32_V_M1_MF2_MASK + 0U, // PseudoVSOXEI32_V_M1_MF4 + 0U, // PseudoVSOXEI32_V_M1_MF4_MASK + 0U, // PseudoVSOXEI32_V_M2_M1 + 0U, // PseudoVSOXEI32_V_M2_M1_MASK + 0U, // PseudoVSOXEI32_V_M2_M2 + 0U, // PseudoVSOXEI32_V_M2_M2_MASK + 0U, // PseudoVSOXEI32_V_M2_M4 + 0U, // PseudoVSOXEI32_V_M2_M4_MASK + 0U, // PseudoVSOXEI32_V_M2_MF2 + 0U, // PseudoVSOXEI32_V_M2_MF2_MASK + 0U, // PseudoVSOXEI32_V_M4_M1 + 0U, // PseudoVSOXEI32_V_M4_M1_MASK + 0U, // PseudoVSOXEI32_V_M4_M2 + 0U, // PseudoVSOXEI32_V_M4_M2_MASK + 0U, // PseudoVSOXEI32_V_M4_M4 + 0U, // PseudoVSOXEI32_V_M4_M4_MASK + 0U, // PseudoVSOXEI32_V_M4_M8 + 0U, // PseudoVSOXEI32_V_M4_M8_MASK + 0U, // PseudoVSOXEI32_V_M8_M2 + 0U, // PseudoVSOXEI32_V_M8_M2_MASK + 0U, // PseudoVSOXEI32_V_M8_M4 + 0U, // PseudoVSOXEI32_V_M8_M4_MASK + 0U, // PseudoVSOXEI32_V_M8_M8 + 0U, // PseudoVSOXEI32_V_M8_M8_MASK + 0U, // PseudoVSOXEI32_V_MF2_M1 + 0U, // PseudoVSOXEI32_V_MF2_M1_MASK + 0U, // PseudoVSOXEI32_V_MF2_MF2 + 0U, // PseudoVSOXEI32_V_MF2_MF2_MASK + 0U, // PseudoVSOXEI32_V_MF2_MF4 + 0U, // PseudoVSOXEI32_V_MF2_MF4_MASK + 0U, // PseudoVSOXEI32_V_MF2_MF8 + 0U, // PseudoVSOXEI32_V_MF2_MF8_MASK + 0U, // PseudoVSOXEI64_V_M1_M1 + 0U, // PseudoVSOXEI64_V_M1_M1_MASK + 0U, // PseudoVSOXEI64_V_M1_MF2 + 0U, // PseudoVSOXEI64_V_M1_MF2_MASK + 0U, // PseudoVSOXEI64_V_M1_MF4 + 0U, // PseudoVSOXEI64_V_M1_MF4_MASK + 0U, // PseudoVSOXEI64_V_M1_MF8 + 0U, // PseudoVSOXEI64_V_M1_MF8_MASK + 0U, // PseudoVSOXEI64_V_M2_M1 + 0U, // PseudoVSOXEI64_V_M2_M1_MASK + 0U, // PseudoVSOXEI64_V_M2_M2 + 0U, // PseudoVSOXEI64_V_M2_M2_MASK + 0U, // PseudoVSOXEI64_V_M2_MF2 + 0U, // PseudoVSOXEI64_V_M2_MF2_MASK + 0U, // PseudoVSOXEI64_V_M2_MF4 + 0U, // PseudoVSOXEI64_V_M2_MF4_MASK + 0U, // PseudoVSOXEI64_V_M4_M1 + 0U, // PseudoVSOXEI64_V_M4_M1_MASK + 0U, // PseudoVSOXEI64_V_M4_M2 + 0U, // PseudoVSOXEI64_V_M4_M2_MASK + 0U, // PseudoVSOXEI64_V_M4_M4 + 0U, // PseudoVSOXEI64_V_M4_M4_MASK + 0U, // PseudoVSOXEI64_V_M4_MF2 + 0U, // PseudoVSOXEI64_V_M4_MF2_MASK + 0U, // PseudoVSOXEI64_V_M8_M1 + 0U, // PseudoVSOXEI64_V_M8_M1_MASK + 0U, // PseudoVSOXEI64_V_M8_M2 + 0U, // PseudoVSOXEI64_V_M8_M2_MASK + 0U, // PseudoVSOXEI64_V_M8_M4 + 0U, // PseudoVSOXEI64_V_M8_M4_MASK + 0U, // PseudoVSOXEI64_V_M8_M8 + 0U, // PseudoVSOXEI64_V_M8_M8_MASK + 0U, // PseudoVSOXEI8_V_M1_M1 + 0U, // PseudoVSOXEI8_V_M1_M1_MASK + 0U, // PseudoVSOXEI8_V_M1_M2 + 0U, // PseudoVSOXEI8_V_M1_M2_MASK + 0U, // PseudoVSOXEI8_V_M1_M4 + 0U, // PseudoVSOXEI8_V_M1_M4_MASK + 0U, // PseudoVSOXEI8_V_M1_M8 + 0U, // PseudoVSOXEI8_V_M1_M8_MASK + 0U, // PseudoVSOXEI8_V_M2_M2 + 0U, // PseudoVSOXEI8_V_M2_M2_MASK + 0U, // PseudoVSOXEI8_V_M2_M4 + 0U, // PseudoVSOXEI8_V_M2_M4_MASK + 0U, // PseudoVSOXEI8_V_M2_M8 + 0U, // PseudoVSOXEI8_V_M2_M8_MASK + 0U, // PseudoVSOXEI8_V_M4_M4 + 0U, // PseudoVSOXEI8_V_M4_M4_MASK + 0U, // PseudoVSOXEI8_V_M4_M8 + 0U, // PseudoVSOXEI8_V_M4_M8_MASK + 0U, // PseudoVSOXEI8_V_M8_M8 + 0U, // PseudoVSOXEI8_V_M8_M8_MASK + 0U, // PseudoVSOXEI8_V_MF2_M1 + 0U, // PseudoVSOXEI8_V_MF2_M1_MASK + 0U, // PseudoVSOXEI8_V_MF2_M2 + 0U, // PseudoVSOXEI8_V_MF2_M2_MASK + 0U, // PseudoVSOXEI8_V_MF2_M4 + 0U, // PseudoVSOXEI8_V_MF2_M4_MASK + 0U, // PseudoVSOXEI8_V_MF2_MF2 + 0U, // PseudoVSOXEI8_V_MF2_MF2_MASK + 0U, // PseudoVSOXEI8_V_MF4_M1 + 0U, // PseudoVSOXEI8_V_MF4_M1_MASK + 0U, // PseudoVSOXEI8_V_MF4_M2 + 0U, // PseudoVSOXEI8_V_MF4_M2_MASK + 0U, // PseudoVSOXEI8_V_MF4_MF2 + 0U, // PseudoVSOXEI8_V_MF4_MF2_MASK + 0U, // PseudoVSOXEI8_V_MF4_MF4 + 0U, // PseudoVSOXEI8_V_MF4_MF4_MASK + 0U, // PseudoVSOXEI8_V_MF8_M1 + 0U, // PseudoVSOXEI8_V_MF8_M1_MASK + 0U, // PseudoVSOXEI8_V_MF8_MF2 + 0U, // PseudoVSOXEI8_V_MF8_MF2_MASK + 0U, // PseudoVSOXEI8_V_MF8_MF4 + 0U, // PseudoVSOXEI8_V_MF8_MF4_MASK + 0U, // PseudoVSOXEI8_V_MF8_MF8 + 0U, // PseudoVSOXEI8_V_MF8_MF8_MASK + 0U, // PseudoVSOXSEG2EI16_V_M1_M1 + 0U, // PseudoVSOXSEG2EI16_V_M1_M1_MASK + 0U, // PseudoVSOXSEG2EI16_V_M1_M2 + 0U, // PseudoVSOXSEG2EI16_V_M1_M2_MASK + 0U, // PseudoVSOXSEG2EI16_V_M1_M4 + 0U, // PseudoVSOXSEG2EI16_V_M1_M4_MASK + 0U, // PseudoVSOXSEG2EI16_V_M1_MF2 + 0U, // PseudoVSOXSEG2EI16_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG2EI16_V_M2_M1 + 0U, // PseudoVSOXSEG2EI16_V_M2_M1_MASK + 0U, // PseudoVSOXSEG2EI16_V_M2_M2 + 0U, // PseudoVSOXSEG2EI16_V_M2_M2_MASK + 0U, // PseudoVSOXSEG2EI16_V_M2_M4 + 0U, // PseudoVSOXSEG2EI16_V_M2_M4_MASK + 0U, // PseudoVSOXSEG2EI16_V_M4_M2 + 0U, // PseudoVSOXSEG2EI16_V_M4_M2_MASK + 0U, // PseudoVSOXSEG2EI16_V_M4_M4 + 0U, // PseudoVSOXSEG2EI16_V_M4_M4_MASK + 0U, // PseudoVSOXSEG2EI16_V_M8_M4 + 0U, // PseudoVSOXSEG2EI16_V_M8_M4_MASK + 0U, // PseudoVSOXSEG2EI16_V_MF2_M1 + 0U, // PseudoVSOXSEG2EI16_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG2EI16_V_MF2_M2 + 0U, // PseudoVSOXSEG2EI16_V_MF2_M2_MASK + 0U, // PseudoVSOXSEG2EI16_V_MF2_MF2 + 0U, // PseudoVSOXSEG2EI16_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG2EI16_V_MF2_MF4 + 0U, // PseudoVSOXSEG2EI16_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG2EI16_V_MF4_M1 + 0U, // PseudoVSOXSEG2EI16_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG2EI16_V_MF4_MF2 + 0U, // PseudoVSOXSEG2EI16_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG2EI16_V_MF4_MF4 + 0U, // PseudoVSOXSEG2EI16_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG2EI16_V_MF4_MF8 + 0U, // PseudoVSOXSEG2EI16_V_MF4_MF8_MASK + 0U, // PseudoVSOXSEG2EI32_V_M1_M1 + 0U, // PseudoVSOXSEG2EI32_V_M1_M1_MASK + 0U, // PseudoVSOXSEG2EI32_V_M1_M2 + 0U, // PseudoVSOXSEG2EI32_V_M1_M2_MASK + 0U, // PseudoVSOXSEG2EI32_V_M1_MF2 + 0U, // PseudoVSOXSEG2EI32_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG2EI32_V_M1_MF4 + 0U, // PseudoVSOXSEG2EI32_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG2EI32_V_M2_M1 + 0U, // PseudoVSOXSEG2EI32_V_M2_M1_MASK + 0U, // PseudoVSOXSEG2EI32_V_M2_M2 + 0U, // PseudoVSOXSEG2EI32_V_M2_M2_MASK + 0U, // PseudoVSOXSEG2EI32_V_M2_M4 + 0U, // PseudoVSOXSEG2EI32_V_M2_M4_MASK + 0U, // PseudoVSOXSEG2EI32_V_M2_MF2 + 0U, // PseudoVSOXSEG2EI32_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG2EI32_V_M4_M1 + 0U, // PseudoVSOXSEG2EI32_V_M4_M1_MASK + 0U, // PseudoVSOXSEG2EI32_V_M4_M2 + 0U, // PseudoVSOXSEG2EI32_V_M4_M2_MASK + 0U, // PseudoVSOXSEG2EI32_V_M4_M4 + 0U, // PseudoVSOXSEG2EI32_V_M4_M4_MASK + 0U, // PseudoVSOXSEG2EI32_V_M8_M2 + 0U, // PseudoVSOXSEG2EI32_V_M8_M2_MASK + 0U, // PseudoVSOXSEG2EI32_V_M8_M4 + 0U, // PseudoVSOXSEG2EI32_V_M8_M4_MASK + 0U, // PseudoVSOXSEG2EI32_V_MF2_M1 + 0U, // PseudoVSOXSEG2EI32_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG2EI32_V_MF2_MF2 + 0U, // PseudoVSOXSEG2EI32_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG2EI32_V_MF2_MF4 + 0U, // PseudoVSOXSEG2EI32_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG2EI32_V_MF2_MF8 + 0U, // PseudoVSOXSEG2EI32_V_MF2_MF8_MASK + 0U, // PseudoVSOXSEG2EI64_V_M1_M1 + 0U, // PseudoVSOXSEG2EI64_V_M1_M1_MASK + 0U, // PseudoVSOXSEG2EI64_V_M1_MF2 + 0U, // PseudoVSOXSEG2EI64_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG2EI64_V_M1_MF4 + 0U, // PseudoVSOXSEG2EI64_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG2EI64_V_M1_MF8 + 0U, // PseudoVSOXSEG2EI64_V_M1_MF8_MASK + 0U, // PseudoVSOXSEG2EI64_V_M2_M1 + 0U, // PseudoVSOXSEG2EI64_V_M2_M1_MASK + 0U, // PseudoVSOXSEG2EI64_V_M2_M2 + 0U, // PseudoVSOXSEG2EI64_V_M2_M2_MASK + 0U, // PseudoVSOXSEG2EI64_V_M2_MF2 + 0U, // PseudoVSOXSEG2EI64_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG2EI64_V_M2_MF4 + 0U, // PseudoVSOXSEG2EI64_V_M2_MF4_MASK + 0U, // PseudoVSOXSEG2EI64_V_M4_M1 + 0U, // PseudoVSOXSEG2EI64_V_M4_M1_MASK + 0U, // PseudoVSOXSEG2EI64_V_M4_M2 + 0U, // PseudoVSOXSEG2EI64_V_M4_M2_MASK + 0U, // PseudoVSOXSEG2EI64_V_M4_M4 + 0U, // PseudoVSOXSEG2EI64_V_M4_M4_MASK + 0U, // PseudoVSOXSEG2EI64_V_M4_MF2 + 0U, // PseudoVSOXSEG2EI64_V_M4_MF2_MASK + 0U, // PseudoVSOXSEG2EI64_V_M8_M1 + 0U, // PseudoVSOXSEG2EI64_V_M8_M1_MASK + 0U, // PseudoVSOXSEG2EI64_V_M8_M2 + 0U, // PseudoVSOXSEG2EI64_V_M8_M2_MASK + 0U, // PseudoVSOXSEG2EI64_V_M8_M4 + 0U, // PseudoVSOXSEG2EI64_V_M8_M4_MASK + 0U, // PseudoVSOXSEG2EI8_V_M1_M1 + 0U, // PseudoVSOXSEG2EI8_V_M1_M1_MASK + 0U, // PseudoVSOXSEG2EI8_V_M1_M2 + 0U, // PseudoVSOXSEG2EI8_V_M1_M2_MASK + 0U, // PseudoVSOXSEG2EI8_V_M1_M4 + 0U, // PseudoVSOXSEG2EI8_V_M1_M4_MASK + 0U, // PseudoVSOXSEG2EI8_V_M2_M2 + 0U, // PseudoVSOXSEG2EI8_V_M2_M2_MASK + 0U, // PseudoVSOXSEG2EI8_V_M2_M4 + 0U, // PseudoVSOXSEG2EI8_V_M2_M4_MASK + 0U, // PseudoVSOXSEG2EI8_V_M4_M4 + 0U, // PseudoVSOXSEG2EI8_V_M4_M4_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF2_M1 + 0U, // PseudoVSOXSEG2EI8_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF2_M2 + 0U, // PseudoVSOXSEG2EI8_V_MF2_M2_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF2_M4 + 0U, // PseudoVSOXSEG2EI8_V_MF2_M4_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF2_MF2 + 0U, // PseudoVSOXSEG2EI8_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF4_M1 + 0U, // PseudoVSOXSEG2EI8_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF4_M2 + 0U, // PseudoVSOXSEG2EI8_V_MF4_M2_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF4_MF2 + 0U, // PseudoVSOXSEG2EI8_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF4_MF4 + 0U, // PseudoVSOXSEG2EI8_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF8_M1 + 0U, // PseudoVSOXSEG2EI8_V_MF8_M1_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF8_MF2 + 0U, // PseudoVSOXSEG2EI8_V_MF8_MF2_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF8_MF4 + 0U, // PseudoVSOXSEG2EI8_V_MF8_MF4_MASK + 0U, // PseudoVSOXSEG2EI8_V_MF8_MF8 + 0U, // PseudoVSOXSEG2EI8_V_MF8_MF8_MASK + 0U, // PseudoVSOXSEG3EI16_V_M1_M1 + 0U, // PseudoVSOXSEG3EI16_V_M1_M1_MASK + 0U, // PseudoVSOXSEG3EI16_V_M1_M2 + 0U, // PseudoVSOXSEG3EI16_V_M1_M2_MASK + 0U, // PseudoVSOXSEG3EI16_V_M1_MF2 + 0U, // PseudoVSOXSEG3EI16_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG3EI16_V_M2_M1 + 0U, // PseudoVSOXSEG3EI16_V_M2_M1_MASK + 0U, // PseudoVSOXSEG3EI16_V_M2_M2 + 0U, // PseudoVSOXSEG3EI16_V_M2_M2_MASK + 0U, // PseudoVSOXSEG3EI16_V_M4_M2 + 0U, // PseudoVSOXSEG3EI16_V_M4_M2_MASK + 0U, // PseudoVSOXSEG3EI16_V_MF2_M1 + 0U, // PseudoVSOXSEG3EI16_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG3EI16_V_MF2_M2 + 0U, // PseudoVSOXSEG3EI16_V_MF2_M2_MASK + 0U, // PseudoVSOXSEG3EI16_V_MF2_MF2 + 0U, // PseudoVSOXSEG3EI16_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG3EI16_V_MF2_MF4 + 0U, // PseudoVSOXSEG3EI16_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG3EI16_V_MF4_M1 + 0U, // PseudoVSOXSEG3EI16_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG3EI16_V_MF4_MF2 + 0U, // PseudoVSOXSEG3EI16_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG3EI16_V_MF4_MF4 + 0U, // PseudoVSOXSEG3EI16_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG3EI16_V_MF4_MF8 + 0U, // PseudoVSOXSEG3EI16_V_MF4_MF8_MASK + 0U, // PseudoVSOXSEG3EI32_V_M1_M1 + 0U, // PseudoVSOXSEG3EI32_V_M1_M1_MASK + 0U, // PseudoVSOXSEG3EI32_V_M1_M2 + 0U, // PseudoVSOXSEG3EI32_V_M1_M2_MASK + 0U, // PseudoVSOXSEG3EI32_V_M1_MF2 + 0U, // PseudoVSOXSEG3EI32_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG3EI32_V_M1_MF4 + 0U, // PseudoVSOXSEG3EI32_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG3EI32_V_M2_M1 + 0U, // PseudoVSOXSEG3EI32_V_M2_M1_MASK + 0U, // PseudoVSOXSEG3EI32_V_M2_M2 + 0U, // PseudoVSOXSEG3EI32_V_M2_M2_MASK + 0U, // PseudoVSOXSEG3EI32_V_M2_MF2 + 0U, // PseudoVSOXSEG3EI32_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG3EI32_V_M4_M1 + 0U, // PseudoVSOXSEG3EI32_V_M4_M1_MASK + 0U, // PseudoVSOXSEG3EI32_V_M4_M2 + 0U, // PseudoVSOXSEG3EI32_V_M4_M2_MASK + 0U, // PseudoVSOXSEG3EI32_V_M8_M2 + 0U, // PseudoVSOXSEG3EI32_V_M8_M2_MASK + 0U, // PseudoVSOXSEG3EI32_V_MF2_M1 + 0U, // PseudoVSOXSEG3EI32_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG3EI32_V_MF2_MF2 + 0U, // PseudoVSOXSEG3EI32_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG3EI32_V_MF2_MF4 + 0U, // PseudoVSOXSEG3EI32_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG3EI32_V_MF2_MF8 + 0U, // PseudoVSOXSEG3EI32_V_MF2_MF8_MASK + 0U, // PseudoVSOXSEG3EI64_V_M1_M1 + 0U, // PseudoVSOXSEG3EI64_V_M1_M1_MASK + 0U, // PseudoVSOXSEG3EI64_V_M1_MF2 + 0U, // PseudoVSOXSEG3EI64_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG3EI64_V_M1_MF4 + 0U, // PseudoVSOXSEG3EI64_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG3EI64_V_M1_MF8 + 0U, // PseudoVSOXSEG3EI64_V_M1_MF8_MASK + 0U, // PseudoVSOXSEG3EI64_V_M2_M1 + 0U, // PseudoVSOXSEG3EI64_V_M2_M1_MASK + 0U, // PseudoVSOXSEG3EI64_V_M2_M2 + 0U, // PseudoVSOXSEG3EI64_V_M2_M2_MASK + 0U, // PseudoVSOXSEG3EI64_V_M2_MF2 + 0U, // PseudoVSOXSEG3EI64_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG3EI64_V_M2_MF4 + 0U, // PseudoVSOXSEG3EI64_V_M2_MF4_MASK + 0U, // PseudoVSOXSEG3EI64_V_M4_M1 + 0U, // PseudoVSOXSEG3EI64_V_M4_M1_MASK + 0U, // PseudoVSOXSEG3EI64_V_M4_M2 + 0U, // PseudoVSOXSEG3EI64_V_M4_M2_MASK + 0U, // PseudoVSOXSEG3EI64_V_M4_MF2 + 0U, // PseudoVSOXSEG3EI64_V_M4_MF2_MASK + 0U, // PseudoVSOXSEG3EI64_V_M8_M1 + 0U, // PseudoVSOXSEG3EI64_V_M8_M1_MASK + 0U, // PseudoVSOXSEG3EI64_V_M8_M2 + 0U, // PseudoVSOXSEG3EI64_V_M8_M2_MASK + 0U, // PseudoVSOXSEG3EI8_V_M1_M1 + 0U, // PseudoVSOXSEG3EI8_V_M1_M1_MASK + 0U, // PseudoVSOXSEG3EI8_V_M1_M2 + 0U, // PseudoVSOXSEG3EI8_V_M1_M2_MASK + 0U, // PseudoVSOXSEG3EI8_V_M2_M2 + 0U, // PseudoVSOXSEG3EI8_V_M2_M2_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF2_M1 + 0U, // PseudoVSOXSEG3EI8_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF2_M2 + 0U, // PseudoVSOXSEG3EI8_V_MF2_M2_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF2_MF2 + 0U, // PseudoVSOXSEG3EI8_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF4_M1 + 0U, // PseudoVSOXSEG3EI8_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF4_M2 + 0U, // PseudoVSOXSEG3EI8_V_MF4_M2_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF4_MF2 + 0U, // PseudoVSOXSEG3EI8_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF4_MF4 + 0U, // PseudoVSOXSEG3EI8_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF8_M1 + 0U, // PseudoVSOXSEG3EI8_V_MF8_M1_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF8_MF2 + 0U, // PseudoVSOXSEG3EI8_V_MF8_MF2_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF8_MF4 + 0U, // PseudoVSOXSEG3EI8_V_MF8_MF4_MASK + 0U, // PseudoVSOXSEG3EI8_V_MF8_MF8 + 0U, // PseudoVSOXSEG3EI8_V_MF8_MF8_MASK + 0U, // PseudoVSOXSEG4EI16_V_M1_M1 + 0U, // PseudoVSOXSEG4EI16_V_M1_M1_MASK + 0U, // PseudoVSOXSEG4EI16_V_M1_M2 + 0U, // PseudoVSOXSEG4EI16_V_M1_M2_MASK + 0U, // PseudoVSOXSEG4EI16_V_M1_MF2 + 0U, // PseudoVSOXSEG4EI16_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG4EI16_V_M2_M1 + 0U, // PseudoVSOXSEG4EI16_V_M2_M1_MASK + 0U, // PseudoVSOXSEG4EI16_V_M2_M2 + 0U, // PseudoVSOXSEG4EI16_V_M2_M2_MASK + 0U, // PseudoVSOXSEG4EI16_V_M4_M2 + 0U, // PseudoVSOXSEG4EI16_V_M4_M2_MASK + 0U, // PseudoVSOXSEG4EI16_V_MF2_M1 + 0U, // PseudoVSOXSEG4EI16_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG4EI16_V_MF2_M2 + 0U, // PseudoVSOXSEG4EI16_V_MF2_M2_MASK + 0U, // PseudoVSOXSEG4EI16_V_MF2_MF2 + 0U, // PseudoVSOXSEG4EI16_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG4EI16_V_MF2_MF4 + 0U, // PseudoVSOXSEG4EI16_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG4EI16_V_MF4_M1 + 0U, // PseudoVSOXSEG4EI16_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG4EI16_V_MF4_MF2 + 0U, // PseudoVSOXSEG4EI16_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG4EI16_V_MF4_MF4 + 0U, // PseudoVSOXSEG4EI16_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG4EI16_V_MF4_MF8 + 0U, // PseudoVSOXSEG4EI16_V_MF4_MF8_MASK + 0U, // PseudoVSOXSEG4EI32_V_M1_M1 + 0U, // PseudoVSOXSEG4EI32_V_M1_M1_MASK + 0U, // PseudoVSOXSEG4EI32_V_M1_M2 + 0U, // PseudoVSOXSEG4EI32_V_M1_M2_MASK + 0U, // PseudoVSOXSEG4EI32_V_M1_MF2 + 0U, // PseudoVSOXSEG4EI32_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG4EI32_V_M1_MF4 + 0U, // PseudoVSOXSEG4EI32_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG4EI32_V_M2_M1 + 0U, // PseudoVSOXSEG4EI32_V_M2_M1_MASK + 0U, // PseudoVSOXSEG4EI32_V_M2_M2 + 0U, // PseudoVSOXSEG4EI32_V_M2_M2_MASK + 0U, // PseudoVSOXSEG4EI32_V_M2_MF2 + 0U, // PseudoVSOXSEG4EI32_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG4EI32_V_M4_M1 + 0U, // PseudoVSOXSEG4EI32_V_M4_M1_MASK + 0U, // PseudoVSOXSEG4EI32_V_M4_M2 + 0U, // PseudoVSOXSEG4EI32_V_M4_M2_MASK + 0U, // PseudoVSOXSEG4EI32_V_M8_M2 + 0U, // PseudoVSOXSEG4EI32_V_M8_M2_MASK + 0U, // PseudoVSOXSEG4EI32_V_MF2_M1 + 0U, // PseudoVSOXSEG4EI32_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG4EI32_V_MF2_MF2 + 0U, // PseudoVSOXSEG4EI32_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG4EI32_V_MF2_MF4 + 0U, // PseudoVSOXSEG4EI32_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG4EI32_V_MF2_MF8 + 0U, // PseudoVSOXSEG4EI32_V_MF2_MF8_MASK + 0U, // PseudoVSOXSEG4EI64_V_M1_M1 + 0U, // PseudoVSOXSEG4EI64_V_M1_M1_MASK + 0U, // PseudoVSOXSEG4EI64_V_M1_MF2 + 0U, // PseudoVSOXSEG4EI64_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG4EI64_V_M1_MF4 + 0U, // PseudoVSOXSEG4EI64_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG4EI64_V_M1_MF8 + 0U, // PseudoVSOXSEG4EI64_V_M1_MF8_MASK + 0U, // PseudoVSOXSEG4EI64_V_M2_M1 + 0U, // PseudoVSOXSEG4EI64_V_M2_M1_MASK + 0U, // PseudoVSOXSEG4EI64_V_M2_M2 + 0U, // PseudoVSOXSEG4EI64_V_M2_M2_MASK + 0U, // PseudoVSOXSEG4EI64_V_M2_MF2 + 0U, // PseudoVSOXSEG4EI64_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG4EI64_V_M2_MF4 + 0U, // PseudoVSOXSEG4EI64_V_M2_MF4_MASK + 0U, // PseudoVSOXSEG4EI64_V_M4_M1 + 0U, // PseudoVSOXSEG4EI64_V_M4_M1_MASK + 0U, // PseudoVSOXSEG4EI64_V_M4_M2 + 0U, // PseudoVSOXSEG4EI64_V_M4_M2_MASK + 0U, // PseudoVSOXSEG4EI64_V_M4_MF2 + 0U, // PseudoVSOXSEG4EI64_V_M4_MF2_MASK + 0U, // PseudoVSOXSEG4EI64_V_M8_M1 + 0U, // PseudoVSOXSEG4EI64_V_M8_M1_MASK + 0U, // PseudoVSOXSEG4EI64_V_M8_M2 + 0U, // PseudoVSOXSEG4EI64_V_M8_M2_MASK + 0U, // PseudoVSOXSEG4EI8_V_M1_M1 + 0U, // PseudoVSOXSEG4EI8_V_M1_M1_MASK + 0U, // PseudoVSOXSEG4EI8_V_M1_M2 + 0U, // PseudoVSOXSEG4EI8_V_M1_M2_MASK + 0U, // PseudoVSOXSEG4EI8_V_M2_M2 + 0U, // PseudoVSOXSEG4EI8_V_M2_M2_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF2_M1 + 0U, // PseudoVSOXSEG4EI8_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF2_M2 + 0U, // PseudoVSOXSEG4EI8_V_MF2_M2_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF2_MF2 + 0U, // PseudoVSOXSEG4EI8_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF4_M1 + 0U, // PseudoVSOXSEG4EI8_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF4_M2 + 0U, // PseudoVSOXSEG4EI8_V_MF4_M2_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF4_MF2 + 0U, // PseudoVSOXSEG4EI8_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF4_MF4 + 0U, // PseudoVSOXSEG4EI8_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF8_M1 + 0U, // PseudoVSOXSEG4EI8_V_MF8_M1_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF8_MF2 + 0U, // PseudoVSOXSEG4EI8_V_MF8_MF2_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF8_MF4 + 0U, // PseudoVSOXSEG4EI8_V_MF8_MF4_MASK + 0U, // PseudoVSOXSEG4EI8_V_MF8_MF8 + 0U, // PseudoVSOXSEG4EI8_V_MF8_MF8_MASK + 0U, // PseudoVSOXSEG5EI16_V_M1_M1 + 0U, // PseudoVSOXSEG5EI16_V_M1_M1_MASK + 0U, // PseudoVSOXSEG5EI16_V_M1_MF2 + 0U, // PseudoVSOXSEG5EI16_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG5EI16_V_M2_M1 + 0U, // PseudoVSOXSEG5EI16_V_M2_M1_MASK + 0U, // PseudoVSOXSEG5EI16_V_MF2_M1 + 0U, // PseudoVSOXSEG5EI16_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG5EI16_V_MF2_MF2 + 0U, // PseudoVSOXSEG5EI16_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG5EI16_V_MF2_MF4 + 0U, // PseudoVSOXSEG5EI16_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG5EI16_V_MF4_M1 + 0U, // PseudoVSOXSEG5EI16_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG5EI16_V_MF4_MF2 + 0U, // PseudoVSOXSEG5EI16_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG5EI16_V_MF4_MF4 + 0U, // PseudoVSOXSEG5EI16_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG5EI16_V_MF4_MF8 + 0U, // PseudoVSOXSEG5EI16_V_MF4_MF8_MASK + 0U, // PseudoVSOXSEG5EI32_V_M1_M1 + 0U, // PseudoVSOXSEG5EI32_V_M1_M1_MASK + 0U, // PseudoVSOXSEG5EI32_V_M1_MF2 + 0U, // PseudoVSOXSEG5EI32_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG5EI32_V_M1_MF4 + 0U, // PseudoVSOXSEG5EI32_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG5EI32_V_M2_M1 + 0U, // PseudoVSOXSEG5EI32_V_M2_M1_MASK + 0U, // PseudoVSOXSEG5EI32_V_M2_MF2 + 0U, // PseudoVSOXSEG5EI32_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG5EI32_V_M4_M1 + 0U, // PseudoVSOXSEG5EI32_V_M4_M1_MASK + 0U, // PseudoVSOXSEG5EI32_V_MF2_M1 + 0U, // PseudoVSOXSEG5EI32_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG5EI32_V_MF2_MF2 + 0U, // PseudoVSOXSEG5EI32_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG5EI32_V_MF2_MF4 + 0U, // PseudoVSOXSEG5EI32_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG5EI32_V_MF2_MF8 + 0U, // PseudoVSOXSEG5EI32_V_MF2_MF8_MASK + 0U, // PseudoVSOXSEG5EI64_V_M1_M1 + 0U, // PseudoVSOXSEG5EI64_V_M1_M1_MASK + 0U, // PseudoVSOXSEG5EI64_V_M1_MF2 + 0U, // PseudoVSOXSEG5EI64_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG5EI64_V_M1_MF4 + 0U, // PseudoVSOXSEG5EI64_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG5EI64_V_M1_MF8 + 0U, // PseudoVSOXSEG5EI64_V_M1_MF8_MASK + 0U, // PseudoVSOXSEG5EI64_V_M2_M1 + 0U, // PseudoVSOXSEG5EI64_V_M2_M1_MASK + 0U, // PseudoVSOXSEG5EI64_V_M2_MF2 + 0U, // PseudoVSOXSEG5EI64_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG5EI64_V_M2_MF4 + 0U, // PseudoVSOXSEG5EI64_V_M2_MF4_MASK + 0U, // PseudoVSOXSEG5EI64_V_M4_M1 + 0U, // PseudoVSOXSEG5EI64_V_M4_M1_MASK + 0U, // PseudoVSOXSEG5EI64_V_M4_MF2 + 0U, // PseudoVSOXSEG5EI64_V_M4_MF2_MASK + 0U, // PseudoVSOXSEG5EI64_V_M8_M1 + 0U, // PseudoVSOXSEG5EI64_V_M8_M1_MASK + 0U, // PseudoVSOXSEG5EI8_V_M1_M1 + 0U, // PseudoVSOXSEG5EI8_V_M1_M1_MASK + 0U, // PseudoVSOXSEG5EI8_V_MF2_M1 + 0U, // PseudoVSOXSEG5EI8_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG5EI8_V_MF2_MF2 + 0U, // PseudoVSOXSEG5EI8_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG5EI8_V_MF4_M1 + 0U, // PseudoVSOXSEG5EI8_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG5EI8_V_MF4_MF2 + 0U, // PseudoVSOXSEG5EI8_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG5EI8_V_MF4_MF4 + 0U, // PseudoVSOXSEG5EI8_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG5EI8_V_MF8_M1 + 0U, // PseudoVSOXSEG5EI8_V_MF8_M1_MASK + 0U, // PseudoVSOXSEG5EI8_V_MF8_MF2 + 0U, // PseudoVSOXSEG5EI8_V_MF8_MF2_MASK + 0U, // PseudoVSOXSEG5EI8_V_MF8_MF4 + 0U, // PseudoVSOXSEG5EI8_V_MF8_MF4_MASK + 0U, // PseudoVSOXSEG5EI8_V_MF8_MF8 + 0U, // PseudoVSOXSEG5EI8_V_MF8_MF8_MASK + 0U, // PseudoVSOXSEG6EI16_V_M1_M1 + 0U, // PseudoVSOXSEG6EI16_V_M1_M1_MASK + 0U, // PseudoVSOXSEG6EI16_V_M1_MF2 + 0U, // PseudoVSOXSEG6EI16_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG6EI16_V_M2_M1 + 0U, // PseudoVSOXSEG6EI16_V_M2_M1_MASK + 0U, // PseudoVSOXSEG6EI16_V_MF2_M1 + 0U, // PseudoVSOXSEG6EI16_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG6EI16_V_MF2_MF2 + 0U, // PseudoVSOXSEG6EI16_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG6EI16_V_MF2_MF4 + 0U, // PseudoVSOXSEG6EI16_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG6EI16_V_MF4_M1 + 0U, // PseudoVSOXSEG6EI16_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG6EI16_V_MF4_MF2 + 0U, // PseudoVSOXSEG6EI16_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG6EI16_V_MF4_MF4 + 0U, // PseudoVSOXSEG6EI16_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG6EI16_V_MF4_MF8 + 0U, // PseudoVSOXSEG6EI16_V_MF4_MF8_MASK + 0U, // PseudoVSOXSEG6EI32_V_M1_M1 + 0U, // PseudoVSOXSEG6EI32_V_M1_M1_MASK + 0U, // PseudoVSOXSEG6EI32_V_M1_MF2 + 0U, // PseudoVSOXSEG6EI32_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG6EI32_V_M1_MF4 + 0U, // PseudoVSOXSEG6EI32_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG6EI32_V_M2_M1 + 0U, // PseudoVSOXSEG6EI32_V_M2_M1_MASK + 0U, // PseudoVSOXSEG6EI32_V_M2_MF2 + 0U, // PseudoVSOXSEG6EI32_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG6EI32_V_M4_M1 + 0U, // PseudoVSOXSEG6EI32_V_M4_M1_MASK + 0U, // PseudoVSOXSEG6EI32_V_MF2_M1 + 0U, // PseudoVSOXSEG6EI32_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG6EI32_V_MF2_MF2 + 0U, // PseudoVSOXSEG6EI32_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG6EI32_V_MF2_MF4 + 0U, // PseudoVSOXSEG6EI32_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG6EI32_V_MF2_MF8 + 0U, // PseudoVSOXSEG6EI32_V_MF2_MF8_MASK + 0U, // PseudoVSOXSEG6EI64_V_M1_M1 + 0U, // PseudoVSOXSEG6EI64_V_M1_M1_MASK + 0U, // PseudoVSOXSEG6EI64_V_M1_MF2 + 0U, // PseudoVSOXSEG6EI64_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG6EI64_V_M1_MF4 + 0U, // PseudoVSOXSEG6EI64_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG6EI64_V_M1_MF8 + 0U, // PseudoVSOXSEG6EI64_V_M1_MF8_MASK + 0U, // PseudoVSOXSEG6EI64_V_M2_M1 + 0U, // PseudoVSOXSEG6EI64_V_M2_M1_MASK + 0U, // PseudoVSOXSEG6EI64_V_M2_MF2 + 0U, // PseudoVSOXSEG6EI64_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG6EI64_V_M2_MF4 + 0U, // PseudoVSOXSEG6EI64_V_M2_MF4_MASK + 0U, // PseudoVSOXSEG6EI64_V_M4_M1 + 0U, // PseudoVSOXSEG6EI64_V_M4_M1_MASK + 0U, // PseudoVSOXSEG6EI64_V_M4_MF2 + 0U, // PseudoVSOXSEG6EI64_V_M4_MF2_MASK + 0U, // PseudoVSOXSEG6EI64_V_M8_M1 + 0U, // PseudoVSOXSEG6EI64_V_M8_M1_MASK + 0U, // PseudoVSOXSEG6EI8_V_M1_M1 + 0U, // PseudoVSOXSEG6EI8_V_M1_M1_MASK + 0U, // PseudoVSOXSEG6EI8_V_MF2_M1 + 0U, // PseudoVSOXSEG6EI8_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG6EI8_V_MF2_MF2 + 0U, // PseudoVSOXSEG6EI8_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG6EI8_V_MF4_M1 + 0U, // PseudoVSOXSEG6EI8_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG6EI8_V_MF4_MF2 + 0U, // PseudoVSOXSEG6EI8_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG6EI8_V_MF4_MF4 + 0U, // PseudoVSOXSEG6EI8_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG6EI8_V_MF8_M1 + 0U, // PseudoVSOXSEG6EI8_V_MF8_M1_MASK + 0U, // PseudoVSOXSEG6EI8_V_MF8_MF2 + 0U, // PseudoVSOXSEG6EI8_V_MF8_MF2_MASK + 0U, // PseudoVSOXSEG6EI8_V_MF8_MF4 + 0U, // PseudoVSOXSEG6EI8_V_MF8_MF4_MASK + 0U, // PseudoVSOXSEG6EI8_V_MF8_MF8 + 0U, // PseudoVSOXSEG6EI8_V_MF8_MF8_MASK + 0U, // PseudoVSOXSEG7EI16_V_M1_M1 + 0U, // PseudoVSOXSEG7EI16_V_M1_M1_MASK + 0U, // PseudoVSOXSEG7EI16_V_M1_MF2 + 0U, // PseudoVSOXSEG7EI16_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG7EI16_V_M2_M1 + 0U, // PseudoVSOXSEG7EI16_V_M2_M1_MASK + 0U, // PseudoVSOXSEG7EI16_V_MF2_M1 + 0U, // PseudoVSOXSEG7EI16_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG7EI16_V_MF2_MF2 + 0U, // PseudoVSOXSEG7EI16_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG7EI16_V_MF2_MF4 + 0U, // PseudoVSOXSEG7EI16_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG7EI16_V_MF4_M1 + 0U, // PseudoVSOXSEG7EI16_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG7EI16_V_MF4_MF2 + 0U, // PseudoVSOXSEG7EI16_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG7EI16_V_MF4_MF4 + 0U, // PseudoVSOXSEG7EI16_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG7EI16_V_MF4_MF8 + 0U, // PseudoVSOXSEG7EI16_V_MF4_MF8_MASK + 0U, // PseudoVSOXSEG7EI32_V_M1_M1 + 0U, // PseudoVSOXSEG7EI32_V_M1_M1_MASK + 0U, // PseudoVSOXSEG7EI32_V_M1_MF2 + 0U, // PseudoVSOXSEG7EI32_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG7EI32_V_M1_MF4 + 0U, // PseudoVSOXSEG7EI32_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG7EI32_V_M2_M1 + 0U, // PseudoVSOXSEG7EI32_V_M2_M1_MASK + 0U, // PseudoVSOXSEG7EI32_V_M2_MF2 + 0U, // PseudoVSOXSEG7EI32_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG7EI32_V_M4_M1 + 0U, // PseudoVSOXSEG7EI32_V_M4_M1_MASK + 0U, // PseudoVSOXSEG7EI32_V_MF2_M1 + 0U, // PseudoVSOXSEG7EI32_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG7EI32_V_MF2_MF2 + 0U, // PseudoVSOXSEG7EI32_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG7EI32_V_MF2_MF4 + 0U, // PseudoVSOXSEG7EI32_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG7EI32_V_MF2_MF8 + 0U, // PseudoVSOXSEG7EI32_V_MF2_MF8_MASK + 0U, // PseudoVSOXSEG7EI64_V_M1_M1 + 0U, // PseudoVSOXSEG7EI64_V_M1_M1_MASK + 0U, // PseudoVSOXSEG7EI64_V_M1_MF2 + 0U, // PseudoVSOXSEG7EI64_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG7EI64_V_M1_MF4 + 0U, // PseudoVSOXSEG7EI64_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG7EI64_V_M1_MF8 + 0U, // PseudoVSOXSEG7EI64_V_M1_MF8_MASK + 0U, // PseudoVSOXSEG7EI64_V_M2_M1 + 0U, // PseudoVSOXSEG7EI64_V_M2_M1_MASK + 0U, // PseudoVSOXSEG7EI64_V_M2_MF2 + 0U, // PseudoVSOXSEG7EI64_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG7EI64_V_M2_MF4 + 0U, // PseudoVSOXSEG7EI64_V_M2_MF4_MASK + 0U, // PseudoVSOXSEG7EI64_V_M4_M1 + 0U, // PseudoVSOXSEG7EI64_V_M4_M1_MASK + 0U, // PseudoVSOXSEG7EI64_V_M4_MF2 + 0U, // PseudoVSOXSEG7EI64_V_M4_MF2_MASK + 0U, // PseudoVSOXSEG7EI64_V_M8_M1 + 0U, // PseudoVSOXSEG7EI64_V_M8_M1_MASK + 0U, // PseudoVSOXSEG7EI8_V_M1_M1 + 0U, // PseudoVSOXSEG7EI8_V_M1_M1_MASK + 0U, // PseudoVSOXSEG7EI8_V_MF2_M1 + 0U, // PseudoVSOXSEG7EI8_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG7EI8_V_MF2_MF2 + 0U, // PseudoVSOXSEG7EI8_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG7EI8_V_MF4_M1 + 0U, // PseudoVSOXSEG7EI8_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG7EI8_V_MF4_MF2 + 0U, // PseudoVSOXSEG7EI8_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG7EI8_V_MF4_MF4 + 0U, // PseudoVSOXSEG7EI8_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG7EI8_V_MF8_M1 + 0U, // PseudoVSOXSEG7EI8_V_MF8_M1_MASK + 0U, // PseudoVSOXSEG7EI8_V_MF8_MF2 + 0U, // PseudoVSOXSEG7EI8_V_MF8_MF2_MASK + 0U, // PseudoVSOXSEG7EI8_V_MF8_MF4 + 0U, // PseudoVSOXSEG7EI8_V_MF8_MF4_MASK + 0U, // PseudoVSOXSEG7EI8_V_MF8_MF8 + 0U, // PseudoVSOXSEG7EI8_V_MF8_MF8_MASK + 0U, // PseudoVSOXSEG8EI16_V_M1_M1 + 0U, // PseudoVSOXSEG8EI16_V_M1_M1_MASK + 0U, // PseudoVSOXSEG8EI16_V_M1_MF2 + 0U, // PseudoVSOXSEG8EI16_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG8EI16_V_M2_M1 + 0U, // PseudoVSOXSEG8EI16_V_M2_M1_MASK + 0U, // PseudoVSOXSEG8EI16_V_MF2_M1 + 0U, // PseudoVSOXSEG8EI16_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG8EI16_V_MF2_MF2 + 0U, // PseudoVSOXSEG8EI16_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG8EI16_V_MF2_MF4 + 0U, // PseudoVSOXSEG8EI16_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG8EI16_V_MF4_M1 + 0U, // PseudoVSOXSEG8EI16_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG8EI16_V_MF4_MF2 + 0U, // PseudoVSOXSEG8EI16_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG8EI16_V_MF4_MF4 + 0U, // PseudoVSOXSEG8EI16_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG8EI16_V_MF4_MF8 + 0U, // PseudoVSOXSEG8EI16_V_MF4_MF8_MASK + 0U, // PseudoVSOXSEG8EI32_V_M1_M1 + 0U, // PseudoVSOXSEG8EI32_V_M1_M1_MASK + 0U, // PseudoVSOXSEG8EI32_V_M1_MF2 + 0U, // PseudoVSOXSEG8EI32_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG8EI32_V_M1_MF4 + 0U, // PseudoVSOXSEG8EI32_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG8EI32_V_M2_M1 + 0U, // PseudoVSOXSEG8EI32_V_M2_M1_MASK + 0U, // PseudoVSOXSEG8EI32_V_M2_MF2 + 0U, // PseudoVSOXSEG8EI32_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG8EI32_V_M4_M1 + 0U, // PseudoVSOXSEG8EI32_V_M4_M1_MASK + 0U, // PseudoVSOXSEG8EI32_V_MF2_M1 + 0U, // PseudoVSOXSEG8EI32_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG8EI32_V_MF2_MF2 + 0U, // PseudoVSOXSEG8EI32_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG8EI32_V_MF2_MF4 + 0U, // PseudoVSOXSEG8EI32_V_MF2_MF4_MASK + 0U, // PseudoVSOXSEG8EI32_V_MF2_MF8 + 0U, // PseudoVSOXSEG8EI32_V_MF2_MF8_MASK + 0U, // PseudoVSOXSEG8EI64_V_M1_M1 + 0U, // PseudoVSOXSEG8EI64_V_M1_M1_MASK + 0U, // PseudoVSOXSEG8EI64_V_M1_MF2 + 0U, // PseudoVSOXSEG8EI64_V_M1_MF2_MASK + 0U, // PseudoVSOXSEG8EI64_V_M1_MF4 + 0U, // PseudoVSOXSEG8EI64_V_M1_MF4_MASK + 0U, // PseudoVSOXSEG8EI64_V_M1_MF8 + 0U, // PseudoVSOXSEG8EI64_V_M1_MF8_MASK + 0U, // PseudoVSOXSEG8EI64_V_M2_M1 + 0U, // PseudoVSOXSEG8EI64_V_M2_M1_MASK + 0U, // PseudoVSOXSEG8EI64_V_M2_MF2 + 0U, // PseudoVSOXSEG8EI64_V_M2_MF2_MASK + 0U, // PseudoVSOXSEG8EI64_V_M2_MF4 + 0U, // PseudoVSOXSEG8EI64_V_M2_MF4_MASK + 0U, // PseudoVSOXSEG8EI64_V_M4_M1 + 0U, // PseudoVSOXSEG8EI64_V_M4_M1_MASK + 0U, // PseudoVSOXSEG8EI64_V_M4_MF2 + 0U, // PseudoVSOXSEG8EI64_V_M4_MF2_MASK + 0U, // PseudoVSOXSEG8EI64_V_M8_M1 + 0U, // PseudoVSOXSEG8EI64_V_M8_M1_MASK + 0U, // PseudoVSOXSEG8EI8_V_M1_M1 + 0U, // PseudoVSOXSEG8EI8_V_M1_M1_MASK + 0U, // PseudoVSOXSEG8EI8_V_MF2_M1 + 0U, // PseudoVSOXSEG8EI8_V_MF2_M1_MASK + 0U, // PseudoVSOXSEG8EI8_V_MF2_MF2 + 0U, // PseudoVSOXSEG8EI8_V_MF2_MF2_MASK + 0U, // PseudoVSOXSEG8EI8_V_MF4_M1 + 0U, // PseudoVSOXSEG8EI8_V_MF4_M1_MASK + 0U, // PseudoVSOXSEG8EI8_V_MF4_MF2 + 0U, // PseudoVSOXSEG8EI8_V_MF4_MF2_MASK + 0U, // PseudoVSOXSEG8EI8_V_MF4_MF4 + 0U, // PseudoVSOXSEG8EI8_V_MF4_MF4_MASK + 0U, // PseudoVSOXSEG8EI8_V_MF8_M1 + 0U, // PseudoVSOXSEG8EI8_V_MF8_M1_MASK + 0U, // PseudoVSOXSEG8EI8_V_MF8_MF2 + 0U, // PseudoVSOXSEG8EI8_V_MF8_MF2_MASK + 0U, // PseudoVSOXSEG8EI8_V_MF8_MF4 + 0U, // PseudoVSOXSEG8EI8_V_MF8_MF4_MASK + 0U, // PseudoVSOXSEG8EI8_V_MF8_MF8 + 0U, // PseudoVSOXSEG8EI8_V_MF8_MF8_MASK + 0U, // PseudoVSPILL2_M1 + 0U, // PseudoVSPILL2_M2 + 0U, // PseudoVSPILL2_M4 + 0U, // PseudoVSPILL2_MF2 + 0U, // PseudoVSPILL2_MF4 + 0U, // PseudoVSPILL2_MF8 + 0U, // PseudoVSPILL3_M1 + 0U, // PseudoVSPILL3_M2 + 0U, // PseudoVSPILL3_MF2 + 0U, // PseudoVSPILL3_MF4 + 0U, // PseudoVSPILL3_MF8 + 0U, // PseudoVSPILL4_M1 + 0U, // PseudoVSPILL4_M2 + 0U, // PseudoVSPILL4_MF2 + 0U, // PseudoVSPILL4_MF4 + 0U, // PseudoVSPILL4_MF8 + 0U, // PseudoVSPILL5_M1 + 0U, // PseudoVSPILL5_MF2 + 0U, // PseudoVSPILL5_MF4 + 0U, // PseudoVSPILL5_MF8 + 0U, // PseudoVSPILL6_M1 + 0U, // PseudoVSPILL6_MF2 + 0U, // PseudoVSPILL6_MF4 + 0U, // PseudoVSPILL6_MF8 + 0U, // PseudoVSPILL7_M1 + 0U, // PseudoVSPILL7_MF2 + 0U, // PseudoVSPILL7_MF4 + 0U, // PseudoVSPILL7_MF8 + 0U, // PseudoVSPILL8_M1 + 0U, // PseudoVSPILL8_MF2 + 0U, // PseudoVSPILL8_MF4 + 0U, // PseudoVSPILL8_MF8 + 0U, // PseudoVSPILL_M1 + 0U, // PseudoVSPILL_M2 + 0U, // PseudoVSPILL_M4 + 0U, // PseudoVSPILL_M8 + 0U, // PseudoVSRA_VI_M1 + 0U, // PseudoVSRA_VI_M1_MASK + 0U, // PseudoVSRA_VI_M2 + 0U, // PseudoVSRA_VI_M2_MASK + 0U, // PseudoVSRA_VI_M4 + 0U, // PseudoVSRA_VI_M4_MASK + 0U, // PseudoVSRA_VI_M8 + 0U, // PseudoVSRA_VI_M8_MASK + 0U, // PseudoVSRA_VI_MF2 + 0U, // PseudoVSRA_VI_MF2_MASK + 0U, // PseudoVSRA_VI_MF4 + 0U, // PseudoVSRA_VI_MF4_MASK + 0U, // PseudoVSRA_VI_MF8 + 0U, // PseudoVSRA_VI_MF8_MASK + 0U, // PseudoVSRA_VV_M1 + 0U, // PseudoVSRA_VV_M1_MASK + 0U, // PseudoVSRA_VV_M2 + 0U, // PseudoVSRA_VV_M2_MASK + 0U, // PseudoVSRA_VV_M4 + 0U, // PseudoVSRA_VV_M4_MASK + 0U, // PseudoVSRA_VV_M8 + 0U, // PseudoVSRA_VV_M8_MASK + 0U, // PseudoVSRA_VV_MF2 + 0U, // PseudoVSRA_VV_MF2_MASK + 0U, // PseudoVSRA_VV_MF4 + 0U, // PseudoVSRA_VV_MF4_MASK + 0U, // PseudoVSRA_VV_MF8 + 0U, // PseudoVSRA_VV_MF8_MASK + 0U, // PseudoVSRA_VX_M1 + 0U, // PseudoVSRA_VX_M1_MASK + 0U, // PseudoVSRA_VX_M2 + 0U, // PseudoVSRA_VX_M2_MASK + 0U, // PseudoVSRA_VX_M4 + 0U, // PseudoVSRA_VX_M4_MASK + 0U, // PseudoVSRA_VX_M8 + 0U, // PseudoVSRA_VX_M8_MASK + 0U, // PseudoVSRA_VX_MF2 + 0U, // PseudoVSRA_VX_MF2_MASK + 0U, // PseudoVSRA_VX_MF4 + 0U, // PseudoVSRA_VX_MF4_MASK + 0U, // PseudoVSRA_VX_MF8 + 0U, // PseudoVSRA_VX_MF8_MASK + 0U, // PseudoVSRL_VI_M1 + 0U, // PseudoVSRL_VI_M1_MASK + 0U, // PseudoVSRL_VI_M2 + 0U, // PseudoVSRL_VI_M2_MASK + 0U, // PseudoVSRL_VI_M4 + 0U, // PseudoVSRL_VI_M4_MASK + 0U, // PseudoVSRL_VI_M8 + 0U, // PseudoVSRL_VI_M8_MASK + 0U, // PseudoVSRL_VI_MF2 + 0U, // PseudoVSRL_VI_MF2_MASK + 0U, // PseudoVSRL_VI_MF4 + 0U, // PseudoVSRL_VI_MF4_MASK + 0U, // PseudoVSRL_VI_MF8 + 0U, // PseudoVSRL_VI_MF8_MASK + 0U, // PseudoVSRL_VV_M1 + 0U, // PseudoVSRL_VV_M1_MASK + 0U, // PseudoVSRL_VV_M2 + 0U, // PseudoVSRL_VV_M2_MASK + 0U, // PseudoVSRL_VV_M4 + 0U, // PseudoVSRL_VV_M4_MASK + 0U, // PseudoVSRL_VV_M8 + 0U, // PseudoVSRL_VV_M8_MASK + 0U, // PseudoVSRL_VV_MF2 + 0U, // PseudoVSRL_VV_MF2_MASK + 0U, // PseudoVSRL_VV_MF4 + 0U, // PseudoVSRL_VV_MF4_MASK + 0U, // PseudoVSRL_VV_MF8 + 0U, // PseudoVSRL_VV_MF8_MASK + 0U, // PseudoVSRL_VX_M1 + 0U, // PseudoVSRL_VX_M1_MASK + 0U, // PseudoVSRL_VX_M2 + 0U, // PseudoVSRL_VX_M2_MASK + 0U, // PseudoVSRL_VX_M4 + 0U, // PseudoVSRL_VX_M4_MASK + 0U, // PseudoVSRL_VX_M8 + 0U, // PseudoVSRL_VX_M8_MASK + 0U, // PseudoVSRL_VX_MF2 + 0U, // PseudoVSRL_VX_MF2_MASK + 0U, // PseudoVSRL_VX_MF4 + 0U, // PseudoVSRL_VX_MF4_MASK + 0U, // PseudoVSRL_VX_MF8 + 0U, // PseudoVSRL_VX_MF8_MASK + 0U, // PseudoVSSE16_V_M1 + 0U, // PseudoVSSE16_V_M1_MASK + 0U, // PseudoVSSE16_V_M2 + 0U, // PseudoVSSE16_V_M2_MASK + 0U, // PseudoVSSE16_V_M4 + 0U, // PseudoVSSE16_V_M4_MASK + 0U, // PseudoVSSE16_V_M8 + 0U, // PseudoVSSE16_V_M8_MASK + 0U, // PseudoVSSE16_V_MF2 + 0U, // PseudoVSSE16_V_MF2_MASK + 0U, // PseudoVSSE16_V_MF4 + 0U, // PseudoVSSE16_V_MF4_MASK + 0U, // PseudoVSSE32_V_M1 + 0U, // PseudoVSSE32_V_M1_MASK + 0U, // PseudoVSSE32_V_M2 + 0U, // PseudoVSSE32_V_M2_MASK + 0U, // PseudoVSSE32_V_M4 + 0U, // PseudoVSSE32_V_M4_MASK + 0U, // PseudoVSSE32_V_M8 + 0U, // PseudoVSSE32_V_M8_MASK + 0U, // PseudoVSSE32_V_MF2 + 0U, // PseudoVSSE32_V_MF2_MASK + 0U, // PseudoVSSE64_V_M1 + 0U, // PseudoVSSE64_V_M1_MASK + 0U, // PseudoVSSE64_V_M2 + 0U, // PseudoVSSE64_V_M2_MASK + 0U, // PseudoVSSE64_V_M4 + 0U, // PseudoVSSE64_V_M4_MASK + 0U, // PseudoVSSE64_V_M8 + 0U, // PseudoVSSE64_V_M8_MASK + 0U, // PseudoVSSE8_V_M1 + 0U, // PseudoVSSE8_V_M1_MASK + 0U, // PseudoVSSE8_V_M2 + 0U, // PseudoVSSE8_V_M2_MASK + 0U, // PseudoVSSE8_V_M4 + 0U, // PseudoVSSE8_V_M4_MASK + 0U, // PseudoVSSE8_V_M8 + 0U, // PseudoVSSE8_V_M8_MASK + 0U, // PseudoVSSE8_V_MF2 + 0U, // PseudoVSSE8_V_MF2_MASK + 0U, // PseudoVSSE8_V_MF4 + 0U, // PseudoVSSE8_V_MF4_MASK + 0U, // PseudoVSSE8_V_MF8 + 0U, // PseudoVSSE8_V_MF8_MASK + 0U, // PseudoVSSEG2E16_V_M1 + 0U, // PseudoVSSEG2E16_V_M1_MASK + 0U, // PseudoVSSEG2E16_V_M2 + 0U, // PseudoVSSEG2E16_V_M2_MASK + 0U, // PseudoVSSEG2E16_V_M4 + 0U, // PseudoVSSEG2E16_V_M4_MASK + 0U, // PseudoVSSEG2E16_V_MF2 + 0U, // PseudoVSSEG2E16_V_MF2_MASK + 0U, // PseudoVSSEG2E16_V_MF4 + 0U, // PseudoVSSEG2E16_V_MF4_MASK + 0U, // PseudoVSSEG2E32_V_M1 + 0U, // PseudoVSSEG2E32_V_M1_MASK + 0U, // PseudoVSSEG2E32_V_M2 + 0U, // PseudoVSSEG2E32_V_M2_MASK + 0U, // PseudoVSSEG2E32_V_M4 + 0U, // PseudoVSSEG2E32_V_M4_MASK + 0U, // PseudoVSSEG2E32_V_MF2 + 0U, // PseudoVSSEG2E32_V_MF2_MASK + 0U, // PseudoVSSEG2E64_V_M1 + 0U, // PseudoVSSEG2E64_V_M1_MASK + 0U, // PseudoVSSEG2E64_V_M2 + 0U, // PseudoVSSEG2E64_V_M2_MASK + 0U, // PseudoVSSEG2E64_V_M4 + 0U, // PseudoVSSEG2E64_V_M4_MASK + 0U, // PseudoVSSEG2E8_V_M1 + 0U, // PseudoVSSEG2E8_V_M1_MASK + 0U, // PseudoVSSEG2E8_V_M2 + 0U, // PseudoVSSEG2E8_V_M2_MASK + 0U, // PseudoVSSEG2E8_V_M4 + 0U, // PseudoVSSEG2E8_V_M4_MASK + 0U, // PseudoVSSEG2E8_V_MF2 + 0U, // PseudoVSSEG2E8_V_MF2_MASK + 0U, // PseudoVSSEG2E8_V_MF4 + 0U, // PseudoVSSEG2E8_V_MF4_MASK + 0U, // PseudoVSSEG2E8_V_MF8 + 0U, // PseudoVSSEG2E8_V_MF8_MASK + 0U, // PseudoVSSEG3E16_V_M1 + 0U, // PseudoVSSEG3E16_V_M1_MASK + 0U, // PseudoVSSEG3E16_V_M2 + 0U, // PseudoVSSEG3E16_V_M2_MASK + 0U, // PseudoVSSEG3E16_V_MF2 + 0U, // PseudoVSSEG3E16_V_MF2_MASK + 0U, // PseudoVSSEG3E16_V_MF4 + 0U, // PseudoVSSEG3E16_V_MF4_MASK + 0U, // PseudoVSSEG3E32_V_M1 + 0U, // PseudoVSSEG3E32_V_M1_MASK + 0U, // PseudoVSSEG3E32_V_M2 + 0U, // PseudoVSSEG3E32_V_M2_MASK + 0U, // PseudoVSSEG3E32_V_MF2 + 0U, // PseudoVSSEG3E32_V_MF2_MASK + 0U, // PseudoVSSEG3E64_V_M1 + 0U, // PseudoVSSEG3E64_V_M1_MASK + 0U, // PseudoVSSEG3E64_V_M2 + 0U, // PseudoVSSEG3E64_V_M2_MASK + 0U, // PseudoVSSEG3E8_V_M1 + 0U, // PseudoVSSEG3E8_V_M1_MASK + 0U, // PseudoVSSEG3E8_V_M2 + 0U, // PseudoVSSEG3E8_V_M2_MASK + 0U, // PseudoVSSEG3E8_V_MF2 + 0U, // PseudoVSSEG3E8_V_MF2_MASK + 0U, // PseudoVSSEG3E8_V_MF4 + 0U, // PseudoVSSEG3E8_V_MF4_MASK + 0U, // PseudoVSSEG3E8_V_MF8 + 0U, // PseudoVSSEG3E8_V_MF8_MASK + 0U, // PseudoVSSEG4E16_V_M1 + 0U, // PseudoVSSEG4E16_V_M1_MASK + 0U, // PseudoVSSEG4E16_V_M2 + 0U, // PseudoVSSEG4E16_V_M2_MASK + 0U, // PseudoVSSEG4E16_V_MF2 + 0U, // PseudoVSSEG4E16_V_MF2_MASK + 0U, // PseudoVSSEG4E16_V_MF4 + 0U, // PseudoVSSEG4E16_V_MF4_MASK + 0U, // PseudoVSSEG4E32_V_M1 + 0U, // PseudoVSSEG4E32_V_M1_MASK + 0U, // PseudoVSSEG4E32_V_M2 + 0U, // PseudoVSSEG4E32_V_M2_MASK + 0U, // PseudoVSSEG4E32_V_MF2 + 0U, // PseudoVSSEG4E32_V_MF2_MASK + 0U, // PseudoVSSEG4E64_V_M1 + 0U, // PseudoVSSEG4E64_V_M1_MASK + 0U, // PseudoVSSEG4E64_V_M2 + 0U, // PseudoVSSEG4E64_V_M2_MASK + 0U, // PseudoVSSEG4E8_V_M1 + 0U, // PseudoVSSEG4E8_V_M1_MASK + 0U, // PseudoVSSEG4E8_V_M2 + 0U, // PseudoVSSEG4E8_V_M2_MASK + 0U, // PseudoVSSEG4E8_V_MF2 + 0U, // PseudoVSSEG4E8_V_MF2_MASK + 0U, // PseudoVSSEG4E8_V_MF4 + 0U, // PseudoVSSEG4E8_V_MF4_MASK + 0U, // PseudoVSSEG4E8_V_MF8 + 0U, // PseudoVSSEG4E8_V_MF8_MASK + 0U, // PseudoVSSEG5E16_V_M1 + 0U, // PseudoVSSEG5E16_V_M1_MASK + 0U, // PseudoVSSEG5E16_V_MF2 + 0U, // PseudoVSSEG5E16_V_MF2_MASK + 0U, // PseudoVSSEG5E16_V_MF4 + 0U, // PseudoVSSEG5E16_V_MF4_MASK + 0U, // PseudoVSSEG5E32_V_M1 + 0U, // PseudoVSSEG5E32_V_M1_MASK + 0U, // PseudoVSSEG5E32_V_MF2 + 0U, // PseudoVSSEG5E32_V_MF2_MASK + 0U, // PseudoVSSEG5E64_V_M1 + 0U, // PseudoVSSEG5E64_V_M1_MASK + 0U, // PseudoVSSEG5E8_V_M1 + 0U, // PseudoVSSEG5E8_V_M1_MASK + 0U, // PseudoVSSEG5E8_V_MF2 + 0U, // PseudoVSSEG5E8_V_MF2_MASK + 0U, // PseudoVSSEG5E8_V_MF4 + 0U, // PseudoVSSEG5E8_V_MF4_MASK + 0U, // PseudoVSSEG5E8_V_MF8 + 0U, // PseudoVSSEG5E8_V_MF8_MASK + 0U, // PseudoVSSEG6E16_V_M1 + 0U, // PseudoVSSEG6E16_V_M1_MASK + 0U, // PseudoVSSEG6E16_V_MF2 + 0U, // PseudoVSSEG6E16_V_MF2_MASK + 0U, // PseudoVSSEG6E16_V_MF4 + 0U, // PseudoVSSEG6E16_V_MF4_MASK + 0U, // PseudoVSSEG6E32_V_M1 + 0U, // PseudoVSSEG6E32_V_M1_MASK + 0U, // PseudoVSSEG6E32_V_MF2 + 0U, // PseudoVSSEG6E32_V_MF2_MASK + 0U, // PseudoVSSEG6E64_V_M1 + 0U, // PseudoVSSEG6E64_V_M1_MASK + 0U, // PseudoVSSEG6E8_V_M1 + 0U, // PseudoVSSEG6E8_V_M1_MASK + 0U, // PseudoVSSEG6E8_V_MF2 + 0U, // PseudoVSSEG6E8_V_MF2_MASK + 0U, // PseudoVSSEG6E8_V_MF4 + 0U, // PseudoVSSEG6E8_V_MF4_MASK + 0U, // PseudoVSSEG6E8_V_MF8 + 0U, // PseudoVSSEG6E8_V_MF8_MASK + 0U, // PseudoVSSEG7E16_V_M1 + 0U, // PseudoVSSEG7E16_V_M1_MASK + 0U, // PseudoVSSEG7E16_V_MF2 + 0U, // PseudoVSSEG7E16_V_MF2_MASK + 0U, // PseudoVSSEG7E16_V_MF4 + 0U, // PseudoVSSEG7E16_V_MF4_MASK + 0U, // PseudoVSSEG7E32_V_M1 + 0U, // PseudoVSSEG7E32_V_M1_MASK + 0U, // PseudoVSSEG7E32_V_MF2 + 0U, // PseudoVSSEG7E32_V_MF2_MASK + 0U, // PseudoVSSEG7E64_V_M1 + 0U, // PseudoVSSEG7E64_V_M1_MASK + 0U, // PseudoVSSEG7E8_V_M1 + 0U, // PseudoVSSEG7E8_V_M1_MASK + 0U, // PseudoVSSEG7E8_V_MF2 + 0U, // PseudoVSSEG7E8_V_MF2_MASK + 0U, // PseudoVSSEG7E8_V_MF4 + 0U, // PseudoVSSEG7E8_V_MF4_MASK + 0U, // PseudoVSSEG7E8_V_MF8 + 0U, // PseudoVSSEG7E8_V_MF8_MASK + 0U, // PseudoVSSEG8E16_V_M1 + 0U, // PseudoVSSEG8E16_V_M1_MASK + 0U, // PseudoVSSEG8E16_V_MF2 + 0U, // PseudoVSSEG8E16_V_MF2_MASK + 0U, // PseudoVSSEG8E16_V_MF4 + 0U, // PseudoVSSEG8E16_V_MF4_MASK + 0U, // PseudoVSSEG8E32_V_M1 + 0U, // PseudoVSSEG8E32_V_M1_MASK + 0U, // PseudoVSSEG8E32_V_MF2 + 0U, // PseudoVSSEG8E32_V_MF2_MASK + 0U, // PseudoVSSEG8E64_V_M1 + 0U, // PseudoVSSEG8E64_V_M1_MASK + 0U, // PseudoVSSEG8E8_V_M1 + 0U, // PseudoVSSEG8E8_V_M1_MASK + 0U, // PseudoVSSEG8E8_V_MF2 + 0U, // PseudoVSSEG8E8_V_MF2_MASK + 0U, // PseudoVSSEG8E8_V_MF4 + 0U, // PseudoVSSEG8E8_V_MF4_MASK + 0U, // PseudoVSSEG8E8_V_MF8 + 0U, // PseudoVSSEG8E8_V_MF8_MASK + 0U, // PseudoVSSRA_VI_M1 + 0U, // PseudoVSSRA_VI_M1_MASK + 0U, // PseudoVSSRA_VI_M2 + 0U, // PseudoVSSRA_VI_M2_MASK + 0U, // PseudoVSSRA_VI_M4 + 0U, // PseudoVSSRA_VI_M4_MASK + 0U, // PseudoVSSRA_VI_M8 + 0U, // PseudoVSSRA_VI_M8_MASK + 0U, // PseudoVSSRA_VI_MF2 + 0U, // PseudoVSSRA_VI_MF2_MASK + 0U, // PseudoVSSRA_VI_MF4 + 0U, // PseudoVSSRA_VI_MF4_MASK + 0U, // PseudoVSSRA_VI_MF8 + 0U, // PseudoVSSRA_VI_MF8_MASK + 0U, // PseudoVSSRA_VV_M1 + 0U, // PseudoVSSRA_VV_M1_MASK + 0U, // PseudoVSSRA_VV_M2 + 0U, // PseudoVSSRA_VV_M2_MASK + 0U, // PseudoVSSRA_VV_M4 + 0U, // PseudoVSSRA_VV_M4_MASK + 0U, // PseudoVSSRA_VV_M8 + 0U, // PseudoVSSRA_VV_M8_MASK + 0U, // PseudoVSSRA_VV_MF2 + 0U, // PseudoVSSRA_VV_MF2_MASK + 0U, // PseudoVSSRA_VV_MF4 + 0U, // PseudoVSSRA_VV_MF4_MASK + 0U, // PseudoVSSRA_VV_MF8 + 0U, // PseudoVSSRA_VV_MF8_MASK + 0U, // PseudoVSSRA_VX_M1 + 0U, // PseudoVSSRA_VX_M1_MASK + 0U, // PseudoVSSRA_VX_M2 + 0U, // PseudoVSSRA_VX_M2_MASK + 0U, // PseudoVSSRA_VX_M4 + 0U, // PseudoVSSRA_VX_M4_MASK + 0U, // PseudoVSSRA_VX_M8 + 0U, // PseudoVSSRA_VX_M8_MASK + 0U, // PseudoVSSRA_VX_MF2 + 0U, // PseudoVSSRA_VX_MF2_MASK + 0U, // PseudoVSSRA_VX_MF4 + 0U, // PseudoVSSRA_VX_MF4_MASK + 0U, // PseudoVSSRA_VX_MF8 + 0U, // PseudoVSSRA_VX_MF8_MASK + 0U, // PseudoVSSRL_VI_M1 + 0U, // PseudoVSSRL_VI_M1_MASK + 0U, // PseudoVSSRL_VI_M2 + 0U, // PseudoVSSRL_VI_M2_MASK + 0U, // PseudoVSSRL_VI_M4 + 0U, // PseudoVSSRL_VI_M4_MASK + 0U, // PseudoVSSRL_VI_M8 + 0U, // PseudoVSSRL_VI_M8_MASK + 0U, // PseudoVSSRL_VI_MF2 + 0U, // PseudoVSSRL_VI_MF2_MASK + 0U, // PseudoVSSRL_VI_MF4 + 0U, // PseudoVSSRL_VI_MF4_MASK + 0U, // PseudoVSSRL_VI_MF8 + 0U, // PseudoVSSRL_VI_MF8_MASK + 0U, // PseudoVSSRL_VV_M1 + 0U, // PseudoVSSRL_VV_M1_MASK + 0U, // PseudoVSSRL_VV_M2 + 0U, // PseudoVSSRL_VV_M2_MASK + 0U, // PseudoVSSRL_VV_M4 + 0U, // PseudoVSSRL_VV_M4_MASK + 0U, // PseudoVSSRL_VV_M8 + 0U, // PseudoVSSRL_VV_M8_MASK + 0U, // PseudoVSSRL_VV_MF2 + 0U, // PseudoVSSRL_VV_MF2_MASK + 0U, // PseudoVSSRL_VV_MF4 + 0U, // PseudoVSSRL_VV_MF4_MASK + 0U, // PseudoVSSRL_VV_MF8 + 0U, // PseudoVSSRL_VV_MF8_MASK + 0U, // PseudoVSSRL_VX_M1 + 0U, // PseudoVSSRL_VX_M1_MASK + 0U, // PseudoVSSRL_VX_M2 + 0U, // PseudoVSSRL_VX_M2_MASK + 0U, // PseudoVSSRL_VX_M4 + 0U, // PseudoVSSRL_VX_M4_MASK + 0U, // PseudoVSSRL_VX_M8 + 0U, // PseudoVSSRL_VX_M8_MASK + 0U, // PseudoVSSRL_VX_MF2 + 0U, // PseudoVSSRL_VX_MF2_MASK + 0U, // PseudoVSSRL_VX_MF4 + 0U, // PseudoVSSRL_VX_MF4_MASK + 0U, // PseudoVSSRL_VX_MF8 + 0U, // PseudoVSSRL_VX_MF8_MASK + 0U, // PseudoVSSSEG2E16_V_M1 + 0U, // PseudoVSSSEG2E16_V_M1_MASK + 0U, // PseudoVSSSEG2E16_V_M2 + 0U, // PseudoVSSSEG2E16_V_M2_MASK + 0U, // PseudoVSSSEG2E16_V_M4 + 0U, // PseudoVSSSEG2E16_V_M4_MASK + 0U, // PseudoVSSSEG2E16_V_MF2 + 0U, // PseudoVSSSEG2E16_V_MF2_MASK + 0U, // PseudoVSSSEG2E16_V_MF4 + 0U, // PseudoVSSSEG2E16_V_MF4_MASK + 0U, // PseudoVSSSEG2E32_V_M1 + 0U, // PseudoVSSSEG2E32_V_M1_MASK + 0U, // PseudoVSSSEG2E32_V_M2 + 0U, // PseudoVSSSEG2E32_V_M2_MASK + 0U, // PseudoVSSSEG2E32_V_M4 + 0U, // PseudoVSSSEG2E32_V_M4_MASK + 0U, // PseudoVSSSEG2E32_V_MF2 + 0U, // PseudoVSSSEG2E32_V_MF2_MASK + 0U, // PseudoVSSSEG2E64_V_M1 + 0U, // PseudoVSSSEG2E64_V_M1_MASK + 0U, // PseudoVSSSEG2E64_V_M2 + 0U, // PseudoVSSSEG2E64_V_M2_MASK + 0U, // PseudoVSSSEG2E64_V_M4 + 0U, // PseudoVSSSEG2E64_V_M4_MASK + 0U, // PseudoVSSSEG2E8_V_M1 + 0U, // PseudoVSSSEG2E8_V_M1_MASK + 0U, // PseudoVSSSEG2E8_V_M2 + 0U, // PseudoVSSSEG2E8_V_M2_MASK + 0U, // PseudoVSSSEG2E8_V_M4 + 0U, // PseudoVSSSEG2E8_V_M4_MASK + 0U, // PseudoVSSSEG2E8_V_MF2 + 0U, // PseudoVSSSEG2E8_V_MF2_MASK + 0U, // PseudoVSSSEG2E8_V_MF4 + 0U, // PseudoVSSSEG2E8_V_MF4_MASK + 0U, // PseudoVSSSEG2E8_V_MF8 + 0U, // PseudoVSSSEG2E8_V_MF8_MASK + 0U, // PseudoVSSSEG3E16_V_M1 + 0U, // PseudoVSSSEG3E16_V_M1_MASK + 0U, // PseudoVSSSEG3E16_V_M2 + 0U, // PseudoVSSSEG3E16_V_M2_MASK + 0U, // PseudoVSSSEG3E16_V_MF2 + 0U, // PseudoVSSSEG3E16_V_MF2_MASK + 0U, // PseudoVSSSEG3E16_V_MF4 + 0U, // PseudoVSSSEG3E16_V_MF4_MASK + 0U, // PseudoVSSSEG3E32_V_M1 + 0U, // PseudoVSSSEG3E32_V_M1_MASK + 0U, // PseudoVSSSEG3E32_V_M2 + 0U, // PseudoVSSSEG3E32_V_M2_MASK + 0U, // PseudoVSSSEG3E32_V_MF2 + 0U, // PseudoVSSSEG3E32_V_MF2_MASK + 0U, // PseudoVSSSEG3E64_V_M1 + 0U, // PseudoVSSSEG3E64_V_M1_MASK + 0U, // PseudoVSSSEG3E64_V_M2 + 0U, // PseudoVSSSEG3E64_V_M2_MASK + 0U, // PseudoVSSSEG3E8_V_M1 + 0U, // PseudoVSSSEG3E8_V_M1_MASK + 0U, // PseudoVSSSEG3E8_V_M2 + 0U, // PseudoVSSSEG3E8_V_M2_MASK + 0U, // PseudoVSSSEG3E8_V_MF2 + 0U, // PseudoVSSSEG3E8_V_MF2_MASK + 0U, // PseudoVSSSEG3E8_V_MF4 + 0U, // PseudoVSSSEG3E8_V_MF4_MASK + 0U, // PseudoVSSSEG3E8_V_MF8 + 0U, // PseudoVSSSEG3E8_V_MF8_MASK + 0U, // PseudoVSSSEG4E16_V_M1 + 0U, // PseudoVSSSEG4E16_V_M1_MASK + 0U, // PseudoVSSSEG4E16_V_M2 + 0U, // PseudoVSSSEG4E16_V_M2_MASK + 0U, // PseudoVSSSEG4E16_V_MF2 + 0U, // PseudoVSSSEG4E16_V_MF2_MASK + 0U, // PseudoVSSSEG4E16_V_MF4 + 0U, // PseudoVSSSEG4E16_V_MF4_MASK + 0U, // PseudoVSSSEG4E32_V_M1 + 0U, // PseudoVSSSEG4E32_V_M1_MASK + 0U, // PseudoVSSSEG4E32_V_M2 + 0U, // PseudoVSSSEG4E32_V_M2_MASK + 0U, // PseudoVSSSEG4E32_V_MF2 + 0U, // PseudoVSSSEG4E32_V_MF2_MASK + 0U, // PseudoVSSSEG4E64_V_M1 + 0U, // PseudoVSSSEG4E64_V_M1_MASK + 0U, // PseudoVSSSEG4E64_V_M2 + 0U, // PseudoVSSSEG4E64_V_M2_MASK + 0U, // PseudoVSSSEG4E8_V_M1 + 0U, // PseudoVSSSEG4E8_V_M1_MASK + 0U, // PseudoVSSSEG4E8_V_M2 + 0U, // PseudoVSSSEG4E8_V_M2_MASK + 0U, // PseudoVSSSEG4E8_V_MF2 + 0U, // PseudoVSSSEG4E8_V_MF2_MASK + 0U, // PseudoVSSSEG4E8_V_MF4 + 0U, // PseudoVSSSEG4E8_V_MF4_MASK + 0U, // PseudoVSSSEG4E8_V_MF8 + 0U, // PseudoVSSSEG4E8_V_MF8_MASK + 0U, // PseudoVSSSEG5E16_V_M1 + 0U, // PseudoVSSSEG5E16_V_M1_MASK + 0U, // PseudoVSSSEG5E16_V_MF2 + 0U, // PseudoVSSSEG5E16_V_MF2_MASK + 0U, // PseudoVSSSEG5E16_V_MF4 + 0U, // PseudoVSSSEG5E16_V_MF4_MASK + 0U, // PseudoVSSSEG5E32_V_M1 + 0U, // PseudoVSSSEG5E32_V_M1_MASK + 0U, // PseudoVSSSEG5E32_V_MF2 + 0U, // PseudoVSSSEG5E32_V_MF2_MASK + 0U, // PseudoVSSSEG5E64_V_M1 + 0U, // PseudoVSSSEG5E64_V_M1_MASK + 0U, // PseudoVSSSEG5E8_V_M1 + 0U, // PseudoVSSSEG5E8_V_M1_MASK + 0U, // PseudoVSSSEG5E8_V_MF2 + 0U, // PseudoVSSSEG5E8_V_MF2_MASK + 0U, // PseudoVSSSEG5E8_V_MF4 + 0U, // PseudoVSSSEG5E8_V_MF4_MASK + 0U, // PseudoVSSSEG5E8_V_MF8 + 0U, // PseudoVSSSEG5E8_V_MF8_MASK + 0U, // PseudoVSSSEG6E16_V_M1 + 0U, // PseudoVSSSEG6E16_V_M1_MASK + 0U, // PseudoVSSSEG6E16_V_MF2 + 0U, // PseudoVSSSEG6E16_V_MF2_MASK + 0U, // PseudoVSSSEG6E16_V_MF4 + 0U, // PseudoVSSSEG6E16_V_MF4_MASK + 0U, // PseudoVSSSEG6E32_V_M1 + 0U, // PseudoVSSSEG6E32_V_M1_MASK + 0U, // PseudoVSSSEG6E32_V_MF2 + 0U, // PseudoVSSSEG6E32_V_MF2_MASK + 0U, // PseudoVSSSEG6E64_V_M1 + 0U, // PseudoVSSSEG6E64_V_M1_MASK + 0U, // PseudoVSSSEG6E8_V_M1 + 0U, // PseudoVSSSEG6E8_V_M1_MASK + 0U, // PseudoVSSSEG6E8_V_MF2 + 0U, // PseudoVSSSEG6E8_V_MF2_MASK + 0U, // PseudoVSSSEG6E8_V_MF4 + 0U, // PseudoVSSSEG6E8_V_MF4_MASK + 0U, // PseudoVSSSEG6E8_V_MF8 + 0U, // PseudoVSSSEG6E8_V_MF8_MASK + 0U, // PseudoVSSSEG7E16_V_M1 + 0U, // PseudoVSSSEG7E16_V_M1_MASK + 0U, // PseudoVSSSEG7E16_V_MF2 + 0U, // PseudoVSSSEG7E16_V_MF2_MASK + 0U, // PseudoVSSSEG7E16_V_MF4 + 0U, // PseudoVSSSEG7E16_V_MF4_MASK + 0U, // PseudoVSSSEG7E32_V_M1 + 0U, // PseudoVSSSEG7E32_V_M1_MASK + 0U, // PseudoVSSSEG7E32_V_MF2 + 0U, // PseudoVSSSEG7E32_V_MF2_MASK + 0U, // PseudoVSSSEG7E64_V_M1 + 0U, // PseudoVSSSEG7E64_V_M1_MASK + 0U, // PseudoVSSSEG7E8_V_M1 + 0U, // PseudoVSSSEG7E8_V_M1_MASK + 0U, // PseudoVSSSEG7E8_V_MF2 + 0U, // PseudoVSSSEG7E8_V_MF2_MASK + 0U, // PseudoVSSSEG7E8_V_MF4 + 0U, // PseudoVSSSEG7E8_V_MF4_MASK + 0U, // PseudoVSSSEG7E8_V_MF8 + 0U, // PseudoVSSSEG7E8_V_MF8_MASK + 0U, // PseudoVSSSEG8E16_V_M1 + 0U, // PseudoVSSSEG8E16_V_M1_MASK + 0U, // PseudoVSSSEG8E16_V_MF2 + 0U, // PseudoVSSSEG8E16_V_MF2_MASK + 0U, // PseudoVSSSEG8E16_V_MF4 + 0U, // PseudoVSSSEG8E16_V_MF4_MASK + 0U, // PseudoVSSSEG8E32_V_M1 + 0U, // PseudoVSSSEG8E32_V_M1_MASK + 0U, // PseudoVSSSEG8E32_V_MF2 + 0U, // PseudoVSSSEG8E32_V_MF2_MASK + 0U, // PseudoVSSSEG8E64_V_M1 + 0U, // PseudoVSSSEG8E64_V_M1_MASK + 0U, // PseudoVSSSEG8E8_V_M1 + 0U, // PseudoVSSSEG8E8_V_M1_MASK + 0U, // PseudoVSSSEG8E8_V_MF2 + 0U, // PseudoVSSSEG8E8_V_MF2_MASK + 0U, // PseudoVSSSEG8E8_V_MF4 + 0U, // PseudoVSSSEG8E8_V_MF4_MASK + 0U, // PseudoVSSSEG8E8_V_MF8 + 0U, // PseudoVSSSEG8E8_V_MF8_MASK + 0U, // PseudoVSSUBU_VV_M1 + 0U, // PseudoVSSUBU_VV_M1_MASK + 0U, // PseudoVSSUBU_VV_M2 + 0U, // PseudoVSSUBU_VV_M2_MASK + 0U, // PseudoVSSUBU_VV_M4 + 0U, // PseudoVSSUBU_VV_M4_MASK + 0U, // PseudoVSSUBU_VV_M8 + 0U, // PseudoVSSUBU_VV_M8_MASK + 0U, // PseudoVSSUBU_VV_MF2 + 0U, // PseudoVSSUBU_VV_MF2_MASK + 0U, // PseudoVSSUBU_VV_MF4 + 0U, // PseudoVSSUBU_VV_MF4_MASK + 0U, // PseudoVSSUBU_VV_MF8 + 0U, // PseudoVSSUBU_VV_MF8_MASK + 0U, // PseudoVSSUBU_VX_M1 + 0U, // PseudoVSSUBU_VX_M1_MASK + 0U, // PseudoVSSUBU_VX_M2 + 0U, // PseudoVSSUBU_VX_M2_MASK + 0U, // PseudoVSSUBU_VX_M4 + 0U, // PseudoVSSUBU_VX_M4_MASK + 0U, // PseudoVSSUBU_VX_M8 + 0U, // PseudoVSSUBU_VX_M8_MASK + 0U, // PseudoVSSUBU_VX_MF2 + 0U, // PseudoVSSUBU_VX_MF2_MASK + 0U, // PseudoVSSUBU_VX_MF4 + 0U, // PseudoVSSUBU_VX_MF4_MASK + 0U, // PseudoVSSUBU_VX_MF8 + 0U, // PseudoVSSUBU_VX_MF8_MASK + 0U, // PseudoVSSUB_VV_M1 + 0U, // PseudoVSSUB_VV_M1_MASK + 0U, // PseudoVSSUB_VV_M2 + 0U, // PseudoVSSUB_VV_M2_MASK + 0U, // PseudoVSSUB_VV_M4 + 0U, // PseudoVSSUB_VV_M4_MASK + 0U, // PseudoVSSUB_VV_M8 + 0U, // PseudoVSSUB_VV_M8_MASK + 0U, // PseudoVSSUB_VV_MF2 + 0U, // PseudoVSSUB_VV_MF2_MASK + 0U, // PseudoVSSUB_VV_MF4 + 0U, // PseudoVSSUB_VV_MF4_MASK + 0U, // PseudoVSSUB_VV_MF8 + 0U, // PseudoVSSUB_VV_MF8_MASK + 0U, // PseudoVSSUB_VX_M1 + 0U, // PseudoVSSUB_VX_M1_MASK + 0U, // PseudoVSSUB_VX_M2 + 0U, // PseudoVSSUB_VX_M2_MASK + 0U, // PseudoVSSUB_VX_M4 + 0U, // PseudoVSSUB_VX_M4_MASK + 0U, // PseudoVSSUB_VX_M8 + 0U, // PseudoVSSUB_VX_M8_MASK + 0U, // PseudoVSSUB_VX_MF2 + 0U, // PseudoVSSUB_VX_MF2_MASK + 0U, // PseudoVSSUB_VX_MF4 + 0U, // PseudoVSSUB_VX_MF4_MASK + 0U, // PseudoVSSUB_VX_MF8 + 0U, // PseudoVSSUB_VX_MF8_MASK + 0U, // PseudoVSUB_VV_M1 + 0U, // PseudoVSUB_VV_M1_MASK + 0U, // PseudoVSUB_VV_M2 + 0U, // PseudoVSUB_VV_M2_MASK + 0U, // PseudoVSUB_VV_M4 + 0U, // PseudoVSUB_VV_M4_MASK + 0U, // PseudoVSUB_VV_M8 + 0U, // PseudoVSUB_VV_M8_MASK + 0U, // PseudoVSUB_VV_MF2 + 0U, // PseudoVSUB_VV_MF2_MASK + 0U, // PseudoVSUB_VV_MF4 + 0U, // PseudoVSUB_VV_MF4_MASK + 0U, // PseudoVSUB_VV_MF8 + 0U, // PseudoVSUB_VV_MF8_MASK + 0U, // PseudoVSUB_VX_M1 + 0U, // PseudoVSUB_VX_M1_MASK + 0U, // PseudoVSUB_VX_M2 + 0U, // PseudoVSUB_VX_M2_MASK + 0U, // PseudoVSUB_VX_M4 + 0U, // PseudoVSUB_VX_M4_MASK + 0U, // PseudoVSUB_VX_M8 + 0U, // PseudoVSUB_VX_M8_MASK + 0U, // PseudoVSUB_VX_MF2 + 0U, // PseudoVSUB_VX_MF2_MASK + 0U, // PseudoVSUB_VX_MF4 + 0U, // PseudoVSUB_VX_MF4_MASK + 0U, // PseudoVSUB_VX_MF8 + 0U, // PseudoVSUB_VX_MF8_MASK + 0U, // PseudoVSUXEI16_V_M1_M1 + 0U, // PseudoVSUXEI16_V_M1_M1_MASK + 0U, // PseudoVSUXEI16_V_M1_M2 + 0U, // PseudoVSUXEI16_V_M1_M2_MASK + 0U, // PseudoVSUXEI16_V_M1_M4 + 0U, // PseudoVSUXEI16_V_M1_M4_MASK + 0U, // PseudoVSUXEI16_V_M1_MF2 + 0U, // PseudoVSUXEI16_V_M1_MF2_MASK + 0U, // PseudoVSUXEI16_V_M2_M1 + 0U, // PseudoVSUXEI16_V_M2_M1_MASK + 0U, // PseudoVSUXEI16_V_M2_M2 + 0U, // PseudoVSUXEI16_V_M2_M2_MASK + 0U, // PseudoVSUXEI16_V_M2_M4 + 0U, // PseudoVSUXEI16_V_M2_M4_MASK + 0U, // PseudoVSUXEI16_V_M2_M8 + 0U, // PseudoVSUXEI16_V_M2_M8_MASK + 0U, // PseudoVSUXEI16_V_M4_M2 + 0U, // PseudoVSUXEI16_V_M4_M2_MASK + 0U, // PseudoVSUXEI16_V_M4_M4 + 0U, // PseudoVSUXEI16_V_M4_M4_MASK + 0U, // PseudoVSUXEI16_V_M4_M8 + 0U, // PseudoVSUXEI16_V_M4_M8_MASK + 0U, // PseudoVSUXEI16_V_M8_M4 + 0U, // PseudoVSUXEI16_V_M8_M4_MASK + 0U, // PseudoVSUXEI16_V_M8_M8 + 0U, // PseudoVSUXEI16_V_M8_M8_MASK + 0U, // PseudoVSUXEI16_V_MF2_M1 + 0U, // PseudoVSUXEI16_V_MF2_M1_MASK + 0U, // PseudoVSUXEI16_V_MF2_M2 + 0U, // PseudoVSUXEI16_V_MF2_M2_MASK + 0U, // PseudoVSUXEI16_V_MF2_MF2 + 0U, // PseudoVSUXEI16_V_MF2_MF2_MASK + 0U, // PseudoVSUXEI16_V_MF2_MF4 + 0U, // PseudoVSUXEI16_V_MF2_MF4_MASK + 0U, // PseudoVSUXEI16_V_MF4_M1 + 0U, // PseudoVSUXEI16_V_MF4_M1_MASK + 0U, // PseudoVSUXEI16_V_MF4_MF2 + 0U, // PseudoVSUXEI16_V_MF4_MF2_MASK + 0U, // PseudoVSUXEI16_V_MF4_MF4 + 0U, // PseudoVSUXEI16_V_MF4_MF4_MASK + 0U, // PseudoVSUXEI16_V_MF4_MF8 + 0U, // PseudoVSUXEI16_V_MF4_MF8_MASK + 0U, // PseudoVSUXEI32_V_M1_M1 + 0U, // PseudoVSUXEI32_V_M1_M1_MASK + 0U, // PseudoVSUXEI32_V_M1_M2 + 0U, // PseudoVSUXEI32_V_M1_M2_MASK + 0U, // PseudoVSUXEI32_V_M1_MF2 + 0U, // PseudoVSUXEI32_V_M1_MF2_MASK + 0U, // PseudoVSUXEI32_V_M1_MF4 + 0U, // PseudoVSUXEI32_V_M1_MF4_MASK + 0U, // PseudoVSUXEI32_V_M2_M1 + 0U, // PseudoVSUXEI32_V_M2_M1_MASK + 0U, // PseudoVSUXEI32_V_M2_M2 + 0U, // PseudoVSUXEI32_V_M2_M2_MASK + 0U, // PseudoVSUXEI32_V_M2_M4 + 0U, // PseudoVSUXEI32_V_M2_M4_MASK + 0U, // PseudoVSUXEI32_V_M2_MF2 + 0U, // PseudoVSUXEI32_V_M2_MF2_MASK + 0U, // PseudoVSUXEI32_V_M4_M1 + 0U, // PseudoVSUXEI32_V_M4_M1_MASK + 0U, // PseudoVSUXEI32_V_M4_M2 + 0U, // PseudoVSUXEI32_V_M4_M2_MASK + 0U, // PseudoVSUXEI32_V_M4_M4 + 0U, // PseudoVSUXEI32_V_M4_M4_MASK + 0U, // PseudoVSUXEI32_V_M4_M8 + 0U, // PseudoVSUXEI32_V_M4_M8_MASK + 0U, // PseudoVSUXEI32_V_M8_M2 + 0U, // PseudoVSUXEI32_V_M8_M2_MASK + 0U, // PseudoVSUXEI32_V_M8_M4 + 0U, // PseudoVSUXEI32_V_M8_M4_MASK + 0U, // PseudoVSUXEI32_V_M8_M8 + 0U, // PseudoVSUXEI32_V_M8_M8_MASK + 0U, // PseudoVSUXEI32_V_MF2_M1 + 0U, // PseudoVSUXEI32_V_MF2_M1_MASK + 0U, // PseudoVSUXEI32_V_MF2_MF2 + 0U, // PseudoVSUXEI32_V_MF2_MF2_MASK + 0U, // PseudoVSUXEI32_V_MF2_MF4 + 0U, // PseudoVSUXEI32_V_MF2_MF4_MASK + 0U, // PseudoVSUXEI32_V_MF2_MF8 + 0U, // PseudoVSUXEI32_V_MF2_MF8_MASK + 0U, // PseudoVSUXEI64_V_M1_M1 + 0U, // PseudoVSUXEI64_V_M1_M1_MASK + 0U, // PseudoVSUXEI64_V_M1_MF2 + 0U, // PseudoVSUXEI64_V_M1_MF2_MASK + 0U, // PseudoVSUXEI64_V_M1_MF4 + 0U, // PseudoVSUXEI64_V_M1_MF4_MASK + 0U, // PseudoVSUXEI64_V_M1_MF8 + 0U, // PseudoVSUXEI64_V_M1_MF8_MASK + 0U, // PseudoVSUXEI64_V_M2_M1 + 0U, // PseudoVSUXEI64_V_M2_M1_MASK + 0U, // PseudoVSUXEI64_V_M2_M2 + 0U, // PseudoVSUXEI64_V_M2_M2_MASK + 0U, // PseudoVSUXEI64_V_M2_MF2 + 0U, // PseudoVSUXEI64_V_M2_MF2_MASK + 0U, // PseudoVSUXEI64_V_M2_MF4 + 0U, // PseudoVSUXEI64_V_M2_MF4_MASK + 0U, // PseudoVSUXEI64_V_M4_M1 + 0U, // PseudoVSUXEI64_V_M4_M1_MASK + 0U, // PseudoVSUXEI64_V_M4_M2 + 0U, // PseudoVSUXEI64_V_M4_M2_MASK + 0U, // PseudoVSUXEI64_V_M4_M4 + 0U, // PseudoVSUXEI64_V_M4_M4_MASK + 0U, // PseudoVSUXEI64_V_M4_MF2 + 0U, // PseudoVSUXEI64_V_M4_MF2_MASK + 0U, // PseudoVSUXEI64_V_M8_M1 + 0U, // PseudoVSUXEI64_V_M8_M1_MASK + 0U, // PseudoVSUXEI64_V_M8_M2 + 0U, // PseudoVSUXEI64_V_M8_M2_MASK + 0U, // PseudoVSUXEI64_V_M8_M4 + 0U, // PseudoVSUXEI64_V_M8_M4_MASK + 0U, // PseudoVSUXEI64_V_M8_M8 + 0U, // PseudoVSUXEI64_V_M8_M8_MASK + 0U, // PseudoVSUXEI8_V_M1_M1 + 0U, // PseudoVSUXEI8_V_M1_M1_MASK + 0U, // PseudoVSUXEI8_V_M1_M2 + 0U, // PseudoVSUXEI8_V_M1_M2_MASK + 0U, // PseudoVSUXEI8_V_M1_M4 + 0U, // PseudoVSUXEI8_V_M1_M4_MASK + 0U, // PseudoVSUXEI8_V_M1_M8 + 0U, // PseudoVSUXEI8_V_M1_M8_MASK + 0U, // PseudoVSUXEI8_V_M2_M2 + 0U, // PseudoVSUXEI8_V_M2_M2_MASK + 0U, // PseudoVSUXEI8_V_M2_M4 + 0U, // PseudoVSUXEI8_V_M2_M4_MASK + 0U, // PseudoVSUXEI8_V_M2_M8 + 0U, // PseudoVSUXEI8_V_M2_M8_MASK + 0U, // PseudoVSUXEI8_V_M4_M4 + 0U, // PseudoVSUXEI8_V_M4_M4_MASK + 0U, // PseudoVSUXEI8_V_M4_M8 + 0U, // PseudoVSUXEI8_V_M4_M8_MASK + 0U, // PseudoVSUXEI8_V_M8_M8 + 0U, // PseudoVSUXEI8_V_M8_M8_MASK + 0U, // PseudoVSUXEI8_V_MF2_M1 + 0U, // PseudoVSUXEI8_V_MF2_M1_MASK + 0U, // PseudoVSUXEI8_V_MF2_M2 + 0U, // PseudoVSUXEI8_V_MF2_M2_MASK + 0U, // PseudoVSUXEI8_V_MF2_M4 + 0U, // PseudoVSUXEI8_V_MF2_M4_MASK + 0U, // PseudoVSUXEI8_V_MF2_MF2 + 0U, // PseudoVSUXEI8_V_MF2_MF2_MASK + 0U, // PseudoVSUXEI8_V_MF4_M1 + 0U, // PseudoVSUXEI8_V_MF4_M1_MASK + 0U, // PseudoVSUXEI8_V_MF4_M2 + 0U, // PseudoVSUXEI8_V_MF4_M2_MASK + 0U, // PseudoVSUXEI8_V_MF4_MF2 + 0U, // PseudoVSUXEI8_V_MF4_MF2_MASK + 0U, // PseudoVSUXEI8_V_MF4_MF4 + 0U, // PseudoVSUXEI8_V_MF4_MF4_MASK + 0U, // PseudoVSUXEI8_V_MF8_M1 + 0U, // PseudoVSUXEI8_V_MF8_M1_MASK + 0U, // PseudoVSUXEI8_V_MF8_MF2 + 0U, // PseudoVSUXEI8_V_MF8_MF2_MASK + 0U, // PseudoVSUXEI8_V_MF8_MF4 + 0U, // PseudoVSUXEI8_V_MF8_MF4_MASK + 0U, // PseudoVSUXEI8_V_MF8_MF8 + 0U, // PseudoVSUXEI8_V_MF8_MF8_MASK + 0U, // PseudoVSUXSEG2EI16_V_M1_M1 + 0U, // PseudoVSUXSEG2EI16_V_M1_M1_MASK + 0U, // PseudoVSUXSEG2EI16_V_M1_M2 + 0U, // PseudoVSUXSEG2EI16_V_M1_M2_MASK + 0U, // PseudoVSUXSEG2EI16_V_M1_M4 + 0U, // PseudoVSUXSEG2EI16_V_M1_M4_MASK + 0U, // PseudoVSUXSEG2EI16_V_M1_MF2 + 0U, // PseudoVSUXSEG2EI16_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG2EI16_V_M2_M1 + 0U, // PseudoVSUXSEG2EI16_V_M2_M1_MASK + 0U, // PseudoVSUXSEG2EI16_V_M2_M2 + 0U, // PseudoVSUXSEG2EI16_V_M2_M2_MASK + 0U, // PseudoVSUXSEG2EI16_V_M2_M4 + 0U, // PseudoVSUXSEG2EI16_V_M2_M4_MASK + 0U, // PseudoVSUXSEG2EI16_V_M4_M2 + 0U, // PseudoVSUXSEG2EI16_V_M4_M2_MASK + 0U, // PseudoVSUXSEG2EI16_V_M4_M4 + 0U, // PseudoVSUXSEG2EI16_V_M4_M4_MASK + 0U, // PseudoVSUXSEG2EI16_V_M8_M4 + 0U, // PseudoVSUXSEG2EI16_V_M8_M4_MASK + 0U, // PseudoVSUXSEG2EI16_V_MF2_M1 + 0U, // PseudoVSUXSEG2EI16_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG2EI16_V_MF2_M2 + 0U, // PseudoVSUXSEG2EI16_V_MF2_M2_MASK + 0U, // PseudoVSUXSEG2EI16_V_MF2_MF2 + 0U, // PseudoVSUXSEG2EI16_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG2EI16_V_MF2_MF4 + 0U, // PseudoVSUXSEG2EI16_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG2EI16_V_MF4_M1 + 0U, // PseudoVSUXSEG2EI16_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG2EI16_V_MF4_MF2 + 0U, // PseudoVSUXSEG2EI16_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG2EI16_V_MF4_MF4 + 0U, // PseudoVSUXSEG2EI16_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG2EI16_V_MF4_MF8 + 0U, // PseudoVSUXSEG2EI16_V_MF4_MF8_MASK + 0U, // PseudoVSUXSEG2EI32_V_M1_M1 + 0U, // PseudoVSUXSEG2EI32_V_M1_M1_MASK + 0U, // PseudoVSUXSEG2EI32_V_M1_M2 + 0U, // PseudoVSUXSEG2EI32_V_M1_M2_MASK + 0U, // PseudoVSUXSEG2EI32_V_M1_MF2 + 0U, // PseudoVSUXSEG2EI32_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG2EI32_V_M1_MF4 + 0U, // PseudoVSUXSEG2EI32_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG2EI32_V_M2_M1 + 0U, // PseudoVSUXSEG2EI32_V_M2_M1_MASK + 0U, // PseudoVSUXSEG2EI32_V_M2_M2 + 0U, // PseudoVSUXSEG2EI32_V_M2_M2_MASK + 0U, // PseudoVSUXSEG2EI32_V_M2_M4 + 0U, // PseudoVSUXSEG2EI32_V_M2_M4_MASK + 0U, // PseudoVSUXSEG2EI32_V_M2_MF2 + 0U, // PseudoVSUXSEG2EI32_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG2EI32_V_M4_M1 + 0U, // PseudoVSUXSEG2EI32_V_M4_M1_MASK + 0U, // PseudoVSUXSEG2EI32_V_M4_M2 + 0U, // PseudoVSUXSEG2EI32_V_M4_M2_MASK + 0U, // PseudoVSUXSEG2EI32_V_M4_M4 + 0U, // PseudoVSUXSEG2EI32_V_M4_M4_MASK + 0U, // PseudoVSUXSEG2EI32_V_M8_M2 + 0U, // PseudoVSUXSEG2EI32_V_M8_M2_MASK + 0U, // PseudoVSUXSEG2EI32_V_M8_M4 + 0U, // PseudoVSUXSEG2EI32_V_M8_M4_MASK + 0U, // PseudoVSUXSEG2EI32_V_MF2_M1 + 0U, // PseudoVSUXSEG2EI32_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG2EI32_V_MF2_MF2 + 0U, // PseudoVSUXSEG2EI32_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG2EI32_V_MF2_MF4 + 0U, // PseudoVSUXSEG2EI32_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG2EI32_V_MF2_MF8 + 0U, // PseudoVSUXSEG2EI32_V_MF2_MF8_MASK + 0U, // PseudoVSUXSEG2EI64_V_M1_M1 + 0U, // PseudoVSUXSEG2EI64_V_M1_M1_MASK + 0U, // PseudoVSUXSEG2EI64_V_M1_MF2 + 0U, // PseudoVSUXSEG2EI64_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG2EI64_V_M1_MF4 + 0U, // PseudoVSUXSEG2EI64_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG2EI64_V_M1_MF8 + 0U, // PseudoVSUXSEG2EI64_V_M1_MF8_MASK + 0U, // PseudoVSUXSEG2EI64_V_M2_M1 + 0U, // PseudoVSUXSEG2EI64_V_M2_M1_MASK + 0U, // PseudoVSUXSEG2EI64_V_M2_M2 + 0U, // PseudoVSUXSEG2EI64_V_M2_M2_MASK + 0U, // PseudoVSUXSEG2EI64_V_M2_MF2 + 0U, // PseudoVSUXSEG2EI64_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG2EI64_V_M2_MF4 + 0U, // PseudoVSUXSEG2EI64_V_M2_MF4_MASK + 0U, // PseudoVSUXSEG2EI64_V_M4_M1 + 0U, // PseudoVSUXSEG2EI64_V_M4_M1_MASK + 0U, // PseudoVSUXSEG2EI64_V_M4_M2 + 0U, // PseudoVSUXSEG2EI64_V_M4_M2_MASK + 0U, // PseudoVSUXSEG2EI64_V_M4_M4 + 0U, // PseudoVSUXSEG2EI64_V_M4_M4_MASK + 0U, // PseudoVSUXSEG2EI64_V_M4_MF2 + 0U, // PseudoVSUXSEG2EI64_V_M4_MF2_MASK + 0U, // PseudoVSUXSEG2EI64_V_M8_M1 + 0U, // PseudoVSUXSEG2EI64_V_M8_M1_MASK + 0U, // PseudoVSUXSEG2EI64_V_M8_M2 + 0U, // PseudoVSUXSEG2EI64_V_M8_M2_MASK + 0U, // PseudoVSUXSEG2EI64_V_M8_M4 + 0U, // PseudoVSUXSEG2EI64_V_M8_M4_MASK + 0U, // PseudoVSUXSEG2EI8_V_M1_M1 + 0U, // PseudoVSUXSEG2EI8_V_M1_M1_MASK + 0U, // PseudoVSUXSEG2EI8_V_M1_M2 + 0U, // PseudoVSUXSEG2EI8_V_M1_M2_MASK + 0U, // PseudoVSUXSEG2EI8_V_M1_M4 + 0U, // PseudoVSUXSEG2EI8_V_M1_M4_MASK + 0U, // PseudoVSUXSEG2EI8_V_M2_M2 + 0U, // PseudoVSUXSEG2EI8_V_M2_M2_MASK + 0U, // PseudoVSUXSEG2EI8_V_M2_M4 + 0U, // PseudoVSUXSEG2EI8_V_M2_M4_MASK + 0U, // PseudoVSUXSEG2EI8_V_M4_M4 + 0U, // PseudoVSUXSEG2EI8_V_M4_M4_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF2_M1 + 0U, // PseudoVSUXSEG2EI8_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF2_M2 + 0U, // PseudoVSUXSEG2EI8_V_MF2_M2_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF2_M4 + 0U, // PseudoVSUXSEG2EI8_V_MF2_M4_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF2_MF2 + 0U, // PseudoVSUXSEG2EI8_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF4_M1 + 0U, // PseudoVSUXSEG2EI8_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF4_M2 + 0U, // PseudoVSUXSEG2EI8_V_MF4_M2_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF4_MF2 + 0U, // PseudoVSUXSEG2EI8_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF4_MF4 + 0U, // PseudoVSUXSEG2EI8_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF8_M1 + 0U, // PseudoVSUXSEG2EI8_V_MF8_M1_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF8_MF2 + 0U, // PseudoVSUXSEG2EI8_V_MF8_MF2_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF8_MF4 + 0U, // PseudoVSUXSEG2EI8_V_MF8_MF4_MASK + 0U, // PseudoVSUXSEG2EI8_V_MF8_MF8 + 0U, // PseudoVSUXSEG2EI8_V_MF8_MF8_MASK + 0U, // PseudoVSUXSEG3EI16_V_M1_M1 + 0U, // PseudoVSUXSEG3EI16_V_M1_M1_MASK + 0U, // PseudoVSUXSEG3EI16_V_M1_M2 + 0U, // PseudoVSUXSEG3EI16_V_M1_M2_MASK + 0U, // PseudoVSUXSEG3EI16_V_M1_MF2 + 0U, // PseudoVSUXSEG3EI16_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG3EI16_V_M2_M1 + 0U, // PseudoVSUXSEG3EI16_V_M2_M1_MASK + 0U, // PseudoVSUXSEG3EI16_V_M2_M2 + 0U, // PseudoVSUXSEG3EI16_V_M2_M2_MASK + 0U, // PseudoVSUXSEG3EI16_V_M4_M2 + 0U, // PseudoVSUXSEG3EI16_V_M4_M2_MASK + 0U, // PseudoVSUXSEG3EI16_V_MF2_M1 + 0U, // PseudoVSUXSEG3EI16_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG3EI16_V_MF2_M2 + 0U, // PseudoVSUXSEG3EI16_V_MF2_M2_MASK + 0U, // PseudoVSUXSEG3EI16_V_MF2_MF2 + 0U, // PseudoVSUXSEG3EI16_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG3EI16_V_MF2_MF4 + 0U, // PseudoVSUXSEG3EI16_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG3EI16_V_MF4_M1 + 0U, // PseudoVSUXSEG3EI16_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG3EI16_V_MF4_MF2 + 0U, // PseudoVSUXSEG3EI16_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG3EI16_V_MF4_MF4 + 0U, // PseudoVSUXSEG3EI16_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG3EI16_V_MF4_MF8 + 0U, // PseudoVSUXSEG3EI16_V_MF4_MF8_MASK + 0U, // PseudoVSUXSEG3EI32_V_M1_M1 + 0U, // PseudoVSUXSEG3EI32_V_M1_M1_MASK + 0U, // PseudoVSUXSEG3EI32_V_M1_M2 + 0U, // PseudoVSUXSEG3EI32_V_M1_M2_MASK + 0U, // PseudoVSUXSEG3EI32_V_M1_MF2 + 0U, // PseudoVSUXSEG3EI32_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG3EI32_V_M1_MF4 + 0U, // PseudoVSUXSEG3EI32_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG3EI32_V_M2_M1 + 0U, // PseudoVSUXSEG3EI32_V_M2_M1_MASK + 0U, // PseudoVSUXSEG3EI32_V_M2_M2 + 0U, // PseudoVSUXSEG3EI32_V_M2_M2_MASK + 0U, // PseudoVSUXSEG3EI32_V_M2_MF2 + 0U, // PseudoVSUXSEG3EI32_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG3EI32_V_M4_M1 + 0U, // PseudoVSUXSEG3EI32_V_M4_M1_MASK + 0U, // PseudoVSUXSEG3EI32_V_M4_M2 + 0U, // PseudoVSUXSEG3EI32_V_M4_M2_MASK + 0U, // PseudoVSUXSEG3EI32_V_M8_M2 + 0U, // PseudoVSUXSEG3EI32_V_M8_M2_MASK + 0U, // PseudoVSUXSEG3EI32_V_MF2_M1 + 0U, // PseudoVSUXSEG3EI32_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG3EI32_V_MF2_MF2 + 0U, // PseudoVSUXSEG3EI32_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG3EI32_V_MF2_MF4 + 0U, // PseudoVSUXSEG3EI32_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG3EI32_V_MF2_MF8 + 0U, // PseudoVSUXSEG3EI32_V_MF2_MF8_MASK + 0U, // PseudoVSUXSEG3EI64_V_M1_M1 + 0U, // PseudoVSUXSEG3EI64_V_M1_M1_MASK + 0U, // PseudoVSUXSEG3EI64_V_M1_MF2 + 0U, // PseudoVSUXSEG3EI64_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG3EI64_V_M1_MF4 + 0U, // PseudoVSUXSEG3EI64_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG3EI64_V_M1_MF8 + 0U, // PseudoVSUXSEG3EI64_V_M1_MF8_MASK + 0U, // PseudoVSUXSEG3EI64_V_M2_M1 + 0U, // PseudoVSUXSEG3EI64_V_M2_M1_MASK + 0U, // PseudoVSUXSEG3EI64_V_M2_M2 + 0U, // PseudoVSUXSEG3EI64_V_M2_M2_MASK + 0U, // PseudoVSUXSEG3EI64_V_M2_MF2 + 0U, // PseudoVSUXSEG3EI64_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG3EI64_V_M2_MF4 + 0U, // PseudoVSUXSEG3EI64_V_M2_MF4_MASK + 0U, // PseudoVSUXSEG3EI64_V_M4_M1 + 0U, // PseudoVSUXSEG3EI64_V_M4_M1_MASK + 0U, // PseudoVSUXSEG3EI64_V_M4_M2 + 0U, // PseudoVSUXSEG3EI64_V_M4_M2_MASK + 0U, // PseudoVSUXSEG3EI64_V_M4_MF2 + 0U, // PseudoVSUXSEG3EI64_V_M4_MF2_MASK + 0U, // PseudoVSUXSEG3EI64_V_M8_M1 + 0U, // PseudoVSUXSEG3EI64_V_M8_M1_MASK + 0U, // PseudoVSUXSEG3EI64_V_M8_M2 + 0U, // PseudoVSUXSEG3EI64_V_M8_M2_MASK + 0U, // PseudoVSUXSEG3EI8_V_M1_M1 + 0U, // PseudoVSUXSEG3EI8_V_M1_M1_MASK + 0U, // PseudoVSUXSEG3EI8_V_M1_M2 + 0U, // PseudoVSUXSEG3EI8_V_M1_M2_MASK + 0U, // PseudoVSUXSEG3EI8_V_M2_M2 + 0U, // PseudoVSUXSEG3EI8_V_M2_M2_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF2_M1 + 0U, // PseudoVSUXSEG3EI8_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF2_M2 + 0U, // PseudoVSUXSEG3EI8_V_MF2_M2_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF2_MF2 + 0U, // PseudoVSUXSEG3EI8_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF4_M1 + 0U, // PseudoVSUXSEG3EI8_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF4_M2 + 0U, // PseudoVSUXSEG3EI8_V_MF4_M2_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF4_MF2 + 0U, // PseudoVSUXSEG3EI8_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF4_MF4 + 0U, // PseudoVSUXSEG3EI8_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF8_M1 + 0U, // PseudoVSUXSEG3EI8_V_MF8_M1_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF8_MF2 + 0U, // PseudoVSUXSEG3EI8_V_MF8_MF2_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF8_MF4 + 0U, // PseudoVSUXSEG3EI8_V_MF8_MF4_MASK + 0U, // PseudoVSUXSEG3EI8_V_MF8_MF8 + 0U, // PseudoVSUXSEG3EI8_V_MF8_MF8_MASK + 0U, // PseudoVSUXSEG4EI16_V_M1_M1 + 0U, // PseudoVSUXSEG4EI16_V_M1_M1_MASK + 0U, // PseudoVSUXSEG4EI16_V_M1_M2 + 0U, // PseudoVSUXSEG4EI16_V_M1_M2_MASK + 0U, // PseudoVSUXSEG4EI16_V_M1_MF2 + 0U, // PseudoVSUXSEG4EI16_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG4EI16_V_M2_M1 + 0U, // PseudoVSUXSEG4EI16_V_M2_M1_MASK + 0U, // PseudoVSUXSEG4EI16_V_M2_M2 + 0U, // PseudoVSUXSEG4EI16_V_M2_M2_MASK + 0U, // PseudoVSUXSEG4EI16_V_M4_M2 + 0U, // PseudoVSUXSEG4EI16_V_M4_M2_MASK + 0U, // PseudoVSUXSEG4EI16_V_MF2_M1 + 0U, // PseudoVSUXSEG4EI16_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG4EI16_V_MF2_M2 + 0U, // PseudoVSUXSEG4EI16_V_MF2_M2_MASK + 0U, // PseudoVSUXSEG4EI16_V_MF2_MF2 + 0U, // PseudoVSUXSEG4EI16_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG4EI16_V_MF2_MF4 + 0U, // PseudoVSUXSEG4EI16_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG4EI16_V_MF4_M1 + 0U, // PseudoVSUXSEG4EI16_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG4EI16_V_MF4_MF2 + 0U, // PseudoVSUXSEG4EI16_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG4EI16_V_MF4_MF4 + 0U, // PseudoVSUXSEG4EI16_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG4EI16_V_MF4_MF8 + 0U, // PseudoVSUXSEG4EI16_V_MF4_MF8_MASK + 0U, // PseudoVSUXSEG4EI32_V_M1_M1 + 0U, // PseudoVSUXSEG4EI32_V_M1_M1_MASK + 0U, // PseudoVSUXSEG4EI32_V_M1_M2 + 0U, // PseudoVSUXSEG4EI32_V_M1_M2_MASK + 0U, // PseudoVSUXSEG4EI32_V_M1_MF2 + 0U, // PseudoVSUXSEG4EI32_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG4EI32_V_M1_MF4 + 0U, // PseudoVSUXSEG4EI32_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG4EI32_V_M2_M1 + 0U, // PseudoVSUXSEG4EI32_V_M2_M1_MASK + 0U, // PseudoVSUXSEG4EI32_V_M2_M2 + 0U, // PseudoVSUXSEG4EI32_V_M2_M2_MASK + 0U, // PseudoVSUXSEG4EI32_V_M2_MF2 + 0U, // PseudoVSUXSEG4EI32_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG4EI32_V_M4_M1 + 0U, // PseudoVSUXSEG4EI32_V_M4_M1_MASK + 0U, // PseudoVSUXSEG4EI32_V_M4_M2 + 0U, // PseudoVSUXSEG4EI32_V_M4_M2_MASK + 0U, // PseudoVSUXSEG4EI32_V_M8_M2 + 0U, // PseudoVSUXSEG4EI32_V_M8_M2_MASK + 0U, // PseudoVSUXSEG4EI32_V_MF2_M1 + 0U, // PseudoVSUXSEG4EI32_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG4EI32_V_MF2_MF2 + 0U, // PseudoVSUXSEG4EI32_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG4EI32_V_MF2_MF4 + 0U, // PseudoVSUXSEG4EI32_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG4EI32_V_MF2_MF8 + 0U, // PseudoVSUXSEG4EI32_V_MF2_MF8_MASK + 0U, // PseudoVSUXSEG4EI64_V_M1_M1 + 0U, // PseudoVSUXSEG4EI64_V_M1_M1_MASK + 0U, // PseudoVSUXSEG4EI64_V_M1_MF2 + 0U, // PseudoVSUXSEG4EI64_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG4EI64_V_M1_MF4 + 0U, // PseudoVSUXSEG4EI64_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG4EI64_V_M1_MF8 + 0U, // PseudoVSUXSEG4EI64_V_M1_MF8_MASK + 0U, // PseudoVSUXSEG4EI64_V_M2_M1 + 0U, // PseudoVSUXSEG4EI64_V_M2_M1_MASK + 0U, // PseudoVSUXSEG4EI64_V_M2_M2 + 0U, // PseudoVSUXSEG4EI64_V_M2_M2_MASK + 0U, // PseudoVSUXSEG4EI64_V_M2_MF2 + 0U, // PseudoVSUXSEG4EI64_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG4EI64_V_M2_MF4 + 0U, // PseudoVSUXSEG4EI64_V_M2_MF4_MASK + 0U, // PseudoVSUXSEG4EI64_V_M4_M1 + 0U, // PseudoVSUXSEG4EI64_V_M4_M1_MASK + 0U, // PseudoVSUXSEG4EI64_V_M4_M2 + 0U, // PseudoVSUXSEG4EI64_V_M4_M2_MASK + 0U, // PseudoVSUXSEG4EI64_V_M4_MF2 + 0U, // PseudoVSUXSEG4EI64_V_M4_MF2_MASK + 0U, // PseudoVSUXSEG4EI64_V_M8_M1 + 0U, // PseudoVSUXSEG4EI64_V_M8_M1_MASK + 0U, // PseudoVSUXSEG4EI64_V_M8_M2 + 0U, // PseudoVSUXSEG4EI64_V_M8_M2_MASK + 0U, // PseudoVSUXSEG4EI8_V_M1_M1 + 0U, // PseudoVSUXSEG4EI8_V_M1_M1_MASK + 0U, // PseudoVSUXSEG4EI8_V_M1_M2 + 0U, // PseudoVSUXSEG4EI8_V_M1_M2_MASK + 0U, // PseudoVSUXSEG4EI8_V_M2_M2 + 0U, // PseudoVSUXSEG4EI8_V_M2_M2_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF2_M1 + 0U, // PseudoVSUXSEG4EI8_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF2_M2 + 0U, // PseudoVSUXSEG4EI8_V_MF2_M2_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF2_MF2 + 0U, // PseudoVSUXSEG4EI8_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF4_M1 + 0U, // PseudoVSUXSEG4EI8_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF4_M2 + 0U, // PseudoVSUXSEG4EI8_V_MF4_M2_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF4_MF2 + 0U, // PseudoVSUXSEG4EI8_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF4_MF4 + 0U, // PseudoVSUXSEG4EI8_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF8_M1 + 0U, // PseudoVSUXSEG4EI8_V_MF8_M1_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF8_MF2 + 0U, // PseudoVSUXSEG4EI8_V_MF8_MF2_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF8_MF4 + 0U, // PseudoVSUXSEG4EI8_V_MF8_MF4_MASK + 0U, // PseudoVSUXSEG4EI8_V_MF8_MF8 + 0U, // PseudoVSUXSEG4EI8_V_MF8_MF8_MASK + 0U, // PseudoVSUXSEG5EI16_V_M1_M1 + 0U, // PseudoVSUXSEG5EI16_V_M1_M1_MASK + 0U, // PseudoVSUXSEG5EI16_V_M1_MF2 + 0U, // PseudoVSUXSEG5EI16_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG5EI16_V_M2_M1 + 0U, // PseudoVSUXSEG5EI16_V_M2_M1_MASK + 0U, // PseudoVSUXSEG5EI16_V_MF2_M1 + 0U, // PseudoVSUXSEG5EI16_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG5EI16_V_MF2_MF2 + 0U, // PseudoVSUXSEG5EI16_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG5EI16_V_MF2_MF4 + 0U, // PseudoVSUXSEG5EI16_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG5EI16_V_MF4_M1 + 0U, // PseudoVSUXSEG5EI16_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG5EI16_V_MF4_MF2 + 0U, // PseudoVSUXSEG5EI16_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG5EI16_V_MF4_MF4 + 0U, // PseudoVSUXSEG5EI16_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG5EI16_V_MF4_MF8 + 0U, // PseudoVSUXSEG5EI16_V_MF4_MF8_MASK + 0U, // PseudoVSUXSEG5EI32_V_M1_M1 + 0U, // PseudoVSUXSEG5EI32_V_M1_M1_MASK + 0U, // PseudoVSUXSEG5EI32_V_M1_MF2 + 0U, // PseudoVSUXSEG5EI32_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG5EI32_V_M1_MF4 + 0U, // PseudoVSUXSEG5EI32_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG5EI32_V_M2_M1 + 0U, // PseudoVSUXSEG5EI32_V_M2_M1_MASK + 0U, // PseudoVSUXSEG5EI32_V_M2_MF2 + 0U, // PseudoVSUXSEG5EI32_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG5EI32_V_M4_M1 + 0U, // PseudoVSUXSEG5EI32_V_M4_M1_MASK + 0U, // PseudoVSUXSEG5EI32_V_MF2_M1 + 0U, // PseudoVSUXSEG5EI32_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG5EI32_V_MF2_MF2 + 0U, // PseudoVSUXSEG5EI32_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG5EI32_V_MF2_MF4 + 0U, // PseudoVSUXSEG5EI32_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG5EI32_V_MF2_MF8 + 0U, // PseudoVSUXSEG5EI32_V_MF2_MF8_MASK + 0U, // PseudoVSUXSEG5EI64_V_M1_M1 + 0U, // PseudoVSUXSEG5EI64_V_M1_M1_MASK + 0U, // PseudoVSUXSEG5EI64_V_M1_MF2 + 0U, // PseudoVSUXSEG5EI64_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG5EI64_V_M1_MF4 + 0U, // PseudoVSUXSEG5EI64_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG5EI64_V_M1_MF8 + 0U, // PseudoVSUXSEG5EI64_V_M1_MF8_MASK + 0U, // PseudoVSUXSEG5EI64_V_M2_M1 + 0U, // PseudoVSUXSEG5EI64_V_M2_M1_MASK + 0U, // PseudoVSUXSEG5EI64_V_M2_MF2 + 0U, // PseudoVSUXSEG5EI64_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG5EI64_V_M2_MF4 + 0U, // PseudoVSUXSEG5EI64_V_M2_MF4_MASK + 0U, // PseudoVSUXSEG5EI64_V_M4_M1 + 0U, // PseudoVSUXSEG5EI64_V_M4_M1_MASK + 0U, // PseudoVSUXSEG5EI64_V_M4_MF2 + 0U, // PseudoVSUXSEG5EI64_V_M4_MF2_MASK + 0U, // PseudoVSUXSEG5EI64_V_M8_M1 + 0U, // PseudoVSUXSEG5EI64_V_M8_M1_MASK + 0U, // PseudoVSUXSEG5EI8_V_M1_M1 + 0U, // PseudoVSUXSEG5EI8_V_M1_M1_MASK + 0U, // PseudoVSUXSEG5EI8_V_MF2_M1 + 0U, // PseudoVSUXSEG5EI8_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG5EI8_V_MF2_MF2 + 0U, // PseudoVSUXSEG5EI8_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG5EI8_V_MF4_M1 + 0U, // PseudoVSUXSEG5EI8_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG5EI8_V_MF4_MF2 + 0U, // PseudoVSUXSEG5EI8_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG5EI8_V_MF4_MF4 + 0U, // PseudoVSUXSEG5EI8_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG5EI8_V_MF8_M1 + 0U, // PseudoVSUXSEG5EI8_V_MF8_M1_MASK + 0U, // PseudoVSUXSEG5EI8_V_MF8_MF2 + 0U, // PseudoVSUXSEG5EI8_V_MF8_MF2_MASK + 0U, // PseudoVSUXSEG5EI8_V_MF8_MF4 + 0U, // PseudoVSUXSEG5EI8_V_MF8_MF4_MASK + 0U, // PseudoVSUXSEG5EI8_V_MF8_MF8 + 0U, // PseudoVSUXSEG5EI8_V_MF8_MF8_MASK + 0U, // PseudoVSUXSEG6EI16_V_M1_M1 + 0U, // PseudoVSUXSEG6EI16_V_M1_M1_MASK + 0U, // PseudoVSUXSEG6EI16_V_M1_MF2 + 0U, // PseudoVSUXSEG6EI16_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG6EI16_V_M2_M1 + 0U, // PseudoVSUXSEG6EI16_V_M2_M1_MASK + 0U, // PseudoVSUXSEG6EI16_V_MF2_M1 + 0U, // PseudoVSUXSEG6EI16_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG6EI16_V_MF2_MF2 + 0U, // PseudoVSUXSEG6EI16_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG6EI16_V_MF2_MF4 + 0U, // PseudoVSUXSEG6EI16_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG6EI16_V_MF4_M1 + 0U, // PseudoVSUXSEG6EI16_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG6EI16_V_MF4_MF2 + 0U, // PseudoVSUXSEG6EI16_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG6EI16_V_MF4_MF4 + 0U, // PseudoVSUXSEG6EI16_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG6EI16_V_MF4_MF8 + 0U, // PseudoVSUXSEG6EI16_V_MF4_MF8_MASK + 0U, // PseudoVSUXSEG6EI32_V_M1_M1 + 0U, // PseudoVSUXSEG6EI32_V_M1_M1_MASK + 0U, // PseudoVSUXSEG6EI32_V_M1_MF2 + 0U, // PseudoVSUXSEG6EI32_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG6EI32_V_M1_MF4 + 0U, // PseudoVSUXSEG6EI32_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG6EI32_V_M2_M1 + 0U, // PseudoVSUXSEG6EI32_V_M2_M1_MASK + 0U, // PseudoVSUXSEG6EI32_V_M2_MF2 + 0U, // PseudoVSUXSEG6EI32_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG6EI32_V_M4_M1 + 0U, // PseudoVSUXSEG6EI32_V_M4_M1_MASK + 0U, // PseudoVSUXSEG6EI32_V_MF2_M1 + 0U, // PseudoVSUXSEG6EI32_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG6EI32_V_MF2_MF2 + 0U, // PseudoVSUXSEG6EI32_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG6EI32_V_MF2_MF4 + 0U, // PseudoVSUXSEG6EI32_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG6EI32_V_MF2_MF8 + 0U, // PseudoVSUXSEG6EI32_V_MF2_MF8_MASK + 0U, // PseudoVSUXSEG6EI64_V_M1_M1 + 0U, // PseudoVSUXSEG6EI64_V_M1_M1_MASK + 0U, // PseudoVSUXSEG6EI64_V_M1_MF2 + 0U, // PseudoVSUXSEG6EI64_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG6EI64_V_M1_MF4 + 0U, // PseudoVSUXSEG6EI64_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG6EI64_V_M1_MF8 + 0U, // PseudoVSUXSEG6EI64_V_M1_MF8_MASK + 0U, // PseudoVSUXSEG6EI64_V_M2_M1 + 0U, // PseudoVSUXSEG6EI64_V_M2_M1_MASK + 0U, // PseudoVSUXSEG6EI64_V_M2_MF2 + 0U, // PseudoVSUXSEG6EI64_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG6EI64_V_M2_MF4 + 0U, // PseudoVSUXSEG6EI64_V_M2_MF4_MASK + 0U, // PseudoVSUXSEG6EI64_V_M4_M1 + 0U, // PseudoVSUXSEG6EI64_V_M4_M1_MASK + 0U, // PseudoVSUXSEG6EI64_V_M4_MF2 + 0U, // PseudoVSUXSEG6EI64_V_M4_MF2_MASK + 0U, // PseudoVSUXSEG6EI64_V_M8_M1 + 0U, // PseudoVSUXSEG6EI64_V_M8_M1_MASK + 0U, // PseudoVSUXSEG6EI8_V_M1_M1 + 0U, // PseudoVSUXSEG6EI8_V_M1_M1_MASK + 0U, // PseudoVSUXSEG6EI8_V_MF2_M1 + 0U, // PseudoVSUXSEG6EI8_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG6EI8_V_MF2_MF2 + 0U, // PseudoVSUXSEG6EI8_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG6EI8_V_MF4_M1 + 0U, // PseudoVSUXSEG6EI8_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG6EI8_V_MF4_MF2 + 0U, // PseudoVSUXSEG6EI8_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG6EI8_V_MF4_MF4 + 0U, // PseudoVSUXSEG6EI8_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG6EI8_V_MF8_M1 + 0U, // PseudoVSUXSEG6EI8_V_MF8_M1_MASK + 0U, // PseudoVSUXSEG6EI8_V_MF8_MF2 + 0U, // PseudoVSUXSEG6EI8_V_MF8_MF2_MASK + 0U, // PseudoVSUXSEG6EI8_V_MF8_MF4 + 0U, // PseudoVSUXSEG6EI8_V_MF8_MF4_MASK + 0U, // PseudoVSUXSEG6EI8_V_MF8_MF8 + 0U, // PseudoVSUXSEG6EI8_V_MF8_MF8_MASK + 0U, // PseudoVSUXSEG7EI16_V_M1_M1 + 0U, // PseudoVSUXSEG7EI16_V_M1_M1_MASK + 0U, // PseudoVSUXSEG7EI16_V_M1_MF2 + 0U, // PseudoVSUXSEG7EI16_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG7EI16_V_M2_M1 + 0U, // PseudoVSUXSEG7EI16_V_M2_M1_MASK + 0U, // PseudoVSUXSEG7EI16_V_MF2_M1 + 0U, // PseudoVSUXSEG7EI16_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG7EI16_V_MF2_MF2 + 0U, // PseudoVSUXSEG7EI16_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG7EI16_V_MF2_MF4 + 0U, // PseudoVSUXSEG7EI16_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG7EI16_V_MF4_M1 + 0U, // PseudoVSUXSEG7EI16_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG7EI16_V_MF4_MF2 + 0U, // PseudoVSUXSEG7EI16_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG7EI16_V_MF4_MF4 + 0U, // PseudoVSUXSEG7EI16_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG7EI16_V_MF4_MF8 + 0U, // PseudoVSUXSEG7EI16_V_MF4_MF8_MASK + 0U, // PseudoVSUXSEG7EI32_V_M1_M1 + 0U, // PseudoVSUXSEG7EI32_V_M1_M1_MASK + 0U, // PseudoVSUXSEG7EI32_V_M1_MF2 + 0U, // PseudoVSUXSEG7EI32_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG7EI32_V_M1_MF4 + 0U, // PseudoVSUXSEG7EI32_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG7EI32_V_M2_M1 + 0U, // PseudoVSUXSEG7EI32_V_M2_M1_MASK + 0U, // PseudoVSUXSEG7EI32_V_M2_MF2 + 0U, // PseudoVSUXSEG7EI32_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG7EI32_V_M4_M1 + 0U, // PseudoVSUXSEG7EI32_V_M4_M1_MASK + 0U, // PseudoVSUXSEG7EI32_V_MF2_M1 + 0U, // PseudoVSUXSEG7EI32_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG7EI32_V_MF2_MF2 + 0U, // PseudoVSUXSEG7EI32_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG7EI32_V_MF2_MF4 + 0U, // PseudoVSUXSEG7EI32_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG7EI32_V_MF2_MF8 + 0U, // PseudoVSUXSEG7EI32_V_MF2_MF8_MASK + 0U, // PseudoVSUXSEG7EI64_V_M1_M1 + 0U, // PseudoVSUXSEG7EI64_V_M1_M1_MASK + 0U, // PseudoVSUXSEG7EI64_V_M1_MF2 + 0U, // PseudoVSUXSEG7EI64_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG7EI64_V_M1_MF4 + 0U, // PseudoVSUXSEG7EI64_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG7EI64_V_M1_MF8 + 0U, // PseudoVSUXSEG7EI64_V_M1_MF8_MASK + 0U, // PseudoVSUXSEG7EI64_V_M2_M1 + 0U, // PseudoVSUXSEG7EI64_V_M2_M1_MASK + 0U, // PseudoVSUXSEG7EI64_V_M2_MF2 + 0U, // PseudoVSUXSEG7EI64_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG7EI64_V_M2_MF4 + 0U, // PseudoVSUXSEG7EI64_V_M2_MF4_MASK + 0U, // PseudoVSUXSEG7EI64_V_M4_M1 + 0U, // PseudoVSUXSEG7EI64_V_M4_M1_MASK + 0U, // PseudoVSUXSEG7EI64_V_M4_MF2 + 0U, // PseudoVSUXSEG7EI64_V_M4_MF2_MASK + 0U, // PseudoVSUXSEG7EI64_V_M8_M1 + 0U, // PseudoVSUXSEG7EI64_V_M8_M1_MASK + 0U, // PseudoVSUXSEG7EI8_V_M1_M1 + 0U, // PseudoVSUXSEG7EI8_V_M1_M1_MASK + 0U, // PseudoVSUXSEG7EI8_V_MF2_M1 + 0U, // PseudoVSUXSEG7EI8_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG7EI8_V_MF2_MF2 + 0U, // PseudoVSUXSEG7EI8_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG7EI8_V_MF4_M1 + 0U, // PseudoVSUXSEG7EI8_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG7EI8_V_MF4_MF2 + 0U, // PseudoVSUXSEG7EI8_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG7EI8_V_MF4_MF4 + 0U, // PseudoVSUXSEG7EI8_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG7EI8_V_MF8_M1 + 0U, // PseudoVSUXSEG7EI8_V_MF8_M1_MASK + 0U, // PseudoVSUXSEG7EI8_V_MF8_MF2 + 0U, // PseudoVSUXSEG7EI8_V_MF8_MF2_MASK + 0U, // PseudoVSUXSEG7EI8_V_MF8_MF4 + 0U, // PseudoVSUXSEG7EI8_V_MF8_MF4_MASK + 0U, // PseudoVSUXSEG7EI8_V_MF8_MF8 + 0U, // PseudoVSUXSEG7EI8_V_MF8_MF8_MASK + 0U, // PseudoVSUXSEG8EI16_V_M1_M1 + 0U, // PseudoVSUXSEG8EI16_V_M1_M1_MASK + 0U, // PseudoVSUXSEG8EI16_V_M1_MF2 + 0U, // PseudoVSUXSEG8EI16_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG8EI16_V_M2_M1 + 0U, // PseudoVSUXSEG8EI16_V_M2_M1_MASK + 0U, // PseudoVSUXSEG8EI16_V_MF2_M1 + 0U, // PseudoVSUXSEG8EI16_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG8EI16_V_MF2_MF2 + 0U, // PseudoVSUXSEG8EI16_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG8EI16_V_MF2_MF4 + 0U, // PseudoVSUXSEG8EI16_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG8EI16_V_MF4_M1 + 0U, // PseudoVSUXSEG8EI16_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG8EI16_V_MF4_MF2 + 0U, // PseudoVSUXSEG8EI16_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG8EI16_V_MF4_MF4 + 0U, // PseudoVSUXSEG8EI16_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG8EI16_V_MF4_MF8 + 0U, // PseudoVSUXSEG8EI16_V_MF4_MF8_MASK + 0U, // PseudoVSUXSEG8EI32_V_M1_M1 + 0U, // PseudoVSUXSEG8EI32_V_M1_M1_MASK + 0U, // PseudoVSUXSEG8EI32_V_M1_MF2 + 0U, // PseudoVSUXSEG8EI32_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG8EI32_V_M1_MF4 + 0U, // PseudoVSUXSEG8EI32_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG8EI32_V_M2_M1 + 0U, // PseudoVSUXSEG8EI32_V_M2_M1_MASK + 0U, // PseudoVSUXSEG8EI32_V_M2_MF2 + 0U, // PseudoVSUXSEG8EI32_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG8EI32_V_M4_M1 + 0U, // PseudoVSUXSEG8EI32_V_M4_M1_MASK + 0U, // PseudoVSUXSEG8EI32_V_MF2_M1 + 0U, // PseudoVSUXSEG8EI32_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG8EI32_V_MF2_MF2 + 0U, // PseudoVSUXSEG8EI32_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG8EI32_V_MF2_MF4 + 0U, // PseudoVSUXSEG8EI32_V_MF2_MF4_MASK + 0U, // PseudoVSUXSEG8EI32_V_MF2_MF8 + 0U, // PseudoVSUXSEG8EI32_V_MF2_MF8_MASK + 0U, // PseudoVSUXSEG8EI64_V_M1_M1 + 0U, // PseudoVSUXSEG8EI64_V_M1_M1_MASK + 0U, // PseudoVSUXSEG8EI64_V_M1_MF2 + 0U, // PseudoVSUXSEG8EI64_V_M1_MF2_MASK + 0U, // PseudoVSUXSEG8EI64_V_M1_MF4 + 0U, // PseudoVSUXSEG8EI64_V_M1_MF4_MASK + 0U, // PseudoVSUXSEG8EI64_V_M1_MF8 + 0U, // PseudoVSUXSEG8EI64_V_M1_MF8_MASK + 0U, // PseudoVSUXSEG8EI64_V_M2_M1 + 0U, // PseudoVSUXSEG8EI64_V_M2_M1_MASK + 0U, // PseudoVSUXSEG8EI64_V_M2_MF2 + 0U, // PseudoVSUXSEG8EI64_V_M2_MF2_MASK + 0U, // PseudoVSUXSEG8EI64_V_M2_MF4 + 0U, // PseudoVSUXSEG8EI64_V_M2_MF4_MASK + 0U, // PseudoVSUXSEG8EI64_V_M4_M1 + 0U, // PseudoVSUXSEG8EI64_V_M4_M1_MASK + 0U, // PseudoVSUXSEG8EI64_V_M4_MF2 + 0U, // PseudoVSUXSEG8EI64_V_M4_MF2_MASK + 0U, // PseudoVSUXSEG8EI64_V_M8_M1 + 0U, // PseudoVSUXSEG8EI64_V_M8_M1_MASK + 0U, // PseudoVSUXSEG8EI8_V_M1_M1 + 0U, // PseudoVSUXSEG8EI8_V_M1_M1_MASK + 0U, // PseudoVSUXSEG8EI8_V_MF2_M1 + 0U, // PseudoVSUXSEG8EI8_V_MF2_M1_MASK + 0U, // PseudoVSUXSEG8EI8_V_MF2_MF2 + 0U, // PseudoVSUXSEG8EI8_V_MF2_MF2_MASK + 0U, // PseudoVSUXSEG8EI8_V_MF4_M1 + 0U, // PseudoVSUXSEG8EI8_V_MF4_M1_MASK + 0U, // PseudoVSUXSEG8EI8_V_MF4_MF2 + 0U, // PseudoVSUXSEG8EI8_V_MF4_MF2_MASK + 0U, // PseudoVSUXSEG8EI8_V_MF4_MF4 + 0U, // PseudoVSUXSEG8EI8_V_MF4_MF4_MASK + 0U, // PseudoVSUXSEG8EI8_V_MF8_M1 + 0U, // PseudoVSUXSEG8EI8_V_MF8_M1_MASK + 0U, // PseudoVSUXSEG8EI8_V_MF8_MF2 + 0U, // PseudoVSUXSEG8EI8_V_MF8_MF2_MASK + 0U, // PseudoVSUXSEG8EI8_V_MF8_MF4 + 0U, // PseudoVSUXSEG8EI8_V_MF8_MF4_MASK + 0U, // PseudoVSUXSEG8EI8_V_MF8_MF8 + 0U, // PseudoVSUXSEG8EI8_V_MF8_MF8_MASK + 0U, // PseudoVWADDU_VV_M1 + 0U, // PseudoVWADDU_VV_M1_MASK + 0U, // PseudoVWADDU_VV_M2 + 0U, // PseudoVWADDU_VV_M2_MASK + 0U, // PseudoVWADDU_VV_M4 + 0U, // PseudoVWADDU_VV_M4_MASK + 0U, // PseudoVWADDU_VV_MF2 + 0U, // PseudoVWADDU_VV_MF2_MASK + 0U, // PseudoVWADDU_VV_MF4 + 0U, // PseudoVWADDU_VV_MF4_MASK + 0U, // PseudoVWADDU_VV_MF8 + 0U, // PseudoVWADDU_VV_MF8_MASK + 0U, // PseudoVWADDU_VX_M1 + 0U, // PseudoVWADDU_VX_M1_MASK + 0U, // PseudoVWADDU_VX_M2 + 0U, // PseudoVWADDU_VX_M2_MASK + 0U, // PseudoVWADDU_VX_M4 + 0U, // PseudoVWADDU_VX_M4_MASK + 0U, // PseudoVWADDU_VX_MF2 + 0U, // PseudoVWADDU_VX_MF2_MASK + 0U, // PseudoVWADDU_VX_MF4 + 0U, // PseudoVWADDU_VX_MF4_MASK + 0U, // PseudoVWADDU_VX_MF8 + 0U, // PseudoVWADDU_VX_MF8_MASK + 0U, // PseudoVWADDU_WV_M1 + 0U, // PseudoVWADDU_WV_M1_MASK + 0U, // PseudoVWADDU_WV_M1_MASK_TIED + 0U, // PseudoVWADDU_WV_M1_TIED + 0U, // PseudoVWADDU_WV_M2 + 0U, // PseudoVWADDU_WV_M2_MASK + 0U, // PseudoVWADDU_WV_M2_MASK_TIED + 0U, // PseudoVWADDU_WV_M2_TIED + 0U, // PseudoVWADDU_WV_M4 + 0U, // PseudoVWADDU_WV_M4_MASK + 0U, // PseudoVWADDU_WV_M4_MASK_TIED + 0U, // PseudoVWADDU_WV_M4_TIED + 0U, // PseudoVWADDU_WV_MF2 + 0U, // PseudoVWADDU_WV_MF2_MASK + 0U, // PseudoVWADDU_WV_MF2_MASK_TIED + 0U, // PseudoVWADDU_WV_MF2_TIED + 0U, // PseudoVWADDU_WV_MF4 + 0U, // PseudoVWADDU_WV_MF4_MASK + 0U, // PseudoVWADDU_WV_MF4_MASK_TIED + 0U, // PseudoVWADDU_WV_MF4_TIED + 0U, // PseudoVWADDU_WV_MF8 + 0U, // PseudoVWADDU_WV_MF8_MASK + 0U, // PseudoVWADDU_WV_MF8_MASK_TIED + 0U, // PseudoVWADDU_WV_MF8_TIED + 0U, // PseudoVWADDU_WX_M1 + 0U, // PseudoVWADDU_WX_M1_MASK + 0U, // PseudoVWADDU_WX_M2 + 0U, // PseudoVWADDU_WX_M2_MASK + 0U, // PseudoVWADDU_WX_M4 + 0U, // PseudoVWADDU_WX_M4_MASK + 0U, // PseudoVWADDU_WX_MF2 + 0U, // PseudoVWADDU_WX_MF2_MASK + 0U, // PseudoVWADDU_WX_MF4 + 0U, // PseudoVWADDU_WX_MF4_MASK + 0U, // PseudoVWADDU_WX_MF8 + 0U, // PseudoVWADDU_WX_MF8_MASK + 0U, // PseudoVWADD_VV_M1 + 0U, // PseudoVWADD_VV_M1_MASK + 0U, // PseudoVWADD_VV_M2 + 0U, // PseudoVWADD_VV_M2_MASK + 0U, // PseudoVWADD_VV_M4 + 0U, // PseudoVWADD_VV_M4_MASK + 0U, // PseudoVWADD_VV_MF2 + 0U, // PseudoVWADD_VV_MF2_MASK + 0U, // PseudoVWADD_VV_MF4 + 0U, // PseudoVWADD_VV_MF4_MASK + 0U, // PseudoVWADD_VV_MF8 + 0U, // PseudoVWADD_VV_MF8_MASK + 0U, // PseudoVWADD_VX_M1 + 0U, // PseudoVWADD_VX_M1_MASK + 0U, // PseudoVWADD_VX_M2 + 0U, // PseudoVWADD_VX_M2_MASK + 0U, // PseudoVWADD_VX_M4 + 0U, // PseudoVWADD_VX_M4_MASK + 0U, // PseudoVWADD_VX_MF2 + 0U, // PseudoVWADD_VX_MF2_MASK + 0U, // PseudoVWADD_VX_MF4 + 0U, // PseudoVWADD_VX_MF4_MASK + 0U, // PseudoVWADD_VX_MF8 + 0U, // PseudoVWADD_VX_MF8_MASK + 0U, // PseudoVWADD_WV_M1 + 0U, // PseudoVWADD_WV_M1_MASK + 0U, // PseudoVWADD_WV_M1_MASK_TIED + 0U, // PseudoVWADD_WV_M1_TIED + 0U, // PseudoVWADD_WV_M2 + 0U, // PseudoVWADD_WV_M2_MASK + 0U, // PseudoVWADD_WV_M2_MASK_TIED + 0U, // PseudoVWADD_WV_M2_TIED + 0U, // PseudoVWADD_WV_M4 + 0U, // PseudoVWADD_WV_M4_MASK + 0U, // PseudoVWADD_WV_M4_MASK_TIED + 0U, // PseudoVWADD_WV_M4_TIED + 0U, // PseudoVWADD_WV_MF2 + 0U, // PseudoVWADD_WV_MF2_MASK + 0U, // PseudoVWADD_WV_MF2_MASK_TIED + 0U, // PseudoVWADD_WV_MF2_TIED + 0U, // PseudoVWADD_WV_MF4 + 0U, // PseudoVWADD_WV_MF4_MASK + 0U, // PseudoVWADD_WV_MF4_MASK_TIED + 0U, // PseudoVWADD_WV_MF4_TIED + 0U, // PseudoVWADD_WV_MF8 + 0U, // PseudoVWADD_WV_MF8_MASK + 0U, // PseudoVWADD_WV_MF8_MASK_TIED + 0U, // PseudoVWADD_WV_MF8_TIED + 0U, // PseudoVWADD_WX_M1 + 0U, // PseudoVWADD_WX_M1_MASK + 0U, // PseudoVWADD_WX_M2 + 0U, // PseudoVWADD_WX_M2_MASK + 0U, // PseudoVWADD_WX_M4 + 0U, // PseudoVWADD_WX_M4_MASK + 0U, // PseudoVWADD_WX_MF2 + 0U, // PseudoVWADD_WX_MF2_MASK + 0U, // PseudoVWADD_WX_MF4 + 0U, // PseudoVWADD_WX_MF4_MASK + 0U, // PseudoVWADD_WX_MF8 + 0U, // PseudoVWADD_WX_MF8_MASK + 0U, // PseudoVWMACCSU_VV_M1 + 0U, // PseudoVWMACCSU_VV_M1_MASK + 0U, // PseudoVWMACCSU_VV_M2 + 0U, // PseudoVWMACCSU_VV_M2_MASK + 0U, // PseudoVWMACCSU_VV_M4 + 0U, // PseudoVWMACCSU_VV_M4_MASK + 0U, // PseudoVWMACCSU_VV_MF2 + 0U, // PseudoVWMACCSU_VV_MF2_MASK + 0U, // PseudoVWMACCSU_VV_MF4 + 0U, // PseudoVWMACCSU_VV_MF4_MASK + 0U, // PseudoVWMACCSU_VV_MF8 + 0U, // PseudoVWMACCSU_VV_MF8_MASK + 0U, // PseudoVWMACCSU_VX_M1 + 0U, // PseudoVWMACCSU_VX_M1_MASK + 0U, // PseudoVWMACCSU_VX_M2 + 0U, // PseudoVWMACCSU_VX_M2_MASK + 0U, // PseudoVWMACCSU_VX_M4 + 0U, // PseudoVWMACCSU_VX_M4_MASK + 0U, // PseudoVWMACCSU_VX_MF2 + 0U, // PseudoVWMACCSU_VX_MF2_MASK + 0U, // PseudoVWMACCSU_VX_MF4 + 0U, // PseudoVWMACCSU_VX_MF4_MASK + 0U, // PseudoVWMACCSU_VX_MF8 + 0U, // PseudoVWMACCSU_VX_MF8_MASK + 0U, // PseudoVWMACCUS_VX_M1 + 0U, // PseudoVWMACCUS_VX_M1_MASK + 0U, // PseudoVWMACCUS_VX_M2 + 0U, // PseudoVWMACCUS_VX_M2_MASK + 0U, // PseudoVWMACCUS_VX_M4 + 0U, // PseudoVWMACCUS_VX_M4_MASK + 0U, // PseudoVWMACCUS_VX_MF2 + 0U, // PseudoVWMACCUS_VX_MF2_MASK + 0U, // PseudoVWMACCUS_VX_MF4 + 0U, // PseudoVWMACCUS_VX_MF4_MASK + 0U, // PseudoVWMACCUS_VX_MF8 + 0U, // PseudoVWMACCUS_VX_MF8_MASK + 0U, // PseudoVWMACCU_VV_M1 + 0U, // PseudoVWMACCU_VV_M1_MASK + 0U, // PseudoVWMACCU_VV_M2 + 0U, // PseudoVWMACCU_VV_M2_MASK + 0U, // PseudoVWMACCU_VV_M4 + 0U, // PseudoVWMACCU_VV_M4_MASK + 0U, // PseudoVWMACCU_VV_MF2 + 0U, // PseudoVWMACCU_VV_MF2_MASK + 0U, // PseudoVWMACCU_VV_MF4 + 0U, // PseudoVWMACCU_VV_MF4_MASK + 0U, // PseudoVWMACCU_VV_MF8 + 0U, // PseudoVWMACCU_VV_MF8_MASK + 0U, // PseudoVWMACCU_VX_M1 + 0U, // PseudoVWMACCU_VX_M1_MASK + 0U, // PseudoVWMACCU_VX_M2 + 0U, // PseudoVWMACCU_VX_M2_MASK + 0U, // PseudoVWMACCU_VX_M4 + 0U, // PseudoVWMACCU_VX_M4_MASK + 0U, // PseudoVWMACCU_VX_MF2 + 0U, // PseudoVWMACCU_VX_MF2_MASK + 0U, // PseudoVWMACCU_VX_MF4 + 0U, // PseudoVWMACCU_VX_MF4_MASK + 0U, // PseudoVWMACCU_VX_MF8 + 0U, // PseudoVWMACCU_VX_MF8_MASK + 0U, // PseudoVWMACC_VV_M1 + 0U, // PseudoVWMACC_VV_M1_MASK + 0U, // PseudoVWMACC_VV_M2 + 0U, // PseudoVWMACC_VV_M2_MASK + 0U, // PseudoVWMACC_VV_M4 + 0U, // PseudoVWMACC_VV_M4_MASK + 0U, // PseudoVWMACC_VV_MF2 + 0U, // PseudoVWMACC_VV_MF2_MASK + 0U, // PseudoVWMACC_VV_MF4 + 0U, // PseudoVWMACC_VV_MF4_MASK + 0U, // PseudoVWMACC_VV_MF8 + 0U, // PseudoVWMACC_VV_MF8_MASK + 0U, // PseudoVWMACC_VX_M1 + 0U, // PseudoVWMACC_VX_M1_MASK + 0U, // PseudoVWMACC_VX_M2 + 0U, // PseudoVWMACC_VX_M2_MASK + 0U, // PseudoVWMACC_VX_M4 + 0U, // PseudoVWMACC_VX_M4_MASK + 0U, // PseudoVWMACC_VX_MF2 + 0U, // PseudoVWMACC_VX_MF2_MASK + 0U, // PseudoVWMACC_VX_MF4 + 0U, // PseudoVWMACC_VX_MF4_MASK + 0U, // PseudoVWMACC_VX_MF8 + 0U, // PseudoVWMACC_VX_MF8_MASK + 0U, // PseudoVWMULSU_VV_M1 + 0U, // PseudoVWMULSU_VV_M1_MASK + 0U, // PseudoVWMULSU_VV_M2 + 0U, // PseudoVWMULSU_VV_M2_MASK + 0U, // PseudoVWMULSU_VV_M4 + 0U, // PseudoVWMULSU_VV_M4_MASK + 0U, // PseudoVWMULSU_VV_MF2 + 0U, // PseudoVWMULSU_VV_MF2_MASK + 0U, // PseudoVWMULSU_VV_MF4 + 0U, // PseudoVWMULSU_VV_MF4_MASK + 0U, // PseudoVWMULSU_VV_MF8 + 0U, // PseudoVWMULSU_VV_MF8_MASK + 0U, // PseudoVWMULSU_VX_M1 + 0U, // PseudoVWMULSU_VX_M1_MASK + 0U, // PseudoVWMULSU_VX_M2 + 0U, // PseudoVWMULSU_VX_M2_MASK + 0U, // PseudoVWMULSU_VX_M4 + 0U, // PseudoVWMULSU_VX_M4_MASK + 0U, // PseudoVWMULSU_VX_MF2 + 0U, // PseudoVWMULSU_VX_MF2_MASK + 0U, // PseudoVWMULSU_VX_MF4 + 0U, // PseudoVWMULSU_VX_MF4_MASK + 0U, // PseudoVWMULSU_VX_MF8 + 0U, // PseudoVWMULSU_VX_MF8_MASK + 0U, // PseudoVWMULU_VV_M1 + 0U, // PseudoVWMULU_VV_M1_MASK + 0U, // PseudoVWMULU_VV_M2 + 0U, // PseudoVWMULU_VV_M2_MASK + 0U, // PseudoVWMULU_VV_M4 + 0U, // PseudoVWMULU_VV_M4_MASK + 0U, // PseudoVWMULU_VV_MF2 + 0U, // PseudoVWMULU_VV_MF2_MASK + 0U, // PseudoVWMULU_VV_MF4 + 0U, // PseudoVWMULU_VV_MF4_MASK + 0U, // PseudoVWMULU_VV_MF8 + 0U, // PseudoVWMULU_VV_MF8_MASK + 0U, // PseudoVWMULU_VX_M1 + 0U, // PseudoVWMULU_VX_M1_MASK + 0U, // PseudoVWMULU_VX_M2 + 0U, // PseudoVWMULU_VX_M2_MASK + 0U, // PseudoVWMULU_VX_M4 + 0U, // PseudoVWMULU_VX_M4_MASK + 0U, // PseudoVWMULU_VX_MF2 + 0U, // PseudoVWMULU_VX_MF2_MASK + 0U, // PseudoVWMULU_VX_MF4 + 0U, // PseudoVWMULU_VX_MF4_MASK + 0U, // PseudoVWMULU_VX_MF8 + 0U, // PseudoVWMULU_VX_MF8_MASK + 0U, // PseudoVWMUL_VV_M1 + 0U, // PseudoVWMUL_VV_M1_MASK + 0U, // PseudoVWMUL_VV_M2 + 0U, // PseudoVWMUL_VV_M2_MASK + 0U, // PseudoVWMUL_VV_M4 + 0U, // PseudoVWMUL_VV_M4_MASK + 0U, // PseudoVWMUL_VV_MF2 + 0U, // PseudoVWMUL_VV_MF2_MASK + 0U, // PseudoVWMUL_VV_MF4 + 0U, // PseudoVWMUL_VV_MF4_MASK + 0U, // PseudoVWMUL_VV_MF8 + 0U, // PseudoVWMUL_VV_MF8_MASK + 0U, // PseudoVWMUL_VX_M1 + 0U, // PseudoVWMUL_VX_M1_MASK + 0U, // PseudoVWMUL_VX_M2 + 0U, // PseudoVWMUL_VX_M2_MASK + 0U, // PseudoVWMUL_VX_M4 + 0U, // PseudoVWMUL_VX_M4_MASK + 0U, // PseudoVWMUL_VX_MF2 + 0U, // PseudoVWMUL_VX_MF2_MASK + 0U, // PseudoVWMUL_VX_MF4 + 0U, // PseudoVWMUL_VX_MF4_MASK + 0U, // PseudoVWMUL_VX_MF8 + 0U, // PseudoVWMUL_VX_MF8_MASK + 0U, // PseudoVWREDSUMU_VS_M1 + 0U, // PseudoVWREDSUMU_VS_M1_MASK + 0U, // PseudoVWREDSUMU_VS_M2 + 0U, // PseudoVWREDSUMU_VS_M2_MASK + 0U, // PseudoVWREDSUMU_VS_M4 + 0U, // PseudoVWREDSUMU_VS_M4_MASK + 0U, // PseudoVWREDSUMU_VS_M8 + 0U, // PseudoVWREDSUMU_VS_M8_MASK + 0U, // PseudoVWREDSUMU_VS_MF2 + 0U, // PseudoVWREDSUMU_VS_MF2_MASK + 0U, // PseudoVWREDSUMU_VS_MF4 + 0U, // PseudoVWREDSUMU_VS_MF4_MASK + 0U, // PseudoVWREDSUMU_VS_MF8 + 0U, // PseudoVWREDSUMU_VS_MF8_MASK + 0U, // PseudoVWREDSUM_VS_M1 + 0U, // PseudoVWREDSUM_VS_M1_MASK + 0U, // PseudoVWREDSUM_VS_M2 + 0U, // PseudoVWREDSUM_VS_M2_MASK + 0U, // PseudoVWREDSUM_VS_M4 + 0U, // PseudoVWREDSUM_VS_M4_MASK + 0U, // PseudoVWREDSUM_VS_M8 + 0U, // PseudoVWREDSUM_VS_M8_MASK + 0U, // PseudoVWREDSUM_VS_MF2 + 0U, // PseudoVWREDSUM_VS_MF2_MASK + 0U, // PseudoVWREDSUM_VS_MF4 + 0U, // PseudoVWREDSUM_VS_MF4_MASK + 0U, // PseudoVWREDSUM_VS_MF8 + 0U, // PseudoVWREDSUM_VS_MF8_MASK + 0U, // PseudoVWSUBU_VV_M1 + 0U, // PseudoVWSUBU_VV_M1_MASK + 0U, // PseudoVWSUBU_VV_M2 + 0U, // PseudoVWSUBU_VV_M2_MASK + 0U, // PseudoVWSUBU_VV_M4 + 0U, // PseudoVWSUBU_VV_M4_MASK + 0U, // PseudoVWSUBU_VV_MF2 + 0U, // PseudoVWSUBU_VV_MF2_MASK + 0U, // PseudoVWSUBU_VV_MF4 + 0U, // PseudoVWSUBU_VV_MF4_MASK + 0U, // PseudoVWSUBU_VV_MF8 + 0U, // PseudoVWSUBU_VV_MF8_MASK + 0U, // PseudoVWSUBU_VX_M1 + 0U, // PseudoVWSUBU_VX_M1_MASK + 0U, // PseudoVWSUBU_VX_M2 + 0U, // PseudoVWSUBU_VX_M2_MASK + 0U, // PseudoVWSUBU_VX_M4 + 0U, // PseudoVWSUBU_VX_M4_MASK + 0U, // PseudoVWSUBU_VX_MF2 + 0U, // PseudoVWSUBU_VX_MF2_MASK + 0U, // PseudoVWSUBU_VX_MF4 + 0U, // PseudoVWSUBU_VX_MF4_MASK + 0U, // PseudoVWSUBU_VX_MF8 + 0U, // PseudoVWSUBU_VX_MF8_MASK + 0U, // PseudoVWSUBU_WV_M1 + 0U, // PseudoVWSUBU_WV_M1_MASK + 0U, // PseudoVWSUBU_WV_M1_MASK_TIED + 0U, // PseudoVWSUBU_WV_M1_TIED + 0U, // PseudoVWSUBU_WV_M2 + 0U, // PseudoVWSUBU_WV_M2_MASK + 0U, // PseudoVWSUBU_WV_M2_MASK_TIED + 0U, // PseudoVWSUBU_WV_M2_TIED + 0U, // PseudoVWSUBU_WV_M4 + 0U, // PseudoVWSUBU_WV_M4_MASK + 0U, // PseudoVWSUBU_WV_M4_MASK_TIED + 0U, // PseudoVWSUBU_WV_M4_TIED + 0U, // PseudoVWSUBU_WV_MF2 + 0U, // PseudoVWSUBU_WV_MF2_MASK + 0U, // PseudoVWSUBU_WV_MF2_MASK_TIED + 0U, // PseudoVWSUBU_WV_MF2_TIED + 0U, // PseudoVWSUBU_WV_MF4 + 0U, // PseudoVWSUBU_WV_MF4_MASK + 0U, // PseudoVWSUBU_WV_MF4_MASK_TIED + 0U, // PseudoVWSUBU_WV_MF4_TIED + 0U, // PseudoVWSUBU_WV_MF8 + 0U, // PseudoVWSUBU_WV_MF8_MASK + 0U, // PseudoVWSUBU_WV_MF8_MASK_TIED + 0U, // PseudoVWSUBU_WV_MF8_TIED + 0U, // PseudoVWSUBU_WX_M1 + 0U, // PseudoVWSUBU_WX_M1_MASK + 0U, // PseudoVWSUBU_WX_M2 + 0U, // PseudoVWSUBU_WX_M2_MASK + 0U, // PseudoVWSUBU_WX_M4 + 0U, // PseudoVWSUBU_WX_M4_MASK + 0U, // PseudoVWSUBU_WX_MF2 + 0U, // PseudoVWSUBU_WX_MF2_MASK + 0U, // PseudoVWSUBU_WX_MF4 + 0U, // PseudoVWSUBU_WX_MF4_MASK + 0U, // PseudoVWSUBU_WX_MF8 + 0U, // PseudoVWSUBU_WX_MF8_MASK + 0U, // PseudoVWSUB_VV_M1 + 0U, // PseudoVWSUB_VV_M1_MASK + 0U, // PseudoVWSUB_VV_M2 + 0U, // PseudoVWSUB_VV_M2_MASK + 0U, // PseudoVWSUB_VV_M4 + 0U, // PseudoVWSUB_VV_M4_MASK + 0U, // PseudoVWSUB_VV_MF2 + 0U, // PseudoVWSUB_VV_MF2_MASK + 0U, // PseudoVWSUB_VV_MF4 + 0U, // PseudoVWSUB_VV_MF4_MASK + 0U, // PseudoVWSUB_VV_MF8 + 0U, // PseudoVWSUB_VV_MF8_MASK + 0U, // PseudoVWSUB_VX_M1 + 0U, // PseudoVWSUB_VX_M1_MASK + 0U, // PseudoVWSUB_VX_M2 + 0U, // PseudoVWSUB_VX_M2_MASK + 0U, // PseudoVWSUB_VX_M4 + 0U, // PseudoVWSUB_VX_M4_MASK + 0U, // PseudoVWSUB_VX_MF2 + 0U, // PseudoVWSUB_VX_MF2_MASK + 0U, // PseudoVWSUB_VX_MF4 + 0U, // PseudoVWSUB_VX_MF4_MASK + 0U, // PseudoVWSUB_VX_MF8 + 0U, // PseudoVWSUB_VX_MF8_MASK + 0U, // PseudoVWSUB_WV_M1 + 0U, // PseudoVWSUB_WV_M1_MASK + 0U, // PseudoVWSUB_WV_M1_MASK_TIED + 0U, // PseudoVWSUB_WV_M1_TIED + 0U, // PseudoVWSUB_WV_M2 + 0U, // PseudoVWSUB_WV_M2_MASK + 0U, // PseudoVWSUB_WV_M2_MASK_TIED + 0U, // PseudoVWSUB_WV_M2_TIED + 0U, // PseudoVWSUB_WV_M4 + 0U, // PseudoVWSUB_WV_M4_MASK + 0U, // PseudoVWSUB_WV_M4_MASK_TIED + 0U, // PseudoVWSUB_WV_M4_TIED + 0U, // PseudoVWSUB_WV_MF2 + 0U, // PseudoVWSUB_WV_MF2_MASK + 0U, // PseudoVWSUB_WV_MF2_MASK_TIED + 0U, // PseudoVWSUB_WV_MF2_TIED + 0U, // PseudoVWSUB_WV_MF4 + 0U, // PseudoVWSUB_WV_MF4_MASK + 0U, // PseudoVWSUB_WV_MF4_MASK_TIED + 0U, // PseudoVWSUB_WV_MF4_TIED + 0U, // PseudoVWSUB_WV_MF8 + 0U, // PseudoVWSUB_WV_MF8_MASK + 0U, // PseudoVWSUB_WV_MF8_MASK_TIED + 0U, // PseudoVWSUB_WV_MF8_TIED + 0U, // PseudoVWSUB_WX_M1 + 0U, // PseudoVWSUB_WX_M1_MASK + 0U, // PseudoVWSUB_WX_M2 + 0U, // PseudoVWSUB_WX_M2_MASK + 0U, // PseudoVWSUB_WX_M4 + 0U, // PseudoVWSUB_WX_M4_MASK + 0U, // PseudoVWSUB_WX_MF2 + 0U, // PseudoVWSUB_WX_MF2_MASK + 0U, // PseudoVWSUB_WX_MF4 + 0U, // PseudoVWSUB_WX_MF4_MASK + 0U, // PseudoVWSUB_WX_MF8 + 0U, // PseudoVWSUB_WX_MF8_MASK + 0U, // PseudoVXOR_VI_M1 + 0U, // PseudoVXOR_VI_M1_MASK + 0U, // PseudoVXOR_VI_M2 + 0U, // PseudoVXOR_VI_M2_MASK + 0U, // PseudoVXOR_VI_M4 + 0U, // PseudoVXOR_VI_M4_MASK + 0U, // PseudoVXOR_VI_M8 + 0U, // PseudoVXOR_VI_M8_MASK + 0U, // PseudoVXOR_VI_MF2 + 0U, // PseudoVXOR_VI_MF2_MASK + 0U, // PseudoVXOR_VI_MF4 + 0U, // PseudoVXOR_VI_MF4_MASK + 0U, // PseudoVXOR_VI_MF8 + 0U, // PseudoVXOR_VI_MF8_MASK + 0U, // PseudoVXOR_VV_M1 + 0U, // PseudoVXOR_VV_M1_MASK + 0U, // PseudoVXOR_VV_M2 + 0U, // PseudoVXOR_VV_M2_MASK + 0U, // PseudoVXOR_VV_M4 + 0U, // PseudoVXOR_VV_M4_MASK + 0U, // PseudoVXOR_VV_M8 + 0U, // PseudoVXOR_VV_M8_MASK + 0U, // PseudoVXOR_VV_MF2 + 0U, // PseudoVXOR_VV_MF2_MASK + 0U, // PseudoVXOR_VV_MF4 + 0U, // PseudoVXOR_VV_MF4_MASK + 0U, // PseudoVXOR_VV_MF8 + 0U, // PseudoVXOR_VV_MF8_MASK + 0U, // PseudoVXOR_VX_M1 + 0U, // PseudoVXOR_VX_M1_MASK + 0U, // PseudoVXOR_VX_M2 + 0U, // PseudoVXOR_VX_M2_MASK + 0U, // PseudoVXOR_VX_M4 + 0U, // PseudoVXOR_VX_M4_MASK + 0U, // PseudoVXOR_VX_M8 + 0U, // PseudoVXOR_VX_M8_MASK + 0U, // PseudoVXOR_VX_MF2 + 0U, // PseudoVXOR_VX_MF2_MASK + 0U, // PseudoVXOR_VX_MF4 + 0U, // PseudoVXOR_VX_MF4_MASK + 0U, // PseudoVXOR_VX_MF8 + 0U, // PseudoVXOR_VX_MF8_MASK + 0U, // PseudoVZEXT_VF2_M1 + 0U, // PseudoVZEXT_VF2_M1_MASK + 0U, // PseudoVZEXT_VF2_M2 + 0U, // PseudoVZEXT_VF2_M2_MASK + 0U, // PseudoVZEXT_VF2_M4 + 0U, // PseudoVZEXT_VF2_M4_MASK + 0U, // PseudoVZEXT_VF2_M8 + 0U, // PseudoVZEXT_VF2_M8_MASK + 0U, // PseudoVZEXT_VF2_MF2 + 0U, // PseudoVZEXT_VF2_MF2_MASK + 0U, // PseudoVZEXT_VF2_MF4 + 0U, // PseudoVZEXT_VF2_MF4_MASK + 0U, // PseudoVZEXT_VF4_M1 + 0U, // PseudoVZEXT_VF4_M1_MASK + 0U, // PseudoVZEXT_VF4_M2 + 0U, // PseudoVZEXT_VF4_M2_MASK + 0U, // PseudoVZEXT_VF4_M4 + 0U, // PseudoVZEXT_VF4_M4_MASK + 0U, // PseudoVZEXT_VF4_M8 + 0U, // PseudoVZEXT_VF4_M8_MASK + 0U, // PseudoVZEXT_VF4_MF2 + 0U, // PseudoVZEXT_VF4_MF2_MASK + 0U, // PseudoVZEXT_VF8_M1 + 0U, // PseudoVZEXT_VF8_M1_MASK + 0U, // PseudoVZEXT_VF8_M2 + 0U, // PseudoVZEXT_VF8_M2_MASK + 0U, // PseudoVZEXT_VF8_M4 + 0U, // PseudoVZEXT_VF8_M4_MASK + 0U, // PseudoVZEXT_VF8_M8 + 0U, // PseudoVZEXT_VF8_M8_MASK + 0U, // PseudoZEXT_H + 0U, // PseudoZEXT_W + 0U, // ReadCycleWide + 0U, // ReadFRM + 0U, // Select_FPR16_Using_CC_GPR + 0U, // Select_FPR32_Using_CC_GPR + 0U, // Select_FPR64_Using_CC_GPR + 0U, // Select_GPR_Using_CC_GPR + 0U, // SplitF64Pseudo + 0U, // WriteFRM + 0U, // WriteFRMImm + 0U, // ADD + 0U, // ADDI + 0U, // ADDIW + 0U, // ADDUW + 0U, // ADDW + 0U, // AMOADD_D + 0U, // AMOADD_D_AQ + 0U, // AMOADD_D_AQ_RL + 0U, // AMOADD_D_RL + 0U, // AMOADD_W + 0U, // AMOADD_W_AQ + 0U, // AMOADD_W_AQ_RL + 0U, // AMOADD_W_RL + 0U, // AMOAND_D + 0U, // AMOAND_D_AQ + 0U, // AMOAND_D_AQ_RL + 0U, // AMOAND_D_RL + 0U, // AMOAND_W + 0U, // AMOAND_W_AQ + 0U, // AMOAND_W_AQ_RL + 0U, // AMOAND_W_RL + 0U, // AMOMAXU_D + 0U, // AMOMAXU_D_AQ + 0U, // AMOMAXU_D_AQ_RL + 0U, // AMOMAXU_D_RL + 0U, // AMOMAXU_W + 0U, // AMOMAXU_W_AQ + 0U, // AMOMAXU_W_AQ_RL + 0U, // AMOMAXU_W_RL + 0U, // AMOMAX_D + 0U, // AMOMAX_D_AQ + 0U, // AMOMAX_D_AQ_RL + 0U, // AMOMAX_D_RL + 0U, // AMOMAX_W + 0U, // AMOMAX_W_AQ + 0U, // AMOMAX_W_AQ_RL + 0U, // AMOMAX_W_RL + 0U, // AMOMINU_D + 0U, // AMOMINU_D_AQ + 0U, // AMOMINU_D_AQ_RL + 0U, // AMOMINU_D_RL + 0U, // AMOMINU_W + 0U, // AMOMINU_W_AQ + 0U, // AMOMINU_W_AQ_RL + 0U, // AMOMINU_W_RL + 0U, // AMOMIN_D + 0U, // AMOMIN_D_AQ + 0U, // AMOMIN_D_AQ_RL + 0U, // AMOMIN_D_RL + 0U, // AMOMIN_W + 0U, // AMOMIN_W_AQ + 0U, // AMOMIN_W_AQ_RL + 0U, // AMOMIN_W_RL + 0U, // AMOOR_D + 0U, // AMOOR_D_AQ + 0U, // AMOOR_D_AQ_RL + 0U, // AMOOR_D_RL + 0U, // AMOOR_W + 0U, // AMOOR_W_AQ + 0U, // AMOOR_W_AQ_RL + 0U, // AMOOR_W_RL + 0U, // AMOSWAP_D + 0U, // AMOSWAP_D_AQ + 0U, // AMOSWAP_D_AQ_RL + 0U, // AMOSWAP_D_RL + 0U, // AMOSWAP_W + 0U, // AMOSWAP_W_AQ + 0U, // AMOSWAP_W_AQ_RL + 0U, // AMOSWAP_W_RL + 0U, // AMOXOR_D + 0U, // AMOXOR_D_AQ + 0U, // AMOXOR_D_AQ_RL + 0U, // AMOXOR_D_RL + 0U, // AMOXOR_W + 0U, // AMOXOR_W_AQ + 0U, // AMOXOR_W_AQ_RL + 0U, // AMOXOR_W_RL + 0U, // AND + 0U, // ANDI + 0U, // ANDN + 0U, // AUIPC + 0U, // BCLR + 0U, // BCLRI + 0U, // BCOMPRESS + 0U, // BCOMPRESSW + 0U, // BDECOMPRESS + 0U, // BDECOMPRESSW + 0U, // BEQ + 0U, // BEXT + 0U, // BEXTI + 0U, // BFP + 0U, // BFPW + 0U, // BGE + 0U, // BGEU + 0U, // BINV + 0U, // BINVI + 0U, // BLT + 0U, // BLTU + 0U, // BMATFLIP + 0U, // BMATOR + 0U, // BMATXOR + 0U, // BNE + 0U, // BSET + 0U, // BSETI + 0U, // CLMUL + 0U, // CLMULH + 0U, // CLMULR + 0U, // CLZ + 0U, // CLZW + 0U, // CMIX + 0U, // CMOV + 0U, // CPOP + 0U, // CPOPW + 0U, // CRC32B + 0U, // CRC32CB + 0U, // CRC32CD + 0U, // CRC32CH + 0U, // CRC32CW + 0U, // CRC32D + 0U, // CRC32H + 0U, // CRC32W + 0U, // CSRRC + 0U, // CSRRCI + 0U, // CSRRS + 0U, // CSRRSI + 0U, // CSRRW + 0U, // CSRRWI + 0U, // CTZ + 0U, // CTZW + 0U, // C_ADD + 0U, // C_ADDI + 0U, // C_ADDI16SP + 0U, // C_ADDI4SPN + 0U, // C_ADDIW + 0U, // C_ADDI_HINT_IMM_ZERO + 0U, // C_ADDI_HINT_X0 + 0U, // C_ADDI_NOP + 0U, // C_ADDW + 0U, // C_ADD_HINT + 0U, // C_AND + 0U, // C_ANDI + 0U, // C_BEQZ + 0U, // C_BNEZ + 0U, // C_EBREAK + 0U, // C_FLD + 0U, // C_FLDSP + 0U, // C_FLW + 0U, // C_FLWSP + 0U, // C_FSD + 0U, // C_FSDSP + 0U, // C_FSW + 0U, // C_FSWSP + 0U, // C_J + 0U, // C_JAL + 0U, // C_JALR + 0U, // C_JR + 0U, // C_LD + 0U, // C_LDSP + 0U, // C_LI + 0U, // C_LI_HINT + 0U, // C_LUI + 0U, // C_LUI_HINT + 0U, // C_LW + 0U, // C_LWSP + 0U, // C_MV + 0U, // C_MV_HINT + 0U, // C_NOP + 0U, // C_NOP_HINT + 0U, // C_OR + 0U, // C_SD + 0U, // C_SDSP + 0U, // C_SLLI + 0U, // C_SLLI64_HINT + 0U, // C_SLLI_HINT + 0U, // C_SRAI + 0U, // C_SRAI64_HINT + 0U, // C_SRLI + 0U, // C_SRLI64_HINT + 0U, // C_SUB + 0U, // C_SUBW + 0U, // C_SW + 0U, // C_SWSP + 0U, // C_UNIMP + 0U, // C_XOR + 0U, // DIV + 0U, // DIVU + 0U, // DIVUW + 0U, // DIVW + 0U, // DRET + 0U, // EBREAK + 0U, // ECALL + 2U, // FADD_D + 2U, // FADD_H + 2U, // FADD_S + 0U, // FCLASS_D + 0U, // FCLASS_H + 0U, // FCLASS_S + 0U, // FCVT_D_H + 0U, // FCVT_D_L + 0U, // FCVT_D_LU + 0U, // FCVT_D_S + 0U, // FCVT_D_W + 0U, // FCVT_D_WU + 0U, // FCVT_H_D + 0U, // FCVT_H_L + 0U, // FCVT_H_LU + 0U, // FCVT_H_S + 0U, // FCVT_H_W + 0U, // FCVT_H_WU + 0U, // FCVT_LU_D + 0U, // FCVT_LU_H + 0U, // FCVT_LU_S + 0U, // FCVT_L_D + 0U, // FCVT_L_H + 0U, // FCVT_L_S + 0U, // FCVT_S_D + 0U, // FCVT_S_H + 0U, // FCVT_S_L + 0U, // FCVT_S_LU + 0U, // FCVT_S_W + 0U, // FCVT_S_WU + 0U, // FCVT_WU_D + 0U, // FCVT_WU_H + 0U, // FCVT_WU_S + 0U, // FCVT_W_D + 0U, // FCVT_W_H + 0U, // FCVT_W_S + 2U, // FDIV_D + 2U, // FDIV_H + 2U, // FDIV_S + 0U, // FENCE + 0U, // FENCE_I + 0U, // FENCE_TSO + 0U, // FEQ_D + 0U, // FEQ_H + 0U, // FEQ_S + 0U, // FLD + 0U, // FLE_D + 0U, // FLE_H + 0U, // FLE_S + 0U, // FLH + 0U, // FLT_D + 0U, // FLT_H + 0U, // FLT_S + 0U, // FLW + 8U, // FMADD_D + 8U, // FMADD_H + 8U, // FMADD_S + 0U, // FMAX_D + 0U, // FMAX_H + 0U, // FMAX_S + 0U, // FMIN_D + 0U, // FMIN_H + 0U, // FMIN_S + 8U, // FMSUB_D + 8U, // FMSUB_H + 8U, // FMSUB_S + 2U, // FMUL_D + 2U, // FMUL_H + 2U, // FMUL_S + 0U, // FMV_D_X + 0U, // FMV_H_X + 0U, // FMV_W_X + 0U, // FMV_X_D + 0U, // FMV_X_H + 0U, // FMV_X_W + 8U, // FNMADD_D + 8U, // FNMADD_H + 8U, // FNMADD_S + 8U, // FNMSUB_D + 8U, // FNMSUB_H + 8U, // FNMSUB_S + 0U, // FSD + 0U, // FSGNJN_D + 0U, // FSGNJN_H + 0U, // FSGNJN_S + 0U, // FSGNJX_D + 0U, // FSGNJX_H + 0U, // FSGNJX_S + 0U, // FSGNJ_D + 0U, // FSGNJ_H + 0U, // FSGNJ_S + 0U, // FSH + 3U, // FSL + 3U, // FSLW + 0U, // FSQRT_D + 0U, // FSQRT_H + 0U, // FSQRT_S + 3U, // FSR + 0U, // FSRI + 0U, // FSRIW + 3U, // FSRW + 2U, // FSUB_D + 2U, // FSUB_H + 2U, // FSUB_S + 0U, // FSW + 0U, // GORC + 0U, // GORCI + 0U, // GORCIW + 0U, // GORCW + 0U, // GREV + 0U, // GREVI + 0U, // GREVIW + 0U, // GREVW + 24U, // InsnB + 40U, // InsnI + 4U, // InsnI_Mem + 0U, // InsnJ + 5U, // InsnR + 61U, // InsnR4 + 4U, // InsnS + 0U, // InsnU + 0U, // JAL + 0U, // JALR + 0U, // LB + 0U, // LBU + 0U, // LD + 0U, // LH + 0U, // LHU + 0U, // LR_D + 0U, // LR_D_AQ + 0U, // LR_D_AQ_RL + 0U, // LR_D_RL + 0U, // LR_W + 0U, // LR_W_AQ + 0U, // LR_W_AQ_RL + 0U, // LR_W_RL + 0U, // LUI + 0U, // LW + 0U, // LWU + 0U, // MAX + 0U, // MAXU + 0U, // MIN + 0U, // MINU + 0U, // MRET + 0U, // MUL + 0U, // MULH + 0U, // MULHSU + 0U, // MULHU + 0U, // MULW + 0U, // OR + 0U, // ORCB + 0U, // ORI + 0U, // ORN + 0U, // PACK + 0U, // PACKH + 0U, // PACKU + 0U, // PACKUW + 0U, // PACKW + 0U, // REM + 0U, // REMU + 0U, // REMUW + 0U, // REMW + 0U, // REV8_RV32 + 0U, // REV8_RV64 + 0U, // ROL + 0U, // ROLW + 0U, // ROR + 0U, // RORI + 0U, // RORIW + 0U, // RORW + 0U, // SB + 0U, // SC_D + 0U, // SC_D_AQ + 0U, // SC_D_AQ_RL + 0U, // SC_D_RL + 0U, // SC_W + 0U, // SC_W_AQ + 0U, // SC_W_AQ_RL + 0U, // SC_W_RL + 0U, // SD + 0U, // SEXTB + 0U, // SEXTH + 0U, // SFENCE_VMA + 0U, // SH + 0U, // SH1ADD + 0U, // SH1ADDUW + 0U, // SH2ADD + 0U, // SH2ADDUW + 0U, // SH3ADD + 0U, // SH3ADDUW + 0U, // SHFL + 0U, // SHFLI + 0U, // SHFLW + 0U, // SLL + 0U, // SLLI + 0U, // SLLIUW + 0U, // SLLIW + 0U, // SLLW + 0U, // SLT + 0U, // SLTI + 0U, // SLTIU + 0U, // SLTU + 0U, // SRA + 0U, // SRAI + 0U, // SRAIW + 0U, // SRAW + 0U, // SRET + 0U, // SRL + 0U, // SRLI + 0U, // SRLIW + 0U, // SRLW + 0U, // SUB + 0U, // SUBW + 0U, // SW + 0U, // UNIMP + 0U, // UNSHFL + 0U, // UNSHFLI + 0U, // UNSHFLW + 0U, // URET + 0U, // VAADDU_VV + 0U, // VAADDU_VX + 0U, // VAADD_VV + 0U, // VAADD_VX + 0U, // VADC_VIM + 0U, // VADC_VVM + 0U, // VADC_VXM + 0U, // VADD_VI + 0U, // VADD_VV + 0U, // VADD_VX + 0U, // VAMOADDEI16_UNWD + 6U, // VAMOADDEI16_WD + 0U, // VAMOADDEI32_UNWD + 6U, // VAMOADDEI32_WD + 0U, // VAMOADDEI64_UNWD + 6U, // VAMOADDEI64_WD + 0U, // VAMOADDEI8_UNWD + 6U, // VAMOADDEI8_WD + 0U, // VAMOANDEI16_UNWD + 6U, // VAMOANDEI16_WD + 0U, // VAMOANDEI32_UNWD + 6U, // VAMOANDEI32_WD + 0U, // VAMOANDEI64_UNWD + 6U, // VAMOANDEI64_WD + 0U, // VAMOANDEI8_UNWD + 6U, // VAMOANDEI8_WD + 0U, // VAMOMAXEI16_UNWD + 6U, // VAMOMAXEI16_WD + 0U, // VAMOMAXEI32_UNWD + 6U, // VAMOMAXEI32_WD + 0U, // VAMOMAXEI64_UNWD + 6U, // VAMOMAXEI64_WD + 0U, // VAMOMAXEI8_UNWD + 6U, // VAMOMAXEI8_WD + 0U, // VAMOMAXUEI16_UNWD + 6U, // VAMOMAXUEI16_WD + 0U, // VAMOMAXUEI32_UNWD + 6U, // VAMOMAXUEI32_WD + 0U, // VAMOMAXUEI64_UNWD + 6U, // VAMOMAXUEI64_WD + 0U, // VAMOMAXUEI8_UNWD + 6U, // VAMOMAXUEI8_WD + 0U, // VAMOMINEI16_UNWD + 6U, // VAMOMINEI16_WD + 0U, // VAMOMINEI32_UNWD + 6U, // VAMOMINEI32_WD + 0U, // VAMOMINEI64_UNWD + 6U, // VAMOMINEI64_WD + 0U, // VAMOMINEI8_UNWD + 6U, // VAMOMINEI8_WD + 0U, // VAMOMINUEI16_UNWD + 6U, // VAMOMINUEI16_WD + 0U, // VAMOMINUEI32_UNWD + 6U, // VAMOMINUEI32_WD + 0U, // VAMOMINUEI64_UNWD + 6U, // VAMOMINUEI64_WD + 0U, // VAMOMINUEI8_UNWD + 6U, // VAMOMINUEI8_WD + 0U, // VAMOOREI16_UNWD + 6U, // VAMOOREI16_WD + 0U, // VAMOOREI32_UNWD + 6U, // VAMOOREI32_WD + 0U, // VAMOOREI64_UNWD + 6U, // VAMOOREI64_WD + 0U, // VAMOOREI8_UNWD + 6U, // VAMOOREI8_WD + 0U, // VAMOSWAPEI16_UNWD + 6U, // VAMOSWAPEI16_WD + 0U, // VAMOSWAPEI32_UNWD + 6U, // VAMOSWAPEI32_WD + 0U, // VAMOSWAPEI64_UNWD + 6U, // VAMOSWAPEI64_WD + 0U, // VAMOSWAPEI8_UNWD + 6U, // VAMOSWAPEI8_WD + 0U, // VAMOXOREI16_UNWD + 6U, // VAMOXOREI16_WD + 0U, // VAMOXOREI32_UNWD + 6U, // VAMOXOREI32_WD + 0U, // VAMOXOREI64_UNWD + 6U, // VAMOXOREI64_WD + 0U, // VAMOXOREI8_UNWD + 6U, // VAMOXOREI8_WD + 0U, // VAND_VI + 0U, // VAND_VV + 0U, // VAND_VX + 0U, // VASUBU_VV + 0U, // VASUBU_VX + 0U, // VASUB_VV + 0U, // VASUB_VX + 0U, // VCOMPRESS_VM + 0U, // VCPOP_M + 0U, // VDIVU_VV + 0U, // VDIVU_VX + 0U, // VDIV_VV + 0U, // VDIV_VX + 0U, // VFADD_VF + 0U, // VFADD_VV + 0U, // VFCLASS_V + 0U, // VFCVT_F_XU_V + 0U, // VFCVT_F_X_V + 0U, // VFCVT_RTZ_XU_F_V + 0U, // VFCVT_RTZ_X_F_V + 0U, // VFCVT_XU_F_V + 0U, // VFCVT_X_F_V + 0U, // VFDIV_VF + 0U, // VFDIV_VV + 0U, // VFIRST_M + 0U, // VFMACC_VF + 0U, // VFMACC_VV + 0U, // VFMADD_VF + 0U, // VFMADD_VV + 0U, // VFMAX_VF + 0U, // VFMAX_VV + 0U, // VFMERGE_VFM + 0U, // VFMIN_VF + 0U, // VFMIN_VV + 0U, // VFMSAC_VF + 0U, // VFMSAC_VV + 0U, // VFMSUB_VF + 0U, // VFMSUB_VV + 0U, // VFMUL_VF + 0U, // VFMUL_VV + 0U, // VFMV_F_S + 0U, // VFMV_S_F + 0U, // VFMV_V_F + 0U, // VFNCVT_F_F_W + 0U, // VFNCVT_F_XU_W + 0U, // VFNCVT_F_X_W + 0U, // VFNCVT_ROD_F_F_W + 0U, // VFNCVT_RTZ_XU_F_W + 0U, // VFNCVT_RTZ_X_F_W + 0U, // VFNCVT_XU_F_W + 0U, // VFNCVT_X_F_W + 0U, // VFNMACC_VF + 0U, // VFNMACC_VV + 0U, // VFNMADD_VF + 0U, // VFNMADD_VV + 0U, // VFNMSAC_VF + 0U, // VFNMSAC_VV + 0U, // VFNMSUB_VF + 0U, // VFNMSUB_VV + 0U, // VFRDIV_VF + 0U, // VFREC7_V + 0U, // VFREDMAX_VS + 0U, // VFREDMIN_VS + 0U, // VFREDOSUM_VS + 0U, // VFREDUSUM_VS + 0U, // VFRSQRT7_V + 0U, // VFRSUB_VF + 0U, // VFSGNJN_VF + 0U, // VFSGNJN_VV + 0U, // VFSGNJX_VF + 0U, // VFSGNJX_VV + 0U, // VFSGNJ_VF + 0U, // VFSGNJ_VV + 0U, // VFSLIDE1DOWN_VF + 0U, // VFSLIDE1UP_VF + 0U, // VFSQRT_V + 0U, // VFSUB_VF + 0U, // VFSUB_VV + 0U, // VFWADD_VF + 0U, // VFWADD_VV + 0U, // VFWADD_WF + 0U, // VFWADD_WV + 0U, // VFWCVT_F_F_V + 0U, // VFWCVT_F_XU_V + 0U, // VFWCVT_F_X_V + 0U, // VFWCVT_RTZ_XU_F_V + 0U, // VFWCVT_RTZ_X_F_V + 0U, // VFWCVT_XU_F_V + 0U, // VFWCVT_X_F_V + 0U, // VFWMACC_VF + 0U, // VFWMACC_VV + 0U, // VFWMSAC_VF + 0U, // VFWMSAC_VV + 0U, // VFWMUL_VF + 0U, // VFWMUL_VV + 0U, // VFWNMACC_VF + 0U, // VFWNMACC_VV + 0U, // VFWNMSAC_VF + 0U, // VFWNMSAC_VV + 0U, // VFWREDOSUM_VS + 0U, // VFWREDUSUM_VS + 0U, // VFWSUB_VF + 0U, // VFWSUB_VV + 0U, // VFWSUB_WF + 0U, // VFWSUB_WV + 0U, // VID_V + 0U, // VIOTA_M + 0U, // VL1RE16_V + 0U, // VL1RE32_V + 0U, // VL1RE64_V + 0U, // VL1RE8_V + 0U, // VL2RE16_V + 0U, // VL2RE32_V + 0U, // VL2RE64_V + 0U, // VL2RE8_V + 0U, // VL4RE16_V + 0U, // VL4RE32_V + 0U, // VL4RE64_V + 0U, // VL4RE8_V + 0U, // VL8RE16_V + 0U, // VL8RE32_V + 0U, // VL8RE64_V + 0U, // VL8RE8_V + 0U, // VLE16FF_V + 0U, // VLE16_V + 0U, // VLE32FF_V + 0U, // VLE32_V + 0U, // VLE64FF_V + 0U, // VLE64_V + 0U, // VLE8FF_V + 0U, // VLE8_V + 0U, // VLM_V + 0U, // VLOXEI16_V + 0U, // VLOXEI32_V + 0U, // VLOXEI64_V + 0U, // VLOXEI8_V + 0U, // VLOXSEG2EI16_V + 0U, // VLOXSEG2EI32_V + 0U, // VLOXSEG2EI64_V + 0U, // VLOXSEG2EI8_V + 0U, // VLOXSEG3EI16_V + 0U, // VLOXSEG3EI32_V + 0U, // VLOXSEG3EI64_V + 0U, // VLOXSEG3EI8_V + 0U, // VLOXSEG4EI16_V + 0U, // VLOXSEG4EI32_V + 0U, // VLOXSEG4EI64_V + 0U, // VLOXSEG4EI8_V + 0U, // VLOXSEG5EI16_V + 0U, // VLOXSEG5EI32_V + 0U, // VLOXSEG5EI64_V + 0U, // VLOXSEG5EI8_V + 0U, // VLOXSEG6EI16_V + 0U, // VLOXSEG6EI32_V + 0U, // VLOXSEG6EI64_V + 0U, // VLOXSEG6EI8_V + 0U, // VLOXSEG7EI16_V + 0U, // VLOXSEG7EI32_V + 0U, // VLOXSEG7EI64_V + 0U, // VLOXSEG7EI8_V + 0U, // VLOXSEG8EI16_V + 0U, // VLOXSEG8EI32_V + 0U, // VLOXSEG8EI64_V + 0U, // VLOXSEG8EI8_V + 0U, // VLSE16_V + 0U, // VLSE32_V + 0U, // VLSE64_V + 0U, // VLSE8_V + 0U, // VLSEG2E16FF_V + 0U, // VLSEG2E16_V + 0U, // VLSEG2E32FF_V + 0U, // VLSEG2E32_V + 0U, // VLSEG2E64FF_V + 0U, // VLSEG2E64_V + 0U, // VLSEG2E8FF_V + 0U, // VLSEG2E8_V + 0U, // VLSEG3E16FF_V + 0U, // VLSEG3E16_V + 0U, // VLSEG3E32FF_V + 0U, // VLSEG3E32_V + 0U, // VLSEG3E64FF_V + 0U, // VLSEG3E64_V + 0U, // VLSEG3E8FF_V + 0U, // VLSEG3E8_V + 0U, // VLSEG4E16FF_V + 0U, // VLSEG4E16_V + 0U, // VLSEG4E32FF_V + 0U, // VLSEG4E32_V + 0U, // VLSEG4E64FF_V + 0U, // VLSEG4E64_V + 0U, // VLSEG4E8FF_V + 0U, // VLSEG4E8_V + 0U, // VLSEG5E16FF_V + 0U, // VLSEG5E16_V + 0U, // VLSEG5E32FF_V + 0U, // VLSEG5E32_V + 0U, // VLSEG5E64FF_V + 0U, // VLSEG5E64_V + 0U, // VLSEG5E8FF_V + 0U, // VLSEG5E8_V + 0U, // VLSEG6E16FF_V + 0U, // VLSEG6E16_V + 0U, // VLSEG6E32FF_V + 0U, // VLSEG6E32_V + 0U, // VLSEG6E64FF_V + 0U, // VLSEG6E64_V + 0U, // VLSEG6E8FF_V + 0U, // VLSEG6E8_V + 0U, // VLSEG7E16FF_V + 0U, // VLSEG7E16_V + 0U, // VLSEG7E32FF_V + 0U, // VLSEG7E32_V + 0U, // VLSEG7E64FF_V + 0U, // VLSEG7E64_V + 0U, // VLSEG7E8FF_V + 0U, // VLSEG7E8_V + 0U, // VLSEG8E16FF_V + 0U, // VLSEG8E16_V + 0U, // VLSEG8E32FF_V + 0U, // VLSEG8E32_V + 0U, // VLSEG8E64FF_V + 0U, // VLSEG8E64_V + 0U, // VLSEG8E8FF_V + 0U, // VLSEG8E8_V + 0U, // VLSSEG2E16_V + 0U, // VLSSEG2E32_V + 0U, // VLSSEG2E64_V + 0U, // VLSSEG2E8_V + 0U, // VLSSEG3E16_V + 0U, // VLSSEG3E32_V + 0U, // VLSSEG3E64_V + 0U, // VLSSEG3E8_V + 0U, // VLSSEG4E16_V + 0U, // VLSSEG4E32_V + 0U, // VLSSEG4E64_V + 0U, // VLSSEG4E8_V + 0U, // VLSSEG5E16_V + 0U, // VLSSEG5E32_V + 0U, // VLSSEG5E64_V + 0U, // VLSSEG5E8_V + 0U, // VLSSEG6E16_V + 0U, // VLSSEG6E32_V + 0U, // VLSSEG6E64_V + 0U, // VLSSEG6E8_V + 0U, // VLSSEG7E16_V + 0U, // VLSSEG7E32_V + 0U, // VLSSEG7E64_V + 0U, // VLSSEG7E8_V + 0U, // VLSSEG8E16_V + 0U, // VLSSEG8E32_V + 0U, // VLSSEG8E64_V + 0U, // VLSSEG8E8_V + 0U, // VLUXEI16_V + 0U, // VLUXEI32_V + 0U, // VLUXEI64_V + 0U, // VLUXEI8_V + 0U, // VLUXSEG2EI16_V + 0U, // VLUXSEG2EI32_V + 0U, // VLUXSEG2EI64_V + 0U, // VLUXSEG2EI8_V + 0U, // VLUXSEG3EI16_V + 0U, // VLUXSEG3EI32_V + 0U, // VLUXSEG3EI64_V + 0U, // VLUXSEG3EI8_V + 0U, // VLUXSEG4EI16_V + 0U, // VLUXSEG4EI32_V + 0U, // VLUXSEG4EI64_V + 0U, // VLUXSEG4EI8_V + 0U, // VLUXSEG5EI16_V + 0U, // VLUXSEG5EI32_V + 0U, // VLUXSEG5EI64_V + 0U, // VLUXSEG5EI8_V + 0U, // VLUXSEG6EI16_V + 0U, // VLUXSEG6EI32_V + 0U, // VLUXSEG6EI64_V + 0U, // VLUXSEG6EI8_V + 0U, // VLUXSEG7EI16_V + 0U, // VLUXSEG7EI32_V + 0U, // VLUXSEG7EI64_V + 0U, // VLUXSEG7EI8_V + 0U, // VLUXSEG8EI16_V + 0U, // VLUXSEG8EI32_V + 0U, // VLUXSEG8EI64_V + 0U, // VLUXSEG8EI8_V + 0U, // VMACC_VV + 0U, // VMACC_VX + 0U, // VMADC_VI + 0U, // VMADC_VIM + 0U, // VMADC_VV + 0U, // VMADC_VVM + 0U, // VMADC_VX + 0U, // VMADC_VXM + 0U, // VMADD_VV + 0U, // VMADD_VX + 0U, // VMANDN_MM + 0U, // VMAND_MM + 0U, // VMAXU_VV + 0U, // VMAXU_VX + 0U, // VMAX_VV + 0U, // VMAX_VX + 0U, // VMERGE_VIM + 0U, // VMERGE_VVM + 0U, // VMERGE_VXM + 0U, // VMFEQ_VF + 0U, // VMFEQ_VV + 0U, // VMFGE_VF + 0U, // VMFGT_VF + 0U, // VMFLE_VF + 0U, // VMFLE_VV + 0U, // VMFLT_VF + 0U, // VMFLT_VV + 0U, // VMFNE_VF + 0U, // VMFNE_VV + 0U, // VMINU_VV + 0U, // VMINU_VX + 0U, // VMIN_VV + 0U, // VMIN_VX + 0U, // VMNAND_MM + 0U, // VMNOR_MM + 0U, // VMORN_MM + 0U, // VMOR_MM + 0U, // VMSBC_VV + 0U, // VMSBC_VVM + 0U, // VMSBC_VX + 0U, // VMSBC_VXM + 0U, // VMSBF_M + 0U, // VMSEQ_VI + 0U, // VMSEQ_VV + 0U, // VMSEQ_VX + 0U, // VMSGTU_VI + 0U, // VMSGTU_VX + 0U, // VMSGT_VI + 0U, // VMSGT_VX + 0U, // VMSIF_M + 0U, // VMSLEU_VI + 0U, // VMSLEU_VV + 0U, // VMSLEU_VX + 0U, // VMSLE_VI + 0U, // VMSLE_VV + 0U, // VMSLE_VX + 0U, // VMSLTU_VV + 0U, // VMSLTU_VX + 0U, // VMSLT_VV + 0U, // VMSLT_VX + 0U, // VMSNE_VI + 0U, // VMSNE_VV + 0U, // VMSNE_VX + 0U, // VMSOF_M + 0U, // VMULHSU_VV + 0U, // VMULHSU_VX + 0U, // VMULHU_VV + 0U, // VMULHU_VX + 0U, // VMULH_VV + 0U, // VMULH_VX + 0U, // VMUL_VV + 0U, // VMUL_VX + 0U, // VMV1R_V + 0U, // VMV2R_V + 0U, // VMV4R_V + 0U, // VMV8R_V + 0U, // VMV_S_X + 0U, // VMV_V_I + 0U, // VMV_V_V + 0U, // VMV_V_X + 0U, // VMV_X_S + 0U, // VMXNOR_MM + 0U, // VMXOR_MM + 0U, // VNCLIPU_WI + 0U, // VNCLIPU_WV + 0U, // VNCLIPU_WX + 0U, // VNCLIP_WI + 0U, // VNCLIP_WV + 0U, // VNCLIP_WX + 0U, // VNMSAC_VV + 0U, // VNMSAC_VX + 0U, // VNMSUB_VV + 0U, // VNMSUB_VX + 0U, // VNSRA_WI + 0U, // VNSRA_WV + 0U, // VNSRA_WX + 0U, // VNSRL_WI + 0U, // VNSRL_WV + 0U, // VNSRL_WX + 0U, // VOR_VI + 0U, // VOR_VV + 0U, // VOR_VX + 0U, // VREDAND_VS + 0U, // VREDMAXU_VS + 0U, // VREDMAX_VS + 0U, // VREDMINU_VS + 0U, // VREDMIN_VS + 0U, // VREDOR_VS + 0U, // VREDSUM_VS + 0U, // VREDXOR_VS + 0U, // VREMU_VV + 0U, // VREMU_VX + 0U, // VREM_VV + 0U, // VREM_VX + 0U, // VRGATHEREI16_VV + 0U, // VRGATHER_VI + 0U, // VRGATHER_VV + 0U, // VRGATHER_VX + 0U, // VRSUB_VI + 0U, // VRSUB_VX + 0U, // VS1R_V + 0U, // VS2R_V + 0U, // VS4R_V + 0U, // VS8R_V + 0U, // VSADDU_VI + 0U, // VSADDU_VV + 0U, // VSADDU_VX + 0U, // VSADD_VI + 0U, // VSADD_VV + 0U, // VSADD_VX + 0U, // VSBC_VVM + 0U, // VSBC_VXM + 0U, // VSE16_V + 0U, // VSE32_V + 0U, // VSE64_V + 0U, // VSE8_V + 0U, // VSETIVLI + 0U, // VSETVL + 0U, // VSETVLI + 0U, // VSEXT_VF2 + 0U, // VSEXT_VF4 + 0U, // VSEXT_VF8 + 0U, // VSLIDE1DOWN_VX + 0U, // VSLIDE1UP_VX + 0U, // VSLIDEDOWN_VI + 0U, // VSLIDEDOWN_VX + 0U, // VSLIDEUP_VI + 0U, // VSLIDEUP_VX + 0U, // VSLL_VI + 0U, // VSLL_VV + 0U, // VSLL_VX + 0U, // VSMUL_VV + 0U, // VSMUL_VX + 0U, // VSM_V + 0U, // VSOXEI16_V + 0U, // VSOXEI32_V + 0U, // VSOXEI64_V + 0U, // VSOXEI8_V + 0U, // VSOXSEG2EI16_V + 0U, // VSOXSEG2EI32_V + 0U, // VSOXSEG2EI64_V + 0U, // VSOXSEG2EI8_V + 0U, // VSOXSEG3EI16_V + 0U, // VSOXSEG3EI32_V + 0U, // VSOXSEG3EI64_V + 0U, // VSOXSEG3EI8_V + 0U, // VSOXSEG4EI16_V + 0U, // VSOXSEG4EI32_V + 0U, // VSOXSEG4EI64_V + 0U, // VSOXSEG4EI8_V + 0U, // VSOXSEG5EI16_V + 0U, // VSOXSEG5EI32_V + 0U, // VSOXSEG5EI64_V + 0U, // VSOXSEG5EI8_V + 0U, // VSOXSEG6EI16_V + 0U, // VSOXSEG6EI32_V + 0U, // VSOXSEG6EI64_V + 0U, // VSOXSEG6EI8_V + 0U, // VSOXSEG7EI16_V + 0U, // VSOXSEG7EI32_V + 0U, // VSOXSEG7EI64_V + 0U, // VSOXSEG7EI8_V + 0U, // VSOXSEG8EI16_V + 0U, // VSOXSEG8EI32_V + 0U, // VSOXSEG8EI64_V + 0U, // VSOXSEG8EI8_V + 0U, // VSRA_VI + 0U, // VSRA_VV + 0U, // VSRA_VX + 0U, // VSRL_VI + 0U, // VSRL_VV + 0U, // VSRL_VX + 0U, // VSSE16_V + 0U, // VSSE32_V + 0U, // VSSE64_V + 0U, // VSSE8_V + 0U, // VSSEG2E16_V + 0U, // VSSEG2E32_V + 0U, // VSSEG2E64_V + 0U, // VSSEG2E8_V + 0U, // VSSEG3E16_V + 0U, // VSSEG3E32_V + 0U, // VSSEG3E64_V + 0U, // VSSEG3E8_V + 0U, // VSSEG4E16_V + 0U, // VSSEG4E32_V + 0U, // VSSEG4E64_V + 0U, // VSSEG4E8_V + 0U, // VSSEG5E16_V + 0U, // VSSEG5E32_V + 0U, // VSSEG5E64_V + 0U, // VSSEG5E8_V + 0U, // VSSEG6E16_V + 0U, // VSSEG6E32_V + 0U, // VSSEG6E64_V + 0U, // VSSEG6E8_V + 0U, // VSSEG7E16_V + 0U, // VSSEG7E32_V + 0U, // VSSEG7E64_V + 0U, // VSSEG7E8_V + 0U, // VSSEG8E16_V + 0U, // VSSEG8E32_V + 0U, // VSSEG8E64_V + 0U, // VSSEG8E8_V + 0U, // VSSRA_VI + 0U, // VSSRA_VV + 0U, // VSSRA_VX + 0U, // VSSRL_VI + 0U, // VSSRL_VV + 0U, // VSSRL_VX + 0U, // VSSSEG2E16_V + 0U, // VSSSEG2E32_V + 0U, // VSSSEG2E64_V + 0U, // VSSSEG2E8_V + 0U, // VSSSEG3E16_V + 0U, // VSSSEG3E32_V + 0U, // VSSSEG3E64_V + 0U, // VSSSEG3E8_V + 0U, // VSSSEG4E16_V + 0U, // VSSSEG4E32_V + 0U, // VSSSEG4E64_V + 0U, // VSSSEG4E8_V + 0U, // VSSSEG5E16_V + 0U, // VSSSEG5E32_V + 0U, // VSSSEG5E64_V + 0U, // VSSSEG5E8_V + 0U, // VSSSEG6E16_V + 0U, // VSSSEG6E32_V + 0U, // VSSSEG6E64_V + 0U, // VSSSEG6E8_V + 0U, // VSSSEG7E16_V + 0U, // VSSSEG7E32_V + 0U, // VSSSEG7E64_V + 0U, // VSSSEG7E8_V + 0U, // VSSSEG8E16_V + 0U, // VSSSEG8E32_V + 0U, // VSSSEG8E64_V + 0U, // VSSSEG8E8_V + 0U, // VSSUBU_VV + 0U, // VSSUBU_VX + 0U, // VSSUB_VV + 0U, // VSSUB_VX + 0U, // VSUB_VV + 0U, // VSUB_VX + 0U, // VSUXEI16_V + 0U, // VSUXEI32_V + 0U, // VSUXEI64_V + 0U, // VSUXEI8_V + 0U, // VSUXSEG2EI16_V + 0U, // VSUXSEG2EI32_V + 0U, // VSUXSEG2EI64_V + 0U, // VSUXSEG2EI8_V + 0U, // VSUXSEG3EI16_V + 0U, // VSUXSEG3EI32_V + 0U, // VSUXSEG3EI64_V + 0U, // VSUXSEG3EI8_V + 0U, // VSUXSEG4EI16_V + 0U, // VSUXSEG4EI32_V + 0U, // VSUXSEG4EI64_V + 0U, // VSUXSEG4EI8_V + 0U, // VSUXSEG5EI16_V + 0U, // VSUXSEG5EI32_V + 0U, // VSUXSEG5EI64_V + 0U, // VSUXSEG5EI8_V + 0U, // VSUXSEG6EI16_V + 0U, // VSUXSEG6EI32_V + 0U, // VSUXSEG6EI64_V + 0U, // VSUXSEG6EI8_V + 0U, // VSUXSEG7EI16_V + 0U, // VSUXSEG7EI32_V + 0U, // VSUXSEG7EI64_V + 0U, // VSUXSEG7EI8_V + 0U, // VSUXSEG8EI16_V + 0U, // VSUXSEG8EI32_V + 0U, // VSUXSEG8EI64_V + 0U, // VSUXSEG8EI8_V + 0U, // VWADDU_VV + 0U, // VWADDU_VX + 0U, // VWADDU_WV + 0U, // VWADDU_WX + 0U, // VWADD_VV + 0U, // VWADD_VX + 0U, // VWADD_WV + 0U, // VWADD_WX + 0U, // VWMACCSU_VV + 0U, // VWMACCSU_VX + 0U, // VWMACCUS_VX + 0U, // VWMACCU_VV + 0U, // VWMACCU_VX + 0U, // VWMACC_VV + 0U, // VWMACC_VX + 0U, // VWMULSU_VV + 0U, // VWMULSU_VX + 0U, // VWMULU_VV + 0U, // VWMULU_VX + 0U, // VWMUL_VV + 0U, // VWMUL_VX + 0U, // VWREDSUMU_VS + 0U, // VWREDSUM_VS + 0U, // VWSUBU_VV + 0U, // VWSUBU_VX + 0U, // VWSUBU_WV + 0U, // VWSUBU_WX + 0U, // VWSUB_VV + 0U, // VWSUB_VX + 0U, // VWSUB_WV + 0U, // VWSUB_WX + 0U, // VXOR_VI + 0U, // VXOR_VV + 0U, // VXOR_VX + 0U, // VZEXT_VF2 + 0U, // VZEXT_VF4 + 0U, // VZEXT_VF8 + 0U, // WFI + 0U, // XNOR + 0U, // XOR + 0U, // XORI + 0U, // XPERMB + 0U, // XPERMH + 0U, // XPERMN + 0U, // XPERMW + 0U, // ZEXTH_RV32 + 0U, // ZEXTH_RV64 + }; + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + return createMnemonic(AsmStrs + (Bits & 16383) - 1, Bits); +} +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) { + MCMnemonic MnemonicInfo = RISCV_getMnemonic(MI); + +#ifndef CAPSTONE_DIET + + SStream_concat0(O, MnemonicInfo.first); +#endif + + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 14) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // PseudoAddTPRel, PseudoCALL, PseudoCALLReg, PseudoLA, PseudoLA_TLS_GD, ... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 2: + // PseudoFLD, PseudoFLH, PseudoFLW, PseudoFSD, PseudoFSH, PseudoFSW, Pseu... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 3: + // C_J, C_JAL + printBranchOperand /* printBranchOperand (+ ) */ (MI, 0, O); + return; + break; + case 4: + // FENCE + printFenceArg /* printFenceArg (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printFenceArg /* printFenceArg (+ ) */ (MI, 1, O); + return; + break; + } + + // Fragment 1 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 17) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // PseudoAddTPRel, PseudoCALLReg, PseudoFLD, PseudoFLH, PseudoFLW, Pseudo... + SStream_concat0(O, ", "); + break; + case 1: + // PseudoCALL, PseudoTAIL, C_JALR, C_JR, C_NOP_HINT, C_SLLI64_HINT, C_SRA... + return; + break; + case 2: + // VAMOADDEI16_UNWD, VAMOADDEI32_UNWD, VAMOADDEI64_UNWD, VAMOADDEI8_UNWD,... + SStream_concat0(O, "), "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + printVMaskReg /* printVMaskReg (+ ) */ (MI, 3, O); + return; + break; + case 3: + // VAMOADDEI16_WD, VAMOADDEI32_WD, VAMOADDEI64_WD, VAMOADDEI8_WD, VAMOAND... + SStream_concat0(O, ", ("); + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 4: + // VID_V + printVMaskReg /* printVMaskReg (+ ) */ (MI, 1, O); + return; + break; + } + + // Fragment 2 encoded into 3 bits for 8 unique commands. + switch ((Bits >> 20) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // PseudoAddTPRel, PseudoCALLReg, PseudoLA, PseudoLA_TLS_GD, PseudoLA_TLS... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 1: + // PseudoFLD, PseudoFLH, PseudoFLW, PseudoFSD, PseudoFSH, PseudoFSW, Pseu... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 2: + // PseudoJump, InsnJ, InsnU + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 3: + // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI + printCSRSystemRegister /* printCSRSystemRegister (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 4: + // C_BEQZ, C_BNEZ, JAL + printBranchOperand /* printBranchOperand (+ ) */ (MI, 1, O); + return; + break; + case 5: + // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL + printAtomicMemOp /* printAtomicMemOp (+ ) */ (MI, 1, O); + return; + break; + case 6: + // VAMOADDEI16_WD, VAMOADDEI32_WD, VAMOADDEI64_WD, VAMOADDEI8_WD, VAMOAND... + SStream_concat0(O, "), "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 7: + // VL1RE16_V, VL1RE32_V, VL1RE64_V, VL1RE8_V, VL2RE16_V, VL2RE32_V, VL2RE... + SStream_concat0(O, ")"); + break; + } + + // Fragment 3 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 23) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // PseudoAddTPRel, PseudoFLD, PseudoFLH, PseudoFLW, PseudoFSD, PseudoFSH,... + SStream_concat0(O, ", "); + break; + case 1: + // PseudoCALLReg, PseudoJump, PseudoLA, PseudoLA_TLS_GD, PseudoLA_TLS_IE,... + return; + break; + case 2: + // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ... + SStream_concat0(O, "("); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ")"); + return; + break; + case 3: + // VCPOP_M, VFCLASS_V, VFCVT_F_XU_V, VFCVT_F_X_V, VFCVT_RTZ_XU_F_V, VFCVT... + printVMaskReg /* printVMaskReg (+ ) */ (MI, 2, O); + return; + break; + case 4: + // VLOXEI16_V, VLOXEI32_V, VLOXEI64_V, VLOXEI8_V, VLOXSEG2EI16_V, VLOXSEG... + printVMaskReg /* printVMaskReg (+ ) */ (MI, 3, O); + return; + break; + } + + // Fragment 4 encoded into 3 bits for 8 unique commands. + switch ((Bits >> 26) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // PseudoAddTPRel, PseudoVMSGEU_VI, PseudoVMSGEU_VX, PseudoVMSGEU_VX_M, P... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 1: + // PseudoFLD, PseudoFLH, PseudoFLW, PseudoFSD, PseudoFSH, PseudoFSW, Pseu... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 2: + // PseudoVMSGEU_VX_M_T, PseudoVMSGE_VX_M_T, FSL, FSLW, FSR, FSRW, InsnR, ... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 3: + // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... + printAtomicMemOp /* printAtomicMemOp (+ ) */ (MI, 1, O); + return; + break; + case 4: + // BEQ, BGE, BGEU, BLT, BLTU, BNE, InsnJ + printBranchOperand /* printBranchOperand (+ ) */ (MI, 2, O); + return; + break; + case 5: + // CMIX, CMOV + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 6: + // FCVT_D_L, FCVT_D_LU, FCVT_H_D, FCVT_H_L, FCVT_H_LU, FCVT_H_S, FCVT_H_W... + printFRMArg /* printFRMArg (+ ) */ (MI, 2, O); + return; + break; + case 7: + // VSETIVLI, VSETVLI + printVTypeI /* printVTypeI (+ ) */ (MI, 2, O); + return; + break; + } + + // Fragment 5 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 29) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // PseudoAddTPRel, FADD_D, FADD_H, FADD_S, FDIV_D, FDIV_H, FDIV_S, FMADD_... + SStream_concat0(O, ", "); + break; + case 1: + // PseudoFLD, PseudoFLH, PseudoFLW, PseudoFSD, PseudoFSH, PseudoFSW, Pseu... + return; + break; + case 2: + // PseudoVMSGEU_VI, PseudoVMSGEU_VX_M, PseudoVMSGE_VI, PseudoVMSGE_VX_M, ... + printVMaskReg /* printVMaskReg (+ ) */ (MI, 3, O); + return; + break; + case 3: + // PseudoVMSGEU_VX_M_T, PseudoVMSGE_VX_M_T, VAMOADDEI16_WD, VAMOADDEI32_W... + printVMaskReg /* printVMaskReg (+ ) */ (MI, 4, O); + break; + case 4: + // VADC_VIM, VADC_VVM, VADC_VXM, VFMERGE_VFM, VMADC_VIM, VMADC_VVM, VMADC... + SStream_concat0(O, ", v0"); + return; + break; + } + + // Fragment 6 encoded into 3 bits for 7 unique commands. + switch ((Bits >> 32) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // PseudoAddTPRel, FMADD_D, FMADD_H, FMADD_S, FMSUB_D, FMSUB_H, FMSUB_S, ... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 1: + // PseudoVMSGEU_VX_M_T, PseudoVMSGE_VX_M_T + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 2: + // FADD_D, FADD_H, FADD_S, FDIV_D, FDIV_H, FDIV_S, FMUL_D, FMUL_H, FMUL_S... + printFRMArg /* printFRMArg (+ ) */ (MI, 3, O); + return; + break; + case 3: + // FSL, FSLW, FSR, FSRW + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 4: + // InsnI_Mem, InsnS + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, "("); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ")"); + return; + break; + case 5: + // InsnR, InsnR4 + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + break; + case 6: + // VAMOADDEI16_WD, VAMOADDEI32_WD, VAMOADDEI64_WD, VAMOADDEI8_WD, VAMOAND... + return; + break; + } + + // Fragment 7 encoded into 1 bits for 2 unique commands. + if ((Bits >> 35) & 1) { + // FMADD_D, FMADD_H, FMADD_S, FMSUB_D, FMSUB_H, FMSUB_S, FNMADD_D, FNMADD... + SStream_concat0(O, ", "); + } else { + // PseudoAddTPRel, FSRI, FSRIW, InsnR + return; + } + + // Fragment 8 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 36) & 3) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // FMADD_D, FMADD_H, FMADD_S, FMSUB_D, FMSUB_H, FMSUB_S, FNMADD_D, FNMADD... + printFRMArg /* printFRMArg (+ ) */ (MI, 4, O); + return; + break; + case 1: + // InsnB + printBranchOperand /* printBranchOperand (+ ) */ (MI, 4, O); + return; + break; + case 2: + // InsnI + printOperand /* printOperand (+ ) */ (MI, 4, O); + return; + break; + case 3: + // InsnR4 + printOperand /* printOperand (+ ) */ (MI, 6, O); + return; + break; + } +} + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo, unsigned AltIdx) { + assert(RegNo && RegNo < 441 && "Invalid register number!"); + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrsABIRegAltName[] = {/* 0 */ "fs10\0" + /* 5 */ "ft10\0" + /* 10 */ "v10\0" + /* 14 */ "v20\0" + /* 18 */ "v30\0" + /* 22 */ "fa0\0" + /* 26 */ "fs0\0" + /* 30 */ "ft0\0" + /* 34 */ "v0\0" + /* 37 */ "fs11\0" + /* 42 */ "ft11\0" + /* 47 */ "v11\0" + /* 51 */ "v21\0" + /* 55 */ "v31\0" + /* 59 */ "fa1\0" + /* 63 */ "fs1\0" + /* 67 */ "ft1\0" + /* 71 */ "v1\0" + /* 74 */ "v12\0" + /* 78 */ "v22\0" + /* 82 */ "fa2\0" + /* 86 */ "fs2\0" + /* 90 */ "ft2\0" + /* 94 */ "v2\0" + /* 97 */ "v13\0" + /* 101 */ "v23\0" + /* 105 */ "fa3\0" + /* 109 */ "fs3\0" + /* 113 */ "ft3\0" + /* 117 */ "v3\0" + /* 120 */ "v14\0" + /* 124 */ "v24\0" + /* 128 */ "fa4\0" + /* 132 */ "fs4\0" + /* 136 */ "ft4\0" + /* 140 */ "v4\0" + /* 143 */ "v15\0" + /* 147 */ "v25\0" + /* 151 */ "fa5\0" + /* 155 */ "fs5\0" + /* 159 */ "ft5\0" + /* 163 */ "v5\0" + /* 166 */ "v16\0" + /* 170 */ "v26\0" + /* 174 */ "fa6\0" + /* 178 */ "fs6\0" + /* 182 */ "ft6\0" + /* 186 */ "v6\0" + /* 189 */ "v17\0" + /* 193 */ "v27\0" + /* 197 */ "fa7\0" + /* 201 */ "fs7\0" + /* 205 */ "ft7\0" + /* 209 */ "v7\0" + /* 212 */ "v18\0" + /* 216 */ "v28\0" + /* 220 */ "fs8\0" + /* 224 */ "ft8\0" + /* 228 */ "v8\0" + /* 231 */ "v19\0" + /* 235 */ "v29\0" + /* 239 */ "fs9\0" + /* 243 */ "ft9\0" + /* 247 */ "v9\0" + /* 250 */ "ra\0" + /* 253 */ "vtype\0" + /* 259 */ "vl\0" + /* 262 */ "vxrm\0" + /* 267 */ "zero\0" + /* 272 */ "gp\0" + /* 275 */ "sp\0" + /* 278 */ "tp\0" + /* 281 */ "vxsat\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint16_t RegAsmOffsetABIRegAltName[] = { + 4, 4, 4, 259, 253, 262, 281, 34, 71, 94, 117, 140, 163, 186, 209, + 228, 247, 10, 47, 74, 97, 120, 143, 166, 189, 212, 231, 14, 51, 78, + 101, 124, 147, 170, 193, 216, 235, 18, 55, 267, 250, 275, 272, 278, 31, + 68, 91, 27, 64, 23, 60, 83, 106, 129, 152, 175, 198, 87, 110, 133, + 156, 179, 202, 221, 240, 1, 38, 114, 137, 160, 183, 30, 67, 90, 113, + 136, 159, 182, 205, 26, 63, 22, 59, 82, 105, 128, 151, 174, 197, 86, + 109, 132, 155, 178, 201, 220, 239, 0, 37, 224, 243, 5, 42, 30, 67, + 90, 113, 136, 159, 182, 205, 26, 63, 22, 59, 82, 105, 128, 151, 174, + 197, 86, 109, 132, 155, 178, 201, 220, 239, 0, 37, 224, 243, 5, 42, + 30, 67, 90, 113, 136, 159, 182, 205, 26, 63, 22, 59, 82, 105, 128, + 151, 174, 197, 86, 109, 132, 155, 178, 201, 220, 239, 0, 37, 224, 243, + 5, 42, 34, 34, 34, 94, 140, 140, 186, 228, 228, 228, 10, 74, 74, + 120, 166, 166, 166, 212, 14, 14, 78, 124, 124, 124, 170, 216, 216, 18, + 71, 94, 117, 140, 163, 186, 209, 228, 247, 10, 47, 74, 97, 120, 143, + 166, 189, 212, 231, 14, 51, 78, 101, 124, 147, 170, 193, 216, 235, 18, + 34, 94, 140, 186, 228, 10, 74, 120, 166, 212, 14, 78, 124, 170, 216, + 34, 140, 228, 74, 166, 14, 124, 34, 71, 94, 117, 140, 163, 186, 209, + 228, 247, 10, 47, 74, 97, 120, 143, 166, 189, 212, 231, 14, 51, 78, + 101, 124, 147, 170, 193, 216, 235, 34, 94, 140, 186, 228, 10, 74, 120, + 166, 212, 14, 78, 124, 170, 34, 71, 94, 117, 140, 163, 186, 209, 228, + 247, 10, 47, 74, 97, 120, 143, 166, 189, 212, 231, 14, 51, 78, 101, + 124, 147, 170, 193, 216, 34, 94, 140, 186, 228, 10, 74, 120, 166, 212, + 14, 78, 124, 34, 71, 94, 117, 140, 163, 186, 209, 228, 247, 10, 47, + 74, 97, 120, 143, 166, 189, 212, 231, 14, 51, 78, 101, 124, 147, 170, + 193, 34, 71, 94, 117, 140, 163, 186, 209, 228, 247, 10, 47, 74, 97, + 120, 143, 166, 189, 212, 231, 14, 51, 78, 101, 124, 147, 170, 34, 71, + 94, 117, 140, 163, 186, 209, 228, 247, 10, 47, 74, 97, 120, 143, 166, + 189, 212, 231, 14, 51, 78, 101, 124, 147, 34, 71, 94, 117, 140, 163, + 186, 209, 228, 247, 10, 47, 74, 97, 120, 143, 166, 189, 212, 231, 14, + 51, 78, 101, 124, 34, + }; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrsNoRegAltName[] = { + /* 0 */ "V3_V4_V5_V6_V7_V8_V9_V10\0" + /* 25 */ "f10\0" + /* 29 */ "v10\0" + /* 33 */ "x10\0" + /* 37 */ "V13_V14_V15_V16_V17_V18_V19_V20\0" + /* 69 */ "f20\0" + /* 73 */ "v20\0" + /* 77 */ "x20\0" + /* 81 */ "V23_V24_V25_V26_V27_V28_V29_V30\0" + /* 113 */ "f30\0" + /* 117 */ "v30\0" + /* 121 */ "x30\0" + /* 125 */ "f0\0" + /* 128 */ "v0\0" + /* 131 */ "x0\0" + /* 134 */ "V4_V5_V6_V7_V8_V9_V10_V11\0" + /* 160 */ "f11\0" + /* 164 */ "v11\0" + /* 168 */ "x11\0" + /* 172 */ "V14_V15_V16_V17_V18_V19_V20_V21\0" + /* 204 */ "f21\0" + /* 208 */ "v21\0" + /* 212 */ "x21\0" + /* 216 */ "V24_V25_V26_V27_V28_V29_V30_V31\0" + /* 248 */ "f31\0" + /* 252 */ "v31\0" + /* 256 */ "x31\0" + /* 260 */ "V0_V1\0" + /* 266 */ "f1\0" + /* 269 */ "v1\0" + /* 272 */ "x1\0" + /* 275 */ "V5_V6_V7_V8_V9_V10_V11_V12\0" + /* 302 */ "f12\0" + /* 306 */ "v12\0" + /* 310 */ "x12\0" + /* 314 */ "V15_V16_V17_V18_V19_V20_V21_V22\0" + /* 346 */ "f22\0" + /* 350 */ "v22\0" + /* 354 */ "x22\0" + /* 358 */ "V4M2_V6M2_V8M2_V10M2\0" + /* 379 */ "V14M2_V16M2_V18M2_V20M2\0" + /* 403 */ "V24M2_V26M2_V28M2_V30M2\0" + /* 427 */ "V6M2_V8M2_V10M2_V12M2\0" + /* 449 */ "V16M2_V18M2_V20M2_V22M2\0" + /* 473 */ "V0M2_V2M2\0" + /* 483 */ "V8M2_V10M2_V12M2_V14M2\0" + /* 506 */ "V18M2_V20M2_V22M2_V24M2\0" + /* 530 */ "V0M2_V2M2_V4M2\0" + /* 545 */ "V10M2_V12M2_V14M2_V16M2\0" + /* 569 */ "V20M2_V22M2_V24M2_V26M2\0" + /* 593 */ "V0M2_V2M2_V4M2_V6M2\0" + /* 613 */ "V12M2_V14M2_V16M2_V18M2\0" + /* 637 */ "V22M2_V24M2_V26M2_V28M2\0" + /* 661 */ "V2M2_V4M2_V6M2_V8M2\0" + /* 681 */ "V0_V1_V2\0" + /* 690 */ "f2\0" + /* 693 */ "v2\0" + /* 696 */ "x2\0" + /* 699 */ "V6_V7_V8_V9_V10_V11_V12_V13\0" + /* 727 */ "f13\0" + /* 731 */ "v13\0" + /* 735 */ "x13\0" + /* 739 */ "V16_V17_V18_V19_V20_V21_V22_V23\0" + /* 771 */ "f23\0" + /* 775 */ "v23\0" + /* 779 */ "x23\0" + /* 783 */ "V0_V1_V2_V3\0" + /* 795 */ "f3\0" + /* 798 */ "v3\0" + /* 801 */ "x3\0" + /* 804 */ "V7_V8_V9_V10_V11_V12_V13_V14\0" + /* 833 */ "f14\0" + /* 837 */ "v14\0" + /* 841 */ "x14\0" + /* 845 */ "V17_V18_V19_V20_V21_V22_V23_V24\0" + /* 877 */ "f24\0" + /* 881 */ "v24\0" + /* 885 */ "x24\0" + /* 889 */ "V16M4_V20M4\0" + /* 901 */ "V8M4_V12M4\0" + /* 912 */ "V20M4_V24M4\0" + /* 924 */ "V0M4_V4M4\0" + /* 934 */ "V12M4_V16M4\0" + /* 946 */ "V24M4_V28M4\0" + /* 958 */ "V4M4_V8M4\0" + /* 968 */ "V0_V1_V2_V3_V4\0" + /* 983 */ "f4\0" + /* 986 */ "v4\0" + /* 989 */ "x4\0" + /* 992 */ "V8_V9_V10_V11_V12_V13_V14_V15\0" + /* 1022 */ "f15\0" + /* 1026 */ "v15\0" + /* 1030 */ "x15\0" + /* 1034 */ "V18_V19_V20_V21_V22_V23_V24_V25\0" + /* 1066 */ "f25\0" + /* 1070 */ "v25\0" + /* 1074 */ "x25\0" + /* 1078 */ "V0_V1_V2_V3_V4_V5\0" + /* 1096 */ "f5\0" + /* 1099 */ "v5\0" + /* 1102 */ "x5\0" + /* 1105 */ "V9_V10_V11_V12_V13_V14_V15_V16\0" + /* 1136 */ "f16\0" + /* 1140 */ "v16\0" + /* 1144 */ "x16\0" + /* 1148 */ "V19_V20_V21_V22_V23_V24_V25_V26\0" + /* 1180 */ "f26\0" + /* 1184 */ "v26\0" + /* 1188 */ "x26\0" + /* 1192 */ "V0_V1_V2_V3_V4_V5_V6\0" + /* 1213 */ "f6\0" + /* 1216 */ "v6\0" + /* 1219 */ "x6\0" + /* 1222 */ "V10_V11_V12_V13_V14_V15_V16_V17\0" + /* 1254 */ "f17\0" + /* 1258 */ "v17\0" + /* 1262 */ "x17\0" + /* 1266 */ "V20_V21_V22_V23_V24_V25_V26_V27\0" + /* 1298 */ "f27\0" + /* 1302 */ "v27\0" + /* 1306 */ "x27\0" + /* 1310 */ "V0_V1_V2_V3_V4_V5_V6_V7\0" + /* 1334 */ "f7\0" + /* 1337 */ "v7\0" + /* 1340 */ "x7\0" + /* 1343 */ "V11_V12_V13_V14_V15_V16_V17_V18\0" + /* 1375 */ "f18\0" + /* 1379 */ "v18\0" + /* 1383 */ "x18\0" + /* 1387 */ "V21_V22_V23_V24_V25_V26_V27_V28\0" + /* 1419 */ "f28\0" + /* 1423 */ "v28\0" + /* 1427 */ "x28\0" + /* 1431 */ "V1_V2_V3_V4_V5_V6_V7_V8\0" + /* 1455 */ "f8\0" + /* 1458 */ "v8\0" + /* 1461 */ "x8\0" + /* 1464 */ "V12_V13_V14_V15_V16_V17_V18_V19\0" + /* 1496 */ "f19\0" + /* 1500 */ "v19\0" + /* 1504 */ "x19\0" + /* 1508 */ "V22_V23_V24_V25_V26_V27_V28_V29\0" + /* 1540 */ "f29\0" + /* 1544 */ "v29\0" + /* 1548 */ "x29\0" + /* 1552 */ "V2_V3_V4_V5_V6_V7_V8_V9\0" + /* 1576 */ "f9\0" + /* 1579 */ "v9\0" + /* 1582 */ "x9\0" + /* 1585 */ "vtype\0" + /* 1591 */ "vl\0" + /* 1594 */ "frm\0" + /* 1598 */ "vxrm\0" + /* 1603 */ "fcsr\0" + /* 1608 */ "fflags\0" + /* 1615 */ "vxsat\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint16_t RegAsmOffsetNoRegAltName[] = { + 1603, 1608, 1594, 1591, 1585, 1598, 1615, 128, 269, 693, 798, 986, + 1099, 1216, 1337, 1458, 1579, 29, 164, 306, 731, 837, 1026, 1140, + 1258, 1379, 1500, 73, 208, 350, 775, 881, 1070, 1184, 1302, 1423, + 1544, 117, 252, 131, 272, 696, 801, 989, 1102, 1219, 1340, 1461, + 1582, 33, 168, 310, 735, 841, 1030, 1144, 1262, 1383, 1504, 77, + 212, 354, 779, 885, 1074, 1188, 1306, 1427, 1548, 121, 256, 125, + 266, 690, 795, 983, 1096, 1213, 1334, 1455, 1576, 25, 160, 302, + 727, 833, 1022, 1136, 1254, 1375, 1496, 69, 204, 346, 771, 877, + 1066, 1180, 1298, 1419, 1540, 113, 248, 125, 266, 690, 795, 983, + 1096, 1213, 1334, 1455, 1576, 25, 160, 302, 727, 833, 1022, 1136, + 1254, 1375, 1496, 69, 204, 346, 771, 877, 1066, 1180, 1298, 1419, + 1540, 113, 248, 125, 266, 690, 795, 983, 1096, 1213, 1334, 1455, + 1576, 25, 160, 302, 727, 833, 1022, 1136, 1254, 1375, 1496, 69, + 204, 346, 771, 877, 1066, 1180, 1298, 1419, 1540, 113, 248, 128, + 128, 128, 693, 986, 986, 1216, 1458, 1458, 1458, 29, 306, 306, + 837, 1140, 1140, 1140, 1379, 73, 73, 350, 881, 881, 881, 1184, + 1423, 1423, 117, 684, 789, 977, 1090, 1207, 1328, 1449, 1570, 18, + 152, 294, 719, 825, 1014, 1128, 1246, 1367, 1488, 61, 196, 338, + 763, 869, 1058, 1172, 1290, 1411, 1532, 105, 240, 260, 535, 603, + 671, 368, 437, 494, 557, 625, 391, 461, 518, 581, 649, 415, + 473, 958, 901, 934, 889, 912, 946, 924, 786, 974, 1087, 1204, + 1325, 1446, 1567, 15, 149, 290, 715, 821, 1010, 1124, 1242, 1363, + 1484, 57, 192, 334, 759, 865, 1054, 1168, 1286, 1407, 1528, 101, + 236, 681, 598, 666, 363, 432, 488, 551, 619, 385, 455, 512, + 575, 643, 409, 530, 971, 1084, 1201, 1322, 1443, 1564, 12, 146, + 287, 711, 817, 1006, 1120, 1238, 1359, 1480, 53, 188, 330, 755, + 861, 1050, 1164, 1282, 1403, 1524, 97, 232, 783, 661, 358, 427, + 483, 545, 613, 379, 449, 506, 569, 637, 403, 593, 1081, 1198, + 1319, 1440, 1561, 9, 143, 284, 708, 813, 1002, 1116, 1234, 1355, + 1476, 49, 184, 326, 751, 857, 1046, 1160, 1278, 1399, 1520, 93, + 228, 968, 1195, 1316, 1437, 1558, 6, 140, 281, 705, 810, 998, + 1112, 1230, 1351, 1472, 45, 180, 322, 747, 853, 1042, 1156, 1274, + 1395, 1516, 89, 224, 1078, 1313, 1434, 1555, 3, 137, 278, 702, + 807, 995, 1108, 1226, 1347, 1468, 41, 176, 318, 743, 849, 1038, + 1152, 1270, 1391, 1512, 85, 220, 1192, 1431, 1552, 0, 134, 275, + 699, 804, 992, 1105, 1222, 1343, 1464, 37, 172, 314, 739, 845, + 1034, 1148, 1266, 1387, 1508, 81, 216, 1310, + }; + + switch (AltIdx) { + default: + llvm_unreachable("Invalid register alt name index!"); + case RISCV_ABIRegAltName: + assert(*(AsmStrsABIRegAltName + RegAsmOffsetABIRegAltName[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrsABIRegAltName + RegAsmOffsetABIRegAltName[RegNo - 1]; + case RISCV_NoRegAltName: + assert(*(AsmStrsNoRegAltName + RegAsmOffsetNoRegAltName[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrsNoRegAltName + RegAsmOffsetNoRegAltName[RegNo - 1]; + } +} +#endif +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +static char *printAliasInstr(MCInst *MI, SStream *OS) { + static const PatternsForOpcode OpToPatterns[] = { + {RISCV_ADDI, 0, 3}, {RISCV_ADDIW, 3, 1}, + {RISCV_ADDUW, 4, 1}, {RISCV_BEQ, 5, 1}, + {RISCV_BGE, 6, 2}, {RISCV_BLT, 8, 2}, + {RISCV_BNE, 10, 1}, {RISCV_CSRRC, 11, 1}, + {RISCV_CSRRCI, 12, 1}, {RISCV_CSRRS, 13, 11}, + {RISCV_CSRRSI, 24, 1}, {RISCV_CSRRW, 25, 7}, + {RISCV_CSRRWI, 32, 5}, {RISCV_FADD_D, 37, 1}, + {RISCV_FADD_H, 38, 1}, {RISCV_FADD_S, 39, 1}, + {RISCV_FCVT_D_L, 40, 1}, {RISCV_FCVT_D_LU, 41, 1}, + {RISCV_FCVT_H_D, 42, 1}, {RISCV_FCVT_H_L, 43, 1}, + {RISCV_FCVT_H_LU, 44, 1}, {RISCV_FCVT_H_S, 45, 1}, + {RISCV_FCVT_H_W, 46, 1}, {RISCV_FCVT_H_WU, 47, 1}, + {RISCV_FCVT_LU_D, 48, 1}, {RISCV_FCVT_LU_H, 49, 1}, + {RISCV_FCVT_LU_S, 50, 1}, {RISCV_FCVT_L_D, 51, 1}, + {RISCV_FCVT_L_H, 52, 1}, {RISCV_FCVT_L_S, 53, 1}, + {RISCV_FCVT_S_D, 54, 1}, {RISCV_FCVT_S_L, 55, 1}, + {RISCV_FCVT_S_LU, 56, 1}, {RISCV_FCVT_S_W, 57, 1}, + {RISCV_FCVT_S_WU, 58, 1}, {RISCV_FCVT_WU_D, 59, 1}, + {RISCV_FCVT_WU_H, 60, 1}, {RISCV_FCVT_WU_S, 61, 1}, + {RISCV_FCVT_W_D, 62, 1}, {RISCV_FCVT_W_H, 63, 1}, + {RISCV_FCVT_W_S, 64, 1}, {RISCV_FDIV_D, 65, 1}, + {RISCV_FDIV_H, 66, 1}, {RISCV_FDIV_S, 67, 1}, + {RISCV_FENCE, 68, 1}, {RISCV_FMADD_D, 69, 1}, + {RISCV_FMADD_H, 70, 1}, {RISCV_FMADD_S, 71, 1}, + {RISCV_FMSUB_D, 72, 1}, {RISCV_FMSUB_H, 73, 1}, + {RISCV_FMSUB_S, 74, 1}, {RISCV_FMUL_D, 75, 1}, + {RISCV_FMUL_H, 76, 1}, {RISCV_FMUL_S, 77, 1}, + {RISCV_FNMADD_D, 78, 1}, {RISCV_FNMADD_H, 79, 1}, + {RISCV_FNMADD_S, 80, 1}, {RISCV_FNMSUB_D, 81, 1}, + {RISCV_FNMSUB_H, 82, 1}, {RISCV_FNMSUB_S, 83, 1}, + {RISCV_FSGNJN_D, 84, 1}, {RISCV_FSGNJN_H, 85, 1}, + {RISCV_FSGNJN_S, 86, 1}, {RISCV_FSGNJX_D, 87, 1}, + {RISCV_FSGNJX_H, 88, 1}, {RISCV_FSGNJX_S, 89, 1}, + {RISCV_FSGNJ_D, 90, 1}, {RISCV_FSGNJ_H, 91, 1}, + {RISCV_FSGNJ_S, 92, 1}, {RISCV_FSQRT_D, 93, 1}, + {RISCV_FSQRT_H, 94, 1}, {RISCV_FSQRT_S, 95, 1}, + {RISCV_FSUB_D, 96, 1}, {RISCV_FSUB_H, 97, 1}, + {RISCV_FSUB_S, 98, 1}, {RISCV_GORCI, 99, 25}, + {RISCV_GREVI, 124, 24}, {RISCV_JAL, 148, 2}, + {RISCV_JALR, 150, 6}, {RISCV_SFENCE_VMA, 156, 2}, + {RISCV_SHFLI, 158, 19}, {RISCV_SLT, 177, 2}, + {RISCV_SLTIU, 179, 1}, {RISCV_SLTU, 180, 1}, + {RISCV_SUB, 181, 1}, {RISCV_SUBW, 182, 1}, + {RISCV_UNSHFLI, 183, 19}, {RISCV_VFSGNJN_VV, 202, 1}, + {RISCV_VFSGNJX_VV, 203, 1}, {RISCV_VL1RE8_V, 204, 1}, + {RISCV_VL2RE8_V, 205, 1}, {RISCV_VL4RE8_V, 206, 1}, + {RISCV_VL8RE8_V, 207, 1}, {RISCV_VMAND_MM, 208, 1}, + {RISCV_VMNAND_MM, 209, 1}, {RISCV_VMXNOR_MM, 210, 1}, + {RISCV_VMXOR_MM, 211, 1}, {RISCV_VNSRL_WX, 212, 1}, + {RISCV_VRSUB_VX, 213, 1}, {RISCV_VWADDU_VX, 214, 1}, + {RISCV_VWADD_VX, 215, 1}, {RISCV_VXOR_VI, 216, 1}, + {RISCV_XORI, 217, 1}, + }; + + static const AliasPattern Patterns[] = { + // RISCV::ADDI - 0 + {0, 0, 3, 3}, + {4, 3, 3, 3}, + {14, 6, 3, 3}, + // RISCV::ADDIW - 3 + {24, 9, 3, 4}, + // RISCV::ADDUW - 4 + {38, 13, 3, 5}, + // RISCV::BEQ - 5 + {52, 18, 3, 3}, + // RISCV::BGE - 6 + {66, 21, 3, 3}, + {80, 24, 3, 3}, + // RISCV::BLT - 8 + {94, 27, 3, 3}, + {108, 30, 3, 3}, + // RISCV::BNE - 10 + {122, 33, 3, 3}, + // RISCV::CSRRC - 11 + {136, 36, 3, 3}, + // RISCV::CSRRCI - 12 + {150, 39, 3, 2}, + // RISCV::CSRRS - 13 + {165, 41, 3, 4}, + {174, 45, 3, 4}, + {182, 49, 3, 4}, + {193, 53, 3, 3}, + {206, 56, 3, 3}, + {217, 59, 3, 3}, + {227, 62, 3, 4}, + {241, 66, 3, 4}, + {253, 70, 3, 4}, + {264, 74, 3, 3}, + {278, 77, 3, 3}, + // RISCV::CSRRSI - 24 + {292, 80, 3, 2}, + // RISCV::CSRRW - 25 + {307, 82, 3, 4}, + {316, 86, 3, 4}, + {324, 90, 3, 4}, + {335, 94, 3, 3}, + {349, 97, 3, 4}, + {362, 101, 3, 4}, + {374, 105, 3, 4}, + // RISCV::CSRRWI - 32 + {389, 109, 3, 3}, + {398, 112, 3, 3}, + {410, 115, 3, 2}, + {425, 117, 3, 3}, + {438, 120, 3, 3}, + // RISCV::FADD_D - 37 + {454, 123, 4, 5}, + // RISCV::FADD_H - 38 + {472, 128, 4, 5}, + // RISCV::FADD_S - 39 + {490, 133, 4, 5}, + // RISCV::FCVT_D_L - 40 + {508, 138, 3, 5}, + // RISCV::FCVT_D_LU - 41 + {524, 143, 3, 5}, + // RISCV::FCVT_H_D - 42 + {541, 148, 3, 5}, + // RISCV::FCVT_H_L - 43 + {557, 153, 3, 5}, + // RISCV::FCVT_H_LU - 44 + {573, 158, 3, 5}, + // RISCV::FCVT_H_S - 45 + {590, 163, 3, 4}, + // RISCV::FCVT_H_W - 46 + {606, 167, 3, 4}, + // RISCV::FCVT_H_WU - 47 + {622, 171, 3, 4}, + // RISCV::FCVT_LU_D - 48 + {639, 175, 3, 5}, + // RISCV::FCVT_LU_H - 49 + {656, 180, 3, 5}, + // RISCV::FCVT_LU_S - 50 + {673, 185, 3, 5}, + // RISCV::FCVT_L_D - 51 + {690, 190, 3, 5}, + // RISCV::FCVT_L_H - 52 + {706, 195, 3, 5}, + // RISCV::FCVT_L_S - 53 + {722, 200, 3, 5}, + // RISCV::FCVT_S_D - 54 + {738, 205, 3, 4}, + // RISCV::FCVT_S_L - 55 + {754, 209, 3, 5}, + // RISCV::FCVT_S_LU - 56 + {770, 214, 3, 5}, + // RISCV::FCVT_S_W - 57 + {787, 219, 3, 4}, + // RISCV::FCVT_S_WU - 58 + {803, 223, 3, 4}, + // RISCV::FCVT_WU_D - 59 + {820, 227, 3, 4}, + // RISCV::FCVT_WU_H - 60 + {837, 231, 3, 4}, + // RISCV::FCVT_WU_S - 61 + {854, 235, 3, 4}, + // RISCV::FCVT_W_D - 62 + {871, 239, 3, 4}, + // RISCV::FCVT_W_H - 63 + {887, 243, 3, 4}, + // RISCV::FCVT_W_S - 64 + {903, 247, 3, 4}, + // RISCV::FDIV_D - 65 + {919, 251, 4, 5}, + // RISCV::FDIV_H - 66 + {937, 256, 4, 5}, + // RISCV::FDIV_S - 67 + {955, 261, 4, 5}, + // RISCV::FENCE - 68 + {973, 266, 2, 2}, + // RISCV::FMADD_D - 69 + {979, 268, 5, 6}, + // RISCV::FMADD_H - 70 + {1002, 274, 5, 6}, + // RISCV::FMADD_S - 71 + {1025, 280, 5, 6}, + // RISCV::FMSUB_D - 72 + {1048, 286, 5, 6}, + // RISCV::FMSUB_H - 73 + {1071, 292, 5, 6}, + // RISCV::FMSUB_S - 74 + {1094, 298, 5, 6}, + // RISCV::FMUL_D - 75 + {1117, 304, 4, 5}, + // RISCV::FMUL_H - 76 + {1135, 309, 4, 5}, + // RISCV::FMUL_S - 77 + {1153, 314, 4, 5}, + // RISCV::FNMADD_D - 78 + {1171, 319, 5, 6}, + // RISCV::FNMADD_H - 79 + {1195, 325, 5, 6}, + // RISCV::FNMADD_S - 80 + {1219, 331, 5, 6}, + // RISCV::FNMSUB_D - 81 + {1243, 337, 5, 6}, + // RISCV::FNMSUB_H - 82 + {1267, 343, 5, 6}, + // RISCV::FNMSUB_S - 83 + {1291, 349, 5, 6}, + // RISCV::FSGNJN_D - 84 + {1315, 355, 3, 4}, + // RISCV::FSGNJN_H - 85 + {1329, 359, 3, 4}, + // RISCV::FSGNJN_S - 86 + {1343, 363, 3, 4}, + // RISCV::FSGNJX_D - 87 + {1357, 367, 3, 4}, + // RISCV::FSGNJX_H - 88 + {1371, 371, 3, 4}, + // RISCV::FSGNJX_S - 89 + {1385, 375, 3, 4}, + // RISCV::FSGNJ_D - 90 + {1399, 379, 3, 4}, + // RISCV::FSGNJ_H - 91 + {1412, 383, 3, 4}, + // RISCV::FSGNJ_S - 92 + {1425, 387, 3, 4}, + // RISCV::FSQRT_D - 93 + {1438, 391, 3, 4}, + // RISCV::FSQRT_H - 94 + {1453, 395, 3, 4}, + // RISCV::FSQRT_S - 95 + {1468, 399, 3, 4}, + // RISCV::FSUB_D - 96 + {1483, 403, 4, 5}, + // RISCV::FSUB_H - 97 + {1501, 408, 4, 5}, + // RISCV::FSUB_S - 98 + {1519, 413, 4, 5}, + // RISCV::GORCI - 99 + {1537, 418, 3, 4}, + {1550, 422, 3, 4}, + {1564, 426, 3, 4}, + {1577, 430, 3, 4}, + {1591, 434, 3, 4}, + {1605, 438, 3, 4}, + {1619, 442, 3, 4}, + {1633, 446, 3, 4}, + {1647, 450, 3, 4}, + {1660, 454, 3, 5}, + {1673, 459, 3, 5}, + {1685, 464, 3, 5}, + {1697, 469, 3, 5}, + {1709, 474, 3, 5}, + {1720, 479, 3, 5}, + {1735, 484, 3, 5}, + {1749, 489, 3, 5}, + {1763, 494, 3, 5}, + {1777, 499, 3, 5}, + {1790, 504, 3, 5}, + {1660, 509, 3, 5}, + {1673, 514, 3, 5}, + {1685, 519, 3, 5}, + {1697, 524, 3, 5}, + {1709, 529, 3, 5}, + // RISCV::GREVI - 124 + {1803, 534, 3, 4}, + {1816, 538, 3, 4}, + {1830, 542, 3, 4}, + {1843, 546, 3, 4}, + {1857, 550, 3, 4}, + {1871, 554, 3, 4}, + {1884, 558, 3, 4}, + {1898, 562, 3, 4}, + {1912, 566, 3, 4}, + {1926, 570, 3, 4}, + {1939, 574, 3, 5}, + {1952, 579, 3, 5}, + {1964, 584, 3, 5}, + {1976, 589, 3, 5}, + {1987, 594, 3, 5}, + {2002, 599, 3, 5}, + {2016, 604, 3, 5}, + {2030, 609, 3, 5}, + {2044, 614, 3, 5}, + {2057, 619, 3, 5}, + {1939, 624, 3, 5}, + {1952, 629, 3, 5}, + {1964, 634, 3, 5}, + {1976, 639, 3, 5}, + // RISCV::JAL - 148 + {2070, 644, 2, 2}, + {2077, 646, 2, 2}, + // RISCV::JALR - 150 + {2086, 648, 3, 3}, + {2090, 651, 3, 3}, + {2096, 654, 3, 3}, + {2104, 657, 3, 3}, + {2116, 660, 3, 3}, + {2126, 663, 3, 3}, + // RISCV::SFENCE_VMA - 156 + {2138, 666, 2, 2}, + {2149, 668, 2, 2}, + // RISCV::SHFLI - 158 + {2163, 670, 3, 4}, + {2176, 674, 3, 4}, + {2190, 678, 3, 4}, + {2203, 682, 3, 4}, + {2217, 686, 3, 4}, + {2231, 690, 3, 4}, + {2244, 694, 3, 5}, + {2256, 699, 3, 5}, + {2268, 704, 3, 5}, + {2280, 709, 3, 5}, + {2291, 714, 3, 5}, + {2305, 719, 3, 5}, + {2319, 724, 3, 5}, + {2333, 729, 3, 5}, + {2346, 734, 3, 5}, + {2244, 739, 3, 5}, + {2256, 744, 3, 5}, + {2268, 749, 3, 5}, + {2280, 754, 3, 5}, + // RISCV::SLT - 177 + {2359, 759, 3, 3}, + {2371, 762, 3, 3}, + // RISCV::SLTIU - 179 + {2383, 765, 3, 3}, + // RISCV::SLTU - 180 + {2395, 768, 3, 3}, + // RISCV::SUB - 181 + {2407, 771, 3, 3}, + // RISCV::SUBW - 182 + {2418, 774, 3, 4}, + // RISCV::UNSHFLI - 183 + {2430, 778, 3, 4}, + {2445, 782, 3, 4}, + {2461, 786, 3, 4}, + {2476, 790, 3, 4}, + {2492, 794, 3, 4}, + {2508, 798, 3, 4}, + {2523, 802, 3, 5}, + {2537, 807, 3, 5}, + {2551, 812, 3, 5}, + {2565, 817, 3, 5}, + {2578, 822, 3, 5}, + {2594, 827, 3, 5}, + {2610, 832, 3, 5}, + {2626, 837, 3, 5}, + {2641, 842, 3, 5}, + {2523, 847, 3, 5}, + {2537, 852, 3, 5}, + {2551, 857, 3, 5}, + {2565, 862, 3, 5}, + // RISCV::VFSGNJN_VV - 202 + {2656, 867, 4, 6}, + // RISCV::VFSGNJX_VV - 203 + {2675, 873, 4, 6}, + // RISCV::VL1RE8_V - 204 + {2694, 879, 2, 3}, + // RISCV::VL2RE8_V - 205 + {2710, 882, 2, 3}, + // RISCV::VL4RE8_V - 206 + {2726, 885, 2, 3}, + // RISCV::VL8RE8_V - 207 + {2742, 888, 2, 3}, + // RISCV::VMAND_MM - 208 + {2758, 891, 3, 4}, + // RISCV::VMNAND_MM - 209 + {2772, 895, 3, 4}, + // RISCV::VMXNOR_MM - 210 + {2787, 899, 3, 4}, + // RISCV::VMXOR_MM - 211 + {2798, 903, 3, 4}, + // RISCV::VNSRL_WX - 212 + {2809, 907, 4, 5}, + // RISCV::VRSUB_VX - 213 + {2832, 912, 4, 5}, + // RISCV::VWADDU_VX - 214 + {2850, 917, 4, 5}, + // RISCV::VWADD_VX - 215 + {2874, 922, 4, 5}, + // RISCV::VXOR_VI - 216 + {2897, 927, 4, 5}, + // RISCV::XORI - 217 + {2915, 932, 3, 3}, + }; + + static const AliasPatternCond Conds[] = { + // (ADDI X0, X0, 0) - 0 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDI GPR:$rd, X0, simm12:$imm) - 3 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Custom, 1}, + // (ADDI GPR:$rd, GPR:$rs, 0) - 6 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (ADDIW GPR:$rd, GPR:$rs, 0) - 9 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (ADDUW GPR:$rd, GPR:$rs, X0) - 13 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZba}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (BEQ GPR:$rs, X0, simm13_lsb0:$offset) - 18 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Custom, 2}, + // (BGE X0, GPR:$rs, simm13_lsb0:$offset) - 21 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Custom, 2}, + // (BGE GPR:$rs, X0, simm13_lsb0:$offset) - 24 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Custom, 2}, + // (BLT GPR:$rs, X0, simm13_lsb0:$offset) - 27 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Custom, 2}, + // (BLT X0, GPR:$rs, simm13_lsb0:$offset) - 30 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Custom, 2}, + // (BNE GPR:$rs, X0, simm13_lsb0:$offset) - 33 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Custom, 2}, + // (CSRRC X0, csr_sysreg:$csr, GPR:$rs) - 36 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm) - 39 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Ignore, 0}, + // (CSRRS GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 }, X0) - 41 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRS GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, X0) - 45 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRS GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, X0) - 49 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRS GPR:$rd, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, X0) - 53 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3074}, + {AliasPatternCond_K_Reg, RISCV_X0}, + // (CSRRS GPR:$rd, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, X0) - 56 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3072}, + {AliasPatternCond_K_Reg, RISCV_X0}, + // (CSRRS GPR:$rd, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, X0) - 59 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3073}, + {AliasPatternCond_K_Reg, RISCV_X0}, + // (CSRRS GPR:$rd, { 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0 }, X0) - 62 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3202}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (CSRRS GPR:$rd, { 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 }, X0) - 66 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3200}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (CSRRS GPR:$rd, { 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1 }, X0) - 70 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3201}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (CSRRS GPR:$rd, csr_sysreg:$csr, X0) - 74 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Reg, RISCV_X0}, + // (CSRRS X0, csr_sysreg:$csr, GPR:$rs) - 77 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm) - 80 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Ignore, 0}, + // (CSRRW X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 }, GPR:$rs) - 82 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRW X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, GPR:$rs) - 86 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRW X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, GPR:$rs) - 90 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRW X0, csr_sysreg:$csr, GPR:$rs) - 94 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + // (CSRRW GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 }, GPR:$rs) - 97 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRW GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, GPR:$rs) - 101 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRW GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, GPR:$rs) - 105 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRWI X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, uimm5:$imm) - 109 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRWI X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, uimm5:$imm) - 112 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm) - 115 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Ignore, 0}, + // (CSRRWI GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, uimm5:$imm) - + // 117 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (CSRRWI GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, uimm5:$imm) - + // 120 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 123 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FADD_H FPR16:$rd, FPR16:$rs1, FPR16:$rs2, { 1, 1, 1 }) - 128 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 133 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) - 138 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) - 143 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_H_D FPR16:$rd, FPR64:$rs1, { 1, 1, 1 }) - 148 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfhmin}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FCVT_H_L FPR16:$rd, GPR:$rs1, { 1, 1, 1 }) - 153 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_H_LU FPR16:$rd, GPR:$rs1, { 1, 1, 1 }) - 158 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_H_S FPR16:$rd, FPR32:$rs1, { 1, 1, 1 }) - 163 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfhmin}, + // (FCVT_H_W FPR16:$rd, GPR:$rs1, { 1, 1, 1 }) - 167 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FCVT_H_WU FPR16:$rd, GPR:$rs1, { 1, 1, 1 }) - 171 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 175 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_LU_H GPR:$rd, FPR16:$rs1, { 1, 1, 1 }) - 180 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 185 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 190 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_L_H GPR:$rd, FPR16:$rs1, { 1, 1, 1 }) - 195 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 200 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 }) - 205 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 209 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 214 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 219 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 223 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 227 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FCVT_WU_H GPR:$rd, FPR16:$rs1, { 1, 1, 1 }) - 231 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 235 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 239 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FCVT_W_H GPR:$rd, FPR16:$rs1, { 1, 1, 1 }) - 243 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 247 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 251 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FDIV_H FPR16:$rd, FPR16:$rs1, FPR16:$rs2, { 1, 1, 1 }) - 256 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 261 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FENCE 15, 15) - 266 + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - + // 268 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FMADD_H FPR16:$rd, FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, { 1, 1, 1 }) - + // 274 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - + // 280 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - + // 286 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FMSUB_H FPR16:$rd, FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, { 1, 1, 1 }) - + // 292 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - + // 298 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 304 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FMUL_H FPR16:$rd, FPR16:$rs1, FPR16:$rs2, { 1, 1, 1 }) - 309 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 314 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - + // 319 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FNMADD_H FPR16:$rd, FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, { 1, 1, 1 }) - + // 325 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - + // 331 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - + // 337 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FNMSUB_H FPR16:$rd, FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, { 1, 1, 1 }) - + // 343 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - + // 349 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - 355 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FSGNJN_H FPR16:$rd, FPR16:$rs, FPR16:$rs) - 359 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - 363 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - 367 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FSGNJX_H FPR16:$rd, FPR16:$rs, FPR16:$rs) - 371 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - 375 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - 379 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FSGNJ_H FPR16:$rd, FPR16:$rs, FPR16:$rs) - 383 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - 387 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 }) - 391 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FSQRT_H FPR16:$rd, FPR16:$rs1, { 1, 1, 1 }) - 395 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 }) - 399 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 403 + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR64RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtD}, + // (FSUB_H FPR16:$rd, FPR16:$rs1, FPR16:$rs2, { 1, 1, 1 }) - 408 + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR16RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZfh}, + // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 413 + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_FPR32RegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 0, 0, 0, 1 }) - 418 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 0, 0, 1, 0 }) - 422 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 0, 0, 1, 1 }) - 426 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 0, 1, 0, 0 }) - 430 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 0, 1, 1, 0 }) - 434 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 1, 0, 0, 0 }) - 438 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 1, 1, 0, 0 }) - 442 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 0 }) - 446 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 1 }) - 450 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 0, 0, 0, 0 }) - 454 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 1, 0, 0, 0 }) - 459 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 1, 1, 0, 0 }) - 464 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 0 }) - 469 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)30}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 1 }) - 474 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 1, 0, 0, 0, 0 }) - 479 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 1, 1, 0, 0, 0 }) - 484 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 0, 0 }) - 489 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 1, 0 }) - 494 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)30}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 1, 1 }) - 499 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 0, 0, 0, 0, 0 }) - 504 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)32}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 1, 0, 0, 0, 0 }) - 509 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)48}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 1, 1, 0, 0, 0 }) - 514 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)56}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 0, 0 }) - 519 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)60}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 1, 0 }) - 524 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)62}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GORCI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 1, 1 }) - 529 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)63}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 0, 0, 0, 1 }) - 534 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 0, 0, 1, 0 }) - 538 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 0, 0, 1, 1 }) - 542 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 0, 1, 0, 0 }) - 546 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 0, 1, 1, 0 }) - 550 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 0, 1, 1, 1 }) - 554 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 1, 0, 0, 0 }) - 558 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 1, 1, 0, 0 }) - 562 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 0 }) - 566 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 1 }) - 570 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (GREVI GPR:$rd, GPR:$rs, { 1, 0, 0, 0, 0 }) - 574 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 1, 1, 1, 0, 0 }) - 579 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 0 }) - 584 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)30}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 1 }) - 589 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 1, 0, 0, 0, 0 }) - 594 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 1, 1, 0, 0, 0 }) - 599 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 0, 0 }) - 604 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 1, 0 }) - 609 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)30}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 1, 1 }) - 614 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 1, 0, 0, 0, 0, 0 }) - 619 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)32}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 1, 1, 0, 0, 0, 0 }) - 624 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)48}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 0, 0 }) - 629 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)60}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 1, 0 }) - 634 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)62}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (GREVI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 1, 1 }) - 639 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)63}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (JAL X0, simm21_lsb0_jal:$offset) - 644 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Custom, 3}, + // (JAL X1, simm21_lsb0_jal:$offset) - 646 + {AliasPatternCond_K_Reg, RISCV_X1}, + {AliasPatternCond_K_Custom, 3}, + // (JALR X0, X1, 0) - 648 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Reg, RISCV_X1}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JALR X0, GPR:$rs, 0) - 651 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JALR X1, GPR:$rs, 0) - 654 + {AliasPatternCond_K_Reg, RISCV_X1}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JALR GPR:$rd, GPR:$rs, 0) - 657 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (JALR X0, GPR:$rs, simm12:$offset) - 660 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Custom, 1}, + // (JALR X1, GPR:$rs, simm12:$offset) - 663 + {AliasPatternCond_K_Reg, RISCV_X1}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Custom, 1}, + // (SFENCE_VMA X0, X0) - 666 + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_Reg, RISCV_X0}, + // (SFENCE_VMA GPR:$rs, X0) - 668 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 0, 0, 1 }) - 670 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 0, 1, 0 }) - 674 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 0, 1, 1 }) - 678 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 1, 0, 0 }) - 682 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 0 }) - 686 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 1 }) - 690 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (SHFLI GPR:$rd, GPR:$rs, { 1, 0, 0, 0 }) - 694 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 1, 1, 0, 0 }) - 699 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 0 }) - 704 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 1 }) - 709 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 1, 0, 0, 0 }) - 714 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 0, 0 }) - 719 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 0 }) - 724 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 1 }) - 729 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 1, 0, 0, 0, 0 }) - 734 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 1, 1, 0, 0, 0 }) - 739 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 0, 0 }) - 744 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 0 }) - 749 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)30}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (SHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 1 }) - 754 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (SLT GPR:$rd, GPR:$rs, X0) - 759 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + // (SLT GPR:$rd, X0, GPR:$rs) - 762 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + // (SLTIU GPR:$rd, GPR:$rs, 1) - 765 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (SLTU GPR:$rd, X0, GPR:$rs) - 768 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + // (SUB GPR:$rd, X0, GPR:$rs) - 771 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + // (SUBW GPR:$rd, X0, GPR:$rs) - 774 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 0, 0, 1 }) - 778 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 0, 1, 0 }) - 782 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 0, 1, 1 }) - 786 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 1, 0, 0 }) - 790 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 0 }) - 794 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 1 }) - 798 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 1, 0, 0, 0 }) - 802 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 1, 1, 0, 0 }) - 807 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 0 }) - 812 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 1 }) - 817 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_NegFeature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 1, 0, 0, 0 }) - 822 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 0, 0 }) - 827 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 0 }) - 832 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 0, 1, 1, 1, 1 }) - 837 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 1, 0, 0, 0, 0 }) - 842 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)16}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 1, 1, 0, 0, 0 }) - 847 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)24}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 0, 0 }) - 852 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)28}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 0 }) - 857 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)30}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (UNSHFLI GPR:$rd, GPR:$rs, { 1, 1, 1, 1, 1 }) - 862 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)31}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtZbp}, + {AliasPatternCond_K_Feature, RISCV_Feature64Bit}, + // (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm) - 867 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_RegClass, RISCV_VMV0RegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm) - 873 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_RegClass, RISCV_VMV0RegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtF}, + // (VL1RE8_V VR:$vd, GPR:$rs1) - 879 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VL2RE8_V VRM2:$vd, GPR:$rs1) - 882 + {AliasPatternCond_K_RegClass, RISCV_VRM2RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VL4RE8_V VRM4:$vd, GPR:$rs1) - 885 + {AliasPatternCond_K_RegClass, RISCV_VRM4RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VL8RE8_V VRM8:$vd, GPR:$rs1) - 888 + {AliasPatternCond_K_RegClass, RISCV_VRM8RegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VMAND_MM VR:$vd, VR:$vs, VR:$vs) - 891 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VMNAND_MM VR:$vd, VR:$vs, VR:$vs) - 895 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_TiedReg, 1}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VMXNOR_MM VR:$vd, VR:$vd, VR:$vd) - 899 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VMXOR_MM VR:$vd, VR:$vd, VR:$vd) - 903 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_TiedReg, 0}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VNSRL_WX VR:$vd, VR:$vs, X0, VMaskOp:$vm) - 907 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_VMV0RegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm) - 912 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_VMV0RegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VWADDU_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm) - 917 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_VMV0RegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm) - 922 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_Reg, RISCV_X0}, + {AliasPatternCond_K_RegClass, RISCV_VMV0RegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm) - 927 + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_VRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)-1}, + {AliasPatternCond_K_RegClass, RISCV_VMV0RegClassID}, + {AliasPatternCond_K_Feature, RISCV_FeatureStdExtV}, + // (XORI GPR:$rd, GPR:$rs, -1) - 932 + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_RegClass, RISCV_GPRRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)-1}, + }; + + static const char *AsmStrings[] = { + /* 0 */ "nop\0" + /* 4 */ "li $\x01, $\x03\0" + /* 14 */ "mv $\x01, $\x02\0" + /* 24 */ "sext.w $\x01, $\x02\0" + /* 38 */ "zext.w $\x01, $\x02\0" + /* 52 */ "beqz $\x01, $\xFF\x03\x01\0" + /* 66 */ "blez $\x02, $\xFF\x03\x01\0" + /* 80 */ "bgez $\x01, $\xFF\x03\x01\0" + /* 94 */ "bltz $\x01, $\xFF\x03\x01\0" + /* 108 */ "bgtz $\x02, $\xFF\x03\x01\0" + /* 122 */ "bnez $\x01, $\xFF\x03\x01\0" + /* 136 */ "csrc $\xFF\x02\x02, $\x03\0" + /* 150 */ "csrci $\xFF\x02\x02, $\x03\0" + /* 165 */ "frcsr $\x01\0" + /* 174 */ "frrm $\x01\0" + /* 182 */ "frflags $\x01\0" + /* 193 */ "rdinstret $\x01\0" + /* 206 */ "rdcycle $\x01\0" + /* 217 */ "rdtime $\x01\0" + /* 227 */ "rdinstreth $\x01\0" + /* 241 */ "rdcycleh $\x01\0" + /* 253 */ "rdtimeh $\x01\0" + /* 264 */ "csrr $\x01, $\xFF\x02\x02\0" + /* 278 */ "csrs $\xFF\x02\x02, $\x03\0" + /* 292 */ "csrsi $\xFF\x02\x02, $\x03\0" + /* 307 */ "fscsr $\x03\0" + /* 316 */ "fsrm $\x03\0" + /* 324 */ "fsflags $\x03\0" + /* 335 */ "csrw $\xFF\x02\x02, $\x03\0" + /* 349 */ "fscsr $\x01, $\x03\0" + /* 362 */ "fsrm $\x01, $\x03\0" + /* 374 */ "fsflags $\x01, $\x03\0" + /* 389 */ "fsrmi $\x03\0" + /* 398 */ "fsflagsi $\x03\0" + /* 410 */ "csrwi $\xFF\x02\x02, $\x03\0" + /* 425 */ "fsrmi $\x01, $\x03\0" + /* 438 */ "fsflagsi $\x01, $\x03\0" + /* 454 */ "fadd.d $\x01, $\x02, $\x03\0" + /* 472 */ "fadd.h $\x01, $\x02, $\x03\0" + /* 490 */ "fadd.s $\x01, $\x02, $\x03\0" + /* 508 */ "fcvt.d.l $\x01, $\x02\0" + /* 524 */ "fcvt.d.lu $\x01, $\x02\0" + /* 541 */ "fcvt.h.d $\x01, $\x02\0" + /* 557 */ "fcvt.h.l $\x01, $\x02\0" + /* 573 */ "fcvt.h.lu $\x01, $\x02\0" + /* 590 */ "fcvt.h.s $\x01, $\x02\0" + /* 606 */ "fcvt.h.w $\x01, $\x02\0" + /* 622 */ "fcvt.h.wu $\x01, $\x02\0" + /* 639 */ "fcvt.lu.d $\x01, $\x02\0" + /* 656 */ "fcvt.lu.h $\x01, $\x02\0" + /* 673 */ "fcvt.lu.s $\x01, $\x02\0" + /* 690 */ "fcvt.l.d $\x01, $\x02\0" + /* 706 */ "fcvt.l.h $\x01, $\x02\0" + /* 722 */ "fcvt.l.s $\x01, $\x02\0" + /* 738 */ "fcvt.s.d $\x01, $\x02\0" + /* 754 */ "fcvt.s.l $\x01, $\x02\0" + /* 770 */ "fcvt.s.lu $\x01, $\x02\0" + /* 787 */ "fcvt.s.w $\x01, $\x02\0" + /* 803 */ "fcvt.s.wu $\x01, $\x02\0" + /* 820 */ "fcvt.wu.d $\x01, $\x02\0" + /* 837 */ "fcvt.wu.h $\x01, $\x02\0" + /* 854 */ "fcvt.wu.s $\x01, $\x02\0" + /* 871 */ "fcvt.w.d $\x01, $\x02\0" + /* 887 */ "fcvt.w.h $\x01, $\x02\0" + /* 903 */ "fcvt.w.s $\x01, $\x02\0" + /* 919 */ "fdiv.d $\x01, $\x02, $\x03\0" + /* 937 */ "fdiv.h $\x01, $\x02, $\x03\0" + /* 955 */ "fdiv.s $\x01, $\x02, $\x03\0" + /* 973 */ "fence\0" + /* 979 */ "fmadd.d $\x01, $\x02, $\x03, $\x04\0" + /* 1002 */ "fmadd.h $\x01, $\x02, $\x03, $\x04\0" + /* 1025 */ "fmadd.s $\x01, $\x02, $\x03, $\x04\0" + /* 1048 */ "fmsub.d $\x01, $\x02, $\x03, $\x04\0" + /* 1071 */ "fmsub.h $\x01, $\x02, $\x03, $\x04\0" + /* 1094 */ "fmsub.s $\x01, $\x02, $\x03, $\x04\0" + /* 1117 */ "fmul.d $\x01, $\x02, $\x03\0" + /* 1135 */ "fmul.h $\x01, $\x02, $\x03\0" + /* 1153 */ "fmul.s $\x01, $\x02, $\x03\0" + /* 1171 */ "fnmadd.d $\x01, $\x02, $\x03, $\x04\0" + /* 1195 */ "fnmadd.h $\x01, $\x02, $\x03, $\x04\0" + /* 1219 */ "fnmadd.s $\x01, $\x02, $\x03, $\x04\0" + /* 1243 */ "fnmsub.d $\x01, $\x02, $\x03, $\x04\0" + /* 1267 */ "fnmsub.h $\x01, $\x02, $\x03, $\x04\0" + /* 1291 */ "fnmsub.s $\x01, $\x02, $\x03, $\x04\0" + /* 1315 */ "fneg.d $\x01, $\x02\0" + /* 1329 */ "fneg.h $\x01, $\x02\0" + /* 1343 */ "fneg.s $\x01, $\x02\0" + /* 1357 */ "fabs.d $\x01, $\x02\0" + /* 1371 */ "fabs.h $\x01, $\x02\0" + /* 1385 */ "fabs.s $\x01, $\x02\0" + /* 1399 */ "fmv.d $\x01, $\x02\0" + /* 1412 */ "fmv.h $\x01, $\x02\0" + /* 1425 */ "fmv.s $\x01, $\x02\0" + /* 1438 */ "fsqrt.d $\x01, $\x02\0" + /* 1453 */ "fsqrt.h $\x01, $\x02\0" + /* 1468 */ "fsqrt.s $\x01, $\x02\0" + /* 1483 */ "fsub.d $\x01, $\x02, $\x03\0" + /* 1501 */ "fsub.h $\x01, $\x02, $\x03\0" + /* 1519 */ "fsub.s $\x01, $\x02, $\x03\0" + /* 1537 */ "orc.p $\x01, $\x02\0" + /* 1550 */ "orc2.n $\x01, $\x02\0" + /* 1564 */ "orc.n $\x01, $\x02\0" + /* 1577 */ "orc4.b $\x01, $\x02\0" + /* 1591 */ "orc2.b $\x01, $\x02\0" + /* 1605 */ "orc8.h $\x01, $\x02\0" + /* 1619 */ "orc4.h $\x01, $\x02\0" + /* 1633 */ "orc2.h $\x01, $\x02\0" + /* 1647 */ "orc.h $\x01, $\x02\0" + /* 1660 */ "orc16 $\x01, $\x02\0" + /* 1673 */ "orc8 $\x01, $\x02\0" + /* 1685 */ "orc4 $\x01, $\x02\0" + /* 1697 */ "orc2 $\x01, $\x02\0" + /* 1709 */ "orc $\x01, $\x02\0" + /* 1720 */ "orc16.w $\x01, $\x02\0" + /* 1735 */ "orc8.w $\x01, $\x02\0" + /* 1749 */ "orc4.w $\x01, $\x02\0" + /* 1763 */ "orc2.w $\x01, $\x02\0" + /* 1777 */ "orc.w $\x01, $\x02\0" + /* 1790 */ "orc32 $\x01, $\x02\0" + /* 1803 */ "rev.p $\x01, $\x02\0" + /* 1816 */ "rev2.n $\x01, $\x02\0" + /* 1830 */ "rev.n $\x01, $\x02\0" + /* 1843 */ "rev4.b $\x01, $\x02\0" + /* 1857 */ "rev2.b $\x01, $\x02\0" + /* 1871 */ "rev.b $\x01, $\x02\0" + /* 1884 */ "rev8.h $\x01, $\x02\0" + /* 1898 */ "rev4.h $\x01, $\x02\0" + /* 1912 */ "rev2.h $\x01, $\x02\0" + /* 1926 */ "rev.h $\x01, $\x02\0" + /* 1939 */ "rev16 $\x01, $\x02\0" + /* 1952 */ "rev4 $\x01, $\x02\0" + /* 1964 */ "rev2 $\x01, $\x02\0" + /* 1976 */ "rev $\x01, $\x02\0" + /* 1987 */ "rev16.w $\x01, $\x02\0" + /* 2002 */ "rev8.w $\x01, $\x02\0" + /* 2016 */ "rev4.w $\x01, $\x02\0" + /* 2030 */ "rev2.w $\x01, $\x02\0" + /* 2044 */ "rev.w $\x01, $\x02\0" + /* 2057 */ "rev32 $\x01, $\x02\0" + /* 2070 */ "j $\xFF\x02\x01\0" + /* 2077 */ "jal $\xFF\x02\x01\0" + /* 2086 */ "ret\0" + /* 2090 */ "jr $\x02\0" + /* 2096 */ "jalr $\x02\0" + /* 2104 */ "jalr $\x01, $\x02\0" + /* 2116 */ "jr $\x03($\x02)\0" + /* 2126 */ "jalr $\x03($\x02)\0" + /* 2138 */ "sfence.vma\0" + /* 2149 */ "sfence.vma $\x01\0" + /* 2163 */ "zip.n $\x01, $\x02\0" + /* 2176 */ "zip2.b $\x01, $\x02\0" + /* 2190 */ "zip.b $\x01, $\x02\0" + /* 2203 */ "zip4.h $\x01, $\x02\0" + /* 2217 */ "zip2.h $\x01, $\x02\0" + /* 2231 */ "zip.h $\x01, $\x02\0" + /* 2244 */ "zip8 $\x01, $\x02\0" + /* 2256 */ "zip4 $\x01, $\x02\0" + /* 2268 */ "zip2 $\x01, $\x02\0" + /* 2280 */ "zip $\x01, $\x02\0" + /* 2291 */ "zip8.w $\x01, $\x02\0" + /* 2305 */ "zip4.w $\x01, $\x02\0" + /* 2319 */ "zip2.w $\x01, $\x02\0" + /* 2333 */ "zip.w $\x01, $\x02\0" + /* 2346 */ "zip16 $\x01, $\x02\0" + /* 2359 */ "sltz $\x01, $\x02\0" + /* 2371 */ "sgtz $\x01, $\x03\0" + /* 2383 */ "seqz $\x01, $\x02\0" + /* 2395 */ "snez $\x01, $\x03\0" + /* 2407 */ "neg $\x01, $\x03\0" + /* 2418 */ "negw $\x01, $\x03\0" + /* 2430 */ "unzip.n $\x01, $\x02\0" + /* 2445 */ "unzip2.b $\x01, $\x02\0" + /* 2461 */ "unzip.b $\x01, $\x02\0" + /* 2476 */ "unzip4.h $\x01, $\x02\0" + /* 2492 */ "unzip2.h $\x01, $\x02\0" + /* 2508 */ "unzip.h $\x01, $\x02\0" + /* 2523 */ "unzip8 $\x01, $\x02\0" + /* 2537 */ "unzip4 $\x01, $\x02\0" + /* 2551 */ "unzip2 $\x01, $\x02\0" + /* 2565 */ "unzip $\x01, $\x02\0" + /* 2578 */ "unzip8.w $\x01, $\x02\0" + /* 2594 */ "unzip4.w $\x01, $\x02\0" + /* 2610 */ "unzip2.w $\x01, $\x02\0" + /* 2626 */ "unzip.w $\x01, $\x02\0" + /* 2641 */ "unzip16 $\x01, $\x02\0" + /* 2656 */ "vfneg.v $\x01, $\x02$\xFF\x04\x03\0" + /* 2675 */ "vfabs.v $\x01, $\x02$\xFF\x04\x03\0" + /* 2694 */ "vl1r.v $\x01, ($\x02)\0" + /* 2710 */ "vl2r.v $\x01, ($\x02)\0" + /* 2726 */ "vl4r.v $\x01, ($\x02)\0" + /* 2742 */ "vl8r.v $\x01, ($\x02)\0" + /* 2758 */ "vmmv.m $\x01, $\x02\0" + /* 2772 */ "vmnot.m $\x01, $\x02\0" + /* 2787 */ "vmset.m $\x01\0" + /* 2798 */ "vmclr.m $\x01\0" + /* 2809 */ "vncvt.x.x.w $\x01, $\x02$\xFF\x04\x03\0" + /* 2832 */ "vneg.v $\x01, $\x02$\xFF\x04\x03\0" + /* 2850 */ "vwcvtu.x.x.v $\x01, $\x02$\xFF\x04\x03\0" + /* 2874 */ "vwcvt.x.x.v $\x01, $\x02$\xFF\x04\x03\0" + /* 2897 */ "vnot.v $\x01, $\x02$\xFF\x04\x03\0" + /* 2915 */ "not $\x01, $\x02\0"}; + + const char *AsmString = MCInstPrinter_matchAliasPatterns( + MI, OpToPatterns, Patterns, Conds, AsmStrings, 103); + if (!AsmString) + return false; + + char *tmpString = cs_strdup(AsmString); + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, "\t"); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, *(tmpString + (I++))); + } + } while (AsmString[I] != '\0'); + } + + return tmpString; +} + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { + switch (PrintMethodIdx) { + default: + llvm_unreachable("Unknown PrintMethod kind"); + break; + // printBranchOperand + case 0: + printBranchOperand(MI, OpIdx, OS); + break; + // printCSRSystemRegister + case 1: + printCSRSystemRegister(MI, OpIdx, OS); + break; + // printVMaskReg + case 2: + printVMaskReg(MI, OpIdx, OS); + break; + } +} + +#endif // PRINT_ALIAS_INSTR +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo3[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo4[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo5[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo6[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo7[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo8[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo9[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo10[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo11[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo12[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo13[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo14[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo15[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo16[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo17[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo18[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo19[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo20[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo21[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo22[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo23[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo24[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo25[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo26[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo27[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo28[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo29[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo30[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo31[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo32[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo33[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo34[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo35[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo36[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo37[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo38[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo39[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo40[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo41[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo42[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo43[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo44[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo45[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo46[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo47[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo48[] = { + {RISCV_GPRJALRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo49[] = { + {RISCV_GPRJALRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo50[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo51[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo52[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo53[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo54[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo55[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo56[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo57[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo58[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo59[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo60[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo61[] = { + {RISCV_GPRTCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo62[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo63[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo64[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo65[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo66[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo67[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo68[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo69[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo70[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo71[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo72[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo73[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo74[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo75[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo76[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo77[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo78[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo79[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo80[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo81[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo82[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo83[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo84[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo85[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo86[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo87[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo88[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo89[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo90[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo91[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo92[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo93[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo94[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo95[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo96[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo97[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo98[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo99[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo100[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo101[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo102[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo103[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo104[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo105[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo106[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo107[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo108[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo109[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo110[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo111[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo112[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo113[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo114[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo115[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo116[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo117[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo118[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo119[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo120[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo121[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo122[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo123[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo124[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo125[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo126[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo127[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo128[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo129[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo130[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo131[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo132[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo133[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo134[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo135[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo136[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo137[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo138[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo139[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo140[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo141[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo142[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo143[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo144[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo145[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo146[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo147[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo148[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo149[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo150[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo151[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo152[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo153[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo154[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo155[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo156[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo157[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo158[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo159[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo160[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo161[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo162[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo163[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo164[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo165[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo166[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo167[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo168[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo169[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo170[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo171[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo172[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo173[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo174[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo175[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo176[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo177[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo178[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo179[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo180[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo181[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo182[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo183[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo184[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo185[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo186[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo187[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo188[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo189[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo190[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo191[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo192[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo193[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo194[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo195[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo196[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo197[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo198[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo199[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo200[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo201[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo202[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo203[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo204[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo205[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo206[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo207[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo208[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo209[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo210[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo211[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo212[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo213[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo214[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo215[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo216[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo217[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo218[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo219[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo220[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo221[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo222[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo223[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo224[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo225[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo226[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo227[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo228[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo229[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo230[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo231[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo232[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo233[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo234[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo235[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo236[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo237[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo238[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo239[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo240[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo241[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo242[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo243[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo244[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo245[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo246[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo247[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo248[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo249[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo250[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo251[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo252[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo253[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo254[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo255[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo256[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo257[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo258[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo259[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo260[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo261[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo262[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo263[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo264[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo265[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo266[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo267[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo268[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo269[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo270[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo271[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo272[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo273[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo274[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo275[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo276[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo277[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo278[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo279[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo280[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo281[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo282[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo283[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo284[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo285[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo286[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo287[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo288[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo289[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo290[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo291[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo292[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo293[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo294[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo295[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo296[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo297[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo298[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo299[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo300[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo301[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo302[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo303[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo304[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo305[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo306[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo307[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo308[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo309[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo310[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo311[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo312[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo313[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo314[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo315[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo316[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo317[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo318[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo319[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo320[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo321[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo322[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo323[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo324[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo325[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo326[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo327[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo328[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo329[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo330[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo331[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo332[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo333[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo334[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo335[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo336[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo337[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo338[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo339[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo340[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo341[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo342[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo343[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo344[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo345[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo346[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo347[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo348[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo349[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo350[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo351[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo352[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo353[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo354[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo355[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo356[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo357[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo358[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo359[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo360[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo361[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo362[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo363[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo364[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo365[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo366[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo367[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo368[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo369[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo370[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo371[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo372[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo373[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo374[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo375[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo376[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo377[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo378[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo379[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo380[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo381[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo382[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo383[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo384[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo385[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo386[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo387[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo388[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo389[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo390[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo391[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo392[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo393[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo394[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo395[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo396[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo397[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo398[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo399[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo400[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo401[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo402[] = { + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo403[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo404[] = { + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo405[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo406[] = { + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo407[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo408[] = { + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo409[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo410[] = { + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo411[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo412[] = { + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo413[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo414[] = { + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo415[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo416[] = { + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo417[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo418[] = { + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo419[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo420[] = { + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo421[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo422[] = { + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo423[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo424[] = { + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo425[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo426[] = { + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo427[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo428[] = { + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo429[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo430[] = { + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo431[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo432[] = { + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo433[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo434[] = { + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo435[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo436[] = { + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo437[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo438[] = { + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo439[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo440[] = { + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo441[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo442[] = { + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo443[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo444[] = { + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo445[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo446[] = { + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo447[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo448[] = { + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo449[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo450[] = { + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo451[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo452[] = { + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo453[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo454[] = { + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo455[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo456[] = { + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo457[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo458[] = { + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo459[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo460[] = { + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo461[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo462[] = { + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo463[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo464[] = { + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo465[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo466[] = { + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo467[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo468[] = { + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo469[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo470[] = { + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo471[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo472[] = { + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo473[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo474[] = { + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo475[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo476[] = { + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo477[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo478[] = { + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo479[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo480[] = { + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo481[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo482[] = { + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo483[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo484[] = { + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo485[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo486[] = { + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo487[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo488[] = { + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo489[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo490[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo491[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo492[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo493[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo494[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo495[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo496[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo497[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo498[] = { + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo499[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo500[] = { + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo501[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo502[] = { + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo503[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo504[] = { + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo505[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo506[] = { + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo507[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo508[] = { + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo509[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo510[] = { + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo511[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo512[] = { + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo513[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo514[] = { + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo515[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo516[] = { + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo517[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo518[] = { + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo519[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo520[] = { + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN2M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo521[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo522[] = { + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN2M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo523[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo524[] = { + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN2M4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo525[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo526[] = { + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN3M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo527[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo528[] = { + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN3M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo529[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo530[] = { + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN4M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo531[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo532[] = { + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN4M2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo533[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo534[] = { + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN5M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo535[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo536[] = { + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN6M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo537[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo538[] = { + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN7M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo539[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo540[] = { + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRN8M1NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo541[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo542[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo543[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo544[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo545[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo546[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo547[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo548[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo549[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo550[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo551[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo552[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo553[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo554[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo555[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo556[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo557[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo558[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo559[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo560[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo561[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo562[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo563[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo564[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo565[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo566[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo567[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo568[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo569[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo570[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo571[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo572[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo573[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo574[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo575[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo576[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo577[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo578[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo579[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo580[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo581[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo582[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo583[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo584[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo585[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo586[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo587[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo588[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo589[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo590[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo591[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo592[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo593[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo594[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo595[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo596[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo597[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo598[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo599[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo600[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo601[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo602[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo603[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo604[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo605[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo606[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo607[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo608[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo609[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo610[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo611[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo612[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo613[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo614[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo615[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo616[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo617[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo618[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo619[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo620[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo621[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo622[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo623[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo624[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo625[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo626[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo627[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo628[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo629[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo630[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo631[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo632[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo633[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo634[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo635[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo636[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo637[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo638[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo639[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo640[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo641[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo642[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo643[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo644[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo645[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo646[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo647[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo648[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo649[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo650[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo651[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo652[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo653[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo654[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo655[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo656[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo657[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo658[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo659[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo660[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo661[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo662[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo663[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo664[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo665[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo666[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo667[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo668[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo669[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo670[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo671[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo672[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo673[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo674[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo675[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo676[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo677[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo678[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo679[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo680[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo681[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo682[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo683[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo684[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo685[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo686[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo687[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo688[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo689[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo690[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo691[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo692[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo693[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo694[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo695[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo696[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo697[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo698[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo699[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo700[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo701[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo702[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo703[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo704[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo705[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo706[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo707[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo708[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo709[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo710[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo711[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo712[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo713[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo714[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo715[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo716[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo717[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo718[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo719[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo720[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo721[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo722[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo723[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo724[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo725[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo726[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo727[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo728[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo729[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo730[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo731[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo732[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo733[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo734[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo735[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo736[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo737[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo738[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo739[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo740[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo741[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo742[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo743[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo744[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo745[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo746[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo747[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo748[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo749[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo750[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo751[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo752[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo753[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo754[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo755[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo756[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo757[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo758[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo759[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo760[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo761[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo762[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo763[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo764[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo765[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo766[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo767[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo768[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo769[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo770[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo771[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo772[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo773[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo774[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo775[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo776[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo777[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo778[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo779[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo780[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo781[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo782[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo783[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo784[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo785[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo786[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo787[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo788[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo789[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo790[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo791[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo792[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo793[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo794[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo795[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo796[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo797[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo798[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo799[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo800[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo801[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo802[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo803[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo804[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo805[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo806[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo807[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo808[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo809[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo810[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo811[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo812[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo813[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo814[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo815[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo816[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo817[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo818[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo819[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo820[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo821[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo822[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo823[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo824[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo825[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo826[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo827[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo828[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo829[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo830[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo831[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo832[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo833[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo834[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo835[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo836[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo837[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo838[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo839[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo840[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo841[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo842[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo843[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo844[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo845[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo846[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo847[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo848[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo849[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo850[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo851[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo852[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo853[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo854[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo855[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo856[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo857[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo858[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo859[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo860[] = { + {RISCV_VRN2M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo861[] = { + {RISCV_VRN2M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo862[] = { + {RISCV_VRN2M4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo863[] = { + {RISCV_VRN3M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo864[] = { + {RISCV_VRN3M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo865[] = { + {RISCV_VRN4M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo866[] = { + {RISCV_VRN4M2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo867[] = { + {RISCV_VRN5M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo868[] = { + {RISCV_VRN6M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo869[] = { + {RISCV_VRN7M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo870[] = { + {RISCV_VRN8M1RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo871[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo872[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo873[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo874[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo875[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo876[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo877[] = { + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo878[] = { + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM2NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo879[] = { + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo880[] = { + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM4NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo881[] = { + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo882[] = { + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRM8NoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRM4RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo883[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo884[] = { + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRNoV0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo885[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo886[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo887[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo888[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo889[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo890[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo891[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo892[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo893[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo894[] = { + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo895[] = { + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo896[] = { + {RISCV_SPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_SPRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo897[] = { + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_SPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo898[] = { + {RISCV_GPRX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRX0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo899[] = { + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo900[] = { + {RISCV_GPRX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRX0RegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo901[] = { + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo902[] = { + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo903[] = { + {RISCV_FPR64CRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo904[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_SPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo905[] = { + {RISCV_FPR32CRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo906[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_SPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo907[] = { + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo908[] = { + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo909[] = { + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_SPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo910[] = { + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo911[] = { + {RISCV_GPRX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo912[] = { + {RISCV_GPRNoX0X2RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo913[] = { + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo914[] = { + {RISCV_GPRX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRNoX0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo915[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_SPRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo916[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo917[] = { + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRCRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo918[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo919[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo920[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo921[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo922[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo923[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo924[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo925[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo926[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo927[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo928[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo929[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo930[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo931[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo932[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo933[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo934[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo935[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo936[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo937[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo938[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo939[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo940[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo941[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo942[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo943[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo944[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo945[] = { + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR64RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo946[] = { + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR16RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo947[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo948[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo949[] = { + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo950[] = { + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo951[] = { + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo952[] = { + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo953[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo954[] = { + {RISCV_AnyRegRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo955[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo956[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo957[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo958[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo959[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo960[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo961[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo962[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo963[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo964[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo965[] = { + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo966[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo967[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo968[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo969[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo970[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo971[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_FPR32RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo972[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo973[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo974[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo975[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo976[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo977[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo978[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo979[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo980[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo981[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo982[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo983[] = { + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo984[] = { + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_EARLY_CLOBBER}, + {RISCV_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VRRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {RISCV_VMV0RegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; + +extern const MCInstrDesc RISCVInsts[] = { + {1, OperandInfo2}, // Inst #0 = PHI + {0, NULL}, // Inst #1 = INLINEASM + {0, NULL}, // Inst #2 = INLINEASM_BR + {1, OperandInfo3}, // Inst #3 = CFI_INSTRUCTION + {1, OperandInfo3}, // Inst #4 = EH_LABEL + {1, OperandInfo3}, // Inst #5 = GC_LABEL + {1, OperandInfo3}, // Inst #6 = ANNOTATION_LABEL + {0, NULL}, // Inst #7 = KILL + {3, OperandInfo4}, // Inst #8 = EXTRACT_SUBREG + {4, OperandInfo5}, // Inst #9 = INSERT_SUBREG + {1, OperandInfo2}, // Inst #10 = IMPLICIT_DEF + {4, OperandInfo6}, // Inst #11 = SUBREG_TO_REG + {3, OperandInfo4}, // Inst #12 = COPY_TO_REGCLASS + {0, NULL}, // Inst #13 = DBG_VALUE + {0, NULL}, // Inst #14 = DBG_VALUE_LIST + {0, NULL}, // Inst #15 = DBG_INSTR_REF + {0, NULL}, // Inst #16 = DBG_PHI + {1, OperandInfo2}, // Inst #17 = DBG_LABEL + {2, OperandInfo7}, // Inst #18 = REG_SEQUENCE + {2, OperandInfo7}, // Inst #19 = COPY + {0, NULL}, // Inst #20 = BUNDLE + {1, OperandInfo3}, // Inst #21 = LIFETIME_START + {1, OperandInfo3}, // Inst #22 = LIFETIME_END + {4, OperandInfo8}, // Inst #23 = PSEUDO_PROBE + {2, OperandInfo9}, // Inst #24 = ARITH_FENCE + {2, OperandInfo10}, // Inst #25 = STACKMAP + {0, NULL}, // Inst #26 = FENTRY_CALL + {6, OperandInfo11}, // Inst #27 = PATCHPOINT + {1, OperandInfo12}, // Inst #28 = LOAD_STACK_GUARD + {1, OperandInfo3}, // Inst #29 = PREALLOCATED_SETUP + {3, OperandInfo13}, // Inst #30 = PREALLOCATED_ARG + {0, NULL}, // Inst #31 = STATEPOINT + {2, OperandInfo14}, // Inst #32 = LOCAL_ESCAPE + {1, OperandInfo2}, // Inst #33 = FAULTING_OP + {0, NULL}, // Inst #34 = PATCHABLE_OP + {0, NULL}, // Inst #35 = PATCHABLE_FUNCTION_ENTER + {0, NULL}, // Inst #36 = PATCHABLE_RET + {0, NULL}, // Inst #37 = PATCHABLE_FUNCTION_EXIT + {0, NULL}, // Inst #38 = PATCHABLE_TAIL_CALL + {2, OperandInfo15}, // Inst #39 = PATCHABLE_EVENT_CALL + {3, OperandInfo16}, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + {0, NULL}, // Inst #41 = ICALL_BRANCH_FUNNEL + {3, OperandInfo17}, // Inst #42 = G_ASSERT_SEXT + {3, OperandInfo17}, // Inst #43 = G_ASSERT_ZEXT + {3, OperandInfo18}, // Inst #44 = G_ADD + {3, OperandInfo18}, // Inst #45 = G_SUB + {3, OperandInfo18}, // Inst #46 = G_MUL + {3, OperandInfo18}, // Inst #47 = G_SDIV + {3, OperandInfo18}, // Inst #48 = G_UDIV + {3, OperandInfo18}, // Inst #49 = G_SREM + {3, OperandInfo18}, // Inst #50 = G_UREM + {4, OperandInfo19}, // Inst #51 = G_SDIVREM + {4, OperandInfo19}, // Inst #52 = G_UDIVREM + {3, OperandInfo18}, // Inst #53 = G_AND + {3, OperandInfo18}, // Inst #54 = G_OR + {3, OperandInfo18}, // Inst #55 = G_XOR + {1, OperandInfo20}, // Inst #56 = G_IMPLICIT_DEF + {1, OperandInfo20}, // Inst #57 = G_PHI + {2, OperandInfo21}, // Inst #58 = G_FRAME_INDEX + {2, OperandInfo21}, // Inst #59 = G_GLOBAL_VALUE + {3, OperandInfo22}, // Inst #60 = G_EXTRACT + {2, OperandInfo23}, // Inst #61 = G_UNMERGE_VALUES + {4, OperandInfo24}, // Inst #62 = G_INSERT + {2, OperandInfo23}, // Inst #63 = G_MERGE_VALUES + {2, OperandInfo23}, // Inst #64 = G_BUILD_VECTOR + {2, OperandInfo23}, // Inst #65 = G_BUILD_VECTOR_TRUNC + {2, OperandInfo23}, // Inst #66 = G_CONCAT_VECTORS + {2, OperandInfo23}, // Inst #67 = G_PTRTOINT + {2, OperandInfo23}, // Inst #68 = G_INTTOPTR + {2, OperandInfo23}, // Inst #69 = G_BITCAST + {2, OperandInfo25}, // Inst #70 = G_FREEZE + {2, OperandInfo25}, // Inst #71 = G_INTRINSIC_TRUNC + {2, OperandInfo25}, // Inst #72 = G_INTRINSIC_ROUND + {2, OperandInfo23}, // Inst #73 = G_INTRINSIC_LRINT + {2, OperandInfo25}, // Inst #74 = G_INTRINSIC_ROUNDEVEN + {1, OperandInfo20}, // Inst #75 = G_READCYCLECOUNTER + {2, OperandInfo23}, // Inst #76 = G_LOAD + {2, OperandInfo23}, // Inst #77 = G_SEXTLOAD + {2, OperandInfo23}, // Inst #78 = G_ZEXTLOAD + {5, OperandInfo26}, // Inst #79 = G_INDEXED_LOAD + {5, OperandInfo26}, // Inst #80 = G_INDEXED_SEXTLOAD + {5, OperandInfo26}, // Inst #81 = G_INDEXED_ZEXTLOAD + {2, OperandInfo23}, // Inst #82 = G_STORE + {5, OperandInfo27}, // Inst #83 = G_INDEXED_STORE + {5, OperandInfo28}, // Inst #84 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + {4, OperandInfo29}, // Inst #85 = G_ATOMIC_CMPXCHG + {3, OperandInfo30}, // Inst #86 = G_ATOMICRMW_XCHG + {3, OperandInfo30}, // Inst #87 = G_ATOMICRMW_ADD + {3, OperandInfo30}, // Inst #88 = G_ATOMICRMW_SUB + {3, OperandInfo30}, // Inst #89 = G_ATOMICRMW_AND + {3, OperandInfo30}, // Inst #90 = G_ATOMICRMW_NAND + {3, OperandInfo30}, // Inst #91 = G_ATOMICRMW_OR + {3, OperandInfo30}, // Inst #92 = G_ATOMICRMW_XOR + {3, OperandInfo30}, // Inst #93 = G_ATOMICRMW_MAX + {3, OperandInfo30}, // Inst #94 = G_ATOMICRMW_MIN + {3, OperandInfo30}, // Inst #95 = G_ATOMICRMW_UMAX + {3, OperandInfo30}, // Inst #96 = G_ATOMICRMW_UMIN + {3, OperandInfo30}, // Inst #97 = G_ATOMICRMW_FADD + {3, OperandInfo30}, // Inst #98 = G_ATOMICRMW_FSUB + {2, OperandInfo10}, // Inst #99 = G_FENCE + {2, OperandInfo21}, // Inst #100 = G_BRCOND + {1, OperandInfo20}, // Inst #101 = G_BRINDIRECT + {1, OperandInfo2}, // Inst #102 = G_INTRINSIC + {1, OperandInfo2}, // Inst #103 = G_INTRINSIC_W_SIDE_EFFECTS + {2, OperandInfo23}, // Inst #104 = G_ANYEXT + {2, OperandInfo23}, // Inst #105 = G_TRUNC + {2, OperandInfo21}, // Inst #106 = G_CONSTANT + {2, OperandInfo21}, // Inst #107 = G_FCONSTANT + {1, OperandInfo20}, // Inst #108 = G_VASTART + {3, OperandInfo31}, // Inst #109 = G_VAARG + {2, OperandInfo23}, // Inst #110 = G_SEXT + {3, OperandInfo17}, // Inst #111 = G_SEXT_INREG + {2, OperandInfo23}, // Inst #112 = G_ZEXT + {3, OperandInfo32}, // Inst #113 = G_SHL + {3, OperandInfo32}, // Inst #114 = G_LSHR + {3, OperandInfo32}, // Inst #115 = G_ASHR + {4, OperandInfo33}, // Inst #116 = G_FSHL + {4, OperandInfo33}, // Inst #117 = G_FSHR + {3, OperandInfo32}, // Inst #118 = G_ROTR + {3, OperandInfo32}, // Inst #119 = G_ROTL + {4, OperandInfo34}, // Inst #120 = G_ICMP + {4, OperandInfo34}, // Inst #121 = G_FCMP + {4, OperandInfo29}, // Inst #122 = G_SELECT + {4, OperandInfo29}, // Inst #123 = G_UADDO + {5, OperandInfo35}, // Inst #124 = G_UADDE + {4, OperandInfo29}, // Inst #125 = G_USUBO + {5, OperandInfo35}, // Inst #126 = G_USUBE + {4, OperandInfo29}, // Inst #127 = G_SADDO + {5, OperandInfo35}, // Inst #128 = G_SADDE + {4, OperandInfo29}, // Inst #129 = G_SSUBO + {5, OperandInfo35}, // Inst #130 = G_SSUBE + {4, OperandInfo29}, // Inst #131 = G_UMULO + {4, OperandInfo29}, // Inst #132 = G_SMULO + {3, OperandInfo18}, // Inst #133 = G_UMULH + {3, OperandInfo18}, // Inst #134 = G_SMULH + {3, OperandInfo18}, // Inst #135 = G_UADDSAT + {3, OperandInfo18}, // Inst #136 = G_SADDSAT + {3, OperandInfo18}, // Inst #137 = G_USUBSAT + {3, OperandInfo18}, // Inst #138 = G_SSUBSAT + {3, OperandInfo32}, // Inst #139 = G_USHLSAT + {3, OperandInfo32}, // Inst #140 = G_SSHLSAT + {4, OperandInfo36}, // Inst #141 = G_SMULFIX + {4, OperandInfo36}, // Inst #142 = G_UMULFIX + {4, OperandInfo36}, // Inst #143 = G_SMULFIXSAT + {4, OperandInfo36}, // Inst #144 = G_UMULFIXSAT + {4, OperandInfo36}, // Inst #145 = G_SDIVFIX + {4, OperandInfo36}, // Inst #146 = G_UDIVFIX + {4, OperandInfo36}, // Inst #147 = G_SDIVFIXSAT + {4, OperandInfo36}, // Inst #148 = G_UDIVFIXSAT + {3, OperandInfo18}, // Inst #149 = G_FADD + {3, OperandInfo18}, // Inst #150 = G_FSUB + {3, OperandInfo18}, // Inst #151 = G_FMUL + {4, OperandInfo19}, // Inst #152 = G_FMA + {4, OperandInfo19}, // Inst #153 = G_FMAD + {3, OperandInfo18}, // Inst #154 = G_FDIV + {3, OperandInfo18}, // Inst #155 = G_FREM + {3, OperandInfo18}, // Inst #156 = G_FPOW + {3, OperandInfo32}, // Inst #157 = G_FPOWI + {2, OperandInfo25}, // Inst #158 = G_FEXP + {2, OperandInfo25}, // Inst #159 = G_FEXP2 + {2, OperandInfo25}, // Inst #160 = G_FLOG + {2, OperandInfo25}, // Inst #161 = G_FLOG2 + {2, OperandInfo25}, // Inst #162 = G_FLOG10 + {2, OperandInfo25}, // Inst #163 = G_FNEG + {2, OperandInfo23}, // Inst #164 = G_FPEXT + {2, OperandInfo23}, // Inst #165 = G_FPTRUNC + {2, OperandInfo23}, // Inst #166 = G_FPTOSI + {2, OperandInfo23}, // Inst #167 = G_FPTOUI + {2, OperandInfo23}, // Inst #168 = G_SITOFP + {2, OperandInfo23}, // Inst #169 = G_UITOFP + {2, OperandInfo25}, // Inst #170 = G_FABS + {3, OperandInfo32}, // Inst #171 = G_FCOPYSIGN + {2, OperandInfo25}, // Inst #172 = G_FCANONICALIZE + {3, OperandInfo18}, // Inst #173 = G_FMINNUM + {3, OperandInfo18}, // Inst #174 = G_FMAXNUM + {3, OperandInfo18}, // Inst #175 = G_FMINNUM_IEEE + {3, OperandInfo18}, // Inst #176 = G_FMAXNUM_IEEE + {3, OperandInfo18}, // Inst #177 = G_FMINIMUM + {3, OperandInfo18}, // Inst #178 = G_FMAXIMUM + {3, OperandInfo32}, // Inst #179 = G_PTR_ADD + {3, OperandInfo32}, // Inst #180 = G_PTRMASK + {3, OperandInfo18}, // Inst #181 = G_SMIN + {3, OperandInfo18}, // Inst #182 = G_SMAX + {3, OperandInfo18}, // Inst #183 = G_UMIN + {3, OperandInfo18}, // Inst #184 = G_UMAX + {2, OperandInfo25}, // Inst #185 = G_ABS + {2, OperandInfo23}, // Inst #186 = G_LROUND + {2, OperandInfo23}, // Inst #187 = G_LLROUND + {1, OperandInfo2}, // Inst #188 = G_BR + {3, OperandInfo37}, // Inst #189 = G_BRJT + {4, OperandInfo38}, // Inst #190 = G_INSERT_VECTOR_ELT + {3, OperandInfo39}, // Inst #191 = G_EXTRACT_VECTOR_ELT + {4, OperandInfo40}, // Inst #192 = G_SHUFFLE_VECTOR + {2, OperandInfo23}, // Inst #193 = G_CTTZ + {2, OperandInfo23}, // Inst #194 = G_CTTZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #195 = G_CTLZ + {2, OperandInfo23}, // Inst #196 = G_CTLZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #197 = G_CTPOP + {2, OperandInfo25}, // Inst #198 = G_BSWAP + {2, OperandInfo25}, // Inst #199 = G_BITREVERSE + {2, OperandInfo25}, // Inst #200 = G_FCEIL + {2, OperandInfo25}, // Inst #201 = G_FCOS + {2, OperandInfo25}, // Inst #202 = G_FSIN + {2, OperandInfo25}, // Inst #203 = G_FSQRT + {2, OperandInfo25}, // Inst #204 = G_FFLOOR + {2, OperandInfo25}, // Inst #205 = G_FRINT + {2, OperandInfo25}, // Inst #206 = G_FNEARBYINT + {2, OperandInfo23}, // Inst #207 = G_ADDRSPACE_CAST + {2, OperandInfo21}, // Inst #208 = G_BLOCK_ADDR + {2, OperandInfo21}, // Inst #209 = G_JUMP_TABLE + {3, OperandInfo22}, // Inst #210 = G_DYN_STACKALLOC + {3, OperandInfo18}, // Inst #211 = G_STRICT_FADD + {3, OperandInfo18}, // Inst #212 = G_STRICT_FSUB + {3, OperandInfo18}, // Inst #213 = G_STRICT_FMUL + {3, OperandInfo18}, // Inst #214 = G_STRICT_FDIV + {3, OperandInfo18}, // Inst #215 = G_STRICT_FREM + {4, OperandInfo19}, // Inst #216 = G_STRICT_FMA + {2, OperandInfo25}, // Inst #217 = G_STRICT_FSQRT + {2, OperandInfo21}, // Inst #218 = G_READ_REGISTER + {2, OperandInfo41}, // Inst #219 = G_WRITE_REGISTER + {4, OperandInfo42}, // Inst #220 = G_MEMCPY + {3, OperandInfo39}, // Inst #221 = G_MEMCPY_INLINE + {4, OperandInfo42}, // Inst #222 = G_MEMMOVE + {4, OperandInfo42}, // Inst #223 = G_MEMSET + {3, OperandInfo22}, // Inst #224 = G_BZERO + {3, OperandInfo39}, // Inst #225 = G_VECREDUCE_SEQ_FADD + {3, OperandInfo39}, // Inst #226 = G_VECREDUCE_SEQ_FMUL + {2, OperandInfo23}, // Inst #227 = G_VECREDUCE_FADD + {2, OperandInfo23}, // Inst #228 = G_VECREDUCE_FMUL + {2, OperandInfo23}, // Inst #229 = G_VECREDUCE_FMAX + {2, OperandInfo23}, // Inst #230 = G_VECREDUCE_FMIN + {2, OperandInfo23}, // Inst #231 = G_VECREDUCE_ADD + {2, OperandInfo23}, // Inst #232 = G_VECREDUCE_MUL + {2, OperandInfo23}, // Inst #233 = G_VECREDUCE_AND + {2, OperandInfo23}, // Inst #234 = G_VECREDUCE_OR + {2, OperandInfo23}, // Inst #235 = G_VECREDUCE_XOR + {2, OperandInfo23}, // Inst #236 = G_VECREDUCE_SMAX + {2, OperandInfo23}, // Inst #237 = G_VECREDUCE_SMIN + {2, OperandInfo23}, // Inst #238 = G_VECREDUCE_UMAX + {2, OperandInfo23}, // Inst #239 = G_VECREDUCE_UMIN + {4, OperandInfo43}, // Inst #240 = G_SBFX + {4, OperandInfo43}, // Inst #241 = G_UBFX + {2, OperandInfo10}, // Inst #242 = ADJCALLSTACKDOWN + {2, OperandInfo10}, // Inst #243 = ADJCALLSTACKUP + {3, OperandInfo44}, // Inst #244 = BuildPairF64Pseudo + {4, OperandInfo45}, // Inst #245 = PseudoAddTPRel + {5, OperandInfo46}, // Inst #246 = PseudoAtomicLoadNand32 + {5, OperandInfo46}, // Inst #247 = PseudoAtomicLoadNand64 + {1, OperandInfo47}, // Inst #248 = PseudoBR + {2, OperandInfo48}, // Inst #249 = PseudoBRIND + {1, OperandInfo2}, // Inst #250 = PseudoCALL + {1, OperandInfo49}, // Inst #251 = PseudoCALLIndirect + {2, OperandInfo50}, // Inst #252 = PseudoCALLReg + {6, OperandInfo51}, // Inst #253 = PseudoCmpXchg32 + {6, OperandInfo51}, // Inst #254 = PseudoCmpXchg64 + {3, OperandInfo52}, // Inst #255 = PseudoFLD + {3, OperandInfo53}, // Inst #256 = PseudoFLH + {3, OperandInfo54}, // Inst #257 = PseudoFLW + {3, OperandInfo52}, // Inst #258 = PseudoFSD + {3, OperandInfo53}, // Inst #259 = PseudoFSH + {3, OperandInfo54}, // Inst #260 = PseudoFSW + {2, OperandInfo50}, // Inst #261 = PseudoJump + {2, OperandInfo50}, // Inst #262 = PseudoLA + {2, OperandInfo50}, // Inst #263 = PseudoLA_TLS_GD + {2, OperandInfo50}, // Inst #264 = PseudoLA_TLS_IE + {2, OperandInfo50}, // Inst #265 = PseudoLB + {2, OperandInfo50}, // Inst #266 = PseudoLBU + {2, OperandInfo50}, // Inst #267 = PseudoLD + {2, OperandInfo50}, // Inst #268 = PseudoLH + {2, OperandInfo50}, // Inst #269 = PseudoLHU + {2, OperandInfo50}, // Inst #270 = PseudoLI + {2, OperandInfo50}, // Inst #271 = PseudoLLA + {2, OperandInfo50}, // Inst #272 = PseudoLW + {2, OperandInfo50}, // Inst #273 = PseudoLWU + {6, OperandInfo51}, // Inst #274 = PseudoMaskedAtomicLoadAdd32 + {8, OperandInfo55}, // Inst #275 = PseudoMaskedAtomicLoadMax32 + {8, OperandInfo55}, // Inst #276 = PseudoMaskedAtomicLoadMin32 + {6, OperandInfo51}, // Inst #277 = PseudoMaskedAtomicLoadNand32 + {6, OperandInfo51}, // Inst #278 = PseudoMaskedAtomicLoadSub32 + {7, OperandInfo56}, // Inst #279 = PseudoMaskedAtomicLoadUMax32 + {7, OperandInfo56}, // Inst #280 = PseudoMaskedAtomicLoadUMin32 + {6, OperandInfo51}, // Inst #281 = PseudoMaskedAtomicSwap32 + {7, OperandInfo57}, // Inst #282 = PseudoMaskedCmpXchg32 + {0, NULL}, // Inst #283 = PseudoRET + {1, OperandInfo58}, // Inst #284 = PseudoReadVL + {1, OperandInfo58}, // Inst #285 = PseudoReadVLENB + {3, OperandInfo59}, // Inst #286 = PseudoSB + {3, OperandInfo59}, // Inst #287 = PseudoSD + {2, OperandInfo60}, // Inst #288 = PseudoSEXT_B + {2, OperandInfo60}, // Inst #289 = PseudoSEXT_H + {3, OperandInfo59}, // Inst #290 = PseudoSH + {3, OperandInfo59}, // Inst #291 = PseudoSW + {1, OperandInfo2}, // Inst #292 = PseudoTAIL + {1, OperandInfo61}, // Inst #293 = PseudoTAILIndirect + {5, OperandInfo62}, // Inst #294 = PseudoVAADDU_VV_M1 + {8, OperandInfo63}, // Inst #295 = PseudoVAADDU_VV_M1_MASK + {5, OperandInfo64}, // Inst #296 = PseudoVAADDU_VV_M2 + {8, OperandInfo65}, // Inst #297 = PseudoVAADDU_VV_M2_MASK + {5, OperandInfo66}, // Inst #298 = PseudoVAADDU_VV_M4 + {8, OperandInfo67}, // Inst #299 = PseudoVAADDU_VV_M4_MASK + {5, OperandInfo68}, // Inst #300 = PseudoVAADDU_VV_M8 + {8, OperandInfo69}, // Inst #301 = PseudoVAADDU_VV_M8_MASK + {5, OperandInfo62}, // Inst #302 = PseudoVAADDU_VV_MF2 + {8, OperandInfo63}, // Inst #303 = PseudoVAADDU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #304 = PseudoVAADDU_VV_MF4 + {8, OperandInfo63}, // Inst #305 = PseudoVAADDU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #306 = PseudoVAADDU_VV_MF8 + {8, OperandInfo63}, // Inst #307 = PseudoVAADDU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #308 = PseudoVAADDU_VX_M1 + {8, OperandInfo71}, // Inst #309 = PseudoVAADDU_VX_M1_MASK + {5, OperandInfo72}, // Inst #310 = PseudoVAADDU_VX_M2 + {8, OperandInfo73}, // Inst #311 = PseudoVAADDU_VX_M2_MASK + {5, OperandInfo74}, // Inst #312 = PseudoVAADDU_VX_M4 + {8, OperandInfo75}, // Inst #313 = PseudoVAADDU_VX_M4_MASK + {5, OperandInfo76}, // Inst #314 = PseudoVAADDU_VX_M8 + {8, OperandInfo77}, // Inst #315 = PseudoVAADDU_VX_M8_MASK + {5, OperandInfo70}, // Inst #316 = PseudoVAADDU_VX_MF2 + {8, OperandInfo71}, // Inst #317 = PseudoVAADDU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #318 = PseudoVAADDU_VX_MF4 + {8, OperandInfo71}, // Inst #319 = PseudoVAADDU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #320 = PseudoVAADDU_VX_MF8 + {8, OperandInfo71}, // Inst #321 = PseudoVAADDU_VX_MF8_MASK + {5, OperandInfo62}, // Inst #322 = PseudoVAADD_VV_M1 + {8, OperandInfo63}, // Inst #323 = PseudoVAADD_VV_M1_MASK + {5, OperandInfo64}, // Inst #324 = PseudoVAADD_VV_M2 + {8, OperandInfo65}, // Inst #325 = PseudoVAADD_VV_M2_MASK + {5, OperandInfo66}, // Inst #326 = PseudoVAADD_VV_M4 + {8, OperandInfo67}, // Inst #327 = PseudoVAADD_VV_M4_MASK + {5, OperandInfo68}, // Inst #328 = PseudoVAADD_VV_M8 + {8, OperandInfo69}, // Inst #329 = PseudoVAADD_VV_M8_MASK + {5, OperandInfo62}, // Inst #330 = PseudoVAADD_VV_MF2 + {8, OperandInfo63}, // Inst #331 = PseudoVAADD_VV_MF2_MASK + {5, OperandInfo62}, // Inst #332 = PseudoVAADD_VV_MF4 + {8, OperandInfo63}, // Inst #333 = PseudoVAADD_VV_MF4_MASK + {5, OperandInfo62}, // Inst #334 = PseudoVAADD_VV_MF8 + {8, OperandInfo63}, // Inst #335 = PseudoVAADD_VV_MF8_MASK + {5, OperandInfo70}, // Inst #336 = PseudoVAADD_VX_M1 + {8, OperandInfo71}, // Inst #337 = PseudoVAADD_VX_M1_MASK + {5, OperandInfo72}, // Inst #338 = PseudoVAADD_VX_M2 + {8, OperandInfo73}, // Inst #339 = PseudoVAADD_VX_M2_MASK + {5, OperandInfo74}, // Inst #340 = PseudoVAADD_VX_M4 + {8, OperandInfo75}, // Inst #341 = PseudoVAADD_VX_M4_MASK + {5, OperandInfo76}, // Inst #342 = PseudoVAADD_VX_M8 + {8, OperandInfo77}, // Inst #343 = PseudoVAADD_VX_M8_MASK + {5, OperandInfo70}, // Inst #344 = PseudoVAADD_VX_MF2 + {8, OperandInfo71}, // Inst #345 = PseudoVAADD_VX_MF2_MASK + {5, OperandInfo70}, // Inst #346 = PseudoVAADD_VX_MF4 + {8, OperandInfo71}, // Inst #347 = PseudoVAADD_VX_MF4_MASK + {5, OperandInfo70}, // Inst #348 = PseudoVAADD_VX_MF8 + {8, OperandInfo71}, // Inst #349 = PseudoVAADD_VX_MF8_MASK + {6, OperandInfo78}, // Inst #350 = PseudoVADC_VIM_M1 + {6, OperandInfo79}, // Inst #351 = PseudoVADC_VIM_M2 + {6, OperandInfo80}, // Inst #352 = PseudoVADC_VIM_M4 + {6, OperandInfo81}, // Inst #353 = PseudoVADC_VIM_M8 + {6, OperandInfo78}, // Inst #354 = PseudoVADC_VIM_MF2 + {6, OperandInfo78}, // Inst #355 = PseudoVADC_VIM_MF4 + {6, OperandInfo78}, // Inst #356 = PseudoVADC_VIM_MF8 + {6, OperandInfo82}, // Inst #357 = PseudoVADC_VVM_M1 + {6, OperandInfo83}, // Inst #358 = PseudoVADC_VVM_M2 + {6, OperandInfo84}, // Inst #359 = PseudoVADC_VVM_M4 + {6, OperandInfo85}, // Inst #360 = PseudoVADC_VVM_M8 + {6, OperandInfo82}, // Inst #361 = PseudoVADC_VVM_MF2 + {6, OperandInfo82}, // Inst #362 = PseudoVADC_VVM_MF4 + {6, OperandInfo82}, // Inst #363 = PseudoVADC_VVM_MF8 + {6, OperandInfo86}, // Inst #364 = PseudoVADC_VXM_M1 + {6, OperandInfo87}, // Inst #365 = PseudoVADC_VXM_M2 + {6, OperandInfo88}, // Inst #366 = PseudoVADC_VXM_M4 + {6, OperandInfo89}, // Inst #367 = PseudoVADC_VXM_M8 + {6, OperandInfo86}, // Inst #368 = PseudoVADC_VXM_MF2 + {6, OperandInfo86}, // Inst #369 = PseudoVADC_VXM_MF4 + {6, OperandInfo86}, // Inst #370 = PseudoVADC_VXM_MF8 + {5, OperandInfo90}, // Inst #371 = PseudoVADD_VI_M1 + {8, OperandInfo91}, // Inst #372 = PseudoVADD_VI_M1_MASK + {5, OperandInfo92}, // Inst #373 = PseudoVADD_VI_M2 + {8, OperandInfo93}, // Inst #374 = PseudoVADD_VI_M2_MASK + {5, OperandInfo94}, // Inst #375 = PseudoVADD_VI_M4 + {8, OperandInfo95}, // Inst #376 = PseudoVADD_VI_M4_MASK + {5, OperandInfo96}, // Inst #377 = PseudoVADD_VI_M8 + {8, OperandInfo97}, // Inst #378 = PseudoVADD_VI_M8_MASK + {5, OperandInfo90}, // Inst #379 = PseudoVADD_VI_MF2 + {8, OperandInfo91}, // Inst #380 = PseudoVADD_VI_MF2_MASK + {5, OperandInfo90}, // Inst #381 = PseudoVADD_VI_MF4 + {8, OperandInfo91}, // Inst #382 = PseudoVADD_VI_MF4_MASK + {5, OperandInfo90}, // Inst #383 = PseudoVADD_VI_MF8 + {8, OperandInfo91}, // Inst #384 = PseudoVADD_VI_MF8_MASK + {5, OperandInfo62}, // Inst #385 = PseudoVADD_VV_M1 + {8, OperandInfo63}, // Inst #386 = PseudoVADD_VV_M1_MASK + {5, OperandInfo64}, // Inst #387 = PseudoVADD_VV_M2 + {8, OperandInfo65}, // Inst #388 = PseudoVADD_VV_M2_MASK + {5, OperandInfo66}, // Inst #389 = PseudoVADD_VV_M4 + {8, OperandInfo67}, // Inst #390 = PseudoVADD_VV_M4_MASK + {5, OperandInfo68}, // Inst #391 = PseudoVADD_VV_M8 + {8, OperandInfo69}, // Inst #392 = PseudoVADD_VV_M8_MASK + {5, OperandInfo62}, // Inst #393 = PseudoVADD_VV_MF2 + {8, OperandInfo63}, // Inst #394 = PseudoVADD_VV_MF2_MASK + {5, OperandInfo62}, // Inst #395 = PseudoVADD_VV_MF4 + {8, OperandInfo63}, // Inst #396 = PseudoVADD_VV_MF4_MASK + {5, OperandInfo62}, // Inst #397 = PseudoVADD_VV_MF8 + {8, OperandInfo63}, // Inst #398 = PseudoVADD_VV_MF8_MASK + {5, OperandInfo70}, // Inst #399 = PseudoVADD_VX_M1 + {8, OperandInfo71}, // Inst #400 = PseudoVADD_VX_M1_MASK + {5, OperandInfo72}, // Inst #401 = PseudoVADD_VX_M2 + {8, OperandInfo73}, // Inst #402 = PseudoVADD_VX_M2_MASK + {5, OperandInfo74}, // Inst #403 = PseudoVADD_VX_M4 + {8, OperandInfo75}, // Inst #404 = PseudoVADD_VX_M4_MASK + {5, OperandInfo76}, // Inst #405 = PseudoVADD_VX_M8 + {8, OperandInfo77}, // Inst #406 = PseudoVADD_VX_M8_MASK + {5, OperandInfo70}, // Inst #407 = PseudoVADD_VX_MF2 + {8, OperandInfo71}, // Inst #408 = PseudoVADD_VX_MF2_MASK + {5, OperandInfo70}, // Inst #409 = PseudoVADD_VX_MF4 + {8, OperandInfo71}, // Inst #410 = PseudoVADD_VX_MF4_MASK + {5, OperandInfo70}, // Inst #411 = PseudoVADD_VX_MF8 + {8, OperandInfo71}, // Inst #412 = PseudoVADD_VX_MF8_MASK + {6, OperandInfo98}, // Inst #413 = PseudoVAMOADDEI16_WD_M1_MF2 + {7, OperandInfo99}, // Inst #414 = PseudoVAMOADDEI16_WD_M1_MF2_MASK + {6, OperandInfo98}, // Inst #415 = PseudoVAMOADDEI16_WD_M1_MF4 + {7, OperandInfo99}, // Inst #416 = PseudoVAMOADDEI16_WD_M1_MF4_MASK + {6, OperandInfo100}, // Inst #417 = PseudoVAMOADDEI16_WD_M2_M1 + {7, OperandInfo101}, // Inst #418 = PseudoVAMOADDEI16_WD_M2_M1_MASK + {6, OperandInfo100}, // Inst #419 = PseudoVAMOADDEI16_WD_M2_MF2 + {7, OperandInfo101}, // Inst #420 = PseudoVAMOADDEI16_WD_M2_MF2_MASK + {6, OperandInfo102}, // Inst #421 = PseudoVAMOADDEI16_WD_M4_M1 + {7, OperandInfo103}, // Inst #422 = PseudoVAMOADDEI16_WD_M4_M1_MASK + {6, OperandInfo104}, // Inst #423 = PseudoVAMOADDEI16_WD_M4_M2 + {7, OperandInfo105}, // Inst #424 = PseudoVAMOADDEI16_WD_M4_M2_MASK + {6, OperandInfo106}, // Inst #425 = PseudoVAMOADDEI16_WD_M8_M2 + {7, OperandInfo107}, // Inst #426 = PseudoVAMOADDEI16_WD_M8_M2_MASK + {6, OperandInfo108}, // Inst #427 = PseudoVAMOADDEI16_WD_M8_M4 + {7, OperandInfo109}, // Inst #428 = PseudoVAMOADDEI16_WD_M8_M4_MASK + {6, OperandInfo98}, // Inst #429 = PseudoVAMOADDEI16_WD_MF2_MF4 + {7, OperandInfo99}, // Inst #430 = PseudoVAMOADDEI16_WD_MF2_MF4_MASK + {6, OperandInfo98}, // Inst #431 = PseudoVAMOADDEI32_WD_M1_M1 + {7, OperandInfo99}, // Inst #432 = PseudoVAMOADDEI32_WD_M1_M1_MASK + {6, OperandInfo98}, // Inst #433 = PseudoVAMOADDEI32_WD_M1_MF2 + {7, OperandInfo99}, // Inst #434 = PseudoVAMOADDEI32_WD_M1_MF2_MASK + {6, OperandInfo100}, // Inst #435 = PseudoVAMOADDEI32_WD_M2_M1 + {7, OperandInfo101}, // Inst #436 = PseudoVAMOADDEI32_WD_M2_M1_MASK + {6, OperandInfo110}, // Inst #437 = PseudoVAMOADDEI32_WD_M2_M2 + {7, OperandInfo111}, // Inst #438 = PseudoVAMOADDEI32_WD_M2_M2_MASK + {6, OperandInfo104}, // Inst #439 = PseudoVAMOADDEI32_WD_M4_M2 + {7, OperandInfo105}, // Inst #440 = PseudoVAMOADDEI32_WD_M4_M2_MASK + {6, OperandInfo112}, // Inst #441 = PseudoVAMOADDEI32_WD_M4_M4 + {7, OperandInfo113}, // Inst #442 = PseudoVAMOADDEI32_WD_M4_M4_MASK + {6, OperandInfo108}, // Inst #443 = PseudoVAMOADDEI32_WD_M8_M4 + {7, OperandInfo109}, // Inst #444 = PseudoVAMOADDEI32_WD_M8_M4_MASK + {6, OperandInfo114}, // Inst #445 = PseudoVAMOADDEI32_WD_M8_M8 + {7, OperandInfo115}, // Inst #446 = PseudoVAMOADDEI32_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #447 = PseudoVAMOADDEI32_WD_MF2_MF2 + {7, OperandInfo99}, // Inst #448 = PseudoVAMOADDEI32_WD_MF2_MF2_MASK + {6, OperandInfo98}, // Inst #449 = PseudoVAMOADDEI64_WD_M1_M1 + {7, OperandInfo99}, // Inst #450 = PseudoVAMOADDEI64_WD_M1_M1_MASK + {6, OperandInfo116}, // Inst #451 = PseudoVAMOADDEI64_WD_M1_M2 + {7, OperandInfo117}, // Inst #452 = PseudoVAMOADDEI64_WD_M1_M2_MASK + {6, OperandInfo110}, // Inst #453 = PseudoVAMOADDEI64_WD_M2_M2 + {7, OperandInfo111}, // Inst #454 = PseudoVAMOADDEI64_WD_M2_M2_MASK + {6, OperandInfo118}, // Inst #455 = PseudoVAMOADDEI64_WD_M2_M4 + {7, OperandInfo119}, // Inst #456 = PseudoVAMOADDEI64_WD_M2_M4_MASK + {6, OperandInfo112}, // Inst #457 = PseudoVAMOADDEI64_WD_M4_M4 + {7, OperandInfo113}, // Inst #458 = PseudoVAMOADDEI64_WD_M4_M4_MASK + {6, OperandInfo120}, // Inst #459 = PseudoVAMOADDEI64_WD_M4_M8 + {7, OperandInfo121}, // Inst #460 = PseudoVAMOADDEI64_WD_M4_M8_MASK + {6, OperandInfo114}, // Inst #461 = PseudoVAMOADDEI64_WD_M8_M8 + {7, OperandInfo115}, // Inst #462 = PseudoVAMOADDEI64_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #463 = PseudoVAMOADDEI64_WD_MF2_M1 + {7, OperandInfo99}, // Inst #464 = PseudoVAMOADDEI64_WD_MF2_M1_MASK + {6, OperandInfo98}, // Inst #465 = PseudoVAMOADDEI8_WD_M1_MF4 + {7, OperandInfo99}, // Inst #466 = PseudoVAMOADDEI8_WD_M1_MF4_MASK + {6, OperandInfo98}, // Inst #467 = PseudoVAMOADDEI8_WD_M1_MF8 + {7, OperandInfo99}, // Inst #468 = PseudoVAMOADDEI8_WD_M1_MF8_MASK + {6, OperandInfo100}, // Inst #469 = PseudoVAMOADDEI8_WD_M2_MF2 + {7, OperandInfo101}, // Inst #470 = PseudoVAMOADDEI8_WD_M2_MF2_MASK + {6, OperandInfo100}, // Inst #471 = PseudoVAMOADDEI8_WD_M2_MF4 + {7, OperandInfo101}, // Inst #472 = PseudoVAMOADDEI8_WD_M2_MF4_MASK + {6, OperandInfo102}, // Inst #473 = PseudoVAMOADDEI8_WD_M4_M1 + {7, OperandInfo103}, // Inst #474 = PseudoVAMOADDEI8_WD_M4_M1_MASK + {6, OperandInfo102}, // Inst #475 = PseudoVAMOADDEI8_WD_M4_MF2 + {7, OperandInfo103}, // Inst #476 = PseudoVAMOADDEI8_WD_M4_MF2_MASK + {6, OperandInfo122}, // Inst #477 = PseudoVAMOADDEI8_WD_M8_M1 + {7, OperandInfo123}, // Inst #478 = PseudoVAMOADDEI8_WD_M8_M1_MASK + {6, OperandInfo106}, // Inst #479 = PseudoVAMOADDEI8_WD_M8_M2 + {7, OperandInfo107}, // Inst #480 = PseudoVAMOADDEI8_WD_M8_M2_MASK + {6, OperandInfo98}, // Inst #481 = PseudoVAMOADDEI8_WD_MF2_MF8 + {7, OperandInfo99}, // Inst #482 = PseudoVAMOADDEI8_WD_MF2_MF8_MASK + {6, OperandInfo98}, // Inst #483 = PseudoVAMOANDEI16_WD_M1_MF2 + {7, OperandInfo99}, // Inst #484 = PseudoVAMOANDEI16_WD_M1_MF2_MASK + {6, OperandInfo98}, // Inst #485 = PseudoVAMOANDEI16_WD_M1_MF4 + {7, OperandInfo99}, // Inst #486 = PseudoVAMOANDEI16_WD_M1_MF4_MASK + {6, OperandInfo100}, // Inst #487 = PseudoVAMOANDEI16_WD_M2_M1 + {7, OperandInfo101}, // Inst #488 = PseudoVAMOANDEI16_WD_M2_M1_MASK + {6, OperandInfo100}, // Inst #489 = PseudoVAMOANDEI16_WD_M2_MF2 + {7, OperandInfo101}, // Inst #490 = PseudoVAMOANDEI16_WD_M2_MF2_MASK + {6, OperandInfo102}, // Inst #491 = PseudoVAMOANDEI16_WD_M4_M1 + {7, OperandInfo103}, // Inst #492 = PseudoVAMOANDEI16_WD_M4_M1_MASK + {6, OperandInfo104}, // Inst #493 = PseudoVAMOANDEI16_WD_M4_M2 + {7, OperandInfo105}, // Inst #494 = PseudoVAMOANDEI16_WD_M4_M2_MASK + {6, OperandInfo106}, // Inst #495 = PseudoVAMOANDEI16_WD_M8_M2 + {7, OperandInfo107}, // Inst #496 = PseudoVAMOANDEI16_WD_M8_M2_MASK + {6, OperandInfo108}, // Inst #497 = PseudoVAMOANDEI16_WD_M8_M4 + {7, OperandInfo109}, // Inst #498 = PseudoVAMOANDEI16_WD_M8_M4_MASK + {6, OperandInfo98}, // Inst #499 = PseudoVAMOANDEI16_WD_MF2_MF4 + {7, OperandInfo99}, // Inst #500 = PseudoVAMOANDEI16_WD_MF2_MF4_MASK + {6, OperandInfo98}, // Inst #501 = PseudoVAMOANDEI32_WD_M1_M1 + {7, OperandInfo99}, // Inst #502 = PseudoVAMOANDEI32_WD_M1_M1_MASK + {6, OperandInfo98}, // Inst #503 = PseudoVAMOANDEI32_WD_M1_MF2 + {7, OperandInfo99}, // Inst #504 = PseudoVAMOANDEI32_WD_M1_MF2_MASK + {6, OperandInfo100}, // Inst #505 = PseudoVAMOANDEI32_WD_M2_M1 + {7, OperandInfo101}, // Inst #506 = PseudoVAMOANDEI32_WD_M2_M1_MASK + {6, OperandInfo110}, // Inst #507 = PseudoVAMOANDEI32_WD_M2_M2 + {7, OperandInfo111}, // Inst #508 = PseudoVAMOANDEI32_WD_M2_M2_MASK + {6, OperandInfo104}, // Inst #509 = PseudoVAMOANDEI32_WD_M4_M2 + {7, OperandInfo105}, // Inst #510 = PseudoVAMOANDEI32_WD_M4_M2_MASK + {6, OperandInfo112}, // Inst #511 = PseudoVAMOANDEI32_WD_M4_M4 + {7, OperandInfo113}, // Inst #512 = PseudoVAMOANDEI32_WD_M4_M4_MASK + {6, OperandInfo108}, // Inst #513 = PseudoVAMOANDEI32_WD_M8_M4 + {7, OperandInfo109}, // Inst #514 = PseudoVAMOANDEI32_WD_M8_M4_MASK + {6, OperandInfo114}, // Inst #515 = PseudoVAMOANDEI32_WD_M8_M8 + {7, OperandInfo115}, // Inst #516 = PseudoVAMOANDEI32_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #517 = PseudoVAMOANDEI32_WD_MF2_MF2 + {7, OperandInfo99}, // Inst #518 = PseudoVAMOANDEI32_WD_MF2_MF2_MASK + {6, OperandInfo98}, // Inst #519 = PseudoVAMOANDEI64_WD_M1_M1 + {7, OperandInfo99}, // Inst #520 = PseudoVAMOANDEI64_WD_M1_M1_MASK + {6, OperandInfo116}, // Inst #521 = PseudoVAMOANDEI64_WD_M1_M2 + {7, OperandInfo117}, // Inst #522 = PseudoVAMOANDEI64_WD_M1_M2_MASK + {6, OperandInfo110}, // Inst #523 = PseudoVAMOANDEI64_WD_M2_M2 + {7, OperandInfo111}, // Inst #524 = PseudoVAMOANDEI64_WD_M2_M2_MASK + {6, OperandInfo118}, // Inst #525 = PseudoVAMOANDEI64_WD_M2_M4 + {7, OperandInfo119}, // Inst #526 = PseudoVAMOANDEI64_WD_M2_M4_MASK + {6, OperandInfo112}, // Inst #527 = PseudoVAMOANDEI64_WD_M4_M4 + {7, OperandInfo113}, // Inst #528 = PseudoVAMOANDEI64_WD_M4_M4_MASK + {6, OperandInfo120}, // Inst #529 = PseudoVAMOANDEI64_WD_M4_M8 + {7, OperandInfo121}, // Inst #530 = PseudoVAMOANDEI64_WD_M4_M8_MASK + {6, OperandInfo114}, // Inst #531 = PseudoVAMOANDEI64_WD_M8_M8 + {7, OperandInfo115}, // Inst #532 = PseudoVAMOANDEI64_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #533 = PseudoVAMOANDEI64_WD_MF2_M1 + {7, OperandInfo99}, // Inst #534 = PseudoVAMOANDEI64_WD_MF2_M1_MASK + {6, OperandInfo98}, // Inst #535 = PseudoVAMOANDEI8_WD_M1_MF4 + {7, OperandInfo99}, // Inst #536 = PseudoVAMOANDEI8_WD_M1_MF4_MASK + {6, OperandInfo98}, // Inst #537 = PseudoVAMOANDEI8_WD_M1_MF8 + {7, OperandInfo99}, // Inst #538 = PseudoVAMOANDEI8_WD_M1_MF8_MASK + {6, OperandInfo100}, // Inst #539 = PseudoVAMOANDEI8_WD_M2_MF2 + {7, OperandInfo101}, // Inst #540 = PseudoVAMOANDEI8_WD_M2_MF2_MASK + {6, OperandInfo100}, // Inst #541 = PseudoVAMOANDEI8_WD_M2_MF4 + {7, OperandInfo101}, // Inst #542 = PseudoVAMOANDEI8_WD_M2_MF4_MASK + {6, OperandInfo102}, // Inst #543 = PseudoVAMOANDEI8_WD_M4_M1 + {7, OperandInfo103}, // Inst #544 = PseudoVAMOANDEI8_WD_M4_M1_MASK + {6, OperandInfo102}, // Inst #545 = PseudoVAMOANDEI8_WD_M4_MF2 + {7, OperandInfo103}, // Inst #546 = PseudoVAMOANDEI8_WD_M4_MF2_MASK + {6, OperandInfo122}, // Inst #547 = PseudoVAMOANDEI8_WD_M8_M1 + {7, OperandInfo123}, // Inst #548 = PseudoVAMOANDEI8_WD_M8_M1_MASK + {6, OperandInfo106}, // Inst #549 = PseudoVAMOANDEI8_WD_M8_M2 + {7, OperandInfo107}, // Inst #550 = PseudoVAMOANDEI8_WD_M8_M2_MASK + {6, OperandInfo98}, // Inst #551 = PseudoVAMOANDEI8_WD_MF2_MF8 + {7, OperandInfo99}, // Inst #552 = PseudoVAMOANDEI8_WD_MF2_MF8_MASK + {6, OperandInfo98}, // Inst #553 = PseudoVAMOMAXEI16_WD_M1_MF2 + {7, OperandInfo99}, // Inst #554 = PseudoVAMOMAXEI16_WD_M1_MF2_MASK + {6, OperandInfo98}, // Inst #555 = PseudoVAMOMAXEI16_WD_M1_MF4 + {7, OperandInfo99}, // Inst #556 = PseudoVAMOMAXEI16_WD_M1_MF4_MASK + {6, OperandInfo100}, // Inst #557 = PseudoVAMOMAXEI16_WD_M2_M1 + {7, OperandInfo101}, // Inst #558 = PseudoVAMOMAXEI16_WD_M2_M1_MASK + {6, OperandInfo100}, // Inst #559 = PseudoVAMOMAXEI16_WD_M2_MF2 + {7, OperandInfo101}, // Inst #560 = PseudoVAMOMAXEI16_WD_M2_MF2_MASK + {6, OperandInfo102}, // Inst #561 = PseudoVAMOMAXEI16_WD_M4_M1 + {7, OperandInfo103}, // Inst #562 = PseudoVAMOMAXEI16_WD_M4_M1_MASK + {6, OperandInfo104}, // Inst #563 = PseudoVAMOMAXEI16_WD_M4_M2 + {7, OperandInfo105}, // Inst #564 = PseudoVAMOMAXEI16_WD_M4_M2_MASK + {6, OperandInfo106}, // Inst #565 = PseudoVAMOMAXEI16_WD_M8_M2 + {7, OperandInfo107}, // Inst #566 = PseudoVAMOMAXEI16_WD_M8_M2_MASK + {6, OperandInfo108}, // Inst #567 = PseudoVAMOMAXEI16_WD_M8_M4 + {7, OperandInfo109}, // Inst #568 = PseudoVAMOMAXEI16_WD_M8_M4_MASK + {6, OperandInfo98}, // Inst #569 = PseudoVAMOMAXEI16_WD_MF2_MF4 + {7, OperandInfo99}, // Inst #570 = PseudoVAMOMAXEI16_WD_MF2_MF4_MASK + {6, OperandInfo98}, // Inst #571 = PseudoVAMOMAXEI32_WD_M1_M1 + {7, OperandInfo99}, // Inst #572 = PseudoVAMOMAXEI32_WD_M1_M1_MASK + {6, OperandInfo98}, // Inst #573 = PseudoVAMOMAXEI32_WD_M1_MF2 + {7, OperandInfo99}, // Inst #574 = PseudoVAMOMAXEI32_WD_M1_MF2_MASK + {6, OperandInfo100}, // Inst #575 = PseudoVAMOMAXEI32_WD_M2_M1 + {7, OperandInfo101}, // Inst #576 = PseudoVAMOMAXEI32_WD_M2_M1_MASK + {6, OperandInfo110}, // Inst #577 = PseudoVAMOMAXEI32_WD_M2_M2 + {7, OperandInfo111}, // Inst #578 = PseudoVAMOMAXEI32_WD_M2_M2_MASK + {6, OperandInfo104}, // Inst #579 = PseudoVAMOMAXEI32_WD_M4_M2 + {7, OperandInfo105}, // Inst #580 = PseudoVAMOMAXEI32_WD_M4_M2_MASK + {6, OperandInfo112}, // Inst #581 = PseudoVAMOMAXEI32_WD_M4_M4 + {7, OperandInfo113}, // Inst #582 = PseudoVAMOMAXEI32_WD_M4_M4_MASK + {6, OperandInfo108}, // Inst #583 = PseudoVAMOMAXEI32_WD_M8_M4 + {7, OperandInfo109}, // Inst #584 = PseudoVAMOMAXEI32_WD_M8_M4_MASK + {6, OperandInfo114}, // Inst #585 = PseudoVAMOMAXEI32_WD_M8_M8 + {7, OperandInfo115}, // Inst #586 = PseudoVAMOMAXEI32_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #587 = PseudoVAMOMAXEI32_WD_MF2_MF2 + {7, OperandInfo99}, // Inst #588 = PseudoVAMOMAXEI32_WD_MF2_MF2_MASK + {6, OperandInfo98}, // Inst #589 = PseudoVAMOMAXEI64_WD_M1_M1 + {7, OperandInfo99}, // Inst #590 = PseudoVAMOMAXEI64_WD_M1_M1_MASK + {6, OperandInfo116}, // Inst #591 = PseudoVAMOMAXEI64_WD_M1_M2 + {7, OperandInfo117}, // Inst #592 = PseudoVAMOMAXEI64_WD_M1_M2_MASK + {6, OperandInfo110}, // Inst #593 = PseudoVAMOMAXEI64_WD_M2_M2 + {7, OperandInfo111}, // Inst #594 = PseudoVAMOMAXEI64_WD_M2_M2_MASK + {6, OperandInfo118}, // Inst #595 = PseudoVAMOMAXEI64_WD_M2_M4 + {7, OperandInfo119}, // Inst #596 = PseudoVAMOMAXEI64_WD_M2_M4_MASK + {6, OperandInfo112}, // Inst #597 = PseudoVAMOMAXEI64_WD_M4_M4 + {7, OperandInfo113}, // Inst #598 = PseudoVAMOMAXEI64_WD_M4_M4_MASK + {6, OperandInfo120}, // Inst #599 = PseudoVAMOMAXEI64_WD_M4_M8 + {7, OperandInfo121}, // Inst #600 = PseudoVAMOMAXEI64_WD_M4_M8_MASK + {6, OperandInfo114}, // Inst #601 = PseudoVAMOMAXEI64_WD_M8_M8 + {7, OperandInfo115}, // Inst #602 = PseudoVAMOMAXEI64_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #603 = PseudoVAMOMAXEI64_WD_MF2_M1 + {7, OperandInfo99}, // Inst #604 = PseudoVAMOMAXEI64_WD_MF2_M1_MASK + {6, OperandInfo98}, // Inst #605 = PseudoVAMOMAXEI8_WD_M1_MF4 + {7, OperandInfo99}, // Inst #606 = PseudoVAMOMAXEI8_WD_M1_MF4_MASK + {6, OperandInfo98}, // Inst #607 = PseudoVAMOMAXEI8_WD_M1_MF8 + {7, OperandInfo99}, // Inst #608 = PseudoVAMOMAXEI8_WD_M1_MF8_MASK + {6, OperandInfo100}, // Inst #609 = PseudoVAMOMAXEI8_WD_M2_MF2 + {7, OperandInfo101}, // Inst #610 = PseudoVAMOMAXEI8_WD_M2_MF2_MASK + {6, OperandInfo100}, // Inst #611 = PseudoVAMOMAXEI8_WD_M2_MF4 + {7, OperandInfo101}, // Inst #612 = PseudoVAMOMAXEI8_WD_M2_MF4_MASK + {6, OperandInfo102}, // Inst #613 = PseudoVAMOMAXEI8_WD_M4_M1 + {7, OperandInfo103}, // Inst #614 = PseudoVAMOMAXEI8_WD_M4_M1_MASK + {6, OperandInfo102}, // Inst #615 = PseudoVAMOMAXEI8_WD_M4_MF2 + {7, OperandInfo103}, // Inst #616 = PseudoVAMOMAXEI8_WD_M4_MF2_MASK + {6, OperandInfo122}, // Inst #617 = PseudoVAMOMAXEI8_WD_M8_M1 + {7, OperandInfo123}, // Inst #618 = PseudoVAMOMAXEI8_WD_M8_M1_MASK + {6, OperandInfo106}, // Inst #619 = PseudoVAMOMAXEI8_WD_M8_M2 + {7, OperandInfo107}, // Inst #620 = PseudoVAMOMAXEI8_WD_M8_M2_MASK + {6, OperandInfo98}, // Inst #621 = PseudoVAMOMAXEI8_WD_MF2_MF8 + {7, OperandInfo99}, // Inst #622 = PseudoVAMOMAXEI8_WD_MF2_MF8_MASK + {6, OperandInfo98}, // Inst #623 = PseudoVAMOMAXUEI16_WD_M1_MF2 + {7, OperandInfo99}, // Inst #624 = PseudoVAMOMAXUEI16_WD_M1_MF2_MASK + {6, OperandInfo98}, // Inst #625 = PseudoVAMOMAXUEI16_WD_M1_MF4 + {7, OperandInfo99}, // Inst #626 = PseudoVAMOMAXUEI16_WD_M1_MF4_MASK + {6, OperandInfo100}, // Inst #627 = PseudoVAMOMAXUEI16_WD_M2_M1 + {7, OperandInfo101}, // Inst #628 = PseudoVAMOMAXUEI16_WD_M2_M1_MASK + {6, OperandInfo100}, // Inst #629 = PseudoVAMOMAXUEI16_WD_M2_MF2 + {7, OperandInfo101}, // Inst #630 = PseudoVAMOMAXUEI16_WD_M2_MF2_MASK + {6, OperandInfo102}, // Inst #631 = PseudoVAMOMAXUEI16_WD_M4_M1 + {7, OperandInfo103}, // Inst #632 = PseudoVAMOMAXUEI16_WD_M4_M1_MASK + {6, OperandInfo104}, // Inst #633 = PseudoVAMOMAXUEI16_WD_M4_M2 + {7, OperandInfo105}, // Inst #634 = PseudoVAMOMAXUEI16_WD_M4_M2_MASK + {6, OperandInfo106}, // Inst #635 = PseudoVAMOMAXUEI16_WD_M8_M2 + {7, OperandInfo107}, // Inst #636 = PseudoVAMOMAXUEI16_WD_M8_M2_MASK + {6, OperandInfo108}, // Inst #637 = PseudoVAMOMAXUEI16_WD_M8_M4 + {7, OperandInfo109}, // Inst #638 = PseudoVAMOMAXUEI16_WD_M8_M4_MASK + {6, OperandInfo98}, // Inst #639 = PseudoVAMOMAXUEI16_WD_MF2_MF4 + {7, OperandInfo99}, // Inst #640 = PseudoVAMOMAXUEI16_WD_MF2_MF4_MASK + {6, OperandInfo98}, // Inst #641 = PseudoVAMOMAXUEI32_WD_M1_M1 + {7, OperandInfo99}, // Inst #642 = PseudoVAMOMAXUEI32_WD_M1_M1_MASK + {6, OperandInfo98}, // Inst #643 = PseudoVAMOMAXUEI32_WD_M1_MF2 + {7, OperandInfo99}, // Inst #644 = PseudoVAMOMAXUEI32_WD_M1_MF2_MASK + {6, OperandInfo100}, // Inst #645 = PseudoVAMOMAXUEI32_WD_M2_M1 + {7, OperandInfo101}, // Inst #646 = PseudoVAMOMAXUEI32_WD_M2_M1_MASK + {6, OperandInfo110}, // Inst #647 = PseudoVAMOMAXUEI32_WD_M2_M2 + {7, OperandInfo111}, // Inst #648 = PseudoVAMOMAXUEI32_WD_M2_M2_MASK + {6, OperandInfo104}, // Inst #649 = PseudoVAMOMAXUEI32_WD_M4_M2 + {7, OperandInfo105}, // Inst #650 = PseudoVAMOMAXUEI32_WD_M4_M2_MASK + {6, OperandInfo112}, // Inst #651 = PseudoVAMOMAXUEI32_WD_M4_M4 + {7, OperandInfo113}, // Inst #652 = PseudoVAMOMAXUEI32_WD_M4_M4_MASK + {6, OperandInfo108}, // Inst #653 = PseudoVAMOMAXUEI32_WD_M8_M4 + {7, OperandInfo109}, // Inst #654 = PseudoVAMOMAXUEI32_WD_M8_M4_MASK + {6, OperandInfo114}, // Inst #655 = PseudoVAMOMAXUEI32_WD_M8_M8 + {7, OperandInfo115}, // Inst #656 = PseudoVAMOMAXUEI32_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #657 = PseudoVAMOMAXUEI32_WD_MF2_MF2 + {7, OperandInfo99}, // Inst #658 = PseudoVAMOMAXUEI32_WD_MF2_MF2_MASK + {6, OperandInfo98}, // Inst #659 = PseudoVAMOMAXUEI64_WD_M1_M1 + {7, OperandInfo99}, // Inst #660 = PseudoVAMOMAXUEI64_WD_M1_M1_MASK + {6, OperandInfo116}, // Inst #661 = PseudoVAMOMAXUEI64_WD_M1_M2 + {7, OperandInfo117}, // Inst #662 = PseudoVAMOMAXUEI64_WD_M1_M2_MASK + {6, OperandInfo110}, // Inst #663 = PseudoVAMOMAXUEI64_WD_M2_M2 + {7, OperandInfo111}, // Inst #664 = PseudoVAMOMAXUEI64_WD_M2_M2_MASK + {6, OperandInfo118}, // Inst #665 = PseudoVAMOMAXUEI64_WD_M2_M4 + {7, OperandInfo119}, // Inst #666 = PseudoVAMOMAXUEI64_WD_M2_M4_MASK + {6, OperandInfo112}, // Inst #667 = PseudoVAMOMAXUEI64_WD_M4_M4 + {7, OperandInfo113}, // Inst #668 = PseudoVAMOMAXUEI64_WD_M4_M4_MASK + {6, OperandInfo120}, // Inst #669 = PseudoVAMOMAXUEI64_WD_M4_M8 + {7, OperandInfo121}, // Inst #670 = PseudoVAMOMAXUEI64_WD_M4_M8_MASK + {6, OperandInfo114}, // Inst #671 = PseudoVAMOMAXUEI64_WD_M8_M8 + {7, OperandInfo115}, // Inst #672 = PseudoVAMOMAXUEI64_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #673 = PseudoVAMOMAXUEI64_WD_MF2_M1 + {7, OperandInfo99}, // Inst #674 = PseudoVAMOMAXUEI64_WD_MF2_M1_MASK + {6, OperandInfo98}, // Inst #675 = PseudoVAMOMAXUEI8_WD_M1_MF4 + {7, OperandInfo99}, // Inst #676 = PseudoVAMOMAXUEI8_WD_M1_MF4_MASK + {6, OperandInfo98}, // Inst #677 = PseudoVAMOMAXUEI8_WD_M1_MF8 + {7, OperandInfo99}, // Inst #678 = PseudoVAMOMAXUEI8_WD_M1_MF8_MASK + {6, OperandInfo100}, // Inst #679 = PseudoVAMOMAXUEI8_WD_M2_MF2 + {7, OperandInfo101}, // Inst #680 = PseudoVAMOMAXUEI8_WD_M2_MF2_MASK + {6, OperandInfo100}, // Inst #681 = PseudoVAMOMAXUEI8_WD_M2_MF4 + {7, OperandInfo101}, // Inst #682 = PseudoVAMOMAXUEI8_WD_M2_MF4_MASK + {6, OperandInfo102}, // Inst #683 = PseudoVAMOMAXUEI8_WD_M4_M1 + {7, OperandInfo103}, // Inst #684 = PseudoVAMOMAXUEI8_WD_M4_M1_MASK + {6, OperandInfo102}, // Inst #685 = PseudoVAMOMAXUEI8_WD_M4_MF2 + {7, OperandInfo103}, // Inst #686 = PseudoVAMOMAXUEI8_WD_M4_MF2_MASK + {6, OperandInfo122}, // Inst #687 = PseudoVAMOMAXUEI8_WD_M8_M1 + {7, OperandInfo123}, // Inst #688 = PseudoVAMOMAXUEI8_WD_M8_M1_MASK + {6, OperandInfo106}, // Inst #689 = PseudoVAMOMAXUEI8_WD_M8_M2 + {7, OperandInfo107}, // Inst #690 = PseudoVAMOMAXUEI8_WD_M8_M2_MASK + {6, OperandInfo98}, // Inst #691 = PseudoVAMOMAXUEI8_WD_MF2_MF8 + {7, OperandInfo99}, // Inst #692 = PseudoVAMOMAXUEI8_WD_MF2_MF8_MASK + {6, OperandInfo98}, // Inst #693 = PseudoVAMOMINEI16_WD_M1_MF2 + {7, OperandInfo99}, // Inst #694 = PseudoVAMOMINEI16_WD_M1_MF2_MASK + {6, OperandInfo98}, // Inst #695 = PseudoVAMOMINEI16_WD_M1_MF4 + {7, OperandInfo99}, // Inst #696 = PseudoVAMOMINEI16_WD_M1_MF4_MASK + {6, OperandInfo100}, // Inst #697 = PseudoVAMOMINEI16_WD_M2_M1 + {7, OperandInfo101}, // Inst #698 = PseudoVAMOMINEI16_WD_M2_M1_MASK + {6, OperandInfo100}, // Inst #699 = PseudoVAMOMINEI16_WD_M2_MF2 + {7, OperandInfo101}, // Inst #700 = PseudoVAMOMINEI16_WD_M2_MF2_MASK + {6, OperandInfo102}, // Inst #701 = PseudoVAMOMINEI16_WD_M4_M1 + {7, OperandInfo103}, // Inst #702 = PseudoVAMOMINEI16_WD_M4_M1_MASK + {6, OperandInfo104}, // Inst #703 = PseudoVAMOMINEI16_WD_M4_M2 + {7, OperandInfo105}, // Inst #704 = PseudoVAMOMINEI16_WD_M4_M2_MASK + {6, OperandInfo106}, // Inst #705 = PseudoVAMOMINEI16_WD_M8_M2 + {7, OperandInfo107}, // Inst #706 = PseudoVAMOMINEI16_WD_M8_M2_MASK + {6, OperandInfo108}, // Inst #707 = PseudoVAMOMINEI16_WD_M8_M4 + {7, OperandInfo109}, // Inst #708 = PseudoVAMOMINEI16_WD_M8_M4_MASK + {6, OperandInfo98}, // Inst #709 = PseudoVAMOMINEI16_WD_MF2_MF4 + {7, OperandInfo99}, // Inst #710 = PseudoVAMOMINEI16_WD_MF2_MF4_MASK + {6, OperandInfo98}, // Inst #711 = PseudoVAMOMINEI32_WD_M1_M1 + {7, OperandInfo99}, // Inst #712 = PseudoVAMOMINEI32_WD_M1_M1_MASK + {6, OperandInfo98}, // Inst #713 = PseudoVAMOMINEI32_WD_M1_MF2 + {7, OperandInfo99}, // Inst #714 = PseudoVAMOMINEI32_WD_M1_MF2_MASK + {6, OperandInfo100}, // Inst #715 = PseudoVAMOMINEI32_WD_M2_M1 + {7, OperandInfo101}, // Inst #716 = PseudoVAMOMINEI32_WD_M2_M1_MASK + {6, OperandInfo110}, // Inst #717 = PseudoVAMOMINEI32_WD_M2_M2 + {7, OperandInfo111}, // Inst #718 = PseudoVAMOMINEI32_WD_M2_M2_MASK + {6, OperandInfo104}, // Inst #719 = PseudoVAMOMINEI32_WD_M4_M2 + {7, OperandInfo105}, // Inst #720 = PseudoVAMOMINEI32_WD_M4_M2_MASK + {6, OperandInfo112}, // Inst #721 = PseudoVAMOMINEI32_WD_M4_M4 + {7, OperandInfo113}, // Inst #722 = PseudoVAMOMINEI32_WD_M4_M4_MASK + {6, OperandInfo108}, // Inst #723 = PseudoVAMOMINEI32_WD_M8_M4 + {7, OperandInfo109}, // Inst #724 = PseudoVAMOMINEI32_WD_M8_M4_MASK + {6, OperandInfo114}, // Inst #725 = PseudoVAMOMINEI32_WD_M8_M8 + {7, OperandInfo115}, // Inst #726 = PseudoVAMOMINEI32_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #727 = PseudoVAMOMINEI32_WD_MF2_MF2 + {7, OperandInfo99}, // Inst #728 = PseudoVAMOMINEI32_WD_MF2_MF2_MASK + {6, OperandInfo98}, // Inst #729 = PseudoVAMOMINEI64_WD_M1_M1 + {7, OperandInfo99}, // Inst #730 = PseudoVAMOMINEI64_WD_M1_M1_MASK + {6, OperandInfo116}, // Inst #731 = PseudoVAMOMINEI64_WD_M1_M2 + {7, OperandInfo117}, // Inst #732 = PseudoVAMOMINEI64_WD_M1_M2_MASK + {6, OperandInfo110}, // Inst #733 = PseudoVAMOMINEI64_WD_M2_M2 + {7, OperandInfo111}, // Inst #734 = PseudoVAMOMINEI64_WD_M2_M2_MASK + {6, OperandInfo118}, // Inst #735 = PseudoVAMOMINEI64_WD_M2_M4 + {7, OperandInfo119}, // Inst #736 = PseudoVAMOMINEI64_WD_M2_M4_MASK + {6, OperandInfo112}, // Inst #737 = PseudoVAMOMINEI64_WD_M4_M4 + {7, OperandInfo113}, // Inst #738 = PseudoVAMOMINEI64_WD_M4_M4_MASK + {6, OperandInfo120}, // Inst #739 = PseudoVAMOMINEI64_WD_M4_M8 + {7, OperandInfo121}, // Inst #740 = PseudoVAMOMINEI64_WD_M4_M8_MASK + {6, OperandInfo114}, // Inst #741 = PseudoVAMOMINEI64_WD_M8_M8 + {7, OperandInfo115}, // Inst #742 = PseudoVAMOMINEI64_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #743 = PseudoVAMOMINEI64_WD_MF2_M1 + {7, OperandInfo99}, // Inst #744 = PseudoVAMOMINEI64_WD_MF2_M1_MASK + {6, OperandInfo98}, // Inst #745 = PseudoVAMOMINEI8_WD_M1_MF4 + {7, OperandInfo99}, // Inst #746 = PseudoVAMOMINEI8_WD_M1_MF4_MASK + {6, OperandInfo98}, // Inst #747 = PseudoVAMOMINEI8_WD_M1_MF8 + {7, OperandInfo99}, // Inst #748 = PseudoVAMOMINEI8_WD_M1_MF8_MASK + {6, OperandInfo100}, // Inst #749 = PseudoVAMOMINEI8_WD_M2_MF2 + {7, OperandInfo101}, // Inst #750 = PseudoVAMOMINEI8_WD_M2_MF2_MASK + {6, OperandInfo100}, // Inst #751 = PseudoVAMOMINEI8_WD_M2_MF4 + {7, OperandInfo101}, // Inst #752 = PseudoVAMOMINEI8_WD_M2_MF4_MASK + {6, OperandInfo102}, // Inst #753 = PseudoVAMOMINEI8_WD_M4_M1 + {7, OperandInfo103}, // Inst #754 = PseudoVAMOMINEI8_WD_M4_M1_MASK + {6, OperandInfo102}, // Inst #755 = PseudoVAMOMINEI8_WD_M4_MF2 + {7, OperandInfo103}, // Inst #756 = PseudoVAMOMINEI8_WD_M4_MF2_MASK + {6, OperandInfo122}, // Inst #757 = PseudoVAMOMINEI8_WD_M8_M1 + {7, OperandInfo123}, // Inst #758 = PseudoVAMOMINEI8_WD_M8_M1_MASK + {6, OperandInfo106}, // Inst #759 = PseudoVAMOMINEI8_WD_M8_M2 + {7, OperandInfo107}, // Inst #760 = PseudoVAMOMINEI8_WD_M8_M2_MASK + {6, OperandInfo98}, // Inst #761 = PseudoVAMOMINEI8_WD_MF2_MF8 + {7, OperandInfo99}, // Inst #762 = PseudoVAMOMINEI8_WD_MF2_MF8_MASK + {6, OperandInfo98}, // Inst #763 = PseudoVAMOMINUEI16_WD_M1_MF2 + {7, OperandInfo99}, // Inst #764 = PseudoVAMOMINUEI16_WD_M1_MF2_MASK + {6, OperandInfo98}, // Inst #765 = PseudoVAMOMINUEI16_WD_M1_MF4 + {7, OperandInfo99}, // Inst #766 = PseudoVAMOMINUEI16_WD_M1_MF4_MASK + {6, OperandInfo100}, // Inst #767 = PseudoVAMOMINUEI16_WD_M2_M1 + {7, OperandInfo101}, // Inst #768 = PseudoVAMOMINUEI16_WD_M2_M1_MASK + {6, OperandInfo100}, // Inst #769 = PseudoVAMOMINUEI16_WD_M2_MF2 + {7, OperandInfo101}, // Inst #770 = PseudoVAMOMINUEI16_WD_M2_MF2_MASK + {6, OperandInfo102}, // Inst #771 = PseudoVAMOMINUEI16_WD_M4_M1 + {7, OperandInfo103}, // Inst #772 = PseudoVAMOMINUEI16_WD_M4_M1_MASK + {6, OperandInfo104}, // Inst #773 = PseudoVAMOMINUEI16_WD_M4_M2 + {7, OperandInfo105}, // Inst #774 = PseudoVAMOMINUEI16_WD_M4_M2_MASK + {6, OperandInfo106}, // Inst #775 = PseudoVAMOMINUEI16_WD_M8_M2 + {7, OperandInfo107}, // Inst #776 = PseudoVAMOMINUEI16_WD_M8_M2_MASK + {6, OperandInfo108}, // Inst #777 = PseudoVAMOMINUEI16_WD_M8_M4 + {7, OperandInfo109}, // Inst #778 = PseudoVAMOMINUEI16_WD_M8_M4_MASK + {6, OperandInfo98}, // Inst #779 = PseudoVAMOMINUEI16_WD_MF2_MF4 + {7, OperandInfo99}, // Inst #780 = PseudoVAMOMINUEI16_WD_MF2_MF4_MASK + {6, OperandInfo98}, // Inst #781 = PseudoVAMOMINUEI32_WD_M1_M1 + {7, OperandInfo99}, // Inst #782 = PseudoVAMOMINUEI32_WD_M1_M1_MASK + {6, OperandInfo98}, // Inst #783 = PseudoVAMOMINUEI32_WD_M1_MF2 + {7, OperandInfo99}, // Inst #784 = PseudoVAMOMINUEI32_WD_M1_MF2_MASK + {6, OperandInfo100}, // Inst #785 = PseudoVAMOMINUEI32_WD_M2_M1 + {7, OperandInfo101}, // Inst #786 = PseudoVAMOMINUEI32_WD_M2_M1_MASK + {6, OperandInfo110}, // Inst #787 = PseudoVAMOMINUEI32_WD_M2_M2 + {7, OperandInfo111}, // Inst #788 = PseudoVAMOMINUEI32_WD_M2_M2_MASK + {6, OperandInfo104}, // Inst #789 = PseudoVAMOMINUEI32_WD_M4_M2 + {7, OperandInfo105}, // Inst #790 = PseudoVAMOMINUEI32_WD_M4_M2_MASK + {6, OperandInfo112}, // Inst #791 = PseudoVAMOMINUEI32_WD_M4_M4 + {7, OperandInfo113}, // Inst #792 = PseudoVAMOMINUEI32_WD_M4_M4_MASK + {6, OperandInfo108}, // Inst #793 = PseudoVAMOMINUEI32_WD_M8_M4 + {7, OperandInfo109}, // Inst #794 = PseudoVAMOMINUEI32_WD_M8_M4_MASK + {6, OperandInfo114}, // Inst #795 = PseudoVAMOMINUEI32_WD_M8_M8 + {7, OperandInfo115}, // Inst #796 = PseudoVAMOMINUEI32_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #797 = PseudoVAMOMINUEI32_WD_MF2_MF2 + {7, OperandInfo99}, // Inst #798 = PseudoVAMOMINUEI32_WD_MF2_MF2_MASK + {6, OperandInfo98}, // Inst #799 = PseudoVAMOMINUEI64_WD_M1_M1 + {7, OperandInfo99}, // Inst #800 = PseudoVAMOMINUEI64_WD_M1_M1_MASK + {6, OperandInfo116}, // Inst #801 = PseudoVAMOMINUEI64_WD_M1_M2 + {7, OperandInfo117}, // Inst #802 = PseudoVAMOMINUEI64_WD_M1_M2_MASK + {6, OperandInfo110}, // Inst #803 = PseudoVAMOMINUEI64_WD_M2_M2 + {7, OperandInfo111}, // Inst #804 = PseudoVAMOMINUEI64_WD_M2_M2_MASK + {6, OperandInfo118}, // Inst #805 = PseudoVAMOMINUEI64_WD_M2_M4 + {7, OperandInfo119}, // Inst #806 = PseudoVAMOMINUEI64_WD_M2_M4_MASK + {6, OperandInfo112}, // Inst #807 = PseudoVAMOMINUEI64_WD_M4_M4 + {7, OperandInfo113}, // Inst #808 = PseudoVAMOMINUEI64_WD_M4_M4_MASK + {6, OperandInfo120}, // Inst #809 = PseudoVAMOMINUEI64_WD_M4_M8 + {7, OperandInfo121}, // Inst #810 = PseudoVAMOMINUEI64_WD_M4_M8_MASK + {6, OperandInfo114}, // Inst #811 = PseudoVAMOMINUEI64_WD_M8_M8 + {7, OperandInfo115}, // Inst #812 = PseudoVAMOMINUEI64_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #813 = PseudoVAMOMINUEI64_WD_MF2_M1 + {7, OperandInfo99}, // Inst #814 = PseudoVAMOMINUEI64_WD_MF2_M1_MASK + {6, OperandInfo98}, // Inst #815 = PseudoVAMOMINUEI8_WD_M1_MF4 + {7, OperandInfo99}, // Inst #816 = PseudoVAMOMINUEI8_WD_M1_MF4_MASK + {6, OperandInfo98}, // Inst #817 = PseudoVAMOMINUEI8_WD_M1_MF8 + {7, OperandInfo99}, // Inst #818 = PseudoVAMOMINUEI8_WD_M1_MF8_MASK + {6, OperandInfo100}, // Inst #819 = PseudoVAMOMINUEI8_WD_M2_MF2 + {7, OperandInfo101}, // Inst #820 = PseudoVAMOMINUEI8_WD_M2_MF2_MASK + {6, OperandInfo100}, // Inst #821 = PseudoVAMOMINUEI8_WD_M2_MF4 + {7, OperandInfo101}, // Inst #822 = PseudoVAMOMINUEI8_WD_M2_MF4_MASK + {6, OperandInfo102}, // Inst #823 = PseudoVAMOMINUEI8_WD_M4_M1 + {7, OperandInfo103}, // Inst #824 = PseudoVAMOMINUEI8_WD_M4_M1_MASK + {6, OperandInfo102}, // Inst #825 = PseudoVAMOMINUEI8_WD_M4_MF2 + {7, OperandInfo103}, // Inst #826 = PseudoVAMOMINUEI8_WD_M4_MF2_MASK + {6, OperandInfo122}, // Inst #827 = PseudoVAMOMINUEI8_WD_M8_M1 + {7, OperandInfo123}, // Inst #828 = PseudoVAMOMINUEI8_WD_M8_M1_MASK + {6, OperandInfo106}, // Inst #829 = PseudoVAMOMINUEI8_WD_M8_M2 + {7, OperandInfo107}, // Inst #830 = PseudoVAMOMINUEI8_WD_M8_M2_MASK + {6, OperandInfo98}, // Inst #831 = PseudoVAMOMINUEI8_WD_MF2_MF8 + {7, OperandInfo99}, // Inst #832 = PseudoVAMOMINUEI8_WD_MF2_MF8_MASK + {6, OperandInfo98}, // Inst #833 = PseudoVAMOOREI16_WD_M1_MF2 + {7, OperandInfo99}, // Inst #834 = PseudoVAMOOREI16_WD_M1_MF2_MASK + {6, OperandInfo98}, // Inst #835 = PseudoVAMOOREI16_WD_M1_MF4 + {7, OperandInfo99}, // Inst #836 = PseudoVAMOOREI16_WD_M1_MF4_MASK + {6, OperandInfo100}, // Inst #837 = PseudoVAMOOREI16_WD_M2_M1 + {7, OperandInfo101}, // Inst #838 = PseudoVAMOOREI16_WD_M2_M1_MASK + {6, OperandInfo100}, // Inst #839 = PseudoVAMOOREI16_WD_M2_MF2 + {7, OperandInfo101}, // Inst #840 = PseudoVAMOOREI16_WD_M2_MF2_MASK + {6, OperandInfo102}, // Inst #841 = PseudoVAMOOREI16_WD_M4_M1 + {7, OperandInfo103}, // Inst #842 = PseudoVAMOOREI16_WD_M4_M1_MASK + {6, OperandInfo104}, // Inst #843 = PseudoVAMOOREI16_WD_M4_M2 + {7, OperandInfo105}, // Inst #844 = PseudoVAMOOREI16_WD_M4_M2_MASK + {6, OperandInfo106}, // Inst #845 = PseudoVAMOOREI16_WD_M8_M2 + {7, OperandInfo107}, // Inst #846 = PseudoVAMOOREI16_WD_M8_M2_MASK + {6, OperandInfo108}, // Inst #847 = PseudoVAMOOREI16_WD_M8_M4 + {7, OperandInfo109}, // Inst #848 = PseudoVAMOOREI16_WD_M8_M4_MASK + {6, OperandInfo98}, // Inst #849 = PseudoVAMOOREI16_WD_MF2_MF4 + {7, OperandInfo99}, // Inst #850 = PseudoVAMOOREI16_WD_MF2_MF4_MASK + {6, OperandInfo98}, // Inst #851 = PseudoVAMOOREI32_WD_M1_M1 + {7, OperandInfo99}, // Inst #852 = PseudoVAMOOREI32_WD_M1_M1_MASK + {6, OperandInfo98}, // Inst #853 = PseudoVAMOOREI32_WD_M1_MF2 + {7, OperandInfo99}, // Inst #854 = PseudoVAMOOREI32_WD_M1_MF2_MASK + {6, OperandInfo100}, // Inst #855 = PseudoVAMOOREI32_WD_M2_M1 + {7, OperandInfo101}, // Inst #856 = PseudoVAMOOREI32_WD_M2_M1_MASK + {6, OperandInfo110}, // Inst #857 = PseudoVAMOOREI32_WD_M2_M2 + {7, OperandInfo111}, // Inst #858 = PseudoVAMOOREI32_WD_M2_M2_MASK + {6, OperandInfo104}, // Inst #859 = PseudoVAMOOREI32_WD_M4_M2 + {7, OperandInfo105}, // Inst #860 = PseudoVAMOOREI32_WD_M4_M2_MASK + {6, OperandInfo112}, // Inst #861 = PseudoVAMOOREI32_WD_M4_M4 + {7, OperandInfo113}, // Inst #862 = PseudoVAMOOREI32_WD_M4_M4_MASK + {6, OperandInfo108}, // Inst #863 = PseudoVAMOOREI32_WD_M8_M4 + {7, OperandInfo109}, // Inst #864 = PseudoVAMOOREI32_WD_M8_M4_MASK + {6, OperandInfo114}, // Inst #865 = PseudoVAMOOREI32_WD_M8_M8 + {7, OperandInfo115}, // Inst #866 = PseudoVAMOOREI32_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #867 = PseudoVAMOOREI32_WD_MF2_MF2 + {7, OperandInfo99}, // Inst #868 = PseudoVAMOOREI32_WD_MF2_MF2_MASK + {6, OperandInfo98}, // Inst #869 = PseudoVAMOOREI64_WD_M1_M1 + {7, OperandInfo99}, // Inst #870 = PseudoVAMOOREI64_WD_M1_M1_MASK + {6, OperandInfo116}, // Inst #871 = PseudoVAMOOREI64_WD_M1_M2 + {7, OperandInfo117}, // Inst #872 = PseudoVAMOOREI64_WD_M1_M2_MASK + {6, OperandInfo110}, // Inst #873 = PseudoVAMOOREI64_WD_M2_M2 + {7, OperandInfo111}, // Inst #874 = PseudoVAMOOREI64_WD_M2_M2_MASK + {6, OperandInfo118}, // Inst #875 = PseudoVAMOOREI64_WD_M2_M4 + {7, OperandInfo119}, // Inst #876 = PseudoVAMOOREI64_WD_M2_M4_MASK + {6, OperandInfo112}, // Inst #877 = PseudoVAMOOREI64_WD_M4_M4 + {7, OperandInfo113}, // Inst #878 = PseudoVAMOOREI64_WD_M4_M4_MASK + {6, OperandInfo120}, // Inst #879 = PseudoVAMOOREI64_WD_M4_M8 + {7, OperandInfo121}, // Inst #880 = PseudoVAMOOREI64_WD_M4_M8_MASK + {6, OperandInfo114}, // Inst #881 = PseudoVAMOOREI64_WD_M8_M8 + {7, OperandInfo115}, // Inst #882 = PseudoVAMOOREI64_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #883 = PseudoVAMOOREI64_WD_MF2_M1 + {7, OperandInfo99}, // Inst #884 = PseudoVAMOOREI64_WD_MF2_M1_MASK + {6, OperandInfo98}, // Inst #885 = PseudoVAMOOREI8_WD_M1_MF4 + {7, OperandInfo99}, // Inst #886 = PseudoVAMOOREI8_WD_M1_MF4_MASK + {6, OperandInfo98}, // Inst #887 = PseudoVAMOOREI8_WD_M1_MF8 + {7, OperandInfo99}, // Inst #888 = PseudoVAMOOREI8_WD_M1_MF8_MASK + {6, OperandInfo100}, // Inst #889 = PseudoVAMOOREI8_WD_M2_MF2 + {7, OperandInfo101}, // Inst #890 = PseudoVAMOOREI8_WD_M2_MF2_MASK + {6, OperandInfo100}, // Inst #891 = PseudoVAMOOREI8_WD_M2_MF4 + {7, OperandInfo101}, // Inst #892 = PseudoVAMOOREI8_WD_M2_MF4_MASK + {6, OperandInfo102}, // Inst #893 = PseudoVAMOOREI8_WD_M4_M1 + {7, OperandInfo103}, // Inst #894 = PseudoVAMOOREI8_WD_M4_M1_MASK + {6, OperandInfo102}, // Inst #895 = PseudoVAMOOREI8_WD_M4_MF2 + {7, OperandInfo103}, // Inst #896 = PseudoVAMOOREI8_WD_M4_MF2_MASK + {6, OperandInfo122}, // Inst #897 = PseudoVAMOOREI8_WD_M8_M1 + {7, OperandInfo123}, // Inst #898 = PseudoVAMOOREI8_WD_M8_M1_MASK + {6, OperandInfo106}, // Inst #899 = PseudoVAMOOREI8_WD_M8_M2 + {7, OperandInfo107}, // Inst #900 = PseudoVAMOOREI8_WD_M8_M2_MASK + {6, OperandInfo98}, // Inst #901 = PseudoVAMOOREI8_WD_MF2_MF8 + {7, OperandInfo99}, // Inst #902 = PseudoVAMOOREI8_WD_MF2_MF8_MASK + {6, OperandInfo98}, // Inst #903 = PseudoVAMOSWAPEI16_WD_M1_MF2 + {7, OperandInfo99}, // Inst #904 = PseudoVAMOSWAPEI16_WD_M1_MF2_MASK + {6, OperandInfo98}, // Inst #905 = PseudoVAMOSWAPEI16_WD_M1_MF4 + {7, OperandInfo99}, // Inst #906 = PseudoVAMOSWAPEI16_WD_M1_MF4_MASK + {6, OperandInfo100}, // Inst #907 = PseudoVAMOSWAPEI16_WD_M2_M1 + {7, OperandInfo101}, // Inst #908 = PseudoVAMOSWAPEI16_WD_M2_M1_MASK + {6, OperandInfo100}, // Inst #909 = PseudoVAMOSWAPEI16_WD_M2_MF2 + {7, OperandInfo101}, // Inst #910 = PseudoVAMOSWAPEI16_WD_M2_MF2_MASK + {6, OperandInfo102}, // Inst #911 = PseudoVAMOSWAPEI16_WD_M4_M1 + {7, OperandInfo103}, // Inst #912 = PseudoVAMOSWAPEI16_WD_M4_M1_MASK + {6, OperandInfo104}, // Inst #913 = PseudoVAMOSWAPEI16_WD_M4_M2 + {7, OperandInfo105}, // Inst #914 = PseudoVAMOSWAPEI16_WD_M4_M2_MASK + {6, OperandInfo106}, // Inst #915 = PseudoVAMOSWAPEI16_WD_M8_M2 + {7, OperandInfo107}, // Inst #916 = PseudoVAMOSWAPEI16_WD_M8_M2_MASK + {6, OperandInfo108}, // Inst #917 = PseudoVAMOSWAPEI16_WD_M8_M4 + {7, OperandInfo109}, // Inst #918 = PseudoVAMOSWAPEI16_WD_M8_M4_MASK + {6, OperandInfo98}, // Inst #919 = PseudoVAMOSWAPEI16_WD_MF2_MF4 + {7, OperandInfo99}, // Inst #920 = PseudoVAMOSWAPEI16_WD_MF2_MF4_MASK + {6, OperandInfo98}, // Inst #921 = PseudoVAMOSWAPEI32_WD_M1_M1 + {7, OperandInfo99}, // Inst #922 = PseudoVAMOSWAPEI32_WD_M1_M1_MASK + {6, OperandInfo98}, // Inst #923 = PseudoVAMOSWAPEI32_WD_M1_MF2 + {7, OperandInfo99}, // Inst #924 = PseudoVAMOSWAPEI32_WD_M1_MF2_MASK + {6, OperandInfo100}, // Inst #925 = PseudoVAMOSWAPEI32_WD_M2_M1 + {7, OperandInfo101}, // Inst #926 = PseudoVAMOSWAPEI32_WD_M2_M1_MASK + {6, OperandInfo110}, // Inst #927 = PseudoVAMOSWAPEI32_WD_M2_M2 + {7, OperandInfo111}, // Inst #928 = PseudoVAMOSWAPEI32_WD_M2_M2_MASK + {6, OperandInfo104}, // Inst #929 = PseudoVAMOSWAPEI32_WD_M4_M2 + {7, OperandInfo105}, // Inst #930 = PseudoVAMOSWAPEI32_WD_M4_M2_MASK + {6, OperandInfo112}, // Inst #931 = PseudoVAMOSWAPEI32_WD_M4_M4 + {7, OperandInfo113}, // Inst #932 = PseudoVAMOSWAPEI32_WD_M4_M4_MASK + {6, OperandInfo108}, // Inst #933 = PseudoVAMOSWAPEI32_WD_M8_M4 + {7, OperandInfo109}, // Inst #934 = PseudoVAMOSWAPEI32_WD_M8_M4_MASK + {6, OperandInfo114}, // Inst #935 = PseudoVAMOSWAPEI32_WD_M8_M8 + {7, OperandInfo115}, // Inst #936 = PseudoVAMOSWAPEI32_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #937 = PseudoVAMOSWAPEI32_WD_MF2_MF2 + {7, OperandInfo99}, // Inst #938 = PseudoVAMOSWAPEI32_WD_MF2_MF2_MASK + {6, OperandInfo98}, // Inst #939 = PseudoVAMOSWAPEI64_WD_M1_M1 + {7, OperandInfo99}, // Inst #940 = PseudoVAMOSWAPEI64_WD_M1_M1_MASK + {6, OperandInfo116}, // Inst #941 = PseudoVAMOSWAPEI64_WD_M1_M2 + {7, OperandInfo117}, // Inst #942 = PseudoVAMOSWAPEI64_WD_M1_M2_MASK + {6, OperandInfo110}, // Inst #943 = PseudoVAMOSWAPEI64_WD_M2_M2 + {7, OperandInfo111}, // Inst #944 = PseudoVAMOSWAPEI64_WD_M2_M2_MASK + {6, OperandInfo118}, // Inst #945 = PseudoVAMOSWAPEI64_WD_M2_M4 + {7, OperandInfo119}, // Inst #946 = PseudoVAMOSWAPEI64_WD_M2_M4_MASK + {6, OperandInfo112}, // Inst #947 = PseudoVAMOSWAPEI64_WD_M4_M4 + {7, OperandInfo113}, // Inst #948 = PseudoVAMOSWAPEI64_WD_M4_M4_MASK + {6, OperandInfo120}, // Inst #949 = PseudoVAMOSWAPEI64_WD_M4_M8 + {7, OperandInfo121}, // Inst #950 = PseudoVAMOSWAPEI64_WD_M4_M8_MASK + {6, OperandInfo114}, // Inst #951 = PseudoVAMOSWAPEI64_WD_M8_M8 + {7, OperandInfo115}, // Inst #952 = PseudoVAMOSWAPEI64_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #953 = PseudoVAMOSWAPEI64_WD_MF2_M1 + {7, OperandInfo99}, // Inst #954 = PseudoVAMOSWAPEI64_WD_MF2_M1_MASK + {6, OperandInfo98}, // Inst #955 = PseudoVAMOSWAPEI8_WD_M1_MF4 + {7, OperandInfo99}, // Inst #956 = PseudoVAMOSWAPEI8_WD_M1_MF4_MASK + {6, OperandInfo98}, // Inst #957 = PseudoVAMOSWAPEI8_WD_M1_MF8 + {7, OperandInfo99}, // Inst #958 = PseudoVAMOSWAPEI8_WD_M1_MF8_MASK + {6, OperandInfo100}, // Inst #959 = PseudoVAMOSWAPEI8_WD_M2_MF2 + {7, OperandInfo101}, // Inst #960 = PseudoVAMOSWAPEI8_WD_M2_MF2_MASK + {6, OperandInfo100}, // Inst #961 = PseudoVAMOSWAPEI8_WD_M2_MF4 + {7, OperandInfo101}, // Inst #962 = PseudoVAMOSWAPEI8_WD_M2_MF4_MASK + {6, OperandInfo102}, // Inst #963 = PseudoVAMOSWAPEI8_WD_M4_M1 + {7, OperandInfo103}, // Inst #964 = PseudoVAMOSWAPEI8_WD_M4_M1_MASK + {6, OperandInfo102}, // Inst #965 = PseudoVAMOSWAPEI8_WD_M4_MF2 + {7, OperandInfo103}, // Inst #966 = PseudoVAMOSWAPEI8_WD_M4_MF2_MASK + {6, OperandInfo122}, // Inst #967 = PseudoVAMOSWAPEI8_WD_M8_M1 + {7, OperandInfo123}, // Inst #968 = PseudoVAMOSWAPEI8_WD_M8_M1_MASK + {6, OperandInfo106}, // Inst #969 = PseudoVAMOSWAPEI8_WD_M8_M2 + {7, OperandInfo107}, // Inst #970 = PseudoVAMOSWAPEI8_WD_M8_M2_MASK + {6, OperandInfo98}, // Inst #971 = PseudoVAMOSWAPEI8_WD_MF2_MF8 + {7, OperandInfo99}, // Inst #972 = PseudoVAMOSWAPEI8_WD_MF2_MF8_MASK + {6, OperandInfo98}, // Inst #973 = PseudoVAMOXOREI16_WD_M1_MF2 + {7, OperandInfo99}, // Inst #974 = PseudoVAMOXOREI16_WD_M1_MF2_MASK + {6, OperandInfo98}, // Inst #975 = PseudoVAMOXOREI16_WD_M1_MF4 + {7, OperandInfo99}, // Inst #976 = PseudoVAMOXOREI16_WD_M1_MF4_MASK + {6, OperandInfo100}, // Inst #977 = PseudoVAMOXOREI16_WD_M2_M1 + {7, OperandInfo101}, // Inst #978 = PseudoVAMOXOREI16_WD_M2_M1_MASK + {6, OperandInfo100}, // Inst #979 = PseudoVAMOXOREI16_WD_M2_MF2 + {7, OperandInfo101}, // Inst #980 = PseudoVAMOXOREI16_WD_M2_MF2_MASK + {6, OperandInfo102}, // Inst #981 = PseudoVAMOXOREI16_WD_M4_M1 + {7, OperandInfo103}, // Inst #982 = PseudoVAMOXOREI16_WD_M4_M1_MASK + {6, OperandInfo104}, // Inst #983 = PseudoVAMOXOREI16_WD_M4_M2 + {7, OperandInfo105}, // Inst #984 = PseudoVAMOXOREI16_WD_M4_M2_MASK + {6, OperandInfo106}, // Inst #985 = PseudoVAMOXOREI16_WD_M8_M2 + {7, OperandInfo107}, // Inst #986 = PseudoVAMOXOREI16_WD_M8_M2_MASK + {6, OperandInfo108}, // Inst #987 = PseudoVAMOXOREI16_WD_M8_M4 + {7, OperandInfo109}, // Inst #988 = PseudoVAMOXOREI16_WD_M8_M4_MASK + {6, OperandInfo98}, // Inst #989 = PseudoVAMOXOREI16_WD_MF2_MF4 + {7, OperandInfo99}, // Inst #990 = PseudoVAMOXOREI16_WD_MF2_MF4_MASK + {6, OperandInfo98}, // Inst #991 = PseudoVAMOXOREI32_WD_M1_M1 + {7, OperandInfo99}, // Inst #992 = PseudoVAMOXOREI32_WD_M1_M1_MASK + {6, OperandInfo98}, // Inst #993 = PseudoVAMOXOREI32_WD_M1_MF2 + {7, OperandInfo99}, // Inst #994 = PseudoVAMOXOREI32_WD_M1_MF2_MASK + {6, OperandInfo100}, // Inst #995 = PseudoVAMOXOREI32_WD_M2_M1 + {7, OperandInfo101}, // Inst #996 = PseudoVAMOXOREI32_WD_M2_M1_MASK + {6, OperandInfo110}, // Inst #997 = PseudoVAMOXOREI32_WD_M2_M2 + {7, OperandInfo111}, // Inst #998 = PseudoVAMOXOREI32_WD_M2_M2_MASK + {6, OperandInfo104}, // Inst #999 = PseudoVAMOXOREI32_WD_M4_M2 + {7, OperandInfo105}, // Inst #1000 = PseudoVAMOXOREI32_WD_M4_M2_MASK + {6, OperandInfo112}, // Inst #1001 = PseudoVAMOXOREI32_WD_M4_M4 + {7, OperandInfo113}, // Inst #1002 = PseudoVAMOXOREI32_WD_M4_M4_MASK + {6, OperandInfo108}, // Inst #1003 = PseudoVAMOXOREI32_WD_M8_M4 + {7, OperandInfo109}, // Inst #1004 = PseudoVAMOXOREI32_WD_M8_M4_MASK + {6, OperandInfo114}, // Inst #1005 = PseudoVAMOXOREI32_WD_M8_M8 + {7, OperandInfo115}, // Inst #1006 = PseudoVAMOXOREI32_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #1007 = PseudoVAMOXOREI32_WD_MF2_MF2 + {7, OperandInfo99}, // Inst #1008 = PseudoVAMOXOREI32_WD_MF2_MF2_MASK + {6, OperandInfo98}, // Inst #1009 = PseudoVAMOXOREI64_WD_M1_M1 + {7, OperandInfo99}, // Inst #1010 = PseudoVAMOXOREI64_WD_M1_M1_MASK + {6, OperandInfo116}, // Inst #1011 = PseudoVAMOXOREI64_WD_M1_M2 + {7, OperandInfo117}, // Inst #1012 = PseudoVAMOXOREI64_WD_M1_M2_MASK + {6, OperandInfo110}, // Inst #1013 = PseudoVAMOXOREI64_WD_M2_M2 + {7, OperandInfo111}, // Inst #1014 = PseudoVAMOXOREI64_WD_M2_M2_MASK + {6, OperandInfo118}, // Inst #1015 = PseudoVAMOXOREI64_WD_M2_M4 + {7, OperandInfo119}, // Inst #1016 = PseudoVAMOXOREI64_WD_M2_M4_MASK + {6, OperandInfo112}, // Inst #1017 = PseudoVAMOXOREI64_WD_M4_M4 + {7, OperandInfo113}, // Inst #1018 = PseudoVAMOXOREI64_WD_M4_M4_MASK + {6, OperandInfo120}, // Inst #1019 = PseudoVAMOXOREI64_WD_M4_M8 + {7, OperandInfo121}, // Inst #1020 = PseudoVAMOXOREI64_WD_M4_M8_MASK + {6, OperandInfo114}, // Inst #1021 = PseudoVAMOXOREI64_WD_M8_M8 + {7, OperandInfo115}, // Inst #1022 = PseudoVAMOXOREI64_WD_M8_M8_MASK + {6, OperandInfo98}, // Inst #1023 = PseudoVAMOXOREI64_WD_MF2_M1 + {7, OperandInfo99}, // Inst #1024 = PseudoVAMOXOREI64_WD_MF2_M1_MASK + {6, OperandInfo98}, // Inst #1025 = PseudoVAMOXOREI8_WD_M1_MF4 + {7, OperandInfo99}, // Inst #1026 = PseudoVAMOXOREI8_WD_M1_MF4_MASK + {6, OperandInfo98}, // Inst #1027 = PseudoVAMOXOREI8_WD_M1_MF8 + {7, OperandInfo99}, // Inst #1028 = PseudoVAMOXOREI8_WD_M1_MF8_MASK + {6, OperandInfo100}, // Inst #1029 = PseudoVAMOXOREI8_WD_M2_MF2 + {7, OperandInfo101}, // Inst #1030 = PseudoVAMOXOREI8_WD_M2_MF2_MASK + {6, OperandInfo100}, // Inst #1031 = PseudoVAMOXOREI8_WD_M2_MF4 + {7, OperandInfo101}, // Inst #1032 = PseudoVAMOXOREI8_WD_M2_MF4_MASK + {6, OperandInfo102}, // Inst #1033 = PseudoVAMOXOREI8_WD_M4_M1 + {7, OperandInfo103}, // Inst #1034 = PseudoVAMOXOREI8_WD_M4_M1_MASK + {6, OperandInfo102}, // Inst #1035 = PseudoVAMOXOREI8_WD_M4_MF2 + {7, OperandInfo103}, // Inst #1036 = PseudoVAMOXOREI8_WD_M4_MF2_MASK + {6, OperandInfo122}, // Inst #1037 = PseudoVAMOXOREI8_WD_M8_M1 + {7, OperandInfo123}, // Inst #1038 = PseudoVAMOXOREI8_WD_M8_M1_MASK + {6, OperandInfo106}, // Inst #1039 = PseudoVAMOXOREI8_WD_M8_M2 + {7, OperandInfo107}, // Inst #1040 = PseudoVAMOXOREI8_WD_M8_M2_MASK + {6, OperandInfo98}, // Inst #1041 = PseudoVAMOXOREI8_WD_MF2_MF8 + {7, OperandInfo99}, // Inst #1042 = PseudoVAMOXOREI8_WD_MF2_MF8_MASK + {5, OperandInfo90}, // Inst #1043 = PseudoVAND_VI_M1 + {8, OperandInfo91}, // Inst #1044 = PseudoVAND_VI_M1_MASK + {5, OperandInfo92}, // Inst #1045 = PseudoVAND_VI_M2 + {8, OperandInfo93}, // Inst #1046 = PseudoVAND_VI_M2_MASK + {5, OperandInfo94}, // Inst #1047 = PseudoVAND_VI_M4 + {8, OperandInfo95}, // Inst #1048 = PseudoVAND_VI_M4_MASK + {5, OperandInfo96}, // Inst #1049 = PseudoVAND_VI_M8 + {8, OperandInfo97}, // Inst #1050 = PseudoVAND_VI_M8_MASK + {5, OperandInfo90}, // Inst #1051 = PseudoVAND_VI_MF2 + {8, OperandInfo91}, // Inst #1052 = PseudoVAND_VI_MF2_MASK + {5, OperandInfo90}, // Inst #1053 = PseudoVAND_VI_MF4 + {8, OperandInfo91}, // Inst #1054 = PseudoVAND_VI_MF4_MASK + {5, OperandInfo90}, // Inst #1055 = PseudoVAND_VI_MF8 + {8, OperandInfo91}, // Inst #1056 = PseudoVAND_VI_MF8_MASK + {5, OperandInfo62}, // Inst #1057 = PseudoVAND_VV_M1 + {8, OperandInfo63}, // Inst #1058 = PseudoVAND_VV_M1_MASK + {5, OperandInfo64}, // Inst #1059 = PseudoVAND_VV_M2 + {8, OperandInfo65}, // Inst #1060 = PseudoVAND_VV_M2_MASK + {5, OperandInfo66}, // Inst #1061 = PseudoVAND_VV_M4 + {8, OperandInfo67}, // Inst #1062 = PseudoVAND_VV_M4_MASK + {5, OperandInfo68}, // Inst #1063 = PseudoVAND_VV_M8 + {8, OperandInfo69}, // Inst #1064 = PseudoVAND_VV_M8_MASK + {5, OperandInfo62}, // Inst #1065 = PseudoVAND_VV_MF2 + {8, OperandInfo63}, // Inst #1066 = PseudoVAND_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1067 = PseudoVAND_VV_MF4 + {8, OperandInfo63}, // Inst #1068 = PseudoVAND_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1069 = PseudoVAND_VV_MF8 + {8, OperandInfo63}, // Inst #1070 = PseudoVAND_VV_MF8_MASK + {5, OperandInfo70}, // Inst #1071 = PseudoVAND_VX_M1 + {8, OperandInfo71}, // Inst #1072 = PseudoVAND_VX_M1_MASK + {5, OperandInfo72}, // Inst #1073 = PseudoVAND_VX_M2 + {8, OperandInfo73}, // Inst #1074 = PseudoVAND_VX_M2_MASK + {5, OperandInfo74}, // Inst #1075 = PseudoVAND_VX_M4 + {8, OperandInfo75}, // Inst #1076 = PseudoVAND_VX_M4_MASK + {5, OperandInfo76}, // Inst #1077 = PseudoVAND_VX_M8 + {8, OperandInfo77}, // Inst #1078 = PseudoVAND_VX_M8_MASK + {5, OperandInfo70}, // Inst #1079 = PseudoVAND_VX_MF2 + {8, OperandInfo71}, // Inst #1080 = PseudoVAND_VX_MF2_MASK + {5, OperandInfo70}, // Inst #1081 = PseudoVAND_VX_MF4 + {8, OperandInfo71}, // Inst #1082 = PseudoVAND_VX_MF4_MASK + {5, OperandInfo70}, // Inst #1083 = PseudoVAND_VX_MF8 + {8, OperandInfo71}, // Inst #1084 = PseudoVAND_VX_MF8_MASK + {5, OperandInfo62}, // Inst #1085 = PseudoVASUBU_VV_M1 + {8, OperandInfo63}, // Inst #1086 = PseudoVASUBU_VV_M1_MASK + {5, OperandInfo64}, // Inst #1087 = PseudoVASUBU_VV_M2 + {8, OperandInfo65}, // Inst #1088 = PseudoVASUBU_VV_M2_MASK + {5, OperandInfo66}, // Inst #1089 = PseudoVASUBU_VV_M4 + {8, OperandInfo67}, // Inst #1090 = PseudoVASUBU_VV_M4_MASK + {5, OperandInfo68}, // Inst #1091 = PseudoVASUBU_VV_M8 + {8, OperandInfo69}, // Inst #1092 = PseudoVASUBU_VV_M8_MASK + {5, OperandInfo62}, // Inst #1093 = PseudoVASUBU_VV_MF2 + {8, OperandInfo63}, // Inst #1094 = PseudoVASUBU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1095 = PseudoVASUBU_VV_MF4 + {8, OperandInfo63}, // Inst #1096 = PseudoVASUBU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1097 = PseudoVASUBU_VV_MF8 + {8, OperandInfo63}, // Inst #1098 = PseudoVASUBU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #1099 = PseudoVASUBU_VX_M1 + {8, OperandInfo71}, // Inst #1100 = PseudoVASUBU_VX_M1_MASK + {5, OperandInfo72}, // Inst #1101 = PseudoVASUBU_VX_M2 + {8, OperandInfo73}, // Inst #1102 = PseudoVASUBU_VX_M2_MASK + {5, OperandInfo74}, // Inst #1103 = PseudoVASUBU_VX_M4 + {8, OperandInfo75}, // Inst #1104 = PseudoVASUBU_VX_M4_MASK + {5, OperandInfo76}, // Inst #1105 = PseudoVASUBU_VX_M8 + {8, OperandInfo77}, // Inst #1106 = PseudoVASUBU_VX_M8_MASK + {5, OperandInfo70}, // Inst #1107 = PseudoVASUBU_VX_MF2 + {8, OperandInfo71}, // Inst #1108 = PseudoVASUBU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #1109 = PseudoVASUBU_VX_MF4 + {8, OperandInfo71}, // Inst #1110 = PseudoVASUBU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #1111 = PseudoVASUBU_VX_MF8 + {8, OperandInfo71}, // Inst #1112 = PseudoVASUBU_VX_MF8_MASK + {5, OperandInfo62}, // Inst #1113 = PseudoVASUB_VV_M1 + {8, OperandInfo63}, // Inst #1114 = PseudoVASUB_VV_M1_MASK + {5, OperandInfo64}, // Inst #1115 = PseudoVASUB_VV_M2 + {8, OperandInfo65}, // Inst #1116 = PseudoVASUB_VV_M2_MASK + {5, OperandInfo66}, // Inst #1117 = PseudoVASUB_VV_M4 + {8, OperandInfo67}, // Inst #1118 = PseudoVASUB_VV_M4_MASK + {5, OperandInfo68}, // Inst #1119 = PseudoVASUB_VV_M8 + {8, OperandInfo69}, // Inst #1120 = PseudoVASUB_VV_M8_MASK + {5, OperandInfo62}, // Inst #1121 = PseudoVASUB_VV_MF2 + {8, OperandInfo63}, // Inst #1122 = PseudoVASUB_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1123 = PseudoVASUB_VV_MF4 + {8, OperandInfo63}, // Inst #1124 = PseudoVASUB_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1125 = PseudoVASUB_VV_MF8 + {8, OperandInfo63}, // Inst #1126 = PseudoVASUB_VV_MF8_MASK + {5, OperandInfo70}, // Inst #1127 = PseudoVASUB_VX_M1 + {8, OperandInfo71}, // Inst #1128 = PseudoVASUB_VX_M1_MASK + {5, OperandInfo72}, // Inst #1129 = PseudoVASUB_VX_M2 + {8, OperandInfo73}, // Inst #1130 = PseudoVASUB_VX_M2_MASK + {5, OperandInfo74}, // Inst #1131 = PseudoVASUB_VX_M4 + {8, OperandInfo75}, // Inst #1132 = PseudoVASUB_VX_M4_MASK + {5, OperandInfo76}, // Inst #1133 = PseudoVASUB_VX_M8 + {8, OperandInfo77}, // Inst #1134 = PseudoVASUB_VX_M8_MASK + {5, OperandInfo70}, // Inst #1135 = PseudoVASUB_VX_MF2 + {8, OperandInfo71}, // Inst #1136 = PseudoVASUB_VX_MF2_MASK + {5, OperandInfo70}, // Inst #1137 = PseudoVASUB_VX_MF4 + {8, OperandInfo71}, // Inst #1138 = PseudoVASUB_VX_MF4_MASK + {5, OperandInfo70}, // Inst #1139 = PseudoVASUB_VX_MF8 + {8, OperandInfo71}, // Inst #1140 = PseudoVASUB_VX_MF8_MASK + {6, OperandInfo124}, // Inst #1141 = PseudoVCOMPRESS_VM_M1 + {6, OperandInfo125}, // Inst #1142 = PseudoVCOMPRESS_VM_M2 + {6, OperandInfo126}, // Inst #1143 = PseudoVCOMPRESS_VM_M4 + {6, OperandInfo127}, // Inst #1144 = PseudoVCOMPRESS_VM_M8 + {6, OperandInfo124}, // Inst #1145 = PseudoVCOMPRESS_VM_MF2 + {6, OperandInfo124}, // Inst #1146 = PseudoVCOMPRESS_VM_MF4 + {6, OperandInfo124}, // Inst #1147 = PseudoVCOMPRESS_VM_MF8 + {4, OperandInfo128}, // Inst #1148 = PseudoVCPOP_M_B1 + {4, OperandInfo128}, // Inst #1149 = PseudoVCPOP_M_B16 + {5, OperandInfo129}, // Inst #1150 = PseudoVCPOP_M_B16_MASK + {5, OperandInfo129}, // Inst #1151 = PseudoVCPOP_M_B1_MASK + {4, OperandInfo128}, // Inst #1152 = PseudoVCPOP_M_B2 + {5, OperandInfo129}, // Inst #1153 = PseudoVCPOP_M_B2_MASK + {4, OperandInfo128}, // Inst #1154 = PseudoVCPOP_M_B32 + {5, OperandInfo129}, // Inst #1155 = PseudoVCPOP_M_B32_MASK + {4, OperandInfo128}, // Inst #1156 = PseudoVCPOP_M_B4 + {5, OperandInfo129}, // Inst #1157 = PseudoVCPOP_M_B4_MASK + {4, OperandInfo128}, // Inst #1158 = PseudoVCPOP_M_B64 + {5, OperandInfo129}, // Inst #1159 = PseudoVCPOP_M_B64_MASK + {4, OperandInfo128}, // Inst #1160 = PseudoVCPOP_M_B8 + {5, OperandInfo129}, // Inst #1161 = PseudoVCPOP_M_B8_MASK + {5, OperandInfo62}, // Inst #1162 = PseudoVDIVU_VV_M1 + {8, OperandInfo63}, // Inst #1163 = PseudoVDIVU_VV_M1_MASK + {5, OperandInfo64}, // Inst #1164 = PseudoVDIVU_VV_M2 + {8, OperandInfo65}, // Inst #1165 = PseudoVDIVU_VV_M2_MASK + {5, OperandInfo66}, // Inst #1166 = PseudoVDIVU_VV_M4 + {8, OperandInfo67}, // Inst #1167 = PseudoVDIVU_VV_M4_MASK + {5, OperandInfo68}, // Inst #1168 = PseudoVDIVU_VV_M8 + {8, OperandInfo69}, // Inst #1169 = PseudoVDIVU_VV_M8_MASK + {5, OperandInfo62}, // Inst #1170 = PseudoVDIVU_VV_MF2 + {8, OperandInfo63}, // Inst #1171 = PseudoVDIVU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1172 = PseudoVDIVU_VV_MF4 + {8, OperandInfo63}, // Inst #1173 = PseudoVDIVU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1174 = PseudoVDIVU_VV_MF8 + {8, OperandInfo63}, // Inst #1175 = PseudoVDIVU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #1176 = PseudoVDIVU_VX_M1 + {8, OperandInfo71}, // Inst #1177 = PseudoVDIVU_VX_M1_MASK + {5, OperandInfo72}, // Inst #1178 = PseudoVDIVU_VX_M2 + {8, OperandInfo73}, // Inst #1179 = PseudoVDIVU_VX_M2_MASK + {5, OperandInfo74}, // Inst #1180 = PseudoVDIVU_VX_M4 + {8, OperandInfo75}, // Inst #1181 = PseudoVDIVU_VX_M4_MASK + {5, OperandInfo76}, // Inst #1182 = PseudoVDIVU_VX_M8 + {8, OperandInfo77}, // Inst #1183 = PseudoVDIVU_VX_M8_MASK + {5, OperandInfo70}, // Inst #1184 = PseudoVDIVU_VX_MF2 + {8, OperandInfo71}, // Inst #1185 = PseudoVDIVU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #1186 = PseudoVDIVU_VX_MF4 + {8, OperandInfo71}, // Inst #1187 = PseudoVDIVU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #1188 = PseudoVDIVU_VX_MF8 + {8, OperandInfo71}, // Inst #1189 = PseudoVDIVU_VX_MF8_MASK + {5, OperandInfo62}, // Inst #1190 = PseudoVDIV_VV_M1 + {8, OperandInfo63}, // Inst #1191 = PseudoVDIV_VV_M1_MASK + {5, OperandInfo64}, // Inst #1192 = PseudoVDIV_VV_M2 + {8, OperandInfo65}, // Inst #1193 = PseudoVDIV_VV_M2_MASK + {5, OperandInfo66}, // Inst #1194 = PseudoVDIV_VV_M4 + {8, OperandInfo67}, // Inst #1195 = PseudoVDIV_VV_M4_MASK + {5, OperandInfo68}, // Inst #1196 = PseudoVDIV_VV_M8 + {8, OperandInfo69}, // Inst #1197 = PseudoVDIV_VV_M8_MASK + {5, OperandInfo62}, // Inst #1198 = PseudoVDIV_VV_MF2 + {8, OperandInfo63}, // Inst #1199 = PseudoVDIV_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1200 = PseudoVDIV_VV_MF4 + {8, OperandInfo63}, // Inst #1201 = PseudoVDIV_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1202 = PseudoVDIV_VV_MF8 + {8, OperandInfo63}, // Inst #1203 = PseudoVDIV_VV_MF8_MASK + {5, OperandInfo70}, // Inst #1204 = PseudoVDIV_VX_M1 + {8, OperandInfo71}, // Inst #1205 = PseudoVDIV_VX_M1_MASK + {5, OperandInfo72}, // Inst #1206 = PseudoVDIV_VX_M2 + {8, OperandInfo73}, // Inst #1207 = PseudoVDIV_VX_M2_MASK + {5, OperandInfo74}, // Inst #1208 = PseudoVDIV_VX_M4 + {8, OperandInfo75}, // Inst #1209 = PseudoVDIV_VX_M4_MASK + {5, OperandInfo76}, // Inst #1210 = PseudoVDIV_VX_M8 + {8, OperandInfo77}, // Inst #1211 = PseudoVDIV_VX_M8_MASK + {5, OperandInfo70}, // Inst #1212 = PseudoVDIV_VX_MF2 + {8, OperandInfo71}, // Inst #1213 = PseudoVDIV_VX_MF2_MASK + {5, OperandInfo70}, // Inst #1214 = PseudoVDIV_VX_MF4 + {8, OperandInfo71}, // Inst #1215 = PseudoVDIV_VX_MF4_MASK + {5, OperandInfo70}, // Inst #1216 = PseudoVDIV_VX_MF8 + {8, OperandInfo71}, // Inst #1217 = PseudoVDIV_VX_MF8_MASK + {5, OperandInfo130}, // Inst #1218 = PseudoVFADD_VF16_M1 + {8, OperandInfo131}, // Inst #1219 = PseudoVFADD_VF16_M1_MASK + {5, OperandInfo132}, // Inst #1220 = PseudoVFADD_VF16_M2 + {8, OperandInfo133}, // Inst #1221 = PseudoVFADD_VF16_M2_MASK + {5, OperandInfo134}, // Inst #1222 = PseudoVFADD_VF16_M4 + {8, OperandInfo135}, // Inst #1223 = PseudoVFADD_VF16_M4_MASK + {5, OperandInfo136}, // Inst #1224 = PseudoVFADD_VF16_M8 + {8, OperandInfo137}, // Inst #1225 = PseudoVFADD_VF16_M8_MASK + {5, OperandInfo130}, // Inst #1226 = PseudoVFADD_VF16_MF2 + {8, OperandInfo131}, // Inst #1227 = PseudoVFADD_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #1228 = PseudoVFADD_VF16_MF4 + {8, OperandInfo131}, // Inst #1229 = PseudoVFADD_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #1230 = PseudoVFADD_VF16_MF8 + {8, OperandInfo131}, // Inst #1231 = PseudoVFADD_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #1232 = PseudoVFADD_VF32_M1 + {8, OperandInfo139}, // Inst #1233 = PseudoVFADD_VF32_M1_MASK + {5, OperandInfo140}, // Inst #1234 = PseudoVFADD_VF32_M2 + {8, OperandInfo141}, // Inst #1235 = PseudoVFADD_VF32_M2_MASK + {5, OperandInfo142}, // Inst #1236 = PseudoVFADD_VF32_M4 + {8, OperandInfo143}, // Inst #1237 = PseudoVFADD_VF32_M4_MASK + {5, OperandInfo144}, // Inst #1238 = PseudoVFADD_VF32_M8 + {8, OperandInfo145}, // Inst #1239 = PseudoVFADD_VF32_M8_MASK + {5, OperandInfo138}, // Inst #1240 = PseudoVFADD_VF32_MF2 + {8, OperandInfo139}, // Inst #1241 = PseudoVFADD_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #1242 = PseudoVFADD_VF32_MF4 + {8, OperandInfo139}, // Inst #1243 = PseudoVFADD_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #1244 = PseudoVFADD_VF32_MF8 + {8, OperandInfo139}, // Inst #1245 = PseudoVFADD_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #1246 = PseudoVFADD_VF64_M1 + {8, OperandInfo147}, // Inst #1247 = PseudoVFADD_VF64_M1_MASK + {5, OperandInfo148}, // Inst #1248 = PseudoVFADD_VF64_M2 + {8, OperandInfo149}, // Inst #1249 = PseudoVFADD_VF64_M2_MASK + {5, OperandInfo150}, // Inst #1250 = PseudoVFADD_VF64_M4 + {8, OperandInfo151}, // Inst #1251 = PseudoVFADD_VF64_M4_MASK + {5, OperandInfo152}, // Inst #1252 = PseudoVFADD_VF64_M8 + {8, OperandInfo153}, // Inst #1253 = PseudoVFADD_VF64_M8_MASK + {5, OperandInfo146}, // Inst #1254 = PseudoVFADD_VF64_MF2 + {8, OperandInfo147}, // Inst #1255 = PseudoVFADD_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #1256 = PseudoVFADD_VF64_MF4 + {8, OperandInfo147}, // Inst #1257 = PseudoVFADD_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #1258 = PseudoVFADD_VF64_MF8 + {8, OperandInfo147}, // Inst #1259 = PseudoVFADD_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #1260 = PseudoVFADD_VV_M1 + {8, OperandInfo63}, // Inst #1261 = PseudoVFADD_VV_M1_MASK + {5, OperandInfo64}, // Inst #1262 = PseudoVFADD_VV_M2 + {8, OperandInfo65}, // Inst #1263 = PseudoVFADD_VV_M2_MASK + {5, OperandInfo66}, // Inst #1264 = PseudoVFADD_VV_M4 + {8, OperandInfo67}, // Inst #1265 = PseudoVFADD_VV_M4_MASK + {5, OperandInfo68}, // Inst #1266 = PseudoVFADD_VV_M8 + {8, OperandInfo69}, // Inst #1267 = PseudoVFADD_VV_M8_MASK + {5, OperandInfo62}, // Inst #1268 = PseudoVFADD_VV_MF2 + {8, OperandInfo63}, // Inst #1269 = PseudoVFADD_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1270 = PseudoVFADD_VV_MF4 + {8, OperandInfo63}, // Inst #1271 = PseudoVFADD_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1272 = PseudoVFADD_VV_MF8 + {8, OperandInfo63}, // Inst #1273 = PseudoVFADD_VV_MF8_MASK + {4, OperandInfo154}, // Inst #1274 = PseudoVFCLASS_V_M1 + {6, OperandInfo155}, // Inst #1275 = PseudoVFCLASS_V_M1_MASK + {4, OperandInfo156}, // Inst #1276 = PseudoVFCLASS_V_M2 + {6, OperandInfo157}, // Inst #1277 = PseudoVFCLASS_V_M2_MASK + {4, OperandInfo158}, // Inst #1278 = PseudoVFCLASS_V_M4 + {6, OperandInfo159}, // Inst #1279 = PseudoVFCLASS_V_M4_MASK + {4, OperandInfo160}, // Inst #1280 = PseudoVFCLASS_V_M8 + {6, OperandInfo161}, // Inst #1281 = PseudoVFCLASS_V_M8_MASK + {4, OperandInfo154}, // Inst #1282 = PseudoVFCLASS_V_MF2 + {6, OperandInfo155}, // Inst #1283 = PseudoVFCLASS_V_MF2_MASK + {4, OperandInfo154}, // Inst #1284 = PseudoVFCLASS_V_MF4 + {6, OperandInfo155}, // Inst #1285 = PseudoVFCLASS_V_MF4_MASK + {4, OperandInfo154}, // Inst #1286 = PseudoVFCLASS_V_MF8 + {6, OperandInfo155}, // Inst #1287 = PseudoVFCLASS_V_MF8_MASK + {4, OperandInfo154}, // Inst #1288 = PseudoVFCVT_F_XU_V_M1 + {7, OperandInfo162}, // Inst #1289 = PseudoVFCVT_F_XU_V_M1_MASK + {4, OperandInfo156}, // Inst #1290 = PseudoVFCVT_F_XU_V_M2 + {7, OperandInfo163}, // Inst #1291 = PseudoVFCVT_F_XU_V_M2_MASK + {4, OperandInfo158}, // Inst #1292 = PseudoVFCVT_F_XU_V_M4 + {7, OperandInfo164}, // Inst #1293 = PseudoVFCVT_F_XU_V_M4_MASK + {4, OperandInfo160}, // Inst #1294 = PseudoVFCVT_F_XU_V_M8 + {7, OperandInfo165}, // Inst #1295 = PseudoVFCVT_F_XU_V_M8_MASK + {4, OperandInfo154}, // Inst #1296 = PseudoVFCVT_F_XU_V_MF2 + {7, OperandInfo162}, // Inst #1297 = PseudoVFCVT_F_XU_V_MF2_MASK + {4, OperandInfo154}, // Inst #1298 = PseudoVFCVT_F_XU_V_MF4 + {7, OperandInfo162}, // Inst #1299 = PseudoVFCVT_F_XU_V_MF4_MASK + {4, OperandInfo154}, // Inst #1300 = PseudoVFCVT_F_XU_V_MF8 + {7, OperandInfo162}, // Inst #1301 = PseudoVFCVT_F_XU_V_MF8_MASK + {4, OperandInfo154}, // Inst #1302 = PseudoVFCVT_F_X_V_M1 + {7, OperandInfo162}, // Inst #1303 = PseudoVFCVT_F_X_V_M1_MASK + {4, OperandInfo156}, // Inst #1304 = PseudoVFCVT_F_X_V_M2 + {7, OperandInfo163}, // Inst #1305 = PseudoVFCVT_F_X_V_M2_MASK + {4, OperandInfo158}, // Inst #1306 = PseudoVFCVT_F_X_V_M4 + {7, OperandInfo164}, // Inst #1307 = PseudoVFCVT_F_X_V_M4_MASK + {4, OperandInfo160}, // Inst #1308 = PseudoVFCVT_F_X_V_M8 + {7, OperandInfo165}, // Inst #1309 = PseudoVFCVT_F_X_V_M8_MASK + {4, OperandInfo154}, // Inst #1310 = PseudoVFCVT_F_X_V_MF2 + {7, OperandInfo162}, // Inst #1311 = PseudoVFCVT_F_X_V_MF2_MASK + {4, OperandInfo154}, // Inst #1312 = PseudoVFCVT_F_X_V_MF4 + {7, OperandInfo162}, // Inst #1313 = PseudoVFCVT_F_X_V_MF4_MASK + {4, OperandInfo154}, // Inst #1314 = PseudoVFCVT_F_X_V_MF8 + {7, OperandInfo162}, // Inst #1315 = PseudoVFCVT_F_X_V_MF8_MASK + {4, OperandInfo154}, // Inst #1316 = PseudoVFCVT_RTZ_XU_F_V_M1 + {7, OperandInfo162}, // Inst #1317 = PseudoVFCVT_RTZ_XU_F_V_M1_MASK + {4, OperandInfo156}, // Inst #1318 = PseudoVFCVT_RTZ_XU_F_V_M2 + {7, OperandInfo163}, // Inst #1319 = PseudoVFCVT_RTZ_XU_F_V_M2_MASK + {4, OperandInfo158}, // Inst #1320 = PseudoVFCVT_RTZ_XU_F_V_M4 + {7, OperandInfo164}, // Inst #1321 = PseudoVFCVT_RTZ_XU_F_V_M4_MASK + {4, OperandInfo160}, // Inst #1322 = PseudoVFCVT_RTZ_XU_F_V_M8 + {7, OperandInfo165}, // Inst #1323 = PseudoVFCVT_RTZ_XU_F_V_M8_MASK + {4, OperandInfo154}, // Inst #1324 = PseudoVFCVT_RTZ_XU_F_V_MF2 + {7, OperandInfo162}, // Inst #1325 = PseudoVFCVT_RTZ_XU_F_V_MF2_MASK + {4, OperandInfo154}, // Inst #1326 = PseudoVFCVT_RTZ_XU_F_V_MF4 + {7, OperandInfo162}, // Inst #1327 = PseudoVFCVT_RTZ_XU_F_V_MF4_MASK + {4, OperandInfo154}, // Inst #1328 = PseudoVFCVT_RTZ_XU_F_V_MF8 + {7, OperandInfo162}, // Inst #1329 = PseudoVFCVT_RTZ_XU_F_V_MF8_MASK + {4, OperandInfo154}, // Inst #1330 = PseudoVFCVT_RTZ_X_F_V_M1 + {7, OperandInfo162}, // Inst #1331 = PseudoVFCVT_RTZ_X_F_V_M1_MASK + {4, OperandInfo156}, // Inst #1332 = PseudoVFCVT_RTZ_X_F_V_M2 + {7, OperandInfo163}, // Inst #1333 = PseudoVFCVT_RTZ_X_F_V_M2_MASK + {4, OperandInfo158}, // Inst #1334 = PseudoVFCVT_RTZ_X_F_V_M4 + {7, OperandInfo164}, // Inst #1335 = PseudoVFCVT_RTZ_X_F_V_M4_MASK + {4, OperandInfo160}, // Inst #1336 = PseudoVFCVT_RTZ_X_F_V_M8 + {7, OperandInfo165}, // Inst #1337 = PseudoVFCVT_RTZ_X_F_V_M8_MASK + {4, OperandInfo154}, // Inst #1338 = PseudoVFCVT_RTZ_X_F_V_MF2 + {7, OperandInfo162}, // Inst #1339 = PseudoVFCVT_RTZ_X_F_V_MF2_MASK + {4, OperandInfo154}, // Inst #1340 = PseudoVFCVT_RTZ_X_F_V_MF4 + {7, OperandInfo162}, // Inst #1341 = PseudoVFCVT_RTZ_X_F_V_MF4_MASK + {4, OperandInfo154}, // Inst #1342 = PseudoVFCVT_RTZ_X_F_V_MF8 + {7, OperandInfo162}, // Inst #1343 = PseudoVFCVT_RTZ_X_F_V_MF8_MASK + {4, OperandInfo154}, // Inst #1344 = PseudoVFCVT_XU_F_V_M1 + {7, OperandInfo162}, // Inst #1345 = PseudoVFCVT_XU_F_V_M1_MASK + {4, OperandInfo156}, // Inst #1346 = PseudoVFCVT_XU_F_V_M2 + {7, OperandInfo163}, // Inst #1347 = PseudoVFCVT_XU_F_V_M2_MASK + {4, OperandInfo158}, // Inst #1348 = PseudoVFCVT_XU_F_V_M4 + {7, OperandInfo164}, // Inst #1349 = PseudoVFCVT_XU_F_V_M4_MASK + {4, OperandInfo160}, // Inst #1350 = PseudoVFCVT_XU_F_V_M8 + {7, OperandInfo165}, // Inst #1351 = PseudoVFCVT_XU_F_V_M8_MASK + {4, OperandInfo154}, // Inst #1352 = PseudoVFCVT_XU_F_V_MF2 + {7, OperandInfo162}, // Inst #1353 = PseudoVFCVT_XU_F_V_MF2_MASK + {4, OperandInfo154}, // Inst #1354 = PseudoVFCVT_XU_F_V_MF4 + {7, OperandInfo162}, // Inst #1355 = PseudoVFCVT_XU_F_V_MF4_MASK + {4, OperandInfo154}, // Inst #1356 = PseudoVFCVT_XU_F_V_MF8 + {7, OperandInfo162}, // Inst #1357 = PseudoVFCVT_XU_F_V_MF8_MASK + {4, OperandInfo154}, // Inst #1358 = PseudoVFCVT_X_F_V_M1 + {7, OperandInfo162}, // Inst #1359 = PseudoVFCVT_X_F_V_M1_MASK + {4, OperandInfo156}, // Inst #1360 = PseudoVFCVT_X_F_V_M2 + {7, OperandInfo163}, // Inst #1361 = PseudoVFCVT_X_F_V_M2_MASK + {4, OperandInfo158}, // Inst #1362 = PseudoVFCVT_X_F_V_M4 + {7, OperandInfo164}, // Inst #1363 = PseudoVFCVT_X_F_V_M4_MASK + {4, OperandInfo160}, // Inst #1364 = PseudoVFCVT_X_F_V_M8 + {7, OperandInfo165}, // Inst #1365 = PseudoVFCVT_X_F_V_M8_MASK + {4, OperandInfo154}, // Inst #1366 = PseudoVFCVT_X_F_V_MF2 + {7, OperandInfo162}, // Inst #1367 = PseudoVFCVT_X_F_V_MF2_MASK + {4, OperandInfo154}, // Inst #1368 = PseudoVFCVT_X_F_V_MF4 + {7, OperandInfo162}, // Inst #1369 = PseudoVFCVT_X_F_V_MF4_MASK + {4, OperandInfo154}, // Inst #1370 = PseudoVFCVT_X_F_V_MF8 + {7, OperandInfo162}, // Inst #1371 = PseudoVFCVT_X_F_V_MF8_MASK + {5, OperandInfo130}, // Inst #1372 = PseudoVFDIV_VF16_M1 + {8, OperandInfo131}, // Inst #1373 = PseudoVFDIV_VF16_M1_MASK + {5, OperandInfo132}, // Inst #1374 = PseudoVFDIV_VF16_M2 + {8, OperandInfo133}, // Inst #1375 = PseudoVFDIV_VF16_M2_MASK + {5, OperandInfo134}, // Inst #1376 = PseudoVFDIV_VF16_M4 + {8, OperandInfo135}, // Inst #1377 = PseudoVFDIV_VF16_M4_MASK + {5, OperandInfo136}, // Inst #1378 = PseudoVFDIV_VF16_M8 + {8, OperandInfo137}, // Inst #1379 = PseudoVFDIV_VF16_M8_MASK + {5, OperandInfo130}, // Inst #1380 = PseudoVFDIV_VF16_MF2 + {8, OperandInfo131}, // Inst #1381 = PseudoVFDIV_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #1382 = PseudoVFDIV_VF16_MF4 + {8, OperandInfo131}, // Inst #1383 = PseudoVFDIV_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #1384 = PseudoVFDIV_VF16_MF8 + {8, OperandInfo131}, // Inst #1385 = PseudoVFDIV_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #1386 = PseudoVFDIV_VF32_M1 + {8, OperandInfo139}, // Inst #1387 = PseudoVFDIV_VF32_M1_MASK + {5, OperandInfo140}, // Inst #1388 = PseudoVFDIV_VF32_M2 + {8, OperandInfo141}, // Inst #1389 = PseudoVFDIV_VF32_M2_MASK + {5, OperandInfo142}, // Inst #1390 = PseudoVFDIV_VF32_M4 + {8, OperandInfo143}, // Inst #1391 = PseudoVFDIV_VF32_M4_MASK + {5, OperandInfo144}, // Inst #1392 = PseudoVFDIV_VF32_M8 + {8, OperandInfo145}, // Inst #1393 = PseudoVFDIV_VF32_M8_MASK + {5, OperandInfo138}, // Inst #1394 = PseudoVFDIV_VF32_MF2 + {8, OperandInfo139}, // Inst #1395 = PseudoVFDIV_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #1396 = PseudoVFDIV_VF32_MF4 + {8, OperandInfo139}, // Inst #1397 = PseudoVFDIV_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #1398 = PseudoVFDIV_VF32_MF8 + {8, OperandInfo139}, // Inst #1399 = PseudoVFDIV_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #1400 = PseudoVFDIV_VF64_M1 + {8, OperandInfo147}, // Inst #1401 = PseudoVFDIV_VF64_M1_MASK + {5, OperandInfo148}, // Inst #1402 = PseudoVFDIV_VF64_M2 + {8, OperandInfo149}, // Inst #1403 = PseudoVFDIV_VF64_M2_MASK + {5, OperandInfo150}, // Inst #1404 = PseudoVFDIV_VF64_M4 + {8, OperandInfo151}, // Inst #1405 = PseudoVFDIV_VF64_M4_MASK + {5, OperandInfo152}, // Inst #1406 = PseudoVFDIV_VF64_M8 + {8, OperandInfo153}, // Inst #1407 = PseudoVFDIV_VF64_M8_MASK + {5, OperandInfo146}, // Inst #1408 = PseudoVFDIV_VF64_MF2 + {8, OperandInfo147}, // Inst #1409 = PseudoVFDIV_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #1410 = PseudoVFDIV_VF64_MF4 + {8, OperandInfo147}, // Inst #1411 = PseudoVFDIV_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #1412 = PseudoVFDIV_VF64_MF8 + {8, OperandInfo147}, // Inst #1413 = PseudoVFDIV_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #1414 = PseudoVFDIV_VV_M1 + {8, OperandInfo63}, // Inst #1415 = PseudoVFDIV_VV_M1_MASK + {5, OperandInfo64}, // Inst #1416 = PseudoVFDIV_VV_M2 + {8, OperandInfo65}, // Inst #1417 = PseudoVFDIV_VV_M2_MASK + {5, OperandInfo66}, // Inst #1418 = PseudoVFDIV_VV_M4 + {8, OperandInfo67}, // Inst #1419 = PseudoVFDIV_VV_M4_MASK + {5, OperandInfo68}, // Inst #1420 = PseudoVFDIV_VV_M8 + {8, OperandInfo69}, // Inst #1421 = PseudoVFDIV_VV_M8_MASK + {5, OperandInfo62}, // Inst #1422 = PseudoVFDIV_VV_MF2 + {8, OperandInfo63}, // Inst #1423 = PseudoVFDIV_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1424 = PseudoVFDIV_VV_MF4 + {8, OperandInfo63}, // Inst #1425 = PseudoVFDIV_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1426 = PseudoVFDIV_VV_MF8 + {8, OperandInfo63}, // Inst #1427 = PseudoVFDIV_VV_MF8_MASK + {4, OperandInfo128}, // Inst #1428 = PseudoVFIRST_M_B1 + {4, OperandInfo128}, // Inst #1429 = PseudoVFIRST_M_B16 + {5, OperandInfo129}, // Inst #1430 = PseudoVFIRST_M_B16_MASK + {5, OperandInfo129}, // Inst #1431 = PseudoVFIRST_M_B1_MASK + {4, OperandInfo128}, // Inst #1432 = PseudoVFIRST_M_B2 + {5, OperandInfo129}, // Inst #1433 = PseudoVFIRST_M_B2_MASK + {4, OperandInfo128}, // Inst #1434 = PseudoVFIRST_M_B32 + {5, OperandInfo129}, // Inst #1435 = PseudoVFIRST_M_B32_MASK + {4, OperandInfo128}, // Inst #1436 = PseudoVFIRST_M_B4 + {5, OperandInfo129}, // Inst #1437 = PseudoVFIRST_M_B4_MASK + {4, OperandInfo128}, // Inst #1438 = PseudoVFIRST_M_B64 + {5, OperandInfo129}, // Inst #1439 = PseudoVFIRST_M_B64_MASK + {4, OperandInfo128}, // Inst #1440 = PseudoVFIRST_M_B8 + {5, OperandInfo129}, // Inst #1441 = PseudoVFIRST_M_B8_MASK + {7, OperandInfo166}, // Inst #1442 = PseudoVFMACC_VF16_M1 + {7, OperandInfo167}, // Inst #1443 = PseudoVFMACC_VF16_M1_MASK + {7, OperandInfo168}, // Inst #1444 = PseudoVFMACC_VF16_M2 + {7, OperandInfo169}, // Inst #1445 = PseudoVFMACC_VF16_M2_MASK + {7, OperandInfo170}, // Inst #1446 = PseudoVFMACC_VF16_M4 + {7, OperandInfo171}, // Inst #1447 = PseudoVFMACC_VF16_M4_MASK + {7, OperandInfo172}, // Inst #1448 = PseudoVFMACC_VF16_M8 + {7, OperandInfo173}, // Inst #1449 = PseudoVFMACC_VF16_M8_MASK + {7, OperandInfo166}, // Inst #1450 = PseudoVFMACC_VF16_MF2 + {7, OperandInfo167}, // Inst #1451 = PseudoVFMACC_VF16_MF2_MASK + {7, OperandInfo166}, // Inst #1452 = PseudoVFMACC_VF16_MF4 + {7, OperandInfo167}, // Inst #1453 = PseudoVFMACC_VF16_MF4_MASK + {7, OperandInfo166}, // Inst #1454 = PseudoVFMACC_VF16_MF8 + {7, OperandInfo167}, // Inst #1455 = PseudoVFMACC_VF16_MF8_MASK + {7, OperandInfo174}, // Inst #1456 = PseudoVFMACC_VF32_M1 + {7, OperandInfo175}, // Inst #1457 = PseudoVFMACC_VF32_M1_MASK + {7, OperandInfo176}, // Inst #1458 = PseudoVFMACC_VF32_M2 + {7, OperandInfo177}, // Inst #1459 = PseudoVFMACC_VF32_M2_MASK + {7, OperandInfo178}, // Inst #1460 = PseudoVFMACC_VF32_M4 + {7, OperandInfo179}, // Inst #1461 = PseudoVFMACC_VF32_M4_MASK + {7, OperandInfo180}, // Inst #1462 = PseudoVFMACC_VF32_M8 + {7, OperandInfo181}, // Inst #1463 = PseudoVFMACC_VF32_M8_MASK + {7, OperandInfo174}, // Inst #1464 = PseudoVFMACC_VF32_MF2 + {7, OperandInfo175}, // Inst #1465 = PseudoVFMACC_VF32_MF2_MASK + {7, OperandInfo174}, // Inst #1466 = PseudoVFMACC_VF32_MF4 + {7, OperandInfo175}, // Inst #1467 = PseudoVFMACC_VF32_MF4_MASK + {7, OperandInfo174}, // Inst #1468 = PseudoVFMACC_VF32_MF8 + {7, OperandInfo175}, // Inst #1469 = PseudoVFMACC_VF32_MF8_MASK + {7, OperandInfo182}, // Inst #1470 = PseudoVFMACC_VF64_M1 + {7, OperandInfo183}, // Inst #1471 = PseudoVFMACC_VF64_M1_MASK + {7, OperandInfo184}, // Inst #1472 = PseudoVFMACC_VF64_M2 + {7, OperandInfo185}, // Inst #1473 = PseudoVFMACC_VF64_M2_MASK + {7, OperandInfo186}, // Inst #1474 = PseudoVFMACC_VF64_M4 + {7, OperandInfo187}, // Inst #1475 = PseudoVFMACC_VF64_M4_MASK + {7, OperandInfo188}, // Inst #1476 = PseudoVFMACC_VF64_M8 + {7, OperandInfo189}, // Inst #1477 = PseudoVFMACC_VF64_M8_MASK + {7, OperandInfo182}, // Inst #1478 = PseudoVFMACC_VF64_MF2 + {7, OperandInfo183}, // Inst #1479 = PseudoVFMACC_VF64_MF2_MASK + {7, OperandInfo182}, // Inst #1480 = PseudoVFMACC_VF64_MF4 + {7, OperandInfo183}, // Inst #1481 = PseudoVFMACC_VF64_MF4_MASK + {7, OperandInfo182}, // Inst #1482 = PseudoVFMACC_VF64_MF8 + {7, OperandInfo183}, // Inst #1483 = PseudoVFMACC_VF64_MF8_MASK + {7, OperandInfo190}, // Inst #1484 = PseudoVFMACC_VV_M1 + {7, OperandInfo191}, // Inst #1485 = PseudoVFMACC_VV_M1_MASK + {7, OperandInfo192}, // Inst #1486 = PseudoVFMACC_VV_M2 + {7, OperandInfo193}, // Inst #1487 = PseudoVFMACC_VV_M2_MASK + {7, OperandInfo194}, // Inst #1488 = PseudoVFMACC_VV_M4 + {7, OperandInfo195}, // Inst #1489 = PseudoVFMACC_VV_M4_MASK + {7, OperandInfo196}, // Inst #1490 = PseudoVFMACC_VV_M8 + {7, OperandInfo197}, // Inst #1491 = PseudoVFMACC_VV_M8_MASK + {7, OperandInfo190}, // Inst #1492 = PseudoVFMACC_VV_MF2 + {7, OperandInfo191}, // Inst #1493 = PseudoVFMACC_VV_MF2_MASK + {7, OperandInfo190}, // Inst #1494 = PseudoVFMACC_VV_MF4 + {7, OperandInfo191}, // Inst #1495 = PseudoVFMACC_VV_MF4_MASK + {7, OperandInfo190}, // Inst #1496 = PseudoVFMACC_VV_MF8 + {7, OperandInfo191}, // Inst #1497 = PseudoVFMACC_VV_MF8_MASK + {7, OperandInfo166}, // Inst #1498 = PseudoVFMADD_VF16_M1 + {7, OperandInfo167}, // Inst #1499 = PseudoVFMADD_VF16_M1_MASK + {7, OperandInfo168}, // Inst #1500 = PseudoVFMADD_VF16_M2 + {7, OperandInfo169}, // Inst #1501 = PseudoVFMADD_VF16_M2_MASK + {7, OperandInfo170}, // Inst #1502 = PseudoVFMADD_VF16_M4 + {7, OperandInfo171}, // Inst #1503 = PseudoVFMADD_VF16_M4_MASK + {7, OperandInfo172}, // Inst #1504 = PseudoVFMADD_VF16_M8 + {7, OperandInfo173}, // Inst #1505 = PseudoVFMADD_VF16_M8_MASK + {7, OperandInfo166}, // Inst #1506 = PseudoVFMADD_VF16_MF2 + {7, OperandInfo167}, // Inst #1507 = PseudoVFMADD_VF16_MF2_MASK + {7, OperandInfo166}, // Inst #1508 = PseudoVFMADD_VF16_MF4 + {7, OperandInfo167}, // Inst #1509 = PseudoVFMADD_VF16_MF4_MASK + {7, OperandInfo166}, // Inst #1510 = PseudoVFMADD_VF16_MF8 + {7, OperandInfo167}, // Inst #1511 = PseudoVFMADD_VF16_MF8_MASK + {7, OperandInfo174}, // Inst #1512 = PseudoVFMADD_VF32_M1 + {7, OperandInfo175}, // Inst #1513 = PseudoVFMADD_VF32_M1_MASK + {7, OperandInfo176}, // Inst #1514 = PseudoVFMADD_VF32_M2 + {7, OperandInfo177}, // Inst #1515 = PseudoVFMADD_VF32_M2_MASK + {7, OperandInfo178}, // Inst #1516 = PseudoVFMADD_VF32_M4 + {7, OperandInfo179}, // Inst #1517 = PseudoVFMADD_VF32_M4_MASK + {7, OperandInfo180}, // Inst #1518 = PseudoVFMADD_VF32_M8 + {7, OperandInfo181}, // Inst #1519 = PseudoVFMADD_VF32_M8_MASK + {7, OperandInfo174}, // Inst #1520 = PseudoVFMADD_VF32_MF2 + {7, OperandInfo175}, // Inst #1521 = PseudoVFMADD_VF32_MF2_MASK + {7, OperandInfo174}, // Inst #1522 = PseudoVFMADD_VF32_MF4 + {7, OperandInfo175}, // Inst #1523 = PseudoVFMADD_VF32_MF4_MASK + {7, OperandInfo174}, // Inst #1524 = PseudoVFMADD_VF32_MF8 + {7, OperandInfo175}, // Inst #1525 = PseudoVFMADD_VF32_MF8_MASK + {7, OperandInfo182}, // Inst #1526 = PseudoVFMADD_VF64_M1 + {7, OperandInfo183}, // Inst #1527 = PseudoVFMADD_VF64_M1_MASK + {7, OperandInfo184}, // Inst #1528 = PseudoVFMADD_VF64_M2 + {7, OperandInfo185}, // Inst #1529 = PseudoVFMADD_VF64_M2_MASK + {7, OperandInfo186}, // Inst #1530 = PseudoVFMADD_VF64_M4 + {7, OperandInfo187}, // Inst #1531 = PseudoVFMADD_VF64_M4_MASK + {7, OperandInfo188}, // Inst #1532 = PseudoVFMADD_VF64_M8 + {7, OperandInfo189}, // Inst #1533 = PseudoVFMADD_VF64_M8_MASK + {7, OperandInfo182}, // Inst #1534 = PseudoVFMADD_VF64_MF2 + {7, OperandInfo183}, // Inst #1535 = PseudoVFMADD_VF64_MF2_MASK + {7, OperandInfo182}, // Inst #1536 = PseudoVFMADD_VF64_MF4 + {7, OperandInfo183}, // Inst #1537 = PseudoVFMADD_VF64_MF4_MASK + {7, OperandInfo182}, // Inst #1538 = PseudoVFMADD_VF64_MF8 + {7, OperandInfo183}, // Inst #1539 = PseudoVFMADD_VF64_MF8_MASK + {7, OperandInfo190}, // Inst #1540 = PseudoVFMADD_VV_M1 + {7, OperandInfo191}, // Inst #1541 = PseudoVFMADD_VV_M1_MASK + {7, OperandInfo192}, // Inst #1542 = PseudoVFMADD_VV_M2 + {7, OperandInfo193}, // Inst #1543 = PseudoVFMADD_VV_M2_MASK + {7, OperandInfo194}, // Inst #1544 = PseudoVFMADD_VV_M4 + {7, OperandInfo195}, // Inst #1545 = PseudoVFMADD_VV_M4_MASK + {7, OperandInfo196}, // Inst #1546 = PseudoVFMADD_VV_M8 + {7, OperandInfo197}, // Inst #1547 = PseudoVFMADD_VV_M8_MASK + {7, OperandInfo190}, // Inst #1548 = PseudoVFMADD_VV_MF2 + {7, OperandInfo191}, // Inst #1549 = PseudoVFMADD_VV_MF2_MASK + {7, OperandInfo190}, // Inst #1550 = PseudoVFMADD_VV_MF4 + {7, OperandInfo191}, // Inst #1551 = PseudoVFMADD_VV_MF4_MASK + {7, OperandInfo190}, // Inst #1552 = PseudoVFMADD_VV_MF8 + {7, OperandInfo191}, // Inst #1553 = PseudoVFMADD_VV_MF8_MASK + {5, OperandInfo130}, // Inst #1554 = PseudoVFMAX_VF16_M1 + {8, OperandInfo131}, // Inst #1555 = PseudoVFMAX_VF16_M1_MASK + {5, OperandInfo132}, // Inst #1556 = PseudoVFMAX_VF16_M2 + {8, OperandInfo133}, // Inst #1557 = PseudoVFMAX_VF16_M2_MASK + {5, OperandInfo134}, // Inst #1558 = PseudoVFMAX_VF16_M4 + {8, OperandInfo135}, // Inst #1559 = PseudoVFMAX_VF16_M4_MASK + {5, OperandInfo136}, // Inst #1560 = PseudoVFMAX_VF16_M8 + {8, OperandInfo137}, // Inst #1561 = PseudoVFMAX_VF16_M8_MASK + {5, OperandInfo130}, // Inst #1562 = PseudoVFMAX_VF16_MF2 + {8, OperandInfo131}, // Inst #1563 = PseudoVFMAX_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #1564 = PseudoVFMAX_VF16_MF4 + {8, OperandInfo131}, // Inst #1565 = PseudoVFMAX_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #1566 = PseudoVFMAX_VF16_MF8 + {8, OperandInfo131}, // Inst #1567 = PseudoVFMAX_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #1568 = PseudoVFMAX_VF32_M1 + {8, OperandInfo139}, // Inst #1569 = PseudoVFMAX_VF32_M1_MASK + {5, OperandInfo140}, // Inst #1570 = PseudoVFMAX_VF32_M2 + {8, OperandInfo141}, // Inst #1571 = PseudoVFMAX_VF32_M2_MASK + {5, OperandInfo142}, // Inst #1572 = PseudoVFMAX_VF32_M4 + {8, OperandInfo143}, // Inst #1573 = PseudoVFMAX_VF32_M4_MASK + {5, OperandInfo144}, // Inst #1574 = PseudoVFMAX_VF32_M8 + {8, OperandInfo145}, // Inst #1575 = PseudoVFMAX_VF32_M8_MASK + {5, OperandInfo138}, // Inst #1576 = PseudoVFMAX_VF32_MF2 + {8, OperandInfo139}, // Inst #1577 = PseudoVFMAX_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #1578 = PseudoVFMAX_VF32_MF4 + {8, OperandInfo139}, // Inst #1579 = PseudoVFMAX_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #1580 = PseudoVFMAX_VF32_MF8 + {8, OperandInfo139}, // Inst #1581 = PseudoVFMAX_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #1582 = PseudoVFMAX_VF64_M1 + {8, OperandInfo147}, // Inst #1583 = PseudoVFMAX_VF64_M1_MASK + {5, OperandInfo148}, // Inst #1584 = PseudoVFMAX_VF64_M2 + {8, OperandInfo149}, // Inst #1585 = PseudoVFMAX_VF64_M2_MASK + {5, OperandInfo150}, // Inst #1586 = PseudoVFMAX_VF64_M4 + {8, OperandInfo151}, // Inst #1587 = PseudoVFMAX_VF64_M4_MASK + {5, OperandInfo152}, // Inst #1588 = PseudoVFMAX_VF64_M8 + {8, OperandInfo153}, // Inst #1589 = PseudoVFMAX_VF64_M8_MASK + {5, OperandInfo146}, // Inst #1590 = PseudoVFMAX_VF64_MF2 + {8, OperandInfo147}, // Inst #1591 = PseudoVFMAX_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #1592 = PseudoVFMAX_VF64_MF4 + {8, OperandInfo147}, // Inst #1593 = PseudoVFMAX_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #1594 = PseudoVFMAX_VF64_MF8 + {8, OperandInfo147}, // Inst #1595 = PseudoVFMAX_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #1596 = PseudoVFMAX_VV_M1 + {8, OperandInfo63}, // Inst #1597 = PseudoVFMAX_VV_M1_MASK + {5, OperandInfo64}, // Inst #1598 = PseudoVFMAX_VV_M2 + {8, OperandInfo65}, // Inst #1599 = PseudoVFMAX_VV_M2_MASK + {5, OperandInfo66}, // Inst #1600 = PseudoVFMAX_VV_M4 + {8, OperandInfo67}, // Inst #1601 = PseudoVFMAX_VV_M4_MASK + {5, OperandInfo68}, // Inst #1602 = PseudoVFMAX_VV_M8 + {8, OperandInfo69}, // Inst #1603 = PseudoVFMAX_VV_M8_MASK + {5, OperandInfo62}, // Inst #1604 = PseudoVFMAX_VV_MF2 + {8, OperandInfo63}, // Inst #1605 = PseudoVFMAX_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1606 = PseudoVFMAX_VV_MF4 + {8, OperandInfo63}, // Inst #1607 = PseudoVFMAX_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1608 = PseudoVFMAX_VV_MF8 + {8, OperandInfo63}, // Inst #1609 = PseudoVFMAX_VV_MF8_MASK + {6, OperandInfo198}, // Inst #1610 = PseudoVFMERGE_VF16M_M1 + {6, OperandInfo199}, // Inst #1611 = PseudoVFMERGE_VF16M_M2 + {6, OperandInfo200}, // Inst #1612 = PseudoVFMERGE_VF16M_M4 + {6, OperandInfo201}, // Inst #1613 = PseudoVFMERGE_VF16M_M8 + {6, OperandInfo198}, // Inst #1614 = PseudoVFMERGE_VF16M_MF2 + {6, OperandInfo198}, // Inst #1615 = PseudoVFMERGE_VF16M_MF4 + {6, OperandInfo198}, // Inst #1616 = PseudoVFMERGE_VF16M_MF8 + {6, OperandInfo202}, // Inst #1617 = PseudoVFMERGE_VF32M_M1 + {6, OperandInfo203}, // Inst #1618 = PseudoVFMERGE_VF32M_M2 + {6, OperandInfo204}, // Inst #1619 = PseudoVFMERGE_VF32M_M4 + {6, OperandInfo205}, // Inst #1620 = PseudoVFMERGE_VF32M_M8 + {6, OperandInfo202}, // Inst #1621 = PseudoVFMERGE_VF32M_MF2 + {6, OperandInfo202}, // Inst #1622 = PseudoVFMERGE_VF32M_MF4 + {6, OperandInfo202}, // Inst #1623 = PseudoVFMERGE_VF32M_MF8 + {6, OperandInfo206}, // Inst #1624 = PseudoVFMERGE_VF64M_M1 + {6, OperandInfo207}, // Inst #1625 = PseudoVFMERGE_VF64M_M2 + {6, OperandInfo208}, // Inst #1626 = PseudoVFMERGE_VF64M_M4 + {6, OperandInfo209}, // Inst #1627 = PseudoVFMERGE_VF64M_M8 + {6, OperandInfo206}, // Inst #1628 = PseudoVFMERGE_VF64M_MF2 + {6, OperandInfo206}, // Inst #1629 = PseudoVFMERGE_VF64M_MF4 + {6, OperandInfo206}, // Inst #1630 = PseudoVFMERGE_VF64M_MF8 + {5, OperandInfo130}, // Inst #1631 = PseudoVFMIN_VF16_M1 + {8, OperandInfo131}, // Inst #1632 = PseudoVFMIN_VF16_M1_MASK + {5, OperandInfo132}, // Inst #1633 = PseudoVFMIN_VF16_M2 + {8, OperandInfo133}, // Inst #1634 = PseudoVFMIN_VF16_M2_MASK + {5, OperandInfo134}, // Inst #1635 = PseudoVFMIN_VF16_M4 + {8, OperandInfo135}, // Inst #1636 = PseudoVFMIN_VF16_M4_MASK + {5, OperandInfo136}, // Inst #1637 = PseudoVFMIN_VF16_M8 + {8, OperandInfo137}, // Inst #1638 = PseudoVFMIN_VF16_M8_MASK + {5, OperandInfo130}, // Inst #1639 = PseudoVFMIN_VF16_MF2 + {8, OperandInfo131}, // Inst #1640 = PseudoVFMIN_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #1641 = PseudoVFMIN_VF16_MF4 + {8, OperandInfo131}, // Inst #1642 = PseudoVFMIN_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #1643 = PseudoVFMIN_VF16_MF8 + {8, OperandInfo131}, // Inst #1644 = PseudoVFMIN_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #1645 = PseudoVFMIN_VF32_M1 + {8, OperandInfo139}, // Inst #1646 = PseudoVFMIN_VF32_M1_MASK + {5, OperandInfo140}, // Inst #1647 = PseudoVFMIN_VF32_M2 + {8, OperandInfo141}, // Inst #1648 = PseudoVFMIN_VF32_M2_MASK + {5, OperandInfo142}, // Inst #1649 = PseudoVFMIN_VF32_M4 + {8, OperandInfo143}, // Inst #1650 = PseudoVFMIN_VF32_M4_MASK + {5, OperandInfo144}, // Inst #1651 = PseudoVFMIN_VF32_M8 + {8, OperandInfo145}, // Inst #1652 = PseudoVFMIN_VF32_M8_MASK + {5, OperandInfo138}, // Inst #1653 = PseudoVFMIN_VF32_MF2 + {8, OperandInfo139}, // Inst #1654 = PseudoVFMIN_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #1655 = PseudoVFMIN_VF32_MF4 + {8, OperandInfo139}, // Inst #1656 = PseudoVFMIN_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #1657 = PseudoVFMIN_VF32_MF8 + {8, OperandInfo139}, // Inst #1658 = PseudoVFMIN_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #1659 = PseudoVFMIN_VF64_M1 + {8, OperandInfo147}, // Inst #1660 = PseudoVFMIN_VF64_M1_MASK + {5, OperandInfo148}, // Inst #1661 = PseudoVFMIN_VF64_M2 + {8, OperandInfo149}, // Inst #1662 = PseudoVFMIN_VF64_M2_MASK + {5, OperandInfo150}, // Inst #1663 = PseudoVFMIN_VF64_M4 + {8, OperandInfo151}, // Inst #1664 = PseudoVFMIN_VF64_M4_MASK + {5, OperandInfo152}, // Inst #1665 = PseudoVFMIN_VF64_M8 + {8, OperandInfo153}, // Inst #1666 = PseudoVFMIN_VF64_M8_MASK + {5, OperandInfo146}, // Inst #1667 = PseudoVFMIN_VF64_MF2 + {8, OperandInfo147}, // Inst #1668 = PseudoVFMIN_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #1669 = PseudoVFMIN_VF64_MF4 + {8, OperandInfo147}, // Inst #1670 = PseudoVFMIN_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #1671 = PseudoVFMIN_VF64_MF8 + {8, OperandInfo147}, // Inst #1672 = PseudoVFMIN_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #1673 = PseudoVFMIN_VV_M1 + {8, OperandInfo63}, // Inst #1674 = PseudoVFMIN_VV_M1_MASK + {5, OperandInfo64}, // Inst #1675 = PseudoVFMIN_VV_M2 + {8, OperandInfo65}, // Inst #1676 = PseudoVFMIN_VV_M2_MASK + {5, OperandInfo66}, // Inst #1677 = PseudoVFMIN_VV_M4 + {8, OperandInfo67}, // Inst #1678 = PseudoVFMIN_VV_M4_MASK + {5, OperandInfo68}, // Inst #1679 = PseudoVFMIN_VV_M8 + {8, OperandInfo69}, // Inst #1680 = PseudoVFMIN_VV_M8_MASK + {5, OperandInfo62}, // Inst #1681 = PseudoVFMIN_VV_MF2 + {8, OperandInfo63}, // Inst #1682 = PseudoVFMIN_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1683 = PseudoVFMIN_VV_MF4 + {8, OperandInfo63}, // Inst #1684 = PseudoVFMIN_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1685 = PseudoVFMIN_VV_MF8 + {8, OperandInfo63}, // Inst #1686 = PseudoVFMIN_VV_MF8_MASK + {7, OperandInfo166}, // Inst #1687 = PseudoVFMSAC_VF16_M1 + {7, OperandInfo167}, // Inst #1688 = PseudoVFMSAC_VF16_M1_MASK + {7, OperandInfo168}, // Inst #1689 = PseudoVFMSAC_VF16_M2 + {7, OperandInfo169}, // Inst #1690 = PseudoVFMSAC_VF16_M2_MASK + {7, OperandInfo170}, // Inst #1691 = PseudoVFMSAC_VF16_M4 + {7, OperandInfo171}, // Inst #1692 = PseudoVFMSAC_VF16_M4_MASK + {7, OperandInfo172}, // Inst #1693 = PseudoVFMSAC_VF16_M8 + {7, OperandInfo173}, // Inst #1694 = PseudoVFMSAC_VF16_M8_MASK + {7, OperandInfo166}, // Inst #1695 = PseudoVFMSAC_VF16_MF2 + {7, OperandInfo167}, // Inst #1696 = PseudoVFMSAC_VF16_MF2_MASK + {7, OperandInfo166}, // Inst #1697 = PseudoVFMSAC_VF16_MF4 + {7, OperandInfo167}, // Inst #1698 = PseudoVFMSAC_VF16_MF4_MASK + {7, OperandInfo166}, // Inst #1699 = PseudoVFMSAC_VF16_MF8 + {7, OperandInfo167}, // Inst #1700 = PseudoVFMSAC_VF16_MF8_MASK + {7, OperandInfo174}, // Inst #1701 = PseudoVFMSAC_VF32_M1 + {7, OperandInfo175}, // Inst #1702 = PseudoVFMSAC_VF32_M1_MASK + {7, OperandInfo176}, // Inst #1703 = PseudoVFMSAC_VF32_M2 + {7, OperandInfo177}, // Inst #1704 = PseudoVFMSAC_VF32_M2_MASK + {7, OperandInfo178}, // Inst #1705 = PseudoVFMSAC_VF32_M4 + {7, OperandInfo179}, // Inst #1706 = PseudoVFMSAC_VF32_M4_MASK + {7, OperandInfo180}, // Inst #1707 = PseudoVFMSAC_VF32_M8 + {7, OperandInfo181}, // Inst #1708 = PseudoVFMSAC_VF32_M8_MASK + {7, OperandInfo174}, // Inst #1709 = PseudoVFMSAC_VF32_MF2 + {7, OperandInfo175}, // Inst #1710 = PseudoVFMSAC_VF32_MF2_MASK + {7, OperandInfo174}, // Inst #1711 = PseudoVFMSAC_VF32_MF4 + {7, OperandInfo175}, // Inst #1712 = PseudoVFMSAC_VF32_MF4_MASK + {7, OperandInfo174}, // Inst #1713 = PseudoVFMSAC_VF32_MF8 + {7, OperandInfo175}, // Inst #1714 = PseudoVFMSAC_VF32_MF8_MASK + {7, OperandInfo182}, // Inst #1715 = PseudoVFMSAC_VF64_M1 + {7, OperandInfo183}, // Inst #1716 = PseudoVFMSAC_VF64_M1_MASK + {7, OperandInfo184}, // Inst #1717 = PseudoVFMSAC_VF64_M2 + {7, OperandInfo185}, // Inst #1718 = PseudoVFMSAC_VF64_M2_MASK + {7, OperandInfo186}, // Inst #1719 = PseudoVFMSAC_VF64_M4 + {7, OperandInfo187}, // Inst #1720 = PseudoVFMSAC_VF64_M4_MASK + {7, OperandInfo188}, // Inst #1721 = PseudoVFMSAC_VF64_M8 + {7, OperandInfo189}, // Inst #1722 = PseudoVFMSAC_VF64_M8_MASK + {7, OperandInfo182}, // Inst #1723 = PseudoVFMSAC_VF64_MF2 + {7, OperandInfo183}, // Inst #1724 = PseudoVFMSAC_VF64_MF2_MASK + {7, OperandInfo182}, // Inst #1725 = PseudoVFMSAC_VF64_MF4 + {7, OperandInfo183}, // Inst #1726 = PseudoVFMSAC_VF64_MF4_MASK + {7, OperandInfo182}, // Inst #1727 = PseudoVFMSAC_VF64_MF8 + {7, OperandInfo183}, // Inst #1728 = PseudoVFMSAC_VF64_MF8_MASK + {7, OperandInfo190}, // Inst #1729 = PseudoVFMSAC_VV_M1 + {7, OperandInfo191}, // Inst #1730 = PseudoVFMSAC_VV_M1_MASK + {7, OperandInfo192}, // Inst #1731 = PseudoVFMSAC_VV_M2 + {7, OperandInfo193}, // Inst #1732 = PseudoVFMSAC_VV_M2_MASK + {7, OperandInfo194}, // Inst #1733 = PseudoVFMSAC_VV_M4 + {7, OperandInfo195}, // Inst #1734 = PseudoVFMSAC_VV_M4_MASK + {7, OperandInfo196}, // Inst #1735 = PseudoVFMSAC_VV_M8 + {7, OperandInfo197}, // Inst #1736 = PseudoVFMSAC_VV_M8_MASK + {7, OperandInfo190}, // Inst #1737 = PseudoVFMSAC_VV_MF2 + {7, OperandInfo191}, // Inst #1738 = PseudoVFMSAC_VV_MF2_MASK + {7, OperandInfo190}, // Inst #1739 = PseudoVFMSAC_VV_MF4 + {7, OperandInfo191}, // Inst #1740 = PseudoVFMSAC_VV_MF4_MASK + {7, OperandInfo190}, // Inst #1741 = PseudoVFMSAC_VV_MF8 + {7, OperandInfo191}, // Inst #1742 = PseudoVFMSAC_VV_MF8_MASK + {7, OperandInfo166}, // Inst #1743 = PseudoVFMSUB_VF16_M1 + {7, OperandInfo167}, // Inst #1744 = PseudoVFMSUB_VF16_M1_MASK + {7, OperandInfo168}, // Inst #1745 = PseudoVFMSUB_VF16_M2 + {7, OperandInfo169}, // Inst #1746 = PseudoVFMSUB_VF16_M2_MASK + {7, OperandInfo170}, // Inst #1747 = PseudoVFMSUB_VF16_M4 + {7, OperandInfo171}, // Inst #1748 = PseudoVFMSUB_VF16_M4_MASK + {7, OperandInfo172}, // Inst #1749 = PseudoVFMSUB_VF16_M8 + {7, OperandInfo173}, // Inst #1750 = PseudoVFMSUB_VF16_M8_MASK + {7, OperandInfo166}, // Inst #1751 = PseudoVFMSUB_VF16_MF2 + {7, OperandInfo167}, // Inst #1752 = PseudoVFMSUB_VF16_MF2_MASK + {7, OperandInfo166}, // Inst #1753 = PseudoVFMSUB_VF16_MF4 + {7, OperandInfo167}, // Inst #1754 = PseudoVFMSUB_VF16_MF4_MASK + {7, OperandInfo166}, // Inst #1755 = PseudoVFMSUB_VF16_MF8 + {7, OperandInfo167}, // Inst #1756 = PseudoVFMSUB_VF16_MF8_MASK + {7, OperandInfo174}, // Inst #1757 = PseudoVFMSUB_VF32_M1 + {7, OperandInfo175}, // Inst #1758 = PseudoVFMSUB_VF32_M1_MASK + {7, OperandInfo176}, // Inst #1759 = PseudoVFMSUB_VF32_M2 + {7, OperandInfo177}, // Inst #1760 = PseudoVFMSUB_VF32_M2_MASK + {7, OperandInfo178}, // Inst #1761 = PseudoVFMSUB_VF32_M4 + {7, OperandInfo179}, // Inst #1762 = PseudoVFMSUB_VF32_M4_MASK + {7, OperandInfo180}, // Inst #1763 = PseudoVFMSUB_VF32_M8 + {7, OperandInfo181}, // Inst #1764 = PseudoVFMSUB_VF32_M8_MASK + {7, OperandInfo174}, // Inst #1765 = PseudoVFMSUB_VF32_MF2 + {7, OperandInfo175}, // Inst #1766 = PseudoVFMSUB_VF32_MF2_MASK + {7, OperandInfo174}, // Inst #1767 = PseudoVFMSUB_VF32_MF4 + {7, OperandInfo175}, // Inst #1768 = PseudoVFMSUB_VF32_MF4_MASK + {7, OperandInfo174}, // Inst #1769 = PseudoVFMSUB_VF32_MF8 + {7, OperandInfo175}, // Inst #1770 = PseudoVFMSUB_VF32_MF8_MASK + {7, OperandInfo182}, // Inst #1771 = PseudoVFMSUB_VF64_M1 + {7, OperandInfo183}, // Inst #1772 = PseudoVFMSUB_VF64_M1_MASK + {7, OperandInfo184}, // Inst #1773 = PseudoVFMSUB_VF64_M2 + {7, OperandInfo185}, // Inst #1774 = PseudoVFMSUB_VF64_M2_MASK + {7, OperandInfo186}, // Inst #1775 = PseudoVFMSUB_VF64_M4 + {7, OperandInfo187}, // Inst #1776 = PseudoVFMSUB_VF64_M4_MASK + {7, OperandInfo188}, // Inst #1777 = PseudoVFMSUB_VF64_M8 + {7, OperandInfo189}, // Inst #1778 = PseudoVFMSUB_VF64_M8_MASK + {7, OperandInfo182}, // Inst #1779 = PseudoVFMSUB_VF64_MF2 + {7, OperandInfo183}, // Inst #1780 = PseudoVFMSUB_VF64_MF2_MASK + {7, OperandInfo182}, // Inst #1781 = PseudoVFMSUB_VF64_MF4 + {7, OperandInfo183}, // Inst #1782 = PseudoVFMSUB_VF64_MF4_MASK + {7, OperandInfo182}, // Inst #1783 = PseudoVFMSUB_VF64_MF8 + {7, OperandInfo183}, // Inst #1784 = PseudoVFMSUB_VF64_MF8_MASK + {7, OperandInfo190}, // Inst #1785 = PseudoVFMSUB_VV_M1 + {7, OperandInfo191}, // Inst #1786 = PseudoVFMSUB_VV_M1_MASK + {7, OperandInfo192}, // Inst #1787 = PseudoVFMSUB_VV_M2 + {7, OperandInfo193}, // Inst #1788 = PseudoVFMSUB_VV_M2_MASK + {7, OperandInfo194}, // Inst #1789 = PseudoVFMSUB_VV_M4 + {7, OperandInfo195}, // Inst #1790 = PseudoVFMSUB_VV_M4_MASK + {7, OperandInfo196}, // Inst #1791 = PseudoVFMSUB_VV_M8 + {7, OperandInfo197}, // Inst #1792 = PseudoVFMSUB_VV_M8_MASK + {7, OperandInfo190}, // Inst #1793 = PseudoVFMSUB_VV_MF2 + {7, OperandInfo191}, // Inst #1794 = PseudoVFMSUB_VV_MF2_MASK + {7, OperandInfo190}, // Inst #1795 = PseudoVFMSUB_VV_MF4 + {7, OperandInfo191}, // Inst #1796 = PseudoVFMSUB_VV_MF4_MASK + {7, OperandInfo190}, // Inst #1797 = PseudoVFMSUB_VV_MF8 + {7, OperandInfo191}, // Inst #1798 = PseudoVFMSUB_VV_MF8_MASK + {5, OperandInfo130}, // Inst #1799 = PseudoVFMUL_VF16_M1 + {8, OperandInfo131}, // Inst #1800 = PseudoVFMUL_VF16_M1_MASK + {5, OperandInfo132}, // Inst #1801 = PseudoVFMUL_VF16_M2 + {8, OperandInfo133}, // Inst #1802 = PseudoVFMUL_VF16_M2_MASK + {5, OperandInfo134}, // Inst #1803 = PseudoVFMUL_VF16_M4 + {8, OperandInfo135}, // Inst #1804 = PseudoVFMUL_VF16_M4_MASK + {5, OperandInfo136}, // Inst #1805 = PseudoVFMUL_VF16_M8 + {8, OperandInfo137}, // Inst #1806 = PseudoVFMUL_VF16_M8_MASK + {5, OperandInfo130}, // Inst #1807 = PseudoVFMUL_VF16_MF2 + {8, OperandInfo131}, // Inst #1808 = PseudoVFMUL_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #1809 = PseudoVFMUL_VF16_MF4 + {8, OperandInfo131}, // Inst #1810 = PseudoVFMUL_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #1811 = PseudoVFMUL_VF16_MF8 + {8, OperandInfo131}, // Inst #1812 = PseudoVFMUL_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #1813 = PseudoVFMUL_VF32_M1 + {8, OperandInfo139}, // Inst #1814 = PseudoVFMUL_VF32_M1_MASK + {5, OperandInfo140}, // Inst #1815 = PseudoVFMUL_VF32_M2 + {8, OperandInfo141}, // Inst #1816 = PseudoVFMUL_VF32_M2_MASK + {5, OperandInfo142}, // Inst #1817 = PseudoVFMUL_VF32_M4 + {8, OperandInfo143}, // Inst #1818 = PseudoVFMUL_VF32_M4_MASK + {5, OperandInfo144}, // Inst #1819 = PseudoVFMUL_VF32_M8 + {8, OperandInfo145}, // Inst #1820 = PseudoVFMUL_VF32_M8_MASK + {5, OperandInfo138}, // Inst #1821 = PseudoVFMUL_VF32_MF2 + {8, OperandInfo139}, // Inst #1822 = PseudoVFMUL_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #1823 = PseudoVFMUL_VF32_MF4 + {8, OperandInfo139}, // Inst #1824 = PseudoVFMUL_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #1825 = PseudoVFMUL_VF32_MF8 + {8, OperandInfo139}, // Inst #1826 = PseudoVFMUL_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #1827 = PseudoVFMUL_VF64_M1 + {8, OperandInfo147}, // Inst #1828 = PseudoVFMUL_VF64_M1_MASK + {5, OperandInfo148}, // Inst #1829 = PseudoVFMUL_VF64_M2 + {8, OperandInfo149}, // Inst #1830 = PseudoVFMUL_VF64_M2_MASK + {5, OperandInfo150}, // Inst #1831 = PseudoVFMUL_VF64_M4 + {8, OperandInfo151}, // Inst #1832 = PseudoVFMUL_VF64_M4_MASK + {5, OperandInfo152}, // Inst #1833 = PseudoVFMUL_VF64_M8 + {8, OperandInfo153}, // Inst #1834 = PseudoVFMUL_VF64_M8_MASK + {5, OperandInfo146}, // Inst #1835 = PseudoVFMUL_VF64_MF2 + {8, OperandInfo147}, // Inst #1836 = PseudoVFMUL_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #1837 = PseudoVFMUL_VF64_MF4 + {8, OperandInfo147}, // Inst #1838 = PseudoVFMUL_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #1839 = PseudoVFMUL_VF64_MF8 + {8, OperandInfo147}, // Inst #1840 = PseudoVFMUL_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #1841 = PseudoVFMUL_VV_M1 + {8, OperandInfo63}, // Inst #1842 = PseudoVFMUL_VV_M1_MASK + {5, OperandInfo64}, // Inst #1843 = PseudoVFMUL_VV_M2 + {8, OperandInfo65}, // Inst #1844 = PseudoVFMUL_VV_M2_MASK + {5, OperandInfo66}, // Inst #1845 = PseudoVFMUL_VV_M4 + {8, OperandInfo67}, // Inst #1846 = PseudoVFMUL_VV_M4_MASK + {5, OperandInfo68}, // Inst #1847 = PseudoVFMUL_VV_M8 + {8, OperandInfo69}, // Inst #1848 = PseudoVFMUL_VV_M8_MASK + {5, OperandInfo62}, // Inst #1849 = PseudoVFMUL_VV_MF2 + {8, OperandInfo63}, // Inst #1850 = PseudoVFMUL_VV_MF2_MASK + {5, OperandInfo62}, // Inst #1851 = PseudoVFMUL_VV_MF4 + {8, OperandInfo63}, // Inst #1852 = PseudoVFMUL_VV_MF4_MASK + {5, OperandInfo62}, // Inst #1853 = PseudoVFMUL_VV_MF8 + {8, OperandInfo63}, // Inst #1854 = PseudoVFMUL_VV_MF8_MASK + {3, OperandInfo210}, // Inst #1855 = PseudoVFMV_F16_S_M1 + {3, OperandInfo211}, // Inst #1856 = PseudoVFMV_F16_S_M2 + {3, OperandInfo212}, // Inst #1857 = PseudoVFMV_F16_S_M4 + {3, OperandInfo213}, // Inst #1858 = PseudoVFMV_F16_S_M8 + {3, OperandInfo210}, // Inst #1859 = PseudoVFMV_F16_S_MF2 + {3, OperandInfo210}, // Inst #1860 = PseudoVFMV_F16_S_MF4 + {3, OperandInfo210}, // Inst #1861 = PseudoVFMV_F16_S_MF8 + {3, OperandInfo214}, // Inst #1862 = PseudoVFMV_F32_S_M1 + {3, OperandInfo215}, // Inst #1863 = PseudoVFMV_F32_S_M2 + {3, OperandInfo216}, // Inst #1864 = PseudoVFMV_F32_S_M4 + {3, OperandInfo217}, // Inst #1865 = PseudoVFMV_F32_S_M8 + {3, OperandInfo214}, // Inst #1866 = PseudoVFMV_F32_S_MF2 + {3, OperandInfo214}, // Inst #1867 = PseudoVFMV_F32_S_MF4 + {3, OperandInfo214}, // Inst #1868 = PseudoVFMV_F32_S_MF8 + {3, OperandInfo218}, // Inst #1869 = PseudoVFMV_F64_S_M1 + {3, OperandInfo219}, // Inst #1870 = PseudoVFMV_F64_S_M2 + {3, OperandInfo220}, // Inst #1871 = PseudoVFMV_F64_S_M4 + {3, OperandInfo221}, // Inst #1872 = PseudoVFMV_F64_S_M8 + {3, OperandInfo218}, // Inst #1873 = PseudoVFMV_F64_S_MF2 + {3, OperandInfo218}, // Inst #1874 = PseudoVFMV_F64_S_MF4 + {3, OperandInfo218}, // Inst #1875 = PseudoVFMV_F64_S_MF8 + {5, OperandInfo222}, // Inst #1876 = PseudoVFMV_S_F16_M1 + {5, OperandInfo223}, // Inst #1877 = PseudoVFMV_S_F16_M2 + {5, OperandInfo224}, // Inst #1878 = PseudoVFMV_S_F16_M4 + {5, OperandInfo225}, // Inst #1879 = PseudoVFMV_S_F16_M8 + {5, OperandInfo222}, // Inst #1880 = PseudoVFMV_S_F16_MF2 + {5, OperandInfo222}, // Inst #1881 = PseudoVFMV_S_F16_MF4 + {5, OperandInfo222}, // Inst #1882 = PseudoVFMV_S_F16_MF8 + {5, OperandInfo226}, // Inst #1883 = PseudoVFMV_S_F32_M1 + {5, OperandInfo227}, // Inst #1884 = PseudoVFMV_S_F32_M2 + {5, OperandInfo228}, // Inst #1885 = PseudoVFMV_S_F32_M4 + {5, OperandInfo229}, // Inst #1886 = PseudoVFMV_S_F32_M8 + {5, OperandInfo226}, // Inst #1887 = PseudoVFMV_S_F32_MF2 + {5, OperandInfo226}, // Inst #1888 = PseudoVFMV_S_F32_MF4 + {5, OperandInfo226}, // Inst #1889 = PseudoVFMV_S_F32_MF8 + {5, OperandInfo230}, // Inst #1890 = PseudoVFMV_S_F64_M1 + {5, OperandInfo231}, // Inst #1891 = PseudoVFMV_S_F64_M2 + {5, OperandInfo232}, // Inst #1892 = PseudoVFMV_S_F64_M4 + {5, OperandInfo233}, // Inst #1893 = PseudoVFMV_S_F64_M8 + {5, OperandInfo230}, // Inst #1894 = PseudoVFMV_S_F64_MF2 + {5, OperandInfo230}, // Inst #1895 = PseudoVFMV_S_F64_MF4 + {5, OperandInfo230}, // Inst #1896 = PseudoVFMV_S_F64_MF8 + {4, OperandInfo234}, // Inst #1897 = PseudoVFMV_V_F16_M1 + {4, OperandInfo235}, // Inst #1898 = PseudoVFMV_V_F16_M2 + {4, OperandInfo236}, // Inst #1899 = PseudoVFMV_V_F16_M4 + {4, OperandInfo237}, // Inst #1900 = PseudoVFMV_V_F16_M8 + {4, OperandInfo234}, // Inst #1901 = PseudoVFMV_V_F16_MF2 + {4, OperandInfo234}, // Inst #1902 = PseudoVFMV_V_F16_MF4 + {4, OperandInfo234}, // Inst #1903 = PseudoVFMV_V_F16_MF8 + {4, OperandInfo238}, // Inst #1904 = PseudoVFMV_V_F32_M1 + {4, OperandInfo239}, // Inst #1905 = PseudoVFMV_V_F32_M2 + {4, OperandInfo240}, // Inst #1906 = PseudoVFMV_V_F32_M4 + {4, OperandInfo241}, // Inst #1907 = PseudoVFMV_V_F32_M8 + {4, OperandInfo238}, // Inst #1908 = PseudoVFMV_V_F32_MF2 + {4, OperandInfo238}, // Inst #1909 = PseudoVFMV_V_F32_MF4 + {4, OperandInfo238}, // Inst #1910 = PseudoVFMV_V_F32_MF8 + {4, OperandInfo242}, // Inst #1911 = PseudoVFMV_V_F64_M1 + {4, OperandInfo243}, // Inst #1912 = PseudoVFMV_V_F64_M2 + {4, OperandInfo244}, // Inst #1913 = PseudoVFMV_V_F64_M4 + {4, OperandInfo245}, // Inst #1914 = PseudoVFMV_V_F64_M8 + {4, OperandInfo242}, // Inst #1915 = PseudoVFMV_V_F64_MF2 + {4, OperandInfo242}, // Inst #1916 = PseudoVFMV_V_F64_MF4 + {4, OperandInfo242}, // Inst #1917 = PseudoVFMV_V_F64_MF8 + {4, OperandInfo246}, // Inst #1918 = PseudoVFNCVT_F_F_W_M1 + {7, OperandInfo247}, // Inst #1919 = PseudoVFNCVT_F_F_W_M1_MASK + {4, OperandInfo248}, // Inst #1920 = PseudoVFNCVT_F_F_W_M2 + {7, OperandInfo249}, // Inst #1921 = PseudoVFNCVT_F_F_W_M2_MASK + {4, OperandInfo250}, // Inst #1922 = PseudoVFNCVT_F_F_W_M4 + {7, OperandInfo251}, // Inst #1923 = PseudoVFNCVT_F_F_W_M4_MASK + {4, OperandInfo252}, // Inst #1924 = PseudoVFNCVT_F_F_W_MF2 + {7, OperandInfo253}, // Inst #1925 = PseudoVFNCVT_F_F_W_MF2_MASK + {4, OperandInfo252}, // Inst #1926 = PseudoVFNCVT_F_F_W_MF4 + {7, OperandInfo253}, // Inst #1927 = PseudoVFNCVT_F_F_W_MF4_MASK + {4, OperandInfo252}, // Inst #1928 = PseudoVFNCVT_F_F_W_MF8 + {7, OperandInfo253}, // Inst #1929 = PseudoVFNCVT_F_F_W_MF8_MASK + {4, OperandInfo246}, // Inst #1930 = PseudoVFNCVT_F_XU_W_M1 + {7, OperandInfo247}, // Inst #1931 = PseudoVFNCVT_F_XU_W_M1_MASK + {4, OperandInfo248}, // Inst #1932 = PseudoVFNCVT_F_XU_W_M2 + {7, OperandInfo249}, // Inst #1933 = PseudoVFNCVT_F_XU_W_M2_MASK + {4, OperandInfo250}, // Inst #1934 = PseudoVFNCVT_F_XU_W_M4 + {7, OperandInfo251}, // Inst #1935 = PseudoVFNCVT_F_XU_W_M4_MASK + {4, OperandInfo252}, // Inst #1936 = PseudoVFNCVT_F_XU_W_MF2 + {7, OperandInfo253}, // Inst #1937 = PseudoVFNCVT_F_XU_W_MF2_MASK + {4, OperandInfo252}, // Inst #1938 = PseudoVFNCVT_F_XU_W_MF4 + {7, OperandInfo253}, // Inst #1939 = PseudoVFNCVT_F_XU_W_MF4_MASK + {4, OperandInfo252}, // Inst #1940 = PseudoVFNCVT_F_XU_W_MF8 + {7, OperandInfo253}, // Inst #1941 = PseudoVFNCVT_F_XU_W_MF8_MASK + {4, OperandInfo246}, // Inst #1942 = PseudoVFNCVT_F_X_W_M1 + {7, OperandInfo247}, // Inst #1943 = PseudoVFNCVT_F_X_W_M1_MASK + {4, OperandInfo248}, // Inst #1944 = PseudoVFNCVT_F_X_W_M2 + {7, OperandInfo249}, // Inst #1945 = PseudoVFNCVT_F_X_W_M2_MASK + {4, OperandInfo250}, // Inst #1946 = PseudoVFNCVT_F_X_W_M4 + {7, OperandInfo251}, // Inst #1947 = PseudoVFNCVT_F_X_W_M4_MASK + {4, OperandInfo252}, // Inst #1948 = PseudoVFNCVT_F_X_W_MF2 + {7, OperandInfo253}, // Inst #1949 = PseudoVFNCVT_F_X_W_MF2_MASK + {4, OperandInfo252}, // Inst #1950 = PseudoVFNCVT_F_X_W_MF4 + {7, OperandInfo253}, // Inst #1951 = PseudoVFNCVT_F_X_W_MF4_MASK + {4, OperandInfo252}, // Inst #1952 = PseudoVFNCVT_F_X_W_MF8 + {7, OperandInfo253}, // Inst #1953 = PseudoVFNCVT_F_X_W_MF8_MASK + {4, OperandInfo246}, // Inst #1954 = PseudoVFNCVT_ROD_F_F_W_M1 + {7, OperandInfo247}, // Inst #1955 = PseudoVFNCVT_ROD_F_F_W_M1_MASK + {4, OperandInfo248}, // Inst #1956 = PseudoVFNCVT_ROD_F_F_W_M2 + {7, OperandInfo249}, // Inst #1957 = PseudoVFNCVT_ROD_F_F_W_M2_MASK + {4, OperandInfo250}, // Inst #1958 = PseudoVFNCVT_ROD_F_F_W_M4 + {7, OperandInfo251}, // Inst #1959 = PseudoVFNCVT_ROD_F_F_W_M4_MASK + {4, OperandInfo252}, // Inst #1960 = PseudoVFNCVT_ROD_F_F_W_MF2 + {7, OperandInfo253}, // Inst #1961 = PseudoVFNCVT_ROD_F_F_W_MF2_MASK + {4, OperandInfo252}, // Inst #1962 = PseudoVFNCVT_ROD_F_F_W_MF4 + {7, OperandInfo253}, // Inst #1963 = PseudoVFNCVT_ROD_F_F_W_MF4_MASK + {4, OperandInfo252}, // Inst #1964 = PseudoVFNCVT_ROD_F_F_W_MF8 + {7, OperandInfo253}, // Inst #1965 = PseudoVFNCVT_ROD_F_F_W_MF8_MASK + {4, OperandInfo246}, // Inst #1966 = PseudoVFNCVT_RTZ_XU_F_W_M1 + {7, OperandInfo247}, // Inst #1967 = PseudoVFNCVT_RTZ_XU_F_W_M1_MASK + {4, OperandInfo248}, // Inst #1968 = PseudoVFNCVT_RTZ_XU_F_W_M2 + {7, OperandInfo249}, // Inst #1969 = PseudoVFNCVT_RTZ_XU_F_W_M2_MASK + {4, OperandInfo250}, // Inst #1970 = PseudoVFNCVT_RTZ_XU_F_W_M4 + {7, OperandInfo251}, // Inst #1971 = PseudoVFNCVT_RTZ_XU_F_W_M4_MASK + {4, OperandInfo252}, // Inst #1972 = PseudoVFNCVT_RTZ_XU_F_W_MF2 + {7, OperandInfo253}, // Inst #1973 = PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK + {4, OperandInfo252}, // Inst #1974 = PseudoVFNCVT_RTZ_XU_F_W_MF4 + {7, OperandInfo253}, // Inst #1975 = PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK + {4, OperandInfo252}, // Inst #1976 = PseudoVFNCVT_RTZ_XU_F_W_MF8 + {7, OperandInfo253}, // Inst #1977 = PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK + {4, OperandInfo246}, // Inst #1978 = PseudoVFNCVT_RTZ_X_F_W_M1 + {7, OperandInfo247}, // Inst #1979 = PseudoVFNCVT_RTZ_X_F_W_M1_MASK + {4, OperandInfo248}, // Inst #1980 = PseudoVFNCVT_RTZ_X_F_W_M2 + {7, OperandInfo249}, // Inst #1981 = PseudoVFNCVT_RTZ_X_F_W_M2_MASK + {4, OperandInfo250}, // Inst #1982 = PseudoVFNCVT_RTZ_X_F_W_M4 + {7, OperandInfo251}, // Inst #1983 = PseudoVFNCVT_RTZ_X_F_W_M4_MASK + {4, OperandInfo252}, // Inst #1984 = PseudoVFNCVT_RTZ_X_F_W_MF2 + {7, OperandInfo253}, // Inst #1985 = PseudoVFNCVT_RTZ_X_F_W_MF2_MASK + {4, OperandInfo252}, // Inst #1986 = PseudoVFNCVT_RTZ_X_F_W_MF4 + {7, OperandInfo253}, // Inst #1987 = PseudoVFNCVT_RTZ_X_F_W_MF4_MASK + {4, OperandInfo252}, // Inst #1988 = PseudoVFNCVT_RTZ_X_F_W_MF8 + {7, OperandInfo253}, // Inst #1989 = PseudoVFNCVT_RTZ_X_F_W_MF8_MASK + {4, OperandInfo246}, // Inst #1990 = PseudoVFNCVT_XU_F_W_M1 + {7, OperandInfo247}, // Inst #1991 = PseudoVFNCVT_XU_F_W_M1_MASK + {4, OperandInfo248}, // Inst #1992 = PseudoVFNCVT_XU_F_W_M2 + {7, OperandInfo249}, // Inst #1993 = PseudoVFNCVT_XU_F_W_M2_MASK + {4, OperandInfo250}, // Inst #1994 = PseudoVFNCVT_XU_F_W_M4 + {7, OperandInfo251}, // Inst #1995 = PseudoVFNCVT_XU_F_W_M4_MASK + {4, OperandInfo252}, // Inst #1996 = PseudoVFNCVT_XU_F_W_MF2 + {7, OperandInfo253}, // Inst #1997 = PseudoVFNCVT_XU_F_W_MF2_MASK + {4, OperandInfo252}, // Inst #1998 = PseudoVFNCVT_XU_F_W_MF4 + {7, OperandInfo253}, // Inst #1999 = PseudoVFNCVT_XU_F_W_MF4_MASK + {4, OperandInfo252}, // Inst #2000 = PseudoVFNCVT_XU_F_W_MF8 + {7, OperandInfo253}, // Inst #2001 = PseudoVFNCVT_XU_F_W_MF8_MASK + {4, OperandInfo246}, // Inst #2002 = PseudoVFNCVT_X_F_W_M1 + {7, OperandInfo247}, // Inst #2003 = PseudoVFNCVT_X_F_W_M1_MASK + {4, OperandInfo248}, // Inst #2004 = PseudoVFNCVT_X_F_W_M2 + {7, OperandInfo249}, // Inst #2005 = PseudoVFNCVT_X_F_W_M2_MASK + {4, OperandInfo250}, // Inst #2006 = PseudoVFNCVT_X_F_W_M4 + {7, OperandInfo251}, // Inst #2007 = PseudoVFNCVT_X_F_W_M4_MASK + {4, OperandInfo252}, // Inst #2008 = PseudoVFNCVT_X_F_W_MF2 + {7, OperandInfo253}, // Inst #2009 = PseudoVFNCVT_X_F_W_MF2_MASK + {4, OperandInfo252}, // Inst #2010 = PseudoVFNCVT_X_F_W_MF4 + {7, OperandInfo253}, // Inst #2011 = PseudoVFNCVT_X_F_W_MF4_MASK + {4, OperandInfo252}, // Inst #2012 = PseudoVFNCVT_X_F_W_MF8 + {7, OperandInfo253}, // Inst #2013 = PseudoVFNCVT_X_F_W_MF8_MASK + {7, OperandInfo166}, // Inst #2014 = PseudoVFNMACC_VF16_M1 + {7, OperandInfo167}, // Inst #2015 = PseudoVFNMACC_VF16_M1_MASK + {7, OperandInfo168}, // Inst #2016 = PseudoVFNMACC_VF16_M2 + {7, OperandInfo169}, // Inst #2017 = PseudoVFNMACC_VF16_M2_MASK + {7, OperandInfo170}, // Inst #2018 = PseudoVFNMACC_VF16_M4 + {7, OperandInfo171}, // Inst #2019 = PseudoVFNMACC_VF16_M4_MASK + {7, OperandInfo172}, // Inst #2020 = PseudoVFNMACC_VF16_M8 + {7, OperandInfo173}, // Inst #2021 = PseudoVFNMACC_VF16_M8_MASK + {7, OperandInfo166}, // Inst #2022 = PseudoVFNMACC_VF16_MF2 + {7, OperandInfo167}, // Inst #2023 = PseudoVFNMACC_VF16_MF2_MASK + {7, OperandInfo166}, // Inst #2024 = PseudoVFNMACC_VF16_MF4 + {7, OperandInfo167}, // Inst #2025 = PseudoVFNMACC_VF16_MF4_MASK + {7, OperandInfo166}, // Inst #2026 = PseudoVFNMACC_VF16_MF8 + {7, OperandInfo167}, // Inst #2027 = PseudoVFNMACC_VF16_MF8_MASK + {7, OperandInfo174}, // Inst #2028 = PseudoVFNMACC_VF32_M1 + {7, OperandInfo175}, // Inst #2029 = PseudoVFNMACC_VF32_M1_MASK + {7, OperandInfo176}, // Inst #2030 = PseudoVFNMACC_VF32_M2 + {7, OperandInfo177}, // Inst #2031 = PseudoVFNMACC_VF32_M2_MASK + {7, OperandInfo178}, // Inst #2032 = PseudoVFNMACC_VF32_M4 + {7, OperandInfo179}, // Inst #2033 = PseudoVFNMACC_VF32_M4_MASK + {7, OperandInfo180}, // Inst #2034 = PseudoVFNMACC_VF32_M8 + {7, OperandInfo181}, // Inst #2035 = PseudoVFNMACC_VF32_M8_MASK + {7, OperandInfo174}, // Inst #2036 = PseudoVFNMACC_VF32_MF2 + {7, OperandInfo175}, // Inst #2037 = PseudoVFNMACC_VF32_MF2_MASK + {7, OperandInfo174}, // Inst #2038 = PseudoVFNMACC_VF32_MF4 + {7, OperandInfo175}, // Inst #2039 = PseudoVFNMACC_VF32_MF4_MASK + {7, OperandInfo174}, // Inst #2040 = PseudoVFNMACC_VF32_MF8 + {7, OperandInfo175}, // Inst #2041 = PseudoVFNMACC_VF32_MF8_MASK + {7, OperandInfo182}, // Inst #2042 = PseudoVFNMACC_VF64_M1 + {7, OperandInfo183}, // Inst #2043 = PseudoVFNMACC_VF64_M1_MASK + {7, OperandInfo184}, // Inst #2044 = PseudoVFNMACC_VF64_M2 + {7, OperandInfo185}, // Inst #2045 = PseudoVFNMACC_VF64_M2_MASK + {7, OperandInfo186}, // Inst #2046 = PseudoVFNMACC_VF64_M4 + {7, OperandInfo187}, // Inst #2047 = PseudoVFNMACC_VF64_M4_MASK + {7, OperandInfo188}, // Inst #2048 = PseudoVFNMACC_VF64_M8 + {7, OperandInfo189}, // Inst #2049 = PseudoVFNMACC_VF64_M8_MASK + {7, OperandInfo182}, // Inst #2050 = PseudoVFNMACC_VF64_MF2 + {7, OperandInfo183}, // Inst #2051 = PseudoVFNMACC_VF64_MF2_MASK + {7, OperandInfo182}, // Inst #2052 = PseudoVFNMACC_VF64_MF4 + {7, OperandInfo183}, // Inst #2053 = PseudoVFNMACC_VF64_MF4_MASK + {7, OperandInfo182}, // Inst #2054 = PseudoVFNMACC_VF64_MF8 + {7, OperandInfo183}, // Inst #2055 = PseudoVFNMACC_VF64_MF8_MASK + {7, OperandInfo190}, // Inst #2056 = PseudoVFNMACC_VV_M1 + {7, OperandInfo191}, // Inst #2057 = PseudoVFNMACC_VV_M1_MASK + {7, OperandInfo192}, // Inst #2058 = PseudoVFNMACC_VV_M2 + {7, OperandInfo193}, // Inst #2059 = PseudoVFNMACC_VV_M2_MASK + {7, OperandInfo194}, // Inst #2060 = PseudoVFNMACC_VV_M4 + {7, OperandInfo195}, // Inst #2061 = PseudoVFNMACC_VV_M4_MASK + {7, OperandInfo196}, // Inst #2062 = PseudoVFNMACC_VV_M8 + {7, OperandInfo197}, // Inst #2063 = PseudoVFNMACC_VV_M8_MASK + {7, OperandInfo190}, // Inst #2064 = PseudoVFNMACC_VV_MF2 + {7, OperandInfo191}, // Inst #2065 = PseudoVFNMACC_VV_MF2_MASK + {7, OperandInfo190}, // Inst #2066 = PseudoVFNMACC_VV_MF4 + {7, OperandInfo191}, // Inst #2067 = PseudoVFNMACC_VV_MF4_MASK + {7, OperandInfo190}, // Inst #2068 = PseudoVFNMACC_VV_MF8 + {7, OperandInfo191}, // Inst #2069 = PseudoVFNMACC_VV_MF8_MASK + {7, OperandInfo166}, // Inst #2070 = PseudoVFNMADD_VF16_M1 + {7, OperandInfo167}, // Inst #2071 = PseudoVFNMADD_VF16_M1_MASK + {7, OperandInfo168}, // Inst #2072 = PseudoVFNMADD_VF16_M2 + {7, OperandInfo169}, // Inst #2073 = PseudoVFNMADD_VF16_M2_MASK + {7, OperandInfo170}, // Inst #2074 = PseudoVFNMADD_VF16_M4 + {7, OperandInfo171}, // Inst #2075 = PseudoVFNMADD_VF16_M4_MASK + {7, OperandInfo172}, // Inst #2076 = PseudoVFNMADD_VF16_M8 + {7, OperandInfo173}, // Inst #2077 = PseudoVFNMADD_VF16_M8_MASK + {7, OperandInfo166}, // Inst #2078 = PseudoVFNMADD_VF16_MF2 + {7, OperandInfo167}, // Inst #2079 = PseudoVFNMADD_VF16_MF2_MASK + {7, OperandInfo166}, // Inst #2080 = PseudoVFNMADD_VF16_MF4 + {7, OperandInfo167}, // Inst #2081 = PseudoVFNMADD_VF16_MF4_MASK + {7, OperandInfo166}, // Inst #2082 = PseudoVFNMADD_VF16_MF8 + {7, OperandInfo167}, // Inst #2083 = PseudoVFNMADD_VF16_MF8_MASK + {7, OperandInfo174}, // Inst #2084 = PseudoVFNMADD_VF32_M1 + {7, OperandInfo175}, // Inst #2085 = PseudoVFNMADD_VF32_M1_MASK + {7, OperandInfo176}, // Inst #2086 = PseudoVFNMADD_VF32_M2 + {7, OperandInfo177}, // Inst #2087 = PseudoVFNMADD_VF32_M2_MASK + {7, OperandInfo178}, // Inst #2088 = PseudoVFNMADD_VF32_M4 + {7, OperandInfo179}, // Inst #2089 = PseudoVFNMADD_VF32_M4_MASK + {7, OperandInfo180}, // Inst #2090 = PseudoVFNMADD_VF32_M8 + {7, OperandInfo181}, // Inst #2091 = PseudoVFNMADD_VF32_M8_MASK + {7, OperandInfo174}, // Inst #2092 = PseudoVFNMADD_VF32_MF2 + {7, OperandInfo175}, // Inst #2093 = PseudoVFNMADD_VF32_MF2_MASK + {7, OperandInfo174}, // Inst #2094 = PseudoVFNMADD_VF32_MF4 + {7, OperandInfo175}, // Inst #2095 = PseudoVFNMADD_VF32_MF4_MASK + {7, OperandInfo174}, // Inst #2096 = PseudoVFNMADD_VF32_MF8 + {7, OperandInfo175}, // Inst #2097 = PseudoVFNMADD_VF32_MF8_MASK + {7, OperandInfo182}, // Inst #2098 = PseudoVFNMADD_VF64_M1 + {7, OperandInfo183}, // Inst #2099 = PseudoVFNMADD_VF64_M1_MASK + {7, OperandInfo184}, // Inst #2100 = PseudoVFNMADD_VF64_M2 + {7, OperandInfo185}, // Inst #2101 = PseudoVFNMADD_VF64_M2_MASK + {7, OperandInfo186}, // Inst #2102 = PseudoVFNMADD_VF64_M4 + {7, OperandInfo187}, // Inst #2103 = PseudoVFNMADD_VF64_M4_MASK + {7, OperandInfo188}, // Inst #2104 = PseudoVFNMADD_VF64_M8 + {7, OperandInfo189}, // Inst #2105 = PseudoVFNMADD_VF64_M8_MASK + {7, OperandInfo182}, // Inst #2106 = PseudoVFNMADD_VF64_MF2 + {7, OperandInfo183}, // Inst #2107 = PseudoVFNMADD_VF64_MF2_MASK + {7, OperandInfo182}, // Inst #2108 = PseudoVFNMADD_VF64_MF4 + {7, OperandInfo183}, // Inst #2109 = PseudoVFNMADD_VF64_MF4_MASK + {7, OperandInfo182}, // Inst #2110 = PseudoVFNMADD_VF64_MF8 + {7, OperandInfo183}, // Inst #2111 = PseudoVFNMADD_VF64_MF8_MASK + {7, OperandInfo190}, // Inst #2112 = PseudoVFNMADD_VV_M1 + {7, OperandInfo191}, // Inst #2113 = PseudoVFNMADD_VV_M1_MASK + {7, OperandInfo192}, // Inst #2114 = PseudoVFNMADD_VV_M2 + {7, OperandInfo193}, // Inst #2115 = PseudoVFNMADD_VV_M2_MASK + {7, OperandInfo194}, // Inst #2116 = PseudoVFNMADD_VV_M4 + {7, OperandInfo195}, // Inst #2117 = PseudoVFNMADD_VV_M4_MASK + {7, OperandInfo196}, // Inst #2118 = PseudoVFNMADD_VV_M8 + {7, OperandInfo197}, // Inst #2119 = PseudoVFNMADD_VV_M8_MASK + {7, OperandInfo190}, // Inst #2120 = PseudoVFNMADD_VV_MF2 + {7, OperandInfo191}, // Inst #2121 = PseudoVFNMADD_VV_MF2_MASK + {7, OperandInfo190}, // Inst #2122 = PseudoVFNMADD_VV_MF4 + {7, OperandInfo191}, // Inst #2123 = PseudoVFNMADD_VV_MF4_MASK + {7, OperandInfo190}, // Inst #2124 = PseudoVFNMADD_VV_MF8 + {7, OperandInfo191}, // Inst #2125 = PseudoVFNMADD_VV_MF8_MASK + {7, OperandInfo166}, // Inst #2126 = PseudoVFNMSAC_VF16_M1 + {7, OperandInfo167}, // Inst #2127 = PseudoVFNMSAC_VF16_M1_MASK + {7, OperandInfo168}, // Inst #2128 = PseudoVFNMSAC_VF16_M2 + {7, OperandInfo169}, // Inst #2129 = PseudoVFNMSAC_VF16_M2_MASK + {7, OperandInfo170}, // Inst #2130 = PseudoVFNMSAC_VF16_M4 + {7, OperandInfo171}, // Inst #2131 = PseudoVFNMSAC_VF16_M4_MASK + {7, OperandInfo172}, // Inst #2132 = PseudoVFNMSAC_VF16_M8 + {7, OperandInfo173}, // Inst #2133 = PseudoVFNMSAC_VF16_M8_MASK + {7, OperandInfo166}, // Inst #2134 = PseudoVFNMSAC_VF16_MF2 + {7, OperandInfo167}, // Inst #2135 = PseudoVFNMSAC_VF16_MF2_MASK + {7, OperandInfo166}, // Inst #2136 = PseudoVFNMSAC_VF16_MF4 + {7, OperandInfo167}, // Inst #2137 = PseudoVFNMSAC_VF16_MF4_MASK + {7, OperandInfo166}, // Inst #2138 = PseudoVFNMSAC_VF16_MF8 + {7, OperandInfo167}, // Inst #2139 = PseudoVFNMSAC_VF16_MF8_MASK + {7, OperandInfo174}, // Inst #2140 = PseudoVFNMSAC_VF32_M1 + {7, OperandInfo175}, // Inst #2141 = PseudoVFNMSAC_VF32_M1_MASK + {7, OperandInfo176}, // Inst #2142 = PseudoVFNMSAC_VF32_M2 + {7, OperandInfo177}, // Inst #2143 = PseudoVFNMSAC_VF32_M2_MASK + {7, OperandInfo178}, // Inst #2144 = PseudoVFNMSAC_VF32_M4 + {7, OperandInfo179}, // Inst #2145 = PseudoVFNMSAC_VF32_M4_MASK + {7, OperandInfo180}, // Inst #2146 = PseudoVFNMSAC_VF32_M8 + {7, OperandInfo181}, // Inst #2147 = PseudoVFNMSAC_VF32_M8_MASK + {7, OperandInfo174}, // Inst #2148 = PseudoVFNMSAC_VF32_MF2 + {7, OperandInfo175}, // Inst #2149 = PseudoVFNMSAC_VF32_MF2_MASK + {7, OperandInfo174}, // Inst #2150 = PseudoVFNMSAC_VF32_MF4 + {7, OperandInfo175}, // Inst #2151 = PseudoVFNMSAC_VF32_MF4_MASK + {7, OperandInfo174}, // Inst #2152 = PseudoVFNMSAC_VF32_MF8 + {7, OperandInfo175}, // Inst #2153 = PseudoVFNMSAC_VF32_MF8_MASK + {7, OperandInfo182}, // Inst #2154 = PseudoVFNMSAC_VF64_M1 + {7, OperandInfo183}, // Inst #2155 = PseudoVFNMSAC_VF64_M1_MASK + {7, OperandInfo184}, // Inst #2156 = PseudoVFNMSAC_VF64_M2 + {7, OperandInfo185}, // Inst #2157 = PseudoVFNMSAC_VF64_M2_MASK + {7, OperandInfo186}, // Inst #2158 = PseudoVFNMSAC_VF64_M4 + {7, OperandInfo187}, // Inst #2159 = PseudoVFNMSAC_VF64_M4_MASK + {7, OperandInfo188}, // Inst #2160 = PseudoVFNMSAC_VF64_M8 + {7, OperandInfo189}, // Inst #2161 = PseudoVFNMSAC_VF64_M8_MASK + {7, OperandInfo182}, // Inst #2162 = PseudoVFNMSAC_VF64_MF2 + {7, OperandInfo183}, // Inst #2163 = PseudoVFNMSAC_VF64_MF2_MASK + {7, OperandInfo182}, // Inst #2164 = PseudoVFNMSAC_VF64_MF4 + {7, OperandInfo183}, // Inst #2165 = PseudoVFNMSAC_VF64_MF4_MASK + {7, OperandInfo182}, // Inst #2166 = PseudoVFNMSAC_VF64_MF8 + {7, OperandInfo183}, // Inst #2167 = PseudoVFNMSAC_VF64_MF8_MASK + {7, OperandInfo190}, // Inst #2168 = PseudoVFNMSAC_VV_M1 + {7, OperandInfo191}, // Inst #2169 = PseudoVFNMSAC_VV_M1_MASK + {7, OperandInfo192}, // Inst #2170 = PseudoVFNMSAC_VV_M2 + {7, OperandInfo193}, // Inst #2171 = PseudoVFNMSAC_VV_M2_MASK + {7, OperandInfo194}, // Inst #2172 = PseudoVFNMSAC_VV_M4 + {7, OperandInfo195}, // Inst #2173 = PseudoVFNMSAC_VV_M4_MASK + {7, OperandInfo196}, // Inst #2174 = PseudoVFNMSAC_VV_M8 + {7, OperandInfo197}, // Inst #2175 = PseudoVFNMSAC_VV_M8_MASK + {7, OperandInfo190}, // Inst #2176 = PseudoVFNMSAC_VV_MF2 + {7, OperandInfo191}, // Inst #2177 = PseudoVFNMSAC_VV_MF2_MASK + {7, OperandInfo190}, // Inst #2178 = PseudoVFNMSAC_VV_MF4 + {7, OperandInfo191}, // Inst #2179 = PseudoVFNMSAC_VV_MF4_MASK + {7, OperandInfo190}, // Inst #2180 = PseudoVFNMSAC_VV_MF8 + {7, OperandInfo191}, // Inst #2181 = PseudoVFNMSAC_VV_MF8_MASK + {7, OperandInfo166}, // Inst #2182 = PseudoVFNMSUB_VF16_M1 + {7, OperandInfo167}, // Inst #2183 = PseudoVFNMSUB_VF16_M1_MASK + {7, OperandInfo168}, // Inst #2184 = PseudoVFNMSUB_VF16_M2 + {7, OperandInfo169}, // Inst #2185 = PseudoVFNMSUB_VF16_M2_MASK + {7, OperandInfo170}, // Inst #2186 = PseudoVFNMSUB_VF16_M4 + {7, OperandInfo171}, // Inst #2187 = PseudoVFNMSUB_VF16_M4_MASK + {7, OperandInfo172}, // Inst #2188 = PseudoVFNMSUB_VF16_M8 + {7, OperandInfo173}, // Inst #2189 = PseudoVFNMSUB_VF16_M8_MASK + {7, OperandInfo166}, // Inst #2190 = PseudoVFNMSUB_VF16_MF2 + {7, OperandInfo167}, // Inst #2191 = PseudoVFNMSUB_VF16_MF2_MASK + {7, OperandInfo166}, // Inst #2192 = PseudoVFNMSUB_VF16_MF4 + {7, OperandInfo167}, // Inst #2193 = PseudoVFNMSUB_VF16_MF4_MASK + {7, OperandInfo166}, // Inst #2194 = PseudoVFNMSUB_VF16_MF8 + {7, OperandInfo167}, // Inst #2195 = PseudoVFNMSUB_VF16_MF8_MASK + {7, OperandInfo174}, // Inst #2196 = PseudoVFNMSUB_VF32_M1 + {7, OperandInfo175}, // Inst #2197 = PseudoVFNMSUB_VF32_M1_MASK + {7, OperandInfo176}, // Inst #2198 = PseudoVFNMSUB_VF32_M2 + {7, OperandInfo177}, // Inst #2199 = PseudoVFNMSUB_VF32_M2_MASK + {7, OperandInfo178}, // Inst #2200 = PseudoVFNMSUB_VF32_M4 + {7, OperandInfo179}, // Inst #2201 = PseudoVFNMSUB_VF32_M4_MASK + {7, OperandInfo180}, // Inst #2202 = PseudoVFNMSUB_VF32_M8 + {7, OperandInfo181}, // Inst #2203 = PseudoVFNMSUB_VF32_M8_MASK + {7, OperandInfo174}, // Inst #2204 = PseudoVFNMSUB_VF32_MF2 + {7, OperandInfo175}, // Inst #2205 = PseudoVFNMSUB_VF32_MF2_MASK + {7, OperandInfo174}, // Inst #2206 = PseudoVFNMSUB_VF32_MF4 + {7, OperandInfo175}, // Inst #2207 = PseudoVFNMSUB_VF32_MF4_MASK + {7, OperandInfo174}, // Inst #2208 = PseudoVFNMSUB_VF32_MF8 + {7, OperandInfo175}, // Inst #2209 = PseudoVFNMSUB_VF32_MF8_MASK + {7, OperandInfo182}, // Inst #2210 = PseudoVFNMSUB_VF64_M1 + {7, OperandInfo183}, // Inst #2211 = PseudoVFNMSUB_VF64_M1_MASK + {7, OperandInfo184}, // Inst #2212 = PseudoVFNMSUB_VF64_M2 + {7, OperandInfo185}, // Inst #2213 = PseudoVFNMSUB_VF64_M2_MASK + {7, OperandInfo186}, // Inst #2214 = PseudoVFNMSUB_VF64_M4 + {7, OperandInfo187}, // Inst #2215 = PseudoVFNMSUB_VF64_M4_MASK + {7, OperandInfo188}, // Inst #2216 = PseudoVFNMSUB_VF64_M8 + {7, OperandInfo189}, // Inst #2217 = PseudoVFNMSUB_VF64_M8_MASK + {7, OperandInfo182}, // Inst #2218 = PseudoVFNMSUB_VF64_MF2 + {7, OperandInfo183}, // Inst #2219 = PseudoVFNMSUB_VF64_MF2_MASK + {7, OperandInfo182}, // Inst #2220 = PseudoVFNMSUB_VF64_MF4 + {7, OperandInfo183}, // Inst #2221 = PseudoVFNMSUB_VF64_MF4_MASK + {7, OperandInfo182}, // Inst #2222 = PseudoVFNMSUB_VF64_MF8 + {7, OperandInfo183}, // Inst #2223 = PseudoVFNMSUB_VF64_MF8_MASK + {7, OperandInfo190}, // Inst #2224 = PseudoVFNMSUB_VV_M1 + {7, OperandInfo191}, // Inst #2225 = PseudoVFNMSUB_VV_M1_MASK + {7, OperandInfo192}, // Inst #2226 = PseudoVFNMSUB_VV_M2 + {7, OperandInfo193}, // Inst #2227 = PseudoVFNMSUB_VV_M2_MASK + {7, OperandInfo194}, // Inst #2228 = PseudoVFNMSUB_VV_M4 + {7, OperandInfo195}, // Inst #2229 = PseudoVFNMSUB_VV_M4_MASK + {7, OperandInfo196}, // Inst #2230 = PseudoVFNMSUB_VV_M8 + {7, OperandInfo197}, // Inst #2231 = PseudoVFNMSUB_VV_M8_MASK + {7, OperandInfo190}, // Inst #2232 = PseudoVFNMSUB_VV_MF2 + {7, OperandInfo191}, // Inst #2233 = PseudoVFNMSUB_VV_MF2_MASK + {7, OperandInfo190}, // Inst #2234 = PseudoVFNMSUB_VV_MF4 + {7, OperandInfo191}, // Inst #2235 = PseudoVFNMSUB_VV_MF4_MASK + {7, OperandInfo190}, // Inst #2236 = PseudoVFNMSUB_VV_MF8 + {7, OperandInfo191}, // Inst #2237 = PseudoVFNMSUB_VV_MF8_MASK + {5, OperandInfo130}, // Inst #2238 = PseudoVFRDIV_VF16_M1 + {8, OperandInfo131}, // Inst #2239 = PseudoVFRDIV_VF16_M1_MASK + {5, OperandInfo132}, // Inst #2240 = PseudoVFRDIV_VF16_M2 + {8, OperandInfo133}, // Inst #2241 = PseudoVFRDIV_VF16_M2_MASK + {5, OperandInfo134}, // Inst #2242 = PseudoVFRDIV_VF16_M4 + {8, OperandInfo135}, // Inst #2243 = PseudoVFRDIV_VF16_M4_MASK + {5, OperandInfo136}, // Inst #2244 = PseudoVFRDIV_VF16_M8 + {8, OperandInfo137}, // Inst #2245 = PseudoVFRDIV_VF16_M8_MASK + {5, OperandInfo130}, // Inst #2246 = PseudoVFRDIV_VF16_MF2 + {8, OperandInfo131}, // Inst #2247 = PseudoVFRDIV_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #2248 = PseudoVFRDIV_VF16_MF4 + {8, OperandInfo131}, // Inst #2249 = PseudoVFRDIV_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #2250 = PseudoVFRDIV_VF16_MF8 + {8, OperandInfo131}, // Inst #2251 = PseudoVFRDIV_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #2252 = PseudoVFRDIV_VF32_M1 + {8, OperandInfo139}, // Inst #2253 = PseudoVFRDIV_VF32_M1_MASK + {5, OperandInfo140}, // Inst #2254 = PseudoVFRDIV_VF32_M2 + {8, OperandInfo141}, // Inst #2255 = PseudoVFRDIV_VF32_M2_MASK + {5, OperandInfo142}, // Inst #2256 = PseudoVFRDIV_VF32_M4 + {8, OperandInfo143}, // Inst #2257 = PseudoVFRDIV_VF32_M4_MASK + {5, OperandInfo144}, // Inst #2258 = PseudoVFRDIV_VF32_M8 + {8, OperandInfo145}, // Inst #2259 = PseudoVFRDIV_VF32_M8_MASK + {5, OperandInfo138}, // Inst #2260 = PseudoVFRDIV_VF32_MF2 + {8, OperandInfo139}, // Inst #2261 = PseudoVFRDIV_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #2262 = PseudoVFRDIV_VF32_MF4 + {8, OperandInfo139}, // Inst #2263 = PseudoVFRDIV_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #2264 = PseudoVFRDIV_VF32_MF8 + {8, OperandInfo139}, // Inst #2265 = PseudoVFRDIV_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #2266 = PseudoVFRDIV_VF64_M1 + {8, OperandInfo147}, // Inst #2267 = PseudoVFRDIV_VF64_M1_MASK + {5, OperandInfo148}, // Inst #2268 = PseudoVFRDIV_VF64_M2 + {8, OperandInfo149}, // Inst #2269 = PseudoVFRDIV_VF64_M2_MASK + {5, OperandInfo150}, // Inst #2270 = PseudoVFRDIV_VF64_M4 + {8, OperandInfo151}, // Inst #2271 = PseudoVFRDIV_VF64_M4_MASK + {5, OperandInfo152}, // Inst #2272 = PseudoVFRDIV_VF64_M8 + {8, OperandInfo153}, // Inst #2273 = PseudoVFRDIV_VF64_M8_MASK + {5, OperandInfo146}, // Inst #2274 = PseudoVFRDIV_VF64_MF2 + {8, OperandInfo147}, // Inst #2275 = PseudoVFRDIV_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #2276 = PseudoVFRDIV_VF64_MF4 + {8, OperandInfo147}, // Inst #2277 = PseudoVFRDIV_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #2278 = PseudoVFRDIV_VF64_MF8 + {8, OperandInfo147}, // Inst #2279 = PseudoVFRDIV_VF64_MF8_MASK + {4, OperandInfo154}, // Inst #2280 = PseudoVFREC7_V_M1 + {7, OperandInfo162}, // Inst #2281 = PseudoVFREC7_V_M1_MASK + {4, OperandInfo156}, // Inst #2282 = PseudoVFREC7_V_M2 + {7, OperandInfo163}, // Inst #2283 = PseudoVFREC7_V_M2_MASK + {4, OperandInfo158}, // Inst #2284 = PseudoVFREC7_V_M4 + {7, OperandInfo164}, // Inst #2285 = PseudoVFREC7_V_M4_MASK + {4, OperandInfo160}, // Inst #2286 = PseudoVFREC7_V_M8 + {7, OperandInfo165}, // Inst #2287 = PseudoVFREC7_V_M8_MASK + {4, OperandInfo154}, // Inst #2288 = PseudoVFREC7_V_MF2 + {7, OperandInfo162}, // Inst #2289 = PseudoVFREC7_V_MF2_MASK + {4, OperandInfo154}, // Inst #2290 = PseudoVFREC7_V_MF4 + {7, OperandInfo162}, // Inst #2291 = PseudoVFREC7_V_MF4_MASK + {4, OperandInfo154}, // Inst #2292 = PseudoVFREC7_V_MF8 + {7, OperandInfo162}, // Inst #2293 = PseudoVFREC7_V_MF8_MASK + {6, OperandInfo254}, // Inst #2294 = PseudoVFREDMAX_VS_M1 + {7, OperandInfo191}, // Inst #2295 = PseudoVFREDMAX_VS_M1_MASK + {6, OperandInfo255}, // Inst #2296 = PseudoVFREDMAX_VS_M2 + {7, OperandInfo256}, // Inst #2297 = PseudoVFREDMAX_VS_M2_MASK + {6, OperandInfo257}, // Inst #2298 = PseudoVFREDMAX_VS_M4 + {7, OperandInfo258}, // Inst #2299 = PseudoVFREDMAX_VS_M4_MASK + {6, OperandInfo259}, // Inst #2300 = PseudoVFREDMAX_VS_M8 + {7, OperandInfo260}, // Inst #2301 = PseudoVFREDMAX_VS_M8_MASK + {6, OperandInfo254}, // Inst #2302 = PseudoVFREDMAX_VS_MF2 + {7, OperandInfo191}, // Inst #2303 = PseudoVFREDMAX_VS_MF2_MASK + {6, OperandInfo254}, // Inst #2304 = PseudoVFREDMAX_VS_MF4 + {7, OperandInfo191}, // Inst #2305 = PseudoVFREDMAX_VS_MF4_MASK + {6, OperandInfo254}, // Inst #2306 = PseudoVFREDMAX_VS_MF8 + {7, OperandInfo191}, // Inst #2307 = PseudoVFREDMAX_VS_MF8_MASK + {6, OperandInfo254}, // Inst #2308 = PseudoVFREDMIN_VS_M1 + {7, OperandInfo191}, // Inst #2309 = PseudoVFREDMIN_VS_M1_MASK + {6, OperandInfo255}, // Inst #2310 = PseudoVFREDMIN_VS_M2 + {7, OperandInfo256}, // Inst #2311 = PseudoVFREDMIN_VS_M2_MASK + {6, OperandInfo257}, // Inst #2312 = PseudoVFREDMIN_VS_M4 + {7, OperandInfo258}, // Inst #2313 = PseudoVFREDMIN_VS_M4_MASK + {6, OperandInfo259}, // Inst #2314 = PseudoVFREDMIN_VS_M8 + {7, OperandInfo260}, // Inst #2315 = PseudoVFREDMIN_VS_M8_MASK + {6, OperandInfo254}, // Inst #2316 = PseudoVFREDMIN_VS_MF2 + {7, OperandInfo191}, // Inst #2317 = PseudoVFREDMIN_VS_MF2_MASK + {6, OperandInfo254}, // Inst #2318 = PseudoVFREDMIN_VS_MF4 + {7, OperandInfo191}, // Inst #2319 = PseudoVFREDMIN_VS_MF4_MASK + {6, OperandInfo254}, // Inst #2320 = PseudoVFREDMIN_VS_MF8 + {7, OperandInfo191}, // Inst #2321 = PseudoVFREDMIN_VS_MF8_MASK + {6, OperandInfo254}, // Inst #2322 = PseudoVFREDOSUM_VS_M1 + {7, OperandInfo191}, // Inst #2323 = PseudoVFREDOSUM_VS_M1_MASK + {6, OperandInfo255}, // Inst #2324 = PseudoVFREDOSUM_VS_M2 + {7, OperandInfo256}, // Inst #2325 = PseudoVFREDOSUM_VS_M2_MASK + {6, OperandInfo257}, // Inst #2326 = PseudoVFREDOSUM_VS_M4 + {7, OperandInfo258}, // Inst #2327 = PseudoVFREDOSUM_VS_M4_MASK + {6, OperandInfo259}, // Inst #2328 = PseudoVFREDOSUM_VS_M8 + {7, OperandInfo260}, // Inst #2329 = PseudoVFREDOSUM_VS_M8_MASK + {6, OperandInfo254}, // Inst #2330 = PseudoVFREDOSUM_VS_MF2 + {7, OperandInfo191}, // Inst #2331 = PseudoVFREDOSUM_VS_MF2_MASK + {6, OperandInfo254}, // Inst #2332 = PseudoVFREDOSUM_VS_MF4 + {7, OperandInfo191}, // Inst #2333 = PseudoVFREDOSUM_VS_MF4_MASK + {6, OperandInfo254}, // Inst #2334 = PseudoVFREDOSUM_VS_MF8 + {7, OperandInfo191}, // Inst #2335 = PseudoVFREDOSUM_VS_MF8_MASK + {6, OperandInfo254}, // Inst #2336 = PseudoVFREDUSUM_VS_M1 + {7, OperandInfo191}, // Inst #2337 = PseudoVFREDUSUM_VS_M1_MASK + {6, OperandInfo255}, // Inst #2338 = PseudoVFREDUSUM_VS_M2 + {7, OperandInfo256}, // Inst #2339 = PseudoVFREDUSUM_VS_M2_MASK + {6, OperandInfo257}, // Inst #2340 = PseudoVFREDUSUM_VS_M4 + {7, OperandInfo258}, // Inst #2341 = PseudoVFREDUSUM_VS_M4_MASK + {6, OperandInfo259}, // Inst #2342 = PseudoVFREDUSUM_VS_M8 + {7, OperandInfo260}, // Inst #2343 = PseudoVFREDUSUM_VS_M8_MASK + {6, OperandInfo254}, // Inst #2344 = PseudoVFREDUSUM_VS_MF2 + {7, OperandInfo191}, // Inst #2345 = PseudoVFREDUSUM_VS_MF2_MASK + {6, OperandInfo254}, // Inst #2346 = PseudoVFREDUSUM_VS_MF4 + {7, OperandInfo191}, // Inst #2347 = PseudoVFREDUSUM_VS_MF4_MASK + {6, OperandInfo254}, // Inst #2348 = PseudoVFREDUSUM_VS_MF8 + {7, OperandInfo191}, // Inst #2349 = PseudoVFREDUSUM_VS_MF8_MASK + {4, OperandInfo154}, // Inst #2350 = PseudoVFRSQRT7_V_M1 + {7, OperandInfo162}, // Inst #2351 = PseudoVFRSQRT7_V_M1_MASK + {4, OperandInfo156}, // Inst #2352 = PseudoVFRSQRT7_V_M2 + {7, OperandInfo163}, // Inst #2353 = PseudoVFRSQRT7_V_M2_MASK + {4, OperandInfo158}, // Inst #2354 = PseudoVFRSQRT7_V_M4 + {7, OperandInfo164}, // Inst #2355 = PseudoVFRSQRT7_V_M4_MASK + {4, OperandInfo160}, // Inst #2356 = PseudoVFRSQRT7_V_M8 + {7, OperandInfo165}, // Inst #2357 = PseudoVFRSQRT7_V_M8_MASK + {4, OperandInfo154}, // Inst #2358 = PseudoVFRSQRT7_V_MF2 + {7, OperandInfo162}, // Inst #2359 = PseudoVFRSQRT7_V_MF2_MASK + {4, OperandInfo154}, // Inst #2360 = PseudoVFRSQRT7_V_MF4 + {7, OperandInfo162}, // Inst #2361 = PseudoVFRSQRT7_V_MF4_MASK + {4, OperandInfo154}, // Inst #2362 = PseudoVFRSQRT7_V_MF8 + {7, OperandInfo162}, // Inst #2363 = PseudoVFRSQRT7_V_MF8_MASK + {5, OperandInfo130}, // Inst #2364 = PseudoVFRSUB_VF16_M1 + {8, OperandInfo131}, // Inst #2365 = PseudoVFRSUB_VF16_M1_MASK + {5, OperandInfo132}, // Inst #2366 = PseudoVFRSUB_VF16_M2 + {8, OperandInfo133}, // Inst #2367 = PseudoVFRSUB_VF16_M2_MASK + {5, OperandInfo134}, // Inst #2368 = PseudoVFRSUB_VF16_M4 + {8, OperandInfo135}, // Inst #2369 = PseudoVFRSUB_VF16_M4_MASK + {5, OperandInfo136}, // Inst #2370 = PseudoVFRSUB_VF16_M8 + {8, OperandInfo137}, // Inst #2371 = PseudoVFRSUB_VF16_M8_MASK + {5, OperandInfo130}, // Inst #2372 = PseudoVFRSUB_VF16_MF2 + {8, OperandInfo131}, // Inst #2373 = PseudoVFRSUB_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #2374 = PseudoVFRSUB_VF16_MF4 + {8, OperandInfo131}, // Inst #2375 = PseudoVFRSUB_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #2376 = PseudoVFRSUB_VF16_MF8 + {8, OperandInfo131}, // Inst #2377 = PseudoVFRSUB_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #2378 = PseudoVFRSUB_VF32_M1 + {8, OperandInfo139}, // Inst #2379 = PseudoVFRSUB_VF32_M1_MASK + {5, OperandInfo140}, // Inst #2380 = PseudoVFRSUB_VF32_M2 + {8, OperandInfo141}, // Inst #2381 = PseudoVFRSUB_VF32_M2_MASK + {5, OperandInfo142}, // Inst #2382 = PseudoVFRSUB_VF32_M4 + {8, OperandInfo143}, // Inst #2383 = PseudoVFRSUB_VF32_M4_MASK + {5, OperandInfo144}, // Inst #2384 = PseudoVFRSUB_VF32_M8 + {8, OperandInfo145}, // Inst #2385 = PseudoVFRSUB_VF32_M8_MASK + {5, OperandInfo138}, // Inst #2386 = PseudoVFRSUB_VF32_MF2 + {8, OperandInfo139}, // Inst #2387 = PseudoVFRSUB_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #2388 = PseudoVFRSUB_VF32_MF4 + {8, OperandInfo139}, // Inst #2389 = PseudoVFRSUB_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #2390 = PseudoVFRSUB_VF32_MF8 + {8, OperandInfo139}, // Inst #2391 = PseudoVFRSUB_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #2392 = PseudoVFRSUB_VF64_M1 + {8, OperandInfo147}, // Inst #2393 = PseudoVFRSUB_VF64_M1_MASK + {5, OperandInfo148}, // Inst #2394 = PseudoVFRSUB_VF64_M2 + {8, OperandInfo149}, // Inst #2395 = PseudoVFRSUB_VF64_M2_MASK + {5, OperandInfo150}, // Inst #2396 = PseudoVFRSUB_VF64_M4 + {8, OperandInfo151}, // Inst #2397 = PseudoVFRSUB_VF64_M4_MASK + {5, OperandInfo152}, // Inst #2398 = PseudoVFRSUB_VF64_M8 + {8, OperandInfo153}, // Inst #2399 = PseudoVFRSUB_VF64_M8_MASK + {5, OperandInfo146}, // Inst #2400 = PseudoVFRSUB_VF64_MF2 + {8, OperandInfo147}, // Inst #2401 = PseudoVFRSUB_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #2402 = PseudoVFRSUB_VF64_MF4 + {8, OperandInfo147}, // Inst #2403 = PseudoVFRSUB_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #2404 = PseudoVFRSUB_VF64_MF8 + {8, OperandInfo147}, // Inst #2405 = PseudoVFRSUB_VF64_MF8_MASK + {5, OperandInfo130}, // Inst #2406 = PseudoVFSGNJN_VF16_M1 + {8, OperandInfo131}, // Inst #2407 = PseudoVFSGNJN_VF16_M1_MASK + {5, OperandInfo132}, // Inst #2408 = PseudoVFSGNJN_VF16_M2 + {8, OperandInfo133}, // Inst #2409 = PseudoVFSGNJN_VF16_M2_MASK + {5, OperandInfo134}, // Inst #2410 = PseudoVFSGNJN_VF16_M4 + {8, OperandInfo135}, // Inst #2411 = PseudoVFSGNJN_VF16_M4_MASK + {5, OperandInfo136}, // Inst #2412 = PseudoVFSGNJN_VF16_M8 + {8, OperandInfo137}, // Inst #2413 = PseudoVFSGNJN_VF16_M8_MASK + {5, OperandInfo130}, // Inst #2414 = PseudoVFSGNJN_VF16_MF2 + {8, OperandInfo131}, // Inst #2415 = PseudoVFSGNJN_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #2416 = PseudoVFSGNJN_VF16_MF4 + {8, OperandInfo131}, // Inst #2417 = PseudoVFSGNJN_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #2418 = PseudoVFSGNJN_VF16_MF8 + {8, OperandInfo131}, // Inst #2419 = PseudoVFSGNJN_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #2420 = PseudoVFSGNJN_VF32_M1 + {8, OperandInfo139}, // Inst #2421 = PseudoVFSGNJN_VF32_M1_MASK + {5, OperandInfo140}, // Inst #2422 = PseudoVFSGNJN_VF32_M2 + {8, OperandInfo141}, // Inst #2423 = PseudoVFSGNJN_VF32_M2_MASK + {5, OperandInfo142}, // Inst #2424 = PseudoVFSGNJN_VF32_M4 + {8, OperandInfo143}, // Inst #2425 = PseudoVFSGNJN_VF32_M4_MASK + {5, OperandInfo144}, // Inst #2426 = PseudoVFSGNJN_VF32_M8 + {8, OperandInfo145}, // Inst #2427 = PseudoVFSGNJN_VF32_M8_MASK + {5, OperandInfo138}, // Inst #2428 = PseudoVFSGNJN_VF32_MF2 + {8, OperandInfo139}, // Inst #2429 = PseudoVFSGNJN_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #2430 = PseudoVFSGNJN_VF32_MF4 + {8, OperandInfo139}, // Inst #2431 = PseudoVFSGNJN_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #2432 = PseudoVFSGNJN_VF32_MF8 + {8, OperandInfo139}, // Inst #2433 = PseudoVFSGNJN_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #2434 = PseudoVFSGNJN_VF64_M1 + {8, OperandInfo147}, // Inst #2435 = PseudoVFSGNJN_VF64_M1_MASK + {5, OperandInfo148}, // Inst #2436 = PseudoVFSGNJN_VF64_M2 + {8, OperandInfo149}, // Inst #2437 = PseudoVFSGNJN_VF64_M2_MASK + {5, OperandInfo150}, // Inst #2438 = PseudoVFSGNJN_VF64_M4 + {8, OperandInfo151}, // Inst #2439 = PseudoVFSGNJN_VF64_M4_MASK + {5, OperandInfo152}, // Inst #2440 = PseudoVFSGNJN_VF64_M8 + {8, OperandInfo153}, // Inst #2441 = PseudoVFSGNJN_VF64_M8_MASK + {5, OperandInfo146}, // Inst #2442 = PseudoVFSGNJN_VF64_MF2 + {8, OperandInfo147}, // Inst #2443 = PseudoVFSGNJN_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #2444 = PseudoVFSGNJN_VF64_MF4 + {8, OperandInfo147}, // Inst #2445 = PseudoVFSGNJN_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #2446 = PseudoVFSGNJN_VF64_MF8 + {8, OperandInfo147}, // Inst #2447 = PseudoVFSGNJN_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #2448 = PseudoVFSGNJN_VV_M1 + {8, OperandInfo63}, // Inst #2449 = PseudoVFSGNJN_VV_M1_MASK + {5, OperandInfo64}, // Inst #2450 = PseudoVFSGNJN_VV_M2 + {8, OperandInfo65}, // Inst #2451 = PseudoVFSGNJN_VV_M2_MASK + {5, OperandInfo66}, // Inst #2452 = PseudoVFSGNJN_VV_M4 + {8, OperandInfo67}, // Inst #2453 = PseudoVFSGNJN_VV_M4_MASK + {5, OperandInfo68}, // Inst #2454 = PseudoVFSGNJN_VV_M8 + {8, OperandInfo69}, // Inst #2455 = PseudoVFSGNJN_VV_M8_MASK + {5, OperandInfo62}, // Inst #2456 = PseudoVFSGNJN_VV_MF2 + {8, OperandInfo63}, // Inst #2457 = PseudoVFSGNJN_VV_MF2_MASK + {5, OperandInfo62}, // Inst #2458 = PseudoVFSGNJN_VV_MF4 + {8, OperandInfo63}, // Inst #2459 = PseudoVFSGNJN_VV_MF4_MASK + {5, OperandInfo62}, // Inst #2460 = PseudoVFSGNJN_VV_MF8 + {8, OperandInfo63}, // Inst #2461 = PseudoVFSGNJN_VV_MF8_MASK + {5, OperandInfo130}, // Inst #2462 = PseudoVFSGNJX_VF16_M1 + {8, OperandInfo131}, // Inst #2463 = PseudoVFSGNJX_VF16_M1_MASK + {5, OperandInfo132}, // Inst #2464 = PseudoVFSGNJX_VF16_M2 + {8, OperandInfo133}, // Inst #2465 = PseudoVFSGNJX_VF16_M2_MASK + {5, OperandInfo134}, // Inst #2466 = PseudoVFSGNJX_VF16_M4 + {8, OperandInfo135}, // Inst #2467 = PseudoVFSGNJX_VF16_M4_MASK + {5, OperandInfo136}, // Inst #2468 = PseudoVFSGNJX_VF16_M8 + {8, OperandInfo137}, // Inst #2469 = PseudoVFSGNJX_VF16_M8_MASK + {5, OperandInfo130}, // Inst #2470 = PseudoVFSGNJX_VF16_MF2 + {8, OperandInfo131}, // Inst #2471 = PseudoVFSGNJX_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #2472 = PseudoVFSGNJX_VF16_MF4 + {8, OperandInfo131}, // Inst #2473 = PseudoVFSGNJX_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #2474 = PseudoVFSGNJX_VF16_MF8 + {8, OperandInfo131}, // Inst #2475 = PseudoVFSGNJX_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #2476 = PseudoVFSGNJX_VF32_M1 + {8, OperandInfo139}, // Inst #2477 = PseudoVFSGNJX_VF32_M1_MASK + {5, OperandInfo140}, // Inst #2478 = PseudoVFSGNJX_VF32_M2 + {8, OperandInfo141}, // Inst #2479 = PseudoVFSGNJX_VF32_M2_MASK + {5, OperandInfo142}, // Inst #2480 = PseudoVFSGNJX_VF32_M4 + {8, OperandInfo143}, // Inst #2481 = PseudoVFSGNJX_VF32_M4_MASK + {5, OperandInfo144}, // Inst #2482 = PseudoVFSGNJX_VF32_M8 + {8, OperandInfo145}, // Inst #2483 = PseudoVFSGNJX_VF32_M8_MASK + {5, OperandInfo138}, // Inst #2484 = PseudoVFSGNJX_VF32_MF2 + {8, OperandInfo139}, // Inst #2485 = PseudoVFSGNJX_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #2486 = PseudoVFSGNJX_VF32_MF4 + {8, OperandInfo139}, // Inst #2487 = PseudoVFSGNJX_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #2488 = PseudoVFSGNJX_VF32_MF8 + {8, OperandInfo139}, // Inst #2489 = PseudoVFSGNJX_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #2490 = PseudoVFSGNJX_VF64_M1 + {8, OperandInfo147}, // Inst #2491 = PseudoVFSGNJX_VF64_M1_MASK + {5, OperandInfo148}, // Inst #2492 = PseudoVFSGNJX_VF64_M2 + {8, OperandInfo149}, // Inst #2493 = PseudoVFSGNJX_VF64_M2_MASK + {5, OperandInfo150}, // Inst #2494 = PseudoVFSGNJX_VF64_M4 + {8, OperandInfo151}, // Inst #2495 = PseudoVFSGNJX_VF64_M4_MASK + {5, OperandInfo152}, // Inst #2496 = PseudoVFSGNJX_VF64_M8 + {8, OperandInfo153}, // Inst #2497 = PseudoVFSGNJX_VF64_M8_MASK + {5, OperandInfo146}, // Inst #2498 = PseudoVFSGNJX_VF64_MF2 + {8, OperandInfo147}, // Inst #2499 = PseudoVFSGNJX_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #2500 = PseudoVFSGNJX_VF64_MF4 + {8, OperandInfo147}, // Inst #2501 = PseudoVFSGNJX_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #2502 = PseudoVFSGNJX_VF64_MF8 + {8, OperandInfo147}, // Inst #2503 = PseudoVFSGNJX_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #2504 = PseudoVFSGNJX_VV_M1 + {8, OperandInfo63}, // Inst #2505 = PseudoVFSGNJX_VV_M1_MASK + {5, OperandInfo64}, // Inst #2506 = PseudoVFSGNJX_VV_M2 + {8, OperandInfo65}, // Inst #2507 = PseudoVFSGNJX_VV_M2_MASK + {5, OperandInfo66}, // Inst #2508 = PseudoVFSGNJX_VV_M4 + {8, OperandInfo67}, // Inst #2509 = PseudoVFSGNJX_VV_M4_MASK + {5, OperandInfo68}, // Inst #2510 = PseudoVFSGNJX_VV_M8 + {8, OperandInfo69}, // Inst #2511 = PseudoVFSGNJX_VV_M8_MASK + {5, OperandInfo62}, // Inst #2512 = PseudoVFSGNJX_VV_MF2 + {8, OperandInfo63}, // Inst #2513 = PseudoVFSGNJX_VV_MF2_MASK + {5, OperandInfo62}, // Inst #2514 = PseudoVFSGNJX_VV_MF4 + {8, OperandInfo63}, // Inst #2515 = PseudoVFSGNJX_VV_MF4_MASK + {5, OperandInfo62}, // Inst #2516 = PseudoVFSGNJX_VV_MF8 + {8, OperandInfo63}, // Inst #2517 = PseudoVFSGNJX_VV_MF8_MASK + {5, OperandInfo130}, // Inst #2518 = PseudoVFSGNJ_VF16_M1 + {8, OperandInfo131}, // Inst #2519 = PseudoVFSGNJ_VF16_M1_MASK + {5, OperandInfo132}, // Inst #2520 = PseudoVFSGNJ_VF16_M2 + {8, OperandInfo133}, // Inst #2521 = PseudoVFSGNJ_VF16_M2_MASK + {5, OperandInfo134}, // Inst #2522 = PseudoVFSGNJ_VF16_M4 + {8, OperandInfo135}, // Inst #2523 = PseudoVFSGNJ_VF16_M4_MASK + {5, OperandInfo136}, // Inst #2524 = PseudoVFSGNJ_VF16_M8 + {8, OperandInfo137}, // Inst #2525 = PseudoVFSGNJ_VF16_M8_MASK + {5, OperandInfo130}, // Inst #2526 = PseudoVFSGNJ_VF16_MF2 + {8, OperandInfo131}, // Inst #2527 = PseudoVFSGNJ_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #2528 = PseudoVFSGNJ_VF16_MF4 + {8, OperandInfo131}, // Inst #2529 = PseudoVFSGNJ_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #2530 = PseudoVFSGNJ_VF16_MF8 + {8, OperandInfo131}, // Inst #2531 = PseudoVFSGNJ_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #2532 = PseudoVFSGNJ_VF32_M1 + {8, OperandInfo139}, // Inst #2533 = PseudoVFSGNJ_VF32_M1_MASK + {5, OperandInfo140}, // Inst #2534 = PseudoVFSGNJ_VF32_M2 + {8, OperandInfo141}, // Inst #2535 = PseudoVFSGNJ_VF32_M2_MASK + {5, OperandInfo142}, // Inst #2536 = PseudoVFSGNJ_VF32_M4 + {8, OperandInfo143}, // Inst #2537 = PseudoVFSGNJ_VF32_M4_MASK + {5, OperandInfo144}, // Inst #2538 = PseudoVFSGNJ_VF32_M8 + {8, OperandInfo145}, // Inst #2539 = PseudoVFSGNJ_VF32_M8_MASK + {5, OperandInfo138}, // Inst #2540 = PseudoVFSGNJ_VF32_MF2 + {8, OperandInfo139}, // Inst #2541 = PseudoVFSGNJ_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #2542 = PseudoVFSGNJ_VF32_MF4 + {8, OperandInfo139}, // Inst #2543 = PseudoVFSGNJ_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #2544 = PseudoVFSGNJ_VF32_MF8 + {8, OperandInfo139}, // Inst #2545 = PseudoVFSGNJ_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #2546 = PseudoVFSGNJ_VF64_M1 + {8, OperandInfo147}, // Inst #2547 = PseudoVFSGNJ_VF64_M1_MASK + {5, OperandInfo148}, // Inst #2548 = PseudoVFSGNJ_VF64_M2 + {8, OperandInfo149}, // Inst #2549 = PseudoVFSGNJ_VF64_M2_MASK + {5, OperandInfo150}, // Inst #2550 = PseudoVFSGNJ_VF64_M4 + {8, OperandInfo151}, // Inst #2551 = PseudoVFSGNJ_VF64_M4_MASK + {5, OperandInfo152}, // Inst #2552 = PseudoVFSGNJ_VF64_M8 + {8, OperandInfo153}, // Inst #2553 = PseudoVFSGNJ_VF64_M8_MASK + {5, OperandInfo146}, // Inst #2554 = PseudoVFSGNJ_VF64_MF2 + {8, OperandInfo147}, // Inst #2555 = PseudoVFSGNJ_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #2556 = PseudoVFSGNJ_VF64_MF4 + {8, OperandInfo147}, // Inst #2557 = PseudoVFSGNJ_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #2558 = PseudoVFSGNJ_VF64_MF8 + {8, OperandInfo147}, // Inst #2559 = PseudoVFSGNJ_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #2560 = PseudoVFSGNJ_VV_M1 + {8, OperandInfo63}, // Inst #2561 = PseudoVFSGNJ_VV_M1_MASK + {5, OperandInfo64}, // Inst #2562 = PseudoVFSGNJ_VV_M2 + {8, OperandInfo65}, // Inst #2563 = PseudoVFSGNJ_VV_M2_MASK + {5, OperandInfo66}, // Inst #2564 = PseudoVFSGNJ_VV_M4 + {8, OperandInfo67}, // Inst #2565 = PseudoVFSGNJ_VV_M4_MASK + {5, OperandInfo68}, // Inst #2566 = PseudoVFSGNJ_VV_M8 + {8, OperandInfo69}, // Inst #2567 = PseudoVFSGNJ_VV_M8_MASK + {5, OperandInfo62}, // Inst #2568 = PseudoVFSGNJ_VV_MF2 + {8, OperandInfo63}, // Inst #2569 = PseudoVFSGNJ_VV_MF2_MASK + {5, OperandInfo62}, // Inst #2570 = PseudoVFSGNJ_VV_MF4 + {8, OperandInfo63}, // Inst #2571 = PseudoVFSGNJ_VV_MF4_MASK + {5, OperandInfo62}, // Inst #2572 = PseudoVFSGNJ_VV_MF8 + {8, OperandInfo63}, // Inst #2573 = PseudoVFSGNJ_VV_MF8_MASK + {5, OperandInfo130}, // Inst #2574 = PseudoVFSLIDE1DOWN_VF16_M1 + {8, OperandInfo131}, // Inst #2575 = PseudoVFSLIDE1DOWN_VF16_M1_MASK + {5, OperandInfo132}, // Inst #2576 = PseudoVFSLIDE1DOWN_VF16_M2 + {8, OperandInfo133}, // Inst #2577 = PseudoVFSLIDE1DOWN_VF16_M2_MASK + {5, OperandInfo134}, // Inst #2578 = PseudoVFSLIDE1DOWN_VF16_M4 + {8, OperandInfo135}, // Inst #2579 = PseudoVFSLIDE1DOWN_VF16_M4_MASK + {5, OperandInfo136}, // Inst #2580 = PseudoVFSLIDE1DOWN_VF16_M8 + {8, OperandInfo137}, // Inst #2581 = PseudoVFSLIDE1DOWN_VF16_M8_MASK + {5, OperandInfo130}, // Inst #2582 = PseudoVFSLIDE1DOWN_VF16_MF2 + {8, OperandInfo131}, // Inst #2583 = PseudoVFSLIDE1DOWN_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #2584 = PseudoVFSLIDE1DOWN_VF16_MF4 + {8, OperandInfo131}, // Inst #2585 = PseudoVFSLIDE1DOWN_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #2586 = PseudoVFSLIDE1DOWN_VF16_MF8 + {8, OperandInfo131}, // Inst #2587 = PseudoVFSLIDE1DOWN_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #2588 = PseudoVFSLIDE1DOWN_VF32_M1 + {8, OperandInfo139}, // Inst #2589 = PseudoVFSLIDE1DOWN_VF32_M1_MASK + {5, OperandInfo140}, // Inst #2590 = PseudoVFSLIDE1DOWN_VF32_M2 + {8, OperandInfo141}, // Inst #2591 = PseudoVFSLIDE1DOWN_VF32_M2_MASK + {5, OperandInfo142}, // Inst #2592 = PseudoVFSLIDE1DOWN_VF32_M4 + {8, OperandInfo143}, // Inst #2593 = PseudoVFSLIDE1DOWN_VF32_M4_MASK + {5, OperandInfo144}, // Inst #2594 = PseudoVFSLIDE1DOWN_VF32_M8 + {8, OperandInfo145}, // Inst #2595 = PseudoVFSLIDE1DOWN_VF32_M8_MASK + {5, OperandInfo138}, // Inst #2596 = PseudoVFSLIDE1DOWN_VF32_MF2 + {8, OperandInfo139}, // Inst #2597 = PseudoVFSLIDE1DOWN_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #2598 = PseudoVFSLIDE1DOWN_VF32_MF4 + {8, OperandInfo139}, // Inst #2599 = PseudoVFSLIDE1DOWN_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #2600 = PseudoVFSLIDE1DOWN_VF32_MF8 + {8, OperandInfo139}, // Inst #2601 = PseudoVFSLIDE1DOWN_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #2602 = PseudoVFSLIDE1DOWN_VF64_M1 + {8, OperandInfo147}, // Inst #2603 = PseudoVFSLIDE1DOWN_VF64_M1_MASK + {5, OperandInfo148}, // Inst #2604 = PseudoVFSLIDE1DOWN_VF64_M2 + {8, OperandInfo149}, // Inst #2605 = PseudoVFSLIDE1DOWN_VF64_M2_MASK + {5, OperandInfo150}, // Inst #2606 = PseudoVFSLIDE1DOWN_VF64_M4 + {8, OperandInfo151}, // Inst #2607 = PseudoVFSLIDE1DOWN_VF64_M4_MASK + {5, OperandInfo152}, // Inst #2608 = PseudoVFSLIDE1DOWN_VF64_M8 + {8, OperandInfo153}, // Inst #2609 = PseudoVFSLIDE1DOWN_VF64_M8_MASK + {5, OperandInfo146}, // Inst #2610 = PseudoVFSLIDE1DOWN_VF64_MF2 + {8, OperandInfo147}, // Inst #2611 = PseudoVFSLIDE1DOWN_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #2612 = PseudoVFSLIDE1DOWN_VF64_MF4 + {8, OperandInfo147}, // Inst #2613 = PseudoVFSLIDE1DOWN_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #2614 = PseudoVFSLIDE1DOWN_VF64_MF8 + {8, OperandInfo147}, // Inst #2615 = PseudoVFSLIDE1DOWN_VF64_MF8_MASK + {5, OperandInfo261}, // Inst #2616 = PseudoVFSLIDE1UP_VF16_M1 + {8, OperandInfo262}, // Inst #2617 = PseudoVFSLIDE1UP_VF16_M1_MASK + {5, OperandInfo263}, // Inst #2618 = PseudoVFSLIDE1UP_VF16_M2 + {8, OperandInfo264}, // Inst #2619 = PseudoVFSLIDE1UP_VF16_M2_MASK + {5, OperandInfo265}, // Inst #2620 = PseudoVFSLIDE1UP_VF16_M4 + {8, OperandInfo266}, // Inst #2621 = PseudoVFSLIDE1UP_VF16_M4_MASK + {5, OperandInfo267}, // Inst #2622 = PseudoVFSLIDE1UP_VF16_M8 + {8, OperandInfo268}, // Inst #2623 = PseudoVFSLIDE1UP_VF16_M8_MASK + {5, OperandInfo261}, // Inst #2624 = PseudoVFSLIDE1UP_VF16_MF2 + {8, OperandInfo262}, // Inst #2625 = PseudoVFSLIDE1UP_VF16_MF2_MASK + {5, OperandInfo261}, // Inst #2626 = PseudoVFSLIDE1UP_VF16_MF4 + {8, OperandInfo262}, // Inst #2627 = PseudoVFSLIDE1UP_VF16_MF4_MASK + {5, OperandInfo261}, // Inst #2628 = PseudoVFSLIDE1UP_VF16_MF8 + {8, OperandInfo262}, // Inst #2629 = PseudoVFSLIDE1UP_VF16_MF8_MASK + {5, OperandInfo269}, // Inst #2630 = PseudoVFSLIDE1UP_VF32_M1 + {8, OperandInfo270}, // Inst #2631 = PseudoVFSLIDE1UP_VF32_M1_MASK + {5, OperandInfo271}, // Inst #2632 = PseudoVFSLIDE1UP_VF32_M2 + {8, OperandInfo272}, // Inst #2633 = PseudoVFSLIDE1UP_VF32_M2_MASK + {5, OperandInfo273}, // Inst #2634 = PseudoVFSLIDE1UP_VF32_M4 + {8, OperandInfo274}, // Inst #2635 = PseudoVFSLIDE1UP_VF32_M4_MASK + {5, OperandInfo275}, // Inst #2636 = PseudoVFSLIDE1UP_VF32_M8 + {8, OperandInfo276}, // Inst #2637 = PseudoVFSLIDE1UP_VF32_M8_MASK + {5, OperandInfo269}, // Inst #2638 = PseudoVFSLIDE1UP_VF32_MF2 + {8, OperandInfo270}, // Inst #2639 = PseudoVFSLIDE1UP_VF32_MF2_MASK + {5, OperandInfo269}, // Inst #2640 = PseudoVFSLIDE1UP_VF32_MF4 + {8, OperandInfo270}, // Inst #2641 = PseudoVFSLIDE1UP_VF32_MF4_MASK + {5, OperandInfo269}, // Inst #2642 = PseudoVFSLIDE1UP_VF32_MF8 + {8, OperandInfo270}, // Inst #2643 = PseudoVFSLIDE1UP_VF32_MF8_MASK + {5, OperandInfo277}, // Inst #2644 = PseudoVFSLIDE1UP_VF64_M1 + {8, OperandInfo278}, // Inst #2645 = PseudoVFSLIDE1UP_VF64_M1_MASK + {5, OperandInfo279}, // Inst #2646 = PseudoVFSLIDE1UP_VF64_M2 + {8, OperandInfo280}, // Inst #2647 = PseudoVFSLIDE1UP_VF64_M2_MASK + {5, OperandInfo281}, // Inst #2648 = PseudoVFSLIDE1UP_VF64_M4 + {8, OperandInfo282}, // Inst #2649 = PseudoVFSLIDE1UP_VF64_M4_MASK + {5, OperandInfo283}, // Inst #2650 = PseudoVFSLIDE1UP_VF64_M8 + {8, OperandInfo284}, // Inst #2651 = PseudoVFSLIDE1UP_VF64_M8_MASK + {5, OperandInfo277}, // Inst #2652 = PseudoVFSLIDE1UP_VF64_MF2 + {8, OperandInfo278}, // Inst #2653 = PseudoVFSLIDE1UP_VF64_MF2_MASK + {5, OperandInfo277}, // Inst #2654 = PseudoVFSLIDE1UP_VF64_MF4 + {8, OperandInfo278}, // Inst #2655 = PseudoVFSLIDE1UP_VF64_MF4_MASK + {5, OperandInfo277}, // Inst #2656 = PseudoVFSLIDE1UP_VF64_MF8 + {8, OperandInfo278}, // Inst #2657 = PseudoVFSLIDE1UP_VF64_MF8_MASK + {4, OperandInfo154}, // Inst #2658 = PseudoVFSQRT_V_M1 + {7, OperandInfo162}, // Inst #2659 = PseudoVFSQRT_V_M1_MASK + {4, OperandInfo156}, // Inst #2660 = PseudoVFSQRT_V_M2 + {7, OperandInfo163}, // Inst #2661 = PseudoVFSQRT_V_M2_MASK + {4, OperandInfo158}, // Inst #2662 = PseudoVFSQRT_V_M4 + {7, OperandInfo164}, // Inst #2663 = PseudoVFSQRT_V_M4_MASK + {4, OperandInfo160}, // Inst #2664 = PseudoVFSQRT_V_M8 + {7, OperandInfo165}, // Inst #2665 = PseudoVFSQRT_V_M8_MASK + {4, OperandInfo154}, // Inst #2666 = PseudoVFSQRT_V_MF2 + {7, OperandInfo162}, // Inst #2667 = PseudoVFSQRT_V_MF2_MASK + {4, OperandInfo154}, // Inst #2668 = PseudoVFSQRT_V_MF4 + {7, OperandInfo162}, // Inst #2669 = PseudoVFSQRT_V_MF4_MASK + {4, OperandInfo154}, // Inst #2670 = PseudoVFSQRT_V_MF8 + {7, OperandInfo162}, // Inst #2671 = PseudoVFSQRT_V_MF8_MASK + {5, OperandInfo130}, // Inst #2672 = PseudoVFSUB_VF16_M1 + {8, OperandInfo131}, // Inst #2673 = PseudoVFSUB_VF16_M1_MASK + {5, OperandInfo132}, // Inst #2674 = PseudoVFSUB_VF16_M2 + {8, OperandInfo133}, // Inst #2675 = PseudoVFSUB_VF16_M2_MASK + {5, OperandInfo134}, // Inst #2676 = PseudoVFSUB_VF16_M4 + {8, OperandInfo135}, // Inst #2677 = PseudoVFSUB_VF16_M4_MASK + {5, OperandInfo136}, // Inst #2678 = PseudoVFSUB_VF16_M8 + {8, OperandInfo137}, // Inst #2679 = PseudoVFSUB_VF16_M8_MASK + {5, OperandInfo130}, // Inst #2680 = PseudoVFSUB_VF16_MF2 + {8, OperandInfo131}, // Inst #2681 = PseudoVFSUB_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #2682 = PseudoVFSUB_VF16_MF4 + {8, OperandInfo131}, // Inst #2683 = PseudoVFSUB_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #2684 = PseudoVFSUB_VF16_MF8 + {8, OperandInfo131}, // Inst #2685 = PseudoVFSUB_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #2686 = PseudoVFSUB_VF32_M1 + {8, OperandInfo139}, // Inst #2687 = PseudoVFSUB_VF32_M1_MASK + {5, OperandInfo140}, // Inst #2688 = PseudoVFSUB_VF32_M2 + {8, OperandInfo141}, // Inst #2689 = PseudoVFSUB_VF32_M2_MASK + {5, OperandInfo142}, // Inst #2690 = PseudoVFSUB_VF32_M4 + {8, OperandInfo143}, // Inst #2691 = PseudoVFSUB_VF32_M4_MASK + {5, OperandInfo144}, // Inst #2692 = PseudoVFSUB_VF32_M8 + {8, OperandInfo145}, // Inst #2693 = PseudoVFSUB_VF32_M8_MASK + {5, OperandInfo138}, // Inst #2694 = PseudoVFSUB_VF32_MF2 + {8, OperandInfo139}, // Inst #2695 = PseudoVFSUB_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #2696 = PseudoVFSUB_VF32_MF4 + {8, OperandInfo139}, // Inst #2697 = PseudoVFSUB_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #2698 = PseudoVFSUB_VF32_MF8 + {8, OperandInfo139}, // Inst #2699 = PseudoVFSUB_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #2700 = PseudoVFSUB_VF64_M1 + {8, OperandInfo147}, // Inst #2701 = PseudoVFSUB_VF64_M1_MASK + {5, OperandInfo148}, // Inst #2702 = PseudoVFSUB_VF64_M2 + {8, OperandInfo149}, // Inst #2703 = PseudoVFSUB_VF64_M2_MASK + {5, OperandInfo150}, // Inst #2704 = PseudoVFSUB_VF64_M4 + {8, OperandInfo151}, // Inst #2705 = PseudoVFSUB_VF64_M4_MASK + {5, OperandInfo152}, // Inst #2706 = PseudoVFSUB_VF64_M8 + {8, OperandInfo153}, // Inst #2707 = PseudoVFSUB_VF64_M8_MASK + {5, OperandInfo146}, // Inst #2708 = PseudoVFSUB_VF64_MF2 + {8, OperandInfo147}, // Inst #2709 = PseudoVFSUB_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #2710 = PseudoVFSUB_VF64_MF4 + {8, OperandInfo147}, // Inst #2711 = PseudoVFSUB_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #2712 = PseudoVFSUB_VF64_MF8 + {8, OperandInfo147}, // Inst #2713 = PseudoVFSUB_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #2714 = PseudoVFSUB_VV_M1 + {8, OperandInfo63}, // Inst #2715 = PseudoVFSUB_VV_M1_MASK + {5, OperandInfo64}, // Inst #2716 = PseudoVFSUB_VV_M2 + {8, OperandInfo65}, // Inst #2717 = PseudoVFSUB_VV_M2_MASK + {5, OperandInfo66}, // Inst #2718 = PseudoVFSUB_VV_M4 + {8, OperandInfo67}, // Inst #2719 = PseudoVFSUB_VV_M4_MASK + {5, OperandInfo68}, // Inst #2720 = PseudoVFSUB_VV_M8 + {8, OperandInfo69}, // Inst #2721 = PseudoVFSUB_VV_M8_MASK + {5, OperandInfo62}, // Inst #2722 = PseudoVFSUB_VV_MF2 + {8, OperandInfo63}, // Inst #2723 = PseudoVFSUB_VV_MF2_MASK + {5, OperandInfo62}, // Inst #2724 = PseudoVFSUB_VV_MF4 + {8, OperandInfo63}, // Inst #2725 = PseudoVFSUB_VV_MF4_MASK + {5, OperandInfo62}, // Inst #2726 = PseudoVFSUB_VV_MF8 + {8, OperandInfo63}, // Inst #2727 = PseudoVFSUB_VV_MF8_MASK + {5, OperandInfo285}, // Inst #2728 = PseudoVFWADD_VF16_M1 + {8, OperandInfo286}, // Inst #2729 = PseudoVFWADD_VF16_M1_MASK + {5, OperandInfo287}, // Inst #2730 = PseudoVFWADD_VF16_M2 + {8, OperandInfo288}, // Inst #2731 = PseudoVFWADD_VF16_M2_MASK + {5, OperandInfo289}, // Inst #2732 = PseudoVFWADD_VF16_M4 + {8, OperandInfo290}, // Inst #2733 = PseudoVFWADD_VF16_M4_MASK + {5, OperandInfo261}, // Inst #2734 = PseudoVFWADD_VF16_MF2 + {8, OperandInfo262}, // Inst #2735 = PseudoVFWADD_VF16_MF2_MASK + {5, OperandInfo261}, // Inst #2736 = PseudoVFWADD_VF16_MF4 + {8, OperandInfo262}, // Inst #2737 = PseudoVFWADD_VF16_MF4_MASK + {5, OperandInfo261}, // Inst #2738 = PseudoVFWADD_VF16_MF8 + {8, OperandInfo262}, // Inst #2739 = PseudoVFWADD_VF16_MF8_MASK + {5, OperandInfo291}, // Inst #2740 = PseudoVFWADD_VF32_M1 + {8, OperandInfo292}, // Inst #2741 = PseudoVFWADD_VF32_M1_MASK + {5, OperandInfo293}, // Inst #2742 = PseudoVFWADD_VF32_M2 + {8, OperandInfo294}, // Inst #2743 = PseudoVFWADD_VF32_M2_MASK + {5, OperandInfo295}, // Inst #2744 = PseudoVFWADD_VF32_M4 + {8, OperandInfo296}, // Inst #2745 = PseudoVFWADD_VF32_M4_MASK + {5, OperandInfo269}, // Inst #2746 = PseudoVFWADD_VF32_MF2 + {8, OperandInfo270}, // Inst #2747 = PseudoVFWADD_VF32_MF2_MASK + {5, OperandInfo269}, // Inst #2748 = PseudoVFWADD_VF32_MF4 + {8, OperandInfo270}, // Inst #2749 = PseudoVFWADD_VF32_MF4_MASK + {5, OperandInfo269}, // Inst #2750 = PseudoVFWADD_VF32_MF8 + {8, OperandInfo270}, // Inst #2751 = PseudoVFWADD_VF32_MF8_MASK + {5, OperandInfo297}, // Inst #2752 = PseudoVFWADD_VV_M1 + {8, OperandInfo298}, // Inst #2753 = PseudoVFWADD_VV_M1_MASK + {5, OperandInfo299}, // Inst #2754 = PseudoVFWADD_VV_M2 + {8, OperandInfo300}, // Inst #2755 = PseudoVFWADD_VV_M2_MASK + {5, OperandInfo301}, // Inst #2756 = PseudoVFWADD_VV_M4 + {8, OperandInfo302}, // Inst #2757 = PseudoVFWADD_VV_M4_MASK + {5, OperandInfo303}, // Inst #2758 = PseudoVFWADD_VV_MF2 + {8, OperandInfo304}, // Inst #2759 = PseudoVFWADD_VV_MF2_MASK + {5, OperandInfo303}, // Inst #2760 = PseudoVFWADD_VV_MF4 + {8, OperandInfo304}, // Inst #2761 = PseudoVFWADD_VV_MF4_MASK + {5, OperandInfo303}, // Inst #2762 = PseudoVFWADD_VV_MF8 + {8, OperandInfo304}, // Inst #2763 = PseudoVFWADD_VV_MF8_MASK + {5, OperandInfo132}, // Inst #2764 = PseudoVFWADD_WF16_M1 + {8, OperandInfo133}, // Inst #2765 = PseudoVFWADD_WF16_M1_MASK + {5, OperandInfo134}, // Inst #2766 = PseudoVFWADD_WF16_M2 + {8, OperandInfo135}, // Inst #2767 = PseudoVFWADD_WF16_M2_MASK + {5, OperandInfo136}, // Inst #2768 = PseudoVFWADD_WF16_M4 + {8, OperandInfo137}, // Inst #2769 = PseudoVFWADD_WF16_M4_MASK + {5, OperandInfo130}, // Inst #2770 = PseudoVFWADD_WF16_MF2 + {8, OperandInfo131}, // Inst #2771 = PseudoVFWADD_WF16_MF2_MASK + {5, OperandInfo130}, // Inst #2772 = PseudoVFWADD_WF16_MF4 + {8, OperandInfo131}, // Inst #2773 = PseudoVFWADD_WF16_MF4_MASK + {5, OperandInfo130}, // Inst #2774 = PseudoVFWADD_WF16_MF8 + {8, OperandInfo131}, // Inst #2775 = PseudoVFWADD_WF16_MF8_MASK + {5, OperandInfo140}, // Inst #2776 = PseudoVFWADD_WF32_M1 + {8, OperandInfo141}, // Inst #2777 = PseudoVFWADD_WF32_M1_MASK + {5, OperandInfo142}, // Inst #2778 = PseudoVFWADD_WF32_M2 + {8, OperandInfo143}, // Inst #2779 = PseudoVFWADD_WF32_M2_MASK + {5, OperandInfo144}, // Inst #2780 = PseudoVFWADD_WF32_M4 + {8, OperandInfo145}, // Inst #2781 = PseudoVFWADD_WF32_M4_MASK + {5, OperandInfo138}, // Inst #2782 = PseudoVFWADD_WF32_MF2 + {8, OperandInfo139}, // Inst #2783 = PseudoVFWADD_WF32_MF2_MASK + {5, OperandInfo138}, // Inst #2784 = PseudoVFWADD_WF32_MF4 + {8, OperandInfo139}, // Inst #2785 = PseudoVFWADD_WF32_MF4_MASK + {5, OperandInfo138}, // Inst #2786 = PseudoVFWADD_WF32_MF8 + {8, OperandInfo139}, // Inst #2787 = PseudoVFWADD_WF32_MF8_MASK + {5, OperandInfo305}, // Inst #2788 = PseudoVFWADD_WV_M1 + {8, OperandInfo306}, // Inst #2789 = PseudoVFWADD_WV_M1_MASK + {7, OperandInfo307}, // Inst #2790 = PseudoVFWADD_WV_M1_MASK_TIED + {5, OperandInfo308}, // Inst #2791 = PseudoVFWADD_WV_M1_TIED + {5, OperandInfo309}, // Inst #2792 = PseudoVFWADD_WV_M2 + {8, OperandInfo310}, // Inst #2793 = PseudoVFWADD_WV_M2_MASK + {7, OperandInfo311}, // Inst #2794 = PseudoVFWADD_WV_M2_MASK_TIED + {5, OperandInfo312}, // Inst #2795 = PseudoVFWADD_WV_M2_TIED + {5, OperandInfo313}, // Inst #2796 = PseudoVFWADD_WV_M4 + {8, OperandInfo314}, // Inst #2797 = PseudoVFWADD_WV_M4_MASK + {7, OperandInfo315}, // Inst #2798 = PseudoVFWADD_WV_M4_MASK_TIED + {5, OperandInfo316}, // Inst #2799 = PseudoVFWADD_WV_M4_TIED + {5, OperandInfo303}, // Inst #2800 = PseudoVFWADD_WV_MF2 + {8, OperandInfo304}, // Inst #2801 = PseudoVFWADD_WV_MF2_MASK + {7, OperandInfo253}, // Inst #2802 = PseudoVFWADD_WV_MF2_MASK_TIED + {5, OperandInfo317}, // Inst #2803 = PseudoVFWADD_WV_MF2_TIED + {5, OperandInfo303}, // Inst #2804 = PseudoVFWADD_WV_MF4 + {8, OperandInfo304}, // Inst #2805 = PseudoVFWADD_WV_MF4_MASK + {7, OperandInfo253}, // Inst #2806 = PseudoVFWADD_WV_MF4_MASK_TIED + {5, OperandInfo317}, // Inst #2807 = PseudoVFWADD_WV_MF4_TIED + {5, OperandInfo303}, // Inst #2808 = PseudoVFWADD_WV_MF8 + {8, OperandInfo304}, // Inst #2809 = PseudoVFWADD_WV_MF8_MASK + {7, OperandInfo253}, // Inst #2810 = PseudoVFWADD_WV_MF8_MASK_TIED + {5, OperandInfo317}, // Inst #2811 = PseudoVFWADD_WV_MF8_TIED + {4, OperandInfo318}, // Inst #2812 = PseudoVFWCVT_F_F_V_M1 + {7, OperandInfo307}, // Inst #2813 = PseudoVFWCVT_F_F_V_M1_MASK + {4, OperandInfo319}, // Inst #2814 = PseudoVFWCVT_F_F_V_M2 + {7, OperandInfo311}, // Inst #2815 = PseudoVFWCVT_F_F_V_M2_MASK + {4, OperandInfo320}, // Inst #2816 = PseudoVFWCVT_F_F_V_M4 + {7, OperandInfo315}, // Inst #2817 = PseudoVFWCVT_F_F_V_M4_MASK + {4, OperandInfo252}, // Inst #2818 = PseudoVFWCVT_F_F_V_MF2 + {7, OperandInfo253}, // Inst #2819 = PseudoVFWCVT_F_F_V_MF2_MASK + {4, OperandInfo252}, // Inst #2820 = PseudoVFWCVT_F_F_V_MF4 + {7, OperandInfo253}, // Inst #2821 = PseudoVFWCVT_F_F_V_MF4_MASK + {4, OperandInfo252}, // Inst #2822 = PseudoVFWCVT_F_F_V_MF8 + {7, OperandInfo253}, // Inst #2823 = PseudoVFWCVT_F_F_V_MF8_MASK + {4, OperandInfo318}, // Inst #2824 = PseudoVFWCVT_F_XU_V_M1 + {7, OperandInfo307}, // Inst #2825 = PseudoVFWCVT_F_XU_V_M1_MASK + {4, OperandInfo319}, // Inst #2826 = PseudoVFWCVT_F_XU_V_M2 + {7, OperandInfo311}, // Inst #2827 = PseudoVFWCVT_F_XU_V_M2_MASK + {4, OperandInfo320}, // Inst #2828 = PseudoVFWCVT_F_XU_V_M4 + {7, OperandInfo315}, // Inst #2829 = PseudoVFWCVT_F_XU_V_M4_MASK + {4, OperandInfo252}, // Inst #2830 = PseudoVFWCVT_F_XU_V_MF2 + {7, OperandInfo253}, // Inst #2831 = PseudoVFWCVT_F_XU_V_MF2_MASK + {4, OperandInfo252}, // Inst #2832 = PseudoVFWCVT_F_XU_V_MF4 + {7, OperandInfo253}, // Inst #2833 = PseudoVFWCVT_F_XU_V_MF4_MASK + {4, OperandInfo252}, // Inst #2834 = PseudoVFWCVT_F_XU_V_MF8 + {7, OperandInfo253}, // Inst #2835 = PseudoVFWCVT_F_XU_V_MF8_MASK + {4, OperandInfo318}, // Inst #2836 = PseudoVFWCVT_F_X_V_M1 + {7, OperandInfo307}, // Inst #2837 = PseudoVFWCVT_F_X_V_M1_MASK + {4, OperandInfo319}, // Inst #2838 = PseudoVFWCVT_F_X_V_M2 + {7, OperandInfo311}, // Inst #2839 = PseudoVFWCVT_F_X_V_M2_MASK + {4, OperandInfo320}, // Inst #2840 = PseudoVFWCVT_F_X_V_M4 + {7, OperandInfo315}, // Inst #2841 = PseudoVFWCVT_F_X_V_M4_MASK + {4, OperandInfo252}, // Inst #2842 = PseudoVFWCVT_F_X_V_MF2 + {7, OperandInfo253}, // Inst #2843 = PseudoVFWCVT_F_X_V_MF2_MASK + {4, OperandInfo252}, // Inst #2844 = PseudoVFWCVT_F_X_V_MF4 + {7, OperandInfo253}, // Inst #2845 = PseudoVFWCVT_F_X_V_MF4_MASK + {4, OperandInfo252}, // Inst #2846 = PseudoVFWCVT_F_X_V_MF8 + {7, OperandInfo253}, // Inst #2847 = PseudoVFWCVT_F_X_V_MF8_MASK + {4, OperandInfo318}, // Inst #2848 = PseudoVFWCVT_RTZ_XU_F_V_M1 + {7, OperandInfo307}, // Inst #2849 = PseudoVFWCVT_RTZ_XU_F_V_M1_MASK + {4, OperandInfo319}, // Inst #2850 = PseudoVFWCVT_RTZ_XU_F_V_M2 + {7, OperandInfo311}, // Inst #2851 = PseudoVFWCVT_RTZ_XU_F_V_M2_MASK + {4, OperandInfo320}, // Inst #2852 = PseudoVFWCVT_RTZ_XU_F_V_M4 + {7, OperandInfo315}, // Inst #2853 = PseudoVFWCVT_RTZ_XU_F_V_M4_MASK + {4, OperandInfo252}, // Inst #2854 = PseudoVFWCVT_RTZ_XU_F_V_MF2 + {7, OperandInfo253}, // Inst #2855 = PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK + {4, OperandInfo252}, // Inst #2856 = PseudoVFWCVT_RTZ_XU_F_V_MF4 + {7, OperandInfo253}, // Inst #2857 = PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK + {4, OperandInfo252}, // Inst #2858 = PseudoVFWCVT_RTZ_XU_F_V_MF8 + {7, OperandInfo253}, // Inst #2859 = PseudoVFWCVT_RTZ_XU_F_V_MF8_MASK + {4, OperandInfo318}, // Inst #2860 = PseudoVFWCVT_RTZ_X_F_V_M1 + {7, OperandInfo307}, // Inst #2861 = PseudoVFWCVT_RTZ_X_F_V_M1_MASK + {4, OperandInfo319}, // Inst #2862 = PseudoVFWCVT_RTZ_X_F_V_M2 + {7, OperandInfo311}, // Inst #2863 = PseudoVFWCVT_RTZ_X_F_V_M2_MASK + {4, OperandInfo320}, // Inst #2864 = PseudoVFWCVT_RTZ_X_F_V_M4 + {7, OperandInfo315}, // Inst #2865 = PseudoVFWCVT_RTZ_X_F_V_M4_MASK + {4, OperandInfo252}, // Inst #2866 = PseudoVFWCVT_RTZ_X_F_V_MF2 + {7, OperandInfo253}, // Inst #2867 = PseudoVFWCVT_RTZ_X_F_V_MF2_MASK + {4, OperandInfo252}, // Inst #2868 = PseudoVFWCVT_RTZ_X_F_V_MF4 + {7, OperandInfo253}, // Inst #2869 = PseudoVFWCVT_RTZ_X_F_V_MF4_MASK + {4, OperandInfo252}, // Inst #2870 = PseudoVFWCVT_RTZ_X_F_V_MF8 + {7, OperandInfo253}, // Inst #2871 = PseudoVFWCVT_RTZ_X_F_V_MF8_MASK + {4, OperandInfo318}, // Inst #2872 = PseudoVFWCVT_XU_F_V_M1 + {7, OperandInfo307}, // Inst #2873 = PseudoVFWCVT_XU_F_V_M1_MASK + {4, OperandInfo319}, // Inst #2874 = PseudoVFWCVT_XU_F_V_M2 + {7, OperandInfo311}, // Inst #2875 = PseudoVFWCVT_XU_F_V_M2_MASK + {4, OperandInfo320}, // Inst #2876 = PseudoVFWCVT_XU_F_V_M4 + {7, OperandInfo315}, // Inst #2877 = PseudoVFWCVT_XU_F_V_M4_MASK + {4, OperandInfo252}, // Inst #2878 = PseudoVFWCVT_XU_F_V_MF2 + {7, OperandInfo253}, // Inst #2879 = PseudoVFWCVT_XU_F_V_MF2_MASK + {4, OperandInfo252}, // Inst #2880 = PseudoVFWCVT_XU_F_V_MF4 + {7, OperandInfo253}, // Inst #2881 = PseudoVFWCVT_XU_F_V_MF4_MASK + {4, OperandInfo252}, // Inst #2882 = PseudoVFWCVT_XU_F_V_MF8 + {7, OperandInfo253}, // Inst #2883 = PseudoVFWCVT_XU_F_V_MF8_MASK + {4, OperandInfo318}, // Inst #2884 = PseudoVFWCVT_X_F_V_M1 + {7, OperandInfo307}, // Inst #2885 = PseudoVFWCVT_X_F_V_M1_MASK + {4, OperandInfo319}, // Inst #2886 = PseudoVFWCVT_X_F_V_M2 + {7, OperandInfo311}, // Inst #2887 = PseudoVFWCVT_X_F_V_M2_MASK + {4, OperandInfo320}, // Inst #2888 = PseudoVFWCVT_X_F_V_M4 + {7, OperandInfo315}, // Inst #2889 = PseudoVFWCVT_X_F_V_M4_MASK + {4, OperandInfo252}, // Inst #2890 = PseudoVFWCVT_X_F_V_MF2 + {7, OperandInfo253}, // Inst #2891 = PseudoVFWCVT_X_F_V_MF2_MASK + {4, OperandInfo252}, // Inst #2892 = PseudoVFWCVT_X_F_V_MF4 + {7, OperandInfo253}, // Inst #2893 = PseudoVFWCVT_X_F_V_MF4_MASK + {4, OperandInfo252}, // Inst #2894 = PseudoVFWCVT_X_F_V_MF8 + {7, OperandInfo253}, // Inst #2895 = PseudoVFWCVT_X_F_V_MF8_MASK + {7, OperandInfo321}, // Inst #2896 = PseudoVFWMACC_VF16_M1 + {7, OperandInfo322}, // Inst #2897 = PseudoVFWMACC_VF16_M1_MASK + {7, OperandInfo323}, // Inst #2898 = PseudoVFWMACC_VF16_M2 + {7, OperandInfo324}, // Inst #2899 = PseudoVFWMACC_VF16_M2_MASK + {7, OperandInfo325}, // Inst #2900 = PseudoVFWMACC_VF16_M4 + {7, OperandInfo326}, // Inst #2901 = PseudoVFWMACC_VF16_M4_MASK + {7, OperandInfo327}, // Inst #2902 = PseudoVFWMACC_VF16_MF2 + {7, OperandInfo328}, // Inst #2903 = PseudoVFWMACC_VF16_MF2_MASK + {7, OperandInfo327}, // Inst #2904 = PseudoVFWMACC_VF16_MF4 + {7, OperandInfo328}, // Inst #2905 = PseudoVFWMACC_VF16_MF4_MASK + {7, OperandInfo327}, // Inst #2906 = PseudoVFWMACC_VF16_MF8 + {7, OperandInfo328}, // Inst #2907 = PseudoVFWMACC_VF16_MF8_MASK + {7, OperandInfo329}, // Inst #2908 = PseudoVFWMACC_VF32_M1 + {7, OperandInfo330}, // Inst #2909 = PseudoVFWMACC_VF32_M1_MASK + {7, OperandInfo331}, // Inst #2910 = PseudoVFWMACC_VF32_M2 + {7, OperandInfo332}, // Inst #2911 = PseudoVFWMACC_VF32_M2_MASK + {7, OperandInfo333}, // Inst #2912 = PseudoVFWMACC_VF32_M4 + {7, OperandInfo334}, // Inst #2913 = PseudoVFWMACC_VF32_M4_MASK + {7, OperandInfo335}, // Inst #2914 = PseudoVFWMACC_VF32_MF2 + {7, OperandInfo336}, // Inst #2915 = PseudoVFWMACC_VF32_MF2_MASK + {7, OperandInfo335}, // Inst #2916 = PseudoVFWMACC_VF32_MF4 + {7, OperandInfo336}, // Inst #2917 = PseudoVFWMACC_VF32_MF4_MASK + {7, OperandInfo335}, // Inst #2918 = PseudoVFWMACC_VF32_MF8 + {7, OperandInfo336}, // Inst #2919 = PseudoVFWMACC_VF32_MF8_MASK + {7, OperandInfo337}, // Inst #2920 = PseudoVFWMACC_VV_M1 + {7, OperandInfo338}, // Inst #2921 = PseudoVFWMACC_VV_M1_MASK + {7, OperandInfo339}, // Inst #2922 = PseudoVFWMACC_VV_M2 + {7, OperandInfo340}, // Inst #2923 = PseudoVFWMACC_VV_M2_MASK + {7, OperandInfo341}, // Inst #2924 = PseudoVFWMACC_VV_M4 + {7, OperandInfo342}, // Inst #2925 = PseudoVFWMACC_VV_M4_MASK + {7, OperandInfo343}, // Inst #2926 = PseudoVFWMACC_VV_MF2 + {7, OperandInfo344}, // Inst #2927 = PseudoVFWMACC_VV_MF2_MASK + {7, OperandInfo343}, // Inst #2928 = PseudoVFWMACC_VV_MF4 + {7, OperandInfo344}, // Inst #2929 = PseudoVFWMACC_VV_MF4_MASK + {7, OperandInfo343}, // Inst #2930 = PseudoVFWMACC_VV_MF8 + {7, OperandInfo344}, // Inst #2931 = PseudoVFWMACC_VV_MF8_MASK + {7, OperandInfo321}, // Inst #2932 = PseudoVFWMSAC_VF16_M1 + {7, OperandInfo322}, // Inst #2933 = PseudoVFWMSAC_VF16_M1_MASK + {7, OperandInfo323}, // Inst #2934 = PseudoVFWMSAC_VF16_M2 + {7, OperandInfo324}, // Inst #2935 = PseudoVFWMSAC_VF16_M2_MASK + {7, OperandInfo325}, // Inst #2936 = PseudoVFWMSAC_VF16_M4 + {7, OperandInfo326}, // Inst #2937 = PseudoVFWMSAC_VF16_M4_MASK + {7, OperandInfo327}, // Inst #2938 = PseudoVFWMSAC_VF16_MF2 + {7, OperandInfo328}, // Inst #2939 = PseudoVFWMSAC_VF16_MF2_MASK + {7, OperandInfo327}, // Inst #2940 = PseudoVFWMSAC_VF16_MF4 + {7, OperandInfo328}, // Inst #2941 = PseudoVFWMSAC_VF16_MF4_MASK + {7, OperandInfo327}, // Inst #2942 = PseudoVFWMSAC_VF16_MF8 + {7, OperandInfo328}, // Inst #2943 = PseudoVFWMSAC_VF16_MF8_MASK + {7, OperandInfo329}, // Inst #2944 = PseudoVFWMSAC_VF32_M1 + {7, OperandInfo330}, // Inst #2945 = PseudoVFWMSAC_VF32_M1_MASK + {7, OperandInfo331}, // Inst #2946 = PseudoVFWMSAC_VF32_M2 + {7, OperandInfo332}, // Inst #2947 = PseudoVFWMSAC_VF32_M2_MASK + {7, OperandInfo333}, // Inst #2948 = PseudoVFWMSAC_VF32_M4 + {7, OperandInfo334}, // Inst #2949 = PseudoVFWMSAC_VF32_M4_MASK + {7, OperandInfo335}, // Inst #2950 = PseudoVFWMSAC_VF32_MF2 + {7, OperandInfo336}, // Inst #2951 = PseudoVFWMSAC_VF32_MF2_MASK + {7, OperandInfo335}, // Inst #2952 = PseudoVFWMSAC_VF32_MF4 + {7, OperandInfo336}, // Inst #2953 = PseudoVFWMSAC_VF32_MF4_MASK + {7, OperandInfo335}, // Inst #2954 = PseudoVFWMSAC_VF32_MF8 + {7, OperandInfo336}, // Inst #2955 = PseudoVFWMSAC_VF32_MF8_MASK + {7, OperandInfo337}, // Inst #2956 = PseudoVFWMSAC_VV_M1 + {7, OperandInfo338}, // Inst #2957 = PseudoVFWMSAC_VV_M1_MASK + {7, OperandInfo339}, // Inst #2958 = PseudoVFWMSAC_VV_M2 + {7, OperandInfo340}, // Inst #2959 = PseudoVFWMSAC_VV_M2_MASK + {7, OperandInfo341}, // Inst #2960 = PseudoVFWMSAC_VV_M4 + {7, OperandInfo342}, // Inst #2961 = PseudoVFWMSAC_VV_M4_MASK + {7, OperandInfo343}, // Inst #2962 = PseudoVFWMSAC_VV_MF2 + {7, OperandInfo344}, // Inst #2963 = PseudoVFWMSAC_VV_MF2_MASK + {7, OperandInfo343}, // Inst #2964 = PseudoVFWMSAC_VV_MF4 + {7, OperandInfo344}, // Inst #2965 = PseudoVFWMSAC_VV_MF4_MASK + {7, OperandInfo343}, // Inst #2966 = PseudoVFWMSAC_VV_MF8 + {7, OperandInfo344}, // Inst #2967 = PseudoVFWMSAC_VV_MF8_MASK + {5, OperandInfo285}, // Inst #2968 = PseudoVFWMUL_VF16_M1 + {8, OperandInfo286}, // Inst #2969 = PseudoVFWMUL_VF16_M1_MASK + {5, OperandInfo287}, // Inst #2970 = PseudoVFWMUL_VF16_M2 + {8, OperandInfo288}, // Inst #2971 = PseudoVFWMUL_VF16_M2_MASK + {5, OperandInfo289}, // Inst #2972 = PseudoVFWMUL_VF16_M4 + {8, OperandInfo290}, // Inst #2973 = PseudoVFWMUL_VF16_M4_MASK + {5, OperandInfo261}, // Inst #2974 = PseudoVFWMUL_VF16_MF2 + {8, OperandInfo262}, // Inst #2975 = PseudoVFWMUL_VF16_MF2_MASK + {5, OperandInfo261}, // Inst #2976 = PseudoVFWMUL_VF16_MF4 + {8, OperandInfo262}, // Inst #2977 = PseudoVFWMUL_VF16_MF4_MASK + {5, OperandInfo261}, // Inst #2978 = PseudoVFWMUL_VF16_MF8 + {8, OperandInfo262}, // Inst #2979 = PseudoVFWMUL_VF16_MF8_MASK + {5, OperandInfo291}, // Inst #2980 = PseudoVFWMUL_VF32_M1 + {8, OperandInfo292}, // Inst #2981 = PseudoVFWMUL_VF32_M1_MASK + {5, OperandInfo293}, // Inst #2982 = PseudoVFWMUL_VF32_M2 + {8, OperandInfo294}, // Inst #2983 = PseudoVFWMUL_VF32_M2_MASK + {5, OperandInfo295}, // Inst #2984 = PseudoVFWMUL_VF32_M4 + {8, OperandInfo296}, // Inst #2985 = PseudoVFWMUL_VF32_M4_MASK + {5, OperandInfo269}, // Inst #2986 = PseudoVFWMUL_VF32_MF2 + {8, OperandInfo270}, // Inst #2987 = PseudoVFWMUL_VF32_MF2_MASK + {5, OperandInfo269}, // Inst #2988 = PseudoVFWMUL_VF32_MF4 + {8, OperandInfo270}, // Inst #2989 = PseudoVFWMUL_VF32_MF4_MASK + {5, OperandInfo269}, // Inst #2990 = PseudoVFWMUL_VF32_MF8 + {8, OperandInfo270}, // Inst #2991 = PseudoVFWMUL_VF32_MF8_MASK + {5, OperandInfo297}, // Inst #2992 = PseudoVFWMUL_VV_M1 + {8, OperandInfo298}, // Inst #2993 = PseudoVFWMUL_VV_M1_MASK + {5, OperandInfo299}, // Inst #2994 = PseudoVFWMUL_VV_M2 + {8, OperandInfo300}, // Inst #2995 = PseudoVFWMUL_VV_M2_MASK + {5, OperandInfo301}, // Inst #2996 = PseudoVFWMUL_VV_M4 + {8, OperandInfo302}, // Inst #2997 = PseudoVFWMUL_VV_M4_MASK + {5, OperandInfo303}, // Inst #2998 = PseudoVFWMUL_VV_MF2 + {8, OperandInfo304}, // Inst #2999 = PseudoVFWMUL_VV_MF2_MASK + {5, OperandInfo303}, // Inst #3000 = PseudoVFWMUL_VV_MF4 + {8, OperandInfo304}, // Inst #3001 = PseudoVFWMUL_VV_MF4_MASK + {5, OperandInfo303}, // Inst #3002 = PseudoVFWMUL_VV_MF8 + {8, OperandInfo304}, // Inst #3003 = PseudoVFWMUL_VV_MF8_MASK + {7, OperandInfo321}, // Inst #3004 = PseudoVFWNMACC_VF16_M1 + {7, OperandInfo322}, // Inst #3005 = PseudoVFWNMACC_VF16_M1_MASK + {7, OperandInfo323}, // Inst #3006 = PseudoVFWNMACC_VF16_M2 + {7, OperandInfo324}, // Inst #3007 = PseudoVFWNMACC_VF16_M2_MASK + {7, OperandInfo325}, // Inst #3008 = PseudoVFWNMACC_VF16_M4 + {7, OperandInfo326}, // Inst #3009 = PseudoVFWNMACC_VF16_M4_MASK + {7, OperandInfo327}, // Inst #3010 = PseudoVFWNMACC_VF16_MF2 + {7, OperandInfo328}, // Inst #3011 = PseudoVFWNMACC_VF16_MF2_MASK + {7, OperandInfo327}, // Inst #3012 = PseudoVFWNMACC_VF16_MF4 + {7, OperandInfo328}, // Inst #3013 = PseudoVFWNMACC_VF16_MF4_MASK + {7, OperandInfo327}, // Inst #3014 = PseudoVFWNMACC_VF16_MF8 + {7, OperandInfo328}, // Inst #3015 = PseudoVFWNMACC_VF16_MF8_MASK + {7, OperandInfo329}, // Inst #3016 = PseudoVFWNMACC_VF32_M1 + {7, OperandInfo330}, // Inst #3017 = PseudoVFWNMACC_VF32_M1_MASK + {7, OperandInfo331}, // Inst #3018 = PseudoVFWNMACC_VF32_M2 + {7, OperandInfo332}, // Inst #3019 = PseudoVFWNMACC_VF32_M2_MASK + {7, OperandInfo333}, // Inst #3020 = PseudoVFWNMACC_VF32_M4 + {7, OperandInfo334}, // Inst #3021 = PseudoVFWNMACC_VF32_M4_MASK + {7, OperandInfo335}, // Inst #3022 = PseudoVFWNMACC_VF32_MF2 + {7, OperandInfo336}, // Inst #3023 = PseudoVFWNMACC_VF32_MF2_MASK + {7, OperandInfo335}, // Inst #3024 = PseudoVFWNMACC_VF32_MF4 + {7, OperandInfo336}, // Inst #3025 = PseudoVFWNMACC_VF32_MF4_MASK + {7, OperandInfo335}, // Inst #3026 = PseudoVFWNMACC_VF32_MF8 + {7, OperandInfo336}, // Inst #3027 = PseudoVFWNMACC_VF32_MF8_MASK + {7, OperandInfo337}, // Inst #3028 = PseudoVFWNMACC_VV_M1 + {7, OperandInfo338}, // Inst #3029 = PseudoVFWNMACC_VV_M1_MASK + {7, OperandInfo339}, // Inst #3030 = PseudoVFWNMACC_VV_M2 + {7, OperandInfo340}, // Inst #3031 = PseudoVFWNMACC_VV_M2_MASK + {7, OperandInfo341}, // Inst #3032 = PseudoVFWNMACC_VV_M4 + {7, OperandInfo342}, // Inst #3033 = PseudoVFWNMACC_VV_M4_MASK + {7, OperandInfo343}, // Inst #3034 = PseudoVFWNMACC_VV_MF2 + {7, OperandInfo344}, // Inst #3035 = PseudoVFWNMACC_VV_MF2_MASK + {7, OperandInfo343}, // Inst #3036 = PseudoVFWNMACC_VV_MF4 + {7, OperandInfo344}, // Inst #3037 = PseudoVFWNMACC_VV_MF4_MASK + {7, OperandInfo343}, // Inst #3038 = PseudoVFWNMACC_VV_MF8 + {7, OperandInfo344}, // Inst #3039 = PseudoVFWNMACC_VV_MF8_MASK + {7, OperandInfo321}, // Inst #3040 = PseudoVFWNMSAC_VF16_M1 + {7, OperandInfo322}, // Inst #3041 = PseudoVFWNMSAC_VF16_M1_MASK + {7, OperandInfo323}, // Inst #3042 = PseudoVFWNMSAC_VF16_M2 + {7, OperandInfo324}, // Inst #3043 = PseudoVFWNMSAC_VF16_M2_MASK + {7, OperandInfo325}, // Inst #3044 = PseudoVFWNMSAC_VF16_M4 + {7, OperandInfo326}, // Inst #3045 = PseudoVFWNMSAC_VF16_M4_MASK + {7, OperandInfo327}, // Inst #3046 = PseudoVFWNMSAC_VF16_MF2 + {7, OperandInfo328}, // Inst #3047 = PseudoVFWNMSAC_VF16_MF2_MASK + {7, OperandInfo327}, // Inst #3048 = PseudoVFWNMSAC_VF16_MF4 + {7, OperandInfo328}, // Inst #3049 = PseudoVFWNMSAC_VF16_MF4_MASK + {7, OperandInfo327}, // Inst #3050 = PseudoVFWNMSAC_VF16_MF8 + {7, OperandInfo328}, // Inst #3051 = PseudoVFWNMSAC_VF16_MF8_MASK + {7, OperandInfo329}, // Inst #3052 = PseudoVFWNMSAC_VF32_M1 + {7, OperandInfo330}, // Inst #3053 = PseudoVFWNMSAC_VF32_M1_MASK + {7, OperandInfo331}, // Inst #3054 = PseudoVFWNMSAC_VF32_M2 + {7, OperandInfo332}, // Inst #3055 = PseudoVFWNMSAC_VF32_M2_MASK + {7, OperandInfo333}, // Inst #3056 = PseudoVFWNMSAC_VF32_M4 + {7, OperandInfo334}, // Inst #3057 = PseudoVFWNMSAC_VF32_M4_MASK + {7, OperandInfo335}, // Inst #3058 = PseudoVFWNMSAC_VF32_MF2 + {7, OperandInfo336}, // Inst #3059 = PseudoVFWNMSAC_VF32_MF2_MASK + {7, OperandInfo335}, // Inst #3060 = PseudoVFWNMSAC_VF32_MF4 + {7, OperandInfo336}, // Inst #3061 = PseudoVFWNMSAC_VF32_MF4_MASK + {7, OperandInfo335}, // Inst #3062 = PseudoVFWNMSAC_VF32_MF8 + {7, OperandInfo336}, // Inst #3063 = PseudoVFWNMSAC_VF32_MF8_MASK + {7, OperandInfo337}, // Inst #3064 = PseudoVFWNMSAC_VV_M1 + {7, OperandInfo338}, // Inst #3065 = PseudoVFWNMSAC_VV_M1_MASK + {7, OperandInfo339}, // Inst #3066 = PseudoVFWNMSAC_VV_M2 + {7, OperandInfo340}, // Inst #3067 = PseudoVFWNMSAC_VV_M2_MASK + {7, OperandInfo341}, // Inst #3068 = PseudoVFWNMSAC_VV_M4 + {7, OperandInfo342}, // Inst #3069 = PseudoVFWNMSAC_VV_M4_MASK + {7, OperandInfo343}, // Inst #3070 = PseudoVFWNMSAC_VV_MF2 + {7, OperandInfo344}, // Inst #3071 = PseudoVFWNMSAC_VV_MF2_MASK + {7, OperandInfo343}, // Inst #3072 = PseudoVFWNMSAC_VV_MF4 + {7, OperandInfo344}, // Inst #3073 = PseudoVFWNMSAC_VV_MF4_MASK + {7, OperandInfo343}, // Inst #3074 = PseudoVFWNMSAC_VV_MF8 + {7, OperandInfo344}, // Inst #3075 = PseudoVFWNMSAC_VV_MF8_MASK + {6, OperandInfo254}, // Inst #3076 = PseudoVFWREDOSUM_VS_M1 + {7, OperandInfo191}, // Inst #3077 = PseudoVFWREDOSUM_VS_M1_MASK + {6, OperandInfo255}, // Inst #3078 = PseudoVFWREDOSUM_VS_M2 + {7, OperandInfo256}, // Inst #3079 = PseudoVFWREDOSUM_VS_M2_MASK + {6, OperandInfo257}, // Inst #3080 = PseudoVFWREDOSUM_VS_M4 + {7, OperandInfo258}, // Inst #3081 = PseudoVFWREDOSUM_VS_M4_MASK + {6, OperandInfo259}, // Inst #3082 = PseudoVFWREDOSUM_VS_M8 + {7, OperandInfo260}, // Inst #3083 = PseudoVFWREDOSUM_VS_M8_MASK + {6, OperandInfo254}, // Inst #3084 = PseudoVFWREDOSUM_VS_MF2 + {7, OperandInfo191}, // Inst #3085 = PseudoVFWREDOSUM_VS_MF2_MASK + {6, OperandInfo254}, // Inst #3086 = PseudoVFWREDOSUM_VS_MF4 + {7, OperandInfo191}, // Inst #3087 = PseudoVFWREDOSUM_VS_MF4_MASK + {6, OperandInfo254}, // Inst #3088 = PseudoVFWREDOSUM_VS_MF8 + {7, OperandInfo191}, // Inst #3089 = PseudoVFWREDOSUM_VS_MF8_MASK + {6, OperandInfo254}, // Inst #3090 = PseudoVFWREDUSUM_VS_M1 + {7, OperandInfo191}, // Inst #3091 = PseudoVFWREDUSUM_VS_M1_MASK + {6, OperandInfo255}, // Inst #3092 = PseudoVFWREDUSUM_VS_M2 + {7, OperandInfo256}, // Inst #3093 = PseudoVFWREDUSUM_VS_M2_MASK + {6, OperandInfo257}, // Inst #3094 = PseudoVFWREDUSUM_VS_M4 + {7, OperandInfo258}, // Inst #3095 = PseudoVFWREDUSUM_VS_M4_MASK + {6, OperandInfo259}, // Inst #3096 = PseudoVFWREDUSUM_VS_M8 + {7, OperandInfo260}, // Inst #3097 = PseudoVFWREDUSUM_VS_M8_MASK + {6, OperandInfo254}, // Inst #3098 = PseudoVFWREDUSUM_VS_MF2 + {7, OperandInfo191}, // Inst #3099 = PseudoVFWREDUSUM_VS_MF2_MASK + {6, OperandInfo254}, // Inst #3100 = PseudoVFWREDUSUM_VS_MF4 + {7, OperandInfo191}, // Inst #3101 = PseudoVFWREDUSUM_VS_MF4_MASK + {6, OperandInfo254}, // Inst #3102 = PseudoVFWREDUSUM_VS_MF8 + {7, OperandInfo191}, // Inst #3103 = PseudoVFWREDUSUM_VS_MF8_MASK + {5, OperandInfo285}, // Inst #3104 = PseudoVFWSUB_VF16_M1 + {8, OperandInfo286}, // Inst #3105 = PseudoVFWSUB_VF16_M1_MASK + {5, OperandInfo287}, // Inst #3106 = PseudoVFWSUB_VF16_M2 + {8, OperandInfo288}, // Inst #3107 = PseudoVFWSUB_VF16_M2_MASK + {5, OperandInfo289}, // Inst #3108 = PseudoVFWSUB_VF16_M4 + {8, OperandInfo290}, // Inst #3109 = PseudoVFWSUB_VF16_M4_MASK + {5, OperandInfo261}, // Inst #3110 = PseudoVFWSUB_VF16_MF2 + {8, OperandInfo262}, // Inst #3111 = PseudoVFWSUB_VF16_MF2_MASK + {5, OperandInfo261}, // Inst #3112 = PseudoVFWSUB_VF16_MF4 + {8, OperandInfo262}, // Inst #3113 = PseudoVFWSUB_VF16_MF4_MASK + {5, OperandInfo261}, // Inst #3114 = PseudoVFWSUB_VF16_MF8 + {8, OperandInfo262}, // Inst #3115 = PseudoVFWSUB_VF16_MF8_MASK + {5, OperandInfo291}, // Inst #3116 = PseudoVFWSUB_VF32_M1 + {8, OperandInfo292}, // Inst #3117 = PseudoVFWSUB_VF32_M1_MASK + {5, OperandInfo293}, // Inst #3118 = PseudoVFWSUB_VF32_M2 + {8, OperandInfo294}, // Inst #3119 = PseudoVFWSUB_VF32_M2_MASK + {5, OperandInfo295}, // Inst #3120 = PseudoVFWSUB_VF32_M4 + {8, OperandInfo296}, // Inst #3121 = PseudoVFWSUB_VF32_M4_MASK + {5, OperandInfo269}, // Inst #3122 = PseudoVFWSUB_VF32_MF2 + {8, OperandInfo270}, // Inst #3123 = PseudoVFWSUB_VF32_MF2_MASK + {5, OperandInfo269}, // Inst #3124 = PseudoVFWSUB_VF32_MF4 + {8, OperandInfo270}, // Inst #3125 = PseudoVFWSUB_VF32_MF4_MASK + {5, OperandInfo269}, // Inst #3126 = PseudoVFWSUB_VF32_MF8 + {8, OperandInfo270}, // Inst #3127 = PseudoVFWSUB_VF32_MF8_MASK + {5, OperandInfo297}, // Inst #3128 = PseudoVFWSUB_VV_M1 + {8, OperandInfo298}, // Inst #3129 = PseudoVFWSUB_VV_M1_MASK + {5, OperandInfo299}, // Inst #3130 = PseudoVFWSUB_VV_M2 + {8, OperandInfo300}, // Inst #3131 = PseudoVFWSUB_VV_M2_MASK + {5, OperandInfo301}, // Inst #3132 = PseudoVFWSUB_VV_M4 + {8, OperandInfo302}, // Inst #3133 = PseudoVFWSUB_VV_M4_MASK + {5, OperandInfo303}, // Inst #3134 = PseudoVFWSUB_VV_MF2 + {8, OperandInfo304}, // Inst #3135 = PseudoVFWSUB_VV_MF2_MASK + {5, OperandInfo303}, // Inst #3136 = PseudoVFWSUB_VV_MF4 + {8, OperandInfo304}, // Inst #3137 = PseudoVFWSUB_VV_MF4_MASK + {5, OperandInfo303}, // Inst #3138 = PseudoVFWSUB_VV_MF8 + {8, OperandInfo304}, // Inst #3139 = PseudoVFWSUB_VV_MF8_MASK + {5, OperandInfo132}, // Inst #3140 = PseudoVFWSUB_WF16_M1 + {8, OperandInfo133}, // Inst #3141 = PseudoVFWSUB_WF16_M1_MASK + {5, OperandInfo134}, // Inst #3142 = PseudoVFWSUB_WF16_M2 + {8, OperandInfo135}, // Inst #3143 = PseudoVFWSUB_WF16_M2_MASK + {5, OperandInfo136}, // Inst #3144 = PseudoVFWSUB_WF16_M4 + {8, OperandInfo137}, // Inst #3145 = PseudoVFWSUB_WF16_M4_MASK + {5, OperandInfo130}, // Inst #3146 = PseudoVFWSUB_WF16_MF2 + {8, OperandInfo131}, // Inst #3147 = PseudoVFWSUB_WF16_MF2_MASK + {5, OperandInfo130}, // Inst #3148 = PseudoVFWSUB_WF16_MF4 + {8, OperandInfo131}, // Inst #3149 = PseudoVFWSUB_WF16_MF4_MASK + {5, OperandInfo130}, // Inst #3150 = PseudoVFWSUB_WF16_MF8 + {8, OperandInfo131}, // Inst #3151 = PseudoVFWSUB_WF16_MF8_MASK + {5, OperandInfo140}, // Inst #3152 = PseudoVFWSUB_WF32_M1 + {8, OperandInfo141}, // Inst #3153 = PseudoVFWSUB_WF32_M1_MASK + {5, OperandInfo142}, // Inst #3154 = PseudoVFWSUB_WF32_M2 + {8, OperandInfo143}, // Inst #3155 = PseudoVFWSUB_WF32_M2_MASK + {5, OperandInfo144}, // Inst #3156 = PseudoVFWSUB_WF32_M4 + {8, OperandInfo145}, // Inst #3157 = PseudoVFWSUB_WF32_M4_MASK + {5, OperandInfo138}, // Inst #3158 = PseudoVFWSUB_WF32_MF2 + {8, OperandInfo139}, // Inst #3159 = PseudoVFWSUB_WF32_MF2_MASK + {5, OperandInfo138}, // Inst #3160 = PseudoVFWSUB_WF32_MF4 + {8, OperandInfo139}, // Inst #3161 = PseudoVFWSUB_WF32_MF4_MASK + {5, OperandInfo138}, // Inst #3162 = PseudoVFWSUB_WF32_MF8 + {8, OperandInfo139}, // Inst #3163 = PseudoVFWSUB_WF32_MF8_MASK + {5, OperandInfo305}, // Inst #3164 = PseudoVFWSUB_WV_M1 + {8, OperandInfo306}, // Inst #3165 = PseudoVFWSUB_WV_M1_MASK + {7, OperandInfo307}, // Inst #3166 = PseudoVFWSUB_WV_M1_MASK_TIED + {5, OperandInfo308}, // Inst #3167 = PseudoVFWSUB_WV_M1_TIED + {5, OperandInfo309}, // Inst #3168 = PseudoVFWSUB_WV_M2 + {8, OperandInfo310}, // Inst #3169 = PseudoVFWSUB_WV_M2_MASK + {7, OperandInfo311}, // Inst #3170 = PseudoVFWSUB_WV_M2_MASK_TIED + {5, OperandInfo312}, // Inst #3171 = PseudoVFWSUB_WV_M2_TIED + {5, OperandInfo313}, // Inst #3172 = PseudoVFWSUB_WV_M4 + {8, OperandInfo314}, // Inst #3173 = PseudoVFWSUB_WV_M4_MASK + {7, OperandInfo315}, // Inst #3174 = PseudoVFWSUB_WV_M4_MASK_TIED + {5, OperandInfo316}, // Inst #3175 = PseudoVFWSUB_WV_M4_TIED + {5, OperandInfo303}, // Inst #3176 = PseudoVFWSUB_WV_MF2 + {8, OperandInfo304}, // Inst #3177 = PseudoVFWSUB_WV_MF2_MASK + {7, OperandInfo253}, // Inst #3178 = PseudoVFWSUB_WV_MF2_MASK_TIED + {5, OperandInfo317}, // Inst #3179 = PseudoVFWSUB_WV_MF2_TIED + {5, OperandInfo303}, // Inst #3180 = PseudoVFWSUB_WV_MF4 + {8, OperandInfo304}, // Inst #3181 = PseudoVFWSUB_WV_MF4_MASK + {7, OperandInfo253}, // Inst #3182 = PseudoVFWSUB_WV_MF4_MASK_TIED + {5, OperandInfo317}, // Inst #3183 = PseudoVFWSUB_WV_MF4_TIED + {5, OperandInfo303}, // Inst #3184 = PseudoVFWSUB_WV_MF8 + {8, OperandInfo304}, // Inst #3185 = PseudoVFWSUB_WV_MF8_MASK + {7, OperandInfo253}, // Inst #3186 = PseudoVFWSUB_WV_MF8_MASK_TIED + {5, OperandInfo317}, // Inst #3187 = PseudoVFWSUB_WV_MF8_TIED + {3, OperandInfo345}, // Inst #3188 = PseudoVID_V_M1 + {5, OperandInfo346}, // Inst #3189 = PseudoVID_V_M1_MASK + {3, OperandInfo347}, // Inst #3190 = PseudoVID_V_M2 + {5, OperandInfo348}, // Inst #3191 = PseudoVID_V_M2_MASK + {3, OperandInfo349}, // Inst #3192 = PseudoVID_V_M4 + {5, OperandInfo350}, // Inst #3193 = PseudoVID_V_M4_MASK + {3, OperandInfo351}, // Inst #3194 = PseudoVID_V_M8 + {5, OperandInfo352}, // Inst #3195 = PseudoVID_V_M8_MASK + {3, OperandInfo345}, // Inst #3196 = PseudoVID_V_MF2 + {5, OperandInfo346}, // Inst #3197 = PseudoVID_V_MF2_MASK + {3, OperandInfo345}, // Inst #3198 = PseudoVID_V_MF4 + {5, OperandInfo346}, // Inst #3199 = PseudoVID_V_MF4_MASK + {3, OperandInfo345}, // Inst #3200 = PseudoVID_V_MF8 + {5, OperandInfo346}, // Inst #3201 = PseudoVID_V_MF8_MASK + {4, OperandInfo252}, // Inst #3202 = PseudoVIOTA_M_M1 + {6, OperandInfo353}, // Inst #3203 = PseudoVIOTA_M_M1_MASK + {4, OperandInfo318}, // Inst #3204 = PseudoVIOTA_M_M2 + {6, OperandInfo354}, // Inst #3205 = PseudoVIOTA_M_M2_MASK + {4, OperandInfo355}, // Inst #3206 = PseudoVIOTA_M_M4 + {6, OperandInfo356}, // Inst #3207 = PseudoVIOTA_M_M4_MASK + {4, OperandInfo357}, // Inst #3208 = PseudoVIOTA_M_M8 + {6, OperandInfo358}, // Inst #3209 = PseudoVIOTA_M_M8_MASK + {4, OperandInfo252}, // Inst #3210 = PseudoVIOTA_M_MF2 + {6, OperandInfo353}, // Inst #3211 = PseudoVIOTA_M_MF2_MASK + {4, OperandInfo252}, // Inst #3212 = PseudoVIOTA_M_MF4 + {6, OperandInfo353}, // Inst #3213 = PseudoVIOTA_M_MF4_MASK + {4, OperandInfo252}, // Inst #3214 = PseudoVIOTA_M_MF8 + {6, OperandInfo353}, // Inst #3215 = PseudoVIOTA_M_MF8_MASK + {4, OperandInfo359}, // Inst #3216 = PseudoVLE16FF_V_M1 + {7, OperandInfo360}, // Inst #3217 = PseudoVLE16FF_V_M1_MASK + {4, OperandInfo361}, // Inst #3218 = PseudoVLE16FF_V_M2 + {7, OperandInfo362}, // Inst #3219 = PseudoVLE16FF_V_M2_MASK + {4, OperandInfo363}, // Inst #3220 = PseudoVLE16FF_V_M4 + {7, OperandInfo364}, // Inst #3221 = PseudoVLE16FF_V_M4_MASK + {4, OperandInfo365}, // Inst #3222 = PseudoVLE16FF_V_M8 + {7, OperandInfo366}, // Inst #3223 = PseudoVLE16FF_V_M8_MASK + {4, OperandInfo359}, // Inst #3224 = PseudoVLE16FF_V_MF2 + {7, OperandInfo360}, // Inst #3225 = PseudoVLE16FF_V_MF2_MASK + {4, OperandInfo359}, // Inst #3226 = PseudoVLE16FF_V_MF4 + {7, OperandInfo360}, // Inst #3227 = PseudoVLE16FF_V_MF4_MASK + {4, OperandInfo359}, // Inst #3228 = PseudoVLE16_V_M1 + {7, OperandInfo360}, // Inst #3229 = PseudoVLE16_V_M1_MASK + {4, OperandInfo361}, // Inst #3230 = PseudoVLE16_V_M2 + {7, OperandInfo362}, // Inst #3231 = PseudoVLE16_V_M2_MASK + {4, OperandInfo363}, // Inst #3232 = PseudoVLE16_V_M4 + {7, OperandInfo364}, // Inst #3233 = PseudoVLE16_V_M4_MASK + {4, OperandInfo365}, // Inst #3234 = PseudoVLE16_V_M8 + {7, OperandInfo366}, // Inst #3235 = PseudoVLE16_V_M8_MASK + {4, OperandInfo359}, // Inst #3236 = PseudoVLE16_V_MF2 + {7, OperandInfo360}, // Inst #3237 = PseudoVLE16_V_MF2_MASK + {4, OperandInfo359}, // Inst #3238 = PseudoVLE16_V_MF4 + {7, OperandInfo360}, // Inst #3239 = PseudoVLE16_V_MF4_MASK + {4, OperandInfo359}, // Inst #3240 = PseudoVLE32FF_V_M1 + {7, OperandInfo360}, // Inst #3241 = PseudoVLE32FF_V_M1_MASK + {4, OperandInfo361}, // Inst #3242 = PseudoVLE32FF_V_M2 + {7, OperandInfo362}, // Inst #3243 = PseudoVLE32FF_V_M2_MASK + {4, OperandInfo363}, // Inst #3244 = PseudoVLE32FF_V_M4 + {7, OperandInfo364}, // Inst #3245 = PseudoVLE32FF_V_M4_MASK + {4, OperandInfo365}, // Inst #3246 = PseudoVLE32FF_V_M8 + {7, OperandInfo366}, // Inst #3247 = PseudoVLE32FF_V_M8_MASK + {4, OperandInfo359}, // Inst #3248 = PseudoVLE32FF_V_MF2 + {7, OperandInfo360}, // Inst #3249 = PseudoVLE32FF_V_MF2_MASK + {4, OperandInfo359}, // Inst #3250 = PseudoVLE32_V_M1 + {7, OperandInfo360}, // Inst #3251 = PseudoVLE32_V_M1_MASK + {4, OperandInfo361}, // Inst #3252 = PseudoVLE32_V_M2 + {7, OperandInfo362}, // Inst #3253 = PseudoVLE32_V_M2_MASK + {4, OperandInfo363}, // Inst #3254 = PseudoVLE32_V_M4 + {7, OperandInfo364}, // Inst #3255 = PseudoVLE32_V_M4_MASK + {4, OperandInfo365}, // Inst #3256 = PseudoVLE32_V_M8 + {7, OperandInfo366}, // Inst #3257 = PseudoVLE32_V_M8_MASK + {4, OperandInfo359}, // Inst #3258 = PseudoVLE32_V_MF2 + {7, OperandInfo360}, // Inst #3259 = PseudoVLE32_V_MF2_MASK + {4, OperandInfo359}, // Inst #3260 = PseudoVLE64FF_V_M1 + {7, OperandInfo360}, // Inst #3261 = PseudoVLE64FF_V_M1_MASK + {4, OperandInfo361}, // Inst #3262 = PseudoVLE64FF_V_M2 + {7, OperandInfo362}, // Inst #3263 = PseudoVLE64FF_V_M2_MASK + {4, OperandInfo363}, // Inst #3264 = PseudoVLE64FF_V_M4 + {7, OperandInfo364}, // Inst #3265 = PseudoVLE64FF_V_M4_MASK + {4, OperandInfo365}, // Inst #3266 = PseudoVLE64FF_V_M8 + {7, OperandInfo366}, // Inst #3267 = PseudoVLE64FF_V_M8_MASK + {4, OperandInfo359}, // Inst #3268 = PseudoVLE64_V_M1 + {7, OperandInfo360}, // Inst #3269 = PseudoVLE64_V_M1_MASK + {4, OperandInfo361}, // Inst #3270 = PseudoVLE64_V_M2 + {7, OperandInfo362}, // Inst #3271 = PseudoVLE64_V_M2_MASK + {4, OperandInfo363}, // Inst #3272 = PseudoVLE64_V_M4 + {7, OperandInfo364}, // Inst #3273 = PseudoVLE64_V_M4_MASK + {4, OperandInfo365}, // Inst #3274 = PseudoVLE64_V_M8 + {7, OperandInfo366}, // Inst #3275 = PseudoVLE64_V_M8_MASK + {4, OperandInfo359}, // Inst #3276 = PseudoVLE8FF_V_M1 + {7, OperandInfo360}, // Inst #3277 = PseudoVLE8FF_V_M1_MASK + {4, OperandInfo361}, // Inst #3278 = PseudoVLE8FF_V_M2 + {7, OperandInfo362}, // Inst #3279 = PseudoVLE8FF_V_M2_MASK + {4, OperandInfo363}, // Inst #3280 = PseudoVLE8FF_V_M4 + {7, OperandInfo364}, // Inst #3281 = PseudoVLE8FF_V_M4_MASK + {4, OperandInfo365}, // Inst #3282 = PseudoVLE8FF_V_M8 + {7, OperandInfo366}, // Inst #3283 = PseudoVLE8FF_V_M8_MASK + {4, OperandInfo359}, // Inst #3284 = PseudoVLE8FF_V_MF2 + {7, OperandInfo360}, // Inst #3285 = PseudoVLE8FF_V_MF2_MASK + {4, OperandInfo359}, // Inst #3286 = PseudoVLE8FF_V_MF4 + {7, OperandInfo360}, // Inst #3287 = PseudoVLE8FF_V_MF4_MASK + {4, OperandInfo359}, // Inst #3288 = PseudoVLE8FF_V_MF8 + {7, OperandInfo360}, // Inst #3289 = PseudoVLE8FF_V_MF8_MASK + {4, OperandInfo359}, // Inst #3290 = PseudoVLE8_V_M1 + {7, OperandInfo360}, // Inst #3291 = PseudoVLE8_V_M1_MASK + {4, OperandInfo361}, // Inst #3292 = PseudoVLE8_V_M2 + {7, OperandInfo362}, // Inst #3293 = PseudoVLE8_V_M2_MASK + {4, OperandInfo363}, // Inst #3294 = PseudoVLE8_V_M4 + {7, OperandInfo364}, // Inst #3295 = PseudoVLE8_V_M4_MASK + {4, OperandInfo365}, // Inst #3296 = PseudoVLE8_V_M8 + {7, OperandInfo366}, // Inst #3297 = PseudoVLE8_V_M8_MASK + {4, OperandInfo359}, // Inst #3298 = PseudoVLE8_V_MF2 + {7, OperandInfo360}, // Inst #3299 = PseudoVLE8_V_MF2_MASK + {4, OperandInfo359}, // Inst #3300 = PseudoVLE8_V_MF4 + {7, OperandInfo360}, // Inst #3301 = PseudoVLE8_V_MF4_MASK + {4, OperandInfo359}, // Inst #3302 = PseudoVLE8_V_MF8 + {7, OperandInfo360}, // Inst #3303 = PseudoVLE8_V_MF8_MASK + {4, OperandInfo359}, // Inst #3304 = PseudoVLM_V_B1 + {4, OperandInfo359}, // Inst #3305 = PseudoVLM_V_B16 + {4, OperandInfo359}, // Inst #3306 = PseudoVLM_V_B2 + {4, OperandInfo359}, // Inst #3307 = PseudoVLM_V_B32 + {4, OperandInfo359}, // Inst #3308 = PseudoVLM_V_B4 + {4, OperandInfo359}, // Inst #3309 = PseudoVLM_V_B64 + {4, OperandInfo359}, // Inst #3310 = PseudoVLM_V_B8 + {5, OperandInfo367}, // Inst #3311 = PseudoVLOXEI16_V_M1_M1 + {8, OperandInfo368}, // Inst #3312 = PseudoVLOXEI16_V_M1_M1_MASK + {5, OperandInfo369}, // Inst #3313 = PseudoVLOXEI16_V_M1_M2 + {8, OperandInfo370}, // Inst #3314 = PseudoVLOXEI16_V_M1_M2_MASK + {5, OperandInfo371}, // Inst #3315 = PseudoVLOXEI16_V_M1_M4 + {8, OperandInfo372}, // Inst #3316 = PseudoVLOXEI16_V_M1_M4_MASK + {5, OperandInfo373}, // Inst #3317 = PseudoVLOXEI16_V_M1_MF2 + {8, OperandInfo374}, // Inst #3318 = PseudoVLOXEI16_V_M1_MF2_MASK + {5, OperandInfo375}, // Inst #3319 = PseudoVLOXEI16_V_M2_M1 + {8, OperandInfo376}, // Inst #3320 = PseudoVLOXEI16_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #3321 = PseudoVLOXEI16_V_M2_M2 + {8, OperandInfo378}, // Inst #3322 = PseudoVLOXEI16_V_M2_M2_MASK + {5, OperandInfo379}, // Inst #3323 = PseudoVLOXEI16_V_M2_M4 + {8, OperandInfo380}, // Inst #3324 = PseudoVLOXEI16_V_M2_M4_MASK + {5, OperandInfo381}, // Inst #3325 = PseudoVLOXEI16_V_M2_M8 + {8, OperandInfo382}, // Inst #3326 = PseudoVLOXEI16_V_M2_M8_MASK + {5, OperandInfo383}, // Inst #3327 = PseudoVLOXEI16_V_M4_M2 + {8, OperandInfo384}, // Inst #3328 = PseudoVLOXEI16_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #3329 = PseudoVLOXEI16_V_M4_M4 + {8, OperandInfo386}, // Inst #3330 = PseudoVLOXEI16_V_M4_M4_MASK + {5, OperandInfo387}, // Inst #3331 = PseudoVLOXEI16_V_M4_M8 + {8, OperandInfo388}, // Inst #3332 = PseudoVLOXEI16_V_M4_M8_MASK + {5, OperandInfo389}, // Inst #3333 = PseudoVLOXEI16_V_M8_M4 + {8, OperandInfo390}, // Inst #3334 = PseudoVLOXEI16_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #3335 = PseudoVLOXEI16_V_M8_M8 + {8, OperandInfo392}, // Inst #3336 = PseudoVLOXEI16_V_M8_M8_MASK + {5, OperandInfo373}, // Inst #3337 = PseudoVLOXEI16_V_MF2_M1 + {8, OperandInfo374}, // Inst #3338 = PseudoVLOXEI16_V_MF2_M1_MASK + {5, OperandInfo369}, // Inst #3339 = PseudoVLOXEI16_V_MF2_M2 + {8, OperandInfo370}, // Inst #3340 = PseudoVLOXEI16_V_MF2_M2_MASK + {5, OperandInfo367}, // Inst #3341 = PseudoVLOXEI16_V_MF2_MF2 + {8, OperandInfo368}, // Inst #3342 = PseudoVLOXEI16_V_MF2_MF2_MASK + {5, OperandInfo373}, // Inst #3343 = PseudoVLOXEI16_V_MF2_MF4 + {8, OperandInfo374}, // Inst #3344 = PseudoVLOXEI16_V_MF2_MF4_MASK + {5, OperandInfo373}, // Inst #3345 = PseudoVLOXEI16_V_MF4_M1 + {8, OperandInfo374}, // Inst #3346 = PseudoVLOXEI16_V_MF4_M1_MASK + {5, OperandInfo373}, // Inst #3347 = PseudoVLOXEI16_V_MF4_MF2 + {8, OperandInfo374}, // Inst #3348 = PseudoVLOXEI16_V_MF4_MF2_MASK + {5, OperandInfo367}, // Inst #3349 = PseudoVLOXEI16_V_MF4_MF4 + {8, OperandInfo368}, // Inst #3350 = PseudoVLOXEI16_V_MF4_MF4_MASK + {5, OperandInfo373}, // Inst #3351 = PseudoVLOXEI16_V_MF4_MF8 + {8, OperandInfo374}, // Inst #3352 = PseudoVLOXEI16_V_MF4_MF8_MASK + {5, OperandInfo367}, // Inst #3353 = PseudoVLOXEI32_V_M1_M1 + {8, OperandInfo368}, // Inst #3354 = PseudoVLOXEI32_V_M1_M1_MASK + {5, OperandInfo369}, // Inst #3355 = PseudoVLOXEI32_V_M1_M2 + {8, OperandInfo370}, // Inst #3356 = PseudoVLOXEI32_V_M1_M2_MASK + {5, OperandInfo373}, // Inst #3357 = PseudoVLOXEI32_V_M1_MF2 + {8, OperandInfo374}, // Inst #3358 = PseudoVLOXEI32_V_M1_MF2_MASK + {5, OperandInfo373}, // Inst #3359 = PseudoVLOXEI32_V_M1_MF4 + {8, OperandInfo374}, // Inst #3360 = PseudoVLOXEI32_V_M1_MF4_MASK + {5, OperandInfo375}, // Inst #3361 = PseudoVLOXEI32_V_M2_M1 + {8, OperandInfo376}, // Inst #3362 = PseudoVLOXEI32_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #3363 = PseudoVLOXEI32_V_M2_M2 + {8, OperandInfo378}, // Inst #3364 = PseudoVLOXEI32_V_M2_M2_MASK + {5, OperandInfo379}, // Inst #3365 = PseudoVLOXEI32_V_M2_M4 + {8, OperandInfo380}, // Inst #3366 = PseudoVLOXEI32_V_M2_M4_MASK + {5, OperandInfo375}, // Inst #3367 = PseudoVLOXEI32_V_M2_MF2 + {8, OperandInfo376}, // Inst #3368 = PseudoVLOXEI32_V_M2_MF2_MASK + {5, OperandInfo393}, // Inst #3369 = PseudoVLOXEI32_V_M4_M1 + {8, OperandInfo394}, // Inst #3370 = PseudoVLOXEI32_V_M4_M1_MASK + {5, OperandInfo383}, // Inst #3371 = PseudoVLOXEI32_V_M4_M2 + {8, OperandInfo384}, // Inst #3372 = PseudoVLOXEI32_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #3373 = PseudoVLOXEI32_V_M4_M4 + {8, OperandInfo386}, // Inst #3374 = PseudoVLOXEI32_V_M4_M4_MASK + {5, OperandInfo387}, // Inst #3375 = PseudoVLOXEI32_V_M4_M8 + {8, OperandInfo388}, // Inst #3376 = PseudoVLOXEI32_V_M4_M8_MASK + {5, OperandInfo395}, // Inst #3377 = PseudoVLOXEI32_V_M8_M2 + {8, OperandInfo396}, // Inst #3378 = PseudoVLOXEI32_V_M8_M2_MASK + {5, OperandInfo389}, // Inst #3379 = PseudoVLOXEI32_V_M8_M4 + {8, OperandInfo390}, // Inst #3380 = PseudoVLOXEI32_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #3381 = PseudoVLOXEI32_V_M8_M8 + {8, OperandInfo392}, // Inst #3382 = PseudoVLOXEI32_V_M8_M8_MASK + {5, OperandInfo373}, // Inst #3383 = PseudoVLOXEI32_V_MF2_M1 + {8, OperandInfo374}, // Inst #3384 = PseudoVLOXEI32_V_MF2_M1_MASK + {5, OperandInfo367}, // Inst #3385 = PseudoVLOXEI32_V_MF2_MF2 + {8, OperandInfo368}, // Inst #3386 = PseudoVLOXEI32_V_MF2_MF2_MASK + {5, OperandInfo373}, // Inst #3387 = PseudoVLOXEI32_V_MF2_MF4 + {8, OperandInfo374}, // Inst #3388 = PseudoVLOXEI32_V_MF2_MF4_MASK + {5, OperandInfo373}, // Inst #3389 = PseudoVLOXEI32_V_MF2_MF8 + {8, OperandInfo374}, // Inst #3390 = PseudoVLOXEI32_V_MF2_MF8_MASK + {5, OperandInfo367}, // Inst #3391 = PseudoVLOXEI64_V_M1_M1 + {8, OperandInfo368}, // Inst #3392 = PseudoVLOXEI64_V_M1_M1_MASK + {5, OperandInfo373}, // Inst #3393 = PseudoVLOXEI64_V_M1_MF2 + {8, OperandInfo374}, // Inst #3394 = PseudoVLOXEI64_V_M1_MF2_MASK + {5, OperandInfo373}, // Inst #3395 = PseudoVLOXEI64_V_M1_MF4 + {8, OperandInfo374}, // Inst #3396 = PseudoVLOXEI64_V_M1_MF4_MASK + {5, OperandInfo373}, // Inst #3397 = PseudoVLOXEI64_V_M1_MF8 + {8, OperandInfo374}, // Inst #3398 = PseudoVLOXEI64_V_M1_MF8_MASK + {5, OperandInfo375}, // Inst #3399 = PseudoVLOXEI64_V_M2_M1 + {8, OperandInfo376}, // Inst #3400 = PseudoVLOXEI64_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #3401 = PseudoVLOXEI64_V_M2_M2 + {8, OperandInfo378}, // Inst #3402 = PseudoVLOXEI64_V_M2_M2_MASK + {5, OperandInfo375}, // Inst #3403 = PseudoVLOXEI64_V_M2_MF2 + {8, OperandInfo376}, // Inst #3404 = PseudoVLOXEI64_V_M2_MF2_MASK + {5, OperandInfo375}, // Inst #3405 = PseudoVLOXEI64_V_M2_MF4 + {8, OperandInfo376}, // Inst #3406 = PseudoVLOXEI64_V_M2_MF4_MASK + {5, OperandInfo393}, // Inst #3407 = PseudoVLOXEI64_V_M4_M1 + {8, OperandInfo394}, // Inst #3408 = PseudoVLOXEI64_V_M4_M1_MASK + {5, OperandInfo383}, // Inst #3409 = PseudoVLOXEI64_V_M4_M2 + {8, OperandInfo384}, // Inst #3410 = PseudoVLOXEI64_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #3411 = PseudoVLOXEI64_V_M4_M4 + {8, OperandInfo386}, // Inst #3412 = PseudoVLOXEI64_V_M4_M4_MASK + {5, OperandInfo393}, // Inst #3413 = PseudoVLOXEI64_V_M4_MF2 + {8, OperandInfo394}, // Inst #3414 = PseudoVLOXEI64_V_M4_MF2_MASK + {5, OperandInfo397}, // Inst #3415 = PseudoVLOXEI64_V_M8_M1 + {8, OperandInfo398}, // Inst #3416 = PseudoVLOXEI64_V_M8_M1_MASK + {5, OperandInfo395}, // Inst #3417 = PseudoVLOXEI64_V_M8_M2 + {8, OperandInfo396}, // Inst #3418 = PseudoVLOXEI64_V_M8_M2_MASK + {5, OperandInfo389}, // Inst #3419 = PseudoVLOXEI64_V_M8_M4 + {8, OperandInfo390}, // Inst #3420 = PseudoVLOXEI64_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #3421 = PseudoVLOXEI64_V_M8_M8 + {8, OperandInfo392}, // Inst #3422 = PseudoVLOXEI64_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #3423 = PseudoVLOXEI8_V_M1_M1 + {8, OperandInfo368}, // Inst #3424 = PseudoVLOXEI8_V_M1_M1_MASK + {5, OperandInfo369}, // Inst #3425 = PseudoVLOXEI8_V_M1_M2 + {8, OperandInfo370}, // Inst #3426 = PseudoVLOXEI8_V_M1_M2_MASK + {5, OperandInfo371}, // Inst #3427 = PseudoVLOXEI8_V_M1_M4 + {8, OperandInfo372}, // Inst #3428 = PseudoVLOXEI8_V_M1_M4_MASK + {5, OperandInfo399}, // Inst #3429 = PseudoVLOXEI8_V_M1_M8 + {8, OperandInfo400}, // Inst #3430 = PseudoVLOXEI8_V_M1_M8_MASK + {5, OperandInfo377}, // Inst #3431 = PseudoVLOXEI8_V_M2_M2 + {8, OperandInfo378}, // Inst #3432 = PseudoVLOXEI8_V_M2_M2_MASK + {5, OperandInfo379}, // Inst #3433 = PseudoVLOXEI8_V_M2_M4 + {8, OperandInfo380}, // Inst #3434 = PseudoVLOXEI8_V_M2_M4_MASK + {5, OperandInfo381}, // Inst #3435 = PseudoVLOXEI8_V_M2_M8 + {8, OperandInfo382}, // Inst #3436 = PseudoVLOXEI8_V_M2_M8_MASK + {5, OperandInfo385}, // Inst #3437 = PseudoVLOXEI8_V_M4_M4 + {8, OperandInfo386}, // Inst #3438 = PseudoVLOXEI8_V_M4_M4_MASK + {5, OperandInfo387}, // Inst #3439 = PseudoVLOXEI8_V_M4_M8 + {8, OperandInfo388}, // Inst #3440 = PseudoVLOXEI8_V_M4_M8_MASK + {5, OperandInfo391}, // Inst #3441 = PseudoVLOXEI8_V_M8_M8 + {8, OperandInfo392}, // Inst #3442 = PseudoVLOXEI8_V_M8_M8_MASK + {5, OperandInfo373}, // Inst #3443 = PseudoVLOXEI8_V_MF2_M1 + {8, OperandInfo374}, // Inst #3444 = PseudoVLOXEI8_V_MF2_M1_MASK + {5, OperandInfo369}, // Inst #3445 = PseudoVLOXEI8_V_MF2_M2 + {8, OperandInfo370}, // Inst #3446 = PseudoVLOXEI8_V_MF2_M2_MASK + {5, OperandInfo371}, // Inst #3447 = PseudoVLOXEI8_V_MF2_M4 + {8, OperandInfo372}, // Inst #3448 = PseudoVLOXEI8_V_MF2_M4_MASK + {5, OperandInfo367}, // Inst #3449 = PseudoVLOXEI8_V_MF2_MF2 + {8, OperandInfo368}, // Inst #3450 = PseudoVLOXEI8_V_MF2_MF2_MASK + {5, OperandInfo373}, // Inst #3451 = PseudoVLOXEI8_V_MF4_M1 + {8, OperandInfo374}, // Inst #3452 = PseudoVLOXEI8_V_MF4_M1_MASK + {5, OperandInfo369}, // Inst #3453 = PseudoVLOXEI8_V_MF4_M2 + {8, OperandInfo370}, // Inst #3454 = PseudoVLOXEI8_V_MF4_M2_MASK + {5, OperandInfo373}, // Inst #3455 = PseudoVLOXEI8_V_MF4_MF2 + {8, OperandInfo374}, // Inst #3456 = PseudoVLOXEI8_V_MF4_MF2_MASK + {5, OperandInfo367}, // Inst #3457 = PseudoVLOXEI8_V_MF4_MF4 + {8, OperandInfo368}, // Inst #3458 = PseudoVLOXEI8_V_MF4_MF4_MASK + {5, OperandInfo373}, // Inst #3459 = PseudoVLOXEI8_V_MF8_M1 + {8, OperandInfo374}, // Inst #3460 = PseudoVLOXEI8_V_MF8_M1_MASK + {5, OperandInfo373}, // Inst #3461 = PseudoVLOXEI8_V_MF8_MF2 + {8, OperandInfo374}, // Inst #3462 = PseudoVLOXEI8_V_MF8_MF2_MASK + {5, OperandInfo373}, // Inst #3463 = PseudoVLOXEI8_V_MF8_MF4 + {8, OperandInfo374}, // Inst #3464 = PseudoVLOXEI8_V_MF8_MF4_MASK + {5, OperandInfo367}, // Inst #3465 = PseudoVLOXEI8_V_MF8_MF8 + {8, OperandInfo368}, // Inst #3466 = PseudoVLOXEI8_V_MF8_MF8_MASK + {5, OperandInfo401}, // Inst #3467 = PseudoVLOXSEG2EI16_V_M1_M1 + {8, OperandInfo402}, // Inst #3468 = PseudoVLOXSEG2EI16_V_M1_M1_MASK + {5, OperandInfo403}, // Inst #3469 = PseudoVLOXSEG2EI16_V_M1_M2 + {8, OperandInfo404}, // Inst #3470 = PseudoVLOXSEG2EI16_V_M1_M2_MASK + {5, OperandInfo405}, // Inst #3471 = PseudoVLOXSEG2EI16_V_M1_M4 + {8, OperandInfo406}, // Inst #3472 = PseudoVLOXSEG2EI16_V_M1_M4_MASK + {5, OperandInfo401}, // Inst #3473 = PseudoVLOXSEG2EI16_V_M1_MF2 + {8, OperandInfo402}, // Inst #3474 = PseudoVLOXSEG2EI16_V_M1_MF2_MASK + {5, OperandInfo407}, // Inst #3475 = PseudoVLOXSEG2EI16_V_M2_M1 + {8, OperandInfo408}, // Inst #3476 = PseudoVLOXSEG2EI16_V_M2_M1_MASK + {5, OperandInfo409}, // Inst #3477 = PseudoVLOXSEG2EI16_V_M2_M2 + {8, OperandInfo410}, // Inst #3478 = PseudoVLOXSEG2EI16_V_M2_M2_MASK + {5, OperandInfo411}, // Inst #3479 = PseudoVLOXSEG2EI16_V_M2_M4 + {8, OperandInfo412}, // Inst #3480 = PseudoVLOXSEG2EI16_V_M2_M4_MASK + {5, OperandInfo413}, // Inst #3481 = PseudoVLOXSEG2EI16_V_M4_M2 + {8, OperandInfo414}, // Inst #3482 = PseudoVLOXSEG2EI16_V_M4_M2_MASK + {5, OperandInfo415}, // Inst #3483 = PseudoVLOXSEG2EI16_V_M4_M4 + {8, OperandInfo416}, // Inst #3484 = PseudoVLOXSEG2EI16_V_M4_M4_MASK + {5, OperandInfo417}, // Inst #3485 = PseudoVLOXSEG2EI16_V_M8_M4 + {8, OperandInfo418}, // Inst #3486 = PseudoVLOXSEG2EI16_V_M8_M4_MASK + {5, OperandInfo401}, // Inst #3487 = PseudoVLOXSEG2EI16_V_MF2_M1 + {8, OperandInfo402}, // Inst #3488 = PseudoVLOXSEG2EI16_V_MF2_M1_MASK + {5, OperandInfo403}, // Inst #3489 = PseudoVLOXSEG2EI16_V_MF2_M2 + {8, OperandInfo404}, // Inst #3490 = PseudoVLOXSEG2EI16_V_MF2_M2_MASK + {5, OperandInfo401}, // Inst #3491 = PseudoVLOXSEG2EI16_V_MF2_MF2 + {8, OperandInfo402}, // Inst #3492 = PseudoVLOXSEG2EI16_V_MF2_MF2_MASK + {5, OperandInfo401}, // Inst #3493 = PseudoVLOXSEG2EI16_V_MF2_MF4 + {8, OperandInfo402}, // Inst #3494 = PseudoVLOXSEG2EI16_V_MF2_MF4_MASK + {5, OperandInfo401}, // Inst #3495 = PseudoVLOXSEG2EI16_V_MF4_M1 + {8, OperandInfo402}, // Inst #3496 = PseudoVLOXSEG2EI16_V_MF4_M1_MASK + {5, OperandInfo401}, // Inst #3497 = PseudoVLOXSEG2EI16_V_MF4_MF2 + {8, OperandInfo402}, // Inst #3498 = PseudoVLOXSEG2EI16_V_MF4_MF2_MASK + {5, OperandInfo401}, // Inst #3499 = PseudoVLOXSEG2EI16_V_MF4_MF4 + {8, OperandInfo402}, // Inst #3500 = PseudoVLOXSEG2EI16_V_MF4_MF4_MASK + {5, OperandInfo401}, // Inst #3501 = PseudoVLOXSEG2EI16_V_MF4_MF8 + {8, OperandInfo402}, // Inst #3502 = PseudoVLOXSEG2EI16_V_MF4_MF8_MASK + {5, OperandInfo401}, // Inst #3503 = PseudoVLOXSEG2EI32_V_M1_M1 + {8, OperandInfo402}, // Inst #3504 = PseudoVLOXSEG2EI32_V_M1_M1_MASK + {5, OperandInfo403}, // Inst #3505 = PseudoVLOXSEG2EI32_V_M1_M2 + {8, OperandInfo404}, // Inst #3506 = PseudoVLOXSEG2EI32_V_M1_M2_MASK + {5, OperandInfo401}, // Inst #3507 = PseudoVLOXSEG2EI32_V_M1_MF2 + {8, OperandInfo402}, // Inst #3508 = PseudoVLOXSEG2EI32_V_M1_MF2_MASK + {5, OperandInfo401}, // Inst #3509 = PseudoVLOXSEG2EI32_V_M1_MF4 + {8, OperandInfo402}, // Inst #3510 = PseudoVLOXSEG2EI32_V_M1_MF4_MASK + {5, OperandInfo407}, // Inst #3511 = PseudoVLOXSEG2EI32_V_M2_M1 + {8, OperandInfo408}, // Inst #3512 = PseudoVLOXSEG2EI32_V_M2_M1_MASK + {5, OperandInfo409}, // Inst #3513 = PseudoVLOXSEG2EI32_V_M2_M2 + {8, OperandInfo410}, // Inst #3514 = PseudoVLOXSEG2EI32_V_M2_M2_MASK + {5, OperandInfo411}, // Inst #3515 = PseudoVLOXSEG2EI32_V_M2_M4 + {8, OperandInfo412}, // Inst #3516 = PseudoVLOXSEG2EI32_V_M2_M4_MASK + {5, OperandInfo407}, // Inst #3517 = PseudoVLOXSEG2EI32_V_M2_MF2 + {8, OperandInfo408}, // Inst #3518 = PseudoVLOXSEG2EI32_V_M2_MF2_MASK + {5, OperandInfo419}, // Inst #3519 = PseudoVLOXSEG2EI32_V_M4_M1 + {8, OperandInfo420}, // Inst #3520 = PseudoVLOXSEG2EI32_V_M4_M1_MASK + {5, OperandInfo413}, // Inst #3521 = PseudoVLOXSEG2EI32_V_M4_M2 + {8, OperandInfo414}, // Inst #3522 = PseudoVLOXSEG2EI32_V_M4_M2_MASK + {5, OperandInfo415}, // Inst #3523 = PseudoVLOXSEG2EI32_V_M4_M4 + {8, OperandInfo416}, // Inst #3524 = PseudoVLOXSEG2EI32_V_M4_M4_MASK + {5, OperandInfo421}, // Inst #3525 = PseudoVLOXSEG2EI32_V_M8_M2 + {8, OperandInfo422}, // Inst #3526 = PseudoVLOXSEG2EI32_V_M8_M2_MASK + {5, OperandInfo417}, // Inst #3527 = PseudoVLOXSEG2EI32_V_M8_M4 + {8, OperandInfo418}, // Inst #3528 = PseudoVLOXSEG2EI32_V_M8_M4_MASK + {5, OperandInfo401}, // Inst #3529 = PseudoVLOXSEG2EI32_V_MF2_M1 + {8, OperandInfo402}, // Inst #3530 = PseudoVLOXSEG2EI32_V_MF2_M1_MASK + {5, OperandInfo401}, // Inst #3531 = PseudoVLOXSEG2EI32_V_MF2_MF2 + {8, OperandInfo402}, // Inst #3532 = PseudoVLOXSEG2EI32_V_MF2_MF2_MASK + {5, OperandInfo401}, // Inst #3533 = PseudoVLOXSEG2EI32_V_MF2_MF4 + {8, OperandInfo402}, // Inst #3534 = PseudoVLOXSEG2EI32_V_MF2_MF4_MASK + {5, OperandInfo401}, // Inst #3535 = PseudoVLOXSEG2EI32_V_MF2_MF8 + {8, OperandInfo402}, // Inst #3536 = PseudoVLOXSEG2EI32_V_MF2_MF8_MASK + {5, OperandInfo401}, // Inst #3537 = PseudoVLOXSEG2EI64_V_M1_M1 + {8, OperandInfo402}, // Inst #3538 = PseudoVLOXSEG2EI64_V_M1_M1_MASK + {5, OperandInfo401}, // Inst #3539 = PseudoVLOXSEG2EI64_V_M1_MF2 + {8, OperandInfo402}, // Inst #3540 = PseudoVLOXSEG2EI64_V_M1_MF2_MASK + {5, OperandInfo401}, // Inst #3541 = PseudoVLOXSEG2EI64_V_M1_MF4 + {8, OperandInfo402}, // Inst #3542 = PseudoVLOXSEG2EI64_V_M1_MF4_MASK + {5, OperandInfo401}, // Inst #3543 = PseudoVLOXSEG2EI64_V_M1_MF8 + {8, OperandInfo402}, // Inst #3544 = PseudoVLOXSEG2EI64_V_M1_MF8_MASK + {5, OperandInfo407}, // Inst #3545 = PseudoVLOXSEG2EI64_V_M2_M1 + {8, OperandInfo408}, // Inst #3546 = PseudoVLOXSEG2EI64_V_M2_M1_MASK + {5, OperandInfo409}, // Inst #3547 = PseudoVLOXSEG2EI64_V_M2_M2 + {8, OperandInfo410}, // Inst #3548 = PseudoVLOXSEG2EI64_V_M2_M2_MASK + {5, OperandInfo407}, // Inst #3549 = PseudoVLOXSEG2EI64_V_M2_MF2 + {8, OperandInfo408}, // Inst #3550 = PseudoVLOXSEG2EI64_V_M2_MF2_MASK + {5, OperandInfo407}, // Inst #3551 = PseudoVLOXSEG2EI64_V_M2_MF4 + {8, OperandInfo408}, // Inst #3552 = PseudoVLOXSEG2EI64_V_M2_MF4_MASK + {5, OperandInfo419}, // Inst #3553 = PseudoVLOXSEG2EI64_V_M4_M1 + {8, OperandInfo420}, // Inst #3554 = PseudoVLOXSEG2EI64_V_M4_M1_MASK + {5, OperandInfo413}, // Inst #3555 = PseudoVLOXSEG2EI64_V_M4_M2 + {8, OperandInfo414}, // Inst #3556 = PseudoVLOXSEG2EI64_V_M4_M2_MASK + {5, OperandInfo415}, // Inst #3557 = PseudoVLOXSEG2EI64_V_M4_M4 + {8, OperandInfo416}, // Inst #3558 = PseudoVLOXSEG2EI64_V_M4_M4_MASK + {5, OperandInfo419}, // Inst #3559 = PseudoVLOXSEG2EI64_V_M4_MF2 + {8, OperandInfo420}, // Inst #3560 = PseudoVLOXSEG2EI64_V_M4_MF2_MASK + {5, OperandInfo423}, // Inst #3561 = PseudoVLOXSEG2EI64_V_M8_M1 + {8, OperandInfo424}, // Inst #3562 = PseudoVLOXSEG2EI64_V_M8_M1_MASK + {5, OperandInfo421}, // Inst #3563 = PseudoVLOXSEG2EI64_V_M8_M2 + {8, OperandInfo422}, // Inst #3564 = PseudoVLOXSEG2EI64_V_M8_M2_MASK + {5, OperandInfo417}, // Inst #3565 = PseudoVLOXSEG2EI64_V_M8_M4 + {8, OperandInfo418}, // Inst #3566 = PseudoVLOXSEG2EI64_V_M8_M4_MASK + {5, OperandInfo401}, // Inst #3567 = PseudoVLOXSEG2EI8_V_M1_M1 + {8, OperandInfo402}, // Inst #3568 = PseudoVLOXSEG2EI8_V_M1_M1_MASK + {5, OperandInfo403}, // Inst #3569 = PseudoVLOXSEG2EI8_V_M1_M2 + {8, OperandInfo404}, // Inst #3570 = PseudoVLOXSEG2EI8_V_M1_M2_MASK + {5, OperandInfo405}, // Inst #3571 = PseudoVLOXSEG2EI8_V_M1_M4 + {8, OperandInfo406}, // Inst #3572 = PseudoVLOXSEG2EI8_V_M1_M4_MASK + {5, OperandInfo409}, // Inst #3573 = PseudoVLOXSEG2EI8_V_M2_M2 + {8, OperandInfo410}, // Inst #3574 = PseudoVLOXSEG2EI8_V_M2_M2_MASK + {5, OperandInfo411}, // Inst #3575 = PseudoVLOXSEG2EI8_V_M2_M4 + {8, OperandInfo412}, // Inst #3576 = PseudoVLOXSEG2EI8_V_M2_M4_MASK + {5, OperandInfo415}, // Inst #3577 = PseudoVLOXSEG2EI8_V_M4_M4 + {8, OperandInfo416}, // Inst #3578 = PseudoVLOXSEG2EI8_V_M4_M4_MASK + {5, OperandInfo401}, // Inst #3579 = PseudoVLOXSEG2EI8_V_MF2_M1 + {8, OperandInfo402}, // Inst #3580 = PseudoVLOXSEG2EI8_V_MF2_M1_MASK + {5, OperandInfo403}, // Inst #3581 = PseudoVLOXSEG2EI8_V_MF2_M2 + {8, OperandInfo404}, // Inst #3582 = PseudoVLOXSEG2EI8_V_MF2_M2_MASK + {5, OperandInfo405}, // Inst #3583 = PseudoVLOXSEG2EI8_V_MF2_M4 + {8, OperandInfo406}, // Inst #3584 = PseudoVLOXSEG2EI8_V_MF2_M4_MASK + {5, OperandInfo401}, // Inst #3585 = PseudoVLOXSEG2EI8_V_MF2_MF2 + {8, OperandInfo402}, // Inst #3586 = PseudoVLOXSEG2EI8_V_MF2_MF2_MASK + {5, OperandInfo401}, // Inst #3587 = PseudoVLOXSEG2EI8_V_MF4_M1 + {8, OperandInfo402}, // Inst #3588 = PseudoVLOXSEG2EI8_V_MF4_M1_MASK + {5, OperandInfo403}, // Inst #3589 = PseudoVLOXSEG2EI8_V_MF4_M2 + {8, OperandInfo404}, // Inst #3590 = PseudoVLOXSEG2EI8_V_MF4_M2_MASK + {5, OperandInfo401}, // Inst #3591 = PseudoVLOXSEG2EI8_V_MF4_MF2 + {8, OperandInfo402}, // Inst #3592 = PseudoVLOXSEG2EI8_V_MF4_MF2_MASK + {5, OperandInfo401}, // Inst #3593 = PseudoVLOXSEG2EI8_V_MF4_MF4 + {8, OperandInfo402}, // Inst #3594 = PseudoVLOXSEG2EI8_V_MF4_MF4_MASK + {5, OperandInfo401}, // Inst #3595 = PseudoVLOXSEG2EI8_V_MF8_M1 + {8, OperandInfo402}, // Inst #3596 = PseudoVLOXSEG2EI8_V_MF8_M1_MASK + {5, OperandInfo401}, // Inst #3597 = PseudoVLOXSEG2EI8_V_MF8_MF2 + {8, OperandInfo402}, // Inst #3598 = PseudoVLOXSEG2EI8_V_MF8_MF2_MASK + {5, OperandInfo401}, // Inst #3599 = PseudoVLOXSEG2EI8_V_MF8_MF4 + {8, OperandInfo402}, // Inst #3600 = PseudoVLOXSEG2EI8_V_MF8_MF4_MASK + {5, OperandInfo401}, // Inst #3601 = PseudoVLOXSEG2EI8_V_MF8_MF8 + {8, OperandInfo402}, // Inst #3602 = PseudoVLOXSEG2EI8_V_MF8_MF8_MASK + {5, OperandInfo425}, // Inst #3603 = PseudoVLOXSEG3EI16_V_M1_M1 + {8, OperandInfo426}, // Inst #3604 = PseudoVLOXSEG3EI16_V_M1_M1_MASK + {5, OperandInfo427}, // Inst #3605 = PseudoVLOXSEG3EI16_V_M1_M2 + {8, OperandInfo428}, // Inst #3606 = PseudoVLOXSEG3EI16_V_M1_M2_MASK + {5, OperandInfo425}, // Inst #3607 = PseudoVLOXSEG3EI16_V_M1_MF2 + {8, OperandInfo426}, // Inst #3608 = PseudoVLOXSEG3EI16_V_M1_MF2_MASK + {5, OperandInfo429}, // Inst #3609 = PseudoVLOXSEG3EI16_V_M2_M1 + {8, OperandInfo430}, // Inst #3610 = PseudoVLOXSEG3EI16_V_M2_M1_MASK + {5, OperandInfo431}, // Inst #3611 = PseudoVLOXSEG3EI16_V_M2_M2 + {8, OperandInfo432}, // Inst #3612 = PseudoVLOXSEG3EI16_V_M2_M2_MASK + {5, OperandInfo433}, // Inst #3613 = PseudoVLOXSEG3EI16_V_M4_M2 + {8, OperandInfo434}, // Inst #3614 = PseudoVLOXSEG3EI16_V_M4_M2_MASK + {5, OperandInfo425}, // Inst #3615 = PseudoVLOXSEG3EI16_V_MF2_M1 + {8, OperandInfo426}, // Inst #3616 = PseudoVLOXSEG3EI16_V_MF2_M1_MASK + {5, OperandInfo427}, // Inst #3617 = PseudoVLOXSEG3EI16_V_MF2_M2 + {8, OperandInfo428}, // Inst #3618 = PseudoVLOXSEG3EI16_V_MF2_M2_MASK + {5, OperandInfo425}, // Inst #3619 = PseudoVLOXSEG3EI16_V_MF2_MF2 + {8, OperandInfo426}, // Inst #3620 = PseudoVLOXSEG3EI16_V_MF2_MF2_MASK + {5, OperandInfo425}, // Inst #3621 = PseudoVLOXSEG3EI16_V_MF2_MF4 + {8, OperandInfo426}, // Inst #3622 = PseudoVLOXSEG3EI16_V_MF2_MF4_MASK + {5, OperandInfo425}, // Inst #3623 = PseudoVLOXSEG3EI16_V_MF4_M1 + {8, OperandInfo426}, // Inst #3624 = PseudoVLOXSEG3EI16_V_MF4_M1_MASK + {5, OperandInfo425}, // Inst #3625 = PseudoVLOXSEG3EI16_V_MF4_MF2 + {8, OperandInfo426}, // Inst #3626 = PseudoVLOXSEG3EI16_V_MF4_MF2_MASK + {5, OperandInfo425}, // Inst #3627 = PseudoVLOXSEG3EI16_V_MF4_MF4 + {8, OperandInfo426}, // Inst #3628 = PseudoVLOXSEG3EI16_V_MF4_MF4_MASK + {5, OperandInfo425}, // Inst #3629 = PseudoVLOXSEG3EI16_V_MF4_MF8 + {8, OperandInfo426}, // Inst #3630 = PseudoVLOXSEG3EI16_V_MF4_MF8_MASK + {5, OperandInfo425}, // Inst #3631 = PseudoVLOXSEG3EI32_V_M1_M1 + {8, OperandInfo426}, // Inst #3632 = PseudoVLOXSEG3EI32_V_M1_M1_MASK + {5, OperandInfo427}, // Inst #3633 = PseudoVLOXSEG3EI32_V_M1_M2 + {8, OperandInfo428}, // Inst #3634 = PseudoVLOXSEG3EI32_V_M1_M2_MASK + {5, OperandInfo425}, // Inst #3635 = PseudoVLOXSEG3EI32_V_M1_MF2 + {8, OperandInfo426}, // Inst #3636 = PseudoVLOXSEG3EI32_V_M1_MF2_MASK + {5, OperandInfo425}, // Inst #3637 = PseudoVLOXSEG3EI32_V_M1_MF4 + {8, OperandInfo426}, // Inst #3638 = PseudoVLOXSEG3EI32_V_M1_MF4_MASK + {5, OperandInfo429}, // Inst #3639 = PseudoVLOXSEG3EI32_V_M2_M1 + {8, OperandInfo430}, // Inst #3640 = PseudoVLOXSEG3EI32_V_M2_M1_MASK + {5, OperandInfo431}, // Inst #3641 = PseudoVLOXSEG3EI32_V_M2_M2 + {8, OperandInfo432}, // Inst #3642 = PseudoVLOXSEG3EI32_V_M2_M2_MASK + {5, OperandInfo429}, // Inst #3643 = PseudoVLOXSEG3EI32_V_M2_MF2 + {8, OperandInfo430}, // Inst #3644 = PseudoVLOXSEG3EI32_V_M2_MF2_MASK + {5, OperandInfo435}, // Inst #3645 = PseudoVLOXSEG3EI32_V_M4_M1 + {8, OperandInfo436}, // Inst #3646 = PseudoVLOXSEG3EI32_V_M4_M1_MASK + {5, OperandInfo433}, // Inst #3647 = PseudoVLOXSEG3EI32_V_M4_M2 + {8, OperandInfo434}, // Inst #3648 = PseudoVLOXSEG3EI32_V_M4_M2_MASK + {5, OperandInfo437}, // Inst #3649 = PseudoVLOXSEG3EI32_V_M8_M2 + {8, OperandInfo438}, // Inst #3650 = PseudoVLOXSEG3EI32_V_M8_M2_MASK + {5, OperandInfo425}, // Inst #3651 = PseudoVLOXSEG3EI32_V_MF2_M1 + {8, OperandInfo426}, // Inst #3652 = PseudoVLOXSEG3EI32_V_MF2_M1_MASK + {5, OperandInfo425}, // Inst #3653 = PseudoVLOXSEG3EI32_V_MF2_MF2 + {8, OperandInfo426}, // Inst #3654 = PseudoVLOXSEG3EI32_V_MF2_MF2_MASK + {5, OperandInfo425}, // Inst #3655 = PseudoVLOXSEG3EI32_V_MF2_MF4 + {8, OperandInfo426}, // Inst #3656 = PseudoVLOXSEG3EI32_V_MF2_MF4_MASK + {5, OperandInfo425}, // Inst #3657 = PseudoVLOXSEG3EI32_V_MF2_MF8 + {8, OperandInfo426}, // Inst #3658 = PseudoVLOXSEG3EI32_V_MF2_MF8_MASK + {5, OperandInfo425}, // Inst #3659 = PseudoVLOXSEG3EI64_V_M1_M1 + {8, OperandInfo426}, // Inst #3660 = PseudoVLOXSEG3EI64_V_M1_M1_MASK + {5, OperandInfo425}, // Inst #3661 = PseudoVLOXSEG3EI64_V_M1_MF2 + {8, OperandInfo426}, // Inst #3662 = PseudoVLOXSEG3EI64_V_M1_MF2_MASK + {5, OperandInfo425}, // Inst #3663 = PseudoVLOXSEG3EI64_V_M1_MF4 + {8, OperandInfo426}, // Inst #3664 = PseudoVLOXSEG3EI64_V_M1_MF4_MASK + {5, OperandInfo425}, // Inst #3665 = PseudoVLOXSEG3EI64_V_M1_MF8 + {8, OperandInfo426}, // Inst #3666 = PseudoVLOXSEG3EI64_V_M1_MF8_MASK + {5, OperandInfo429}, // Inst #3667 = PseudoVLOXSEG3EI64_V_M2_M1 + {8, OperandInfo430}, // Inst #3668 = PseudoVLOXSEG3EI64_V_M2_M1_MASK + {5, OperandInfo431}, // Inst #3669 = PseudoVLOXSEG3EI64_V_M2_M2 + {8, OperandInfo432}, // Inst #3670 = PseudoVLOXSEG3EI64_V_M2_M2_MASK + {5, OperandInfo429}, // Inst #3671 = PseudoVLOXSEG3EI64_V_M2_MF2 + {8, OperandInfo430}, // Inst #3672 = PseudoVLOXSEG3EI64_V_M2_MF2_MASK + {5, OperandInfo429}, // Inst #3673 = PseudoVLOXSEG3EI64_V_M2_MF4 + {8, OperandInfo430}, // Inst #3674 = PseudoVLOXSEG3EI64_V_M2_MF4_MASK + {5, OperandInfo435}, // Inst #3675 = PseudoVLOXSEG3EI64_V_M4_M1 + {8, OperandInfo436}, // Inst #3676 = PseudoVLOXSEG3EI64_V_M4_M1_MASK + {5, OperandInfo433}, // Inst #3677 = PseudoVLOXSEG3EI64_V_M4_M2 + {8, OperandInfo434}, // Inst #3678 = PseudoVLOXSEG3EI64_V_M4_M2_MASK + {5, OperandInfo435}, // Inst #3679 = PseudoVLOXSEG3EI64_V_M4_MF2 + {8, OperandInfo436}, // Inst #3680 = PseudoVLOXSEG3EI64_V_M4_MF2_MASK + {5, OperandInfo439}, // Inst #3681 = PseudoVLOXSEG3EI64_V_M8_M1 + {8, OperandInfo440}, // Inst #3682 = PseudoVLOXSEG3EI64_V_M8_M1_MASK + {5, OperandInfo437}, // Inst #3683 = PseudoVLOXSEG3EI64_V_M8_M2 + {8, OperandInfo438}, // Inst #3684 = PseudoVLOXSEG3EI64_V_M8_M2_MASK + {5, OperandInfo425}, // Inst #3685 = PseudoVLOXSEG3EI8_V_M1_M1 + {8, OperandInfo426}, // Inst #3686 = PseudoVLOXSEG3EI8_V_M1_M1_MASK + {5, OperandInfo427}, // Inst #3687 = PseudoVLOXSEG3EI8_V_M1_M2 + {8, OperandInfo428}, // Inst #3688 = PseudoVLOXSEG3EI8_V_M1_M2_MASK + {5, OperandInfo431}, // Inst #3689 = PseudoVLOXSEG3EI8_V_M2_M2 + {8, OperandInfo432}, // Inst #3690 = PseudoVLOXSEG3EI8_V_M2_M2_MASK + {5, OperandInfo425}, // Inst #3691 = PseudoVLOXSEG3EI8_V_MF2_M1 + {8, OperandInfo426}, // Inst #3692 = PseudoVLOXSEG3EI8_V_MF2_M1_MASK + {5, OperandInfo427}, // Inst #3693 = PseudoVLOXSEG3EI8_V_MF2_M2 + {8, OperandInfo428}, // Inst #3694 = PseudoVLOXSEG3EI8_V_MF2_M2_MASK + {5, OperandInfo425}, // Inst #3695 = PseudoVLOXSEG3EI8_V_MF2_MF2 + {8, OperandInfo426}, // Inst #3696 = PseudoVLOXSEG3EI8_V_MF2_MF2_MASK + {5, OperandInfo425}, // Inst #3697 = PseudoVLOXSEG3EI8_V_MF4_M1 + {8, OperandInfo426}, // Inst #3698 = PseudoVLOXSEG3EI8_V_MF4_M1_MASK + {5, OperandInfo427}, // Inst #3699 = PseudoVLOXSEG3EI8_V_MF4_M2 + {8, OperandInfo428}, // Inst #3700 = PseudoVLOXSEG3EI8_V_MF4_M2_MASK + {5, OperandInfo425}, // Inst #3701 = PseudoVLOXSEG3EI8_V_MF4_MF2 + {8, OperandInfo426}, // Inst #3702 = PseudoVLOXSEG3EI8_V_MF4_MF2_MASK + {5, OperandInfo425}, // Inst #3703 = PseudoVLOXSEG3EI8_V_MF4_MF4 + {8, OperandInfo426}, // Inst #3704 = PseudoVLOXSEG3EI8_V_MF4_MF4_MASK + {5, OperandInfo425}, // Inst #3705 = PseudoVLOXSEG3EI8_V_MF8_M1 + {8, OperandInfo426}, // Inst #3706 = PseudoVLOXSEG3EI8_V_MF8_M1_MASK + {5, OperandInfo425}, // Inst #3707 = PseudoVLOXSEG3EI8_V_MF8_MF2 + {8, OperandInfo426}, // Inst #3708 = PseudoVLOXSEG3EI8_V_MF8_MF2_MASK + {5, OperandInfo425}, // Inst #3709 = PseudoVLOXSEG3EI8_V_MF8_MF4 + {8, OperandInfo426}, // Inst #3710 = PseudoVLOXSEG3EI8_V_MF8_MF4_MASK + {5, OperandInfo425}, // Inst #3711 = PseudoVLOXSEG3EI8_V_MF8_MF8 + {8, OperandInfo426}, // Inst #3712 = PseudoVLOXSEG3EI8_V_MF8_MF8_MASK + {5, OperandInfo441}, // Inst #3713 = PseudoVLOXSEG4EI16_V_M1_M1 + {8, OperandInfo442}, // Inst #3714 = PseudoVLOXSEG4EI16_V_M1_M1_MASK + {5, OperandInfo443}, // Inst #3715 = PseudoVLOXSEG4EI16_V_M1_M2 + {8, OperandInfo444}, // Inst #3716 = PseudoVLOXSEG4EI16_V_M1_M2_MASK + {5, OperandInfo441}, // Inst #3717 = PseudoVLOXSEG4EI16_V_M1_MF2 + {8, OperandInfo442}, // Inst #3718 = PseudoVLOXSEG4EI16_V_M1_MF2_MASK + {5, OperandInfo445}, // Inst #3719 = PseudoVLOXSEG4EI16_V_M2_M1 + {8, OperandInfo446}, // Inst #3720 = PseudoVLOXSEG4EI16_V_M2_M1_MASK + {5, OperandInfo447}, // Inst #3721 = PseudoVLOXSEG4EI16_V_M2_M2 + {8, OperandInfo448}, // Inst #3722 = PseudoVLOXSEG4EI16_V_M2_M2_MASK + {5, OperandInfo449}, // Inst #3723 = PseudoVLOXSEG4EI16_V_M4_M2 + {8, OperandInfo450}, // Inst #3724 = PseudoVLOXSEG4EI16_V_M4_M2_MASK + {5, OperandInfo441}, // Inst #3725 = PseudoVLOXSEG4EI16_V_MF2_M1 + {8, OperandInfo442}, // Inst #3726 = PseudoVLOXSEG4EI16_V_MF2_M1_MASK + {5, OperandInfo443}, // Inst #3727 = PseudoVLOXSEG4EI16_V_MF2_M2 + {8, OperandInfo444}, // Inst #3728 = PseudoVLOXSEG4EI16_V_MF2_M2_MASK + {5, OperandInfo441}, // Inst #3729 = PseudoVLOXSEG4EI16_V_MF2_MF2 + {8, OperandInfo442}, // Inst #3730 = PseudoVLOXSEG4EI16_V_MF2_MF2_MASK + {5, OperandInfo441}, // Inst #3731 = PseudoVLOXSEG4EI16_V_MF2_MF4 + {8, OperandInfo442}, // Inst #3732 = PseudoVLOXSEG4EI16_V_MF2_MF4_MASK + {5, OperandInfo441}, // Inst #3733 = PseudoVLOXSEG4EI16_V_MF4_M1 + {8, OperandInfo442}, // Inst #3734 = PseudoVLOXSEG4EI16_V_MF4_M1_MASK + {5, OperandInfo441}, // Inst #3735 = PseudoVLOXSEG4EI16_V_MF4_MF2 + {8, OperandInfo442}, // Inst #3736 = PseudoVLOXSEG4EI16_V_MF4_MF2_MASK + {5, OperandInfo441}, // Inst #3737 = PseudoVLOXSEG4EI16_V_MF4_MF4 + {8, OperandInfo442}, // Inst #3738 = PseudoVLOXSEG4EI16_V_MF4_MF4_MASK + {5, OperandInfo441}, // Inst #3739 = PseudoVLOXSEG4EI16_V_MF4_MF8 + {8, OperandInfo442}, // Inst #3740 = PseudoVLOXSEG4EI16_V_MF4_MF8_MASK + {5, OperandInfo441}, // Inst #3741 = PseudoVLOXSEG4EI32_V_M1_M1 + {8, OperandInfo442}, // Inst #3742 = PseudoVLOXSEG4EI32_V_M1_M1_MASK + {5, OperandInfo443}, // Inst #3743 = PseudoVLOXSEG4EI32_V_M1_M2 + {8, OperandInfo444}, // Inst #3744 = PseudoVLOXSEG4EI32_V_M1_M2_MASK + {5, OperandInfo441}, // Inst #3745 = PseudoVLOXSEG4EI32_V_M1_MF2 + {8, OperandInfo442}, // Inst #3746 = PseudoVLOXSEG4EI32_V_M1_MF2_MASK + {5, OperandInfo441}, // Inst #3747 = PseudoVLOXSEG4EI32_V_M1_MF4 + {8, OperandInfo442}, // Inst #3748 = PseudoVLOXSEG4EI32_V_M1_MF4_MASK + {5, OperandInfo445}, // Inst #3749 = PseudoVLOXSEG4EI32_V_M2_M1 + {8, OperandInfo446}, // Inst #3750 = PseudoVLOXSEG4EI32_V_M2_M1_MASK + {5, OperandInfo447}, // Inst #3751 = PseudoVLOXSEG4EI32_V_M2_M2 + {8, OperandInfo448}, // Inst #3752 = PseudoVLOXSEG4EI32_V_M2_M2_MASK + {5, OperandInfo445}, // Inst #3753 = PseudoVLOXSEG4EI32_V_M2_MF2 + {8, OperandInfo446}, // Inst #3754 = PseudoVLOXSEG4EI32_V_M2_MF2_MASK + {5, OperandInfo451}, // Inst #3755 = PseudoVLOXSEG4EI32_V_M4_M1 + {8, OperandInfo452}, // Inst #3756 = PseudoVLOXSEG4EI32_V_M4_M1_MASK + {5, OperandInfo449}, // Inst #3757 = PseudoVLOXSEG4EI32_V_M4_M2 + {8, OperandInfo450}, // Inst #3758 = PseudoVLOXSEG4EI32_V_M4_M2_MASK + {5, OperandInfo453}, // Inst #3759 = PseudoVLOXSEG4EI32_V_M8_M2 + {8, OperandInfo454}, // Inst #3760 = PseudoVLOXSEG4EI32_V_M8_M2_MASK + {5, OperandInfo441}, // Inst #3761 = PseudoVLOXSEG4EI32_V_MF2_M1 + {8, OperandInfo442}, // Inst #3762 = PseudoVLOXSEG4EI32_V_MF2_M1_MASK + {5, OperandInfo441}, // Inst #3763 = PseudoVLOXSEG4EI32_V_MF2_MF2 + {8, OperandInfo442}, // Inst #3764 = PseudoVLOXSEG4EI32_V_MF2_MF2_MASK + {5, OperandInfo441}, // Inst #3765 = PseudoVLOXSEG4EI32_V_MF2_MF4 + {8, OperandInfo442}, // Inst #3766 = PseudoVLOXSEG4EI32_V_MF2_MF4_MASK + {5, OperandInfo441}, // Inst #3767 = PseudoVLOXSEG4EI32_V_MF2_MF8 + {8, OperandInfo442}, // Inst #3768 = PseudoVLOXSEG4EI32_V_MF2_MF8_MASK + {5, OperandInfo441}, // Inst #3769 = PseudoVLOXSEG4EI64_V_M1_M1 + {8, OperandInfo442}, // Inst #3770 = PseudoVLOXSEG4EI64_V_M1_M1_MASK + {5, OperandInfo441}, // Inst #3771 = PseudoVLOXSEG4EI64_V_M1_MF2 + {8, OperandInfo442}, // Inst #3772 = PseudoVLOXSEG4EI64_V_M1_MF2_MASK + {5, OperandInfo441}, // Inst #3773 = PseudoVLOXSEG4EI64_V_M1_MF4 + {8, OperandInfo442}, // Inst #3774 = PseudoVLOXSEG4EI64_V_M1_MF4_MASK + {5, OperandInfo441}, // Inst #3775 = PseudoVLOXSEG4EI64_V_M1_MF8 + {8, OperandInfo442}, // Inst #3776 = PseudoVLOXSEG4EI64_V_M1_MF8_MASK + {5, OperandInfo445}, // Inst #3777 = PseudoVLOXSEG4EI64_V_M2_M1 + {8, OperandInfo446}, // Inst #3778 = PseudoVLOXSEG4EI64_V_M2_M1_MASK + {5, OperandInfo447}, // Inst #3779 = PseudoVLOXSEG4EI64_V_M2_M2 + {8, OperandInfo448}, // Inst #3780 = PseudoVLOXSEG4EI64_V_M2_M2_MASK + {5, OperandInfo445}, // Inst #3781 = PseudoVLOXSEG4EI64_V_M2_MF2 + {8, OperandInfo446}, // Inst #3782 = PseudoVLOXSEG4EI64_V_M2_MF2_MASK + {5, OperandInfo445}, // Inst #3783 = PseudoVLOXSEG4EI64_V_M2_MF4 + {8, OperandInfo446}, // Inst #3784 = PseudoVLOXSEG4EI64_V_M2_MF4_MASK + {5, OperandInfo451}, // Inst #3785 = PseudoVLOXSEG4EI64_V_M4_M1 + {8, OperandInfo452}, // Inst #3786 = PseudoVLOXSEG4EI64_V_M4_M1_MASK + {5, OperandInfo449}, // Inst #3787 = PseudoVLOXSEG4EI64_V_M4_M2 + {8, OperandInfo450}, // Inst #3788 = PseudoVLOXSEG4EI64_V_M4_M2_MASK + {5, OperandInfo451}, // Inst #3789 = PseudoVLOXSEG4EI64_V_M4_MF2 + {8, OperandInfo452}, // Inst #3790 = PseudoVLOXSEG4EI64_V_M4_MF2_MASK + {5, OperandInfo455}, // Inst #3791 = PseudoVLOXSEG4EI64_V_M8_M1 + {8, OperandInfo456}, // Inst #3792 = PseudoVLOXSEG4EI64_V_M8_M1_MASK + {5, OperandInfo453}, // Inst #3793 = PseudoVLOXSEG4EI64_V_M8_M2 + {8, OperandInfo454}, // Inst #3794 = PseudoVLOXSEG4EI64_V_M8_M2_MASK + {5, OperandInfo441}, // Inst #3795 = PseudoVLOXSEG4EI8_V_M1_M1 + {8, OperandInfo442}, // Inst #3796 = PseudoVLOXSEG4EI8_V_M1_M1_MASK + {5, OperandInfo443}, // Inst #3797 = PseudoVLOXSEG4EI8_V_M1_M2 + {8, OperandInfo444}, // Inst #3798 = PseudoVLOXSEG4EI8_V_M1_M2_MASK + {5, OperandInfo447}, // Inst #3799 = PseudoVLOXSEG4EI8_V_M2_M2 + {8, OperandInfo448}, // Inst #3800 = PseudoVLOXSEG4EI8_V_M2_M2_MASK + {5, OperandInfo441}, // Inst #3801 = PseudoVLOXSEG4EI8_V_MF2_M1 + {8, OperandInfo442}, // Inst #3802 = PseudoVLOXSEG4EI8_V_MF2_M1_MASK + {5, OperandInfo443}, // Inst #3803 = PseudoVLOXSEG4EI8_V_MF2_M2 + {8, OperandInfo444}, // Inst #3804 = PseudoVLOXSEG4EI8_V_MF2_M2_MASK + {5, OperandInfo441}, // Inst #3805 = PseudoVLOXSEG4EI8_V_MF2_MF2 + {8, OperandInfo442}, // Inst #3806 = PseudoVLOXSEG4EI8_V_MF2_MF2_MASK + {5, OperandInfo441}, // Inst #3807 = PseudoVLOXSEG4EI8_V_MF4_M1 + {8, OperandInfo442}, // Inst #3808 = PseudoVLOXSEG4EI8_V_MF4_M1_MASK + {5, OperandInfo443}, // Inst #3809 = PseudoVLOXSEG4EI8_V_MF4_M2 + {8, OperandInfo444}, // Inst #3810 = PseudoVLOXSEG4EI8_V_MF4_M2_MASK + {5, OperandInfo441}, // Inst #3811 = PseudoVLOXSEG4EI8_V_MF4_MF2 + {8, OperandInfo442}, // Inst #3812 = PseudoVLOXSEG4EI8_V_MF4_MF2_MASK + {5, OperandInfo441}, // Inst #3813 = PseudoVLOXSEG4EI8_V_MF4_MF4 + {8, OperandInfo442}, // Inst #3814 = PseudoVLOXSEG4EI8_V_MF4_MF4_MASK + {5, OperandInfo441}, // Inst #3815 = PseudoVLOXSEG4EI8_V_MF8_M1 + {8, OperandInfo442}, // Inst #3816 = PseudoVLOXSEG4EI8_V_MF8_M1_MASK + {5, OperandInfo441}, // Inst #3817 = PseudoVLOXSEG4EI8_V_MF8_MF2 + {8, OperandInfo442}, // Inst #3818 = PseudoVLOXSEG4EI8_V_MF8_MF2_MASK + {5, OperandInfo441}, // Inst #3819 = PseudoVLOXSEG4EI8_V_MF8_MF4 + {8, OperandInfo442}, // Inst #3820 = PseudoVLOXSEG4EI8_V_MF8_MF4_MASK + {5, OperandInfo441}, // Inst #3821 = PseudoVLOXSEG4EI8_V_MF8_MF8 + {8, OperandInfo442}, // Inst #3822 = PseudoVLOXSEG4EI8_V_MF8_MF8_MASK + {5, OperandInfo457}, // Inst #3823 = PseudoVLOXSEG5EI16_V_M1_M1 + {8, OperandInfo458}, // Inst #3824 = PseudoVLOXSEG5EI16_V_M1_M1_MASK + {5, OperandInfo457}, // Inst #3825 = PseudoVLOXSEG5EI16_V_M1_MF2 + {8, OperandInfo458}, // Inst #3826 = PseudoVLOXSEG5EI16_V_M1_MF2_MASK + {5, OperandInfo459}, // Inst #3827 = PseudoVLOXSEG5EI16_V_M2_M1 + {8, OperandInfo460}, // Inst #3828 = PseudoVLOXSEG5EI16_V_M2_M1_MASK + {5, OperandInfo457}, // Inst #3829 = PseudoVLOXSEG5EI16_V_MF2_M1 + {8, OperandInfo458}, // Inst #3830 = PseudoVLOXSEG5EI16_V_MF2_M1_MASK + {5, OperandInfo457}, // Inst #3831 = PseudoVLOXSEG5EI16_V_MF2_MF2 + {8, OperandInfo458}, // Inst #3832 = PseudoVLOXSEG5EI16_V_MF2_MF2_MASK + {5, OperandInfo457}, // Inst #3833 = PseudoVLOXSEG5EI16_V_MF2_MF4 + {8, OperandInfo458}, // Inst #3834 = PseudoVLOXSEG5EI16_V_MF2_MF4_MASK + {5, OperandInfo457}, // Inst #3835 = PseudoVLOXSEG5EI16_V_MF4_M1 + {8, OperandInfo458}, // Inst #3836 = PseudoVLOXSEG5EI16_V_MF4_M1_MASK + {5, OperandInfo457}, // Inst #3837 = PseudoVLOXSEG5EI16_V_MF4_MF2 + {8, OperandInfo458}, // Inst #3838 = PseudoVLOXSEG5EI16_V_MF4_MF2_MASK + {5, OperandInfo457}, // Inst #3839 = PseudoVLOXSEG5EI16_V_MF4_MF4 + {8, OperandInfo458}, // Inst #3840 = PseudoVLOXSEG5EI16_V_MF4_MF4_MASK + {5, OperandInfo457}, // Inst #3841 = PseudoVLOXSEG5EI16_V_MF4_MF8 + {8, OperandInfo458}, // Inst #3842 = PseudoVLOXSEG5EI16_V_MF4_MF8_MASK + {5, OperandInfo457}, // Inst #3843 = PseudoVLOXSEG5EI32_V_M1_M1 + {8, OperandInfo458}, // Inst #3844 = PseudoVLOXSEG5EI32_V_M1_M1_MASK + {5, OperandInfo457}, // Inst #3845 = PseudoVLOXSEG5EI32_V_M1_MF2 + {8, OperandInfo458}, // Inst #3846 = PseudoVLOXSEG5EI32_V_M1_MF2_MASK + {5, OperandInfo457}, // Inst #3847 = PseudoVLOXSEG5EI32_V_M1_MF4 + {8, OperandInfo458}, // Inst #3848 = PseudoVLOXSEG5EI32_V_M1_MF4_MASK + {5, OperandInfo459}, // Inst #3849 = PseudoVLOXSEG5EI32_V_M2_M1 + {8, OperandInfo460}, // Inst #3850 = PseudoVLOXSEG5EI32_V_M2_M1_MASK + {5, OperandInfo459}, // Inst #3851 = PseudoVLOXSEG5EI32_V_M2_MF2 + {8, OperandInfo460}, // Inst #3852 = PseudoVLOXSEG5EI32_V_M2_MF2_MASK + {5, OperandInfo461}, // Inst #3853 = PseudoVLOXSEG5EI32_V_M4_M1 + {8, OperandInfo462}, // Inst #3854 = PseudoVLOXSEG5EI32_V_M4_M1_MASK + {5, OperandInfo457}, // Inst #3855 = PseudoVLOXSEG5EI32_V_MF2_M1 + {8, OperandInfo458}, // Inst #3856 = PseudoVLOXSEG5EI32_V_MF2_M1_MASK + {5, OperandInfo457}, // Inst #3857 = PseudoVLOXSEG5EI32_V_MF2_MF2 + {8, OperandInfo458}, // Inst #3858 = PseudoVLOXSEG5EI32_V_MF2_MF2_MASK + {5, OperandInfo457}, // Inst #3859 = PseudoVLOXSEG5EI32_V_MF2_MF4 + {8, OperandInfo458}, // Inst #3860 = PseudoVLOXSEG5EI32_V_MF2_MF4_MASK + {5, OperandInfo457}, // Inst #3861 = PseudoVLOXSEG5EI32_V_MF2_MF8 + {8, OperandInfo458}, // Inst #3862 = PseudoVLOXSEG5EI32_V_MF2_MF8_MASK + {5, OperandInfo457}, // Inst #3863 = PseudoVLOXSEG5EI64_V_M1_M1 + {8, OperandInfo458}, // Inst #3864 = PseudoVLOXSEG5EI64_V_M1_M1_MASK + {5, OperandInfo457}, // Inst #3865 = PseudoVLOXSEG5EI64_V_M1_MF2 + {8, OperandInfo458}, // Inst #3866 = PseudoVLOXSEG5EI64_V_M1_MF2_MASK + {5, OperandInfo457}, // Inst #3867 = PseudoVLOXSEG5EI64_V_M1_MF4 + {8, OperandInfo458}, // Inst #3868 = PseudoVLOXSEG5EI64_V_M1_MF4_MASK + {5, OperandInfo457}, // Inst #3869 = PseudoVLOXSEG5EI64_V_M1_MF8 + {8, OperandInfo458}, // Inst #3870 = PseudoVLOXSEG5EI64_V_M1_MF8_MASK + {5, OperandInfo459}, // Inst #3871 = PseudoVLOXSEG5EI64_V_M2_M1 + {8, OperandInfo460}, // Inst #3872 = PseudoVLOXSEG5EI64_V_M2_M1_MASK + {5, OperandInfo459}, // Inst #3873 = PseudoVLOXSEG5EI64_V_M2_MF2 + {8, OperandInfo460}, // Inst #3874 = PseudoVLOXSEG5EI64_V_M2_MF2_MASK + {5, OperandInfo459}, // Inst #3875 = PseudoVLOXSEG5EI64_V_M2_MF4 + {8, OperandInfo460}, // Inst #3876 = PseudoVLOXSEG5EI64_V_M2_MF4_MASK + {5, OperandInfo461}, // Inst #3877 = PseudoVLOXSEG5EI64_V_M4_M1 + {8, OperandInfo462}, // Inst #3878 = PseudoVLOXSEG5EI64_V_M4_M1_MASK + {5, OperandInfo461}, // Inst #3879 = PseudoVLOXSEG5EI64_V_M4_MF2 + {8, OperandInfo462}, // Inst #3880 = PseudoVLOXSEG5EI64_V_M4_MF2_MASK + {5, OperandInfo463}, // Inst #3881 = PseudoVLOXSEG5EI64_V_M8_M1 + {8, OperandInfo464}, // Inst #3882 = PseudoVLOXSEG5EI64_V_M8_M1_MASK + {5, OperandInfo457}, // Inst #3883 = PseudoVLOXSEG5EI8_V_M1_M1 + {8, OperandInfo458}, // Inst #3884 = PseudoVLOXSEG5EI8_V_M1_M1_MASK + {5, OperandInfo457}, // Inst #3885 = PseudoVLOXSEG5EI8_V_MF2_M1 + {8, OperandInfo458}, // Inst #3886 = PseudoVLOXSEG5EI8_V_MF2_M1_MASK + {5, OperandInfo457}, // Inst #3887 = PseudoVLOXSEG5EI8_V_MF2_MF2 + {8, OperandInfo458}, // Inst #3888 = PseudoVLOXSEG5EI8_V_MF2_MF2_MASK + {5, OperandInfo457}, // Inst #3889 = PseudoVLOXSEG5EI8_V_MF4_M1 + {8, OperandInfo458}, // Inst #3890 = PseudoVLOXSEG5EI8_V_MF4_M1_MASK + {5, OperandInfo457}, // Inst #3891 = PseudoVLOXSEG5EI8_V_MF4_MF2 + {8, OperandInfo458}, // Inst #3892 = PseudoVLOXSEG5EI8_V_MF4_MF2_MASK + {5, OperandInfo457}, // Inst #3893 = PseudoVLOXSEG5EI8_V_MF4_MF4 + {8, OperandInfo458}, // Inst #3894 = PseudoVLOXSEG5EI8_V_MF4_MF4_MASK + {5, OperandInfo457}, // Inst #3895 = PseudoVLOXSEG5EI8_V_MF8_M1 + {8, OperandInfo458}, // Inst #3896 = PseudoVLOXSEG5EI8_V_MF8_M1_MASK + {5, OperandInfo457}, // Inst #3897 = PseudoVLOXSEG5EI8_V_MF8_MF2 + {8, OperandInfo458}, // Inst #3898 = PseudoVLOXSEG5EI8_V_MF8_MF2_MASK + {5, OperandInfo457}, // Inst #3899 = PseudoVLOXSEG5EI8_V_MF8_MF4 + {8, OperandInfo458}, // Inst #3900 = PseudoVLOXSEG5EI8_V_MF8_MF4_MASK + {5, OperandInfo457}, // Inst #3901 = PseudoVLOXSEG5EI8_V_MF8_MF8 + {8, OperandInfo458}, // Inst #3902 = PseudoVLOXSEG5EI8_V_MF8_MF8_MASK + {5, OperandInfo465}, // Inst #3903 = PseudoVLOXSEG6EI16_V_M1_M1 + {8, OperandInfo466}, // Inst #3904 = PseudoVLOXSEG6EI16_V_M1_M1_MASK + {5, OperandInfo465}, // Inst #3905 = PseudoVLOXSEG6EI16_V_M1_MF2 + {8, OperandInfo466}, // Inst #3906 = PseudoVLOXSEG6EI16_V_M1_MF2_MASK + {5, OperandInfo467}, // Inst #3907 = PseudoVLOXSEG6EI16_V_M2_M1 + {8, OperandInfo468}, // Inst #3908 = PseudoVLOXSEG6EI16_V_M2_M1_MASK + {5, OperandInfo465}, // Inst #3909 = PseudoVLOXSEG6EI16_V_MF2_M1 + {8, OperandInfo466}, // Inst #3910 = PseudoVLOXSEG6EI16_V_MF2_M1_MASK + {5, OperandInfo465}, // Inst #3911 = PseudoVLOXSEG6EI16_V_MF2_MF2 + {8, OperandInfo466}, // Inst #3912 = PseudoVLOXSEG6EI16_V_MF2_MF2_MASK + {5, OperandInfo465}, // Inst #3913 = PseudoVLOXSEG6EI16_V_MF2_MF4 + {8, OperandInfo466}, // Inst #3914 = PseudoVLOXSEG6EI16_V_MF2_MF4_MASK + {5, OperandInfo465}, // Inst #3915 = PseudoVLOXSEG6EI16_V_MF4_M1 + {8, OperandInfo466}, // Inst #3916 = PseudoVLOXSEG6EI16_V_MF4_M1_MASK + {5, OperandInfo465}, // Inst #3917 = PseudoVLOXSEG6EI16_V_MF4_MF2 + {8, OperandInfo466}, // Inst #3918 = PseudoVLOXSEG6EI16_V_MF4_MF2_MASK + {5, OperandInfo465}, // Inst #3919 = PseudoVLOXSEG6EI16_V_MF4_MF4 + {8, OperandInfo466}, // Inst #3920 = PseudoVLOXSEG6EI16_V_MF4_MF4_MASK + {5, OperandInfo465}, // Inst #3921 = PseudoVLOXSEG6EI16_V_MF4_MF8 + {8, OperandInfo466}, // Inst #3922 = PseudoVLOXSEG6EI16_V_MF4_MF8_MASK + {5, OperandInfo465}, // Inst #3923 = PseudoVLOXSEG6EI32_V_M1_M1 + {8, OperandInfo466}, // Inst #3924 = PseudoVLOXSEG6EI32_V_M1_M1_MASK + {5, OperandInfo465}, // Inst #3925 = PseudoVLOXSEG6EI32_V_M1_MF2 + {8, OperandInfo466}, // Inst #3926 = PseudoVLOXSEG6EI32_V_M1_MF2_MASK + {5, OperandInfo465}, // Inst #3927 = PseudoVLOXSEG6EI32_V_M1_MF4 + {8, OperandInfo466}, // Inst #3928 = PseudoVLOXSEG6EI32_V_M1_MF4_MASK + {5, OperandInfo467}, // Inst #3929 = PseudoVLOXSEG6EI32_V_M2_M1 + {8, OperandInfo468}, // Inst #3930 = PseudoVLOXSEG6EI32_V_M2_M1_MASK + {5, OperandInfo467}, // Inst #3931 = PseudoVLOXSEG6EI32_V_M2_MF2 + {8, OperandInfo468}, // Inst #3932 = PseudoVLOXSEG6EI32_V_M2_MF2_MASK + {5, OperandInfo469}, // Inst #3933 = PseudoVLOXSEG6EI32_V_M4_M1 + {8, OperandInfo470}, // Inst #3934 = PseudoVLOXSEG6EI32_V_M4_M1_MASK + {5, OperandInfo465}, // Inst #3935 = PseudoVLOXSEG6EI32_V_MF2_M1 + {8, OperandInfo466}, // Inst #3936 = PseudoVLOXSEG6EI32_V_MF2_M1_MASK + {5, OperandInfo465}, // Inst #3937 = PseudoVLOXSEG6EI32_V_MF2_MF2 + {8, OperandInfo466}, // Inst #3938 = PseudoVLOXSEG6EI32_V_MF2_MF2_MASK + {5, OperandInfo465}, // Inst #3939 = PseudoVLOXSEG6EI32_V_MF2_MF4 + {8, OperandInfo466}, // Inst #3940 = PseudoVLOXSEG6EI32_V_MF2_MF4_MASK + {5, OperandInfo465}, // Inst #3941 = PseudoVLOXSEG6EI32_V_MF2_MF8 + {8, OperandInfo466}, // Inst #3942 = PseudoVLOXSEG6EI32_V_MF2_MF8_MASK + {5, OperandInfo465}, // Inst #3943 = PseudoVLOXSEG6EI64_V_M1_M1 + {8, OperandInfo466}, // Inst #3944 = PseudoVLOXSEG6EI64_V_M1_M1_MASK + {5, OperandInfo465}, // Inst #3945 = PseudoVLOXSEG6EI64_V_M1_MF2 + {8, OperandInfo466}, // Inst #3946 = PseudoVLOXSEG6EI64_V_M1_MF2_MASK + {5, OperandInfo465}, // Inst #3947 = PseudoVLOXSEG6EI64_V_M1_MF4 + {8, OperandInfo466}, // Inst #3948 = PseudoVLOXSEG6EI64_V_M1_MF4_MASK + {5, OperandInfo465}, // Inst #3949 = PseudoVLOXSEG6EI64_V_M1_MF8 + {8, OperandInfo466}, // Inst #3950 = PseudoVLOXSEG6EI64_V_M1_MF8_MASK + {5, OperandInfo467}, // Inst #3951 = PseudoVLOXSEG6EI64_V_M2_M1 + {8, OperandInfo468}, // Inst #3952 = PseudoVLOXSEG6EI64_V_M2_M1_MASK + {5, OperandInfo467}, // Inst #3953 = PseudoVLOXSEG6EI64_V_M2_MF2 + {8, OperandInfo468}, // Inst #3954 = PseudoVLOXSEG6EI64_V_M2_MF2_MASK + {5, OperandInfo467}, // Inst #3955 = PseudoVLOXSEG6EI64_V_M2_MF4 + {8, OperandInfo468}, // Inst #3956 = PseudoVLOXSEG6EI64_V_M2_MF4_MASK + {5, OperandInfo469}, // Inst #3957 = PseudoVLOXSEG6EI64_V_M4_M1 + {8, OperandInfo470}, // Inst #3958 = PseudoVLOXSEG6EI64_V_M4_M1_MASK + {5, OperandInfo469}, // Inst #3959 = PseudoVLOXSEG6EI64_V_M4_MF2 + {8, OperandInfo470}, // Inst #3960 = PseudoVLOXSEG6EI64_V_M4_MF2_MASK + {5, OperandInfo471}, // Inst #3961 = PseudoVLOXSEG6EI64_V_M8_M1 + {8, OperandInfo472}, // Inst #3962 = PseudoVLOXSEG6EI64_V_M8_M1_MASK + {5, OperandInfo465}, // Inst #3963 = PseudoVLOXSEG6EI8_V_M1_M1 + {8, OperandInfo466}, // Inst #3964 = PseudoVLOXSEG6EI8_V_M1_M1_MASK + {5, OperandInfo465}, // Inst #3965 = PseudoVLOXSEG6EI8_V_MF2_M1 + {8, OperandInfo466}, // Inst #3966 = PseudoVLOXSEG6EI8_V_MF2_M1_MASK + {5, OperandInfo465}, // Inst #3967 = PseudoVLOXSEG6EI8_V_MF2_MF2 + {8, OperandInfo466}, // Inst #3968 = PseudoVLOXSEG6EI8_V_MF2_MF2_MASK + {5, OperandInfo465}, // Inst #3969 = PseudoVLOXSEG6EI8_V_MF4_M1 + {8, OperandInfo466}, // Inst #3970 = PseudoVLOXSEG6EI8_V_MF4_M1_MASK + {5, OperandInfo465}, // Inst #3971 = PseudoVLOXSEG6EI8_V_MF4_MF2 + {8, OperandInfo466}, // Inst #3972 = PseudoVLOXSEG6EI8_V_MF4_MF2_MASK + {5, OperandInfo465}, // Inst #3973 = PseudoVLOXSEG6EI8_V_MF4_MF4 + {8, OperandInfo466}, // Inst #3974 = PseudoVLOXSEG6EI8_V_MF4_MF4_MASK + {5, OperandInfo465}, // Inst #3975 = PseudoVLOXSEG6EI8_V_MF8_M1 + {8, OperandInfo466}, // Inst #3976 = PseudoVLOXSEG6EI8_V_MF8_M1_MASK + {5, OperandInfo465}, // Inst #3977 = PseudoVLOXSEG6EI8_V_MF8_MF2 + {8, OperandInfo466}, // Inst #3978 = PseudoVLOXSEG6EI8_V_MF8_MF2_MASK + {5, OperandInfo465}, // Inst #3979 = PseudoVLOXSEG6EI8_V_MF8_MF4 + {8, OperandInfo466}, // Inst #3980 = PseudoVLOXSEG6EI8_V_MF8_MF4_MASK + {5, OperandInfo465}, // Inst #3981 = PseudoVLOXSEG6EI8_V_MF8_MF8 + {8, OperandInfo466}, // Inst #3982 = PseudoVLOXSEG6EI8_V_MF8_MF8_MASK + {5, OperandInfo473}, // Inst #3983 = PseudoVLOXSEG7EI16_V_M1_M1 + {8, OperandInfo474}, // Inst #3984 = PseudoVLOXSEG7EI16_V_M1_M1_MASK + {5, OperandInfo473}, // Inst #3985 = PseudoVLOXSEG7EI16_V_M1_MF2 + {8, OperandInfo474}, // Inst #3986 = PseudoVLOXSEG7EI16_V_M1_MF2_MASK + {5, OperandInfo475}, // Inst #3987 = PseudoVLOXSEG7EI16_V_M2_M1 + {8, OperandInfo476}, // Inst #3988 = PseudoVLOXSEG7EI16_V_M2_M1_MASK + {5, OperandInfo473}, // Inst #3989 = PseudoVLOXSEG7EI16_V_MF2_M1 + {8, OperandInfo474}, // Inst #3990 = PseudoVLOXSEG7EI16_V_MF2_M1_MASK + {5, OperandInfo473}, // Inst #3991 = PseudoVLOXSEG7EI16_V_MF2_MF2 + {8, OperandInfo474}, // Inst #3992 = PseudoVLOXSEG7EI16_V_MF2_MF2_MASK + {5, OperandInfo473}, // Inst #3993 = PseudoVLOXSEG7EI16_V_MF2_MF4 + {8, OperandInfo474}, // Inst #3994 = PseudoVLOXSEG7EI16_V_MF2_MF4_MASK + {5, OperandInfo473}, // Inst #3995 = PseudoVLOXSEG7EI16_V_MF4_M1 + {8, OperandInfo474}, // Inst #3996 = PseudoVLOXSEG7EI16_V_MF4_M1_MASK + {5, OperandInfo473}, // Inst #3997 = PseudoVLOXSEG7EI16_V_MF4_MF2 + {8, OperandInfo474}, // Inst #3998 = PseudoVLOXSEG7EI16_V_MF4_MF2_MASK + {5, OperandInfo473}, // Inst #3999 = PseudoVLOXSEG7EI16_V_MF4_MF4 + {8, OperandInfo474}, // Inst #4000 = PseudoVLOXSEG7EI16_V_MF4_MF4_MASK + {5, OperandInfo473}, // Inst #4001 = PseudoVLOXSEG7EI16_V_MF4_MF8 + {8, OperandInfo474}, // Inst #4002 = PseudoVLOXSEG7EI16_V_MF4_MF8_MASK + {5, OperandInfo473}, // Inst #4003 = PseudoVLOXSEG7EI32_V_M1_M1 + {8, OperandInfo474}, // Inst #4004 = PseudoVLOXSEG7EI32_V_M1_M1_MASK + {5, OperandInfo473}, // Inst #4005 = PseudoVLOXSEG7EI32_V_M1_MF2 + {8, OperandInfo474}, // Inst #4006 = PseudoVLOXSEG7EI32_V_M1_MF2_MASK + {5, OperandInfo473}, // Inst #4007 = PseudoVLOXSEG7EI32_V_M1_MF4 + {8, OperandInfo474}, // Inst #4008 = PseudoVLOXSEG7EI32_V_M1_MF4_MASK + {5, OperandInfo475}, // Inst #4009 = PseudoVLOXSEG7EI32_V_M2_M1 + {8, OperandInfo476}, // Inst #4010 = PseudoVLOXSEG7EI32_V_M2_M1_MASK + {5, OperandInfo475}, // Inst #4011 = PseudoVLOXSEG7EI32_V_M2_MF2 + {8, OperandInfo476}, // Inst #4012 = PseudoVLOXSEG7EI32_V_M2_MF2_MASK + {5, OperandInfo477}, // Inst #4013 = PseudoVLOXSEG7EI32_V_M4_M1 + {8, OperandInfo478}, // Inst #4014 = PseudoVLOXSEG7EI32_V_M4_M1_MASK + {5, OperandInfo473}, // Inst #4015 = PseudoVLOXSEG7EI32_V_MF2_M1 + {8, OperandInfo474}, // Inst #4016 = PseudoVLOXSEG7EI32_V_MF2_M1_MASK + {5, OperandInfo473}, // Inst #4017 = PseudoVLOXSEG7EI32_V_MF2_MF2 + {8, OperandInfo474}, // Inst #4018 = PseudoVLOXSEG7EI32_V_MF2_MF2_MASK + {5, OperandInfo473}, // Inst #4019 = PseudoVLOXSEG7EI32_V_MF2_MF4 + {8, OperandInfo474}, // Inst #4020 = PseudoVLOXSEG7EI32_V_MF2_MF4_MASK + {5, OperandInfo473}, // Inst #4021 = PseudoVLOXSEG7EI32_V_MF2_MF8 + {8, OperandInfo474}, // Inst #4022 = PseudoVLOXSEG7EI32_V_MF2_MF8_MASK + {5, OperandInfo473}, // Inst #4023 = PseudoVLOXSEG7EI64_V_M1_M1 + {8, OperandInfo474}, // Inst #4024 = PseudoVLOXSEG7EI64_V_M1_M1_MASK + {5, OperandInfo473}, // Inst #4025 = PseudoVLOXSEG7EI64_V_M1_MF2 + {8, OperandInfo474}, // Inst #4026 = PseudoVLOXSEG7EI64_V_M1_MF2_MASK + {5, OperandInfo473}, // Inst #4027 = PseudoVLOXSEG7EI64_V_M1_MF4 + {8, OperandInfo474}, // Inst #4028 = PseudoVLOXSEG7EI64_V_M1_MF4_MASK + {5, OperandInfo473}, // Inst #4029 = PseudoVLOXSEG7EI64_V_M1_MF8 + {8, OperandInfo474}, // Inst #4030 = PseudoVLOXSEG7EI64_V_M1_MF8_MASK + {5, OperandInfo475}, // Inst #4031 = PseudoVLOXSEG7EI64_V_M2_M1 + {8, OperandInfo476}, // Inst #4032 = PseudoVLOXSEG7EI64_V_M2_M1_MASK + {5, OperandInfo475}, // Inst #4033 = PseudoVLOXSEG7EI64_V_M2_MF2 + {8, OperandInfo476}, // Inst #4034 = PseudoVLOXSEG7EI64_V_M2_MF2_MASK + {5, OperandInfo475}, // Inst #4035 = PseudoVLOXSEG7EI64_V_M2_MF4 + {8, OperandInfo476}, // Inst #4036 = PseudoVLOXSEG7EI64_V_M2_MF4_MASK + {5, OperandInfo477}, // Inst #4037 = PseudoVLOXSEG7EI64_V_M4_M1 + {8, OperandInfo478}, // Inst #4038 = PseudoVLOXSEG7EI64_V_M4_M1_MASK + {5, OperandInfo477}, // Inst #4039 = PseudoVLOXSEG7EI64_V_M4_MF2 + {8, OperandInfo478}, // Inst #4040 = PseudoVLOXSEG7EI64_V_M4_MF2_MASK + {5, OperandInfo479}, // Inst #4041 = PseudoVLOXSEG7EI64_V_M8_M1 + {8, OperandInfo480}, // Inst #4042 = PseudoVLOXSEG7EI64_V_M8_M1_MASK + {5, OperandInfo473}, // Inst #4043 = PseudoVLOXSEG7EI8_V_M1_M1 + {8, OperandInfo474}, // Inst #4044 = PseudoVLOXSEG7EI8_V_M1_M1_MASK + {5, OperandInfo473}, // Inst #4045 = PseudoVLOXSEG7EI8_V_MF2_M1 + {8, OperandInfo474}, // Inst #4046 = PseudoVLOXSEG7EI8_V_MF2_M1_MASK + {5, OperandInfo473}, // Inst #4047 = PseudoVLOXSEG7EI8_V_MF2_MF2 + {8, OperandInfo474}, // Inst #4048 = PseudoVLOXSEG7EI8_V_MF2_MF2_MASK + {5, OperandInfo473}, // Inst #4049 = PseudoVLOXSEG7EI8_V_MF4_M1 + {8, OperandInfo474}, // Inst #4050 = PseudoVLOXSEG7EI8_V_MF4_M1_MASK + {5, OperandInfo473}, // Inst #4051 = PseudoVLOXSEG7EI8_V_MF4_MF2 + {8, OperandInfo474}, // Inst #4052 = PseudoVLOXSEG7EI8_V_MF4_MF2_MASK + {5, OperandInfo473}, // Inst #4053 = PseudoVLOXSEG7EI8_V_MF4_MF4 + {8, OperandInfo474}, // Inst #4054 = PseudoVLOXSEG7EI8_V_MF4_MF4_MASK + {5, OperandInfo473}, // Inst #4055 = PseudoVLOXSEG7EI8_V_MF8_M1 + {8, OperandInfo474}, // Inst #4056 = PseudoVLOXSEG7EI8_V_MF8_M1_MASK + {5, OperandInfo473}, // Inst #4057 = PseudoVLOXSEG7EI8_V_MF8_MF2 + {8, OperandInfo474}, // Inst #4058 = PseudoVLOXSEG7EI8_V_MF8_MF2_MASK + {5, OperandInfo473}, // Inst #4059 = PseudoVLOXSEG7EI8_V_MF8_MF4 + {8, OperandInfo474}, // Inst #4060 = PseudoVLOXSEG7EI8_V_MF8_MF4_MASK + {5, OperandInfo473}, // Inst #4061 = PseudoVLOXSEG7EI8_V_MF8_MF8 + {8, OperandInfo474}, // Inst #4062 = PseudoVLOXSEG7EI8_V_MF8_MF8_MASK + {5, OperandInfo481}, // Inst #4063 = PseudoVLOXSEG8EI16_V_M1_M1 + {8, OperandInfo482}, // Inst #4064 = PseudoVLOXSEG8EI16_V_M1_M1_MASK + {5, OperandInfo481}, // Inst #4065 = PseudoVLOXSEG8EI16_V_M1_MF2 + {8, OperandInfo482}, // Inst #4066 = PseudoVLOXSEG8EI16_V_M1_MF2_MASK + {5, OperandInfo483}, // Inst #4067 = PseudoVLOXSEG8EI16_V_M2_M1 + {8, OperandInfo484}, // Inst #4068 = PseudoVLOXSEG8EI16_V_M2_M1_MASK + {5, OperandInfo481}, // Inst #4069 = PseudoVLOXSEG8EI16_V_MF2_M1 + {8, OperandInfo482}, // Inst #4070 = PseudoVLOXSEG8EI16_V_MF2_M1_MASK + {5, OperandInfo481}, // Inst #4071 = PseudoVLOXSEG8EI16_V_MF2_MF2 + {8, OperandInfo482}, // Inst #4072 = PseudoVLOXSEG8EI16_V_MF2_MF2_MASK + {5, OperandInfo481}, // Inst #4073 = PseudoVLOXSEG8EI16_V_MF2_MF4 + {8, OperandInfo482}, // Inst #4074 = PseudoVLOXSEG8EI16_V_MF2_MF4_MASK + {5, OperandInfo481}, // Inst #4075 = PseudoVLOXSEG8EI16_V_MF4_M1 + {8, OperandInfo482}, // Inst #4076 = PseudoVLOXSEG8EI16_V_MF4_M1_MASK + {5, OperandInfo481}, // Inst #4077 = PseudoVLOXSEG8EI16_V_MF4_MF2 + {8, OperandInfo482}, // Inst #4078 = PseudoVLOXSEG8EI16_V_MF4_MF2_MASK + {5, OperandInfo481}, // Inst #4079 = PseudoVLOXSEG8EI16_V_MF4_MF4 + {8, OperandInfo482}, // Inst #4080 = PseudoVLOXSEG8EI16_V_MF4_MF4_MASK + {5, OperandInfo481}, // Inst #4081 = PseudoVLOXSEG8EI16_V_MF4_MF8 + {8, OperandInfo482}, // Inst #4082 = PseudoVLOXSEG8EI16_V_MF4_MF8_MASK + {5, OperandInfo481}, // Inst #4083 = PseudoVLOXSEG8EI32_V_M1_M1 + {8, OperandInfo482}, // Inst #4084 = PseudoVLOXSEG8EI32_V_M1_M1_MASK + {5, OperandInfo481}, // Inst #4085 = PseudoVLOXSEG8EI32_V_M1_MF2 + {8, OperandInfo482}, // Inst #4086 = PseudoVLOXSEG8EI32_V_M1_MF2_MASK + {5, OperandInfo481}, // Inst #4087 = PseudoVLOXSEG8EI32_V_M1_MF4 + {8, OperandInfo482}, // Inst #4088 = PseudoVLOXSEG8EI32_V_M1_MF4_MASK + {5, OperandInfo483}, // Inst #4089 = PseudoVLOXSEG8EI32_V_M2_M1 + {8, OperandInfo484}, // Inst #4090 = PseudoVLOXSEG8EI32_V_M2_M1_MASK + {5, OperandInfo483}, // Inst #4091 = PseudoVLOXSEG8EI32_V_M2_MF2 + {8, OperandInfo484}, // Inst #4092 = PseudoVLOXSEG8EI32_V_M2_MF2_MASK + {5, OperandInfo485}, // Inst #4093 = PseudoVLOXSEG8EI32_V_M4_M1 + {8, OperandInfo486}, // Inst #4094 = PseudoVLOXSEG8EI32_V_M4_M1_MASK + {5, OperandInfo481}, // Inst #4095 = PseudoVLOXSEG8EI32_V_MF2_M1 + {8, OperandInfo482}, // Inst #4096 = PseudoVLOXSEG8EI32_V_MF2_M1_MASK + {5, OperandInfo481}, // Inst #4097 = PseudoVLOXSEG8EI32_V_MF2_MF2 + {8, OperandInfo482}, // Inst #4098 = PseudoVLOXSEG8EI32_V_MF2_MF2_MASK + {5, OperandInfo481}, // Inst #4099 = PseudoVLOXSEG8EI32_V_MF2_MF4 + {8, OperandInfo482}, // Inst #4100 = PseudoVLOXSEG8EI32_V_MF2_MF4_MASK + {5, OperandInfo481}, // Inst #4101 = PseudoVLOXSEG8EI32_V_MF2_MF8 + {8, OperandInfo482}, // Inst #4102 = PseudoVLOXSEG8EI32_V_MF2_MF8_MASK + {5, OperandInfo481}, // Inst #4103 = PseudoVLOXSEG8EI64_V_M1_M1 + {8, OperandInfo482}, // Inst #4104 = PseudoVLOXSEG8EI64_V_M1_M1_MASK + {5, OperandInfo481}, // Inst #4105 = PseudoVLOXSEG8EI64_V_M1_MF2 + {8, OperandInfo482}, // Inst #4106 = PseudoVLOXSEG8EI64_V_M1_MF2_MASK + {5, OperandInfo481}, // Inst #4107 = PseudoVLOXSEG8EI64_V_M1_MF4 + {8, OperandInfo482}, // Inst #4108 = PseudoVLOXSEG8EI64_V_M1_MF4_MASK + {5, OperandInfo481}, // Inst #4109 = PseudoVLOXSEG8EI64_V_M1_MF8 + {8, OperandInfo482}, // Inst #4110 = PseudoVLOXSEG8EI64_V_M1_MF8_MASK + {5, OperandInfo483}, // Inst #4111 = PseudoVLOXSEG8EI64_V_M2_M1 + {8, OperandInfo484}, // Inst #4112 = PseudoVLOXSEG8EI64_V_M2_M1_MASK + {5, OperandInfo483}, // Inst #4113 = PseudoVLOXSEG8EI64_V_M2_MF2 + {8, OperandInfo484}, // Inst #4114 = PseudoVLOXSEG8EI64_V_M2_MF2_MASK + {5, OperandInfo483}, // Inst #4115 = PseudoVLOXSEG8EI64_V_M2_MF4 + {8, OperandInfo484}, // Inst #4116 = PseudoVLOXSEG8EI64_V_M2_MF4_MASK + {5, OperandInfo485}, // Inst #4117 = PseudoVLOXSEG8EI64_V_M4_M1 + {8, OperandInfo486}, // Inst #4118 = PseudoVLOXSEG8EI64_V_M4_M1_MASK + {5, OperandInfo485}, // Inst #4119 = PseudoVLOXSEG8EI64_V_M4_MF2 + {8, OperandInfo486}, // Inst #4120 = PseudoVLOXSEG8EI64_V_M4_MF2_MASK + {5, OperandInfo487}, // Inst #4121 = PseudoVLOXSEG8EI64_V_M8_M1 + {8, OperandInfo488}, // Inst #4122 = PseudoVLOXSEG8EI64_V_M8_M1_MASK + {5, OperandInfo481}, // Inst #4123 = PseudoVLOXSEG8EI8_V_M1_M1 + {8, OperandInfo482}, // Inst #4124 = PseudoVLOXSEG8EI8_V_M1_M1_MASK + {5, OperandInfo481}, // Inst #4125 = PseudoVLOXSEG8EI8_V_MF2_M1 + {8, OperandInfo482}, // Inst #4126 = PseudoVLOXSEG8EI8_V_MF2_M1_MASK + {5, OperandInfo481}, // Inst #4127 = PseudoVLOXSEG8EI8_V_MF2_MF2 + {8, OperandInfo482}, // Inst #4128 = PseudoVLOXSEG8EI8_V_MF2_MF2_MASK + {5, OperandInfo481}, // Inst #4129 = PseudoVLOXSEG8EI8_V_MF4_M1 + {8, OperandInfo482}, // Inst #4130 = PseudoVLOXSEG8EI8_V_MF4_M1_MASK + {5, OperandInfo481}, // Inst #4131 = PseudoVLOXSEG8EI8_V_MF4_MF2 + {8, OperandInfo482}, // Inst #4132 = PseudoVLOXSEG8EI8_V_MF4_MF2_MASK + {5, OperandInfo481}, // Inst #4133 = PseudoVLOXSEG8EI8_V_MF4_MF4 + {8, OperandInfo482}, // Inst #4134 = PseudoVLOXSEG8EI8_V_MF4_MF4_MASK + {5, OperandInfo481}, // Inst #4135 = PseudoVLOXSEG8EI8_V_MF8_M1 + {8, OperandInfo482}, // Inst #4136 = PseudoVLOXSEG8EI8_V_MF8_M1_MASK + {5, OperandInfo481}, // Inst #4137 = PseudoVLOXSEG8EI8_V_MF8_MF2 + {8, OperandInfo482}, // Inst #4138 = PseudoVLOXSEG8EI8_V_MF8_MF2_MASK + {5, OperandInfo481}, // Inst #4139 = PseudoVLOXSEG8EI8_V_MF8_MF4 + {8, OperandInfo482}, // Inst #4140 = PseudoVLOXSEG8EI8_V_MF8_MF4_MASK + {5, OperandInfo481}, // Inst #4141 = PseudoVLOXSEG8EI8_V_MF8_MF8 + {8, OperandInfo482}, // Inst #4142 = PseudoVLOXSEG8EI8_V_MF8_MF8_MASK + {5, OperandInfo489}, // Inst #4143 = PseudoVLSE16_V_M1 + {8, OperandInfo490}, // Inst #4144 = PseudoVLSE16_V_M1_MASK + {5, OperandInfo491}, // Inst #4145 = PseudoVLSE16_V_M2 + {8, OperandInfo492}, // Inst #4146 = PseudoVLSE16_V_M2_MASK + {5, OperandInfo493}, // Inst #4147 = PseudoVLSE16_V_M4 + {8, OperandInfo494}, // Inst #4148 = PseudoVLSE16_V_M4_MASK + {5, OperandInfo495}, // Inst #4149 = PseudoVLSE16_V_M8 + {8, OperandInfo496}, // Inst #4150 = PseudoVLSE16_V_M8_MASK + {5, OperandInfo489}, // Inst #4151 = PseudoVLSE16_V_MF2 + {8, OperandInfo490}, // Inst #4152 = PseudoVLSE16_V_MF2_MASK + {5, OperandInfo489}, // Inst #4153 = PseudoVLSE16_V_MF4 + {8, OperandInfo490}, // Inst #4154 = PseudoVLSE16_V_MF4_MASK + {5, OperandInfo489}, // Inst #4155 = PseudoVLSE32_V_M1 + {8, OperandInfo490}, // Inst #4156 = PseudoVLSE32_V_M1_MASK + {5, OperandInfo491}, // Inst #4157 = PseudoVLSE32_V_M2 + {8, OperandInfo492}, // Inst #4158 = PseudoVLSE32_V_M2_MASK + {5, OperandInfo493}, // Inst #4159 = PseudoVLSE32_V_M4 + {8, OperandInfo494}, // Inst #4160 = PseudoVLSE32_V_M4_MASK + {5, OperandInfo495}, // Inst #4161 = PseudoVLSE32_V_M8 + {8, OperandInfo496}, // Inst #4162 = PseudoVLSE32_V_M8_MASK + {5, OperandInfo489}, // Inst #4163 = PseudoVLSE32_V_MF2 + {8, OperandInfo490}, // Inst #4164 = PseudoVLSE32_V_MF2_MASK + {5, OperandInfo489}, // Inst #4165 = PseudoVLSE64_V_M1 + {8, OperandInfo490}, // Inst #4166 = PseudoVLSE64_V_M1_MASK + {5, OperandInfo491}, // Inst #4167 = PseudoVLSE64_V_M2 + {8, OperandInfo492}, // Inst #4168 = PseudoVLSE64_V_M2_MASK + {5, OperandInfo493}, // Inst #4169 = PseudoVLSE64_V_M4 + {8, OperandInfo494}, // Inst #4170 = PseudoVLSE64_V_M4_MASK + {5, OperandInfo495}, // Inst #4171 = PseudoVLSE64_V_M8 + {8, OperandInfo496}, // Inst #4172 = PseudoVLSE64_V_M8_MASK + {5, OperandInfo489}, // Inst #4173 = PseudoVLSE8_V_M1 + {8, OperandInfo490}, // Inst #4174 = PseudoVLSE8_V_M1_MASK + {5, OperandInfo491}, // Inst #4175 = PseudoVLSE8_V_M2 + {8, OperandInfo492}, // Inst #4176 = PseudoVLSE8_V_M2_MASK + {5, OperandInfo493}, // Inst #4177 = PseudoVLSE8_V_M4 + {8, OperandInfo494}, // Inst #4178 = PseudoVLSE8_V_M4_MASK + {5, OperandInfo495}, // Inst #4179 = PseudoVLSE8_V_M8 + {8, OperandInfo496}, // Inst #4180 = PseudoVLSE8_V_M8_MASK + {5, OperandInfo489}, // Inst #4181 = PseudoVLSE8_V_MF2 + {8, OperandInfo490}, // Inst #4182 = PseudoVLSE8_V_MF2_MASK + {5, OperandInfo489}, // Inst #4183 = PseudoVLSE8_V_MF4 + {8, OperandInfo490}, // Inst #4184 = PseudoVLSE8_V_MF4_MASK + {5, OperandInfo489}, // Inst #4185 = PseudoVLSE8_V_MF8 + {8, OperandInfo490}, // Inst #4186 = PseudoVLSE8_V_MF8_MASK + {4, OperandInfo497}, // Inst #4187 = PseudoVLSEG2E16FF_V_M1 + {7, OperandInfo498}, // Inst #4188 = PseudoVLSEG2E16FF_V_M1_MASK + {4, OperandInfo499}, // Inst #4189 = PseudoVLSEG2E16FF_V_M2 + {7, OperandInfo500}, // Inst #4190 = PseudoVLSEG2E16FF_V_M2_MASK + {4, OperandInfo501}, // Inst #4191 = PseudoVLSEG2E16FF_V_M4 + {7, OperandInfo502}, // Inst #4192 = PseudoVLSEG2E16FF_V_M4_MASK + {4, OperandInfo497}, // Inst #4193 = PseudoVLSEG2E16FF_V_MF2 + {7, OperandInfo498}, // Inst #4194 = PseudoVLSEG2E16FF_V_MF2_MASK + {4, OperandInfo497}, // Inst #4195 = PseudoVLSEG2E16FF_V_MF4 + {7, OperandInfo498}, // Inst #4196 = PseudoVLSEG2E16FF_V_MF4_MASK + {4, OperandInfo497}, // Inst #4197 = PseudoVLSEG2E16_V_M1 + {7, OperandInfo498}, // Inst #4198 = PseudoVLSEG2E16_V_M1_MASK + {4, OperandInfo499}, // Inst #4199 = PseudoVLSEG2E16_V_M2 + {7, OperandInfo500}, // Inst #4200 = PseudoVLSEG2E16_V_M2_MASK + {4, OperandInfo501}, // Inst #4201 = PseudoVLSEG2E16_V_M4 + {7, OperandInfo502}, // Inst #4202 = PseudoVLSEG2E16_V_M4_MASK + {4, OperandInfo497}, // Inst #4203 = PseudoVLSEG2E16_V_MF2 + {7, OperandInfo498}, // Inst #4204 = PseudoVLSEG2E16_V_MF2_MASK + {4, OperandInfo497}, // Inst #4205 = PseudoVLSEG2E16_V_MF4 + {7, OperandInfo498}, // Inst #4206 = PseudoVLSEG2E16_V_MF4_MASK + {4, OperandInfo497}, // Inst #4207 = PseudoVLSEG2E32FF_V_M1 + {7, OperandInfo498}, // Inst #4208 = PseudoVLSEG2E32FF_V_M1_MASK + {4, OperandInfo499}, // Inst #4209 = PseudoVLSEG2E32FF_V_M2 + {7, OperandInfo500}, // Inst #4210 = PseudoVLSEG2E32FF_V_M2_MASK + {4, OperandInfo501}, // Inst #4211 = PseudoVLSEG2E32FF_V_M4 + {7, OperandInfo502}, // Inst #4212 = PseudoVLSEG2E32FF_V_M4_MASK + {4, OperandInfo497}, // Inst #4213 = PseudoVLSEG2E32FF_V_MF2 + {7, OperandInfo498}, // Inst #4214 = PseudoVLSEG2E32FF_V_MF2_MASK + {4, OperandInfo497}, // Inst #4215 = PseudoVLSEG2E32_V_M1 + {7, OperandInfo498}, // Inst #4216 = PseudoVLSEG2E32_V_M1_MASK + {4, OperandInfo499}, // Inst #4217 = PseudoVLSEG2E32_V_M2 + {7, OperandInfo500}, // Inst #4218 = PseudoVLSEG2E32_V_M2_MASK + {4, OperandInfo501}, // Inst #4219 = PseudoVLSEG2E32_V_M4 + {7, OperandInfo502}, // Inst #4220 = PseudoVLSEG2E32_V_M4_MASK + {4, OperandInfo497}, // Inst #4221 = PseudoVLSEG2E32_V_MF2 + {7, OperandInfo498}, // Inst #4222 = PseudoVLSEG2E32_V_MF2_MASK + {4, OperandInfo497}, // Inst #4223 = PseudoVLSEG2E64FF_V_M1 + {7, OperandInfo498}, // Inst #4224 = PseudoVLSEG2E64FF_V_M1_MASK + {4, OperandInfo499}, // Inst #4225 = PseudoVLSEG2E64FF_V_M2 + {7, OperandInfo500}, // Inst #4226 = PseudoVLSEG2E64FF_V_M2_MASK + {4, OperandInfo501}, // Inst #4227 = PseudoVLSEG2E64FF_V_M4 + {7, OperandInfo502}, // Inst #4228 = PseudoVLSEG2E64FF_V_M4_MASK + {4, OperandInfo497}, // Inst #4229 = PseudoVLSEG2E64_V_M1 + {7, OperandInfo498}, // Inst #4230 = PseudoVLSEG2E64_V_M1_MASK + {4, OperandInfo499}, // Inst #4231 = PseudoVLSEG2E64_V_M2 + {7, OperandInfo500}, // Inst #4232 = PseudoVLSEG2E64_V_M2_MASK + {4, OperandInfo501}, // Inst #4233 = PseudoVLSEG2E64_V_M4 + {7, OperandInfo502}, // Inst #4234 = PseudoVLSEG2E64_V_M4_MASK + {4, OperandInfo497}, // Inst #4235 = PseudoVLSEG2E8FF_V_M1 + {7, OperandInfo498}, // Inst #4236 = PseudoVLSEG2E8FF_V_M1_MASK + {4, OperandInfo499}, // Inst #4237 = PseudoVLSEG2E8FF_V_M2 + {7, OperandInfo500}, // Inst #4238 = PseudoVLSEG2E8FF_V_M2_MASK + {4, OperandInfo501}, // Inst #4239 = PseudoVLSEG2E8FF_V_M4 + {7, OperandInfo502}, // Inst #4240 = PseudoVLSEG2E8FF_V_M4_MASK + {4, OperandInfo497}, // Inst #4241 = PseudoVLSEG2E8FF_V_MF2 + {7, OperandInfo498}, // Inst #4242 = PseudoVLSEG2E8FF_V_MF2_MASK + {4, OperandInfo497}, // Inst #4243 = PseudoVLSEG2E8FF_V_MF4 + {7, OperandInfo498}, // Inst #4244 = PseudoVLSEG2E8FF_V_MF4_MASK + {4, OperandInfo497}, // Inst #4245 = PseudoVLSEG2E8FF_V_MF8 + {7, OperandInfo498}, // Inst #4246 = PseudoVLSEG2E8FF_V_MF8_MASK + {4, OperandInfo497}, // Inst #4247 = PseudoVLSEG2E8_V_M1 + {7, OperandInfo498}, // Inst #4248 = PseudoVLSEG2E8_V_M1_MASK + {4, OperandInfo499}, // Inst #4249 = PseudoVLSEG2E8_V_M2 + {7, OperandInfo500}, // Inst #4250 = PseudoVLSEG2E8_V_M2_MASK + {4, OperandInfo501}, // Inst #4251 = PseudoVLSEG2E8_V_M4 + {7, OperandInfo502}, // Inst #4252 = PseudoVLSEG2E8_V_M4_MASK + {4, OperandInfo497}, // Inst #4253 = PseudoVLSEG2E8_V_MF2 + {7, OperandInfo498}, // Inst #4254 = PseudoVLSEG2E8_V_MF2_MASK + {4, OperandInfo497}, // Inst #4255 = PseudoVLSEG2E8_V_MF4 + {7, OperandInfo498}, // Inst #4256 = PseudoVLSEG2E8_V_MF4_MASK + {4, OperandInfo497}, // Inst #4257 = PseudoVLSEG2E8_V_MF8 + {7, OperandInfo498}, // Inst #4258 = PseudoVLSEG2E8_V_MF8_MASK + {4, OperandInfo503}, // Inst #4259 = PseudoVLSEG3E16FF_V_M1 + {7, OperandInfo504}, // Inst #4260 = PseudoVLSEG3E16FF_V_M1_MASK + {4, OperandInfo505}, // Inst #4261 = PseudoVLSEG3E16FF_V_M2 + {7, OperandInfo506}, // Inst #4262 = PseudoVLSEG3E16FF_V_M2_MASK + {4, OperandInfo503}, // Inst #4263 = PseudoVLSEG3E16FF_V_MF2 + {7, OperandInfo504}, // Inst #4264 = PseudoVLSEG3E16FF_V_MF2_MASK + {4, OperandInfo503}, // Inst #4265 = PseudoVLSEG3E16FF_V_MF4 + {7, OperandInfo504}, // Inst #4266 = PseudoVLSEG3E16FF_V_MF4_MASK + {4, OperandInfo503}, // Inst #4267 = PseudoVLSEG3E16_V_M1 + {7, OperandInfo504}, // Inst #4268 = PseudoVLSEG3E16_V_M1_MASK + {4, OperandInfo505}, // Inst #4269 = PseudoVLSEG3E16_V_M2 + {7, OperandInfo506}, // Inst #4270 = PseudoVLSEG3E16_V_M2_MASK + {4, OperandInfo503}, // Inst #4271 = PseudoVLSEG3E16_V_MF2 + {7, OperandInfo504}, // Inst #4272 = PseudoVLSEG3E16_V_MF2_MASK + {4, OperandInfo503}, // Inst #4273 = PseudoVLSEG3E16_V_MF4 + {7, OperandInfo504}, // Inst #4274 = PseudoVLSEG3E16_V_MF4_MASK + {4, OperandInfo503}, // Inst #4275 = PseudoVLSEG3E32FF_V_M1 + {7, OperandInfo504}, // Inst #4276 = PseudoVLSEG3E32FF_V_M1_MASK + {4, OperandInfo505}, // Inst #4277 = PseudoVLSEG3E32FF_V_M2 + {7, OperandInfo506}, // Inst #4278 = PseudoVLSEG3E32FF_V_M2_MASK + {4, OperandInfo503}, // Inst #4279 = PseudoVLSEG3E32FF_V_MF2 + {7, OperandInfo504}, // Inst #4280 = PseudoVLSEG3E32FF_V_MF2_MASK + {4, OperandInfo503}, // Inst #4281 = PseudoVLSEG3E32_V_M1 + {7, OperandInfo504}, // Inst #4282 = PseudoVLSEG3E32_V_M1_MASK + {4, OperandInfo505}, // Inst #4283 = PseudoVLSEG3E32_V_M2 + {7, OperandInfo506}, // Inst #4284 = PseudoVLSEG3E32_V_M2_MASK + {4, OperandInfo503}, // Inst #4285 = PseudoVLSEG3E32_V_MF2 + {7, OperandInfo504}, // Inst #4286 = PseudoVLSEG3E32_V_MF2_MASK + {4, OperandInfo503}, // Inst #4287 = PseudoVLSEG3E64FF_V_M1 + {7, OperandInfo504}, // Inst #4288 = PseudoVLSEG3E64FF_V_M1_MASK + {4, OperandInfo505}, // Inst #4289 = PseudoVLSEG3E64FF_V_M2 + {7, OperandInfo506}, // Inst #4290 = PseudoVLSEG3E64FF_V_M2_MASK + {4, OperandInfo503}, // Inst #4291 = PseudoVLSEG3E64_V_M1 + {7, OperandInfo504}, // Inst #4292 = PseudoVLSEG3E64_V_M1_MASK + {4, OperandInfo505}, // Inst #4293 = PseudoVLSEG3E64_V_M2 + {7, OperandInfo506}, // Inst #4294 = PseudoVLSEG3E64_V_M2_MASK + {4, OperandInfo503}, // Inst #4295 = PseudoVLSEG3E8FF_V_M1 + {7, OperandInfo504}, // Inst #4296 = PseudoVLSEG3E8FF_V_M1_MASK + {4, OperandInfo505}, // Inst #4297 = PseudoVLSEG3E8FF_V_M2 + {7, OperandInfo506}, // Inst #4298 = PseudoVLSEG3E8FF_V_M2_MASK + {4, OperandInfo503}, // Inst #4299 = PseudoVLSEG3E8FF_V_MF2 + {7, OperandInfo504}, // Inst #4300 = PseudoVLSEG3E8FF_V_MF2_MASK + {4, OperandInfo503}, // Inst #4301 = PseudoVLSEG3E8FF_V_MF4 + {7, OperandInfo504}, // Inst #4302 = PseudoVLSEG3E8FF_V_MF4_MASK + {4, OperandInfo503}, // Inst #4303 = PseudoVLSEG3E8FF_V_MF8 + {7, OperandInfo504}, // Inst #4304 = PseudoVLSEG3E8FF_V_MF8_MASK + {4, OperandInfo503}, // Inst #4305 = PseudoVLSEG3E8_V_M1 + {7, OperandInfo504}, // Inst #4306 = PseudoVLSEG3E8_V_M1_MASK + {4, OperandInfo505}, // Inst #4307 = PseudoVLSEG3E8_V_M2 + {7, OperandInfo506}, // Inst #4308 = PseudoVLSEG3E8_V_M2_MASK + {4, OperandInfo503}, // Inst #4309 = PseudoVLSEG3E8_V_MF2 + {7, OperandInfo504}, // Inst #4310 = PseudoVLSEG3E8_V_MF2_MASK + {4, OperandInfo503}, // Inst #4311 = PseudoVLSEG3E8_V_MF4 + {7, OperandInfo504}, // Inst #4312 = PseudoVLSEG3E8_V_MF4_MASK + {4, OperandInfo503}, // Inst #4313 = PseudoVLSEG3E8_V_MF8 + {7, OperandInfo504}, // Inst #4314 = PseudoVLSEG3E8_V_MF8_MASK + {4, OperandInfo507}, // Inst #4315 = PseudoVLSEG4E16FF_V_M1 + {7, OperandInfo508}, // Inst #4316 = PseudoVLSEG4E16FF_V_M1_MASK + {4, OperandInfo509}, // Inst #4317 = PseudoVLSEG4E16FF_V_M2 + {7, OperandInfo510}, // Inst #4318 = PseudoVLSEG4E16FF_V_M2_MASK + {4, OperandInfo507}, // Inst #4319 = PseudoVLSEG4E16FF_V_MF2 + {7, OperandInfo508}, // Inst #4320 = PseudoVLSEG4E16FF_V_MF2_MASK + {4, OperandInfo507}, // Inst #4321 = PseudoVLSEG4E16FF_V_MF4 + {7, OperandInfo508}, // Inst #4322 = PseudoVLSEG4E16FF_V_MF4_MASK + {4, OperandInfo507}, // Inst #4323 = PseudoVLSEG4E16_V_M1 + {7, OperandInfo508}, // Inst #4324 = PseudoVLSEG4E16_V_M1_MASK + {4, OperandInfo509}, // Inst #4325 = PseudoVLSEG4E16_V_M2 + {7, OperandInfo510}, // Inst #4326 = PseudoVLSEG4E16_V_M2_MASK + {4, OperandInfo507}, // Inst #4327 = PseudoVLSEG4E16_V_MF2 + {7, OperandInfo508}, // Inst #4328 = PseudoVLSEG4E16_V_MF2_MASK + {4, OperandInfo507}, // Inst #4329 = PseudoVLSEG4E16_V_MF4 + {7, OperandInfo508}, // Inst #4330 = PseudoVLSEG4E16_V_MF4_MASK + {4, OperandInfo507}, // Inst #4331 = PseudoVLSEG4E32FF_V_M1 + {7, OperandInfo508}, // Inst #4332 = PseudoVLSEG4E32FF_V_M1_MASK + {4, OperandInfo509}, // Inst #4333 = PseudoVLSEG4E32FF_V_M2 + {7, OperandInfo510}, // Inst #4334 = PseudoVLSEG4E32FF_V_M2_MASK + {4, OperandInfo507}, // Inst #4335 = PseudoVLSEG4E32FF_V_MF2 + {7, OperandInfo508}, // Inst #4336 = PseudoVLSEG4E32FF_V_MF2_MASK + {4, OperandInfo507}, // Inst #4337 = PseudoVLSEG4E32_V_M1 + {7, OperandInfo508}, // Inst #4338 = PseudoVLSEG4E32_V_M1_MASK + {4, OperandInfo509}, // Inst #4339 = PseudoVLSEG4E32_V_M2 + {7, OperandInfo510}, // Inst #4340 = PseudoVLSEG4E32_V_M2_MASK + {4, OperandInfo507}, // Inst #4341 = PseudoVLSEG4E32_V_MF2 + {7, OperandInfo508}, // Inst #4342 = PseudoVLSEG4E32_V_MF2_MASK + {4, OperandInfo507}, // Inst #4343 = PseudoVLSEG4E64FF_V_M1 + {7, OperandInfo508}, // Inst #4344 = PseudoVLSEG4E64FF_V_M1_MASK + {4, OperandInfo509}, // Inst #4345 = PseudoVLSEG4E64FF_V_M2 + {7, OperandInfo510}, // Inst #4346 = PseudoVLSEG4E64FF_V_M2_MASK + {4, OperandInfo507}, // Inst #4347 = PseudoVLSEG4E64_V_M1 + {7, OperandInfo508}, // Inst #4348 = PseudoVLSEG4E64_V_M1_MASK + {4, OperandInfo509}, // Inst #4349 = PseudoVLSEG4E64_V_M2 + {7, OperandInfo510}, // Inst #4350 = PseudoVLSEG4E64_V_M2_MASK + {4, OperandInfo507}, // Inst #4351 = PseudoVLSEG4E8FF_V_M1 + {7, OperandInfo508}, // Inst #4352 = PseudoVLSEG4E8FF_V_M1_MASK + {4, OperandInfo509}, // Inst #4353 = PseudoVLSEG4E8FF_V_M2 + {7, OperandInfo510}, // Inst #4354 = PseudoVLSEG4E8FF_V_M2_MASK + {4, OperandInfo507}, // Inst #4355 = PseudoVLSEG4E8FF_V_MF2 + {7, OperandInfo508}, // Inst #4356 = PseudoVLSEG4E8FF_V_MF2_MASK + {4, OperandInfo507}, // Inst #4357 = PseudoVLSEG4E8FF_V_MF4 + {7, OperandInfo508}, // Inst #4358 = PseudoVLSEG4E8FF_V_MF4_MASK + {4, OperandInfo507}, // Inst #4359 = PseudoVLSEG4E8FF_V_MF8 + {7, OperandInfo508}, // Inst #4360 = PseudoVLSEG4E8FF_V_MF8_MASK + {4, OperandInfo507}, // Inst #4361 = PseudoVLSEG4E8_V_M1 + {7, OperandInfo508}, // Inst #4362 = PseudoVLSEG4E8_V_M1_MASK + {4, OperandInfo509}, // Inst #4363 = PseudoVLSEG4E8_V_M2 + {7, OperandInfo510}, // Inst #4364 = PseudoVLSEG4E8_V_M2_MASK + {4, OperandInfo507}, // Inst #4365 = PseudoVLSEG4E8_V_MF2 + {7, OperandInfo508}, // Inst #4366 = PseudoVLSEG4E8_V_MF2_MASK + {4, OperandInfo507}, // Inst #4367 = PseudoVLSEG4E8_V_MF4 + {7, OperandInfo508}, // Inst #4368 = PseudoVLSEG4E8_V_MF4_MASK + {4, OperandInfo507}, // Inst #4369 = PseudoVLSEG4E8_V_MF8 + {7, OperandInfo508}, // Inst #4370 = PseudoVLSEG4E8_V_MF8_MASK + {4, OperandInfo511}, // Inst #4371 = PseudoVLSEG5E16FF_V_M1 + {7, OperandInfo512}, // Inst #4372 = PseudoVLSEG5E16FF_V_M1_MASK + {4, OperandInfo511}, // Inst #4373 = PseudoVLSEG5E16FF_V_MF2 + {7, OperandInfo512}, // Inst #4374 = PseudoVLSEG5E16FF_V_MF2_MASK + {4, OperandInfo511}, // Inst #4375 = PseudoVLSEG5E16FF_V_MF4 + {7, OperandInfo512}, // Inst #4376 = PseudoVLSEG5E16FF_V_MF4_MASK + {4, OperandInfo511}, // Inst #4377 = PseudoVLSEG5E16_V_M1 + {7, OperandInfo512}, // Inst #4378 = PseudoVLSEG5E16_V_M1_MASK + {4, OperandInfo511}, // Inst #4379 = PseudoVLSEG5E16_V_MF2 + {7, OperandInfo512}, // Inst #4380 = PseudoVLSEG5E16_V_MF2_MASK + {4, OperandInfo511}, // Inst #4381 = PseudoVLSEG5E16_V_MF4 + {7, OperandInfo512}, // Inst #4382 = PseudoVLSEG5E16_V_MF4_MASK + {4, OperandInfo511}, // Inst #4383 = PseudoVLSEG5E32FF_V_M1 + {7, OperandInfo512}, // Inst #4384 = PseudoVLSEG5E32FF_V_M1_MASK + {4, OperandInfo511}, // Inst #4385 = PseudoVLSEG5E32FF_V_MF2 + {7, OperandInfo512}, // Inst #4386 = PseudoVLSEG5E32FF_V_MF2_MASK + {4, OperandInfo511}, // Inst #4387 = PseudoVLSEG5E32_V_M1 + {7, OperandInfo512}, // Inst #4388 = PseudoVLSEG5E32_V_M1_MASK + {4, OperandInfo511}, // Inst #4389 = PseudoVLSEG5E32_V_MF2 + {7, OperandInfo512}, // Inst #4390 = PseudoVLSEG5E32_V_MF2_MASK + {4, OperandInfo511}, // Inst #4391 = PseudoVLSEG5E64FF_V_M1 + {7, OperandInfo512}, // Inst #4392 = PseudoVLSEG5E64FF_V_M1_MASK + {4, OperandInfo511}, // Inst #4393 = PseudoVLSEG5E64_V_M1 + {7, OperandInfo512}, // Inst #4394 = PseudoVLSEG5E64_V_M1_MASK + {4, OperandInfo511}, // Inst #4395 = PseudoVLSEG5E8FF_V_M1 + {7, OperandInfo512}, // Inst #4396 = PseudoVLSEG5E8FF_V_M1_MASK + {4, OperandInfo511}, // Inst #4397 = PseudoVLSEG5E8FF_V_MF2 + {7, OperandInfo512}, // Inst #4398 = PseudoVLSEG5E8FF_V_MF2_MASK + {4, OperandInfo511}, // Inst #4399 = PseudoVLSEG5E8FF_V_MF4 + {7, OperandInfo512}, // Inst #4400 = PseudoVLSEG5E8FF_V_MF4_MASK + {4, OperandInfo511}, // Inst #4401 = PseudoVLSEG5E8FF_V_MF8 + {7, OperandInfo512}, // Inst #4402 = PseudoVLSEG5E8FF_V_MF8_MASK + {4, OperandInfo511}, // Inst #4403 = PseudoVLSEG5E8_V_M1 + {7, OperandInfo512}, // Inst #4404 = PseudoVLSEG5E8_V_M1_MASK + {4, OperandInfo511}, // Inst #4405 = PseudoVLSEG5E8_V_MF2 + {7, OperandInfo512}, // Inst #4406 = PseudoVLSEG5E8_V_MF2_MASK + {4, OperandInfo511}, // Inst #4407 = PseudoVLSEG5E8_V_MF4 + {7, OperandInfo512}, // Inst #4408 = PseudoVLSEG5E8_V_MF4_MASK + {4, OperandInfo511}, // Inst #4409 = PseudoVLSEG5E8_V_MF8 + {7, OperandInfo512}, // Inst #4410 = PseudoVLSEG5E8_V_MF8_MASK + {4, OperandInfo513}, // Inst #4411 = PseudoVLSEG6E16FF_V_M1 + {7, OperandInfo514}, // Inst #4412 = PseudoVLSEG6E16FF_V_M1_MASK + {4, OperandInfo513}, // Inst #4413 = PseudoVLSEG6E16FF_V_MF2 + {7, OperandInfo514}, // Inst #4414 = PseudoVLSEG6E16FF_V_MF2_MASK + {4, OperandInfo513}, // Inst #4415 = PseudoVLSEG6E16FF_V_MF4 + {7, OperandInfo514}, // Inst #4416 = PseudoVLSEG6E16FF_V_MF4_MASK + {4, OperandInfo513}, // Inst #4417 = PseudoVLSEG6E16_V_M1 + {7, OperandInfo514}, // Inst #4418 = PseudoVLSEG6E16_V_M1_MASK + {4, OperandInfo513}, // Inst #4419 = PseudoVLSEG6E16_V_MF2 + {7, OperandInfo514}, // Inst #4420 = PseudoVLSEG6E16_V_MF2_MASK + {4, OperandInfo513}, // Inst #4421 = PseudoVLSEG6E16_V_MF4 + {7, OperandInfo514}, // Inst #4422 = PseudoVLSEG6E16_V_MF4_MASK + {4, OperandInfo513}, // Inst #4423 = PseudoVLSEG6E32FF_V_M1 + {7, OperandInfo514}, // Inst #4424 = PseudoVLSEG6E32FF_V_M1_MASK + {4, OperandInfo513}, // Inst #4425 = PseudoVLSEG6E32FF_V_MF2 + {7, OperandInfo514}, // Inst #4426 = PseudoVLSEG6E32FF_V_MF2_MASK + {4, OperandInfo513}, // Inst #4427 = PseudoVLSEG6E32_V_M1 + {7, OperandInfo514}, // Inst #4428 = PseudoVLSEG6E32_V_M1_MASK + {4, OperandInfo513}, // Inst #4429 = PseudoVLSEG6E32_V_MF2 + {7, OperandInfo514}, // Inst #4430 = PseudoVLSEG6E32_V_MF2_MASK + {4, OperandInfo513}, // Inst #4431 = PseudoVLSEG6E64FF_V_M1 + {7, OperandInfo514}, // Inst #4432 = PseudoVLSEG6E64FF_V_M1_MASK + {4, OperandInfo513}, // Inst #4433 = PseudoVLSEG6E64_V_M1 + {7, OperandInfo514}, // Inst #4434 = PseudoVLSEG6E64_V_M1_MASK + {4, OperandInfo513}, // Inst #4435 = PseudoVLSEG6E8FF_V_M1 + {7, OperandInfo514}, // Inst #4436 = PseudoVLSEG6E8FF_V_M1_MASK + {4, OperandInfo513}, // Inst #4437 = PseudoVLSEG6E8FF_V_MF2 + {7, OperandInfo514}, // Inst #4438 = PseudoVLSEG6E8FF_V_MF2_MASK + {4, OperandInfo513}, // Inst #4439 = PseudoVLSEG6E8FF_V_MF4 + {7, OperandInfo514}, // Inst #4440 = PseudoVLSEG6E8FF_V_MF4_MASK + {4, OperandInfo513}, // Inst #4441 = PseudoVLSEG6E8FF_V_MF8 + {7, OperandInfo514}, // Inst #4442 = PseudoVLSEG6E8FF_V_MF8_MASK + {4, OperandInfo513}, // Inst #4443 = PseudoVLSEG6E8_V_M1 + {7, OperandInfo514}, // Inst #4444 = PseudoVLSEG6E8_V_M1_MASK + {4, OperandInfo513}, // Inst #4445 = PseudoVLSEG6E8_V_MF2 + {7, OperandInfo514}, // Inst #4446 = PseudoVLSEG6E8_V_MF2_MASK + {4, OperandInfo513}, // Inst #4447 = PseudoVLSEG6E8_V_MF4 + {7, OperandInfo514}, // Inst #4448 = PseudoVLSEG6E8_V_MF4_MASK + {4, OperandInfo513}, // Inst #4449 = PseudoVLSEG6E8_V_MF8 + {7, OperandInfo514}, // Inst #4450 = PseudoVLSEG6E8_V_MF8_MASK + {4, OperandInfo515}, // Inst #4451 = PseudoVLSEG7E16FF_V_M1 + {7, OperandInfo516}, // Inst #4452 = PseudoVLSEG7E16FF_V_M1_MASK + {4, OperandInfo515}, // Inst #4453 = PseudoVLSEG7E16FF_V_MF2 + {7, OperandInfo516}, // Inst #4454 = PseudoVLSEG7E16FF_V_MF2_MASK + {4, OperandInfo515}, // Inst #4455 = PseudoVLSEG7E16FF_V_MF4 + {7, OperandInfo516}, // Inst #4456 = PseudoVLSEG7E16FF_V_MF4_MASK + {4, OperandInfo515}, // Inst #4457 = PseudoVLSEG7E16_V_M1 + {7, OperandInfo516}, // Inst #4458 = PseudoVLSEG7E16_V_M1_MASK + {4, OperandInfo515}, // Inst #4459 = PseudoVLSEG7E16_V_MF2 + {7, OperandInfo516}, // Inst #4460 = PseudoVLSEG7E16_V_MF2_MASK + {4, OperandInfo515}, // Inst #4461 = PseudoVLSEG7E16_V_MF4 + {7, OperandInfo516}, // Inst #4462 = PseudoVLSEG7E16_V_MF4_MASK + {4, OperandInfo515}, // Inst #4463 = PseudoVLSEG7E32FF_V_M1 + {7, OperandInfo516}, // Inst #4464 = PseudoVLSEG7E32FF_V_M1_MASK + {4, OperandInfo515}, // Inst #4465 = PseudoVLSEG7E32FF_V_MF2 + {7, OperandInfo516}, // Inst #4466 = PseudoVLSEG7E32FF_V_MF2_MASK + {4, OperandInfo515}, // Inst #4467 = PseudoVLSEG7E32_V_M1 + {7, OperandInfo516}, // Inst #4468 = PseudoVLSEG7E32_V_M1_MASK + {4, OperandInfo515}, // Inst #4469 = PseudoVLSEG7E32_V_MF2 + {7, OperandInfo516}, // Inst #4470 = PseudoVLSEG7E32_V_MF2_MASK + {4, OperandInfo515}, // Inst #4471 = PseudoVLSEG7E64FF_V_M1 + {7, OperandInfo516}, // Inst #4472 = PseudoVLSEG7E64FF_V_M1_MASK + {4, OperandInfo515}, // Inst #4473 = PseudoVLSEG7E64_V_M1 + {7, OperandInfo516}, // Inst #4474 = PseudoVLSEG7E64_V_M1_MASK + {4, OperandInfo515}, // Inst #4475 = PseudoVLSEG7E8FF_V_M1 + {7, OperandInfo516}, // Inst #4476 = PseudoVLSEG7E8FF_V_M1_MASK + {4, OperandInfo515}, // Inst #4477 = PseudoVLSEG7E8FF_V_MF2 + {7, OperandInfo516}, // Inst #4478 = PseudoVLSEG7E8FF_V_MF2_MASK + {4, OperandInfo515}, // Inst #4479 = PseudoVLSEG7E8FF_V_MF4 + {7, OperandInfo516}, // Inst #4480 = PseudoVLSEG7E8FF_V_MF4_MASK + {4, OperandInfo515}, // Inst #4481 = PseudoVLSEG7E8FF_V_MF8 + {7, OperandInfo516}, // Inst #4482 = PseudoVLSEG7E8FF_V_MF8_MASK + {4, OperandInfo515}, // Inst #4483 = PseudoVLSEG7E8_V_M1 + {7, OperandInfo516}, // Inst #4484 = PseudoVLSEG7E8_V_M1_MASK + {4, OperandInfo515}, // Inst #4485 = PseudoVLSEG7E8_V_MF2 + {7, OperandInfo516}, // Inst #4486 = PseudoVLSEG7E8_V_MF2_MASK + {4, OperandInfo515}, // Inst #4487 = PseudoVLSEG7E8_V_MF4 + {7, OperandInfo516}, // Inst #4488 = PseudoVLSEG7E8_V_MF4_MASK + {4, OperandInfo515}, // Inst #4489 = PseudoVLSEG7E8_V_MF8 + {7, OperandInfo516}, // Inst #4490 = PseudoVLSEG7E8_V_MF8_MASK + {4, OperandInfo517}, // Inst #4491 = PseudoVLSEG8E16FF_V_M1 + {7, OperandInfo518}, // Inst #4492 = PseudoVLSEG8E16FF_V_M1_MASK + {4, OperandInfo517}, // Inst #4493 = PseudoVLSEG8E16FF_V_MF2 + {7, OperandInfo518}, // Inst #4494 = PseudoVLSEG8E16FF_V_MF2_MASK + {4, OperandInfo517}, // Inst #4495 = PseudoVLSEG8E16FF_V_MF4 + {7, OperandInfo518}, // Inst #4496 = PseudoVLSEG8E16FF_V_MF4_MASK + {4, OperandInfo517}, // Inst #4497 = PseudoVLSEG8E16_V_M1 + {7, OperandInfo518}, // Inst #4498 = PseudoVLSEG8E16_V_M1_MASK + {4, OperandInfo517}, // Inst #4499 = PseudoVLSEG8E16_V_MF2 + {7, OperandInfo518}, // Inst #4500 = PseudoVLSEG8E16_V_MF2_MASK + {4, OperandInfo517}, // Inst #4501 = PseudoVLSEG8E16_V_MF4 + {7, OperandInfo518}, // Inst #4502 = PseudoVLSEG8E16_V_MF4_MASK + {4, OperandInfo517}, // Inst #4503 = PseudoVLSEG8E32FF_V_M1 + {7, OperandInfo518}, // Inst #4504 = PseudoVLSEG8E32FF_V_M1_MASK + {4, OperandInfo517}, // Inst #4505 = PseudoVLSEG8E32FF_V_MF2 + {7, OperandInfo518}, // Inst #4506 = PseudoVLSEG8E32FF_V_MF2_MASK + {4, OperandInfo517}, // Inst #4507 = PseudoVLSEG8E32_V_M1 + {7, OperandInfo518}, // Inst #4508 = PseudoVLSEG8E32_V_M1_MASK + {4, OperandInfo517}, // Inst #4509 = PseudoVLSEG8E32_V_MF2 + {7, OperandInfo518}, // Inst #4510 = PseudoVLSEG8E32_V_MF2_MASK + {4, OperandInfo517}, // Inst #4511 = PseudoVLSEG8E64FF_V_M1 + {7, OperandInfo518}, // Inst #4512 = PseudoVLSEG8E64FF_V_M1_MASK + {4, OperandInfo517}, // Inst #4513 = PseudoVLSEG8E64_V_M1 + {7, OperandInfo518}, // Inst #4514 = PseudoVLSEG8E64_V_M1_MASK + {4, OperandInfo517}, // Inst #4515 = PseudoVLSEG8E8FF_V_M1 + {7, OperandInfo518}, // Inst #4516 = PseudoVLSEG8E8FF_V_M1_MASK + {4, OperandInfo517}, // Inst #4517 = PseudoVLSEG8E8FF_V_MF2 + {7, OperandInfo518}, // Inst #4518 = PseudoVLSEG8E8FF_V_MF2_MASK + {4, OperandInfo517}, // Inst #4519 = PseudoVLSEG8E8FF_V_MF4 + {7, OperandInfo518}, // Inst #4520 = PseudoVLSEG8E8FF_V_MF4_MASK + {4, OperandInfo517}, // Inst #4521 = PseudoVLSEG8E8FF_V_MF8 + {7, OperandInfo518}, // Inst #4522 = PseudoVLSEG8E8FF_V_MF8_MASK + {4, OperandInfo517}, // Inst #4523 = PseudoVLSEG8E8_V_M1 + {7, OperandInfo518}, // Inst #4524 = PseudoVLSEG8E8_V_M1_MASK + {4, OperandInfo517}, // Inst #4525 = PseudoVLSEG8E8_V_MF2 + {7, OperandInfo518}, // Inst #4526 = PseudoVLSEG8E8_V_MF2_MASK + {4, OperandInfo517}, // Inst #4527 = PseudoVLSEG8E8_V_MF4 + {7, OperandInfo518}, // Inst #4528 = PseudoVLSEG8E8_V_MF4_MASK + {4, OperandInfo517}, // Inst #4529 = PseudoVLSEG8E8_V_MF8 + {7, OperandInfo518}, // Inst #4530 = PseudoVLSEG8E8_V_MF8_MASK + {5, OperandInfo519}, // Inst #4531 = PseudoVLSSEG2E16_V_M1 + {8, OperandInfo520}, // Inst #4532 = PseudoVLSSEG2E16_V_M1_MASK + {5, OperandInfo521}, // Inst #4533 = PseudoVLSSEG2E16_V_M2 + {8, OperandInfo522}, // Inst #4534 = PseudoVLSSEG2E16_V_M2_MASK + {5, OperandInfo523}, // Inst #4535 = PseudoVLSSEG2E16_V_M4 + {8, OperandInfo524}, // Inst #4536 = PseudoVLSSEG2E16_V_M4_MASK + {5, OperandInfo519}, // Inst #4537 = PseudoVLSSEG2E16_V_MF2 + {8, OperandInfo520}, // Inst #4538 = PseudoVLSSEG2E16_V_MF2_MASK + {5, OperandInfo519}, // Inst #4539 = PseudoVLSSEG2E16_V_MF4 + {8, OperandInfo520}, // Inst #4540 = PseudoVLSSEG2E16_V_MF4_MASK + {5, OperandInfo519}, // Inst #4541 = PseudoVLSSEG2E32_V_M1 + {8, OperandInfo520}, // Inst #4542 = PseudoVLSSEG2E32_V_M1_MASK + {5, OperandInfo521}, // Inst #4543 = PseudoVLSSEG2E32_V_M2 + {8, OperandInfo522}, // Inst #4544 = PseudoVLSSEG2E32_V_M2_MASK + {5, OperandInfo523}, // Inst #4545 = PseudoVLSSEG2E32_V_M4 + {8, OperandInfo524}, // Inst #4546 = PseudoVLSSEG2E32_V_M4_MASK + {5, OperandInfo519}, // Inst #4547 = PseudoVLSSEG2E32_V_MF2 + {8, OperandInfo520}, // Inst #4548 = PseudoVLSSEG2E32_V_MF2_MASK + {5, OperandInfo519}, // Inst #4549 = PseudoVLSSEG2E64_V_M1 + {8, OperandInfo520}, // Inst #4550 = PseudoVLSSEG2E64_V_M1_MASK + {5, OperandInfo521}, // Inst #4551 = PseudoVLSSEG2E64_V_M2 + {8, OperandInfo522}, // Inst #4552 = PseudoVLSSEG2E64_V_M2_MASK + {5, OperandInfo523}, // Inst #4553 = PseudoVLSSEG2E64_V_M4 + {8, OperandInfo524}, // Inst #4554 = PseudoVLSSEG2E64_V_M4_MASK + {5, OperandInfo519}, // Inst #4555 = PseudoVLSSEG2E8_V_M1 + {8, OperandInfo520}, // Inst #4556 = PseudoVLSSEG2E8_V_M1_MASK + {5, OperandInfo521}, // Inst #4557 = PseudoVLSSEG2E8_V_M2 + {8, OperandInfo522}, // Inst #4558 = PseudoVLSSEG2E8_V_M2_MASK + {5, OperandInfo523}, // Inst #4559 = PseudoVLSSEG2E8_V_M4 + {8, OperandInfo524}, // Inst #4560 = PseudoVLSSEG2E8_V_M4_MASK + {5, OperandInfo519}, // Inst #4561 = PseudoVLSSEG2E8_V_MF2 + {8, OperandInfo520}, // Inst #4562 = PseudoVLSSEG2E8_V_MF2_MASK + {5, OperandInfo519}, // Inst #4563 = PseudoVLSSEG2E8_V_MF4 + {8, OperandInfo520}, // Inst #4564 = PseudoVLSSEG2E8_V_MF4_MASK + {5, OperandInfo519}, // Inst #4565 = PseudoVLSSEG2E8_V_MF8 + {8, OperandInfo520}, // Inst #4566 = PseudoVLSSEG2E8_V_MF8_MASK + {5, OperandInfo525}, // Inst #4567 = PseudoVLSSEG3E16_V_M1 + {8, OperandInfo526}, // Inst #4568 = PseudoVLSSEG3E16_V_M1_MASK + {5, OperandInfo527}, // Inst #4569 = PseudoVLSSEG3E16_V_M2 + {8, OperandInfo528}, // Inst #4570 = PseudoVLSSEG3E16_V_M2_MASK + {5, OperandInfo525}, // Inst #4571 = PseudoVLSSEG3E16_V_MF2 + {8, OperandInfo526}, // Inst #4572 = PseudoVLSSEG3E16_V_MF2_MASK + {5, OperandInfo525}, // Inst #4573 = PseudoVLSSEG3E16_V_MF4 + {8, OperandInfo526}, // Inst #4574 = PseudoVLSSEG3E16_V_MF4_MASK + {5, OperandInfo525}, // Inst #4575 = PseudoVLSSEG3E32_V_M1 + {8, OperandInfo526}, // Inst #4576 = PseudoVLSSEG3E32_V_M1_MASK + {5, OperandInfo527}, // Inst #4577 = PseudoVLSSEG3E32_V_M2 + {8, OperandInfo528}, // Inst #4578 = PseudoVLSSEG3E32_V_M2_MASK + {5, OperandInfo525}, // Inst #4579 = PseudoVLSSEG3E32_V_MF2 + {8, OperandInfo526}, // Inst #4580 = PseudoVLSSEG3E32_V_MF2_MASK + {5, OperandInfo525}, // Inst #4581 = PseudoVLSSEG3E64_V_M1 + {8, OperandInfo526}, // Inst #4582 = PseudoVLSSEG3E64_V_M1_MASK + {5, OperandInfo527}, // Inst #4583 = PseudoVLSSEG3E64_V_M2 + {8, OperandInfo528}, // Inst #4584 = PseudoVLSSEG3E64_V_M2_MASK + {5, OperandInfo525}, // Inst #4585 = PseudoVLSSEG3E8_V_M1 + {8, OperandInfo526}, // Inst #4586 = PseudoVLSSEG3E8_V_M1_MASK + {5, OperandInfo527}, // Inst #4587 = PseudoVLSSEG3E8_V_M2 + {8, OperandInfo528}, // Inst #4588 = PseudoVLSSEG3E8_V_M2_MASK + {5, OperandInfo525}, // Inst #4589 = PseudoVLSSEG3E8_V_MF2 + {8, OperandInfo526}, // Inst #4590 = PseudoVLSSEG3E8_V_MF2_MASK + {5, OperandInfo525}, // Inst #4591 = PseudoVLSSEG3E8_V_MF4 + {8, OperandInfo526}, // Inst #4592 = PseudoVLSSEG3E8_V_MF4_MASK + {5, OperandInfo525}, // Inst #4593 = PseudoVLSSEG3E8_V_MF8 + {8, OperandInfo526}, // Inst #4594 = PseudoVLSSEG3E8_V_MF8_MASK + {5, OperandInfo529}, // Inst #4595 = PseudoVLSSEG4E16_V_M1 + {8, OperandInfo530}, // Inst #4596 = PseudoVLSSEG4E16_V_M1_MASK + {5, OperandInfo531}, // Inst #4597 = PseudoVLSSEG4E16_V_M2 + {8, OperandInfo532}, // Inst #4598 = PseudoVLSSEG4E16_V_M2_MASK + {5, OperandInfo529}, // Inst #4599 = PseudoVLSSEG4E16_V_MF2 + {8, OperandInfo530}, // Inst #4600 = PseudoVLSSEG4E16_V_MF2_MASK + {5, OperandInfo529}, // Inst #4601 = PseudoVLSSEG4E16_V_MF4 + {8, OperandInfo530}, // Inst #4602 = PseudoVLSSEG4E16_V_MF4_MASK + {5, OperandInfo529}, // Inst #4603 = PseudoVLSSEG4E32_V_M1 + {8, OperandInfo530}, // Inst #4604 = PseudoVLSSEG4E32_V_M1_MASK + {5, OperandInfo531}, // Inst #4605 = PseudoVLSSEG4E32_V_M2 + {8, OperandInfo532}, // Inst #4606 = PseudoVLSSEG4E32_V_M2_MASK + {5, OperandInfo529}, // Inst #4607 = PseudoVLSSEG4E32_V_MF2 + {8, OperandInfo530}, // Inst #4608 = PseudoVLSSEG4E32_V_MF2_MASK + {5, OperandInfo529}, // Inst #4609 = PseudoVLSSEG4E64_V_M1 + {8, OperandInfo530}, // Inst #4610 = PseudoVLSSEG4E64_V_M1_MASK + {5, OperandInfo531}, // Inst #4611 = PseudoVLSSEG4E64_V_M2 + {8, OperandInfo532}, // Inst #4612 = PseudoVLSSEG4E64_V_M2_MASK + {5, OperandInfo529}, // Inst #4613 = PseudoVLSSEG4E8_V_M1 + {8, OperandInfo530}, // Inst #4614 = PseudoVLSSEG4E8_V_M1_MASK + {5, OperandInfo531}, // Inst #4615 = PseudoVLSSEG4E8_V_M2 + {8, OperandInfo532}, // Inst #4616 = PseudoVLSSEG4E8_V_M2_MASK + {5, OperandInfo529}, // Inst #4617 = PseudoVLSSEG4E8_V_MF2 + {8, OperandInfo530}, // Inst #4618 = PseudoVLSSEG4E8_V_MF2_MASK + {5, OperandInfo529}, // Inst #4619 = PseudoVLSSEG4E8_V_MF4 + {8, OperandInfo530}, // Inst #4620 = PseudoVLSSEG4E8_V_MF4_MASK + {5, OperandInfo529}, // Inst #4621 = PseudoVLSSEG4E8_V_MF8 + {8, OperandInfo530}, // Inst #4622 = PseudoVLSSEG4E8_V_MF8_MASK + {5, OperandInfo533}, // Inst #4623 = PseudoVLSSEG5E16_V_M1 + {8, OperandInfo534}, // Inst #4624 = PseudoVLSSEG5E16_V_M1_MASK + {5, OperandInfo533}, // Inst #4625 = PseudoVLSSEG5E16_V_MF2 + {8, OperandInfo534}, // Inst #4626 = PseudoVLSSEG5E16_V_MF2_MASK + {5, OperandInfo533}, // Inst #4627 = PseudoVLSSEG5E16_V_MF4 + {8, OperandInfo534}, // Inst #4628 = PseudoVLSSEG5E16_V_MF4_MASK + {5, OperandInfo533}, // Inst #4629 = PseudoVLSSEG5E32_V_M1 + {8, OperandInfo534}, // Inst #4630 = PseudoVLSSEG5E32_V_M1_MASK + {5, OperandInfo533}, // Inst #4631 = PseudoVLSSEG5E32_V_MF2 + {8, OperandInfo534}, // Inst #4632 = PseudoVLSSEG5E32_V_MF2_MASK + {5, OperandInfo533}, // Inst #4633 = PseudoVLSSEG5E64_V_M1 + {8, OperandInfo534}, // Inst #4634 = PseudoVLSSEG5E64_V_M1_MASK + {5, OperandInfo533}, // Inst #4635 = PseudoVLSSEG5E8_V_M1 + {8, OperandInfo534}, // Inst #4636 = PseudoVLSSEG5E8_V_M1_MASK + {5, OperandInfo533}, // Inst #4637 = PseudoVLSSEG5E8_V_MF2 + {8, OperandInfo534}, // Inst #4638 = PseudoVLSSEG5E8_V_MF2_MASK + {5, OperandInfo533}, // Inst #4639 = PseudoVLSSEG5E8_V_MF4 + {8, OperandInfo534}, // Inst #4640 = PseudoVLSSEG5E8_V_MF4_MASK + {5, OperandInfo533}, // Inst #4641 = PseudoVLSSEG5E8_V_MF8 + {8, OperandInfo534}, // Inst #4642 = PseudoVLSSEG5E8_V_MF8_MASK + {5, OperandInfo535}, // Inst #4643 = PseudoVLSSEG6E16_V_M1 + {8, OperandInfo536}, // Inst #4644 = PseudoVLSSEG6E16_V_M1_MASK + {5, OperandInfo535}, // Inst #4645 = PseudoVLSSEG6E16_V_MF2 + {8, OperandInfo536}, // Inst #4646 = PseudoVLSSEG6E16_V_MF2_MASK + {5, OperandInfo535}, // Inst #4647 = PseudoVLSSEG6E16_V_MF4 + {8, OperandInfo536}, // Inst #4648 = PseudoVLSSEG6E16_V_MF4_MASK + {5, OperandInfo535}, // Inst #4649 = PseudoVLSSEG6E32_V_M1 + {8, OperandInfo536}, // Inst #4650 = PseudoVLSSEG6E32_V_M1_MASK + {5, OperandInfo535}, // Inst #4651 = PseudoVLSSEG6E32_V_MF2 + {8, OperandInfo536}, // Inst #4652 = PseudoVLSSEG6E32_V_MF2_MASK + {5, OperandInfo535}, // Inst #4653 = PseudoVLSSEG6E64_V_M1 + {8, OperandInfo536}, // Inst #4654 = PseudoVLSSEG6E64_V_M1_MASK + {5, OperandInfo535}, // Inst #4655 = PseudoVLSSEG6E8_V_M1 + {8, OperandInfo536}, // Inst #4656 = PseudoVLSSEG6E8_V_M1_MASK + {5, OperandInfo535}, // Inst #4657 = PseudoVLSSEG6E8_V_MF2 + {8, OperandInfo536}, // Inst #4658 = PseudoVLSSEG6E8_V_MF2_MASK + {5, OperandInfo535}, // Inst #4659 = PseudoVLSSEG6E8_V_MF4 + {8, OperandInfo536}, // Inst #4660 = PseudoVLSSEG6E8_V_MF4_MASK + {5, OperandInfo535}, // Inst #4661 = PseudoVLSSEG6E8_V_MF8 + {8, OperandInfo536}, // Inst #4662 = PseudoVLSSEG6E8_V_MF8_MASK + {5, OperandInfo537}, // Inst #4663 = PseudoVLSSEG7E16_V_M1 + {8, OperandInfo538}, // Inst #4664 = PseudoVLSSEG7E16_V_M1_MASK + {5, OperandInfo537}, // Inst #4665 = PseudoVLSSEG7E16_V_MF2 + {8, OperandInfo538}, // Inst #4666 = PseudoVLSSEG7E16_V_MF2_MASK + {5, OperandInfo537}, // Inst #4667 = PseudoVLSSEG7E16_V_MF4 + {8, OperandInfo538}, // Inst #4668 = PseudoVLSSEG7E16_V_MF4_MASK + {5, OperandInfo537}, // Inst #4669 = PseudoVLSSEG7E32_V_M1 + {8, OperandInfo538}, // Inst #4670 = PseudoVLSSEG7E32_V_M1_MASK + {5, OperandInfo537}, // Inst #4671 = PseudoVLSSEG7E32_V_MF2 + {8, OperandInfo538}, // Inst #4672 = PseudoVLSSEG7E32_V_MF2_MASK + {5, OperandInfo537}, // Inst #4673 = PseudoVLSSEG7E64_V_M1 + {8, OperandInfo538}, // Inst #4674 = PseudoVLSSEG7E64_V_M1_MASK + {5, OperandInfo537}, // Inst #4675 = PseudoVLSSEG7E8_V_M1 + {8, OperandInfo538}, // Inst #4676 = PseudoVLSSEG7E8_V_M1_MASK + {5, OperandInfo537}, // Inst #4677 = PseudoVLSSEG7E8_V_MF2 + {8, OperandInfo538}, // Inst #4678 = PseudoVLSSEG7E8_V_MF2_MASK + {5, OperandInfo537}, // Inst #4679 = PseudoVLSSEG7E8_V_MF4 + {8, OperandInfo538}, // Inst #4680 = PseudoVLSSEG7E8_V_MF4_MASK + {5, OperandInfo537}, // Inst #4681 = PseudoVLSSEG7E8_V_MF8 + {8, OperandInfo538}, // Inst #4682 = PseudoVLSSEG7E8_V_MF8_MASK + {5, OperandInfo539}, // Inst #4683 = PseudoVLSSEG8E16_V_M1 + {8, OperandInfo540}, // Inst #4684 = PseudoVLSSEG8E16_V_M1_MASK + {5, OperandInfo539}, // Inst #4685 = PseudoVLSSEG8E16_V_MF2 + {8, OperandInfo540}, // Inst #4686 = PseudoVLSSEG8E16_V_MF2_MASK + {5, OperandInfo539}, // Inst #4687 = PseudoVLSSEG8E16_V_MF4 + {8, OperandInfo540}, // Inst #4688 = PseudoVLSSEG8E16_V_MF4_MASK + {5, OperandInfo539}, // Inst #4689 = PseudoVLSSEG8E32_V_M1 + {8, OperandInfo540}, // Inst #4690 = PseudoVLSSEG8E32_V_M1_MASK + {5, OperandInfo539}, // Inst #4691 = PseudoVLSSEG8E32_V_MF2 + {8, OperandInfo540}, // Inst #4692 = PseudoVLSSEG8E32_V_MF2_MASK + {5, OperandInfo539}, // Inst #4693 = PseudoVLSSEG8E64_V_M1 + {8, OperandInfo540}, // Inst #4694 = PseudoVLSSEG8E64_V_M1_MASK + {5, OperandInfo539}, // Inst #4695 = PseudoVLSSEG8E8_V_M1 + {8, OperandInfo540}, // Inst #4696 = PseudoVLSSEG8E8_V_M1_MASK + {5, OperandInfo539}, // Inst #4697 = PseudoVLSSEG8E8_V_MF2 + {8, OperandInfo540}, // Inst #4698 = PseudoVLSSEG8E8_V_MF2_MASK + {5, OperandInfo539}, // Inst #4699 = PseudoVLSSEG8E8_V_MF4 + {8, OperandInfo540}, // Inst #4700 = PseudoVLSSEG8E8_V_MF4_MASK + {5, OperandInfo539}, // Inst #4701 = PseudoVLSSEG8E8_V_MF8 + {8, OperandInfo540}, // Inst #4702 = PseudoVLSSEG8E8_V_MF8_MASK + {5, OperandInfo367}, // Inst #4703 = PseudoVLUXEI16_V_M1_M1 + {8, OperandInfo368}, // Inst #4704 = PseudoVLUXEI16_V_M1_M1_MASK + {5, OperandInfo369}, // Inst #4705 = PseudoVLUXEI16_V_M1_M2 + {8, OperandInfo370}, // Inst #4706 = PseudoVLUXEI16_V_M1_M2_MASK + {5, OperandInfo371}, // Inst #4707 = PseudoVLUXEI16_V_M1_M4 + {8, OperandInfo372}, // Inst #4708 = PseudoVLUXEI16_V_M1_M4_MASK + {5, OperandInfo373}, // Inst #4709 = PseudoVLUXEI16_V_M1_MF2 + {8, OperandInfo374}, // Inst #4710 = PseudoVLUXEI16_V_M1_MF2_MASK + {5, OperandInfo375}, // Inst #4711 = PseudoVLUXEI16_V_M2_M1 + {8, OperandInfo376}, // Inst #4712 = PseudoVLUXEI16_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #4713 = PseudoVLUXEI16_V_M2_M2 + {8, OperandInfo378}, // Inst #4714 = PseudoVLUXEI16_V_M2_M2_MASK + {5, OperandInfo379}, // Inst #4715 = PseudoVLUXEI16_V_M2_M4 + {8, OperandInfo380}, // Inst #4716 = PseudoVLUXEI16_V_M2_M4_MASK + {5, OperandInfo381}, // Inst #4717 = PseudoVLUXEI16_V_M2_M8 + {8, OperandInfo382}, // Inst #4718 = PseudoVLUXEI16_V_M2_M8_MASK + {5, OperandInfo383}, // Inst #4719 = PseudoVLUXEI16_V_M4_M2 + {8, OperandInfo384}, // Inst #4720 = PseudoVLUXEI16_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #4721 = PseudoVLUXEI16_V_M4_M4 + {8, OperandInfo386}, // Inst #4722 = PseudoVLUXEI16_V_M4_M4_MASK + {5, OperandInfo387}, // Inst #4723 = PseudoVLUXEI16_V_M4_M8 + {8, OperandInfo388}, // Inst #4724 = PseudoVLUXEI16_V_M4_M8_MASK + {5, OperandInfo389}, // Inst #4725 = PseudoVLUXEI16_V_M8_M4 + {8, OperandInfo390}, // Inst #4726 = PseudoVLUXEI16_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #4727 = PseudoVLUXEI16_V_M8_M8 + {8, OperandInfo392}, // Inst #4728 = PseudoVLUXEI16_V_M8_M8_MASK + {5, OperandInfo373}, // Inst #4729 = PseudoVLUXEI16_V_MF2_M1 + {8, OperandInfo374}, // Inst #4730 = PseudoVLUXEI16_V_MF2_M1_MASK + {5, OperandInfo369}, // Inst #4731 = PseudoVLUXEI16_V_MF2_M2 + {8, OperandInfo370}, // Inst #4732 = PseudoVLUXEI16_V_MF2_M2_MASK + {5, OperandInfo367}, // Inst #4733 = PseudoVLUXEI16_V_MF2_MF2 + {8, OperandInfo368}, // Inst #4734 = PseudoVLUXEI16_V_MF2_MF2_MASK + {5, OperandInfo373}, // Inst #4735 = PseudoVLUXEI16_V_MF2_MF4 + {8, OperandInfo374}, // Inst #4736 = PseudoVLUXEI16_V_MF2_MF4_MASK + {5, OperandInfo373}, // Inst #4737 = PseudoVLUXEI16_V_MF4_M1 + {8, OperandInfo374}, // Inst #4738 = PseudoVLUXEI16_V_MF4_M1_MASK + {5, OperandInfo373}, // Inst #4739 = PseudoVLUXEI16_V_MF4_MF2 + {8, OperandInfo374}, // Inst #4740 = PseudoVLUXEI16_V_MF4_MF2_MASK + {5, OperandInfo367}, // Inst #4741 = PseudoVLUXEI16_V_MF4_MF4 + {8, OperandInfo368}, // Inst #4742 = PseudoVLUXEI16_V_MF4_MF4_MASK + {5, OperandInfo373}, // Inst #4743 = PseudoVLUXEI16_V_MF4_MF8 + {8, OperandInfo374}, // Inst #4744 = PseudoVLUXEI16_V_MF4_MF8_MASK + {5, OperandInfo367}, // Inst #4745 = PseudoVLUXEI32_V_M1_M1 + {8, OperandInfo368}, // Inst #4746 = PseudoVLUXEI32_V_M1_M1_MASK + {5, OperandInfo369}, // Inst #4747 = PseudoVLUXEI32_V_M1_M2 + {8, OperandInfo370}, // Inst #4748 = PseudoVLUXEI32_V_M1_M2_MASK + {5, OperandInfo373}, // Inst #4749 = PseudoVLUXEI32_V_M1_MF2 + {8, OperandInfo374}, // Inst #4750 = PseudoVLUXEI32_V_M1_MF2_MASK + {5, OperandInfo373}, // Inst #4751 = PseudoVLUXEI32_V_M1_MF4 + {8, OperandInfo374}, // Inst #4752 = PseudoVLUXEI32_V_M1_MF4_MASK + {5, OperandInfo375}, // Inst #4753 = PseudoVLUXEI32_V_M2_M1 + {8, OperandInfo376}, // Inst #4754 = PseudoVLUXEI32_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #4755 = PseudoVLUXEI32_V_M2_M2 + {8, OperandInfo378}, // Inst #4756 = PseudoVLUXEI32_V_M2_M2_MASK + {5, OperandInfo379}, // Inst #4757 = PseudoVLUXEI32_V_M2_M4 + {8, OperandInfo380}, // Inst #4758 = PseudoVLUXEI32_V_M2_M4_MASK + {5, OperandInfo375}, // Inst #4759 = PseudoVLUXEI32_V_M2_MF2 + {8, OperandInfo376}, // Inst #4760 = PseudoVLUXEI32_V_M2_MF2_MASK + {5, OperandInfo393}, // Inst #4761 = PseudoVLUXEI32_V_M4_M1 + {8, OperandInfo394}, // Inst #4762 = PseudoVLUXEI32_V_M4_M1_MASK + {5, OperandInfo383}, // Inst #4763 = PseudoVLUXEI32_V_M4_M2 + {8, OperandInfo384}, // Inst #4764 = PseudoVLUXEI32_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #4765 = PseudoVLUXEI32_V_M4_M4 + {8, OperandInfo386}, // Inst #4766 = PseudoVLUXEI32_V_M4_M4_MASK + {5, OperandInfo387}, // Inst #4767 = PseudoVLUXEI32_V_M4_M8 + {8, OperandInfo388}, // Inst #4768 = PseudoVLUXEI32_V_M4_M8_MASK + {5, OperandInfo395}, // Inst #4769 = PseudoVLUXEI32_V_M8_M2 + {8, OperandInfo396}, // Inst #4770 = PseudoVLUXEI32_V_M8_M2_MASK + {5, OperandInfo389}, // Inst #4771 = PseudoVLUXEI32_V_M8_M4 + {8, OperandInfo390}, // Inst #4772 = PseudoVLUXEI32_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #4773 = PseudoVLUXEI32_V_M8_M8 + {8, OperandInfo392}, // Inst #4774 = PseudoVLUXEI32_V_M8_M8_MASK + {5, OperandInfo373}, // Inst #4775 = PseudoVLUXEI32_V_MF2_M1 + {8, OperandInfo374}, // Inst #4776 = PseudoVLUXEI32_V_MF2_M1_MASK + {5, OperandInfo367}, // Inst #4777 = PseudoVLUXEI32_V_MF2_MF2 + {8, OperandInfo368}, // Inst #4778 = PseudoVLUXEI32_V_MF2_MF2_MASK + {5, OperandInfo373}, // Inst #4779 = PseudoVLUXEI32_V_MF2_MF4 + {8, OperandInfo374}, // Inst #4780 = PseudoVLUXEI32_V_MF2_MF4_MASK + {5, OperandInfo373}, // Inst #4781 = PseudoVLUXEI32_V_MF2_MF8 + {8, OperandInfo374}, // Inst #4782 = PseudoVLUXEI32_V_MF2_MF8_MASK + {5, OperandInfo367}, // Inst #4783 = PseudoVLUXEI64_V_M1_M1 + {8, OperandInfo368}, // Inst #4784 = PseudoVLUXEI64_V_M1_M1_MASK + {5, OperandInfo373}, // Inst #4785 = PseudoVLUXEI64_V_M1_MF2 + {8, OperandInfo374}, // Inst #4786 = PseudoVLUXEI64_V_M1_MF2_MASK + {5, OperandInfo373}, // Inst #4787 = PseudoVLUXEI64_V_M1_MF4 + {8, OperandInfo374}, // Inst #4788 = PseudoVLUXEI64_V_M1_MF4_MASK + {5, OperandInfo373}, // Inst #4789 = PseudoVLUXEI64_V_M1_MF8 + {8, OperandInfo374}, // Inst #4790 = PseudoVLUXEI64_V_M1_MF8_MASK + {5, OperandInfo375}, // Inst #4791 = PseudoVLUXEI64_V_M2_M1 + {8, OperandInfo376}, // Inst #4792 = PseudoVLUXEI64_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #4793 = PseudoVLUXEI64_V_M2_M2 + {8, OperandInfo378}, // Inst #4794 = PseudoVLUXEI64_V_M2_M2_MASK + {5, OperandInfo375}, // Inst #4795 = PseudoVLUXEI64_V_M2_MF2 + {8, OperandInfo376}, // Inst #4796 = PseudoVLUXEI64_V_M2_MF2_MASK + {5, OperandInfo375}, // Inst #4797 = PseudoVLUXEI64_V_M2_MF4 + {8, OperandInfo376}, // Inst #4798 = PseudoVLUXEI64_V_M2_MF4_MASK + {5, OperandInfo393}, // Inst #4799 = PseudoVLUXEI64_V_M4_M1 + {8, OperandInfo394}, // Inst #4800 = PseudoVLUXEI64_V_M4_M1_MASK + {5, OperandInfo383}, // Inst #4801 = PseudoVLUXEI64_V_M4_M2 + {8, OperandInfo384}, // Inst #4802 = PseudoVLUXEI64_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #4803 = PseudoVLUXEI64_V_M4_M4 + {8, OperandInfo386}, // Inst #4804 = PseudoVLUXEI64_V_M4_M4_MASK + {5, OperandInfo393}, // Inst #4805 = PseudoVLUXEI64_V_M4_MF2 + {8, OperandInfo394}, // Inst #4806 = PseudoVLUXEI64_V_M4_MF2_MASK + {5, OperandInfo397}, // Inst #4807 = PseudoVLUXEI64_V_M8_M1 + {8, OperandInfo398}, // Inst #4808 = PseudoVLUXEI64_V_M8_M1_MASK + {5, OperandInfo395}, // Inst #4809 = PseudoVLUXEI64_V_M8_M2 + {8, OperandInfo396}, // Inst #4810 = PseudoVLUXEI64_V_M8_M2_MASK + {5, OperandInfo389}, // Inst #4811 = PseudoVLUXEI64_V_M8_M4 + {8, OperandInfo390}, // Inst #4812 = PseudoVLUXEI64_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #4813 = PseudoVLUXEI64_V_M8_M8 + {8, OperandInfo392}, // Inst #4814 = PseudoVLUXEI64_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #4815 = PseudoVLUXEI8_V_M1_M1 + {8, OperandInfo368}, // Inst #4816 = PseudoVLUXEI8_V_M1_M1_MASK + {5, OperandInfo369}, // Inst #4817 = PseudoVLUXEI8_V_M1_M2 + {8, OperandInfo370}, // Inst #4818 = PseudoVLUXEI8_V_M1_M2_MASK + {5, OperandInfo371}, // Inst #4819 = PseudoVLUXEI8_V_M1_M4 + {8, OperandInfo372}, // Inst #4820 = PseudoVLUXEI8_V_M1_M4_MASK + {5, OperandInfo399}, // Inst #4821 = PseudoVLUXEI8_V_M1_M8 + {8, OperandInfo400}, // Inst #4822 = PseudoVLUXEI8_V_M1_M8_MASK + {5, OperandInfo377}, // Inst #4823 = PseudoVLUXEI8_V_M2_M2 + {8, OperandInfo378}, // Inst #4824 = PseudoVLUXEI8_V_M2_M2_MASK + {5, OperandInfo379}, // Inst #4825 = PseudoVLUXEI8_V_M2_M4 + {8, OperandInfo380}, // Inst #4826 = PseudoVLUXEI8_V_M2_M4_MASK + {5, OperandInfo381}, // Inst #4827 = PseudoVLUXEI8_V_M2_M8 + {8, OperandInfo382}, // Inst #4828 = PseudoVLUXEI8_V_M2_M8_MASK + {5, OperandInfo385}, // Inst #4829 = PseudoVLUXEI8_V_M4_M4 + {8, OperandInfo386}, // Inst #4830 = PseudoVLUXEI8_V_M4_M4_MASK + {5, OperandInfo387}, // Inst #4831 = PseudoVLUXEI8_V_M4_M8 + {8, OperandInfo388}, // Inst #4832 = PseudoVLUXEI8_V_M4_M8_MASK + {5, OperandInfo391}, // Inst #4833 = PseudoVLUXEI8_V_M8_M8 + {8, OperandInfo392}, // Inst #4834 = PseudoVLUXEI8_V_M8_M8_MASK + {5, OperandInfo373}, // Inst #4835 = PseudoVLUXEI8_V_MF2_M1 + {8, OperandInfo374}, // Inst #4836 = PseudoVLUXEI8_V_MF2_M1_MASK + {5, OperandInfo369}, // Inst #4837 = PseudoVLUXEI8_V_MF2_M2 + {8, OperandInfo370}, // Inst #4838 = PseudoVLUXEI8_V_MF2_M2_MASK + {5, OperandInfo371}, // Inst #4839 = PseudoVLUXEI8_V_MF2_M4 + {8, OperandInfo372}, // Inst #4840 = PseudoVLUXEI8_V_MF2_M4_MASK + {5, OperandInfo367}, // Inst #4841 = PseudoVLUXEI8_V_MF2_MF2 + {8, OperandInfo368}, // Inst #4842 = PseudoVLUXEI8_V_MF2_MF2_MASK + {5, OperandInfo373}, // Inst #4843 = PseudoVLUXEI8_V_MF4_M1 + {8, OperandInfo374}, // Inst #4844 = PseudoVLUXEI8_V_MF4_M1_MASK + {5, OperandInfo369}, // Inst #4845 = PseudoVLUXEI8_V_MF4_M2 + {8, OperandInfo370}, // Inst #4846 = PseudoVLUXEI8_V_MF4_M2_MASK + {5, OperandInfo373}, // Inst #4847 = PseudoVLUXEI8_V_MF4_MF2 + {8, OperandInfo374}, // Inst #4848 = PseudoVLUXEI8_V_MF4_MF2_MASK + {5, OperandInfo367}, // Inst #4849 = PseudoVLUXEI8_V_MF4_MF4 + {8, OperandInfo368}, // Inst #4850 = PseudoVLUXEI8_V_MF4_MF4_MASK + {5, OperandInfo373}, // Inst #4851 = PseudoVLUXEI8_V_MF8_M1 + {8, OperandInfo374}, // Inst #4852 = PseudoVLUXEI8_V_MF8_M1_MASK + {5, OperandInfo373}, // Inst #4853 = PseudoVLUXEI8_V_MF8_MF2 + {8, OperandInfo374}, // Inst #4854 = PseudoVLUXEI8_V_MF8_MF2_MASK + {5, OperandInfo373}, // Inst #4855 = PseudoVLUXEI8_V_MF8_MF4 + {8, OperandInfo374}, // Inst #4856 = PseudoVLUXEI8_V_MF8_MF4_MASK + {5, OperandInfo367}, // Inst #4857 = PseudoVLUXEI8_V_MF8_MF8 + {8, OperandInfo368}, // Inst #4858 = PseudoVLUXEI8_V_MF8_MF8_MASK + {5, OperandInfo401}, // Inst #4859 = PseudoVLUXSEG2EI16_V_M1_M1 + {8, OperandInfo402}, // Inst #4860 = PseudoVLUXSEG2EI16_V_M1_M1_MASK + {5, OperandInfo403}, // Inst #4861 = PseudoVLUXSEG2EI16_V_M1_M2 + {8, OperandInfo404}, // Inst #4862 = PseudoVLUXSEG2EI16_V_M1_M2_MASK + {5, OperandInfo405}, // Inst #4863 = PseudoVLUXSEG2EI16_V_M1_M4 + {8, OperandInfo406}, // Inst #4864 = PseudoVLUXSEG2EI16_V_M1_M4_MASK + {5, OperandInfo401}, // Inst #4865 = PseudoVLUXSEG2EI16_V_M1_MF2 + {8, OperandInfo402}, // Inst #4866 = PseudoVLUXSEG2EI16_V_M1_MF2_MASK + {5, OperandInfo407}, // Inst #4867 = PseudoVLUXSEG2EI16_V_M2_M1 + {8, OperandInfo408}, // Inst #4868 = PseudoVLUXSEG2EI16_V_M2_M1_MASK + {5, OperandInfo409}, // Inst #4869 = PseudoVLUXSEG2EI16_V_M2_M2 + {8, OperandInfo410}, // Inst #4870 = PseudoVLUXSEG2EI16_V_M2_M2_MASK + {5, OperandInfo411}, // Inst #4871 = PseudoVLUXSEG2EI16_V_M2_M4 + {8, OperandInfo412}, // Inst #4872 = PseudoVLUXSEG2EI16_V_M2_M4_MASK + {5, OperandInfo413}, // Inst #4873 = PseudoVLUXSEG2EI16_V_M4_M2 + {8, OperandInfo414}, // Inst #4874 = PseudoVLUXSEG2EI16_V_M4_M2_MASK + {5, OperandInfo415}, // Inst #4875 = PseudoVLUXSEG2EI16_V_M4_M4 + {8, OperandInfo416}, // Inst #4876 = PseudoVLUXSEG2EI16_V_M4_M4_MASK + {5, OperandInfo417}, // Inst #4877 = PseudoVLUXSEG2EI16_V_M8_M4 + {8, OperandInfo418}, // Inst #4878 = PseudoVLUXSEG2EI16_V_M8_M4_MASK + {5, OperandInfo401}, // Inst #4879 = PseudoVLUXSEG2EI16_V_MF2_M1 + {8, OperandInfo402}, // Inst #4880 = PseudoVLUXSEG2EI16_V_MF2_M1_MASK + {5, OperandInfo403}, // Inst #4881 = PseudoVLUXSEG2EI16_V_MF2_M2 + {8, OperandInfo404}, // Inst #4882 = PseudoVLUXSEG2EI16_V_MF2_M2_MASK + {5, OperandInfo401}, // Inst #4883 = PseudoVLUXSEG2EI16_V_MF2_MF2 + {8, OperandInfo402}, // Inst #4884 = PseudoVLUXSEG2EI16_V_MF2_MF2_MASK + {5, OperandInfo401}, // Inst #4885 = PseudoVLUXSEG2EI16_V_MF2_MF4 + {8, OperandInfo402}, // Inst #4886 = PseudoVLUXSEG2EI16_V_MF2_MF4_MASK + {5, OperandInfo401}, // Inst #4887 = PseudoVLUXSEG2EI16_V_MF4_M1 + {8, OperandInfo402}, // Inst #4888 = PseudoVLUXSEG2EI16_V_MF4_M1_MASK + {5, OperandInfo401}, // Inst #4889 = PseudoVLUXSEG2EI16_V_MF4_MF2 + {8, OperandInfo402}, // Inst #4890 = PseudoVLUXSEG2EI16_V_MF4_MF2_MASK + {5, OperandInfo401}, // Inst #4891 = PseudoVLUXSEG2EI16_V_MF4_MF4 + {8, OperandInfo402}, // Inst #4892 = PseudoVLUXSEG2EI16_V_MF4_MF4_MASK + {5, OperandInfo401}, // Inst #4893 = PseudoVLUXSEG2EI16_V_MF4_MF8 + {8, OperandInfo402}, // Inst #4894 = PseudoVLUXSEG2EI16_V_MF4_MF8_MASK + {5, OperandInfo401}, // Inst #4895 = PseudoVLUXSEG2EI32_V_M1_M1 + {8, OperandInfo402}, // Inst #4896 = PseudoVLUXSEG2EI32_V_M1_M1_MASK + {5, OperandInfo403}, // Inst #4897 = PseudoVLUXSEG2EI32_V_M1_M2 + {8, OperandInfo404}, // Inst #4898 = PseudoVLUXSEG2EI32_V_M1_M2_MASK + {5, OperandInfo401}, // Inst #4899 = PseudoVLUXSEG2EI32_V_M1_MF2 + {8, OperandInfo402}, // Inst #4900 = PseudoVLUXSEG2EI32_V_M1_MF2_MASK + {5, OperandInfo401}, // Inst #4901 = PseudoVLUXSEG2EI32_V_M1_MF4 + {8, OperandInfo402}, // Inst #4902 = PseudoVLUXSEG2EI32_V_M1_MF4_MASK + {5, OperandInfo407}, // Inst #4903 = PseudoVLUXSEG2EI32_V_M2_M1 + {8, OperandInfo408}, // Inst #4904 = PseudoVLUXSEG2EI32_V_M2_M1_MASK + {5, OperandInfo409}, // Inst #4905 = PseudoVLUXSEG2EI32_V_M2_M2 + {8, OperandInfo410}, // Inst #4906 = PseudoVLUXSEG2EI32_V_M2_M2_MASK + {5, OperandInfo411}, // Inst #4907 = PseudoVLUXSEG2EI32_V_M2_M4 + {8, OperandInfo412}, // Inst #4908 = PseudoVLUXSEG2EI32_V_M2_M4_MASK + {5, OperandInfo407}, // Inst #4909 = PseudoVLUXSEG2EI32_V_M2_MF2 + {8, OperandInfo408}, // Inst #4910 = PseudoVLUXSEG2EI32_V_M2_MF2_MASK + {5, OperandInfo419}, // Inst #4911 = PseudoVLUXSEG2EI32_V_M4_M1 + {8, OperandInfo420}, // Inst #4912 = PseudoVLUXSEG2EI32_V_M4_M1_MASK + {5, OperandInfo413}, // Inst #4913 = PseudoVLUXSEG2EI32_V_M4_M2 + {8, OperandInfo414}, // Inst #4914 = PseudoVLUXSEG2EI32_V_M4_M2_MASK + {5, OperandInfo415}, // Inst #4915 = PseudoVLUXSEG2EI32_V_M4_M4 + {8, OperandInfo416}, // Inst #4916 = PseudoVLUXSEG2EI32_V_M4_M4_MASK + {5, OperandInfo421}, // Inst #4917 = PseudoVLUXSEG2EI32_V_M8_M2 + {8, OperandInfo422}, // Inst #4918 = PseudoVLUXSEG2EI32_V_M8_M2_MASK + {5, OperandInfo417}, // Inst #4919 = PseudoVLUXSEG2EI32_V_M8_M4 + {8, OperandInfo418}, // Inst #4920 = PseudoVLUXSEG2EI32_V_M8_M4_MASK + {5, OperandInfo401}, // Inst #4921 = PseudoVLUXSEG2EI32_V_MF2_M1 + {8, OperandInfo402}, // Inst #4922 = PseudoVLUXSEG2EI32_V_MF2_M1_MASK + {5, OperandInfo401}, // Inst #4923 = PseudoVLUXSEG2EI32_V_MF2_MF2 + {8, OperandInfo402}, // Inst #4924 = PseudoVLUXSEG2EI32_V_MF2_MF2_MASK + {5, OperandInfo401}, // Inst #4925 = PseudoVLUXSEG2EI32_V_MF2_MF4 + {8, OperandInfo402}, // Inst #4926 = PseudoVLUXSEG2EI32_V_MF2_MF4_MASK + {5, OperandInfo401}, // Inst #4927 = PseudoVLUXSEG2EI32_V_MF2_MF8 + {8, OperandInfo402}, // Inst #4928 = PseudoVLUXSEG2EI32_V_MF2_MF8_MASK + {5, OperandInfo401}, // Inst #4929 = PseudoVLUXSEG2EI64_V_M1_M1 + {8, OperandInfo402}, // Inst #4930 = PseudoVLUXSEG2EI64_V_M1_M1_MASK + {5, OperandInfo401}, // Inst #4931 = PseudoVLUXSEG2EI64_V_M1_MF2 + {8, OperandInfo402}, // Inst #4932 = PseudoVLUXSEG2EI64_V_M1_MF2_MASK + {5, OperandInfo401}, // Inst #4933 = PseudoVLUXSEG2EI64_V_M1_MF4 + {8, OperandInfo402}, // Inst #4934 = PseudoVLUXSEG2EI64_V_M1_MF4_MASK + {5, OperandInfo401}, // Inst #4935 = PseudoVLUXSEG2EI64_V_M1_MF8 + {8, OperandInfo402}, // Inst #4936 = PseudoVLUXSEG2EI64_V_M1_MF8_MASK + {5, OperandInfo407}, // Inst #4937 = PseudoVLUXSEG2EI64_V_M2_M1 + {8, OperandInfo408}, // Inst #4938 = PseudoVLUXSEG2EI64_V_M2_M1_MASK + {5, OperandInfo409}, // Inst #4939 = PseudoVLUXSEG2EI64_V_M2_M2 + {8, OperandInfo410}, // Inst #4940 = PseudoVLUXSEG2EI64_V_M2_M2_MASK + {5, OperandInfo407}, // Inst #4941 = PseudoVLUXSEG2EI64_V_M2_MF2 + {8, OperandInfo408}, // Inst #4942 = PseudoVLUXSEG2EI64_V_M2_MF2_MASK + {5, OperandInfo407}, // Inst #4943 = PseudoVLUXSEG2EI64_V_M2_MF4 + {8, OperandInfo408}, // Inst #4944 = PseudoVLUXSEG2EI64_V_M2_MF4_MASK + {5, OperandInfo419}, // Inst #4945 = PseudoVLUXSEG2EI64_V_M4_M1 + {8, OperandInfo420}, // Inst #4946 = PseudoVLUXSEG2EI64_V_M4_M1_MASK + {5, OperandInfo413}, // Inst #4947 = PseudoVLUXSEG2EI64_V_M4_M2 + {8, OperandInfo414}, // Inst #4948 = PseudoVLUXSEG2EI64_V_M4_M2_MASK + {5, OperandInfo415}, // Inst #4949 = PseudoVLUXSEG2EI64_V_M4_M4 + {8, OperandInfo416}, // Inst #4950 = PseudoVLUXSEG2EI64_V_M4_M4_MASK + {5, OperandInfo419}, // Inst #4951 = PseudoVLUXSEG2EI64_V_M4_MF2 + {8, OperandInfo420}, // Inst #4952 = PseudoVLUXSEG2EI64_V_M4_MF2_MASK + {5, OperandInfo423}, // Inst #4953 = PseudoVLUXSEG2EI64_V_M8_M1 + {8, OperandInfo424}, // Inst #4954 = PseudoVLUXSEG2EI64_V_M8_M1_MASK + {5, OperandInfo421}, // Inst #4955 = PseudoVLUXSEG2EI64_V_M8_M2 + {8, OperandInfo422}, // Inst #4956 = PseudoVLUXSEG2EI64_V_M8_M2_MASK + {5, OperandInfo417}, // Inst #4957 = PseudoVLUXSEG2EI64_V_M8_M4 + {8, OperandInfo418}, // Inst #4958 = PseudoVLUXSEG2EI64_V_M8_M4_MASK + {5, OperandInfo401}, // Inst #4959 = PseudoVLUXSEG2EI8_V_M1_M1 + {8, OperandInfo402}, // Inst #4960 = PseudoVLUXSEG2EI8_V_M1_M1_MASK + {5, OperandInfo403}, // Inst #4961 = PseudoVLUXSEG2EI8_V_M1_M2 + {8, OperandInfo404}, // Inst #4962 = PseudoVLUXSEG2EI8_V_M1_M2_MASK + {5, OperandInfo405}, // Inst #4963 = PseudoVLUXSEG2EI8_V_M1_M4 + {8, OperandInfo406}, // Inst #4964 = PseudoVLUXSEG2EI8_V_M1_M4_MASK + {5, OperandInfo409}, // Inst #4965 = PseudoVLUXSEG2EI8_V_M2_M2 + {8, OperandInfo410}, // Inst #4966 = PseudoVLUXSEG2EI8_V_M2_M2_MASK + {5, OperandInfo411}, // Inst #4967 = PseudoVLUXSEG2EI8_V_M2_M4 + {8, OperandInfo412}, // Inst #4968 = PseudoVLUXSEG2EI8_V_M2_M4_MASK + {5, OperandInfo415}, // Inst #4969 = PseudoVLUXSEG2EI8_V_M4_M4 + {8, OperandInfo416}, // Inst #4970 = PseudoVLUXSEG2EI8_V_M4_M4_MASK + {5, OperandInfo401}, // Inst #4971 = PseudoVLUXSEG2EI8_V_MF2_M1 + {8, OperandInfo402}, // Inst #4972 = PseudoVLUXSEG2EI8_V_MF2_M1_MASK + {5, OperandInfo403}, // Inst #4973 = PseudoVLUXSEG2EI8_V_MF2_M2 + {8, OperandInfo404}, // Inst #4974 = PseudoVLUXSEG2EI8_V_MF2_M2_MASK + {5, OperandInfo405}, // Inst #4975 = PseudoVLUXSEG2EI8_V_MF2_M4 + {8, OperandInfo406}, // Inst #4976 = PseudoVLUXSEG2EI8_V_MF2_M4_MASK + {5, OperandInfo401}, // Inst #4977 = PseudoVLUXSEG2EI8_V_MF2_MF2 + {8, OperandInfo402}, // Inst #4978 = PseudoVLUXSEG2EI8_V_MF2_MF2_MASK + {5, OperandInfo401}, // Inst #4979 = PseudoVLUXSEG2EI8_V_MF4_M1 + {8, OperandInfo402}, // Inst #4980 = PseudoVLUXSEG2EI8_V_MF4_M1_MASK + {5, OperandInfo403}, // Inst #4981 = PseudoVLUXSEG2EI8_V_MF4_M2 + {8, OperandInfo404}, // Inst #4982 = PseudoVLUXSEG2EI8_V_MF4_M2_MASK + {5, OperandInfo401}, // Inst #4983 = PseudoVLUXSEG2EI8_V_MF4_MF2 + {8, OperandInfo402}, // Inst #4984 = PseudoVLUXSEG2EI8_V_MF4_MF2_MASK + {5, OperandInfo401}, // Inst #4985 = PseudoVLUXSEG2EI8_V_MF4_MF4 + {8, OperandInfo402}, // Inst #4986 = PseudoVLUXSEG2EI8_V_MF4_MF4_MASK + {5, OperandInfo401}, // Inst #4987 = PseudoVLUXSEG2EI8_V_MF8_M1 + {8, OperandInfo402}, // Inst #4988 = PseudoVLUXSEG2EI8_V_MF8_M1_MASK + {5, OperandInfo401}, // Inst #4989 = PseudoVLUXSEG2EI8_V_MF8_MF2 + {8, OperandInfo402}, // Inst #4990 = PseudoVLUXSEG2EI8_V_MF8_MF2_MASK + {5, OperandInfo401}, // Inst #4991 = PseudoVLUXSEG2EI8_V_MF8_MF4 + {8, OperandInfo402}, // Inst #4992 = PseudoVLUXSEG2EI8_V_MF8_MF4_MASK + {5, OperandInfo401}, // Inst #4993 = PseudoVLUXSEG2EI8_V_MF8_MF8 + {8, OperandInfo402}, // Inst #4994 = PseudoVLUXSEG2EI8_V_MF8_MF8_MASK + {5, OperandInfo425}, // Inst #4995 = PseudoVLUXSEG3EI16_V_M1_M1 + {8, OperandInfo426}, // Inst #4996 = PseudoVLUXSEG3EI16_V_M1_M1_MASK + {5, OperandInfo427}, // Inst #4997 = PseudoVLUXSEG3EI16_V_M1_M2 + {8, OperandInfo428}, // Inst #4998 = PseudoVLUXSEG3EI16_V_M1_M2_MASK + {5, OperandInfo425}, // Inst #4999 = PseudoVLUXSEG3EI16_V_M1_MF2 + {8, OperandInfo426}, // Inst #5000 = PseudoVLUXSEG3EI16_V_M1_MF2_MASK + {5, OperandInfo429}, // Inst #5001 = PseudoVLUXSEG3EI16_V_M2_M1 + {8, OperandInfo430}, // Inst #5002 = PseudoVLUXSEG3EI16_V_M2_M1_MASK + {5, OperandInfo431}, // Inst #5003 = PseudoVLUXSEG3EI16_V_M2_M2 + {8, OperandInfo432}, // Inst #5004 = PseudoVLUXSEG3EI16_V_M2_M2_MASK + {5, OperandInfo433}, // Inst #5005 = PseudoVLUXSEG3EI16_V_M4_M2 + {8, OperandInfo434}, // Inst #5006 = PseudoVLUXSEG3EI16_V_M4_M2_MASK + {5, OperandInfo425}, // Inst #5007 = PseudoVLUXSEG3EI16_V_MF2_M1 + {8, OperandInfo426}, // Inst #5008 = PseudoVLUXSEG3EI16_V_MF2_M1_MASK + {5, OperandInfo427}, // Inst #5009 = PseudoVLUXSEG3EI16_V_MF2_M2 + {8, OperandInfo428}, // Inst #5010 = PseudoVLUXSEG3EI16_V_MF2_M2_MASK + {5, OperandInfo425}, // Inst #5011 = PseudoVLUXSEG3EI16_V_MF2_MF2 + {8, OperandInfo426}, // Inst #5012 = PseudoVLUXSEG3EI16_V_MF2_MF2_MASK + {5, OperandInfo425}, // Inst #5013 = PseudoVLUXSEG3EI16_V_MF2_MF4 + {8, OperandInfo426}, // Inst #5014 = PseudoVLUXSEG3EI16_V_MF2_MF4_MASK + {5, OperandInfo425}, // Inst #5015 = PseudoVLUXSEG3EI16_V_MF4_M1 + {8, OperandInfo426}, // Inst #5016 = PseudoVLUXSEG3EI16_V_MF4_M1_MASK + {5, OperandInfo425}, // Inst #5017 = PseudoVLUXSEG3EI16_V_MF4_MF2 + {8, OperandInfo426}, // Inst #5018 = PseudoVLUXSEG3EI16_V_MF4_MF2_MASK + {5, OperandInfo425}, // Inst #5019 = PseudoVLUXSEG3EI16_V_MF4_MF4 + {8, OperandInfo426}, // Inst #5020 = PseudoVLUXSEG3EI16_V_MF4_MF4_MASK + {5, OperandInfo425}, // Inst #5021 = PseudoVLUXSEG3EI16_V_MF4_MF8 + {8, OperandInfo426}, // Inst #5022 = PseudoVLUXSEG3EI16_V_MF4_MF8_MASK + {5, OperandInfo425}, // Inst #5023 = PseudoVLUXSEG3EI32_V_M1_M1 + {8, OperandInfo426}, // Inst #5024 = PseudoVLUXSEG3EI32_V_M1_M1_MASK + {5, OperandInfo427}, // Inst #5025 = PseudoVLUXSEG3EI32_V_M1_M2 + {8, OperandInfo428}, // Inst #5026 = PseudoVLUXSEG3EI32_V_M1_M2_MASK + {5, OperandInfo425}, // Inst #5027 = PseudoVLUXSEG3EI32_V_M1_MF2 + {8, OperandInfo426}, // Inst #5028 = PseudoVLUXSEG3EI32_V_M1_MF2_MASK + {5, OperandInfo425}, // Inst #5029 = PseudoVLUXSEG3EI32_V_M1_MF4 + {8, OperandInfo426}, // Inst #5030 = PseudoVLUXSEG3EI32_V_M1_MF4_MASK + {5, OperandInfo429}, // Inst #5031 = PseudoVLUXSEG3EI32_V_M2_M1 + {8, OperandInfo430}, // Inst #5032 = PseudoVLUXSEG3EI32_V_M2_M1_MASK + {5, OperandInfo431}, // Inst #5033 = PseudoVLUXSEG3EI32_V_M2_M2 + {8, OperandInfo432}, // Inst #5034 = PseudoVLUXSEG3EI32_V_M2_M2_MASK + {5, OperandInfo429}, // Inst #5035 = PseudoVLUXSEG3EI32_V_M2_MF2 + {8, OperandInfo430}, // Inst #5036 = PseudoVLUXSEG3EI32_V_M2_MF2_MASK + {5, OperandInfo435}, // Inst #5037 = PseudoVLUXSEG3EI32_V_M4_M1 + {8, OperandInfo436}, // Inst #5038 = PseudoVLUXSEG3EI32_V_M4_M1_MASK + {5, OperandInfo433}, // Inst #5039 = PseudoVLUXSEG3EI32_V_M4_M2 + {8, OperandInfo434}, // Inst #5040 = PseudoVLUXSEG3EI32_V_M4_M2_MASK + {5, OperandInfo437}, // Inst #5041 = PseudoVLUXSEG3EI32_V_M8_M2 + {8, OperandInfo438}, // Inst #5042 = PseudoVLUXSEG3EI32_V_M8_M2_MASK + {5, OperandInfo425}, // Inst #5043 = PseudoVLUXSEG3EI32_V_MF2_M1 + {8, OperandInfo426}, // Inst #5044 = PseudoVLUXSEG3EI32_V_MF2_M1_MASK + {5, OperandInfo425}, // Inst #5045 = PseudoVLUXSEG3EI32_V_MF2_MF2 + {8, OperandInfo426}, // Inst #5046 = PseudoVLUXSEG3EI32_V_MF2_MF2_MASK + {5, OperandInfo425}, // Inst #5047 = PseudoVLUXSEG3EI32_V_MF2_MF4 + {8, OperandInfo426}, // Inst #5048 = PseudoVLUXSEG3EI32_V_MF2_MF4_MASK + {5, OperandInfo425}, // Inst #5049 = PseudoVLUXSEG3EI32_V_MF2_MF8 + {8, OperandInfo426}, // Inst #5050 = PseudoVLUXSEG3EI32_V_MF2_MF8_MASK + {5, OperandInfo425}, // Inst #5051 = PseudoVLUXSEG3EI64_V_M1_M1 + {8, OperandInfo426}, // Inst #5052 = PseudoVLUXSEG3EI64_V_M1_M1_MASK + {5, OperandInfo425}, // Inst #5053 = PseudoVLUXSEG3EI64_V_M1_MF2 + {8, OperandInfo426}, // Inst #5054 = PseudoVLUXSEG3EI64_V_M1_MF2_MASK + {5, OperandInfo425}, // Inst #5055 = PseudoVLUXSEG3EI64_V_M1_MF4 + {8, OperandInfo426}, // Inst #5056 = PseudoVLUXSEG3EI64_V_M1_MF4_MASK + {5, OperandInfo425}, // Inst #5057 = PseudoVLUXSEG3EI64_V_M1_MF8 + {8, OperandInfo426}, // Inst #5058 = PseudoVLUXSEG3EI64_V_M1_MF8_MASK + {5, OperandInfo429}, // Inst #5059 = PseudoVLUXSEG3EI64_V_M2_M1 + {8, OperandInfo430}, // Inst #5060 = PseudoVLUXSEG3EI64_V_M2_M1_MASK + {5, OperandInfo431}, // Inst #5061 = PseudoVLUXSEG3EI64_V_M2_M2 + {8, OperandInfo432}, // Inst #5062 = PseudoVLUXSEG3EI64_V_M2_M2_MASK + {5, OperandInfo429}, // Inst #5063 = PseudoVLUXSEG3EI64_V_M2_MF2 + {8, OperandInfo430}, // Inst #5064 = PseudoVLUXSEG3EI64_V_M2_MF2_MASK + {5, OperandInfo429}, // Inst #5065 = PseudoVLUXSEG3EI64_V_M2_MF4 + {8, OperandInfo430}, // Inst #5066 = PseudoVLUXSEG3EI64_V_M2_MF4_MASK + {5, OperandInfo435}, // Inst #5067 = PseudoVLUXSEG3EI64_V_M4_M1 + {8, OperandInfo436}, // Inst #5068 = PseudoVLUXSEG3EI64_V_M4_M1_MASK + {5, OperandInfo433}, // Inst #5069 = PseudoVLUXSEG3EI64_V_M4_M2 + {8, OperandInfo434}, // Inst #5070 = PseudoVLUXSEG3EI64_V_M4_M2_MASK + {5, OperandInfo435}, // Inst #5071 = PseudoVLUXSEG3EI64_V_M4_MF2 + {8, OperandInfo436}, // Inst #5072 = PseudoVLUXSEG3EI64_V_M4_MF2_MASK + {5, OperandInfo439}, // Inst #5073 = PseudoVLUXSEG3EI64_V_M8_M1 + {8, OperandInfo440}, // Inst #5074 = PseudoVLUXSEG3EI64_V_M8_M1_MASK + {5, OperandInfo437}, // Inst #5075 = PseudoVLUXSEG3EI64_V_M8_M2 + {8, OperandInfo438}, // Inst #5076 = PseudoVLUXSEG3EI64_V_M8_M2_MASK + {5, OperandInfo425}, // Inst #5077 = PseudoVLUXSEG3EI8_V_M1_M1 + {8, OperandInfo426}, // Inst #5078 = PseudoVLUXSEG3EI8_V_M1_M1_MASK + {5, OperandInfo427}, // Inst #5079 = PseudoVLUXSEG3EI8_V_M1_M2 + {8, OperandInfo428}, // Inst #5080 = PseudoVLUXSEG3EI8_V_M1_M2_MASK + {5, OperandInfo431}, // Inst #5081 = PseudoVLUXSEG3EI8_V_M2_M2 + {8, OperandInfo432}, // Inst #5082 = PseudoVLUXSEG3EI8_V_M2_M2_MASK + {5, OperandInfo425}, // Inst #5083 = PseudoVLUXSEG3EI8_V_MF2_M1 + {8, OperandInfo426}, // Inst #5084 = PseudoVLUXSEG3EI8_V_MF2_M1_MASK + {5, OperandInfo427}, // Inst #5085 = PseudoVLUXSEG3EI8_V_MF2_M2 + {8, OperandInfo428}, // Inst #5086 = PseudoVLUXSEG3EI8_V_MF2_M2_MASK + {5, OperandInfo425}, // Inst #5087 = PseudoVLUXSEG3EI8_V_MF2_MF2 + {8, OperandInfo426}, // Inst #5088 = PseudoVLUXSEG3EI8_V_MF2_MF2_MASK + {5, OperandInfo425}, // Inst #5089 = PseudoVLUXSEG3EI8_V_MF4_M1 + {8, OperandInfo426}, // Inst #5090 = PseudoVLUXSEG3EI8_V_MF4_M1_MASK + {5, OperandInfo427}, // Inst #5091 = PseudoVLUXSEG3EI8_V_MF4_M2 + {8, OperandInfo428}, // Inst #5092 = PseudoVLUXSEG3EI8_V_MF4_M2_MASK + {5, OperandInfo425}, // Inst #5093 = PseudoVLUXSEG3EI8_V_MF4_MF2 + {8, OperandInfo426}, // Inst #5094 = PseudoVLUXSEG3EI8_V_MF4_MF2_MASK + {5, OperandInfo425}, // Inst #5095 = PseudoVLUXSEG3EI8_V_MF4_MF4 + {8, OperandInfo426}, // Inst #5096 = PseudoVLUXSEG3EI8_V_MF4_MF4_MASK + {5, OperandInfo425}, // Inst #5097 = PseudoVLUXSEG3EI8_V_MF8_M1 + {8, OperandInfo426}, // Inst #5098 = PseudoVLUXSEG3EI8_V_MF8_M1_MASK + {5, OperandInfo425}, // Inst #5099 = PseudoVLUXSEG3EI8_V_MF8_MF2 + {8, OperandInfo426}, // Inst #5100 = PseudoVLUXSEG3EI8_V_MF8_MF2_MASK + {5, OperandInfo425}, // Inst #5101 = PseudoVLUXSEG3EI8_V_MF8_MF4 + {8, OperandInfo426}, // Inst #5102 = PseudoVLUXSEG3EI8_V_MF8_MF4_MASK + {5, OperandInfo425}, // Inst #5103 = PseudoVLUXSEG3EI8_V_MF8_MF8 + {8, OperandInfo426}, // Inst #5104 = PseudoVLUXSEG3EI8_V_MF8_MF8_MASK + {5, OperandInfo441}, // Inst #5105 = PseudoVLUXSEG4EI16_V_M1_M1 + {8, OperandInfo442}, // Inst #5106 = PseudoVLUXSEG4EI16_V_M1_M1_MASK + {5, OperandInfo443}, // Inst #5107 = PseudoVLUXSEG4EI16_V_M1_M2 + {8, OperandInfo444}, // Inst #5108 = PseudoVLUXSEG4EI16_V_M1_M2_MASK + {5, OperandInfo441}, // Inst #5109 = PseudoVLUXSEG4EI16_V_M1_MF2 + {8, OperandInfo442}, // Inst #5110 = PseudoVLUXSEG4EI16_V_M1_MF2_MASK + {5, OperandInfo445}, // Inst #5111 = PseudoVLUXSEG4EI16_V_M2_M1 + {8, OperandInfo446}, // Inst #5112 = PseudoVLUXSEG4EI16_V_M2_M1_MASK + {5, OperandInfo447}, // Inst #5113 = PseudoVLUXSEG4EI16_V_M2_M2 + {8, OperandInfo448}, // Inst #5114 = PseudoVLUXSEG4EI16_V_M2_M2_MASK + {5, OperandInfo449}, // Inst #5115 = PseudoVLUXSEG4EI16_V_M4_M2 + {8, OperandInfo450}, // Inst #5116 = PseudoVLUXSEG4EI16_V_M4_M2_MASK + {5, OperandInfo441}, // Inst #5117 = PseudoVLUXSEG4EI16_V_MF2_M1 + {8, OperandInfo442}, // Inst #5118 = PseudoVLUXSEG4EI16_V_MF2_M1_MASK + {5, OperandInfo443}, // Inst #5119 = PseudoVLUXSEG4EI16_V_MF2_M2 + {8, OperandInfo444}, // Inst #5120 = PseudoVLUXSEG4EI16_V_MF2_M2_MASK + {5, OperandInfo441}, // Inst #5121 = PseudoVLUXSEG4EI16_V_MF2_MF2 + {8, OperandInfo442}, // Inst #5122 = PseudoVLUXSEG4EI16_V_MF2_MF2_MASK + {5, OperandInfo441}, // Inst #5123 = PseudoVLUXSEG4EI16_V_MF2_MF4 + {8, OperandInfo442}, // Inst #5124 = PseudoVLUXSEG4EI16_V_MF2_MF4_MASK + {5, OperandInfo441}, // Inst #5125 = PseudoVLUXSEG4EI16_V_MF4_M1 + {8, OperandInfo442}, // Inst #5126 = PseudoVLUXSEG4EI16_V_MF4_M1_MASK + {5, OperandInfo441}, // Inst #5127 = PseudoVLUXSEG4EI16_V_MF4_MF2 + {8, OperandInfo442}, // Inst #5128 = PseudoVLUXSEG4EI16_V_MF4_MF2_MASK + {5, OperandInfo441}, // Inst #5129 = PseudoVLUXSEG4EI16_V_MF4_MF4 + {8, OperandInfo442}, // Inst #5130 = PseudoVLUXSEG4EI16_V_MF4_MF4_MASK + {5, OperandInfo441}, // Inst #5131 = PseudoVLUXSEG4EI16_V_MF4_MF8 + {8, OperandInfo442}, // Inst #5132 = PseudoVLUXSEG4EI16_V_MF4_MF8_MASK + {5, OperandInfo441}, // Inst #5133 = PseudoVLUXSEG4EI32_V_M1_M1 + {8, OperandInfo442}, // Inst #5134 = PseudoVLUXSEG4EI32_V_M1_M1_MASK + {5, OperandInfo443}, // Inst #5135 = PseudoVLUXSEG4EI32_V_M1_M2 + {8, OperandInfo444}, // Inst #5136 = PseudoVLUXSEG4EI32_V_M1_M2_MASK + {5, OperandInfo441}, // Inst #5137 = PseudoVLUXSEG4EI32_V_M1_MF2 + {8, OperandInfo442}, // Inst #5138 = PseudoVLUXSEG4EI32_V_M1_MF2_MASK + {5, OperandInfo441}, // Inst #5139 = PseudoVLUXSEG4EI32_V_M1_MF4 + {8, OperandInfo442}, // Inst #5140 = PseudoVLUXSEG4EI32_V_M1_MF4_MASK + {5, OperandInfo445}, // Inst #5141 = PseudoVLUXSEG4EI32_V_M2_M1 + {8, OperandInfo446}, // Inst #5142 = PseudoVLUXSEG4EI32_V_M2_M1_MASK + {5, OperandInfo447}, // Inst #5143 = PseudoVLUXSEG4EI32_V_M2_M2 + {8, OperandInfo448}, // Inst #5144 = PseudoVLUXSEG4EI32_V_M2_M2_MASK + {5, OperandInfo445}, // Inst #5145 = PseudoVLUXSEG4EI32_V_M2_MF2 + {8, OperandInfo446}, // Inst #5146 = PseudoVLUXSEG4EI32_V_M2_MF2_MASK + {5, OperandInfo451}, // Inst #5147 = PseudoVLUXSEG4EI32_V_M4_M1 + {8, OperandInfo452}, // Inst #5148 = PseudoVLUXSEG4EI32_V_M4_M1_MASK + {5, OperandInfo449}, // Inst #5149 = PseudoVLUXSEG4EI32_V_M4_M2 + {8, OperandInfo450}, // Inst #5150 = PseudoVLUXSEG4EI32_V_M4_M2_MASK + {5, OperandInfo453}, // Inst #5151 = PseudoVLUXSEG4EI32_V_M8_M2 + {8, OperandInfo454}, // Inst #5152 = PseudoVLUXSEG4EI32_V_M8_M2_MASK + {5, OperandInfo441}, // Inst #5153 = PseudoVLUXSEG4EI32_V_MF2_M1 + {8, OperandInfo442}, // Inst #5154 = PseudoVLUXSEG4EI32_V_MF2_M1_MASK + {5, OperandInfo441}, // Inst #5155 = PseudoVLUXSEG4EI32_V_MF2_MF2 + {8, OperandInfo442}, // Inst #5156 = PseudoVLUXSEG4EI32_V_MF2_MF2_MASK + {5, OperandInfo441}, // Inst #5157 = PseudoVLUXSEG4EI32_V_MF2_MF4 + {8, OperandInfo442}, // Inst #5158 = PseudoVLUXSEG4EI32_V_MF2_MF4_MASK + {5, OperandInfo441}, // Inst #5159 = PseudoVLUXSEG4EI32_V_MF2_MF8 + {8, OperandInfo442}, // Inst #5160 = PseudoVLUXSEG4EI32_V_MF2_MF8_MASK + {5, OperandInfo441}, // Inst #5161 = PseudoVLUXSEG4EI64_V_M1_M1 + {8, OperandInfo442}, // Inst #5162 = PseudoVLUXSEG4EI64_V_M1_M1_MASK + {5, OperandInfo441}, // Inst #5163 = PseudoVLUXSEG4EI64_V_M1_MF2 + {8, OperandInfo442}, // Inst #5164 = PseudoVLUXSEG4EI64_V_M1_MF2_MASK + {5, OperandInfo441}, // Inst #5165 = PseudoVLUXSEG4EI64_V_M1_MF4 + {8, OperandInfo442}, // Inst #5166 = PseudoVLUXSEG4EI64_V_M1_MF4_MASK + {5, OperandInfo441}, // Inst #5167 = PseudoVLUXSEG4EI64_V_M1_MF8 + {8, OperandInfo442}, // Inst #5168 = PseudoVLUXSEG4EI64_V_M1_MF8_MASK + {5, OperandInfo445}, // Inst #5169 = PseudoVLUXSEG4EI64_V_M2_M1 + {8, OperandInfo446}, // Inst #5170 = PseudoVLUXSEG4EI64_V_M2_M1_MASK + {5, OperandInfo447}, // Inst #5171 = PseudoVLUXSEG4EI64_V_M2_M2 + {8, OperandInfo448}, // Inst #5172 = PseudoVLUXSEG4EI64_V_M2_M2_MASK + {5, OperandInfo445}, // Inst #5173 = PseudoVLUXSEG4EI64_V_M2_MF2 + {8, OperandInfo446}, // Inst #5174 = PseudoVLUXSEG4EI64_V_M2_MF2_MASK + {5, OperandInfo445}, // Inst #5175 = PseudoVLUXSEG4EI64_V_M2_MF4 + {8, OperandInfo446}, // Inst #5176 = PseudoVLUXSEG4EI64_V_M2_MF4_MASK + {5, OperandInfo451}, // Inst #5177 = PseudoVLUXSEG4EI64_V_M4_M1 + {8, OperandInfo452}, // Inst #5178 = PseudoVLUXSEG4EI64_V_M4_M1_MASK + {5, OperandInfo449}, // Inst #5179 = PseudoVLUXSEG4EI64_V_M4_M2 + {8, OperandInfo450}, // Inst #5180 = PseudoVLUXSEG4EI64_V_M4_M2_MASK + {5, OperandInfo451}, // Inst #5181 = PseudoVLUXSEG4EI64_V_M4_MF2 + {8, OperandInfo452}, // Inst #5182 = PseudoVLUXSEG4EI64_V_M4_MF2_MASK + {5, OperandInfo455}, // Inst #5183 = PseudoVLUXSEG4EI64_V_M8_M1 + {8, OperandInfo456}, // Inst #5184 = PseudoVLUXSEG4EI64_V_M8_M1_MASK + {5, OperandInfo453}, // Inst #5185 = PseudoVLUXSEG4EI64_V_M8_M2 + {8, OperandInfo454}, // Inst #5186 = PseudoVLUXSEG4EI64_V_M8_M2_MASK + {5, OperandInfo441}, // Inst #5187 = PseudoVLUXSEG4EI8_V_M1_M1 + {8, OperandInfo442}, // Inst #5188 = PseudoVLUXSEG4EI8_V_M1_M1_MASK + {5, OperandInfo443}, // Inst #5189 = PseudoVLUXSEG4EI8_V_M1_M2 + {8, OperandInfo444}, // Inst #5190 = PseudoVLUXSEG4EI8_V_M1_M2_MASK + {5, OperandInfo447}, // Inst #5191 = PseudoVLUXSEG4EI8_V_M2_M2 + {8, OperandInfo448}, // Inst #5192 = PseudoVLUXSEG4EI8_V_M2_M2_MASK + {5, OperandInfo441}, // Inst #5193 = PseudoVLUXSEG4EI8_V_MF2_M1 + {8, OperandInfo442}, // Inst #5194 = PseudoVLUXSEG4EI8_V_MF2_M1_MASK + {5, OperandInfo443}, // Inst #5195 = PseudoVLUXSEG4EI8_V_MF2_M2 + {8, OperandInfo444}, // Inst #5196 = PseudoVLUXSEG4EI8_V_MF2_M2_MASK + {5, OperandInfo441}, // Inst #5197 = PseudoVLUXSEG4EI8_V_MF2_MF2 + {8, OperandInfo442}, // Inst #5198 = PseudoVLUXSEG4EI8_V_MF2_MF2_MASK + {5, OperandInfo441}, // Inst #5199 = PseudoVLUXSEG4EI8_V_MF4_M1 + {8, OperandInfo442}, // Inst #5200 = PseudoVLUXSEG4EI8_V_MF4_M1_MASK + {5, OperandInfo443}, // Inst #5201 = PseudoVLUXSEG4EI8_V_MF4_M2 + {8, OperandInfo444}, // Inst #5202 = PseudoVLUXSEG4EI8_V_MF4_M2_MASK + {5, OperandInfo441}, // Inst #5203 = PseudoVLUXSEG4EI8_V_MF4_MF2 + {8, OperandInfo442}, // Inst #5204 = PseudoVLUXSEG4EI8_V_MF4_MF2_MASK + {5, OperandInfo441}, // Inst #5205 = PseudoVLUXSEG4EI8_V_MF4_MF4 + {8, OperandInfo442}, // Inst #5206 = PseudoVLUXSEG4EI8_V_MF4_MF4_MASK + {5, OperandInfo441}, // Inst #5207 = PseudoVLUXSEG4EI8_V_MF8_M1 + {8, OperandInfo442}, // Inst #5208 = PseudoVLUXSEG4EI8_V_MF8_M1_MASK + {5, OperandInfo441}, // Inst #5209 = PseudoVLUXSEG4EI8_V_MF8_MF2 + {8, OperandInfo442}, // Inst #5210 = PseudoVLUXSEG4EI8_V_MF8_MF2_MASK + {5, OperandInfo441}, // Inst #5211 = PseudoVLUXSEG4EI8_V_MF8_MF4 + {8, OperandInfo442}, // Inst #5212 = PseudoVLUXSEG4EI8_V_MF8_MF4_MASK + {5, OperandInfo441}, // Inst #5213 = PseudoVLUXSEG4EI8_V_MF8_MF8 + {8, OperandInfo442}, // Inst #5214 = PseudoVLUXSEG4EI8_V_MF8_MF8_MASK + {5, OperandInfo457}, // Inst #5215 = PseudoVLUXSEG5EI16_V_M1_M1 + {8, OperandInfo458}, // Inst #5216 = PseudoVLUXSEG5EI16_V_M1_M1_MASK + {5, OperandInfo457}, // Inst #5217 = PseudoVLUXSEG5EI16_V_M1_MF2 + {8, OperandInfo458}, // Inst #5218 = PseudoVLUXSEG5EI16_V_M1_MF2_MASK + {5, OperandInfo459}, // Inst #5219 = PseudoVLUXSEG5EI16_V_M2_M1 + {8, OperandInfo460}, // Inst #5220 = PseudoVLUXSEG5EI16_V_M2_M1_MASK + {5, OperandInfo457}, // Inst #5221 = PseudoVLUXSEG5EI16_V_MF2_M1 + {8, OperandInfo458}, // Inst #5222 = PseudoVLUXSEG5EI16_V_MF2_M1_MASK + {5, OperandInfo457}, // Inst #5223 = PseudoVLUXSEG5EI16_V_MF2_MF2 + {8, OperandInfo458}, // Inst #5224 = PseudoVLUXSEG5EI16_V_MF2_MF2_MASK + {5, OperandInfo457}, // Inst #5225 = PseudoVLUXSEG5EI16_V_MF2_MF4 + {8, OperandInfo458}, // Inst #5226 = PseudoVLUXSEG5EI16_V_MF2_MF4_MASK + {5, OperandInfo457}, // Inst #5227 = PseudoVLUXSEG5EI16_V_MF4_M1 + {8, OperandInfo458}, // Inst #5228 = PseudoVLUXSEG5EI16_V_MF4_M1_MASK + {5, OperandInfo457}, // Inst #5229 = PseudoVLUXSEG5EI16_V_MF4_MF2 + {8, OperandInfo458}, // Inst #5230 = PseudoVLUXSEG5EI16_V_MF4_MF2_MASK + {5, OperandInfo457}, // Inst #5231 = PseudoVLUXSEG5EI16_V_MF4_MF4 + {8, OperandInfo458}, // Inst #5232 = PseudoVLUXSEG5EI16_V_MF4_MF4_MASK + {5, OperandInfo457}, // Inst #5233 = PseudoVLUXSEG5EI16_V_MF4_MF8 + {8, OperandInfo458}, // Inst #5234 = PseudoVLUXSEG5EI16_V_MF4_MF8_MASK + {5, OperandInfo457}, // Inst #5235 = PseudoVLUXSEG5EI32_V_M1_M1 + {8, OperandInfo458}, // Inst #5236 = PseudoVLUXSEG5EI32_V_M1_M1_MASK + {5, OperandInfo457}, // Inst #5237 = PseudoVLUXSEG5EI32_V_M1_MF2 + {8, OperandInfo458}, // Inst #5238 = PseudoVLUXSEG5EI32_V_M1_MF2_MASK + {5, OperandInfo457}, // Inst #5239 = PseudoVLUXSEG5EI32_V_M1_MF4 + {8, OperandInfo458}, // Inst #5240 = PseudoVLUXSEG5EI32_V_M1_MF4_MASK + {5, OperandInfo459}, // Inst #5241 = PseudoVLUXSEG5EI32_V_M2_M1 + {8, OperandInfo460}, // Inst #5242 = PseudoVLUXSEG5EI32_V_M2_M1_MASK + {5, OperandInfo459}, // Inst #5243 = PseudoVLUXSEG5EI32_V_M2_MF2 + {8, OperandInfo460}, // Inst #5244 = PseudoVLUXSEG5EI32_V_M2_MF2_MASK + {5, OperandInfo461}, // Inst #5245 = PseudoVLUXSEG5EI32_V_M4_M1 + {8, OperandInfo462}, // Inst #5246 = PseudoVLUXSEG5EI32_V_M4_M1_MASK + {5, OperandInfo457}, // Inst #5247 = PseudoVLUXSEG5EI32_V_MF2_M1 + {8, OperandInfo458}, // Inst #5248 = PseudoVLUXSEG5EI32_V_MF2_M1_MASK + {5, OperandInfo457}, // Inst #5249 = PseudoVLUXSEG5EI32_V_MF2_MF2 + {8, OperandInfo458}, // Inst #5250 = PseudoVLUXSEG5EI32_V_MF2_MF2_MASK + {5, OperandInfo457}, // Inst #5251 = PseudoVLUXSEG5EI32_V_MF2_MF4 + {8, OperandInfo458}, // Inst #5252 = PseudoVLUXSEG5EI32_V_MF2_MF4_MASK + {5, OperandInfo457}, // Inst #5253 = PseudoVLUXSEG5EI32_V_MF2_MF8 + {8, OperandInfo458}, // Inst #5254 = PseudoVLUXSEG5EI32_V_MF2_MF8_MASK + {5, OperandInfo457}, // Inst #5255 = PseudoVLUXSEG5EI64_V_M1_M1 + {8, OperandInfo458}, // Inst #5256 = PseudoVLUXSEG5EI64_V_M1_M1_MASK + {5, OperandInfo457}, // Inst #5257 = PseudoVLUXSEG5EI64_V_M1_MF2 + {8, OperandInfo458}, // Inst #5258 = PseudoVLUXSEG5EI64_V_M1_MF2_MASK + {5, OperandInfo457}, // Inst #5259 = PseudoVLUXSEG5EI64_V_M1_MF4 + {8, OperandInfo458}, // Inst #5260 = PseudoVLUXSEG5EI64_V_M1_MF4_MASK + {5, OperandInfo457}, // Inst #5261 = PseudoVLUXSEG5EI64_V_M1_MF8 + {8, OperandInfo458}, // Inst #5262 = PseudoVLUXSEG5EI64_V_M1_MF8_MASK + {5, OperandInfo459}, // Inst #5263 = PseudoVLUXSEG5EI64_V_M2_M1 + {8, OperandInfo460}, // Inst #5264 = PseudoVLUXSEG5EI64_V_M2_M1_MASK + {5, OperandInfo459}, // Inst #5265 = PseudoVLUXSEG5EI64_V_M2_MF2 + {8, OperandInfo460}, // Inst #5266 = PseudoVLUXSEG5EI64_V_M2_MF2_MASK + {5, OperandInfo459}, // Inst #5267 = PseudoVLUXSEG5EI64_V_M2_MF4 + {8, OperandInfo460}, // Inst #5268 = PseudoVLUXSEG5EI64_V_M2_MF4_MASK + {5, OperandInfo461}, // Inst #5269 = PseudoVLUXSEG5EI64_V_M4_M1 + {8, OperandInfo462}, // Inst #5270 = PseudoVLUXSEG5EI64_V_M4_M1_MASK + {5, OperandInfo461}, // Inst #5271 = PseudoVLUXSEG5EI64_V_M4_MF2 + {8, OperandInfo462}, // Inst #5272 = PseudoVLUXSEG5EI64_V_M4_MF2_MASK + {5, OperandInfo463}, // Inst #5273 = PseudoVLUXSEG5EI64_V_M8_M1 + {8, OperandInfo464}, // Inst #5274 = PseudoVLUXSEG5EI64_V_M8_M1_MASK + {5, OperandInfo457}, // Inst #5275 = PseudoVLUXSEG5EI8_V_M1_M1 + {8, OperandInfo458}, // Inst #5276 = PseudoVLUXSEG5EI8_V_M1_M1_MASK + {5, OperandInfo457}, // Inst #5277 = PseudoVLUXSEG5EI8_V_MF2_M1 + {8, OperandInfo458}, // Inst #5278 = PseudoVLUXSEG5EI8_V_MF2_M1_MASK + {5, OperandInfo457}, // Inst #5279 = PseudoVLUXSEG5EI8_V_MF2_MF2 + {8, OperandInfo458}, // Inst #5280 = PseudoVLUXSEG5EI8_V_MF2_MF2_MASK + {5, OperandInfo457}, // Inst #5281 = PseudoVLUXSEG5EI8_V_MF4_M1 + {8, OperandInfo458}, // Inst #5282 = PseudoVLUXSEG5EI8_V_MF4_M1_MASK + {5, OperandInfo457}, // Inst #5283 = PseudoVLUXSEG5EI8_V_MF4_MF2 + {8, OperandInfo458}, // Inst #5284 = PseudoVLUXSEG5EI8_V_MF4_MF2_MASK + {5, OperandInfo457}, // Inst #5285 = PseudoVLUXSEG5EI8_V_MF4_MF4 + {8, OperandInfo458}, // Inst #5286 = PseudoVLUXSEG5EI8_V_MF4_MF4_MASK + {5, OperandInfo457}, // Inst #5287 = PseudoVLUXSEG5EI8_V_MF8_M1 + {8, OperandInfo458}, // Inst #5288 = PseudoVLUXSEG5EI8_V_MF8_M1_MASK + {5, OperandInfo457}, // Inst #5289 = PseudoVLUXSEG5EI8_V_MF8_MF2 + {8, OperandInfo458}, // Inst #5290 = PseudoVLUXSEG5EI8_V_MF8_MF2_MASK + {5, OperandInfo457}, // Inst #5291 = PseudoVLUXSEG5EI8_V_MF8_MF4 + {8, OperandInfo458}, // Inst #5292 = PseudoVLUXSEG5EI8_V_MF8_MF4_MASK + {5, OperandInfo457}, // Inst #5293 = PseudoVLUXSEG5EI8_V_MF8_MF8 + {8, OperandInfo458}, // Inst #5294 = PseudoVLUXSEG5EI8_V_MF8_MF8_MASK + {5, OperandInfo465}, // Inst #5295 = PseudoVLUXSEG6EI16_V_M1_M1 + {8, OperandInfo466}, // Inst #5296 = PseudoVLUXSEG6EI16_V_M1_M1_MASK + {5, OperandInfo465}, // Inst #5297 = PseudoVLUXSEG6EI16_V_M1_MF2 + {8, OperandInfo466}, // Inst #5298 = PseudoVLUXSEG6EI16_V_M1_MF2_MASK + {5, OperandInfo467}, // Inst #5299 = PseudoVLUXSEG6EI16_V_M2_M1 + {8, OperandInfo468}, // Inst #5300 = PseudoVLUXSEG6EI16_V_M2_M1_MASK + {5, OperandInfo465}, // Inst #5301 = PseudoVLUXSEG6EI16_V_MF2_M1 + {8, OperandInfo466}, // Inst #5302 = PseudoVLUXSEG6EI16_V_MF2_M1_MASK + {5, OperandInfo465}, // Inst #5303 = PseudoVLUXSEG6EI16_V_MF2_MF2 + {8, OperandInfo466}, // Inst #5304 = PseudoVLUXSEG6EI16_V_MF2_MF2_MASK + {5, OperandInfo465}, // Inst #5305 = PseudoVLUXSEG6EI16_V_MF2_MF4 + {8, OperandInfo466}, // Inst #5306 = PseudoVLUXSEG6EI16_V_MF2_MF4_MASK + {5, OperandInfo465}, // Inst #5307 = PseudoVLUXSEG6EI16_V_MF4_M1 + {8, OperandInfo466}, // Inst #5308 = PseudoVLUXSEG6EI16_V_MF4_M1_MASK + {5, OperandInfo465}, // Inst #5309 = PseudoVLUXSEG6EI16_V_MF4_MF2 + {8, OperandInfo466}, // Inst #5310 = PseudoVLUXSEG6EI16_V_MF4_MF2_MASK + {5, OperandInfo465}, // Inst #5311 = PseudoVLUXSEG6EI16_V_MF4_MF4 + {8, OperandInfo466}, // Inst #5312 = PseudoVLUXSEG6EI16_V_MF4_MF4_MASK + {5, OperandInfo465}, // Inst #5313 = PseudoVLUXSEG6EI16_V_MF4_MF8 + {8, OperandInfo466}, // Inst #5314 = PseudoVLUXSEG6EI16_V_MF4_MF8_MASK + {5, OperandInfo465}, // Inst #5315 = PseudoVLUXSEG6EI32_V_M1_M1 + {8, OperandInfo466}, // Inst #5316 = PseudoVLUXSEG6EI32_V_M1_M1_MASK + {5, OperandInfo465}, // Inst #5317 = PseudoVLUXSEG6EI32_V_M1_MF2 + {8, OperandInfo466}, // Inst #5318 = PseudoVLUXSEG6EI32_V_M1_MF2_MASK + {5, OperandInfo465}, // Inst #5319 = PseudoVLUXSEG6EI32_V_M1_MF4 + {8, OperandInfo466}, // Inst #5320 = PseudoVLUXSEG6EI32_V_M1_MF4_MASK + {5, OperandInfo467}, // Inst #5321 = PseudoVLUXSEG6EI32_V_M2_M1 + {8, OperandInfo468}, // Inst #5322 = PseudoVLUXSEG6EI32_V_M2_M1_MASK + {5, OperandInfo467}, // Inst #5323 = PseudoVLUXSEG6EI32_V_M2_MF2 + {8, OperandInfo468}, // Inst #5324 = PseudoVLUXSEG6EI32_V_M2_MF2_MASK + {5, OperandInfo469}, // Inst #5325 = PseudoVLUXSEG6EI32_V_M4_M1 + {8, OperandInfo470}, // Inst #5326 = PseudoVLUXSEG6EI32_V_M4_M1_MASK + {5, OperandInfo465}, // Inst #5327 = PseudoVLUXSEG6EI32_V_MF2_M1 + {8, OperandInfo466}, // Inst #5328 = PseudoVLUXSEG6EI32_V_MF2_M1_MASK + {5, OperandInfo465}, // Inst #5329 = PseudoVLUXSEG6EI32_V_MF2_MF2 + {8, OperandInfo466}, // Inst #5330 = PseudoVLUXSEG6EI32_V_MF2_MF2_MASK + {5, OperandInfo465}, // Inst #5331 = PseudoVLUXSEG6EI32_V_MF2_MF4 + {8, OperandInfo466}, // Inst #5332 = PseudoVLUXSEG6EI32_V_MF2_MF4_MASK + {5, OperandInfo465}, // Inst #5333 = PseudoVLUXSEG6EI32_V_MF2_MF8 + {8, OperandInfo466}, // Inst #5334 = PseudoVLUXSEG6EI32_V_MF2_MF8_MASK + {5, OperandInfo465}, // Inst #5335 = PseudoVLUXSEG6EI64_V_M1_M1 + {8, OperandInfo466}, // Inst #5336 = PseudoVLUXSEG6EI64_V_M1_M1_MASK + {5, OperandInfo465}, // Inst #5337 = PseudoVLUXSEG6EI64_V_M1_MF2 + {8, OperandInfo466}, // Inst #5338 = PseudoVLUXSEG6EI64_V_M1_MF2_MASK + {5, OperandInfo465}, // Inst #5339 = PseudoVLUXSEG6EI64_V_M1_MF4 + {8, OperandInfo466}, // Inst #5340 = PseudoVLUXSEG6EI64_V_M1_MF4_MASK + {5, OperandInfo465}, // Inst #5341 = PseudoVLUXSEG6EI64_V_M1_MF8 + {8, OperandInfo466}, // Inst #5342 = PseudoVLUXSEG6EI64_V_M1_MF8_MASK + {5, OperandInfo467}, // Inst #5343 = PseudoVLUXSEG6EI64_V_M2_M1 + {8, OperandInfo468}, // Inst #5344 = PseudoVLUXSEG6EI64_V_M2_M1_MASK + {5, OperandInfo467}, // Inst #5345 = PseudoVLUXSEG6EI64_V_M2_MF2 + {8, OperandInfo468}, // Inst #5346 = PseudoVLUXSEG6EI64_V_M2_MF2_MASK + {5, OperandInfo467}, // Inst #5347 = PseudoVLUXSEG6EI64_V_M2_MF4 + {8, OperandInfo468}, // Inst #5348 = PseudoVLUXSEG6EI64_V_M2_MF4_MASK + {5, OperandInfo469}, // Inst #5349 = PseudoVLUXSEG6EI64_V_M4_M1 + {8, OperandInfo470}, // Inst #5350 = PseudoVLUXSEG6EI64_V_M4_M1_MASK + {5, OperandInfo469}, // Inst #5351 = PseudoVLUXSEG6EI64_V_M4_MF2 + {8, OperandInfo470}, // Inst #5352 = PseudoVLUXSEG6EI64_V_M4_MF2_MASK + {5, OperandInfo471}, // Inst #5353 = PseudoVLUXSEG6EI64_V_M8_M1 + {8, OperandInfo472}, // Inst #5354 = PseudoVLUXSEG6EI64_V_M8_M1_MASK + {5, OperandInfo465}, // Inst #5355 = PseudoVLUXSEG6EI8_V_M1_M1 + {8, OperandInfo466}, // Inst #5356 = PseudoVLUXSEG6EI8_V_M1_M1_MASK + {5, OperandInfo465}, // Inst #5357 = PseudoVLUXSEG6EI8_V_MF2_M1 + {8, OperandInfo466}, // Inst #5358 = PseudoVLUXSEG6EI8_V_MF2_M1_MASK + {5, OperandInfo465}, // Inst #5359 = PseudoVLUXSEG6EI8_V_MF2_MF2 + {8, OperandInfo466}, // Inst #5360 = PseudoVLUXSEG6EI8_V_MF2_MF2_MASK + {5, OperandInfo465}, // Inst #5361 = PseudoVLUXSEG6EI8_V_MF4_M1 + {8, OperandInfo466}, // Inst #5362 = PseudoVLUXSEG6EI8_V_MF4_M1_MASK + {5, OperandInfo465}, // Inst #5363 = PseudoVLUXSEG6EI8_V_MF4_MF2 + {8, OperandInfo466}, // Inst #5364 = PseudoVLUXSEG6EI8_V_MF4_MF2_MASK + {5, OperandInfo465}, // Inst #5365 = PseudoVLUXSEG6EI8_V_MF4_MF4 + {8, OperandInfo466}, // Inst #5366 = PseudoVLUXSEG6EI8_V_MF4_MF4_MASK + {5, OperandInfo465}, // Inst #5367 = PseudoVLUXSEG6EI8_V_MF8_M1 + {8, OperandInfo466}, // Inst #5368 = PseudoVLUXSEG6EI8_V_MF8_M1_MASK + {5, OperandInfo465}, // Inst #5369 = PseudoVLUXSEG6EI8_V_MF8_MF2 + {8, OperandInfo466}, // Inst #5370 = PseudoVLUXSEG6EI8_V_MF8_MF2_MASK + {5, OperandInfo465}, // Inst #5371 = PseudoVLUXSEG6EI8_V_MF8_MF4 + {8, OperandInfo466}, // Inst #5372 = PseudoVLUXSEG6EI8_V_MF8_MF4_MASK + {5, OperandInfo465}, // Inst #5373 = PseudoVLUXSEG6EI8_V_MF8_MF8 + {8, OperandInfo466}, // Inst #5374 = PseudoVLUXSEG6EI8_V_MF8_MF8_MASK + {5, OperandInfo473}, // Inst #5375 = PseudoVLUXSEG7EI16_V_M1_M1 + {8, OperandInfo474}, // Inst #5376 = PseudoVLUXSEG7EI16_V_M1_M1_MASK + {5, OperandInfo473}, // Inst #5377 = PseudoVLUXSEG7EI16_V_M1_MF2 + {8, OperandInfo474}, // Inst #5378 = PseudoVLUXSEG7EI16_V_M1_MF2_MASK + {5, OperandInfo475}, // Inst #5379 = PseudoVLUXSEG7EI16_V_M2_M1 + {8, OperandInfo476}, // Inst #5380 = PseudoVLUXSEG7EI16_V_M2_M1_MASK + {5, OperandInfo473}, // Inst #5381 = PseudoVLUXSEG7EI16_V_MF2_M1 + {8, OperandInfo474}, // Inst #5382 = PseudoVLUXSEG7EI16_V_MF2_M1_MASK + {5, OperandInfo473}, // Inst #5383 = PseudoVLUXSEG7EI16_V_MF2_MF2 + {8, OperandInfo474}, // Inst #5384 = PseudoVLUXSEG7EI16_V_MF2_MF2_MASK + {5, OperandInfo473}, // Inst #5385 = PseudoVLUXSEG7EI16_V_MF2_MF4 + {8, OperandInfo474}, // Inst #5386 = PseudoVLUXSEG7EI16_V_MF2_MF4_MASK + {5, OperandInfo473}, // Inst #5387 = PseudoVLUXSEG7EI16_V_MF4_M1 + {8, OperandInfo474}, // Inst #5388 = PseudoVLUXSEG7EI16_V_MF4_M1_MASK + {5, OperandInfo473}, // Inst #5389 = PseudoVLUXSEG7EI16_V_MF4_MF2 + {8, OperandInfo474}, // Inst #5390 = PseudoVLUXSEG7EI16_V_MF4_MF2_MASK + {5, OperandInfo473}, // Inst #5391 = PseudoVLUXSEG7EI16_V_MF4_MF4 + {8, OperandInfo474}, // Inst #5392 = PseudoVLUXSEG7EI16_V_MF4_MF4_MASK + {5, OperandInfo473}, // Inst #5393 = PseudoVLUXSEG7EI16_V_MF4_MF8 + {8, OperandInfo474}, // Inst #5394 = PseudoVLUXSEG7EI16_V_MF4_MF8_MASK + {5, OperandInfo473}, // Inst #5395 = PseudoVLUXSEG7EI32_V_M1_M1 + {8, OperandInfo474}, // Inst #5396 = PseudoVLUXSEG7EI32_V_M1_M1_MASK + {5, OperandInfo473}, // Inst #5397 = PseudoVLUXSEG7EI32_V_M1_MF2 + {8, OperandInfo474}, // Inst #5398 = PseudoVLUXSEG7EI32_V_M1_MF2_MASK + {5, OperandInfo473}, // Inst #5399 = PseudoVLUXSEG7EI32_V_M1_MF4 + {8, OperandInfo474}, // Inst #5400 = PseudoVLUXSEG7EI32_V_M1_MF4_MASK + {5, OperandInfo475}, // Inst #5401 = PseudoVLUXSEG7EI32_V_M2_M1 + {8, OperandInfo476}, // Inst #5402 = PseudoVLUXSEG7EI32_V_M2_M1_MASK + {5, OperandInfo475}, // Inst #5403 = PseudoVLUXSEG7EI32_V_M2_MF2 + {8, OperandInfo476}, // Inst #5404 = PseudoVLUXSEG7EI32_V_M2_MF2_MASK + {5, OperandInfo477}, // Inst #5405 = PseudoVLUXSEG7EI32_V_M4_M1 + {8, OperandInfo478}, // Inst #5406 = PseudoVLUXSEG7EI32_V_M4_M1_MASK + {5, OperandInfo473}, // Inst #5407 = PseudoVLUXSEG7EI32_V_MF2_M1 + {8, OperandInfo474}, // Inst #5408 = PseudoVLUXSEG7EI32_V_MF2_M1_MASK + {5, OperandInfo473}, // Inst #5409 = PseudoVLUXSEG7EI32_V_MF2_MF2 + {8, OperandInfo474}, // Inst #5410 = PseudoVLUXSEG7EI32_V_MF2_MF2_MASK + {5, OperandInfo473}, // Inst #5411 = PseudoVLUXSEG7EI32_V_MF2_MF4 + {8, OperandInfo474}, // Inst #5412 = PseudoVLUXSEG7EI32_V_MF2_MF4_MASK + {5, OperandInfo473}, // Inst #5413 = PseudoVLUXSEG7EI32_V_MF2_MF8 + {8, OperandInfo474}, // Inst #5414 = PseudoVLUXSEG7EI32_V_MF2_MF8_MASK + {5, OperandInfo473}, // Inst #5415 = PseudoVLUXSEG7EI64_V_M1_M1 + {8, OperandInfo474}, // Inst #5416 = PseudoVLUXSEG7EI64_V_M1_M1_MASK + {5, OperandInfo473}, // Inst #5417 = PseudoVLUXSEG7EI64_V_M1_MF2 + {8, OperandInfo474}, // Inst #5418 = PseudoVLUXSEG7EI64_V_M1_MF2_MASK + {5, OperandInfo473}, // Inst #5419 = PseudoVLUXSEG7EI64_V_M1_MF4 + {8, OperandInfo474}, // Inst #5420 = PseudoVLUXSEG7EI64_V_M1_MF4_MASK + {5, OperandInfo473}, // Inst #5421 = PseudoVLUXSEG7EI64_V_M1_MF8 + {8, OperandInfo474}, // Inst #5422 = PseudoVLUXSEG7EI64_V_M1_MF8_MASK + {5, OperandInfo475}, // Inst #5423 = PseudoVLUXSEG7EI64_V_M2_M1 + {8, OperandInfo476}, // Inst #5424 = PseudoVLUXSEG7EI64_V_M2_M1_MASK + {5, OperandInfo475}, // Inst #5425 = PseudoVLUXSEG7EI64_V_M2_MF2 + {8, OperandInfo476}, // Inst #5426 = PseudoVLUXSEG7EI64_V_M2_MF2_MASK + {5, OperandInfo475}, // Inst #5427 = PseudoVLUXSEG7EI64_V_M2_MF4 + {8, OperandInfo476}, // Inst #5428 = PseudoVLUXSEG7EI64_V_M2_MF4_MASK + {5, OperandInfo477}, // Inst #5429 = PseudoVLUXSEG7EI64_V_M4_M1 + {8, OperandInfo478}, // Inst #5430 = PseudoVLUXSEG7EI64_V_M4_M1_MASK + {5, OperandInfo477}, // Inst #5431 = PseudoVLUXSEG7EI64_V_M4_MF2 + {8, OperandInfo478}, // Inst #5432 = PseudoVLUXSEG7EI64_V_M4_MF2_MASK + {5, OperandInfo479}, // Inst #5433 = PseudoVLUXSEG7EI64_V_M8_M1 + {8, OperandInfo480}, // Inst #5434 = PseudoVLUXSEG7EI64_V_M8_M1_MASK + {5, OperandInfo473}, // Inst #5435 = PseudoVLUXSEG7EI8_V_M1_M1 + {8, OperandInfo474}, // Inst #5436 = PseudoVLUXSEG7EI8_V_M1_M1_MASK + {5, OperandInfo473}, // Inst #5437 = PseudoVLUXSEG7EI8_V_MF2_M1 + {8, OperandInfo474}, // Inst #5438 = PseudoVLUXSEG7EI8_V_MF2_M1_MASK + {5, OperandInfo473}, // Inst #5439 = PseudoVLUXSEG7EI8_V_MF2_MF2 + {8, OperandInfo474}, // Inst #5440 = PseudoVLUXSEG7EI8_V_MF2_MF2_MASK + {5, OperandInfo473}, // Inst #5441 = PseudoVLUXSEG7EI8_V_MF4_M1 + {8, OperandInfo474}, // Inst #5442 = PseudoVLUXSEG7EI8_V_MF4_M1_MASK + {5, OperandInfo473}, // Inst #5443 = PseudoVLUXSEG7EI8_V_MF4_MF2 + {8, OperandInfo474}, // Inst #5444 = PseudoVLUXSEG7EI8_V_MF4_MF2_MASK + {5, OperandInfo473}, // Inst #5445 = PseudoVLUXSEG7EI8_V_MF4_MF4 + {8, OperandInfo474}, // Inst #5446 = PseudoVLUXSEG7EI8_V_MF4_MF4_MASK + {5, OperandInfo473}, // Inst #5447 = PseudoVLUXSEG7EI8_V_MF8_M1 + {8, OperandInfo474}, // Inst #5448 = PseudoVLUXSEG7EI8_V_MF8_M1_MASK + {5, OperandInfo473}, // Inst #5449 = PseudoVLUXSEG7EI8_V_MF8_MF2 + {8, OperandInfo474}, // Inst #5450 = PseudoVLUXSEG7EI8_V_MF8_MF2_MASK + {5, OperandInfo473}, // Inst #5451 = PseudoVLUXSEG7EI8_V_MF8_MF4 + {8, OperandInfo474}, // Inst #5452 = PseudoVLUXSEG7EI8_V_MF8_MF4_MASK + {5, OperandInfo473}, // Inst #5453 = PseudoVLUXSEG7EI8_V_MF8_MF8 + {8, OperandInfo474}, // Inst #5454 = PseudoVLUXSEG7EI8_V_MF8_MF8_MASK + {5, OperandInfo481}, // Inst #5455 = PseudoVLUXSEG8EI16_V_M1_M1 + {8, OperandInfo482}, // Inst #5456 = PseudoVLUXSEG8EI16_V_M1_M1_MASK + {5, OperandInfo481}, // Inst #5457 = PseudoVLUXSEG8EI16_V_M1_MF2 + {8, OperandInfo482}, // Inst #5458 = PseudoVLUXSEG8EI16_V_M1_MF2_MASK + {5, OperandInfo483}, // Inst #5459 = PseudoVLUXSEG8EI16_V_M2_M1 + {8, OperandInfo484}, // Inst #5460 = PseudoVLUXSEG8EI16_V_M2_M1_MASK + {5, OperandInfo481}, // Inst #5461 = PseudoVLUXSEG8EI16_V_MF2_M1 + {8, OperandInfo482}, // Inst #5462 = PseudoVLUXSEG8EI16_V_MF2_M1_MASK + {5, OperandInfo481}, // Inst #5463 = PseudoVLUXSEG8EI16_V_MF2_MF2 + {8, OperandInfo482}, // Inst #5464 = PseudoVLUXSEG8EI16_V_MF2_MF2_MASK + {5, OperandInfo481}, // Inst #5465 = PseudoVLUXSEG8EI16_V_MF2_MF4 + {8, OperandInfo482}, // Inst #5466 = PseudoVLUXSEG8EI16_V_MF2_MF4_MASK + {5, OperandInfo481}, // Inst #5467 = PseudoVLUXSEG8EI16_V_MF4_M1 + {8, OperandInfo482}, // Inst #5468 = PseudoVLUXSEG8EI16_V_MF4_M1_MASK + {5, OperandInfo481}, // Inst #5469 = PseudoVLUXSEG8EI16_V_MF4_MF2 + {8, OperandInfo482}, // Inst #5470 = PseudoVLUXSEG8EI16_V_MF4_MF2_MASK + {5, OperandInfo481}, // Inst #5471 = PseudoVLUXSEG8EI16_V_MF4_MF4 + {8, OperandInfo482}, // Inst #5472 = PseudoVLUXSEG8EI16_V_MF4_MF4_MASK + {5, OperandInfo481}, // Inst #5473 = PseudoVLUXSEG8EI16_V_MF4_MF8 + {8, OperandInfo482}, // Inst #5474 = PseudoVLUXSEG8EI16_V_MF4_MF8_MASK + {5, OperandInfo481}, // Inst #5475 = PseudoVLUXSEG8EI32_V_M1_M1 + {8, OperandInfo482}, // Inst #5476 = PseudoVLUXSEG8EI32_V_M1_M1_MASK + {5, OperandInfo481}, // Inst #5477 = PseudoVLUXSEG8EI32_V_M1_MF2 + {8, OperandInfo482}, // Inst #5478 = PseudoVLUXSEG8EI32_V_M1_MF2_MASK + {5, OperandInfo481}, // Inst #5479 = PseudoVLUXSEG8EI32_V_M1_MF4 + {8, OperandInfo482}, // Inst #5480 = PseudoVLUXSEG8EI32_V_M1_MF4_MASK + {5, OperandInfo483}, // Inst #5481 = PseudoVLUXSEG8EI32_V_M2_M1 + {8, OperandInfo484}, // Inst #5482 = PseudoVLUXSEG8EI32_V_M2_M1_MASK + {5, OperandInfo483}, // Inst #5483 = PseudoVLUXSEG8EI32_V_M2_MF2 + {8, OperandInfo484}, // Inst #5484 = PseudoVLUXSEG8EI32_V_M2_MF2_MASK + {5, OperandInfo485}, // Inst #5485 = PseudoVLUXSEG8EI32_V_M4_M1 + {8, OperandInfo486}, // Inst #5486 = PseudoVLUXSEG8EI32_V_M4_M1_MASK + {5, OperandInfo481}, // Inst #5487 = PseudoVLUXSEG8EI32_V_MF2_M1 + {8, OperandInfo482}, // Inst #5488 = PseudoVLUXSEG8EI32_V_MF2_M1_MASK + {5, OperandInfo481}, // Inst #5489 = PseudoVLUXSEG8EI32_V_MF2_MF2 + {8, OperandInfo482}, // Inst #5490 = PseudoVLUXSEG8EI32_V_MF2_MF2_MASK + {5, OperandInfo481}, // Inst #5491 = PseudoVLUXSEG8EI32_V_MF2_MF4 + {8, OperandInfo482}, // Inst #5492 = PseudoVLUXSEG8EI32_V_MF2_MF4_MASK + {5, OperandInfo481}, // Inst #5493 = PseudoVLUXSEG8EI32_V_MF2_MF8 + {8, OperandInfo482}, // Inst #5494 = PseudoVLUXSEG8EI32_V_MF2_MF8_MASK + {5, OperandInfo481}, // Inst #5495 = PseudoVLUXSEG8EI64_V_M1_M1 + {8, OperandInfo482}, // Inst #5496 = PseudoVLUXSEG8EI64_V_M1_M1_MASK + {5, OperandInfo481}, // Inst #5497 = PseudoVLUXSEG8EI64_V_M1_MF2 + {8, OperandInfo482}, // Inst #5498 = PseudoVLUXSEG8EI64_V_M1_MF2_MASK + {5, OperandInfo481}, // Inst #5499 = PseudoVLUXSEG8EI64_V_M1_MF4 + {8, OperandInfo482}, // Inst #5500 = PseudoVLUXSEG8EI64_V_M1_MF4_MASK + {5, OperandInfo481}, // Inst #5501 = PseudoVLUXSEG8EI64_V_M1_MF8 + {8, OperandInfo482}, // Inst #5502 = PseudoVLUXSEG8EI64_V_M1_MF8_MASK + {5, OperandInfo483}, // Inst #5503 = PseudoVLUXSEG8EI64_V_M2_M1 + {8, OperandInfo484}, // Inst #5504 = PseudoVLUXSEG8EI64_V_M2_M1_MASK + {5, OperandInfo483}, // Inst #5505 = PseudoVLUXSEG8EI64_V_M2_MF2 + {8, OperandInfo484}, // Inst #5506 = PseudoVLUXSEG8EI64_V_M2_MF2_MASK + {5, OperandInfo483}, // Inst #5507 = PseudoVLUXSEG8EI64_V_M2_MF4 + {8, OperandInfo484}, // Inst #5508 = PseudoVLUXSEG8EI64_V_M2_MF4_MASK + {5, OperandInfo485}, // Inst #5509 = PseudoVLUXSEG8EI64_V_M4_M1 + {8, OperandInfo486}, // Inst #5510 = PseudoVLUXSEG8EI64_V_M4_M1_MASK + {5, OperandInfo485}, // Inst #5511 = PseudoVLUXSEG8EI64_V_M4_MF2 + {8, OperandInfo486}, // Inst #5512 = PseudoVLUXSEG8EI64_V_M4_MF2_MASK + {5, OperandInfo487}, // Inst #5513 = PseudoVLUXSEG8EI64_V_M8_M1 + {8, OperandInfo488}, // Inst #5514 = PseudoVLUXSEG8EI64_V_M8_M1_MASK + {5, OperandInfo481}, // Inst #5515 = PseudoVLUXSEG8EI8_V_M1_M1 + {8, OperandInfo482}, // Inst #5516 = PseudoVLUXSEG8EI8_V_M1_M1_MASK + {5, OperandInfo481}, // Inst #5517 = PseudoVLUXSEG8EI8_V_MF2_M1 + {8, OperandInfo482}, // Inst #5518 = PseudoVLUXSEG8EI8_V_MF2_M1_MASK + {5, OperandInfo481}, // Inst #5519 = PseudoVLUXSEG8EI8_V_MF2_MF2 + {8, OperandInfo482}, // Inst #5520 = PseudoVLUXSEG8EI8_V_MF2_MF2_MASK + {5, OperandInfo481}, // Inst #5521 = PseudoVLUXSEG8EI8_V_MF4_M1 + {8, OperandInfo482}, // Inst #5522 = PseudoVLUXSEG8EI8_V_MF4_M1_MASK + {5, OperandInfo481}, // Inst #5523 = PseudoVLUXSEG8EI8_V_MF4_MF2 + {8, OperandInfo482}, // Inst #5524 = PseudoVLUXSEG8EI8_V_MF4_MF2_MASK + {5, OperandInfo481}, // Inst #5525 = PseudoVLUXSEG8EI8_V_MF4_MF4 + {8, OperandInfo482}, // Inst #5526 = PseudoVLUXSEG8EI8_V_MF4_MF4_MASK + {5, OperandInfo481}, // Inst #5527 = PseudoVLUXSEG8EI8_V_MF8_M1 + {8, OperandInfo482}, // Inst #5528 = PseudoVLUXSEG8EI8_V_MF8_M1_MASK + {5, OperandInfo481}, // Inst #5529 = PseudoVLUXSEG8EI8_V_MF8_MF2 + {8, OperandInfo482}, // Inst #5530 = PseudoVLUXSEG8EI8_V_MF8_MF2_MASK + {5, OperandInfo481}, // Inst #5531 = PseudoVLUXSEG8EI8_V_MF8_MF4 + {8, OperandInfo482}, // Inst #5532 = PseudoVLUXSEG8EI8_V_MF8_MF4_MASK + {5, OperandInfo481}, // Inst #5533 = PseudoVLUXSEG8EI8_V_MF8_MF8 + {8, OperandInfo482}, // Inst #5534 = PseudoVLUXSEG8EI8_V_MF8_MF8_MASK + {7, OperandInfo190}, // Inst #5535 = PseudoVMACC_VV_M1 + {7, OperandInfo191}, // Inst #5536 = PseudoVMACC_VV_M1_MASK + {7, OperandInfo192}, // Inst #5537 = PseudoVMACC_VV_M2 + {7, OperandInfo193}, // Inst #5538 = PseudoVMACC_VV_M2_MASK + {7, OperandInfo194}, // Inst #5539 = PseudoVMACC_VV_M4 + {7, OperandInfo195}, // Inst #5540 = PseudoVMACC_VV_M4_MASK + {7, OperandInfo196}, // Inst #5541 = PseudoVMACC_VV_M8 + {7, OperandInfo197}, // Inst #5542 = PseudoVMACC_VV_M8_MASK + {7, OperandInfo190}, // Inst #5543 = PseudoVMACC_VV_MF2 + {7, OperandInfo191}, // Inst #5544 = PseudoVMACC_VV_MF2_MASK + {7, OperandInfo190}, // Inst #5545 = PseudoVMACC_VV_MF4 + {7, OperandInfo191}, // Inst #5546 = PseudoVMACC_VV_MF4_MASK + {7, OperandInfo190}, // Inst #5547 = PseudoVMACC_VV_MF8 + {7, OperandInfo191}, // Inst #5548 = PseudoVMACC_VV_MF8_MASK + {7, OperandInfo541}, // Inst #5549 = PseudoVMACC_VX_M1 + {7, OperandInfo542}, // Inst #5550 = PseudoVMACC_VX_M1_MASK + {7, OperandInfo543}, // Inst #5551 = PseudoVMACC_VX_M2 + {7, OperandInfo544}, // Inst #5552 = PseudoVMACC_VX_M2_MASK + {7, OperandInfo545}, // Inst #5553 = PseudoVMACC_VX_M4 + {7, OperandInfo546}, // Inst #5554 = PseudoVMACC_VX_M4_MASK + {7, OperandInfo547}, // Inst #5555 = PseudoVMACC_VX_M8 + {7, OperandInfo548}, // Inst #5556 = PseudoVMACC_VX_M8_MASK + {7, OperandInfo541}, // Inst #5557 = PseudoVMACC_VX_MF2 + {7, OperandInfo542}, // Inst #5558 = PseudoVMACC_VX_MF2_MASK + {7, OperandInfo541}, // Inst #5559 = PseudoVMACC_VX_MF4 + {7, OperandInfo542}, // Inst #5560 = PseudoVMACC_VX_MF4_MASK + {7, OperandInfo541}, // Inst #5561 = PseudoVMACC_VX_MF8 + {7, OperandInfo542}, // Inst #5562 = PseudoVMACC_VX_MF8_MASK + {6, OperandInfo549}, // Inst #5563 = PseudoVMADC_VIM_M1 + {6, OperandInfo550}, // Inst #5564 = PseudoVMADC_VIM_M2 + {6, OperandInfo551}, // Inst #5565 = PseudoVMADC_VIM_M4 + {6, OperandInfo552}, // Inst #5566 = PseudoVMADC_VIM_M8 + {6, OperandInfo549}, // Inst #5567 = PseudoVMADC_VIM_MF2 + {6, OperandInfo549}, // Inst #5568 = PseudoVMADC_VIM_MF4 + {6, OperandInfo549}, // Inst #5569 = PseudoVMADC_VIM_MF8 + {5, OperandInfo553}, // Inst #5570 = PseudoVMADC_VI_M1 + {5, OperandInfo554}, // Inst #5571 = PseudoVMADC_VI_M2 + {5, OperandInfo555}, // Inst #5572 = PseudoVMADC_VI_M4 + {5, OperandInfo556}, // Inst #5573 = PseudoVMADC_VI_M8 + {5, OperandInfo553}, // Inst #5574 = PseudoVMADC_VI_MF2 + {5, OperandInfo553}, // Inst #5575 = PseudoVMADC_VI_MF4 + {5, OperandInfo553}, // Inst #5576 = PseudoVMADC_VI_MF8 + {6, OperandInfo557}, // Inst #5577 = PseudoVMADC_VVM_M1 + {6, OperandInfo558}, // Inst #5578 = PseudoVMADC_VVM_M2 + {6, OperandInfo559}, // Inst #5579 = PseudoVMADC_VVM_M4 + {6, OperandInfo560}, // Inst #5580 = PseudoVMADC_VVM_M8 + {6, OperandInfo557}, // Inst #5581 = PseudoVMADC_VVM_MF2 + {6, OperandInfo557}, // Inst #5582 = PseudoVMADC_VVM_MF4 + {6, OperandInfo557}, // Inst #5583 = PseudoVMADC_VVM_MF8 + {5, OperandInfo303}, // Inst #5584 = PseudoVMADC_VV_M1 + {5, OperandInfo561}, // Inst #5585 = PseudoVMADC_VV_M2 + {5, OperandInfo562}, // Inst #5586 = PseudoVMADC_VV_M4 + {5, OperandInfo563}, // Inst #5587 = PseudoVMADC_VV_M8 + {5, OperandInfo303}, // Inst #5588 = PseudoVMADC_VV_MF2 + {5, OperandInfo303}, // Inst #5589 = PseudoVMADC_VV_MF4 + {5, OperandInfo303}, // Inst #5590 = PseudoVMADC_VV_MF8 + {6, OperandInfo564}, // Inst #5591 = PseudoVMADC_VXM_M1 + {6, OperandInfo565}, // Inst #5592 = PseudoVMADC_VXM_M2 + {6, OperandInfo566}, // Inst #5593 = PseudoVMADC_VXM_M4 + {6, OperandInfo567}, // Inst #5594 = PseudoVMADC_VXM_M8 + {6, OperandInfo564}, // Inst #5595 = PseudoVMADC_VXM_MF2 + {6, OperandInfo564}, // Inst #5596 = PseudoVMADC_VXM_MF4 + {6, OperandInfo564}, // Inst #5597 = PseudoVMADC_VXM_MF8 + {5, OperandInfo568}, // Inst #5598 = PseudoVMADC_VX_M1 + {5, OperandInfo569}, // Inst #5599 = PseudoVMADC_VX_M2 + {5, OperandInfo570}, // Inst #5600 = PseudoVMADC_VX_M4 + {5, OperandInfo571}, // Inst #5601 = PseudoVMADC_VX_M8 + {5, OperandInfo568}, // Inst #5602 = PseudoVMADC_VX_MF2 + {5, OperandInfo568}, // Inst #5603 = PseudoVMADC_VX_MF4 + {5, OperandInfo568}, // Inst #5604 = PseudoVMADC_VX_MF8 + {7, OperandInfo190}, // Inst #5605 = PseudoVMADD_VV_M1 + {7, OperandInfo191}, // Inst #5606 = PseudoVMADD_VV_M1_MASK + {7, OperandInfo192}, // Inst #5607 = PseudoVMADD_VV_M2 + {7, OperandInfo193}, // Inst #5608 = PseudoVMADD_VV_M2_MASK + {7, OperandInfo194}, // Inst #5609 = PseudoVMADD_VV_M4 + {7, OperandInfo195}, // Inst #5610 = PseudoVMADD_VV_M4_MASK + {7, OperandInfo196}, // Inst #5611 = PseudoVMADD_VV_M8 + {7, OperandInfo197}, // Inst #5612 = PseudoVMADD_VV_M8_MASK + {7, OperandInfo190}, // Inst #5613 = PseudoVMADD_VV_MF2 + {7, OperandInfo191}, // Inst #5614 = PseudoVMADD_VV_MF2_MASK + {7, OperandInfo190}, // Inst #5615 = PseudoVMADD_VV_MF4 + {7, OperandInfo191}, // Inst #5616 = PseudoVMADD_VV_MF4_MASK + {7, OperandInfo190}, // Inst #5617 = PseudoVMADD_VV_MF8 + {7, OperandInfo191}, // Inst #5618 = PseudoVMADD_VV_MF8_MASK + {7, OperandInfo541}, // Inst #5619 = PseudoVMADD_VX_M1 + {7, OperandInfo542}, // Inst #5620 = PseudoVMADD_VX_M1_MASK + {7, OperandInfo543}, // Inst #5621 = PseudoVMADD_VX_M2 + {7, OperandInfo544}, // Inst #5622 = PseudoVMADD_VX_M2_MASK + {7, OperandInfo545}, // Inst #5623 = PseudoVMADD_VX_M4 + {7, OperandInfo546}, // Inst #5624 = PseudoVMADD_VX_M4_MASK + {7, OperandInfo547}, // Inst #5625 = PseudoVMADD_VX_M8 + {7, OperandInfo548}, // Inst #5626 = PseudoVMADD_VX_M8_MASK + {7, OperandInfo541}, // Inst #5627 = PseudoVMADD_VX_MF2 + {7, OperandInfo542}, // Inst #5628 = PseudoVMADD_VX_MF2_MASK + {7, OperandInfo541}, // Inst #5629 = PseudoVMADD_VX_MF4 + {7, OperandInfo542}, // Inst #5630 = PseudoVMADD_VX_MF4_MASK + {7, OperandInfo541}, // Inst #5631 = PseudoVMADD_VX_MF8 + {7, OperandInfo542}, // Inst #5632 = PseudoVMADD_VX_MF8_MASK + {5, OperandInfo62}, // Inst #5633 = PseudoVMANDN_MM_M1 + {5, OperandInfo62}, // Inst #5634 = PseudoVMANDN_MM_M2 + {5, OperandInfo62}, // Inst #5635 = PseudoVMANDN_MM_M4 + {5, OperandInfo62}, // Inst #5636 = PseudoVMANDN_MM_M8 + {5, OperandInfo62}, // Inst #5637 = PseudoVMANDN_MM_MF2 + {5, OperandInfo62}, // Inst #5638 = PseudoVMANDN_MM_MF4 + {5, OperandInfo62}, // Inst #5639 = PseudoVMANDN_MM_MF8 + {5, OperandInfo62}, // Inst #5640 = PseudoVMAND_MM_M1 + {5, OperandInfo62}, // Inst #5641 = PseudoVMAND_MM_M2 + {5, OperandInfo62}, // Inst #5642 = PseudoVMAND_MM_M4 + {5, OperandInfo62}, // Inst #5643 = PseudoVMAND_MM_M8 + {5, OperandInfo62}, // Inst #5644 = PseudoVMAND_MM_MF2 + {5, OperandInfo62}, // Inst #5645 = PseudoVMAND_MM_MF4 + {5, OperandInfo62}, // Inst #5646 = PseudoVMAND_MM_MF8 + {5, OperandInfo62}, // Inst #5647 = PseudoVMAXU_VV_M1 + {8, OperandInfo63}, // Inst #5648 = PseudoVMAXU_VV_M1_MASK + {5, OperandInfo64}, // Inst #5649 = PseudoVMAXU_VV_M2 + {8, OperandInfo65}, // Inst #5650 = PseudoVMAXU_VV_M2_MASK + {5, OperandInfo66}, // Inst #5651 = PseudoVMAXU_VV_M4 + {8, OperandInfo67}, // Inst #5652 = PseudoVMAXU_VV_M4_MASK + {5, OperandInfo68}, // Inst #5653 = PseudoVMAXU_VV_M8 + {8, OperandInfo69}, // Inst #5654 = PseudoVMAXU_VV_M8_MASK + {5, OperandInfo62}, // Inst #5655 = PseudoVMAXU_VV_MF2 + {8, OperandInfo63}, // Inst #5656 = PseudoVMAXU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #5657 = PseudoVMAXU_VV_MF4 + {8, OperandInfo63}, // Inst #5658 = PseudoVMAXU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #5659 = PseudoVMAXU_VV_MF8 + {8, OperandInfo63}, // Inst #5660 = PseudoVMAXU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #5661 = PseudoVMAXU_VX_M1 + {8, OperandInfo71}, // Inst #5662 = PseudoVMAXU_VX_M1_MASK + {5, OperandInfo72}, // Inst #5663 = PseudoVMAXU_VX_M2 + {8, OperandInfo73}, // Inst #5664 = PseudoVMAXU_VX_M2_MASK + {5, OperandInfo74}, // Inst #5665 = PseudoVMAXU_VX_M4 + {8, OperandInfo75}, // Inst #5666 = PseudoVMAXU_VX_M4_MASK + {5, OperandInfo76}, // Inst #5667 = PseudoVMAXU_VX_M8 + {8, OperandInfo77}, // Inst #5668 = PseudoVMAXU_VX_M8_MASK + {5, OperandInfo70}, // Inst #5669 = PseudoVMAXU_VX_MF2 + {8, OperandInfo71}, // Inst #5670 = PseudoVMAXU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #5671 = PseudoVMAXU_VX_MF4 + {8, OperandInfo71}, // Inst #5672 = PseudoVMAXU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #5673 = PseudoVMAXU_VX_MF8 + {8, OperandInfo71}, // Inst #5674 = PseudoVMAXU_VX_MF8_MASK + {5, OperandInfo62}, // Inst #5675 = PseudoVMAX_VV_M1 + {8, OperandInfo63}, // Inst #5676 = PseudoVMAX_VV_M1_MASK + {5, OperandInfo64}, // Inst #5677 = PseudoVMAX_VV_M2 + {8, OperandInfo65}, // Inst #5678 = PseudoVMAX_VV_M2_MASK + {5, OperandInfo66}, // Inst #5679 = PseudoVMAX_VV_M4 + {8, OperandInfo67}, // Inst #5680 = PseudoVMAX_VV_M4_MASK + {5, OperandInfo68}, // Inst #5681 = PseudoVMAX_VV_M8 + {8, OperandInfo69}, // Inst #5682 = PseudoVMAX_VV_M8_MASK + {5, OperandInfo62}, // Inst #5683 = PseudoVMAX_VV_MF2 + {8, OperandInfo63}, // Inst #5684 = PseudoVMAX_VV_MF2_MASK + {5, OperandInfo62}, // Inst #5685 = PseudoVMAX_VV_MF4 + {8, OperandInfo63}, // Inst #5686 = PseudoVMAX_VV_MF4_MASK + {5, OperandInfo62}, // Inst #5687 = PseudoVMAX_VV_MF8 + {8, OperandInfo63}, // Inst #5688 = PseudoVMAX_VV_MF8_MASK + {5, OperandInfo70}, // Inst #5689 = PseudoVMAX_VX_M1 + {8, OperandInfo71}, // Inst #5690 = PseudoVMAX_VX_M1_MASK + {5, OperandInfo72}, // Inst #5691 = PseudoVMAX_VX_M2 + {8, OperandInfo73}, // Inst #5692 = PseudoVMAX_VX_M2_MASK + {5, OperandInfo74}, // Inst #5693 = PseudoVMAX_VX_M4 + {8, OperandInfo75}, // Inst #5694 = PseudoVMAX_VX_M4_MASK + {5, OperandInfo76}, // Inst #5695 = PseudoVMAX_VX_M8 + {8, OperandInfo77}, // Inst #5696 = PseudoVMAX_VX_M8_MASK + {5, OperandInfo70}, // Inst #5697 = PseudoVMAX_VX_MF2 + {8, OperandInfo71}, // Inst #5698 = PseudoVMAX_VX_MF2_MASK + {5, OperandInfo70}, // Inst #5699 = PseudoVMAX_VX_MF4 + {8, OperandInfo71}, // Inst #5700 = PseudoVMAX_VX_MF4_MASK + {5, OperandInfo70}, // Inst #5701 = PseudoVMAX_VX_MF8 + {8, OperandInfo71}, // Inst #5702 = PseudoVMAX_VX_MF8_MASK + {3, OperandInfo345}, // Inst #5703 = PseudoVMCLR_M_B1 + {3, OperandInfo345}, // Inst #5704 = PseudoVMCLR_M_B16 + {3, OperandInfo345}, // Inst #5705 = PseudoVMCLR_M_B2 + {3, OperandInfo345}, // Inst #5706 = PseudoVMCLR_M_B32 + {3, OperandInfo345}, // Inst #5707 = PseudoVMCLR_M_B4 + {3, OperandInfo345}, // Inst #5708 = PseudoVMCLR_M_B64 + {3, OperandInfo345}, // Inst #5709 = PseudoVMCLR_M_B8 + {6, OperandInfo78}, // Inst #5710 = PseudoVMERGE_VIM_M1 + {6, OperandInfo79}, // Inst #5711 = PseudoVMERGE_VIM_M2 + {6, OperandInfo80}, // Inst #5712 = PseudoVMERGE_VIM_M4 + {6, OperandInfo81}, // Inst #5713 = PseudoVMERGE_VIM_M8 + {6, OperandInfo78}, // Inst #5714 = PseudoVMERGE_VIM_MF2 + {6, OperandInfo78}, // Inst #5715 = PseudoVMERGE_VIM_MF4 + {6, OperandInfo78}, // Inst #5716 = PseudoVMERGE_VIM_MF8 + {6, OperandInfo82}, // Inst #5717 = PseudoVMERGE_VVM_M1 + {6, OperandInfo83}, // Inst #5718 = PseudoVMERGE_VVM_M2 + {6, OperandInfo84}, // Inst #5719 = PseudoVMERGE_VVM_M4 + {6, OperandInfo85}, // Inst #5720 = PseudoVMERGE_VVM_M8 + {6, OperandInfo82}, // Inst #5721 = PseudoVMERGE_VVM_MF2 + {6, OperandInfo82}, // Inst #5722 = PseudoVMERGE_VVM_MF4 + {6, OperandInfo82}, // Inst #5723 = PseudoVMERGE_VVM_MF8 + {6, OperandInfo86}, // Inst #5724 = PseudoVMERGE_VXM_M1 + {6, OperandInfo87}, // Inst #5725 = PseudoVMERGE_VXM_M2 + {6, OperandInfo88}, // Inst #5726 = PseudoVMERGE_VXM_M4 + {6, OperandInfo89}, // Inst #5727 = PseudoVMERGE_VXM_M8 + {6, OperandInfo86}, // Inst #5728 = PseudoVMERGE_VXM_MF2 + {6, OperandInfo86}, // Inst #5729 = PseudoVMERGE_VXM_MF4 + {6, OperandInfo86}, // Inst #5730 = PseudoVMERGE_VXM_MF8 + {5, OperandInfo130}, // Inst #5731 = PseudoVMFEQ_VF16_M1 + {7, OperandInfo572}, // Inst #5732 = PseudoVMFEQ_VF16_M1_MASK + {5, OperandInfo573}, // Inst #5733 = PseudoVMFEQ_VF16_M2 + {7, OperandInfo574}, // Inst #5734 = PseudoVMFEQ_VF16_M2_MASK + {5, OperandInfo575}, // Inst #5735 = PseudoVMFEQ_VF16_M4 + {7, OperandInfo576}, // Inst #5736 = PseudoVMFEQ_VF16_M4_MASK + {5, OperandInfo577}, // Inst #5737 = PseudoVMFEQ_VF16_M8 + {7, OperandInfo578}, // Inst #5738 = PseudoVMFEQ_VF16_M8_MASK + {5, OperandInfo130}, // Inst #5739 = PseudoVMFEQ_VF16_MF2 + {7, OperandInfo572}, // Inst #5740 = PseudoVMFEQ_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #5741 = PseudoVMFEQ_VF16_MF4 + {7, OperandInfo572}, // Inst #5742 = PseudoVMFEQ_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #5743 = PseudoVMFEQ_VF16_MF8 + {7, OperandInfo572}, // Inst #5744 = PseudoVMFEQ_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #5745 = PseudoVMFEQ_VF32_M1 + {7, OperandInfo579}, // Inst #5746 = PseudoVMFEQ_VF32_M1_MASK + {5, OperandInfo580}, // Inst #5747 = PseudoVMFEQ_VF32_M2 + {7, OperandInfo581}, // Inst #5748 = PseudoVMFEQ_VF32_M2_MASK + {5, OperandInfo582}, // Inst #5749 = PseudoVMFEQ_VF32_M4 + {7, OperandInfo583}, // Inst #5750 = PseudoVMFEQ_VF32_M4_MASK + {5, OperandInfo584}, // Inst #5751 = PseudoVMFEQ_VF32_M8 + {7, OperandInfo585}, // Inst #5752 = PseudoVMFEQ_VF32_M8_MASK + {5, OperandInfo138}, // Inst #5753 = PseudoVMFEQ_VF32_MF2 + {7, OperandInfo579}, // Inst #5754 = PseudoVMFEQ_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #5755 = PseudoVMFEQ_VF32_MF4 + {7, OperandInfo579}, // Inst #5756 = PseudoVMFEQ_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #5757 = PseudoVMFEQ_VF32_MF8 + {7, OperandInfo579}, // Inst #5758 = PseudoVMFEQ_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #5759 = PseudoVMFEQ_VF64_M1 + {7, OperandInfo586}, // Inst #5760 = PseudoVMFEQ_VF64_M1_MASK + {5, OperandInfo587}, // Inst #5761 = PseudoVMFEQ_VF64_M2 + {7, OperandInfo588}, // Inst #5762 = PseudoVMFEQ_VF64_M2_MASK + {5, OperandInfo589}, // Inst #5763 = PseudoVMFEQ_VF64_M4 + {7, OperandInfo590}, // Inst #5764 = PseudoVMFEQ_VF64_M4_MASK + {5, OperandInfo591}, // Inst #5765 = PseudoVMFEQ_VF64_M8 + {7, OperandInfo592}, // Inst #5766 = PseudoVMFEQ_VF64_M8_MASK + {5, OperandInfo146}, // Inst #5767 = PseudoVMFEQ_VF64_MF2 + {7, OperandInfo586}, // Inst #5768 = PseudoVMFEQ_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #5769 = PseudoVMFEQ_VF64_MF4 + {7, OperandInfo586}, // Inst #5770 = PseudoVMFEQ_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #5771 = PseudoVMFEQ_VF64_MF8 + {7, OperandInfo586}, // Inst #5772 = PseudoVMFEQ_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #5773 = PseudoVMFEQ_VV_M1 + {7, OperandInfo593}, // Inst #5774 = PseudoVMFEQ_VV_M1_MASK + {5, OperandInfo561}, // Inst #5775 = PseudoVMFEQ_VV_M2 + {7, OperandInfo594}, // Inst #5776 = PseudoVMFEQ_VV_M2_MASK + {5, OperandInfo562}, // Inst #5777 = PseudoVMFEQ_VV_M4 + {7, OperandInfo595}, // Inst #5778 = PseudoVMFEQ_VV_M4_MASK + {5, OperandInfo563}, // Inst #5779 = PseudoVMFEQ_VV_M8 + {7, OperandInfo596}, // Inst #5780 = PseudoVMFEQ_VV_M8_MASK + {5, OperandInfo62}, // Inst #5781 = PseudoVMFEQ_VV_MF2 + {7, OperandInfo593}, // Inst #5782 = PseudoVMFEQ_VV_MF2_MASK + {5, OperandInfo62}, // Inst #5783 = PseudoVMFEQ_VV_MF4 + {7, OperandInfo593}, // Inst #5784 = PseudoVMFEQ_VV_MF4_MASK + {5, OperandInfo62}, // Inst #5785 = PseudoVMFEQ_VV_MF8 + {7, OperandInfo593}, // Inst #5786 = PseudoVMFEQ_VV_MF8_MASK + {5, OperandInfo130}, // Inst #5787 = PseudoVMFGE_VF16_M1 + {7, OperandInfo572}, // Inst #5788 = PseudoVMFGE_VF16_M1_MASK + {5, OperandInfo573}, // Inst #5789 = PseudoVMFGE_VF16_M2 + {7, OperandInfo574}, // Inst #5790 = PseudoVMFGE_VF16_M2_MASK + {5, OperandInfo575}, // Inst #5791 = PseudoVMFGE_VF16_M4 + {7, OperandInfo576}, // Inst #5792 = PseudoVMFGE_VF16_M4_MASK + {5, OperandInfo577}, // Inst #5793 = PseudoVMFGE_VF16_M8 + {7, OperandInfo578}, // Inst #5794 = PseudoVMFGE_VF16_M8_MASK + {5, OperandInfo130}, // Inst #5795 = PseudoVMFGE_VF16_MF2 + {7, OperandInfo572}, // Inst #5796 = PseudoVMFGE_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #5797 = PseudoVMFGE_VF16_MF4 + {7, OperandInfo572}, // Inst #5798 = PseudoVMFGE_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #5799 = PseudoVMFGE_VF16_MF8 + {7, OperandInfo572}, // Inst #5800 = PseudoVMFGE_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #5801 = PseudoVMFGE_VF32_M1 + {7, OperandInfo579}, // Inst #5802 = PseudoVMFGE_VF32_M1_MASK + {5, OperandInfo580}, // Inst #5803 = PseudoVMFGE_VF32_M2 + {7, OperandInfo581}, // Inst #5804 = PseudoVMFGE_VF32_M2_MASK + {5, OperandInfo582}, // Inst #5805 = PseudoVMFGE_VF32_M4 + {7, OperandInfo583}, // Inst #5806 = PseudoVMFGE_VF32_M4_MASK + {5, OperandInfo584}, // Inst #5807 = PseudoVMFGE_VF32_M8 + {7, OperandInfo585}, // Inst #5808 = PseudoVMFGE_VF32_M8_MASK + {5, OperandInfo138}, // Inst #5809 = PseudoVMFGE_VF32_MF2 + {7, OperandInfo579}, // Inst #5810 = PseudoVMFGE_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #5811 = PseudoVMFGE_VF32_MF4 + {7, OperandInfo579}, // Inst #5812 = PseudoVMFGE_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #5813 = PseudoVMFGE_VF32_MF8 + {7, OperandInfo579}, // Inst #5814 = PseudoVMFGE_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #5815 = PseudoVMFGE_VF64_M1 + {7, OperandInfo586}, // Inst #5816 = PseudoVMFGE_VF64_M1_MASK + {5, OperandInfo587}, // Inst #5817 = PseudoVMFGE_VF64_M2 + {7, OperandInfo588}, // Inst #5818 = PseudoVMFGE_VF64_M2_MASK + {5, OperandInfo589}, // Inst #5819 = PseudoVMFGE_VF64_M4 + {7, OperandInfo590}, // Inst #5820 = PseudoVMFGE_VF64_M4_MASK + {5, OperandInfo591}, // Inst #5821 = PseudoVMFGE_VF64_M8 + {7, OperandInfo592}, // Inst #5822 = PseudoVMFGE_VF64_M8_MASK + {5, OperandInfo146}, // Inst #5823 = PseudoVMFGE_VF64_MF2 + {7, OperandInfo586}, // Inst #5824 = PseudoVMFGE_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #5825 = PseudoVMFGE_VF64_MF4 + {7, OperandInfo586}, // Inst #5826 = PseudoVMFGE_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #5827 = PseudoVMFGE_VF64_MF8 + {7, OperandInfo586}, // Inst #5828 = PseudoVMFGE_VF64_MF8_MASK + {5, OperandInfo130}, // Inst #5829 = PseudoVMFGT_VF16_M1 + {7, OperandInfo572}, // Inst #5830 = PseudoVMFGT_VF16_M1_MASK + {5, OperandInfo573}, // Inst #5831 = PseudoVMFGT_VF16_M2 + {7, OperandInfo574}, // Inst #5832 = PseudoVMFGT_VF16_M2_MASK + {5, OperandInfo575}, // Inst #5833 = PseudoVMFGT_VF16_M4 + {7, OperandInfo576}, // Inst #5834 = PseudoVMFGT_VF16_M4_MASK + {5, OperandInfo577}, // Inst #5835 = PseudoVMFGT_VF16_M8 + {7, OperandInfo578}, // Inst #5836 = PseudoVMFGT_VF16_M8_MASK + {5, OperandInfo130}, // Inst #5837 = PseudoVMFGT_VF16_MF2 + {7, OperandInfo572}, // Inst #5838 = PseudoVMFGT_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #5839 = PseudoVMFGT_VF16_MF4 + {7, OperandInfo572}, // Inst #5840 = PseudoVMFGT_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #5841 = PseudoVMFGT_VF16_MF8 + {7, OperandInfo572}, // Inst #5842 = PseudoVMFGT_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #5843 = PseudoVMFGT_VF32_M1 + {7, OperandInfo579}, // Inst #5844 = PseudoVMFGT_VF32_M1_MASK + {5, OperandInfo580}, // Inst #5845 = PseudoVMFGT_VF32_M2 + {7, OperandInfo581}, // Inst #5846 = PseudoVMFGT_VF32_M2_MASK + {5, OperandInfo582}, // Inst #5847 = PseudoVMFGT_VF32_M4 + {7, OperandInfo583}, // Inst #5848 = PseudoVMFGT_VF32_M4_MASK + {5, OperandInfo584}, // Inst #5849 = PseudoVMFGT_VF32_M8 + {7, OperandInfo585}, // Inst #5850 = PseudoVMFGT_VF32_M8_MASK + {5, OperandInfo138}, // Inst #5851 = PseudoVMFGT_VF32_MF2 + {7, OperandInfo579}, // Inst #5852 = PseudoVMFGT_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #5853 = PseudoVMFGT_VF32_MF4 + {7, OperandInfo579}, // Inst #5854 = PseudoVMFGT_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #5855 = PseudoVMFGT_VF32_MF8 + {7, OperandInfo579}, // Inst #5856 = PseudoVMFGT_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #5857 = PseudoVMFGT_VF64_M1 + {7, OperandInfo586}, // Inst #5858 = PseudoVMFGT_VF64_M1_MASK + {5, OperandInfo587}, // Inst #5859 = PseudoVMFGT_VF64_M2 + {7, OperandInfo588}, // Inst #5860 = PseudoVMFGT_VF64_M2_MASK + {5, OperandInfo589}, // Inst #5861 = PseudoVMFGT_VF64_M4 + {7, OperandInfo590}, // Inst #5862 = PseudoVMFGT_VF64_M4_MASK + {5, OperandInfo591}, // Inst #5863 = PseudoVMFGT_VF64_M8 + {7, OperandInfo592}, // Inst #5864 = PseudoVMFGT_VF64_M8_MASK + {5, OperandInfo146}, // Inst #5865 = PseudoVMFGT_VF64_MF2 + {7, OperandInfo586}, // Inst #5866 = PseudoVMFGT_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #5867 = PseudoVMFGT_VF64_MF4 + {7, OperandInfo586}, // Inst #5868 = PseudoVMFGT_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #5869 = PseudoVMFGT_VF64_MF8 + {7, OperandInfo586}, // Inst #5870 = PseudoVMFGT_VF64_MF8_MASK + {5, OperandInfo130}, // Inst #5871 = PseudoVMFLE_VF16_M1 + {7, OperandInfo572}, // Inst #5872 = PseudoVMFLE_VF16_M1_MASK + {5, OperandInfo573}, // Inst #5873 = PseudoVMFLE_VF16_M2 + {7, OperandInfo574}, // Inst #5874 = PseudoVMFLE_VF16_M2_MASK + {5, OperandInfo575}, // Inst #5875 = PseudoVMFLE_VF16_M4 + {7, OperandInfo576}, // Inst #5876 = PseudoVMFLE_VF16_M4_MASK + {5, OperandInfo577}, // Inst #5877 = PseudoVMFLE_VF16_M8 + {7, OperandInfo578}, // Inst #5878 = PseudoVMFLE_VF16_M8_MASK + {5, OperandInfo130}, // Inst #5879 = PseudoVMFLE_VF16_MF2 + {7, OperandInfo572}, // Inst #5880 = PseudoVMFLE_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #5881 = PseudoVMFLE_VF16_MF4 + {7, OperandInfo572}, // Inst #5882 = PseudoVMFLE_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #5883 = PseudoVMFLE_VF16_MF8 + {7, OperandInfo572}, // Inst #5884 = PseudoVMFLE_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #5885 = PseudoVMFLE_VF32_M1 + {7, OperandInfo579}, // Inst #5886 = PseudoVMFLE_VF32_M1_MASK + {5, OperandInfo580}, // Inst #5887 = PseudoVMFLE_VF32_M2 + {7, OperandInfo581}, // Inst #5888 = PseudoVMFLE_VF32_M2_MASK + {5, OperandInfo582}, // Inst #5889 = PseudoVMFLE_VF32_M4 + {7, OperandInfo583}, // Inst #5890 = PseudoVMFLE_VF32_M4_MASK + {5, OperandInfo584}, // Inst #5891 = PseudoVMFLE_VF32_M8 + {7, OperandInfo585}, // Inst #5892 = PseudoVMFLE_VF32_M8_MASK + {5, OperandInfo138}, // Inst #5893 = PseudoVMFLE_VF32_MF2 + {7, OperandInfo579}, // Inst #5894 = PseudoVMFLE_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #5895 = PseudoVMFLE_VF32_MF4 + {7, OperandInfo579}, // Inst #5896 = PseudoVMFLE_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #5897 = PseudoVMFLE_VF32_MF8 + {7, OperandInfo579}, // Inst #5898 = PseudoVMFLE_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #5899 = PseudoVMFLE_VF64_M1 + {7, OperandInfo586}, // Inst #5900 = PseudoVMFLE_VF64_M1_MASK + {5, OperandInfo587}, // Inst #5901 = PseudoVMFLE_VF64_M2 + {7, OperandInfo588}, // Inst #5902 = PseudoVMFLE_VF64_M2_MASK + {5, OperandInfo589}, // Inst #5903 = PseudoVMFLE_VF64_M4 + {7, OperandInfo590}, // Inst #5904 = PseudoVMFLE_VF64_M4_MASK + {5, OperandInfo591}, // Inst #5905 = PseudoVMFLE_VF64_M8 + {7, OperandInfo592}, // Inst #5906 = PseudoVMFLE_VF64_M8_MASK + {5, OperandInfo146}, // Inst #5907 = PseudoVMFLE_VF64_MF2 + {7, OperandInfo586}, // Inst #5908 = PseudoVMFLE_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #5909 = PseudoVMFLE_VF64_MF4 + {7, OperandInfo586}, // Inst #5910 = PseudoVMFLE_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #5911 = PseudoVMFLE_VF64_MF8 + {7, OperandInfo586}, // Inst #5912 = PseudoVMFLE_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #5913 = PseudoVMFLE_VV_M1 + {7, OperandInfo593}, // Inst #5914 = PseudoVMFLE_VV_M1_MASK + {5, OperandInfo561}, // Inst #5915 = PseudoVMFLE_VV_M2 + {7, OperandInfo594}, // Inst #5916 = PseudoVMFLE_VV_M2_MASK + {5, OperandInfo562}, // Inst #5917 = PseudoVMFLE_VV_M4 + {7, OperandInfo595}, // Inst #5918 = PseudoVMFLE_VV_M4_MASK + {5, OperandInfo563}, // Inst #5919 = PseudoVMFLE_VV_M8 + {7, OperandInfo596}, // Inst #5920 = PseudoVMFLE_VV_M8_MASK + {5, OperandInfo62}, // Inst #5921 = PseudoVMFLE_VV_MF2 + {7, OperandInfo593}, // Inst #5922 = PseudoVMFLE_VV_MF2_MASK + {5, OperandInfo62}, // Inst #5923 = PseudoVMFLE_VV_MF4 + {7, OperandInfo593}, // Inst #5924 = PseudoVMFLE_VV_MF4_MASK + {5, OperandInfo62}, // Inst #5925 = PseudoVMFLE_VV_MF8 + {7, OperandInfo593}, // Inst #5926 = PseudoVMFLE_VV_MF8_MASK + {5, OperandInfo130}, // Inst #5927 = PseudoVMFLT_VF16_M1 + {7, OperandInfo572}, // Inst #5928 = PseudoVMFLT_VF16_M1_MASK + {5, OperandInfo573}, // Inst #5929 = PseudoVMFLT_VF16_M2 + {7, OperandInfo574}, // Inst #5930 = PseudoVMFLT_VF16_M2_MASK + {5, OperandInfo575}, // Inst #5931 = PseudoVMFLT_VF16_M4 + {7, OperandInfo576}, // Inst #5932 = PseudoVMFLT_VF16_M4_MASK + {5, OperandInfo577}, // Inst #5933 = PseudoVMFLT_VF16_M8 + {7, OperandInfo578}, // Inst #5934 = PseudoVMFLT_VF16_M8_MASK + {5, OperandInfo130}, // Inst #5935 = PseudoVMFLT_VF16_MF2 + {7, OperandInfo572}, // Inst #5936 = PseudoVMFLT_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #5937 = PseudoVMFLT_VF16_MF4 + {7, OperandInfo572}, // Inst #5938 = PseudoVMFLT_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #5939 = PseudoVMFLT_VF16_MF8 + {7, OperandInfo572}, // Inst #5940 = PseudoVMFLT_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #5941 = PseudoVMFLT_VF32_M1 + {7, OperandInfo579}, // Inst #5942 = PseudoVMFLT_VF32_M1_MASK + {5, OperandInfo580}, // Inst #5943 = PseudoVMFLT_VF32_M2 + {7, OperandInfo581}, // Inst #5944 = PseudoVMFLT_VF32_M2_MASK + {5, OperandInfo582}, // Inst #5945 = PseudoVMFLT_VF32_M4 + {7, OperandInfo583}, // Inst #5946 = PseudoVMFLT_VF32_M4_MASK + {5, OperandInfo584}, // Inst #5947 = PseudoVMFLT_VF32_M8 + {7, OperandInfo585}, // Inst #5948 = PseudoVMFLT_VF32_M8_MASK + {5, OperandInfo138}, // Inst #5949 = PseudoVMFLT_VF32_MF2 + {7, OperandInfo579}, // Inst #5950 = PseudoVMFLT_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #5951 = PseudoVMFLT_VF32_MF4 + {7, OperandInfo579}, // Inst #5952 = PseudoVMFLT_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #5953 = PseudoVMFLT_VF32_MF8 + {7, OperandInfo579}, // Inst #5954 = PseudoVMFLT_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #5955 = PseudoVMFLT_VF64_M1 + {7, OperandInfo586}, // Inst #5956 = PseudoVMFLT_VF64_M1_MASK + {5, OperandInfo587}, // Inst #5957 = PseudoVMFLT_VF64_M2 + {7, OperandInfo588}, // Inst #5958 = PseudoVMFLT_VF64_M2_MASK + {5, OperandInfo589}, // Inst #5959 = PseudoVMFLT_VF64_M4 + {7, OperandInfo590}, // Inst #5960 = PseudoVMFLT_VF64_M4_MASK + {5, OperandInfo591}, // Inst #5961 = PseudoVMFLT_VF64_M8 + {7, OperandInfo592}, // Inst #5962 = PseudoVMFLT_VF64_M8_MASK + {5, OperandInfo146}, // Inst #5963 = PseudoVMFLT_VF64_MF2 + {7, OperandInfo586}, // Inst #5964 = PseudoVMFLT_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #5965 = PseudoVMFLT_VF64_MF4 + {7, OperandInfo586}, // Inst #5966 = PseudoVMFLT_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #5967 = PseudoVMFLT_VF64_MF8 + {7, OperandInfo586}, // Inst #5968 = PseudoVMFLT_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #5969 = PseudoVMFLT_VV_M1 + {7, OperandInfo593}, // Inst #5970 = PseudoVMFLT_VV_M1_MASK + {5, OperandInfo561}, // Inst #5971 = PseudoVMFLT_VV_M2 + {7, OperandInfo594}, // Inst #5972 = PseudoVMFLT_VV_M2_MASK + {5, OperandInfo562}, // Inst #5973 = PseudoVMFLT_VV_M4 + {7, OperandInfo595}, // Inst #5974 = PseudoVMFLT_VV_M4_MASK + {5, OperandInfo563}, // Inst #5975 = PseudoVMFLT_VV_M8 + {7, OperandInfo596}, // Inst #5976 = PseudoVMFLT_VV_M8_MASK + {5, OperandInfo62}, // Inst #5977 = PseudoVMFLT_VV_MF2 + {7, OperandInfo593}, // Inst #5978 = PseudoVMFLT_VV_MF2_MASK + {5, OperandInfo62}, // Inst #5979 = PseudoVMFLT_VV_MF4 + {7, OperandInfo593}, // Inst #5980 = PseudoVMFLT_VV_MF4_MASK + {5, OperandInfo62}, // Inst #5981 = PseudoVMFLT_VV_MF8 + {7, OperandInfo593}, // Inst #5982 = PseudoVMFLT_VV_MF8_MASK + {5, OperandInfo130}, // Inst #5983 = PseudoVMFNE_VF16_M1 + {7, OperandInfo572}, // Inst #5984 = PseudoVMFNE_VF16_M1_MASK + {5, OperandInfo573}, // Inst #5985 = PseudoVMFNE_VF16_M2 + {7, OperandInfo574}, // Inst #5986 = PseudoVMFNE_VF16_M2_MASK + {5, OperandInfo575}, // Inst #5987 = PseudoVMFNE_VF16_M4 + {7, OperandInfo576}, // Inst #5988 = PseudoVMFNE_VF16_M4_MASK + {5, OperandInfo577}, // Inst #5989 = PseudoVMFNE_VF16_M8 + {7, OperandInfo578}, // Inst #5990 = PseudoVMFNE_VF16_M8_MASK + {5, OperandInfo130}, // Inst #5991 = PseudoVMFNE_VF16_MF2 + {7, OperandInfo572}, // Inst #5992 = PseudoVMFNE_VF16_MF2_MASK + {5, OperandInfo130}, // Inst #5993 = PseudoVMFNE_VF16_MF4 + {7, OperandInfo572}, // Inst #5994 = PseudoVMFNE_VF16_MF4_MASK + {5, OperandInfo130}, // Inst #5995 = PseudoVMFNE_VF16_MF8 + {7, OperandInfo572}, // Inst #5996 = PseudoVMFNE_VF16_MF8_MASK + {5, OperandInfo138}, // Inst #5997 = PseudoVMFNE_VF32_M1 + {7, OperandInfo579}, // Inst #5998 = PseudoVMFNE_VF32_M1_MASK + {5, OperandInfo580}, // Inst #5999 = PseudoVMFNE_VF32_M2 + {7, OperandInfo581}, // Inst #6000 = PseudoVMFNE_VF32_M2_MASK + {5, OperandInfo582}, // Inst #6001 = PseudoVMFNE_VF32_M4 + {7, OperandInfo583}, // Inst #6002 = PseudoVMFNE_VF32_M4_MASK + {5, OperandInfo584}, // Inst #6003 = PseudoVMFNE_VF32_M8 + {7, OperandInfo585}, // Inst #6004 = PseudoVMFNE_VF32_M8_MASK + {5, OperandInfo138}, // Inst #6005 = PseudoVMFNE_VF32_MF2 + {7, OperandInfo579}, // Inst #6006 = PseudoVMFNE_VF32_MF2_MASK + {5, OperandInfo138}, // Inst #6007 = PseudoVMFNE_VF32_MF4 + {7, OperandInfo579}, // Inst #6008 = PseudoVMFNE_VF32_MF4_MASK + {5, OperandInfo138}, // Inst #6009 = PseudoVMFNE_VF32_MF8 + {7, OperandInfo579}, // Inst #6010 = PseudoVMFNE_VF32_MF8_MASK + {5, OperandInfo146}, // Inst #6011 = PseudoVMFNE_VF64_M1 + {7, OperandInfo586}, // Inst #6012 = PseudoVMFNE_VF64_M1_MASK + {5, OperandInfo587}, // Inst #6013 = PseudoVMFNE_VF64_M2 + {7, OperandInfo588}, // Inst #6014 = PseudoVMFNE_VF64_M2_MASK + {5, OperandInfo589}, // Inst #6015 = PseudoVMFNE_VF64_M4 + {7, OperandInfo590}, // Inst #6016 = PseudoVMFNE_VF64_M4_MASK + {5, OperandInfo591}, // Inst #6017 = PseudoVMFNE_VF64_M8 + {7, OperandInfo592}, // Inst #6018 = PseudoVMFNE_VF64_M8_MASK + {5, OperandInfo146}, // Inst #6019 = PseudoVMFNE_VF64_MF2 + {7, OperandInfo586}, // Inst #6020 = PseudoVMFNE_VF64_MF2_MASK + {5, OperandInfo146}, // Inst #6021 = PseudoVMFNE_VF64_MF4 + {7, OperandInfo586}, // Inst #6022 = PseudoVMFNE_VF64_MF4_MASK + {5, OperandInfo146}, // Inst #6023 = PseudoVMFNE_VF64_MF8 + {7, OperandInfo586}, // Inst #6024 = PseudoVMFNE_VF64_MF8_MASK + {5, OperandInfo62}, // Inst #6025 = PseudoVMFNE_VV_M1 + {7, OperandInfo593}, // Inst #6026 = PseudoVMFNE_VV_M1_MASK + {5, OperandInfo561}, // Inst #6027 = PseudoVMFNE_VV_M2 + {7, OperandInfo594}, // Inst #6028 = PseudoVMFNE_VV_M2_MASK + {5, OperandInfo562}, // Inst #6029 = PseudoVMFNE_VV_M4 + {7, OperandInfo595}, // Inst #6030 = PseudoVMFNE_VV_M4_MASK + {5, OperandInfo563}, // Inst #6031 = PseudoVMFNE_VV_M8 + {7, OperandInfo596}, // Inst #6032 = PseudoVMFNE_VV_M8_MASK + {5, OperandInfo62}, // Inst #6033 = PseudoVMFNE_VV_MF2 + {7, OperandInfo593}, // Inst #6034 = PseudoVMFNE_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6035 = PseudoVMFNE_VV_MF4 + {7, OperandInfo593}, // Inst #6036 = PseudoVMFNE_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6037 = PseudoVMFNE_VV_MF8 + {7, OperandInfo593}, // Inst #6038 = PseudoVMFNE_VV_MF8_MASK + {5, OperandInfo62}, // Inst #6039 = PseudoVMINU_VV_M1 + {8, OperandInfo63}, // Inst #6040 = PseudoVMINU_VV_M1_MASK + {5, OperandInfo64}, // Inst #6041 = PseudoVMINU_VV_M2 + {8, OperandInfo65}, // Inst #6042 = PseudoVMINU_VV_M2_MASK + {5, OperandInfo66}, // Inst #6043 = PseudoVMINU_VV_M4 + {8, OperandInfo67}, // Inst #6044 = PseudoVMINU_VV_M4_MASK + {5, OperandInfo68}, // Inst #6045 = PseudoVMINU_VV_M8 + {8, OperandInfo69}, // Inst #6046 = PseudoVMINU_VV_M8_MASK + {5, OperandInfo62}, // Inst #6047 = PseudoVMINU_VV_MF2 + {8, OperandInfo63}, // Inst #6048 = PseudoVMINU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6049 = PseudoVMINU_VV_MF4 + {8, OperandInfo63}, // Inst #6050 = PseudoVMINU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6051 = PseudoVMINU_VV_MF8 + {8, OperandInfo63}, // Inst #6052 = PseudoVMINU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6053 = PseudoVMINU_VX_M1 + {8, OperandInfo71}, // Inst #6054 = PseudoVMINU_VX_M1_MASK + {5, OperandInfo72}, // Inst #6055 = PseudoVMINU_VX_M2 + {8, OperandInfo73}, // Inst #6056 = PseudoVMINU_VX_M2_MASK + {5, OperandInfo74}, // Inst #6057 = PseudoVMINU_VX_M4 + {8, OperandInfo75}, // Inst #6058 = PseudoVMINU_VX_M4_MASK + {5, OperandInfo76}, // Inst #6059 = PseudoVMINU_VX_M8 + {8, OperandInfo77}, // Inst #6060 = PseudoVMINU_VX_M8_MASK + {5, OperandInfo70}, // Inst #6061 = PseudoVMINU_VX_MF2 + {8, OperandInfo71}, // Inst #6062 = PseudoVMINU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6063 = PseudoVMINU_VX_MF4 + {8, OperandInfo71}, // Inst #6064 = PseudoVMINU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6065 = PseudoVMINU_VX_MF8 + {8, OperandInfo71}, // Inst #6066 = PseudoVMINU_VX_MF8_MASK + {5, OperandInfo62}, // Inst #6067 = PseudoVMIN_VV_M1 + {8, OperandInfo63}, // Inst #6068 = PseudoVMIN_VV_M1_MASK + {5, OperandInfo64}, // Inst #6069 = PseudoVMIN_VV_M2 + {8, OperandInfo65}, // Inst #6070 = PseudoVMIN_VV_M2_MASK + {5, OperandInfo66}, // Inst #6071 = PseudoVMIN_VV_M4 + {8, OperandInfo67}, // Inst #6072 = PseudoVMIN_VV_M4_MASK + {5, OperandInfo68}, // Inst #6073 = PseudoVMIN_VV_M8 + {8, OperandInfo69}, // Inst #6074 = PseudoVMIN_VV_M8_MASK + {5, OperandInfo62}, // Inst #6075 = PseudoVMIN_VV_MF2 + {8, OperandInfo63}, // Inst #6076 = PseudoVMIN_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6077 = PseudoVMIN_VV_MF4 + {8, OperandInfo63}, // Inst #6078 = PseudoVMIN_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6079 = PseudoVMIN_VV_MF8 + {8, OperandInfo63}, // Inst #6080 = PseudoVMIN_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6081 = PseudoVMIN_VX_M1 + {8, OperandInfo71}, // Inst #6082 = PseudoVMIN_VX_M1_MASK + {5, OperandInfo72}, // Inst #6083 = PseudoVMIN_VX_M2 + {8, OperandInfo73}, // Inst #6084 = PseudoVMIN_VX_M2_MASK + {5, OperandInfo74}, // Inst #6085 = PseudoVMIN_VX_M4 + {8, OperandInfo75}, // Inst #6086 = PseudoVMIN_VX_M4_MASK + {5, OperandInfo76}, // Inst #6087 = PseudoVMIN_VX_M8 + {8, OperandInfo77}, // Inst #6088 = PseudoVMIN_VX_M8_MASK + {5, OperandInfo70}, // Inst #6089 = PseudoVMIN_VX_MF2 + {8, OperandInfo71}, // Inst #6090 = PseudoVMIN_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6091 = PseudoVMIN_VX_MF4 + {8, OperandInfo71}, // Inst #6092 = PseudoVMIN_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6093 = PseudoVMIN_VX_MF8 + {8, OperandInfo71}, // Inst #6094 = PseudoVMIN_VX_MF8_MASK + {5, OperandInfo62}, // Inst #6095 = PseudoVMNAND_MM_M1 + {5, OperandInfo62}, // Inst #6096 = PseudoVMNAND_MM_M2 + {5, OperandInfo62}, // Inst #6097 = PseudoVMNAND_MM_M4 + {5, OperandInfo62}, // Inst #6098 = PseudoVMNAND_MM_M8 + {5, OperandInfo62}, // Inst #6099 = PseudoVMNAND_MM_MF2 + {5, OperandInfo62}, // Inst #6100 = PseudoVMNAND_MM_MF4 + {5, OperandInfo62}, // Inst #6101 = PseudoVMNAND_MM_MF8 + {5, OperandInfo62}, // Inst #6102 = PseudoVMNOR_MM_M1 + {5, OperandInfo62}, // Inst #6103 = PseudoVMNOR_MM_M2 + {5, OperandInfo62}, // Inst #6104 = PseudoVMNOR_MM_M4 + {5, OperandInfo62}, // Inst #6105 = PseudoVMNOR_MM_M8 + {5, OperandInfo62}, // Inst #6106 = PseudoVMNOR_MM_MF2 + {5, OperandInfo62}, // Inst #6107 = PseudoVMNOR_MM_MF4 + {5, OperandInfo62}, // Inst #6108 = PseudoVMNOR_MM_MF8 + {5, OperandInfo62}, // Inst #6109 = PseudoVMORN_MM_M1 + {5, OperandInfo62}, // Inst #6110 = PseudoVMORN_MM_M2 + {5, OperandInfo62}, // Inst #6111 = PseudoVMORN_MM_M4 + {5, OperandInfo62}, // Inst #6112 = PseudoVMORN_MM_M8 + {5, OperandInfo62}, // Inst #6113 = PseudoVMORN_MM_MF2 + {5, OperandInfo62}, // Inst #6114 = PseudoVMORN_MM_MF4 + {5, OperandInfo62}, // Inst #6115 = PseudoVMORN_MM_MF8 + {5, OperandInfo62}, // Inst #6116 = PseudoVMOR_MM_M1 + {5, OperandInfo62}, // Inst #6117 = PseudoVMOR_MM_M2 + {5, OperandInfo62}, // Inst #6118 = PseudoVMOR_MM_M4 + {5, OperandInfo62}, // Inst #6119 = PseudoVMOR_MM_M8 + {5, OperandInfo62}, // Inst #6120 = PseudoVMOR_MM_MF2 + {5, OperandInfo62}, // Inst #6121 = PseudoVMOR_MM_MF4 + {5, OperandInfo62}, // Inst #6122 = PseudoVMOR_MM_MF8 + {6, OperandInfo557}, // Inst #6123 = PseudoVMSBC_VVM_M1 + {6, OperandInfo558}, // Inst #6124 = PseudoVMSBC_VVM_M2 + {6, OperandInfo559}, // Inst #6125 = PseudoVMSBC_VVM_M4 + {6, OperandInfo560}, // Inst #6126 = PseudoVMSBC_VVM_M8 + {6, OperandInfo557}, // Inst #6127 = PseudoVMSBC_VVM_MF2 + {6, OperandInfo557}, // Inst #6128 = PseudoVMSBC_VVM_MF4 + {6, OperandInfo557}, // Inst #6129 = PseudoVMSBC_VVM_MF8 + {5, OperandInfo303}, // Inst #6130 = PseudoVMSBC_VV_M1 + {5, OperandInfo561}, // Inst #6131 = PseudoVMSBC_VV_M2 + {5, OperandInfo562}, // Inst #6132 = PseudoVMSBC_VV_M4 + {5, OperandInfo563}, // Inst #6133 = PseudoVMSBC_VV_M8 + {5, OperandInfo303}, // Inst #6134 = PseudoVMSBC_VV_MF2 + {5, OperandInfo303}, // Inst #6135 = PseudoVMSBC_VV_MF4 + {5, OperandInfo303}, // Inst #6136 = PseudoVMSBC_VV_MF8 + {6, OperandInfo564}, // Inst #6137 = PseudoVMSBC_VXM_M1 + {6, OperandInfo565}, // Inst #6138 = PseudoVMSBC_VXM_M2 + {6, OperandInfo566}, // Inst #6139 = PseudoVMSBC_VXM_M4 + {6, OperandInfo567}, // Inst #6140 = PseudoVMSBC_VXM_M8 + {6, OperandInfo564}, // Inst #6141 = PseudoVMSBC_VXM_MF2 + {6, OperandInfo564}, // Inst #6142 = PseudoVMSBC_VXM_MF4 + {6, OperandInfo564}, // Inst #6143 = PseudoVMSBC_VXM_MF8 + {5, OperandInfo568}, // Inst #6144 = PseudoVMSBC_VX_M1 + {5, OperandInfo569}, // Inst #6145 = PseudoVMSBC_VX_M2 + {5, OperandInfo570}, // Inst #6146 = PseudoVMSBC_VX_M4 + {5, OperandInfo571}, // Inst #6147 = PseudoVMSBC_VX_M8 + {5, OperandInfo568}, // Inst #6148 = PseudoVMSBC_VX_MF2 + {5, OperandInfo568}, // Inst #6149 = PseudoVMSBC_VX_MF4 + {5, OperandInfo568}, // Inst #6150 = PseudoVMSBC_VX_MF8 + {4, OperandInfo252}, // Inst #6151 = PseudoVMSBF_M_B1 + {4, OperandInfo252}, // Inst #6152 = PseudoVMSBF_M_B16 + {6, OperandInfo353}, // Inst #6153 = PseudoVMSBF_M_B16_MASK + {6, OperandInfo353}, // Inst #6154 = PseudoVMSBF_M_B1_MASK + {4, OperandInfo252}, // Inst #6155 = PseudoVMSBF_M_B2 + {6, OperandInfo353}, // Inst #6156 = PseudoVMSBF_M_B2_MASK + {4, OperandInfo252}, // Inst #6157 = PseudoVMSBF_M_B32 + {6, OperandInfo353}, // Inst #6158 = PseudoVMSBF_M_B32_MASK + {4, OperandInfo252}, // Inst #6159 = PseudoVMSBF_M_B4 + {6, OperandInfo353}, // Inst #6160 = PseudoVMSBF_M_B4_MASK + {4, OperandInfo252}, // Inst #6161 = PseudoVMSBF_M_B64 + {6, OperandInfo353}, // Inst #6162 = PseudoVMSBF_M_B64_MASK + {4, OperandInfo252}, // Inst #6163 = PseudoVMSBF_M_B8 + {6, OperandInfo353}, // Inst #6164 = PseudoVMSBF_M_B8_MASK + {5, OperandInfo90}, // Inst #6165 = PseudoVMSEQ_VI_M1 + {7, OperandInfo597}, // Inst #6166 = PseudoVMSEQ_VI_M1_MASK + {5, OperandInfo554}, // Inst #6167 = PseudoVMSEQ_VI_M2 + {7, OperandInfo598}, // Inst #6168 = PseudoVMSEQ_VI_M2_MASK + {5, OperandInfo555}, // Inst #6169 = PseudoVMSEQ_VI_M4 + {7, OperandInfo599}, // Inst #6170 = PseudoVMSEQ_VI_M4_MASK + {5, OperandInfo556}, // Inst #6171 = PseudoVMSEQ_VI_M8 + {7, OperandInfo600}, // Inst #6172 = PseudoVMSEQ_VI_M8_MASK + {5, OperandInfo90}, // Inst #6173 = PseudoVMSEQ_VI_MF2 + {7, OperandInfo597}, // Inst #6174 = PseudoVMSEQ_VI_MF2_MASK + {5, OperandInfo90}, // Inst #6175 = PseudoVMSEQ_VI_MF4 + {7, OperandInfo597}, // Inst #6176 = PseudoVMSEQ_VI_MF4_MASK + {5, OperandInfo90}, // Inst #6177 = PseudoVMSEQ_VI_MF8 + {7, OperandInfo597}, // Inst #6178 = PseudoVMSEQ_VI_MF8_MASK + {5, OperandInfo62}, // Inst #6179 = PseudoVMSEQ_VV_M1 + {7, OperandInfo593}, // Inst #6180 = PseudoVMSEQ_VV_M1_MASK + {5, OperandInfo561}, // Inst #6181 = PseudoVMSEQ_VV_M2 + {7, OperandInfo594}, // Inst #6182 = PseudoVMSEQ_VV_M2_MASK + {5, OperandInfo562}, // Inst #6183 = PseudoVMSEQ_VV_M4 + {7, OperandInfo595}, // Inst #6184 = PseudoVMSEQ_VV_M4_MASK + {5, OperandInfo563}, // Inst #6185 = PseudoVMSEQ_VV_M8 + {7, OperandInfo596}, // Inst #6186 = PseudoVMSEQ_VV_M8_MASK + {5, OperandInfo62}, // Inst #6187 = PseudoVMSEQ_VV_MF2 + {7, OperandInfo593}, // Inst #6188 = PseudoVMSEQ_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6189 = PseudoVMSEQ_VV_MF4 + {7, OperandInfo593}, // Inst #6190 = PseudoVMSEQ_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6191 = PseudoVMSEQ_VV_MF8 + {7, OperandInfo593}, // Inst #6192 = PseudoVMSEQ_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6193 = PseudoVMSEQ_VX_M1 + {7, OperandInfo601}, // Inst #6194 = PseudoVMSEQ_VX_M1_MASK + {5, OperandInfo569}, // Inst #6195 = PseudoVMSEQ_VX_M2 + {7, OperandInfo602}, // Inst #6196 = PseudoVMSEQ_VX_M2_MASK + {5, OperandInfo570}, // Inst #6197 = PseudoVMSEQ_VX_M4 + {7, OperandInfo603}, // Inst #6198 = PseudoVMSEQ_VX_M4_MASK + {5, OperandInfo571}, // Inst #6199 = PseudoVMSEQ_VX_M8 + {7, OperandInfo604}, // Inst #6200 = PseudoVMSEQ_VX_M8_MASK + {5, OperandInfo70}, // Inst #6201 = PseudoVMSEQ_VX_MF2 + {7, OperandInfo601}, // Inst #6202 = PseudoVMSEQ_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6203 = PseudoVMSEQ_VX_MF4 + {7, OperandInfo601}, // Inst #6204 = PseudoVMSEQ_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6205 = PseudoVMSEQ_VX_MF8 + {7, OperandInfo601}, // Inst #6206 = PseudoVMSEQ_VX_MF8_MASK + {3, OperandInfo345}, // Inst #6207 = PseudoVMSET_M_B1 + {3, OperandInfo345}, // Inst #6208 = PseudoVMSET_M_B16 + {3, OperandInfo345}, // Inst #6209 = PseudoVMSET_M_B2 + {3, OperandInfo345}, // Inst #6210 = PseudoVMSET_M_B32 + {3, OperandInfo345}, // Inst #6211 = PseudoVMSET_M_B4 + {3, OperandInfo345}, // Inst #6212 = PseudoVMSET_M_B64 + {3, OperandInfo345}, // Inst #6213 = PseudoVMSET_M_B8 + {4, OperandInfo605}, // Inst #6214 = PseudoVMSGEU_VI + {3, OperandInfo606}, // Inst #6215 = PseudoVMSGEU_VX + {4, OperandInfo607}, // Inst #6216 = PseudoVMSGEU_VX_M + {5, OperandInfo608}, // Inst #6217 = PseudoVMSGEU_VX_M_T + {4, OperandInfo605}, // Inst #6218 = PseudoVMSGE_VI + {3, OperandInfo606}, // Inst #6219 = PseudoVMSGE_VX + {4, OperandInfo607}, // Inst #6220 = PseudoVMSGE_VX_M + {5, OperandInfo608}, // Inst #6221 = PseudoVMSGE_VX_M_T + {5, OperandInfo90}, // Inst #6222 = PseudoVMSGTU_VI_M1 + {7, OperandInfo597}, // Inst #6223 = PseudoVMSGTU_VI_M1_MASK + {5, OperandInfo554}, // Inst #6224 = PseudoVMSGTU_VI_M2 + {7, OperandInfo598}, // Inst #6225 = PseudoVMSGTU_VI_M2_MASK + {5, OperandInfo555}, // Inst #6226 = PseudoVMSGTU_VI_M4 + {7, OperandInfo599}, // Inst #6227 = PseudoVMSGTU_VI_M4_MASK + {5, OperandInfo556}, // Inst #6228 = PseudoVMSGTU_VI_M8 + {7, OperandInfo600}, // Inst #6229 = PseudoVMSGTU_VI_M8_MASK + {5, OperandInfo90}, // Inst #6230 = PseudoVMSGTU_VI_MF2 + {7, OperandInfo597}, // Inst #6231 = PseudoVMSGTU_VI_MF2_MASK + {5, OperandInfo90}, // Inst #6232 = PseudoVMSGTU_VI_MF4 + {7, OperandInfo597}, // Inst #6233 = PseudoVMSGTU_VI_MF4_MASK + {5, OperandInfo90}, // Inst #6234 = PseudoVMSGTU_VI_MF8 + {7, OperandInfo597}, // Inst #6235 = PseudoVMSGTU_VI_MF8_MASK + {5, OperandInfo70}, // Inst #6236 = PseudoVMSGTU_VX_M1 + {7, OperandInfo601}, // Inst #6237 = PseudoVMSGTU_VX_M1_MASK + {5, OperandInfo569}, // Inst #6238 = PseudoVMSGTU_VX_M2 + {7, OperandInfo602}, // Inst #6239 = PseudoVMSGTU_VX_M2_MASK + {5, OperandInfo570}, // Inst #6240 = PseudoVMSGTU_VX_M4 + {7, OperandInfo603}, // Inst #6241 = PseudoVMSGTU_VX_M4_MASK + {5, OperandInfo571}, // Inst #6242 = PseudoVMSGTU_VX_M8 + {7, OperandInfo604}, // Inst #6243 = PseudoVMSGTU_VX_M8_MASK + {5, OperandInfo70}, // Inst #6244 = PseudoVMSGTU_VX_MF2 + {7, OperandInfo601}, // Inst #6245 = PseudoVMSGTU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6246 = PseudoVMSGTU_VX_MF4 + {7, OperandInfo601}, // Inst #6247 = PseudoVMSGTU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6248 = PseudoVMSGTU_VX_MF8 + {7, OperandInfo601}, // Inst #6249 = PseudoVMSGTU_VX_MF8_MASK + {5, OperandInfo90}, // Inst #6250 = PseudoVMSGT_VI_M1 + {7, OperandInfo597}, // Inst #6251 = PseudoVMSGT_VI_M1_MASK + {5, OperandInfo554}, // Inst #6252 = PseudoVMSGT_VI_M2 + {7, OperandInfo598}, // Inst #6253 = PseudoVMSGT_VI_M2_MASK + {5, OperandInfo555}, // Inst #6254 = PseudoVMSGT_VI_M4 + {7, OperandInfo599}, // Inst #6255 = PseudoVMSGT_VI_M4_MASK + {5, OperandInfo556}, // Inst #6256 = PseudoVMSGT_VI_M8 + {7, OperandInfo600}, // Inst #6257 = PseudoVMSGT_VI_M8_MASK + {5, OperandInfo90}, // Inst #6258 = PseudoVMSGT_VI_MF2 + {7, OperandInfo597}, // Inst #6259 = PseudoVMSGT_VI_MF2_MASK + {5, OperandInfo90}, // Inst #6260 = PseudoVMSGT_VI_MF4 + {7, OperandInfo597}, // Inst #6261 = PseudoVMSGT_VI_MF4_MASK + {5, OperandInfo90}, // Inst #6262 = PseudoVMSGT_VI_MF8 + {7, OperandInfo597}, // Inst #6263 = PseudoVMSGT_VI_MF8_MASK + {5, OperandInfo70}, // Inst #6264 = PseudoVMSGT_VX_M1 + {7, OperandInfo601}, // Inst #6265 = PseudoVMSGT_VX_M1_MASK + {5, OperandInfo569}, // Inst #6266 = PseudoVMSGT_VX_M2 + {7, OperandInfo602}, // Inst #6267 = PseudoVMSGT_VX_M2_MASK + {5, OperandInfo570}, // Inst #6268 = PseudoVMSGT_VX_M4 + {7, OperandInfo603}, // Inst #6269 = PseudoVMSGT_VX_M4_MASK + {5, OperandInfo571}, // Inst #6270 = PseudoVMSGT_VX_M8 + {7, OperandInfo604}, // Inst #6271 = PseudoVMSGT_VX_M8_MASK + {5, OperandInfo70}, // Inst #6272 = PseudoVMSGT_VX_MF2 + {7, OperandInfo601}, // Inst #6273 = PseudoVMSGT_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6274 = PseudoVMSGT_VX_MF4 + {7, OperandInfo601}, // Inst #6275 = PseudoVMSGT_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6276 = PseudoVMSGT_VX_MF8 + {7, OperandInfo601}, // Inst #6277 = PseudoVMSGT_VX_MF8_MASK + {4, OperandInfo252}, // Inst #6278 = PseudoVMSIF_M_B1 + {4, OperandInfo252}, // Inst #6279 = PseudoVMSIF_M_B16 + {6, OperandInfo353}, // Inst #6280 = PseudoVMSIF_M_B16_MASK + {6, OperandInfo353}, // Inst #6281 = PseudoVMSIF_M_B1_MASK + {4, OperandInfo252}, // Inst #6282 = PseudoVMSIF_M_B2 + {6, OperandInfo353}, // Inst #6283 = PseudoVMSIF_M_B2_MASK + {4, OperandInfo252}, // Inst #6284 = PseudoVMSIF_M_B32 + {6, OperandInfo353}, // Inst #6285 = PseudoVMSIF_M_B32_MASK + {4, OperandInfo252}, // Inst #6286 = PseudoVMSIF_M_B4 + {6, OperandInfo353}, // Inst #6287 = PseudoVMSIF_M_B4_MASK + {4, OperandInfo252}, // Inst #6288 = PseudoVMSIF_M_B64 + {6, OperandInfo353}, // Inst #6289 = PseudoVMSIF_M_B64_MASK + {4, OperandInfo252}, // Inst #6290 = PseudoVMSIF_M_B8 + {6, OperandInfo353}, // Inst #6291 = PseudoVMSIF_M_B8_MASK + {5, OperandInfo90}, // Inst #6292 = PseudoVMSLEU_VI_M1 + {7, OperandInfo597}, // Inst #6293 = PseudoVMSLEU_VI_M1_MASK + {5, OperandInfo554}, // Inst #6294 = PseudoVMSLEU_VI_M2 + {7, OperandInfo598}, // Inst #6295 = PseudoVMSLEU_VI_M2_MASK + {5, OperandInfo555}, // Inst #6296 = PseudoVMSLEU_VI_M4 + {7, OperandInfo599}, // Inst #6297 = PseudoVMSLEU_VI_M4_MASK + {5, OperandInfo556}, // Inst #6298 = PseudoVMSLEU_VI_M8 + {7, OperandInfo600}, // Inst #6299 = PseudoVMSLEU_VI_M8_MASK + {5, OperandInfo90}, // Inst #6300 = PseudoVMSLEU_VI_MF2 + {7, OperandInfo597}, // Inst #6301 = PseudoVMSLEU_VI_MF2_MASK + {5, OperandInfo90}, // Inst #6302 = PseudoVMSLEU_VI_MF4 + {7, OperandInfo597}, // Inst #6303 = PseudoVMSLEU_VI_MF4_MASK + {5, OperandInfo90}, // Inst #6304 = PseudoVMSLEU_VI_MF8 + {7, OperandInfo597}, // Inst #6305 = PseudoVMSLEU_VI_MF8_MASK + {5, OperandInfo62}, // Inst #6306 = PseudoVMSLEU_VV_M1 + {7, OperandInfo593}, // Inst #6307 = PseudoVMSLEU_VV_M1_MASK + {5, OperandInfo561}, // Inst #6308 = PseudoVMSLEU_VV_M2 + {7, OperandInfo594}, // Inst #6309 = PseudoVMSLEU_VV_M2_MASK + {5, OperandInfo562}, // Inst #6310 = PseudoVMSLEU_VV_M4 + {7, OperandInfo595}, // Inst #6311 = PseudoVMSLEU_VV_M4_MASK + {5, OperandInfo563}, // Inst #6312 = PseudoVMSLEU_VV_M8 + {7, OperandInfo596}, // Inst #6313 = PseudoVMSLEU_VV_M8_MASK + {5, OperandInfo62}, // Inst #6314 = PseudoVMSLEU_VV_MF2 + {7, OperandInfo593}, // Inst #6315 = PseudoVMSLEU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6316 = PseudoVMSLEU_VV_MF4 + {7, OperandInfo593}, // Inst #6317 = PseudoVMSLEU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6318 = PseudoVMSLEU_VV_MF8 + {7, OperandInfo593}, // Inst #6319 = PseudoVMSLEU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6320 = PseudoVMSLEU_VX_M1 + {7, OperandInfo601}, // Inst #6321 = PseudoVMSLEU_VX_M1_MASK + {5, OperandInfo569}, // Inst #6322 = PseudoVMSLEU_VX_M2 + {7, OperandInfo602}, // Inst #6323 = PseudoVMSLEU_VX_M2_MASK + {5, OperandInfo570}, // Inst #6324 = PseudoVMSLEU_VX_M4 + {7, OperandInfo603}, // Inst #6325 = PseudoVMSLEU_VX_M4_MASK + {5, OperandInfo571}, // Inst #6326 = PseudoVMSLEU_VX_M8 + {7, OperandInfo604}, // Inst #6327 = PseudoVMSLEU_VX_M8_MASK + {5, OperandInfo70}, // Inst #6328 = PseudoVMSLEU_VX_MF2 + {7, OperandInfo601}, // Inst #6329 = PseudoVMSLEU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6330 = PseudoVMSLEU_VX_MF4 + {7, OperandInfo601}, // Inst #6331 = PseudoVMSLEU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6332 = PseudoVMSLEU_VX_MF8 + {7, OperandInfo601}, // Inst #6333 = PseudoVMSLEU_VX_MF8_MASK + {5, OperandInfo90}, // Inst #6334 = PseudoVMSLE_VI_M1 + {7, OperandInfo597}, // Inst #6335 = PseudoVMSLE_VI_M1_MASK + {5, OperandInfo554}, // Inst #6336 = PseudoVMSLE_VI_M2 + {7, OperandInfo598}, // Inst #6337 = PseudoVMSLE_VI_M2_MASK + {5, OperandInfo555}, // Inst #6338 = PseudoVMSLE_VI_M4 + {7, OperandInfo599}, // Inst #6339 = PseudoVMSLE_VI_M4_MASK + {5, OperandInfo556}, // Inst #6340 = PseudoVMSLE_VI_M8 + {7, OperandInfo600}, // Inst #6341 = PseudoVMSLE_VI_M8_MASK + {5, OperandInfo90}, // Inst #6342 = PseudoVMSLE_VI_MF2 + {7, OperandInfo597}, // Inst #6343 = PseudoVMSLE_VI_MF2_MASK + {5, OperandInfo90}, // Inst #6344 = PseudoVMSLE_VI_MF4 + {7, OperandInfo597}, // Inst #6345 = PseudoVMSLE_VI_MF4_MASK + {5, OperandInfo90}, // Inst #6346 = PseudoVMSLE_VI_MF8 + {7, OperandInfo597}, // Inst #6347 = PseudoVMSLE_VI_MF8_MASK + {5, OperandInfo62}, // Inst #6348 = PseudoVMSLE_VV_M1 + {7, OperandInfo593}, // Inst #6349 = PseudoVMSLE_VV_M1_MASK + {5, OperandInfo561}, // Inst #6350 = PseudoVMSLE_VV_M2 + {7, OperandInfo594}, // Inst #6351 = PseudoVMSLE_VV_M2_MASK + {5, OperandInfo562}, // Inst #6352 = PseudoVMSLE_VV_M4 + {7, OperandInfo595}, // Inst #6353 = PseudoVMSLE_VV_M4_MASK + {5, OperandInfo563}, // Inst #6354 = PseudoVMSLE_VV_M8 + {7, OperandInfo596}, // Inst #6355 = PseudoVMSLE_VV_M8_MASK + {5, OperandInfo62}, // Inst #6356 = PseudoVMSLE_VV_MF2 + {7, OperandInfo593}, // Inst #6357 = PseudoVMSLE_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6358 = PseudoVMSLE_VV_MF4 + {7, OperandInfo593}, // Inst #6359 = PseudoVMSLE_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6360 = PseudoVMSLE_VV_MF8 + {7, OperandInfo593}, // Inst #6361 = PseudoVMSLE_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6362 = PseudoVMSLE_VX_M1 + {7, OperandInfo601}, // Inst #6363 = PseudoVMSLE_VX_M1_MASK + {5, OperandInfo569}, // Inst #6364 = PseudoVMSLE_VX_M2 + {7, OperandInfo602}, // Inst #6365 = PseudoVMSLE_VX_M2_MASK + {5, OperandInfo570}, // Inst #6366 = PseudoVMSLE_VX_M4 + {7, OperandInfo603}, // Inst #6367 = PseudoVMSLE_VX_M4_MASK + {5, OperandInfo571}, // Inst #6368 = PseudoVMSLE_VX_M8 + {7, OperandInfo604}, // Inst #6369 = PseudoVMSLE_VX_M8_MASK + {5, OperandInfo70}, // Inst #6370 = PseudoVMSLE_VX_MF2 + {7, OperandInfo601}, // Inst #6371 = PseudoVMSLE_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6372 = PseudoVMSLE_VX_MF4 + {7, OperandInfo601}, // Inst #6373 = PseudoVMSLE_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6374 = PseudoVMSLE_VX_MF8 + {7, OperandInfo601}, // Inst #6375 = PseudoVMSLE_VX_MF8_MASK + {4, OperandInfo605}, // Inst #6376 = PseudoVMSLTU_VI + {5, OperandInfo62}, // Inst #6377 = PseudoVMSLTU_VV_M1 + {7, OperandInfo593}, // Inst #6378 = PseudoVMSLTU_VV_M1_MASK + {5, OperandInfo561}, // Inst #6379 = PseudoVMSLTU_VV_M2 + {7, OperandInfo594}, // Inst #6380 = PseudoVMSLTU_VV_M2_MASK + {5, OperandInfo562}, // Inst #6381 = PseudoVMSLTU_VV_M4 + {7, OperandInfo595}, // Inst #6382 = PseudoVMSLTU_VV_M4_MASK + {5, OperandInfo563}, // Inst #6383 = PseudoVMSLTU_VV_M8 + {7, OperandInfo596}, // Inst #6384 = PseudoVMSLTU_VV_M8_MASK + {5, OperandInfo62}, // Inst #6385 = PseudoVMSLTU_VV_MF2 + {7, OperandInfo593}, // Inst #6386 = PseudoVMSLTU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6387 = PseudoVMSLTU_VV_MF4 + {7, OperandInfo593}, // Inst #6388 = PseudoVMSLTU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6389 = PseudoVMSLTU_VV_MF8 + {7, OperandInfo593}, // Inst #6390 = PseudoVMSLTU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6391 = PseudoVMSLTU_VX_M1 + {7, OperandInfo601}, // Inst #6392 = PseudoVMSLTU_VX_M1_MASK + {5, OperandInfo569}, // Inst #6393 = PseudoVMSLTU_VX_M2 + {7, OperandInfo602}, // Inst #6394 = PseudoVMSLTU_VX_M2_MASK + {5, OperandInfo570}, // Inst #6395 = PseudoVMSLTU_VX_M4 + {7, OperandInfo603}, // Inst #6396 = PseudoVMSLTU_VX_M4_MASK + {5, OperandInfo571}, // Inst #6397 = PseudoVMSLTU_VX_M8 + {7, OperandInfo604}, // Inst #6398 = PseudoVMSLTU_VX_M8_MASK + {5, OperandInfo70}, // Inst #6399 = PseudoVMSLTU_VX_MF2 + {7, OperandInfo601}, // Inst #6400 = PseudoVMSLTU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6401 = PseudoVMSLTU_VX_MF4 + {7, OperandInfo601}, // Inst #6402 = PseudoVMSLTU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6403 = PseudoVMSLTU_VX_MF8 + {7, OperandInfo601}, // Inst #6404 = PseudoVMSLTU_VX_MF8_MASK + {4, OperandInfo605}, // Inst #6405 = PseudoVMSLT_VI + {5, OperandInfo62}, // Inst #6406 = PseudoVMSLT_VV_M1 + {7, OperandInfo593}, // Inst #6407 = PseudoVMSLT_VV_M1_MASK + {5, OperandInfo561}, // Inst #6408 = PseudoVMSLT_VV_M2 + {7, OperandInfo594}, // Inst #6409 = PseudoVMSLT_VV_M2_MASK + {5, OperandInfo562}, // Inst #6410 = PseudoVMSLT_VV_M4 + {7, OperandInfo595}, // Inst #6411 = PseudoVMSLT_VV_M4_MASK + {5, OperandInfo563}, // Inst #6412 = PseudoVMSLT_VV_M8 + {7, OperandInfo596}, // Inst #6413 = PseudoVMSLT_VV_M8_MASK + {5, OperandInfo62}, // Inst #6414 = PseudoVMSLT_VV_MF2 + {7, OperandInfo593}, // Inst #6415 = PseudoVMSLT_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6416 = PseudoVMSLT_VV_MF4 + {7, OperandInfo593}, // Inst #6417 = PseudoVMSLT_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6418 = PseudoVMSLT_VV_MF8 + {7, OperandInfo593}, // Inst #6419 = PseudoVMSLT_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6420 = PseudoVMSLT_VX_M1 + {7, OperandInfo601}, // Inst #6421 = PseudoVMSLT_VX_M1_MASK + {5, OperandInfo569}, // Inst #6422 = PseudoVMSLT_VX_M2 + {7, OperandInfo602}, // Inst #6423 = PseudoVMSLT_VX_M2_MASK + {5, OperandInfo570}, // Inst #6424 = PseudoVMSLT_VX_M4 + {7, OperandInfo603}, // Inst #6425 = PseudoVMSLT_VX_M4_MASK + {5, OperandInfo571}, // Inst #6426 = PseudoVMSLT_VX_M8 + {7, OperandInfo604}, // Inst #6427 = PseudoVMSLT_VX_M8_MASK + {5, OperandInfo70}, // Inst #6428 = PseudoVMSLT_VX_MF2 + {7, OperandInfo601}, // Inst #6429 = PseudoVMSLT_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6430 = PseudoVMSLT_VX_MF4 + {7, OperandInfo601}, // Inst #6431 = PseudoVMSLT_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6432 = PseudoVMSLT_VX_MF8 + {7, OperandInfo601}, // Inst #6433 = PseudoVMSLT_VX_MF8_MASK + {5, OperandInfo90}, // Inst #6434 = PseudoVMSNE_VI_M1 + {7, OperandInfo597}, // Inst #6435 = PseudoVMSNE_VI_M1_MASK + {5, OperandInfo554}, // Inst #6436 = PseudoVMSNE_VI_M2 + {7, OperandInfo598}, // Inst #6437 = PseudoVMSNE_VI_M2_MASK + {5, OperandInfo555}, // Inst #6438 = PseudoVMSNE_VI_M4 + {7, OperandInfo599}, // Inst #6439 = PseudoVMSNE_VI_M4_MASK + {5, OperandInfo556}, // Inst #6440 = PseudoVMSNE_VI_M8 + {7, OperandInfo600}, // Inst #6441 = PseudoVMSNE_VI_M8_MASK + {5, OperandInfo90}, // Inst #6442 = PseudoVMSNE_VI_MF2 + {7, OperandInfo597}, // Inst #6443 = PseudoVMSNE_VI_MF2_MASK + {5, OperandInfo90}, // Inst #6444 = PseudoVMSNE_VI_MF4 + {7, OperandInfo597}, // Inst #6445 = PseudoVMSNE_VI_MF4_MASK + {5, OperandInfo90}, // Inst #6446 = PseudoVMSNE_VI_MF8 + {7, OperandInfo597}, // Inst #6447 = PseudoVMSNE_VI_MF8_MASK + {5, OperandInfo62}, // Inst #6448 = PseudoVMSNE_VV_M1 + {7, OperandInfo593}, // Inst #6449 = PseudoVMSNE_VV_M1_MASK + {5, OperandInfo561}, // Inst #6450 = PseudoVMSNE_VV_M2 + {7, OperandInfo594}, // Inst #6451 = PseudoVMSNE_VV_M2_MASK + {5, OperandInfo562}, // Inst #6452 = PseudoVMSNE_VV_M4 + {7, OperandInfo595}, // Inst #6453 = PseudoVMSNE_VV_M4_MASK + {5, OperandInfo563}, // Inst #6454 = PseudoVMSNE_VV_M8 + {7, OperandInfo596}, // Inst #6455 = PseudoVMSNE_VV_M8_MASK + {5, OperandInfo62}, // Inst #6456 = PseudoVMSNE_VV_MF2 + {7, OperandInfo593}, // Inst #6457 = PseudoVMSNE_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6458 = PseudoVMSNE_VV_MF4 + {7, OperandInfo593}, // Inst #6459 = PseudoVMSNE_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6460 = PseudoVMSNE_VV_MF8 + {7, OperandInfo593}, // Inst #6461 = PseudoVMSNE_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6462 = PseudoVMSNE_VX_M1 + {7, OperandInfo601}, // Inst #6463 = PseudoVMSNE_VX_M1_MASK + {5, OperandInfo569}, // Inst #6464 = PseudoVMSNE_VX_M2 + {7, OperandInfo602}, // Inst #6465 = PseudoVMSNE_VX_M2_MASK + {5, OperandInfo570}, // Inst #6466 = PseudoVMSNE_VX_M4 + {7, OperandInfo603}, // Inst #6467 = PseudoVMSNE_VX_M4_MASK + {5, OperandInfo571}, // Inst #6468 = PseudoVMSNE_VX_M8 + {7, OperandInfo604}, // Inst #6469 = PseudoVMSNE_VX_M8_MASK + {5, OperandInfo70}, // Inst #6470 = PseudoVMSNE_VX_MF2 + {7, OperandInfo601}, // Inst #6471 = PseudoVMSNE_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6472 = PseudoVMSNE_VX_MF4 + {7, OperandInfo601}, // Inst #6473 = PseudoVMSNE_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6474 = PseudoVMSNE_VX_MF8 + {7, OperandInfo601}, // Inst #6475 = PseudoVMSNE_VX_MF8_MASK + {4, OperandInfo252}, // Inst #6476 = PseudoVMSOF_M_B1 + {4, OperandInfo252}, // Inst #6477 = PseudoVMSOF_M_B16 + {6, OperandInfo353}, // Inst #6478 = PseudoVMSOF_M_B16_MASK + {6, OperandInfo353}, // Inst #6479 = PseudoVMSOF_M_B1_MASK + {4, OperandInfo252}, // Inst #6480 = PseudoVMSOF_M_B2 + {6, OperandInfo353}, // Inst #6481 = PseudoVMSOF_M_B2_MASK + {4, OperandInfo252}, // Inst #6482 = PseudoVMSOF_M_B32 + {6, OperandInfo353}, // Inst #6483 = PseudoVMSOF_M_B32_MASK + {4, OperandInfo252}, // Inst #6484 = PseudoVMSOF_M_B4 + {6, OperandInfo353}, // Inst #6485 = PseudoVMSOF_M_B4_MASK + {4, OperandInfo252}, // Inst #6486 = PseudoVMSOF_M_B64 + {6, OperandInfo353}, // Inst #6487 = PseudoVMSOF_M_B64_MASK + {4, OperandInfo252}, // Inst #6488 = PseudoVMSOF_M_B8 + {6, OperandInfo353}, // Inst #6489 = PseudoVMSOF_M_B8_MASK + {5, OperandInfo62}, // Inst #6490 = PseudoVMULHSU_VV_M1 + {8, OperandInfo63}, // Inst #6491 = PseudoVMULHSU_VV_M1_MASK + {5, OperandInfo64}, // Inst #6492 = PseudoVMULHSU_VV_M2 + {8, OperandInfo65}, // Inst #6493 = PseudoVMULHSU_VV_M2_MASK + {5, OperandInfo66}, // Inst #6494 = PseudoVMULHSU_VV_M4 + {8, OperandInfo67}, // Inst #6495 = PseudoVMULHSU_VV_M4_MASK + {5, OperandInfo68}, // Inst #6496 = PseudoVMULHSU_VV_M8 + {8, OperandInfo69}, // Inst #6497 = PseudoVMULHSU_VV_M8_MASK + {5, OperandInfo62}, // Inst #6498 = PseudoVMULHSU_VV_MF2 + {8, OperandInfo63}, // Inst #6499 = PseudoVMULHSU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6500 = PseudoVMULHSU_VV_MF4 + {8, OperandInfo63}, // Inst #6501 = PseudoVMULHSU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6502 = PseudoVMULHSU_VV_MF8 + {8, OperandInfo63}, // Inst #6503 = PseudoVMULHSU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6504 = PseudoVMULHSU_VX_M1 + {8, OperandInfo71}, // Inst #6505 = PseudoVMULHSU_VX_M1_MASK + {5, OperandInfo72}, // Inst #6506 = PseudoVMULHSU_VX_M2 + {8, OperandInfo73}, // Inst #6507 = PseudoVMULHSU_VX_M2_MASK + {5, OperandInfo74}, // Inst #6508 = PseudoVMULHSU_VX_M4 + {8, OperandInfo75}, // Inst #6509 = PseudoVMULHSU_VX_M4_MASK + {5, OperandInfo76}, // Inst #6510 = PseudoVMULHSU_VX_M8 + {8, OperandInfo77}, // Inst #6511 = PseudoVMULHSU_VX_M8_MASK + {5, OperandInfo70}, // Inst #6512 = PseudoVMULHSU_VX_MF2 + {8, OperandInfo71}, // Inst #6513 = PseudoVMULHSU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6514 = PseudoVMULHSU_VX_MF4 + {8, OperandInfo71}, // Inst #6515 = PseudoVMULHSU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6516 = PseudoVMULHSU_VX_MF8 + {8, OperandInfo71}, // Inst #6517 = PseudoVMULHSU_VX_MF8_MASK + {5, OperandInfo62}, // Inst #6518 = PseudoVMULHU_VV_M1 + {8, OperandInfo63}, // Inst #6519 = PseudoVMULHU_VV_M1_MASK + {5, OperandInfo64}, // Inst #6520 = PseudoVMULHU_VV_M2 + {8, OperandInfo65}, // Inst #6521 = PseudoVMULHU_VV_M2_MASK + {5, OperandInfo66}, // Inst #6522 = PseudoVMULHU_VV_M4 + {8, OperandInfo67}, // Inst #6523 = PseudoVMULHU_VV_M4_MASK + {5, OperandInfo68}, // Inst #6524 = PseudoVMULHU_VV_M8 + {8, OperandInfo69}, // Inst #6525 = PseudoVMULHU_VV_M8_MASK + {5, OperandInfo62}, // Inst #6526 = PseudoVMULHU_VV_MF2 + {8, OperandInfo63}, // Inst #6527 = PseudoVMULHU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6528 = PseudoVMULHU_VV_MF4 + {8, OperandInfo63}, // Inst #6529 = PseudoVMULHU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6530 = PseudoVMULHU_VV_MF8 + {8, OperandInfo63}, // Inst #6531 = PseudoVMULHU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6532 = PseudoVMULHU_VX_M1 + {8, OperandInfo71}, // Inst #6533 = PseudoVMULHU_VX_M1_MASK + {5, OperandInfo72}, // Inst #6534 = PseudoVMULHU_VX_M2 + {8, OperandInfo73}, // Inst #6535 = PseudoVMULHU_VX_M2_MASK + {5, OperandInfo74}, // Inst #6536 = PseudoVMULHU_VX_M4 + {8, OperandInfo75}, // Inst #6537 = PseudoVMULHU_VX_M4_MASK + {5, OperandInfo76}, // Inst #6538 = PseudoVMULHU_VX_M8 + {8, OperandInfo77}, // Inst #6539 = PseudoVMULHU_VX_M8_MASK + {5, OperandInfo70}, // Inst #6540 = PseudoVMULHU_VX_MF2 + {8, OperandInfo71}, // Inst #6541 = PseudoVMULHU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6542 = PseudoVMULHU_VX_MF4 + {8, OperandInfo71}, // Inst #6543 = PseudoVMULHU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6544 = PseudoVMULHU_VX_MF8 + {8, OperandInfo71}, // Inst #6545 = PseudoVMULHU_VX_MF8_MASK + {5, OperandInfo62}, // Inst #6546 = PseudoVMULH_VV_M1 + {8, OperandInfo63}, // Inst #6547 = PseudoVMULH_VV_M1_MASK + {5, OperandInfo64}, // Inst #6548 = PseudoVMULH_VV_M2 + {8, OperandInfo65}, // Inst #6549 = PseudoVMULH_VV_M2_MASK + {5, OperandInfo66}, // Inst #6550 = PseudoVMULH_VV_M4 + {8, OperandInfo67}, // Inst #6551 = PseudoVMULH_VV_M4_MASK + {5, OperandInfo68}, // Inst #6552 = PseudoVMULH_VV_M8 + {8, OperandInfo69}, // Inst #6553 = PseudoVMULH_VV_M8_MASK + {5, OperandInfo62}, // Inst #6554 = PseudoVMULH_VV_MF2 + {8, OperandInfo63}, // Inst #6555 = PseudoVMULH_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6556 = PseudoVMULH_VV_MF4 + {8, OperandInfo63}, // Inst #6557 = PseudoVMULH_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6558 = PseudoVMULH_VV_MF8 + {8, OperandInfo63}, // Inst #6559 = PseudoVMULH_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6560 = PseudoVMULH_VX_M1 + {8, OperandInfo71}, // Inst #6561 = PseudoVMULH_VX_M1_MASK + {5, OperandInfo72}, // Inst #6562 = PseudoVMULH_VX_M2 + {8, OperandInfo73}, // Inst #6563 = PseudoVMULH_VX_M2_MASK + {5, OperandInfo74}, // Inst #6564 = PseudoVMULH_VX_M4 + {8, OperandInfo75}, // Inst #6565 = PseudoVMULH_VX_M4_MASK + {5, OperandInfo76}, // Inst #6566 = PseudoVMULH_VX_M8 + {8, OperandInfo77}, // Inst #6567 = PseudoVMULH_VX_M8_MASK + {5, OperandInfo70}, // Inst #6568 = PseudoVMULH_VX_MF2 + {8, OperandInfo71}, // Inst #6569 = PseudoVMULH_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6570 = PseudoVMULH_VX_MF4 + {8, OperandInfo71}, // Inst #6571 = PseudoVMULH_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6572 = PseudoVMULH_VX_MF8 + {8, OperandInfo71}, // Inst #6573 = PseudoVMULH_VX_MF8_MASK + {5, OperandInfo62}, // Inst #6574 = PseudoVMUL_VV_M1 + {8, OperandInfo63}, // Inst #6575 = PseudoVMUL_VV_M1_MASK + {5, OperandInfo64}, // Inst #6576 = PseudoVMUL_VV_M2 + {8, OperandInfo65}, // Inst #6577 = PseudoVMUL_VV_M2_MASK + {5, OperandInfo66}, // Inst #6578 = PseudoVMUL_VV_M4 + {8, OperandInfo67}, // Inst #6579 = PseudoVMUL_VV_M4_MASK + {5, OperandInfo68}, // Inst #6580 = PseudoVMUL_VV_M8 + {8, OperandInfo69}, // Inst #6581 = PseudoVMUL_VV_M8_MASK + {5, OperandInfo62}, // Inst #6582 = PseudoVMUL_VV_MF2 + {8, OperandInfo63}, // Inst #6583 = PseudoVMUL_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6584 = PseudoVMUL_VV_MF4 + {8, OperandInfo63}, // Inst #6585 = PseudoVMUL_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6586 = PseudoVMUL_VV_MF8 + {8, OperandInfo63}, // Inst #6587 = PseudoVMUL_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6588 = PseudoVMUL_VX_M1 + {8, OperandInfo71}, // Inst #6589 = PseudoVMUL_VX_M1_MASK + {5, OperandInfo72}, // Inst #6590 = PseudoVMUL_VX_M2 + {8, OperandInfo73}, // Inst #6591 = PseudoVMUL_VX_M2_MASK + {5, OperandInfo74}, // Inst #6592 = PseudoVMUL_VX_M4 + {8, OperandInfo75}, // Inst #6593 = PseudoVMUL_VX_M4_MASK + {5, OperandInfo76}, // Inst #6594 = PseudoVMUL_VX_M8 + {8, OperandInfo77}, // Inst #6595 = PseudoVMUL_VX_M8_MASK + {5, OperandInfo70}, // Inst #6596 = PseudoVMUL_VX_MF2 + {8, OperandInfo71}, // Inst #6597 = PseudoVMUL_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6598 = PseudoVMUL_VX_MF4 + {8, OperandInfo71}, // Inst #6599 = PseudoVMUL_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6600 = PseudoVMUL_VX_MF8 + {8, OperandInfo71}, // Inst #6601 = PseudoVMUL_VX_MF8_MASK + {2, OperandInfo609}, // Inst #6602 = PseudoVMV1R_V + {2, OperandInfo610}, // Inst #6603 = PseudoVMV2R_V + {2, OperandInfo611}, // Inst #6604 = PseudoVMV4R_V + {2, OperandInfo612}, // Inst #6605 = PseudoVMV8R_V + {5, OperandInfo613}, // Inst #6606 = PseudoVMV_S_X_M1 + {5, OperandInfo614}, // Inst #6607 = PseudoVMV_S_X_M2 + {5, OperandInfo615}, // Inst #6608 = PseudoVMV_S_X_M4 + {5, OperandInfo616}, // Inst #6609 = PseudoVMV_S_X_M8 + {5, OperandInfo613}, // Inst #6610 = PseudoVMV_S_X_MF2 + {5, OperandInfo613}, // Inst #6611 = PseudoVMV_S_X_MF4 + {5, OperandInfo613}, // Inst #6612 = PseudoVMV_S_X_MF8 + {4, OperandInfo617}, // Inst #6613 = PseudoVMV_V_I_M1 + {4, OperandInfo618}, // Inst #6614 = PseudoVMV_V_I_M2 + {4, OperandInfo619}, // Inst #6615 = PseudoVMV_V_I_M4 + {4, OperandInfo620}, // Inst #6616 = PseudoVMV_V_I_M8 + {4, OperandInfo617}, // Inst #6617 = PseudoVMV_V_I_MF2 + {4, OperandInfo617}, // Inst #6618 = PseudoVMV_V_I_MF4 + {4, OperandInfo617}, // Inst #6619 = PseudoVMV_V_I_MF8 + {4, OperandInfo154}, // Inst #6620 = PseudoVMV_V_V_M1 + {4, OperandInfo156}, // Inst #6621 = PseudoVMV_V_V_M2 + {4, OperandInfo158}, // Inst #6622 = PseudoVMV_V_V_M4 + {4, OperandInfo160}, // Inst #6623 = PseudoVMV_V_V_M8 + {4, OperandInfo154}, // Inst #6624 = PseudoVMV_V_V_MF2 + {4, OperandInfo154}, // Inst #6625 = PseudoVMV_V_V_MF4 + {4, OperandInfo154}, // Inst #6626 = PseudoVMV_V_V_MF8 + {4, OperandInfo359}, // Inst #6627 = PseudoVMV_V_X_M1 + {4, OperandInfo361}, // Inst #6628 = PseudoVMV_V_X_M2 + {4, OperandInfo363}, // Inst #6629 = PseudoVMV_V_X_M4 + {4, OperandInfo365}, // Inst #6630 = PseudoVMV_V_X_M8 + {4, OperandInfo359}, // Inst #6631 = PseudoVMV_V_X_MF2 + {4, OperandInfo359}, // Inst #6632 = PseudoVMV_V_X_MF4 + {4, OperandInfo359}, // Inst #6633 = PseudoVMV_V_X_MF8 + {3, OperandInfo621}, // Inst #6634 = PseudoVMV_X_S_M1 + {3, OperandInfo622}, // Inst #6635 = PseudoVMV_X_S_M2 + {3, OperandInfo623}, // Inst #6636 = PseudoVMV_X_S_M4 + {3, OperandInfo624}, // Inst #6637 = PseudoVMV_X_S_M8 + {3, OperandInfo621}, // Inst #6638 = PseudoVMV_X_S_MF2 + {3, OperandInfo621}, // Inst #6639 = PseudoVMV_X_S_MF4 + {3, OperandInfo621}, // Inst #6640 = PseudoVMV_X_S_MF8 + {5, OperandInfo62}, // Inst #6641 = PseudoVMXNOR_MM_M1 + {5, OperandInfo62}, // Inst #6642 = PseudoVMXNOR_MM_M2 + {5, OperandInfo62}, // Inst #6643 = PseudoVMXNOR_MM_M4 + {5, OperandInfo62}, // Inst #6644 = PseudoVMXNOR_MM_M8 + {5, OperandInfo62}, // Inst #6645 = PseudoVMXNOR_MM_MF2 + {5, OperandInfo62}, // Inst #6646 = PseudoVMXNOR_MM_MF4 + {5, OperandInfo62}, // Inst #6647 = PseudoVMXNOR_MM_MF8 + {5, OperandInfo62}, // Inst #6648 = PseudoVMXOR_MM_M1 + {5, OperandInfo62}, // Inst #6649 = PseudoVMXOR_MM_M2 + {5, OperandInfo62}, // Inst #6650 = PseudoVMXOR_MM_M4 + {5, OperandInfo62}, // Inst #6651 = PseudoVMXOR_MM_M8 + {5, OperandInfo62}, // Inst #6652 = PseudoVMXOR_MM_MF2 + {5, OperandInfo62}, // Inst #6653 = PseudoVMXOR_MM_MF4 + {5, OperandInfo62}, // Inst #6654 = PseudoVMXOR_MM_MF8 + {5, OperandInfo554}, // Inst #6655 = PseudoVNCLIPU_WI_M1 + {8, OperandInfo625}, // Inst #6656 = PseudoVNCLIPU_WI_M1_MASK + {5, OperandInfo626}, // Inst #6657 = PseudoVNCLIPU_WI_M2 + {8, OperandInfo627}, // Inst #6658 = PseudoVNCLIPU_WI_M2_MASK + {5, OperandInfo628}, // Inst #6659 = PseudoVNCLIPU_WI_M4 + {8, OperandInfo629}, // Inst #6660 = PseudoVNCLIPU_WI_M4_MASK + {5, OperandInfo90}, // Inst #6661 = PseudoVNCLIPU_WI_MF2 + {8, OperandInfo91}, // Inst #6662 = PseudoVNCLIPU_WI_MF2_MASK + {5, OperandInfo90}, // Inst #6663 = PseudoVNCLIPU_WI_MF4 + {8, OperandInfo91}, // Inst #6664 = PseudoVNCLIPU_WI_MF4_MASK + {5, OperandInfo90}, // Inst #6665 = PseudoVNCLIPU_WI_MF8 + {8, OperandInfo91}, // Inst #6666 = PseudoVNCLIPU_WI_MF8_MASK + {5, OperandInfo630}, // Inst #6667 = PseudoVNCLIPU_WV_M1 + {8, OperandInfo631}, // Inst #6668 = PseudoVNCLIPU_WV_M1_MASK + {5, OperandInfo632}, // Inst #6669 = PseudoVNCLIPU_WV_M2 + {8, OperandInfo633}, // Inst #6670 = PseudoVNCLIPU_WV_M2_MASK + {5, OperandInfo634}, // Inst #6671 = PseudoVNCLIPU_WV_M4 + {8, OperandInfo635}, // Inst #6672 = PseudoVNCLIPU_WV_M4_MASK + {5, OperandInfo62}, // Inst #6673 = PseudoVNCLIPU_WV_MF2 + {8, OperandInfo63}, // Inst #6674 = PseudoVNCLIPU_WV_MF2_MASK + {5, OperandInfo62}, // Inst #6675 = PseudoVNCLIPU_WV_MF4 + {8, OperandInfo63}, // Inst #6676 = PseudoVNCLIPU_WV_MF4_MASK + {5, OperandInfo62}, // Inst #6677 = PseudoVNCLIPU_WV_MF8 + {8, OperandInfo63}, // Inst #6678 = PseudoVNCLIPU_WV_MF8_MASK + {5, OperandInfo569}, // Inst #6679 = PseudoVNCLIPU_WX_M1 + {8, OperandInfo636}, // Inst #6680 = PseudoVNCLIPU_WX_M1_MASK + {5, OperandInfo637}, // Inst #6681 = PseudoVNCLIPU_WX_M2 + {8, OperandInfo638}, // Inst #6682 = PseudoVNCLIPU_WX_M2_MASK + {5, OperandInfo639}, // Inst #6683 = PseudoVNCLIPU_WX_M4 + {8, OperandInfo640}, // Inst #6684 = PseudoVNCLIPU_WX_M4_MASK + {5, OperandInfo70}, // Inst #6685 = PseudoVNCLIPU_WX_MF2 + {8, OperandInfo71}, // Inst #6686 = PseudoVNCLIPU_WX_MF2_MASK + {5, OperandInfo70}, // Inst #6687 = PseudoVNCLIPU_WX_MF4 + {8, OperandInfo71}, // Inst #6688 = PseudoVNCLIPU_WX_MF4_MASK + {5, OperandInfo70}, // Inst #6689 = PseudoVNCLIPU_WX_MF8 + {8, OperandInfo71}, // Inst #6690 = PseudoVNCLIPU_WX_MF8_MASK + {5, OperandInfo554}, // Inst #6691 = PseudoVNCLIP_WI_M1 + {8, OperandInfo625}, // Inst #6692 = PseudoVNCLIP_WI_M1_MASK + {5, OperandInfo626}, // Inst #6693 = PseudoVNCLIP_WI_M2 + {8, OperandInfo627}, // Inst #6694 = PseudoVNCLIP_WI_M2_MASK + {5, OperandInfo628}, // Inst #6695 = PseudoVNCLIP_WI_M4 + {8, OperandInfo629}, // Inst #6696 = PseudoVNCLIP_WI_M4_MASK + {5, OperandInfo90}, // Inst #6697 = PseudoVNCLIP_WI_MF2 + {8, OperandInfo91}, // Inst #6698 = PseudoVNCLIP_WI_MF2_MASK + {5, OperandInfo90}, // Inst #6699 = PseudoVNCLIP_WI_MF4 + {8, OperandInfo91}, // Inst #6700 = PseudoVNCLIP_WI_MF4_MASK + {5, OperandInfo90}, // Inst #6701 = PseudoVNCLIP_WI_MF8 + {8, OperandInfo91}, // Inst #6702 = PseudoVNCLIP_WI_MF8_MASK + {5, OperandInfo630}, // Inst #6703 = PseudoVNCLIP_WV_M1 + {8, OperandInfo631}, // Inst #6704 = PseudoVNCLIP_WV_M1_MASK + {5, OperandInfo632}, // Inst #6705 = PseudoVNCLIP_WV_M2 + {8, OperandInfo633}, // Inst #6706 = PseudoVNCLIP_WV_M2_MASK + {5, OperandInfo634}, // Inst #6707 = PseudoVNCLIP_WV_M4 + {8, OperandInfo635}, // Inst #6708 = PseudoVNCLIP_WV_M4_MASK + {5, OperandInfo62}, // Inst #6709 = PseudoVNCLIP_WV_MF2 + {8, OperandInfo63}, // Inst #6710 = PseudoVNCLIP_WV_MF2_MASK + {5, OperandInfo62}, // Inst #6711 = PseudoVNCLIP_WV_MF4 + {8, OperandInfo63}, // Inst #6712 = PseudoVNCLIP_WV_MF4_MASK + {5, OperandInfo62}, // Inst #6713 = PseudoVNCLIP_WV_MF8 + {8, OperandInfo63}, // Inst #6714 = PseudoVNCLIP_WV_MF8_MASK + {5, OperandInfo569}, // Inst #6715 = PseudoVNCLIP_WX_M1 + {8, OperandInfo636}, // Inst #6716 = PseudoVNCLIP_WX_M1_MASK + {5, OperandInfo637}, // Inst #6717 = PseudoVNCLIP_WX_M2 + {8, OperandInfo638}, // Inst #6718 = PseudoVNCLIP_WX_M2_MASK + {5, OperandInfo639}, // Inst #6719 = PseudoVNCLIP_WX_M4 + {8, OperandInfo640}, // Inst #6720 = PseudoVNCLIP_WX_M4_MASK + {5, OperandInfo70}, // Inst #6721 = PseudoVNCLIP_WX_MF2 + {8, OperandInfo71}, // Inst #6722 = PseudoVNCLIP_WX_MF2_MASK + {5, OperandInfo70}, // Inst #6723 = PseudoVNCLIP_WX_MF4 + {8, OperandInfo71}, // Inst #6724 = PseudoVNCLIP_WX_MF4_MASK + {5, OperandInfo70}, // Inst #6725 = PseudoVNCLIP_WX_MF8 + {8, OperandInfo71}, // Inst #6726 = PseudoVNCLIP_WX_MF8_MASK + {7, OperandInfo190}, // Inst #6727 = PseudoVNMSAC_VV_M1 + {7, OperandInfo191}, // Inst #6728 = PseudoVNMSAC_VV_M1_MASK + {7, OperandInfo192}, // Inst #6729 = PseudoVNMSAC_VV_M2 + {7, OperandInfo193}, // Inst #6730 = PseudoVNMSAC_VV_M2_MASK + {7, OperandInfo194}, // Inst #6731 = PseudoVNMSAC_VV_M4 + {7, OperandInfo195}, // Inst #6732 = PseudoVNMSAC_VV_M4_MASK + {7, OperandInfo196}, // Inst #6733 = PseudoVNMSAC_VV_M8 + {7, OperandInfo197}, // Inst #6734 = PseudoVNMSAC_VV_M8_MASK + {7, OperandInfo190}, // Inst #6735 = PseudoVNMSAC_VV_MF2 + {7, OperandInfo191}, // Inst #6736 = PseudoVNMSAC_VV_MF2_MASK + {7, OperandInfo190}, // Inst #6737 = PseudoVNMSAC_VV_MF4 + {7, OperandInfo191}, // Inst #6738 = PseudoVNMSAC_VV_MF4_MASK + {7, OperandInfo190}, // Inst #6739 = PseudoVNMSAC_VV_MF8 + {7, OperandInfo191}, // Inst #6740 = PseudoVNMSAC_VV_MF8_MASK + {7, OperandInfo541}, // Inst #6741 = PseudoVNMSAC_VX_M1 + {7, OperandInfo542}, // Inst #6742 = PseudoVNMSAC_VX_M1_MASK + {7, OperandInfo543}, // Inst #6743 = PseudoVNMSAC_VX_M2 + {7, OperandInfo544}, // Inst #6744 = PseudoVNMSAC_VX_M2_MASK + {7, OperandInfo545}, // Inst #6745 = PseudoVNMSAC_VX_M4 + {7, OperandInfo546}, // Inst #6746 = PseudoVNMSAC_VX_M4_MASK + {7, OperandInfo547}, // Inst #6747 = PseudoVNMSAC_VX_M8 + {7, OperandInfo548}, // Inst #6748 = PseudoVNMSAC_VX_M8_MASK + {7, OperandInfo541}, // Inst #6749 = PseudoVNMSAC_VX_MF2 + {7, OperandInfo542}, // Inst #6750 = PseudoVNMSAC_VX_MF2_MASK + {7, OperandInfo541}, // Inst #6751 = PseudoVNMSAC_VX_MF4 + {7, OperandInfo542}, // Inst #6752 = PseudoVNMSAC_VX_MF4_MASK + {7, OperandInfo541}, // Inst #6753 = PseudoVNMSAC_VX_MF8 + {7, OperandInfo542}, // Inst #6754 = PseudoVNMSAC_VX_MF8_MASK + {7, OperandInfo190}, // Inst #6755 = PseudoVNMSUB_VV_M1 + {7, OperandInfo191}, // Inst #6756 = PseudoVNMSUB_VV_M1_MASK + {7, OperandInfo192}, // Inst #6757 = PseudoVNMSUB_VV_M2 + {7, OperandInfo193}, // Inst #6758 = PseudoVNMSUB_VV_M2_MASK + {7, OperandInfo194}, // Inst #6759 = PseudoVNMSUB_VV_M4 + {7, OperandInfo195}, // Inst #6760 = PseudoVNMSUB_VV_M4_MASK + {7, OperandInfo196}, // Inst #6761 = PseudoVNMSUB_VV_M8 + {7, OperandInfo197}, // Inst #6762 = PseudoVNMSUB_VV_M8_MASK + {7, OperandInfo190}, // Inst #6763 = PseudoVNMSUB_VV_MF2 + {7, OperandInfo191}, // Inst #6764 = PseudoVNMSUB_VV_MF2_MASK + {7, OperandInfo190}, // Inst #6765 = PseudoVNMSUB_VV_MF4 + {7, OperandInfo191}, // Inst #6766 = PseudoVNMSUB_VV_MF4_MASK + {7, OperandInfo190}, // Inst #6767 = PseudoVNMSUB_VV_MF8 + {7, OperandInfo191}, // Inst #6768 = PseudoVNMSUB_VV_MF8_MASK + {7, OperandInfo541}, // Inst #6769 = PseudoVNMSUB_VX_M1 + {7, OperandInfo542}, // Inst #6770 = PseudoVNMSUB_VX_M1_MASK + {7, OperandInfo543}, // Inst #6771 = PseudoVNMSUB_VX_M2 + {7, OperandInfo544}, // Inst #6772 = PseudoVNMSUB_VX_M2_MASK + {7, OperandInfo545}, // Inst #6773 = PseudoVNMSUB_VX_M4 + {7, OperandInfo546}, // Inst #6774 = PseudoVNMSUB_VX_M4_MASK + {7, OperandInfo547}, // Inst #6775 = PseudoVNMSUB_VX_M8 + {7, OperandInfo548}, // Inst #6776 = PseudoVNMSUB_VX_M8_MASK + {7, OperandInfo541}, // Inst #6777 = PseudoVNMSUB_VX_MF2 + {7, OperandInfo542}, // Inst #6778 = PseudoVNMSUB_VX_MF2_MASK + {7, OperandInfo541}, // Inst #6779 = PseudoVNMSUB_VX_MF4 + {7, OperandInfo542}, // Inst #6780 = PseudoVNMSUB_VX_MF4_MASK + {7, OperandInfo541}, // Inst #6781 = PseudoVNMSUB_VX_MF8 + {7, OperandInfo542}, // Inst #6782 = PseudoVNMSUB_VX_MF8_MASK + {5, OperandInfo554}, // Inst #6783 = PseudoVNSRA_WI_M1 + {8, OperandInfo625}, // Inst #6784 = PseudoVNSRA_WI_M1_MASK + {5, OperandInfo626}, // Inst #6785 = PseudoVNSRA_WI_M2 + {8, OperandInfo627}, // Inst #6786 = PseudoVNSRA_WI_M2_MASK + {5, OperandInfo628}, // Inst #6787 = PseudoVNSRA_WI_M4 + {8, OperandInfo629}, // Inst #6788 = PseudoVNSRA_WI_M4_MASK + {5, OperandInfo90}, // Inst #6789 = PseudoVNSRA_WI_MF2 + {8, OperandInfo91}, // Inst #6790 = PseudoVNSRA_WI_MF2_MASK + {5, OperandInfo90}, // Inst #6791 = PseudoVNSRA_WI_MF4 + {8, OperandInfo91}, // Inst #6792 = PseudoVNSRA_WI_MF4_MASK + {5, OperandInfo90}, // Inst #6793 = PseudoVNSRA_WI_MF8 + {8, OperandInfo91}, // Inst #6794 = PseudoVNSRA_WI_MF8_MASK + {5, OperandInfo630}, // Inst #6795 = PseudoVNSRA_WV_M1 + {8, OperandInfo631}, // Inst #6796 = PseudoVNSRA_WV_M1_MASK + {5, OperandInfo632}, // Inst #6797 = PseudoVNSRA_WV_M2 + {8, OperandInfo633}, // Inst #6798 = PseudoVNSRA_WV_M2_MASK + {5, OperandInfo634}, // Inst #6799 = PseudoVNSRA_WV_M4 + {8, OperandInfo635}, // Inst #6800 = PseudoVNSRA_WV_M4_MASK + {5, OperandInfo62}, // Inst #6801 = PseudoVNSRA_WV_MF2 + {8, OperandInfo63}, // Inst #6802 = PseudoVNSRA_WV_MF2_MASK + {5, OperandInfo62}, // Inst #6803 = PseudoVNSRA_WV_MF4 + {8, OperandInfo63}, // Inst #6804 = PseudoVNSRA_WV_MF4_MASK + {5, OperandInfo62}, // Inst #6805 = PseudoVNSRA_WV_MF8 + {8, OperandInfo63}, // Inst #6806 = PseudoVNSRA_WV_MF8_MASK + {5, OperandInfo569}, // Inst #6807 = PseudoVNSRA_WX_M1 + {8, OperandInfo636}, // Inst #6808 = PseudoVNSRA_WX_M1_MASK + {5, OperandInfo637}, // Inst #6809 = PseudoVNSRA_WX_M2 + {8, OperandInfo638}, // Inst #6810 = PseudoVNSRA_WX_M2_MASK + {5, OperandInfo639}, // Inst #6811 = PseudoVNSRA_WX_M4 + {8, OperandInfo640}, // Inst #6812 = PseudoVNSRA_WX_M4_MASK + {5, OperandInfo70}, // Inst #6813 = PseudoVNSRA_WX_MF2 + {8, OperandInfo71}, // Inst #6814 = PseudoVNSRA_WX_MF2_MASK + {5, OperandInfo70}, // Inst #6815 = PseudoVNSRA_WX_MF4 + {8, OperandInfo71}, // Inst #6816 = PseudoVNSRA_WX_MF4_MASK + {5, OperandInfo70}, // Inst #6817 = PseudoVNSRA_WX_MF8 + {8, OperandInfo71}, // Inst #6818 = PseudoVNSRA_WX_MF8_MASK + {5, OperandInfo554}, // Inst #6819 = PseudoVNSRL_WI_M1 + {8, OperandInfo625}, // Inst #6820 = PseudoVNSRL_WI_M1_MASK + {5, OperandInfo626}, // Inst #6821 = PseudoVNSRL_WI_M2 + {8, OperandInfo627}, // Inst #6822 = PseudoVNSRL_WI_M2_MASK + {5, OperandInfo628}, // Inst #6823 = PseudoVNSRL_WI_M4 + {8, OperandInfo629}, // Inst #6824 = PseudoVNSRL_WI_M4_MASK + {5, OperandInfo90}, // Inst #6825 = PseudoVNSRL_WI_MF2 + {8, OperandInfo91}, // Inst #6826 = PseudoVNSRL_WI_MF2_MASK + {5, OperandInfo90}, // Inst #6827 = PseudoVNSRL_WI_MF4 + {8, OperandInfo91}, // Inst #6828 = PseudoVNSRL_WI_MF4_MASK + {5, OperandInfo90}, // Inst #6829 = PseudoVNSRL_WI_MF8 + {8, OperandInfo91}, // Inst #6830 = PseudoVNSRL_WI_MF8_MASK + {5, OperandInfo630}, // Inst #6831 = PseudoVNSRL_WV_M1 + {8, OperandInfo631}, // Inst #6832 = PseudoVNSRL_WV_M1_MASK + {5, OperandInfo632}, // Inst #6833 = PseudoVNSRL_WV_M2 + {8, OperandInfo633}, // Inst #6834 = PseudoVNSRL_WV_M2_MASK + {5, OperandInfo634}, // Inst #6835 = PseudoVNSRL_WV_M4 + {8, OperandInfo635}, // Inst #6836 = PseudoVNSRL_WV_M4_MASK + {5, OperandInfo62}, // Inst #6837 = PseudoVNSRL_WV_MF2 + {8, OperandInfo63}, // Inst #6838 = PseudoVNSRL_WV_MF2_MASK + {5, OperandInfo62}, // Inst #6839 = PseudoVNSRL_WV_MF4 + {8, OperandInfo63}, // Inst #6840 = PseudoVNSRL_WV_MF4_MASK + {5, OperandInfo62}, // Inst #6841 = PseudoVNSRL_WV_MF8 + {8, OperandInfo63}, // Inst #6842 = PseudoVNSRL_WV_MF8_MASK + {5, OperandInfo569}, // Inst #6843 = PseudoVNSRL_WX_M1 + {8, OperandInfo636}, // Inst #6844 = PseudoVNSRL_WX_M1_MASK + {5, OperandInfo637}, // Inst #6845 = PseudoVNSRL_WX_M2 + {8, OperandInfo638}, // Inst #6846 = PseudoVNSRL_WX_M2_MASK + {5, OperandInfo639}, // Inst #6847 = PseudoVNSRL_WX_M4 + {8, OperandInfo640}, // Inst #6848 = PseudoVNSRL_WX_M4_MASK + {5, OperandInfo70}, // Inst #6849 = PseudoVNSRL_WX_MF2 + {8, OperandInfo71}, // Inst #6850 = PseudoVNSRL_WX_MF2_MASK + {5, OperandInfo70}, // Inst #6851 = PseudoVNSRL_WX_MF4 + {8, OperandInfo71}, // Inst #6852 = PseudoVNSRL_WX_MF4_MASK + {5, OperandInfo70}, // Inst #6853 = PseudoVNSRL_WX_MF8 + {8, OperandInfo71}, // Inst #6854 = PseudoVNSRL_WX_MF8_MASK + {5, OperandInfo90}, // Inst #6855 = PseudoVOR_VI_M1 + {8, OperandInfo91}, // Inst #6856 = PseudoVOR_VI_M1_MASK + {5, OperandInfo92}, // Inst #6857 = PseudoVOR_VI_M2 + {8, OperandInfo93}, // Inst #6858 = PseudoVOR_VI_M2_MASK + {5, OperandInfo94}, // Inst #6859 = PseudoVOR_VI_M4 + {8, OperandInfo95}, // Inst #6860 = PseudoVOR_VI_M4_MASK + {5, OperandInfo96}, // Inst #6861 = PseudoVOR_VI_M8 + {8, OperandInfo97}, // Inst #6862 = PseudoVOR_VI_M8_MASK + {5, OperandInfo90}, // Inst #6863 = PseudoVOR_VI_MF2 + {8, OperandInfo91}, // Inst #6864 = PseudoVOR_VI_MF2_MASK + {5, OperandInfo90}, // Inst #6865 = PseudoVOR_VI_MF4 + {8, OperandInfo91}, // Inst #6866 = PseudoVOR_VI_MF4_MASK + {5, OperandInfo90}, // Inst #6867 = PseudoVOR_VI_MF8 + {8, OperandInfo91}, // Inst #6868 = PseudoVOR_VI_MF8_MASK + {5, OperandInfo62}, // Inst #6869 = PseudoVOR_VV_M1 + {8, OperandInfo63}, // Inst #6870 = PseudoVOR_VV_M1_MASK + {5, OperandInfo64}, // Inst #6871 = PseudoVOR_VV_M2 + {8, OperandInfo65}, // Inst #6872 = PseudoVOR_VV_M2_MASK + {5, OperandInfo66}, // Inst #6873 = PseudoVOR_VV_M4 + {8, OperandInfo67}, // Inst #6874 = PseudoVOR_VV_M4_MASK + {5, OperandInfo68}, // Inst #6875 = PseudoVOR_VV_M8 + {8, OperandInfo69}, // Inst #6876 = PseudoVOR_VV_M8_MASK + {5, OperandInfo62}, // Inst #6877 = PseudoVOR_VV_MF2 + {8, OperandInfo63}, // Inst #6878 = PseudoVOR_VV_MF2_MASK + {5, OperandInfo62}, // Inst #6879 = PseudoVOR_VV_MF4 + {8, OperandInfo63}, // Inst #6880 = PseudoVOR_VV_MF4_MASK + {5, OperandInfo62}, // Inst #6881 = PseudoVOR_VV_MF8 + {8, OperandInfo63}, // Inst #6882 = PseudoVOR_VV_MF8_MASK + {5, OperandInfo70}, // Inst #6883 = PseudoVOR_VX_M1 + {8, OperandInfo71}, // Inst #6884 = PseudoVOR_VX_M1_MASK + {5, OperandInfo72}, // Inst #6885 = PseudoVOR_VX_M2 + {8, OperandInfo73}, // Inst #6886 = PseudoVOR_VX_M2_MASK + {5, OperandInfo74}, // Inst #6887 = PseudoVOR_VX_M4 + {8, OperandInfo75}, // Inst #6888 = PseudoVOR_VX_M4_MASK + {5, OperandInfo76}, // Inst #6889 = PseudoVOR_VX_M8 + {8, OperandInfo77}, // Inst #6890 = PseudoVOR_VX_M8_MASK + {5, OperandInfo70}, // Inst #6891 = PseudoVOR_VX_MF2 + {8, OperandInfo71}, // Inst #6892 = PseudoVOR_VX_MF2_MASK + {5, OperandInfo70}, // Inst #6893 = PseudoVOR_VX_MF4 + {8, OperandInfo71}, // Inst #6894 = PseudoVOR_VX_MF4_MASK + {5, OperandInfo70}, // Inst #6895 = PseudoVOR_VX_MF8 + {8, OperandInfo71}, // Inst #6896 = PseudoVOR_VX_MF8_MASK + {6, OperandInfo254}, // Inst #6897 = PseudoVREDAND_VS_M1 + {7, OperandInfo191}, // Inst #6898 = PseudoVREDAND_VS_M1_MASK + {6, OperandInfo255}, // Inst #6899 = PseudoVREDAND_VS_M2 + {7, OperandInfo256}, // Inst #6900 = PseudoVREDAND_VS_M2_MASK + {6, OperandInfo257}, // Inst #6901 = PseudoVREDAND_VS_M4 + {7, OperandInfo258}, // Inst #6902 = PseudoVREDAND_VS_M4_MASK + {6, OperandInfo259}, // Inst #6903 = PseudoVREDAND_VS_M8 + {7, OperandInfo260}, // Inst #6904 = PseudoVREDAND_VS_M8_MASK + {6, OperandInfo254}, // Inst #6905 = PseudoVREDAND_VS_MF2 + {7, OperandInfo191}, // Inst #6906 = PseudoVREDAND_VS_MF2_MASK + {6, OperandInfo254}, // Inst #6907 = PseudoVREDAND_VS_MF4 + {7, OperandInfo191}, // Inst #6908 = PseudoVREDAND_VS_MF4_MASK + {6, OperandInfo254}, // Inst #6909 = PseudoVREDAND_VS_MF8 + {7, OperandInfo191}, // Inst #6910 = PseudoVREDAND_VS_MF8_MASK + {6, OperandInfo254}, // Inst #6911 = PseudoVREDMAXU_VS_M1 + {7, OperandInfo191}, // Inst #6912 = PseudoVREDMAXU_VS_M1_MASK + {6, OperandInfo255}, // Inst #6913 = PseudoVREDMAXU_VS_M2 + {7, OperandInfo256}, // Inst #6914 = PseudoVREDMAXU_VS_M2_MASK + {6, OperandInfo257}, // Inst #6915 = PseudoVREDMAXU_VS_M4 + {7, OperandInfo258}, // Inst #6916 = PseudoVREDMAXU_VS_M4_MASK + {6, OperandInfo259}, // Inst #6917 = PseudoVREDMAXU_VS_M8 + {7, OperandInfo260}, // Inst #6918 = PseudoVREDMAXU_VS_M8_MASK + {6, OperandInfo254}, // Inst #6919 = PseudoVREDMAXU_VS_MF2 + {7, OperandInfo191}, // Inst #6920 = PseudoVREDMAXU_VS_MF2_MASK + {6, OperandInfo254}, // Inst #6921 = PseudoVREDMAXU_VS_MF4 + {7, OperandInfo191}, // Inst #6922 = PseudoVREDMAXU_VS_MF4_MASK + {6, OperandInfo254}, // Inst #6923 = PseudoVREDMAXU_VS_MF8 + {7, OperandInfo191}, // Inst #6924 = PseudoVREDMAXU_VS_MF8_MASK + {6, OperandInfo254}, // Inst #6925 = PseudoVREDMAX_VS_M1 + {7, OperandInfo191}, // Inst #6926 = PseudoVREDMAX_VS_M1_MASK + {6, OperandInfo255}, // Inst #6927 = PseudoVREDMAX_VS_M2 + {7, OperandInfo256}, // Inst #6928 = PseudoVREDMAX_VS_M2_MASK + {6, OperandInfo257}, // Inst #6929 = PseudoVREDMAX_VS_M4 + {7, OperandInfo258}, // Inst #6930 = PseudoVREDMAX_VS_M4_MASK + {6, OperandInfo259}, // Inst #6931 = PseudoVREDMAX_VS_M8 + {7, OperandInfo260}, // Inst #6932 = PseudoVREDMAX_VS_M8_MASK + {6, OperandInfo254}, // Inst #6933 = PseudoVREDMAX_VS_MF2 + {7, OperandInfo191}, // Inst #6934 = PseudoVREDMAX_VS_MF2_MASK + {6, OperandInfo254}, // Inst #6935 = PseudoVREDMAX_VS_MF4 + {7, OperandInfo191}, // Inst #6936 = PseudoVREDMAX_VS_MF4_MASK + {6, OperandInfo254}, // Inst #6937 = PseudoVREDMAX_VS_MF8 + {7, OperandInfo191}, // Inst #6938 = PseudoVREDMAX_VS_MF8_MASK + {6, OperandInfo254}, // Inst #6939 = PseudoVREDMINU_VS_M1 + {7, OperandInfo191}, // Inst #6940 = PseudoVREDMINU_VS_M1_MASK + {6, OperandInfo255}, // Inst #6941 = PseudoVREDMINU_VS_M2 + {7, OperandInfo256}, // Inst #6942 = PseudoVREDMINU_VS_M2_MASK + {6, OperandInfo257}, // Inst #6943 = PseudoVREDMINU_VS_M4 + {7, OperandInfo258}, // Inst #6944 = PseudoVREDMINU_VS_M4_MASK + {6, OperandInfo259}, // Inst #6945 = PseudoVREDMINU_VS_M8 + {7, OperandInfo260}, // Inst #6946 = PseudoVREDMINU_VS_M8_MASK + {6, OperandInfo254}, // Inst #6947 = PseudoVREDMINU_VS_MF2 + {7, OperandInfo191}, // Inst #6948 = PseudoVREDMINU_VS_MF2_MASK + {6, OperandInfo254}, // Inst #6949 = PseudoVREDMINU_VS_MF4 + {7, OperandInfo191}, // Inst #6950 = PseudoVREDMINU_VS_MF4_MASK + {6, OperandInfo254}, // Inst #6951 = PseudoVREDMINU_VS_MF8 + {7, OperandInfo191}, // Inst #6952 = PseudoVREDMINU_VS_MF8_MASK + {6, OperandInfo254}, // Inst #6953 = PseudoVREDMIN_VS_M1 + {7, OperandInfo191}, // Inst #6954 = PseudoVREDMIN_VS_M1_MASK + {6, OperandInfo255}, // Inst #6955 = PseudoVREDMIN_VS_M2 + {7, OperandInfo256}, // Inst #6956 = PseudoVREDMIN_VS_M2_MASK + {6, OperandInfo257}, // Inst #6957 = PseudoVREDMIN_VS_M4 + {7, OperandInfo258}, // Inst #6958 = PseudoVREDMIN_VS_M4_MASK + {6, OperandInfo259}, // Inst #6959 = PseudoVREDMIN_VS_M8 + {7, OperandInfo260}, // Inst #6960 = PseudoVREDMIN_VS_M8_MASK + {6, OperandInfo254}, // Inst #6961 = PseudoVREDMIN_VS_MF2 + {7, OperandInfo191}, // Inst #6962 = PseudoVREDMIN_VS_MF2_MASK + {6, OperandInfo254}, // Inst #6963 = PseudoVREDMIN_VS_MF4 + {7, OperandInfo191}, // Inst #6964 = PseudoVREDMIN_VS_MF4_MASK + {6, OperandInfo254}, // Inst #6965 = PseudoVREDMIN_VS_MF8 + {7, OperandInfo191}, // Inst #6966 = PseudoVREDMIN_VS_MF8_MASK + {6, OperandInfo254}, // Inst #6967 = PseudoVREDOR_VS_M1 + {7, OperandInfo191}, // Inst #6968 = PseudoVREDOR_VS_M1_MASK + {6, OperandInfo255}, // Inst #6969 = PseudoVREDOR_VS_M2 + {7, OperandInfo256}, // Inst #6970 = PseudoVREDOR_VS_M2_MASK + {6, OperandInfo257}, // Inst #6971 = PseudoVREDOR_VS_M4 + {7, OperandInfo258}, // Inst #6972 = PseudoVREDOR_VS_M4_MASK + {6, OperandInfo259}, // Inst #6973 = PseudoVREDOR_VS_M8 + {7, OperandInfo260}, // Inst #6974 = PseudoVREDOR_VS_M8_MASK + {6, OperandInfo254}, // Inst #6975 = PseudoVREDOR_VS_MF2 + {7, OperandInfo191}, // Inst #6976 = PseudoVREDOR_VS_MF2_MASK + {6, OperandInfo254}, // Inst #6977 = PseudoVREDOR_VS_MF4 + {7, OperandInfo191}, // Inst #6978 = PseudoVREDOR_VS_MF4_MASK + {6, OperandInfo254}, // Inst #6979 = PseudoVREDOR_VS_MF8 + {7, OperandInfo191}, // Inst #6980 = PseudoVREDOR_VS_MF8_MASK + {6, OperandInfo254}, // Inst #6981 = PseudoVREDSUM_VS_M1 + {7, OperandInfo191}, // Inst #6982 = PseudoVREDSUM_VS_M1_MASK + {6, OperandInfo255}, // Inst #6983 = PseudoVREDSUM_VS_M2 + {7, OperandInfo256}, // Inst #6984 = PseudoVREDSUM_VS_M2_MASK + {6, OperandInfo257}, // Inst #6985 = PseudoVREDSUM_VS_M4 + {7, OperandInfo258}, // Inst #6986 = PseudoVREDSUM_VS_M4_MASK + {6, OperandInfo259}, // Inst #6987 = PseudoVREDSUM_VS_M8 + {7, OperandInfo260}, // Inst #6988 = PseudoVREDSUM_VS_M8_MASK + {6, OperandInfo254}, // Inst #6989 = PseudoVREDSUM_VS_MF2 + {7, OperandInfo191}, // Inst #6990 = PseudoVREDSUM_VS_MF2_MASK + {6, OperandInfo254}, // Inst #6991 = PseudoVREDSUM_VS_MF4 + {7, OperandInfo191}, // Inst #6992 = PseudoVREDSUM_VS_MF4_MASK + {6, OperandInfo254}, // Inst #6993 = PseudoVREDSUM_VS_MF8 + {7, OperandInfo191}, // Inst #6994 = PseudoVREDSUM_VS_MF8_MASK + {6, OperandInfo254}, // Inst #6995 = PseudoVREDXOR_VS_M1 + {7, OperandInfo191}, // Inst #6996 = PseudoVREDXOR_VS_M1_MASK + {6, OperandInfo255}, // Inst #6997 = PseudoVREDXOR_VS_M2 + {7, OperandInfo256}, // Inst #6998 = PseudoVREDXOR_VS_M2_MASK + {6, OperandInfo257}, // Inst #6999 = PseudoVREDXOR_VS_M4 + {7, OperandInfo258}, // Inst #7000 = PseudoVREDXOR_VS_M4_MASK + {6, OperandInfo259}, // Inst #7001 = PseudoVREDXOR_VS_M8 + {7, OperandInfo260}, // Inst #7002 = PseudoVREDXOR_VS_M8_MASK + {6, OperandInfo254}, // Inst #7003 = PseudoVREDXOR_VS_MF2 + {7, OperandInfo191}, // Inst #7004 = PseudoVREDXOR_VS_MF2_MASK + {6, OperandInfo254}, // Inst #7005 = PseudoVREDXOR_VS_MF4 + {7, OperandInfo191}, // Inst #7006 = PseudoVREDXOR_VS_MF4_MASK + {6, OperandInfo254}, // Inst #7007 = PseudoVREDXOR_VS_MF8 + {7, OperandInfo191}, // Inst #7008 = PseudoVREDXOR_VS_MF8_MASK + {3, OperandInfo641}, // Inst #7009 = PseudoVRELOAD2_M1 + {3, OperandInfo642}, // Inst #7010 = PseudoVRELOAD2_M2 + {3, OperandInfo643}, // Inst #7011 = PseudoVRELOAD2_M4 + {3, OperandInfo641}, // Inst #7012 = PseudoVRELOAD2_MF2 + {3, OperandInfo641}, // Inst #7013 = PseudoVRELOAD2_MF4 + {3, OperandInfo641}, // Inst #7014 = PseudoVRELOAD2_MF8 + {3, OperandInfo644}, // Inst #7015 = PseudoVRELOAD3_M1 + {3, OperandInfo645}, // Inst #7016 = PseudoVRELOAD3_M2 + {3, OperandInfo644}, // Inst #7017 = PseudoVRELOAD3_MF2 + {3, OperandInfo644}, // Inst #7018 = PseudoVRELOAD3_MF4 + {3, OperandInfo644}, // Inst #7019 = PseudoVRELOAD3_MF8 + {3, OperandInfo646}, // Inst #7020 = PseudoVRELOAD4_M1 + {3, OperandInfo647}, // Inst #7021 = PseudoVRELOAD4_M2 + {3, OperandInfo646}, // Inst #7022 = PseudoVRELOAD4_MF2 + {3, OperandInfo646}, // Inst #7023 = PseudoVRELOAD4_MF4 + {3, OperandInfo646}, // Inst #7024 = PseudoVRELOAD4_MF8 + {3, OperandInfo648}, // Inst #7025 = PseudoVRELOAD5_M1 + {3, OperandInfo648}, // Inst #7026 = PseudoVRELOAD5_MF2 + {3, OperandInfo648}, // Inst #7027 = PseudoVRELOAD5_MF4 + {3, OperandInfo648}, // Inst #7028 = PseudoVRELOAD5_MF8 + {3, OperandInfo649}, // Inst #7029 = PseudoVRELOAD6_M1 + {3, OperandInfo649}, // Inst #7030 = PseudoVRELOAD6_MF2 + {3, OperandInfo649}, // Inst #7031 = PseudoVRELOAD6_MF4 + {3, OperandInfo649}, // Inst #7032 = PseudoVRELOAD6_MF8 + {3, OperandInfo650}, // Inst #7033 = PseudoVRELOAD7_M1 + {3, OperandInfo650}, // Inst #7034 = PseudoVRELOAD7_MF2 + {3, OperandInfo650}, // Inst #7035 = PseudoVRELOAD7_MF4 + {3, OperandInfo650}, // Inst #7036 = PseudoVRELOAD7_MF8 + {3, OperandInfo651}, // Inst #7037 = PseudoVRELOAD8_M1 + {3, OperandInfo651}, // Inst #7038 = PseudoVRELOAD8_MF2 + {3, OperandInfo651}, // Inst #7039 = PseudoVRELOAD8_MF4 + {3, OperandInfo651}, // Inst #7040 = PseudoVRELOAD8_MF8 + {2, OperandInfo652}, // Inst #7041 = PseudoVRELOAD_M1 + {2, OperandInfo653}, // Inst #7042 = PseudoVRELOAD_M2 + {2, OperandInfo654}, // Inst #7043 = PseudoVRELOAD_M4 + {2, OperandInfo655}, // Inst #7044 = PseudoVRELOAD_M8 + {5, OperandInfo62}, // Inst #7045 = PseudoVREMU_VV_M1 + {8, OperandInfo63}, // Inst #7046 = PseudoVREMU_VV_M1_MASK + {5, OperandInfo64}, // Inst #7047 = PseudoVREMU_VV_M2 + {8, OperandInfo65}, // Inst #7048 = PseudoVREMU_VV_M2_MASK + {5, OperandInfo66}, // Inst #7049 = PseudoVREMU_VV_M4 + {8, OperandInfo67}, // Inst #7050 = PseudoVREMU_VV_M4_MASK + {5, OperandInfo68}, // Inst #7051 = PseudoVREMU_VV_M8 + {8, OperandInfo69}, // Inst #7052 = PseudoVREMU_VV_M8_MASK + {5, OperandInfo62}, // Inst #7053 = PseudoVREMU_VV_MF2 + {8, OperandInfo63}, // Inst #7054 = PseudoVREMU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #7055 = PseudoVREMU_VV_MF4 + {8, OperandInfo63}, // Inst #7056 = PseudoVREMU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #7057 = PseudoVREMU_VV_MF8 + {8, OperandInfo63}, // Inst #7058 = PseudoVREMU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #7059 = PseudoVREMU_VX_M1 + {8, OperandInfo71}, // Inst #7060 = PseudoVREMU_VX_M1_MASK + {5, OperandInfo72}, // Inst #7061 = PseudoVREMU_VX_M2 + {8, OperandInfo73}, // Inst #7062 = PseudoVREMU_VX_M2_MASK + {5, OperandInfo74}, // Inst #7063 = PseudoVREMU_VX_M4 + {8, OperandInfo75}, // Inst #7064 = PseudoVREMU_VX_M4_MASK + {5, OperandInfo76}, // Inst #7065 = PseudoVREMU_VX_M8 + {8, OperandInfo77}, // Inst #7066 = PseudoVREMU_VX_M8_MASK + {5, OperandInfo70}, // Inst #7067 = PseudoVREMU_VX_MF2 + {8, OperandInfo71}, // Inst #7068 = PseudoVREMU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #7069 = PseudoVREMU_VX_MF4 + {8, OperandInfo71}, // Inst #7070 = PseudoVREMU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #7071 = PseudoVREMU_VX_MF8 + {8, OperandInfo71}, // Inst #7072 = PseudoVREMU_VX_MF8_MASK + {5, OperandInfo62}, // Inst #7073 = PseudoVREM_VV_M1 + {8, OperandInfo63}, // Inst #7074 = PseudoVREM_VV_M1_MASK + {5, OperandInfo64}, // Inst #7075 = PseudoVREM_VV_M2 + {8, OperandInfo65}, // Inst #7076 = PseudoVREM_VV_M2_MASK + {5, OperandInfo66}, // Inst #7077 = PseudoVREM_VV_M4 + {8, OperandInfo67}, // Inst #7078 = PseudoVREM_VV_M4_MASK + {5, OperandInfo68}, // Inst #7079 = PseudoVREM_VV_M8 + {8, OperandInfo69}, // Inst #7080 = PseudoVREM_VV_M8_MASK + {5, OperandInfo62}, // Inst #7081 = PseudoVREM_VV_MF2 + {8, OperandInfo63}, // Inst #7082 = PseudoVREM_VV_MF2_MASK + {5, OperandInfo62}, // Inst #7083 = PseudoVREM_VV_MF4 + {8, OperandInfo63}, // Inst #7084 = PseudoVREM_VV_MF4_MASK + {5, OperandInfo62}, // Inst #7085 = PseudoVREM_VV_MF8 + {8, OperandInfo63}, // Inst #7086 = PseudoVREM_VV_MF8_MASK + {5, OperandInfo70}, // Inst #7087 = PseudoVREM_VX_M1 + {8, OperandInfo71}, // Inst #7088 = PseudoVREM_VX_M1_MASK + {5, OperandInfo72}, // Inst #7089 = PseudoVREM_VX_M2 + {8, OperandInfo73}, // Inst #7090 = PseudoVREM_VX_M2_MASK + {5, OperandInfo74}, // Inst #7091 = PseudoVREM_VX_M4 + {8, OperandInfo75}, // Inst #7092 = PseudoVREM_VX_M4_MASK + {5, OperandInfo76}, // Inst #7093 = PseudoVREM_VX_M8 + {8, OperandInfo77}, // Inst #7094 = PseudoVREM_VX_M8_MASK + {5, OperandInfo70}, // Inst #7095 = PseudoVREM_VX_MF2 + {8, OperandInfo71}, // Inst #7096 = PseudoVREM_VX_MF2_MASK + {5, OperandInfo70}, // Inst #7097 = PseudoVREM_VX_MF4 + {8, OperandInfo71}, // Inst #7098 = PseudoVREM_VX_MF4_MASK + {5, OperandInfo70}, // Inst #7099 = PseudoVREM_VX_MF8 + {8, OperandInfo71}, // Inst #7100 = PseudoVREM_VX_MF8_MASK + {5, OperandInfo303}, // Inst #7101 = PseudoVRGATHEREI16_VV_M1_M1 + {8, OperandInfo304}, // Inst #7102 = PseudoVRGATHEREI16_VV_M1_M1_MASK + {5, OperandInfo656}, // Inst #7103 = PseudoVRGATHEREI16_VV_M1_M2 + {8, OperandInfo657}, // Inst #7104 = PseudoVRGATHEREI16_VV_M1_M2_MASK + {5, OperandInfo303}, // Inst #7105 = PseudoVRGATHEREI16_VV_M1_MF2 + {8, OperandInfo304}, // Inst #7106 = PseudoVRGATHEREI16_VV_M1_MF2_MASK + {5, OperandInfo303}, // Inst #7107 = PseudoVRGATHEREI16_VV_M1_MF4 + {8, OperandInfo304}, // Inst #7108 = PseudoVRGATHEREI16_VV_M1_MF4_MASK + {5, OperandInfo305}, // Inst #7109 = PseudoVRGATHEREI16_VV_M2_M1 + {8, OperandInfo306}, // Inst #7110 = PseudoVRGATHEREI16_VV_M2_M1_MASK + {5, OperandInfo658}, // Inst #7111 = PseudoVRGATHEREI16_VV_M2_M2 + {8, OperandInfo659}, // Inst #7112 = PseudoVRGATHEREI16_VV_M2_M2_MASK + {5, OperandInfo660}, // Inst #7113 = PseudoVRGATHEREI16_VV_M2_M4 + {8, OperandInfo661}, // Inst #7114 = PseudoVRGATHEREI16_VV_M2_M4_MASK + {5, OperandInfo305}, // Inst #7115 = PseudoVRGATHEREI16_VV_M2_MF2 + {8, OperandInfo306}, // Inst #7116 = PseudoVRGATHEREI16_VV_M2_MF2_MASK + {5, OperandInfo662}, // Inst #7117 = PseudoVRGATHEREI16_VV_M4_M1 + {8, OperandInfo663}, // Inst #7118 = PseudoVRGATHEREI16_VV_M4_M1_MASK + {5, OperandInfo309}, // Inst #7119 = PseudoVRGATHEREI16_VV_M4_M2 + {8, OperandInfo310}, // Inst #7120 = PseudoVRGATHEREI16_VV_M4_M2_MASK + {5, OperandInfo664}, // Inst #7121 = PseudoVRGATHEREI16_VV_M4_M4 + {8, OperandInfo665}, // Inst #7122 = PseudoVRGATHEREI16_VV_M4_M4_MASK + {5, OperandInfo666}, // Inst #7123 = PseudoVRGATHEREI16_VV_M4_M8 + {8, OperandInfo667}, // Inst #7124 = PseudoVRGATHEREI16_VV_M4_M8_MASK + {5, OperandInfo668}, // Inst #7125 = PseudoVRGATHEREI16_VV_M8_M2 + {8, OperandInfo669}, // Inst #7126 = PseudoVRGATHEREI16_VV_M8_M2_MASK + {5, OperandInfo313}, // Inst #7127 = PseudoVRGATHEREI16_VV_M8_M4 + {8, OperandInfo314}, // Inst #7128 = PseudoVRGATHEREI16_VV_M8_M4_MASK + {5, OperandInfo670}, // Inst #7129 = PseudoVRGATHEREI16_VV_M8_M8 + {8, OperandInfo671}, // Inst #7130 = PseudoVRGATHEREI16_VV_M8_M8_MASK + {5, OperandInfo303}, // Inst #7131 = PseudoVRGATHEREI16_VV_MF2_M1 + {8, OperandInfo304}, // Inst #7132 = PseudoVRGATHEREI16_VV_MF2_M1_MASK + {5, OperandInfo303}, // Inst #7133 = PseudoVRGATHEREI16_VV_MF2_MF2 + {8, OperandInfo304}, // Inst #7134 = PseudoVRGATHEREI16_VV_MF2_MF2_MASK + {5, OperandInfo303}, // Inst #7135 = PseudoVRGATHEREI16_VV_MF2_MF4 + {8, OperandInfo304}, // Inst #7136 = PseudoVRGATHEREI16_VV_MF2_MF4_MASK + {5, OperandInfo303}, // Inst #7137 = PseudoVRGATHEREI16_VV_MF2_MF8 + {8, OperandInfo304}, // Inst #7138 = PseudoVRGATHEREI16_VV_MF2_MF8_MASK + {5, OperandInfo303}, // Inst #7139 = PseudoVRGATHEREI16_VV_MF4_MF2 + {8, OperandInfo304}, // Inst #7140 = PseudoVRGATHEREI16_VV_MF4_MF2_MASK + {5, OperandInfo303}, // Inst #7141 = PseudoVRGATHEREI16_VV_MF4_MF4 + {8, OperandInfo304}, // Inst #7142 = PseudoVRGATHEREI16_VV_MF4_MF4_MASK + {5, OperandInfo303}, // Inst #7143 = PseudoVRGATHEREI16_VV_MF4_MF8 + {8, OperandInfo304}, // Inst #7144 = PseudoVRGATHEREI16_VV_MF4_MF8_MASK + {5, OperandInfo303}, // Inst #7145 = PseudoVRGATHEREI16_VV_MF8_MF4 + {8, OperandInfo304}, // Inst #7146 = PseudoVRGATHEREI16_VV_MF8_MF4_MASK + {5, OperandInfo303}, // Inst #7147 = PseudoVRGATHEREI16_VV_MF8_MF8 + {8, OperandInfo304}, // Inst #7148 = PseudoVRGATHEREI16_VV_MF8_MF8_MASK + {5, OperandInfo553}, // Inst #7149 = PseudoVRGATHER_VI_M1 + {8, OperandInfo672}, // Inst #7150 = PseudoVRGATHER_VI_M1_MASK + {5, OperandInfo673}, // Inst #7151 = PseudoVRGATHER_VI_M2 + {8, OperandInfo674}, // Inst #7152 = PseudoVRGATHER_VI_M2_MASK + {5, OperandInfo675}, // Inst #7153 = PseudoVRGATHER_VI_M4 + {8, OperandInfo676}, // Inst #7154 = PseudoVRGATHER_VI_M4_MASK + {5, OperandInfo677}, // Inst #7155 = PseudoVRGATHER_VI_M8 + {8, OperandInfo678}, // Inst #7156 = PseudoVRGATHER_VI_M8_MASK + {5, OperandInfo553}, // Inst #7157 = PseudoVRGATHER_VI_MF2 + {8, OperandInfo672}, // Inst #7158 = PseudoVRGATHER_VI_MF2_MASK + {5, OperandInfo553}, // Inst #7159 = PseudoVRGATHER_VI_MF4 + {8, OperandInfo672}, // Inst #7160 = PseudoVRGATHER_VI_MF4_MASK + {5, OperandInfo553}, // Inst #7161 = PseudoVRGATHER_VI_MF8 + {8, OperandInfo672}, // Inst #7162 = PseudoVRGATHER_VI_MF8_MASK + {5, OperandInfo303}, // Inst #7163 = PseudoVRGATHER_VV_M1 + {8, OperandInfo304}, // Inst #7164 = PseudoVRGATHER_VV_M1_MASK + {5, OperandInfo658}, // Inst #7165 = PseudoVRGATHER_VV_M2 + {8, OperandInfo659}, // Inst #7166 = PseudoVRGATHER_VV_M2_MASK + {5, OperandInfo664}, // Inst #7167 = PseudoVRGATHER_VV_M4 + {8, OperandInfo665}, // Inst #7168 = PseudoVRGATHER_VV_M4_MASK + {5, OperandInfo670}, // Inst #7169 = PseudoVRGATHER_VV_M8 + {8, OperandInfo671}, // Inst #7170 = PseudoVRGATHER_VV_M8_MASK + {5, OperandInfo303}, // Inst #7171 = PseudoVRGATHER_VV_MF2 + {8, OperandInfo304}, // Inst #7172 = PseudoVRGATHER_VV_MF2_MASK + {5, OperandInfo303}, // Inst #7173 = PseudoVRGATHER_VV_MF4 + {8, OperandInfo304}, // Inst #7174 = PseudoVRGATHER_VV_MF4_MASK + {5, OperandInfo303}, // Inst #7175 = PseudoVRGATHER_VV_MF8 + {8, OperandInfo304}, // Inst #7176 = PseudoVRGATHER_VV_MF8_MASK + {5, OperandInfo568}, // Inst #7177 = PseudoVRGATHER_VX_M1 + {8, OperandInfo679}, // Inst #7178 = PseudoVRGATHER_VX_M1_MASK + {5, OperandInfo680}, // Inst #7179 = PseudoVRGATHER_VX_M2 + {8, OperandInfo681}, // Inst #7180 = PseudoVRGATHER_VX_M2_MASK + {5, OperandInfo682}, // Inst #7181 = PseudoVRGATHER_VX_M4 + {8, OperandInfo683}, // Inst #7182 = PseudoVRGATHER_VX_M4_MASK + {5, OperandInfo684}, // Inst #7183 = PseudoVRGATHER_VX_M8 + {8, OperandInfo685}, // Inst #7184 = PseudoVRGATHER_VX_M8_MASK + {5, OperandInfo568}, // Inst #7185 = PseudoVRGATHER_VX_MF2 + {8, OperandInfo679}, // Inst #7186 = PseudoVRGATHER_VX_MF2_MASK + {5, OperandInfo568}, // Inst #7187 = PseudoVRGATHER_VX_MF4 + {8, OperandInfo679}, // Inst #7188 = PseudoVRGATHER_VX_MF4_MASK + {5, OperandInfo568}, // Inst #7189 = PseudoVRGATHER_VX_MF8 + {8, OperandInfo679}, // Inst #7190 = PseudoVRGATHER_VX_MF8_MASK + {5, OperandInfo90}, // Inst #7191 = PseudoVRSUB_VI_M1 + {8, OperandInfo91}, // Inst #7192 = PseudoVRSUB_VI_M1_MASK + {5, OperandInfo92}, // Inst #7193 = PseudoVRSUB_VI_M2 + {8, OperandInfo93}, // Inst #7194 = PseudoVRSUB_VI_M2_MASK + {5, OperandInfo94}, // Inst #7195 = PseudoVRSUB_VI_M4 + {8, OperandInfo95}, // Inst #7196 = PseudoVRSUB_VI_M4_MASK + {5, OperandInfo96}, // Inst #7197 = PseudoVRSUB_VI_M8 + {8, OperandInfo97}, // Inst #7198 = PseudoVRSUB_VI_M8_MASK + {5, OperandInfo90}, // Inst #7199 = PseudoVRSUB_VI_MF2 + {8, OperandInfo91}, // Inst #7200 = PseudoVRSUB_VI_MF2_MASK + {5, OperandInfo90}, // Inst #7201 = PseudoVRSUB_VI_MF4 + {8, OperandInfo91}, // Inst #7202 = PseudoVRSUB_VI_MF4_MASK + {5, OperandInfo90}, // Inst #7203 = PseudoVRSUB_VI_MF8 + {8, OperandInfo91}, // Inst #7204 = PseudoVRSUB_VI_MF8_MASK + {5, OperandInfo70}, // Inst #7205 = PseudoVRSUB_VX_M1 + {8, OperandInfo71}, // Inst #7206 = PseudoVRSUB_VX_M1_MASK + {5, OperandInfo72}, // Inst #7207 = PseudoVRSUB_VX_M2 + {8, OperandInfo73}, // Inst #7208 = PseudoVRSUB_VX_M2_MASK + {5, OperandInfo74}, // Inst #7209 = PseudoVRSUB_VX_M4 + {8, OperandInfo75}, // Inst #7210 = PseudoVRSUB_VX_M4_MASK + {5, OperandInfo76}, // Inst #7211 = PseudoVRSUB_VX_M8 + {8, OperandInfo77}, // Inst #7212 = PseudoVRSUB_VX_M8_MASK + {5, OperandInfo70}, // Inst #7213 = PseudoVRSUB_VX_MF2 + {8, OperandInfo71}, // Inst #7214 = PseudoVRSUB_VX_MF2_MASK + {5, OperandInfo70}, // Inst #7215 = PseudoVRSUB_VX_MF4 + {8, OperandInfo71}, // Inst #7216 = PseudoVRSUB_VX_MF4_MASK + {5, OperandInfo70}, // Inst #7217 = PseudoVRSUB_VX_MF8 + {8, OperandInfo71}, // Inst #7218 = PseudoVRSUB_VX_MF8_MASK + {5, OperandInfo90}, // Inst #7219 = PseudoVSADDU_VI_M1 + {8, OperandInfo91}, // Inst #7220 = PseudoVSADDU_VI_M1_MASK + {5, OperandInfo92}, // Inst #7221 = PseudoVSADDU_VI_M2 + {8, OperandInfo93}, // Inst #7222 = PseudoVSADDU_VI_M2_MASK + {5, OperandInfo94}, // Inst #7223 = PseudoVSADDU_VI_M4 + {8, OperandInfo95}, // Inst #7224 = PseudoVSADDU_VI_M4_MASK + {5, OperandInfo96}, // Inst #7225 = PseudoVSADDU_VI_M8 + {8, OperandInfo97}, // Inst #7226 = PseudoVSADDU_VI_M8_MASK + {5, OperandInfo90}, // Inst #7227 = PseudoVSADDU_VI_MF2 + {8, OperandInfo91}, // Inst #7228 = PseudoVSADDU_VI_MF2_MASK + {5, OperandInfo90}, // Inst #7229 = PseudoVSADDU_VI_MF4 + {8, OperandInfo91}, // Inst #7230 = PseudoVSADDU_VI_MF4_MASK + {5, OperandInfo90}, // Inst #7231 = PseudoVSADDU_VI_MF8 + {8, OperandInfo91}, // Inst #7232 = PseudoVSADDU_VI_MF8_MASK + {5, OperandInfo62}, // Inst #7233 = PseudoVSADDU_VV_M1 + {8, OperandInfo63}, // Inst #7234 = PseudoVSADDU_VV_M1_MASK + {5, OperandInfo64}, // Inst #7235 = PseudoVSADDU_VV_M2 + {8, OperandInfo65}, // Inst #7236 = PseudoVSADDU_VV_M2_MASK + {5, OperandInfo66}, // Inst #7237 = PseudoVSADDU_VV_M4 + {8, OperandInfo67}, // Inst #7238 = PseudoVSADDU_VV_M4_MASK + {5, OperandInfo68}, // Inst #7239 = PseudoVSADDU_VV_M8 + {8, OperandInfo69}, // Inst #7240 = PseudoVSADDU_VV_M8_MASK + {5, OperandInfo62}, // Inst #7241 = PseudoVSADDU_VV_MF2 + {8, OperandInfo63}, // Inst #7242 = PseudoVSADDU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #7243 = PseudoVSADDU_VV_MF4 + {8, OperandInfo63}, // Inst #7244 = PseudoVSADDU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #7245 = PseudoVSADDU_VV_MF8 + {8, OperandInfo63}, // Inst #7246 = PseudoVSADDU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #7247 = PseudoVSADDU_VX_M1 + {8, OperandInfo71}, // Inst #7248 = PseudoVSADDU_VX_M1_MASK + {5, OperandInfo72}, // Inst #7249 = PseudoVSADDU_VX_M2 + {8, OperandInfo73}, // Inst #7250 = PseudoVSADDU_VX_M2_MASK + {5, OperandInfo74}, // Inst #7251 = PseudoVSADDU_VX_M4 + {8, OperandInfo75}, // Inst #7252 = PseudoVSADDU_VX_M4_MASK + {5, OperandInfo76}, // Inst #7253 = PseudoVSADDU_VX_M8 + {8, OperandInfo77}, // Inst #7254 = PseudoVSADDU_VX_M8_MASK + {5, OperandInfo70}, // Inst #7255 = PseudoVSADDU_VX_MF2 + {8, OperandInfo71}, // Inst #7256 = PseudoVSADDU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #7257 = PseudoVSADDU_VX_MF4 + {8, OperandInfo71}, // Inst #7258 = PseudoVSADDU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #7259 = PseudoVSADDU_VX_MF8 + {8, OperandInfo71}, // Inst #7260 = PseudoVSADDU_VX_MF8_MASK + {5, OperandInfo90}, // Inst #7261 = PseudoVSADD_VI_M1 + {8, OperandInfo91}, // Inst #7262 = PseudoVSADD_VI_M1_MASK + {5, OperandInfo92}, // Inst #7263 = PseudoVSADD_VI_M2 + {8, OperandInfo93}, // Inst #7264 = PseudoVSADD_VI_M2_MASK + {5, OperandInfo94}, // Inst #7265 = PseudoVSADD_VI_M4 + {8, OperandInfo95}, // Inst #7266 = PseudoVSADD_VI_M4_MASK + {5, OperandInfo96}, // Inst #7267 = PseudoVSADD_VI_M8 + {8, OperandInfo97}, // Inst #7268 = PseudoVSADD_VI_M8_MASK + {5, OperandInfo90}, // Inst #7269 = PseudoVSADD_VI_MF2 + {8, OperandInfo91}, // Inst #7270 = PseudoVSADD_VI_MF2_MASK + {5, OperandInfo90}, // Inst #7271 = PseudoVSADD_VI_MF4 + {8, OperandInfo91}, // Inst #7272 = PseudoVSADD_VI_MF4_MASK + {5, OperandInfo90}, // Inst #7273 = PseudoVSADD_VI_MF8 + {8, OperandInfo91}, // Inst #7274 = PseudoVSADD_VI_MF8_MASK + {5, OperandInfo62}, // Inst #7275 = PseudoVSADD_VV_M1 + {8, OperandInfo63}, // Inst #7276 = PseudoVSADD_VV_M1_MASK + {5, OperandInfo64}, // Inst #7277 = PseudoVSADD_VV_M2 + {8, OperandInfo65}, // Inst #7278 = PseudoVSADD_VV_M2_MASK + {5, OperandInfo66}, // Inst #7279 = PseudoVSADD_VV_M4 + {8, OperandInfo67}, // Inst #7280 = PseudoVSADD_VV_M4_MASK + {5, OperandInfo68}, // Inst #7281 = PseudoVSADD_VV_M8 + {8, OperandInfo69}, // Inst #7282 = PseudoVSADD_VV_M8_MASK + {5, OperandInfo62}, // Inst #7283 = PseudoVSADD_VV_MF2 + {8, OperandInfo63}, // Inst #7284 = PseudoVSADD_VV_MF2_MASK + {5, OperandInfo62}, // Inst #7285 = PseudoVSADD_VV_MF4 + {8, OperandInfo63}, // Inst #7286 = PseudoVSADD_VV_MF4_MASK + {5, OperandInfo62}, // Inst #7287 = PseudoVSADD_VV_MF8 + {8, OperandInfo63}, // Inst #7288 = PseudoVSADD_VV_MF8_MASK + {5, OperandInfo70}, // Inst #7289 = PseudoVSADD_VX_M1 + {8, OperandInfo71}, // Inst #7290 = PseudoVSADD_VX_M1_MASK + {5, OperandInfo72}, // Inst #7291 = PseudoVSADD_VX_M2 + {8, OperandInfo73}, // Inst #7292 = PseudoVSADD_VX_M2_MASK + {5, OperandInfo74}, // Inst #7293 = PseudoVSADD_VX_M4 + {8, OperandInfo75}, // Inst #7294 = PseudoVSADD_VX_M4_MASK + {5, OperandInfo76}, // Inst #7295 = PseudoVSADD_VX_M8 + {8, OperandInfo77}, // Inst #7296 = PseudoVSADD_VX_M8_MASK + {5, OperandInfo70}, // Inst #7297 = PseudoVSADD_VX_MF2 + {8, OperandInfo71}, // Inst #7298 = PseudoVSADD_VX_MF2_MASK + {5, OperandInfo70}, // Inst #7299 = PseudoVSADD_VX_MF4 + {8, OperandInfo71}, // Inst #7300 = PseudoVSADD_VX_MF4_MASK + {5, OperandInfo70}, // Inst #7301 = PseudoVSADD_VX_MF8 + {8, OperandInfo71}, // Inst #7302 = PseudoVSADD_VX_MF8_MASK + {6, OperandInfo82}, // Inst #7303 = PseudoVSBC_VVM_M1 + {6, OperandInfo83}, // Inst #7304 = PseudoVSBC_VVM_M2 + {6, OperandInfo84}, // Inst #7305 = PseudoVSBC_VVM_M4 + {6, OperandInfo85}, // Inst #7306 = PseudoVSBC_VVM_M8 + {6, OperandInfo82}, // Inst #7307 = PseudoVSBC_VVM_MF2 + {6, OperandInfo82}, // Inst #7308 = PseudoVSBC_VVM_MF4 + {6, OperandInfo82}, // Inst #7309 = PseudoVSBC_VVM_MF8 + {6, OperandInfo86}, // Inst #7310 = PseudoVSBC_VXM_M1 + {6, OperandInfo87}, // Inst #7311 = PseudoVSBC_VXM_M2 + {6, OperandInfo88}, // Inst #7312 = PseudoVSBC_VXM_M4 + {6, OperandInfo89}, // Inst #7313 = PseudoVSBC_VXM_M8 + {6, OperandInfo86}, // Inst #7314 = PseudoVSBC_VXM_MF2 + {6, OperandInfo86}, // Inst #7315 = PseudoVSBC_VXM_MF4 + {6, OperandInfo86}, // Inst #7316 = PseudoVSBC_VXM_MF8 + {4, OperandInfo359}, // Inst #7317 = PseudoVSE16_V_M1 + {5, OperandInfo686}, // Inst #7318 = PseudoVSE16_V_M1_MASK + {4, OperandInfo361}, // Inst #7319 = PseudoVSE16_V_M2 + {5, OperandInfo687}, // Inst #7320 = PseudoVSE16_V_M2_MASK + {4, OperandInfo363}, // Inst #7321 = PseudoVSE16_V_M4 + {5, OperandInfo688}, // Inst #7322 = PseudoVSE16_V_M4_MASK + {4, OperandInfo365}, // Inst #7323 = PseudoVSE16_V_M8 + {5, OperandInfo689}, // Inst #7324 = PseudoVSE16_V_M8_MASK + {4, OperandInfo359}, // Inst #7325 = PseudoVSE16_V_MF2 + {5, OperandInfo686}, // Inst #7326 = PseudoVSE16_V_MF2_MASK + {4, OperandInfo359}, // Inst #7327 = PseudoVSE16_V_MF4 + {5, OperandInfo686}, // Inst #7328 = PseudoVSE16_V_MF4_MASK + {4, OperandInfo359}, // Inst #7329 = PseudoVSE32_V_M1 + {5, OperandInfo686}, // Inst #7330 = PseudoVSE32_V_M1_MASK + {4, OperandInfo361}, // Inst #7331 = PseudoVSE32_V_M2 + {5, OperandInfo687}, // Inst #7332 = PseudoVSE32_V_M2_MASK + {4, OperandInfo363}, // Inst #7333 = PseudoVSE32_V_M4 + {5, OperandInfo688}, // Inst #7334 = PseudoVSE32_V_M4_MASK + {4, OperandInfo365}, // Inst #7335 = PseudoVSE32_V_M8 + {5, OperandInfo689}, // Inst #7336 = PseudoVSE32_V_M8_MASK + {4, OperandInfo359}, // Inst #7337 = PseudoVSE32_V_MF2 + {5, OperandInfo686}, // Inst #7338 = PseudoVSE32_V_MF2_MASK + {4, OperandInfo359}, // Inst #7339 = PseudoVSE64_V_M1 + {5, OperandInfo686}, // Inst #7340 = PseudoVSE64_V_M1_MASK + {4, OperandInfo361}, // Inst #7341 = PseudoVSE64_V_M2 + {5, OperandInfo687}, // Inst #7342 = PseudoVSE64_V_M2_MASK + {4, OperandInfo363}, // Inst #7343 = PseudoVSE64_V_M4 + {5, OperandInfo688}, // Inst #7344 = PseudoVSE64_V_M4_MASK + {4, OperandInfo365}, // Inst #7345 = PseudoVSE64_V_M8 + {5, OperandInfo689}, // Inst #7346 = PseudoVSE64_V_M8_MASK + {4, OperandInfo359}, // Inst #7347 = PseudoVSE8_V_M1 + {5, OperandInfo686}, // Inst #7348 = PseudoVSE8_V_M1_MASK + {4, OperandInfo361}, // Inst #7349 = PseudoVSE8_V_M2 + {5, OperandInfo687}, // Inst #7350 = PseudoVSE8_V_M2_MASK + {4, OperandInfo363}, // Inst #7351 = PseudoVSE8_V_M4 + {5, OperandInfo688}, // Inst #7352 = PseudoVSE8_V_M4_MASK + {4, OperandInfo365}, // Inst #7353 = PseudoVSE8_V_M8 + {5, OperandInfo689}, // Inst #7354 = PseudoVSE8_V_M8_MASK + {4, OperandInfo359}, // Inst #7355 = PseudoVSE8_V_MF2 + {5, OperandInfo686}, // Inst #7356 = PseudoVSE8_V_MF2_MASK + {4, OperandInfo359}, // Inst #7357 = PseudoVSE8_V_MF4 + {5, OperandInfo686}, // Inst #7358 = PseudoVSE8_V_MF4_MASK + {4, OperandInfo359}, // Inst #7359 = PseudoVSE8_V_MF8 + {5, OperandInfo686}, // Inst #7360 = PseudoVSE8_V_MF8_MASK + {3, OperandInfo690}, // Inst #7361 = PseudoVSETIVLI + {3, OperandInfo691}, // Inst #7362 = PseudoVSETVLI + {3, OperandInfo692}, // Inst #7363 = PseudoVSETVLIX0 + {4, OperandInfo252}, // Inst #7364 = PseudoVSEXT_VF2_M1 + {7, OperandInfo253}, // Inst #7365 = PseudoVSEXT_VF2_M1_MASK + {4, OperandInfo318}, // Inst #7366 = PseudoVSEXT_VF2_M2 + {7, OperandInfo307}, // Inst #7367 = PseudoVSEXT_VF2_M2_MASK + {4, OperandInfo319}, // Inst #7368 = PseudoVSEXT_VF2_M4 + {7, OperandInfo311}, // Inst #7369 = PseudoVSEXT_VF2_M4_MASK + {4, OperandInfo320}, // Inst #7370 = PseudoVSEXT_VF2_M8 + {7, OperandInfo315}, // Inst #7371 = PseudoVSEXT_VF2_M8_MASK + {4, OperandInfo252}, // Inst #7372 = PseudoVSEXT_VF2_MF2 + {7, OperandInfo253}, // Inst #7373 = PseudoVSEXT_VF2_MF2_MASK + {4, OperandInfo252}, // Inst #7374 = PseudoVSEXT_VF2_MF4 + {7, OperandInfo253}, // Inst #7375 = PseudoVSEXT_VF2_MF4_MASK + {4, OperandInfo252}, // Inst #7376 = PseudoVSEXT_VF4_M1 + {7, OperandInfo253}, // Inst #7377 = PseudoVSEXT_VF4_M1_MASK + {4, OperandInfo318}, // Inst #7378 = PseudoVSEXT_VF4_M2 + {7, OperandInfo307}, // Inst #7379 = PseudoVSEXT_VF4_M2_MASK + {4, OperandInfo355}, // Inst #7380 = PseudoVSEXT_VF4_M4 + {7, OperandInfo693}, // Inst #7381 = PseudoVSEXT_VF4_M4_MASK + {4, OperandInfo694}, // Inst #7382 = PseudoVSEXT_VF4_M8 + {7, OperandInfo695}, // Inst #7383 = PseudoVSEXT_VF4_M8_MASK + {4, OperandInfo252}, // Inst #7384 = PseudoVSEXT_VF4_MF2 + {7, OperandInfo253}, // Inst #7385 = PseudoVSEXT_VF4_MF2_MASK + {4, OperandInfo252}, // Inst #7386 = PseudoVSEXT_VF8_M1 + {7, OperandInfo253}, // Inst #7387 = PseudoVSEXT_VF8_M1_MASK + {4, OperandInfo318}, // Inst #7388 = PseudoVSEXT_VF8_M2 + {7, OperandInfo307}, // Inst #7389 = PseudoVSEXT_VF8_M2_MASK + {4, OperandInfo355}, // Inst #7390 = PseudoVSEXT_VF8_M4 + {7, OperandInfo693}, // Inst #7391 = PseudoVSEXT_VF8_M4_MASK + {4, OperandInfo357}, // Inst #7392 = PseudoVSEXT_VF8_M8 + {7, OperandInfo696}, // Inst #7393 = PseudoVSEXT_VF8_M8_MASK + {5, OperandInfo70}, // Inst #7394 = PseudoVSLIDE1DOWN_VX_M1 + {8, OperandInfo71}, // Inst #7395 = PseudoVSLIDE1DOWN_VX_M1_MASK + {5, OperandInfo72}, // Inst #7396 = PseudoVSLIDE1DOWN_VX_M2 + {8, OperandInfo73}, // Inst #7397 = PseudoVSLIDE1DOWN_VX_M2_MASK + {5, OperandInfo74}, // Inst #7398 = PseudoVSLIDE1DOWN_VX_M4 + {8, OperandInfo75}, // Inst #7399 = PseudoVSLIDE1DOWN_VX_M4_MASK + {5, OperandInfo76}, // Inst #7400 = PseudoVSLIDE1DOWN_VX_M8 + {8, OperandInfo77}, // Inst #7401 = PseudoVSLIDE1DOWN_VX_M8_MASK + {5, OperandInfo70}, // Inst #7402 = PseudoVSLIDE1DOWN_VX_MF2 + {8, OperandInfo71}, // Inst #7403 = PseudoVSLIDE1DOWN_VX_MF2_MASK + {5, OperandInfo70}, // Inst #7404 = PseudoVSLIDE1DOWN_VX_MF4 + {8, OperandInfo71}, // Inst #7405 = PseudoVSLIDE1DOWN_VX_MF4_MASK + {5, OperandInfo70}, // Inst #7406 = PseudoVSLIDE1DOWN_VX_MF8 + {8, OperandInfo71}, // Inst #7407 = PseudoVSLIDE1DOWN_VX_MF8_MASK + {5, OperandInfo568}, // Inst #7408 = PseudoVSLIDE1UP_VX_M1 + {8, OperandInfo679}, // Inst #7409 = PseudoVSLIDE1UP_VX_M1_MASK + {5, OperandInfo680}, // Inst #7410 = PseudoVSLIDE1UP_VX_M2 + {8, OperandInfo681}, // Inst #7411 = PseudoVSLIDE1UP_VX_M2_MASK + {5, OperandInfo682}, // Inst #7412 = PseudoVSLIDE1UP_VX_M4 + {8, OperandInfo683}, // Inst #7413 = PseudoVSLIDE1UP_VX_M4_MASK + {5, OperandInfo684}, // Inst #7414 = PseudoVSLIDE1UP_VX_M8 + {8, OperandInfo685}, // Inst #7415 = PseudoVSLIDE1UP_VX_M8_MASK + {5, OperandInfo568}, // Inst #7416 = PseudoVSLIDE1UP_VX_MF2 + {8, OperandInfo679}, // Inst #7417 = PseudoVSLIDE1UP_VX_MF2_MASK + {5, OperandInfo568}, // Inst #7418 = PseudoVSLIDE1UP_VX_MF4 + {8, OperandInfo679}, // Inst #7419 = PseudoVSLIDE1UP_VX_MF4_MASK + {5, OperandInfo568}, // Inst #7420 = PseudoVSLIDE1UP_VX_MF8 + {8, OperandInfo679}, // Inst #7421 = PseudoVSLIDE1UP_VX_MF8_MASK + {6, OperandInfo697}, // Inst #7422 = PseudoVSLIDEDOWN_VI_M1 + {7, OperandInfo698}, // Inst #7423 = PseudoVSLIDEDOWN_VI_M1_MASK + {6, OperandInfo699}, // Inst #7424 = PseudoVSLIDEDOWN_VI_M2 + {7, OperandInfo700}, // Inst #7425 = PseudoVSLIDEDOWN_VI_M2_MASK + {6, OperandInfo701}, // Inst #7426 = PseudoVSLIDEDOWN_VI_M4 + {7, OperandInfo702}, // Inst #7427 = PseudoVSLIDEDOWN_VI_M4_MASK + {6, OperandInfo703}, // Inst #7428 = PseudoVSLIDEDOWN_VI_M8 + {7, OperandInfo704}, // Inst #7429 = PseudoVSLIDEDOWN_VI_M8_MASK + {6, OperandInfo697}, // Inst #7430 = PseudoVSLIDEDOWN_VI_MF2 + {7, OperandInfo698}, // Inst #7431 = PseudoVSLIDEDOWN_VI_MF2_MASK + {6, OperandInfo697}, // Inst #7432 = PseudoVSLIDEDOWN_VI_MF4 + {7, OperandInfo698}, // Inst #7433 = PseudoVSLIDEDOWN_VI_MF4_MASK + {6, OperandInfo697}, // Inst #7434 = PseudoVSLIDEDOWN_VI_MF8 + {7, OperandInfo698}, // Inst #7435 = PseudoVSLIDEDOWN_VI_MF8_MASK + {6, OperandInfo705}, // Inst #7436 = PseudoVSLIDEDOWN_VX_M1 + {7, OperandInfo706}, // Inst #7437 = PseudoVSLIDEDOWN_VX_M1_MASK + {6, OperandInfo707}, // Inst #7438 = PseudoVSLIDEDOWN_VX_M2 + {7, OperandInfo708}, // Inst #7439 = PseudoVSLIDEDOWN_VX_M2_MASK + {6, OperandInfo709}, // Inst #7440 = PseudoVSLIDEDOWN_VX_M4 + {7, OperandInfo710}, // Inst #7441 = PseudoVSLIDEDOWN_VX_M4_MASK + {6, OperandInfo711}, // Inst #7442 = PseudoVSLIDEDOWN_VX_M8 + {7, OperandInfo712}, // Inst #7443 = PseudoVSLIDEDOWN_VX_M8_MASK + {6, OperandInfo705}, // Inst #7444 = PseudoVSLIDEDOWN_VX_MF2 + {7, OperandInfo706}, // Inst #7445 = PseudoVSLIDEDOWN_VX_MF2_MASK + {6, OperandInfo705}, // Inst #7446 = PseudoVSLIDEDOWN_VX_MF4 + {7, OperandInfo706}, // Inst #7447 = PseudoVSLIDEDOWN_VX_MF4_MASK + {6, OperandInfo705}, // Inst #7448 = PseudoVSLIDEDOWN_VX_MF8 + {7, OperandInfo706}, // Inst #7449 = PseudoVSLIDEDOWN_VX_MF8_MASK + {6, OperandInfo713}, // Inst #7450 = PseudoVSLIDEUP_VI_M1 + {7, OperandInfo714}, // Inst #7451 = PseudoVSLIDEUP_VI_M1_MASK + {6, OperandInfo715}, // Inst #7452 = PseudoVSLIDEUP_VI_M2 + {7, OperandInfo716}, // Inst #7453 = PseudoVSLIDEUP_VI_M2_MASK + {6, OperandInfo717}, // Inst #7454 = PseudoVSLIDEUP_VI_M4 + {7, OperandInfo718}, // Inst #7455 = PseudoVSLIDEUP_VI_M4_MASK + {6, OperandInfo719}, // Inst #7456 = PseudoVSLIDEUP_VI_M8 + {7, OperandInfo720}, // Inst #7457 = PseudoVSLIDEUP_VI_M8_MASK + {6, OperandInfo713}, // Inst #7458 = PseudoVSLIDEUP_VI_MF2 + {7, OperandInfo714}, // Inst #7459 = PseudoVSLIDEUP_VI_MF2_MASK + {6, OperandInfo713}, // Inst #7460 = PseudoVSLIDEUP_VI_MF4 + {7, OperandInfo714}, // Inst #7461 = PseudoVSLIDEUP_VI_MF4_MASK + {6, OperandInfo713}, // Inst #7462 = PseudoVSLIDEUP_VI_MF8 + {7, OperandInfo714}, // Inst #7463 = PseudoVSLIDEUP_VI_MF8_MASK + {6, OperandInfo721}, // Inst #7464 = PseudoVSLIDEUP_VX_M1 + {7, OperandInfo722}, // Inst #7465 = PseudoVSLIDEUP_VX_M1_MASK + {6, OperandInfo723}, // Inst #7466 = PseudoVSLIDEUP_VX_M2 + {7, OperandInfo724}, // Inst #7467 = PseudoVSLIDEUP_VX_M2_MASK + {6, OperandInfo725}, // Inst #7468 = PseudoVSLIDEUP_VX_M4 + {7, OperandInfo726}, // Inst #7469 = PseudoVSLIDEUP_VX_M4_MASK + {6, OperandInfo727}, // Inst #7470 = PseudoVSLIDEUP_VX_M8 + {7, OperandInfo728}, // Inst #7471 = PseudoVSLIDEUP_VX_M8_MASK + {6, OperandInfo721}, // Inst #7472 = PseudoVSLIDEUP_VX_MF2 + {7, OperandInfo722}, // Inst #7473 = PseudoVSLIDEUP_VX_MF2_MASK + {6, OperandInfo721}, // Inst #7474 = PseudoVSLIDEUP_VX_MF4 + {7, OperandInfo722}, // Inst #7475 = PseudoVSLIDEUP_VX_MF4_MASK + {6, OperandInfo721}, // Inst #7476 = PseudoVSLIDEUP_VX_MF8 + {7, OperandInfo722}, // Inst #7477 = PseudoVSLIDEUP_VX_MF8_MASK + {5, OperandInfo90}, // Inst #7478 = PseudoVSLL_VI_M1 + {8, OperandInfo91}, // Inst #7479 = PseudoVSLL_VI_M1_MASK + {5, OperandInfo92}, // Inst #7480 = PseudoVSLL_VI_M2 + {8, OperandInfo93}, // Inst #7481 = PseudoVSLL_VI_M2_MASK + {5, OperandInfo94}, // Inst #7482 = PseudoVSLL_VI_M4 + {8, OperandInfo95}, // Inst #7483 = PseudoVSLL_VI_M4_MASK + {5, OperandInfo96}, // Inst #7484 = PseudoVSLL_VI_M8 + {8, OperandInfo97}, // Inst #7485 = PseudoVSLL_VI_M8_MASK + {5, OperandInfo90}, // Inst #7486 = PseudoVSLL_VI_MF2 + {8, OperandInfo91}, // Inst #7487 = PseudoVSLL_VI_MF2_MASK + {5, OperandInfo90}, // Inst #7488 = PseudoVSLL_VI_MF4 + {8, OperandInfo91}, // Inst #7489 = PseudoVSLL_VI_MF4_MASK + {5, OperandInfo90}, // Inst #7490 = PseudoVSLL_VI_MF8 + {8, OperandInfo91}, // Inst #7491 = PseudoVSLL_VI_MF8_MASK + {5, OperandInfo62}, // Inst #7492 = PseudoVSLL_VV_M1 + {8, OperandInfo63}, // Inst #7493 = PseudoVSLL_VV_M1_MASK + {5, OperandInfo64}, // Inst #7494 = PseudoVSLL_VV_M2 + {8, OperandInfo65}, // Inst #7495 = PseudoVSLL_VV_M2_MASK + {5, OperandInfo66}, // Inst #7496 = PseudoVSLL_VV_M4 + {8, OperandInfo67}, // Inst #7497 = PseudoVSLL_VV_M4_MASK + {5, OperandInfo68}, // Inst #7498 = PseudoVSLL_VV_M8 + {8, OperandInfo69}, // Inst #7499 = PseudoVSLL_VV_M8_MASK + {5, OperandInfo62}, // Inst #7500 = PseudoVSLL_VV_MF2 + {8, OperandInfo63}, // Inst #7501 = PseudoVSLL_VV_MF2_MASK + {5, OperandInfo62}, // Inst #7502 = PseudoVSLL_VV_MF4 + {8, OperandInfo63}, // Inst #7503 = PseudoVSLL_VV_MF4_MASK + {5, OperandInfo62}, // Inst #7504 = PseudoVSLL_VV_MF8 + {8, OperandInfo63}, // Inst #7505 = PseudoVSLL_VV_MF8_MASK + {5, OperandInfo70}, // Inst #7506 = PseudoVSLL_VX_M1 + {8, OperandInfo71}, // Inst #7507 = PseudoVSLL_VX_M1_MASK + {5, OperandInfo72}, // Inst #7508 = PseudoVSLL_VX_M2 + {8, OperandInfo73}, // Inst #7509 = PseudoVSLL_VX_M2_MASK + {5, OperandInfo74}, // Inst #7510 = PseudoVSLL_VX_M4 + {8, OperandInfo75}, // Inst #7511 = PseudoVSLL_VX_M4_MASK + {5, OperandInfo76}, // Inst #7512 = PseudoVSLL_VX_M8 + {8, OperandInfo77}, // Inst #7513 = PseudoVSLL_VX_M8_MASK + {5, OperandInfo70}, // Inst #7514 = PseudoVSLL_VX_MF2 + {8, OperandInfo71}, // Inst #7515 = PseudoVSLL_VX_MF2_MASK + {5, OperandInfo70}, // Inst #7516 = PseudoVSLL_VX_MF4 + {8, OperandInfo71}, // Inst #7517 = PseudoVSLL_VX_MF4_MASK + {5, OperandInfo70}, // Inst #7518 = PseudoVSLL_VX_MF8 + {8, OperandInfo71}, // Inst #7519 = PseudoVSLL_VX_MF8_MASK + {5, OperandInfo62}, // Inst #7520 = PseudoVSMUL_VV_M1 + {8, OperandInfo63}, // Inst #7521 = PseudoVSMUL_VV_M1_MASK + {5, OperandInfo64}, // Inst #7522 = PseudoVSMUL_VV_M2 + {8, OperandInfo65}, // Inst #7523 = PseudoVSMUL_VV_M2_MASK + {5, OperandInfo66}, // Inst #7524 = PseudoVSMUL_VV_M4 + {8, OperandInfo67}, // Inst #7525 = PseudoVSMUL_VV_M4_MASK + {5, OperandInfo68}, // Inst #7526 = PseudoVSMUL_VV_M8 + {8, OperandInfo69}, // Inst #7527 = PseudoVSMUL_VV_M8_MASK + {5, OperandInfo62}, // Inst #7528 = PseudoVSMUL_VV_MF2 + {8, OperandInfo63}, // Inst #7529 = PseudoVSMUL_VV_MF2_MASK + {5, OperandInfo62}, // Inst #7530 = PseudoVSMUL_VV_MF4 + {8, OperandInfo63}, // Inst #7531 = PseudoVSMUL_VV_MF4_MASK + {5, OperandInfo62}, // Inst #7532 = PseudoVSMUL_VV_MF8 + {8, OperandInfo63}, // Inst #7533 = PseudoVSMUL_VV_MF8_MASK + {5, OperandInfo70}, // Inst #7534 = PseudoVSMUL_VX_M1 + {8, OperandInfo71}, // Inst #7535 = PseudoVSMUL_VX_M1_MASK + {5, OperandInfo72}, // Inst #7536 = PseudoVSMUL_VX_M2 + {8, OperandInfo73}, // Inst #7537 = PseudoVSMUL_VX_M2_MASK + {5, OperandInfo74}, // Inst #7538 = PseudoVSMUL_VX_M4 + {8, OperandInfo75}, // Inst #7539 = PseudoVSMUL_VX_M4_MASK + {5, OperandInfo76}, // Inst #7540 = PseudoVSMUL_VX_M8 + {8, OperandInfo77}, // Inst #7541 = PseudoVSMUL_VX_M8_MASK + {5, OperandInfo70}, // Inst #7542 = PseudoVSMUL_VX_MF2 + {8, OperandInfo71}, // Inst #7543 = PseudoVSMUL_VX_MF2_MASK + {5, OperandInfo70}, // Inst #7544 = PseudoVSMUL_VX_MF4 + {8, OperandInfo71}, // Inst #7545 = PseudoVSMUL_VX_MF4_MASK + {5, OperandInfo70}, // Inst #7546 = PseudoVSMUL_VX_MF8 + {8, OperandInfo71}, // Inst #7547 = PseudoVSMUL_VX_MF8_MASK + {4, OperandInfo359}, // Inst #7548 = PseudoVSM_V_B1 + {4, OperandInfo359}, // Inst #7549 = PseudoVSM_V_B16 + {4, OperandInfo359}, // Inst #7550 = PseudoVSM_V_B2 + {4, OperandInfo359}, // Inst #7551 = PseudoVSM_V_B32 + {4, OperandInfo359}, // Inst #7552 = PseudoVSM_V_B4 + {4, OperandInfo359}, // Inst #7553 = PseudoVSM_V_B64 + {4, OperandInfo359}, // Inst #7554 = PseudoVSM_V_B8 + {5, OperandInfo367}, // Inst #7555 = PseudoVSOXEI16_V_M1_M1 + {6, OperandInfo729}, // Inst #7556 = PseudoVSOXEI16_V_M1_M1_MASK + {5, OperandInfo730}, // Inst #7557 = PseudoVSOXEI16_V_M1_M2 + {6, OperandInfo731}, // Inst #7558 = PseudoVSOXEI16_V_M1_M2_MASK + {5, OperandInfo732}, // Inst #7559 = PseudoVSOXEI16_V_M1_M4 + {6, OperandInfo733}, // Inst #7560 = PseudoVSOXEI16_V_M1_M4_MASK + {5, OperandInfo367}, // Inst #7561 = PseudoVSOXEI16_V_M1_MF2 + {6, OperandInfo729}, // Inst #7562 = PseudoVSOXEI16_V_M1_MF2_MASK + {5, OperandInfo734}, // Inst #7563 = PseudoVSOXEI16_V_M2_M1 + {6, OperandInfo735}, // Inst #7564 = PseudoVSOXEI16_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #7565 = PseudoVSOXEI16_V_M2_M2 + {6, OperandInfo736}, // Inst #7566 = PseudoVSOXEI16_V_M2_M2_MASK + {5, OperandInfo737}, // Inst #7567 = PseudoVSOXEI16_V_M2_M4 + {6, OperandInfo738}, // Inst #7568 = PseudoVSOXEI16_V_M2_M4_MASK + {5, OperandInfo739}, // Inst #7569 = PseudoVSOXEI16_V_M2_M8 + {6, OperandInfo740}, // Inst #7570 = PseudoVSOXEI16_V_M2_M8_MASK + {5, OperandInfo741}, // Inst #7571 = PseudoVSOXEI16_V_M4_M2 + {6, OperandInfo742}, // Inst #7572 = PseudoVSOXEI16_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #7573 = PseudoVSOXEI16_V_M4_M4 + {6, OperandInfo743}, // Inst #7574 = PseudoVSOXEI16_V_M4_M4_MASK + {5, OperandInfo744}, // Inst #7575 = PseudoVSOXEI16_V_M4_M8 + {6, OperandInfo745}, // Inst #7576 = PseudoVSOXEI16_V_M4_M8_MASK + {5, OperandInfo746}, // Inst #7577 = PseudoVSOXEI16_V_M8_M4 + {6, OperandInfo747}, // Inst #7578 = PseudoVSOXEI16_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #7579 = PseudoVSOXEI16_V_M8_M8 + {6, OperandInfo748}, // Inst #7580 = PseudoVSOXEI16_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #7581 = PseudoVSOXEI16_V_MF2_M1 + {6, OperandInfo729}, // Inst #7582 = PseudoVSOXEI16_V_MF2_M1_MASK + {5, OperandInfo730}, // Inst #7583 = PseudoVSOXEI16_V_MF2_M2 + {6, OperandInfo731}, // Inst #7584 = PseudoVSOXEI16_V_MF2_M2_MASK + {5, OperandInfo367}, // Inst #7585 = PseudoVSOXEI16_V_MF2_MF2 + {6, OperandInfo729}, // Inst #7586 = PseudoVSOXEI16_V_MF2_MF2_MASK + {5, OperandInfo367}, // Inst #7587 = PseudoVSOXEI16_V_MF2_MF4 + {6, OperandInfo729}, // Inst #7588 = PseudoVSOXEI16_V_MF2_MF4_MASK + {5, OperandInfo367}, // Inst #7589 = PseudoVSOXEI16_V_MF4_M1 + {6, OperandInfo729}, // Inst #7590 = PseudoVSOXEI16_V_MF4_M1_MASK + {5, OperandInfo367}, // Inst #7591 = PseudoVSOXEI16_V_MF4_MF2 + {6, OperandInfo729}, // Inst #7592 = PseudoVSOXEI16_V_MF4_MF2_MASK + {5, OperandInfo367}, // Inst #7593 = PseudoVSOXEI16_V_MF4_MF4 + {6, OperandInfo729}, // Inst #7594 = PseudoVSOXEI16_V_MF4_MF4_MASK + {5, OperandInfo367}, // Inst #7595 = PseudoVSOXEI16_V_MF4_MF8 + {6, OperandInfo729}, // Inst #7596 = PseudoVSOXEI16_V_MF4_MF8_MASK + {5, OperandInfo367}, // Inst #7597 = PseudoVSOXEI32_V_M1_M1 + {6, OperandInfo729}, // Inst #7598 = PseudoVSOXEI32_V_M1_M1_MASK + {5, OperandInfo730}, // Inst #7599 = PseudoVSOXEI32_V_M1_M2 + {6, OperandInfo731}, // Inst #7600 = PseudoVSOXEI32_V_M1_M2_MASK + {5, OperandInfo367}, // Inst #7601 = PseudoVSOXEI32_V_M1_MF2 + {6, OperandInfo729}, // Inst #7602 = PseudoVSOXEI32_V_M1_MF2_MASK + {5, OperandInfo367}, // Inst #7603 = PseudoVSOXEI32_V_M1_MF4 + {6, OperandInfo729}, // Inst #7604 = PseudoVSOXEI32_V_M1_MF4_MASK + {5, OperandInfo734}, // Inst #7605 = PseudoVSOXEI32_V_M2_M1 + {6, OperandInfo735}, // Inst #7606 = PseudoVSOXEI32_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #7607 = PseudoVSOXEI32_V_M2_M2 + {6, OperandInfo736}, // Inst #7608 = PseudoVSOXEI32_V_M2_M2_MASK + {5, OperandInfo737}, // Inst #7609 = PseudoVSOXEI32_V_M2_M4 + {6, OperandInfo738}, // Inst #7610 = PseudoVSOXEI32_V_M2_M4_MASK + {5, OperandInfo734}, // Inst #7611 = PseudoVSOXEI32_V_M2_MF2 + {6, OperandInfo735}, // Inst #7612 = PseudoVSOXEI32_V_M2_MF2_MASK + {5, OperandInfo749}, // Inst #7613 = PseudoVSOXEI32_V_M4_M1 + {6, OperandInfo750}, // Inst #7614 = PseudoVSOXEI32_V_M4_M1_MASK + {5, OperandInfo741}, // Inst #7615 = PseudoVSOXEI32_V_M4_M2 + {6, OperandInfo742}, // Inst #7616 = PseudoVSOXEI32_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #7617 = PseudoVSOXEI32_V_M4_M4 + {6, OperandInfo743}, // Inst #7618 = PseudoVSOXEI32_V_M4_M4_MASK + {5, OperandInfo744}, // Inst #7619 = PseudoVSOXEI32_V_M4_M8 + {6, OperandInfo745}, // Inst #7620 = PseudoVSOXEI32_V_M4_M8_MASK + {5, OperandInfo751}, // Inst #7621 = PseudoVSOXEI32_V_M8_M2 + {6, OperandInfo752}, // Inst #7622 = PseudoVSOXEI32_V_M8_M2_MASK + {5, OperandInfo746}, // Inst #7623 = PseudoVSOXEI32_V_M8_M4 + {6, OperandInfo747}, // Inst #7624 = PseudoVSOXEI32_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #7625 = PseudoVSOXEI32_V_M8_M8 + {6, OperandInfo748}, // Inst #7626 = PseudoVSOXEI32_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #7627 = PseudoVSOXEI32_V_MF2_M1 + {6, OperandInfo729}, // Inst #7628 = PseudoVSOXEI32_V_MF2_M1_MASK + {5, OperandInfo367}, // Inst #7629 = PseudoVSOXEI32_V_MF2_MF2 + {6, OperandInfo729}, // Inst #7630 = PseudoVSOXEI32_V_MF2_MF2_MASK + {5, OperandInfo367}, // Inst #7631 = PseudoVSOXEI32_V_MF2_MF4 + {6, OperandInfo729}, // Inst #7632 = PseudoVSOXEI32_V_MF2_MF4_MASK + {5, OperandInfo367}, // Inst #7633 = PseudoVSOXEI32_V_MF2_MF8 + {6, OperandInfo729}, // Inst #7634 = PseudoVSOXEI32_V_MF2_MF8_MASK + {5, OperandInfo367}, // Inst #7635 = PseudoVSOXEI64_V_M1_M1 + {6, OperandInfo729}, // Inst #7636 = PseudoVSOXEI64_V_M1_M1_MASK + {5, OperandInfo367}, // Inst #7637 = PseudoVSOXEI64_V_M1_MF2 + {6, OperandInfo729}, // Inst #7638 = PseudoVSOXEI64_V_M1_MF2_MASK + {5, OperandInfo367}, // Inst #7639 = PseudoVSOXEI64_V_M1_MF4 + {6, OperandInfo729}, // Inst #7640 = PseudoVSOXEI64_V_M1_MF4_MASK + {5, OperandInfo367}, // Inst #7641 = PseudoVSOXEI64_V_M1_MF8 + {6, OperandInfo729}, // Inst #7642 = PseudoVSOXEI64_V_M1_MF8_MASK + {5, OperandInfo734}, // Inst #7643 = PseudoVSOXEI64_V_M2_M1 + {6, OperandInfo735}, // Inst #7644 = PseudoVSOXEI64_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #7645 = PseudoVSOXEI64_V_M2_M2 + {6, OperandInfo736}, // Inst #7646 = PseudoVSOXEI64_V_M2_M2_MASK + {5, OperandInfo734}, // Inst #7647 = PseudoVSOXEI64_V_M2_MF2 + {6, OperandInfo735}, // Inst #7648 = PseudoVSOXEI64_V_M2_MF2_MASK + {5, OperandInfo734}, // Inst #7649 = PseudoVSOXEI64_V_M2_MF4 + {6, OperandInfo735}, // Inst #7650 = PseudoVSOXEI64_V_M2_MF4_MASK + {5, OperandInfo749}, // Inst #7651 = PseudoVSOXEI64_V_M4_M1 + {6, OperandInfo750}, // Inst #7652 = PseudoVSOXEI64_V_M4_M1_MASK + {5, OperandInfo741}, // Inst #7653 = PseudoVSOXEI64_V_M4_M2 + {6, OperandInfo742}, // Inst #7654 = PseudoVSOXEI64_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #7655 = PseudoVSOXEI64_V_M4_M4 + {6, OperandInfo743}, // Inst #7656 = PseudoVSOXEI64_V_M4_M4_MASK + {5, OperandInfo749}, // Inst #7657 = PseudoVSOXEI64_V_M4_MF2 + {6, OperandInfo750}, // Inst #7658 = PseudoVSOXEI64_V_M4_MF2_MASK + {5, OperandInfo753}, // Inst #7659 = PseudoVSOXEI64_V_M8_M1 + {6, OperandInfo754}, // Inst #7660 = PseudoVSOXEI64_V_M8_M1_MASK + {5, OperandInfo751}, // Inst #7661 = PseudoVSOXEI64_V_M8_M2 + {6, OperandInfo752}, // Inst #7662 = PseudoVSOXEI64_V_M8_M2_MASK + {5, OperandInfo746}, // Inst #7663 = PseudoVSOXEI64_V_M8_M4 + {6, OperandInfo747}, // Inst #7664 = PseudoVSOXEI64_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #7665 = PseudoVSOXEI64_V_M8_M8 + {6, OperandInfo748}, // Inst #7666 = PseudoVSOXEI64_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #7667 = PseudoVSOXEI8_V_M1_M1 + {6, OperandInfo729}, // Inst #7668 = PseudoVSOXEI8_V_M1_M1_MASK + {5, OperandInfo730}, // Inst #7669 = PseudoVSOXEI8_V_M1_M2 + {6, OperandInfo731}, // Inst #7670 = PseudoVSOXEI8_V_M1_M2_MASK + {5, OperandInfo732}, // Inst #7671 = PseudoVSOXEI8_V_M1_M4 + {6, OperandInfo733}, // Inst #7672 = PseudoVSOXEI8_V_M1_M4_MASK + {5, OperandInfo755}, // Inst #7673 = PseudoVSOXEI8_V_M1_M8 + {6, OperandInfo756}, // Inst #7674 = PseudoVSOXEI8_V_M1_M8_MASK + {5, OperandInfo377}, // Inst #7675 = PseudoVSOXEI8_V_M2_M2 + {6, OperandInfo736}, // Inst #7676 = PseudoVSOXEI8_V_M2_M2_MASK + {5, OperandInfo737}, // Inst #7677 = PseudoVSOXEI8_V_M2_M4 + {6, OperandInfo738}, // Inst #7678 = PseudoVSOXEI8_V_M2_M4_MASK + {5, OperandInfo739}, // Inst #7679 = PseudoVSOXEI8_V_M2_M8 + {6, OperandInfo740}, // Inst #7680 = PseudoVSOXEI8_V_M2_M8_MASK + {5, OperandInfo385}, // Inst #7681 = PseudoVSOXEI8_V_M4_M4 + {6, OperandInfo743}, // Inst #7682 = PseudoVSOXEI8_V_M4_M4_MASK + {5, OperandInfo744}, // Inst #7683 = PseudoVSOXEI8_V_M4_M8 + {6, OperandInfo745}, // Inst #7684 = PseudoVSOXEI8_V_M4_M8_MASK + {5, OperandInfo391}, // Inst #7685 = PseudoVSOXEI8_V_M8_M8 + {6, OperandInfo748}, // Inst #7686 = PseudoVSOXEI8_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #7687 = PseudoVSOXEI8_V_MF2_M1 + {6, OperandInfo729}, // Inst #7688 = PseudoVSOXEI8_V_MF2_M1_MASK + {5, OperandInfo730}, // Inst #7689 = PseudoVSOXEI8_V_MF2_M2 + {6, OperandInfo731}, // Inst #7690 = PseudoVSOXEI8_V_MF2_M2_MASK + {5, OperandInfo732}, // Inst #7691 = PseudoVSOXEI8_V_MF2_M4 + {6, OperandInfo733}, // Inst #7692 = PseudoVSOXEI8_V_MF2_M4_MASK + {5, OperandInfo367}, // Inst #7693 = PseudoVSOXEI8_V_MF2_MF2 + {6, OperandInfo729}, // Inst #7694 = PseudoVSOXEI8_V_MF2_MF2_MASK + {5, OperandInfo367}, // Inst #7695 = PseudoVSOXEI8_V_MF4_M1 + {6, OperandInfo729}, // Inst #7696 = PseudoVSOXEI8_V_MF4_M1_MASK + {5, OperandInfo730}, // Inst #7697 = PseudoVSOXEI8_V_MF4_M2 + {6, OperandInfo731}, // Inst #7698 = PseudoVSOXEI8_V_MF4_M2_MASK + {5, OperandInfo367}, // Inst #7699 = PseudoVSOXEI8_V_MF4_MF2 + {6, OperandInfo729}, // Inst #7700 = PseudoVSOXEI8_V_MF4_MF2_MASK + {5, OperandInfo367}, // Inst #7701 = PseudoVSOXEI8_V_MF4_MF4 + {6, OperandInfo729}, // Inst #7702 = PseudoVSOXEI8_V_MF4_MF4_MASK + {5, OperandInfo367}, // Inst #7703 = PseudoVSOXEI8_V_MF8_M1 + {6, OperandInfo729}, // Inst #7704 = PseudoVSOXEI8_V_MF8_M1_MASK + {5, OperandInfo367}, // Inst #7705 = PseudoVSOXEI8_V_MF8_MF2 + {6, OperandInfo729}, // Inst #7706 = PseudoVSOXEI8_V_MF8_MF2_MASK + {5, OperandInfo367}, // Inst #7707 = PseudoVSOXEI8_V_MF8_MF4 + {6, OperandInfo729}, // Inst #7708 = PseudoVSOXEI8_V_MF8_MF4_MASK + {5, OperandInfo367}, // Inst #7709 = PseudoVSOXEI8_V_MF8_MF8 + {6, OperandInfo729}, // Inst #7710 = PseudoVSOXEI8_V_MF8_MF8_MASK + {5, OperandInfo757}, // Inst #7711 = PseudoVSOXSEG2EI16_V_M1_M1 + {6, OperandInfo758}, // Inst #7712 = PseudoVSOXSEG2EI16_V_M1_M1_MASK + {5, OperandInfo759}, // Inst #7713 = PseudoVSOXSEG2EI16_V_M1_M2 + {6, OperandInfo760}, // Inst #7714 = PseudoVSOXSEG2EI16_V_M1_M2_MASK + {5, OperandInfo761}, // Inst #7715 = PseudoVSOXSEG2EI16_V_M1_M4 + {6, OperandInfo762}, // Inst #7716 = PseudoVSOXSEG2EI16_V_M1_M4_MASK + {5, OperandInfo757}, // Inst #7717 = PseudoVSOXSEG2EI16_V_M1_MF2 + {6, OperandInfo758}, // Inst #7718 = PseudoVSOXSEG2EI16_V_M1_MF2_MASK + {5, OperandInfo763}, // Inst #7719 = PseudoVSOXSEG2EI16_V_M2_M1 + {6, OperandInfo764}, // Inst #7720 = PseudoVSOXSEG2EI16_V_M2_M1_MASK + {5, OperandInfo765}, // Inst #7721 = PseudoVSOXSEG2EI16_V_M2_M2 + {6, OperandInfo766}, // Inst #7722 = PseudoVSOXSEG2EI16_V_M2_M2_MASK + {5, OperandInfo767}, // Inst #7723 = PseudoVSOXSEG2EI16_V_M2_M4 + {6, OperandInfo768}, // Inst #7724 = PseudoVSOXSEG2EI16_V_M2_M4_MASK + {5, OperandInfo769}, // Inst #7725 = PseudoVSOXSEG2EI16_V_M4_M2 + {6, OperandInfo770}, // Inst #7726 = PseudoVSOXSEG2EI16_V_M4_M2_MASK + {5, OperandInfo771}, // Inst #7727 = PseudoVSOXSEG2EI16_V_M4_M4 + {6, OperandInfo772}, // Inst #7728 = PseudoVSOXSEG2EI16_V_M4_M4_MASK + {5, OperandInfo773}, // Inst #7729 = PseudoVSOXSEG2EI16_V_M8_M4 + {6, OperandInfo774}, // Inst #7730 = PseudoVSOXSEG2EI16_V_M8_M4_MASK + {5, OperandInfo757}, // Inst #7731 = PseudoVSOXSEG2EI16_V_MF2_M1 + {6, OperandInfo758}, // Inst #7732 = PseudoVSOXSEG2EI16_V_MF2_M1_MASK + {5, OperandInfo759}, // Inst #7733 = PseudoVSOXSEG2EI16_V_MF2_M2 + {6, OperandInfo760}, // Inst #7734 = PseudoVSOXSEG2EI16_V_MF2_M2_MASK + {5, OperandInfo757}, // Inst #7735 = PseudoVSOXSEG2EI16_V_MF2_MF2 + {6, OperandInfo758}, // Inst #7736 = PseudoVSOXSEG2EI16_V_MF2_MF2_MASK + {5, OperandInfo757}, // Inst #7737 = PseudoVSOXSEG2EI16_V_MF2_MF4 + {6, OperandInfo758}, // Inst #7738 = PseudoVSOXSEG2EI16_V_MF2_MF4_MASK + {5, OperandInfo757}, // Inst #7739 = PseudoVSOXSEG2EI16_V_MF4_M1 + {6, OperandInfo758}, // Inst #7740 = PseudoVSOXSEG2EI16_V_MF4_M1_MASK + {5, OperandInfo757}, // Inst #7741 = PseudoVSOXSEG2EI16_V_MF4_MF2 + {6, OperandInfo758}, // Inst #7742 = PseudoVSOXSEG2EI16_V_MF4_MF2_MASK + {5, OperandInfo757}, // Inst #7743 = PseudoVSOXSEG2EI16_V_MF4_MF4 + {6, OperandInfo758}, // Inst #7744 = PseudoVSOXSEG2EI16_V_MF4_MF4_MASK + {5, OperandInfo757}, // Inst #7745 = PseudoVSOXSEG2EI16_V_MF4_MF8 + {6, OperandInfo758}, // Inst #7746 = PseudoVSOXSEG2EI16_V_MF4_MF8_MASK + {5, OperandInfo757}, // Inst #7747 = PseudoVSOXSEG2EI32_V_M1_M1 + {6, OperandInfo758}, // Inst #7748 = PseudoVSOXSEG2EI32_V_M1_M1_MASK + {5, OperandInfo759}, // Inst #7749 = PseudoVSOXSEG2EI32_V_M1_M2 + {6, OperandInfo760}, // Inst #7750 = PseudoVSOXSEG2EI32_V_M1_M2_MASK + {5, OperandInfo757}, // Inst #7751 = PseudoVSOXSEG2EI32_V_M1_MF2 + {6, OperandInfo758}, // Inst #7752 = PseudoVSOXSEG2EI32_V_M1_MF2_MASK + {5, OperandInfo757}, // Inst #7753 = PseudoVSOXSEG2EI32_V_M1_MF4 + {6, OperandInfo758}, // Inst #7754 = PseudoVSOXSEG2EI32_V_M1_MF4_MASK + {5, OperandInfo763}, // Inst #7755 = PseudoVSOXSEG2EI32_V_M2_M1 + {6, OperandInfo764}, // Inst #7756 = PseudoVSOXSEG2EI32_V_M2_M1_MASK + {5, OperandInfo765}, // Inst #7757 = PseudoVSOXSEG2EI32_V_M2_M2 + {6, OperandInfo766}, // Inst #7758 = PseudoVSOXSEG2EI32_V_M2_M2_MASK + {5, OperandInfo767}, // Inst #7759 = PseudoVSOXSEG2EI32_V_M2_M4 + {6, OperandInfo768}, // Inst #7760 = PseudoVSOXSEG2EI32_V_M2_M4_MASK + {5, OperandInfo763}, // Inst #7761 = PseudoVSOXSEG2EI32_V_M2_MF2 + {6, OperandInfo764}, // Inst #7762 = PseudoVSOXSEG2EI32_V_M2_MF2_MASK + {5, OperandInfo775}, // Inst #7763 = PseudoVSOXSEG2EI32_V_M4_M1 + {6, OperandInfo776}, // Inst #7764 = PseudoVSOXSEG2EI32_V_M4_M1_MASK + {5, OperandInfo769}, // Inst #7765 = PseudoVSOXSEG2EI32_V_M4_M2 + {6, OperandInfo770}, // Inst #7766 = PseudoVSOXSEG2EI32_V_M4_M2_MASK + {5, OperandInfo771}, // Inst #7767 = PseudoVSOXSEG2EI32_V_M4_M4 + {6, OperandInfo772}, // Inst #7768 = PseudoVSOXSEG2EI32_V_M4_M4_MASK + {5, OperandInfo777}, // Inst #7769 = PseudoVSOXSEG2EI32_V_M8_M2 + {6, OperandInfo778}, // Inst #7770 = PseudoVSOXSEG2EI32_V_M8_M2_MASK + {5, OperandInfo773}, // Inst #7771 = PseudoVSOXSEG2EI32_V_M8_M4 + {6, OperandInfo774}, // Inst #7772 = PseudoVSOXSEG2EI32_V_M8_M4_MASK + {5, OperandInfo757}, // Inst #7773 = PseudoVSOXSEG2EI32_V_MF2_M1 + {6, OperandInfo758}, // Inst #7774 = PseudoVSOXSEG2EI32_V_MF2_M1_MASK + {5, OperandInfo757}, // Inst #7775 = PseudoVSOXSEG2EI32_V_MF2_MF2 + {6, OperandInfo758}, // Inst #7776 = PseudoVSOXSEG2EI32_V_MF2_MF2_MASK + {5, OperandInfo757}, // Inst #7777 = PseudoVSOXSEG2EI32_V_MF2_MF4 + {6, OperandInfo758}, // Inst #7778 = PseudoVSOXSEG2EI32_V_MF2_MF4_MASK + {5, OperandInfo757}, // Inst #7779 = PseudoVSOXSEG2EI32_V_MF2_MF8 + {6, OperandInfo758}, // Inst #7780 = PseudoVSOXSEG2EI32_V_MF2_MF8_MASK + {5, OperandInfo757}, // Inst #7781 = PseudoVSOXSEG2EI64_V_M1_M1 + {6, OperandInfo758}, // Inst #7782 = PseudoVSOXSEG2EI64_V_M1_M1_MASK + {5, OperandInfo757}, // Inst #7783 = PseudoVSOXSEG2EI64_V_M1_MF2 + {6, OperandInfo758}, // Inst #7784 = PseudoVSOXSEG2EI64_V_M1_MF2_MASK + {5, OperandInfo757}, // Inst #7785 = PseudoVSOXSEG2EI64_V_M1_MF4 + {6, OperandInfo758}, // Inst #7786 = PseudoVSOXSEG2EI64_V_M1_MF4_MASK + {5, OperandInfo757}, // Inst #7787 = PseudoVSOXSEG2EI64_V_M1_MF8 + {6, OperandInfo758}, // Inst #7788 = PseudoVSOXSEG2EI64_V_M1_MF8_MASK + {5, OperandInfo763}, // Inst #7789 = PseudoVSOXSEG2EI64_V_M2_M1 + {6, OperandInfo764}, // Inst #7790 = PseudoVSOXSEG2EI64_V_M2_M1_MASK + {5, OperandInfo765}, // Inst #7791 = PseudoVSOXSEG2EI64_V_M2_M2 + {6, OperandInfo766}, // Inst #7792 = PseudoVSOXSEG2EI64_V_M2_M2_MASK + {5, OperandInfo763}, // Inst #7793 = PseudoVSOXSEG2EI64_V_M2_MF2 + {6, OperandInfo764}, // Inst #7794 = PseudoVSOXSEG2EI64_V_M2_MF2_MASK + {5, OperandInfo763}, // Inst #7795 = PseudoVSOXSEG2EI64_V_M2_MF4 + {6, OperandInfo764}, // Inst #7796 = PseudoVSOXSEG2EI64_V_M2_MF4_MASK + {5, OperandInfo775}, // Inst #7797 = PseudoVSOXSEG2EI64_V_M4_M1 + {6, OperandInfo776}, // Inst #7798 = PseudoVSOXSEG2EI64_V_M4_M1_MASK + {5, OperandInfo769}, // Inst #7799 = PseudoVSOXSEG2EI64_V_M4_M2 + {6, OperandInfo770}, // Inst #7800 = PseudoVSOXSEG2EI64_V_M4_M2_MASK + {5, OperandInfo771}, // Inst #7801 = PseudoVSOXSEG2EI64_V_M4_M4 + {6, OperandInfo772}, // Inst #7802 = PseudoVSOXSEG2EI64_V_M4_M4_MASK + {5, OperandInfo775}, // Inst #7803 = PseudoVSOXSEG2EI64_V_M4_MF2 + {6, OperandInfo776}, // Inst #7804 = PseudoVSOXSEG2EI64_V_M4_MF2_MASK + {5, OperandInfo779}, // Inst #7805 = PseudoVSOXSEG2EI64_V_M8_M1 + {6, OperandInfo780}, // Inst #7806 = PseudoVSOXSEG2EI64_V_M8_M1_MASK + {5, OperandInfo777}, // Inst #7807 = PseudoVSOXSEG2EI64_V_M8_M2 + {6, OperandInfo778}, // Inst #7808 = PseudoVSOXSEG2EI64_V_M8_M2_MASK + {5, OperandInfo773}, // Inst #7809 = PseudoVSOXSEG2EI64_V_M8_M4 + {6, OperandInfo774}, // Inst #7810 = PseudoVSOXSEG2EI64_V_M8_M4_MASK + {5, OperandInfo757}, // Inst #7811 = PseudoVSOXSEG2EI8_V_M1_M1 + {6, OperandInfo758}, // Inst #7812 = PseudoVSOXSEG2EI8_V_M1_M1_MASK + {5, OperandInfo759}, // Inst #7813 = PseudoVSOXSEG2EI8_V_M1_M2 + {6, OperandInfo760}, // Inst #7814 = PseudoVSOXSEG2EI8_V_M1_M2_MASK + {5, OperandInfo761}, // Inst #7815 = PseudoVSOXSEG2EI8_V_M1_M4 + {6, OperandInfo762}, // Inst #7816 = PseudoVSOXSEG2EI8_V_M1_M4_MASK + {5, OperandInfo765}, // Inst #7817 = PseudoVSOXSEG2EI8_V_M2_M2 + {6, OperandInfo766}, // Inst #7818 = PseudoVSOXSEG2EI8_V_M2_M2_MASK + {5, OperandInfo767}, // Inst #7819 = PseudoVSOXSEG2EI8_V_M2_M4 + {6, OperandInfo768}, // Inst #7820 = PseudoVSOXSEG2EI8_V_M2_M4_MASK + {5, OperandInfo771}, // Inst #7821 = PseudoVSOXSEG2EI8_V_M4_M4 + {6, OperandInfo772}, // Inst #7822 = PseudoVSOXSEG2EI8_V_M4_M4_MASK + {5, OperandInfo757}, // Inst #7823 = PseudoVSOXSEG2EI8_V_MF2_M1 + {6, OperandInfo758}, // Inst #7824 = PseudoVSOXSEG2EI8_V_MF2_M1_MASK + {5, OperandInfo759}, // Inst #7825 = PseudoVSOXSEG2EI8_V_MF2_M2 + {6, OperandInfo760}, // Inst #7826 = PseudoVSOXSEG2EI8_V_MF2_M2_MASK + {5, OperandInfo761}, // Inst #7827 = PseudoVSOXSEG2EI8_V_MF2_M4 + {6, OperandInfo762}, // Inst #7828 = PseudoVSOXSEG2EI8_V_MF2_M4_MASK + {5, OperandInfo757}, // Inst #7829 = PseudoVSOXSEG2EI8_V_MF2_MF2 + {6, OperandInfo758}, // Inst #7830 = PseudoVSOXSEG2EI8_V_MF2_MF2_MASK + {5, OperandInfo757}, // Inst #7831 = PseudoVSOXSEG2EI8_V_MF4_M1 + {6, OperandInfo758}, // Inst #7832 = PseudoVSOXSEG2EI8_V_MF4_M1_MASK + {5, OperandInfo759}, // Inst #7833 = PseudoVSOXSEG2EI8_V_MF4_M2 + {6, OperandInfo760}, // Inst #7834 = PseudoVSOXSEG2EI8_V_MF4_M2_MASK + {5, OperandInfo757}, // Inst #7835 = PseudoVSOXSEG2EI8_V_MF4_MF2 + {6, OperandInfo758}, // Inst #7836 = PseudoVSOXSEG2EI8_V_MF4_MF2_MASK + {5, OperandInfo757}, // Inst #7837 = PseudoVSOXSEG2EI8_V_MF4_MF4 + {6, OperandInfo758}, // Inst #7838 = PseudoVSOXSEG2EI8_V_MF4_MF4_MASK + {5, OperandInfo757}, // Inst #7839 = PseudoVSOXSEG2EI8_V_MF8_M1 + {6, OperandInfo758}, // Inst #7840 = PseudoVSOXSEG2EI8_V_MF8_M1_MASK + {5, OperandInfo757}, // Inst #7841 = PseudoVSOXSEG2EI8_V_MF8_MF2 + {6, OperandInfo758}, // Inst #7842 = PseudoVSOXSEG2EI8_V_MF8_MF2_MASK + {5, OperandInfo757}, // Inst #7843 = PseudoVSOXSEG2EI8_V_MF8_MF4 + {6, OperandInfo758}, // Inst #7844 = PseudoVSOXSEG2EI8_V_MF8_MF4_MASK + {5, OperandInfo757}, // Inst #7845 = PseudoVSOXSEG2EI8_V_MF8_MF8 + {6, OperandInfo758}, // Inst #7846 = PseudoVSOXSEG2EI8_V_MF8_MF8_MASK + {5, OperandInfo781}, // Inst #7847 = PseudoVSOXSEG3EI16_V_M1_M1 + {6, OperandInfo782}, // Inst #7848 = PseudoVSOXSEG3EI16_V_M1_M1_MASK + {5, OperandInfo783}, // Inst #7849 = PseudoVSOXSEG3EI16_V_M1_M2 + {6, OperandInfo784}, // Inst #7850 = PseudoVSOXSEG3EI16_V_M1_M2_MASK + {5, OperandInfo781}, // Inst #7851 = PseudoVSOXSEG3EI16_V_M1_MF2 + {6, OperandInfo782}, // Inst #7852 = PseudoVSOXSEG3EI16_V_M1_MF2_MASK + {5, OperandInfo785}, // Inst #7853 = PseudoVSOXSEG3EI16_V_M2_M1 + {6, OperandInfo786}, // Inst #7854 = PseudoVSOXSEG3EI16_V_M2_M1_MASK + {5, OperandInfo787}, // Inst #7855 = PseudoVSOXSEG3EI16_V_M2_M2 + {6, OperandInfo788}, // Inst #7856 = PseudoVSOXSEG3EI16_V_M2_M2_MASK + {5, OperandInfo789}, // Inst #7857 = PseudoVSOXSEG3EI16_V_M4_M2 + {6, OperandInfo790}, // Inst #7858 = PseudoVSOXSEG3EI16_V_M4_M2_MASK + {5, OperandInfo781}, // Inst #7859 = PseudoVSOXSEG3EI16_V_MF2_M1 + {6, OperandInfo782}, // Inst #7860 = PseudoVSOXSEG3EI16_V_MF2_M1_MASK + {5, OperandInfo783}, // Inst #7861 = PseudoVSOXSEG3EI16_V_MF2_M2 + {6, OperandInfo784}, // Inst #7862 = PseudoVSOXSEG3EI16_V_MF2_M2_MASK + {5, OperandInfo781}, // Inst #7863 = PseudoVSOXSEG3EI16_V_MF2_MF2 + {6, OperandInfo782}, // Inst #7864 = PseudoVSOXSEG3EI16_V_MF2_MF2_MASK + {5, OperandInfo781}, // Inst #7865 = PseudoVSOXSEG3EI16_V_MF2_MF4 + {6, OperandInfo782}, // Inst #7866 = PseudoVSOXSEG3EI16_V_MF2_MF4_MASK + {5, OperandInfo781}, // Inst #7867 = PseudoVSOXSEG3EI16_V_MF4_M1 + {6, OperandInfo782}, // Inst #7868 = PseudoVSOXSEG3EI16_V_MF4_M1_MASK + {5, OperandInfo781}, // Inst #7869 = PseudoVSOXSEG3EI16_V_MF4_MF2 + {6, OperandInfo782}, // Inst #7870 = PseudoVSOXSEG3EI16_V_MF4_MF2_MASK + {5, OperandInfo781}, // Inst #7871 = PseudoVSOXSEG3EI16_V_MF4_MF4 + {6, OperandInfo782}, // Inst #7872 = PseudoVSOXSEG3EI16_V_MF4_MF4_MASK + {5, OperandInfo781}, // Inst #7873 = PseudoVSOXSEG3EI16_V_MF4_MF8 + {6, OperandInfo782}, // Inst #7874 = PseudoVSOXSEG3EI16_V_MF4_MF8_MASK + {5, OperandInfo781}, // Inst #7875 = PseudoVSOXSEG3EI32_V_M1_M1 + {6, OperandInfo782}, // Inst #7876 = PseudoVSOXSEG3EI32_V_M1_M1_MASK + {5, OperandInfo783}, // Inst #7877 = PseudoVSOXSEG3EI32_V_M1_M2 + {6, OperandInfo784}, // Inst #7878 = PseudoVSOXSEG3EI32_V_M1_M2_MASK + {5, OperandInfo781}, // Inst #7879 = PseudoVSOXSEG3EI32_V_M1_MF2 + {6, OperandInfo782}, // Inst #7880 = PseudoVSOXSEG3EI32_V_M1_MF2_MASK + {5, OperandInfo781}, // Inst #7881 = PseudoVSOXSEG3EI32_V_M1_MF4 + {6, OperandInfo782}, // Inst #7882 = PseudoVSOXSEG3EI32_V_M1_MF4_MASK + {5, OperandInfo785}, // Inst #7883 = PseudoVSOXSEG3EI32_V_M2_M1 + {6, OperandInfo786}, // Inst #7884 = PseudoVSOXSEG3EI32_V_M2_M1_MASK + {5, OperandInfo787}, // Inst #7885 = PseudoVSOXSEG3EI32_V_M2_M2 + {6, OperandInfo788}, // Inst #7886 = PseudoVSOXSEG3EI32_V_M2_M2_MASK + {5, OperandInfo785}, // Inst #7887 = PseudoVSOXSEG3EI32_V_M2_MF2 + {6, OperandInfo786}, // Inst #7888 = PseudoVSOXSEG3EI32_V_M2_MF2_MASK + {5, OperandInfo791}, // Inst #7889 = PseudoVSOXSEG3EI32_V_M4_M1 + {6, OperandInfo792}, // Inst #7890 = PseudoVSOXSEG3EI32_V_M4_M1_MASK + {5, OperandInfo789}, // Inst #7891 = PseudoVSOXSEG3EI32_V_M4_M2 + {6, OperandInfo790}, // Inst #7892 = PseudoVSOXSEG3EI32_V_M4_M2_MASK + {5, OperandInfo793}, // Inst #7893 = PseudoVSOXSEG3EI32_V_M8_M2 + {6, OperandInfo794}, // Inst #7894 = PseudoVSOXSEG3EI32_V_M8_M2_MASK + {5, OperandInfo781}, // Inst #7895 = PseudoVSOXSEG3EI32_V_MF2_M1 + {6, OperandInfo782}, // Inst #7896 = PseudoVSOXSEG3EI32_V_MF2_M1_MASK + {5, OperandInfo781}, // Inst #7897 = PseudoVSOXSEG3EI32_V_MF2_MF2 + {6, OperandInfo782}, // Inst #7898 = PseudoVSOXSEG3EI32_V_MF2_MF2_MASK + {5, OperandInfo781}, // Inst #7899 = PseudoVSOXSEG3EI32_V_MF2_MF4 + {6, OperandInfo782}, // Inst #7900 = PseudoVSOXSEG3EI32_V_MF2_MF4_MASK + {5, OperandInfo781}, // Inst #7901 = PseudoVSOXSEG3EI32_V_MF2_MF8 + {6, OperandInfo782}, // Inst #7902 = PseudoVSOXSEG3EI32_V_MF2_MF8_MASK + {5, OperandInfo781}, // Inst #7903 = PseudoVSOXSEG3EI64_V_M1_M1 + {6, OperandInfo782}, // Inst #7904 = PseudoVSOXSEG3EI64_V_M1_M1_MASK + {5, OperandInfo781}, // Inst #7905 = PseudoVSOXSEG3EI64_V_M1_MF2 + {6, OperandInfo782}, // Inst #7906 = PseudoVSOXSEG3EI64_V_M1_MF2_MASK + {5, OperandInfo781}, // Inst #7907 = PseudoVSOXSEG3EI64_V_M1_MF4 + {6, OperandInfo782}, // Inst #7908 = PseudoVSOXSEG3EI64_V_M1_MF4_MASK + {5, OperandInfo781}, // Inst #7909 = PseudoVSOXSEG3EI64_V_M1_MF8 + {6, OperandInfo782}, // Inst #7910 = PseudoVSOXSEG3EI64_V_M1_MF8_MASK + {5, OperandInfo785}, // Inst #7911 = PseudoVSOXSEG3EI64_V_M2_M1 + {6, OperandInfo786}, // Inst #7912 = PseudoVSOXSEG3EI64_V_M2_M1_MASK + {5, OperandInfo787}, // Inst #7913 = PseudoVSOXSEG3EI64_V_M2_M2 + {6, OperandInfo788}, // Inst #7914 = PseudoVSOXSEG3EI64_V_M2_M2_MASK + {5, OperandInfo785}, // Inst #7915 = PseudoVSOXSEG3EI64_V_M2_MF2 + {6, OperandInfo786}, // Inst #7916 = PseudoVSOXSEG3EI64_V_M2_MF2_MASK + {5, OperandInfo785}, // Inst #7917 = PseudoVSOXSEG3EI64_V_M2_MF4 + {6, OperandInfo786}, // Inst #7918 = PseudoVSOXSEG3EI64_V_M2_MF4_MASK + {5, OperandInfo791}, // Inst #7919 = PseudoVSOXSEG3EI64_V_M4_M1 + {6, OperandInfo792}, // Inst #7920 = PseudoVSOXSEG3EI64_V_M4_M1_MASK + {5, OperandInfo789}, // Inst #7921 = PseudoVSOXSEG3EI64_V_M4_M2 + {6, OperandInfo790}, // Inst #7922 = PseudoVSOXSEG3EI64_V_M4_M2_MASK + {5, OperandInfo791}, // Inst #7923 = PseudoVSOXSEG3EI64_V_M4_MF2 + {6, OperandInfo792}, // Inst #7924 = PseudoVSOXSEG3EI64_V_M4_MF2_MASK + {5, OperandInfo795}, // Inst #7925 = PseudoVSOXSEG3EI64_V_M8_M1 + {6, OperandInfo796}, // Inst #7926 = PseudoVSOXSEG3EI64_V_M8_M1_MASK + {5, OperandInfo793}, // Inst #7927 = PseudoVSOXSEG3EI64_V_M8_M2 + {6, OperandInfo794}, // Inst #7928 = PseudoVSOXSEG3EI64_V_M8_M2_MASK + {5, OperandInfo781}, // Inst #7929 = PseudoVSOXSEG3EI8_V_M1_M1 + {6, OperandInfo782}, // Inst #7930 = PseudoVSOXSEG3EI8_V_M1_M1_MASK + {5, OperandInfo783}, // Inst #7931 = PseudoVSOXSEG3EI8_V_M1_M2 + {6, OperandInfo784}, // Inst #7932 = PseudoVSOXSEG3EI8_V_M1_M2_MASK + {5, OperandInfo787}, // Inst #7933 = PseudoVSOXSEG3EI8_V_M2_M2 + {6, OperandInfo788}, // Inst #7934 = PseudoVSOXSEG3EI8_V_M2_M2_MASK + {5, OperandInfo781}, // Inst #7935 = PseudoVSOXSEG3EI8_V_MF2_M1 + {6, OperandInfo782}, // Inst #7936 = PseudoVSOXSEG3EI8_V_MF2_M1_MASK + {5, OperandInfo783}, // Inst #7937 = PseudoVSOXSEG3EI8_V_MF2_M2 + {6, OperandInfo784}, // Inst #7938 = PseudoVSOXSEG3EI8_V_MF2_M2_MASK + {5, OperandInfo781}, // Inst #7939 = PseudoVSOXSEG3EI8_V_MF2_MF2 + {6, OperandInfo782}, // Inst #7940 = PseudoVSOXSEG3EI8_V_MF2_MF2_MASK + {5, OperandInfo781}, // Inst #7941 = PseudoVSOXSEG3EI8_V_MF4_M1 + {6, OperandInfo782}, // Inst #7942 = PseudoVSOXSEG3EI8_V_MF4_M1_MASK + {5, OperandInfo783}, // Inst #7943 = PseudoVSOXSEG3EI8_V_MF4_M2 + {6, OperandInfo784}, // Inst #7944 = PseudoVSOXSEG3EI8_V_MF4_M2_MASK + {5, OperandInfo781}, // Inst #7945 = PseudoVSOXSEG3EI8_V_MF4_MF2 + {6, OperandInfo782}, // Inst #7946 = PseudoVSOXSEG3EI8_V_MF4_MF2_MASK + {5, OperandInfo781}, // Inst #7947 = PseudoVSOXSEG3EI8_V_MF4_MF4 + {6, OperandInfo782}, // Inst #7948 = PseudoVSOXSEG3EI8_V_MF4_MF4_MASK + {5, OperandInfo781}, // Inst #7949 = PseudoVSOXSEG3EI8_V_MF8_M1 + {6, OperandInfo782}, // Inst #7950 = PseudoVSOXSEG3EI8_V_MF8_M1_MASK + {5, OperandInfo781}, // Inst #7951 = PseudoVSOXSEG3EI8_V_MF8_MF2 + {6, OperandInfo782}, // Inst #7952 = PseudoVSOXSEG3EI8_V_MF8_MF2_MASK + {5, OperandInfo781}, // Inst #7953 = PseudoVSOXSEG3EI8_V_MF8_MF4 + {6, OperandInfo782}, // Inst #7954 = PseudoVSOXSEG3EI8_V_MF8_MF4_MASK + {5, OperandInfo781}, // Inst #7955 = PseudoVSOXSEG3EI8_V_MF8_MF8 + {6, OperandInfo782}, // Inst #7956 = PseudoVSOXSEG3EI8_V_MF8_MF8_MASK + {5, OperandInfo797}, // Inst #7957 = PseudoVSOXSEG4EI16_V_M1_M1 + {6, OperandInfo798}, // Inst #7958 = PseudoVSOXSEG4EI16_V_M1_M1_MASK + {5, OperandInfo799}, // Inst #7959 = PseudoVSOXSEG4EI16_V_M1_M2 + {6, OperandInfo800}, // Inst #7960 = PseudoVSOXSEG4EI16_V_M1_M2_MASK + {5, OperandInfo797}, // Inst #7961 = PseudoVSOXSEG4EI16_V_M1_MF2 + {6, OperandInfo798}, // Inst #7962 = PseudoVSOXSEG4EI16_V_M1_MF2_MASK + {5, OperandInfo801}, // Inst #7963 = PseudoVSOXSEG4EI16_V_M2_M1 + {6, OperandInfo802}, // Inst #7964 = PseudoVSOXSEG4EI16_V_M2_M1_MASK + {5, OperandInfo803}, // Inst #7965 = PseudoVSOXSEG4EI16_V_M2_M2 + {6, OperandInfo804}, // Inst #7966 = PseudoVSOXSEG4EI16_V_M2_M2_MASK + {5, OperandInfo805}, // Inst #7967 = PseudoVSOXSEG4EI16_V_M4_M2 + {6, OperandInfo806}, // Inst #7968 = PseudoVSOXSEG4EI16_V_M4_M2_MASK + {5, OperandInfo797}, // Inst #7969 = PseudoVSOXSEG4EI16_V_MF2_M1 + {6, OperandInfo798}, // Inst #7970 = PseudoVSOXSEG4EI16_V_MF2_M1_MASK + {5, OperandInfo799}, // Inst #7971 = PseudoVSOXSEG4EI16_V_MF2_M2 + {6, OperandInfo800}, // Inst #7972 = PseudoVSOXSEG4EI16_V_MF2_M2_MASK + {5, OperandInfo797}, // Inst #7973 = PseudoVSOXSEG4EI16_V_MF2_MF2 + {6, OperandInfo798}, // Inst #7974 = PseudoVSOXSEG4EI16_V_MF2_MF2_MASK + {5, OperandInfo797}, // Inst #7975 = PseudoVSOXSEG4EI16_V_MF2_MF4 + {6, OperandInfo798}, // Inst #7976 = PseudoVSOXSEG4EI16_V_MF2_MF4_MASK + {5, OperandInfo797}, // Inst #7977 = PseudoVSOXSEG4EI16_V_MF4_M1 + {6, OperandInfo798}, // Inst #7978 = PseudoVSOXSEG4EI16_V_MF4_M1_MASK + {5, OperandInfo797}, // Inst #7979 = PseudoVSOXSEG4EI16_V_MF4_MF2 + {6, OperandInfo798}, // Inst #7980 = PseudoVSOXSEG4EI16_V_MF4_MF2_MASK + {5, OperandInfo797}, // Inst #7981 = PseudoVSOXSEG4EI16_V_MF4_MF4 + {6, OperandInfo798}, // Inst #7982 = PseudoVSOXSEG4EI16_V_MF4_MF4_MASK + {5, OperandInfo797}, // Inst #7983 = PseudoVSOXSEG4EI16_V_MF4_MF8 + {6, OperandInfo798}, // Inst #7984 = PseudoVSOXSEG4EI16_V_MF4_MF8_MASK + {5, OperandInfo797}, // Inst #7985 = PseudoVSOXSEG4EI32_V_M1_M1 + {6, OperandInfo798}, // Inst #7986 = PseudoVSOXSEG4EI32_V_M1_M1_MASK + {5, OperandInfo799}, // Inst #7987 = PseudoVSOXSEG4EI32_V_M1_M2 + {6, OperandInfo800}, // Inst #7988 = PseudoVSOXSEG4EI32_V_M1_M2_MASK + {5, OperandInfo797}, // Inst #7989 = PseudoVSOXSEG4EI32_V_M1_MF2 + {6, OperandInfo798}, // Inst #7990 = PseudoVSOXSEG4EI32_V_M1_MF2_MASK + {5, OperandInfo797}, // Inst #7991 = PseudoVSOXSEG4EI32_V_M1_MF4 + {6, OperandInfo798}, // Inst #7992 = PseudoVSOXSEG4EI32_V_M1_MF4_MASK + {5, OperandInfo801}, // Inst #7993 = PseudoVSOXSEG4EI32_V_M2_M1 + {6, OperandInfo802}, // Inst #7994 = PseudoVSOXSEG4EI32_V_M2_M1_MASK + {5, OperandInfo803}, // Inst #7995 = PseudoVSOXSEG4EI32_V_M2_M2 + {6, OperandInfo804}, // Inst #7996 = PseudoVSOXSEG4EI32_V_M2_M2_MASK + {5, OperandInfo801}, // Inst #7997 = PseudoVSOXSEG4EI32_V_M2_MF2 + {6, OperandInfo802}, // Inst #7998 = PseudoVSOXSEG4EI32_V_M2_MF2_MASK + {5, OperandInfo807}, // Inst #7999 = PseudoVSOXSEG4EI32_V_M4_M1 + {6, OperandInfo808}, // Inst #8000 = PseudoVSOXSEG4EI32_V_M4_M1_MASK + {5, OperandInfo805}, // Inst #8001 = PseudoVSOXSEG4EI32_V_M4_M2 + {6, OperandInfo806}, // Inst #8002 = PseudoVSOXSEG4EI32_V_M4_M2_MASK + {5, OperandInfo809}, // Inst #8003 = PseudoVSOXSEG4EI32_V_M8_M2 + {6, OperandInfo810}, // Inst #8004 = PseudoVSOXSEG4EI32_V_M8_M2_MASK + {5, OperandInfo797}, // Inst #8005 = PseudoVSOXSEG4EI32_V_MF2_M1 + {6, OperandInfo798}, // Inst #8006 = PseudoVSOXSEG4EI32_V_MF2_M1_MASK + {5, OperandInfo797}, // Inst #8007 = PseudoVSOXSEG4EI32_V_MF2_MF2 + {6, OperandInfo798}, // Inst #8008 = PseudoVSOXSEG4EI32_V_MF2_MF2_MASK + {5, OperandInfo797}, // Inst #8009 = PseudoVSOXSEG4EI32_V_MF2_MF4 + {6, OperandInfo798}, // Inst #8010 = PseudoVSOXSEG4EI32_V_MF2_MF4_MASK + {5, OperandInfo797}, // Inst #8011 = PseudoVSOXSEG4EI32_V_MF2_MF8 + {6, OperandInfo798}, // Inst #8012 = PseudoVSOXSEG4EI32_V_MF2_MF8_MASK + {5, OperandInfo797}, // Inst #8013 = PseudoVSOXSEG4EI64_V_M1_M1 + {6, OperandInfo798}, // Inst #8014 = PseudoVSOXSEG4EI64_V_M1_M1_MASK + {5, OperandInfo797}, // Inst #8015 = PseudoVSOXSEG4EI64_V_M1_MF2 + {6, OperandInfo798}, // Inst #8016 = PseudoVSOXSEG4EI64_V_M1_MF2_MASK + {5, OperandInfo797}, // Inst #8017 = PseudoVSOXSEG4EI64_V_M1_MF4 + {6, OperandInfo798}, // Inst #8018 = PseudoVSOXSEG4EI64_V_M1_MF4_MASK + {5, OperandInfo797}, // Inst #8019 = PseudoVSOXSEG4EI64_V_M1_MF8 + {6, OperandInfo798}, // Inst #8020 = PseudoVSOXSEG4EI64_V_M1_MF8_MASK + {5, OperandInfo801}, // Inst #8021 = PseudoVSOXSEG4EI64_V_M2_M1 + {6, OperandInfo802}, // Inst #8022 = PseudoVSOXSEG4EI64_V_M2_M1_MASK + {5, OperandInfo803}, // Inst #8023 = PseudoVSOXSEG4EI64_V_M2_M2 + {6, OperandInfo804}, // Inst #8024 = PseudoVSOXSEG4EI64_V_M2_M2_MASK + {5, OperandInfo801}, // Inst #8025 = PseudoVSOXSEG4EI64_V_M2_MF2 + {6, OperandInfo802}, // Inst #8026 = PseudoVSOXSEG4EI64_V_M2_MF2_MASK + {5, OperandInfo801}, // Inst #8027 = PseudoVSOXSEG4EI64_V_M2_MF4 + {6, OperandInfo802}, // Inst #8028 = PseudoVSOXSEG4EI64_V_M2_MF4_MASK + {5, OperandInfo807}, // Inst #8029 = PseudoVSOXSEG4EI64_V_M4_M1 + {6, OperandInfo808}, // Inst #8030 = PseudoVSOXSEG4EI64_V_M4_M1_MASK + {5, OperandInfo805}, // Inst #8031 = PseudoVSOXSEG4EI64_V_M4_M2 + {6, OperandInfo806}, // Inst #8032 = PseudoVSOXSEG4EI64_V_M4_M2_MASK + {5, OperandInfo807}, // Inst #8033 = PseudoVSOXSEG4EI64_V_M4_MF2 + {6, OperandInfo808}, // Inst #8034 = PseudoVSOXSEG4EI64_V_M4_MF2_MASK + {5, OperandInfo811}, // Inst #8035 = PseudoVSOXSEG4EI64_V_M8_M1 + {6, OperandInfo812}, // Inst #8036 = PseudoVSOXSEG4EI64_V_M8_M1_MASK + {5, OperandInfo809}, // Inst #8037 = PseudoVSOXSEG4EI64_V_M8_M2 + {6, OperandInfo810}, // Inst #8038 = PseudoVSOXSEG4EI64_V_M8_M2_MASK + {5, OperandInfo797}, // Inst #8039 = PseudoVSOXSEG4EI8_V_M1_M1 + {6, OperandInfo798}, // Inst #8040 = PseudoVSOXSEG4EI8_V_M1_M1_MASK + {5, OperandInfo799}, // Inst #8041 = PseudoVSOXSEG4EI8_V_M1_M2 + {6, OperandInfo800}, // Inst #8042 = PseudoVSOXSEG4EI8_V_M1_M2_MASK + {5, OperandInfo803}, // Inst #8043 = PseudoVSOXSEG4EI8_V_M2_M2 + {6, OperandInfo804}, // Inst #8044 = PseudoVSOXSEG4EI8_V_M2_M2_MASK + {5, OperandInfo797}, // Inst #8045 = PseudoVSOXSEG4EI8_V_MF2_M1 + {6, OperandInfo798}, // Inst #8046 = PseudoVSOXSEG4EI8_V_MF2_M1_MASK + {5, OperandInfo799}, // Inst #8047 = PseudoVSOXSEG4EI8_V_MF2_M2 + {6, OperandInfo800}, // Inst #8048 = PseudoVSOXSEG4EI8_V_MF2_M2_MASK + {5, OperandInfo797}, // Inst #8049 = PseudoVSOXSEG4EI8_V_MF2_MF2 + {6, OperandInfo798}, // Inst #8050 = PseudoVSOXSEG4EI8_V_MF2_MF2_MASK + {5, OperandInfo797}, // Inst #8051 = PseudoVSOXSEG4EI8_V_MF4_M1 + {6, OperandInfo798}, // Inst #8052 = PseudoVSOXSEG4EI8_V_MF4_M1_MASK + {5, OperandInfo799}, // Inst #8053 = PseudoVSOXSEG4EI8_V_MF4_M2 + {6, OperandInfo800}, // Inst #8054 = PseudoVSOXSEG4EI8_V_MF4_M2_MASK + {5, OperandInfo797}, // Inst #8055 = PseudoVSOXSEG4EI8_V_MF4_MF2 + {6, OperandInfo798}, // Inst #8056 = PseudoVSOXSEG4EI8_V_MF4_MF2_MASK + {5, OperandInfo797}, // Inst #8057 = PseudoVSOXSEG4EI8_V_MF4_MF4 + {6, OperandInfo798}, // Inst #8058 = PseudoVSOXSEG4EI8_V_MF4_MF4_MASK + {5, OperandInfo797}, // Inst #8059 = PseudoVSOXSEG4EI8_V_MF8_M1 + {6, OperandInfo798}, // Inst #8060 = PseudoVSOXSEG4EI8_V_MF8_M1_MASK + {5, OperandInfo797}, // Inst #8061 = PseudoVSOXSEG4EI8_V_MF8_MF2 + {6, OperandInfo798}, // Inst #8062 = PseudoVSOXSEG4EI8_V_MF8_MF2_MASK + {5, OperandInfo797}, // Inst #8063 = PseudoVSOXSEG4EI8_V_MF8_MF4 + {6, OperandInfo798}, // Inst #8064 = PseudoVSOXSEG4EI8_V_MF8_MF4_MASK + {5, OperandInfo797}, // Inst #8065 = PseudoVSOXSEG4EI8_V_MF8_MF8 + {6, OperandInfo798}, // Inst #8066 = PseudoVSOXSEG4EI8_V_MF8_MF8_MASK + {5, OperandInfo813}, // Inst #8067 = PseudoVSOXSEG5EI16_V_M1_M1 + {6, OperandInfo814}, // Inst #8068 = PseudoVSOXSEG5EI16_V_M1_M1_MASK + {5, OperandInfo813}, // Inst #8069 = PseudoVSOXSEG5EI16_V_M1_MF2 + {6, OperandInfo814}, // Inst #8070 = PseudoVSOXSEG5EI16_V_M1_MF2_MASK + {5, OperandInfo815}, // Inst #8071 = PseudoVSOXSEG5EI16_V_M2_M1 + {6, OperandInfo816}, // Inst #8072 = PseudoVSOXSEG5EI16_V_M2_M1_MASK + {5, OperandInfo813}, // Inst #8073 = PseudoVSOXSEG5EI16_V_MF2_M1 + {6, OperandInfo814}, // Inst #8074 = PseudoVSOXSEG5EI16_V_MF2_M1_MASK + {5, OperandInfo813}, // Inst #8075 = PseudoVSOXSEG5EI16_V_MF2_MF2 + {6, OperandInfo814}, // Inst #8076 = PseudoVSOXSEG5EI16_V_MF2_MF2_MASK + {5, OperandInfo813}, // Inst #8077 = PseudoVSOXSEG5EI16_V_MF2_MF4 + {6, OperandInfo814}, // Inst #8078 = PseudoVSOXSEG5EI16_V_MF2_MF4_MASK + {5, OperandInfo813}, // Inst #8079 = PseudoVSOXSEG5EI16_V_MF4_M1 + {6, OperandInfo814}, // Inst #8080 = PseudoVSOXSEG5EI16_V_MF4_M1_MASK + {5, OperandInfo813}, // Inst #8081 = PseudoVSOXSEG5EI16_V_MF4_MF2 + {6, OperandInfo814}, // Inst #8082 = PseudoVSOXSEG5EI16_V_MF4_MF2_MASK + {5, OperandInfo813}, // Inst #8083 = PseudoVSOXSEG5EI16_V_MF4_MF4 + {6, OperandInfo814}, // Inst #8084 = PseudoVSOXSEG5EI16_V_MF4_MF4_MASK + {5, OperandInfo813}, // Inst #8085 = PseudoVSOXSEG5EI16_V_MF4_MF8 + {6, OperandInfo814}, // Inst #8086 = PseudoVSOXSEG5EI16_V_MF4_MF8_MASK + {5, OperandInfo813}, // Inst #8087 = PseudoVSOXSEG5EI32_V_M1_M1 + {6, OperandInfo814}, // Inst #8088 = PseudoVSOXSEG5EI32_V_M1_M1_MASK + {5, OperandInfo813}, // Inst #8089 = PseudoVSOXSEG5EI32_V_M1_MF2 + {6, OperandInfo814}, // Inst #8090 = PseudoVSOXSEG5EI32_V_M1_MF2_MASK + {5, OperandInfo813}, // Inst #8091 = PseudoVSOXSEG5EI32_V_M1_MF4 + {6, OperandInfo814}, // Inst #8092 = PseudoVSOXSEG5EI32_V_M1_MF4_MASK + {5, OperandInfo815}, // Inst #8093 = PseudoVSOXSEG5EI32_V_M2_M1 + {6, OperandInfo816}, // Inst #8094 = PseudoVSOXSEG5EI32_V_M2_M1_MASK + {5, OperandInfo815}, // Inst #8095 = PseudoVSOXSEG5EI32_V_M2_MF2 + {6, OperandInfo816}, // Inst #8096 = PseudoVSOXSEG5EI32_V_M2_MF2_MASK + {5, OperandInfo817}, // Inst #8097 = PseudoVSOXSEG5EI32_V_M4_M1 + {6, OperandInfo818}, // Inst #8098 = PseudoVSOXSEG5EI32_V_M4_M1_MASK + {5, OperandInfo813}, // Inst #8099 = PseudoVSOXSEG5EI32_V_MF2_M1 + {6, OperandInfo814}, // Inst #8100 = PseudoVSOXSEG5EI32_V_MF2_M1_MASK + {5, OperandInfo813}, // Inst #8101 = PseudoVSOXSEG5EI32_V_MF2_MF2 + {6, OperandInfo814}, // Inst #8102 = PseudoVSOXSEG5EI32_V_MF2_MF2_MASK + {5, OperandInfo813}, // Inst #8103 = PseudoVSOXSEG5EI32_V_MF2_MF4 + {6, OperandInfo814}, // Inst #8104 = PseudoVSOXSEG5EI32_V_MF2_MF4_MASK + {5, OperandInfo813}, // Inst #8105 = PseudoVSOXSEG5EI32_V_MF2_MF8 + {6, OperandInfo814}, // Inst #8106 = PseudoVSOXSEG5EI32_V_MF2_MF8_MASK + {5, OperandInfo813}, // Inst #8107 = PseudoVSOXSEG5EI64_V_M1_M1 + {6, OperandInfo814}, // Inst #8108 = PseudoVSOXSEG5EI64_V_M1_M1_MASK + {5, OperandInfo813}, // Inst #8109 = PseudoVSOXSEG5EI64_V_M1_MF2 + {6, OperandInfo814}, // Inst #8110 = PseudoVSOXSEG5EI64_V_M1_MF2_MASK + {5, OperandInfo813}, // Inst #8111 = PseudoVSOXSEG5EI64_V_M1_MF4 + {6, OperandInfo814}, // Inst #8112 = PseudoVSOXSEG5EI64_V_M1_MF4_MASK + {5, OperandInfo813}, // Inst #8113 = PseudoVSOXSEG5EI64_V_M1_MF8 + {6, OperandInfo814}, // Inst #8114 = PseudoVSOXSEG5EI64_V_M1_MF8_MASK + {5, OperandInfo815}, // Inst #8115 = PseudoVSOXSEG5EI64_V_M2_M1 + {6, OperandInfo816}, // Inst #8116 = PseudoVSOXSEG5EI64_V_M2_M1_MASK + {5, OperandInfo815}, // Inst #8117 = PseudoVSOXSEG5EI64_V_M2_MF2 + {6, OperandInfo816}, // Inst #8118 = PseudoVSOXSEG5EI64_V_M2_MF2_MASK + {5, OperandInfo815}, // Inst #8119 = PseudoVSOXSEG5EI64_V_M2_MF4 + {6, OperandInfo816}, // Inst #8120 = PseudoVSOXSEG5EI64_V_M2_MF4_MASK + {5, OperandInfo817}, // Inst #8121 = PseudoVSOXSEG5EI64_V_M4_M1 + {6, OperandInfo818}, // Inst #8122 = PseudoVSOXSEG5EI64_V_M4_M1_MASK + {5, OperandInfo817}, // Inst #8123 = PseudoVSOXSEG5EI64_V_M4_MF2 + {6, OperandInfo818}, // Inst #8124 = PseudoVSOXSEG5EI64_V_M4_MF2_MASK + {5, OperandInfo819}, // Inst #8125 = PseudoVSOXSEG5EI64_V_M8_M1 + {6, OperandInfo820}, // Inst #8126 = PseudoVSOXSEG5EI64_V_M8_M1_MASK + {5, OperandInfo813}, // Inst #8127 = PseudoVSOXSEG5EI8_V_M1_M1 + {6, OperandInfo814}, // Inst #8128 = PseudoVSOXSEG5EI8_V_M1_M1_MASK + {5, OperandInfo813}, // Inst #8129 = PseudoVSOXSEG5EI8_V_MF2_M1 + {6, OperandInfo814}, // Inst #8130 = PseudoVSOXSEG5EI8_V_MF2_M1_MASK + {5, OperandInfo813}, // Inst #8131 = PseudoVSOXSEG5EI8_V_MF2_MF2 + {6, OperandInfo814}, // Inst #8132 = PseudoVSOXSEG5EI8_V_MF2_MF2_MASK + {5, OperandInfo813}, // Inst #8133 = PseudoVSOXSEG5EI8_V_MF4_M1 + {6, OperandInfo814}, // Inst #8134 = PseudoVSOXSEG5EI8_V_MF4_M1_MASK + {5, OperandInfo813}, // Inst #8135 = PseudoVSOXSEG5EI8_V_MF4_MF2 + {6, OperandInfo814}, // Inst #8136 = PseudoVSOXSEG5EI8_V_MF4_MF2_MASK + {5, OperandInfo813}, // Inst #8137 = PseudoVSOXSEG5EI8_V_MF4_MF4 + {6, OperandInfo814}, // Inst #8138 = PseudoVSOXSEG5EI8_V_MF4_MF4_MASK + {5, OperandInfo813}, // Inst #8139 = PseudoVSOXSEG5EI8_V_MF8_M1 + {6, OperandInfo814}, // Inst #8140 = PseudoVSOXSEG5EI8_V_MF8_M1_MASK + {5, OperandInfo813}, // Inst #8141 = PseudoVSOXSEG5EI8_V_MF8_MF2 + {6, OperandInfo814}, // Inst #8142 = PseudoVSOXSEG5EI8_V_MF8_MF2_MASK + {5, OperandInfo813}, // Inst #8143 = PseudoVSOXSEG5EI8_V_MF8_MF4 + {6, OperandInfo814}, // Inst #8144 = PseudoVSOXSEG5EI8_V_MF8_MF4_MASK + {5, OperandInfo813}, // Inst #8145 = PseudoVSOXSEG5EI8_V_MF8_MF8 + {6, OperandInfo814}, // Inst #8146 = PseudoVSOXSEG5EI8_V_MF8_MF8_MASK + {5, OperandInfo821}, // Inst #8147 = PseudoVSOXSEG6EI16_V_M1_M1 + {6, OperandInfo822}, // Inst #8148 = PseudoVSOXSEG6EI16_V_M1_M1_MASK + {5, OperandInfo821}, // Inst #8149 = PseudoVSOXSEG6EI16_V_M1_MF2 + {6, OperandInfo822}, // Inst #8150 = PseudoVSOXSEG6EI16_V_M1_MF2_MASK + {5, OperandInfo823}, // Inst #8151 = PseudoVSOXSEG6EI16_V_M2_M1 + {6, OperandInfo824}, // Inst #8152 = PseudoVSOXSEG6EI16_V_M2_M1_MASK + {5, OperandInfo821}, // Inst #8153 = PseudoVSOXSEG6EI16_V_MF2_M1 + {6, OperandInfo822}, // Inst #8154 = PseudoVSOXSEG6EI16_V_MF2_M1_MASK + {5, OperandInfo821}, // Inst #8155 = PseudoVSOXSEG6EI16_V_MF2_MF2 + {6, OperandInfo822}, // Inst #8156 = PseudoVSOXSEG6EI16_V_MF2_MF2_MASK + {5, OperandInfo821}, // Inst #8157 = PseudoVSOXSEG6EI16_V_MF2_MF4 + {6, OperandInfo822}, // Inst #8158 = PseudoVSOXSEG6EI16_V_MF2_MF4_MASK + {5, OperandInfo821}, // Inst #8159 = PseudoVSOXSEG6EI16_V_MF4_M1 + {6, OperandInfo822}, // Inst #8160 = PseudoVSOXSEG6EI16_V_MF4_M1_MASK + {5, OperandInfo821}, // Inst #8161 = PseudoVSOXSEG6EI16_V_MF4_MF2 + {6, OperandInfo822}, // Inst #8162 = PseudoVSOXSEG6EI16_V_MF4_MF2_MASK + {5, OperandInfo821}, // Inst #8163 = PseudoVSOXSEG6EI16_V_MF4_MF4 + {6, OperandInfo822}, // Inst #8164 = PseudoVSOXSEG6EI16_V_MF4_MF4_MASK + {5, OperandInfo821}, // Inst #8165 = PseudoVSOXSEG6EI16_V_MF4_MF8 + {6, OperandInfo822}, // Inst #8166 = PseudoVSOXSEG6EI16_V_MF4_MF8_MASK + {5, OperandInfo821}, // Inst #8167 = PseudoVSOXSEG6EI32_V_M1_M1 + {6, OperandInfo822}, // Inst #8168 = PseudoVSOXSEG6EI32_V_M1_M1_MASK + {5, OperandInfo821}, // Inst #8169 = PseudoVSOXSEG6EI32_V_M1_MF2 + {6, OperandInfo822}, // Inst #8170 = PseudoVSOXSEG6EI32_V_M1_MF2_MASK + {5, OperandInfo821}, // Inst #8171 = PseudoVSOXSEG6EI32_V_M1_MF4 + {6, OperandInfo822}, // Inst #8172 = PseudoVSOXSEG6EI32_V_M1_MF4_MASK + {5, OperandInfo823}, // Inst #8173 = PseudoVSOXSEG6EI32_V_M2_M1 + {6, OperandInfo824}, // Inst #8174 = PseudoVSOXSEG6EI32_V_M2_M1_MASK + {5, OperandInfo823}, // Inst #8175 = PseudoVSOXSEG6EI32_V_M2_MF2 + {6, OperandInfo824}, // Inst #8176 = PseudoVSOXSEG6EI32_V_M2_MF2_MASK + {5, OperandInfo825}, // Inst #8177 = PseudoVSOXSEG6EI32_V_M4_M1 + {6, OperandInfo826}, // Inst #8178 = PseudoVSOXSEG6EI32_V_M4_M1_MASK + {5, OperandInfo821}, // Inst #8179 = PseudoVSOXSEG6EI32_V_MF2_M1 + {6, OperandInfo822}, // Inst #8180 = PseudoVSOXSEG6EI32_V_MF2_M1_MASK + {5, OperandInfo821}, // Inst #8181 = PseudoVSOXSEG6EI32_V_MF2_MF2 + {6, OperandInfo822}, // Inst #8182 = PseudoVSOXSEG6EI32_V_MF2_MF2_MASK + {5, OperandInfo821}, // Inst #8183 = PseudoVSOXSEG6EI32_V_MF2_MF4 + {6, OperandInfo822}, // Inst #8184 = PseudoVSOXSEG6EI32_V_MF2_MF4_MASK + {5, OperandInfo821}, // Inst #8185 = PseudoVSOXSEG6EI32_V_MF2_MF8 + {6, OperandInfo822}, // Inst #8186 = PseudoVSOXSEG6EI32_V_MF2_MF8_MASK + {5, OperandInfo821}, // Inst #8187 = PseudoVSOXSEG6EI64_V_M1_M1 + {6, OperandInfo822}, // Inst #8188 = PseudoVSOXSEG6EI64_V_M1_M1_MASK + {5, OperandInfo821}, // Inst #8189 = PseudoVSOXSEG6EI64_V_M1_MF2 + {6, OperandInfo822}, // Inst #8190 = PseudoVSOXSEG6EI64_V_M1_MF2_MASK + {5, OperandInfo821}, // Inst #8191 = PseudoVSOXSEG6EI64_V_M1_MF4 + {6, OperandInfo822}, // Inst #8192 = PseudoVSOXSEG6EI64_V_M1_MF4_MASK + {5, OperandInfo821}, // Inst #8193 = PseudoVSOXSEG6EI64_V_M1_MF8 + {6, OperandInfo822}, // Inst #8194 = PseudoVSOXSEG6EI64_V_M1_MF8_MASK + {5, OperandInfo823}, // Inst #8195 = PseudoVSOXSEG6EI64_V_M2_M1 + {6, OperandInfo824}, // Inst #8196 = PseudoVSOXSEG6EI64_V_M2_M1_MASK + {5, OperandInfo823}, // Inst #8197 = PseudoVSOXSEG6EI64_V_M2_MF2 + {6, OperandInfo824}, // Inst #8198 = PseudoVSOXSEG6EI64_V_M2_MF2_MASK + {5, OperandInfo823}, // Inst #8199 = PseudoVSOXSEG6EI64_V_M2_MF4 + {6, OperandInfo824}, // Inst #8200 = PseudoVSOXSEG6EI64_V_M2_MF4_MASK + {5, OperandInfo825}, // Inst #8201 = PseudoVSOXSEG6EI64_V_M4_M1 + {6, OperandInfo826}, // Inst #8202 = PseudoVSOXSEG6EI64_V_M4_M1_MASK + {5, OperandInfo825}, // Inst #8203 = PseudoVSOXSEG6EI64_V_M4_MF2 + {6, OperandInfo826}, // Inst #8204 = PseudoVSOXSEG6EI64_V_M4_MF2_MASK + {5, OperandInfo827}, // Inst #8205 = PseudoVSOXSEG6EI64_V_M8_M1 + {6, OperandInfo828}, // Inst #8206 = PseudoVSOXSEG6EI64_V_M8_M1_MASK + {5, OperandInfo821}, // Inst #8207 = PseudoVSOXSEG6EI8_V_M1_M1 + {6, OperandInfo822}, // Inst #8208 = PseudoVSOXSEG6EI8_V_M1_M1_MASK + {5, OperandInfo821}, // Inst #8209 = PseudoVSOXSEG6EI8_V_MF2_M1 + {6, OperandInfo822}, // Inst #8210 = PseudoVSOXSEG6EI8_V_MF2_M1_MASK + {5, OperandInfo821}, // Inst #8211 = PseudoVSOXSEG6EI8_V_MF2_MF2 + {6, OperandInfo822}, // Inst #8212 = PseudoVSOXSEG6EI8_V_MF2_MF2_MASK + {5, OperandInfo821}, // Inst #8213 = PseudoVSOXSEG6EI8_V_MF4_M1 + {6, OperandInfo822}, // Inst #8214 = PseudoVSOXSEG6EI8_V_MF4_M1_MASK + {5, OperandInfo821}, // Inst #8215 = PseudoVSOXSEG6EI8_V_MF4_MF2 + {6, OperandInfo822}, // Inst #8216 = PseudoVSOXSEG6EI8_V_MF4_MF2_MASK + {5, OperandInfo821}, // Inst #8217 = PseudoVSOXSEG6EI8_V_MF4_MF4 + {6, OperandInfo822}, // Inst #8218 = PseudoVSOXSEG6EI8_V_MF4_MF4_MASK + {5, OperandInfo821}, // Inst #8219 = PseudoVSOXSEG6EI8_V_MF8_M1 + {6, OperandInfo822}, // Inst #8220 = PseudoVSOXSEG6EI8_V_MF8_M1_MASK + {5, OperandInfo821}, // Inst #8221 = PseudoVSOXSEG6EI8_V_MF8_MF2 + {6, OperandInfo822}, // Inst #8222 = PseudoVSOXSEG6EI8_V_MF8_MF2_MASK + {5, OperandInfo821}, // Inst #8223 = PseudoVSOXSEG6EI8_V_MF8_MF4 + {6, OperandInfo822}, // Inst #8224 = PseudoVSOXSEG6EI8_V_MF8_MF4_MASK + {5, OperandInfo821}, // Inst #8225 = PseudoVSOXSEG6EI8_V_MF8_MF8 + {6, OperandInfo822}, // Inst #8226 = PseudoVSOXSEG6EI8_V_MF8_MF8_MASK + {5, OperandInfo829}, // Inst #8227 = PseudoVSOXSEG7EI16_V_M1_M1 + {6, OperandInfo830}, // Inst #8228 = PseudoVSOXSEG7EI16_V_M1_M1_MASK + {5, OperandInfo829}, // Inst #8229 = PseudoVSOXSEG7EI16_V_M1_MF2 + {6, OperandInfo830}, // Inst #8230 = PseudoVSOXSEG7EI16_V_M1_MF2_MASK + {5, OperandInfo831}, // Inst #8231 = PseudoVSOXSEG7EI16_V_M2_M1 + {6, OperandInfo832}, // Inst #8232 = PseudoVSOXSEG7EI16_V_M2_M1_MASK + {5, OperandInfo829}, // Inst #8233 = PseudoVSOXSEG7EI16_V_MF2_M1 + {6, OperandInfo830}, // Inst #8234 = PseudoVSOXSEG7EI16_V_MF2_M1_MASK + {5, OperandInfo829}, // Inst #8235 = PseudoVSOXSEG7EI16_V_MF2_MF2 + {6, OperandInfo830}, // Inst #8236 = PseudoVSOXSEG7EI16_V_MF2_MF2_MASK + {5, OperandInfo829}, // Inst #8237 = PseudoVSOXSEG7EI16_V_MF2_MF4 + {6, OperandInfo830}, // Inst #8238 = PseudoVSOXSEG7EI16_V_MF2_MF4_MASK + {5, OperandInfo829}, // Inst #8239 = PseudoVSOXSEG7EI16_V_MF4_M1 + {6, OperandInfo830}, // Inst #8240 = PseudoVSOXSEG7EI16_V_MF4_M1_MASK + {5, OperandInfo829}, // Inst #8241 = PseudoVSOXSEG7EI16_V_MF4_MF2 + {6, OperandInfo830}, // Inst #8242 = PseudoVSOXSEG7EI16_V_MF4_MF2_MASK + {5, OperandInfo829}, // Inst #8243 = PseudoVSOXSEG7EI16_V_MF4_MF4 + {6, OperandInfo830}, // Inst #8244 = PseudoVSOXSEG7EI16_V_MF4_MF4_MASK + {5, OperandInfo829}, // Inst #8245 = PseudoVSOXSEG7EI16_V_MF4_MF8 + {6, OperandInfo830}, // Inst #8246 = PseudoVSOXSEG7EI16_V_MF4_MF8_MASK + {5, OperandInfo829}, // Inst #8247 = PseudoVSOXSEG7EI32_V_M1_M1 + {6, OperandInfo830}, // Inst #8248 = PseudoVSOXSEG7EI32_V_M1_M1_MASK + {5, OperandInfo829}, // Inst #8249 = PseudoVSOXSEG7EI32_V_M1_MF2 + {6, OperandInfo830}, // Inst #8250 = PseudoVSOXSEG7EI32_V_M1_MF2_MASK + {5, OperandInfo829}, // Inst #8251 = PseudoVSOXSEG7EI32_V_M1_MF4 + {6, OperandInfo830}, // Inst #8252 = PseudoVSOXSEG7EI32_V_M1_MF4_MASK + {5, OperandInfo831}, // Inst #8253 = PseudoVSOXSEG7EI32_V_M2_M1 + {6, OperandInfo832}, // Inst #8254 = PseudoVSOXSEG7EI32_V_M2_M1_MASK + {5, OperandInfo831}, // Inst #8255 = PseudoVSOXSEG7EI32_V_M2_MF2 + {6, OperandInfo832}, // Inst #8256 = PseudoVSOXSEG7EI32_V_M2_MF2_MASK + {5, OperandInfo833}, // Inst #8257 = PseudoVSOXSEG7EI32_V_M4_M1 + {6, OperandInfo834}, // Inst #8258 = PseudoVSOXSEG7EI32_V_M4_M1_MASK + {5, OperandInfo829}, // Inst #8259 = PseudoVSOXSEG7EI32_V_MF2_M1 + {6, OperandInfo830}, // Inst #8260 = PseudoVSOXSEG7EI32_V_MF2_M1_MASK + {5, OperandInfo829}, // Inst #8261 = PseudoVSOXSEG7EI32_V_MF2_MF2 + {6, OperandInfo830}, // Inst #8262 = PseudoVSOXSEG7EI32_V_MF2_MF2_MASK + {5, OperandInfo829}, // Inst #8263 = PseudoVSOXSEG7EI32_V_MF2_MF4 + {6, OperandInfo830}, // Inst #8264 = PseudoVSOXSEG7EI32_V_MF2_MF4_MASK + {5, OperandInfo829}, // Inst #8265 = PseudoVSOXSEG7EI32_V_MF2_MF8 + {6, OperandInfo830}, // Inst #8266 = PseudoVSOXSEG7EI32_V_MF2_MF8_MASK + {5, OperandInfo829}, // Inst #8267 = PseudoVSOXSEG7EI64_V_M1_M1 + {6, OperandInfo830}, // Inst #8268 = PseudoVSOXSEG7EI64_V_M1_M1_MASK + {5, OperandInfo829}, // Inst #8269 = PseudoVSOXSEG7EI64_V_M1_MF2 + {6, OperandInfo830}, // Inst #8270 = PseudoVSOXSEG7EI64_V_M1_MF2_MASK + {5, OperandInfo829}, // Inst #8271 = PseudoVSOXSEG7EI64_V_M1_MF4 + {6, OperandInfo830}, // Inst #8272 = PseudoVSOXSEG7EI64_V_M1_MF4_MASK + {5, OperandInfo829}, // Inst #8273 = PseudoVSOXSEG7EI64_V_M1_MF8 + {6, OperandInfo830}, // Inst #8274 = PseudoVSOXSEG7EI64_V_M1_MF8_MASK + {5, OperandInfo831}, // Inst #8275 = PseudoVSOXSEG7EI64_V_M2_M1 + {6, OperandInfo832}, // Inst #8276 = PseudoVSOXSEG7EI64_V_M2_M1_MASK + {5, OperandInfo831}, // Inst #8277 = PseudoVSOXSEG7EI64_V_M2_MF2 + {6, OperandInfo832}, // Inst #8278 = PseudoVSOXSEG7EI64_V_M2_MF2_MASK + {5, OperandInfo831}, // Inst #8279 = PseudoVSOXSEG7EI64_V_M2_MF4 + {6, OperandInfo832}, // Inst #8280 = PseudoVSOXSEG7EI64_V_M2_MF4_MASK + {5, OperandInfo833}, // Inst #8281 = PseudoVSOXSEG7EI64_V_M4_M1 + {6, OperandInfo834}, // Inst #8282 = PseudoVSOXSEG7EI64_V_M4_M1_MASK + {5, OperandInfo833}, // Inst #8283 = PseudoVSOXSEG7EI64_V_M4_MF2 + {6, OperandInfo834}, // Inst #8284 = PseudoVSOXSEG7EI64_V_M4_MF2_MASK + {5, OperandInfo835}, // Inst #8285 = PseudoVSOXSEG7EI64_V_M8_M1 + {6, OperandInfo836}, // Inst #8286 = PseudoVSOXSEG7EI64_V_M8_M1_MASK + {5, OperandInfo829}, // Inst #8287 = PseudoVSOXSEG7EI8_V_M1_M1 + {6, OperandInfo830}, // Inst #8288 = PseudoVSOXSEG7EI8_V_M1_M1_MASK + {5, OperandInfo829}, // Inst #8289 = PseudoVSOXSEG7EI8_V_MF2_M1 + {6, OperandInfo830}, // Inst #8290 = PseudoVSOXSEG7EI8_V_MF2_M1_MASK + {5, OperandInfo829}, // Inst #8291 = PseudoVSOXSEG7EI8_V_MF2_MF2 + {6, OperandInfo830}, // Inst #8292 = PseudoVSOXSEG7EI8_V_MF2_MF2_MASK + {5, OperandInfo829}, // Inst #8293 = PseudoVSOXSEG7EI8_V_MF4_M1 + {6, OperandInfo830}, // Inst #8294 = PseudoVSOXSEG7EI8_V_MF4_M1_MASK + {5, OperandInfo829}, // Inst #8295 = PseudoVSOXSEG7EI8_V_MF4_MF2 + {6, OperandInfo830}, // Inst #8296 = PseudoVSOXSEG7EI8_V_MF4_MF2_MASK + {5, OperandInfo829}, // Inst #8297 = PseudoVSOXSEG7EI8_V_MF4_MF4 + {6, OperandInfo830}, // Inst #8298 = PseudoVSOXSEG7EI8_V_MF4_MF4_MASK + {5, OperandInfo829}, // Inst #8299 = PseudoVSOXSEG7EI8_V_MF8_M1 + {6, OperandInfo830}, // Inst #8300 = PseudoVSOXSEG7EI8_V_MF8_M1_MASK + {5, OperandInfo829}, // Inst #8301 = PseudoVSOXSEG7EI8_V_MF8_MF2 + {6, OperandInfo830}, // Inst #8302 = PseudoVSOXSEG7EI8_V_MF8_MF2_MASK + {5, OperandInfo829}, // Inst #8303 = PseudoVSOXSEG7EI8_V_MF8_MF4 + {6, OperandInfo830}, // Inst #8304 = PseudoVSOXSEG7EI8_V_MF8_MF4_MASK + {5, OperandInfo829}, // Inst #8305 = PseudoVSOXSEG7EI8_V_MF8_MF8 + {6, OperandInfo830}, // Inst #8306 = PseudoVSOXSEG7EI8_V_MF8_MF8_MASK + {5, OperandInfo837}, // Inst #8307 = PseudoVSOXSEG8EI16_V_M1_M1 + {6, OperandInfo838}, // Inst #8308 = PseudoVSOXSEG8EI16_V_M1_M1_MASK + {5, OperandInfo837}, // Inst #8309 = PseudoVSOXSEG8EI16_V_M1_MF2 + {6, OperandInfo838}, // Inst #8310 = PseudoVSOXSEG8EI16_V_M1_MF2_MASK + {5, OperandInfo839}, // Inst #8311 = PseudoVSOXSEG8EI16_V_M2_M1 + {6, OperandInfo840}, // Inst #8312 = PseudoVSOXSEG8EI16_V_M2_M1_MASK + {5, OperandInfo837}, // Inst #8313 = PseudoVSOXSEG8EI16_V_MF2_M1 + {6, OperandInfo838}, // Inst #8314 = PseudoVSOXSEG8EI16_V_MF2_M1_MASK + {5, OperandInfo837}, // Inst #8315 = PseudoVSOXSEG8EI16_V_MF2_MF2 + {6, OperandInfo838}, // Inst #8316 = PseudoVSOXSEG8EI16_V_MF2_MF2_MASK + {5, OperandInfo837}, // Inst #8317 = PseudoVSOXSEG8EI16_V_MF2_MF4 + {6, OperandInfo838}, // Inst #8318 = PseudoVSOXSEG8EI16_V_MF2_MF4_MASK + {5, OperandInfo837}, // Inst #8319 = PseudoVSOXSEG8EI16_V_MF4_M1 + {6, OperandInfo838}, // Inst #8320 = PseudoVSOXSEG8EI16_V_MF4_M1_MASK + {5, OperandInfo837}, // Inst #8321 = PseudoVSOXSEG8EI16_V_MF4_MF2 + {6, OperandInfo838}, // Inst #8322 = PseudoVSOXSEG8EI16_V_MF4_MF2_MASK + {5, OperandInfo837}, // Inst #8323 = PseudoVSOXSEG8EI16_V_MF4_MF4 + {6, OperandInfo838}, // Inst #8324 = PseudoVSOXSEG8EI16_V_MF4_MF4_MASK + {5, OperandInfo837}, // Inst #8325 = PseudoVSOXSEG8EI16_V_MF4_MF8 + {6, OperandInfo838}, // Inst #8326 = PseudoVSOXSEG8EI16_V_MF4_MF8_MASK + {5, OperandInfo837}, // Inst #8327 = PseudoVSOXSEG8EI32_V_M1_M1 + {6, OperandInfo838}, // Inst #8328 = PseudoVSOXSEG8EI32_V_M1_M1_MASK + {5, OperandInfo837}, // Inst #8329 = PseudoVSOXSEG8EI32_V_M1_MF2 + {6, OperandInfo838}, // Inst #8330 = PseudoVSOXSEG8EI32_V_M1_MF2_MASK + {5, OperandInfo837}, // Inst #8331 = PseudoVSOXSEG8EI32_V_M1_MF4 + {6, OperandInfo838}, // Inst #8332 = PseudoVSOXSEG8EI32_V_M1_MF4_MASK + {5, OperandInfo839}, // Inst #8333 = PseudoVSOXSEG8EI32_V_M2_M1 + {6, OperandInfo840}, // Inst #8334 = PseudoVSOXSEG8EI32_V_M2_M1_MASK + {5, OperandInfo839}, // Inst #8335 = PseudoVSOXSEG8EI32_V_M2_MF2 + {6, OperandInfo840}, // Inst #8336 = PseudoVSOXSEG8EI32_V_M2_MF2_MASK + {5, OperandInfo841}, // Inst #8337 = PseudoVSOXSEG8EI32_V_M4_M1 + {6, OperandInfo842}, // Inst #8338 = PseudoVSOXSEG8EI32_V_M4_M1_MASK + {5, OperandInfo837}, // Inst #8339 = PseudoVSOXSEG8EI32_V_MF2_M1 + {6, OperandInfo838}, // Inst #8340 = PseudoVSOXSEG8EI32_V_MF2_M1_MASK + {5, OperandInfo837}, // Inst #8341 = PseudoVSOXSEG8EI32_V_MF2_MF2 + {6, OperandInfo838}, // Inst #8342 = PseudoVSOXSEG8EI32_V_MF2_MF2_MASK + {5, OperandInfo837}, // Inst #8343 = PseudoVSOXSEG8EI32_V_MF2_MF4 + {6, OperandInfo838}, // Inst #8344 = PseudoVSOXSEG8EI32_V_MF2_MF4_MASK + {5, OperandInfo837}, // Inst #8345 = PseudoVSOXSEG8EI32_V_MF2_MF8 + {6, OperandInfo838}, // Inst #8346 = PseudoVSOXSEG8EI32_V_MF2_MF8_MASK + {5, OperandInfo837}, // Inst #8347 = PseudoVSOXSEG8EI64_V_M1_M1 + {6, OperandInfo838}, // Inst #8348 = PseudoVSOXSEG8EI64_V_M1_M1_MASK + {5, OperandInfo837}, // Inst #8349 = PseudoVSOXSEG8EI64_V_M1_MF2 + {6, OperandInfo838}, // Inst #8350 = PseudoVSOXSEG8EI64_V_M1_MF2_MASK + {5, OperandInfo837}, // Inst #8351 = PseudoVSOXSEG8EI64_V_M1_MF4 + {6, OperandInfo838}, // Inst #8352 = PseudoVSOXSEG8EI64_V_M1_MF4_MASK + {5, OperandInfo837}, // Inst #8353 = PseudoVSOXSEG8EI64_V_M1_MF8 + {6, OperandInfo838}, // Inst #8354 = PseudoVSOXSEG8EI64_V_M1_MF8_MASK + {5, OperandInfo839}, // Inst #8355 = PseudoVSOXSEG8EI64_V_M2_M1 + {6, OperandInfo840}, // Inst #8356 = PseudoVSOXSEG8EI64_V_M2_M1_MASK + {5, OperandInfo839}, // Inst #8357 = PseudoVSOXSEG8EI64_V_M2_MF2 + {6, OperandInfo840}, // Inst #8358 = PseudoVSOXSEG8EI64_V_M2_MF2_MASK + {5, OperandInfo839}, // Inst #8359 = PseudoVSOXSEG8EI64_V_M2_MF4 + {6, OperandInfo840}, // Inst #8360 = PseudoVSOXSEG8EI64_V_M2_MF4_MASK + {5, OperandInfo841}, // Inst #8361 = PseudoVSOXSEG8EI64_V_M4_M1 + {6, OperandInfo842}, // Inst #8362 = PseudoVSOXSEG8EI64_V_M4_M1_MASK + {5, OperandInfo841}, // Inst #8363 = PseudoVSOXSEG8EI64_V_M4_MF2 + {6, OperandInfo842}, // Inst #8364 = PseudoVSOXSEG8EI64_V_M4_MF2_MASK + {5, OperandInfo843}, // Inst #8365 = PseudoVSOXSEG8EI64_V_M8_M1 + {6, OperandInfo844}, // Inst #8366 = PseudoVSOXSEG8EI64_V_M8_M1_MASK + {5, OperandInfo837}, // Inst #8367 = PseudoVSOXSEG8EI8_V_M1_M1 + {6, OperandInfo838}, // Inst #8368 = PseudoVSOXSEG8EI8_V_M1_M1_MASK + {5, OperandInfo837}, // Inst #8369 = PseudoVSOXSEG8EI8_V_MF2_M1 + {6, OperandInfo838}, // Inst #8370 = PseudoVSOXSEG8EI8_V_MF2_M1_MASK + {5, OperandInfo837}, // Inst #8371 = PseudoVSOXSEG8EI8_V_MF2_MF2 + {6, OperandInfo838}, // Inst #8372 = PseudoVSOXSEG8EI8_V_MF2_MF2_MASK + {5, OperandInfo837}, // Inst #8373 = PseudoVSOXSEG8EI8_V_MF4_M1 + {6, OperandInfo838}, // Inst #8374 = PseudoVSOXSEG8EI8_V_MF4_M1_MASK + {5, OperandInfo837}, // Inst #8375 = PseudoVSOXSEG8EI8_V_MF4_MF2 + {6, OperandInfo838}, // Inst #8376 = PseudoVSOXSEG8EI8_V_MF4_MF2_MASK + {5, OperandInfo837}, // Inst #8377 = PseudoVSOXSEG8EI8_V_MF4_MF4 + {6, OperandInfo838}, // Inst #8378 = PseudoVSOXSEG8EI8_V_MF4_MF4_MASK + {5, OperandInfo837}, // Inst #8379 = PseudoVSOXSEG8EI8_V_MF8_M1 + {6, OperandInfo838}, // Inst #8380 = PseudoVSOXSEG8EI8_V_MF8_M1_MASK + {5, OperandInfo837}, // Inst #8381 = PseudoVSOXSEG8EI8_V_MF8_MF2 + {6, OperandInfo838}, // Inst #8382 = PseudoVSOXSEG8EI8_V_MF8_MF2_MASK + {5, OperandInfo837}, // Inst #8383 = PseudoVSOXSEG8EI8_V_MF8_MF4 + {6, OperandInfo838}, // Inst #8384 = PseudoVSOXSEG8EI8_V_MF8_MF4_MASK + {5, OperandInfo837}, // Inst #8385 = PseudoVSOXSEG8EI8_V_MF8_MF8 + {6, OperandInfo838}, // Inst #8386 = PseudoVSOXSEG8EI8_V_MF8_MF8_MASK + {3, OperandInfo641}, // Inst #8387 = PseudoVSPILL2_M1 + {3, OperandInfo642}, // Inst #8388 = PseudoVSPILL2_M2 + {3, OperandInfo643}, // Inst #8389 = PseudoVSPILL2_M4 + {3, OperandInfo641}, // Inst #8390 = PseudoVSPILL2_MF2 + {3, OperandInfo641}, // Inst #8391 = PseudoVSPILL2_MF4 + {3, OperandInfo641}, // Inst #8392 = PseudoVSPILL2_MF8 + {3, OperandInfo644}, // Inst #8393 = PseudoVSPILL3_M1 + {3, OperandInfo645}, // Inst #8394 = PseudoVSPILL3_M2 + {3, OperandInfo644}, // Inst #8395 = PseudoVSPILL3_MF2 + {3, OperandInfo644}, // Inst #8396 = PseudoVSPILL3_MF4 + {3, OperandInfo644}, // Inst #8397 = PseudoVSPILL3_MF8 + {3, OperandInfo646}, // Inst #8398 = PseudoVSPILL4_M1 + {3, OperandInfo647}, // Inst #8399 = PseudoVSPILL4_M2 + {3, OperandInfo646}, // Inst #8400 = PseudoVSPILL4_MF2 + {3, OperandInfo646}, // Inst #8401 = PseudoVSPILL4_MF4 + {3, OperandInfo646}, // Inst #8402 = PseudoVSPILL4_MF8 + {3, OperandInfo648}, // Inst #8403 = PseudoVSPILL5_M1 + {3, OperandInfo648}, // Inst #8404 = PseudoVSPILL5_MF2 + {3, OperandInfo648}, // Inst #8405 = PseudoVSPILL5_MF4 + {3, OperandInfo648}, // Inst #8406 = PseudoVSPILL5_MF8 + {3, OperandInfo649}, // Inst #8407 = PseudoVSPILL6_M1 + {3, OperandInfo649}, // Inst #8408 = PseudoVSPILL6_MF2 + {3, OperandInfo649}, // Inst #8409 = PseudoVSPILL6_MF4 + {3, OperandInfo649}, // Inst #8410 = PseudoVSPILL6_MF8 + {3, OperandInfo650}, // Inst #8411 = PseudoVSPILL7_M1 + {3, OperandInfo650}, // Inst #8412 = PseudoVSPILL7_MF2 + {3, OperandInfo650}, // Inst #8413 = PseudoVSPILL7_MF4 + {3, OperandInfo650}, // Inst #8414 = PseudoVSPILL7_MF8 + {3, OperandInfo651}, // Inst #8415 = PseudoVSPILL8_M1 + {3, OperandInfo651}, // Inst #8416 = PseudoVSPILL8_MF2 + {3, OperandInfo651}, // Inst #8417 = PseudoVSPILL8_MF4 + {3, OperandInfo651}, // Inst #8418 = PseudoVSPILL8_MF8 + {2, OperandInfo652}, // Inst #8419 = PseudoVSPILL_M1 + {2, OperandInfo653}, // Inst #8420 = PseudoVSPILL_M2 + {2, OperandInfo654}, // Inst #8421 = PseudoVSPILL_M4 + {2, OperandInfo655}, // Inst #8422 = PseudoVSPILL_M8 + {5, OperandInfo90}, // Inst #8423 = PseudoVSRA_VI_M1 + {8, OperandInfo91}, // Inst #8424 = PseudoVSRA_VI_M1_MASK + {5, OperandInfo92}, // Inst #8425 = PseudoVSRA_VI_M2 + {8, OperandInfo93}, // Inst #8426 = PseudoVSRA_VI_M2_MASK + {5, OperandInfo94}, // Inst #8427 = PseudoVSRA_VI_M4 + {8, OperandInfo95}, // Inst #8428 = PseudoVSRA_VI_M4_MASK + {5, OperandInfo96}, // Inst #8429 = PseudoVSRA_VI_M8 + {8, OperandInfo97}, // Inst #8430 = PseudoVSRA_VI_M8_MASK + {5, OperandInfo90}, // Inst #8431 = PseudoVSRA_VI_MF2 + {8, OperandInfo91}, // Inst #8432 = PseudoVSRA_VI_MF2_MASK + {5, OperandInfo90}, // Inst #8433 = PseudoVSRA_VI_MF4 + {8, OperandInfo91}, // Inst #8434 = PseudoVSRA_VI_MF4_MASK + {5, OperandInfo90}, // Inst #8435 = PseudoVSRA_VI_MF8 + {8, OperandInfo91}, // Inst #8436 = PseudoVSRA_VI_MF8_MASK + {5, OperandInfo62}, // Inst #8437 = PseudoVSRA_VV_M1 + {8, OperandInfo63}, // Inst #8438 = PseudoVSRA_VV_M1_MASK + {5, OperandInfo64}, // Inst #8439 = PseudoVSRA_VV_M2 + {8, OperandInfo65}, // Inst #8440 = PseudoVSRA_VV_M2_MASK + {5, OperandInfo66}, // Inst #8441 = PseudoVSRA_VV_M4 + {8, OperandInfo67}, // Inst #8442 = PseudoVSRA_VV_M4_MASK + {5, OperandInfo68}, // Inst #8443 = PseudoVSRA_VV_M8 + {8, OperandInfo69}, // Inst #8444 = PseudoVSRA_VV_M8_MASK + {5, OperandInfo62}, // Inst #8445 = PseudoVSRA_VV_MF2 + {8, OperandInfo63}, // Inst #8446 = PseudoVSRA_VV_MF2_MASK + {5, OperandInfo62}, // Inst #8447 = PseudoVSRA_VV_MF4 + {8, OperandInfo63}, // Inst #8448 = PseudoVSRA_VV_MF4_MASK + {5, OperandInfo62}, // Inst #8449 = PseudoVSRA_VV_MF8 + {8, OperandInfo63}, // Inst #8450 = PseudoVSRA_VV_MF8_MASK + {5, OperandInfo70}, // Inst #8451 = PseudoVSRA_VX_M1 + {8, OperandInfo71}, // Inst #8452 = PseudoVSRA_VX_M1_MASK + {5, OperandInfo72}, // Inst #8453 = PseudoVSRA_VX_M2 + {8, OperandInfo73}, // Inst #8454 = PseudoVSRA_VX_M2_MASK + {5, OperandInfo74}, // Inst #8455 = PseudoVSRA_VX_M4 + {8, OperandInfo75}, // Inst #8456 = PseudoVSRA_VX_M4_MASK + {5, OperandInfo76}, // Inst #8457 = PseudoVSRA_VX_M8 + {8, OperandInfo77}, // Inst #8458 = PseudoVSRA_VX_M8_MASK + {5, OperandInfo70}, // Inst #8459 = PseudoVSRA_VX_MF2 + {8, OperandInfo71}, // Inst #8460 = PseudoVSRA_VX_MF2_MASK + {5, OperandInfo70}, // Inst #8461 = PseudoVSRA_VX_MF4 + {8, OperandInfo71}, // Inst #8462 = PseudoVSRA_VX_MF4_MASK + {5, OperandInfo70}, // Inst #8463 = PseudoVSRA_VX_MF8 + {8, OperandInfo71}, // Inst #8464 = PseudoVSRA_VX_MF8_MASK + {5, OperandInfo90}, // Inst #8465 = PseudoVSRL_VI_M1 + {8, OperandInfo91}, // Inst #8466 = PseudoVSRL_VI_M1_MASK + {5, OperandInfo92}, // Inst #8467 = PseudoVSRL_VI_M2 + {8, OperandInfo93}, // Inst #8468 = PseudoVSRL_VI_M2_MASK + {5, OperandInfo94}, // Inst #8469 = PseudoVSRL_VI_M4 + {8, OperandInfo95}, // Inst #8470 = PseudoVSRL_VI_M4_MASK + {5, OperandInfo96}, // Inst #8471 = PseudoVSRL_VI_M8 + {8, OperandInfo97}, // Inst #8472 = PseudoVSRL_VI_M8_MASK + {5, OperandInfo90}, // Inst #8473 = PseudoVSRL_VI_MF2 + {8, OperandInfo91}, // Inst #8474 = PseudoVSRL_VI_MF2_MASK + {5, OperandInfo90}, // Inst #8475 = PseudoVSRL_VI_MF4 + {8, OperandInfo91}, // Inst #8476 = PseudoVSRL_VI_MF4_MASK + {5, OperandInfo90}, // Inst #8477 = PseudoVSRL_VI_MF8 + {8, OperandInfo91}, // Inst #8478 = PseudoVSRL_VI_MF8_MASK + {5, OperandInfo62}, // Inst #8479 = PseudoVSRL_VV_M1 + {8, OperandInfo63}, // Inst #8480 = PseudoVSRL_VV_M1_MASK + {5, OperandInfo64}, // Inst #8481 = PseudoVSRL_VV_M2 + {8, OperandInfo65}, // Inst #8482 = PseudoVSRL_VV_M2_MASK + {5, OperandInfo66}, // Inst #8483 = PseudoVSRL_VV_M4 + {8, OperandInfo67}, // Inst #8484 = PseudoVSRL_VV_M4_MASK + {5, OperandInfo68}, // Inst #8485 = PseudoVSRL_VV_M8 + {8, OperandInfo69}, // Inst #8486 = PseudoVSRL_VV_M8_MASK + {5, OperandInfo62}, // Inst #8487 = PseudoVSRL_VV_MF2 + {8, OperandInfo63}, // Inst #8488 = PseudoVSRL_VV_MF2_MASK + {5, OperandInfo62}, // Inst #8489 = PseudoVSRL_VV_MF4 + {8, OperandInfo63}, // Inst #8490 = PseudoVSRL_VV_MF4_MASK + {5, OperandInfo62}, // Inst #8491 = PseudoVSRL_VV_MF8 + {8, OperandInfo63}, // Inst #8492 = PseudoVSRL_VV_MF8_MASK + {5, OperandInfo70}, // Inst #8493 = PseudoVSRL_VX_M1 + {8, OperandInfo71}, // Inst #8494 = PseudoVSRL_VX_M1_MASK + {5, OperandInfo72}, // Inst #8495 = PseudoVSRL_VX_M2 + {8, OperandInfo73}, // Inst #8496 = PseudoVSRL_VX_M2_MASK + {5, OperandInfo74}, // Inst #8497 = PseudoVSRL_VX_M4 + {8, OperandInfo75}, // Inst #8498 = PseudoVSRL_VX_M4_MASK + {5, OperandInfo76}, // Inst #8499 = PseudoVSRL_VX_M8 + {8, OperandInfo77}, // Inst #8500 = PseudoVSRL_VX_M8_MASK + {5, OperandInfo70}, // Inst #8501 = PseudoVSRL_VX_MF2 + {8, OperandInfo71}, // Inst #8502 = PseudoVSRL_VX_MF2_MASK + {5, OperandInfo70}, // Inst #8503 = PseudoVSRL_VX_MF4 + {8, OperandInfo71}, // Inst #8504 = PseudoVSRL_VX_MF4_MASK + {5, OperandInfo70}, // Inst #8505 = PseudoVSRL_VX_MF8 + {8, OperandInfo71}, // Inst #8506 = PseudoVSRL_VX_MF8_MASK + {5, OperandInfo489}, // Inst #8507 = PseudoVSSE16_V_M1 + {6, OperandInfo845}, // Inst #8508 = PseudoVSSE16_V_M1_MASK + {5, OperandInfo491}, // Inst #8509 = PseudoVSSE16_V_M2 + {6, OperandInfo846}, // Inst #8510 = PseudoVSSE16_V_M2_MASK + {5, OperandInfo493}, // Inst #8511 = PseudoVSSE16_V_M4 + {6, OperandInfo847}, // Inst #8512 = PseudoVSSE16_V_M4_MASK + {5, OperandInfo495}, // Inst #8513 = PseudoVSSE16_V_M8 + {6, OperandInfo848}, // Inst #8514 = PseudoVSSE16_V_M8_MASK + {5, OperandInfo489}, // Inst #8515 = PseudoVSSE16_V_MF2 + {6, OperandInfo845}, // Inst #8516 = PseudoVSSE16_V_MF2_MASK + {5, OperandInfo489}, // Inst #8517 = PseudoVSSE16_V_MF4 + {6, OperandInfo845}, // Inst #8518 = PseudoVSSE16_V_MF4_MASK + {5, OperandInfo489}, // Inst #8519 = PseudoVSSE32_V_M1 + {6, OperandInfo845}, // Inst #8520 = PseudoVSSE32_V_M1_MASK + {5, OperandInfo491}, // Inst #8521 = PseudoVSSE32_V_M2 + {6, OperandInfo846}, // Inst #8522 = PseudoVSSE32_V_M2_MASK + {5, OperandInfo493}, // Inst #8523 = PseudoVSSE32_V_M4 + {6, OperandInfo847}, // Inst #8524 = PseudoVSSE32_V_M4_MASK + {5, OperandInfo495}, // Inst #8525 = PseudoVSSE32_V_M8 + {6, OperandInfo848}, // Inst #8526 = PseudoVSSE32_V_M8_MASK + {5, OperandInfo489}, // Inst #8527 = PseudoVSSE32_V_MF2 + {6, OperandInfo845}, // Inst #8528 = PseudoVSSE32_V_MF2_MASK + {5, OperandInfo489}, // Inst #8529 = PseudoVSSE64_V_M1 + {6, OperandInfo845}, // Inst #8530 = PseudoVSSE64_V_M1_MASK + {5, OperandInfo491}, // Inst #8531 = PseudoVSSE64_V_M2 + {6, OperandInfo846}, // Inst #8532 = PseudoVSSE64_V_M2_MASK + {5, OperandInfo493}, // Inst #8533 = PseudoVSSE64_V_M4 + {6, OperandInfo847}, // Inst #8534 = PseudoVSSE64_V_M4_MASK + {5, OperandInfo495}, // Inst #8535 = PseudoVSSE64_V_M8 + {6, OperandInfo848}, // Inst #8536 = PseudoVSSE64_V_M8_MASK + {5, OperandInfo489}, // Inst #8537 = PseudoVSSE8_V_M1 + {6, OperandInfo845}, // Inst #8538 = PseudoVSSE8_V_M1_MASK + {5, OperandInfo491}, // Inst #8539 = PseudoVSSE8_V_M2 + {6, OperandInfo846}, // Inst #8540 = PseudoVSSE8_V_M2_MASK + {5, OperandInfo493}, // Inst #8541 = PseudoVSSE8_V_M4 + {6, OperandInfo847}, // Inst #8542 = PseudoVSSE8_V_M4_MASK + {5, OperandInfo495}, // Inst #8543 = PseudoVSSE8_V_M8 + {6, OperandInfo848}, // Inst #8544 = PseudoVSSE8_V_M8_MASK + {5, OperandInfo489}, // Inst #8545 = PseudoVSSE8_V_MF2 + {6, OperandInfo845}, // Inst #8546 = PseudoVSSE8_V_MF2_MASK + {5, OperandInfo489}, // Inst #8547 = PseudoVSSE8_V_MF4 + {6, OperandInfo845}, // Inst #8548 = PseudoVSSE8_V_MF4_MASK + {5, OperandInfo489}, // Inst #8549 = PseudoVSSE8_V_MF8 + {6, OperandInfo845}, // Inst #8550 = PseudoVSSE8_V_MF8_MASK + {4, OperandInfo497}, // Inst #8551 = PseudoVSSEG2E16_V_M1 + {5, OperandInfo849}, // Inst #8552 = PseudoVSSEG2E16_V_M1_MASK + {4, OperandInfo499}, // Inst #8553 = PseudoVSSEG2E16_V_M2 + {5, OperandInfo850}, // Inst #8554 = PseudoVSSEG2E16_V_M2_MASK + {4, OperandInfo501}, // Inst #8555 = PseudoVSSEG2E16_V_M4 + {5, OperandInfo851}, // Inst #8556 = PseudoVSSEG2E16_V_M4_MASK + {4, OperandInfo497}, // Inst #8557 = PseudoVSSEG2E16_V_MF2 + {5, OperandInfo849}, // Inst #8558 = PseudoVSSEG2E16_V_MF2_MASK + {4, OperandInfo497}, // Inst #8559 = PseudoVSSEG2E16_V_MF4 + {5, OperandInfo849}, // Inst #8560 = PseudoVSSEG2E16_V_MF4_MASK + {4, OperandInfo497}, // Inst #8561 = PseudoVSSEG2E32_V_M1 + {5, OperandInfo849}, // Inst #8562 = PseudoVSSEG2E32_V_M1_MASK + {4, OperandInfo499}, // Inst #8563 = PseudoVSSEG2E32_V_M2 + {5, OperandInfo850}, // Inst #8564 = PseudoVSSEG2E32_V_M2_MASK + {4, OperandInfo501}, // Inst #8565 = PseudoVSSEG2E32_V_M4 + {5, OperandInfo851}, // Inst #8566 = PseudoVSSEG2E32_V_M4_MASK + {4, OperandInfo497}, // Inst #8567 = PseudoVSSEG2E32_V_MF2 + {5, OperandInfo849}, // Inst #8568 = PseudoVSSEG2E32_V_MF2_MASK + {4, OperandInfo497}, // Inst #8569 = PseudoVSSEG2E64_V_M1 + {5, OperandInfo849}, // Inst #8570 = PseudoVSSEG2E64_V_M1_MASK + {4, OperandInfo499}, // Inst #8571 = PseudoVSSEG2E64_V_M2 + {5, OperandInfo850}, // Inst #8572 = PseudoVSSEG2E64_V_M2_MASK + {4, OperandInfo501}, // Inst #8573 = PseudoVSSEG2E64_V_M4 + {5, OperandInfo851}, // Inst #8574 = PseudoVSSEG2E64_V_M4_MASK + {4, OperandInfo497}, // Inst #8575 = PseudoVSSEG2E8_V_M1 + {5, OperandInfo849}, // Inst #8576 = PseudoVSSEG2E8_V_M1_MASK + {4, OperandInfo499}, // Inst #8577 = PseudoVSSEG2E8_V_M2 + {5, OperandInfo850}, // Inst #8578 = PseudoVSSEG2E8_V_M2_MASK + {4, OperandInfo501}, // Inst #8579 = PseudoVSSEG2E8_V_M4 + {5, OperandInfo851}, // Inst #8580 = PseudoVSSEG2E8_V_M4_MASK + {4, OperandInfo497}, // Inst #8581 = PseudoVSSEG2E8_V_MF2 + {5, OperandInfo849}, // Inst #8582 = PseudoVSSEG2E8_V_MF2_MASK + {4, OperandInfo497}, // Inst #8583 = PseudoVSSEG2E8_V_MF4 + {5, OperandInfo849}, // Inst #8584 = PseudoVSSEG2E8_V_MF4_MASK + {4, OperandInfo497}, // Inst #8585 = PseudoVSSEG2E8_V_MF8 + {5, OperandInfo849}, // Inst #8586 = PseudoVSSEG2E8_V_MF8_MASK + {4, OperandInfo503}, // Inst #8587 = PseudoVSSEG3E16_V_M1 + {5, OperandInfo852}, // Inst #8588 = PseudoVSSEG3E16_V_M1_MASK + {4, OperandInfo505}, // Inst #8589 = PseudoVSSEG3E16_V_M2 + {5, OperandInfo853}, // Inst #8590 = PseudoVSSEG3E16_V_M2_MASK + {4, OperandInfo503}, // Inst #8591 = PseudoVSSEG3E16_V_MF2 + {5, OperandInfo852}, // Inst #8592 = PseudoVSSEG3E16_V_MF2_MASK + {4, OperandInfo503}, // Inst #8593 = PseudoVSSEG3E16_V_MF4 + {5, OperandInfo852}, // Inst #8594 = PseudoVSSEG3E16_V_MF4_MASK + {4, OperandInfo503}, // Inst #8595 = PseudoVSSEG3E32_V_M1 + {5, OperandInfo852}, // Inst #8596 = PseudoVSSEG3E32_V_M1_MASK + {4, OperandInfo505}, // Inst #8597 = PseudoVSSEG3E32_V_M2 + {5, OperandInfo853}, // Inst #8598 = PseudoVSSEG3E32_V_M2_MASK + {4, OperandInfo503}, // Inst #8599 = PseudoVSSEG3E32_V_MF2 + {5, OperandInfo852}, // Inst #8600 = PseudoVSSEG3E32_V_MF2_MASK + {4, OperandInfo503}, // Inst #8601 = PseudoVSSEG3E64_V_M1 + {5, OperandInfo852}, // Inst #8602 = PseudoVSSEG3E64_V_M1_MASK + {4, OperandInfo505}, // Inst #8603 = PseudoVSSEG3E64_V_M2 + {5, OperandInfo853}, // Inst #8604 = PseudoVSSEG3E64_V_M2_MASK + {4, OperandInfo503}, // Inst #8605 = PseudoVSSEG3E8_V_M1 + {5, OperandInfo852}, // Inst #8606 = PseudoVSSEG3E8_V_M1_MASK + {4, OperandInfo505}, // Inst #8607 = PseudoVSSEG3E8_V_M2 + {5, OperandInfo853}, // Inst #8608 = PseudoVSSEG3E8_V_M2_MASK + {4, OperandInfo503}, // Inst #8609 = PseudoVSSEG3E8_V_MF2 + {5, OperandInfo852}, // Inst #8610 = PseudoVSSEG3E8_V_MF2_MASK + {4, OperandInfo503}, // Inst #8611 = PseudoVSSEG3E8_V_MF4 + {5, OperandInfo852}, // Inst #8612 = PseudoVSSEG3E8_V_MF4_MASK + {4, OperandInfo503}, // Inst #8613 = PseudoVSSEG3E8_V_MF8 + {5, OperandInfo852}, // Inst #8614 = PseudoVSSEG3E8_V_MF8_MASK + {4, OperandInfo507}, // Inst #8615 = PseudoVSSEG4E16_V_M1 + {5, OperandInfo854}, // Inst #8616 = PseudoVSSEG4E16_V_M1_MASK + {4, OperandInfo509}, // Inst #8617 = PseudoVSSEG4E16_V_M2 + {5, OperandInfo855}, // Inst #8618 = PseudoVSSEG4E16_V_M2_MASK + {4, OperandInfo507}, // Inst #8619 = PseudoVSSEG4E16_V_MF2 + {5, OperandInfo854}, // Inst #8620 = PseudoVSSEG4E16_V_MF2_MASK + {4, OperandInfo507}, // Inst #8621 = PseudoVSSEG4E16_V_MF4 + {5, OperandInfo854}, // Inst #8622 = PseudoVSSEG4E16_V_MF4_MASK + {4, OperandInfo507}, // Inst #8623 = PseudoVSSEG4E32_V_M1 + {5, OperandInfo854}, // Inst #8624 = PseudoVSSEG4E32_V_M1_MASK + {4, OperandInfo509}, // Inst #8625 = PseudoVSSEG4E32_V_M2 + {5, OperandInfo855}, // Inst #8626 = PseudoVSSEG4E32_V_M2_MASK + {4, OperandInfo507}, // Inst #8627 = PseudoVSSEG4E32_V_MF2 + {5, OperandInfo854}, // Inst #8628 = PseudoVSSEG4E32_V_MF2_MASK + {4, OperandInfo507}, // Inst #8629 = PseudoVSSEG4E64_V_M1 + {5, OperandInfo854}, // Inst #8630 = PseudoVSSEG4E64_V_M1_MASK + {4, OperandInfo509}, // Inst #8631 = PseudoVSSEG4E64_V_M2 + {5, OperandInfo855}, // Inst #8632 = PseudoVSSEG4E64_V_M2_MASK + {4, OperandInfo507}, // Inst #8633 = PseudoVSSEG4E8_V_M1 + {5, OperandInfo854}, // Inst #8634 = PseudoVSSEG4E8_V_M1_MASK + {4, OperandInfo509}, // Inst #8635 = PseudoVSSEG4E8_V_M2 + {5, OperandInfo855}, // Inst #8636 = PseudoVSSEG4E8_V_M2_MASK + {4, OperandInfo507}, // Inst #8637 = PseudoVSSEG4E8_V_MF2 + {5, OperandInfo854}, // Inst #8638 = PseudoVSSEG4E8_V_MF2_MASK + {4, OperandInfo507}, // Inst #8639 = PseudoVSSEG4E8_V_MF4 + {5, OperandInfo854}, // Inst #8640 = PseudoVSSEG4E8_V_MF4_MASK + {4, OperandInfo507}, // Inst #8641 = PseudoVSSEG4E8_V_MF8 + {5, OperandInfo854}, // Inst #8642 = PseudoVSSEG4E8_V_MF8_MASK + {4, OperandInfo511}, // Inst #8643 = PseudoVSSEG5E16_V_M1 + {5, OperandInfo856}, // Inst #8644 = PseudoVSSEG5E16_V_M1_MASK + {4, OperandInfo511}, // Inst #8645 = PseudoVSSEG5E16_V_MF2 + {5, OperandInfo856}, // Inst #8646 = PseudoVSSEG5E16_V_MF2_MASK + {4, OperandInfo511}, // Inst #8647 = PseudoVSSEG5E16_V_MF4 + {5, OperandInfo856}, // Inst #8648 = PseudoVSSEG5E16_V_MF4_MASK + {4, OperandInfo511}, // Inst #8649 = PseudoVSSEG5E32_V_M1 + {5, OperandInfo856}, // Inst #8650 = PseudoVSSEG5E32_V_M1_MASK + {4, OperandInfo511}, // Inst #8651 = PseudoVSSEG5E32_V_MF2 + {5, OperandInfo856}, // Inst #8652 = PseudoVSSEG5E32_V_MF2_MASK + {4, OperandInfo511}, // Inst #8653 = PseudoVSSEG5E64_V_M1 + {5, OperandInfo856}, // Inst #8654 = PseudoVSSEG5E64_V_M1_MASK + {4, OperandInfo511}, // Inst #8655 = PseudoVSSEG5E8_V_M1 + {5, OperandInfo856}, // Inst #8656 = PseudoVSSEG5E8_V_M1_MASK + {4, OperandInfo511}, // Inst #8657 = PseudoVSSEG5E8_V_MF2 + {5, OperandInfo856}, // Inst #8658 = PseudoVSSEG5E8_V_MF2_MASK + {4, OperandInfo511}, // Inst #8659 = PseudoVSSEG5E8_V_MF4 + {5, OperandInfo856}, // Inst #8660 = PseudoVSSEG5E8_V_MF4_MASK + {4, OperandInfo511}, // Inst #8661 = PseudoVSSEG5E8_V_MF8 + {5, OperandInfo856}, // Inst #8662 = PseudoVSSEG5E8_V_MF8_MASK + {4, OperandInfo513}, // Inst #8663 = PseudoVSSEG6E16_V_M1 + {5, OperandInfo857}, // Inst #8664 = PseudoVSSEG6E16_V_M1_MASK + {4, OperandInfo513}, // Inst #8665 = PseudoVSSEG6E16_V_MF2 + {5, OperandInfo857}, // Inst #8666 = PseudoVSSEG6E16_V_MF2_MASK + {4, OperandInfo513}, // Inst #8667 = PseudoVSSEG6E16_V_MF4 + {5, OperandInfo857}, // Inst #8668 = PseudoVSSEG6E16_V_MF4_MASK + {4, OperandInfo513}, // Inst #8669 = PseudoVSSEG6E32_V_M1 + {5, OperandInfo857}, // Inst #8670 = PseudoVSSEG6E32_V_M1_MASK + {4, OperandInfo513}, // Inst #8671 = PseudoVSSEG6E32_V_MF2 + {5, OperandInfo857}, // Inst #8672 = PseudoVSSEG6E32_V_MF2_MASK + {4, OperandInfo513}, // Inst #8673 = PseudoVSSEG6E64_V_M1 + {5, OperandInfo857}, // Inst #8674 = PseudoVSSEG6E64_V_M1_MASK + {4, OperandInfo513}, // Inst #8675 = PseudoVSSEG6E8_V_M1 + {5, OperandInfo857}, // Inst #8676 = PseudoVSSEG6E8_V_M1_MASK + {4, OperandInfo513}, // Inst #8677 = PseudoVSSEG6E8_V_MF2 + {5, OperandInfo857}, // Inst #8678 = PseudoVSSEG6E8_V_MF2_MASK + {4, OperandInfo513}, // Inst #8679 = PseudoVSSEG6E8_V_MF4 + {5, OperandInfo857}, // Inst #8680 = PseudoVSSEG6E8_V_MF4_MASK + {4, OperandInfo513}, // Inst #8681 = PseudoVSSEG6E8_V_MF8 + {5, OperandInfo857}, // Inst #8682 = PseudoVSSEG6E8_V_MF8_MASK + {4, OperandInfo515}, // Inst #8683 = PseudoVSSEG7E16_V_M1 + {5, OperandInfo858}, // Inst #8684 = PseudoVSSEG7E16_V_M1_MASK + {4, OperandInfo515}, // Inst #8685 = PseudoVSSEG7E16_V_MF2 + {5, OperandInfo858}, // Inst #8686 = PseudoVSSEG7E16_V_MF2_MASK + {4, OperandInfo515}, // Inst #8687 = PseudoVSSEG7E16_V_MF4 + {5, OperandInfo858}, // Inst #8688 = PseudoVSSEG7E16_V_MF4_MASK + {4, OperandInfo515}, // Inst #8689 = PseudoVSSEG7E32_V_M1 + {5, OperandInfo858}, // Inst #8690 = PseudoVSSEG7E32_V_M1_MASK + {4, OperandInfo515}, // Inst #8691 = PseudoVSSEG7E32_V_MF2 + {5, OperandInfo858}, // Inst #8692 = PseudoVSSEG7E32_V_MF2_MASK + {4, OperandInfo515}, // Inst #8693 = PseudoVSSEG7E64_V_M1 + {5, OperandInfo858}, // Inst #8694 = PseudoVSSEG7E64_V_M1_MASK + {4, OperandInfo515}, // Inst #8695 = PseudoVSSEG7E8_V_M1 + {5, OperandInfo858}, // Inst #8696 = PseudoVSSEG7E8_V_M1_MASK + {4, OperandInfo515}, // Inst #8697 = PseudoVSSEG7E8_V_MF2 + {5, OperandInfo858}, // Inst #8698 = PseudoVSSEG7E8_V_MF2_MASK + {4, OperandInfo515}, // Inst #8699 = PseudoVSSEG7E8_V_MF4 + {5, OperandInfo858}, // Inst #8700 = PseudoVSSEG7E8_V_MF4_MASK + {4, OperandInfo515}, // Inst #8701 = PseudoVSSEG7E8_V_MF8 + {5, OperandInfo858}, // Inst #8702 = PseudoVSSEG7E8_V_MF8_MASK + {4, OperandInfo517}, // Inst #8703 = PseudoVSSEG8E16_V_M1 + {5, OperandInfo859}, // Inst #8704 = PseudoVSSEG8E16_V_M1_MASK + {4, OperandInfo517}, // Inst #8705 = PseudoVSSEG8E16_V_MF2 + {5, OperandInfo859}, // Inst #8706 = PseudoVSSEG8E16_V_MF2_MASK + {4, OperandInfo517}, // Inst #8707 = PseudoVSSEG8E16_V_MF4 + {5, OperandInfo859}, // Inst #8708 = PseudoVSSEG8E16_V_MF4_MASK + {4, OperandInfo517}, // Inst #8709 = PseudoVSSEG8E32_V_M1 + {5, OperandInfo859}, // Inst #8710 = PseudoVSSEG8E32_V_M1_MASK + {4, OperandInfo517}, // Inst #8711 = PseudoVSSEG8E32_V_MF2 + {5, OperandInfo859}, // Inst #8712 = PseudoVSSEG8E32_V_MF2_MASK + {4, OperandInfo517}, // Inst #8713 = PseudoVSSEG8E64_V_M1 + {5, OperandInfo859}, // Inst #8714 = PseudoVSSEG8E64_V_M1_MASK + {4, OperandInfo517}, // Inst #8715 = PseudoVSSEG8E8_V_M1 + {5, OperandInfo859}, // Inst #8716 = PseudoVSSEG8E8_V_M1_MASK + {4, OperandInfo517}, // Inst #8717 = PseudoVSSEG8E8_V_MF2 + {5, OperandInfo859}, // Inst #8718 = PseudoVSSEG8E8_V_MF2_MASK + {4, OperandInfo517}, // Inst #8719 = PseudoVSSEG8E8_V_MF4 + {5, OperandInfo859}, // Inst #8720 = PseudoVSSEG8E8_V_MF4_MASK + {4, OperandInfo517}, // Inst #8721 = PseudoVSSEG8E8_V_MF8 + {5, OperandInfo859}, // Inst #8722 = PseudoVSSEG8E8_V_MF8_MASK + {5, OperandInfo90}, // Inst #8723 = PseudoVSSRA_VI_M1 + {8, OperandInfo91}, // Inst #8724 = PseudoVSSRA_VI_M1_MASK + {5, OperandInfo92}, // Inst #8725 = PseudoVSSRA_VI_M2 + {8, OperandInfo93}, // Inst #8726 = PseudoVSSRA_VI_M2_MASK + {5, OperandInfo94}, // Inst #8727 = PseudoVSSRA_VI_M4 + {8, OperandInfo95}, // Inst #8728 = PseudoVSSRA_VI_M4_MASK + {5, OperandInfo96}, // Inst #8729 = PseudoVSSRA_VI_M8 + {8, OperandInfo97}, // Inst #8730 = PseudoVSSRA_VI_M8_MASK + {5, OperandInfo90}, // Inst #8731 = PseudoVSSRA_VI_MF2 + {8, OperandInfo91}, // Inst #8732 = PseudoVSSRA_VI_MF2_MASK + {5, OperandInfo90}, // Inst #8733 = PseudoVSSRA_VI_MF4 + {8, OperandInfo91}, // Inst #8734 = PseudoVSSRA_VI_MF4_MASK + {5, OperandInfo90}, // Inst #8735 = PseudoVSSRA_VI_MF8 + {8, OperandInfo91}, // Inst #8736 = PseudoVSSRA_VI_MF8_MASK + {5, OperandInfo62}, // Inst #8737 = PseudoVSSRA_VV_M1 + {8, OperandInfo63}, // Inst #8738 = PseudoVSSRA_VV_M1_MASK + {5, OperandInfo64}, // Inst #8739 = PseudoVSSRA_VV_M2 + {8, OperandInfo65}, // Inst #8740 = PseudoVSSRA_VV_M2_MASK + {5, OperandInfo66}, // Inst #8741 = PseudoVSSRA_VV_M4 + {8, OperandInfo67}, // Inst #8742 = PseudoVSSRA_VV_M4_MASK + {5, OperandInfo68}, // Inst #8743 = PseudoVSSRA_VV_M8 + {8, OperandInfo69}, // Inst #8744 = PseudoVSSRA_VV_M8_MASK + {5, OperandInfo62}, // Inst #8745 = PseudoVSSRA_VV_MF2 + {8, OperandInfo63}, // Inst #8746 = PseudoVSSRA_VV_MF2_MASK + {5, OperandInfo62}, // Inst #8747 = PseudoVSSRA_VV_MF4 + {8, OperandInfo63}, // Inst #8748 = PseudoVSSRA_VV_MF4_MASK + {5, OperandInfo62}, // Inst #8749 = PseudoVSSRA_VV_MF8 + {8, OperandInfo63}, // Inst #8750 = PseudoVSSRA_VV_MF8_MASK + {5, OperandInfo70}, // Inst #8751 = PseudoVSSRA_VX_M1 + {8, OperandInfo71}, // Inst #8752 = PseudoVSSRA_VX_M1_MASK + {5, OperandInfo72}, // Inst #8753 = PseudoVSSRA_VX_M2 + {8, OperandInfo73}, // Inst #8754 = PseudoVSSRA_VX_M2_MASK + {5, OperandInfo74}, // Inst #8755 = PseudoVSSRA_VX_M4 + {8, OperandInfo75}, // Inst #8756 = PseudoVSSRA_VX_M4_MASK + {5, OperandInfo76}, // Inst #8757 = PseudoVSSRA_VX_M8 + {8, OperandInfo77}, // Inst #8758 = PseudoVSSRA_VX_M8_MASK + {5, OperandInfo70}, // Inst #8759 = PseudoVSSRA_VX_MF2 + {8, OperandInfo71}, // Inst #8760 = PseudoVSSRA_VX_MF2_MASK + {5, OperandInfo70}, // Inst #8761 = PseudoVSSRA_VX_MF4 + {8, OperandInfo71}, // Inst #8762 = PseudoVSSRA_VX_MF4_MASK + {5, OperandInfo70}, // Inst #8763 = PseudoVSSRA_VX_MF8 + {8, OperandInfo71}, // Inst #8764 = PseudoVSSRA_VX_MF8_MASK + {5, OperandInfo90}, // Inst #8765 = PseudoVSSRL_VI_M1 + {8, OperandInfo91}, // Inst #8766 = PseudoVSSRL_VI_M1_MASK + {5, OperandInfo92}, // Inst #8767 = PseudoVSSRL_VI_M2 + {8, OperandInfo93}, // Inst #8768 = PseudoVSSRL_VI_M2_MASK + {5, OperandInfo94}, // Inst #8769 = PseudoVSSRL_VI_M4 + {8, OperandInfo95}, // Inst #8770 = PseudoVSSRL_VI_M4_MASK + {5, OperandInfo96}, // Inst #8771 = PseudoVSSRL_VI_M8 + {8, OperandInfo97}, // Inst #8772 = PseudoVSSRL_VI_M8_MASK + {5, OperandInfo90}, // Inst #8773 = PseudoVSSRL_VI_MF2 + {8, OperandInfo91}, // Inst #8774 = PseudoVSSRL_VI_MF2_MASK + {5, OperandInfo90}, // Inst #8775 = PseudoVSSRL_VI_MF4 + {8, OperandInfo91}, // Inst #8776 = PseudoVSSRL_VI_MF4_MASK + {5, OperandInfo90}, // Inst #8777 = PseudoVSSRL_VI_MF8 + {8, OperandInfo91}, // Inst #8778 = PseudoVSSRL_VI_MF8_MASK + {5, OperandInfo62}, // Inst #8779 = PseudoVSSRL_VV_M1 + {8, OperandInfo63}, // Inst #8780 = PseudoVSSRL_VV_M1_MASK + {5, OperandInfo64}, // Inst #8781 = PseudoVSSRL_VV_M2 + {8, OperandInfo65}, // Inst #8782 = PseudoVSSRL_VV_M2_MASK + {5, OperandInfo66}, // Inst #8783 = PseudoVSSRL_VV_M4 + {8, OperandInfo67}, // Inst #8784 = PseudoVSSRL_VV_M4_MASK + {5, OperandInfo68}, // Inst #8785 = PseudoVSSRL_VV_M8 + {8, OperandInfo69}, // Inst #8786 = PseudoVSSRL_VV_M8_MASK + {5, OperandInfo62}, // Inst #8787 = PseudoVSSRL_VV_MF2 + {8, OperandInfo63}, // Inst #8788 = PseudoVSSRL_VV_MF2_MASK + {5, OperandInfo62}, // Inst #8789 = PseudoVSSRL_VV_MF4 + {8, OperandInfo63}, // Inst #8790 = PseudoVSSRL_VV_MF4_MASK + {5, OperandInfo62}, // Inst #8791 = PseudoVSSRL_VV_MF8 + {8, OperandInfo63}, // Inst #8792 = PseudoVSSRL_VV_MF8_MASK + {5, OperandInfo70}, // Inst #8793 = PseudoVSSRL_VX_M1 + {8, OperandInfo71}, // Inst #8794 = PseudoVSSRL_VX_M1_MASK + {5, OperandInfo72}, // Inst #8795 = PseudoVSSRL_VX_M2 + {8, OperandInfo73}, // Inst #8796 = PseudoVSSRL_VX_M2_MASK + {5, OperandInfo74}, // Inst #8797 = PseudoVSSRL_VX_M4 + {8, OperandInfo75}, // Inst #8798 = PseudoVSSRL_VX_M4_MASK + {5, OperandInfo76}, // Inst #8799 = PseudoVSSRL_VX_M8 + {8, OperandInfo77}, // Inst #8800 = PseudoVSSRL_VX_M8_MASK + {5, OperandInfo70}, // Inst #8801 = PseudoVSSRL_VX_MF2 + {8, OperandInfo71}, // Inst #8802 = PseudoVSSRL_VX_MF2_MASK + {5, OperandInfo70}, // Inst #8803 = PseudoVSSRL_VX_MF4 + {8, OperandInfo71}, // Inst #8804 = PseudoVSSRL_VX_MF4_MASK + {5, OperandInfo70}, // Inst #8805 = PseudoVSSRL_VX_MF8 + {8, OperandInfo71}, // Inst #8806 = PseudoVSSRL_VX_MF8_MASK + {5, OperandInfo519}, // Inst #8807 = PseudoVSSSEG2E16_V_M1 + {6, OperandInfo860}, // Inst #8808 = PseudoVSSSEG2E16_V_M1_MASK + {5, OperandInfo521}, // Inst #8809 = PseudoVSSSEG2E16_V_M2 + {6, OperandInfo861}, // Inst #8810 = PseudoVSSSEG2E16_V_M2_MASK + {5, OperandInfo523}, // Inst #8811 = PseudoVSSSEG2E16_V_M4 + {6, OperandInfo862}, // Inst #8812 = PseudoVSSSEG2E16_V_M4_MASK + {5, OperandInfo519}, // Inst #8813 = PseudoVSSSEG2E16_V_MF2 + {6, OperandInfo860}, // Inst #8814 = PseudoVSSSEG2E16_V_MF2_MASK + {5, OperandInfo519}, // Inst #8815 = PseudoVSSSEG2E16_V_MF4 + {6, OperandInfo860}, // Inst #8816 = PseudoVSSSEG2E16_V_MF4_MASK + {5, OperandInfo519}, // Inst #8817 = PseudoVSSSEG2E32_V_M1 + {6, OperandInfo860}, // Inst #8818 = PseudoVSSSEG2E32_V_M1_MASK + {5, OperandInfo521}, // Inst #8819 = PseudoVSSSEG2E32_V_M2 + {6, OperandInfo861}, // Inst #8820 = PseudoVSSSEG2E32_V_M2_MASK + {5, OperandInfo523}, // Inst #8821 = PseudoVSSSEG2E32_V_M4 + {6, OperandInfo862}, // Inst #8822 = PseudoVSSSEG2E32_V_M4_MASK + {5, OperandInfo519}, // Inst #8823 = PseudoVSSSEG2E32_V_MF2 + {6, OperandInfo860}, // Inst #8824 = PseudoVSSSEG2E32_V_MF2_MASK + {5, OperandInfo519}, // Inst #8825 = PseudoVSSSEG2E64_V_M1 + {6, OperandInfo860}, // Inst #8826 = PseudoVSSSEG2E64_V_M1_MASK + {5, OperandInfo521}, // Inst #8827 = PseudoVSSSEG2E64_V_M2 + {6, OperandInfo861}, // Inst #8828 = PseudoVSSSEG2E64_V_M2_MASK + {5, OperandInfo523}, // Inst #8829 = PseudoVSSSEG2E64_V_M4 + {6, OperandInfo862}, // Inst #8830 = PseudoVSSSEG2E64_V_M4_MASK + {5, OperandInfo519}, // Inst #8831 = PseudoVSSSEG2E8_V_M1 + {6, OperandInfo860}, // Inst #8832 = PseudoVSSSEG2E8_V_M1_MASK + {5, OperandInfo521}, // Inst #8833 = PseudoVSSSEG2E8_V_M2 + {6, OperandInfo861}, // Inst #8834 = PseudoVSSSEG2E8_V_M2_MASK + {5, OperandInfo523}, // Inst #8835 = PseudoVSSSEG2E8_V_M4 + {6, OperandInfo862}, // Inst #8836 = PseudoVSSSEG2E8_V_M4_MASK + {5, OperandInfo519}, // Inst #8837 = PseudoVSSSEG2E8_V_MF2 + {6, OperandInfo860}, // Inst #8838 = PseudoVSSSEG2E8_V_MF2_MASK + {5, OperandInfo519}, // Inst #8839 = PseudoVSSSEG2E8_V_MF4 + {6, OperandInfo860}, // Inst #8840 = PseudoVSSSEG2E8_V_MF4_MASK + {5, OperandInfo519}, // Inst #8841 = PseudoVSSSEG2E8_V_MF8 + {6, OperandInfo860}, // Inst #8842 = PseudoVSSSEG2E8_V_MF8_MASK + {5, OperandInfo525}, // Inst #8843 = PseudoVSSSEG3E16_V_M1 + {6, OperandInfo863}, // Inst #8844 = PseudoVSSSEG3E16_V_M1_MASK + {5, OperandInfo527}, // Inst #8845 = PseudoVSSSEG3E16_V_M2 + {6, OperandInfo864}, // Inst #8846 = PseudoVSSSEG3E16_V_M2_MASK + {5, OperandInfo525}, // Inst #8847 = PseudoVSSSEG3E16_V_MF2 + {6, OperandInfo863}, // Inst #8848 = PseudoVSSSEG3E16_V_MF2_MASK + {5, OperandInfo525}, // Inst #8849 = PseudoVSSSEG3E16_V_MF4 + {6, OperandInfo863}, // Inst #8850 = PseudoVSSSEG3E16_V_MF4_MASK + {5, OperandInfo525}, // Inst #8851 = PseudoVSSSEG3E32_V_M1 + {6, OperandInfo863}, // Inst #8852 = PseudoVSSSEG3E32_V_M1_MASK + {5, OperandInfo527}, // Inst #8853 = PseudoVSSSEG3E32_V_M2 + {6, OperandInfo864}, // Inst #8854 = PseudoVSSSEG3E32_V_M2_MASK + {5, OperandInfo525}, // Inst #8855 = PseudoVSSSEG3E32_V_MF2 + {6, OperandInfo863}, // Inst #8856 = PseudoVSSSEG3E32_V_MF2_MASK + {5, OperandInfo525}, // Inst #8857 = PseudoVSSSEG3E64_V_M1 + {6, OperandInfo863}, // Inst #8858 = PseudoVSSSEG3E64_V_M1_MASK + {5, OperandInfo527}, // Inst #8859 = PseudoVSSSEG3E64_V_M2 + {6, OperandInfo864}, // Inst #8860 = PseudoVSSSEG3E64_V_M2_MASK + {5, OperandInfo525}, // Inst #8861 = PseudoVSSSEG3E8_V_M1 + {6, OperandInfo863}, // Inst #8862 = PseudoVSSSEG3E8_V_M1_MASK + {5, OperandInfo527}, // Inst #8863 = PseudoVSSSEG3E8_V_M2 + {6, OperandInfo864}, // Inst #8864 = PseudoVSSSEG3E8_V_M2_MASK + {5, OperandInfo525}, // Inst #8865 = PseudoVSSSEG3E8_V_MF2 + {6, OperandInfo863}, // Inst #8866 = PseudoVSSSEG3E8_V_MF2_MASK + {5, OperandInfo525}, // Inst #8867 = PseudoVSSSEG3E8_V_MF4 + {6, OperandInfo863}, // Inst #8868 = PseudoVSSSEG3E8_V_MF4_MASK + {5, OperandInfo525}, // Inst #8869 = PseudoVSSSEG3E8_V_MF8 + {6, OperandInfo863}, // Inst #8870 = PseudoVSSSEG3E8_V_MF8_MASK + {5, OperandInfo529}, // Inst #8871 = PseudoVSSSEG4E16_V_M1 + {6, OperandInfo865}, // Inst #8872 = PseudoVSSSEG4E16_V_M1_MASK + {5, OperandInfo531}, // Inst #8873 = PseudoVSSSEG4E16_V_M2 + {6, OperandInfo866}, // Inst #8874 = PseudoVSSSEG4E16_V_M2_MASK + {5, OperandInfo529}, // Inst #8875 = PseudoVSSSEG4E16_V_MF2 + {6, OperandInfo865}, // Inst #8876 = PseudoVSSSEG4E16_V_MF2_MASK + {5, OperandInfo529}, // Inst #8877 = PseudoVSSSEG4E16_V_MF4 + {6, OperandInfo865}, // Inst #8878 = PseudoVSSSEG4E16_V_MF4_MASK + {5, OperandInfo529}, // Inst #8879 = PseudoVSSSEG4E32_V_M1 + {6, OperandInfo865}, // Inst #8880 = PseudoVSSSEG4E32_V_M1_MASK + {5, OperandInfo531}, // Inst #8881 = PseudoVSSSEG4E32_V_M2 + {6, OperandInfo866}, // Inst #8882 = PseudoVSSSEG4E32_V_M2_MASK + {5, OperandInfo529}, // Inst #8883 = PseudoVSSSEG4E32_V_MF2 + {6, OperandInfo865}, // Inst #8884 = PseudoVSSSEG4E32_V_MF2_MASK + {5, OperandInfo529}, // Inst #8885 = PseudoVSSSEG4E64_V_M1 + {6, OperandInfo865}, // Inst #8886 = PseudoVSSSEG4E64_V_M1_MASK + {5, OperandInfo531}, // Inst #8887 = PseudoVSSSEG4E64_V_M2 + {6, OperandInfo866}, // Inst #8888 = PseudoVSSSEG4E64_V_M2_MASK + {5, OperandInfo529}, // Inst #8889 = PseudoVSSSEG4E8_V_M1 + {6, OperandInfo865}, // Inst #8890 = PseudoVSSSEG4E8_V_M1_MASK + {5, OperandInfo531}, // Inst #8891 = PseudoVSSSEG4E8_V_M2 + {6, OperandInfo866}, // Inst #8892 = PseudoVSSSEG4E8_V_M2_MASK + {5, OperandInfo529}, // Inst #8893 = PseudoVSSSEG4E8_V_MF2 + {6, OperandInfo865}, // Inst #8894 = PseudoVSSSEG4E8_V_MF2_MASK + {5, OperandInfo529}, // Inst #8895 = PseudoVSSSEG4E8_V_MF4 + {6, OperandInfo865}, // Inst #8896 = PseudoVSSSEG4E8_V_MF4_MASK + {5, OperandInfo529}, // Inst #8897 = PseudoVSSSEG4E8_V_MF8 + {6, OperandInfo865}, // Inst #8898 = PseudoVSSSEG4E8_V_MF8_MASK + {5, OperandInfo533}, // Inst #8899 = PseudoVSSSEG5E16_V_M1 + {6, OperandInfo867}, // Inst #8900 = PseudoVSSSEG5E16_V_M1_MASK + {5, OperandInfo533}, // Inst #8901 = PseudoVSSSEG5E16_V_MF2 + {6, OperandInfo867}, // Inst #8902 = PseudoVSSSEG5E16_V_MF2_MASK + {5, OperandInfo533}, // Inst #8903 = PseudoVSSSEG5E16_V_MF4 + {6, OperandInfo867}, // Inst #8904 = PseudoVSSSEG5E16_V_MF4_MASK + {5, OperandInfo533}, // Inst #8905 = PseudoVSSSEG5E32_V_M1 + {6, OperandInfo867}, // Inst #8906 = PseudoVSSSEG5E32_V_M1_MASK + {5, OperandInfo533}, // Inst #8907 = PseudoVSSSEG5E32_V_MF2 + {6, OperandInfo867}, // Inst #8908 = PseudoVSSSEG5E32_V_MF2_MASK + {5, OperandInfo533}, // Inst #8909 = PseudoVSSSEG5E64_V_M1 + {6, OperandInfo867}, // Inst #8910 = PseudoVSSSEG5E64_V_M1_MASK + {5, OperandInfo533}, // Inst #8911 = PseudoVSSSEG5E8_V_M1 + {6, OperandInfo867}, // Inst #8912 = PseudoVSSSEG5E8_V_M1_MASK + {5, OperandInfo533}, // Inst #8913 = PseudoVSSSEG5E8_V_MF2 + {6, OperandInfo867}, // Inst #8914 = PseudoVSSSEG5E8_V_MF2_MASK + {5, OperandInfo533}, // Inst #8915 = PseudoVSSSEG5E8_V_MF4 + {6, OperandInfo867}, // Inst #8916 = PseudoVSSSEG5E8_V_MF4_MASK + {5, OperandInfo533}, // Inst #8917 = PseudoVSSSEG5E8_V_MF8 + {6, OperandInfo867}, // Inst #8918 = PseudoVSSSEG5E8_V_MF8_MASK + {5, OperandInfo535}, // Inst #8919 = PseudoVSSSEG6E16_V_M1 + {6, OperandInfo868}, // Inst #8920 = PseudoVSSSEG6E16_V_M1_MASK + {5, OperandInfo535}, // Inst #8921 = PseudoVSSSEG6E16_V_MF2 + {6, OperandInfo868}, // Inst #8922 = PseudoVSSSEG6E16_V_MF2_MASK + {5, OperandInfo535}, // Inst #8923 = PseudoVSSSEG6E16_V_MF4 + {6, OperandInfo868}, // Inst #8924 = PseudoVSSSEG6E16_V_MF4_MASK + {5, OperandInfo535}, // Inst #8925 = PseudoVSSSEG6E32_V_M1 + {6, OperandInfo868}, // Inst #8926 = PseudoVSSSEG6E32_V_M1_MASK + {5, OperandInfo535}, // Inst #8927 = PseudoVSSSEG6E32_V_MF2 + {6, OperandInfo868}, // Inst #8928 = PseudoVSSSEG6E32_V_MF2_MASK + {5, OperandInfo535}, // Inst #8929 = PseudoVSSSEG6E64_V_M1 + {6, OperandInfo868}, // Inst #8930 = PseudoVSSSEG6E64_V_M1_MASK + {5, OperandInfo535}, // Inst #8931 = PseudoVSSSEG6E8_V_M1 + {6, OperandInfo868}, // Inst #8932 = PseudoVSSSEG6E8_V_M1_MASK + {5, OperandInfo535}, // Inst #8933 = PseudoVSSSEG6E8_V_MF2 + {6, OperandInfo868}, // Inst #8934 = PseudoVSSSEG6E8_V_MF2_MASK + {5, OperandInfo535}, // Inst #8935 = PseudoVSSSEG6E8_V_MF4 + {6, OperandInfo868}, // Inst #8936 = PseudoVSSSEG6E8_V_MF4_MASK + {5, OperandInfo535}, // Inst #8937 = PseudoVSSSEG6E8_V_MF8 + {6, OperandInfo868}, // Inst #8938 = PseudoVSSSEG6E8_V_MF8_MASK + {5, OperandInfo537}, // Inst #8939 = PseudoVSSSEG7E16_V_M1 + {6, OperandInfo869}, // Inst #8940 = PseudoVSSSEG7E16_V_M1_MASK + {5, OperandInfo537}, // Inst #8941 = PseudoVSSSEG7E16_V_MF2 + {6, OperandInfo869}, // Inst #8942 = PseudoVSSSEG7E16_V_MF2_MASK + {5, OperandInfo537}, // Inst #8943 = PseudoVSSSEG7E16_V_MF4 + {6, OperandInfo869}, // Inst #8944 = PseudoVSSSEG7E16_V_MF4_MASK + {5, OperandInfo537}, // Inst #8945 = PseudoVSSSEG7E32_V_M1 + {6, OperandInfo869}, // Inst #8946 = PseudoVSSSEG7E32_V_M1_MASK + {5, OperandInfo537}, // Inst #8947 = PseudoVSSSEG7E32_V_MF2 + {6, OperandInfo869}, // Inst #8948 = PseudoVSSSEG7E32_V_MF2_MASK + {5, OperandInfo537}, // Inst #8949 = PseudoVSSSEG7E64_V_M1 + {6, OperandInfo869}, // Inst #8950 = PseudoVSSSEG7E64_V_M1_MASK + {5, OperandInfo537}, // Inst #8951 = PseudoVSSSEG7E8_V_M1 + {6, OperandInfo869}, // Inst #8952 = PseudoVSSSEG7E8_V_M1_MASK + {5, OperandInfo537}, // Inst #8953 = PseudoVSSSEG7E8_V_MF2 + {6, OperandInfo869}, // Inst #8954 = PseudoVSSSEG7E8_V_MF2_MASK + {5, OperandInfo537}, // Inst #8955 = PseudoVSSSEG7E8_V_MF4 + {6, OperandInfo869}, // Inst #8956 = PseudoVSSSEG7E8_V_MF4_MASK + {5, OperandInfo537}, // Inst #8957 = PseudoVSSSEG7E8_V_MF8 + {6, OperandInfo869}, // Inst #8958 = PseudoVSSSEG7E8_V_MF8_MASK + {5, OperandInfo539}, // Inst #8959 = PseudoVSSSEG8E16_V_M1 + {6, OperandInfo870}, // Inst #8960 = PseudoVSSSEG8E16_V_M1_MASK + {5, OperandInfo539}, // Inst #8961 = PseudoVSSSEG8E16_V_MF2 + {6, OperandInfo870}, // Inst #8962 = PseudoVSSSEG8E16_V_MF2_MASK + {5, OperandInfo539}, // Inst #8963 = PseudoVSSSEG8E16_V_MF4 + {6, OperandInfo870}, // Inst #8964 = PseudoVSSSEG8E16_V_MF4_MASK + {5, OperandInfo539}, // Inst #8965 = PseudoVSSSEG8E32_V_M1 + {6, OperandInfo870}, // Inst #8966 = PseudoVSSSEG8E32_V_M1_MASK + {5, OperandInfo539}, // Inst #8967 = PseudoVSSSEG8E32_V_MF2 + {6, OperandInfo870}, // Inst #8968 = PseudoVSSSEG8E32_V_MF2_MASK + {5, OperandInfo539}, // Inst #8969 = PseudoVSSSEG8E64_V_M1 + {6, OperandInfo870}, // Inst #8970 = PseudoVSSSEG8E64_V_M1_MASK + {5, OperandInfo539}, // Inst #8971 = PseudoVSSSEG8E8_V_M1 + {6, OperandInfo870}, // Inst #8972 = PseudoVSSSEG8E8_V_M1_MASK + {5, OperandInfo539}, // Inst #8973 = PseudoVSSSEG8E8_V_MF2 + {6, OperandInfo870}, // Inst #8974 = PseudoVSSSEG8E8_V_MF2_MASK + {5, OperandInfo539}, // Inst #8975 = PseudoVSSSEG8E8_V_MF4 + {6, OperandInfo870}, // Inst #8976 = PseudoVSSSEG8E8_V_MF4_MASK + {5, OperandInfo539}, // Inst #8977 = PseudoVSSSEG8E8_V_MF8 + {6, OperandInfo870}, // Inst #8978 = PseudoVSSSEG8E8_V_MF8_MASK + {5, OperandInfo62}, // Inst #8979 = PseudoVSSUBU_VV_M1 + {8, OperandInfo63}, // Inst #8980 = PseudoVSSUBU_VV_M1_MASK + {5, OperandInfo64}, // Inst #8981 = PseudoVSSUBU_VV_M2 + {8, OperandInfo65}, // Inst #8982 = PseudoVSSUBU_VV_M2_MASK + {5, OperandInfo66}, // Inst #8983 = PseudoVSSUBU_VV_M4 + {8, OperandInfo67}, // Inst #8984 = PseudoVSSUBU_VV_M4_MASK + {5, OperandInfo68}, // Inst #8985 = PseudoVSSUBU_VV_M8 + {8, OperandInfo69}, // Inst #8986 = PseudoVSSUBU_VV_M8_MASK + {5, OperandInfo62}, // Inst #8987 = PseudoVSSUBU_VV_MF2 + {8, OperandInfo63}, // Inst #8988 = PseudoVSSUBU_VV_MF2_MASK + {5, OperandInfo62}, // Inst #8989 = PseudoVSSUBU_VV_MF4 + {8, OperandInfo63}, // Inst #8990 = PseudoVSSUBU_VV_MF4_MASK + {5, OperandInfo62}, // Inst #8991 = PseudoVSSUBU_VV_MF8 + {8, OperandInfo63}, // Inst #8992 = PseudoVSSUBU_VV_MF8_MASK + {5, OperandInfo70}, // Inst #8993 = PseudoVSSUBU_VX_M1 + {8, OperandInfo71}, // Inst #8994 = PseudoVSSUBU_VX_M1_MASK + {5, OperandInfo72}, // Inst #8995 = PseudoVSSUBU_VX_M2 + {8, OperandInfo73}, // Inst #8996 = PseudoVSSUBU_VX_M2_MASK + {5, OperandInfo74}, // Inst #8997 = PseudoVSSUBU_VX_M4 + {8, OperandInfo75}, // Inst #8998 = PseudoVSSUBU_VX_M4_MASK + {5, OperandInfo76}, // Inst #8999 = PseudoVSSUBU_VX_M8 + {8, OperandInfo77}, // Inst #9000 = PseudoVSSUBU_VX_M8_MASK + {5, OperandInfo70}, // Inst #9001 = PseudoVSSUBU_VX_MF2 + {8, OperandInfo71}, // Inst #9002 = PseudoVSSUBU_VX_MF2_MASK + {5, OperandInfo70}, // Inst #9003 = PseudoVSSUBU_VX_MF4 + {8, OperandInfo71}, // Inst #9004 = PseudoVSSUBU_VX_MF4_MASK + {5, OperandInfo70}, // Inst #9005 = PseudoVSSUBU_VX_MF8 + {8, OperandInfo71}, // Inst #9006 = PseudoVSSUBU_VX_MF8_MASK + {5, OperandInfo62}, // Inst #9007 = PseudoVSSUB_VV_M1 + {8, OperandInfo63}, // Inst #9008 = PseudoVSSUB_VV_M1_MASK + {5, OperandInfo64}, // Inst #9009 = PseudoVSSUB_VV_M2 + {8, OperandInfo65}, // Inst #9010 = PseudoVSSUB_VV_M2_MASK + {5, OperandInfo66}, // Inst #9011 = PseudoVSSUB_VV_M4 + {8, OperandInfo67}, // Inst #9012 = PseudoVSSUB_VV_M4_MASK + {5, OperandInfo68}, // Inst #9013 = PseudoVSSUB_VV_M8 + {8, OperandInfo69}, // Inst #9014 = PseudoVSSUB_VV_M8_MASK + {5, OperandInfo62}, // Inst #9015 = PseudoVSSUB_VV_MF2 + {8, OperandInfo63}, // Inst #9016 = PseudoVSSUB_VV_MF2_MASK + {5, OperandInfo62}, // Inst #9017 = PseudoVSSUB_VV_MF4 + {8, OperandInfo63}, // Inst #9018 = PseudoVSSUB_VV_MF4_MASK + {5, OperandInfo62}, // Inst #9019 = PseudoVSSUB_VV_MF8 + {8, OperandInfo63}, // Inst #9020 = PseudoVSSUB_VV_MF8_MASK + {5, OperandInfo70}, // Inst #9021 = PseudoVSSUB_VX_M1 + {8, OperandInfo71}, // Inst #9022 = PseudoVSSUB_VX_M1_MASK + {5, OperandInfo72}, // Inst #9023 = PseudoVSSUB_VX_M2 + {8, OperandInfo73}, // Inst #9024 = PseudoVSSUB_VX_M2_MASK + {5, OperandInfo74}, // Inst #9025 = PseudoVSSUB_VX_M4 + {8, OperandInfo75}, // Inst #9026 = PseudoVSSUB_VX_M4_MASK + {5, OperandInfo76}, // Inst #9027 = PseudoVSSUB_VX_M8 + {8, OperandInfo77}, // Inst #9028 = PseudoVSSUB_VX_M8_MASK + {5, OperandInfo70}, // Inst #9029 = PseudoVSSUB_VX_MF2 + {8, OperandInfo71}, // Inst #9030 = PseudoVSSUB_VX_MF2_MASK + {5, OperandInfo70}, // Inst #9031 = PseudoVSSUB_VX_MF4 + {8, OperandInfo71}, // Inst #9032 = PseudoVSSUB_VX_MF4_MASK + {5, OperandInfo70}, // Inst #9033 = PseudoVSSUB_VX_MF8 + {8, OperandInfo71}, // Inst #9034 = PseudoVSSUB_VX_MF8_MASK + {5, OperandInfo62}, // Inst #9035 = PseudoVSUB_VV_M1 + {8, OperandInfo63}, // Inst #9036 = PseudoVSUB_VV_M1_MASK + {5, OperandInfo64}, // Inst #9037 = PseudoVSUB_VV_M2 + {8, OperandInfo65}, // Inst #9038 = PseudoVSUB_VV_M2_MASK + {5, OperandInfo66}, // Inst #9039 = PseudoVSUB_VV_M4 + {8, OperandInfo67}, // Inst #9040 = PseudoVSUB_VV_M4_MASK + {5, OperandInfo68}, // Inst #9041 = PseudoVSUB_VV_M8 + {8, OperandInfo69}, // Inst #9042 = PseudoVSUB_VV_M8_MASK + {5, OperandInfo62}, // Inst #9043 = PseudoVSUB_VV_MF2 + {8, OperandInfo63}, // Inst #9044 = PseudoVSUB_VV_MF2_MASK + {5, OperandInfo62}, // Inst #9045 = PseudoVSUB_VV_MF4 + {8, OperandInfo63}, // Inst #9046 = PseudoVSUB_VV_MF4_MASK + {5, OperandInfo62}, // Inst #9047 = PseudoVSUB_VV_MF8 + {8, OperandInfo63}, // Inst #9048 = PseudoVSUB_VV_MF8_MASK + {5, OperandInfo70}, // Inst #9049 = PseudoVSUB_VX_M1 + {8, OperandInfo71}, // Inst #9050 = PseudoVSUB_VX_M1_MASK + {5, OperandInfo72}, // Inst #9051 = PseudoVSUB_VX_M2 + {8, OperandInfo73}, // Inst #9052 = PseudoVSUB_VX_M2_MASK + {5, OperandInfo74}, // Inst #9053 = PseudoVSUB_VX_M4 + {8, OperandInfo75}, // Inst #9054 = PseudoVSUB_VX_M4_MASK + {5, OperandInfo76}, // Inst #9055 = PseudoVSUB_VX_M8 + {8, OperandInfo77}, // Inst #9056 = PseudoVSUB_VX_M8_MASK + {5, OperandInfo70}, // Inst #9057 = PseudoVSUB_VX_MF2 + {8, OperandInfo71}, // Inst #9058 = PseudoVSUB_VX_MF2_MASK + {5, OperandInfo70}, // Inst #9059 = PseudoVSUB_VX_MF4 + {8, OperandInfo71}, // Inst #9060 = PseudoVSUB_VX_MF4_MASK + {5, OperandInfo70}, // Inst #9061 = PseudoVSUB_VX_MF8 + {8, OperandInfo71}, // Inst #9062 = PseudoVSUB_VX_MF8_MASK + {5, OperandInfo367}, // Inst #9063 = PseudoVSUXEI16_V_M1_M1 + {6, OperandInfo729}, // Inst #9064 = PseudoVSUXEI16_V_M1_M1_MASK + {5, OperandInfo730}, // Inst #9065 = PseudoVSUXEI16_V_M1_M2 + {6, OperandInfo731}, // Inst #9066 = PseudoVSUXEI16_V_M1_M2_MASK + {5, OperandInfo732}, // Inst #9067 = PseudoVSUXEI16_V_M1_M4 + {6, OperandInfo733}, // Inst #9068 = PseudoVSUXEI16_V_M1_M4_MASK + {5, OperandInfo367}, // Inst #9069 = PseudoVSUXEI16_V_M1_MF2 + {6, OperandInfo729}, // Inst #9070 = PseudoVSUXEI16_V_M1_MF2_MASK + {5, OperandInfo734}, // Inst #9071 = PseudoVSUXEI16_V_M2_M1 + {6, OperandInfo735}, // Inst #9072 = PseudoVSUXEI16_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #9073 = PseudoVSUXEI16_V_M2_M2 + {6, OperandInfo736}, // Inst #9074 = PseudoVSUXEI16_V_M2_M2_MASK + {5, OperandInfo737}, // Inst #9075 = PseudoVSUXEI16_V_M2_M4 + {6, OperandInfo738}, // Inst #9076 = PseudoVSUXEI16_V_M2_M4_MASK + {5, OperandInfo739}, // Inst #9077 = PseudoVSUXEI16_V_M2_M8 + {6, OperandInfo740}, // Inst #9078 = PseudoVSUXEI16_V_M2_M8_MASK + {5, OperandInfo741}, // Inst #9079 = PseudoVSUXEI16_V_M4_M2 + {6, OperandInfo742}, // Inst #9080 = PseudoVSUXEI16_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #9081 = PseudoVSUXEI16_V_M4_M4 + {6, OperandInfo743}, // Inst #9082 = PseudoVSUXEI16_V_M4_M4_MASK + {5, OperandInfo744}, // Inst #9083 = PseudoVSUXEI16_V_M4_M8 + {6, OperandInfo745}, // Inst #9084 = PseudoVSUXEI16_V_M4_M8_MASK + {5, OperandInfo746}, // Inst #9085 = PseudoVSUXEI16_V_M8_M4 + {6, OperandInfo747}, // Inst #9086 = PseudoVSUXEI16_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #9087 = PseudoVSUXEI16_V_M8_M8 + {6, OperandInfo748}, // Inst #9088 = PseudoVSUXEI16_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #9089 = PseudoVSUXEI16_V_MF2_M1 + {6, OperandInfo729}, // Inst #9090 = PseudoVSUXEI16_V_MF2_M1_MASK + {5, OperandInfo730}, // Inst #9091 = PseudoVSUXEI16_V_MF2_M2 + {6, OperandInfo731}, // Inst #9092 = PseudoVSUXEI16_V_MF2_M2_MASK + {5, OperandInfo367}, // Inst #9093 = PseudoVSUXEI16_V_MF2_MF2 + {6, OperandInfo729}, // Inst #9094 = PseudoVSUXEI16_V_MF2_MF2_MASK + {5, OperandInfo367}, // Inst #9095 = PseudoVSUXEI16_V_MF2_MF4 + {6, OperandInfo729}, // Inst #9096 = PseudoVSUXEI16_V_MF2_MF4_MASK + {5, OperandInfo367}, // Inst #9097 = PseudoVSUXEI16_V_MF4_M1 + {6, OperandInfo729}, // Inst #9098 = PseudoVSUXEI16_V_MF4_M1_MASK + {5, OperandInfo367}, // Inst #9099 = PseudoVSUXEI16_V_MF4_MF2 + {6, OperandInfo729}, // Inst #9100 = PseudoVSUXEI16_V_MF4_MF2_MASK + {5, OperandInfo367}, // Inst #9101 = PseudoVSUXEI16_V_MF4_MF4 + {6, OperandInfo729}, // Inst #9102 = PseudoVSUXEI16_V_MF4_MF4_MASK + {5, OperandInfo367}, // Inst #9103 = PseudoVSUXEI16_V_MF4_MF8 + {6, OperandInfo729}, // Inst #9104 = PseudoVSUXEI16_V_MF4_MF8_MASK + {5, OperandInfo367}, // Inst #9105 = PseudoVSUXEI32_V_M1_M1 + {6, OperandInfo729}, // Inst #9106 = PseudoVSUXEI32_V_M1_M1_MASK + {5, OperandInfo730}, // Inst #9107 = PseudoVSUXEI32_V_M1_M2 + {6, OperandInfo731}, // Inst #9108 = PseudoVSUXEI32_V_M1_M2_MASK + {5, OperandInfo367}, // Inst #9109 = PseudoVSUXEI32_V_M1_MF2 + {6, OperandInfo729}, // Inst #9110 = PseudoVSUXEI32_V_M1_MF2_MASK + {5, OperandInfo367}, // Inst #9111 = PseudoVSUXEI32_V_M1_MF4 + {6, OperandInfo729}, // Inst #9112 = PseudoVSUXEI32_V_M1_MF4_MASK + {5, OperandInfo734}, // Inst #9113 = PseudoVSUXEI32_V_M2_M1 + {6, OperandInfo735}, // Inst #9114 = PseudoVSUXEI32_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #9115 = PseudoVSUXEI32_V_M2_M2 + {6, OperandInfo736}, // Inst #9116 = PseudoVSUXEI32_V_M2_M2_MASK + {5, OperandInfo737}, // Inst #9117 = PseudoVSUXEI32_V_M2_M4 + {6, OperandInfo738}, // Inst #9118 = PseudoVSUXEI32_V_M2_M4_MASK + {5, OperandInfo734}, // Inst #9119 = PseudoVSUXEI32_V_M2_MF2 + {6, OperandInfo735}, // Inst #9120 = PseudoVSUXEI32_V_M2_MF2_MASK + {5, OperandInfo749}, // Inst #9121 = PseudoVSUXEI32_V_M4_M1 + {6, OperandInfo750}, // Inst #9122 = PseudoVSUXEI32_V_M4_M1_MASK + {5, OperandInfo741}, // Inst #9123 = PseudoVSUXEI32_V_M4_M2 + {6, OperandInfo742}, // Inst #9124 = PseudoVSUXEI32_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #9125 = PseudoVSUXEI32_V_M4_M4 + {6, OperandInfo743}, // Inst #9126 = PseudoVSUXEI32_V_M4_M4_MASK + {5, OperandInfo744}, // Inst #9127 = PseudoVSUXEI32_V_M4_M8 + {6, OperandInfo745}, // Inst #9128 = PseudoVSUXEI32_V_M4_M8_MASK + {5, OperandInfo751}, // Inst #9129 = PseudoVSUXEI32_V_M8_M2 + {6, OperandInfo752}, // Inst #9130 = PseudoVSUXEI32_V_M8_M2_MASK + {5, OperandInfo746}, // Inst #9131 = PseudoVSUXEI32_V_M8_M4 + {6, OperandInfo747}, // Inst #9132 = PseudoVSUXEI32_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #9133 = PseudoVSUXEI32_V_M8_M8 + {6, OperandInfo748}, // Inst #9134 = PseudoVSUXEI32_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #9135 = PseudoVSUXEI32_V_MF2_M1 + {6, OperandInfo729}, // Inst #9136 = PseudoVSUXEI32_V_MF2_M1_MASK + {5, OperandInfo367}, // Inst #9137 = PseudoVSUXEI32_V_MF2_MF2 + {6, OperandInfo729}, // Inst #9138 = PseudoVSUXEI32_V_MF2_MF2_MASK + {5, OperandInfo367}, // Inst #9139 = PseudoVSUXEI32_V_MF2_MF4 + {6, OperandInfo729}, // Inst #9140 = PseudoVSUXEI32_V_MF2_MF4_MASK + {5, OperandInfo367}, // Inst #9141 = PseudoVSUXEI32_V_MF2_MF8 + {6, OperandInfo729}, // Inst #9142 = PseudoVSUXEI32_V_MF2_MF8_MASK + {5, OperandInfo367}, // Inst #9143 = PseudoVSUXEI64_V_M1_M1 + {6, OperandInfo729}, // Inst #9144 = PseudoVSUXEI64_V_M1_M1_MASK + {5, OperandInfo367}, // Inst #9145 = PseudoVSUXEI64_V_M1_MF2 + {6, OperandInfo729}, // Inst #9146 = PseudoVSUXEI64_V_M1_MF2_MASK + {5, OperandInfo367}, // Inst #9147 = PseudoVSUXEI64_V_M1_MF4 + {6, OperandInfo729}, // Inst #9148 = PseudoVSUXEI64_V_M1_MF4_MASK + {5, OperandInfo367}, // Inst #9149 = PseudoVSUXEI64_V_M1_MF8 + {6, OperandInfo729}, // Inst #9150 = PseudoVSUXEI64_V_M1_MF8_MASK + {5, OperandInfo734}, // Inst #9151 = PseudoVSUXEI64_V_M2_M1 + {6, OperandInfo735}, // Inst #9152 = PseudoVSUXEI64_V_M2_M1_MASK + {5, OperandInfo377}, // Inst #9153 = PseudoVSUXEI64_V_M2_M2 + {6, OperandInfo736}, // Inst #9154 = PseudoVSUXEI64_V_M2_M2_MASK + {5, OperandInfo734}, // Inst #9155 = PseudoVSUXEI64_V_M2_MF2 + {6, OperandInfo735}, // Inst #9156 = PseudoVSUXEI64_V_M2_MF2_MASK + {5, OperandInfo734}, // Inst #9157 = PseudoVSUXEI64_V_M2_MF4 + {6, OperandInfo735}, // Inst #9158 = PseudoVSUXEI64_V_M2_MF4_MASK + {5, OperandInfo749}, // Inst #9159 = PseudoVSUXEI64_V_M4_M1 + {6, OperandInfo750}, // Inst #9160 = PseudoVSUXEI64_V_M4_M1_MASK + {5, OperandInfo741}, // Inst #9161 = PseudoVSUXEI64_V_M4_M2 + {6, OperandInfo742}, // Inst #9162 = PseudoVSUXEI64_V_M4_M2_MASK + {5, OperandInfo385}, // Inst #9163 = PseudoVSUXEI64_V_M4_M4 + {6, OperandInfo743}, // Inst #9164 = PseudoVSUXEI64_V_M4_M4_MASK + {5, OperandInfo749}, // Inst #9165 = PseudoVSUXEI64_V_M4_MF2 + {6, OperandInfo750}, // Inst #9166 = PseudoVSUXEI64_V_M4_MF2_MASK + {5, OperandInfo753}, // Inst #9167 = PseudoVSUXEI64_V_M8_M1 + {6, OperandInfo754}, // Inst #9168 = PseudoVSUXEI64_V_M8_M1_MASK + {5, OperandInfo751}, // Inst #9169 = PseudoVSUXEI64_V_M8_M2 + {6, OperandInfo752}, // Inst #9170 = PseudoVSUXEI64_V_M8_M2_MASK + {5, OperandInfo746}, // Inst #9171 = PseudoVSUXEI64_V_M8_M4 + {6, OperandInfo747}, // Inst #9172 = PseudoVSUXEI64_V_M8_M4_MASK + {5, OperandInfo391}, // Inst #9173 = PseudoVSUXEI64_V_M8_M8 + {6, OperandInfo748}, // Inst #9174 = PseudoVSUXEI64_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #9175 = PseudoVSUXEI8_V_M1_M1 + {6, OperandInfo729}, // Inst #9176 = PseudoVSUXEI8_V_M1_M1_MASK + {5, OperandInfo730}, // Inst #9177 = PseudoVSUXEI8_V_M1_M2 + {6, OperandInfo731}, // Inst #9178 = PseudoVSUXEI8_V_M1_M2_MASK + {5, OperandInfo732}, // Inst #9179 = PseudoVSUXEI8_V_M1_M4 + {6, OperandInfo733}, // Inst #9180 = PseudoVSUXEI8_V_M1_M4_MASK + {5, OperandInfo755}, // Inst #9181 = PseudoVSUXEI8_V_M1_M8 + {6, OperandInfo756}, // Inst #9182 = PseudoVSUXEI8_V_M1_M8_MASK + {5, OperandInfo377}, // Inst #9183 = PseudoVSUXEI8_V_M2_M2 + {6, OperandInfo736}, // Inst #9184 = PseudoVSUXEI8_V_M2_M2_MASK + {5, OperandInfo737}, // Inst #9185 = PseudoVSUXEI8_V_M2_M4 + {6, OperandInfo738}, // Inst #9186 = PseudoVSUXEI8_V_M2_M4_MASK + {5, OperandInfo739}, // Inst #9187 = PseudoVSUXEI8_V_M2_M8 + {6, OperandInfo740}, // Inst #9188 = PseudoVSUXEI8_V_M2_M8_MASK + {5, OperandInfo385}, // Inst #9189 = PseudoVSUXEI8_V_M4_M4 + {6, OperandInfo743}, // Inst #9190 = PseudoVSUXEI8_V_M4_M4_MASK + {5, OperandInfo744}, // Inst #9191 = PseudoVSUXEI8_V_M4_M8 + {6, OperandInfo745}, // Inst #9192 = PseudoVSUXEI8_V_M4_M8_MASK + {5, OperandInfo391}, // Inst #9193 = PseudoVSUXEI8_V_M8_M8 + {6, OperandInfo748}, // Inst #9194 = PseudoVSUXEI8_V_M8_M8_MASK + {5, OperandInfo367}, // Inst #9195 = PseudoVSUXEI8_V_MF2_M1 + {6, OperandInfo729}, // Inst #9196 = PseudoVSUXEI8_V_MF2_M1_MASK + {5, OperandInfo730}, // Inst #9197 = PseudoVSUXEI8_V_MF2_M2 + {6, OperandInfo731}, // Inst #9198 = PseudoVSUXEI8_V_MF2_M2_MASK + {5, OperandInfo732}, // Inst #9199 = PseudoVSUXEI8_V_MF2_M4 + {6, OperandInfo733}, // Inst #9200 = PseudoVSUXEI8_V_MF2_M4_MASK + {5, OperandInfo367}, // Inst #9201 = PseudoVSUXEI8_V_MF2_MF2 + {6, OperandInfo729}, // Inst #9202 = PseudoVSUXEI8_V_MF2_MF2_MASK + {5, OperandInfo367}, // Inst #9203 = PseudoVSUXEI8_V_MF4_M1 + {6, OperandInfo729}, // Inst #9204 = PseudoVSUXEI8_V_MF4_M1_MASK + {5, OperandInfo730}, // Inst #9205 = PseudoVSUXEI8_V_MF4_M2 + {6, OperandInfo731}, // Inst #9206 = PseudoVSUXEI8_V_MF4_M2_MASK + {5, OperandInfo367}, // Inst #9207 = PseudoVSUXEI8_V_MF4_MF2 + {6, OperandInfo729}, // Inst #9208 = PseudoVSUXEI8_V_MF4_MF2_MASK + {5, OperandInfo367}, // Inst #9209 = PseudoVSUXEI8_V_MF4_MF4 + {6, OperandInfo729}, // Inst #9210 = PseudoVSUXEI8_V_MF4_MF4_MASK + {5, OperandInfo367}, // Inst #9211 = PseudoVSUXEI8_V_MF8_M1 + {6, OperandInfo729}, // Inst #9212 = PseudoVSUXEI8_V_MF8_M1_MASK + {5, OperandInfo367}, // Inst #9213 = PseudoVSUXEI8_V_MF8_MF2 + {6, OperandInfo729}, // Inst #9214 = PseudoVSUXEI8_V_MF8_MF2_MASK + {5, OperandInfo367}, // Inst #9215 = PseudoVSUXEI8_V_MF8_MF4 + {6, OperandInfo729}, // Inst #9216 = PseudoVSUXEI8_V_MF8_MF4_MASK + {5, OperandInfo367}, // Inst #9217 = PseudoVSUXEI8_V_MF8_MF8 + {6, OperandInfo729}, // Inst #9218 = PseudoVSUXEI8_V_MF8_MF8_MASK + {5, OperandInfo757}, // Inst #9219 = PseudoVSUXSEG2EI16_V_M1_M1 + {6, OperandInfo758}, // Inst #9220 = PseudoVSUXSEG2EI16_V_M1_M1_MASK + {5, OperandInfo759}, // Inst #9221 = PseudoVSUXSEG2EI16_V_M1_M2 + {6, OperandInfo760}, // Inst #9222 = PseudoVSUXSEG2EI16_V_M1_M2_MASK + {5, OperandInfo761}, // Inst #9223 = PseudoVSUXSEG2EI16_V_M1_M4 + {6, OperandInfo762}, // Inst #9224 = PseudoVSUXSEG2EI16_V_M1_M4_MASK + {5, OperandInfo757}, // Inst #9225 = PseudoVSUXSEG2EI16_V_M1_MF2 + {6, OperandInfo758}, // Inst #9226 = PseudoVSUXSEG2EI16_V_M1_MF2_MASK + {5, OperandInfo763}, // Inst #9227 = PseudoVSUXSEG2EI16_V_M2_M1 + {6, OperandInfo764}, // Inst #9228 = PseudoVSUXSEG2EI16_V_M2_M1_MASK + {5, OperandInfo765}, // Inst #9229 = PseudoVSUXSEG2EI16_V_M2_M2 + {6, OperandInfo766}, // Inst #9230 = PseudoVSUXSEG2EI16_V_M2_M2_MASK + {5, OperandInfo767}, // Inst #9231 = PseudoVSUXSEG2EI16_V_M2_M4 + {6, OperandInfo768}, // Inst #9232 = PseudoVSUXSEG2EI16_V_M2_M4_MASK + {5, OperandInfo769}, // Inst #9233 = PseudoVSUXSEG2EI16_V_M4_M2 + {6, OperandInfo770}, // Inst #9234 = PseudoVSUXSEG2EI16_V_M4_M2_MASK + {5, OperandInfo771}, // Inst #9235 = PseudoVSUXSEG2EI16_V_M4_M4 + {6, OperandInfo772}, // Inst #9236 = PseudoVSUXSEG2EI16_V_M4_M4_MASK + {5, OperandInfo773}, // Inst #9237 = PseudoVSUXSEG2EI16_V_M8_M4 + {6, OperandInfo774}, // Inst #9238 = PseudoVSUXSEG2EI16_V_M8_M4_MASK + {5, OperandInfo757}, // Inst #9239 = PseudoVSUXSEG2EI16_V_MF2_M1 + {6, OperandInfo758}, // Inst #9240 = PseudoVSUXSEG2EI16_V_MF2_M1_MASK + {5, OperandInfo759}, // Inst #9241 = PseudoVSUXSEG2EI16_V_MF2_M2 + {6, OperandInfo760}, // Inst #9242 = PseudoVSUXSEG2EI16_V_MF2_M2_MASK + {5, OperandInfo757}, // Inst #9243 = PseudoVSUXSEG2EI16_V_MF2_MF2 + {6, OperandInfo758}, // Inst #9244 = PseudoVSUXSEG2EI16_V_MF2_MF2_MASK + {5, OperandInfo757}, // Inst #9245 = PseudoVSUXSEG2EI16_V_MF2_MF4 + {6, OperandInfo758}, // Inst #9246 = PseudoVSUXSEG2EI16_V_MF2_MF4_MASK + {5, OperandInfo757}, // Inst #9247 = PseudoVSUXSEG2EI16_V_MF4_M1 + {6, OperandInfo758}, // Inst #9248 = PseudoVSUXSEG2EI16_V_MF4_M1_MASK + {5, OperandInfo757}, // Inst #9249 = PseudoVSUXSEG2EI16_V_MF4_MF2 + {6, OperandInfo758}, // Inst #9250 = PseudoVSUXSEG2EI16_V_MF4_MF2_MASK + {5, OperandInfo757}, // Inst #9251 = PseudoVSUXSEG2EI16_V_MF4_MF4 + {6, OperandInfo758}, // Inst #9252 = PseudoVSUXSEG2EI16_V_MF4_MF4_MASK + {5, OperandInfo757}, // Inst #9253 = PseudoVSUXSEG2EI16_V_MF4_MF8 + {6, OperandInfo758}, // Inst #9254 = PseudoVSUXSEG2EI16_V_MF4_MF8_MASK + {5, OperandInfo757}, // Inst #9255 = PseudoVSUXSEG2EI32_V_M1_M1 + {6, OperandInfo758}, // Inst #9256 = PseudoVSUXSEG2EI32_V_M1_M1_MASK + {5, OperandInfo759}, // Inst #9257 = PseudoVSUXSEG2EI32_V_M1_M2 + {6, OperandInfo760}, // Inst #9258 = PseudoVSUXSEG2EI32_V_M1_M2_MASK + {5, OperandInfo757}, // Inst #9259 = PseudoVSUXSEG2EI32_V_M1_MF2 + {6, OperandInfo758}, // Inst #9260 = PseudoVSUXSEG2EI32_V_M1_MF2_MASK + {5, OperandInfo757}, // Inst #9261 = PseudoVSUXSEG2EI32_V_M1_MF4 + {6, OperandInfo758}, // Inst #9262 = PseudoVSUXSEG2EI32_V_M1_MF4_MASK + {5, OperandInfo763}, // Inst #9263 = PseudoVSUXSEG2EI32_V_M2_M1 + {6, OperandInfo764}, // Inst #9264 = PseudoVSUXSEG2EI32_V_M2_M1_MASK + {5, OperandInfo765}, // Inst #9265 = PseudoVSUXSEG2EI32_V_M2_M2 + {6, OperandInfo766}, // Inst #9266 = PseudoVSUXSEG2EI32_V_M2_M2_MASK + {5, OperandInfo767}, // Inst #9267 = PseudoVSUXSEG2EI32_V_M2_M4 + {6, OperandInfo768}, // Inst #9268 = PseudoVSUXSEG2EI32_V_M2_M4_MASK + {5, OperandInfo763}, // Inst #9269 = PseudoVSUXSEG2EI32_V_M2_MF2 + {6, OperandInfo764}, // Inst #9270 = PseudoVSUXSEG2EI32_V_M2_MF2_MASK + {5, OperandInfo775}, // Inst #9271 = PseudoVSUXSEG2EI32_V_M4_M1 + {6, OperandInfo776}, // Inst #9272 = PseudoVSUXSEG2EI32_V_M4_M1_MASK + {5, OperandInfo769}, // Inst #9273 = PseudoVSUXSEG2EI32_V_M4_M2 + {6, OperandInfo770}, // Inst #9274 = PseudoVSUXSEG2EI32_V_M4_M2_MASK + {5, OperandInfo771}, // Inst #9275 = PseudoVSUXSEG2EI32_V_M4_M4 + {6, OperandInfo772}, // Inst #9276 = PseudoVSUXSEG2EI32_V_M4_M4_MASK + {5, OperandInfo777}, // Inst #9277 = PseudoVSUXSEG2EI32_V_M8_M2 + {6, OperandInfo778}, // Inst #9278 = PseudoVSUXSEG2EI32_V_M8_M2_MASK + {5, OperandInfo773}, // Inst #9279 = PseudoVSUXSEG2EI32_V_M8_M4 + {6, OperandInfo774}, // Inst #9280 = PseudoVSUXSEG2EI32_V_M8_M4_MASK + {5, OperandInfo757}, // Inst #9281 = PseudoVSUXSEG2EI32_V_MF2_M1 + {6, OperandInfo758}, // Inst #9282 = PseudoVSUXSEG2EI32_V_MF2_M1_MASK + {5, OperandInfo757}, // Inst #9283 = PseudoVSUXSEG2EI32_V_MF2_MF2 + {6, OperandInfo758}, // Inst #9284 = PseudoVSUXSEG2EI32_V_MF2_MF2_MASK + {5, OperandInfo757}, // Inst #9285 = PseudoVSUXSEG2EI32_V_MF2_MF4 + {6, OperandInfo758}, // Inst #9286 = PseudoVSUXSEG2EI32_V_MF2_MF4_MASK + {5, OperandInfo757}, // Inst #9287 = PseudoVSUXSEG2EI32_V_MF2_MF8 + {6, OperandInfo758}, // Inst #9288 = PseudoVSUXSEG2EI32_V_MF2_MF8_MASK + {5, OperandInfo757}, // Inst #9289 = PseudoVSUXSEG2EI64_V_M1_M1 + {6, OperandInfo758}, // Inst #9290 = PseudoVSUXSEG2EI64_V_M1_M1_MASK + {5, OperandInfo757}, // Inst #9291 = PseudoVSUXSEG2EI64_V_M1_MF2 + {6, OperandInfo758}, // Inst #9292 = PseudoVSUXSEG2EI64_V_M1_MF2_MASK + {5, OperandInfo757}, // Inst #9293 = PseudoVSUXSEG2EI64_V_M1_MF4 + {6, OperandInfo758}, // Inst #9294 = PseudoVSUXSEG2EI64_V_M1_MF4_MASK + {5, OperandInfo757}, // Inst #9295 = PseudoVSUXSEG2EI64_V_M1_MF8 + {6, OperandInfo758}, // Inst #9296 = PseudoVSUXSEG2EI64_V_M1_MF8_MASK + {5, OperandInfo763}, // Inst #9297 = PseudoVSUXSEG2EI64_V_M2_M1 + {6, OperandInfo764}, // Inst #9298 = PseudoVSUXSEG2EI64_V_M2_M1_MASK + {5, OperandInfo765}, // Inst #9299 = PseudoVSUXSEG2EI64_V_M2_M2 + {6, OperandInfo766}, // Inst #9300 = PseudoVSUXSEG2EI64_V_M2_M2_MASK + {5, OperandInfo763}, // Inst #9301 = PseudoVSUXSEG2EI64_V_M2_MF2 + {6, OperandInfo764}, // Inst #9302 = PseudoVSUXSEG2EI64_V_M2_MF2_MASK + {5, OperandInfo763}, // Inst #9303 = PseudoVSUXSEG2EI64_V_M2_MF4 + {6, OperandInfo764}, // Inst #9304 = PseudoVSUXSEG2EI64_V_M2_MF4_MASK + {5, OperandInfo775}, // Inst #9305 = PseudoVSUXSEG2EI64_V_M4_M1 + {6, OperandInfo776}, // Inst #9306 = PseudoVSUXSEG2EI64_V_M4_M1_MASK + {5, OperandInfo769}, // Inst #9307 = PseudoVSUXSEG2EI64_V_M4_M2 + {6, OperandInfo770}, // Inst #9308 = PseudoVSUXSEG2EI64_V_M4_M2_MASK + {5, OperandInfo771}, // Inst #9309 = PseudoVSUXSEG2EI64_V_M4_M4 + {6, OperandInfo772}, // Inst #9310 = PseudoVSUXSEG2EI64_V_M4_M4_MASK + {5, OperandInfo775}, // Inst #9311 = PseudoVSUXSEG2EI64_V_M4_MF2 + {6, OperandInfo776}, // Inst #9312 = PseudoVSUXSEG2EI64_V_M4_MF2_MASK + {5, OperandInfo779}, // Inst #9313 = PseudoVSUXSEG2EI64_V_M8_M1 + {6, OperandInfo780}, // Inst #9314 = PseudoVSUXSEG2EI64_V_M8_M1_MASK + {5, OperandInfo777}, // Inst #9315 = PseudoVSUXSEG2EI64_V_M8_M2 + {6, OperandInfo778}, // Inst #9316 = PseudoVSUXSEG2EI64_V_M8_M2_MASK + {5, OperandInfo773}, // Inst #9317 = PseudoVSUXSEG2EI64_V_M8_M4 + {6, OperandInfo774}, // Inst #9318 = PseudoVSUXSEG2EI64_V_M8_M4_MASK + {5, OperandInfo757}, // Inst #9319 = PseudoVSUXSEG2EI8_V_M1_M1 + {6, OperandInfo758}, // Inst #9320 = PseudoVSUXSEG2EI8_V_M1_M1_MASK + {5, OperandInfo759}, // Inst #9321 = PseudoVSUXSEG2EI8_V_M1_M2 + {6, OperandInfo760}, // Inst #9322 = PseudoVSUXSEG2EI8_V_M1_M2_MASK + {5, OperandInfo761}, // Inst #9323 = PseudoVSUXSEG2EI8_V_M1_M4 + {6, OperandInfo762}, // Inst #9324 = PseudoVSUXSEG2EI8_V_M1_M4_MASK + {5, OperandInfo765}, // Inst #9325 = PseudoVSUXSEG2EI8_V_M2_M2 + {6, OperandInfo766}, // Inst #9326 = PseudoVSUXSEG2EI8_V_M2_M2_MASK + {5, OperandInfo767}, // Inst #9327 = PseudoVSUXSEG2EI8_V_M2_M4 + {6, OperandInfo768}, // Inst #9328 = PseudoVSUXSEG2EI8_V_M2_M4_MASK + {5, OperandInfo771}, // Inst #9329 = PseudoVSUXSEG2EI8_V_M4_M4 + {6, OperandInfo772}, // Inst #9330 = PseudoVSUXSEG2EI8_V_M4_M4_MASK + {5, OperandInfo757}, // Inst #9331 = PseudoVSUXSEG2EI8_V_MF2_M1 + {6, OperandInfo758}, // Inst #9332 = PseudoVSUXSEG2EI8_V_MF2_M1_MASK + {5, OperandInfo759}, // Inst #9333 = PseudoVSUXSEG2EI8_V_MF2_M2 + {6, OperandInfo760}, // Inst #9334 = PseudoVSUXSEG2EI8_V_MF2_M2_MASK + {5, OperandInfo761}, // Inst #9335 = PseudoVSUXSEG2EI8_V_MF2_M4 + {6, OperandInfo762}, // Inst #9336 = PseudoVSUXSEG2EI8_V_MF2_M4_MASK + {5, OperandInfo757}, // Inst #9337 = PseudoVSUXSEG2EI8_V_MF2_MF2 + {6, OperandInfo758}, // Inst #9338 = PseudoVSUXSEG2EI8_V_MF2_MF2_MASK + {5, OperandInfo757}, // Inst #9339 = PseudoVSUXSEG2EI8_V_MF4_M1 + {6, OperandInfo758}, // Inst #9340 = PseudoVSUXSEG2EI8_V_MF4_M1_MASK + {5, OperandInfo759}, // Inst #9341 = PseudoVSUXSEG2EI8_V_MF4_M2 + {6, OperandInfo760}, // Inst #9342 = PseudoVSUXSEG2EI8_V_MF4_M2_MASK + {5, OperandInfo757}, // Inst #9343 = PseudoVSUXSEG2EI8_V_MF4_MF2 + {6, OperandInfo758}, // Inst #9344 = PseudoVSUXSEG2EI8_V_MF4_MF2_MASK + {5, OperandInfo757}, // Inst #9345 = PseudoVSUXSEG2EI8_V_MF4_MF4 + {6, OperandInfo758}, // Inst #9346 = PseudoVSUXSEG2EI8_V_MF4_MF4_MASK + {5, OperandInfo757}, // Inst #9347 = PseudoVSUXSEG2EI8_V_MF8_M1 + {6, OperandInfo758}, // Inst #9348 = PseudoVSUXSEG2EI8_V_MF8_M1_MASK + {5, OperandInfo757}, // Inst #9349 = PseudoVSUXSEG2EI8_V_MF8_MF2 + {6, OperandInfo758}, // Inst #9350 = PseudoVSUXSEG2EI8_V_MF8_MF2_MASK + {5, OperandInfo757}, // Inst #9351 = PseudoVSUXSEG2EI8_V_MF8_MF4 + {6, OperandInfo758}, // Inst #9352 = PseudoVSUXSEG2EI8_V_MF8_MF4_MASK + {5, OperandInfo757}, // Inst #9353 = PseudoVSUXSEG2EI8_V_MF8_MF8 + {6, OperandInfo758}, // Inst #9354 = PseudoVSUXSEG2EI8_V_MF8_MF8_MASK + {5, OperandInfo781}, // Inst #9355 = PseudoVSUXSEG3EI16_V_M1_M1 + {6, OperandInfo782}, // Inst #9356 = PseudoVSUXSEG3EI16_V_M1_M1_MASK + {5, OperandInfo783}, // Inst #9357 = PseudoVSUXSEG3EI16_V_M1_M2 + {6, OperandInfo784}, // Inst #9358 = PseudoVSUXSEG3EI16_V_M1_M2_MASK + {5, OperandInfo781}, // Inst #9359 = PseudoVSUXSEG3EI16_V_M1_MF2 + {6, OperandInfo782}, // Inst #9360 = PseudoVSUXSEG3EI16_V_M1_MF2_MASK + {5, OperandInfo785}, // Inst #9361 = PseudoVSUXSEG3EI16_V_M2_M1 + {6, OperandInfo786}, // Inst #9362 = PseudoVSUXSEG3EI16_V_M2_M1_MASK + {5, OperandInfo787}, // Inst #9363 = PseudoVSUXSEG3EI16_V_M2_M2 + {6, OperandInfo788}, // Inst #9364 = PseudoVSUXSEG3EI16_V_M2_M2_MASK + {5, OperandInfo789}, // Inst #9365 = PseudoVSUXSEG3EI16_V_M4_M2 + {6, OperandInfo790}, // Inst #9366 = PseudoVSUXSEG3EI16_V_M4_M2_MASK + {5, OperandInfo781}, // Inst #9367 = PseudoVSUXSEG3EI16_V_MF2_M1 + {6, OperandInfo782}, // Inst #9368 = PseudoVSUXSEG3EI16_V_MF2_M1_MASK + {5, OperandInfo783}, // Inst #9369 = PseudoVSUXSEG3EI16_V_MF2_M2 + {6, OperandInfo784}, // Inst #9370 = PseudoVSUXSEG3EI16_V_MF2_M2_MASK + {5, OperandInfo781}, // Inst #9371 = PseudoVSUXSEG3EI16_V_MF2_MF2 + {6, OperandInfo782}, // Inst #9372 = PseudoVSUXSEG3EI16_V_MF2_MF2_MASK + {5, OperandInfo781}, // Inst #9373 = PseudoVSUXSEG3EI16_V_MF2_MF4 + {6, OperandInfo782}, // Inst #9374 = PseudoVSUXSEG3EI16_V_MF2_MF4_MASK + {5, OperandInfo781}, // Inst #9375 = PseudoVSUXSEG3EI16_V_MF4_M1 + {6, OperandInfo782}, // Inst #9376 = PseudoVSUXSEG3EI16_V_MF4_M1_MASK + {5, OperandInfo781}, // Inst #9377 = PseudoVSUXSEG3EI16_V_MF4_MF2 + {6, OperandInfo782}, // Inst #9378 = PseudoVSUXSEG3EI16_V_MF4_MF2_MASK + {5, OperandInfo781}, // Inst #9379 = PseudoVSUXSEG3EI16_V_MF4_MF4 + {6, OperandInfo782}, // Inst #9380 = PseudoVSUXSEG3EI16_V_MF4_MF4_MASK + {5, OperandInfo781}, // Inst #9381 = PseudoVSUXSEG3EI16_V_MF4_MF8 + {6, OperandInfo782}, // Inst #9382 = PseudoVSUXSEG3EI16_V_MF4_MF8_MASK + {5, OperandInfo781}, // Inst #9383 = PseudoVSUXSEG3EI32_V_M1_M1 + {6, OperandInfo782}, // Inst #9384 = PseudoVSUXSEG3EI32_V_M1_M1_MASK + {5, OperandInfo783}, // Inst #9385 = PseudoVSUXSEG3EI32_V_M1_M2 + {6, OperandInfo784}, // Inst #9386 = PseudoVSUXSEG3EI32_V_M1_M2_MASK + {5, OperandInfo781}, // Inst #9387 = PseudoVSUXSEG3EI32_V_M1_MF2 + {6, OperandInfo782}, // Inst #9388 = PseudoVSUXSEG3EI32_V_M1_MF2_MASK + {5, OperandInfo781}, // Inst #9389 = PseudoVSUXSEG3EI32_V_M1_MF4 + {6, OperandInfo782}, // Inst #9390 = PseudoVSUXSEG3EI32_V_M1_MF4_MASK + {5, OperandInfo785}, // Inst #9391 = PseudoVSUXSEG3EI32_V_M2_M1 + {6, OperandInfo786}, // Inst #9392 = PseudoVSUXSEG3EI32_V_M2_M1_MASK + {5, OperandInfo787}, // Inst #9393 = PseudoVSUXSEG3EI32_V_M2_M2 + {6, OperandInfo788}, // Inst #9394 = PseudoVSUXSEG3EI32_V_M2_M2_MASK + {5, OperandInfo785}, // Inst #9395 = PseudoVSUXSEG3EI32_V_M2_MF2 + {6, OperandInfo786}, // Inst #9396 = PseudoVSUXSEG3EI32_V_M2_MF2_MASK + {5, OperandInfo791}, // Inst #9397 = PseudoVSUXSEG3EI32_V_M4_M1 + {6, OperandInfo792}, // Inst #9398 = PseudoVSUXSEG3EI32_V_M4_M1_MASK + {5, OperandInfo789}, // Inst #9399 = PseudoVSUXSEG3EI32_V_M4_M2 + {6, OperandInfo790}, // Inst #9400 = PseudoVSUXSEG3EI32_V_M4_M2_MASK + {5, OperandInfo793}, // Inst #9401 = PseudoVSUXSEG3EI32_V_M8_M2 + {6, OperandInfo794}, // Inst #9402 = PseudoVSUXSEG3EI32_V_M8_M2_MASK + {5, OperandInfo781}, // Inst #9403 = PseudoVSUXSEG3EI32_V_MF2_M1 + {6, OperandInfo782}, // Inst #9404 = PseudoVSUXSEG3EI32_V_MF2_M1_MASK + {5, OperandInfo781}, // Inst #9405 = PseudoVSUXSEG3EI32_V_MF2_MF2 + {6, OperandInfo782}, // Inst #9406 = PseudoVSUXSEG3EI32_V_MF2_MF2_MASK + {5, OperandInfo781}, // Inst #9407 = PseudoVSUXSEG3EI32_V_MF2_MF4 + {6, OperandInfo782}, // Inst #9408 = PseudoVSUXSEG3EI32_V_MF2_MF4_MASK + {5, OperandInfo781}, // Inst #9409 = PseudoVSUXSEG3EI32_V_MF2_MF8 + {6, OperandInfo782}, // Inst #9410 = PseudoVSUXSEG3EI32_V_MF2_MF8_MASK + {5, OperandInfo781}, // Inst #9411 = PseudoVSUXSEG3EI64_V_M1_M1 + {6, OperandInfo782}, // Inst #9412 = PseudoVSUXSEG3EI64_V_M1_M1_MASK + {5, OperandInfo781}, // Inst #9413 = PseudoVSUXSEG3EI64_V_M1_MF2 + {6, OperandInfo782}, // Inst #9414 = PseudoVSUXSEG3EI64_V_M1_MF2_MASK + {5, OperandInfo781}, // Inst #9415 = PseudoVSUXSEG3EI64_V_M1_MF4 + {6, OperandInfo782}, // Inst #9416 = PseudoVSUXSEG3EI64_V_M1_MF4_MASK + {5, OperandInfo781}, // Inst #9417 = PseudoVSUXSEG3EI64_V_M1_MF8 + {6, OperandInfo782}, // Inst #9418 = PseudoVSUXSEG3EI64_V_M1_MF8_MASK + {5, OperandInfo785}, // Inst #9419 = PseudoVSUXSEG3EI64_V_M2_M1 + {6, OperandInfo786}, // Inst #9420 = PseudoVSUXSEG3EI64_V_M2_M1_MASK + {5, OperandInfo787}, // Inst #9421 = PseudoVSUXSEG3EI64_V_M2_M2 + {6, OperandInfo788}, // Inst #9422 = PseudoVSUXSEG3EI64_V_M2_M2_MASK + {5, OperandInfo785}, // Inst #9423 = PseudoVSUXSEG3EI64_V_M2_MF2 + {6, OperandInfo786}, // Inst #9424 = PseudoVSUXSEG3EI64_V_M2_MF2_MASK + {5, OperandInfo785}, // Inst #9425 = PseudoVSUXSEG3EI64_V_M2_MF4 + {6, OperandInfo786}, // Inst #9426 = PseudoVSUXSEG3EI64_V_M2_MF4_MASK + {5, OperandInfo791}, // Inst #9427 = PseudoVSUXSEG3EI64_V_M4_M1 + {6, OperandInfo792}, // Inst #9428 = PseudoVSUXSEG3EI64_V_M4_M1_MASK + {5, OperandInfo789}, // Inst #9429 = PseudoVSUXSEG3EI64_V_M4_M2 + {6, OperandInfo790}, // Inst #9430 = PseudoVSUXSEG3EI64_V_M4_M2_MASK + {5, OperandInfo791}, // Inst #9431 = PseudoVSUXSEG3EI64_V_M4_MF2 + {6, OperandInfo792}, // Inst #9432 = PseudoVSUXSEG3EI64_V_M4_MF2_MASK + {5, OperandInfo795}, // Inst #9433 = PseudoVSUXSEG3EI64_V_M8_M1 + {6, OperandInfo796}, // Inst #9434 = PseudoVSUXSEG3EI64_V_M8_M1_MASK + {5, OperandInfo793}, // Inst #9435 = PseudoVSUXSEG3EI64_V_M8_M2 + {6, OperandInfo794}, // Inst #9436 = PseudoVSUXSEG3EI64_V_M8_M2_MASK + {5, OperandInfo781}, // Inst #9437 = PseudoVSUXSEG3EI8_V_M1_M1 + {6, OperandInfo782}, // Inst #9438 = PseudoVSUXSEG3EI8_V_M1_M1_MASK + {5, OperandInfo783}, // Inst #9439 = PseudoVSUXSEG3EI8_V_M1_M2 + {6, OperandInfo784}, // Inst #9440 = PseudoVSUXSEG3EI8_V_M1_M2_MASK + {5, OperandInfo787}, // Inst #9441 = PseudoVSUXSEG3EI8_V_M2_M2 + {6, OperandInfo788}, // Inst #9442 = PseudoVSUXSEG3EI8_V_M2_M2_MASK + {5, OperandInfo781}, // Inst #9443 = PseudoVSUXSEG3EI8_V_MF2_M1 + {6, OperandInfo782}, // Inst #9444 = PseudoVSUXSEG3EI8_V_MF2_M1_MASK + {5, OperandInfo783}, // Inst #9445 = PseudoVSUXSEG3EI8_V_MF2_M2 + {6, OperandInfo784}, // Inst #9446 = PseudoVSUXSEG3EI8_V_MF2_M2_MASK + {5, OperandInfo781}, // Inst #9447 = PseudoVSUXSEG3EI8_V_MF2_MF2 + {6, OperandInfo782}, // Inst #9448 = PseudoVSUXSEG3EI8_V_MF2_MF2_MASK + {5, OperandInfo781}, // Inst #9449 = PseudoVSUXSEG3EI8_V_MF4_M1 + {6, OperandInfo782}, // Inst #9450 = PseudoVSUXSEG3EI8_V_MF4_M1_MASK + {5, OperandInfo783}, // Inst #9451 = PseudoVSUXSEG3EI8_V_MF4_M2 + {6, OperandInfo784}, // Inst #9452 = PseudoVSUXSEG3EI8_V_MF4_M2_MASK + {5, OperandInfo781}, // Inst #9453 = PseudoVSUXSEG3EI8_V_MF4_MF2 + {6, OperandInfo782}, // Inst #9454 = PseudoVSUXSEG3EI8_V_MF4_MF2_MASK + {5, OperandInfo781}, // Inst #9455 = PseudoVSUXSEG3EI8_V_MF4_MF4 + {6, OperandInfo782}, // Inst #9456 = PseudoVSUXSEG3EI8_V_MF4_MF4_MASK + {5, OperandInfo781}, // Inst #9457 = PseudoVSUXSEG3EI8_V_MF8_M1 + {6, OperandInfo782}, // Inst #9458 = PseudoVSUXSEG3EI8_V_MF8_M1_MASK + {5, OperandInfo781}, // Inst #9459 = PseudoVSUXSEG3EI8_V_MF8_MF2 + {6, OperandInfo782}, // Inst #9460 = PseudoVSUXSEG3EI8_V_MF8_MF2_MASK + {5, OperandInfo781}, // Inst #9461 = PseudoVSUXSEG3EI8_V_MF8_MF4 + {6, OperandInfo782}, // Inst #9462 = PseudoVSUXSEG3EI8_V_MF8_MF4_MASK + {5, OperandInfo781}, // Inst #9463 = PseudoVSUXSEG3EI8_V_MF8_MF8 + {6, OperandInfo782}, // Inst #9464 = PseudoVSUXSEG3EI8_V_MF8_MF8_MASK + {5, OperandInfo797}, // Inst #9465 = PseudoVSUXSEG4EI16_V_M1_M1 + {6, OperandInfo798}, // Inst #9466 = PseudoVSUXSEG4EI16_V_M1_M1_MASK + {5, OperandInfo799}, // Inst #9467 = PseudoVSUXSEG4EI16_V_M1_M2 + {6, OperandInfo800}, // Inst #9468 = PseudoVSUXSEG4EI16_V_M1_M2_MASK + {5, OperandInfo797}, // Inst #9469 = PseudoVSUXSEG4EI16_V_M1_MF2 + {6, OperandInfo798}, // Inst #9470 = PseudoVSUXSEG4EI16_V_M1_MF2_MASK + {5, OperandInfo801}, // Inst #9471 = PseudoVSUXSEG4EI16_V_M2_M1 + {6, OperandInfo802}, // Inst #9472 = PseudoVSUXSEG4EI16_V_M2_M1_MASK + {5, OperandInfo803}, // Inst #9473 = PseudoVSUXSEG4EI16_V_M2_M2 + {6, OperandInfo804}, // Inst #9474 = PseudoVSUXSEG4EI16_V_M2_M2_MASK + {5, OperandInfo805}, // Inst #9475 = PseudoVSUXSEG4EI16_V_M4_M2 + {6, OperandInfo806}, // Inst #9476 = PseudoVSUXSEG4EI16_V_M4_M2_MASK + {5, OperandInfo797}, // Inst #9477 = PseudoVSUXSEG4EI16_V_MF2_M1 + {6, OperandInfo798}, // Inst #9478 = PseudoVSUXSEG4EI16_V_MF2_M1_MASK + {5, OperandInfo799}, // Inst #9479 = PseudoVSUXSEG4EI16_V_MF2_M2 + {6, OperandInfo800}, // Inst #9480 = PseudoVSUXSEG4EI16_V_MF2_M2_MASK + {5, OperandInfo797}, // Inst #9481 = PseudoVSUXSEG4EI16_V_MF2_MF2 + {6, OperandInfo798}, // Inst #9482 = PseudoVSUXSEG4EI16_V_MF2_MF2_MASK + {5, OperandInfo797}, // Inst #9483 = PseudoVSUXSEG4EI16_V_MF2_MF4 + {6, OperandInfo798}, // Inst #9484 = PseudoVSUXSEG4EI16_V_MF2_MF4_MASK + {5, OperandInfo797}, // Inst #9485 = PseudoVSUXSEG4EI16_V_MF4_M1 + {6, OperandInfo798}, // Inst #9486 = PseudoVSUXSEG4EI16_V_MF4_M1_MASK + {5, OperandInfo797}, // Inst #9487 = PseudoVSUXSEG4EI16_V_MF4_MF2 + {6, OperandInfo798}, // Inst #9488 = PseudoVSUXSEG4EI16_V_MF4_MF2_MASK + {5, OperandInfo797}, // Inst #9489 = PseudoVSUXSEG4EI16_V_MF4_MF4 + {6, OperandInfo798}, // Inst #9490 = PseudoVSUXSEG4EI16_V_MF4_MF4_MASK + {5, OperandInfo797}, // Inst #9491 = PseudoVSUXSEG4EI16_V_MF4_MF8 + {6, OperandInfo798}, // Inst #9492 = PseudoVSUXSEG4EI16_V_MF4_MF8_MASK + {5, OperandInfo797}, // Inst #9493 = PseudoVSUXSEG4EI32_V_M1_M1 + {6, OperandInfo798}, // Inst #9494 = PseudoVSUXSEG4EI32_V_M1_M1_MASK + {5, OperandInfo799}, // Inst #9495 = PseudoVSUXSEG4EI32_V_M1_M2 + {6, OperandInfo800}, // Inst #9496 = PseudoVSUXSEG4EI32_V_M1_M2_MASK + {5, OperandInfo797}, // Inst #9497 = PseudoVSUXSEG4EI32_V_M1_MF2 + {6, OperandInfo798}, // Inst #9498 = PseudoVSUXSEG4EI32_V_M1_MF2_MASK + {5, OperandInfo797}, // Inst #9499 = PseudoVSUXSEG4EI32_V_M1_MF4 + {6, OperandInfo798}, // Inst #9500 = PseudoVSUXSEG4EI32_V_M1_MF4_MASK + {5, OperandInfo801}, // Inst #9501 = PseudoVSUXSEG4EI32_V_M2_M1 + {6, OperandInfo802}, // Inst #9502 = PseudoVSUXSEG4EI32_V_M2_M1_MASK + {5, OperandInfo803}, // Inst #9503 = PseudoVSUXSEG4EI32_V_M2_M2 + {6, OperandInfo804}, // Inst #9504 = PseudoVSUXSEG4EI32_V_M2_M2_MASK + {5, OperandInfo801}, // Inst #9505 = PseudoVSUXSEG4EI32_V_M2_MF2 + {6, OperandInfo802}, // Inst #9506 = PseudoVSUXSEG4EI32_V_M2_MF2_MASK + {5, OperandInfo807}, // Inst #9507 = PseudoVSUXSEG4EI32_V_M4_M1 + {6, OperandInfo808}, // Inst #9508 = PseudoVSUXSEG4EI32_V_M4_M1_MASK + {5, OperandInfo805}, // Inst #9509 = PseudoVSUXSEG4EI32_V_M4_M2 + {6, OperandInfo806}, // Inst #9510 = PseudoVSUXSEG4EI32_V_M4_M2_MASK + {5, OperandInfo809}, // Inst #9511 = PseudoVSUXSEG4EI32_V_M8_M2 + {6, OperandInfo810}, // Inst #9512 = PseudoVSUXSEG4EI32_V_M8_M2_MASK + {5, OperandInfo797}, // Inst #9513 = PseudoVSUXSEG4EI32_V_MF2_M1 + {6, OperandInfo798}, // Inst #9514 = PseudoVSUXSEG4EI32_V_MF2_M1_MASK + {5, OperandInfo797}, // Inst #9515 = PseudoVSUXSEG4EI32_V_MF2_MF2 + {6, OperandInfo798}, // Inst #9516 = PseudoVSUXSEG4EI32_V_MF2_MF2_MASK + {5, OperandInfo797}, // Inst #9517 = PseudoVSUXSEG4EI32_V_MF2_MF4 + {6, OperandInfo798}, // Inst #9518 = PseudoVSUXSEG4EI32_V_MF2_MF4_MASK + {5, OperandInfo797}, // Inst #9519 = PseudoVSUXSEG4EI32_V_MF2_MF8 + {6, OperandInfo798}, // Inst #9520 = PseudoVSUXSEG4EI32_V_MF2_MF8_MASK + {5, OperandInfo797}, // Inst #9521 = PseudoVSUXSEG4EI64_V_M1_M1 + {6, OperandInfo798}, // Inst #9522 = PseudoVSUXSEG4EI64_V_M1_M1_MASK + {5, OperandInfo797}, // Inst #9523 = PseudoVSUXSEG4EI64_V_M1_MF2 + {6, OperandInfo798}, // Inst #9524 = PseudoVSUXSEG4EI64_V_M1_MF2_MASK + {5, OperandInfo797}, // Inst #9525 = PseudoVSUXSEG4EI64_V_M1_MF4 + {6, OperandInfo798}, // Inst #9526 = PseudoVSUXSEG4EI64_V_M1_MF4_MASK + {5, OperandInfo797}, // Inst #9527 = PseudoVSUXSEG4EI64_V_M1_MF8 + {6, OperandInfo798}, // Inst #9528 = PseudoVSUXSEG4EI64_V_M1_MF8_MASK + {5, OperandInfo801}, // Inst #9529 = PseudoVSUXSEG4EI64_V_M2_M1 + {6, OperandInfo802}, // Inst #9530 = PseudoVSUXSEG4EI64_V_M2_M1_MASK + {5, OperandInfo803}, // Inst #9531 = PseudoVSUXSEG4EI64_V_M2_M2 + {6, OperandInfo804}, // Inst #9532 = PseudoVSUXSEG4EI64_V_M2_M2_MASK + {5, OperandInfo801}, // Inst #9533 = PseudoVSUXSEG4EI64_V_M2_MF2 + {6, OperandInfo802}, // Inst #9534 = PseudoVSUXSEG4EI64_V_M2_MF2_MASK + {5, OperandInfo801}, // Inst #9535 = PseudoVSUXSEG4EI64_V_M2_MF4 + {6, OperandInfo802}, // Inst #9536 = PseudoVSUXSEG4EI64_V_M2_MF4_MASK + {5, OperandInfo807}, // Inst #9537 = PseudoVSUXSEG4EI64_V_M4_M1 + {6, OperandInfo808}, // Inst #9538 = PseudoVSUXSEG4EI64_V_M4_M1_MASK + {5, OperandInfo805}, // Inst #9539 = PseudoVSUXSEG4EI64_V_M4_M2 + {6, OperandInfo806}, // Inst #9540 = PseudoVSUXSEG4EI64_V_M4_M2_MASK + {5, OperandInfo807}, // Inst #9541 = PseudoVSUXSEG4EI64_V_M4_MF2 + {6, OperandInfo808}, // Inst #9542 = PseudoVSUXSEG4EI64_V_M4_MF2_MASK + {5, OperandInfo811}, // Inst #9543 = PseudoVSUXSEG4EI64_V_M8_M1 + {6, OperandInfo812}, // Inst #9544 = PseudoVSUXSEG4EI64_V_M8_M1_MASK + {5, OperandInfo809}, // Inst #9545 = PseudoVSUXSEG4EI64_V_M8_M2 + {6, OperandInfo810}, // Inst #9546 = PseudoVSUXSEG4EI64_V_M8_M2_MASK + {5, OperandInfo797}, // Inst #9547 = PseudoVSUXSEG4EI8_V_M1_M1 + {6, OperandInfo798}, // Inst #9548 = PseudoVSUXSEG4EI8_V_M1_M1_MASK + {5, OperandInfo799}, // Inst #9549 = PseudoVSUXSEG4EI8_V_M1_M2 + {6, OperandInfo800}, // Inst #9550 = PseudoVSUXSEG4EI8_V_M1_M2_MASK + {5, OperandInfo803}, // Inst #9551 = PseudoVSUXSEG4EI8_V_M2_M2 + {6, OperandInfo804}, // Inst #9552 = PseudoVSUXSEG4EI8_V_M2_M2_MASK + {5, OperandInfo797}, // Inst #9553 = PseudoVSUXSEG4EI8_V_MF2_M1 + {6, OperandInfo798}, // Inst #9554 = PseudoVSUXSEG4EI8_V_MF2_M1_MASK + {5, OperandInfo799}, // Inst #9555 = PseudoVSUXSEG4EI8_V_MF2_M2 + {6, OperandInfo800}, // Inst #9556 = PseudoVSUXSEG4EI8_V_MF2_M2_MASK + {5, OperandInfo797}, // Inst #9557 = PseudoVSUXSEG4EI8_V_MF2_MF2 + {6, OperandInfo798}, // Inst #9558 = PseudoVSUXSEG4EI8_V_MF2_MF2_MASK + {5, OperandInfo797}, // Inst #9559 = PseudoVSUXSEG4EI8_V_MF4_M1 + {6, OperandInfo798}, // Inst #9560 = PseudoVSUXSEG4EI8_V_MF4_M1_MASK + {5, OperandInfo799}, // Inst #9561 = PseudoVSUXSEG4EI8_V_MF4_M2 + {6, OperandInfo800}, // Inst #9562 = PseudoVSUXSEG4EI8_V_MF4_M2_MASK + {5, OperandInfo797}, // Inst #9563 = PseudoVSUXSEG4EI8_V_MF4_MF2 + {6, OperandInfo798}, // Inst #9564 = PseudoVSUXSEG4EI8_V_MF4_MF2_MASK + {5, OperandInfo797}, // Inst #9565 = PseudoVSUXSEG4EI8_V_MF4_MF4 + {6, OperandInfo798}, // Inst #9566 = PseudoVSUXSEG4EI8_V_MF4_MF4_MASK + {5, OperandInfo797}, // Inst #9567 = PseudoVSUXSEG4EI8_V_MF8_M1 + {6, OperandInfo798}, // Inst #9568 = PseudoVSUXSEG4EI8_V_MF8_M1_MASK + {5, OperandInfo797}, // Inst #9569 = PseudoVSUXSEG4EI8_V_MF8_MF2 + {6, OperandInfo798}, // Inst #9570 = PseudoVSUXSEG4EI8_V_MF8_MF2_MASK + {5, OperandInfo797}, // Inst #9571 = PseudoVSUXSEG4EI8_V_MF8_MF4 + {6, OperandInfo798}, // Inst #9572 = PseudoVSUXSEG4EI8_V_MF8_MF4_MASK + {5, OperandInfo797}, // Inst #9573 = PseudoVSUXSEG4EI8_V_MF8_MF8 + {6, OperandInfo798}, // Inst #9574 = PseudoVSUXSEG4EI8_V_MF8_MF8_MASK + {5, OperandInfo813}, // Inst #9575 = PseudoVSUXSEG5EI16_V_M1_M1 + {6, OperandInfo814}, // Inst #9576 = PseudoVSUXSEG5EI16_V_M1_M1_MASK + {5, OperandInfo813}, // Inst #9577 = PseudoVSUXSEG5EI16_V_M1_MF2 + {6, OperandInfo814}, // Inst #9578 = PseudoVSUXSEG5EI16_V_M1_MF2_MASK + {5, OperandInfo815}, // Inst #9579 = PseudoVSUXSEG5EI16_V_M2_M1 + {6, OperandInfo816}, // Inst #9580 = PseudoVSUXSEG5EI16_V_M2_M1_MASK + {5, OperandInfo813}, // Inst #9581 = PseudoVSUXSEG5EI16_V_MF2_M1 + {6, OperandInfo814}, // Inst #9582 = PseudoVSUXSEG5EI16_V_MF2_M1_MASK + {5, OperandInfo813}, // Inst #9583 = PseudoVSUXSEG5EI16_V_MF2_MF2 + {6, OperandInfo814}, // Inst #9584 = PseudoVSUXSEG5EI16_V_MF2_MF2_MASK + {5, OperandInfo813}, // Inst #9585 = PseudoVSUXSEG5EI16_V_MF2_MF4 + {6, OperandInfo814}, // Inst #9586 = PseudoVSUXSEG5EI16_V_MF2_MF4_MASK + {5, OperandInfo813}, // Inst #9587 = PseudoVSUXSEG5EI16_V_MF4_M1 + {6, OperandInfo814}, // Inst #9588 = PseudoVSUXSEG5EI16_V_MF4_M1_MASK + {5, OperandInfo813}, // Inst #9589 = PseudoVSUXSEG5EI16_V_MF4_MF2 + {6, OperandInfo814}, // Inst #9590 = PseudoVSUXSEG5EI16_V_MF4_MF2_MASK + {5, OperandInfo813}, // Inst #9591 = PseudoVSUXSEG5EI16_V_MF4_MF4 + {6, OperandInfo814}, // Inst #9592 = PseudoVSUXSEG5EI16_V_MF4_MF4_MASK + {5, OperandInfo813}, // Inst #9593 = PseudoVSUXSEG5EI16_V_MF4_MF8 + {6, OperandInfo814}, // Inst #9594 = PseudoVSUXSEG5EI16_V_MF4_MF8_MASK + {5, OperandInfo813}, // Inst #9595 = PseudoVSUXSEG5EI32_V_M1_M1 + {6, OperandInfo814}, // Inst #9596 = PseudoVSUXSEG5EI32_V_M1_M1_MASK + {5, OperandInfo813}, // Inst #9597 = PseudoVSUXSEG5EI32_V_M1_MF2 + {6, OperandInfo814}, // Inst #9598 = PseudoVSUXSEG5EI32_V_M1_MF2_MASK + {5, OperandInfo813}, // Inst #9599 = PseudoVSUXSEG5EI32_V_M1_MF4 + {6, OperandInfo814}, // Inst #9600 = PseudoVSUXSEG5EI32_V_M1_MF4_MASK + {5, OperandInfo815}, // Inst #9601 = PseudoVSUXSEG5EI32_V_M2_M1 + {6, OperandInfo816}, // Inst #9602 = PseudoVSUXSEG5EI32_V_M2_M1_MASK + {5, OperandInfo815}, // Inst #9603 = PseudoVSUXSEG5EI32_V_M2_MF2 + {6, OperandInfo816}, // Inst #9604 = PseudoVSUXSEG5EI32_V_M2_MF2_MASK + {5, OperandInfo817}, // Inst #9605 = PseudoVSUXSEG5EI32_V_M4_M1 + {6, OperandInfo818}, // Inst #9606 = PseudoVSUXSEG5EI32_V_M4_M1_MASK + {5, OperandInfo813}, // Inst #9607 = PseudoVSUXSEG5EI32_V_MF2_M1 + {6, OperandInfo814}, // Inst #9608 = PseudoVSUXSEG5EI32_V_MF2_M1_MASK + {5, OperandInfo813}, // Inst #9609 = PseudoVSUXSEG5EI32_V_MF2_MF2 + {6, OperandInfo814}, // Inst #9610 = PseudoVSUXSEG5EI32_V_MF2_MF2_MASK + {5, OperandInfo813}, // Inst #9611 = PseudoVSUXSEG5EI32_V_MF2_MF4 + {6, OperandInfo814}, // Inst #9612 = PseudoVSUXSEG5EI32_V_MF2_MF4_MASK + {5, OperandInfo813}, // Inst #9613 = PseudoVSUXSEG5EI32_V_MF2_MF8 + {6, OperandInfo814}, // Inst #9614 = PseudoVSUXSEG5EI32_V_MF2_MF8_MASK + {5, OperandInfo813}, // Inst #9615 = PseudoVSUXSEG5EI64_V_M1_M1 + {6, OperandInfo814}, // Inst #9616 = PseudoVSUXSEG5EI64_V_M1_M1_MASK + {5, OperandInfo813}, // Inst #9617 = PseudoVSUXSEG5EI64_V_M1_MF2 + {6, OperandInfo814}, // Inst #9618 = PseudoVSUXSEG5EI64_V_M1_MF2_MASK + {5, OperandInfo813}, // Inst #9619 = PseudoVSUXSEG5EI64_V_M1_MF4 + {6, OperandInfo814}, // Inst #9620 = PseudoVSUXSEG5EI64_V_M1_MF4_MASK + {5, OperandInfo813}, // Inst #9621 = PseudoVSUXSEG5EI64_V_M1_MF8 + {6, OperandInfo814}, // Inst #9622 = PseudoVSUXSEG5EI64_V_M1_MF8_MASK + {5, OperandInfo815}, // Inst #9623 = PseudoVSUXSEG5EI64_V_M2_M1 + {6, OperandInfo816}, // Inst #9624 = PseudoVSUXSEG5EI64_V_M2_M1_MASK + {5, OperandInfo815}, // Inst #9625 = PseudoVSUXSEG5EI64_V_M2_MF2 + {6, OperandInfo816}, // Inst #9626 = PseudoVSUXSEG5EI64_V_M2_MF2_MASK + {5, OperandInfo815}, // Inst #9627 = PseudoVSUXSEG5EI64_V_M2_MF4 + {6, OperandInfo816}, // Inst #9628 = PseudoVSUXSEG5EI64_V_M2_MF4_MASK + {5, OperandInfo817}, // Inst #9629 = PseudoVSUXSEG5EI64_V_M4_M1 + {6, OperandInfo818}, // Inst #9630 = PseudoVSUXSEG5EI64_V_M4_M1_MASK + {5, OperandInfo817}, // Inst #9631 = PseudoVSUXSEG5EI64_V_M4_MF2 + {6, OperandInfo818}, // Inst #9632 = PseudoVSUXSEG5EI64_V_M4_MF2_MASK + {5, OperandInfo819}, // Inst #9633 = PseudoVSUXSEG5EI64_V_M8_M1 + {6, OperandInfo820}, // Inst #9634 = PseudoVSUXSEG5EI64_V_M8_M1_MASK + {5, OperandInfo813}, // Inst #9635 = PseudoVSUXSEG5EI8_V_M1_M1 + {6, OperandInfo814}, // Inst #9636 = PseudoVSUXSEG5EI8_V_M1_M1_MASK + {5, OperandInfo813}, // Inst #9637 = PseudoVSUXSEG5EI8_V_MF2_M1 + {6, OperandInfo814}, // Inst #9638 = PseudoVSUXSEG5EI8_V_MF2_M1_MASK + {5, OperandInfo813}, // Inst #9639 = PseudoVSUXSEG5EI8_V_MF2_MF2 + {6, OperandInfo814}, // Inst #9640 = PseudoVSUXSEG5EI8_V_MF2_MF2_MASK + {5, OperandInfo813}, // Inst #9641 = PseudoVSUXSEG5EI8_V_MF4_M1 + {6, OperandInfo814}, // Inst #9642 = PseudoVSUXSEG5EI8_V_MF4_M1_MASK + {5, OperandInfo813}, // Inst #9643 = PseudoVSUXSEG5EI8_V_MF4_MF2 + {6, OperandInfo814}, // Inst #9644 = PseudoVSUXSEG5EI8_V_MF4_MF2_MASK + {5, OperandInfo813}, // Inst #9645 = PseudoVSUXSEG5EI8_V_MF4_MF4 + {6, OperandInfo814}, // Inst #9646 = PseudoVSUXSEG5EI8_V_MF4_MF4_MASK + {5, OperandInfo813}, // Inst #9647 = PseudoVSUXSEG5EI8_V_MF8_M1 + {6, OperandInfo814}, // Inst #9648 = PseudoVSUXSEG5EI8_V_MF8_M1_MASK + {5, OperandInfo813}, // Inst #9649 = PseudoVSUXSEG5EI8_V_MF8_MF2 + {6, OperandInfo814}, // Inst #9650 = PseudoVSUXSEG5EI8_V_MF8_MF2_MASK + {5, OperandInfo813}, // Inst #9651 = PseudoVSUXSEG5EI8_V_MF8_MF4 + {6, OperandInfo814}, // Inst #9652 = PseudoVSUXSEG5EI8_V_MF8_MF4_MASK + {5, OperandInfo813}, // Inst #9653 = PseudoVSUXSEG5EI8_V_MF8_MF8 + {6, OperandInfo814}, // Inst #9654 = PseudoVSUXSEG5EI8_V_MF8_MF8_MASK + {5, OperandInfo821}, // Inst #9655 = PseudoVSUXSEG6EI16_V_M1_M1 + {6, OperandInfo822}, // Inst #9656 = PseudoVSUXSEG6EI16_V_M1_M1_MASK + {5, OperandInfo821}, // Inst #9657 = PseudoVSUXSEG6EI16_V_M1_MF2 + {6, OperandInfo822}, // Inst #9658 = PseudoVSUXSEG6EI16_V_M1_MF2_MASK + {5, OperandInfo823}, // Inst #9659 = PseudoVSUXSEG6EI16_V_M2_M1 + {6, OperandInfo824}, // Inst #9660 = PseudoVSUXSEG6EI16_V_M2_M1_MASK + {5, OperandInfo821}, // Inst #9661 = PseudoVSUXSEG6EI16_V_MF2_M1 + {6, OperandInfo822}, // Inst #9662 = PseudoVSUXSEG6EI16_V_MF2_M1_MASK + {5, OperandInfo821}, // Inst #9663 = PseudoVSUXSEG6EI16_V_MF2_MF2 + {6, OperandInfo822}, // Inst #9664 = PseudoVSUXSEG6EI16_V_MF2_MF2_MASK + {5, OperandInfo821}, // Inst #9665 = PseudoVSUXSEG6EI16_V_MF2_MF4 + {6, OperandInfo822}, // Inst #9666 = PseudoVSUXSEG6EI16_V_MF2_MF4_MASK + {5, OperandInfo821}, // Inst #9667 = PseudoVSUXSEG6EI16_V_MF4_M1 + {6, OperandInfo822}, // Inst #9668 = PseudoVSUXSEG6EI16_V_MF4_M1_MASK + {5, OperandInfo821}, // Inst #9669 = PseudoVSUXSEG6EI16_V_MF4_MF2 + {6, OperandInfo822}, // Inst #9670 = PseudoVSUXSEG6EI16_V_MF4_MF2_MASK + {5, OperandInfo821}, // Inst #9671 = PseudoVSUXSEG6EI16_V_MF4_MF4 + {6, OperandInfo822}, // Inst #9672 = PseudoVSUXSEG6EI16_V_MF4_MF4_MASK + {5, OperandInfo821}, // Inst #9673 = PseudoVSUXSEG6EI16_V_MF4_MF8 + {6, OperandInfo822}, // Inst #9674 = PseudoVSUXSEG6EI16_V_MF4_MF8_MASK + {5, OperandInfo821}, // Inst #9675 = PseudoVSUXSEG6EI32_V_M1_M1 + {6, OperandInfo822}, // Inst #9676 = PseudoVSUXSEG6EI32_V_M1_M1_MASK + {5, OperandInfo821}, // Inst #9677 = PseudoVSUXSEG6EI32_V_M1_MF2 + {6, OperandInfo822}, // Inst #9678 = PseudoVSUXSEG6EI32_V_M1_MF2_MASK + {5, OperandInfo821}, // Inst #9679 = PseudoVSUXSEG6EI32_V_M1_MF4 + {6, OperandInfo822}, // Inst #9680 = PseudoVSUXSEG6EI32_V_M1_MF4_MASK + {5, OperandInfo823}, // Inst #9681 = PseudoVSUXSEG6EI32_V_M2_M1 + {6, OperandInfo824}, // Inst #9682 = PseudoVSUXSEG6EI32_V_M2_M1_MASK + {5, OperandInfo823}, // Inst #9683 = PseudoVSUXSEG6EI32_V_M2_MF2 + {6, OperandInfo824}, // Inst #9684 = PseudoVSUXSEG6EI32_V_M2_MF2_MASK + {5, OperandInfo825}, // Inst #9685 = PseudoVSUXSEG6EI32_V_M4_M1 + {6, OperandInfo826}, // Inst #9686 = PseudoVSUXSEG6EI32_V_M4_M1_MASK + {5, OperandInfo821}, // Inst #9687 = PseudoVSUXSEG6EI32_V_MF2_M1 + {6, OperandInfo822}, // Inst #9688 = PseudoVSUXSEG6EI32_V_MF2_M1_MASK + {5, OperandInfo821}, // Inst #9689 = PseudoVSUXSEG6EI32_V_MF2_MF2 + {6, OperandInfo822}, // Inst #9690 = PseudoVSUXSEG6EI32_V_MF2_MF2_MASK + {5, OperandInfo821}, // Inst #9691 = PseudoVSUXSEG6EI32_V_MF2_MF4 + {6, OperandInfo822}, // Inst #9692 = PseudoVSUXSEG6EI32_V_MF2_MF4_MASK + {5, OperandInfo821}, // Inst #9693 = PseudoVSUXSEG6EI32_V_MF2_MF8 + {6, OperandInfo822}, // Inst #9694 = PseudoVSUXSEG6EI32_V_MF2_MF8_MASK + {5, OperandInfo821}, // Inst #9695 = PseudoVSUXSEG6EI64_V_M1_M1 + {6, OperandInfo822}, // Inst #9696 = PseudoVSUXSEG6EI64_V_M1_M1_MASK + {5, OperandInfo821}, // Inst #9697 = PseudoVSUXSEG6EI64_V_M1_MF2 + {6, OperandInfo822}, // Inst #9698 = PseudoVSUXSEG6EI64_V_M1_MF2_MASK + {5, OperandInfo821}, // Inst #9699 = PseudoVSUXSEG6EI64_V_M1_MF4 + {6, OperandInfo822}, // Inst #9700 = PseudoVSUXSEG6EI64_V_M1_MF4_MASK + {5, OperandInfo821}, // Inst #9701 = PseudoVSUXSEG6EI64_V_M1_MF8 + {6, OperandInfo822}, // Inst #9702 = PseudoVSUXSEG6EI64_V_M1_MF8_MASK + {5, OperandInfo823}, // Inst #9703 = PseudoVSUXSEG6EI64_V_M2_M1 + {6, OperandInfo824}, // Inst #9704 = PseudoVSUXSEG6EI64_V_M2_M1_MASK + {5, OperandInfo823}, // Inst #9705 = PseudoVSUXSEG6EI64_V_M2_MF2 + {6, OperandInfo824}, // Inst #9706 = PseudoVSUXSEG6EI64_V_M2_MF2_MASK + {5, OperandInfo823}, // Inst #9707 = PseudoVSUXSEG6EI64_V_M2_MF4 + {6, OperandInfo824}, // Inst #9708 = PseudoVSUXSEG6EI64_V_M2_MF4_MASK + {5, OperandInfo825}, // Inst #9709 = PseudoVSUXSEG6EI64_V_M4_M1 + {6, OperandInfo826}, // Inst #9710 = PseudoVSUXSEG6EI64_V_M4_M1_MASK + {5, OperandInfo825}, // Inst #9711 = PseudoVSUXSEG6EI64_V_M4_MF2 + {6, OperandInfo826}, // Inst #9712 = PseudoVSUXSEG6EI64_V_M4_MF2_MASK + {5, OperandInfo827}, // Inst #9713 = PseudoVSUXSEG6EI64_V_M8_M1 + {6, OperandInfo828}, // Inst #9714 = PseudoVSUXSEG6EI64_V_M8_M1_MASK + {5, OperandInfo821}, // Inst #9715 = PseudoVSUXSEG6EI8_V_M1_M1 + {6, OperandInfo822}, // Inst #9716 = PseudoVSUXSEG6EI8_V_M1_M1_MASK + {5, OperandInfo821}, // Inst #9717 = PseudoVSUXSEG6EI8_V_MF2_M1 + {6, OperandInfo822}, // Inst #9718 = PseudoVSUXSEG6EI8_V_MF2_M1_MASK + {5, OperandInfo821}, // Inst #9719 = PseudoVSUXSEG6EI8_V_MF2_MF2 + {6, OperandInfo822}, // Inst #9720 = PseudoVSUXSEG6EI8_V_MF2_MF2_MASK + {5, OperandInfo821}, // Inst #9721 = PseudoVSUXSEG6EI8_V_MF4_M1 + {6, OperandInfo822}, // Inst #9722 = PseudoVSUXSEG6EI8_V_MF4_M1_MASK + {5, OperandInfo821}, // Inst #9723 = PseudoVSUXSEG6EI8_V_MF4_MF2 + {6, OperandInfo822}, // Inst #9724 = PseudoVSUXSEG6EI8_V_MF4_MF2_MASK + {5, OperandInfo821}, // Inst #9725 = PseudoVSUXSEG6EI8_V_MF4_MF4 + {6, OperandInfo822}, // Inst #9726 = PseudoVSUXSEG6EI8_V_MF4_MF4_MASK + {5, OperandInfo821}, // Inst #9727 = PseudoVSUXSEG6EI8_V_MF8_M1 + {6, OperandInfo822}, // Inst #9728 = PseudoVSUXSEG6EI8_V_MF8_M1_MASK + {5, OperandInfo821}, // Inst #9729 = PseudoVSUXSEG6EI8_V_MF8_MF2 + {6, OperandInfo822}, // Inst #9730 = PseudoVSUXSEG6EI8_V_MF8_MF2_MASK + {5, OperandInfo821}, // Inst #9731 = PseudoVSUXSEG6EI8_V_MF8_MF4 + {6, OperandInfo822}, // Inst #9732 = PseudoVSUXSEG6EI8_V_MF8_MF4_MASK + {5, OperandInfo821}, // Inst #9733 = PseudoVSUXSEG6EI8_V_MF8_MF8 + {6, OperandInfo822}, // Inst #9734 = PseudoVSUXSEG6EI8_V_MF8_MF8_MASK + {5, OperandInfo829}, // Inst #9735 = PseudoVSUXSEG7EI16_V_M1_M1 + {6, OperandInfo830}, // Inst #9736 = PseudoVSUXSEG7EI16_V_M1_M1_MASK + {5, OperandInfo829}, // Inst #9737 = PseudoVSUXSEG7EI16_V_M1_MF2 + {6, OperandInfo830}, // Inst #9738 = PseudoVSUXSEG7EI16_V_M1_MF2_MASK + {5, OperandInfo831}, // Inst #9739 = PseudoVSUXSEG7EI16_V_M2_M1 + {6, OperandInfo832}, // Inst #9740 = PseudoVSUXSEG7EI16_V_M2_M1_MASK + {5, OperandInfo829}, // Inst #9741 = PseudoVSUXSEG7EI16_V_MF2_M1 + {6, OperandInfo830}, // Inst #9742 = PseudoVSUXSEG7EI16_V_MF2_M1_MASK + {5, OperandInfo829}, // Inst #9743 = PseudoVSUXSEG7EI16_V_MF2_MF2 + {6, OperandInfo830}, // Inst #9744 = PseudoVSUXSEG7EI16_V_MF2_MF2_MASK + {5, OperandInfo829}, // Inst #9745 = PseudoVSUXSEG7EI16_V_MF2_MF4 + {6, OperandInfo830}, // Inst #9746 = PseudoVSUXSEG7EI16_V_MF2_MF4_MASK + {5, OperandInfo829}, // Inst #9747 = PseudoVSUXSEG7EI16_V_MF4_M1 + {6, OperandInfo830}, // Inst #9748 = PseudoVSUXSEG7EI16_V_MF4_M1_MASK + {5, OperandInfo829}, // Inst #9749 = PseudoVSUXSEG7EI16_V_MF4_MF2 + {6, OperandInfo830}, // Inst #9750 = PseudoVSUXSEG7EI16_V_MF4_MF2_MASK + {5, OperandInfo829}, // Inst #9751 = PseudoVSUXSEG7EI16_V_MF4_MF4 + {6, OperandInfo830}, // Inst #9752 = PseudoVSUXSEG7EI16_V_MF4_MF4_MASK + {5, OperandInfo829}, // Inst #9753 = PseudoVSUXSEG7EI16_V_MF4_MF8 + {6, OperandInfo830}, // Inst #9754 = PseudoVSUXSEG7EI16_V_MF4_MF8_MASK + {5, OperandInfo829}, // Inst #9755 = PseudoVSUXSEG7EI32_V_M1_M1 + {6, OperandInfo830}, // Inst #9756 = PseudoVSUXSEG7EI32_V_M1_M1_MASK + {5, OperandInfo829}, // Inst #9757 = PseudoVSUXSEG7EI32_V_M1_MF2 + {6, OperandInfo830}, // Inst #9758 = PseudoVSUXSEG7EI32_V_M1_MF2_MASK + {5, OperandInfo829}, // Inst #9759 = PseudoVSUXSEG7EI32_V_M1_MF4 + {6, OperandInfo830}, // Inst #9760 = PseudoVSUXSEG7EI32_V_M1_MF4_MASK + {5, OperandInfo831}, // Inst #9761 = PseudoVSUXSEG7EI32_V_M2_M1 + {6, OperandInfo832}, // Inst #9762 = PseudoVSUXSEG7EI32_V_M2_M1_MASK + {5, OperandInfo831}, // Inst #9763 = PseudoVSUXSEG7EI32_V_M2_MF2 + {6, OperandInfo832}, // Inst #9764 = PseudoVSUXSEG7EI32_V_M2_MF2_MASK + {5, OperandInfo833}, // Inst #9765 = PseudoVSUXSEG7EI32_V_M4_M1 + {6, OperandInfo834}, // Inst #9766 = PseudoVSUXSEG7EI32_V_M4_M1_MASK + {5, OperandInfo829}, // Inst #9767 = PseudoVSUXSEG7EI32_V_MF2_M1 + {6, OperandInfo830}, // Inst #9768 = PseudoVSUXSEG7EI32_V_MF2_M1_MASK + {5, OperandInfo829}, // Inst #9769 = PseudoVSUXSEG7EI32_V_MF2_MF2 + {6, OperandInfo830}, // Inst #9770 = PseudoVSUXSEG7EI32_V_MF2_MF2_MASK + {5, OperandInfo829}, // Inst #9771 = PseudoVSUXSEG7EI32_V_MF2_MF4 + {6, OperandInfo830}, // Inst #9772 = PseudoVSUXSEG7EI32_V_MF2_MF4_MASK + {5, OperandInfo829}, // Inst #9773 = PseudoVSUXSEG7EI32_V_MF2_MF8 + {6, OperandInfo830}, // Inst #9774 = PseudoVSUXSEG7EI32_V_MF2_MF8_MASK + {5, OperandInfo829}, // Inst #9775 = PseudoVSUXSEG7EI64_V_M1_M1 + {6, OperandInfo830}, // Inst #9776 = PseudoVSUXSEG7EI64_V_M1_M1_MASK + {5, OperandInfo829}, // Inst #9777 = PseudoVSUXSEG7EI64_V_M1_MF2 + {6, OperandInfo830}, // Inst #9778 = PseudoVSUXSEG7EI64_V_M1_MF2_MASK + {5, OperandInfo829}, // Inst #9779 = PseudoVSUXSEG7EI64_V_M1_MF4 + {6, OperandInfo830}, // Inst #9780 = PseudoVSUXSEG7EI64_V_M1_MF4_MASK + {5, OperandInfo829}, // Inst #9781 = PseudoVSUXSEG7EI64_V_M1_MF8 + {6, OperandInfo830}, // Inst #9782 = PseudoVSUXSEG7EI64_V_M1_MF8_MASK + {5, OperandInfo831}, // Inst #9783 = PseudoVSUXSEG7EI64_V_M2_M1 + {6, OperandInfo832}, // Inst #9784 = PseudoVSUXSEG7EI64_V_M2_M1_MASK + {5, OperandInfo831}, // Inst #9785 = PseudoVSUXSEG7EI64_V_M2_MF2 + {6, OperandInfo832}, // Inst #9786 = PseudoVSUXSEG7EI64_V_M2_MF2_MASK + {5, OperandInfo831}, // Inst #9787 = PseudoVSUXSEG7EI64_V_M2_MF4 + {6, OperandInfo832}, // Inst #9788 = PseudoVSUXSEG7EI64_V_M2_MF4_MASK + {5, OperandInfo833}, // Inst #9789 = PseudoVSUXSEG7EI64_V_M4_M1 + {6, OperandInfo834}, // Inst #9790 = PseudoVSUXSEG7EI64_V_M4_M1_MASK + {5, OperandInfo833}, // Inst #9791 = PseudoVSUXSEG7EI64_V_M4_MF2 + {6, OperandInfo834}, // Inst #9792 = PseudoVSUXSEG7EI64_V_M4_MF2_MASK + {5, OperandInfo835}, // Inst #9793 = PseudoVSUXSEG7EI64_V_M8_M1 + {6, OperandInfo836}, // Inst #9794 = PseudoVSUXSEG7EI64_V_M8_M1_MASK + {5, OperandInfo829}, // Inst #9795 = PseudoVSUXSEG7EI8_V_M1_M1 + {6, OperandInfo830}, // Inst #9796 = PseudoVSUXSEG7EI8_V_M1_M1_MASK + {5, OperandInfo829}, // Inst #9797 = PseudoVSUXSEG7EI8_V_MF2_M1 + {6, OperandInfo830}, // Inst #9798 = PseudoVSUXSEG7EI8_V_MF2_M1_MASK + {5, OperandInfo829}, // Inst #9799 = PseudoVSUXSEG7EI8_V_MF2_MF2 + {6, OperandInfo830}, // Inst #9800 = PseudoVSUXSEG7EI8_V_MF2_MF2_MASK + {5, OperandInfo829}, // Inst #9801 = PseudoVSUXSEG7EI8_V_MF4_M1 + {6, OperandInfo830}, // Inst #9802 = PseudoVSUXSEG7EI8_V_MF4_M1_MASK + {5, OperandInfo829}, // Inst #9803 = PseudoVSUXSEG7EI8_V_MF4_MF2 + {6, OperandInfo830}, // Inst #9804 = PseudoVSUXSEG7EI8_V_MF4_MF2_MASK + {5, OperandInfo829}, // Inst #9805 = PseudoVSUXSEG7EI8_V_MF4_MF4 + {6, OperandInfo830}, // Inst #9806 = PseudoVSUXSEG7EI8_V_MF4_MF4_MASK + {5, OperandInfo829}, // Inst #9807 = PseudoVSUXSEG7EI8_V_MF8_M1 + {6, OperandInfo830}, // Inst #9808 = PseudoVSUXSEG7EI8_V_MF8_M1_MASK + {5, OperandInfo829}, // Inst #9809 = PseudoVSUXSEG7EI8_V_MF8_MF2 + {6, OperandInfo830}, // Inst #9810 = PseudoVSUXSEG7EI8_V_MF8_MF2_MASK + {5, OperandInfo829}, // Inst #9811 = PseudoVSUXSEG7EI8_V_MF8_MF4 + {6, OperandInfo830}, // Inst #9812 = PseudoVSUXSEG7EI8_V_MF8_MF4_MASK + {5, OperandInfo829}, // Inst #9813 = PseudoVSUXSEG7EI8_V_MF8_MF8 + {6, OperandInfo830}, // Inst #9814 = PseudoVSUXSEG7EI8_V_MF8_MF8_MASK + {5, OperandInfo837}, // Inst #9815 = PseudoVSUXSEG8EI16_V_M1_M1 + {6, OperandInfo838}, // Inst #9816 = PseudoVSUXSEG8EI16_V_M1_M1_MASK + {5, OperandInfo837}, // Inst #9817 = PseudoVSUXSEG8EI16_V_M1_MF2 + {6, OperandInfo838}, // Inst #9818 = PseudoVSUXSEG8EI16_V_M1_MF2_MASK + {5, OperandInfo839}, // Inst #9819 = PseudoVSUXSEG8EI16_V_M2_M1 + {6, OperandInfo840}, // Inst #9820 = PseudoVSUXSEG8EI16_V_M2_M1_MASK + {5, OperandInfo837}, // Inst #9821 = PseudoVSUXSEG8EI16_V_MF2_M1 + {6, OperandInfo838}, // Inst #9822 = PseudoVSUXSEG8EI16_V_MF2_M1_MASK + {5, OperandInfo837}, // Inst #9823 = PseudoVSUXSEG8EI16_V_MF2_MF2 + {6, OperandInfo838}, // Inst #9824 = PseudoVSUXSEG8EI16_V_MF2_MF2_MASK + {5, OperandInfo837}, // Inst #9825 = PseudoVSUXSEG8EI16_V_MF2_MF4 + {6, OperandInfo838}, // Inst #9826 = PseudoVSUXSEG8EI16_V_MF2_MF4_MASK + {5, OperandInfo837}, // Inst #9827 = PseudoVSUXSEG8EI16_V_MF4_M1 + {6, OperandInfo838}, // Inst #9828 = PseudoVSUXSEG8EI16_V_MF4_M1_MASK + {5, OperandInfo837}, // Inst #9829 = PseudoVSUXSEG8EI16_V_MF4_MF2 + {6, OperandInfo838}, // Inst #9830 = PseudoVSUXSEG8EI16_V_MF4_MF2_MASK + {5, OperandInfo837}, // Inst #9831 = PseudoVSUXSEG8EI16_V_MF4_MF4 + {6, OperandInfo838}, // Inst #9832 = PseudoVSUXSEG8EI16_V_MF4_MF4_MASK + {5, OperandInfo837}, // Inst #9833 = PseudoVSUXSEG8EI16_V_MF4_MF8 + {6, OperandInfo838}, // Inst #9834 = PseudoVSUXSEG8EI16_V_MF4_MF8_MASK + {5, OperandInfo837}, // Inst #9835 = PseudoVSUXSEG8EI32_V_M1_M1 + {6, OperandInfo838}, // Inst #9836 = PseudoVSUXSEG8EI32_V_M1_M1_MASK + {5, OperandInfo837}, // Inst #9837 = PseudoVSUXSEG8EI32_V_M1_MF2 + {6, OperandInfo838}, // Inst #9838 = PseudoVSUXSEG8EI32_V_M1_MF2_MASK + {5, OperandInfo837}, // Inst #9839 = PseudoVSUXSEG8EI32_V_M1_MF4 + {6, OperandInfo838}, // Inst #9840 = PseudoVSUXSEG8EI32_V_M1_MF4_MASK + {5, OperandInfo839}, // Inst #9841 = PseudoVSUXSEG8EI32_V_M2_M1 + {6, OperandInfo840}, // Inst #9842 = PseudoVSUXSEG8EI32_V_M2_M1_MASK + {5, OperandInfo839}, // Inst #9843 = PseudoVSUXSEG8EI32_V_M2_MF2 + {6, OperandInfo840}, // Inst #9844 = PseudoVSUXSEG8EI32_V_M2_MF2_MASK + {5, OperandInfo841}, // Inst #9845 = PseudoVSUXSEG8EI32_V_M4_M1 + {6, OperandInfo842}, // Inst #9846 = PseudoVSUXSEG8EI32_V_M4_M1_MASK + {5, OperandInfo837}, // Inst #9847 = PseudoVSUXSEG8EI32_V_MF2_M1 + {6, OperandInfo838}, // Inst #9848 = PseudoVSUXSEG8EI32_V_MF2_M1_MASK + {5, OperandInfo837}, // Inst #9849 = PseudoVSUXSEG8EI32_V_MF2_MF2 + {6, OperandInfo838}, // Inst #9850 = PseudoVSUXSEG8EI32_V_MF2_MF2_MASK + {5, OperandInfo837}, // Inst #9851 = PseudoVSUXSEG8EI32_V_MF2_MF4 + {6, OperandInfo838}, // Inst #9852 = PseudoVSUXSEG8EI32_V_MF2_MF4_MASK + {5, OperandInfo837}, // Inst #9853 = PseudoVSUXSEG8EI32_V_MF2_MF8 + {6, OperandInfo838}, // Inst #9854 = PseudoVSUXSEG8EI32_V_MF2_MF8_MASK + {5, OperandInfo837}, // Inst #9855 = PseudoVSUXSEG8EI64_V_M1_M1 + {6, OperandInfo838}, // Inst #9856 = PseudoVSUXSEG8EI64_V_M1_M1_MASK + {5, OperandInfo837}, // Inst #9857 = PseudoVSUXSEG8EI64_V_M1_MF2 + {6, OperandInfo838}, // Inst #9858 = PseudoVSUXSEG8EI64_V_M1_MF2_MASK + {5, OperandInfo837}, // Inst #9859 = PseudoVSUXSEG8EI64_V_M1_MF4 + {6, OperandInfo838}, // Inst #9860 = PseudoVSUXSEG8EI64_V_M1_MF4_MASK + {5, OperandInfo837}, // Inst #9861 = PseudoVSUXSEG8EI64_V_M1_MF8 + {6, OperandInfo838}, // Inst #9862 = PseudoVSUXSEG8EI64_V_M1_MF8_MASK + {5, OperandInfo839}, // Inst #9863 = PseudoVSUXSEG8EI64_V_M2_M1 + {6, OperandInfo840}, // Inst #9864 = PseudoVSUXSEG8EI64_V_M2_M1_MASK + {5, OperandInfo839}, // Inst #9865 = PseudoVSUXSEG8EI64_V_M2_MF2 + {6, OperandInfo840}, // Inst #9866 = PseudoVSUXSEG8EI64_V_M2_MF2_MASK + {5, OperandInfo839}, // Inst #9867 = PseudoVSUXSEG8EI64_V_M2_MF4 + {6, OperandInfo840}, // Inst #9868 = PseudoVSUXSEG8EI64_V_M2_MF4_MASK + {5, OperandInfo841}, // Inst #9869 = PseudoVSUXSEG8EI64_V_M4_M1 + {6, OperandInfo842}, // Inst #9870 = PseudoVSUXSEG8EI64_V_M4_M1_MASK + {5, OperandInfo841}, // Inst #9871 = PseudoVSUXSEG8EI64_V_M4_MF2 + {6, OperandInfo842}, // Inst #9872 = PseudoVSUXSEG8EI64_V_M4_MF2_MASK + {5, OperandInfo843}, // Inst #9873 = PseudoVSUXSEG8EI64_V_M8_M1 + {6, OperandInfo844}, // Inst #9874 = PseudoVSUXSEG8EI64_V_M8_M1_MASK + {5, OperandInfo837}, // Inst #9875 = PseudoVSUXSEG8EI8_V_M1_M1 + {6, OperandInfo838}, // Inst #9876 = PseudoVSUXSEG8EI8_V_M1_M1_MASK + {5, OperandInfo837}, // Inst #9877 = PseudoVSUXSEG8EI8_V_MF2_M1 + {6, OperandInfo838}, // Inst #9878 = PseudoVSUXSEG8EI8_V_MF2_M1_MASK + {5, OperandInfo837}, // Inst #9879 = PseudoVSUXSEG8EI8_V_MF2_MF2 + {6, OperandInfo838}, // Inst #9880 = PseudoVSUXSEG8EI8_V_MF2_MF2_MASK + {5, OperandInfo837}, // Inst #9881 = PseudoVSUXSEG8EI8_V_MF4_M1 + {6, OperandInfo838}, // Inst #9882 = PseudoVSUXSEG8EI8_V_MF4_M1_MASK + {5, OperandInfo837}, // Inst #9883 = PseudoVSUXSEG8EI8_V_MF4_MF2 + {6, OperandInfo838}, // Inst #9884 = PseudoVSUXSEG8EI8_V_MF4_MF2_MASK + {5, OperandInfo837}, // Inst #9885 = PseudoVSUXSEG8EI8_V_MF4_MF4 + {6, OperandInfo838}, // Inst #9886 = PseudoVSUXSEG8EI8_V_MF4_MF4_MASK + {5, OperandInfo837}, // Inst #9887 = PseudoVSUXSEG8EI8_V_MF8_M1 + {6, OperandInfo838}, // Inst #9888 = PseudoVSUXSEG8EI8_V_MF8_M1_MASK + {5, OperandInfo837}, // Inst #9889 = PseudoVSUXSEG8EI8_V_MF8_MF2 + {6, OperandInfo838}, // Inst #9890 = PseudoVSUXSEG8EI8_V_MF8_MF2_MASK + {5, OperandInfo837}, // Inst #9891 = PseudoVSUXSEG8EI8_V_MF8_MF4 + {6, OperandInfo838}, // Inst #9892 = PseudoVSUXSEG8EI8_V_MF8_MF4_MASK + {5, OperandInfo837}, // Inst #9893 = PseudoVSUXSEG8EI8_V_MF8_MF8 + {6, OperandInfo838}, // Inst #9894 = PseudoVSUXSEG8EI8_V_MF8_MF8_MASK + {5, OperandInfo297}, // Inst #9895 = PseudoVWADDU_VV_M1 + {8, OperandInfo298}, // Inst #9896 = PseudoVWADDU_VV_M1_MASK + {5, OperandInfo299}, // Inst #9897 = PseudoVWADDU_VV_M2 + {8, OperandInfo300}, // Inst #9898 = PseudoVWADDU_VV_M2_MASK + {5, OperandInfo301}, // Inst #9899 = PseudoVWADDU_VV_M4 + {8, OperandInfo302}, // Inst #9900 = PseudoVWADDU_VV_M4_MASK + {5, OperandInfo303}, // Inst #9901 = PseudoVWADDU_VV_MF2 + {8, OperandInfo304}, // Inst #9902 = PseudoVWADDU_VV_MF2_MASK + {5, OperandInfo303}, // Inst #9903 = PseudoVWADDU_VV_MF4 + {8, OperandInfo304}, // Inst #9904 = PseudoVWADDU_VV_MF4_MASK + {5, OperandInfo303}, // Inst #9905 = PseudoVWADDU_VV_MF8 + {8, OperandInfo304}, // Inst #9906 = PseudoVWADDU_VV_MF8_MASK + {5, OperandInfo871}, // Inst #9907 = PseudoVWADDU_VX_M1 + {8, OperandInfo872}, // Inst #9908 = PseudoVWADDU_VX_M1_MASK + {5, OperandInfo873}, // Inst #9909 = PseudoVWADDU_VX_M2 + {8, OperandInfo874}, // Inst #9910 = PseudoVWADDU_VX_M2_MASK + {5, OperandInfo875}, // Inst #9911 = PseudoVWADDU_VX_M4 + {8, OperandInfo876}, // Inst #9912 = PseudoVWADDU_VX_M4_MASK + {5, OperandInfo568}, // Inst #9913 = PseudoVWADDU_VX_MF2 + {8, OperandInfo679}, // Inst #9914 = PseudoVWADDU_VX_MF2_MASK + {5, OperandInfo568}, // Inst #9915 = PseudoVWADDU_VX_MF4 + {8, OperandInfo679}, // Inst #9916 = PseudoVWADDU_VX_MF4_MASK + {5, OperandInfo568}, // Inst #9917 = PseudoVWADDU_VX_MF8 + {8, OperandInfo679}, // Inst #9918 = PseudoVWADDU_VX_MF8_MASK + {5, OperandInfo305}, // Inst #9919 = PseudoVWADDU_WV_M1 + {8, OperandInfo306}, // Inst #9920 = PseudoVWADDU_WV_M1_MASK + {7, OperandInfo307}, // Inst #9921 = PseudoVWADDU_WV_M1_MASK_TIED + {5, OperandInfo308}, // Inst #9922 = PseudoVWADDU_WV_M1_TIED + {5, OperandInfo309}, // Inst #9923 = PseudoVWADDU_WV_M2 + {8, OperandInfo310}, // Inst #9924 = PseudoVWADDU_WV_M2_MASK + {7, OperandInfo311}, // Inst #9925 = PseudoVWADDU_WV_M2_MASK_TIED + {5, OperandInfo312}, // Inst #9926 = PseudoVWADDU_WV_M2_TIED + {5, OperandInfo313}, // Inst #9927 = PseudoVWADDU_WV_M4 + {8, OperandInfo314}, // Inst #9928 = PseudoVWADDU_WV_M4_MASK + {7, OperandInfo315}, // Inst #9929 = PseudoVWADDU_WV_M4_MASK_TIED + {5, OperandInfo316}, // Inst #9930 = PseudoVWADDU_WV_M4_TIED + {5, OperandInfo303}, // Inst #9931 = PseudoVWADDU_WV_MF2 + {8, OperandInfo304}, // Inst #9932 = PseudoVWADDU_WV_MF2_MASK + {7, OperandInfo253}, // Inst #9933 = PseudoVWADDU_WV_MF2_MASK_TIED + {5, OperandInfo317}, // Inst #9934 = PseudoVWADDU_WV_MF2_TIED + {5, OperandInfo303}, // Inst #9935 = PseudoVWADDU_WV_MF4 + {8, OperandInfo304}, // Inst #9936 = PseudoVWADDU_WV_MF4_MASK + {7, OperandInfo253}, // Inst #9937 = PseudoVWADDU_WV_MF4_MASK_TIED + {5, OperandInfo317}, // Inst #9938 = PseudoVWADDU_WV_MF4_TIED + {5, OperandInfo303}, // Inst #9939 = PseudoVWADDU_WV_MF8 + {8, OperandInfo304}, // Inst #9940 = PseudoVWADDU_WV_MF8_MASK + {7, OperandInfo253}, // Inst #9941 = PseudoVWADDU_WV_MF8_MASK_TIED + {5, OperandInfo317}, // Inst #9942 = PseudoVWADDU_WV_MF8_TIED + {5, OperandInfo72}, // Inst #9943 = PseudoVWADDU_WX_M1 + {8, OperandInfo73}, // Inst #9944 = PseudoVWADDU_WX_M1_MASK + {5, OperandInfo74}, // Inst #9945 = PseudoVWADDU_WX_M2 + {8, OperandInfo75}, // Inst #9946 = PseudoVWADDU_WX_M2_MASK + {5, OperandInfo76}, // Inst #9947 = PseudoVWADDU_WX_M4 + {8, OperandInfo77}, // Inst #9948 = PseudoVWADDU_WX_M4_MASK + {5, OperandInfo70}, // Inst #9949 = PseudoVWADDU_WX_MF2 + {8, OperandInfo71}, // Inst #9950 = PseudoVWADDU_WX_MF2_MASK + {5, OperandInfo70}, // Inst #9951 = PseudoVWADDU_WX_MF4 + {8, OperandInfo71}, // Inst #9952 = PseudoVWADDU_WX_MF4_MASK + {5, OperandInfo70}, // Inst #9953 = PseudoVWADDU_WX_MF8 + {8, OperandInfo71}, // Inst #9954 = PseudoVWADDU_WX_MF8_MASK + {5, OperandInfo297}, // Inst #9955 = PseudoVWADD_VV_M1 + {8, OperandInfo298}, // Inst #9956 = PseudoVWADD_VV_M1_MASK + {5, OperandInfo299}, // Inst #9957 = PseudoVWADD_VV_M2 + {8, OperandInfo300}, // Inst #9958 = PseudoVWADD_VV_M2_MASK + {5, OperandInfo301}, // Inst #9959 = PseudoVWADD_VV_M4 + {8, OperandInfo302}, // Inst #9960 = PseudoVWADD_VV_M4_MASK + {5, OperandInfo303}, // Inst #9961 = PseudoVWADD_VV_MF2 + {8, OperandInfo304}, // Inst #9962 = PseudoVWADD_VV_MF2_MASK + {5, OperandInfo303}, // Inst #9963 = PseudoVWADD_VV_MF4 + {8, OperandInfo304}, // Inst #9964 = PseudoVWADD_VV_MF4_MASK + {5, OperandInfo303}, // Inst #9965 = PseudoVWADD_VV_MF8 + {8, OperandInfo304}, // Inst #9966 = PseudoVWADD_VV_MF8_MASK + {5, OperandInfo871}, // Inst #9967 = PseudoVWADD_VX_M1 + {8, OperandInfo872}, // Inst #9968 = PseudoVWADD_VX_M1_MASK + {5, OperandInfo873}, // Inst #9969 = PseudoVWADD_VX_M2 + {8, OperandInfo874}, // Inst #9970 = PseudoVWADD_VX_M2_MASK + {5, OperandInfo875}, // Inst #9971 = PseudoVWADD_VX_M4 + {8, OperandInfo876}, // Inst #9972 = PseudoVWADD_VX_M4_MASK + {5, OperandInfo568}, // Inst #9973 = PseudoVWADD_VX_MF2 + {8, OperandInfo679}, // Inst #9974 = PseudoVWADD_VX_MF2_MASK + {5, OperandInfo568}, // Inst #9975 = PseudoVWADD_VX_MF4 + {8, OperandInfo679}, // Inst #9976 = PseudoVWADD_VX_MF4_MASK + {5, OperandInfo568}, // Inst #9977 = PseudoVWADD_VX_MF8 + {8, OperandInfo679}, // Inst #9978 = PseudoVWADD_VX_MF8_MASK + {5, OperandInfo305}, // Inst #9979 = PseudoVWADD_WV_M1 + {8, OperandInfo306}, // Inst #9980 = PseudoVWADD_WV_M1_MASK + {7, OperandInfo307}, // Inst #9981 = PseudoVWADD_WV_M1_MASK_TIED + {5, OperandInfo308}, // Inst #9982 = PseudoVWADD_WV_M1_TIED + {5, OperandInfo309}, // Inst #9983 = PseudoVWADD_WV_M2 + {8, OperandInfo310}, // Inst #9984 = PseudoVWADD_WV_M2_MASK + {7, OperandInfo311}, // Inst #9985 = PseudoVWADD_WV_M2_MASK_TIED + {5, OperandInfo312}, // Inst #9986 = PseudoVWADD_WV_M2_TIED + {5, OperandInfo313}, // Inst #9987 = PseudoVWADD_WV_M4 + {8, OperandInfo314}, // Inst #9988 = PseudoVWADD_WV_M4_MASK + {7, OperandInfo315}, // Inst #9989 = PseudoVWADD_WV_M4_MASK_TIED + {5, OperandInfo316}, // Inst #9990 = PseudoVWADD_WV_M4_TIED + {5, OperandInfo303}, // Inst #9991 = PseudoVWADD_WV_MF2 + {8, OperandInfo304}, // Inst #9992 = PseudoVWADD_WV_MF2_MASK + {7, OperandInfo253}, // Inst #9993 = PseudoVWADD_WV_MF2_MASK_TIED + {5, OperandInfo317}, // Inst #9994 = PseudoVWADD_WV_MF2_TIED + {5, OperandInfo303}, // Inst #9995 = PseudoVWADD_WV_MF4 + {8, OperandInfo304}, // Inst #9996 = PseudoVWADD_WV_MF4_MASK + {7, OperandInfo253}, // Inst #9997 = PseudoVWADD_WV_MF4_MASK_TIED + {5, OperandInfo317}, // Inst #9998 = PseudoVWADD_WV_MF4_TIED + {5, OperandInfo303}, // Inst #9999 = PseudoVWADD_WV_MF8 + {8, OperandInfo304}, // Inst #10000 = PseudoVWADD_WV_MF8_MASK + {7, OperandInfo253}, // Inst #10001 = PseudoVWADD_WV_MF8_MASK_TIED + {5, OperandInfo317}, // Inst #10002 = PseudoVWADD_WV_MF8_TIED + {5, OperandInfo72}, // Inst #10003 = PseudoVWADD_WX_M1 + {8, OperandInfo73}, // Inst #10004 = PseudoVWADD_WX_M1_MASK + {5, OperandInfo74}, // Inst #10005 = PseudoVWADD_WX_M2 + {8, OperandInfo75}, // Inst #10006 = PseudoVWADD_WX_M2_MASK + {5, OperandInfo76}, // Inst #10007 = PseudoVWADD_WX_M4 + {8, OperandInfo77}, // Inst #10008 = PseudoVWADD_WX_M4_MASK + {5, OperandInfo70}, // Inst #10009 = PseudoVWADD_WX_MF2 + {8, OperandInfo71}, // Inst #10010 = PseudoVWADD_WX_MF2_MASK + {5, OperandInfo70}, // Inst #10011 = PseudoVWADD_WX_MF4 + {8, OperandInfo71}, // Inst #10012 = PseudoVWADD_WX_MF4_MASK + {5, OperandInfo70}, // Inst #10013 = PseudoVWADD_WX_MF8 + {8, OperandInfo71}, // Inst #10014 = PseudoVWADD_WX_MF8_MASK + {7, OperandInfo337}, // Inst #10015 = PseudoVWMACCSU_VV_M1 + {7, OperandInfo338}, // Inst #10016 = PseudoVWMACCSU_VV_M1_MASK + {7, OperandInfo339}, // Inst #10017 = PseudoVWMACCSU_VV_M2 + {7, OperandInfo340}, // Inst #10018 = PseudoVWMACCSU_VV_M2_MASK + {7, OperandInfo341}, // Inst #10019 = PseudoVWMACCSU_VV_M4 + {7, OperandInfo342}, // Inst #10020 = PseudoVWMACCSU_VV_M4_MASK + {7, OperandInfo343}, // Inst #10021 = PseudoVWMACCSU_VV_MF2 + {7, OperandInfo344}, // Inst #10022 = PseudoVWMACCSU_VV_MF2_MASK + {7, OperandInfo343}, // Inst #10023 = PseudoVWMACCSU_VV_MF4 + {7, OperandInfo344}, // Inst #10024 = PseudoVWMACCSU_VV_MF4_MASK + {7, OperandInfo343}, // Inst #10025 = PseudoVWMACCSU_VV_MF8 + {7, OperandInfo344}, // Inst #10026 = PseudoVWMACCSU_VV_MF8_MASK + {7, OperandInfo877}, // Inst #10027 = PseudoVWMACCSU_VX_M1 + {7, OperandInfo878}, // Inst #10028 = PseudoVWMACCSU_VX_M1_MASK + {7, OperandInfo879}, // Inst #10029 = PseudoVWMACCSU_VX_M2 + {7, OperandInfo880}, // Inst #10030 = PseudoVWMACCSU_VX_M2_MASK + {7, OperandInfo881}, // Inst #10031 = PseudoVWMACCSU_VX_M4 + {7, OperandInfo882}, // Inst #10032 = PseudoVWMACCSU_VX_M4_MASK + {7, OperandInfo883}, // Inst #10033 = PseudoVWMACCSU_VX_MF2 + {7, OperandInfo884}, // Inst #10034 = PseudoVWMACCSU_VX_MF2_MASK + {7, OperandInfo883}, // Inst #10035 = PseudoVWMACCSU_VX_MF4 + {7, OperandInfo884}, // Inst #10036 = PseudoVWMACCSU_VX_MF4_MASK + {7, OperandInfo883}, // Inst #10037 = PseudoVWMACCSU_VX_MF8 + {7, OperandInfo884}, // Inst #10038 = PseudoVWMACCSU_VX_MF8_MASK + {7, OperandInfo877}, // Inst #10039 = PseudoVWMACCUS_VX_M1 + {7, OperandInfo878}, // Inst #10040 = PseudoVWMACCUS_VX_M1_MASK + {7, OperandInfo879}, // Inst #10041 = PseudoVWMACCUS_VX_M2 + {7, OperandInfo880}, // Inst #10042 = PseudoVWMACCUS_VX_M2_MASK + {7, OperandInfo881}, // Inst #10043 = PseudoVWMACCUS_VX_M4 + {7, OperandInfo882}, // Inst #10044 = PseudoVWMACCUS_VX_M4_MASK + {7, OperandInfo883}, // Inst #10045 = PseudoVWMACCUS_VX_MF2 + {7, OperandInfo884}, // Inst #10046 = PseudoVWMACCUS_VX_MF2_MASK + {7, OperandInfo883}, // Inst #10047 = PseudoVWMACCUS_VX_MF4 + {7, OperandInfo884}, // Inst #10048 = PseudoVWMACCUS_VX_MF4_MASK + {7, OperandInfo883}, // Inst #10049 = PseudoVWMACCUS_VX_MF8 + {7, OperandInfo884}, // Inst #10050 = PseudoVWMACCUS_VX_MF8_MASK + {7, OperandInfo337}, // Inst #10051 = PseudoVWMACCU_VV_M1 + {7, OperandInfo338}, // Inst #10052 = PseudoVWMACCU_VV_M1_MASK + {7, OperandInfo339}, // Inst #10053 = PseudoVWMACCU_VV_M2 + {7, OperandInfo340}, // Inst #10054 = PseudoVWMACCU_VV_M2_MASK + {7, OperandInfo341}, // Inst #10055 = PseudoVWMACCU_VV_M4 + {7, OperandInfo342}, // Inst #10056 = PseudoVWMACCU_VV_M4_MASK + {7, OperandInfo343}, // Inst #10057 = PseudoVWMACCU_VV_MF2 + {7, OperandInfo344}, // Inst #10058 = PseudoVWMACCU_VV_MF2_MASK + {7, OperandInfo343}, // Inst #10059 = PseudoVWMACCU_VV_MF4 + {7, OperandInfo344}, // Inst #10060 = PseudoVWMACCU_VV_MF4_MASK + {7, OperandInfo343}, // Inst #10061 = PseudoVWMACCU_VV_MF8 + {7, OperandInfo344}, // Inst #10062 = PseudoVWMACCU_VV_MF8_MASK + {7, OperandInfo877}, // Inst #10063 = PseudoVWMACCU_VX_M1 + {7, OperandInfo878}, // Inst #10064 = PseudoVWMACCU_VX_M1_MASK + {7, OperandInfo879}, // Inst #10065 = PseudoVWMACCU_VX_M2 + {7, OperandInfo880}, // Inst #10066 = PseudoVWMACCU_VX_M2_MASK + {7, OperandInfo881}, // Inst #10067 = PseudoVWMACCU_VX_M4 + {7, OperandInfo882}, // Inst #10068 = PseudoVWMACCU_VX_M4_MASK + {7, OperandInfo883}, // Inst #10069 = PseudoVWMACCU_VX_MF2 + {7, OperandInfo884}, // Inst #10070 = PseudoVWMACCU_VX_MF2_MASK + {7, OperandInfo883}, // Inst #10071 = PseudoVWMACCU_VX_MF4 + {7, OperandInfo884}, // Inst #10072 = PseudoVWMACCU_VX_MF4_MASK + {7, OperandInfo883}, // Inst #10073 = PseudoVWMACCU_VX_MF8 + {7, OperandInfo884}, // Inst #10074 = PseudoVWMACCU_VX_MF8_MASK + {7, OperandInfo337}, // Inst #10075 = PseudoVWMACC_VV_M1 + {7, OperandInfo338}, // Inst #10076 = PseudoVWMACC_VV_M1_MASK + {7, OperandInfo339}, // Inst #10077 = PseudoVWMACC_VV_M2 + {7, OperandInfo340}, // Inst #10078 = PseudoVWMACC_VV_M2_MASK + {7, OperandInfo341}, // Inst #10079 = PseudoVWMACC_VV_M4 + {7, OperandInfo342}, // Inst #10080 = PseudoVWMACC_VV_M4_MASK + {7, OperandInfo343}, // Inst #10081 = PseudoVWMACC_VV_MF2 + {7, OperandInfo344}, // Inst #10082 = PseudoVWMACC_VV_MF2_MASK + {7, OperandInfo343}, // Inst #10083 = PseudoVWMACC_VV_MF4 + {7, OperandInfo344}, // Inst #10084 = PseudoVWMACC_VV_MF4_MASK + {7, OperandInfo343}, // Inst #10085 = PseudoVWMACC_VV_MF8 + {7, OperandInfo344}, // Inst #10086 = PseudoVWMACC_VV_MF8_MASK + {7, OperandInfo877}, // Inst #10087 = PseudoVWMACC_VX_M1 + {7, OperandInfo878}, // Inst #10088 = PseudoVWMACC_VX_M1_MASK + {7, OperandInfo879}, // Inst #10089 = PseudoVWMACC_VX_M2 + {7, OperandInfo880}, // Inst #10090 = PseudoVWMACC_VX_M2_MASK + {7, OperandInfo881}, // Inst #10091 = PseudoVWMACC_VX_M4 + {7, OperandInfo882}, // Inst #10092 = PseudoVWMACC_VX_M4_MASK + {7, OperandInfo883}, // Inst #10093 = PseudoVWMACC_VX_MF2 + {7, OperandInfo884}, // Inst #10094 = PseudoVWMACC_VX_MF2_MASK + {7, OperandInfo883}, // Inst #10095 = PseudoVWMACC_VX_MF4 + {7, OperandInfo884}, // Inst #10096 = PseudoVWMACC_VX_MF4_MASK + {7, OperandInfo883}, // Inst #10097 = PseudoVWMACC_VX_MF8 + {7, OperandInfo884}, // Inst #10098 = PseudoVWMACC_VX_MF8_MASK + {5, OperandInfo297}, // Inst #10099 = PseudoVWMULSU_VV_M1 + {8, OperandInfo298}, // Inst #10100 = PseudoVWMULSU_VV_M1_MASK + {5, OperandInfo299}, // Inst #10101 = PseudoVWMULSU_VV_M2 + {8, OperandInfo300}, // Inst #10102 = PseudoVWMULSU_VV_M2_MASK + {5, OperandInfo301}, // Inst #10103 = PseudoVWMULSU_VV_M4 + {8, OperandInfo302}, // Inst #10104 = PseudoVWMULSU_VV_M4_MASK + {5, OperandInfo303}, // Inst #10105 = PseudoVWMULSU_VV_MF2 + {8, OperandInfo304}, // Inst #10106 = PseudoVWMULSU_VV_MF2_MASK + {5, OperandInfo303}, // Inst #10107 = PseudoVWMULSU_VV_MF4 + {8, OperandInfo304}, // Inst #10108 = PseudoVWMULSU_VV_MF4_MASK + {5, OperandInfo303}, // Inst #10109 = PseudoVWMULSU_VV_MF8 + {8, OperandInfo304}, // Inst #10110 = PseudoVWMULSU_VV_MF8_MASK + {5, OperandInfo871}, // Inst #10111 = PseudoVWMULSU_VX_M1 + {8, OperandInfo872}, // Inst #10112 = PseudoVWMULSU_VX_M1_MASK + {5, OperandInfo873}, // Inst #10113 = PseudoVWMULSU_VX_M2 + {8, OperandInfo874}, // Inst #10114 = PseudoVWMULSU_VX_M2_MASK + {5, OperandInfo875}, // Inst #10115 = PseudoVWMULSU_VX_M4 + {8, OperandInfo876}, // Inst #10116 = PseudoVWMULSU_VX_M4_MASK + {5, OperandInfo568}, // Inst #10117 = PseudoVWMULSU_VX_MF2 + {8, OperandInfo679}, // Inst #10118 = PseudoVWMULSU_VX_MF2_MASK + {5, OperandInfo568}, // Inst #10119 = PseudoVWMULSU_VX_MF4 + {8, OperandInfo679}, // Inst #10120 = PseudoVWMULSU_VX_MF4_MASK + {5, OperandInfo568}, // Inst #10121 = PseudoVWMULSU_VX_MF8 + {8, OperandInfo679}, // Inst #10122 = PseudoVWMULSU_VX_MF8_MASK + {5, OperandInfo297}, // Inst #10123 = PseudoVWMULU_VV_M1 + {8, OperandInfo298}, // Inst #10124 = PseudoVWMULU_VV_M1_MASK + {5, OperandInfo299}, // Inst #10125 = PseudoVWMULU_VV_M2 + {8, OperandInfo300}, // Inst #10126 = PseudoVWMULU_VV_M2_MASK + {5, OperandInfo301}, // Inst #10127 = PseudoVWMULU_VV_M4 + {8, OperandInfo302}, // Inst #10128 = PseudoVWMULU_VV_M4_MASK + {5, OperandInfo303}, // Inst #10129 = PseudoVWMULU_VV_MF2 + {8, OperandInfo304}, // Inst #10130 = PseudoVWMULU_VV_MF2_MASK + {5, OperandInfo303}, // Inst #10131 = PseudoVWMULU_VV_MF4 + {8, OperandInfo304}, // Inst #10132 = PseudoVWMULU_VV_MF4_MASK + {5, OperandInfo303}, // Inst #10133 = PseudoVWMULU_VV_MF8 + {8, OperandInfo304}, // Inst #10134 = PseudoVWMULU_VV_MF8_MASK + {5, OperandInfo871}, // Inst #10135 = PseudoVWMULU_VX_M1 + {8, OperandInfo872}, // Inst #10136 = PseudoVWMULU_VX_M1_MASK + {5, OperandInfo873}, // Inst #10137 = PseudoVWMULU_VX_M2 + {8, OperandInfo874}, // Inst #10138 = PseudoVWMULU_VX_M2_MASK + {5, OperandInfo875}, // Inst #10139 = PseudoVWMULU_VX_M4 + {8, OperandInfo876}, // Inst #10140 = PseudoVWMULU_VX_M4_MASK + {5, OperandInfo568}, // Inst #10141 = PseudoVWMULU_VX_MF2 + {8, OperandInfo679}, // Inst #10142 = PseudoVWMULU_VX_MF2_MASK + {5, OperandInfo568}, // Inst #10143 = PseudoVWMULU_VX_MF4 + {8, OperandInfo679}, // Inst #10144 = PseudoVWMULU_VX_MF4_MASK + {5, OperandInfo568}, // Inst #10145 = PseudoVWMULU_VX_MF8 + {8, OperandInfo679}, // Inst #10146 = PseudoVWMULU_VX_MF8_MASK + {5, OperandInfo297}, // Inst #10147 = PseudoVWMUL_VV_M1 + {8, OperandInfo298}, // Inst #10148 = PseudoVWMUL_VV_M1_MASK + {5, OperandInfo299}, // Inst #10149 = PseudoVWMUL_VV_M2 + {8, OperandInfo300}, // Inst #10150 = PseudoVWMUL_VV_M2_MASK + {5, OperandInfo301}, // Inst #10151 = PseudoVWMUL_VV_M4 + {8, OperandInfo302}, // Inst #10152 = PseudoVWMUL_VV_M4_MASK + {5, OperandInfo303}, // Inst #10153 = PseudoVWMUL_VV_MF2 + {8, OperandInfo304}, // Inst #10154 = PseudoVWMUL_VV_MF2_MASK + {5, OperandInfo303}, // Inst #10155 = PseudoVWMUL_VV_MF4 + {8, OperandInfo304}, // Inst #10156 = PseudoVWMUL_VV_MF4_MASK + {5, OperandInfo303}, // Inst #10157 = PseudoVWMUL_VV_MF8 + {8, OperandInfo304}, // Inst #10158 = PseudoVWMUL_VV_MF8_MASK + {5, OperandInfo871}, // Inst #10159 = PseudoVWMUL_VX_M1 + {8, OperandInfo872}, // Inst #10160 = PseudoVWMUL_VX_M1_MASK + {5, OperandInfo873}, // Inst #10161 = PseudoVWMUL_VX_M2 + {8, OperandInfo874}, // Inst #10162 = PseudoVWMUL_VX_M2_MASK + {5, OperandInfo875}, // Inst #10163 = PseudoVWMUL_VX_M4 + {8, OperandInfo876}, // Inst #10164 = PseudoVWMUL_VX_M4_MASK + {5, OperandInfo568}, // Inst #10165 = PseudoVWMUL_VX_MF2 + {8, OperandInfo679}, // Inst #10166 = PseudoVWMUL_VX_MF2_MASK + {5, OperandInfo568}, // Inst #10167 = PseudoVWMUL_VX_MF4 + {8, OperandInfo679}, // Inst #10168 = PseudoVWMUL_VX_MF4_MASK + {5, OperandInfo568}, // Inst #10169 = PseudoVWMUL_VX_MF8 + {8, OperandInfo679}, // Inst #10170 = PseudoVWMUL_VX_MF8_MASK + {6, OperandInfo254}, // Inst #10171 = PseudoVWREDSUMU_VS_M1 + {7, OperandInfo191}, // Inst #10172 = PseudoVWREDSUMU_VS_M1_MASK + {6, OperandInfo255}, // Inst #10173 = PseudoVWREDSUMU_VS_M2 + {7, OperandInfo256}, // Inst #10174 = PseudoVWREDSUMU_VS_M2_MASK + {6, OperandInfo257}, // Inst #10175 = PseudoVWREDSUMU_VS_M4 + {7, OperandInfo258}, // Inst #10176 = PseudoVWREDSUMU_VS_M4_MASK + {6, OperandInfo259}, // Inst #10177 = PseudoVWREDSUMU_VS_M8 + {7, OperandInfo260}, // Inst #10178 = PseudoVWREDSUMU_VS_M8_MASK + {6, OperandInfo254}, // Inst #10179 = PseudoVWREDSUMU_VS_MF2 + {7, OperandInfo191}, // Inst #10180 = PseudoVWREDSUMU_VS_MF2_MASK + {6, OperandInfo254}, // Inst #10181 = PseudoVWREDSUMU_VS_MF4 + {7, OperandInfo191}, // Inst #10182 = PseudoVWREDSUMU_VS_MF4_MASK + {6, OperandInfo254}, // Inst #10183 = PseudoVWREDSUMU_VS_MF8 + {7, OperandInfo191}, // Inst #10184 = PseudoVWREDSUMU_VS_MF8_MASK + {6, OperandInfo254}, // Inst #10185 = PseudoVWREDSUM_VS_M1 + {7, OperandInfo191}, // Inst #10186 = PseudoVWREDSUM_VS_M1_MASK + {6, OperandInfo255}, // Inst #10187 = PseudoVWREDSUM_VS_M2 + {7, OperandInfo256}, // Inst #10188 = PseudoVWREDSUM_VS_M2_MASK + {6, OperandInfo257}, // Inst #10189 = PseudoVWREDSUM_VS_M4 + {7, OperandInfo258}, // Inst #10190 = PseudoVWREDSUM_VS_M4_MASK + {6, OperandInfo259}, // Inst #10191 = PseudoVWREDSUM_VS_M8 + {7, OperandInfo260}, // Inst #10192 = PseudoVWREDSUM_VS_M8_MASK + {6, OperandInfo254}, // Inst #10193 = PseudoVWREDSUM_VS_MF2 + {7, OperandInfo191}, // Inst #10194 = PseudoVWREDSUM_VS_MF2_MASK + {6, OperandInfo254}, // Inst #10195 = PseudoVWREDSUM_VS_MF4 + {7, OperandInfo191}, // Inst #10196 = PseudoVWREDSUM_VS_MF4_MASK + {6, OperandInfo254}, // Inst #10197 = PseudoVWREDSUM_VS_MF8 + {7, OperandInfo191}, // Inst #10198 = PseudoVWREDSUM_VS_MF8_MASK + {5, OperandInfo297}, // Inst #10199 = PseudoVWSUBU_VV_M1 + {8, OperandInfo298}, // Inst #10200 = PseudoVWSUBU_VV_M1_MASK + {5, OperandInfo299}, // Inst #10201 = PseudoVWSUBU_VV_M2 + {8, OperandInfo300}, // Inst #10202 = PseudoVWSUBU_VV_M2_MASK + {5, OperandInfo301}, // Inst #10203 = PseudoVWSUBU_VV_M4 + {8, OperandInfo302}, // Inst #10204 = PseudoVWSUBU_VV_M4_MASK + {5, OperandInfo303}, // Inst #10205 = PseudoVWSUBU_VV_MF2 + {8, OperandInfo304}, // Inst #10206 = PseudoVWSUBU_VV_MF2_MASK + {5, OperandInfo303}, // Inst #10207 = PseudoVWSUBU_VV_MF4 + {8, OperandInfo304}, // Inst #10208 = PseudoVWSUBU_VV_MF4_MASK + {5, OperandInfo303}, // Inst #10209 = PseudoVWSUBU_VV_MF8 + {8, OperandInfo304}, // Inst #10210 = PseudoVWSUBU_VV_MF8_MASK + {5, OperandInfo871}, // Inst #10211 = PseudoVWSUBU_VX_M1 + {8, OperandInfo872}, // Inst #10212 = PseudoVWSUBU_VX_M1_MASK + {5, OperandInfo873}, // Inst #10213 = PseudoVWSUBU_VX_M2 + {8, OperandInfo874}, // Inst #10214 = PseudoVWSUBU_VX_M2_MASK + {5, OperandInfo875}, // Inst #10215 = PseudoVWSUBU_VX_M4 + {8, OperandInfo876}, // Inst #10216 = PseudoVWSUBU_VX_M4_MASK + {5, OperandInfo568}, // Inst #10217 = PseudoVWSUBU_VX_MF2 + {8, OperandInfo679}, // Inst #10218 = PseudoVWSUBU_VX_MF2_MASK + {5, OperandInfo568}, // Inst #10219 = PseudoVWSUBU_VX_MF4 + {8, OperandInfo679}, // Inst #10220 = PseudoVWSUBU_VX_MF4_MASK + {5, OperandInfo568}, // Inst #10221 = PseudoVWSUBU_VX_MF8 + {8, OperandInfo679}, // Inst #10222 = PseudoVWSUBU_VX_MF8_MASK + {5, OperandInfo305}, // Inst #10223 = PseudoVWSUBU_WV_M1 + {8, OperandInfo306}, // Inst #10224 = PseudoVWSUBU_WV_M1_MASK + {7, OperandInfo307}, // Inst #10225 = PseudoVWSUBU_WV_M1_MASK_TIED + {5, OperandInfo308}, // Inst #10226 = PseudoVWSUBU_WV_M1_TIED + {5, OperandInfo309}, // Inst #10227 = PseudoVWSUBU_WV_M2 + {8, OperandInfo310}, // Inst #10228 = PseudoVWSUBU_WV_M2_MASK + {7, OperandInfo311}, // Inst #10229 = PseudoVWSUBU_WV_M2_MASK_TIED + {5, OperandInfo312}, // Inst #10230 = PseudoVWSUBU_WV_M2_TIED + {5, OperandInfo313}, // Inst #10231 = PseudoVWSUBU_WV_M4 + {8, OperandInfo314}, // Inst #10232 = PseudoVWSUBU_WV_M4_MASK + {7, OperandInfo315}, // Inst #10233 = PseudoVWSUBU_WV_M4_MASK_TIED + {5, OperandInfo316}, // Inst #10234 = PseudoVWSUBU_WV_M4_TIED + {5, OperandInfo303}, // Inst #10235 = PseudoVWSUBU_WV_MF2 + {8, OperandInfo304}, // Inst #10236 = PseudoVWSUBU_WV_MF2_MASK + {7, OperandInfo253}, // Inst #10237 = PseudoVWSUBU_WV_MF2_MASK_TIED + {5, OperandInfo317}, // Inst #10238 = PseudoVWSUBU_WV_MF2_TIED + {5, OperandInfo303}, // Inst #10239 = PseudoVWSUBU_WV_MF4 + {8, OperandInfo304}, // Inst #10240 = PseudoVWSUBU_WV_MF4_MASK + {7, OperandInfo253}, // Inst #10241 = PseudoVWSUBU_WV_MF4_MASK_TIED + {5, OperandInfo317}, // Inst #10242 = PseudoVWSUBU_WV_MF4_TIED + {5, OperandInfo303}, // Inst #10243 = PseudoVWSUBU_WV_MF8 + {8, OperandInfo304}, // Inst #10244 = PseudoVWSUBU_WV_MF8_MASK + {7, OperandInfo253}, // Inst #10245 = PseudoVWSUBU_WV_MF8_MASK_TIED + {5, OperandInfo317}, // Inst #10246 = PseudoVWSUBU_WV_MF8_TIED + {5, OperandInfo72}, // Inst #10247 = PseudoVWSUBU_WX_M1 + {8, OperandInfo73}, // Inst #10248 = PseudoVWSUBU_WX_M1_MASK + {5, OperandInfo74}, // Inst #10249 = PseudoVWSUBU_WX_M2 + {8, OperandInfo75}, // Inst #10250 = PseudoVWSUBU_WX_M2_MASK + {5, OperandInfo76}, // Inst #10251 = PseudoVWSUBU_WX_M4 + {8, OperandInfo77}, // Inst #10252 = PseudoVWSUBU_WX_M4_MASK + {5, OperandInfo70}, // Inst #10253 = PseudoVWSUBU_WX_MF2 + {8, OperandInfo71}, // Inst #10254 = PseudoVWSUBU_WX_MF2_MASK + {5, OperandInfo70}, // Inst #10255 = PseudoVWSUBU_WX_MF4 + {8, OperandInfo71}, // Inst #10256 = PseudoVWSUBU_WX_MF4_MASK + {5, OperandInfo70}, // Inst #10257 = PseudoVWSUBU_WX_MF8 + {8, OperandInfo71}, // Inst #10258 = PseudoVWSUBU_WX_MF8_MASK + {5, OperandInfo297}, // Inst #10259 = PseudoVWSUB_VV_M1 + {8, OperandInfo298}, // Inst #10260 = PseudoVWSUB_VV_M1_MASK + {5, OperandInfo299}, // Inst #10261 = PseudoVWSUB_VV_M2 + {8, OperandInfo300}, // Inst #10262 = PseudoVWSUB_VV_M2_MASK + {5, OperandInfo301}, // Inst #10263 = PseudoVWSUB_VV_M4 + {8, OperandInfo302}, // Inst #10264 = PseudoVWSUB_VV_M4_MASK + {5, OperandInfo303}, // Inst #10265 = PseudoVWSUB_VV_MF2 + {8, OperandInfo304}, // Inst #10266 = PseudoVWSUB_VV_MF2_MASK + {5, OperandInfo303}, // Inst #10267 = PseudoVWSUB_VV_MF4 + {8, OperandInfo304}, // Inst #10268 = PseudoVWSUB_VV_MF4_MASK + {5, OperandInfo303}, // Inst #10269 = PseudoVWSUB_VV_MF8 + {8, OperandInfo304}, // Inst #10270 = PseudoVWSUB_VV_MF8_MASK + {5, OperandInfo871}, // Inst #10271 = PseudoVWSUB_VX_M1 + {8, OperandInfo872}, // Inst #10272 = PseudoVWSUB_VX_M1_MASK + {5, OperandInfo873}, // Inst #10273 = PseudoVWSUB_VX_M2 + {8, OperandInfo874}, // Inst #10274 = PseudoVWSUB_VX_M2_MASK + {5, OperandInfo875}, // Inst #10275 = PseudoVWSUB_VX_M4 + {8, OperandInfo876}, // Inst #10276 = PseudoVWSUB_VX_M4_MASK + {5, OperandInfo568}, // Inst #10277 = PseudoVWSUB_VX_MF2 + {8, OperandInfo679}, // Inst #10278 = PseudoVWSUB_VX_MF2_MASK + {5, OperandInfo568}, // Inst #10279 = PseudoVWSUB_VX_MF4 + {8, OperandInfo679}, // Inst #10280 = PseudoVWSUB_VX_MF4_MASK + {5, OperandInfo568}, // Inst #10281 = PseudoVWSUB_VX_MF8 + {8, OperandInfo679}, // Inst #10282 = PseudoVWSUB_VX_MF8_MASK + {5, OperandInfo305}, // Inst #10283 = PseudoVWSUB_WV_M1 + {8, OperandInfo306}, // Inst #10284 = PseudoVWSUB_WV_M1_MASK + {7, OperandInfo307}, // Inst #10285 = PseudoVWSUB_WV_M1_MASK_TIED + {5, OperandInfo308}, // Inst #10286 = PseudoVWSUB_WV_M1_TIED + {5, OperandInfo309}, // Inst #10287 = PseudoVWSUB_WV_M2 + {8, OperandInfo310}, // Inst #10288 = PseudoVWSUB_WV_M2_MASK + {7, OperandInfo311}, // Inst #10289 = PseudoVWSUB_WV_M2_MASK_TIED + {5, OperandInfo312}, // Inst #10290 = PseudoVWSUB_WV_M2_TIED + {5, OperandInfo313}, // Inst #10291 = PseudoVWSUB_WV_M4 + {8, OperandInfo314}, // Inst #10292 = PseudoVWSUB_WV_M4_MASK + {7, OperandInfo315}, // Inst #10293 = PseudoVWSUB_WV_M4_MASK_TIED + {5, OperandInfo316}, // Inst #10294 = PseudoVWSUB_WV_M4_TIED + {5, OperandInfo303}, // Inst #10295 = PseudoVWSUB_WV_MF2 + {8, OperandInfo304}, // Inst #10296 = PseudoVWSUB_WV_MF2_MASK + {7, OperandInfo253}, // Inst #10297 = PseudoVWSUB_WV_MF2_MASK_TIED + {5, OperandInfo317}, // Inst #10298 = PseudoVWSUB_WV_MF2_TIED + {5, OperandInfo303}, // Inst #10299 = PseudoVWSUB_WV_MF4 + {8, OperandInfo304}, // Inst #10300 = PseudoVWSUB_WV_MF4_MASK + {7, OperandInfo253}, // Inst #10301 = PseudoVWSUB_WV_MF4_MASK_TIED + {5, OperandInfo317}, // Inst #10302 = PseudoVWSUB_WV_MF4_TIED + {5, OperandInfo303}, // Inst #10303 = PseudoVWSUB_WV_MF8 + {8, OperandInfo304}, // Inst #10304 = PseudoVWSUB_WV_MF8_MASK + {7, OperandInfo253}, // Inst #10305 = PseudoVWSUB_WV_MF8_MASK_TIED + {5, OperandInfo317}, // Inst #10306 = PseudoVWSUB_WV_MF8_TIED + {5, OperandInfo72}, // Inst #10307 = PseudoVWSUB_WX_M1 + {8, OperandInfo73}, // Inst #10308 = PseudoVWSUB_WX_M1_MASK + {5, OperandInfo74}, // Inst #10309 = PseudoVWSUB_WX_M2 + {8, OperandInfo75}, // Inst #10310 = PseudoVWSUB_WX_M2_MASK + {5, OperandInfo76}, // Inst #10311 = PseudoVWSUB_WX_M4 + {8, OperandInfo77}, // Inst #10312 = PseudoVWSUB_WX_M4_MASK + {5, OperandInfo70}, // Inst #10313 = PseudoVWSUB_WX_MF2 + {8, OperandInfo71}, // Inst #10314 = PseudoVWSUB_WX_MF2_MASK + {5, OperandInfo70}, // Inst #10315 = PseudoVWSUB_WX_MF4 + {8, OperandInfo71}, // Inst #10316 = PseudoVWSUB_WX_MF4_MASK + {5, OperandInfo70}, // Inst #10317 = PseudoVWSUB_WX_MF8 + {8, OperandInfo71}, // Inst #10318 = PseudoVWSUB_WX_MF8_MASK + {5, OperandInfo90}, // Inst #10319 = PseudoVXOR_VI_M1 + {8, OperandInfo91}, // Inst #10320 = PseudoVXOR_VI_M1_MASK + {5, OperandInfo92}, // Inst #10321 = PseudoVXOR_VI_M2 + {8, OperandInfo93}, // Inst #10322 = PseudoVXOR_VI_M2_MASK + {5, OperandInfo94}, // Inst #10323 = PseudoVXOR_VI_M4 + {8, OperandInfo95}, // Inst #10324 = PseudoVXOR_VI_M4_MASK + {5, OperandInfo96}, // Inst #10325 = PseudoVXOR_VI_M8 + {8, OperandInfo97}, // Inst #10326 = PseudoVXOR_VI_M8_MASK + {5, OperandInfo90}, // Inst #10327 = PseudoVXOR_VI_MF2 + {8, OperandInfo91}, // Inst #10328 = PseudoVXOR_VI_MF2_MASK + {5, OperandInfo90}, // Inst #10329 = PseudoVXOR_VI_MF4 + {8, OperandInfo91}, // Inst #10330 = PseudoVXOR_VI_MF4_MASK + {5, OperandInfo90}, // Inst #10331 = PseudoVXOR_VI_MF8 + {8, OperandInfo91}, // Inst #10332 = PseudoVXOR_VI_MF8_MASK + {5, OperandInfo62}, // Inst #10333 = PseudoVXOR_VV_M1 + {8, OperandInfo63}, // Inst #10334 = PseudoVXOR_VV_M1_MASK + {5, OperandInfo64}, // Inst #10335 = PseudoVXOR_VV_M2 + {8, OperandInfo65}, // Inst #10336 = PseudoVXOR_VV_M2_MASK + {5, OperandInfo66}, // Inst #10337 = PseudoVXOR_VV_M4 + {8, OperandInfo67}, // Inst #10338 = PseudoVXOR_VV_M4_MASK + {5, OperandInfo68}, // Inst #10339 = PseudoVXOR_VV_M8 + {8, OperandInfo69}, // Inst #10340 = PseudoVXOR_VV_M8_MASK + {5, OperandInfo62}, // Inst #10341 = PseudoVXOR_VV_MF2 + {8, OperandInfo63}, // Inst #10342 = PseudoVXOR_VV_MF2_MASK + {5, OperandInfo62}, // Inst #10343 = PseudoVXOR_VV_MF4 + {8, OperandInfo63}, // Inst #10344 = PseudoVXOR_VV_MF4_MASK + {5, OperandInfo62}, // Inst #10345 = PseudoVXOR_VV_MF8 + {8, OperandInfo63}, // Inst #10346 = PseudoVXOR_VV_MF8_MASK + {5, OperandInfo70}, // Inst #10347 = PseudoVXOR_VX_M1 + {8, OperandInfo71}, // Inst #10348 = PseudoVXOR_VX_M1_MASK + {5, OperandInfo72}, // Inst #10349 = PseudoVXOR_VX_M2 + {8, OperandInfo73}, // Inst #10350 = PseudoVXOR_VX_M2_MASK + {5, OperandInfo74}, // Inst #10351 = PseudoVXOR_VX_M4 + {8, OperandInfo75}, // Inst #10352 = PseudoVXOR_VX_M4_MASK + {5, OperandInfo76}, // Inst #10353 = PseudoVXOR_VX_M8 + {8, OperandInfo77}, // Inst #10354 = PseudoVXOR_VX_M8_MASK + {5, OperandInfo70}, // Inst #10355 = PseudoVXOR_VX_MF2 + {8, OperandInfo71}, // Inst #10356 = PseudoVXOR_VX_MF2_MASK + {5, OperandInfo70}, // Inst #10357 = PseudoVXOR_VX_MF4 + {8, OperandInfo71}, // Inst #10358 = PseudoVXOR_VX_MF4_MASK + {5, OperandInfo70}, // Inst #10359 = PseudoVXOR_VX_MF8 + {8, OperandInfo71}, // Inst #10360 = PseudoVXOR_VX_MF8_MASK + {4, OperandInfo252}, // Inst #10361 = PseudoVZEXT_VF2_M1 + {7, OperandInfo253}, // Inst #10362 = PseudoVZEXT_VF2_M1_MASK + {4, OperandInfo318}, // Inst #10363 = PseudoVZEXT_VF2_M2 + {7, OperandInfo307}, // Inst #10364 = PseudoVZEXT_VF2_M2_MASK + {4, OperandInfo319}, // Inst #10365 = PseudoVZEXT_VF2_M4 + {7, OperandInfo311}, // Inst #10366 = PseudoVZEXT_VF2_M4_MASK + {4, OperandInfo320}, // Inst #10367 = PseudoVZEXT_VF2_M8 + {7, OperandInfo315}, // Inst #10368 = PseudoVZEXT_VF2_M8_MASK + {4, OperandInfo252}, // Inst #10369 = PseudoVZEXT_VF2_MF2 + {7, OperandInfo253}, // Inst #10370 = PseudoVZEXT_VF2_MF2_MASK + {4, OperandInfo252}, // Inst #10371 = PseudoVZEXT_VF2_MF4 + {7, OperandInfo253}, // Inst #10372 = PseudoVZEXT_VF2_MF4_MASK + {4, OperandInfo252}, // Inst #10373 = PseudoVZEXT_VF4_M1 + {7, OperandInfo253}, // Inst #10374 = PseudoVZEXT_VF4_M1_MASK + {4, OperandInfo318}, // Inst #10375 = PseudoVZEXT_VF4_M2 + {7, OperandInfo307}, // Inst #10376 = PseudoVZEXT_VF4_M2_MASK + {4, OperandInfo355}, // Inst #10377 = PseudoVZEXT_VF4_M4 + {7, OperandInfo693}, // Inst #10378 = PseudoVZEXT_VF4_M4_MASK + {4, OperandInfo694}, // Inst #10379 = PseudoVZEXT_VF4_M8 + {7, OperandInfo695}, // Inst #10380 = PseudoVZEXT_VF4_M8_MASK + {4, OperandInfo252}, // Inst #10381 = PseudoVZEXT_VF4_MF2 + {7, OperandInfo253}, // Inst #10382 = PseudoVZEXT_VF4_MF2_MASK + {4, OperandInfo252}, // Inst #10383 = PseudoVZEXT_VF8_M1 + {7, OperandInfo253}, // Inst #10384 = PseudoVZEXT_VF8_M1_MASK + {4, OperandInfo318}, // Inst #10385 = PseudoVZEXT_VF8_M2 + {7, OperandInfo307}, // Inst #10386 = PseudoVZEXT_VF8_M2_MASK + {4, OperandInfo355}, // Inst #10387 = PseudoVZEXT_VF8_M4 + {7, OperandInfo693}, // Inst #10388 = PseudoVZEXT_VF8_M4_MASK + {4, OperandInfo357}, // Inst #10389 = PseudoVZEXT_VF8_M8 + {7, OperandInfo696}, // Inst #10390 = PseudoVZEXT_VF8_M8_MASK + {2, OperandInfo60}, // Inst #10391 = PseudoZEXT_H + {2, OperandInfo60}, // Inst #10392 = PseudoZEXT_W + {2, OperandInfo60}, // Inst #10393 = ReadCycleWide + {1, OperandInfo58}, // Inst #10394 = ReadFRM + {6, OperandInfo885}, // Inst #10395 = Select_FPR16_Using_CC_GPR + {6, OperandInfo886}, // Inst #10396 = Select_FPR32_Using_CC_GPR + {6, OperandInfo887}, // Inst #10397 = Select_FPR64_Using_CC_GPR + {6, OperandInfo888}, // Inst #10398 = Select_GPR_Using_CC_GPR + {3, OperandInfo889}, // Inst #10399 = SplitF64Pseudo + {1, OperandInfo58}, // Inst #10400 = WriteFRM + {1, OperandInfo2}, // Inst #10401 = WriteFRMImm + {3, OperandInfo890}, // Inst #10402 = ADD + {3, OperandInfo59}, // Inst #10403 = ADDI + {3, OperandInfo59}, // Inst #10404 = ADDIW + {3, OperandInfo890}, // Inst #10405 = ADDUW + {3, OperandInfo890}, // Inst #10406 = ADDW + {3, OperandInfo890}, // Inst #10407 = AMOADD_D + {3, OperandInfo890}, // Inst #10408 = AMOADD_D_AQ + {3, OperandInfo890}, // Inst #10409 = AMOADD_D_AQ_RL + {3, OperandInfo890}, // Inst #10410 = AMOADD_D_RL + {3, OperandInfo890}, // Inst #10411 = AMOADD_W + {3, OperandInfo890}, // Inst #10412 = AMOADD_W_AQ + {3, OperandInfo890}, // Inst #10413 = AMOADD_W_AQ_RL + {3, OperandInfo890}, // Inst #10414 = AMOADD_W_RL + {3, OperandInfo890}, // Inst #10415 = AMOAND_D + {3, OperandInfo890}, // Inst #10416 = AMOAND_D_AQ + {3, OperandInfo890}, // Inst #10417 = AMOAND_D_AQ_RL + {3, OperandInfo890}, // Inst #10418 = AMOAND_D_RL + {3, OperandInfo890}, // Inst #10419 = AMOAND_W + {3, OperandInfo890}, // Inst #10420 = AMOAND_W_AQ + {3, OperandInfo890}, // Inst #10421 = AMOAND_W_AQ_RL + {3, OperandInfo890}, // Inst #10422 = AMOAND_W_RL + {3, OperandInfo890}, // Inst #10423 = AMOMAXU_D + {3, OperandInfo890}, // Inst #10424 = AMOMAXU_D_AQ + {3, OperandInfo890}, // Inst #10425 = AMOMAXU_D_AQ_RL + {3, OperandInfo890}, // Inst #10426 = AMOMAXU_D_RL + {3, OperandInfo890}, // Inst #10427 = AMOMAXU_W + {3, OperandInfo890}, // Inst #10428 = AMOMAXU_W_AQ + {3, OperandInfo890}, // Inst #10429 = AMOMAXU_W_AQ_RL + {3, OperandInfo890}, // Inst #10430 = AMOMAXU_W_RL + {3, OperandInfo890}, // Inst #10431 = AMOMAX_D + {3, OperandInfo890}, // Inst #10432 = AMOMAX_D_AQ + {3, OperandInfo890}, // Inst #10433 = AMOMAX_D_AQ_RL + {3, OperandInfo890}, // Inst #10434 = AMOMAX_D_RL + {3, OperandInfo890}, // Inst #10435 = AMOMAX_W + {3, OperandInfo890}, // Inst #10436 = AMOMAX_W_AQ + {3, OperandInfo890}, // Inst #10437 = AMOMAX_W_AQ_RL + {3, OperandInfo890}, // Inst #10438 = AMOMAX_W_RL + {3, OperandInfo890}, // Inst #10439 = AMOMINU_D + {3, OperandInfo890}, // Inst #10440 = AMOMINU_D_AQ + {3, OperandInfo890}, // Inst #10441 = AMOMINU_D_AQ_RL + {3, OperandInfo890}, // Inst #10442 = AMOMINU_D_RL + {3, OperandInfo890}, // Inst #10443 = AMOMINU_W + {3, OperandInfo890}, // Inst #10444 = AMOMINU_W_AQ + {3, OperandInfo890}, // Inst #10445 = AMOMINU_W_AQ_RL + {3, OperandInfo890}, // Inst #10446 = AMOMINU_W_RL + {3, OperandInfo890}, // Inst #10447 = AMOMIN_D + {3, OperandInfo890}, // Inst #10448 = AMOMIN_D_AQ + {3, OperandInfo890}, // Inst #10449 = AMOMIN_D_AQ_RL + {3, OperandInfo890}, // Inst #10450 = AMOMIN_D_RL + {3, OperandInfo890}, // Inst #10451 = AMOMIN_W + {3, OperandInfo890}, // Inst #10452 = AMOMIN_W_AQ + {3, OperandInfo890}, // Inst #10453 = AMOMIN_W_AQ_RL + {3, OperandInfo890}, // Inst #10454 = AMOMIN_W_RL + {3, OperandInfo890}, // Inst #10455 = AMOOR_D + {3, OperandInfo890}, // Inst #10456 = AMOOR_D_AQ + {3, OperandInfo890}, // Inst #10457 = AMOOR_D_AQ_RL + {3, OperandInfo890}, // Inst #10458 = AMOOR_D_RL + {3, OperandInfo890}, // Inst #10459 = AMOOR_W + {3, OperandInfo890}, // Inst #10460 = AMOOR_W_AQ + {3, OperandInfo890}, // Inst #10461 = AMOOR_W_AQ_RL + {3, OperandInfo890}, // Inst #10462 = AMOOR_W_RL + {3, OperandInfo890}, // Inst #10463 = AMOSWAP_D + {3, OperandInfo890}, // Inst #10464 = AMOSWAP_D_AQ + {3, OperandInfo890}, // Inst #10465 = AMOSWAP_D_AQ_RL + {3, OperandInfo890}, // Inst #10466 = AMOSWAP_D_RL + {3, OperandInfo890}, // Inst #10467 = AMOSWAP_W + {3, OperandInfo890}, // Inst #10468 = AMOSWAP_W_AQ + {3, OperandInfo890}, // Inst #10469 = AMOSWAP_W_AQ_RL + {3, OperandInfo890}, // Inst #10470 = AMOSWAP_W_RL + {3, OperandInfo890}, // Inst #10471 = AMOXOR_D + {3, OperandInfo890}, // Inst #10472 = AMOXOR_D_AQ + {3, OperandInfo890}, // Inst #10473 = AMOXOR_D_AQ_RL + {3, OperandInfo890}, // Inst #10474 = AMOXOR_D_RL + {3, OperandInfo890}, // Inst #10475 = AMOXOR_W + {3, OperandInfo890}, // Inst #10476 = AMOXOR_W_AQ + {3, OperandInfo890}, // Inst #10477 = AMOXOR_W_AQ_RL + {3, OperandInfo890}, // Inst #10478 = AMOXOR_W_RL + {3, OperandInfo890}, // Inst #10479 = AND + {3, OperandInfo59}, // Inst #10480 = ANDI + {3, OperandInfo890}, // Inst #10481 = ANDN + {2, OperandInfo50}, // Inst #10482 = AUIPC + {3, OperandInfo890}, // Inst #10483 = BCLR + {3, OperandInfo59}, // Inst #10484 = BCLRI + {3, OperandInfo890}, // Inst #10485 = BCOMPRESS + {3, OperandInfo890}, // Inst #10486 = BCOMPRESSW + {3, OperandInfo890}, // Inst #10487 = BDECOMPRESS + {3, OperandInfo890}, // Inst #10488 = BDECOMPRESSW + {3, OperandInfo891}, // Inst #10489 = BEQ + {3, OperandInfo890}, // Inst #10490 = BEXT + {3, OperandInfo59}, // Inst #10491 = BEXTI + {3, OperandInfo890}, // Inst #10492 = BFP + {3, OperandInfo890}, // Inst #10493 = BFPW + {3, OperandInfo891}, // Inst #10494 = BGE + {3, OperandInfo891}, // Inst #10495 = BGEU + {3, OperandInfo890}, // Inst #10496 = BINV + {3, OperandInfo59}, // Inst #10497 = BINVI + {3, OperandInfo891}, // Inst #10498 = BLT + {3, OperandInfo891}, // Inst #10499 = BLTU + {2, OperandInfo60}, // Inst #10500 = BMATFLIP + {3, OperandInfo890}, // Inst #10501 = BMATOR + {3, OperandInfo890}, // Inst #10502 = BMATXOR + {3, OperandInfo891}, // Inst #10503 = BNE + {3, OperandInfo890}, // Inst #10504 = BSET + {3, OperandInfo59}, // Inst #10505 = BSETI + {3, OperandInfo890}, // Inst #10506 = CLMUL + {3, OperandInfo890}, // Inst #10507 = CLMULH + {3, OperandInfo890}, // Inst #10508 = CLMULR + {2, OperandInfo60}, // Inst #10509 = CLZ + {2, OperandInfo60}, // Inst #10510 = CLZW + {4, OperandInfo892}, // Inst #10511 = CMIX + {4, OperandInfo892}, // Inst #10512 = CMOV + {2, OperandInfo60}, // Inst #10513 = CPOP + {2, OperandInfo60}, // Inst #10514 = CPOPW + {2, OperandInfo60}, // Inst #10515 = CRC32B + {2, OperandInfo60}, // Inst #10516 = CRC32CB + {2, OperandInfo60}, // Inst #10517 = CRC32CD + {2, OperandInfo60}, // Inst #10518 = CRC32CH + {2, OperandInfo60}, // Inst #10519 = CRC32CW + {2, OperandInfo60}, // Inst #10520 = CRC32D + {2, OperandInfo60}, // Inst #10521 = CRC32H + {2, OperandInfo60}, // Inst #10522 = CRC32W + {3, OperandInfo893}, // Inst #10523 = CSRRC + {3, OperandInfo690}, // Inst #10524 = CSRRCI + {3, OperandInfo893}, // Inst #10525 = CSRRS + {3, OperandInfo690}, // Inst #10526 = CSRRSI + {3, OperandInfo893}, // Inst #10527 = CSRRW + {3, OperandInfo690}, // Inst #10528 = CSRRWI + {2, OperandInfo60}, // Inst #10529 = CTZ + {2, OperandInfo60}, // Inst #10530 = CTZW + {3, OperandInfo894}, // Inst #10531 = C_ADD + {3, OperandInfo895}, // Inst #10532 = C_ADDI + {3, OperandInfo896}, // Inst #10533 = C_ADDI16SP + {3, OperandInfo897}, // Inst #10534 = C_ADDI4SPN + {3, OperandInfo895}, // Inst #10535 = C_ADDIW + {3, OperandInfo895}, // Inst #10536 = C_ADDI_HINT_IMM_ZERO + {3, OperandInfo898}, // Inst #10537 = C_ADDI_HINT_X0 + {3, OperandInfo898}, // Inst #10538 = C_ADDI_NOP + {3, OperandInfo899}, // Inst #10539 = C_ADDW + {3, OperandInfo900}, // Inst #10540 = C_ADD_HINT + {3, OperandInfo899}, // Inst #10541 = C_AND + {3, OperandInfo901}, // Inst #10542 = C_ANDI + {2, OperandInfo902}, // Inst #10543 = C_BEQZ + {2, OperandInfo902}, // Inst #10544 = C_BNEZ + {0, NULL}, // Inst #10545 = C_EBREAK + {3, OperandInfo903}, // Inst #10546 = C_FLD + {3, OperandInfo904}, // Inst #10547 = C_FLDSP + {3, OperandInfo905}, // Inst #10548 = C_FLW + {3, OperandInfo906}, // Inst #10549 = C_FLWSP + {3, OperandInfo903}, // Inst #10550 = C_FSD + {3, OperandInfo904}, // Inst #10551 = C_FSDSP + {3, OperandInfo905}, // Inst #10552 = C_FSW + {3, OperandInfo906}, // Inst #10553 = C_FSWSP + {1, OperandInfo47}, // Inst #10554 = C_J + {1, OperandInfo47}, // Inst #10555 = C_JAL + {1, OperandInfo907}, // Inst #10556 = C_JALR + {1, OperandInfo907}, // Inst #10557 = C_JR + {3, OperandInfo908}, // Inst #10558 = C_LD + {3, OperandInfo909}, // Inst #10559 = C_LDSP + {2, OperandInfo910}, // Inst #10560 = C_LI + {2, OperandInfo911}, // Inst #10561 = C_LI_HINT + {2, OperandInfo912}, // Inst #10562 = C_LUI + {2, OperandInfo911}, // Inst #10563 = C_LUI_HINT + {3, OperandInfo908}, // Inst #10564 = C_LW + {3, OperandInfo909}, // Inst #10565 = C_LWSP + {2, OperandInfo913}, // Inst #10566 = C_MV + {2, OperandInfo914}, // Inst #10567 = C_MV_HINT + {0, NULL}, // Inst #10568 = C_NOP + {1, OperandInfo2}, // Inst #10569 = C_NOP_HINT + {3, OperandInfo899}, // Inst #10570 = C_OR + {3, OperandInfo908}, // Inst #10571 = C_SD + {3, OperandInfo915}, // Inst #10572 = C_SDSP + {3, OperandInfo895}, // Inst #10573 = C_SLLI + {2, OperandInfo916}, // Inst #10574 = C_SLLI64_HINT + {3, OperandInfo898}, // Inst #10575 = C_SLLI_HINT + {3, OperandInfo901}, // Inst #10576 = C_SRAI + {2, OperandInfo917}, // Inst #10577 = C_SRAI64_HINT + {3, OperandInfo901}, // Inst #10578 = C_SRLI + {2, OperandInfo917}, // Inst #10579 = C_SRLI64_HINT + {3, OperandInfo899}, // Inst #10580 = C_SUB + {3, OperandInfo899}, // Inst #10581 = C_SUBW + {3, OperandInfo908}, // Inst #10582 = C_SW + {3, OperandInfo915}, // Inst #10583 = C_SWSP + {0, NULL}, // Inst #10584 = C_UNIMP + {3, OperandInfo899}, // Inst #10585 = C_XOR + {3, OperandInfo890}, // Inst #10586 = DIV + {3, OperandInfo890}, // Inst #10587 = DIVU + {3, OperandInfo890}, // Inst #10588 = DIVUW + {3, OperandInfo890}, // Inst #10589 = DIVW + {2, OperandInfo60}, // Inst #10590 = DRET + {0, NULL}, // Inst #10591 = EBREAK + {0, NULL}, // Inst #10592 = ECALL + {4, OperandInfo918}, // Inst #10593 = FADD_D + {4, OperandInfo919}, // Inst #10594 = FADD_H + {4, OperandInfo920}, // Inst #10595 = FADD_S + {2, OperandInfo921}, // Inst #10596 = FCLASS_D + {2, OperandInfo922}, // Inst #10597 = FCLASS_H + {2, OperandInfo923}, // Inst #10598 = FCLASS_S + {2, OperandInfo924}, // Inst #10599 = FCVT_D_H + {3, OperandInfo925}, // Inst #10600 = FCVT_D_L + {3, OperandInfo925}, // Inst #10601 = FCVT_D_LU + {2, OperandInfo926}, // Inst #10602 = FCVT_D_S + {2, OperandInfo927}, // Inst #10603 = FCVT_D_W + {2, OperandInfo927}, // Inst #10604 = FCVT_D_WU + {3, OperandInfo928}, // Inst #10605 = FCVT_H_D + {3, OperandInfo929}, // Inst #10606 = FCVT_H_L + {3, OperandInfo929}, // Inst #10607 = FCVT_H_LU + {3, OperandInfo930}, // Inst #10608 = FCVT_H_S + {3, OperandInfo929}, // Inst #10609 = FCVT_H_W + {3, OperandInfo929}, // Inst #10610 = FCVT_H_WU + {3, OperandInfo52}, // Inst #10611 = FCVT_LU_D + {3, OperandInfo53}, // Inst #10612 = FCVT_LU_H + {3, OperandInfo54}, // Inst #10613 = FCVT_LU_S + {3, OperandInfo52}, // Inst #10614 = FCVT_L_D + {3, OperandInfo53}, // Inst #10615 = FCVT_L_H + {3, OperandInfo54}, // Inst #10616 = FCVT_L_S + {3, OperandInfo931}, // Inst #10617 = FCVT_S_D + {2, OperandInfo932}, // Inst #10618 = FCVT_S_H + {3, OperandInfo933}, // Inst #10619 = FCVT_S_L + {3, OperandInfo933}, // Inst #10620 = FCVT_S_LU + {3, OperandInfo933}, // Inst #10621 = FCVT_S_W + {3, OperandInfo933}, // Inst #10622 = FCVT_S_WU + {3, OperandInfo52}, // Inst #10623 = FCVT_WU_D + {3, OperandInfo53}, // Inst #10624 = FCVT_WU_H + {3, OperandInfo54}, // Inst #10625 = FCVT_WU_S + {3, OperandInfo52}, // Inst #10626 = FCVT_W_D + {3, OperandInfo53}, // Inst #10627 = FCVT_W_H + {3, OperandInfo54}, // Inst #10628 = FCVT_W_S + {4, OperandInfo918}, // Inst #10629 = FDIV_D + {4, OperandInfo919}, // Inst #10630 = FDIV_H + {4, OperandInfo920}, // Inst #10631 = FDIV_S + {2, OperandInfo7}, // Inst #10632 = FENCE + {0, NULL}, // Inst #10633 = FENCE_I + {0, NULL}, // Inst #10634 = FENCE_TSO + {3, OperandInfo934}, // Inst #10635 = FEQ_D + {3, OperandInfo935}, // Inst #10636 = FEQ_H + {3, OperandInfo936}, // Inst #10637 = FEQ_S + {3, OperandInfo925}, // Inst #10638 = FLD + {3, OperandInfo934}, // Inst #10639 = FLE_D + {3, OperandInfo935}, // Inst #10640 = FLE_H + {3, OperandInfo936}, // Inst #10641 = FLE_S + {3, OperandInfo929}, // Inst #10642 = FLH + {3, OperandInfo934}, // Inst #10643 = FLT_D + {3, OperandInfo935}, // Inst #10644 = FLT_H + {3, OperandInfo936}, // Inst #10645 = FLT_S + {3, OperandInfo933}, // Inst #10646 = FLW + {5, OperandInfo937}, // Inst #10647 = FMADD_D + {5, OperandInfo938}, // Inst #10648 = FMADD_H + {5, OperandInfo939}, // Inst #10649 = FMADD_S + {3, OperandInfo940}, // Inst #10650 = FMAX_D + {3, OperandInfo941}, // Inst #10651 = FMAX_H + {3, OperandInfo942}, // Inst #10652 = FMAX_S + {3, OperandInfo940}, // Inst #10653 = FMIN_D + {3, OperandInfo941}, // Inst #10654 = FMIN_H + {3, OperandInfo942}, // Inst #10655 = FMIN_S + {5, OperandInfo937}, // Inst #10656 = FMSUB_D + {5, OperandInfo938}, // Inst #10657 = FMSUB_H + {5, OperandInfo939}, // Inst #10658 = FMSUB_S + {4, OperandInfo918}, // Inst #10659 = FMUL_D + {4, OperandInfo919}, // Inst #10660 = FMUL_H + {4, OperandInfo920}, // Inst #10661 = FMUL_S + {2, OperandInfo927}, // Inst #10662 = FMV_D_X + {2, OperandInfo943}, // Inst #10663 = FMV_H_X + {2, OperandInfo944}, // Inst #10664 = FMV_W_X + {2, OperandInfo921}, // Inst #10665 = FMV_X_D + {2, OperandInfo922}, // Inst #10666 = FMV_X_H + {2, OperandInfo923}, // Inst #10667 = FMV_X_W + {5, OperandInfo937}, // Inst #10668 = FNMADD_D + {5, OperandInfo938}, // Inst #10669 = FNMADD_H + {5, OperandInfo939}, // Inst #10670 = FNMADD_S + {5, OperandInfo937}, // Inst #10671 = FNMSUB_D + {5, OperandInfo938}, // Inst #10672 = FNMSUB_H + {5, OperandInfo939}, // Inst #10673 = FNMSUB_S + {3, OperandInfo925}, // Inst #10674 = FSD + {3, OperandInfo940}, // Inst #10675 = FSGNJN_D + {3, OperandInfo941}, // Inst #10676 = FSGNJN_H + {3, OperandInfo942}, // Inst #10677 = FSGNJN_S + {3, OperandInfo940}, // Inst #10678 = FSGNJX_D + {3, OperandInfo941}, // Inst #10679 = FSGNJX_H + {3, OperandInfo942}, // Inst #10680 = FSGNJX_S + {3, OperandInfo940}, // Inst #10681 = FSGNJ_D + {3, OperandInfo941}, // Inst #10682 = FSGNJ_H + {3, OperandInfo942}, // Inst #10683 = FSGNJ_S + {3, OperandInfo929}, // Inst #10684 = FSH + {4, OperandInfo892}, // Inst #10685 = FSL + {4, OperandInfo892}, // Inst #10686 = FSLW + {3, OperandInfo945}, // Inst #10687 = FSQRT_D + {3, OperandInfo946}, // Inst #10688 = FSQRT_H + {3, OperandInfo947}, // Inst #10689 = FSQRT_S + {4, OperandInfo892}, // Inst #10690 = FSR + {4, OperandInfo45}, // Inst #10691 = FSRI + {4, OperandInfo45}, // Inst #10692 = FSRIW + {4, OperandInfo892}, // Inst #10693 = FSRW + {4, OperandInfo918}, // Inst #10694 = FSUB_D + {4, OperandInfo919}, // Inst #10695 = FSUB_H + {4, OperandInfo920}, // Inst #10696 = FSUB_S + {3, OperandInfo933}, // Inst #10697 = FSW + {3, OperandInfo890}, // Inst #10698 = GORC + {3, OperandInfo59}, // Inst #10699 = GORCI + {3, OperandInfo59}, // Inst #10700 = GORCIW + {3, OperandInfo890}, // Inst #10701 = GORCW + {3, OperandInfo890}, // Inst #10702 = GREV + {3, OperandInfo59}, // Inst #10703 = GREVI + {3, OperandInfo59}, // Inst #10704 = GREVIW + {3, OperandInfo890}, // Inst #10705 = GREVW + {5, OperandInfo948}, // Inst #10706 = InsnB + {5, OperandInfo949}, // Inst #10707 = InsnI + {5, OperandInfo949}, // Inst #10708 = InsnI_Mem + {3, OperandInfo950}, // Inst #10709 = InsnJ + {6, OperandInfo951}, // Inst #10710 = InsnR + {7, OperandInfo952}, // Inst #10711 = InsnR4 + {5, OperandInfo953}, // Inst #10712 = InsnS + {3, OperandInfo954}, // Inst #10713 = InsnU + {2, OperandInfo955}, // Inst #10714 = JAL + {3, OperandInfo59}, // Inst #10715 = JALR + {3, OperandInfo59}, // Inst #10716 = LB + {3, OperandInfo59}, // Inst #10717 = LBU + {3, OperandInfo59}, // Inst #10718 = LD + {3, OperandInfo59}, // Inst #10719 = LH + {3, OperandInfo59}, // Inst #10720 = LHU + {2, OperandInfo60}, // Inst #10721 = LR_D + {2, OperandInfo60}, // Inst #10722 = LR_D_AQ + {2, OperandInfo60}, // Inst #10723 = LR_D_AQ_RL + {2, OperandInfo60}, // Inst #10724 = LR_D_RL + {2, OperandInfo60}, // Inst #10725 = LR_W + {2, OperandInfo60}, // Inst #10726 = LR_W_AQ + {2, OperandInfo60}, // Inst #10727 = LR_W_AQ_RL + {2, OperandInfo60}, // Inst #10728 = LR_W_RL + {2, OperandInfo50}, // Inst #10729 = LUI + {3, OperandInfo59}, // Inst #10730 = LW + {3, OperandInfo59}, // Inst #10731 = LWU + {3, OperandInfo890}, // Inst #10732 = MAX + {3, OperandInfo890}, // Inst #10733 = MAXU + {3, OperandInfo890}, // Inst #10734 = MIN + {3, OperandInfo890}, // Inst #10735 = MINU + {2, OperandInfo60}, // Inst #10736 = MRET + {3, OperandInfo890}, // Inst #10737 = MUL + {3, OperandInfo890}, // Inst #10738 = MULH + {3, OperandInfo890}, // Inst #10739 = MULHSU + {3, OperandInfo890}, // Inst #10740 = MULHU + {3, OperandInfo890}, // Inst #10741 = MULW + {3, OperandInfo890}, // Inst #10742 = OR + {2, OperandInfo60}, // Inst #10743 = ORCB + {3, OperandInfo59}, // Inst #10744 = ORI + {3, OperandInfo890}, // Inst #10745 = ORN + {3, OperandInfo890}, // Inst #10746 = PACK + {3, OperandInfo890}, // Inst #10747 = PACKH + {3, OperandInfo890}, // Inst #10748 = PACKU + {3, OperandInfo890}, // Inst #10749 = PACKUW + {3, OperandInfo890}, // Inst #10750 = PACKW + {3, OperandInfo890}, // Inst #10751 = REM + {3, OperandInfo890}, // Inst #10752 = REMU + {3, OperandInfo890}, // Inst #10753 = REMUW + {3, OperandInfo890}, // Inst #10754 = REMW + {2, OperandInfo60}, // Inst #10755 = REV8_RV32 + {2, OperandInfo60}, // Inst #10756 = REV8_RV64 + {3, OperandInfo890}, // Inst #10757 = ROL + {3, OperandInfo890}, // Inst #10758 = ROLW + {3, OperandInfo890}, // Inst #10759 = ROR + {3, OperandInfo59}, // Inst #10760 = RORI + {3, OperandInfo59}, // Inst #10761 = RORIW + {3, OperandInfo890}, // Inst #10762 = RORW + {3, OperandInfo59}, // Inst #10763 = SB + {3, OperandInfo890}, // Inst #10764 = SC_D + {3, OperandInfo890}, // Inst #10765 = SC_D_AQ + {3, OperandInfo890}, // Inst #10766 = SC_D_AQ_RL + {3, OperandInfo890}, // Inst #10767 = SC_D_RL + {3, OperandInfo890}, // Inst #10768 = SC_W + {3, OperandInfo890}, // Inst #10769 = SC_W_AQ + {3, OperandInfo890}, // Inst #10770 = SC_W_AQ_RL + {3, OperandInfo890}, // Inst #10771 = SC_W_RL + {3, OperandInfo59}, // Inst #10772 = SD + {2, OperandInfo60}, // Inst #10773 = SEXTB + {2, OperandInfo60}, // Inst #10774 = SEXTH + {2, OperandInfo60}, // Inst #10775 = SFENCE_VMA + {3, OperandInfo59}, // Inst #10776 = SH + {3, OperandInfo890}, // Inst #10777 = SH1ADD + {3, OperandInfo890}, // Inst #10778 = SH1ADDUW + {3, OperandInfo890}, // Inst #10779 = SH2ADD + {3, OperandInfo890}, // Inst #10780 = SH2ADDUW + {3, OperandInfo890}, // Inst #10781 = SH3ADD + {3, OperandInfo890}, // Inst #10782 = SH3ADDUW + {3, OperandInfo890}, // Inst #10783 = SHFL + {3, OperandInfo59}, // Inst #10784 = SHFLI + {3, OperandInfo890}, // Inst #10785 = SHFLW + {3, OperandInfo890}, // Inst #10786 = SLL + {3, OperandInfo59}, // Inst #10787 = SLLI + {3, OperandInfo59}, // Inst #10788 = SLLIUW + {3, OperandInfo59}, // Inst #10789 = SLLIW + {3, OperandInfo890}, // Inst #10790 = SLLW + {3, OperandInfo890}, // Inst #10791 = SLT + {3, OperandInfo59}, // Inst #10792 = SLTI + {3, OperandInfo59}, // Inst #10793 = SLTIU + {3, OperandInfo890}, // Inst #10794 = SLTU + {3, OperandInfo890}, // Inst #10795 = SRA + {3, OperandInfo59}, // Inst #10796 = SRAI + {3, OperandInfo59}, // Inst #10797 = SRAIW + {3, OperandInfo890}, // Inst #10798 = SRAW + {2, OperandInfo60}, // Inst #10799 = SRET + {3, OperandInfo890}, // Inst #10800 = SRL + {3, OperandInfo59}, // Inst #10801 = SRLI + {3, OperandInfo59}, // Inst #10802 = SRLIW + {3, OperandInfo890}, // Inst #10803 = SRLW + {3, OperandInfo890}, // Inst #10804 = SUB + {3, OperandInfo890}, // Inst #10805 = SUBW + {3, OperandInfo59}, // Inst #10806 = SW + {0, NULL}, // Inst #10807 = UNIMP + {3, OperandInfo890}, // Inst #10808 = UNSHFL + {3, OperandInfo59}, // Inst #10809 = UNSHFLI + {3, OperandInfo890}, // Inst #10810 = UNSHFLW + {2, OperandInfo60}, // Inst #10811 = URET + {4, OperandInfo956}, // Inst #10812 = VAADDU_VV + {4, OperandInfo957}, // Inst #10813 = VAADDU_VX + {4, OperandInfo956}, // Inst #10814 = VAADD_VV + {4, OperandInfo957}, // Inst #10815 = VAADD_VX + {4, OperandInfo605}, // Inst #10816 = VADC_VIM + {4, OperandInfo956}, // Inst #10817 = VADC_VVM + {4, OperandInfo957}, // Inst #10818 = VADC_VXM + {4, OperandInfo605}, // Inst #10819 = VADD_VI + {4, OperandInfo956}, // Inst #10820 = VADD_VV + {4, OperandInfo957}, // Inst #10821 = VADD_VX + {4, OperandInfo958}, // Inst #10822 = VAMOADDEI16_UNWD + {5, OperandInfo959}, // Inst #10823 = VAMOADDEI16_WD + {4, OperandInfo958}, // Inst #10824 = VAMOADDEI32_UNWD + {5, OperandInfo959}, // Inst #10825 = VAMOADDEI32_WD + {4, OperandInfo958}, // Inst #10826 = VAMOADDEI64_UNWD + {5, OperandInfo959}, // Inst #10827 = VAMOADDEI64_WD + {4, OperandInfo958}, // Inst #10828 = VAMOADDEI8_UNWD + {5, OperandInfo959}, // Inst #10829 = VAMOADDEI8_WD + {4, OperandInfo958}, // Inst #10830 = VAMOANDEI16_UNWD + {5, OperandInfo959}, // Inst #10831 = VAMOANDEI16_WD + {4, OperandInfo958}, // Inst #10832 = VAMOANDEI32_UNWD + {5, OperandInfo959}, // Inst #10833 = VAMOANDEI32_WD + {4, OperandInfo958}, // Inst #10834 = VAMOANDEI64_UNWD + {5, OperandInfo959}, // Inst #10835 = VAMOANDEI64_WD + {4, OperandInfo958}, // Inst #10836 = VAMOANDEI8_UNWD + {5, OperandInfo959}, // Inst #10837 = VAMOANDEI8_WD + {4, OperandInfo958}, // Inst #10838 = VAMOMAXEI16_UNWD + {5, OperandInfo959}, // Inst #10839 = VAMOMAXEI16_WD + {4, OperandInfo958}, // Inst #10840 = VAMOMAXEI32_UNWD + {5, OperandInfo959}, // Inst #10841 = VAMOMAXEI32_WD + {4, OperandInfo958}, // Inst #10842 = VAMOMAXEI64_UNWD + {5, OperandInfo959}, // Inst #10843 = VAMOMAXEI64_WD + {4, OperandInfo958}, // Inst #10844 = VAMOMAXEI8_UNWD + {5, OperandInfo959}, // Inst #10845 = VAMOMAXEI8_WD + {4, OperandInfo958}, // Inst #10846 = VAMOMAXUEI16_UNWD + {5, OperandInfo959}, // Inst #10847 = VAMOMAXUEI16_WD + {4, OperandInfo958}, // Inst #10848 = VAMOMAXUEI32_UNWD + {5, OperandInfo959}, // Inst #10849 = VAMOMAXUEI32_WD + {4, OperandInfo958}, // Inst #10850 = VAMOMAXUEI64_UNWD + {5, OperandInfo959}, // Inst #10851 = VAMOMAXUEI64_WD + {4, OperandInfo958}, // Inst #10852 = VAMOMAXUEI8_UNWD + {5, OperandInfo959}, // Inst #10853 = VAMOMAXUEI8_WD + {4, OperandInfo958}, // Inst #10854 = VAMOMINEI16_UNWD + {5, OperandInfo959}, // Inst #10855 = VAMOMINEI16_WD + {4, OperandInfo958}, // Inst #10856 = VAMOMINEI32_UNWD + {5, OperandInfo959}, // Inst #10857 = VAMOMINEI32_WD + {4, OperandInfo958}, // Inst #10858 = VAMOMINEI64_UNWD + {5, OperandInfo959}, // Inst #10859 = VAMOMINEI64_WD + {4, OperandInfo958}, // Inst #10860 = VAMOMINEI8_UNWD + {5, OperandInfo959}, // Inst #10861 = VAMOMINEI8_WD + {4, OperandInfo958}, // Inst #10862 = VAMOMINUEI16_UNWD + {5, OperandInfo959}, // Inst #10863 = VAMOMINUEI16_WD + {4, OperandInfo958}, // Inst #10864 = VAMOMINUEI32_UNWD + {5, OperandInfo959}, // Inst #10865 = VAMOMINUEI32_WD + {4, OperandInfo958}, // Inst #10866 = VAMOMINUEI64_UNWD + {5, OperandInfo959}, // Inst #10867 = VAMOMINUEI64_WD + {4, OperandInfo958}, // Inst #10868 = VAMOMINUEI8_UNWD + {5, OperandInfo959}, // Inst #10869 = VAMOMINUEI8_WD + {4, OperandInfo958}, // Inst #10870 = VAMOOREI16_UNWD + {5, OperandInfo959}, // Inst #10871 = VAMOOREI16_WD + {4, OperandInfo958}, // Inst #10872 = VAMOOREI32_UNWD + {5, OperandInfo959}, // Inst #10873 = VAMOOREI32_WD + {4, OperandInfo958}, // Inst #10874 = VAMOOREI64_UNWD + {5, OperandInfo959}, // Inst #10875 = VAMOOREI64_WD + {4, OperandInfo958}, // Inst #10876 = VAMOOREI8_UNWD + {5, OperandInfo959}, // Inst #10877 = VAMOOREI8_WD + {4, OperandInfo958}, // Inst #10878 = VAMOSWAPEI16_UNWD + {5, OperandInfo959}, // Inst #10879 = VAMOSWAPEI16_WD + {4, OperandInfo958}, // Inst #10880 = VAMOSWAPEI32_UNWD + {5, OperandInfo959}, // Inst #10881 = VAMOSWAPEI32_WD + {4, OperandInfo958}, // Inst #10882 = VAMOSWAPEI64_UNWD + {5, OperandInfo959}, // Inst #10883 = VAMOSWAPEI64_WD + {4, OperandInfo958}, // Inst #10884 = VAMOSWAPEI8_UNWD + {5, OperandInfo959}, // Inst #10885 = VAMOSWAPEI8_WD + {4, OperandInfo958}, // Inst #10886 = VAMOXOREI16_UNWD + {5, OperandInfo959}, // Inst #10887 = VAMOXOREI16_WD + {4, OperandInfo958}, // Inst #10888 = VAMOXOREI32_UNWD + {5, OperandInfo959}, // Inst #10889 = VAMOXOREI32_WD + {4, OperandInfo958}, // Inst #10890 = VAMOXOREI64_UNWD + {5, OperandInfo959}, // Inst #10891 = VAMOXOREI64_WD + {4, OperandInfo958}, // Inst #10892 = VAMOXOREI8_UNWD + {5, OperandInfo959}, // Inst #10893 = VAMOXOREI8_WD + {4, OperandInfo605}, // Inst #10894 = VAND_VI + {4, OperandInfo956}, // Inst #10895 = VAND_VV + {4, OperandInfo957}, // Inst #10896 = VAND_VX + {4, OperandInfo956}, // Inst #10897 = VASUBU_VV + {4, OperandInfo957}, // Inst #10898 = VASUBU_VX + {4, OperandInfo956}, // Inst #10899 = VASUB_VV + {4, OperandInfo957}, // Inst #10900 = VASUB_VX + {3, OperandInfo960}, // Inst #10901 = VCOMPRESS_VM + {3, OperandInfo961}, // Inst #10902 = VCPOP_M + {4, OperandInfo956}, // Inst #10903 = VDIVU_VV + {4, OperandInfo957}, // Inst #10904 = VDIVU_VX + {4, OperandInfo956}, // Inst #10905 = VDIV_VV + {4, OperandInfo957}, // Inst #10906 = VDIV_VX + {4, OperandInfo962}, // Inst #10907 = VFADD_VF + {4, OperandInfo956}, // Inst #10908 = VFADD_VV + {3, OperandInfo963}, // Inst #10909 = VFCLASS_V + {3, OperandInfo963}, // Inst #10910 = VFCVT_F_XU_V + {3, OperandInfo963}, // Inst #10911 = VFCVT_F_X_V + {3, OperandInfo963}, // Inst #10912 = VFCVT_RTZ_XU_F_V + {3, OperandInfo963}, // Inst #10913 = VFCVT_RTZ_X_F_V + {3, OperandInfo963}, // Inst #10914 = VFCVT_XU_F_V + {3, OperandInfo963}, // Inst #10915 = VFCVT_X_F_V + {4, OperandInfo962}, // Inst #10916 = VFDIV_VF + {4, OperandInfo956}, // Inst #10917 = VFDIV_VV + {3, OperandInfo961}, // Inst #10918 = VFIRST_M + {4, OperandInfo964}, // Inst #10919 = VFMACC_VF + {4, OperandInfo956}, // Inst #10920 = VFMACC_VV + {4, OperandInfo964}, // Inst #10921 = VFMADD_VF + {4, OperandInfo956}, // Inst #10922 = VFMADD_VV + {4, OperandInfo962}, // Inst #10923 = VFMAX_VF + {4, OperandInfo956}, // Inst #10924 = VFMAX_VV + {4, OperandInfo962}, // Inst #10925 = VFMERGE_VFM + {4, OperandInfo962}, // Inst #10926 = VFMIN_VF + {4, OperandInfo956}, // Inst #10927 = VFMIN_VV + {4, OperandInfo964}, // Inst #10928 = VFMSAC_VF + {4, OperandInfo956}, // Inst #10929 = VFMSAC_VV + {4, OperandInfo964}, // Inst #10930 = VFMSUB_VF + {4, OperandInfo956}, // Inst #10931 = VFMSUB_VV + {4, OperandInfo962}, // Inst #10932 = VFMUL_VF + {4, OperandInfo956}, // Inst #10933 = VFMUL_VV + {2, OperandInfo965}, // Inst #10934 = VFMV_F_S + {3, OperandInfo966}, // Inst #10935 = VFMV_S_F + {2, OperandInfo967}, // Inst #10936 = VFMV_V_F + {3, OperandInfo968}, // Inst #10937 = VFNCVT_F_F_W + {3, OperandInfo968}, // Inst #10938 = VFNCVT_F_XU_W + {3, OperandInfo968}, // Inst #10939 = VFNCVT_F_X_W + {3, OperandInfo968}, // Inst #10940 = VFNCVT_ROD_F_F_W + {3, OperandInfo968}, // Inst #10941 = VFNCVT_RTZ_XU_F_W + {3, OperandInfo968}, // Inst #10942 = VFNCVT_RTZ_X_F_W + {3, OperandInfo968}, // Inst #10943 = VFNCVT_XU_F_W + {3, OperandInfo968}, // Inst #10944 = VFNCVT_X_F_W + {4, OperandInfo964}, // Inst #10945 = VFNMACC_VF + {4, OperandInfo956}, // Inst #10946 = VFNMACC_VV + {4, OperandInfo964}, // Inst #10947 = VFNMADD_VF + {4, OperandInfo956}, // Inst #10948 = VFNMADD_VV + {4, OperandInfo964}, // Inst #10949 = VFNMSAC_VF + {4, OperandInfo956}, // Inst #10950 = VFNMSAC_VV + {4, OperandInfo964}, // Inst #10951 = VFNMSUB_VF + {4, OperandInfo956}, // Inst #10952 = VFNMSUB_VV + {4, OperandInfo962}, // Inst #10953 = VFRDIV_VF + {3, OperandInfo963}, // Inst #10954 = VFREC7_V + {4, OperandInfo956}, // Inst #10955 = VFREDMAX_VS + {4, OperandInfo956}, // Inst #10956 = VFREDMIN_VS + {4, OperandInfo956}, // Inst #10957 = VFREDOSUM_VS + {4, OperandInfo956}, // Inst #10958 = VFREDUSUM_VS + {3, OperandInfo963}, // Inst #10959 = VFRSQRT7_V + {4, OperandInfo962}, // Inst #10960 = VFRSUB_VF + {4, OperandInfo962}, // Inst #10961 = VFSGNJN_VF + {4, OperandInfo956}, // Inst #10962 = VFSGNJN_VV + {4, OperandInfo962}, // Inst #10963 = VFSGNJX_VF + {4, OperandInfo956}, // Inst #10964 = VFSGNJX_VV + {4, OperandInfo962}, // Inst #10965 = VFSGNJ_VF + {4, OperandInfo956}, // Inst #10966 = VFSGNJ_VV + {4, OperandInfo962}, // Inst #10967 = VFSLIDE1DOWN_VF + {4, OperandInfo969}, // Inst #10968 = VFSLIDE1UP_VF + {3, OperandInfo963}, // Inst #10969 = VFSQRT_V + {4, OperandInfo962}, // Inst #10970 = VFSUB_VF + {4, OperandInfo956}, // Inst #10971 = VFSUB_VV + {4, OperandInfo969}, // Inst #10972 = VFWADD_VF + {4, OperandInfo970}, // Inst #10973 = VFWADD_VV + {4, OperandInfo969}, // Inst #10974 = VFWADD_WF + {4, OperandInfo970}, // Inst #10975 = VFWADD_WV + {3, OperandInfo968}, // Inst #10976 = VFWCVT_F_F_V + {3, OperandInfo968}, // Inst #10977 = VFWCVT_F_XU_V + {3, OperandInfo968}, // Inst #10978 = VFWCVT_F_X_V + {3, OperandInfo968}, // Inst #10979 = VFWCVT_RTZ_XU_F_V + {3, OperandInfo968}, // Inst #10980 = VFWCVT_RTZ_X_F_V + {3, OperandInfo968}, // Inst #10981 = VFWCVT_XU_F_V + {3, OperandInfo968}, // Inst #10982 = VFWCVT_X_F_V + {4, OperandInfo971}, // Inst #10983 = VFWMACC_VF + {4, OperandInfo970}, // Inst #10984 = VFWMACC_VV + {4, OperandInfo971}, // Inst #10985 = VFWMSAC_VF + {4, OperandInfo970}, // Inst #10986 = VFWMSAC_VV + {4, OperandInfo969}, // Inst #10987 = VFWMUL_VF + {4, OperandInfo970}, // Inst #10988 = VFWMUL_VV + {4, OperandInfo971}, // Inst #10989 = VFWNMACC_VF + {4, OperandInfo970}, // Inst #10990 = VFWNMACC_VV + {4, OperandInfo971}, // Inst #10991 = VFWNMSAC_VF + {4, OperandInfo970}, // Inst #10992 = VFWNMSAC_VV + {4, OperandInfo970}, // Inst #10993 = VFWREDOSUM_VS + {4, OperandInfo970}, // Inst #10994 = VFWREDUSUM_VS + {4, OperandInfo969}, // Inst #10995 = VFWSUB_VF + {4, OperandInfo970}, // Inst #10996 = VFWSUB_VV + {4, OperandInfo969}, // Inst #10997 = VFWSUB_WF + {4, OperandInfo970}, // Inst #10998 = VFWSUB_WV + {2, OperandInfo972}, // Inst #10999 = VID_V + {3, OperandInfo968}, // Inst #11000 = VIOTA_M + {2, OperandInfo652}, // Inst #11001 = VL1RE16_V + {2, OperandInfo652}, // Inst #11002 = VL1RE32_V + {2, OperandInfo652}, // Inst #11003 = VL1RE64_V + {2, OperandInfo652}, // Inst #11004 = VL1RE8_V + {2, OperandInfo653}, // Inst #11005 = VL2RE16_V + {2, OperandInfo653}, // Inst #11006 = VL2RE32_V + {2, OperandInfo653}, // Inst #11007 = VL2RE64_V + {2, OperandInfo653}, // Inst #11008 = VL2RE8_V + {2, OperandInfo654}, // Inst #11009 = VL4RE16_V + {2, OperandInfo654}, // Inst #11010 = VL4RE32_V + {2, OperandInfo654}, // Inst #11011 = VL4RE64_V + {2, OperandInfo654}, // Inst #11012 = VL4RE8_V + {2, OperandInfo655}, // Inst #11013 = VL8RE16_V + {2, OperandInfo655}, // Inst #11014 = VL8RE32_V + {2, OperandInfo655}, // Inst #11015 = VL8RE64_V + {2, OperandInfo655}, // Inst #11016 = VL8RE8_V + {3, OperandInfo973}, // Inst #11017 = VLE16FF_V + {3, OperandInfo973}, // Inst #11018 = VLE16_V + {3, OperandInfo973}, // Inst #11019 = VLE32FF_V + {3, OperandInfo973}, // Inst #11020 = VLE32_V + {3, OperandInfo973}, // Inst #11021 = VLE64FF_V + {3, OperandInfo973}, // Inst #11022 = VLE64_V + {3, OperandInfo973}, // Inst #11023 = VLE8FF_V + {3, OperandInfo973}, // Inst #11024 = VLE8_V + {2, OperandInfo652}, // Inst #11025 = VLM_V + {4, OperandInfo974}, // Inst #11026 = VLOXEI16_V + {4, OperandInfo974}, // Inst #11027 = VLOXEI32_V + {4, OperandInfo974}, // Inst #11028 = VLOXEI64_V + {4, OperandInfo974}, // Inst #11029 = VLOXEI8_V + {4, OperandInfo974}, // Inst #11030 = VLOXSEG2EI16_V + {4, OperandInfo974}, // Inst #11031 = VLOXSEG2EI32_V + {4, OperandInfo974}, // Inst #11032 = VLOXSEG2EI64_V + {4, OperandInfo974}, // Inst #11033 = VLOXSEG2EI8_V + {4, OperandInfo974}, // Inst #11034 = VLOXSEG3EI16_V + {4, OperandInfo974}, // Inst #11035 = VLOXSEG3EI32_V + {4, OperandInfo974}, // Inst #11036 = VLOXSEG3EI64_V + {4, OperandInfo974}, // Inst #11037 = VLOXSEG3EI8_V + {4, OperandInfo974}, // Inst #11038 = VLOXSEG4EI16_V + {4, OperandInfo974}, // Inst #11039 = VLOXSEG4EI32_V + {4, OperandInfo974}, // Inst #11040 = VLOXSEG4EI64_V + {4, OperandInfo974}, // Inst #11041 = VLOXSEG4EI8_V + {4, OperandInfo974}, // Inst #11042 = VLOXSEG5EI16_V + {4, OperandInfo974}, // Inst #11043 = VLOXSEG5EI32_V + {4, OperandInfo974}, // Inst #11044 = VLOXSEG5EI64_V + {4, OperandInfo974}, // Inst #11045 = VLOXSEG5EI8_V + {4, OperandInfo974}, // Inst #11046 = VLOXSEG6EI16_V + {4, OperandInfo974}, // Inst #11047 = VLOXSEG6EI32_V + {4, OperandInfo974}, // Inst #11048 = VLOXSEG6EI64_V + {4, OperandInfo974}, // Inst #11049 = VLOXSEG6EI8_V + {4, OperandInfo974}, // Inst #11050 = VLOXSEG7EI16_V + {4, OperandInfo974}, // Inst #11051 = VLOXSEG7EI32_V + {4, OperandInfo974}, // Inst #11052 = VLOXSEG7EI64_V + {4, OperandInfo974}, // Inst #11053 = VLOXSEG7EI8_V + {4, OperandInfo974}, // Inst #11054 = VLOXSEG8EI16_V + {4, OperandInfo974}, // Inst #11055 = VLOXSEG8EI32_V + {4, OperandInfo974}, // Inst #11056 = VLOXSEG8EI64_V + {4, OperandInfo974}, // Inst #11057 = VLOXSEG8EI8_V + {4, OperandInfo975}, // Inst #11058 = VLSE16_V + {4, OperandInfo975}, // Inst #11059 = VLSE32_V + {4, OperandInfo975}, // Inst #11060 = VLSE64_V + {4, OperandInfo975}, // Inst #11061 = VLSE8_V + {3, OperandInfo973}, // Inst #11062 = VLSEG2E16FF_V + {3, OperandInfo973}, // Inst #11063 = VLSEG2E16_V + {3, OperandInfo973}, // Inst #11064 = VLSEG2E32FF_V + {3, OperandInfo973}, // Inst #11065 = VLSEG2E32_V + {3, OperandInfo973}, // Inst #11066 = VLSEG2E64FF_V + {3, OperandInfo973}, // Inst #11067 = VLSEG2E64_V + {3, OperandInfo973}, // Inst #11068 = VLSEG2E8FF_V + {3, OperandInfo973}, // Inst #11069 = VLSEG2E8_V + {3, OperandInfo973}, // Inst #11070 = VLSEG3E16FF_V + {3, OperandInfo973}, // Inst #11071 = VLSEG3E16_V + {3, OperandInfo973}, // Inst #11072 = VLSEG3E32FF_V + {3, OperandInfo973}, // Inst #11073 = VLSEG3E32_V + {3, OperandInfo973}, // Inst #11074 = VLSEG3E64FF_V + {3, OperandInfo973}, // Inst #11075 = VLSEG3E64_V + {3, OperandInfo973}, // Inst #11076 = VLSEG3E8FF_V + {3, OperandInfo973}, // Inst #11077 = VLSEG3E8_V + {3, OperandInfo973}, // Inst #11078 = VLSEG4E16FF_V + {3, OperandInfo973}, // Inst #11079 = VLSEG4E16_V + {3, OperandInfo973}, // Inst #11080 = VLSEG4E32FF_V + {3, OperandInfo973}, // Inst #11081 = VLSEG4E32_V + {3, OperandInfo973}, // Inst #11082 = VLSEG4E64FF_V + {3, OperandInfo973}, // Inst #11083 = VLSEG4E64_V + {3, OperandInfo973}, // Inst #11084 = VLSEG4E8FF_V + {3, OperandInfo973}, // Inst #11085 = VLSEG4E8_V + {3, OperandInfo973}, // Inst #11086 = VLSEG5E16FF_V + {3, OperandInfo973}, // Inst #11087 = VLSEG5E16_V + {3, OperandInfo973}, // Inst #11088 = VLSEG5E32FF_V + {3, OperandInfo973}, // Inst #11089 = VLSEG5E32_V + {3, OperandInfo973}, // Inst #11090 = VLSEG5E64FF_V + {3, OperandInfo973}, // Inst #11091 = VLSEG5E64_V + {3, OperandInfo973}, // Inst #11092 = VLSEG5E8FF_V + {3, OperandInfo973}, // Inst #11093 = VLSEG5E8_V + {3, OperandInfo973}, // Inst #11094 = VLSEG6E16FF_V + {3, OperandInfo973}, // Inst #11095 = VLSEG6E16_V + {3, OperandInfo973}, // Inst #11096 = VLSEG6E32FF_V + {3, OperandInfo973}, // Inst #11097 = VLSEG6E32_V + {3, OperandInfo973}, // Inst #11098 = VLSEG6E64FF_V + {3, OperandInfo973}, // Inst #11099 = VLSEG6E64_V + {3, OperandInfo973}, // Inst #11100 = VLSEG6E8FF_V + {3, OperandInfo973}, // Inst #11101 = VLSEG6E8_V + {3, OperandInfo973}, // Inst #11102 = VLSEG7E16FF_V + {3, OperandInfo973}, // Inst #11103 = VLSEG7E16_V + {3, OperandInfo973}, // Inst #11104 = VLSEG7E32FF_V + {3, OperandInfo973}, // Inst #11105 = VLSEG7E32_V + {3, OperandInfo973}, // Inst #11106 = VLSEG7E64FF_V + {3, OperandInfo973}, // Inst #11107 = VLSEG7E64_V + {3, OperandInfo973}, // Inst #11108 = VLSEG7E8FF_V + {3, OperandInfo973}, // Inst #11109 = VLSEG7E8_V + {3, OperandInfo973}, // Inst #11110 = VLSEG8E16FF_V + {3, OperandInfo973}, // Inst #11111 = VLSEG8E16_V + {3, OperandInfo973}, // Inst #11112 = VLSEG8E32FF_V + {3, OperandInfo973}, // Inst #11113 = VLSEG8E32_V + {3, OperandInfo973}, // Inst #11114 = VLSEG8E64FF_V + {3, OperandInfo973}, // Inst #11115 = VLSEG8E64_V + {3, OperandInfo973}, // Inst #11116 = VLSEG8E8FF_V + {3, OperandInfo973}, // Inst #11117 = VLSEG8E8_V + {4, OperandInfo975}, // Inst #11118 = VLSSEG2E16_V + {4, OperandInfo975}, // Inst #11119 = VLSSEG2E32_V + {4, OperandInfo975}, // Inst #11120 = VLSSEG2E64_V + {4, OperandInfo975}, // Inst #11121 = VLSSEG2E8_V + {4, OperandInfo975}, // Inst #11122 = VLSSEG3E16_V + {4, OperandInfo975}, // Inst #11123 = VLSSEG3E32_V + {4, OperandInfo975}, // Inst #11124 = VLSSEG3E64_V + {4, OperandInfo975}, // Inst #11125 = VLSSEG3E8_V + {4, OperandInfo975}, // Inst #11126 = VLSSEG4E16_V + {4, OperandInfo975}, // Inst #11127 = VLSSEG4E32_V + {4, OperandInfo975}, // Inst #11128 = VLSSEG4E64_V + {4, OperandInfo975}, // Inst #11129 = VLSSEG4E8_V + {4, OperandInfo975}, // Inst #11130 = VLSSEG5E16_V + {4, OperandInfo975}, // Inst #11131 = VLSSEG5E32_V + {4, OperandInfo975}, // Inst #11132 = VLSSEG5E64_V + {4, OperandInfo975}, // Inst #11133 = VLSSEG5E8_V + {4, OperandInfo975}, // Inst #11134 = VLSSEG6E16_V + {4, OperandInfo975}, // Inst #11135 = VLSSEG6E32_V + {4, OperandInfo975}, // Inst #11136 = VLSSEG6E64_V + {4, OperandInfo975}, // Inst #11137 = VLSSEG6E8_V + {4, OperandInfo975}, // Inst #11138 = VLSSEG7E16_V + {4, OperandInfo975}, // Inst #11139 = VLSSEG7E32_V + {4, OperandInfo975}, // Inst #11140 = VLSSEG7E64_V + {4, OperandInfo975}, // Inst #11141 = VLSSEG7E8_V + {4, OperandInfo975}, // Inst #11142 = VLSSEG8E16_V + {4, OperandInfo975}, // Inst #11143 = VLSSEG8E32_V + {4, OperandInfo975}, // Inst #11144 = VLSSEG8E64_V + {4, OperandInfo975}, // Inst #11145 = VLSSEG8E8_V + {4, OperandInfo974}, // Inst #11146 = VLUXEI16_V + {4, OperandInfo974}, // Inst #11147 = VLUXEI32_V + {4, OperandInfo974}, // Inst #11148 = VLUXEI64_V + {4, OperandInfo974}, // Inst #11149 = VLUXEI8_V + {4, OperandInfo974}, // Inst #11150 = VLUXSEG2EI16_V + {4, OperandInfo974}, // Inst #11151 = VLUXSEG2EI32_V + {4, OperandInfo974}, // Inst #11152 = VLUXSEG2EI64_V + {4, OperandInfo974}, // Inst #11153 = VLUXSEG2EI8_V + {4, OperandInfo974}, // Inst #11154 = VLUXSEG3EI16_V + {4, OperandInfo974}, // Inst #11155 = VLUXSEG3EI32_V + {4, OperandInfo974}, // Inst #11156 = VLUXSEG3EI64_V + {4, OperandInfo974}, // Inst #11157 = VLUXSEG3EI8_V + {4, OperandInfo974}, // Inst #11158 = VLUXSEG4EI16_V + {4, OperandInfo974}, // Inst #11159 = VLUXSEG4EI32_V + {4, OperandInfo974}, // Inst #11160 = VLUXSEG4EI64_V + {4, OperandInfo974}, // Inst #11161 = VLUXSEG4EI8_V + {4, OperandInfo974}, // Inst #11162 = VLUXSEG5EI16_V + {4, OperandInfo974}, // Inst #11163 = VLUXSEG5EI32_V + {4, OperandInfo974}, // Inst #11164 = VLUXSEG5EI64_V + {4, OperandInfo974}, // Inst #11165 = VLUXSEG5EI8_V + {4, OperandInfo974}, // Inst #11166 = VLUXSEG6EI16_V + {4, OperandInfo974}, // Inst #11167 = VLUXSEG6EI32_V + {4, OperandInfo974}, // Inst #11168 = VLUXSEG6EI64_V + {4, OperandInfo974}, // Inst #11169 = VLUXSEG6EI8_V + {4, OperandInfo974}, // Inst #11170 = VLUXSEG7EI16_V + {4, OperandInfo974}, // Inst #11171 = VLUXSEG7EI32_V + {4, OperandInfo974}, // Inst #11172 = VLUXSEG7EI64_V + {4, OperandInfo974}, // Inst #11173 = VLUXSEG7EI8_V + {4, OperandInfo974}, // Inst #11174 = VLUXSEG8EI16_V + {4, OperandInfo974}, // Inst #11175 = VLUXSEG8EI32_V + {4, OperandInfo974}, // Inst #11176 = VLUXSEG8EI64_V + {4, OperandInfo974}, // Inst #11177 = VLUXSEG8EI8_V + {4, OperandInfo956}, // Inst #11178 = VMACC_VV + {4, OperandInfo974}, // Inst #11179 = VMACC_VX + {3, OperandInfo976}, // Inst #11180 = VMADC_VI + {4, OperandInfo977}, // Inst #11181 = VMADC_VIM + {3, OperandInfo960}, // Inst #11182 = VMADC_VV + {4, OperandInfo970}, // Inst #11183 = VMADC_VVM + {3, OperandInfo978}, // Inst #11184 = VMADC_VX + {4, OperandInfo979}, // Inst #11185 = VMADC_VXM + {4, OperandInfo956}, // Inst #11186 = VMADD_VV + {4, OperandInfo974}, // Inst #11187 = VMADD_VX + {3, OperandInfo980}, // Inst #11188 = VMANDN_MM + {3, OperandInfo980}, // Inst #11189 = VMAND_MM + {4, OperandInfo956}, // Inst #11190 = VMAXU_VV + {4, OperandInfo957}, // Inst #11191 = VMAXU_VX + {4, OperandInfo956}, // Inst #11192 = VMAX_VV + {4, OperandInfo957}, // Inst #11193 = VMAX_VX + {4, OperandInfo605}, // Inst #11194 = VMERGE_VIM + {4, OperandInfo956}, // Inst #11195 = VMERGE_VVM + {4, OperandInfo957}, // Inst #11196 = VMERGE_VXM + {4, OperandInfo962}, // Inst #11197 = VMFEQ_VF + {4, OperandInfo956}, // Inst #11198 = VMFEQ_VV + {4, OperandInfo962}, // Inst #11199 = VMFGE_VF + {4, OperandInfo962}, // Inst #11200 = VMFGT_VF + {4, OperandInfo962}, // Inst #11201 = VMFLE_VF + {4, OperandInfo956}, // Inst #11202 = VMFLE_VV + {4, OperandInfo962}, // Inst #11203 = VMFLT_VF + {4, OperandInfo956}, // Inst #11204 = VMFLT_VV + {4, OperandInfo962}, // Inst #11205 = VMFNE_VF + {4, OperandInfo956}, // Inst #11206 = VMFNE_VV + {4, OperandInfo956}, // Inst #11207 = VMINU_VV + {4, OperandInfo957}, // Inst #11208 = VMINU_VX + {4, OperandInfo956}, // Inst #11209 = VMIN_VV + {4, OperandInfo957}, // Inst #11210 = VMIN_VX + {3, OperandInfo980}, // Inst #11211 = VMNAND_MM + {3, OperandInfo980}, // Inst #11212 = VMNOR_MM + {3, OperandInfo980}, // Inst #11213 = VMORN_MM + {3, OperandInfo980}, // Inst #11214 = VMOR_MM + {3, OperandInfo960}, // Inst #11215 = VMSBC_VV + {4, OperandInfo970}, // Inst #11216 = VMSBC_VVM + {3, OperandInfo978}, // Inst #11217 = VMSBC_VX + {4, OperandInfo979}, // Inst #11218 = VMSBC_VXM + {3, OperandInfo968}, // Inst #11219 = VMSBF_M + {4, OperandInfo605}, // Inst #11220 = VMSEQ_VI + {4, OperandInfo956}, // Inst #11221 = VMSEQ_VV + {4, OperandInfo957}, // Inst #11222 = VMSEQ_VX + {4, OperandInfo605}, // Inst #11223 = VMSGTU_VI + {4, OperandInfo957}, // Inst #11224 = VMSGTU_VX + {4, OperandInfo605}, // Inst #11225 = VMSGT_VI + {4, OperandInfo957}, // Inst #11226 = VMSGT_VX + {3, OperandInfo968}, // Inst #11227 = VMSIF_M + {4, OperandInfo605}, // Inst #11228 = VMSLEU_VI + {4, OperandInfo956}, // Inst #11229 = VMSLEU_VV + {4, OperandInfo957}, // Inst #11230 = VMSLEU_VX + {4, OperandInfo605}, // Inst #11231 = VMSLE_VI + {4, OperandInfo956}, // Inst #11232 = VMSLE_VV + {4, OperandInfo957}, // Inst #11233 = VMSLE_VX + {4, OperandInfo956}, // Inst #11234 = VMSLTU_VV + {4, OperandInfo957}, // Inst #11235 = VMSLTU_VX + {4, OperandInfo956}, // Inst #11236 = VMSLT_VV + {4, OperandInfo957}, // Inst #11237 = VMSLT_VX + {4, OperandInfo605}, // Inst #11238 = VMSNE_VI + {4, OperandInfo956}, // Inst #11239 = VMSNE_VV + {4, OperandInfo957}, // Inst #11240 = VMSNE_VX + {3, OperandInfo968}, // Inst #11241 = VMSOF_M + {4, OperandInfo956}, // Inst #11242 = VMULHSU_VV + {4, OperandInfo957}, // Inst #11243 = VMULHSU_VX + {4, OperandInfo956}, // Inst #11244 = VMULHU_VV + {4, OperandInfo957}, // Inst #11245 = VMULHU_VX + {4, OperandInfo956}, // Inst #11246 = VMULH_VV + {4, OperandInfo957}, // Inst #11247 = VMULH_VX + {4, OperandInfo956}, // Inst #11248 = VMUL_VV + {4, OperandInfo957}, // Inst #11249 = VMUL_VX + {2, OperandInfo609}, // Inst #11250 = VMV1R_V + {2, OperandInfo609}, // Inst #11251 = VMV2R_V + {2, OperandInfo609}, // Inst #11252 = VMV4R_V + {2, OperandInfo609}, // Inst #11253 = VMV8R_V + {3, OperandInfo981}, // Inst #11254 = VMV_S_X + {2, OperandInfo982}, // Inst #11255 = VMV_V_I + {2, OperandInfo609}, // Inst #11256 = VMV_V_V + {2, OperandInfo652}, // Inst #11257 = VMV_V_X + {2, OperandInfo983}, // Inst #11258 = VMV_X_S + {3, OperandInfo980}, // Inst #11259 = VMXNOR_MM + {3, OperandInfo980}, // Inst #11260 = VMXOR_MM + {4, OperandInfo977}, // Inst #11261 = VNCLIPU_WI + {4, OperandInfo970}, // Inst #11262 = VNCLIPU_WV + {4, OperandInfo979}, // Inst #11263 = VNCLIPU_WX + {4, OperandInfo977}, // Inst #11264 = VNCLIP_WI + {4, OperandInfo970}, // Inst #11265 = VNCLIP_WV + {4, OperandInfo979}, // Inst #11266 = VNCLIP_WX + {4, OperandInfo956}, // Inst #11267 = VNMSAC_VV + {4, OperandInfo974}, // Inst #11268 = VNMSAC_VX + {4, OperandInfo956}, // Inst #11269 = VNMSUB_VV + {4, OperandInfo974}, // Inst #11270 = VNMSUB_VX + {4, OperandInfo977}, // Inst #11271 = VNSRA_WI + {4, OperandInfo970}, // Inst #11272 = VNSRA_WV + {4, OperandInfo979}, // Inst #11273 = VNSRA_WX + {4, OperandInfo977}, // Inst #11274 = VNSRL_WI + {4, OperandInfo970}, // Inst #11275 = VNSRL_WV + {4, OperandInfo979}, // Inst #11276 = VNSRL_WX + {4, OperandInfo605}, // Inst #11277 = VOR_VI + {4, OperandInfo956}, // Inst #11278 = VOR_VV + {4, OperandInfo957}, // Inst #11279 = VOR_VX + {4, OperandInfo956}, // Inst #11280 = VREDAND_VS + {4, OperandInfo956}, // Inst #11281 = VREDMAXU_VS + {4, OperandInfo956}, // Inst #11282 = VREDMAX_VS + {4, OperandInfo956}, // Inst #11283 = VREDMINU_VS + {4, OperandInfo956}, // Inst #11284 = VREDMIN_VS + {4, OperandInfo956}, // Inst #11285 = VREDOR_VS + {4, OperandInfo956}, // Inst #11286 = VREDSUM_VS + {4, OperandInfo956}, // Inst #11287 = VREDXOR_VS + {4, OperandInfo956}, // Inst #11288 = VREMU_VV + {4, OperandInfo957}, // Inst #11289 = VREMU_VX + {4, OperandInfo956}, // Inst #11290 = VREM_VV + {4, OperandInfo957}, // Inst #11291 = VREM_VX + {4, OperandInfo970}, // Inst #11292 = VRGATHEREI16_VV + {4, OperandInfo977}, // Inst #11293 = VRGATHER_VI + {4, OperandInfo970}, // Inst #11294 = VRGATHER_VV + {4, OperandInfo979}, // Inst #11295 = VRGATHER_VX + {4, OperandInfo605}, // Inst #11296 = VRSUB_VI + {4, OperandInfo957}, // Inst #11297 = VRSUB_VX + {2, OperandInfo652}, // Inst #11298 = VS1R_V + {2, OperandInfo653}, // Inst #11299 = VS2R_V + {2, OperandInfo654}, // Inst #11300 = VS4R_V + {2, OperandInfo655}, // Inst #11301 = VS8R_V + {4, OperandInfo605}, // Inst #11302 = VSADDU_VI + {4, OperandInfo956}, // Inst #11303 = VSADDU_VV + {4, OperandInfo957}, // Inst #11304 = VSADDU_VX + {4, OperandInfo605}, // Inst #11305 = VSADD_VI + {4, OperandInfo956}, // Inst #11306 = VSADD_VV + {4, OperandInfo957}, // Inst #11307 = VSADD_VX + {4, OperandInfo956}, // Inst #11308 = VSBC_VVM + {4, OperandInfo957}, // Inst #11309 = VSBC_VXM + {3, OperandInfo973}, // Inst #11310 = VSE16_V + {3, OperandInfo973}, // Inst #11311 = VSE32_V + {3, OperandInfo973}, // Inst #11312 = VSE64_V + {3, OperandInfo973}, // Inst #11313 = VSE8_V + {3, OperandInfo690}, // Inst #11314 = VSETIVLI + {3, OperandInfo890}, // Inst #11315 = VSETVL + {3, OperandInfo59}, // Inst #11316 = VSETVLI + {3, OperandInfo963}, // Inst #11317 = VSEXT_VF2 + {3, OperandInfo963}, // Inst #11318 = VSEXT_VF4 + {3, OperandInfo963}, // Inst #11319 = VSEXT_VF8 + {4, OperandInfo957}, // Inst #11320 = VSLIDE1DOWN_VX + {4, OperandInfo979}, // Inst #11321 = VSLIDE1UP_VX + {4, OperandInfo605}, // Inst #11322 = VSLIDEDOWN_VI + {4, OperandInfo957}, // Inst #11323 = VSLIDEDOWN_VX + {4, OperandInfo977}, // Inst #11324 = VSLIDEUP_VI + {4, OperandInfo979}, // Inst #11325 = VSLIDEUP_VX + {4, OperandInfo605}, // Inst #11326 = VSLL_VI + {4, OperandInfo956}, // Inst #11327 = VSLL_VV + {4, OperandInfo957}, // Inst #11328 = VSLL_VX + {4, OperandInfo956}, // Inst #11329 = VSMUL_VV + {4, OperandInfo957}, // Inst #11330 = VSMUL_VX + {2, OperandInfo652}, // Inst #11331 = VSM_V + {4, OperandInfo974}, // Inst #11332 = VSOXEI16_V + {4, OperandInfo974}, // Inst #11333 = VSOXEI32_V + {4, OperandInfo974}, // Inst #11334 = VSOXEI64_V + {4, OperandInfo974}, // Inst #11335 = VSOXEI8_V + {4, OperandInfo974}, // Inst #11336 = VSOXSEG2EI16_V + {4, OperandInfo974}, // Inst #11337 = VSOXSEG2EI32_V + {4, OperandInfo974}, // Inst #11338 = VSOXSEG2EI64_V + {4, OperandInfo974}, // Inst #11339 = VSOXSEG2EI8_V + {4, OperandInfo974}, // Inst #11340 = VSOXSEG3EI16_V + {4, OperandInfo974}, // Inst #11341 = VSOXSEG3EI32_V + {4, OperandInfo974}, // Inst #11342 = VSOXSEG3EI64_V + {4, OperandInfo974}, // Inst #11343 = VSOXSEG3EI8_V + {4, OperandInfo974}, // Inst #11344 = VSOXSEG4EI16_V + {4, OperandInfo974}, // Inst #11345 = VSOXSEG4EI32_V + {4, OperandInfo974}, // Inst #11346 = VSOXSEG4EI64_V + {4, OperandInfo974}, // Inst #11347 = VSOXSEG4EI8_V + {4, OperandInfo974}, // Inst #11348 = VSOXSEG5EI16_V + {4, OperandInfo974}, // Inst #11349 = VSOXSEG5EI32_V + {4, OperandInfo974}, // Inst #11350 = VSOXSEG5EI64_V + {4, OperandInfo974}, // Inst #11351 = VSOXSEG5EI8_V + {4, OperandInfo974}, // Inst #11352 = VSOXSEG6EI16_V + {4, OperandInfo974}, // Inst #11353 = VSOXSEG6EI32_V + {4, OperandInfo974}, // Inst #11354 = VSOXSEG6EI64_V + {4, OperandInfo974}, // Inst #11355 = VSOXSEG6EI8_V + {4, OperandInfo974}, // Inst #11356 = VSOXSEG7EI16_V + {4, OperandInfo974}, // Inst #11357 = VSOXSEG7EI32_V + {4, OperandInfo974}, // Inst #11358 = VSOXSEG7EI64_V + {4, OperandInfo974}, // Inst #11359 = VSOXSEG7EI8_V + {4, OperandInfo974}, // Inst #11360 = VSOXSEG8EI16_V + {4, OperandInfo974}, // Inst #11361 = VSOXSEG8EI32_V + {4, OperandInfo974}, // Inst #11362 = VSOXSEG8EI64_V + {4, OperandInfo974}, // Inst #11363 = VSOXSEG8EI8_V + {4, OperandInfo605}, // Inst #11364 = VSRA_VI + {4, OperandInfo956}, // Inst #11365 = VSRA_VV + {4, OperandInfo957}, // Inst #11366 = VSRA_VX + {4, OperandInfo605}, // Inst #11367 = VSRL_VI + {4, OperandInfo956}, // Inst #11368 = VSRL_VV + {4, OperandInfo957}, // Inst #11369 = VSRL_VX + {4, OperandInfo975}, // Inst #11370 = VSSE16_V + {4, OperandInfo975}, // Inst #11371 = VSSE32_V + {4, OperandInfo975}, // Inst #11372 = VSSE64_V + {4, OperandInfo975}, // Inst #11373 = VSSE8_V + {3, OperandInfo973}, // Inst #11374 = VSSEG2E16_V + {3, OperandInfo973}, // Inst #11375 = VSSEG2E32_V + {3, OperandInfo973}, // Inst #11376 = VSSEG2E64_V + {3, OperandInfo973}, // Inst #11377 = VSSEG2E8_V + {3, OperandInfo973}, // Inst #11378 = VSSEG3E16_V + {3, OperandInfo973}, // Inst #11379 = VSSEG3E32_V + {3, OperandInfo973}, // Inst #11380 = VSSEG3E64_V + {3, OperandInfo973}, // Inst #11381 = VSSEG3E8_V + {3, OperandInfo973}, // Inst #11382 = VSSEG4E16_V + {3, OperandInfo973}, // Inst #11383 = VSSEG4E32_V + {3, OperandInfo973}, // Inst #11384 = VSSEG4E64_V + {3, OperandInfo973}, // Inst #11385 = VSSEG4E8_V + {3, OperandInfo973}, // Inst #11386 = VSSEG5E16_V + {3, OperandInfo973}, // Inst #11387 = VSSEG5E32_V + {3, OperandInfo973}, // Inst #11388 = VSSEG5E64_V + {3, OperandInfo973}, // Inst #11389 = VSSEG5E8_V + {3, OperandInfo973}, // Inst #11390 = VSSEG6E16_V + {3, OperandInfo973}, // Inst #11391 = VSSEG6E32_V + {3, OperandInfo973}, // Inst #11392 = VSSEG6E64_V + {3, OperandInfo973}, // Inst #11393 = VSSEG6E8_V + {3, OperandInfo973}, // Inst #11394 = VSSEG7E16_V + {3, OperandInfo973}, // Inst #11395 = VSSEG7E32_V + {3, OperandInfo973}, // Inst #11396 = VSSEG7E64_V + {3, OperandInfo973}, // Inst #11397 = VSSEG7E8_V + {3, OperandInfo973}, // Inst #11398 = VSSEG8E16_V + {3, OperandInfo973}, // Inst #11399 = VSSEG8E32_V + {3, OperandInfo973}, // Inst #11400 = VSSEG8E64_V + {3, OperandInfo973}, // Inst #11401 = VSSEG8E8_V + {4, OperandInfo605}, // Inst #11402 = VSSRA_VI + {4, OperandInfo956}, // Inst #11403 = VSSRA_VV + {4, OperandInfo957}, // Inst #11404 = VSSRA_VX + {4, OperandInfo605}, // Inst #11405 = VSSRL_VI + {4, OperandInfo956}, // Inst #11406 = VSSRL_VV + {4, OperandInfo957}, // Inst #11407 = VSSRL_VX + {4, OperandInfo975}, // Inst #11408 = VSSSEG2E16_V + {4, OperandInfo975}, // Inst #11409 = VSSSEG2E32_V + {4, OperandInfo975}, // Inst #11410 = VSSSEG2E64_V + {4, OperandInfo975}, // Inst #11411 = VSSSEG2E8_V + {4, OperandInfo975}, // Inst #11412 = VSSSEG3E16_V + {4, OperandInfo975}, // Inst #11413 = VSSSEG3E32_V + {4, OperandInfo975}, // Inst #11414 = VSSSEG3E64_V + {4, OperandInfo975}, // Inst #11415 = VSSSEG3E8_V + {4, OperandInfo975}, // Inst #11416 = VSSSEG4E16_V + {4, OperandInfo975}, // Inst #11417 = VSSSEG4E32_V + {4, OperandInfo975}, // Inst #11418 = VSSSEG4E64_V + {4, OperandInfo975}, // Inst #11419 = VSSSEG4E8_V + {4, OperandInfo975}, // Inst #11420 = VSSSEG5E16_V + {4, OperandInfo975}, // Inst #11421 = VSSSEG5E32_V + {4, OperandInfo975}, // Inst #11422 = VSSSEG5E64_V + {4, OperandInfo975}, // Inst #11423 = VSSSEG5E8_V + {4, OperandInfo975}, // Inst #11424 = VSSSEG6E16_V + {4, OperandInfo975}, // Inst #11425 = VSSSEG6E32_V + {4, OperandInfo975}, // Inst #11426 = VSSSEG6E64_V + {4, OperandInfo975}, // Inst #11427 = VSSSEG6E8_V + {4, OperandInfo975}, // Inst #11428 = VSSSEG7E16_V + {4, OperandInfo975}, // Inst #11429 = VSSSEG7E32_V + {4, OperandInfo975}, // Inst #11430 = VSSSEG7E64_V + {4, OperandInfo975}, // Inst #11431 = VSSSEG7E8_V + {4, OperandInfo975}, // Inst #11432 = VSSSEG8E16_V + {4, OperandInfo975}, // Inst #11433 = VSSSEG8E32_V + {4, OperandInfo975}, // Inst #11434 = VSSSEG8E64_V + {4, OperandInfo975}, // Inst #11435 = VSSSEG8E8_V + {4, OperandInfo956}, // Inst #11436 = VSSUBU_VV + {4, OperandInfo957}, // Inst #11437 = VSSUBU_VX + {4, OperandInfo956}, // Inst #11438 = VSSUB_VV + {4, OperandInfo957}, // Inst #11439 = VSSUB_VX + {4, OperandInfo956}, // Inst #11440 = VSUB_VV + {4, OperandInfo957}, // Inst #11441 = VSUB_VX + {4, OperandInfo974}, // Inst #11442 = VSUXEI16_V + {4, OperandInfo974}, // Inst #11443 = VSUXEI32_V + {4, OperandInfo974}, // Inst #11444 = VSUXEI64_V + {4, OperandInfo974}, // Inst #11445 = VSUXEI8_V + {4, OperandInfo974}, // Inst #11446 = VSUXSEG2EI16_V + {4, OperandInfo974}, // Inst #11447 = VSUXSEG2EI32_V + {4, OperandInfo974}, // Inst #11448 = VSUXSEG2EI64_V + {4, OperandInfo974}, // Inst #11449 = VSUXSEG2EI8_V + {4, OperandInfo974}, // Inst #11450 = VSUXSEG3EI16_V + {4, OperandInfo974}, // Inst #11451 = VSUXSEG3EI32_V + {4, OperandInfo974}, // Inst #11452 = VSUXSEG3EI64_V + {4, OperandInfo974}, // Inst #11453 = VSUXSEG3EI8_V + {4, OperandInfo974}, // Inst #11454 = VSUXSEG4EI16_V + {4, OperandInfo974}, // Inst #11455 = VSUXSEG4EI32_V + {4, OperandInfo974}, // Inst #11456 = VSUXSEG4EI64_V + {4, OperandInfo974}, // Inst #11457 = VSUXSEG4EI8_V + {4, OperandInfo974}, // Inst #11458 = VSUXSEG5EI16_V + {4, OperandInfo974}, // Inst #11459 = VSUXSEG5EI32_V + {4, OperandInfo974}, // Inst #11460 = VSUXSEG5EI64_V + {4, OperandInfo974}, // Inst #11461 = VSUXSEG5EI8_V + {4, OperandInfo974}, // Inst #11462 = VSUXSEG6EI16_V + {4, OperandInfo974}, // Inst #11463 = VSUXSEG6EI32_V + {4, OperandInfo974}, // Inst #11464 = VSUXSEG6EI64_V + {4, OperandInfo974}, // Inst #11465 = VSUXSEG6EI8_V + {4, OperandInfo974}, // Inst #11466 = VSUXSEG7EI16_V + {4, OperandInfo974}, // Inst #11467 = VSUXSEG7EI32_V + {4, OperandInfo974}, // Inst #11468 = VSUXSEG7EI64_V + {4, OperandInfo974}, // Inst #11469 = VSUXSEG7EI8_V + {4, OperandInfo974}, // Inst #11470 = VSUXSEG8EI16_V + {4, OperandInfo974}, // Inst #11471 = VSUXSEG8EI32_V + {4, OperandInfo974}, // Inst #11472 = VSUXSEG8EI64_V + {4, OperandInfo974}, // Inst #11473 = VSUXSEG8EI8_V + {4, OperandInfo970}, // Inst #11474 = VWADDU_VV + {4, OperandInfo979}, // Inst #11475 = VWADDU_VX + {4, OperandInfo970}, // Inst #11476 = VWADDU_WV + {4, OperandInfo979}, // Inst #11477 = VWADDU_WX + {4, OperandInfo970}, // Inst #11478 = VWADD_VV + {4, OperandInfo979}, // Inst #11479 = VWADD_VX + {4, OperandInfo970}, // Inst #11480 = VWADD_WV + {4, OperandInfo979}, // Inst #11481 = VWADD_WX + {4, OperandInfo970}, // Inst #11482 = VWMACCSU_VV + {4, OperandInfo984}, // Inst #11483 = VWMACCSU_VX + {4, OperandInfo984}, // Inst #11484 = VWMACCUS_VX + {4, OperandInfo970}, // Inst #11485 = VWMACCU_VV + {4, OperandInfo984}, // Inst #11486 = VWMACCU_VX + {4, OperandInfo970}, // Inst #11487 = VWMACC_VV + {4, OperandInfo984}, // Inst #11488 = VWMACC_VX + {4, OperandInfo970}, // Inst #11489 = VWMULSU_VV + {4, OperandInfo979}, // Inst #11490 = VWMULSU_VX + {4, OperandInfo970}, // Inst #11491 = VWMULU_VV + {4, OperandInfo979}, // Inst #11492 = VWMULU_VX + {4, OperandInfo970}, // Inst #11493 = VWMUL_VV + {4, OperandInfo979}, // Inst #11494 = VWMUL_VX + {4, OperandInfo970}, // Inst #11495 = VWREDSUMU_VS + {4, OperandInfo970}, // Inst #11496 = VWREDSUM_VS + {4, OperandInfo970}, // Inst #11497 = VWSUBU_VV + {4, OperandInfo979}, // Inst #11498 = VWSUBU_VX + {4, OperandInfo970}, // Inst #11499 = VWSUBU_WV + {4, OperandInfo979}, // Inst #11500 = VWSUBU_WX + {4, OperandInfo970}, // Inst #11501 = VWSUB_VV + {4, OperandInfo979}, // Inst #11502 = VWSUB_VX + {4, OperandInfo970}, // Inst #11503 = VWSUB_WV + {4, OperandInfo979}, // Inst #11504 = VWSUB_WX + {4, OperandInfo605}, // Inst #11505 = VXOR_VI + {4, OperandInfo956}, // Inst #11506 = VXOR_VV + {4, OperandInfo957}, // Inst #11507 = VXOR_VX + {3, OperandInfo963}, // Inst #11508 = VZEXT_VF2 + {3, OperandInfo963}, // Inst #11509 = VZEXT_VF4 + {3, OperandInfo963}, // Inst #11510 = VZEXT_VF8 + {2, OperandInfo60}, // Inst #11511 = WFI + {3, OperandInfo890}, // Inst #11512 = XNOR + {3, OperandInfo890}, // Inst #11513 = XOR + {3, OperandInfo59}, // Inst #11514 = XORI + {3, OperandInfo890}, // Inst #11515 = XPERMB + {3, OperandInfo890}, // Inst #11516 = XPERMH + {3, OperandInfo890}, // Inst #11517 = XPERMN + {3, OperandInfo890}, // Inst #11518 = XPERMW + {2, OperandInfo60}, // Inst #11519 = ZEXTH_RV32 + {2, OperandInfo60}, // Inst #11520 = ZEXTH_RV64 +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +extern const char RISCVInstrNameData[] = { + /* 0 */ "G_FLOG10\0" + /* 9 */ "PseudoVSETVLIX0\0" + /* 25 */ "C_ADDI_HINT_X0\0" + /* 40 */ "PseudoVMSBF_M_B1\0" + /* 57 */ "PseudoVMSIF_M_B1\0" + /* 74 */ "PseudoVMSOF_M_B1\0" + /* 91 */ "PseudoVCPOP_M_B1\0" + /* 108 */ "PseudoVMCLR_M_B1\0" + /* 125 */ "PseudoVMSET_M_B1\0" + /* 142 */ "PseudoVFIRST_M_B1\0" + /* 160 */ "PseudoVLM_V_B1\0" + /* 175 */ "PseudoVSM_V_B1\0" + /* 190 */ "PseudoVAMOADDEI32_WD_M1_M1\0" + /* 217 */ "PseudoVAMOANDEI32_WD_M1_M1\0" + /* 244 */ "PseudoVAMOMINEI32_WD_M1_M1\0" + /* 271 */ "PseudoVAMOSWAPEI32_WD_M1_M1\0" + /* 299 */ "PseudoVAMOOREI32_WD_M1_M1\0" + /* 325 */ "PseudoVAMOXOREI32_WD_M1_M1\0" + /* 352 */ "PseudoVAMOMINUEI32_WD_M1_M1\0" + /* 380 */ "PseudoVAMOMAXUEI32_WD_M1_M1\0" + /* 408 */ "PseudoVAMOMAXEI32_WD_M1_M1\0" + /* 435 */ "PseudoVAMOADDEI64_WD_M1_M1\0" + /* 462 */ "PseudoVAMOANDEI64_WD_M1_M1\0" + /* 489 */ "PseudoVAMOMINEI64_WD_M1_M1\0" + /* 516 */ "PseudoVAMOSWAPEI64_WD_M1_M1\0" + /* 544 */ "PseudoVAMOOREI64_WD_M1_M1\0" + /* 570 */ "PseudoVAMOXOREI64_WD_M1_M1\0" + /* 597 */ "PseudoVAMOMINUEI64_WD_M1_M1\0" + /* 625 */ "PseudoVAMOMAXUEI64_WD_M1_M1\0" + /* 653 */ "PseudoVAMOMAXEI64_WD_M1_M1\0" + /* 680 */ "PseudoVRGATHEREI16_VV_M1_M1\0" + /* 708 */ "PseudoVLOXSEG2EI32_V_M1_M1\0" + /* 735 */ "PseudoVSOXSEG2EI32_V_M1_M1\0" + /* 762 */ "PseudoVLUXSEG2EI32_V_M1_M1\0" + /* 789 */ "PseudoVSUXSEG2EI32_V_M1_M1\0" + /* 816 */ "PseudoVLOXSEG3EI32_V_M1_M1\0" + /* 843 */ "PseudoVSOXSEG3EI32_V_M1_M1\0" + /* 870 */ "PseudoVLUXSEG3EI32_V_M1_M1\0" + /* 897 */ "PseudoVSUXSEG3EI32_V_M1_M1\0" + /* 924 */ "PseudoVLOXSEG4EI32_V_M1_M1\0" + /* 951 */ "PseudoVSOXSEG4EI32_V_M1_M1\0" + /* 978 */ "PseudoVLUXSEG4EI32_V_M1_M1\0" + /* 1005 */ "PseudoVSUXSEG4EI32_V_M1_M1\0" + /* 1032 */ "PseudoVLOXSEG5EI32_V_M1_M1\0" + /* 1059 */ "PseudoVSOXSEG5EI32_V_M1_M1\0" + /* 1086 */ "PseudoVLUXSEG5EI32_V_M1_M1\0" + /* 1113 */ "PseudoVSUXSEG5EI32_V_M1_M1\0" + /* 1140 */ "PseudoVLOXSEG6EI32_V_M1_M1\0" + /* 1167 */ "PseudoVSOXSEG6EI32_V_M1_M1\0" + /* 1194 */ "PseudoVLUXSEG6EI32_V_M1_M1\0" + /* 1221 */ "PseudoVSUXSEG6EI32_V_M1_M1\0" + /* 1248 */ "PseudoVLOXSEG7EI32_V_M1_M1\0" + /* 1275 */ "PseudoVSOXSEG7EI32_V_M1_M1\0" + /* 1302 */ "PseudoVLUXSEG7EI32_V_M1_M1\0" + /* 1329 */ "PseudoVSUXSEG7EI32_V_M1_M1\0" + /* 1356 */ "PseudoVLOXSEG8EI32_V_M1_M1\0" + /* 1383 */ "PseudoVSOXSEG8EI32_V_M1_M1\0" + /* 1410 */ "PseudoVLUXSEG8EI32_V_M1_M1\0" + /* 1437 */ "PseudoVSUXSEG8EI32_V_M1_M1\0" + /* 1464 */ "PseudoVLOXEI32_V_M1_M1\0" + /* 1487 */ "PseudoVSOXEI32_V_M1_M1\0" + /* 1510 */ "PseudoVLUXEI32_V_M1_M1\0" + /* 1533 */ "PseudoVSUXEI32_V_M1_M1\0" + /* 1556 */ "PseudoVLOXSEG2EI64_V_M1_M1\0" + /* 1583 */ "PseudoVSOXSEG2EI64_V_M1_M1\0" + /* 1610 */ "PseudoVLUXSEG2EI64_V_M1_M1\0" + /* 1637 */ "PseudoVSUXSEG2EI64_V_M1_M1\0" + /* 1664 */ "PseudoVLOXSEG3EI64_V_M1_M1\0" + /* 1691 */ "PseudoVSOXSEG3EI64_V_M1_M1\0" + /* 1718 */ "PseudoVLUXSEG3EI64_V_M1_M1\0" + /* 1745 */ "PseudoVSUXSEG3EI64_V_M1_M1\0" + /* 1772 */ "PseudoVLOXSEG4EI64_V_M1_M1\0" + /* 1799 */ "PseudoVSOXSEG4EI64_V_M1_M1\0" + /* 1826 */ "PseudoVLUXSEG4EI64_V_M1_M1\0" + /* 1853 */ "PseudoVSUXSEG4EI64_V_M1_M1\0" + /* 1880 */ "PseudoVLOXSEG5EI64_V_M1_M1\0" + /* 1907 */ "PseudoVSOXSEG5EI64_V_M1_M1\0" + /* 1934 */ "PseudoVLUXSEG5EI64_V_M1_M1\0" + /* 1961 */ "PseudoVSUXSEG5EI64_V_M1_M1\0" + /* 1988 */ "PseudoVLOXSEG6EI64_V_M1_M1\0" + /* 2015 */ "PseudoVSOXSEG6EI64_V_M1_M1\0" + /* 2042 */ "PseudoVLUXSEG6EI64_V_M1_M1\0" + /* 2069 */ "PseudoVSUXSEG6EI64_V_M1_M1\0" + /* 2096 */ "PseudoVLOXSEG7EI64_V_M1_M1\0" + /* 2123 */ "PseudoVSOXSEG7EI64_V_M1_M1\0" + /* 2150 */ "PseudoVLUXSEG7EI64_V_M1_M1\0" + /* 2177 */ "PseudoVSUXSEG7EI64_V_M1_M1\0" + /* 2204 */ "PseudoVLOXSEG8EI64_V_M1_M1\0" + /* 2231 */ "PseudoVSOXSEG8EI64_V_M1_M1\0" + /* 2258 */ "PseudoVLUXSEG8EI64_V_M1_M1\0" + /* 2285 */ "PseudoVSUXSEG8EI64_V_M1_M1\0" + /* 2312 */ "PseudoVLOXEI64_V_M1_M1\0" + /* 2335 */ "PseudoVSOXEI64_V_M1_M1\0" + /* 2358 */ "PseudoVLUXEI64_V_M1_M1\0" + /* 2381 */ "PseudoVSUXEI64_V_M1_M1\0" + /* 2404 */ "PseudoVLOXSEG2EI16_V_M1_M1\0" + /* 2431 */ "PseudoVSOXSEG2EI16_V_M1_M1\0" + /* 2458 */ "PseudoVLUXSEG2EI16_V_M1_M1\0" + /* 2485 */ "PseudoVSUXSEG2EI16_V_M1_M1\0" + /* 2512 */ "PseudoVLOXSEG3EI16_V_M1_M1\0" + /* 2539 */ "PseudoVSOXSEG3EI16_V_M1_M1\0" + /* 2566 */ "PseudoVLUXSEG3EI16_V_M1_M1\0" + /* 2593 */ "PseudoVSUXSEG3EI16_V_M1_M1\0" + /* 2620 */ "PseudoVLOXSEG4EI16_V_M1_M1\0" + /* 2647 */ "PseudoVSOXSEG4EI16_V_M1_M1\0" + /* 2674 */ "PseudoVLUXSEG4EI16_V_M1_M1\0" + /* 2701 */ "PseudoVSUXSEG4EI16_V_M1_M1\0" + /* 2728 */ "PseudoVLOXSEG5EI16_V_M1_M1\0" + /* 2755 */ "PseudoVSOXSEG5EI16_V_M1_M1\0" + /* 2782 */ "PseudoVLUXSEG5EI16_V_M1_M1\0" + /* 2809 */ "PseudoVSUXSEG5EI16_V_M1_M1\0" + /* 2836 */ "PseudoVLOXSEG6EI16_V_M1_M1\0" + /* 2863 */ "PseudoVSOXSEG6EI16_V_M1_M1\0" + /* 2890 */ "PseudoVLUXSEG6EI16_V_M1_M1\0" + /* 2917 */ "PseudoVSUXSEG6EI16_V_M1_M1\0" + /* 2944 */ "PseudoVLOXSEG7EI16_V_M1_M1\0" + /* 2971 */ "PseudoVSOXSEG7EI16_V_M1_M1\0" + /* 2998 */ "PseudoVLUXSEG7EI16_V_M1_M1\0" + /* 3025 */ "PseudoVSUXSEG7EI16_V_M1_M1\0" + /* 3052 */ "PseudoVLOXSEG8EI16_V_M1_M1\0" + /* 3079 */ "PseudoVSOXSEG8EI16_V_M1_M1\0" + /* 3106 */ "PseudoVLUXSEG8EI16_V_M1_M1\0" + /* 3133 */ "PseudoVSUXSEG8EI16_V_M1_M1\0" + /* 3160 */ "PseudoVLOXEI16_V_M1_M1\0" + /* 3183 */ "PseudoVSOXEI16_V_M1_M1\0" + /* 3206 */ "PseudoVLUXEI16_V_M1_M1\0" + /* 3229 */ "PseudoVSUXEI16_V_M1_M1\0" + /* 3252 */ "PseudoVLOXSEG2EI8_V_M1_M1\0" + /* 3278 */ "PseudoVSOXSEG2EI8_V_M1_M1\0" + /* 3304 */ "PseudoVLUXSEG2EI8_V_M1_M1\0" + /* 3330 */ "PseudoVSUXSEG2EI8_V_M1_M1\0" + /* 3356 */ "PseudoVLOXSEG3EI8_V_M1_M1\0" + /* 3382 */ "PseudoVSOXSEG3EI8_V_M1_M1\0" + /* 3408 */ "PseudoVLUXSEG3EI8_V_M1_M1\0" + /* 3434 */ "PseudoVSUXSEG3EI8_V_M1_M1\0" + /* 3460 */ "PseudoVLOXSEG4EI8_V_M1_M1\0" + /* 3486 */ "PseudoVSOXSEG4EI8_V_M1_M1\0" + /* 3512 */ "PseudoVLUXSEG4EI8_V_M1_M1\0" + /* 3538 */ "PseudoVSUXSEG4EI8_V_M1_M1\0" + /* 3564 */ "PseudoVLOXSEG5EI8_V_M1_M1\0" + /* 3590 */ "PseudoVSOXSEG5EI8_V_M1_M1\0" + /* 3616 */ "PseudoVLUXSEG5EI8_V_M1_M1\0" + /* 3642 */ "PseudoVSUXSEG5EI8_V_M1_M1\0" + /* 3668 */ "PseudoVLOXSEG6EI8_V_M1_M1\0" + /* 3694 */ "PseudoVSOXSEG6EI8_V_M1_M1\0" + /* 3720 */ "PseudoVLUXSEG6EI8_V_M1_M1\0" + /* 3746 */ "PseudoVSUXSEG6EI8_V_M1_M1\0" + /* 3772 */ "PseudoVLOXSEG7EI8_V_M1_M1\0" + /* 3798 */ "PseudoVSOXSEG7EI8_V_M1_M1\0" + /* 3824 */ "PseudoVLUXSEG7EI8_V_M1_M1\0" + /* 3850 */ "PseudoVSUXSEG7EI8_V_M1_M1\0" + /* 3876 */ "PseudoVLOXSEG8EI8_V_M1_M1\0" + /* 3902 */ "PseudoVSOXSEG8EI8_V_M1_M1\0" + /* 3928 */ "PseudoVLUXSEG8EI8_V_M1_M1\0" + /* 3954 */ "PseudoVSUXSEG8EI8_V_M1_M1\0" + /* 3980 */ "PseudoVLOXEI8_V_M1_M1\0" + /* 4002 */ "PseudoVSOXEI8_V_M1_M1\0" + /* 4024 */ "PseudoVLUXEI8_V_M1_M1\0" + /* 4046 */ "PseudoVSUXEI8_V_M1_M1\0" + /* 4068 */ "PseudoVFSUB_VF32_M1\0" + /* 4088 */ "PseudoVFMSUB_VF32_M1\0" + /* 4109 */ "PseudoVFNMSUB_VF32_M1\0" + /* 4131 */ "PseudoVFRSUB_VF32_M1\0" + /* 4152 */ "PseudoVFWSUB_VF32_M1\0" + /* 4173 */ "PseudoVFMSAC_VF32_M1\0" + /* 4194 */ "PseudoVFNMSAC_VF32_M1\0" + /* 4216 */ "PseudoVFWNMSAC_VF32_M1\0" + /* 4239 */ "PseudoVFWMSAC_VF32_M1\0" + /* 4261 */ "PseudoVFMACC_VF32_M1\0" + /* 4282 */ "PseudoVFNMACC_VF32_M1\0" + /* 4304 */ "PseudoVFWNMACC_VF32_M1\0" + /* 4327 */ "PseudoVFWMACC_VF32_M1\0" + /* 4349 */ "PseudoVFADD_VF32_M1\0" + /* 4369 */ "PseudoVFMADD_VF32_M1\0" + /* 4390 */ "PseudoVFNMADD_VF32_M1\0" + /* 4412 */ "PseudoVFWADD_VF32_M1\0" + /* 4433 */ "PseudoVMFGE_VF32_M1\0" + /* 4453 */ "PseudoVMFLE_VF32_M1\0" + /* 4473 */ "PseudoVMFNE_VF32_M1\0" + /* 4493 */ "PseudoVFSGNJ_VF32_M1\0" + /* 4514 */ "PseudoVFMUL_VF32_M1\0" + /* 4534 */ "PseudoVFWMUL_VF32_M1\0" + /* 4555 */ "PseudoVFMIN_VF32_M1\0" + /* 4575 */ "PseudoVFSGNJN_VF32_M1\0" + /* 4597 */ "PseudoVFSLIDE1DOWN_VF32_M1\0" + /* 4624 */ "PseudoVFSLIDE1UP_VF32_M1\0" + /* 4649 */ "PseudoVMFEQ_VF32_M1\0" + /* 4669 */ "PseudoVMFGT_VF32_M1\0" + /* 4689 */ "PseudoVMFLT_VF32_M1\0" + /* 4709 */ "PseudoVFDIV_VF32_M1\0" + /* 4729 */ "PseudoVFRDIV_VF32_M1\0" + /* 4750 */ "PseudoVFMAX_VF32_M1\0" + /* 4770 */ "PseudoVFSGNJX_VF32_M1\0" + /* 4792 */ "PseudoVFWSUB_WF32_M1\0" + /* 4813 */ "PseudoVFWADD_WF32_M1\0" + /* 4834 */ "PseudoVFMV_S_F32_M1\0" + /* 4854 */ "PseudoVFMV_V_F32_M1\0" + /* 4874 */ "PseudoVRELOAD2_M1\0" + /* 4892 */ "PseudoVAMOADDEI64_WD_MF2_M1\0" + /* 4920 */ "PseudoVAMOANDEI64_WD_MF2_M1\0" + /* 4948 */ "PseudoVAMOMINEI64_WD_MF2_M1\0" + /* 4976 */ "PseudoVAMOSWAPEI64_WD_MF2_M1\0" + /* 5005 */ "PseudoVAMOOREI64_WD_MF2_M1\0" + /* 5032 */ "PseudoVAMOXOREI64_WD_MF2_M1\0" + /* 5060 */ "PseudoVAMOMINUEI64_WD_MF2_M1\0" + /* 5089 */ "PseudoVAMOMAXUEI64_WD_MF2_M1\0" + /* 5118 */ "PseudoVAMOMAXEI64_WD_MF2_M1\0" + /* 5146 */ "PseudoVRGATHEREI16_VV_MF2_M1\0" + /* 5175 */ "PseudoVLOXSEG2EI32_V_MF2_M1\0" + /* 5203 */ "PseudoVSOXSEG2EI32_V_MF2_M1\0" + /* 5231 */ "PseudoVLUXSEG2EI32_V_MF2_M1\0" + /* 5259 */ "PseudoVSUXSEG2EI32_V_MF2_M1\0" + /* 5287 */ "PseudoVLOXSEG3EI32_V_MF2_M1\0" + /* 5315 */ "PseudoVSOXSEG3EI32_V_MF2_M1\0" + /* 5343 */ "PseudoVLUXSEG3EI32_V_MF2_M1\0" + /* 5371 */ "PseudoVSUXSEG3EI32_V_MF2_M1\0" + /* 5399 */ "PseudoVLOXSEG4EI32_V_MF2_M1\0" + /* 5427 */ "PseudoVSOXSEG4EI32_V_MF2_M1\0" + /* 5455 */ "PseudoVLUXSEG4EI32_V_MF2_M1\0" + /* 5483 */ "PseudoVSUXSEG4EI32_V_MF2_M1\0" + /* 5511 */ "PseudoVLOXSEG5EI32_V_MF2_M1\0" + /* 5539 */ "PseudoVSOXSEG5EI32_V_MF2_M1\0" + /* 5567 */ "PseudoVLUXSEG5EI32_V_MF2_M1\0" + /* 5595 */ "PseudoVSUXSEG5EI32_V_MF2_M1\0" + /* 5623 */ "PseudoVLOXSEG6EI32_V_MF2_M1\0" + /* 5651 */ "PseudoVSOXSEG6EI32_V_MF2_M1\0" + /* 5679 */ "PseudoVLUXSEG6EI32_V_MF2_M1\0" + /* 5707 */ "PseudoVSUXSEG6EI32_V_MF2_M1\0" + /* 5735 */ "PseudoVLOXSEG7EI32_V_MF2_M1\0" + /* 5763 */ "PseudoVSOXSEG7EI32_V_MF2_M1\0" + /* 5791 */ "PseudoVLUXSEG7EI32_V_MF2_M1\0" + /* 5819 */ "PseudoVSUXSEG7EI32_V_MF2_M1\0" + /* 5847 */ "PseudoVLOXSEG8EI32_V_MF2_M1\0" + /* 5875 */ "PseudoVSOXSEG8EI32_V_MF2_M1\0" + /* 5903 */ "PseudoVLUXSEG8EI32_V_MF2_M1\0" + /* 5931 */ "PseudoVSUXSEG8EI32_V_MF2_M1\0" + /* 5959 */ "PseudoVLOXEI32_V_MF2_M1\0" + /* 5983 */ "PseudoVSOXEI32_V_MF2_M1\0" + /* 6007 */ "PseudoVLUXEI32_V_MF2_M1\0" + /* 6031 */ "PseudoVSUXEI32_V_MF2_M1\0" + /* 6055 */ "PseudoVLOXSEG2EI16_V_MF2_M1\0" + /* 6083 */ "PseudoVSOXSEG2EI16_V_MF2_M1\0" + /* 6111 */ "PseudoVLUXSEG2EI16_V_MF2_M1\0" + /* 6139 */ "PseudoVSUXSEG2EI16_V_MF2_M1\0" + /* 6167 */ "PseudoVLOXSEG3EI16_V_MF2_M1\0" + /* 6195 */ "PseudoVSOXSEG3EI16_V_MF2_M1\0" + /* 6223 */ "PseudoVLUXSEG3EI16_V_MF2_M1\0" + /* 6251 */ "PseudoVSUXSEG3EI16_V_MF2_M1\0" + /* 6279 */ "PseudoVLOXSEG4EI16_V_MF2_M1\0" + /* 6307 */ "PseudoVSOXSEG4EI16_V_MF2_M1\0" + /* 6335 */ "PseudoVLUXSEG4EI16_V_MF2_M1\0" + /* 6363 */ "PseudoVSUXSEG4EI16_V_MF2_M1\0" + /* 6391 */ "PseudoVLOXSEG5EI16_V_MF2_M1\0" + /* 6419 */ "PseudoVSOXSEG5EI16_V_MF2_M1\0" + /* 6447 */ "PseudoVLUXSEG5EI16_V_MF2_M1\0" + /* 6475 */ "PseudoVSUXSEG5EI16_V_MF2_M1\0" + /* 6503 */ "PseudoVLOXSEG6EI16_V_MF2_M1\0" + /* 6531 */ "PseudoVSOXSEG6EI16_V_MF2_M1\0" + /* 6559 */ "PseudoVLUXSEG6EI16_V_MF2_M1\0" + /* 6587 */ "PseudoVSUXSEG6EI16_V_MF2_M1\0" + /* 6615 */ "PseudoVLOXSEG7EI16_V_MF2_M1\0" + /* 6643 */ "PseudoVSOXSEG7EI16_V_MF2_M1\0" + /* 6671 */ "PseudoVLUXSEG7EI16_V_MF2_M1\0" + /* 6699 */ "PseudoVSUXSEG7EI16_V_MF2_M1\0" + /* 6727 */ "PseudoVLOXSEG8EI16_V_MF2_M1\0" + /* 6755 */ "PseudoVSOXSEG8EI16_V_MF2_M1\0" + /* 6783 */ "PseudoVLUXSEG8EI16_V_MF2_M1\0" + /* 6811 */ "PseudoVSUXSEG8EI16_V_MF2_M1\0" + /* 6839 */ "PseudoVLOXEI16_V_MF2_M1\0" + /* 6863 */ "PseudoVSOXEI16_V_MF2_M1\0" + /* 6887 */ "PseudoVLUXEI16_V_MF2_M1\0" + /* 6911 */ "PseudoVSUXEI16_V_MF2_M1\0" + /* 6935 */ "PseudoVLOXSEG2EI8_V_MF2_M1\0" + /* 6962 */ "PseudoVSOXSEG2EI8_V_MF2_M1\0" + /* 6989 */ "PseudoVLUXSEG2EI8_V_MF2_M1\0" + /* 7016 */ "PseudoVSUXSEG2EI8_V_MF2_M1\0" + /* 7043 */ "PseudoVLOXSEG3EI8_V_MF2_M1\0" + /* 7070 */ "PseudoVSOXSEG3EI8_V_MF2_M1\0" + /* 7097 */ "PseudoVLUXSEG3EI8_V_MF2_M1\0" + /* 7124 */ "PseudoVSUXSEG3EI8_V_MF2_M1\0" + /* 7151 */ "PseudoVLOXSEG4EI8_V_MF2_M1\0" + /* 7178 */ "PseudoVSOXSEG4EI8_V_MF2_M1\0" + /* 7205 */ "PseudoVLUXSEG4EI8_V_MF2_M1\0" + /* 7232 */ "PseudoVSUXSEG4EI8_V_MF2_M1\0" + /* 7259 */ "PseudoVLOXSEG5EI8_V_MF2_M1\0" + /* 7286 */ "PseudoVSOXSEG5EI8_V_MF2_M1\0" + /* 7313 */ "PseudoVLUXSEG5EI8_V_MF2_M1\0" + /* 7340 */ "PseudoVSUXSEG5EI8_V_MF2_M1\0" + /* 7367 */ "PseudoVLOXSEG6EI8_V_MF2_M1\0" + /* 7394 */ "PseudoVSOXSEG6EI8_V_MF2_M1\0" + /* 7421 */ "PseudoVLUXSEG6EI8_V_MF2_M1\0" + /* 7448 */ "PseudoVSUXSEG6EI8_V_MF2_M1\0" + /* 7475 */ "PseudoVLOXSEG7EI8_V_MF2_M1\0" + /* 7502 */ "PseudoVSOXSEG7EI8_V_MF2_M1\0" + /* 7529 */ "PseudoVLUXSEG7EI8_V_MF2_M1\0" + /* 7556 */ "PseudoVSUXSEG7EI8_V_MF2_M1\0" + /* 7583 */ "PseudoVLOXSEG8EI8_V_MF2_M1\0" + /* 7610 */ "PseudoVSOXSEG8EI8_V_MF2_M1\0" + /* 7637 */ "PseudoVLUXSEG8EI8_V_MF2_M1\0" + /* 7664 */ "PseudoVSUXSEG8EI8_V_MF2_M1\0" + /* 7691 */ "PseudoVLOXEI8_V_MF2_M1\0" + /* 7714 */ "PseudoVSOXEI8_V_MF2_M1\0" + /* 7737 */ "PseudoVLUXEI8_V_MF2_M1\0" + /* 7760 */ "PseudoVSUXEI8_V_MF2_M1\0" + /* 7783 */ "PseudoVSEXT_VF2_M1\0" + /* 7802 */ "PseudoVZEXT_VF2_M1\0" + /* 7821 */ "PseudoVSPILL2_M1\0" + /* 7838 */ "PseudoVAMOADDEI32_WD_M2_M1\0" + /* 7865 */ "PseudoVAMOANDEI32_WD_M2_M1\0" + /* 7892 */ "PseudoVAMOMINEI32_WD_M2_M1\0" + /* 7919 */ "PseudoVAMOSWAPEI32_WD_M2_M1\0" + /* 7947 */ "PseudoVAMOOREI32_WD_M2_M1\0" + /* 7973 */ "PseudoVAMOXOREI32_WD_M2_M1\0" + /* 8000 */ "PseudoVAMOMINUEI32_WD_M2_M1\0" + /* 8028 */ "PseudoVAMOMAXUEI32_WD_M2_M1\0" + /* 8056 */ "PseudoVAMOMAXEI32_WD_M2_M1\0" + /* 8083 */ "PseudoVAMOADDEI16_WD_M2_M1\0" + /* 8110 */ "PseudoVAMOANDEI16_WD_M2_M1\0" + /* 8137 */ "PseudoVAMOMINEI16_WD_M2_M1\0" + /* 8164 */ "PseudoVAMOSWAPEI16_WD_M2_M1\0" + /* 8192 */ "PseudoVAMOOREI16_WD_M2_M1\0" + /* 8218 */ "PseudoVAMOXOREI16_WD_M2_M1\0" + /* 8245 */ "PseudoVAMOMINUEI16_WD_M2_M1\0" + /* 8273 */ "PseudoVAMOMAXUEI16_WD_M2_M1\0" + /* 8301 */ "PseudoVAMOMAXEI16_WD_M2_M1\0" + /* 8328 */ "PseudoVRGATHEREI16_VV_M2_M1\0" + /* 8356 */ "PseudoVLOXSEG2EI32_V_M2_M1\0" + /* 8383 */ "PseudoVSOXSEG2EI32_V_M2_M1\0" + /* 8410 */ "PseudoVLUXSEG2EI32_V_M2_M1\0" + /* 8437 */ "PseudoVSUXSEG2EI32_V_M2_M1\0" + /* 8464 */ "PseudoVLOXSEG3EI32_V_M2_M1\0" + /* 8491 */ "PseudoVSOXSEG3EI32_V_M2_M1\0" + /* 8518 */ "PseudoVLUXSEG3EI32_V_M2_M1\0" + /* 8545 */ "PseudoVSUXSEG3EI32_V_M2_M1\0" + /* 8572 */ "PseudoVLOXSEG4EI32_V_M2_M1\0" + /* 8599 */ "PseudoVSOXSEG4EI32_V_M2_M1\0" + /* 8626 */ "PseudoVLUXSEG4EI32_V_M2_M1\0" + /* 8653 */ "PseudoVSUXSEG4EI32_V_M2_M1\0" + /* 8680 */ "PseudoVLOXSEG5EI32_V_M2_M1\0" + /* 8707 */ "PseudoVSOXSEG5EI32_V_M2_M1\0" + /* 8734 */ "PseudoVLUXSEG5EI32_V_M2_M1\0" + /* 8761 */ "PseudoVSUXSEG5EI32_V_M2_M1\0" + /* 8788 */ "PseudoVLOXSEG6EI32_V_M2_M1\0" + /* 8815 */ "PseudoVSOXSEG6EI32_V_M2_M1\0" + /* 8842 */ "PseudoVLUXSEG6EI32_V_M2_M1\0" + /* 8869 */ "PseudoVSUXSEG6EI32_V_M2_M1\0" + /* 8896 */ "PseudoVLOXSEG7EI32_V_M2_M1\0" + /* 8923 */ "PseudoVSOXSEG7EI32_V_M2_M1\0" + /* 8950 */ "PseudoVLUXSEG7EI32_V_M2_M1\0" + /* 8977 */ "PseudoVSUXSEG7EI32_V_M2_M1\0" + /* 9004 */ "PseudoVLOXSEG8EI32_V_M2_M1\0" + /* 9031 */ "PseudoVSOXSEG8EI32_V_M2_M1\0" + /* 9058 */ "PseudoVLUXSEG8EI32_V_M2_M1\0" + /* 9085 */ "PseudoVSUXSEG8EI32_V_M2_M1\0" + /* 9112 */ "PseudoVLOXEI32_V_M2_M1\0" + /* 9135 */ "PseudoVSOXEI32_V_M2_M1\0" + /* 9158 */ "PseudoVLUXEI32_V_M2_M1\0" + /* 9181 */ "PseudoVSUXEI32_V_M2_M1\0" + /* 9204 */ "PseudoVLOXSEG2EI64_V_M2_M1\0" + /* 9231 */ "PseudoVSOXSEG2EI64_V_M2_M1\0" + /* 9258 */ "PseudoVLUXSEG2EI64_V_M2_M1\0" + /* 9285 */ "PseudoVSUXSEG2EI64_V_M2_M1\0" + /* 9312 */ "PseudoVLOXSEG3EI64_V_M2_M1\0" + /* 9339 */ "PseudoVSOXSEG3EI64_V_M2_M1\0" + /* 9366 */ "PseudoVLUXSEG3EI64_V_M2_M1\0" + /* 9393 */ "PseudoVSUXSEG3EI64_V_M2_M1\0" + /* 9420 */ "PseudoVLOXSEG4EI64_V_M2_M1\0" + /* 9447 */ "PseudoVSOXSEG4EI64_V_M2_M1\0" + /* 9474 */ "PseudoVLUXSEG4EI64_V_M2_M1\0" + /* 9501 */ "PseudoVSUXSEG4EI64_V_M2_M1\0" + /* 9528 */ "PseudoVLOXSEG5EI64_V_M2_M1\0" + /* 9555 */ "PseudoVSOXSEG5EI64_V_M2_M1\0" + /* 9582 */ "PseudoVLUXSEG5EI64_V_M2_M1\0" + /* 9609 */ "PseudoVSUXSEG5EI64_V_M2_M1\0" + /* 9636 */ "PseudoVLOXSEG6EI64_V_M2_M1\0" + /* 9663 */ "PseudoVSOXSEG6EI64_V_M2_M1\0" + /* 9690 */ "PseudoVLUXSEG6EI64_V_M2_M1\0" + /* 9717 */ "PseudoVSUXSEG6EI64_V_M2_M1\0" + /* 9744 */ "PseudoVLOXSEG7EI64_V_M2_M1\0" + /* 9771 */ "PseudoVSOXSEG7EI64_V_M2_M1\0" + /* 9798 */ "PseudoVLUXSEG7EI64_V_M2_M1\0" + /* 9825 */ "PseudoVSUXSEG7EI64_V_M2_M1\0" + /* 9852 */ "PseudoVLOXSEG8EI64_V_M2_M1\0" + /* 9879 */ "PseudoVSOXSEG8EI64_V_M2_M1\0" + /* 9906 */ "PseudoVLUXSEG8EI64_V_M2_M1\0" + /* 9933 */ "PseudoVSUXSEG8EI64_V_M2_M1\0" + /* 9960 */ "PseudoVLOXEI64_V_M2_M1\0" + /* 9983 */ "PseudoVSOXEI64_V_M2_M1\0" + /* 10006 */ "PseudoVLUXEI64_V_M2_M1\0" + /* 10029 */ "PseudoVSUXEI64_V_M2_M1\0" + /* 10052 */ "PseudoVLOXSEG2EI16_V_M2_M1\0" + /* 10079 */ "PseudoVSOXSEG2EI16_V_M2_M1\0" + /* 10106 */ "PseudoVLUXSEG2EI16_V_M2_M1\0" + /* 10133 */ "PseudoVSUXSEG2EI16_V_M2_M1\0" + /* 10160 */ "PseudoVLOXSEG3EI16_V_M2_M1\0" + /* 10187 */ "PseudoVSOXSEG3EI16_V_M2_M1\0" + /* 10214 */ "PseudoVLUXSEG3EI16_V_M2_M1\0" + /* 10241 */ "PseudoVSUXSEG3EI16_V_M2_M1\0" + /* 10268 */ "PseudoVLOXSEG4EI16_V_M2_M1\0" + /* 10295 */ "PseudoVSOXSEG4EI16_V_M2_M1\0" + /* 10322 */ "PseudoVLUXSEG4EI16_V_M2_M1\0" + /* 10349 */ "PseudoVSUXSEG4EI16_V_M2_M1\0" + /* 10376 */ "PseudoVLOXSEG5EI16_V_M2_M1\0" + /* 10403 */ "PseudoVSOXSEG5EI16_V_M2_M1\0" + /* 10430 */ "PseudoVLUXSEG5EI16_V_M2_M1\0" + /* 10457 */ "PseudoVSUXSEG5EI16_V_M2_M1\0" + /* 10484 */ "PseudoVLOXSEG6EI16_V_M2_M1\0" + /* 10511 */ "PseudoVSOXSEG6EI16_V_M2_M1\0" + /* 10538 */ "PseudoVLUXSEG6EI16_V_M2_M1\0" + /* 10565 */ "PseudoVSUXSEG6EI16_V_M2_M1\0" + /* 10592 */ "PseudoVLOXSEG7EI16_V_M2_M1\0" + /* 10619 */ "PseudoVSOXSEG7EI16_V_M2_M1\0" + /* 10646 */ "PseudoVLUXSEG7EI16_V_M2_M1\0" + /* 10673 */ "PseudoVSUXSEG7EI16_V_M2_M1\0" + /* 10700 */ "PseudoVLOXSEG8EI16_V_M2_M1\0" + /* 10727 */ "PseudoVSOXSEG8EI16_V_M2_M1\0" + /* 10754 */ "PseudoVLUXSEG8EI16_V_M2_M1\0" + /* 10781 */ "PseudoVSUXSEG8EI16_V_M2_M1\0" + /* 10808 */ "PseudoVLOXEI16_V_M2_M1\0" + /* 10831 */ "PseudoVSOXEI16_V_M2_M1\0" + /* 10854 */ "PseudoVLUXEI16_V_M2_M1\0" + /* 10877 */ "PseudoVSUXEI16_V_M2_M1\0" + /* 10900 */ "PseudoVRELOAD3_M1\0" + /* 10918 */ "PseudoVSPILL3_M1\0" + /* 10935 */ "PseudoVFSUB_VF64_M1\0" + /* 10955 */ "PseudoVFMSUB_VF64_M1\0" + /* 10976 */ "PseudoVFNMSUB_VF64_M1\0" + /* 10998 */ "PseudoVFRSUB_VF64_M1\0" + /* 11019 */ "PseudoVFMSAC_VF64_M1\0" + /* 11040 */ "PseudoVFNMSAC_VF64_M1\0" + /* 11062 */ "PseudoVFMACC_VF64_M1\0" + /* 11083 */ "PseudoVFNMACC_VF64_M1\0" + /* 11105 */ "PseudoVFADD_VF64_M1\0" + /* 11125 */ "PseudoVFMADD_VF64_M1\0" + /* 11146 */ "PseudoVFNMADD_VF64_M1\0" + /* 11168 */ "PseudoVMFGE_VF64_M1\0" + /* 11188 */ "PseudoVMFLE_VF64_M1\0" + /* 11208 */ "PseudoVMFNE_VF64_M1\0" + /* 11228 */ "PseudoVFSGNJ_VF64_M1\0" + /* 11249 */ "PseudoVFMUL_VF64_M1\0" + /* 11269 */ "PseudoVFMIN_VF64_M1\0" + /* 11289 */ "PseudoVFSGNJN_VF64_M1\0" + /* 11311 */ "PseudoVFSLIDE1DOWN_VF64_M1\0" + /* 11338 */ "PseudoVFSLIDE1UP_VF64_M1\0" + /* 11363 */ "PseudoVMFEQ_VF64_M1\0" + /* 11383 */ "PseudoVMFGT_VF64_M1\0" + /* 11403 */ "PseudoVMFLT_VF64_M1\0" + /* 11423 */ "PseudoVFDIV_VF64_M1\0" + /* 11443 */ "PseudoVFRDIV_VF64_M1\0" + /* 11464 */ "PseudoVFMAX_VF64_M1\0" + /* 11484 */ "PseudoVFSGNJX_VF64_M1\0" + /* 11506 */ "PseudoVFMV_S_F64_M1\0" + /* 11526 */ "PseudoVFMV_V_F64_M1\0" + /* 11546 */ "PseudoVRELOAD4_M1\0" + /* 11564 */ "PseudoVLOXSEG2EI16_V_MF4_M1\0" + /* 11592 */ "PseudoVSOXSEG2EI16_V_MF4_M1\0" + /* 11620 */ "PseudoVLUXSEG2EI16_V_MF4_M1\0" + /* 11648 */ "PseudoVSUXSEG2EI16_V_MF4_M1\0" + /* 11676 */ "PseudoVLOXSEG3EI16_V_MF4_M1\0" + /* 11704 */ "PseudoVSOXSEG3EI16_V_MF4_M1\0" + /* 11732 */ "PseudoVLUXSEG3EI16_V_MF4_M1\0" + /* 11760 */ "PseudoVSUXSEG3EI16_V_MF4_M1\0" + /* 11788 */ "PseudoVLOXSEG4EI16_V_MF4_M1\0" + /* 11816 */ "PseudoVSOXSEG4EI16_V_MF4_M1\0" + /* 11844 */ "PseudoVLUXSEG4EI16_V_MF4_M1\0" + /* 11872 */ "PseudoVSUXSEG4EI16_V_MF4_M1\0" + /* 11900 */ "PseudoVLOXSEG5EI16_V_MF4_M1\0" + /* 11928 */ "PseudoVSOXSEG5EI16_V_MF4_M1\0" + /* 11956 */ "PseudoVLUXSEG5EI16_V_MF4_M1\0" + /* 11984 */ "PseudoVSUXSEG5EI16_V_MF4_M1\0" + /* 12012 */ "PseudoVLOXSEG6EI16_V_MF4_M1\0" + /* 12040 */ "PseudoVSOXSEG6EI16_V_MF4_M1\0" + /* 12068 */ "PseudoVLUXSEG6EI16_V_MF4_M1\0" + /* 12096 */ "PseudoVSUXSEG6EI16_V_MF4_M1\0" + /* 12124 */ "PseudoVLOXSEG7EI16_V_MF4_M1\0" + /* 12152 */ "PseudoVSOXSEG7EI16_V_MF4_M1\0" + /* 12180 */ "PseudoVLUXSEG7EI16_V_MF4_M1\0" + /* 12208 */ "PseudoVSUXSEG7EI16_V_MF4_M1\0" + /* 12236 */ "PseudoVLOXSEG8EI16_V_MF4_M1\0" + /* 12264 */ "PseudoVSOXSEG8EI16_V_MF4_M1\0" + /* 12292 */ "PseudoVLUXSEG8EI16_V_MF4_M1\0" + /* 12320 */ "PseudoVSUXSEG8EI16_V_MF4_M1\0" + /* 12348 */ "PseudoVLOXEI16_V_MF4_M1\0" + /* 12372 */ "PseudoVSOXEI16_V_MF4_M1\0" + /* 12396 */ "PseudoVLUXEI16_V_MF4_M1\0" + /* 12420 */ "PseudoVSUXEI16_V_MF4_M1\0" + /* 12444 */ "PseudoVLOXSEG2EI8_V_MF4_M1\0" + /* 12471 */ "PseudoVSOXSEG2EI8_V_MF4_M1\0" + /* 12498 */ "PseudoVLUXSEG2EI8_V_MF4_M1\0" + /* 12525 */ "PseudoVSUXSEG2EI8_V_MF4_M1\0" + /* 12552 */ "PseudoVLOXSEG3EI8_V_MF4_M1\0" + /* 12579 */ "PseudoVSOXSEG3EI8_V_MF4_M1\0" + /* 12606 */ "PseudoVLUXSEG3EI8_V_MF4_M1\0" + /* 12633 */ "PseudoVSUXSEG3EI8_V_MF4_M1\0" + /* 12660 */ "PseudoVLOXSEG4EI8_V_MF4_M1\0" + /* 12687 */ "PseudoVSOXSEG4EI8_V_MF4_M1\0" + /* 12714 */ "PseudoVLUXSEG4EI8_V_MF4_M1\0" + /* 12741 */ "PseudoVSUXSEG4EI8_V_MF4_M1\0" + /* 12768 */ "PseudoVLOXSEG5EI8_V_MF4_M1\0" + /* 12795 */ "PseudoVSOXSEG5EI8_V_MF4_M1\0" + /* 12822 */ "PseudoVLUXSEG5EI8_V_MF4_M1\0" + /* 12849 */ "PseudoVSUXSEG5EI8_V_MF4_M1\0" + /* 12876 */ "PseudoVLOXSEG6EI8_V_MF4_M1\0" + /* 12903 */ "PseudoVSOXSEG6EI8_V_MF4_M1\0" + /* 12930 */ "PseudoVLUXSEG6EI8_V_MF4_M1\0" + /* 12957 */ "PseudoVSUXSEG6EI8_V_MF4_M1\0" + /* 12984 */ "PseudoVLOXSEG7EI8_V_MF4_M1\0" + /* 13011 */ "PseudoVSOXSEG7EI8_V_MF4_M1\0" + /* 13038 */ "PseudoVLUXSEG7EI8_V_MF4_M1\0" + /* 13065 */ "PseudoVSUXSEG7EI8_V_MF4_M1\0" + /* 13092 */ "PseudoVLOXSEG8EI8_V_MF4_M1\0" + /* 13119 */ "PseudoVSOXSEG8EI8_V_MF4_M1\0" + /* 13146 */ "PseudoVLUXSEG8EI8_V_MF4_M1\0" + /* 13173 */ "PseudoVSUXSEG8EI8_V_MF4_M1\0" + /* 13200 */ "PseudoVLOXEI8_V_MF4_M1\0" + /* 13223 */ "PseudoVSOXEI8_V_MF4_M1\0" + /* 13246 */ "PseudoVLUXEI8_V_MF4_M1\0" + /* 13269 */ "PseudoVSUXEI8_V_MF4_M1\0" + /* 13292 */ "PseudoVSEXT_VF4_M1\0" + /* 13311 */ "PseudoVZEXT_VF4_M1\0" + /* 13330 */ "PseudoVSPILL4_M1\0" + /* 13347 */ "PseudoVAMOADDEI16_WD_M4_M1\0" + /* 13374 */ "PseudoVAMOANDEI16_WD_M4_M1\0" + /* 13401 */ "PseudoVAMOMINEI16_WD_M4_M1\0" + /* 13428 */ "PseudoVAMOSWAPEI16_WD_M4_M1\0" + /* 13456 */ "PseudoVAMOOREI16_WD_M4_M1\0" + /* 13482 */ "PseudoVAMOXOREI16_WD_M4_M1\0" + /* 13509 */ "PseudoVAMOMINUEI16_WD_M4_M1\0" + /* 13537 */ "PseudoVAMOMAXUEI16_WD_M4_M1\0" + /* 13565 */ "PseudoVAMOMAXEI16_WD_M4_M1\0" + /* 13592 */ "PseudoVAMOADDEI8_WD_M4_M1\0" + /* 13618 */ "PseudoVAMOANDEI8_WD_M4_M1\0" + /* 13644 */ "PseudoVAMOMINEI8_WD_M4_M1\0" + /* 13670 */ "PseudoVAMOSWAPEI8_WD_M4_M1\0" + /* 13697 */ "PseudoVAMOOREI8_WD_M4_M1\0" + /* 13722 */ "PseudoVAMOXOREI8_WD_M4_M1\0" + /* 13748 */ "PseudoVAMOMINUEI8_WD_M4_M1\0" + /* 13775 */ "PseudoVAMOMAXUEI8_WD_M4_M1\0" + /* 13802 */ "PseudoVAMOMAXEI8_WD_M4_M1\0" + /* 13828 */ "PseudoVRGATHEREI16_VV_M4_M1\0" + /* 13856 */ "PseudoVLOXSEG2EI32_V_M4_M1\0" + /* 13883 */ "PseudoVSOXSEG2EI32_V_M4_M1\0" + /* 13910 */ "PseudoVLUXSEG2EI32_V_M4_M1\0" + /* 13937 */ "PseudoVSUXSEG2EI32_V_M4_M1\0" + /* 13964 */ "PseudoVLOXSEG3EI32_V_M4_M1\0" + /* 13991 */ "PseudoVSOXSEG3EI32_V_M4_M1\0" + /* 14018 */ "PseudoVLUXSEG3EI32_V_M4_M1\0" + /* 14045 */ "PseudoVSUXSEG3EI32_V_M4_M1\0" + /* 14072 */ "PseudoVLOXSEG4EI32_V_M4_M1\0" + /* 14099 */ "PseudoVSOXSEG4EI32_V_M4_M1\0" + /* 14126 */ "PseudoVLUXSEG4EI32_V_M4_M1\0" + /* 14153 */ "PseudoVSUXSEG4EI32_V_M4_M1\0" + /* 14180 */ "PseudoVLOXSEG5EI32_V_M4_M1\0" + /* 14207 */ "PseudoVSOXSEG5EI32_V_M4_M1\0" + /* 14234 */ "PseudoVLUXSEG5EI32_V_M4_M1\0" + /* 14261 */ "PseudoVSUXSEG5EI32_V_M4_M1\0" + /* 14288 */ "PseudoVLOXSEG6EI32_V_M4_M1\0" + /* 14315 */ "PseudoVSOXSEG6EI32_V_M4_M1\0" + /* 14342 */ "PseudoVLUXSEG6EI32_V_M4_M1\0" + /* 14369 */ "PseudoVSUXSEG6EI32_V_M4_M1\0" + /* 14396 */ "PseudoVLOXSEG7EI32_V_M4_M1\0" + /* 14423 */ "PseudoVSOXSEG7EI32_V_M4_M1\0" + /* 14450 */ "PseudoVLUXSEG7EI32_V_M4_M1\0" + /* 14477 */ "PseudoVSUXSEG7EI32_V_M4_M1\0" + /* 14504 */ "PseudoVLOXSEG8EI32_V_M4_M1\0" + /* 14531 */ "PseudoVSOXSEG8EI32_V_M4_M1\0" + /* 14558 */ "PseudoVLUXSEG8EI32_V_M4_M1\0" + /* 14585 */ "PseudoVSUXSEG8EI32_V_M4_M1\0" + /* 14612 */ "PseudoVLOXEI32_V_M4_M1\0" + /* 14635 */ "PseudoVSOXEI32_V_M4_M1\0" + /* 14658 */ "PseudoVLUXEI32_V_M4_M1\0" + /* 14681 */ "PseudoVSUXEI32_V_M4_M1\0" + /* 14704 */ "PseudoVLOXSEG2EI64_V_M4_M1\0" + /* 14731 */ "PseudoVSOXSEG2EI64_V_M4_M1\0" + /* 14758 */ "PseudoVLUXSEG2EI64_V_M4_M1\0" + /* 14785 */ "PseudoVSUXSEG2EI64_V_M4_M1\0" + /* 14812 */ "PseudoVLOXSEG3EI64_V_M4_M1\0" + /* 14839 */ "PseudoVSOXSEG3EI64_V_M4_M1\0" + /* 14866 */ "PseudoVLUXSEG3EI64_V_M4_M1\0" + /* 14893 */ "PseudoVSUXSEG3EI64_V_M4_M1\0" + /* 14920 */ "PseudoVLOXSEG4EI64_V_M4_M1\0" + /* 14947 */ "PseudoVSOXSEG4EI64_V_M4_M1\0" + /* 14974 */ "PseudoVLUXSEG4EI64_V_M4_M1\0" + /* 15001 */ "PseudoVSUXSEG4EI64_V_M4_M1\0" + /* 15028 */ "PseudoVLOXSEG5EI64_V_M4_M1\0" + /* 15055 */ "PseudoVSOXSEG5EI64_V_M4_M1\0" + /* 15082 */ "PseudoVLUXSEG5EI64_V_M4_M1\0" + /* 15109 */ "PseudoVSUXSEG5EI64_V_M4_M1\0" + /* 15136 */ "PseudoVLOXSEG6EI64_V_M4_M1\0" + /* 15163 */ "PseudoVSOXSEG6EI64_V_M4_M1\0" + /* 15190 */ "PseudoVLUXSEG6EI64_V_M4_M1\0" + /* 15217 */ "PseudoVSUXSEG6EI64_V_M4_M1\0" + /* 15244 */ "PseudoVLOXSEG7EI64_V_M4_M1\0" + /* 15271 */ "PseudoVSOXSEG7EI64_V_M4_M1\0" + /* 15298 */ "PseudoVLUXSEG7EI64_V_M4_M1\0" + /* 15325 */ "PseudoVSUXSEG7EI64_V_M4_M1\0" + /* 15352 */ "PseudoVLOXSEG8EI64_V_M4_M1\0" + /* 15379 */ "PseudoVSOXSEG8EI64_V_M4_M1\0" + /* 15406 */ "PseudoVLUXSEG8EI64_V_M4_M1\0" + /* 15433 */ "PseudoVSUXSEG8EI64_V_M4_M1\0" + /* 15460 */ "PseudoVLOXEI64_V_M4_M1\0" + /* 15483 */ "PseudoVSOXEI64_V_M4_M1\0" + /* 15506 */ "PseudoVLUXEI64_V_M4_M1\0" + /* 15529 */ "PseudoVSUXEI64_V_M4_M1\0" + /* 15552 */ "PseudoVRELOAD5_M1\0" + /* 15570 */ "PseudoVSPILL5_M1\0" + /* 15587 */ "PseudoVFSUB_VF16_M1\0" + /* 15607 */ "PseudoVFMSUB_VF16_M1\0" + /* 15628 */ "PseudoVFNMSUB_VF16_M1\0" + /* 15650 */ "PseudoVFRSUB_VF16_M1\0" + /* 15671 */ "PseudoVFWSUB_VF16_M1\0" + /* 15692 */ "PseudoVFMSAC_VF16_M1\0" + /* 15713 */ "PseudoVFNMSAC_VF16_M1\0" + /* 15735 */ "PseudoVFWNMSAC_VF16_M1\0" + /* 15758 */ "PseudoVFWMSAC_VF16_M1\0" + /* 15780 */ "PseudoVFMACC_VF16_M1\0" + /* 15801 */ "PseudoVFNMACC_VF16_M1\0" + /* 15823 */ "PseudoVFWNMACC_VF16_M1\0" + /* 15846 */ "PseudoVFWMACC_VF16_M1\0" + /* 15868 */ "PseudoVFADD_VF16_M1\0" + /* 15888 */ "PseudoVFMADD_VF16_M1\0" + /* 15909 */ "PseudoVFNMADD_VF16_M1\0" + /* 15931 */ "PseudoVFWADD_VF16_M1\0" + /* 15952 */ "PseudoVMFGE_VF16_M1\0" + /* 15972 */ "PseudoVMFLE_VF16_M1\0" + /* 15992 */ "PseudoVMFNE_VF16_M1\0" + /* 16012 */ "PseudoVFSGNJ_VF16_M1\0" + /* 16033 */ "PseudoVFMUL_VF16_M1\0" + /* 16053 */ "PseudoVFWMUL_VF16_M1\0" + /* 16074 */ "PseudoVFMIN_VF16_M1\0" + /* 16094 */ "PseudoVFSGNJN_VF16_M1\0" + /* 16116 */ "PseudoVFSLIDE1DOWN_VF16_M1\0" + /* 16143 */ "PseudoVFSLIDE1UP_VF16_M1\0" + /* 16168 */ "PseudoVMFEQ_VF16_M1\0" + /* 16188 */ "PseudoVMFGT_VF16_M1\0" + /* 16208 */ "PseudoVMFLT_VF16_M1\0" + /* 16228 */ "PseudoVFDIV_VF16_M1\0" + /* 16248 */ "PseudoVFRDIV_VF16_M1\0" + /* 16269 */ "PseudoVFMAX_VF16_M1\0" + /* 16289 */ "PseudoVFSGNJX_VF16_M1\0" + /* 16311 */ "PseudoVFWSUB_WF16_M1\0" + /* 16332 */ "PseudoVFWADD_WF16_M1\0" + /* 16353 */ "PseudoVFMV_S_F16_M1\0" + /* 16373 */ "PseudoVFMV_V_F16_M1\0" + /* 16393 */ "PseudoVRELOAD6_M1\0" + /* 16411 */ "PseudoVSPILL6_M1\0" + /* 16428 */ "PseudoVRELOAD7_M1\0" + /* 16446 */ "PseudoVSPILL7_M1\0" + /* 16463 */ "PseudoVRELOAD8_M1\0" + /* 16481 */ "PseudoVLOXSEG2EI8_V_MF8_M1\0" + /* 16508 */ "PseudoVSOXSEG2EI8_V_MF8_M1\0" + /* 16535 */ "PseudoVLUXSEG2EI8_V_MF8_M1\0" + /* 16562 */ "PseudoVSUXSEG2EI8_V_MF8_M1\0" + /* 16589 */ "PseudoVLOXSEG3EI8_V_MF8_M1\0" + /* 16616 */ "PseudoVSOXSEG3EI8_V_MF8_M1\0" + /* 16643 */ "PseudoVLUXSEG3EI8_V_MF8_M1\0" + /* 16670 */ "PseudoVSUXSEG3EI8_V_MF8_M1\0" + /* 16697 */ "PseudoVLOXSEG4EI8_V_MF8_M1\0" + /* 16724 */ "PseudoVSOXSEG4EI8_V_MF8_M1\0" + /* 16751 */ "PseudoVLUXSEG4EI8_V_MF8_M1\0" + /* 16778 */ "PseudoVSUXSEG4EI8_V_MF8_M1\0" + /* 16805 */ "PseudoVLOXSEG5EI8_V_MF8_M1\0" + /* 16832 */ "PseudoVSOXSEG5EI8_V_MF8_M1\0" + /* 16859 */ "PseudoVLUXSEG5EI8_V_MF8_M1\0" + /* 16886 */ "PseudoVSUXSEG5EI8_V_MF8_M1\0" + /* 16913 */ "PseudoVLOXSEG6EI8_V_MF8_M1\0" + /* 16940 */ "PseudoVSOXSEG6EI8_V_MF8_M1\0" + /* 16967 */ "PseudoVLUXSEG6EI8_V_MF8_M1\0" + /* 16994 */ "PseudoVSUXSEG6EI8_V_MF8_M1\0" + /* 17021 */ "PseudoVLOXSEG7EI8_V_MF8_M1\0" + /* 17048 */ "PseudoVSOXSEG7EI8_V_MF8_M1\0" + /* 17075 */ "PseudoVLUXSEG7EI8_V_MF8_M1\0" + /* 17102 */ "PseudoVSUXSEG7EI8_V_MF8_M1\0" + /* 17129 */ "PseudoVLOXSEG8EI8_V_MF8_M1\0" + /* 17156 */ "PseudoVSOXSEG8EI8_V_MF8_M1\0" + /* 17183 */ "PseudoVLUXSEG8EI8_V_MF8_M1\0" + /* 17210 */ "PseudoVSUXSEG8EI8_V_MF8_M1\0" + /* 17237 */ "PseudoVLOXEI8_V_MF8_M1\0" + /* 17260 */ "PseudoVSOXEI8_V_MF8_M1\0" + /* 17283 */ "PseudoVLUXEI8_V_MF8_M1\0" + /* 17306 */ "PseudoVSUXEI8_V_MF8_M1\0" + /* 17329 */ "PseudoVSEXT_VF8_M1\0" + /* 17348 */ "PseudoVZEXT_VF8_M1\0" + /* 17367 */ "PseudoVSPILL8_M1\0" + /* 17384 */ "PseudoVAMOADDEI8_WD_M8_M1\0" + /* 17410 */ "PseudoVAMOANDEI8_WD_M8_M1\0" + /* 17436 */ "PseudoVAMOMINEI8_WD_M8_M1\0" + /* 17462 */ "PseudoVAMOSWAPEI8_WD_M8_M1\0" + /* 17489 */ "PseudoVAMOOREI8_WD_M8_M1\0" + /* 17514 */ "PseudoVAMOXOREI8_WD_M8_M1\0" + /* 17540 */ "PseudoVAMOMINUEI8_WD_M8_M1\0" + /* 17567 */ "PseudoVAMOMAXUEI8_WD_M8_M1\0" + /* 17594 */ "PseudoVAMOMAXEI8_WD_M8_M1\0" + /* 17620 */ "PseudoVLOXSEG2EI64_V_M8_M1\0" + /* 17647 */ "PseudoVSOXSEG2EI64_V_M8_M1\0" + /* 17674 */ "PseudoVLUXSEG2EI64_V_M8_M1\0" + /* 17701 */ "PseudoVSUXSEG2EI64_V_M8_M1\0" + /* 17728 */ "PseudoVLOXSEG3EI64_V_M8_M1\0" + /* 17755 */ "PseudoVSOXSEG3EI64_V_M8_M1\0" + /* 17782 */ "PseudoVLUXSEG3EI64_V_M8_M1\0" + /* 17809 */ "PseudoVSUXSEG3EI64_V_M8_M1\0" + /* 17836 */ "PseudoVLOXSEG4EI64_V_M8_M1\0" + /* 17863 */ "PseudoVSOXSEG4EI64_V_M8_M1\0" + /* 17890 */ "PseudoVLUXSEG4EI64_V_M8_M1\0" + /* 17917 */ "PseudoVSUXSEG4EI64_V_M8_M1\0" + /* 17944 */ "PseudoVLOXSEG5EI64_V_M8_M1\0" + /* 17971 */ "PseudoVSOXSEG5EI64_V_M8_M1\0" + /* 17998 */ "PseudoVLUXSEG5EI64_V_M8_M1\0" + /* 18025 */ "PseudoVSUXSEG5EI64_V_M8_M1\0" + /* 18052 */ "PseudoVLOXSEG6EI64_V_M8_M1\0" + /* 18079 */ "PseudoVSOXSEG6EI64_V_M8_M1\0" + /* 18106 */ "PseudoVLUXSEG6EI64_V_M8_M1\0" + /* 18133 */ "PseudoVSUXSEG6EI64_V_M8_M1\0" + /* 18160 */ "PseudoVLOXSEG7EI64_V_M8_M1\0" + /* 18187 */ "PseudoVSOXSEG7EI64_V_M8_M1\0" + /* 18214 */ "PseudoVLUXSEG7EI64_V_M8_M1\0" + /* 18241 */ "PseudoVSUXSEG7EI64_V_M8_M1\0" + /* 18268 */ "PseudoVLOXSEG8EI64_V_M8_M1\0" + /* 18295 */ "PseudoVSOXSEG8EI64_V_M8_M1\0" + /* 18322 */ "PseudoVLUXSEG8EI64_V_M8_M1\0" + /* 18349 */ "PseudoVSUXSEG8EI64_V_M8_M1\0" + /* 18376 */ "PseudoVLOXEI64_V_M8_M1\0" + /* 18399 */ "PseudoVSOXEI64_V_M8_M1\0" + /* 18422 */ "PseudoVLUXEI64_V_M8_M1\0" + /* 18445 */ "PseudoVSUXEI64_V_M8_M1\0" + /* 18468 */ "PseudoVRELOAD_M1\0" + /* 18485 */ "PseudoVSSRA_VI_M1\0" + /* 18503 */ "PseudoVSRA_VI_M1\0" + /* 18520 */ "PseudoVRSUB_VI_M1\0" + /* 18538 */ "PseudoVMADC_VI_M1\0" + /* 18556 */ "PseudoVSADD_VI_M1\0" + /* 18574 */ "PseudoVADD_VI_M1\0" + /* 18591 */ "PseudoVAND_VI_M1\0" + /* 18608 */ "PseudoVMSLE_VI_M1\0" + /* 18626 */ "PseudoVMSNE_VI_M1\0" + /* 18644 */ "PseudoVSLL_VI_M1\0" + /* 18661 */ "PseudoVSSRL_VI_M1\0" + /* 18679 */ "PseudoVSRL_VI_M1\0" + /* 18696 */ "PseudoVSLIDEDOWN_VI_M1\0" + /* 18719 */ "PseudoVSLIDEUP_VI_M1\0" + /* 18740 */ "PseudoVMSEQ_VI_M1\0" + /* 18758 */ "PseudoVRGATHER_VI_M1\0" + /* 18779 */ "PseudoVOR_VI_M1\0" + /* 18795 */ "PseudoVXOR_VI_M1\0" + /* 18812 */ "PseudoVMSGT_VI_M1\0" + /* 18830 */ "PseudoVSADDU_VI_M1\0" + /* 18849 */ "PseudoVMSLEU_VI_M1\0" + /* 18868 */ "PseudoVMSGTU_VI_M1\0" + /* 18887 */ "PseudoVNSRA_WI_M1\0" + /* 18905 */ "PseudoVNSRL_WI_M1\0" + /* 18923 */ "PseudoVNCLIP_WI_M1\0" + /* 18942 */ "PseudoVNCLIPU_WI_M1\0" + /* 18962 */ "PseudoVMV_V_I_M1\0" + /* 18979 */ "PseudoVSPILL_M1\0" + /* 18995 */ "PseudoVFMERGE_VF32M_M1\0" + /* 19018 */ "PseudoVFMERGE_VF64M_M1\0" + /* 19041 */ "PseudoVFMERGE_VF16M_M1\0" + /* 19064 */ "PseudoVMADC_VIM_M1\0" + /* 19083 */ "PseudoVADC_VIM_M1\0" + /* 19101 */ "PseudoVMERGE_VIM_M1\0" + /* 19121 */ "PseudoVMAND_MM_M1\0" + /* 19139 */ "PseudoVMNAND_MM_M1\0" + /* 19158 */ "PseudoVMANDN_MM_M1\0" + /* 19177 */ "PseudoVMORN_MM_M1\0" + /* 19195 */ "PseudoVMOR_MM_M1\0" + /* 19212 */ "PseudoVMNOR_MM_M1\0" + /* 19230 */ "PseudoVMXNOR_MM_M1\0" + /* 19249 */ "PseudoVMXOR_MM_M1\0" + /* 19267 */ "PseudoVMSBC_VVM_M1\0" + /* 19286 */ "PseudoVSBC_VVM_M1\0" + /* 19304 */ "PseudoVMADC_VVM_M1\0" + /* 19323 */ "PseudoVADC_VVM_M1\0" + /* 19341 */ "PseudoVMERGE_VVM_M1\0" + /* 19361 */ "PseudoVCOMPRESS_VM_M1\0" + /* 19383 */ "PseudoVMSBC_VXM_M1\0" + /* 19402 */ "PseudoVSBC_VXM_M1\0" + /* 19420 */ "PseudoVMADC_VXM_M1\0" + /* 19439 */ "PseudoVADC_VXM_M1\0" + /* 19457 */ "PseudoVMERGE_VXM_M1\0" + /* 19477 */ "PseudoVIOTA_M_M1\0" + /* 19494 */ "PseudoVREDAND_VS_M1\0" + /* 19514 */ "PseudoVREDSUM_VS_M1\0" + /* 19534 */ "PseudoVWREDSUM_VS_M1\0" + /* 19555 */ "PseudoVFREDOSUM_VS_M1\0" + /* 19577 */ "PseudoVFWREDOSUM_VS_M1\0" + /* 19600 */ "PseudoVFREDUSUM_VS_M1\0" + /* 19622 */ "PseudoVFWREDUSUM_VS_M1\0" + /* 19645 */ "PseudoVFREDMIN_VS_M1\0" + /* 19666 */ "PseudoVREDMIN_VS_M1\0" + /* 19686 */ "PseudoVREDOR_VS_M1\0" + /* 19705 */ "PseudoVREDXOR_VS_M1\0" + /* 19725 */ "PseudoVWREDSUMU_VS_M1\0" + /* 19747 */ "PseudoVREDMINU_VS_M1\0" + /* 19768 */ "PseudoVREDMAXU_VS_M1\0" + /* 19789 */ "PseudoVFREDMAX_VS_M1\0" + /* 19810 */ "PseudoVREDMAX_VS_M1\0" + /* 19830 */ "PseudoVFMV_F32_S_M1\0" + /* 19850 */ "PseudoVFMV_F64_S_M1\0" + /* 19870 */ "PseudoVFMV_F16_S_M1\0" + /* 19890 */ "PseudoVMV_X_S_M1\0" + /* 19907 */ "PseudoVSSRA_VV_M1\0" + /* 19925 */ "PseudoVSRA_VV_M1\0" + /* 19942 */ "PseudoVASUB_VV_M1\0" + /* 19960 */ "PseudoVFSUB_VV_M1\0" + /* 19978 */ "PseudoVFMSUB_VV_M1\0" + /* 19997 */ "PseudoVFNMSUB_VV_M1\0" + /* 20017 */ "PseudoVNMSUB_VV_M1\0" + /* 20036 */ "PseudoVSSUB_VV_M1\0" + /* 20054 */ "PseudoVSUB_VV_M1\0" + /* 20071 */ "PseudoVFWSUB_VV_M1\0" + /* 20090 */ "PseudoVWSUB_VV_M1\0" + /* 20108 */ "PseudoVFMSAC_VV_M1\0" + /* 20127 */ "PseudoVFNMSAC_VV_M1\0" + /* 20147 */ "PseudoVNMSAC_VV_M1\0" + /* 20166 */ "PseudoVFWNMSAC_VV_M1\0" + /* 20187 */ "PseudoVFWMSAC_VV_M1\0" + /* 20207 */ "PseudoVMSBC_VV_M1\0" + /* 20225 */ "PseudoVFMACC_VV_M1\0" + /* 20244 */ "PseudoVFNMACC_VV_M1\0" + /* 20264 */ "PseudoVFWNMACC_VV_M1\0" + /* 20285 */ "PseudoVMACC_VV_M1\0" + /* 20303 */ "PseudoVFWMACC_VV_M1\0" + /* 20323 */ "PseudoVWMACC_VV_M1\0" + /* 20342 */ "PseudoVMADC_VV_M1\0" + /* 20360 */ "PseudoVAADD_VV_M1\0" + /* 20378 */ "PseudoVFADD_VV_M1\0" + /* 20396 */ "PseudoVFMADD_VV_M1\0" + /* 20415 */ "PseudoVFNMADD_VV_M1\0" + /* 20435 */ "PseudoVMADD_VV_M1\0" + /* 20453 */ "PseudoVSADD_VV_M1\0" + /* 20471 */ "PseudoVADD_VV_M1\0" + /* 20488 */ "PseudoVFWADD_VV_M1\0" + /* 20507 */ "PseudoVWADD_VV_M1\0" + /* 20525 */ "PseudoVAND_VV_M1\0" + /* 20542 */ "PseudoVMFLE_VV_M1\0" + /* 20560 */ "PseudoVMSLE_VV_M1\0" + /* 20578 */ "PseudoVMFNE_VV_M1\0" + /* 20596 */ "PseudoVMSNE_VV_M1\0" + /* 20614 */ "PseudoVMULH_VV_M1\0" + /* 20632 */ "PseudoVFSGNJ_VV_M1\0" + /* 20651 */ "PseudoVSLL_VV_M1\0" + /* 20668 */ "PseudoVSSRL_VV_M1\0" + /* 20686 */ "PseudoVSRL_VV_M1\0" + /* 20703 */ "PseudoVFMUL_VV_M1\0" + /* 20721 */ "PseudoVSMUL_VV_M1\0" + /* 20739 */ "PseudoVMUL_VV_M1\0" + /* 20756 */ "PseudoVFWMUL_VV_M1\0" + /* 20775 */ "PseudoVWMUL_VV_M1\0" + /* 20793 */ "PseudoVREM_VV_M1\0" + /* 20810 */ "PseudoVFMIN_VV_M1\0" + /* 20828 */ "PseudoVMIN_VV_M1\0" + /* 20845 */ "PseudoVFSGNJN_VV_M1\0" + /* 20865 */ "PseudoVMFEQ_VV_M1\0" + /* 20883 */ "PseudoVMSEQ_VV_M1\0" + /* 20901 */ "PseudoVRGATHER_VV_M1\0" + /* 20922 */ "PseudoVOR_VV_M1\0" + /* 20938 */ "PseudoVXOR_VV_M1\0" + /* 20955 */ "PseudoVMFLT_VV_M1\0" + /* 20973 */ "PseudoVMSLT_VV_M1\0" + /* 20991 */ "PseudoVASUBU_VV_M1\0" + /* 21010 */ "PseudoVSSUBU_VV_M1\0" + /* 21029 */ "PseudoVWSUBU_VV_M1\0" + /* 21048 */ "PseudoVWMACCU_VV_M1\0" + /* 21068 */ "PseudoVAADDU_VV_M1\0" + /* 21087 */ "PseudoVSADDU_VV_M1\0" + /* 21106 */ "PseudoVWADDU_VV_M1\0" + /* 21125 */ "PseudoVMSLEU_VV_M1\0" + /* 21144 */ "PseudoVMULHU_VV_M1\0" + /* 21163 */ "PseudoVWMULU_VV_M1\0" + /* 21182 */ "PseudoVREMU_VV_M1\0" + /* 21200 */ "PseudoVMINU_VV_M1\0" + /* 21218 */ "PseudoVWMACCSU_VV_M1\0" + /* 21239 */ "PseudoVMULHSU_VV_M1\0" + /* 21259 */ "PseudoVWMULSU_VV_M1\0" + /* 21279 */ "PseudoVMSLTU_VV_M1\0" + /* 21298 */ "PseudoVDIVU_VV_M1\0" + /* 21316 */ "PseudoVMAXU_VV_M1\0" + /* 21334 */ "PseudoVFDIV_VV_M1\0" + /* 21352 */ "PseudoVDIV_VV_M1\0" + /* 21369 */ "PseudoVFMAX_VV_M1\0" + /* 21387 */ "PseudoVMAX_VV_M1\0" + /* 21404 */ "PseudoVFSGNJX_VV_M1\0" + /* 21424 */ "PseudoVNSRA_WV_M1\0" + /* 21442 */ "PseudoVFWSUB_WV_M1\0" + /* 21461 */ "PseudoVWSUB_WV_M1\0" + /* 21479 */ "PseudoVFWADD_WV_M1\0" + /* 21498 */ "PseudoVWADD_WV_M1\0" + /* 21516 */ "PseudoVNSRL_WV_M1\0" + /* 21534 */ "PseudoVNCLIP_WV_M1\0" + /* 21553 */ "PseudoVWSUBU_WV_M1\0" + /* 21572 */ "PseudoVWADDU_WV_M1\0" + /* 21591 */ "PseudoVNCLIPU_WV_M1\0" + /* 21611 */ "PseudoVLSEG2E32_V_M1\0" + /* 21632 */ "PseudoVLSSEG2E32_V_M1\0" + /* 21654 */ "PseudoVSSSEG2E32_V_M1\0" + /* 21676 */ "PseudoVSSEG2E32_V_M1\0" + /* 21697 */ "PseudoVLSEG3E32_V_M1\0" + /* 21718 */ "PseudoVLSSEG3E32_V_M1\0" + /* 21740 */ "PseudoVSSSEG3E32_V_M1\0" + /* 21762 */ "PseudoVSSEG3E32_V_M1\0" + /* 21783 */ "PseudoVLSEG4E32_V_M1\0" + /* 21804 */ "PseudoVLSSEG4E32_V_M1\0" + /* 21826 */ "PseudoVSSSEG4E32_V_M1\0" + /* 21848 */ "PseudoVSSEG4E32_V_M1\0" + /* 21869 */ "PseudoVLSEG5E32_V_M1\0" + /* 21890 */ "PseudoVLSSEG5E32_V_M1\0" + /* 21912 */ "PseudoVSSSEG5E32_V_M1\0" + /* 21934 */ "PseudoVSSEG5E32_V_M1\0" + /* 21955 */ "PseudoVLSEG6E32_V_M1\0" + /* 21976 */ "PseudoVLSSEG6E32_V_M1\0" + /* 21998 */ "PseudoVSSSEG6E32_V_M1\0" + /* 22020 */ "PseudoVSSEG6E32_V_M1\0" + /* 22041 */ "PseudoVLSEG7E32_V_M1\0" + /* 22062 */ "PseudoVLSSEG7E32_V_M1\0" + /* 22084 */ "PseudoVSSSEG7E32_V_M1\0" + /* 22106 */ "PseudoVSSEG7E32_V_M1\0" + /* 22127 */ "PseudoVLSEG8E32_V_M1\0" + /* 22148 */ "PseudoVLSSEG8E32_V_M1\0" + /* 22170 */ "PseudoVSSSEG8E32_V_M1\0" + /* 22192 */ "PseudoVSSEG8E32_V_M1\0" + /* 22213 */ "PseudoVLE32_V_M1\0" + /* 22230 */ "PseudoVLSE32_V_M1\0" + /* 22248 */ "PseudoVSSE32_V_M1\0" + /* 22266 */ "PseudoVSE32_V_M1\0" + /* 22283 */ "PseudoVLSEG2E64_V_M1\0" + /* 22304 */ "PseudoVLSSEG2E64_V_M1\0" + /* 22326 */ "PseudoVSSSEG2E64_V_M1\0" + /* 22348 */ "PseudoVSSEG2E64_V_M1\0" + /* 22369 */ "PseudoVLSEG3E64_V_M1\0" + /* 22390 */ "PseudoVLSSEG3E64_V_M1\0" + /* 22412 */ "PseudoVSSSEG3E64_V_M1\0" + /* 22434 */ "PseudoVSSEG3E64_V_M1\0" + /* 22455 */ "PseudoVLSEG4E64_V_M1\0" + /* 22476 */ "PseudoVLSSEG4E64_V_M1\0" + /* 22498 */ "PseudoVSSSEG4E64_V_M1\0" + /* 22520 */ "PseudoVSSEG4E64_V_M1\0" + /* 22541 */ "PseudoVLSEG5E64_V_M1\0" + /* 22562 */ "PseudoVLSSEG5E64_V_M1\0" + /* 22584 */ "PseudoVSSSEG5E64_V_M1\0" + /* 22606 */ "PseudoVSSEG5E64_V_M1\0" + /* 22627 */ "PseudoVLSEG6E64_V_M1\0" + /* 22648 */ "PseudoVLSSEG6E64_V_M1\0" + /* 22670 */ "PseudoVSSSEG6E64_V_M1\0" + /* 22692 */ "PseudoVSSEG6E64_V_M1\0" + /* 22713 */ "PseudoVLSEG7E64_V_M1\0" + /* 22734 */ "PseudoVLSSEG7E64_V_M1\0" + /* 22756 */ "PseudoVSSSEG7E64_V_M1\0" + /* 22778 */ "PseudoVSSEG7E64_V_M1\0" + /* 22799 */ "PseudoVLSEG8E64_V_M1\0" + /* 22820 */ "PseudoVLSSEG8E64_V_M1\0" + /* 22842 */ "PseudoVSSSEG8E64_V_M1\0" + /* 22864 */ "PseudoVSSEG8E64_V_M1\0" + /* 22885 */ "PseudoVLE64_V_M1\0" + /* 22902 */ "PseudoVLSE64_V_M1\0" + /* 22920 */ "PseudoVSSE64_V_M1\0" + /* 22938 */ "PseudoVSE64_V_M1\0" + /* 22955 */ "PseudoVLSEG2E16_V_M1\0" + /* 22976 */ "PseudoVLSSEG2E16_V_M1\0" + /* 22998 */ "PseudoVSSSEG2E16_V_M1\0" + /* 23020 */ "PseudoVSSEG2E16_V_M1\0" + /* 23041 */ "PseudoVLSEG3E16_V_M1\0" + /* 23062 */ "PseudoVLSSEG3E16_V_M1\0" + /* 23084 */ "PseudoVSSSEG3E16_V_M1\0" + /* 23106 */ "PseudoVSSEG3E16_V_M1\0" + /* 23127 */ "PseudoVLSEG4E16_V_M1\0" + /* 23148 */ "PseudoVLSSEG4E16_V_M1\0" + /* 23170 */ "PseudoVSSSEG4E16_V_M1\0" + /* 23192 */ "PseudoVSSEG4E16_V_M1\0" + /* 23213 */ "PseudoVLSEG5E16_V_M1\0" + /* 23234 */ "PseudoVLSSEG5E16_V_M1\0" + /* 23256 */ "PseudoVSSSEG5E16_V_M1\0" + /* 23278 */ "PseudoVSSEG5E16_V_M1\0" + /* 23299 */ "PseudoVLSEG6E16_V_M1\0" + /* 23320 */ "PseudoVLSSEG6E16_V_M1\0" + /* 23342 */ "PseudoVSSSEG6E16_V_M1\0" + /* 23364 */ "PseudoVSSEG6E16_V_M1\0" + /* 23385 */ "PseudoVLSEG7E16_V_M1\0" + /* 23406 */ "PseudoVLSSEG7E16_V_M1\0" + /* 23428 */ "PseudoVSSSEG7E16_V_M1\0" + /* 23450 */ "PseudoVSSEG7E16_V_M1\0" + /* 23471 */ "PseudoVLSEG8E16_V_M1\0" + /* 23492 */ "PseudoVLSSEG8E16_V_M1\0" + /* 23514 */ "PseudoVSSSEG8E16_V_M1\0" + /* 23536 */ "PseudoVSSEG8E16_V_M1\0" + /* 23557 */ "PseudoVLE16_V_M1\0" + /* 23574 */ "PseudoVLSE16_V_M1\0" + /* 23592 */ "PseudoVSSE16_V_M1\0" + /* 23610 */ "PseudoVSE16_V_M1\0" + /* 23627 */ "PseudoVFREC7_V_M1\0" + /* 23645 */ "PseudoVFRSQRT7_V_M1\0" + /* 23665 */ "PseudoVLSEG2E8_V_M1\0" + /* 23685 */ "PseudoVLSSEG2E8_V_M1\0" + /* 23706 */ "PseudoVSSSEG2E8_V_M1\0" + /* 23727 */ "PseudoVSSEG2E8_V_M1\0" + /* 23747 */ "PseudoVLSEG3E8_V_M1\0" + /* 23767 */ "PseudoVLSSEG3E8_V_M1\0" + /* 23788 */ "PseudoVSSSEG3E8_V_M1\0" + /* 23809 */ "PseudoVSSEG3E8_V_M1\0" + /* 23829 */ "PseudoVLSEG4E8_V_M1\0" + /* 23849 */ "PseudoVLSSEG4E8_V_M1\0" + /* 23870 */ "PseudoVSSSEG4E8_V_M1\0" + /* 23891 */ "PseudoVSSEG4E8_V_M1\0" + /* 23911 */ "PseudoVLSEG5E8_V_M1\0" + /* 23931 */ "PseudoVLSSEG5E8_V_M1\0" + /* 23952 */ "PseudoVSSSEG5E8_V_M1\0" + /* 23973 */ "PseudoVSSEG5E8_V_M1\0" + /* 23993 */ "PseudoVLSEG6E8_V_M1\0" + /* 24013 */ "PseudoVLSSEG6E8_V_M1\0" + /* 24034 */ "PseudoVSSSEG6E8_V_M1\0" + /* 24055 */ "PseudoVSSEG6E8_V_M1\0" + /* 24075 */ "PseudoVLSEG7E8_V_M1\0" + /* 24095 */ "PseudoVLSSEG7E8_V_M1\0" + /* 24116 */ "PseudoVSSSEG7E8_V_M1\0" + /* 24137 */ "PseudoVSSEG7E8_V_M1\0" + /* 24157 */ "PseudoVLSEG8E8_V_M1\0" + /* 24177 */ "PseudoVLSSEG8E8_V_M1\0" + /* 24198 */ "PseudoVSSSEG8E8_V_M1\0" + /* 24219 */ "PseudoVSSEG8E8_V_M1\0" + /* 24239 */ "PseudoVLE8_V_M1\0" + /* 24255 */ "PseudoVLSE8_V_M1\0" + /* 24272 */ "PseudoVSSE8_V_M1\0" + /* 24289 */ "PseudoVSE8_V_M1\0" + /* 24305 */ "PseudoVID_V_M1\0" + /* 24320 */ "PseudoVLSEG2E32FF_V_M1\0" + /* 24343 */ "PseudoVLSEG3E32FF_V_M1\0" + /* 24366 */ "PseudoVLSEG4E32FF_V_M1\0" + /* 24389 */ "PseudoVLSEG5E32FF_V_M1\0" + /* 24412 */ "PseudoVLSEG6E32FF_V_M1\0" + /* 24435 */ "PseudoVLSEG7E32FF_V_M1\0" + /* 24458 */ "PseudoVLSEG8E32FF_V_M1\0" + /* 24481 */ "PseudoVLE32FF_V_M1\0" + /* 24500 */ "PseudoVLSEG2E64FF_V_M1\0" + /* 24523 */ "PseudoVLSEG3E64FF_V_M1\0" + /* 24546 */ "PseudoVLSEG4E64FF_V_M1\0" + /* 24569 */ "PseudoVLSEG5E64FF_V_M1\0" + /* 24592 */ "PseudoVLSEG6E64FF_V_M1\0" + /* 24615 */ "PseudoVLSEG7E64FF_V_M1\0" + /* 24638 */ "PseudoVLSEG8E64FF_V_M1\0" + /* 24661 */ "PseudoVLE64FF_V_M1\0" + /* 24680 */ "PseudoVLSEG2E16FF_V_M1\0" + /* 24703 */ "PseudoVLSEG3E16FF_V_M1\0" + /* 24726 */ "PseudoVLSEG4E16FF_V_M1\0" + /* 24749 */ "PseudoVLSEG5E16FF_V_M1\0" + /* 24772 */ "PseudoVLSEG6E16FF_V_M1\0" + /* 24795 */ "PseudoVLSEG7E16FF_V_M1\0" + /* 24818 */ "PseudoVLSEG8E16FF_V_M1\0" + /* 24841 */ "PseudoVLE16FF_V_M1\0" + /* 24860 */ "PseudoVLSEG2E8FF_V_M1\0" + /* 24882 */ "PseudoVLSEG3E8FF_V_M1\0" + /* 24904 */ "PseudoVLSEG4E8FF_V_M1\0" + /* 24926 */ "PseudoVLSEG5E8FF_V_M1\0" + /* 24948 */ "PseudoVLSEG6E8FF_V_M1\0" + /* 24970 */ "PseudoVLSEG7E8FF_V_M1\0" + /* 24992 */ "PseudoVLSEG8E8FF_V_M1\0" + /* 25014 */ "PseudoVLE8FF_V_M1\0" + /* 25032 */ "PseudoVFWCVT_F_F_V_M1\0" + /* 25054 */ "PseudoVFCVT_XU_F_V_M1\0" + /* 25076 */ "PseudoVFWCVT_XU_F_V_M1\0" + /* 25099 */ "PseudoVFCVT_RTZ_XU_F_V_M1\0" + /* 25125 */ "PseudoVFWCVT_RTZ_XU_F_V_M1\0" + /* 25152 */ "PseudoVFCVT_X_F_V_M1\0" + /* 25173 */ "PseudoVFWCVT_X_F_V_M1\0" + /* 25195 */ "PseudoVFCVT_RTZ_X_F_V_M1\0" + /* 25220 */ "PseudoVFWCVT_RTZ_X_F_V_M1\0" + /* 25246 */ "PseudoVFCLASS_V_M1\0" + /* 25265 */ "PseudoVFSQRT_V_M1\0" + /* 25283 */ "PseudoVFCVT_F_XU_V_M1\0" + /* 25305 */ "PseudoVFWCVT_F_XU_V_M1\0" + /* 25328 */ "PseudoVMV_V_V_M1\0" + /* 25345 */ "PseudoVFCVT_F_X_V_M1\0" + /* 25366 */ "PseudoVFWCVT_F_X_V_M1\0" + /* 25388 */ "PseudoVFNCVT_ROD_F_F_W_M1\0" + /* 25414 */ "PseudoVFNCVT_F_F_W_M1\0" + /* 25436 */ "PseudoVFNCVT_XU_F_W_M1\0" + /* 25459 */ "PseudoVFNCVT_RTZ_XU_F_W_M1\0" + /* 25486 */ "PseudoVFNCVT_X_F_W_M1\0" + /* 25508 */ "PseudoVFNCVT_RTZ_X_F_W_M1\0" + /* 25534 */ "PseudoVFNCVT_F_XU_W_M1\0" + /* 25557 */ "PseudoVFNCVT_F_X_W_M1\0" + /* 25579 */ "PseudoVSSRA_VX_M1\0" + /* 25597 */ "PseudoVSRA_VX_M1\0" + /* 25614 */ "PseudoVASUB_VX_M1\0" + /* 25632 */ "PseudoVNMSUB_VX_M1\0" + /* 25651 */ "PseudoVRSUB_VX_M1\0" + /* 25669 */ "PseudoVSSUB_VX_M1\0" + /* 25687 */ "PseudoVSUB_VX_M1\0" + /* 25704 */ "PseudoVWSUB_VX_M1\0" + /* 25722 */ "PseudoVNMSAC_VX_M1\0" + /* 25741 */ "PseudoVMSBC_VX_M1\0" + /* 25759 */ "PseudoVMACC_VX_M1\0" + /* 25777 */ "PseudoVWMACC_VX_M1\0" + /* 25796 */ "PseudoVMADC_VX_M1\0" + /* 25814 */ "PseudoVAADD_VX_M1\0" + /* 25832 */ "PseudoVMADD_VX_M1\0" + /* 25850 */ "PseudoVSADD_VX_M1\0" + /* 25868 */ "PseudoVADD_VX_M1\0" + /* 25885 */ "PseudoVWADD_VX_M1\0" + /* 25903 */ "PseudoVAND_VX_M1\0" + /* 25920 */ "PseudoVMSLE_VX_M1\0" + /* 25938 */ "PseudoVMSNE_VX_M1\0" + /* 25956 */ "PseudoVMULH_VX_M1\0" + /* 25974 */ "PseudoVSLL_VX_M1\0" + /* 25991 */ "PseudoVSSRL_VX_M1\0" + /* 26009 */ "PseudoVSRL_VX_M1\0" + /* 26026 */ "PseudoVSMUL_VX_M1\0" + /* 26044 */ "PseudoVMUL_VX_M1\0" + /* 26061 */ "PseudoVWMUL_VX_M1\0" + /* 26079 */ "PseudoVREM_VX_M1\0" + /* 26096 */ "PseudoVMIN_VX_M1\0" + /* 26113 */ "PseudoVSLIDE1DOWN_VX_M1\0" + /* 26137 */ "PseudoVSLIDEDOWN_VX_M1\0" + /* 26160 */ "PseudoVSLIDE1UP_VX_M1\0" + /* 26182 */ "PseudoVSLIDEUP_VX_M1\0" + /* 26203 */ "PseudoVMSEQ_VX_M1\0" + /* 26221 */ "PseudoVRGATHER_VX_M1\0" + /* 26242 */ "PseudoVOR_VX_M1\0" + /* 26258 */ "PseudoVXOR_VX_M1\0" + /* 26275 */ "PseudoVWMACCUS_VX_M1\0" + /* 26296 */ "PseudoVMSGT_VX_M1\0" + /* 26314 */ "PseudoVMSLT_VX_M1\0" + /* 26332 */ "PseudoVASUBU_VX_M1\0" + /* 26351 */ "PseudoVSSUBU_VX_M1\0" + /* 26370 */ "PseudoVWSUBU_VX_M1\0" + /* 26389 */ "PseudoVWMACCU_VX_M1\0" + /* 26409 */ "PseudoVAADDU_VX_M1\0" + /* 26428 */ "PseudoVSADDU_VX_M1\0" + /* 26447 */ "PseudoVWADDU_VX_M1\0" + /* 26466 */ "PseudoVMSLEU_VX_M1\0" + /* 26485 */ "PseudoVMULHU_VX_M1\0" + /* 26504 */ "PseudoVWMULU_VX_M1\0" + /* 26523 */ "PseudoVREMU_VX_M1\0" + /* 26541 */ "PseudoVMINU_VX_M1\0" + /* 26559 */ "PseudoVWMACCSU_VX_M1\0" + /* 26580 */ "PseudoVMULHSU_VX_M1\0" + /* 26600 */ "PseudoVWMULSU_VX_M1\0" + /* 26620 */ "PseudoVMSGTU_VX_M1\0" + /* 26639 */ "PseudoVMSLTU_VX_M1\0" + /* 26658 */ "PseudoVDIVU_VX_M1\0" + /* 26676 */ "PseudoVMAXU_VX_M1\0" + /* 26694 */ "PseudoVDIV_VX_M1\0" + /* 26711 */ "PseudoVMAX_VX_M1\0" + /* 26728 */ "PseudoVNSRA_WX_M1\0" + /* 26746 */ "PseudoVWSUB_WX_M1\0" + /* 26764 */ "PseudoVWADD_WX_M1\0" + /* 26782 */ "PseudoVNSRL_WX_M1\0" + /* 26800 */ "PseudoVNCLIP_WX_M1\0" + /* 26819 */ "PseudoVWSUBU_WX_M1\0" + /* 26838 */ "PseudoVWADDU_WX_M1\0" + /* 26857 */ "PseudoVNCLIPU_WX_M1\0" + /* 26877 */ "PseudoVMV_S_X_M1\0" + /* 26894 */ "PseudoVMV_V_X_M1\0" + /* 26911 */ "PseudoVMSBF_M_B32\0" + /* 26929 */ "PseudoVMSIF_M_B32\0" + /* 26947 */ "PseudoVMSOF_M_B32\0" + /* 26965 */ "PseudoVCPOP_M_B32\0" + /* 26983 */ "PseudoVMCLR_M_B32\0" + /* 27001 */ "PseudoVMSET_M_B32\0" + /* 27019 */ "PseudoVFIRST_M_B32\0" + /* 27038 */ "PseudoVLM_V_B32\0" + /* 27054 */ "PseudoVSM_V_B32\0" + /* 27070 */ "REV8_RV32\0" + /* 27080 */ "ZEXTH_RV32\0" + /* 27091 */ "PseudoMaskedAtomicLoadSub32\0" + /* 27119 */ "PseudoMaskedAtomicLoadAdd32\0" + /* 27147 */ "PseudoMaskedAtomicLoadNand32\0" + /* 27176 */ "PseudoAtomicLoadNand32\0" + /* 27199 */ "PseudoMaskedCmpXchg32\0" + /* 27221 */ "PseudoCmpXchg32\0" + /* 27237 */ "PseudoMaskedAtomicLoadUMin32\0" + /* 27266 */ "PseudoMaskedAtomicLoadMin32\0" + /* 27294 */ "PseudoMaskedAtomicSwap32\0" + /* 27319 */ "PseudoMaskedAtomicLoadUMax32\0" + /* 27348 */ "PseudoMaskedAtomicLoadMax32\0" + /* 27376 */ "PseudoVMSBF_M_B2\0" + /* 27393 */ "PseudoVMSIF_M_B2\0" + /* 27410 */ "PseudoVMSOF_M_B2\0" + /* 27427 */ "PseudoVCPOP_M_B2\0" + /* 27444 */ "PseudoVMCLR_M_B2\0" + /* 27461 */ "PseudoVMSET_M_B2\0" + /* 27478 */ "PseudoVFIRST_M_B2\0" + /* 27496 */ "PseudoVLM_V_B2\0" + /* 27511 */ "PseudoVSM_V_B2\0" + /* 27526 */ "PseudoVAMOADDEI32_WD_M1_MF2\0" + /* 27554 */ "PseudoVAMOANDEI32_WD_M1_MF2\0" + /* 27582 */ "PseudoVAMOMINEI32_WD_M1_MF2\0" + /* 27610 */ "PseudoVAMOSWAPEI32_WD_M1_MF2\0" + /* 27639 */ "PseudoVAMOOREI32_WD_M1_MF2\0" + /* 27666 */ "PseudoVAMOXOREI32_WD_M1_MF2\0" + /* 27694 */ "PseudoVAMOMINUEI32_WD_M1_MF2\0" + /* 27723 */ "PseudoVAMOMAXUEI32_WD_M1_MF2\0" + /* 27752 */ "PseudoVAMOMAXEI32_WD_M1_MF2\0" + /* 27780 */ "PseudoVAMOADDEI16_WD_M1_MF2\0" + /* 27808 */ "PseudoVAMOANDEI16_WD_M1_MF2\0" + /* 27836 */ "PseudoVAMOMINEI16_WD_M1_MF2\0" + /* 27864 */ "PseudoVAMOSWAPEI16_WD_M1_MF2\0" + /* 27893 */ "PseudoVAMOOREI16_WD_M1_MF2\0" + /* 27920 */ "PseudoVAMOXOREI16_WD_M1_MF2\0" + /* 27948 */ "PseudoVAMOMINUEI16_WD_M1_MF2\0" + /* 27977 */ "PseudoVAMOMAXUEI16_WD_M1_MF2\0" + /* 28006 */ "PseudoVAMOMAXEI16_WD_M1_MF2\0" + /* 28034 */ "PseudoVRGATHEREI16_VV_M1_MF2\0" + /* 28063 */ "PseudoVLOXSEG2EI32_V_M1_MF2\0" + /* 28091 */ "PseudoVSOXSEG2EI32_V_M1_MF2\0" + /* 28119 */ "PseudoVLUXSEG2EI32_V_M1_MF2\0" + /* 28147 */ "PseudoVSUXSEG2EI32_V_M1_MF2\0" + /* 28175 */ "PseudoVLOXSEG3EI32_V_M1_MF2\0" + /* 28203 */ "PseudoVSOXSEG3EI32_V_M1_MF2\0" + /* 28231 */ "PseudoVLUXSEG3EI32_V_M1_MF2\0" + /* 28259 */ "PseudoVSUXSEG3EI32_V_M1_MF2\0" + /* 28287 */ "PseudoVLOXSEG4EI32_V_M1_MF2\0" + /* 28315 */ "PseudoVSOXSEG4EI32_V_M1_MF2\0" + /* 28343 */ "PseudoVLUXSEG4EI32_V_M1_MF2\0" + /* 28371 */ "PseudoVSUXSEG4EI32_V_M1_MF2\0" + /* 28399 */ "PseudoVLOXSEG5EI32_V_M1_MF2\0" + /* 28427 */ "PseudoVSOXSEG5EI32_V_M1_MF2\0" + /* 28455 */ "PseudoVLUXSEG5EI32_V_M1_MF2\0" + /* 28483 */ "PseudoVSUXSEG5EI32_V_M1_MF2\0" + /* 28511 */ "PseudoVLOXSEG6EI32_V_M1_MF2\0" + /* 28539 */ "PseudoVSOXSEG6EI32_V_M1_MF2\0" + /* 28567 */ "PseudoVLUXSEG6EI32_V_M1_MF2\0" + /* 28595 */ "PseudoVSUXSEG6EI32_V_M1_MF2\0" + /* 28623 */ "PseudoVLOXSEG7EI32_V_M1_MF2\0" + /* 28651 */ "PseudoVSOXSEG7EI32_V_M1_MF2\0" + /* 28679 */ "PseudoVLUXSEG7EI32_V_M1_MF2\0" + /* 28707 */ "PseudoVSUXSEG7EI32_V_M1_MF2\0" + /* 28735 */ "PseudoVLOXSEG8EI32_V_M1_MF2\0" + /* 28763 */ "PseudoVSOXSEG8EI32_V_M1_MF2\0" + /* 28791 */ "PseudoVLUXSEG8EI32_V_M1_MF2\0" + /* 28819 */ "PseudoVSUXSEG8EI32_V_M1_MF2\0" + /* 28847 */ "PseudoVLOXEI32_V_M1_MF2\0" + /* 28871 */ "PseudoVSOXEI32_V_M1_MF2\0" + /* 28895 */ "PseudoVLUXEI32_V_M1_MF2\0" + /* 28919 */ "PseudoVSUXEI32_V_M1_MF2\0" + /* 28943 */ "PseudoVLOXSEG2EI64_V_M1_MF2\0" + /* 28971 */ "PseudoVSOXSEG2EI64_V_M1_MF2\0" + /* 28999 */ "PseudoVLUXSEG2EI64_V_M1_MF2\0" + /* 29027 */ "PseudoVSUXSEG2EI64_V_M1_MF2\0" + /* 29055 */ "PseudoVLOXSEG3EI64_V_M1_MF2\0" + /* 29083 */ "PseudoVSOXSEG3EI64_V_M1_MF2\0" + /* 29111 */ "PseudoVLUXSEG3EI64_V_M1_MF2\0" + /* 29139 */ "PseudoVSUXSEG3EI64_V_M1_MF2\0" + /* 29167 */ "PseudoVLOXSEG4EI64_V_M1_MF2\0" + /* 29195 */ "PseudoVSOXSEG4EI64_V_M1_MF2\0" + /* 29223 */ "PseudoVLUXSEG4EI64_V_M1_MF2\0" + /* 29251 */ "PseudoVSUXSEG4EI64_V_M1_MF2\0" + /* 29279 */ "PseudoVLOXSEG5EI64_V_M1_MF2\0" + /* 29307 */ "PseudoVSOXSEG5EI64_V_M1_MF2\0" + /* 29335 */ "PseudoVLUXSEG5EI64_V_M1_MF2\0" + /* 29363 */ "PseudoVSUXSEG5EI64_V_M1_MF2\0" + /* 29391 */ "PseudoVLOXSEG6EI64_V_M1_MF2\0" + /* 29419 */ "PseudoVSOXSEG6EI64_V_M1_MF2\0" + /* 29447 */ "PseudoVLUXSEG6EI64_V_M1_MF2\0" + /* 29475 */ "PseudoVSUXSEG6EI64_V_M1_MF2\0" + /* 29503 */ "PseudoVLOXSEG7EI64_V_M1_MF2\0" + /* 29531 */ "PseudoVSOXSEG7EI64_V_M1_MF2\0" + /* 29559 */ "PseudoVLUXSEG7EI64_V_M1_MF2\0" + /* 29587 */ "PseudoVSUXSEG7EI64_V_M1_MF2\0" + /* 29615 */ "PseudoVLOXSEG8EI64_V_M1_MF2\0" + /* 29643 */ "PseudoVSOXSEG8EI64_V_M1_MF2\0" + /* 29671 */ "PseudoVLUXSEG8EI64_V_M1_MF2\0" + /* 29699 */ "PseudoVSUXSEG8EI64_V_M1_MF2\0" + /* 29727 */ "PseudoVLOXEI64_V_M1_MF2\0" + /* 29751 */ "PseudoVSOXEI64_V_M1_MF2\0" + /* 29775 */ "PseudoVLUXEI64_V_M1_MF2\0" + /* 29799 */ "PseudoVSUXEI64_V_M1_MF2\0" + /* 29823 */ "PseudoVLOXSEG2EI16_V_M1_MF2\0" + /* 29851 */ "PseudoVSOXSEG2EI16_V_M1_MF2\0" + /* 29879 */ "PseudoVLUXSEG2EI16_V_M1_MF2\0" + /* 29907 */ "PseudoVSUXSEG2EI16_V_M1_MF2\0" + /* 29935 */ "PseudoVLOXSEG3EI16_V_M1_MF2\0" + /* 29963 */ "PseudoVSOXSEG3EI16_V_M1_MF2\0" + /* 29991 */ "PseudoVLUXSEG3EI16_V_M1_MF2\0" + /* 30019 */ "PseudoVSUXSEG3EI16_V_M1_MF2\0" + /* 30047 */ "PseudoVLOXSEG4EI16_V_M1_MF2\0" + /* 30075 */ "PseudoVSOXSEG4EI16_V_M1_MF2\0" + /* 30103 */ "PseudoVLUXSEG4EI16_V_M1_MF2\0" + /* 30131 */ "PseudoVSUXSEG4EI16_V_M1_MF2\0" + /* 30159 */ "PseudoVLOXSEG5EI16_V_M1_MF2\0" + /* 30187 */ "PseudoVSOXSEG5EI16_V_M1_MF2\0" + /* 30215 */ "PseudoVLUXSEG5EI16_V_M1_MF2\0" + /* 30243 */ "PseudoVSUXSEG5EI16_V_M1_MF2\0" + /* 30271 */ "PseudoVLOXSEG6EI16_V_M1_MF2\0" + /* 30299 */ "PseudoVSOXSEG6EI16_V_M1_MF2\0" + /* 30327 */ "PseudoVLUXSEG6EI16_V_M1_MF2\0" + /* 30355 */ "PseudoVSUXSEG6EI16_V_M1_MF2\0" + /* 30383 */ "PseudoVLOXSEG7EI16_V_M1_MF2\0" + /* 30411 */ "PseudoVSOXSEG7EI16_V_M1_MF2\0" + /* 30439 */ "PseudoVLUXSEG7EI16_V_M1_MF2\0" + /* 30467 */ "PseudoVSUXSEG7EI16_V_M1_MF2\0" + /* 30495 */ "PseudoVLOXSEG8EI16_V_M1_MF2\0" + /* 30523 */ "PseudoVSOXSEG8EI16_V_M1_MF2\0" + /* 30551 */ "PseudoVLUXSEG8EI16_V_M1_MF2\0" + /* 30579 */ "PseudoVSUXSEG8EI16_V_M1_MF2\0" + /* 30607 */ "PseudoVLOXEI16_V_M1_MF2\0" + /* 30631 */ "PseudoVSOXEI16_V_M1_MF2\0" + /* 30655 */ "PseudoVLUXEI16_V_M1_MF2\0" + /* 30679 */ "PseudoVSUXEI16_V_M1_MF2\0" + /* 30703 */ "PseudoVFSUB_VF32_MF2\0" + /* 30724 */ "PseudoVFMSUB_VF32_MF2\0" + /* 30746 */ "PseudoVFNMSUB_VF32_MF2\0" + /* 30769 */ "PseudoVFRSUB_VF32_MF2\0" + /* 30791 */ "PseudoVFWSUB_VF32_MF2\0" + /* 30813 */ "PseudoVFMSAC_VF32_MF2\0" + /* 30835 */ "PseudoVFNMSAC_VF32_MF2\0" + /* 30858 */ "PseudoVFWNMSAC_VF32_MF2\0" + /* 30882 */ "PseudoVFWMSAC_VF32_MF2\0" + /* 30905 */ "PseudoVFMACC_VF32_MF2\0" + /* 30927 */ "PseudoVFNMACC_VF32_MF2\0" + /* 30950 */ "PseudoVFWNMACC_VF32_MF2\0" + /* 30974 */ "PseudoVFWMACC_VF32_MF2\0" + /* 30997 */ "PseudoVFADD_VF32_MF2\0" + /* 31018 */ "PseudoVFMADD_VF32_MF2\0" + /* 31040 */ "PseudoVFNMADD_VF32_MF2\0" + /* 31063 */ "PseudoVFWADD_VF32_MF2\0" + /* 31085 */ "PseudoVMFGE_VF32_MF2\0" + /* 31106 */ "PseudoVMFLE_VF32_MF2\0" + /* 31127 */ "PseudoVMFNE_VF32_MF2\0" + /* 31148 */ "PseudoVFSGNJ_VF32_MF2\0" + /* 31170 */ "PseudoVFMUL_VF32_MF2\0" + /* 31191 */ "PseudoVFWMUL_VF32_MF2\0" + /* 31213 */ "PseudoVFMIN_VF32_MF2\0" + /* 31234 */ "PseudoVFSGNJN_VF32_MF2\0" + /* 31257 */ "PseudoVFSLIDE1DOWN_VF32_MF2\0" + /* 31285 */ "PseudoVFSLIDE1UP_VF32_MF2\0" + /* 31311 */ "PseudoVMFEQ_VF32_MF2\0" + /* 31332 */ "PseudoVMFGT_VF32_MF2\0" + /* 31353 */ "PseudoVMFLT_VF32_MF2\0" + /* 31374 */ "PseudoVFDIV_VF32_MF2\0" + /* 31395 */ "PseudoVFRDIV_VF32_MF2\0" + /* 31417 */ "PseudoVFMAX_VF32_MF2\0" + /* 31438 */ "PseudoVFSGNJX_VF32_MF2\0" + /* 31461 */ "PseudoVFWSUB_WF32_MF2\0" + /* 31483 */ "PseudoVFWADD_WF32_MF2\0" + /* 31505 */ "PseudoVFMV_S_F32_MF2\0" + /* 31526 */ "PseudoVFMV_V_F32_MF2\0" + /* 31547 */ "PseudoVRELOAD2_MF2\0" + /* 31566 */ "PseudoVAMOADDEI32_WD_MF2_MF2\0" + /* 31595 */ "PseudoVAMOANDEI32_WD_MF2_MF2\0" + /* 31624 */ "PseudoVAMOMINEI32_WD_MF2_MF2\0" + /* 31653 */ "PseudoVAMOSWAPEI32_WD_MF2_MF2\0" + /* 31683 */ "PseudoVAMOOREI32_WD_MF2_MF2\0" + /* 31711 */ "PseudoVAMOXOREI32_WD_MF2_MF2\0" + /* 31740 */ "PseudoVAMOMINUEI32_WD_MF2_MF2\0" + /* 31770 */ "PseudoVAMOMAXUEI32_WD_MF2_MF2\0" + /* 31800 */ "PseudoVAMOMAXEI32_WD_MF2_MF2\0" + /* 31829 */ "PseudoVRGATHEREI16_VV_MF2_MF2\0" + /* 31859 */ "PseudoVLOXSEG2EI32_V_MF2_MF2\0" + /* 31888 */ "PseudoVSOXSEG2EI32_V_MF2_MF2\0" + /* 31917 */ "PseudoVLUXSEG2EI32_V_MF2_MF2\0" + /* 31946 */ "PseudoVSUXSEG2EI32_V_MF2_MF2\0" + /* 31975 */ "PseudoVLOXSEG3EI32_V_MF2_MF2\0" + /* 32004 */ "PseudoVSOXSEG3EI32_V_MF2_MF2\0" + /* 32033 */ "PseudoVLUXSEG3EI32_V_MF2_MF2\0" + /* 32062 */ "PseudoVSUXSEG3EI32_V_MF2_MF2\0" + /* 32091 */ "PseudoVLOXSEG4EI32_V_MF2_MF2\0" + /* 32120 */ "PseudoVSOXSEG4EI32_V_MF2_MF2\0" + /* 32149 */ "PseudoVLUXSEG4EI32_V_MF2_MF2\0" + /* 32178 */ "PseudoVSUXSEG4EI32_V_MF2_MF2\0" + /* 32207 */ "PseudoVLOXSEG5EI32_V_MF2_MF2\0" + /* 32236 */ "PseudoVSOXSEG5EI32_V_MF2_MF2\0" + /* 32265 */ "PseudoVLUXSEG5EI32_V_MF2_MF2\0" + /* 32294 */ "PseudoVSUXSEG5EI32_V_MF2_MF2\0" + /* 32323 */ "PseudoVLOXSEG6EI32_V_MF2_MF2\0" + /* 32352 */ "PseudoVSOXSEG6EI32_V_MF2_MF2\0" + /* 32381 */ "PseudoVLUXSEG6EI32_V_MF2_MF2\0" + /* 32410 */ "PseudoVSUXSEG6EI32_V_MF2_MF2\0" + /* 32439 */ "PseudoVLOXSEG7EI32_V_MF2_MF2\0" + /* 32468 */ "PseudoVSOXSEG7EI32_V_MF2_MF2\0" + /* 32497 */ "PseudoVLUXSEG7EI32_V_MF2_MF2\0" + /* 32526 */ "PseudoVSUXSEG7EI32_V_MF2_MF2\0" + /* 32555 */ "PseudoVLOXSEG8EI32_V_MF2_MF2\0" + /* 32584 */ "PseudoVSOXSEG8EI32_V_MF2_MF2\0" + /* 32613 */ "PseudoVLUXSEG8EI32_V_MF2_MF2\0" + /* 32642 */ "PseudoVSUXSEG8EI32_V_MF2_MF2\0" + /* 32671 */ "PseudoVLOXEI32_V_MF2_MF2\0" + /* 32696 */ "PseudoVSOXEI32_V_MF2_MF2\0" + /* 32721 */ "PseudoVLUXEI32_V_MF2_MF2\0" + /* 32746 */ "PseudoVSUXEI32_V_MF2_MF2\0" + /* 32771 */ "PseudoVLOXSEG2EI16_V_MF2_MF2\0" + /* 32800 */ "PseudoVSOXSEG2EI16_V_MF2_MF2\0" + /* 32829 */ "PseudoVLUXSEG2EI16_V_MF2_MF2\0" + /* 32858 */ "PseudoVSUXSEG2EI16_V_MF2_MF2\0" + /* 32887 */ "PseudoVLOXSEG3EI16_V_MF2_MF2\0" + /* 32916 */ "PseudoVSOXSEG3EI16_V_MF2_MF2\0" + /* 32945 */ "PseudoVLUXSEG3EI16_V_MF2_MF2\0" + /* 32974 */ "PseudoVSUXSEG3EI16_V_MF2_MF2\0" + /* 33003 */ "PseudoVLOXSEG4EI16_V_MF2_MF2\0" + /* 33032 */ "PseudoVSOXSEG4EI16_V_MF2_MF2\0" + /* 33061 */ "PseudoVLUXSEG4EI16_V_MF2_MF2\0" + /* 33090 */ "PseudoVSUXSEG4EI16_V_MF2_MF2\0" + /* 33119 */ "PseudoVLOXSEG5EI16_V_MF2_MF2\0" + /* 33148 */ "PseudoVSOXSEG5EI16_V_MF2_MF2\0" + /* 33177 */ "PseudoVLUXSEG5EI16_V_MF2_MF2\0" + /* 33206 */ "PseudoVSUXSEG5EI16_V_MF2_MF2\0" + /* 33235 */ "PseudoVLOXSEG6EI16_V_MF2_MF2\0" + /* 33264 */ "PseudoVSOXSEG6EI16_V_MF2_MF2\0" + /* 33293 */ "PseudoVLUXSEG6EI16_V_MF2_MF2\0" + /* 33322 */ "PseudoVSUXSEG6EI16_V_MF2_MF2\0" + /* 33351 */ "PseudoVLOXSEG7EI16_V_MF2_MF2\0" + /* 33380 */ "PseudoVSOXSEG7EI16_V_MF2_MF2\0" + /* 33409 */ "PseudoVLUXSEG7EI16_V_MF2_MF2\0" + /* 33438 */ "PseudoVSUXSEG7EI16_V_MF2_MF2\0" + /* 33467 */ "PseudoVLOXSEG8EI16_V_MF2_MF2\0" + /* 33496 */ "PseudoVSOXSEG8EI16_V_MF2_MF2\0" + /* 33525 */ "PseudoVLUXSEG8EI16_V_MF2_MF2\0" + /* 33554 */ "PseudoVSUXSEG8EI16_V_MF2_MF2\0" + /* 33583 */ "PseudoVLOXEI16_V_MF2_MF2\0" + /* 33608 */ "PseudoVSOXEI16_V_MF2_MF2\0" + /* 33633 */ "PseudoVLUXEI16_V_MF2_MF2\0" + /* 33658 */ "PseudoVSUXEI16_V_MF2_MF2\0" + /* 33683 */ "PseudoVLOXSEG2EI8_V_MF2_MF2\0" + /* 33711 */ "PseudoVSOXSEG2EI8_V_MF2_MF2\0" + /* 33739 */ "PseudoVLUXSEG2EI8_V_MF2_MF2\0" + /* 33767 */ "PseudoVSUXSEG2EI8_V_MF2_MF2\0" + /* 33795 */ "PseudoVLOXSEG3EI8_V_MF2_MF2\0" + /* 33823 */ "PseudoVSOXSEG3EI8_V_MF2_MF2\0" + /* 33851 */ "PseudoVLUXSEG3EI8_V_MF2_MF2\0" + /* 33879 */ "PseudoVSUXSEG3EI8_V_MF2_MF2\0" + /* 33907 */ "PseudoVLOXSEG4EI8_V_MF2_MF2\0" + /* 33935 */ "PseudoVSOXSEG4EI8_V_MF2_MF2\0" + /* 33963 */ "PseudoVLUXSEG4EI8_V_MF2_MF2\0" + /* 33991 */ "PseudoVSUXSEG4EI8_V_MF2_MF2\0" + /* 34019 */ "PseudoVLOXSEG5EI8_V_MF2_MF2\0" + /* 34047 */ "PseudoVSOXSEG5EI8_V_MF2_MF2\0" + /* 34075 */ "PseudoVLUXSEG5EI8_V_MF2_MF2\0" + /* 34103 */ "PseudoVSUXSEG5EI8_V_MF2_MF2\0" + /* 34131 */ "PseudoVLOXSEG6EI8_V_MF2_MF2\0" + /* 34159 */ "PseudoVSOXSEG6EI8_V_MF2_MF2\0" + /* 34187 */ "PseudoVLUXSEG6EI8_V_MF2_MF2\0" + /* 34215 */ "PseudoVSUXSEG6EI8_V_MF2_MF2\0" + /* 34243 */ "PseudoVLOXSEG7EI8_V_MF2_MF2\0" + /* 34271 */ "PseudoVSOXSEG7EI8_V_MF2_MF2\0" + /* 34299 */ "PseudoVLUXSEG7EI8_V_MF2_MF2\0" + /* 34327 */ "PseudoVSUXSEG7EI8_V_MF2_MF2\0" + /* 34355 */ "PseudoVLOXSEG8EI8_V_MF2_MF2\0" + /* 34383 */ "PseudoVSOXSEG8EI8_V_MF2_MF2\0" + /* 34411 */ "PseudoVLUXSEG8EI8_V_MF2_MF2\0" + /* 34439 */ "PseudoVSUXSEG8EI8_V_MF2_MF2\0" + /* 34467 */ "PseudoVLOXEI8_V_MF2_MF2\0" + /* 34491 */ "PseudoVSOXEI8_V_MF2_MF2\0" + /* 34515 */ "PseudoVLUXEI8_V_MF2_MF2\0" + /* 34539 */ "PseudoVSUXEI8_V_MF2_MF2\0" + /* 34563 */ "PseudoVSEXT_VF2_MF2\0" + /* 34583 */ "PseudoVZEXT_VF2_MF2\0" + /* 34603 */ "PseudoVSPILL2_MF2\0" + /* 34621 */ "PseudoVAMOADDEI16_WD_M2_MF2\0" + /* 34649 */ "PseudoVAMOANDEI16_WD_M2_MF2\0" + /* 34677 */ "PseudoVAMOMINEI16_WD_M2_MF2\0" + /* 34705 */ "PseudoVAMOSWAPEI16_WD_M2_MF2\0" + /* 34734 */ "PseudoVAMOOREI16_WD_M2_MF2\0" + /* 34761 */ "PseudoVAMOXOREI16_WD_M2_MF2\0" + /* 34789 */ "PseudoVAMOMINUEI16_WD_M2_MF2\0" + /* 34818 */ "PseudoVAMOMAXUEI16_WD_M2_MF2\0" + /* 34847 */ "PseudoVAMOMAXEI16_WD_M2_MF2\0" + /* 34875 */ "PseudoVAMOADDEI8_WD_M2_MF2\0" + /* 34902 */ "PseudoVAMOANDEI8_WD_M2_MF2\0" + /* 34929 */ "PseudoVAMOMINEI8_WD_M2_MF2\0" + /* 34956 */ "PseudoVAMOSWAPEI8_WD_M2_MF2\0" + /* 34984 */ "PseudoVAMOOREI8_WD_M2_MF2\0" + /* 35010 */ "PseudoVAMOXOREI8_WD_M2_MF2\0" + /* 35037 */ "PseudoVAMOMINUEI8_WD_M2_MF2\0" + /* 35065 */ "PseudoVAMOMAXUEI8_WD_M2_MF2\0" + /* 35093 */ "PseudoVAMOMAXEI8_WD_M2_MF2\0" + /* 35120 */ "PseudoVRGATHEREI16_VV_M2_MF2\0" + /* 35149 */ "PseudoVLOXSEG2EI32_V_M2_MF2\0" + /* 35177 */ "PseudoVSOXSEG2EI32_V_M2_MF2\0" + /* 35205 */ "PseudoVLUXSEG2EI32_V_M2_MF2\0" + /* 35233 */ "PseudoVSUXSEG2EI32_V_M2_MF2\0" + /* 35261 */ "PseudoVLOXSEG3EI32_V_M2_MF2\0" + /* 35289 */ "PseudoVSOXSEG3EI32_V_M2_MF2\0" + /* 35317 */ "PseudoVLUXSEG3EI32_V_M2_MF2\0" + /* 35345 */ "PseudoVSUXSEG3EI32_V_M2_MF2\0" + /* 35373 */ "PseudoVLOXSEG4EI32_V_M2_MF2\0" + /* 35401 */ "PseudoVSOXSEG4EI32_V_M2_MF2\0" + /* 35429 */ "PseudoVLUXSEG4EI32_V_M2_MF2\0" + /* 35457 */ "PseudoVSUXSEG4EI32_V_M2_MF2\0" + /* 35485 */ "PseudoVLOXSEG5EI32_V_M2_MF2\0" + /* 35513 */ "PseudoVSOXSEG5EI32_V_M2_MF2\0" + /* 35541 */ "PseudoVLUXSEG5EI32_V_M2_MF2\0" + /* 35569 */ "PseudoVSUXSEG5EI32_V_M2_MF2\0" + /* 35597 */ "PseudoVLOXSEG6EI32_V_M2_MF2\0" + /* 35625 */ "PseudoVSOXSEG6EI32_V_M2_MF2\0" + /* 35653 */ "PseudoVLUXSEG6EI32_V_M2_MF2\0" + /* 35681 */ "PseudoVSUXSEG6EI32_V_M2_MF2\0" + /* 35709 */ "PseudoVLOXSEG7EI32_V_M2_MF2\0" + /* 35737 */ "PseudoVSOXSEG7EI32_V_M2_MF2\0" + /* 35765 */ "PseudoVLUXSEG7EI32_V_M2_MF2\0" + /* 35793 */ "PseudoVSUXSEG7EI32_V_M2_MF2\0" + /* 35821 */ "PseudoVLOXSEG8EI32_V_M2_MF2\0" + /* 35849 */ "PseudoVSOXSEG8EI32_V_M2_MF2\0" + /* 35877 */ "PseudoVLUXSEG8EI32_V_M2_MF2\0" + /* 35905 */ "PseudoVSUXSEG8EI32_V_M2_MF2\0" + /* 35933 */ "PseudoVLOXEI32_V_M2_MF2\0" + /* 35957 */ "PseudoVSOXEI32_V_M2_MF2\0" + /* 35981 */ "PseudoVLUXEI32_V_M2_MF2\0" + /* 36005 */ "PseudoVSUXEI32_V_M2_MF2\0" + /* 36029 */ "PseudoVLOXSEG2EI64_V_M2_MF2\0" + /* 36057 */ "PseudoVSOXSEG2EI64_V_M2_MF2\0" + /* 36085 */ "PseudoVLUXSEG2EI64_V_M2_MF2\0" + /* 36113 */ "PseudoVSUXSEG2EI64_V_M2_MF2\0" + /* 36141 */ "PseudoVLOXSEG3EI64_V_M2_MF2\0" + /* 36169 */ "PseudoVSOXSEG3EI64_V_M2_MF2\0" + /* 36197 */ "PseudoVLUXSEG3EI64_V_M2_MF2\0" + /* 36225 */ "PseudoVSUXSEG3EI64_V_M2_MF2\0" + /* 36253 */ "PseudoVLOXSEG4EI64_V_M2_MF2\0" + /* 36281 */ "PseudoVSOXSEG4EI64_V_M2_MF2\0" + /* 36309 */ "PseudoVLUXSEG4EI64_V_M2_MF2\0" + /* 36337 */ "PseudoVSUXSEG4EI64_V_M2_MF2\0" + /* 36365 */ "PseudoVLOXSEG5EI64_V_M2_MF2\0" + /* 36393 */ "PseudoVSOXSEG5EI64_V_M2_MF2\0" + /* 36421 */ "PseudoVLUXSEG5EI64_V_M2_MF2\0" + /* 36449 */ "PseudoVSUXSEG5EI64_V_M2_MF2\0" + /* 36477 */ "PseudoVLOXSEG6EI64_V_M2_MF2\0" + /* 36505 */ "PseudoVSOXSEG6EI64_V_M2_MF2\0" + /* 36533 */ "PseudoVLUXSEG6EI64_V_M2_MF2\0" + /* 36561 */ "PseudoVSUXSEG6EI64_V_M2_MF2\0" + /* 36589 */ "PseudoVLOXSEG7EI64_V_M2_MF2\0" + /* 36617 */ "PseudoVSOXSEG7EI64_V_M2_MF2\0" + /* 36645 */ "PseudoVLUXSEG7EI64_V_M2_MF2\0" + /* 36673 */ "PseudoVSUXSEG7EI64_V_M2_MF2\0" + /* 36701 */ "PseudoVLOXSEG8EI64_V_M2_MF2\0" + /* 36729 */ "PseudoVSOXSEG8EI64_V_M2_MF2\0" + /* 36757 */ "PseudoVLUXSEG8EI64_V_M2_MF2\0" + /* 36785 */ "PseudoVSUXSEG8EI64_V_M2_MF2\0" + /* 36813 */ "PseudoVLOXEI64_V_M2_MF2\0" + /* 36837 */ "PseudoVSOXEI64_V_M2_MF2\0" + /* 36861 */ "PseudoVLUXEI64_V_M2_MF2\0" + /* 36885 */ "PseudoVSUXEI64_V_M2_MF2\0" + /* 36909 */ "PseudoVRELOAD3_MF2\0" + /* 36928 */ "PseudoVSPILL3_MF2\0" + /* 36946 */ "PseudoVFSUB_VF64_MF2\0" + /* 36967 */ "PseudoVFMSUB_VF64_MF2\0" + /* 36989 */ "PseudoVFNMSUB_VF64_MF2\0" + /* 37012 */ "PseudoVFRSUB_VF64_MF2\0" + /* 37034 */ "PseudoVFMSAC_VF64_MF2\0" + /* 37056 */ "PseudoVFNMSAC_VF64_MF2\0" + /* 37079 */ "PseudoVFMACC_VF64_MF2\0" + /* 37101 */ "PseudoVFNMACC_VF64_MF2\0" + /* 37124 */ "PseudoVFADD_VF64_MF2\0" + /* 37145 */ "PseudoVFMADD_VF64_MF2\0" + /* 37167 */ "PseudoVFNMADD_VF64_MF2\0" + /* 37190 */ "PseudoVMFGE_VF64_MF2\0" + /* 37211 */ "PseudoVMFLE_VF64_MF2\0" + /* 37232 */ "PseudoVMFNE_VF64_MF2\0" + /* 37253 */ "PseudoVFSGNJ_VF64_MF2\0" + /* 37275 */ "PseudoVFMUL_VF64_MF2\0" + /* 37296 */ "PseudoVFMIN_VF64_MF2\0" + /* 37317 */ "PseudoVFSGNJN_VF64_MF2\0" + /* 37340 */ "PseudoVFSLIDE1DOWN_VF64_MF2\0" + /* 37368 */ "PseudoVFSLIDE1UP_VF64_MF2\0" + /* 37394 */ "PseudoVMFEQ_VF64_MF2\0" + /* 37415 */ "PseudoVMFGT_VF64_MF2\0" + /* 37436 */ "PseudoVMFLT_VF64_MF2\0" + /* 37457 */ "PseudoVFDIV_VF64_MF2\0" + /* 37478 */ "PseudoVFRDIV_VF64_MF2\0" + /* 37500 */ "PseudoVFMAX_VF64_MF2\0" + /* 37521 */ "PseudoVFSGNJX_VF64_MF2\0" + /* 37544 */ "PseudoVFMV_S_F64_MF2\0" + /* 37565 */ "PseudoVFMV_V_F64_MF2\0" + /* 37586 */ "PseudoVRELOAD4_MF2\0" + /* 37605 */ "PseudoVRGATHEREI16_VV_MF4_MF2\0" + /* 37635 */ "PseudoVLOXSEG2EI16_V_MF4_MF2\0" + /* 37664 */ "PseudoVSOXSEG2EI16_V_MF4_MF2\0" + /* 37693 */ "PseudoVLUXSEG2EI16_V_MF4_MF2\0" + /* 37722 */ "PseudoVSUXSEG2EI16_V_MF4_MF2\0" + /* 37751 */ "PseudoVLOXSEG3EI16_V_MF4_MF2\0" + /* 37780 */ "PseudoVSOXSEG3EI16_V_MF4_MF2\0" + /* 37809 */ "PseudoVLUXSEG3EI16_V_MF4_MF2\0" + /* 37838 */ "PseudoVSUXSEG3EI16_V_MF4_MF2\0" + /* 37867 */ "PseudoVLOXSEG4EI16_V_MF4_MF2\0" + /* 37896 */ "PseudoVSOXSEG4EI16_V_MF4_MF2\0" + /* 37925 */ "PseudoVLUXSEG4EI16_V_MF4_MF2\0" + /* 37954 */ "PseudoVSUXSEG4EI16_V_MF4_MF2\0" + /* 37983 */ "PseudoVLOXSEG5EI16_V_MF4_MF2\0" + /* 38012 */ "PseudoVSOXSEG5EI16_V_MF4_MF2\0" + /* 38041 */ "PseudoVLUXSEG5EI16_V_MF4_MF2\0" + /* 38070 */ "PseudoVSUXSEG5EI16_V_MF4_MF2\0" + /* 38099 */ "PseudoVLOXSEG6EI16_V_MF4_MF2\0" + /* 38128 */ "PseudoVSOXSEG6EI16_V_MF4_MF2\0" + /* 38157 */ "PseudoVLUXSEG6EI16_V_MF4_MF2\0" + /* 38186 */ "PseudoVSUXSEG6EI16_V_MF4_MF2\0" + /* 38215 */ "PseudoVLOXSEG7EI16_V_MF4_MF2\0" + /* 38244 */ "PseudoVSOXSEG7EI16_V_MF4_MF2\0" + /* 38273 */ "PseudoVLUXSEG7EI16_V_MF4_MF2\0" + /* 38302 */ "PseudoVSUXSEG7EI16_V_MF4_MF2\0" + /* 38331 */ "PseudoVLOXSEG8EI16_V_MF4_MF2\0" + /* 38360 */ "PseudoVSOXSEG8EI16_V_MF4_MF2\0" + /* 38389 */ "PseudoVLUXSEG8EI16_V_MF4_MF2\0" + /* 38418 */ "PseudoVSUXSEG8EI16_V_MF4_MF2\0" + /* 38447 */ "PseudoVLOXEI16_V_MF4_MF2\0" + /* 38472 */ "PseudoVSOXEI16_V_MF4_MF2\0" + /* 38497 */ "PseudoVLUXEI16_V_MF4_MF2\0" + /* 38522 */ "PseudoVSUXEI16_V_MF4_MF2\0" + /* 38547 */ "PseudoVLOXSEG2EI8_V_MF4_MF2\0" + /* 38575 */ "PseudoVSOXSEG2EI8_V_MF4_MF2\0" + /* 38603 */ "PseudoVLUXSEG2EI8_V_MF4_MF2\0" + /* 38631 */ "PseudoVSUXSEG2EI8_V_MF4_MF2\0" + /* 38659 */ "PseudoVLOXSEG3EI8_V_MF4_MF2\0" + /* 38687 */ "PseudoVSOXSEG3EI8_V_MF4_MF2\0" + /* 38715 */ "PseudoVLUXSEG3EI8_V_MF4_MF2\0" + /* 38743 */ "PseudoVSUXSEG3EI8_V_MF4_MF2\0" + /* 38771 */ "PseudoVLOXSEG4EI8_V_MF4_MF2\0" + /* 38799 */ "PseudoVSOXSEG4EI8_V_MF4_MF2\0" + /* 38827 */ "PseudoVLUXSEG4EI8_V_MF4_MF2\0" + /* 38855 */ "PseudoVSUXSEG4EI8_V_MF4_MF2\0" + /* 38883 */ "PseudoVLOXSEG5EI8_V_MF4_MF2\0" + /* 38911 */ "PseudoVSOXSEG5EI8_V_MF4_MF2\0" + /* 38939 */ "PseudoVLUXSEG5EI8_V_MF4_MF2\0" + /* 38967 */ "PseudoVSUXSEG5EI8_V_MF4_MF2\0" + /* 38995 */ "PseudoVLOXSEG6EI8_V_MF4_MF2\0" + /* 39023 */ "PseudoVSOXSEG6EI8_V_MF4_MF2\0" + /* 39051 */ "PseudoVLUXSEG6EI8_V_MF4_MF2\0" + /* 39079 */ "PseudoVSUXSEG6EI8_V_MF4_MF2\0" + /* 39107 */ "PseudoVLOXSEG7EI8_V_MF4_MF2\0" + /* 39135 */ "PseudoVSOXSEG7EI8_V_MF4_MF2\0" + /* 39163 */ "PseudoVLUXSEG7EI8_V_MF4_MF2\0" + /* 39191 */ "PseudoVSUXSEG7EI8_V_MF4_MF2\0" + /* 39219 */ "PseudoVLOXSEG8EI8_V_MF4_MF2\0" + /* 39247 */ "PseudoVSOXSEG8EI8_V_MF4_MF2\0" + /* 39275 */ "PseudoVLUXSEG8EI8_V_MF4_MF2\0" + /* 39303 */ "PseudoVSUXSEG8EI8_V_MF4_MF2\0" + /* 39331 */ "PseudoVLOXEI8_V_MF4_MF2\0" + /* 39355 */ "PseudoVSOXEI8_V_MF4_MF2\0" + /* 39379 */ "PseudoVLUXEI8_V_MF4_MF2\0" + /* 39403 */ "PseudoVSUXEI8_V_MF4_MF2\0" + /* 39427 */ "PseudoVSEXT_VF4_MF2\0" + /* 39447 */ "PseudoVZEXT_VF4_MF2\0" + /* 39467 */ "PseudoVSPILL4_MF2\0" + /* 39485 */ "PseudoVAMOADDEI8_WD_M4_MF2\0" + /* 39512 */ "PseudoVAMOANDEI8_WD_M4_MF2\0" + /* 39539 */ "PseudoVAMOMINEI8_WD_M4_MF2\0" + /* 39566 */ "PseudoVAMOSWAPEI8_WD_M4_MF2\0" + /* 39594 */ "PseudoVAMOOREI8_WD_M4_MF2\0" + /* 39620 */ "PseudoVAMOXOREI8_WD_M4_MF2\0" + /* 39647 */ "PseudoVAMOMINUEI8_WD_M4_MF2\0" + /* 39675 */ "PseudoVAMOMAXUEI8_WD_M4_MF2\0" + /* 39703 */ "PseudoVAMOMAXEI8_WD_M4_MF2\0" + /* 39730 */ "PseudoVLOXSEG2EI64_V_M4_MF2\0" + /* 39758 */ "PseudoVSOXSEG2EI64_V_M4_MF2\0" + /* 39786 */ "PseudoVLUXSEG2EI64_V_M4_MF2\0" + /* 39814 */ "PseudoVSUXSEG2EI64_V_M4_MF2\0" + /* 39842 */ "PseudoVLOXSEG3EI64_V_M4_MF2\0" + /* 39870 */ "PseudoVSOXSEG3EI64_V_M4_MF2\0" + /* 39898 */ "PseudoVLUXSEG3EI64_V_M4_MF2\0" + /* 39926 */ "PseudoVSUXSEG3EI64_V_M4_MF2\0" + /* 39954 */ "PseudoVLOXSEG4EI64_V_M4_MF2\0" + /* 39982 */ "PseudoVSOXSEG4EI64_V_M4_MF2\0" + /* 40010 */ "PseudoVLUXSEG4EI64_V_M4_MF2\0" + /* 40038 */ "PseudoVSUXSEG4EI64_V_M4_MF2\0" + /* 40066 */ "PseudoVLOXSEG5EI64_V_M4_MF2\0" + /* 40094 */ "PseudoVSOXSEG5EI64_V_M4_MF2\0" + /* 40122 */ "PseudoVLUXSEG5EI64_V_M4_MF2\0" + /* 40150 */ "PseudoVSUXSEG5EI64_V_M4_MF2\0" + /* 40178 */ "PseudoVLOXSEG6EI64_V_M4_MF2\0" + /* 40206 */ "PseudoVSOXSEG6EI64_V_M4_MF2\0" + /* 40234 */ "PseudoVLUXSEG6EI64_V_M4_MF2\0" + /* 40262 */ "PseudoVSUXSEG6EI64_V_M4_MF2\0" + /* 40290 */ "PseudoVLOXSEG7EI64_V_M4_MF2\0" + /* 40318 */ "PseudoVSOXSEG7EI64_V_M4_MF2\0" + /* 40346 */ "PseudoVLUXSEG7EI64_V_M4_MF2\0" + /* 40374 */ "PseudoVSUXSEG7EI64_V_M4_MF2\0" + /* 40402 */ "PseudoVLOXSEG8EI64_V_M4_MF2\0" + /* 40430 */ "PseudoVSOXSEG8EI64_V_M4_MF2\0" + /* 40458 */ "PseudoVLUXSEG8EI64_V_M4_MF2\0" + /* 40486 */ "PseudoVSUXSEG8EI64_V_M4_MF2\0" + /* 40514 */ "PseudoVLOXEI64_V_M4_MF2\0" + /* 40538 */ "PseudoVSOXEI64_V_M4_MF2\0" + /* 40562 */ "PseudoVLUXEI64_V_M4_MF2\0" + /* 40586 */ "PseudoVSUXEI64_V_M4_MF2\0" + /* 40610 */ "PseudoVRELOAD5_MF2\0" + /* 40629 */ "PseudoVSPILL5_MF2\0" + /* 40647 */ "PseudoVFSUB_VF16_MF2\0" + /* 40668 */ "PseudoVFMSUB_VF16_MF2\0" + /* 40690 */ "PseudoVFNMSUB_VF16_MF2\0" + /* 40713 */ "PseudoVFRSUB_VF16_MF2\0" + /* 40735 */ "PseudoVFWSUB_VF16_MF2\0" + /* 40757 */ "PseudoVFMSAC_VF16_MF2\0" + /* 40779 */ "PseudoVFNMSAC_VF16_MF2\0" + /* 40802 */ "PseudoVFWNMSAC_VF16_MF2\0" + /* 40826 */ "PseudoVFWMSAC_VF16_MF2\0" + /* 40849 */ "PseudoVFMACC_VF16_MF2\0" + /* 40871 */ "PseudoVFNMACC_VF16_MF2\0" + /* 40894 */ "PseudoVFWNMACC_VF16_MF2\0" + /* 40918 */ "PseudoVFWMACC_VF16_MF2\0" + /* 40941 */ "PseudoVFADD_VF16_MF2\0" + /* 40962 */ "PseudoVFMADD_VF16_MF2\0" + /* 40984 */ "PseudoVFNMADD_VF16_MF2\0" + /* 41007 */ "PseudoVFWADD_VF16_MF2\0" + /* 41029 */ "PseudoVMFGE_VF16_MF2\0" + /* 41050 */ "PseudoVMFLE_VF16_MF2\0" + /* 41071 */ "PseudoVMFNE_VF16_MF2\0" + /* 41092 */ "PseudoVFSGNJ_VF16_MF2\0" + /* 41114 */ "PseudoVFMUL_VF16_MF2\0" + /* 41135 */ "PseudoVFWMUL_VF16_MF2\0" + /* 41157 */ "PseudoVFMIN_VF16_MF2\0" + /* 41178 */ "PseudoVFSGNJN_VF16_MF2\0" + /* 41201 */ "PseudoVFSLIDE1DOWN_VF16_MF2\0" + /* 41229 */ "PseudoVFSLIDE1UP_VF16_MF2\0" + /* 41255 */ "PseudoVMFEQ_VF16_MF2\0" + /* 41276 */ "PseudoVMFGT_VF16_MF2\0" + /* 41297 */ "PseudoVMFLT_VF16_MF2\0" + /* 41318 */ "PseudoVFDIV_VF16_MF2\0" + /* 41339 */ "PseudoVFRDIV_VF16_MF2\0" + /* 41361 */ "PseudoVFMAX_VF16_MF2\0" + /* 41382 */ "PseudoVFSGNJX_VF16_MF2\0" + /* 41405 */ "PseudoVFWSUB_WF16_MF2\0" + /* 41427 */ "PseudoVFWADD_WF16_MF2\0" + /* 41449 */ "PseudoVFMV_S_F16_MF2\0" + /* 41470 */ "PseudoVFMV_V_F16_MF2\0" + /* 41491 */ "PseudoVRELOAD6_MF2\0" + /* 41510 */ "PseudoVSPILL6_MF2\0" + /* 41528 */ "PseudoVRELOAD7_MF2\0" + /* 41547 */ "PseudoVSPILL7_MF2\0" + /* 41565 */ "PseudoVRELOAD8_MF2\0" + /* 41584 */ "PseudoVLOXSEG2EI8_V_MF8_MF2\0" + /* 41612 */ "PseudoVSOXSEG2EI8_V_MF8_MF2\0" + /* 41640 */ "PseudoVLUXSEG2EI8_V_MF8_MF2\0" + /* 41668 */ "PseudoVSUXSEG2EI8_V_MF8_MF2\0" + /* 41696 */ "PseudoVLOXSEG3EI8_V_MF8_MF2\0" + /* 41724 */ "PseudoVSOXSEG3EI8_V_MF8_MF2\0" + /* 41752 */ "PseudoVLUXSEG3EI8_V_MF8_MF2\0" + /* 41780 */ "PseudoVSUXSEG3EI8_V_MF8_MF2\0" + /* 41808 */ "PseudoVLOXSEG4EI8_V_MF8_MF2\0" + /* 41836 */ "PseudoVSOXSEG4EI8_V_MF8_MF2\0" + /* 41864 */ "PseudoVLUXSEG4EI8_V_MF8_MF2\0" + /* 41892 */ "PseudoVSUXSEG4EI8_V_MF8_MF2\0" + /* 41920 */ "PseudoVLOXSEG5EI8_V_MF8_MF2\0" + /* 41948 */ "PseudoVSOXSEG5EI8_V_MF8_MF2\0" + /* 41976 */ "PseudoVLUXSEG5EI8_V_MF8_MF2\0" + /* 42004 */ "PseudoVSUXSEG5EI8_V_MF8_MF2\0" + /* 42032 */ "PseudoVLOXSEG6EI8_V_MF8_MF2\0" + /* 42060 */ "PseudoVSOXSEG6EI8_V_MF8_MF2\0" + /* 42088 */ "PseudoVLUXSEG6EI8_V_MF8_MF2\0" + /* 42116 */ "PseudoVSUXSEG6EI8_V_MF8_MF2\0" + /* 42144 */ "PseudoVLOXSEG7EI8_V_MF8_MF2\0" + /* 42172 */ "PseudoVSOXSEG7EI8_V_MF8_MF2\0" + /* 42200 */ "PseudoVLUXSEG7EI8_V_MF8_MF2\0" + /* 42228 */ "PseudoVSUXSEG7EI8_V_MF8_MF2\0" + /* 42256 */ "PseudoVLOXSEG8EI8_V_MF8_MF2\0" + /* 42284 */ "PseudoVSOXSEG8EI8_V_MF8_MF2\0" + /* 42312 */ "PseudoVLUXSEG8EI8_V_MF8_MF2\0" + /* 42340 */ "PseudoVSUXSEG8EI8_V_MF8_MF2\0" + /* 42368 */ "PseudoVLOXEI8_V_MF8_MF2\0" + /* 42392 */ "PseudoVSOXEI8_V_MF8_MF2\0" + /* 42416 */ "PseudoVLUXEI8_V_MF8_MF2\0" + /* 42440 */ "PseudoVSUXEI8_V_MF8_MF2\0" + /* 42464 */ "PseudoVSPILL8_MF2\0" + /* 42482 */ "PseudoVSSRA_VI_MF2\0" + /* 42501 */ "PseudoVSRA_VI_MF2\0" + /* 42519 */ "PseudoVRSUB_VI_MF2\0" + /* 42538 */ "PseudoVMADC_VI_MF2\0" + /* 42557 */ "PseudoVSADD_VI_MF2\0" + /* 42576 */ "PseudoVADD_VI_MF2\0" + /* 42594 */ "PseudoVAND_VI_MF2\0" + /* 42612 */ "PseudoVMSLE_VI_MF2\0" + /* 42631 */ "PseudoVMSNE_VI_MF2\0" + /* 42650 */ "PseudoVSLL_VI_MF2\0" + /* 42668 */ "PseudoVSSRL_VI_MF2\0" + /* 42687 */ "PseudoVSRL_VI_MF2\0" + /* 42705 */ "PseudoVSLIDEDOWN_VI_MF2\0" + /* 42729 */ "PseudoVSLIDEUP_VI_MF2\0" + /* 42751 */ "PseudoVMSEQ_VI_MF2\0" + /* 42770 */ "PseudoVRGATHER_VI_MF2\0" + /* 42792 */ "PseudoVOR_VI_MF2\0" + /* 42809 */ "PseudoVXOR_VI_MF2\0" + /* 42827 */ "PseudoVMSGT_VI_MF2\0" + /* 42846 */ "PseudoVSADDU_VI_MF2\0" + /* 42866 */ "PseudoVMSLEU_VI_MF2\0" + /* 42886 */ "PseudoVMSGTU_VI_MF2\0" + /* 42906 */ "PseudoVNSRA_WI_MF2\0" + /* 42925 */ "PseudoVNSRL_WI_MF2\0" + /* 42944 */ "PseudoVNCLIP_WI_MF2\0" + /* 42964 */ "PseudoVNCLIPU_WI_MF2\0" + /* 42985 */ "PseudoVMV_V_I_MF2\0" + /* 43003 */ "PseudoVFMERGE_VF32M_MF2\0" + /* 43027 */ "PseudoVFMERGE_VF64M_MF2\0" + /* 43051 */ "PseudoVFMERGE_VF16M_MF2\0" + /* 43075 */ "PseudoVMADC_VIM_MF2\0" + /* 43095 */ "PseudoVADC_VIM_MF2\0" + /* 43114 */ "PseudoVMERGE_VIM_MF2\0" + /* 43135 */ "PseudoVMAND_MM_MF2\0" + /* 43154 */ "PseudoVMNAND_MM_MF2\0" + /* 43174 */ "PseudoVMANDN_MM_MF2\0" + /* 43194 */ "PseudoVMORN_MM_MF2\0" + /* 43213 */ "PseudoVMOR_MM_MF2\0" + /* 43231 */ "PseudoVMNOR_MM_MF2\0" + /* 43250 */ "PseudoVMXNOR_MM_MF2\0" + /* 43270 */ "PseudoVMXOR_MM_MF2\0" + /* 43289 */ "PseudoVMSBC_VVM_MF2\0" + /* 43309 */ "PseudoVSBC_VVM_MF2\0" + /* 43328 */ "PseudoVMADC_VVM_MF2\0" + /* 43348 */ "PseudoVADC_VVM_MF2\0" + /* 43367 */ "PseudoVMERGE_VVM_MF2\0" + /* 43388 */ "PseudoVCOMPRESS_VM_MF2\0" + /* 43411 */ "PseudoVMSBC_VXM_MF2\0" + /* 43431 */ "PseudoVSBC_VXM_MF2\0" + /* 43450 */ "PseudoVMADC_VXM_MF2\0" + /* 43470 */ "PseudoVADC_VXM_MF2\0" + /* 43489 */ "PseudoVMERGE_VXM_MF2\0" + /* 43510 */ "PseudoVIOTA_M_MF2\0" + /* 43528 */ "PseudoVREDAND_VS_MF2\0" + /* 43549 */ "PseudoVREDSUM_VS_MF2\0" + /* 43570 */ "PseudoVWREDSUM_VS_MF2\0" + /* 43592 */ "PseudoVFREDOSUM_VS_MF2\0" + /* 43615 */ "PseudoVFWREDOSUM_VS_MF2\0" + /* 43639 */ "PseudoVFREDUSUM_VS_MF2\0" + /* 43662 */ "PseudoVFWREDUSUM_VS_MF2\0" + /* 43686 */ "PseudoVFREDMIN_VS_MF2\0" + /* 43708 */ "PseudoVREDMIN_VS_MF2\0" + /* 43729 */ "PseudoVREDOR_VS_MF2\0" + /* 43749 */ "PseudoVREDXOR_VS_MF2\0" + /* 43770 */ "PseudoVWREDSUMU_VS_MF2\0" + /* 43793 */ "PseudoVREDMINU_VS_MF2\0" + /* 43815 */ "PseudoVREDMAXU_VS_MF2\0" + /* 43837 */ "PseudoVFREDMAX_VS_MF2\0" + /* 43859 */ "PseudoVREDMAX_VS_MF2\0" + /* 43880 */ "PseudoVFMV_F32_S_MF2\0" + /* 43901 */ "PseudoVFMV_F64_S_MF2\0" + /* 43922 */ "PseudoVFMV_F16_S_MF2\0" + /* 43943 */ "PseudoVMV_X_S_MF2\0" + /* 43961 */ "PseudoVSSRA_VV_MF2\0" + /* 43980 */ "PseudoVSRA_VV_MF2\0" + /* 43998 */ "PseudoVASUB_VV_MF2\0" + /* 44017 */ "PseudoVFSUB_VV_MF2\0" + /* 44036 */ "PseudoVFMSUB_VV_MF2\0" + /* 44056 */ "PseudoVFNMSUB_VV_MF2\0" + /* 44077 */ "PseudoVNMSUB_VV_MF2\0" + /* 44097 */ "PseudoVSSUB_VV_MF2\0" + /* 44116 */ "PseudoVSUB_VV_MF2\0" + /* 44134 */ "PseudoVFWSUB_VV_MF2\0" + /* 44154 */ "PseudoVWSUB_VV_MF2\0" + /* 44173 */ "PseudoVFMSAC_VV_MF2\0" + /* 44193 */ "PseudoVFNMSAC_VV_MF2\0" + /* 44214 */ "PseudoVNMSAC_VV_MF2\0" + /* 44234 */ "PseudoVFWNMSAC_VV_MF2\0" + /* 44256 */ "PseudoVFWMSAC_VV_MF2\0" + /* 44277 */ "PseudoVMSBC_VV_MF2\0" + /* 44296 */ "PseudoVFMACC_VV_MF2\0" + /* 44316 */ "PseudoVFNMACC_VV_MF2\0" + /* 44337 */ "PseudoVFWNMACC_VV_MF2\0" + /* 44359 */ "PseudoVMACC_VV_MF2\0" + /* 44378 */ "PseudoVFWMACC_VV_MF2\0" + /* 44399 */ "PseudoVWMACC_VV_MF2\0" + /* 44419 */ "PseudoVMADC_VV_MF2\0" + /* 44438 */ "PseudoVAADD_VV_MF2\0" + /* 44457 */ "PseudoVFADD_VV_MF2\0" + /* 44476 */ "PseudoVFMADD_VV_MF2\0" + /* 44496 */ "PseudoVFNMADD_VV_MF2\0" + /* 44517 */ "PseudoVMADD_VV_MF2\0" + /* 44536 */ "PseudoVSADD_VV_MF2\0" + /* 44555 */ "PseudoVADD_VV_MF2\0" + /* 44573 */ "PseudoVFWADD_VV_MF2\0" + /* 44593 */ "PseudoVWADD_VV_MF2\0" + /* 44612 */ "PseudoVAND_VV_MF2\0" + /* 44630 */ "PseudoVMFLE_VV_MF2\0" + /* 44649 */ "PseudoVMSLE_VV_MF2\0" + /* 44668 */ "PseudoVMFNE_VV_MF2\0" + /* 44687 */ "PseudoVMSNE_VV_MF2\0" + /* 44706 */ "PseudoVMULH_VV_MF2\0" + /* 44725 */ "PseudoVFSGNJ_VV_MF2\0" + /* 44745 */ "PseudoVSLL_VV_MF2\0" + /* 44763 */ "PseudoVSSRL_VV_MF2\0" + /* 44782 */ "PseudoVSRL_VV_MF2\0" + /* 44800 */ "PseudoVFMUL_VV_MF2\0" + /* 44819 */ "PseudoVSMUL_VV_MF2\0" + /* 44838 */ "PseudoVMUL_VV_MF2\0" + /* 44856 */ "PseudoVFWMUL_VV_MF2\0" + /* 44876 */ "PseudoVWMUL_VV_MF2\0" + /* 44895 */ "PseudoVREM_VV_MF2\0" + /* 44913 */ "PseudoVFMIN_VV_MF2\0" + /* 44932 */ "PseudoVMIN_VV_MF2\0" + /* 44950 */ "PseudoVFSGNJN_VV_MF2\0" + /* 44971 */ "PseudoVMFEQ_VV_MF2\0" + /* 44990 */ "PseudoVMSEQ_VV_MF2\0" + /* 45009 */ "PseudoVRGATHER_VV_MF2\0" + /* 45031 */ "PseudoVOR_VV_MF2\0" + /* 45048 */ "PseudoVXOR_VV_MF2\0" + /* 45066 */ "PseudoVMFLT_VV_MF2\0" + /* 45085 */ "PseudoVMSLT_VV_MF2\0" + /* 45104 */ "PseudoVASUBU_VV_MF2\0" + /* 45124 */ "PseudoVSSUBU_VV_MF2\0" + /* 45144 */ "PseudoVWSUBU_VV_MF2\0" + /* 45164 */ "PseudoVWMACCU_VV_MF2\0" + /* 45185 */ "PseudoVAADDU_VV_MF2\0" + /* 45205 */ "PseudoVSADDU_VV_MF2\0" + /* 45225 */ "PseudoVWADDU_VV_MF2\0" + /* 45245 */ "PseudoVMSLEU_VV_MF2\0" + /* 45265 */ "PseudoVMULHU_VV_MF2\0" + /* 45285 */ "PseudoVWMULU_VV_MF2\0" + /* 45305 */ "PseudoVREMU_VV_MF2\0" + /* 45324 */ "PseudoVMINU_VV_MF2\0" + /* 45343 */ "PseudoVWMACCSU_VV_MF2\0" + /* 45365 */ "PseudoVMULHSU_VV_MF2\0" + /* 45386 */ "PseudoVWMULSU_VV_MF2\0" + /* 45407 */ "PseudoVMSLTU_VV_MF2\0" + /* 45427 */ "PseudoVDIVU_VV_MF2\0" + /* 45446 */ "PseudoVMAXU_VV_MF2\0" + /* 45465 */ "PseudoVFDIV_VV_MF2\0" + /* 45484 */ "PseudoVDIV_VV_MF2\0" + /* 45502 */ "PseudoVFMAX_VV_MF2\0" + /* 45521 */ "PseudoVMAX_VV_MF2\0" + /* 45539 */ "PseudoVFSGNJX_VV_MF2\0" + /* 45560 */ "PseudoVNSRA_WV_MF2\0" + /* 45579 */ "PseudoVFWSUB_WV_MF2\0" + /* 45599 */ "PseudoVWSUB_WV_MF2\0" + /* 45618 */ "PseudoVFWADD_WV_MF2\0" + /* 45638 */ "PseudoVWADD_WV_MF2\0" + /* 45657 */ "PseudoVNSRL_WV_MF2\0" + /* 45676 */ "PseudoVNCLIP_WV_MF2\0" + /* 45696 */ "PseudoVWSUBU_WV_MF2\0" + /* 45716 */ "PseudoVWADDU_WV_MF2\0" + /* 45736 */ "PseudoVNCLIPU_WV_MF2\0" + /* 45757 */ "PseudoVLSEG2E32_V_MF2\0" + /* 45779 */ "PseudoVLSSEG2E32_V_MF2\0" + /* 45802 */ "PseudoVSSSEG2E32_V_MF2\0" + /* 45825 */ "PseudoVSSEG2E32_V_MF2\0" + /* 45847 */ "PseudoVLSEG3E32_V_MF2\0" + /* 45869 */ "PseudoVLSSEG3E32_V_MF2\0" + /* 45892 */ "PseudoVSSSEG3E32_V_MF2\0" + /* 45915 */ "PseudoVSSEG3E32_V_MF2\0" + /* 45937 */ "PseudoVLSEG4E32_V_MF2\0" + /* 45959 */ "PseudoVLSSEG4E32_V_MF2\0" + /* 45982 */ "PseudoVSSSEG4E32_V_MF2\0" + /* 46005 */ "PseudoVSSEG4E32_V_MF2\0" + /* 46027 */ "PseudoVLSEG5E32_V_MF2\0" + /* 46049 */ "PseudoVLSSEG5E32_V_MF2\0" + /* 46072 */ "PseudoVSSSEG5E32_V_MF2\0" + /* 46095 */ "PseudoVSSEG5E32_V_MF2\0" + /* 46117 */ "PseudoVLSEG6E32_V_MF2\0" + /* 46139 */ "PseudoVLSSEG6E32_V_MF2\0" + /* 46162 */ "PseudoVSSSEG6E32_V_MF2\0" + /* 46185 */ "PseudoVSSEG6E32_V_MF2\0" + /* 46207 */ "PseudoVLSEG7E32_V_MF2\0" + /* 46229 */ "PseudoVLSSEG7E32_V_MF2\0" + /* 46252 */ "PseudoVSSSEG7E32_V_MF2\0" + /* 46275 */ "PseudoVSSEG7E32_V_MF2\0" + /* 46297 */ "PseudoVLSEG8E32_V_MF2\0" + /* 46319 */ "PseudoVLSSEG8E32_V_MF2\0" + /* 46342 */ "PseudoVSSSEG8E32_V_MF2\0" + /* 46365 */ "PseudoVSSEG8E32_V_MF2\0" + /* 46387 */ "PseudoVLE32_V_MF2\0" + /* 46405 */ "PseudoVLSE32_V_MF2\0" + /* 46424 */ "PseudoVSSE32_V_MF2\0" + /* 46443 */ "PseudoVSE32_V_MF2\0" + /* 46461 */ "PseudoVLSEG2E16_V_MF2\0" + /* 46483 */ "PseudoVLSSEG2E16_V_MF2\0" + /* 46506 */ "PseudoVSSSEG2E16_V_MF2\0" + /* 46529 */ "PseudoVSSEG2E16_V_MF2\0" + /* 46551 */ "PseudoVLSEG3E16_V_MF2\0" + /* 46573 */ "PseudoVLSSEG3E16_V_MF2\0" + /* 46596 */ "PseudoVSSSEG3E16_V_MF2\0" + /* 46619 */ "PseudoVSSEG3E16_V_MF2\0" + /* 46641 */ "PseudoVLSEG4E16_V_MF2\0" + /* 46663 */ "PseudoVLSSEG4E16_V_MF2\0" + /* 46686 */ "PseudoVSSSEG4E16_V_MF2\0" + /* 46709 */ "PseudoVSSEG4E16_V_MF2\0" + /* 46731 */ "PseudoVLSEG5E16_V_MF2\0" + /* 46753 */ "PseudoVLSSEG5E16_V_MF2\0" + /* 46776 */ "PseudoVSSSEG5E16_V_MF2\0" + /* 46799 */ "PseudoVSSEG5E16_V_MF2\0" + /* 46821 */ "PseudoVLSEG6E16_V_MF2\0" + /* 46843 */ "PseudoVLSSEG6E16_V_MF2\0" + /* 46866 */ "PseudoVSSSEG6E16_V_MF2\0" + /* 46889 */ "PseudoVSSEG6E16_V_MF2\0" + /* 46911 */ "PseudoVLSEG7E16_V_MF2\0" + /* 46933 */ "PseudoVLSSEG7E16_V_MF2\0" + /* 46956 */ "PseudoVSSSEG7E16_V_MF2\0" + /* 46979 */ "PseudoVSSEG7E16_V_MF2\0" + /* 47001 */ "PseudoVLSEG8E16_V_MF2\0" + /* 47023 */ "PseudoVLSSEG8E16_V_MF2\0" + /* 47046 */ "PseudoVSSSEG8E16_V_MF2\0" + /* 47069 */ "PseudoVSSEG8E16_V_MF2\0" + /* 47091 */ "PseudoVLE16_V_MF2\0" + /* 47109 */ "PseudoVLSE16_V_MF2\0" + /* 47128 */ "PseudoVSSE16_V_MF2\0" + /* 47147 */ "PseudoVSE16_V_MF2\0" + /* 47165 */ "PseudoVFREC7_V_MF2\0" + /* 47184 */ "PseudoVFRSQRT7_V_MF2\0" + /* 47205 */ "PseudoVLSEG2E8_V_MF2\0" + /* 47226 */ "PseudoVLSSEG2E8_V_MF2\0" + /* 47248 */ "PseudoVSSSEG2E8_V_MF2\0" + /* 47270 */ "PseudoVSSEG2E8_V_MF2\0" + /* 47291 */ "PseudoVLSEG3E8_V_MF2\0" + /* 47312 */ "PseudoVLSSEG3E8_V_MF2\0" + /* 47334 */ "PseudoVSSSEG3E8_V_MF2\0" + /* 47356 */ "PseudoVSSEG3E8_V_MF2\0" + /* 47377 */ "PseudoVLSEG4E8_V_MF2\0" + /* 47398 */ "PseudoVLSSEG4E8_V_MF2\0" + /* 47420 */ "PseudoVSSSEG4E8_V_MF2\0" + /* 47442 */ "PseudoVSSEG4E8_V_MF2\0" + /* 47463 */ "PseudoVLSEG5E8_V_MF2\0" + /* 47484 */ "PseudoVLSSEG5E8_V_MF2\0" + /* 47506 */ "PseudoVSSSEG5E8_V_MF2\0" + /* 47528 */ "PseudoVSSEG5E8_V_MF2\0" + /* 47549 */ "PseudoVLSEG6E8_V_MF2\0" + /* 47570 */ "PseudoVLSSEG6E8_V_MF2\0" + /* 47592 */ "PseudoVSSSEG6E8_V_MF2\0" + /* 47614 */ "PseudoVSSEG6E8_V_MF2\0" + /* 47635 */ "PseudoVLSEG7E8_V_MF2\0" + /* 47656 */ "PseudoVLSSEG7E8_V_MF2\0" + /* 47678 */ "PseudoVSSSEG7E8_V_MF2\0" + /* 47700 */ "PseudoVSSEG7E8_V_MF2\0" + /* 47721 */ "PseudoVLSEG8E8_V_MF2\0" + /* 47742 */ "PseudoVLSSEG8E8_V_MF2\0" + /* 47764 */ "PseudoVSSSEG8E8_V_MF2\0" + /* 47786 */ "PseudoVSSEG8E8_V_MF2\0" + /* 47807 */ "PseudoVLE8_V_MF2\0" + /* 47824 */ "PseudoVLSE8_V_MF2\0" + /* 47842 */ "PseudoVSSE8_V_MF2\0" + /* 47860 */ "PseudoVSE8_V_MF2\0" + /* 47877 */ "PseudoVID_V_MF2\0" + /* 47893 */ "PseudoVLSEG2E32FF_V_MF2\0" + /* 47917 */ "PseudoVLSEG3E32FF_V_MF2\0" + /* 47941 */ "PseudoVLSEG4E32FF_V_MF2\0" + /* 47965 */ "PseudoVLSEG5E32FF_V_MF2\0" + /* 47989 */ "PseudoVLSEG6E32FF_V_MF2\0" + /* 48013 */ "PseudoVLSEG7E32FF_V_MF2\0" + /* 48037 */ "PseudoVLSEG8E32FF_V_MF2\0" + /* 48061 */ "PseudoVLE32FF_V_MF2\0" + /* 48081 */ "PseudoVLSEG2E16FF_V_MF2\0" + /* 48105 */ "PseudoVLSEG3E16FF_V_MF2\0" + /* 48129 */ "PseudoVLSEG4E16FF_V_MF2\0" + /* 48153 */ "PseudoVLSEG5E16FF_V_MF2\0" + /* 48177 */ "PseudoVLSEG6E16FF_V_MF2\0" + /* 48201 */ "PseudoVLSEG7E16FF_V_MF2\0" + /* 48225 */ "PseudoVLSEG8E16FF_V_MF2\0" + /* 48249 */ "PseudoVLE16FF_V_MF2\0" + /* 48269 */ "PseudoVLSEG2E8FF_V_MF2\0" + /* 48292 */ "PseudoVLSEG3E8FF_V_MF2\0" + /* 48315 */ "PseudoVLSEG4E8FF_V_MF2\0" + /* 48338 */ "PseudoVLSEG5E8FF_V_MF2\0" + /* 48361 */ "PseudoVLSEG6E8FF_V_MF2\0" + /* 48384 */ "PseudoVLSEG7E8FF_V_MF2\0" + /* 48407 */ "PseudoVLSEG8E8FF_V_MF2\0" + /* 48430 */ "PseudoVLE8FF_V_MF2\0" + /* 48449 */ "PseudoVFWCVT_F_F_V_MF2\0" + /* 48472 */ "PseudoVFCVT_XU_F_V_MF2\0" + /* 48495 */ "PseudoVFWCVT_XU_F_V_MF2\0" + /* 48519 */ "PseudoVFCVT_RTZ_XU_F_V_MF2\0" + /* 48546 */ "PseudoVFWCVT_RTZ_XU_F_V_MF2\0" + /* 48574 */ "PseudoVFCVT_X_F_V_MF2\0" + /* 48596 */ "PseudoVFWCVT_X_F_V_MF2\0" + /* 48619 */ "PseudoVFCVT_RTZ_X_F_V_MF2\0" + /* 48645 */ "PseudoVFWCVT_RTZ_X_F_V_MF2\0" + /* 48672 */ "PseudoVFCLASS_V_MF2\0" + /* 48692 */ "PseudoVFSQRT_V_MF2\0" + /* 48711 */ "PseudoVFCVT_F_XU_V_MF2\0" + /* 48734 */ "PseudoVFWCVT_F_XU_V_MF2\0" + /* 48758 */ "PseudoVMV_V_V_MF2\0" + /* 48776 */ "PseudoVFCVT_F_X_V_MF2\0" + /* 48798 */ "PseudoVFWCVT_F_X_V_MF2\0" + /* 48821 */ "PseudoVFNCVT_ROD_F_F_W_MF2\0" + /* 48848 */ "PseudoVFNCVT_F_F_W_MF2\0" + /* 48871 */ "PseudoVFNCVT_XU_F_W_MF2\0" + /* 48895 */ "PseudoVFNCVT_RTZ_XU_F_W_MF2\0" + /* 48923 */ "PseudoVFNCVT_X_F_W_MF2\0" + /* 48946 */ "PseudoVFNCVT_RTZ_X_F_W_MF2\0" + /* 48973 */ "PseudoVFNCVT_F_XU_W_MF2\0" + /* 48997 */ "PseudoVFNCVT_F_X_W_MF2\0" + /* 49020 */ "PseudoVSSRA_VX_MF2\0" + /* 49039 */ "PseudoVSRA_VX_MF2\0" + /* 49057 */ "PseudoVASUB_VX_MF2\0" + /* 49076 */ "PseudoVNMSUB_VX_MF2\0" + /* 49096 */ "PseudoVRSUB_VX_MF2\0" + /* 49115 */ "PseudoVSSUB_VX_MF2\0" + /* 49134 */ "PseudoVSUB_VX_MF2\0" + /* 49152 */ "PseudoVWSUB_VX_MF2\0" + /* 49171 */ "PseudoVNMSAC_VX_MF2\0" + /* 49191 */ "PseudoVMSBC_VX_MF2\0" + /* 49210 */ "PseudoVMACC_VX_MF2\0" + /* 49229 */ "PseudoVWMACC_VX_MF2\0" + /* 49249 */ "PseudoVMADC_VX_MF2\0" + /* 49268 */ "PseudoVAADD_VX_MF2\0" + /* 49287 */ "PseudoVMADD_VX_MF2\0" + /* 49306 */ "PseudoVSADD_VX_MF2\0" + /* 49325 */ "PseudoVADD_VX_MF2\0" + /* 49343 */ "PseudoVWADD_VX_MF2\0" + /* 49362 */ "PseudoVAND_VX_MF2\0" + /* 49380 */ "PseudoVMSLE_VX_MF2\0" + /* 49399 */ "PseudoVMSNE_VX_MF2\0" + /* 49418 */ "PseudoVMULH_VX_MF2\0" + /* 49437 */ "PseudoVSLL_VX_MF2\0" + /* 49455 */ "PseudoVSSRL_VX_MF2\0" + /* 49474 */ "PseudoVSRL_VX_MF2\0" + /* 49492 */ "PseudoVSMUL_VX_MF2\0" + /* 49511 */ "PseudoVMUL_VX_MF2\0" + /* 49529 */ "PseudoVWMUL_VX_MF2\0" + /* 49548 */ "PseudoVREM_VX_MF2\0" + /* 49566 */ "PseudoVMIN_VX_MF2\0" + /* 49584 */ "PseudoVSLIDE1DOWN_VX_MF2\0" + /* 49609 */ "PseudoVSLIDEDOWN_VX_MF2\0" + /* 49633 */ "PseudoVSLIDE1UP_VX_MF2\0" + /* 49656 */ "PseudoVSLIDEUP_VX_MF2\0" + /* 49678 */ "PseudoVMSEQ_VX_MF2\0" + /* 49697 */ "PseudoVRGATHER_VX_MF2\0" + /* 49719 */ "PseudoVOR_VX_MF2\0" + /* 49736 */ "PseudoVXOR_VX_MF2\0" + /* 49754 */ "PseudoVWMACCUS_VX_MF2\0" + /* 49776 */ "PseudoVMSGT_VX_MF2\0" + /* 49795 */ "PseudoVMSLT_VX_MF2\0" + /* 49814 */ "PseudoVASUBU_VX_MF2\0" + /* 49834 */ "PseudoVSSUBU_VX_MF2\0" + /* 49854 */ "PseudoVWSUBU_VX_MF2\0" + /* 49874 */ "PseudoVWMACCU_VX_MF2\0" + /* 49895 */ "PseudoVAADDU_VX_MF2\0" + /* 49915 */ "PseudoVSADDU_VX_MF2\0" + /* 49935 */ "PseudoVWADDU_VX_MF2\0" + /* 49955 */ "PseudoVMSLEU_VX_MF2\0" + /* 49975 */ "PseudoVMULHU_VX_MF2\0" + /* 49995 */ "PseudoVWMULU_VX_MF2\0" + /* 50015 */ "PseudoVREMU_VX_MF2\0" + /* 50034 */ "PseudoVMINU_VX_MF2\0" + /* 50053 */ "PseudoVWMACCSU_VX_MF2\0" + /* 50075 */ "PseudoVMULHSU_VX_MF2\0" + /* 50096 */ "PseudoVWMULSU_VX_MF2\0" + /* 50117 */ "PseudoVMSGTU_VX_MF2\0" + /* 50137 */ "PseudoVMSLTU_VX_MF2\0" + /* 50157 */ "PseudoVDIVU_VX_MF2\0" + /* 50176 */ "PseudoVMAXU_VX_MF2\0" + /* 50195 */ "PseudoVDIV_VX_MF2\0" + /* 50213 */ "PseudoVMAX_VX_MF2\0" + /* 50231 */ "PseudoVNSRA_WX_MF2\0" + /* 50250 */ "PseudoVWSUB_WX_MF2\0" + /* 50269 */ "PseudoVWADD_WX_MF2\0" + /* 50288 */ "PseudoVNSRL_WX_MF2\0" + /* 50307 */ "PseudoVNCLIP_WX_MF2\0" + /* 50327 */ "PseudoVWSUBU_WX_MF2\0" + /* 50347 */ "PseudoVWADDU_WX_MF2\0" + /* 50367 */ "PseudoVNCLIPU_WX_MF2\0" + /* 50388 */ "PseudoVMV_S_X_MF2\0" + /* 50406 */ "PseudoVMV_V_X_MF2\0" + /* 50424 */ "VSEXT_VF2\0" + /* 50434 */ "VZEXT_VF2\0" + /* 50444 */ "G_FLOG2\0" + /* 50452 */ "PseudoVAMOADDEI64_WD_M1_M2\0" + /* 50479 */ "PseudoVAMOANDEI64_WD_M1_M2\0" + /* 50506 */ "PseudoVAMOMINEI64_WD_M1_M2\0" + /* 50533 */ "PseudoVAMOSWAPEI64_WD_M1_M2\0" + /* 50561 */ "PseudoVAMOOREI64_WD_M1_M2\0" + /* 50587 */ "PseudoVAMOXOREI64_WD_M1_M2\0" + /* 50614 */ "PseudoVAMOMINUEI64_WD_M1_M2\0" + /* 50642 */ "PseudoVAMOMAXUEI64_WD_M1_M2\0" + /* 50670 */ "PseudoVAMOMAXEI64_WD_M1_M2\0" + /* 50697 */ "PseudoVRGATHEREI16_VV_M1_M2\0" + /* 50725 */ "PseudoVLOXSEG2EI32_V_M1_M2\0" + /* 50752 */ "PseudoVSOXSEG2EI32_V_M1_M2\0" + /* 50779 */ "PseudoVLUXSEG2EI32_V_M1_M2\0" + /* 50806 */ "PseudoVSUXSEG2EI32_V_M1_M2\0" + /* 50833 */ "PseudoVLOXSEG3EI32_V_M1_M2\0" + /* 50860 */ "PseudoVSOXSEG3EI32_V_M1_M2\0" + /* 50887 */ "PseudoVLUXSEG3EI32_V_M1_M2\0" + /* 50914 */ "PseudoVSUXSEG3EI32_V_M1_M2\0" + /* 50941 */ "PseudoVLOXSEG4EI32_V_M1_M2\0" + /* 50968 */ "PseudoVSOXSEG4EI32_V_M1_M2\0" + /* 50995 */ "PseudoVLUXSEG4EI32_V_M1_M2\0" + /* 51022 */ "PseudoVSUXSEG4EI32_V_M1_M2\0" + /* 51049 */ "PseudoVLOXEI32_V_M1_M2\0" + /* 51072 */ "PseudoVSOXEI32_V_M1_M2\0" + /* 51095 */ "PseudoVLUXEI32_V_M1_M2\0" + /* 51118 */ "PseudoVSUXEI32_V_M1_M2\0" + /* 51141 */ "PseudoVLOXSEG2EI16_V_M1_M2\0" + /* 51168 */ "PseudoVSOXSEG2EI16_V_M1_M2\0" + /* 51195 */ "PseudoVLUXSEG2EI16_V_M1_M2\0" + /* 51222 */ "PseudoVSUXSEG2EI16_V_M1_M2\0" + /* 51249 */ "PseudoVLOXSEG3EI16_V_M1_M2\0" + /* 51276 */ "PseudoVSOXSEG3EI16_V_M1_M2\0" + /* 51303 */ "PseudoVLUXSEG3EI16_V_M1_M2\0" + /* 51330 */ "PseudoVSUXSEG3EI16_V_M1_M2\0" + /* 51357 */ "PseudoVLOXSEG4EI16_V_M1_M2\0" + /* 51384 */ "PseudoVSOXSEG4EI16_V_M1_M2\0" + /* 51411 */ "PseudoVLUXSEG4EI16_V_M1_M2\0" + /* 51438 */ "PseudoVSUXSEG4EI16_V_M1_M2\0" + /* 51465 */ "PseudoVLOXEI16_V_M1_M2\0" + /* 51488 */ "PseudoVSOXEI16_V_M1_M2\0" + /* 51511 */ "PseudoVLUXEI16_V_M1_M2\0" + /* 51534 */ "PseudoVSUXEI16_V_M1_M2\0" + /* 51557 */ "PseudoVLOXSEG2EI8_V_M1_M2\0" + /* 51583 */ "PseudoVSOXSEG2EI8_V_M1_M2\0" + /* 51609 */ "PseudoVLUXSEG2EI8_V_M1_M2\0" + /* 51635 */ "PseudoVSUXSEG2EI8_V_M1_M2\0" + /* 51661 */ "PseudoVLOXSEG3EI8_V_M1_M2\0" + /* 51687 */ "PseudoVSOXSEG3EI8_V_M1_M2\0" + /* 51713 */ "PseudoVLUXSEG3EI8_V_M1_M2\0" + /* 51739 */ "PseudoVSUXSEG3EI8_V_M1_M2\0" + /* 51765 */ "PseudoVLOXSEG4EI8_V_M1_M2\0" + /* 51791 */ "PseudoVSOXSEG4EI8_V_M1_M2\0" + /* 51817 */ "PseudoVLUXSEG4EI8_V_M1_M2\0" + /* 51843 */ "PseudoVSUXSEG4EI8_V_M1_M2\0" + /* 51869 */ "PseudoVLOXEI8_V_M1_M2\0" + /* 51891 */ "PseudoVSOXEI8_V_M1_M2\0" + /* 51913 */ "PseudoVLUXEI8_V_M1_M2\0" + /* 51935 */ "PseudoVSUXEI8_V_M1_M2\0" + /* 51957 */ "PseudoVFSUB_VF32_M2\0" + /* 51977 */ "PseudoVFMSUB_VF32_M2\0" + /* 51998 */ "PseudoVFNMSUB_VF32_M2\0" + /* 52020 */ "PseudoVFRSUB_VF32_M2\0" + /* 52041 */ "PseudoVFWSUB_VF32_M2\0" + /* 52062 */ "PseudoVFMSAC_VF32_M2\0" + /* 52083 */ "PseudoVFNMSAC_VF32_M2\0" + /* 52105 */ "PseudoVFWNMSAC_VF32_M2\0" + /* 52128 */ "PseudoVFWMSAC_VF32_M2\0" + /* 52150 */ "PseudoVFMACC_VF32_M2\0" + /* 52171 */ "PseudoVFNMACC_VF32_M2\0" + /* 52193 */ "PseudoVFWNMACC_VF32_M2\0" + /* 52216 */ "PseudoVFWMACC_VF32_M2\0" + /* 52238 */ "PseudoVFADD_VF32_M2\0" + /* 52258 */ "PseudoVFMADD_VF32_M2\0" + /* 52279 */ "PseudoVFNMADD_VF32_M2\0" + /* 52301 */ "PseudoVFWADD_VF32_M2\0" + /* 52322 */ "PseudoVMFGE_VF32_M2\0" + /* 52342 */ "PseudoVMFLE_VF32_M2\0" + /* 52362 */ "PseudoVMFNE_VF32_M2\0" + /* 52382 */ "PseudoVFSGNJ_VF32_M2\0" + /* 52403 */ "PseudoVFMUL_VF32_M2\0" + /* 52423 */ "PseudoVFWMUL_VF32_M2\0" + /* 52444 */ "PseudoVFMIN_VF32_M2\0" + /* 52464 */ "PseudoVFSGNJN_VF32_M2\0" + /* 52486 */ "PseudoVFSLIDE1DOWN_VF32_M2\0" + /* 52513 */ "PseudoVFSLIDE1UP_VF32_M2\0" + /* 52538 */ "PseudoVMFEQ_VF32_M2\0" + /* 52558 */ "PseudoVMFGT_VF32_M2\0" + /* 52578 */ "PseudoVMFLT_VF32_M2\0" + /* 52598 */ "PseudoVFDIV_VF32_M2\0" + /* 52618 */ "PseudoVFRDIV_VF32_M2\0" + /* 52639 */ "PseudoVFMAX_VF32_M2\0" + /* 52659 */ "PseudoVFSGNJX_VF32_M2\0" + /* 52681 */ "PseudoVFWSUB_WF32_M2\0" + /* 52702 */ "PseudoVFWADD_WF32_M2\0" + /* 52723 */ "PseudoVFMV_S_F32_M2\0" + /* 52743 */ "PseudoVFMV_V_F32_M2\0" + /* 52763 */ "PseudoVRELOAD2_M2\0" + /* 52781 */ "PseudoVLOXSEG2EI16_V_MF2_M2\0" + /* 52809 */ "PseudoVSOXSEG2EI16_V_MF2_M2\0" + /* 52837 */ "PseudoVLUXSEG2EI16_V_MF2_M2\0" + /* 52865 */ "PseudoVSUXSEG2EI16_V_MF2_M2\0" + /* 52893 */ "PseudoVLOXSEG3EI16_V_MF2_M2\0" + /* 52921 */ "PseudoVSOXSEG3EI16_V_MF2_M2\0" + /* 52949 */ "PseudoVLUXSEG3EI16_V_MF2_M2\0" + /* 52977 */ "PseudoVSUXSEG3EI16_V_MF2_M2\0" + /* 53005 */ "PseudoVLOXSEG4EI16_V_MF2_M2\0" + /* 53033 */ "PseudoVSOXSEG4EI16_V_MF2_M2\0" + /* 53061 */ "PseudoVLUXSEG4EI16_V_MF2_M2\0" + /* 53089 */ "PseudoVSUXSEG4EI16_V_MF2_M2\0" + /* 53117 */ "PseudoVLOXEI16_V_MF2_M2\0" + /* 53141 */ "PseudoVSOXEI16_V_MF2_M2\0" + /* 53165 */ "PseudoVLUXEI16_V_MF2_M2\0" + /* 53189 */ "PseudoVSUXEI16_V_MF2_M2\0" + /* 53213 */ "PseudoVLOXSEG2EI8_V_MF2_M2\0" + /* 53240 */ "PseudoVSOXSEG2EI8_V_MF2_M2\0" + /* 53267 */ "PseudoVLUXSEG2EI8_V_MF2_M2\0" + /* 53294 */ "PseudoVSUXSEG2EI8_V_MF2_M2\0" + /* 53321 */ "PseudoVLOXSEG3EI8_V_MF2_M2\0" + /* 53348 */ "PseudoVSOXSEG3EI8_V_MF2_M2\0" + /* 53375 */ "PseudoVLUXSEG3EI8_V_MF2_M2\0" + /* 53402 */ "PseudoVSUXSEG3EI8_V_MF2_M2\0" + /* 53429 */ "PseudoVLOXSEG4EI8_V_MF2_M2\0" + /* 53456 */ "PseudoVSOXSEG4EI8_V_MF2_M2\0" + /* 53483 */ "PseudoVLUXSEG4EI8_V_MF2_M2\0" + /* 53510 */ "PseudoVSUXSEG4EI8_V_MF2_M2\0" + /* 53537 */ "PseudoVLOXEI8_V_MF2_M2\0" + /* 53560 */ "PseudoVSOXEI8_V_MF2_M2\0" + /* 53583 */ "PseudoVLUXEI8_V_MF2_M2\0" + /* 53606 */ "PseudoVSUXEI8_V_MF2_M2\0" + /* 53629 */ "PseudoVSEXT_VF2_M2\0" + /* 53648 */ "PseudoVZEXT_VF2_M2\0" + /* 53667 */ "PseudoVSPILL2_M2\0" + /* 53684 */ "PseudoVAMOADDEI32_WD_M2_M2\0" + /* 53711 */ "PseudoVAMOANDEI32_WD_M2_M2\0" + /* 53738 */ "PseudoVAMOMINEI32_WD_M2_M2\0" + /* 53765 */ "PseudoVAMOSWAPEI32_WD_M2_M2\0" + /* 53793 */ "PseudoVAMOOREI32_WD_M2_M2\0" + /* 53819 */ "PseudoVAMOXOREI32_WD_M2_M2\0" + /* 53846 */ "PseudoVAMOMINUEI32_WD_M2_M2\0" + /* 53874 */ "PseudoVAMOMAXUEI32_WD_M2_M2\0" + /* 53902 */ "PseudoVAMOMAXEI32_WD_M2_M2\0" + /* 53929 */ "PseudoVAMOADDEI64_WD_M2_M2\0" + /* 53956 */ "PseudoVAMOANDEI64_WD_M2_M2\0" + /* 53983 */ "PseudoVAMOMINEI64_WD_M2_M2\0" + /* 54010 */ "PseudoVAMOSWAPEI64_WD_M2_M2\0" + /* 54038 */ "PseudoVAMOOREI64_WD_M2_M2\0" + /* 54064 */ "PseudoVAMOXOREI64_WD_M2_M2\0" + /* 54091 */ "PseudoVAMOMINUEI64_WD_M2_M2\0" + /* 54119 */ "PseudoVAMOMAXUEI64_WD_M2_M2\0" + /* 54147 */ "PseudoVAMOMAXEI64_WD_M2_M2\0" + /* 54174 */ "PseudoVRGATHEREI16_VV_M2_M2\0" + /* 54202 */ "PseudoVLOXSEG2EI32_V_M2_M2\0" + /* 54229 */ "PseudoVSOXSEG2EI32_V_M2_M2\0" + /* 54256 */ "PseudoVLUXSEG2EI32_V_M2_M2\0" + /* 54283 */ "PseudoVSUXSEG2EI32_V_M2_M2\0" + /* 54310 */ "PseudoVLOXSEG3EI32_V_M2_M2\0" + /* 54337 */ "PseudoVSOXSEG3EI32_V_M2_M2\0" + /* 54364 */ "PseudoVLUXSEG3EI32_V_M2_M2\0" + /* 54391 */ "PseudoVSUXSEG3EI32_V_M2_M2\0" + /* 54418 */ "PseudoVLOXSEG4EI32_V_M2_M2\0" + /* 54445 */ "PseudoVSOXSEG4EI32_V_M2_M2\0" + /* 54472 */ "PseudoVLUXSEG4EI32_V_M2_M2\0" + /* 54499 */ "PseudoVSUXSEG4EI32_V_M2_M2\0" + /* 54526 */ "PseudoVLOXEI32_V_M2_M2\0" + /* 54549 */ "PseudoVSOXEI32_V_M2_M2\0" + /* 54572 */ "PseudoVLUXEI32_V_M2_M2\0" + /* 54595 */ "PseudoVSUXEI32_V_M2_M2\0" + /* 54618 */ "PseudoVLOXSEG2EI64_V_M2_M2\0" + /* 54645 */ "PseudoVSOXSEG2EI64_V_M2_M2\0" + /* 54672 */ "PseudoVLUXSEG2EI64_V_M2_M2\0" + /* 54699 */ "PseudoVSUXSEG2EI64_V_M2_M2\0" + /* 54726 */ "PseudoVLOXSEG3EI64_V_M2_M2\0" + /* 54753 */ "PseudoVSOXSEG3EI64_V_M2_M2\0" + /* 54780 */ "PseudoVLUXSEG3EI64_V_M2_M2\0" + /* 54807 */ "PseudoVSUXSEG3EI64_V_M2_M2\0" + /* 54834 */ "PseudoVLOXSEG4EI64_V_M2_M2\0" + /* 54861 */ "PseudoVSOXSEG4EI64_V_M2_M2\0" + /* 54888 */ "PseudoVLUXSEG4EI64_V_M2_M2\0" + /* 54915 */ "PseudoVSUXSEG4EI64_V_M2_M2\0" + /* 54942 */ "PseudoVLOXEI64_V_M2_M2\0" + /* 54965 */ "PseudoVSOXEI64_V_M2_M2\0" + /* 54988 */ "PseudoVLUXEI64_V_M2_M2\0" + /* 55011 */ "PseudoVSUXEI64_V_M2_M2\0" + /* 55034 */ "PseudoVLOXSEG2EI16_V_M2_M2\0" + /* 55061 */ "PseudoVSOXSEG2EI16_V_M2_M2\0" + /* 55088 */ "PseudoVLUXSEG2EI16_V_M2_M2\0" + /* 55115 */ "PseudoVSUXSEG2EI16_V_M2_M2\0" + /* 55142 */ "PseudoVLOXSEG3EI16_V_M2_M2\0" + /* 55169 */ "PseudoVSOXSEG3EI16_V_M2_M2\0" + /* 55196 */ "PseudoVLUXSEG3EI16_V_M2_M2\0" + /* 55223 */ "PseudoVSUXSEG3EI16_V_M2_M2\0" + /* 55250 */ "PseudoVLOXSEG4EI16_V_M2_M2\0" + /* 55277 */ "PseudoVSOXSEG4EI16_V_M2_M2\0" + /* 55304 */ "PseudoVLUXSEG4EI16_V_M2_M2\0" + /* 55331 */ "PseudoVSUXSEG4EI16_V_M2_M2\0" + /* 55358 */ "PseudoVLOXEI16_V_M2_M2\0" + /* 55381 */ "PseudoVSOXEI16_V_M2_M2\0" + /* 55404 */ "PseudoVLUXEI16_V_M2_M2\0" + /* 55427 */ "PseudoVSUXEI16_V_M2_M2\0" + /* 55450 */ "PseudoVLOXSEG2EI8_V_M2_M2\0" + /* 55476 */ "PseudoVSOXSEG2EI8_V_M2_M2\0" + /* 55502 */ "PseudoVLUXSEG2EI8_V_M2_M2\0" + /* 55528 */ "PseudoVSUXSEG2EI8_V_M2_M2\0" + /* 55554 */ "PseudoVLOXSEG3EI8_V_M2_M2\0" + /* 55580 */ "PseudoVSOXSEG3EI8_V_M2_M2\0" + /* 55606 */ "PseudoVLUXSEG3EI8_V_M2_M2\0" + /* 55632 */ "PseudoVSUXSEG3EI8_V_M2_M2\0" + /* 55658 */ "PseudoVLOXSEG4EI8_V_M2_M2\0" + /* 55684 */ "PseudoVSOXSEG4EI8_V_M2_M2\0" + /* 55710 */ "PseudoVLUXSEG4EI8_V_M2_M2\0" + /* 55736 */ "PseudoVSUXSEG4EI8_V_M2_M2\0" + /* 55762 */ "PseudoVLOXEI8_V_M2_M2\0" + /* 55784 */ "PseudoVSOXEI8_V_M2_M2\0" + /* 55806 */ "PseudoVLUXEI8_V_M2_M2\0" + /* 55828 */ "PseudoVSUXEI8_V_M2_M2\0" + /* 55850 */ "PseudoVRELOAD3_M2\0" + /* 55868 */ "PseudoVSPILL3_M2\0" + /* 55885 */ "PseudoVFSUB_VF64_M2\0" + /* 55905 */ "PseudoVFMSUB_VF64_M2\0" + /* 55926 */ "PseudoVFNMSUB_VF64_M2\0" + /* 55948 */ "PseudoVFRSUB_VF64_M2\0" + /* 55969 */ "PseudoVFMSAC_VF64_M2\0" + /* 55990 */ "PseudoVFNMSAC_VF64_M2\0" + /* 56012 */ "PseudoVFMACC_VF64_M2\0" + /* 56033 */ "PseudoVFNMACC_VF64_M2\0" + /* 56055 */ "PseudoVFADD_VF64_M2\0" + /* 56075 */ "PseudoVFMADD_VF64_M2\0" + /* 56096 */ "PseudoVFNMADD_VF64_M2\0" + /* 56118 */ "PseudoVMFGE_VF64_M2\0" + /* 56138 */ "PseudoVMFLE_VF64_M2\0" + /* 56158 */ "PseudoVMFNE_VF64_M2\0" + /* 56178 */ "PseudoVFSGNJ_VF64_M2\0" + /* 56199 */ "PseudoVFMUL_VF64_M2\0" + /* 56219 */ "PseudoVFMIN_VF64_M2\0" + /* 56239 */ "PseudoVFSGNJN_VF64_M2\0" + /* 56261 */ "PseudoVFSLIDE1DOWN_VF64_M2\0" + /* 56288 */ "PseudoVFSLIDE1UP_VF64_M2\0" + /* 56313 */ "PseudoVMFEQ_VF64_M2\0" + /* 56333 */ "PseudoVMFGT_VF64_M2\0" + /* 56353 */ "PseudoVMFLT_VF64_M2\0" + /* 56373 */ "PseudoVFDIV_VF64_M2\0" + /* 56393 */ "PseudoVFRDIV_VF64_M2\0" + /* 56414 */ "PseudoVFMAX_VF64_M2\0" + /* 56434 */ "PseudoVFSGNJX_VF64_M2\0" + /* 56456 */ "PseudoVFMV_S_F64_M2\0" + /* 56476 */ "PseudoVFMV_V_F64_M2\0" + /* 56496 */ "PseudoVRELOAD4_M2\0" + /* 56514 */ "PseudoVLOXSEG2EI8_V_MF4_M2\0" + /* 56541 */ "PseudoVSOXSEG2EI8_V_MF4_M2\0" + /* 56568 */ "PseudoVLUXSEG2EI8_V_MF4_M2\0" + /* 56595 */ "PseudoVSUXSEG2EI8_V_MF4_M2\0" + /* 56622 */ "PseudoVLOXSEG3EI8_V_MF4_M2\0" + /* 56649 */ "PseudoVSOXSEG3EI8_V_MF4_M2\0" + /* 56676 */ "PseudoVLUXSEG3EI8_V_MF4_M2\0" + /* 56703 */ "PseudoVSUXSEG3EI8_V_MF4_M2\0" + /* 56730 */ "PseudoVLOXSEG4EI8_V_MF4_M2\0" + /* 56757 */ "PseudoVSOXSEG4EI8_V_MF4_M2\0" + /* 56784 */ "PseudoVLUXSEG4EI8_V_MF4_M2\0" + /* 56811 */ "PseudoVSUXSEG4EI8_V_MF4_M2\0" + /* 56838 */ "PseudoVLOXEI8_V_MF4_M2\0" + /* 56861 */ "PseudoVSOXEI8_V_MF4_M2\0" + /* 56884 */ "PseudoVLUXEI8_V_MF4_M2\0" + /* 56907 */ "PseudoVSUXEI8_V_MF4_M2\0" + /* 56930 */ "PseudoVSEXT_VF4_M2\0" + /* 56949 */ "PseudoVZEXT_VF4_M2\0" + /* 56968 */ "PseudoVSPILL4_M2\0" + /* 56985 */ "PseudoVAMOADDEI32_WD_M4_M2\0" + /* 57012 */ "PseudoVAMOANDEI32_WD_M4_M2\0" + /* 57039 */ "PseudoVAMOMINEI32_WD_M4_M2\0" + /* 57066 */ "PseudoVAMOSWAPEI32_WD_M4_M2\0" + /* 57094 */ "PseudoVAMOOREI32_WD_M4_M2\0" + /* 57120 */ "PseudoVAMOXOREI32_WD_M4_M2\0" + /* 57147 */ "PseudoVAMOMINUEI32_WD_M4_M2\0" + /* 57175 */ "PseudoVAMOMAXUEI32_WD_M4_M2\0" + /* 57203 */ "PseudoVAMOMAXEI32_WD_M4_M2\0" + /* 57230 */ "PseudoVAMOADDEI16_WD_M4_M2\0" + /* 57257 */ "PseudoVAMOANDEI16_WD_M4_M2\0" + /* 57284 */ "PseudoVAMOMINEI16_WD_M4_M2\0" + /* 57311 */ "PseudoVAMOSWAPEI16_WD_M4_M2\0" + /* 57339 */ "PseudoVAMOOREI16_WD_M4_M2\0" + /* 57365 */ "PseudoVAMOXOREI16_WD_M4_M2\0" + /* 57392 */ "PseudoVAMOMINUEI16_WD_M4_M2\0" + /* 57420 */ "PseudoVAMOMAXUEI16_WD_M4_M2\0" + /* 57448 */ "PseudoVAMOMAXEI16_WD_M4_M2\0" + /* 57475 */ "PseudoVRGATHEREI16_VV_M4_M2\0" + /* 57503 */ "PseudoVLOXSEG2EI32_V_M4_M2\0" + /* 57530 */ "PseudoVSOXSEG2EI32_V_M4_M2\0" + /* 57557 */ "PseudoVLUXSEG2EI32_V_M4_M2\0" + /* 57584 */ "PseudoVSUXSEG2EI32_V_M4_M2\0" + /* 57611 */ "PseudoVLOXSEG3EI32_V_M4_M2\0" + /* 57638 */ "PseudoVSOXSEG3EI32_V_M4_M2\0" + /* 57665 */ "PseudoVLUXSEG3EI32_V_M4_M2\0" + /* 57692 */ "PseudoVSUXSEG3EI32_V_M4_M2\0" + /* 57719 */ "PseudoVLOXSEG4EI32_V_M4_M2\0" + /* 57746 */ "PseudoVSOXSEG4EI32_V_M4_M2\0" + /* 57773 */ "PseudoVLUXSEG4EI32_V_M4_M2\0" + /* 57800 */ "PseudoVSUXSEG4EI32_V_M4_M2\0" + /* 57827 */ "PseudoVLOXEI32_V_M4_M2\0" + /* 57850 */ "PseudoVSOXEI32_V_M4_M2\0" + /* 57873 */ "PseudoVLUXEI32_V_M4_M2\0" + /* 57896 */ "PseudoVSUXEI32_V_M4_M2\0" + /* 57919 */ "PseudoVLOXSEG2EI64_V_M4_M2\0" + /* 57946 */ "PseudoVSOXSEG2EI64_V_M4_M2\0" + /* 57973 */ "PseudoVLUXSEG2EI64_V_M4_M2\0" + /* 58000 */ "PseudoVSUXSEG2EI64_V_M4_M2\0" + /* 58027 */ "PseudoVLOXSEG3EI64_V_M4_M2\0" + /* 58054 */ "PseudoVSOXSEG3EI64_V_M4_M2\0" + /* 58081 */ "PseudoVLUXSEG3EI64_V_M4_M2\0" + /* 58108 */ "PseudoVSUXSEG3EI64_V_M4_M2\0" + /* 58135 */ "PseudoVLOXSEG4EI64_V_M4_M2\0" + /* 58162 */ "PseudoVSOXSEG4EI64_V_M4_M2\0" + /* 58189 */ "PseudoVLUXSEG4EI64_V_M4_M2\0" + /* 58216 */ "PseudoVSUXSEG4EI64_V_M4_M2\0" + /* 58243 */ "PseudoVLOXEI64_V_M4_M2\0" + /* 58266 */ "PseudoVSOXEI64_V_M4_M2\0" + /* 58289 */ "PseudoVLUXEI64_V_M4_M2\0" + /* 58312 */ "PseudoVSUXEI64_V_M4_M2\0" + /* 58335 */ "PseudoVLOXSEG2EI16_V_M4_M2\0" + /* 58362 */ "PseudoVSOXSEG2EI16_V_M4_M2\0" + /* 58389 */ "PseudoVLUXSEG2EI16_V_M4_M2\0" + /* 58416 */ "PseudoVSUXSEG2EI16_V_M4_M2\0" + /* 58443 */ "PseudoVLOXSEG3EI16_V_M4_M2\0" + /* 58470 */ "PseudoVSOXSEG3EI16_V_M4_M2\0" + /* 58497 */ "PseudoVLUXSEG3EI16_V_M4_M2\0" + /* 58524 */ "PseudoVSUXSEG3EI16_V_M4_M2\0" + /* 58551 */ "PseudoVLOXSEG4EI16_V_M4_M2\0" + /* 58578 */ "PseudoVSOXSEG4EI16_V_M4_M2\0" + /* 58605 */ "PseudoVLUXSEG4EI16_V_M4_M2\0" + /* 58632 */ "PseudoVSUXSEG4EI16_V_M4_M2\0" + /* 58659 */ "PseudoVLOXEI16_V_M4_M2\0" + /* 58682 */ "PseudoVSOXEI16_V_M4_M2\0" + /* 58705 */ "PseudoVLUXEI16_V_M4_M2\0" + /* 58728 */ "PseudoVSUXEI16_V_M4_M2\0" + /* 58751 */ "PseudoVFSUB_VF16_M2\0" + /* 58771 */ "PseudoVFMSUB_VF16_M2\0" + /* 58792 */ "PseudoVFNMSUB_VF16_M2\0" + /* 58814 */ "PseudoVFRSUB_VF16_M2\0" + /* 58835 */ "PseudoVFWSUB_VF16_M2\0" + /* 58856 */ "PseudoVFMSAC_VF16_M2\0" + /* 58877 */ "PseudoVFNMSAC_VF16_M2\0" + /* 58899 */ "PseudoVFWNMSAC_VF16_M2\0" + /* 58922 */ "PseudoVFWMSAC_VF16_M2\0" + /* 58944 */ "PseudoVFMACC_VF16_M2\0" + /* 58965 */ "PseudoVFNMACC_VF16_M2\0" + /* 58987 */ "PseudoVFWNMACC_VF16_M2\0" + /* 59010 */ "PseudoVFWMACC_VF16_M2\0" + /* 59032 */ "PseudoVFADD_VF16_M2\0" + /* 59052 */ "PseudoVFMADD_VF16_M2\0" + /* 59073 */ "PseudoVFNMADD_VF16_M2\0" + /* 59095 */ "PseudoVFWADD_VF16_M2\0" + /* 59116 */ "PseudoVMFGE_VF16_M2\0" + /* 59136 */ "PseudoVMFLE_VF16_M2\0" + /* 59156 */ "PseudoVMFNE_VF16_M2\0" + /* 59176 */ "PseudoVFSGNJ_VF16_M2\0" + /* 59197 */ "PseudoVFMUL_VF16_M2\0" + /* 59217 */ "PseudoVFWMUL_VF16_M2\0" + /* 59238 */ "PseudoVFMIN_VF16_M2\0" + /* 59258 */ "PseudoVFSGNJN_VF16_M2\0" + /* 59280 */ "PseudoVFSLIDE1DOWN_VF16_M2\0" + /* 59307 */ "PseudoVFSLIDE1UP_VF16_M2\0" + /* 59332 */ "PseudoVMFEQ_VF16_M2\0" + /* 59352 */ "PseudoVMFGT_VF16_M2\0" + /* 59372 */ "PseudoVMFLT_VF16_M2\0" + /* 59392 */ "PseudoVFDIV_VF16_M2\0" + /* 59412 */ "PseudoVFRDIV_VF16_M2\0" + /* 59433 */ "PseudoVFMAX_VF16_M2\0" + /* 59453 */ "PseudoVFSGNJX_VF16_M2\0" + /* 59475 */ "PseudoVFWSUB_WF16_M2\0" + /* 59496 */ "PseudoVFWADD_WF16_M2\0" + /* 59517 */ "PseudoVFMV_S_F16_M2\0" + /* 59537 */ "PseudoVFMV_V_F16_M2\0" + /* 59557 */ "PseudoVSEXT_VF8_M2\0" + /* 59576 */ "PseudoVZEXT_VF8_M2\0" + /* 59595 */ "PseudoVAMOADDEI16_WD_M8_M2\0" + /* 59622 */ "PseudoVAMOANDEI16_WD_M8_M2\0" + /* 59649 */ "PseudoVAMOMINEI16_WD_M8_M2\0" + /* 59676 */ "PseudoVAMOSWAPEI16_WD_M8_M2\0" + /* 59704 */ "PseudoVAMOOREI16_WD_M8_M2\0" + /* 59730 */ "PseudoVAMOXOREI16_WD_M8_M2\0" + /* 59757 */ "PseudoVAMOMINUEI16_WD_M8_M2\0" + /* 59785 */ "PseudoVAMOMAXUEI16_WD_M8_M2\0" + /* 59813 */ "PseudoVAMOMAXEI16_WD_M8_M2\0" + /* 59840 */ "PseudoVAMOADDEI8_WD_M8_M2\0" + /* 59866 */ "PseudoVAMOANDEI8_WD_M8_M2\0" + /* 59892 */ "PseudoVAMOMINEI8_WD_M8_M2\0" + /* 59918 */ "PseudoVAMOSWAPEI8_WD_M8_M2\0" + /* 59945 */ "PseudoVAMOOREI8_WD_M8_M2\0" + /* 59970 */ "PseudoVAMOXOREI8_WD_M8_M2\0" + /* 59996 */ "PseudoVAMOMINUEI8_WD_M8_M2\0" + /* 60023 */ "PseudoVAMOMAXUEI8_WD_M8_M2\0" + /* 60050 */ "PseudoVAMOMAXEI8_WD_M8_M2\0" + /* 60076 */ "PseudoVRGATHEREI16_VV_M8_M2\0" + /* 60104 */ "PseudoVLOXSEG2EI32_V_M8_M2\0" + /* 60131 */ "PseudoVSOXSEG2EI32_V_M8_M2\0" + /* 60158 */ "PseudoVLUXSEG2EI32_V_M8_M2\0" + /* 60185 */ "PseudoVSUXSEG2EI32_V_M8_M2\0" + /* 60212 */ "PseudoVLOXSEG3EI32_V_M8_M2\0" + /* 60239 */ "PseudoVSOXSEG3EI32_V_M8_M2\0" + /* 60266 */ "PseudoVLUXSEG3EI32_V_M8_M2\0" + /* 60293 */ "PseudoVSUXSEG3EI32_V_M8_M2\0" + /* 60320 */ "PseudoVLOXSEG4EI32_V_M8_M2\0" + /* 60347 */ "PseudoVSOXSEG4EI32_V_M8_M2\0" + /* 60374 */ "PseudoVLUXSEG4EI32_V_M8_M2\0" + /* 60401 */ "PseudoVSUXSEG4EI32_V_M8_M2\0" + /* 60428 */ "PseudoVLOXEI32_V_M8_M2\0" + /* 60451 */ "PseudoVSOXEI32_V_M8_M2\0" + /* 60474 */ "PseudoVLUXEI32_V_M8_M2\0" + /* 60497 */ "PseudoVSUXEI32_V_M8_M2\0" + /* 60520 */ "PseudoVLOXSEG2EI64_V_M8_M2\0" + /* 60547 */ "PseudoVSOXSEG2EI64_V_M8_M2\0" + /* 60574 */ "PseudoVLUXSEG2EI64_V_M8_M2\0" + /* 60601 */ "PseudoVSUXSEG2EI64_V_M8_M2\0" + /* 60628 */ "PseudoVLOXSEG3EI64_V_M8_M2\0" + /* 60655 */ "PseudoVSOXSEG3EI64_V_M8_M2\0" + /* 60682 */ "PseudoVLUXSEG3EI64_V_M8_M2\0" + /* 60709 */ "PseudoVSUXSEG3EI64_V_M8_M2\0" + /* 60736 */ "PseudoVLOXSEG4EI64_V_M8_M2\0" + /* 60763 */ "PseudoVSOXSEG4EI64_V_M8_M2\0" + /* 60790 */ "PseudoVLUXSEG4EI64_V_M8_M2\0" + /* 60817 */ "PseudoVSUXSEG4EI64_V_M8_M2\0" + /* 60844 */ "PseudoVLOXEI64_V_M8_M2\0" + /* 60867 */ "PseudoVSOXEI64_V_M8_M2\0" + /* 60890 */ "PseudoVLUXEI64_V_M8_M2\0" + /* 60913 */ "PseudoVSUXEI64_V_M8_M2\0" + /* 60936 */ "PseudoVRELOAD_M2\0" + /* 60953 */ "PseudoVSSRA_VI_M2\0" + /* 60971 */ "PseudoVSRA_VI_M2\0" + /* 60988 */ "PseudoVRSUB_VI_M2\0" + /* 61006 */ "PseudoVMADC_VI_M2\0" + /* 61024 */ "PseudoVSADD_VI_M2\0" + /* 61042 */ "PseudoVADD_VI_M2\0" + /* 61059 */ "PseudoVAND_VI_M2\0" + /* 61076 */ "PseudoVMSLE_VI_M2\0" + /* 61094 */ "PseudoVMSNE_VI_M2\0" + /* 61112 */ "PseudoVSLL_VI_M2\0" + /* 61129 */ "PseudoVSSRL_VI_M2\0" + /* 61147 */ "PseudoVSRL_VI_M2\0" + /* 61164 */ "PseudoVSLIDEDOWN_VI_M2\0" + /* 61187 */ "PseudoVSLIDEUP_VI_M2\0" + /* 61208 */ "PseudoVMSEQ_VI_M2\0" + /* 61226 */ "PseudoVRGATHER_VI_M2\0" + /* 61247 */ "PseudoVOR_VI_M2\0" + /* 61263 */ "PseudoVXOR_VI_M2\0" + /* 61280 */ "PseudoVMSGT_VI_M2\0" + /* 61298 */ "PseudoVSADDU_VI_M2\0" + /* 61317 */ "PseudoVMSLEU_VI_M2\0" + /* 61336 */ "PseudoVMSGTU_VI_M2\0" + /* 61355 */ "PseudoVNSRA_WI_M2\0" + /* 61373 */ "PseudoVNSRL_WI_M2\0" + /* 61391 */ "PseudoVNCLIP_WI_M2\0" + /* 61410 */ "PseudoVNCLIPU_WI_M2\0" + /* 61430 */ "PseudoVMV_V_I_M2\0" + /* 61447 */ "PseudoVSPILL_M2\0" + /* 61463 */ "PseudoVFMERGE_VF32M_M2\0" + /* 61486 */ "PseudoVFMERGE_VF64M_M2\0" + /* 61509 */ "PseudoVFMERGE_VF16M_M2\0" + /* 61532 */ "PseudoVMADC_VIM_M2\0" + /* 61551 */ "PseudoVADC_VIM_M2\0" + /* 61569 */ "PseudoVMERGE_VIM_M2\0" + /* 61589 */ "PseudoVMAND_MM_M2\0" + /* 61607 */ "PseudoVMNAND_MM_M2\0" + /* 61626 */ "PseudoVMANDN_MM_M2\0" + /* 61645 */ "PseudoVMORN_MM_M2\0" + /* 61663 */ "PseudoVMOR_MM_M2\0" + /* 61680 */ "PseudoVMNOR_MM_M2\0" + /* 61698 */ "PseudoVMXNOR_MM_M2\0" + /* 61717 */ "PseudoVMXOR_MM_M2\0" + /* 61735 */ "PseudoVMSBC_VVM_M2\0" + /* 61754 */ "PseudoVSBC_VVM_M2\0" + /* 61772 */ "PseudoVMADC_VVM_M2\0" + /* 61791 */ "PseudoVADC_VVM_M2\0" + /* 61809 */ "PseudoVMERGE_VVM_M2\0" + /* 61829 */ "PseudoVCOMPRESS_VM_M2\0" + /* 61851 */ "PseudoVMSBC_VXM_M2\0" + /* 61870 */ "PseudoVSBC_VXM_M2\0" + /* 61888 */ "PseudoVMADC_VXM_M2\0" + /* 61907 */ "PseudoVADC_VXM_M2\0" + /* 61925 */ "PseudoVMERGE_VXM_M2\0" + /* 61945 */ "PseudoVIOTA_M_M2\0" + /* 61962 */ "PseudoVREDAND_VS_M2\0" + /* 61982 */ "PseudoVREDSUM_VS_M2\0" + /* 62002 */ "PseudoVWREDSUM_VS_M2\0" + /* 62023 */ "PseudoVFREDOSUM_VS_M2\0" + /* 62045 */ "PseudoVFWREDOSUM_VS_M2\0" + /* 62068 */ "PseudoVFREDUSUM_VS_M2\0" + /* 62090 */ "PseudoVFWREDUSUM_VS_M2\0" + /* 62113 */ "PseudoVFREDMIN_VS_M2\0" + /* 62134 */ "PseudoVREDMIN_VS_M2\0" + /* 62154 */ "PseudoVREDOR_VS_M2\0" + /* 62173 */ "PseudoVREDXOR_VS_M2\0" + /* 62193 */ "PseudoVWREDSUMU_VS_M2\0" + /* 62215 */ "PseudoVREDMINU_VS_M2\0" + /* 62236 */ "PseudoVREDMAXU_VS_M2\0" + /* 62257 */ "PseudoVFREDMAX_VS_M2\0" + /* 62278 */ "PseudoVREDMAX_VS_M2\0" + /* 62298 */ "PseudoVFMV_F32_S_M2\0" + /* 62318 */ "PseudoVFMV_F64_S_M2\0" + /* 62338 */ "PseudoVFMV_F16_S_M2\0" + /* 62358 */ "PseudoVMV_X_S_M2\0" + /* 62375 */ "PseudoVSSRA_VV_M2\0" + /* 62393 */ "PseudoVSRA_VV_M2\0" + /* 62410 */ "PseudoVASUB_VV_M2\0" + /* 62428 */ "PseudoVFSUB_VV_M2\0" + /* 62446 */ "PseudoVFMSUB_VV_M2\0" + /* 62465 */ "PseudoVFNMSUB_VV_M2\0" + /* 62485 */ "PseudoVNMSUB_VV_M2\0" + /* 62504 */ "PseudoVSSUB_VV_M2\0" + /* 62522 */ "PseudoVSUB_VV_M2\0" + /* 62539 */ "PseudoVFWSUB_VV_M2\0" + /* 62558 */ "PseudoVWSUB_VV_M2\0" + /* 62576 */ "PseudoVFMSAC_VV_M2\0" + /* 62595 */ "PseudoVFNMSAC_VV_M2\0" + /* 62615 */ "PseudoVNMSAC_VV_M2\0" + /* 62634 */ "PseudoVFWNMSAC_VV_M2\0" + /* 62655 */ "PseudoVFWMSAC_VV_M2\0" + /* 62675 */ "PseudoVMSBC_VV_M2\0" + /* 62693 */ "PseudoVFMACC_VV_M2\0" + /* 62712 */ "PseudoVFNMACC_VV_M2\0" + /* 62732 */ "PseudoVFWNMACC_VV_M2\0" + /* 62753 */ "PseudoVMACC_VV_M2\0" + /* 62771 */ "PseudoVFWMACC_VV_M2\0" + /* 62791 */ "PseudoVWMACC_VV_M2\0" + /* 62810 */ "PseudoVMADC_VV_M2\0" + /* 62828 */ "PseudoVAADD_VV_M2\0" + /* 62846 */ "PseudoVFADD_VV_M2\0" + /* 62864 */ "PseudoVFMADD_VV_M2\0" + /* 62883 */ "PseudoVFNMADD_VV_M2\0" + /* 62903 */ "PseudoVMADD_VV_M2\0" + /* 62921 */ "PseudoVSADD_VV_M2\0" + /* 62939 */ "PseudoVADD_VV_M2\0" + /* 62956 */ "PseudoVFWADD_VV_M2\0" + /* 62975 */ "PseudoVWADD_VV_M2\0" + /* 62993 */ "PseudoVAND_VV_M2\0" + /* 63010 */ "PseudoVMFLE_VV_M2\0" + /* 63028 */ "PseudoVMSLE_VV_M2\0" + /* 63046 */ "PseudoVMFNE_VV_M2\0" + /* 63064 */ "PseudoVMSNE_VV_M2\0" + /* 63082 */ "PseudoVMULH_VV_M2\0" + /* 63100 */ "PseudoVFSGNJ_VV_M2\0" + /* 63119 */ "PseudoVSLL_VV_M2\0" + /* 63136 */ "PseudoVSSRL_VV_M2\0" + /* 63154 */ "PseudoVSRL_VV_M2\0" + /* 63171 */ "PseudoVFMUL_VV_M2\0" + /* 63189 */ "PseudoVSMUL_VV_M2\0" + /* 63207 */ "PseudoVMUL_VV_M2\0" + /* 63224 */ "PseudoVFWMUL_VV_M2\0" + /* 63243 */ "PseudoVWMUL_VV_M2\0" + /* 63261 */ "PseudoVREM_VV_M2\0" + /* 63278 */ "PseudoVFMIN_VV_M2\0" + /* 63296 */ "PseudoVMIN_VV_M2\0" + /* 63313 */ "PseudoVFSGNJN_VV_M2\0" + /* 63333 */ "PseudoVMFEQ_VV_M2\0" + /* 63351 */ "PseudoVMSEQ_VV_M2\0" + /* 63369 */ "PseudoVRGATHER_VV_M2\0" + /* 63390 */ "PseudoVOR_VV_M2\0" + /* 63406 */ "PseudoVXOR_VV_M2\0" + /* 63423 */ "PseudoVMFLT_VV_M2\0" + /* 63441 */ "PseudoVMSLT_VV_M2\0" + /* 63459 */ "PseudoVASUBU_VV_M2\0" + /* 63478 */ "PseudoVSSUBU_VV_M2\0" + /* 63497 */ "PseudoVWSUBU_VV_M2\0" + /* 63516 */ "PseudoVWMACCU_VV_M2\0" + /* 63536 */ "PseudoVAADDU_VV_M2\0" + /* 63555 */ "PseudoVSADDU_VV_M2\0" + /* 63574 */ "PseudoVWADDU_VV_M2\0" + /* 63593 */ "PseudoVMSLEU_VV_M2\0" + /* 63612 */ "PseudoVMULHU_VV_M2\0" + /* 63631 */ "PseudoVWMULU_VV_M2\0" + /* 63650 */ "PseudoVREMU_VV_M2\0" + /* 63668 */ "PseudoVMINU_VV_M2\0" + /* 63686 */ "PseudoVWMACCSU_VV_M2\0" + /* 63707 */ "PseudoVMULHSU_VV_M2\0" + /* 63727 */ "PseudoVWMULSU_VV_M2\0" + /* 63747 */ "PseudoVMSLTU_VV_M2\0" + /* 63766 */ "PseudoVDIVU_VV_M2\0" + /* 63784 */ "PseudoVMAXU_VV_M2\0" + /* 63802 */ "PseudoVFDIV_VV_M2\0" + /* 63820 */ "PseudoVDIV_VV_M2\0" + /* 63837 */ "PseudoVFMAX_VV_M2\0" + /* 63855 */ "PseudoVMAX_VV_M2\0" + /* 63872 */ "PseudoVFSGNJX_VV_M2\0" + /* 63892 */ "PseudoVNSRA_WV_M2\0" + /* 63910 */ "PseudoVFWSUB_WV_M2\0" + /* 63929 */ "PseudoVWSUB_WV_M2\0" + /* 63947 */ "PseudoVFWADD_WV_M2\0" + /* 63966 */ "PseudoVWADD_WV_M2\0" + /* 63984 */ "PseudoVNSRL_WV_M2\0" + /* 64002 */ "PseudoVNCLIP_WV_M2\0" + /* 64021 */ "PseudoVWSUBU_WV_M2\0" + /* 64040 */ "PseudoVWADDU_WV_M2\0" + /* 64059 */ "PseudoVNCLIPU_WV_M2\0" + /* 64079 */ "PseudoVLSEG2E32_V_M2\0" + /* 64100 */ "PseudoVLSSEG2E32_V_M2\0" + /* 64122 */ "PseudoVSSSEG2E32_V_M2\0" + /* 64144 */ "PseudoVSSEG2E32_V_M2\0" + /* 64165 */ "PseudoVLSEG3E32_V_M2\0" + /* 64186 */ "PseudoVLSSEG3E32_V_M2\0" + /* 64208 */ "PseudoVSSSEG3E32_V_M2\0" + /* 64230 */ "PseudoVSSEG3E32_V_M2\0" + /* 64251 */ "PseudoVLSEG4E32_V_M2\0" + /* 64272 */ "PseudoVLSSEG4E32_V_M2\0" + /* 64294 */ "PseudoVSSSEG4E32_V_M2\0" + /* 64316 */ "PseudoVSSEG4E32_V_M2\0" + /* 64337 */ "PseudoVLE32_V_M2\0" + /* 64354 */ "PseudoVLSE32_V_M2\0" + /* 64372 */ "PseudoVSSE32_V_M2\0" + /* 64390 */ "PseudoVSE32_V_M2\0" + /* 64407 */ "PseudoVLSEG2E64_V_M2\0" + /* 64428 */ "PseudoVLSSEG2E64_V_M2\0" + /* 64450 */ "PseudoVSSSEG2E64_V_M2\0" + /* 64472 */ "PseudoVSSEG2E64_V_M2\0" + /* 64493 */ "PseudoVLSEG3E64_V_M2\0" + /* 64514 */ "PseudoVLSSEG3E64_V_M2\0" + /* 64536 */ "PseudoVSSSEG3E64_V_M2\0" + /* 64558 */ "PseudoVSSEG3E64_V_M2\0" + /* 64579 */ "PseudoVLSEG4E64_V_M2\0" + /* 64600 */ "PseudoVLSSEG4E64_V_M2\0" + /* 64622 */ "PseudoVSSSEG4E64_V_M2\0" + /* 64644 */ "PseudoVSSEG4E64_V_M2\0" + /* 64665 */ "PseudoVLE64_V_M2\0" + /* 64682 */ "PseudoVLSE64_V_M2\0" + /* 64700 */ "PseudoVSSE64_V_M2\0" + /* 64718 */ "PseudoVSE64_V_M2\0" + /* 64735 */ "PseudoVLSEG2E16_V_M2\0" + /* 64756 */ "PseudoVLSSEG2E16_V_M2\0" + /* 64778 */ "PseudoVSSSEG2E16_V_M2\0" + /* 64800 */ "PseudoVSSEG2E16_V_M2\0" + /* 64821 */ "PseudoVLSEG3E16_V_M2\0" + /* 64842 */ "PseudoVLSSEG3E16_V_M2\0" + /* 64864 */ "PseudoVSSSEG3E16_V_M2\0" + /* 64886 */ "PseudoVSSEG3E16_V_M2\0" + /* 64907 */ "PseudoVLSEG4E16_V_M2\0" + /* 64928 */ "PseudoVLSSEG4E16_V_M2\0" + /* 64950 */ "PseudoVSSSEG4E16_V_M2\0" + /* 64972 */ "PseudoVSSEG4E16_V_M2\0" + /* 64993 */ "PseudoVLE16_V_M2\0" + /* 65010 */ "PseudoVLSE16_V_M2\0" + /* 65028 */ "PseudoVSSE16_V_M2\0" + /* 65046 */ "PseudoVSE16_V_M2\0" + /* 65063 */ "PseudoVFREC7_V_M2\0" + /* 65081 */ "PseudoVFRSQRT7_V_M2\0" + /* 65101 */ "PseudoVLSEG2E8_V_M2\0" + /* 65121 */ "PseudoVLSSEG2E8_V_M2\0" + /* 65142 */ "PseudoVSSSEG2E8_V_M2\0" + /* 65163 */ "PseudoVSSEG2E8_V_M2\0" + /* 65183 */ "PseudoVLSEG3E8_V_M2\0" + /* 65203 */ "PseudoVLSSEG3E8_V_M2\0" + /* 65224 */ "PseudoVSSSEG3E8_V_M2\0" + /* 65245 */ "PseudoVSSEG3E8_V_M2\0" + /* 65265 */ "PseudoVLSEG4E8_V_M2\0" + /* 65285 */ "PseudoVLSSEG4E8_V_M2\0" + /* 65306 */ "PseudoVSSSEG4E8_V_M2\0" + /* 65327 */ "PseudoVSSEG4E8_V_M2\0" + /* 65347 */ "PseudoVLE8_V_M2\0" + /* 65363 */ "PseudoVLSE8_V_M2\0" + /* 65380 */ "PseudoVSSE8_V_M2\0" + /* 65397 */ "PseudoVSE8_V_M2\0" + /* 65413 */ "PseudoVID_V_M2\0" + /* 65428 */ "PseudoVLSEG2E32FF_V_M2\0" + /* 65451 */ "PseudoVLSEG3E32FF_V_M2\0" + /* 65474 */ "PseudoVLSEG4E32FF_V_M2\0" + /* 65497 */ "PseudoVLE32FF_V_M2\0" + /* 65516 */ "PseudoVLSEG2E64FF_V_M2\0" + /* 65539 */ "PseudoVLSEG3E64FF_V_M2\0" + /* 65562 */ "PseudoVLSEG4E64FF_V_M2\0" + /* 65585 */ "PseudoVLE64FF_V_M2\0" + /* 65604 */ "PseudoVLSEG2E16FF_V_M2\0" + /* 65627 */ "PseudoVLSEG3E16FF_V_M2\0" + /* 65650 */ "PseudoVLSEG4E16FF_V_M2\0" + /* 65673 */ "PseudoVLE16FF_V_M2\0" + /* 65692 */ "PseudoVLSEG2E8FF_V_M2\0" + /* 65714 */ "PseudoVLSEG3E8FF_V_M2\0" + /* 65736 */ "PseudoVLSEG4E8FF_V_M2\0" + /* 65758 */ "PseudoVLE8FF_V_M2\0" + /* 65776 */ "PseudoVFWCVT_F_F_V_M2\0" + /* 65798 */ "PseudoVFCVT_XU_F_V_M2\0" + /* 65820 */ "PseudoVFWCVT_XU_F_V_M2\0" + /* 65843 */ "PseudoVFCVT_RTZ_XU_F_V_M2\0" + /* 65869 */ "PseudoVFWCVT_RTZ_XU_F_V_M2\0" + /* 65896 */ "PseudoVFCVT_X_F_V_M2\0" + /* 65917 */ "PseudoVFWCVT_X_F_V_M2\0" + /* 65939 */ "PseudoVFCVT_RTZ_X_F_V_M2\0" + /* 65964 */ "PseudoVFWCVT_RTZ_X_F_V_M2\0" + /* 65990 */ "PseudoVFCLASS_V_M2\0" + /* 66009 */ "PseudoVFSQRT_V_M2\0" + /* 66027 */ "PseudoVFCVT_F_XU_V_M2\0" + /* 66049 */ "PseudoVFWCVT_F_XU_V_M2\0" + /* 66072 */ "PseudoVMV_V_V_M2\0" + /* 66089 */ "PseudoVFCVT_F_X_V_M2\0" + /* 66110 */ "PseudoVFWCVT_F_X_V_M2\0" + /* 66132 */ "PseudoVFNCVT_ROD_F_F_W_M2\0" + /* 66158 */ "PseudoVFNCVT_F_F_W_M2\0" + /* 66180 */ "PseudoVFNCVT_XU_F_W_M2\0" + /* 66203 */ "PseudoVFNCVT_RTZ_XU_F_W_M2\0" + /* 66230 */ "PseudoVFNCVT_X_F_W_M2\0" + /* 66252 */ "PseudoVFNCVT_RTZ_X_F_W_M2\0" + /* 66278 */ "PseudoVFNCVT_F_XU_W_M2\0" + /* 66301 */ "PseudoVFNCVT_F_X_W_M2\0" + /* 66323 */ "PseudoVSSRA_VX_M2\0" + /* 66341 */ "PseudoVSRA_VX_M2\0" + /* 66358 */ "PseudoVASUB_VX_M2\0" + /* 66376 */ "PseudoVNMSUB_VX_M2\0" + /* 66395 */ "PseudoVRSUB_VX_M2\0" + /* 66413 */ "PseudoVSSUB_VX_M2\0" + /* 66431 */ "PseudoVSUB_VX_M2\0" + /* 66448 */ "PseudoVWSUB_VX_M2\0" + /* 66466 */ "PseudoVNMSAC_VX_M2\0" + /* 66485 */ "PseudoVMSBC_VX_M2\0" + /* 66503 */ "PseudoVMACC_VX_M2\0" + /* 66521 */ "PseudoVWMACC_VX_M2\0" + /* 66540 */ "PseudoVMADC_VX_M2\0" + /* 66558 */ "PseudoVAADD_VX_M2\0" + /* 66576 */ "PseudoVMADD_VX_M2\0" + /* 66594 */ "PseudoVSADD_VX_M2\0" + /* 66612 */ "PseudoVADD_VX_M2\0" + /* 66629 */ "PseudoVWADD_VX_M2\0" + /* 66647 */ "PseudoVAND_VX_M2\0" + /* 66664 */ "PseudoVMSLE_VX_M2\0" + /* 66682 */ "PseudoVMSNE_VX_M2\0" + /* 66700 */ "PseudoVMULH_VX_M2\0" + /* 66718 */ "PseudoVSLL_VX_M2\0" + /* 66735 */ "PseudoVSSRL_VX_M2\0" + /* 66753 */ "PseudoVSRL_VX_M2\0" + /* 66770 */ "PseudoVSMUL_VX_M2\0" + /* 66788 */ "PseudoVMUL_VX_M2\0" + /* 66805 */ "PseudoVWMUL_VX_M2\0" + /* 66823 */ "PseudoVREM_VX_M2\0" + /* 66840 */ "PseudoVMIN_VX_M2\0" + /* 66857 */ "PseudoVSLIDE1DOWN_VX_M2\0" + /* 66881 */ "PseudoVSLIDEDOWN_VX_M2\0" + /* 66904 */ "PseudoVSLIDE1UP_VX_M2\0" + /* 66926 */ "PseudoVSLIDEUP_VX_M2\0" + /* 66947 */ "PseudoVMSEQ_VX_M2\0" + /* 66965 */ "PseudoVRGATHER_VX_M2\0" + /* 66986 */ "PseudoVOR_VX_M2\0" + /* 67002 */ "PseudoVXOR_VX_M2\0" + /* 67019 */ "PseudoVWMACCUS_VX_M2\0" + /* 67040 */ "PseudoVMSGT_VX_M2\0" + /* 67058 */ "PseudoVMSLT_VX_M2\0" + /* 67076 */ "PseudoVASUBU_VX_M2\0" + /* 67095 */ "PseudoVSSUBU_VX_M2\0" + /* 67114 */ "PseudoVWSUBU_VX_M2\0" + /* 67133 */ "PseudoVWMACCU_VX_M2\0" + /* 67153 */ "PseudoVAADDU_VX_M2\0" + /* 67172 */ "PseudoVSADDU_VX_M2\0" + /* 67191 */ "PseudoVWADDU_VX_M2\0" + /* 67210 */ "PseudoVMSLEU_VX_M2\0" + /* 67229 */ "PseudoVMULHU_VX_M2\0" + /* 67248 */ "PseudoVWMULU_VX_M2\0" + /* 67267 */ "PseudoVREMU_VX_M2\0" + /* 67285 */ "PseudoVMINU_VX_M2\0" + /* 67303 */ "PseudoVWMACCSU_VX_M2\0" + /* 67324 */ "PseudoVMULHSU_VX_M2\0" + /* 67344 */ "PseudoVWMULSU_VX_M2\0" + /* 67364 */ "PseudoVMSGTU_VX_M2\0" + /* 67383 */ "PseudoVMSLTU_VX_M2\0" + /* 67402 */ "PseudoVDIVU_VX_M2\0" + /* 67420 */ "PseudoVMAXU_VX_M2\0" + /* 67438 */ "PseudoVDIV_VX_M2\0" + /* 67455 */ "PseudoVMAX_VX_M2\0" + /* 67472 */ "PseudoVNSRA_WX_M2\0" + /* 67490 */ "PseudoVWSUB_WX_M2\0" + /* 67508 */ "PseudoVWADD_WX_M2\0" + /* 67526 */ "PseudoVNSRL_WX_M2\0" + /* 67544 */ "PseudoVNCLIP_WX_M2\0" + /* 67563 */ "PseudoVWSUBU_WX_M2\0" + /* 67582 */ "PseudoVWADDU_WX_M2\0" + /* 67601 */ "PseudoVNCLIPU_WX_M2\0" + /* 67621 */ "PseudoVMV_S_X_M2\0" + /* 67638 */ "PseudoVMV_V_X_M2\0" + /* 67655 */ "G_FEXP2\0" + /* 67663 */ "PseudoVMSBF_M_B64\0" + /* 67681 */ "PseudoVMSIF_M_B64\0" + /* 67699 */ "PseudoVMSOF_M_B64\0" + /* 67717 */ "PseudoVCPOP_M_B64\0" + /* 67735 */ "PseudoVMCLR_M_B64\0" + /* 67753 */ "PseudoVMSET_M_B64\0" + /* 67771 */ "PseudoVFIRST_M_B64\0" + /* 67790 */ "PseudoVLM_V_B64\0" + /* 67806 */ "PseudoVSM_V_B64\0" + /* 67822 */ "REV8_RV64\0" + /* 67832 */ "ZEXTH_RV64\0" + /* 67843 */ "PseudoAtomicLoadNand64\0" + /* 67866 */ "PseudoCmpXchg64\0" + /* 67882 */ "PseudoVMSBF_M_B4\0" + /* 67899 */ "PseudoVMSIF_M_B4\0" + /* 67916 */ "PseudoVMSOF_M_B4\0" + /* 67933 */ "PseudoVCPOP_M_B4\0" + /* 67950 */ "PseudoVMCLR_M_B4\0" + /* 67967 */ "PseudoVMSET_M_B4\0" + /* 67984 */ "PseudoVFIRST_M_B4\0" + /* 68002 */ "PseudoVLM_V_B4\0" + /* 68017 */ "PseudoVSM_V_B4\0" + /* 68032 */ "PseudoVAMOADDEI16_WD_M1_MF4\0" + /* 68060 */ "PseudoVAMOANDEI16_WD_M1_MF4\0" + /* 68088 */ "PseudoVAMOMINEI16_WD_M1_MF4\0" + /* 68116 */ "PseudoVAMOSWAPEI16_WD_M1_MF4\0" + /* 68145 */ "PseudoVAMOOREI16_WD_M1_MF4\0" + /* 68172 */ "PseudoVAMOXOREI16_WD_M1_MF4\0" + /* 68200 */ "PseudoVAMOMINUEI16_WD_M1_MF4\0" + /* 68229 */ "PseudoVAMOMAXUEI16_WD_M1_MF4\0" + /* 68258 */ "PseudoVAMOMAXEI16_WD_M1_MF4\0" + /* 68286 */ "PseudoVAMOADDEI8_WD_M1_MF4\0" + /* 68313 */ "PseudoVAMOANDEI8_WD_M1_MF4\0" + /* 68340 */ "PseudoVAMOMINEI8_WD_M1_MF4\0" + /* 68367 */ "PseudoVAMOSWAPEI8_WD_M1_MF4\0" + /* 68395 */ "PseudoVAMOOREI8_WD_M1_MF4\0" + /* 68421 */ "PseudoVAMOXOREI8_WD_M1_MF4\0" + /* 68448 */ "PseudoVAMOMINUEI8_WD_M1_MF4\0" + /* 68476 */ "PseudoVAMOMAXUEI8_WD_M1_MF4\0" + /* 68504 */ "PseudoVAMOMAXEI8_WD_M1_MF4\0" + /* 68531 */ "PseudoVRGATHEREI16_VV_M1_MF4\0" + /* 68560 */ "PseudoVLOXSEG2EI32_V_M1_MF4\0" + /* 68588 */ "PseudoVSOXSEG2EI32_V_M1_MF4\0" + /* 68616 */ "PseudoVLUXSEG2EI32_V_M1_MF4\0" + /* 68644 */ "PseudoVSUXSEG2EI32_V_M1_MF4\0" + /* 68672 */ "PseudoVLOXSEG3EI32_V_M1_MF4\0" + /* 68700 */ "PseudoVSOXSEG3EI32_V_M1_MF4\0" + /* 68728 */ "PseudoVLUXSEG3EI32_V_M1_MF4\0" + /* 68756 */ "PseudoVSUXSEG3EI32_V_M1_MF4\0" + /* 68784 */ "PseudoVLOXSEG4EI32_V_M1_MF4\0" + /* 68812 */ "PseudoVSOXSEG4EI32_V_M1_MF4\0" + /* 68840 */ "PseudoVLUXSEG4EI32_V_M1_MF4\0" + /* 68868 */ "PseudoVSUXSEG4EI32_V_M1_MF4\0" + /* 68896 */ "PseudoVLOXSEG5EI32_V_M1_MF4\0" + /* 68924 */ "PseudoVSOXSEG5EI32_V_M1_MF4\0" + /* 68952 */ "PseudoVLUXSEG5EI32_V_M1_MF4\0" + /* 68980 */ "PseudoVSUXSEG5EI32_V_M1_MF4\0" + /* 69008 */ "PseudoVLOXSEG6EI32_V_M1_MF4\0" + /* 69036 */ "PseudoVSOXSEG6EI32_V_M1_MF4\0" + /* 69064 */ "PseudoVLUXSEG6EI32_V_M1_MF4\0" + /* 69092 */ "PseudoVSUXSEG6EI32_V_M1_MF4\0" + /* 69120 */ "PseudoVLOXSEG7EI32_V_M1_MF4\0" + /* 69148 */ "PseudoVSOXSEG7EI32_V_M1_MF4\0" + /* 69176 */ "PseudoVLUXSEG7EI32_V_M1_MF4\0" + /* 69204 */ "PseudoVSUXSEG7EI32_V_M1_MF4\0" + /* 69232 */ "PseudoVLOXSEG8EI32_V_M1_MF4\0" + /* 69260 */ "PseudoVSOXSEG8EI32_V_M1_MF4\0" + /* 69288 */ "PseudoVLUXSEG8EI32_V_M1_MF4\0" + /* 69316 */ "PseudoVSUXSEG8EI32_V_M1_MF4\0" + /* 69344 */ "PseudoVLOXEI32_V_M1_MF4\0" + /* 69368 */ "PseudoVSOXEI32_V_M1_MF4\0" + /* 69392 */ "PseudoVLUXEI32_V_M1_MF4\0" + /* 69416 */ "PseudoVSUXEI32_V_M1_MF4\0" + /* 69440 */ "PseudoVLOXSEG2EI64_V_M1_MF4\0" + /* 69468 */ "PseudoVSOXSEG2EI64_V_M1_MF4\0" + /* 69496 */ "PseudoVLUXSEG2EI64_V_M1_MF4\0" + /* 69524 */ "PseudoVSUXSEG2EI64_V_M1_MF4\0" + /* 69552 */ "PseudoVLOXSEG3EI64_V_M1_MF4\0" + /* 69580 */ "PseudoVSOXSEG3EI64_V_M1_MF4\0" + /* 69608 */ "PseudoVLUXSEG3EI64_V_M1_MF4\0" + /* 69636 */ "PseudoVSUXSEG3EI64_V_M1_MF4\0" + /* 69664 */ "PseudoVLOXSEG4EI64_V_M1_MF4\0" + /* 69692 */ "PseudoVSOXSEG4EI64_V_M1_MF4\0" + /* 69720 */ "PseudoVLUXSEG4EI64_V_M1_MF4\0" + /* 69748 */ "PseudoVSUXSEG4EI64_V_M1_MF4\0" + /* 69776 */ "PseudoVLOXSEG5EI64_V_M1_MF4\0" + /* 69804 */ "PseudoVSOXSEG5EI64_V_M1_MF4\0" + /* 69832 */ "PseudoVLUXSEG5EI64_V_M1_MF4\0" + /* 69860 */ "PseudoVSUXSEG5EI64_V_M1_MF4\0" + /* 69888 */ "PseudoVLOXSEG6EI64_V_M1_MF4\0" + /* 69916 */ "PseudoVSOXSEG6EI64_V_M1_MF4\0" + /* 69944 */ "PseudoVLUXSEG6EI64_V_M1_MF4\0" + /* 69972 */ "PseudoVSUXSEG6EI64_V_M1_MF4\0" + /* 70000 */ "PseudoVLOXSEG7EI64_V_M1_MF4\0" + /* 70028 */ "PseudoVSOXSEG7EI64_V_M1_MF4\0" + /* 70056 */ "PseudoVLUXSEG7EI64_V_M1_MF4\0" + /* 70084 */ "PseudoVSUXSEG7EI64_V_M1_MF4\0" + /* 70112 */ "PseudoVLOXSEG8EI64_V_M1_MF4\0" + /* 70140 */ "PseudoVSOXSEG8EI64_V_M1_MF4\0" + /* 70168 */ "PseudoVLUXSEG8EI64_V_M1_MF4\0" + /* 70196 */ "PseudoVSUXSEG8EI64_V_M1_MF4\0" + /* 70224 */ "PseudoVLOXEI64_V_M1_MF4\0" + /* 70248 */ "PseudoVSOXEI64_V_M1_MF4\0" + /* 70272 */ "PseudoVLUXEI64_V_M1_MF4\0" + /* 70296 */ "PseudoVSUXEI64_V_M1_MF4\0" + /* 70320 */ "PseudoVFSUB_VF32_MF4\0" + /* 70341 */ "PseudoVFMSUB_VF32_MF4\0" + /* 70363 */ "PseudoVFNMSUB_VF32_MF4\0" + /* 70386 */ "PseudoVFRSUB_VF32_MF4\0" + /* 70408 */ "PseudoVFWSUB_VF32_MF4\0" + /* 70430 */ "PseudoVFMSAC_VF32_MF4\0" + /* 70452 */ "PseudoVFNMSAC_VF32_MF4\0" + /* 70475 */ "PseudoVFWNMSAC_VF32_MF4\0" + /* 70499 */ "PseudoVFWMSAC_VF32_MF4\0" + /* 70522 */ "PseudoVFMACC_VF32_MF4\0" + /* 70544 */ "PseudoVFNMACC_VF32_MF4\0" + /* 70567 */ "PseudoVFWNMACC_VF32_MF4\0" + /* 70591 */ "PseudoVFWMACC_VF32_MF4\0" + /* 70614 */ "PseudoVFADD_VF32_MF4\0" + /* 70635 */ "PseudoVFMADD_VF32_MF4\0" + /* 70657 */ "PseudoVFNMADD_VF32_MF4\0" + /* 70680 */ "PseudoVFWADD_VF32_MF4\0" + /* 70702 */ "PseudoVMFGE_VF32_MF4\0" + /* 70723 */ "PseudoVMFLE_VF32_MF4\0" + /* 70744 */ "PseudoVMFNE_VF32_MF4\0" + /* 70765 */ "PseudoVFSGNJ_VF32_MF4\0" + /* 70787 */ "PseudoVFMUL_VF32_MF4\0" + /* 70808 */ "PseudoVFWMUL_VF32_MF4\0" + /* 70830 */ "PseudoVFMIN_VF32_MF4\0" + /* 70851 */ "PseudoVFSGNJN_VF32_MF4\0" + /* 70874 */ "PseudoVFSLIDE1DOWN_VF32_MF4\0" + /* 70902 */ "PseudoVFSLIDE1UP_VF32_MF4\0" + /* 70928 */ "PseudoVMFEQ_VF32_MF4\0" + /* 70949 */ "PseudoVMFGT_VF32_MF4\0" + /* 70970 */ "PseudoVMFLT_VF32_MF4\0" + /* 70991 */ "PseudoVFDIV_VF32_MF4\0" + /* 71012 */ "PseudoVFRDIV_VF32_MF4\0" + /* 71034 */ "PseudoVFMAX_VF32_MF4\0" + /* 71055 */ "PseudoVFSGNJX_VF32_MF4\0" + /* 71078 */ "PseudoVFWSUB_WF32_MF4\0" + /* 71100 */ "PseudoVFWADD_WF32_MF4\0" + /* 71122 */ "PseudoVFMV_S_F32_MF4\0" + /* 71143 */ "PseudoVFMV_V_F32_MF4\0" + /* 71164 */ "PseudoVRELOAD2_MF4\0" + /* 71183 */ "PseudoVAMOADDEI16_WD_MF2_MF4\0" + /* 71212 */ "PseudoVAMOANDEI16_WD_MF2_MF4\0" + /* 71241 */ "PseudoVAMOMINEI16_WD_MF2_MF4\0" + /* 71270 */ "PseudoVAMOSWAPEI16_WD_MF2_MF4\0" + /* 71300 */ "PseudoVAMOOREI16_WD_MF2_MF4\0" + /* 71328 */ "PseudoVAMOXOREI16_WD_MF2_MF4\0" + /* 71357 */ "PseudoVAMOMINUEI16_WD_MF2_MF4\0" + /* 71387 */ "PseudoVAMOMAXUEI16_WD_MF2_MF4\0" + /* 71417 */ "PseudoVAMOMAXEI16_WD_MF2_MF4\0" + /* 71446 */ "PseudoVRGATHEREI16_VV_MF2_MF4\0" + /* 71476 */ "PseudoVLOXSEG2EI32_V_MF2_MF4\0" + /* 71505 */ "PseudoVSOXSEG2EI32_V_MF2_MF4\0" + /* 71534 */ "PseudoVLUXSEG2EI32_V_MF2_MF4\0" + /* 71563 */ "PseudoVSUXSEG2EI32_V_MF2_MF4\0" + /* 71592 */ "PseudoVLOXSEG3EI32_V_MF2_MF4\0" + /* 71621 */ "PseudoVSOXSEG3EI32_V_MF2_MF4\0" + /* 71650 */ "PseudoVLUXSEG3EI32_V_MF2_MF4\0" + /* 71679 */ "PseudoVSUXSEG3EI32_V_MF2_MF4\0" + /* 71708 */ "PseudoVLOXSEG4EI32_V_MF2_MF4\0" + /* 71737 */ "PseudoVSOXSEG4EI32_V_MF2_MF4\0" + /* 71766 */ "PseudoVLUXSEG4EI32_V_MF2_MF4\0" + /* 71795 */ "PseudoVSUXSEG4EI32_V_MF2_MF4\0" + /* 71824 */ "PseudoVLOXSEG5EI32_V_MF2_MF4\0" + /* 71853 */ "PseudoVSOXSEG5EI32_V_MF2_MF4\0" + /* 71882 */ "PseudoVLUXSEG5EI32_V_MF2_MF4\0" + /* 71911 */ "PseudoVSUXSEG5EI32_V_MF2_MF4\0" + /* 71940 */ "PseudoVLOXSEG6EI32_V_MF2_MF4\0" + /* 71969 */ "PseudoVSOXSEG6EI32_V_MF2_MF4\0" + /* 71998 */ "PseudoVLUXSEG6EI32_V_MF2_MF4\0" + /* 72027 */ "PseudoVSUXSEG6EI32_V_MF2_MF4\0" + /* 72056 */ "PseudoVLOXSEG7EI32_V_MF2_MF4\0" + /* 72085 */ "PseudoVSOXSEG7EI32_V_MF2_MF4\0" + /* 72114 */ "PseudoVLUXSEG7EI32_V_MF2_MF4\0" + /* 72143 */ "PseudoVSUXSEG7EI32_V_MF2_MF4\0" + /* 72172 */ "PseudoVLOXSEG8EI32_V_MF2_MF4\0" + /* 72201 */ "PseudoVSOXSEG8EI32_V_MF2_MF4\0" + /* 72230 */ "PseudoVLUXSEG8EI32_V_MF2_MF4\0" + /* 72259 */ "PseudoVSUXSEG8EI32_V_MF2_MF4\0" + /* 72288 */ "PseudoVLOXEI32_V_MF2_MF4\0" + /* 72313 */ "PseudoVSOXEI32_V_MF2_MF4\0" + /* 72338 */ "PseudoVLUXEI32_V_MF2_MF4\0" + /* 72363 */ "PseudoVSUXEI32_V_MF2_MF4\0" + /* 72388 */ "PseudoVLOXSEG2EI16_V_MF2_MF4\0" + /* 72417 */ "PseudoVSOXSEG2EI16_V_MF2_MF4\0" + /* 72446 */ "PseudoVLUXSEG2EI16_V_MF2_MF4\0" + /* 72475 */ "PseudoVSUXSEG2EI16_V_MF2_MF4\0" + /* 72504 */ "PseudoVLOXSEG3EI16_V_MF2_MF4\0" + /* 72533 */ "PseudoVSOXSEG3EI16_V_MF2_MF4\0" + /* 72562 */ "PseudoVLUXSEG3EI16_V_MF2_MF4\0" + /* 72591 */ "PseudoVSUXSEG3EI16_V_MF2_MF4\0" + /* 72620 */ "PseudoVLOXSEG4EI16_V_MF2_MF4\0" + /* 72649 */ "PseudoVSOXSEG4EI16_V_MF2_MF4\0" + /* 72678 */ "PseudoVLUXSEG4EI16_V_MF2_MF4\0" + /* 72707 */ "PseudoVSUXSEG4EI16_V_MF2_MF4\0" + /* 72736 */ "PseudoVLOXSEG5EI16_V_MF2_MF4\0" + /* 72765 */ "PseudoVSOXSEG5EI16_V_MF2_MF4\0" + /* 72794 */ "PseudoVLUXSEG5EI16_V_MF2_MF4\0" + /* 72823 */ "PseudoVSUXSEG5EI16_V_MF2_MF4\0" + /* 72852 */ "PseudoVLOXSEG6EI16_V_MF2_MF4\0" + /* 72881 */ "PseudoVSOXSEG6EI16_V_MF2_MF4\0" + /* 72910 */ "PseudoVLUXSEG6EI16_V_MF2_MF4\0" + /* 72939 */ "PseudoVSUXSEG6EI16_V_MF2_MF4\0" + /* 72968 */ "PseudoVLOXSEG7EI16_V_MF2_MF4\0" + /* 72997 */ "PseudoVSOXSEG7EI16_V_MF2_MF4\0" + /* 73026 */ "PseudoVLUXSEG7EI16_V_MF2_MF4\0" + /* 73055 */ "PseudoVSUXSEG7EI16_V_MF2_MF4\0" + /* 73084 */ "PseudoVLOXSEG8EI16_V_MF2_MF4\0" + /* 73113 */ "PseudoVSOXSEG8EI16_V_MF2_MF4\0" + /* 73142 */ "PseudoVLUXSEG8EI16_V_MF2_MF4\0" + /* 73171 */ "PseudoVSUXSEG8EI16_V_MF2_MF4\0" + /* 73200 */ "PseudoVLOXEI16_V_MF2_MF4\0" + /* 73225 */ "PseudoVSOXEI16_V_MF2_MF4\0" + /* 73250 */ "PseudoVLUXEI16_V_MF2_MF4\0" + /* 73275 */ "PseudoVSUXEI16_V_MF2_MF4\0" + /* 73300 */ "PseudoVSEXT_VF2_MF4\0" + /* 73320 */ "PseudoVZEXT_VF2_MF4\0" + /* 73340 */ "PseudoVSPILL2_MF4\0" + /* 73358 */ "PseudoVAMOADDEI8_WD_M2_MF4\0" + /* 73385 */ "PseudoVAMOANDEI8_WD_M2_MF4\0" + /* 73412 */ "PseudoVAMOMINEI8_WD_M2_MF4\0" + /* 73439 */ "PseudoVAMOSWAPEI8_WD_M2_MF4\0" + /* 73467 */ "PseudoVAMOOREI8_WD_M2_MF4\0" + /* 73493 */ "PseudoVAMOXOREI8_WD_M2_MF4\0" + /* 73520 */ "PseudoVAMOMINUEI8_WD_M2_MF4\0" + /* 73548 */ "PseudoVAMOMAXUEI8_WD_M2_MF4\0" + /* 73576 */ "PseudoVAMOMAXEI8_WD_M2_MF4\0" + /* 73603 */ "PseudoVLOXSEG2EI64_V_M2_MF4\0" + /* 73631 */ "PseudoVSOXSEG2EI64_V_M2_MF4\0" + /* 73659 */ "PseudoVLUXSEG2EI64_V_M2_MF4\0" + /* 73687 */ "PseudoVSUXSEG2EI64_V_M2_MF4\0" + /* 73715 */ "PseudoVLOXSEG3EI64_V_M2_MF4\0" + /* 73743 */ "PseudoVSOXSEG3EI64_V_M2_MF4\0" + /* 73771 */ "PseudoVLUXSEG3EI64_V_M2_MF4\0" + /* 73799 */ "PseudoVSUXSEG3EI64_V_M2_MF4\0" + /* 73827 */ "PseudoVLOXSEG4EI64_V_M2_MF4\0" + /* 73855 */ "PseudoVSOXSEG4EI64_V_M2_MF4\0" + /* 73883 */ "PseudoVLUXSEG4EI64_V_M2_MF4\0" + /* 73911 */ "PseudoVSUXSEG4EI64_V_M2_MF4\0" + /* 73939 */ "PseudoVLOXSEG5EI64_V_M2_MF4\0" + /* 73967 */ "PseudoVSOXSEG5EI64_V_M2_MF4\0" + /* 73995 */ "PseudoVLUXSEG5EI64_V_M2_MF4\0" + /* 74023 */ "PseudoVSUXSEG5EI64_V_M2_MF4\0" + /* 74051 */ "PseudoVLOXSEG6EI64_V_M2_MF4\0" + /* 74079 */ "PseudoVSOXSEG6EI64_V_M2_MF4\0" + /* 74107 */ "PseudoVLUXSEG6EI64_V_M2_MF4\0" + /* 74135 */ "PseudoVSUXSEG6EI64_V_M2_MF4\0" + /* 74163 */ "PseudoVLOXSEG7EI64_V_M2_MF4\0" + /* 74191 */ "PseudoVSOXSEG7EI64_V_M2_MF4\0" + /* 74219 */ "PseudoVLUXSEG7EI64_V_M2_MF4\0" + /* 74247 */ "PseudoVSUXSEG7EI64_V_M2_MF4\0" + /* 74275 */ "PseudoVLOXSEG8EI64_V_M2_MF4\0" + /* 74303 */ "PseudoVSOXSEG8EI64_V_M2_MF4\0" + /* 74331 */ "PseudoVLUXSEG8EI64_V_M2_MF4\0" + /* 74359 */ "PseudoVSUXSEG8EI64_V_M2_MF4\0" + /* 74387 */ "PseudoVLOXEI64_V_M2_MF4\0" + /* 74411 */ "PseudoVSOXEI64_V_M2_MF4\0" + /* 74435 */ "PseudoVLUXEI64_V_M2_MF4\0" + /* 74459 */ "PseudoVSUXEI64_V_M2_MF4\0" + /* 74483 */ "PseudoVRELOAD3_MF4\0" + /* 74502 */ "PseudoVSPILL3_MF4\0" + /* 74520 */ "PseudoVFSUB_VF64_MF4\0" + /* 74541 */ "PseudoVFMSUB_VF64_MF4\0" + /* 74563 */ "PseudoVFNMSUB_VF64_MF4\0" + /* 74586 */ "PseudoVFRSUB_VF64_MF4\0" + /* 74608 */ "PseudoVFMSAC_VF64_MF4\0" + /* 74630 */ "PseudoVFNMSAC_VF64_MF4\0" + /* 74653 */ "PseudoVFMACC_VF64_MF4\0" + /* 74675 */ "PseudoVFNMACC_VF64_MF4\0" + /* 74698 */ "PseudoVFADD_VF64_MF4\0" + /* 74719 */ "PseudoVFMADD_VF64_MF4\0" + /* 74741 */ "PseudoVFNMADD_VF64_MF4\0" + /* 74764 */ "PseudoVMFGE_VF64_MF4\0" + /* 74785 */ "PseudoVMFLE_VF64_MF4\0" + /* 74806 */ "PseudoVMFNE_VF64_MF4\0" + /* 74827 */ "PseudoVFSGNJ_VF64_MF4\0" + /* 74849 */ "PseudoVFMUL_VF64_MF4\0" + /* 74870 */ "PseudoVFMIN_VF64_MF4\0" + /* 74891 */ "PseudoVFSGNJN_VF64_MF4\0" + /* 74914 */ "PseudoVFSLIDE1DOWN_VF64_MF4\0" + /* 74942 */ "PseudoVFSLIDE1UP_VF64_MF4\0" + /* 74968 */ "PseudoVMFEQ_VF64_MF4\0" + /* 74989 */ "PseudoVMFGT_VF64_MF4\0" + /* 75010 */ "PseudoVMFLT_VF64_MF4\0" + /* 75031 */ "PseudoVFDIV_VF64_MF4\0" + /* 75052 */ "PseudoVFRDIV_VF64_MF4\0" + /* 75074 */ "PseudoVFMAX_VF64_MF4\0" + /* 75095 */ "PseudoVFSGNJX_VF64_MF4\0" + /* 75118 */ "PseudoVFMV_S_F64_MF4\0" + /* 75139 */ "PseudoVFMV_V_F64_MF4\0" + /* 75160 */ "PseudoVRELOAD4_MF4\0" + /* 75179 */ "PseudoVRGATHEREI16_VV_MF4_MF4\0" + /* 75209 */ "PseudoVLOXSEG2EI16_V_MF4_MF4\0" + /* 75238 */ "PseudoVSOXSEG2EI16_V_MF4_MF4\0" + /* 75267 */ "PseudoVLUXSEG2EI16_V_MF4_MF4\0" + /* 75296 */ "PseudoVSUXSEG2EI16_V_MF4_MF4\0" + /* 75325 */ "PseudoVLOXSEG3EI16_V_MF4_MF4\0" + /* 75354 */ "PseudoVSOXSEG3EI16_V_MF4_MF4\0" + /* 75383 */ "PseudoVLUXSEG3EI16_V_MF4_MF4\0" + /* 75412 */ "PseudoVSUXSEG3EI16_V_MF4_MF4\0" + /* 75441 */ "PseudoVLOXSEG4EI16_V_MF4_MF4\0" + /* 75470 */ "PseudoVSOXSEG4EI16_V_MF4_MF4\0" + /* 75499 */ "PseudoVLUXSEG4EI16_V_MF4_MF4\0" + /* 75528 */ "PseudoVSUXSEG4EI16_V_MF4_MF4\0" + /* 75557 */ "PseudoVLOXSEG5EI16_V_MF4_MF4\0" + /* 75586 */ "PseudoVSOXSEG5EI16_V_MF4_MF4\0" + /* 75615 */ "PseudoVLUXSEG5EI16_V_MF4_MF4\0" + /* 75644 */ "PseudoVSUXSEG5EI16_V_MF4_MF4\0" + /* 75673 */ "PseudoVLOXSEG6EI16_V_MF4_MF4\0" + /* 75702 */ "PseudoVSOXSEG6EI16_V_MF4_MF4\0" + /* 75731 */ "PseudoVLUXSEG6EI16_V_MF4_MF4\0" + /* 75760 */ "PseudoVSUXSEG6EI16_V_MF4_MF4\0" + /* 75789 */ "PseudoVLOXSEG7EI16_V_MF4_MF4\0" + /* 75818 */ "PseudoVSOXSEG7EI16_V_MF4_MF4\0" + /* 75847 */ "PseudoVLUXSEG7EI16_V_MF4_MF4\0" + /* 75876 */ "PseudoVSUXSEG7EI16_V_MF4_MF4\0" + /* 75905 */ "PseudoVLOXSEG8EI16_V_MF4_MF4\0" + /* 75934 */ "PseudoVSOXSEG8EI16_V_MF4_MF4\0" + /* 75963 */ "PseudoVLUXSEG8EI16_V_MF4_MF4\0" + /* 75992 */ "PseudoVSUXSEG8EI16_V_MF4_MF4\0" + /* 76021 */ "PseudoVLOXEI16_V_MF4_MF4\0" + /* 76046 */ "PseudoVSOXEI16_V_MF4_MF4\0" + /* 76071 */ "PseudoVLUXEI16_V_MF4_MF4\0" + /* 76096 */ "PseudoVSUXEI16_V_MF4_MF4\0" + /* 76121 */ "PseudoVLOXSEG2EI8_V_MF4_MF4\0" + /* 76149 */ "PseudoVSOXSEG2EI8_V_MF4_MF4\0" + /* 76177 */ "PseudoVLUXSEG2EI8_V_MF4_MF4\0" + /* 76205 */ "PseudoVSUXSEG2EI8_V_MF4_MF4\0" + /* 76233 */ "PseudoVLOXSEG3EI8_V_MF4_MF4\0" + /* 76261 */ "PseudoVSOXSEG3EI8_V_MF4_MF4\0" + /* 76289 */ "PseudoVLUXSEG3EI8_V_MF4_MF4\0" + /* 76317 */ "PseudoVSUXSEG3EI8_V_MF4_MF4\0" + /* 76345 */ "PseudoVLOXSEG4EI8_V_MF4_MF4\0" + /* 76373 */ "PseudoVSOXSEG4EI8_V_MF4_MF4\0" + /* 76401 */ "PseudoVLUXSEG4EI8_V_MF4_MF4\0" + /* 76429 */ "PseudoVSUXSEG4EI8_V_MF4_MF4\0" + /* 76457 */ "PseudoVLOXSEG5EI8_V_MF4_MF4\0" + /* 76485 */ "PseudoVSOXSEG5EI8_V_MF4_MF4\0" + /* 76513 */ "PseudoVLUXSEG5EI8_V_MF4_MF4\0" + /* 76541 */ "PseudoVSUXSEG5EI8_V_MF4_MF4\0" + /* 76569 */ "PseudoVLOXSEG6EI8_V_MF4_MF4\0" + /* 76597 */ "PseudoVSOXSEG6EI8_V_MF4_MF4\0" + /* 76625 */ "PseudoVLUXSEG6EI8_V_MF4_MF4\0" + /* 76653 */ "PseudoVSUXSEG6EI8_V_MF4_MF4\0" + /* 76681 */ "PseudoVLOXSEG7EI8_V_MF4_MF4\0" + /* 76709 */ "PseudoVSOXSEG7EI8_V_MF4_MF4\0" + /* 76737 */ "PseudoVLUXSEG7EI8_V_MF4_MF4\0" + /* 76765 */ "PseudoVSUXSEG7EI8_V_MF4_MF4\0" + /* 76793 */ "PseudoVLOXSEG8EI8_V_MF4_MF4\0" + /* 76821 */ "PseudoVSOXSEG8EI8_V_MF4_MF4\0" + /* 76849 */ "PseudoVLUXSEG8EI8_V_MF4_MF4\0" + /* 76877 */ "PseudoVSUXSEG8EI8_V_MF4_MF4\0" + /* 76905 */ "PseudoVLOXEI8_V_MF4_MF4\0" + /* 76929 */ "PseudoVSOXEI8_V_MF4_MF4\0" + /* 76953 */ "PseudoVLUXEI8_V_MF4_MF4\0" + /* 76977 */ "PseudoVSUXEI8_V_MF4_MF4\0" + /* 77001 */ "PseudoVSPILL4_MF4\0" + /* 77019 */ "PseudoVRELOAD5_MF4\0" + /* 77038 */ "PseudoVSPILL5_MF4\0" + /* 77056 */ "PseudoVFSUB_VF16_MF4\0" + /* 77077 */ "PseudoVFMSUB_VF16_MF4\0" + /* 77099 */ "PseudoVFNMSUB_VF16_MF4\0" + /* 77122 */ "PseudoVFRSUB_VF16_MF4\0" + /* 77144 */ "PseudoVFWSUB_VF16_MF4\0" + /* 77166 */ "PseudoVFMSAC_VF16_MF4\0" + /* 77188 */ "PseudoVFNMSAC_VF16_MF4\0" + /* 77211 */ "PseudoVFWNMSAC_VF16_MF4\0" + /* 77235 */ "PseudoVFWMSAC_VF16_MF4\0" + /* 77258 */ "PseudoVFMACC_VF16_MF4\0" + /* 77280 */ "PseudoVFNMACC_VF16_MF4\0" + /* 77303 */ "PseudoVFWNMACC_VF16_MF4\0" + /* 77327 */ "PseudoVFWMACC_VF16_MF4\0" + /* 77350 */ "PseudoVFADD_VF16_MF4\0" + /* 77371 */ "PseudoVFMADD_VF16_MF4\0" + /* 77393 */ "PseudoVFNMADD_VF16_MF4\0" + /* 77416 */ "PseudoVFWADD_VF16_MF4\0" + /* 77438 */ "PseudoVMFGE_VF16_MF4\0" + /* 77459 */ "PseudoVMFLE_VF16_MF4\0" + /* 77480 */ "PseudoVMFNE_VF16_MF4\0" + /* 77501 */ "PseudoVFSGNJ_VF16_MF4\0" + /* 77523 */ "PseudoVFMUL_VF16_MF4\0" + /* 77544 */ "PseudoVFWMUL_VF16_MF4\0" + /* 77566 */ "PseudoVFMIN_VF16_MF4\0" + /* 77587 */ "PseudoVFSGNJN_VF16_MF4\0" + /* 77610 */ "PseudoVFSLIDE1DOWN_VF16_MF4\0" + /* 77638 */ "PseudoVFSLIDE1UP_VF16_MF4\0" + /* 77664 */ "PseudoVMFEQ_VF16_MF4\0" + /* 77685 */ "PseudoVMFGT_VF16_MF4\0" + /* 77706 */ "PseudoVMFLT_VF16_MF4\0" + /* 77727 */ "PseudoVFDIV_VF16_MF4\0" + /* 77748 */ "PseudoVFRDIV_VF16_MF4\0" + /* 77770 */ "PseudoVFMAX_VF16_MF4\0" + /* 77791 */ "PseudoVFSGNJX_VF16_MF4\0" + /* 77814 */ "PseudoVFWSUB_WF16_MF4\0" + /* 77836 */ "PseudoVFWADD_WF16_MF4\0" + /* 77858 */ "PseudoVFMV_S_F16_MF4\0" + /* 77879 */ "PseudoVFMV_V_F16_MF4\0" + /* 77900 */ "PseudoVRELOAD6_MF4\0" + /* 77919 */ "PseudoVSPILL6_MF4\0" + /* 77937 */ "PseudoVRELOAD7_MF4\0" + /* 77956 */ "PseudoVSPILL7_MF4\0" + /* 77974 */ "PseudoVRELOAD8_MF4\0" + /* 77993 */ "PseudoVRGATHEREI16_VV_MF8_MF4\0" + /* 78023 */ "PseudoVLOXSEG2EI8_V_MF8_MF4\0" + /* 78051 */ "PseudoVSOXSEG2EI8_V_MF8_MF4\0" + /* 78079 */ "PseudoVLUXSEG2EI8_V_MF8_MF4\0" + /* 78107 */ "PseudoVSUXSEG2EI8_V_MF8_MF4\0" + /* 78135 */ "PseudoVLOXSEG3EI8_V_MF8_MF4\0" + /* 78163 */ "PseudoVSOXSEG3EI8_V_MF8_MF4\0" + /* 78191 */ "PseudoVLUXSEG3EI8_V_MF8_MF4\0" + /* 78219 */ "PseudoVSUXSEG3EI8_V_MF8_MF4\0" + /* 78247 */ "PseudoVLOXSEG4EI8_V_MF8_MF4\0" + /* 78275 */ "PseudoVSOXSEG4EI8_V_MF8_MF4\0" + /* 78303 */ "PseudoVLUXSEG4EI8_V_MF8_MF4\0" + /* 78331 */ "PseudoVSUXSEG4EI8_V_MF8_MF4\0" + /* 78359 */ "PseudoVLOXSEG5EI8_V_MF8_MF4\0" + /* 78387 */ "PseudoVSOXSEG5EI8_V_MF8_MF4\0" + /* 78415 */ "PseudoVLUXSEG5EI8_V_MF8_MF4\0" + /* 78443 */ "PseudoVSUXSEG5EI8_V_MF8_MF4\0" + /* 78471 */ "PseudoVLOXSEG6EI8_V_MF8_MF4\0" + /* 78499 */ "PseudoVSOXSEG6EI8_V_MF8_MF4\0" + /* 78527 */ "PseudoVLUXSEG6EI8_V_MF8_MF4\0" + /* 78555 */ "PseudoVSUXSEG6EI8_V_MF8_MF4\0" + /* 78583 */ "PseudoVLOXSEG7EI8_V_MF8_MF4\0" + /* 78611 */ "PseudoVSOXSEG7EI8_V_MF8_MF4\0" + /* 78639 */ "PseudoVLUXSEG7EI8_V_MF8_MF4\0" + /* 78667 */ "PseudoVSUXSEG7EI8_V_MF8_MF4\0" + /* 78695 */ "PseudoVLOXSEG8EI8_V_MF8_MF4\0" + /* 78723 */ "PseudoVSOXSEG8EI8_V_MF8_MF4\0" + /* 78751 */ "PseudoVLUXSEG8EI8_V_MF8_MF4\0" + /* 78779 */ "PseudoVSUXSEG8EI8_V_MF8_MF4\0" + /* 78807 */ "PseudoVLOXEI8_V_MF8_MF4\0" + /* 78831 */ "PseudoVSOXEI8_V_MF8_MF4\0" + /* 78855 */ "PseudoVLUXEI8_V_MF8_MF4\0" + /* 78879 */ "PseudoVSUXEI8_V_MF8_MF4\0" + /* 78903 */ "PseudoVSPILL8_MF4\0" + /* 78921 */ "PseudoVSSRA_VI_MF4\0" + /* 78940 */ "PseudoVSRA_VI_MF4\0" + /* 78958 */ "PseudoVRSUB_VI_MF4\0" + /* 78977 */ "PseudoVMADC_VI_MF4\0" + /* 78996 */ "PseudoVSADD_VI_MF4\0" + /* 79015 */ "PseudoVADD_VI_MF4\0" + /* 79033 */ "PseudoVAND_VI_MF4\0" + /* 79051 */ "PseudoVMSLE_VI_MF4\0" + /* 79070 */ "PseudoVMSNE_VI_MF4\0" + /* 79089 */ "PseudoVSLL_VI_MF4\0" + /* 79107 */ "PseudoVSSRL_VI_MF4\0" + /* 79126 */ "PseudoVSRL_VI_MF4\0" + /* 79144 */ "PseudoVSLIDEDOWN_VI_MF4\0" + /* 79168 */ "PseudoVSLIDEUP_VI_MF4\0" + /* 79190 */ "PseudoVMSEQ_VI_MF4\0" + /* 79209 */ "PseudoVRGATHER_VI_MF4\0" + /* 79231 */ "PseudoVOR_VI_MF4\0" + /* 79248 */ "PseudoVXOR_VI_MF4\0" + /* 79266 */ "PseudoVMSGT_VI_MF4\0" + /* 79285 */ "PseudoVSADDU_VI_MF4\0" + /* 79305 */ "PseudoVMSLEU_VI_MF4\0" + /* 79325 */ "PseudoVMSGTU_VI_MF4\0" + /* 79345 */ "PseudoVNSRA_WI_MF4\0" + /* 79364 */ "PseudoVNSRL_WI_MF4\0" + /* 79383 */ "PseudoVNCLIP_WI_MF4\0" + /* 79403 */ "PseudoVNCLIPU_WI_MF4\0" + /* 79424 */ "PseudoVMV_V_I_MF4\0" + /* 79442 */ "PseudoVFMERGE_VF32M_MF4\0" + /* 79466 */ "PseudoVFMERGE_VF64M_MF4\0" + /* 79490 */ "PseudoVFMERGE_VF16M_MF4\0" + /* 79514 */ "PseudoVMADC_VIM_MF4\0" + /* 79534 */ "PseudoVADC_VIM_MF4\0" + /* 79553 */ "PseudoVMERGE_VIM_MF4\0" + /* 79574 */ "PseudoVMAND_MM_MF4\0" + /* 79593 */ "PseudoVMNAND_MM_MF4\0" + /* 79613 */ "PseudoVMANDN_MM_MF4\0" + /* 79633 */ "PseudoVMORN_MM_MF4\0" + /* 79652 */ "PseudoVMOR_MM_MF4\0" + /* 79670 */ "PseudoVMNOR_MM_MF4\0" + /* 79689 */ "PseudoVMXNOR_MM_MF4\0" + /* 79709 */ "PseudoVMXOR_MM_MF4\0" + /* 79728 */ "PseudoVMSBC_VVM_MF4\0" + /* 79748 */ "PseudoVSBC_VVM_MF4\0" + /* 79767 */ "PseudoVMADC_VVM_MF4\0" + /* 79787 */ "PseudoVADC_VVM_MF4\0" + /* 79806 */ "PseudoVMERGE_VVM_MF4\0" + /* 79827 */ "PseudoVCOMPRESS_VM_MF4\0" + /* 79850 */ "PseudoVMSBC_VXM_MF4\0" + /* 79870 */ "PseudoVSBC_VXM_MF4\0" + /* 79889 */ "PseudoVMADC_VXM_MF4\0" + /* 79909 */ "PseudoVADC_VXM_MF4\0" + /* 79928 */ "PseudoVMERGE_VXM_MF4\0" + /* 79949 */ "PseudoVIOTA_M_MF4\0" + /* 79967 */ "PseudoVREDAND_VS_MF4\0" + /* 79988 */ "PseudoVREDSUM_VS_MF4\0" + /* 80009 */ "PseudoVWREDSUM_VS_MF4\0" + /* 80031 */ "PseudoVFREDOSUM_VS_MF4\0" + /* 80054 */ "PseudoVFWREDOSUM_VS_MF4\0" + /* 80078 */ "PseudoVFREDUSUM_VS_MF4\0" + /* 80101 */ "PseudoVFWREDUSUM_VS_MF4\0" + /* 80125 */ "PseudoVFREDMIN_VS_MF4\0" + /* 80147 */ "PseudoVREDMIN_VS_MF4\0" + /* 80168 */ "PseudoVREDOR_VS_MF4\0" + /* 80188 */ "PseudoVREDXOR_VS_MF4\0" + /* 80209 */ "PseudoVWREDSUMU_VS_MF4\0" + /* 80232 */ "PseudoVREDMINU_VS_MF4\0" + /* 80254 */ "PseudoVREDMAXU_VS_MF4\0" + /* 80276 */ "PseudoVFREDMAX_VS_MF4\0" + /* 80298 */ "PseudoVREDMAX_VS_MF4\0" + /* 80319 */ "PseudoVFMV_F32_S_MF4\0" + /* 80340 */ "PseudoVFMV_F64_S_MF4\0" + /* 80361 */ "PseudoVFMV_F16_S_MF4\0" + /* 80382 */ "PseudoVMV_X_S_MF4\0" + /* 80400 */ "PseudoVSSRA_VV_MF4\0" + /* 80419 */ "PseudoVSRA_VV_MF4\0" + /* 80437 */ "PseudoVASUB_VV_MF4\0" + /* 80456 */ "PseudoVFSUB_VV_MF4\0" + /* 80475 */ "PseudoVFMSUB_VV_MF4\0" + /* 80495 */ "PseudoVFNMSUB_VV_MF4\0" + /* 80516 */ "PseudoVNMSUB_VV_MF4\0" + /* 80536 */ "PseudoVSSUB_VV_MF4\0" + /* 80555 */ "PseudoVSUB_VV_MF4\0" + /* 80573 */ "PseudoVFWSUB_VV_MF4\0" + /* 80593 */ "PseudoVWSUB_VV_MF4\0" + /* 80612 */ "PseudoVFMSAC_VV_MF4\0" + /* 80632 */ "PseudoVFNMSAC_VV_MF4\0" + /* 80653 */ "PseudoVNMSAC_VV_MF4\0" + /* 80673 */ "PseudoVFWNMSAC_VV_MF4\0" + /* 80695 */ "PseudoVFWMSAC_VV_MF4\0" + /* 80716 */ "PseudoVMSBC_VV_MF4\0" + /* 80735 */ "PseudoVFMACC_VV_MF4\0" + /* 80755 */ "PseudoVFNMACC_VV_MF4\0" + /* 80776 */ "PseudoVFWNMACC_VV_MF4\0" + /* 80798 */ "PseudoVMACC_VV_MF4\0" + /* 80817 */ "PseudoVFWMACC_VV_MF4\0" + /* 80838 */ "PseudoVWMACC_VV_MF4\0" + /* 80858 */ "PseudoVMADC_VV_MF4\0" + /* 80877 */ "PseudoVAADD_VV_MF4\0" + /* 80896 */ "PseudoVFADD_VV_MF4\0" + /* 80915 */ "PseudoVFMADD_VV_MF4\0" + /* 80935 */ "PseudoVFNMADD_VV_MF4\0" + /* 80956 */ "PseudoVMADD_VV_MF4\0" + /* 80975 */ "PseudoVSADD_VV_MF4\0" + /* 80994 */ "PseudoVADD_VV_MF4\0" + /* 81012 */ "PseudoVFWADD_VV_MF4\0" + /* 81032 */ "PseudoVWADD_VV_MF4\0" + /* 81051 */ "PseudoVAND_VV_MF4\0" + /* 81069 */ "PseudoVMFLE_VV_MF4\0" + /* 81088 */ "PseudoVMSLE_VV_MF4\0" + /* 81107 */ "PseudoVMFNE_VV_MF4\0" + /* 81126 */ "PseudoVMSNE_VV_MF4\0" + /* 81145 */ "PseudoVMULH_VV_MF4\0" + /* 81164 */ "PseudoVFSGNJ_VV_MF4\0" + /* 81184 */ "PseudoVSLL_VV_MF4\0" + /* 81202 */ "PseudoVSSRL_VV_MF4\0" + /* 81221 */ "PseudoVSRL_VV_MF4\0" + /* 81239 */ "PseudoVFMUL_VV_MF4\0" + /* 81258 */ "PseudoVSMUL_VV_MF4\0" + /* 81277 */ "PseudoVMUL_VV_MF4\0" + /* 81295 */ "PseudoVFWMUL_VV_MF4\0" + /* 81315 */ "PseudoVWMUL_VV_MF4\0" + /* 81334 */ "PseudoVREM_VV_MF4\0" + /* 81352 */ "PseudoVFMIN_VV_MF4\0" + /* 81371 */ "PseudoVMIN_VV_MF4\0" + /* 81389 */ "PseudoVFSGNJN_VV_MF4\0" + /* 81410 */ "PseudoVMFEQ_VV_MF4\0" + /* 81429 */ "PseudoVMSEQ_VV_MF4\0" + /* 81448 */ "PseudoVRGATHER_VV_MF4\0" + /* 81470 */ "PseudoVOR_VV_MF4\0" + /* 81487 */ "PseudoVXOR_VV_MF4\0" + /* 81505 */ "PseudoVMFLT_VV_MF4\0" + /* 81524 */ "PseudoVMSLT_VV_MF4\0" + /* 81543 */ "PseudoVASUBU_VV_MF4\0" + /* 81563 */ "PseudoVSSUBU_VV_MF4\0" + /* 81583 */ "PseudoVWSUBU_VV_MF4\0" + /* 81603 */ "PseudoVWMACCU_VV_MF4\0" + /* 81624 */ "PseudoVAADDU_VV_MF4\0" + /* 81644 */ "PseudoVSADDU_VV_MF4\0" + /* 81664 */ "PseudoVWADDU_VV_MF4\0" + /* 81684 */ "PseudoVMSLEU_VV_MF4\0" + /* 81704 */ "PseudoVMULHU_VV_MF4\0" + /* 81724 */ "PseudoVWMULU_VV_MF4\0" + /* 81744 */ "PseudoVREMU_VV_MF4\0" + /* 81763 */ "PseudoVMINU_VV_MF4\0" + /* 81782 */ "PseudoVWMACCSU_VV_MF4\0" + /* 81804 */ "PseudoVMULHSU_VV_MF4\0" + /* 81825 */ "PseudoVWMULSU_VV_MF4\0" + /* 81846 */ "PseudoVMSLTU_VV_MF4\0" + /* 81866 */ "PseudoVDIVU_VV_MF4\0" + /* 81885 */ "PseudoVMAXU_VV_MF4\0" + /* 81904 */ "PseudoVFDIV_VV_MF4\0" + /* 81923 */ "PseudoVDIV_VV_MF4\0" + /* 81941 */ "PseudoVFMAX_VV_MF4\0" + /* 81960 */ "PseudoVMAX_VV_MF4\0" + /* 81978 */ "PseudoVFSGNJX_VV_MF4\0" + /* 81999 */ "PseudoVNSRA_WV_MF4\0" + /* 82018 */ "PseudoVFWSUB_WV_MF4\0" + /* 82038 */ "PseudoVWSUB_WV_MF4\0" + /* 82057 */ "PseudoVFWADD_WV_MF4\0" + /* 82077 */ "PseudoVWADD_WV_MF4\0" + /* 82096 */ "PseudoVNSRL_WV_MF4\0" + /* 82115 */ "PseudoVNCLIP_WV_MF4\0" + /* 82135 */ "PseudoVWSUBU_WV_MF4\0" + /* 82155 */ "PseudoVWADDU_WV_MF4\0" + /* 82175 */ "PseudoVNCLIPU_WV_MF4\0" + /* 82196 */ "PseudoVLSEG2E16_V_MF4\0" + /* 82218 */ "PseudoVLSSEG2E16_V_MF4\0" + /* 82241 */ "PseudoVSSSEG2E16_V_MF4\0" + /* 82264 */ "PseudoVSSEG2E16_V_MF4\0" + /* 82286 */ "PseudoVLSEG3E16_V_MF4\0" + /* 82308 */ "PseudoVLSSEG3E16_V_MF4\0" + /* 82331 */ "PseudoVSSSEG3E16_V_MF4\0" + /* 82354 */ "PseudoVSSEG3E16_V_MF4\0" + /* 82376 */ "PseudoVLSEG4E16_V_MF4\0" + /* 82398 */ "PseudoVLSSEG4E16_V_MF4\0" + /* 82421 */ "PseudoVSSSEG4E16_V_MF4\0" + /* 82444 */ "PseudoVSSEG4E16_V_MF4\0" + /* 82466 */ "PseudoVLSEG5E16_V_MF4\0" + /* 82488 */ "PseudoVLSSEG5E16_V_MF4\0" + /* 82511 */ "PseudoVSSSEG5E16_V_MF4\0" + /* 82534 */ "PseudoVSSEG5E16_V_MF4\0" + /* 82556 */ "PseudoVLSEG6E16_V_MF4\0" + /* 82578 */ "PseudoVLSSEG6E16_V_MF4\0" + /* 82601 */ "PseudoVSSSEG6E16_V_MF4\0" + /* 82624 */ "PseudoVSSEG6E16_V_MF4\0" + /* 82646 */ "PseudoVLSEG7E16_V_MF4\0" + /* 82668 */ "PseudoVLSSEG7E16_V_MF4\0" + /* 82691 */ "PseudoVSSSEG7E16_V_MF4\0" + /* 82714 */ "PseudoVSSEG7E16_V_MF4\0" + /* 82736 */ "PseudoVLSEG8E16_V_MF4\0" + /* 82758 */ "PseudoVLSSEG8E16_V_MF4\0" + /* 82781 */ "PseudoVSSSEG8E16_V_MF4\0" + /* 82804 */ "PseudoVSSEG8E16_V_MF4\0" + /* 82826 */ "PseudoVLE16_V_MF4\0" + /* 82844 */ "PseudoVLSE16_V_MF4\0" + /* 82863 */ "PseudoVSSE16_V_MF4\0" + /* 82882 */ "PseudoVSE16_V_MF4\0" + /* 82900 */ "PseudoVFREC7_V_MF4\0" + /* 82919 */ "PseudoVFRSQRT7_V_MF4\0" + /* 82940 */ "PseudoVLSEG2E8_V_MF4\0" + /* 82961 */ "PseudoVLSSEG2E8_V_MF4\0" + /* 82983 */ "PseudoVSSSEG2E8_V_MF4\0" + /* 83005 */ "PseudoVSSEG2E8_V_MF4\0" + /* 83026 */ "PseudoVLSEG3E8_V_MF4\0" + /* 83047 */ "PseudoVLSSEG3E8_V_MF4\0" + /* 83069 */ "PseudoVSSSEG3E8_V_MF4\0" + /* 83091 */ "PseudoVSSEG3E8_V_MF4\0" + /* 83112 */ "PseudoVLSEG4E8_V_MF4\0" + /* 83133 */ "PseudoVLSSEG4E8_V_MF4\0" + /* 83155 */ "PseudoVSSSEG4E8_V_MF4\0" + /* 83177 */ "PseudoVSSEG4E8_V_MF4\0" + /* 83198 */ "PseudoVLSEG5E8_V_MF4\0" + /* 83219 */ "PseudoVLSSEG5E8_V_MF4\0" + /* 83241 */ "PseudoVSSSEG5E8_V_MF4\0" + /* 83263 */ "PseudoVSSEG5E8_V_MF4\0" + /* 83284 */ "PseudoVLSEG6E8_V_MF4\0" + /* 83305 */ "PseudoVLSSEG6E8_V_MF4\0" + /* 83327 */ "PseudoVSSSEG6E8_V_MF4\0" + /* 83349 */ "PseudoVSSEG6E8_V_MF4\0" + /* 83370 */ "PseudoVLSEG7E8_V_MF4\0" + /* 83391 */ "PseudoVLSSEG7E8_V_MF4\0" + /* 83413 */ "PseudoVSSSEG7E8_V_MF4\0" + /* 83435 */ "PseudoVSSEG7E8_V_MF4\0" + /* 83456 */ "PseudoVLSEG8E8_V_MF4\0" + /* 83477 */ "PseudoVLSSEG8E8_V_MF4\0" + /* 83499 */ "PseudoVSSSEG8E8_V_MF4\0" + /* 83521 */ "PseudoVSSEG8E8_V_MF4\0" + /* 83542 */ "PseudoVLE8_V_MF4\0" + /* 83559 */ "PseudoVLSE8_V_MF4\0" + /* 83577 */ "PseudoVSSE8_V_MF4\0" + /* 83595 */ "PseudoVSE8_V_MF4\0" + /* 83612 */ "PseudoVID_V_MF4\0" + /* 83628 */ "PseudoVLSEG2E16FF_V_MF4\0" + /* 83652 */ "PseudoVLSEG3E16FF_V_MF4\0" + /* 83676 */ "PseudoVLSEG4E16FF_V_MF4\0" + /* 83700 */ "PseudoVLSEG5E16FF_V_MF4\0" + /* 83724 */ "PseudoVLSEG6E16FF_V_MF4\0" + /* 83748 */ "PseudoVLSEG7E16FF_V_MF4\0" + /* 83772 */ "PseudoVLSEG8E16FF_V_MF4\0" + /* 83796 */ "PseudoVLE16FF_V_MF4\0" + /* 83816 */ "PseudoVLSEG2E8FF_V_MF4\0" + /* 83839 */ "PseudoVLSEG3E8FF_V_MF4\0" + /* 83862 */ "PseudoVLSEG4E8FF_V_MF4\0" + /* 83885 */ "PseudoVLSEG5E8FF_V_MF4\0" + /* 83908 */ "PseudoVLSEG6E8FF_V_MF4\0" + /* 83931 */ "PseudoVLSEG7E8FF_V_MF4\0" + /* 83954 */ "PseudoVLSEG8E8FF_V_MF4\0" + /* 83977 */ "PseudoVLE8FF_V_MF4\0" + /* 83996 */ "PseudoVFWCVT_F_F_V_MF4\0" + /* 84019 */ "PseudoVFCVT_XU_F_V_MF4\0" + /* 84042 */ "PseudoVFWCVT_XU_F_V_MF4\0" + /* 84066 */ "PseudoVFCVT_RTZ_XU_F_V_MF4\0" + /* 84093 */ "PseudoVFWCVT_RTZ_XU_F_V_MF4\0" + /* 84121 */ "PseudoVFCVT_X_F_V_MF4\0" + /* 84143 */ "PseudoVFWCVT_X_F_V_MF4\0" + /* 84166 */ "PseudoVFCVT_RTZ_X_F_V_MF4\0" + /* 84192 */ "PseudoVFWCVT_RTZ_X_F_V_MF4\0" + /* 84219 */ "PseudoVFCLASS_V_MF4\0" + /* 84239 */ "PseudoVFSQRT_V_MF4\0" + /* 84258 */ "PseudoVFCVT_F_XU_V_MF4\0" + /* 84281 */ "PseudoVFWCVT_F_XU_V_MF4\0" + /* 84305 */ "PseudoVMV_V_V_MF4\0" + /* 84323 */ "PseudoVFCVT_F_X_V_MF4\0" + /* 84345 */ "PseudoVFWCVT_F_X_V_MF4\0" + /* 84368 */ "PseudoVFNCVT_ROD_F_F_W_MF4\0" + /* 84395 */ "PseudoVFNCVT_F_F_W_MF4\0" + /* 84418 */ "PseudoVFNCVT_XU_F_W_MF4\0" + /* 84442 */ "PseudoVFNCVT_RTZ_XU_F_W_MF4\0" + /* 84470 */ "PseudoVFNCVT_X_F_W_MF4\0" + /* 84493 */ "PseudoVFNCVT_RTZ_X_F_W_MF4\0" + /* 84520 */ "PseudoVFNCVT_F_XU_W_MF4\0" + /* 84544 */ "PseudoVFNCVT_F_X_W_MF4\0" + /* 84567 */ "PseudoVSSRA_VX_MF4\0" + /* 84586 */ "PseudoVSRA_VX_MF4\0" + /* 84604 */ "PseudoVASUB_VX_MF4\0" + /* 84623 */ "PseudoVNMSUB_VX_MF4\0" + /* 84643 */ "PseudoVRSUB_VX_MF4\0" + /* 84662 */ "PseudoVSSUB_VX_MF4\0" + /* 84681 */ "PseudoVSUB_VX_MF4\0" + /* 84699 */ "PseudoVWSUB_VX_MF4\0" + /* 84718 */ "PseudoVNMSAC_VX_MF4\0" + /* 84738 */ "PseudoVMSBC_VX_MF4\0" + /* 84757 */ "PseudoVMACC_VX_MF4\0" + /* 84776 */ "PseudoVWMACC_VX_MF4\0" + /* 84796 */ "PseudoVMADC_VX_MF4\0" + /* 84815 */ "PseudoVAADD_VX_MF4\0" + /* 84834 */ "PseudoVMADD_VX_MF4\0" + /* 84853 */ "PseudoVSADD_VX_MF4\0" + /* 84872 */ "PseudoVADD_VX_MF4\0" + /* 84890 */ "PseudoVWADD_VX_MF4\0" + /* 84909 */ "PseudoVAND_VX_MF4\0" + /* 84927 */ "PseudoVMSLE_VX_MF4\0" + /* 84946 */ "PseudoVMSNE_VX_MF4\0" + /* 84965 */ "PseudoVMULH_VX_MF4\0" + /* 84984 */ "PseudoVSLL_VX_MF4\0" + /* 85002 */ "PseudoVSSRL_VX_MF4\0" + /* 85021 */ "PseudoVSRL_VX_MF4\0" + /* 85039 */ "PseudoVSMUL_VX_MF4\0" + /* 85058 */ "PseudoVMUL_VX_MF4\0" + /* 85076 */ "PseudoVWMUL_VX_MF4\0" + /* 85095 */ "PseudoVREM_VX_MF4\0" + /* 85113 */ "PseudoVMIN_VX_MF4\0" + /* 85131 */ "PseudoVSLIDE1DOWN_VX_MF4\0" + /* 85156 */ "PseudoVSLIDEDOWN_VX_MF4\0" + /* 85180 */ "PseudoVSLIDE1UP_VX_MF4\0" + /* 85203 */ "PseudoVSLIDEUP_VX_MF4\0" + /* 85225 */ "PseudoVMSEQ_VX_MF4\0" + /* 85244 */ "PseudoVRGATHER_VX_MF4\0" + /* 85266 */ "PseudoVOR_VX_MF4\0" + /* 85283 */ "PseudoVXOR_VX_MF4\0" + /* 85301 */ "PseudoVWMACCUS_VX_MF4\0" + /* 85323 */ "PseudoVMSGT_VX_MF4\0" + /* 85342 */ "PseudoVMSLT_VX_MF4\0" + /* 85361 */ "PseudoVASUBU_VX_MF4\0" + /* 85381 */ "PseudoVSSUBU_VX_MF4\0" + /* 85401 */ "PseudoVWSUBU_VX_MF4\0" + /* 85421 */ "PseudoVWMACCU_VX_MF4\0" + /* 85442 */ "PseudoVAADDU_VX_MF4\0" + /* 85462 */ "PseudoVSADDU_VX_MF4\0" + /* 85482 */ "PseudoVWADDU_VX_MF4\0" + /* 85502 */ "PseudoVMSLEU_VX_MF4\0" + /* 85522 */ "PseudoVMULHU_VX_MF4\0" + /* 85542 */ "PseudoVWMULU_VX_MF4\0" + /* 85562 */ "PseudoVREMU_VX_MF4\0" + /* 85581 */ "PseudoVMINU_VX_MF4\0" + /* 85600 */ "PseudoVWMACCSU_VX_MF4\0" + /* 85622 */ "PseudoVMULHSU_VX_MF4\0" + /* 85643 */ "PseudoVWMULSU_VX_MF4\0" + /* 85664 */ "PseudoVMSGTU_VX_MF4\0" + /* 85684 */ "PseudoVMSLTU_VX_MF4\0" + /* 85704 */ "PseudoVDIVU_VX_MF4\0" + /* 85723 */ "PseudoVMAXU_VX_MF4\0" + /* 85742 */ "PseudoVDIV_VX_MF4\0" + /* 85760 */ "PseudoVMAX_VX_MF4\0" + /* 85778 */ "PseudoVNSRA_WX_MF4\0" + /* 85797 */ "PseudoVWSUB_WX_MF4\0" + /* 85816 */ "PseudoVWADD_WX_MF4\0" + /* 85835 */ "PseudoVNSRL_WX_MF4\0" + /* 85854 */ "PseudoVNCLIP_WX_MF4\0" + /* 85874 */ "PseudoVWSUBU_WX_MF4\0" + /* 85894 */ "PseudoVWADDU_WX_MF4\0" + /* 85914 */ "PseudoVNCLIPU_WX_MF4\0" + /* 85935 */ "PseudoVMV_S_X_MF4\0" + /* 85953 */ "PseudoVMV_V_X_MF4\0" + /* 85971 */ "VSEXT_VF4\0" + /* 85981 */ "VZEXT_VF4\0" + /* 85991 */ "PseudoVLOXSEG2EI16_V_M1_M4\0" + /* 86018 */ "PseudoVSOXSEG2EI16_V_M1_M4\0" + /* 86045 */ "PseudoVLUXSEG2EI16_V_M1_M4\0" + /* 86072 */ "PseudoVSUXSEG2EI16_V_M1_M4\0" + /* 86099 */ "PseudoVLOXEI16_V_M1_M4\0" + /* 86122 */ "PseudoVSOXEI16_V_M1_M4\0" + /* 86145 */ "PseudoVLUXEI16_V_M1_M4\0" + /* 86168 */ "PseudoVSUXEI16_V_M1_M4\0" + /* 86191 */ "PseudoVLOXSEG2EI8_V_M1_M4\0" + /* 86217 */ "PseudoVSOXSEG2EI8_V_M1_M4\0" + /* 86243 */ "PseudoVLUXSEG2EI8_V_M1_M4\0" + /* 86269 */ "PseudoVSUXSEG2EI8_V_M1_M4\0" + /* 86295 */ "PseudoVLOXEI8_V_M1_M4\0" + /* 86317 */ "PseudoVSOXEI8_V_M1_M4\0" + /* 86339 */ "PseudoVLUXEI8_V_M1_M4\0" + /* 86361 */ "PseudoVSUXEI8_V_M1_M4\0" + /* 86383 */ "PseudoVFSUB_VF32_M4\0" + /* 86403 */ "PseudoVFMSUB_VF32_M4\0" + /* 86424 */ "PseudoVFNMSUB_VF32_M4\0" + /* 86446 */ "PseudoVFRSUB_VF32_M4\0" + /* 86467 */ "PseudoVFWSUB_VF32_M4\0" + /* 86488 */ "PseudoVFMSAC_VF32_M4\0" + /* 86509 */ "PseudoVFNMSAC_VF32_M4\0" + /* 86531 */ "PseudoVFWNMSAC_VF32_M4\0" + /* 86554 */ "PseudoVFWMSAC_VF32_M4\0" + /* 86576 */ "PseudoVFMACC_VF32_M4\0" + /* 86597 */ "PseudoVFNMACC_VF32_M4\0" + /* 86619 */ "PseudoVFWNMACC_VF32_M4\0" + /* 86642 */ "PseudoVFWMACC_VF32_M4\0" + /* 86664 */ "PseudoVFADD_VF32_M4\0" + /* 86684 */ "PseudoVFMADD_VF32_M4\0" + /* 86705 */ "PseudoVFNMADD_VF32_M4\0" + /* 86727 */ "PseudoVFWADD_VF32_M4\0" + /* 86748 */ "PseudoVMFGE_VF32_M4\0" + /* 86768 */ "PseudoVMFLE_VF32_M4\0" + /* 86788 */ "PseudoVMFNE_VF32_M4\0" + /* 86808 */ "PseudoVFSGNJ_VF32_M4\0" + /* 86829 */ "PseudoVFMUL_VF32_M4\0" + /* 86849 */ "PseudoVFWMUL_VF32_M4\0" + /* 86870 */ "PseudoVFMIN_VF32_M4\0" + /* 86890 */ "PseudoVFSGNJN_VF32_M4\0" + /* 86912 */ "PseudoVFSLIDE1DOWN_VF32_M4\0" + /* 86939 */ "PseudoVFSLIDE1UP_VF32_M4\0" + /* 86964 */ "PseudoVMFEQ_VF32_M4\0" + /* 86984 */ "PseudoVMFGT_VF32_M4\0" + /* 87004 */ "PseudoVMFLT_VF32_M4\0" + /* 87024 */ "PseudoVFDIV_VF32_M4\0" + /* 87044 */ "PseudoVFRDIV_VF32_M4\0" + /* 87065 */ "PseudoVFMAX_VF32_M4\0" + /* 87085 */ "PseudoVFSGNJX_VF32_M4\0" + /* 87107 */ "PseudoVFWSUB_WF32_M4\0" + /* 87128 */ "PseudoVFWADD_WF32_M4\0" + /* 87149 */ "PseudoVFMV_S_F32_M4\0" + /* 87169 */ "PseudoVFMV_V_F32_M4\0" + /* 87189 */ "PseudoVRELOAD2_M4\0" + /* 87207 */ "PseudoVLOXSEG2EI8_V_MF2_M4\0" + /* 87234 */ "PseudoVSOXSEG2EI8_V_MF2_M4\0" + /* 87261 */ "PseudoVLUXSEG2EI8_V_MF2_M4\0" + /* 87288 */ "PseudoVSUXSEG2EI8_V_MF2_M4\0" + /* 87315 */ "PseudoVLOXEI8_V_MF2_M4\0" + /* 87338 */ "PseudoVSOXEI8_V_MF2_M4\0" + /* 87361 */ "PseudoVLUXEI8_V_MF2_M4\0" + /* 87384 */ "PseudoVSUXEI8_V_MF2_M4\0" + /* 87407 */ "PseudoVSEXT_VF2_M4\0" + /* 87426 */ "PseudoVZEXT_VF2_M4\0" + /* 87445 */ "PseudoVSPILL2_M4\0" + /* 87462 */ "PseudoVAMOADDEI64_WD_M2_M4\0" + /* 87489 */ "PseudoVAMOANDEI64_WD_M2_M4\0" + /* 87516 */ "PseudoVAMOMINEI64_WD_M2_M4\0" + /* 87543 */ "PseudoVAMOSWAPEI64_WD_M2_M4\0" + /* 87571 */ "PseudoVAMOOREI64_WD_M2_M4\0" + /* 87597 */ "PseudoVAMOXOREI64_WD_M2_M4\0" + /* 87624 */ "PseudoVAMOMINUEI64_WD_M2_M4\0" + /* 87652 */ "PseudoVAMOMAXUEI64_WD_M2_M4\0" + /* 87680 */ "PseudoVAMOMAXEI64_WD_M2_M4\0" + /* 87707 */ "PseudoVRGATHEREI16_VV_M2_M4\0" + /* 87735 */ "PseudoVLOXSEG2EI32_V_M2_M4\0" + /* 87762 */ "PseudoVSOXSEG2EI32_V_M2_M4\0" + /* 87789 */ "PseudoVLUXSEG2EI32_V_M2_M4\0" + /* 87816 */ "PseudoVSUXSEG2EI32_V_M2_M4\0" + /* 87843 */ "PseudoVLOXEI32_V_M2_M4\0" + /* 87866 */ "PseudoVSOXEI32_V_M2_M4\0" + /* 87889 */ "PseudoVLUXEI32_V_M2_M4\0" + /* 87912 */ "PseudoVSUXEI32_V_M2_M4\0" + /* 87935 */ "PseudoVLOXSEG2EI16_V_M2_M4\0" + /* 87962 */ "PseudoVSOXSEG2EI16_V_M2_M4\0" + /* 87989 */ "PseudoVLUXSEG2EI16_V_M2_M4\0" + /* 88016 */ "PseudoVSUXSEG2EI16_V_M2_M4\0" + /* 88043 */ "PseudoVLOXEI16_V_M2_M4\0" + /* 88066 */ "PseudoVSOXEI16_V_M2_M4\0" + /* 88089 */ "PseudoVLUXEI16_V_M2_M4\0" + /* 88112 */ "PseudoVSUXEI16_V_M2_M4\0" + /* 88135 */ "PseudoVLOXSEG2EI8_V_M2_M4\0" + /* 88161 */ "PseudoVSOXSEG2EI8_V_M2_M4\0" + /* 88187 */ "PseudoVLUXSEG2EI8_V_M2_M4\0" + /* 88213 */ "PseudoVSUXSEG2EI8_V_M2_M4\0" + /* 88239 */ "PseudoVLOXEI8_V_M2_M4\0" + /* 88261 */ "PseudoVSOXEI8_V_M2_M4\0" + /* 88283 */ "PseudoVLUXEI8_V_M2_M4\0" + /* 88305 */ "PseudoVSUXEI8_V_M2_M4\0" + /* 88327 */ "PseudoVFSUB_VF64_M4\0" + /* 88347 */ "PseudoVFMSUB_VF64_M4\0" + /* 88368 */ "PseudoVFNMSUB_VF64_M4\0" + /* 88390 */ "PseudoVFRSUB_VF64_M4\0" + /* 88411 */ "PseudoVFMSAC_VF64_M4\0" + /* 88432 */ "PseudoVFNMSAC_VF64_M4\0" + /* 88454 */ "PseudoVFMACC_VF64_M4\0" + /* 88475 */ "PseudoVFNMACC_VF64_M4\0" + /* 88497 */ "PseudoVFADD_VF64_M4\0" + /* 88517 */ "PseudoVFMADD_VF64_M4\0" + /* 88538 */ "PseudoVFNMADD_VF64_M4\0" + /* 88560 */ "PseudoVMFGE_VF64_M4\0" + /* 88580 */ "PseudoVMFLE_VF64_M4\0" + /* 88600 */ "PseudoVMFNE_VF64_M4\0" + /* 88620 */ "PseudoVFSGNJ_VF64_M4\0" + /* 88641 */ "PseudoVFMUL_VF64_M4\0" + /* 88661 */ "PseudoVFMIN_VF64_M4\0" + /* 88681 */ "PseudoVFSGNJN_VF64_M4\0" + /* 88703 */ "PseudoVFSLIDE1DOWN_VF64_M4\0" + /* 88730 */ "PseudoVFSLIDE1UP_VF64_M4\0" + /* 88755 */ "PseudoVMFEQ_VF64_M4\0" + /* 88775 */ "PseudoVMFGT_VF64_M4\0" + /* 88795 */ "PseudoVMFLT_VF64_M4\0" + /* 88815 */ "PseudoVFDIV_VF64_M4\0" + /* 88835 */ "PseudoVFRDIV_VF64_M4\0" + /* 88856 */ "PseudoVFMAX_VF64_M4\0" + /* 88876 */ "PseudoVFSGNJX_VF64_M4\0" + /* 88898 */ "PseudoVFMV_S_F64_M4\0" + /* 88918 */ "PseudoVFMV_V_F64_M4\0" + /* 88938 */ "PseudoVSEXT_VF4_M4\0" + /* 88957 */ "PseudoVZEXT_VF4_M4\0" + /* 88976 */ "PseudoVAMOADDEI32_WD_M4_M4\0" + /* 89003 */ "PseudoVAMOANDEI32_WD_M4_M4\0" + /* 89030 */ "PseudoVAMOMINEI32_WD_M4_M4\0" + /* 89057 */ "PseudoVAMOSWAPEI32_WD_M4_M4\0" + /* 89085 */ "PseudoVAMOOREI32_WD_M4_M4\0" + /* 89111 */ "PseudoVAMOXOREI32_WD_M4_M4\0" + /* 89138 */ "PseudoVAMOMINUEI32_WD_M4_M4\0" + /* 89166 */ "PseudoVAMOMAXUEI32_WD_M4_M4\0" + /* 89194 */ "PseudoVAMOMAXEI32_WD_M4_M4\0" + /* 89221 */ "PseudoVAMOADDEI64_WD_M4_M4\0" + /* 89248 */ "PseudoVAMOANDEI64_WD_M4_M4\0" + /* 89275 */ "PseudoVAMOMINEI64_WD_M4_M4\0" + /* 89302 */ "PseudoVAMOSWAPEI64_WD_M4_M4\0" + /* 89330 */ "PseudoVAMOOREI64_WD_M4_M4\0" + /* 89356 */ "PseudoVAMOXOREI64_WD_M4_M4\0" + /* 89383 */ "PseudoVAMOMINUEI64_WD_M4_M4\0" + /* 89411 */ "PseudoVAMOMAXUEI64_WD_M4_M4\0" + /* 89439 */ "PseudoVAMOMAXEI64_WD_M4_M4\0" + /* 89466 */ "PseudoVRGATHEREI16_VV_M4_M4\0" + /* 89494 */ "PseudoVLOXSEG2EI32_V_M4_M4\0" + /* 89521 */ "PseudoVSOXSEG2EI32_V_M4_M4\0" + /* 89548 */ "PseudoVLUXSEG2EI32_V_M4_M4\0" + /* 89575 */ "PseudoVSUXSEG2EI32_V_M4_M4\0" + /* 89602 */ "PseudoVLOXEI32_V_M4_M4\0" + /* 89625 */ "PseudoVSOXEI32_V_M4_M4\0" + /* 89648 */ "PseudoVLUXEI32_V_M4_M4\0" + /* 89671 */ "PseudoVSUXEI32_V_M4_M4\0" + /* 89694 */ "PseudoVLOXSEG2EI64_V_M4_M4\0" + /* 89721 */ "PseudoVSOXSEG2EI64_V_M4_M4\0" + /* 89748 */ "PseudoVLUXSEG2EI64_V_M4_M4\0" + /* 89775 */ "PseudoVSUXSEG2EI64_V_M4_M4\0" + /* 89802 */ "PseudoVLOXEI64_V_M4_M4\0" + /* 89825 */ "PseudoVSOXEI64_V_M4_M4\0" + /* 89848 */ "PseudoVLUXEI64_V_M4_M4\0" + /* 89871 */ "PseudoVSUXEI64_V_M4_M4\0" + /* 89894 */ "PseudoVLOXSEG2EI16_V_M4_M4\0" + /* 89921 */ "PseudoVSOXSEG2EI16_V_M4_M4\0" + /* 89948 */ "PseudoVLUXSEG2EI16_V_M4_M4\0" + /* 89975 */ "PseudoVSUXSEG2EI16_V_M4_M4\0" + /* 90002 */ "PseudoVLOXEI16_V_M4_M4\0" + /* 90025 */ "PseudoVSOXEI16_V_M4_M4\0" + /* 90048 */ "PseudoVLUXEI16_V_M4_M4\0" + /* 90071 */ "PseudoVSUXEI16_V_M4_M4\0" + /* 90094 */ "PseudoVLOXSEG2EI8_V_M4_M4\0" + /* 90120 */ "PseudoVSOXSEG2EI8_V_M4_M4\0" + /* 90146 */ "PseudoVLUXSEG2EI8_V_M4_M4\0" + /* 90172 */ "PseudoVSUXSEG2EI8_V_M4_M4\0" + /* 90198 */ "PseudoVLOXEI8_V_M4_M4\0" + /* 90220 */ "PseudoVSOXEI8_V_M4_M4\0" + /* 90242 */ "PseudoVLUXEI8_V_M4_M4\0" + /* 90264 */ "PseudoVSUXEI8_V_M4_M4\0" + /* 90286 */ "PseudoVFSUB_VF16_M4\0" + /* 90306 */ "PseudoVFMSUB_VF16_M4\0" + /* 90327 */ "PseudoVFNMSUB_VF16_M4\0" + /* 90349 */ "PseudoVFRSUB_VF16_M4\0" + /* 90370 */ "PseudoVFWSUB_VF16_M4\0" + /* 90391 */ "PseudoVFMSAC_VF16_M4\0" + /* 90412 */ "PseudoVFNMSAC_VF16_M4\0" + /* 90434 */ "PseudoVFWNMSAC_VF16_M4\0" + /* 90457 */ "PseudoVFWMSAC_VF16_M4\0" + /* 90479 */ "PseudoVFMACC_VF16_M4\0" + /* 90500 */ "PseudoVFNMACC_VF16_M4\0" + /* 90522 */ "PseudoVFWNMACC_VF16_M4\0" + /* 90545 */ "PseudoVFWMACC_VF16_M4\0" + /* 90567 */ "PseudoVFADD_VF16_M4\0" + /* 90587 */ "PseudoVFMADD_VF16_M4\0" + /* 90608 */ "PseudoVFNMADD_VF16_M4\0" + /* 90630 */ "PseudoVFWADD_VF16_M4\0" + /* 90651 */ "PseudoVMFGE_VF16_M4\0" + /* 90671 */ "PseudoVMFLE_VF16_M4\0" + /* 90691 */ "PseudoVMFNE_VF16_M4\0" + /* 90711 */ "PseudoVFSGNJ_VF16_M4\0" + /* 90732 */ "PseudoVFMUL_VF16_M4\0" + /* 90752 */ "PseudoVFWMUL_VF16_M4\0" + /* 90773 */ "PseudoVFMIN_VF16_M4\0" + /* 90793 */ "PseudoVFSGNJN_VF16_M4\0" + /* 90815 */ "PseudoVFSLIDE1DOWN_VF16_M4\0" + /* 90842 */ "PseudoVFSLIDE1UP_VF16_M4\0" + /* 90867 */ "PseudoVMFEQ_VF16_M4\0" + /* 90887 */ "PseudoVMFGT_VF16_M4\0" + /* 90907 */ "PseudoVMFLT_VF16_M4\0" + /* 90927 */ "PseudoVFDIV_VF16_M4\0" + /* 90947 */ "PseudoVFRDIV_VF16_M4\0" + /* 90968 */ "PseudoVFMAX_VF16_M4\0" + /* 90988 */ "PseudoVFSGNJX_VF16_M4\0" + /* 91010 */ "PseudoVFWSUB_WF16_M4\0" + /* 91031 */ "PseudoVFWADD_WF16_M4\0" + /* 91052 */ "PseudoVFMV_S_F16_M4\0" + /* 91072 */ "PseudoVFMV_V_F16_M4\0" + /* 91092 */ "PseudoVSEXT_VF8_M4\0" + /* 91111 */ "PseudoVZEXT_VF8_M4\0" + /* 91130 */ "PseudoVAMOADDEI32_WD_M8_M4\0" + /* 91157 */ "PseudoVAMOANDEI32_WD_M8_M4\0" + /* 91184 */ "PseudoVAMOMINEI32_WD_M8_M4\0" + /* 91211 */ "PseudoVAMOSWAPEI32_WD_M8_M4\0" + /* 91239 */ "PseudoVAMOOREI32_WD_M8_M4\0" + /* 91265 */ "PseudoVAMOXOREI32_WD_M8_M4\0" + /* 91292 */ "PseudoVAMOMINUEI32_WD_M8_M4\0" + /* 91320 */ "PseudoVAMOMAXUEI32_WD_M8_M4\0" + /* 91348 */ "PseudoVAMOMAXEI32_WD_M8_M4\0" + /* 91375 */ "PseudoVAMOADDEI16_WD_M8_M4\0" + /* 91402 */ "PseudoVAMOANDEI16_WD_M8_M4\0" + /* 91429 */ "PseudoVAMOMINEI16_WD_M8_M4\0" + /* 91456 */ "PseudoVAMOSWAPEI16_WD_M8_M4\0" + /* 91484 */ "PseudoVAMOOREI16_WD_M8_M4\0" + /* 91510 */ "PseudoVAMOXOREI16_WD_M8_M4\0" + /* 91537 */ "PseudoVAMOMINUEI16_WD_M8_M4\0" + /* 91565 */ "PseudoVAMOMAXUEI16_WD_M8_M4\0" + /* 91593 */ "PseudoVAMOMAXEI16_WD_M8_M4\0" + /* 91620 */ "PseudoVRGATHEREI16_VV_M8_M4\0" + /* 91648 */ "PseudoVLOXSEG2EI32_V_M8_M4\0" + /* 91675 */ "PseudoVSOXSEG2EI32_V_M8_M4\0" + /* 91702 */ "PseudoVLUXSEG2EI32_V_M8_M4\0" + /* 91729 */ "PseudoVSUXSEG2EI32_V_M8_M4\0" + /* 91756 */ "PseudoVLOXEI32_V_M8_M4\0" + /* 91779 */ "PseudoVSOXEI32_V_M8_M4\0" + /* 91802 */ "PseudoVLUXEI32_V_M8_M4\0" + /* 91825 */ "PseudoVSUXEI32_V_M8_M4\0" + /* 91848 */ "PseudoVLOXSEG2EI64_V_M8_M4\0" + /* 91875 */ "PseudoVSOXSEG2EI64_V_M8_M4\0" + /* 91902 */ "PseudoVLUXSEG2EI64_V_M8_M4\0" + /* 91929 */ "PseudoVSUXSEG2EI64_V_M8_M4\0" + /* 91956 */ "PseudoVLOXEI64_V_M8_M4\0" + /* 91979 */ "PseudoVSOXEI64_V_M8_M4\0" + /* 92002 */ "PseudoVLUXEI64_V_M8_M4\0" + /* 92025 */ "PseudoVSUXEI64_V_M8_M4\0" + /* 92048 */ "PseudoVLOXSEG2EI16_V_M8_M4\0" + /* 92075 */ "PseudoVSOXSEG2EI16_V_M8_M4\0" + /* 92102 */ "PseudoVLUXSEG2EI16_V_M8_M4\0" + /* 92129 */ "PseudoVSUXSEG2EI16_V_M8_M4\0" + /* 92156 */ "PseudoVLOXEI16_V_M8_M4\0" + /* 92179 */ "PseudoVSOXEI16_V_M8_M4\0" + /* 92202 */ "PseudoVLUXEI16_V_M8_M4\0" + /* 92225 */ "PseudoVSUXEI16_V_M8_M4\0" + /* 92248 */ "PseudoVRELOAD_M4\0" + /* 92265 */ "PseudoVSSRA_VI_M4\0" + /* 92283 */ "PseudoVSRA_VI_M4\0" + /* 92300 */ "PseudoVRSUB_VI_M4\0" + /* 92318 */ "PseudoVMADC_VI_M4\0" + /* 92336 */ "PseudoVSADD_VI_M4\0" + /* 92354 */ "PseudoVADD_VI_M4\0" + /* 92371 */ "PseudoVAND_VI_M4\0" + /* 92388 */ "PseudoVMSLE_VI_M4\0" + /* 92406 */ "PseudoVMSNE_VI_M4\0" + /* 92424 */ "PseudoVSLL_VI_M4\0" + /* 92441 */ "PseudoVSSRL_VI_M4\0" + /* 92459 */ "PseudoVSRL_VI_M4\0" + /* 92476 */ "PseudoVSLIDEDOWN_VI_M4\0" + /* 92499 */ "PseudoVSLIDEUP_VI_M4\0" + /* 92520 */ "PseudoVMSEQ_VI_M4\0" + /* 92538 */ "PseudoVRGATHER_VI_M4\0" + /* 92559 */ "PseudoVOR_VI_M4\0" + /* 92575 */ "PseudoVXOR_VI_M4\0" + /* 92592 */ "PseudoVMSGT_VI_M4\0" + /* 92610 */ "PseudoVSADDU_VI_M4\0" + /* 92629 */ "PseudoVMSLEU_VI_M4\0" + /* 92648 */ "PseudoVMSGTU_VI_M4\0" + /* 92667 */ "PseudoVNSRA_WI_M4\0" + /* 92685 */ "PseudoVNSRL_WI_M4\0" + /* 92703 */ "PseudoVNCLIP_WI_M4\0" + /* 92722 */ "PseudoVNCLIPU_WI_M4\0" + /* 92742 */ "PseudoVMV_V_I_M4\0" + /* 92759 */ "PseudoVSPILL_M4\0" + /* 92775 */ "PseudoVFMERGE_VF32M_M4\0" + /* 92798 */ "PseudoVFMERGE_VF64M_M4\0" + /* 92821 */ "PseudoVFMERGE_VF16M_M4\0" + /* 92844 */ "PseudoVMADC_VIM_M4\0" + /* 92863 */ "PseudoVADC_VIM_M4\0" + /* 92881 */ "PseudoVMERGE_VIM_M4\0" + /* 92901 */ "PseudoVMAND_MM_M4\0" + /* 92919 */ "PseudoVMNAND_MM_M4\0" + /* 92938 */ "PseudoVMANDN_MM_M4\0" + /* 92957 */ "PseudoVMORN_MM_M4\0" + /* 92975 */ "PseudoVMOR_MM_M4\0" + /* 92992 */ "PseudoVMNOR_MM_M4\0" + /* 93010 */ "PseudoVMXNOR_MM_M4\0" + /* 93029 */ "PseudoVMXOR_MM_M4\0" + /* 93047 */ "PseudoVMSBC_VVM_M4\0" + /* 93066 */ "PseudoVSBC_VVM_M4\0" + /* 93084 */ "PseudoVMADC_VVM_M4\0" + /* 93103 */ "PseudoVADC_VVM_M4\0" + /* 93121 */ "PseudoVMERGE_VVM_M4\0" + /* 93141 */ "PseudoVCOMPRESS_VM_M4\0" + /* 93163 */ "PseudoVMSBC_VXM_M4\0" + /* 93182 */ "PseudoVSBC_VXM_M4\0" + /* 93200 */ "PseudoVMADC_VXM_M4\0" + /* 93219 */ "PseudoVADC_VXM_M4\0" + /* 93237 */ "PseudoVMERGE_VXM_M4\0" + /* 93257 */ "PseudoVIOTA_M_M4\0" + /* 93274 */ "PseudoVREDAND_VS_M4\0" + /* 93294 */ "PseudoVREDSUM_VS_M4\0" + /* 93314 */ "PseudoVWREDSUM_VS_M4\0" + /* 93335 */ "PseudoVFREDOSUM_VS_M4\0" + /* 93357 */ "PseudoVFWREDOSUM_VS_M4\0" + /* 93380 */ "PseudoVFREDUSUM_VS_M4\0" + /* 93402 */ "PseudoVFWREDUSUM_VS_M4\0" + /* 93425 */ "PseudoVFREDMIN_VS_M4\0" + /* 93446 */ "PseudoVREDMIN_VS_M4\0" + /* 93466 */ "PseudoVREDOR_VS_M4\0" + /* 93485 */ "PseudoVREDXOR_VS_M4\0" + /* 93505 */ "PseudoVWREDSUMU_VS_M4\0" + /* 93527 */ "PseudoVREDMINU_VS_M4\0" + /* 93548 */ "PseudoVREDMAXU_VS_M4\0" + /* 93569 */ "PseudoVFREDMAX_VS_M4\0" + /* 93590 */ "PseudoVREDMAX_VS_M4\0" + /* 93610 */ "PseudoVFMV_F32_S_M4\0" + /* 93630 */ "PseudoVFMV_F64_S_M4\0" + /* 93650 */ "PseudoVFMV_F16_S_M4\0" + /* 93670 */ "PseudoVMV_X_S_M4\0" + /* 93687 */ "PseudoVSSRA_VV_M4\0" + /* 93705 */ "PseudoVSRA_VV_M4\0" + /* 93722 */ "PseudoVASUB_VV_M4\0" + /* 93740 */ "PseudoVFSUB_VV_M4\0" + /* 93758 */ "PseudoVFMSUB_VV_M4\0" + /* 93777 */ "PseudoVFNMSUB_VV_M4\0" + /* 93797 */ "PseudoVNMSUB_VV_M4\0" + /* 93816 */ "PseudoVSSUB_VV_M4\0" + /* 93834 */ "PseudoVSUB_VV_M4\0" + /* 93851 */ "PseudoVFWSUB_VV_M4\0" + /* 93870 */ "PseudoVWSUB_VV_M4\0" + /* 93888 */ "PseudoVFMSAC_VV_M4\0" + /* 93907 */ "PseudoVFNMSAC_VV_M4\0" + /* 93927 */ "PseudoVNMSAC_VV_M4\0" + /* 93946 */ "PseudoVFWNMSAC_VV_M4\0" + /* 93967 */ "PseudoVFWMSAC_VV_M4\0" + /* 93987 */ "PseudoVMSBC_VV_M4\0" + /* 94005 */ "PseudoVFMACC_VV_M4\0" + /* 94024 */ "PseudoVFNMACC_VV_M4\0" + /* 94044 */ "PseudoVFWNMACC_VV_M4\0" + /* 94065 */ "PseudoVMACC_VV_M4\0" + /* 94083 */ "PseudoVFWMACC_VV_M4\0" + /* 94103 */ "PseudoVWMACC_VV_M4\0" + /* 94122 */ "PseudoVMADC_VV_M4\0" + /* 94140 */ "PseudoVAADD_VV_M4\0" + /* 94158 */ "PseudoVFADD_VV_M4\0" + /* 94176 */ "PseudoVFMADD_VV_M4\0" + /* 94195 */ "PseudoVFNMADD_VV_M4\0" + /* 94215 */ "PseudoVMADD_VV_M4\0" + /* 94233 */ "PseudoVSADD_VV_M4\0" + /* 94251 */ "PseudoVADD_VV_M4\0" + /* 94268 */ "PseudoVFWADD_VV_M4\0" + /* 94287 */ "PseudoVWADD_VV_M4\0" + /* 94305 */ "PseudoVAND_VV_M4\0" + /* 94322 */ "PseudoVMFLE_VV_M4\0" + /* 94340 */ "PseudoVMSLE_VV_M4\0" + /* 94358 */ "PseudoVMFNE_VV_M4\0" + /* 94376 */ "PseudoVMSNE_VV_M4\0" + /* 94394 */ "PseudoVMULH_VV_M4\0" + /* 94412 */ "PseudoVFSGNJ_VV_M4\0" + /* 94431 */ "PseudoVSLL_VV_M4\0" + /* 94448 */ "PseudoVSSRL_VV_M4\0" + /* 94466 */ "PseudoVSRL_VV_M4\0" + /* 94483 */ "PseudoVFMUL_VV_M4\0" + /* 94501 */ "PseudoVSMUL_VV_M4\0" + /* 94519 */ "PseudoVMUL_VV_M4\0" + /* 94536 */ "PseudoVFWMUL_VV_M4\0" + /* 94555 */ "PseudoVWMUL_VV_M4\0" + /* 94573 */ "PseudoVREM_VV_M4\0" + /* 94590 */ "PseudoVFMIN_VV_M4\0" + /* 94608 */ "PseudoVMIN_VV_M4\0" + /* 94625 */ "PseudoVFSGNJN_VV_M4\0" + /* 94645 */ "PseudoVMFEQ_VV_M4\0" + /* 94663 */ "PseudoVMSEQ_VV_M4\0" + /* 94681 */ "PseudoVRGATHER_VV_M4\0" + /* 94702 */ "PseudoVOR_VV_M4\0" + /* 94718 */ "PseudoVXOR_VV_M4\0" + /* 94735 */ "PseudoVMFLT_VV_M4\0" + /* 94753 */ "PseudoVMSLT_VV_M4\0" + /* 94771 */ "PseudoVASUBU_VV_M4\0" + /* 94790 */ "PseudoVSSUBU_VV_M4\0" + /* 94809 */ "PseudoVWSUBU_VV_M4\0" + /* 94828 */ "PseudoVWMACCU_VV_M4\0" + /* 94848 */ "PseudoVAADDU_VV_M4\0" + /* 94867 */ "PseudoVSADDU_VV_M4\0" + /* 94886 */ "PseudoVWADDU_VV_M4\0" + /* 94905 */ "PseudoVMSLEU_VV_M4\0" + /* 94924 */ "PseudoVMULHU_VV_M4\0" + /* 94943 */ "PseudoVWMULU_VV_M4\0" + /* 94962 */ "PseudoVREMU_VV_M4\0" + /* 94980 */ "PseudoVMINU_VV_M4\0" + /* 94998 */ "PseudoVWMACCSU_VV_M4\0" + /* 95019 */ "PseudoVMULHSU_VV_M4\0" + /* 95039 */ "PseudoVWMULSU_VV_M4\0" + /* 95059 */ "PseudoVMSLTU_VV_M4\0" + /* 95078 */ "PseudoVDIVU_VV_M4\0" + /* 95096 */ "PseudoVMAXU_VV_M4\0" + /* 95114 */ "PseudoVFDIV_VV_M4\0" + /* 95132 */ "PseudoVDIV_VV_M4\0" + /* 95149 */ "PseudoVFMAX_VV_M4\0" + /* 95167 */ "PseudoVMAX_VV_M4\0" + /* 95184 */ "PseudoVFSGNJX_VV_M4\0" + /* 95204 */ "PseudoVNSRA_WV_M4\0" + /* 95222 */ "PseudoVFWSUB_WV_M4\0" + /* 95241 */ "PseudoVWSUB_WV_M4\0" + /* 95259 */ "PseudoVFWADD_WV_M4\0" + /* 95278 */ "PseudoVWADD_WV_M4\0" + /* 95296 */ "PseudoVNSRL_WV_M4\0" + /* 95314 */ "PseudoVNCLIP_WV_M4\0" + /* 95333 */ "PseudoVWSUBU_WV_M4\0" + /* 95352 */ "PseudoVWADDU_WV_M4\0" + /* 95371 */ "PseudoVNCLIPU_WV_M4\0" + /* 95391 */ "PseudoVLSEG2E32_V_M4\0" + /* 95412 */ "PseudoVLSSEG2E32_V_M4\0" + /* 95434 */ "PseudoVSSSEG2E32_V_M4\0" + /* 95456 */ "PseudoVSSEG2E32_V_M4\0" + /* 95477 */ "PseudoVLE32_V_M4\0" + /* 95494 */ "PseudoVLSE32_V_M4\0" + /* 95512 */ "PseudoVSSE32_V_M4\0" + /* 95530 */ "PseudoVSE32_V_M4\0" + /* 95547 */ "PseudoVLSEG2E64_V_M4\0" + /* 95568 */ "PseudoVLSSEG2E64_V_M4\0" + /* 95590 */ "PseudoVSSSEG2E64_V_M4\0" + /* 95612 */ "PseudoVSSEG2E64_V_M4\0" + /* 95633 */ "PseudoVLE64_V_M4\0" + /* 95650 */ "PseudoVLSE64_V_M4\0" + /* 95668 */ "PseudoVSSE64_V_M4\0" + /* 95686 */ "PseudoVSE64_V_M4\0" + /* 95703 */ "PseudoVLSEG2E16_V_M4\0" + /* 95724 */ "PseudoVLSSEG2E16_V_M4\0" + /* 95746 */ "PseudoVSSSEG2E16_V_M4\0" + /* 95768 */ "PseudoVSSEG2E16_V_M4\0" + /* 95789 */ "PseudoVLE16_V_M4\0" + /* 95806 */ "PseudoVLSE16_V_M4\0" + /* 95824 */ "PseudoVSSE16_V_M4\0" + /* 95842 */ "PseudoVSE16_V_M4\0" + /* 95859 */ "PseudoVFREC7_V_M4\0" + /* 95877 */ "PseudoVFRSQRT7_V_M4\0" + /* 95897 */ "PseudoVLSEG2E8_V_M4\0" + /* 95917 */ "PseudoVLSSEG2E8_V_M4\0" + /* 95938 */ "PseudoVSSSEG2E8_V_M4\0" + /* 95959 */ "PseudoVSSEG2E8_V_M4\0" + /* 95979 */ "PseudoVLE8_V_M4\0" + /* 95995 */ "PseudoVLSE8_V_M4\0" + /* 96012 */ "PseudoVSSE8_V_M4\0" + /* 96029 */ "PseudoVSE8_V_M4\0" + /* 96045 */ "PseudoVID_V_M4\0" + /* 96060 */ "PseudoVLSEG2E32FF_V_M4\0" + /* 96083 */ "PseudoVLE32FF_V_M4\0" + /* 96102 */ "PseudoVLSEG2E64FF_V_M4\0" + /* 96125 */ "PseudoVLE64FF_V_M4\0" + /* 96144 */ "PseudoVLSEG2E16FF_V_M4\0" + /* 96167 */ "PseudoVLE16FF_V_M4\0" + /* 96186 */ "PseudoVLSEG2E8FF_V_M4\0" + /* 96208 */ "PseudoVLE8FF_V_M4\0" + /* 96226 */ "PseudoVFWCVT_F_F_V_M4\0" + /* 96248 */ "PseudoVFCVT_XU_F_V_M4\0" + /* 96270 */ "PseudoVFWCVT_XU_F_V_M4\0" + /* 96293 */ "PseudoVFCVT_RTZ_XU_F_V_M4\0" + /* 96319 */ "PseudoVFWCVT_RTZ_XU_F_V_M4\0" + /* 96346 */ "PseudoVFCVT_X_F_V_M4\0" + /* 96367 */ "PseudoVFWCVT_X_F_V_M4\0" + /* 96389 */ "PseudoVFCVT_RTZ_X_F_V_M4\0" + /* 96414 */ "PseudoVFWCVT_RTZ_X_F_V_M4\0" + /* 96440 */ "PseudoVFCLASS_V_M4\0" + /* 96459 */ "PseudoVFSQRT_V_M4\0" + /* 96477 */ "PseudoVFCVT_F_XU_V_M4\0" + /* 96499 */ "PseudoVFWCVT_F_XU_V_M4\0" + /* 96522 */ "PseudoVMV_V_V_M4\0" + /* 96539 */ "PseudoVFCVT_F_X_V_M4\0" + /* 96560 */ "PseudoVFWCVT_F_X_V_M4\0" + /* 96582 */ "PseudoVFNCVT_ROD_F_F_W_M4\0" + /* 96608 */ "PseudoVFNCVT_F_F_W_M4\0" + /* 96630 */ "PseudoVFNCVT_XU_F_W_M4\0" + /* 96653 */ "PseudoVFNCVT_RTZ_XU_F_W_M4\0" + /* 96680 */ "PseudoVFNCVT_X_F_W_M4\0" + /* 96702 */ "PseudoVFNCVT_RTZ_X_F_W_M4\0" + /* 96728 */ "PseudoVFNCVT_F_XU_W_M4\0" + /* 96751 */ "PseudoVFNCVT_F_X_W_M4\0" + /* 96773 */ "PseudoVSSRA_VX_M4\0" + /* 96791 */ "PseudoVSRA_VX_M4\0" + /* 96808 */ "PseudoVASUB_VX_M4\0" + /* 96826 */ "PseudoVNMSUB_VX_M4\0" + /* 96845 */ "PseudoVRSUB_VX_M4\0" + /* 96863 */ "PseudoVSSUB_VX_M4\0" + /* 96881 */ "PseudoVSUB_VX_M4\0" + /* 96898 */ "PseudoVWSUB_VX_M4\0" + /* 96916 */ "PseudoVNMSAC_VX_M4\0" + /* 96935 */ "PseudoVMSBC_VX_M4\0" + /* 96953 */ "PseudoVMACC_VX_M4\0" + /* 96971 */ "PseudoVWMACC_VX_M4\0" + /* 96990 */ "PseudoVMADC_VX_M4\0" + /* 97008 */ "PseudoVAADD_VX_M4\0" + /* 97026 */ "PseudoVMADD_VX_M4\0" + /* 97044 */ "PseudoVSADD_VX_M4\0" + /* 97062 */ "PseudoVADD_VX_M4\0" + /* 97079 */ "PseudoVWADD_VX_M4\0" + /* 97097 */ "PseudoVAND_VX_M4\0" + /* 97114 */ "PseudoVMSLE_VX_M4\0" + /* 97132 */ "PseudoVMSNE_VX_M4\0" + /* 97150 */ "PseudoVMULH_VX_M4\0" + /* 97168 */ "PseudoVSLL_VX_M4\0" + /* 97185 */ "PseudoVSSRL_VX_M4\0" + /* 97203 */ "PseudoVSRL_VX_M4\0" + /* 97220 */ "PseudoVSMUL_VX_M4\0" + /* 97238 */ "PseudoVMUL_VX_M4\0" + /* 97255 */ "PseudoVWMUL_VX_M4\0" + /* 97273 */ "PseudoVREM_VX_M4\0" + /* 97290 */ "PseudoVMIN_VX_M4\0" + /* 97307 */ "PseudoVSLIDE1DOWN_VX_M4\0" + /* 97331 */ "PseudoVSLIDEDOWN_VX_M4\0" + /* 97354 */ "PseudoVSLIDE1UP_VX_M4\0" + /* 97376 */ "PseudoVSLIDEUP_VX_M4\0" + /* 97397 */ "PseudoVMSEQ_VX_M4\0" + /* 97415 */ "PseudoVRGATHER_VX_M4\0" + /* 97436 */ "PseudoVOR_VX_M4\0" + /* 97452 */ "PseudoVXOR_VX_M4\0" + /* 97469 */ "PseudoVWMACCUS_VX_M4\0" + /* 97490 */ "PseudoVMSGT_VX_M4\0" + /* 97508 */ "PseudoVMSLT_VX_M4\0" + /* 97526 */ "PseudoVASUBU_VX_M4\0" + /* 97545 */ "PseudoVSSUBU_VX_M4\0" + /* 97564 */ "PseudoVWSUBU_VX_M4\0" + /* 97583 */ "PseudoVWMACCU_VX_M4\0" + /* 97603 */ "PseudoVAADDU_VX_M4\0" + /* 97622 */ "PseudoVSADDU_VX_M4\0" + /* 97641 */ "PseudoVWADDU_VX_M4\0" + /* 97660 */ "PseudoVMSLEU_VX_M4\0" + /* 97679 */ "PseudoVMULHU_VX_M4\0" + /* 97698 */ "PseudoVWMULU_VX_M4\0" + /* 97717 */ "PseudoVREMU_VX_M4\0" + /* 97735 */ "PseudoVMINU_VX_M4\0" + /* 97753 */ "PseudoVWMACCSU_VX_M4\0" + /* 97774 */ "PseudoVMULHSU_VX_M4\0" + /* 97794 */ "PseudoVWMULSU_VX_M4\0" + /* 97814 */ "PseudoVMSGTU_VX_M4\0" + /* 97833 */ "PseudoVMSLTU_VX_M4\0" + /* 97852 */ "PseudoVDIVU_VX_M4\0" + /* 97870 */ "PseudoVMAXU_VX_M4\0" + /* 97888 */ "PseudoVDIV_VX_M4\0" + /* 97905 */ "PseudoVMAX_VX_M4\0" + /* 97922 */ "PseudoVNSRA_WX_M4\0" + /* 97940 */ "PseudoVWSUB_WX_M4\0" + /* 97958 */ "PseudoVWADD_WX_M4\0" + /* 97976 */ "PseudoVNSRL_WX_M4\0" + /* 97994 */ "PseudoVNCLIP_WX_M4\0" + /* 98013 */ "PseudoVWSUBU_WX_M4\0" + /* 98032 */ "PseudoVWADDU_WX_M4\0" + /* 98051 */ "PseudoVNCLIPU_WX_M4\0" + /* 98071 */ "PseudoVMV_S_X_M4\0" + /* 98088 */ "PseudoVMV_V_X_M4\0" + /* 98105 */ "InsnR4\0" + /* 98112 */ "PseudoVMSBF_M_B16\0" + /* 98130 */ "PseudoVMSIF_M_B16\0" + /* 98148 */ "PseudoVMSOF_M_B16\0" + /* 98166 */ "PseudoVCPOP_M_B16\0" + /* 98184 */ "PseudoVMCLR_M_B16\0" + /* 98202 */ "PseudoVMSET_M_B16\0" + /* 98220 */ "PseudoVFIRST_M_B16\0" + /* 98239 */ "PseudoVLM_V_B16\0" + /* 98255 */ "PseudoVSM_V_B16\0" + /* 98271 */ "PseudoVMSBF_M_B8\0" + /* 98288 */ "PseudoVMSIF_M_B8\0" + /* 98305 */ "PseudoVMSOF_M_B8\0" + /* 98322 */ "PseudoVCPOP_M_B8\0" + /* 98339 */ "PseudoVMCLR_M_B8\0" + /* 98356 */ "PseudoVMSET_M_B8\0" + /* 98373 */ "PseudoVFIRST_M_B8\0" + /* 98391 */ "PseudoVLM_V_B8\0" + /* 98406 */ "PseudoVSM_V_B8\0" + /* 98421 */ "PseudoVAMOADDEI8_WD_M1_MF8\0" + /* 98448 */ "PseudoVAMOANDEI8_WD_M1_MF8\0" + /* 98475 */ "PseudoVAMOMINEI8_WD_M1_MF8\0" + /* 98502 */ "PseudoVAMOSWAPEI8_WD_M1_MF8\0" + /* 98530 */ "PseudoVAMOOREI8_WD_M1_MF8\0" + /* 98556 */ "PseudoVAMOXOREI8_WD_M1_MF8\0" + /* 98583 */ "PseudoVAMOMINUEI8_WD_M1_MF8\0" + /* 98611 */ "PseudoVAMOMAXUEI8_WD_M1_MF8\0" + /* 98639 */ "PseudoVAMOMAXEI8_WD_M1_MF8\0" + /* 98666 */ "PseudoVLOXSEG2EI64_V_M1_MF8\0" + /* 98694 */ "PseudoVSOXSEG2EI64_V_M1_MF8\0" + /* 98722 */ "PseudoVLUXSEG2EI64_V_M1_MF8\0" + /* 98750 */ "PseudoVSUXSEG2EI64_V_M1_MF8\0" + /* 98778 */ "PseudoVLOXSEG3EI64_V_M1_MF8\0" + /* 98806 */ "PseudoVSOXSEG3EI64_V_M1_MF8\0" + /* 98834 */ "PseudoVLUXSEG3EI64_V_M1_MF8\0" + /* 98862 */ "PseudoVSUXSEG3EI64_V_M1_MF8\0" + /* 98890 */ "PseudoVLOXSEG4EI64_V_M1_MF8\0" + /* 98918 */ "PseudoVSOXSEG4EI64_V_M1_MF8\0" + /* 98946 */ "PseudoVLUXSEG4EI64_V_M1_MF8\0" + /* 98974 */ "PseudoVSUXSEG4EI64_V_M1_MF8\0" + /* 99002 */ "PseudoVLOXSEG5EI64_V_M1_MF8\0" + /* 99030 */ "PseudoVSOXSEG5EI64_V_M1_MF8\0" + /* 99058 */ "PseudoVLUXSEG5EI64_V_M1_MF8\0" + /* 99086 */ "PseudoVSUXSEG5EI64_V_M1_MF8\0" + /* 99114 */ "PseudoVLOXSEG6EI64_V_M1_MF8\0" + /* 99142 */ "PseudoVSOXSEG6EI64_V_M1_MF8\0" + /* 99170 */ "PseudoVLUXSEG6EI64_V_M1_MF8\0" + /* 99198 */ "PseudoVSUXSEG6EI64_V_M1_MF8\0" + /* 99226 */ "PseudoVLOXSEG7EI64_V_M1_MF8\0" + /* 99254 */ "PseudoVSOXSEG7EI64_V_M1_MF8\0" + /* 99282 */ "PseudoVLUXSEG7EI64_V_M1_MF8\0" + /* 99310 */ "PseudoVSUXSEG7EI64_V_M1_MF8\0" + /* 99338 */ "PseudoVLOXSEG8EI64_V_M1_MF8\0" + /* 99366 */ "PseudoVSOXSEG8EI64_V_M1_MF8\0" + /* 99394 */ "PseudoVLUXSEG8EI64_V_M1_MF8\0" + /* 99422 */ "PseudoVSUXSEG8EI64_V_M1_MF8\0" + /* 99450 */ "PseudoVLOXEI64_V_M1_MF8\0" + /* 99474 */ "PseudoVSOXEI64_V_M1_MF8\0" + /* 99498 */ "PseudoVLUXEI64_V_M1_MF8\0" + /* 99522 */ "PseudoVSUXEI64_V_M1_MF8\0" + /* 99546 */ "PseudoVFSUB_VF32_MF8\0" + /* 99567 */ "PseudoVFMSUB_VF32_MF8\0" + /* 99589 */ "PseudoVFNMSUB_VF32_MF8\0" + /* 99612 */ "PseudoVFRSUB_VF32_MF8\0" + /* 99634 */ "PseudoVFWSUB_VF32_MF8\0" + /* 99656 */ "PseudoVFMSAC_VF32_MF8\0" + /* 99678 */ "PseudoVFNMSAC_VF32_MF8\0" + /* 99701 */ "PseudoVFWNMSAC_VF32_MF8\0" + /* 99725 */ "PseudoVFWMSAC_VF32_MF8\0" + /* 99748 */ "PseudoVFMACC_VF32_MF8\0" + /* 99770 */ "PseudoVFNMACC_VF32_MF8\0" + /* 99793 */ "PseudoVFWNMACC_VF32_MF8\0" + /* 99817 */ "PseudoVFWMACC_VF32_MF8\0" + /* 99840 */ "PseudoVFADD_VF32_MF8\0" + /* 99861 */ "PseudoVFMADD_VF32_MF8\0" + /* 99883 */ "PseudoVFNMADD_VF32_MF8\0" + /* 99906 */ "PseudoVFWADD_VF32_MF8\0" + /* 99928 */ "PseudoVMFGE_VF32_MF8\0" + /* 99949 */ "PseudoVMFLE_VF32_MF8\0" + /* 99970 */ "PseudoVMFNE_VF32_MF8\0" + /* 99991 */ "PseudoVFSGNJ_VF32_MF8\0" + /* 100013 */ "PseudoVFMUL_VF32_MF8\0" + /* 100034 */ "PseudoVFWMUL_VF32_MF8\0" + /* 100056 */ "PseudoVFMIN_VF32_MF8\0" + /* 100077 */ "PseudoVFSGNJN_VF32_MF8\0" + /* 100100 */ "PseudoVFSLIDE1DOWN_VF32_MF8\0" + /* 100128 */ "PseudoVFSLIDE1UP_VF32_MF8\0" + /* 100154 */ "PseudoVMFEQ_VF32_MF8\0" + /* 100175 */ "PseudoVMFGT_VF32_MF8\0" + /* 100196 */ "PseudoVMFLT_VF32_MF8\0" + /* 100217 */ "PseudoVFDIV_VF32_MF8\0" + /* 100238 */ "PseudoVFRDIV_VF32_MF8\0" + /* 100260 */ "PseudoVFMAX_VF32_MF8\0" + /* 100281 */ "PseudoVFSGNJX_VF32_MF8\0" + /* 100304 */ "PseudoVFWSUB_WF32_MF8\0" + /* 100326 */ "PseudoVFWADD_WF32_MF8\0" + /* 100348 */ "PseudoVFMV_S_F32_MF8\0" + /* 100369 */ "PseudoVFMV_V_F32_MF8\0" + /* 100390 */ "PseudoVRELOAD2_MF8\0" + /* 100409 */ "PseudoVAMOADDEI8_WD_MF2_MF8\0" + /* 100437 */ "PseudoVAMOANDEI8_WD_MF2_MF8\0" + /* 100465 */ "PseudoVAMOMINEI8_WD_MF2_MF8\0" + /* 100493 */ "PseudoVAMOSWAPEI8_WD_MF2_MF8\0" + /* 100522 */ "PseudoVAMOOREI8_WD_MF2_MF8\0" + /* 100549 */ "PseudoVAMOXOREI8_WD_MF2_MF8\0" + /* 100577 */ "PseudoVAMOMINUEI8_WD_MF2_MF8\0" + /* 100606 */ "PseudoVAMOMAXUEI8_WD_MF2_MF8\0" + /* 100635 */ "PseudoVAMOMAXEI8_WD_MF2_MF8\0" + /* 100663 */ "PseudoVRGATHEREI16_VV_MF2_MF8\0" + /* 100693 */ "PseudoVLOXSEG2EI32_V_MF2_MF8\0" + /* 100722 */ "PseudoVSOXSEG2EI32_V_MF2_MF8\0" + /* 100751 */ "PseudoVLUXSEG2EI32_V_MF2_MF8\0" + /* 100780 */ "PseudoVSUXSEG2EI32_V_MF2_MF8\0" + /* 100809 */ "PseudoVLOXSEG3EI32_V_MF2_MF8\0" + /* 100838 */ "PseudoVSOXSEG3EI32_V_MF2_MF8\0" + /* 100867 */ "PseudoVLUXSEG3EI32_V_MF2_MF8\0" + /* 100896 */ "PseudoVSUXSEG3EI32_V_MF2_MF8\0" + /* 100925 */ "PseudoVLOXSEG4EI32_V_MF2_MF8\0" + /* 100954 */ "PseudoVSOXSEG4EI32_V_MF2_MF8\0" + /* 100983 */ "PseudoVLUXSEG4EI32_V_MF2_MF8\0" + /* 101012 */ "PseudoVSUXSEG4EI32_V_MF2_MF8\0" + /* 101041 */ "PseudoVLOXSEG5EI32_V_MF2_MF8\0" + /* 101070 */ "PseudoVSOXSEG5EI32_V_MF2_MF8\0" + /* 101099 */ "PseudoVLUXSEG5EI32_V_MF2_MF8\0" + /* 101128 */ "PseudoVSUXSEG5EI32_V_MF2_MF8\0" + /* 101157 */ "PseudoVLOXSEG6EI32_V_MF2_MF8\0" + /* 101186 */ "PseudoVSOXSEG6EI32_V_MF2_MF8\0" + /* 101215 */ "PseudoVLUXSEG6EI32_V_MF2_MF8\0" + /* 101244 */ "PseudoVSUXSEG6EI32_V_MF2_MF8\0" + /* 101273 */ "PseudoVLOXSEG7EI32_V_MF2_MF8\0" + /* 101302 */ "PseudoVSOXSEG7EI32_V_MF2_MF8\0" + /* 101331 */ "PseudoVLUXSEG7EI32_V_MF2_MF8\0" + /* 101360 */ "PseudoVSUXSEG7EI32_V_MF2_MF8\0" + /* 101389 */ "PseudoVLOXSEG8EI32_V_MF2_MF8\0" + /* 101418 */ "PseudoVSOXSEG8EI32_V_MF2_MF8\0" + /* 101447 */ "PseudoVLUXSEG8EI32_V_MF2_MF8\0" + /* 101476 */ "PseudoVSUXSEG8EI32_V_MF2_MF8\0" + /* 101505 */ "PseudoVLOXEI32_V_MF2_MF8\0" + /* 101530 */ "PseudoVSOXEI32_V_MF2_MF8\0" + /* 101555 */ "PseudoVLUXEI32_V_MF2_MF8\0" + /* 101580 */ "PseudoVSUXEI32_V_MF2_MF8\0" + /* 101605 */ "PseudoVSPILL2_MF8\0" + /* 101623 */ "PseudoVRELOAD3_MF8\0" + /* 101642 */ "PseudoVSPILL3_MF8\0" + /* 101660 */ "PseudoVFSUB_VF64_MF8\0" + /* 101681 */ "PseudoVFMSUB_VF64_MF8\0" + /* 101703 */ "PseudoVFNMSUB_VF64_MF8\0" + /* 101726 */ "PseudoVFRSUB_VF64_MF8\0" + /* 101748 */ "PseudoVFMSAC_VF64_MF8\0" + /* 101770 */ "PseudoVFNMSAC_VF64_MF8\0" + /* 101793 */ "PseudoVFMACC_VF64_MF8\0" + /* 101815 */ "PseudoVFNMACC_VF64_MF8\0" + /* 101838 */ "PseudoVFADD_VF64_MF8\0" + /* 101859 */ "PseudoVFMADD_VF64_MF8\0" + /* 101881 */ "PseudoVFNMADD_VF64_MF8\0" + /* 101904 */ "PseudoVMFGE_VF64_MF8\0" + /* 101925 */ "PseudoVMFLE_VF64_MF8\0" + /* 101946 */ "PseudoVMFNE_VF64_MF8\0" + /* 101967 */ "PseudoVFSGNJ_VF64_MF8\0" + /* 101989 */ "PseudoVFMUL_VF64_MF8\0" + /* 102010 */ "PseudoVFMIN_VF64_MF8\0" + /* 102031 */ "PseudoVFSGNJN_VF64_MF8\0" + /* 102054 */ "PseudoVFSLIDE1DOWN_VF64_MF8\0" + /* 102082 */ "PseudoVFSLIDE1UP_VF64_MF8\0" + /* 102108 */ "PseudoVMFEQ_VF64_MF8\0" + /* 102129 */ "PseudoVMFGT_VF64_MF8\0" + /* 102150 */ "PseudoVMFLT_VF64_MF8\0" + /* 102171 */ "PseudoVFDIV_VF64_MF8\0" + /* 102192 */ "PseudoVFRDIV_VF64_MF8\0" + /* 102214 */ "PseudoVFMAX_VF64_MF8\0" + /* 102235 */ "PseudoVFSGNJX_VF64_MF8\0" + /* 102258 */ "PseudoVFMV_S_F64_MF8\0" + /* 102279 */ "PseudoVFMV_V_F64_MF8\0" + /* 102300 */ "PseudoVRELOAD4_MF8\0" + /* 102319 */ "PseudoVRGATHEREI16_VV_MF4_MF8\0" + /* 102349 */ "PseudoVLOXSEG2EI16_V_MF4_MF8\0" + /* 102378 */ "PseudoVSOXSEG2EI16_V_MF4_MF8\0" + /* 102407 */ "PseudoVLUXSEG2EI16_V_MF4_MF8\0" + /* 102436 */ "PseudoVSUXSEG2EI16_V_MF4_MF8\0" + /* 102465 */ "PseudoVLOXSEG3EI16_V_MF4_MF8\0" + /* 102494 */ "PseudoVSOXSEG3EI16_V_MF4_MF8\0" + /* 102523 */ "PseudoVLUXSEG3EI16_V_MF4_MF8\0" + /* 102552 */ "PseudoVSUXSEG3EI16_V_MF4_MF8\0" + /* 102581 */ "PseudoVLOXSEG4EI16_V_MF4_MF8\0" + /* 102610 */ "PseudoVSOXSEG4EI16_V_MF4_MF8\0" + /* 102639 */ "PseudoVLUXSEG4EI16_V_MF4_MF8\0" + /* 102668 */ "PseudoVSUXSEG4EI16_V_MF4_MF8\0" + /* 102697 */ "PseudoVLOXSEG5EI16_V_MF4_MF8\0" + /* 102726 */ "PseudoVSOXSEG5EI16_V_MF4_MF8\0" + /* 102755 */ "PseudoVLUXSEG5EI16_V_MF4_MF8\0" + /* 102784 */ "PseudoVSUXSEG5EI16_V_MF4_MF8\0" + /* 102813 */ "PseudoVLOXSEG6EI16_V_MF4_MF8\0" + /* 102842 */ "PseudoVSOXSEG6EI16_V_MF4_MF8\0" + /* 102871 */ "PseudoVLUXSEG6EI16_V_MF4_MF8\0" + /* 102900 */ "PseudoVSUXSEG6EI16_V_MF4_MF8\0" + /* 102929 */ "PseudoVLOXSEG7EI16_V_MF4_MF8\0" + /* 102958 */ "PseudoVSOXSEG7EI16_V_MF4_MF8\0" + /* 102987 */ "PseudoVLUXSEG7EI16_V_MF4_MF8\0" + /* 103016 */ "PseudoVSUXSEG7EI16_V_MF4_MF8\0" + /* 103045 */ "PseudoVLOXSEG8EI16_V_MF4_MF8\0" + /* 103074 */ "PseudoVSOXSEG8EI16_V_MF4_MF8\0" + /* 103103 */ "PseudoVLUXSEG8EI16_V_MF4_MF8\0" + /* 103132 */ "PseudoVSUXSEG8EI16_V_MF4_MF8\0" + /* 103161 */ "PseudoVLOXEI16_V_MF4_MF8\0" + /* 103186 */ "PseudoVSOXEI16_V_MF4_MF8\0" + /* 103211 */ "PseudoVLUXEI16_V_MF4_MF8\0" + /* 103236 */ "PseudoVSUXEI16_V_MF4_MF8\0" + /* 103261 */ "PseudoVSPILL4_MF8\0" + /* 103279 */ "PseudoVRELOAD5_MF8\0" + /* 103298 */ "PseudoVSPILL5_MF8\0" + /* 103316 */ "PseudoVFSUB_VF16_MF8\0" + /* 103337 */ "PseudoVFMSUB_VF16_MF8\0" + /* 103359 */ "PseudoVFNMSUB_VF16_MF8\0" + /* 103382 */ "PseudoVFRSUB_VF16_MF8\0" + /* 103404 */ "PseudoVFWSUB_VF16_MF8\0" + /* 103426 */ "PseudoVFMSAC_VF16_MF8\0" + /* 103448 */ "PseudoVFNMSAC_VF16_MF8\0" + /* 103471 */ "PseudoVFWNMSAC_VF16_MF8\0" + /* 103495 */ "PseudoVFWMSAC_VF16_MF8\0" + /* 103518 */ "PseudoVFMACC_VF16_MF8\0" + /* 103540 */ "PseudoVFNMACC_VF16_MF8\0" + /* 103563 */ "PseudoVFWNMACC_VF16_MF8\0" + /* 103587 */ "PseudoVFWMACC_VF16_MF8\0" + /* 103610 */ "PseudoVFADD_VF16_MF8\0" + /* 103631 */ "PseudoVFMADD_VF16_MF8\0" + /* 103653 */ "PseudoVFNMADD_VF16_MF8\0" + /* 103676 */ "PseudoVFWADD_VF16_MF8\0" + /* 103698 */ "PseudoVMFGE_VF16_MF8\0" + /* 103719 */ "PseudoVMFLE_VF16_MF8\0" + /* 103740 */ "PseudoVMFNE_VF16_MF8\0" + /* 103761 */ "PseudoVFSGNJ_VF16_MF8\0" + /* 103783 */ "PseudoVFMUL_VF16_MF8\0" + /* 103804 */ "PseudoVFWMUL_VF16_MF8\0" + /* 103826 */ "PseudoVFMIN_VF16_MF8\0" + /* 103847 */ "PseudoVFSGNJN_VF16_MF8\0" + /* 103870 */ "PseudoVFSLIDE1DOWN_VF16_MF8\0" + /* 103898 */ "PseudoVFSLIDE1UP_VF16_MF8\0" + /* 103924 */ "PseudoVMFEQ_VF16_MF8\0" + /* 103945 */ "PseudoVMFGT_VF16_MF8\0" + /* 103966 */ "PseudoVMFLT_VF16_MF8\0" + /* 103987 */ "PseudoVFDIV_VF16_MF8\0" + /* 104008 */ "PseudoVFRDIV_VF16_MF8\0" + /* 104030 */ "PseudoVFMAX_VF16_MF8\0" + /* 104051 */ "PseudoVFSGNJX_VF16_MF8\0" + /* 104074 */ "PseudoVFWSUB_WF16_MF8\0" + /* 104096 */ "PseudoVFWADD_WF16_MF8\0" + /* 104118 */ "PseudoVFMV_S_F16_MF8\0" + /* 104139 */ "PseudoVFMV_V_F16_MF8\0" + /* 104160 */ "PseudoVRELOAD6_MF8\0" + /* 104179 */ "PseudoVSPILL6_MF8\0" + /* 104197 */ "PseudoVRELOAD7_MF8\0" + /* 104216 */ "PseudoVSPILL7_MF8\0" + /* 104234 */ "PseudoVRELOAD8_MF8\0" + /* 104253 */ "PseudoVRGATHEREI16_VV_MF8_MF8\0" + /* 104283 */ "PseudoVLOXSEG2EI8_V_MF8_MF8\0" + /* 104311 */ "PseudoVSOXSEG2EI8_V_MF8_MF8\0" + /* 104339 */ "PseudoVLUXSEG2EI8_V_MF8_MF8\0" + /* 104367 */ "PseudoVSUXSEG2EI8_V_MF8_MF8\0" + /* 104395 */ "PseudoVLOXSEG3EI8_V_MF8_MF8\0" + /* 104423 */ "PseudoVSOXSEG3EI8_V_MF8_MF8\0" + /* 104451 */ "PseudoVLUXSEG3EI8_V_MF8_MF8\0" + /* 104479 */ "PseudoVSUXSEG3EI8_V_MF8_MF8\0" + /* 104507 */ "PseudoVLOXSEG4EI8_V_MF8_MF8\0" + /* 104535 */ "PseudoVSOXSEG4EI8_V_MF8_MF8\0" + /* 104563 */ "PseudoVLUXSEG4EI8_V_MF8_MF8\0" + /* 104591 */ "PseudoVSUXSEG4EI8_V_MF8_MF8\0" + /* 104619 */ "PseudoVLOXSEG5EI8_V_MF8_MF8\0" + /* 104647 */ "PseudoVSOXSEG5EI8_V_MF8_MF8\0" + /* 104675 */ "PseudoVLUXSEG5EI8_V_MF8_MF8\0" + /* 104703 */ "PseudoVSUXSEG5EI8_V_MF8_MF8\0" + /* 104731 */ "PseudoVLOXSEG6EI8_V_MF8_MF8\0" + /* 104759 */ "PseudoVSOXSEG6EI8_V_MF8_MF8\0" + /* 104787 */ "PseudoVLUXSEG6EI8_V_MF8_MF8\0" + /* 104815 */ "PseudoVSUXSEG6EI8_V_MF8_MF8\0" + /* 104843 */ "PseudoVLOXSEG7EI8_V_MF8_MF8\0" + /* 104871 */ "PseudoVSOXSEG7EI8_V_MF8_MF8\0" + /* 104899 */ "PseudoVLUXSEG7EI8_V_MF8_MF8\0" + /* 104927 */ "PseudoVSUXSEG7EI8_V_MF8_MF8\0" + /* 104955 */ "PseudoVLOXSEG8EI8_V_MF8_MF8\0" + /* 104983 */ "PseudoVSOXSEG8EI8_V_MF8_MF8\0" + /* 105011 */ "PseudoVLUXSEG8EI8_V_MF8_MF8\0" + /* 105039 */ "PseudoVSUXSEG8EI8_V_MF8_MF8\0" + /* 105067 */ "PseudoVLOXEI8_V_MF8_MF8\0" + /* 105091 */ "PseudoVSOXEI8_V_MF8_MF8\0" + /* 105115 */ "PseudoVLUXEI8_V_MF8_MF8\0" + /* 105139 */ "PseudoVSUXEI8_V_MF8_MF8\0" + /* 105163 */ "PseudoVSPILL8_MF8\0" + /* 105181 */ "PseudoVSSRA_VI_MF8\0" + /* 105200 */ "PseudoVSRA_VI_MF8\0" + /* 105218 */ "PseudoVRSUB_VI_MF8\0" + /* 105237 */ "PseudoVMADC_VI_MF8\0" + /* 105256 */ "PseudoVSADD_VI_MF8\0" + /* 105275 */ "PseudoVADD_VI_MF8\0" + /* 105293 */ "PseudoVAND_VI_MF8\0" + /* 105311 */ "PseudoVMSLE_VI_MF8\0" + /* 105330 */ "PseudoVMSNE_VI_MF8\0" + /* 105349 */ "PseudoVSLL_VI_MF8\0" + /* 105367 */ "PseudoVSSRL_VI_MF8\0" + /* 105386 */ "PseudoVSRL_VI_MF8\0" + /* 105404 */ "PseudoVSLIDEDOWN_VI_MF8\0" + /* 105428 */ "PseudoVSLIDEUP_VI_MF8\0" + /* 105450 */ "PseudoVMSEQ_VI_MF8\0" + /* 105469 */ "PseudoVRGATHER_VI_MF8\0" + /* 105491 */ "PseudoVOR_VI_MF8\0" + /* 105508 */ "PseudoVXOR_VI_MF8\0" + /* 105526 */ "PseudoVMSGT_VI_MF8\0" + /* 105545 */ "PseudoVSADDU_VI_MF8\0" + /* 105565 */ "PseudoVMSLEU_VI_MF8\0" + /* 105585 */ "PseudoVMSGTU_VI_MF8\0" + /* 105605 */ "PseudoVNSRA_WI_MF8\0" + /* 105624 */ "PseudoVNSRL_WI_MF8\0" + /* 105643 */ "PseudoVNCLIP_WI_MF8\0" + /* 105663 */ "PseudoVNCLIPU_WI_MF8\0" + /* 105684 */ "PseudoVMV_V_I_MF8\0" + /* 105702 */ "PseudoVFMERGE_VF32M_MF8\0" + /* 105726 */ "PseudoVFMERGE_VF64M_MF8\0" + /* 105750 */ "PseudoVFMERGE_VF16M_MF8\0" + /* 105774 */ "PseudoVMADC_VIM_MF8\0" + /* 105794 */ "PseudoVADC_VIM_MF8\0" + /* 105813 */ "PseudoVMERGE_VIM_MF8\0" + /* 105834 */ "PseudoVMAND_MM_MF8\0" + /* 105853 */ "PseudoVMNAND_MM_MF8\0" + /* 105873 */ "PseudoVMANDN_MM_MF8\0" + /* 105893 */ "PseudoVMORN_MM_MF8\0" + /* 105912 */ "PseudoVMOR_MM_MF8\0" + /* 105930 */ "PseudoVMNOR_MM_MF8\0" + /* 105949 */ "PseudoVMXNOR_MM_MF8\0" + /* 105969 */ "PseudoVMXOR_MM_MF8\0" + /* 105988 */ "PseudoVMSBC_VVM_MF8\0" + /* 106008 */ "PseudoVSBC_VVM_MF8\0" + /* 106027 */ "PseudoVMADC_VVM_MF8\0" + /* 106047 */ "PseudoVADC_VVM_MF8\0" + /* 106066 */ "PseudoVMERGE_VVM_MF8\0" + /* 106087 */ "PseudoVCOMPRESS_VM_MF8\0" + /* 106110 */ "PseudoVMSBC_VXM_MF8\0" + /* 106130 */ "PseudoVSBC_VXM_MF8\0" + /* 106149 */ "PseudoVMADC_VXM_MF8\0" + /* 106169 */ "PseudoVADC_VXM_MF8\0" + /* 106188 */ "PseudoVMERGE_VXM_MF8\0" + /* 106209 */ "PseudoVIOTA_M_MF8\0" + /* 106227 */ "PseudoVREDAND_VS_MF8\0" + /* 106248 */ "PseudoVREDSUM_VS_MF8\0" + /* 106269 */ "PseudoVWREDSUM_VS_MF8\0" + /* 106291 */ "PseudoVFREDOSUM_VS_MF8\0" + /* 106314 */ "PseudoVFWREDOSUM_VS_MF8\0" + /* 106338 */ "PseudoVFREDUSUM_VS_MF8\0" + /* 106361 */ "PseudoVFWREDUSUM_VS_MF8\0" + /* 106385 */ "PseudoVFREDMIN_VS_MF8\0" + /* 106407 */ "PseudoVREDMIN_VS_MF8\0" + /* 106428 */ "PseudoVREDOR_VS_MF8\0" + /* 106448 */ "PseudoVREDXOR_VS_MF8\0" + /* 106469 */ "PseudoVWREDSUMU_VS_MF8\0" + /* 106492 */ "PseudoVREDMINU_VS_MF8\0" + /* 106514 */ "PseudoVREDMAXU_VS_MF8\0" + /* 106536 */ "PseudoVFREDMAX_VS_MF8\0" + /* 106558 */ "PseudoVREDMAX_VS_MF8\0" + /* 106579 */ "PseudoVFMV_F32_S_MF8\0" + /* 106600 */ "PseudoVFMV_F64_S_MF8\0" + /* 106621 */ "PseudoVFMV_F16_S_MF8\0" + /* 106642 */ "PseudoVMV_X_S_MF8\0" + /* 106660 */ "PseudoVSSRA_VV_MF8\0" + /* 106679 */ "PseudoVSRA_VV_MF8\0" + /* 106697 */ "PseudoVASUB_VV_MF8\0" + /* 106716 */ "PseudoVFSUB_VV_MF8\0" + /* 106735 */ "PseudoVFMSUB_VV_MF8\0" + /* 106755 */ "PseudoVFNMSUB_VV_MF8\0" + /* 106776 */ "PseudoVNMSUB_VV_MF8\0" + /* 106796 */ "PseudoVSSUB_VV_MF8\0" + /* 106815 */ "PseudoVSUB_VV_MF8\0" + /* 106833 */ "PseudoVFWSUB_VV_MF8\0" + /* 106853 */ "PseudoVWSUB_VV_MF8\0" + /* 106872 */ "PseudoVFMSAC_VV_MF8\0" + /* 106892 */ "PseudoVFNMSAC_VV_MF8\0" + /* 106913 */ "PseudoVNMSAC_VV_MF8\0" + /* 106933 */ "PseudoVFWNMSAC_VV_MF8\0" + /* 106955 */ "PseudoVFWMSAC_VV_MF8\0" + /* 106976 */ "PseudoVMSBC_VV_MF8\0" + /* 106995 */ "PseudoVFMACC_VV_MF8\0" + /* 107015 */ "PseudoVFNMACC_VV_MF8\0" + /* 107036 */ "PseudoVFWNMACC_VV_MF8\0" + /* 107058 */ "PseudoVMACC_VV_MF8\0" + /* 107077 */ "PseudoVFWMACC_VV_MF8\0" + /* 107098 */ "PseudoVWMACC_VV_MF8\0" + /* 107118 */ "PseudoVMADC_VV_MF8\0" + /* 107137 */ "PseudoVAADD_VV_MF8\0" + /* 107156 */ "PseudoVFADD_VV_MF8\0" + /* 107175 */ "PseudoVFMADD_VV_MF8\0" + /* 107195 */ "PseudoVFNMADD_VV_MF8\0" + /* 107216 */ "PseudoVMADD_VV_MF8\0" + /* 107235 */ "PseudoVSADD_VV_MF8\0" + /* 107254 */ "PseudoVADD_VV_MF8\0" + /* 107272 */ "PseudoVFWADD_VV_MF8\0" + /* 107292 */ "PseudoVWADD_VV_MF8\0" + /* 107311 */ "PseudoVAND_VV_MF8\0" + /* 107329 */ "PseudoVMFLE_VV_MF8\0" + /* 107348 */ "PseudoVMSLE_VV_MF8\0" + /* 107367 */ "PseudoVMFNE_VV_MF8\0" + /* 107386 */ "PseudoVMSNE_VV_MF8\0" + /* 107405 */ "PseudoVMULH_VV_MF8\0" + /* 107424 */ "PseudoVFSGNJ_VV_MF8\0" + /* 107444 */ "PseudoVSLL_VV_MF8\0" + /* 107462 */ "PseudoVSSRL_VV_MF8\0" + /* 107481 */ "PseudoVSRL_VV_MF8\0" + /* 107499 */ "PseudoVFMUL_VV_MF8\0" + /* 107518 */ "PseudoVSMUL_VV_MF8\0" + /* 107537 */ "PseudoVMUL_VV_MF8\0" + /* 107555 */ "PseudoVFWMUL_VV_MF8\0" + /* 107575 */ "PseudoVWMUL_VV_MF8\0" + /* 107594 */ "PseudoVREM_VV_MF8\0" + /* 107612 */ "PseudoVFMIN_VV_MF8\0" + /* 107631 */ "PseudoVMIN_VV_MF8\0" + /* 107649 */ "PseudoVFSGNJN_VV_MF8\0" + /* 107670 */ "PseudoVMFEQ_VV_MF8\0" + /* 107689 */ "PseudoVMSEQ_VV_MF8\0" + /* 107708 */ "PseudoVRGATHER_VV_MF8\0" + /* 107730 */ "PseudoVOR_VV_MF8\0" + /* 107747 */ "PseudoVXOR_VV_MF8\0" + /* 107765 */ "PseudoVMFLT_VV_MF8\0" + /* 107784 */ "PseudoVMSLT_VV_MF8\0" + /* 107803 */ "PseudoVASUBU_VV_MF8\0" + /* 107823 */ "PseudoVSSUBU_VV_MF8\0" + /* 107843 */ "PseudoVWSUBU_VV_MF8\0" + /* 107863 */ "PseudoVWMACCU_VV_MF8\0" + /* 107884 */ "PseudoVAADDU_VV_MF8\0" + /* 107904 */ "PseudoVSADDU_VV_MF8\0" + /* 107924 */ "PseudoVWADDU_VV_MF8\0" + /* 107944 */ "PseudoVMSLEU_VV_MF8\0" + /* 107964 */ "PseudoVMULHU_VV_MF8\0" + /* 107984 */ "PseudoVWMULU_VV_MF8\0" + /* 108004 */ "PseudoVREMU_VV_MF8\0" + /* 108023 */ "PseudoVMINU_VV_MF8\0" + /* 108042 */ "PseudoVWMACCSU_VV_MF8\0" + /* 108064 */ "PseudoVMULHSU_VV_MF8\0" + /* 108085 */ "PseudoVWMULSU_VV_MF8\0" + /* 108106 */ "PseudoVMSLTU_VV_MF8\0" + /* 108126 */ "PseudoVDIVU_VV_MF8\0" + /* 108145 */ "PseudoVMAXU_VV_MF8\0" + /* 108164 */ "PseudoVFDIV_VV_MF8\0" + /* 108183 */ "PseudoVDIV_VV_MF8\0" + /* 108201 */ "PseudoVFMAX_VV_MF8\0" + /* 108220 */ "PseudoVMAX_VV_MF8\0" + /* 108238 */ "PseudoVFSGNJX_VV_MF8\0" + /* 108259 */ "PseudoVNSRA_WV_MF8\0" + /* 108278 */ "PseudoVFWSUB_WV_MF8\0" + /* 108298 */ "PseudoVWSUB_WV_MF8\0" + /* 108317 */ "PseudoVFWADD_WV_MF8\0" + /* 108337 */ "PseudoVWADD_WV_MF8\0" + /* 108356 */ "PseudoVNSRL_WV_MF8\0" + /* 108375 */ "PseudoVNCLIP_WV_MF8\0" + /* 108395 */ "PseudoVWSUBU_WV_MF8\0" + /* 108415 */ "PseudoVWADDU_WV_MF8\0" + /* 108435 */ "PseudoVNCLIPU_WV_MF8\0" + /* 108456 */ "PseudoVFREC7_V_MF8\0" + /* 108475 */ "PseudoVFRSQRT7_V_MF8\0" + /* 108496 */ "PseudoVLSEG2E8_V_MF8\0" + /* 108517 */ "PseudoVLSSEG2E8_V_MF8\0" + /* 108539 */ "PseudoVSSSEG2E8_V_MF8\0" + /* 108561 */ "PseudoVSSEG2E8_V_MF8\0" + /* 108582 */ "PseudoVLSEG3E8_V_MF8\0" + /* 108603 */ "PseudoVLSSEG3E8_V_MF8\0" + /* 108625 */ "PseudoVSSSEG3E8_V_MF8\0" + /* 108647 */ "PseudoVSSEG3E8_V_MF8\0" + /* 108668 */ "PseudoVLSEG4E8_V_MF8\0" + /* 108689 */ "PseudoVLSSEG4E8_V_MF8\0" + /* 108711 */ "PseudoVSSSEG4E8_V_MF8\0" + /* 108733 */ "PseudoVSSEG4E8_V_MF8\0" + /* 108754 */ "PseudoVLSEG5E8_V_MF8\0" + /* 108775 */ "PseudoVLSSEG5E8_V_MF8\0" + /* 108797 */ "PseudoVSSSEG5E8_V_MF8\0" + /* 108819 */ "PseudoVSSEG5E8_V_MF8\0" + /* 108840 */ "PseudoVLSEG6E8_V_MF8\0" + /* 108861 */ "PseudoVLSSEG6E8_V_MF8\0" + /* 108883 */ "PseudoVSSSEG6E8_V_MF8\0" + /* 108905 */ "PseudoVSSEG6E8_V_MF8\0" + /* 108926 */ "PseudoVLSEG7E8_V_MF8\0" + /* 108947 */ "PseudoVLSSEG7E8_V_MF8\0" + /* 108969 */ "PseudoVSSSEG7E8_V_MF8\0" + /* 108991 */ "PseudoVSSEG7E8_V_MF8\0" + /* 109012 */ "PseudoVLSEG8E8_V_MF8\0" + /* 109033 */ "PseudoVLSSEG8E8_V_MF8\0" + /* 109055 */ "PseudoVSSSEG8E8_V_MF8\0" + /* 109077 */ "PseudoVSSEG8E8_V_MF8\0" + /* 109098 */ "PseudoVLE8_V_MF8\0" + /* 109115 */ "PseudoVLSE8_V_MF8\0" + /* 109133 */ "PseudoVSSE8_V_MF8\0" + /* 109151 */ "PseudoVSE8_V_MF8\0" + /* 109168 */ "PseudoVID_V_MF8\0" + /* 109184 */ "PseudoVLSEG2E8FF_V_MF8\0" + /* 109207 */ "PseudoVLSEG3E8FF_V_MF8\0" + /* 109230 */ "PseudoVLSEG4E8FF_V_MF8\0" + /* 109253 */ "PseudoVLSEG5E8FF_V_MF8\0" + /* 109276 */ "PseudoVLSEG6E8FF_V_MF8\0" + /* 109299 */ "PseudoVLSEG7E8FF_V_MF8\0" + /* 109322 */ "PseudoVLSEG8E8FF_V_MF8\0" + /* 109345 */ "PseudoVLE8FF_V_MF8\0" + /* 109364 */ "PseudoVFWCVT_F_F_V_MF8\0" + /* 109387 */ "PseudoVFCVT_XU_F_V_MF8\0" + /* 109410 */ "PseudoVFWCVT_XU_F_V_MF8\0" + /* 109434 */ "PseudoVFCVT_RTZ_XU_F_V_MF8\0" + /* 109461 */ "PseudoVFWCVT_RTZ_XU_F_V_MF8\0" + /* 109489 */ "PseudoVFCVT_X_F_V_MF8\0" + /* 109511 */ "PseudoVFWCVT_X_F_V_MF8\0" + /* 109534 */ "PseudoVFCVT_RTZ_X_F_V_MF8\0" + /* 109560 */ "PseudoVFWCVT_RTZ_X_F_V_MF8\0" + /* 109587 */ "PseudoVFCLASS_V_MF8\0" + /* 109607 */ "PseudoVFSQRT_V_MF8\0" + /* 109626 */ "PseudoVFCVT_F_XU_V_MF8\0" + /* 109649 */ "PseudoVFWCVT_F_XU_V_MF8\0" + /* 109673 */ "PseudoVMV_V_V_MF8\0" + /* 109691 */ "PseudoVFCVT_F_X_V_MF8\0" + /* 109713 */ "PseudoVFWCVT_F_X_V_MF8\0" + /* 109736 */ "PseudoVFNCVT_ROD_F_F_W_MF8\0" + /* 109763 */ "PseudoVFNCVT_F_F_W_MF8\0" + /* 109786 */ "PseudoVFNCVT_XU_F_W_MF8\0" + /* 109810 */ "PseudoVFNCVT_RTZ_XU_F_W_MF8\0" + /* 109838 */ "PseudoVFNCVT_X_F_W_MF8\0" + /* 109861 */ "PseudoVFNCVT_RTZ_X_F_W_MF8\0" + /* 109888 */ "PseudoVFNCVT_F_XU_W_MF8\0" + /* 109912 */ "PseudoVFNCVT_F_X_W_MF8\0" + /* 109935 */ "PseudoVSSRA_VX_MF8\0" + /* 109954 */ "PseudoVSRA_VX_MF8\0" + /* 109972 */ "PseudoVASUB_VX_MF8\0" + /* 109991 */ "PseudoVNMSUB_VX_MF8\0" + /* 110011 */ "PseudoVRSUB_VX_MF8\0" + /* 110030 */ "PseudoVSSUB_VX_MF8\0" + /* 110049 */ "PseudoVSUB_VX_MF8\0" + /* 110067 */ "PseudoVWSUB_VX_MF8\0" + /* 110086 */ "PseudoVNMSAC_VX_MF8\0" + /* 110106 */ "PseudoVMSBC_VX_MF8\0" + /* 110125 */ "PseudoVMACC_VX_MF8\0" + /* 110144 */ "PseudoVWMACC_VX_MF8\0" + /* 110164 */ "PseudoVMADC_VX_MF8\0" + /* 110183 */ "PseudoVAADD_VX_MF8\0" + /* 110202 */ "PseudoVMADD_VX_MF8\0" + /* 110221 */ "PseudoVSADD_VX_MF8\0" + /* 110240 */ "PseudoVADD_VX_MF8\0" + /* 110258 */ "PseudoVWADD_VX_MF8\0" + /* 110277 */ "PseudoVAND_VX_MF8\0" + /* 110295 */ "PseudoVMSLE_VX_MF8\0" + /* 110314 */ "PseudoVMSNE_VX_MF8\0" + /* 110333 */ "PseudoVMULH_VX_MF8\0" + /* 110352 */ "PseudoVSLL_VX_MF8\0" + /* 110370 */ "PseudoVSSRL_VX_MF8\0" + /* 110389 */ "PseudoVSRL_VX_MF8\0" + /* 110407 */ "PseudoVSMUL_VX_MF8\0" + /* 110426 */ "PseudoVMUL_VX_MF8\0" + /* 110444 */ "PseudoVWMUL_VX_MF8\0" + /* 110463 */ "PseudoVREM_VX_MF8\0" + /* 110481 */ "PseudoVMIN_VX_MF8\0" + /* 110499 */ "PseudoVSLIDE1DOWN_VX_MF8\0" + /* 110524 */ "PseudoVSLIDEDOWN_VX_MF8\0" + /* 110548 */ "PseudoVSLIDE1UP_VX_MF8\0" + /* 110571 */ "PseudoVSLIDEUP_VX_MF8\0" + /* 110593 */ "PseudoVMSEQ_VX_MF8\0" + /* 110612 */ "PseudoVRGATHER_VX_MF8\0" + /* 110634 */ "PseudoVOR_VX_MF8\0" + /* 110651 */ "PseudoVXOR_VX_MF8\0" + /* 110669 */ "PseudoVWMACCUS_VX_MF8\0" + /* 110691 */ "PseudoVMSGT_VX_MF8\0" + /* 110710 */ "PseudoVMSLT_VX_MF8\0" + /* 110729 */ "PseudoVASUBU_VX_MF8\0" + /* 110749 */ "PseudoVSSUBU_VX_MF8\0" + /* 110769 */ "PseudoVWSUBU_VX_MF8\0" + /* 110789 */ "PseudoVWMACCU_VX_MF8\0" + /* 110810 */ "PseudoVAADDU_VX_MF8\0" + /* 110830 */ "PseudoVSADDU_VX_MF8\0" + /* 110850 */ "PseudoVWADDU_VX_MF8\0" + /* 110870 */ "PseudoVMSLEU_VX_MF8\0" + /* 110890 */ "PseudoVMULHU_VX_MF8\0" + /* 110910 */ "PseudoVWMULU_VX_MF8\0" + /* 110930 */ "PseudoVREMU_VX_MF8\0" + /* 110949 */ "PseudoVMINU_VX_MF8\0" + /* 110968 */ "PseudoVWMACCSU_VX_MF8\0" + /* 110990 */ "PseudoVMULHSU_VX_MF8\0" + /* 111011 */ "PseudoVWMULSU_VX_MF8\0" + /* 111032 */ "PseudoVMSGTU_VX_MF8\0" + /* 111052 */ "PseudoVMSLTU_VX_MF8\0" + /* 111072 */ "PseudoVDIVU_VX_MF8\0" + /* 111091 */ "PseudoVMAXU_VX_MF8\0" + /* 111110 */ "PseudoVDIV_VX_MF8\0" + /* 111128 */ "PseudoVMAX_VX_MF8\0" + /* 111146 */ "PseudoVNSRA_WX_MF8\0" + /* 111165 */ "PseudoVWSUB_WX_MF8\0" + /* 111184 */ "PseudoVWADD_WX_MF8\0" + /* 111203 */ "PseudoVNSRL_WX_MF8\0" + /* 111222 */ "PseudoVNCLIP_WX_MF8\0" + /* 111242 */ "PseudoVWSUBU_WX_MF8\0" + /* 111262 */ "PseudoVWADDU_WX_MF8\0" + /* 111282 */ "PseudoVNCLIPU_WX_MF8\0" + /* 111303 */ "PseudoVMV_S_X_MF8\0" + /* 111321 */ "PseudoVMV_V_X_MF8\0" + /* 111339 */ "VSEXT_VF8\0" + /* 111349 */ "VZEXT_VF8\0" + /* 111359 */ "PseudoVLOXEI8_V_M1_M8\0" + /* 111381 */ "PseudoVSOXEI8_V_M1_M8\0" + /* 111403 */ "PseudoVLUXEI8_V_M1_M8\0" + /* 111425 */ "PseudoVSUXEI8_V_M1_M8\0" + /* 111447 */ "PseudoVFSUB_VF32_M8\0" + /* 111467 */ "PseudoVFMSUB_VF32_M8\0" + /* 111488 */ "PseudoVFNMSUB_VF32_M8\0" + /* 111510 */ "PseudoVFRSUB_VF32_M8\0" + /* 111531 */ "PseudoVFMSAC_VF32_M8\0" + /* 111552 */ "PseudoVFNMSAC_VF32_M8\0" + /* 111574 */ "PseudoVFMACC_VF32_M8\0" + /* 111595 */ "PseudoVFNMACC_VF32_M8\0" + /* 111617 */ "PseudoVFADD_VF32_M8\0" + /* 111637 */ "PseudoVFMADD_VF32_M8\0" + /* 111658 */ "PseudoVFNMADD_VF32_M8\0" + /* 111680 */ "PseudoVMFGE_VF32_M8\0" + /* 111700 */ "PseudoVMFLE_VF32_M8\0" + /* 111720 */ "PseudoVMFNE_VF32_M8\0" + /* 111740 */ "PseudoVFSGNJ_VF32_M8\0" + /* 111761 */ "PseudoVFMUL_VF32_M8\0" + /* 111781 */ "PseudoVFMIN_VF32_M8\0" + /* 111801 */ "PseudoVFSGNJN_VF32_M8\0" + /* 111823 */ "PseudoVFSLIDE1DOWN_VF32_M8\0" + /* 111850 */ "PseudoVFSLIDE1UP_VF32_M8\0" + /* 111875 */ "PseudoVMFEQ_VF32_M8\0" + /* 111895 */ "PseudoVMFGT_VF32_M8\0" + /* 111915 */ "PseudoVMFLT_VF32_M8\0" + /* 111935 */ "PseudoVFDIV_VF32_M8\0" + /* 111955 */ "PseudoVFRDIV_VF32_M8\0" + /* 111976 */ "PseudoVFMAX_VF32_M8\0" + /* 111996 */ "PseudoVFSGNJX_VF32_M8\0" + /* 112018 */ "PseudoVFMV_S_F32_M8\0" + /* 112038 */ "PseudoVFMV_V_F32_M8\0" + /* 112058 */ "PseudoVSEXT_VF2_M8\0" + /* 112077 */ "PseudoVZEXT_VF2_M8\0" + /* 112096 */ "PseudoVLOXEI16_V_M2_M8\0" + /* 112119 */ "PseudoVSOXEI16_V_M2_M8\0" + /* 112142 */ "PseudoVLUXEI16_V_M2_M8\0" + /* 112165 */ "PseudoVSUXEI16_V_M2_M8\0" + /* 112188 */ "PseudoVLOXEI8_V_M2_M8\0" + /* 112210 */ "PseudoVSOXEI8_V_M2_M8\0" + /* 112232 */ "PseudoVLUXEI8_V_M2_M8\0" + /* 112254 */ "PseudoVSUXEI8_V_M2_M8\0" + /* 112276 */ "PseudoVFSUB_VF64_M8\0" + /* 112296 */ "PseudoVFMSUB_VF64_M8\0" + /* 112317 */ "PseudoVFNMSUB_VF64_M8\0" + /* 112339 */ "PseudoVFRSUB_VF64_M8\0" + /* 112360 */ "PseudoVFMSAC_VF64_M8\0" + /* 112381 */ "PseudoVFNMSAC_VF64_M8\0" + /* 112403 */ "PseudoVFMACC_VF64_M8\0" + /* 112424 */ "PseudoVFNMACC_VF64_M8\0" + /* 112446 */ "PseudoVFADD_VF64_M8\0" + /* 112466 */ "PseudoVFMADD_VF64_M8\0" + /* 112487 */ "PseudoVFNMADD_VF64_M8\0" + /* 112509 */ "PseudoVMFGE_VF64_M8\0" + /* 112529 */ "PseudoVMFLE_VF64_M8\0" + /* 112549 */ "PseudoVMFNE_VF64_M8\0" + /* 112569 */ "PseudoVFSGNJ_VF64_M8\0" + /* 112590 */ "PseudoVFMUL_VF64_M8\0" + /* 112610 */ "PseudoVFMIN_VF64_M8\0" + /* 112630 */ "PseudoVFSGNJN_VF64_M8\0" + /* 112652 */ "PseudoVFSLIDE1DOWN_VF64_M8\0" + /* 112679 */ "PseudoVFSLIDE1UP_VF64_M8\0" + /* 112704 */ "PseudoVMFEQ_VF64_M8\0" + /* 112724 */ "PseudoVMFGT_VF64_M8\0" + /* 112744 */ "PseudoVMFLT_VF64_M8\0" + /* 112764 */ "PseudoVFDIV_VF64_M8\0" + /* 112784 */ "PseudoVFRDIV_VF64_M8\0" + /* 112805 */ "PseudoVFMAX_VF64_M8\0" + /* 112825 */ "PseudoVFSGNJX_VF64_M8\0" + /* 112847 */ "PseudoVFMV_S_F64_M8\0" + /* 112867 */ "PseudoVFMV_V_F64_M8\0" + /* 112887 */ "PseudoVSEXT_VF4_M8\0" + /* 112906 */ "PseudoVZEXT_VF4_M8\0" + /* 112925 */ "PseudoVAMOADDEI64_WD_M4_M8\0" + /* 112952 */ "PseudoVAMOANDEI64_WD_M4_M8\0" + /* 112979 */ "PseudoVAMOMINEI64_WD_M4_M8\0" + /* 113006 */ "PseudoVAMOSWAPEI64_WD_M4_M8\0" + /* 113034 */ "PseudoVAMOOREI64_WD_M4_M8\0" + /* 113060 */ "PseudoVAMOXOREI64_WD_M4_M8\0" + /* 113087 */ "PseudoVAMOMINUEI64_WD_M4_M8\0" + /* 113115 */ "PseudoVAMOMAXUEI64_WD_M4_M8\0" + /* 113143 */ "PseudoVAMOMAXEI64_WD_M4_M8\0" + /* 113170 */ "PseudoVRGATHEREI16_VV_M4_M8\0" + /* 113198 */ "PseudoVLOXEI32_V_M4_M8\0" + /* 113221 */ "PseudoVSOXEI32_V_M4_M8\0" + /* 113244 */ "PseudoVLUXEI32_V_M4_M8\0" + /* 113267 */ "PseudoVSUXEI32_V_M4_M8\0" + /* 113290 */ "PseudoVLOXEI16_V_M4_M8\0" + /* 113313 */ "PseudoVSOXEI16_V_M4_M8\0" + /* 113336 */ "PseudoVLUXEI16_V_M4_M8\0" + /* 113359 */ "PseudoVSUXEI16_V_M4_M8\0" + /* 113382 */ "PseudoVLOXEI8_V_M4_M8\0" + /* 113404 */ "PseudoVSOXEI8_V_M4_M8\0" + /* 113426 */ "PseudoVLUXEI8_V_M4_M8\0" + /* 113448 */ "PseudoVSUXEI8_V_M4_M8\0" + /* 113470 */ "PseudoVFSUB_VF16_M8\0" + /* 113490 */ "PseudoVFMSUB_VF16_M8\0" + /* 113511 */ "PseudoVFNMSUB_VF16_M8\0" + /* 113533 */ "PseudoVFRSUB_VF16_M8\0" + /* 113554 */ "PseudoVFMSAC_VF16_M8\0" + /* 113575 */ "PseudoVFNMSAC_VF16_M8\0" + /* 113597 */ "PseudoVFMACC_VF16_M8\0" + /* 113618 */ "PseudoVFNMACC_VF16_M8\0" + /* 113640 */ "PseudoVFADD_VF16_M8\0" + /* 113660 */ "PseudoVFMADD_VF16_M8\0" + /* 113681 */ "PseudoVFNMADD_VF16_M8\0" + /* 113703 */ "PseudoVMFGE_VF16_M8\0" + /* 113723 */ "PseudoVMFLE_VF16_M8\0" + /* 113743 */ "PseudoVMFNE_VF16_M8\0" + /* 113763 */ "PseudoVFSGNJ_VF16_M8\0" + /* 113784 */ "PseudoVFMUL_VF16_M8\0" + /* 113804 */ "PseudoVFMIN_VF16_M8\0" + /* 113824 */ "PseudoVFSGNJN_VF16_M8\0" + /* 113846 */ "PseudoVFSLIDE1DOWN_VF16_M8\0" + /* 113873 */ "PseudoVFSLIDE1UP_VF16_M8\0" + /* 113898 */ "PseudoVMFEQ_VF16_M8\0" + /* 113918 */ "PseudoVMFGT_VF16_M8\0" + /* 113938 */ "PseudoVMFLT_VF16_M8\0" + /* 113958 */ "PseudoVFDIV_VF16_M8\0" + /* 113978 */ "PseudoVFRDIV_VF16_M8\0" + /* 113999 */ "PseudoVFMAX_VF16_M8\0" + /* 114019 */ "PseudoVFSGNJX_VF16_M8\0" + /* 114041 */ "PseudoVFMV_S_F16_M8\0" + /* 114061 */ "PseudoVFMV_V_F16_M8\0" + /* 114081 */ "PseudoVSEXT_VF8_M8\0" + /* 114100 */ "PseudoVZEXT_VF8_M8\0" + /* 114119 */ "PseudoVAMOADDEI32_WD_M8_M8\0" + /* 114146 */ "PseudoVAMOANDEI32_WD_M8_M8\0" + /* 114173 */ "PseudoVAMOMINEI32_WD_M8_M8\0" + /* 114200 */ "PseudoVAMOSWAPEI32_WD_M8_M8\0" + /* 114228 */ "PseudoVAMOOREI32_WD_M8_M8\0" + /* 114254 */ "PseudoVAMOXOREI32_WD_M8_M8\0" + /* 114281 */ "PseudoVAMOMINUEI32_WD_M8_M8\0" + /* 114309 */ "PseudoVAMOMAXUEI32_WD_M8_M8\0" + /* 114337 */ "PseudoVAMOMAXEI32_WD_M8_M8\0" + /* 114364 */ "PseudoVAMOADDEI64_WD_M8_M8\0" + /* 114391 */ "PseudoVAMOANDEI64_WD_M8_M8\0" + /* 114418 */ "PseudoVAMOMINEI64_WD_M8_M8\0" + /* 114445 */ "PseudoVAMOSWAPEI64_WD_M8_M8\0" + /* 114473 */ "PseudoVAMOOREI64_WD_M8_M8\0" + /* 114499 */ "PseudoVAMOXOREI64_WD_M8_M8\0" + /* 114526 */ "PseudoVAMOMINUEI64_WD_M8_M8\0" + /* 114554 */ "PseudoVAMOMAXUEI64_WD_M8_M8\0" + /* 114582 */ "PseudoVAMOMAXEI64_WD_M8_M8\0" + /* 114609 */ "PseudoVRGATHEREI16_VV_M8_M8\0" + /* 114637 */ "PseudoVLOXEI32_V_M8_M8\0" + /* 114660 */ "PseudoVSOXEI32_V_M8_M8\0" + /* 114683 */ "PseudoVLUXEI32_V_M8_M8\0" + /* 114706 */ "PseudoVSUXEI32_V_M8_M8\0" + /* 114729 */ "PseudoVLOXEI64_V_M8_M8\0" + /* 114752 */ "PseudoVSOXEI64_V_M8_M8\0" + /* 114775 */ "PseudoVLUXEI64_V_M8_M8\0" + /* 114798 */ "PseudoVSUXEI64_V_M8_M8\0" + /* 114821 */ "PseudoVLOXEI16_V_M8_M8\0" + /* 114844 */ "PseudoVSOXEI16_V_M8_M8\0" + /* 114867 */ "PseudoVLUXEI16_V_M8_M8\0" + /* 114890 */ "PseudoVSUXEI16_V_M8_M8\0" + /* 114913 */ "PseudoVLOXEI8_V_M8_M8\0" + /* 114935 */ "PseudoVSOXEI8_V_M8_M8\0" + /* 114957 */ "PseudoVLUXEI8_V_M8_M8\0" + /* 114979 */ "PseudoVSUXEI8_V_M8_M8\0" + /* 115001 */ "PseudoVRELOAD_M8\0" + /* 115018 */ "PseudoVSSRA_VI_M8\0" + /* 115036 */ "PseudoVSRA_VI_M8\0" + /* 115053 */ "PseudoVRSUB_VI_M8\0" + /* 115071 */ "PseudoVMADC_VI_M8\0" + /* 115089 */ "PseudoVSADD_VI_M8\0" + /* 115107 */ "PseudoVADD_VI_M8\0" + /* 115124 */ "PseudoVAND_VI_M8\0" + /* 115141 */ "PseudoVMSLE_VI_M8\0" + /* 115159 */ "PseudoVMSNE_VI_M8\0" + /* 115177 */ "PseudoVSLL_VI_M8\0" + /* 115194 */ "PseudoVSSRL_VI_M8\0" + /* 115212 */ "PseudoVSRL_VI_M8\0" + /* 115229 */ "PseudoVSLIDEDOWN_VI_M8\0" + /* 115252 */ "PseudoVSLIDEUP_VI_M8\0" + /* 115273 */ "PseudoVMSEQ_VI_M8\0" + /* 115291 */ "PseudoVRGATHER_VI_M8\0" + /* 115312 */ "PseudoVOR_VI_M8\0" + /* 115328 */ "PseudoVXOR_VI_M8\0" + /* 115345 */ "PseudoVMSGT_VI_M8\0" + /* 115363 */ "PseudoVSADDU_VI_M8\0" + /* 115382 */ "PseudoVMSLEU_VI_M8\0" + /* 115401 */ "PseudoVMSGTU_VI_M8\0" + /* 115420 */ "PseudoVMV_V_I_M8\0" + /* 115437 */ "PseudoVSPILL_M8\0" + /* 115453 */ "PseudoVFMERGE_VF32M_M8\0" + /* 115476 */ "PseudoVFMERGE_VF64M_M8\0" + /* 115499 */ "PseudoVFMERGE_VF16M_M8\0" + /* 115522 */ "PseudoVMADC_VIM_M8\0" + /* 115541 */ "PseudoVADC_VIM_M8\0" + /* 115559 */ "PseudoVMERGE_VIM_M8\0" + /* 115579 */ "PseudoVMAND_MM_M8\0" + /* 115597 */ "PseudoVMNAND_MM_M8\0" + /* 115616 */ "PseudoVMANDN_MM_M8\0" + /* 115635 */ "PseudoVMORN_MM_M8\0" + /* 115653 */ "PseudoVMOR_MM_M8\0" + /* 115670 */ "PseudoVMNOR_MM_M8\0" + /* 115688 */ "PseudoVMXNOR_MM_M8\0" + /* 115707 */ "PseudoVMXOR_MM_M8\0" + /* 115725 */ "PseudoVMSBC_VVM_M8\0" + /* 115744 */ "PseudoVSBC_VVM_M8\0" + /* 115762 */ "PseudoVMADC_VVM_M8\0" + /* 115781 */ "PseudoVADC_VVM_M8\0" + /* 115799 */ "PseudoVMERGE_VVM_M8\0" + /* 115819 */ "PseudoVCOMPRESS_VM_M8\0" + /* 115841 */ "PseudoVMSBC_VXM_M8\0" + /* 115860 */ "PseudoVSBC_VXM_M8\0" + /* 115878 */ "PseudoVMADC_VXM_M8\0" + /* 115897 */ "PseudoVADC_VXM_M8\0" + /* 115915 */ "PseudoVMERGE_VXM_M8\0" + /* 115935 */ "PseudoVIOTA_M_M8\0" + /* 115952 */ "PseudoVREDAND_VS_M8\0" + /* 115972 */ "PseudoVREDSUM_VS_M8\0" + /* 115992 */ "PseudoVWREDSUM_VS_M8\0" + /* 116013 */ "PseudoVFREDOSUM_VS_M8\0" + /* 116035 */ "PseudoVFWREDOSUM_VS_M8\0" + /* 116058 */ "PseudoVFREDUSUM_VS_M8\0" + /* 116080 */ "PseudoVFWREDUSUM_VS_M8\0" + /* 116103 */ "PseudoVFREDMIN_VS_M8\0" + /* 116124 */ "PseudoVREDMIN_VS_M8\0" + /* 116144 */ "PseudoVREDOR_VS_M8\0" + /* 116163 */ "PseudoVREDXOR_VS_M8\0" + /* 116183 */ "PseudoVWREDSUMU_VS_M8\0" + /* 116205 */ "PseudoVREDMINU_VS_M8\0" + /* 116226 */ "PseudoVREDMAXU_VS_M8\0" + /* 116247 */ "PseudoVFREDMAX_VS_M8\0" + /* 116268 */ "PseudoVREDMAX_VS_M8\0" + /* 116288 */ "PseudoVFMV_F32_S_M8\0" + /* 116308 */ "PseudoVFMV_F64_S_M8\0" + /* 116328 */ "PseudoVFMV_F16_S_M8\0" + /* 116348 */ "PseudoVMV_X_S_M8\0" + /* 116365 */ "PseudoVSSRA_VV_M8\0" + /* 116383 */ "PseudoVSRA_VV_M8\0" + /* 116400 */ "PseudoVASUB_VV_M8\0" + /* 116418 */ "PseudoVFSUB_VV_M8\0" + /* 116436 */ "PseudoVFMSUB_VV_M8\0" + /* 116455 */ "PseudoVFNMSUB_VV_M8\0" + /* 116475 */ "PseudoVNMSUB_VV_M8\0" + /* 116494 */ "PseudoVSSUB_VV_M8\0" + /* 116512 */ "PseudoVSUB_VV_M8\0" + /* 116529 */ "PseudoVFMSAC_VV_M8\0" + /* 116548 */ "PseudoVFNMSAC_VV_M8\0" + /* 116568 */ "PseudoVNMSAC_VV_M8\0" + /* 116587 */ "PseudoVMSBC_VV_M8\0" + /* 116605 */ "PseudoVFMACC_VV_M8\0" + /* 116624 */ "PseudoVFNMACC_VV_M8\0" + /* 116644 */ "PseudoVMACC_VV_M8\0" + /* 116662 */ "PseudoVMADC_VV_M8\0" + /* 116680 */ "PseudoVAADD_VV_M8\0" + /* 116698 */ "PseudoVFADD_VV_M8\0" + /* 116716 */ "PseudoVFMADD_VV_M8\0" + /* 116735 */ "PseudoVFNMADD_VV_M8\0" + /* 116755 */ "PseudoVMADD_VV_M8\0" + /* 116773 */ "PseudoVSADD_VV_M8\0" + /* 116791 */ "PseudoVADD_VV_M8\0" + /* 116808 */ "PseudoVAND_VV_M8\0" + /* 116825 */ "PseudoVMFLE_VV_M8\0" + /* 116843 */ "PseudoVMSLE_VV_M8\0" + /* 116861 */ "PseudoVMFNE_VV_M8\0" + /* 116879 */ "PseudoVMSNE_VV_M8\0" + /* 116897 */ "PseudoVMULH_VV_M8\0" + /* 116915 */ "PseudoVFSGNJ_VV_M8\0" + /* 116934 */ "PseudoVSLL_VV_M8\0" + /* 116951 */ "PseudoVSSRL_VV_M8\0" + /* 116969 */ "PseudoVSRL_VV_M8\0" + /* 116986 */ "PseudoVFMUL_VV_M8\0" + /* 117004 */ "PseudoVSMUL_VV_M8\0" + /* 117022 */ "PseudoVMUL_VV_M8\0" + /* 117039 */ "PseudoVREM_VV_M8\0" + /* 117056 */ "PseudoVFMIN_VV_M8\0" + /* 117074 */ "PseudoVMIN_VV_M8\0" + /* 117091 */ "PseudoVFSGNJN_VV_M8\0" + /* 117111 */ "PseudoVMFEQ_VV_M8\0" + /* 117129 */ "PseudoVMSEQ_VV_M8\0" + /* 117147 */ "PseudoVRGATHER_VV_M8\0" + /* 117168 */ "PseudoVOR_VV_M8\0" + /* 117184 */ "PseudoVXOR_VV_M8\0" + /* 117201 */ "PseudoVMFLT_VV_M8\0" + /* 117219 */ "PseudoVMSLT_VV_M8\0" + /* 117237 */ "PseudoVASUBU_VV_M8\0" + /* 117256 */ "PseudoVSSUBU_VV_M8\0" + /* 117275 */ "PseudoVAADDU_VV_M8\0" + /* 117294 */ "PseudoVSADDU_VV_M8\0" + /* 117313 */ "PseudoVMSLEU_VV_M8\0" + /* 117332 */ "PseudoVMULHU_VV_M8\0" + /* 117351 */ "PseudoVREMU_VV_M8\0" + /* 117369 */ "PseudoVMINU_VV_M8\0" + /* 117387 */ "PseudoVMULHSU_VV_M8\0" + /* 117407 */ "PseudoVMSLTU_VV_M8\0" + /* 117426 */ "PseudoVDIVU_VV_M8\0" + /* 117444 */ "PseudoVMAXU_VV_M8\0" + /* 117462 */ "PseudoVFDIV_VV_M8\0" + /* 117480 */ "PseudoVDIV_VV_M8\0" + /* 117497 */ "PseudoVFMAX_VV_M8\0" + /* 117515 */ "PseudoVMAX_VV_M8\0" + /* 117532 */ "PseudoVFSGNJX_VV_M8\0" + /* 117552 */ "PseudoVLE32_V_M8\0" + /* 117569 */ "PseudoVLSE32_V_M8\0" + /* 117587 */ "PseudoVSSE32_V_M8\0" + /* 117605 */ "PseudoVSE32_V_M8\0" + /* 117622 */ "PseudoVLE64_V_M8\0" + /* 117639 */ "PseudoVLSE64_V_M8\0" + /* 117657 */ "PseudoVSSE64_V_M8\0" + /* 117675 */ "PseudoVSE64_V_M8\0" + /* 117692 */ "PseudoVLE16_V_M8\0" + /* 117709 */ "PseudoVLSE16_V_M8\0" + /* 117727 */ "PseudoVSSE16_V_M8\0" + /* 117745 */ "PseudoVSE16_V_M8\0" + /* 117762 */ "PseudoVFREC7_V_M8\0" + /* 117780 */ "PseudoVFRSQRT7_V_M8\0" + /* 117800 */ "PseudoVLE8_V_M8\0" + /* 117816 */ "PseudoVLSE8_V_M8\0" + /* 117833 */ "PseudoVSSE8_V_M8\0" + /* 117850 */ "PseudoVSE8_V_M8\0" + /* 117866 */ "PseudoVID_V_M8\0" + /* 117881 */ "PseudoVLE32FF_V_M8\0" + /* 117900 */ "PseudoVLE64FF_V_M8\0" + /* 117919 */ "PseudoVLE16FF_V_M8\0" + /* 117938 */ "PseudoVLE8FF_V_M8\0" + /* 117956 */ "PseudoVFCVT_XU_F_V_M8\0" + /* 117978 */ "PseudoVFCVT_RTZ_XU_F_V_M8\0" + /* 118004 */ "PseudoVFCVT_X_F_V_M8\0" + /* 118025 */ "PseudoVFCVT_RTZ_X_F_V_M8\0" + /* 118050 */ "PseudoVFCLASS_V_M8\0" + /* 118069 */ "PseudoVFSQRT_V_M8\0" + /* 118087 */ "PseudoVFCVT_F_XU_V_M8\0" + /* 118109 */ "PseudoVMV_V_V_M8\0" + /* 118126 */ "PseudoVFCVT_F_X_V_M8\0" + /* 118147 */ "PseudoVSSRA_VX_M8\0" + /* 118165 */ "PseudoVSRA_VX_M8\0" + /* 118182 */ "PseudoVASUB_VX_M8\0" + /* 118200 */ "PseudoVNMSUB_VX_M8\0" + /* 118219 */ "PseudoVRSUB_VX_M8\0" + /* 118237 */ "PseudoVSSUB_VX_M8\0" + /* 118255 */ "PseudoVSUB_VX_M8\0" + /* 118272 */ "PseudoVNMSAC_VX_M8\0" + /* 118291 */ "PseudoVMSBC_VX_M8\0" + /* 118309 */ "PseudoVMACC_VX_M8\0" + /* 118327 */ "PseudoVMADC_VX_M8\0" + /* 118345 */ "PseudoVAADD_VX_M8\0" + /* 118363 */ "PseudoVMADD_VX_M8\0" + /* 118381 */ "PseudoVSADD_VX_M8\0" + /* 118399 */ "PseudoVADD_VX_M8\0" + /* 118416 */ "PseudoVAND_VX_M8\0" + /* 118433 */ "PseudoVMSLE_VX_M8\0" + /* 118451 */ "PseudoVMSNE_VX_M8\0" + /* 118469 */ "PseudoVMULH_VX_M8\0" + /* 118487 */ "PseudoVSLL_VX_M8\0" + /* 118504 */ "PseudoVSSRL_VX_M8\0" + /* 118522 */ "PseudoVSRL_VX_M8\0" + /* 118539 */ "PseudoVSMUL_VX_M8\0" + /* 118557 */ "PseudoVMUL_VX_M8\0" + /* 118574 */ "PseudoVREM_VX_M8\0" + /* 118591 */ "PseudoVMIN_VX_M8\0" + /* 118608 */ "PseudoVSLIDE1DOWN_VX_M8\0" + /* 118632 */ "PseudoVSLIDEDOWN_VX_M8\0" + /* 118655 */ "PseudoVSLIDE1UP_VX_M8\0" + /* 118677 */ "PseudoVSLIDEUP_VX_M8\0" + /* 118698 */ "PseudoVMSEQ_VX_M8\0" + /* 118716 */ "PseudoVRGATHER_VX_M8\0" + /* 118737 */ "PseudoVOR_VX_M8\0" + /* 118753 */ "PseudoVXOR_VX_M8\0" + /* 118770 */ "PseudoVMSGT_VX_M8\0" + /* 118788 */ "PseudoVMSLT_VX_M8\0" + /* 118806 */ "PseudoVASUBU_VX_M8\0" + /* 118825 */ "PseudoVSSUBU_VX_M8\0" + /* 118844 */ "PseudoVAADDU_VX_M8\0" + /* 118863 */ "PseudoVSADDU_VX_M8\0" + /* 118882 */ "PseudoVMSLEU_VX_M8\0" + /* 118901 */ "PseudoVMULHU_VX_M8\0" + /* 118920 */ "PseudoVREMU_VX_M8\0" + /* 118938 */ "PseudoVMINU_VX_M8\0" + /* 118956 */ "PseudoVMULHSU_VX_M8\0" + /* 118976 */ "PseudoVMSGTU_VX_M8\0" + /* 118995 */ "PseudoVMSLTU_VX_M8\0" + /* 119014 */ "PseudoVDIVU_VX_M8\0" + /* 119032 */ "PseudoVMAXU_VX_M8\0" + /* 119050 */ "PseudoVDIV_VX_M8\0" + /* 119067 */ "PseudoVMAX_VX_M8\0" + /* 119084 */ "PseudoVMV_S_X_M8\0" + /* 119101 */ "PseudoVMV_V_X_M8\0" + /* 119118 */ "PseudoLLA\0" + /* 119128 */ "PseudoLA\0" + /* 119137 */ "G_FMA\0" + /* 119143 */ "G_STRICT_FMA\0" + /* 119156 */ "SFENCE_VMA\0" + /* 119167 */ "SRA\0" + /* 119171 */ "CRC32B\0" + /* 119178 */ "CRC32CB\0" + /* 119186 */ "ORCB\0" + /* 119191 */ "PseudoLB\0" + /* 119200 */ "XPERMB\0" + /* 119207 */ "PseudoReadVLENB\0" + /* 119223 */ "PseudoSB\0" + /* 119232 */ "SEXTB\0" + /* 119238 */ "G_FSUB\0" + /* 119245 */ "G_STRICT_FSUB\0" + /* 119259 */ "G_ATOMICRMW_FSUB\0" + /* 119276 */ "C_SUB\0" + /* 119282 */ "G_SUB\0" + /* 119288 */ "G_ATOMICRMW_SUB\0" + /* 119304 */ "PseudoSEXT_B\0" + /* 119317 */ "InsnB\0" + /* 119323 */ "G_INTRINSIC\0" + /* 119335 */ "G_FPTRUNC\0" + /* 119345 */ "G_INTRINSIC_TRUNC\0" + /* 119363 */ "G_TRUNC\0" + /* 119371 */ "G_BUILD_VECTOR_TRUNC\0" + /* 119392 */ "G_DYN_STACKALLOC\0" + /* 119409 */ "AUIPC\0" + /* 119415 */ "GORC\0" + /* 119420 */ "CSRRC\0" + /* 119426 */ "CRC32D\0" + /* 119433 */ "G_FMAD\0" + /* 119440 */ "G_INDEXED_SEXTLOAD\0" + /* 119459 */ "G_SEXTLOAD\0" + /* 119470 */ "G_INDEXED_ZEXTLOAD\0" + /* 119489 */ "G_ZEXTLOAD\0" + /* 119500 */ "G_INDEXED_LOAD\0" + /* 119515 */ "G_LOAD\0" + /* 119522 */ "CRC32CD\0" + /* 119530 */ "SH1ADD\0" + /* 119537 */ "SH2ADD\0" + /* 119544 */ "SH3ADD\0" + /* 119551 */ "G_VECREDUCE_FADD\0" + /* 119568 */ "G_FADD\0" + /* 119575 */ "G_VECREDUCE_SEQ_FADD\0" + /* 119596 */ "G_STRICT_FADD\0" + /* 119610 */ "G_ATOMICRMW_FADD\0" + /* 119627 */ "C_ADD\0" + /* 119633 */ "G_VECREDUCE_ADD\0" + /* 119649 */ "G_ADD\0" + /* 119655 */ "G_PTR_ADD\0" + /* 119665 */ "G_ATOMICRMW_ADD\0" + /* 119681 */ "PseudoVFWSUB_WV_M1_TIED\0" + /* 119705 */ "PseudoVWSUB_WV_M1_TIED\0" + /* 119728 */ "PseudoVFWADD_WV_M1_TIED\0" + /* 119752 */ "PseudoVWADD_WV_M1_TIED\0" + /* 119775 */ "PseudoVWSUBU_WV_M1_TIED\0" + /* 119799 */ "PseudoVWADDU_WV_M1_TIED\0" + /* 119823 */ "PseudoVFWSUB_WV_MF2_TIED\0" + /* 119848 */ "PseudoVWSUB_WV_MF2_TIED\0" + /* 119872 */ "PseudoVFWADD_WV_MF2_TIED\0" + /* 119897 */ "PseudoVWADD_WV_MF2_TIED\0" + /* 119921 */ "PseudoVWSUBU_WV_MF2_TIED\0" + /* 119946 */ "PseudoVWADDU_WV_MF2_TIED\0" + /* 119971 */ "PseudoVFWSUB_WV_M2_TIED\0" + /* 119995 */ "PseudoVWSUB_WV_M2_TIED\0" + /* 120018 */ "PseudoVFWADD_WV_M2_TIED\0" + /* 120042 */ "PseudoVWADD_WV_M2_TIED\0" + /* 120065 */ "PseudoVWSUBU_WV_M2_TIED\0" + /* 120089 */ "PseudoVWADDU_WV_M2_TIED\0" + /* 120113 */ "PseudoVFWSUB_WV_MF4_TIED\0" + /* 120138 */ "PseudoVWSUB_WV_MF4_TIED\0" + /* 120162 */ "PseudoVFWADD_WV_MF4_TIED\0" + /* 120187 */ "PseudoVWADD_WV_MF4_TIED\0" + /* 120211 */ "PseudoVWSUBU_WV_MF4_TIED\0" + /* 120236 */ "PseudoVWADDU_WV_MF4_TIED\0" + /* 120261 */ "PseudoVFWSUB_WV_M4_TIED\0" + /* 120285 */ "PseudoVWSUB_WV_M4_TIED\0" + /* 120308 */ "PseudoVFWADD_WV_M4_TIED\0" + /* 120332 */ "PseudoVWADD_WV_M4_TIED\0" + /* 120355 */ "PseudoVWSUBU_WV_M4_TIED\0" + /* 120379 */ "PseudoVWADDU_WV_M4_TIED\0" + /* 120403 */ "PseudoVFWSUB_WV_MF8_TIED\0" + /* 120428 */ "PseudoVWSUB_WV_MF8_TIED\0" + /* 120452 */ "PseudoVFWADD_WV_MF8_TIED\0" + /* 120477 */ "PseudoVWADD_WV_MF8_TIED\0" + /* 120501 */ "PseudoVWSUBU_WV_MF8_TIED\0" + /* 120526 */ "PseudoVWADDU_WV_MF8_TIED\0" + /* 120551 */ "PseudoVFWSUB_WV_M1_MASK_TIED\0" + /* 120580 */ "PseudoVWSUB_WV_M1_MASK_TIED\0" + /* 120608 */ "PseudoVFWADD_WV_M1_MASK_TIED\0" + /* 120637 */ "PseudoVWADD_WV_M1_MASK_TIED\0" + /* 120665 */ "PseudoVWSUBU_WV_M1_MASK_TIED\0" + /* 120694 */ "PseudoVWADDU_WV_M1_MASK_TIED\0" + /* 120723 */ "PseudoVFWSUB_WV_MF2_MASK_TIED\0" + /* 120753 */ "PseudoVWSUB_WV_MF2_MASK_TIED\0" + /* 120782 */ "PseudoVFWADD_WV_MF2_MASK_TIED\0" + /* 120812 */ "PseudoVWADD_WV_MF2_MASK_TIED\0" + /* 120841 */ "PseudoVWSUBU_WV_MF2_MASK_TIED\0" + /* 120871 */ "PseudoVWADDU_WV_MF2_MASK_TIED\0" + /* 120901 */ "PseudoVFWSUB_WV_M2_MASK_TIED\0" + /* 120930 */ "PseudoVWSUB_WV_M2_MASK_TIED\0" + /* 120958 */ "PseudoVFWADD_WV_M2_MASK_TIED\0" + /* 120987 */ "PseudoVWADD_WV_M2_MASK_TIED\0" + /* 121015 */ "PseudoVWSUBU_WV_M2_MASK_TIED\0" + /* 121044 */ "PseudoVWADDU_WV_M2_MASK_TIED\0" + /* 121073 */ "PseudoVFWSUB_WV_MF4_MASK_TIED\0" + /* 121103 */ "PseudoVWSUB_WV_MF4_MASK_TIED\0" + /* 121132 */ "PseudoVFWADD_WV_MF4_MASK_TIED\0" + /* 121162 */ "PseudoVWADD_WV_MF4_MASK_TIED\0" + /* 121191 */ "PseudoVWSUBU_WV_MF4_MASK_TIED\0" + /* 121221 */ "PseudoVWADDU_WV_MF4_MASK_TIED\0" + /* 121251 */ "PseudoVFWSUB_WV_M4_MASK_TIED\0" + /* 121280 */ "PseudoVWSUB_WV_M4_MASK_TIED\0" + /* 121308 */ "PseudoVFWADD_WV_M4_MASK_TIED\0" + /* 121337 */ "PseudoVWADD_WV_M4_MASK_TIED\0" + /* 121365 */ "PseudoVWSUBU_WV_M4_MASK_TIED\0" + /* 121394 */ "PseudoVWADDU_WV_M4_MASK_TIED\0" + /* 121423 */ "PseudoVFWSUB_WV_MF8_MASK_TIED\0" + /* 121453 */ "PseudoVWSUB_WV_MF8_MASK_TIED\0" + /* 121482 */ "PseudoVFWADD_WV_MF8_MASK_TIED\0" + /* 121512 */ "PseudoVWADD_WV_MF8_MASK_TIED\0" + /* 121541 */ "PseudoVWSUBU_WV_MF8_MASK_TIED\0" + /* 121571 */ "PseudoVWADDU_WV_MF8_MASK_TIED\0" + /* 121601 */ "PseudoLA_TLS_GD\0" + /* 121617 */ "C_FLD\0" + /* 121623 */ "PseudoFLD\0" + /* 121633 */ "C_LD\0" + /* 121638 */ "PseudoLD\0" + /* 121647 */ "G_ATOMICRMW_NAND\0" + /* 121664 */ "C_AND\0" + /* 121670 */ "G_VECREDUCE_AND\0" + /* 121686 */ "G_AND\0" + /* 121692 */ "G_ATOMICRMW_AND\0" + /* 121708 */ "LIFETIME_END\0" + /* 121721 */ "PseudoBRIND\0" + /* 121733 */ "G_BRCOND\0" + /* 121742 */ "G_LLROUND\0" + /* 121752 */ "G_LROUND\0" + /* 121761 */ "G_INTRINSIC_ROUND\0" + /* 121779 */ "LOAD_STACK_GUARD\0" + /* 121796 */ "C_FSD\0" + /* 121802 */ "PseudoFSD\0" + /* 121812 */ "C_SD\0" + /* 121817 */ "PseudoSD\0" + /* 121826 */ "VAMOADDEI32_UNWD\0" + /* 121843 */ "VAMOANDEI32_UNWD\0" + /* 121860 */ "VAMOMINEI32_UNWD\0" + /* 121877 */ "VAMOSWAPEI32_UNWD\0" + /* 121895 */ "VAMOOREI32_UNWD\0" + /* 121911 */ "VAMOXOREI32_UNWD\0" + /* 121928 */ "VAMOMINUEI32_UNWD\0" + /* 121946 */ "VAMOMAXUEI32_UNWD\0" + /* 121964 */ "VAMOMAXEI32_UNWD\0" + /* 121981 */ "VAMOADDEI64_UNWD\0" + /* 121998 */ "VAMOANDEI64_UNWD\0" + /* 122015 */ "VAMOMINEI64_UNWD\0" + /* 122032 */ "VAMOSWAPEI64_UNWD\0" + /* 122050 */ "VAMOOREI64_UNWD\0" + /* 122066 */ "VAMOXOREI64_UNWD\0" + /* 122083 */ "VAMOMINUEI64_UNWD\0" + /* 122101 */ "VAMOMAXUEI64_UNWD\0" + /* 122119 */ "VAMOMAXEI64_UNWD\0" + /* 122136 */ "VAMOADDEI16_UNWD\0" + /* 122153 */ "VAMOANDEI16_UNWD\0" + /* 122170 */ "VAMOMINEI16_UNWD\0" + /* 122187 */ "VAMOSWAPEI16_UNWD\0" + /* 122205 */ "VAMOOREI16_UNWD\0" + /* 122221 */ "VAMOXOREI16_UNWD\0" + /* 122238 */ "VAMOMINUEI16_UNWD\0" + /* 122256 */ "VAMOMAXUEI16_UNWD\0" + /* 122274 */ "VAMOMAXEI16_UNWD\0" + /* 122291 */ "VAMOADDEI8_UNWD\0" + /* 122307 */ "VAMOANDEI8_UNWD\0" + /* 122323 */ "VAMOMINEI8_UNWD\0" + /* 122339 */ "VAMOSWAPEI8_UNWD\0" + /* 122356 */ "VAMOOREI8_UNWD\0" + /* 122371 */ "VAMOXOREI8_UNWD\0" + /* 122387 */ "VAMOMINUEI8_UNWD\0" + /* 122404 */ "VAMOMAXUEI8_UNWD\0" + /* 122421 */ "VAMOMAXEI8_UNWD\0" + /* 122437 */ "VAMOADDEI32_WD\0" + /* 122452 */ "VAMOANDEI32_WD\0" + /* 122467 */ "VAMOMINEI32_WD\0" + /* 122482 */ "VAMOSWAPEI32_WD\0" + /* 122498 */ "VAMOOREI32_WD\0" + /* 122512 */ "VAMOXOREI32_WD\0" + /* 122527 */ "VAMOMINUEI32_WD\0" + /* 122543 */ "VAMOMAXUEI32_WD\0" + /* 122559 */ "VAMOMAXEI32_WD\0" + /* 122574 */ "VAMOADDEI64_WD\0" + /* 122589 */ "VAMOANDEI64_WD\0" + /* 122604 */ "VAMOMINEI64_WD\0" + /* 122619 */ "VAMOSWAPEI64_WD\0" + /* 122635 */ "VAMOOREI64_WD\0" + /* 122649 */ "VAMOXOREI64_WD\0" + /* 122664 */ "VAMOMINUEI64_WD\0" + /* 122680 */ "VAMOMAXUEI64_WD\0" + /* 122696 */ "VAMOMAXEI64_WD\0" + /* 122711 */ "VAMOADDEI16_WD\0" + /* 122726 */ "VAMOANDEI16_WD\0" + /* 122741 */ "VAMOMINEI16_WD\0" + /* 122756 */ "VAMOSWAPEI16_WD\0" + /* 122772 */ "VAMOOREI16_WD\0" + /* 122786 */ "VAMOXOREI16_WD\0" + /* 122801 */ "VAMOMINUEI16_WD\0" + /* 122817 */ "VAMOMAXUEI16_WD\0" + /* 122833 */ "VAMOMAXEI16_WD\0" + /* 122848 */ "VAMOADDEI8_WD\0" + /* 122862 */ "VAMOANDEI8_WD\0" + /* 122876 */ "VAMOMINEI8_WD\0" + /* 122890 */ "VAMOSWAPEI8_WD\0" + /* 122905 */ "VAMOOREI8_WD\0" + /* 122918 */ "VAMOXOREI8_WD\0" + /* 122932 */ "VAMOMINUEI8_WD\0" + /* 122947 */ "VAMOMAXUEI8_WD\0" + /* 122962 */ "VAMOMAXEI8_WD\0" + /* 122976 */ "FSUB_D\0" + /* 122983 */ "FMSUB_D\0" + /* 122991 */ "FNMSUB_D\0" + /* 123000 */ "SC_D\0" + /* 123005 */ "FADD_D\0" + /* 123012 */ "FMADD_D\0" + /* 123020 */ "FNMADD_D\0" + /* 123029 */ "AMOADD_D\0" + /* 123038 */ "AMOAND_D\0" + /* 123047 */ "FLE_D\0" + /* 123053 */ "FCVT_H_D\0" + /* 123062 */ "FSGNJ_D\0" + /* 123070 */ "FMUL_D\0" + /* 123077 */ "FCVT_L_D\0" + /* 123086 */ "FMIN_D\0" + /* 123093 */ "AMOMIN_D\0" + /* 123102 */ "FSGNJN_D\0" + /* 123111 */ "AMOSWAP_D\0" + /* 123121 */ "FEQ_D\0" + /* 123127 */ "LR_D\0" + /* 123132 */ "AMOOR_D\0" + /* 123140 */ "AMOXOR_D\0" + /* 123149 */ "FCLASS_D\0" + /* 123158 */ "FCVT_S_D\0" + /* 123167 */ "FLT_D\0" + /* 123173 */ "FSQRT_D\0" + /* 123181 */ "FCVT_LU_D\0" + /* 123191 */ "AMOMINU_D\0" + /* 123201 */ "FCVT_WU_D\0" + /* 123211 */ "AMOMAXU_D\0" + /* 123221 */ "FDIV_D\0" + /* 123228 */ "FCVT_W_D\0" + /* 123237 */ "FMAX_D\0" + /* 123244 */ "AMOMAX_D\0" + /* 123253 */ "FSGNJX_D\0" + /* 123262 */ "FMV_X_D\0" + /* 123270 */ "PSEUDO_PROBE\0" + /* 123283 */ "G_SSUBE\0" + /* 123291 */ "G_USUBE\0" + /* 123299 */ "G_FENCE\0" + /* 123307 */ "ARITH_FENCE\0" + /* 123319 */ "REG_SEQUENCE\0" + /* 123332 */ "G_SADDE\0" + /* 123340 */ "G_UADDE\0" + /* 123348 */ "G_FMINNUM_IEEE\0" + /* 123363 */ "G_FMAXNUM_IEEE\0" + /* 123378 */ "BGE\0" + /* 123382 */ "PseudoLA_TLS_IE\0" + /* 123398 */ "G_JUMP_TABLE\0" + /* 123411 */ "BUNDLE\0" + /* 123418 */ "BNE\0" + /* 123422 */ "G_MEMCPY_INLINE\0" + /* 123438 */ "LOCAL_ESCAPE\0" + /* 123451 */ "G_INDEXED_STORE\0" + /* 123467 */ "G_STORE\0" + /* 123475 */ "G_BITREVERSE\0" + /* 123488 */ "DBG_VALUE\0" + /* 123498 */ "G_GLOBAL_VALUE\0" + /* 123513 */ "G_MEMMOVE\0" + /* 123523 */ "G_FREEZE\0" + /* 123532 */ "G_FCANONICALIZE\0" + /* 123548 */ "G_CTLZ_ZERO_UNDEF\0" + /* 123566 */ "G_CTTZ_ZERO_UNDEF\0" + /* 123584 */ "G_IMPLICIT_DEF\0" + /* 123599 */ "DBG_INSTR_REF\0" + /* 123613 */ "VFSUB_VF\0" + /* 123622 */ "VFMSUB_VF\0" + /* 123632 */ "VFNMSUB_VF\0" + /* 123643 */ "VFRSUB_VF\0" + /* 123653 */ "VFWSUB_VF\0" + /* 123663 */ "VFMSAC_VF\0" + /* 123673 */ "VFNMSAC_VF\0" + /* 123684 */ "VFWNMSAC_VF\0" + /* 123696 */ "VFWMSAC_VF\0" + /* 123707 */ "VFMACC_VF\0" + /* 123717 */ "VFNMACC_VF\0" + /* 123728 */ "VFWNMACC_VF\0" + /* 123740 */ "VFWMACC_VF\0" + /* 123751 */ "VFADD_VF\0" + /* 123760 */ "VFMADD_VF\0" + /* 123770 */ "VFNMADD_VF\0" + /* 123781 */ "VFWADD_VF\0" + /* 123791 */ "VMFGE_VF\0" + /* 123800 */ "VMFLE_VF\0" + /* 123809 */ "VMFNE_VF\0" + /* 123818 */ "VFSGNJ_VF\0" + /* 123828 */ "VFMUL_VF\0" + /* 123837 */ "VFWMUL_VF\0" + /* 123847 */ "VFMIN_VF\0" + /* 123856 */ "VFSGNJN_VF\0" + /* 123867 */ "VFSLIDE1DOWN_VF\0" + /* 123883 */ "VFSLIDE1UP_VF\0" + /* 123897 */ "VMFEQ_VF\0" + /* 123906 */ "VMFGT_VF\0" + /* 123915 */ "VMFLT_VF\0" + /* 123924 */ "VFDIV_VF\0" + /* 123933 */ "VFRDIV_VF\0" + /* 123943 */ "VFMAX_VF\0" + /* 123952 */ "VFSGNJX_VF\0" + /* 123963 */ "VFWSUB_WF\0" + /* 123973 */ "VFWADD_WF\0" + /* 123983 */ "VFMV_S_F\0" + /* 123992 */ "VFMV_V_F\0" + /* 124001 */ "G_FNEG\0" + /* 124008 */ "EXTRACT_SUBREG\0" + /* 124023 */ "INSERT_SUBREG\0" + /* 124037 */ "G_SEXT_INREG\0" + /* 124050 */ "SUBREG_TO_REG\0" + /* 124064 */ "G_ATOMIC_CMPXCHG\0" + /* 124081 */ "G_ATOMICRMW_XCHG\0" + /* 124098 */ "G_FLOG\0" + /* 124105 */ "G_VAARG\0" + /* 124113 */ "PREALLOCATED_ARG\0" + /* 124130 */ "CRC32H\0" + /* 124137 */ "CRC32CH\0" + /* 124145 */ "PACKH\0" + /* 124151 */ "PseudoFLH\0" + /* 124161 */ "CLMULH\0" + /* 124168 */ "G_SMULH\0" + /* 124176 */ "G_UMULH\0" + /* 124184 */ "PseudoLH\0" + /* 124193 */ "XPERMH\0" + /* 124200 */ "PseudoFSH\0" + /* 124210 */ "PseudoSH\0" + /* 124219 */ "SEXTH\0" + /* 124225 */ "FSUB_H\0" + /* 124232 */ "FMSUB_H\0" + /* 124240 */ "FNMSUB_H\0" + /* 124249 */ "FADD_H\0" + /* 124256 */ "FMADD_H\0" + /* 124264 */ "FNMADD_H\0" + /* 124273 */ "FCVT_D_H\0" + /* 124282 */ "FLE_H\0" + /* 124288 */ "FSGNJ_H\0" + /* 124296 */ "FMUL_H\0" + /* 124303 */ "FCVT_L_H\0" + /* 124312 */ "FMIN_H\0" + /* 124319 */ "FSGNJN_H\0" + /* 124328 */ "FEQ_H\0" + /* 124334 */ "FCLASS_H\0" + /* 124343 */ "FCVT_S_H\0" + /* 124352 */ "FLT_H\0" + /* 124358 */ "FSQRT_H\0" + /* 124366 */ "PseudoSEXT_H\0" + /* 124379 */ "PseudoZEXT_H\0" + /* 124392 */ "FCVT_LU_H\0" + /* 124402 */ "FCVT_WU_H\0" + /* 124412 */ "FDIV_H\0" + /* 124419 */ "FCVT_W_H\0" + /* 124428 */ "FMAX_H\0" + /* 124435 */ "FSGNJX_H\0" + /* 124444 */ "FMV_X_H\0" + /* 124452 */ "C_SRAI\0" + /* 124459 */ "GORCI\0" + /* 124465 */ "CSRRCI\0" + /* 124472 */ "C_ADDI\0" + /* 124479 */ "C_ANDI\0" + /* 124486 */ "WFI\0" + /* 124490 */ "DBG_PHI\0" + /* 124498 */ "UNSHFLI\0" + /* 124506 */ "C_SLLI\0" + /* 124513 */ "C_SRLI\0" + /* 124520 */ "PseudoVSETIVLI\0" + /* 124535 */ "PseudoVSETVLI\0" + /* 124549 */ "C_LI\0" + /* 124554 */ "PseudoLI\0" + /* 124563 */ "BCLRI\0" + /* 124569 */ "RORI\0" + /* 124574 */ "XORI\0" + /* 124579 */ "FSRI\0" + /* 124584 */ "G_FPTOSI\0" + /* 124593 */ "CSRRSI\0" + /* 124600 */ "BSETI\0" + /* 124606 */ "SLTI\0" + /* 124611 */ "BEXTI\0" + /* 124617 */ "C_LUI\0" + /* 124623 */ "G_FPTOUI\0" + /* 124632 */ "GREVI\0" + /* 124638 */ "BINVI\0" + /* 124644 */ "VSSRA_VI\0" + /* 124653 */ "VSRA_VI\0" + /* 124661 */ "VRSUB_VI\0" + /* 124670 */ "VMADC_VI\0" + /* 124679 */ "VSADD_VI\0" + /* 124688 */ "VADD_VI\0" + /* 124696 */ "VAND_VI\0" + /* 124704 */ "PseudoVMSGE_VI\0" + /* 124719 */ "VMSLE_VI\0" + /* 124728 */ "VMSNE_VI\0" + /* 124737 */ "VSLL_VI\0" + /* 124745 */ "VSSRL_VI\0" + /* 124754 */ "VSRL_VI\0" + /* 124762 */ "VSLIDEDOWN_VI\0" + /* 124776 */ "VSLIDEUP_VI\0" + /* 124788 */ "VMSEQ_VI\0" + /* 124797 */ "VRGATHER_VI\0" + /* 124809 */ "VOR_VI\0" + /* 124816 */ "VXOR_VI\0" + /* 124824 */ "VMSGT_VI\0" + /* 124833 */ "PseudoVMSLT_VI\0" + /* 124848 */ "VSADDU_VI\0" + /* 124858 */ "PseudoVMSGEU_VI\0" + /* 124874 */ "VMSLEU_VI\0" + /* 124884 */ "VMSGTU_VI\0" + /* 124894 */ "PseudoVMSLTU_VI\0" + /* 124910 */ "G_FPOWI\0" + /* 124918 */ "CSRRWI\0" + /* 124925 */ "VNSRA_WI\0" + /* 124934 */ "VNSRL_WI\0" + /* 124943 */ "VNCLIP_WI\0" + /* 124953 */ "VNCLIPU_WI\0" + /* 124964 */ "FENCE_I\0" + /* 124972 */ "VMV_V_I\0" + /* 124980 */ "InsnI\0" + /* 124986 */ "C_J\0" + /* 124990 */ "InsnJ\0" + /* 124996 */ "C_EBREAK\0" + /* 125005 */ "PACK\0" + /* 125010 */ "G_PTRMASK\0" + /* 125020 */ "PseudoVMSBF_M_B1_MASK\0" + /* 125042 */ "PseudoVMSIF_M_B1_MASK\0" + /* 125064 */ "PseudoVMSOF_M_B1_MASK\0" + /* 125086 */ "PseudoVCPOP_M_B1_MASK\0" + /* 125108 */ "PseudoVFIRST_M_B1_MASK\0" + /* 125131 */ "PseudoVAMOADDEI32_WD_M1_M1_MASK\0" + /* 125163 */ "PseudoVAMOANDEI32_WD_M1_M1_MASK\0" + /* 125195 */ "PseudoVAMOMINEI32_WD_M1_M1_MASK\0" + /* 125227 */ "PseudoVAMOSWAPEI32_WD_M1_M1_MASK\0" + /* 125260 */ "PseudoVAMOOREI32_WD_M1_M1_MASK\0" + /* 125291 */ "PseudoVAMOXOREI32_WD_M1_M1_MASK\0" + /* 125323 */ "PseudoVAMOMINUEI32_WD_M1_M1_MASK\0" + /* 125356 */ "PseudoVAMOMAXUEI32_WD_M1_M1_MASK\0" + /* 125389 */ "PseudoVAMOMAXEI32_WD_M1_M1_MASK\0" + /* 125421 */ "PseudoVAMOADDEI64_WD_M1_M1_MASK\0" + /* 125453 */ "PseudoVAMOANDEI64_WD_M1_M1_MASK\0" + /* 125485 */ "PseudoVAMOMINEI64_WD_M1_M1_MASK\0" + /* 125517 */ "PseudoVAMOSWAPEI64_WD_M1_M1_MASK\0" + /* 125550 */ "PseudoVAMOOREI64_WD_M1_M1_MASK\0" + /* 125581 */ "PseudoVAMOXOREI64_WD_M1_M1_MASK\0" + /* 125613 */ "PseudoVAMOMINUEI64_WD_M1_M1_MASK\0" + /* 125646 */ "PseudoVAMOMAXUEI64_WD_M1_M1_MASK\0" + /* 125679 */ "PseudoVAMOMAXEI64_WD_M1_M1_MASK\0" + /* 125711 */ "PseudoVRGATHEREI16_VV_M1_M1_MASK\0" + /* 125744 */ "PseudoVLOXSEG2EI32_V_M1_M1_MASK\0" + /* 125776 */ "PseudoVSOXSEG2EI32_V_M1_M1_MASK\0" + /* 125808 */ "PseudoVLUXSEG2EI32_V_M1_M1_MASK\0" + /* 125840 */ "PseudoVSUXSEG2EI32_V_M1_M1_MASK\0" + /* 125872 */ "PseudoVLOXSEG3EI32_V_M1_M1_MASK\0" + /* 125904 */ "PseudoVSOXSEG3EI32_V_M1_M1_MASK\0" + /* 125936 */ "PseudoVLUXSEG3EI32_V_M1_M1_MASK\0" + /* 125968 */ "PseudoVSUXSEG3EI32_V_M1_M1_MASK\0" + /* 126000 */ "PseudoVLOXSEG4EI32_V_M1_M1_MASK\0" + /* 126032 */ "PseudoVSOXSEG4EI32_V_M1_M1_MASK\0" + /* 126064 */ "PseudoVLUXSEG4EI32_V_M1_M1_MASK\0" + /* 126096 */ "PseudoVSUXSEG4EI32_V_M1_M1_MASK\0" + /* 126128 */ "PseudoVLOXSEG5EI32_V_M1_M1_MASK\0" + /* 126160 */ "PseudoVSOXSEG5EI32_V_M1_M1_MASK\0" + /* 126192 */ "PseudoVLUXSEG5EI32_V_M1_M1_MASK\0" + /* 126224 */ "PseudoVSUXSEG5EI32_V_M1_M1_MASK\0" + /* 126256 */ "PseudoVLOXSEG6EI32_V_M1_M1_MASK\0" + /* 126288 */ "PseudoVSOXSEG6EI32_V_M1_M1_MASK\0" + /* 126320 */ "PseudoVLUXSEG6EI32_V_M1_M1_MASK\0" + /* 126352 */ "PseudoVSUXSEG6EI32_V_M1_M1_MASK\0" + /* 126384 */ "PseudoVLOXSEG7EI32_V_M1_M1_MASK\0" + /* 126416 */ "PseudoVSOXSEG7EI32_V_M1_M1_MASK\0" + /* 126448 */ "PseudoVLUXSEG7EI32_V_M1_M1_MASK\0" + /* 126480 */ "PseudoVSUXSEG7EI32_V_M1_M1_MASK\0" + /* 126512 */ "PseudoVLOXSEG8EI32_V_M1_M1_MASK\0" + /* 126544 */ "PseudoVSOXSEG8EI32_V_M1_M1_MASK\0" + /* 126576 */ "PseudoVLUXSEG8EI32_V_M1_M1_MASK\0" + /* 126608 */ "PseudoVSUXSEG8EI32_V_M1_M1_MASK\0" + /* 126640 */ "PseudoVLOXEI32_V_M1_M1_MASK\0" + /* 126668 */ "PseudoVSOXEI32_V_M1_M1_MASK\0" + /* 126696 */ "PseudoVLUXEI32_V_M1_M1_MASK\0" + /* 126724 */ "PseudoVSUXEI32_V_M1_M1_MASK\0" + /* 126752 */ "PseudoVLOXSEG2EI64_V_M1_M1_MASK\0" + /* 126784 */ "PseudoVSOXSEG2EI64_V_M1_M1_MASK\0" + /* 126816 */ "PseudoVLUXSEG2EI64_V_M1_M1_MASK\0" + /* 126848 */ "PseudoVSUXSEG2EI64_V_M1_M1_MASK\0" + /* 126880 */ "PseudoVLOXSEG3EI64_V_M1_M1_MASK\0" + /* 126912 */ "PseudoVSOXSEG3EI64_V_M1_M1_MASK\0" + /* 126944 */ "PseudoVLUXSEG3EI64_V_M1_M1_MASK\0" + /* 126976 */ "PseudoVSUXSEG3EI64_V_M1_M1_MASK\0" + /* 127008 */ "PseudoVLOXSEG4EI64_V_M1_M1_MASK\0" + /* 127040 */ "PseudoVSOXSEG4EI64_V_M1_M1_MASK\0" + /* 127072 */ "PseudoVLUXSEG4EI64_V_M1_M1_MASK\0" + /* 127104 */ "PseudoVSUXSEG4EI64_V_M1_M1_MASK\0" + /* 127136 */ "PseudoVLOXSEG5EI64_V_M1_M1_MASK\0" + /* 127168 */ "PseudoVSOXSEG5EI64_V_M1_M1_MASK\0" + /* 127200 */ "PseudoVLUXSEG5EI64_V_M1_M1_MASK\0" + /* 127232 */ "PseudoVSUXSEG5EI64_V_M1_M1_MASK\0" + /* 127264 */ "PseudoVLOXSEG6EI64_V_M1_M1_MASK\0" + /* 127296 */ "PseudoVSOXSEG6EI64_V_M1_M1_MASK\0" + /* 127328 */ "PseudoVLUXSEG6EI64_V_M1_M1_MASK\0" + /* 127360 */ "PseudoVSUXSEG6EI64_V_M1_M1_MASK\0" + /* 127392 */ "PseudoVLOXSEG7EI64_V_M1_M1_MASK\0" + /* 127424 */ "PseudoVSOXSEG7EI64_V_M1_M1_MASK\0" + /* 127456 */ "PseudoVLUXSEG7EI64_V_M1_M1_MASK\0" + /* 127488 */ "PseudoVSUXSEG7EI64_V_M1_M1_MASK\0" + /* 127520 */ "PseudoVLOXSEG8EI64_V_M1_M1_MASK\0" + /* 127552 */ "PseudoVSOXSEG8EI64_V_M1_M1_MASK\0" + /* 127584 */ "PseudoVLUXSEG8EI64_V_M1_M1_MASK\0" + /* 127616 */ "PseudoVSUXSEG8EI64_V_M1_M1_MASK\0" + /* 127648 */ "PseudoVLOXEI64_V_M1_M1_MASK\0" + /* 127676 */ "PseudoVSOXEI64_V_M1_M1_MASK\0" + /* 127704 */ "PseudoVLUXEI64_V_M1_M1_MASK\0" + /* 127732 */ "PseudoVSUXEI64_V_M1_M1_MASK\0" + /* 127760 */ "PseudoVLOXSEG2EI16_V_M1_M1_MASK\0" + /* 127792 */ "PseudoVSOXSEG2EI16_V_M1_M1_MASK\0" + /* 127824 */ "PseudoVLUXSEG2EI16_V_M1_M1_MASK\0" + /* 127856 */ "PseudoVSUXSEG2EI16_V_M1_M1_MASK\0" + /* 127888 */ "PseudoVLOXSEG3EI16_V_M1_M1_MASK\0" + /* 127920 */ "PseudoVSOXSEG3EI16_V_M1_M1_MASK\0" + /* 127952 */ "PseudoVLUXSEG3EI16_V_M1_M1_MASK\0" + /* 127984 */ "PseudoVSUXSEG3EI16_V_M1_M1_MASK\0" + /* 128016 */ "PseudoVLOXSEG4EI16_V_M1_M1_MASK\0" + /* 128048 */ "PseudoVSOXSEG4EI16_V_M1_M1_MASK\0" + /* 128080 */ "PseudoVLUXSEG4EI16_V_M1_M1_MASK\0" + /* 128112 */ "PseudoVSUXSEG4EI16_V_M1_M1_MASK\0" + /* 128144 */ "PseudoVLOXSEG5EI16_V_M1_M1_MASK\0" + /* 128176 */ "PseudoVSOXSEG5EI16_V_M1_M1_MASK\0" + /* 128208 */ "PseudoVLUXSEG5EI16_V_M1_M1_MASK\0" + /* 128240 */ "PseudoVSUXSEG5EI16_V_M1_M1_MASK\0" + /* 128272 */ "PseudoVLOXSEG6EI16_V_M1_M1_MASK\0" + /* 128304 */ "PseudoVSOXSEG6EI16_V_M1_M1_MASK\0" + /* 128336 */ "PseudoVLUXSEG6EI16_V_M1_M1_MASK\0" + /* 128368 */ "PseudoVSUXSEG6EI16_V_M1_M1_MASK\0" + /* 128400 */ "PseudoVLOXSEG7EI16_V_M1_M1_MASK\0" + /* 128432 */ "PseudoVSOXSEG7EI16_V_M1_M1_MASK\0" + /* 128464 */ "PseudoVLUXSEG7EI16_V_M1_M1_MASK\0" + /* 128496 */ "PseudoVSUXSEG7EI16_V_M1_M1_MASK\0" + /* 128528 */ "PseudoVLOXSEG8EI16_V_M1_M1_MASK\0" + /* 128560 */ "PseudoVSOXSEG8EI16_V_M1_M1_MASK\0" + /* 128592 */ "PseudoVLUXSEG8EI16_V_M1_M1_MASK\0" + /* 128624 */ "PseudoVSUXSEG8EI16_V_M1_M1_MASK\0" + /* 128656 */ "PseudoVLOXEI16_V_M1_M1_MASK\0" + /* 128684 */ "PseudoVSOXEI16_V_M1_M1_MASK\0" + /* 128712 */ "PseudoVLUXEI16_V_M1_M1_MASK\0" + /* 128740 */ "PseudoVSUXEI16_V_M1_M1_MASK\0" + /* 128768 */ "PseudoVLOXSEG2EI8_V_M1_M1_MASK\0" + /* 128799 */ "PseudoVSOXSEG2EI8_V_M1_M1_MASK\0" + /* 128830 */ "PseudoVLUXSEG2EI8_V_M1_M1_MASK\0" + /* 128861 */ "PseudoVSUXSEG2EI8_V_M1_M1_MASK\0" + /* 128892 */ "PseudoVLOXSEG3EI8_V_M1_M1_MASK\0" + /* 128923 */ "PseudoVSOXSEG3EI8_V_M1_M1_MASK\0" + /* 128954 */ "PseudoVLUXSEG3EI8_V_M1_M1_MASK\0" + /* 128985 */ "PseudoVSUXSEG3EI8_V_M1_M1_MASK\0" + /* 129016 */ "PseudoVLOXSEG4EI8_V_M1_M1_MASK\0" + /* 129047 */ "PseudoVSOXSEG4EI8_V_M1_M1_MASK\0" + /* 129078 */ "PseudoVLUXSEG4EI8_V_M1_M1_MASK\0" + /* 129109 */ "PseudoVSUXSEG4EI8_V_M1_M1_MASK\0" + /* 129140 */ "PseudoVLOXSEG5EI8_V_M1_M1_MASK\0" + /* 129171 */ "PseudoVSOXSEG5EI8_V_M1_M1_MASK\0" + /* 129202 */ "PseudoVLUXSEG5EI8_V_M1_M1_MASK\0" + /* 129233 */ "PseudoVSUXSEG5EI8_V_M1_M1_MASK\0" + /* 129264 */ "PseudoVLOXSEG6EI8_V_M1_M1_MASK\0" + /* 129295 */ "PseudoVSOXSEG6EI8_V_M1_M1_MASK\0" + /* 129326 */ "PseudoVLUXSEG6EI8_V_M1_M1_MASK\0" + /* 129357 */ "PseudoVSUXSEG6EI8_V_M1_M1_MASK\0" + /* 129388 */ "PseudoVLOXSEG7EI8_V_M1_M1_MASK\0" + /* 129419 */ "PseudoVSOXSEG7EI8_V_M1_M1_MASK\0" + /* 129450 */ "PseudoVLUXSEG7EI8_V_M1_M1_MASK\0" + /* 129481 */ "PseudoVSUXSEG7EI8_V_M1_M1_MASK\0" + /* 129512 */ "PseudoVLOXSEG8EI8_V_M1_M1_MASK\0" + /* 129543 */ "PseudoVSOXSEG8EI8_V_M1_M1_MASK\0" + /* 129574 */ "PseudoVLUXSEG8EI8_V_M1_M1_MASK\0" + /* 129605 */ "PseudoVSUXSEG8EI8_V_M1_M1_MASK\0" + /* 129636 */ "PseudoVLOXEI8_V_M1_M1_MASK\0" + /* 129663 */ "PseudoVSOXEI8_V_M1_M1_MASK\0" + /* 129690 */ "PseudoVLUXEI8_V_M1_M1_MASK\0" + /* 129717 */ "PseudoVSUXEI8_V_M1_M1_MASK\0" + /* 129744 */ "PseudoVFSUB_VF32_M1_MASK\0" + /* 129769 */ "PseudoVFMSUB_VF32_M1_MASK\0" + /* 129795 */ "PseudoVFNMSUB_VF32_M1_MASK\0" + /* 129822 */ "PseudoVFRSUB_VF32_M1_MASK\0" + /* 129848 */ "PseudoVFWSUB_VF32_M1_MASK\0" + /* 129874 */ "PseudoVFMSAC_VF32_M1_MASK\0" + /* 129900 */ "PseudoVFNMSAC_VF32_M1_MASK\0" + /* 129927 */ "PseudoVFWNMSAC_VF32_M1_MASK\0" + /* 129955 */ "PseudoVFWMSAC_VF32_M1_MASK\0" + /* 129982 */ "PseudoVFMACC_VF32_M1_MASK\0" + /* 130008 */ "PseudoVFNMACC_VF32_M1_MASK\0" + /* 130035 */ "PseudoVFWNMACC_VF32_M1_MASK\0" + /* 130063 */ "PseudoVFWMACC_VF32_M1_MASK\0" + /* 130090 */ "PseudoVFADD_VF32_M1_MASK\0" + /* 130115 */ "PseudoVFMADD_VF32_M1_MASK\0" + /* 130141 */ "PseudoVFNMADD_VF32_M1_MASK\0" + /* 130168 */ "PseudoVFWADD_VF32_M1_MASK\0" + /* 130194 */ "PseudoVMFGE_VF32_M1_MASK\0" + /* 130219 */ "PseudoVMFLE_VF32_M1_MASK\0" + /* 130244 */ "PseudoVMFNE_VF32_M1_MASK\0" + /* 130269 */ "PseudoVFSGNJ_VF32_M1_MASK\0" + /* 130295 */ "PseudoVFMUL_VF32_M1_MASK\0" + /* 130320 */ "PseudoVFWMUL_VF32_M1_MASK\0" + /* 130346 */ "PseudoVFMIN_VF32_M1_MASK\0" + /* 130371 */ "PseudoVFSGNJN_VF32_M1_MASK\0" + /* 130398 */ "PseudoVFSLIDE1DOWN_VF32_M1_MASK\0" + /* 130430 */ "PseudoVFSLIDE1UP_VF32_M1_MASK\0" + /* 130460 */ "PseudoVMFEQ_VF32_M1_MASK\0" + /* 130485 */ "PseudoVMFGT_VF32_M1_MASK\0" + /* 130510 */ "PseudoVMFLT_VF32_M1_MASK\0" + /* 130535 */ "PseudoVFDIV_VF32_M1_MASK\0" + /* 130560 */ "PseudoVFRDIV_VF32_M1_MASK\0" + /* 130586 */ "PseudoVFMAX_VF32_M1_MASK\0" + /* 130611 */ "PseudoVFSGNJX_VF32_M1_MASK\0" + /* 130638 */ "PseudoVFWSUB_WF32_M1_MASK\0" + /* 130664 */ "PseudoVFWADD_WF32_M1_MASK\0" + /* 130690 */ "PseudoVAMOADDEI64_WD_MF2_M1_MASK\0" + /* 130723 */ "PseudoVAMOANDEI64_WD_MF2_M1_MASK\0" + /* 130756 */ "PseudoVAMOMINEI64_WD_MF2_M1_MASK\0" + /* 130789 */ "PseudoVAMOSWAPEI64_WD_MF2_M1_MASK\0" + /* 130823 */ "PseudoVAMOOREI64_WD_MF2_M1_MASK\0" + /* 130855 */ "PseudoVAMOXOREI64_WD_MF2_M1_MASK\0" + /* 130888 */ "PseudoVAMOMINUEI64_WD_MF2_M1_MASK\0" + /* 130922 */ "PseudoVAMOMAXUEI64_WD_MF2_M1_MASK\0" + /* 130956 */ "PseudoVAMOMAXEI64_WD_MF2_M1_MASK\0" + /* 130989 */ "PseudoVRGATHEREI16_VV_MF2_M1_MASK\0" + /* 131023 */ "PseudoVLOXSEG2EI32_V_MF2_M1_MASK\0" + /* 131056 */ "PseudoVSOXSEG2EI32_V_MF2_M1_MASK\0" + /* 131089 */ "PseudoVLUXSEG2EI32_V_MF2_M1_MASK\0" + /* 131122 */ "PseudoVSUXSEG2EI32_V_MF2_M1_MASK\0" + /* 131155 */ "PseudoVLOXSEG3EI32_V_MF2_M1_MASK\0" + /* 131188 */ "PseudoVSOXSEG3EI32_V_MF2_M1_MASK\0" + /* 131221 */ "PseudoVLUXSEG3EI32_V_MF2_M1_MASK\0" + /* 131254 */ "PseudoVSUXSEG3EI32_V_MF2_M1_MASK\0" + /* 131287 */ "PseudoVLOXSEG4EI32_V_MF2_M1_MASK\0" + /* 131320 */ "PseudoVSOXSEG4EI32_V_MF2_M1_MASK\0" + /* 131353 */ "PseudoVLUXSEG4EI32_V_MF2_M1_MASK\0" + /* 131386 */ "PseudoVSUXSEG4EI32_V_MF2_M1_MASK\0" + /* 131419 */ "PseudoVLOXSEG5EI32_V_MF2_M1_MASK\0" + /* 131452 */ "PseudoVSOXSEG5EI32_V_MF2_M1_MASK\0" + /* 131485 */ "PseudoVLUXSEG5EI32_V_MF2_M1_MASK\0" + /* 131518 */ "PseudoVSUXSEG5EI32_V_MF2_M1_MASK\0" + /* 131551 */ "PseudoVLOXSEG6EI32_V_MF2_M1_MASK\0" + /* 131584 */ "PseudoVSOXSEG6EI32_V_MF2_M1_MASK\0" + /* 131617 */ "PseudoVLUXSEG6EI32_V_MF2_M1_MASK\0" + /* 131650 */ "PseudoVSUXSEG6EI32_V_MF2_M1_MASK\0" + /* 131683 */ "PseudoVLOXSEG7EI32_V_MF2_M1_MASK\0" + /* 131716 */ "PseudoVSOXSEG7EI32_V_MF2_M1_MASK\0" + /* 131749 */ "PseudoVLUXSEG7EI32_V_MF2_M1_MASK\0" + /* 131782 */ "PseudoVSUXSEG7EI32_V_MF2_M1_MASK\0" + /* 131815 */ "PseudoVLOXSEG8EI32_V_MF2_M1_MASK\0" + /* 131848 */ "PseudoVSOXSEG8EI32_V_MF2_M1_MASK\0" + /* 131881 */ "PseudoVLUXSEG8EI32_V_MF2_M1_MASK\0" + /* 131914 */ "PseudoVSUXSEG8EI32_V_MF2_M1_MASK\0" + /* 131947 */ "PseudoVLOXEI32_V_MF2_M1_MASK\0" + /* 131976 */ "PseudoVSOXEI32_V_MF2_M1_MASK\0" + /* 132005 */ "PseudoVLUXEI32_V_MF2_M1_MASK\0" + /* 132034 */ "PseudoVSUXEI32_V_MF2_M1_MASK\0" + /* 132063 */ "PseudoVLOXSEG2EI16_V_MF2_M1_MASK\0" + /* 132096 */ "PseudoVSOXSEG2EI16_V_MF2_M1_MASK\0" + /* 132129 */ "PseudoVLUXSEG2EI16_V_MF2_M1_MASK\0" + /* 132162 */ "PseudoVSUXSEG2EI16_V_MF2_M1_MASK\0" + /* 132195 */ "PseudoVLOXSEG3EI16_V_MF2_M1_MASK\0" + /* 132228 */ "PseudoVSOXSEG3EI16_V_MF2_M1_MASK\0" + /* 132261 */ "PseudoVLUXSEG3EI16_V_MF2_M1_MASK\0" + /* 132294 */ "PseudoVSUXSEG3EI16_V_MF2_M1_MASK\0" + /* 132327 */ "PseudoVLOXSEG4EI16_V_MF2_M1_MASK\0" + /* 132360 */ "PseudoVSOXSEG4EI16_V_MF2_M1_MASK\0" + /* 132393 */ "PseudoVLUXSEG4EI16_V_MF2_M1_MASK\0" + /* 132426 */ "PseudoVSUXSEG4EI16_V_MF2_M1_MASK\0" + /* 132459 */ "PseudoVLOXSEG5EI16_V_MF2_M1_MASK\0" + /* 132492 */ "PseudoVSOXSEG5EI16_V_MF2_M1_MASK\0" + /* 132525 */ "PseudoVLUXSEG5EI16_V_MF2_M1_MASK\0" + /* 132558 */ "PseudoVSUXSEG5EI16_V_MF2_M1_MASK\0" + /* 132591 */ "PseudoVLOXSEG6EI16_V_MF2_M1_MASK\0" + /* 132624 */ "PseudoVSOXSEG6EI16_V_MF2_M1_MASK\0" + /* 132657 */ "PseudoVLUXSEG6EI16_V_MF2_M1_MASK\0" + /* 132690 */ "PseudoVSUXSEG6EI16_V_MF2_M1_MASK\0" + /* 132723 */ "PseudoVLOXSEG7EI16_V_MF2_M1_MASK\0" + /* 132756 */ "PseudoVSOXSEG7EI16_V_MF2_M1_MASK\0" + /* 132789 */ "PseudoVLUXSEG7EI16_V_MF2_M1_MASK\0" + /* 132822 */ "PseudoVSUXSEG7EI16_V_MF2_M1_MASK\0" + /* 132855 */ "PseudoVLOXSEG8EI16_V_MF2_M1_MASK\0" + /* 132888 */ "PseudoVSOXSEG8EI16_V_MF2_M1_MASK\0" + /* 132921 */ "PseudoVLUXSEG8EI16_V_MF2_M1_MASK\0" + /* 132954 */ "PseudoVSUXSEG8EI16_V_MF2_M1_MASK\0" + /* 132987 */ "PseudoVLOXEI16_V_MF2_M1_MASK\0" + /* 133016 */ "PseudoVSOXEI16_V_MF2_M1_MASK\0" + /* 133045 */ "PseudoVLUXEI16_V_MF2_M1_MASK\0" + /* 133074 */ "PseudoVSUXEI16_V_MF2_M1_MASK\0" + /* 133103 */ "PseudoVLOXSEG2EI8_V_MF2_M1_MASK\0" + /* 133135 */ "PseudoVSOXSEG2EI8_V_MF2_M1_MASK\0" + /* 133167 */ "PseudoVLUXSEG2EI8_V_MF2_M1_MASK\0" + /* 133199 */ "PseudoVSUXSEG2EI8_V_MF2_M1_MASK\0" + /* 133231 */ "PseudoVLOXSEG3EI8_V_MF2_M1_MASK\0" + /* 133263 */ "PseudoVSOXSEG3EI8_V_MF2_M1_MASK\0" + /* 133295 */ "PseudoVLUXSEG3EI8_V_MF2_M1_MASK\0" + /* 133327 */ "PseudoVSUXSEG3EI8_V_MF2_M1_MASK\0" + /* 133359 */ "PseudoVLOXSEG4EI8_V_MF2_M1_MASK\0" + /* 133391 */ "PseudoVSOXSEG4EI8_V_MF2_M1_MASK\0" + /* 133423 */ "PseudoVLUXSEG4EI8_V_MF2_M1_MASK\0" + /* 133455 */ "PseudoVSUXSEG4EI8_V_MF2_M1_MASK\0" + /* 133487 */ "PseudoVLOXSEG5EI8_V_MF2_M1_MASK\0" + /* 133519 */ "PseudoVSOXSEG5EI8_V_MF2_M1_MASK\0" + /* 133551 */ "PseudoVLUXSEG5EI8_V_MF2_M1_MASK\0" + /* 133583 */ "PseudoVSUXSEG5EI8_V_MF2_M1_MASK\0" + /* 133615 */ "PseudoVLOXSEG6EI8_V_MF2_M1_MASK\0" + /* 133647 */ "PseudoVSOXSEG6EI8_V_MF2_M1_MASK\0" + /* 133679 */ "PseudoVLUXSEG6EI8_V_MF2_M1_MASK\0" + /* 133711 */ "PseudoVSUXSEG6EI8_V_MF2_M1_MASK\0" + /* 133743 */ "PseudoVLOXSEG7EI8_V_MF2_M1_MASK\0" + /* 133775 */ "PseudoVSOXSEG7EI8_V_MF2_M1_MASK\0" + /* 133807 */ "PseudoVLUXSEG7EI8_V_MF2_M1_MASK\0" + /* 133839 */ "PseudoVSUXSEG7EI8_V_MF2_M1_MASK\0" + /* 133871 */ "PseudoVLOXSEG8EI8_V_MF2_M1_MASK\0" + /* 133903 */ "PseudoVSOXSEG8EI8_V_MF2_M1_MASK\0" + /* 133935 */ "PseudoVLUXSEG8EI8_V_MF2_M1_MASK\0" + /* 133967 */ "PseudoVSUXSEG8EI8_V_MF2_M1_MASK\0" + /* 133999 */ "PseudoVLOXEI8_V_MF2_M1_MASK\0" + /* 134027 */ "PseudoVSOXEI8_V_MF2_M1_MASK\0" + /* 134055 */ "PseudoVLUXEI8_V_MF2_M1_MASK\0" + /* 134083 */ "PseudoVSUXEI8_V_MF2_M1_MASK\0" + /* 134111 */ "PseudoVSEXT_VF2_M1_MASK\0" + /* 134135 */ "PseudoVZEXT_VF2_M1_MASK\0" + /* 134159 */ "PseudoVAMOADDEI32_WD_M2_M1_MASK\0" + /* 134191 */ "PseudoVAMOANDEI32_WD_M2_M1_MASK\0" + /* 134223 */ "PseudoVAMOMINEI32_WD_M2_M1_MASK\0" + /* 134255 */ "PseudoVAMOSWAPEI32_WD_M2_M1_MASK\0" + /* 134288 */ "PseudoVAMOOREI32_WD_M2_M1_MASK\0" + /* 134319 */ "PseudoVAMOXOREI32_WD_M2_M1_MASK\0" + /* 134351 */ "PseudoVAMOMINUEI32_WD_M2_M1_MASK\0" + /* 134384 */ "PseudoVAMOMAXUEI32_WD_M2_M1_MASK\0" + /* 134417 */ "PseudoVAMOMAXEI32_WD_M2_M1_MASK\0" + /* 134449 */ "PseudoVAMOADDEI16_WD_M2_M1_MASK\0" + /* 134481 */ "PseudoVAMOANDEI16_WD_M2_M1_MASK\0" + /* 134513 */ "PseudoVAMOMINEI16_WD_M2_M1_MASK\0" + /* 134545 */ "PseudoVAMOSWAPEI16_WD_M2_M1_MASK\0" + /* 134578 */ "PseudoVAMOOREI16_WD_M2_M1_MASK\0" + /* 134609 */ "PseudoVAMOXOREI16_WD_M2_M1_MASK\0" + /* 134641 */ "PseudoVAMOMINUEI16_WD_M2_M1_MASK\0" + /* 134674 */ "PseudoVAMOMAXUEI16_WD_M2_M1_MASK\0" + /* 134707 */ "PseudoVAMOMAXEI16_WD_M2_M1_MASK\0" + /* 134739 */ "PseudoVRGATHEREI16_VV_M2_M1_MASK\0" + /* 134772 */ "PseudoVLOXSEG2EI32_V_M2_M1_MASK\0" + /* 134804 */ "PseudoVSOXSEG2EI32_V_M2_M1_MASK\0" + /* 134836 */ "PseudoVLUXSEG2EI32_V_M2_M1_MASK\0" + /* 134868 */ "PseudoVSUXSEG2EI32_V_M2_M1_MASK\0" + /* 134900 */ "PseudoVLOXSEG3EI32_V_M2_M1_MASK\0" + /* 134932 */ "PseudoVSOXSEG3EI32_V_M2_M1_MASK\0" + /* 134964 */ "PseudoVLUXSEG3EI32_V_M2_M1_MASK\0" + /* 134996 */ "PseudoVSUXSEG3EI32_V_M2_M1_MASK\0" + /* 135028 */ "PseudoVLOXSEG4EI32_V_M2_M1_MASK\0" + /* 135060 */ "PseudoVSOXSEG4EI32_V_M2_M1_MASK\0" + /* 135092 */ "PseudoVLUXSEG4EI32_V_M2_M1_MASK\0" + /* 135124 */ "PseudoVSUXSEG4EI32_V_M2_M1_MASK\0" + /* 135156 */ "PseudoVLOXSEG5EI32_V_M2_M1_MASK\0" + /* 135188 */ "PseudoVSOXSEG5EI32_V_M2_M1_MASK\0" + /* 135220 */ "PseudoVLUXSEG5EI32_V_M2_M1_MASK\0" + /* 135252 */ "PseudoVSUXSEG5EI32_V_M2_M1_MASK\0" + /* 135284 */ "PseudoVLOXSEG6EI32_V_M2_M1_MASK\0" + /* 135316 */ "PseudoVSOXSEG6EI32_V_M2_M1_MASK\0" + /* 135348 */ "PseudoVLUXSEG6EI32_V_M2_M1_MASK\0" + /* 135380 */ "PseudoVSUXSEG6EI32_V_M2_M1_MASK\0" + /* 135412 */ "PseudoVLOXSEG7EI32_V_M2_M1_MASK\0" + /* 135444 */ "PseudoVSOXSEG7EI32_V_M2_M1_MASK\0" + /* 135476 */ "PseudoVLUXSEG7EI32_V_M2_M1_MASK\0" + /* 135508 */ "PseudoVSUXSEG7EI32_V_M2_M1_MASK\0" + /* 135540 */ "PseudoVLOXSEG8EI32_V_M2_M1_MASK\0" + /* 135572 */ "PseudoVSOXSEG8EI32_V_M2_M1_MASK\0" + /* 135604 */ "PseudoVLUXSEG8EI32_V_M2_M1_MASK\0" + /* 135636 */ "PseudoVSUXSEG8EI32_V_M2_M1_MASK\0" + /* 135668 */ "PseudoVLOXEI32_V_M2_M1_MASK\0" + /* 135696 */ "PseudoVSOXEI32_V_M2_M1_MASK\0" + /* 135724 */ "PseudoVLUXEI32_V_M2_M1_MASK\0" + /* 135752 */ "PseudoVSUXEI32_V_M2_M1_MASK\0" + /* 135780 */ "PseudoVLOXSEG2EI64_V_M2_M1_MASK\0" + /* 135812 */ "PseudoVSOXSEG2EI64_V_M2_M1_MASK\0" + /* 135844 */ "PseudoVLUXSEG2EI64_V_M2_M1_MASK\0" + /* 135876 */ "PseudoVSUXSEG2EI64_V_M2_M1_MASK\0" + /* 135908 */ "PseudoVLOXSEG3EI64_V_M2_M1_MASK\0" + /* 135940 */ "PseudoVSOXSEG3EI64_V_M2_M1_MASK\0" + /* 135972 */ "PseudoVLUXSEG3EI64_V_M2_M1_MASK\0" + /* 136004 */ "PseudoVSUXSEG3EI64_V_M2_M1_MASK\0" + /* 136036 */ "PseudoVLOXSEG4EI64_V_M2_M1_MASK\0" + /* 136068 */ "PseudoVSOXSEG4EI64_V_M2_M1_MASK\0" + /* 136100 */ "PseudoVLUXSEG4EI64_V_M2_M1_MASK\0" + /* 136132 */ "PseudoVSUXSEG4EI64_V_M2_M1_MASK\0" + /* 136164 */ "PseudoVLOXSEG5EI64_V_M2_M1_MASK\0" + /* 136196 */ "PseudoVSOXSEG5EI64_V_M2_M1_MASK\0" + /* 136228 */ "PseudoVLUXSEG5EI64_V_M2_M1_MASK\0" + /* 136260 */ "PseudoVSUXSEG5EI64_V_M2_M1_MASK\0" + /* 136292 */ "PseudoVLOXSEG6EI64_V_M2_M1_MASK\0" + /* 136324 */ "PseudoVSOXSEG6EI64_V_M2_M1_MASK\0" + /* 136356 */ "PseudoVLUXSEG6EI64_V_M2_M1_MASK\0" + /* 136388 */ "PseudoVSUXSEG6EI64_V_M2_M1_MASK\0" + /* 136420 */ "PseudoVLOXSEG7EI64_V_M2_M1_MASK\0" + /* 136452 */ "PseudoVSOXSEG7EI64_V_M2_M1_MASK\0" + /* 136484 */ "PseudoVLUXSEG7EI64_V_M2_M1_MASK\0" + /* 136516 */ "PseudoVSUXSEG7EI64_V_M2_M1_MASK\0" + /* 136548 */ "PseudoVLOXSEG8EI64_V_M2_M1_MASK\0" + /* 136580 */ "PseudoVSOXSEG8EI64_V_M2_M1_MASK\0" + /* 136612 */ "PseudoVLUXSEG8EI64_V_M2_M1_MASK\0" + /* 136644 */ "PseudoVSUXSEG8EI64_V_M2_M1_MASK\0" + /* 136676 */ "PseudoVLOXEI64_V_M2_M1_MASK\0" + /* 136704 */ "PseudoVSOXEI64_V_M2_M1_MASK\0" + /* 136732 */ "PseudoVLUXEI64_V_M2_M1_MASK\0" + /* 136760 */ "PseudoVSUXEI64_V_M2_M1_MASK\0" + /* 136788 */ "PseudoVLOXSEG2EI16_V_M2_M1_MASK\0" + /* 136820 */ "PseudoVSOXSEG2EI16_V_M2_M1_MASK\0" + /* 136852 */ "PseudoVLUXSEG2EI16_V_M2_M1_MASK\0" + /* 136884 */ "PseudoVSUXSEG2EI16_V_M2_M1_MASK\0" + /* 136916 */ "PseudoVLOXSEG3EI16_V_M2_M1_MASK\0" + /* 136948 */ "PseudoVSOXSEG3EI16_V_M2_M1_MASK\0" + /* 136980 */ "PseudoVLUXSEG3EI16_V_M2_M1_MASK\0" + /* 137012 */ "PseudoVSUXSEG3EI16_V_M2_M1_MASK\0" + /* 137044 */ "PseudoVLOXSEG4EI16_V_M2_M1_MASK\0" + /* 137076 */ "PseudoVSOXSEG4EI16_V_M2_M1_MASK\0" + /* 137108 */ "PseudoVLUXSEG4EI16_V_M2_M1_MASK\0" + /* 137140 */ "PseudoVSUXSEG4EI16_V_M2_M1_MASK\0" + /* 137172 */ "PseudoVLOXSEG5EI16_V_M2_M1_MASK\0" + /* 137204 */ "PseudoVSOXSEG5EI16_V_M2_M1_MASK\0" + /* 137236 */ "PseudoVLUXSEG5EI16_V_M2_M1_MASK\0" + /* 137268 */ "PseudoVSUXSEG5EI16_V_M2_M1_MASK\0" + /* 137300 */ "PseudoVLOXSEG6EI16_V_M2_M1_MASK\0" + /* 137332 */ "PseudoVSOXSEG6EI16_V_M2_M1_MASK\0" + /* 137364 */ "PseudoVLUXSEG6EI16_V_M2_M1_MASK\0" + /* 137396 */ "PseudoVSUXSEG6EI16_V_M2_M1_MASK\0" + /* 137428 */ "PseudoVLOXSEG7EI16_V_M2_M1_MASK\0" + /* 137460 */ "PseudoVSOXSEG7EI16_V_M2_M1_MASK\0" + /* 137492 */ "PseudoVLUXSEG7EI16_V_M2_M1_MASK\0" + /* 137524 */ "PseudoVSUXSEG7EI16_V_M2_M1_MASK\0" + /* 137556 */ "PseudoVLOXSEG8EI16_V_M2_M1_MASK\0" + /* 137588 */ "PseudoVSOXSEG8EI16_V_M2_M1_MASK\0" + /* 137620 */ "PseudoVLUXSEG8EI16_V_M2_M1_MASK\0" + /* 137652 */ "PseudoVSUXSEG8EI16_V_M2_M1_MASK\0" + /* 137684 */ "PseudoVLOXEI16_V_M2_M1_MASK\0" + /* 137712 */ "PseudoVSOXEI16_V_M2_M1_MASK\0" + /* 137740 */ "PseudoVLUXEI16_V_M2_M1_MASK\0" + /* 137768 */ "PseudoVSUXEI16_V_M2_M1_MASK\0" + /* 137796 */ "PseudoVFSUB_VF64_M1_MASK\0" + /* 137821 */ "PseudoVFMSUB_VF64_M1_MASK\0" + /* 137847 */ "PseudoVFNMSUB_VF64_M1_MASK\0" + /* 137874 */ "PseudoVFRSUB_VF64_M1_MASK\0" + /* 137900 */ "PseudoVFMSAC_VF64_M1_MASK\0" + /* 137926 */ "PseudoVFNMSAC_VF64_M1_MASK\0" + /* 137953 */ "PseudoVFMACC_VF64_M1_MASK\0" + /* 137979 */ "PseudoVFNMACC_VF64_M1_MASK\0" + /* 138006 */ "PseudoVFADD_VF64_M1_MASK\0" + /* 138031 */ "PseudoVFMADD_VF64_M1_MASK\0" + /* 138057 */ "PseudoVFNMADD_VF64_M1_MASK\0" + /* 138084 */ "PseudoVMFGE_VF64_M1_MASK\0" + /* 138109 */ "PseudoVMFLE_VF64_M1_MASK\0" + /* 138134 */ "PseudoVMFNE_VF64_M1_MASK\0" + /* 138159 */ "PseudoVFSGNJ_VF64_M1_MASK\0" + /* 138185 */ "PseudoVFMUL_VF64_M1_MASK\0" + /* 138210 */ "PseudoVFMIN_VF64_M1_MASK\0" + /* 138235 */ "PseudoVFSGNJN_VF64_M1_MASK\0" + /* 138262 */ "PseudoVFSLIDE1DOWN_VF64_M1_MASK\0" + /* 138294 */ "PseudoVFSLIDE1UP_VF64_M1_MASK\0" + /* 138324 */ "PseudoVMFEQ_VF64_M1_MASK\0" + /* 138349 */ "PseudoVMFGT_VF64_M1_MASK\0" + /* 138374 */ "PseudoVMFLT_VF64_M1_MASK\0" + /* 138399 */ "PseudoVFDIV_VF64_M1_MASK\0" + /* 138424 */ "PseudoVFRDIV_VF64_M1_MASK\0" + /* 138450 */ "PseudoVFMAX_VF64_M1_MASK\0" + /* 138475 */ "PseudoVFSGNJX_VF64_M1_MASK\0" + /* 138502 */ "PseudoVLOXSEG2EI16_V_MF4_M1_MASK\0" + /* 138535 */ "PseudoVSOXSEG2EI16_V_MF4_M1_MASK\0" + /* 138568 */ "PseudoVLUXSEG2EI16_V_MF4_M1_MASK\0" + /* 138601 */ "PseudoVSUXSEG2EI16_V_MF4_M1_MASK\0" + /* 138634 */ "PseudoVLOXSEG3EI16_V_MF4_M1_MASK\0" + /* 138667 */ "PseudoVSOXSEG3EI16_V_MF4_M1_MASK\0" + /* 138700 */ "PseudoVLUXSEG3EI16_V_MF4_M1_MASK\0" + /* 138733 */ "PseudoVSUXSEG3EI16_V_MF4_M1_MASK\0" + /* 138766 */ "PseudoVLOXSEG4EI16_V_MF4_M1_MASK\0" + /* 138799 */ "PseudoVSOXSEG4EI16_V_MF4_M1_MASK\0" + /* 138832 */ "PseudoVLUXSEG4EI16_V_MF4_M1_MASK\0" + /* 138865 */ "PseudoVSUXSEG4EI16_V_MF4_M1_MASK\0" + /* 138898 */ "PseudoVLOXSEG5EI16_V_MF4_M1_MASK\0" + /* 138931 */ "PseudoVSOXSEG5EI16_V_MF4_M1_MASK\0" + /* 138964 */ "PseudoVLUXSEG5EI16_V_MF4_M1_MASK\0" + /* 138997 */ "PseudoVSUXSEG5EI16_V_MF4_M1_MASK\0" + /* 139030 */ "PseudoVLOXSEG6EI16_V_MF4_M1_MASK\0" + /* 139063 */ "PseudoVSOXSEG6EI16_V_MF4_M1_MASK\0" + /* 139096 */ "PseudoVLUXSEG6EI16_V_MF4_M1_MASK\0" + /* 139129 */ "PseudoVSUXSEG6EI16_V_MF4_M1_MASK\0" + /* 139162 */ "PseudoVLOXSEG7EI16_V_MF4_M1_MASK\0" + /* 139195 */ "PseudoVSOXSEG7EI16_V_MF4_M1_MASK\0" + /* 139228 */ "PseudoVLUXSEG7EI16_V_MF4_M1_MASK\0" + /* 139261 */ "PseudoVSUXSEG7EI16_V_MF4_M1_MASK\0" + /* 139294 */ "PseudoVLOXSEG8EI16_V_MF4_M1_MASK\0" + /* 139327 */ "PseudoVSOXSEG8EI16_V_MF4_M1_MASK\0" + /* 139360 */ "PseudoVLUXSEG8EI16_V_MF4_M1_MASK\0" + /* 139393 */ "PseudoVSUXSEG8EI16_V_MF4_M1_MASK\0" + /* 139426 */ "PseudoVLOXEI16_V_MF4_M1_MASK\0" + /* 139455 */ "PseudoVSOXEI16_V_MF4_M1_MASK\0" + /* 139484 */ "PseudoVLUXEI16_V_MF4_M1_MASK\0" + /* 139513 */ "PseudoVSUXEI16_V_MF4_M1_MASK\0" + /* 139542 */ "PseudoVLOXSEG2EI8_V_MF4_M1_MASK\0" + /* 139574 */ "PseudoVSOXSEG2EI8_V_MF4_M1_MASK\0" + /* 139606 */ "PseudoVLUXSEG2EI8_V_MF4_M1_MASK\0" + /* 139638 */ "PseudoVSUXSEG2EI8_V_MF4_M1_MASK\0" + /* 139670 */ "PseudoVLOXSEG3EI8_V_MF4_M1_MASK\0" + /* 139702 */ "PseudoVSOXSEG3EI8_V_MF4_M1_MASK\0" + /* 139734 */ "PseudoVLUXSEG3EI8_V_MF4_M1_MASK\0" + /* 139766 */ "PseudoVSUXSEG3EI8_V_MF4_M1_MASK\0" + /* 139798 */ "PseudoVLOXSEG4EI8_V_MF4_M1_MASK\0" + /* 139830 */ "PseudoVSOXSEG4EI8_V_MF4_M1_MASK\0" + /* 139862 */ "PseudoVLUXSEG4EI8_V_MF4_M1_MASK\0" + /* 139894 */ "PseudoVSUXSEG4EI8_V_MF4_M1_MASK\0" + /* 139926 */ "PseudoVLOXSEG5EI8_V_MF4_M1_MASK\0" + /* 139958 */ "PseudoVSOXSEG5EI8_V_MF4_M1_MASK\0" + /* 139990 */ "PseudoVLUXSEG5EI8_V_MF4_M1_MASK\0" + /* 140022 */ "PseudoVSUXSEG5EI8_V_MF4_M1_MASK\0" + /* 140054 */ "PseudoVLOXSEG6EI8_V_MF4_M1_MASK\0" + /* 140086 */ "PseudoVSOXSEG6EI8_V_MF4_M1_MASK\0" + /* 140118 */ "PseudoVLUXSEG6EI8_V_MF4_M1_MASK\0" + /* 140150 */ "PseudoVSUXSEG6EI8_V_MF4_M1_MASK\0" + /* 140182 */ "PseudoVLOXSEG7EI8_V_MF4_M1_MASK\0" + /* 140214 */ "PseudoVSOXSEG7EI8_V_MF4_M1_MASK\0" + /* 140246 */ "PseudoVLUXSEG7EI8_V_MF4_M1_MASK\0" + /* 140278 */ "PseudoVSUXSEG7EI8_V_MF4_M1_MASK\0" + /* 140310 */ "PseudoVLOXSEG8EI8_V_MF4_M1_MASK\0" + /* 140342 */ "PseudoVSOXSEG8EI8_V_MF4_M1_MASK\0" + /* 140374 */ "PseudoVLUXSEG8EI8_V_MF4_M1_MASK\0" + /* 140406 */ "PseudoVSUXSEG8EI8_V_MF4_M1_MASK\0" + /* 140438 */ "PseudoVLOXEI8_V_MF4_M1_MASK\0" + /* 140466 */ "PseudoVSOXEI8_V_MF4_M1_MASK\0" + /* 140494 */ "PseudoVLUXEI8_V_MF4_M1_MASK\0" + /* 140522 */ "PseudoVSUXEI8_V_MF4_M1_MASK\0" + /* 140550 */ "PseudoVSEXT_VF4_M1_MASK\0" + /* 140574 */ "PseudoVZEXT_VF4_M1_MASK\0" + /* 140598 */ "PseudoVAMOADDEI16_WD_M4_M1_MASK\0" + /* 140630 */ "PseudoVAMOANDEI16_WD_M4_M1_MASK\0" + /* 140662 */ "PseudoVAMOMINEI16_WD_M4_M1_MASK\0" + /* 140694 */ "PseudoVAMOSWAPEI16_WD_M4_M1_MASK\0" + /* 140727 */ "PseudoVAMOOREI16_WD_M4_M1_MASK\0" + /* 140758 */ "PseudoVAMOXOREI16_WD_M4_M1_MASK\0" + /* 140790 */ "PseudoVAMOMINUEI16_WD_M4_M1_MASK\0" + /* 140823 */ "PseudoVAMOMAXUEI16_WD_M4_M1_MASK\0" + /* 140856 */ "PseudoVAMOMAXEI16_WD_M4_M1_MASK\0" + /* 140888 */ "PseudoVAMOADDEI8_WD_M4_M1_MASK\0" + /* 140919 */ "PseudoVAMOANDEI8_WD_M4_M1_MASK\0" + /* 140950 */ "PseudoVAMOMINEI8_WD_M4_M1_MASK\0" + /* 140981 */ "PseudoVAMOSWAPEI8_WD_M4_M1_MASK\0" + /* 141013 */ "PseudoVAMOOREI8_WD_M4_M1_MASK\0" + /* 141043 */ "PseudoVAMOXOREI8_WD_M4_M1_MASK\0" + /* 141074 */ "PseudoVAMOMINUEI8_WD_M4_M1_MASK\0" + /* 141106 */ "PseudoVAMOMAXUEI8_WD_M4_M1_MASK\0" + /* 141138 */ "PseudoVAMOMAXEI8_WD_M4_M1_MASK\0" + /* 141169 */ "PseudoVRGATHEREI16_VV_M4_M1_MASK\0" + /* 141202 */ "PseudoVLOXSEG2EI32_V_M4_M1_MASK\0" + /* 141234 */ "PseudoVSOXSEG2EI32_V_M4_M1_MASK\0" + /* 141266 */ "PseudoVLUXSEG2EI32_V_M4_M1_MASK\0" + /* 141298 */ "PseudoVSUXSEG2EI32_V_M4_M1_MASK\0" + /* 141330 */ "PseudoVLOXSEG3EI32_V_M4_M1_MASK\0" + /* 141362 */ "PseudoVSOXSEG3EI32_V_M4_M1_MASK\0" + /* 141394 */ "PseudoVLUXSEG3EI32_V_M4_M1_MASK\0" + /* 141426 */ "PseudoVSUXSEG3EI32_V_M4_M1_MASK\0" + /* 141458 */ "PseudoVLOXSEG4EI32_V_M4_M1_MASK\0" + /* 141490 */ "PseudoVSOXSEG4EI32_V_M4_M1_MASK\0" + /* 141522 */ "PseudoVLUXSEG4EI32_V_M4_M1_MASK\0" + /* 141554 */ "PseudoVSUXSEG4EI32_V_M4_M1_MASK\0" + /* 141586 */ "PseudoVLOXSEG5EI32_V_M4_M1_MASK\0" + /* 141618 */ "PseudoVSOXSEG5EI32_V_M4_M1_MASK\0" + /* 141650 */ "PseudoVLUXSEG5EI32_V_M4_M1_MASK\0" + /* 141682 */ "PseudoVSUXSEG5EI32_V_M4_M1_MASK\0" + /* 141714 */ "PseudoVLOXSEG6EI32_V_M4_M1_MASK\0" + /* 141746 */ "PseudoVSOXSEG6EI32_V_M4_M1_MASK\0" + /* 141778 */ "PseudoVLUXSEG6EI32_V_M4_M1_MASK\0" + /* 141810 */ "PseudoVSUXSEG6EI32_V_M4_M1_MASK\0" + /* 141842 */ "PseudoVLOXSEG7EI32_V_M4_M1_MASK\0" + /* 141874 */ "PseudoVSOXSEG7EI32_V_M4_M1_MASK\0" + /* 141906 */ "PseudoVLUXSEG7EI32_V_M4_M1_MASK\0" + /* 141938 */ "PseudoVSUXSEG7EI32_V_M4_M1_MASK\0" + /* 141970 */ "PseudoVLOXSEG8EI32_V_M4_M1_MASK\0" + /* 142002 */ "PseudoVSOXSEG8EI32_V_M4_M1_MASK\0" + /* 142034 */ "PseudoVLUXSEG8EI32_V_M4_M1_MASK\0" + /* 142066 */ "PseudoVSUXSEG8EI32_V_M4_M1_MASK\0" + /* 142098 */ "PseudoVLOXEI32_V_M4_M1_MASK\0" + /* 142126 */ "PseudoVSOXEI32_V_M4_M1_MASK\0" + /* 142154 */ "PseudoVLUXEI32_V_M4_M1_MASK\0" + /* 142182 */ "PseudoVSUXEI32_V_M4_M1_MASK\0" + /* 142210 */ "PseudoVLOXSEG2EI64_V_M4_M1_MASK\0" + /* 142242 */ "PseudoVSOXSEG2EI64_V_M4_M1_MASK\0" + /* 142274 */ "PseudoVLUXSEG2EI64_V_M4_M1_MASK\0" + /* 142306 */ "PseudoVSUXSEG2EI64_V_M4_M1_MASK\0" + /* 142338 */ "PseudoVLOXSEG3EI64_V_M4_M1_MASK\0" + /* 142370 */ "PseudoVSOXSEG3EI64_V_M4_M1_MASK\0" + /* 142402 */ "PseudoVLUXSEG3EI64_V_M4_M1_MASK\0" + /* 142434 */ "PseudoVSUXSEG3EI64_V_M4_M1_MASK\0" + /* 142466 */ "PseudoVLOXSEG4EI64_V_M4_M1_MASK\0" + /* 142498 */ "PseudoVSOXSEG4EI64_V_M4_M1_MASK\0" + /* 142530 */ "PseudoVLUXSEG4EI64_V_M4_M1_MASK\0" + /* 142562 */ "PseudoVSUXSEG4EI64_V_M4_M1_MASK\0" + /* 142594 */ "PseudoVLOXSEG5EI64_V_M4_M1_MASK\0" + /* 142626 */ "PseudoVSOXSEG5EI64_V_M4_M1_MASK\0" + /* 142658 */ "PseudoVLUXSEG5EI64_V_M4_M1_MASK\0" + /* 142690 */ "PseudoVSUXSEG5EI64_V_M4_M1_MASK\0" + /* 142722 */ "PseudoVLOXSEG6EI64_V_M4_M1_MASK\0" + /* 142754 */ "PseudoVSOXSEG6EI64_V_M4_M1_MASK\0" + /* 142786 */ "PseudoVLUXSEG6EI64_V_M4_M1_MASK\0" + /* 142818 */ "PseudoVSUXSEG6EI64_V_M4_M1_MASK\0" + /* 142850 */ "PseudoVLOXSEG7EI64_V_M4_M1_MASK\0" + /* 142882 */ "PseudoVSOXSEG7EI64_V_M4_M1_MASK\0" + /* 142914 */ "PseudoVLUXSEG7EI64_V_M4_M1_MASK\0" + /* 142946 */ "PseudoVSUXSEG7EI64_V_M4_M1_MASK\0" + /* 142978 */ "PseudoVLOXSEG8EI64_V_M4_M1_MASK\0" + /* 143010 */ "PseudoVSOXSEG8EI64_V_M4_M1_MASK\0" + /* 143042 */ "PseudoVLUXSEG8EI64_V_M4_M1_MASK\0" + /* 143074 */ "PseudoVSUXSEG8EI64_V_M4_M1_MASK\0" + /* 143106 */ "PseudoVLOXEI64_V_M4_M1_MASK\0" + /* 143134 */ "PseudoVSOXEI64_V_M4_M1_MASK\0" + /* 143162 */ "PseudoVLUXEI64_V_M4_M1_MASK\0" + /* 143190 */ "PseudoVSUXEI64_V_M4_M1_MASK\0" + /* 143218 */ "PseudoVFSUB_VF16_M1_MASK\0" + /* 143243 */ "PseudoVFMSUB_VF16_M1_MASK\0" + /* 143269 */ "PseudoVFNMSUB_VF16_M1_MASK\0" + /* 143296 */ "PseudoVFRSUB_VF16_M1_MASK\0" + /* 143322 */ "PseudoVFWSUB_VF16_M1_MASK\0" + /* 143348 */ "PseudoVFMSAC_VF16_M1_MASK\0" + /* 143374 */ "PseudoVFNMSAC_VF16_M1_MASK\0" + /* 143401 */ "PseudoVFWNMSAC_VF16_M1_MASK\0" + /* 143429 */ "PseudoVFWMSAC_VF16_M1_MASK\0" + /* 143456 */ "PseudoVFMACC_VF16_M1_MASK\0" + /* 143482 */ "PseudoVFNMACC_VF16_M1_MASK\0" + /* 143509 */ "PseudoVFWNMACC_VF16_M1_MASK\0" + /* 143537 */ "PseudoVFWMACC_VF16_M1_MASK\0" + /* 143564 */ "PseudoVFADD_VF16_M1_MASK\0" + /* 143589 */ "PseudoVFMADD_VF16_M1_MASK\0" + /* 143615 */ "PseudoVFNMADD_VF16_M1_MASK\0" + /* 143642 */ "PseudoVFWADD_VF16_M1_MASK\0" + /* 143668 */ "PseudoVMFGE_VF16_M1_MASK\0" + /* 143693 */ "PseudoVMFLE_VF16_M1_MASK\0" + /* 143718 */ "PseudoVMFNE_VF16_M1_MASK\0" + /* 143743 */ "PseudoVFSGNJ_VF16_M1_MASK\0" + /* 143769 */ "PseudoVFMUL_VF16_M1_MASK\0" + /* 143794 */ "PseudoVFWMUL_VF16_M1_MASK\0" + /* 143820 */ "PseudoVFMIN_VF16_M1_MASK\0" + /* 143845 */ "PseudoVFSGNJN_VF16_M1_MASK\0" + /* 143872 */ "PseudoVFSLIDE1DOWN_VF16_M1_MASK\0" + /* 143904 */ "PseudoVFSLIDE1UP_VF16_M1_MASK\0" + /* 143934 */ "PseudoVMFEQ_VF16_M1_MASK\0" + /* 143959 */ "PseudoVMFGT_VF16_M1_MASK\0" + /* 143984 */ "PseudoVMFLT_VF16_M1_MASK\0" + /* 144009 */ "PseudoVFDIV_VF16_M1_MASK\0" + /* 144034 */ "PseudoVFRDIV_VF16_M1_MASK\0" + /* 144060 */ "PseudoVFMAX_VF16_M1_MASK\0" + /* 144085 */ "PseudoVFSGNJX_VF16_M1_MASK\0" + /* 144112 */ "PseudoVFWSUB_WF16_M1_MASK\0" + /* 144138 */ "PseudoVFWADD_WF16_M1_MASK\0" + /* 144164 */ "PseudoVLOXSEG2EI8_V_MF8_M1_MASK\0" + /* 144196 */ "PseudoVSOXSEG2EI8_V_MF8_M1_MASK\0" + /* 144228 */ "PseudoVLUXSEG2EI8_V_MF8_M1_MASK\0" + /* 144260 */ "PseudoVSUXSEG2EI8_V_MF8_M1_MASK\0" + /* 144292 */ "PseudoVLOXSEG3EI8_V_MF8_M1_MASK\0" + /* 144324 */ "PseudoVSOXSEG3EI8_V_MF8_M1_MASK\0" + /* 144356 */ "PseudoVLUXSEG3EI8_V_MF8_M1_MASK\0" + /* 144388 */ "PseudoVSUXSEG3EI8_V_MF8_M1_MASK\0" + /* 144420 */ "PseudoVLOXSEG4EI8_V_MF8_M1_MASK\0" + /* 144452 */ "PseudoVSOXSEG4EI8_V_MF8_M1_MASK\0" + /* 144484 */ "PseudoVLUXSEG4EI8_V_MF8_M1_MASK\0" + /* 144516 */ "PseudoVSUXSEG4EI8_V_MF8_M1_MASK\0" + /* 144548 */ "PseudoVLOXSEG5EI8_V_MF8_M1_MASK\0" + /* 144580 */ "PseudoVSOXSEG5EI8_V_MF8_M1_MASK\0" + /* 144612 */ "PseudoVLUXSEG5EI8_V_MF8_M1_MASK\0" + /* 144644 */ "PseudoVSUXSEG5EI8_V_MF8_M1_MASK\0" + /* 144676 */ "PseudoVLOXSEG6EI8_V_MF8_M1_MASK\0" + /* 144708 */ "PseudoVSOXSEG6EI8_V_MF8_M1_MASK\0" + /* 144740 */ "PseudoVLUXSEG6EI8_V_MF8_M1_MASK\0" + /* 144772 */ "PseudoVSUXSEG6EI8_V_MF8_M1_MASK\0" + /* 144804 */ "PseudoVLOXSEG7EI8_V_MF8_M1_MASK\0" + /* 144836 */ "PseudoVSOXSEG7EI8_V_MF8_M1_MASK\0" + /* 144868 */ "PseudoVLUXSEG7EI8_V_MF8_M1_MASK\0" + /* 144900 */ "PseudoVSUXSEG7EI8_V_MF8_M1_MASK\0" + /* 144932 */ "PseudoVLOXSEG8EI8_V_MF8_M1_MASK\0" + /* 144964 */ "PseudoVSOXSEG8EI8_V_MF8_M1_MASK\0" + /* 144996 */ "PseudoVLUXSEG8EI8_V_MF8_M1_MASK\0" + /* 145028 */ "PseudoVSUXSEG8EI8_V_MF8_M1_MASK\0" + /* 145060 */ "PseudoVLOXEI8_V_MF8_M1_MASK\0" + /* 145088 */ "PseudoVSOXEI8_V_MF8_M1_MASK\0" + /* 145116 */ "PseudoVLUXEI8_V_MF8_M1_MASK\0" + /* 145144 */ "PseudoVSUXEI8_V_MF8_M1_MASK\0" + /* 145172 */ "PseudoVSEXT_VF8_M1_MASK\0" + /* 145196 */ "PseudoVZEXT_VF8_M1_MASK\0" + /* 145220 */ "PseudoVAMOADDEI8_WD_M8_M1_MASK\0" + /* 145251 */ "PseudoVAMOANDEI8_WD_M8_M1_MASK\0" + /* 145282 */ "PseudoVAMOMINEI8_WD_M8_M1_MASK\0" + /* 145313 */ "PseudoVAMOSWAPEI8_WD_M8_M1_MASK\0" + /* 145345 */ "PseudoVAMOOREI8_WD_M8_M1_MASK\0" + /* 145375 */ "PseudoVAMOXOREI8_WD_M8_M1_MASK\0" + /* 145406 */ "PseudoVAMOMINUEI8_WD_M8_M1_MASK\0" + /* 145438 */ "PseudoVAMOMAXUEI8_WD_M8_M1_MASK\0" + /* 145470 */ "PseudoVAMOMAXEI8_WD_M8_M1_MASK\0" + /* 145501 */ "PseudoVLOXSEG2EI64_V_M8_M1_MASK\0" + /* 145533 */ "PseudoVSOXSEG2EI64_V_M8_M1_MASK\0" + /* 145565 */ "PseudoVLUXSEG2EI64_V_M8_M1_MASK\0" + /* 145597 */ "PseudoVSUXSEG2EI64_V_M8_M1_MASK\0" + /* 145629 */ "PseudoVLOXSEG3EI64_V_M8_M1_MASK\0" + /* 145661 */ "PseudoVSOXSEG3EI64_V_M8_M1_MASK\0" + /* 145693 */ "PseudoVLUXSEG3EI64_V_M8_M1_MASK\0" + /* 145725 */ "PseudoVSUXSEG3EI64_V_M8_M1_MASK\0" + /* 145757 */ "PseudoVLOXSEG4EI64_V_M8_M1_MASK\0" + /* 145789 */ "PseudoVSOXSEG4EI64_V_M8_M1_MASK\0" + /* 145821 */ "PseudoVLUXSEG4EI64_V_M8_M1_MASK\0" + /* 145853 */ "PseudoVSUXSEG4EI64_V_M8_M1_MASK\0" + /* 145885 */ "PseudoVLOXSEG5EI64_V_M8_M1_MASK\0" + /* 145917 */ "PseudoVSOXSEG5EI64_V_M8_M1_MASK\0" + /* 145949 */ "PseudoVLUXSEG5EI64_V_M8_M1_MASK\0" + /* 145981 */ "PseudoVSUXSEG5EI64_V_M8_M1_MASK\0" + /* 146013 */ "PseudoVLOXSEG6EI64_V_M8_M1_MASK\0" + /* 146045 */ "PseudoVSOXSEG6EI64_V_M8_M1_MASK\0" + /* 146077 */ "PseudoVLUXSEG6EI64_V_M8_M1_MASK\0" + /* 146109 */ "PseudoVSUXSEG6EI64_V_M8_M1_MASK\0" + /* 146141 */ "PseudoVLOXSEG7EI64_V_M8_M1_MASK\0" + /* 146173 */ "PseudoVSOXSEG7EI64_V_M8_M1_MASK\0" + /* 146205 */ "PseudoVLUXSEG7EI64_V_M8_M1_MASK\0" + /* 146237 */ "PseudoVSUXSEG7EI64_V_M8_M1_MASK\0" + /* 146269 */ "PseudoVLOXSEG8EI64_V_M8_M1_MASK\0" + /* 146301 */ "PseudoVSOXSEG8EI64_V_M8_M1_MASK\0" + /* 146333 */ "PseudoVLUXSEG8EI64_V_M8_M1_MASK\0" + /* 146365 */ "PseudoVSUXSEG8EI64_V_M8_M1_MASK\0" + /* 146397 */ "PseudoVLOXEI64_V_M8_M1_MASK\0" + /* 146425 */ "PseudoVSOXEI64_V_M8_M1_MASK\0" + /* 146453 */ "PseudoVLUXEI64_V_M8_M1_MASK\0" + /* 146481 */ "PseudoVSUXEI64_V_M8_M1_MASK\0" + /* 146509 */ "PseudoVSSRA_VI_M1_MASK\0" + /* 146532 */ "PseudoVSRA_VI_M1_MASK\0" + /* 146554 */ "PseudoVRSUB_VI_M1_MASK\0" + /* 146577 */ "PseudoVSADD_VI_M1_MASK\0" + /* 146600 */ "PseudoVADD_VI_M1_MASK\0" + /* 146622 */ "PseudoVAND_VI_M1_MASK\0" + /* 146644 */ "PseudoVMSLE_VI_M1_MASK\0" + /* 146667 */ "PseudoVMSNE_VI_M1_MASK\0" + /* 146690 */ "PseudoVSLL_VI_M1_MASK\0" + /* 146712 */ "PseudoVSSRL_VI_M1_MASK\0" + /* 146735 */ "PseudoVSRL_VI_M1_MASK\0" + /* 146757 */ "PseudoVSLIDEDOWN_VI_M1_MASK\0" + /* 146785 */ "PseudoVSLIDEUP_VI_M1_MASK\0" + /* 146811 */ "PseudoVMSEQ_VI_M1_MASK\0" + /* 146834 */ "PseudoVRGATHER_VI_M1_MASK\0" + /* 146860 */ "PseudoVOR_VI_M1_MASK\0" + /* 146881 */ "PseudoVXOR_VI_M1_MASK\0" + /* 146903 */ "PseudoVMSGT_VI_M1_MASK\0" + /* 146926 */ "PseudoVSADDU_VI_M1_MASK\0" + /* 146950 */ "PseudoVMSLEU_VI_M1_MASK\0" + /* 146974 */ "PseudoVMSGTU_VI_M1_MASK\0" + /* 146998 */ "PseudoVNSRA_WI_M1_MASK\0" + /* 147021 */ "PseudoVNSRL_WI_M1_MASK\0" + /* 147044 */ "PseudoVNCLIP_WI_M1_MASK\0" + /* 147068 */ "PseudoVNCLIPU_WI_M1_MASK\0" + /* 147093 */ "PseudoVIOTA_M_M1_MASK\0" + /* 147115 */ "PseudoVREDAND_VS_M1_MASK\0" + /* 147140 */ "PseudoVREDSUM_VS_M1_MASK\0" + /* 147165 */ "PseudoVWREDSUM_VS_M1_MASK\0" + /* 147191 */ "PseudoVFREDOSUM_VS_M1_MASK\0" + /* 147218 */ "PseudoVFWREDOSUM_VS_M1_MASK\0" + /* 147246 */ "PseudoVFREDUSUM_VS_M1_MASK\0" + /* 147273 */ "PseudoVFWREDUSUM_VS_M1_MASK\0" + /* 147301 */ "PseudoVFREDMIN_VS_M1_MASK\0" + /* 147327 */ "PseudoVREDMIN_VS_M1_MASK\0" + /* 147352 */ "PseudoVREDOR_VS_M1_MASK\0" + /* 147376 */ "PseudoVREDXOR_VS_M1_MASK\0" + /* 147401 */ "PseudoVWREDSUMU_VS_M1_MASK\0" + /* 147428 */ "PseudoVREDMINU_VS_M1_MASK\0" + /* 147454 */ "PseudoVREDMAXU_VS_M1_MASK\0" + /* 147480 */ "PseudoVFREDMAX_VS_M1_MASK\0" + /* 147506 */ "PseudoVREDMAX_VS_M1_MASK\0" + /* 147531 */ "PseudoVSSRA_VV_M1_MASK\0" + /* 147554 */ "PseudoVSRA_VV_M1_MASK\0" + /* 147576 */ "PseudoVASUB_VV_M1_MASK\0" + /* 147599 */ "PseudoVFSUB_VV_M1_MASK\0" + /* 147622 */ "PseudoVFMSUB_VV_M1_MASK\0" + /* 147646 */ "PseudoVFNMSUB_VV_M1_MASK\0" + /* 147671 */ "PseudoVNMSUB_VV_M1_MASK\0" + /* 147695 */ "PseudoVSSUB_VV_M1_MASK\0" + /* 147718 */ "PseudoVSUB_VV_M1_MASK\0" + /* 147740 */ "PseudoVFWSUB_VV_M1_MASK\0" + /* 147764 */ "PseudoVWSUB_VV_M1_MASK\0" + /* 147787 */ "PseudoVFMSAC_VV_M1_MASK\0" + /* 147811 */ "PseudoVFNMSAC_VV_M1_MASK\0" + /* 147836 */ "PseudoVNMSAC_VV_M1_MASK\0" + /* 147860 */ "PseudoVFWNMSAC_VV_M1_MASK\0" + /* 147886 */ "PseudoVFWMSAC_VV_M1_MASK\0" + /* 147911 */ "PseudoVFMACC_VV_M1_MASK\0" + /* 147935 */ "PseudoVFNMACC_VV_M1_MASK\0" + /* 147960 */ "PseudoVFWNMACC_VV_M1_MASK\0" + /* 147986 */ "PseudoVMACC_VV_M1_MASK\0" + /* 148009 */ "PseudoVFWMACC_VV_M1_MASK\0" + /* 148034 */ "PseudoVWMACC_VV_M1_MASK\0" + /* 148058 */ "PseudoVAADD_VV_M1_MASK\0" + /* 148081 */ "PseudoVFADD_VV_M1_MASK\0" + /* 148104 */ "PseudoVFMADD_VV_M1_MASK\0" + /* 148128 */ "PseudoVFNMADD_VV_M1_MASK\0" + /* 148153 */ "PseudoVMADD_VV_M1_MASK\0" + /* 148176 */ "PseudoVSADD_VV_M1_MASK\0" + /* 148199 */ "PseudoVADD_VV_M1_MASK\0" + /* 148221 */ "PseudoVFWADD_VV_M1_MASK\0" + /* 148245 */ "PseudoVWADD_VV_M1_MASK\0" + /* 148268 */ "PseudoVAND_VV_M1_MASK\0" + /* 148290 */ "PseudoVMFLE_VV_M1_MASK\0" + /* 148313 */ "PseudoVMSLE_VV_M1_MASK\0" + /* 148336 */ "PseudoVMFNE_VV_M1_MASK\0" + /* 148359 */ "PseudoVMSNE_VV_M1_MASK\0" + /* 148382 */ "PseudoVMULH_VV_M1_MASK\0" + /* 148405 */ "PseudoVFSGNJ_VV_M1_MASK\0" + /* 148429 */ "PseudoVSLL_VV_M1_MASK\0" + /* 148451 */ "PseudoVSSRL_VV_M1_MASK\0" + /* 148474 */ "PseudoVSRL_VV_M1_MASK\0" + /* 148496 */ "PseudoVFMUL_VV_M1_MASK\0" + /* 148519 */ "PseudoVSMUL_VV_M1_MASK\0" + /* 148542 */ "PseudoVMUL_VV_M1_MASK\0" + /* 148564 */ "PseudoVFWMUL_VV_M1_MASK\0" + /* 148588 */ "PseudoVWMUL_VV_M1_MASK\0" + /* 148611 */ "PseudoVREM_VV_M1_MASK\0" + /* 148633 */ "PseudoVFMIN_VV_M1_MASK\0" + /* 148656 */ "PseudoVMIN_VV_M1_MASK\0" + /* 148678 */ "PseudoVFSGNJN_VV_M1_MASK\0" + /* 148703 */ "PseudoVMFEQ_VV_M1_MASK\0" + /* 148726 */ "PseudoVMSEQ_VV_M1_MASK\0" + /* 148749 */ "PseudoVRGATHER_VV_M1_MASK\0" + /* 148775 */ "PseudoVOR_VV_M1_MASK\0" + /* 148796 */ "PseudoVXOR_VV_M1_MASK\0" + /* 148818 */ "PseudoVMFLT_VV_M1_MASK\0" + /* 148841 */ "PseudoVMSLT_VV_M1_MASK\0" + /* 148864 */ "PseudoVASUBU_VV_M1_MASK\0" + /* 148888 */ "PseudoVSSUBU_VV_M1_MASK\0" + /* 148912 */ "PseudoVWSUBU_VV_M1_MASK\0" + /* 148936 */ "PseudoVWMACCU_VV_M1_MASK\0" + /* 148961 */ "PseudoVAADDU_VV_M1_MASK\0" + /* 148985 */ "PseudoVSADDU_VV_M1_MASK\0" + /* 149009 */ "PseudoVWADDU_VV_M1_MASK\0" + /* 149033 */ "PseudoVMSLEU_VV_M1_MASK\0" + /* 149057 */ "PseudoVMULHU_VV_M1_MASK\0" + /* 149081 */ "PseudoVWMULU_VV_M1_MASK\0" + /* 149105 */ "PseudoVREMU_VV_M1_MASK\0" + /* 149128 */ "PseudoVMINU_VV_M1_MASK\0" + /* 149151 */ "PseudoVWMACCSU_VV_M1_MASK\0" + /* 149177 */ "PseudoVMULHSU_VV_M1_MASK\0" + /* 149202 */ "PseudoVWMULSU_VV_M1_MASK\0" + /* 149227 */ "PseudoVMSLTU_VV_M1_MASK\0" + /* 149251 */ "PseudoVDIVU_VV_M1_MASK\0" + /* 149274 */ "PseudoVMAXU_VV_M1_MASK\0" + /* 149297 */ "PseudoVFDIV_VV_M1_MASK\0" + /* 149320 */ "PseudoVDIV_VV_M1_MASK\0" + /* 149342 */ "PseudoVFMAX_VV_M1_MASK\0" + /* 149365 */ "PseudoVMAX_VV_M1_MASK\0" + /* 149387 */ "PseudoVFSGNJX_VV_M1_MASK\0" + /* 149412 */ "PseudoVNSRA_WV_M1_MASK\0" + /* 149435 */ "PseudoVFWSUB_WV_M1_MASK\0" + /* 149459 */ "PseudoVWSUB_WV_M1_MASK\0" + /* 149482 */ "PseudoVFWADD_WV_M1_MASK\0" + /* 149506 */ "PseudoVWADD_WV_M1_MASK\0" + /* 149529 */ "PseudoVNSRL_WV_M1_MASK\0" + /* 149552 */ "PseudoVNCLIP_WV_M1_MASK\0" + /* 149576 */ "PseudoVWSUBU_WV_M1_MASK\0" + /* 149600 */ "PseudoVWADDU_WV_M1_MASK\0" + /* 149624 */ "PseudoVNCLIPU_WV_M1_MASK\0" + /* 149649 */ "PseudoVLSEG2E32_V_M1_MASK\0" + /* 149675 */ "PseudoVLSSEG2E32_V_M1_MASK\0" + /* 149702 */ "PseudoVSSSEG2E32_V_M1_MASK\0" + /* 149729 */ "PseudoVSSEG2E32_V_M1_MASK\0" + /* 149755 */ "PseudoVLSEG3E32_V_M1_MASK\0" + /* 149781 */ "PseudoVLSSEG3E32_V_M1_MASK\0" + /* 149808 */ "PseudoVSSSEG3E32_V_M1_MASK\0" + /* 149835 */ "PseudoVSSEG3E32_V_M1_MASK\0" + /* 149861 */ "PseudoVLSEG4E32_V_M1_MASK\0" + /* 149887 */ "PseudoVLSSEG4E32_V_M1_MASK\0" + /* 149914 */ "PseudoVSSSEG4E32_V_M1_MASK\0" + /* 149941 */ "PseudoVSSEG4E32_V_M1_MASK\0" + /* 149967 */ "PseudoVLSEG5E32_V_M1_MASK\0" + /* 149993 */ "PseudoVLSSEG5E32_V_M1_MASK\0" + /* 150020 */ "PseudoVSSSEG5E32_V_M1_MASK\0" + /* 150047 */ "PseudoVSSEG5E32_V_M1_MASK\0" + /* 150073 */ "PseudoVLSEG6E32_V_M1_MASK\0" + /* 150099 */ "PseudoVLSSEG6E32_V_M1_MASK\0" + /* 150126 */ "PseudoVSSSEG6E32_V_M1_MASK\0" + /* 150153 */ "PseudoVSSEG6E32_V_M1_MASK\0" + /* 150179 */ "PseudoVLSEG7E32_V_M1_MASK\0" + /* 150205 */ "PseudoVLSSEG7E32_V_M1_MASK\0" + /* 150232 */ "PseudoVSSSEG7E32_V_M1_MASK\0" + /* 150259 */ "PseudoVSSEG7E32_V_M1_MASK\0" + /* 150285 */ "PseudoVLSEG8E32_V_M1_MASK\0" + /* 150311 */ "PseudoVLSSEG8E32_V_M1_MASK\0" + /* 150338 */ "PseudoVSSSEG8E32_V_M1_MASK\0" + /* 150365 */ "PseudoVSSEG8E32_V_M1_MASK\0" + /* 150391 */ "PseudoVLE32_V_M1_MASK\0" + /* 150413 */ "PseudoVLSE32_V_M1_MASK\0" + /* 150436 */ "PseudoVSSE32_V_M1_MASK\0" + /* 150459 */ "PseudoVSE32_V_M1_MASK\0" + /* 150481 */ "PseudoVLSEG2E64_V_M1_MASK\0" + /* 150507 */ "PseudoVLSSEG2E64_V_M1_MASK\0" + /* 150534 */ "PseudoVSSSEG2E64_V_M1_MASK\0" + /* 150561 */ "PseudoVSSEG2E64_V_M1_MASK\0" + /* 150587 */ "PseudoVLSEG3E64_V_M1_MASK\0" + /* 150613 */ "PseudoVLSSEG3E64_V_M1_MASK\0" + /* 150640 */ "PseudoVSSSEG3E64_V_M1_MASK\0" + /* 150667 */ "PseudoVSSEG3E64_V_M1_MASK\0" + /* 150693 */ "PseudoVLSEG4E64_V_M1_MASK\0" + /* 150719 */ "PseudoVLSSEG4E64_V_M1_MASK\0" + /* 150746 */ "PseudoVSSSEG4E64_V_M1_MASK\0" + /* 150773 */ "PseudoVSSEG4E64_V_M1_MASK\0" + /* 150799 */ "PseudoVLSEG5E64_V_M1_MASK\0" + /* 150825 */ "PseudoVLSSEG5E64_V_M1_MASK\0" + /* 150852 */ "PseudoVSSSEG5E64_V_M1_MASK\0" + /* 150879 */ "PseudoVSSEG5E64_V_M1_MASK\0" + /* 150905 */ "PseudoVLSEG6E64_V_M1_MASK\0" + /* 150931 */ "PseudoVLSSEG6E64_V_M1_MASK\0" + /* 150958 */ "PseudoVSSSEG6E64_V_M1_MASK\0" + /* 150985 */ "PseudoVSSEG6E64_V_M1_MASK\0" + /* 151011 */ "PseudoVLSEG7E64_V_M1_MASK\0" + /* 151037 */ "PseudoVLSSEG7E64_V_M1_MASK\0" + /* 151064 */ "PseudoVSSSEG7E64_V_M1_MASK\0" + /* 151091 */ "PseudoVSSEG7E64_V_M1_MASK\0" + /* 151117 */ "PseudoVLSEG8E64_V_M1_MASK\0" + /* 151143 */ "PseudoVLSSEG8E64_V_M1_MASK\0" + /* 151170 */ "PseudoVSSSEG8E64_V_M1_MASK\0" + /* 151197 */ "PseudoVSSEG8E64_V_M1_MASK\0" + /* 151223 */ "PseudoVLE64_V_M1_MASK\0" + /* 151245 */ "PseudoVLSE64_V_M1_MASK\0" + /* 151268 */ "PseudoVSSE64_V_M1_MASK\0" + /* 151291 */ "PseudoVSE64_V_M1_MASK\0" + /* 151313 */ "PseudoVLSEG2E16_V_M1_MASK\0" + /* 151339 */ "PseudoVLSSEG2E16_V_M1_MASK\0" + /* 151366 */ "PseudoVSSSEG2E16_V_M1_MASK\0" + /* 151393 */ "PseudoVSSEG2E16_V_M1_MASK\0" + /* 151419 */ "PseudoVLSEG3E16_V_M1_MASK\0" + /* 151445 */ "PseudoVLSSEG3E16_V_M1_MASK\0" + /* 151472 */ "PseudoVSSSEG3E16_V_M1_MASK\0" + /* 151499 */ "PseudoVSSEG3E16_V_M1_MASK\0" + /* 151525 */ "PseudoVLSEG4E16_V_M1_MASK\0" + /* 151551 */ "PseudoVLSSEG4E16_V_M1_MASK\0" + /* 151578 */ "PseudoVSSSEG4E16_V_M1_MASK\0" + /* 151605 */ "PseudoVSSEG4E16_V_M1_MASK\0" + /* 151631 */ "PseudoVLSEG5E16_V_M1_MASK\0" + /* 151657 */ "PseudoVLSSEG5E16_V_M1_MASK\0" + /* 151684 */ "PseudoVSSSEG5E16_V_M1_MASK\0" + /* 151711 */ "PseudoVSSEG5E16_V_M1_MASK\0" + /* 151737 */ "PseudoVLSEG6E16_V_M1_MASK\0" + /* 151763 */ "PseudoVLSSEG6E16_V_M1_MASK\0" + /* 151790 */ "PseudoVSSSEG6E16_V_M1_MASK\0" + /* 151817 */ "PseudoVSSEG6E16_V_M1_MASK\0" + /* 151843 */ "PseudoVLSEG7E16_V_M1_MASK\0" + /* 151869 */ "PseudoVLSSEG7E16_V_M1_MASK\0" + /* 151896 */ "PseudoVSSSEG7E16_V_M1_MASK\0" + /* 151923 */ "PseudoVSSEG7E16_V_M1_MASK\0" + /* 151949 */ "PseudoVLSEG8E16_V_M1_MASK\0" + /* 151975 */ "PseudoVLSSEG8E16_V_M1_MASK\0" + /* 152002 */ "PseudoVSSSEG8E16_V_M1_MASK\0" + /* 152029 */ "PseudoVSSEG8E16_V_M1_MASK\0" + /* 152055 */ "PseudoVLE16_V_M1_MASK\0" + /* 152077 */ "PseudoVLSE16_V_M1_MASK\0" + /* 152100 */ "PseudoVSSE16_V_M1_MASK\0" + /* 152123 */ "PseudoVSE16_V_M1_MASK\0" + /* 152145 */ "PseudoVFREC7_V_M1_MASK\0" + /* 152168 */ "PseudoVFRSQRT7_V_M1_MASK\0" + /* 152193 */ "PseudoVLSEG2E8_V_M1_MASK\0" + /* 152218 */ "PseudoVLSSEG2E8_V_M1_MASK\0" + /* 152244 */ "PseudoVSSSEG2E8_V_M1_MASK\0" + /* 152270 */ "PseudoVSSEG2E8_V_M1_MASK\0" + /* 152295 */ "PseudoVLSEG3E8_V_M1_MASK\0" + /* 152320 */ "PseudoVLSSEG3E8_V_M1_MASK\0" + /* 152346 */ "PseudoVSSSEG3E8_V_M1_MASK\0" + /* 152372 */ "PseudoVSSEG3E8_V_M1_MASK\0" + /* 152397 */ "PseudoVLSEG4E8_V_M1_MASK\0" + /* 152422 */ "PseudoVLSSEG4E8_V_M1_MASK\0" + /* 152448 */ "PseudoVSSSEG4E8_V_M1_MASK\0" + /* 152474 */ "PseudoVSSEG4E8_V_M1_MASK\0" + /* 152499 */ "PseudoVLSEG5E8_V_M1_MASK\0" + /* 152524 */ "PseudoVLSSEG5E8_V_M1_MASK\0" + /* 152550 */ "PseudoVSSSEG5E8_V_M1_MASK\0" + /* 152576 */ "PseudoVSSEG5E8_V_M1_MASK\0" + /* 152601 */ "PseudoVLSEG6E8_V_M1_MASK\0" + /* 152626 */ "PseudoVLSSEG6E8_V_M1_MASK\0" + /* 152652 */ "PseudoVSSSEG6E8_V_M1_MASK\0" + /* 152678 */ "PseudoVSSEG6E8_V_M1_MASK\0" + /* 152703 */ "PseudoVLSEG7E8_V_M1_MASK\0" + /* 152728 */ "PseudoVLSSEG7E8_V_M1_MASK\0" + /* 152754 */ "PseudoVSSSEG7E8_V_M1_MASK\0" + /* 152780 */ "PseudoVSSEG7E8_V_M1_MASK\0" + /* 152805 */ "PseudoVLSEG8E8_V_M1_MASK\0" + /* 152830 */ "PseudoVLSSEG8E8_V_M1_MASK\0" + /* 152856 */ "PseudoVSSSEG8E8_V_M1_MASK\0" + /* 152882 */ "PseudoVSSEG8E8_V_M1_MASK\0" + /* 152907 */ "PseudoVLE8_V_M1_MASK\0" + /* 152928 */ "PseudoVLSE8_V_M1_MASK\0" + /* 152950 */ "PseudoVSSE8_V_M1_MASK\0" + /* 152972 */ "PseudoVSE8_V_M1_MASK\0" + /* 152993 */ "PseudoVID_V_M1_MASK\0" + /* 153013 */ "PseudoVLSEG2E32FF_V_M1_MASK\0" + /* 153041 */ "PseudoVLSEG3E32FF_V_M1_MASK\0" + /* 153069 */ "PseudoVLSEG4E32FF_V_M1_MASK\0" + /* 153097 */ "PseudoVLSEG5E32FF_V_M1_MASK\0" + /* 153125 */ "PseudoVLSEG6E32FF_V_M1_MASK\0" + /* 153153 */ "PseudoVLSEG7E32FF_V_M1_MASK\0" + /* 153181 */ "PseudoVLSEG8E32FF_V_M1_MASK\0" + /* 153209 */ "PseudoVLE32FF_V_M1_MASK\0" + /* 153233 */ "PseudoVLSEG2E64FF_V_M1_MASK\0" + /* 153261 */ "PseudoVLSEG3E64FF_V_M1_MASK\0" + /* 153289 */ "PseudoVLSEG4E64FF_V_M1_MASK\0" + /* 153317 */ "PseudoVLSEG5E64FF_V_M1_MASK\0" + /* 153345 */ "PseudoVLSEG6E64FF_V_M1_MASK\0" + /* 153373 */ "PseudoVLSEG7E64FF_V_M1_MASK\0" + /* 153401 */ "PseudoVLSEG8E64FF_V_M1_MASK\0" + /* 153429 */ "PseudoVLE64FF_V_M1_MASK\0" + /* 153453 */ "PseudoVLSEG2E16FF_V_M1_MASK\0" + /* 153481 */ "PseudoVLSEG3E16FF_V_M1_MASK\0" + /* 153509 */ "PseudoVLSEG4E16FF_V_M1_MASK\0" + /* 153537 */ "PseudoVLSEG5E16FF_V_M1_MASK\0" + /* 153565 */ "PseudoVLSEG6E16FF_V_M1_MASK\0" + /* 153593 */ "PseudoVLSEG7E16FF_V_M1_MASK\0" + /* 153621 */ "PseudoVLSEG8E16FF_V_M1_MASK\0" + /* 153649 */ "PseudoVLE16FF_V_M1_MASK\0" + /* 153673 */ "PseudoVLSEG2E8FF_V_M1_MASK\0" + /* 153700 */ "PseudoVLSEG3E8FF_V_M1_MASK\0" + /* 153727 */ "PseudoVLSEG4E8FF_V_M1_MASK\0" + /* 153754 */ "PseudoVLSEG5E8FF_V_M1_MASK\0" + /* 153781 */ "PseudoVLSEG6E8FF_V_M1_MASK\0" + /* 153808 */ "PseudoVLSEG7E8FF_V_M1_MASK\0" + /* 153835 */ "PseudoVLSEG8E8FF_V_M1_MASK\0" + /* 153862 */ "PseudoVLE8FF_V_M1_MASK\0" + /* 153885 */ "PseudoVFWCVT_F_F_V_M1_MASK\0" + /* 153912 */ "PseudoVFCVT_XU_F_V_M1_MASK\0" + /* 153939 */ "PseudoVFWCVT_XU_F_V_M1_MASK\0" + /* 153967 */ "PseudoVFCVT_RTZ_XU_F_V_M1_MASK\0" + /* 153998 */ "PseudoVFWCVT_RTZ_XU_F_V_M1_MASK\0" + /* 154030 */ "PseudoVFCVT_X_F_V_M1_MASK\0" + /* 154056 */ "PseudoVFWCVT_X_F_V_M1_MASK\0" + /* 154083 */ "PseudoVFCVT_RTZ_X_F_V_M1_MASK\0" + /* 154113 */ "PseudoVFWCVT_RTZ_X_F_V_M1_MASK\0" + /* 154144 */ "PseudoVFCLASS_V_M1_MASK\0" + /* 154168 */ "PseudoVFSQRT_V_M1_MASK\0" + /* 154191 */ "PseudoVFCVT_F_XU_V_M1_MASK\0" + /* 154218 */ "PseudoVFWCVT_F_XU_V_M1_MASK\0" + /* 154246 */ "PseudoVFCVT_F_X_V_M1_MASK\0" + /* 154272 */ "PseudoVFWCVT_F_X_V_M1_MASK\0" + /* 154299 */ "PseudoVFNCVT_ROD_F_F_W_M1_MASK\0" + /* 154330 */ "PseudoVFNCVT_F_F_W_M1_MASK\0" + /* 154357 */ "PseudoVFNCVT_XU_F_W_M1_MASK\0" + /* 154385 */ "PseudoVFNCVT_RTZ_XU_F_W_M1_MASK\0" + /* 154417 */ "PseudoVFNCVT_X_F_W_M1_MASK\0" + /* 154444 */ "PseudoVFNCVT_RTZ_X_F_W_M1_MASK\0" + /* 154475 */ "PseudoVFNCVT_F_XU_W_M1_MASK\0" + /* 154503 */ "PseudoVFNCVT_F_X_W_M1_MASK\0" + /* 154530 */ "PseudoVSSRA_VX_M1_MASK\0" + /* 154553 */ "PseudoVSRA_VX_M1_MASK\0" + /* 154575 */ "PseudoVASUB_VX_M1_MASK\0" + /* 154598 */ "PseudoVNMSUB_VX_M1_MASK\0" + /* 154622 */ "PseudoVRSUB_VX_M1_MASK\0" + /* 154645 */ "PseudoVSSUB_VX_M1_MASK\0" + /* 154668 */ "PseudoVSUB_VX_M1_MASK\0" + /* 154690 */ "PseudoVWSUB_VX_M1_MASK\0" + /* 154713 */ "PseudoVNMSAC_VX_M1_MASK\0" + /* 154737 */ "PseudoVMACC_VX_M1_MASK\0" + /* 154760 */ "PseudoVWMACC_VX_M1_MASK\0" + /* 154784 */ "PseudoVAADD_VX_M1_MASK\0" + /* 154807 */ "PseudoVMADD_VX_M1_MASK\0" + /* 154830 */ "PseudoVSADD_VX_M1_MASK\0" + /* 154853 */ "PseudoVADD_VX_M1_MASK\0" + /* 154875 */ "PseudoVWADD_VX_M1_MASK\0" + /* 154898 */ "PseudoVAND_VX_M1_MASK\0" + /* 154920 */ "PseudoVMSLE_VX_M1_MASK\0" + /* 154943 */ "PseudoVMSNE_VX_M1_MASK\0" + /* 154966 */ "PseudoVMULH_VX_M1_MASK\0" + /* 154989 */ "PseudoVSLL_VX_M1_MASK\0" + /* 155011 */ "PseudoVSSRL_VX_M1_MASK\0" + /* 155034 */ "PseudoVSRL_VX_M1_MASK\0" + /* 155056 */ "PseudoVSMUL_VX_M1_MASK\0" + /* 155079 */ "PseudoVMUL_VX_M1_MASK\0" + /* 155101 */ "PseudoVWMUL_VX_M1_MASK\0" + /* 155124 */ "PseudoVREM_VX_M1_MASK\0" + /* 155146 */ "PseudoVMIN_VX_M1_MASK\0" + /* 155168 */ "PseudoVSLIDE1DOWN_VX_M1_MASK\0" + /* 155197 */ "PseudoVSLIDEDOWN_VX_M1_MASK\0" + /* 155225 */ "PseudoVSLIDE1UP_VX_M1_MASK\0" + /* 155252 */ "PseudoVSLIDEUP_VX_M1_MASK\0" + /* 155278 */ "PseudoVMSEQ_VX_M1_MASK\0" + /* 155301 */ "PseudoVRGATHER_VX_M1_MASK\0" + /* 155327 */ "PseudoVOR_VX_M1_MASK\0" + /* 155348 */ "PseudoVXOR_VX_M1_MASK\0" + /* 155370 */ "PseudoVWMACCUS_VX_M1_MASK\0" + /* 155396 */ "PseudoVMSGT_VX_M1_MASK\0" + /* 155419 */ "PseudoVMSLT_VX_M1_MASK\0" + /* 155442 */ "PseudoVASUBU_VX_M1_MASK\0" + /* 155466 */ "PseudoVSSUBU_VX_M1_MASK\0" + /* 155490 */ "PseudoVWSUBU_VX_M1_MASK\0" + /* 155514 */ "PseudoVWMACCU_VX_M1_MASK\0" + /* 155539 */ "PseudoVAADDU_VX_M1_MASK\0" + /* 155563 */ "PseudoVSADDU_VX_M1_MASK\0" + /* 155587 */ "PseudoVWADDU_VX_M1_MASK\0" + /* 155611 */ "PseudoVMSLEU_VX_M1_MASK\0" + /* 155635 */ "PseudoVMULHU_VX_M1_MASK\0" + /* 155659 */ "PseudoVWMULU_VX_M1_MASK\0" + /* 155683 */ "PseudoVREMU_VX_M1_MASK\0" + /* 155706 */ "PseudoVMINU_VX_M1_MASK\0" + /* 155729 */ "PseudoVWMACCSU_VX_M1_MASK\0" + /* 155755 */ "PseudoVMULHSU_VX_M1_MASK\0" + /* 155780 */ "PseudoVWMULSU_VX_M1_MASK\0" + /* 155805 */ "PseudoVMSGTU_VX_M1_MASK\0" + /* 155829 */ "PseudoVMSLTU_VX_M1_MASK\0" + /* 155853 */ "PseudoVDIVU_VX_M1_MASK\0" + /* 155876 */ "PseudoVMAXU_VX_M1_MASK\0" + /* 155899 */ "PseudoVDIV_VX_M1_MASK\0" + /* 155921 */ "PseudoVMAX_VX_M1_MASK\0" + /* 155943 */ "PseudoVNSRA_WX_M1_MASK\0" + /* 155966 */ "PseudoVWSUB_WX_M1_MASK\0" + /* 155989 */ "PseudoVWADD_WX_M1_MASK\0" + /* 156012 */ "PseudoVNSRL_WX_M1_MASK\0" + /* 156035 */ "PseudoVNCLIP_WX_M1_MASK\0" + /* 156059 */ "PseudoVWSUBU_WX_M1_MASK\0" + /* 156083 */ "PseudoVWADDU_WX_M1_MASK\0" + /* 156107 */ "PseudoVNCLIPU_WX_M1_MASK\0" + /* 156132 */ "PseudoVMSBF_M_B32_MASK\0" + /* 156155 */ "PseudoVMSIF_M_B32_MASK\0" + /* 156178 */ "PseudoVMSOF_M_B32_MASK\0" + /* 156201 */ "PseudoVCPOP_M_B32_MASK\0" + /* 156224 */ "PseudoVFIRST_M_B32_MASK\0" + /* 156248 */ "PseudoVMSBF_M_B2_MASK\0" + /* 156270 */ "PseudoVMSIF_M_B2_MASK\0" + /* 156292 */ "PseudoVMSOF_M_B2_MASK\0" + /* 156314 */ "PseudoVCPOP_M_B2_MASK\0" + /* 156336 */ "PseudoVFIRST_M_B2_MASK\0" + /* 156359 */ "PseudoVAMOADDEI32_WD_M1_MF2_MASK\0" + /* 156392 */ "PseudoVAMOANDEI32_WD_M1_MF2_MASK\0" + /* 156425 */ "PseudoVAMOMINEI32_WD_M1_MF2_MASK\0" + /* 156458 */ "PseudoVAMOSWAPEI32_WD_M1_MF2_MASK\0" + /* 156492 */ "PseudoVAMOOREI32_WD_M1_MF2_MASK\0" + /* 156524 */ "PseudoVAMOXOREI32_WD_M1_MF2_MASK\0" + /* 156557 */ "PseudoVAMOMINUEI32_WD_M1_MF2_MASK\0" + /* 156591 */ "PseudoVAMOMAXUEI32_WD_M1_MF2_MASK\0" + /* 156625 */ "PseudoVAMOMAXEI32_WD_M1_MF2_MASK\0" + /* 156658 */ "PseudoVAMOADDEI16_WD_M1_MF2_MASK\0" + /* 156691 */ "PseudoVAMOANDEI16_WD_M1_MF2_MASK\0" + /* 156724 */ "PseudoVAMOMINEI16_WD_M1_MF2_MASK\0" + /* 156757 */ "PseudoVAMOSWAPEI16_WD_M1_MF2_MASK\0" + /* 156791 */ "PseudoVAMOOREI16_WD_M1_MF2_MASK\0" + /* 156823 */ "PseudoVAMOXOREI16_WD_M1_MF2_MASK\0" + /* 156856 */ "PseudoVAMOMINUEI16_WD_M1_MF2_MASK\0" + /* 156890 */ "PseudoVAMOMAXUEI16_WD_M1_MF2_MASK\0" + /* 156924 */ "PseudoVAMOMAXEI16_WD_M1_MF2_MASK\0" + /* 156957 */ "PseudoVRGATHEREI16_VV_M1_MF2_MASK\0" + /* 156991 */ "PseudoVLOXSEG2EI32_V_M1_MF2_MASK\0" + /* 157024 */ "PseudoVSOXSEG2EI32_V_M1_MF2_MASK\0" + /* 157057 */ "PseudoVLUXSEG2EI32_V_M1_MF2_MASK\0" + /* 157090 */ "PseudoVSUXSEG2EI32_V_M1_MF2_MASK\0" + /* 157123 */ "PseudoVLOXSEG3EI32_V_M1_MF2_MASK\0" + /* 157156 */ "PseudoVSOXSEG3EI32_V_M1_MF2_MASK\0" + /* 157189 */ "PseudoVLUXSEG3EI32_V_M1_MF2_MASK\0" + /* 157222 */ "PseudoVSUXSEG3EI32_V_M1_MF2_MASK\0" + /* 157255 */ "PseudoVLOXSEG4EI32_V_M1_MF2_MASK\0" + /* 157288 */ "PseudoVSOXSEG4EI32_V_M1_MF2_MASK\0" + /* 157321 */ "PseudoVLUXSEG4EI32_V_M1_MF2_MASK\0" + /* 157354 */ "PseudoVSUXSEG4EI32_V_M1_MF2_MASK\0" + /* 157387 */ "PseudoVLOXSEG5EI32_V_M1_MF2_MASK\0" + /* 157420 */ "PseudoVSOXSEG5EI32_V_M1_MF2_MASK\0" + /* 157453 */ "PseudoVLUXSEG5EI32_V_M1_MF2_MASK\0" + /* 157486 */ "PseudoVSUXSEG5EI32_V_M1_MF2_MASK\0" + /* 157519 */ "PseudoVLOXSEG6EI32_V_M1_MF2_MASK\0" + /* 157552 */ "PseudoVSOXSEG6EI32_V_M1_MF2_MASK\0" + /* 157585 */ "PseudoVLUXSEG6EI32_V_M1_MF2_MASK\0" + /* 157618 */ "PseudoVSUXSEG6EI32_V_M1_MF2_MASK\0" + /* 157651 */ "PseudoVLOXSEG7EI32_V_M1_MF2_MASK\0" + /* 157684 */ "PseudoVSOXSEG7EI32_V_M1_MF2_MASK\0" + /* 157717 */ "PseudoVLUXSEG7EI32_V_M1_MF2_MASK\0" + /* 157750 */ "PseudoVSUXSEG7EI32_V_M1_MF2_MASK\0" + /* 157783 */ "PseudoVLOXSEG8EI32_V_M1_MF2_MASK\0" + /* 157816 */ "PseudoVSOXSEG8EI32_V_M1_MF2_MASK\0" + /* 157849 */ "PseudoVLUXSEG8EI32_V_M1_MF2_MASK\0" + /* 157882 */ "PseudoVSUXSEG8EI32_V_M1_MF2_MASK\0" + /* 157915 */ "PseudoVLOXEI32_V_M1_MF2_MASK\0" + /* 157944 */ "PseudoVSOXEI32_V_M1_MF2_MASK\0" + /* 157973 */ "PseudoVLUXEI32_V_M1_MF2_MASK\0" + /* 158002 */ "PseudoVSUXEI32_V_M1_MF2_MASK\0" + /* 158031 */ "PseudoVLOXSEG2EI64_V_M1_MF2_MASK\0" + /* 158064 */ "PseudoVSOXSEG2EI64_V_M1_MF2_MASK\0" + /* 158097 */ "PseudoVLUXSEG2EI64_V_M1_MF2_MASK\0" + /* 158130 */ "PseudoVSUXSEG2EI64_V_M1_MF2_MASK\0" + /* 158163 */ "PseudoVLOXSEG3EI64_V_M1_MF2_MASK\0" + /* 158196 */ "PseudoVSOXSEG3EI64_V_M1_MF2_MASK\0" + /* 158229 */ "PseudoVLUXSEG3EI64_V_M1_MF2_MASK\0" + /* 158262 */ "PseudoVSUXSEG3EI64_V_M1_MF2_MASK\0" + /* 158295 */ "PseudoVLOXSEG4EI64_V_M1_MF2_MASK\0" + /* 158328 */ "PseudoVSOXSEG4EI64_V_M1_MF2_MASK\0" + /* 158361 */ "PseudoVLUXSEG4EI64_V_M1_MF2_MASK\0" + /* 158394 */ "PseudoVSUXSEG4EI64_V_M1_MF2_MASK\0" + /* 158427 */ "PseudoVLOXSEG5EI64_V_M1_MF2_MASK\0" + /* 158460 */ "PseudoVSOXSEG5EI64_V_M1_MF2_MASK\0" + /* 158493 */ "PseudoVLUXSEG5EI64_V_M1_MF2_MASK\0" + /* 158526 */ "PseudoVSUXSEG5EI64_V_M1_MF2_MASK\0" + /* 158559 */ "PseudoVLOXSEG6EI64_V_M1_MF2_MASK\0" + /* 158592 */ "PseudoVSOXSEG6EI64_V_M1_MF2_MASK\0" + /* 158625 */ "PseudoVLUXSEG6EI64_V_M1_MF2_MASK\0" + /* 158658 */ "PseudoVSUXSEG6EI64_V_M1_MF2_MASK\0" + /* 158691 */ "PseudoVLOXSEG7EI64_V_M1_MF2_MASK\0" + /* 158724 */ "PseudoVSOXSEG7EI64_V_M1_MF2_MASK\0" + /* 158757 */ "PseudoVLUXSEG7EI64_V_M1_MF2_MASK\0" + /* 158790 */ "PseudoVSUXSEG7EI64_V_M1_MF2_MASK\0" + /* 158823 */ "PseudoVLOXSEG8EI64_V_M1_MF2_MASK\0" + /* 158856 */ "PseudoVSOXSEG8EI64_V_M1_MF2_MASK\0" + /* 158889 */ "PseudoVLUXSEG8EI64_V_M1_MF2_MASK\0" + /* 158922 */ "PseudoVSUXSEG8EI64_V_M1_MF2_MASK\0" + /* 158955 */ "PseudoVLOXEI64_V_M1_MF2_MASK\0" + /* 158984 */ "PseudoVSOXEI64_V_M1_MF2_MASK\0" + /* 159013 */ "PseudoVLUXEI64_V_M1_MF2_MASK\0" + /* 159042 */ "PseudoVSUXEI64_V_M1_MF2_MASK\0" + /* 159071 */ "PseudoVLOXSEG2EI16_V_M1_MF2_MASK\0" + /* 159104 */ "PseudoVSOXSEG2EI16_V_M1_MF2_MASK\0" + /* 159137 */ "PseudoVLUXSEG2EI16_V_M1_MF2_MASK\0" + /* 159170 */ "PseudoVSUXSEG2EI16_V_M1_MF2_MASK\0" + /* 159203 */ "PseudoVLOXSEG3EI16_V_M1_MF2_MASK\0" + /* 159236 */ "PseudoVSOXSEG3EI16_V_M1_MF2_MASK\0" + /* 159269 */ "PseudoVLUXSEG3EI16_V_M1_MF2_MASK\0" + /* 159302 */ "PseudoVSUXSEG3EI16_V_M1_MF2_MASK\0" + /* 159335 */ "PseudoVLOXSEG4EI16_V_M1_MF2_MASK\0" + /* 159368 */ "PseudoVSOXSEG4EI16_V_M1_MF2_MASK\0" + /* 159401 */ "PseudoVLUXSEG4EI16_V_M1_MF2_MASK\0" + /* 159434 */ "PseudoVSUXSEG4EI16_V_M1_MF2_MASK\0" + /* 159467 */ "PseudoVLOXSEG5EI16_V_M1_MF2_MASK\0" + /* 159500 */ "PseudoVSOXSEG5EI16_V_M1_MF2_MASK\0" + /* 159533 */ "PseudoVLUXSEG5EI16_V_M1_MF2_MASK\0" + /* 159566 */ "PseudoVSUXSEG5EI16_V_M1_MF2_MASK\0" + /* 159599 */ "PseudoVLOXSEG6EI16_V_M1_MF2_MASK\0" + /* 159632 */ "PseudoVSOXSEG6EI16_V_M1_MF2_MASK\0" + /* 159665 */ "PseudoVLUXSEG6EI16_V_M1_MF2_MASK\0" + /* 159698 */ "PseudoVSUXSEG6EI16_V_M1_MF2_MASK\0" + /* 159731 */ "PseudoVLOXSEG7EI16_V_M1_MF2_MASK\0" + /* 159764 */ "PseudoVSOXSEG7EI16_V_M1_MF2_MASK\0" + /* 159797 */ "PseudoVLUXSEG7EI16_V_M1_MF2_MASK\0" + /* 159830 */ "PseudoVSUXSEG7EI16_V_M1_MF2_MASK\0" + /* 159863 */ "PseudoVLOXSEG8EI16_V_M1_MF2_MASK\0" + /* 159896 */ "PseudoVSOXSEG8EI16_V_M1_MF2_MASK\0" + /* 159929 */ "PseudoVLUXSEG8EI16_V_M1_MF2_MASK\0" + /* 159962 */ "PseudoVSUXSEG8EI16_V_M1_MF2_MASK\0" + /* 159995 */ "PseudoVLOXEI16_V_M1_MF2_MASK\0" + /* 160024 */ "PseudoVSOXEI16_V_M1_MF2_MASK\0" + /* 160053 */ "PseudoVLUXEI16_V_M1_MF2_MASK\0" + /* 160082 */ "PseudoVSUXEI16_V_M1_MF2_MASK\0" + /* 160111 */ "PseudoVFSUB_VF32_MF2_MASK\0" + /* 160137 */ "PseudoVFMSUB_VF32_MF2_MASK\0" + /* 160164 */ "PseudoVFNMSUB_VF32_MF2_MASK\0" + /* 160192 */ "PseudoVFRSUB_VF32_MF2_MASK\0" + /* 160219 */ "PseudoVFWSUB_VF32_MF2_MASK\0" + /* 160246 */ "PseudoVFMSAC_VF32_MF2_MASK\0" + /* 160273 */ "PseudoVFNMSAC_VF32_MF2_MASK\0" + /* 160301 */ "PseudoVFWNMSAC_VF32_MF2_MASK\0" + /* 160330 */ "PseudoVFWMSAC_VF32_MF2_MASK\0" + /* 160358 */ "PseudoVFMACC_VF32_MF2_MASK\0" + /* 160385 */ "PseudoVFNMACC_VF32_MF2_MASK\0" + /* 160413 */ "PseudoVFWNMACC_VF32_MF2_MASK\0" + /* 160442 */ "PseudoVFWMACC_VF32_MF2_MASK\0" + /* 160470 */ "PseudoVFADD_VF32_MF2_MASK\0" + /* 160496 */ "PseudoVFMADD_VF32_MF2_MASK\0" + /* 160523 */ "PseudoVFNMADD_VF32_MF2_MASK\0" + /* 160551 */ "PseudoVFWADD_VF32_MF2_MASK\0" + /* 160578 */ "PseudoVMFGE_VF32_MF2_MASK\0" + /* 160604 */ "PseudoVMFLE_VF32_MF2_MASK\0" + /* 160630 */ "PseudoVMFNE_VF32_MF2_MASK\0" + /* 160656 */ "PseudoVFSGNJ_VF32_MF2_MASK\0" + /* 160683 */ "PseudoVFMUL_VF32_MF2_MASK\0" + /* 160709 */ "PseudoVFWMUL_VF32_MF2_MASK\0" + /* 160736 */ "PseudoVFMIN_VF32_MF2_MASK\0" + /* 160762 */ "PseudoVFSGNJN_VF32_MF2_MASK\0" + /* 160790 */ "PseudoVFSLIDE1DOWN_VF32_MF2_MASK\0" + /* 160823 */ "PseudoVFSLIDE1UP_VF32_MF2_MASK\0" + /* 160854 */ "PseudoVMFEQ_VF32_MF2_MASK\0" + /* 160880 */ "PseudoVMFGT_VF32_MF2_MASK\0" + /* 160906 */ "PseudoVMFLT_VF32_MF2_MASK\0" + /* 160932 */ "PseudoVFDIV_VF32_MF2_MASK\0" + /* 160958 */ "PseudoVFRDIV_VF32_MF2_MASK\0" + /* 160985 */ "PseudoVFMAX_VF32_MF2_MASK\0" + /* 161011 */ "PseudoVFSGNJX_VF32_MF2_MASK\0" + /* 161039 */ "PseudoVFWSUB_WF32_MF2_MASK\0" + /* 161066 */ "PseudoVFWADD_WF32_MF2_MASK\0" + /* 161093 */ "PseudoVAMOADDEI32_WD_MF2_MF2_MASK\0" + /* 161127 */ "PseudoVAMOANDEI32_WD_MF2_MF2_MASK\0" + /* 161161 */ "PseudoVAMOMINEI32_WD_MF2_MF2_MASK\0" + /* 161195 */ "PseudoVAMOSWAPEI32_WD_MF2_MF2_MASK\0" + /* 161230 */ "PseudoVAMOOREI32_WD_MF2_MF2_MASK\0" + /* 161263 */ "PseudoVAMOXOREI32_WD_MF2_MF2_MASK\0" + /* 161297 */ "PseudoVAMOMINUEI32_WD_MF2_MF2_MASK\0" + /* 161332 */ "PseudoVAMOMAXUEI32_WD_MF2_MF2_MASK\0" + /* 161367 */ "PseudoVAMOMAXEI32_WD_MF2_MF2_MASK\0" + /* 161401 */ "PseudoVRGATHEREI16_VV_MF2_MF2_MASK\0" + /* 161436 */ "PseudoVLOXSEG2EI32_V_MF2_MF2_MASK\0" + /* 161470 */ "PseudoVSOXSEG2EI32_V_MF2_MF2_MASK\0" + /* 161504 */ "PseudoVLUXSEG2EI32_V_MF2_MF2_MASK\0" + /* 161538 */ "PseudoVSUXSEG2EI32_V_MF2_MF2_MASK\0" + /* 161572 */ "PseudoVLOXSEG3EI32_V_MF2_MF2_MASK\0" + /* 161606 */ "PseudoVSOXSEG3EI32_V_MF2_MF2_MASK\0" + /* 161640 */ "PseudoVLUXSEG3EI32_V_MF2_MF2_MASK\0" + /* 161674 */ "PseudoVSUXSEG3EI32_V_MF2_MF2_MASK\0" + /* 161708 */ "PseudoVLOXSEG4EI32_V_MF2_MF2_MASK\0" + /* 161742 */ "PseudoVSOXSEG4EI32_V_MF2_MF2_MASK\0" + /* 161776 */ "PseudoVLUXSEG4EI32_V_MF2_MF2_MASK\0" + /* 161810 */ "PseudoVSUXSEG4EI32_V_MF2_MF2_MASK\0" + /* 161844 */ "PseudoVLOXSEG5EI32_V_MF2_MF2_MASK\0" + /* 161878 */ "PseudoVSOXSEG5EI32_V_MF2_MF2_MASK\0" + /* 161912 */ "PseudoVLUXSEG5EI32_V_MF2_MF2_MASK\0" + /* 161946 */ "PseudoVSUXSEG5EI32_V_MF2_MF2_MASK\0" + /* 161980 */ "PseudoVLOXSEG6EI32_V_MF2_MF2_MASK\0" + /* 162014 */ "PseudoVSOXSEG6EI32_V_MF2_MF2_MASK\0" + /* 162048 */ "PseudoVLUXSEG6EI32_V_MF2_MF2_MASK\0" + /* 162082 */ "PseudoVSUXSEG6EI32_V_MF2_MF2_MASK\0" + /* 162116 */ "PseudoVLOXSEG7EI32_V_MF2_MF2_MASK\0" + /* 162150 */ "PseudoVSOXSEG7EI32_V_MF2_MF2_MASK\0" + /* 162184 */ "PseudoVLUXSEG7EI32_V_MF2_MF2_MASK\0" + /* 162218 */ "PseudoVSUXSEG7EI32_V_MF2_MF2_MASK\0" + /* 162252 */ "PseudoVLOXSEG8EI32_V_MF2_MF2_MASK\0" + /* 162286 */ "PseudoVSOXSEG8EI32_V_MF2_MF2_MASK\0" + /* 162320 */ "PseudoVLUXSEG8EI32_V_MF2_MF2_MASK\0" + /* 162354 */ "PseudoVSUXSEG8EI32_V_MF2_MF2_MASK\0" + /* 162388 */ "PseudoVLOXEI32_V_MF2_MF2_MASK\0" + /* 162418 */ "PseudoVSOXEI32_V_MF2_MF2_MASK\0" + /* 162448 */ "PseudoVLUXEI32_V_MF2_MF2_MASK\0" + /* 162478 */ "PseudoVSUXEI32_V_MF2_MF2_MASK\0" + /* 162508 */ "PseudoVLOXSEG2EI16_V_MF2_MF2_MASK\0" + /* 162542 */ "PseudoVSOXSEG2EI16_V_MF2_MF2_MASK\0" + /* 162576 */ "PseudoVLUXSEG2EI16_V_MF2_MF2_MASK\0" + /* 162610 */ "PseudoVSUXSEG2EI16_V_MF2_MF2_MASK\0" + /* 162644 */ "PseudoVLOXSEG3EI16_V_MF2_MF2_MASK\0" + /* 162678 */ "PseudoVSOXSEG3EI16_V_MF2_MF2_MASK\0" + /* 162712 */ "PseudoVLUXSEG3EI16_V_MF2_MF2_MASK\0" + /* 162746 */ "PseudoVSUXSEG3EI16_V_MF2_MF2_MASK\0" + /* 162780 */ "PseudoVLOXSEG4EI16_V_MF2_MF2_MASK\0" + /* 162814 */ "PseudoVSOXSEG4EI16_V_MF2_MF2_MASK\0" + /* 162848 */ "PseudoVLUXSEG4EI16_V_MF2_MF2_MASK\0" + /* 162882 */ "PseudoVSUXSEG4EI16_V_MF2_MF2_MASK\0" + /* 162916 */ "PseudoVLOXSEG5EI16_V_MF2_MF2_MASK\0" + /* 162950 */ "PseudoVSOXSEG5EI16_V_MF2_MF2_MASK\0" + /* 162984 */ "PseudoVLUXSEG5EI16_V_MF2_MF2_MASK\0" + /* 163018 */ "PseudoVSUXSEG5EI16_V_MF2_MF2_MASK\0" + /* 163052 */ "PseudoVLOXSEG6EI16_V_MF2_MF2_MASK\0" + /* 163086 */ "PseudoVSOXSEG6EI16_V_MF2_MF2_MASK\0" + /* 163120 */ "PseudoVLUXSEG6EI16_V_MF2_MF2_MASK\0" + /* 163154 */ "PseudoVSUXSEG6EI16_V_MF2_MF2_MASK\0" + /* 163188 */ "PseudoVLOXSEG7EI16_V_MF2_MF2_MASK\0" + /* 163222 */ "PseudoVSOXSEG7EI16_V_MF2_MF2_MASK\0" + /* 163256 */ "PseudoVLUXSEG7EI16_V_MF2_MF2_MASK\0" + /* 163290 */ "PseudoVSUXSEG7EI16_V_MF2_MF2_MASK\0" + /* 163324 */ "PseudoVLOXSEG8EI16_V_MF2_MF2_MASK\0" + /* 163358 */ "PseudoVSOXSEG8EI16_V_MF2_MF2_MASK\0" + /* 163392 */ "PseudoVLUXSEG8EI16_V_MF2_MF2_MASK\0" + /* 163426 */ "PseudoVSUXSEG8EI16_V_MF2_MF2_MASK\0" + /* 163460 */ "PseudoVLOXEI16_V_MF2_MF2_MASK\0" + /* 163490 */ "PseudoVSOXEI16_V_MF2_MF2_MASK\0" + /* 163520 */ "PseudoVLUXEI16_V_MF2_MF2_MASK\0" + /* 163550 */ "PseudoVSUXEI16_V_MF2_MF2_MASK\0" + /* 163580 */ "PseudoVLOXSEG2EI8_V_MF2_MF2_MASK\0" + /* 163613 */ "PseudoVSOXSEG2EI8_V_MF2_MF2_MASK\0" + /* 163646 */ "PseudoVLUXSEG2EI8_V_MF2_MF2_MASK\0" + /* 163679 */ "PseudoVSUXSEG2EI8_V_MF2_MF2_MASK\0" + /* 163712 */ "PseudoVLOXSEG3EI8_V_MF2_MF2_MASK\0" + /* 163745 */ "PseudoVSOXSEG3EI8_V_MF2_MF2_MASK\0" + /* 163778 */ "PseudoVLUXSEG3EI8_V_MF2_MF2_MASK\0" + /* 163811 */ "PseudoVSUXSEG3EI8_V_MF2_MF2_MASK\0" + /* 163844 */ "PseudoVLOXSEG4EI8_V_MF2_MF2_MASK\0" + /* 163877 */ "PseudoVSOXSEG4EI8_V_MF2_MF2_MASK\0" + /* 163910 */ "PseudoVLUXSEG4EI8_V_MF2_MF2_MASK\0" + /* 163943 */ "PseudoVSUXSEG4EI8_V_MF2_MF2_MASK\0" + /* 163976 */ "PseudoVLOXSEG5EI8_V_MF2_MF2_MASK\0" + /* 164009 */ "PseudoVSOXSEG5EI8_V_MF2_MF2_MASK\0" + /* 164042 */ "PseudoVLUXSEG5EI8_V_MF2_MF2_MASK\0" + /* 164075 */ "PseudoVSUXSEG5EI8_V_MF2_MF2_MASK\0" + /* 164108 */ "PseudoVLOXSEG6EI8_V_MF2_MF2_MASK\0" + /* 164141 */ "PseudoVSOXSEG6EI8_V_MF2_MF2_MASK\0" + /* 164174 */ "PseudoVLUXSEG6EI8_V_MF2_MF2_MASK\0" + /* 164207 */ "PseudoVSUXSEG6EI8_V_MF2_MF2_MASK\0" + /* 164240 */ "PseudoVLOXSEG7EI8_V_MF2_MF2_MASK\0" + /* 164273 */ "PseudoVSOXSEG7EI8_V_MF2_MF2_MASK\0" + /* 164306 */ "PseudoVLUXSEG7EI8_V_MF2_MF2_MASK\0" + /* 164339 */ "PseudoVSUXSEG7EI8_V_MF2_MF2_MASK\0" + /* 164372 */ "PseudoVLOXSEG8EI8_V_MF2_MF2_MASK\0" + /* 164405 */ "PseudoVSOXSEG8EI8_V_MF2_MF2_MASK\0" + /* 164438 */ "PseudoVLUXSEG8EI8_V_MF2_MF2_MASK\0" + /* 164471 */ "PseudoVSUXSEG8EI8_V_MF2_MF2_MASK\0" + /* 164504 */ "PseudoVLOXEI8_V_MF2_MF2_MASK\0" + /* 164533 */ "PseudoVSOXEI8_V_MF2_MF2_MASK\0" + /* 164562 */ "PseudoVLUXEI8_V_MF2_MF2_MASK\0" + /* 164591 */ "PseudoVSUXEI8_V_MF2_MF2_MASK\0" + /* 164620 */ "PseudoVSEXT_VF2_MF2_MASK\0" + /* 164645 */ "PseudoVZEXT_VF2_MF2_MASK\0" + /* 164670 */ "PseudoVAMOADDEI16_WD_M2_MF2_MASK\0" + /* 164703 */ "PseudoVAMOANDEI16_WD_M2_MF2_MASK\0" + /* 164736 */ "PseudoVAMOMINEI16_WD_M2_MF2_MASK\0" + /* 164769 */ "PseudoVAMOSWAPEI16_WD_M2_MF2_MASK\0" + /* 164803 */ "PseudoVAMOOREI16_WD_M2_MF2_MASK\0" + /* 164835 */ "PseudoVAMOXOREI16_WD_M2_MF2_MASK\0" + /* 164868 */ "PseudoVAMOMINUEI16_WD_M2_MF2_MASK\0" + /* 164902 */ "PseudoVAMOMAXUEI16_WD_M2_MF2_MASK\0" + /* 164936 */ "PseudoVAMOMAXEI16_WD_M2_MF2_MASK\0" + /* 164969 */ "PseudoVAMOADDEI8_WD_M2_MF2_MASK\0" + /* 165001 */ "PseudoVAMOANDEI8_WD_M2_MF2_MASK\0" + /* 165033 */ "PseudoVAMOMINEI8_WD_M2_MF2_MASK\0" + /* 165065 */ "PseudoVAMOSWAPEI8_WD_M2_MF2_MASK\0" + /* 165098 */ "PseudoVAMOOREI8_WD_M2_MF2_MASK\0" + /* 165129 */ "PseudoVAMOXOREI8_WD_M2_MF2_MASK\0" + /* 165161 */ "PseudoVAMOMINUEI8_WD_M2_MF2_MASK\0" + /* 165194 */ "PseudoVAMOMAXUEI8_WD_M2_MF2_MASK\0" + /* 165227 */ "PseudoVAMOMAXEI8_WD_M2_MF2_MASK\0" + /* 165259 */ "PseudoVRGATHEREI16_VV_M2_MF2_MASK\0" + /* 165293 */ "PseudoVLOXSEG2EI32_V_M2_MF2_MASK\0" + /* 165326 */ "PseudoVSOXSEG2EI32_V_M2_MF2_MASK\0" + /* 165359 */ "PseudoVLUXSEG2EI32_V_M2_MF2_MASK\0" + /* 165392 */ "PseudoVSUXSEG2EI32_V_M2_MF2_MASK\0" + /* 165425 */ "PseudoVLOXSEG3EI32_V_M2_MF2_MASK\0" + /* 165458 */ "PseudoVSOXSEG3EI32_V_M2_MF2_MASK\0" + /* 165491 */ "PseudoVLUXSEG3EI32_V_M2_MF2_MASK\0" + /* 165524 */ "PseudoVSUXSEG3EI32_V_M2_MF2_MASK\0" + /* 165557 */ "PseudoVLOXSEG4EI32_V_M2_MF2_MASK\0" + /* 165590 */ "PseudoVSOXSEG4EI32_V_M2_MF2_MASK\0" + /* 165623 */ "PseudoVLUXSEG4EI32_V_M2_MF2_MASK\0" + /* 165656 */ "PseudoVSUXSEG4EI32_V_M2_MF2_MASK\0" + /* 165689 */ "PseudoVLOXSEG5EI32_V_M2_MF2_MASK\0" + /* 165722 */ "PseudoVSOXSEG5EI32_V_M2_MF2_MASK\0" + /* 165755 */ "PseudoVLUXSEG5EI32_V_M2_MF2_MASK\0" + /* 165788 */ "PseudoVSUXSEG5EI32_V_M2_MF2_MASK\0" + /* 165821 */ "PseudoVLOXSEG6EI32_V_M2_MF2_MASK\0" + /* 165854 */ "PseudoVSOXSEG6EI32_V_M2_MF2_MASK\0" + /* 165887 */ "PseudoVLUXSEG6EI32_V_M2_MF2_MASK\0" + /* 165920 */ "PseudoVSUXSEG6EI32_V_M2_MF2_MASK\0" + /* 165953 */ "PseudoVLOXSEG7EI32_V_M2_MF2_MASK\0" + /* 165986 */ "PseudoVSOXSEG7EI32_V_M2_MF2_MASK\0" + /* 166019 */ "PseudoVLUXSEG7EI32_V_M2_MF2_MASK\0" + /* 166052 */ "PseudoVSUXSEG7EI32_V_M2_MF2_MASK\0" + /* 166085 */ "PseudoVLOXSEG8EI32_V_M2_MF2_MASK\0" + /* 166118 */ "PseudoVSOXSEG8EI32_V_M2_MF2_MASK\0" + /* 166151 */ "PseudoVLUXSEG8EI32_V_M2_MF2_MASK\0" + /* 166184 */ "PseudoVSUXSEG8EI32_V_M2_MF2_MASK\0" + /* 166217 */ "PseudoVLOXEI32_V_M2_MF2_MASK\0" + /* 166246 */ "PseudoVSOXEI32_V_M2_MF2_MASK\0" + /* 166275 */ "PseudoVLUXEI32_V_M2_MF2_MASK\0" + /* 166304 */ "PseudoVSUXEI32_V_M2_MF2_MASK\0" + /* 166333 */ "PseudoVLOXSEG2EI64_V_M2_MF2_MASK\0" + /* 166366 */ "PseudoVSOXSEG2EI64_V_M2_MF2_MASK\0" + /* 166399 */ "PseudoVLUXSEG2EI64_V_M2_MF2_MASK\0" + /* 166432 */ "PseudoVSUXSEG2EI64_V_M2_MF2_MASK\0" + /* 166465 */ "PseudoVLOXSEG3EI64_V_M2_MF2_MASK\0" + /* 166498 */ "PseudoVSOXSEG3EI64_V_M2_MF2_MASK\0" + /* 166531 */ "PseudoVLUXSEG3EI64_V_M2_MF2_MASK\0" + /* 166564 */ "PseudoVSUXSEG3EI64_V_M2_MF2_MASK\0" + /* 166597 */ "PseudoVLOXSEG4EI64_V_M2_MF2_MASK\0" + /* 166630 */ "PseudoVSOXSEG4EI64_V_M2_MF2_MASK\0" + /* 166663 */ "PseudoVLUXSEG4EI64_V_M2_MF2_MASK\0" + /* 166696 */ "PseudoVSUXSEG4EI64_V_M2_MF2_MASK\0" + /* 166729 */ "PseudoVLOXSEG5EI64_V_M2_MF2_MASK\0" + /* 166762 */ "PseudoVSOXSEG5EI64_V_M2_MF2_MASK\0" + /* 166795 */ "PseudoVLUXSEG5EI64_V_M2_MF2_MASK\0" + /* 166828 */ "PseudoVSUXSEG5EI64_V_M2_MF2_MASK\0" + /* 166861 */ "PseudoVLOXSEG6EI64_V_M2_MF2_MASK\0" + /* 166894 */ "PseudoVSOXSEG6EI64_V_M2_MF2_MASK\0" + /* 166927 */ "PseudoVLUXSEG6EI64_V_M2_MF2_MASK\0" + /* 166960 */ "PseudoVSUXSEG6EI64_V_M2_MF2_MASK\0" + /* 166993 */ "PseudoVLOXSEG7EI64_V_M2_MF2_MASK\0" + /* 167026 */ "PseudoVSOXSEG7EI64_V_M2_MF2_MASK\0" + /* 167059 */ "PseudoVLUXSEG7EI64_V_M2_MF2_MASK\0" + /* 167092 */ "PseudoVSUXSEG7EI64_V_M2_MF2_MASK\0" + /* 167125 */ "PseudoVLOXSEG8EI64_V_M2_MF2_MASK\0" + /* 167158 */ "PseudoVSOXSEG8EI64_V_M2_MF2_MASK\0" + /* 167191 */ "PseudoVLUXSEG8EI64_V_M2_MF2_MASK\0" + /* 167224 */ "PseudoVSUXSEG8EI64_V_M2_MF2_MASK\0" + /* 167257 */ "PseudoVLOXEI64_V_M2_MF2_MASK\0" + /* 167286 */ "PseudoVSOXEI64_V_M2_MF2_MASK\0" + /* 167315 */ "PseudoVLUXEI64_V_M2_MF2_MASK\0" + /* 167344 */ "PseudoVSUXEI64_V_M2_MF2_MASK\0" + /* 167373 */ "PseudoVFSUB_VF64_MF2_MASK\0" + /* 167399 */ "PseudoVFMSUB_VF64_MF2_MASK\0" + /* 167426 */ "PseudoVFNMSUB_VF64_MF2_MASK\0" + /* 167454 */ "PseudoVFRSUB_VF64_MF2_MASK\0" + /* 167481 */ "PseudoVFMSAC_VF64_MF2_MASK\0" + /* 167508 */ "PseudoVFNMSAC_VF64_MF2_MASK\0" + /* 167536 */ "PseudoVFMACC_VF64_MF2_MASK\0" + /* 167563 */ "PseudoVFNMACC_VF64_MF2_MASK\0" + /* 167591 */ "PseudoVFADD_VF64_MF2_MASK\0" + /* 167617 */ "PseudoVFMADD_VF64_MF2_MASK\0" + /* 167644 */ "PseudoVFNMADD_VF64_MF2_MASK\0" + /* 167672 */ "PseudoVMFGE_VF64_MF2_MASK\0" + /* 167698 */ "PseudoVMFLE_VF64_MF2_MASK\0" + /* 167724 */ "PseudoVMFNE_VF64_MF2_MASK\0" + /* 167750 */ "PseudoVFSGNJ_VF64_MF2_MASK\0" + /* 167777 */ "PseudoVFMUL_VF64_MF2_MASK\0" + /* 167803 */ "PseudoVFMIN_VF64_MF2_MASK\0" + /* 167829 */ "PseudoVFSGNJN_VF64_MF2_MASK\0" + /* 167857 */ "PseudoVFSLIDE1DOWN_VF64_MF2_MASK\0" + /* 167890 */ "PseudoVFSLIDE1UP_VF64_MF2_MASK\0" + /* 167921 */ "PseudoVMFEQ_VF64_MF2_MASK\0" + /* 167947 */ "PseudoVMFGT_VF64_MF2_MASK\0" + /* 167973 */ "PseudoVMFLT_VF64_MF2_MASK\0" + /* 167999 */ "PseudoVFDIV_VF64_MF2_MASK\0" + /* 168025 */ "PseudoVFRDIV_VF64_MF2_MASK\0" + /* 168052 */ "PseudoVFMAX_VF64_MF2_MASK\0" + /* 168078 */ "PseudoVFSGNJX_VF64_MF2_MASK\0" + /* 168106 */ "PseudoVRGATHEREI16_VV_MF4_MF2_MASK\0" + /* 168141 */ "PseudoVLOXSEG2EI16_V_MF4_MF2_MASK\0" + /* 168175 */ "PseudoVSOXSEG2EI16_V_MF4_MF2_MASK\0" + /* 168209 */ "PseudoVLUXSEG2EI16_V_MF4_MF2_MASK\0" + /* 168243 */ "PseudoVSUXSEG2EI16_V_MF4_MF2_MASK\0" + /* 168277 */ "PseudoVLOXSEG3EI16_V_MF4_MF2_MASK\0" + /* 168311 */ "PseudoVSOXSEG3EI16_V_MF4_MF2_MASK\0" + /* 168345 */ "PseudoVLUXSEG3EI16_V_MF4_MF2_MASK\0" + /* 168379 */ "PseudoVSUXSEG3EI16_V_MF4_MF2_MASK\0" + /* 168413 */ "PseudoVLOXSEG4EI16_V_MF4_MF2_MASK\0" + /* 168447 */ "PseudoVSOXSEG4EI16_V_MF4_MF2_MASK\0" + /* 168481 */ "PseudoVLUXSEG4EI16_V_MF4_MF2_MASK\0" + /* 168515 */ "PseudoVSUXSEG4EI16_V_MF4_MF2_MASK\0" + /* 168549 */ "PseudoVLOXSEG5EI16_V_MF4_MF2_MASK\0" + /* 168583 */ "PseudoVSOXSEG5EI16_V_MF4_MF2_MASK\0" + /* 168617 */ "PseudoVLUXSEG5EI16_V_MF4_MF2_MASK\0" + /* 168651 */ "PseudoVSUXSEG5EI16_V_MF4_MF2_MASK\0" + /* 168685 */ "PseudoVLOXSEG6EI16_V_MF4_MF2_MASK\0" + /* 168719 */ "PseudoVSOXSEG6EI16_V_MF4_MF2_MASK\0" + /* 168753 */ "PseudoVLUXSEG6EI16_V_MF4_MF2_MASK\0" + /* 168787 */ "PseudoVSUXSEG6EI16_V_MF4_MF2_MASK\0" + /* 168821 */ "PseudoVLOXSEG7EI16_V_MF4_MF2_MASK\0" + /* 168855 */ "PseudoVSOXSEG7EI16_V_MF4_MF2_MASK\0" + /* 168889 */ "PseudoVLUXSEG7EI16_V_MF4_MF2_MASK\0" + /* 168923 */ "PseudoVSUXSEG7EI16_V_MF4_MF2_MASK\0" + /* 168957 */ "PseudoVLOXSEG8EI16_V_MF4_MF2_MASK\0" + /* 168991 */ "PseudoVSOXSEG8EI16_V_MF4_MF2_MASK\0" + /* 169025 */ "PseudoVLUXSEG8EI16_V_MF4_MF2_MASK\0" + /* 169059 */ "PseudoVSUXSEG8EI16_V_MF4_MF2_MASK\0" + /* 169093 */ "PseudoVLOXEI16_V_MF4_MF2_MASK\0" + /* 169123 */ "PseudoVSOXEI16_V_MF4_MF2_MASK\0" + /* 169153 */ "PseudoVLUXEI16_V_MF4_MF2_MASK\0" + /* 169183 */ "PseudoVSUXEI16_V_MF4_MF2_MASK\0" + /* 169213 */ "PseudoVLOXSEG2EI8_V_MF4_MF2_MASK\0" + /* 169246 */ "PseudoVSOXSEG2EI8_V_MF4_MF2_MASK\0" + /* 169279 */ "PseudoVLUXSEG2EI8_V_MF4_MF2_MASK\0" + /* 169312 */ "PseudoVSUXSEG2EI8_V_MF4_MF2_MASK\0" + /* 169345 */ "PseudoVLOXSEG3EI8_V_MF4_MF2_MASK\0" + /* 169378 */ "PseudoVSOXSEG3EI8_V_MF4_MF2_MASK\0" + /* 169411 */ "PseudoVLUXSEG3EI8_V_MF4_MF2_MASK\0" + /* 169444 */ "PseudoVSUXSEG3EI8_V_MF4_MF2_MASK\0" + /* 169477 */ "PseudoVLOXSEG4EI8_V_MF4_MF2_MASK\0" + /* 169510 */ "PseudoVSOXSEG4EI8_V_MF4_MF2_MASK\0" + /* 169543 */ "PseudoVLUXSEG4EI8_V_MF4_MF2_MASK\0" + /* 169576 */ "PseudoVSUXSEG4EI8_V_MF4_MF2_MASK\0" + /* 169609 */ "PseudoVLOXSEG5EI8_V_MF4_MF2_MASK\0" + /* 169642 */ "PseudoVSOXSEG5EI8_V_MF4_MF2_MASK\0" + /* 169675 */ "PseudoVLUXSEG5EI8_V_MF4_MF2_MASK\0" + /* 169708 */ "PseudoVSUXSEG5EI8_V_MF4_MF2_MASK\0" + /* 169741 */ "PseudoVLOXSEG6EI8_V_MF4_MF2_MASK\0" + /* 169774 */ "PseudoVSOXSEG6EI8_V_MF4_MF2_MASK\0" + /* 169807 */ "PseudoVLUXSEG6EI8_V_MF4_MF2_MASK\0" + /* 169840 */ "PseudoVSUXSEG6EI8_V_MF4_MF2_MASK\0" + /* 169873 */ "PseudoVLOXSEG7EI8_V_MF4_MF2_MASK\0" + /* 169906 */ "PseudoVSOXSEG7EI8_V_MF4_MF2_MASK\0" + /* 169939 */ "PseudoVLUXSEG7EI8_V_MF4_MF2_MASK\0" + /* 169972 */ "PseudoVSUXSEG7EI8_V_MF4_MF2_MASK\0" + /* 170005 */ "PseudoVLOXSEG8EI8_V_MF4_MF2_MASK\0" + /* 170038 */ "PseudoVSOXSEG8EI8_V_MF4_MF2_MASK\0" + /* 170071 */ "PseudoVLUXSEG8EI8_V_MF4_MF2_MASK\0" + /* 170104 */ "PseudoVSUXSEG8EI8_V_MF4_MF2_MASK\0" + /* 170137 */ "PseudoVLOXEI8_V_MF4_MF2_MASK\0" + /* 170166 */ "PseudoVSOXEI8_V_MF4_MF2_MASK\0" + /* 170195 */ "PseudoVLUXEI8_V_MF4_MF2_MASK\0" + /* 170224 */ "PseudoVSUXEI8_V_MF4_MF2_MASK\0" + /* 170253 */ "PseudoVSEXT_VF4_MF2_MASK\0" + /* 170278 */ "PseudoVZEXT_VF4_MF2_MASK\0" + /* 170303 */ "PseudoVAMOADDEI8_WD_M4_MF2_MASK\0" + /* 170335 */ "PseudoVAMOANDEI8_WD_M4_MF2_MASK\0" + /* 170367 */ "PseudoVAMOMINEI8_WD_M4_MF2_MASK\0" + /* 170399 */ "PseudoVAMOSWAPEI8_WD_M4_MF2_MASK\0" + /* 170432 */ "PseudoVAMOOREI8_WD_M4_MF2_MASK\0" + /* 170463 */ "PseudoVAMOXOREI8_WD_M4_MF2_MASK\0" + /* 170495 */ "PseudoVAMOMINUEI8_WD_M4_MF2_MASK\0" + /* 170528 */ "PseudoVAMOMAXUEI8_WD_M4_MF2_MASK\0" + /* 170561 */ "PseudoVAMOMAXEI8_WD_M4_MF2_MASK\0" + /* 170593 */ "PseudoVLOXSEG2EI64_V_M4_MF2_MASK\0" + /* 170626 */ "PseudoVSOXSEG2EI64_V_M4_MF2_MASK\0" + /* 170659 */ "PseudoVLUXSEG2EI64_V_M4_MF2_MASK\0" + /* 170692 */ "PseudoVSUXSEG2EI64_V_M4_MF2_MASK\0" + /* 170725 */ "PseudoVLOXSEG3EI64_V_M4_MF2_MASK\0" + /* 170758 */ "PseudoVSOXSEG3EI64_V_M4_MF2_MASK\0" + /* 170791 */ "PseudoVLUXSEG3EI64_V_M4_MF2_MASK\0" + /* 170824 */ "PseudoVSUXSEG3EI64_V_M4_MF2_MASK\0" + /* 170857 */ "PseudoVLOXSEG4EI64_V_M4_MF2_MASK\0" + /* 170890 */ "PseudoVSOXSEG4EI64_V_M4_MF2_MASK\0" + /* 170923 */ "PseudoVLUXSEG4EI64_V_M4_MF2_MASK\0" + /* 170956 */ "PseudoVSUXSEG4EI64_V_M4_MF2_MASK\0" + /* 170989 */ "PseudoVLOXSEG5EI64_V_M4_MF2_MASK\0" + /* 171022 */ "PseudoVSOXSEG5EI64_V_M4_MF2_MASK\0" + /* 171055 */ "PseudoVLUXSEG5EI64_V_M4_MF2_MASK\0" + /* 171088 */ "PseudoVSUXSEG5EI64_V_M4_MF2_MASK\0" + /* 171121 */ "PseudoVLOXSEG6EI64_V_M4_MF2_MASK\0" + /* 171154 */ "PseudoVSOXSEG6EI64_V_M4_MF2_MASK\0" + /* 171187 */ "PseudoVLUXSEG6EI64_V_M4_MF2_MASK\0" + /* 171220 */ "PseudoVSUXSEG6EI64_V_M4_MF2_MASK\0" + /* 171253 */ "PseudoVLOXSEG7EI64_V_M4_MF2_MASK\0" + /* 171286 */ "PseudoVSOXSEG7EI64_V_M4_MF2_MASK\0" + /* 171319 */ "PseudoVLUXSEG7EI64_V_M4_MF2_MASK\0" + /* 171352 */ "PseudoVSUXSEG7EI64_V_M4_MF2_MASK\0" + /* 171385 */ "PseudoVLOXSEG8EI64_V_M4_MF2_MASK\0" + /* 171418 */ "PseudoVSOXSEG8EI64_V_M4_MF2_MASK\0" + /* 171451 */ "PseudoVLUXSEG8EI64_V_M4_MF2_MASK\0" + /* 171484 */ "PseudoVSUXSEG8EI64_V_M4_MF2_MASK\0" + /* 171517 */ "PseudoVLOXEI64_V_M4_MF2_MASK\0" + /* 171546 */ "PseudoVSOXEI64_V_M4_MF2_MASK\0" + /* 171575 */ "PseudoVLUXEI64_V_M4_MF2_MASK\0" + /* 171604 */ "PseudoVSUXEI64_V_M4_MF2_MASK\0" + /* 171633 */ "PseudoVFSUB_VF16_MF2_MASK\0" + /* 171659 */ "PseudoVFMSUB_VF16_MF2_MASK\0" + /* 171686 */ "PseudoVFNMSUB_VF16_MF2_MASK\0" + /* 171714 */ "PseudoVFRSUB_VF16_MF2_MASK\0" + /* 171741 */ "PseudoVFWSUB_VF16_MF2_MASK\0" + /* 171768 */ "PseudoVFMSAC_VF16_MF2_MASK\0" + /* 171795 */ "PseudoVFNMSAC_VF16_MF2_MASK\0" + /* 171823 */ "PseudoVFWNMSAC_VF16_MF2_MASK\0" + /* 171852 */ "PseudoVFWMSAC_VF16_MF2_MASK\0" + /* 171880 */ "PseudoVFMACC_VF16_MF2_MASK\0" + /* 171907 */ "PseudoVFNMACC_VF16_MF2_MASK\0" + /* 171935 */ "PseudoVFWNMACC_VF16_MF2_MASK\0" + /* 171964 */ "PseudoVFWMACC_VF16_MF2_MASK\0" + /* 171992 */ "PseudoVFADD_VF16_MF2_MASK\0" + /* 172018 */ "PseudoVFMADD_VF16_MF2_MASK\0" + /* 172045 */ "PseudoVFNMADD_VF16_MF2_MASK\0" + /* 172073 */ "PseudoVFWADD_VF16_MF2_MASK\0" + /* 172100 */ "PseudoVMFGE_VF16_MF2_MASK\0" + /* 172126 */ "PseudoVMFLE_VF16_MF2_MASK\0" + /* 172152 */ "PseudoVMFNE_VF16_MF2_MASK\0" + /* 172178 */ "PseudoVFSGNJ_VF16_MF2_MASK\0" + /* 172205 */ "PseudoVFMUL_VF16_MF2_MASK\0" + /* 172231 */ "PseudoVFWMUL_VF16_MF2_MASK\0" + /* 172258 */ "PseudoVFMIN_VF16_MF2_MASK\0" + /* 172284 */ "PseudoVFSGNJN_VF16_MF2_MASK\0" + /* 172312 */ "PseudoVFSLIDE1DOWN_VF16_MF2_MASK\0" + /* 172345 */ "PseudoVFSLIDE1UP_VF16_MF2_MASK\0" + /* 172376 */ "PseudoVMFEQ_VF16_MF2_MASK\0" + /* 172402 */ "PseudoVMFGT_VF16_MF2_MASK\0" + /* 172428 */ "PseudoVMFLT_VF16_MF2_MASK\0" + /* 172454 */ "PseudoVFDIV_VF16_MF2_MASK\0" + /* 172480 */ "PseudoVFRDIV_VF16_MF2_MASK\0" + /* 172507 */ "PseudoVFMAX_VF16_MF2_MASK\0" + /* 172533 */ "PseudoVFSGNJX_VF16_MF2_MASK\0" + /* 172561 */ "PseudoVFWSUB_WF16_MF2_MASK\0" + /* 172588 */ "PseudoVFWADD_WF16_MF2_MASK\0" + /* 172615 */ "PseudoVLOXSEG2EI8_V_MF8_MF2_MASK\0" + /* 172648 */ "PseudoVSOXSEG2EI8_V_MF8_MF2_MASK\0" + /* 172681 */ "PseudoVLUXSEG2EI8_V_MF8_MF2_MASK\0" + /* 172714 */ "PseudoVSUXSEG2EI8_V_MF8_MF2_MASK\0" + /* 172747 */ "PseudoVLOXSEG3EI8_V_MF8_MF2_MASK\0" + /* 172780 */ "PseudoVSOXSEG3EI8_V_MF8_MF2_MASK\0" + /* 172813 */ "PseudoVLUXSEG3EI8_V_MF8_MF2_MASK\0" + /* 172846 */ "PseudoVSUXSEG3EI8_V_MF8_MF2_MASK\0" + /* 172879 */ "PseudoVLOXSEG4EI8_V_MF8_MF2_MASK\0" + /* 172912 */ "PseudoVSOXSEG4EI8_V_MF8_MF2_MASK\0" + /* 172945 */ "PseudoVLUXSEG4EI8_V_MF8_MF2_MASK\0" + /* 172978 */ "PseudoVSUXSEG4EI8_V_MF8_MF2_MASK\0" + /* 173011 */ "PseudoVLOXSEG5EI8_V_MF8_MF2_MASK\0" + /* 173044 */ "PseudoVSOXSEG5EI8_V_MF8_MF2_MASK\0" + /* 173077 */ "PseudoVLUXSEG5EI8_V_MF8_MF2_MASK\0" + /* 173110 */ "PseudoVSUXSEG5EI8_V_MF8_MF2_MASK\0" + /* 173143 */ "PseudoVLOXSEG6EI8_V_MF8_MF2_MASK\0" + /* 173176 */ "PseudoVSOXSEG6EI8_V_MF8_MF2_MASK\0" + /* 173209 */ "PseudoVLUXSEG6EI8_V_MF8_MF2_MASK\0" + /* 173242 */ "PseudoVSUXSEG6EI8_V_MF8_MF2_MASK\0" + /* 173275 */ "PseudoVLOXSEG7EI8_V_MF8_MF2_MASK\0" + /* 173308 */ "PseudoVSOXSEG7EI8_V_MF8_MF2_MASK\0" + /* 173341 */ "PseudoVLUXSEG7EI8_V_MF8_MF2_MASK\0" + /* 173374 */ "PseudoVSUXSEG7EI8_V_MF8_MF2_MASK\0" + /* 173407 */ "PseudoVLOXSEG8EI8_V_MF8_MF2_MASK\0" + /* 173440 */ "PseudoVSOXSEG8EI8_V_MF8_MF2_MASK\0" + /* 173473 */ "PseudoVLUXSEG8EI8_V_MF8_MF2_MASK\0" + /* 173506 */ "PseudoVSUXSEG8EI8_V_MF8_MF2_MASK\0" + /* 173539 */ "PseudoVLOXEI8_V_MF8_MF2_MASK\0" + /* 173568 */ "PseudoVSOXEI8_V_MF8_MF2_MASK\0" + /* 173597 */ "PseudoVLUXEI8_V_MF8_MF2_MASK\0" + /* 173626 */ "PseudoVSUXEI8_V_MF8_MF2_MASK\0" + /* 173655 */ "PseudoVSSRA_VI_MF2_MASK\0" + /* 173679 */ "PseudoVSRA_VI_MF2_MASK\0" + /* 173702 */ "PseudoVRSUB_VI_MF2_MASK\0" + /* 173726 */ "PseudoVSADD_VI_MF2_MASK\0" + /* 173750 */ "PseudoVADD_VI_MF2_MASK\0" + /* 173773 */ "PseudoVAND_VI_MF2_MASK\0" + /* 173796 */ "PseudoVMSLE_VI_MF2_MASK\0" + /* 173820 */ "PseudoVMSNE_VI_MF2_MASK\0" + /* 173844 */ "PseudoVSLL_VI_MF2_MASK\0" + /* 173867 */ "PseudoVSSRL_VI_MF2_MASK\0" + /* 173891 */ "PseudoVSRL_VI_MF2_MASK\0" + /* 173914 */ "PseudoVSLIDEDOWN_VI_MF2_MASK\0" + /* 173943 */ "PseudoVSLIDEUP_VI_MF2_MASK\0" + /* 173970 */ "PseudoVMSEQ_VI_MF2_MASK\0" + /* 173994 */ "PseudoVRGATHER_VI_MF2_MASK\0" + /* 174021 */ "PseudoVOR_VI_MF2_MASK\0" + /* 174043 */ "PseudoVXOR_VI_MF2_MASK\0" + /* 174066 */ "PseudoVMSGT_VI_MF2_MASK\0" + /* 174090 */ "PseudoVSADDU_VI_MF2_MASK\0" + /* 174115 */ "PseudoVMSLEU_VI_MF2_MASK\0" + /* 174140 */ "PseudoVMSGTU_VI_MF2_MASK\0" + /* 174165 */ "PseudoVNSRA_WI_MF2_MASK\0" + /* 174189 */ "PseudoVNSRL_WI_MF2_MASK\0" + /* 174213 */ "PseudoVNCLIP_WI_MF2_MASK\0" + /* 174238 */ "PseudoVNCLIPU_WI_MF2_MASK\0" + /* 174264 */ "PseudoVIOTA_M_MF2_MASK\0" + /* 174287 */ "PseudoVREDAND_VS_MF2_MASK\0" + /* 174313 */ "PseudoVREDSUM_VS_MF2_MASK\0" + /* 174339 */ "PseudoVWREDSUM_VS_MF2_MASK\0" + /* 174366 */ "PseudoVFREDOSUM_VS_MF2_MASK\0" + /* 174394 */ "PseudoVFWREDOSUM_VS_MF2_MASK\0" + /* 174423 */ "PseudoVFREDUSUM_VS_MF2_MASK\0" + /* 174451 */ "PseudoVFWREDUSUM_VS_MF2_MASK\0" + /* 174480 */ "PseudoVFREDMIN_VS_MF2_MASK\0" + /* 174507 */ "PseudoVREDMIN_VS_MF2_MASK\0" + /* 174533 */ "PseudoVREDOR_VS_MF2_MASK\0" + /* 174558 */ "PseudoVREDXOR_VS_MF2_MASK\0" + /* 174584 */ "PseudoVWREDSUMU_VS_MF2_MASK\0" + /* 174612 */ "PseudoVREDMINU_VS_MF2_MASK\0" + /* 174639 */ "PseudoVREDMAXU_VS_MF2_MASK\0" + /* 174666 */ "PseudoVFREDMAX_VS_MF2_MASK\0" + /* 174693 */ "PseudoVREDMAX_VS_MF2_MASK\0" + /* 174719 */ "PseudoVSSRA_VV_MF2_MASK\0" + /* 174743 */ "PseudoVSRA_VV_MF2_MASK\0" + /* 174766 */ "PseudoVASUB_VV_MF2_MASK\0" + /* 174790 */ "PseudoVFSUB_VV_MF2_MASK\0" + /* 174814 */ "PseudoVFMSUB_VV_MF2_MASK\0" + /* 174839 */ "PseudoVFNMSUB_VV_MF2_MASK\0" + /* 174865 */ "PseudoVNMSUB_VV_MF2_MASK\0" + /* 174890 */ "PseudoVSSUB_VV_MF2_MASK\0" + /* 174914 */ "PseudoVSUB_VV_MF2_MASK\0" + /* 174937 */ "PseudoVFWSUB_VV_MF2_MASK\0" + /* 174962 */ "PseudoVWSUB_VV_MF2_MASK\0" + /* 174986 */ "PseudoVFMSAC_VV_MF2_MASK\0" + /* 175011 */ "PseudoVFNMSAC_VV_MF2_MASK\0" + /* 175037 */ "PseudoVNMSAC_VV_MF2_MASK\0" + /* 175062 */ "PseudoVFWNMSAC_VV_MF2_MASK\0" + /* 175089 */ "PseudoVFWMSAC_VV_MF2_MASK\0" + /* 175115 */ "PseudoVFMACC_VV_MF2_MASK\0" + /* 175140 */ "PseudoVFNMACC_VV_MF2_MASK\0" + /* 175166 */ "PseudoVFWNMACC_VV_MF2_MASK\0" + /* 175193 */ "PseudoVMACC_VV_MF2_MASK\0" + /* 175217 */ "PseudoVFWMACC_VV_MF2_MASK\0" + /* 175243 */ "PseudoVWMACC_VV_MF2_MASK\0" + /* 175268 */ "PseudoVAADD_VV_MF2_MASK\0" + /* 175292 */ "PseudoVFADD_VV_MF2_MASK\0" + /* 175316 */ "PseudoVFMADD_VV_MF2_MASK\0" + /* 175341 */ "PseudoVFNMADD_VV_MF2_MASK\0" + /* 175367 */ "PseudoVMADD_VV_MF2_MASK\0" + /* 175391 */ "PseudoVSADD_VV_MF2_MASK\0" + /* 175415 */ "PseudoVADD_VV_MF2_MASK\0" + /* 175438 */ "PseudoVFWADD_VV_MF2_MASK\0" + /* 175463 */ "PseudoVWADD_VV_MF2_MASK\0" + /* 175487 */ "PseudoVAND_VV_MF2_MASK\0" + /* 175510 */ "PseudoVMFLE_VV_MF2_MASK\0" + /* 175534 */ "PseudoVMSLE_VV_MF2_MASK\0" + /* 175558 */ "PseudoVMFNE_VV_MF2_MASK\0" + /* 175582 */ "PseudoVMSNE_VV_MF2_MASK\0" + /* 175606 */ "PseudoVMULH_VV_MF2_MASK\0" + /* 175630 */ "PseudoVFSGNJ_VV_MF2_MASK\0" + /* 175655 */ "PseudoVSLL_VV_MF2_MASK\0" + /* 175678 */ "PseudoVSSRL_VV_MF2_MASK\0" + /* 175702 */ "PseudoVSRL_VV_MF2_MASK\0" + /* 175725 */ "PseudoVFMUL_VV_MF2_MASK\0" + /* 175749 */ "PseudoVSMUL_VV_MF2_MASK\0" + /* 175773 */ "PseudoVMUL_VV_MF2_MASK\0" + /* 175796 */ "PseudoVFWMUL_VV_MF2_MASK\0" + /* 175821 */ "PseudoVWMUL_VV_MF2_MASK\0" + /* 175845 */ "PseudoVREM_VV_MF2_MASK\0" + /* 175868 */ "PseudoVFMIN_VV_MF2_MASK\0" + /* 175892 */ "PseudoVMIN_VV_MF2_MASK\0" + /* 175915 */ "PseudoVFSGNJN_VV_MF2_MASK\0" + /* 175941 */ "PseudoVMFEQ_VV_MF2_MASK\0" + /* 175965 */ "PseudoVMSEQ_VV_MF2_MASK\0" + /* 175989 */ "PseudoVRGATHER_VV_MF2_MASK\0" + /* 176016 */ "PseudoVOR_VV_MF2_MASK\0" + /* 176038 */ "PseudoVXOR_VV_MF2_MASK\0" + /* 176061 */ "PseudoVMFLT_VV_MF2_MASK\0" + /* 176085 */ "PseudoVMSLT_VV_MF2_MASK\0" + /* 176109 */ "PseudoVASUBU_VV_MF2_MASK\0" + /* 176134 */ "PseudoVSSUBU_VV_MF2_MASK\0" + /* 176159 */ "PseudoVWSUBU_VV_MF2_MASK\0" + /* 176184 */ "PseudoVWMACCU_VV_MF2_MASK\0" + /* 176210 */ "PseudoVAADDU_VV_MF2_MASK\0" + /* 176235 */ "PseudoVSADDU_VV_MF2_MASK\0" + /* 176260 */ "PseudoVWADDU_VV_MF2_MASK\0" + /* 176285 */ "PseudoVMSLEU_VV_MF2_MASK\0" + /* 176310 */ "PseudoVMULHU_VV_MF2_MASK\0" + /* 176335 */ "PseudoVWMULU_VV_MF2_MASK\0" + /* 176360 */ "PseudoVREMU_VV_MF2_MASK\0" + /* 176384 */ "PseudoVMINU_VV_MF2_MASK\0" + /* 176408 */ "PseudoVWMACCSU_VV_MF2_MASK\0" + /* 176435 */ "PseudoVMULHSU_VV_MF2_MASK\0" + /* 176461 */ "PseudoVWMULSU_VV_MF2_MASK\0" + /* 176487 */ "PseudoVMSLTU_VV_MF2_MASK\0" + /* 176512 */ "PseudoVDIVU_VV_MF2_MASK\0" + /* 176536 */ "PseudoVMAXU_VV_MF2_MASK\0" + /* 176560 */ "PseudoVFDIV_VV_MF2_MASK\0" + /* 176584 */ "PseudoVDIV_VV_MF2_MASK\0" + /* 176607 */ "PseudoVFMAX_VV_MF2_MASK\0" + /* 176631 */ "PseudoVMAX_VV_MF2_MASK\0" + /* 176654 */ "PseudoVFSGNJX_VV_MF2_MASK\0" + /* 176680 */ "PseudoVNSRA_WV_MF2_MASK\0" + /* 176704 */ "PseudoVFWSUB_WV_MF2_MASK\0" + /* 176729 */ "PseudoVWSUB_WV_MF2_MASK\0" + /* 176753 */ "PseudoVFWADD_WV_MF2_MASK\0" + /* 176778 */ "PseudoVWADD_WV_MF2_MASK\0" + /* 176802 */ "PseudoVNSRL_WV_MF2_MASK\0" + /* 176826 */ "PseudoVNCLIP_WV_MF2_MASK\0" + /* 176851 */ "PseudoVWSUBU_WV_MF2_MASK\0" + /* 176876 */ "PseudoVWADDU_WV_MF2_MASK\0" + /* 176901 */ "PseudoVNCLIPU_WV_MF2_MASK\0" + /* 176927 */ "PseudoVLSEG2E32_V_MF2_MASK\0" + /* 176954 */ "PseudoVLSSEG2E32_V_MF2_MASK\0" + /* 176982 */ "PseudoVSSSEG2E32_V_MF2_MASK\0" + /* 177010 */ "PseudoVSSEG2E32_V_MF2_MASK\0" + /* 177037 */ "PseudoVLSEG3E32_V_MF2_MASK\0" + /* 177064 */ "PseudoVLSSEG3E32_V_MF2_MASK\0" + /* 177092 */ "PseudoVSSSEG3E32_V_MF2_MASK\0" + /* 177120 */ "PseudoVSSEG3E32_V_MF2_MASK\0" + /* 177147 */ "PseudoVLSEG4E32_V_MF2_MASK\0" + /* 177174 */ "PseudoVLSSEG4E32_V_MF2_MASK\0" + /* 177202 */ "PseudoVSSSEG4E32_V_MF2_MASK\0" + /* 177230 */ "PseudoVSSEG4E32_V_MF2_MASK\0" + /* 177257 */ "PseudoVLSEG5E32_V_MF2_MASK\0" + /* 177284 */ "PseudoVLSSEG5E32_V_MF2_MASK\0" + /* 177312 */ "PseudoVSSSEG5E32_V_MF2_MASK\0" + /* 177340 */ "PseudoVSSEG5E32_V_MF2_MASK\0" + /* 177367 */ "PseudoVLSEG6E32_V_MF2_MASK\0" + /* 177394 */ "PseudoVLSSEG6E32_V_MF2_MASK\0" + /* 177422 */ "PseudoVSSSEG6E32_V_MF2_MASK\0" + /* 177450 */ "PseudoVSSEG6E32_V_MF2_MASK\0" + /* 177477 */ "PseudoVLSEG7E32_V_MF2_MASK\0" + /* 177504 */ "PseudoVLSSEG7E32_V_MF2_MASK\0" + /* 177532 */ "PseudoVSSSEG7E32_V_MF2_MASK\0" + /* 177560 */ "PseudoVSSEG7E32_V_MF2_MASK\0" + /* 177587 */ "PseudoVLSEG8E32_V_MF2_MASK\0" + /* 177614 */ "PseudoVLSSEG8E32_V_MF2_MASK\0" + /* 177642 */ "PseudoVSSSEG8E32_V_MF2_MASK\0" + /* 177670 */ "PseudoVSSEG8E32_V_MF2_MASK\0" + /* 177697 */ "PseudoVLE32_V_MF2_MASK\0" + /* 177720 */ "PseudoVLSE32_V_MF2_MASK\0" + /* 177744 */ "PseudoVSSE32_V_MF2_MASK\0" + /* 177768 */ "PseudoVSE32_V_MF2_MASK\0" + /* 177791 */ "PseudoVLSEG2E16_V_MF2_MASK\0" + /* 177818 */ "PseudoVLSSEG2E16_V_MF2_MASK\0" + /* 177846 */ "PseudoVSSSEG2E16_V_MF2_MASK\0" + /* 177874 */ "PseudoVSSEG2E16_V_MF2_MASK\0" + /* 177901 */ "PseudoVLSEG3E16_V_MF2_MASK\0" + /* 177928 */ "PseudoVLSSEG3E16_V_MF2_MASK\0" + /* 177956 */ "PseudoVSSSEG3E16_V_MF2_MASK\0" + /* 177984 */ "PseudoVSSEG3E16_V_MF2_MASK\0" + /* 178011 */ "PseudoVLSEG4E16_V_MF2_MASK\0" + /* 178038 */ "PseudoVLSSEG4E16_V_MF2_MASK\0" + /* 178066 */ "PseudoVSSSEG4E16_V_MF2_MASK\0" + /* 178094 */ "PseudoVSSEG4E16_V_MF2_MASK\0" + /* 178121 */ "PseudoVLSEG5E16_V_MF2_MASK\0" + /* 178148 */ "PseudoVLSSEG5E16_V_MF2_MASK\0" + /* 178176 */ "PseudoVSSSEG5E16_V_MF2_MASK\0" + /* 178204 */ "PseudoVSSEG5E16_V_MF2_MASK\0" + /* 178231 */ "PseudoVLSEG6E16_V_MF2_MASK\0" + /* 178258 */ "PseudoVLSSEG6E16_V_MF2_MASK\0" + /* 178286 */ "PseudoVSSSEG6E16_V_MF2_MASK\0" + /* 178314 */ "PseudoVSSEG6E16_V_MF2_MASK\0" + /* 178341 */ "PseudoVLSEG7E16_V_MF2_MASK\0" + /* 178368 */ "PseudoVLSSEG7E16_V_MF2_MASK\0" + /* 178396 */ "PseudoVSSSEG7E16_V_MF2_MASK\0" + /* 178424 */ "PseudoVSSEG7E16_V_MF2_MASK\0" + /* 178451 */ "PseudoVLSEG8E16_V_MF2_MASK\0" + /* 178478 */ "PseudoVLSSEG8E16_V_MF2_MASK\0" + /* 178506 */ "PseudoVSSSEG8E16_V_MF2_MASK\0" + /* 178534 */ "PseudoVSSEG8E16_V_MF2_MASK\0" + /* 178561 */ "PseudoVLE16_V_MF2_MASK\0" + /* 178584 */ "PseudoVLSE16_V_MF2_MASK\0" + /* 178608 */ "PseudoVSSE16_V_MF2_MASK\0" + /* 178632 */ "PseudoVSE16_V_MF2_MASK\0" + /* 178655 */ "PseudoVFREC7_V_MF2_MASK\0" + /* 178679 */ "PseudoVFRSQRT7_V_MF2_MASK\0" + /* 178705 */ "PseudoVLSEG2E8_V_MF2_MASK\0" + /* 178731 */ "PseudoVLSSEG2E8_V_MF2_MASK\0" + /* 178758 */ "PseudoVSSSEG2E8_V_MF2_MASK\0" + /* 178785 */ "PseudoVSSEG2E8_V_MF2_MASK\0" + /* 178811 */ "PseudoVLSEG3E8_V_MF2_MASK\0" + /* 178837 */ "PseudoVLSSEG3E8_V_MF2_MASK\0" + /* 178864 */ "PseudoVSSSEG3E8_V_MF2_MASK\0" + /* 178891 */ "PseudoVSSEG3E8_V_MF2_MASK\0" + /* 178917 */ "PseudoVLSEG4E8_V_MF2_MASK\0" + /* 178943 */ "PseudoVLSSEG4E8_V_MF2_MASK\0" + /* 178970 */ "PseudoVSSSEG4E8_V_MF2_MASK\0" + /* 178997 */ "PseudoVSSEG4E8_V_MF2_MASK\0" + /* 179023 */ "PseudoVLSEG5E8_V_MF2_MASK\0" + /* 179049 */ "PseudoVLSSEG5E8_V_MF2_MASK\0" + /* 179076 */ "PseudoVSSSEG5E8_V_MF2_MASK\0" + /* 179103 */ "PseudoVSSEG5E8_V_MF2_MASK\0" + /* 179129 */ "PseudoVLSEG6E8_V_MF2_MASK\0" + /* 179155 */ "PseudoVLSSEG6E8_V_MF2_MASK\0" + /* 179182 */ "PseudoVSSSEG6E8_V_MF2_MASK\0" + /* 179209 */ "PseudoVSSEG6E8_V_MF2_MASK\0" + /* 179235 */ "PseudoVLSEG7E8_V_MF2_MASK\0" + /* 179261 */ "PseudoVLSSEG7E8_V_MF2_MASK\0" + /* 179288 */ "PseudoVSSSEG7E8_V_MF2_MASK\0" + /* 179315 */ "PseudoVSSEG7E8_V_MF2_MASK\0" + /* 179341 */ "PseudoVLSEG8E8_V_MF2_MASK\0" + /* 179367 */ "PseudoVLSSEG8E8_V_MF2_MASK\0" + /* 179394 */ "PseudoVSSSEG8E8_V_MF2_MASK\0" + /* 179421 */ "PseudoVSSEG8E8_V_MF2_MASK\0" + /* 179447 */ "PseudoVLE8_V_MF2_MASK\0" + /* 179469 */ "PseudoVLSE8_V_MF2_MASK\0" + /* 179492 */ "PseudoVSSE8_V_MF2_MASK\0" + /* 179515 */ "PseudoVSE8_V_MF2_MASK\0" + /* 179537 */ "PseudoVID_V_MF2_MASK\0" + /* 179558 */ "PseudoVLSEG2E32FF_V_MF2_MASK\0" + /* 179587 */ "PseudoVLSEG3E32FF_V_MF2_MASK\0" + /* 179616 */ "PseudoVLSEG4E32FF_V_MF2_MASK\0" + /* 179645 */ "PseudoVLSEG5E32FF_V_MF2_MASK\0" + /* 179674 */ "PseudoVLSEG6E32FF_V_MF2_MASK\0" + /* 179703 */ "PseudoVLSEG7E32FF_V_MF2_MASK\0" + /* 179732 */ "PseudoVLSEG8E32FF_V_MF2_MASK\0" + /* 179761 */ "PseudoVLE32FF_V_MF2_MASK\0" + /* 179786 */ "PseudoVLSEG2E16FF_V_MF2_MASK\0" + /* 179815 */ "PseudoVLSEG3E16FF_V_MF2_MASK\0" + /* 179844 */ "PseudoVLSEG4E16FF_V_MF2_MASK\0" + /* 179873 */ "PseudoVLSEG5E16FF_V_MF2_MASK\0" + /* 179902 */ "PseudoVLSEG6E16FF_V_MF2_MASK\0" + /* 179931 */ "PseudoVLSEG7E16FF_V_MF2_MASK\0" + /* 179960 */ "PseudoVLSEG8E16FF_V_MF2_MASK\0" + /* 179989 */ "PseudoVLE16FF_V_MF2_MASK\0" + /* 180014 */ "PseudoVLSEG2E8FF_V_MF2_MASK\0" + /* 180042 */ "PseudoVLSEG3E8FF_V_MF2_MASK\0" + /* 180070 */ "PseudoVLSEG4E8FF_V_MF2_MASK\0" + /* 180098 */ "PseudoVLSEG5E8FF_V_MF2_MASK\0" + /* 180126 */ "PseudoVLSEG6E8FF_V_MF2_MASK\0" + /* 180154 */ "PseudoVLSEG7E8FF_V_MF2_MASK\0" + /* 180182 */ "PseudoVLSEG8E8FF_V_MF2_MASK\0" + /* 180210 */ "PseudoVLE8FF_V_MF2_MASK\0" + /* 180234 */ "PseudoVFWCVT_F_F_V_MF2_MASK\0" + /* 180262 */ "PseudoVFCVT_XU_F_V_MF2_MASK\0" + /* 180290 */ "PseudoVFWCVT_XU_F_V_MF2_MASK\0" + /* 180319 */ "PseudoVFCVT_RTZ_XU_F_V_MF2_MASK\0" + /* 180351 */ "PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK\0" + /* 180384 */ "PseudoVFCVT_X_F_V_MF2_MASK\0" + /* 180411 */ "PseudoVFWCVT_X_F_V_MF2_MASK\0" + /* 180439 */ "PseudoVFCVT_RTZ_X_F_V_MF2_MASK\0" + /* 180470 */ "PseudoVFWCVT_RTZ_X_F_V_MF2_MASK\0" + /* 180502 */ "PseudoVFCLASS_V_MF2_MASK\0" + /* 180527 */ "PseudoVFSQRT_V_MF2_MASK\0" + /* 180551 */ "PseudoVFCVT_F_XU_V_MF2_MASK\0" + /* 180579 */ "PseudoVFWCVT_F_XU_V_MF2_MASK\0" + /* 180608 */ "PseudoVFCVT_F_X_V_MF2_MASK\0" + /* 180635 */ "PseudoVFWCVT_F_X_V_MF2_MASK\0" + /* 180663 */ "PseudoVFNCVT_ROD_F_F_W_MF2_MASK\0" + /* 180695 */ "PseudoVFNCVT_F_F_W_MF2_MASK\0" + /* 180723 */ "PseudoVFNCVT_XU_F_W_MF2_MASK\0" + /* 180752 */ "PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK\0" + /* 180785 */ "PseudoVFNCVT_X_F_W_MF2_MASK\0" + /* 180813 */ "PseudoVFNCVT_RTZ_X_F_W_MF2_MASK\0" + /* 180845 */ "PseudoVFNCVT_F_XU_W_MF2_MASK\0" + /* 180874 */ "PseudoVFNCVT_F_X_W_MF2_MASK\0" + /* 180902 */ "PseudoVSSRA_VX_MF2_MASK\0" + /* 180926 */ "PseudoVSRA_VX_MF2_MASK\0" + /* 180949 */ "PseudoVASUB_VX_MF2_MASK\0" + /* 180973 */ "PseudoVNMSUB_VX_MF2_MASK\0" + /* 180998 */ "PseudoVRSUB_VX_MF2_MASK\0" + /* 181022 */ "PseudoVSSUB_VX_MF2_MASK\0" + /* 181046 */ "PseudoVSUB_VX_MF2_MASK\0" + /* 181069 */ "PseudoVWSUB_VX_MF2_MASK\0" + /* 181093 */ "PseudoVNMSAC_VX_MF2_MASK\0" + /* 181118 */ "PseudoVMACC_VX_MF2_MASK\0" + /* 181142 */ "PseudoVWMACC_VX_MF2_MASK\0" + /* 181167 */ "PseudoVAADD_VX_MF2_MASK\0" + /* 181191 */ "PseudoVMADD_VX_MF2_MASK\0" + /* 181215 */ "PseudoVSADD_VX_MF2_MASK\0" + /* 181239 */ "PseudoVADD_VX_MF2_MASK\0" + /* 181262 */ "PseudoVWADD_VX_MF2_MASK\0" + /* 181286 */ "PseudoVAND_VX_MF2_MASK\0" + /* 181309 */ "PseudoVMSLE_VX_MF2_MASK\0" + /* 181333 */ "PseudoVMSNE_VX_MF2_MASK\0" + /* 181357 */ "PseudoVMULH_VX_MF2_MASK\0" + /* 181381 */ "PseudoVSLL_VX_MF2_MASK\0" + /* 181404 */ "PseudoVSSRL_VX_MF2_MASK\0" + /* 181428 */ "PseudoVSRL_VX_MF2_MASK\0" + /* 181451 */ "PseudoVSMUL_VX_MF2_MASK\0" + /* 181475 */ "PseudoVMUL_VX_MF2_MASK\0" + /* 181498 */ "PseudoVWMUL_VX_MF2_MASK\0" + /* 181522 */ "PseudoVREM_VX_MF2_MASK\0" + /* 181545 */ "PseudoVMIN_VX_MF2_MASK\0" + /* 181568 */ "PseudoVSLIDE1DOWN_VX_MF2_MASK\0" + /* 181598 */ "PseudoVSLIDEDOWN_VX_MF2_MASK\0" + /* 181627 */ "PseudoVSLIDE1UP_VX_MF2_MASK\0" + /* 181655 */ "PseudoVSLIDEUP_VX_MF2_MASK\0" + /* 181682 */ "PseudoVMSEQ_VX_MF2_MASK\0" + /* 181706 */ "PseudoVRGATHER_VX_MF2_MASK\0" + /* 181733 */ "PseudoVOR_VX_MF2_MASK\0" + /* 181755 */ "PseudoVXOR_VX_MF2_MASK\0" + /* 181778 */ "PseudoVWMACCUS_VX_MF2_MASK\0" + /* 181805 */ "PseudoVMSGT_VX_MF2_MASK\0" + /* 181829 */ "PseudoVMSLT_VX_MF2_MASK\0" + /* 181853 */ "PseudoVASUBU_VX_MF2_MASK\0" + /* 181878 */ "PseudoVSSUBU_VX_MF2_MASK\0" + /* 181903 */ "PseudoVWSUBU_VX_MF2_MASK\0" + /* 181928 */ "PseudoVWMACCU_VX_MF2_MASK\0" + /* 181954 */ "PseudoVAADDU_VX_MF2_MASK\0" + /* 181979 */ "PseudoVSADDU_VX_MF2_MASK\0" + /* 182004 */ "PseudoVWADDU_VX_MF2_MASK\0" + /* 182029 */ "PseudoVMSLEU_VX_MF2_MASK\0" + /* 182054 */ "PseudoVMULHU_VX_MF2_MASK\0" + /* 182079 */ "PseudoVWMULU_VX_MF2_MASK\0" + /* 182104 */ "PseudoVREMU_VX_MF2_MASK\0" + /* 182128 */ "PseudoVMINU_VX_MF2_MASK\0" + /* 182152 */ "PseudoVWMACCSU_VX_MF2_MASK\0" + /* 182179 */ "PseudoVMULHSU_VX_MF2_MASK\0" + /* 182205 */ "PseudoVWMULSU_VX_MF2_MASK\0" + /* 182231 */ "PseudoVMSGTU_VX_MF2_MASK\0" + /* 182256 */ "PseudoVMSLTU_VX_MF2_MASK\0" + /* 182281 */ "PseudoVDIVU_VX_MF2_MASK\0" + /* 182305 */ "PseudoVMAXU_VX_MF2_MASK\0" + /* 182329 */ "PseudoVDIV_VX_MF2_MASK\0" + /* 182352 */ "PseudoVMAX_VX_MF2_MASK\0" + /* 182375 */ "PseudoVNSRA_WX_MF2_MASK\0" + /* 182399 */ "PseudoVWSUB_WX_MF2_MASK\0" + /* 182423 */ "PseudoVWADD_WX_MF2_MASK\0" + /* 182447 */ "PseudoVNSRL_WX_MF2_MASK\0" + /* 182471 */ "PseudoVNCLIP_WX_MF2_MASK\0" + /* 182496 */ "PseudoVWSUBU_WX_MF2_MASK\0" + /* 182521 */ "PseudoVWADDU_WX_MF2_MASK\0" + /* 182546 */ "PseudoVNCLIPU_WX_MF2_MASK\0" + /* 182572 */ "PseudoVAMOADDEI64_WD_M1_M2_MASK\0" + /* 182604 */ "PseudoVAMOANDEI64_WD_M1_M2_MASK\0" + /* 182636 */ "PseudoVAMOMINEI64_WD_M1_M2_MASK\0" + /* 182668 */ "PseudoVAMOSWAPEI64_WD_M1_M2_MASK\0" + /* 182701 */ "PseudoVAMOOREI64_WD_M1_M2_MASK\0" + /* 182732 */ "PseudoVAMOXOREI64_WD_M1_M2_MASK\0" + /* 182764 */ "PseudoVAMOMINUEI64_WD_M1_M2_MASK\0" + /* 182797 */ "PseudoVAMOMAXUEI64_WD_M1_M2_MASK\0" + /* 182830 */ "PseudoVAMOMAXEI64_WD_M1_M2_MASK\0" + /* 182862 */ "PseudoVRGATHEREI16_VV_M1_M2_MASK\0" + /* 182895 */ "PseudoVLOXSEG2EI32_V_M1_M2_MASK\0" + /* 182927 */ "PseudoVSOXSEG2EI32_V_M1_M2_MASK\0" + /* 182959 */ "PseudoVLUXSEG2EI32_V_M1_M2_MASK\0" + /* 182991 */ "PseudoVSUXSEG2EI32_V_M1_M2_MASK\0" + /* 183023 */ "PseudoVLOXSEG3EI32_V_M1_M2_MASK\0" + /* 183055 */ "PseudoVSOXSEG3EI32_V_M1_M2_MASK\0" + /* 183087 */ "PseudoVLUXSEG3EI32_V_M1_M2_MASK\0" + /* 183119 */ "PseudoVSUXSEG3EI32_V_M1_M2_MASK\0" + /* 183151 */ "PseudoVLOXSEG4EI32_V_M1_M2_MASK\0" + /* 183183 */ "PseudoVSOXSEG4EI32_V_M1_M2_MASK\0" + /* 183215 */ "PseudoVLUXSEG4EI32_V_M1_M2_MASK\0" + /* 183247 */ "PseudoVSUXSEG4EI32_V_M1_M2_MASK\0" + /* 183279 */ "PseudoVLOXEI32_V_M1_M2_MASK\0" + /* 183307 */ "PseudoVSOXEI32_V_M1_M2_MASK\0" + /* 183335 */ "PseudoVLUXEI32_V_M1_M2_MASK\0" + /* 183363 */ "PseudoVSUXEI32_V_M1_M2_MASK\0" + /* 183391 */ "PseudoVLOXSEG2EI16_V_M1_M2_MASK\0" + /* 183423 */ "PseudoVSOXSEG2EI16_V_M1_M2_MASK\0" + /* 183455 */ "PseudoVLUXSEG2EI16_V_M1_M2_MASK\0" + /* 183487 */ "PseudoVSUXSEG2EI16_V_M1_M2_MASK\0" + /* 183519 */ "PseudoVLOXSEG3EI16_V_M1_M2_MASK\0" + /* 183551 */ "PseudoVSOXSEG3EI16_V_M1_M2_MASK\0" + /* 183583 */ "PseudoVLUXSEG3EI16_V_M1_M2_MASK\0" + /* 183615 */ "PseudoVSUXSEG3EI16_V_M1_M2_MASK\0" + /* 183647 */ "PseudoVLOXSEG4EI16_V_M1_M2_MASK\0" + /* 183679 */ "PseudoVSOXSEG4EI16_V_M1_M2_MASK\0" + /* 183711 */ "PseudoVLUXSEG4EI16_V_M1_M2_MASK\0" + /* 183743 */ "PseudoVSUXSEG4EI16_V_M1_M2_MASK\0" + /* 183775 */ "PseudoVLOXEI16_V_M1_M2_MASK\0" + /* 183803 */ "PseudoVSOXEI16_V_M1_M2_MASK\0" + /* 183831 */ "PseudoVLUXEI16_V_M1_M2_MASK\0" + /* 183859 */ "PseudoVSUXEI16_V_M1_M2_MASK\0" + /* 183887 */ "PseudoVLOXSEG2EI8_V_M1_M2_MASK\0" + /* 183918 */ "PseudoVSOXSEG2EI8_V_M1_M2_MASK\0" + /* 183949 */ "PseudoVLUXSEG2EI8_V_M1_M2_MASK\0" + /* 183980 */ "PseudoVSUXSEG2EI8_V_M1_M2_MASK\0" + /* 184011 */ "PseudoVLOXSEG3EI8_V_M1_M2_MASK\0" + /* 184042 */ "PseudoVSOXSEG3EI8_V_M1_M2_MASK\0" + /* 184073 */ "PseudoVLUXSEG3EI8_V_M1_M2_MASK\0" + /* 184104 */ "PseudoVSUXSEG3EI8_V_M1_M2_MASK\0" + /* 184135 */ "PseudoVLOXSEG4EI8_V_M1_M2_MASK\0" + /* 184166 */ "PseudoVSOXSEG4EI8_V_M1_M2_MASK\0" + /* 184197 */ "PseudoVLUXSEG4EI8_V_M1_M2_MASK\0" + /* 184228 */ "PseudoVSUXSEG4EI8_V_M1_M2_MASK\0" + /* 184259 */ "PseudoVLOXEI8_V_M1_M2_MASK\0" + /* 184286 */ "PseudoVSOXEI8_V_M1_M2_MASK\0" + /* 184313 */ "PseudoVLUXEI8_V_M1_M2_MASK\0" + /* 184340 */ "PseudoVSUXEI8_V_M1_M2_MASK\0" + /* 184367 */ "PseudoVFSUB_VF32_M2_MASK\0" + /* 184392 */ "PseudoVFMSUB_VF32_M2_MASK\0" + /* 184418 */ "PseudoVFNMSUB_VF32_M2_MASK\0" + /* 184445 */ "PseudoVFRSUB_VF32_M2_MASK\0" + /* 184471 */ "PseudoVFWSUB_VF32_M2_MASK\0" + /* 184497 */ "PseudoVFMSAC_VF32_M2_MASK\0" + /* 184523 */ "PseudoVFNMSAC_VF32_M2_MASK\0" + /* 184550 */ "PseudoVFWNMSAC_VF32_M2_MASK\0" + /* 184578 */ "PseudoVFWMSAC_VF32_M2_MASK\0" + /* 184605 */ "PseudoVFMACC_VF32_M2_MASK\0" + /* 184631 */ "PseudoVFNMACC_VF32_M2_MASK\0" + /* 184658 */ "PseudoVFWNMACC_VF32_M2_MASK\0" + /* 184686 */ "PseudoVFWMACC_VF32_M2_MASK\0" + /* 184713 */ "PseudoVFADD_VF32_M2_MASK\0" + /* 184738 */ "PseudoVFMADD_VF32_M2_MASK\0" + /* 184764 */ "PseudoVFNMADD_VF32_M2_MASK\0" + /* 184791 */ "PseudoVFWADD_VF32_M2_MASK\0" + /* 184817 */ "PseudoVMFGE_VF32_M2_MASK\0" + /* 184842 */ "PseudoVMFLE_VF32_M2_MASK\0" + /* 184867 */ "PseudoVMFNE_VF32_M2_MASK\0" + /* 184892 */ "PseudoVFSGNJ_VF32_M2_MASK\0" + /* 184918 */ "PseudoVFMUL_VF32_M2_MASK\0" + /* 184943 */ "PseudoVFWMUL_VF32_M2_MASK\0" + /* 184969 */ "PseudoVFMIN_VF32_M2_MASK\0" + /* 184994 */ "PseudoVFSGNJN_VF32_M2_MASK\0" + /* 185021 */ "PseudoVFSLIDE1DOWN_VF32_M2_MASK\0" + /* 185053 */ "PseudoVFSLIDE1UP_VF32_M2_MASK\0" + /* 185083 */ "PseudoVMFEQ_VF32_M2_MASK\0" + /* 185108 */ "PseudoVMFGT_VF32_M2_MASK\0" + /* 185133 */ "PseudoVMFLT_VF32_M2_MASK\0" + /* 185158 */ "PseudoVFDIV_VF32_M2_MASK\0" + /* 185183 */ "PseudoVFRDIV_VF32_M2_MASK\0" + /* 185209 */ "PseudoVFMAX_VF32_M2_MASK\0" + /* 185234 */ "PseudoVFSGNJX_VF32_M2_MASK\0" + /* 185261 */ "PseudoVFWSUB_WF32_M2_MASK\0" + /* 185287 */ "PseudoVFWADD_WF32_M2_MASK\0" + /* 185313 */ "PseudoVLOXSEG2EI16_V_MF2_M2_MASK\0" + /* 185346 */ "PseudoVSOXSEG2EI16_V_MF2_M2_MASK\0" + /* 185379 */ "PseudoVLUXSEG2EI16_V_MF2_M2_MASK\0" + /* 185412 */ "PseudoVSUXSEG2EI16_V_MF2_M2_MASK\0" + /* 185445 */ "PseudoVLOXSEG3EI16_V_MF2_M2_MASK\0" + /* 185478 */ "PseudoVSOXSEG3EI16_V_MF2_M2_MASK\0" + /* 185511 */ "PseudoVLUXSEG3EI16_V_MF2_M2_MASK\0" + /* 185544 */ "PseudoVSUXSEG3EI16_V_MF2_M2_MASK\0" + /* 185577 */ "PseudoVLOXSEG4EI16_V_MF2_M2_MASK\0" + /* 185610 */ "PseudoVSOXSEG4EI16_V_MF2_M2_MASK\0" + /* 185643 */ "PseudoVLUXSEG4EI16_V_MF2_M2_MASK\0" + /* 185676 */ "PseudoVSUXSEG4EI16_V_MF2_M2_MASK\0" + /* 185709 */ "PseudoVLOXEI16_V_MF2_M2_MASK\0" + /* 185738 */ "PseudoVSOXEI16_V_MF2_M2_MASK\0" + /* 185767 */ "PseudoVLUXEI16_V_MF2_M2_MASK\0" + /* 185796 */ "PseudoVSUXEI16_V_MF2_M2_MASK\0" + /* 185825 */ "PseudoVLOXSEG2EI8_V_MF2_M2_MASK\0" + /* 185857 */ "PseudoVSOXSEG2EI8_V_MF2_M2_MASK\0" + /* 185889 */ "PseudoVLUXSEG2EI8_V_MF2_M2_MASK\0" + /* 185921 */ "PseudoVSUXSEG2EI8_V_MF2_M2_MASK\0" + /* 185953 */ "PseudoVLOXSEG3EI8_V_MF2_M2_MASK\0" + /* 185985 */ "PseudoVSOXSEG3EI8_V_MF2_M2_MASK\0" + /* 186017 */ "PseudoVLUXSEG3EI8_V_MF2_M2_MASK\0" + /* 186049 */ "PseudoVSUXSEG3EI8_V_MF2_M2_MASK\0" + /* 186081 */ "PseudoVLOXSEG4EI8_V_MF2_M2_MASK\0" + /* 186113 */ "PseudoVSOXSEG4EI8_V_MF2_M2_MASK\0" + /* 186145 */ "PseudoVLUXSEG4EI8_V_MF2_M2_MASK\0" + /* 186177 */ "PseudoVSUXSEG4EI8_V_MF2_M2_MASK\0" + /* 186209 */ "PseudoVLOXEI8_V_MF2_M2_MASK\0" + /* 186237 */ "PseudoVSOXEI8_V_MF2_M2_MASK\0" + /* 186265 */ "PseudoVLUXEI8_V_MF2_M2_MASK\0" + /* 186293 */ "PseudoVSUXEI8_V_MF2_M2_MASK\0" + /* 186321 */ "PseudoVSEXT_VF2_M2_MASK\0" + /* 186345 */ "PseudoVZEXT_VF2_M2_MASK\0" + /* 186369 */ "PseudoVAMOADDEI32_WD_M2_M2_MASK\0" + /* 186401 */ "PseudoVAMOANDEI32_WD_M2_M2_MASK\0" + /* 186433 */ "PseudoVAMOMINEI32_WD_M2_M2_MASK\0" + /* 186465 */ "PseudoVAMOSWAPEI32_WD_M2_M2_MASK\0" + /* 186498 */ "PseudoVAMOOREI32_WD_M2_M2_MASK\0" + /* 186529 */ "PseudoVAMOXOREI32_WD_M2_M2_MASK\0" + /* 186561 */ "PseudoVAMOMINUEI32_WD_M2_M2_MASK\0" + /* 186594 */ "PseudoVAMOMAXUEI32_WD_M2_M2_MASK\0" + /* 186627 */ "PseudoVAMOMAXEI32_WD_M2_M2_MASK\0" + /* 186659 */ "PseudoVAMOADDEI64_WD_M2_M2_MASK\0" + /* 186691 */ "PseudoVAMOANDEI64_WD_M2_M2_MASK\0" + /* 186723 */ "PseudoVAMOMINEI64_WD_M2_M2_MASK\0" + /* 186755 */ "PseudoVAMOSWAPEI64_WD_M2_M2_MASK\0" + /* 186788 */ "PseudoVAMOOREI64_WD_M2_M2_MASK\0" + /* 186819 */ "PseudoVAMOXOREI64_WD_M2_M2_MASK\0" + /* 186851 */ "PseudoVAMOMINUEI64_WD_M2_M2_MASK\0" + /* 186884 */ "PseudoVAMOMAXUEI64_WD_M2_M2_MASK\0" + /* 186917 */ "PseudoVAMOMAXEI64_WD_M2_M2_MASK\0" + /* 186949 */ "PseudoVRGATHEREI16_VV_M2_M2_MASK\0" + /* 186982 */ "PseudoVLOXSEG2EI32_V_M2_M2_MASK\0" + /* 187014 */ "PseudoVSOXSEG2EI32_V_M2_M2_MASK\0" + /* 187046 */ "PseudoVLUXSEG2EI32_V_M2_M2_MASK\0" + /* 187078 */ "PseudoVSUXSEG2EI32_V_M2_M2_MASK\0" + /* 187110 */ "PseudoVLOXSEG3EI32_V_M2_M2_MASK\0" + /* 187142 */ "PseudoVSOXSEG3EI32_V_M2_M2_MASK\0" + /* 187174 */ "PseudoVLUXSEG3EI32_V_M2_M2_MASK\0" + /* 187206 */ "PseudoVSUXSEG3EI32_V_M2_M2_MASK\0" + /* 187238 */ "PseudoVLOXSEG4EI32_V_M2_M2_MASK\0" + /* 187270 */ "PseudoVSOXSEG4EI32_V_M2_M2_MASK\0" + /* 187302 */ "PseudoVLUXSEG4EI32_V_M2_M2_MASK\0" + /* 187334 */ "PseudoVSUXSEG4EI32_V_M2_M2_MASK\0" + /* 187366 */ "PseudoVLOXEI32_V_M2_M2_MASK\0" + /* 187394 */ "PseudoVSOXEI32_V_M2_M2_MASK\0" + /* 187422 */ "PseudoVLUXEI32_V_M2_M2_MASK\0" + /* 187450 */ "PseudoVSUXEI32_V_M2_M2_MASK\0" + /* 187478 */ "PseudoVLOXSEG2EI64_V_M2_M2_MASK\0" + /* 187510 */ "PseudoVSOXSEG2EI64_V_M2_M2_MASK\0" + /* 187542 */ "PseudoVLUXSEG2EI64_V_M2_M2_MASK\0" + /* 187574 */ "PseudoVSUXSEG2EI64_V_M2_M2_MASK\0" + /* 187606 */ "PseudoVLOXSEG3EI64_V_M2_M2_MASK\0" + /* 187638 */ "PseudoVSOXSEG3EI64_V_M2_M2_MASK\0" + /* 187670 */ "PseudoVLUXSEG3EI64_V_M2_M2_MASK\0" + /* 187702 */ "PseudoVSUXSEG3EI64_V_M2_M2_MASK\0" + /* 187734 */ "PseudoVLOXSEG4EI64_V_M2_M2_MASK\0" + /* 187766 */ "PseudoVSOXSEG4EI64_V_M2_M2_MASK\0" + /* 187798 */ "PseudoVLUXSEG4EI64_V_M2_M2_MASK\0" + /* 187830 */ "PseudoVSUXSEG4EI64_V_M2_M2_MASK\0" + /* 187862 */ "PseudoVLOXEI64_V_M2_M2_MASK\0" + /* 187890 */ "PseudoVSOXEI64_V_M2_M2_MASK\0" + /* 187918 */ "PseudoVLUXEI64_V_M2_M2_MASK\0" + /* 187946 */ "PseudoVSUXEI64_V_M2_M2_MASK\0" + /* 187974 */ "PseudoVLOXSEG2EI16_V_M2_M2_MASK\0" + /* 188006 */ "PseudoVSOXSEG2EI16_V_M2_M2_MASK\0" + /* 188038 */ "PseudoVLUXSEG2EI16_V_M2_M2_MASK\0" + /* 188070 */ "PseudoVSUXSEG2EI16_V_M2_M2_MASK\0" + /* 188102 */ "PseudoVLOXSEG3EI16_V_M2_M2_MASK\0" + /* 188134 */ "PseudoVSOXSEG3EI16_V_M2_M2_MASK\0" + /* 188166 */ "PseudoVLUXSEG3EI16_V_M2_M2_MASK\0" + /* 188198 */ "PseudoVSUXSEG3EI16_V_M2_M2_MASK\0" + /* 188230 */ "PseudoVLOXSEG4EI16_V_M2_M2_MASK\0" + /* 188262 */ "PseudoVSOXSEG4EI16_V_M2_M2_MASK\0" + /* 188294 */ "PseudoVLUXSEG4EI16_V_M2_M2_MASK\0" + /* 188326 */ "PseudoVSUXSEG4EI16_V_M2_M2_MASK\0" + /* 188358 */ "PseudoVLOXEI16_V_M2_M2_MASK\0" + /* 188386 */ "PseudoVSOXEI16_V_M2_M2_MASK\0" + /* 188414 */ "PseudoVLUXEI16_V_M2_M2_MASK\0" + /* 188442 */ "PseudoVSUXEI16_V_M2_M2_MASK\0" + /* 188470 */ "PseudoVLOXSEG2EI8_V_M2_M2_MASK\0" + /* 188501 */ "PseudoVSOXSEG2EI8_V_M2_M2_MASK\0" + /* 188532 */ "PseudoVLUXSEG2EI8_V_M2_M2_MASK\0" + /* 188563 */ "PseudoVSUXSEG2EI8_V_M2_M2_MASK\0" + /* 188594 */ "PseudoVLOXSEG3EI8_V_M2_M2_MASK\0" + /* 188625 */ "PseudoVSOXSEG3EI8_V_M2_M2_MASK\0" + /* 188656 */ "PseudoVLUXSEG3EI8_V_M2_M2_MASK\0" + /* 188687 */ "PseudoVSUXSEG3EI8_V_M2_M2_MASK\0" + /* 188718 */ "PseudoVLOXSEG4EI8_V_M2_M2_MASK\0" + /* 188749 */ "PseudoVSOXSEG4EI8_V_M2_M2_MASK\0" + /* 188780 */ "PseudoVLUXSEG4EI8_V_M2_M2_MASK\0" + /* 188811 */ "PseudoVSUXSEG4EI8_V_M2_M2_MASK\0" + /* 188842 */ "PseudoVLOXEI8_V_M2_M2_MASK\0" + /* 188869 */ "PseudoVSOXEI8_V_M2_M2_MASK\0" + /* 188896 */ "PseudoVLUXEI8_V_M2_M2_MASK\0" + /* 188923 */ "PseudoVSUXEI8_V_M2_M2_MASK\0" + /* 188950 */ "PseudoVFSUB_VF64_M2_MASK\0" + /* 188975 */ "PseudoVFMSUB_VF64_M2_MASK\0" + /* 189001 */ "PseudoVFNMSUB_VF64_M2_MASK\0" + /* 189028 */ "PseudoVFRSUB_VF64_M2_MASK\0" + /* 189054 */ "PseudoVFMSAC_VF64_M2_MASK\0" + /* 189080 */ "PseudoVFNMSAC_VF64_M2_MASK\0" + /* 189107 */ "PseudoVFMACC_VF64_M2_MASK\0" + /* 189133 */ "PseudoVFNMACC_VF64_M2_MASK\0" + /* 189160 */ "PseudoVFADD_VF64_M2_MASK\0" + /* 189185 */ "PseudoVFMADD_VF64_M2_MASK\0" + /* 189211 */ "PseudoVFNMADD_VF64_M2_MASK\0" + /* 189238 */ "PseudoVMFGE_VF64_M2_MASK\0" + /* 189263 */ "PseudoVMFLE_VF64_M2_MASK\0" + /* 189288 */ "PseudoVMFNE_VF64_M2_MASK\0" + /* 189313 */ "PseudoVFSGNJ_VF64_M2_MASK\0" + /* 189339 */ "PseudoVFMUL_VF64_M2_MASK\0" + /* 189364 */ "PseudoVFMIN_VF64_M2_MASK\0" + /* 189389 */ "PseudoVFSGNJN_VF64_M2_MASK\0" + /* 189416 */ "PseudoVFSLIDE1DOWN_VF64_M2_MASK\0" + /* 189448 */ "PseudoVFSLIDE1UP_VF64_M2_MASK\0" + /* 189478 */ "PseudoVMFEQ_VF64_M2_MASK\0" + /* 189503 */ "PseudoVMFGT_VF64_M2_MASK\0" + /* 189528 */ "PseudoVMFLT_VF64_M2_MASK\0" + /* 189553 */ "PseudoVFDIV_VF64_M2_MASK\0" + /* 189578 */ "PseudoVFRDIV_VF64_M2_MASK\0" + /* 189604 */ "PseudoVFMAX_VF64_M2_MASK\0" + /* 189629 */ "PseudoVFSGNJX_VF64_M2_MASK\0" + /* 189656 */ "PseudoVLOXSEG2EI8_V_MF4_M2_MASK\0" + /* 189688 */ "PseudoVSOXSEG2EI8_V_MF4_M2_MASK\0" + /* 189720 */ "PseudoVLUXSEG2EI8_V_MF4_M2_MASK\0" + /* 189752 */ "PseudoVSUXSEG2EI8_V_MF4_M2_MASK\0" + /* 189784 */ "PseudoVLOXSEG3EI8_V_MF4_M2_MASK\0" + /* 189816 */ "PseudoVSOXSEG3EI8_V_MF4_M2_MASK\0" + /* 189848 */ "PseudoVLUXSEG3EI8_V_MF4_M2_MASK\0" + /* 189880 */ "PseudoVSUXSEG3EI8_V_MF4_M2_MASK\0" + /* 189912 */ "PseudoVLOXSEG4EI8_V_MF4_M2_MASK\0" + /* 189944 */ "PseudoVSOXSEG4EI8_V_MF4_M2_MASK\0" + /* 189976 */ "PseudoVLUXSEG4EI8_V_MF4_M2_MASK\0" + /* 190008 */ "PseudoVSUXSEG4EI8_V_MF4_M2_MASK\0" + /* 190040 */ "PseudoVLOXEI8_V_MF4_M2_MASK\0" + /* 190068 */ "PseudoVSOXEI8_V_MF4_M2_MASK\0" + /* 190096 */ "PseudoVLUXEI8_V_MF4_M2_MASK\0" + /* 190124 */ "PseudoVSUXEI8_V_MF4_M2_MASK\0" + /* 190152 */ "PseudoVSEXT_VF4_M2_MASK\0" + /* 190176 */ "PseudoVZEXT_VF4_M2_MASK\0" + /* 190200 */ "PseudoVAMOADDEI32_WD_M4_M2_MASK\0" + /* 190232 */ "PseudoVAMOANDEI32_WD_M4_M2_MASK\0" + /* 190264 */ "PseudoVAMOMINEI32_WD_M4_M2_MASK\0" + /* 190296 */ "PseudoVAMOSWAPEI32_WD_M4_M2_MASK\0" + /* 190329 */ "PseudoVAMOOREI32_WD_M4_M2_MASK\0" + /* 190360 */ "PseudoVAMOXOREI32_WD_M4_M2_MASK\0" + /* 190392 */ "PseudoVAMOMINUEI32_WD_M4_M2_MASK\0" + /* 190425 */ "PseudoVAMOMAXUEI32_WD_M4_M2_MASK\0" + /* 190458 */ "PseudoVAMOMAXEI32_WD_M4_M2_MASK\0" + /* 190490 */ "PseudoVAMOADDEI16_WD_M4_M2_MASK\0" + /* 190522 */ "PseudoVAMOANDEI16_WD_M4_M2_MASK\0" + /* 190554 */ "PseudoVAMOMINEI16_WD_M4_M2_MASK\0" + /* 190586 */ "PseudoVAMOSWAPEI16_WD_M4_M2_MASK\0" + /* 190619 */ "PseudoVAMOOREI16_WD_M4_M2_MASK\0" + /* 190650 */ "PseudoVAMOXOREI16_WD_M4_M2_MASK\0" + /* 190682 */ "PseudoVAMOMINUEI16_WD_M4_M2_MASK\0" + /* 190715 */ "PseudoVAMOMAXUEI16_WD_M4_M2_MASK\0" + /* 190748 */ "PseudoVAMOMAXEI16_WD_M4_M2_MASK\0" + /* 190780 */ "PseudoVRGATHEREI16_VV_M4_M2_MASK\0" + /* 190813 */ "PseudoVLOXSEG2EI32_V_M4_M2_MASK\0" + /* 190845 */ "PseudoVSOXSEG2EI32_V_M4_M2_MASK\0" + /* 190877 */ "PseudoVLUXSEG2EI32_V_M4_M2_MASK\0" + /* 190909 */ "PseudoVSUXSEG2EI32_V_M4_M2_MASK\0" + /* 190941 */ "PseudoVLOXSEG3EI32_V_M4_M2_MASK\0" + /* 190973 */ "PseudoVSOXSEG3EI32_V_M4_M2_MASK\0" + /* 191005 */ "PseudoVLUXSEG3EI32_V_M4_M2_MASK\0" + /* 191037 */ "PseudoVSUXSEG3EI32_V_M4_M2_MASK\0" + /* 191069 */ "PseudoVLOXSEG4EI32_V_M4_M2_MASK\0" + /* 191101 */ "PseudoVSOXSEG4EI32_V_M4_M2_MASK\0" + /* 191133 */ "PseudoVLUXSEG4EI32_V_M4_M2_MASK\0" + /* 191165 */ "PseudoVSUXSEG4EI32_V_M4_M2_MASK\0" + /* 191197 */ "PseudoVLOXEI32_V_M4_M2_MASK\0" + /* 191225 */ "PseudoVSOXEI32_V_M4_M2_MASK\0" + /* 191253 */ "PseudoVLUXEI32_V_M4_M2_MASK\0" + /* 191281 */ "PseudoVSUXEI32_V_M4_M2_MASK\0" + /* 191309 */ "PseudoVLOXSEG2EI64_V_M4_M2_MASK\0" + /* 191341 */ "PseudoVSOXSEG2EI64_V_M4_M2_MASK\0" + /* 191373 */ "PseudoVLUXSEG2EI64_V_M4_M2_MASK\0" + /* 191405 */ "PseudoVSUXSEG2EI64_V_M4_M2_MASK\0" + /* 191437 */ "PseudoVLOXSEG3EI64_V_M4_M2_MASK\0" + /* 191469 */ "PseudoVSOXSEG3EI64_V_M4_M2_MASK\0" + /* 191501 */ "PseudoVLUXSEG3EI64_V_M4_M2_MASK\0" + /* 191533 */ "PseudoVSUXSEG3EI64_V_M4_M2_MASK\0" + /* 191565 */ "PseudoVLOXSEG4EI64_V_M4_M2_MASK\0" + /* 191597 */ "PseudoVSOXSEG4EI64_V_M4_M2_MASK\0" + /* 191629 */ "PseudoVLUXSEG4EI64_V_M4_M2_MASK\0" + /* 191661 */ "PseudoVSUXSEG4EI64_V_M4_M2_MASK\0" + /* 191693 */ "PseudoVLOXEI64_V_M4_M2_MASK\0" + /* 191721 */ "PseudoVSOXEI64_V_M4_M2_MASK\0" + /* 191749 */ "PseudoVLUXEI64_V_M4_M2_MASK\0" + /* 191777 */ "PseudoVSUXEI64_V_M4_M2_MASK\0" + /* 191805 */ "PseudoVLOXSEG2EI16_V_M4_M2_MASK\0" + /* 191837 */ "PseudoVSOXSEG2EI16_V_M4_M2_MASK\0" + /* 191869 */ "PseudoVLUXSEG2EI16_V_M4_M2_MASK\0" + /* 191901 */ "PseudoVSUXSEG2EI16_V_M4_M2_MASK\0" + /* 191933 */ "PseudoVLOXSEG3EI16_V_M4_M2_MASK\0" + /* 191965 */ "PseudoVSOXSEG3EI16_V_M4_M2_MASK\0" + /* 191997 */ "PseudoVLUXSEG3EI16_V_M4_M2_MASK\0" + /* 192029 */ "PseudoVSUXSEG3EI16_V_M4_M2_MASK\0" + /* 192061 */ "PseudoVLOXSEG4EI16_V_M4_M2_MASK\0" + /* 192093 */ "PseudoVSOXSEG4EI16_V_M4_M2_MASK\0" + /* 192125 */ "PseudoVLUXSEG4EI16_V_M4_M2_MASK\0" + /* 192157 */ "PseudoVSUXSEG4EI16_V_M4_M2_MASK\0" + /* 192189 */ "PseudoVLOXEI16_V_M4_M2_MASK\0" + /* 192217 */ "PseudoVSOXEI16_V_M4_M2_MASK\0" + /* 192245 */ "PseudoVLUXEI16_V_M4_M2_MASK\0" + /* 192273 */ "PseudoVSUXEI16_V_M4_M2_MASK\0" + /* 192301 */ "PseudoVFSUB_VF16_M2_MASK\0" + /* 192326 */ "PseudoVFMSUB_VF16_M2_MASK\0" + /* 192352 */ "PseudoVFNMSUB_VF16_M2_MASK\0" + /* 192379 */ "PseudoVFRSUB_VF16_M2_MASK\0" + /* 192405 */ "PseudoVFWSUB_VF16_M2_MASK\0" + /* 192431 */ "PseudoVFMSAC_VF16_M2_MASK\0" + /* 192457 */ "PseudoVFNMSAC_VF16_M2_MASK\0" + /* 192484 */ "PseudoVFWNMSAC_VF16_M2_MASK\0" + /* 192512 */ "PseudoVFWMSAC_VF16_M2_MASK\0" + /* 192539 */ "PseudoVFMACC_VF16_M2_MASK\0" + /* 192565 */ "PseudoVFNMACC_VF16_M2_MASK\0" + /* 192592 */ "PseudoVFWNMACC_VF16_M2_MASK\0" + /* 192620 */ "PseudoVFWMACC_VF16_M2_MASK\0" + /* 192647 */ "PseudoVFADD_VF16_M2_MASK\0" + /* 192672 */ "PseudoVFMADD_VF16_M2_MASK\0" + /* 192698 */ "PseudoVFNMADD_VF16_M2_MASK\0" + /* 192725 */ "PseudoVFWADD_VF16_M2_MASK\0" + /* 192751 */ "PseudoVMFGE_VF16_M2_MASK\0" + /* 192776 */ "PseudoVMFLE_VF16_M2_MASK\0" + /* 192801 */ "PseudoVMFNE_VF16_M2_MASK\0" + /* 192826 */ "PseudoVFSGNJ_VF16_M2_MASK\0" + /* 192852 */ "PseudoVFMUL_VF16_M2_MASK\0" + /* 192877 */ "PseudoVFWMUL_VF16_M2_MASK\0" + /* 192903 */ "PseudoVFMIN_VF16_M2_MASK\0" + /* 192928 */ "PseudoVFSGNJN_VF16_M2_MASK\0" + /* 192955 */ "PseudoVFSLIDE1DOWN_VF16_M2_MASK\0" + /* 192987 */ "PseudoVFSLIDE1UP_VF16_M2_MASK\0" + /* 193017 */ "PseudoVMFEQ_VF16_M2_MASK\0" + /* 193042 */ "PseudoVMFGT_VF16_M2_MASK\0" + /* 193067 */ "PseudoVMFLT_VF16_M2_MASK\0" + /* 193092 */ "PseudoVFDIV_VF16_M2_MASK\0" + /* 193117 */ "PseudoVFRDIV_VF16_M2_MASK\0" + /* 193143 */ "PseudoVFMAX_VF16_M2_MASK\0" + /* 193168 */ "PseudoVFSGNJX_VF16_M2_MASK\0" + /* 193195 */ "PseudoVFWSUB_WF16_M2_MASK\0" + /* 193221 */ "PseudoVFWADD_WF16_M2_MASK\0" + /* 193247 */ "PseudoVSEXT_VF8_M2_MASK\0" + /* 193271 */ "PseudoVZEXT_VF8_M2_MASK\0" + /* 193295 */ "PseudoVAMOADDEI16_WD_M8_M2_MASK\0" + /* 193327 */ "PseudoVAMOANDEI16_WD_M8_M2_MASK\0" + /* 193359 */ "PseudoVAMOMINEI16_WD_M8_M2_MASK\0" + /* 193391 */ "PseudoVAMOSWAPEI16_WD_M8_M2_MASK\0" + /* 193424 */ "PseudoVAMOOREI16_WD_M8_M2_MASK\0" + /* 193455 */ "PseudoVAMOXOREI16_WD_M8_M2_MASK\0" + /* 193487 */ "PseudoVAMOMINUEI16_WD_M8_M2_MASK\0" + /* 193520 */ "PseudoVAMOMAXUEI16_WD_M8_M2_MASK\0" + /* 193553 */ "PseudoVAMOMAXEI16_WD_M8_M2_MASK\0" + /* 193585 */ "PseudoVAMOADDEI8_WD_M8_M2_MASK\0" + /* 193616 */ "PseudoVAMOANDEI8_WD_M8_M2_MASK\0" + /* 193647 */ "PseudoVAMOMINEI8_WD_M8_M2_MASK\0" + /* 193678 */ "PseudoVAMOSWAPEI8_WD_M8_M2_MASK\0" + /* 193710 */ "PseudoVAMOOREI8_WD_M8_M2_MASK\0" + /* 193740 */ "PseudoVAMOXOREI8_WD_M8_M2_MASK\0" + /* 193771 */ "PseudoVAMOMINUEI8_WD_M8_M2_MASK\0" + /* 193803 */ "PseudoVAMOMAXUEI8_WD_M8_M2_MASK\0" + /* 193835 */ "PseudoVAMOMAXEI8_WD_M8_M2_MASK\0" + /* 193866 */ "PseudoVRGATHEREI16_VV_M8_M2_MASK\0" + /* 193899 */ "PseudoVLOXSEG2EI32_V_M8_M2_MASK\0" + /* 193931 */ "PseudoVSOXSEG2EI32_V_M8_M2_MASK\0" + /* 193963 */ "PseudoVLUXSEG2EI32_V_M8_M2_MASK\0" + /* 193995 */ "PseudoVSUXSEG2EI32_V_M8_M2_MASK\0" + /* 194027 */ "PseudoVLOXSEG3EI32_V_M8_M2_MASK\0" + /* 194059 */ "PseudoVSOXSEG3EI32_V_M8_M2_MASK\0" + /* 194091 */ "PseudoVLUXSEG3EI32_V_M8_M2_MASK\0" + /* 194123 */ "PseudoVSUXSEG3EI32_V_M8_M2_MASK\0" + /* 194155 */ "PseudoVLOXSEG4EI32_V_M8_M2_MASK\0" + /* 194187 */ "PseudoVSOXSEG4EI32_V_M8_M2_MASK\0" + /* 194219 */ "PseudoVLUXSEG4EI32_V_M8_M2_MASK\0" + /* 194251 */ "PseudoVSUXSEG4EI32_V_M8_M2_MASK\0" + /* 194283 */ "PseudoVLOXEI32_V_M8_M2_MASK\0" + /* 194311 */ "PseudoVSOXEI32_V_M8_M2_MASK\0" + /* 194339 */ "PseudoVLUXEI32_V_M8_M2_MASK\0" + /* 194367 */ "PseudoVSUXEI32_V_M8_M2_MASK\0" + /* 194395 */ "PseudoVLOXSEG2EI64_V_M8_M2_MASK\0" + /* 194427 */ "PseudoVSOXSEG2EI64_V_M8_M2_MASK\0" + /* 194459 */ "PseudoVLUXSEG2EI64_V_M8_M2_MASK\0" + /* 194491 */ "PseudoVSUXSEG2EI64_V_M8_M2_MASK\0" + /* 194523 */ "PseudoVLOXSEG3EI64_V_M8_M2_MASK\0" + /* 194555 */ "PseudoVSOXSEG3EI64_V_M8_M2_MASK\0" + /* 194587 */ "PseudoVLUXSEG3EI64_V_M8_M2_MASK\0" + /* 194619 */ "PseudoVSUXSEG3EI64_V_M8_M2_MASK\0" + /* 194651 */ "PseudoVLOXSEG4EI64_V_M8_M2_MASK\0" + /* 194683 */ "PseudoVSOXSEG4EI64_V_M8_M2_MASK\0" + /* 194715 */ "PseudoVLUXSEG4EI64_V_M8_M2_MASK\0" + /* 194747 */ "PseudoVSUXSEG4EI64_V_M8_M2_MASK\0" + /* 194779 */ "PseudoVLOXEI64_V_M8_M2_MASK\0" + /* 194807 */ "PseudoVSOXEI64_V_M8_M2_MASK\0" + /* 194835 */ "PseudoVLUXEI64_V_M8_M2_MASK\0" + /* 194863 */ "PseudoVSUXEI64_V_M8_M2_MASK\0" + /* 194891 */ "PseudoVSSRA_VI_M2_MASK\0" + /* 194914 */ "PseudoVSRA_VI_M2_MASK\0" + /* 194936 */ "PseudoVRSUB_VI_M2_MASK\0" + /* 194959 */ "PseudoVSADD_VI_M2_MASK\0" + /* 194982 */ "PseudoVADD_VI_M2_MASK\0" + /* 195004 */ "PseudoVAND_VI_M2_MASK\0" + /* 195026 */ "PseudoVMSLE_VI_M2_MASK\0" + /* 195049 */ "PseudoVMSNE_VI_M2_MASK\0" + /* 195072 */ "PseudoVSLL_VI_M2_MASK\0" + /* 195094 */ "PseudoVSSRL_VI_M2_MASK\0" + /* 195117 */ "PseudoVSRL_VI_M2_MASK\0" + /* 195139 */ "PseudoVSLIDEDOWN_VI_M2_MASK\0" + /* 195167 */ "PseudoVSLIDEUP_VI_M2_MASK\0" + /* 195193 */ "PseudoVMSEQ_VI_M2_MASK\0" + /* 195216 */ "PseudoVRGATHER_VI_M2_MASK\0" + /* 195242 */ "PseudoVOR_VI_M2_MASK\0" + /* 195263 */ "PseudoVXOR_VI_M2_MASK\0" + /* 195285 */ "PseudoVMSGT_VI_M2_MASK\0" + /* 195308 */ "PseudoVSADDU_VI_M2_MASK\0" + /* 195332 */ "PseudoVMSLEU_VI_M2_MASK\0" + /* 195356 */ "PseudoVMSGTU_VI_M2_MASK\0" + /* 195380 */ "PseudoVNSRA_WI_M2_MASK\0" + /* 195403 */ "PseudoVNSRL_WI_M2_MASK\0" + /* 195426 */ "PseudoVNCLIP_WI_M2_MASK\0" + /* 195450 */ "PseudoVNCLIPU_WI_M2_MASK\0" + /* 195475 */ "PseudoVIOTA_M_M2_MASK\0" + /* 195497 */ "PseudoVREDAND_VS_M2_MASK\0" + /* 195522 */ "PseudoVREDSUM_VS_M2_MASK\0" + /* 195547 */ "PseudoVWREDSUM_VS_M2_MASK\0" + /* 195573 */ "PseudoVFREDOSUM_VS_M2_MASK\0" + /* 195600 */ "PseudoVFWREDOSUM_VS_M2_MASK\0" + /* 195628 */ "PseudoVFREDUSUM_VS_M2_MASK\0" + /* 195655 */ "PseudoVFWREDUSUM_VS_M2_MASK\0" + /* 195683 */ "PseudoVFREDMIN_VS_M2_MASK\0" + /* 195709 */ "PseudoVREDMIN_VS_M2_MASK\0" + /* 195734 */ "PseudoVREDOR_VS_M2_MASK\0" + /* 195758 */ "PseudoVREDXOR_VS_M2_MASK\0" + /* 195783 */ "PseudoVWREDSUMU_VS_M2_MASK\0" + /* 195810 */ "PseudoVREDMINU_VS_M2_MASK\0" + /* 195836 */ "PseudoVREDMAXU_VS_M2_MASK\0" + /* 195862 */ "PseudoVFREDMAX_VS_M2_MASK\0" + /* 195888 */ "PseudoVREDMAX_VS_M2_MASK\0" + /* 195913 */ "PseudoVSSRA_VV_M2_MASK\0" + /* 195936 */ "PseudoVSRA_VV_M2_MASK\0" + /* 195958 */ "PseudoVASUB_VV_M2_MASK\0" + /* 195981 */ "PseudoVFSUB_VV_M2_MASK\0" + /* 196004 */ "PseudoVFMSUB_VV_M2_MASK\0" + /* 196028 */ "PseudoVFNMSUB_VV_M2_MASK\0" + /* 196053 */ "PseudoVNMSUB_VV_M2_MASK\0" + /* 196077 */ "PseudoVSSUB_VV_M2_MASK\0" + /* 196100 */ "PseudoVSUB_VV_M2_MASK\0" + /* 196122 */ "PseudoVFWSUB_VV_M2_MASK\0" + /* 196146 */ "PseudoVWSUB_VV_M2_MASK\0" + /* 196169 */ "PseudoVFMSAC_VV_M2_MASK\0" + /* 196193 */ "PseudoVFNMSAC_VV_M2_MASK\0" + /* 196218 */ "PseudoVNMSAC_VV_M2_MASK\0" + /* 196242 */ "PseudoVFWNMSAC_VV_M2_MASK\0" + /* 196268 */ "PseudoVFWMSAC_VV_M2_MASK\0" + /* 196293 */ "PseudoVFMACC_VV_M2_MASK\0" + /* 196317 */ "PseudoVFNMACC_VV_M2_MASK\0" + /* 196342 */ "PseudoVFWNMACC_VV_M2_MASK\0" + /* 196368 */ "PseudoVMACC_VV_M2_MASK\0" + /* 196391 */ "PseudoVFWMACC_VV_M2_MASK\0" + /* 196416 */ "PseudoVWMACC_VV_M2_MASK\0" + /* 196440 */ "PseudoVAADD_VV_M2_MASK\0" + /* 196463 */ "PseudoVFADD_VV_M2_MASK\0" + /* 196486 */ "PseudoVFMADD_VV_M2_MASK\0" + /* 196510 */ "PseudoVFNMADD_VV_M2_MASK\0" + /* 196535 */ "PseudoVMADD_VV_M2_MASK\0" + /* 196558 */ "PseudoVSADD_VV_M2_MASK\0" + /* 196581 */ "PseudoVADD_VV_M2_MASK\0" + /* 196603 */ "PseudoVFWADD_VV_M2_MASK\0" + /* 196627 */ "PseudoVWADD_VV_M2_MASK\0" + /* 196650 */ "PseudoVAND_VV_M2_MASK\0" + /* 196672 */ "PseudoVMFLE_VV_M2_MASK\0" + /* 196695 */ "PseudoVMSLE_VV_M2_MASK\0" + /* 196718 */ "PseudoVMFNE_VV_M2_MASK\0" + /* 196741 */ "PseudoVMSNE_VV_M2_MASK\0" + /* 196764 */ "PseudoVMULH_VV_M2_MASK\0" + /* 196787 */ "PseudoVFSGNJ_VV_M2_MASK\0" + /* 196811 */ "PseudoVSLL_VV_M2_MASK\0" + /* 196833 */ "PseudoVSSRL_VV_M2_MASK\0" + /* 196856 */ "PseudoVSRL_VV_M2_MASK\0" + /* 196878 */ "PseudoVFMUL_VV_M2_MASK\0" + /* 196901 */ "PseudoVSMUL_VV_M2_MASK\0" + /* 196924 */ "PseudoVMUL_VV_M2_MASK\0" + /* 196946 */ "PseudoVFWMUL_VV_M2_MASK\0" + /* 196970 */ "PseudoVWMUL_VV_M2_MASK\0" + /* 196993 */ "PseudoVREM_VV_M2_MASK\0" + /* 197015 */ "PseudoVFMIN_VV_M2_MASK\0" + /* 197038 */ "PseudoVMIN_VV_M2_MASK\0" + /* 197060 */ "PseudoVFSGNJN_VV_M2_MASK\0" + /* 197085 */ "PseudoVMFEQ_VV_M2_MASK\0" + /* 197108 */ "PseudoVMSEQ_VV_M2_MASK\0" + /* 197131 */ "PseudoVRGATHER_VV_M2_MASK\0" + /* 197157 */ "PseudoVOR_VV_M2_MASK\0" + /* 197178 */ "PseudoVXOR_VV_M2_MASK\0" + /* 197200 */ "PseudoVMFLT_VV_M2_MASK\0" + /* 197223 */ "PseudoVMSLT_VV_M2_MASK\0" + /* 197246 */ "PseudoVASUBU_VV_M2_MASK\0" + /* 197270 */ "PseudoVSSUBU_VV_M2_MASK\0" + /* 197294 */ "PseudoVWSUBU_VV_M2_MASK\0" + /* 197318 */ "PseudoVWMACCU_VV_M2_MASK\0" + /* 197343 */ "PseudoVAADDU_VV_M2_MASK\0" + /* 197367 */ "PseudoVSADDU_VV_M2_MASK\0" + /* 197391 */ "PseudoVWADDU_VV_M2_MASK\0" + /* 197415 */ "PseudoVMSLEU_VV_M2_MASK\0" + /* 197439 */ "PseudoVMULHU_VV_M2_MASK\0" + /* 197463 */ "PseudoVWMULU_VV_M2_MASK\0" + /* 197487 */ "PseudoVREMU_VV_M2_MASK\0" + /* 197510 */ "PseudoVMINU_VV_M2_MASK\0" + /* 197533 */ "PseudoVWMACCSU_VV_M2_MASK\0" + /* 197559 */ "PseudoVMULHSU_VV_M2_MASK\0" + /* 197584 */ "PseudoVWMULSU_VV_M2_MASK\0" + /* 197609 */ "PseudoVMSLTU_VV_M2_MASK\0" + /* 197633 */ "PseudoVDIVU_VV_M2_MASK\0" + /* 197656 */ "PseudoVMAXU_VV_M2_MASK\0" + /* 197679 */ "PseudoVFDIV_VV_M2_MASK\0" + /* 197702 */ "PseudoVDIV_VV_M2_MASK\0" + /* 197724 */ "PseudoVFMAX_VV_M2_MASK\0" + /* 197747 */ "PseudoVMAX_VV_M2_MASK\0" + /* 197769 */ "PseudoVFSGNJX_VV_M2_MASK\0" + /* 197794 */ "PseudoVNSRA_WV_M2_MASK\0" + /* 197817 */ "PseudoVFWSUB_WV_M2_MASK\0" + /* 197841 */ "PseudoVWSUB_WV_M2_MASK\0" + /* 197864 */ "PseudoVFWADD_WV_M2_MASK\0" + /* 197888 */ "PseudoVWADD_WV_M2_MASK\0" + /* 197911 */ "PseudoVNSRL_WV_M2_MASK\0" + /* 197934 */ "PseudoVNCLIP_WV_M2_MASK\0" + /* 197958 */ "PseudoVWSUBU_WV_M2_MASK\0" + /* 197982 */ "PseudoVWADDU_WV_M2_MASK\0" + /* 198006 */ "PseudoVNCLIPU_WV_M2_MASK\0" + /* 198031 */ "PseudoVLSEG2E32_V_M2_MASK\0" + /* 198057 */ "PseudoVLSSEG2E32_V_M2_MASK\0" + /* 198084 */ "PseudoVSSSEG2E32_V_M2_MASK\0" + /* 198111 */ "PseudoVSSEG2E32_V_M2_MASK\0" + /* 198137 */ "PseudoVLSEG3E32_V_M2_MASK\0" + /* 198163 */ "PseudoVLSSEG3E32_V_M2_MASK\0" + /* 198190 */ "PseudoVSSSEG3E32_V_M2_MASK\0" + /* 198217 */ "PseudoVSSEG3E32_V_M2_MASK\0" + /* 198243 */ "PseudoVLSEG4E32_V_M2_MASK\0" + /* 198269 */ "PseudoVLSSEG4E32_V_M2_MASK\0" + /* 198296 */ "PseudoVSSSEG4E32_V_M2_MASK\0" + /* 198323 */ "PseudoVSSEG4E32_V_M2_MASK\0" + /* 198349 */ "PseudoVLE32_V_M2_MASK\0" + /* 198371 */ "PseudoVLSE32_V_M2_MASK\0" + /* 198394 */ "PseudoVSSE32_V_M2_MASK\0" + /* 198417 */ "PseudoVSE32_V_M2_MASK\0" + /* 198439 */ "PseudoVLSEG2E64_V_M2_MASK\0" + /* 198465 */ "PseudoVLSSEG2E64_V_M2_MASK\0" + /* 198492 */ "PseudoVSSSEG2E64_V_M2_MASK\0" + /* 198519 */ "PseudoVSSEG2E64_V_M2_MASK\0" + /* 198545 */ "PseudoVLSEG3E64_V_M2_MASK\0" + /* 198571 */ "PseudoVLSSEG3E64_V_M2_MASK\0" + /* 198598 */ "PseudoVSSSEG3E64_V_M2_MASK\0" + /* 198625 */ "PseudoVSSEG3E64_V_M2_MASK\0" + /* 198651 */ "PseudoVLSEG4E64_V_M2_MASK\0" + /* 198677 */ "PseudoVLSSEG4E64_V_M2_MASK\0" + /* 198704 */ "PseudoVSSSEG4E64_V_M2_MASK\0" + /* 198731 */ "PseudoVSSEG4E64_V_M2_MASK\0" + /* 198757 */ "PseudoVLE64_V_M2_MASK\0" + /* 198779 */ "PseudoVLSE64_V_M2_MASK\0" + /* 198802 */ "PseudoVSSE64_V_M2_MASK\0" + /* 198825 */ "PseudoVSE64_V_M2_MASK\0" + /* 198847 */ "PseudoVLSEG2E16_V_M2_MASK\0" + /* 198873 */ "PseudoVLSSEG2E16_V_M2_MASK\0" + /* 198900 */ "PseudoVSSSEG2E16_V_M2_MASK\0" + /* 198927 */ "PseudoVSSEG2E16_V_M2_MASK\0" + /* 198953 */ "PseudoVLSEG3E16_V_M2_MASK\0" + /* 198979 */ "PseudoVLSSEG3E16_V_M2_MASK\0" + /* 199006 */ "PseudoVSSSEG3E16_V_M2_MASK\0" + /* 199033 */ "PseudoVSSEG3E16_V_M2_MASK\0" + /* 199059 */ "PseudoVLSEG4E16_V_M2_MASK\0" + /* 199085 */ "PseudoVLSSEG4E16_V_M2_MASK\0" + /* 199112 */ "PseudoVSSSEG4E16_V_M2_MASK\0" + /* 199139 */ "PseudoVSSEG4E16_V_M2_MASK\0" + /* 199165 */ "PseudoVLE16_V_M2_MASK\0" + /* 199187 */ "PseudoVLSE16_V_M2_MASK\0" + /* 199210 */ "PseudoVSSE16_V_M2_MASK\0" + /* 199233 */ "PseudoVSE16_V_M2_MASK\0" + /* 199255 */ "PseudoVFREC7_V_M2_MASK\0" + /* 199278 */ "PseudoVFRSQRT7_V_M2_MASK\0" + /* 199303 */ "PseudoVLSEG2E8_V_M2_MASK\0" + /* 199328 */ "PseudoVLSSEG2E8_V_M2_MASK\0" + /* 199354 */ "PseudoVSSSEG2E8_V_M2_MASK\0" + /* 199380 */ "PseudoVSSEG2E8_V_M2_MASK\0" + /* 199405 */ "PseudoVLSEG3E8_V_M2_MASK\0" + /* 199430 */ "PseudoVLSSEG3E8_V_M2_MASK\0" + /* 199456 */ "PseudoVSSSEG3E8_V_M2_MASK\0" + /* 199482 */ "PseudoVSSEG3E8_V_M2_MASK\0" + /* 199507 */ "PseudoVLSEG4E8_V_M2_MASK\0" + /* 199532 */ "PseudoVLSSEG4E8_V_M2_MASK\0" + /* 199558 */ "PseudoVSSSEG4E8_V_M2_MASK\0" + /* 199584 */ "PseudoVSSEG4E8_V_M2_MASK\0" + /* 199609 */ "PseudoVLE8_V_M2_MASK\0" + /* 199630 */ "PseudoVLSE8_V_M2_MASK\0" + /* 199652 */ "PseudoVSSE8_V_M2_MASK\0" + /* 199674 */ "PseudoVSE8_V_M2_MASK\0" + /* 199695 */ "PseudoVID_V_M2_MASK\0" + /* 199715 */ "PseudoVLSEG2E32FF_V_M2_MASK\0" + /* 199743 */ "PseudoVLSEG3E32FF_V_M2_MASK\0" + /* 199771 */ "PseudoVLSEG4E32FF_V_M2_MASK\0" + /* 199799 */ "PseudoVLE32FF_V_M2_MASK\0" + /* 199823 */ "PseudoVLSEG2E64FF_V_M2_MASK\0" + /* 199851 */ "PseudoVLSEG3E64FF_V_M2_MASK\0" + /* 199879 */ "PseudoVLSEG4E64FF_V_M2_MASK\0" + /* 199907 */ "PseudoVLE64FF_V_M2_MASK\0" + /* 199931 */ "PseudoVLSEG2E16FF_V_M2_MASK\0" + /* 199959 */ "PseudoVLSEG3E16FF_V_M2_MASK\0" + /* 199987 */ "PseudoVLSEG4E16FF_V_M2_MASK\0" + /* 200015 */ "PseudoVLE16FF_V_M2_MASK\0" + /* 200039 */ "PseudoVLSEG2E8FF_V_M2_MASK\0" + /* 200066 */ "PseudoVLSEG3E8FF_V_M2_MASK\0" + /* 200093 */ "PseudoVLSEG4E8FF_V_M2_MASK\0" + /* 200120 */ "PseudoVLE8FF_V_M2_MASK\0" + /* 200143 */ "PseudoVFWCVT_F_F_V_M2_MASK\0" + /* 200170 */ "PseudoVFCVT_XU_F_V_M2_MASK\0" + /* 200197 */ "PseudoVFWCVT_XU_F_V_M2_MASK\0" + /* 200225 */ "PseudoVFCVT_RTZ_XU_F_V_M2_MASK\0" + /* 200256 */ "PseudoVFWCVT_RTZ_XU_F_V_M2_MASK\0" + /* 200288 */ "PseudoVFCVT_X_F_V_M2_MASK\0" + /* 200314 */ "PseudoVFWCVT_X_F_V_M2_MASK\0" + /* 200341 */ "PseudoVFCVT_RTZ_X_F_V_M2_MASK\0" + /* 200371 */ "PseudoVFWCVT_RTZ_X_F_V_M2_MASK\0" + /* 200402 */ "PseudoVFCLASS_V_M2_MASK\0" + /* 200426 */ "PseudoVFSQRT_V_M2_MASK\0" + /* 200449 */ "PseudoVFCVT_F_XU_V_M2_MASK\0" + /* 200476 */ "PseudoVFWCVT_F_XU_V_M2_MASK\0" + /* 200504 */ "PseudoVFCVT_F_X_V_M2_MASK\0" + /* 200530 */ "PseudoVFWCVT_F_X_V_M2_MASK\0" + /* 200557 */ "PseudoVFNCVT_ROD_F_F_W_M2_MASK\0" + /* 200588 */ "PseudoVFNCVT_F_F_W_M2_MASK\0" + /* 200615 */ "PseudoVFNCVT_XU_F_W_M2_MASK\0" + /* 200643 */ "PseudoVFNCVT_RTZ_XU_F_W_M2_MASK\0" + /* 200675 */ "PseudoVFNCVT_X_F_W_M2_MASK\0" + /* 200702 */ "PseudoVFNCVT_RTZ_X_F_W_M2_MASK\0" + /* 200733 */ "PseudoVFNCVT_F_XU_W_M2_MASK\0" + /* 200761 */ "PseudoVFNCVT_F_X_W_M2_MASK\0" + /* 200788 */ "PseudoVSSRA_VX_M2_MASK\0" + /* 200811 */ "PseudoVSRA_VX_M2_MASK\0" + /* 200833 */ "PseudoVASUB_VX_M2_MASK\0" + /* 200856 */ "PseudoVNMSUB_VX_M2_MASK\0" + /* 200880 */ "PseudoVRSUB_VX_M2_MASK\0" + /* 200903 */ "PseudoVSSUB_VX_M2_MASK\0" + /* 200926 */ "PseudoVSUB_VX_M2_MASK\0" + /* 200948 */ "PseudoVWSUB_VX_M2_MASK\0" + /* 200971 */ "PseudoVNMSAC_VX_M2_MASK\0" + /* 200995 */ "PseudoVMACC_VX_M2_MASK\0" + /* 201018 */ "PseudoVWMACC_VX_M2_MASK\0" + /* 201042 */ "PseudoVAADD_VX_M2_MASK\0" + /* 201065 */ "PseudoVMADD_VX_M2_MASK\0" + /* 201088 */ "PseudoVSADD_VX_M2_MASK\0" + /* 201111 */ "PseudoVADD_VX_M2_MASK\0" + /* 201133 */ "PseudoVWADD_VX_M2_MASK\0" + /* 201156 */ "PseudoVAND_VX_M2_MASK\0" + /* 201178 */ "PseudoVMSLE_VX_M2_MASK\0" + /* 201201 */ "PseudoVMSNE_VX_M2_MASK\0" + /* 201224 */ "PseudoVMULH_VX_M2_MASK\0" + /* 201247 */ "PseudoVSLL_VX_M2_MASK\0" + /* 201269 */ "PseudoVSSRL_VX_M2_MASK\0" + /* 201292 */ "PseudoVSRL_VX_M2_MASK\0" + /* 201314 */ "PseudoVSMUL_VX_M2_MASK\0" + /* 201337 */ "PseudoVMUL_VX_M2_MASK\0" + /* 201359 */ "PseudoVWMUL_VX_M2_MASK\0" + /* 201382 */ "PseudoVREM_VX_M2_MASK\0" + /* 201404 */ "PseudoVMIN_VX_M2_MASK\0" + /* 201426 */ "PseudoVSLIDE1DOWN_VX_M2_MASK\0" + /* 201455 */ "PseudoVSLIDEDOWN_VX_M2_MASK\0" + /* 201483 */ "PseudoVSLIDE1UP_VX_M2_MASK\0" + /* 201510 */ "PseudoVSLIDEUP_VX_M2_MASK\0" + /* 201536 */ "PseudoVMSEQ_VX_M2_MASK\0" + /* 201559 */ "PseudoVRGATHER_VX_M2_MASK\0" + /* 201585 */ "PseudoVOR_VX_M2_MASK\0" + /* 201606 */ "PseudoVXOR_VX_M2_MASK\0" + /* 201628 */ "PseudoVWMACCUS_VX_M2_MASK\0" + /* 201654 */ "PseudoVMSGT_VX_M2_MASK\0" + /* 201677 */ "PseudoVMSLT_VX_M2_MASK\0" + /* 201700 */ "PseudoVASUBU_VX_M2_MASK\0" + /* 201724 */ "PseudoVSSUBU_VX_M2_MASK\0" + /* 201748 */ "PseudoVWSUBU_VX_M2_MASK\0" + /* 201772 */ "PseudoVWMACCU_VX_M2_MASK\0" + /* 201797 */ "PseudoVAADDU_VX_M2_MASK\0" + /* 201821 */ "PseudoVSADDU_VX_M2_MASK\0" + /* 201845 */ "PseudoVWADDU_VX_M2_MASK\0" + /* 201869 */ "PseudoVMSLEU_VX_M2_MASK\0" + /* 201893 */ "PseudoVMULHU_VX_M2_MASK\0" + /* 201917 */ "PseudoVWMULU_VX_M2_MASK\0" + /* 201941 */ "PseudoVREMU_VX_M2_MASK\0" + /* 201964 */ "PseudoVMINU_VX_M2_MASK\0" + /* 201987 */ "PseudoVWMACCSU_VX_M2_MASK\0" + /* 202013 */ "PseudoVMULHSU_VX_M2_MASK\0" + /* 202038 */ "PseudoVWMULSU_VX_M2_MASK\0" + /* 202063 */ "PseudoVMSGTU_VX_M2_MASK\0" + /* 202087 */ "PseudoVMSLTU_VX_M2_MASK\0" + /* 202111 */ "PseudoVDIVU_VX_M2_MASK\0" + /* 202134 */ "PseudoVMAXU_VX_M2_MASK\0" + /* 202157 */ "PseudoVDIV_VX_M2_MASK\0" + /* 202179 */ "PseudoVMAX_VX_M2_MASK\0" + /* 202201 */ "PseudoVNSRA_WX_M2_MASK\0" + /* 202224 */ "PseudoVWSUB_WX_M2_MASK\0" + /* 202247 */ "PseudoVWADD_WX_M2_MASK\0" + /* 202270 */ "PseudoVNSRL_WX_M2_MASK\0" + /* 202293 */ "PseudoVNCLIP_WX_M2_MASK\0" + /* 202317 */ "PseudoVWSUBU_WX_M2_MASK\0" + /* 202341 */ "PseudoVWADDU_WX_M2_MASK\0" + /* 202365 */ "PseudoVNCLIPU_WX_M2_MASK\0" + /* 202390 */ "PseudoVMSBF_M_B64_MASK\0" + /* 202413 */ "PseudoVMSIF_M_B64_MASK\0" + /* 202436 */ "PseudoVMSOF_M_B64_MASK\0" + /* 202459 */ "PseudoVCPOP_M_B64_MASK\0" + /* 202482 */ "PseudoVFIRST_M_B64_MASK\0" + /* 202506 */ "PseudoVMSBF_M_B4_MASK\0" + /* 202528 */ "PseudoVMSIF_M_B4_MASK\0" + /* 202550 */ "PseudoVMSOF_M_B4_MASK\0" + /* 202572 */ "PseudoVCPOP_M_B4_MASK\0" + /* 202594 */ "PseudoVFIRST_M_B4_MASK\0" + /* 202617 */ "PseudoVAMOADDEI16_WD_M1_MF4_MASK\0" + /* 202650 */ "PseudoVAMOANDEI16_WD_M1_MF4_MASK\0" + /* 202683 */ "PseudoVAMOMINEI16_WD_M1_MF4_MASK\0" + /* 202716 */ "PseudoVAMOSWAPEI16_WD_M1_MF4_MASK\0" + /* 202750 */ "PseudoVAMOOREI16_WD_M1_MF4_MASK\0" + /* 202782 */ "PseudoVAMOXOREI16_WD_M1_MF4_MASK\0" + /* 202815 */ "PseudoVAMOMINUEI16_WD_M1_MF4_MASK\0" + /* 202849 */ "PseudoVAMOMAXUEI16_WD_M1_MF4_MASK\0" + /* 202883 */ "PseudoVAMOMAXEI16_WD_M1_MF4_MASK\0" + /* 202916 */ "PseudoVAMOADDEI8_WD_M1_MF4_MASK\0" + /* 202948 */ "PseudoVAMOANDEI8_WD_M1_MF4_MASK\0" + /* 202980 */ "PseudoVAMOMINEI8_WD_M1_MF4_MASK\0" + /* 203012 */ "PseudoVAMOSWAPEI8_WD_M1_MF4_MASK\0" + /* 203045 */ "PseudoVAMOOREI8_WD_M1_MF4_MASK\0" + /* 203076 */ "PseudoVAMOXOREI8_WD_M1_MF4_MASK\0" + /* 203108 */ "PseudoVAMOMINUEI8_WD_M1_MF4_MASK\0" + /* 203141 */ "PseudoVAMOMAXUEI8_WD_M1_MF4_MASK\0" + /* 203174 */ "PseudoVAMOMAXEI8_WD_M1_MF4_MASK\0" + /* 203206 */ "PseudoVRGATHEREI16_VV_M1_MF4_MASK\0" + /* 203240 */ "PseudoVLOXSEG2EI32_V_M1_MF4_MASK\0" + /* 203273 */ "PseudoVSOXSEG2EI32_V_M1_MF4_MASK\0" + /* 203306 */ "PseudoVLUXSEG2EI32_V_M1_MF4_MASK\0" + /* 203339 */ "PseudoVSUXSEG2EI32_V_M1_MF4_MASK\0" + /* 203372 */ "PseudoVLOXSEG3EI32_V_M1_MF4_MASK\0" + /* 203405 */ "PseudoVSOXSEG3EI32_V_M1_MF4_MASK\0" + /* 203438 */ "PseudoVLUXSEG3EI32_V_M1_MF4_MASK\0" + /* 203471 */ "PseudoVSUXSEG3EI32_V_M1_MF4_MASK\0" + /* 203504 */ "PseudoVLOXSEG4EI32_V_M1_MF4_MASK\0" + /* 203537 */ "PseudoVSOXSEG4EI32_V_M1_MF4_MASK\0" + /* 203570 */ "PseudoVLUXSEG4EI32_V_M1_MF4_MASK\0" + /* 203603 */ "PseudoVSUXSEG4EI32_V_M1_MF4_MASK\0" + /* 203636 */ "PseudoVLOXSEG5EI32_V_M1_MF4_MASK\0" + /* 203669 */ "PseudoVSOXSEG5EI32_V_M1_MF4_MASK\0" + /* 203702 */ "PseudoVLUXSEG5EI32_V_M1_MF4_MASK\0" + /* 203735 */ "PseudoVSUXSEG5EI32_V_M1_MF4_MASK\0" + /* 203768 */ "PseudoVLOXSEG6EI32_V_M1_MF4_MASK\0" + /* 203801 */ "PseudoVSOXSEG6EI32_V_M1_MF4_MASK\0" + /* 203834 */ "PseudoVLUXSEG6EI32_V_M1_MF4_MASK\0" + /* 203867 */ "PseudoVSUXSEG6EI32_V_M1_MF4_MASK\0" + /* 203900 */ "PseudoVLOXSEG7EI32_V_M1_MF4_MASK\0" + /* 203933 */ "PseudoVSOXSEG7EI32_V_M1_MF4_MASK\0" + /* 203966 */ "PseudoVLUXSEG7EI32_V_M1_MF4_MASK\0" + /* 203999 */ "PseudoVSUXSEG7EI32_V_M1_MF4_MASK\0" + /* 204032 */ "PseudoVLOXSEG8EI32_V_M1_MF4_MASK\0" + /* 204065 */ "PseudoVSOXSEG8EI32_V_M1_MF4_MASK\0" + /* 204098 */ "PseudoVLUXSEG8EI32_V_M1_MF4_MASK\0" + /* 204131 */ "PseudoVSUXSEG8EI32_V_M1_MF4_MASK\0" + /* 204164 */ "PseudoVLOXEI32_V_M1_MF4_MASK\0" + /* 204193 */ "PseudoVSOXEI32_V_M1_MF4_MASK\0" + /* 204222 */ "PseudoVLUXEI32_V_M1_MF4_MASK\0" + /* 204251 */ "PseudoVSUXEI32_V_M1_MF4_MASK\0" + /* 204280 */ "PseudoVLOXSEG2EI64_V_M1_MF4_MASK\0" + /* 204313 */ "PseudoVSOXSEG2EI64_V_M1_MF4_MASK\0" + /* 204346 */ "PseudoVLUXSEG2EI64_V_M1_MF4_MASK\0" + /* 204379 */ "PseudoVSUXSEG2EI64_V_M1_MF4_MASK\0" + /* 204412 */ "PseudoVLOXSEG3EI64_V_M1_MF4_MASK\0" + /* 204445 */ "PseudoVSOXSEG3EI64_V_M1_MF4_MASK\0" + /* 204478 */ "PseudoVLUXSEG3EI64_V_M1_MF4_MASK\0" + /* 204511 */ "PseudoVSUXSEG3EI64_V_M1_MF4_MASK\0" + /* 204544 */ "PseudoVLOXSEG4EI64_V_M1_MF4_MASK\0" + /* 204577 */ "PseudoVSOXSEG4EI64_V_M1_MF4_MASK\0" + /* 204610 */ "PseudoVLUXSEG4EI64_V_M1_MF4_MASK\0" + /* 204643 */ "PseudoVSUXSEG4EI64_V_M1_MF4_MASK\0" + /* 204676 */ "PseudoVLOXSEG5EI64_V_M1_MF4_MASK\0" + /* 204709 */ "PseudoVSOXSEG5EI64_V_M1_MF4_MASK\0" + /* 204742 */ "PseudoVLUXSEG5EI64_V_M1_MF4_MASK\0" + /* 204775 */ "PseudoVSUXSEG5EI64_V_M1_MF4_MASK\0" + /* 204808 */ "PseudoVLOXSEG6EI64_V_M1_MF4_MASK\0" + /* 204841 */ "PseudoVSOXSEG6EI64_V_M1_MF4_MASK\0" + /* 204874 */ "PseudoVLUXSEG6EI64_V_M1_MF4_MASK\0" + /* 204907 */ "PseudoVSUXSEG6EI64_V_M1_MF4_MASK\0" + /* 204940 */ "PseudoVLOXSEG7EI64_V_M1_MF4_MASK\0" + /* 204973 */ "PseudoVSOXSEG7EI64_V_M1_MF4_MASK\0" + /* 205006 */ "PseudoVLUXSEG7EI64_V_M1_MF4_MASK\0" + /* 205039 */ "PseudoVSUXSEG7EI64_V_M1_MF4_MASK\0" + /* 205072 */ "PseudoVLOXSEG8EI64_V_M1_MF4_MASK\0" + /* 205105 */ "PseudoVSOXSEG8EI64_V_M1_MF4_MASK\0" + /* 205138 */ "PseudoVLUXSEG8EI64_V_M1_MF4_MASK\0" + /* 205171 */ "PseudoVSUXSEG8EI64_V_M1_MF4_MASK\0" + /* 205204 */ "PseudoVLOXEI64_V_M1_MF4_MASK\0" + /* 205233 */ "PseudoVSOXEI64_V_M1_MF4_MASK\0" + /* 205262 */ "PseudoVLUXEI64_V_M1_MF4_MASK\0" + /* 205291 */ "PseudoVSUXEI64_V_M1_MF4_MASK\0" + /* 205320 */ "PseudoVFSUB_VF32_MF4_MASK\0" + /* 205346 */ "PseudoVFMSUB_VF32_MF4_MASK\0" + /* 205373 */ "PseudoVFNMSUB_VF32_MF4_MASK\0" + /* 205401 */ "PseudoVFRSUB_VF32_MF4_MASK\0" + /* 205428 */ "PseudoVFWSUB_VF32_MF4_MASK\0" + /* 205455 */ "PseudoVFMSAC_VF32_MF4_MASK\0" + /* 205482 */ "PseudoVFNMSAC_VF32_MF4_MASK\0" + /* 205510 */ "PseudoVFWNMSAC_VF32_MF4_MASK\0" + /* 205539 */ "PseudoVFWMSAC_VF32_MF4_MASK\0" + /* 205567 */ "PseudoVFMACC_VF32_MF4_MASK\0" + /* 205594 */ "PseudoVFNMACC_VF32_MF4_MASK\0" + /* 205622 */ "PseudoVFWNMACC_VF32_MF4_MASK\0" + /* 205651 */ "PseudoVFWMACC_VF32_MF4_MASK\0" + /* 205679 */ "PseudoVFADD_VF32_MF4_MASK\0" + /* 205705 */ "PseudoVFMADD_VF32_MF4_MASK\0" + /* 205732 */ "PseudoVFNMADD_VF32_MF4_MASK\0" + /* 205760 */ "PseudoVFWADD_VF32_MF4_MASK\0" + /* 205787 */ "PseudoVMFGE_VF32_MF4_MASK\0" + /* 205813 */ "PseudoVMFLE_VF32_MF4_MASK\0" + /* 205839 */ "PseudoVMFNE_VF32_MF4_MASK\0" + /* 205865 */ "PseudoVFSGNJ_VF32_MF4_MASK\0" + /* 205892 */ "PseudoVFMUL_VF32_MF4_MASK\0" + /* 205918 */ "PseudoVFWMUL_VF32_MF4_MASK\0" + /* 205945 */ "PseudoVFMIN_VF32_MF4_MASK\0" + /* 205971 */ "PseudoVFSGNJN_VF32_MF4_MASK\0" + /* 205999 */ "PseudoVFSLIDE1DOWN_VF32_MF4_MASK\0" + /* 206032 */ "PseudoVFSLIDE1UP_VF32_MF4_MASK\0" + /* 206063 */ "PseudoVMFEQ_VF32_MF4_MASK\0" + /* 206089 */ "PseudoVMFGT_VF32_MF4_MASK\0" + /* 206115 */ "PseudoVMFLT_VF32_MF4_MASK\0" + /* 206141 */ "PseudoVFDIV_VF32_MF4_MASK\0" + /* 206167 */ "PseudoVFRDIV_VF32_MF4_MASK\0" + /* 206194 */ "PseudoVFMAX_VF32_MF4_MASK\0" + /* 206220 */ "PseudoVFSGNJX_VF32_MF4_MASK\0" + /* 206248 */ "PseudoVFWSUB_WF32_MF4_MASK\0" + /* 206275 */ "PseudoVFWADD_WF32_MF4_MASK\0" + /* 206302 */ "PseudoVAMOADDEI16_WD_MF2_MF4_MASK\0" + /* 206336 */ "PseudoVAMOANDEI16_WD_MF2_MF4_MASK\0" + /* 206370 */ "PseudoVAMOMINEI16_WD_MF2_MF4_MASK\0" + /* 206404 */ "PseudoVAMOSWAPEI16_WD_MF2_MF4_MASK\0" + /* 206439 */ "PseudoVAMOOREI16_WD_MF2_MF4_MASK\0" + /* 206472 */ "PseudoVAMOXOREI16_WD_MF2_MF4_MASK\0" + /* 206506 */ "PseudoVAMOMINUEI16_WD_MF2_MF4_MASK\0" + /* 206541 */ "PseudoVAMOMAXUEI16_WD_MF2_MF4_MASK\0" + /* 206576 */ "PseudoVAMOMAXEI16_WD_MF2_MF4_MASK\0" + /* 206610 */ "PseudoVRGATHEREI16_VV_MF2_MF4_MASK\0" + /* 206645 */ "PseudoVLOXSEG2EI32_V_MF2_MF4_MASK\0" + /* 206679 */ "PseudoVSOXSEG2EI32_V_MF2_MF4_MASK\0" + /* 206713 */ "PseudoVLUXSEG2EI32_V_MF2_MF4_MASK\0" + /* 206747 */ "PseudoVSUXSEG2EI32_V_MF2_MF4_MASK\0" + /* 206781 */ "PseudoVLOXSEG3EI32_V_MF2_MF4_MASK\0" + /* 206815 */ "PseudoVSOXSEG3EI32_V_MF2_MF4_MASK\0" + /* 206849 */ "PseudoVLUXSEG3EI32_V_MF2_MF4_MASK\0" + /* 206883 */ "PseudoVSUXSEG3EI32_V_MF2_MF4_MASK\0" + /* 206917 */ "PseudoVLOXSEG4EI32_V_MF2_MF4_MASK\0" + /* 206951 */ "PseudoVSOXSEG4EI32_V_MF2_MF4_MASK\0" + /* 206985 */ "PseudoVLUXSEG4EI32_V_MF2_MF4_MASK\0" + /* 207019 */ "PseudoVSUXSEG4EI32_V_MF2_MF4_MASK\0" + /* 207053 */ "PseudoVLOXSEG5EI32_V_MF2_MF4_MASK\0" + /* 207087 */ "PseudoVSOXSEG5EI32_V_MF2_MF4_MASK\0" + /* 207121 */ "PseudoVLUXSEG5EI32_V_MF2_MF4_MASK\0" + /* 207155 */ "PseudoVSUXSEG5EI32_V_MF2_MF4_MASK\0" + /* 207189 */ "PseudoVLOXSEG6EI32_V_MF2_MF4_MASK\0" + /* 207223 */ "PseudoVSOXSEG6EI32_V_MF2_MF4_MASK\0" + /* 207257 */ "PseudoVLUXSEG6EI32_V_MF2_MF4_MASK\0" + /* 207291 */ "PseudoVSUXSEG6EI32_V_MF2_MF4_MASK\0" + /* 207325 */ "PseudoVLOXSEG7EI32_V_MF2_MF4_MASK\0" + /* 207359 */ "PseudoVSOXSEG7EI32_V_MF2_MF4_MASK\0" + /* 207393 */ "PseudoVLUXSEG7EI32_V_MF2_MF4_MASK\0" + /* 207427 */ "PseudoVSUXSEG7EI32_V_MF2_MF4_MASK\0" + /* 207461 */ "PseudoVLOXSEG8EI32_V_MF2_MF4_MASK\0" + /* 207495 */ "PseudoVSOXSEG8EI32_V_MF2_MF4_MASK\0" + /* 207529 */ "PseudoVLUXSEG8EI32_V_MF2_MF4_MASK\0" + /* 207563 */ "PseudoVSUXSEG8EI32_V_MF2_MF4_MASK\0" + /* 207597 */ "PseudoVLOXEI32_V_MF2_MF4_MASK\0" + /* 207627 */ "PseudoVSOXEI32_V_MF2_MF4_MASK\0" + /* 207657 */ "PseudoVLUXEI32_V_MF2_MF4_MASK\0" + /* 207687 */ "PseudoVSUXEI32_V_MF2_MF4_MASK\0" + /* 207717 */ "PseudoVLOXSEG2EI16_V_MF2_MF4_MASK\0" + /* 207751 */ "PseudoVSOXSEG2EI16_V_MF2_MF4_MASK\0" + /* 207785 */ "PseudoVLUXSEG2EI16_V_MF2_MF4_MASK\0" + /* 207819 */ "PseudoVSUXSEG2EI16_V_MF2_MF4_MASK\0" + /* 207853 */ "PseudoVLOXSEG3EI16_V_MF2_MF4_MASK\0" + /* 207887 */ "PseudoVSOXSEG3EI16_V_MF2_MF4_MASK\0" + /* 207921 */ "PseudoVLUXSEG3EI16_V_MF2_MF4_MASK\0" + /* 207955 */ "PseudoVSUXSEG3EI16_V_MF2_MF4_MASK\0" + /* 207989 */ "PseudoVLOXSEG4EI16_V_MF2_MF4_MASK\0" + /* 208023 */ "PseudoVSOXSEG4EI16_V_MF2_MF4_MASK\0" + /* 208057 */ "PseudoVLUXSEG4EI16_V_MF2_MF4_MASK\0" + /* 208091 */ "PseudoVSUXSEG4EI16_V_MF2_MF4_MASK\0" + /* 208125 */ "PseudoVLOXSEG5EI16_V_MF2_MF4_MASK\0" + /* 208159 */ "PseudoVSOXSEG5EI16_V_MF2_MF4_MASK\0" + /* 208193 */ "PseudoVLUXSEG5EI16_V_MF2_MF4_MASK\0" + /* 208227 */ "PseudoVSUXSEG5EI16_V_MF2_MF4_MASK\0" + /* 208261 */ "PseudoVLOXSEG6EI16_V_MF2_MF4_MASK\0" + /* 208295 */ "PseudoVSOXSEG6EI16_V_MF2_MF4_MASK\0" + /* 208329 */ "PseudoVLUXSEG6EI16_V_MF2_MF4_MASK\0" + /* 208363 */ "PseudoVSUXSEG6EI16_V_MF2_MF4_MASK\0" + /* 208397 */ "PseudoVLOXSEG7EI16_V_MF2_MF4_MASK\0" + /* 208431 */ "PseudoVSOXSEG7EI16_V_MF2_MF4_MASK\0" + /* 208465 */ "PseudoVLUXSEG7EI16_V_MF2_MF4_MASK\0" + /* 208499 */ "PseudoVSUXSEG7EI16_V_MF2_MF4_MASK\0" + /* 208533 */ "PseudoVLOXSEG8EI16_V_MF2_MF4_MASK\0" + /* 208567 */ "PseudoVSOXSEG8EI16_V_MF2_MF4_MASK\0" + /* 208601 */ "PseudoVLUXSEG8EI16_V_MF2_MF4_MASK\0" + /* 208635 */ "PseudoVSUXSEG8EI16_V_MF2_MF4_MASK\0" + /* 208669 */ "PseudoVLOXEI16_V_MF2_MF4_MASK\0" + /* 208699 */ "PseudoVSOXEI16_V_MF2_MF4_MASK\0" + /* 208729 */ "PseudoVLUXEI16_V_MF2_MF4_MASK\0" + /* 208759 */ "PseudoVSUXEI16_V_MF2_MF4_MASK\0" + /* 208789 */ "PseudoVSEXT_VF2_MF4_MASK\0" + /* 208814 */ "PseudoVZEXT_VF2_MF4_MASK\0" + /* 208839 */ "PseudoVAMOADDEI8_WD_M2_MF4_MASK\0" + /* 208871 */ "PseudoVAMOANDEI8_WD_M2_MF4_MASK\0" + /* 208903 */ "PseudoVAMOMINEI8_WD_M2_MF4_MASK\0" + /* 208935 */ "PseudoVAMOSWAPEI8_WD_M2_MF4_MASK\0" + /* 208968 */ "PseudoVAMOOREI8_WD_M2_MF4_MASK\0" + /* 208999 */ "PseudoVAMOXOREI8_WD_M2_MF4_MASK\0" + /* 209031 */ "PseudoVAMOMINUEI8_WD_M2_MF4_MASK\0" + /* 209064 */ "PseudoVAMOMAXUEI8_WD_M2_MF4_MASK\0" + /* 209097 */ "PseudoVAMOMAXEI8_WD_M2_MF4_MASK\0" + /* 209129 */ "PseudoVLOXSEG2EI64_V_M2_MF4_MASK\0" + /* 209162 */ "PseudoVSOXSEG2EI64_V_M2_MF4_MASK\0" + /* 209195 */ "PseudoVLUXSEG2EI64_V_M2_MF4_MASK\0" + /* 209228 */ "PseudoVSUXSEG2EI64_V_M2_MF4_MASK\0" + /* 209261 */ "PseudoVLOXSEG3EI64_V_M2_MF4_MASK\0" + /* 209294 */ "PseudoVSOXSEG3EI64_V_M2_MF4_MASK\0" + /* 209327 */ "PseudoVLUXSEG3EI64_V_M2_MF4_MASK\0" + /* 209360 */ "PseudoVSUXSEG3EI64_V_M2_MF4_MASK\0" + /* 209393 */ "PseudoVLOXSEG4EI64_V_M2_MF4_MASK\0" + /* 209426 */ "PseudoVSOXSEG4EI64_V_M2_MF4_MASK\0" + /* 209459 */ "PseudoVLUXSEG4EI64_V_M2_MF4_MASK\0" + /* 209492 */ "PseudoVSUXSEG4EI64_V_M2_MF4_MASK\0" + /* 209525 */ "PseudoVLOXSEG5EI64_V_M2_MF4_MASK\0" + /* 209558 */ "PseudoVSOXSEG5EI64_V_M2_MF4_MASK\0" + /* 209591 */ "PseudoVLUXSEG5EI64_V_M2_MF4_MASK\0" + /* 209624 */ "PseudoVSUXSEG5EI64_V_M2_MF4_MASK\0" + /* 209657 */ "PseudoVLOXSEG6EI64_V_M2_MF4_MASK\0" + /* 209690 */ "PseudoVSOXSEG6EI64_V_M2_MF4_MASK\0" + /* 209723 */ "PseudoVLUXSEG6EI64_V_M2_MF4_MASK\0" + /* 209756 */ "PseudoVSUXSEG6EI64_V_M2_MF4_MASK\0" + /* 209789 */ "PseudoVLOXSEG7EI64_V_M2_MF4_MASK\0" + /* 209822 */ "PseudoVSOXSEG7EI64_V_M2_MF4_MASK\0" + /* 209855 */ "PseudoVLUXSEG7EI64_V_M2_MF4_MASK\0" + /* 209888 */ "PseudoVSUXSEG7EI64_V_M2_MF4_MASK\0" + /* 209921 */ "PseudoVLOXSEG8EI64_V_M2_MF4_MASK\0" + /* 209954 */ "PseudoVSOXSEG8EI64_V_M2_MF4_MASK\0" + /* 209987 */ "PseudoVLUXSEG8EI64_V_M2_MF4_MASK\0" + /* 210020 */ "PseudoVSUXSEG8EI64_V_M2_MF4_MASK\0" + /* 210053 */ "PseudoVLOXEI64_V_M2_MF4_MASK\0" + /* 210082 */ "PseudoVSOXEI64_V_M2_MF4_MASK\0" + /* 210111 */ "PseudoVLUXEI64_V_M2_MF4_MASK\0" + /* 210140 */ "PseudoVSUXEI64_V_M2_MF4_MASK\0" + /* 210169 */ "PseudoVFSUB_VF64_MF4_MASK\0" + /* 210195 */ "PseudoVFMSUB_VF64_MF4_MASK\0" + /* 210222 */ "PseudoVFNMSUB_VF64_MF4_MASK\0" + /* 210250 */ "PseudoVFRSUB_VF64_MF4_MASK\0" + /* 210277 */ "PseudoVFMSAC_VF64_MF4_MASK\0" + /* 210304 */ "PseudoVFNMSAC_VF64_MF4_MASK\0" + /* 210332 */ "PseudoVFMACC_VF64_MF4_MASK\0" + /* 210359 */ "PseudoVFNMACC_VF64_MF4_MASK\0" + /* 210387 */ "PseudoVFADD_VF64_MF4_MASK\0" + /* 210413 */ "PseudoVFMADD_VF64_MF4_MASK\0" + /* 210440 */ "PseudoVFNMADD_VF64_MF4_MASK\0" + /* 210468 */ "PseudoVMFGE_VF64_MF4_MASK\0" + /* 210494 */ "PseudoVMFLE_VF64_MF4_MASK\0" + /* 210520 */ "PseudoVMFNE_VF64_MF4_MASK\0" + /* 210546 */ "PseudoVFSGNJ_VF64_MF4_MASK\0" + /* 210573 */ "PseudoVFMUL_VF64_MF4_MASK\0" + /* 210599 */ "PseudoVFMIN_VF64_MF4_MASK\0" + /* 210625 */ "PseudoVFSGNJN_VF64_MF4_MASK\0" + /* 210653 */ "PseudoVFSLIDE1DOWN_VF64_MF4_MASK\0" + /* 210686 */ "PseudoVFSLIDE1UP_VF64_MF4_MASK\0" + /* 210717 */ "PseudoVMFEQ_VF64_MF4_MASK\0" + /* 210743 */ "PseudoVMFGT_VF64_MF4_MASK\0" + /* 210769 */ "PseudoVMFLT_VF64_MF4_MASK\0" + /* 210795 */ "PseudoVFDIV_VF64_MF4_MASK\0" + /* 210821 */ "PseudoVFRDIV_VF64_MF4_MASK\0" + /* 210848 */ "PseudoVFMAX_VF64_MF4_MASK\0" + /* 210874 */ "PseudoVFSGNJX_VF64_MF4_MASK\0" + /* 210902 */ "PseudoVRGATHEREI16_VV_MF4_MF4_MASK\0" + /* 210937 */ "PseudoVLOXSEG2EI16_V_MF4_MF4_MASK\0" + /* 210971 */ "PseudoVSOXSEG2EI16_V_MF4_MF4_MASK\0" + /* 211005 */ "PseudoVLUXSEG2EI16_V_MF4_MF4_MASK\0" + /* 211039 */ "PseudoVSUXSEG2EI16_V_MF4_MF4_MASK\0" + /* 211073 */ "PseudoVLOXSEG3EI16_V_MF4_MF4_MASK\0" + /* 211107 */ "PseudoVSOXSEG3EI16_V_MF4_MF4_MASK\0" + /* 211141 */ "PseudoVLUXSEG3EI16_V_MF4_MF4_MASK\0" + /* 211175 */ "PseudoVSUXSEG3EI16_V_MF4_MF4_MASK\0" + /* 211209 */ "PseudoVLOXSEG4EI16_V_MF4_MF4_MASK\0" + /* 211243 */ "PseudoVSOXSEG4EI16_V_MF4_MF4_MASK\0" + /* 211277 */ "PseudoVLUXSEG4EI16_V_MF4_MF4_MASK\0" + /* 211311 */ "PseudoVSUXSEG4EI16_V_MF4_MF4_MASK\0" + /* 211345 */ "PseudoVLOXSEG5EI16_V_MF4_MF4_MASK\0" + /* 211379 */ "PseudoVSOXSEG5EI16_V_MF4_MF4_MASK\0" + /* 211413 */ "PseudoVLUXSEG5EI16_V_MF4_MF4_MASK\0" + /* 211447 */ "PseudoVSUXSEG5EI16_V_MF4_MF4_MASK\0" + /* 211481 */ "PseudoVLOXSEG6EI16_V_MF4_MF4_MASK\0" + /* 211515 */ "PseudoVSOXSEG6EI16_V_MF4_MF4_MASK\0" + /* 211549 */ "PseudoVLUXSEG6EI16_V_MF4_MF4_MASK\0" + /* 211583 */ "PseudoVSUXSEG6EI16_V_MF4_MF4_MASK\0" + /* 211617 */ "PseudoVLOXSEG7EI16_V_MF4_MF4_MASK\0" + /* 211651 */ "PseudoVSOXSEG7EI16_V_MF4_MF4_MASK\0" + /* 211685 */ "PseudoVLUXSEG7EI16_V_MF4_MF4_MASK\0" + /* 211719 */ "PseudoVSUXSEG7EI16_V_MF4_MF4_MASK\0" + /* 211753 */ "PseudoVLOXSEG8EI16_V_MF4_MF4_MASK\0" + /* 211787 */ "PseudoVSOXSEG8EI16_V_MF4_MF4_MASK\0" + /* 211821 */ "PseudoVLUXSEG8EI16_V_MF4_MF4_MASK\0" + /* 211855 */ "PseudoVSUXSEG8EI16_V_MF4_MF4_MASK\0" + /* 211889 */ "PseudoVLOXEI16_V_MF4_MF4_MASK\0" + /* 211919 */ "PseudoVSOXEI16_V_MF4_MF4_MASK\0" + /* 211949 */ "PseudoVLUXEI16_V_MF4_MF4_MASK\0" + /* 211979 */ "PseudoVSUXEI16_V_MF4_MF4_MASK\0" + /* 212009 */ "PseudoVLOXSEG2EI8_V_MF4_MF4_MASK\0" + /* 212042 */ "PseudoVSOXSEG2EI8_V_MF4_MF4_MASK\0" + /* 212075 */ "PseudoVLUXSEG2EI8_V_MF4_MF4_MASK\0" + /* 212108 */ "PseudoVSUXSEG2EI8_V_MF4_MF4_MASK\0" + /* 212141 */ "PseudoVLOXSEG3EI8_V_MF4_MF4_MASK\0" + /* 212174 */ "PseudoVSOXSEG3EI8_V_MF4_MF4_MASK\0" + /* 212207 */ "PseudoVLUXSEG3EI8_V_MF4_MF4_MASK\0" + /* 212240 */ "PseudoVSUXSEG3EI8_V_MF4_MF4_MASK\0" + /* 212273 */ "PseudoVLOXSEG4EI8_V_MF4_MF4_MASK\0" + /* 212306 */ "PseudoVSOXSEG4EI8_V_MF4_MF4_MASK\0" + /* 212339 */ "PseudoVLUXSEG4EI8_V_MF4_MF4_MASK\0" + /* 212372 */ "PseudoVSUXSEG4EI8_V_MF4_MF4_MASK\0" + /* 212405 */ "PseudoVLOXSEG5EI8_V_MF4_MF4_MASK\0" + /* 212438 */ "PseudoVSOXSEG5EI8_V_MF4_MF4_MASK\0" + /* 212471 */ "PseudoVLUXSEG5EI8_V_MF4_MF4_MASK\0" + /* 212504 */ "PseudoVSUXSEG5EI8_V_MF4_MF4_MASK\0" + /* 212537 */ "PseudoVLOXSEG6EI8_V_MF4_MF4_MASK\0" + /* 212570 */ "PseudoVSOXSEG6EI8_V_MF4_MF4_MASK\0" + /* 212603 */ "PseudoVLUXSEG6EI8_V_MF4_MF4_MASK\0" + /* 212636 */ "PseudoVSUXSEG6EI8_V_MF4_MF4_MASK\0" + /* 212669 */ "PseudoVLOXSEG7EI8_V_MF4_MF4_MASK\0" + /* 212702 */ "PseudoVSOXSEG7EI8_V_MF4_MF4_MASK\0" + /* 212735 */ "PseudoVLUXSEG7EI8_V_MF4_MF4_MASK\0" + /* 212768 */ "PseudoVSUXSEG7EI8_V_MF4_MF4_MASK\0" + /* 212801 */ "PseudoVLOXSEG8EI8_V_MF4_MF4_MASK\0" + /* 212834 */ "PseudoVSOXSEG8EI8_V_MF4_MF4_MASK\0" + /* 212867 */ "PseudoVLUXSEG8EI8_V_MF4_MF4_MASK\0" + /* 212900 */ "PseudoVSUXSEG8EI8_V_MF4_MF4_MASK\0" + /* 212933 */ "PseudoVLOXEI8_V_MF4_MF4_MASK\0" + /* 212962 */ "PseudoVSOXEI8_V_MF4_MF4_MASK\0" + /* 212991 */ "PseudoVLUXEI8_V_MF4_MF4_MASK\0" + /* 213020 */ "PseudoVSUXEI8_V_MF4_MF4_MASK\0" + /* 213049 */ "PseudoVFSUB_VF16_MF4_MASK\0" + /* 213075 */ "PseudoVFMSUB_VF16_MF4_MASK\0" + /* 213102 */ "PseudoVFNMSUB_VF16_MF4_MASK\0" + /* 213130 */ "PseudoVFRSUB_VF16_MF4_MASK\0" + /* 213157 */ "PseudoVFWSUB_VF16_MF4_MASK\0" + /* 213184 */ "PseudoVFMSAC_VF16_MF4_MASK\0" + /* 213211 */ "PseudoVFNMSAC_VF16_MF4_MASK\0" + /* 213239 */ "PseudoVFWNMSAC_VF16_MF4_MASK\0" + /* 213268 */ "PseudoVFWMSAC_VF16_MF4_MASK\0" + /* 213296 */ "PseudoVFMACC_VF16_MF4_MASK\0" + /* 213323 */ "PseudoVFNMACC_VF16_MF4_MASK\0" + /* 213351 */ "PseudoVFWNMACC_VF16_MF4_MASK\0" + /* 213380 */ "PseudoVFWMACC_VF16_MF4_MASK\0" + /* 213408 */ "PseudoVFADD_VF16_MF4_MASK\0" + /* 213434 */ "PseudoVFMADD_VF16_MF4_MASK\0" + /* 213461 */ "PseudoVFNMADD_VF16_MF4_MASK\0" + /* 213489 */ "PseudoVFWADD_VF16_MF4_MASK\0" + /* 213516 */ "PseudoVMFGE_VF16_MF4_MASK\0" + /* 213542 */ "PseudoVMFLE_VF16_MF4_MASK\0" + /* 213568 */ "PseudoVMFNE_VF16_MF4_MASK\0" + /* 213594 */ "PseudoVFSGNJ_VF16_MF4_MASK\0" + /* 213621 */ "PseudoVFMUL_VF16_MF4_MASK\0" + /* 213647 */ "PseudoVFWMUL_VF16_MF4_MASK\0" + /* 213674 */ "PseudoVFMIN_VF16_MF4_MASK\0" + /* 213700 */ "PseudoVFSGNJN_VF16_MF4_MASK\0" + /* 213728 */ "PseudoVFSLIDE1DOWN_VF16_MF4_MASK\0" + /* 213761 */ "PseudoVFSLIDE1UP_VF16_MF4_MASK\0" + /* 213792 */ "PseudoVMFEQ_VF16_MF4_MASK\0" + /* 213818 */ "PseudoVMFGT_VF16_MF4_MASK\0" + /* 213844 */ "PseudoVMFLT_VF16_MF4_MASK\0" + /* 213870 */ "PseudoVFDIV_VF16_MF4_MASK\0" + /* 213896 */ "PseudoVFRDIV_VF16_MF4_MASK\0" + /* 213923 */ "PseudoVFMAX_VF16_MF4_MASK\0" + /* 213949 */ "PseudoVFSGNJX_VF16_MF4_MASK\0" + /* 213977 */ "PseudoVFWSUB_WF16_MF4_MASK\0" + /* 214004 */ "PseudoVFWADD_WF16_MF4_MASK\0" + /* 214031 */ "PseudoVRGATHEREI16_VV_MF8_MF4_MASK\0" + /* 214066 */ "PseudoVLOXSEG2EI8_V_MF8_MF4_MASK\0" + /* 214099 */ "PseudoVSOXSEG2EI8_V_MF8_MF4_MASK\0" + /* 214132 */ "PseudoVLUXSEG2EI8_V_MF8_MF4_MASK\0" + /* 214165 */ "PseudoVSUXSEG2EI8_V_MF8_MF4_MASK\0" + /* 214198 */ "PseudoVLOXSEG3EI8_V_MF8_MF4_MASK\0" + /* 214231 */ "PseudoVSOXSEG3EI8_V_MF8_MF4_MASK\0" + /* 214264 */ "PseudoVLUXSEG3EI8_V_MF8_MF4_MASK\0" + /* 214297 */ "PseudoVSUXSEG3EI8_V_MF8_MF4_MASK\0" + /* 214330 */ "PseudoVLOXSEG4EI8_V_MF8_MF4_MASK\0" + /* 214363 */ "PseudoVSOXSEG4EI8_V_MF8_MF4_MASK\0" + /* 214396 */ "PseudoVLUXSEG4EI8_V_MF8_MF4_MASK\0" + /* 214429 */ "PseudoVSUXSEG4EI8_V_MF8_MF4_MASK\0" + /* 214462 */ "PseudoVLOXSEG5EI8_V_MF8_MF4_MASK\0" + /* 214495 */ "PseudoVSOXSEG5EI8_V_MF8_MF4_MASK\0" + /* 214528 */ "PseudoVLUXSEG5EI8_V_MF8_MF4_MASK\0" + /* 214561 */ "PseudoVSUXSEG5EI8_V_MF8_MF4_MASK\0" + /* 214594 */ "PseudoVLOXSEG6EI8_V_MF8_MF4_MASK\0" + /* 214627 */ "PseudoVSOXSEG6EI8_V_MF8_MF4_MASK\0" + /* 214660 */ "PseudoVLUXSEG6EI8_V_MF8_MF4_MASK\0" + /* 214693 */ "PseudoVSUXSEG6EI8_V_MF8_MF4_MASK\0" + /* 214726 */ "PseudoVLOXSEG7EI8_V_MF8_MF4_MASK\0" + /* 214759 */ "PseudoVSOXSEG7EI8_V_MF8_MF4_MASK\0" + /* 214792 */ "PseudoVLUXSEG7EI8_V_MF8_MF4_MASK\0" + /* 214825 */ "PseudoVSUXSEG7EI8_V_MF8_MF4_MASK\0" + /* 214858 */ "PseudoVLOXSEG8EI8_V_MF8_MF4_MASK\0" + /* 214891 */ "PseudoVSOXSEG8EI8_V_MF8_MF4_MASK\0" + /* 214924 */ "PseudoVLUXSEG8EI8_V_MF8_MF4_MASK\0" + /* 214957 */ "PseudoVSUXSEG8EI8_V_MF8_MF4_MASK\0" + /* 214990 */ "PseudoVLOXEI8_V_MF8_MF4_MASK\0" + /* 215019 */ "PseudoVSOXEI8_V_MF8_MF4_MASK\0" + /* 215048 */ "PseudoVLUXEI8_V_MF8_MF4_MASK\0" + /* 215077 */ "PseudoVSUXEI8_V_MF8_MF4_MASK\0" + /* 215106 */ "PseudoVSSRA_VI_MF4_MASK\0" + /* 215130 */ "PseudoVSRA_VI_MF4_MASK\0" + /* 215153 */ "PseudoVRSUB_VI_MF4_MASK\0" + /* 215177 */ "PseudoVSADD_VI_MF4_MASK\0" + /* 215201 */ "PseudoVADD_VI_MF4_MASK\0" + /* 215224 */ "PseudoVAND_VI_MF4_MASK\0" + /* 215247 */ "PseudoVMSLE_VI_MF4_MASK\0" + /* 215271 */ "PseudoVMSNE_VI_MF4_MASK\0" + /* 215295 */ "PseudoVSLL_VI_MF4_MASK\0" + /* 215318 */ "PseudoVSSRL_VI_MF4_MASK\0" + /* 215342 */ "PseudoVSRL_VI_MF4_MASK\0" + /* 215365 */ "PseudoVSLIDEDOWN_VI_MF4_MASK\0" + /* 215394 */ "PseudoVSLIDEUP_VI_MF4_MASK\0" + /* 215421 */ "PseudoVMSEQ_VI_MF4_MASK\0" + /* 215445 */ "PseudoVRGATHER_VI_MF4_MASK\0" + /* 215472 */ "PseudoVOR_VI_MF4_MASK\0" + /* 215494 */ "PseudoVXOR_VI_MF4_MASK\0" + /* 215517 */ "PseudoVMSGT_VI_MF4_MASK\0" + /* 215541 */ "PseudoVSADDU_VI_MF4_MASK\0" + /* 215566 */ "PseudoVMSLEU_VI_MF4_MASK\0" + /* 215591 */ "PseudoVMSGTU_VI_MF4_MASK\0" + /* 215616 */ "PseudoVNSRA_WI_MF4_MASK\0" + /* 215640 */ "PseudoVNSRL_WI_MF4_MASK\0" + /* 215664 */ "PseudoVNCLIP_WI_MF4_MASK\0" + /* 215689 */ "PseudoVNCLIPU_WI_MF4_MASK\0" + /* 215715 */ "PseudoVIOTA_M_MF4_MASK\0" + /* 215738 */ "PseudoVREDAND_VS_MF4_MASK\0" + /* 215764 */ "PseudoVREDSUM_VS_MF4_MASK\0" + /* 215790 */ "PseudoVWREDSUM_VS_MF4_MASK\0" + /* 215817 */ "PseudoVFREDOSUM_VS_MF4_MASK\0" + /* 215845 */ "PseudoVFWREDOSUM_VS_MF4_MASK\0" + /* 215874 */ "PseudoVFREDUSUM_VS_MF4_MASK\0" + /* 215902 */ "PseudoVFWREDUSUM_VS_MF4_MASK\0" + /* 215931 */ "PseudoVFREDMIN_VS_MF4_MASK\0" + /* 215958 */ "PseudoVREDMIN_VS_MF4_MASK\0" + /* 215984 */ "PseudoVREDOR_VS_MF4_MASK\0" + /* 216009 */ "PseudoVREDXOR_VS_MF4_MASK\0" + /* 216035 */ "PseudoVWREDSUMU_VS_MF4_MASK\0" + /* 216063 */ "PseudoVREDMINU_VS_MF4_MASK\0" + /* 216090 */ "PseudoVREDMAXU_VS_MF4_MASK\0" + /* 216117 */ "PseudoVFREDMAX_VS_MF4_MASK\0" + /* 216144 */ "PseudoVREDMAX_VS_MF4_MASK\0" + /* 216170 */ "PseudoVSSRA_VV_MF4_MASK\0" + /* 216194 */ "PseudoVSRA_VV_MF4_MASK\0" + /* 216217 */ "PseudoVASUB_VV_MF4_MASK\0" + /* 216241 */ "PseudoVFSUB_VV_MF4_MASK\0" + /* 216265 */ "PseudoVFMSUB_VV_MF4_MASK\0" + /* 216290 */ "PseudoVFNMSUB_VV_MF4_MASK\0" + /* 216316 */ "PseudoVNMSUB_VV_MF4_MASK\0" + /* 216341 */ "PseudoVSSUB_VV_MF4_MASK\0" + /* 216365 */ "PseudoVSUB_VV_MF4_MASK\0" + /* 216388 */ "PseudoVFWSUB_VV_MF4_MASK\0" + /* 216413 */ "PseudoVWSUB_VV_MF4_MASK\0" + /* 216437 */ "PseudoVFMSAC_VV_MF4_MASK\0" + /* 216462 */ "PseudoVFNMSAC_VV_MF4_MASK\0" + /* 216488 */ "PseudoVNMSAC_VV_MF4_MASK\0" + /* 216513 */ "PseudoVFWNMSAC_VV_MF4_MASK\0" + /* 216540 */ "PseudoVFWMSAC_VV_MF4_MASK\0" + /* 216566 */ "PseudoVFMACC_VV_MF4_MASK\0" + /* 216591 */ "PseudoVFNMACC_VV_MF4_MASK\0" + /* 216617 */ "PseudoVFWNMACC_VV_MF4_MASK\0" + /* 216644 */ "PseudoVMACC_VV_MF4_MASK\0" + /* 216668 */ "PseudoVFWMACC_VV_MF4_MASK\0" + /* 216694 */ "PseudoVWMACC_VV_MF4_MASK\0" + /* 216719 */ "PseudoVAADD_VV_MF4_MASK\0" + /* 216743 */ "PseudoVFADD_VV_MF4_MASK\0" + /* 216767 */ "PseudoVFMADD_VV_MF4_MASK\0" + /* 216792 */ "PseudoVFNMADD_VV_MF4_MASK\0" + /* 216818 */ "PseudoVMADD_VV_MF4_MASK\0" + /* 216842 */ "PseudoVSADD_VV_MF4_MASK\0" + /* 216866 */ "PseudoVADD_VV_MF4_MASK\0" + /* 216889 */ "PseudoVFWADD_VV_MF4_MASK\0" + /* 216914 */ "PseudoVWADD_VV_MF4_MASK\0" + /* 216938 */ "PseudoVAND_VV_MF4_MASK\0" + /* 216961 */ "PseudoVMFLE_VV_MF4_MASK\0" + /* 216985 */ "PseudoVMSLE_VV_MF4_MASK\0" + /* 217009 */ "PseudoVMFNE_VV_MF4_MASK\0" + /* 217033 */ "PseudoVMSNE_VV_MF4_MASK\0" + /* 217057 */ "PseudoVMULH_VV_MF4_MASK\0" + /* 217081 */ "PseudoVFSGNJ_VV_MF4_MASK\0" + /* 217106 */ "PseudoVSLL_VV_MF4_MASK\0" + /* 217129 */ "PseudoVSSRL_VV_MF4_MASK\0" + /* 217153 */ "PseudoVSRL_VV_MF4_MASK\0" + /* 217176 */ "PseudoVFMUL_VV_MF4_MASK\0" + /* 217200 */ "PseudoVSMUL_VV_MF4_MASK\0" + /* 217224 */ "PseudoVMUL_VV_MF4_MASK\0" + /* 217247 */ "PseudoVFWMUL_VV_MF4_MASK\0" + /* 217272 */ "PseudoVWMUL_VV_MF4_MASK\0" + /* 217296 */ "PseudoVREM_VV_MF4_MASK\0" + /* 217319 */ "PseudoVFMIN_VV_MF4_MASK\0" + /* 217343 */ "PseudoVMIN_VV_MF4_MASK\0" + /* 217366 */ "PseudoVFSGNJN_VV_MF4_MASK\0" + /* 217392 */ "PseudoVMFEQ_VV_MF4_MASK\0" + /* 217416 */ "PseudoVMSEQ_VV_MF4_MASK\0" + /* 217440 */ "PseudoVRGATHER_VV_MF4_MASK\0" + /* 217467 */ "PseudoVOR_VV_MF4_MASK\0" + /* 217489 */ "PseudoVXOR_VV_MF4_MASK\0" + /* 217512 */ "PseudoVMFLT_VV_MF4_MASK\0" + /* 217536 */ "PseudoVMSLT_VV_MF4_MASK\0" + /* 217560 */ "PseudoVASUBU_VV_MF4_MASK\0" + /* 217585 */ "PseudoVSSUBU_VV_MF4_MASK\0" + /* 217610 */ "PseudoVWSUBU_VV_MF4_MASK\0" + /* 217635 */ "PseudoVWMACCU_VV_MF4_MASK\0" + /* 217661 */ "PseudoVAADDU_VV_MF4_MASK\0" + /* 217686 */ "PseudoVSADDU_VV_MF4_MASK\0" + /* 217711 */ "PseudoVWADDU_VV_MF4_MASK\0" + /* 217736 */ "PseudoVMSLEU_VV_MF4_MASK\0" + /* 217761 */ "PseudoVMULHU_VV_MF4_MASK\0" + /* 217786 */ "PseudoVWMULU_VV_MF4_MASK\0" + /* 217811 */ "PseudoVREMU_VV_MF4_MASK\0" + /* 217835 */ "PseudoVMINU_VV_MF4_MASK\0" + /* 217859 */ "PseudoVWMACCSU_VV_MF4_MASK\0" + /* 217886 */ "PseudoVMULHSU_VV_MF4_MASK\0" + /* 217912 */ "PseudoVWMULSU_VV_MF4_MASK\0" + /* 217938 */ "PseudoVMSLTU_VV_MF4_MASK\0" + /* 217963 */ "PseudoVDIVU_VV_MF4_MASK\0" + /* 217987 */ "PseudoVMAXU_VV_MF4_MASK\0" + /* 218011 */ "PseudoVFDIV_VV_MF4_MASK\0" + /* 218035 */ "PseudoVDIV_VV_MF4_MASK\0" + /* 218058 */ "PseudoVFMAX_VV_MF4_MASK\0" + /* 218082 */ "PseudoVMAX_VV_MF4_MASK\0" + /* 218105 */ "PseudoVFSGNJX_VV_MF4_MASK\0" + /* 218131 */ "PseudoVNSRA_WV_MF4_MASK\0" + /* 218155 */ "PseudoVFWSUB_WV_MF4_MASK\0" + /* 218180 */ "PseudoVWSUB_WV_MF4_MASK\0" + /* 218204 */ "PseudoVFWADD_WV_MF4_MASK\0" + /* 218229 */ "PseudoVWADD_WV_MF4_MASK\0" + /* 218253 */ "PseudoVNSRL_WV_MF4_MASK\0" + /* 218277 */ "PseudoVNCLIP_WV_MF4_MASK\0" + /* 218302 */ "PseudoVWSUBU_WV_MF4_MASK\0" + /* 218327 */ "PseudoVWADDU_WV_MF4_MASK\0" + /* 218352 */ "PseudoVNCLIPU_WV_MF4_MASK\0" + /* 218378 */ "PseudoVLSEG2E16_V_MF4_MASK\0" + /* 218405 */ "PseudoVLSSEG2E16_V_MF4_MASK\0" + /* 218433 */ "PseudoVSSSEG2E16_V_MF4_MASK\0" + /* 218461 */ "PseudoVSSEG2E16_V_MF4_MASK\0" + /* 218488 */ "PseudoVLSEG3E16_V_MF4_MASK\0" + /* 218515 */ "PseudoVLSSEG3E16_V_MF4_MASK\0" + /* 218543 */ "PseudoVSSSEG3E16_V_MF4_MASK\0" + /* 218571 */ "PseudoVSSEG3E16_V_MF4_MASK\0" + /* 218598 */ "PseudoVLSEG4E16_V_MF4_MASK\0" + /* 218625 */ "PseudoVLSSEG4E16_V_MF4_MASK\0" + /* 218653 */ "PseudoVSSSEG4E16_V_MF4_MASK\0" + /* 218681 */ "PseudoVSSEG4E16_V_MF4_MASK\0" + /* 218708 */ "PseudoVLSEG5E16_V_MF4_MASK\0" + /* 218735 */ "PseudoVLSSEG5E16_V_MF4_MASK\0" + /* 218763 */ "PseudoVSSSEG5E16_V_MF4_MASK\0" + /* 218791 */ "PseudoVSSEG5E16_V_MF4_MASK\0" + /* 218818 */ "PseudoVLSEG6E16_V_MF4_MASK\0" + /* 218845 */ "PseudoVLSSEG6E16_V_MF4_MASK\0" + /* 218873 */ "PseudoVSSSEG6E16_V_MF4_MASK\0" + /* 218901 */ "PseudoVSSEG6E16_V_MF4_MASK\0" + /* 218928 */ "PseudoVLSEG7E16_V_MF4_MASK\0" + /* 218955 */ "PseudoVLSSEG7E16_V_MF4_MASK\0" + /* 218983 */ "PseudoVSSSEG7E16_V_MF4_MASK\0" + /* 219011 */ "PseudoVSSEG7E16_V_MF4_MASK\0" + /* 219038 */ "PseudoVLSEG8E16_V_MF4_MASK\0" + /* 219065 */ "PseudoVLSSEG8E16_V_MF4_MASK\0" + /* 219093 */ "PseudoVSSSEG8E16_V_MF4_MASK\0" + /* 219121 */ "PseudoVSSEG8E16_V_MF4_MASK\0" + /* 219148 */ "PseudoVLE16_V_MF4_MASK\0" + /* 219171 */ "PseudoVLSE16_V_MF4_MASK\0" + /* 219195 */ "PseudoVSSE16_V_MF4_MASK\0" + /* 219219 */ "PseudoVSE16_V_MF4_MASK\0" + /* 219242 */ "PseudoVFREC7_V_MF4_MASK\0" + /* 219266 */ "PseudoVFRSQRT7_V_MF4_MASK\0" + /* 219292 */ "PseudoVLSEG2E8_V_MF4_MASK\0" + /* 219318 */ "PseudoVLSSEG2E8_V_MF4_MASK\0" + /* 219345 */ "PseudoVSSSEG2E8_V_MF4_MASK\0" + /* 219372 */ "PseudoVSSEG2E8_V_MF4_MASK\0" + /* 219398 */ "PseudoVLSEG3E8_V_MF4_MASK\0" + /* 219424 */ "PseudoVLSSEG3E8_V_MF4_MASK\0" + /* 219451 */ "PseudoVSSSEG3E8_V_MF4_MASK\0" + /* 219478 */ "PseudoVSSEG3E8_V_MF4_MASK\0" + /* 219504 */ "PseudoVLSEG4E8_V_MF4_MASK\0" + /* 219530 */ "PseudoVLSSEG4E8_V_MF4_MASK\0" + /* 219557 */ "PseudoVSSSEG4E8_V_MF4_MASK\0" + /* 219584 */ "PseudoVSSEG4E8_V_MF4_MASK\0" + /* 219610 */ "PseudoVLSEG5E8_V_MF4_MASK\0" + /* 219636 */ "PseudoVLSSEG5E8_V_MF4_MASK\0" + /* 219663 */ "PseudoVSSSEG5E8_V_MF4_MASK\0" + /* 219690 */ "PseudoVSSEG5E8_V_MF4_MASK\0" + /* 219716 */ "PseudoVLSEG6E8_V_MF4_MASK\0" + /* 219742 */ "PseudoVLSSEG6E8_V_MF4_MASK\0" + /* 219769 */ "PseudoVSSSEG6E8_V_MF4_MASK\0" + /* 219796 */ "PseudoVSSEG6E8_V_MF4_MASK\0" + /* 219822 */ "PseudoVLSEG7E8_V_MF4_MASK\0" + /* 219848 */ "PseudoVLSSEG7E8_V_MF4_MASK\0" + /* 219875 */ "PseudoVSSSEG7E8_V_MF4_MASK\0" + /* 219902 */ "PseudoVSSEG7E8_V_MF4_MASK\0" + /* 219928 */ "PseudoVLSEG8E8_V_MF4_MASK\0" + /* 219954 */ "PseudoVLSSEG8E8_V_MF4_MASK\0" + /* 219981 */ "PseudoVSSSEG8E8_V_MF4_MASK\0" + /* 220008 */ "PseudoVSSEG8E8_V_MF4_MASK\0" + /* 220034 */ "PseudoVLE8_V_MF4_MASK\0" + /* 220056 */ "PseudoVLSE8_V_MF4_MASK\0" + /* 220079 */ "PseudoVSSE8_V_MF4_MASK\0" + /* 220102 */ "PseudoVSE8_V_MF4_MASK\0" + /* 220124 */ "PseudoVID_V_MF4_MASK\0" + /* 220145 */ "PseudoVLSEG2E16FF_V_MF4_MASK\0" + /* 220174 */ "PseudoVLSEG3E16FF_V_MF4_MASK\0" + /* 220203 */ "PseudoVLSEG4E16FF_V_MF4_MASK\0" + /* 220232 */ "PseudoVLSEG5E16FF_V_MF4_MASK\0" + /* 220261 */ "PseudoVLSEG6E16FF_V_MF4_MASK\0" + /* 220290 */ "PseudoVLSEG7E16FF_V_MF4_MASK\0" + /* 220319 */ "PseudoVLSEG8E16FF_V_MF4_MASK\0" + /* 220348 */ "PseudoVLE16FF_V_MF4_MASK\0" + /* 220373 */ "PseudoVLSEG2E8FF_V_MF4_MASK\0" + /* 220401 */ "PseudoVLSEG3E8FF_V_MF4_MASK\0" + /* 220429 */ "PseudoVLSEG4E8FF_V_MF4_MASK\0" + /* 220457 */ "PseudoVLSEG5E8FF_V_MF4_MASK\0" + /* 220485 */ "PseudoVLSEG6E8FF_V_MF4_MASK\0" + /* 220513 */ "PseudoVLSEG7E8FF_V_MF4_MASK\0" + /* 220541 */ "PseudoVLSEG8E8FF_V_MF4_MASK\0" + /* 220569 */ "PseudoVLE8FF_V_MF4_MASK\0" + /* 220593 */ "PseudoVFWCVT_F_F_V_MF4_MASK\0" + /* 220621 */ "PseudoVFCVT_XU_F_V_MF4_MASK\0" + /* 220649 */ "PseudoVFWCVT_XU_F_V_MF4_MASK\0" + /* 220678 */ "PseudoVFCVT_RTZ_XU_F_V_MF4_MASK\0" + /* 220710 */ "PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK\0" + /* 220743 */ "PseudoVFCVT_X_F_V_MF4_MASK\0" + /* 220770 */ "PseudoVFWCVT_X_F_V_MF4_MASK\0" + /* 220798 */ "PseudoVFCVT_RTZ_X_F_V_MF4_MASK\0" + /* 220829 */ "PseudoVFWCVT_RTZ_X_F_V_MF4_MASK\0" + /* 220861 */ "PseudoVFCLASS_V_MF4_MASK\0" + /* 220886 */ "PseudoVFSQRT_V_MF4_MASK\0" + /* 220910 */ "PseudoVFCVT_F_XU_V_MF4_MASK\0" + /* 220938 */ "PseudoVFWCVT_F_XU_V_MF4_MASK\0" + /* 220967 */ "PseudoVFCVT_F_X_V_MF4_MASK\0" + /* 220994 */ "PseudoVFWCVT_F_X_V_MF4_MASK\0" + /* 221022 */ "PseudoVFNCVT_ROD_F_F_W_MF4_MASK\0" + /* 221054 */ "PseudoVFNCVT_F_F_W_MF4_MASK\0" + /* 221082 */ "PseudoVFNCVT_XU_F_W_MF4_MASK\0" + /* 221111 */ "PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK\0" + /* 221144 */ "PseudoVFNCVT_X_F_W_MF4_MASK\0" + /* 221172 */ "PseudoVFNCVT_RTZ_X_F_W_MF4_MASK\0" + /* 221204 */ "PseudoVFNCVT_F_XU_W_MF4_MASK\0" + /* 221233 */ "PseudoVFNCVT_F_X_W_MF4_MASK\0" + /* 221261 */ "PseudoVSSRA_VX_MF4_MASK\0" + /* 221285 */ "PseudoVSRA_VX_MF4_MASK\0" + /* 221308 */ "PseudoVASUB_VX_MF4_MASK\0" + /* 221332 */ "PseudoVNMSUB_VX_MF4_MASK\0" + /* 221357 */ "PseudoVRSUB_VX_MF4_MASK\0" + /* 221381 */ "PseudoVSSUB_VX_MF4_MASK\0" + /* 221405 */ "PseudoVSUB_VX_MF4_MASK\0" + /* 221428 */ "PseudoVWSUB_VX_MF4_MASK\0" + /* 221452 */ "PseudoVNMSAC_VX_MF4_MASK\0" + /* 221477 */ "PseudoVMACC_VX_MF4_MASK\0" + /* 221501 */ "PseudoVWMACC_VX_MF4_MASK\0" + /* 221526 */ "PseudoVAADD_VX_MF4_MASK\0" + /* 221550 */ "PseudoVMADD_VX_MF4_MASK\0" + /* 221574 */ "PseudoVSADD_VX_MF4_MASK\0" + /* 221598 */ "PseudoVADD_VX_MF4_MASK\0" + /* 221621 */ "PseudoVWADD_VX_MF4_MASK\0" + /* 221645 */ "PseudoVAND_VX_MF4_MASK\0" + /* 221668 */ "PseudoVMSLE_VX_MF4_MASK\0" + /* 221692 */ "PseudoVMSNE_VX_MF4_MASK\0" + /* 221716 */ "PseudoVMULH_VX_MF4_MASK\0" + /* 221740 */ "PseudoVSLL_VX_MF4_MASK\0" + /* 221763 */ "PseudoVSSRL_VX_MF4_MASK\0" + /* 221787 */ "PseudoVSRL_VX_MF4_MASK\0" + /* 221810 */ "PseudoVSMUL_VX_MF4_MASK\0" + /* 221834 */ "PseudoVMUL_VX_MF4_MASK\0" + /* 221857 */ "PseudoVWMUL_VX_MF4_MASK\0" + /* 221881 */ "PseudoVREM_VX_MF4_MASK\0" + /* 221904 */ "PseudoVMIN_VX_MF4_MASK\0" + /* 221927 */ "PseudoVSLIDE1DOWN_VX_MF4_MASK\0" + /* 221957 */ "PseudoVSLIDEDOWN_VX_MF4_MASK\0" + /* 221986 */ "PseudoVSLIDE1UP_VX_MF4_MASK\0" + /* 222014 */ "PseudoVSLIDEUP_VX_MF4_MASK\0" + /* 222041 */ "PseudoVMSEQ_VX_MF4_MASK\0" + /* 222065 */ "PseudoVRGATHER_VX_MF4_MASK\0" + /* 222092 */ "PseudoVOR_VX_MF4_MASK\0" + /* 222114 */ "PseudoVXOR_VX_MF4_MASK\0" + /* 222137 */ "PseudoVWMACCUS_VX_MF4_MASK\0" + /* 222164 */ "PseudoVMSGT_VX_MF4_MASK\0" + /* 222188 */ "PseudoVMSLT_VX_MF4_MASK\0" + /* 222212 */ "PseudoVASUBU_VX_MF4_MASK\0" + /* 222237 */ "PseudoVSSUBU_VX_MF4_MASK\0" + /* 222262 */ "PseudoVWSUBU_VX_MF4_MASK\0" + /* 222287 */ "PseudoVWMACCU_VX_MF4_MASK\0" + /* 222313 */ "PseudoVAADDU_VX_MF4_MASK\0" + /* 222338 */ "PseudoVSADDU_VX_MF4_MASK\0" + /* 222363 */ "PseudoVWADDU_VX_MF4_MASK\0" + /* 222388 */ "PseudoVMSLEU_VX_MF4_MASK\0" + /* 222413 */ "PseudoVMULHU_VX_MF4_MASK\0" + /* 222438 */ "PseudoVWMULU_VX_MF4_MASK\0" + /* 222463 */ "PseudoVREMU_VX_MF4_MASK\0" + /* 222487 */ "PseudoVMINU_VX_MF4_MASK\0" + /* 222511 */ "PseudoVWMACCSU_VX_MF4_MASK\0" + /* 222538 */ "PseudoVMULHSU_VX_MF4_MASK\0" + /* 222564 */ "PseudoVWMULSU_VX_MF4_MASK\0" + /* 222590 */ "PseudoVMSGTU_VX_MF4_MASK\0" + /* 222615 */ "PseudoVMSLTU_VX_MF4_MASK\0" + /* 222640 */ "PseudoVDIVU_VX_MF4_MASK\0" + /* 222664 */ "PseudoVMAXU_VX_MF4_MASK\0" + /* 222688 */ "PseudoVDIV_VX_MF4_MASK\0" + /* 222711 */ "PseudoVMAX_VX_MF4_MASK\0" + /* 222734 */ "PseudoVNSRA_WX_MF4_MASK\0" + /* 222758 */ "PseudoVWSUB_WX_MF4_MASK\0" + /* 222782 */ "PseudoVWADD_WX_MF4_MASK\0" + /* 222806 */ "PseudoVNSRL_WX_MF4_MASK\0" + /* 222830 */ "PseudoVNCLIP_WX_MF4_MASK\0" + /* 222855 */ "PseudoVWSUBU_WX_MF4_MASK\0" + /* 222880 */ "PseudoVWADDU_WX_MF4_MASK\0" + /* 222905 */ "PseudoVNCLIPU_WX_MF4_MASK\0" + /* 222931 */ "PseudoVLOXSEG2EI16_V_M1_M4_MASK\0" + /* 222963 */ "PseudoVSOXSEG2EI16_V_M1_M4_MASK\0" + /* 222995 */ "PseudoVLUXSEG2EI16_V_M1_M4_MASK\0" + /* 223027 */ "PseudoVSUXSEG2EI16_V_M1_M4_MASK\0" + /* 223059 */ "PseudoVLOXEI16_V_M1_M4_MASK\0" + /* 223087 */ "PseudoVSOXEI16_V_M1_M4_MASK\0" + /* 223115 */ "PseudoVLUXEI16_V_M1_M4_MASK\0" + /* 223143 */ "PseudoVSUXEI16_V_M1_M4_MASK\0" + /* 223171 */ "PseudoVLOXSEG2EI8_V_M1_M4_MASK\0" + /* 223202 */ "PseudoVSOXSEG2EI8_V_M1_M4_MASK\0" + /* 223233 */ "PseudoVLUXSEG2EI8_V_M1_M4_MASK\0" + /* 223264 */ "PseudoVSUXSEG2EI8_V_M1_M4_MASK\0" + /* 223295 */ "PseudoVLOXEI8_V_M1_M4_MASK\0" + /* 223322 */ "PseudoVSOXEI8_V_M1_M4_MASK\0" + /* 223349 */ "PseudoVLUXEI8_V_M1_M4_MASK\0" + /* 223376 */ "PseudoVSUXEI8_V_M1_M4_MASK\0" + /* 223403 */ "PseudoVFSUB_VF32_M4_MASK\0" + /* 223428 */ "PseudoVFMSUB_VF32_M4_MASK\0" + /* 223454 */ "PseudoVFNMSUB_VF32_M4_MASK\0" + /* 223481 */ "PseudoVFRSUB_VF32_M4_MASK\0" + /* 223507 */ "PseudoVFWSUB_VF32_M4_MASK\0" + /* 223533 */ "PseudoVFMSAC_VF32_M4_MASK\0" + /* 223559 */ "PseudoVFNMSAC_VF32_M4_MASK\0" + /* 223586 */ "PseudoVFWNMSAC_VF32_M4_MASK\0" + /* 223614 */ "PseudoVFWMSAC_VF32_M4_MASK\0" + /* 223641 */ "PseudoVFMACC_VF32_M4_MASK\0" + /* 223667 */ "PseudoVFNMACC_VF32_M4_MASK\0" + /* 223694 */ "PseudoVFWNMACC_VF32_M4_MASK\0" + /* 223722 */ "PseudoVFWMACC_VF32_M4_MASK\0" + /* 223749 */ "PseudoVFADD_VF32_M4_MASK\0" + /* 223774 */ "PseudoVFMADD_VF32_M4_MASK\0" + /* 223800 */ "PseudoVFNMADD_VF32_M4_MASK\0" + /* 223827 */ "PseudoVFWADD_VF32_M4_MASK\0" + /* 223853 */ "PseudoVMFGE_VF32_M4_MASK\0" + /* 223878 */ "PseudoVMFLE_VF32_M4_MASK\0" + /* 223903 */ "PseudoVMFNE_VF32_M4_MASK\0" + /* 223928 */ "PseudoVFSGNJ_VF32_M4_MASK\0" + /* 223954 */ "PseudoVFMUL_VF32_M4_MASK\0" + /* 223979 */ "PseudoVFWMUL_VF32_M4_MASK\0" + /* 224005 */ "PseudoVFMIN_VF32_M4_MASK\0" + /* 224030 */ "PseudoVFSGNJN_VF32_M4_MASK\0" + /* 224057 */ "PseudoVFSLIDE1DOWN_VF32_M4_MASK\0" + /* 224089 */ "PseudoVFSLIDE1UP_VF32_M4_MASK\0" + /* 224119 */ "PseudoVMFEQ_VF32_M4_MASK\0" + /* 224144 */ "PseudoVMFGT_VF32_M4_MASK\0" + /* 224169 */ "PseudoVMFLT_VF32_M4_MASK\0" + /* 224194 */ "PseudoVFDIV_VF32_M4_MASK\0" + /* 224219 */ "PseudoVFRDIV_VF32_M4_MASK\0" + /* 224245 */ "PseudoVFMAX_VF32_M4_MASK\0" + /* 224270 */ "PseudoVFSGNJX_VF32_M4_MASK\0" + /* 224297 */ "PseudoVFWSUB_WF32_M4_MASK\0" + /* 224323 */ "PseudoVFWADD_WF32_M4_MASK\0" + /* 224349 */ "PseudoVLOXSEG2EI8_V_MF2_M4_MASK\0" + /* 224381 */ "PseudoVSOXSEG2EI8_V_MF2_M4_MASK\0" + /* 224413 */ "PseudoVLUXSEG2EI8_V_MF2_M4_MASK\0" + /* 224445 */ "PseudoVSUXSEG2EI8_V_MF2_M4_MASK\0" + /* 224477 */ "PseudoVLOXEI8_V_MF2_M4_MASK\0" + /* 224505 */ "PseudoVSOXEI8_V_MF2_M4_MASK\0" + /* 224533 */ "PseudoVLUXEI8_V_MF2_M4_MASK\0" + /* 224561 */ "PseudoVSUXEI8_V_MF2_M4_MASK\0" + /* 224589 */ "PseudoVSEXT_VF2_M4_MASK\0" + /* 224613 */ "PseudoVZEXT_VF2_M4_MASK\0" + /* 224637 */ "PseudoVAMOADDEI64_WD_M2_M4_MASK\0" + /* 224669 */ "PseudoVAMOANDEI64_WD_M2_M4_MASK\0" + /* 224701 */ "PseudoVAMOMINEI64_WD_M2_M4_MASK\0" + /* 224733 */ "PseudoVAMOSWAPEI64_WD_M2_M4_MASK\0" + /* 224766 */ "PseudoVAMOOREI64_WD_M2_M4_MASK\0" + /* 224797 */ "PseudoVAMOXOREI64_WD_M2_M4_MASK\0" + /* 224829 */ "PseudoVAMOMINUEI64_WD_M2_M4_MASK\0" + /* 224862 */ "PseudoVAMOMAXUEI64_WD_M2_M4_MASK\0" + /* 224895 */ "PseudoVAMOMAXEI64_WD_M2_M4_MASK\0" + /* 224927 */ "PseudoVRGATHEREI16_VV_M2_M4_MASK\0" + /* 224960 */ "PseudoVLOXSEG2EI32_V_M2_M4_MASK\0" + /* 224992 */ "PseudoVSOXSEG2EI32_V_M2_M4_MASK\0" + /* 225024 */ "PseudoVLUXSEG2EI32_V_M2_M4_MASK\0" + /* 225056 */ "PseudoVSUXSEG2EI32_V_M2_M4_MASK\0" + /* 225088 */ "PseudoVLOXEI32_V_M2_M4_MASK\0" + /* 225116 */ "PseudoVSOXEI32_V_M2_M4_MASK\0" + /* 225144 */ "PseudoVLUXEI32_V_M2_M4_MASK\0" + /* 225172 */ "PseudoVSUXEI32_V_M2_M4_MASK\0" + /* 225200 */ "PseudoVLOXSEG2EI16_V_M2_M4_MASK\0" + /* 225232 */ "PseudoVSOXSEG2EI16_V_M2_M4_MASK\0" + /* 225264 */ "PseudoVLUXSEG2EI16_V_M2_M4_MASK\0" + /* 225296 */ "PseudoVSUXSEG2EI16_V_M2_M4_MASK\0" + /* 225328 */ "PseudoVLOXEI16_V_M2_M4_MASK\0" + /* 225356 */ "PseudoVSOXEI16_V_M2_M4_MASK\0" + /* 225384 */ "PseudoVLUXEI16_V_M2_M4_MASK\0" + /* 225412 */ "PseudoVSUXEI16_V_M2_M4_MASK\0" + /* 225440 */ "PseudoVLOXSEG2EI8_V_M2_M4_MASK\0" + /* 225471 */ "PseudoVSOXSEG2EI8_V_M2_M4_MASK\0" + /* 225502 */ "PseudoVLUXSEG2EI8_V_M2_M4_MASK\0" + /* 225533 */ "PseudoVSUXSEG2EI8_V_M2_M4_MASK\0" + /* 225564 */ "PseudoVLOXEI8_V_M2_M4_MASK\0" + /* 225591 */ "PseudoVSOXEI8_V_M2_M4_MASK\0" + /* 225618 */ "PseudoVLUXEI8_V_M2_M4_MASK\0" + /* 225645 */ "PseudoVSUXEI8_V_M2_M4_MASK\0" + /* 225672 */ "PseudoVFSUB_VF64_M4_MASK\0" + /* 225697 */ "PseudoVFMSUB_VF64_M4_MASK\0" + /* 225723 */ "PseudoVFNMSUB_VF64_M4_MASK\0" + /* 225750 */ "PseudoVFRSUB_VF64_M4_MASK\0" + /* 225776 */ "PseudoVFMSAC_VF64_M4_MASK\0" + /* 225802 */ "PseudoVFNMSAC_VF64_M4_MASK\0" + /* 225829 */ "PseudoVFMACC_VF64_M4_MASK\0" + /* 225855 */ "PseudoVFNMACC_VF64_M4_MASK\0" + /* 225882 */ "PseudoVFADD_VF64_M4_MASK\0" + /* 225907 */ "PseudoVFMADD_VF64_M4_MASK\0" + /* 225933 */ "PseudoVFNMADD_VF64_M4_MASK\0" + /* 225960 */ "PseudoVMFGE_VF64_M4_MASK\0" + /* 225985 */ "PseudoVMFLE_VF64_M4_MASK\0" + /* 226010 */ "PseudoVMFNE_VF64_M4_MASK\0" + /* 226035 */ "PseudoVFSGNJ_VF64_M4_MASK\0" + /* 226061 */ "PseudoVFMUL_VF64_M4_MASK\0" + /* 226086 */ "PseudoVFMIN_VF64_M4_MASK\0" + /* 226111 */ "PseudoVFSGNJN_VF64_M4_MASK\0" + /* 226138 */ "PseudoVFSLIDE1DOWN_VF64_M4_MASK\0" + /* 226170 */ "PseudoVFSLIDE1UP_VF64_M4_MASK\0" + /* 226200 */ "PseudoVMFEQ_VF64_M4_MASK\0" + /* 226225 */ "PseudoVMFGT_VF64_M4_MASK\0" + /* 226250 */ "PseudoVMFLT_VF64_M4_MASK\0" + /* 226275 */ "PseudoVFDIV_VF64_M4_MASK\0" + /* 226300 */ "PseudoVFRDIV_VF64_M4_MASK\0" + /* 226326 */ "PseudoVFMAX_VF64_M4_MASK\0" + /* 226351 */ "PseudoVFSGNJX_VF64_M4_MASK\0" + /* 226378 */ "PseudoVSEXT_VF4_M4_MASK\0" + /* 226402 */ "PseudoVZEXT_VF4_M4_MASK\0" + /* 226426 */ "PseudoVAMOADDEI32_WD_M4_M4_MASK\0" + /* 226458 */ "PseudoVAMOANDEI32_WD_M4_M4_MASK\0" + /* 226490 */ "PseudoVAMOMINEI32_WD_M4_M4_MASK\0" + /* 226522 */ "PseudoVAMOSWAPEI32_WD_M4_M4_MASK\0" + /* 226555 */ "PseudoVAMOOREI32_WD_M4_M4_MASK\0" + /* 226586 */ "PseudoVAMOXOREI32_WD_M4_M4_MASK\0" + /* 226618 */ "PseudoVAMOMINUEI32_WD_M4_M4_MASK\0" + /* 226651 */ "PseudoVAMOMAXUEI32_WD_M4_M4_MASK\0" + /* 226684 */ "PseudoVAMOMAXEI32_WD_M4_M4_MASK\0" + /* 226716 */ "PseudoVAMOADDEI64_WD_M4_M4_MASK\0" + /* 226748 */ "PseudoVAMOANDEI64_WD_M4_M4_MASK\0" + /* 226780 */ "PseudoVAMOMINEI64_WD_M4_M4_MASK\0" + /* 226812 */ "PseudoVAMOSWAPEI64_WD_M4_M4_MASK\0" + /* 226845 */ "PseudoVAMOOREI64_WD_M4_M4_MASK\0" + /* 226876 */ "PseudoVAMOXOREI64_WD_M4_M4_MASK\0" + /* 226908 */ "PseudoVAMOMINUEI64_WD_M4_M4_MASK\0" + /* 226941 */ "PseudoVAMOMAXUEI64_WD_M4_M4_MASK\0" + /* 226974 */ "PseudoVAMOMAXEI64_WD_M4_M4_MASK\0" + /* 227006 */ "PseudoVRGATHEREI16_VV_M4_M4_MASK\0" + /* 227039 */ "PseudoVLOXSEG2EI32_V_M4_M4_MASK\0" + /* 227071 */ "PseudoVSOXSEG2EI32_V_M4_M4_MASK\0" + /* 227103 */ "PseudoVLUXSEG2EI32_V_M4_M4_MASK\0" + /* 227135 */ "PseudoVSUXSEG2EI32_V_M4_M4_MASK\0" + /* 227167 */ "PseudoVLOXEI32_V_M4_M4_MASK\0" + /* 227195 */ "PseudoVSOXEI32_V_M4_M4_MASK\0" + /* 227223 */ "PseudoVLUXEI32_V_M4_M4_MASK\0" + /* 227251 */ "PseudoVSUXEI32_V_M4_M4_MASK\0" + /* 227279 */ "PseudoVLOXSEG2EI64_V_M4_M4_MASK\0" + /* 227311 */ "PseudoVSOXSEG2EI64_V_M4_M4_MASK\0" + /* 227343 */ "PseudoVLUXSEG2EI64_V_M4_M4_MASK\0" + /* 227375 */ "PseudoVSUXSEG2EI64_V_M4_M4_MASK\0" + /* 227407 */ "PseudoVLOXEI64_V_M4_M4_MASK\0" + /* 227435 */ "PseudoVSOXEI64_V_M4_M4_MASK\0" + /* 227463 */ "PseudoVLUXEI64_V_M4_M4_MASK\0" + /* 227491 */ "PseudoVSUXEI64_V_M4_M4_MASK\0" + /* 227519 */ "PseudoVLOXSEG2EI16_V_M4_M4_MASK\0" + /* 227551 */ "PseudoVSOXSEG2EI16_V_M4_M4_MASK\0" + /* 227583 */ "PseudoVLUXSEG2EI16_V_M4_M4_MASK\0" + /* 227615 */ "PseudoVSUXSEG2EI16_V_M4_M4_MASK\0" + /* 227647 */ "PseudoVLOXEI16_V_M4_M4_MASK\0" + /* 227675 */ "PseudoVSOXEI16_V_M4_M4_MASK\0" + /* 227703 */ "PseudoVLUXEI16_V_M4_M4_MASK\0" + /* 227731 */ "PseudoVSUXEI16_V_M4_M4_MASK\0" + /* 227759 */ "PseudoVLOXSEG2EI8_V_M4_M4_MASK\0" + /* 227790 */ "PseudoVSOXSEG2EI8_V_M4_M4_MASK\0" + /* 227821 */ "PseudoVLUXSEG2EI8_V_M4_M4_MASK\0" + /* 227852 */ "PseudoVSUXSEG2EI8_V_M4_M4_MASK\0" + /* 227883 */ "PseudoVLOXEI8_V_M4_M4_MASK\0" + /* 227910 */ "PseudoVSOXEI8_V_M4_M4_MASK\0" + /* 227937 */ "PseudoVLUXEI8_V_M4_M4_MASK\0" + /* 227964 */ "PseudoVSUXEI8_V_M4_M4_MASK\0" + /* 227991 */ "PseudoVFSUB_VF16_M4_MASK\0" + /* 228016 */ "PseudoVFMSUB_VF16_M4_MASK\0" + /* 228042 */ "PseudoVFNMSUB_VF16_M4_MASK\0" + /* 228069 */ "PseudoVFRSUB_VF16_M4_MASK\0" + /* 228095 */ "PseudoVFWSUB_VF16_M4_MASK\0" + /* 228121 */ "PseudoVFMSAC_VF16_M4_MASK\0" + /* 228147 */ "PseudoVFNMSAC_VF16_M4_MASK\0" + /* 228174 */ "PseudoVFWNMSAC_VF16_M4_MASK\0" + /* 228202 */ "PseudoVFWMSAC_VF16_M4_MASK\0" + /* 228229 */ "PseudoVFMACC_VF16_M4_MASK\0" + /* 228255 */ "PseudoVFNMACC_VF16_M4_MASK\0" + /* 228282 */ "PseudoVFWNMACC_VF16_M4_MASK\0" + /* 228310 */ "PseudoVFWMACC_VF16_M4_MASK\0" + /* 228337 */ "PseudoVFADD_VF16_M4_MASK\0" + /* 228362 */ "PseudoVFMADD_VF16_M4_MASK\0" + /* 228388 */ "PseudoVFNMADD_VF16_M4_MASK\0" + /* 228415 */ "PseudoVFWADD_VF16_M4_MASK\0" + /* 228441 */ "PseudoVMFGE_VF16_M4_MASK\0" + /* 228466 */ "PseudoVMFLE_VF16_M4_MASK\0" + /* 228491 */ "PseudoVMFNE_VF16_M4_MASK\0" + /* 228516 */ "PseudoVFSGNJ_VF16_M4_MASK\0" + /* 228542 */ "PseudoVFMUL_VF16_M4_MASK\0" + /* 228567 */ "PseudoVFWMUL_VF16_M4_MASK\0" + /* 228593 */ "PseudoVFMIN_VF16_M4_MASK\0" + /* 228618 */ "PseudoVFSGNJN_VF16_M4_MASK\0" + /* 228645 */ "PseudoVFSLIDE1DOWN_VF16_M4_MASK\0" + /* 228677 */ "PseudoVFSLIDE1UP_VF16_M4_MASK\0" + /* 228707 */ "PseudoVMFEQ_VF16_M4_MASK\0" + /* 228732 */ "PseudoVMFGT_VF16_M4_MASK\0" + /* 228757 */ "PseudoVMFLT_VF16_M4_MASK\0" + /* 228782 */ "PseudoVFDIV_VF16_M4_MASK\0" + /* 228807 */ "PseudoVFRDIV_VF16_M4_MASK\0" + /* 228833 */ "PseudoVFMAX_VF16_M4_MASK\0" + /* 228858 */ "PseudoVFSGNJX_VF16_M4_MASK\0" + /* 228885 */ "PseudoVFWSUB_WF16_M4_MASK\0" + /* 228911 */ "PseudoVFWADD_WF16_M4_MASK\0" + /* 228937 */ "PseudoVSEXT_VF8_M4_MASK\0" + /* 228961 */ "PseudoVZEXT_VF8_M4_MASK\0" + /* 228985 */ "PseudoVAMOADDEI32_WD_M8_M4_MASK\0" + /* 229017 */ "PseudoVAMOANDEI32_WD_M8_M4_MASK\0" + /* 229049 */ "PseudoVAMOMINEI32_WD_M8_M4_MASK\0" + /* 229081 */ "PseudoVAMOSWAPEI32_WD_M8_M4_MASK\0" + /* 229114 */ "PseudoVAMOOREI32_WD_M8_M4_MASK\0" + /* 229145 */ "PseudoVAMOXOREI32_WD_M8_M4_MASK\0" + /* 229177 */ "PseudoVAMOMINUEI32_WD_M8_M4_MASK\0" + /* 229210 */ "PseudoVAMOMAXUEI32_WD_M8_M4_MASK\0" + /* 229243 */ "PseudoVAMOMAXEI32_WD_M8_M4_MASK\0" + /* 229275 */ "PseudoVAMOADDEI16_WD_M8_M4_MASK\0" + /* 229307 */ "PseudoVAMOANDEI16_WD_M8_M4_MASK\0" + /* 229339 */ "PseudoVAMOMINEI16_WD_M8_M4_MASK\0" + /* 229371 */ "PseudoVAMOSWAPEI16_WD_M8_M4_MASK\0" + /* 229404 */ "PseudoVAMOOREI16_WD_M8_M4_MASK\0" + /* 229435 */ "PseudoVAMOXOREI16_WD_M8_M4_MASK\0" + /* 229467 */ "PseudoVAMOMINUEI16_WD_M8_M4_MASK\0" + /* 229500 */ "PseudoVAMOMAXUEI16_WD_M8_M4_MASK\0" + /* 229533 */ "PseudoVAMOMAXEI16_WD_M8_M4_MASK\0" + /* 229565 */ "PseudoVRGATHEREI16_VV_M8_M4_MASK\0" + /* 229598 */ "PseudoVLOXSEG2EI32_V_M8_M4_MASK\0" + /* 229630 */ "PseudoVSOXSEG2EI32_V_M8_M4_MASK\0" + /* 229662 */ "PseudoVLUXSEG2EI32_V_M8_M4_MASK\0" + /* 229694 */ "PseudoVSUXSEG2EI32_V_M8_M4_MASK\0" + /* 229726 */ "PseudoVLOXEI32_V_M8_M4_MASK\0" + /* 229754 */ "PseudoVSOXEI32_V_M8_M4_MASK\0" + /* 229782 */ "PseudoVLUXEI32_V_M8_M4_MASK\0" + /* 229810 */ "PseudoVSUXEI32_V_M8_M4_MASK\0" + /* 229838 */ "PseudoVLOXSEG2EI64_V_M8_M4_MASK\0" + /* 229870 */ "PseudoVSOXSEG2EI64_V_M8_M4_MASK\0" + /* 229902 */ "PseudoVLUXSEG2EI64_V_M8_M4_MASK\0" + /* 229934 */ "PseudoVSUXSEG2EI64_V_M8_M4_MASK\0" + /* 229966 */ "PseudoVLOXEI64_V_M8_M4_MASK\0" + /* 229994 */ "PseudoVSOXEI64_V_M8_M4_MASK\0" + /* 230022 */ "PseudoVLUXEI64_V_M8_M4_MASK\0" + /* 230050 */ "PseudoVSUXEI64_V_M8_M4_MASK\0" + /* 230078 */ "PseudoVLOXSEG2EI16_V_M8_M4_MASK\0" + /* 230110 */ "PseudoVSOXSEG2EI16_V_M8_M4_MASK\0" + /* 230142 */ "PseudoVLUXSEG2EI16_V_M8_M4_MASK\0" + /* 230174 */ "PseudoVSUXSEG2EI16_V_M8_M4_MASK\0" + /* 230206 */ "PseudoVLOXEI16_V_M8_M4_MASK\0" + /* 230234 */ "PseudoVSOXEI16_V_M8_M4_MASK\0" + /* 230262 */ "PseudoVLUXEI16_V_M8_M4_MASK\0" + /* 230290 */ "PseudoVSUXEI16_V_M8_M4_MASK\0" + /* 230318 */ "PseudoVSSRA_VI_M4_MASK\0" + /* 230341 */ "PseudoVSRA_VI_M4_MASK\0" + /* 230363 */ "PseudoVRSUB_VI_M4_MASK\0" + /* 230386 */ "PseudoVSADD_VI_M4_MASK\0" + /* 230409 */ "PseudoVADD_VI_M4_MASK\0" + /* 230431 */ "PseudoVAND_VI_M4_MASK\0" + /* 230453 */ "PseudoVMSLE_VI_M4_MASK\0" + /* 230476 */ "PseudoVMSNE_VI_M4_MASK\0" + /* 230499 */ "PseudoVSLL_VI_M4_MASK\0" + /* 230521 */ "PseudoVSSRL_VI_M4_MASK\0" + /* 230544 */ "PseudoVSRL_VI_M4_MASK\0" + /* 230566 */ "PseudoVSLIDEDOWN_VI_M4_MASK\0" + /* 230594 */ "PseudoVSLIDEUP_VI_M4_MASK\0" + /* 230620 */ "PseudoVMSEQ_VI_M4_MASK\0" + /* 230643 */ "PseudoVRGATHER_VI_M4_MASK\0" + /* 230669 */ "PseudoVOR_VI_M4_MASK\0" + /* 230690 */ "PseudoVXOR_VI_M4_MASK\0" + /* 230712 */ "PseudoVMSGT_VI_M4_MASK\0" + /* 230735 */ "PseudoVSADDU_VI_M4_MASK\0" + /* 230759 */ "PseudoVMSLEU_VI_M4_MASK\0" + /* 230783 */ "PseudoVMSGTU_VI_M4_MASK\0" + /* 230807 */ "PseudoVNSRA_WI_M4_MASK\0" + /* 230830 */ "PseudoVNSRL_WI_M4_MASK\0" + /* 230853 */ "PseudoVNCLIP_WI_M4_MASK\0" + /* 230877 */ "PseudoVNCLIPU_WI_M4_MASK\0" + /* 230902 */ "PseudoVIOTA_M_M4_MASK\0" + /* 230924 */ "PseudoVREDAND_VS_M4_MASK\0" + /* 230949 */ "PseudoVREDSUM_VS_M4_MASK\0" + /* 230974 */ "PseudoVWREDSUM_VS_M4_MASK\0" + /* 231000 */ "PseudoVFREDOSUM_VS_M4_MASK\0" + /* 231027 */ "PseudoVFWREDOSUM_VS_M4_MASK\0" + /* 231055 */ "PseudoVFREDUSUM_VS_M4_MASK\0" + /* 231082 */ "PseudoVFWREDUSUM_VS_M4_MASK\0" + /* 231110 */ "PseudoVFREDMIN_VS_M4_MASK\0" + /* 231136 */ "PseudoVREDMIN_VS_M4_MASK\0" + /* 231161 */ "PseudoVREDOR_VS_M4_MASK\0" + /* 231185 */ "PseudoVREDXOR_VS_M4_MASK\0" + /* 231210 */ "PseudoVWREDSUMU_VS_M4_MASK\0" + /* 231237 */ "PseudoVREDMINU_VS_M4_MASK\0" + /* 231263 */ "PseudoVREDMAXU_VS_M4_MASK\0" + /* 231289 */ "PseudoVFREDMAX_VS_M4_MASK\0" + /* 231315 */ "PseudoVREDMAX_VS_M4_MASK\0" + /* 231340 */ "PseudoVSSRA_VV_M4_MASK\0" + /* 231363 */ "PseudoVSRA_VV_M4_MASK\0" + /* 231385 */ "PseudoVASUB_VV_M4_MASK\0" + /* 231408 */ "PseudoVFSUB_VV_M4_MASK\0" + /* 231431 */ "PseudoVFMSUB_VV_M4_MASK\0" + /* 231455 */ "PseudoVFNMSUB_VV_M4_MASK\0" + /* 231480 */ "PseudoVNMSUB_VV_M4_MASK\0" + /* 231504 */ "PseudoVSSUB_VV_M4_MASK\0" + /* 231527 */ "PseudoVSUB_VV_M4_MASK\0" + /* 231549 */ "PseudoVFWSUB_VV_M4_MASK\0" + /* 231573 */ "PseudoVWSUB_VV_M4_MASK\0" + /* 231596 */ "PseudoVFMSAC_VV_M4_MASK\0" + /* 231620 */ "PseudoVFNMSAC_VV_M4_MASK\0" + /* 231645 */ "PseudoVNMSAC_VV_M4_MASK\0" + /* 231669 */ "PseudoVFWNMSAC_VV_M4_MASK\0" + /* 231695 */ "PseudoVFWMSAC_VV_M4_MASK\0" + /* 231720 */ "PseudoVFMACC_VV_M4_MASK\0" + /* 231744 */ "PseudoVFNMACC_VV_M4_MASK\0" + /* 231769 */ "PseudoVFWNMACC_VV_M4_MASK\0" + /* 231795 */ "PseudoVMACC_VV_M4_MASK\0" + /* 231818 */ "PseudoVFWMACC_VV_M4_MASK\0" + /* 231843 */ "PseudoVWMACC_VV_M4_MASK\0" + /* 231867 */ "PseudoVAADD_VV_M4_MASK\0" + /* 231890 */ "PseudoVFADD_VV_M4_MASK\0" + /* 231913 */ "PseudoVFMADD_VV_M4_MASK\0" + /* 231937 */ "PseudoVFNMADD_VV_M4_MASK\0" + /* 231962 */ "PseudoVMADD_VV_M4_MASK\0" + /* 231985 */ "PseudoVSADD_VV_M4_MASK\0" + /* 232008 */ "PseudoVADD_VV_M4_MASK\0" + /* 232030 */ "PseudoVFWADD_VV_M4_MASK\0" + /* 232054 */ "PseudoVWADD_VV_M4_MASK\0" + /* 232077 */ "PseudoVAND_VV_M4_MASK\0" + /* 232099 */ "PseudoVMFLE_VV_M4_MASK\0" + /* 232122 */ "PseudoVMSLE_VV_M4_MASK\0" + /* 232145 */ "PseudoVMFNE_VV_M4_MASK\0" + /* 232168 */ "PseudoVMSNE_VV_M4_MASK\0" + /* 232191 */ "PseudoVMULH_VV_M4_MASK\0" + /* 232214 */ "PseudoVFSGNJ_VV_M4_MASK\0" + /* 232238 */ "PseudoVSLL_VV_M4_MASK\0" + /* 232260 */ "PseudoVSSRL_VV_M4_MASK\0" + /* 232283 */ "PseudoVSRL_VV_M4_MASK\0" + /* 232305 */ "PseudoVFMUL_VV_M4_MASK\0" + /* 232328 */ "PseudoVSMUL_VV_M4_MASK\0" + /* 232351 */ "PseudoVMUL_VV_M4_MASK\0" + /* 232373 */ "PseudoVFWMUL_VV_M4_MASK\0" + /* 232397 */ "PseudoVWMUL_VV_M4_MASK\0" + /* 232420 */ "PseudoVREM_VV_M4_MASK\0" + /* 232442 */ "PseudoVFMIN_VV_M4_MASK\0" + /* 232465 */ "PseudoVMIN_VV_M4_MASK\0" + /* 232487 */ "PseudoVFSGNJN_VV_M4_MASK\0" + /* 232512 */ "PseudoVMFEQ_VV_M4_MASK\0" + /* 232535 */ "PseudoVMSEQ_VV_M4_MASK\0" + /* 232558 */ "PseudoVRGATHER_VV_M4_MASK\0" + /* 232584 */ "PseudoVOR_VV_M4_MASK\0" + /* 232605 */ "PseudoVXOR_VV_M4_MASK\0" + /* 232627 */ "PseudoVMFLT_VV_M4_MASK\0" + /* 232650 */ "PseudoVMSLT_VV_M4_MASK\0" + /* 232673 */ "PseudoVASUBU_VV_M4_MASK\0" + /* 232697 */ "PseudoVSSUBU_VV_M4_MASK\0" + /* 232721 */ "PseudoVWSUBU_VV_M4_MASK\0" + /* 232745 */ "PseudoVWMACCU_VV_M4_MASK\0" + /* 232770 */ "PseudoVAADDU_VV_M4_MASK\0" + /* 232794 */ "PseudoVSADDU_VV_M4_MASK\0" + /* 232818 */ "PseudoVWADDU_VV_M4_MASK\0" + /* 232842 */ "PseudoVMSLEU_VV_M4_MASK\0" + /* 232866 */ "PseudoVMULHU_VV_M4_MASK\0" + /* 232890 */ "PseudoVWMULU_VV_M4_MASK\0" + /* 232914 */ "PseudoVREMU_VV_M4_MASK\0" + /* 232937 */ "PseudoVMINU_VV_M4_MASK\0" + /* 232960 */ "PseudoVWMACCSU_VV_M4_MASK\0" + /* 232986 */ "PseudoVMULHSU_VV_M4_MASK\0" + /* 233011 */ "PseudoVWMULSU_VV_M4_MASK\0" + /* 233036 */ "PseudoVMSLTU_VV_M4_MASK\0" + /* 233060 */ "PseudoVDIVU_VV_M4_MASK\0" + /* 233083 */ "PseudoVMAXU_VV_M4_MASK\0" + /* 233106 */ "PseudoVFDIV_VV_M4_MASK\0" + /* 233129 */ "PseudoVDIV_VV_M4_MASK\0" + /* 233151 */ "PseudoVFMAX_VV_M4_MASK\0" + /* 233174 */ "PseudoVMAX_VV_M4_MASK\0" + /* 233196 */ "PseudoVFSGNJX_VV_M4_MASK\0" + /* 233221 */ "PseudoVNSRA_WV_M4_MASK\0" + /* 233244 */ "PseudoVFWSUB_WV_M4_MASK\0" + /* 233268 */ "PseudoVWSUB_WV_M4_MASK\0" + /* 233291 */ "PseudoVFWADD_WV_M4_MASK\0" + /* 233315 */ "PseudoVWADD_WV_M4_MASK\0" + /* 233338 */ "PseudoVNSRL_WV_M4_MASK\0" + /* 233361 */ "PseudoVNCLIP_WV_M4_MASK\0" + /* 233385 */ "PseudoVWSUBU_WV_M4_MASK\0" + /* 233409 */ "PseudoVWADDU_WV_M4_MASK\0" + /* 233433 */ "PseudoVNCLIPU_WV_M4_MASK\0" + /* 233458 */ "PseudoVLSEG2E32_V_M4_MASK\0" + /* 233484 */ "PseudoVLSSEG2E32_V_M4_MASK\0" + /* 233511 */ "PseudoVSSSEG2E32_V_M4_MASK\0" + /* 233538 */ "PseudoVSSEG2E32_V_M4_MASK\0" + /* 233564 */ "PseudoVLE32_V_M4_MASK\0" + /* 233586 */ "PseudoVLSE32_V_M4_MASK\0" + /* 233609 */ "PseudoVSSE32_V_M4_MASK\0" + /* 233632 */ "PseudoVSE32_V_M4_MASK\0" + /* 233654 */ "PseudoVLSEG2E64_V_M4_MASK\0" + /* 233680 */ "PseudoVLSSEG2E64_V_M4_MASK\0" + /* 233707 */ "PseudoVSSSEG2E64_V_M4_MASK\0" + /* 233734 */ "PseudoVSSEG2E64_V_M4_MASK\0" + /* 233760 */ "PseudoVLE64_V_M4_MASK\0" + /* 233782 */ "PseudoVLSE64_V_M4_MASK\0" + /* 233805 */ "PseudoVSSE64_V_M4_MASK\0" + /* 233828 */ "PseudoVSE64_V_M4_MASK\0" + /* 233850 */ "PseudoVLSEG2E16_V_M4_MASK\0" + /* 233876 */ "PseudoVLSSEG2E16_V_M4_MASK\0" + /* 233903 */ "PseudoVSSSEG2E16_V_M4_MASK\0" + /* 233930 */ "PseudoVSSEG2E16_V_M4_MASK\0" + /* 233956 */ "PseudoVLE16_V_M4_MASK\0" + /* 233978 */ "PseudoVLSE16_V_M4_MASK\0" + /* 234001 */ "PseudoVSSE16_V_M4_MASK\0" + /* 234024 */ "PseudoVSE16_V_M4_MASK\0" + /* 234046 */ "PseudoVFREC7_V_M4_MASK\0" + /* 234069 */ "PseudoVFRSQRT7_V_M4_MASK\0" + /* 234094 */ "PseudoVLSEG2E8_V_M4_MASK\0" + /* 234119 */ "PseudoVLSSEG2E8_V_M4_MASK\0" + /* 234145 */ "PseudoVSSSEG2E8_V_M4_MASK\0" + /* 234171 */ "PseudoVSSEG2E8_V_M4_MASK\0" + /* 234196 */ "PseudoVLE8_V_M4_MASK\0" + /* 234217 */ "PseudoVLSE8_V_M4_MASK\0" + /* 234239 */ "PseudoVSSE8_V_M4_MASK\0" + /* 234261 */ "PseudoVSE8_V_M4_MASK\0" + /* 234282 */ "PseudoVID_V_M4_MASK\0" + /* 234302 */ "PseudoVLSEG2E32FF_V_M4_MASK\0" + /* 234330 */ "PseudoVLE32FF_V_M4_MASK\0" + /* 234354 */ "PseudoVLSEG2E64FF_V_M4_MASK\0" + /* 234382 */ "PseudoVLE64FF_V_M4_MASK\0" + /* 234406 */ "PseudoVLSEG2E16FF_V_M4_MASK\0" + /* 234434 */ "PseudoVLE16FF_V_M4_MASK\0" + /* 234458 */ "PseudoVLSEG2E8FF_V_M4_MASK\0" + /* 234485 */ "PseudoVLE8FF_V_M4_MASK\0" + /* 234508 */ "PseudoVFWCVT_F_F_V_M4_MASK\0" + /* 234535 */ "PseudoVFCVT_XU_F_V_M4_MASK\0" + /* 234562 */ "PseudoVFWCVT_XU_F_V_M4_MASK\0" + /* 234590 */ "PseudoVFCVT_RTZ_XU_F_V_M4_MASK\0" + /* 234621 */ "PseudoVFWCVT_RTZ_XU_F_V_M4_MASK\0" + /* 234653 */ "PseudoVFCVT_X_F_V_M4_MASK\0" + /* 234679 */ "PseudoVFWCVT_X_F_V_M4_MASK\0" + /* 234706 */ "PseudoVFCVT_RTZ_X_F_V_M4_MASK\0" + /* 234736 */ "PseudoVFWCVT_RTZ_X_F_V_M4_MASK\0" + /* 234767 */ "PseudoVFCLASS_V_M4_MASK\0" + /* 234791 */ "PseudoVFSQRT_V_M4_MASK\0" + /* 234814 */ "PseudoVFCVT_F_XU_V_M4_MASK\0" + /* 234841 */ "PseudoVFWCVT_F_XU_V_M4_MASK\0" + /* 234869 */ "PseudoVFCVT_F_X_V_M4_MASK\0" + /* 234895 */ "PseudoVFWCVT_F_X_V_M4_MASK\0" + /* 234922 */ "PseudoVFNCVT_ROD_F_F_W_M4_MASK\0" + /* 234953 */ "PseudoVFNCVT_F_F_W_M4_MASK\0" + /* 234980 */ "PseudoVFNCVT_XU_F_W_M4_MASK\0" + /* 235008 */ "PseudoVFNCVT_RTZ_XU_F_W_M4_MASK\0" + /* 235040 */ "PseudoVFNCVT_X_F_W_M4_MASK\0" + /* 235067 */ "PseudoVFNCVT_RTZ_X_F_W_M4_MASK\0" + /* 235098 */ "PseudoVFNCVT_F_XU_W_M4_MASK\0" + /* 235126 */ "PseudoVFNCVT_F_X_W_M4_MASK\0" + /* 235153 */ "PseudoVSSRA_VX_M4_MASK\0" + /* 235176 */ "PseudoVSRA_VX_M4_MASK\0" + /* 235198 */ "PseudoVASUB_VX_M4_MASK\0" + /* 235221 */ "PseudoVNMSUB_VX_M4_MASK\0" + /* 235245 */ "PseudoVRSUB_VX_M4_MASK\0" + /* 235268 */ "PseudoVSSUB_VX_M4_MASK\0" + /* 235291 */ "PseudoVSUB_VX_M4_MASK\0" + /* 235313 */ "PseudoVWSUB_VX_M4_MASK\0" + /* 235336 */ "PseudoVNMSAC_VX_M4_MASK\0" + /* 235360 */ "PseudoVMACC_VX_M4_MASK\0" + /* 235383 */ "PseudoVWMACC_VX_M4_MASK\0" + /* 235407 */ "PseudoVAADD_VX_M4_MASK\0" + /* 235430 */ "PseudoVMADD_VX_M4_MASK\0" + /* 235453 */ "PseudoVSADD_VX_M4_MASK\0" + /* 235476 */ "PseudoVADD_VX_M4_MASK\0" + /* 235498 */ "PseudoVWADD_VX_M4_MASK\0" + /* 235521 */ "PseudoVAND_VX_M4_MASK\0" + /* 235543 */ "PseudoVMSLE_VX_M4_MASK\0" + /* 235566 */ "PseudoVMSNE_VX_M4_MASK\0" + /* 235589 */ "PseudoVMULH_VX_M4_MASK\0" + /* 235612 */ "PseudoVSLL_VX_M4_MASK\0" + /* 235634 */ "PseudoVSSRL_VX_M4_MASK\0" + /* 235657 */ "PseudoVSRL_VX_M4_MASK\0" + /* 235679 */ "PseudoVSMUL_VX_M4_MASK\0" + /* 235702 */ "PseudoVMUL_VX_M4_MASK\0" + /* 235724 */ "PseudoVWMUL_VX_M4_MASK\0" + /* 235747 */ "PseudoVREM_VX_M4_MASK\0" + /* 235769 */ "PseudoVMIN_VX_M4_MASK\0" + /* 235791 */ "PseudoVSLIDE1DOWN_VX_M4_MASK\0" + /* 235820 */ "PseudoVSLIDEDOWN_VX_M4_MASK\0" + /* 235848 */ "PseudoVSLIDE1UP_VX_M4_MASK\0" + /* 235875 */ "PseudoVSLIDEUP_VX_M4_MASK\0" + /* 235901 */ "PseudoVMSEQ_VX_M4_MASK\0" + /* 235924 */ "PseudoVRGATHER_VX_M4_MASK\0" + /* 235950 */ "PseudoVOR_VX_M4_MASK\0" + /* 235971 */ "PseudoVXOR_VX_M4_MASK\0" + /* 235993 */ "PseudoVWMACCUS_VX_M4_MASK\0" + /* 236019 */ "PseudoVMSGT_VX_M4_MASK\0" + /* 236042 */ "PseudoVMSLT_VX_M4_MASK\0" + /* 236065 */ "PseudoVASUBU_VX_M4_MASK\0" + /* 236089 */ "PseudoVSSUBU_VX_M4_MASK\0" + /* 236113 */ "PseudoVWSUBU_VX_M4_MASK\0" + /* 236137 */ "PseudoVWMACCU_VX_M4_MASK\0" + /* 236162 */ "PseudoVAADDU_VX_M4_MASK\0" + /* 236186 */ "PseudoVSADDU_VX_M4_MASK\0" + /* 236210 */ "PseudoVWADDU_VX_M4_MASK\0" + /* 236234 */ "PseudoVMSLEU_VX_M4_MASK\0" + /* 236258 */ "PseudoVMULHU_VX_M4_MASK\0" + /* 236282 */ "PseudoVWMULU_VX_M4_MASK\0" + /* 236306 */ "PseudoVREMU_VX_M4_MASK\0" + /* 236329 */ "PseudoVMINU_VX_M4_MASK\0" + /* 236352 */ "PseudoVWMACCSU_VX_M4_MASK\0" + /* 236378 */ "PseudoVMULHSU_VX_M4_MASK\0" + /* 236403 */ "PseudoVWMULSU_VX_M4_MASK\0" + /* 236428 */ "PseudoVMSGTU_VX_M4_MASK\0" + /* 236452 */ "PseudoVMSLTU_VX_M4_MASK\0" + /* 236476 */ "PseudoVDIVU_VX_M4_MASK\0" + /* 236499 */ "PseudoVMAXU_VX_M4_MASK\0" + /* 236522 */ "PseudoVDIV_VX_M4_MASK\0" + /* 236544 */ "PseudoVMAX_VX_M4_MASK\0" + /* 236566 */ "PseudoVNSRA_WX_M4_MASK\0" + /* 236589 */ "PseudoVWSUB_WX_M4_MASK\0" + /* 236612 */ "PseudoVWADD_WX_M4_MASK\0" + /* 236635 */ "PseudoVNSRL_WX_M4_MASK\0" + /* 236658 */ "PseudoVNCLIP_WX_M4_MASK\0" + /* 236682 */ "PseudoVWSUBU_WX_M4_MASK\0" + /* 236706 */ "PseudoVWADDU_WX_M4_MASK\0" + /* 236730 */ "PseudoVNCLIPU_WX_M4_MASK\0" + /* 236755 */ "PseudoVMSBF_M_B16_MASK\0" + /* 236778 */ "PseudoVMSIF_M_B16_MASK\0" + /* 236801 */ "PseudoVMSOF_M_B16_MASK\0" + /* 236824 */ "PseudoVCPOP_M_B16_MASK\0" + /* 236847 */ "PseudoVFIRST_M_B16_MASK\0" + /* 236871 */ "PseudoVMSBF_M_B8_MASK\0" + /* 236893 */ "PseudoVMSIF_M_B8_MASK\0" + /* 236915 */ "PseudoVMSOF_M_B8_MASK\0" + /* 236937 */ "PseudoVCPOP_M_B8_MASK\0" + /* 236959 */ "PseudoVFIRST_M_B8_MASK\0" + /* 236982 */ "PseudoVAMOADDEI8_WD_M1_MF8_MASK\0" + /* 237014 */ "PseudoVAMOANDEI8_WD_M1_MF8_MASK\0" + /* 237046 */ "PseudoVAMOMINEI8_WD_M1_MF8_MASK\0" + /* 237078 */ "PseudoVAMOSWAPEI8_WD_M1_MF8_MASK\0" + /* 237111 */ "PseudoVAMOOREI8_WD_M1_MF8_MASK\0" + /* 237142 */ "PseudoVAMOXOREI8_WD_M1_MF8_MASK\0" + /* 237174 */ "PseudoVAMOMINUEI8_WD_M1_MF8_MASK\0" + /* 237207 */ "PseudoVAMOMAXUEI8_WD_M1_MF8_MASK\0" + /* 237240 */ "PseudoVAMOMAXEI8_WD_M1_MF8_MASK\0" + /* 237272 */ "PseudoVLOXSEG2EI64_V_M1_MF8_MASK\0" + /* 237305 */ "PseudoVSOXSEG2EI64_V_M1_MF8_MASK\0" + /* 237338 */ "PseudoVLUXSEG2EI64_V_M1_MF8_MASK\0" + /* 237371 */ "PseudoVSUXSEG2EI64_V_M1_MF8_MASK\0" + /* 237404 */ "PseudoVLOXSEG3EI64_V_M1_MF8_MASK\0" + /* 237437 */ "PseudoVSOXSEG3EI64_V_M1_MF8_MASK\0" + /* 237470 */ "PseudoVLUXSEG3EI64_V_M1_MF8_MASK\0" + /* 237503 */ "PseudoVSUXSEG3EI64_V_M1_MF8_MASK\0" + /* 237536 */ "PseudoVLOXSEG4EI64_V_M1_MF8_MASK\0" + /* 237569 */ "PseudoVSOXSEG4EI64_V_M1_MF8_MASK\0" + /* 237602 */ "PseudoVLUXSEG4EI64_V_M1_MF8_MASK\0" + /* 237635 */ "PseudoVSUXSEG4EI64_V_M1_MF8_MASK\0" + /* 237668 */ "PseudoVLOXSEG5EI64_V_M1_MF8_MASK\0" + /* 237701 */ "PseudoVSOXSEG5EI64_V_M1_MF8_MASK\0" + /* 237734 */ "PseudoVLUXSEG5EI64_V_M1_MF8_MASK\0" + /* 237767 */ "PseudoVSUXSEG5EI64_V_M1_MF8_MASK\0" + /* 237800 */ "PseudoVLOXSEG6EI64_V_M1_MF8_MASK\0" + /* 237833 */ "PseudoVSOXSEG6EI64_V_M1_MF8_MASK\0" + /* 237866 */ "PseudoVLUXSEG6EI64_V_M1_MF8_MASK\0" + /* 237899 */ "PseudoVSUXSEG6EI64_V_M1_MF8_MASK\0" + /* 237932 */ "PseudoVLOXSEG7EI64_V_M1_MF8_MASK\0" + /* 237965 */ "PseudoVSOXSEG7EI64_V_M1_MF8_MASK\0" + /* 237998 */ "PseudoVLUXSEG7EI64_V_M1_MF8_MASK\0" + /* 238031 */ "PseudoVSUXSEG7EI64_V_M1_MF8_MASK\0" + /* 238064 */ "PseudoVLOXSEG8EI64_V_M1_MF8_MASK\0" + /* 238097 */ "PseudoVSOXSEG8EI64_V_M1_MF8_MASK\0" + /* 238130 */ "PseudoVLUXSEG8EI64_V_M1_MF8_MASK\0" + /* 238163 */ "PseudoVSUXSEG8EI64_V_M1_MF8_MASK\0" + /* 238196 */ "PseudoVLOXEI64_V_M1_MF8_MASK\0" + /* 238225 */ "PseudoVSOXEI64_V_M1_MF8_MASK\0" + /* 238254 */ "PseudoVLUXEI64_V_M1_MF8_MASK\0" + /* 238283 */ "PseudoVSUXEI64_V_M1_MF8_MASK\0" + /* 238312 */ "PseudoVFSUB_VF32_MF8_MASK\0" + /* 238338 */ "PseudoVFMSUB_VF32_MF8_MASK\0" + /* 238365 */ "PseudoVFNMSUB_VF32_MF8_MASK\0" + /* 238393 */ "PseudoVFRSUB_VF32_MF8_MASK\0" + /* 238420 */ "PseudoVFWSUB_VF32_MF8_MASK\0" + /* 238447 */ "PseudoVFMSAC_VF32_MF8_MASK\0" + /* 238474 */ "PseudoVFNMSAC_VF32_MF8_MASK\0" + /* 238502 */ "PseudoVFWNMSAC_VF32_MF8_MASK\0" + /* 238531 */ "PseudoVFWMSAC_VF32_MF8_MASK\0" + /* 238559 */ "PseudoVFMACC_VF32_MF8_MASK\0" + /* 238586 */ "PseudoVFNMACC_VF32_MF8_MASK\0" + /* 238614 */ "PseudoVFWNMACC_VF32_MF8_MASK\0" + /* 238643 */ "PseudoVFWMACC_VF32_MF8_MASK\0" + /* 238671 */ "PseudoVFADD_VF32_MF8_MASK\0" + /* 238697 */ "PseudoVFMADD_VF32_MF8_MASK\0" + /* 238724 */ "PseudoVFNMADD_VF32_MF8_MASK\0" + /* 238752 */ "PseudoVFWADD_VF32_MF8_MASK\0" + /* 238779 */ "PseudoVMFGE_VF32_MF8_MASK\0" + /* 238805 */ "PseudoVMFLE_VF32_MF8_MASK\0" + /* 238831 */ "PseudoVMFNE_VF32_MF8_MASK\0" + /* 238857 */ "PseudoVFSGNJ_VF32_MF8_MASK\0" + /* 238884 */ "PseudoVFMUL_VF32_MF8_MASK\0" + /* 238910 */ "PseudoVFWMUL_VF32_MF8_MASK\0" + /* 238937 */ "PseudoVFMIN_VF32_MF8_MASK\0" + /* 238963 */ "PseudoVFSGNJN_VF32_MF8_MASK\0" + /* 238991 */ "PseudoVFSLIDE1DOWN_VF32_MF8_MASK\0" + /* 239024 */ "PseudoVFSLIDE1UP_VF32_MF8_MASK\0" + /* 239055 */ "PseudoVMFEQ_VF32_MF8_MASK\0" + /* 239081 */ "PseudoVMFGT_VF32_MF8_MASK\0" + /* 239107 */ "PseudoVMFLT_VF32_MF8_MASK\0" + /* 239133 */ "PseudoVFDIV_VF32_MF8_MASK\0" + /* 239159 */ "PseudoVFRDIV_VF32_MF8_MASK\0" + /* 239186 */ "PseudoVFMAX_VF32_MF8_MASK\0" + /* 239212 */ "PseudoVFSGNJX_VF32_MF8_MASK\0" + /* 239240 */ "PseudoVFWSUB_WF32_MF8_MASK\0" + /* 239267 */ "PseudoVFWADD_WF32_MF8_MASK\0" + /* 239294 */ "PseudoVAMOADDEI8_WD_MF2_MF8_MASK\0" + /* 239327 */ "PseudoVAMOANDEI8_WD_MF2_MF8_MASK\0" + /* 239360 */ "PseudoVAMOMINEI8_WD_MF2_MF8_MASK\0" + /* 239393 */ "PseudoVAMOSWAPEI8_WD_MF2_MF8_MASK\0" + /* 239427 */ "PseudoVAMOOREI8_WD_MF2_MF8_MASK\0" + /* 239459 */ "PseudoVAMOXOREI8_WD_MF2_MF8_MASK\0" + /* 239492 */ "PseudoVAMOMINUEI8_WD_MF2_MF8_MASK\0" + /* 239526 */ "PseudoVAMOMAXUEI8_WD_MF2_MF8_MASK\0" + /* 239560 */ "PseudoVAMOMAXEI8_WD_MF2_MF8_MASK\0" + /* 239593 */ "PseudoVRGATHEREI16_VV_MF2_MF8_MASK\0" + /* 239628 */ "PseudoVLOXSEG2EI32_V_MF2_MF8_MASK\0" + /* 239662 */ "PseudoVSOXSEG2EI32_V_MF2_MF8_MASK\0" + /* 239696 */ "PseudoVLUXSEG2EI32_V_MF2_MF8_MASK\0" + /* 239730 */ "PseudoVSUXSEG2EI32_V_MF2_MF8_MASK\0" + /* 239764 */ "PseudoVLOXSEG3EI32_V_MF2_MF8_MASK\0" + /* 239798 */ "PseudoVSOXSEG3EI32_V_MF2_MF8_MASK\0" + /* 239832 */ "PseudoVLUXSEG3EI32_V_MF2_MF8_MASK\0" + /* 239866 */ "PseudoVSUXSEG3EI32_V_MF2_MF8_MASK\0" + /* 239900 */ "PseudoVLOXSEG4EI32_V_MF2_MF8_MASK\0" + /* 239934 */ "PseudoVSOXSEG4EI32_V_MF2_MF8_MASK\0" + /* 239968 */ "PseudoVLUXSEG4EI32_V_MF2_MF8_MASK\0" + /* 240002 */ "PseudoVSUXSEG4EI32_V_MF2_MF8_MASK\0" + /* 240036 */ "PseudoVLOXSEG5EI32_V_MF2_MF8_MASK\0" + /* 240070 */ "PseudoVSOXSEG5EI32_V_MF2_MF8_MASK\0" + /* 240104 */ "PseudoVLUXSEG5EI32_V_MF2_MF8_MASK\0" + /* 240138 */ "PseudoVSUXSEG5EI32_V_MF2_MF8_MASK\0" + /* 240172 */ "PseudoVLOXSEG6EI32_V_MF2_MF8_MASK\0" + /* 240206 */ "PseudoVSOXSEG6EI32_V_MF2_MF8_MASK\0" + /* 240240 */ "PseudoVLUXSEG6EI32_V_MF2_MF8_MASK\0" + /* 240274 */ "PseudoVSUXSEG6EI32_V_MF2_MF8_MASK\0" + /* 240308 */ "PseudoVLOXSEG7EI32_V_MF2_MF8_MASK\0" + /* 240342 */ "PseudoVSOXSEG7EI32_V_MF2_MF8_MASK\0" + /* 240376 */ "PseudoVLUXSEG7EI32_V_MF2_MF8_MASK\0" + /* 240410 */ "PseudoVSUXSEG7EI32_V_MF2_MF8_MASK\0" + /* 240444 */ "PseudoVLOXSEG8EI32_V_MF2_MF8_MASK\0" + /* 240478 */ "PseudoVSOXSEG8EI32_V_MF2_MF8_MASK\0" + /* 240512 */ "PseudoVLUXSEG8EI32_V_MF2_MF8_MASK\0" + /* 240546 */ "PseudoVSUXSEG8EI32_V_MF2_MF8_MASK\0" + /* 240580 */ "PseudoVLOXEI32_V_MF2_MF8_MASK\0" + /* 240610 */ "PseudoVSOXEI32_V_MF2_MF8_MASK\0" + /* 240640 */ "PseudoVLUXEI32_V_MF2_MF8_MASK\0" + /* 240670 */ "PseudoVSUXEI32_V_MF2_MF8_MASK\0" + /* 240700 */ "PseudoVFSUB_VF64_MF8_MASK\0" + /* 240726 */ "PseudoVFMSUB_VF64_MF8_MASK\0" + /* 240753 */ "PseudoVFNMSUB_VF64_MF8_MASK\0" + /* 240781 */ "PseudoVFRSUB_VF64_MF8_MASK\0" + /* 240808 */ "PseudoVFMSAC_VF64_MF8_MASK\0" + /* 240835 */ "PseudoVFNMSAC_VF64_MF8_MASK\0" + /* 240863 */ "PseudoVFMACC_VF64_MF8_MASK\0" + /* 240890 */ "PseudoVFNMACC_VF64_MF8_MASK\0" + /* 240918 */ "PseudoVFADD_VF64_MF8_MASK\0" + /* 240944 */ "PseudoVFMADD_VF64_MF8_MASK\0" + /* 240971 */ "PseudoVFNMADD_VF64_MF8_MASK\0" + /* 240999 */ "PseudoVMFGE_VF64_MF8_MASK\0" + /* 241025 */ "PseudoVMFLE_VF64_MF8_MASK\0" + /* 241051 */ "PseudoVMFNE_VF64_MF8_MASK\0" + /* 241077 */ "PseudoVFSGNJ_VF64_MF8_MASK\0" + /* 241104 */ "PseudoVFMUL_VF64_MF8_MASK\0" + /* 241130 */ "PseudoVFMIN_VF64_MF8_MASK\0" + /* 241156 */ "PseudoVFSGNJN_VF64_MF8_MASK\0" + /* 241184 */ "PseudoVFSLIDE1DOWN_VF64_MF8_MASK\0" + /* 241217 */ "PseudoVFSLIDE1UP_VF64_MF8_MASK\0" + /* 241248 */ "PseudoVMFEQ_VF64_MF8_MASK\0" + /* 241274 */ "PseudoVMFGT_VF64_MF8_MASK\0" + /* 241300 */ "PseudoVMFLT_VF64_MF8_MASK\0" + /* 241326 */ "PseudoVFDIV_VF64_MF8_MASK\0" + /* 241352 */ "PseudoVFRDIV_VF64_MF8_MASK\0" + /* 241379 */ "PseudoVFMAX_VF64_MF8_MASK\0" + /* 241405 */ "PseudoVFSGNJX_VF64_MF8_MASK\0" + /* 241433 */ "PseudoVRGATHEREI16_VV_MF4_MF8_MASK\0" + /* 241468 */ "PseudoVLOXSEG2EI16_V_MF4_MF8_MASK\0" + /* 241502 */ "PseudoVSOXSEG2EI16_V_MF4_MF8_MASK\0" + /* 241536 */ "PseudoVLUXSEG2EI16_V_MF4_MF8_MASK\0" + /* 241570 */ "PseudoVSUXSEG2EI16_V_MF4_MF8_MASK\0" + /* 241604 */ "PseudoVLOXSEG3EI16_V_MF4_MF8_MASK\0" + /* 241638 */ "PseudoVSOXSEG3EI16_V_MF4_MF8_MASK\0" + /* 241672 */ "PseudoVLUXSEG3EI16_V_MF4_MF8_MASK\0" + /* 241706 */ "PseudoVSUXSEG3EI16_V_MF4_MF8_MASK\0" + /* 241740 */ "PseudoVLOXSEG4EI16_V_MF4_MF8_MASK\0" + /* 241774 */ "PseudoVSOXSEG4EI16_V_MF4_MF8_MASK\0" + /* 241808 */ "PseudoVLUXSEG4EI16_V_MF4_MF8_MASK\0" + /* 241842 */ "PseudoVSUXSEG4EI16_V_MF4_MF8_MASK\0" + /* 241876 */ "PseudoVLOXSEG5EI16_V_MF4_MF8_MASK\0" + /* 241910 */ "PseudoVSOXSEG5EI16_V_MF4_MF8_MASK\0" + /* 241944 */ "PseudoVLUXSEG5EI16_V_MF4_MF8_MASK\0" + /* 241978 */ "PseudoVSUXSEG5EI16_V_MF4_MF8_MASK\0" + /* 242012 */ "PseudoVLOXSEG6EI16_V_MF4_MF8_MASK\0" + /* 242046 */ "PseudoVSOXSEG6EI16_V_MF4_MF8_MASK\0" + /* 242080 */ "PseudoVLUXSEG6EI16_V_MF4_MF8_MASK\0" + /* 242114 */ "PseudoVSUXSEG6EI16_V_MF4_MF8_MASK\0" + /* 242148 */ "PseudoVLOXSEG7EI16_V_MF4_MF8_MASK\0" + /* 242182 */ "PseudoVSOXSEG7EI16_V_MF4_MF8_MASK\0" + /* 242216 */ "PseudoVLUXSEG7EI16_V_MF4_MF8_MASK\0" + /* 242250 */ "PseudoVSUXSEG7EI16_V_MF4_MF8_MASK\0" + /* 242284 */ "PseudoVLOXSEG8EI16_V_MF4_MF8_MASK\0" + /* 242318 */ "PseudoVSOXSEG8EI16_V_MF4_MF8_MASK\0" + /* 242352 */ "PseudoVLUXSEG8EI16_V_MF4_MF8_MASK\0" + /* 242386 */ "PseudoVSUXSEG8EI16_V_MF4_MF8_MASK\0" + /* 242420 */ "PseudoVLOXEI16_V_MF4_MF8_MASK\0" + /* 242450 */ "PseudoVSOXEI16_V_MF4_MF8_MASK\0" + /* 242480 */ "PseudoVLUXEI16_V_MF4_MF8_MASK\0" + /* 242510 */ "PseudoVSUXEI16_V_MF4_MF8_MASK\0" + /* 242540 */ "PseudoVFSUB_VF16_MF8_MASK\0" + /* 242566 */ "PseudoVFMSUB_VF16_MF8_MASK\0" + /* 242593 */ "PseudoVFNMSUB_VF16_MF8_MASK\0" + /* 242621 */ "PseudoVFRSUB_VF16_MF8_MASK\0" + /* 242648 */ "PseudoVFWSUB_VF16_MF8_MASK\0" + /* 242675 */ "PseudoVFMSAC_VF16_MF8_MASK\0" + /* 242702 */ "PseudoVFNMSAC_VF16_MF8_MASK\0" + /* 242730 */ "PseudoVFWNMSAC_VF16_MF8_MASK\0" + /* 242759 */ "PseudoVFWMSAC_VF16_MF8_MASK\0" + /* 242787 */ "PseudoVFMACC_VF16_MF8_MASK\0" + /* 242814 */ "PseudoVFNMACC_VF16_MF8_MASK\0" + /* 242842 */ "PseudoVFWNMACC_VF16_MF8_MASK\0" + /* 242871 */ "PseudoVFWMACC_VF16_MF8_MASK\0" + /* 242899 */ "PseudoVFADD_VF16_MF8_MASK\0" + /* 242925 */ "PseudoVFMADD_VF16_MF8_MASK\0" + /* 242952 */ "PseudoVFNMADD_VF16_MF8_MASK\0" + /* 242980 */ "PseudoVFWADD_VF16_MF8_MASK\0" + /* 243007 */ "PseudoVMFGE_VF16_MF8_MASK\0" + /* 243033 */ "PseudoVMFLE_VF16_MF8_MASK\0" + /* 243059 */ "PseudoVMFNE_VF16_MF8_MASK\0" + /* 243085 */ "PseudoVFSGNJ_VF16_MF8_MASK\0" + /* 243112 */ "PseudoVFMUL_VF16_MF8_MASK\0" + /* 243138 */ "PseudoVFWMUL_VF16_MF8_MASK\0" + /* 243165 */ "PseudoVFMIN_VF16_MF8_MASK\0" + /* 243191 */ "PseudoVFSGNJN_VF16_MF8_MASK\0" + /* 243219 */ "PseudoVFSLIDE1DOWN_VF16_MF8_MASK\0" + /* 243252 */ "PseudoVFSLIDE1UP_VF16_MF8_MASK\0" + /* 243283 */ "PseudoVMFEQ_VF16_MF8_MASK\0" + /* 243309 */ "PseudoVMFGT_VF16_MF8_MASK\0" + /* 243335 */ "PseudoVMFLT_VF16_MF8_MASK\0" + /* 243361 */ "PseudoVFDIV_VF16_MF8_MASK\0" + /* 243387 */ "PseudoVFRDIV_VF16_MF8_MASK\0" + /* 243414 */ "PseudoVFMAX_VF16_MF8_MASK\0" + /* 243440 */ "PseudoVFSGNJX_VF16_MF8_MASK\0" + /* 243468 */ "PseudoVFWSUB_WF16_MF8_MASK\0" + /* 243495 */ "PseudoVFWADD_WF16_MF8_MASK\0" + /* 243522 */ "PseudoVRGATHEREI16_VV_MF8_MF8_MASK\0" + /* 243557 */ "PseudoVLOXSEG2EI8_V_MF8_MF8_MASK\0" + /* 243590 */ "PseudoVSOXSEG2EI8_V_MF8_MF8_MASK\0" + /* 243623 */ "PseudoVLUXSEG2EI8_V_MF8_MF8_MASK\0" + /* 243656 */ "PseudoVSUXSEG2EI8_V_MF8_MF8_MASK\0" + /* 243689 */ "PseudoVLOXSEG3EI8_V_MF8_MF8_MASK\0" + /* 243722 */ "PseudoVSOXSEG3EI8_V_MF8_MF8_MASK\0" + /* 243755 */ "PseudoVLUXSEG3EI8_V_MF8_MF8_MASK\0" + /* 243788 */ "PseudoVSUXSEG3EI8_V_MF8_MF8_MASK\0" + /* 243821 */ "PseudoVLOXSEG4EI8_V_MF8_MF8_MASK\0" + /* 243854 */ "PseudoVSOXSEG4EI8_V_MF8_MF8_MASK\0" + /* 243887 */ "PseudoVLUXSEG4EI8_V_MF8_MF8_MASK\0" + /* 243920 */ "PseudoVSUXSEG4EI8_V_MF8_MF8_MASK\0" + /* 243953 */ "PseudoVLOXSEG5EI8_V_MF8_MF8_MASK\0" + /* 243986 */ "PseudoVSOXSEG5EI8_V_MF8_MF8_MASK\0" + /* 244019 */ "PseudoVLUXSEG5EI8_V_MF8_MF8_MASK\0" + /* 244052 */ "PseudoVSUXSEG5EI8_V_MF8_MF8_MASK\0" + /* 244085 */ "PseudoVLOXSEG6EI8_V_MF8_MF8_MASK\0" + /* 244118 */ "PseudoVSOXSEG6EI8_V_MF8_MF8_MASK\0" + /* 244151 */ "PseudoVLUXSEG6EI8_V_MF8_MF8_MASK\0" + /* 244184 */ "PseudoVSUXSEG6EI8_V_MF8_MF8_MASK\0" + /* 244217 */ "PseudoVLOXSEG7EI8_V_MF8_MF8_MASK\0" + /* 244250 */ "PseudoVSOXSEG7EI8_V_MF8_MF8_MASK\0" + /* 244283 */ "PseudoVLUXSEG7EI8_V_MF8_MF8_MASK\0" + /* 244316 */ "PseudoVSUXSEG7EI8_V_MF8_MF8_MASK\0" + /* 244349 */ "PseudoVLOXSEG8EI8_V_MF8_MF8_MASK\0" + /* 244382 */ "PseudoVSOXSEG8EI8_V_MF8_MF8_MASK\0" + /* 244415 */ "PseudoVLUXSEG8EI8_V_MF8_MF8_MASK\0" + /* 244448 */ "PseudoVSUXSEG8EI8_V_MF8_MF8_MASK\0" + /* 244481 */ "PseudoVLOXEI8_V_MF8_MF8_MASK\0" + /* 244510 */ "PseudoVSOXEI8_V_MF8_MF8_MASK\0" + /* 244539 */ "PseudoVLUXEI8_V_MF8_MF8_MASK\0" + /* 244568 */ "PseudoVSUXEI8_V_MF8_MF8_MASK\0" + /* 244597 */ "PseudoVSSRA_VI_MF8_MASK\0" + /* 244621 */ "PseudoVSRA_VI_MF8_MASK\0" + /* 244644 */ "PseudoVRSUB_VI_MF8_MASK\0" + /* 244668 */ "PseudoVSADD_VI_MF8_MASK\0" + /* 244692 */ "PseudoVADD_VI_MF8_MASK\0" + /* 244715 */ "PseudoVAND_VI_MF8_MASK\0" + /* 244738 */ "PseudoVMSLE_VI_MF8_MASK\0" + /* 244762 */ "PseudoVMSNE_VI_MF8_MASK\0" + /* 244786 */ "PseudoVSLL_VI_MF8_MASK\0" + /* 244809 */ "PseudoVSSRL_VI_MF8_MASK\0" + /* 244833 */ "PseudoVSRL_VI_MF8_MASK\0" + /* 244856 */ "PseudoVSLIDEDOWN_VI_MF8_MASK\0" + /* 244885 */ "PseudoVSLIDEUP_VI_MF8_MASK\0" + /* 244912 */ "PseudoVMSEQ_VI_MF8_MASK\0" + /* 244936 */ "PseudoVRGATHER_VI_MF8_MASK\0" + /* 244963 */ "PseudoVOR_VI_MF8_MASK\0" + /* 244985 */ "PseudoVXOR_VI_MF8_MASK\0" + /* 245008 */ "PseudoVMSGT_VI_MF8_MASK\0" + /* 245032 */ "PseudoVSADDU_VI_MF8_MASK\0" + /* 245057 */ "PseudoVMSLEU_VI_MF8_MASK\0" + /* 245082 */ "PseudoVMSGTU_VI_MF8_MASK\0" + /* 245107 */ "PseudoVNSRA_WI_MF8_MASK\0" + /* 245131 */ "PseudoVNSRL_WI_MF8_MASK\0" + /* 245155 */ "PseudoVNCLIP_WI_MF8_MASK\0" + /* 245180 */ "PseudoVNCLIPU_WI_MF8_MASK\0" + /* 245206 */ "PseudoVIOTA_M_MF8_MASK\0" + /* 245229 */ "PseudoVREDAND_VS_MF8_MASK\0" + /* 245255 */ "PseudoVREDSUM_VS_MF8_MASK\0" + /* 245281 */ "PseudoVWREDSUM_VS_MF8_MASK\0" + /* 245308 */ "PseudoVFREDOSUM_VS_MF8_MASK\0" + /* 245336 */ "PseudoVFWREDOSUM_VS_MF8_MASK\0" + /* 245365 */ "PseudoVFREDUSUM_VS_MF8_MASK\0" + /* 245393 */ "PseudoVFWREDUSUM_VS_MF8_MASK\0" + /* 245422 */ "PseudoVFREDMIN_VS_MF8_MASK\0" + /* 245449 */ "PseudoVREDMIN_VS_MF8_MASK\0" + /* 245475 */ "PseudoVREDOR_VS_MF8_MASK\0" + /* 245500 */ "PseudoVREDXOR_VS_MF8_MASK\0" + /* 245526 */ "PseudoVWREDSUMU_VS_MF8_MASK\0" + /* 245554 */ "PseudoVREDMINU_VS_MF8_MASK\0" + /* 245581 */ "PseudoVREDMAXU_VS_MF8_MASK\0" + /* 245608 */ "PseudoVFREDMAX_VS_MF8_MASK\0" + /* 245635 */ "PseudoVREDMAX_VS_MF8_MASK\0" + /* 245661 */ "PseudoVSSRA_VV_MF8_MASK\0" + /* 245685 */ "PseudoVSRA_VV_MF8_MASK\0" + /* 245708 */ "PseudoVASUB_VV_MF8_MASK\0" + /* 245732 */ "PseudoVFSUB_VV_MF8_MASK\0" + /* 245756 */ "PseudoVFMSUB_VV_MF8_MASK\0" + /* 245781 */ "PseudoVFNMSUB_VV_MF8_MASK\0" + /* 245807 */ "PseudoVNMSUB_VV_MF8_MASK\0" + /* 245832 */ "PseudoVSSUB_VV_MF8_MASK\0" + /* 245856 */ "PseudoVSUB_VV_MF8_MASK\0" + /* 245879 */ "PseudoVFWSUB_VV_MF8_MASK\0" + /* 245904 */ "PseudoVWSUB_VV_MF8_MASK\0" + /* 245928 */ "PseudoVFMSAC_VV_MF8_MASK\0" + /* 245953 */ "PseudoVFNMSAC_VV_MF8_MASK\0" + /* 245979 */ "PseudoVNMSAC_VV_MF8_MASK\0" + /* 246004 */ "PseudoVFWNMSAC_VV_MF8_MASK\0" + /* 246031 */ "PseudoVFWMSAC_VV_MF8_MASK\0" + /* 246057 */ "PseudoVFMACC_VV_MF8_MASK\0" + /* 246082 */ "PseudoVFNMACC_VV_MF8_MASK\0" + /* 246108 */ "PseudoVFWNMACC_VV_MF8_MASK\0" + /* 246135 */ "PseudoVMACC_VV_MF8_MASK\0" + /* 246159 */ "PseudoVFWMACC_VV_MF8_MASK\0" + /* 246185 */ "PseudoVWMACC_VV_MF8_MASK\0" + /* 246210 */ "PseudoVAADD_VV_MF8_MASK\0" + /* 246234 */ "PseudoVFADD_VV_MF8_MASK\0" + /* 246258 */ "PseudoVFMADD_VV_MF8_MASK\0" + /* 246283 */ "PseudoVFNMADD_VV_MF8_MASK\0" + /* 246309 */ "PseudoVMADD_VV_MF8_MASK\0" + /* 246333 */ "PseudoVSADD_VV_MF8_MASK\0" + /* 246357 */ "PseudoVADD_VV_MF8_MASK\0" + /* 246380 */ "PseudoVFWADD_VV_MF8_MASK\0" + /* 246405 */ "PseudoVWADD_VV_MF8_MASK\0" + /* 246429 */ "PseudoVAND_VV_MF8_MASK\0" + /* 246452 */ "PseudoVMFLE_VV_MF8_MASK\0" + /* 246476 */ "PseudoVMSLE_VV_MF8_MASK\0" + /* 246500 */ "PseudoVMFNE_VV_MF8_MASK\0" + /* 246524 */ "PseudoVMSNE_VV_MF8_MASK\0" + /* 246548 */ "PseudoVMULH_VV_MF8_MASK\0" + /* 246572 */ "PseudoVFSGNJ_VV_MF8_MASK\0" + /* 246597 */ "PseudoVSLL_VV_MF8_MASK\0" + /* 246620 */ "PseudoVSSRL_VV_MF8_MASK\0" + /* 246644 */ "PseudoVSRL_VV_MF8_MASK\0" + /* 246667 */ "PseudoVFMUL_VV_MF8_MASK\0" + /* 246691 */ "PseudoVSMUL_VV_MF8_MASK\0" + /* 246715 */ "PseudoVMUL_VV_MF8_MASK\0" + /* 246738 */ "PseudoVFWMUL_VV_MF8_MASK\0" + /* 246763 */ "PseudoVWMUL_VV_MF8_MASK\0" + /* 246787 */ "PseudoVREM_VV_MF8_MASK\0" + /* 246810 */ "PseudoVFMIN_VV_MF8_MASK\0" + /* 246834 */ "PseudoVMIN_VV_MF8_MASK\0" + /* 246857 */ "PseudoVFSGNJN_VV_MF8_MASK\0" + /* 246883 */ "PseudoVMFEQ_VV_MF8_MASK\0" + /* 246907 */ "PseudoVMSEQ_VV_MF8_MASK\0" + /* 246931 */ "PseudoVRGATHER_VV_MF8_MASK\0" + /* 246958 */ "PseudoVOR_VV_MF8_MASK\0" + /* 246980 */ "PseudoVXOR_VV_MF8_MASK\0" + /* 247003 */ "PseudoVMFLT_VV_MF8_MASK\0" + /* 247027 */ "PseudoVMSLT_VV_MF8_MASK\0" + /* 247051 */ "PseudoVASUBU_VV_MF8_MASK\0" + /* 247076 */ "PseudoVSSUBU_VV_MF8_MASK\0" + /* 247101 */ "PseudoVWSUBU_VV_MF8_MASK\0" + /* 247126 */ "PseudoVWMACCU_VV_MF8_MASK\0" + /* 247152 */ "PseudoVAADDU_VV_MF8_MASK\0" + /* 247177 */ "PseudoVSADDU_VV_MF8_MASK\0" + /* 247202 */ "PseudoVWADDU_VV_MF8_MASK\0" + /* 247227 */ "PseudoVMSLEU_VV_MF8_MASK\0" + /* 247252 */ "PseudoVMULHU_VV_MF8_MASK\0" + /* 247277 */ "PseudoVWMULU_VV_MF8_MASK\0" + /* 247302 */ "PseudoVREMU_VV_MF8_MASK\0" + /* 247326 */ "PseudoVMINU_VV_MF8_MASK\0" + /* 247350 */ "PseudoVWMACCSU_VV_MF8_MASK\0" + /* 247377 */ "PseudoVMULHSU_VV_MF8_MASK\0" + /* 247403 */ "PseudoVWMULSU_VV_MF8_MASK\0" + /* 247429 */ "PseudoVMSLTU_VV_MF8_MASK\0" + /* 247454 */ "PseudoVDIVU_VV_MF8_MASK\0" + /* 247478 */ "PseudoVMAXU_VV_MF8_MASK\0" + /* 247502 */ "PseudoVFDIV_VV_MF8_MASK\0" + /* 247526 */ "PseudoVDIV_VV_MF8_MASK\0" + /* 247549 */ "PseudoVFMAX_VV_MF8_MASK\0" + /* 247573 */ "PseudoVMAX_VV_MF8_MASK\0" + /* 247596 */ "PseudoVFSGNJX_VV_MF8_MASK\0" + /* 247622 */ "PseudoVNSRA_WV_MF8_MASK\0" + /* 247646 */ "PseudoVFWSUB_WV_MF8_MASK\0" + /* 247671 */ "PseudoVWSUB_WV_MF8_MASK\0" + /* 247695 */ "PseudoVFWADD_WV_MF8_MASK\0" + /* 247720 */ "PseudoVWADD_WV_MF8_MASK\0" + /* 247744 */ "PseudoVNSRL_WV_MF8_MASK\0" + /* 247768 */ "PseudoVNCLIP_WV_MF8_MASK\0" + /* 247793 */ "PseudoVWSUBU_WV_MF8_MASK\0" + /* 247818 */ "PseudoVWADDU_WV_MF8_MASK\0" + /* 247843 */ "PseudoVNCLIPU_WV_MF8_MASK\0" + /* 247869 */ "PseudoVFREC7_V_MF8_MASK\0" + /* 247893 */ "PseudoVFRSQRT7_V_MF8_MASK\0" + /* 247919 */ "PseudoVLSEG2E8_V_MF8_MASK\0" + /* 247945 */ "PseudoVLSSEG2E8_V_MF8_MASK\0" + /* 247972 */ "PseudoVSSSEG2E8_V_MF8_MASK\0" + /* 247999 */ "PseudoVSSEG2E8_V_MF8_MASK\0" + /* 248025 */ "PseudoVLSEG3E8_V_MF8_MASK\0" + /* 248051 */ "PseudoVLSSEG3E8_V_MF8_MASK\0" + /* 248078 */ "PseudoVSSSEG3E8_V_MF8_MASK\0" + /* 248105 */ "PseudoVSSEG3E8_V_MF8_MASK\0" + /* 248131 */ "PseudoVLSEG4E8_V_MF8_MASK\0" + /* 248157 */ "PseudoVLSSEG4E8_V_MF8_MASK\0" + /* 248184 */ "PseudoVSSSEG4E8_V_MF8_MASK\0" + /* 248211 */ "PseudoVSSEG4E8_V_MF8_MASK\0" + /* 248237 */ "PseudoVLSEG5E8_V_MF8_MASK\0" + /* 248263 */ "PseudoVLSSEG5E8_V_MF8_MASK\0" + /* 248290 */ "PseudoVSSSEG5E8_V_MF8_MASK\0" + /* 248317 */ "PseudoVSSEG5E8_V_MF8_MASK\0" + /* 248343 */ "PseudoVLSEG6E8_V_MF8_MASK\0" + /* 248369 */ "PseudoVLSSEG6E8_V_MF8_MASK\0" + /* 248396 */ "PseudoVSSSEG6E8_V_MF8_MASK\0" + /* 248423 */ "PseudoVSSEG6E8_V_MF8_MASK\0" + /* 248449 */ "PseudoVLSEG7E8_V_MF8_MASK\0" + /* 248475 */ "PseudoVLSSEG7E8_V_MF8_MASK\0" + /* 248502 */ "PseudoVSSSEG7E8_V_MF8_MASK\0" + /* 248529 */ "PseudoVSSEG7E8_V_MF8_MASK\0" + /* 248555 */ "PseudoVLSEG8E8_V_MF8_MASK\0" + /* 248581 */ "PseudoVLSSEG8E8_V_MF8_MASK\0" + /* 248608 */ "PseudoVSSSEG8E8_V_MF8_MASK\0" + /* 248635 */ "PseudoVSSEG8E8_V_MF8_MASK\0" + /* 248661 */ "PseudoVLE8_V_MF8_MASK\0" + /* 248683 */ "PseudoVLSE8_V_MF8_MASK\0" + /* 248706 */ "PseudoVSSE8_V_MF8_MASK\0" + /* 248729 */ "PseudoVSE8_V_MF8_MASK\0" + /* 248751 */ "PseudoVID_V_MF8_MASK\0" + /* 248772 */ "PseudoVLSEG2E8FF_V_MF8_MASK\0" + /* 248800 */ "PseudoVLSEG3E8FF_V_MF8_MASK\0" + /* 248828 */ "PseudoVLSEG4E8FF_V_MF8_MASK\0" + /* 248856 */ "PseudoVLSEG5E8FF_V_MF8_MASK\0" + /* 248884 */ "PseudoVLSEG6E8FF_V_MF8_MASK\0" + /* 248912 */ "PseudoVLSEG7E8FF_V_MF8_MASK\0" + /* 248940 */ "PseudoVLSEG8E8FF_V_MF8_MASK\0" + /* 248968 */ "PseudoVLE8FF_V_MF8_MASK\0" + /* 248992 */ "PseudoVFWCVT_F_F_V_MF8_MASK\0" + /* 249020 */ "PseudoVFCVT_XU_F_V_MF8_MASK\0" + /* 249048 */ "PseudoVFWCVT_XU_F_V_MF8_MASK\0" + /* 249077 */ "PseudoVFCVT_RTZ_XU_F_V_MF8_MASK\0" + /* 249109 */ "PseudoVFWCVT_RTZ_XU_F_V_MF8_MASK\0" + /* 249142 */ "PseudoVFCVT_X_F_V_MF8_MASK\0" + /* 249169 */ "PseudoVFWCVT_X_F_V_MF8_MASK\0" + /* 249197 */ "PseudoVFCVT_RTZ_X_F_V_MF8_MASK\0" + /* 249228 */ "PseudoVFWCVT_RTZ_X_F_V_MF8_MASK\0" + /* 249260 */ "PseudoVFCLASS_V_MF8_MASK\0" + /* 249285 */ "PseudoVFSQRT_V_MF8_MASK\0" + /* 249309 */ "PseudoVFCVT_F_XU_V_MF8_MASK\0" + /* 249337 */ "PseudoVFWCVT_F_XU_V_MF8_MASK\0" + /* 249366 */ "PseudoVFCVT_F_X_V_MF8_MASK\0" + /* 249393 */ "PseudoVFWCVT_F_X_V_MF8_MASK\0" + /* 249421 */ "PseudoVFNCVT_ROD_F_F_W_MF8_MASK\0" + /* 249453 */ "PseudoVFNCVT_F_F_W_MF8_MASK\0" + /* 249481 */ "PseudoVFNCVT_XU_F_W_MF8_MASK\0" + /* 249510 */ "PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK\0" + /* 249543 */ "PseudoVFNCVT_X_F_W_MF8_MASK\0" + /* 249571 */ "PseudoVFNCVT_RTZ_X_F_W_MF8_MASK\0" + /* 249603 */ "PseudoVFNCVT_F_XU_W_MF8_MASK\0" + /* 249632 */ "PseudoVFNCVT_F_X_W_MF8_MASK\0" + /* 249660 */ "PseudoVSSRA_VX_MF8_MASK\0" + /* 249684 */ "PseudoVSRA_VX_MF8_MASK\0" + /* 249707 */ "PseudoVASUB_VX_MF8_MASK\0" + /* 249731 */ "PseudoVNMSUB_VX_MF8_MASK\0" + /* 249756 */ "PseudoVRSUB_VX_MF8_MASK\0" + /* 249780 */ "PseudoVSSUB_VX_MF8_MASK\0" + /* 249804 */ "PseudoVSUB_VX_MF8_MASK\0" + /* 249827 */ "PseudoVWSUB_VX_MF8_MASK\0" + /* 249851 */ "PseudoVNMSAC_VX_MF8_MASK\0" + /* 249876 */ "PseudoVMACC_VX_MF8_MASK\0" + /* 249900 */ "PseudoVWMACC_VX_MF8_MASK\0" + /* 249925 */ "PseudoVAADD_VX_MF8_MASK\0" + /* 249949 */ "PseudoVMADD_VX_MF8_MASK\0" + /* 249973 */ "PseudoVSADD_VX_MF8_MASK\0" + /* 249997 */ "PseudoVADD_VX_MF8_MASK\0" + /* 250020 */ "PseudoVWADD_VX_MF8_MASK\0" + /* 250044 */ "PseudoVAND_VX_MF8_MASK\0" + /* 250067 */ "PseudoVMSLE_VX_MF8_MASK\0" + /* 250091 */ "PseudoVMSNE_VX_MF8_MASK\0" + /* 250115 */ "PseudoVMULH_VX_MF8_MASK\0" + /* 250139 */ "PseudoVSLL_VX_MF8_MASK\0" + /* 250162 */ "PseudoVSSRL_VX_MF8_MASK\0" + /* 250186 */ "PseudoVSRL_VX_MF8_MASK\0" + /* 250209 */ "PseudoVSMUL_VX_MF8_MASK\0" + /* 250233 */ "PseudoVMUL_VX_MF8_MASK\0" + /* 250256 */ "PseudoVWMUL_VX_MF8_MASK\0" + /* 250280 */ "PseudoVREM_VX_MF8_MASK\0" + /* 250303 */ "PseudoVMIN_VX_MF8_MASK\0" + /* 250326 */ "PseudoVSLIDE1DOWN_VX_MF8_MASK\0" + /* 250356 */ "PseudoVSLIDEDOWN_VX_MF8_MASK\0" + /* 250385 */ "PseudoVSLIDE1UP_VX_MF8_MASK\0" + /* 250413 */ "PseudoVSLIDEUP_VX_MF8_MASK\0" + /* 250440 */ "PseudoVMSEQ_VX_MF8_MASK\0" + /* 250464 */ "PseudoVRGATHER_VX_MF8_MASK\0" + /* 250491 */ "PseudoVOR_VX_MF8_MASK\0" + /* 250513 */ "PseudoVXOR_VX_MF8_MASK\0" + /* 250536 */ "PseudoVWMACCUS_VX_MF8_MASK\0" + /* 250563 */ "PseudoVMSGT_VX_MF8_MASK\0" + /* 250587 */ "PseudoVMSLT_VX_MF8_MASK\0" + /* 250611 */ "PseudoVASUBU_VX_MF8_MASK\0" + /* 250636 */ "PseudoVSSUBU_VX_MF8_MASK\0" + /* 250661 */ "PseudoVWSUBU_VX_MF8_MASK\0" + /* 250686 */ "PseudoVWMACCU_VX_MF8_MASK\0" + /* 250712 */ "PseudoVAADDU_VX_MF8_MASK\0" + /* 250737 */ "PseudoVSADDU_VX_MF8_MASK\0" + /* 250762 */ "PseudoVWADDU_VX_MF8_MASK\0" + /* 250787 */ "PseudoVMSLEU_VX_MF8_MASK\0" + /* 250812 */ "PseudoVMULHU_VX_MF8_MASK\0" + /* 250837 */ "PseudoVWMULU_VX_MF8_MASK\0" + /* 250862 */ "PseudoVREMU_VX_MF8_MASK\0" + /* 250886 */ "PseudoVMINU_VX_MF8_MASK\0" + /* 250910 */ "PseudoVWMACCSU_VX_MF8_MASK\0" + /* 250937 */ "PseudoVMULHSU_VX_MF8_MASK\0" + /* 250963 */ "PseudoVWMULSU_VX_MF8_MASK\0" + /* 250989 */ "PseudoVMSGTU_VX_MF8_MASK\0" + /* 251014 */ "PseudoVMSLTU_VX_MF8_MASK\0" + /* 251039 */ "PseudoVDIVU_VX_MF8_MASK\0" + /* 251063 */ "PseudoVMAXU_VX_MF8_MASK\0" + /* 251087 */ "PseudoVDIV_VX_MF8_MASK\0" + /* 251110 */ "PseudoVMAX_VX_MF8_MASK\0" + /* 251133 */ "PseudoVNSRA_WX_MF8_MASK\0" + /* 251157 */ "PseudoVWSUB_WX_MF8_MASK\0" + /* 251181 */ "PseudoVWADD_WX_MF8_MASK\0" + /* 251205 */ "PseudoVNSRL_WX_MF8_MASK\0" + /* 251229 */ "PseudoVNCLIP_WX_MF8_MASK\0" + /* 251254 */ "PseudoVWSUBU_WX_MF8_MASK\0" + /* 251279 */ "PseudoVWADDU_WX_MF8_MASK\0" + /* 251304 */ "PseudoVNCLIPU_WX_MF8_MASK\0" + /* 251330 */ "PseudoVLOXEI8_V_M1_M8_MASK\0" + /* 251357 */ "PseudoVSOXEI8_V_M1_M8_MASK\0" + /* 251384 */ "PseudoVLUXEI8_V_M1_M8_MASK\0" + /* 251411 */ "PseudoVSUXEI8_V_M1_M8_MASK\0" + /* 251438 */ "PseudoVFSUB_VF32_M8_MASK\0" + /* 251463 */ "PseudoVFMSUB_VF32_M8_MASK\0" + /* 251489 */ "PseudoVFNMSUB_VF32_M8_MASK\0" + /* 251516 */ "PseudoVFRSUB_VF32_M8_MASK\0" + /* 251542 */ "PseudoVFMSAC_VF32_M8_MASK\0" + /* 251568 */ "PseudoVFNMSAC_VF32_M8_MASK\0" + /* 251595 */ "PseudoVFMACC_VF32_M8_MASK\0" + /* 251621 */ "PseudoVFNMACC_VF32_M8_MASK\0" + /* 251648 */ "PseudoVFADD_VF32_M8_MASK\0" + /* 251673 */ "PseudoVFMADD_VF32_M8_MASK\0" + /* 251699 */ "PseudoVFNMADD_VF32_M8_MASK\0" + /* 251726 */ "PseudoVMFGE_VF32_M8_MASK\0" + /* 251751 */ "PseudoVMFLE_VF32_M8_MASK\0" + /* 251776 */ "PseudoVMFNE_VF32_M8_MASK\0" + /* 251801 */ "PseudoVFSGNJ_VF32_M8_MASK\0" + /* 251827 */ "PseudoVFMUL_VF32_M8_MASK\0" + /* 251852 */ "PseudoVFMIN_VF32_M8_MASK\0" + /* 251877 */ "PseudoVFSGNJN_VF32_M8_MASK\0" + /* 251904 */ "PseudoVFSLIDE1DOWN_VF32_M8_MASK\0" + /* 251936 */ "PseudoVFSLIDE1UP_VF32_M8_MASK\0" + /* 251966 */ "PseudoVMFEQ_VF32_M8_MASK\0" + /* 251991 */ "PseudoVMFGT_VF32_M8_MASK\0" + /* 252016 */ "PseudoVMFLT_VF32_M8_MASK\0" + /* 252041 */ "PseudoVFDIV_VF32_M8_MASK\0" + /* 252066 */ "PseudoVFRDIV_VF32_M8_MASK\0" + /* 252092 */ "PseudoVFMAX_VF32_M8_MASK\0" + /* 252117 */ "PseudoVFSGNJX_VF32_M8_MASK\0" + /* 252144 */ "PseudoVSEXT_VF2_M8_MASK\0" + /* 252168 */ "PseudoVZEXT_VF2_M8_MASK\0" + /* 252192 */ "PseudoVLOXEI16_V_M2_M8_MASK\0" + /* 252220 */ "PseudoVSOXEI16_V_M2_M8_MASK\0" + /* 252248 */ "PseudoVLUXEI16_V_M2_M8_MASK\0" + /* 252276 */ "PseudoVSUXEI16_V_M2_M8_MASK\0" + /* 252304 */ "PseudoVLOXEI8_V_M2_M8_MASK\0" + /* 252331 */ "PseudoVSOXEI8_V_M2_M8_MASK\0" + /* 252358 */ "PseudoVLUXEI8_V_M2_M8_MASK\0" + /* 252385 */ "PseudoVSUXEI8_V_M2_M8_MASK\0" + /* 252412 */ "PseudoVFSUB_VF64_M8_MASK\0" + /* 252437 */ "PseudoVFMSUB_VF64_M8_MASK\0" + /* 252463 */ "PseudoVFNMSUB_VF64_M8_MASK\0" + /* 252490 */ "PseudoVFRSUB_VF64_M8_MASK\0" + /* 252516 */ "PseudoVFMSAC_VF64_M8_MASK\0" + /* 252542 */ "PseudoVFNMSAC_VF64_M8_MASK\0" + /* 252569 */ "PseudoVFMACC_VF64_M8_MASK\0" + /* 252595 */ "PseudoVFNMACC_VF64_M8_MASK\0" + /* 252622 */ "PseudoVFADD_VF64_M8_MASK\0" + /* 252647 */ "PseudoVFMADD_VF64_M8_MASK\0" + /* 252673 */ "PseudoVFNMADD_VF64_M8_MASK\0" + /* 252700 */ "PseudoVMFGE_VF64_M8_MASK\0" + /* 252725 */ "PseudoVMFLE_VF64_M8_MASK\0" + /* 252750 */ "PseudoVMFNE_VF64_M8_MASK\0" + /* 252775 */ "PseudoVFSGNJ_VF64_M8_MASK\0" + /* 252801 */ "PseudoVFMUL_VF64_M8_MASK\0" + /* 252826 */ "PseudoVFMIN_VF64_M8_MASK\0" + /* 252851 */ "PseudoVFSGNJN_VF64_M8_MASK\0" + /* 252878 */ "PseudoVFSLIDE1DOWN_VF64_M8_MASK\0" + /* 252910 */ "PseudoVFSLIDE1UP_VF64_M8_MASK\0" + /* 252940 */ "PseudoVMFEQ_VF64_M8_MASK\0" + /* 252965 */ "PseudoVMFGT_VF64_M8_MASK\0" + /* 252990 */ "PseudoVMFLT_VF64_M8_MASK\0" + /* 253015 */ "PseudoVFDIV_VF64_M8_MASK\0" + /* 253040 */ "PseudoVFRDIV_VF64_M8_MASK\0" + /* 253066 */ "PseudoVFMAX_VF64_M8_MASK\0" + /* 253091 */ "PseudoVFSGNJX_VF64_M8_MASK\0" + /* 253118 */ "PseudoVSEXT_VF4_M8_MASK\0" + /* 253142 */ "PseudoVZEXT_VF4_M8_MASK\0" + /* 253166 */ "PseudoVAMOADDEI64_WD_M4_M8_MASK\0" + /* 253198 */ "PseudoVAMOANDEI64_WD_M4_M8_MASK\0" + /* 253230 */ "PseudoVAMOMINEI64_WD_M4_M8_MASK\0" + /* 253262 */ "PseudoVAMOSWAPEI64_WD_M4_M8_MASK\0" + /* 253295 */ "PseudoVAMOOREI64_WD_M4_M8_MASK\0" + /* 253326 */ "PseudoVAMOXOREI64_WD_M4_M8_MASK\0" + /* 253358 */ "PseudoVAMOMINUEI64_WD_M4_M8_MASK\0" + /* 253391 */ "PseudoVAMOMAXUEI64_WD_M4_M8_MASK\0" + /* 253424 */ "PseudoVAMOMAXEI64_WD_M4_M8_MASK\0" + /* 253456 */ "PseudoVRGATHEREI16_VV_M4_M8_MASK\0" + /* 253489 */ "PseudoVLOXEI32_V_M4_M8_MASK\0" + /* 253517 */ "PseudoVSOXEI32_V_M4_M8_MASK\0" + /* 253545 */ "PseudoVLUXEI32_V_M4_M8_MASK\0" + /* 253573 */ "PseudoVSUXEI32_V_M4_M8_MASK\0" + /* 253601 */ "PseudoVLOXEI16_V_M4_M8_MASK\0" + /* 253629 */ "PseudoVSOXEI16_V_M4_M8_MASK\0" + /* 253657 */ "PseudoVLUXEI16_V_M4_M8_MASK\0" + /* 253685 */ "PseudoVSUXEI16_V_M4_M8_MASK\0" + /* 253713 */ "PseudoVLOXEI8_V_M4_M8_MASK\0" + /* 253740 */ "PseudoVSOXEI8_V_M4_M8_MASK\0" + /* 253767 */ "PseudoVLUXEI8_V_M4_M8_MASK\0" + /* 253794 */ "PseudoVSUXEI8_V_M4_M8_MASK\0" + /* 253821 */ "PseudoVFSUB_VF16_M8_MASK\0" + /* 253846 */ "PseudoVFMSUB_VF16_M8_MASK\0" + /* 253872 */ "PseudoVFNMSUB_VF16_M8_MASK\0" + /* 253899 */ "PseudoVFRSUB_VF16_M8_MASK\0" + /* 253925 */ "PseudoVFMSAC_VF16_M8_MASK\0" + /* 253951 */ "PseudoVFNMSAC_VF16_M8_MASK\0" + /* 253978 */ "PseudoVFMACC_VF16_M8_MASK\0" + /* 254004 */ "PseudoVFNMACC_VF16_M8_MASK\0" + /* 254031 */ "PseudoVFADD_VF16_M8_MASK\0" + /* 254056 */ "PseudoVFMADD_VF16_M8_MASK\0" + /* 254082 */ "PseudoVFNMADD_VF16_M8_MASK\0" + /* 254109 */ "PseudoVMFGE_VF16_M8_MASK\0" + /* 254134 */ "PseudoVMFLE_VF16_M8_MASK\0" + /* 254159 */ "PseudoVMFNE_VF16_M8_MASK\0" + /* 254184 */ "PseudoVFSGNJ_VF16_M8_MASK\0" + /* 254210 */ "PseudoVFMUL_VF16_M8_MASK\0" + /* 254235 */ "PseudoVFMIN_VF16_M8_MASK\0" + /* 254260 */ "PseudoVFSGNJN_VF16_M8_MASK\0" + /* 254287 */ "PseudoVFSLIDE1DOWN_VF16_M8_MASK\0" + /* 254319 */ "PseudoVFSLIDE1UP_VF16_M8_MASK\0" + /* 254349 */ "PseudoVMFEQ_VF16_M8_MASK\0" + /* 254374 */ "PseudoVMFGT_VF16_M8_MASK\0" + /* 254399 */ "PseudoVMFLT_VF16_M8_MASK\0" + /* 254424 */ "PseudoVFDIV_VF16_M8_MASK\0" + /* 254449 */ "PseudoVFRDIV_VF16_M8_MASK\0" + /* 254475 */ "PseudoVFMAX_VF16_M8_MASK\0" + /* 254500 */ "PseudoVFSGNJX_VF16_M8_MASK\0" + /* 254527 */ "PseudoVSEXT_VF8_M8_MASK\0" + /* 254551 */ "PseudoVZEXT_VF8_M8_MASK\0" + /* 254575 */ "PseudoVAMOADDEI32_WD_M8_M8_MASK\0" + /* 254607 */ "PseudoVAMOANDEI32_WD_M8_M8_MASK\0" + /* 254639 */ "PseudoVAMOMINEI32_WD_M8_M8_MASK\0" + /* 254671 */ "PseudoVAMOSWAPEI32_WD_M8_M8_MASK\0" + /* 254704 */ "PseudoVAMOOREI32_WD_M8_M8_MASK\0" + /* 254735 */ "PseudoVAMOXOREI32_WD_M8_M8_MASK\0" + /* 254767 */ "PseudoVAMOMINUEI32_WD_M8_M8_MASK\0" + /* 254800 */ "PseudoVAMOMAXUEI32_WD_M8_M8_MASK\0" + /* 254833 */ "PseudoVAMOMAXEI32_WD_M8_M8_MASK\0" + /* 254865 */ "PseudoVAMOADDEI64_WD_M8_M8_MASK\0" + /* 254897 */ "PseudoVAMOANDEI64_WD_M8_M8_MASK\0" + /* 254929 */ "PseudoVAMOMINEI64_WD_M8_M8_MASK\0" + /* 254961 */ "PseudoVAMOSWAPEI64_WD_M8_M8_MASK\0" + /* 254994 */ "PseudoVAMOOREI64_WD_M8_M8_MASK\0" + /* 255025 */ "PseudoVAMOXOREI64_WD_M8_M8_MASK\0" + /* 255057 */ "PseudoVAMOMINUEI64_WD_M8_M8_MASK\0" + /* 255090 */ "PseudoVAMOMAXUEI64_WD_M8_M8_MASK\0" + /* 255123 */ "PseudoVAMOMAXEI64_WD_M8_M8_MASK\0" + /* 255155 */ "PseudoVRGATHEREI16_VV_M8_M8_MASK\0" + /* 255188 */ "PseudoVLOXEI32_V_M8_M8_MASK\0" + /* 255216 */ "PseudoVSOXEI32_V_M8_M8_MASK\0" + /* 255244 */ "PseudoVLUXEI32_V_M8_M8_MASK\0" + /* 255272 */ "PseudoVSUXEI32_V_M8_M8_MASK\0" + /* 255300 */ "PseudoVLOXEI64_V_M8_M8_MASK\0" + /* 255328 */ "PseudoVSOXEI64_V_M8_M8_MASK\0" + /* 255356 */ "PseudoVLUXEI64_V_M8_M8_MASK\0" + /* 255384 */ "PseudoVSUXEI64_V_M8_M8_MASK\0" + /* 255412 */ "PseudoVLOXEI16_V_M8_M8_MASK\0" + /* 255440 */ "PseudoVSOXEI16_V_M8_M8_MASK\0" + /* 255468 */ "PseudoVLUXEI16_V_M8_M8_MASK\0" + /* 255496 */ "PseudoVSUXEI16_V_M8_M8_MASK\0" + /* 255524 */ "PseudoVLOXEI8_V_M8_M8_MASK\0" + /* 255551 */ "PseudoVSOXEI8_V_M8_M8_MASK\0" + /* 255578 */ "PseudoVLUXEI8_V_M8_M8_MASK\0" + /* 255605 */ "PseudoVSUXEI8_V_M8_M8_MASK\0" + /* 255632 */ "PseudoVSSRA_VI_M8_MASK\0" + /* 255655 */ "PseudoVSRA_VI_M8_MASK\0" + /* 255677 */ "PseudoVRSUB_VI_M8_MASK\0" + /* 255700 */ "PseudoVSADD_VI_M8_MASK\0" + /* 255723 */ "PseudoVADD_VI_M8_MASK\0" + /* 255745 */ "PseudoVAND_VI_M8_MASK\0" + /* 255767 */ "PseudoVMSLE_VI_M8_MASK\0" + /* 255790 */ "PseudoVMSNE_VI_M8_MASK\0" + /* 255813 */ "PseudoVSLL_VI_M8_MASK\0" + /* 255835 */ "PseudoVSSRL_VI_M8_MASK\0" + /* 255858 */ "PseudoVSRL_VI_M8_MASK\0" + /* 255880 */ "PseudoVSLIDEDOWN_VI_M8_MASK\0" + /* 255908 */ "PseudoVSLIDEUP_VI_M8_MASK\0" + /* 255934 */ "PseudoVMSEQ_VI_M8_MASK\0" + /* 255957 */ "PseudoVRGATHER_VI_M8_MASK\0" + /* 255983 */ "PseudoVOR_VI_M8_MASK\0" + /* 256004 */ "PseudoVXOR_VI_M8_MASK\0" + /* 256026 */ "PseudoVMSGT_VI_M8_MASK\0" + /* 256049 */ "PseudoVSADDU_VI_M8_MASK\0" + /* 256073 */ "PseudoVMSLEU_VI_M8_MASK\0" + /* 256097 */ "PseudoVMSGTU_VI_M8_MASK\0" + /* 256121 */ "PseudoVIOTA_M_M8_MASK\0" + /* 256143 */ "PseudoVREDAND_VS_M8_MASK\0" + /* 256168 */ "PseudoVREDSUM_VS_M8_MASK\0" + /* 256193 */ "PseudoVWREDSUM_VS_M8_MASK\0" + /* 256219 */ "PseudoVFREDOSUM_VS_M8_MASK\0" + /* 256246 */ "PseudoVFWREDOSUM_VS_M8_MASK\0" + /* 256274 */ "PseudoVFREDUSUM_VS_M8_MASK\0" + /* 256301 */ "PseudoVFWREDUSUM_VS_M8_MASK\0" + /* 256329 */ "PseudoVFREDMIN_VS_M8_MASK\0" + /* 256355 */ "PseudoVREDMIN_VS_M8_MASK\0" + /* 256380 */ "PseudoVREDOR_VS_M8_MASK\0" + /* 256404 */ "PseudoVREDXOR_VS_M8_MASK\0" + /* 256429 */ "PseudoVWREDSUMU_VS_M8_MASK\0" + /* 256456 */ "PseudoVREDMINU_VS_M8_MASK\0" + /* 256482 */ "PseudoVREDMAXU_VS_M8_MASK\0" + /* 256508 */ "PseudoVFREDMAX_VS_M8_MASK\0" + /* 256534 */ "PseudoVREDMAX_VS_M8_MASK\0" + /* 256559 */ "PseudoVSSRA_VV_M8_MASK\0" + /* 256582 */ "PseudoVSRA_VV_M8_MASK\0" + /* 256604 */ "PseudoVASUB_VV_M8_MASK\0" + /* 256627 */ "PseudoVFSUB_VV_M8_MASK\0" + /* 256650 */ "PseudoVFMSUB_VV_M8_MASK\0" + /* 256674 */ "PseudoVFNMSUB_VV_M8_MASK\0" + /* 256699 */ "PseudoVNMSUB_VV_M8_MASK\0" + /* 256723 */ "PseudoVSSUB_VV_M8_MASK\0" + /* 256746 */ "PseudoVSUB_VV_M8_MASK\0" + /* 256768 */ "PseudoVFMSAC_VV_M8_MASK\0" + /* 256792 */ "PseudoVFNMSAC_VV_M8_MASK\0" + /* 256817 */ "PseudoVNMSAC_VV_M8_MASK\0" + /* 256841 */ "PseudoVFMACC_VV_M8_MASK\0" + /* 256865 */ "PseudoVFNMACC_VV_M8_MASK\0" + /* 256890 */ "PseudoVMACC_VV_M8_MASK\0" + /* 256913 */ "PseudoVAADD_VV_M8_MASK\0" + /* 256936 */ "PseudoVFADD_VV_M8_MASK\0" + /* 256959 */ "PseudoVFMADD_VV_M8_MASK\0" + /* 256983 */ "PseudoVFNMADD_VV_M8_MASK\0" + /* 257008 */ "PseudoVMADD_VV_M8_MASK\0" + /* 257031 */ "PseudoVSADD_VV_M8_MASK\0" + /* 257054 */ "PseudoVADD_VV_M8_MASK\0" + /* 257076 */ "PseudoVAND_VV_M8_MASK\0" + /* 257098 */ "PseudoVMFLE_VV_M8_MASK\0" + /* 257121 */ "PseudoVMSLE_VV_M8_MASK\0" + /* 257144 */ "PseudoVMFNE_VV_M8_MASK\0" + /* 257167 */ "PseudoVMSNE_VV_M8_MASK\0" + /* 257190 */ "PseudoVMULH_VV_M8_MASK\0" + /* 257213 */ "PseudoVFSGNJ_VV_M8_MASK\0" + /* 257237 */ "PseudoVSLL_VV_M8_MASK\0" + /* 257259 */ "PseudoVSSRL_VV_M8_MASK\0" + /* 257282 */ "PseudoVSRL_VV_M8_MASK\0" + /* 257304 */ "PseudoVFMUL_VV_M8_MASK\0" + /* 257327 */ "PseudoVSMUL_VV_M8_MASK\0" + /* 257350 */ "PseudoVMUL_VV_M8_MASK\0" + /* 257372 */ "PseudoVREM_VV_M8_MASK\0" + /* 257394 */ "PseudoVFMIN_VV_M8_MASK\0" + /* 257417 */ "PseudoVMIN_VV_M8_MASK\0" + /* 257439 */ "PseudoVFSGNJN_VV_M8_MASK\0" + /* 257464 */ "PseudoVMFEQ_VV_M8_MASK\0" + /* 257487 */ "PseudoVMSEQ_VV_M8_MASK\0" + /* 257510 */ "PseudoVRGATHER_VV_M8_MASK\0" + /* 257536 */ "PseudoVOR_VV_M8_MASK\0" + /* 257557 */ "PseudoVXOR_VV_M8_MASK\0" + /* 257579 */ "PseudoVMFLT_VV_M8_MASK\0" + /* 257602 */ "PseudoVMSLT_VV_M8_MASK\0" + /* 257625 */ "PseudoVASUBU_VV_M8_MASK\0" + /* 257649 */ "PseudoVSSUBU_VV_M8_MASK\0" + /* 257673 */ "PseudoVAADDU_VV_M8_MASK\0" + /* 257697 */ "PseudoVSADDU_VV_M8_MASK\0" + /* 257721 */ "PseudoVMSLEU_VV_M8_MASK\0" + /* 257745 */ "PseudoVMULHU_VV_M8_MASK\0" + /* 257769 */ "PseudoVREMU_VV_M8_MASK\0" + /* 257792 */ "PseudoVMINU_VV_M8_MASK\0" + /* 257815 */ "PseudoVMULHSU_VV_M8_MASK\0" + /* 257840 */ "PseudoVMSLTU_VV_M8_MASK\0" + /* 257864 */ "PseudoVDIVU_VV_M8_MASK\0" + /* 257887 */ "PseudoVMAXU_VV_M8_MASK\0" + /* 257910 */ "PseudoVFDIV_VV_M8_MASK\0" + /* 257933 */ "PseudoVDIV_VV_M8_MASK\0" + /* 257955 */ "PseudoVFMAX_VV_M8_MASK\0" + /* 257978 */ "PseudoVMAX_VV_M8_MASK\0" + /* 258000 */ "PseudoVFSGNJX_VV_M8_MASK\0" + /* 258025 */ "PseudoVLE32_V_M8_MASK\0" + /* 258047 */ "PseudoVLSE32_V_M8_MASK\0" + /* 258070 */ "PseudoVSSE32_V_M8_MASK\0" + /* 258093 */ "PseudoVSE32_V_M8_MASK\0" + /* 258115 */ "PseudoVLE64_V_M8_MASK\0" + /* 258137 */ "PseudoVLSE64_V_M8_MASK\0" + /* 258160 */ "PseudoVSSE64_V_M8_MASK\0" + /* 258183 */ "PseudoVSE64_V_M8_MASK\0" + /* 258205 */ "PseudoVLE16_V_M8_MASK\0" + /* 258227 */ "PseudoVLSE16_V_M8_MASK\0" + /* 258250 */ "PseudoVSSE16_V_M8_MASK\0" + /* 258273 */ "PseudoVSE16_V_M8_MASK\0" + /* 258295 */ "PseudoVFREC7_V_M8_MASK\0" + /* 258318 */ "PseudoVFRSQRT7_V_M8_MASK\0" + /* 258343 */ "PseudoVLE8_V_M8_MASK\0" + /* 258364 */ "PseudoVLSE8_V_M8_MASK\0" + /* 258386 */ "PseudoVSSE8_V_M8_MASK\0" + /* 258408 */ "PseudoVSE8_V_M8_MASK\0" + /* 258429 */ "PseudoVID_V_M8_MASK\0" + /* 258449 */ "PseudoVLE32FF_V_M8_MASK\0" + /* 258473 */ "PseudoVLE64FF_V_M8_MASK\0" + /* 258497 */ "PseudoVLE16FF_V_M8_MASK\0" + /* 258521 */ "PseudoVLE8FF_V_M8_MASK\0" + /* 258544 */ "PseudoVFCVT_XU_F_V_M8_MASK\0" + /* 258571 */ "PseudoVFCVT_RTZ_XU_F_V_M8_MASK\0" + /* 258602 */ "PseudoVFCVT_X_F_V_M8_MASK\0" + /* 258628 */ "PseudoVFCVT_RTZ_X_F_V_M8_MASK\0" + /* 258658 */ "PseudoVFCLASS_V_M8_MASK\0" + /* 258682 */ "PseudoVFSQRT_V_M8_MASK\0" + /* 258705 */ "PseudoVFCVT_F_XU_V_M8_MASK\0" + /* 258732 */ "PseudoVFCVT_F_X_V_M8_MASK\0" + /* 258758 */ "PseudoVSSRA_VX_M8_MASK\0" + /* 258781 */ "PseudoVSRA_VX_M8_MASK\0" + /* 258803 */ "PseudoVASUB_VX_M8_MASK\0" + /* 258826 */ "PseudoVNMSUB_VX_M8_MASK\0" + /* 258850 */ "PseudoVRSUB_VX_M8_MASK\0" + /* 258873 */ "PseudoVSSUB_VX_M8_MASK\0" + /* 258896 */ "PseudoVSUB_VX_M8_MASK\0" + /* 258918 */ "PseudoVNMSAC_VX_M8_MASK\0" + /* 258942 */ "PseudoVMACC_VX_M8_MASK\0" + /* 258965 */ "PseudoVAADD_VX_M8_MASK\0" + /* 258988 */ "PseudoVMADD_VX_M8_MASK\0" + /* 259011 */ "PseudoVSADD_VX_M8_MASK\0" + /* 259034 */ "PseudoVADD_VX_M8_MASK\0" + /* 259056 */ "PseudoVAND_VX_M8_MASK\0" + /* 259078 */ "PseudoVMSLE_VX_M8_MASK\0" + /* 259101 */ "PseudoVMSNE_VX_M8_MASK\0" + /* 259124 */ "PseudoVMULH_VX_M8_MASK\0" + /* 259147 */ "PseudoVSLL_VX_M8_MASK\0" + /* 259169 */ "PseudoVSSRL_VX_M8_MASK\0" + /* 259192 */ "PseudoVSRL_VX_M8_MASK\0" + /* 259214 */ "PseudoVSMUL_VX_M8_MASK\0" + /* 259237 */ "PseudoVMUL_VX_M8_MASK\0" + /* 259259 */ "PseudoVREM_VX_M8_MASK\0" + /* 259281 */ "PseudoVMIN_VX_M8_MASK\0" + /* 259303 */ "PseudoVSLIDE1DOWN_VX_M8_MASK\0" + /* 259332 */ "PseudoVSLIDEDOWN_VX_M8_MASK\0" + /* 259360 */ "PseudoVSLIDE1UP_VX_M8_MASK\0" + /* 259387 */ "PseudoVSLIDEUP_VX_M8_MASK\0" + /* 259413 */ "PseudoVMSEQ_VX_M8_MASK\0" + /* 259436 */ "PseudoVRGATHER_VX_M8_MASK\0" + /* 259462 */ "PseudoVOR_VX_M8_MASK\0" + /* 259483 */ "PseudoVXOR_VX_M8_MASK\0" + /* 259505 */ "PseudoVMSGT_VX_M8_MASK\0" + /* 259528 */ "PseudoVMSLT_VX_M8_MASK\0" + /* 259551 */ "PseudoVASUBU_VX_M8_MASK\0" + /* 259575 */ "PseudoVSSUBU_VX_M8_MASK\0" + /* 259599 */ "PseudoVAADDU_VX_M8_MASK\0" + /* 259623 */ "PseudoVSADDU_VX_M8_MASK\0" + /* 259647 */ "PseudoVMSLEU_VX_M8_MASK\0" + /* 259671 */ "PseudoVMULHU_VX_M8_MASK\0" + /* 259695 */ "PseudoVREMU_VX_M8_MASK\0" + /* 259718 */ "PseudoVMINU_VX_M8_MASK\0" + /* 259741 */ "PseudoVMULHSU_VX_M8_MASK\0" + /* 259766 */ "PseudoVMSGTU_VX_M8_MASK\0" + /* 259790 */ "PseudoVMSLTU_VX_M8_MASK\0" + /* 259814 */ "PseudoVDIVU_VX_M8_MASK\0" + /* 259837 */ "PseudoVMAXU_VX_M8_MASK\0" + /* 259860 */ "PseudoVDIV_VX_M8_MASK\0" + /* 259882 */ "PseudoVMAX_VX_M8_MASK\0" + /* 259904 */ "C_JAL\0" + /* 259910 */ "GC_LABEL\0" + /* 259919 */ "DBG_LABEL\0" + /* 259929 */ "EH_LABEL\0" + /* 259938 */ "ANNOTATION_LABEL\0" + /* 259955 */ "ICALL_BRANCH_FUNNEL\0" + /* 259975 */ "UNSHFL\0" + /* 259982 */ "G_FSHL\0" + /* 259989 */ "G_SHL\0" + /* 259995 */ "PseudoTAIL\0" + /* 260006 */ "G_FCEIL\0" + /* 260014 */ "ECALL\0" + /* 260020 */ "PATCHABLE_TAIL_CALL\0" + /* 260040 */ "PATCHABLE_TYPED_EVENT_CALL\0" + /* 260067 */ "PATCHABLE_EVENT_CALL\0" + /* 260088 */ "FENTRY_CALL\0" + /* 260100 */ "PseudoCALL\0" + /* 260111 */ "KILL\0" + /* 260116 */ "SLL\0" + /* 260120 */ "ROL\0" + /* 260124 */ "SRL\0" + /* 260128 */ "SC_D_RL\0" + /* 260136 */ "AMOADD_D_RL\0" + /* 260148 */ "AMOAND_D_RL\0" + /* 260160 */ "AMOMIN_D_RL\0" + /* 260172 */ "AMOSWAP_D_RL\0" + /* 260185 */ "LR_D_RL\0" + /* 260193 */ "AMOOR_D_RL\0" + /* 260204 */ "AMOXOR_D_RL\0" + /* 260216 */ "AMOMINU_D_RL\0" + /* 260229 */ "AMOMAXU_D_RL\0" + /* 260242 */ "AMOMAX_D_RL\0" + /* 260254 */ "SC_D_AQ_RL\0" + /* 260265 */ "AMOADD_D_AQ_RL\0" + /* 260280 */ "AMOAND_D_AQ_RL\0" + /* 260295 */ "AMOMIN_D_AQ_RL\0" + /* 260310 */ "AMOSWAP_D_AQ_RL\0" + /* 260326 */ "LR_D_AQ_RL\0" + /* 260337 */ "AMOOR_D_AQ_RL\0" + /* 260351 */ "AMOXOR_D_AQ_RL\0" + /* 260366 */ "AMOMINU_D_AQ_RL\0" + /* 260382 */ "AMOMAXU_D_AQ_RL\0" + /* 260398 */ "AMOMAX_D_AQ_RL\0" + /* 260413 */ "SC_W_AQ_RL\0" + /* 260424 */ "AMOADD_W_AQ_RL\0" + /* 260439 */ "AMOAND_W_AQ_RL\0" + /* 260454 */ "AMOMIN_W_AQ_RL\0" + /* 260469 */ "AMOSWAP_W_AQ_RL\0" + /* 260485 */ "LR_W_AQ_RL\0" + /* 260496 */ "AMOOR_W_AQ_RL\0" + /* 260510 */ "AMOXOR_W_AQ_RL\0" + /* 260525 */ "AMOMINU_W_AQ_RL\0" + /* 260541 */ "AMOMAXU_W_AQ_RL\0" + /* 260557 */ "AMOMAX_W_AQ_RL\0" + /* 260572 */ "SC_W_RL\0" + /* 260580 */ "AMOADD_W_RL\0" + /* 260592 */ "AMOAND_W_RL\0" + /* 260604 */ "AMOMIN_W_RL\0" + /* 260616 */ "AMOSWAP_W_RL\0" + /* 260629 */ "LR_W_RL\0" + /* 260637 */ "AMOOR_W_RL\0" + /* 260648 */ "AMOXOR_W_RL\0" + /* 260660 */ "AMOMINU_W_RL\0" + /* 260673 */ "AMOMAXU_W_RL\0" + /* 260686 */ "AMOMAX_W_RL\0" + /* 260698 */ "FSL\0" + /* 260702 */ "G_ROTL\0" + /* 260709 */ "G_VECREDUCE_FMUL\0" + /* 260726 */ "G_FMUL\0" + /* 260733 */ "G_VECREDUCE_SEQ_FMUL\0" + /* 260754 */ "G_STRICT_FMUL\0" + /* 260768 */ "CLMUL\0" + /* 260774 */ "G_VECREDUCE_MUL\0" + /* 260790 */ "G_MUL\0" + /* 260796 */ "VSETVL\0" + /* 260803 */ "PseudoReadVL\0" + /* 260816 */ "FCVT_D_L\0" + /* 260825 */ "FCVT_H_L\0" + /* 260834 */ "FCVT_S_L\0" + /* 260843 */ "G_FREM\0" + /* 260850 */ "G_STRICT_FREM\0" + /* 260864 */ "G_SREM\0" + /* 260871 */ "G_UREM\0" + /* 260878 */ "G_SDIVREM\0" + /* 260888 */ "G_UDIVREM\0" + /* 260898 */ "VFMERGE_VFM\0" + /* 260910 */ "VMADC_VIM\0" + /* 260920 */ "VADC_VIM\0" + /* 260929 */ "VMERGE_VIM\0" + /* 260940 */ "VMAND_MM\0" + /* 260949 */ "VMNAND_MM\0" + /* 260959 */ "VMANDN_MM\0" + /* 260969 */ "VMORN_MM\0" + /* 260978 */ "VMOR_MM\0" + /* 260986 */ "VMNOR_MM\0" + /* 260995 */ "VMXNOR_MM\0" + /* 261005 */ "VMXOR_MM\0" + /* 261014 */ "ReadFRM\0" + /* 261022 */ "WriteFRM\0" + /* 261031 */ "INLINEASM\0" + /* 261041 */ "G_FMINIMUM\0" + /* 261052 */ "G_FMAXIMUM\0" + /* 261063 */ "G_FMINNUM\0" + /* 261073 */ "G_FMAXNUM\0" + /* 261083 */ "VMSBC_VVM\0" + /* 261093 */ "VSBC_VVM\0" + /* 261102 */ "VMADC_VVM\0" + /* 261112 */ "VADC_VVM\0" + /* 261121 */ "VMERGE_VVM\0" + /* 261132 */ "VCOMPRESS_VM\0" + /* 261145 */ "VMSBC_VXM\0" + /* 261155 */ "VSBC_VXM\0" + /* 261164 */ "VMADC_VXM\0" + /* 261174 */ "VADC_VXM\0" + /* 261183 */ "VMERGE_VXM\0" + /* 261194 */ "VIOTA_M\0" + /* 261202 */ "VMSBF_M\0" + /* 261210 */ "VMSIF_M\0" + /* 261218 */ "VMSOF_M\0" + /* 261226 */ "VCPOP_M\0" + /* 261234 */ "VFIRST_M\0" + /* 261243 */ "PseudoVMSGE_VX_M\0" + /* 261260 */ "PseudoVMSGEU_VX_M\0" + /* 261278 */ "ANDN\0" + /* 261283 */ "G_INTRINSIC_ROUNDEVEN\0" + /* 261305 */ "G_FCOPYSIGN\0" + /* 261317 */ "G_VECREDUCE_FMIN\0" + /* 261334 */ "G_VECREDUCE_SMIN\0" + /* 261351 */ "G_SMIN\0" + /* 261358 */ "G_VECREDUCE_UMIN\0" + /* 261375 */ "G_UMIN\0" + /* 261382 */ "G_ATOMICRMW_UMIN\0" + /* 261399 */ "G_ATOMICRMW_MIN\0" + /* 261415 */ "G_FSIN\0" + /* 261422 */ "XPERMN\0" + /* 261429 */ "CFI_INSTRUCTION\0" + /* 261445 */ "C_ADDI4SPN\0" + /* 261456 */ "ORN\0" + /* 261460 */ "ADJCALLSTACKDOWN\0" + /* 261477 */ "G_SSUBO\0" + /* 261485 */ "G_USUBO\0" + /* 261493 */ "G_SADDO\0" + /* 261501 */ "G_UADDO\0" + /* 261509 */ "G_SMULO\0" + /* 261517 */ "G_UMULO\0" + /* 261525 */ "G_BZERO\0" + /* 261533 */ "C_ADDI_HINT_IMM_ZERO\0" + /* 261554 */ "FENCE_TSO\0" + /* 261564 */ "STACKMAP\0" + /* 261573 */ "G_BSWAP\0" + /* 261581 */ "BFP\0" + /* 261585 */ "G_SITOFP\0" + /* 261594 */ "G_UITOFP\0" + /* 261603 */ "BMATFLIP\0" + /* 261612 */ "G_FCMP\0" + /* 261619 */ "G_ICMP\0" + /* 261626 */ "C_UNIMP\0" + /* 261634 */ "C_NOP\0" + /* 261640 */ "C_ADDI_NOP\0" + /* 261651 */ "CPOP\0" + /* 261656 */ "G_CTPOP\0" + /* 261664 */ "PATCHABLE_OP\0" + /* 261677 */ "FAULTING_OP\0" + /* 261689 */ "C_ADDI16SP\0" + /* 261700 */ "C_FLDSP\0" + /* 261708 */ "C_LDSP\0" + /* 261715 */ "C_FSDSP\0" + /* 261723 */ "C_SDSP\0" + /* 261730 */ "C_FLWSP\0" + /* 261738 */ "C_LWSP\0" + /* 261745 */ "C_FSWSP\0" + /* 261753 */ "C_SWSP\0" + /* 261760 */ "ADJCALLSTACKUP\0" + /* 261775 */ "PREALLOCATED_SETUP\0" + /* 261794 */ "G_FEXP\0" + /* 261801 */ "SC_D_AQ\0" + /* 261809 */ "AMOADD_D_AQ\0" + /* 261821 */ "AMOAND_D_AQ\0" + /* 261833 */ "AMOMIN_D_AQ\0" + /* 261845 */ "AMOSWAP_D_AQ\0" + /* 261858 */ "LR_D_AQ\0" + /* 261866 */ "AMOOR_D_AQ\0" + /* 261877 */ "AMOXOR_D_AQ\0" + /* 261889 */ "AMOMINU_D_AQ\0" + /* 261902 */ "AMOMAXU_D_AQ\0" + /* 261915 */ "AMOMAX_D_AQ\0" + /* 261927 */ "SC_W_AQ\0" + /* 261935 */ "AMOADD_W_AQ\0" + /* 261947 */ "AMOAND_W_AQ\0" + /* 261959 */ "AMOMIN_W_AQ\0" + /* 261971 */ "AMOSWAP_W_AQ\0" + /* 261984 */ "LR_W_AQ\0" + /* 261992 */ "AMOOR_W_AQ\0" + /* 262003 */ "AMOXOR_W_AQ\0" + /* 262015 */ "AMOMINU_W_AQ\0" + /* 262028 */ "AMOMAXU_W_AQ\0" + /* 262041 */ "AMOMAX_W_AQ\0" + /* 262053 */ "BEQ\0" + /* 262057 */ "G_BR\0" + /* 262062 */ "INLINEASM_BR\0" + /* 262075 */ "PseudoBR\0" + /* 262084 */ "G_BLOCK_ADDR\0" + /* 262097 */ "PATCHABLE_FUNCTION_ENTER\0" + /* 262122 */ "G_READCYCLECOUNTER\0" + /* 262141 */ "G_READ_REGISTER\0" + /* 262157 */ "G_WRITE_REGISTER\0" + /* 262174 */ "G_ASHR\0" + /* 262181 */ "G_FSHR\0" + /* 262188 */ "G_LSHR\0" + /* 262195 */ "C_JR\0" + /* 262200 */ "C_JALR\0" + /* 262207 */ "BCLR\0" + /* 262212 */ "CLMULR\0" + /* 262219 */ "XNOR\0" + /* 262224 */ "G_FFLOOR\0" + /* 262233 */ "ROR\0" + /* 262237 */ "BMATOR\0" + /* 262244 */ "G_BUILD_VECTOR\0" + /* 262259 */ "G_SHUFFLE_VECTOR\0" + /* 262276 */ "BMATXOR\0" + /* 262284 */ "C_XOR\0" + /* 262290 */ "G_VECREDUCE_XOR\0" + /* 262306 */ "G_XOR\0" + /* 262312 */ "G_ATOMICRMW_XOR\0" + /* 262328 */ "C_OR\0" + /* 262333 */ "G_VECREDUCE_OR\0" + /* 262348 */ "G_OR\0" + /* 262353 */ "G_ATOMICRMW_OR\0" + /* 262368 */ "Select_FPR32_Using_CC_GPR\0" + /* 262394 */ "Select_FPR64_Using_CC_GPR\0" + /* 262420 */ "Select_FPR16_Using_CC_GPR\0" + /* 262446 */ "Select_GPR_Using_CC_GPR\0" + /* 262470 */ "FSR\0" + /* 262474 */ "G_ROTR\0" + /* 262481 */ "G_INTTOPTR\0" + /* 262492 */ "InsnR\0" + /* 262498 */ "G_FABS\0" + /* 262505 */ "G_ABS\0" + /* 262511 */ "G_UNMERGE_VALUES\0" + /* 262528 */ "G_MERGE_VALUES\0" + /* 262543 */ "G_FCOS\0" + /* 262550 */ "G_CONCAT_VECTORS\0" + /* 262567 */ "CSRRS\0" + /* 262573 */ "COPY_TO_REGCLASS\0" + /* 262590 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" + /* 262620 */ "BCOMPRESS\0" + /* 262630 */ "BDECOMPRESS\0" + /* 262642 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" + /* 262669 */ "VREDAND_VS\0" + /* 262680 */ "VREDSUM_VS\0" + /* 262691 */ "VWREDSUM_VS\0" + /* 262703 */ "VFREDOSUM_VS\0" + /* 262716 */ "VFWREDOSUM_VS\0" + /* 262730 */ "VFREDUSUM_VS\0" + /* 262743 */ "VFWREDUSUM_VS\0" + /* 262757 */ "VFREDMIN_VS\0" + /* 262769 */ "VREDMIN_VS\0" + /* 262780 */ "VREDOR_VS\0" + /* 262790 */ "VREDXOR_VS\0" + /* 262801 */ "VWREDSUMU_VS\0" + /* 262814 */ "VREDMINU_VS\0" + /* 262826 */ "VREDMAXU_VS\0" + /* 262838 */ "VFREDMAX_VS\0" + /* 262850 */ "VREDMAX_VS\0" + /* 262861 */ "FSUB_S\0" + /* 262868 */ "FMSUB_S\0" + /* 262876 */ "FNMSUB_S\0" + /* 262885 */ "FADD_S\0" + /* 262892 */ "FMADD_S\0" + /* 262900 */ "FNMADD_S\0" + /* 262909 */ "FCVT_D_S\0" + /* 262918 */ "FLE_S\0" + /* 262924 */ "VFMV_F_S\0" + /* 262933 */ "FCVT_H_S\0" + /* 262942 */ "FSGNJ_S\0" + /* 262950 */ "FMUL_S\0" + /* 262957 */ "FCVT_L_S\0" + /* 262966 */ "FMIN_S\0" + /* 262973 */ "FSGNJN_S\0" + /* 262982 */ "FEQ_S\0" + /* 262988 */ "FCLASS_S\0" + /* 262997 */ "FLT_S\0" + /* 263003 */ "FSQRT_S\0" + /* 263011 */ "FCVT_LU_S\0" + /* 263021 */ "FCVT_WU_S\0" + /* 263031 */ "FDIV_S\0" + /* 263038 */ "FCVT_W_S\0" + /* 263047 */ "FMAX_S\0" + /* 263054 */ "FSGNJX_S\0" + /* 263063 */ "VMV_X_S\0" + /* 263071 */ "InsnS\0" + /* 263077 */ "G_SSUBSAT\0" + /* 263087 */ "G_USUBSAT\0" + /* 263097 */ "G_SADDSAT\0" + /* 263107 */ "G_UADDSAT\0" + /* 263117 */ "G_SSHLSAT\0" + /* 263127 */ "G_USHLSAT\0" + /* 263137 */ "G_SMULFIXSAT\0" + /* 263150 */ "G_UMULFIXSAT\0" + /* 263163 */ "G_SDIVFIXSAT\0" + /* 263176 */ "G_UDIVFIXSAT\0" + /* 263189 */ "G_EXTRACT\0" + /* 263199 */ "G_SELECT\0" + /* 263208 */ "G_BRINDIRECT\0" + /* 263221 */ "DRET\0" + /* 263226 */ "MRET\0" + /* 263231 */ "SRET\0" + /* 263236 */ "URET\0" + /* 263241 */ "PATCHABLE_RET\0" + /* 263255 */ "PseudoRET\0" + /* 263265 */ "BSET\0" + /* 263270 */ "G_MEMSET\0" + /* 263279 */ "PATCHABLE_FUNCTION_EXIT\0" + /* 263303 */ "G_BRJT\0" + /* 263310 */ "BLT\0" + /* 263314 */ "G_EXTRACT_VECTOR_ELT\0" + /* 263335 */ "G_INSERT_VECTOR_ELT\0" + /* 263355 */ "SLT\0" + /* 263359 */ "G_FCONSTANT\0" + /* 263371 */ "G_CONSTANT\0" + /* 263382 */ "C_SRAI64_HINT\0" + /* 263396 */ "C_SLLI64_HINT\0" + /* 263410 */ "C_SRLI64_HINT\0" + /* 263424 */ "C_ADD_HINT\0" + /* 263435 */ "C_SLLI_HINT\0" + /* 263447 */ "C_LI_HINT\0" + /* 263457 */ "C_LUI_HINT\0" + /* 263468 */ "C_NOP_HINT\0" + /* 263479 */ "C_MV_HINT\0" + /* 263489 */ "STATEPOINT\0" + /* 263500 */ "PATCHPOINT\0" + /* 263511 */ "G_PTRTOINT\0" + /* 263522 */ "G_FRINT\0" + /* 263530 */ "G_INTRINSIC_LRINT\0" + /* 263548 */ "G_FNEARBYINT\0" + /* 263561 */ "G_VASTART\0" + /* 263571 */ "LIFETIME_START\0" + /* 263586 */ "G_INSERT\0" + /* 263595 */ "G_FSQRT\0" + /* 263603 */ "G_STRICT_FSQRT\0" + /* 263618 */ "G_BITCAST\0" + /* 263628 */ "G_ADDRSPACE_CAST\0" + /* 263645 */ "DBG_VALUE_LIST\0" + /* 263660 */ "BEXT\0" + /* 263665 */ "G_FPEXT\0" + /* 263673 */ "G_SEXT\0" + /* 263680 */ "G_ASSERT_SEXT\0" + /* 263694 */ "G_ANYEXT\0" + /* 263703 */ "G_ZEXT\0" + /* 263710 */ "G_ASSERT_ZEXT\0" + /* 263724 */ "PseudoVMSGE_VX_M_T\0" + /* 263743 */ "PseudoVMSGEU_VX_M_T\0" + /* 263763 */ "PseudoLBU\0" + /* 263773 */ "BGEU\0" + /* 263778 */ "MULHU\0" + /* 263784 */ "PseudoLHU\0" + /* 263794 */ "SLTIU\0" + /* 263800 */ "PACKU\0" + /* 263806 */ "FCVT_D_LU\0" + /* 263816 */ "FCVT_H_LU\0" + /* 263826 */ "FCVT_S_LU\0" + /* 263836 */ "REMU\0" + /* 263841 */ "MINU\0" + /* 263846 */ "MULHSU\0" + /* 263853 */ "BLTU\0" + /* 263858 */ "SLTU\0" + /* 263863 */ "DIVU\0" + /* 263868 */ "PseudoLWU\0" + /* 263878 */ "FCVT_D_WU\0" + /* 263888 */ "FCVT_H_WU\0" + /* 263898 */ "FCVT_S_WU\0" + /* 263908 */ "MAXU\0" + /* 263913 */ "InsnU\0" + /* 263919 */ "GREV\0" + /* 263924 */ "G_FDIV\0" + /* 263931 */ "G_STRICT_FDIV\0" + /* 263945 */ "G_SDIV\0" + /* 263952 */ "G_UDIV\0" + /* 263959 */ "C_MV\0" + /* 263964 */ "BINV\0" + /* 263969 */ "CMOV\0" + /* 263974 */ "VRGATHEREI16_VV\0" + /* 263990 */ "VSSRA_VV\0" + /* 263999 */ "VSRA_VV\0" + /* 264007 */ "VASUB_VV\0" + /* 264016 */ "VFSUB_VV\0" + /* 264025 */ "VFMSUB_VV\0" + /* 264035 */ "VFNMSUB_VV\0" + /* 264046 */ "VNMSUB_VV\0" + /* 264056 */ "VSSUB_VV\0" + /* 264065 */ "VSUB_VV\0" + /* 264073 */ "VFWSUB_VV\0" + /* 264083 */ "VWSUB_VV\0" + /* 264092 */ "VFMSAC_VV\0" + /* 264102 */ "VFNMSAC_VV\0" + /* 264113 */ "VNMSAC_VV\0" + /* 264123 */ "VFWNMSAC_VV\0" + /* 264135 */ "VFWMSAC_VV\0" + /* 264146 */ "VMSBC_VV\0" + /* 264155 */ "VFMACC_VV\0" + /* 264165 */ "VFNMACC_VV\0" + /* 264176 */ "VFWNMACC_VV\0" + /* 264188 */ "VMACC_VV\0" + /* 264197 */ "VFWMACC_VV\0" + /* 264208 */ "VWMACC_VV\0" + /* 264218 */ "VMADC_VV\0" + /* 264227 */ "VAADD_VV\0" + /* 264236 */ "VFADD_VV\0" + /* 264245 */ "VFMADD_VV\0" + /* 264255 */ "VFNMADD_VV\0" + /* 264266 */ "VMADD_VV\0" + /* 264275 */ "VSADD_VV\0" + /* 264284 */ "VADD_VV\0" + /* 264292 */ "VFWADD_VV\0" + /* 264302 */ "VWADD_VV\0" + /* 264311 */ "VAND_VV\0" + /* 264319 */ "VMFLE_VV\0" + /* 264328 */ "VMSLE_VV\0" + /* 264337 */ "VMFNE_VV\0" + /* 264346 */ "VMSNE_VV\0" + /* 264355 */ "VMULH_VV\0" + /* 264364 */ "VFSGNJ_VV\0" + /* 264374 */ "VSLL_VV\0" + /* 264382 */ "VSSRL_VV\0" + /* 264391 */ "VSRL_VV\0" + /* 264399 */ "VFMUL_VV\0" + /* 264408 */ "VSMUL_VV\0" + /* 264417 */ "VMUL_VV\0" + /* 264425 */ "VFWMUL_VV\0" + /* 264435 */ "VWMUL_VV\0" + /* 264444 */ "VREM_VV\0" + /* 264452 */ "VFMIN_VV\0" + /* 264461 */ "VMIN_VV\0" + /* 264469 */ "VFSGNJN_VV\0" + /* 264480 */ "VMFEQ_VV\0" + /* 264489 */ "VMSEQ_VV\0" + /* 264498 */ "VRGATHER_VV\0" + /* 264510 */ "VOR_VV\0" + /* 264517 */ "VXOR_VV\0" + /* 264525 */ "VMFLT_VV\0" + /* 264534 */ "VMSLT_VV\0" + /* 264543 */ "VASUBU_VV\0" + /* 264553 */ "VSSUBU_VV\0" + /* 264563 */ "VWSUBU_VV\0" + /* 264573 */ "VWMACCU_VV\0" + /* 264584 */ "VAADDU_VV\0" + /* 264594 */ "VSADDU_VV\0" + /* 264604 */ "VWADDU_VV\0" + /* 264614 */ "VMSLEU_VV\0" + /* 264624 */ "VMULHU_VV\0" + /* 264634 */ "VWMULU_VV\0" + /* 264644 */ "VREMU_VV\0" + /* 264653 */ "VMINU_VV\0" + /* 264662 */ "VWMACCSU_VV\0" + /* 264674 */ "VMULHSU_VV\0" + /* 264685 */ "VWMULSU_VV\0" + /* 264696 */ "VMSLTU_VV\0" + /* 264706 */ "VDIVU_VV\0" + /* 264715 */ "VMAXU_VV\0" + /* 264724 */ "VFDIV_VV\0" + /* 264733 */ "VDIV_VV\0" + /* 264741 */ "VFMAX_VV\0" + /* 264750 */ "VMAX_VV\0" + /* 264758 */ "VFSGNJX_VV\0" + /* 264769 */ "VNSRA_WV\0" + /* 264778 */ "VFWSUB_WV\0" + /* 264788 */ "VWSUB_WV\0" + /* 264797 */ "VFWADD_WV\0" + /* 264807 */ "VWADD_WV\0" + /* 264816 */ "VNSRL_WV\0" + /* 264825 */ "VNCLIP_WV\0" + /* 264835 */ "VWSUBU_WV\0" + /* 264845 */ "VWADDU_WV\0" + /* 264855 */ "VNCLIPU_WV\0" + /* 264866 */ "VLSEG2E32_V\0" + /* 264878 */ "VLSSEG2E32_V\0" + /* 264891 */ "VSSSEG2E32_V\0" + /* 264904 */ "VSSEG2E32_V\0" + /* 264916 */ "VLSEG3E32_V\0" + /* 264928 */ "VLSSEG3E32_V\0" + /* 264941 */ "VSSSEG3E32_V\0" + /* 264954 */ "VSSEG3E32_V\0" + /* 264966 */ "VLSEG4E32_V\0" + /* 264978 */ "VLSSEG4E32_V\0" + /* 264991 */ "VSSSEG4E32_V\0" + /* 265004 */ "VSSEG4E32_V\0" + /* 265016 */ "VLSEG5E32_V\0" + /* 265028 */ "VLSSEG5E32_V\0" + /* 265041 */ "VSSSEG5E32_V\0" + /* 265054 */ "VSSEG5E32_V\0" + /* 265066 */ "VLSEG6E32_V\0" + /* 265078 */ "VLSSEG6E32_V\0" + /* 265091 */ "VSSSEG6E32_V\0" + /* 265104 */ "VSSEG6E32_V\0" + /* 265116 */ "VLSEG7E32_V\0" + /* 265128 */ "VLSSEG7E32_V\0" + /* 265141 */ "VSSSEG7E32_V\0" + /* 265154 */ "VSSEG7E32_V\0" + /* 265166 */ "VLSEG8E32_V\0" + /* 265178 */ "VLSSEG8E32_V\0" + /* 265191 */ "VSSSEG8E32_V\0" + /* 265204 */ "VSSEG8E32_V\0" + /* 265216 */ "VLE32_V\0" + /* 265224 */ "VL1RE32_V\0" + /* 265234 */ "VL2RE32_V\0" + /* 265244 */ "VL4RE32_V\0" + /* 265254 */ "VL8RE32_V\0" + /* 265264 */ "VLSE32_V\0" + /* 265273 */ "VSSE32_V\0" + /* 265282 */ "VSE32_V\0" + /* 265290 */ "VLOXSEG2EI32_V\0" + /* 265305 */ "VSOXSEG2EI32_V\0" + /* 265320 */ "VLUXSEG2EI32_V\0" + /* 265335 */ "VSUXSEG2EI32_V\0" + /* 265350 */ "VLOXSEG3EI32_V\0" + /* 265365 */ "VSOXSEG3EI32_V\0" + /* 265380 */ "VLUXSEG3EI32_V\0" + /* 265395 */ "VSUXSEG3EI32_V\0" + /* 265410 */ "VLOXSEG4EI32_V\0" + /* 265425 */ "VSOXSEG4EI32_V\0" + /* 265440 */ "VLUXSEG4EI32_V\0" + /* 265455 */ "VSUXSEG4EI32_V\0" + /* 265470 */ "VLOXSEG5EI32_V\0" + /* 265485 */ "VSOXSEG5EI32_V\0" + /* 265500 */ "VLUXSEG5EI32_V\0" + /* 265515 */ "VSUXSEG5EI32_V\0" + /* 265530 */ "VLOXSEG6EI32_V\0" + /* 265545 */ "VSOXSEG6EI32_V\0" + /* 265560 */ "VLUXSEG6EI32_V\0" + /* 265575 */ "VSUXSEG6EI32_V\0" + /* 265590 */ "VLOXSEG7EI32_V\0" + /* 265605 */ "VSOXSEG7EI32_V\0" + /* 265620 */ "VLUXSEG7EI32_V\0" + /* 265635 */ "VSUXSEG7EI32_V\0" + /* 265650 */ "VLOXSEG8EI32_V\0" + /* 265665 */ "VSOXSEG8EI32_V\0" + /* 265680 */ "VLUXSEG8EI32_V\0" + /* 265695 */ "VSUXSEG8EI32_V\0" + /* 265710 */ "VLOXEI32_V\0" + /* 265721 */ "VSOXEI32_V\0" + /* 265732 */ "VLUXEI32_V\0" + /* 265743 */ "VSUXEI32_V\0" + /* 265754 */ "VLSEG2E64_V\0" + /* 265766 */ "VLSSEG2E64_V\0" + /* 265779 */ "VSSSEG2E64_V\0" + /* 265792 */ "VSSEG2E64_V\0" + /* 265804 */ "VLSEG3E64_V\0" + /* 265816 */ "VLSSEG3E64_V\0" + /* 265829 */ "VSSSEG3E64_V\0" + /* 265842 */ "VSSEG3E64_V\0" + /* 265854 */ "VLSEG4E64_V\0" + /* 265866 */ "VLSSEG4E64_V\0" + /* 265879 */ "VSSSEG4E64_V\0" + /* 265892 */ "VSSEG4E64_V\0" + /* 265904 */ "VLSEG5E64_V\0" + /* 265916 */ "VLSSEG5E64_V\0" + /* 265929 */ "VSSSEG5E64_V\0" + /* 265942 */ "VSSEG5E64_V\0" + /* 265954 */ "VLSEG6E64_V\0" + /* 265966 */ "VLSSEG6E64_V\0" + /* 265979 */ "VSSSEG6E64_V\0" + /* 265992 */ "VSSEG6E64_V\0" + /* 266004 */ "VLSEG7E64_V\0" + /* 266016 */ "VLSSEG7E64_V\0" + /* 266029 */ "VSSSEG7E64_V\0" + /* 266042 */ "VSSEG7E64_V\0" + /* 266054 */ "VLSEG8E64_V\0" + /* 266066 */ "VLSSEG8E64_V\0" + /* 266079 */ "VSSSEG8E64_V\0" + /* 266092 */ "VSSEG8E64_V\0" + /* 266104 */ "VLE64_V\0" + /* 266112 */ "VL1RE64_V\0" + /* 266122 */ "VL2RE64_V\0" + /* 266132 */ "VL4RE64_V\0" + /* 266142 */ "VL8RE64_V\0" + /* 266152 */ "VLSE64_V\0" + /* 266161 */ "VSSE64_V\0" + /* 266170 */ "VSE64_V\0" + /* 266178 */ "VLOXSEG2EI64_V\0" + /* 266193 */ "VSOXSEG2EI64_V\0" + /* 266208 */ "VLUXSEG2EI64_V\0" + /* 266223 */ "VSUXSEG2EI64_V\0" + /* 266238 */ "VLOXSEG3EI64_V\0" + /* 266253 */ "VSOXSEG3EI64_V\0" + /* 266268 */ "VLUXSEG3EI64_V\0" + /* 266283 */ "VSUXSEG3EI64_V\0" + /* 266298 */ "VLOXSEG4EI64_V\0" + /* 266313 */ "VSOXSEG4EI64_V\0" + /* 266328 */ "VLUXSEG4EI64_V\0" + /* 266343 */ "VSUXSEG4EI64_V\0" + /* 266358 */ "VLOXSEG5EI64_V\0" + /* 266373 */ "VSOXSEG5EI64_V\0" + /* 266388 */ "VLUXSEG5EI64_V\0" + /* 266403 */ "VSUXSEG5EI64_V\0" + /* 266418 */ "VLOXSEG6EI64_V\0" + /* 266433 */ "VSOXSEG6EI64_V\0" + /* 266448 */ "VLUXSEG6EI64_V\0" + /* 266463 */ "VSUXSEG6EI64_V\0" + /* 266478 */ "VLOXSEG7EI64_V\0" + /* 266493 */ "VSOXSEG7EI64_V\0" + /* 266508 */ "VLUXSEG7EI64_V\0" + /* 266523 */ "VSUXSEG7EI64_V\0" + /* 266538 */ "VLOXSEG8EI64_V\0" + /* 266553 */ "VSOXSEG8EI64_V\0" + /* 266568 */ "VLUXSEG8EI64_V\0" + /* 266583 */ "VSUXSEG8EI64_V\0" + /* 266598 */ "VLOXEI64_V\0" + /* 266609 */ "VSOXEI64_V\0" + /* 266620 */ "VLUXEI64_V\0" + /* 266631 */ "VSUXEI64_V\0" + /* 266642 */ "VLSEG2E16_V\0" + /* 266654 */ "VLSSEG2E16_V\0" + /* 266667 */ "VSSSEG2E16_V\0" + /* 266680 */ "VSSEG2E16_V\0" + /* 266692 */ "VLSEG3E16_V\0" + /* 266704 */ "VLSSEG3E16_V\0" + /* 266717 */ "VSSSEG3E16_V\0" + /* 266730 */ "VSSEG3E16_V\0" + /* 266742 */ "VLSEG4E16_V\0" + /* 266754 */ "VLSSEG4E16_V\0" + /* 266767 */ "VSSSEG4E16_V\0" + /* 266780 */ "VSSEG4E16_V\0" + /* 266792 */ "VLSEG5E16_V\0" + /* 266804 */ "VLSSEG5E16_V\0" + /* 266817 */ "VSSSEG5E16_V\0" + /* 266830 */ "VSSEG5E16_V\0" + /* 266842 */ "VLSEG6E16_V\0" + /* 266854 */ "VLSSEG6E16_V\0" + /* 266867 */ "VSSSEG6E16_V\0" + /* 266880 */ "VSSEG6E16_V\0" + /* 266892 */ "VLSEG7E16_V\0" + /* 266904 */ "VLSSEG7E16_V\0" + /* 266917 */ "VSSSEG7E16_V\0" + /* 266930 */ "VSSEG7E16_V\0" + /* 266942 */ "VLSEG8E16_V\0" + /* 266954 */ "VLSSEG8E16_V\0" + /* 266967 */ "VSSSEG8E16_V\0" + /* 266980 */ "VSSEG8E16_V\0" + /* 266992 */ "VLE16_V\0" + /* 267000 */ "VL1RE16_V\0" + /* 267010 */ "VL2RE16_V\0" + /* 267020 */ "VL4RE16_V\0" + /* 267030 */ "VL8RE16_V\0" + /* 267040 */ "VLSE16_V\0" + /* 267049 */ "VSSE16_V\0" + /* 267058 */ "VSE16_V\0" + /* 267066 */ "VLOXSEG2EI16_V\0" + /* 267081 */ "VSOXSEG2EI16_V\0" + /* 267096 */ "VLUXSEG2EI16_V\0" + /* 267111 */ "VSUXSEG2EI16_V\0" + /* 267126 */ "VLOXSEG3EI16_V\0" + /* 267141 */ "VSOXSEG3EI16_V\0" + /* 267156 */ "VLUXSEG3EI16_V\0" + /* 267171 */ "VSUXSEG3EI16_V\0" + /* 267186 */ "VLOXSEG4EI16_V\0" + /* 267201 */ "VSOXSEG4EI16_V\0" + /* 267216 */ "VLUXSEG4EI16_V\0" + /* 267231 */ "VSUXSEG4EI16_V\0" + /* 267246 */ "VLOXSEG5EI16_V\0" + /* 267261 */ "VSOXSEG5EI16_V\0" + /* 267276 */ "VLUXSEG5EI16_V\0" + /* 267291 */ "VSUXSEG5EI16_V\0" + /* 267306 */ "VLOXSEG6EI16_V\0" + /* 267321 */ "VSOXSEG6EI16_V\0" + /* 267336 */ "VLUXSEG6EI16_V\0" + /* 267351 */ "VSUXSEG6EI16_V\0" + /* 267366 */ "VLOXSEG7EI16_V\0" + /* 267381 */ "VSOXSEG7EI16_V\0" + /* 267396 */ "VLUXSEG7EI16_V\0" + /* 267411 */ "VSUXSEG7EI16_V\0" + /* 267426 */ "VLOXSEG8EI16_V\0" + /* 267441 */ "VSOXSEG8EI16_V\0" + /* 267456 */ "VLUXSEG8EI16_V\0" + /* 267471 */ "VSUXSEG8EI16_V\0" + /* 267486 */ "VLOXEI16_V\0" + /* 267497 */ "VSOXEI16_V\0" + /* 267508 */ "VLUXEI16_V\0" + /* 267519 */ "VSUXEI16_V\0" + /* 267530 */ "VFREC7_V\0" + /* 267539 */ "VFRSQRT7_V\0" + /* 267550 */ "VLSEG2E8_V\0" + /* 267561 */ "VLSSEG2E8_V\0" + /* 267573 */ "VSSSEG2E8_V\0" + /* 267585 */ "VSSEG2E8_V\0" + /* 267596 */ "VLSEG3E8_V\0" + /* 267607 */ "VLSSEG3E8_V\0" + /* 267619 */ "VSSSEG3E8_V\0" + /* 267631 */ "VSSEG3E8_V\0" + /* 267642 */ "VLSEG4E8_V\0" + /* 267653 */ "VLSSEG4E8_V\0" + /* 267665 */ "VSSSEG4E8_V\0" + /* 267677 */ "VSSEG4E8_V\0" + /* 267688 */ "VLSEG5E8_V\0" + /* 267699 */ "VLSSEG5E8_V\0" + /* 267711 */ "VSSSEG5E8_V\0" + /* 267723 */ "VSSEG5E8_V\0" + /* 267734 */ "VLSEG6E8_V\0" + /* 267745 */ "VLSSEG6E8_V\0" + /* 267757 */ "VSSSEG6E8_V\0" + /* 267769 */ "VSSEG6E8_V\0" + /* 267780 */ "VLSEG7E8_V\0" + /* 267791 */ "VLSSEG7E8_V\0" + /* 267803 */ "VSSSEG7E8_V\0" + /* 267815 */ "VSSEG7E8_V\0" + /* 267826 */ "VLSEG8E8_V\0" + /* 267837 */ "VLSSEG8E8_V\0" + /* 267849 */ "VSSSEG8E8_V\0" + /* 267861 */ "VSSEG8E8_V\0" + /* 267872 */ "VLE8_V\0" + /* 267879 */ "VL1RE8_V\0" + /* 267888 */ "VL2RE8_V\0" + /* 267897 */ "VL4RE8_V\0" + /* 267906 */ "VL8RE8_V\0" + /* 267915 */ "VLSE8_V\0" + /* 267923 */ "VSSE8_V\0" + /* 267931 */ "VSE8_V\0" + /* 267938 */ "VLOXSEG2EI8_V\0" + /* 267952 */ "VSOXSEG2EI8_V\0" + /* 267966 */ "VLUXSEG2EI8_V\0" + /* 267980 */ "VSUXSEG2EI8_V\0" + /* 267994 */ "VLOXSEG3EI8_V\0" + /* 268008 */ "VSOXSEG3EI8_V\0" + /* 268022 */ "VLUXSEG3EI8_V\0" + /* 268036 */ "VSUXSEG3EI8_V\0" + /* 268050 */ "VLOXSEG4EI8_V\0" + /* 268064 */ "VSOXSEG4EI8_V\0" + /* 268078 */ "VLUXSEG4EI8_V\0" + /* 268092 */ "VSUXSEG4EI8_V\0" + /* 268106 */ "VLOXSEG5EI8_V\0" + /* 268120 */ "VSOXSEG5EI8_V\0" + /* 268134 */ "VLUXSEG5EI8_V\0" + /* 268148 */ "VSUXSEG5EI8_V\0" + /* 268162 */ "VLOXSEG6EI8_V\0" + /* 268176 */ "VSOXSEG6EI8_V\0" + /* 268190 */ "VLUXSEG6EI8_V\0" + /* 268204 */ "VSUXSEG6EI8_V\0" + /* 268218 */ "VLOXSEG7EI8_V\0" + /* 268232 */ "VSOXSEG7EI8_V\0" + /* 268246 */ "VLUXSEG7EI8_V\0" + /* 268260 */ "VSUXSEG7EI8_V\0" + /* 268274 */ "VLOXSEG8EI8_V\0" + /* 268288 */ "VSOXSEG8EI8_V\0" + /* 268302 */ "VLUXSEG8EI8_V\0" + /* 268316 */ "VSUXSEG8EI8_V\0" + /* 268330 */ "VLOXEI8_V\0" + /* 268340 */ "VSOXEI8_V\0" + /* 268350 */ "VLUXEI8_V\0" + /* 268360 */ "VSUXEI8_V\0" + /* 268370 */ "VID_V\0" + /* 268376 */ "VLSEG2E32FF_V\0" + /* 268390 */ "VLSEG3E32FF_V\0" + /* 268404 */ "VLSEG4E32FF_V\0" + /* 268418 */ "VLSEG5E32FF_V\0" + /* 268432 */ "VLSEG6E32FF_V\0" + /* 268446 */ "VLSEG7E32FF_V\0" + /* 268460 */ "VLSEG8E32FF_V\0" + /* 268474 */ "VLE32FF_V\0" + /* 268484 */ "VLSEG2E64FF_V\0" + /* 268498 */ "VLSEG3E64FF_V\0" + /* 268512 */ "VLSEG4E64FF_V\0" + /* 268526 */ "VLSEG5E64FF_V\0" + /* 268540 */ "VLSEG6E64FF_V\0" + /* 268554 */ "VLSEG7E64FF_V\0" + /* 268568 */ "VLSEG8E64FF_V\0" + /* 268582 */ "VLE64FF_V\0" + /* 268592 */ "VLSEG2E16FF_V\0" + /* 268606 */ "VLSEG3E16FF_V\0" + /* 268620 */ "VLSEG4E16FF_V\0" + /* 268634 */ "VLSEG5E16FF_V\0" + /* 268648 */ "VLSEG6E16FF_V\0" + /* 268662 */ "VLSEG7E16FF_V\0" + /* 268676 */ "VLSEG8E16FF_V\0" + /* 268690 */ "VLE16FF_V\0" + /* 268700 */ "VLSEG2E8FF_V\0" + /* 268713 */ "VLSEG3E8FF_V\0" + /* 268726 */ "VLSEG4E8FF_V\0" + /* 268739 */ "VLSEG5E8FF_V\0" + /* 268752 */ "VLSEG6E8FF_V\0" + /* 268765 */ "VLSEG7E8FF_V\0" + /* 268778 */ "VLSEG8E8FF_V\0" + /* 268791 */ "VLE8FF_V\0" + /* 268800 */ "VFWCVT_F_F_V\0" + /* 268813 */ "VFCVT_XU_F_V\0" + /* 268826 */ "VFWCVT_XU_F_V\0" + /* 268840 */ "VFCVT_RTZ_XU_F_V\0" + /* 268857 */ "VFWCVT_RTZ_XU_F_V\0" + /* 268875 */ "VFCVT_X_F_V\0" + /* 268887 */ "VFWCVT_X_F_V\0" + /* 268900 */ "VFCVT_RTZ_X_F_V\0" + /* 268916 */ "VFWCVT_RTZ_X_F_V\0" + /* 268933 */ "VLM_V\0" + /* 268939 */ "VSM_V\0" + /* 268945 */ "VS1R_V\0" + /* 268952 */ "PseudoVMV1R_V\0" + /* 268966 */ "VS2R_V\0" + /* 268973 */ "PseudoVMV2R_V\0" + /* 268987 */ "VS4R_V\0" + /* 268994 */ "PseudoVMV4R_V\0" + /* 269008 */ "VS8R_V\0" + /* 269015 */ "PseudoVMV8R_V\0" + /* 269029 */ "VFCLASS_V\0" + /* 269039 */ "VFSQRT_V\0" + /* 269048 */ "VFCVT_F_XU_V\0" + /* 269061 */ "VFWCVT_F_XU_V\0" + /* 269075 */ "VMV_V_V\0" + /* 269083 */ "VFCVT_F_X_V\0" + /* 269095 */ "VFWCVT_F_X_V\0" + /* 269108 */ "CRC32W\0" + /* 269115 */ "SRAW\0" + /* 269120 */ "C_SUBW\0" + /* 269127 */ "CRC32CW\0" + /* 269135 */ "GORCW\0" + /* 269141 */ "C_ADDW\0" + /* 269148 */ "SRAIW\0" + /* 269154 */ "GORCIW\0" + /* 269161 */ "C_ADDIW\0" + /* 269169 */ "SLLIW\0" + /* 269175 */ "SRLIW\0" + /* 269181 */ "RORIW\0" + /* 269187 */ "FSRIW\0" + /* 269193 */ "GREVIW\0" + /* 269200 */ "PACKW\0" + /* 269206 */ "UNSHFLW\0" + /* 269214 */ "C_FLW\0" + /* 269220 */ "PseudoFLW\0" + /* 269230 */ "SLLW\0" + /* 269235 */ "ROLW\0" + /* 269240 */ "SRLW\0" + /* 269245 */ "FSLW\0" + /* 269250 */ "MULW\0" + /* 269255 */ "C_LW\0" + /* 269260 */ "PseudoLW\0" + /* 269269 */ "REMW\0" + /* 269274 */ "XPERMW\0" + /* 269281 */ "G_FPOW\0" + /* 269288 */ "BFPW\0" + /* 269293 */ "CPOPW\0" + /* 269299 */ "RORW\0" + /* 269304 */ "CSRRW\0" + /* 269310 */ "FSRW\0" + /* 269315 */ "C_FSW\0" + /* 269321 */ "PseudoFSW\0" + /* 269331 */ "BCOMPRESSW\0" + /* 269342 */ "BDECOMPRESSW\0" + /* 269355 */ "C_SW\0" + /* 269360 */ "PseudoSW\0" + /* 269369 */ "SH1ADDUW\0" + /* 269378 */ "SH2ADDUW\0" + /* 269387 */ "SH3ADDUW\0" + /* 269396 */ "SLLIUW\0" + /* 269403 */ "PACKUW\0" + /* 269410 */ "REMUW\0" + /* 269416 */ "DIVUW\0" + /* 269422 */ "GREVW\0" + /* 269428 */ "DIVW\0" + /* 269433 */ "CLZW\0" + /* 269438 */ "CTZW\0" + /* 269443 */ "SC_W\0" + /* 269448 */ "AMOADD_W\0" + /* 269457 */ "AMOAND_W\0" + /* 269466 */ "FCVT_D_W\0" + /* 269475 */ "VFNCVT_ROD_F_F_W\0" + /* 269492 */ "VFNCVT_F_F_W\0" + /* 269505 */ "VFNCVT_XU_F_W\0" + /* 269519 */ "VFNCVT_RTZ_XU_F_W\0" + /* 269537 */ "VFNCVT_X_F_W\0" + /* 269550 */ "VFNCVT_RTZ_X_F_W\0" + /* 269567 */ "FCVT_H_W\0" + /* 269576 */ "AMOMIN_W\0" + /* 269585 */ "AMOSWAP_W\0" + /* 269595 */ "LR_W\0" + /* 269600 */ "AMOOR_W\0" + /* 269608 */ "AMOXOR_W\0" + /* 269617 */ "FCVT_S_W\0" + /* 269626 */ "PseudoZEXT_W\0" + /* 269639 */ "AMOMINU_W\0" + /* 269649 */ "AMOMAXU_W\0" + /* 269659 */ "VFNCVT_F_XU_W\0" + /* 269673 */ "AMOMAX_W\0" + /* 269682 */ "VFNCVT_F_X_W\0" + /* 269695 */ "FMV_X_W\0" + /* 269703 */ "G_VECREDUCE_FMAX\0" + /* 269720 */ "G_VECREDUCE_SMAX\0" + /* 269737 */ "G_SMAX\0" + /* 269744 */ "G_VECREDUCE_UMAX\0" + /* 269761 */ "G_UMAX\0" + /* 269768 */ "G_ATOMICRMW_UMAX\0" + /* 269785 */ "G_ATOMICRMW_MAX\0" + /* 269801 */ "G_FRAME_INDEX\0" + /* 269815 */ "G_SBFX\0" + /* 269822 */ "G_UBFX\0" + /* 269829 */ "G_SMULFIX\0" + /* 269839 */ "G_UMULFIX\0" + /* 269849 */ "G_SDIVFIX\0" + /* 269859 */ "G_UDIVFIX\0" + /* 269869 */ "CMIX\0" + /* 269874 */ "VSSRA_VX\0" + /* 269883 */ "VSRA_VX\0" + /* 269891 */ "VASUB_VX\0" + /* 269900 */ "VNMSUB_VX\0" + /* 269910 */ "VRSUB_VX\0" + /* 269919 */ "VSSUB_VX\0" + /* 269928 */ "VSUB_VX\0" + /* 269936 */ "VWSUB_VX\0" + /* 269945 */ "VNMSAC_VX\0" + /* 269955 */ "VMSBC_VX\0" + /* 269964 */ "VMACC_VX\0" + /* 269973 */ "VWMACC_VX\0" + /* 269983 */ "VMADC_VX\0" + /* 269992 */ "VAADD_VX\0" + /* 270001 */ "VMADD_VX\0" + /* 270010 */ "VSADD_VX\0" + /* 270019 */ "VADD_VX\0" + /* 270027 */ "VWADD_VX\0" + /* 270036 */ "VAND_VX\0" + /* 270044 */ "PseudoVMSGE_VX\0" + /* 270059 */ "VMSLE_VX\0" + /* 270068 */ "VMSNE_VX\0" + /* 270077 */ "VMULH_VX\0" + /* 270086 */ "VSLL_VX\0" + /* 270094 */ "VSSRL_VX\0" + /* 270103 */ "VSRL_VX\0" + /* 270111 */ "VSMUL_VX\0" + /* 270120 */ "VMUL_VX\0" + /* 270128 */ "VWMUL_VX\0" + /* 270137 */ "VREM_VX\0" + /* 270145 */ "VMIN_VX\0" + /* 270153 */ "VSLIDE1DOWN_VX\0" + /* 270168 */ "VSLIDEDOWN_VX\0" + /* 270182 */ "VSLIDE1UP_VX\0" + /* 270195 */ "VSLIDEUP_VX\0" + /* 270207 */ "VMSEQ_VX\0" + /* 270216 */ "VRGATHER_VX\0" + /* 270228 */ "VOR_VX\0" + /* 270235 */ "VXOR_VX\0" + /* 270243 */ "VWMACCUS_VX\0" + /* 270255 */ "VMSGT_VX\0" + /* 270264 */ "VMSLT_VX\0" + /* 270273 */ "VASUBU_VX\0" + /* 270283 */ "VSSUBU_VX\0" + /* 270293 */ "VWSUBU_VX\0" + /* 270303 */ "VWMACCU_VX\0" + /* 270314 */ "VAADDU_VX\0" + /* 270324 */ "VSADDU_VX\0" + /* 270334 */ "VWADDU_VX\0" + /* 270344 */ "PseudoVMSGEU_VX\0" + /* 270360 */ "VMSLEU_VX\0" + /* 270370 */ "VMULHU_VX\0" + /* 270380 */ "VWMULU_VX\0" + /* 270390 */ "VREMU_VX\0" + /* 270399 */ "VMINU_VX\0" + /* 270408 */ "VWMACCSU_VX\0" + /* 270420 */ "VMULHSU_VX\0" + /* 270431 */ "VWMULSU_VX\0" + /* 270442 */ "VMSGTU_VX\0" + /* 270452 */ "VMSLTU_VX\0" + /* 270462 */ "VDIVU_VX\0" + /* 270471 */ "VMAXU_VX\0" + /* 270480 */ "VDIV_VX\0" + /* 270488 */ "VMAX_VX\0" + /* 270496 */ "VNSRA_WX\0" + /* 270505 */ "VWSUB_WX\0" + /* 270514 */ "VWADD_WX\0" + /* 270523 */ "VNSRL_WX\0" + /* 270532 */ "VNCLIP_WX\0" + /* 270542 */ "VWSUBU_WX\0" + /* 270552 */ "VWADDU_WX\0" + /* 270562 */ "VNCLIPU_WX\0" + /* 270573 */ "FMV_D_X\0" + /* 270581 */ "FMV_H_X\0" + /* 270589 */ "VMV_S_X\0" + /* 270597 */ "VMV_V_X\0" + /* 270605 */ "FMV_W_X\0" + /* 270613 */ "G_MEMCPY\0" + /* 270622 */ "COPY\0" + /* 270627 */ "C_BNEZ\0" + /* 270634 */ "CLZ\0" + /* 270638 */ "G_CTLZ\0" + /* 270645 */ "C_BEQZ\0" + /* 270652 */ "CTZ\0" + /* 270656 */ "G_CTTZ\0" + /* 270663 */ "ReadCycleWide\0" + /* 270677 */ "PseudoCALLReg\0" + /* 270691 */ "PseudoAddTPRel\0" + /* 270706 */ "InsnI_Mem\0" + /* 270716 */ "WriteFRMImm\0" + /* 270728 */ "BuildPairF64Pseudo\0" + /* 270747 */ "SplitF64Pseudo\0" + /* 270762 */ "PseudoJump\0" + /* 270773 */ "PseudoTAILIndirect\0" + /* 270792 */ "PseudoCALLIndirect\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern const unsigned RISCVInstrNameIndices[] = { + 124494U, 261031U, 262062U, 261429U, 259929U, 259910U, 259938U, 260111U, + 124008U, 124023U, 123586U, 124050U, 262573U, 123488U, 263645U, 123599U, + 124490U, 259919U, 123319U, 270622U, 123411U, 263571U, 121708U, 123270U, + 123307U, 261564U, 260088U, 263500U, 121779U, 261775U, 124113U, 263489U, + 123438U, 261677U, 261664U, 262097U, 263241U, 263279U, 260020U, 260067U, + 260040U, 259955U, 263680U, 263710U, 119649U, 119282U, 260790U, 263945U, + 263952U, 260864U, 260871U, 260878U, 260888U, 121686U, 262348U, 262306U, + 123584U, 124492U, 269801U, 123498U, 263189U, 262511U, 263586U, 262528U, + 262244U, 119371U, 262550U, 263511U, 262481U, 263618U, 123523U, 119345U, + 121761U, 263530U, 261283U, 262122U, 119515U, 119459U, 119489U, 119500U, + 119440U, 119470U, 123467U, 123451U, 262590U, 124064U, 124081U, 119665U, + 119288U, 121692U, 121647U, 262353U, 262312U, 269785U, 261399U, 269768U, + 261382U, 119610U, 119259U, 123299U, 121733U, 263208U, 119323U, 262642U, + 263694U, 119363U, 263371U, 263359U, 263561U, 124105U, 263673U, 124037U, + 263703U, 259989U, 262188U, 262174U, 259982U, 262181U, 262474U, 260702U, + 261619U, 261612U, 263199U, 261501U, 123340U, 261485U, 123291U, 261493U, + 123332U, 261477U, 123283U, 261517U, 261509U, 124176U, 124168U, 263107U, + 263097U, 263087U, 263077U, 263127U, 263117U, 269829U, 269839U, 263137U, + 263150U, 269849U, 269859U, 263163U, 263176U, 119568U, 119238U, 260726U, + 119137U, 119433U, 263924U, 260843U, 269281U, 124910U, 261794U, 67655U, + 124098U, 50444U, 0U, 124001U, 263665U, 119335U, 124584U, 124623U, + 261585U, 261594U, 262498U, 261305U, 123532U, 261063U, 261073U, 123348U, + 123363U, 261041U, 261052U, 119655U, 125010U, 261351U, 269737U, 261375U, + 269761U, 262505U, 121752U, 121742U, 262057U, 263303U, 263335U, 263314U, + 262259U, 270656U, 123566U, 270638U, 123548U, 261656U, 261573U, 123475U, + 260006U, 262543U, 261415U, 263595U, 262224U, 263522U, 263548U, 263628U, + 262084U, 123398U, 119392U, 119596U, 119245U, 260754U, 263931U, 260850U, + 119143U, 263603U, 262141U, 262157U, 270613U, 123422U, 123513U, 263270U, + 261525U, 119575U, 260733U, 119551U, 260709U, 269703U, 261317U, 119633U, + 260774U, 121670U, 262333U, 262290U, 269720U, 261334U, 269744U, 261358U, + 269815U, 269822U, 261460U, 261760U, 270728U, 270691U, 27176U, 67843U, + 262075U, 121721U, 260100U, 270792U, 270677U, 27221U, 67866U, 121623U, + 124151U, 269220U, 121802U, 124200U, 269321U, 270762U, 119128U, 121601U, + 123382U, 119191U, 263763U, 121638U, 124184U, 263784U, 124554U, 119118U, + 269260U, 263868U, 27119U, 27348U, 27266U, 27147U, 27091U, 27319U, + 27237U, 27294U, 27199U, 263255U, 260803U, 119207U, 119223U, 121817U, + 119304U, 124366U, 124210U, 269360U, 259995U, 270773U, 21068U, 148961U, + 63536U, 197343U, 94848U, 232770U, 117275U, 257673U, 45185U, 176210U, + 81624U, 217661U, 107884U, 247152U, 26409U, 155539U, 67153U, 201797U, + 97603U, 236162U, 118844U, 259599U, 49895U, 181954U, 85442U, 222313U, + 110810U, 250712U, 20360U, 148058U, 62828U, 196440U, 94140U, 231867U, + 116680U, 256913U, 44438U, 175268U, 80877U, 216719U, 107137U, 246210U, + 25814U, 154784U, 66558U, 201042U, 97008U, 235407U, 118345U, 258965U, + 49268U, 181167U, 84815U, 221526U, 110183U, 249925U, 19083U, 61551U, + 92863U, 115541U, 43095U, 79534U, 105794U, 19323U, 61791U, 93103U, + 115781U, 43348U, 79787U, 106047U, 19439U, 61907U, 93219U, 115897U, + 43470U, 79909U, 106169U, 18574U, 146600U, 61042U, 194982U, 92354U, + 230409U, 115107U, 255723U, 42576U, 173750U, 79015U, 215201U, 105275U, + 244692U, 20471U, 148199U, 62939U, 196581U, 94251U, 232008U, 116791U, + 257054U, 44555U, 175415U, 80994U, 216866U, 107254U, 246357U, 25868U, + 154853U, 66612U, 201111U, 97062U, 235476U, 118399U, 259034U, 49325U, + 181239U, 84872U, 221598U, 110240U, 249997U, 27780U, 156658U, 68032U, + 202617U, 8083U, 134449U, 34621U, 164670U, 13347U, 140598U, 57230U, + 190490U, 59595U, 193295U, 91375U, 229275U, 71183U, 206302U, 190U, + 125131U, 27526U, 156359U, 7838U, 134159U, 53684U, 186369U, 56985U, + 190200U, 88976U, 226426U, 91130U, 228985U, 114119U, 254575U, 31566U, + 161093U, 435U, 125421U, 50452U, 182572U, 53929U, 186659U, 87462U, + 224637U, 89221U, 226716U, 112925U, 253166U, 114364U, 254865U, 4892U, + 130690U, 68286U, 202916U, 98421U, 236982U, 34875U, 164969U, 73358U, + 208839U, 13592U, 140888U, 39485U, 170303U, 17384U, 145220U, 59840U, + 193585U, 100409U, 239294U, 27808U, 156691U, 68060U, 202650U, 8110U, + 134481U, 34649U, 164703U, 13374U, 140630U, 57257U, 190522U, 59622U, + 193327U, 91402U, 229307U, 71212U, 206336U, 217U, 125163U, 27554U, + 156392U, 7865U, 134191U, 53711U, 186401U, 57012U, 190232U, 89003U, + 226458U, 91157U, 229017U, 114146U, 254607U, 31595U, 161127U, 462U, + 125453U, 50479U, 182604U, 53956U, 186691U, 87489U, 224669U, 89248U, + 226748U, 112952U, 253198U, 114391U, 254897U, 4920U, 130723U, 68313U, + 202948U, 98448U, 237014U, 34902U, 165001U, 73385U, 208871U, 13618U, + 140919U, 39512U, 170335U, 17410U, 145251U, 59866U, 193616U, 100437U, + 239327U, 28006U, 156924U, 68258U, 202883U, 8301U, 134707U, 34847U, + 164936U, 13565U, 140856U, 57448U, 190748U, 59813U, 193553U, 91593U, + 229533U, 71417U, 206576U, 408U, 125389U, 27752U, 156625U, 8056U, + 134417U, 53902U, 186627U, 57203U, 190458U, 89194U, 226684U, 91348U, + 229243U, 114337U, 254833U, 31800U, 161367U, 653U, 125679U, 50670U, + 182830U, 54147U, 186917U, 87680U, 224895U, 89439U, 226974U, 113143U, + 253424U, 114582U, 255123U, 5118U, 130956U, 68504U, 203174U, 98639U, + 237240U, 35093U, 165227U, 73576U, 209097U, 13802U, 141138U, 39703U, + 170561U, 17594U, 145470U, 60050U, 193835U, 100635U, 239560U, 27977U, + 156890U, 68229U, 202849U, 8273U, 134674U, 34818U, 164902U, 13537U, + 140823U, 57420U, 190715U, 59785U, 193520U, 91565U, 229500U, 71387U, + 206541U, 380U, 125356U, 27723U, 156591U, 8028U, 134384U, 53874U, + 186594U, 57175U, 190425U, 89166U, 226651U, 91320U, 229210U, 114309U, + 254800U, 31770U, 161332U, 625U, 125646U, 50642U, 182797U, 54119U, + 186884U, 87652U, 224862U, 89411U, 226941U, 113115U, 253391U, 114554U, + 255090U, 5089U, 130922U, 68476U, 203141U, 98611U, 237207U, 35065U, + 165194U, 73548U, 209064U, 13775U, 141106U, 39675U, 170528U, 17567U, + 145438U, 60023U, 193803U, 100606U, 239526U, 27836U, 156724U, 68088U, + 202683U, 8137U, 134513U, 34677U, 164736U, 13401U, 140662U, 57284U, + 190554U, 59649U, 193359U, 91429U, 229339U, 71241U, 206370U, 244U, + 125195U, 27582U, 156425U, 7892U, 134223U, 53738U, 186433U, 57039U, + 190264U, 89030U, 226490U, 91184U, 229049U, 114173U, 254639U, 31624U, + 161161U, 489U, 125485U, 50506U, 182636U, 53983U, 186723U, 87516U, + 224701U, 89275U, 226780U, 112979U, 253230U, 114418U, 254929U, 4948U, + 130756U, 68340U, 202980U, 98475U, 237046U, 34929U, 165033U, 73412U, + 208903U, 13644U, 140950U, 39539U, 170367U, 17436U, 145282U, 59892U, + 193647U, 100465U, 239360U, 27948U, 156856U, 68200U, 202815U, 8245U, + 134641U, 34789U, 164868U, 13509U, 140790U, 57392U, 190682U, 59757U, + 193487U, 91537U, 229467U, 71357U, 206506U, 352U, 125323U, 27694U, + 156557U, 8000U, 134351U, 53846U, 186561U, 57147U, 190392U, 89138U, + 226618U, 91292U, 229177U, 114281U, 254767U, 31740U, 161297U, 597U, + 125613U, 50614U, 182764U, 54091U, 186851U, 87624U, 224829U, 89383U, + 226908U, 113087U, 253358U, 114526U, 255057U, 5060U, 130888U, 68448U, + 203108U, 98583U, 237174U, 35037U, 165161U, 73520U, 209031U, 13748U, + 141074U, 39647U, 170495U, 17540U, 145406U, 59996U, 193771U, 100577U, + 239492U, 27893U, 156791U, 68145U, 202750U, 8192U, 134578U, 34734U, + 164803U, 13456U, 140727U, 57339U, 190619U, 59704U, 193424U, 91484U, + 229404U, 71300U, 206439U, 299U, 125260U, 27639U, 156492U, 7947U, + 134288U, 53793U, 186498U, 57094U, 190329U, 89085U, 226555U, 91239U, + 229114U, 114228U, 254704U, 31683U, 161230U, 544U, 125550U, 50561U, + 182701U, 54038U, 186788U, 87571U, 224766U, 89330U, 226845U, 113034U, + 253295U, 114473U, 254994U, 5005U, 130823U, 68395U, 203045U, 98530U, + 237111U, 34984U, 165098U, 73467U, 208968U, 13697U, 141013U, 39594U, + 170432U, 17489U, 145345U, 59945U, 193710U, 100522U, 239427U, 27864U, + 156757U, 68116U, 202716U, 8164U, 134545U, 34705U, 164769U, 13428U, + 140694U, 57311U, 190586U, 59676U, 193391U, 91456U, 229371U, 71270U, + 206404U, 271U, 125227U, 27610U, 156458U, 7919U, 134255U, 53765U, + 186465U, 57066U, 190296U, 89057U, 226522U, 91211U, 229081U, 114200U, + 254671U, 31653U, 161195U, 516U, 125517U, 50533U, 182668U, 54010U, + 186755U, 87543U, 224733U, 89302U, 226812U, 113006U, 253262U, 114445U, + 254961U, 4976U, 130789U, 68367U, 203012U, 98502U, 237078U, 34956U, + 165065U, 73439U, 208935U, 13670U, 140981U, 39566U, 170399U, 17462U, + 145313U, 59918U, 193678U, 100493U, 239393U, 27920U, 156823U, 68172U, + 202782U, 8218U, 134609U, 34761U, 164835U, 13482U, 140758U, 57365U, + 190650U, 59730U, 193455U, 91510U, 229435U, 71328U, 206472U, 325U, + 125291U, 27666U, 156524U, 7973U, 134319U, 53819U, 186529U, 57120U, + 190360U, 89111U, 226586U, 91265U, 229145U, 114254U, 254735U, 31711U, + 161263U, 570U, 125581U, 50587U, 182732U, 54064U, 186819U, 87597U, + 224797U, 89356U, 226876U, 113060U, 253326U, 114499U, 255025U, 5032U, + 130855U, 68421U, 203076U, 98556U, 237142U, 35010U, 165129U, 73493U, + 208999U, 13722U, 141043U, 39620U, 170463U, 17514U, 145375U, 59970U, + 193740U, 100549U, 239459U, 18591U, 146622U, 61059U, 195004U, 92371U, + 230431U, 115124U, 255745U, 42594U, 173773U, 79033U, 215224U, 105293U, + 244715U, 20525U, 148268U, 62993U, 196650U, 94305U, 232077U, 116808U, + 257076U, 44612U, 175487U, 81051U, 216938U, 107311U, 246429U, 25903U, + 154898U, 66647U, 201156U, 97097U, 235521U, 118416U, 259056U, 49362U, + 181286U, 84909U, 221645U, 110277U, 250044U, 20991U, 148864U, 63459U, + 197246U, 94771U, 232673U, 117237U, 257625U, 45104U, 176109U, 81543U, + 217560U, 107803U, 247051U, 26332U, 155442U, 67076U, 201700U, 97526U, + 236065U, 118806U, 259551U, 49814U, 181853U, 85361U, 222212U, 110729U, + 250611U, 19942U, 147576U, 62410U, 195958U, 93722U, 231385U, 116400U, + 256604U, 43998U, 174766U, 80437U, 216217U, 106697U, 245708U, 25614U, + 154575U, 66358U, 200833U, 96808U, 235198U, 118182U, 258803U, 49057U, + 180949U, 84604U, 221308U, 109972U, 249707U, 19361U, 61829U, 93141U, + 115819U, 43388U, 79827U, 106087U, 91U, 98166U, 236824U, 125086U, + 27427U, 156314U, 26965U, 156201U, 67933U, 202572U, 67717U, 202459U, + 98322U, 236937U, 21298U, 149251U, 63766U, 197633U, 95078U, 233060U, + 117426U, 257864U, 45427U, 176512U, 81866U, 217963U, 108126U, 247454U, + 26658U, 155853U, 67402U, 202111U, 97852U, 236476U, 119014U, 259814U, + 50157U, 182281U, 85704U, 222640U, 111072U, 251039U, 21352U, 149320U, + 63820U, 197702U, 95132U, 233129U, 117480U, 257933U, 45484U, 176584U, + 81923U, 218035U, 108183U, 247526U, 26694U, 155899U, 67438U, 202157U, + 97888U, 236522U, 119050U, 259860U, 50195U, 182329U, 85742U, 222688U, + 111110U, 251087U, 15868U, 143564U, 59032U, 192647U, 90567U, 228337U, + 113640U, 254031U, 40941U, 171992U, 77350U, 213408U, 103610U, 242899U, + 4349U, 130090U, 52238U, 184713U, 86664U, 223749U, 111617U, 251648U, + 30997U, 160470U, 70614U, 205679U, 99840U, 238671U, 11105U, 138006U, + 56055U, 189160U, 88497U, 225882U, 112446U, 252622U, 37124U, 167591U, + 74698U, 210387U, 101838U, 240918U, 20378U, 148081U, 62846U, 196463U, + 94158U, 231890U, 116698U, 256936U, 44457U, 175292U, 80896U, 216743U, + 107156U, 246234U, 25246U, 154144U, 65990U, 200402U, 96440U, 234767U, + 118050U, 258658U, 48672U, 180502U, 84219U, 220861U, 109587U, 249260U, + 25283U, 154191U, 66027U, 200449U, 96477U, 234814U, 118087U, 258705U, + 48711U, 180551U, 84258U, 220910U, 109626U, 249309U, 25345U, 154246U, + 66089U, 200504U, 96539U, 234869U, 118126U, 258732U, 48776U, 180608U, + 84323U, 220967U, 109691U, 249366U, 25099U, 153967U, 65843U, 200225U, + 96293U, 234590U, 117978U, 258571U, 48519U, 180319U, 84066U, 220678U, + 109434U, 249077U, 25195U, 154083U, 65939U, 200341U, 96389U, 234706U, + 118025U, 258628U, 48619U, 180439U, 84166U, 220798U, 109534U, 249197U, + 25054U, 153912U, 65798U, 200170U, 96248U, 234535U, 117956U, 258544U, + 48472U, 180262U, 84019U, 220621U, 109387U, 249020U, 25152U, 154030U, + 65896U, 200288U, 96346U, 234653U, 118004U, 258602U, 48574U, 180384U, + 84121U, 220743U, 109489U, 249142U, 16228U, 144009U, 59392U, 193092U, + 90927U, 228782U, 113958U, 254424U, 41318U, 172454U, 77727U, 213870U, + 103987U, 243361U, 4709U, 130535U, 52598U, 185158U, 87024U, 224194U, + 111935U, 252041U, 31374U, 160932U, 70991U, 206141U, 100217U, 239133U, + 11423U, 138399U, 56373U, 189553U, 88815U, 226275U, 112764U, 253015U, + 37457U, 167999U, 75031U, 210795U, 102171U, 241326U, 21334U, 149297U, + 63802U, 197679U, 95114U, 233106U, 117462U, 257910U, 45465U, 176560U, + 81904U, 218011U, 108164U, 247502U, 142U, 98220U, 236847U, 125108U, + 27478U, 156336U, 27019U, 156224U, 67984U, 202594U, 67771U, 202482U, + 98373U, 236959U, 15780U, 143456U, 58944U, 192539U, 90479U, 228229U, + 113597U, 253978U, 40849U, 171880U, 77258U, 213296U, 103518U, 242787U, + 4261U, 129982U, 52150U, 184605U, 86576U, 223641U, 111574U, 251595U, + 30905U, 160358U, 70522U, 205567U, 99748U, 238559U, 11062U, 137953U, + 56012U, 189107U, 88454U, 225829U, 112403U, 252569U, 37079U, 167536U, + 74653U, 210332U, 101793U, 240863U, 20225U, 147911U, 62693U, 196293U, + 94005U, 231720U, 116605U, 256841U, 44296U, 175115U, 80735U, 216566U, + 106995U, 246057U, 15888U, 143589U, 59052U, 192672U, 90587U, 228362U, + 113660U, 254056U, 40962U, 172018U, 77371U, 213434U, 103631U, 242925U, + 4369U, 130115U, 52258U, 184738U, 86684U, 223774U, 111637U, 251673U, + 31018U, 160496U, 70635U, 205705U, 99861U, 238697U, 11125U, 138031U, + 56075U, 189185U, 88517U, 225907U, 112466U, 252647U, 37145U, 167617U, + 74719U, 210413U, 101859U, 240944U, 20396U, 148104U, 62864U, 196486U, + 94176U, 231913U, 116716U, 256959U, 44476U, 175316U, 80915U, 216767U, + 107175U, 246258U, 16269U, 144060U, 59433U, 193143U, 90968U, 228833U, + 113999U, 254475U, 41361U, 172507U, 77770U, 213923U, 104030U, 243414U, + 4750U, 130586U, 52639U, 185209U, 87065U, 224245U, 111976U, 252092U, + 31417U, 160985U, 71034U, 206194U, 100260U, 239186U, 11464U, 138450U, + 56414U, 189604U, 88856U, 226326U, 112805U, 253066U, 37500U, 168052U, + 75074U, 210848U, 102214U, 241379U, 21369U, 149342U, 63837U, 197724U, + 95149U, 233151U, 117497U, 257955U, 45502U, 176607U, 81941U, 218058U, + 108201U, 247549U, 19041U, 61509U, 92821U, 115499U, 43051U, 79490U, + 105750U, 18995U, 61463U, 92775U, 115453U, 43003U, 79442U, 105702U, + 19018U, 61486U, 92798U, 115476U, 43027U, 79466U, 105726U, 16074U, + 143820U, 59238U, 192903U, 90773U, 228593U, 113804U, 254235U, 41157U, + 172258U, 77566U, 213674U, 103826U, 243165U, 4555U, 130346U, 52444U, + 184969U, 86870U, 224005U, 111781U, 251852U, 31213U, 160736U, 70830U, + 205945U, 100056U, 238937U, 11269U, 138210U, 56219U, 189364U, 88661U, + 226086U, 112610U, 252826U, 37296U, 167803U, 74870U, 210599U, 102010U, + 241130U, 20810U, 148633U, 63278U, 197015U, 94590U, 232442U, 117056U, + 257394U, 44913U, 175868U, 81352U, 217319U, 107612U, 246810U, 15692U, + 143348U, 58856U, 192431U, 90391U, 228121U, 113554U, 253925U, 40757U, + 171768U, 77166U, 213184U, 103426U, 242675U, 4173U, 129874U, 52062U, + 184497U, 86488U, 223533U, 111531U, 251542U, 30813U, 160246U, 70430U, + 205455U, 99656U, 238447U, 11019U, 137900U, 55969U, 189054U, 88411U, + 225776U, 112360U, 252516U, 37034U, 167481U, 74608U, 210277U, 101748U, + 240808U, 20108U, 147787U, 62576U, 196169U, 93888U, 231596U, 116529U, + 256768U, 44173U, 174986U, 80612U, 216437U, 106872U, 245928U, 15607U, + 143243U, 58771U, 192326U, 90306U, 228016U, 113490U, 253846U, 40668U, + 171659U, 77077U, 213075U, 103337U, 242566U, 4088U, 129769U, 51977U, + 184392U, 86403U, 223428U, 111467U, 251463U, 30724U, 160137U, 70341U, + 205346U, 99567U, 238338U, 10955U, 137821U, 55905U, 188975U, 88347U, + 225697U, 112296U, 252437U, 36967U, 167399U, 74541U, 210195U, 101681U, + 240726U, 19978U, 147622U, 62446U, 196004U, 93758U, 231431U, 116436U, + 256650U, 44036U, 174814U, 80475U, 216265U, 106735U, 245756U, 16033U, + 143769U, 59197U, 192852U, 90732U, 228542U, 113784U, 254210U, 41114U, + 172205U, 77523U, 213621U, 103783U, 243112U, 4514U, 130295U, 52403U, + 184918U, 86829U, 223954U, 111761U, 251827U, 31170U, 160683U, 70787U, + 205892U, 100013U, 238884U, 11249U, 138185U, 56199U, 189339U, 88641U, + 226061U, 112590U, 252801U, 37275U, 167777U, 74849U, 210573U, 101989U, + 241104U, 20703U, 148496U, 63171U, 196878U, 94483U, 232305U, 116986U, + 257304U, 44800U, 175725U, 81239U, 217176U, 107499U, 246667U, 19870U, + 62338U, 93650U, 116328U, 43922U, 80361U, 106621U, 19830U, 62298U, + 93610U, 116288U, 43880U, 80319U, 106579U, 19850U, 62318U, 93630U, + 116308U, 43901U, 80340U, 106600U, 16353U, 59517U, 91052U, 114041U, + 41449U, 77858U, 104118U, 4834U, 52723U, 87149U, 112018U, 31505U, + 71122U, 100348U, 11506U, 56456U, 88898U, 112847U, 37544U, 75118U, + 102258U, 16373U, 59537U, 91072U, 114061U, 41470U, 77879U, 104139U, + 4854U, 52743U, 87169U, 112038U, 31526U, 71143U, 100369U, 11526U, + 56476U, 88918U, 112867U, 37565U, 75139U, 102279U, 25414U, 154330U, + 66158U, 200588U, 96608U, 234953U, 48848U, 180695U, 84395U, 221054U, + 109763U, 249453U, 25534U, 154475U, 66278U, 200733U, 96728U, 235098U, + 48973U, 180845U, 84520U, 221204U, 109888U, 249603U, 25557U, 154503U, + 66301U, 200761U, 96751U, 235126U, 48997U, 180874U, 84544U, 221233U, + 109912U, 249632U, 25388U, 154299U, 66132U, 200557U, 96582U, 234922U, + 48821U, 180663U, 84368U, 221022U, 109736U, 249421U, 25459U, 154385U, + 66203U, 200643U, 96653U, 235008U, 48895U, 180752U, 84442U, 221111U, + 109810U, 249510U, 25508U, 154444U, 66252U, 200702U, 96702U, 235067U, + 48946U, 180813U, 84493U, 221172U, 109861U, 249571U, 25436U, 154357U, + 66180U, 200615U, 96630U, 234980U, 48871U, 180723U, 84418U, 221082U, + 109786U, 249481U, 25486U, 154417U, 66230U, 200675U, 96680U, 235040U, + 48923U, 180785U, 84470U, 221144U, 109838U, 249543U, 15801U, 143482U, + 58965U, 192565U, 90500U, 228255U, 113618U, 254004U, 40871U, 171907U, + 77280U, 213323U, 103540U, 242814U, 4282U, 130008U, 52171U, 184631U, + 86597U, 223667U, 111595U, 251621U, 30927U, 160385U, 70544U, 205594U, + 99770U, 238586U, 11083U, 137979U, 56033U, 189133U, 88475U, 225855U, + 112424U, 252595U, 37101U, 167563U, 74675U, 210359U, 101815U, 240890U, + 20244U, 147935U, 62712U, 196317U, 94024U, 231744U, 116624U, 256865U, + 44316U, 175140U, 80755U, 216591U, 107015U, 246082U, 15909U, 143615U, + 59073U, 192698U, 90608U, 228388U, 113681U, 254082U, 40984U, 172045U, + 77393U, 213461U, 103653U, 242952U, 4390U, 130141U, 52279U, 184764U, + 86705U, 223800U, 111658U, 251699U, 31040U, 160523U, 70657U, 205732U, + 99883U, 238724U, 11146U, 138057U, 56096U, 189211U, 88538U, 225933U, + 112487U, 252673U, 37167U, 167644U, 74741U, 210440U, 101881U, 240971U, + 20415U, 148128U, 62883U, 196510U, 94195U, 231937U, 116735U, 256983U, + 44496U, 175341U, 80935U, 216792U, 107195U, 246283U, 15713U, 143374U, + 58877U, 192457U, 90412U, 228147U, 113575U, 253951U, 40779U, 171795U, + 77188U, 213211U, 103448U, 242702U, 4194U, 129900U, 52083U, 184523U, + 86509U, 223559U, 111552U, 251568U, 30835U, 160273U, 70452U, 205482U, + 99678U, 238474U, 11040U, 137926U, 55990U, 189080U, 88432U, 225802U, + 112381U, 252542U, 37056U, 167508U, 74630U, 210304U, 101770U, 240835U, + 20127U, 147811U, 62595U, 196193U, 93907U, 231620U, 116548U, 256792U, + 44193U, 175011U, 80632U, 216462U, 106892U, 245953U, 15628U, 143269U, + 58792U, 192352U, 90327U, 228042U, 113511U, 253872U, 40690U, 171686U, + 77099U, 213102U, 103359U, 242593U, 4109U, 129795U, 51998U, 184418U, + 86424U, 223454U, 111488U, 251489U, 30746U, 160164U, 70363U, 205373U, + 99589U, 238365U, 10976U, 137847U, 55926U, 189001U, 88368U, 225723U, + 112317U, 252463U, 36989U, 167426U, 74563U, 210222U, 101703U, 240753U, + 19997U, 147646U, 62465U, 196028U, 93777U, 231455U, 116455U, 256674U, + 44056U, 174839U, 80495U, 216290U, 106755U, 245781U, 16248U, 144034U, + 59412U, 193117U, 90947U, 228807U, 113978U, 254449U, 41339U, 172480U, + 77748U, 213896U, 104008U, 243387U, 4729U, 130560U, 52618U, 185183U, + 87044U, 224219U, 111955U, 252066U, 31395U, 160958U, 71012U, 206167U, + 100238U, 239159U, 11443U, 138424U, 56393U, 189578U, 88835U, 226300U, + 112784U, 253040U, 37478U, 168025U, 75052U, 210821U, 102192U, 241352U, + 23627U, 152145U, 65063U, 199255U, 95859U, 234046U, 117762U, 258295U, + 47165U, 178655U, 82900U, 219242U, 108456U, 247869U, 19789U, 147480U, + 62257U, 195862U, 93569U, 231289U, 116247U, 256508U, 43837U, 174666U, + 80276U, 216117U, 106536U, 245608U, 19645U, 147301U, 62113U, 195683U, + 93425U, 231110U, 116103U, 256329U, 43686U, 174480U, 80125U, 215931U, + 106385U, 245422U, 19555U, 147191U, 62023U, 195573U, 93335U, 231000U, + 116013U, 256219U, 43592U, 174366U, 80031U, 215817U, 106291U, 245308U, + 19600U, 147246U, 62068U, 195628U, 93380U, 231055U, 116058U, 256274U, + 43639U, 174423U, 80078U, 215874U, 106338U, 245365U, 23645U, 152168U, + 65081U, 199278U, 95877U, 234069U, 117780U, 258318U, 47184U, 178679U, + 82919U, 219266U, 108475U, 247893U, 15650U, 143296U, 58814U, 192379U, + 90349U, 228069U, 113533U, 253899U, 40713U, 171714U, 77122U, 213130U, + 103382U, 242621U, 4131U, 129822U, 52020U, 184445U, 86446U, 223481U, + 111510U, 251516U, 30769U, 160192U, 70386U, 205401U, 99612U, 238393U, + 10998U, 137874U, 55948U, 189028U, 88390U, 225750U, 112339U, 252490U, + 37012U, 167454U, 74586U, 210250U, 101726U, 240781U, 16094U, 143845U, + 59258U, 192928U, 90793U, 228618U, 113824U, 254260U, 41178U, 172284U, + 77587U, 213700U, 103847U, 243191U, 4575U, 130371U, 52464U, 184994U, + 86890U, 224030U, 111801U, 251877U, 31234U, 160762U, 70851U, 205971U, + 100077U, 238963U, 11289U, 138235U, 56239U, 189389U, 88681U, 226111U, + 112630U, 252851U, 37317U, 167829U, 74891U, 210625U, 102031U, 241156U, + 20845U, 148678U, 63313U, 197060U, 94625U, 232487U, 117091U, 257439U, + 44950U, 175915U, 81389U, 217366U, 107649U, 246857U, 16289U, 144085U, + 59453U, 193168U, 90988U, 228858U, 114019U, 254500U, 41382U, 172533U, + 77791U, 213949U, 104051U, 243440U, 4770U, 130611U, 52659U, 185234U, + 87085U, 224270U, 111996U, 252117U, 31438U, 161011U, 71055U, 206220U, + 100281U, 239212U, 11484U, 138475U, 56434U, 189629U, 88876U, 226351U, + 112825U, 253091U, 37521U, 168078U, 75095U, 210874U, 102235U, 241405U, + 21404U, 149387U, 63872U, 197769U, 95184U, 233196U, 117532U, 258000U, + 45539U, 176654U, 81978U, 218105U, 108238U, 247596U, 16012U, 143743U, + 59176U, 192826U, 90711U, 228516U, 113763U, 254184U, 41092U, 172178U, + 77501U, 213594U, 103761U, 243085U, 4493U, 130269U, 52382U, 184892U, + 86808U, 223928U, 111740U, 251801U, 31148U, 160656U, 70765U, 205865U, + 99991U, 238857U, 11228U, 138159U, 56178U, 189313U, 88620U, 226035U, + 112569U, 252775U, 37253U, 167750U, 74827U, 210546U, 101967U, 241077U, + 20632U, 148405U, 63100U, 196787U, 94412U, 232214U, 116915U, 257213U, + 44725U, 175630U, 81164U, 217081U, 107424U, 246572U, 16116U, 143872U, + 59280U, 192955U, 90815U, 228645U, 113846U, 254287U, 41201U, 172312U, + 77610U, 213728U, 103870U, 243219U, 4597U, 130398U, 52486U, 185021U, + 86912U, 224057U, 111823U, 251904U, 31257U, 160790U, 70874U, 205999U, + 100100U, 238991U, 11311U, 138262U, 56261U, 189416U, 88703U, 226138U, + 112652U, 252878U, 37340U, 167857U, 74914U, 210653U, 102054U, 241184U, + 16143U, 143904U, 59307U, 192987U, 90842U, 228677U, 113873U, 254319U, + 41229U, 172345U, 77638U, 213761U, 103898U, 243252U, 4624U, 130430U, + 52513U, 185053U, 86939U, 224089U, 111850U, 251936U, 31285U, 160823U, + 70902U, 206032U, 100128U, 239024U, 11338U, 138294U, 56288U, 189448U, + 88730U, 226170U, 112679U, 252910U, 37368U, 167890U, 74942U, 210686U, + 102082U, 241217U, 25265U, 154168U, 66009U, 200426U, 96459U, 234791U, + 118069U, 258682U, 48692U, 180527U, 84239U, 220886U, 109607U, 249285U, + 15587U, 143218U, 58751U, 192301U, 90286U, 227991U, 113470U, 253821U, + 40647U, 171633U, 77056U, 213049U, 103316U, 242540U, 4068U, 129744U, + 51957U, 184367U, 86383U, 223403U, 111447U, 251438U, 30703U, 160111U, + 70320U, 205320U, 99546U, 238312U, 10935U, 137796U, 55885U, 188950U, + 88327U, 225672U, 112276U, 252412U, 36946U, 167373U, 74520U, 210169U, + 101660U, 240700U, 19960U, 147599U, 62428U, 195981U, 93740U, 231408U, + 116418U, 256627U, 44017U, 174790U, 80456U, 216241U, 106716U, 245732U, + 15931U, 143642U, 59095U, 192725U, 90630U, 228415U, 41007U, 172073U, + 77416U, 213489U, 103676U, 242980U, 4412U, 130168U, 52301U, 184791U, + 86727U, 223827U, 31063U, 160551U, 70680U, 205760U, 99906U, 238752U, + 20488U, 148221U, 62956U, 196603U, 94268U, 232030U, 44573U, 175438U, + 81012U, 216889U, 107272U, 246380U, 16332U, 144138U, 59496U, 193221U, + 91031U, 228911U, 41427U, 172588U, 77836U, 214004U, 104096U, 243495U, + 4813U, 130664U, 52702U, 185287U, 87128U, 224323U, 31483U, 161066U, + 71100U, 206275U, 100326U, 239267U, 21479U, 149482U, 120608U, 119728U, + 63947U, 197864U, 120958U, 120018U, 95259U, 233291U, 121308U, 120308U, + 45618U, 176753U, 120782U, 119872U, 82057U, 218204U, 121132U, 120162U, + 108317U, 247695U, 121482U, 120452U, 25032U, 153885U, 65776U, 200143U, + 96226U, 234508U, 48449U, 180234U, 83996U, 220593U, 109364U, 248992U, + 25305U, 154218U, 66049U, 200476U, 96499U, 234841U, 48734U, 180579U, + 84281U, 220938U, 109649U, 249337U, 25366U, 154272U, 66110U, 200530U, + 96560U, 234895U, 48798U, 180635U, 84345U, 220994U, 109713U, 249393U, + 25125U, 153998U, 65869U, 200256U, 96319U, 234621U, 48546U, 180351U, + 84093U, 220710U, 109461U, 249109U, 25220U, 154113U, 65964U, 200371U, + 96414U, 234736U, 48645U, 180470U, 84192U, 220829U, 109560U, 249228U, + 25076U, 153939U, 65820U, 200197U, 96270U, 234562U, 48495U, 180290U, + 84042U, 220649U, 109410U, 249048U, 25173U, 154056U, 65917U, 200314U, + 96367U, 234679U, 48596U, 180411U, 84143U, 220770U, 109511U, 249169U, + 15846U, 143537U, 59010U, 192620U, 90545U, 228310U, 40918U, 171964U, + 77327U, 213380U, 103587U, 242871U, 4327U, 130063U, 52216U, 184686U, + 86642U, 223722U, 30974U, 160442U, 70591U, 205651U, 99817U, 238643U, + 20303U, 148009U, 62771U, 196391U, 94083U, 231818U, 44378U, 175217U, + 80817U, 216668U, 107077U, 246159U, 15758U, 143429U, 58922U, 192512U, + 90457U, 228202U, 40826U, 171852U, 77235U, 213268U, 103495U, 242759U, + 4239U, 129955U, 52128U, 184578U, 86554U, 223614U, 30882U, 160330U, + 70499U, 205539U, 99725U, 238531U, 20187U, 147886U, 62655U, 196268U, + 93967U, 231695U, 44256U, 175089U, 80695U, 216540U, 106955U, 246031U, + 16053U, 143794U, 59217U, 192877U, 90752U, 228567U, 41135U, 172231U, + 77544U, 213647U, 103804U, 243138U, 4534U, 130320U, 52423U, 184943U, + 86849U, 223979U, 31191U, 160709U, 70808U, 205918U, 100034U, 238910U, + 20756U, 148564U, 63224U, 196946U, 94536U, 232373U, 44856U, 175796U, + 81295U, 217247U, 107555U, 246738U, 15823U, 143509U, 58987U, 192592U, + 90522U, 228282U, 40894U, 171935U, 77303U, 213351U, 103563U, 242842U, + 4304U, 130035U, 52193U, 184658U, 86619U, 223694U, 30950U, 160413U, + 70567U, 205622U, 99793U, 238614U, 20264U, 147960U, 62732U, 196342U, + 94044U, 231769U, 44337U, 175166U, 80776U, 216617U, 107036U, 246108U, + 15735U, 143401U, 58899U, 192484U, 90434U, 228174U, 40802U, 171823U, + 77211U, 213239U, 103471U, 242730U, 4216U, 129927U, 52105U, 184550U, + 86531U, 223586U, 30858U, 160301U, 70475U, 205510U, 99701U, 238502U, + 20166U, 147860U, 62634U, 196242U, 93946U, 231669U, 44234U, 175062U, + 80673U, 216513U, 106933U, 246004U, 19577U, 147218U, 62045U, 195600U, + 93357U, 231027U, 116035U, 256246U, 43615U, 174394U, 80054U, 215845U, + 106314U, 245336U, 19622U, 147273U, 62090U, 195655U, 93402U, 231082U, + 116080U, 256301U, 43662U, 174451U, 80101U, 215902U, 106361U, 245393U, + 15671U, 143322U, 58835U, 192405U, 90370U, 228095U, 40735U, 171741U, + 77144U, 213157U, 103404U, 242648U, 4152U, 129848U, 52041U, 184471U, + 86467U, 223507U, 30791U, 160219U, 70408U, 205428U, 99634U, 238420U, + 20071U, 147740U, 62539U, 196122U, 93851U, 231549U, 44134U, 174937U, + 80573U, 216388U, 106833U, 245879U, 16311U, 144112U, 59475U, 193195U, + 91010U, 228885U, 41405U, 172561U, 77814U, 213977U, 104074U, 243468U, + 4792U, 130638U, 52681U, 185261U, 87107U, 224297U, 31461U, 161039U, + 71078U, 206248U, 100304U, 239240U, 21442U, 149435U, 120551U, 119681U, + 63910U, 197817U, 120901U, 119971U, 95222U, 233244U, 121251U, 120261U, + 45579U, 176704U, 120723U, 119823U, 82018U, 218155U, 121073U, 120113U, + 108278U, 247646U, 121423U, 120403U, 24305U, 152993U, 65413U, 199695U, + 96045U, 234282U, 117866U, 258429U, 47877U, 179537U, 83612U, 220124U, + 109168U, 248751U, 19477U, 147093U, 61945U, 195475U, 93257U, 230902U, + 115935U, 256121U, 43510U, 174264U, 79949U, 215715U, 106209U, 245206U, + 24841U, 153649U, 65673U, 200015U, 96167U, 234434U, 117919U, 258497U, + 48249U, 179989U, 83796U, 220348U, 23557U, 152055U, 64993U, 199165U, + 95789U, 233956U, 117692U, 258205U, 47091U, 178561U, 82826U, 219148U, + 24481U, 153209U, 65497U, 199799U, 96083U, 234330U, 117881U, 258449U, + 48061U, 179761U, 22213U, 150391U, 64337U, 198349U, 95477U, 233564U, + 117552U, 258025U, 46387U, 177697U, 24661U, 153429U, 65585U, 199907U, + 96125U, 234382U, 117900U, 258473U, 22885U, 151223U, 64665U, 198757U, + 95633U, 233760U, 117622U, 258115U, 25014U, 153862U, 65758U, 200120U, + 96208U, 234485U, 117938U, 258521U, 48430U, 180210U, 83977U, 220569U, + 109345U, 248968U, 24239U, 152907U, 65347U, 199609U, 95979U, 234196U, + 117800U, 258343U, 47807U, 179447U, 83542U, 220034U, 109098U, 248661U, + 160U, 98239U, 27496U, 27038U, 68002U, 67790U, 98391U, 3160U, + 128656U, 51465U, 183775U, 86099U, 223059U, 30607U, 159995U, 10808U, + 137684U, 55358U, 188358U, 88043U, 225328U, 112096U, 252192U, 58659U, + 192189U, 90002U, 227647U, 113290U, 253601U, 92156U, 230206U, 114821U, + 255412U, 6839U, 132987U, 53117U, 185709U, 33583U, 163460U, 73200U, + 208669U, 12348U, 139426U, 38447U, 169093U, 76021U, 211889U, 103161U, + 242420U, 1464U, 126640U, 51049U, 183279U, 28847U, 157915U, 69344U, + 204164U, 9112U, 135668U, 54526U, 187366U, 87843U, 225088U, 35933U, + 166217U, 14612U, 142098U, 57827U, 191197U, 89602U, 227167U, 113198U, + 253489U, 60428U, 194283U, 91756U, 229726U, 114637U, 255188U, 5959U, + 131947U, 32671U, 162388U, 72288U, 207597U, 101505U, 240580U, 2312U, + 127648U, 29727U, 158955U, 70224U, 205204U, 99450U, 238196U, 9960U, + 136676U, 54942U, 187862U, 36813U, 167257U, 74387U, 210053U, 15460U, + 143106U, 58243U, 191693U, 89802U, 227407U, 40514U, 171517U, 18376U, + 146397U, 60844U, 194779U, 91956U, 229966U, 114729U, 255300U, 3980U, + 129636U, 51869U, 184259U, 86295U, 223295U, 111359U, 251330U, 55762U, + 188842U, 88239U, 225564U, 112188U, 252304U, 90198U, 227883U, 113382U, + 253713U, 114913U, 255524U, 7691U, 133999U, 53537U, 186209U, 87315U, + 224477U, 34467U, 164504U, 13200U, 140438U, 56838U, 190040U, 39331U, + 170137U, 76905U, 212933U, 17237U, 145060U, 42368U, 173539U, 78807U, + 214990U, 105067U, 244481U, 2404U, 127760U, 51141U, 183391U, 85991U, + 222931U, 29823U, 159071U, 10052U, 136788U, 55034U, 187974U, 87935U, + 225200U, 58335U, 191805U, 89894U, 227519U, 92048U, 230078U, 6055U, + 132063U, 52781U, 185313U, 32771U, 162508U, 72388U, 207717U, 11564U, + 138502U, 37635U, 168141U, 75209U, 210937U, 102349U, 241468U, 708U, + 125744U, 50725U, 182895U, 28063U, 156991U, 68560U, 203240U, 8356U, + 134772U, 54202U, 186982U, 87735U, 224960U, 35149U, 165293U, 13856U, + 141202U, 57503U, 190813U, 89494U, 227039U, 60104U, 193899U, 91648U, + 229598U, 5175U, 131023U, 31859U, 161436U, 71476U, 206645U, 100693U, + 239628U, 1556U, 126752U, 28943U, 158031U, 69440U, 204280U, 98666U, + 237272U, 9204U, 135780U, 54618U, 187478U, 36029U, 166333U, 73603U, + 209129U, 14704U, 142210U, 57919U, 191309U, 89694U, 227279U, 39730U, + 170593U, 17620U, 145501U, 60520U, 194395U, 91848U, 229838U, 3252U, + 128768U, 51557U, 183887U, 86191U, 223171U, 55450U, 188470U, 88135U, + 225440U, 90094U, 227759U, 6935U, 133103U, 53213U, 185825U, 87207U, + 224349U, 33683U, 163580U, 12444U, 139542U, 56514U, 189656U, 38547U, + 169213U, 76121U, 212009U, 16481U, 144164U, 41584U, 172615U, 78023U, + 214066U, 104283U, 243557U, 2512U, 127888U, 51249U, 183519U, 29935U, + 159203U, 10160U, 136916U, 55142U, 188102U, 58443U, 191933U, 6167U, + 132195U, 52893U, 185445U, 32887U, 162644U, 72504U, 207853U, 11676U, + 138634U, 37751U, 168277U, 75325U, 211073U, 102465U, 241604U, 816U, + 125872U, 50833U, 183023U, 28175U, 157123U, 68672U, 203372U, 8464U, + 134900U, 54310U, 187110U, 35261U, 165425U, 13964U, 141330U, 57611U, + 190941U, 60212U, 194027U, 5287U, 131155U, 31975U, 161572U, 71592U, + 206781U, 100809U, 239764U, 1664U, 126880U, 29055U, 158163U, 69552U, + 204412U, 98778U, 237404U, 9312U, 135908U, 54726U, 187606U, 36141U, + 166465U, 73715U, 209261U, 14812U, 142338U, 58027U, 191437U, 39842U, + 170725U, 17728U, 145629U, 60628U, 194523U, 3356U, 128892U, 51661U, + 184011U, 55554U, 188594U, 7043U, 133231U, 53321U, 185953U, 33795U, + 163712U, 12552U, 139670U, 56622U, 189784U, 38659U, 169345U, 76233U, + 212141U, 16589U, 144292U, 41696U, 172747U, 78135U, 214198U, 104395U, + 243689U, 2620U, 128016U, 51357U, 183647U, 30047U, 159335U, 10268U, + 137044U, 55250U, 188230U, 58551U, 192061U, 6279U, 132327U, 53005U, + 185577U, 33003U, 162780U, 72620U, 207989U, 11788U, 138766U, 37867U, + 168413U, 75441U, 211209U, 102581U, 241740U, 924U, 126000U, 50941U, + 183151U, 28287U, 157255U, 68784U, 203504U, 8572U, 135028U, 54418U, + 187238U, 35373U, 165557U, 14072U, 141458U, 57719U, 191069U, 60320U, + 194155U, 5399U, 131287U, 32091U, 161708U, 71708U, 206917U, 100925U, + 239900U, 1772U, 127008U, 29167U, 158295U, 69664U, 204544U, 98890U, + 237536U, 9420U, 136036U, 54834U, 187734U, 36253U, 166597U, 73827U, + 209393U, 14920U, 142466U, 58135U, 191565U, 39954U, 170857U, 17836U, + 145757U, 60736U, 194651U, 3460U, 129016U, 51765U, 184135U, 55658U, + 188718U, 7151U, 133359U, 53429U, 186081U, 33907U, 163844U, 12660U, + 139798U, 56730U, 189912U, 38771U, 169477U, 76345U, 212273U, 16697U, + 144420U, 41808U, 172879U, 78247U, 214330U, 104507U, 243821U, 2728U, + 128144U, 30159U, 159467U, 10376U, 137172U, 6391U, 132459U, 33119U, + 162916U, 72736U, 208125U, 11900U, 138898U, 37983U, 168549U, 75557U, + 211345U, 102697U, 241876U, 1032U, 126128U, 28399U, 157387U, 68896U, + 203636U, 8680U, 135156U, 35485U, 165689U, 14180U, 141586U, 5511U, + 131419U, 32207U, 161844U, 71824U, 207053U, 101041U, 240036U, 1880U, + 127136U, 29279U, 158427U, 69776U, 204676U, 99002U, 237668U, 9528U, + 136164U, 36365U, 166729U, 73939U, 209525U, 15028U, 142594U, 40066U, + 170989U, 17944U, 145885U, 3564U, 129140U, 7259U, 133487U, 34019U, + 163976U, 12768U, 139926U, 38883U, 169609U, 76457U, 212405U, 16805U, + 144548U, 41920U, 173011U, 78359U, 214462U, 104619U, 243953U, 2836U, + 128272U, 30271U, 159599U, 10484U, 137300U, 6503U, 132591U, 33235U, + 163052U, 72852U, 208261U, 12012U, 139030U, 38099U, 168685U, 75673U, + 211481U, 102813U, 242012U, 1140U, 126256U, 28511U, 157519U, 69008U, + 203768U, 8788U, 135284U, 35597U, 165821U, 14288U, 141714U, 5623U, + 131551U, 32323U, 161980U, 71940U, 207189U, 101157U, 240172U, 1988U, + 127264U, 29391U, 158559U, 69888U, 204808U, 99114U, 237800U, 9636U, + 136292U, 36477U, 166861U, 74051U, 209657U, 15136U, 142722U, 40178U, + 171121U, 18052U, 146013U, 3668U, 129264U, 7367U, 133615U, 34131U, + 164108U, 12876U, 140054U, 38995U, 169741U, 76569U, 212537U, 16913U, + 144676U, 42032U, 173143U, 78471U, 214594U, 104731U, 244085U, 2944U, + 128400U, 30383U, 159731U, 10592U, 137428U, 6615U, 132723U, 33351U, + 163188U, 72968U, 208397U, 12124U, 139162U, 38215U, 168821U, 75789U, + 211617U, 102929U, 242148U, 1248U, 126384U, 28623U, 157651U, 69120U, + 203900U, 8896U, 135412U, 35709U, 165953U, 14396U, 141842U, 5735U, + 131683U, 32439U, 162116U, 72056U, 207325U, 101273U, 240308U, 2096U, + 127392U, 29503U, 158691U, 70000U, 204940U, 99226U, 237932U, 9744U, + 136420U, 36589U, 166993U, 74163U, 209789U, 15244U, 142850U, 40290U, + 171253U, 18160U, 146141U, 3772U, 129388U, 7475U, 133743U, 34243U, + 164240U, 12984U, 140182U, 39107U, 169873U, 76681U, 212669U, 17021U, + 144804U, 42144U, 173275U, 78583U, 214726U, 104843U, 244217U, 3052U, + 128528U, 30495U, 159863U, 10700U, 137556U, 6727U, 132855U, 33467U, + 163324U, 73084U, 208533U, 12236U, 139294U, 38331U, 168957U, 75905U, + 211753U, 103045U, 242284U, 1356U, 126512U, 28735U, 157783U, 69232U, + 204032U, 9004U, 135540U, 35821U, 166085U, 14504U, 141970U, 5847U, + 131815U, 32555U, 162252U, 72172U, 207461U, 101389U, 240444U, 2204U, + 127520U, 29615U, 158823U, 70112U, 205072U, 99338U, 238064U, 9852U, + 136548U, 36701U, 167125U, 74275U, 209921U, 15352U, 142978U, 40402U, + 171385U, 18268U, 146269U, 3876U, 129512U, 7583U, 133871U, 34355U, + 164372U, 13092U, 140310U, 39219U, 170005U, 76793U, 212801U, 17129U, + 144932U, 42256U, 173407U, 78695U, 214858U, 104955U, 244349U, 23574U, + 152077U, 65010U, 199187U, 95806U, 233978U, 117709U, 258227U, 47109U, + 178584U, 82844U, 219171U, 22230U, 150413U, 64354U, 198371U, 95494U, + 233586U, 117569U, 258047U, 46405U, 177720U, 22902U, 151245U, 64682U, + 198779U, 95650U, 233782U, 117639U, 258137U, 24255U, 152928U, 65363U, + 199630U, 95995U, 234217U, 117816U, 258364U, 47824U, 179469U, 83559U, + 220056U, 109115U, 248683U, 24680U, 153453U, 65604U, 199931U, 96144U, + 234406U, 48081U, 179786U, 83628U, 220145U, 22955U, 151313U, 64735U, + 198847U, 95703U, 233850U, 46461U, 177791U, 82196U, 218378U, 24320U, + 153013U, 65428U, 199715U, 96060U, 234302U, 47893U, 179558U, 21611U, + 149649U, 64079U, 198031U, 95391U, 233458U, 45757U, 176927U, 24500U, + 153233U, 65516U, 199823U, 96102U, 234354U, 22283U, 150481U, 64407U, + 198439U, 95547U, 233654U, 24860U, 153673U, 65692U, 200039U, 96186U, + 234458U, 48269U, 180014U, 83816U, 220373U, 109184U, 248772U, 23665U, + 152193U, 65101U, 199303U, 95897U, 234094U, 47205U, 178705U, 82940U, + 219292U, 108496U, 247919U, 24703U, 153481U, 65627U, 199959U, 48105U, + 179815U, 83652U, 220174U, 23041U, 151419U, 64821U, 198953U, 46551U, + 177901U, 82286U, 218488U, 24343U, 153041U, 65451U, 199743U, 47917U, + 179587U, 21697U, 149755U, 64165U, 198137U, 45847U, 177037U, 24523U, + 153261U, 65539U, 199851U, 22369U, 150587U, 64493U, 198545U, 24882U, + 153700U, 65714U, 200066U, 48292U, 180042U, 83839U, 220401U, 109207U, + 248800U, 23747U, 152295U, 65183U, 199405U, 47291U, 178811U, 83026U, + 219398U, 108582U, 248025U, 24726U, 153509U, 65650U, 199987U, 48129U, + 179844U, 83676U, 220203U, 23127U, 151525U, 64907U, 199059U, 46641U, + 178011U, 82376U, 218598U, 24366U, 153069U, 65474U, 199771U, 47941U, + 179616U, 21783U, 149861U, 64251U, 198243U, 45937U, 177147U, 24546U, + 153289U, 65562U, 199879U, 22455U, 150693U, 64579U, 198651U, 24904U, + 153727U, 65736U, 200093U, 48315U, 180070U, 83862U, 220429U, 109230U, + 248828U, 23829U, 152397U, 65265U, 199507U, 47377U, 178917U, 83112U, + 219504U, 108668U, 248131U, 24749U, 153537U, 48153U, 179873U, 83700U, + 220232U, 23213U, 151631U, 46731U, 178121U, 82466U, 218708U, 24389U, + 153097U, 47965U, 179645U, 21869U, 149967U, 46027U, 177257U, 24569U, + 153317U, 22541U, 150799U, 24926U, 153754U, 48338U, 180098U, 83885U, + 220457U, 109253U, 248856U, 23911U, 152499U, 47463U, 179023U, 83198U, + 219610U, 108754U, 248237U, 24772U, 153565U, 48177U, 179902U, 83724U, + 220261U, 23299U, 151737U, 46821U, 178231U, 82556U, 218818U, 24412U, + 153125U, 47989U, 179674U, 21955U, 150073U, 46117U, 177367U, 24592U, + 153345U, 22627U, 150905U, 24948U, 153781U, 48361U, 180126U, 83908U, + 220485U, 109276U, 248884U, 23993U, 152601U, 47549U, 179129U, 83284U, + 219716U, 108840U, 248343U, 24795U, 153593U, 48201U, 179931U, 83748U, + 220290U, 23385U, 151843U, 46911U, 178341U, 82646U, 218928U, 24435U, + 153153U, 48013U, 179703U, 22041U, 150179U, 46207U, 177477U, 24615U, + 153373U, 22713U, 151011U, 24970U, 153808U, 48384U, 180154U, 83931U, + 220513U, 109299U, 248912U, 24075U, 152703U, 47635U, 179235U, 83370U, + 219822U, 108926U, 248449U, 24818U, 153621U, 48225U, 179960U, 83772U, + 220319U, 23471U, 151949U, 47001U, 178451U, 82736U, 219038U, 24458U, + 153181U, 48037U, 179732U, 22127U, 150285U, 46297U, 177587U, 24638U, + 153401U, 22799U, 151117U, 24992U, 153835U, 48407U, 180182U, 83954U, + 220541U, 109322U, 248940U, 24157U, 152805U, 47721U, 179341U, 83456U, + 219928U, 109012U, 248555U, 22976U, 151339U, 64756U, 198873U, 95724U, + 233876U, 46483U, 177818U, 82218U, 218405U, 21632U, 149675U, 64100U, + 198057U, 95412U, 233484U, 45779U, 176954U, 22304U, 150507U, 64428U, + 198465U, 95568U, 233680U, 23685U, 152218U, 65121U, 199328U, 95917U, + 234119U, 47226U, 178731U, 82961U, 219318U, 108517U, 247945U, 23062U, + 151445U, 64842U, 198979U, 46573U, 177928U, 82308U, 218515U, 21718U, + 149781U, 64186U, 198163U, 45869U, 177064U, 22390U, 150613U, 64514U, + 198571U, 23767U, 152320U, 65203U, 199430U, 47312U, 178837U, 83047U, + 219424U, 108603U, 248051U, 23148U, 151551U, 64928U, 199085U, 46663U, + 178038U, 82398U, 218625U, 21804U, 149887U, 64272U, 198269U, 45959U, + 177174U, 22476U, 150719U, 64600U, 198677U, 23849U, 152422U, 65285U, + 199532U, 47398U, 178943U, 83133U, 219530U, 108689U, 248157U, 23234U, + 151657U, 46753U, 178148U, 82488U, 218735U, 21890U, 149993U, 46049U, + 177284U, 22562U, 150825U, 23931U, 152524U, 47484U, 179049U, 83219U, + 219636U, 108775U, 248263U, 23320U, 151763U, 46843U, 178258U, 82578U, + 218845U, 21976U, 150099U, 46139U, 177394U, 22648U, 150931U, 24013U, + 152626U, 47570U, 179155U, 83305U, 219742U, 108861U, 248369U, 23406U, + 151869U, 46933U, 178368U, 82668U, 218955U, 22062U, 150205U, 46229U, + 177504U, 22734U, 151037U, 24095U, 152728U, 47656U, 179261U, 83391U, + 219848U, 108947U, 248475U, 23492U, 151975U, 47023U, 178478U, 82758U, + 219065U, 22148U, 150311U, 46319U, 177614U, 22820U, 151143U, 24177U, + 152830U, 47742U, 179367U, 83477U, 219954U, 109033U, 248581U, 3206U, + 128712U, 51511U, 183831U, 86145U, 223115U, 30655U, 160053U, 10854U, + 137740U, 55404U, 188414U, 88089U, 225384U, 112142U, 252248U, 58705U, + 192245U, 90048U, 227703U, 113336U, 253657U, 92202U, 230262U, 114867U, + 255468U, 6887U, 133045U, 53165U, 185767U, 33633U, 163520U, 73250U, + 208729U, 12396U, 139484U, 38497U, 169153U, 76071U, 211949U, 103211U, + 242480U, 1510U, 126696U, 51095U, 183335U, 28895U, 157973U, 69392U, + 204222U, 9158U, 135724U, 54572U, 187422U, 87889U, 225144U, 35981U, + 166275U, 14658U, 142154U, 57873U, 191253U, 89648U, 227223U, 113244U, + 253545U, 60474U, 194339U, 91802U, 229782U, 114683U, 255244U, 6007U, + 132005U, 32721U, 162448U, 72338U, 207657U, 101555U, 240640U, 2358U, + 127704U, 29775U, 159013U, 70272U, 205262U, 99498U, 238254U, 10006U, + 136732U, 54988U, 187918U, 36861U, 167315U, 74435U, 210111U, 15506U, + 143162U, 58289U, 191749U, 89848U, 227463U, 40562U, 171575U, 18422U, + 146453U, 60890U, 194835U, 92002U, 230022U, 114775U, 255356U, 4024U, + 129690U, 51913U, 184313U, 86339U, 223349U, 111403U, 251384U, 55806U, + 188896U, 88283U, 225618U, 112232U, 252358U, 90242U, 227937U, 113426U, + 253767U, 114957U, 255578U, 7737U, 134055U, 53583U, 186265U, 87361U, + 224533U, 34515U, 164562U, 13246U, 140494U, 56884U, 190096U, 39379U, + 170195U, 76953U, 212991U, 17283U, 145116U, 42416U, 173597U, 78855U, + 215048U, 105115U, 244539U, 2458U, 127824U, 51195U, 183455U, 86045U, + 222995U, 29879U, 159137U, 10106U, 136852U, 55088U, 188038U, 87989U, + 225264U, 58389U, 191869U, 89948U, 227583U, 92102U, 230142U, 6111U, + 132129U, 52837U, 185379U, 32829U, 162576U, 72446U, 207785U, 11620U, + 138568U, 37693U, 168209U, 75267U, 211005U, 102407U, 241536U, 762U, + 125808U, 50779U, 182959U, 28119U, 157057U, 68616U, 203306U, 8410U, + 134836U, 54256U, 187046U, 87789U, 225024U, 35205U, 165359U, 13910U, + 141266U, 57557U, 190877U, 89548U, 227103U, 60158U, 193963U, 91702U, + 229662U, 5231U, 131089U, 31917U, 161504U, 71534U, 206713U, 100751U, + 239696U, 1610U, 126816U, 28999U, 158097U, 69496U, 204346U, 98722U, + 237338U, 9258U, 135844U, 54672U, 187542U, 36085U, 166399U, 73659U, + 209195U, 14758U, 142274U, 57973U, 191373U, 89748U, 227343U, 39786U, + 170659U, 17674U, 145565U, 60574U, 194459U, 91902U, 229902U, 3304U, + 128830U, 51609U, 183949U, 86243U, 223233U, 55502U, 188532U, 88187U, + 225502U, 90146U, 227821U, 6989U, 133167U, 53267U, 185889U, 87261U, + 224413U, 33739U, 163646U, 12498U, 139606U, 56568U, 189720U, 38603U, + 169279U, 76177U, 212075U, 16535U, 144228U, 41640U, 172681U, 78079U, + 214132U, 104339U, 243623U, 2566U, 127952U, 51303U, 183583U, 29991U, + 159269U, 10214U, 136980U, 55196U, 188166U, 58497U, 191997U, 6223U, + 132261U, 52949U, 185511U, 32945U, 162712U, 72562U, 207921U, 11732U, + 138700U, 37809U, 168345U, 75383U, 211141U, 102523U, 241672U, 870U, + 125936U, 50887U, 183087U, 28231U, 157189U, 68728U, 203438U, 8518U, + 134964U, 54364U, 187174U, 35317U, 165491U, 14018U, 141394U, 57665U, + 191005U, 60266U, 194091U, 5343U, 131221U, 32033U, 161640U, 71650U, + 206849U, 100867U, 239832U, 1718U, 126944U, 29111U, 158229U, 69608U, + 204478U, 98834U, 237470U, 9366U, 135972U, 54780U, 187670U, 36197U, + 166531U, 73771U, 209327U, 14866U, 142402U, 58081U, 191501U, 39898U, + 170791U, 17782U, 145693U, 60682U, 194587U, 3408U, 128954U, 51713U, + 184073U, 55606U, 188656U, 7097U, 133295U, 53375U, 186017U, 33851U, + 163778U, 12606U, 139734U, 56676U, 189848U, 38715U, 169411U, 76289U, + 212207U, 16643U, 144356U, 41752U, 172813U, 78191U, 214264U, 104451U, + 243755U, 2674U, 128080U, 51411U, 183711U, 30103U, 159401U, 10322U, + 137108U, 55304U, 188294U, 58605U, 192125U, 6335U, 132393U, 53061U, + 185643U, 33061U, 162848U, 72678U, 208057U, 11844U, 138832U, 37925U, + 168481U, 75499U, 211277U, 102639U, 241808U, 978U, 126064U, 50995U, + 183215U, 28343U, 157321U, 68840U, 203570U, 8626U, 135092U, 54472U, + 187302U, 35429U, 165623U, 14126U, 141522U, 57773U, 191133U, 60374U, + 194219U, 5455U, 131353U, 32149U, 161776U, 71766U, 206985U, 100983U, + 239968U, 1826U, 127072U, 29223U, 158361U, 69720U, 204610U, 98946U, + 237602U, 9474U, 136100U, 54888U, 187798U, 36309U, 166663U, 73883U, + 209459U, 14974U, 142530U, 58189U, 191629U, 40010U, 170923U, 17890U, + 145821U, 60790U, 194715U, 3512U, 129078U, 51817U, 184197U, 55710U, + 188780U, 7205U, 133423U, 53483U, 186145U, 33963U, 163910U, 12714U, + 139862U, 56784U, 189976U, 38827U, 169543U, 76401U, 212339U, 16751U, + 144484U, 41864U, 172945U, 78303U, 214396U, 104563U, 243887U, 2782U, + 128208U, 30215U, 159533U, 10430U, 137236U, 6447U, 132525U, 33177U, + 162984U, 72794U, 208193U, 11956U, 138964U, 38041U, 168617U, 75615U, + 211413U, 102755U, 241944U, 1086U, 126192U, 28455U, 157453U, 68952U, + 203702U, 8734U, 135220U, 35541U, 165755U, 14234U, 141650U, 5567U, + 131485U, 32265U, 161912U, 71882U, 207121U, 101099U, 240104U, 1934U, + 127200U, 29335U, 158493U, 69832U, 204742U, 99058U, 237734U, 9582U, + 136228U, 36421U, 166795U, 73995U, 209591U, 15082U, 142658U, 40122U, + 171055U, 17998U, 145949U, 3616U, 129202U, 7313U, 133551U, 34075U, + 164042U, 12822U, 139990U, 38939U, 169675U, 76513U, 212471U, 16859U, + 144612U, 41976U, 173077U, 78415U, 214528U, 104675U, 244019U, 2890U, + 128336U, 30327U, 159665U, 10538U, 137364U, 6559U, 132657U, 33293U, + 163120U, 72910U, 208329U, 12068U, 139096U, 38157U, 168753U, 75731U, + 211549U, 102871U, 242080U, 1194U, 126320U, 28567U, 157585U, 69064U, + 203834U, 8842U, 135348U, 35653U, 165887U, 14342U, 141778U, 5679U, + 131617U, 32381U, 162048U, 71998U, 207257U, 101215U, 240240U, 2042U, + 127328U, 29447U, 158625U, 69944U, 204874U, 99170U, 237866U, 9690U, + 136356U, 36533U, 166927U, 74107U, 209723U, 15190U, 142786U, 40234U, + 171187U, 18106U, 146077U, 3720U, 129326U, 7421U, 133679U, 34187U, + 164174U, 12930U, 140118U, 39051U, 169807U, 76625U, 212603U, 16967U, + 144740U, 42088U, 173209U, 78527U, 214660U, 104787U, 244151U, 2998U, + 128464U, 30439U, 159797U, 10646U, 137492U, 6671U, 132789U, 33409U, + 163256U, 73026U, 208465U, 12180U, 139228U, 38273U, 168889U, 75847U, + 211685U, 102987U, 242216U, 1302U, 126448U, 28679U, 157717U, 69176U, + 203966U, 8950U, 135476U, 35765U, 166019U, 14450U, 141906U, 5791U, + 131749U, 32497U, 162184U, 72114U, 207393U, 101331U, 240376U, 2150U, + 127456U, 29559U, 158757U, 70056U, 205006U, 99282U, 237998U, 9798U, + 136484U, 36645U, 167059U, 74219U, 209855U, 15298U, 142914U, 40346U, + 171319U, 18214U, 146205U, 3824U, 129450U, 7529U, 133807U, 34299U, + 164306U, 13038U, 140246U, 39163U, 169939U, 76737U, 212735U, 17075U, + 144868U, 42200U, 173341U, 78639U, 214792U, 104899U, 244283U, 3106U, + 128592U, 30551U, 159929U, 10754U, 137620U, 6783U, 132921U, 33525U, + 163392U, 73142U, 208601U, 12292U, 139360U, 38389U, 169025U, 75963U, + 211821U, 103103U, 242352U, 1410U, 126576U, 28791U, 157849U, 69288U, + 204098U, 9058U, 135604U, 35877U, 166151U, 14558U, 142034U, 5903U, + 131881U, 32613U, 162320U, 72230U, 207529U, 101447U, 240512U, 2258U, + 127584U, 29671U, 158889U, 70168U, 205138U, 99394U, 238130U, 9906U, + 136612U, 36757U, 167191U, 74331U, 209987U, 15406U, 143042U, 40458U, + 171451U, 18322U, 146333U, 3928U, 129574U, 7637U, 133935U, 34411U, + 164438U, 13146U, 140374U, 39275U, 170071U, 76849U, 212867U, 17183U, + 144996U, 42312U, 173473U, 78751U, 214924U, 105011U, 244415U, 20285U, + 147986U, 62753U, 196368U, 94065U, 231795U, 116644U, 256890U, 44359U, + 175193U, 80798U, 216644U, 107058U, 246135U, 25759U, 154737U, 66503U, + 200995U, 96953U, 235360U, 118309U, 258942U, 49210U, 181118U, 84757U, + 221477U, 110125U, 249876U, 19064U, 61532U, 92844U, 115522U, 43075U, + 79514U, 105774U, 18538U, 61006U, 92318U, 115071U, 42538U, 78977U, + 105237U, 19304U, 61772U, 93084U, 115762U, 43328U, 79767U, 106027U, + 20342U, 62810U, 94122U, 116662U, 44419U, 80858U, 107118U, 19420U, + 61888U, 93200U, 115878U, 43450U, 79889U, 106149U, 25796U, 66540U, + 96990U, 118327U, 49249U, 84796U, 110164U, 20435U, 148153U, 62903U, + 196535U, 94215U, 231962U, 116755U, 257008U, 44517U, 175367U, 80956U, + 216818U, 107216U, 246309U, 25832U, 154807U, 66576U, 201065U, 97026U, + 235430U, 118363U, 258988U, 49287U, 181191U, 84834U, 221550U, 110202U, + 249949U, 19158U, 61626U, 92938U, 115616U, 43174U, 79613U, 105873U, + 19121U, 61589U, 92901U, 115579U, 43135U, 79574U, 105834U, 21316U, + 149274U, 63784U, 197656U, 95096U, 233083U, 117444U, 257887U, 45446U, + 176536U, 81885U, 217987U, 108145U, 247478U, 26676U, 155876U, 67420U, + 202134U, 97870U, 236499U, 119032U, 259837U, 50176U, 182305U, 85723U, + 222664U, 111091U, 251063U, 21387U, 149365U, 63855U, 197747U, 95167U, + 233174U, 117515U, 257978U, 45521U, 176631U, 81960U, 218082U, 108220U, + 247573U, 26711U, 155921U, 67455U, 202179U, 97905U, 236544U, 119067U, + 259882U, 50213U, 182352U, 85760U, 222711U, 111128U, 251110U, 108U, + 98184U, 27444U, 26983U, 67950U, 67735U, 98339U, 19101U, 61569U, + 92881U, 115559U, 43114U, 79553U, 105813U, 19341U, 61809U, 93121U, + 115799U, 43367U, 79806U, 106066U, 19457U, 61925U, 93237U, 115915U, + 43489U, 79928U, 106188U, 16168U, 143934U, 59332U, 193017U, 90867U, + 228707U, 113898U, 254349U, 41255U, 172376U, 77664U, 213792U, 103924U, + 243283U, 4649U, 130460U, 52538U, 185083U, 86964U, 224119U, 111875U, + 251966U, 31311U, 160854U, 70928U, 206063U, 100154U, 239055U, 11363U, + 138324U, 56313U, 189478U, 88755U, 226200U, 112704U, 252940U, 37394U, + 167921U, 74968U, 210717U, 102108U, 241248U, 20865U, 148703U, 63333U, + 197085U, 94645U, 232512U, 117111U, 257464U, 44971U, 175941U, 81410U, + 217392U, 107670U, 246883U, 15952U, 143668U, 59116U, 192751U, 90651U, + 228441U, 113703U, 254109U, 41029U, 172100U, 77438U, 213516U, 103698U, + 243007U, 4433U, 130194U, 52322U, 184817U, 86748U, 223853U, 111680U, + 251726U, 31085U, 160578U, 70702U, 205787U, 99928U, 238779U, 11168U, + 138084U, 56118U, 189238U, 88560U, 225960U, 112509U, 252700U, 37190U, + 167672U, 74764U, 210468U, 101904U, 240999U, 16188U, 143959U, 59352U, + 193042U, 90887U, 228732U, 113918U, 254374U, 41276U, 172402U, 77685U, + 213818U, 103945U, 243309U, 4669U, 130485U, 52558U, 185108U, 86984U, + 224144U, 111895U, 251991U, 31332U, 160880U, 70949U, 206089U, 100175U, + 239081U, 11383U, 138349U, 56333U, 189503U, 88775U, 226225U, 112724U, + 252965U, 37415U, 167947U, 74989U, 210743U, 102129U, 241274U, 15972U, + 143693U, 59136U, 192776U, 90671U, 228466U, 113723U, 254134U, 41050U, + 172126U, 77459U, 213542U, 103719U, 243033U, 4453U, 130219U, 52342U, + 184842U, 86768U, 223878U, 111700U, 251751U, 31106U, 160604U, 70723U, + 205813U, 99949U, 238805U, 11188U, 138109U, 56138U, 189263U, 88580U, + 225985U, 112529U, 252725U, 37211U, 167698U, 74785U, 210494U, 101925U, + 241025U, 20542U, 148290U, 63010U, 196672U, 94322U, 232099U, 116825U, + 257098U, 44630U, 175510U, 81069U, 216961U, 107329U, 246452U, 16208U, + 143984U, 59372U, 193067U, 90907U, 228757U, 113938U, 254399U, 41297U, + 172428U, 77706U, 213844U, 103966U, 243335U, 4689U, 130510U, 52578U, + 185133U, 87004U, 224169U, 111915U, 252016U, 31353U, 160906U, 70970U, + 206115U, 100196U, 239107U, 11403U, 138374U, 56353U, 189528U, 88795U, + 226250U, 112744U, 252990U, 37436U, 167973U, 75010U, 210769U, 102150U, + 241300U, 20955U, 148818U, 63423U, 197200U, 94735U, 232627U, 117201U, + 257579U, 45066U, 176061U, 81505U, 217512U, 107765U, 247003U, 15992U, + 143718U, 59156U, 192801U, 90691U, 228491U, 113743U, 254159U, 41071U, + 172152U, 77480U, 213568U, 103740U, 243059U, 4473U, 130244U, 52362U, + 184867U, 86788U, 223903U, 111720U, 251776U, 31127U, 160630U, 70744U, + 205839U, 99970U, 238831U, 11208U, 138134U, 56158U, 189288U, 88600U, + 226010U, 112549U, 252750U, 37232U, 167724U, 74806U, 210520U, 101946U, + 241051U, 20578U, 148336U, 63046U, 196718U, 94358U, 232145U, 116861U, + 257144U, 44668U, 175558U, 81107U, 217009U, 107367U, 246500U, 21200U, + 149128U, 63668U, 197510U, 94980U, 232937U, 117369U, 257792U, 45324U, + 176384U, 81763U, 217835U, 108023U, 247326U, 26541U, 155706U, 67285U, + 201964U, 97735U, 236329U, 118938U, 259718U, 50034U, 182128U, 85581U, + 222487U, 110949U, 250886U, 20828U, 148656U, 63296U, 197038U, 94608U, + 232465U, 117074U, 257417U, 44932U, 175892U, 81371U, 217343U, 107631U, + 246834U, 26096U, 155146U, 66840U, 201404U, 97290U, 235769U, 118591U, + 259281U, 49566U, 181545U, 85113U, 221904U, 110481U, 250303U, 19139U, + 61607U, 92919U, 115597U, 43154U, 79593U, 105853U, 19212U, 61680U, + 92992U, 115670U, 43231U, 79670U, 105930U, 19177U, 61645U, 92957U, + 115635U, 43194U, 79633U, 105893U, 19195U, 61663U, 92975U, 115653U, + 43213U, 79652U, 105912U, 19267U, 61735U, 93047U, 115725U, 43289U, + 79728U, 105988U, 20207U, 62675U, 93987U, 116587U, 44277U, 80716U, + 106976U, 19383U, 61851U, 93163U, 115841U, 43411U, 79850U, 106110U, + 25741U, 66485U, 96935U, 118291U, 49191U, 84738U, 110106U, 40U, + 98112U, 236755U, 125020U, 27376U, 156248U, 26911U, 156132U, 67882U, + 202506U, 67663U, 202390U, 98271U, 236871U, 18740U, 146811U, 61208U, + 195193U, 92520U, 230620U, 115273U, 255934U, 42751U, 173970U, 79190U, + 215421U, 105450U, 244912U, 20883U, 148726U, 63351U, 197108U, 94663U, + 232535U, 117129U, 257487U, 44990U, 175965U, 81429U, 217416U, 107689U, + 246907U, 26203U, 155278U, 66947U, 201536U, 97397U, 235901U, 118698U, + 259413U, 49678U, 181682U, 85225U, 222041U, 110593U, 250440U, 125U, + 98202U, 27461U, 27001U, 67967U, 67753U, 98356U, 124858U, 270344U, + 261260U, 263743U, 124704U, 270044U, 261243U, 263724U, 18868U, 146974U, + 61336U, 195356U, 92648U, 230783U, 115401U, 256097U, 42886U, 174140U, + 79325U, 215591U, 105585U, 245082U, 26620U, 155805U, 67364U, 202063U, + 97814U, 236428U, 118976U, 259766U, 50117U, 182231U, 85664U, 222590U, + 111032U, 250989U, 18812U, 146903U, 61280U, 195285U, 92592U, 230712U, + 115345U, 256026U, 42827U, 174066U, 79266U, 215517U, 105526U, 245008U, + 26296U, 155396U, 67040U, 201654U, 97490U, 236019U, 118770U, 259505U, + 49776U, 181805U, 85323U, 222164U, 110691U, 250563U, 57U, 98130U, + 236778U, 125042U, 27393U, 156270U, 26929U, 156155U, 67899U, 202528U, + 67681U, 202413U, 98288U, 236893U, 18849U, 146950U, 61317U, 195332U, + 92629U, 230759U, 115382U, 256073U, 42866U, 174115U, 79305U, 215566U, + 105565U, 245057U, 21125U, 149033U, 63593U, 197415U, 94905U, 232842U, + 117313U, 257721U, 45245U, 176285U, 81684U, 217736U, 107944U, 247227U, + 26466U, 155611U, 67210U, 201869U, 97660U, 236234U, 118882U, 259647U, + 49955U, 182029U, 85502U, 222388U, 110870U, 250787U, 18608U, 146644U, + 61076U, 195026U, 92388U, 230453U, 115141U, 255767U, 42612U, 173796U, + 79051U, 215247U, 105311U, 244738U, 20560U, 148313U, 63028U, 196695U, + 94340U, 232122U, 116843U, 257121U, 44649U, 175534U, 81088U, 216985U, + 107348U, 246476U, 25920U, 154920U, 66664U, 201178U, 97114U, 235543U, + 118433U, 259078U, 49380U, 181309U, 84927U, 221668U, 110295U, 250067U, + 124894U, 21279U, 149227U, 63747U, 197609U, 95059U, 233036U, 117407U, + 257840U, 45407U, 176487U, 81846U, 217938U, 108106U, 247429U, 26639U, + 155829U, 67383U, 202087U, 97833U, 236452U, 118995U, 259790U, 50137U, + 182256U, 85684U, 222615U, 111052U, 251014U, 124833U, 20973U, 148841U, + 63441U, 197223U, 94753U, 232650U, 117219U, 257602U, 45085U, 176085U, + 81524U, 217536U, 107784U, 247027U, 26314U, 155419U, 67058U, 201677U, + 97508U, 236042U, 118788U, 259528U, 49795U, 181829U, 85342U, 222188U, + 110710U, 250587U, 18626U, 146667U, 61094U, 195049U, 92406U, 230476U, + 115159U, 255790U, 42631U, 173820U, 79070U, 215271U, 105330U, 244762U, + 20596U, 148359U, 63064U, 196741U, 94376U, 232168U, 116879U, 257167U, + 44687U, 175582U, 81126U, 217033U, 107386U, 246524U, 25938U, 154943U, + 66682U, 201201U, 97132U, 235566U, 118451U, 259101U, 49399U, 181333U, + 84946U, 221692U, 110314U, 250091U, 74U, 98148U, 236801U, 125064U, + 27410U, 156292U, 26947U, 156178U, 67916U, 202550U, 67699U, 202436U, + 98305U, 236915U, 21239U, 149177U, 63707U, 197559U, 95019U, 232986U, + 117387U, 257815U, 45365U, 176435U, 81804U, 217886U, 108064U, 247377U, + 26580U, 155755U, 67324U, 202013U, 97774U, 236378U, 118956U, 259741U, + 50075U, 182179U, 85622U, 222538U, 110990U, 250937U, 21144U, 149057U, + 63612U, 197439U, 94924U, 232866U, 117332U, 257745U, 45265U, 176310U, + 81704U, 217761U, 107964U, 247252U, 26485U, 155635U, 67229U, 201893U, + 97679U, 236258U, 118901U, 259671U, 49975U, 182054U, 85522U, 222413U, + 110890U, 250812U, 20614U, 148382U, 63082U, 196764U, 94394U, 232191U, + 116897U, 257190U, 44706U, 175606U, 81145U, 217057U, 107405U, 246548U, + 25956U, 154966U, 66700U, 201224U, 97150U, 235589U, 118469U, 259124U, + 49418U, 181357U, 84965U, 221716U, 110333U, 250115U, 20739U, 148542U, + 63207U, 196924U, 94519U, 232351U, 117022U, 257350U, 44838U, 175773U, + 81277U, 217224U, 107537U, 246715U, 26044U, 155079U, 66788U, 201337U, + 97238U, 235702U, 118557U, 259237U, 49511U, 181475U, 85058U, 221834U, + 110426U, 250233U, 268952U, 268973U, 268994U, 269015U, 26877U, 67621U, + 98071U, 119084U, 50388U, 85935U, 111303U, 18962U, 61430U, 92742U, + 115420U, 42985U, 79424U, 105684U, 25328U, 66072U, 96522U, 118109U, + 48758U, 84305U, 109673U, 26894U, 67638U, 98088U, 119101U, 50406U, + 85953U, 111321U, 19890U, 62358U, 93670U, 116348U, 43943U, 80382U, + 106642U, 19230U, 61698U, 93010U, 115688U, 43250U, 79689U, 105949U, + 19249U, 61717U, 93029U, 115707U, 43270U, 79709U, 105969U, 18942U, + 147068U, 61410U, 195450U, 92722U, 230877U, 42964U, 174238U, 79403U, + 215689U, 105663U, 245180U, 21591U, 149624U, 64059U, 198006U, 95371U, + 233433U, 45736U, 176901U, 82175U, 218352U, 108435U, 247843U, 26857U, + 156107U, 67601U, 202365U, 98051U, 236730U, 50367U, 182546U, 85914U, + 222905U, 111282U, 251304U, 18923U, 147044U, 61391U, 195426U, 92703U, + 230853U, 42944U, 174213U, 79383U, 215664U, 105643U, 245155U, 21534U, + 149552U, 64002U, 197934U, 95314U, 233361U, 45676U, 176826U, 82115U, + 218277U, 108375U, 247768U, 26800U, 156035U, 67544U, 202293U, 97994U, + 236658U, 50307U, 182471U, 85854U, 222830U, 111222U, 251229U, 20147U, + 147836U, 62615U, 196218U, 93927U, 231645U, 116568U, 256817U, 44214U, + 175037U, 80653U, 216488U, 106913U, 245979U, 25722U, 154713U, 66466U, + 200971U, 96916U, 235336U, 118272U, 258918U, 49171U, 181093U, 84718U, + 221452U, 110086U, 249851U, 20017U, 147671U, 62485U, 196053U, 93797U, + 231480U, 116475U, 256699U, 44077U, 174865U, 80516U, 216316U, 106776U, + 245807U, 25632U, 154598U, 66376U, 200856U, 96826U, 235221U, 118200U, + 258826U, 49076U, 180973U, 84623U, 221332U, 109991U, 249731U, 18887U, + 146998U, 61355U, 195380U, 92667U, 230807U, 42906U, 174165U, 79345U, + 215616U, 105605U, 245107U, 21424U, 149412U, 63892U, 197794U, 95204U, + 233221U, 45560U, 176680U, 81999U, 218131U, 108259U, 247622U, 26728U, + 155943U, 67472U, 202201U, 97922U, 236566U, 50231U, 182375U, 85778U, + 222734U, 111146U, 251133U, 18905U, 147021U, 61373U, 195403U, 92685U, + 230830U, 42925U, 174189U, 79364U, 215640U, 105624U, 245131U, 21516U, + 149529U, 63984U, 197911U, 95296U, 233338U, 45657U, 176802U, 82096U, + 218253U, 108356U, 247744U, 26782U, 156012U, 67526U, 202270U, 97976U, + 236635U, 50288U, 182447U, 85835U, 222806U, 111203U, 251205U, 18779U, + 146860U, 61247U, 195242U, 92559U, 230669U, 115312U, 255983U, 42792U, + 174021U, 79231U, 215472U, 105491U, 244963U, 20922U, 148775U, 63390U, + 197157U, 94702U, 232584U, 117168U, 257536U, 45031U, 176016U, 81470U, + 217467U, 107730U, 246958U, 26242U, 155327U, 66986U, 201585U, 97436U, + 235950U, 118737U, 259462U, 49719U, 181733U, 85266U, 222092U, 110634U, + 250491U, 19494U, 147115U, 61962U, 195497U, 93274U, 230924U, 115952U, + 256143U, 43528U, 174287U, 79967U, 215738U, 106227U, 245229U, 19768U, + 147454U, 62236U, 195836U, 93548U, 231263U, 116226U, 256482U, 43815U, + 174639U, 80254U, 216090U, 106514U, 245581U, 19810U, 147506U, 62278U, + 195888U, 93590U, 231315U, 116268U, 256534U, 43859U, 174693U, 80298U, + 216144U, 106558U, 245635U, 19747U, 147428U, 62215U, 195810U, 93527U, + 231237U, 116205U, 256456U, 43793U, 174612U, 80232U, 216063U, 106492U, + 245554U, 19666U, 147327U, 62134U, 195709U, 93446U, 231136U, 116124U, + 256355U, 43708U, 174507U, 80147U, 215958U, 106407U, 245449U, 19686U, + 147352U, 62154U, 195734U, 93466U, 231161U, 116144U, 256380U, 43729U, + 174533U, 80168U, 215984U, 106428U, 245475U, 19514U, 147140U, 61982U, + 195522U, 93294U, 230949U, 115972U, 256168U, 43549U, 174313U, 79988U, + 215764U, 106248U, 245255U, 19705U, 147376U, 62173U, 195758U, 93485U, + 231185U, 116163U, 256404U, 43749U, 174558U, 80188U, 216009U, 106448U, + 245500U, 4874U, 52763U, 87189U, 31547U, 71164U, 100390U, 10900U, + 55850U, 36909U, 74483U, 101623U, 11546U, 56496U, 37586U, 75160U, + 102300U, 15552U, 40610U, 77019U, 103279U, 16393U, 41491U, 77900U, + 104160U, 16428U, 41528U, 77937U, 104197U, 16463U, 41565U, 77974U, + 104234U, 18468U, 60936U, 92248U, 115001U, 21182U, 149105U, 63650U, + 197487U, 94962U, 232914U, 117351U, 257769U, 45305U, 176360U, 81744U, + 217811U, 108004U, 247302U, 26523U, 155683U, 67267U, 201941U, 97717U, + 236306U, 118920U, 259695U, 50015U, 182104U, 85562U, 222463U, 110930U, + 250862U, 20793U, 148611U, 63261U, 196993U, 94573U, 232420U, 117039U, + 257372U, 44895U, 175845U, 81334U, 217296U, 107594U, 246787U, 26079U, + 155124U, 66823U, 201382U, 97273U, 235747U, 118574U, 259259U, 49548U, + 181522U, 85095U, 221881U, 110463U, 250280U, 680U, 125711U, 50697U, + 182862U, 28034U, 156957U, 68531U, 203206U, 8328U, 134739U, 54174U, + 186949U, 87707U, 224927U, 35120U, 165259U, 13828U, 141169U, 57475U, + 190780U, 89466U, 227006U, 113170U, 253456U, 60076U, 193866U, 91620U, + 229565U, 114609U, 255155U, 5146U, 130989U, 31829U, 161401U, 71446U, + 206610U, 100663U, 239593U, 37605U, 168106U, 75179U, 210902U, 102319U, + 241433U, 77993U, 214031U, 104253U, 243522U, 18758U, 146834U, 61226U, + 195216U, 92538U, 230643U, 115291U, 255957U, 42770U, 173994U, 79209U, + 215445U, 105469U, 244936U, 20901U, 148749U, 63369U, 197131U, 94681U, + 232558U, 117147U, 257510U, 45009U, 175989U, 81448U, 217440U, 107708U, + 246931U, 26221U, 155301U, 66965U, 201559U, 97415U, 235924U, 118716U, + 259436U, 49697U, 181706U, 85244U, 222065U, 110612U, 250464U, 18520U, + 146554U, 60988U, 194936U, 92300U, 230363U, 115053U, 255677U, 42519U, + 173702U, 78958U, 215153U, 105218U, 244644U, 25651U, 154622U, 66395U, + 200880U, 96845U, 235245U, 118219U, 258850U, 49096U, 180998U, 84643U, + 221357U, 110011U, 249756U, 18830U, 146926U, 61298U, 195308U, 92610U, + 230735U, 115363U, 256049U, 42846U, 174090U, 79285U, 215541U, 105545U, + 245032U, 21087U, 148985U, 63555U, 197367U, 94867U, 232794U, 117294U, + 257697U, 45205U, 176235U, 81644U, 217686U, 107904U, 247177U, 26428U, + 155563U, 67172U, 201821U, 97622U, 236186U, 118863U, 259623U, 49915U, + 181979U, 85462U, 222338U, 110830U, 250737U, 18556U, 146577U, 61024U, + 194959U, 92336U, 230386U, 115089U, 255700U, 42557U, 173726U, 78996U, + 215177U, 105256U, 244668U, 20453U, 148176U, 62921U, 196558U, 94233U, + 231985U, 116773U, 257031U, 44536U, 175391U, 80975U, 216842U, 107235U, + 246333U, 25850U, 154830U, 66594U, 201088U, 97044U, 235453U, 118381U, + 259011U, 49306U, 181215U, 84853U, 221574U, 110221U, 249973U, 19286U, + 61754U, 93066U, 115744U, 43309U, 79748U, 106008U, 19402U, 61870U, + 93182U, 115860U, 43431U, 79870U, 106130U, 23610U, 152123U, 65046U, + 199233U, 95842U, 234024U, 117745U, 258273U, 47147U, 178632U, 82882U, + 219219U, 22266U, 150459U, 64390U, 198417U, 95530U, 233632U, 117605U, + 258093U, 46443U, 177768U, 22938U, 151291U, 64718U, 198825U, 95686U, + 233828U, 117675U, 258183U, 24289U, 152972U, 65397U, 199674U, 96029U, + 234261U, 117850U, 258408U, 47860U, 179515U, 83595U, 220102U, 109151U, + 248729U, 124520U, 124535U, 9U, 7783U, 134111U, 53629U, 186321U, + 87407U, 224589U, 112058U, 252144U, 34563U, 164620U, 73300U, 208789U, + 13292U, 140550U, 56930U, 190152U, 88938U, 226378U, 112887U, 253118U, + 39427U, 170253U, 17329U, 145172U, 59557U, 193247U, 91092U, 228937U, + 114081U, 254527U, 26113U, 155168U, 66857U, 201426U, 97307U, 235791U, + 118608U, 259303U, 49584U, 181568U, 85131U, 221927U, 110499U, 250326U, + 26160U, 155225U, 66904U, 201483U, 97354U, 235848U, 118655U, 259360U, + 49633U, 181627U, 85180U, 221986U, 110548U, 250385U, 18696U, 146757U, + 61164U, 195139U, 92476U, 230566U, 115229U, 255880U, 42705U, 173914U, + 79144U, 215365U, 105404U, 244856U, 26137U, 155197U, 66881U, 201455U, + 97331U, 235820U, 118632U, 259332U, 49609U, 181598U, 85156U, 221957U, + 110524U, 250356U, 18719U, 146785U, 61187U, 195167U, 92499U, 230594U, + 115252U, 255908U, 42729U, 173943U, 79168U, 215394U, 105428U, 244885U, + 26182U, 155252U, 66926U, 201510U, 97376U, 235875U, 118677U, 259387U, + 49656U, 181655U, 85203U, 222014U, 110571U, 250413U, 18644U, 146690U, + 61112U, 195072U, 92424U, 230499U, 115177U, 255813U, 42650U, 173844U, + 79089U, 215295U, 105349U, 244786U, 20651U, 148429U, 63119U, 196811U, + 94431U, 232238U, 116934U, 257237U, 44745U, 175655U, 81184U, 217106U, + 107444U, 246597U, 25974U, 154989U, 66718U, 201247U, 97168U, 235612U, + 118487U, 259147U, 49437U, 181381U, 84984U, 221740U, 110352U, 250139U, + 20721U, 148519U, 63189U, 196901U, 94501U, 232328U, 117004U, 257327U, + 44819U, 175749U, 81258U, 217200U, 107518U, 246691U, 26026U, 155056U, + 66770U, 201314U, 97220U, 235679U, 118539U, 259214U, 49492U, 181451U, + 85039U, 221810U, 110407U, 250209U, 175U, 98255U, 27511U, 27054U, + 68017U, 67806U, 98406U, 3183U, 128684U, 51488U, 183803U, 86122U, + 223087U, 30631U, 160024U, 10831U, 137712U, 55381U, 188386U, 88066U, + 225356U, 112119U, 252220U, 58682U, 192217U, 90025U, 227675U, 113313U, + 253629U, 92179U, 230234U, 114844U, 255440U, 6863U, 133016U, 53141U, + 185738U, 33608U, 163490U, 73225U, 208699U, 12372U, 139455U, 38472U, + 169123U, 76046U, 211919U, 103186U, 242450U, 1487U, 126668U, 51072U, + 183307U, 28871U, 157944U, 69368U, 204193U, 9135U, 135696U, 54549U, + 187394U, 87866U, 225116U, 35957U, 166246U, 14635U, 142126U, 57850U, + 191225U, 89625U, 227195U, 113221U, 253517U, 60451U, 194311U, 91779U, + 229754U, 114660U, 255216U, 5983U, 131976U, 32696U, 162418U, 72313U, + 207627U, 101530U, 240610U, 2335U, 127676U, 29751U, 158984U, 70248U, + 205233U, 99474U, 238225U, 9983U, 136704U, 54965U, 187890U, 36837U, + 167286U, 74411U, 210082U, 15483U, 143134U, 58266U, 191721U, 89825U, + 227435U, 40538U, 171546U, 18399U, 146425U, 60867U, 194807U, 91979U, + 229994U, 114752U, 255328U, 4002U, 129663U, 51891U, 184286U, 86317U, + 223322U, 111381U, 251357U, 55784U, 188869U, 88261U, 225591U, 112210U, + 252331U, 90220U, 227910U, 113404U, 253740U, 114935U, 255551U, 7714U, + 134027U, 53560U, 186237U, 87338U, 224505U, 34491U, 164533U, 13223U, + 140466U, 56861U, 190068U, 39355U, 170166U, 76929U, 212962U, 17260U, + 145088U, 42392U, 173568U, 78831U, 215019U, 105091U, 244510U, 2431U, + 127792U, 51168U, 183423U, 86018U, 222963U, 29851U, 159104U, 10079U, + 136820U, 55061U, 188006U, 87962U, 225232U, 58362U, 191837U, 89921U, + 227551U, 92075U, 230110U, 6083U, 132096U, 52809U, 185346U, 32800U, + 162542U, 72417U, 207751U, 11592U, 138535U, 37664U, 168175U, 75238U, + 210971U, 102378U, 241502U, 735U, 125776U, 50752U, 182927U, 28091U, + 157024U, 68588U, 203273U, 8383U, 134804U, 54229U, 187014U, 87762U, + 224992U, 35177U, 165326U, 13883U, 141234U, 57530U, 190845U, 89521U, + 227071U, 60131U, 193931U, 91675U, 229630U, 5203U, 131056U, 31888U, + 161470U, 71505U, 206679U, 100722U, 239662U, 1583U, 126784U, 28971U, + 158064U, 69468U, 204313U, 98694U, 237305U, 9231U, 135812U, 54645U, + 187510U, 36057U, 166366U, 73631U, 209162U, 14731U, 142242U, 57946U, + 191341U, 89721U, 227311U, 39758U, 170626U, 17647U, 145533U, 60547U, + 194427U, 91875U, 229870U, 3278U, 128799U, 51583U, 183918U, 86217U, + 223202U, 55476U, 188501U, 88161U, 225471U, 90120U, 227790U, 6962U, + 133135U, 53240U, 185857U, 87234U, 224381U, 33711U, 163613U, 12471U, + 139574U, 56541U, 189688U, 38575U, 169246U, 76149U, 212042U, 16508U, + 144196U, 41612U, 172648U, 78051U, 214099U, 104311U, 243590U, 2539U, + 127920U, 51276U, 183551U, 29963U, 159236U, 10187U, 136948U, 55169U, + 188134U, 58470U, 191965U, 6195U, 132228U, 52921U, 185478U, 32916U, + 162678U, 72533U, 207887U, 11704U, 138667U, 37780U, 168311U, 75354U, + 211107U, 102494U, 241638U, 843U, 125904U, 50860U, 183055U, 28203U, + 157156U, 68700U, 203405U, 8491U, 134932U, 54337U, 187142U, 35289U, + 165458U, 13991U, 141362U, 57638U, 190973U, 60239U, 194059U, 5315U, + 131188U, 32004U, 161606U, 71621U, 206815U, 100838U, 239798U, 1691U, + 126912U, 29083U, 158196U, 69580U, 204445U, 98806U, 237437U, 9339U, + 135940U, 54753U, 187638U, 36169U, 166498U, 73743U, 209294U, 14839U, + 142370U, 58054U, 191469U, 39870U, 170758U, 17755U, 145661U, 60655U, + 194555U, 3382U, 128923U, 51687U, 184042U, 55580U, 188625U, 7070U, + 133263U, 53348U, 185985U, 33823U, 163745U, 12579U, 139702U, 56649U, + 189816U, 38687U, 169378U, 76261U, 212174U, 16616U, 144324U, 41724U, + 172780U, 78163U, 214231U, 104423U, 243722U, 2647U, 128048U, 51384U, + 183679U, 30075U, 159368U, 10295U, 137076U, 55277U, 188262U, 58578U, + 192093U, 6307U, 132360U, 53033U, 185610U, 33032U, 162814U, 72649U, + 208023U, 11816U, 138799U, 37896U, 168447U, 75470U, 211243U, 102610U, + 241774U, 951U, 126032U, 50968U, 183183U, 28315U, 157288U, 68812U, + 203537U, 8599U, 135060U, 54445U, 187270U, 35401U, 165590U, 14099U, + 141490U, 57746U, 191101U, 60347U, 194187U, 5427U, 131320U, 32120U, + 161742U, 71737U, 206951U, 100954U, 239934U, 1799U, 127040U, 29195U, + 158328U, 69692U, 204577U, 98918U, 237569U, 9447U, 136068U, 54861U, + 187766U, 36281U, 166630U, 73855U, 209426U, 14947U, 142498U, 58162U, + 191597U, 39982U, 170890U, 17863U, 145789U, 60763U, 194683U, 3486U, + 129047U, 51791U, 184166U, 55684U, 188749U, 7178U, 133391U, 53456U, + 186113U, 33935U, 163877U, 12687U, 139830U, 56757U, 189944U, 38799U, + 169510U, 76373U, 212306U, 16724U, 144452U, 41836U, 172912U, 78275U, + 214363U, 104535U, 243854U, 2755U, 128176U, 30187U, 159500U, 10403U, + 137204U, 6419U, 132492U, 33148U, 162950U, 72765U, 208159U, 11928U, + 138931U, 38012U, 168583U, 75586U, 211379U, 102726U, 241910U, 1059U, + 126160U, 28427U, 157420U, 68924U, 203669U, 8707U, 135188U, 35513U, + 165722U, 14207U, 141618U, 5539U, 131452U, 32236U, 161878U, 71853U, + 207087U, 101070U, 240070U, 1907U, 127168U, 29307U, 158460U, 69804U, + 204709U, 99030U, 237701U, 9555U, 136196U, 36393U, 166762U, 73967U, + 209558U, 15055U, 142626U, 40094U, 171022U, 17971U, 145917U, 3590U, + 129171U, 7286U, 133519U, 34047U, 164009U, 12795U, 139958U, 38911U, + 169642U, 76485U, 212438U, 16832U, 144580U, 41948U, 173044U, 78387U, + 214495U, 104647U, 243986U, 2863U, 128304U, 30299U, 159632U, 10511U, + 137332U, 6531U, 132624U, 33264U, 163086U, 72881U, 208295U, 12040U, + 139063U, 38128U, 168719U, 75702U, 211515U, 102842U, 242046U, 1167U, + 126288U, 28539U, 157552U, 69036U, 203801U, 8815U, 135316U, 35625U, + 165854U, 14315U, 141746U, 5651U, 131584U, 32352U, 162014U, 71969U, + 207223U, 101186U, 240206U, 2015U, 127296U, 29419U, 158592U, 69916U, + 204841U, 99142U, 237833U, 9663U, 136324U, 36505U, 166894U, 74079U, + 209690U, 15163U, 142754U, 40206U, 171154U, 18079U, 146045U, 3694U, + 129295U, 7394U, 133647U, 34159U, 164141U, 12903U, 140086U, 39023U, + 169774U, 76597U, 212570U, 16940U, 144708U, 42060U, 173176U, 78499U, + 214627U, 104759U, 244118U, 2971U, 128432U, 30411U, 159764U, 10619U, + 137460U, 6643U, 132756U, 33380U, 163222U, 72997U, 208431U, 12152U, + 139195U, 38244U, 168855U, 75818U, 211651U, 102958U, 242182U, 1275U, + 126416U, 28651U, 157684U, 69148U, 203933U, 8923U, 135444U, 35737U, + 165986U, 14423U, 141874U, 5763U, 131716U, 32468U, 162150U, 72085U, + 207359U, 101302U, 240342U, 2123U, 127424U, 29531U, 158724U, 70028U, + 204973U, 99254U, 237965U, 9771U, 136452U, 36617U, 167026U, 74191U, + 209822U, 15271U, 142882U, 40318U, 171286U, 18187U, 146173U, 3798U, + 129419U, 7502U, 133775U, 34271U, 164273U, 13011U, 140214U, 39135U, + 169906U, 76709U, 212702U, 17048U, 144836U, 42172U, 173308U, 78611U, + 214759U, 104871U, 244250U, 3079U, 128560U, 30523U, 159896U, 10727U, + 137588U, 6755U, 132888U, 33496U, 163358U, 73113U, 208567U, 12264U, + 139327U, 38360U, 168991U, 75934U, 211787U, 103074U, 242318U, 1383U, + 126544U, 28763U, 157816U, 69260U, 204065U, 9031U, 135572U, 35849U, + 166118U, 14531U, 142002U, 5875U, 131848U, 32584U, 162286U, 72201U, + 207495U, 101418U, 240478U, 2231U, 127552U, 29643U, 158856U, 70140U, + 205105U, 99366U, 238097U, 9879U, 136580U, 36729U, 167158U, 74303U, + 209954U, 15379U, 143010U, 40430U, 171418U, 18295U, 146301U, 3902U, + 129543U, 7610U, 133903U, 34383U, 164405U, 13119U, 140342U, 39247U, + 170038U, 76821U, 212834U, 17156U, 144964U, 42284U, 173440U, 78723U, + 214891U, 104983U, 244382U, 7821U, 53667U, 87445U, 34603U, 73340U, + 101605U, 10918U, 55868U, 36928U, 74502U, 101642U, 13330U, 56968U, + 39467U, 77001U, 103261U, 15570U, 40629U, 77038U, 103298U, 16411U, + 41510U, 77919U, 104179U, 16446U, 41547U, 77956U, 104216U, 17367U, + 42464U, 78903U, 105163U, 18979U, 61447U, 92759U, 115437U, 18503U, + 146532U, 60971U, 194914U, 92283U, 230341U, 115036U, 255655U, 42501U, + 173679U, 78940U, 215130U, 105200U, 244621U, 19925U, 147554U, 62393U, + 195936U, 93705U, 231363U, 116383U, 256582U, 43980U, 174743U, 80419U, + 216194U, 106679U, 245685U, 25597U, 154553U, 66341U, 200811U, 96791U, + 235176U, 118165U, 258781U, 49039U, 180926U, 84586U, 221285U, 109954U, + 249684U, 18679U, 146735U, 61147U, 195117U, 92459U, 230544U, 115212U, + 255858U, 42687U, 173891U, 79126U, 215342U, 105386U, 244833U, 20686U, + 148474U, 63154U, 196856U, 94466U, 232283U, 116969U, 257282U, 44782U, + 175702U, 81221U, 217153U, 107481U, 246644U, 26009U, 155034U, 66753U, + 201292U, 97203U, 235657U, 118522U, 259192U, 49474U, 181428U, 85021U, + 221787U, 110389U, 250186U, 23592U, 152100U, 65028U, 199210U, 95824U, + 234001U, 117727U, 258250U, 47128U, 178608U, 82863U, 219195U, 22248U, + 150436U, 64372U, 198394U, 95512U, 233609U, 117587U, 258070U, 46424U, + 177744U, 22920U, 151268U, 64700U, 198802U, 95668U, 233805U, 117657U, + 258160U, 24272U, 152950U, 65380U, 199652U, 96012U, 234239U, 117833U, + 258386U, 47842U, 179492U, 83577U, 220079U, 109133U, 248706U, 23020U, + 151393U, 64800U, 198927U, 95768U, 233930U, 46529U, 177874U, 82264U, + 218461U, 21676U, 149729U, 64144U, 198111U, 95456U, 233538U, 45825U, + 177010U, 22348U, 150561U, 64472U, 198519U, 95612U, 233734U, 23727U, + 152270U, 65163U, 199380U, 95959U, 234171U, 47270U, 178785U, 83005U, + 219372U, 108561U, 247999U, 23106U, 151499U, 64886U, 199033U, 46619U, + 177984U, 82354U, 218571U, 21762U, 149835U, 64230U, 198217U, 45915U, + 177120U, 22434U, 150667U, 64558U, 198625U, 23809U, 152372U, 65245U, + 199482U, 47356U, 178891U, 83091U, 219478U, 108647U, 248105U, 23192U, + 151605U, 64972U, 199139U, 46709U, 178094U, 82444U, 218681U, 21848U, + 149941U, 64316U, 198323U, 46005U, 177230U, 22520U, 150773U, 64644U, + 198731U, 23891U, 152474U, 65327U, 199584U, 47442U, 178997U, 83177U, + 219584U, 108733U, 248211U, 23278U, 151711U, 46799U, 178204U, 82534U, + 218791U, 21934U, 150047U, 46095U, 177340U, 22606U, 150879U, 23973U, + 152576U, 47528U, 179103U, 83263U, 219690U, 108819U, 248317U, 23364U, + 151817U, 46889U, 178314U, 82624U, 218901U, 22020U, 150153U, 46185U, + 177450U, 22692U, 150985U, 24055U, 152678U, 47614U, 179209U, 83349U, + 219796U, 108905U, 248423U, 23450U, 151923U, 46979U, 178424U, 82714U, + 219011U, 22106U, 150259U, 46275U, 177560U, 22778U, 151091U, 24137U, + 152780U, 47700U, 179315U, 83435U, 219902U, 108991U, 248529U, 23536U, + 152029U, 47069U, 178534U, 82804U, 219121U, 22192U, 150365U, 46365U, + 177670U, 22864U, 151197U, 24219U, 152882U, 47786U, 179421U, 83521U, + 220008U, 109077U, 248635U, 18485U, 146509U, 60953U, 194891U, 92265U, + 230318U, 115018U, 255632U, 42482U, 173655U, 78921U, 215106U, 105181U, + 244597U, 19907U, 147531U, 62375U, 195913U, 93687U, 231340U, 116365U, + 256559U, 43961U, 174719U, 80400U, 216170U, 106660U, 245661U, 25579U, + 154530U, 66323U, 200788U, 96773U, 235153U, 118147U, 258758U, 49020U, + 180902U, 84567U, 221261U, 109935U, 249660U, 18661U, 146712U, 61129U, + 195094U, 92441U, 230521U, 115194U, 255835U, 42668U, 173867U, 79107U, + 215318U, 105367U, 244809U, 20668U, 148451U, 63136U, 196833U, 94448U, + 232260U, 116951U, 257259U, 44763U, 175678U, 81202U, 217129U, 107462U, + 246620U, 25991U, 155011U, 66735U, 201269U, 97185U, 235634U, 118504U, + 259169U, 49455U, 181404U, 85002U, 221763U, 110370U, 250162U, 22998U, + 151366U, 64778U, 198900U, 95746U, 233903U, 46506U, 177846U, 82241U, + 218433U, 21654U, 149702U, 64122U, 198084U, 95434U, 233511U, 45802U, + 176982U, 22326U, 150534U, 64450U, 198492U, 95590U, 233707U, 23706U, + 152244U, 65142U, 199354U, 95938U, 234145U, 47248U, 178758U, 82983U, + 219345U, 108539U, 247972U, 23084U, 151472U, 64864U, 199006U, 46596U, + 177956U, 82331U, 218543U, 21740U, 149808U, 64208U, 198190U, 45892U, + 177092U, 22412U, 150640U, 64536U, 198598U, 23788U, 152346U, 65224U, + 199456U, 47334U, 178864U, 83069U, 219451U, 108625U, 248078U, 23170U, + 151578U, 64950U, 199112U, 46686U, 178066U, 82421U, 218653U, 21826U, + 149914U, 64294U, 198296U, 45982U, 177202U, 22498U, 150746U, 64622U, + 198704U, 23870U, 152448U, 65306U, 199558U, 47420U, 178970U, 83155U, + 219557U, 108711U, 248184U, 23256U, 151684U, 46776U, 178176U, 82511U, + 218763U, 21912U, 150020U, 46072U, 177312U, 22584U, 150852U, 23952U, + 152550U, 47506U, 179076U, 83241U, 219663U, 108797U, 248290U, 23342U, + 151790U, 46866U, 178286U, 82601U, 218873U, 21998U, 150126U, 46162U, + 177422U, 22670U, 150958U, 24034U, 152652U, 47592U, 179182U, 83327U, + 219769U, 108883U, 248396U, 23428U, 151896U, 46956U, 178396U, 82691U, + 218983U, 22084U, 150232U, 46252U, 177532U, 22756U, 151064U, 24116U, + 152754U, 47678U, 179288U, 83413U, 219875U, 108969U, 248502U, 23514U, + 152002U, 47046U, 178506U, 82781U, 219093U, 22170U, 150338U, 46342U, + 177642U, 22842U, 151170U, 24198U, 152856U, 47764U, 179394U, 83499U, + 219981U, 109055U, 248608U, 21010U, 148888U, 63478U, 197270U, 94790U, + 232697U, 117256U, 257649U, 45124U, 176134U, 81563U, 217585U, 107823U, + 247076U, 26351U, 155466U, 67095U, 201724U, 97545U, 236089U, 118825U, + 259575U, 49834U, 181878U, 85381U, 222237U, 110749U, 250636U, 20036U, + 147695U, 62504U, 196077U, 93816U, 231504U, 116494U, 256723U, 44097U, + 174890U, 80536U, 216341U, 106796U, 245832U, 25669U, 154645U, 66413U, + 200903U, 96863U, 235268U, 118237U, 258873U, 49115U, 181022U, 84662U, + 221381U, 110030U, 249780U, 20054U, 147718U, 62522U, 196100U, 93834U, + 231527U, 116512U, 256746U, 44116U, 174914U, 80555U, 216365U, 106815U, + 245856U, 25687U, 154668U, 66431U, 200926U, 96881U, 235291U, 118255U, + 258896U, 49134U, 181046U, 84681U, 221405U, 110049U, 249804U, 3229U, + 128740U, 51534U, 183859U, 86168U, 223143U, 30679U, 160082U, 10877U, + 137768U, 55427U, 188442U, 88112U, 225412U, 112165U, 252276U, 58728U, + 192273U, 90071U, 227731U, 113359U, 253685U, 92225U, 230290U, 114890U, + 255496U, 6911U, 133074U, 53189U, 185796U, 33658U, 163550U, 73275U, + 208759U, 12420U, 139513U, 38522U, 169183U, 76096U, 211979U, 103236U, + 242510U, 1533U, 126724U, 51118U, 183363U, 28919U, 158002U, 69416U, + 204251U, 9181U, 135752U, 54595U, 187450U, 87912U, 225172U, 36005U, + 166304U, 14681U, 142182U, 57896U, 191281U, 89671U, 227251U, 113267U, + 253573U, 60497U, 194367U, 91825U, 229810U, 114706U, 255272U, 6031U, + 132034U, 32746U, 162478U, 72363U, 207687U, 101580U, 240670U, 2381U, + 127732U, 29799U, 159042U, 70296U, 205291U, 99522U, 238283U, 10029U, + 136760U, 55011U, 187946U, 36885U, 167344U, 74459U, 210140U, 15529U, + 143190U, 58312U, 191777U, 89871U, 227491U, 40586U, 171604U, 18445U, + 146481U, 60913U, 194863U, 92025U, 230050U, 114798U, 255384U, 4046U, + 129717U, 51935U, 184340U, 86361U, 223376U, 111425U, 251411U, 55828U, + 188923U, 88305U, 225645U, 112254U, 252385U, 90264U, 227964U, 113448U, + 253794U, 114979U, 255605U, 7760U, 134083U, 53606U, 186293U, 87384U, + 224561U, 34539U, 164591U, 13269U, 140522U, 56907U, 190124U, 39403U, + 170224U, 76977U, 213020U, 17306U, 145144U, 42440U, 173626U, 78879U, + 215077U, 105139U, 244568U, 2485U, 127856U, 51222U, 183487U, 86072U, + 223027U, 29907U, 159170U, 10133U, 136884U, 55115U, 188070U, 88016U, + 225296U, 58416U, 191901U, 89975U, 227615U, 92129U, 230174U, 6139U, + 132162U, 52865U, 185412U, 32858U, 162610U, 72475U, 207819U, 11648U, + 138601U, 37722U, 168243U, 75296U, 211039U, 102436U, 241570U, 789U, + 125840U, 50806U, 182991U, 28147U, 157090U, 68644U, 203339U, 8437U, + 134868U, 54283U, 187078U, 87816U, 225056U, 35233U, 165392U, 13937U, + 141298U, 57584U, 190909U, 89575U, 227135U, 60185U, 193995U, 91729U, + 229694U, 5259U, 131122U, 31946U, 161538U, 71563U, 206747U, 100780U, + 239730U, 1637U, 126848U, 29027U, 158130U, 69524U, 204379U, 98750U, + 237371U, 9285U, 135876U, 54699U, 187574U, 36113U, 166432U, 73687U, + 209228U, 14785U, 142306U, 58000U, 191405U, 89775U, 227375U, 39814U, + 170692U, 17701U, 145597U, 60601U, 194491U, 91929U, 229934U, 3330U, + 128861U, 51635U, 183980U, 86269U, 223264U, 55528U, 188563U, 88213U, + 225533U, 90172U, 227852U, 7016U, 133199U, 53294U, 185921U, 87288U, + 224445U, 33767U, 163679U, 12525U, 139638U, 56595U, 189752U, 38631U, + 169312U, 76205U, 212108U, 16562U, 144260U, 41668U, 172714U, 78107U, + 214165U, 104367U, 243656U, 2593U, 127984U, 51330U, 183615U, 30019U, + 159302U, 10241U, 137012U, 55223U, 188198U, 58524U, 192029U, 6251U, + 132294U, 52977U, 185544U, 32974U, 162746U, 72591U, 207955U, 11760U, + 138733U, 37838U, 168379U, 75412U, 211175U, 102552U, 241706U, 897U, + 125968U, 50914U, 183119U, 28259U, 157222U, 68756U, 203471U, 8545U, + 134996U, 54391U, 187206U, 35345U, 165524U, 14045U, 141426U, 57692U, + 191037U, 60293U, 194123U, 5371U, 131254U, 32062U, 161674U, 71679U, + 206883U, 100896U, 239866U, 1745U, 126976U, 29139U, 158262U, 69636U, + 204511U, 98862U, 237503U, 9393U, 136004U, 54807U, 187702U, 36225U, + 166564U, 73799U, 209360U, 14893U, 142434U, 58108U, 191533U, 39926U, + 170824U, 17809U, 145725U, 60709U, 194619U, 3434U, 128985U, 51739U, + 184104U, 55632U, 188687U, 7124U, 133327U, 53402U, 186049U, 33879U, + 163811U, 12633U, 139766U, 56703U, 189880U, 38743U, 169444U, 76317U, + 212240U, 16670U, 144388U, 41780U, 172846U, 78219U, 214297U, 104479U, + 243788U, 2701U, 128112U, 51438U, 183743U, 30131U, 159434U, 10349U, + 137140U, 55331U, 188326U, 58632U, 192157U, 6363U, 132426U, 53089U, + 185676U, 33090U, 162882U, 72707U, 208091U, 11872U, 138865U, 37954U, + 168515U, 75528U, 211311U, 102668U, 241842U, 1005U, 126096U, 51022U, + 183247U, 28371U, 157354U, 68868U, 203603U, 8653U, 135124U, 54499U, + 187334U, 35457U, 165656U, 14153U, 141554U, 57800U, 191165U, 60401U, + 194251U, 5483U, 131386U, 32178U, 161810U, 71795U, 207019U, 101012U, + 240002U, 1853U, 127104U, 29251U, 158394U, 69748U, 204643U, 98974U, + 237635U, 9501U, 136132U, 54915U, 187830U, 36337U, 166696U, 73911U, + 209492U, 15001U, 142562U, 58216U, 191661U, 40038U, 170956U, 17917U, + 145853U, 60817U, 194747U, 3538U, 129109U, 51843U, 184228U, 55736U, + 188811U, 7232U, 133455U, 53510U, 186177U, 33991U, 163943U, 12741U, + 139894U, 56811U, 190008U, 38855U, 169576U, 76429U, 212372U, 16778U, + 144516U, 41892U, 172978U, 78331U, 214429U, 104591U, 243920U, 2809U, + 128240U, 30243U, 159566U, 10457U, 137268U, 6475U, 132558U, 33206U, + 163018U, 72823U, 208227U, 11984U, 138997U, 38070U, 168651U, 75644U, + 211447U, 102784U, 241978U, 1113U, 126224U, 28483U, 157486U, 68980U, + 203735U, 8761U, 135252U, 35569U, 165788U, 14261U, 141682U, 5595U, + 131518U, 32294U, 161946U, 71911U, 207155U, 101128U, 240138U, 1961U, + 127232U, 29363U, 158526U, 69860U, 204775U, 99086U, 237767U, 9609U, + 136260U, 36449U, 166828U, 74023U, 209624U, 15109U, 142690U, 40150U, + 171088U, 18025U, 145981U, 3642U, 129233U, 7340U, 133583U, 34103U, + 164075U, 12849U, 140022U, 38967U, 169708U, 76541U, 212504U, 16886U, + 144644U, 42004U, 173110U, 78443U, 214561U, 104703U, 244052U, 2917U, + 128368U, 30355U, 159698U, 10565U, 137396U, 6587U, 132690U, 33322U, + 163154U, 72939U, 208363U, 12096U, 139129U, 38186U, 168787U, 75760U, + 211583U, 102900U, 242114U, 1221U, 126352U, 28595U, 157618U, 69092U, + 203867U, 8869U, 135380U, 35681U, 165920U, 14369U, 141810U, 5707U, + 131650U, 32410U, 162082U, 72027U, 207291U, 101244U, 240274U, 2069U, + 127360U, 29475U, 158658U, 69972U, 204907U, 99198U, 237899U, 9717U, + 136388U, 36561U, 166960U, 74135U, 209756U, 15217U, 142818U, 40262U, + 171220U, 18133U, 146109U, 3746U, 129357U, 7448U, 133711U, 34215U, + 164207U, 12957U, 140150U, 39079U, 169840U, 76653U, 212636U, 16994U, + 144772U, 42116U, 173242U, 78555U, 214693U, 104815U, 244184U, 3025U, + 128496U, 30467U, 159830U, 10673U, 137524U, 6699U, 132822U, 33438U, + 163290U, 73055U, 208499U, 12208U, 139261U, 38302U, 168923U, 75876U, + 211719U, 103016U, 242250U, 1329U, 126480U, 28707U, 157750U, 69204U, + 203999U, 8977U, 135508U, 35793U, 166052U, 14477U, 141938U, 5819U, + 131782U, 32526U, 162218U, 72143U, 207427U, 101360U, 240410U, 2177U, + 127488U, 29587U, 158790U, 70084U, 205039U, 99310U, 238031U, 9825U, + 136516U, 36673U, 167092U, 74247U, 209888U, 15325U, 142946U, 40374U, + 171352U, 18241U, 146237U, 3850U, 129481U, 7556U, 133839U, 34327U, + 164339U, 13065U, 140278U, 39191U, 169972U, 76765U, 212768U, 17102U, + 144900U, 42228U, 173374U, 78667U, 214825U, 104927U, 244316U, 3133U, + 128624U, 30579U, 159962U, 10781U, 137652U, 6811U, 132954U, 33554U, + 163426U, 73171U, 208635U, 12320U, 139393U, 38418U, 169059U, 75992U, + 211855U, 103132U, 242386U, 1437U, 126608U, 28819U, 157882U, 69316U, + 204131U, 9085U, 135636U, 35905U, 166184U, 14585U, 142066U, 5931U, + 131914U, 32642U, 162354U, 72259U, 207563U, 101476U, 240546U, 2285U, + 127616U, 29699U, 158922U, 70196U, 205171U, 99422U, 238163U, 9933U, + 136644U, 36785U, 167224U, 74359U, 210020U, 15433U, 143074U, 40486U, + 171484U, 18349U, 146365U, 3954U, 129605U, 7664U, 133967U, 34439U, + 164471U, 13173U, 140406U, 39303U, 170104U, 76877U, 212900U, 17210U, + 145028U, 42340U, 173506U, 78779U, 214957U, 105039U, 244448U, 21106U, + 149009U, 63574U, 197391U, 94886U, 232818U, 45225U, 176260U, 81664U, + 217711U, 107924U, 247202U, 26447U, 155587U, 67191U, 201845U, 97641U, + 236210U, 49935U, 182004U, 85482U, 222363U, 110850U, 250762U, 21572U, + 149600U, 120694U, 119799U, 64040U, 197982U, 121044U, 120089U, 95352U, + 233409U, 121394U, 120379U, 45716U, 176876U, 120871U, 119946U, 82155U, + 218327U, 121221U, 120236U, 108415U, 247818U, 121571U, 120526U, 26838U, + 156083U, 67582U, 202341U, 98032U, 236706U, 50347U, 182521U, 85894U, + 222880U, 111262U, 251279U, 20507U, 148245U, 62975U, 196627U, 94287U, + 232054U, 44593U, 175463U, 81032U, 216914U, 107292U, 246405U, 25885U, + 154875U, 66629U, 201133U, 97079U, 235498U, 49343U, 181262U, 84890U, + 221621U, 110258U, 250020U, 21498U, 149506U, 120637U, 119752U, 63966U, + 197888U, 120987U, 120042U, 95278U, 233315U, 121337U, 120332U, 45638U, + 176778U, 120812U, 119897U, 82077U, 218229U, 121162U, 120187U, 108337U, + 247720U, 121512U, 120477U, 26764U, 155989U, 67508U, 202247U, 97958U, + 236612U, 50269U, 182423U, 85816U, 222782U, 111184U, 251181U, 21218U, + 149151U, 63686U, 197533U, 94998U, 232960U, 45343U, 176408U, 81782U, + 217859U, 108042U, 247350U, 26559U, 155729U, 67303U, 201987U, 97753U, + 236352U, 50053U, 182152U, 85600U, 222511U, 110968U, 250910U, 26275U, + 155370U, 67019U, 201628U, 97469U, 235993U, 49754U, 181778U, 85301U, + 222137U, 110669U, 250536U, 21048U, 148936U, 63516U, 197318U, 94828U, + 232745U, 45164U, 176184U, 81603U, 217635U, 107863U, 247126U, 26389U, + 155514U, 67133U, 201772U, 97583U, 236137U, 49874U, 181928U, 85421U, + 222287U, 110789U, 250686U, 20323U, 148034U, 62791U, 196416U, 94103U, + 231843U, 44399U, 175243U, 80838U, 216694U, 107098U, 246185U, 25777U, + 154760U, 66521U, 201018U, 96971U, 235383U, 49229U, 181142U, 84776U, + 221501U, 110144U, 249900U, 21259U, 149202U, 63727U, 197584U, 95039U, + 233011U, 45386U, 176461U, 81825U, 217912U, 108085U, 247403U, 26600U, + 155780U, 67344U, 202038U, 97794U, 236403U, 50096U, 182205U, 85643U, + 222564U, 111011U, 250963U, 21163U, 149081U, 63631U, 197463U, 94943U, + 232890U, 45285U, 176335U, 81724U, 217786U, 107984U, 247277U, 26504U, + 155659U, 67248U, 201917U, 97698U, 236282U, 49995U, 182079U, 85542U, + 222438U, 110910U, 250837U, 20775U, 148588U, 63243U, 196970U, 94555U, + 232397U, 44876U, 175821U, 81315U, 217272U, 107575U, 246763U, 26061U, + 155101U, 66805U, 201359U, 97255U, 235724U, 49529U, 181498U, 85076U, + 221857U, 110444U, 250256U, 19725U, 147401U, 62193U, 195783U, 93505U, + 231210U, 116183U, 256429U, 43770U, 174584U, 80209U, 216035U, 106469U, + 245526U, 19534U, 147165U, 62002U, 195547U, 93314U, 230974U, 115992U, + 256193U, 43570U, 174339U, 80009U, 215790U, 106269U, 245281U, 21029U, + 148912U, 63497U, 197294U, 94809U, 232721U, 45144U, 176159U, 81583U, + 217610U, 107843U, 247101U, 26370U, 155490U, 67114U, 201748U, 97564U, + 236113U, 49854U, 181903U, 85401U, 222262U, 110769U, 250661U, 21553U, + 149576U, 120665U, 119775U, 64021U, 197958U, 121015U, 120065U, 95333U, + 233385U, 121365U, 120355U, 45696U, 176851U, 120841U, 119921U, 82135U, + 218302U, 121191U, 120211U, 108395U, 247793U, 121541U, 120501U, 26819U, + 156059U, 67563U, 202317U, 98013U, 236682U, 50327U, 182496U, 85874U, + 222855U, 111242U, 251254U, 20090U, 147764U, 62558U, 196146U, 93870U, + 231573U, 44154U, 174962U, 80593U, 216413U, 106853U, 245904U, 25704U, + 154690U, 66448U, 200948U, 96898U, 235313U, 49152U, 181069U, 84699U, + 221428U, 110067U, 249827U, 21461U, 149459U, 120580U, 119705U, 63929U, + 197841U, 120930U, 119995U, 95241U, 233268U, 121280U, 120285U, 45599U, + 176729U, 120753U, 119848U, 82038U, 218180U, 121103U, 120138U, 108298U, + 247671U, 121453U, 120428U, 26746U, 155966U, 67490U, 202224U, 97940U, + 236589U, 50250U, 182399U, 85797U, 222758U, 111165U, 251157U, 18795U, + 146881U, 61263U, 195263U, 92575U, 230690U, 115328U, 256004U, 42809U, + 174043U, 79248U, 215494U, 105508U, 244985U, 20938U, 148796U, 63406U, + 197178U, 94718U, 232605U, 117184U, 257557U, 45048U, 176038U, 81487U, + 217489U, 107747U, 246980U, 26258U, 155348U, 67002U, 201606U, 97452U, + 235971U, 118753U, 259483U, 49736U, 181755U, 85283U, 222114U, 110651U, + 250513U, 7802U, 134135U, 53648U, 186345U, 87426U, 224613U, 112077U, + 252168U, 34583U, 164645U, 73320U, 208814U, 13311U, 140574U, 56949U, + 190176U, 88957U, 226402U, 112906U, 253142U, 39447U, 170278U, 17348U, + 145196U, 59576U, 193271U, 91111U, 228961U, 114100U, 254551U, 124379U, + 269626U, 270663U, 261014U, 262420U, 262368U, 262394U, 262446U, 270747U, + 261022U, 270716U, 119533U, 124474U, 269163U, 269372U, 269143U, 123029U, + 261809U, 260265U, 260136U, 269448U, 261935U, 260424U, 260580U, 123038U, + 261821U, 260280U, 260148U, 269457U, 261947U, 260439U, 260592U, 123211U, + 261902U, 260382U, 260229U, 269649U, 262028U, 260541U, 260673U, 123244U, + 261915U, 260398U, 260242U, 269673U, 262041U, 260557U, 260686U, 123191U, + 261889U, 260366U, 260216U, 269639U, 262015U, 260525U, 260660U, 123093U, + 261833U, 260295U, 260160U, 269576U, 261959U, 260454U, 260604U, 123132U, + 261866U, 260337U, 260193U, 269600U, 261992U, 260496U, 260637U, 123111U, + 261845U, 260310U, 260172U, 269585U, 261971U, 260469U, 260616U, 123140U, + 261877U, 260351U, 260204U, 269608U, 262003U, 260510U, 260648U, 121660U, + 124481U, 261278U, 119409U, 262207U, 124563U, 262620U, 269331U, 262630U, + 269342U, 262053U, 263660U, 124611U, 261581U, 269288U, 123378U, 263773U, + 263964U, 124638U, 263310U, 263853U, 261603U, 262237U, 262276U, 123418U, + 263265U, 124600U, 260768U, 124161U, 262212U, 270634U, 269433U, 269869U, + 263969U, 261651U, 269293U, 119171U, 119178U, 119522U, 124137U, 269127U, + 119426U, 124130U, 269108U, 119420U, 124465U, 262567U, 124593U, 269304U, + 124918U, 270652U, 269438U, 119627U, 124472U, 261689U, 261445U, 269161U, + 261533U, 25U, 261640U, 269141U, 263424U, 121664U, 124479U, 270645U, + 270627U, 124996U, 121617U, 261700U, 269214U, 261730U, 121796U, 261715U, + 269315U, 261745U, 124986U, 259904U, 262200U, 262195U, 121633U, 261708U, + 124549U, 263447U, 124617U, 263457U, 269255U, 261738U, 263959U, 263479U, + 261634U, 263468U, 262328U, 121812U, 261723U, 124506U, 263396U, 263435U, + 124452U, 263382U, 124513U, 263410U, 119276U, 269120U, 269355U, 261753U, + 261626U, 262284U, 263927U, 263863U, 269416U, 269428U, 263221U, 124998U, + 260014U, 123005U, 124249U, 262885U, 123149U, 124334U, 262988U, 124273U, + 260816U, 263806U, 262909U, 269466U, 263878U, 123053U, 260825U, 263816U, + 262933U, 269567U, 263888U, 123181U, 124392U, 263011U, 123077U, 124303U, + 262957U, 123158U, 124343U, 260834U, 263826U, 269617U, 263898U, 123201U, + 124402U, 263021U, 123228U, 124419U, 263038U, 123221U, 124412U, 263031U, + 123301U, 124964U, 261554U, 123121U, 124328U, 262982U, 121619U, 123047U, + 124282U, 262918U, 124157U, 123167U, 124352U, 262997U, 269210U, 123012U, + 124256U, 262892U, 123237U, 124428U, 263047U, 123086U, 124312U, 262966U, + 122983U, 124232U, 262868U, 123070U, 124296U, 262950U, 270573U, 270581U, + 270605U, 123262U, 124444U, 269695U, 123020U, 124264U, 262900U, 122991U, + 124240U, 262876U, 121798U, 123102U, 124319U, 262973U, 123253U, 124435U, + 263054U, 123062U, 124288U, 262942U, 124206U, 260698U, 269245U, 123173U, + 124358U, 263003U, 262470U, 124579U, 269187U, 269310U, 122976U, 124225U, + 262861U, 269317U, 119415U, 124459U, 269154U, 269135U, 263919U, 124632U, + 269193U, 269422U, 119317U, 124980U, 270706U, 124990U, 262492U, 98105U, + 263071U, 263913U, 259906U, 262202U, 119197U, 263769U, 121620U, 124158U, + 263780U, 123127U, 261858U, 260326U, 260185U, 269595U, 261984U, 260485U, + 260629U, 124619U, 269211U, 263874U, 269716U, 263908U, 261330U, 263841U, + 263226U, 260722U, 124163U, 263846U, 263778U, 269250U, 262221U, 119186U, + 124570U, 261456U, 125005U, 124145U, 263800U, 269403U, 269200U, 260846U, + 263836U, 269410U, 269269U, 27070U, 67822U, 260120U, 269235U, 262233U, + 124569U, 269181U, 269299U, 119229U, 123000U, 261801U, 260254U, 260128U, + 269443U, 261927U, 260413U, 260572U, 121799U, 119232U, 124219U, 119156U, + 124207U, 119530U, 269369U, 119537U, 269378U, 119544U, 269387U, 259977U, + 124500U, 269208U, 260116U, 124508U, 269396U, 269169U, 269230U, 263355U, + 124606U, 263794U, 263858U, 119167U, 124454U, 269148U, 269115U, 263231U, + 260124U, 124515U, 269175U, 269240U, 119241U, 269122U, 269318U, 261628U, + 259975U, 124498U, 269206U, 263236U, 264584U, 270314U, 264227U, 269992U, + 260920U, 261112U, 261174U, 124688U, 264284U, 270019U, 122136U, 122711U, + 121826U, 122437U, 121981U, 122574U, 122291U, 122848U, 122153U, 122726U, + 121843U, 122452U, 121998U, 122589U, 122307U, 122862U, 122274U, 122833U, + 121964U, 122559U, 122119U, 122696U, 122421U, 122962U, 122256U, 122817U, + 121946U, 122543U, 122101U, 122680U, 122404U, 122947U, 122170U, 122741U, + 121860U, 122467U, 122015U, 122604U, 122323U, 122876U, 122238U, 122801U, + 121928U, 122527U, 122083U, 122664U, 122387U, 122932U, 122205U, 122772U, + 121895U, 122498U, 122050U, 122635U, 122356U, 122905U, 122187U, 122756U, + 121877U, 122482U, 122032U, 122619U, 122339U, 122890U, 122221U, 122786U, + 121911U, 122512U, 122066U, 122649U, 122371U, 122918U, 124696U, 264311U, + 270036U, 264543U, 270273U, 264007U, 269891U, 261132U, 261226U, 264706U, + 270462U, 264733U, 270480U, 123751U, 264236U, 269029U, 269048U, 269083U, + 268840U, 268900U, 268813U, 268875U, 123924U, 264724U, 261234U, 123707U, + 264155U, 123760U, 264245U, 123943U, 264741U, 260898U, 123847U, 264452U, + 123663U, 264092U, 123622U, 264025U, 123828U, 264399U, 262924U, 123983U, + 123992U, 269492U, 269659U, 269682U, 269475U, 269519U, 269550U, 269505U, + 269537U, 123717U, 264165U, 123770U, 264255U, 123673U, 264102U, 123632U, + 264035U, 123933U, 267530U, 262838U, 262757U, 262703U, 262730U, 267539U, + 123643U, 123856U, 264469U, 123952U, 264758U, 123818U, 264364U, 123867U, + 123883U, 269039U, 123613U, 264016U, 123781U, 264292U, 123973U, 264797U, + 268800U, 269061U, 269095U, 268857U, 268916U, 268826U, 268887U, 123740U, + 264197U, 123696U, 264135U, 123837U, 264425U, 123728U, 264176U, 123684U, + 264123U, 262716U, 262743U, 123653U, 264073U, 123963U, 264778U, 268370U, + 261194U, 267000U, 265224U, 266112U, 267879U, 267010U, 265234U, 266122U, + 267888U, 267020U, 265244U, 266132U, 267897U, 267030U, 265254U, 266142U, + 267906U, 268690U, 266992U, 268474U, 265216U, 268582U, 266104U, 268791U, + 267872U, 268933U, 267486U, 265710U, 266598U, 268330U, 267066U, 265290U, + 266178U, 267938U, 267126U, 265350U, 266238U, 267994U, 267186U, 265410U, + 266298U, 268050U, 267246U, 265470U, 266358U, 268106U, 267306U, 265530U, + 266418U, 268162U, 267366U, 265590U, 266478U, 268218U, 267426U, 265650U, + 266538U, 268274U, 267040U, 265264U, 266152U, 267915U, 268592U, 266642U, + 268376U, 264866U, 268484U, 265754U, 268700U, 267550U, 268606U, 266692U, + 268390U, 264916U, 268498U, 265804U, 268713U, 267596U, 268620U, 266742U, + 268404U, 264966U, 268512U, 265854U, 268726U, 267642U, 268634U, 266792U, + 268418U, 265016U, 268526U, 265904U, 268739U, 267688U, 268648U, 266842U, + 268432U, 265066U, 268540U, 265954U, 268752U, 267734U, 268662U, 266892U, + 268446U, 265116U, 268554U, 266004U, 268765U, 267780U, 268676U, 266942U, + 268460U, 265166U, 268568U, 266054U, 268778U, 267826U, 266654U, 264878U, + 265766U, 267561U, 266704U, 264928U, 265816U, 267607U, 266754U, 264978U, + 265866U, 267653U, 266804U, 265028U, 265916U, 267699U, 266854U, 265078U, + 265966U, 267745U, 266904U, 265128U, 266016U, 267791U, 266954U, 265178U, + 266066U, 267837U, 267508U, 265732U, 266620U, 268350U, 267096U, 265320U, + 266208U, 267966U, 267156U, 265380U, 266268U, 268022U, 267216U, 265440U, + 266328U, 268078U, 267276U, 265500U, 266388U, 268134U, 267336U, 265560U, + 266448U, 268190U, 267396U, 265620U, 266508U, 268246U, 267456U, 265680U, + 266568U, 268302U, 264188U, 269964U, 124670U, 260910U, 264218U, 261102U, + 269983U, 261164U, 264266U, 270001U, 260959U, 260940U, 264715U, 270471U, + 264750U, 270488U, 260929U, 261121U, 261183U, 123897U, 264480U, 123791U, + 123906U, 123800U, 264319U, 123915U, 264525U, 123809U, 264337U, 264653U, + 270399U, 264461U, 270145U, 260949U, 260986U, 260969U, 260978U, 264146U, + 261083U, 269955U, 261145U, 261202U, 124788U, 264489U, 270207U, 124884U, + 270442U, 124824U, 270255U, 261210U, 124874U, 264614U, 270360U, 124719U, + 264328U, 270059U, 264696U, 270452U, 264534U, 270264U, 124728U, 264346U, + 270068U, 261218U, 264674U, 270420U, 264624U, 270370U, 264355U, 270077U, + 264417U, 270120U, 268958U, 268979U, 269000U, 269021U, 270589U, 124972U, + 269075U, 270597U, 263063U, 260995U, 261005U, 124953U, 264855U, 270562U, + 124943U, 264825U, 270532U, 264113U, 269945U, 264046U, 269900U, 124925U, + 264769U, 270496U, 124934U, 264816U, 270523U, 124809U, 264510U, 270228U, + 262669U, 262826U, 262850U, 262814U, 262769U, 262780U, 262680U, 262790U, + 264644U, 270390U, 264444U, 270137U, 263974U, 124797U, 264498U, 270216U, + 124661U, 269910U, 268945U, 268966U, 268987U, 269008U, 124848U, 264594U, + 270324U, 124679U, 264275U, 270010U, 261093U, 261155U, 267058U, 265282U, + 266170U, 267931U, 124526U, 260796U, 124541U, 50424U, 85971U, 111339U, + 270153U, 270182U, 124762U, 270168U, 124776U, 270195U, 124737U, 264374U, + 270086U, 264408U, 270111U, 268939U, 267497U, 265721U, 266609U, 268340U, + 267081U, 265305U, 266193U, 267952U, 267141U, 265365U, 266253U, 268008U, + 267201U, 265425U, 266313U, 268064U, 267261U, 265485U, 266373U, 268120U, + 267321U, 265545U, 266433U, 268176U, 267381U, 265605U, 266493U, 268232U, + 267441U, 265665U, 266553U, 268288U, 124653U, 263999U, 269883U, 124754U, + 264391U, 270103U, 267049U, 265273U, 266161U, 267923U, 266680U, 264904U, + 265792U, 267585U, 266730U, 264954U, 265842U, 267631U, 266780U, 265004U, + 265892U, 267677U, 266830U, 265054U, 265942U, 267723U, 266880U, 265104U, + 265992U, 267769U, 266930U, 265154U, 266042U, 267815U, 266980U, 265204U, + 266092U, 267861U, 124644U, 263990U, 269874U, 124745U, 264382U, 270094U, + 266667U, 264891U, 265779U, 267573U, 266717U, 264941U, 265829U, 267619U, + 266767U, 264991U, 265879U, 267665U, 266817U, 265041U, 265929U, 267711U, + 266867U, 265091U, 265979U, 267757U, 266917U, 265141U, 266029U, 267803U, + 266967U, 265191U, 266079U, 267849U, 264553U, 270283U, 264056U, 269919U, + 264065U, 269928U, 267519U, 265743U, 266631U, 268360U, 267111U, 265335U, + 266223U, 267980U, 267171U, 265395U, 266283U, 268036U, 267231U, 265455U, + 266343U, 268092U, 267291U, 265515U, 266403U, 268148U, 267351U, 265575U, + 266463U, 268204U, 267411U, 265635U, 266523U, 268260U, 267471U, 265695U, + 266583U, 268316U, 264604U, 270334U, 264845U, 270552U, 264302U, 270027U, + 264807U, 270514U, 264662U, 270408U, 270243U, 264573U, 270303U, 264208U, + 269973U, 264685U, 270431U, 264634U, 270380U, 264435U, 270128U, 262801U, + 262691U, 264563U, 270293U, 264835U, 270542U, 264083U, 269936U, 264788U, + 270505U, 124816U, 264517U, 270235U, 50434U, 85981U, 111349U, 124486U, + 262219U, 262280U, 124574U, 119200U, 124193U, 261422U, 269274U, 27080U, + 67832U, +}; + +#endif // GET_INSTRINFO_MC_DESC diff --git a/arch/RISCV/RISCVGenInsnNameMaps.inc b/arch/RISCV/RISCVGenInsnNameMaps.inc index 17d42bf9cc..5061e6accf 100644 --- a/arch/RISCV/RISCVGenInsnNameMaps.inc +++ b/arch/RISCV/RISCVGenInsnNameMaps.inc @@ -1,275 +1,154 @@ // This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh - { RISCV_INS_ADD, "add" }, - { RISCV_INS_ADDI, "addi" }, - { RISCV_INS_ADDIW, "addiw" }, - { RISCV_INS_ADDW, "addw" }, - { RISCV_INS_AMOADD_D, "amoadd.d" }, - { RISCV_INS_AMOADD_D_AQ, "amoadd.d.aq" }, - { RISCV_INS_AMOADD_D_AQ_RL, "amoadd.d.aqrl" }, - { RISCV_INS_AMOADD_D_RL, "amoadd.d.rl" }, - { RISCV_INS_AMOADD_W, "amoadd.w" }, - { RISCV_INS_AMOADD_W_AQ, "amoadd.w.aq" }, - { RISCV_INS_AMOADD_W_AQ_RL, "amoadd.w.aqrl" }, - { RISCV_INS_AMOADD_W_RL, "amoadd.w.rl" }, - { RISCV_INS_AMOAND_D, "amoand.d" }, - { RISCV_INS_AMOAND_D_AQ, "amoand.d.aq" }, - { RISCV_INS_AMOAND_D_AQ_RL, "amoand.d.aqrl" }, - { RISCV_INS_AMOAND_D_RL, "amoand.d.rl" }, - { RISCV_INS_AMOAND_W, "amoand.w" }, - { RISCV_INS_AMOAND_W_AQ, "amoand.w.aq" }, - { RISCV_INS_AMOAND_W_AQ_RL, "amoand.w.aqrl" }, - { RISCV_INS_AMOAND_W_RL, "amoand.w.rl" }, - { RISCV_INS_AMOMAXU_D, "amomaxu.d" }, - { RISCV_INS_AMOMAXU_D_AQ, "amomaxu.d.aq" }, - { RISCV_INS_AMOMAXU_D_AQ_RL, "amomaxu.d.aqrl" }, - { RISCV_INS_AMOMAXU_D_RL, "amomaxu.d.rl" }, - { RISCV_INS_AMOMAXU_W, "amomaxu.w" }, - { RISCV_INS_AMOMAXU_W_AQ, "amomaxu.w.aq" }, - { RISCV_INS_AMOMAXU_W_AQ_RL, "amomaxu.w.aqrl" }, - { RISCV_INS_AMOMAXU_W_RL, "amomaxu.w.rl" }, - { RISCV_INS_AMOMAX_D, "amomax.d" }, - { RISCV_INS_AMOMAX_D_AQ, "amomax.d.aq" }, - { RISCV_INS_AMOMAX_D_AQ_RL, "amomax.d.aqrl" }, - { RISCV_INS_AMOMAX_D_RL, "amomax.d.rl" }, - { RISCV_INS_AMOMAX_W, "amomax.w" }, - { RISCV_INS_AMOMAX_W_AQ, "amomax.w.aq" }, - { RISCV_INS_AMOMAX_W_AQ_RL, "amomax.w.aqrl" }, - { RISCV_INS_AMOMAX_W_RL, "amomax.w.rl" }, - { RISCV_INS_AMOMINU_D, "amominu.d" }, - { RISCV_INS_AMOMINU_D_AQ, "amominu.d.aq" }, - { RISCV_INS_AMOMINU_D_AQ_RL, "amominu.d.aqrl" }, - { RISCV_INS_AMOMINU_D_RL, "amominu.d.rl" }, - { RISCV_INS_AMOMINU_W, "amominu.w" }, - { RISCV_INS_AMOMINU_W_AQ, "amominu.w.aq" }, - { RISCV_INS_AMOMINU_W_AQ_RL, "amominu.w.aqrl" }, - { RISCV_INS_AMOMINU_W_RL, "amominu.w.rl" }, - { RISCV_INS_AMOMIN_D, "amomin.d" }, - { RISCV_INS_AMOMIN_D_AQ, "amomin.d.aq" }, - { RISCV_INS_AMOMIN_D_AQ_RL, "amomin.d.aqrl" }, - { RISCV_INS_AMOMIN_D_RL, "amomin.d.rl" }, - { RISCV_INS_AMOMIN_W, "amomin.w" }, - { RISCV_INS_AMOMIN_W_AQ, "amomin.w.aq" }, - { RISCV_INS_AMOMIN_W_AQ_RL, "amomin.w.aqrl" }, - { RISCV_INS_AMOMIN_W_RL, "amomin.w.rl" }, - { RISCV_INS_AMOOR_D, "amoor.d" }, - { RISCV_INS_AMOOR_D_AQ, "amoor.d.aq" }, - { RISCV_INS_AMOOR_D_AQ_RL, "amoor.d.aqrl" }, - { RISCV_INS_AMOOR_D_RL, "amoor.d.rl" }, - { RISCV_INS_AMOOR_W, "amoor.w" }, - { RISCV_INS_AMOOR_W_AQ, "amoor.w.aq" }, - { RISCV_INS_AMOOR_W_AQ_RL, "amoor.w.aqrl" }, - { RISCV_INS_AMOOR_W_RL, "amoor.w.rl" }, - { RISCV_INS_AMOSWAP_D, "amoswap.d" }, - { RISCV_INS_AMOSWAP_D_AQ, "amoswap.d.aq" }, - { RISCV_INS_AMOSWAP_D_AQ_RL, "amoswap.d.aqrl" }, - { RISCV_INS_AMOSWAP_D_RL, "amoswap.d.rl" }, - { RISCV_INS_AMOSWAP_W, "amoswap.w" }, - { RISCV_INS_AMOSWAP_W_AQ, "amoswap.w.aq" }, - { RISCV_INS_AMOSWAP_W_AQ_RL, "amoswap.w.aqrl" }, - { RISCV_INS_AMOSWAP_W_RL, "amoswap.w.rl" }, - { RISCV_INS_AMOXOR_D, "amoxor.d" }, - { RISCV_INS_AMOXOR_D_AQ, "amoxor.d.aq" }, - { RISCV_INS_AMOXOR_D_AQ_RL, "amoxor.d.aqrl" }, - { RISCV_INS_AMOXOR_D_RL, "amoxor.d.rl" }, - { RISCV_INS_AMOXOR_W, "amoxor.w" }, - { RISCV_INS_AMOXOR_W_AQ, "amoxor.w.aq" }, - { RISCV_INS_AMOXOR_W_AQ_RL, "amoxor.w.aqrl" }, - { RISCV_INS_AMOXOR_W_RL, "amoxor.w.rl" }, - { RISCV_INS_AND, "and" }, - { RISCV_INS_ANDI, "andi" }, - { RISCV_INS_AUIPC, "auipc" }, - { RISCV_INS_BEQ, "beq" }, - { RISCV_INS_BGE, "bge" }, - { RISCV_INS_BGEU, "bgeu" }, - { RISCV_INS_BLT, "blt" }, - { RISCV_INS_BLTU, "bltu" }, - { RISCV_INS_BNE, "bne" }, - { RISCV_INS_CSRRC, "csrrc" }, - { RISCV_INS_CSRRCI, "csrrci" }, - { RISCV_INS_CSRRS, "csrrs" }, - { RISCV_INS_CSRRSI, "csrrsi" }, - { RISCV_INS_CSRRW, "csrrw" }, - { RISCV_INS_CSRRWI, "csrrwi" }, - { RISCV_INS_C_ADD, "c.add" }, - { RISCV_INS_C_ADDI, "c.addi" }, - { RISCV_INS_C_ADDI16SP, "c.addi16sp" }, - { RISCV_INS_C_ADDI4SPN, "c.addi4spn" }, - { RISCV_INS_C_ADDIW, "c.addiw" }, - { RISCV_INS_C_ADDW, "c.addw" }, - { RISCV_INS_C_AND, "c.and" }, - { RISCV_INS_C_ANDI, "c.andi" }, - { RISCV_INS_C_BEQZ, "c.beqz" }, - { RISCV_INS_C_BNEZ, "c.bnez" }, - { RISCV_INS_C_EBREAK, "c.ebreak" }, - { RISCV_INS_C_FLD, "c.fld" }, - { RISCV_INS_C_FLDSP, "c.fldsp" }, - { RISCV_INS_C_FLW, "c.flw" }, - { RISCV_INS_C_FLWSP, "c.flwsp" }, - { RISCV_INS_C_FSD, "c.fsd" }, - { RISCV_INS_C_FSDSP, "c.fsdsp" }, - { RISCV_INS_C_FSW, "c.fsw" }, - { RISCV_INS_C_FSWSP, "c.fswsp" }, - { RISCV_INS_C_J, "c.j" }, - { RISCV_INS_C_JAL, "c.jal" }, - { RISCV_INS_C_JALR, "c.jalr" }, - { RISCV_INS_C_JR, "c.jr" }, - { RISCV_INS_C_LD, "c.ld" }, - { RISCV_INS_C_LDSP, "c.ldsp" }, - { RISCV_INS_C_LI, "c.li" }, - { RISCV_INS_C_LUI, "c.lui" }, - { RISCV_INS_C_LW, "c.lw" }, - { RISCV_INS_C_LWSP, "c.lwsp" }, - { RISCV_INS_C_MV, "c.mv" }, - { RISCV_INS_C_NOP, "c.nop" }, - { RISCV_INS_C_OR, "c.or" }, - { RISCV_INS_C_SD, "c.sd" }, - { RISCV_INS_C_SDSP, "c.sdsp" }, - { RISCV_INS_C_SLLI, "c.slli" }, - { RISCV_INS_C_SRAI, "c.srai" }, - { RISCV_INS_C_SRLI, "c.srli" }, - { RISCV_INS_C_SUB, "c.sub" }, - { RISCV_INS_C_SUBW, "c.subw" }, - { RISCV_INS_C_SW, "c.sw" }, - { RISCV_INS_C_SWSP, "c.swsp" }, - { RISCV_INS_C_UNIMP, "c.unimp" }, - { RISCV_INS_C_XOR, "c.xor" }, - { RISCV_INS_DIV, "div" }, - { RISCV_INS_DIVU, "divu" }, - { RISCV_INS_DIVUW, "divuw" }, - { RISCV_INS_DIVW, "divw" }, - { RISCV_INS_EBREAK, "ebreak" }, - { RISCV_INS_ECALL, "ecall" }, - { RISCV_INS_FADD_D, "fadd.d" }, - { RISCV_INS_FADD_S, "fadd.s" }, - { RISCV_INS_FCLASS_D, "fclass.d" }, - { RISCV_INS_FCLASS_S, "fclass.s" }, - { RISCV_INS_FCVT_D_L, "fcvt.d.l" }, - { RISCV_INS_FCVT_D_LU, "fcvt.d.lu" }, - { RISCV_INS_FCVT_D_S, "fcvt.d.s" }, - { RISCV_INS_FCVT_D_W, "fcvt.d.w" }, - { RISCV_INS_FCVT_D_WU, "fcvt.d.wu" }, - { RISCV_INS_FCVT_LU_D, "fcvt.lu.d" }, - { RISCV_INS_FCVT_LU_S, "fcvt.lu.s" }, - { RISCV_INS_FCVT_L_D, "fcvt.l.d" }, - { RISCV_INS_FCVT_L_S, "fcvt.l.s" }, - { RISCV_INS_FCVT_S_D, "fcvt.s.d" }, - { RISCV_INS_FCVT_S_L, "fcvt.s.l" }, - { RISCV_INS_FCVT_S_LU, "fcvt.s.lu" }, - { RISCV_INS_FCVT_S_W, "fcvt.s.w" }, - { RISCV_INS_FCVT_S_WU, "fcvt.s.wu" }, - { RISCV_INS_FCVT_WU_D, "fcvt.wu.d" }, - { RISCV_INS_FCVT_WU_S, "fcvt.wu.s" }, - { RISCV_INS_FCVT_W_D, "fcvt.w.d" }, - { RISCV_INS_FCVT_W_S, "fcvt.w.s" }, - { RISCV_INS_FDIV_D, "fdiv.d" }, - { RISCV_INS_FDIV_S, "fdiv.s" }, - { RISCV_INS_FENCE, "fence" }, - { RISCV_INS_FENCE_I, "fence.i" }, - { RISCV_INS_FENCE_TSO, "fence.tso" }, - { RISCV_INS_FEQ_D, "feq.d" }, - { RISCV_INS_FEQ_S, "feq.s" }, - { RISCV_INS_FLD, "fld" }, - { RISCV_INS_FLE_D, "fle.d" }, - { RISCV_INS_FLE_S, "fle.s" }, - { RISCV_INS_FLT_D, "flt.d" }, - { RISCV_INS_FLT_S, "flt.s" }, - { RISCV_INS_FLW, "flw" }, - { RISCV_INS_FMADD_D, "fmadd.d" }, - { RISCV_INS_FMADD_S, "fmadd.s" }, - { RISCV_INS_FMAX_D, "fmax.d" }, - { RISCV_INS_FMAX_S, "fmax.s" }, - { RISCV_INS_FMIN_D, "fmin.d" }, - { RISCV_INS_FMIN_S, "fmin.s" }, - { RISCV_INS_FMSUB_D, "fmsub.d" }, - { RISCV_INS_FMSUB_S, "fmsub.s" }, - { RISCV_INS_FMUL_D, "fmul.d" }, - { RISCV_INS_FMUL_S, "fmul.s" }, - { RISCV_INS_FMV_D_X, "fmv.d.x" }, - { RISCV_INS_FMV_W_X, "fmv.w.x" }, - { RISCV_INS_FMV_X_D, "fmv.x.d" }, - { RISCV_INS_FMV_X_W, "fmv.x.w" }, - { RISCV_INS_FNMADD_D, "fnmadd.d" }, - { RISCV_INS_FNMADD_S, "fnmadd.s" }, - { RISCV_INS_FNMSUB_D, "fnmsub.d" }, - { RISCV_INS_FNMSUB_S, "fnmsub.s" }, - { RISCV_INS_FSD, "fsd" }, - { RISCV_INS_FSGNJN_D, "fsgnjn.d" }, - { RISCV_INS_FSGNJN_S, "fsgnjn.s" }, - { RISCV_INS_FSGNJX_D, "fsgnjx.d" }, - { RISCV_INS_FSGNJX_S, "fsgnjx.s" }, - { RISCV_INS_FSGNJ_D, "fsgnj.d" }, - { RISCV_INS_FSGNJ_S, "fsgnj.s" }, - { RISCV_INS_FSQRT_D, "fsqrt.d" }, - { RISCV_INS_FSQRT_S, "fsqrt.s" }, - { RISCV_INS_FSUB_D, "fsub.d" }, - { RISCV_INS_FSUB_S, "fsub.s" }, - { RISCV_INS_FSW, "fsw" }, - { RISCV_INS_JAL, "jal" }, - { RISCV_INS_JALR, "jalr" }, - { RISCV_INS_LB, "lb" }, - { RISCV_INS_LBU, "lbu" }, - { RISCV_INS_LD, "ld" }, - { RISCV_INS_LH, "lh" }, - { RISCV_INS_LHU, "lhu" }, - { RISCV_INS_LR_D, "lr.d" }, - { RISCV_INS_LR_D_AQ, "lr.d.aq" }, - { RISCV_INS_LR_D_AQ_RL, "lr.d.aqrl" }, - { RISCV_INS_LR_D_RL, "lr.d.rl" }, - { RISCV_INS_LR_W, "lr.w" }, - { RISCV_INS_LR_W_AQ, "lr.w.aq" }, - { RISCV_INS_LR_W_AQ_RL, "lr.w.aqrl" }, - { RISCV_INS_LR_W_RL, "lr.w.rl" }, - { RISCV_INS_LUI, "lui" }, - { RISCV_INS_LW, "lw" }, - { RISCV_INS_LWU, "lwu" }, - { RISCV_INS_MRET, "mret" }, - { RISCV_INS_MUL, "mul" }, - { RISCV_INS_MULH, "mulh" }, - { RISCV_INS_MULHSU, "mulhsu" }, - { RISCV_INS_MULHU, "mulhu" }, - { RISCV_INS_MULW, "mulw" }, - { RISCV_INS_OR, "or" }, - { RISCV_INS_ORI, "ori" }, - { RISCV_INS_REM, "rem" }, - { RISCV_INS_REMU, "remu" }, - { RISCV_INS_REMUW, "remuw" }, - { RISCV_INS_REMW, "remw" }, - { RISCV_INS_SB, "sb" }, - { RISCV_INS_SC_D, "sc.d" }, - { RISCV_INS_SC_D_AQ, "sc.d.aq" }, - { RISCV_INS_SC_D_AQ_RL, "sc.d.aqrl" }, - { RISCV_INS_SC_D_RL, "sc.d.rl" }, - { RISCV_INS_SC_W, "sc.w" }, - { RISCV_INS_SC_W_AQ, "sc.w.aq" }, - { RISCV_INS_SC_W_AQ_RL, "sc.w.aqrl" }, - { RISCV_INS_SC_W_RL, "sc.w.rl" }, - { RISCV_INS_SD, "sd" }, - { RISCV_INS_SFENCE_VMA, "sfence.vma" }, - { RISCV_INS_SH, "sh" }, - { RISCV_INS_SLL, "sll" }, - { RISCV_INS_SLLI, "slli" }, - { RISCV_INS_SLLIW, "slliw" }, - { RISCV_INS_SLLW, "sllw" }, - { RISCV_INS_SLT, "slt" }, - { RISCV_INS_SLTI, "slti" }, - { RISCV_INS_SLTIU, "sltiu" }, - { RISCV_INS_SLTU, "sltu" }, - { RISCV_INS_SRA, "sra" }, - { RISCV_INS_SRAI, "srai" }, - { RISCV_INS_SRAIW, "sraiw" }, - { RISCV_INS_SRAW, "sraw" }, - { RISCV_INS_SRET, "sret" }, - { RISCV_INS_SRL, "srl" }, - { RISCV_INS_SRLI, "srli" }, - { RISCV_INS_SRLIW, "srliw" }, - { RISCV_INS_SRLW, "srlw" }, - { RISCV_INS_SUB, "sub" }, - { RISCV_INS_SUBW, "subw" }, - { RISCV_INS_SW, "sw" }, - { RISCV_INS_UNIMP, "unimp" }, - { RISCV_INS_URET, "uret" }, - { RISCV_INS_WFI, "wfi" }, - { RISCV_INS_XOR, "xor" }, - { RISCV_INS_XORI, "xori" }, +{RISCV_INS_ADD, "add"}, {RISCV_INS_ADDI, "addi"}, {RISCV_INS_ADDIW, "addiw"}, + {RISCV_INS_ADDW, "addw"}, {RISCV_INS_AMOADD_D, "amoadd.d"}, + {RISCV_INS_AMOADD_D_AQ, "amoadd.d.aq"}, + {RISCV_INS_AMOADD_D_AQ_RL, "amoadd.d.aqrl"}, + {RISCV_INS_AMOADD_D_RL, "amoadd.d.rl"}, {RISCV_INS_AMOADD_W, "amoadd.w"}, + {RISCV_INS_AMOADD_W_AQ, "amoadd.w.aq"}, + {RISCV_INS_AMOADD_W_AQ_RL, "amoadd.w.aqrl"}, + {RISCV_INS_AMOADD_W_RL, "amoadd.w.rl"}, {RISCV_INS_AMOAND_D, "amoand.d"}, + {RISCV_INS_AMOAND_D_AQ, "amoand.d.aq"}, + {RISCV_INS_AMOAND_D_AQ_RL, "amoand.d.aqrl"}, + {RISCV_INS_AMOAND_D_RL, "amoand.d.rl"}, {RISCV_INS_AMOAND_W, "amoand.w"}, + {RISCV_INS_AMOAND_W_AQ, "amoand.w.aq"}, + {RISCV_INS_AMOAND_W_AQ_RL, "amoand.w.aqrl"}, + {RISCV_INS_AMOAND_W_RL, "amoand.w.rl"}, {RISCV_INS_AMOMAXU_D, "amomaxu.d"}, + {RISCV_INS_AMOMAXU_D_AQ, "amomaxu.d.aq"}, + {RISCV_INS_AMOMAXU_D_AQ_RL, "amomaxu.d.aqrl"}, + {RISCV_INS_AMOMAXU_D_RL, "amomaxu.d.rl"}, + {RISCV_INS_AMOMAXU_W, "amomaxu.w"}, + {RISCV_INS_AMOMAXU_W_AQ, "amomaxu.w.aq"}, + {RISCV_INS_AMOMAXU_W_AQ_RL, "amomaxu.w.aqrl"}, + {RISCV_INS_AMOMAXU_W_RL, "amomaxu.w.rl"}, {RISCV_INS_AMOMAX_D, "amomax.d"}, + {RISCV_INS_AMOMAX_D_AQ, "amomax.d.aq"}, + {RISCV_INS_AMOMAX_D_AQ_RL, "amomax.d.aqrl"}, + {RISCV_INS_AMOMAX_D_RL, "amomax.d.rl"}, {RISCV_INS_AMOMAX_W, "amomax.w"}, + {RISCV_INS_AMOMAX_W_AQ, "amomax.w.aq"}, + {RISCV_INS_AMOMAX_W_AQ_RL, "amomax.w.aqrl"}, + {RISCV_INS_AMOMAX_W_RL, "amomax.w.rl"}, {RISCV_INS_AMOMINU_D, "amominu.d"}, + {RISCV_INS_AMOMINU_D_AQ, "amominu.d.aq"}, + {RISCV_INS_AMOMINU_D_AQ_RL, "amominu.d.aqrl"}, + {RISCV_INS_AMOMINU_D_RL, "amominu.d.rl"}, + {RISCV_INS_AMOMINU_W, "amominu.w"}, + {RISCV_INS_AMOMINU_W_AQ, "amominu.w.aq"}, + {RISCV_INS_AMOMINU_W_AQ_RL, "amominu.w.aqrl"}, + {RISCV_INS_AMOMINU_W_RL, "amominu.w.rl"}, {RISCV_INS_AMOMIN_D, "amomin.d"}, + {RISCV_INS_AMOMIN_D_AQ, "amomin.d.aq"}, + {RISCV_INS_AMOMIN_D_AQ_RL, "amomin.d.aqrl"}, + {RISCV_INS_AMOMIN_D_RL, "amomin.d.rl"}, {RISCV_INS_AMOMIN_W, "amomin.w"}, + {RISCV_INS_AMOMIN_W_AQ, "amomin.w.aq"}, + {RISCV_INS_AMOMIN_W_AQ_RL, "amomin.w.aqrl"}, + {RISCV_INS_AMOMIN_W_RL, "amomin.w.rl"}, {RISCV_INS_AMOOR_D, "amoor.d"}, + {RISCV_INS_AMOOR_D_AQ, "amoor.d.aq"}, + {RISCV_INS_AMOOR_D_AQ_RL, "amoor.d.aqrl"}, + {RISCV_INS_AMOOR_D_RL, "amoor.d.rl"}, {RISCV_INS_AMOOR_W, "amoor.w"}, + {RISCV_INS_AMOOR_W_AQ, "amoor.w.aq"}, + {RISCV_INS_AMOOR_W_AQ_RL, "amoor.w.aqrl"}, + {RISCV_INS_AMOOR_W_RL, "amoor.w.rl"}, {RISCV_INS_AMOSWAP_D, "amoswap.d"}, + {RISCV_INS_AMOSWAP_D_AQ, "amoswap.d.aq"}, + {RISCV_INS_AMOSWAP_D_AQ_RL, "amoswap.d.aqrl"}, + {RISCV_INS_AMOSWAP_D_RL, "amoswap.d.rl"}, + {RISCV_INS_AMOSWAP_W, "amoswap.w"}, + {RISCV_INS_AMOSWAP_W_AQ, "amoswap.w.aq"}, + {RISCV_INS_AMOSWAP_W_AQ_RL, "amoswap.w.aqrl"}, + {RISCV_INS_AMOSWAP_W_RL, "amoswap.w.rl"}, {RISCV_INS_AMOXOR_D, "amoxor.d"}, + {RISCV_INS_AMOXOR_D_AQ, "amoxor.d.aq"}, + {RISCV_INS_AMOXOR_D_AQ_RL, "amoxor.d.aqrl"}, + {RISCV_INS_AMOXOR_D_RL, "amoxor.d.rl"}, {RISCV_INS_AMOXOR_W, "amoxor.w"}, + {RISCV_INS_AMOXOR_W_AQ, "amoxor.w.aq"}, + {RISCV_INS_AMOXOR_W_AQ_RL, "amoxor.w.aqrl"}, + {RISCV_INS_AMOXOR_W_RL, "amoxor.w.rl"}, {RISCV_INS_AND, "and"}, + {RISCV_INS_ANDI, "andi"}, {RISCV_INS_AUIPC, "auipc"}, + {RISCV_INS_BEQ, "beq"}, {RISCV_INS_BGE, "bge"}, {RISCV_INS_BGEU, "bgeu"}, + {RISCV_INS_BLT, "blt"}, {RISCV_INS_BLTU, "bltu"}, {RISCV_INS_BNE, "bne"}, + {RISCV_INS_CSRRC, "csrrc"}, {RISCV_INS_CSRRCI, "csrrci"}, + {RISCV_INS_CSRRS, "csrrs"}, {RISCV_INS_CSRRSI, "csrrsi"}, + {RISCV_INS_CSRRW, "csrrw"}, {RISCV_INS_CSRRWI, "csrrwi"}, + {RISCV_INS_C_ADD, "c.add"}, {RISCV_INS_C_ADDI, "c.addi"}, + {RISCV_INS_C_ADDI16SP, "c.addi16sp"}, {RISCV_INS_C_ADDI4SPN, "c.addi4spn"}, + {RISCV_INS_C_ADDIW, "c.addiw"}, {RISCV_INS_C_ADDW, "c.addw"}, + {RISCV_INS_C_AND, "c.and"}, {RISCV_INS_C_ANDI, "c.andi"}, + {RISCV_INS_C_BEQZ, "c.beqz"}, {RISCV_INS_C_BNEZ, "c.bnez"}, + {RISCV_INS_C_EBREAK, "c.ebreak"}, {RISCV_INS_C_FLD, "c.fld"}, + {RISCV_INS_C_FLDSP, "c.fldsp"}, {RISCV_INS_C_FLW, "c.flw"}, + {RISCV_INS_C_FLWSP, "c.flwsp"}, {RISCV_INS_C_FSD, "c.fsd"}, + {RISCV_INS_C_FSDSP, "c.fsdsp"}, {RISCV_INS_C_FSW, "c.fsw"}, + {RISCV_INS_C_FSWSP, "c.fswsp"}, {RISCV_INS_C_J, "c.j"}, + {RISCV_INS_C_JAL, "c.jal"}, {RISCV_INS_C_JALR, "c.jalr"}, + {RISCV_INS_C_JR, "c.jr"}, {RISCV_INS_C_LD, "c.ld"}, + {RISCV_INS_C_LDSP, "c.ldsp"}, {RISCV_INS_C_LI, "c.li"}, + {RISCV_INS_C_LUI, "c.lui"}, {RISCV_INS_C_LW, "c.lw"}, + {RISCV_INS_C_LWSP, "c.lwsp"}, {RISCV_INS_C_MV, "c.mv"}, + {RISCV_INS_C_NOP, "c.nop"}, {RISCV_INS_C_OR, "c.or"}, + {RISCV_INS_C_SD, "c.sd"}, {RISCV_INS_C_SDSP, "c.sdsp"}, + {RISCV_INS_C_SLLI, "c.slli"}, {RISCV_INS_C_SRAI, "c.srai"}, + {RISCV_INS_C_SRLI, "c.srli"}, {RISCV_INS_C_SUB, "c.sub"}, + {RISCV_INS_C_SUBW, "c.subw"}, {RISCV_INS_C_SW, "c.sw"}, + {RISCV_INS_C_SWSP, "c.swsp"}, {RISCV_INS_C_UNIMP, "c.unimp"}, + {RISCV_INS_C_XOR, "c.xor"}, {RISCV_INS_DIV, "div"}, + {RISCV_INS_DIVU, "divu"}, {RISCV_INS_DIVUW, "divuw"}, + {RISCV_INS_DIVW, "divw"}, {RISCV_INS_EBREAK, "ebreak"}, + {RISCV_INS_ECALL, "ecall"}, {RISCV_INS_FADD_D, "fadd.d"}, + {RISCV_INS_FADD_S, "fadd.s"}, {RISCV_INS_FCLASS_D, "fclass.d"}, + {RISCV_INS_FCLASS_S, "fclass.s"}, {RISCV_INS_FCVT_D_L, "fcvt.d.l"}, + {RISCV_INS_FCVT_D_LU, "fcvt.d.lu"}, {RISCV_INS_FCVT_D_S, "fcvt.d.s"}, + {RISCV_INS_FCVT_D_W, "fcvt.d.w"}, {RISCV_INS_FCVT_D_WU, "fcvt.d.wu"}, + {RISCV_INS_FCVT_LU_D, "fcvt.lu.d"}, {RISCV_INS_FCVT_LU_S, "fcvt.lu.s"}, + {RISCV_INS_FCVT_L_D, "fcvt.l.d"}, {RISCV_INS_FCVT_L_S, "fcvt.l.s"}, + {RISCV_INS_FCVT_S_D, "fcvt.s.d"}, {RISCV_INS_FCVT_S_L, "fcvt.s.l"}, + {RISCV_INS_FCVT_S_LU, "fcvt.s.lu"}, {RISCV_INS_FCVT_S_W, "fcvt.s.w"}, + {RISCV_INS_FCVT_S_WU, "fcvt.s.wu"}, {RISCV_INS_FCVT_WU_D, "fcvt.wu.d"}, + {RISCV_INS_FCVT_WU_S, "fcvt.wu.s"}, {RISCV_INS_FCVT_W_D, "fcvt.w.d"}, + {RISCV_INS_FCVT_W_S, "fcvt.w.s"}, {RISCV_INS_FDIV_D, "fdiv.d"}, + {RISCV_INS_FDIV_S, "fdiv.s"}, {RISCV_INS_FENCE, "fence"}, + {RISCV_INS_FENCE_I, "fence.i"}, {RISCV_INS_FENCE_TSO, "fence.tso"}, + {RISCV_INS_FEQ_D, "feq.d"}, {RISCV_INS_FEQ_S, "feq.s"}, + {RISCV_INS_FLD, "fld"}, {RISCV_INS_FLE_D, "fle.d"}, + {RISCV_INS_FLE_S, "fle.s"}, {RISCV_INS_FLT_D, "flt.d"}, + {RISCV_INS_FLT_S, "flt.s"}, {RISCV_INS_FLW, "flw"}, + {RISCV_INS_FMADD_D, "fmadd.d"}, {RISCV_INS_FMADD_S, "fmadd.s"}, + {RISCV_INS_FMAX_D, "fmax.d"}, {RISCV_INS_FMAX_S, "fmax.s"}, + {RISCV_INS_FMIN_D, "fmin.d"}, {RISCV_INS_FMIN_S, "fmin.s"}, + {RISCV_INS_FMSUB_D, "fmsub.d"}, {RISCV_INS_FMSUB_S, "fmsub.s"}, + {RISCV_INS_FMUL_D, "fmul.d"}, {RISCV_INS_FMUL_S, "fmul.s"}, + {RISCV_INS_FMV_D_X, "fmv.d.x"}, {RISCV_INS_FMV_W_X, "fmv.w.x"}, + {RISCV_INS_FMV_X_D, "fmv.x.d"}, {RISCV_INS_FMV_X_W, "fmv.x.w"}, + {RISCV_INS_FNMADD_D, "fnmadd.d"}, {RISCV_INS_FNMADD_S, "fnmadd.s"}, + {RISCV_INS_FNMSUB_D, "fnmsub.d"}, {RISCV_INS_FNMSUB_S, "fnmsub.s"}, + {RISCV_INS_FSD, "fsd"}, {RISCV_INS_FSGNJN_D, "fsgnjn.d"}, + {RISCV_INS_FSGNJN_S, "fsgnjn.s"}, {RISCV_INS_FSGNJX_D, "fsgnjx.d"}, + {RISCV_INS_FSGNJX_S, "fsgnjx.s"}, {RISCV_INS_FSGNJ_D, "fsgnj.d"}, + {RISCV_INS_FSGNJ_S, "fsgnj.s"}, {RISCV_INS_FSQRT_D, "fsqrt.d"}, + {RISCV_INS_FSQRT_S, "fsqrt.s"}, {RISCV_INS_FSUB_D, "fsub.d"}, + {RISCV_INS_FSUB_S, "fsub.s"}, {RISCV_INS_FSW, "fsw"}, + {RISCV_INS_JAL, "jal"}, {RISCV_INS_JALR, "jalr"}, {RISCV_INS_LB, "lb"}, + {RISCV_INS_LBU, "lbu"}, {RISCV_INS_LD, "ld"}, {RISCV_INS_LH, "lh"}, + {RISCV_INS_LHU, "lhu"}, {RISCV_INS_LR_D, "lr.d"}, + {RISCV_INS_LR_D_AQ, "lr.d.aq"}, {RISCV_INS_LR_D_AQ_RL, "lr.d.aqrl"}, + {RISCV_INS_LR_D_RL, "lr.d.rl"}, {RISCV_INS_LR_W, "lr.w"}, + {RISCV_INS_LR_W_AQ, "lr.w.aq"}, {RISCV_INS_LR_W_AQ_RL, "lr.w.aqrl"}, + {RISCV_INS_LR_W_RL, "lr.w.rl"}, {RISCV_INS_LUI, "lui"}, + {RISCV_INS_LW, "lw"}, {RISCV_INS_LWU, "lwu"}, {RISCV_INS_MRET, "mret"}, + {RISCV_INS_MUL, "mul"}, {RISCV_INS_MULH, "mulh"}, + {RISCV_INS_MULHSU, "mulhsu"}, {RISCV_INS_MULHU, "mulhu"}, + {RISCV_INS_MULW, "mulw"}, {RISCV_INS_OR, "or"}, {RISCV_INS_ORI, "ori"}, + {RISCV_INS_REM, "rem"}, {RISCV_INS_REMU, "remu"}, + {RISCV_INS_REMUW, "remuw"}, {RISCV_INS_REMW, "remw"}, {RISCV_INS_SB, "sb"}, + {RISCV_INS_SC_D, "sc.d"}, {RISCV_INS_SC_D_AQ, "sc.d.aq"}, + {RISCV_INS_SC_D_AQ_RL, "sc.d.aqrl"}, {RISCV_INS_SC_D_RL, "sc.d.rl"}, + {RISCV_INS_SC_W, "sc.w"}, {RISCV_INS_SC_W_AQ, "sc.w.aq"}, + {RISCV_INS_SC_W_AQ_RL, "sc.w.aqrl"}, {RISCV_INS_SC_W_RL, "sc.w.rl"}, + {RISCV_INS_SD, "sd"}, {RISCV_INS_SFENCE_VMA, "sfence.vma"}, + {RISCV_INS_SH, "sh"}, {RISCV_INS_SLL, "sll"}, {RISCV_INS_SLLI, "slli"}, + {RISCV_INS_SLLIW, "slliw"}, {RISCV_INS_SLLW, "sllw"}, + {RISCV_INS_SLT, "slt"}, {RISCV_INS_SLTI, "slti"}, + {RISCV_INS_SLTIU, "sltiu"}, {RISCV_INS_SLTU, "sltu"}, + {RISCV_INS_SRA, "sra"}, {RISCV_INS_SRAI, "srai"}, + {RISCV_INS_SRAIW, "sraiw"}, {RISCV_INS_SRAW, "sraw"}, + {RISCV_INS_SRET, "sret"}, {RISCV_INS_SRL, "srl"}, {RISCV_INS_SRLI, "srli"}, + {RISCV_INS_SRLIW, "srliw"}, {RISCV_INS_SRLW, "srlw"}, + {RISCV_INS_SUB, "sub"}, {RISCV_INS_SUBW, "subw"}, {RISCV_INS_SW, "sw"}, + {RISCV_INS_UNIMP, "unimp"}, {RISCV_INS_URET, "uret"}, + {RISCV_INS_WFI, "wfi"}, {RISCV_INS_XOR, "xor"}, {RISCV_INS_XORI, "xori"}, diff --git a/arch/RISCV/RISCVGenInstrInfo.inc b/arch/RISCV/RISCVGenInstrInfo.inc index 069892e176..801b8dead0 100644 --- a/arch/RISCV/RISCVGenInstrInfo.inc +++ b/arch/RISCV/RISCVGenInstrInfo.inc @@ -9,462 +9,461 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ - #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { - RISCV_PHI = 0, - RISCV_INLINEASM = 1, - RISCV_INLINEASM_BR = 2, - RISCV_CFI_INSTRUCTION = 3, - RISCV_EH_LABEL = 4, - RISCV_GC_LABEL = 5, - RISCV_ANNOTATION_LABEL = 6, - RISCV_KILL = 7, - RISCV_EXTRACT_SUBREG = 8, - RISCV_INSERT_SUBREG = 9, - RISCV_IMPLICIT_DEF = 10, - RISCV_SUBREG_TO_REG = 11, - RISCV_COPY_TO_REGCLASS = 12, - RISCV_DBG_VALUE = 13, - RISCV_DBG_LABEL = 14, - RISCV_REG_SEQUENCE = 15, - RISCV_COPY = 16, - RISCV_BUNDLE = 17, - RISCV_LIFETIME_START = 18, - RISCV_LIFETIME_END = 19, - RISCV_STACKMAP = 20, - RISCV_FENTRY_CALL = 21, - RISCV_PATCHPOINT = 22, - RISCV_LOAD_STACK_GUARD = 23, - RISCV_STATEPOINT = 24, - RISCV_LOCAL_ESCAPE = 25, - RISCV_FAULTING_OP = 26, - RISCV_PATCHABLE_OP = 27, - RISCV_PATCHABLE_FUNCTION_ENTER = 28, - RISCV_PATCHABLE_RET = 29, - RISCV_PATCHABLE_FUNCTION_EXIT = 30, - RISCV_PATCHABLE_TAIL_CALL = 31, - RISCV_PATCHABLE_EVENT_CALL = 32, - RISCV_PATCHABLE_TYPED_EVENT_CALL = 33, - RISCV_ICALL_BRANCH_FUNNEL = 34, - RISCV_G_ADD = 35, - RISCV_G_SUB = 36, - RISCV_G_MUL = 37, - RISCV_G_SDIV = 38, - RISCV_G_UDIV = 39, - RISCV_G_SREM = 40, - RISCV_G_UREM = 41, - RISCV_G_AND = 42, - RISCV_G_OR = 43, - RISCV_G_XOR = 44, - RISCV_G_IMPLICIT_DEF = 45, - RISCV_G_PHI = 46, - RISCV_G_FRAME_INDEX = 47, - RISCV_G_GLOBAL_VALUE = 48, - RISCV_G_EXTRACT = 49, - RISCV_G_UNMERGE_VALUES = 50, - RISCV_G_INSERT = 51, - RISCV_G_MERGE_VALUES = 52, - RISCV_G_BUILD_VECTOR = 53, - RISCV_G_BUILD_VECTOR_TRUNC = 54, - RISCV_G_CONCAT_VECTORS = 55, - RISCV_G_PTRTOINT = 56, - RISCV_G_INTTOPTR = 57, - RISCV_G_BITCAST = 58, - RISCV_G_INTRINSIC_TRUNC = 59, - RISCV_G_INTRINSIC_ROUND = 60, - RISCV_G_LOAD = 61, - RISCV_G_SEXTLOAD = 62, - RISCV_G_ZEXTLOAD = 63, - RISCV_G_STORE = 64, - RISCV_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65, - RISCV_G_ATOMIC_CMPXCHG = 66, - RISCV_G_ATOMICRMW_XCHG = 67, - RISCV_G_ATOMICRMW_ADD = 68, - RISCV_G_ATOMICRMW_SUB = 69, - RISCV_G_ATOMICRMW_AND = 70, - RISCV_G_ATOMICRMW_NAND = 71, - RISCV_G_ATOMICRMW_OR = 72, - RISCV_G_ATOMICRMW_XOR = 73, - RISCV_G_ATOMICRMW_MAX = 74, - RISCV_G_ATOMICRMW_MIN = 75, - RISCV_G_ATOMICRMW_UMAX = 76, - RISCV_G_ATOMICRMW_UMIN = 77, - RISCV_G_BRCOND = 78, - RISCV_G_BRINDIRECT = 79, - RISCV_G_INTRINSIC = 80, - RISCV_G_INTRINSIC_W_SIDE_EFFECTS = 81, - RISCV_G_ANYEXT = 82, - RISCV_G_TRUNC = 83, - RISCV_G_CONSTANT = 84, - RISCV_G_FCONSTANT = 85, - RISCV_G_VASTART = 86, - RISCV_G_VAARG = 87, - RISCV_G_SEXT = 88, - RISCV_G_ZEXT = 89, - RISCV_G_SHL = 90, - RISCV_G_LSHR = 91, - RISCV_G_ASHR = 92, - RISCV_G_ICMP = 93, - RISCV_G_FCMP = 94, - RISCV_G_SELECT = 95, - RISCV_G_UADDO = 96, - RISCV_G_UADDE = 97, - RISCV_G_USUBO = 98, - RISCV_G_USUBE = 99, - RISCV_G_SADDO = 100, - RISCV_G_SADDE = 101, - RISCV_G_SSUBO = 102, - RISCV_G_SSUBE = 103, - RISCV_G_UMULO = 104, - RISCV_G_SMULO = 105, - RISCV_G_UMULH = 106, - RISCV_G_SMULH = 107, - RISCV_G_FADD = 108, - RISCV_G_FSUB = 109, - RISCV_G_FMUL = 110, - RISCV_G_FMA = 111, - RISCV_G_FDIV = 112, - RISCV_G_FREM = 113, - RISCV_G_FPOW = 114, - RISCV_G_FEXP = 115, - RISCV_G_FEXP2 = 116, - RISCV_G_FLOG = 117, - RISCV_G_FLOG2 = 118, - RISCV_G_FLOG10 = 119, - RISCV_G_FNEG = 120, - RISCV_G_FPEXT = 121, - RISCV_G_FPTRUNC = 122, - RISCV_G_FPTOSI = 123, - RISCV_G_FPTOUI = 124, - RISCV_G_SITOFP = 125, - RISCV_G_UITOFP = 126, - RISCV_G_FABS = 127, - RISCV_G_FCANONICALIZE = 128, - RISCV_G_GEP = 129, - RISCV_G_PTR_MASK = 130, - RISCV_G_BR = 131, - RISCV_G_INSERT_VECTOR_ELT = 132, - RISCV_G_EXTRACT_VECTOR_ELT = 133, - RISCV_G_SHUFFLE_VECTOR = 134, - RISCV_G_CTTZ = 135, - RISCV_G_CTTZ_ZERO_UNDEF = 136, - RISCV_G_CTLZ = 137, - RISCV_G_CTLZ_ZERO_UNDEF = 138, - RISCV_G_CTPOP = 139, - RISCV_G_BSWAP = 140, - RISCV_G_FCEIL = 141, - RISCV_G_FCOS = 142, - RISCV_G_FSIN = 143, - RISCV_G_FSQRT = 144, - RISCV_G_FFLOOR = 145, - RISCV_G_ADDRSPACE_CAST = 146, - RISCV_G_BLOCK_ADDR = 147, - RISCV_ADJCALLSTACKDOWN = 148, - RISCV_ADJCALLSTACKUP = 149, - RISCV_BuildPairF64Pseudo = 150, - RISCV_PseudoAtomicLoadNand32 = 151, - RISCV_PseudoAtomicLoadNand64 = 152, - RISCV_PseudoBR = 153, - RISCV_PseudoBRIND = 154, - RISCV_PseudoCALL = 155, - RISCV_PseudoCALLIndirect = 156, - RISCV_PseudoCmpXchg32 = 157, - RISCV_PseudoCmpXchg64 = 158, - RISCV_PseudoLA = 159, - RISCV_PseudoLI = 160, - RISCV_PseudoLLA = 161, - RISCV_PseudoMaskedAtomicLoadAdd32 = 162, - RISCV_PseudoMaskedAtomicLoadMax32 = 163, - RISCV_PseudoMaskedAtomicLoadMin32 = 164, - RISCV_PseudoMaskedAtomicLoadNand32 = 165, - RISCV_PseudoMaskedAtomicLoadSub32 = 166, - RISCV_PseudoMaskedAtomicLoadUMax32 = 167, - RISCV_PseudoMaskedAtomicLoadUMin32 = 168, - RISCV_PseudoMaskedAtomicSwap32 = 169, - RISCV_PseudoMaskedCmpXchg32 = 170, - RISCV_PseudoRET = 171, - RISCV_PseudoTAIL = 172, - RISCV_PseudoTAILIndirect = 173, - RISCV_Select_FPR32_Using_CC_GPR = 174, - RISCV_Select_FPR64_Using_CC_GPR = 175, - RISCV_Select_GPR_Using_CC_GPR = 176, - RISCV_SplitF64Pseudo = 177, - RISCV_ADD = 178, - RISCV_ADDI = 179, - RISCV_ADDIW = 180, - RISCV_ADDW = 181, - RISCV_AMOADD_D = 182, - RISCV_AMOADD_D_AQ = 183, - RISCV_AMOADD_D_AQ_RL = 184, - RISCV_AMOADD_D_RL = 185, - RISCV_AMOADD_W = 186, - RISCV_AMOADD_W_AQ = 187, - RISCV_AMOADD_W_AQ_RL = 188, - RISCV_AMOADD_W_RL = 189, - RISCV_AMOAND_D = 190, - RISCV_AMOAND_D_AQ = 191, - RISCV_AMOAND_D_AQ_RL = 192, - RISCV_AMOAND_D_RL = 193, - RISCV_AMOAND_W = 194, - RISCV_AMOAND_W_AQ = 195, - RISCV_AMOAND_W_AQ_RL = 196, - RISCV_AMOAND_W_RL = 197, - RISCV_AMOMAXU_D = 198, - RISCV_AMOMAXU_D_AQ = 199, - RISCV_AMOMAXU_D_AQ_RL = 200, - RISCV_AMOMAXU_D_RL = 201, - RISCV_AMOMAXU_W = 202, - RISCV_AMOMAXU_W_AQ = 203, - RISCV_AMOMAXU_W_AQ_RL = 204, - RISCV_AMOMAXU_W_RL = 205, - RISCV_AMOMAX_D = 206, - RISCV_AMOMAX_D_AQ = 207, - RISCV_AMOMAX_D_AQ_RL = 208, - RISCV_AMOMAX_D_RL = 209, - RISCV_AMOMAX_W = 210, - RISCV_AMOMAX_W_AQ = 211, - RISCV_AMOMAX_W_AQ_RL = 212, - RISCV_AMOMAX_W_RL = 213, - RISCV_AMOMINU_D = 214, - RISCV_AMOMINU_D_AQ = 215, - RISCV_AMOMINU_D_AQ_RL = 216, - RISCV_AMOMINU_D_RL = 217, - RISCV_AMOMINU_W = 218, - RISCV_AMOMINU_W_AQ = 219, - RISCV_AMOMINU_W_AQ_RL = 220, - RISCV_AMOMINU_W_RL = 221, - RISCV_AMOMIN_D = 222, - RISCV_AMOMIN_D_AQ = 223, - RISCV_AMOMIN_D_AQ_RL = 224, - RISCV_AMOMIN_D_RL = 225, - RISCV_AMOMIN_W = 226, - RISCV_AMOMIN_W_AQ = 227, - RISCV_AMOMIN_W_AQ_RL = 228, - RISCV_AMOMIN_W_RL = 229, - RISCV_AMOOR_D = 230, - RISCV_AMOOR_D_AQ = 231, - RISCV_AMOOR_D_AQ_RL = 232, - RISCV_AMOOR_D_RL = 233, - RISCV_AMOOR_W = 234, - RISCV_AMOOR_W_AQ = 235, - RISCV_AMOOR_W_AQ_RL = 236, - RISCV_AMOOR_W_RL = 237, - RISCV_AMOSWAP_D = 238, - RISCV_AMOSWAP_D_AQ = 239, - RISCV_AMOSWAP_D_AQ_RL = 240, - RISCV_AMOSWAP_D_RL = 241, - RISCV_AMOSWAP_W = 242, - RISCV_AMOSWAP_W_AQ = 243, - RISCV_AMOSWAP_W_AQ_RL = 244, - RISCV_AMOSWAP_W_RL = 245, - RISCV_AMOXOR_D = 246, - RISCV_AMOXOR_D_AQ = 247, - RISCV_AMOXOR_D_AQ_RL = 248, - RISCV_AMOXOR_D_RL = 249, - RISCV_AMOXOR_W = 250, - RISCV_AMOXOR_W_AQ = 251, - RISCV_AMOXOR_W_AQ_RL = 252, - RISCV_AMOXOR_W_RL = 253, - RISCV_AND = 254, - RISCV_ANDI = 255, - RISCV_AUIPC = 256, - RISCV_BEQ = 257, - RISCV_BGE = 258, - RISCV_BGEU = 259, - RISCV_BLT = 260, - RISCV_BLTU = 261, - RISCV_BNE = 262, - RISCV_CSRRC = 263, - RISCV_CSRRCI = 264, - RISCV_CSRRS = 265, - RISCV_CSRRSI = 266, - RISCV_CSRRW = 267, - RISCV_CSRRWI = 268, - RISCV_C_ADD = 269, - RISCV_C_ADDI = 270, - RISCV_C_ADDI16SP = 271, - RISCV_C_ADDI4SPN = 272, - RISCV_C_ADDIW = 273, - RISCV_C_ADDW = 274, - RISCV_C_AND = 275, - RISCV_C_ANDI = 276, - RISCV_C_BEQZ = 277, - RISCV_C_BNEZ = 278, - RISCV_C_EBREAK = 279, - RISCV_C_FLD = 280, - RISCV_C_FLDSP = 281, - RISCV_C_FLW = 282, - RISCV_C_FLWSP = 283, - RISCV_C_FSD = 284, - RISCV_C_FSDSP = 285, - RISCV_C_FSW = 286, - RISCV_C_FSWSP = 287, - RISCV_C_J = 288, - RISCV_C_JAL = 289, - RISCV_C_JALR = 290, - RISCV_C_JR = 291, - RISCV_C_LD = 292, - RISCV_C_LDSP = 293, - RISCV_C_LI = 294, - RISCV_C_LUI = 295, - RISCV_C_LW = 296, - RISCV_C_LWSP = 297, - RISCV_C_MV = 298, - RISCV_C_NOP = 299, - RISCV_C_OR = 300, - RISCV_C_SD = 301, - RISCV_C_SDSP = 302, - RISCV_C_SLLI = 303, - RISCV_C_SRAI = 304, - RISCV_C_SRLI = 305, - RISCV_C_SUB = 306, - RISCV_C_SUBW = 307, - RISCV_C_SW = 308, - RISCV_C_SWSP = 309, - RISCV_C_UNIMP = 310, - RISCV_C_XOR = 311, - RISCV_DIV = 312, - RISCV_DIVU = 313, - RISCV_DIVUW = 314, - RISCV_DIVW = 315, - RISCV_EBREAK = 316, - RISCV_ECALL = 317, - RISCV_FADD_D = 318, - RISCV_FADD_S = 319, - RISCV_FCLASS_D = 320, - RISCV_FCLASS_S = 321, - RISCV_FCVT_D_L = 322, - RISCV_FCVT_D_LU = 323, - RISCV_FCVT_D_S = 324, - RISCV_FCVT_D_W = 325, - RISCV_FCVT_D_WU = 326, - RISCV_FCVT_LU_D = 327, - RISCV_FCVT_LU_S = 328, - RISCV_FCVT_L_D = 329, - RISCV_FCVT_L_S = 330, - RISCV_FCVT_S_D = 331, - RISCV_FCVT_S_L = 332, - RISCV_FCVT_S_LU = 333, - RISCV_FCVT_S_W = 334, - RISCV_FCVT_S_WU = 335, - RISCV_FCVT_WU_D = 336, - RISCV_FCVT_WU_S = 337, - RISCV_FCVT_W_D = 338, - RISCV_FCVT_W_S = 339, - RISCV_FDIV_D = 340, - RISCV_FDIV_S = 341, - RISCV_FENCE = 342, - RISCV_FENCE_I = 343, - RISCV_FENCE_TSO = 344, - RISCV_FEQ_D = 345, - RISCV_FEQ_S = 346, - RISCV_FLD = 347, - RISCV_FLE_D = 348, - RISCV_FLE_S = 349, - RISCV_FLT_D = 350, - RISCV_FLT_S = 351, - RISCV_FLW = 352, - RISCV_FMADD_D = 353, - RISCV_FMADD_S = 354, - RISCV_FMAX_D = 355, - RISCV_FMAX_S = 356, - RISCV_FMIN_D = 357, - RISCV_FMIN_S = 358, - RISCV_FMSUB_D = 359, - RISCV_FMSUB_S = 360, - RISCV_FMUL_D = 361, - RISCV_FMUL_S = 362, - RISCV_FMV_D_X = 363, - RISCV_FMV_W_X = 364, - RISCV_FMV_X_D = 365, - RISCV_FMV_X_W = 366, - RISCV_FNMADD_D = 367, - RISCV_FNMADD_S = 368, - RISCV_FNMSUB_D = 369, - RISCV_FNMSUB_S = 370, - RISCV_FSD = 371, - RISCV_FSGNJN_D = 372, - RISCV_FSGNJN_S = 373, - RISCV_FSGNJX_D = 374, - RISCV_FSGNJX_S = 375, - RISCV_FSGNJ_D = 376, - RISCV_FSGNJ_S = 377, - RISCV_FSQRT_D = 378, - RISCV_FSQRT_S = 379, - RISCV_FSUB_D = 380, - RISCV_FSUB_S = 381, - RISCV_FSW = 382, - RISCV_JAL = 383, - RISCV_JALR = 384, - RISCV_LB = 385, - RISCV_LBU = 386, - RISCV_LD = 387, - RISCV_LH = 388, - RISCV_LHU = 389, - RISCV_LR_D = 390, - RISCV_LR_D_AQ = 391, - RISCV_LR_D_AQ_RL = 392, - RISCV_LR_D_RL = 393, - RISCV_LR_W = 394, - RISCV_LR_W_AQ = 395, - RISCV_LR_W_AQ_RL = 396, - RISCV_LR_W_RL = 397, - RISCV_LUI = 398, - RISCV_LW = 399, - RISCV_LWU = 400, - RISCV_MRET = 401, - RISCV_MUL = 402, - RISCV_MULH = 403, - RISCV_MULHSU = 404, - RISCV_MULHU = 405, - RISCV_MULW = 406, - RISCV_OR = 407, - RISCV_ORI = 408, - RISCV_REM = 409, - RISCV_REMU = 410, - RISCV_REMUW = 411, - RISCV_REMW = 412, - RISCV_SB = 413, - RISCV_SC_D = 414, - RISCV_SC_D_AQ = 415, - RISCV_SC_D_AQ_RL = 416, - RISCV_SC_D_RL = 417, - RISCV_SC_W = 418, - RISCV_SC_W_AQ = 419, - RISCV_SC_W_AQ_RL = 420, - RISCV_SC_W_RL = 421, - RISCV_SD = 422, - RISCV_SFENCE_VMA = 423, - RISCV_SH = 424, - RISCV_SLL = 425, - RISCV_SLLI = 426, - RISCV_SLLIW = 427, - RISCV_SLLW = 428, - RISCV_SLT = 429, - RISCV_SLTI = 430, - RISCV_SLTIU = 431, - RISCV_SLTU = 432, - RISCV_SRA = 433, - RISCV_SRAI = 434, - RISCV_SRAIW = 435, - RISCV_SRAW = 436, - RISCV_SRET = 437, - RISCV_SRL = 438, - RISCV_SRLI = 439, - RISCV_SRLIW = 440, - RISCV_SRLW = 441, - RISCV_SUB = 442, - RISCV_SUBW = 443, - RISCV_SW = 444, - RISCV_UNIMP = 445, - RISCV_URET = 446, - RISCV_WFI = 447, - RISCV_XOR = 448, - RISCV_XORI = 449, - RISCV_INSTRUCTION_LIST_END = 450 - }; + RISCV_PHI = 0, + RISCV_INLINEASM = 1, + RISCV_INLINEASM_BR = 2, + RISCV_CFI_INSTRUCTION = 3, + RISCV_EH_LABEL = 4, + RISCV_GC_LABEL = 5, + RISCV_ANNOTATION_LABEL = 6, + RISCV_KILL = 7, + RISCV_EXTRACT_SUBREG = 8, + RISCV_INSERT_SUBREG = 9, + RISCV_IMPLICIT_DEF = 10, + RISCV_SUBREG_TO_REG = 11, + RISCV_COPY_TO_REGCLASS = 12, + RISCV_DBG_VALUE = 13, + RISCV_DBG_LABEL = 14, + RISCV_REG_SEQUENCE = 15, + RISCV_COPY = 16, + RISCV_BUNDLE = 17, + RISCV_LIFETIME_START = 18, + RISCV_LIFETIME_END = 19, + RISCV_STACKMAP = 20, + RISCV_FENTRY_CALL = 21, + RISCV_PATCHPOINT = 22, + RISCV_LOAD_STACK_GUARD = 23, + RISCV_STATEPOINT = 24, + RISCV_LOCAL_ESCAPE = 25, + RISCV_FAULTING_OP = 26, + RISCV_PATCHABLE_OP = 27, + RISCV_PATCHABLE_FUNCTION_ENTER = 28, + RISCV_PATCHABLE_RET = 29, + RISCV_PATCHABLE_FUNCTION_EXIT = 30, + RISCV_PATCHABLE_TAIL_CALL = 31, + RISCV_PATCHABLE_EVENT_CALL = 32, + RISCV_PATCHABLE_TYPED_EVENT_CALL = 33, + RISCV_ICALL_BRANCH_FUNNEL = 34, + RISCV_G_ADD = 35, + RISCV_G_SUB = 36, + RISCV_G_MUL = 37, + RISCV_G_SDIV = 38, + RISCV_G_UDIV = 39, + RISCV_G_SREM = 40, + RISCV_G_UREM = 41, + RISCV_G_AND = 42, + RISCV_G_OR = 43, + RISCV_G_XOR = 44, + RISCV_G_IMPLICIT_DEF = 45, + RISCV_G_PHI = 46, + RISCV_G_FRAME_INDEX = 47, + RISCV_G_GLOBAL_VALUE = 48, + RISCV_G_EXTRACT = 49, + RISCV_G_UNMERGE_VALUES = 50, + RISCV_G_INSERT = 51, + RISCV_G_MERGE_VALUES = 52, + RISCV_G_BUILD_VECTOR = 53, + RISCV_G_BUILD_VECTOR_TRUNC = 54, + RISCV_G_CONCAT_VECTORS = 55, + RISCV_G_PTRTOINT = 56, + RISCV_G_INTTOPTR = 57, + RISCV_G_BITCAST = 58, + RISCV_G_INTRINSIC_TRUNC = 59, + RISCV_G_INTRINSIC_ROUND = 60, + RISCV_G_LOAD = 61, + RISCV_G_SEXTLOAD = 62, + RISCV_G_ZEXTLOAD = 63, + RISCV_G_STORE = 64, + RISCV_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65, + RISCV_G_ATOMIC_CMPXCHG = 66, + RISCV_G_ATOMICRMW_XCHG = 67, + RISCV_G_ATOMICRMW_ADD = 68, + RISCV_G_ATOMICRMW_SUB = 69, + RISCV_G_ATOMICRMW_AND = 70, + RISCV_G_ATOMICRMW_NAND = 71, + RISCV_G_ATOMICRMW_OR = 72, + RISCV_G_ATOMICRMW_XOR = 73, + RISCV_G_ATOMICRMW_MAX = 74, + RISCV_G_ATOMICRMW_MIN = 75, + RISCV_G_ATOMICRMW_UMAX = 76, + RISCV_G_ATOMICRMW_UMIN = 77, + RISCV_G_BRCOND = 78, + RISCV_G_BRINDIRECT = 79, + RISCV_G_INTRINSIC = 80, + RISCV_G_INTRINSIC_W_SIDE_EFFECTS = 81, + RISCV_G_ANYEXT = 82, + RISCV_G_TRUNC = 83, + RISCV_G_CONSTANT = 84, + RISCV_G_FCONSTANT = 85, + RISCV_G_VASTART = 86, + RISCV_G_VAARG = 87, + RISCV_G_SEXT = 88, + RISCV_G_ZEXT = 89, + RISCV_G_SHL = 90, + RISCV_G_LSHR = 91, + RISCV_G_ASHR = 92, + RISCV_G_ICMP = 93, + RISCV_G_FCMP = 94, + RISCV_G_SELECT = 95, + RISCV_G_UADDO = 96, + RISCV_G_UADDE = 97, + RISCV_G_USUBO = 98, + RISCV_G_USUBE = 99, + RISCV_G_SADDO = 100, + RISCV_G_SADDE = 101, + RISCV_G_SSUBO = 102, + RISCV_G_SSUBE = 103, + RISCV_G_UMULO = 104, + RISCV_G_SMULO = 105, + RISCV_G_UMULH = 106, + RISCV_G_SMULH = 107, + RISCV_G_FADD = 108, + RISCV_G_FSUB = 109, + RISCV_G_FMUL = 110, + RISCV_G_FMA = 111, + RISCV_G_FDIV = 112, + RISCV_G_FREM = 113, + RISCV_G_FPOW = 114, + RISCV_G_FEXP = 115, + RISCV_G_FEXP2 = 116, + RISCV_G_FLOG = 117, + RISCV_G_FLOG2 = 118, + RISCV_G_FLOG10 = 119, + RISCV_G_FNEG = 120, + RISCV_G_FPEXT = 121, + RISCV_G_FPTRUNC = 122, + RISCV_G_FPTOSI = 123, + RISCV_G_FPTOUI = 124, + RISCV_G_SITOFP = 125, + RISCV_G_UITOFP = 126, + RISCV_G_FABS = 127, + RISCV_G_FCANONICALIZE = 128, + RISCV_G_GEP = 129, + RISCV_G_PTR_MASK = 130, + RISCV_G_BR = 131, + RISCV_G_INSERT_VECTOR_ELT = 132, + RISCV_G_EXTRACT_VECTOR_ELT = 133, + RISCV_G_SHUFFLE_VECTOR = 134, + RISCV_G_CTTZ = 135, + RISCV_G_CTTZ_ZERO_UNDEF = 136, + RISCV_G_CTLZ = 137, + RISCV_G_CTLZ_ZERO_UNDEF = 138, + RISCV_G_CTPOP = 139, + RISCV_G_BSWAP = 140, + RISCV_G_FCEIL = 141, + RISCV_G_FCOS = 142, + RISCV_G_FSIN = 143, + RISCV_G_FSQRT = 144, + RISCV_G_FFLOOR = 145, + RISCV_G_ADDRSPACE_CAST = 146, + RISCV_G_BLOCK_ADDR = 147, + RISCV_ADJCALLSTACKDOWN = 148, + RISCV_ADJCALLSTACKUP = 149, + RISCV_BuildPairF64Pseudo = 150, + RISCV_PseudoAtomicLoadNand32 = 151, + RISCV_PseudoAtomicLoadNand64 = 152, + RISCV_PseudoBR = 153, + RISCV_PseudoBRIND = 154, + RISCV_PseudoCALL = 155, + RISCV_PseudoCALLIndirect = 156, + RISCV_PseudoCmpXchg32 = 157, + RISCV_PseudoCmpXchg64 = 158, + RISCV_PseudoLA = 159, + RISCV_PseudoLI = 160, + RISCV_PseudoLLA = 161, + RISCV_PseudoMaskedAtomicLoadAdd32 = 162, + RISCV_PseudoMaskedAtomicLoadMax32 = 163, + RISCV_PseudoMaskedAtomicLoadMin32 = 164, + RISCV_PseudoMaskedAtomicLoadNand32 = 165, + RISCV_PseudoMaskedAtomicLoadSub32 = 166, + RISCV_PseudoMaskedAtomicLoadUMax32 = 167, + RISCV_PseudoMaskedAtomicLoadUMin32 = 168, + RISCV_PseudoMaskedAtomicSwap32 = 169, + RISCV_PseudoMaskedCmpXchg32 = 170, + RISCV_PseudoRET = 171, + RISCV_PseudoTAIL = 172, + RISCV_PseudoTAILIndirect = 173, + RISCV_Select_FPR32_Using_CC_GPR = 174, + RISCV_Select_FPR64_Using_CC_GPR = 175, + RISCV_Select_GPR_Using_CC_GPR = 176, + RISCV_SplitF64Pseudo = 177, + RISCV_ADD = 178, + RISCV_ADDI = 179, + RISCV_ADDIW = 180, + RISCV_ADDW = 181, + RISCV_AMOADD_D = 182, + RISCV_AMOADD_D_AQ = 183, + RISCV_AMOADD_D_AQ_RL = 184, + RISCV_AMOADD_D_RL = 185, + RISCV_AMOADD_W = 186, + RISCV_AMOADD_W_AQ = 187, + RISCV_AMOADD_W_AQ_RL = 188, + RISCV_AMOADD_W_RL = 189, + RISCV_AMOAND_D = 190, + RISCV_AMOAND_D_AQ = 191, + RISCV_AMOAND_D_AQ_RL = 192, + RISCV_AMOAND_D_RL = 193, + RISCV_AMOAND_W = 194, + RISCV_AMOAND_W_AQ = 195, + RISCV_AMOAND_W_AQ_RL = 196, + RISCV_AMOAND_W_RL = 197, + RISCV_AMOMAXU_D = 198, + RISCV_AMOMAXU_D_AQ = 199, + RISCV_AMOMAXU_D_AQ_RL = 200, + RISCV_AMOMAXU_D_RL = 201, + RISCV_AMOMAXU_W = 202, + RISCV_AMOMAXU_W_AQ = 203, + RISCV_AMOMAXU_W_AQ_RL = 204, + RISCV_AMOMAXU_W_RL = 205, + RISCV_AMOMAX_D = 206, + RISCV_AMOMAX_D_AQ = 207, + RISCV_AMOMAX_D_AQ_RL = 208, + RISCV_AMOMAX_D_RL = 209, + RISCV_AMOMAX_W = 210, + RISCV_AMOMAX_W_AQ = 211, + RISCV_AMOMAX_W_AQ_RL = 212, + RISCV_AMOMAX_W_RL = 213, + RISCV_AMOMINU_D = 214, + RISCV_AMOMINU_D_AQ = 215, + RISCV_AMOMINU_D_AQ_RL = 216, + RISCV_AMOMINU_D_RL = 217, + RISCV_AMOMINU_W = 218, + RISCV_AMOMINU_W_AQ = 219, + RISCV_AMOMINU_W_AQ_RL = 220, + RISCV_AMOMINU_W_RL = 221, + RISCV_AMOMIN_D = 222, + RISCV_AMOMIN_D_AQ = 223, + RISCV_AMOMIN_D_AQ_RL = 224, + RISCV_AMOMIN_D_RL = 225, + RISCV_AMOMIN_W = 226, + RISCV_AMOMIN_W_AQ = 227, + RISCV_AMOMIN_W_AQ_RL = 228, + RISCV_AMOMIN_W_RL = 229, + RISCV_AMOOR_D = 230, + RISCV_AMOOR_D_AQ = 231, + RISCV_AMOOR_D_AQ_RL = 232, + RISCV_AMOOR_D_RL = 233, + RISCV_AMOOR_W = 234, + RISCV_AMOOR_W_AQ = 235, + RISCV_AMOOR_W_AQ_RL = 236, + RISCV_AMOOR_W_RL = 237, + RISCV_AMOSWAP_D = 238, + RISCV_AMOSWAP_D_AQ = 239, + RISCV_AMOSWAP_D_AQ_RL = 240, + RISCV_AMOSWAP_D_RL = 241, + RISCV_AMOSWAP_W = 242, + RISCV_AMOSWAP_W_AQ = 243, + RISCV_AMOSWAP_W_AQ_RL = 244, + RISCV_AMOSWAP_W_RL = 245, + RISCV_AMOXOR_D = 246, + RISCV_AMOXOR_D_AQ = 247, + RISCV_AMOXOR_D_AQ_RL = 248, + RISCV_AMOXOR_D_RL = 249, + RISCV_AMOXOR_W = 250, + RISCV_AMOXOR_W_AQ = 251, + RISCV_AMOXOR_W_AQ_RL = 252, + RISCV_AMOXOR_W_RL = 253, + RISCV_AND = 254, + RISCV_ANDI = 255, + RISCV_AUIPC = 256, + RISCV_BEQ = 257, + RISCV_BGE = 258, + RISCV_BGEU = 259, + RISCV_BLT = 260, + RISCV_BLTU = 261, + RISCV_BNE = 262, + RISCV_CSRRC = 263, + RISCV_CSRRCI = 264, + RISCV_CSRRS = 265, + RISCV_CSRRSI = 266, + RISCV_CSRRW = 267, + RISCV_CSRRWI = 268, + RISCV_C_ADD = 269, + RISCV_C_ADDI = 270, + RISCV_C_ADDI16SP = 271, + RISCV_C_ADDI4SPN = 272, + RISCV_C_ADDIW = 273, + RISCV_C_ADDW = 274, + RISCV_C_AND = 275, + RISCV_C_ANDI = 276, + RISCV_C_BEQZ = 277, + RISCV_C_BNEZ = 278, + RISCV_C_EBREAK = 279, + RISCV_C_FLD = 280, + RISCV_C_FLDSP = 281, + RISCV_C_FLW = 282, + RISCV_C_FLWSP = 283, + RISCV_C_FSD = 284, + RISCV_C_FSDSP = 285, + RISCV_C_FSW = 286, + RISCV_C_FSWSP = 287, + RISCV_C_J = 288, + RISCV_C_JAL = 289, + RISCV_C_JALR = 290, + RISCV_C_JR = 291, + RISCV_C_LD = 292, + RISCV_C_LDSP = 293, + RISCV_C_LI = 294, + RISCV_C_LUI = 295, + RISCV_C_LW = 296, + RISCV_C_LWSP = 297, + RISCV_C_MV = 298, + RISCV_C_NOP = 299, + RISCV_C_OR = 300, + RISCV_C_SD = 301, + RISCV_C_SDSP = 302, + RISCV_C_SLLI = 303, + RISCV_C_SRAI = 304, + RISCV_C_SRLI = 305, + RISCV_C_SUB = 306, + RISCV_C_SUBW = 307, + RISCV_C_SW = 308, + RISCV_C_SWSP = 309, + RISCV_C_UNIMP = 310, + RISCV_C_XOR = 311, + RISCV_DIV = 312, + RISCV_DIVU = 313, + RISCV_DIVUW = 314, + RISCV_DIVW = 315, + RISCV_EBREAK = 316, + RISCV_ECALL = 317, + RISCV_FADD_D = 318, + RISCV_FADD_S = 319, + RISCV_FCLASS_D = 320, + RISCV_FCLASS_S = 321, + RISCV_FCVT_D_L = 322, + RISCV_FCVT_D_LU = 323, + RISCV_FCVT_D_S = 324, + RISCV_FCVT_D_W = 325, + RISCV_FCVT_D_WU = 326, + RISCV_FCVT_LU_D = 327, + RISCV_FCVT_LU_S = 328, + RISCV_FCVT_L_D = 329, + RISCV_FCVT_L_S = 330, + RISCV_FCVT_S_D = 331, + RISCV_FCVT_S_L = 332, + RISCV_FCVT_S_LU = 333, + RISCV_FCVT_S_W = 334, + RISCV_FCVT_S_WU = 335, + RISCV_FCVT_WU_D = 336, + RISCV_FCVT_WU_S = 337, + RISCV_FCVT_W_D = 338, + RISCV_FCVT_W_S = 339, + RISCV_FDIV_D = 340, + RISCV_FDIV_S = 341, + RISCV_FENCE = 342, + RISCV_FENCE_I = 343, + RISCV_FENCE_TSO = 344, + RISCV_FEQ_D = 345, + RISCV_FEQ_S = 346, + RISCV_FLD = 347, + RISCV_FLE_D = 348, + RISCV_FLE_S = 349, + RISCV_FLT_D = 350, + RISCV_FLT_S = 351, + RISCV_FLW = 352, + RISCV_FMADD_D = 353, + RISCV_FMADD_S = 354, + RISCV_FMAX_D = 355, + RISCV_FMAX_S = 356, + RISCV_FMIN_D = 357, + RISCV_FMIN_S = 358, + RISCV_FMSUB_D = 359, + RISCV_FMSUB_S = 360, + RISCV_FMUL_D = 361, + RISCV_FMUL_S = 362, + RISCV_FMV_D_X = 363, + RISCV_FMV_W_X = 364, + RISCV_FMV_X_D = 365, + RISCV_FMV_X_W = 366, + RISCV_FNMADD_D = 367, + RISCV_FNMADD_S = 368, + RISCV_FNMSUB_D = 369, + RISCV_FNMSUB_S = 370, + RISCV_FSD = 371, + RISCV_FSGNJN_D = 372, + RISCV_FSGNJN_S = 373, + RISCV_FSGNJX_D = 374, + RISCV_FSGNJX_S = 375, + RISCV_FSGNJ_D = 376, + RISCV_FSGNJ_S = 377, + RISCV_FSQRT_D = 378, + RISCV_FSQRT_S = 379, + RISCV_FSUB_D = 380, + RISCV_FSUB_S = 381, + RISCV_FSW = 382, + RISCV_JAL = 383, + RISCV_JALR = 384, + RISCV_LB = 385, + RISCV_LBU = 386, + RISCV_LD = 387, + RISCV_LH = 388, + RISCV_LHU = 389, + RISCV_LR_D = 390, + RISCV_LR_D_AQ = 391, + RISCV_LR_D_AQ_RL = 392, + RISCV_LR_D_RL = 393, + RISCV_LR_W = 394, + RISCV_LR_W_AQ = 395, + RISCV_LR_W_AQ_RL = 396, + RISCV_LR_W_RL = 397, + RISCV_LUI = 398, + RISCV_LW = 399, + RISCV_LWU = 400, + RISCV_MRET = 401, + RISCV_MUL = 402, + RISCV_MULH = 403, + RISCV_MULHSU = 404, + RISCV_MULHU = 405, + RISCV_MULW = 406, + RISCV_OR = 407, + RISCV_ORI = 408, + RISCV_REM = 409, + RISCV_REMU = 410, + RISCV_REMUW = 411, + RISCV_REMW = 412, + RISCV_SB = 413, + RISCV_SC_D = 414, + RISCV_SC_D_AQ = 415, + RISCV_SC_D_AQ_RL = 416, + RISCV_SC_D_RL = 417, + RISCV_SC_W = 418, + RISCV_SC_W_AQ = 419, + RISCV_SC_W_AQ_RL = 420, + RISCV_SC_W_RL = 421, + RISCV_SD = 422, + RISCV_SFENCE_VMA = 423, + RISCV_SH = 424, + RISCV_SLL = 425, + RISCV_SLLI = 426, + RISCV_SLLIW = 427, + RISCV_SLLW = 428, + RISCV_SLT = 429, + RISCV_SLTI = 430, + RISCV_SLTIU = 431, + RISCV_SLTU = 432, + RISCV_SRA = 433, + RISCV_SRAI = 434, + RISCV_SRAIW = 435, + RISCV_SRAW = 436, + RISCV_SRET = 437, + RISCV_SRL = 438, + RISCV_SRLI = 439, + RISCV_SRLIW = 440, + RISCV_SRLW = 441, + RISCV_SUB = 442, + RISCV_SUBW = 443, + RISCV_SW = 444, + RISCV_UNIMP = 445, + RISCV_URET = 446, + RISCV_WFI = 447, + RISCV_XOR = 448, + RISCV_XORI = 449, + RISCV_INSTRUCTION_LIST_END = 450 +}; #endif // GET_INSTRINFO_ENUM diff --git a/arch/RISCV/RISCVGenRegisterInfo.inc b/arch/RISCV/RISCVGenRegisterInfo.inc index 2b74467913..71d4222c67 100644 --- a/arch/RISCV/RISCVGenRegisterInfo.inc +++ b/arch/RISCV/RISCVGenRegisterInfo.inc @@ -9,7 +9,6 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ - #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM @@ -111,7 +110,7 @@ enum { RISCV_F30_64 = 94, RISCV_F31_32 = 95, RISCV_F31_64 = 96, - RISCV_NUM_TARGET_REGS // 97 + RISCV_NUM_TARGET_REGS // 97 }; // Register classes @@ -132,8 +131,8 @@ enum { // Register alternate name indices enum { - RISCV_ABIRegAltName, // 0 - RISCV_NoRegAltName, // 1 + RISCV_ABIRegAltName, // 0 + RISCV_NoRegAltName, // 1 RISCV_NUM_TARGET_REG_ALT_NAMES = 2 }; @@ -141,7 +140,7 @@ enum { enum { RISCV_NoSubRegister, - RISCV_sub_32, // 1 + RISCV_sub_32, // 1 RISCV_NUM_TARGET_SUBREGS }; #endif // GET_REGINFO_ENUM @@ -154,273 +153,244 @@ enum { |* *| \*===----------------------------------------------------------------------===*/ - #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg RISCVRegDiffLists[] = { - /* 0 */ 1, 0, - /* 2 */ 32, 0, - /* 4 */ 33, 0, - /* 6 */ 34, 0, - /* 8 */ 35, 0, - /* 10 */ 36, 0, - /* 12 */ 37, 0, - /* 14 */ 38, 0, - /* 16 */ 39, 0, - /* 18 */ 40, 0, - /* 20 */ 41, 0, - /* 22 */ 42, 0, - /* 24 */ 43, 0, - /* 26 */ 44, 0, - /* 28 */ 45, 0, - /* 30 */ 46, 0, - /* 32 */ 47, 0, - /* 34 */ 48, 0, - /* 36 */ 49, 0, - /* 38 */ 50, 0, - /* 40 */ 51, 0, - /* 42 */ 52, 0, - /* 44 */ 53, 0, - /* 46 */ 54, 0, - /* 48 */ 55, 0, - /* 50 */ 56, 0, - /* 52 */ 57, 0, - /* 54 */ 58, 0, - /* 56 */ 59, 0, - /* 58 */ 60, 0, - /* 60 */ 61, 0, - /* 62 */ 62, 0, - /* 64 */ 63, 0, - /* 66 */ 65535, 0, + /* 0 */ 1, 0, + /* 2 */ 32, 0, + /* 4 */ 33, 0, + /* 6 */ 34, 0, + /* 8 */ 35, 0, + /* 10 */ 36, 0, + /* 12 */ 37, 0, + /* 14 */ 38, 0, + /* 16 */ 39, 0, + /* 18 */ 40, 0, + /* 20 */ 41, 0, + /* 22 */ 42, 0, + /* 24 */ 43, 0, + /* 26 */ 44, 0, + /* 28 */ 45, 0, + /* 30 */ 46, 0, + /* 32 */ 47, 0, + /* 34 */ 48, 0, + /* 36 */ 49, 0, + /* 38 */ 50, 0, + /* 40 */ 51, 0, + /* 42 */ 52, 0, + /* 44 */ 53, 0, + /* 46 */ 54, 0, + /* 48 */ 55, 0, + /* 50 */ 56, 0, + /* 52 */ 57, 0, + /* 54 */ 58, 0, + /* 56 */ 59, 0, + /* 58 */ 60, 0, + /* 60 */ 61, 0, + /* 62 */ 62, 0, + /* 64 */ 63, 0, + /* 66 */ 65535, 0, }; static const uint16_t RISCVSubRegIdxLists[] = { - /* 0 */ 1, 0, + /* 0 */ 1, + 0, +}; + +static const MCRegisterDesc RISCVRegDesc[] = { + // Descriptors + {3, 0, 0, 0, 0, 0}, {12, 1, 1, 1, 1057, 0}, {27, 1, 1, 1, 1057, 0}, + {252, 1, 1, 1, 1057, 0}, {263, 1, 1, 1, 1057, 0}, {488, 1, 1, 1, 1057, 0}, + {499, 1, 1, 1, 1057, 0}, {510, 1, 1, 1, 1057, 0}, {521, 1, 1, 1, 1057, 0}, + {532, 1, 1, 1, 1057, 0}, {543, 1, 1, 1, 1057, 0}, {0, 1, 1, 1, 1057, 0}, + {15, 1, 1, 1, 1057, 0}, {30, 1, 1, 1, 1057, 0}, {255, 1, 1, 1, 1057, 0}, + {266, 1, 1, 1, 1057, 0}, {491, 1, 1, 1, 1057, 0}, {502, 1, 1, 1, 1057, 0}, + {513, 1, 1, 1, 1057, 0}, {524, 1, 1, 1, 1057, 0}, {535, 1, 1, 1, 1057, 0}, + {4, 1, 1, 1, 1057, 0}, {19, 1, 1, 1, 1057, 0}, {34, 1, 1, 1, 1057, 0}, + {259, 1, 1, 1, 1057, 0}, {270, 1, 1, 1, 1057, 0}, {495, 1, 1, 1, 1057, 0}, + {506, 1, 1, 1, 1057, 0}, {517, 1, 1, 1, 1057, 0}, {528, 1, 1, 1, 1057, 0}, + {539, 1, 1, 1, 1057, 0}, {8, 1, 1, 1, 1057, 0}, {23, 1, 1, 1, 1057, 0}, + {59, 1, 0, 1, 32, 0}, {295, 66, 1, 0, 32, 2}, {86, 1, 0, 1, 64, 0}, + {322, 66, 1, 0, 64, 2}, {106, 1, 0, 1, 96, 0}, {342, 66, 1, 0, 96, 2}, + {126, 1, 0, 1, 128, 0}, {362, 66, 1, 0, 128, 2}, {146, 1, 0, 1, 160, 0}, + {382, 66, 1, 0, 160, 2}, {166, 1, 0, 1, 192, 0}, {402, 66, 1, 0, 192, 2}, + {186, 1, 0, 1, 224, 0}, {422, 66, 1, 0, 224, 2}, {206, 1, 0, 1, 256, 0}, + {442, 66, 1, 0, 256, 2}, {226, 1, 0, 1, 288, 0}, {462, 66, 1, 0, 288, 2}, + {246, 1, 0, 1, 320, 0}, {482, 66, 1, 0, 320, 2}, {38, 1, 0, 1, 352, 0}, + {274, 66, 1, 0, 352, 2}, {65, 1, 0, 1, 384, 0}, {301, 66, 1, 0, 384, 2}, + {92, 1, 0, 1, 416, 0}, {328, 66, 1, 0, 416, 2}, {112, 1, 0, 1, 448, 0}, + {348, 66, 1, 0, 448, 2}, {132, 1, 0, 1, 480, 0}, {368, 66, 1, 0, 480, 2}, + {152, 1, 0, 1, 512, 0}, {388, 66, 1, 0, 512, 2}, {172, 1, 0, 1, 544, 0}, + {408, 66, 1, 0, 544, 2}, {192, 1, 0, 1, 576, 0}, {428, 66, 1, 0, 576, 2}, + {212, 1, 0, 1, 608, 0}, {448, 66, 1, 0, 608, 2}, {232, 1, 0, 1, 640, 0}, + {468, 66, 1, 0, 640, 2}, {45, 1, 0, 1, 672, 0}, {281, 66, 1, 0, 672, 2}, + {72, 1, 0, 1, 704, 0}, {308, 66, 1, 0, 704, 2}, {99, 1, 0, 1, 736, 0}, + {335, 66, 1, 0, 736, 2}, {119, 1, 0, 1, 768, 0}, {355, 66, 1, 0, 768, 2}, + {139, 1, 0, 1, 800, 0}, {375, 66, 1, 0, 800, 2}, {159, 1, 0, 1, 832, 0}, + {395, 66, 1, 0, 832, 2}, {179, 1, 0, 1, 864, 0}, {415, 66, 1, 0, 864, 2}, + {199, 1, 0, 1, 896, 0}, {435, 66, 1, 0, 896, 2}, {219, 1, 0, 1, 928, 0}, + {455, 66, 1, 0, 928, 2}, {239, 1, 0, 1, 960, 0}, {475, 66, 1, 0, 960, 2}, + {52, 1, 0, 1, 992, 0}, {288, 66, 1, 0, 992, 2}, {79, 1, 0, 1, 1024, 0}, + {315, 66, 1, 0, 1024, 2}, +}; + +// FPR32 Register Class... +static const MCPhysReg FPR32[] = { + RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32, RISCV_F4_32, + RISCV_F5_32, RISCV_F6_32, RISCV_F7_32, RISCV_F10_32, RISCV_F11_32, + RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F16_32, + RISCV_F17_32, RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32, + RISCV_F8_32, RISCV_F9_32, RISCV_F18_32, RISCV_F19_32, RISCV_F20_32, + RISCV_F21_32, RISCV_F22_32, RISCV_F23_32, RISCV_F24_32, RISCV_F25_32, + RISCV_F26_32, RISCV_F27_32, +}; + +// FPR32 Bit set. +static const uint8_t FPR32Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +}; + +// GPR Register Class... +static const MCPhysReg GPR[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, + RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, + RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, + RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, + RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, +}; + +// GPR Bit set. +static const uint8_t GPRBits[] = { + 0xfe, 0xff, 0xff, 0xff, 0x01, }; -static const MCRegisterDesc RISCVRegDesc[] = { // Descriptors - { 3, 0, 0, 0, 0, 0 }, - { 12, 1, 1, 1, 1057, 0 }, - { 27, 1, 1, 1, 1057, 0 }, - { 252, 1, 1, 1, 1057, 0 }, - { 263, 1, 1, 1, 1057, 0 }, - { 488, 1, 1, 1, 1057, 0 }, - { 499, 1, 1, 1, 1057, 0 }, - { 510, 1, 1, 1, 1057, 0 }, - { 521, 1, 1, 1, 1057, 0 }, - { 532, 1, 1, 1, 1057, 0 }, - { 543, 1, 1, 1, 1057, 0 }, - { 0, 1, 1, 1, 1057, 0 }, - { 15, 1, 1, 1, 1057, 0 }, - { 30, 1, 1, 1, 1057, 0 }, - { 255, 1, 1, 1, 1057, 0 }, - { 266, 1, 1, 1, 1057, 0 }, - { 491, 1, 1, 1, 1057, 0 }, - { 502, 1, 1, 1, 1057, 0 }, - { 513, 1, 1, 1, 1057, 0 }, - { 524, 1, 1, 1, 1057, 0 }, - { 535, 1, 1, 1, 1057, 0 }, - { 4, 1, 1, 1, 1057, 0 }, - { 19, 1, 1, 1, 1057, 0 }, - { 34, 1, 1, 1, 1057, 0 }, - { 259, 1, 1, 1, 1057, 0 }, - { 270, 1, 1, 1, 1057, 0 }, - { 495, 1, 1, 1, 1057, 0 }, - { 506, 1, 1, 1, 1057, 0 }, - { 517, 1, 1, 1, 1057, 0 }, - { 528, 1, 1, 1, 1057, 0 }, - { 539, 1, 1, 1, 1057, 0 }, - { 8, 1, 1, 1, 1057, 0 }, - { 23, 1, 1, 1, 1057, 0 }, - { 59, 1, 0, 1, 32, 0 }, - { 295, 66, 1, 0, 32, 2 }, - { 86, 1, 0, 1, 64, 0 }, - { 322, 66, 1, 0, 64, 2 }, - { 106, 1, 0, 1, 96, 0 }, - { 342, 66, 1, 0, 96, 2 }, - { 126, 1, 0, 1, 128, 0 }, - { 362, 66, 1, 0, 128, 2 }, - { 146, 1, 0, 1, 160, 0 }, - { 382, 66, 1, 0, 160, 2 }, - { 166, 1, 0, 1, 192, 0 }, - { 402, 66, 1, 0, 192, 2 }, - { 186, 1, 0, 1, 224, 0 }, - { 422, 66, 1, 0, 224, 2 }, - { 206, 1, 0, 1, 256, 0 }, - { 442, 66, 1, 0, 256, 2 }, - { 226, 1, 0, 1, 288, 0 }, - { 462, 66, 1, 0, 288, 2 }, - { 246, 1, 0, 1, 320, 0 }, - { 482, 66, 1, 0, 320, 2 }, - { 38, 1, 0, 1, 352, 0 }, - { 274, 66, 1, 0, 352, 2 }, - { 65, 1, 0, 1, 384, 0 }, - { 301, 66, 1, 0, 384, 2 }, - { 92, 1, 0, 1, 416, 0 }, - { 328, 66, 1, 0, 416, 2 }, - { 112, 1, 0, 1, 448, 0 }, - { 348, 66, 1, 0, 448, 2 }, - { 132, 1, 0, 1, 480, 0 }, - { 368, 66, 1, 0, 480, 2 }, - { 152, 1, 0, 1, 512, 0 }, - { 388, 66, 1, 0, 512, 2 }, - { 172, 1, 0, 1, 544, 0 }, - { 408, 66, 1, 0, 544, 2 }, - { 192, 1, 0, 1, 576, 0 }, - { 428, 66, 1, 0, 576, 2 }, - { 212, 1, 0, 1, 608, 0 }, - { 448, 66, 1, 0, 608, 2 }, - { 232, 1, 0, 1, 640, 0 }, - { 468, 66, 1, 0, 640, 2 }, - { 45, 1, 0, 1, 672, 0 }, - { 281, 66, 1, 0, 672, 2 }, - { 72, 1, 0, 1, 704, 0 }, - { 308, 66, 1, 0, 704, 2 }, - { 99, 1, 0, 1, 736, 0 }, - { 335, 66, 1, 0, 736, 2 }, - { 119, 1, 0, 1, 768, 0 }, - { 355, 66, 1, 0, 768, 2 }, - { 139, 1, 0, 1, 800, 0 }, - { 375, 66, 1, 0, 800, 2 }, - { 159, 1, 0, 1, 832, 0 }, - { 395, 66, 1, 0, 832, 2 }, - { 179, 1, 0, 1, 864, 0 }, - { 415, 66, 1, 0, 864, 2 }, - { 199, 1, 0, 1, 896, 0 }, - { 435, 66, 1, 0, 896, 2 }, - { 219, 1, 0, 1, 928, 0 }, - { 455, 66, 1, 0, 928, 2 }, - { 239, 1, 0, 1, 960, 0 }, - { 475, 66, 1, 0, 960, 2 }, - { 52, 1, 0, 1, 992, 0 }, - { 288, 66, 1, 0, 992, 2 }, - { 79, 1, 0, 1, 1024, 0 }, - { 315, 66, 1, 0, 1024, 2 }, +// GPRNoX0 Register Class... +static const MCPhysReg GPRNoX0[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, + RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, + RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, + RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, + RISCV_X2, RISCV_X3, RISCV_X4, }; - // FPR32 Register Class... - static const MCPhysReg FPR32[] = { - RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32, RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32, RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F16_32, RISCV_F17_32, RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32, RISCV_F8_32, RISCV_F9_32, RISCV_F18_32, RISCV_F19_32, RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32, RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32, - }; - - // FPR32 Bit set. - static const uint8_t FPR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - }; - - // GPR Register Class... - static const MCPhysReg GPR[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, - }; - - // GPR Bit set. - static const uint8_t GPRBits[] = { - 0xfe, 0xff, 0xff, 0xff, 0x01, - }; - - // GPRNoX0 Register Class... - static const MCPhysReg GPRNoX0[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, - }; - - // GPRNoX0 Bit set. - static const uint8_t GPRNoX0Bits[] = { - 0xfc, 0xff, 0xff, 0xff, 0x01, - }; - - // GPRNoX0X2 Register Class... - static const MCPhysReg GPRNoX0X2[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X3, RISCV_X4, - }; - - // GPRNoX0X2 Bit set. - static const uint8_t GPRNoX0X2Bits[] = { - 0xf4, 0xff, 0xff, 0xff, 0x01, - }; - - // GPRTC Register Class... - static const MCPhysReg GPRTC[] = { - RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, - }; - - // GPRTC Bit set. - static const uint8_t GPRTCBits[] = { - 0xc0, 0xf9, 0x07, 0xe0, 0x01, - }; - - // FPR32C Register Class... - static const MCPhysReg FPR32C[] = { - RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F8_32, RISCV_F9_32, - }; - - // FPR32C Bit set. - static const uint8_t FPR32CBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, - }; - - // GPRC Register Class... - static const MCPhysReg GPRC[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X8, RISCV_X9, - }; - - // GPRC Bit set. - static const uint8_t GPRCBits[] = { - 0x00, 0xfe, 0x01, - }; - - // GPRC_and_GPRTC Register Class... - static const MCPhysReg GPRC_and_GPRTC[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, - }; - - // GPRC_and_GPRTC Bit set. - static const uint8_t GPRC_and_GPRTCBits[] = { - 0x00, 0xf8, 0x01, - }; - - // SP Register Class... - static const MCPhysReg SP[] = { - RISCV_X2, - }; - - // SP Bit set. - static const uint8_t SPBits[] = { - 0x08, - }; - - // FPR64 Register Class... - static const MCPhysReg FPR64[] = { - RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64, RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64, RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F16_64, RISCV_F17_64, RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64, RISCV_F8_64, RISCV_F9_64, RISCV_F18_64, RISCV_F19_64, RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64, RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64, - }; - - // FPR64 Bit set. - static const uint8_t FPR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x01, - }; - - // FPR64C Register Class... - static const MCPhysReg FPR64C[] = { - RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F8_64, RISCV_F9_64, - }; - - // FPR64C Bit set. - static const uint8_t FPR64CBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01, - }; +// GPRNoX0 Bit set. +static const uint8_t GPRNoX0Bits[] = { + 0xfc, 0xff, 0xff, 0xff, 0x01, +}; + +// GPRNoX0X2 Register Class... +static const MCPhysReg GPRNoX0X2[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, + RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, + RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, + RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, + RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X3, RISCV_X4, +}; + +// GPRNoX0X2 Bit set. +static const uint8_t GPRNoX0X2Bits[] = { + 0xf4, 0xff, 0xff, 0xff, 0x01, +}; + +// GPRTC Register Class... +static const MCPhysReg GPRTC[] = { + RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X10, RISCV_X11, + RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, + RISCV_X17, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, +}; + +// GPRTC Bit set. +static const uint8_t GPRTCBits[] = { + 0xc0, 0xf9, 0x07, 0xe0, 0x01, +}; + +// FPR32C Register Class... +static const MCPhysReg FPR32C[] = { + RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, + RISCV_F14_32, RISCV_F15_32, RISCV_F8_32, RISCV_F9_32, +}; + +// FPR32C Bit set. +static const uint8_t FPR32CBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, +}; + +// GPRC Register Class... +static const MCPhysReg GPRC[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, + RISCV_X14, RISCV_X15, RISCV_X8, RISCV_X9, +}; + +// GPRC Bit set. +static const uint8_t GPRCBits[] = { + 0x00, + 0xfe, + 0x01, +}; + +// GPRC_and_GPRTC Register Class... +static const MCPhysReg GPRC_and_GPRTC[] = { + RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, +}; + +// GPRC_and_GPRTC Bit set. +static const uint8_t GPRC_and_GPRTCBits[] = { + 0x00, + 0xf8, + 0x01, +}; + +// SP Register Class... +static const MCPhysReg SP[] = { + RISCV_X2, +}; + +// SP Bit set. +static const uint8_t SPBits[] = { + 0x08, +}; + +// FPR64 Register Class... +static const MCPhysReg FPR64[] = { + RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64, RISCV_F4_64, + RISCV_F5_64, RISCV_F6_64, RISCV_F7_64, RISCV_F10_64, RISCV_F11_64, + RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F16_64, + RISCV_F17_64, RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64, + RISCV_F8_64, RISCV_F9_64, RISCV_F18_64, RISCV_F19_64, RISCV_F20_64, + RISCV_F21_64, RISCV_F22_64, RISCV_F23_64, RISCV_F24_64, RISCV_F25_64, + RISCV_F26_64, RISCV_F27_64, +}; + +// FPR64 Bit set. +static const uint8_t FPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x01, +}; + +// FPR64C Register Class... +static const MCPhysReg FPR64C[] = { + RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, + RISCV_F14_64, RISCV_F15_64, RISCV_F8_64, RISCV_F9_64, +}; + +// FPR64C Bit set. +static const uint8_t FPR64CBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01, +}; static const MCRegisterClass RISCVMCRegisterClasses[] = { - { FPR32, FPR32Bits, sizeof(FPR32Bits) }, - { GPR, GPRBits, sizeof(GPRBits) }, - { GPRNoX0, GPRNoX0Bits, sizeof(GPRNoX0Bits) }, - { GPRNoX0X2, GPRNoX0X2Bits, sizeof(GPRNoX0X2Bits) }, - { GPRTC, GPRTCBits, sizeof(GPRTCBits) }, - { FPR32C, FPR32CBits, sizeof(FPR32CBits) }, - { GPRC, GPRCBits, sizeof(GPRCBits) }, - { GPRC_and_GPRTC, GPRC_and_GPRTCBits, sizeof(GPRC_and_GPRTCBits) }, - { SP, SPBits, sizeof(SPBits) }, - { FPR64, FPR64Bits, sizeof(FPR64Bits) }, - { FPR64C, FPR64CBits, sizeof(FPR64CBits) }, + {FPR32, FPR32Bits, sizeof(FPR32Bits)}, + {GPR, GPRBits, sizeof(GPRBits)}, + {GPRNoX0, GPRNoX0Bits, sizeof(GPRNoX0Bits)}, + {GPRNoX0X2, GPRNoX0X2Bits, sizeof(GPRNoX0X2Bits)}, + {GPRTC, GPRTCBits, sizeof(GPRTCBits)}, + {FPR32C, FPR32CBits, sizeof(FPR32CBits)}, + {GPRC, GPRCBits, sizeof(GPRCBits)}, + {GPRC_and_GPRTC, GPRC_and_GPRTCBits, sizeof(GPRC_and_GPRTCBits)}, + {SP, SPBits, sizeof(SPBits)}, + {FPR64, FPR64Bits, sizeof(FPR64Bits)}, + {FPR64C, FPR64CBits, sizeof(FPR64CBits)}, }; #endif // GET_REGINFO_MC_DESC diff --git a/arch/RISCV/RISCVGenSubtargetInfo.inc b/arch/RISCV/RISCVGenSubtargetInfo.inc index c857ce6c1c..c23c24927c 100644 --- a/arch/RISCV/RISCVGenSubtargetInfo.inc +++ b/arch/RISCV/RISCVGenSubtargetInfo.inc @@ -9,25 +9,23 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ - #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM /* - Make sure: + Make sure: CS_MODE_RISCV64 = 0b11111 CS_MODE_RISCV32 = 0b11110 */ enum { - RISCV_Feature64Bit = 1ULL << 0, + RISCV_Feature64Bit = 1ULL << 0, RISCV_FeatureStdExtA = 1ULL << 1, RISCV_FeatureStdExtC = 1ULL << 2, RISCV_FeatureStdExtD = 1ULL << 3, RISCV_FeatureStdExtF = 1ULL << 4, RISCV_FeatureStdExtM = 1ULL << 5, - RISCV_FeatureRelax = 1ULL << 6, + RISCV_FeatureRelax = 1ULL << 6, }; #endif // GET_SUBTARGETINFO_ENUM - diff --git a/arch/RISCV/RISCVInstPrinter.c b/arch/RISCV/RISCVInstPrinter.c index 41e68b3040..ecb9c032a3 100644 --- a/arch/RISCV/RISCVInstPrinter.c +++ b/arch/RISCV/RISCVInstPrinter.c @@ -13,35 +13,36 @@ #ifdef CAPSTONE_HAS_RISCV -#include // DEBUG +#include +#include // DEBUG #include #include -#include -#include "RISCVInstPrinter.h" -#include "RISCVBaseInfo.h" #include "../../MCInst.h" -#include "../../SStream.h" #include "../../MCRegisterInfo.h" +#include "../../SStream.h" #include "../../utils.h" +#include "RISCVBaseInfo.h" +#include "RISCVInstPrinter.h" #include "RISCVMapping.h" -//#include "RISCVDisassembler.h" +#include "../../MCInstPrinter.h" -#define GET_REGINFO_ENUM -#define GET_REGINFO_MC_DESC -#include "RISCVGenRegisterInfo.inc" -#define GET_INSTRINFO_ENUM -#include "RISCVGenInstrInfo.inc" +//#include "RISCVDisassembler.h" // Autogenerated by tblgen. -static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); -static bool printAliasInstr(MCInst *MI, SStream *OS, void *info); +static void printInstruction(MCInst *MI, SStream *O); +static char *printAliasInstr(MCInst *MI, SStream *OS); static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O); -static void printCSRSystemRegister(MCInst*, unsigned, SStream *); +static void printCSRSystemRegister(MCInst *, unsigned, SStream *); static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O); -static void printCustomAliasOperand( MCInst *, unsigned, unsigned, SStream *); +static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printVMaskReg(MCInst *MI, unsigned OpNo, SStream *O); +static void printAtomicMemOp(MCInst *MI, unsigned OpNo, SStream *O); +static void printVTypeI(MCInst *MI, unsigned OpNo, SStream *O); +static void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. @@ -49,399 +50,707 @@ static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); // Include the auto-generated portion of the assembly writer. #define PRINT_ALIAS_INSTR -#include "RISCVGenAsmWriter.inc" - - -static void fixDetailOfEffectiveAddr(MCInst *MI) -{ - unsigned reg = 0; - int64_t imm = 0; - - CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); - CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[0].type); - - if (RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[1].type) { - CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[2].type); - imm = MI->flat_insn->detail->riscv.operands[1].imm; - reg = MI->flat_insn->detail->riscv.operands[2].reg; - } else if (RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[1].type) { - CS_ASSERT(RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[2].type); - reg = MI->flat_insn->detail->riscv.operands[1].reg; - imm = MI->flat_insn->detail->riscv.operands[2].imm; - } - - // set up effective address. - MI->flat_insn->detail->riscv.operands[1].type = RISCV_OP_MEM; - MI->flat_insn->detail->riscv.op_count--; - MI->flat_insn->detail->riscv.operands[1].mem.base = reg; - MI->flat_insn->detail->riscv.operands[1].mem.disp = imm; - - return; +#define GET_REGINFO_ENUM +#define GET_REGINFO_MC_DESC +#define GET_INSTRINFO_ENUM +#define GET_ASM_WRITER +#include "RISCVGenDisassemblerTables.inc" + +static void fixDetailOfEffectiveAddr(MCInst *MI) { + unsigned reg = 0; + int64_t imm = 0; + + CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); + CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[0].type); + + if (RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[1].type) { + CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[2].type); + imm = MI->flat_insn->detail->riscv.operands[1].imm; + reg = MI->flat_insn->detail->riscv.operands[2].reg; + } else if (RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[1].type) { + CS_ASSERT(RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[2].type); + reg = MI->flat_insn->detail->riscv.operands[1].reg; + imm = MI->flat_insn->detail->riscv.operands[2].imm; + } + + // set up effective address. + MI->flat_insn->detail->riscv.operands[1].type = RISCV_OP_MEM; + MI->flat_insn->detail->riscv.op_count--; + MI->flat_insn->detail->riscv.operands[1].mem.base = reg; + MI->flat_insn->detail->riscv.operands[1].mem.disp = imm; + + return; } - -//void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O, -// StringRef Annot, const MCSubtargetInfo &STI) -void RISCV_printInst(MCInst *MI, SStream *O, void *info) -{ - MCRegisterInfo *MRI = (MCRegisterInfo *) info; - //bool Res = false; - //MCInst *NewMI = MI; - // TODO: RISCV compressd instructions. - //MCInst UncompressedMI; - //if (!NoAliases) - //Res = uncompressInst(UncompressedMI, *MI, MRI, STI); - //if (Res) - //NewMI = const_cast(&UncompressedMI); - if (/*NoAliases ||*/ !printAliasInstr(MI, O, info)) - printInstruction(MI, O, MRI); - //printAnnotation(O, Annot); - // fix load/store type insttuction - if (MI->csh->detail && - MI->flat_insn->detail->riscv.need_effective_addr) - fixDetailOfEffectiveAddr(MI); - - return; +// void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O, +// StringRef Annot, const MCSubtargetInfo &STI) +void RISCV_printInst(MCInst *MI, SStream *O, void *info) { + MRI = info; + MCRegisterInfo *MRI = (MCRegisterInfo *)info; + // bool Res = false; + // MCInst *NewMI = MI; + // TODO: RISCV compressd instructions. + // MCInst UncompressedMI; + // if (!NoAliases) + // Res = uncompressInst(UncompressedMI, *MI, MRI, STI); + // if (Res) + // NewMI = const_cast(&UncompressedMI); + if (/*NoAliases ||*/ !printAliasInstr(MI, O)) + printInstruction(MI, O); + // printAnnotation(O, Annot); + // fix load/store type insttuction + if (MI->csh->detail && MI->flat_insn->detail->riscv.need_effective_addr) + fixDetailOfEffectiveAddr(MI); + + return; } -static void printRegName(SStream *OS, unsigned RegNo) -{ - SStream_concat0(OS, getRegisterName(RegNo, RISCV_ABIRegAltName)); +static void printRegName(SStream *OS, unsigned RegNo) { + SStream_concat0(OS, getRegisterName(RegNo, RISCV_ABIRegAltName)); } /** void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O, const char *Modifier) + raw_ostream &O, const char *Modifier) */ -static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned reg; - int64_t Imm = 0; - - MCOperand *MO = MCInst_getOperand(MI, OpNo); - - if (MCOperand_isReg(MO)) { - reg = MCOperand_getReg(MO); - printRegName(O, reg); - if (MI->csh->detail) { - MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].type = RISCV_OP_REG; - MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].reg = reg; - MI->flat_insn->detail->riscv.op_count++; - } - } else { - CS_ASSERT(MCOperand_isImm(MO) && "Unknown operand kind in printOperand"); - Imm = MCOperand_getImm(MO); - if (Imm >= 0) { - if (Imm > HEX_THRESHOLD) - SStream_concat(O, "0x%" PRIx64, Imm); - else - SStream_concat(O, "%" PRIu64, Imm); - } else { - if (Imm < -HEX_THRESHOLD) - SStream_concat(O, "-0x%" PRIx64, -Imm); - else - SStream_concat(O, "-%" PRIu64, -Imm); - } - - if (MI->csh->detail) { - MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].type = RISCV_OP_IMM; - MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].imm = Imm; - MI->flat_insn->detail->riscv.op_count++; - } - } - - //CS_ASSERT(MO.isExpr() && "Unknown operand kind in printOperand"); - - return; +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned reg; + int64_t Imm = 0; + + MCOperand *MO = MCInst_getOperand(MI, OpNo); + + if (MCOperand_isReg(MO)) { + reg = MCOperand_getReg(MO); + printRegName(O, reg); + if (MI->csh->detail) { + MI->flat_insn->detail->riscv + .operands[MI->flat_insn->detail->riscv.op_count] + .type = RISCV_OP_REG; + MI->flat_insn->detail->riscv + .operands[MI->flat_insn->detail->riscv.op_count] + .reg = reg; + MI->flat_insn->detail->riscv.op_count++; + } + } else { + CS_ASSERT(MCOperand_isImm(MO) && "Unknown operand kind in printOperand"); + Imm = MCOperand_getImm(MO); + if (Imm >= 0) { + if (Imm > HEX_THRESHOLD) + SStream_concat(O, "0x%" PRIx64, Imm); + else + SStream_concat(O, "%" PRIu64, Imm); + } else { + if (Imm < -HEX_THRESHOLD) + SStream_concat(O, "-0x%" PRIx64, -Imm); + else + SStream_concat(O, "-%" PRIu64, -Imm); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->riscv + .operands[MI->flat_insn->detail->riscv.op_count] + .type = RISCV_OP_IMM; + MI->flat_insn->detail->riscv + .operands[MI->flat_insn->detail->riscv.op_count] + .imm = Imm; + MI->flat_insn->detail->riscv.op_count++; + } + } + + // CS_ASSERT(MO.isExpr() && "Unknown operand kind in printOperand"); + + return; } -static const char *getCSRSystemRegisterName(unsigned CsrNo) -{ - switch (CsrNo) { - /* - * From RISC-V Privileged Architecture Version 1.10. - * In the same order as Table 2.5. - */ - case 0x0000: return "ustatus"; - case 0x0004: return "uie"; - case 0x0005: return "utvec"; - - case 0x0040: return "uscratch"; - case 0x0041: return "uepc"; - case 0x0042: return "ucause"; - case 0x0043: return "utval"; - case 0x0044: return "uip"; - - case 0x0001: return "fflags"; - case 0x0002: return "frm"; - case 0x0003: return "fcsr"; - - case 0x0c00: return "cycle"; - case 0x0c01: return "time"; - case 0x0c02: return "instret"; - case 0x0c03: return "hpmcounter3"; - case 0x0c04: return "hpmcounter4"; - case 0x0c05: return "hpmcounter5"; - case 0x0c06: return "hpmcounter6"; - case 0x0c07: return "hpmcounter7"; - case 0x0c08: return "hpmcounter8"; - case 0x0c09: return "hpmcounter9"; - case 0x0c0a: return "hpmcounter10"; - case 0x0c0b: return "hpmcounter11"; - case 0x0c0c: return "hpmcounter12"; - case 0x0c0d: return "hpmcounter13"; - case 0x0c0e: return "hpmcounter14"; - case 0x0c0f: return "hpmcounter15"; - case 0x0c10: return "hpmcounter16"; - case 0x0c11: return "hpmcounter17"; - case 0x0c12: return "hpmcounter18"; - case 0x0c13: return "hpmcounter19"; - case 0x0c14: return "hpmcounter20"; - case 0x0c15: return "hpmcounter21"; - case 0x0c16: return "hpmcounter22"; - case 0x0c17: return "hpmcounter23"; - case 0x0c18: return "hpmcounter24"; - case 0x0c19: return "hpmcounter25"; - case 0x0c1a: return "hpmcounter26"; - case 0x0c1b: return "hpmcounter27"; - case 0x0c1c: return "hpmcounter28"; - case 0x0c1d: return "hpmcounter29"; - case 0x0c1e: return "hpmcounter30"; - case 0x0c1f: return "hpmcounter31"; - case 0x0c80: return "cycleh"; - case 0x0c81: return "timeh"; - case 0x0c82: return "instreth"; - case 0x0c83: return "hpmcounter3h"; - case 0x0c84: return "hpmcounter4h"; - case 0x0c85: return "hpmcounter5h"; - case 0x0c86: return "hpmcounter6h"; - case 0x0c87: return "hpmcounter7h"; - case 0x0c88: return "hpmcounter8h"; - case 0x0c89: return "hpmcounter9h"; - case 0x0c8a: return "hpmcounter10h"; - case 0x0c8b: return "hpmcounter11h"; - case 0x0c8c: return "hpmcounter12h"; - case 0x0c8d: return "hpmcounter13h"; - case 0x0c8e: return "hpmcounter14h"; - case 0x0c8f: return "hpmcounter15h"; - case 0x0c90: return "hpmcounter16h"; - case 0x0c91: return "hpmcounter17h"; - case 0x0c92: return "hpmcounter18h"; - case 0x0c93: return "hpmcounter19h"; - case 0x0c94: return "hpmcounter20h"; - case 0x0c95: return "hpmcounter21h"; - case 0x0c96: return "hpmcounter22h"; - case 0x0c97: return "hpmcounter23h"; - case 0x0c98: return "hpmcounter24h"; - case 0x0c99: return "hpmcounter25h"; - case 0x0c9a: return "hpmcounter26h"; - case 0x0c9b: return "hpmcounter27h"; - case 0x0c9c: return "hpmcounter28h"; - case 0x0c9d: return "hpmcounter29h"; - case 0x0c9e: return "hpmcounter30h"; - case 0x0c9f: return "hpmcounter31h"; - - case 0x0100: return "sstatus"; - case 0x0102: return "sedeleg"; - case 0x0103: return "sideleg"; - case 0x0104: return "sie"; - case 0x0105: return "stvec"; - case 0x0106: return "scounteren"; - - case 0x0140: return "sscratch"; - case 0x0141: return "sepc"; - case 0x0142: return "scause"; - case 0x0143: return "stval"; - case 0x0144: return "sip"; - - case 0x0180: return "satp"; - - case 0x0f11: return "mvendorid"; - case 0x0f12: return "marchid"; - case 0x0f13: return "mimpid"; - case 0x0f14: return "mhartid"; - - case 0x0300: return "mstatus"; - case 0x0301: return "misa"; - case 0x0302: return "medeleg"; - case 0x0303: return "mideleg"; - case 0x0304: return "mie"; - case 0x0305: return "mtvec"; - case 0x0306: return "mcounteren"; - - case 0x0340: return "mscratch"; - case 0x0341: return "mepc"; - case 0x0342: return "mcause"; - case 0x0343: return "mtval"; - case 0x0344: return "mip"; - - case 0x03a0: return "pmpcfg0"; - case 0x03a1: return "pmpcfg1"; - case 0x03a2: return "pmpcfg2"; - case 0x03a3: return "pmpcfg3"; - case 0x03b0: return "pmpaddr0"; - case 0x03b1: return "pmpaddr1"; - case 0x03b2: return "pmpaddr2"; - case 0x03b3: return "pmpaddr3"; - case 0x03b4: return "pmpaddr4"; - case 0x03b5: return "pmpaddr5"; - case 0x03b6: return "pmpaddr6"; - case 0x03b7: return "pmpaddr7"; - case 0x03b8: return "pmpaddr8"; - case 0x03b9: return "pmpaddr9"; - case 0x03ba: return "pmpaddr10"; - case 0x03bb: return "pmpaddr11"; - case 0x03bc: return "pmpaddr12"; - case 0x03bd: return "pmpaddr14"; - case 0x03be: return "pmpaddr13"; - case 0x03bf: return "pmpaddr15"; - - case 0x0b00: return "mcycle"; - case 0x0b02: return "minstret"; - case 0x0b03: return "mhpmcounter3"; - case 0x0b04: return "mhpmcounter4"; - case 0x0b05: return "mhpmcounter5"; - case 0x0b06: return "mhpmcounter6"; - case 0x0b07: return "mhpmcounter7"; - case 0x0b08: return "mhpmcounter8"; - case 0x0b09: return "mhpmcounter9"; - case 0x0b0a: return "mhpmcounter10"; - case 0x0b0b: return "mhpmcounter11"; - case 0x0b0c: return "mhpmcounter12"; - case 0x0b0d: return "mhpmcounter13"; - case 0x0b0e: return "mhpmcounter14"; - case 0x0b0f: return "mhpmcounter15"; - case 0x0b10: return "mhpmcounter16"; - case 0x0b11: return "mhpmcounter17"; - case 0x0b12: return "mhpmcounter18"; - case 0x0b13: return "mhpmcounter19"; - case 0x0b14: return "mhpmcounter20"; - case 0x0b15: return "mhpmcounter21"; - case 0x0b16: return "mhpmcounter22"; - case 0x0b17: return "mhpmcounter23"; - case 0x0b18: return "mhpmcounter24"; - case 0x0b19: return "mhpmcounter25"; - case 0x0b1a: return "mhpmcounter26"; - case 0x0b1b: return "mhpmcounter27"; - case 0x0b1c: return "mhpmcounter28"; - case 0x0b1d: return "mhpmcounter29"; - case 0x0b1e: return "mhpmcounter30"; - case 0x0b1f: return "mhpmcounter31"; - case 0x0b80: return "mcycleh"; - case 0x0b82: return "minstreth"; - case 0x0b83: return "mhpmcounter3h"; - case 0x0b84: return "mhpmcounter4h"; - case 0x0b85: return "mhpmcounter5h"; - case 0x0b86: return "mhpmcounter6h"; - case 0x0b87: return "mhpmcounter7h"; - case 0x0b88: return "mhpmcounter8h"; - case 0x0b89: return "mhpmcounter9h"; - case 0x0b8a: return "mhpmcounter10h"; - case 0x0b8b: return "mhpmcounter11h"; - case 0x0b8c: return "mhpmcounter12h"; - case 0x0b8d: return "mhpmcounter13h"; - case 0x0b8e: return "mhpmcounter14h"; - case 0x0b8f: return "mhpmcounter15h"; - case 0x0b90: return "mhpmcounter16h"; - case 0x0b91: return "mhpmcounter17h"; - case 0x0b92: return "mhpmcounter18h"; - case 0x0b93: return "mhpmcounter19h"; - case 0x0b94: return "mhpmcounter20h"; - case 0x0b95: return "mhpmcounter21h"; - case 0x0b96: return "mhpmcounter22h"; - case 0x0b97: return "mhpmcounter23h"; - case 0x0b98: return "mhpmcounter24h"; - case 0x0b99: return "mhpmcounter25h"; - case 0x0b9a: return "mhpmcounter26h"; - case 0x0b9b: return "mhpmcounter27h"; - case 0x0b9c: return "mhpmcounter28h"; - case 0x0b9d: return "mhpmcounter29h"; - case 0x0b9e: return "mhpmcounter30h"; - case 0x0b9f: return "mhpmcounter31h"; - - case 0x0323: return "mhpmevent3"; - case 0x0324: return "mhpmevent4"; - case 0x0325: return "mhpmevent5"; - case 0x0326: return "mhpmevent6"; - case 0x0327: return "mhpmevent7"; - case 0x0328: return "mhpmevent8"; - case 0x0329: return "mhpmevent9"; - case 0x032a: return "mhpmevent10"; - case 0x032b: return "mhpmevent11"; - case 0x032c: return "mhpmevent12"; - case 0x032d: return "mhpmevent13"; - case 0x032e: return "mhpmevent14"; - case 0x032f: return "mhpmevent15"; - case 0x0330: return "mhpmevent16"; - case 0x0331: return "mhpmevent17"; - case 0x0332: return "mhpmevent18"; - case 0x0333: return "mhpmevent19"; - case 0x0334: return "mhpmevent20"; - case 0x0335: return "mhpmevent21"; - case 0x0336: return "mhpmevent22"; - case 0x0337: return "mhpmevent23"; - case 0x0338: return "mhpmevent24"; - case 0x0339: return "mhpmevent25"; - case 0x033a: return "mhpmevent26"; - case 0x033b: return "mhpmevent27"; - case 0x033c: return "mhpmevent28"; - case 0x033d: return "mhpmevent29"; - case 0x033e: return "mhpmevent30"; - case 0x033f: return "mhpmevent31"; - - case 0x07a0: return "tselect"; - case 0x07a1: return "tdata1"; - case 0x07a2: return "tdata2"; - case 0x07a3: return "tdata3"; - - case 0x07b0: return "dcsr"; - case 0x07b1: return "dpc"; - case 0x07b2: return "dscratch"; - } - return NULL; +static const char *getCSRSystemRegisterName(unsigned CsrNo) { + switch (CsrNo) { + /* + * From RISC-V Privileged Architecture Version 1.10. + * In the same order as Table 2.5. + */ + case 0x0000: + return "ustatus"; + case 0x0004: + return "uie"; + case 0x0005: + return "utvec"; + + case 0x0040: + return "uscratch"; + case 0x0041: + return "uepc"; + case 0x0042: + return "ucause"; + case 0x0043: + return "utval"; + case 0x0044: + return "uip"; + + case 0x0001: + return "fflags"; + case 0x0002: + return "frm"; + case 0x0003: + return "fcsr"; + + case 0x0c00: + return "cycle"; + case 0x0c01: + return "time"; + case 0x0c02: + return "instret"; + case 0x0c03: + return "hpmcounter3"; + case 0x0c04: + return "hpmcounter4"; + case 0x0c05: + return "hpmcounter5"; + case 0x0c06: + return "hpmcounter6"; + case 0x0c07: + return "hpmcounter7"; + case 0x0c08: + return "hpmcounter8"; + case 0x0c09: + return "hpmcounter9"; + case 0x0c0a: + return "hpmcounter10"; + case 0x0c0b: + return "hpmcounter11"; + case 0x0c0c: + return "hpmcounter12"; + case 0x0c0d: + return "hpmcounter13"; + case 0x0c0e: + return "hpmcounter14"; + case 0x0c0f: + return "hpmcounter15"; + case 0x0c10: + return "hpmcounter16"; + case 0x0c11: + return "hpmcounter17"; + case 0x0c12: + return "hpmcounter18"; + case 0x0c13: + return "hpmcounter19"; + case 0x0c14: + return "hpmcounter20"; + case 0x0c15: + return "hpmcounter21"; + case 0x0c16: + return "hpmcounter22"; + case 0x0c17: + return "hpmcounter23"; + case 0x0c18: + return "hpmcounter24"; + case 0x0c19: + return "hpmcounter25"; + case 0x0c1a: + return "hpmcounter26"; + case 0x0c1b: + return "hpmcounter27"; + case 0x0c1c: + return "hpmcounter28"; + case 0x0c1d: + return "hpmcounter29"; + case 0x0c1e: + return "hpmcounter30"; + case 0x0c1f: + return "hpmcounter31"; + case 0x0c80: + return "cycleh"; + case 0x0c81: + return "timeh"; + case 0x0c82: + return "instreth"; + case 0x0c83: + return "hpmcounter3h"; + case 0x0c84: + return "hpmcounter4h"; + case 0x0c85: + return "hpmcounter5h"; + case 0x0c86: + return "hpmcounter6h"; + case 0x0c87: + return "hpmcounter7h"; + case 0x0c88: + return "hpmcounter8h"; + case 0x0c89: + return "hpmcounter9h"; + case 0x0c8a: + return "hpmcounter10h"; + case 0x0c8b: + return "hpmcounter11h"; + case 0x0c8c: + return "hpmcounter12h"; + case 0x0c8d: + return "hpmcounter13h"; + case 0x0c8e: + return "hpmcounter14h"; + case 0x0c8f: + return "hpmcounter15h"; + case 0x0c90: + return "hpmcounter16h"; + case 0x0c91: + return "hpmcounter17h"; + case 0x0c92: + return "hpmcounter18h"; + case 0x0c93: + return "hpmcounter19h"; + case 0x0c94: + return "hpmcounter20h"; + case 0x0c95: + return "hpmcounter21h"; + case 0x0c96: + return "hpmcounter22h"; + case 0x0c97: + return "hpmcounter23h"; + case 0x0c98: + return "hpmcounter24h"; + case 0x0c99: + return "hpmcounter25h"; + case 0x0c9a: + return "hpmcounter26h"; + case 0x0c9b: + return "hpmcounter27h"; + case 0x0c9c: + return "hpmcounter28h"; + case 0x0c9d: + return "hpmcounter29h"; + case 0x0c9e: + return "hpmcounter30h"; + case 0x0c9f: + return "hpmcounter31h"; + + case 0x0100: + return "sstatus"; + case 0x0102: + return "sedeleg"; + case 0x0103: + return "sideleg"; + case 0x0104: + return "sie"; + case 0x0105: + return "stvec"; + case 0x0106: + return "scounteren"; + + case 0x0140: + return "sscratch"; + case 0x0141: + return "sepc"; + case 0x0142: + return "scause"; + case 0x0143: + return "stval"; + case 0x0144: + return "sip"; + + case 0x0180: + return "satp"; + + case 0x0f11: + return "mvendorid"; + case 0x0f12: + return "marchid"; + case 0x0f13: + return "mimpid"; + case 0x0f14: + return "mhartid"; + + case 0x0300: + return "mstatus"; + case 0x0301: + return "misa"; + case 0x0302: + return "medeleg"; + case 0x0303: + return "mideleg"; + case 0x0304: + return "mie"; + case 0x0305: + return "mtvec"; + case 0x0306: + return "mcounteren"; + + case 0x0340: + return "mscratch"; + case 0x0341: + return "mepc"; + case 0x0342: + return "mcause"; + case 0x0343: + return "mtval"; + case 0x0344: + return "mip"; + + case 0x03a0: + return "pmpcfg0"; + case 0x03a1: + return "pmpcfg1"; + case 0x03a2: + return "pmpcfg2"; + case 0x03a3: + return "pmpcfg3"; + case 0x03b0: + return "pmpaddr0"; + case 0x03b1: + return "pmpaddr1"; + case 0x03b2: + return "pmpaddr2"; + case 0x03b3: + return "pmpaddr3"; + case 0x03b4: + return "pmpaddr4"; + case 0x03b5: + return "pmpaddr5"; + case 0x03b6: + return "pmpaddr6"; + case 0x03b7: + return "pmpaddr7"; + case 0x03b8: + return "pmpaddr8"; + case 0x03b9: + return "pmpaddr9"; + case 0x03ba: + return "pmpaddr10"; + case 0x03bb: + return "pmpaddr11"; + case 0x03bc: + return "pmpaddr12"; + case 0x03bd: + return "pmpaddr14"; + case 0x03be: + return "pmpaddr13"; + case 0x03bf: + return "pmpaddr15"; + + case 0x0b00: + return "mcycle"; + case 0x0b02: + return "minstret"; + case 0x0b03: + return "mhpmcounter3"; + case 0x0b04: + return "mhpmcounter4"; + case 0x0b05: + return "mhpmcounter5"; + case 0x0b06: + return "mhpmcounter6"; + case 0x0b07: + return "mhpmcounter7"; + case 0x0b08: + return "mhpmcounter8"; + case 0x0b09: + return "mhpmcounter9"; + case 0x0b0a: + return "mhpmcounter10"; + case 0x0b0b: + return "mhpmcounter11"; + case 0x0b0c: + return "mhpmcounter12"; + case 0x0b0d: + return "mhpmcounter13"; + case 0x0b0e: + return "mhpmcounter14"; + case 0x0b0f: + return "mhpmcounter15"; + case 0x0b10: + return "mhpmcounter16"; + case 0x0b11: + return "mhpmcounter17"; + case 0x0b12: + return "mhpmcounter18"; + case 0x0b13: + return "mhpmcounter19"; + case 0x0b14: + return "mhpmcounter20"; + case 0x0b15: + return "mhpmcounter21"; + case 0x0b16: + return "mhpmcounter22"; + case 0x0b17: + return "mhpmcounter23"; + case 0x0b18: + return "mhpmcounter24"; + case 0x0b19: + return "mhpmcounter25"; + case 0x0b1a: + return "mhpmcounter26"; + case 0x0b1b: + return "mhpmcounter27"; + case 0x0b1c: + return "mhpmcounter28"; + case 0x0b1d: + return "mhpmcounter29"; + case 0x0b1e: + return "mhpmcounter30"; + case 0x0b1f: + return "mhpmcounter31"; + case 0x0b80: + return "mcycleh"; + case 0x0b82: + return "minstreth"; + case 0x0b83: + return "mhpmcounter3h"; + case 0x0b84: + return "mhpmcounter4h"; + case 0x0b85: + return "mhpmcounter5h"; + case 0x0b86: + return "mhpmcounter6h"; + case 0x0b87: + return "mhpmcounter7h"; + case 0x0b88: + return "mhpmcounter8h"; + case 0x0b89: + return "mhpmcounter9h"; + case 0x0b8a: + return "mhpmcounter10h"; + case 0x0b8b: + return "mhpmcounter11h"; + case 0x0b8c: + return "mhpmcounter12h"; + case 0x0b8d: + return "mhpmcounter13h"; + case 0x0b8e: + return "mhpmcounter14h"; + case 0x0b8f: + return "mhpmcounter15h"; + case 0x0b90: + return "mhpmcounter16h"; + case 0x0b91: + return "mhpmcounter17h"; + case 0x0b92: + return "mhpmcounter18h"; + case 0x0b93: + return "mhpmcounter19h"; + case 0x0b94: + return "mhpmcounter20h"; + case 0x0b95: + return "mhpmcounter21h"; + case 0x0b96: + return "mhpmcounter22h"; + case 0x0b97: + return "mhpmcounter23h"; + case 0x0b98: + return "mhpmcounter24h"; + case 0x0b99: + return "mhpmcounter25h"; + case 0x0b9a: + return "mhpmcounter26h"; + case 0x0b9b: + return "mhpmcounter27h"; + case 0x0b9c: + return "mhpmcounter28h"; + case 0x0b9d: + return "mhpmcounter29h"; + case 0x0b9e: + return "mhpmcounter30h"; + case 0x0b9f: + return "mhpmcounter31h"; + + case 0x0323: + return "mhpmevent3"; + case 0x0324: + return "mhpmevent4"; + case 0x0325: + return "mhpmevent5"; + case 0x0326: + return "mhpmevent6"; + case 0x0327: + return "mhpmevent7"; + case 0x0328: + return "mhpmevent8"; + case 0x0329: + return "mhpmevent9"; + case 0x032a: + return "mhpmevent10"; + case 0x032b: + return "mhpmevent11"; + case 0x032c: + return "mhpmevent12"; + case 0x032d: + return "mhpmevent13"; + case 0x032e: + return "mhpmevent14"; + case 0x032f: + return "mhpmevent15"; + case 0x0330: + return "mhpmevent16"; + case 0x0331: + return "mhpmevent17"; + case 0x0332: + return "mhpmevent18"; + case 0x0333: + return "mhpmevent19"; + case 0x0334: + return "mhpmevent20"; + case 0x0335: + return "mhpmevent21"; + case 0x0336: + return "mhpmevent22"; + case 0x0337: + return "mhpmevent23"; + case 0x0338: + return "mhpmevent24"; + case 0x0339: + return "mhpmevent25"; + case 0x033a: + return "mhpmevent26"; + case 0x033b: + return "mhpmevent27"; + case 0x033c: + return "mhpmevent28"; + case 0x033d: + return "mhpmevent29"; + case 0x033e: + return "mhpmevent30"; + case 0x033f: + return "mhpmevent31"; + + case 0x07a0: + return "tselect"; + case 0x07a1: + return "tdata1"; + case 0x07a2: + return "tdata2"; + case 0x07a3: + return "tdata3"; + + case 0x07b0: + return "dcsr"; + case 0x07b1: + return "dpc"; + case 0x07b2: + return "dscratch"; + } + return NULL; } static void printCSRSystemRegister(MCInst *MI, unsigned OpNo, - //const MCSubtargetInfo &STI, - SStream *O) -{ - unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - const char *Name = getCSRSystemRegisterName(Imm); - - if (Name) { - SStream_concat0(O, Name); - } else { - SStream_concat(O, "%u", Imm); - } + // const MCSubtargetInfo &STI, + SStream *O) { + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + const char *Name = getCSRSystemRegisterName(Imm); + + if (Name) { + SStream_concat0(O, Name); + } else { + SStream_concat(O, "%u", Imm); + } } -static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned FenceArg = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //CS_ASSERT (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); - - if ((FenceArg & RISCVFenceField_I) != 0) - SStream_concat0(O, "i"); - if ((FenceArg & RISCVFenceField_O) != 0) - SStream_concat0(O, "o"); - if ((FenceArg & RISCVFenceField_R) != 0) - SStream_concat0(O, "r"); - if ((FenceArg & RISCVFenceField_W) != 0) - SStream_concat0(O, "w"); - if (FenceArg == 0) - SStream_concat0(O, "unknown"); +static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned FenceArg = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + // CS_ASSERT (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); + + if ((FenceArg & RISCVFenceField_I) != 0) + SStream_concat0(O, "i"); + if ((FenceArg & RISCVFenceField_O) != 0) + SStream_concat0(O, "o"); + if ((FenceArg & RISCVFenceField_R) != 0) + SStream_concat0(O, "r"); + if ((FenceArg & RISCVFenceField_W) != 0) + SStream_concat0(O, "w"); + if (FenceArg == 0) + SStream_concat0(O, "unknown"); } -static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O) -{ - enum RoundingMode FRMArg = - (enum RoundingMode)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); +static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O) { + enum RoundingMode FRMArg = + (enum RoundingMode)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); #if 0 auto FRMArg = static_cast(MI->getOperand(OpNo).getImm()); O << RISCVFPRndMode::roundingModeToString(FRMArg); #endif - SStream_concat0(O, roundingModeToString(FRMArg)); + SStream_concat0(O, roundingModeToString(FRMArg)); } - -#endif // CAPSTONE_HAS_RISCV + +static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O) { + + MCOperand *MO = MCInst_getOperand(MI, OpNo); + if (!MCOperand_isImm(MO)) + printOperand(MI, OpNo, O); + + // if (PrintBranchImmAsAddress) { - just in it's simplest way + // uint64_t Target = Address + MO.getImm(); + // if (!STI.hasFeature(RISCV::Feature64Bit)) + // Target &= 0xffffffff; + // O << formatHex(Target); + // } else { + // O << MO.getImm(); + // } + + SStream_concat(O, "%u", MCOperand_getImm(MO)); +} + +void printVMaskReg(MCInst *MI, unsigned OpNo, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNo); + + // printVMaskReg can only print register operands + if (MCOperand_getReg(MO) == 0) // No Register + return; + SStream_concat0(O, ", "); + printRegName(O, MCOperand_getReg(MO)); + SStream_concat0(O, ".t"); +} + +void printAtomicMemOp(MCInst *MI, unsigned OpNo, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNo); + + // printAtomicMemOp can only print register operands + SStream_concat0(O, "("); + printRegName(O, MCOperand_getReg(MO)); + SStream_concat0(O, ")"); +} + +inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; } + +inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; } + +void printVType(unsigned VType, SStream *O) { + unsigned VSEW = getVSEW(VType); + unsigned VLMUL = getVLMUL(VType); + + unsigned Sew = 1 << (VSEW + 3); + SStream_concat(O, "e%u", Sew); + + switch (VLMUL) { + case RISCVVLMUL_LMUL_RESERVED: + llvm_unreachable("Unexpected LMUL value!"); + case RISCVVLMUL_LMUL_1: + case RISCVVLMUL_LMUL_2: + case RISCVVLMUL_LMUL_4: + case RISCVVLMUL_LMUL_8: { + unsigned LMul = 1 << VLMUL; + SStream_concat(O, ",m%u", LMul); + break; + } + case RISCVVLMUL_LMUL_F2: + case RISCVVLMUL_LMUL_F4: + case RISCVVLMUL_LMUL_F8: { + unsigned LMul = 1 << (8 - VLMUL); + SStream_concat(O, ",mf%u", LMul); + break; + } + } + + if (isTailAgnostic(VType)) + SStream_concat0(O, ",ta"); + else + SStream_concat0(O, ",tu"); + + if (isMaskAgnostic(VType)) + SStream_concat0(O, ",ma"); + else + SStream_concat0(O, ",mu"); +} + +void printVTypeI(MCInst *MI, unsigned OpNo, SStream *O) { + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + printVType(Imm, O); +} + +#endif // CAPSTONE_HAS_RISCV diff --git a/arch/RISCV/RISCVInstPrinter.h b/arch/RISCV/RISCVInstPrinter.h index 466c3f86db..ef4afd9a43 100644 --- a/arch/RISCV/RISCVInstPrinter.h +++ b/arch/RISCV/RISCVInstPrinter.h @@ -17,8 +17,8 @@ #include "../../MCInst.h" #include "../../SStream.h" -void RISCV_printInst(MCInst * MI, SStream * O, void *info); +void RISCV_printInst(MCInst *MI, SStream *O, void *info); -void RISCV_post_printer(csh ud, cs_insn * insn, char *insn_asm, MCInst * mci); +void RISCV_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); #endif diff --git a/arch/RISCV/RISCVMapping.c b/arch/RISCV/RISCVMapping.c index 8ef9771836..ca09843a39 100644 --- a/arch/RISCV/RISCVMapping.c +++ b/arch/RISCV/RISCVMapping.c @@ -1,359 +1,301 @@ #ifdef CAPSTONE_HAS_RISCV -#include // debug +#include // debug #include #include "../../utils.h" -#include "RISCVMapping.h" #include "RISCVInstPrinter.h" +#include "RISCVMapping.h" #define GET_INSTRINFO_ENUM -#include "RISCVGenInstrInfo.inc" +#define GET_REGINFO_ENUM +#include "RISCVGenDisassemblerTables.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { - { RISCV_REG_INVALID, NULL }, - - { RISCV_REG_X0, "zero" }, - { RISCV_REG_X1, "ra" }, - { RISCV_REG_X2, "sp" }, - { RISCV_REG_X3, "gp" }, - { RISCV_REG_X4, "tp" }, - { RISCV_REG_X5, "t0" }, - { RISCV_REG_X6, "t1" }, - { RISCV_REG_X7, "t2" }, - { RISCV_REG_X8, "s0" }, - { RISCV_REG_X9, "s1" }, - { RISCV_REG_X10, "a0" }, - { RISCV_REG_X11, "a1" }, - { RISCV_REG_X12, "a2" }, - { RISCV_REG_X13, "a3" }, - { RISCV_REG_X14, "a4" }, - { RISCV_REG_X15, "a5" }, - { RISCV_REG_X16, "a6" }, - { RISCV_REG_X17, "a7" }, - { RISCV_REG_X18, "s2" }, - { RISCV_REG_X19, "s3" }, - { RISCV_REG_X20, "s4" }, - { RISCV_REG_X21, "s5" }, - { RISCV_REG_X22, "s6" }, - { RISCV_REG_X23, "s7" }, - { RISCV_REG_X24, "s8" }, - { RISCV_REG_X25, "s9" }, - { RISCV_REG_X26, "s10" }, - { RISCV_REG_X27, "s11" }, - { RISCV_REG_X28, "t3" }, - { RISCV_REG_X29, "t4" }, - { RISCV_REG_X30, "t5" }, - { RISCV_REG_X31, "t6" }, - - { RISCV_REG_F0_32, "ft0" }, - { RISCV_REG_F0_64, "ft0" }, - { RISCV_REG_F1_32, "ft1" }, - { RISCV_REG_F1_64, "ft1" }, - { RISCV_REG_F2_32, "ft2" }, - { RISCV_REG_F2_64, "ft2" }, - { RISCV_REG_F3_32, "ft3" }, - { RISCV_REG_F3_64, "ft3" }, - { RISCV_REG_F4_32, "ft4" }, - { RISCV_REG_F4_64, "ft4" }, - { RISCV_REG_F5_32, "ft5" }, - { RISCV_REG_F5_64, "ft5" }, - { RISCV_REG_F6_32, "ft6" }, - { RISCV_REG_F6_64, "ft6" }, - { RISCV_REG_F7_32, "ft7" }, - { RISCV_REG_F7_64, "ft7" }, - { RISCV_REG_F8_32, "fs0" }, - { RISCV_REG_F8_64, "fs0" }, - { RISCV_REG_F9_32, "fs1" }, - { RISCV_REG_F9_64, "fs1" }, - { RISCV_REG_F10_32, "fa0" }, - { RISCV_REG_F10_64, "fa0" }, - { RISCV_REG_F11_32, "fa1" }, - { RISCV_REG_F11_64, "fa1" }, - { RISCV_REG_F12_32, "fa2" }, - { RISCV_REG_F12_64, "fa2" }, - { RISCV_REG_F13_32, "fa3" }, - { RISCV_REG_F13_64, "fa3" }, - { RISCV_REG_F14_32, "fa4" }, - { RISCV_REG_F14_64, "fa4" }, - { RISCV_REG_F15_32, "fa5" }, - { RISCV_REG_F15_64, "fa5" }, - { RISCV_REG_F16_32, "fa6" }, - { RISCV_REG_F16_64, "fa6" }, - { RISCV_REG_F17_32, "fa7" }, - { RISCV_REG_F17_64, "fa7" }, - { RISCV_REG_F18_32, "fs2" }, - { RISCV_REG_F18_64, "fs2" }, - { RISCV_REG_F19_32, "fs3" }, - { RISCV_REG_F19_64, "fs3" }, - { RISCV_REG_F20_32, "fs4" }, - { RISCV_REG_F20_64, "fs4" }, - { RISCV_REG_F21_32, "fs5" }, - { RISCV_REG_F21_64, "fs5" }, - { RISCV_REG_F22_32, "fs6" }, - { RISCV_REG_F22_64, "fs6" }, - { RISCV_REG_F23_32, "fs7" }, - { RISCV_REG_F23_64, "fs7" }, - { RISCV_REG_F24_32, "fs8" }, - { RISCV_REG_F24_64, "fs8" }, - { RISCV_REG_F25_32, "fs9" }, - { RISCV_REG_F25_64, "fs9" }, - { RISCV_REG_F26_32, "fs10" }, - { RISCV_REG_F26_64, "fs10" }, - { RISCV_REG_F27_32, "fs11" }, - { RISCV_REG_F27_64, "fs11" }, - { RISCV_REG_F28_32, "ft8" }, - { RISCV_REG_F28_64, "ft8" }, - { RISCV_REG_F29_32, "ft9" }, - { RISCV_REG_F29_64, "ft9" }, - { RISCV_REG_F30_32, "ft10" }, - { RISCV_REG_F30_64, "ft10" }, - { RISCV_REG_F31_32, "ft11" }, - { RISCV_REG_F31_64, "ft11" }, + {RISCV_REG_INVALID, NULL}, + + {RISCV_X0, "zero"}, {RISCV_X1, "ra"}, {RISCV_X2, "sp"}, + {RISCV_X3, "gp"}, {RISCV_X4, "tp"}, {RISCV_X5, "t0"}, + {RISCV_X6, "t1"}, {RISCV_X7, "t2"}, {RISCV_X8, "s0"}, + {RISCV_X9, "s1"}, {RISCV_X10, "a0"}, {RISCV_X11, "a1"}, + {RISCV_X12, "a2"}, {RISCV_X13, "a3"}, {RISCV_X14, "a4"}, + {RISCV_X15, "a5"}, {RISCV_X16, "a6"}, {RISCV_X17, "a7"}, + {RISCV_X18, "s2"}, {RISCV_X19, "s3"}, {RISCV_X20, "s4"}, + {RISCV_X21, "s5"}, {RISCV_X22, "s6"}, {RISCV_X23, "s7"}, + {RISCV_X24, "s8"}, {RISCV_X25, "s9"}, {RISCV_X26, "s10"}, + {RISCV_X27, "s11"}, {RISCV_X28, "t3"}, {RISCV_X29, "t4"}, + {RISCV_X30, "t5"}, {RISCV_X31, "t6"}, + + {RISCV_F0_F, "ft0"}, {RISCV_F0_D, "ft0"}, {RISCV_F1_F, "ft1"}, + {RISCV_F1_D, "ft1"}, {RISCV_F2_F, "ft2"}, {RISCV_F2_D, "ft2"}, + {RISCV_F3_F, "ft3"}, {RISCV_F3_D, "ft3"}, {RISCV_F4_F, "ft4"}, + {RISCV_F4_D, "ft4"}, {RISCV_F5_F, "ft5"}, {RISCV_F5_D, "ft5"}, + {RISCV_F6_F, "ft6"}, {RISCV_F6_D, "ft6"}, {RISCV_F7_F, "ft7"}, + {RISCV_F7_D, "ft7"}, {RISCV_F8_F, "fs0"}, {RISCV_F8_D, "fs0"}, + {RISCV_F9_F, "fs1"}, {RISCV_F9_D, "fs1"}, {RISCV_F10_F, "fa0"}, + {RISCV_F10_D, "fa0"}, {RISCV_F11_F, "fa1"}, {RISCV_F11_D, "fa1"}, + {RISCV_F12_F, "fa2"}, {RISCV_F12_D, "fa2"}, {RISCV_F13_F, "fa3"}, + {RISCV_F13_D, "fa3"}, {RISCV_F14_F, "fa4"}, {RISCV_F14_D, "fa4"}, + {RISCV_F15_F, "fa5"}, {RISCV_F15_D, "fa5"}, {RISCV_F16_F, "fa6"}, + {RISCV_F16_D, "fa6"}, {RISCV_F17_F, "fa7"}, {RISCV_F17_D, "fa7"}, + {RISCV_F18_F, "fs2"}, {RISCV_F18_D, "fs2"}, {RISCV_F19_F, "fs3"}, + {RISCV_F19_D, "fs3"}, {RISCV_F20_F, "fs4"}, {RISCV_F20_D, "fs4"}, + {RISCV_F21_F, "fs5"}, {RISCV_F21_D, "fs5"}, {RISCV_F22_F, "fs6"}, + {RISCV_F22_D, "fs6"}, {RISCV_F23_F, "fs7"}, {RISCV_F23_D, "fs7"}, + {RISCV_F24_F, "fs8"}, {RISCV_F24_D, "fs8"}, {RISCV_F25_F, "fs9"}, + {RISCV_F25_D, "fs9"}, {RISCV_F26_F, "fs10"}, {RISCV_F26_D, "fs10"}, + {RISCV_F27_F, "fs11"}, {RISCV_F27_D, "fs11"}, {RISCV_F28_F, "ft8"}, + {RISCV_F28_D, "ft8"}, {RISCV_F29_F, "ft9"}, {RISCV_F29_D, "ft9"}, + {RISCV_F30_F, "ft10"}, {RISCV_F30_D, "ft10"}, {RISCV_F31_F, "ft11"}, + {RISCV_F31_D, "ft11"}, }; #endif -const char *RISCV_reg_name(csh handle, unsigned int reg) -{ +const char *RISCV_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET - if (reg >= RISCV_REG_ENDING) - return NULL; - return reg_name_maps[reg].name; + for (int i = 0; i < ARR_SIZE(reg_name_maps); i++) { + if (reg_name_maps[i].id == reg) { + return reg_name_maps[i].name; + } + } + + // invalid + return "invalid"; #else - return NULL; + return NULL; #endif } static const insn_map insns[] = { - // dummy item - { - 0, 0, + // dummy item + {0, + 0, #ifndef CAPSTONE_DIET - {0}, {0}, {0}, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif - }, + }, #include "RISCVMappingInsn.inc" }; // given internal insn id, return public instruction info -void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id) -{ - unsigned int i; +void RISCV_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { + unsigned int i; - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; - if (h->detail) { + if (h->detail) { #ifndef CAPSTONE_DIET - memcpy(insn->detail->regs_read, - insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + memcpy(insn->detail->regs_read, insns[i].regs_use, + sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = + (uint8_t)count_positive(insns[i].regs_use); - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + memcpy(insn->detail->regs_write, insns[i].regs_mod, + sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = + (uint8_t)count_positive(insns[i].regs_mod); - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = RISCV_GRP_JUMP; - insn->detail->groups_count++; - } + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = RISCV_GRP_JUMP; + insn->detail->groups_count++; + } #endif - } - } + } + } } static const name_map insn_name_maps[] = { - {RISCV_INS_INVALID, NULL}, + {RISCV_INS_INVALID, NULL}, #include "RISCVGenInsnNameMaps.inc" }; -const char *RISCV_insn_name(csh handle, unsigned int id) -{ +const char *RISCV_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - if (id >= RISCV_INS_ENDING) - return NULL; + if (id >= RISCV_INS_ENDING) + return NULL; - return insn_name_maps[id].name; + return insn_name_maps[id].name; #else - return NULL; + return NULL; #endif } #ifndef CAPSTONE_DIET -static const name_map group_name_maps[] = { - { RISCV_GRP_INVALID, NULL }, - { RISCV_GRP_JUMP, "jump" }, - - // architecture specific - { RISCV_GRP_ISRV32, "isrv32" }, - { RISCV_GRP_ISRV64, "isrv64" }, - { RISCV_GRP_HASSTDEXTA, "hasStdExtA" }, - { RISCV_GRP_HASSTDEXTC, "hasStdExtC" }, - { RISCV_GRP_HASSTDEXTD, "hasStdExtD" }, - { RISCV_GRP_HASSTDEXTF, "hasStdExtF" }, - { RISCV_GRP_HASSTDEXTM, "hasStdExtM" }, - - /* - { RISCV_GRP_ISRVA, "isrva" }, - { RISCV_GRP_ISRVC, "isrvc" }, - { RISCV_GRP_ISRVD, "isrvd" }, - { RISCV_GRP_ISRVCD, "isrvcd" }, - { RISCV_GRP_ISRVF, "isrvf" }, - { RISCV_GRP_ISRV32C, "isrv32c" }, - { RISCV_GRP_ISRV32CF, "isrv32cf" }, - { RISCV_GRP_ISRVM, "isrvm" }, - { RISCV_GRP_ISRV64A, "isrv64a" }, - { RISCV_GRP_ISRV64C, "isrv64c" }, - { RISCV_GRP_ISRV64D, "isrv64d" }, - { RISCV_GRP_ISRV64F, "isrv64f" }, - { RISCV_GRP_ISRV64M, "isrv64m" } - */ - { RISCV_GRP_ENDING, NULL } -}; +static const name_map group_name_maps[] = {{RISCV_GRP_INVALID, NULL}, + {RISCV_GRP_JUMP, "jump"}, + + // architecture specific + {RISCV_GRP_ISRV32, "isrv32"}, + {RISCV_GRP_ISRV64, "isrv64"}, + {RISCV_GRP_HASSTDEXTA, "hasStdExtA"}, + {RISCV_GRP_HASSTDEXTC, "hasStdExtC"}, + {RISCV_GRP_HASSTDEXTD, "hasStdExtD"}, + {RISCV_GRP_HASSTDEXTF, "hasStdExtF"}, + {RISCV_GRP_HASSTDEXTM, "hasStdExtM"}, + + /* + { RISCV_GRP_ISRVA, "isrva" }, + { RISCV_GRP_ISRVC, "isrvc" }, + { RISCV_GRP_ISRVD, "isrvd" }, + { RISCV_GRP_ISRVCD, "isrvcd" }, + { RISCV_GRP_ISRVF, "isrvf" }, + { RISCV_GRP_ISRV32C, "isrv32c" }, + { RISCV_GRP_ISRV32CF, "isrv32cf" }, + { RISCV_GRP_ISRVM, "isrvm" }, + { RISCV_GRP_ISRV64A, "isrv64a" }, + { RISCV_GRP_ISRV64C, "isrv64c" }, + { RISCV_GRP_ISRV64D, "isrv64d" }, + { RISCV_GRP_ISRV64F, "isrv64f" }, + { RISCV_GRP_ISRV64M, "isrv64m" } + */ + {RISCV_GRP_ENDING, NULL}}; #endif -const char *RISCV_group_name(csh handle, unsigned int id) -{ +const char *RISCV_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - // verify group id - if (id >= RISCV_GRP_ENDING || - (id > RISCV_GRP_JUMP && id < RISCV_GRP_ISRV32)) - return NULL; - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); + // verify group id + if (id >= RISCV_GRP_ENDING || (id > RISCV_GRP_JUMP && id < RISCV_GRP_ISRV32)) + return NULL; + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else - return NULL; + return NULL; #endif } // map instruction name to public instruction ID -riscv_reg RISCV_map_insn(const char *name) -{ - // handle special alias first - unsigned int i; +riscv_reg RISCV_map_insn(const char *name) { + // handle special alias first + unsigned int i; - // NOTE: skip first NULL name in insn_name_maps - i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + // NOTE: skip first NULL name in insn_name_maps + i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); - return (i != -1) ? i : RISCV_REG_INVALID; + return (i != -1) ? i : RISCV_REG_INVALID; } // map internal raw register to 'public' register -riscv_reg RISCV_map_register(unsigned int r) -{ - static const unsigned int map[] = { 0, - RISCV_REG_X0, - RISCV_REG_X1, - RISCV_REG_X2, - RISCV_REG_X3, - RISCV_REG_X4, - RISCV_REG_X5, - RISCV_REG_X6, - RISCV_REG_X7, - RISCV_REG_X8, - RISCV_REG_X9, - RISCV_REG_X10, - RISCV_REG_X11, - RISCV_REG_X12, - RISCV_REG_X13, - RISCV_REG_X14, - RISCV_REG_X15, - RISCV_REG_X16, - RISCV_REG_X17, - RISCV_REG_X18, - RISCV_REG_X19, - RISCV_REG_X20, - RISCV_REG_X21, - RISCV_REG_X22, - RISCV_REG_X23, - RISCV_REG_X24, - RISCV_REG_X25, - RISCV_REG_X26, - RISCV_REG_X27, - RISCV_REG_X28, - RISCV_REG_X29, - RISCV_REG_X30, - RISCV_REG_X31, - - RISCV_REG_F0_32, - RISCV_REG_F0_64, - RISCV_REG_F1_32, - RISCV_REG_F1_64, - RISCV_REG_F2_32, - RISCV_REG_F2_64, - RISCV_REG_F3_32, - RISCV_REG_F3_64, - RISCV_REG_F4_32, - RISCV_REG_F4_64, - RISCV_REG_F5_32, - RISCV_REG_F5_64, - RISCV_REG_F6_32, - RISCV_REG_F6_64, - RISCV_REG_F7_32, - RISCV_REG_F7_64, - RISCV_REG_F8_32, - RISCV_REG_F8_64, - RISCV_REG_F9_32, - RISCV_REG_F9_64, - RISCV_REG_F10_32, - RISCV_REG_F10_64, - RISCV_REG_F11_32, - RISCV_REG_F11_64, - RISCV_REG_F12_32, - RISCV_REG_F12_64, - RISCV_REG_F13_32, - RISCV_REG_F13_64, - RISCV_REG_F14_32, - RISCV_REG_F14_64, - RISCV_REG_F15_32, - RISCV_REG_F15_64, - RISCV_REG_F16_32, - RISCV_REG_F16_64, - RISCV_REG_F17_32, - RISCV_REG_F17_64, - RISCV_REG_F18_32, - RISCV_REG_F18_64, - RISCV_REG_F19_32, - RISCV_REG_F19_64, - RISCV_REG_F20_32, - RISCV_REG_F20_64, - RISCV_REG_F21_32, - RISCV_REG_F21_64, - RISCV_REG_F22_32, - RISCV_REG_F22_64, - RISCV_REG_F23_32, - RISCV_REG_F23_64, - RISCV_REG_F24_32, - RISCV_REG_F24_64, - RISCV_REG_F25_32, - RISCV_REG_F25_64, - RISCV_REG_F26_32, - RISCV_REG_F26_64, - RISCV_REG_F27_32, - RISCV_REG_F27_64, - RISCV_REG_F28_32, - RISCV_REG_F28_64, - RISCV_REG_F29_32, - RISCV_REG_F29_64, - RISCV_REG_F30_32, - RISCV_REG_F30_64, - RISCV_REG_F31_32, - RISCV_REG_F31_64, - }; - - if (r < ARR_SIZE(map)) - return map[r]; - - // cannot find this register - return 0; +riscv_reg RISCV_map_register(unsigned int r) { + static const unsigned int map[] = { + 0, + RISCV_REG_X0, + RISCV_REG_X1, + RISCV_REG_X2, + RISCV_REG_X3, + RISCV_REG_X4, + RISCV_REG_X5, + RISCV_REG_X6, + RISCV_REG_X7, + RISCV_REG_X8, + RISCV_REG_X9, + RISCV_REG_X10, + RISCV_REG_X11, + RISCV_REG_X12, + RISCV_REG_X13, + RISCV_REG_X14, + RISCV_REG_X15, + RISCV_REG_X16, + RISCV_REG_X17, + RISCV_REG_X18, + RISCV_REG_X19, + RISCV_REG_X20, + RISCV_REG_X21, + RISCV_REG_X22, + RISCV_REG_X23, + RISCV_REG_X24, + RISCV_REG_X25, + RISCV_REG_X26, + RISCV_REG_X27, + RISCV_REG_X28, + RISCV_REG_X29, + RISCV_REG_X30, + RISCV_REG_X31, + + RISCV_REG_F0_32, + RISCV_REG_F0_64, + RISCV_REG_F1_32, + RISCV_REG_F1_64, + RISCV_REG_F2_32, + RISCV_REG_F2_64, + RISCV_REG_F3_32, + RISCV_REG_F3_64, + RISCV_REG_F4_32, + RISCV_REG_F4_64, + RISCV_REG_F5_32, + RISCV_REG_F5_64, + RISCV_REG_F6_32, + RISCV_REG_F6_64, + RISCV_REG_F7_32, + RISCV_REG_F7_64, + RISCV_REG_F8_32, + RISCV_REG_F8_64, + RISCV_REG_F9_32, + RISCV_REG_F9_64, + RISCV_REG_F10_32, + RISCV_REG_F10_64, + RISCV_REG_F11_32, + RISCV_REG_F11_64, + RISCV_REG_F12_32, + RISCV_REG_F12_64, + RISCV_REG_F13_32, + RISCV_REG_F13_64, + RISCV_REG_F14_32, + RISCV_REG_F14_64, + RISCV_REG_F15_32, + RISCV_REG_F15_64, + RISCV_REG_F16_32, + RISCV_REG_F16_64, + RISCV_REG_F17_32, + RISCV_REG_F17_64, + RISCV_REG_F18_32, + RISCV_REG_F18_64, + RISCV_REG_F19_32, + RISCV_REG_F19_64, + RISCV_REG_F20_32, + RISCV_REG_F20_64, + RISCV_REG_F21_32, + RISCV_REG_F21_64, + RISCV_REG_F22_32, + RISCV_REG_F22_64, + RISCV_REG_F23_32, + RISCV_REG_F23_64, + RISCV_REG_F24_32, + RISCV_REG_F24_64, + RISCV_REG_F25_32, + RISCV_REG_F25_64, + RISCV_REG_F26_32, + RISCV_REG_F26_64, + RISCV_REG_F27_32, + RISCV_REG_F27_64, + RISCV_REG_F28_32, + RISCV_REG_F28_64, + RISCV_REG_F29_32, + RISCV_REG_F29_64, + RISCV_REG_F30_32, + RISCV_REG_F30_64, + RISCV_REG_F31_32, + RISCV_REG_F31_64, + }; + + if (r < ARR_SIZE(map)) + return map[r]; + + // cannot find this register + return 0; } #endif diff --git a/arch/RISCV/RISCVMapping.h b/arch/RISCV/RISCVMapping.h index c592e7fb53..2716d81c37 100644 --- a/arch/RISCV/RISCVMapping.h +++ b/arch/RISCV/RISCVMapping.h @@ -5,7 +5,7 @@ #include "../../include/capstone/capstone.h" // given internal insn id, return public instruction info -void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id); +void RISCV_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *RISCV_insn_name(csh handle, unsigned int id); diff --git a/arch/RISCV/RISCVMappingInsn.inc b/arch/RISCV/RISCVMappingInsn.inc index 6789c0b793..d0bcf0abbe 100644 --- a/arch/RISCV/RISCVMappingInsn.inc +++ b/arch/RISCV/RISCVMappingInsn.inc @@ -1,1635 +1,2544 @@ // This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh -{ - RISCV_ADD, RISCV_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ADDI, RISCV_INS_ADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ADDIW, RISCV_INS_ADDIW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_ADDW, RISCV_INS_ADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_D, RISCV_INS_AMOADD_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_D_AQ, RISCV_INS_AMOADD_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_D_AQ_RL, RISCV_INS_AMOADD_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_D_RL, RISCV_INS_AMOADD_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_W, RISCV_INS_AMOADD_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_W_AQ, RISCV_INS_AMOADD_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_W_AQ_RL, RISCV_INS_AMOADD_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_W_RL, RISCV_INS_AMOADD_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_D, RISCV_INS_AMOAND_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_D_AQ, RISCV_INS_AMOAND_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_D_AQ_RL, RISCV_INS_AMOAND_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_D_RL, RISCV_INS_AMOAND_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_W, RISCV_INS_AMOAND_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_W_AQ, RISCV_INS_AMOAND_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_W_AQ_RL, RISCV_INS_AMOAND_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_W_RL, RISCV_INS_AMOAND_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_D, RISCV_INS_AMOMAXU_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_D_AQ, RISCV_INS_AMOMAXU_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_D_AQ_RL, RISCV_INS_AMOMAXU_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_D_RL, RISCV_INS_AMOMAXU_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_W, RISCV_INS_AMOMAXU_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_W_AQ, RISCV_INS_AMOMAXU_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_W_AQ_RL, RISCV_INS_AMOMAXU_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_W_RL, RISCV_INS_AMOMAXU_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_D, RISCV_INS_AMOMAX_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_D_AQ, RISCV_INS_AMOMAX_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_D_AQ_RL, RISCV_INS_AMOMAX_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_D_RL, RISCV_INS_AMOMAX_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_W, RISCV_INS_AMOMAX_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_W_AQ, RISCV_INS_AMOMAX_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_W_AQ_RL, RISCV_INS_AMOMAX_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_W_RL, RISCV_INS_AMOMAX_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_D, RISCV_INS_AMOMINU_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_D_AQ, RISCV_INS_AMOMINU_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_D_AQ_RL, RISCV_INS_AMOMINU_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_D_RL, RISCV_INS_AMOMINU_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_W, RISCV_INS_AMOMINU_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_W_AQ, RISCV_INS_AMOMINU_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_W_AQ_RL, RISCV_INS_AMOMINU_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_W_RL, RISCV_INS_AMOMINU_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_D, RISCV_INS_AMOMIN_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_D_AQ, RISCV_INS_AMOMIN_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_D_AQ_RL, RISCV_INS_AMOMIN_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_D_RL, RISCV_INS_AMOMIN_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_W, RISCV_INS_AMOMIN_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_W_AQ, RISCV_INS_AMOMIN_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_W_AQ_RL, RISCV_INS_AMOMIN_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_W_RL, RISCV_INS_AMOMIN_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_D, RISCV_INS_AMOOR_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_D_AQ, RISCV_INS_AMOOR_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_D_AQ_RL, RISCV_INS_AMOOR_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_D_RL, RISCV_INS_AMOOR_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_W, RISCV_INS_AMOOR_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_W_AQ, RISCV_INS_AMOOR_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_W_AQ_RL, RISCV_INS_AMOOR_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_W_RL, RISCV_INS_AMOOR_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_D, RISCV_INS_AMOSWAP_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_D_AQ, RISCV_INS_AMOSWAP_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_D_AQ_RL, RISCV_INS_AMOSWAP_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_D_RL, RISCV_INS_AMOSWAP_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_W, RISCV_INS_AMOSWAP_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_W_AQ, RISCV_INS_AMOSWAP_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_W_AQ_RL, RISCV_INS_AMOSWAP_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_W_RL, RISCV_INS_AMOSWAP_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_D, RISCV_INS_AMOXOR_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_D_AQ, RISCV_INS_AMOXOR_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_D_AQ_RL, RISCV_INS_AMOXOR_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_D_RL, RISCV_INS_AMOXOR_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_W, RISCV_INS_AMOXOR_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_W_AQ, RISCV_INS_AMOXOR_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_W_AQ_RL, RISCV_INS_AMOXOR_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_W_RL, RISCV_INS_AMOXOR_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AND, RISCV_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ANDI, RISCV_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_AUIPC, RISCV_INS_AUIPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_BEQ, RISCV_INS_BEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - RISCV_BGE, RISCV_INS_BGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - RISCV_BGEU, RISCV_INS_BGEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - RISCV_BLT, RISCV_INS_BLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - RISCV_BLTU, RISCV_INS_BLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - RISCV_BNE, RISCV_INS_BNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - RISCV_CSRRC, RISCV_INS_CSRRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRCI, RISCV_INS_CSRRCI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRS, RISCV_INS_CSRRS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRSI, RISCV_INS_CSRRSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRW, RISCV_INS_CSRRW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRWI, RISCV_INS_CSRRWI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADD, RISCV_INS_C_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDI, RISCV_INS_C_ADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDI16SP, RISCV_INS_C_ADDI16SP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDI4SPN, RISCV_INS_C_ADDI4SPN, -#ifndef CAPSTONE_DIET - { RISCV_REG_X2, 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDIW, RISCV_INS_C_ADDIW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDW, RISCV_INS_C_ADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_AND, RISCV_INS_C_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ANDI, RISCV_INS_C_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_BEQZ, RISCV_INS_C_BEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 0 -#endif -}, -{ - RISCV_C_BNEZ, RISCV_INS_C_BNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 0 -#endif -}, -{ - RISCV_C_EBREAK, RISCV_INS_C_EBREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FLD, RISCV_INS_C_FLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FLDSP, RISCV_INS_C_FLDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FLW, RISCV_INS_C_FLW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FLWSP, RISCV_INS_C_FLWSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FSD, RISCV_INS_C_FSD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FSDSP, RISCV_INS_C_FSDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FSW, RISCV_INS_C_FSW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FSWSP, RISCV_INS_C_FSWSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_J, RISCV_INS_C_J, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 0 -#endif -}, -{ - RISCV_C_JAL, RISCV_INS_C_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV32, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_JALR, RISCV_INS_C_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_JR, RISCV_INS_C_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 1 -#endif -}, -{ - RISCV_C_LD, RISCV_INS_C_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LDSP, RISCV_INS_C_LDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LI, RISCV_INS_C_LI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LUI, RISCV_INS_C_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LW, RISCV_INS_C_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LWSP, RISCV_INS_C_LWSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_MV, RISCV_INS_C_MV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_NOP, RISCV_INS_C_NOP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_OR, RISCV_INS_C_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SD, RISCV_INS_C_SD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SDSP, RISCV_INS_C_SDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SLLI, RISCV_INS_C_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SRAI, RISCV_INS_C_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SRLI, RISCV_INS_C_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SUB, RISCV_INS_C_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SUBW, RISCV_INS_C_SUBW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SW, RISCV_INS_C_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SWSP, RISCV_INS_C_SWSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_UNIMP, RISCV_INS_C_UNIMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_XOR, RISCV_INS_C_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_DIV, RISCV_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_DIVU, RISCV_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_DIVUW, RISCV_INS_DIVUW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_DIVW, RISCV_INS_DIVW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_EBREAK, RISCV_INS_EBREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ECALL, RISCV_INS_ECALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_FADD_D, RISCV_INS_FADD_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FADD_S, RISCV_INS_FADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCLASS_D, RISCV_INS_FCLASS_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCLASS_S, RISCV_INS_FCLASS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_L, RISCV_INS_FCVT_D_L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_LU, RISCV_INS_FCVT_D_LU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_S, RISCV_INS_FCVT_D_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_W, RISCV_INS_FCVT_D_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_WU, RISCV_INS_FCVT_D_WU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_LU_D, RISCV_INS_FCVT_LU_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_LU_S, RISCV_INS_FCVT_LU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_L_D, RISCV_INS_FCVT_L_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_L_S, RISCV_INS_FCVT_L_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_D, RISCV_INS_FCVT_S_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_L, RISCV_INS_FCVT_S_L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_LU, RISCV_INS_FCVT_S_LU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_W, RISCV_INS_FCVT_S_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_WU, RISCV_INS_FCVT_S_WU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_WU_D, RISCV_INS_FCVT_WU_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_WU_S, RISCV_INS_FCVT_WU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_W_D, RISCV_INS_FCVT_W_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_W_S, RISCV_INS_FCVT_W_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FDIV_D, RISCV_INS_FDIV_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FDIV_S, RISCV_INS_FDIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FENCE, RISCV_INS_FENCE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_FENCE_I, RISCV_INS_FENCE_I, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_FENCE_TSO, RISCV_INS_FENCE_TSO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_FEQ_D, RISCV_INS_FEQ_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FEQ_S, RISCV_INS_FEQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLD, RISCV_INS_FLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLE_D, RISCV_INS_FLE_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLE_S, RISCV_INS_FLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLT_D, RISCV_INS_FLT_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLT_S, RISCV_INS_FLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLW, RISCV_INS_FLW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMADD_D, RISCV_INS_FMADD_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMADD_S, RISCV_INS_FMADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMAX_D, RISCV_INS_FMAX_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMAX_S, RISCV_INS_FMAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMIN_D, RISCV_INS_FMIN_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMIN_S, RISCV_INS_FMIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMSUB_D, RISCV_INS_FMSUB_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMSUB_S, RISCV_INS_FMSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMUL_D, RISCV_INS_FMUL_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMUL_S, RISCV_INS_FMUL_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMV_D_X, RISCV_INS_FMV_D_X, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMV_W_X, RISCV_INS_FMV_W_X, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMV_X_D, RISCV_INS_FMV_X_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMV_X_W, RISCV_INS_FMV_X_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FNMADD_D, RISCV_INS_FNMADD_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FNMADD_S, RISCV_INS_FNMADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FNMSUB_D, RISCV_INS_FNMSUB_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FNMSUB_S, RISCV_INS_FNMSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSD, RISCV_INS_FSD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJN_D, RISCV_INS_FSGNJN_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJN_S, RISCV_INS_FSGNJN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJX_D, RISCV_INS_FSGNJX_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJX_S, RISCV_INS_FSGNJX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJ_D, RISCV_INS_FSGNJ_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJ_S, RISCV_INS_FSGNJ_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSQRT_D, RISCV_INS_FSQRT_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSQRT_S, RISCV_INS_FSQRT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSUB_D, RISCV_INS_FSUB_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSUB_S, RISCV_INS_FSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSW, RISCV_INS_FSW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_JAL, RISCV_INS_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_JALR, RISCV_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LB, RISCV_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LBU, RISCV_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LD, RISCV_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_LH, RISCV_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LHU, RISCV_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_D, RISCV_INS_LR_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_D_AQ, RISCV_INS_LR_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 +{RISCV_ADD, RISCV_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif +}, + {RISCV_ADDI, RISCV_INS_ADDI, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {RISCV_ADDIW, + RISCV_INS_ADDIW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_ADDW, + RISCV_INS_ADDW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOADD_D, + RISCV_INS_AMOADD_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOADD_D_AQ, + RISCV_INS_AMOADD_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOADD_D_AQ_RL, + RISCV_INS_AMOADD_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOADD_D_RL, + RISCV_INS_AMOADD_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOADD_W, + RISCV_INS_AMOADD_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOADD_W_AQ, + RISCV_INS_AMOADD_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOADD_W_AQ_RL, + RISCV_INS_AMOADD_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOADD_W_RL, + RISCV_INS_AMOADD_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOAND_D, + RISCV_INS_AMOAND_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOAND_D_AQ, + RISCV_INS_AMOAND_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOAND_D_AQ_RL, + RISCV_INS_AMOAND_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOAND_D_RL, + RISCV_INS_AMOAND_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOAND_W, + RISCV_INS_AMOAND_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOAND_W_AQ, + RISCV_INS_AMOAND_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOAND_W_AQ_RL, + RISCV_INS_AMOAND_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOAND_W_RL, + RISCV_INS_AMOAND_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAXU_D, + RISCV_INS_AMOMAXU_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAXU_D_AQ, + RISCV_INS_AMOMAXU_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAXU_D_AQ_RL, + RISCV_INS_AMOMAXU_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAXU_D_RL, + RISCV_INS_AMOMAXU_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAXU_W, + RISCV_INS_AMOMAXU_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAXU_W_AQ, + RISCV_INS_AMOMAXU_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAXU_W_AQ_RL, + RISCV_INS_AMOMAXU_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAXU_W_RL, + RISCV_INS_AMOMAXU_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAX_D, + RISCV_INS_AMOMAX_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAX_D_AQ, + RISCV_INS_AMOMAX_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAX_D_AQ_RL, + RISCV_INS_AMOMAX_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAX_D_RL, + RISCV_INS_AMOMAX_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAX_W, + RISCV_INS_AMOMAX_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAX_W_AQ, + RISCV_INS_AMOMAX_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAX_W_AQ_RL, + RISCV_INS_AMOMAX_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMAX_W_RL, + RISCV_INS_AMOMAX_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMINU_D, + RISCV_INS_AMOMINU_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMINU_D_AQ, + RISCV_INS_AMOMINU_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMINU_D_AQ_RL, + RISCV_INS_AMOMINU_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMINU_D_RL, + RISCV_INS_AMOMINU_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMINU_W, + RISCV_INS_AMOMINU_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMINU_W_AQ, + RISCV_INS_AMOMINU_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMINU_W_AQ_RL, + RISCV_INS_AMOMINU_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMINU_W_RL, + RISCV_INS_AMOMINU_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMIN_D, + RISCV_INS_AMOMIN_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMIN_D_AQ, + RISCV_INS_AMOMIN_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMIN_D_AQ_RL, + RISCV_INS_AMOMIN_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMIN_D_RL, + RISCV_INS_AMOMIN_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMIN_W, + RISCV_INS_AMOMIN_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMIN_W_AQ, + RISCV_INS_AMOMIN_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMIN_W_AQ_RL, + RISCV_INS_AMOMIN_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOMIN_W_RL, + RISCV_INS_AMOMIN_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOOR_D, + RISCV_INS_AMOOR_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOOR_D_AQ, + RISCV_INS_AMOOR_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOOR_D_AQ_RL, + RISCV_INS_AMOOR_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOOR_D_RL, + RISCV_INS_AMOOR_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOOR_W, + RISCV_INS_AMOOR_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOOR_W_AQ, + RISCV_INS_AMOOR_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOOR_W_AQ_RL, + RISCV_INS_AMOOR_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOOR_W_RL, + RISCV_INS_AMOOR_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOSWAP_D, + RISCV_INS_AMOSWAP_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOSWAP_D_AQ, + RISCV_INS_AMOSWAP_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOSWAP_D_AQ_RL, + RISCV_INS_AMOSWAP_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOSWAP_D_RL, + RISCV_INS_AMOSWAP_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOSWAP_W, + RISCV_INS_AMOSWAP_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOSWAP_W_AQ, + RISCV_INS_AMOSWAP_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOSWAP_W_AQ_RL, + RISCV_INS_AMOSWAP_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOSWAP_W_RL, + RISCV_INS_AMOSWAP_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOXOR_D, + RISCV_INS_AMOXOR_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOXOR_D_AQ, + RISCV_INS_AMOXOR_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOXOR_D_AQ_RL, + RISCV_INS_AMOXOR_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOXOR_D_RL, + RISCV_INS_AMOXOR_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOXOR_W, + RISCV_INS_AMOXOR_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOXOR_W_AQ, + RISCV_INS_AMOXOR_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOXOR_W_AQ_RL, + RISCV_INS_AMOXOR_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AMOXOR_W_RL, + RISCV_INS_AMOXOR_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_AND, RISCV_INS_AND, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_ANDI, RISCV_INS_ANDI, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {RISCV_AUIPC, + RISCV_INS_AUIPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_BEQ, RISCV_INS_BEQ, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 1, + 0 +#endif + }, + {RISCV_BGE, RISCV_INS_BGE, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 1, + 0 +#endif + }, + {RISCV_BGEU, RISCV_INS_BGEU, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 1, + 0 +#endif + }, + {RISCV_BLT, RISCV_INS_BLT, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 1, + 0 +#endif + }, + {RISCV_BLTU, RISCV_INS_BLTU, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 1, + 0 +#endif + }, + {RISCV_BNE, RISCV_INS_BNE, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 1, + 0 +#endif + }, + {RISCV_CSRRC, + RISCV_INS_CSRRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_CSRRCI, + RISCV_INS_CSRRCI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_CSRRS, + RISCV_INS_CSRRS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_CSRRSI, + RISCV_INS_CSRRSI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_CSRRW, + RISCV_INS_CSRRW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_CSRRWI, + RISCV_INS_CSRRWI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_C_ADD, + RISCV_INS_C_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_ADDI, + RISCV_INS_C_ADDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_ADDI16SP, + RISCV_INS_C_ADDI16SP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_ADDI4SPN, + RISCV_INS_C_ADDI4SPN, +#ifndef CAPSTONE_DIET + {RISCV_REG_X2, 0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_ADDIW, + RISCV_INS_C_ADDIW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_C_ADDW, + RISCV_INS_C_ADDW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_C_AND, + RISCV_INS_C_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_ANDI, + RISCV_INS_C_ANDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_BEQZ, + RISCV_INS_C_BEQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 1, + 0 +#endif + }, + {RISCV_C_BNEZ, + RISCV_INS_C_BNEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 1, + 0 +#endif + }, + {RISCV_C_EBREAK, + RISCV_INS_C_EBREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_FLD, + RISCV_INS_C_FLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_C_FLDSP, + RISCV_INS_C_FLDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_C_FLW, + RISCV_INS_C_FLW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0}, + 0, + 0 +#endif + }, + {RISCV_C_FLWSP, + RISCV_INS_C_FLWSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0}, + 0, + 0 +#endif + }, + {RISCV_C_FSD, + RISCV_INS_C_FSD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_C_FSDSP, + RISCV_INS_C_FSDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_C_FSW, + RISCV_INS_C_FSW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0}, + 0, + 0 +#endif + }, + {RISCV_C_FSWSP, + RISCV_INS_C_FSWSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0}, + 0, + 0 +#endif + }, + {RISCV_C_J, RISCV_INS_C_J, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_HASSTDEXTC, 0}, 1, + 0 +#endif + }, + {RISCV_C_JAL, + RISCV_INS_C_JAL, +#ifndef CAPSTONE_DIET + {0}, + {RISCV_REG_X1, 0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV32, 0}, + 0, + 0 +#endif + }, + {RISCV_C_JALR, + RISCV_INS_C_JALR, +#ifndef CAPSTONE_DIET + {0}, + {RISCV_REG_X1, 0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_JR, + RISCV_INS_C_JR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 1, + 1 +#endif + }, + {RISCV_C_LD, + RISCV_INS_C_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_C_LDSP, + RISCV_INS_C_LDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_C_LI, + RISCV_INS_C_LI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_LUI, + RISCV_INS_C_LUI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_LW, + RISCV_INS_C_LW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_LWSP, + RISCV_INS_C_LWSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_MV, + RISCV_INS_C_MV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_NOP, + RISCV_INS_C_NOP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_OR, + RISCV_INS_C_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_SD, + RISCV_INS_C_SD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_C_SDSP, + RISCV_INS_C_SDSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_C_SLLI, + RISCV_INS_C_SLLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_SRAI, + RISCV_INS_C_SRAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_SRLI, + RISCV_INS_C_SRLI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_SUB, + RISCV_INS_C_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_SUBW, + RISCV_INS_C_SUBW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_C_SW, + RISCV_INS_C_SW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_SWSP, + RISCV_INS_C_SWSP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_UNIMP, + RISCV_INS_C_UNIMP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_C_XOR, + RISCV_INS_C_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTC, 0}, + 0, + 0 +#endif + }, + {RISCV_DIV, RISCV_INS_DIV, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_HASSTDEXTM, 0}, 0, + 0 +#endif + }, + {RISCV_DIVU, + RISCV_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, 0}, + 0, + 0 +#endif + }, + {RISCV_DIVUW, + RISCV_INS_DIVUW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_DIVW, + RISCV_INS_DIVW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_EBREAK, + RISCV_INS_EBREAK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_ECALL, + RISCV_INS_ECALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_FADD_D, + RISCV_INS_FADD_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FADD_S, + RISCV_INS_FADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FCLASS_D, + RISCV_INS_FCLASS_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FCLASS_S, + RISCV_INS_FCLASS_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_D_L, + RISCV_INS_FCVT_D_L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_D_LU, + RISCV_INS_FCVT_D_LU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_D_S, + RISCV_INS_FCVT_D_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_D_W, + RISCV_INS_FCVT_D_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_D_WU, + RISCV_INS_FCVT_D_WU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_LU_D, + RISCV_INS_FCVT_LU_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_LU_S, + RISCV_INS_FCVT_LU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_L_D, + RISCV_INS_FCVT_L_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_L_S, + RISCV_INS_FCVT_L_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_S_D, + RISCV_INS_FCVT_S_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_S_L, + RISCV_INS_FCVT_S_L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_S_LU, + RISCV_INS_FCVT_S_LU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_S_W, + RISCV_INS_FCVT_S_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_S_WU, + RISCV_INS_FCVT_S_WU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_WU_D, + RISCV_INS_FCVT_WU_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_WU_S, + RISCV_INS_FCVT_WU_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_W_D, + RISCV_INS_FCVT_W_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FCVT_W_S, + RISCV_INS_FCVT_W_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FDIV_D, + RISCV_INS_FDIV_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FDIV_S, + RISCV_INS_FDIV_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FENCE, + RISCV_INS_FENCE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_FENCE_I, + RISCV_INS_FENCE_I, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_FENCE_TSO, + RISCV_INS_FENCE_TSO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_FEQ_D, + RISCV_INS_FEQ_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FEQ_S, + RISCV_INS_FEQ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FLD, RISCV_INS_FLD, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_HASSTDEXTD, 0}, 0, + 0 +#endif + }, + {RISCV_FLE_D, + RISCV_INS_FLE_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FLE_S, + RISCV_INS_FLE_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FLT_D, + RISCV_INS_FLT_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FLT_S, + RISCV_INS_FLT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FLW, RISCV_INS_FLW, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_HASSTDEXTF, 0}, 0, + 0 +#endif + }, + {RISCV_FMADD_D, + RISCV_INS_FMADD_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FMADD_S, + RISCV_INS_FMADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FMAX_D, + RISCV_INS_FMAX_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FMAX_S, + RISCV_INS_FMAX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FMIN_D, + RISCV_INS_FMIN_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FMIN_S, + RISCV_INS_FMIN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FMSUB_D, + RISCV_INS_FMSUB_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FMSUB_S, + RISCV_INS_FMSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FMUL_D, + RISCV_INS_FMUL_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FMUL_S, + RISCV_INS_FMUL_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FMV_D_X, + RISCV_INS_FMV_D_X, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FMV_W_X, + RISCV_INS_FMV_W_X, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FMV_X_D, + RISCV_INS_FMV_X_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_FMV_X_W, + RISCV_INS_FMV_X_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FNMADD_D, + RISCV_INS_FNMADD_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FNMADD_S, + RISCV_INS_FNMADD_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FNMSUB_D, + RISCV_INS_FNMSUB_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FNMSUB_S, + RISCV_INS_FNMSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FSD, RISCV_INS_FSD, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_HASSTDEXTD, 0}, 0, + 0 +#endif + }, + {RISCV_FSGNJN_D, + RISCV_INS_FSGNJN_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FSGNJN_S, + RISCV_INS_FSGNJN_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FSGNJX_D, + RISCV_INS_FSGNJX_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FSGNJX_S, + RISCV_INS_FSGNJX_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FSGNJ_D, + RISCV_INS_FSGNJ_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FSGNJ_S, + RISCV_INS_FSGNJ_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FSQRT_D, + RISCV_INS_FSQRT_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FSQRT_S, + RISCV_INS_FSQRT_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FSUB_D, + RISCV_INS_FSUB_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTD, 0}, + 0, + 0 +#endif + }, + {RISCV_FSUB_S, + RISCV_INS_FSUB_S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTF, 0}, + 0, + 0 +#endif + }, + {RISCV_FSW, RISCV_INS_FSW, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_HASSTDEXTF, 0}, 0, + 0 +#endif + }, + {RISCV_JAL, RISCV_INS_JAL, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_JALR, RISCV_INS_JALR, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {RISCV_LB, RISCV_INS_LB, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_LBU, RISCV_INS_LBU, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_LD, RISCV_INS_LD, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_ISRV64, 0}, 0, + 0 +#endif + }, + {RISCV_LH, RISCV_INS_LH, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_LHU, RISCV_INS_LHU, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_LR_D, + RISCV_INS_LR_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 #endif -}, -{ - RISCV_LR_D_AQ_RL, RISCV_INS_LR_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_D_RL, RISCV_INS_LR_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_W, RISCV_INS_LR_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_W_AQ, RISCV_INS_LR_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_W_AQ_RL, RISCV_INS_LR_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_W_RL, RISCV_INS_LR_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_LUI, RISCV_INS_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LW, RISCV_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LWU, RISCV_INS_LWU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_MRET, RISCV_INS_MRET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_MUL, RISCV_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_MULH, RISCV_INS_MULH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_MULHSU, RISCV_INS_MULHSU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_MULHU, RISCV_INS_MULHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_MULW, RISCV_INS_MULW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_OR, RISCV_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ORI, RISCV_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_REM, RISCV_INS_REM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_REMU, RISCV_INS_REMU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_REMUW, RISCV_INS_REMUW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_REMW, RISCV_INS_REMW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SB, RISCV_INS_SB, + }, + {RISCV_LR_D_AQ, + RISCV_INS_LR_D_AQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 #endif -}, -{ - RISCV_SC_D, RISCV_INS_SC_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_D_AQ, RISCV_INS_SC_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_D_AQ_RL, RISCV_INS_SC_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_D_RL, RISCV_INS_SC_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_W, RISCV_INS_SC_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_W_AQ, RISCV_INS_SC_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_W_AQ_RL, RISCV_INS_SC_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_W_RL, RISCV_INS_SC_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_SD, RISCV_INS_SD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SFENCE_VMA, RISCV_INS_SFENCE_VMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SH, RISCV_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SLL, RISCV_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SLLI, RISCV_INS_SLLI, + }, + {RISCV_LR_D_AQ_RL, + RISCV_INS_LR_D_AQ_RL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 #endif -}, -{ - RISCV_SLLIW, RISCV_INS_SLLIW, + }, + {RISCV_LR_D_RL, + RISCV_INS_LR_D_RL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 #endif -}, -{ - RISCV_SLLW, RISCV_INS_SLLW, + }, + {RISCV_LR_W, + RISCV_INS_LR_W, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 #endif -}, -{ - RISCV_SLT, RISCV_INS_SLT, + }, + {RISCV_LR_W_AQ, + RISCV_INS_LR_W_AQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 #endif -}, -{ - RISCV_SLTI, RISCV_INS_SLTI, + }, + {RISCV_LR_W_AQ_RL, + RISCV_INS_LR_W_AQ_RL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 #endif -}, -{ - RISCV_SLTIU, RISCV_INS_SLTIU, + }, + {RISCV_LR_W_RL, + RISCV_INS_LR_W_RL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SLTU, RISCV_INS_SLTU, + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_LUI, RISCV_INS_LUI, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_LW, RISCV_INS_LW, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_LWU, RISCV_INS_LWU, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_ISRV64, 0}, 0, + 0 +#endif + }, + {RISCV_MRET, RISCV_INS_MRET, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {RISCV_MUL, RISCV_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_HASSTDEXTM, 0}, 0, + 0 +#endif + }, + {RISCV_MULH, + RISCV_INS_MULH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, 0}, + 0, + 0 +#endif + }, + {RISCV_MULHSU, + RISCV_INS_MULHSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, 0}, + 0, + 0 +#endif + }, + {RISCV_MULHU, + RISCV_INS_MULHU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, 0}, + 0, + 0 +#endif + }, + {RISCV_MULW, + RISCV_INS_MULW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_OR, RISCV_INS_OR, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_ORI, RISCV_INS_ORI, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_REM, RISCV_INS_REM, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_HASSTDEXTM, 0}, 0, + 0 +#endif + }, + {RISCV_REMU, + RISCV_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, 0}, + 0, + 0 +#endif + }, + {RISCV_REMUW, + RISCV_INS_REMUW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_REMW, + RISCV_INS_REMW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_SB, RISCV_INS_SB, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_SC_D, + RISCV_INS_SC_D, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_SC_D_AQ, + RISCV_INS_SC_D_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_SC_D_AQ_RL, + RISCV_INS_SC_D_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_SC_D_RL, + RISCV_INS_SC_D_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_SC_W, + RISCV_INS_SC_W, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_SC_W_AQ, + RISCV_INS_SC_W_AQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_SC_W_AQ_RL, + RISCV_INS_SC_W_AQ_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_SC_W_RL, + RISCV_INS_SC_W_RL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_HASSTDEXTA, 0}, + 0, + 0 +#endif + }, + {RISCV_SD, RISCV_INS_SD, +#ifndef CAPSTONE_DIET + {0}, {0}, {RISCV_GRP_ISRV64, 0}, 0, + 0 +#endif + }, + {RISCV_SFENCE_VMA, + RISCV_INS_SFENCE_VMA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {RISCV_SH, RISCV_INS_SH, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_SLL, RISCV_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_SLLI, RISCV_INS_SLLI, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {RISCV_SLLIW, + RISCV_INS_SLLIW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_SLLW, + RISCV_INS_SLLW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {RISCV_GRP_ISRV64, 0}, + 0, + 0 +#endif + }, + {RISCV_SLT, RISCV_INS_SLT, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_SLTI, RISCV_INS_SLTI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - RISCV_SRA, RISCV_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + }, + {RISCV_SLTIU, + RISCV_INS_SLTIU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 #endif -}, -{ - RISCV_SRAI, RISCV_INS_SRAI, + }, + {RISCV_SLTU, RISCV_INS_SLTU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - RISCV_SRAIW, RISCV_INS_SRAIW, + }, + {RISCV_SRA, RISCV_INS_SRA, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - RISCV_SRAW, RISCV_INS_SRAW, + }, + {RISCV_SRAI, RISCV_INS_SRAI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - RISCV_SRET, RISCV_INS_SRET, + }, + {RISCV_SRAIW, + RISCV_INS_SRAIW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_ISRV64, 0}, + 0, + 0 #endif -}, -{ - RISCV_SRL, RISCV_INS_SRL, + }, + {RISCV_SRAW, + RISCV_INS_SRAW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_ISRV64, 0}, + 0, + 0 #endif -}, -{ - RISCV_SRLI, RISCV_INS_SRLI, + }, + {RISCV_SRET, RISCV_INS_SRET, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - RISCV_SRLIW, RISCV_INS_SRLIW, + }, + {RISCV_SRL, RISCV_INS_SRL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - RISCV_SRLW, RISCV_INS_SRLW, + }, + {RISCV_SRLI, RISCV_INS_SRLI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - RISCV_SUB, RISCV_INS_SUB, + }, + {RISCV_SRLIW, + RISCV_INS_SRLIW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_ISRV64, 0}, + 0, + 0 #endif -}, -{ - RISCV_SUBW, RISCV_INS_SUBW, + }, + {RISCV_SRLW, + RISCV_INS_SRLW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_ISRV64, 0}, + 0, + 0 #endif -}, -{ - RISCV_SW, RISCV_INS_SW, + }, + {RISCV_SUB, RISCV_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - RISCV_UNIMP, RISCV_INS_UNIMP, + }, + {RISCV_SUBW, + RISCV_INS_SUBW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {RISCV_GRP_ISRV64, 0}, + 0, + 0 #endif -}, -{ - RISCV_URET, RISCV_INS_URET, + }, + {RISCV_SW, RISCV_INS_SW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - RISCV_WFI, RISCV_INS_WFI, + }, + {RISCV_UNIMP, + RISCV_INS_UNIMP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, -{ - RISCV_XOR, RISCV_INS_XOR, + }, + {RISCV_URET, RISCV_INS_URET, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {RISCV_WFI, RISCV_INS_WFI, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_XOR, RISCV_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_XORI, RISCV_INS_XORI, + {0}, {0}, {0}, 0, + 0 +#endif + }, + {RISCV_XORI, RISCV_INS_XORI, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, + }, + {RISCV_ZEXTH_RV64, RISCV_INS_INVALID, + #ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 + #endif + }, diff --git a/arch/RISCV/RISCVModule.c b/arch/RISCV/RISCVModule.c index cefd4b11a6..b3d7c93921 100644 --- a/arch/RISCV/RISCVModule.c +++ b/arch/RISCV/RISCVModule.c @@ -1,42 +1,40 @@ /* Capstone Disassembly Engine */ -/* RISC-V Backend By Rodrigo Cortes Porto & +/* RISC-V Backend By Rodrigo Cortes Porto & Shawn Chang , HardenedLinux@2018 */ #ifdef CAPSTONE_HAS_RISCV -#include "../../utils.h" +#include "RISCVModule.h" #include "../../MCRegisterInfo.h" +#include "../../utils.h" #include "RISCVDisassembler.h" #include "RISCVInstPrinter.h" #include "RISCVMapping.h" -#include "RISCVModule.h" -cs_err RISCV_global_init(cs_struct * ud) -{ - MCRegisterInfo *mri; - mri = cs_mem_malloc(sizeof(*mri)); +cs_err RISCV_global_init(cs_struct *ud) { + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); - RISCV_init(mri); - ud->printer = RISCV_printInst; - ud->printer_info = mri; - ud->getinsn_info = mri; - ud->disasm = RISCV_getInstruction; - ud->post_printer = NULL; + RISCV_init(mri); + ud->printer = RISCV_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = RISCV_getInstruction; + ud->post_printer = NULL; - ud->reg_name = RISCV_reg_name; - ud->insn_id = RISCV_get_insn_id; - ud->insn_name = RISCV_insn_name; - ud->group_name = RISCV_group_name; + ud->reg_name = RISCV_reg_name; + ud->insn_id = RISCV_get_insn_id; + ud->insn_name = RISCV_insn_name; + ud->group_name = RISCV_group_name; - return CS_ERR_OK; + return CS_ERR_OK; } -cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value) -{ - if (type == CS_OPT_SYNTAX) - handle->syntax = (int)value; +cs_err RISCV_option(cs_struct *handle, cs_opt_type type, size_t value) { + if (type == CS_OPT_SYNTAX) + handle->syntax = (int)value; - return CS_ERR_OK; + return CS_ERR_OK; } #endif diff --git a/arch/RISCV/RISCVModule.h b/arch/RISCV/RISCVModule.h index c250db554d..df2f2431fd 100644 --- a/arch/RISCV/RISCVModule.h +++ b/arch/RISCV/RISCVModule.h @@ -6,7 +6,7 @@ #include "../../utils.h" -cs_err RISCV_global_init(cs_struct * ud); -cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value); +cs_err RISCV_global_init(cs_struct *ud); +cs_err RISCV_option(cs_struct *handle, cs_opt_type type, size_t value); #endif diff --git a/arch/Sparc/CapstoneSparcModule.h b/arch/Sparc/CapstoneSparcModule.h new file mode 100644 index 0000000000..6bb71817b1 --- /dev/null +++ b/arch/Sparc/CapstoneSparcModule.h @@ -0,0 +1,583 @@ +// +// Created by Phosphorus15 on 2021/7/13. +// + +#ifndef CAPSTONE_CAPSTONESPARCMODULE_H +#define CAPSTONE_CAPSTONESPARCMODULE_H + +static void llvm_unreachable(const char *info) {} + +static void assert(int val) {} + +static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLoadIntPair(MCInst *Inst, unsigned insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLoadCP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLoadCPPair(MCInst *Inst, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeStoreIntPair(MCInst *Inst, unsigned insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, + uint64_t Address, void *Decoder); + +static DecodeStatus DecodeStoreCP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeStoreCPPair(MCInst *Inst, unsigned insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeTRAP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeASRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodePRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +#define GET_REGINFO_ENUM +#define GET_INSTRINFO_ENUM +#define MIPS_GET_DISASSEMBLER +#define GET_REGINFO_MC_DESC + +#include "SparcGenDisassemblerTables.inc" + +FieldFromInstruction(fieldFromInstruction_4, uint32_t) + + DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) + + DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, + decodeToMCInst, uint32_t) + + static const unsigned IntRegDecoderTable[] = { + SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, + SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, + SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, + SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7}; + +static const unsigned FPRegDecoderTable[] = { + SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, + SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, + SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, + SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31}; + +static const unsigned DFPRegDecoderTable[] = { + SP_D0, SP_D16, SP_D1, SP_D17, SP_D2, SP_D18, SP_D3, SP_D19, + SP_D4, SP_D20, SP_D5, SP_D21, SP_D6, SP_D22, SP_D7, SP_D23, + SP_D8, SP_D24, SP_D9, SP_D25, SP_D10, SP_D26, SP_D11, SP_D27, + SP_D12, SP_D28, SP_D13, SP_D29, SP_D14, SP_D30, SP_D15, SP_D31}; + +static const unsigned QFPRegDecoderTable[] = { + SP_Q0, SP_Q8, ~0U, ~0U, SP_Q1, SP_Q9, ~0U, ~0U, SP_Q2, SP_Q10, ~0U, ~0U, + SP_Q3, SP_Q11, ~0U, ~0U, SP_Q4, SP_Q12, ~0U, ~0U, SP_Q5, SP_Q13, ~0U, ~0U, + SP_Q6, SP_Q14, ~0U, ~0U, SP_Q7, SP_Q15, ~0U, ~0U}; + +static const unsigned FCCRegDecoderTable[] = {SP_FCC0, SP_FCC1, SP_FCC2, + SP_FCC3}; + +static const unsigned ASRRegDecoderTable[] = { + SP_Y, SP_ASR1, SP_ASR2, SP_ASR3, SP_ASR4, SP_ASR5, SP_ASR6, + SP_ASR7, SP_ASR8, SP_ASR9, SP_ASR10, SP_ASR11, SP_ASR12, SP_ASR13, + SP_ASR14, SP_ASR15, SP_ASR16, SP_ASR17, SP_ASR18, SP_ASR19, SP_ASR20, + SP_ASR21, SP_ASR22, SP_ASR23, SP_ASR24, SP_ASR25, SP_ASR26, SP_ASR27, + SP_ASR28, SP_ASR29, SP_ASR30, SP_ASR31}; + +static const unsigned PRRegDecoderTable[] = { + SP_TPC, SP_TNPC, SP_TSTATE, SP_TT, SP_TICK, + SP_TBA, SP_PSTATE, SP_TL, SP_PIL, SP_CWP, + SP_CANSAVE, SP_CANRESTORE, SP_CLEANWIN, SP_OTHERWIN, SP_WSTATE}; + +static const uint16_t IntPairDecoderTable[] = { + SP_G0_G1, SP_G2_G3, SP_G4_G5, SP_G6_G7, SP_O0_O1, SP_O2_O3, + SP_O4_O5, SP_O6_O7, SP_L0_L1, SP_L2_L3, SP_L4_L5, SP_L6_L7, + SP_I0_I1, SP_I2_I3, SP_I4_I5, SP_I6_I7, +}; + +static const unsigned CPRegDecoderTable[] = { + SP_C0, SP_C1, SP_C2, SP_C3, SP_C4, SP_C5, SP_C6, SP_C7, + SP_C8, SP_C9, SP_C10, SP_C11, SP_C12, SP_C13, SP_C14, SP_C15, + SP_C16, SP_C17, SP_C18, SP_C19, SP_C20, SP_C21, SP_C22, SP_C23, + SP_C24, SP_C25, SP_C26, SP_C27, SP_C28, SP_C29, SP_C30, SP_C31}; + +static const uint16_t CPPairDecoderTable[] = { + SP_C0_C1, SP_C2_C3, SP_C4_C5, SP_C6_C7, SP_C8_C9, SP_C10_C11, + SP_C12_C13, SP_C14_C15, SP_C16_C17, SP_C18_C19, SP_C20_C21, SP_C22_C23, + SP_C24_C25, SP_C26_C27, SP_C28_C29, SP_C30_C31}; + +static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = IntRegDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = IntRegDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = FPRegDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = DFPRegDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned Reg = QFPRegDecoderTable[RegNo]; + if (Reg == ~0U) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCPRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + unsigned Reg = CPRegDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 3) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeASRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, ASRRegDecoderTable[RegNo]); + return MCDisassembler_Success; +} + +static DecodeStatus DecodePRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo >= sizeof(PRRegDecoderTable)) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, PRRegDecoderTable[RegNo]); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeIntPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + DecodeStatus S = MCDisassembler_Success; + + if (RegNo > 31) + return MCDisassembler_Fail; + + if ((RegNo & 1)) + S = MCDisassembler_SoftFail; + + unsigned RegisterPair = IntPairDecoderTable[RegNo / 2]; + MCOperand_CreateReg0(Inst, RegisterPair); + return S; +} + +static DecodeStatus DecodeCPPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 31) + return MCDisassembler_Fail; + + unsigned RegisterPair = CPPairDecoderTable[RegNo / 2]; + MCOperand_CreateReg0(Inst, RegisterPair); + return MCDisassembler_Success; +} + +typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder, bool isLoad, + DecodeFunc DecodeRD) { + unsigned rd = fieldFromInstruction_4(insn, 25, 5); + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + bool isImm = fieldFromInstruction_4(insn, 13, 1); + bool hasAsi = fieldFromInstruction_4(insn, 23, 1); // (in op3 field) + unsigned asi = fieldFromInstruction_4(insn, 5, 8); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + DecodeStatus status; + if (isLoad) { + status = DecodeRD(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + // Decode rs1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode imm|rs2. + if (isImm) + MCOperand_CreateImm0(MI, simm13); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + if (hasAsi) + MCOperand_CreateImm0(MI, asi); + + if (!isLoad) { + status = DecodeRD(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + return MCDisassembler_Success; +} + +static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeIntRegsRegisterClass); +} + +static DecodeStatus DecodeLoadIntPair(MCInst *Inst, unsigned insn, + uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeIntPairRegisterClass); +} + +static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeFPRegsRegisterClass); +} + +static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeDFPRegsRegisterClass); +} + +static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeQFPRegsRegisterClass); +} + +static DecodeStatus DecodeLoadCP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeCPRegsRegisterClass); +} + +static DecodeStatus DecodeLoadCPPair(MCInst *Inst, unsigned insn, + uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, + DecodeCPPairRegisterClass); +} + +static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, + uint64_t Address, void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeIntRegsRegisterClass); +} + +static DecodeStatus DecodeStoreIntPair(MCInst *Inst, unsigned insn, + uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeIntPairRegisterClass); +} + +static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeFPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, + uint64_t Address, void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeDFPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, + uint64_t Address, void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeQFPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreCP(MCInst *Inst, unsigned insn, uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeCPRegsRegisterClass); +} + +static DecodeStatus DecodeStoreCPPair(MCInst *Inst, unsigned insn, + uint64_t Address, + void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, + DecodeCPPairRegisterClass); +} + +static DecodeStatus DecodeCall(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + unsigned tgt = fieldFromInstruction_4(insn, 0, 30); + tgt <<= 2; + // if (!tryAddingSymbolicOperand(tgt+Address, false, Address, + // 0, 30, MI, Decoder)) + MCOperand_CreateImm0(MI, tgt); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + MCOperand_CreateImm0(MI, tgt); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + + unsigned rd = fieldFromInstruction_4(insn, 25, 5); + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + unsigned isImm = fieldFromInstruction_4(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + // Decode RD. + DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1 | SIMM13. + if (isImm) + MCOperand_CreateImm0(MI, simm13); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + return MCDisassembler_Success; +} + +static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + unsigned isImm = fieldFromInstruction_4(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + // Decode RS1. + DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS2 | SIMM13. + if (isImm) + MCOperand_CreateImm0(MI, simm13); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + + unsigned rd = fieldFromInstruction_4(insn, 25, 5); + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + unsigned isImm = fieldFromInstruction_4(insn, 13, 1); + bool hasAsi = fieldFromInstruction_4(insn, 23, 1); // (in op3 field) + unsigned asi = fieldFromInstruction_4(insn, 5, 8); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + // Decode RD. + DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1 | SIMM13. + if (isImm) + MCOperand_CreateImm0(MI, simm13); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + if (hasAsi) + MCOperand_CreateImm0(MI, asi); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeTRAP(MCInst *MI, unsigned insn, uint64_t Address, + void *Decoder) { + + unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); + unsigned isImm = fieldFromInstruction_4(insn, 13, 1); + unsigned cc = fieldFromInstruction_4(insn, 25, 4); + unsigned rs2 = 0; + unsigned imm7 = 0; + if (isImm) + imm7 = fieldFromInstruction_4(insn, 0, 7); + else + rs2 = fieldFromInstruction_4(insn, 0, 5); + + // Decode RS1. + DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + + // Decode RS1 | IMM7. + if (isImm) + MCOperand_CreateImm0(MI, imm7); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler_Success) + return status; + } + + // Decode CC + MCOperand_CreateImm0(MI, cc); + + return MCDisassembler_Success; +} + +#endif // CAPSTONE_CAPSTONESPARCMODULE_H diff --git a/arch/Sparc/Sparc.h b/arch/Sparc/Sparc.h index 1f773622e5..061bd1847b 100644 --- a/arch/Sparc/Sparc.h +++ b/arch/Sparc/Sparc.h @@ -20,44 +20,76 @@ #include "capstone/sparc.h" -inline static const char *SPARCCondCodeToString(sparc_cc CC) -{ - switch (CC) { - default: return NULL; // unreachable - case SPARC_CC_ICC_A: return "a"; - case SPARC_CC_ICC_N: return "n"; - case SPARC_CC_ICC_NE: return "ne"; - case SPARC_CC_ICC_E: return "e"; - case SPARC_CC_ICC_G: return "g"; - case SPARC_CC_ICC_LE: return "le"; - case SPARC_CC_ICC_GE: return "ge"; - case SPARC_CC_ICC_L: return "l"; - case SPARC_CC_ICC_GU: return "gu"; - case SPARC_CC_ICC_LEU: return "leu"; - case SPARC_CC_ICC_CC: return "cc"; - case SPARC_CC_ICC_CS: return "cs"; - case SPARC_CC_ICC_POS: return "pos"; - case SPARC_CC_ICC_NEG: return "neg"; - case SPARC_CC_ICC_VC: return "vc"; - case SPARC_CC_ICC_VS: return "vs"; +inline static const char *SPARCCondCodeToString(sparc_cc CC) { + switch (CC) { + default: + return NULL; // unreachable + case SPARC_CC_ICC_A: + return "a"; + case SPARC_CC_ICC_N: + return "n"; + case SPARC_CC_ICC_NE: + return "ne"; + case SPARC_CC_ICC_E: + return "e"; + case SPARC_CC_ICC_G: + return "g"; + case SPARC_CC_ICC_LE: + return "le"; + case SPARC_CC_ICC_GE: + return "ge"; + case SPARC_CC_ICC_L: + return "l"; + case SPARC_CC_ICC_GU: + return "gu"; + case SPARC_CC_ICC_LEU: + return "leu"; + case SPARC_CC_ICC_CC: + return "cc"; + case SPARC_CC_ICC_CS: + return "cs"; + case SPARC_CC_ICC_POS: + return "pos"; + case SPARC_CC_ICC_NEG: + return "neg"; + case SPARC_CC_ICC_VC: + return "vc"; + case SPARC_CC_ICC_VS: + return "vs"; - case SPARC_CC_FCC_A: return "a"; - case SPARC_CC_FCC_N: return "n"; - case SPARC_CC_FCC_U: return "u"; - case SPARC_CC_FCC_G: return "g"; - case SPARC_CC_FCC_UG: return "ug"; - case SPARC_CC_FCC_L: return "l"; - case SPARC_CC_FCC_UL: return "ul"; - case SPARC_CC_FCC_LG: return "lg"; - case SPARC_CC_FCC_NE: return "ne"; - case SPARC_CC_FCC_E: return "e"; - case SPARC_CC_FCC_UE: return "ue"; - case SPARC_CC_FCC_GE: return "ge"; - case SPARC_CC_FCC_UGE: return "uge"; - case SPARC_CC_FCC_LE: return "le"; - case SPARC_CC_FCC_ULE: return "ule"; - case SPARC_CC_FCC_O: return "o"; - } + case SPARC_CC_FCC_A: + return "a"; + case SPARC_CC_FCC_N: + return "n"; + case SPARC_CC_FCC_U: + return "u"; + case SPARC_CC_FCC_G: + return "g"; + case SPARC_CC_FCC_UG: + return "ug"; + case SPARC_CC_FCC_L: + return "l"; + case SPARC_CC_FCC_UL: + return "ul"; + case SPARC_CC_FCC_LG: + return "lg"; + case SPARC_CC_FCC_NE: + return "ne"; + case SPARC_CC_FCC_E: + return "e"; + case SPARC_CC_FCC_UE: + return "ue"; + case SPARC_CC_FCC_GE: + return "ge"; + case SPARC_CC_FCC_UGE: + return "uge"; + case SPARC_CC_FCC_LE: + return "le"; + case SPARC_CC_FCC_ULE: + return "ule"; + case SPARC_CC_FCC_O: + return "o"; + } } #endif diff --git a/arch/Sparc/SparcDisassembler.c b/arch/Sparc/SparcDisassembler.c index 3e6d0e0b9e..2b63da4d7f 100644 --- a/arch/Sparc/SparcDisassembler.c +++ b/arch/Sparc/SparcDisassembler.c @@ -1,4 +1,5 @@ -//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// +//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ +//-*-===// // // The LLVM Compiler Infrastructure // @@ -12,7 +13,7 @@ #ifdef CAPSTONE_HAS_SPARC -#include // DEBUG +#include // DEBUG #include #include @@ -21,480 +22,86 @@ #include "SparcDisassembler.h" +#include "../../MCDisassembler.h" +#include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" -#include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" -#include "../../MCDisassembler.h" #include "../../MathExtras.h" - -#define GET_REGINFO_MC_DESC -#define GET_REGINFO_ENUM -#include "SparcGenRegisterInfo.inc" -static const unsigned IntRegDecoderTable[] = { - SP_G0, SP_G1, SP_G2, SP_G3, - SP_G4, SP_G5, SP_G6, SP_G7, - SP_O0, SP_O1, SP_O2, SP_O3, - SP_O4, SP_O5, SP_O6, SP_O7, - SP_L0, SP_L1, SP_L2, SP_L3, - SP_L4, SP_L5, SP_L6, SP_L7, - SP_I0, SP_I1, SP_I2, SP_I3, - SP_I4, SP_I5, SP_I6, SP_I7 -}; - -static const unsigned FPRegDecoderTable[] = { - SP_F0, SP_F1, SP_F2, SP_F3, - SP_F4, SP_F5, SP_F6, SP_F7, - SP_F8, SP_F9, SP_F10, SP_F11, - SP_F12, SP_F13, SP_F14, SP_F15, - SP_F16, SP_F17, SP_F18, SP_F19, - SP_F20, SP_F21, SP_F22, SP_F23, - SP_F24, SP_F25, SP_F26, SP_F27, - SP_F28, SP_F29, SP_F30, SP_F31 -}; - -static const unsigned DFPRegDecoderTable[] = { - SP_D0, SP_D16, SP_D1, SP_D17, - SP_D2, SP_D18, SP_D3, SP_D19, - SP_D4, SP_D20, SP_D5, SP_D21, - SP_D6, SP_D22, SP_D7, SP_D23, - SP_D8, SP_D24, SP_D9, SP_D25, - SP_D10, SP_D26, SP_D11, SP_D27, - SP_D12, SP_D28, SP_D13, SP_D29, - SP_D14, SP_D30, SP_D15, SP_D31 -}; - -static const unsigned QFPRegDecoderTable[] = { - SP_Q0, SP_Q8, ~0U, ~0U, - SP_Q1, SP_Q9, ~0U, ~0U, - SP_Q2, SP_Q10, ~0U, ~0U, - SP_Q3, SP_Q11, ~0U, ~0U, - SP_Q4, SP_Q12, ~0U, ~0U, - SP_Q5, SP_Q13, ~0U, ~0U, - SP_Q6, SP_Q14, ~0U, ~0U, - SP_Q7, SP_Q15, ~0U, ~0U -}; - -static const unsigned FCCRegDecoderTable[] = { - SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3 -}; - -static uint64_t getFeatureBits(int mode) -{ - // support everything - return (uint64_t)-1; -} - -static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = IntRegDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require) { + // extended from original arm module + return Require; } -static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = IntRegDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Reg); +#include "CapstoneSparcModule.h" - return MCDisassembler_Success; +static uint64_t getFeatureBits(int mode) { + // support everything + return (uint64_t)-1; } -static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = FPRegDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = DFPRegDecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg; - - if (RegNo > 31) - return MCDisassembler_Fail; - - Reg = QFPRegDecoderTable[RegNo]; - if (Reg == ~0U) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - if (RegNo > 3) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]); - - return MCDisassembler_Success; -} - - -static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder); - - -#define GET_SUBTARGETINFO_ENUM -#include "SparcGenSubtargetInfo.inc" -#include "SparcGenDisassemblerTables.inc" +//#define GET_SUBTARGETINFO_ENUM +//#include "SparcGenSubtargetInfo.inc" /// readInstruction - read four bytes and return 32 bit word. -static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn) -{ - if (len < 4) - // not enough data - return MCDisassembler_Fail; - - // Encoded as a big-endian 32-bit word in the stream. - *Insn = (code[3] << 0) | - (code[2] << 8) | - (code[1] << 16) | - ((uint32_t) code[0] << 24); - - return MCDisassembler_Success; -} - -bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, - uint16_t *size, uint64_t address, void *info) -{ - uint32_t Insn; - DecodeStatus Result; - - Result = readInstruction32(code, code_len, &Insn); - if (Result == MCDisassembler_Fail) - return false; - - if (MI->flat_insn->detail) { - memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sparc)+sizeof(cs_sparc)); - } - - Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address, - (MCRegisterInfo *)info, 0); - if (Result != MCDisassembler_Fail) { - *size = 4; - return true; - } - - return false; -} - -typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address, - const void *Decoder); - -static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address, - const void *Decoder, - bool isLoad, DecodeFunc DecodeRD) -{ - DecodeStatus status; - unsigned rd = fieldFromInstruction_4(insn, 25, 5); - unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); - bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0; - unsigned rs2 = 0; - unsigned simm13 = 0; - - if (isImm) - simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); - else - rs2 = fieldFromInstruction_4(insn, 0, 5); - - if (isLoad) { - status = DecodeRD(MI, rd, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - } - - // Decode rs1. - status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - - // Decode imm|rs2. - if (isImm) - MCOperand_CreateImm0(MI, simm13); - else { - status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - } - - if (!isLoad) { - status = DecodeRD(MI, rd, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder) -{ - return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeIntRegsRegisterClass); -} - -static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder) -{ - return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeFPRegsRegisterClass); -} - -static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder) -{ - return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeDFPRegsRegisterClass); -} - -static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder) -{ - return DecodeMem(Inst, insn, Address, Decoder, true, - DecodeQFPRegsRegisterClass); -} - -static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, - uint64_t Address, const void *Decoder) -{ - return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeIntRegsRegisterClass); -} - -static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address, - const void *Decoder) -{ - return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeFPRegsRegisterClass); -} - -static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, - uint64_t Address, const void *Decoder) -{ - return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeDFPRegsRegisterClass); -} - -static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, - uint64_t Address, const void *Decoder) -{ - return DecodeMem(Inst, insn, Address, Decoder, false, - DecodeQFPRegsRegisterClass); -} - -static DecodeStatus DecodeCall(MCInst *MI, unsigned insn, - uint64_t Address, const void *Decoder) -{ - unsigned tgt = fieldFromInstruction_4(insn, 0, 30); - tgt <<= 2; - - MCOperand_CreateImm0(MI, tgt); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn, - uint64_t Address, const void *Decoder) -{ - unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); - - MCOperand_CreateImm0(MI, tgt); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address, - const void *Decoder) -{ - DecodeStatus status; - unsigned rd = fieldFromInstruction_4(insn, 25, 5); - unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); - unsigned isImm = fieldFromInstruction_4(insn, 13, 1); - unsigned rs2 = 0; - unsigned simm13 = 0; - - if (isImm) - simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); - else - rs2 = fieldFromInstruction_4(insn, 0, 5); - - // Decode RD. - status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - - // Decode RS1. - status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - - // Decode RS1 | SIMM13. - if (isImm) - MCOperand_CreateImm0(MI, simm13); - else { - status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, - const void *Decoder) -{ - DecodeStatus status; - unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); - unsigned isImm = fieldFromInstruction_4(insn, 13, 1); - unsigned rs2 = 0; - unsigned simm13 = 0; - if (isImm) - simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); - else - rs2 = fieldFromInstruction_4(insn, 0, 5); - - // Decode RS1. - status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - - // Decode RS2 | SIMM13. - if (isImm) - MCOperand_CreateImm0(MI, simm13); - else { - status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - } - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address, - const void *Decoder) -{ - DecodeStatus status; - unsigned rd = fieldFromInstruction_4(insn, 25, 5); - unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); - unsigned isImm = fieldFromInstruction_4(insn, 13, 1); - unsigned rs2 = 0; - unsigned simm13 = 0; - - if (isImm) - simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); - else - rs2 = fieldFromInstruction_4(insn, 0, 5); - - // Decode RD. - status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - - // Decode RS1. - status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - - // Decode RS1 | SIMM13. - if (isImm) - MCOperand_CreateImm0(MI, simm13); - else { - status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); - if (status != MCDisassembler_Success) - return status; - } - - return MCDisassembler_Success; -} - -void Sparc_init(MCRegisterInfo *MRI) -{ - /* - InitMCRegisterInfo(SparcRegDesc, 119, RA, PC, - SparcMCRegisterClasses, 8, - SparcRegUnitRoots, - 86, - SparcRegDiffLists, - SparcRegStrings, - SparcSubRegIdxLists, - 7, - SparcSubRegIdxRanges, - SparcRegEncodingTable); - */ - - MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119, - 0, 0, - SparcMCRegisterClasses, 8, - 0, 0, - SparcRegDiffLists, - 0, - SparcSubRegIdxLists, 7, - 0); +static DecodeStatus readInstruction32(const uint8_t *code, size_t len, + uint32_t *Insn) { + if (len < 4) + // not enough data + return MCDisassembler_Fail; + + // Encoded as a big-endian 32-bit word in the stream. + *Insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | + ((uint32_t)code[0] << 24); + + return MCDisassembler_Success; +} + +bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, uint64_t address, + void *info) { + uint32_t Insn; + DecodeStatus Result; + + Result = readInstruction32(code, code_len, &Insn); + if (Result == MCDisassembler_Fail) + return false; + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, + offsetof(cs_detail, sparc) + sizeof(cs_sparc)); + } + + Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address, + (MCRegisterInfo *)info, 0); + if (Result != MCDisassembler_Fail) { + *size = 4; + return true; + } + + return false; +} + +void Sparc_init(MCRegisterInfo *MRI) { + /* + InitMCRegisterInfo(SparcRegDesc, 119, RA, PC, + SparcMCRegisterClasses, 8, + SparcRegUnitRoots, + 86, + SparcRegDiffLists, + SparcRegStrings, + SparcSubRegIdxLists, + 7, + SparcSubRegIdxRanges, + SparcRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo( + MRI, SparcRegDesc, ARR_SIZE(SparcRegDesc), 0, 0, SparcMCRegisterClasses, + ARR_SIZE(SparcMCRegisterClasses), 0, 0, SparcRegDiffLists, 0, + SparcSubRegIdxLists, ARR_SIZE(SparcSubRegIdxLists), 0); } #endif diff --git a/arch/Sparc/SparcDisassembler.h b/arch/Sparc/SparcDisassembler.h index eccb3cb68c..7c73d68312 100644 --- a/arch/Sparc/SparcDisassembler.h +++ b/arch/Sparc/SparcDisassembler.h @@ -4,14 +4,14 @@ #ifndef CS_SPARCDISASSEMBLER_H #define CS_SPARCDISASSEMBLER_H -#include "capstone/capstone.h" -#include "../../MCRegisterInfo.h" #include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "capstone/capstone.h" void Sparc_init(MCRegisterInfo *MRI); bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); + MCInst *instr, uint16_t *size, uint64_t address, + void *info); #endif - diff --git a/arch/Sparc/SparcGenAsmWriter.inc b/arch/Sparc/SparcGenAsmWriter.inc index d290d3b211..87b91d0947 100644 --- a/arch/Sparc/SparcGenAsmWriter.inc +++ b/arch/Sparc/SparcGenAsmWriter.inc @@ -9,820 +9,3123 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ -#include // debug #include - +#include // debug /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) -{ - static const uint32_t OpInfo[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 2452U, // DBG_VALUE - 0U, // REG_SEQUENCE - 0U, // COPY - 2445U, // BUNDLE - 2462U, // LIFETIME_START - 2432U, // LIFETIME_END - 0U, // STACKMAP - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 4688U, // ADDCCri - 4688U, // ADDCCrr - 5925U, // ADDCri - 5925U, // ADDCrr - 4772U, // ADDEri - 4772U, // ADDErr - 4786U, // ADDXC - 4678U, // ADDXCCC - 4808U, // ADDXri - 4808U, // ADDXrr - 4808U, // ADDri - 4808U, // ADDrr - 74166U, // ADJCALLSTACKDOWN - 74185U, // ADJCALLSTACKUP - 5497U, // ALIGNADDR - 5127U, // ALIGNADDRL - 4695U, // ANDCCri - 4695U, // ANDCCrr - 4718U, // ANDNCCri - 4718U, // ANDNCCrr - 5182U, // ANDNri - 5182U, // ANDNrr - 5182U, // ANDXNrr - 4876U, // ANDXri - 4876U, // ANDXrr - 4876U, // ANDri - 4876U, // ANDrr - 4502U, // ARRAY16 - 4255U, // ARRAY32 - 4526U, // ARRAY8 - 0U, // ATOMIC_LOAD_ADD_32 - 0U, // ATOMIC_LOAD_ADD_64 - 0U, // ATOMIC_LOAD_AND_32 - 0U, // ATOMIC_LOAD_AND_64 - 0U, // ATOMIC_LOAD_MAX_32 - 0U, // ATOMIC_LOAD_MAX_64 - 0U, // ATOMIC_LOAD_MIN_32 - 0U, // ATOMIC_LOAD_MIN_64 - 0U, // ATOMIC_LOAD_NAND_32 - 0U, // ATOMIC_LOAD_NAND_64 - 0U, // ATOMIC_LOAD_OR_32 - 0U, // ATOMIC_LOAD_OR_64 - 0U, // ATOMIC_LOAD_SUB_32 - 0U, // ATOMIC_LOAD_SUB_64 - 0U, // ATOMIC_LOAD_UMAX_32 - 0U, // ATOMIC_LOAD_UMAX_64 - 0U, // ATOMIC_LOAD_UMIN_32 - 0U, // ATOMIC_LOAD_UMIN_64 - 0U, // ATOMIC_LOAD_XOR_32 - 0U, // ATOMIC_LOAD_XOR_64 - 0U, // ATOMIC_SWAP_64 - 74271U, // BA - 1194492U, // BCOND - 1260028U, // BCONDA - 17659U, // BINDri - 17659U, // BINDrr - 5065U, // BMASK - 145915U, // BPFCC - 211451U, // BPFCCA - 276987U, // BPFCCANT - 342523U, // BPFCCNT - 2106465U, // BPGEZapn - 2105838U, // BPGEZapt - 2106532U, // BPGEZnapn - 2107288U, // BPGEZnapt - 2106489U, // BPGZapn - 2105856U, // BPGZapt - 2106552U, // BPGZnapn - 2107384U, // BPGZnapt - 1456636U, // BPICC - 473596U, // BPICCA - 539132U, // BPICCANT - 604668U, // BPICCNT - 2106477U, // BPLEZapn - 2105847U, // BPLEZapt - 2106542U, // BPLEZnapn - 2107337U, // BPLEZnapt - 2106500U, // BPLZapn - 2105864U, // BPLZapt - 2106561U, // BPLZnapn - 2107428U, // BPLZnapt - 2106511U, // BPNZapn - 2105872U, // BPNZapt - 2106570U, // BPNZnapn - 2107472U, // BPNZnapt - 1718780U, // BPXCC - 735740U, // BPXCCA - 801276U, // BPXCCANT - 866812U, // BPXCCNT - 2106522U, // BPZapn - 2105880U, // BPZapt - 2106579U, // BPZnapn - 2107505U, // BPZnapt - 4983U, // BSHUFFLE - 74742U, // CALL - 17398U, // CALLri - 17398U, // CALLrr - 924148U, // CASXrr - 924129U, // CASrr - 74001U, // CMASK16 - 73833U, // CMASK32 - 74150U, // CMASK8 - 2106607U, // CMPri - 2106607U, // CMPrr - 4332U, // EDGE16 - 5081U, // EDGE16L - 5198U, // EDGE16LN - 5165U, // EDGE16N - 4164U, // EDGE32 - 5072U, // EDGE32L - 5188U, // EDGE32LN - 5156U, // EDGE32N - 4511U, // EDGE8 - 5090U, // EDGE8L - 5208U, // EDGE8LN - 5174U, // EDGE8N - 1053516U, // FABSD - 1054031U, // FABSQ - 1054376U, // FABSS - 4813U, // FADDD - 5383U, // FADDQ - 5645U, // FADDS - 4648U, // FALIGNADATA - 4875U, // FAND - 4112U, // FANDNOT1 - 5544U, // FANDNOT1S - 4271U, // FANDNOT2 - 5591U, // FANDNOT2S - 5677U, // FANDS - 1194491U, // FBCOND - 1260027U, // FBCONDA - 4394U, // FCHKSM16 - 2106173U, // FCMPD - 4413U, // FCMPEQ16 - 4226U, // FCMPEQ32 - 4432U, // FCMPGT16 - 4245U, // FCMPGT32 - 4340U, // FCMPLE16 - 4172U, // FCMPLE32 - 4350U, // FCMPNE16 - 4182U, // FCMPNE32 - 2106696U, // FCMPQ - 2107005U, // FCMPS - 4960U, // FDIVD - 5475U, // FDIVQ - 5815U, // FDIVS - 5405U, // FDMULQ - 1053620U, // FDTOI - 1053996U, // FDTOQ - 1054305U, // FDTOS - 1054536U, // FDTOX - 1053464U, // FEXPAND - 4820U, // FHADDD - 5652U, // FHADDS - 4800U, // FHSUBD - 5637U, // FHSUBS - 1053473U, // FITOD - 1054003U, // FITOQ - 1054312U, // FITOS - 6300484U, // FLCMPD - 6301316U, // FLCMPS - 2606U, // FLUSHW - 4404U, // FMEAN16 - 1053543U, // FMOVD - 1006078U, // FMOVD_FCC - 23484926U, // FMOVD_ICC - 23747070U, // FMOVD_XCC - 1054058U, // FMOVQ - 1006102U, // FMOVQ_FCC - 23484950U, // FMOVQ_ICC - 23747094U, // FMOVQ_XCC - 6018U, // FMOVRGEZD - 6029U, // FMOVRGEZQ - 6056U, // FMOVRGEZS - 6116U, // FMOVRGZD - 6126U, // FMOVRGZQ - 6150U, // FMOVRGZS - 6067U, // FMOVRLEZD - 6078U, // FMOVRLEZQ - 6105U, // FMOVRLEZS - 6160U, // FMOVRLZD - 6170U, // FMOVRLZQ - 6194U, // FMOVRLZS - 6204U, // FMOVRNZD - 6214U, // FMOVRNZQ - 6238U, // FMOVRNZS - 6009U, // FMOVRZD - 6248U, // FMOVRZQ - 6269U, // FMOVRZS - 1054398U, // FMOVS - 1006114U, // FMOVS_FCC - 23484962U, // FMOVS_ICC - 23747106U, // FMOVS_XCC - 4490U, // FMUL8SUX16 - 4465U, // FMUL8ULX16 - 4442U, // FMUL8X16 - 5098U, // FMUL8X16AL - 5849U, // FMUL8X16AU - 4860U, // FMULD - 4477U, // FMULD8SUX16 - 4452U, // FMULD8ULX16 - 5413U, // FMULQ - 5714U, // FMULS - 4837U, // FNADDD - 5669U, // FNADDS - 4881U, // FNAND - 5684U, // FNANDS - 1053429U, // FNEGD - 1053974U, // FNEGQ - 1054283U, // FNEGS - 4828U, // FNHADDD - 5660U, // FNHADDS - 4828U, // FNMULD - 5660U, // FNMULS - 5513U, // FNOR - 5778U, // FNORS - 1052698U, // FNOT1 - 1054131U, // FNOT1S - 1052857U, // FNOT2 - 1054178U, // FNOT2S - 5660U, // FNSMULD - 74625U, // FONE - 75324U, // FONES - 5508U, // FOR - 4129U, // FORNOT1 - 5563U, // FORNOT1S - 4288U, // FORNOT2 - 5610U, // FORNOT2S - 5772U, // FORS - 1052936U, // FPACK16 - 4192U, // FPACK32 - 1054507U, // FPACKFIX - 4323U, // FPADD16 - 5620U, // FPADD16S - 4155U, // FPADD32 - 5573U, // FPADD32S - 4297U, // FPADD64 - 4974U, // FPMERGE - 4314U, // FPSUB16 - 4580U, // FPSUB16S - 4146U, // FPSUB32 - 4570U, // FPSUB32S - 1053480U, // FQTOD - 1053627U, // FQTOI - 1054319U, // FQTOS - 1054552U, // FQTOX - 4423U, // FSLAS16 - 4236U, // FSLAS32 - 4378U, // FSLL16 - 4210U, // FSLL32 - 4867U, // FSMULD - 1053523U, // FSQRTD - 1054038U, // FSQRTQ - 1054383U, // FSQRTS - 4306U, // FSRA16 - 4138U, // FSRA32 - 1052681U, // FSRC1 - 1054112U, // FSRC1S - 1052840U, // FSRC2 - 1054159U, // FSRC2S - 4386U, // FSRL16 - 4218U, // FSRL32 - 1053487U, // FSTOD - 1053634U, // FSTOI - 1054010U, // FSTOQ - 1054559U, // FSTOX - 4793U, // FSUBD - 5376U, // FSUBQ - 5630U, // FSUBS - 5519U, // FXNOR - 5785U, // FXNORS - 5526U, // FXOR - 5793U, // FXORS - 1053494U, // FXTOD - 1054017U, // FXTOQ - 1054326U, // FXTOS - 74984U, // FZERO - 75353U, // FZEROS - 24584U, // GETPCX - 1078273U, // JMPLri - 1078273U, // JMPLrr - 1997243U, // LDDFri - 1997243U, // LDDFrr - 1997249U, // LDFri - 1997249U, // LDFrr - 1997275U, // LDQFri - 1997275U, // LDQFrr - 1997229U, // LDSBri - 1997229U, // LDSBrr - 1997254U, // LDSHri - 1997254U, // LDSHrr - 1997287U, // LDSWri - 1997287U, // LDSWrr - 1997236U, // LDUBri - 1997236U, // LDUBrr - 1997261U, // LDUHri - 1997261U, // LDUHrr - 1997294U, // LDXri - 1997294U, // LDXrr - 1997249U, // LDri - 1997249U, // LDrr - 33480U, // LEAX_ADDri - 33480U, // LEA_ADDri - 1054405U, // LZCNT - 75121U, // MEMBARi - 1054543U, // MOVDTOX - 1006122U, // MOVFCCri - 1006122U, // MOVFCCrr - 23484970U, // MOVICCri - 23484970U, // MOVICCrr - 6047U, // MOVRGEZri - 6047U, // MOVRGEZrr - 6142U, // MOVRGZri - 6142U, // MOVRGZrr - 6096U, // MOVRLEZri - 6096U, // MOVRLEZrr - 6186U, // MOVRLZri - 6186U, // MOVRLZrr - 6230U, // MOVRNZri - 6230U, // MOVRNZrr - 6262U, // MOVRRZri - 6262U, // MOVRRZrr - 1054469U, // MOVSTOSW - 1054479U, // MOVSTOUW - 1054543U, // MOVWTOS - 23747114U, // MOVXCCri - 23747114U, // MOVXCCrr - 1054543U, // MOVXTOD - 5954U, // MULXri - 5954U, // MULXrr - 2578U, // NOP - 4735U, // ORCCri - 4735U, // ORCCrr - 4726U, // ORNCCri - 4726U, // ORNCCrr - 5339U, // ORNri - 5339U, // ORNrr - 5339U, // ORXNrr - 5509U, // ORXri - 5509U, // ORXrr - 5509U, // ORri - 5509U, // ORrr - 5836U, // PDIST - 5344U, // PDISTN - 1053356U, // POPCrr - 73729U, // RDY - 4999U, // RESTOREri - 4999U, // RESTORErr - 76132U, // RET - 76141U, // RETL - 18131U, // RETTri - 18131U, // RETTrr - 5008U, // SAVEri - 5008U, // SAVErr - 4748U, // SDIVCCri - 4748U, // SDIVCCrr - 5995U, // SDIVXri - 5995U, // SDIVXrr - 5861U, // SDIVri - 5861U, // SDIVrr - 2182U, // SELECT_CC_DFP_FCC - 2293U, // SELECT_CC_DFP_ICC - 2238U, // SELECT_CC_FP_FCC - 2349U, // SELECT_CC_FP_ICC - 2265U, // SELECT_CC_Int_FCC - 2376U, // SELECT_CC_Int_ICC - 2210U, // SELECT_CC_QFP_FCC - 2321U, // SELECT_CC_QFP_ICC - 1053595U, // SETHIXi - 1053595U, // SETHIi - 2569U, // SHUTDOWN - 2564U, // SIAM - 5941U, // SLLXri - 5941U, // SLLXrr - 5116U, // SLLri - 5116U, // SLLrr - 4702U, // SMULCCri - 4702U, // SMULCCrr - 5144U, // SMULri - 5144U, // SMULrr - 5913U, // SRAXri - 5913U, // SRAXrr - 4643U, // SRAri - 4643U, // SRArr - 5947U, // SRLXri - 5947U, // SRLXrr - 5139U, // SRLri - 5139U, // SRLrr - 2588U, // STBAR - 37428U, // STBri - 37428U, // STBrr - 37723U, // STDFri - 37723U, // STDFrr - 38607U, // STFri - 38607U, // STFrr - 37782U, // STHri - 37782U, // STHrr - 38238U, // STQFri - 38238U, // STQFrr - 38758U, // STXri - 38758U, // STXrr - 38607U, // STri - 38607U, // STrr - 4671U, // SUBCCri - 4671U, // SUBCCrr - 5919U, // SUBCri - 5919U, // SUBCrr - 4764U, // SUBEri - 4764U, // SUBErr - 4665U, // SUBXri - 4665U, // SUBXrr - 4665U, // SUBri - 4665U, // SUBrr - 1997268U, // SWAPri - 1997268U, // SWAPrr - 2422U, // TA3 - 2427U, // TA5 - 5883U, // TADDCCTVri - 5883U, // TADDCCTVrr - 4687U, // TADDCCri - 4687U, // TADDCCrr - 9873960U, // TICCri - 9873960U, // TICCrr - 37753544U, // TLS_ADDXrr - 37753544U, // TLS_ADDrr - 2106358U, // TLS_CALL - 39746030U, // TLS_LDXrr - 39745985U, // TLS_LDrr - 5873U, // TSUBCCTVri - 5873U, // TSUBCCTVrr - 4670U, // TSUBCCri - 4670U, // TSUBCCrr - 10136104U, // TXCCri - 10136104U, // TXCCrr - 4756U, // UDIVCCri - 4756U, // UDIVCCrr - 6002U, // UDIVXri - 6002U, // UDIVXrr - 5867U, // UDIVri - 5867U, // UDIVrr - 4710U, // UMULCCri - 4710U, // UMULCCrr - 5026U, // UMULXHI - 5150U, // UMULri - 5150U, // UMULrr - 74996U, // UNIMP - 6300477U, // V9FCMPD - 6300397U, // V9FCMPED - 6300942U, // V9FCMPEQ - 6301251U, // V9FCMPES - 6301000U, // V9FCMPQ - 6301309U, // V9FCMPS - 47614U, // V9FMOVD_FCC - 47638U, // V9FMOVQ_FCC - 47650U, // V9FMOVS_FCC - 47658U, // V9MOVFCCri - 47658U, // V9MOVFCCrr - 14689692U, // WRYri - 14689692U, // WRYrr - 5953U, // XMULX - 5035U, // XMULXHI - 4733U, // XNORCCri - 4733U, // XNORCCrr - 5520U, // XNORXrr - 5520U, // XNORri - 5520U, // XNORrr - 4741U, // XORCCri - 4741U, // XORCCrr - 5527U, // XORXri - 5527U, // XORXrr - 5527U, // XORri - 5527U, // XORrr - 0U - }; +static void printInstruction(MCInst *MI, SStream *O, + const MCRegisterInfo *MRI) { + static const uint32_t OpInfo[] = {0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2452U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 2445U, // BUNDLE + 2462U, // LIFETIME_START + 2432U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 4688U, // ADDCCri + 4688U, // ADDCCrr + 5925U, // ADDCri + 5925U, // ADDCrr + 4772U, // ADDEri + 4772U, // ADDErr + 4786U, // ADDXC + 4678U, // ADDXCCC + 4808U, // ADDXri + 4808U, // ADDXrr + 4808U, // ADDri + 4808U, // ADDrr + 74166U, // ADJCALLSTACKDOWN + 74185U, // ADJCALLSTACKUP + 5497U, // ALIGNADDR + 5127U, // ALIGNADDRL + 4695U, // ANDCCri + 4695U, // ANDCCrr + 4718U, // ANDNCCri + 4718U, // ANDNCCrr + 5182U, // ANDNri + 5182U, // ANDNrr + 5182U, // ANDXNrr + 4876U, // ANDXri + 4876U, // ANDXrr + 4876U, // ANDri + 4876U, // ANDrr + 4502U, // ARRAY16 + 4255U, // ARRAY32 + 4526U, // ARRAY8 + 0U, // ATOMIC_LOAD_ADD_32 + 0U, // ATOMIC_LOAD_ADD_64 + 0U, // ATOMIC_LOAD_AND_32 + 0U, // ATOMIC_LOAD_AND_64 + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NAND_32 + 0U, // ATOMIC_LOAD_NAND_64 + 0U, // ATOMIC_LOAD_OR_32 + 0U, // ATOMIC_LOAD_OR_64 + 0U, // ATOMIC_LOAD_SUB_32 + 0U, // ATOMIC_LOAD_SUB_64 + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XOR_32 + 0U, // ATOMIC_LOAD_XOR_64 + 0U, // ATOMIC_SWAP_64 + 74271U, // BA + 1194492U, // BCOND + 1260028U, // BCONDA + 17659U, // BINDri + 17659U, // BINDrr + 5065U, // BMASK + 145915U, // BPFCC + 211451U, // BPFCCA + 276987U, // BPFCCANT + 342523U, // BPFCCNT + 2106465U, // BPGEZapn + 2105838U, // BPGEZapt + 2106532U, // BPGEZnapn + 2107288U, // BPGEZnapt + 2106489U, // BPGZapn + 2105856U, // BPGZapt + 2106552U, // BPGZnapn + 2107384U, // BPGZnapt + 1456636U, // BPICC + 473596U, // BPICCA + 539132U, // BPICCANT + 604668U, // BPICCNT + 2106477U, // BPLEZapn + 2105847U, // BPLEZapt + 2106542U, // BPLEZnapn + 2107337U, // BPLEZnapt + 2106500U, // BPLZapn + 2105864U, // BPLZapt + 2106561U, // BPLZnapn + 2107428U, // BPLZnapt + 2106511U, // BPNZapn + 2105872U, // BPNZapt + 2106570U, // BPNZnapn + 2107472U, // BPNZnapt + 1718780U, // BPXCC + 735740U, // BPXCCA + 801276U, // BPXCCANT + 866812U, // BPXCCNT + 2106522U, // BPZapn + 2105880U, // BPZapt + 2106579U, // BPZnapn + 2107505U, // BPZnapt + 4983U, // BSHUFFLE + 74742U, // CALL + 17398U, // CALLri + 17398U, // CALLrr + 924148U, // CASXrr + 924129U, // CASrr + 74001U, // CMASK16 + 73833U, // CMASK32 + 74150U, // CMASK8 + 2106607U, // CMPri + 2106607U, // CMPrr + 4332U, // EDGE16 + 5081U, // EDGE16L + 5198U, // EDGE16LN + 5165U, // EDGE16N + 4164U, // EDGE32 + 5072U, // EDGE32L + 5188U, // EDGE32LN + 5156U, // EDGE32N + 4511U, // EDGE8 + 5090U, // EDGE8L + 5208U, // EDGE8LN + 5174U, // EDGE8N + 1053516U, // FABSD + 1054031U, // FABSQ + 1054376U, // FABSS + 4813U, // FADDD + 5383U, // FADDQ + 5645U, // FADDS + 4648U, // FALIGNADATA + 4875U, // FAND + 4112U, // FANDNOT1 + 5544U, // FANDNOT1S + 4271U, // FANDNOT2 + 5591U, // FANDNOT2S + 5677U, // FANDS + 1194491U, // FBCOND + 1260027U, // FBCONDA + 4394U, // FCHKSM16 + 2106173U, // FCMPD + 4413U, // FCMPEQ16 + 4226U, // FCMPEQ32 + 4432U, // FCMPGT16 + 4245U, // FCMPGT32 + 4340U, // FCMPLE16 + 4172U, // FCMPLE32 + 4350U, // FCMPNE16 + 4182U, // FCMPNE32 + 2106696U, // FCMPQ + 2107005U, // FCMPS + 4960U, // FDIVD + 5475U, // FDIVQ + 5815U, // FDIVS + 5405U, // FDMULQ + 1053620U, // FDTOI + 1053996U, // FDTOQ + 1054305U, // FDTOS + 1054536U, // FDTOX + 1053464U, // FEXPAND + 4820U, // FHADDD + 5652U, // FHADDS + 4800U, // FHSUBD + 5637U, // FHSUBS + 1053473U, // FITOD + 1054003U, // FITOQ + 1054312U, // FITOS + 6300484U, // FLCMPD + 6301316U, // FLCMPS + 2606U, // FLUSHW + 4404U, // FMEAN16 + 1053543U, // FMOVD + 1006078U, // FMOVD_FCC + 23484926U, // FMOVD_ICC + 23747070U, // FMOVD_XCC + 1054058U, // FMOVQ + 1006102U, // FMOVQ_FCC + 23484950U, // FMOVQ_ICC + 23747094U, // FMOVQ_XCC + 6018U, // FMOVRGEZD + 6029U, // FMOVRGEZQ + 6056U, // FMOVRGEZS + 6116U, // FMOVRGZD + 6126U, // FMOVRGZQ + 6150U, // FMOVRGZS + 6067U, // FMOVRLEZD + 6078U, // FMOVRLEZQ + 6105U, // FMOVRLEZS + 6160U, // FMOVRLZD + 6170U, // FMOVRLZQ + 6194U, // FMOVRLZS + 6204U, // FMOVRNZD + 6214U, // FMOVRNZQ + 6238U, // FMOVRNZS + 6009U, // FMOVRZD + 6248U, // FMOVRZQ + 6269U, // FMOVRZS + 1054398U, // FMOVS + 1006114U, // FMOVS_FCC + 23484962U, // FMOVS_ICC + 23747106U, // FMOVS_XCC + 4490U, // FMUL8SUX16 + 4465U, // FMUL8ULX16 + 4442U, // FMUL8X16 + 5098U, // FMUL8X16AL + 5849U, // FMUL8X16AU + 4860U, // FMULD + 4477U, // FMULD8SUX16 + 4452U, // FMULD8ULX16 + 5413U, // FMULQ + 5714U, // FMULS + 4837U, // FNADDD + 5669U, // FNADDS + 4881U, // FNAND + 5684U, // FNANDS + 1053429U, // FNEGD + 1053974U, // FNEGQ + 1054283U, // FNEGS + 4828U, // FNHADDD + 5660U, // FNHADDS + 4828U, // FNMULD + 5660U, // FNMULS + 5513U, // FNOR + 5778U, // FNORS + 1052698U, // FNOT1 + 1054131U, // FNOT1S + 1052857U, // FNOT2 + 1054178U, // FNOT2S + 5660U, // FNSMULD + 74625U, // FONE + 75324U, // FONES + 5508U, // FOR + 4129U, // FORNOT1 + 5563U, // FORNOT1S + 4288U, // FORNOT2 + 5610U, // FORNOT2S + 5772U, // FORS + 1052936U, // FPACK16 + 4192U, // FPACK32 + 1054507U, // FPACKFIX + 4323U, // FPADD16 + 5620U, // FPADD16S + 4155U, // FPADD32 + 5573U, // FPADD32S + 4297U, // FPADD64 + 4974U, // FPMERGE + 4314U, // FPSUB16 + 4580U, // FPSUB16S + 4146U, // FPSUB32 + 4570U, // FPSUB32S + 1053480U, // FQTOD + 1053627U, // FQTOI + 1054319U, // FQTOS + 1054552U, // FQTOX + 4423U, // FSLAS16 + 4236U, // FSLAS32 + 4378U, // FSLL16 + 4210U, // FSLL32 + 4867U, // FSMULD + 1053523U, // FSQRTD + 1054038U, // FSQRTQ + 1054383U, // FSQRTS + 4306U, // FSRA16 + 4138U, // FSRA32 + 1052681U, // FSRC1 + 1054112U, // FSRC1S + 1052840U, // FSRC2 + 1054159U, // FSRC2S + 4386U, // FSRL16 + 4218U, // FSRL32 + 1053487U, // FSTOD + 1053634U, // FSTOI + 1054010U, // FSTOQ + 1054559U, // FSTOX + 4793U, // FSUBD + 5376U, // FSUBQ + 5630U, // FSUBS + 5519U, // FXNOR + 5785U, // FXNORS + 5526U, // FXOR + 5793U, // FXORS + 1053494U, // FXTOD + 1054017U, // FXTOQ + 1054326U, // FXTOS + 74984U, // FZERO + 75353U, // FZEROS + 24584U, // GETPCX + 1078273U, // JMPLri + 1078273U, // JMPLrr + 1997243U, // LDDFri + 1997243U, // LDDFrr + 1997249U, // LDFri + 1997249U, // LDFrr + 1997275U, // LDQFri + 1997275U, // LDQFrr + 1997229U, // LDSBri + 1997229U, // LDSBrr + 1997254U, // LDSHri + 1997254U, // LDSHrr + 1997287U, // LDSWri + 1997287U, // LDSWrr + 1997236U, // LDUBri + 1997236U, // LDUBrr + 1997261U, // LDUHri + 1997261U, // LDUHrr + 1997294U, // LDXri + 1997294U, // LDXrr + 1997249U, // LDri + 1997249U, // LDrr + 33480U, // LEAX_ADDri + 33480U, // LEA_ADDri + 1054405U, // LZCNT + 75121U, // MEMBARi + 1054543U, // MOVDTOX + 1006122U, // MOVFCCri + 1006122U, // MOVFCCrr + 23484970U, // MOVICCri + 23484970U, // MOVICCrr + 6047U, // MOVRGEZri + 6047U, // MOVRGEZrr + 6142U, // MOVRGZri + 6142U, // MOVRGZrr + 6096U, // MOVRLEZri + 6096U, // MOVRLEZrr + 6186U, // MOVRLZri + 6186U, // MOVRLZrr + 6230U, // MOVRNZri + 6230U, // MOVRNZrr + 6262U, // MOVRRZri + 6262U, // MOVRRZrr + 1054469U, // MOVSTOSW + 1054479U, // MOVSTOUW + 1054543U, // MOVWTOS + 23747114U, // MOVXCCri + 23747114U, // MOVXCCrr + 1054543U, // MOVXTOD + 5954U, // MULXri + 5954U, // MULXrr + 2578U, // NOP + 4735U, // ORCCri + 4735U, // ORCCrr + 4726U, // ORNCCri + 4726U, // ORNCCrr + 5339U, // ORNri + 5339U, // ORNrr + 5339U, // ORXNrr + 5509U, // ORXri + 5509U, // ORXrr + 5509U, // ORri + 5509U, // ORrr + 5836U, // PDIST + 5344U, // PDISTN + 1053356U, // POPCrr + 73729U, // RDY + 4999U, // RESTOREri + 4999U, // RESTORErr + 76132U, // RET + 76141U, // RETL + 18131U, // RETTri + 18131U, // RETTrr + 5008U, // SAVEri + 5008U, // SAVErr + 4748U, // SDIVCCri + 4748U, // SDIVCCrr + 5995U, // SDIVXri + 5995U, // SDIVXrr + 5861U, // SDIVri + 5861U, // SDIVrr + 2182U, // SELECT_CC_DFP_FCC + 2293U, // SELECT_CC_DFP_ICC + 2238U, // SELECT_CC_FP_FCC + 2349U, // SELECT_CC_FP_ICC + 2265U, // SELECT_CC_Int_FCC + 2376U, // SELECT_CC_Int_ICC + 2210U, // SELECT_CC_QFP_FCC + 2321U, // SELECT_CC_QFP_ICC + 1053595U, // SETHIXi + 1053595U, // SETHIi + 2569U, // SHUTDOWN + 2564U, // SIAM + 5941U, // SLLXri + 5941U, // SLLXrr + 5116U, // SLLri + 5116U, // SLLrr + 4702U, // SMULCCri + 4702U, // SMULCCrr + 5144U, // SMULri + 5144U, // SMULrr + 5913U, // SRAXri + 5913U, // SRAXrr + 4643U, // SRAri + 4643U, // SRArr + 5947U, // SRLXri + 5947U, // SRLXrr + 5139U, // SRLri + 5139U, // SRLrr + 2588U, // STBAR + 37428U, // STBri + 37428U, // STBrr + 37723U, // STDFri + 37723U, // STDFrr + 38607U, // STFri + 38607U, // STFrr + 37782U, // STHri + 37782U, // STHrr + 38238U, // STQFri + 38238U, // STQFrr + 38758U, // STXri + 38758U, // STXrr + 38607U, // STri + 38607U, // STrr + 4671U, // SUBCCri + 4671U, // SUBCCrr + 5919U, // SUBCri + 5919U, // SUBCrr + 4764U, // SUBEri + 4764U, // SUBErr + 4665U, // SUBXri + 4665U, // SUBXrr + 4665U, // SUBri + 4665U, // SUBrr + 1997268U, // SWAPri + 1997268U, // SWAPrr + 2422U, // TA3 + 2427U, // TA5 + 5883U, // TADDCCTVri + 5883U, // TADDCCTVrr + 4687U, // TADDCCri + 4687U, // TADDCCrr + 9873960U, // TICCri + 9873960U, // TICCrr + 37753544U, // TLS_ADDXrr + 37753544U, // TLS_ADDrr + 2106358U, // TLS_CALL + 39746030U, // TLS_LDXrr + 39745985U, // TLS_LDrr + 5873U, // TSUBCCTVri + 5873U, // TSUBCCTVrr + 4670U, // TSUBCCri + 4670U, // TSUBCCrr + 10136104U, // TXCCri + 10136104U, // TXCCrr + 4756U, // UDIVCCri + 4756U, // UDIVCCrr + 6002U, // UDIVXri + 6002U, // UDIVXrr + 5867U, // UDIVri + 5867U, // UDIVrr + 4710U, // UMULCCri + 4710U, // UMULCCrr + 5026U, // UMULXHI + 5150U, // UMULri + 5150U, // UMULrr + 74996U, // UNIMP + 6300477U, // V9FCMPD + 6300397U, // V9FCMPED + 6300942U, // V9FCMPEQ + 6301251U, // V9FCMPES + 6301000U, // V9FCMPQ + 6301309U, // V9FCMPS + 47614U, // V9FMOVD_FCC + 47638U, // V9FMOVQ_FCC + 47650U, // V9FMOVS_FCC + 47658U, // V9MOVFCCri + 47658U, // V9MOVFCCrr + 14689692U, // WRYri + 14689692U, // WRYrr + 5953U, // XMULX + 5035U, // XMULXHI + 4733U, // XNORCCri + 4733U, // XNORCCrr + 5520U, // XNORXrr + 5520U, // XNORri + 5520U, // XNORrr + 4741U, // XORCCri + 4741U, // XORCCrr + 5527U, // XORXri + 5527U, // XORXrr + 5527U, // XORri + 5527U, // XORrr + 0U}; #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0, - /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0, - /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0, - /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0, - /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0, - /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0, - /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0, - /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0, - /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0, - /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0, - /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0, - /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0, - /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0, - /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0, - /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0, - /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0, - /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0, - /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0, - /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0, - /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0, - /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0, - /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0, - /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0, - /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0, - /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0, - /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0, - /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0, - /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0, - /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0, - /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0, - /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0, - /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0, - /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0, - /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0, - /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0, - /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0, - /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0, - /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0, - /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0, - /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0, - /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0, - /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0, - /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0, - /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0, - /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0, - /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0, - /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0, - /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0, - /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, - /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, - /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0, - /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0, - /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0, - /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0, - /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0, - /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0, - /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0, - /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0, - /* 542 */ 'b', 'a', 32, 0, - /* 546 */ 's', 'r', 'a', 32, 0, - /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0, - /* 563 */ 's', 't', 'b', 32, 0, - /* 568 */ 's', 'u', 'b', 32, 0, - /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0, - /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0, - /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0, - /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0, - /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0, - /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0, - /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0, - /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0, - /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0, - /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0, - /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0, - /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0, - /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0, - /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0, - /* 683 */ 'p', 'o', 'p', 'c', 32, 0, - /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0, - /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0, - /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0, - /* 711 */ 'a', 'd', 'd', 32, 0, - /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0, - /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0, - /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0, - /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0, - /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0, - /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0, - /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0, - /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0, - /* 778 */ 'f', 'a', 'n', 'd', 32, 0, - /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0, - /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0, - /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0, - /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0, - /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0, - /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0, - /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0, - /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0, - /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0, - /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0, - /* 858 */ 's', 't', 'd', 32, 0, - /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0, - /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0, - /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0, - /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0, - /* 896 */ 'f', 'o', 'n', 'e', 32, 0, - /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0, - /* 911 */ 's', 'a', 'v', 'e', 32, 0, - /* 917 */ 's', 't', 'h', 32, 0, - /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0, - /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, - /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, - /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0, - /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0, - /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0, - /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0, - /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0, - /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0, - /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0, - /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0, - /* 1013 */ 'c', 'a', 'l', 'l', 32, 0, - /* 1019 */ 's', 'l', 'l', 32, 0, - /* 1024 */ 'j', 'm', 'p', 'l', 32, 0, - /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0, - /* 1042 */ 's', 'r', 'l', 32, 0, - /* 1047 */ 's', 'm', 'u', 'l', 32, 0, - /* 1053 */ 'u', 'm', 'u', 'l', 32, 0, - /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0, - /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0, - /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0, - /* 1085 */ 'a', 'n', 'd', 'n', 32, 0, - /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0, - /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0, - /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0, - /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, - /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, - /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0, - /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0, - /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0, - /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0, - /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0, - /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0, - /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0, - /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0, - /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0, - /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0, - /* 1242 */ 'o', 'r', 'n', 32, 0, - /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0, - /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0, - /* 1262 */ 'c', 'm', 'p', 32, 0, - /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0, - /* 1274 */ 'j', 'm', 'p', 32, 0, - /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0, - /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0, - /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0, - /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0, - /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0, - /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0, - /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0, - /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0, - /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0, - /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0, - /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0, - /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0, - /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0, - /* 1373 */ 's', 't', 'q', 32, 0, - /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0, - /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0, - /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0, - /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0, - /* 1411 */ 'f', 'o', 'r', 32, 0, - /* 1416 */ 'f', 'n', 'o', 'r', 32, 0, - /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0, - /* 1429 */ 'f', 'x', 'o', 'r', 32, 0, - /* 1435 */ 'w', 'r', 32, 0, - /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0, - /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0, - /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0, - /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0, - /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0, - /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0, - /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0, - /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0, - /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0, - /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0, - /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0, - /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0, - /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0, - /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0, - /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0, - /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0, - /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0, - /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0, - /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0, - /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0, - /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0, - /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0, - /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0, - /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0, - /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0, - /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0, - /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0, - /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0, - /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0, - /* 1675 */ 'f', 'o', 'r', 's', 32, 0, - /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0, - /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0, - /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0, - /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0, - /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0, - /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0, - /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0, - /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0, - /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0, - /* 1746 */ 'r', 'e', 't', 't', 32, 0, - /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0, - /* 1764 */ 's', 'd', 'i', 'v', 32, 0, - /* 1770 */ 'u', 'd', 'i', 'v', 32, 0, - /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0, - /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0, - /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0, - /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0, - /* 1816 */ 's', 'r', 'a', 'x', 32, 0, - /* 1822 */ 's', 'u', 'b', 'x', 32, 0, - /* 1828 */ 'a', 'd', 'd', 'x', 32, 0, - /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0, - /* 1844 */ 's', 'l', 'l', 'x', 32, 0, - /* 1850 */ 's', 'r', 'l', 'x', 32, 0, - /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0, - /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0, - /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0, - /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0, - /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0, - /* 1893 */ 's', 't', 'x', 32, 0, - /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0, - /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0, - /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0, - /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0, - /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0, - /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0, - /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0, - /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0, - /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0, - /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0, - /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0, - /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0, - /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0, - /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0, - /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0, - /* 2039 */ 'b', 'r', 'g', 'z', 32, 0, - /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0, - /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0, - /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0, - /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0, - /* 2083 */ 'b', 'r', 'l', 'z', 32, 0, - /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0, - /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0, - /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0, - /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0, - /* 2127 */ 'b', 'r', 'n', 'z', 32, 0, - /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0, - /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0, - /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0, - /* 2160 */ 'b', 'r', 'z', 32, 0, - /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0, - /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0, - /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, - /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, - /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, - /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, - /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, - /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, - /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, - /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, - /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0, - /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0, - /* 2421 */ 't', 'a', 32, '3', 0, - /* 2426 */ 't', 'a', 32, '5', 0, - /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0, - /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0, - /* 2490 */ 'l', 'd', 'd', 32, '[', 0, - /* 2496 */ 'l', 'd', 32, '[', 0, - /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0, - /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0, - /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0, - /* 2522 */ 'l', 'd', 'q', 32, '[', 0, - /* 2528 */ 'c', 'a', 's', 32, '[', 0, - /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0, - /* 2541 */ 'l', 'd', 'x', 32, '[', 0, - /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0, - /* 2554 */ 'f', 'b', 0, - /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0, - /* 2563 */ 's', 'i', 'a', 'm', 0, - /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0, - /* 2577 */ 'n', 'o', 'p', 0, - /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0, - /* 2587 */ 's', 't', 'b', 'a', 'r', 0, - /* 2593 */ 'f', 'm', 'o', 'v', 's', 0, - /* 2599 */ 't', 0, - /* 2601 */ 'm', 'o', 'v', 0, - /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0, + /* 0 */ 'r', + 'd', + 32, + '%', + 'y', + ',', + 32, + 0, + /* 8 */ 'f', + 's', + 'r', + 'c', + '1', + 32, + 0, + /* 15 */ 'f', + 'a', + 'n', + 'd', + 'n', + 'o', + 't', + '1', + 32, + 0, + /* 25 */ 'f', + 'n', + 'o', + 't', + '1', + 32, + 0, + /* 32 */ 'f', + 'o', + 'r', + 'n', + 'o', + 't', + '1', + 32, + 0, + /* 41 */ 'f', + 's', + 'r', + 'a', + '3', + '2', + 32, + 0, + /* 49 */ 'f', + 'p', + 's', + 'u', + 'b', + '3', + '2', + 32, + 0, + /* 58 */ 'f', + 'p', + 'a', + 'd', + 'd', + '3', + '2', + 32, + 0, + /* 67 */ 'e', + 'd', + 'g', + 'e', + '3', + '2', + 32, + 0, + /* 75 */ 'f', + 'c', + 'm', + 'p', + 'l', + 'e', + '3', + '2', + 32, + 0, + /* 85 */ 'f', + 'c', + 'm', + 'p', + 'n', + 'e', + '3', + '2', + 32, + 0, + /* 95 */ 'f', + 'p', + 'a', + 'c', + 'k', + '3', + '2', + 32, + 0, + /* 104 */ 'c', + 'm', + 'a', + 's', + 'k', + '3', + '2', + 32, + 0, + /* 113 */ 'f', + 's', + 'l', + 'l', + '3', + '2', + 32, + 0, + /* 121 */ 'f', + 's', + 'r', + 'l', + '3', + '2', + 32, + 0, + /* 129 */ 'f', + 'c', + 'm', + 'p', + 'e', + 'q', + '3', + '2', + 32, + 0, + /* 139 */ 'f', + 's', + 'l', + 'a', + 's', + '3', + '2', + 32, + 0, + /* 148 */ 'f', + 'c', + 'm', + 'p', + 'g', + 't', + '3', + '2', + 32, + 0, + /* 158 */ 'a', + 'r', + 'r', + 'a', + 'y', + '3', + '2', + 32, + 0, + /* 167 */ 'f', + 's', + 'r', + 'c', + '2', + 32, + 0, + /* 174 */ 'f', + 'a', + 'n', + 'd', + 'n', + 'o', + 't', + '2', + 32, + 0, + /* 184 */ 'f', + 'n', + 'o', + 't', + '2', + 32, + 0, + /* 191 */ 'f', + 'o', + 'r', + 'n', + 'o', + 't', + '2', + 32, + 0, + /* 200 */ 'f', + 'p', + 'a', + 'd', + 'd', + '6', + '4', + 32, + 0, + /* 209 */ 'f', + 's', + 'r', + 'a', + '1', + '6', + 32, + 0, + /* 217 */ 'f', + 'p', + 's', + 'u', + 'b', + '1', + '6', + 32, + 0, + /* 226 */ 'f', + 'p', + 'a', + 'd', + 'd', + '1', + '6', + 32, + 0, + /* 235 */ 'e', + 'd', + 'g', + 'e', + '1', + '6', + 32, + 0, + /* 243 */ 'f', + 'c', + 'm', + 'p', + 'l', + 'e', + '1', + '6', + 32, + 0, + /* 253 */ 'f', + 'c', + 'm', + 'p', + 'n', + 'e', + '1', + '6', + 32, + 0, + /* 263 */ 'f', + 'p', + 'a', + 'c', + 'k', + '1', + '6', + 32, + 0, + /* 272 */ 'c', + 'm', + 'a', + 's', + 'k', + '1', + '6', + 32, + 0, + /* 281 */ 'f', + 's', + 'l', + 'l', + '1', + '6', + 32, + 0, + /* 289 */ 'f', + 's', + 'r', + 'l', + '1', + '6', + 32, + 0, + /* 297 */ 'f', + 'c', + 'h', + 'k', + 's', + 'm', + '1', + '6', + 32, + 0, + /* 307 */ 'f', + 'm', + 'e', + 'a', + 'n', + '1', + '6', + 32, + 0, + /* 316 */ 'f', + 'c', + 'm', + 'p', + 'e', + 'q', + '1', + '6', + 32, + 0, + /* 326 */ 'f', + 's', + 'l', + 'a', + 's', + '1', + '6', + 32, + 0, + /* 335 */ 'f', + 'c', + 'm', + 'p', + 'g', + 't', + '1', + '6', + 32, + 0, + /* 345 */ 'f', + 'm', + 'u', + 'l', + '8', + 'x', + '1', + '6', + 32, + 0, + /* 355 */ 'f', + 'm', + 'u', + 'l', + 'd', + '8', + 'u', + 'l', + 'x', + '1', + '6', + 32, + 0, + /* 368 */ 'f', + 'm', + 'u', + 'l', + '8', + 'u', + 'l', + 'x', + '1', + '6', + 32, + 0, + /* 380 */ 'f', + 'm', + 'u', + 'l', + 'd', + '8', + 's', + 'u', + 'x', + '1', + '6', + 32, + 0, + /* 393 */ 'f', + 'm', + 'u', + 'l', + '8', + 's', + 'u', + 'x', + '1', + '6', + 32, + 0, + /* 405 */ 'a', + 'r', + 'r', + 'a', + 'y', + '1', + '6', + 32, + 0, + /* 414 */ 'e', + 'd', + 'g', + 'e', + '8', + 32, + 0, + /* 421 */ 'c', + 'm', + 'a', + 's', + 'k', + '8', + 32, + 0, + /* 429 */ 'a', + 'r', + 'r', + 'a', + 'y', + '8', + 32, + 0, + /* 437 */ '!', + 'A', + 'D', + 'J', + 'C', + 'A', + 'L', + 'L', + 'S', + 'T', + 'A', + 'C', + 'K', + 'D', + 'O', + 'W', + 'N', + 32, + 0, + /* 456 */ '!', + 'A', + 'D', + 'J', + 'C', + 'A', + 'L', + 'L', + 'S', + 'T', + 'A', + 'C', + 'K', + 'U', + 'P', + 32, + 0, + /* 473 */ 'f', + 'p', + 's', + 'u', + 'b', + '3', + '2', + 'S', + 32, + 0, + /* 483 */ 'f', + 'p', + 's', + 'u', + 'b', + '1', + '6', + 'S', + 32, + 0, + /* 493 */ 'b', + 'r', + 'g', + 'e', + 'z', + ',', + 'a', + 32, + 0, + /* 502 */ 'b', + 'r', + 'l', + 'e', + 'z', + ',', + 'a', + 32, + 0, + /* 511 */ 'b', + 'r', + 'g', + 'z', + ',', + 'a', + 32, + 0, + /* 519 */ 'b', + 'r', + 'l', + 'z', + ',', + 'a', + 32, + 0, + /* 527 */ 'b', + 'r', + 'n', + 'z', + ',', + 'a', + 32, + 0, + /* 535 */ 'b', + 'r', + 'z', + ',', + 'a', + 32, + 0, + /* 542 */ 'b', + 'a', + 32, + 0, + /* 546 */ 's', + 'r', + 'a', + 32, + 0, + /* 551 */ 'f', + 'a', + 'l', + 'i', + 'g', + 'n', + 'd', + 'a', + 't', + 'a', + 32, + 0, + /* 563 */ 's', + 't', + 'b', + 32, + 0, + /* 568 */ 's', + 'u', + 'b', + 32, + 0, + /* 573 */ 't', + 's', + 'u', + 'b', + 'c', + 'c', + 32, + 0, + /* 581 */ 'a', + 'd', + 'd', + 'x', + 'c', + 'c', + 'c', + 32, + 0, + /* 590 */ 't', + 'a', + 'd', + 'd', + 'c', + 'c', + 32, + 0, + /* 598 */ 'a', + 'n', + 'd', + 'c', + 'c', + 32, + 0, + /* 605 */ 's', + 'm', + 'u', + 'l', + 'c', + 'c', + 32, + 0, + /* 613 */ 'u', + 'm', + 'u', + 'l', + 'c', + 'c', + 32, + 0, + /* 621 */ 'a', + 'n', + 'd', + 'n', + 'c', + 'c', + 32, + 0, + /* 629 */ 'o', + 'r', + 'n', + 'c', + 'c', + 32, + 0, + /* 636 */ 'x', + 'n', + 'o', + 'r', + 'c', + 'c', + 32, + 0, + /* 644 */ 'x', + 'o', + 'r', + 'c', + 'c', + 32, + 0, + /* 651 */ 's', + 'd', + 'i', + 'v', + 'c', + 'c', + 32, + 0, + /* 659 */ 'u', + 'd', + 'i', + 'v', + 'c', + 'c', + 32, + 0, + /* 667 */ 's', + 'u', + 'b', + 'x', + 'c', + 'c', + 32, + 0, + /* 675 */ 'a', + 'd', + 'd', + 'x', + 'c', + 'c', + 32, + 0, + /* 683 */ 'p', + 'o', + 'p', + 'c', + 32, + 0, + /* 689 */ 'a', + 'd', + 'd', + 'x', + 'c', + 32, + 0, + /* 696 */ 'f', + 's', + 'u', + 'b', + 'd', + 32, + 0, + /* 703 */ 'f', + 'h', + 's', + 'u', + 'b', + 'd', + 32, + 0, + /* 711 */ 'a', + 'd', + 'd', + 32, + 0, + /* 716 */ 'f', + 'a', + 'd', + 'd', + 'd', + 32, + 0, + /* 723 */ 'f', + 'h', + 'a', + 'd', + 'd', + 'd', + 32, + 0, + /* 731 */ 'f', + 'n', + 'h', + 'a', + 'd', + 'd', + 'd', + 32, + 0, + /* 740 */ 'f', + 'n', + 'a', + 'd', + 'd', + 'd', + 32, + 0, + /* 748 */ 'f', + 'c', + 'm', + 'p', + 'e', + 'd', + 32, + 0, + /* 756 */ 'f', + 'n', + 'e', + 'g', + 'd', + 32, + 0, + /* 763 */ 'f', + 'm', + 'u', + 'l', + 'd', + 32, + 0, + /* 770 */ 'f', + 's', + 'm', + 'u', + 'l', + 'd', + 32, + 0, + /* 778 */ 'f', + 'a', + 'n', + 'd', + 32, + 0, + /* 784 */ 'f', + 'n', + 'a', + 'n', + 'd', + 32, + 0, + /* 791 */ 'f', + 'e', + 'x', + 'p', + 'a', + 'n', + 'd', + 32, + 0, + /* 800 */ 'f', + 'i', + 't', + 'o', + 'd', + 32, + 0, + /* 807 */ 'f', + 'q', + 't', + 'o', + 'd', + 32, + 0, + /* 814 */ 'f', + 's', + 't', + 'o', + 'd', + 32, + 0, + /* 821 */ 'f', + 'x', + 't', + 'o', + 'd', + 32, + 0, + /* 828 */ 'f', + 'c', + 'm', + 'p', + 'd', + 32, + 0, + /* 835 */ 'f', + 'l', + 'c', + 'm', + 'p', + 'd', + 32, + 0, + /* 843 */ 'f', + 'a', + 'b', + 's', + 'd', + 32, + 0, + /* 850 */ 'f', + 's', + 'q', + 'r', + 't', + 'd', + 32, + 0, + /* 858 */ 's', + 't', + 'd', + 32, + 0, + /* 863 */ 'f', + 'd', + 'i', + 'v', + 'd', + 32, + 0, + /* 870 */ 'f', + 'm', + 'o', + 'v', + 'd', + 32, + 0, + /* 877 */ 'f', + 'p', + 'm', + 'e', + 'r', + 'g', + 'e', + 32, + 0, + /* 886 */ 'b', + 's', + 'h', + 'u', + 'f', + 'f', + 'l', + 'e', + 32, + 0, + /* 896 */ 'f', + 'o', + 'n', + 'e', + 32, + 0, + /* 902 */ 'r', + 'e', + 's', + 't', + 'o', + 'r', + 'e', + 32, + 0, + /* 911 */ 's', + 'a', + 'v', + 'e', + 32, + 0, + /* 917 */ 's', + 't', + 'h', + 32, + 0, + /* 922 */ 's', + 'e', + 't', + 'h', + 'i', + 32, + 0, + /* 929 */ 'u', + 'm', + 'u', + 'l', + 'x', + 'h', + 'i', + 32, + 0, + /* 938 */ 'x', + 'm', + 'u', + 'l', + 'x', + 'h', + 'i', + 32, + 0, + /* 947 */ 'f', + 'd', + 't', + 'o', + 'i', + 32, + 0, + /* 954 */ 'f', + 'q', + 't', + 'o', + 'i', + 32, + 0, + /* 961 */ 'f', + 's', + 't', + 'o', + 'i', + 32, + 0, + /* 968 */ 'b', + 'm', + 'a', + 's', + 'k', + 32, + 0, + /* 975 */ 'e', + 'd', + 'g', + 'e', + '3', + '2', + 'l', + 32, + 0, + /* 984 */ 'e', + 'd', + 'g', + 'e', + '1', + '6', + 'l', + 32, + 0, + /* 993 */ 'e', + 'd', + 'g', + 'e', + '8', + 'l', + 32, + 0, + /* 1001 */ 'f', + 'm', + 'u', + 'l', + '8', + 'x', + '1', + '6', + 'a', + 'l', + 32, + 0, + /* 1013 */ 'c', + 'a', + 'l', + 'l', + 32, + 0, + /* 1019 */ 's', + 'l', + 'l', + 32, + 0, + /* 1024 */ 'j', + 'm', + 'p', + 'l', + 32, + 0, + /* 1030 */ 'a', + 'l', + 'i', + 'g', + 'n', + 'a', + 'd', + 'd', + 'r', + 'l', + 32, + 0, + /* 1042 */ 's', + 'r', + 'l', + 32, + 0, + /* 1047 */ 's', + 'm', + 'u', + 'l', + 32, + 0, + /* 1053 */ 'u', + 'm', + 'u', + 'l', + 32, + 0, + /* 1059 */ 'e', + 'd', + 'g', + 'e', + '3', + '2', + 'n', + 32, + 0, + /* 1068 */ 'e', + 'd', + 'g', + 'e', + '1', + '6', + 'n', + 32, + 0, + /* 1077 */ 'e', + 'd', + 'g', + 'e', + '8', + 'n', + 32, + 0, + /* 1085 */ 'a', + 'n', + 'd', + 'n', + 32, + 0, + /* 1091 */ 'e', + 'd', + 'g', + 'e', + '3', + '2', + 'l', + 'n', + 32, + 0, + /* 1101 */ 'e', + 'd', + 'g', + 'e', + '1', + '6', + 'l', + 'n', + 32, + 0, + /* 1111 */ 'e', + 'd', + 'g', + 'e', + '8', + 'l', + 'n', + 32, + 0, + /* 1120 */ 'b', + 'r', + 'g', + 'e', + 'z', + ',', + 'a', + ',', + 'p', + 'n', + 32, + 0, + /* 1132 */ 'b', + 'r', + 'l', + 'e', + 'z', + ',', + 'a', + ',', + 'p', + 'n', + 32, + 0, + /* 1144 */ 'b', + 'r', + 'g', + 'z', + ',', + 'a', + ',', + 'p', + 'n', + 32, + 0, + /* 1155 */ 'b', + 'r', + 'l', + 'z', + ',', + 'a', + ',', + 'p', + 'n', + 32, + 0, + /* 1166 */ 'b', + 'r', + 'n', + 'z', + ',', + 'a', + ',', + 'p', + 'n', + 32, + 0, + /* 1177 */ 'b', + 'r', + 'z', + ',', + 'a', + ',', + 'p', + 'n', + 32, + 0, + /* 1187 */ 'b', + 'r', + 'g', + 'e', + 'z', + ',', + 'p', + 'n', + 32, + 0, + /* 1197 */ 'b', + 'r', + 'l', + 'e', + 'z', + ',', + 'p', + 'n', + 32, + 0, + /* 1207 */ 'b', + 'r', + 'g', + 'z', + ',', + 'p', + 'n', + 32, + 0, + /* 1216 */ 'b', + 'r', + 'l', + 'z', + ',', + 'p', + 'n', + 32, + 0, + /* 1225 */ 'b', + 'r', + 'n', + 'z', + ',', + 'p', + 'n', + 32, + 0, + /* 1234 */ 'b', + 'r', + 'z', + ',', + 'p', + 'n', + 32, + 0, + /* 1242 */ 'o', + 'r', + 'n', + 32, + 0, + /* 1247 */ 'p', + 'd', + 'i', + 's', + 't', + 'n', + 32, + 0, + /* 1255 */ 'f', + 'z', + 'e', + 'r', + 'o', + 32, + 0, + /* 1262 */ 'c', + 'm', + 'p', + 32, + 0, + /* 1267 */ 'u', + 'n', + 'i', + 'm', + 'p', + 32, + 0, + /* 1274 */ 'j', + 'm', + 'p', + 32, + 0, + /* 1279 */ 'f', + 's', + 'u', + 'b', + 'q', + 32, + 0, + /* 1286 */ 'f', + 'a', + 'd', + 'd', + 'q', + 32, + 0, + /* 1293 */ 'f', + 'c', + 'm', + 'p', + 'e', + 'q', + 32, + 0, + /* 1301 */ 'f', + 'n', + 'e', + 'g', + 'q', + 32, + 0, + /* 1308 */ 'f', + 'd', + 'm', + 'u', + 'l', + 'q', + 32, + 0, + /* 1316 */ 'f', + 'm', + 'u', + 'l', + 'q', + 32, + 0, + /* 1323 */ 'f', + 'd', + 't', + 'o', + 'q', + 32, + 0, + /* 1330 */ 'f', + 'i', + 't', + 'o', + 'q', + 32, + 0, + /* 1337 */ 'f', + 's', + 't', + 'o', + 'q', + 32, + 0, + /* 1344 */ 'f', + 'x', + 't', + 'o', + 'q', + 32, + 0, + /* 1351 */ 'f', + 'c', + 'm', + 'p', + 'q', + 32, + 0, + /* 1358 */ 'f', + 'a', + 'b', + 's', + 'q', + 32, + 0, + /* 1365 */ 'f', + 's', + 'q', + 'r', + 't', + 'q', + 32, + 0, + /* 1373 */ 's', + 't', + 'q', + 32, + 0, + /* 1378 */ 'f', + 'd', + 'i', + 'v', + 'q', + 32, + 0, + /* 1385 */ 'f', + 'm', + 'o', + 'v', + 'q', + 32, + 0, + /* 1392 */ 'm', + 'e', + 'm', + 'b', + 'a', + 'r', + 32, + 0, + /* 1400 */ 'a', + 'l', + 'i', + 'g', + 'n', + 'a', + 'd', + 'd', + 'r', + 32, + 0, + /* 1411 */ 'f', + 'o', + 'r', + 32, + 0, + /* 1416 */ 'f', + 'n', + 'o', + 'r', + 32, + 0, + /* 1422 */ 'f', + 'x', + 'n', + 'o', + 'r', + 32, + 0, + /* 1429 */ 'f', + 'x', + 'o', + 'r', + 32, + 0, + /* 1435 */ 'w', + 'r', + 32, + 0, + /* 1439 */ 'f', + 's', + 'r', + 'c', + '1', + 's', + 32, + 0, + /* 1447 */ 'f', + 'a', + 'n', + 'd', + 'n', + 'o', + 't', + '1', + 's', + 32, + 0, + /* 1458 */ 'f', + 'n', + 'o', + 't', + '1', + 's', + 32, + 0, + /* 1466 */ 'f', + 'o', + 'r', + 'n', + 'o', + 't', + '1', + 's', + 32, + 0, + /* 1476 */ 'f', + 'p', + 'a', + 'd', + 'd', + '3', + '2', + 's', + 32, + 0, + /* 1486 */ 'f', + 's', + 'r', + 'c', + '2', + 's', + 32, + 0, + /* 1494 */ 'f', + 'a', + 'n', + 'd', + 'n', + 'o', + 't', + '2', + 's', + 32, + 0, + /* 1505 */ 'f', + 'n', + 'o', + 't', + '2', + 's', + 32, + 0, + /* 1513 */ 'f', + 'o', + 'r', + 'n', + 'o', + 't', + '2', + 's', + 32, + 0, + /* 1523 */ 'f', + 'p', + 'a', + 'd', + 'd', + '1', + '6', + 's', + 32, + 0, + /* 1533 */ 'f', + 's', + 'u', + 'b', + 's', + 32, + 0, + /* 1540 */ 'f', + 'h', + 's', + 'u', + 'b', + 's', + 32, + 0, + /* 1548 */ 'f', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 1555 */ 'f', + 'h', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 1563 */ 'f', + 'n', + 'h', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 1572 */ 'f', + 'n', + 'a', + 'd', + 'd', + 's', + 32, + 0, + /* 1580 */ 'f', + 'a', + 'n', + 'd', + 's', + 32, + 0, + /* 1587 */ 'f', + 'n', + 'a', + 'n', + 'd', + 's', + 32, + 0, + /* 1595 */ 'f', + 'o', + 'n', + 'e', + 's', + 32, + 0, + /* 1602 */ 'f', + 'c', + 'm', + 'p', + 'e', + 's', + 32, + 0, + /* 1610 */ 'f', + 'n', + 'e', + 'g', + 's', + 32, + 0, + /* 1617 */ 'f', + 'm', + 'u', + 'l', + 's', + 32, + 0, + /* 1624 */ 'f', + 'z', + 'e', + 'r', + 'o', + 's', + 32, + 0, + /* 1632 */ 'f', + 'd', + 't', + 'o', + 's', + 32, + 0, + /* 1639 */ 'f', + 'i', + 't', + 'o', + 's', + 32, + 0, + /* 1646 */ 'f', + 'q', + 't', + 'o', + 's', + 32, + 0, + /* 1653 */ 'f', + 'x', + 't', + 'o', + 's', + 32, + 0, + /* 1660 */ 'f', + 'c', + 'm', + 'p', + 's', + 32, + 0, + /* 1667 */ 'f', + 'l', + 'c', + 'm', + 'p', + 's', + 32, + 0, + /* 1675 */ 'f', + 'o', + 'r', + 's', + 32, + 0, + /* 1681 */ 'f', + 'n', + 'o', + 'r', + 's', + 32, + 0, + /* 1688 */ 'f', + 'x', + 'n', + 'o', + 'r', + 's', + 32, + 0, + /* 1696 */ 'f', + 'x', + 'o', + 'r', + 's', + 32, + 0, + /* 1703 */ 'f', + 'a', + 'b', + 's', + 's', + 32, + 0, + /* 1710 */ 'f', + 's', + 'q', + 'r', + 't', + 's', + 32, + 0, + /* 1718 */ 'f', + 'd', + 'i', + 'v', + 's', + 32, + 0, + /* 1725 */ 'f', + 'm', + 'o', + 'v', + 's', + 32, + 0, + /* 1732 */ 'l', + 'z', + 'c', + 'n', + 't', + 32, + 0, + /* 1739 */ 'p', + 'd', + 'i', + 's', + 't', + 32, + 0, + /* 1746 */ 'r', + 'e', + 't', + 't', + 32, + 0, + /* 1752 */ 'f', + 'm', + 'u', + 'l', + '8', + 'x', + '1', + '6', + 'a', + 'u', + 32, + 0, + /* 1764 */ 's', + 'd', + 'i', + 'v', + 32, + 0, + /* 1770 */ 'u', + 'd', + 'i', + 'v', + 32, + 0, + /* 1776 */ 't', + 's', + 'u', + 'b', + 'c', + 'c', + 't', + 'v', + 32, + 0, + /* 1786 */ 't', + 'a', + 'd', + 'd', + 'c', + 'c', + 't', + 'v', + 32, + 0, + /* 1796 */ 'm', + 'o', + 'v', + 's', + 't', + 'o', + 's', + 'w', + 32, + 0, + /* 1806 */ 'm', + 'o', + 'v', + 's', + 't', + 'o', + 'u', + 'w', + 32, + 0, + /* 1816 */ 's', + 'r', + 'a', + 'x', + 32, + 0, + /* 1822 */ 's', + 'u', + 'b', + 'x', + 32, + 0, + /* 1828 */ 'a', + 'd', + 'd', + 'x', + 32, + 0, + /* 1834 */ 'f', + 'p', + 'a', + 'c', + 'k', + 'f', + 'i', + 'x', + 32, + 0, + /* 1844 */ 's', + 'l', + 'l', + 'x', + 32, + 0, + /* 1850 */ 's', + 'r', + 'l', + 'x', + 32, + 0, + /* 1856 */ 'x', + 'm', + 'u', + 'l', + 'x', + 32, + 0, + /* 1863 */ 'f', + 'd', + 't', + 'o', + 'x', + 32, + 0, + /* 1870 */ 'm', + 'o', + 'v', + 'd', + 't', + 'o', + 'x', + 32, + 0, + /* 1879 */ 'f', + 'q', + 't', + 'o', + 'x', + 32, + 0, + /* 1886 */ 'f', + 's', + 't', + 'o', + 'x', + 32, + 0, + /* 1893 */ 's', + 't', + 'x', + 32, + 0, + /* 1898 */ 's', + 'd', + 'i', + 'v', + 'x', + 32, + 0, + /* 1905 */ 'u', + 'd', + 'i', + 'v', + 'x', + 32, + 0, + /* 1912 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'd', + 'z', + 32, + 0, + /* 1921 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'd', + 'g', + 'e', + 'z', + 32, + 0, + /* 1932 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'q', + 'g', + 'e', + 'z', + 32, + 0, + /* 1943 */ 'b', + 'r', + 'g', + 'e', + 'z', + 32, + 0, + /* 1950 */ 'm', + 'o', + 'v', + 'r', + 'g', + 'e', + 'z', + 32, + 0, + /* 1959 */ 'f', + 'm', + 'o', + 'v', + 'r', + 's', + 'g', + 'e', + 'z', + 32, + 0, + /* 1970 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'd', + 'l', + 'e', + 'z', + 32, + 0, + /* 1981 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'q', + 'l', + 'e', + 'z', + 32, + 0, + /* 1992 */ 'b', + 'r', + 'l', + 'e', + 'z', + 32, + 0, + /* 1999 */ 'm', + 'o', + 'v', + 'r', + 'l', + 'e', + 'z', + 32, + 0, + /* 2008 */ 'f', + 'm', + 'o', + 'v', + 'r', + 's', + 'l', + 'e', + 'z', + 32, + 0, + /* 2019 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'd', + 'g', + 'z', + 32, + 0, + /* 2029 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'q', + 'g', + 'z', + 32, + 0, + /* 2039 */ 'b', + 'r', + 'g', + 'z', + 32, + 0, + /* 2045 */ 'm', + 'o', + 'v', + 'r', + 'g', + 'z', + 32, + 0, + /* 2053 */ 'f', + 'm', + 'o', + 'v', + 'r', + 's', + 'g', + 'z', + 32, + 0, + /* 2063 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'd', + 'l', + 'z', + 32, + 0, + /* 2073 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'q', + 'l', + 'z', + 32, + 0, + /* 2083 */ 'b', + 'r', + 'l', + 'z', + 32, + 0, + /* 2089 */ 'm', + 'o', + 'v', + 'r', + 'l', + 'z', + 32, + 0, + /* 2097 */ 'f', + 'm', + 'o', + 'v', + 'r', + 's', + 'l', + 'z', + 32, + 0, + /* 2107 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'd', + 'n', + 'z', + 32, + 0, + /* 2117 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'q', + 'n', + 'z', + 32, + 0, + /* 2127 */ 'b', + 'r', + 'n', + 'z', + 32, + 0, + /* 2133 */ 'm', + 'o', + 'v', + 'r', + 'n', + 'z', + 32, + 0, + /* 2141 */ 'f', + 'm', + 'o', + 'v', + 'r', + 's', + 'n', + 'z', + 32, + 0, + /* 2151 */ 'f', + 'm', + 'o', + 'v', + 'r', + 'q', + 'z', + 32, + 0, + /* 2160 */ 'b', + 'r', + 'z', + 32, + 0, + /* 2165 */ 'm', + 'o', + 'v', + 'r', + 'z', + 32, + 0, + /* 2172 */ 'f', + 'm', + 'o', + 'v', + 'r', + 's', + 'z', + 32, + 0, + /* 2181 */ ';', + 32, + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'D', + 'F', + 'P', + '_', + 'F', + 'C', + 'C', + 32, + 'P', + 'S', + 'E', + 'U', + 'D', + 'O', + '!', + 0, + /* 2209 */ ';', + 32, + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'Q', + 'F', + 'P', + '_', + 'F', + 'C', + 'C', + 32, + 'P', + 'S', + 'E', + 'U', + 'D', + 'O', + '!', + 0, + /* 2237 */ ';', + 32, + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'F', + 'P', + '_', + 'F', + 'C', + 'C', + 32, + 'P', + 'S', + 'E', + 'U', + 'D', + 'O', + '!', + 0, + /* 2264 */ ';', + 32, + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'I', + 'n', + 't', + '_', + 'F', + 'C', + 'C', + 32, + 'P', + 'S', + 'E', + 'U', + 'D', + 'O', + '!', + 0, + /* 2292 */ ';', + 32, + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'D', + 'F', + 'P', + '_', + 'I', + 'C', + 'C', + 32, + 'P', + 'S', + 'E', + 'U', + 'D', + 'O', + '!', + 0, + /* 2320 */ ';', + 32, + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'Q', + 'F', + 'P', + '_', + 'I', + 'C', + 'C', + 32, + 'P', + 'S', + 'E', + 'U', + 'D', + 'O', + '!', + 0, + /* 2348 */ ';', + 32, + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'F', + 'P', + '_', + 'I', + 'C', + 'C', + 32, + 'P', + 'S', + 'E', + 'U', + 'D', + 'O', + '!', + 0, + /* 2375 */ ';', + 32, + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + '_', + 'I', + 'n', + 't', + '_', + 'I', + 'C', + 'C', + 32, + 'P', + 'S', + 'E', + 'U', + 'D', + 'O', + '!', + 0, + /* 2403 */ 'j', + 'm', + 'p', + 32, + '%', + 'i', + '7', + '+', + 0, + /* 2412 */ 'j', + 'm', + 'p', + 32, + '%', + 'o', + '7', + '+', + 0, + /* 2421 */ 't', + 'a', + 32, + '3', + 0, + /* 2426 */ 't', + 'a', + 32, + '5', + 0, + /* 2431 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'E', + 'N', + 'D', + 0, + /* 2444 */ 'B', + 'U', + 'N', + 'D', + 'L', + 'E', + 0, + /* 2451 */ 'D', + 'B', + 'G', + '_', + 'V', + 'A', + 'L', + 'U', + 'E', + 0, + /* 2461 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'S', + 'T', + 'A', + 'R', + 'T', + 0, + /* 2476 */ 'l', + 'd', + 's', + 'b', + 32, + '[', + 0, + /* 2483 */ 'l', + 'd', + 'u', + 'b', + 32, + '[', + 0, + /* 2490 */ 'l', + 'd', + 'd', + 32, + '[', + 0, + /* 2496 */ 'l', + 'd', + 32, + '[', + 0, + /* 2501 */ 'l', + 'd', + 's', + 'h', + 32, + '[', + 0, + /* 2508 */ 'l', + 'd', + 'u', + 'h', + 32, + '[', + 0, + /* 2515 */ 's', + 'w', + 'a', + 'p', + 32, + '[', + 0, + /* 2522 */ 'l', + 'd', + 'q', + 32, + '[', + 0, + /* 2528 */ 'c', + 'a', + 's', + 32, + '[', + 0, + /* 2534 */ 'l', + 'd', + 's', + 'w', + 32, + '[', + 0, + /* 2541 */ 'l', + 'd', + 'x', + 32, + '[', + 0, + /* 2547 */ 'c', + 'a', + 's', + 'x', + 32, + '[', + 0, + /* 2554 */ 'f', + 'b', + 0, + /* 2557 */ 'f', + 'm', + 'o', + 'v', + 'd', + 0, + /* 2563 */ 's', + 'i', + 'a', + 'm', + 0, + /* 2568 */ 's', + 'h', + 'u', + 't', + 'd', + 'o', + 'w', + 'n', + 0, + /* 2577 */ 'n', + 'o', + 'p', + 0, + /* 2581 */ 'f', + 'm', + 'o', + 'v', + 'q', + 0, + /* 2587 */ 's', + 't', + 'b', + 'a', + 'r', + 0, + /* 2593 */ 'f', + 'm', + 'o', + 'v', + 's', + 0, + /* 2599 */ 't', + 0, + /* 2601 */ 'm', + 'o', + 'v', + 0, + /* 2605 */ 'f', + 'l', + 'u', + 's', + 'h', + 'w', + 0, }; #endif @@ -830,88 +3133,86 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; #ifndef CAPSTONE_DIET // assert(Bits != 0 && "Cannot print this instruction."); - SStream_concat0(O, AsmStrs+(Bits & 4095)-1); + SStream_concat0(O, AsmStrs + (Bits & 4095) - 1); #endif - // Fragment 0 encoded into 4 bits for 12 unique commands. // printf("Frag-0: %u\n", (Bits >> 12) & 15); switch ((Bits >> 12) & 15) { - default: // unreachable. + default: // unreachable. case 0: // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C... return; break; case 1: // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... - printOperand(MI, 1, O); + printOperand(MI, 1, O); break; case 2: // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B... - printOperand(MI, 0, O); + printOperand(MI, 0, O); break; case 3: // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA... - printCCOperand(MI, 1, O); + printCCOperand(MI, 1, O); break; case 4: // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr - printMemOperand(MI, 0, O, NULL); + printMemOperand(MI, 0, O, NULL); return; break; case 5: // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV... - printCCOperand(MI, 3, O); + printCCOperand(MI, 3, O); break; case 6: // GETPCX - printGetPCX(MI, 0, O); + printGetPCX(MI, 0, O); return; break; case 7: // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ... - printMemOperand(MI, 1, O, NULL); + printMemOperand(MI, 1, O, NULL); break; case 8: // LEAX_ADDri, LEA_ADDri - printMemOperand(MI, 1, O, "arith"); - SStream_concat0(O, ", "); - printOperand(MI, 0, O); + printMemOperand(MI, 1, O, "arith"); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); return; break; case 9: // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF... - printOperand(MI, 2, O); - SStream_concat0(O, ", ["); - printMemOperand(MI, 0, O, NULL); - SStream_concat0(O, "]"); + printOperand(MI, 2, O); + SStream_concat0(O, ", ["); + printMemOperand(MI, 0, O, NULL); + SStream_concat0(O, "]"); return; break; case 10: // TICCri, TICCrr, TXCCri, TXCCrr - printCCOperand(MI, 2, O); + printCCOperand(MI, 2, O); break; case 11: // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr - printCCOperand(MI, 4, O); - SStream_concat0(O, " "); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); - SStream_concat0(O, ", "); - printOperand(MI, 0, O); + printCCOperand(MI, 4, O); + SStream_concat0(O, " "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); return; break; } - // Fragment 1 encoded into 4 bits for 16 unique commands. // printf("Frag-1: %u\n", (Bits >> 16) & 15); switch ((Bits >> 16) & 15) { - default: // unreachable. + default: // unreachable. case 0: // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 1: // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ... @@ -919,290 +3220,284 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) break; case 2: // BCOND, BPFCC, FBCOND - SStream_concat0(O, " "); + SStream_concat0(O, " "); break; case 3: // BCONDA, BPFCCA, FBCONDA SStream_concat0(O, ",a "); - Sparc_add_hint(MI, SPARC_HINT_A); + Sparc_add_hint(MI, SPARC_HINT_A); break; case 4: // BPFCCANT SStream_concat0(O, ",a,pn "); - Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); - printOperand(MI, 2, O); - SStream_concat0(O, ", "); - printOperand(MI, 0, O); + Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); return; break; case 5: // BPFCCNT SStream_concat0(O, ",pn "); - Sparc_add_hint(MI, SPARC_HINT_PN); - printOperand(MI, 2, O); - SStream_concat0(O, ", "); - printOperand(MI, 0, O); + Sparc_add_hint(MI, SPARC_HINT_PN); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); return; break; case 6: // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI... SStream_concat0(O, " %icc, "); - Sparc_add_reg(MI, SPARC_REG_ICC); + Sparc_add_reg(MI, SPARC_REG_ICC); break; case 7: // BPICCA SStream_concat0(O, ",a %icc, "); - Sparc_add_hint(MI, SPARC_HINT_A); - Sparc_add_reg(MI, SPARC_REG_ICC); - printOperand(MI, 0, O); + Sparc_add_hint(MI, SPARC_HINT_A); + Sparc_add_reg(MI, SPARC_REG_ICC); + printOperand(MI, 0, O); return; break; case 8: // BPICCANT SStream_concat0(O, ",a,pn %icc, "); - Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); - Sparc_add_reg(MI, SPARC_REG_ICC); - printOperand(MI, 0, O); + Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); + Sparc_add_reg(MI, SPARC_REG_ICC); + printOperand(MI, 0, O); return; break; case 9: // BPICCNT SStream_concat0(O, ",pn %icc, "); - Sparc_add_hint(MI, SPARC_HINT_PN); - Sparc_add_reg(MI, SPARC_REG_ICC); - printOperand(MI, 0, O); + Sparc_add_hint(MI, SPARC_HINT_PN); + Sparc_add_reg(MI, SPARC_REG_ICC); + printOperand(MI, 0, O); return; break; case 10: // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX... SStream_concat0(O, " %xcc, "); - Sparc_add_reg(MI, SPARC_REG_XCC); + Sparc_add_reg(MI, SPARC_REG_XCC); break; case 11: // BPXCCA SStream_concat0(O, ",a %xcc, "); - Sparc_add_hint(MI, SPARC_HINT_A); - Sparc_add_reg(MI, SPARC_REG_XCC); - printOperand(MI, 0, O); + Sparc_add_hint(MI, SPARC_HINT_A); + Sparc_add_reg(MI, SPARC_REG_XCC); + printOperand(MI, 0, O); return; break; case 12: // BPXCCANT SStream_concat0(O, ",a,pn %xcc, "); - Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); - Sparc_add_reg(MI, SPARC_REG_XCC); - printOperand(MI, 0, O); + Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); + Sparc_add_reg(MI, SPARC_REG_XCC); + printOperand(MI, 0, O); return; break; case 13: // BPXCCNT SStream_concat0(O, ",pn %xcc, "); - Sparc_add_hint(MI, SPARC_HINT_PN); - Sparc_add_reg(MI, SPARC_REG_XCC); - printOperand(MI, 0, O); + Sparc_add_hint(MI, SPARC_HINT_PN); + Sparc_add_reg(MI, SPARC_REG_XCC); + printOperand(MI, 0, O); return; break; case 14: // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L... - SStream_concat0(O, "], "); + SStream_concat0(O, "], "); break; case 15: // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr SStream_concat0(O, " %fcc0, "); - Sparc_add_reg(MI, SPARC_REG_FCC0); - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 0, O); + Sparc_add_reg(MI, SPARC_REG_FCC0); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); return; break; } - // Fragment 2 encoded into 2 bits for 3 unique commands. // printf("Frag-2: %u\n", (Bits >> 20) & 3); switch ((Bits >> 20) & 3) { - default: // unreachable. + default: // unreachable. case 0: // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... - printOperand(MI, 2, O); - SStream_concat0(O, ", "); - printOperand(MI, 0, O); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); break; case 1: // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT... - printOperand(MI, 0, O); + printOperand(MI, 0, O); break; case 2: // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ... - printOperand(MI, 1, O); + printOperand(MI, 1, O); break; } - // Fragment 3 encoded into 2 bits for 4 unique commands. // printf("Frag-3: %u\n", (Bits >> 22) & 3); switch ((Bits >> 22) & 3) { - default: // unreachable. + default: // unreachable. case 0: // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... return; break; case 1: // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 2: // TICCri, TICCrr, TXCCri, TXCCrr - SStream_concat0(O, " + "); // qq - printOperand(MI, 1, O); + SStream_concat0(O, " + "); // qq + printOperand(MI, 1, O); return; break; case 3: // WRYri, WRYrr SStream_concat0(O, ", %y"); - Sparc_add_reg(MI, SPARC_REG_Y); + Sparc_add_reg(MI, SPARC_REG_Y); return; break; } - // Fragment 4 encoded into 2 bits for 3 unique commands. // printf("Frag-4: %u\n", (Bits >> 24) & 3); switch ((Bits >> 24) & 3) { - default: // unreachable. + default: // unreachable. case 0: // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP... - printOperand(MI, 2, O); + printOperand(MI, 2, O); return; break; case 1: // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI... - printOperand(MI, 0, O); + printOperand(MI, 0, O); return; break; case 2: // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr - printOperand(MI, 3, O); + printOperand(MI, 3, O); return; break; } } - /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static const char *getRegisterName(unsigned RegNo) -{ +static const char *getRegisterName(unsigned RegNo) { // assert(RegNo && RegNo < 119 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'f', '1', '0', 0, - /* 4 */ 'f', '2', '0', 0, - /* 8 */ 'f', '3', '0', 0, - /* 12 */ 'f', '4', '0', 0, - /* 16 */ 'f', '5', '0', 0, - /* 20 */ 'f', '6', '0', 0, - /* 24 */ 'f', 'c', 'c', '0', 0, - /* 29 */ 'f', '0', 0, - /* 32 */ 'g', '0', 0, - /* 35 */ 'i', '0', 0, - /* 38 */ 'l', '0', 0, - /* 41 */ 'o', '0', 0, - /* 44 */ 'f', '1', '1', 0, - /* 48 */ 'f', '2', '1', 0, - /* 52 */ 'f', '3', '1', 0, - /* 56 */ 'f', 'c', 'c', '1', 0, - /* 61 */ 'f', '1', 0, - /* 64 */ 'g', '1', 0, - /* 67 */ 'i', '1', 0, - /* 70 */ 'l', '1', 0, - /* 73 */ 'o', '1', 0, - /* 76 */ 'f', '1', '2', 0, - /* 80 */ 'f', '2', '2', 0, - /* 84 */ 'f', '3', '2', 0, - /* 88 */ 'f', '4', '2', 0, - /* 92 */ 'f', '5', '2', 0, - /* 96 */ 'f', '6', '2', 0, - /* 100 */ 'f', 'c', 'c', '2', 0, - /* 105 */ 'f', '2', 0, - /* 108 */ 'g', '2', 0, - /* 111 */ 'i', '2', 0, - /* 114 */ 'l', '2', 0, - /* 117 */ 'o', '2', 0, - /* 120 */ 'f', '1', '3', 0, - /* 124 */ 'f', '2', '3', 0, - /* 128 */ 'f', 'c', 'c', '3', 0, - /* 133 */ 'f', '3', 0, - /* 136 */ 'g', '3', 0, - /* 139 */ 'i', '3', 0, - /* 142 */ 'l', '3', 0, - /* 145 */ 'o', '3', 0, - /* 148 */ 'f', '1', '4', 0, - /* 152 */ 'f', '2', '4', 0, - /* 156 */ 'f', '3', '4', 0, - /* 160 */ 'f', '4', '4', 0, - /* 164 */ 'f', '5', '4', 0, - /* 168 */ 'f', '4', 0, - /* 171 */ 'g', '4', 0, - /* 174 */ 'i', '4', 0, - /* 177 */ 'l', '4', 0, - /* 180 */ 'o', '4', 0, - /* 183 */ 'f', '1', '5', 0, - /* 187 */ 'f', '2', '5', 0, - /* 191 */ 'f', '5', 0, - /* 194 */ 'g', '5', 0, - /* 197 */ 'i', '5', 0, - /* 200 */ 'l', '5', 0, - /* 203 */ 'o', '5', 0, - /* 206 */ 'f', '1', '6', 0, - /* 210 */ 'f', '2', '6', 0, - /* 214 */ 'f', '3', '6', 0, - /* 218 */ 'f', '4', '6', 0, - /* 222 */ 'f', '5', '6', 0, - /* 226 */ 'f', '6', 0, - /* 229 */ 'g', '6', 0, - /* 232 */ 'l', '6', 0, - /* 235 */ 'f', '1', '7', 0, - /* 239 */ 'f', '2', '7', 0, - /* 243 */ 'f', '7', 0, - /* 246 */ 'g', '7', 0, - /* 249 */ 'i', '7', 0, - /* 252 */ 'l', '7', 0, - /* 255 */ 'o', '7', 0, - /* 258 */ 'f', '1', '8', 0, - /* 262 */ 'f', '2', '8', 0, - /* 266 */ 'f', '3', '8', 0, - /* 270 */ 'f', '4', '8', 0, - /* 274 */ 'f', '5', '8', 0, - /* 278 */ 'f', '8', 0, - /* 281 */ 'f', '1', '9', 0, - /* 285 */ 'f', '2', '9', 0, - /* 289 */ 'f', '9', 0, - /* 292 */ 'i', 'c', 'c', 0, - /* 296 */ 'f', 'p', 0, - /* 299 */ 's', 'p', 0, - /* 302 */ 'y', 0, + /* 0 */ 'f', '1', '0', 0, + /* 4 */ 'f', '2', '0', 0, + /* 8 */ 'f', '3', '0', 0, + /* 12 */ 'f', '4', '0', 0, + /* 16 */ 'f', '5', '0', 0, + /* 20 */ 'f', '6', '0', 0, + /* 24 */ 'f', 'c', 'c', '0', 0, + /* 29 */ 'f', '0', 0, + /* 32 */ 'g', '0', 0, + /* 35 */ 'i', '0', 0, + /* 38 */ 'l', '0', 0, + /* 41 */ 'o', '0', 0, + /* 44 */ 'f', '1', '1', 0, + /* 48 */ 'f', '2', '1', 0, + /* 52 */ 'f', '3', '1', 0, + /* 56 */ 'f', 'c', 'c', '1', 0, + /* 61 */ 'f', '1', 0, + /* 64 */ 'g', '1', 0, + /* 67 */ 'i', '1', 0, + /* 70 */ 'l', '1', 0, + /* 73 */ 'o', '1', 0, + /* 76 */ 'f', '1', '2', 0, + /* 80 */ 'f', '2', '2', 0, + /* 84 */ 'f', '3', '2', 0, + /* 88 */ 'f', '4', '2', 0, + /* 92 */ 'f', '5', '2', 0, + /* 96 */ 'f', '6', '2', 0, + /* 100 */ 'f', 'c', 'c', '2', 0, + /* 105 */ 'f', '2', 0, + /* 108 */ 'g', '2', 0, + /* 111 */ 'i', '2', 0, + /* 114 */ 'l', '2', 0, + /* 117 */ 'o', '2', 0, + /* 120 */ 'f', '1', '3', 0, + /* 124 */ 'f', '2', '3', 0, + /* 128 */ 'f', 'c', 'c', '3', 0, + /* 133 */ 'f', '3', 0, + /* 136 */ 'g', '3', 0, + /* 139 */ 'i', '3', 0, + /* 142 */ 'l', '3', 0, + /* 145 */ 'o', '3', 0, + /* 148 */ 'f', '1', '4', 0, + /* 152 */ 'f', '2', '4', 0, + /* 156 */ 'f', '3', '4', 0, + /* 160 */ 'f', '4', '4', 0, + /* 164 */ 'f', '5', '4', 0, + /* 168 */ 'f', '4', 0, + /* 171 */ 'g', '4', 0, + /* 174 */ 'i', '4', 0, + /* 177 */ 'l', '4', 0, + /* 180 */ 'o', '4', 0, + /* 183 */ 'f', '1', '5', 0, + /* 187 */ 'f', '2', '5', 0, + /* 191 */ 'f', '5', 0, + /* 194 */ 'g', '5', 0, + /* 197 */ 'i', '5', 0, + /* 200 */ 'l', '5', 0, + /* 203 */ 'o', '5', 0, + /* 206 */ 'f', '1', '6', 0, + /* 210 */ 'f', '2', '6', 0, + /* 214 */ 'f', '3', '6', 0, + /* 218 */ 'f', '4', '6', 0, + /* 222 */ 'f', '5', '6', 0, + /* 226 */ 'f', '6', 0, + /* 229 */ 'g', '6', 0, + /* 232 */ 'l', '6', 0, + /* 235 */ 'f', '1', '7', 0, + /* 239 */ 'f', '2', '7', 0, + /* 243 */ 'f', '7', 0, + /* 246 */ 'g', '7', 0, + /* 249 */ 'i', '7', 0, + /* 252 */ 'l', '7', 0, + /* 255 */ 'o', '7', 0, + /* 258 */ 'f', '1', '8', 0, + /* 262 */ 'f', '2', '8', 0, + /* 266 */ 'f', '3', '8', 0, + /* 270 */ 'f', '4', '8', 0, + /* 274 */ 'f', '5', '8', 0, + /* 278 */ 'f', '8', 0, + /* 281 */ 'f', '1', '9', 0, + /* 285 */ 'f', '2', '9', 0, + /* 289 */ 'f', '9', 0, + /* 292 */ 'i', 'c', 'c', 0, + /* 296 */ 'f', 'p', 0, + /* 299 */ 's', 'p', 0, + /* 302 */ 'y', 0, }; static const uint16_t RegAsmOffset[] = { - 292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, - 152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, - 92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, - 278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, - 80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, - 32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, - 296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, - 180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, - 12, 160, 270, 92, 222, 20, + 292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 152, + 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 92, 164, + 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 278, 289, 0, + 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 80, 124, 152, 187, + 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 32, 64, 108, 136, 171, + 194, 229, 246, 35, 67, 111, 139, 174, 197, 296, 249, 38, 70, 114, 142, + 177, 200, 232, 252, 41, 73, 117, 145, 180, 203, 299, 255, 29, 168, 278, + 76, 206, 4, 152, 262, 84, 214, 12, 160, 270, 92, 222, 20, }; - //int i; - //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) + // int i; + // for (i = 0; i < sizeof(RegAsmOffset)/2; i++) // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); - //printf("*************************\n"); - return AsmStrs+RegAsmOffset[RegNo-1]; + // printf("*************************\n"); + return AsmStrs + RegAsmOffset[RegNo - 1]; #else return NULL; #endif @@ -1212,19 +3507,19 @@ static const char *getRegisterName(unsigned RegNo) #undef PRINT_ALIAS_INSTR static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, SStream *OS) -{ -} + unsigned PrintMethodIdx, SStream *OS) {} -static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) -{ - #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) +static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) { +#define GETREGCLASS_CONTAIN(_class, _reg) \ + MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), \ + MCOperand_getReg(MCInst_getOperand(MI, _reg))) const char *AsmString; char *tmp, *AsmMnem, *AsmOps, *c; int OpIdx, PrintMethodIdx; MCRegisterInfo *MRI = (MCRegisterInfo *)info; switch (MCInst_getOpcode(MI)) { - default: return NULL; + default: + return NULL; case SP_BCOND: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && @@ -5673,7 +7968,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) tmp = cs_strdup(AsmString); AsmMnem = tmp; - for(AsmOps = tmp; *AsmOps; AsmOps++) { + for (AsmOps = tmp; *AsmOps; AsmOps++) { if (*AsmOps == ' ' || *AsmOps == '\t') { *AsmOps = '\0'; AsmOps++; diff --git a/arch/Sparc/SparcGenDisassemblerTables.inc b/arch/Sparc/SparcGenDisassemblerTables.inc index 8a69a13e0e..7fcfafbb38 100644 --- a/arch/Sparc/SparcGenDisassemblerTables.inc +++ b/arch/Sparc/SparcGenDisassemblerTables.inc @@ -1,2028 +1,19256 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * Sparc Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Phosphorus15 , Year 2021 */ +/* This generator is under https://github.com/rizinorg/llvm-capstone */ +/* Automatically generated file, do not edit! */ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#include "../../MCInst.h" #include "../../LEB128.h" +#include "../../MCInst.h" + +#define Sparc_DetectRoundChange 0ULL +#define Sparc_FeatureHardQuad 1ULL +#define Sparc_FeatureLeon 2ULL +#define Sparc_FeatureNoFMULS 3ULL +#define Sparc_FeatureNoFSMULD 4ULL +#define Sparc_FeaturePWRPSR 5ULL +#define Sparc_FeatureSoftFloat 6ULL +#define Sparc_FeatureSoftMulDiv 7ULL +#define Sparc_FeatureV8Deprecated 8ULL +#define Sparc_FeatureV9 9ULL +#define Sparc_FeatureVIS 10ULL +#define Sparc_FeatureVIS2 11ULL +#define Sparc_FeatureVIS3 12ULL +#define Sparc_FixAllFDIVSQRT 13ULL +#define Sparc_InsertNOPLoad 14ULL +#define Sparc_LeonCASA 15ULL +#define Sparc_LeonCycleCounter 16ULL +#define Sparc_UMACSMACSupport 17ULL +#define Sparc_UsePopc 18ULL +#ifdef MIPS_GET_DISASSEMBLER +#undef MIPS_GET_DISASSEMBLER // Helper function for extracting fields from encoded instructions. -#define FieldFromInstruction(fname, InsnType) \ -static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ -{ \ - InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ - fieldMask = (InsnType)(-1LL); \ - else \ - fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ - return (insn & fieldMask) >> startBit; \ -} +#define FieldFromInstruction(fname, InsnType) \ + static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ + } static const uint8_t DecoderTableSparc32[] = { -/* 0 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 3 */ MCD_OPC_FilterValue, 0, 13, 2, // Skip to: 532 -/* 7 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... -/* 10 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 24 -/* 14 */ MCD_OPC_CheckField, 25, 5, 0, 163, 22, // Skip to: 5815 -/* 20 */ MCD_OPC_Decode, 211, 3, 0, // Opcode: UNIMP -/* 24 */ MCD_OPC_FilterValue, 1, 103, 0, // Skip to: 131 -/* 28 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... -/* 31 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 60 -/* 35 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 38 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 49 -/* 42 */ MCD_OPC_CheckPredicate, 0, 137, 22, // Skip to: 5815 -/* 46 */ MCD_OPC_Decode, 94, 1, // Opcode: BPICCNT -/* 49 */ MCD_OPC_FilterValue, 1, 130, 22, // Skip to: 5815 -/* 53 */ MCD_OPC_CheckPredicate, 0, 126, 22, // Skip to: 5815 -/* 57 */ MCD_OPC_Decode, 93, 1, // Opcode: BPICCANT -/* 60 */ MCD_OPC_FilterValue, 1, 25, 0, // Skip to: 89 -/* 64 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 67 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 78 -/* 71 */ MCD_OPC_CheckPredicate, 0, 108, 22, // Skip to: 5815 -/* 75 */ MCD_OPC_Decode, 91, 1, // Opcode: BPICC -/* 78 */ MCD_OPC_FilterValue, 1, 101, 22, // Skip to: 5815 -/* 82 */ MCD_OPC_CheckPredicate, 0, 97, 22, // Skip to: 5815 -/* 86 */ MCD_OPC_Decode, 92, 1, // Opcode: BPICCA -/* 89 */ MCD_OPC_FilterValue, 4, 17, 0, // Skip to: 110 -/* 93 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 96 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 103 -/* 100 */ MCD_OPC_Decode, 110, 1, // Opcode: BPXCCNT -/* 103 */ MCD_OPC_FilterValue, 1, 76, 22, // Skip to: 5815 -/* 107 */ MCD_OPC_Decode, 109, 1, // Opcode: BPXCCANT -/* 110 */ MCD_OPC_FilterValue, 5, 69, 22, // Skip to: 5815 -/* 114 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 117 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 124 -/* 121 */ MCD_OPC_Decode, 107, 1, // Opcode: BPXCC -/* 124 */ MCD_OPC_FilterValue, 1, 55, 22, // Skip to: 5815 -/* 128 */ MCD_OPC_Decode, 108, 1, // Opcode: BPXCCA -/* 131 */ MCD_OPC_FilterValue, 2, 26, 0, // Skip to: 161 -/* 135 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 138 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 154 -/* 142 */ MCD_OPC_CheckField, 25, 4, 8, 3, 0, // Skip to: 151 -/* 148 */ MCD_OPC_Decode, 73, 0, // Opcode: BA -/* 151 */ MCD_OPC_Decode, 74, 2, // Opcode: BCOND -/* 154 */ MCD_OPC_FilterValue, 1, 25, 22, // Skip to: 5815 -/* 158 */ MCD_OPC_Decode, 75, 2, // Opcode: BCONDA -/* 161 */ MCD_OPC_FilterValue, 3, 255, 0, // Skip to: 420 -/* 165 */ MCD_OPC_ExtractField, 25, 5, // Inst{29-25} ... -/* 168 */ MCD_OPC_FilterValue, 1, 17, 0, // Skip to: 189 -/* 172 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 175 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 182 -/* 179 */ MCD_OPC_Decode, 113, 3, // Opcode: BPZnapn -/* 182 */ MCD_OPC_FilterValue, 1, 253, 21, // Skip to: 5815 -/* 186 */ MCD_OPC_Decode, 114, 3, // Opcode: BPZnapt -/* 189 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 210 -/* 193 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 196 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 203 -/* 200 */ MCD_OPC_Decode, 97, 3, // Opcode: BPLEZnapn -/* 203 */ MCD_OPC_FilterValue, 1, 232, 21, // Skip to: 5815 -/* 207 */ MCD_OPC_Decode, 98, 3, // Opcode: BPLEZnapt -/* 210 */ MCD_OPC_FilterValue, 3, 17, 0, // Skip to: 231 -/* 214 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 217 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 224 -/* 221 */ MCD_OPC_Decode, 101, 3, // Opcode: BPLZnapn -/* 224 */ MCD_OPC_FilterValue, 1, 211, 21, // Skip to: 5815 -/* 228 */ MCD_OPC_Decode, 102, 3, // Opcode: BPLZnapt -/* 231 */ MCD_OPC_FilterValue, 5, 17, 0, // Skip to: 252 -/* 235 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 238 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 245 -/* 242 */ MCD_OPC_Decode, 105, 3, // Opcode: BPNZnapn -/* 245 */ MCD_OPC_FilterValue, 1, 190, 21, // Skip to: 5815 -/* 249 */ MCD_OPC_Decode, 106, 3, // Opcode: BPNZnapt -/* 252 */ MCD_OPC_FilterValue, 6, 17, 0, // Skip to: 273 -/* 256 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 259 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 266 -/* 263 */ MCD_OPC_Decode, 89, 3, // Opcode: BPGZnapn -/* 266 */ MCD_OPC_FilterValue, 1, 169, 21, // Skip to: 5815 -/* 270 */ MCD_OPC_Decode, 90, 3, // Opcode: BPGZnapt -/* 273 */ MCD_OPC_FilterValue, 7, 17, 0, // Skip to: 294 -/* 277 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 280 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 287 -/* 284 */ MCD_OPC_Decode, 85, 3, // Opcode: BPGEZnapn -/* 287 */ MCD_OPC_FilterValue, 1, 148, 21, // Skip to: 5815 -/* 291 */ MCD_OPC_Decode, 86, 3, // Opcode: BPGEZnapt -/* 294 */ MCD_OPC_FilterValue, 17, 17, 0, // Skip to: 315 -/* 298 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 301 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 308 -/* 305 */ MCD_OPC_Decode, 111, 3, // Opcode: BPZapn -/* 308 */ MCD_OPC_FilterValue, 1, 127, 21, // Skip to: 5815 -/* 312 */ MCD_OPC_Decode, 112, 3, // Opcode: BPZapt -/* 315 */ MCD_OPC_FilterValue, 18, 17, 0, // Skip to: 336 -/* 319 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 322 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 329 -/* 326 */ MCD_OPC_Decode, 95, 3, // Opcode: BPLEZapn -/* 329 */ MCD_OPC_FilterValue, 1, 106, 21, // Skip to: 5815 -/* 333 */ MCD_OPC_Decode, 96, 3, // Opcode: BPLEZapt -/* 336 */ MCD_OPC_FilterValue, 19, 17, 0, // Skip to: 357 -/* 340 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 343 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 350 -/* 347 */ MCD_OPC_Decode, 99, 3, // Opcode: BPLZapn -/* 350 */ MCD_OPC_FilterValue, 1, 85, 21, // Skip to: 5815 -/* 354 */ MCD_OPC_Decode, 100, 3, // Opcode: BPLZapt -/* 357 */ MCD_OPC_FilterValue, 21, 17, 0, // Skip to: 378 -/* 361 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 364 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 371 -/* 368 */ MCD_OPC_Decode, 103, 3, // Opcode: BPNZapn -/* 371 */ MCD_OPC_FilterValue, 1, 64, 21, // Skip to: 5815 -/* 375 */ MCD_OPC_Decode, 104, 3, // Opcode: BPNZapt -/* 378 */ MCD_OPC_FilterValue, 22, 17, 0, // Skip to: 399 -/* 382 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 385 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 392 -/* 389 */ MCD_OPC_Decode, 87, 3, // Opcode: BPGZapn -/* 392 */ MCD_OPC_FilterValue, 1, 43, 21, // Skip to: 5815 -/* 396 */ MCD_OPC_Decode, 88, 3, // Opcode: BPGZapt -/* 399 */ MCD_OPC_FilterValue, 23, 36, 21, // Skip to: 5815 -/* 403 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 406 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 413 -/* 410 */ MCD_OPC_Decode, 83, 3, // Opcode: BPGEZapn -/* 413 */ MCD_OPC_FilterValue, 1, 22, 21, // Skip to: 5815 -/* 417 */ MCD_OPC_Decode, 84, 3, // Opcode: BPGEZapt -/* 420 */ MCD_OPC_FilterValue, 4, 20, 0, // Skip to: 444 -/* 424 */ MCD_OPC_CheckField, 25, 5, 0, 10, 0, // Skip to: 440 -/* 430 */ MCD_OPC_CheckField, 0, 22, 0, 4, 0, // Skip to: 440 -/* 436 */ MCD_OPC_Decode, 224, 2, 4, // Opcode: NOP -/* 440 */ MCD_OPC_Decode, 135, 3, 5, // Opcode: SETHIi -/* 444 */ MCD_OPC_FilterValue, 5, 61, 0, // Skip to: 509 -/* 448 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 451 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 480 -/* 455 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 458 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 469 -/* 462 */ MCD_OPC_CheckPredicate, 0, 229, 20, // Skip to: 5815 -/* 466 */ MCD_OPC_Decode, 82, 6, // Opcode: BPFCCNT -/* 469 */ MCD_OPC_FilterValue, 1, 222, 20, // Skip to: 5815 -/* 473 */ MCD_OPC_CheckPredicate, 0, 218, 20, // Skip to: 5815 -/* 477 */ MCD_OPC_Decode, 81, 6, // Opcode: BPFCCANT -/* 480 */ MCD_OPC_FilterValue, 1, 211, 20, // Skip to: 5815 -/* 484 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 487 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 498 -/* 491 */ MCD_OPC_CheckPredicate, 0, 200, 20, // Skip to: 5815 -/* 495 */ MCD_OPC_Decode, 79, 6, // Opcode: BPFCC -/* 498 */ MCD_OPC_FilterValue, 1, 193, 20, // Skip to: 5815 -/* 502 */ MCD_OPC_CheckPredicate, 0, 189, 20, // Skip to: 5815 -/* 506 */ MCD_OPC_Decode, 80, 6, // Opcode: BPFCCA -/* 509 */ MCD_OPC_FilterValue, 6, 182, 20, // Skip to: 5815 -/* 513 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 516 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 524 -/* 520 */ MCD_OPC_Decode, 151, 1, 2, // Opcode: FBCOND -/* 524 */ MCD_OPC_FilterValue, 1, 167, 20, // Skip to: 5815 -/* 528 */ MCD_OPC_Decode, 152, 1, 2, // Opcode: FBCONDA -/* 532 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 539 -/* 536 */ MCD_OPC_Decode, 116, 7, // Opcode: CALL -/* 539 */ MCD_OPC_FilterValue, 2, 87, 18, // Skip to: 5238 -/* 543 */ MCD_OPC_ExtractField, 19, 6, // Inst{24-19} ... -/* 546 */ MCD_OPC_FilterValue, 0, 23, 0, // Skip to: 573 -/* 550 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 553 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 566 -/* 557 */ MCD_OPC_CheckField, 5, 8, 0, 132, 20, // Skip to: 5815 -/* 563 */ MCD_OPC_Decode, 33, 8, // Opcode: ADDrr -/* 566 */ MCD_OPC_FilterValue, 1, 125, 20, // Skip to: 5815 -/* 570 */ MCD_OPC_Decode, 32, 9, // Opcode: ADDri -/* 573 */ MCD_OPC_FilterValue, 1, 23, 0, // Skip to: 600 -/* 577 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 580 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 593 -/* 584 */ MCD_OPC_CheckField, 5, 8, 0, 105, 20, // Skip to: 5815 -/* 590 */ MCD_OPC_Decode, 48, 8, // Opcode: ANDrr -/* 593 */ MCD_OPC_FilterValue, 1, 98, 20, // Skip to: 5815 -/* 597 */ MCD_OPC_Decode, 47, 9, // Opcode: ANDri -/* 600 */ MCD_OPC_FilterValue, 2, 25, 0, // Skip to: 629 -/* 604 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 607 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 621 -/* 611 */ MCD_OPC_CheckField, 5, 8, 0, 78, 20, // Skip to: 5815 -/* 617 */ MCD_OPC_Decode, 235, 2, 8, // Opcode: ORrr -/* 621 */ MCD_OPC_FilterValue, 1, 70, 20, // Skip to: 5815 -/* 625 */ MCD_OPC_Decode, 234, 2, 9, // Opcode: ORri -/* 629 */ MCD_OPC_FilterValue, 3, 25, 0, // Skip to: 658 -/* 633 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 636 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 650 -/* 640 */ MCD_OPC_CheckField, 5, 8, 0, 49, 20, // Skip to: 5815 -/* 646 */ MCD_OPC_Decode, 237, 3, 8, // Opcode: XORrr -/* 650 */ MCD_OPC_FilterValue, 1, 41, 20, // Skip to: 5815 -/* 654 */ MCD_OPC_Decode, 236, 3, 9, // Opcode: XORri -/* 658 */ MCD_OPC_FilterValue, 4, 25, 0, // Skip to: 687 -/* 662 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 665 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 679 -/* 669 */ MCD_OPC_CheckField, 5, 8, 0, 20, 20, // Skip to: 5815 -/* 675 */ MCD_OPC_Decode, 178, 3, 8, // Opcode: SUBrr -/* 679 */ MCD_OPC_FilterValue, 1, 12, 20, // Skip to: 5815 -/* 683 */ MCD_OPC_Decode, 177, 3, 9, // Opcode: SUBri -/* 687 */ MCD_OPC_FilterValue, 5, 23, 0, // Skip to: 714 -/* 691 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 694 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 707 -/* 698 */ MCD_OPC_CheckField, 5, 8, 0, 247, 19, // Skip to: 5815 -/* 704 */ MCD_OPC_Decode, 43, 8, // Opcode: ANDNrr -/* 707 */ MCD_OPC_FilterValue, 1, 240, 19, // Skip to: 5815 -/* 711 */ MCD_OPC_Decode, 42, 9, // Opcode: ANDNri -/* 714 */ MCD_OPC_FilterValue, 6, 25, 0, // Skip to: 743 -/* 718 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 721 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 735 -/* 725 */ MCD_OPC_CheckField, 5, 8, 0, 220, 19, // Skip to: 5815 -/* 731 */ MCD_OPC_Decode, 230, 2, 8, // Opcode: ORNrr -/* 735 */ MCD_OPC_FilterValue, 1, 212, 19, // Skip to: 5815 -/* 739 */ MCD_OPC_Decode, 229, 2, 9, // Opcode: ORNri -/* 743 */ MCD_OPC_FilterValue, 7, 25, 0, // Skip to: 772 -/* 747 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 750 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 764 -/* 754 */ MCD_OPC_CheckField, 5, 8, 0, 191, 19, // Skip to: 5815 -/* 760 */ MCD_OPC_Decode, 231, 3, 8, // Opcode: XNORrr -/* 764 */ MCD_OPC_FilterValue, 1, 183, 19, // Skip to: 5815 -/* 768 */ MCD_OPC_Decode, 230, 3, 9, // Opcode: XNORri -/* 772 */ MCD_OPC_FilterValue, 8, 23, 0, // Skip to: 799 -/* 776 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 779 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 792 -/* 783 */ MCD_OPC_CheckField, 5, 8, 0, 162, 19, // Skip to: 5815 -/* 789 */ MCD_OPC_Decode, 25, 8, // Opcode: ADDCrr -/* 792 */ MCD_OPC_FilterValue, 1, 155, 19, // Skip to: 5815 -/* 796 */ MCD_OPC_Decode, 24, 9, // Opcode: ADDCri -/* 799 */ MCD_OPC_FilterValue, 9, 25, 0, // Skip to: 828 -/* 803 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 806 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 820 -/* 810 */ MCD_OPC_CheckField, 5, 8, 0, 135, 19, // Skip to: 5815 -/* 816 */ MCD_OPC_Decode, 223, 2, 10, // Opcode: MULXrr -/* 820 */ MCD_OPC_FilterValue, 1, 127, 19, // Skip to: 5815 -/* 824 */ MCD_OPC_Decode, 222, 2, 11, // Opcode: MULXri -/* 828 */ MCD_OPC_FilterValue, 10, 25, 0, // Skip to: 857 -/* 832 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 835 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 849 -/* 839 */ MCD_OPC_CheckField, 5, 8, 0, 106, 19, // Skip to: 5815 -/* 845 */ MCD_OPC_Decode, 210, 3, 8, // Opcode: UMULrr -/* 849 */ MCD_OPC_FilterValue, 1, 98, 19, // Skip to: 5815 -/* 853 */ MCD_OPC_Decode, 209, 3, 9, // Opcode: UMULri -/* 857 */ MCD_OPC_FilterValue, 11, 25, 0, // Skip to: 886 -/* 861 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 864 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 878 -/* 868 */ MCD_OPC_CheckField, 5, 8, 0, 77, 19, // Skip to: 5815 -/* 874 */ MCD_OPC_Decode, 145, 3, 8, // Opcode: SMULrr -/* 878 */ MCD_OPC_FilterValue, 1, 69, 19, // Skip to: 5815 -/* 882 */ MCD_OPC_Decode, 144, 3, 9, // Opcode: SMULri -/* 886 */ MCD_OPC_FilterValue, 12, 25, 0, // Skip to: 915 -/* 890 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 893 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 907 -/* 897 */ MCD_OPC_CheckField, 5, 8, 0, 48, 19, // Skip to: 5815 -/* 903 */ MCD_OPC_Decode, 172, 3, 8, // Opcode: SUBCrr -/* 907 */ MCD_OPC_FilterValue, 1, 40, 19, // Skip to: 5815 -/* 911 */ MCD_OPC_Decode, 171, 3, 9, // Opcode: SUBCri -/* 915 */ MCD_OPC_FilterValue, 13, 25, 0, // Skip to: 944 -/* 919 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 922 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 936 -/* 926 */ MCD_OPC_CheckField, 5, 8, 0, 19, 19, // Skip to: 5815 -/* 932 */ MCD_OPC_Decode, 203, 3, 10, // Opcode: UDIVXrr -/* 936 */ MCD_OPC_FilterValue, 1, 11, 19, // Skip to: 5815 -/* 940 */ MCD_OPC_Decode, 202, 3, 11, // Opcode: UDIVXri -/* 944 */ MCD_OPC_FilterValue, 14, 25, 0, // Skip to: 973 -/* 948 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 951 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 965 -/* 955 */ MCD_OPC_CheckField, 5, 8, 0, 246, 18, // Skip to: 5815 -/* 961 */ MCD_OPC_Decode, 205, 3, 8, // Opcode: UDIVrr -/* 965 */ MCD_OPC_FilterValue, 1, 238, 18, // Skip to: 5815 -/* 969 */ MCD_OPC_Decode, 204, 3, 9, // Opcode: UDIVri -/* 973 */ MCD_OPC_FilterValue, 15, 25, 0, // Skip to: 1002 -/* 977 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 980 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 994 -/* 984 */ MCD_OPC_CheckField, 5, 8, 0, 217, 18, // Skip to: 5815 -/* 990 */ MCD_OPC_Decode, 253, 2, 8, // Opcode: SDIVrr -/* 994 */ MCD_OPC_FilterValue, 1, 209, 18, // Skip to: 5815 -/* 998 */ MCD_OPC_Decode, 252, 2, 9, // Opcode: SDIVri -/* 1002 */ MCD_OPC_FilterValue, 16, 23, 0, // Skip to: 1029 -/* 1006 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1009 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1022 -/* 1013 */ MCD_OPC_CheckField, 5, 8, 0, 188, 18, // Skip to: 5815 -/* 1019 */ MCD_OPC_Decode, 23, 8, // Opcode: ADDCCrr -/* 1022 */ MCD_OPC_FilterValue, 1, 181, 18, // Skip to: 5815 -/* 1026 */ MCD_OPC_Decode, 22, 9, // Opcode: ADDCCri -/* 1029 */ MCD_OPC_FilterValue, 17, 23, 0, // Skip to: 1056 -/* 1033 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1036 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1049 -/* 1040 */ MCD_OPC_CheckField, 5, 8, 0, 161, 18, // Skip to: 5815 -/* 1046 */ MCD_OPC_Decode, 39, 8, // Opcode: ANDCCrr -/* 1049 */ MCD_OPC_FilterValue, 1, 154, 18, // Skip to: 5815 -/* 1053 */ MCD_OPC_Decode, 38, 9, // Opcode: ANDCCri -/* 1056 */ MCD_OPC_FilterValue, 18, 25, 0, // Skip to: 1085 -/* 1060 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1063 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1077 -/* 1067 */ MCD_OPC_CheckField, 5, 8, 0, 134, 18, // Skip to: 5815 -/* 1073 */ MCD_OPC_Decode, 226, 2, 8, // Opcode: ORCCrr -/* 1077 */ MCD_OPC_FilterValue, 1, 126, 18, // Skip to: 5815 -/* 1081 */ MCD_OPC_Decode, 225, 2, 9, // Opcode: ORCCri -/* 1085 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 1114 -/* 1089 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1092 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1106 -/* 1096 */ MCD_OPC_CheckField, 5, 8, 0, 105, 18, // Skip to: 5815 -/* 1102 */ MCD_OPC_Decode, 233, 3, 8, // Opcode: XORCCrr -/* 1106 */ MCD_OPC_FilterValue, 1, 97, 18, // Skip to: 5815 -/* 1110 */ MCD_OPC_Decode, 232, 3, 9, // Opcode: XORCCri -/* 1114 */ MCD_OPC_FilterValue, 20, 44, 0, // Skip to: 1162 -/* 1118 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1121 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1145 -/* 1125 */ MCD_OPC_ExtractField, 5, 8, // Inst{12-5} ... -/* 1128 */ MCD_OPC_FilterValue, 0, 75, 18, // Skip to: 5815 -/* 1132 */ MCD_OPC_CheckField, 25, 5, 0, 3, 0, // Skip to: 1141 -/* 1138 */ MCD_OPC_Decode, 125, 12, // Opcode: CMPrr -/* 1141 */ MCD_OPC_Decode, 170, 3, 8, // Opcode: SUBCCrr -/* 1145 */ MCD_OPC_FilterValue, 1, 58, 18, // Skip to: 5815 -/* 1149 */ MCD_OPC_CheckField, 25, 5, 0, 3, 0, // Skip to: 1158 -/* 1155 */ MCD_OPC_Decode, 124, 13, // Opcode: CMPri -/* 1158 */ MCD_OPC_Decode, 169, 3, 9, // Opcode: SUBCCri -/* 1162 */ MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1189 -/* 1166 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1169 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1182 -/* 1173 */ MCD_OPC_CheckField, 5, 8, 0, 28, 18, // Skip to: 5815 -/* 1179 */ MCD_OPC_Decode, 41, 8, // Opcode: ANDNCCrr -/* 1182 */ MCD_OPC_FilterValue, 1, 21, 18, // Skip to: 5815 -/* 1186 */ MCD_OPC_Decode, 40, 9, // Opcode: ANDNCCri -/* 1189 */ MCD_OPC_FilterValue, 22, 25, 0, // Skip to: 1218 -/* 1193 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1196 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1210 -/* 1200 */ MCD_OPC_CheckField, 5, 8, 0, 1, 18, // Skip to: 5815 -/* 1206 */ MCD_OPC_Decode, 228, 2, 8, // Opcode: ORNCCrr -/* 1210 */ MCD_OPC_FilterValue, 1, 249, 17, // Skip to: 5815 -/* 1214 */ MCD_OPC_Decode, 227, 2, 9, // Opcode: ORNCCri -/* 1218 */ MCD_OPC_FilterValue, 23, 25, 0, // Skip to: 1247 -/* 1222 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1225 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1239 -/* 1229 */ MCD_OPC_CheckField, 5, 8, 0, 228, 17, // Skip to: 5815 -/* 1235 */ MCD_OPC_Decode, 228, 3, 8, // Opcode: XNORCCrr -/* 1239 */ MCD_OPC_FilterValue, 1, 220, 17, // Skip to: 5815 -/* 1243 */ MCD_OPC_Decode, 227, 3, 9, // Opcode: XNORCCri -/* 1247 */ MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1274 -/* 1251 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1254 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1267 -/* 1258 */ MCD_OPC_CheckField, 5, 8, 0, 199, 17, // Skip to: 5815 -/* 1264 */ MCD_OPC_Decode, 27, 8, // Opcode: ADDErr -/* 1267 */ MCD_OPC_FilterValue, 1, 192, 17, // Skip to: 5815 -/* 1271 */ MCD_OPC_Decode, 26, 9, // Opcode: ADDEri -/* 1274 */ MCD_OPC_FilterValue, 26, 25, 0, // Skip to: 1303 -/* 1278 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1281 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1295 -/* 1285 */ MCD_OPC_CheckField, 5, 8, 0, 172, 17, // Skip to: 5815 -/* 1291 */ MCD_OPC_Decode, 207, 3, 8, // Opcode: UMULCCrr -/* 1295 */ MCD_OPC_FilterValue, 1, 164, 17, // Skip to: 5815 -/* 1299 */ MCD_OPC_Decode, 206, 3, 9, // Opcode: UMULCCri -/* 1303 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 1332 -/* 1307 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1310 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1324 -/* 1314 */ MCD_OPC_CheckField, 5, 8, 0, 143, 17, // Skip to: 5815 -/* 1320 */ MCD_OPC_Decode, 143, 3, 8, // Opcode: SMULCCrr -/* 1324 */ MCD_OPC_FilterValue, 1, 135, 17, // Skip to: 5815 -/* 1328 */ MCD_OPC_Decode, 142, 3, 9, // Opcode: SMULCCri -/* 1332 */ MCD_OPC_FilterValue, 28, 25, 0, // Skip to: 1361 -/* 1336 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1339 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1353 -/* 1343 */ MCD_OPC_CheckField, 5, 8, 0, 114, 17, // Skip to: 5815 -/* 1349 */ MCD_OPC_Decode, 174, 3, 8, // Opcode: SUBErr -/* 1353 */ MCD_OPC_FilterValue, 1, 106, 17, // Skip to: 5815 -/* 1357 */ MCD_OPC_Decode, 173, 3, 9, // Opcode: SUBEri -/* 1361 */ MCD_OPC_FilterValue, 30, 25, 0, // Skip to: 1390 -/* 1365 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1368 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1382 -/* 1372 */ MCD_OPC_CheckField, 5, 8, 0, 85, 17, // Skip to: 5815 -/* 1378 */ MCD_OPC_Decode, 201, 3, 8, // Opcode: UDIVCCrr -/* 1382 */ MCD_OPC_FilterValue, 1, 77, 17, // Skip to: 5815 -/* 1386 */ MCD_OPC_Decode, 200, 3, 9, // Opcode: UDIVCCri -/* 1390 */ MCD_OPC_FilterValue, 31, 25, 0, // Skip to: 1419 -/* 1394 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1397 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1411 -/* 1401 */ MCD_OPC_CheckField, 5, 8, 0, 56, 17, // Skip to: 5815 -/* 1407 */ MCD_OPC_Decode, 249, 2, 8, // Opcode: SDIVCCrr -/* 1411 */ MCD_OPC_FilterValue, 1, 48, 17, // Skip to: 5815 -/* 1415 */ MCD_OPC_Decode, 248, 2, 9, // Opcode: SDIVCCri -/* 1419 */ MCD_OPC_FilterValue, 32, 25, 0, // Skip to: 1448 -/* 1423 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1426 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1440 -/* 1430 */ MCD_OPC_CheckField, 5, 8, 0, 27, 17, // Skip to: 5815 -/* 1436 */ MCD_OPC_Decode, 186, 3, 8, // Opcode: TADDCCrr -/* 1440 */ MCD_OPC_FilterValue, 1, 19, 17, // Skip to: 5815 -/* 1444 */ MCD_OPC_Decode, 185, 3, 9, // Opcode: TADDCCri -/* 1448 */ MCD_OPC_FilterValue, 33, 25, 0, // Skip to: 1477 -/* 1452 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1455 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1469 -/* 1459 */ MCD_OPC_CheckField, 5, 8, 0, 254, 16, // Skip to: 5815 -/* 1465 */ MCD_OPC_Decode, 197, 3, 8, // Opcode: TSUBCCrr -/* 1469 */ MCD_OPC_FilterValue, 1, 246, 16, // Skip to: 5815 -/* 1473 */ MCD_OPC_Decode, 196, 3, 9, // Opcode: TSUBCCri -/* 1477 */ MCD_OPC_FilterValue, 34, 25, 0, // Skip to: 1506 -/* 1481 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1498 -/* 1488 */ MCD_OPC_CheckField, 5, 8, 0, 225, 16, // Skip to: 5815 -/* 1494 */ MCD_OPC_Decode, 184, 3, 8, // Opcode: TADDCCTVrr -/* 1498 */ MCD_OPC_FilterValue, 1, 217, 16, // Skip to: 5815 -/* 1502 */ MCD_OPC_Decode, 183, 3, 9, // Opcode: TADDCCTVri -/* 1506 */ MCD_OPC_FilterValue, 35, 25, 0, // Skip to: 1535 -/* 1510 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1513 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1527 -/* 1517 */ MCD_OPC_CheckField, 5, 8, 0, 196, 16, // Skip to: 5815 -/* 1523 */ MCD_OPC_Decode, 195, 3, 8, // Opcode: TSUBCCTVrr -/* 1527 */ MCD_OPC_FilterValue, 1, 188, 16, // Skip to: 5815 -/* 1531 */ MCD_OPC_Decode, 194, 3, 9, // Opcode: TSUBCCTVri -/* 1535 */ MCD_OPC_FilterValue, 37, 50, 0, // Skip to: 1589 -/* 1539 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1542 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1571 -/* 1546 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 1549 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1563 -/* 1553 */ MCD_OPC_CheckField, 5, 7, 0, 160, 16, // Skip to: 5815 -/* 1559 */ MCD_OPC_Decode, 141, 3, 8, // Opcode: SLLrr -/* 1563 */ MCD_OPC_FilterValue, 1, 152, 16, // Skip to: 5815 -/* 1567 */ MCD_OPC_Decode, 139, 3, 14, // Opcode: SLLXrr -/* 1571 */ MCD_OPC_FilterValue, 1, 144, 16, // Skip to: 5815 -/* 1575 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1585 -/* 1581 */ MCD_OPC_Decode, 138, 3, 15, // Opcode: SLLXri -/* 1585 */ MCD_OPC_Decode, 140, 3, 9, // Opcode: SLLri -/* 1589 */ MCD_OPC_FilterValue, 38, 50, 0, // Skip to: 1643 -/* 1593 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1596 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1625 -/* 1600 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 1603 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1617 -/* 1607 */ MCD_OPC_CheckField, 5, 7, 0, 106, 16, // Skip to: 5815 -/* 1613 */ MCD_OPC_Decode, 153, 3, 8, // Opcode: SRLrr -/* 1617 */ MCD_OPC_FilterValue, 1, 98, 16, // Skip to: 5815 -/* 1621 */ MCD_OPC_Decode, 151, 3, 14, // Opcode: SRLXrr -/* 1625 */ MCD_OPC_FilterValue, 1, 90, 16, // Skip to: 5815 -/* 1629 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1639 -/* 1635 */ MCD_OPC_Decode, 150, 3, 15, // Opcode: SRLXri -/* 1639 */ MCD_OPC_Decode, 152, 3, 9, // Opcode: SRLri -/* 1643 */ MCD_OPC_FilterValue, 39, 50, 0, // Skip to: 1697 -/* 1647 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1650 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1679 -/* 1654 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 1657 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1671 -/* 1661 */ MCD_OPC_CheckField, 5, 7, 0, 52, 16, // Skip to: 5815 -/* 1667 */ MCD_OPC_Decode, 149, 3, 8, // Opcode: SRArr -/* 1671 */ MCD_OPC_FilterValue, 1, 44, 16, // Skip to: 5815 -/* 1675 */ MCD_OPC_Decode, 147, 3, 14, // Opcode: SRAXrr -/* 1679 */ MCD_OPC_FilterValue, 1, 36, 16, // Skip to: 5815 -/* 1683 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1693 -/* 1689 */ MCD_OPC_Decode, 146, 3, 15, // Opcode: SRAXri -/* 1693 */ MCD_OPC_Decode, 148, 3, 9, // Opcode: SRAri -/* 1697 */ MCD_OPC_FilterValue, 40, 55, 0, // Skip to: 1756 -/* 1701 */ MCD_OPC_ExtractField, 13, 6, // Inst{18-13} ... -/* 1704 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1718 -/* 1708 */ MCD_OPC_CheckField, 0, 13, 0, 5, 16, // Skip to: 5815 -/* 1714 */ MCD_OPC_Decode, 239, 2, 4, // Opcode: RDY -/* 1718 */ MCD_OPC_FilterValue, 30, 16, 0, // Skip to: 1738 -/* 1722 */ MCD_OPC_CheckField, 25, 5, 0, 247, 15, // Skip to: 5815 -/* 1728 */ MCD_OPC_CheckField, 0, 13, 0, 241, 15, // Skip to: 5815 -/* 1734 */ MCD_OPC_Decode, 154, 3, 4, // Opcode: STBAR -/* 1738 */ MCD_OPC_FilterValue, 31, 233, 15, // Skip to: 5815 -/* 1742 */ MCD_OPC_CheckPredicate, 0, 229, 15, // Skip to: 5815 -/* 1746 */ MCD_OPC_CheckField, 25, 5, 0, 223, 15, // Skip to: 5815 -/* 1752 */ MCD_OPC_Decode, 198, 2, 16, // Opcode: MEMBARi -/* 1756 */ MCD_OPC_FilterValue, 43, 20, 0, // Skip to: 1780 -/* 1760 */ MCD_OPC_CheckPredicate, 0, 211, 15, // Skip to: 5815 -/* 1764 */ MCD_OPC_CheckField, 25, 5, 0, 205, 15, // Skip to: 5815 -/* 1770 */ MCD_OPC_CheckField, 0, 19, 0, 199, 15, // Skip to: 5815 -/* 1776 */ MCD_OPC_Decode, 183, 1, 4, // Opcode: FLUSHW -/* 1780 */ MCD_OPC_FilterValue, 44, 123, 0, // Skip to: 1907 -/* 1784 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1787 */ MCD_OPC_FilterValue, 0, 56, 0, // Skip to: 1847 -/* 1791 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 1794 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1820 -/* 1798 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1812 -/* 1802 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 1812 -/* 1808 */ MCD_OPC_Decode, 201, 2, 17, // Opcode: MOVFCCrr -/* 1812 */ MCD_OPC_CheckPredicate, 0, 159, 15, // Skip to: 5815 -/* 1816 */ MCD_OPC_Decode, 222, 3, 18, // Opcode: V9MOVFCCrr -/* 1820 */ MCD_OPC_FilterValue, 1, 151, 15, // Skip to: 5815 -/* 1824 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 1827 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1839 -/* 1831 */ MCD_OPC_CheckPredicate, 0, 140, 15, // Skip to: 5815 -/* 1835 */ MCD_OPC_Decode, 203, 2, 17, // Opcode: MOVICCrr -/* 1839 */ MCD_OPC_FilterValue, 2, 132, 15, // Skip to: 5815 -/* 1843 */ MCD_OPC_Decode, 220, 2, 17, // Opcode: MOVXCCrr -/* 1847 */ MCD_OPC_FilterValue, 1, 124, 15, // Skip to: 5815 -/* 1851 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 1854 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1880 -/* 1858 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1872 -/* 1862 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 1872 -/* 1868 */ MCD_OPC_Decode, 200, 2, 19, // Opcode: MOVFCCri -/* 1872 */ MCD_OPC_CheckPredicate, 0, 99, 15, // Skip to: 5815 -/* 1876 */ MCD_OPC_Decode, 221, 3, 20, // Opcode: V9MOVFCCri -/* 1880 */ MCD_OPC_FilterValue, 1, 91, 15, // Skip to: 5815 -/* 1884 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 1887 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1899 -/* 1891 */ MCD_OPC_CheckPredicate, 0, 80, 15, // Skip to: 5815 -/* 1895 */ MCD_OPC_Decode, 202, 2, 19, // Opcode: MOVICCri -/* 1899 */ MCD_OPC_FilterValue, 2, 72, 15, // Skip to: 5815 -/* 1903 */ MCD_OPC_Decode, 219, 2, 19, // Opcode: MOVXCCri -/* 1907 */ MCD_OPC_FilterValue, 45, 25, 0, // Skip to: 1936 -/* 1911 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 1914 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1928 -/* 1918 */ MCD_OPC_CheckField, 5, 8, 0, 51, 15, // Skip to: 5815 -/* 1924 */ MCD_OPC_Decode, 251, 2, 10, // Opcode: SDIVXrr -/* 1928 */ MCD_OPC_FilterValue, 1, 43, 15, // Skip to: 5815 -/* 1932 */ MCD_OPC_Decode, 250, 2, 11, // Opcode: SDIVXri -/* 1936 */ MCD_OPC_FilterValue, 46, 14, 0, // Skip to: 1954 -/* 1940 */ MCD_OPC_CheckPredicate, 0, 31, 15, // Skip to: 5815 -/* 1944 */ MCD_OPC_CheckField, 5, 14, 0, 25, 15, // Skip to: 5815 -/* 1950 */ MCD_OPC_Decode, 238, 2, 21, // Opcode: POPCrr -/* 1954 */ MCD_OPC_FilterValue, 47, 135, 0, // Skip to: 2093 -/* 1958 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 1961 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 1975 -/* 1965 */ MCD_OPC_CheckField, 5, 5, 0, 4, 15, // Skip to: 5815 -/* 1971 */ MCD_OPC_Decode, 215, 2, 14, // Opcode: MOVRRZrr -/* 1975 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 1989 -/* 1979 */ MCD_OPC_CheckField, 5, 5, 0, 246, 14, // Skip to: 5815 -/* 1985 */ MCD_OPC_Decode, 209, 2, 14, // Opcode: MOVRLEZrr -/* 1989 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 2003 -/* 1993 */ MCD_OPC_CheckField, 5, 5, 0, 232, 14, // Skip to: 5815 -/* 1999 */ MCD_OPC_Decode, 211, 2, 14, // Opcode: MOVRLZrr -/* 2003 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2017 -/* 2007 */ MCD_OPC_CheckField, 5, 5, 0, 218, 14, // Skip to: 5815 -/* 2013 */ MCD_OPC_Decode, 213, 2, 14, // Opcode: MOVRNZrr -/* 2017 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2031 -/* 2021 */ MCD_OPC_CheckField, 5, 5, 0, 204, 14, // Skip to: 5815 -/* 2027 */ MCD_OPC_Decode, 207, 2, 14, // Opcode: MOVRGZrr -/* 2031 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 2045 -/* 2035 */ MCD_OPC_CheckField, 5, 5, 0, 190, 14, // Skip to: 5815 -/* 2041 */ MCD_OPC_Decode, 205, 2, 14, // Opcode: MOVRGEZrr -/* 2045 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 2053 -/* 2049 */ MCD_OPC_Decode, 214, 2, 22, // Opcode: MOVRRZri -/* 2053 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 2061 -/* 2057 */ MCD_OPC_Decode, 208, 2, 22, // Opcode: MOVRLEZri -/* 2061 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 2069 -/* 2065 */ MCD_OPC_Decode, 210, 2, 22, // Opcode: MOVRLZri -/* 2069 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 2077 -/* 2073 */ MCD_OPC_Decode, 212, 2, 22, // Opcode: MOVRNZri -/* 2077 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 2085 -/* 2081 */ MCD_OPC_Decode, 206, 2, 22, // Opcode: MOVRGZri -/* 2085 */ MCD_OPC_FilterValue, 15, 142, 14, // Skip to: 5815 -/* 2089 */ MCD_OPC_Decode, 204, 2, 22, // Opcode: MOVRGEZri -/* 2093 */ MCD_OPC_FilterValue, 48, 37, 0, // Skip to: 2134 -/* 2097 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 2100 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 2120 -/* 2104 */ MCD_OPC_CheckField, 25, 5, 0, 121, 14, // Skip to: 5815 -/* 2110 */ MCD_OPC_CheckField, 5, 8, 0, 115, 14, // Skip to: 5815 -/* 2116 */ MCD_OPC_Decode, 224, 3, 12, // Opcode: WRYrr -/* 2120 */ MCD_OPC_FilterValue, 1, 107, 14, // Skip to: 5815 -/* 2124 */ MCD_OPC_CheckField, 25, 5, 0, 101, 14, // Skip to: 5815 -/* 2130 */ MCD_OPC_Decode, 223, 3, 13, // Opcode: WRYri -/* 2134 */ MCD_OPC_FilterValue, 52, 197, 2, // Skip to: 2847 -/* 2138 */ MCD_OPC_ExtractField, 5, 9, // Inst{13-5} ... -/* 2141 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 2155 -/* 2145 */ MCD_OPC_CheckField, 14, 5, 0, 80, 14, // Skip to: 5815 -/* 2151 */ MCD_OPC_Decode, 211, 1, 23, // Opcode: FMOVS -/* 2155 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 2173 -/* 2159 */ MCD_OPC_CheckPredicate, 0, 68, 14, // Skip to: 5815 -/* 2163 */ MCD_OPC_CheckField, 14, 5, 0, 62, 14, // Skip to: 5815 -/* 2169 */ MCD_OPC_Decode, 185, 1, 24, // Opcode: FMOVD -/* 2173 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 2191 -/* 2177 */ MCD_OPC_CheckPredicate, 0, 50, 14, // Skip to: 5815 -/* 2181 */ MCD_OPC_CheckField, 14, 5, 0, 44, 14, // Skip to: 5815 -/* 2187 */ MCD_OPC_Decode, 189, 1, 25, // Opcode: FMOVQ -/* 2191 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2205 -/* 2195 */ MCD_OPC_CheckField, 14, 5, 0, 30, 14, // Skip to: 5815 -/* 2201 */ MCD_OPC_Decode, 231, 1, 23, // Opcode: FNEGS -/* 2205 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2223 -/* 2209 */ MCD_OPC_CheckPredicate, 0, 18, 14, // Skip to: 5815 -/* 2213 */ MCD_OPC_CheckField, 14, 5, 0, 12, 14, // Skip to: 5815 -/* 2219 */ MCD_OPC_Decode, 229, 1, 24, // Opcode: FNEGD -/* 2223 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2241 -/* 2227 */ MCD_OPC_CheckPredicate, 0, 0, 14, // Skip to: 5815 -/* 2231 */ MCD_OPC_CheckField, 14, 5, 0, 250, 13, // Skip to: 5815 -/* 2237 */ MCD_OPC_Decode, 230, 1, 25, // Opcode: FNEGQ -/* 2241 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 2255 -/* 2245 */ MCD_OPC_CheckField, 14, 5, 0, 236, 13, // Skip to: 5815 -/* 2251 */ MCD_OPC_Decode, 140, 1, 23, // Opcode: FABSS -/* 2255 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 2273 -/* 2259 */ MCD_OPC_CheckPredicate, 0, 224, 13, // Skip to: 5815 -/* 2263 */ MCD_OPC_CheckField, 14, 5, 0, 218, 13, // Skip to: 5815 -/* 2269 */ MCD_OPC_Decode, 138, 1, 24, // Opcode: FABSD -/* 2273 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 2291 -/* 2277 */ MCD_OPC_CheckPredicate, 0, 206, 13, // Skip to: 5815 -/* 2281 */ MCD_OPC_CheckField, 14, 5, 0, 200, 13, // Skip to: 5815 -/* 2287 */ MCD_OPC_Decode, 139, 1, 25, // Opcode: FABSQ -/* 2291 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 2305 -/* 2295 */ MCD_OPC_CheckField, 14, 5, 0, 186, 13, // Skip to: 5815 -/* 2301 */ MCD_OPC_Decode, 147, 2, 23, // Opcode: FSQRTS -/* 2305 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 2319 -/* 2309 */ MCD_OPC_CheckField, 14, 5, 0, 172, 13, // Skip to: 5815 -/* 2315 */ MCD_OPC_Decode, 145, 2, 24, // Opcode: FSQRTD -/* 2319 */ MCD_OPC_FilterValue, 43, 10, 0, // Skip to: 2333 -/* 2323 */ MCD_OPC_CheckField, 14, 5, 0, 158, 13, // Skip to: 5815 -/* 2329 */ MCD_OPC_Decode, 146, 2, 25, // Opcode: FSQRTQ -/* 2333 */ MCD_OPC_FilterValue, 65, 4, 0, // Skip to: 2341 -/* 2337 */ MCD_OPC_Decode, 143, 1, 26, // Opcode: FADDS -/* 2341 */ MCD_OPC_FilterValue, 66, 4, 0, // Skip to: 2349 -/* 2345 */ MCD_OPC_Decode, 141, 1, 27, // Opcode: FADDD -/* 2349 */ MCD_OPC_FilterValue, 67, 4, 0, // Skip to: 2357 -/* 2353 */ MCD_OPC_Decode, 142, 1, 28, // Opcode: FADDQ -/* 2357 */ MCD_OPC_FilterValue, 69, 4, 0, // Skip to: 2365 -/* 2361 */ MCD_OPC_Decode, 162, 2, 26, // Opcode: FSUBS -/* 2365 */ MCD_OPC_FilterValue, 70, 4, 0, // Skip to: 2373 -/* 2369 */ MCD_OPC_Decode, 160, 2, 27, // Opcode: FSUBD -/* 2373 */ MCD_OPC_FilterValue, 71, 4, 0, // Skip to: 2381 -/* 2377 */ MCD_OPC_Decode, 161, 2, 28, // Opcode: FSUBQ -/* 2381 */ MCD_OPC_FilterValue, 73, 4, 0, // Skip to: 2389 -/* 2385 */ MCD_OPC_Decode, 224, 1, 26, // Opcode: FMULS -/* 2389 */ MCD_OPC_FilterValue, 74, 4, 0, // Skip to: 2397 -/* 2393 */ MCD_OPC_Decode, 220, 1, 27, // Opcode: FMULD -/* 2397 */ MCD_OPC_FilterValue, 75, 4, 0, // Skip to: 2405 -/* 2401 */ MCD_OPC_Decode, 223, 1, 28, // Opcode: FMULQ -/* 2405 */ MCD_OPC_FilterValue, 77, 4, 0, // Skip to: 2413 -/* 2409 */ MCD_OPC_Decode, 167, 1, 26, // Opcode: FDIVS -/* 2413 */ MCD_OPC_FilterValue, 78, 4, 0, // Skip to: 2421 -/* 2417 */ MCD_OPC_Decode, 165, 1, 27, // Opcode: FDIVD -/* 2421 */ MCD_OPC_FilterValue, 79, 4, 0, // Skip to: 2429 -/* 2425 */ MCD_OPC_Decode, 166, 1, 28, // Opcode: FDIVQ -/* 2429 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 2441 -/* 2433 */ MCD_OPC_CheckPredicate, 1, 50, 13, // Skip to: 5815 -/* 2437 */ MCD_OPC_Decode, 226, 1, 27, // Opcode: FNADDS -/* 2441 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 2453 -/* 2445 */ MCD_OPC_CheckPredicate, 1, 38, 13, // Skip to: 5815 -/* 2449 */ MCD_OPC_Decode, 225, 1, 27, // Opcode: FNADDD -/* 2453 */ MCD_OPC_FilterValue, 89, 8, 0, // Skip to: 2465 -/* 2457 */ MCD_OPC_CheckPredicate, 1, 26, 13, // Skip to: 5815 -/* 2461 */ MCD_OPC_Decode, 235, 1, 27, // Opcode: FNMULS -/* 2465 */ MCD_OPC_FilterValue, 90, 8, 0, // Skip to: 2477 -/* 2469 */ MCD_OPC_CheckPredicate, 1, 14, 13, // Skip to: 5815 -/* 2473 */ MCD_OPC_Decode, 234, 1, 27, // Opcode: FNMULD -/* 2477 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 2489 -/* 2481 */ MCD_OPC_CheckPredicate, 1, 2, 13, // Skip to: 5815 -/* 2485 */ MCD_OPC_Decode, 175, 1, 27, // Opcode: FHADDS -/* 2489 */ MCD_OPC_FilterValue, 98, 8, 0, // Skip to: 2501 -/* 2493 */ MCD_OPC_CheckPredicate, 1, 246, 12, // Skip to: 5815 -/* 2497 */ MCD_OPC_Decode, 174, 1, 27, // Opcode: FHADDD -/* 2501 */ MCD_OPC_FilterValue, 101, 8, 0, // Skip to: 2513 -/* 2505 */ MCD_OPC_CheckPredicate, 1, 234, 12, // Skip to: 5815 -/* 2509 */ MCD_OPC_Decode, 177, 1, 27, // Opcode: FHSUBS -/* 2513 */ MCD_OPC_FilterValue, 102, 8, 0, // Skip to: 2525 -/* 2517 */ MCD_OPC_CheckPredicate, 1, 222, 12, // Skip to: 5815 -/* 2521 */ MCD_OPC_Decode, 176, 1, 27, // Opcode: FHSUBD -/* 2525 */ MCD_OPC_FilterValue, 105, 4, 0, // Skip to: 2533 -/* 2529 */ MCD_OPC_Decode, 144, 2, 29, // Opcode: FSMULD -/* 2533 */ MCD_OPC_FilterValue, 110, 4, 0, // Skip to: 2541 -/* 2537 */ MCD_OPC_Decode, 168, 1, 30, // Opcode: FDMULQ -/* 2541 */ MCD_OPC_FilterValue, 113, 8, 0, // Skip to: 2553 -/* 2545 */ MCD_OPC_CheckPredicate, 1, 194, 12, // Skip to: 5815 -/* 2549 */ MCD_OPC_Decode, 233, 1, 27, // Opcode: FNHADDS -/* 2553 */ MCD_OPC_FilterValue, 114, 8, 0, // Skip to: 2565 -/* 2557 */ MCD_OPC_CheckPredicate, 1, 182, 12, // Skip to: 5815 -/* 2561 */ MCD_OPC_Decode, 232, 1, 27, // Opcode: FNHADDD -/* 2565 */ MCD_OPC_FilterValue, 121, 8, 0, // Skip to: 2577 -/* 2569 */ MCD_OPC_CheckPredicate, 1, 170, 12, // Skip to: 5815 -/* 2573 */ MCD_OPC_Decode, 242, 1, 27, // Opcode: FNSMULD -/* 2577 */ MCD_OPC_FilterValue, 129, 1, 10, 0, // Skip to: 2592 -/* 2582 */ MCD_OPC_CheckField, 14, 5, 0, 155, 12, // Skip to: 5815 -/* 2588 */ MCD_OPC_Decode, 159, 2, 31, // Opcode: FSTOX -/* 2592 */ MCD_OPC_FilterValue, 130, 1, 10, 0, // Skip to: 2607 -/* 2597 */ MCD_OPC_CheckField, 14, 5, 0, 140, 12, // Skip to: 5815 -/* 2603 */ MCD_OPC_Decode, 172, 1, 24, // Opcode: FDTOX -/* 2607 */ MCD_OPC_FilterValue, 131, 1, 10, 0, // Skip to: 2622 -/* 2612 */ MCD_OPC_CheckField, 14, 5, 0, 125, 12, // Skip to: 5815 -/* 2618 */ MCD_OPC_Decode, 139, 2, 32, // Opcode: FQTOX -/* 2622 */ MCD_OPC_FilterValue, 132, 1, 10, 0, // Skip to: 2637 -/* 2627 */ MCD_OPC_CheckField, 14, 5, 0, 110, 12, // Skip to: 5815 -/* 2633 */ MCD_OPC_Decode, 169, 2, 33, // Opcode: FXTOS -/* 2637 */ MCD_OPC_FilterValue, 136, 1, 10, 0, // Skip to: 2652 -/* 2642 */ MCD_OPC_CheckField, 14, 5, 0, 95, 12, // Skip to: 5815 -/* 2648 */ MCD_OPC_Decode, 167, 2, 24, // Opcode: FXTOD -/* 2652 */ MCD_OPC_FilterValue, 140, 1, 10, 0, // Skip to: 2667 -/* 2657 */ MCD_OPC_CheckField, 14, 5, 0, 80, 12, // Skip to: 5815 -/* 2663 */ MCD_OPC_Decode, 168, 2, 34, // Opcode: FXTOQ -/* 2667 */ MCD_OPC_FilterValue, 196, 1, 10, 0, // Skip to: 2682 -/* 2672 */ MCD_OPC_CheckField, 14, 5, 0, 65, 12, // Skip to: 5815 -/* 2678 */ MCD_OPC_Decode, 180, 1, 23, // Opcode: FITOS -/* 2682 */ MCD_OPC_FilterValue, 198, 1, 10, 0, // Skip to: 2697 -/* 2687 */ MCD_OPC_CheckField, 14, 5, 0, 50, 12, // Skip to: 5815 -/* 2693 */ MCD_OPC_Decode, 171, 1, 33, // Opcode: FDTOS -/* 2697 */ MCD_OPC_FilterValue, 199, 1, 10, 0, // Skip to: 2712 -/* 2702 */ MCD_OPC_CheckField, 14, 5, 0, 35, 12, // Skip to: 5815 -/* 2708 */ MCD_OPC_Decode, 138, 2, 35, // Opcode: FQTOS -/* 2712 */ MCD_OPC_FilterValue, 200, 1, 10, 0, // Skip to: 2727 -/* 2717 */ MCD_OPC_CheckField, 14, 5, 0, 20, 12, // Skip to: 5815 -/* 2723 */ MCD_OPC_Decode, 178, 1, 31, // Opcode: FITOD -/* 2727 */ MCD_OPC_FilterValue, 201, 1, 10, 0, // Skip to: 2742 -/* 2732 */ MCD_OPC_CheckField, 14, 5, 0, 5, 12, // Skip to: 5815 -/* 2738 */ MCD_OPC_Decode, 156, 2, 31, // Opcode: FSTOD -/* 2742 */ MCD_OPC_FilterValue, 203, 1, 10, 0, // Skip to: 2757 -/* 2747 */ MCD_OPC_CheckField, 14, 5, 0, 246, 11, // Skip to: 5815 -/* 2753 */ MCD_OPC_Decode, 136, 2, 32, // Opcode: FQTOD -/* 2757 */ MCD_OPC_FilterValue, 204, 1, 10, 0, // Skip to: 2772 -/* 2762 */ MCD_OPC_CheckField, 14, 5, 0, 231, 11, // Skip to: 5815 -/* 2768 */ MCD_OPC_Decode, 179, 1, 36, // Opcode: FITOQ -/* 2772 */ MCD_OPC_FilterValue, 205, 1, 10, 0, // Skip to: 2787 -/* 2777 */ MCD_OPC_CheckField, 14, 5, 0, 216, 11, // Skip to: 5815 -/* 2783 */ MCD_OPC_Decode, 158, 2, 36, // Opcode: FSTOQ -/* 2787 */ MCD_OPC_FilterValue, 206, 1, 10, 0, // Skip to: 2802 -/* 2792 */ MCD_OPC_CheckField, 14, 5, 0, 201, 11, // Skip to: 5815 -/* 2798 */ MCD_OPC_Decode, 170, 1, 34, // Opcode: FDTOQ -/* 2802 */ MCD_OPC_FilterValue, 209, 1, 10, 0, // Skip to: 2817 -/* 2807 */ MCD_OPC_CheckField, 14, 5, 0, 186, 11, // Skip to: 5815 -/* 2813 */ MCD_OPC_Decode, 157, 2, 23, // Opcode: FSTOI -/* 2817 */ MCD_OPC_FilterValue, 210, 1, 10, 0, // Skip to: 2832 -/* 2822 */ MCD_OPC_CheckField, 14, 5, 0, 171, 11, // Skip to: 5815 -/* 2828 */ MCD_OPC_Decode, 169, 1, 33, // Opcode: FDTOI -/* 2832 */ MCD_OPC_FilterValue, 211, 1, 162, 11, // Skip to: 5815 -/* 2837 */ MCD_OPC_CheckField, 14, 5, 0, 156, 11, // Skip to: 5815 -/* 2843 */ MCD_OPC_Decode, 137, 2, 35, // Opcode: FQTOI -/* 2847 */ MCD_OPC_FilterValue, 53, 70, 2, // Skip to: 3433 -/* 2851 */ MCD_OPC_ExtractField, 5, 6, // Inst{10-5} ... -/* 2854 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 2933 -/* 2858 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 2861 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2894 -/* 2865 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 2868 */ MCD_OPC_FilterValue, 0, 127, 11, // Skip to: 5815 -/* 2872 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2886 -/* 2876 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2886 -/* 2882 */ MCD_OPC_Decode, 212, 1, 37, // Opcode: FMOVS_FCC -/* 2886 */ MCD_OPC_CheckPredicate, 0, 109, 11, // Skip to: 5815 -/* 2890 */ MCD_OPC_Decode, 220, 3, 38, // Opcode: V9FMOVS_FCC -/* 2894 */ MCD_OPC_FilterValue, 1, 101, 11, // Skip to: 5815 -/* 2898 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 2901 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2919 -/* 2905 */ MCD_OPC_CheckPredicate, 0, 90, 11, // Skip to: 5815 -/* 2909 */ MCD_OPC_CheckField, 18, 1, 0, 84, 11, // Skip to: 5815 -/* 2915 */ MCD_OPC_Decode, 213, 1, 37, // Opcode: FMOVS_ICC -/* 2919 */ MCD_OPC_FilterValue, 2, 76, 11, // Skip to: 5815 -/* 2923 */ MCD_OPC_CheckField, 18, 1, 0, 70, 11, // Skip to: 5815 -/* 2929 */ MCD_OPC_Decode, 214, 1, 37, // Opcode: FMOVS_XCC -/* 2933 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 3012 -/* 2937 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 2940 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2973 -/* 2944 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 2947 */ MCD_OPC_FilterValue, 0, 48, 11, // Skip to: 5815 -/* 2951 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2965 -/* 2955 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2965 -/* 2961 */ MCD_OPC_Decode, 186, 1, 39, // Opcode: FMOVD_FCC -/* 2965 */ MCD_OPC_CheckPredicate, 0, 30, 11, // Skip to: 5815 -/* 2969 */ MCD_OPC_Decode, 218, 3, 40, // Opcode: V9FMOVD_FCC -/* 2973 */ MCD_OPC_FilterValue, 1, 22, 11, // Skip to: 5815 -/* 2977 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 2980 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2998 -/* 2984 */ MCD_OPC_CheckPredicate, 0, 11, 11, // Skip to: 5815 -/* 2988 */ MCD_OPC_CheckField, 18, 1, 0, 5, 11, // Skip to: 5815 -/* 2994 */ MCD_OPC_Decode, 187, 1, 39, // Opcode: FMOVD_ICC -/* 2998 */ MCD_OPC_FilterValue, 2, 253, 10, // Skip to: 5815 -/* 3002 */ MCD_OPC_CheckField, 18, 1, 0, 247, 10, // Skip to: 5815 -/* 3008 */ MCD_OPC_Decode, 188, 1, 39, // Opcode: FMOVD_XCC -/* 3012 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 3091 -/* 3016 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 3019 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 3052 -/* 3023 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 3026 */ MCD_OPC_FilterValue, 0, 225, 10, // Skip to: 5815 -/* 3030 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 3044 -/* 3034 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3044 -/* 3040 */ MCD_OPC_Decode, 190, 1, 41, // Opcode: FMOVQ_FCC -/* 3044 */ MCD_OPC_CheckPredicate, 0, 207, 10, // Skip to: 5815 -/* 3048 */ MCD_OPC_Decode, 219, 3, 42, // Opcode: V9FMOVQ_FCC -/* 3052 */ MCD_OPC_FilterValue, 1, 199, 10, // Skip to: 5815 -/* 3056 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... -/* 3059 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3077 -/* 3063 */ MCD_OPC_CheckPredicate, 0, 188, 10, // Skip to: 5815 -/* 3067 */ MCD_OPC_CheckField, 18, 1, 0, 182, 10, // Skip to: 5815 -/* 3073 */ MCD_OPC_Decode, 191, 1, 41, // Opcode: FMOVQ_ICC -/* 3077 */ MCD_OPC_FilterValue, 2, 174, 10, // Skip to: 5815 -/* 3081 */ MCD_OPC_CheckField, 18, 1, 0, 168, 10, // Skip to: 5815 -/* 3087 */ MCD_OPC_Decode, 192, 1, 41, // Opcode: FMOVQ_XCC -/* 3091 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 3122 -/* 3095 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 3098 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3110 -/* 3102 */ MCD_OPC_CheckPredicate, 0, 149, 10, // Skip to: 5815 -/* 3106 */ MCD_OPC_Decode, 201, 1, 43, // Opcode: FMOVRLEZS -/* 3110 */ MCD_OPC_FilterValue, 3, 141, 10, // Skip to: 5815 -/* 3114 */ MCD_OPC_CheckPredicate, 0, 137, 10, // Skip to: 5815 -/* 3118 */ MCD_OPC_Decode, 198, 1, 43, // Opcode: FMOVRGZS -/* 3122 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 3153 -/* 3126 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 3129 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3141 -/* 3133 */ MCD_OPC_CheckPredicate, 0, 118, 10, // Skip to: 5815 -/* 3137 */ MCD_OPC_Decode, 199, 1, 43, // Opcode: FMOVRLEZD -/* 3141 */ MCD_OPC_FilterValue, 3, 110, 10, // Skip to: 5815 -/* 3145 */ MCD_OPC_CheckPredicate, 0, 106, 10, // Skip to: 5815 -/* 3149 */ MCD_OPC_Decode, 196, 1, 43, // Opcode: FMOVRGZD -/* 3153 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 3184 -/* 3157 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 3160 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3172 -/* 3164 */ MCD_OPC_CheckPredicate, 0, 87, 10, // Skip to: 5815 -/* 3168 */ MCD_OPC_Decode, 200, 1, 43, // Opcode: FMOVRLEZQ -/* 3172 */ MCD_OPC_FilterValue, 3, 79, 10, // Skip to: 5815 -/* 3176 */ MCD_OPC_CheckPredicate, 0, 75, 10, // Skip to: 5815 -/* 3180 */ MCD_OPC_Decode, 197, 1, 43, // Opcode: FMOVRGZQ -/* 3184 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 3198 -/* 3188 */ MCD_OPC_CheckField, 11, 3, 1, 61, 10, // Skip to: 5815 -/* 3194 */ MCD_OPC_Decode, 217, 3, 44, // Opcode: V9FCMPS -/* 3198 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 3212 -/* 3202 */ MCD_OPC_CheckField, 11, 3, 1, 47, 10, // Skip to: 5815 -/* 3208 */ MCD_OPC_Decode, 212, 3, 45, // Opcode: V9FCMPD -/* 3212 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 3226 -/* 3216 */ MCD_OPC_CheckField, 11, 3, 1, 33, 10, // Skip to: 5815 -/* 3222 */ MCD_OPC_Decode, 216, 3, 46, // Opcode: V9FCMPQ -/* 3226 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 3240 -/* 3230 */ MCD_OPC_CheckField, 11, 3, 1, 19, 10, // Skip to: 5815 -/* 3236 */ MCD_OPC_Decode, 215, 3, 44, // Opcode: V9FCMPES -/* 3240 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 3254 -/* 3244 */ MCD_OPC_CheckField, 11, 3, 1, 5, 10, // Skip to: 5815 -/* 3250 */ MCD_OPC_Decode, 213, 3, 45, // Opcode: V9FCMPED -/* 3254 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 3268 -/* 3258 */ MCD_OPC_CheckField, 11, 3, 1, 247, 9, // Skip to: 5815 -/* 3264 */ MCD_OPC_Decode, 214, 3, 46, // Opcode: V9FCMPEQ -/* 3268 */ MCD_OPC_FilterValue, 37, 51, 0, // Skip to: 3323 -/* 3272 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 3275 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3287 -/* 3279 */ MCD_OPC_CheckPredicate, 0, 228, 9, // Skip to: 5815 -/* 3283 */ MCD_OPC_Decode, 210, 1, 43, // Opcode: FMOVRZS -/* 3287 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3299 -/* 3291 */ MCD_OPC_CheckPredicate, 0, 216, 9, // Skip to: 5815 -/* 3295 */ MCD_OPC_Decode, 204, 1, 43, // Opcode: FMOVRLZS -/* 3299 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3311 -/* 3303 */ MCD_OPC_CheckPredicate, 0, 204, 9, // Skip to: 5815 -/* 3307 */ MCD_OPC_Decode, 207, 1, 43, // Opcode: FMOVRNZS -/* 3311 */ MCD_OPC_FilterValue, 3, 196, 9, // Skip to: 5815 -/* 3315 */ MCD_OPC_CheckPredicate, 0, 192, 9, // Skip to: 5815 -/* 3319 */ MCD_OPC_Decode, 195, 1, 43, // Opcode: FMOVRGEZS -/* 3323 */ MCD_OPC_FilterValue, 38, 51, 0, // Skip to: 3378 -/* 3327 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 3330 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3342 -/* 3334 */ MCD_OPC_CheckPredicate, 0, 173, 9, // Skip to: 5815 -/* 3338 */ MCD_OPC_Decode, 208, 1, 43, // Opcode: FMOVRZD -/* 3342 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3354 -/* 3346 */ MCD_OPC_CheckPredicate, 0, 161, 9, // Skip to: 5815 -/* 3350 */ MCD_OPC_Decode, 202, 1, 43, // Opcode: FMOVRLZD -/* 3354 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3366 -/* 3358 */ MCD_OPC_CheckPredicate, 0, 149, 9, // Skip to: 5815 -/* 3362 */ MCD_OPC_Decode, 205, 1, 43, // Opcode: FMOVRNZD -/* 3366 */ MCD_OPC_FilterValue, 3, 141, 9, // Skip to: 5815 -/* 3370 */ MCD_OPC_CheckPredicate, 0, 137, 9, // Skip to: 5815 -/* 3374 */ MCD_OPC_Decode, 193, 1, 43, // Opcode: FMOVRGEZD -/* 3378 */ MCD_OPC_FilterValue, 39, 129, 9, // Skip to: 5815 -/* 3382 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 3385 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3397 -/* 3389 */ MCD_OPC_CheckPredicate, 0, 118, 9, // Skip to: 5815 -/* 3393 */ MCD_OPC_Decode, 209, 1, 43, // Opcode: FMOVRZQ -/* 3397 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3409 -/* 3401 */ MCD_OPC_CheckPredicate, 0, 106, 9, // Skip to: 5815 -/* 3405 */ MCD_OPC_Decode, 203, 1, 43, // Opcode: FMOVRLZQ -/* 3409 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3421 -/* 3413 */ MCD_OPC_CheckPredicate, 0, 94, 9, // Skip to: 5815 -/* 3417 */ MCD_OPC_Decode, 206, 1, 43, // Opcode: FMOVRNZQ -/* 3421 */ MCD_OPC_FilterValue, 3, 86, 9, // Skip to: 5815 -/* 3425 */ MCD_OPC_CheckPredicate, 0, 82, 9, // Skip to: 5815 -/* 3429 */ MCD_OPC_Decode, 194, 1, 43, // Opcode: FMOVRGEZQ -/* 3433 */ MCD_OPC_FilterValue, 54, 18, 6, // Skip to: 4991 -/* 3437 */ MCD_OPC_ExtractField, 5, 9, // Inst{13-5} ... -/* 3440 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3452 -/* 3444 */ MCD_OPC_CheckPredicate, 2, 63, 9, // Skip to: 5815 -/* 3448 */ MCD_OPC_Decode, 134, 1, 10, // Opcode: EDGE8 -/* 3452 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3464 -/* 3456 */ MCD_OPC_CheckPredicate, 3, 51, 9, // Skip to: 5815 -/* 3460 */ MCD_OPC_Decode, 137, 1, 10, // Opcode: EDGE8N -/* 3464 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3476 -/* 3468 */ MCD_OPC_CheckPredicate, 2, 39, 9, // Skip to: 5815 -/* 3472 */ MCD_OPC_Decode, 135, 1, 10, // Opcode: EDGE8L -/* 3476 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3488 -/* 3480 */ MCD_OPC_CheckPredicate, 3, 27, 9, // Skip to: 5815 -/* 3484 */ MCD_OPC_Decode, 136, 1, 10, // Opcode: EDGE8LN -/* 3488 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 3499 -/* 3492 */ MCD_OPC_CheckPredicate, 2, 15, 9, // Skip to: 5815 -/* 3496 */ MCD_OPC_Decode, 126, 10, // Opcode: EDGE16 -/* 3499 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 3511 -/* 3503 */ MCD_OPC_CheckPredicate, 3, 4, 9, // Skip to: 5815 -/* 3507 */ MCD_OPC_Decode, 129, 1, 10, // Opcode: EDGE16N -/* 3511 */ MCD_OPC_FilterValue, 6, 7, 0, // Skip to: 3522 -/* 3515 */ MCD_OPC_CheckPredicate, 2, 248, 8, // Skip to: 5815 -/* 3519 */ MCD_OPC_Decode, 127, 10, // Opcode: EDGE16L -/* 3522 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 3534 -/* 3526 */ MCD_OPC_CheckPredicate, 3, 237, 8, // Skip to: 5815 -/* 3530 */ MCD_OPC_Decode, 128, 1, 10, // Opcode: EDGE16LN -/* 3534 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 3546 -/* 3538 */ MCD_OPC_CheckPredicate, 2, 225, 8, // Skip to: 5815 -/* 3542 */ MCD_OPC_Decode, 130, 1, 10, // Opcode: EDGE32 -/* 3546 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 3558 -/* 3550 */ MCD_OPC_CheckPredicate, 3, 213, 8, // Skip to: 5815 -/* 3554 */ MCD_OPC_Decode, 133, 1, 10, // Opcode: EDGE32N -/* 3558 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 3570 -/* 3562 */ MCD_OPC_CheckPredicate, 2, 201, 8, // Skip to: 5815 -/* 3566 */ MCD_OPC_Decode, 131, 1, 10, // Opcode: EDGE32L -/* 3570 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 3582 -/* 3574 */ MCD_OPC_CheckPredicate, 3, 189, 8, // Skip to: 5815 -/* 3578 */ MCD_OPC_Decode, 132, 1, 10, // Opcode: EDGE32LN -/* 3582 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 3593 -/* 3586 */ MCD_OPC_CheckPredicate, 2, 177, 8, // Skip to: 5815 -/* 3590 */ MCD_OPC_Decode, 51, 10, // Opcode: ARRAY8 -/* 3593 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 3604 -/* 3597 */ MCD_OPC_CheckPredicate, 1, 166, 8, // Skip to: 5815 -/* 3601 */ MCD_OPC_Decode, 28, 10, // Opcode: ADDXC -/* 3604 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 3615 -/* 3608 */ MCD_OPC_CheckPredicate, 2, 155, 8, // Skip to: 5815 -/* 3612 */ MCD_OPC_Decode, 49, 10, // Opcode: ARRAY16 -/* 3615 */ MCD_OPC_FilterValue, 19, 7, 0, // Skip to: 3626 -/* 3619 */ MCD_OPC_CheckPredicate, 1, 144, 8, // Skip to: 5815 -/* 3623 */ MCD_OPC_Decode, 29, 10, // Opcode: ADDXCCC -/* 3626 */ MCD_OPC_FilterValue, 20, 7, 0, // Skip to: 3637 -/* 3630 */ MCD_OPC_CheckPredicate, 2, 133, 8, // Skip to: 5815 -/* 3634 */ MCD_OPC_Decode, 50, 10, // Opcode: ARRAY32 -/* 3637 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 3649 -/* 3641 */ MCD_OPC_CheckPredicate, 1, 122, 8, // Skip to: 5815 -/* 3645 */ MCD_OPC_Decode, 208, 3, 10, // Opcode: UMULXHI -/* 3649 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3667 -/* 3653 */ MCD_OPC_CheckPredicate, 1, 110, 8, // Skip to: 5815 -/* 3657 */ MCD_OPC_CheckField, 14, 5, 0, 104, 8, // Skip to: 5815 -/* 3663 */ MCD_OPC_Decode, 197, 2, 47, // Opcode: LZCNT -/* 3667 */ MCD_OPC_FilterValue, 24, 7, 0, // Skip to: 3678 -/* 3671 */ MCD_OPC_CheckPredicate, 2, 92, 8, // Skip to: 5815 -/* 3675 */ MCD_OPC_Decode, 36, 10, // Opcode: ALIGNADDR -/* 3678 */ MCD_OPC_FilterValue, 25, 7, 0, // Skip to: 3689 -/* 3682 */ MCD_OPC_CheckPredicate, 3, 81, 8, // Skip to: 5815 -/* 3686 */ MCD_OPC_Decode, 78, 10, // Opcode: BMASK -/* 3689 */ MCD_OPC_FilterValue, 26, 7, 0, // Skip to: 3700 -/* 3693 */ MCD_OPC_CheckPredicate, 2, 70, 8, // Skip to: 5815 -/* 3697 */ MCD_OPC_Decode, 37, 10, // Opcode: ALIGNADDRL -/* 3700 */ MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 3723 -/* 3704 */ MCD_OPC_CheckPredicate, 1, 59, 8, // Skip to: 5815 -/* 3708 */ MCD_OPC_CheckField, 25, 5, 0, 53, 8, // Skip to: 5815 -/* 3714 */ MCD_OPC_CheckField, 14, 5, 0, 47, 8, // Skip to: 5815 -/* 3720 */ MCD_OPC_Decode, 123, 48, // Opcode: CMASK8 -/* 3723 */ MCD_OPC_FilterValue, 28, 7, 0, // Skip to: 3734 -/* 3727 */ MCD_OPC_CheckPredicate, 3, 36, 8, // Skip to: 5815 -/* 3731 */ MCD_OPC_Decode, 115, 27, // Opcode: BSHUFFLE -/* 3734 */ MCD_OPC_FilterValue, 29, 19, 0, // Skip to: 3757 -/* 3738 */ MCD_OPC_CheckPredicate, 1, 25, 8, // Skip to: 5815 -/* 3742 */ MCD_OPC_CheckField, 25, 5, 0, 19, 8, // Skip to: 5815 -/* 3748 */ MCD_OPC_CheckField, 14, 5, 0, 13, 8, // Skip to: 5815 -/* 3754 */ MCD_OPC_Decode, 121, 48, // Opcode: CMASK16 -/* 3757 */ MCD_OPC_FilterValue, 31, 19, 0, // Skip to: 3780 -/* 3761 */ MCD_OPC_CheckPredicate, 1, 2, 8, // Skip to: 5815 -/* 3765 */ MCD_OPC_CheckField, 25, 5, 0, 252, 7, // Skip to: 5815 -/* 3771 */ MCD_OPC_CheckField, 14, 5, 0, 246, 7, // Skip to: 5815 -/* 3777 */ MCD_OPC_Decode, 122, 48, // Opcode: CMASK32 -/* 3780 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3792 -/* 3784 */ MCD_OPC_CheckPredicate, 2, 235, 7, // Skip to: 5815 -/* 3788 */ MCD_OPC_Decode, 159, 1, 49, // Opcode: FCMPLE16 -/* 3792 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3804 -/* 3796 */ MCD_OPC_CheckPredicate, 1, 223, 7, // Skip to: 5815 -/* 3800 */ MCD_OPC_Decode, 142, 2, 27, // Opcode: FSLL16 -/* 3804 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 3816 -/* 3808 */ MCD_OPC_CheckPredicate, 2, 211, 7, // Skip to: 5815 -/* 3812 */ MCD_OPC_Decode, 161, 1, 49, // Opcode: FCMPNE16 -/* 3816 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 3828 -/* 3820 */ MCD_OPC_CheckPredicate, 1, 199, 7, // Skip to: 5815 -/* 3824 */ MCD_OPC_Decode, 154, 2, 27, // Opcode: FSRL16 -/* 3828 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 3840 -/* 3832 */ MCD_OPC_CheckPredicate, 2, 187, 7, // Skip to: 5815 -/* 3836 */ MCD_OPC_Decode, 160, 1, 49, // Opcode: FCMPLE32 -/* 3840 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 3852 -/* 3844 */ MCD_OPC_CheckPredicate, 1, 175, 7, // Skip to: 5815 -/* 3848 */ MCD_OPC_Decode, 143, 2, 27, // Opcode: FSLL32 -/* 3852 */ MCD_OPC_FilterValue, 38, 8, 0, // Skip to: 3864 -/* 3856 */ MCD_OPC_CheckPredicate, 2, 163, 7, // Skip to: 5815 -/* 3860 */ MCD_OPC_Decode, 162, 1, 49, // Opcode: FCMPNE32 -/* 3864 */ MCD_OPC_FilterValue, 39, 8, 0, // Skip to: 3876 -/* 3868 */ MCD_OPC_CheckPredicate, 1, 151, 7, // Skip to: 5815 -/* 3872 */ MCD_OPC_Decode, 155, 2, 27, // Opcode: FSRL32 -/* 3876 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3888 -/* 3880 */ MCD_OPC_CheckPredicate, 2, 139, 7, // Skip to: 5815 -/* 3884 */ MCD_OPC_Decode, 157, 1, 49, // Opcode: FCMPGT16 -/* 3888 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3900 -/* 3892 */ MCD_OPC_CheckPredicate, 1, 127, 7, // Skip to: 5815 -/* 3896 */ MCD_OPC_Decode, 140, 2, 27, // Opcode: FSLAS16 -/* 3900 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 3912 -/* 3904 */ MCD_OPC_CheckPredicate, 2, 115, 7, // Skip to: 5815 -/* 3908 */ MCD_OPC_Decode, 155, 1, 49, // Opcode: FCMPEQ16 -/* 3912 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 3924 -/* 3916 */ MCD_OPC_CheckPredicate, 1, 103, 7, // Skip to: 5815 -/* 3920 */ MCD_OPC_Decode, 148, 2, 27, // Opcode: FSRA16 -/* 3924 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 3936 -/* 3928 */ MCD_OPC_CheckPredicate, 2, 91, 7, // Skip to: 5815 -/* 3932 */ MCD_OPC_Decode, 158, 1, 49, // Opcode: FCMPGT32 -/* 3936 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 3948 -/* 3940 */ MCD_OPC_CheckPredicate, 1, 79, 7, // Skip to: 5815 -/* 3944 */ MCD_OPC_Decode, 141, 2, 27, // Opcode: FSLAS32 -/* 3948 */ MCD_OPC_FilterValue, 46, 8, 0, // Skip to: 3960 -/* 3952 */ MCD_OPC_CheckPredicate, 2, 67, 7, // Skip to: 5815 -/* 3956 */ MCD_OPC_Decode, 156, 1, 49, // Opcode: FCMPEQ32 -/* 3960 */ MCD_OPC_FilterValue, 47, 8, 0, // Skip to: 3972 -/* 3964 */ MCD_OPC_CheckPredicate, 1, 55, 7, // Skip to: 5815 -/* 3968 */ MCD_OPC_Decode, 149, 2, 27, // Opcode: FSRA32 -/* 3972 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3984 -/* 3976 */ MCD_OPC_CheckPredicate, 2, 43, 7, // Skip to: 5815 -/* 3980 */ MCD_OPC_Decode, 217, 1, 27, // Opcode: FMUL8X16 -/* 3984 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 3996 -/* 3988 */ MCD_OPC_CheckPredicate, 2, 31, 7, // Skip to: 5815 -/* 3992 */ MCD_OPC_Decode, 219, 1, 27, // Opcode: FMUL8X16AU -/* 3996 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 4008 -/* 4000 */ MCD_OPC_CheckPredicate, 2, 19, 7, // Skip to: 5815 -/* 4004 */ MCD_OPC_Decode, 218, 1, 27, // Opcode: FMUL8X16AL -/* 4008 */ MCD_OPC_FilterValue, 54, 8, 0, // Skip to: 4020 -/* 4012 */ MCD_OPC_CheckPredicate, 2, 7, 7, // Skip to: 5815 -/* 4016 */ MCD_OPC_Decode, 215, 1, 27, // Opcode: FMUL8SUX16 -/* 4020 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 4032 -/* 4024 */ MCD_OPC_CheckPredicate, 2, 251, 6, // Skip to: 5815 -/* 4028 */ MCD_OPC_Decode, 216, 1, 27, // Opcode: FMUL8ULX16 -/* 4032 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 4044 -/* 4036 */ MCD_OPC_CheckPredicate, 2, 239, 6, // Skip to: 5815 -/* 4040 */ MCD_OPC_Decode, 221, 1, 27, // Opcode: FMULD8SUX16 -/* 4044 */ MCD_OPC_FilterValue, 57, 8, 0, // Skip to: 4056 -/* 4048 */ MCD_OPC_CheckPredicate, 2, 227, 6, // Skip to: 5815 -/* 4052 */ MCD_OPC_Decode, 222, 1, 27, // Opcode: FMULD8ULX16 -/* 4056 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 4068 -/* 4060 */ MCD_OPC_CheckPredicate, 2, 215, 6, // Skip to: 5815 -/* 4064 */ MCD_OPC_Decode, 252, 1, 27, // Opcode: FPACK32 -/* 4068 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 4086 -/* 4072 */ MCD_OPC_CheckPredicate, 2, 203, 6, // Skip to: 5815 -/* 4076 */ MCD_OPC_CheckField, 14, 5, 0, 197, 6, // Skip to: 5815 -/* 4082 */ MCD_OPC_Decode, 251, 1, 24, // Opcode: FPACK16 -/* 4086 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 4104 -/* 4090 */ MCD_OPC_CheckPredicate, 2, 185, 6, // Skip to: 5815 -/* 4094 */ MCD_OPC_CheckField, 14, 5, 0, 179, 6, // Skip to: 5815 -/* 4100 */ MCD_OPC_Decode, 253, 1, 24, // Opcode: FPACKFIX -/* 4104 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 4116 -/* 4108 */ MCD_OPC_CheckPredicate, 2, 167, 6, // Skip to: 5815 -/* 4112 */ MCD_OPC_Decode, 236, 2, 27, // Opcode: PDIST -/* 4116 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 4128 -/* 4120 */ MCD_OPC_CheckPredicate, 1, 155, 6, // Skip to: 5815 -/* 4124 */ MCD_OPC_Decode, 237, 2, 27, // Opcode: PDISTN -/* 4128 */ MCD_OPC_FilterValue, 64, 8, 0, // Skip to: 4140 -/* 4132 */ MCD_OPC_CheckPredicate, 1, 143, 6, // Skip to: 5815 -/* 4136 */ MCD_OPC_Decode, 184, 1, 27, // Opcode: FMEAN16 -/* 4140 */ MCD_OPC_FilterValue, 66, 8, 0, // Skip to: 4152 -/* 4144 */ MCD_OPC_CheckPredicate, 1, 131, 6, // Skip to: 5815 -/* 4148 */ MCD_OPC_Decode, 130, 2, 27, // Opcode: FPADD64 -/* 4152 */ MCD_OPC_FilterValue, 68, 8, 0, // Skip to: 4164 -/* 4156 */ MCD_OPC_CheckPredicate, 1, 119, 6, // Skip to: 5815 -/* 4160 */ MCD_OPC_Decode, 153, 1, 27, // Opcode: FCHKSM16 -/* 4164 */ MCD_OPC_FilterValue, 72, 8, 0, // Skip to: 4176 -/* 4168 */ MCD_OPC_CheckPredicate, 2, 107, 6, // Skip to: 5815 -/* 4172 */ MCD_OPC_Decode, 144, 1, 27, // Opcode: FALIGNADATA -/* 4176 */ MCD_OPC_FilterValue, 75, 8, 0, // Skip to: 4188 -/* 4180 */ MCD_OPC_CheckPredicate, 2, 95, 6, // Skip to: 5815 -/* 4184 */ MCD_OPC_Decode, 131, 2, 27, // Opcode: FPMERGE -/* 4188 */ MCD_OPC_FilterValue, 77, 14, 0, // Skip to: 4206 -/* 4192 */ MCD_OPC_CheckPredicate, 2, 83, 6, // Skip to: 5815 -/* 4196 */ MCD_OPC_CheckField, 14, 5, 0, 77, 6, // Skip to: 5815 -/* 4202 */ MCD_OPC_Decode, 173, 1, 24, // Opcode: FEXPAND -/* 4206 */ MCD_OPC_FilterValue, 80, 8, 0, // Skip to: 4218 -/* 4210 */ MCD_OPC_CheckPredicate, 2, 65, 6, // Skip to: 5815 -/* 4214 */ MCD_OPC_Decode, 254, 1, 27, // Opcode: FPADD16 -/* 4218 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 4230 -/* 4222 */ MCD_OPC_CheckPredicate, 2, 53, 6, // Skip to: 5815 -/* 4226 */ MCD_OPC_Decode, 255, 1, 27, // Opcode: FPADD16S -/* 4230 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 4242 -/* 4234 */ MCD_OPC_CheckPredicate, 2, 41, 6, // Skip to: 5815 -/* 4238 */ MCD_OPC_Decode, 128, 2, 27, // Opcode: FPADD32 -/* 4242 */ MCD_OPC_FilterValue, 83, 8, 0, // Skip to: 4254 -/* 4246 */ MCD_OPC_CheckPredicate, 2, 29, 6, // Skip to: 5815 -/* 4250 */ MCD_OPC_Decode, 129, 2, 27, // Opcode: FPADD32S -/* 4254 */ MCD_OPC_FilterValue, 84, 8, 0, // Skip to: 4266 -/* 4258 */ MCD_OPC_CheckPredicate, 2, 17, 6, // Skip to: 5815 -/* 4262 */ MCD_OPC_Decode, 132, 2, 27, // Opcode: FPSUB16 -/* 4266 */ MCD_OPC_FilterValue, 85, 8, 0, // Skip to: 4278 -/* 4270 */ MCD_OPC_CheckPredicate, 2, 5, 6, // Skip to: 5815 -/* 4274 */ MCD_OPC_Decode, 133, 2, 27, // Opcode: FPSUB16S -/* 4278 */ MCD_OPC_FilterValue, 86, 8, 0, // Skip to: 4290 -/* 4282 */ MCD_OPC_CheckPredicate, 2, 249, 5, // Skip to: 5815 -/* 4286 */ MCD_OPC_Decode, 134, 2, 27, // Opcode: FPSUB32 -/* 4290 */ MCD_OPC_FilterValue, 87, 8, 0, // Skip to: 4302 -/* 4294 */ MCD_OPC_CheckPredicate, 2, 237, 5, // Skip to: 5815 -/* 4298 */ MCD_OPC_Decode, 135, 2, 27, // Opcode: FPSUB32S -/* 4302 */ MCD_OPC_FilterValue, 96, 20, 0, // Skip to: 4326 -/* 4306 */ MCD_OPC_CheckPredicate, 2, 225, 5, // Skip to: 5815 -/* 4310 */ MCD_OPC_CheckField, 14, 5, 0, 219, 5, // Skip to: 5815 -/* 4316 */ MCD_OPC_CheckField, 0, 5, 0, 213, 5, // Skip to: 5815 -/* 4322 */ MCD_OPC_Decode, 170, 2, 50, // Opcode: FZERO -/* 4326 */ MCD_OPC_FilterValue, 97, 20, 0, // Skip to: 4350 -/* 4330 */ MCD_OPC_CheckPredicate, 2, 201, 5, // Skip to: 5815 -/* 4334 */ MCD_OPC_CheckField, 14, 5, 0, 195, 5, // Skip to: 5815 -/* 4340 */ MCD_OPC_CheckField, 0, 5, 0, 189, 5, // Skip to: 5815 -/* 4346 */ MCD_OPC_Decode, 171, 2, 51, // Opcode: FZEROS -/* 4350 */ MCD_OPC_FilterValue, 98, 8, 0, // Skip to: 4362 -/* 4354 */ MCD_OPC_CheckPredicate, 2, 177, 5, // Skip to: 5815 -/* 4358 */ MCD_OPC_Decode, 236, 1, 27, // Opcode: FNOR -/* 4362 */ MCD_OPC_FilterValue, 99, 8, 0, // Skip to: 4374 -/* 4366 */ MCD_OPC_CheckPredicate, 2, 165, 5, // Skip to: 5815 -/* 4370 */ MCD_OPC_Decode, 237, 1, 26, // Opcode: FNORS -/* 4374 */ MCD_OPC_FilterValue, 100, 8, 0, // Skip to: 4386 -/* 4378 */ MCD_OPC_CheckPredicate, 2, 153, 5, // Skip to: 5815 -/* 4382 */ MCD_OPC_Decode, 148, 1, 27, // Opcode: FANDNOT2 -/* 4386 */ MCD_OPC_FilterValue, 101, 8, 0, // Skip to: 4398 -/* 4390 */ MCD_OPC_CheckPredicate, 2, 141, 5, // Skip to: 5815 -/* 4394 */ MCD_OPC_Decode, 149, 1, 26, // Opcode: FANDNOT2S -/* 4398 */ MCD_OPC_FilterValue, 102, 14, 0, // Skip to: 4416 -/* 4402 */ MCD_OPC_CheckPredicate, 2, 129, 5, // Skip to: 5815 -/* 4406 */ MCD_OPC_CheckField, 14, 5, 0, 123, 5, // Skip to: 5815 -/* 4412 */ MCD_OPC_Decode, 240, 1, 24, // Opcode: FNOT2 -/* 4416 */ MCD_OPC_FilterValue, 103, 14, 0, // Skip to: 4434 -/* 4420 */ MCD_OPC_CheckPredicate, 2, 111, 5, // Skip to: 5815 -/* 4424 */ MCD_OPC_CheckField, 14, 5, 0, 105, 5, // Skip to: 5815 -/* 4430 */ MCD_OPC_Decode, 241, 1, 23, // Opcode: FNOT2S -/* 4434 */ MCD_OPC_FilterValue, 104, 8, 0, // Skip to: 4446 -/* 4438 */ MCD_OPC_CheckPredicate, 2, 93, 5, // Skip to: 5815 -/* 4442 */ MCD_OPC_Decode, 146, 1, 27, // Opcode: FANDNOT1 -/* 4446 */ MCD_OPC_FilterValue, 105, 8, 0, // Skip to: 4458 -/* 4450 */ MCD_OPC_CheckPredicate, 2, 81, 5, // Skip to: 5815 -/* 4454 */ MCD_OPC_Decode, 147, 1, 26, // Opcode: FANDNOT1S -/* 4458 */ MCD_OPC_FilterValue, 106, 14, 0, // Skip to: 4476 -/* 4462 */ MCD_OPC_CheckPredicate, 2, 69, 5, // Skip to: 5815 -/* 4466 */ MCD_OPC_CheckField, 0, 5, 0, 63, 5, // Skip to: 5815 -/* 4472 */ MCD_OPC_Decode, 238, 1, 52, // Opcode: FNOT1 -/* 4476 */ MCD_OPC_FilterValue, 107, 14, 0, // Skip to: 4494 -/* 4480 */ MCD_OPC_CheckPredicate, 2, 51, 5, // Skip to: 5815 -/* 4484 */ MCD_OPC_CheckField, 0, 5, 0, 45, 5, // Skip to: 5815 -/* 4490 */ MCD_OPC_Decode, 239, 1, 53, // Opcode: FNOT1S -/* 4494 */ MCD_OPC_FilterValue, 108, 8, 0, // Skip to: 4506 -/* 4498 */ MCD_OPC_CheckPredicate, 2, 33, 5, // Skip to: 5815 -/* 4502 */ MCD_OPC_Decode, 165, 2, 27, // Opcode: FXOR -/* 4506 */ MCD_OPC_FilterValue, 109, 8, 0, // Skip to: 4518 -/* 4510 */ MCD_OPC_CheckPredicate, 2, 21, 5, // Skip to: 5815 -/* 4514 */ MCD_OPC_Decode, 166, 2, 26, // Opcode: FXORS -/* 4518 */ MCD_OPC_FilterValue, 110, 8, 0, // Skip to: 4530 -/* 4522 */ MCD_OPC_CheckPredicate, 2, 9, 5, // Skip to: 5815 -/* 4526 */ MCD_OPC_Decode, 227, 1, 27, // Opcode: FNAND -/* 4530 */ MCD_OPC_FilterValue, 111, 8, 0, // Skip to: 4542 -/* 4534 */ MCD_OPC_CheckPredicate, 2, 253, 4, // Skip to: 5815 -/* 4538 */ MCD_OPC_Decode, 228, 1, 26, // Opcode: FNANDS -/* 4542 */ MCD_OPC_FilterValue, 112, 8, 0, // Skip to: 4554 -/* 4546 */ MCD_OPC_CheckPredicate, 2, 241, 4, // Skip to: 5815 -/* 4550 */ MCD_OPC_Decode, 145, 1, 27, // Opcode: FAND -/* 4554 */ MCD_OPC_FilterValue, 113, 8, 0, // Skip to: 4566 -/* 4558 */ MCD_OPC_CheckPredicate, 2, 229, 4, // Skip to: 5815 -/* 4562 */ MCD_OPC_Decode, 150, 1, 26, // Opcode: FANDS -/* 4566 */ MCD_OPC_FilterValue, 114, 8, 0, // Skip to: 4578 -/* 4570 */ MCD_OPC_CheckPredicate, 2, 217, 4, // Skip to: 5815 -/* 4574 */ MCD_OPC_Decode, 163, 2, 27, // Opcode: FXNOR -/* 4578 */ MCD_OPC_FilterValue, 115, 8, 0, // Skip to: 4590 -/* 4582 */ MCD_OPC_CheckPredicate, 2, 205, 4, // Skip to: 5815 -/* 4586 */ MCD_OPC_Decode, 164, 2, 26, // Opcode: FXNORS -/* 4590 */ MCD_OPC_FilterValue, 116, 14, 0, // Skip to: 4608 -/* 4594 */ MCD_OPC_CheckPredicate, 2, 193, 4, // Skip to: 5815 -/* 4598 */ MCD_OPC_CheckField, 0, 5, 0, 187, 4, // Skip to: 5815 -/* 4604 */ MCD_OPC_Decode, 150, 2, 52, // Opcode: FSRC1 -/* 4608 */ MCD_OPC_FilterValue, 117, 14, 0, // Skip to: 4626 -/* 4612 */ MCD_OPC_CheckPredicate, 2, 175, 4, // Skip to: 5815 -/* 4616 */ MCD_OPC_CheckField, 0, 5, 0, 169, 4, // Skip to: 5815 -/* 4622 */ MCD_OPC_Decode, 151, 2, 53, // Opcode: FSRC1S -/* 4626 */ MCD_OPC_FilterValue, 118, 8, 0, // Skip to: 4638 -/* 4630 */ MCD_OPC_CheckPredicate, 2, 157, 4, // Skip to: 5815 -/* 4634 */ MCD_OPC_Decode, 248, 1, 27, // Opcode: FORNOT2 -/* 4638 */ MCD_OPC_FilterValue, 119, 8, 0, // Skip to: 4650 -/* 4642 */ MCD_OPC_CheckPredicate, 2, 145, 4, // Skip to: 5815 -/* 4646 */ MCD_OPC_Decode, 249, 1, 26, // Opcode: FORNOT2S -/* 4650 */ MCD_OPC_FilterValue, 120, 14, 0, // Skip to: 4668 -/* 4654 */ MCD_OPC_CheckPredicate, 2, 133, 4, // Skip to: 5815 -/* 4658 */ MCD_OPC_CheckField, 14, 5, 0, 127, 4, // Skip to: 5815 -/* 4664 */ MCD_OPC_Decode, 152, 2, 24, // Opcode: FSRC2 -/* 4668 */ MCD_OPC_FilterValue, 121, 14, 0, // Skip to: 4686 -/* 4672 */ MCD_OPC_CheckPredicate, 2, 115, 4, // Skip to: 5815 -/* 4676 */ MCD_OPC_CheckField, 14, 5, 0, 109, 4, // Skip to: 5815 -/* 4682 */ MCD_OPC_Decode, 153, 2, 23, // Opcode: FSRC2S -/* 4686 */ MCD_OPC_FilterValue, 122, 8, 0, // Skip to: 4698 -/* 4690 */ MCD_OPC_CheckPredicate, 2, 97, 4, // Skip to: 5815 -/* 4694 */ MCD_OPC_Decode, 246, 1, 27, // Opcode: FORNOT1 -/* 4698 */ MCD_OPC_FilterValue, 123, 8, 0, // Skip to: 4710 -/* 4702 */ MCD_OPC_CheckPredicate, 2, 85, 4, // Skip to: 5815 -/* 4706 */ MCD_OPC_Decode, 247, 1, 26, // Opcode: FORNOT1S -/* 4710 */ MCD_OPC_FilterValue, 124, 8, 0, // Skip to: 4722 -/* 4714 */ MCD_OPC_CheckPredicate, 2, 73, 4, // Skip to: 5815 -/* 4718 */ MCD_OPC_Decode, 245, 1, 27, // Opcode: FOR -/* 4722 */ MCD_OPC_FilterValue, 125, 8, 0, // Skip to: 4734 -/* 4726 */ MCD_OPC_CheckPredicate, 2, 61, 4, // Skip to: 5815 -/* 4730 */ MCD_OPC_Decode, 250, 1, 26, // Opcode: FORS -/* 4734 */ MCD_OPC_FilterValue, 126, 20, 0, // Skip to: 4758 -/* 4738 */ MCD_OPC_CheckPredicate, 2, 49, 4, // Skip to: 5815 -/* 4742 */ MCD_OPC_CheckField, 14, 5, 0, 43, 4, // Skip to: 5815 -/* 4748 */ MCD_OPC_CheckField, 0, 5, 0, 37, 4, // Skip to: 5815 -/* 4754 */ MCD_OPC_Decode, 243, 1, 50, // Opcode: FONE -/* 4758 */ MCD_OPC_FilterValue, 127, 20, 0, // Skip to: 4782 -/* 4762 */ MCD_OPC_CheckPredicate, 2, 25, 4, // Skip to: 5815 -/* 4766 */ MCD_OPC_CheckField, 14, 5, 0, 19, 4, // Skip to: 5815 -/* 4772 */ MCD_OPC_CheckField, 0, 5, 0, 13, 4, // Skip to: 5815 -/* 4778 */ MCD_OPC_Decode, 244, 1, 51, // Opcode: FONES -/* 4782 */ MCD_OPC_FilterValue, 128, 1, 26, 0, // Skip to: 4813 -/* 4787 */ MCD_OPC_CheckPredicate, 2, 0, 4, // Skip to: 5815 -/* 4791 */ MCD_OPC_CheckField, 25, 5, 0, 250, 3, // Skip to: 5815 -/* 4797 */ MCD_OPC_CheckField, 14, 5, 0, 244, 3, // Skip to: 5815 -/* 4803 */ MCD_OPC_CheckField, 0, 5, 0, 238, 3, // Skip to: 5815 -/* 4809 */ MCD_OPC_Decode, 136, 3, 4, // Opcode: SHUTDOWN -/* 4813 */ MCD_OPC_FilterValue, 129, 1, 26, 0, // Skip to: 4844 -/* 4818 */ MCD_OPC_CheckPredicate, 3, 225, 3, // Skip to: 5815 -/* 4822 */ MCD_OPC_CheckField, 25, 5, 0, 219, 3, // Skip to: 5815 -/* 4828 */ MCD_OPC_CheckField, 14, 5, 0, 213, 3, // Skip to: 5815 -/* 4834 */ MCD_OPC_CheckField, 0, 5, 0, 207, 3, // Skip to: 5815 -/* 4840 */ MCD_OPC_Decode, 137, 3, 4, // Opcode: SIAM -/* 4844 */ MCD_OPC_FilterValue, 144, 2, 14, 0, // Skip to: 4863 -/* 4849 */ MCD_OPC_CheckPredicate, 1, 194, 3, // Skip to: 5815 -/* 4853 */ MCD_OPC_CheckField, 14, 5, 0, 188, 3, // Skip to: 5815 -/* 4859 */ MCD_OPC_Decode, 199, 2, 54, // Opcode: MOVDTOX -/* 4863 */ MCD_OPC_FilterValue, 145, 2, 14, 0, // Skip to: 4882 -/* 4868 */ MCD_OPC_CheckPredicate, 1, 175, 3, // Skip to: 5815 -/* 4872 */ MCD_OPC_CheckField, 14, 5, 0, 169, 3, // Skip to: 5815 -/* 4878 */ MCD_OPC_Decode, 217, 2, 54, // Opcode: MOVSTOUW -/* 4882 */ MCD_OPC_FilterValue, 147, 2, 14, 0, // Skip to: 4901 -/* 4887 */ MCD_OPC_CheckPredicate, 1, 156, 3, // Skip to: 5815 -/* 4891 */ MCD_OPC_CheckField, 14, 5, 0, 150, 3, // Skip to: 5815 -/* 4897 */ MCD_OPC_Decode, 216, 2, 54, // Opcode: MOVSTOSW -/* 4901 */ MCD_OPC_FilterValue, 149, 2, 8, 0, // Skip to: 4914 -/* 4906 */ MCD_OPC_CheckPredicate, 1, 137, 3, // Skip to: 5815 -/* 4910 */ MCD_OPC_Decode, 225, 3, 10, // Opcode: XMULX -/* 4914 */ MCD_OPC_FilterValue, 151, 2, 8, 0, // Skip to: 4927 -/* 4919 */ MCD_OPC_CheckPredicate, 1, 124, 3, // Skip to: 5815 -/* 4923 */ MCD_OPC_Decode, 226, 3, 10, // Opcode: XMULXHI -/* 4927 */ MCD_OPC_FilterValue, 152, 2, 14, 0, // Skip to: 4946 -/* 4932 */ MCD_OPC_CheckPredicate, 1, 111, 3, // Skip to: 5815 -/* 4936 */ MCD_OPC_CheckField, 14, 5, 0, 105, 3, // Skip to: 5815 -/* 4942 */ MCD_OPC_Decode, 221, 2, 55, // Opcode: MOVXTOD -/* 4946 */ MCD_OPC_FilterValue, 153, 2, 14, 0, // Skip to: 4965 -/* 4951 */ MCD_OPC_CheckPredicate, 1, 92, 3, // Skip to: 5815 -/* 4955 */ MCD_OPC_CheckField, 14, 5, 0, 86, 3, // Skip to: 5815 -/* 4961 */ MCD_OPC_Decode, 218, 2, 55, // Opcode: MOVWTOS -/* 4965 */ MCD_OPC_FilterValue, 209, 2, 8, 0, // Skip to: 4978 -/* 4970 */ MCD_OPC_CheckPredicate, 1, 73, 3, // Skip to: 5815 -/* 4974 */ MCD_OPC_Decode, 182, 1, 45, // Opcode: FLCMPS -/* 4978 */ MCD_OPC_FilterValue, 210, 2, 64, 3, // Skip to: 5815 -/* 4983 */ MCD_OPC_CheckPredicate, 1, 60, 3, // Skip to: 5815 -/* 4987 */ MCD_OPC_Decode, 181, 1, 45, // Opcode: FLCMPD -/* 4991 */ MCD_OPC_FilterValue, 56, 25, 0, // Skip to: 5020 -/* 4995 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 4998 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5012 -/* 5002 */ MCD_OPC_CheckField, 5, 8, 0, 39, 3, // Skip to: 5815 -/* 5008 */ MCD_OPC_Decode, 174, 2, 56, // Opcode: JMPLrr -/* 5012 */ MCD_OPC_FilterValue, 1, 31, 3, // Skip to: 5815 -/* 5016 */ MCD_OPC_Decode, 173, 2, 56, // Opcode: JMPLri -/* 5020 */ MCD_OPC_FilterValue, 57, 37, 0, // Skip to: 5061 -/* 5024 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5027 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5047 -/* 5031 */ MCD_OPC_CheckField, 25, 5, 0, 10, 3, // Skip to: 5815 -/* 5037 */ MCD_OPC_CheckField, 5, 8, 0, 4, 3, // Skip to: 5815 -/* 5043 */ MCD_OPC_Decode, 245, 2, 57, // Opcode: RETTrr -/* 5047 */ MCD_OPC_FilterValue, 1, 252, 2, // Skip to: 5815 -/* 5051 */ MCD_OPC_CheckField, 25, 5, 0, 246, 2, // Skip to: 5815 -/* 5057 */ MCD_OPC_Decode, 244, 2, 57, // Opcode: RETTri -/* 5061 */ MCD_OPC_FilterValue, 58, 115, 0, // Skip to: 5180 -/* 5065 */ MCD_OPC_ExtractField, 8, 6, // Inst{13-8} ... -/* 5068 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5088 -/* 5072 */ MCD_OPC_CheckField, 29, 1, 0, 225, 2, // Skip to: 5815 -/* 5078 */ MCD_OPC_CheckField, 5, 3, 0, 219, 2, // Skip to: 5815 -/* 5084 */ MCD_OPC_Decode, 188, 3, 58, // Opcode: TICCrr -/* 5088 */ MCD_OPC_FilterValue, 16, 16, 0, // Skip to: 5108 -/* 5092 */ MCD_OPC_CheckField, 29, 1, 0, 205, 2, // Skip to: 5815 -/* 5098 */ MCD_OPC_CheckField, 5, 3, 0, 199, 2, // Skip to: 5815 -/* 5104 */ MCD_OPC_Decode, 199, 3, 58, // Opcode: TXCCrr -/* 5108 */ MCD_OPC_FilterValue, 32, 54, 0, // Skip to: 5166 -/* 5112 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 5115 */ MCD_OPC_FilterValue, 0, 184, 2, // Skip to: 5815 -/* 5119 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 5122 */ MCD_OPC_FilterValue, 3, 16, 0, // Skip to: 5142 -/* 5126 */ MCD_OPC_CheckField, 25, 4, 0, 30, 0, // Skip to: 5162 -/* 5132 */ MCD_OPC_CheckField, 14, 5, 1, 24, 0, // Skip to: 5162 -/* 5138 */ MCD_OPC_Decode, 181, 3, 4, // Opcode: TA3 -/* 5142 */ MCD_OPC_FilterValue, 5, 16, 0, // Skip to: 5162 -/* 5146 */ MCD_OPC_CheckField, 25, 4, 8, 10, 0, // Skip to: 5162 -/* 5152 */ MCD_OPC_CheckField, 14, 5, 0, 4, 0, // Skip to: 5162 -/* 5158 */ MCD_OPC_Decode, 182, 3, 4, // Opcode: TA5 -/* 5162 */ MCD_OPC_Decode, 187, 3, 59, // Opcode: TICCri -/* 5166 */ MCD_OPC_FilterValue, 48, 133, 2, // Skip to: 5815 -/* 5170 */ MCD_OPC_CheckField, 29, 1, 0, 127, 2, // Skip to: 5815 -/* 5176 */ MCD_OPC_Decode, 198, 3, 59, // Opcode: TXCCri -/* 5180 */ MCD_OPC_FilterValue, 60, 25, 0, // Skip to: 5209 -/* 5184 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5187 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5201 -/* 5191 */ MCD_OPC_CheckField, 5, 8, 0, 106, 2, // Skip to: 5815 -/* 5197 */ MCD_OPC_Decode, 247, 2, 8, // Opcode: SAVErr -/* 5201 */ MCD_OPC_FilterValue, 1, 98, 2, // Skip to: 5815 -/* 5205 */ MCD_OPC_Decode, 246, 2, 9, // Opcode: SAVEri -/* 5209 */ MCD_OPC_FilterValue, 61, 90, 2, // Skip to: 5815 -/* 5213 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5216 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5230 -/* 5220 */ MCD_OPC_CheckField, 5, 8, 0, 77, 2, // Skip to: 5815 -/* 5226 */ MCD_OPC_Decode, 241, 2, 8, // Opcode: RESTORErr -/* 5230 */ MCD_OPC_FilterValue, 1, 69, 2, // Skip to: 5815 -/* 5234 */ MCD_OPC_Decode, 240, 2, 9, // Opcode: RESTOREri -/* 5238 */ MCD_OPC_FilterValue, 3, 61, 2, // Skip to: 5815 -/* 5242 */ MCD_OPC_ExtractField, 19, 6, // Inst{24-19} ... -/* 5245 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 5274 -/* 5249 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5252 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5266 -/* 5256 */ MCD_OPC_CheckField, 5, 8, 0, 41, 2, // Skip to: 5815 -/* 5262 */ MCD_OPC_Decode, 194, 2, 60, // Opcode: LDrr -/* 5266 */ MCD_OPC_FilterValue, 1, 33, 2, // Skip to: 5815 -/* 5270 */ MCD_OPC_Decode, 193, 2, 60, // Opcode: LDri -/* 5274 */ MCD_OPC_FilterValue, 1, 25, 0, // Skip to: 5303 -/* 5278 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5281 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5295 -/* 5285 */ MCD_OPC_CheckField, 5, 8, 0, 12, 2, // Skip to: 5815 -/* 5291 */ MCD_OPC_Decode, 188, 2, 60, // Opcode: LDUBrr -/* 5295 */ MCD_OPC_FilterValue, 1, 4, 2, // Skip to: 5815 -/* 5299 */ MCD_OPC_Decode, 187, 2, 60, // Opcode: LDUBri -/* 5303 */ MCD_OPC_FilterValue, 2, 25, 0, // Skip to: 5332 -/* 5307 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5310 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5324 -/* 5314 */ MCD_OPC_CheckField, 5, 8, 0, 239, 1, // Skip to: 5815 -/* 5320 */ MCD_OPC_Decode, 190, 2, 60, // Opcode: LDUHrr -/* 5324 */ MCD_OPC_FilterValue, 1, 231, 1, // Skip to: 5815 -/* 5328 */ MCD_OPC_Decode, 189, 2, 60, // Opcode: LDUHri -/* 5332 */ MCD_OPC_FilterValue, 4, 25, 0, // Skip to: 5361 -/* 5336 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5339 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5353 -/* 5343 */ MCD_OPC_CheckField, 5, 8, 0, 210, 1, // Skip to: 5815 -/* 5349 */ MCD_OPC_Decode, 168, 3, 61, // Opcode: STrr -/* 5353 */ MCD_OPC_FilterValue, 1, 202, 1, // Skip to: 5815 -/* 5357 */ MCD_OPC_Decode, 167, 3, 61, // Opcode: STri -/* 5361 */ MCD_OPC_FilterValue, 5, 25, 0, // Skip to: 5390 -/* 5365 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5368 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5382 -/* 5372 */ MCD_OPC_CheckField, 5, 8, 0, 181, 1, // Skip to: 5815 -/* 5378 */ MCD_OPC_Decode, 156, 3, 61, // Opcode: STBrr -/* 5382 */ MCD_OPC_FilterValue, 1, 173, 1, // Skip to: 5815 -/* 5386 */ MCD_OPC_Decode, 155, 3, 61, // Opcode: STBri -/* 5390 */ MCD_OPC_FilterValue, 6, 25, 0, // Skip to: 5419 -/* 5394 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5397 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5411 -/* 5401 */ MCD_OPC_CheckField, 5, 8, 0, 152, 1, // Skip to: 5815 -/* 5407 */ MCD_OPC_Decode, 162, 3, 61, // Opcode: STHrr -/* 5411 */ MCD_OPC_FilterValue, 1, 144, 1, // Skip to: 5815 -/* 5415 */ MCD_OPC_Decode, 161, 3, 61, // Opcode: STHri -/* 5419 */ MCD_OPC_FilterValue, 8, 25, 0, // Skip to: 5448 -/* 5423 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5426 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5440 -/* 5430 */ MCD_OPC_CheckField, 5, 8, 0, 123, 1, // Skip to: 5815 -/* 5436 */ MCD_OPC_Decode, 186, 2, 60, // Opcode: LDSWrr -/* 5440 */ MCD_OPC_FilterValue, 1, 115, 1, // Skip to: 5815 -/* 5444 */ MCD_OPC_Decode, 185, 2, 60, // Opcode: LDSWri -/* 5448 */ MCD_OPC_FilterValue, 9, 25, 0, // Skip to: 5477 -/* 5452 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5455 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5469 -/* 5459 */ MCD_OPC_CheckField, 5, 8, 0, 94, 1, // Skip to: 5815 -/* 5465 */ MCD_OPC_Decode, 182, 2, 60, // Opcode: LDSBrr -/* 5469 */ MCD_OPC_FilterValue, 1, 86, 1, // Skip to: 5815 -/* 5473 */ MCD_OPC_Decode, 181, 2, 60, // Opcode: LDSBri -/* 5477 */ MCD_OPC_FilterValue, 10, 25, 0, // Skip to: 5506 -/* 5481 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5498 -/* 5488 */ MCD_OPC_CheckField, 5, 8, 0, 65, 1, // Skip to: 5815 -/* 5494 */ MCD_OPC_Decode, 184, 2, 60, // Opcode: LDSHrr -/* 5498 */ MCD_OPC_FilterValue, 1, 57, 1, // Skip to: 5815 -/* 5502 */ MCD_OPC_Decode, 183, 2, 60, // Opcode: LDSHri -/* 5506 */ MCD_OPC_FilterValue, 11, 25, 0, // Skip to: 5535 -/* 5510 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5513 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5527 -/* 5517 */ MCD_OPC_CheckField, 5, 8, 0, 36, 1, // Skip to: 5815 -/* 5523 */ MCD_OPC_Decode, 192, 2, 60, // Opcode: LDXrr -/* 5527 */ MCD_OPC_FilterValue, 1, 28, 1, // Skip to: 5815 -/* 5531 */ MCD_OPC_Decode, 191, 2, 60, // Opcode: LDXri -/* 5535 */ MCD_OPC_FilterValue, 14, 25, 0, // Skip to: 5564 -/* 5539 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5542 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5556 -/* 5546 */ MCD_OPC_CheckField, 5, 8, 0, 7, 1, // Skip to: 5815 -/* 5552 */ MCD_OPC_Decode, 166, 3, 61, // Opcode: STXrr -/* 5556 */ MCD_OPC_FilterValue, 1, 255, 0, // Skip to: 5815 -/* 5560 */ MCD_OPC_Decode, 165, 3, 61, // Opcode: STXri -/* 5564 */ MCD_OPC_FilterValue, 15, 25, 0, // Skip to: 5593 -/* 5568 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5571 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5585 -/* 5575 */ MCD_OPC_CheckField, 5, 8, 0, 234, 0, // Skip to: 5815 -/* 5581 */ MCD_OPC_Decode, 180, 3, 62, // Opcode: SWAPrr -/* 5585 */ MCD_OPC_FilterValue, 1, 226, 0, // Skip to: 5815 -/* 5589 */ MCD_OPC_Decode, 179, 3, 62, // Opcode: SWAPri -/* 5593 */ MCD_OPC_FilterValue, 32, 25, 0, // Skip to: 5622 -/* 5597 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5600 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5614 -/* 5604 */ MCD_OPC_CheckField, 5, 8, 0, 205, 0, // Skip to: 5815 -/* 5610 */ MCD_OPC_Decode, 178, 2, 63, // Opcode: LDFrr -/* 5614 */ MCD_OPC_FilterValue, 1, 197, 0, // Skip to: 5815 -/* 5618 */ MCD_OPC_Decode, 177, 2, 63, // Opcode: LDFri -/* 5622 */ MCD_OPC_FilterValue, 34, 33, 0, // Skip to: 5659 -/* 5626 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5629 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5647 -/* 5633 */ MCD_OPC_CheckPredicate, 0, 178, 0, // Skip to: 5815 -/* 5637 */ MCD_OPC_CheckField, 5, 8, 0, 172, 0, // Skip to: 5815 -/* 5643 */ MCD_OPC_Decode, 180, 2, 64, // Opcode: LDQFrr -/* 5647 */ MCD_OPC_FilterValue, 1, 164, 0, // Skip to: 5815 -/* 5651 */ MCD_OPC_CheckPredicate, 0, 160, 0, // Skip to: 5815 -/* 5655 */ MCD_OPC_Decode, 179, 2, 64, // Opcode: LDQFri -/* 5659 */ MCD_OPC_FilterValue, 35, 25, 0, // Skip to: 5688 -/* 5663 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5666 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5680 -/* 5670 */ MCD_OPC_CheckField, 5, 8, 0, 139, 0, // Skip to: 5815 -/* 5676 */ MCD_OPC_Decode, 176, 2, 65, // Opcode: LDDFrr -/* 5680 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 5815 -/* 5684 */ MCD_OPC_Decode, 175, 2, 65, // Opcode: LDDFri -/* 5688 */ MCD_OPC_FilterValue, 36, 25, 0, // Skip to: 5717 -/* 5692 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5695 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5709 -/* 5699 */ MCD_OPC_CheckField, 5, 8, 0, 110, 0, // Skip to: 5815 -/* 5705 */ MCD_OPC_Decode, 160, 3, 66, // Opcode: STFrr -/* 5709 */ MCD_OPC_FilterValue, 1, 102, 0, // Skip to: 5815 -/* 5713 */ MCD_OPC_Decode, 159, 3, 66, // Opcode: STFri -/* 5717 */ MCD_OPC_FilterValue, 38, 33, 0, // Skip to: 5754 -/* 5721 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5724 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5742 -/* 5728 */ MCD_OPC_CheckPredicate, 0, 83, 0, // Skip to: 5815 -/* 5732 */ MCD_OPC_CheckField, 5, 8, 0, 77, 0, // Skip to: 5815 -/* 5738 */ MCD_OPC_Decode, 164, 3, 67, // Opcode: STQFrr -/* 5742 */ MCD_OPC_FilterValue, 1, 69, 0, // Skip to: 5815 -/* 5746 */ MCD_OPC_CheckPredicate, 0, 65, 0, // Skip to: 5815 -/* 5750 */ MCD_OPC_Decode, 163, 3, 67, // Opcode: STQFri -/* 5754 */ MCD_OPC_FilterValue, 39, 25, 0, // Skip to: 5783 -/* 5758 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 5761 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5775 -/* 5765 */ MCD_OPC_CheckField, 5, 8, 0, 44, 0, // Skip to: 5815 -/* 5771 */ MCD_OPC_Decode, 158, 3, 68, // Opcode: STDFrr -/* 5775 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 5815 -/* 5779 */ MCD_OPC_Decode, 157, 3, 68, // Opcode: STDFri -/* 5783 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 5801 -/* 5787 */ MCD_OPC_CheckPredicate, 0, 24, 0, // Skip to: 5815 -/* 5791 */ MCD_OPC_CheckField, 5, 9, 128, 1, 17, 0, // Skip to: 5815 -/* 5798 */ MCD_OPC_Decode, 120, 69, // Opcode: CASrr -/* 5801 */ MCD_OPC_FilterValue, 62, 10, 0, // Skip to: 5815 -/* 5805 */ MCD_OPC_CheckField, 5, 9, 128, 1, 3, 0, // Skip to: 5815 -/* 5812 */ MCD_OPC_Decode, 119, 70, // Opcode: CASXrr -/* 5815 */ MCD_OPC_Fail, - 0 -}; - -static bool getbool(uint64_t b) -{ - return b != 0; -} + /* 0 */ MCD_OPC_ExtractField, + 30, + 2, // Inst{31-30} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 155, + 2, + 0, // Skip to: 675 + /* 8 */ MCD_OPC_ExtractField, + 22, + 3, // Inst{24-22} ... + /* 11 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 27 + /* 16 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 97, + 31, + 0, // Skip to: 8056 + /* 23 */ MCD_OPC_Decode, + 229, + 5, + 0, // Opcode: UNIMP + /* 27 */ MCD_OPC_FilterValue, + 1, + 127, + 0, + 0, // Skip to: 159 + /* 32 */ MCD_OPC_ExtractField, + 19, + 3, // Inst{21-19} ... + /* 35 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 71 + /* 40 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 43 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 57 + /* 48 */ MCD_OPC_CheckPredicate, + 0, + 67, + 31, + 0, // Skip to: 8056 + /* 53 */ MCD_OPC_Decode, + 175, + 2, + 1, // Opcode: BPICCNT + /* 57 */ MCD_OPC_FilterValue, + 1, + 58, + 31, + 0, // Skip to: 8056 + /* 62 */ MCD_OPC_CheckPredicate, + 0, + 53, + 31, + 0, // Skip to: 8056 + /* 67 */ MCD_OPC_Decode, + 174, + 2, + 1, // Opcode: BPICCANT + /* 71 */ MCD_OPC_FilterValue, + 1, + 31, + 0, + 0, // Skip to: 107 + /* 76 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 79 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 93 + /* 84 */ MCD_OPC_CheckPredicate, + 0, + 31, + 31, + 0, // Skip to: 8056 + /* 89 */ MCD_OPC_Decode, + 172, + 2, + 1, // Opcode: BPICC + /* 93 */ MCD_OPC_FilterValue, + 1, + 22, + 31, + 0, // Skip to: 8056 + /* 98 */ MCD_OPC_CheckPredicate, + 0, + 17, + 31, + 0, // Skip to: 8056 + /* 103 */ MCD_OPC_Decode, + 173, + 2, + 1, // Opcode: BPICCA + /* 107 */ MCD_OPC_FilterValue, + 4, + 21, + 0, + 0, // Skip to: 133 + /* 112 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 115 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 124 + /* 120 */ MCD_OPC_Decode, + 191, + 2, + 1, // Opcode: BPXCCNT + /* 124 */ MCD_OPC_FilterValue, + 1, + 247, + 30, + 0, // Skip to: 8056 + /* 129 */ MCD_OPC_Decode, + 190, + 2, + 1, // Opcode: BPXCCANT + /* 133 */ MCD_OPC_FilterValue, + 5, + 238, + 30, + 0, // Skip to: 8056 + /* 138 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 141 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 150 + /* 146 */ MCD_OPC_Decode, + 188, + 2, + 1, // Opcode: BPXCC + /* 150 */ MCD_OPC_FilterValue, + 1, + 221, + 30, + 0, // Skip to: 8056 + /* 155 */ MCD_OPC_Decode, + 189, + 2, + 1, // Opcode: BPXCCA + /* 159 */ MCD_OPC_FilterValue, + 2, + 32, + 0, + 0, // Skip to: 196 + /* 164 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 167 */ MCD_OPC_FilterValue, + 0, + 15, + 0, + 0, // Skip to: 187 + /* 172 */ MCD_OPC_CheckField, + 25, + 4, + 8, + 4, + 0, + 0, // Skip to: 183 + /* 179 */ MCD_OPC_Decode, + 154, + 2, + 0, // Opcode: BA + /* 183 */ MCD_OPC_Decode, + 155, + 2, + 2, // Opcode: BCOND + /* 187 */ MCD_OPC_FilterValue, + 1, + 184, + 30, + 0, // Skip to: 8056 + /* 192 */ MCD_OPC_Decode, + 156, + 2, + 2, // Opcode: BCONDA + /* 196 */ MCD_OPC_FilterValue, + 3, + 59, + 1, + 0, // Skip to: 516 + /* 201 */ MCD_OPC_ExtractField, + 25, + 5, // Inst{29-25} ... + /* 204 */ MCD_OPC_FilterValue, + 1, + 21, + 0, + 0, // Skip to: 230 + /* 209 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 212 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 221 + /* 217 */ MCD_OPC_Decode, + 194, + 2, + 3, // Opcode: BPZnapn + /* 221 */ MCD_OPC_FilterValue, + 1, + 150, + 30, + 0, // Skip to: 8056 + /* 226 */ MCD_OPC_Decode, + 195, + 2, + 3, // Opcode: BPZnapt + /* 230 */ MCD_OPC_FilterValue, + 2, + 21, + 0, + 0, // Skip to: 256 + /* 235 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 238 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 247 + /* 243 */ MCD_OPC_Decode, + 178, + 2, + 3, // Opcode: BPLEZnapn + /* 247 */ MCD_OPC_FilterValue, + 1, + 124, + 30, + 0, // Skip to: 8056 + /* 252 */ MCD_OPC_Decode, + 179, + 2, + 3, // Opcode: BPLEZnapt + /* 256 */ MCD_OPC_FilterValue, + 3, + 21, + 0, + 0, // Skip to: 282 + /* 261 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 264 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 273 + /* 269 */ MCD_OPC_Decode, + 182, + 2, + 3, // Opcode: BPLZnapn + /* 273 */ MCD_OPC_FilterValue, + 1, + 98, + 30, + 0, // Skip to: 8056 + /* 278 */ MCD_OPC_Decode, + 183, + 2, + 3, // Opcode: BPLZnapt + /* 282 */ MCD_OPC_FilterValue, + 5, + 21, + 0, + 0, // Skip to: 308 + /* 287 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 290 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 299 + /* 295 */ MCD_OPC_Decode, + 186, + 2, + 3, // Opcode: BPNZnapn + /* 299 */ MCD_OPC_FilterValue, + 1, + 72, + 30, + 0, // Skip to: 8056 + /* 304 */ MCD_OPC_Decode, + 187, + 2, + 3, // Opcode: BPNZnapt + /* 308 */ MCD_OPC_FilterValue, + 6, + 21, + 0, + 0, // Skip to: 334 + /* 313 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 316 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 325 + /* 321 */ MCD_OPC_Decode, + 170, + 2, + 3, // Opcode: BPGZnapn + /* 325 */ MCD_OPC_FilterValue, + 1, + 46, + 30, + 0, // Skip to: 8056 + /* 330 */ MCD_OPC_Decode, + 171, + 2, + 3, // Opcode: BPGZnapt + /* 334 */ MCD_OPC_FilterValue, + 7, + 21, + 0, + 0, // Skip to: 360 + /* 339 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 342 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 351 + /* 347 */ MCD_OPC_Decode, + 166, + 2, + 3, // Opcode: BPGEZnapn + /* 351 */ MCD_OPC_FilterValue, + 1, + 20, + 30, + 0, // Skip to: 8056 + /* 356 */ MCD_OPC_Decode, + 167, + 2, + 3, // Opcode: BPGEZnapt + /* 360 */ MCD_OPC_FilterValue, + 17, + 21, + 0, + 0, // Skip to: 386 + /* 365 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 368 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 377 + /* 373 */ MCD_OPC_Decode, + 192, + 2, + 3, // Opcode: BPZapn + /* 377 */ MCD_OPC_FilterValue, + 1, + 250, + 29, + 0, // Skip to: 8056 + /* 382 */ MCD_OPC_Decode, + 193, + 2, + 3, // Opcode: BPZapt + /* 386 */ MCD_OPC_FilterValue, + 18, + 21, + 0, + 0, // Skip to: 412 + /* 391 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 394 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 403 + /* 399 */ MCD_OPC_Decode, + 176, + 2, + 3, // Opcode: BPLEZapn + /* 403 */ MCD_OPC_FilterValue, + 1, + 224, + 29, + 0, // Skip to: 8056 + /* 408 */ MCD_OPC_Decode, + 177, + 2, + 3, // Opcode: BPLEZapt + /* 412 */ MCD_OPC_FilterValue, + 19, + 21, + 0, + 0, // Skip to: 438 + /* 417 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 420 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 429 + /* 425 */ MCD_OPC_Decode, + 180, + 2, + 3, // Opcode: BPLZapn + /* 429 */ MCD_OPC_FilterValue, + 1, + 198, + 29, + 0, // Skip to: 8056 + /* 434 */ MCD_OPC_Decode, + 181, + 2, + 3, // Opcode: BPLZapt + /* 438 */ MCD_OPC_FilterValue, + 21, + 21, + 0, + 0, // Skip to: 464 + /* 443 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 446 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 455 + /* 451 */ MCD_OPC_Decode, + 184, + 2, + 3, // Opcode: BPNZapn + /* 455 */ MCD_OPC_FilterValue, + 1, + 172, + 29, + 0, // Skip to: 8056 + /* 460 */ MCD_OPC_Decode, + 185, + 2, + 3, // Opcode: BPNZapt + /* 464 */ MCD_OPC_FilterValue, + 22, + 21, + 0, + 0, // Skip to: 490 + /* 469 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 472 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 481 + /* 477 */ MCD_OPC_Decode, + 168, + 2, + 3, // Opcode: BPGZapn + /* 481 */ MCD_OPC_FilterValue, + 1, + 146, + 29, + 0, // Skip to: 8056 + /* 486 */ MCD_OPC_Decode, + 169, + 2, + 3, // Opcode: BPGZapt + /* 490 */ MCD_OPC_FilterValue, + 23, + 137, + 29, + 0, // Skip to: 8056 + /* 495 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 498 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 507 + /* 503 */ MCD_OPC_Decode, + 164, + 2, + 3, // Opcode: BPGEZapn + /* 507 */ MCD_OPC_FilterValue, + 1, + 120, + 29, + 0, // Skip to: 8056 + /* 512 */ MCD_OPC_Decode, + 165, + 2, + 3, // Opcode: BPGEZapt + /* 516 */ MCD_OPC_FilterValue, + 4, + 22, + 0, + 0, // Skip to: 543 + /* 521 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 11, + 0, + 0, // Skip to: 539 + /* 528 */ MCD_OPC_CheckField, + 0, + 22, + 0, + 4, + 0, + 0, // Skip to: 539 + /* 535 */ MCD_OPC_Decode, + 209, + 4, + 4, // Opcode: NOP + /* 539 */ MCD_OPC_Decode, + 249, + 4, + 5, // Opcode: SETHIi + /* 543 */ MCD_OPC_FilterValue, + 5, + 75, + 0, + 0, // Skip to: 623 + /* 548 */ MCD_OPC_ExtractField, + 19, + 1, // Inst{19} ... + /* 551 */ MCD_OPC_FilterValue, + 0, + 31, + 0, + 0, // Skip to: 587 + /* 556 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 559 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 573 + /* 564 */ MCD_OPC_CheckPredicate, + 0, + 63, + 29, + 0, // Skip to: 8056 + /* 569 */ MCD_OPC_Decode, + 163, + 2, + 6, // Opcode: BPFCCNT + /* 573 */ MCD_OPC_FilterValue, + 1, + 54, + 29, + 0, // Skip to: 8056 + /* 578 */ MCD_OPC_CheckPredicate, + 0, + 49, + 29, + 0, // Skip to: 8056 + /* 583 */ MCD_OPC_Decode, + 162, + 2, + 6, // Opcode: BPFCCANT + /* 587 */ MCD_OPC_FilterValue, + 1, + 40, + 29, + 0, // Skip to: 8056 + /* 592 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 595 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 609 + /* 600 */ MCD_OPC_CheckPredicate, + 0, + 27, + 29, + 0, // Skip to: 8056 + /* 605 */ MCD_OPC_Decode, + 160, + 2, + 6, // Opcode: BPFCC + /* 609 */ MCD_OPC_FilterValue, + 1, + 18, + 29, + 0, // Skip to: 8056 + /* 614 */ MCD_OPC_CheckPredicate, + 0, + 13, + 29, + 0, // Skip to: 8056 + /* 619 */ MCD_OPC_Decode, + 161, + 2, + 6, // Opcode: BPFCCA + /* 623 */ MCD_OPC_FilterValue, + 6, + 21, + 0, + 0, // Skip to: 649 + /* 628 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 631 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 640 + /* 636 */ MCD_OPC_Decode, + 236, + 2, + 2, // Opcode: FBCOND + /* 640 */ MCD_OPC_FilterValue, + 1, + 243, + 28, + 0, // Skip to: 8056 + /* 645 */ MCD_OPC_Decode, + 237, + 2, + 2, // Opcode: FBCONDA + /* 649 */ MCD_OPC_FilterValue, + 7, + 234, + 28, + 0, // Skip to: 8056 + /* 654 */ MCD_OPC_ExtractField, + 29, + 1, // Inst{29} ... + /* 657 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 666 + /* 662 */ MCD_OPC_Decode, + 204, + 2, + 2, // Opcode: CBCOND + /* 666 */ MCD_OPC_FilterValue, + 1, + 217, + 28, + 0, // Skip to: 8056 + /* 671 */ MCD_OPC_Decode, + 205, + 2, + 2, // Opcode: CBCONDA + /* 675 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 684 + /* 680 */ MCD_OPC_Decode, + 197, + 2, + 7, // Opcode: CALL + /* 684 */ MCD_OPC_FilterValue, + 2, + 188, + 22, + 0, // Skip to: 6509 + /* 689 */ MCD_OPC_ExtractField, + 19, + 6, // Inst{24-19} ... + /* 692 */ MCD_OPC_FilterValue, + 0, + 28, + 0, + 0, // Skip to: 725 + /* 697 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 700 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 716 + /* 705 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 176, + 28, + 0, // Skip to: 8056 + /* 712 */ MCD_OPC_Decode, + 137, + 2, + 8, // Opcode: ADDrr + /* 716 */ MCD_OPC_FilterValue, + 1, + 167, + 28, + 0, // Skip to: 8056 + /* 721 */ MCD_OPC_Decode, + 136, + 2, + 9, // Opcode: ADDri + /* 725 */ MCD_OPC_FilterValue, + 1, + 28, + 0, + 0, // Skip to: 758 + /* 730 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 733 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 749 + /* 738 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 143, + 28, + 0, // Skip to: 8056 + /* 745 */ MCD_OPC_Decode, + 150, + 2, + 8, // Opcode: ANDrr + /* 749 */ MCD_OPC_FilterValue, + 1, + 134, + 28, + 0, // Skip to: 8056 + /* 754 */ MCD_OPC_Decode, + 149, + 2, + 9, // Opcode: ANDri + /* 758 */ MCD_OPC_FilterValue, + 2, + 28, + 0, + 0, // Skip to: 791 + /* 763 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 766 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 782 + /* 771 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 110, + 28, + 0, // Skip to: 8056 + /* 778 */ MCD_OPC_Decode, + 220, + 4, + 8, // Opcode: ORrr + /* 782 */ MCD_OPC_FilterValue, + 1, + 101, + 28, + 0, // Skip to: 8056 + /* 787 */ MCD_OPC_Decode, + 219, + 4, + 9, // Opcode: ORri + /* 791 */ MCD_OPC_FilterValue, + 3, + 28, + 0, + 0, // Skip to: 824 + /* 796 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 799 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 815 + /* 804 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 77, + 28, + 0, // Skip to: 8056 + /* 811 */ MCD_OPC_Decode, + 135, + 6, + 8, // Opcode: XORrr + /* 815 */ MCD_OPC_FilterValue, + 1, + 68, + 28, + 0, // Skip to: 8056 + /* 820 */ MCD_OPC_Decode, + 134, + 6, + 9, // Opcode: XORri + /* 824 */ MCD_OPC_FilterValue, + 4, + 28, + 0, + 0, // Skip to: 857 + /* 829 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 832 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 848 + /* 837 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 44, + 28, + 0, // Skip to: 8056 + /* 844 */ MCD_OPC_Decode, + 190, + 5, + 8, // Opcode: SUBrr + /* 848 */ MCD_OPC_FilterValue, + 1, + 35, + 28, + 0, // Skip to: 8056 + /* 853 */ MCD_OPC_Decode, + 189, + 5, + 9, // Opcode: SUBri + /* 857 */ MCD_OPC_FilterValue, + 5, + 28, + 0, + 0, // Skip to: 890 + /* 862 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 865 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 881 + /* 870 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 11, + 28, + 0, // Skip to: 8056 + /* 877 */ MCD_OPC_Decode, + 145, + 2, + 8, // Opcode: ANDNrr + /* 881 */ MCD_OPC_FilterValue, + 1, + 2, + 28, + 0, // Skip to: 8056 + /* 886 */ MCD_OPC_Decode, + 144, + 2, + 9, // Opcode: ANDNri + /* 890 */ MCD_OPC_FilterValue, + 6, + 28, + 0, + 0, // Skip to: 923 + /* 895 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 898 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 914 + /* 903 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 234, + 27, + 0, // Skip to: 8056 + /* 910 */ MCD_OPC_Decode, + 215, + 4, + 8, // Opcode: ORNrr + /* 914 */ MCD_OPC_FilterValue, + 1, + 225, + 27, + 0, // Skip to: 8056 + /* 919 */ MCD_OPC_Decode, + 214, + 4, + 9, // Opcode: ORNri + /* 923 */ MCD_OPC_FilterValue, + 7, + 28, + 0, + 0, // Skip to: 956 + /* 928 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 931 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 947 + /* 936 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 201, + 27, + 0, // Skip to: 8056 + /* 943 */ MCD_OPC_Decode, + 129, + 6, + 8, // Opcode: XNORrr + /* 947 */ MCD_OPC_FilterValue, + 1, + 192, + 27, + 0, // Skip to: 8056 + /* 952 */ MCD_OPC_Decode, + 128, + 6, + 9, // Opcode: XNORri + /* 956 */ MCD_OPC_FilterValue, + 8, + 28, + 0, + 0, // Skip to: 989 + /* 961 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 964 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 980 + /* 969 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 168, + 27, + 0, // Skip to: 8056 + /* 976 */ MCD_OPC_Decode, + 129, + 2, + 8, // Opcode: ADDCrr + /* 980 */ MCD_OPC_FilterValue, + 1, + 159, + 27, + 0, // Skip to: 8056 + /* 985 */ MCD_OPC_Decode, + 128, + 2, + 9, // Opcode: ADDCri + /* 989 */ MCD_OPC_FilterValue, + 9, + 28, + 0, + 0, // Skip to: 1022 + /* 994 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 997 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1013 + /* 1002 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 135, + 27, + 0, // Skip to: 8056 + /* 1009 */ MCD_OPC_Decode, + 208, + 4, + 10, // Opcode: MULXrr + /* 1013 */ MCD_OPC_FilterValue, + 1, + 126, + 27, + 0, // Skip to: 8056 + /* 1018 */ MCD_OPC_Decode, + 207, + 4, + 11, // Opcode: MULXri + /* 1022 */ MCD_OPC_FilterValue, + 10, + 28, + 0, + 0, // Skip to: 1055 + /* 1027 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1030 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1046 + /* 1035 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 102, + 27, + 0, // Skip to: 8056 + /* 1042 */ MCD_OPC_Decode, + 228, + 5, + 8, // Opcode: UMULrr + /* 1046 */ MCD_OPC_FilterValue, + 1, + 93, + 27, + 0, // Skip to: 8056 + /* 1051 */ MCD_OPC_Decode, + 227, + 5, + 9, // Opcode: UMULri + /* 1055 */ MCD_OPC_FilterValue, + 11, + 28, + 0, + 0, // Skip to: 1088 + /* 1060 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1063 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1079 + /* 1068 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 69, + 27, + 0, // Skip to: 8056 + /* 1075 */ MCD_OPC_Decode, + 134, + 5, + 8, // Opcode: SMULrr + /* 1079 */ MCD_OPC_FilterValue, + 1, + 60, + 27, + 0, // Skip to: 8056 + /* 1084 */ MCD_OPC_Decode, + 133, + 5, + 9, // Opcode: SMULri + /* 1088 */ MCD_OPC_FilterValue, + 12, + 28, + 0, + 0, // Skip to: 1121 + /* 1093 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1096 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1112 + /* 1101 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 36, + 27, + 0, // Skip to: 8056 + /* 1108 */ MCD_OPC_Decode, + 184, + 5, + 8, // Opcode: SUBCrr + /* 1112 */ MCD_OPC_FilterValue, + 1, + 27, + 27, + 0, // Skip to: 8056 + /* 1117 */ MCD_OPC_Decode, + 183, + 5, + 9, // Opcode: SUBCri + /* 1121 */ MCD_OPC_FilterValue, + 13, + 28, + 0, + 0, // Skip to: 1154 + /* 1126 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1129 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1145 + /* 1134 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 3, + 27, + 0, // Skip to: 8056 + /* 1141 */ MCD_OPC_Decode, + 219, + 5, + 10, // Opcode: UDIVXrr + /* 1145 */ MCD_OPC_FilterValue, + 1, + 250, + 26, + 0, // Skip to: 8056 + /* 1150 */ MCD_OPC_Decode, + 218, + 5, + 11, // Opcode: UDIVXri + /* 1154 */ MCD_OPC_FilterValue, + 14, + 28, + 0, + 0, // Skip to: 1187 + /* 1159 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1162 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1178 + /* 1167 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 226, + 26, + 0, // Skip to: 8056 + /* 1174 */ MCD_OPC_Decode, + 221, + 5, + 8, // Opcode: UDIVrr + /* 1178 */ MCD_OPC_FilterValue, + 1, + 217, + 26, + 0, // Skip to: 8056 + /* 1183 */ MCD_OPC_Decode, + 220, + 5, + 9, // Opcode: UDIVri + /* 1187 */ MCD_OPC_FilterValue, + 15, + 28, + 0, + 0, // Skip to: 1220 + /* 1192 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1195 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1211 + /* 1200 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 193, + 26, + 0, // Skip to: 8056 + /* 1207 */ MCD_OPC_Decode, + 247, + 4, + 8, // Opcode: SDIVrr + /* 1211 */ MCD_OPC_FilterValue, + 1, + 184, + 26, + 0, // Skip to: 8056 + /* 1216 */ MCD_OPC_Decode, + 246, + 4, + 9, // Opcode: SDIVri + /* 1220 */ MCD_OPC_FilterValue, + 16, + 28, + 0, + 0, // Skip to: 1253 + /* 1225 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1228 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1244 + /* 1233 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 160, + 26, + 0, // Skip to: 8056 + /* 1240 */ MCD_OPC_Decode, + 255, + 1, + 8, // Opcode: ADDCCrr + /* 1244 */ MCD_OPC_FilterValue, + 1, + 151, + 26, + 0, // Skip to: 8056 + /* 1249 */ MCD_OPC_Decode, + 254, + 1, + 9, // Opcode: ADDCCri + /* 1253 */ MCD_OPC_FilterValue, + 17, + 28, + 0, + 0, // Skip to: 1286 + /* 1258 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1261 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1277 + /* 1266 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 127, + 26, + 0, // Skip to: 8056 + /* 1273 */ MCD_OPC_Decode, + 141, + 2, + 8, // Opcode: ANDCCrr + /* 1277 */ MCD_OPC_FilterValue, + 1, + 118, + 26, + 0, // Skip to: 8056 + /* 1282 */ MCD_OPC_Decode, + 140, + 2, + 9, // Opcode: ANDCCri + /* 1286 */ MCD_OPC_FilterValue, + 18, + 28, + 0, + 0, // Skip to: 1319 + /* 1291 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1294 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1310 + /* 1299 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 94, + 26, + 0, // Skip to: 8056 + /* 1306 */ MCD_OPC_Decode, + 211, + 4, + 8, // Opcode: ORCCrr + /* 1310 */ MCD_OPC_FilterValue, + 1, + 85, + 26, + 0, // Skip to: 8056 + /* 1315 */ MCD_OPC_Decode, + 210, + 4, + 9, // Opcode: ORCCri + /* 1319 */ MCD_OPC_FilterValue, + 19, + 28, + 0, + 0, // Skip to: 1352 + /* 1324 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1327 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1343 + /* 1332 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 61, + 26, + 0, // Skip to: 8056 + /* 1339 */ MCD_OPC_Decode, + 131, + 6, + 8, // Opcode: XORCCrr + /* 1343 */ MCD_OPC_FilterValue, + 1, + 52, + 26, + 0, // Skip to: 8056 + /* 1348 */ MCD_OPC_Decode, + 130, + 6, + 9, // Opcode: XORCCri + /* 1352 */ MCD_OPC_FilterValue, + 20, + 51, + 0, + 0, // Skip to: 1408 + /* 1357 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1360 */ MCD_OPC_FilterValue, + 0, + 23, + 0, + 0, // Skip to: 1388 + /* 1365 */ MCD_OPC_ExtractField, + 5, + 8, // Inst{12-5} ... + /* 1368 */ MCD_OPC_FilterValue, + 0, + 27, + 26, + 0, // Skip to: 8056 + /* 1373 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 4, + 0, + 0, // Skip to: 1384 + /* 1380 */ MCD_OPC_Decode, + 210, + 2, + 12, // Opcode: CMPrr + /* 1384 */ MCD_OPC_Decode, + 182, + 5, + 8, // Opcode: SUBCCrr + /* 1388 */ MCD_OPC_FilterValue, + 1, + 7, + 26, + 0, // Skip to: 8056 + /* 1393 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 4, + 0, + 0, // Skip to: 1404 + /* 1400 */ MCD_OPC_Decode, + 209, + 2, + 13, // Opcode: CMPri + /* 1404 */ MCD_OPC_Decode, + 181, + 5, + 9, // Opcode: SUBCCri + /* 1408 */ MCD_OPC_FilterValue, + 21, + 28, + 0, + 0, // Skip to: 1441 + /* 1413 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1416 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1432 + /* 1421 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 228, + 25, + 0, // Skip to: 8056 + /* 1428 */ MCD_OPC_Decode, + 143, + 2, + 8, // Opcode: ANDNCCrr + /* 1432 */ MCD_OPC_FilterValue, + 1, + 219, + 25, + 0, // Skip to: 8056 + /* 1437 */ MCD_OPC_Decode, + 142, + 2, + 9, // Opcode: ANDNCCri + /* 1441 */ MCD_OPC_FilterValue, + 22, + 28, + 0, + 0, // Skip to: 1474 + /* 1446 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1449 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1465 + /* 1454 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 195, + 25, + 0, // Skip to: 8056 + /* 1461 */ MCD_OPC_Decode, + 213, + 4, + 8, // Opcode: ORNCCrr + /* 1465 */ MCD_OPC_FilterValue, + 1, + 186, + 25, + 0, // Skip to: 8056 + /* 1470 */ MCD_OPC_Decode, + 212, + 4, + 9, // Opcode: ORNCCri + /* 1474 */ MCD_OPC_FilterValue, + 23, + 28, + 0, + 0, // Skip to: 1507 + /* 1479 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1482 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1498 + /* 1487 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 162, + 25, + 0, // Skip to: 8056 + /* 1494 */ MCD_OPC_Decode, + 254, + 5, + 8, // Opcode: XNORCCrr + /* 1498 */ MCD_OPC_FilterValue, + 1, + 153, + 25, + 0, // Skip to: 8056 + /* 1503 */ MCD_OPC_Decode, + 253, + 5, + 9, // Opcode: XNORCCri + /* 1507 */ MCD_OPC_FilterValue, + 24, + 28, + 0, + 0, // Skip to: 1540 + /* 1512 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1515 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1531 + /* 1520 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 129, + 25, + 0, // Skip to: 8056 + /* 1527 */ MCD_OPC_Decode, + 131, + 2, + 8, // Opcode: ADDErr + /* 1531 */ MCD_OPC_FilterValue, + 1, + 120, + 25, + 0, // Skip to: 8056 + /* 1536 */ MCD_OPC_Decode, + 130, + 2, + 9, // Opcode: ADDEri + /* 1540 */ MCD_OPC_FilterValue, + 26, + 28, + 0, + 0, // Skip to: 1573 + /* 1545 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1548 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1564 + /* 1553 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 96, + 25, + 0, // Skip to: 8056 + /* 1560 */ MCD_OPC_Decode, + 225, + 5, + 8, // Opcode: UMULCCrr + /* 1564 */ MCD_OPC_FilterValue, + 1, + 87, + 25, + 0, // Skip to: 8056 + /* 1569 */ MCD_OPC_Decode, + 224, + 5, + 9, // Opcode: UMULCCri + /* 1573 */ MCD_OPC_FilterValue, + 27, + 28, + 0, + 0, // Skip to: 1606 + /* 1578 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1581 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1597 + /* 1586 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 63, + 25, + 0, // Skip to: 8056 + /* 1593 */ MCD_OPC_Decode, + 132, + 5, + 8, // Opcode: SMULCCrr + /* 1597 */ MCD_OPC_FilterValue, + 1, + 54, + 25, + 0, // Skip to: 8056 + /* 1602 */ MCD_OPC_Decode, + 131, + 5, + 9, // Opcode: SMULCCri + /* 1606 */ MCD_OPC_FilterValue, + 28, + 28, + 0, + 0, // Skip to: 1639 + /* 1611 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1614 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1630 + /* 1619 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 30, + 25, + 0, // Skip to: 8056 + /* 1626 */ MCD_OPC_Decode, + 186, + 5, + 8, // Opcode: SUBErr + /* 1630 */ MCD_OPC_FilterValue, + 1, + 21, + 25, + 0, // Skip to: 8056 + /* 1635 */ MCD_OPC_Decode, + 185, + 5, + 9, // Opcode: SUBEri + /* 1639 */ MCD_OPC_FilterValue, + 30, + 28, + 0, + 0, // Skip to: 1672 + /* 1644 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1647 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1663 + /* 1652 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 253, + 24, + 0, // Skip to: 8056 + /* 1659 */ MCD_OPC_Decode, + 217, + 5, + 8, // Opcode: UDIVCCrr + /* 1663 */ MCD_OPC_FilterValue, + 1, + 244, + 24, + 0, // Skip to: 8056 + /* 1668 */ MCD_OPC_Decode, + 216, + 5, + 9, // Opcode: UDIVCCri + /* 1672 */ MCD_OPC_FilterValue, + 31, + 28, + 0, + 0, // Skip to: 1705 + /* 1677 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1680 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1696 + /* 1685 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 220, + 24, + 0, // Skip to: 8056 + /* 1692 */ MCD_OPC_Decode, + 243, + 4, + 8, // Opcode: SDIVCCrr + /* 1696 */ MCD_OPC_FilterValue, + 1, + 211, + 24, + 0, // Skip to: 8056 + /* 1701 */ MCD_OPC_Decode, + 242, + 4, + 9, // Opcode: SDIVCCri + /* 1705 */ MCD_OPC_FilterValue, + 32, + 28, + 0, + 0, // Skip to: 1738 + /* 1710 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1713 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1729 + /* 1718 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 187, + 24, + 0, // Skip to: 8056 + /* 1725 */ MCD_OPC_Decode, + 200, + 5, + 8, // Opcode: TADDCCrr + /* 1729 */ MCD_OPC_FilterValue, + 1, + 178, + 24, + 0, // Skip to: 8056 + /* 1734 */ MCD_OPC_Decode, + 199, + 5, + 9, // Opcode: TADDCCri + /* 1738 */ MCD_OPC_FilterValue, + 33, + 28, + 0, + 0, // Skip to: 1771 + /* 1743 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1746 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1762 + /* 1751 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 154, + 24, + 0, // Skip to: 8056 + /* 1758 */ MCD_OPC_Decode, + 213, + 5, + 8, // Opcode: TSUBCCrr + /* 1762 */ MCD_OPC_FilterValue, + 1, + 145, + 24, + 0, // Skip to: 8056 + /* 1767 */ MCD_OPC_Decode, + 212, + 5, + 9, // Opcode: TSUBCCri + /* 1771 */ MCD_OPC_FilterValue, + 34, + 28, + 0, + 0, // Skip to: 1804 + /* 1776 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1779 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1795 + /* 1784 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 121, + 24, + 0, // Skip to: 8056 + /* 1791 */ MCD_OPC_Decode, + 198, + 5, + 8, // Opcode: TADDCCTVrr + /* 1795 */ MCD_OPC_FilterValue, + 1, + 112, + 24, + 0, // Skip to: 8056 + /* 1800 */ MCD_OPC_Decode, + 197, + 5, + 9, // Opcode: TADDCCTVri + /* 1804 */ MCD_OPC_FilterValue, + 35, + 28, + 0, + 0, // Skip to: 1837 + /* 1809 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1812 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1828 + /* 1817 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 88, + 24, + 0, // Skip to: 8056 + /* 1824 */ MCD_OPC_Decode, + 211, + 5, + 8, // Opcode: TSUBCCTVrr + /* 1828 */ MCD_OPC_FilterValue, + 1, + 79, + 24, + 0, // Skip to: 8056 + /* 1833 */ MCD_OPC_Decode, + 210, + 5, + 9, // Opcode: TSUBCCTVri + /* 1837 */ MCD_OPC_FilterValue, + 36, + 28, + 0, + 0, // Skip to: 1870 + /* 1842 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 1845 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1861 + /* 1850 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 55, + 24, + 0, // Skip to: 8056 + /* 1857 */ MCD_OPC_Decode, + 206, + 4, + 8, // Opcode: MULSCCrr + /* 1861 */ MCD_OPC_FilterValue, + 1, + 46, + 24, + 0, // Skip to: 8056 + /* 1866 */ MCD_OPC_Decode, + 205, + 4, + 9, // Opcode: MULSCCri + /* 1870 */ MCD_OPC_FilterValue, + 37, + 39, + 0, + 0, // Skip to: 1914 + /* 1875 */ MCD_OPC_ExtractField, + 12, + 2, // Inst{13-12} ... + /* 1878 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1887 + /* 1883 */ MCD_OPC_Decode, + 128, + 5, + 8, // Opcode: SLLrr + /* 1887 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1896 + /* 1892 */ MCD_OPC_Decode, + 254, + 4, + 14, // Opcode: SLLXrr + /* 1896 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 1905 + /* 1901 */ MCD_OPC_Decode, + 255, + 4, + 15, // Opcode: SLLri + /* 1905 */ MCD_OPC_FilterValue, + 3, + 2, + 24, + 0, // Skip to: 8056 + /* 1910 */ MCD_OPC_Decode, + 253, + 4, + 16, // Opcode: SLLXri + /* 1914 */ MCD_OPC_FilterValue, + 38, + 39, + 0, + 0, // Skip to: 1958 + /* 1919 */ MCD_OPC_ExtractField, + 12, + 2, // Inst{13-12} ... + /* 1922 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1931 + /* 1927 */ MCD_OPC_Decode, + 142, + 5, + 8, // Opcode: SRLrr + /* 1931 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1940 + /* 1936 */ MCD_OPC_Decode, + 140, + 5, + 14, // Opcode: SRLXrr + /* 1940 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 1949 + /* 1945 */ MCD_OPC_Decode, + 141, + 5, + 15, // Opcode: SRLri + /* 1949 */ MCD_OPC_FilterValue, + 3, + 214, + 23, + 0, // Skip to: 8056 + /* 1954 */ MCD_OPC_Decode, + 139, + 5, + 16, // Opcode: SRLXri + /* 1958 */ MCD_OPC_FilterValue, + 39, + 39, + 0, + 0, // Skip to: 2002 + /* 1963 */ MCD_OPC_ExtractField, + 12, + 2, // Inst{13-12} ... + /* 1966 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1975 + /* 1971 */ MCD_OPC_Decode, + 138, + 5, + 8, // Opcode: SRArr + /* 1975 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1984 + /* 1980 */ MCD_OPC_Decode, + 136, + 5, + 14, // Opcode: SRAXrr + /* 1984 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 1993 + /* 1989 */ MCD_OPC_Decode, + 137, + 5, + 15, // Opcode: SRAri + /* 1993 */ MCD_OPC_FilterValue, + 3, + 170, + 23, + 0, // Skip to: 8056 + /* 1998 */ MCD_OPC_Decode, + 135, + 5, + 16, // Opcode: SRAXri + /* 2002 */ MCD_OPC_FilterValue, + 40, + 81, + 0, + 0, // Skip to: 2088 + /* 2007 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 2010 */ MCD_OPC_FilterValue, + 0, + 45, + 0, + 0, // Skip to: 2060 + /* 2015 */ MCD_OPC_ExtractField, + 0, + 13, // Inst{12-0} ... + /* 2018 */ MCD_OPC_FilterValue, + 0, + 145, + 23, + 0, // Skip to: 8056 + /* 2023 */ MCD_OPC_ExtractField, + 14, + 5, // Inst{18-14} ... + /* 2026 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 2040 + /* 2031 */ MCD_OPC_CheckPredicate, + 0, + 20, + 0, + 0, // Skip to: 2056 + /* 2036 */ MCD_OPC_Decode, + 229, + 4, + 17, // Opcode: RDPC + /* 2040 */ MCD_OPC_FilterValue, + 15, + 11, + 0, + 0, // Skip to: 2056 + /* 2045 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 4, + 0, + 0, // Skip to: 2056 + /* 2052 */ MCD_OPC_Decode, + 144, + 5, + 4, // Opcode: STBAR + /* 2056 */ MCD_OPC_Decode, + 228, + 4, + 18, // Opcode: RDASR + /* 2060 */ MCD_OPC_FilterValue, + 1, + 103, + 23, + 0, // Skip to: 8056 + /* 2065 */ MCD_OPC_CheckPredicate, + 0, + 98, + 23, + 0, // Skip to: 8056 + /* 2070 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 91, + 23, + 0, // Skip to: 8056 + /* 2077 */ MCD_OPC_CheckField, + 14, + 5, + 15, + 84, + 23, + 0, // Skip to: 8056 + /* 2084 */ MCD_OPC_Decode, + 181, + 4, + 19, // Opcode: MEMBARi + /* 2088 */ MCD_OPC_FilterValue, + 41, + 11, + 0, + 0, // Skip to: 2104 + /* 2093 */ MCD_OPC_CheckField, + 0, + 19, + 0, + 68, + 23, + 0, // Skip to: 8056 + /* 2100 */ MCD_OPC_Decode, + 231, + 4, + 17, // Opcode: RDPSR + /* 2104 */ MCD_OPC_FilterValue, + 42, + 28, + 0, + 0, // Skip to: 2137 + /* 2109 */ MCD_OPC_ExtractField, + 0, + 14, // Inst{13-0} ... + /* 2112 */ MCD_OPC_FilterValue, + 0, + 51, + 23, + 0, // Skip to: 8056 + /* 2117 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 4, + 0, + 0, // Skip to: 2128 + /* 2124 */ MCD_OPC_Decode, + 233, + 4, + 17, // Opcode: RDWIM + /* 2128 */ MCD_OPC_CheckPredicate, + 0, + 35, + 23, + 0, // Skip to: 8056 + /* 2133 */ MCD_OPC_Decode, + 230, + 4, + 20, // Opcode: RDPR + /* 2137 */ MCD_OPC_FilterValue, + 43, + 28, + 0, + 0, // Skip to: 2170 + /* 2142 */ MCD_OPC_ExtractField, + 0, + 19, // Inst{18-0} ... + /* 2145 */ MCD_OPC_FilterValue, + 0, + 18, + 23, + 0, // Skip to: 8056 + /* 2150 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 2166 + /* 2155 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 4, + 0, + 0, // Skip to: 2166 + /* 2162 */ MCD_OPC_Decode, + 141, + 3, + 4, // Opcode: FLUSHW + /* 2166 */ MCD_OPC_Decode, + 232, + 4, + 17, // Opcode: RDTBR + /* 2170 */ MCD_OPC_FilterValue, + 44, + 141, + 0, + 0, // Skip to: 2316 + /* 2175 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 2178 */ MCD_OPC_FilterValue, + 0, + 64, + 0, + 0, // Skip to: 2247 + /* 2183 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 2186 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2216 + /* 2191 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 2207 + /* 2196 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 2207 + /* 2203 */ MCD_OPC_Decode, + 184, + 4, + 21, // Opcode: MOVFCCrr + /* 2207 */ MCD_OPC_CheckPredicate, + 0, + 212, + 22, + 0, // Skip to: 8056 + /* 2212 */ MCD_OPC_Decode, + 240, + 5, + 22, // Opcode: V9MOVFCCrr + /* 2216 */ MCD_OPC_FilterValue, + 1, + 203, + 22, + 0, // Skip to: 8056 + /* 2221 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 2224 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2238 + /* 2229 */ MCD_OPC_CheckPredicate, + 0, + 190, + 22, + 0, // Skip to: 8056 + /* 2234 */ MCD_OPC_Decode, + 186, + 4, + 21, // Opcode: MOVICCrr + /* 2238 */ MCD_OPC_FilterValue, + 2, + 181, + 22, + 0, // Skip to: 8056 + /* 2243 */ MCD_OPC_Decode, + 203, + 4, + 21, // Opcode: MOVXCCrr + /* 2247 */ MCD_OPC_FilterValue, + 1, + 172, + 22, + 0, // Skip to: 8056 + /* 2252 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 2255 */ MCD_OPC_FilterValue, + 0, + 25, + 0, + 0, // Skip to: 2285 + /* 2260 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 2276 + /* 2265 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 2276 + /* 2272 */ MCD_OPC_Decode, + 183, + 4, + 23, // Opcode: MOVFCCri + /* 2276 */ MCD_OPC_CheckPredicate, + 0, + 143, + 22, + 0, // Skip to: 8056 + /* 2281 */ MCD_OPC_Decode, + 239, + 5, + 24, // Opcode: V9MOVFCCri + /* 2285 */ MCD_OPC_FilterValue, + 1, + 134, + 22, + 0, // Skip to: 8056 + /* 2290 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 2293 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 2307 + /* 2298 */ MCD_OPC_CheckPredicate, + 0, + 121, + 22, + 0, // Skip to: 8056 + /* 2303 */ MCD_OPC_Decode, + 185, + 4, + 23, // Opcode: MOVICCri + /* 2307 */ MCD_OPC_FilterValue, + 2, + 112, + 22, + 0, // Skip to: 8056 + /* 2312 */ MCD_OPC_Decode, + 202, + 4, + 23, // Opcode: MOVXCCri + /* 2316 */ MCD_OPC_FilterValue, + 45, + 28, + 0, + 0, // Skip to: 2349 + /* 2321 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 2324 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 2340 + /* 2329 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 88, + 22, + 0, // Skip to: 8056 + /* 2336 */ MCD_OPC_Decode, + 245, + 4, + 10, // Opcode: SDIVXrr + /* 2340 */ MCD_OPC_FilterValue, + 1, + 79, + 22, + 0, // Skip to: 8056 + /* 2345 */ MCD_OPC_Decode, + 244, + 4, + 11, // Opcode: SDIVXri + /* 2349 */ MCD_OPC_FilterValue, + 46, + 16, + 0, + 0, // Skip to: 2370 + /* 2354 */ MCD_OPC_CheckPredicate, + 0, + 65, + 22, + 0, // Skip to: 8056 + /* 2359 */ MCD_OPC_CheckField, + 5, + 14, + 0, + 58, + 22, + 0, // Skip to: 8056 + /* 2366 */ MCD_OPC_Decode, + 223, + 4, + 25, // Opcode: POPCrr + /* 2370 */ MCD_OPC_FilterValue, + 47, + 153, + 0, + 0, // Skip to: 2528 + /* 2375 */ MCD_OPC_ExtractField, + 10, + 4, // Inst{13-10} ... + /* 2378 */ MCD_OPC_FilterValue, + 1, + 11, + 0, + 0, // Skip to: 2394 + /* 2383 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 34, + 22, + 0, // Skip to: 8056 + /* 2390 */ MCD_OPC_Decode, + 198, + 4, + 14, // Opcode: MOVRRZrr + /* 2394 */ MCD_OPC_FilterValue, + 2, + 11, + 0, + 0, // Skip to: 2410 + /* 2399 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 18, + 22, + 0, // Skip to: 8056 + /* 2406 */ MCD_OPC_Decode, + 192, + 4, + 14, // Opcode: MOVRLEZrr + /* 2410 */ MCD_OPC_FilterValue, + 3, + 11, + 0, + 0, // Skip to: 2426 + /* 2415 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 2, + 22, + 0, // Skip to: 8056 + /* 2422 */ MCD_OPC_Decode, + 194, + 4, + 14, // Opcode: MOVRLZrr + /* 2426 */ MCD_OPC_FilterValue, + 5, + 11, + 0, + 0, // Skip to: 2442 + /* 2431 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 242, + 21, + 0, // Skip to: 8056 + /* 2438 */ MCD_OPC_Decode, + 196, + 4, + 14, // Opcode: MOVRNZrr + /* 2442 */ MCD_OPC_FilterValue, + 6, + 11, + 0, + 0, // Skip to: 2458 + /* 2447 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 226, + 21, + 0, // Skip to: 8056 + /* 2454 */ MCD_OPC_Decode, + 190, + 4, + 14, // Opcode: MOVRGZrr + /* 2458 */ MCD_OPC_FilterValue, + 7, + 11, + 0, + 0, // Skip to: 2474 + /* 2463 */ MCD_OPC_CheckField, + 5, + 5, + 0, + 210, + 21, + 0, // Skip to: 8056 + /* 2470 */ MCD_OPC_Decode, + 188, + 4, + 14, // Opcode: MOVRGEZrr + /* 2474 */ MCD_OPC_FilterValue, + 9, + 4, + 0, + 0, // Skip to: 2483 + /* 2479 */ MCD_OPC_Decode, + 197, + 4, + 26, // Opcode: MOVRRZri + /* 2483 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 2492 + /* 2488 */ MCD_OPC_Decode, + 191, + 4, + 26, // Opcode: MOVRLEZri + /* 2492 */ MCD_OPC_FilterValue, + 11, + 4, + 0, + 0, // Skip to: 2501 + /* 2497 */ MCD_OPC_Decode, + 193, + 4, + 26, // Opcode: MOVRLZri + /* 2501 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 2510 + /* 2506 */ MCD_OPC_Decode, + 195, + 4, + 26, // Opcode: MOVRNZri + /* 2510 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 2519 + /* 2515 */ MCD_OPC_Decode, + 189, + 4, + 26, // Opcode: MOVRGZri + /* 2519 */ MCD_OPC_FilterValue, + 15, + 156, + 21, + 0, // Skip to: 8056 + /* 2524 */ MCD_OPC_Decode, + 187, + 4, + 26, // Opcode: MOVRGEZri + /* 2528 */ MCD_OPC_FilterValue, + 48, + 51, + 0, + 0, // Skip to: 2584 + /* 2533 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 2536 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 2552 + /* 2541 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 132, + 21, + 0, // Skip to: 8056 + /* 2548 */ MCD_OPC_Decode, + 242, + 5, + 27, // Opcode: WRASRrr + /* 2552 */ MCD_OPC_FilterValue, + 1, + 123, + 21, + 0, // Skip to: 8056 + /* 2557 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 2580 + /* 2562 */ MCD_OPC_CheckField, + 25, + 5, + 15, + 11, + 0, + 0, // Skip to: 2580 + /* 2569 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 4, + 0, + 0, // Skip to: 2580 + /* 2576 */ MCD_OPC_Decode, + 252, + 4, + 28, // Opcode: SIR + /* 2580 */ MCD_OPC_Decode, + 241, + 5, + 29, // Opcode: WRASRri + /* 2584 */ MCD_OPC_FilterValue, + 49, + 79, + 0, + 0, // Skip to: 2668 + /* 2589 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 2592 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 2637 + /* 2597 */ MCD_OPC_ExtractField, + 25, + 5, // Inst{29-25} ... + /* 2600 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 2616 + /* 2605 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 68, + 21, + 0, // Skip to: 8056 + /* 2612 */ MCD_OPC_Decode, + 246, + 5, + 12, // Opcode: WRPSRrr + /* 2616 */ MCD_OPC_FilterValue, + 1, + 59, + 21, + 0, // Skip to: 8056 + /* 2621 */ MCD_OPC_CheckPredicate, + 1, + 54, + 21, + 0, // Skip to: 8056 + /* 2626 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 47, + 21, + 0, // Skip to: 8056 + /* 2633 */ MCD_OPC_Decode, + 227, + 4, + 12, // Opcode: PWRPSRrr + /* 2637 */ MCD_OPC_FilterValue, + 1, + 38, + 21, + 0, // Skip to: 8056 + /* 2642 */ MCD_OPC_ExtractField, + 25, + 5, // Inst{29-25} ... + /* 2645 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 2654 + /* 2650 */ MCD_OPC_Decode, + 245, + 5, + 13, // Opcode: WRPSRri + /* 2654 */ MCD_OPC_FilterValue, + 1, + 21, + 21, + 0, // Skip to: 8056 + /* 2659 */ MCD_OPC_CheckPredicate, + 1, + 16, + 21, + 0, // Skip to: 8056 + /* 2664 */ MCD_OPC_Decode, + 226, + 4, + 13, // Opcode: PWRPSRri + /* 2668 */ MCD_OPC_FilterValue, + 50, + 61, + 0, + 0, // Skip to: 2734 + /* 2673 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 2676 */ MCD_OPC_FilterValue, + 0, + 28, + 0, + 0, // Skip to: 2709 + /* 2681 */ MCD_OPC_ExtractField, + 5, + 8, // Inst{12-5} ... + /* 2684 */ MCD_OPC_FilterValue, + 0, + 247, + 20, + 0, // Skip to: 8056 + /* 2689 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 4, + 0, + 0, // Skip to: 2700 + /* 2696 */ MCD_OPC_Decode, + 250, + 5, + 12, // Opcode: WRWIMrr + /* 2700 */ MCD_OPC_CheckPredicate, + 0, + 231, + 20, + 0, // Skip to: 8056 + /* 2705 */ MCD_OPC_Decode, + 244, + 5, + 30, // Opcode: WRPRrr + /* 2709 */ MCD_OPC_FilterValue, + 1, + 222, + 20, + 0, // Skip to: 8056 + /* 2714 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 4, + 0, + 0, // Skip to: 2725 + /* 2721 */ MCD_OPC_Decode, + 249, + 5, + 13, // Opcode: WRWIMri + /* 2725 */ MCD_OPC_CheckPredicate, + 0, + 206, + 20, + 0, // Skip to: 8056 + /* 2730 */ MCD_OPC_Decode, + 243, + 5, + 31, // Opcode: WRPRri + /* 2734 */ MCD_OPC_FilterValue, + 51, + 42, + 0, + 0, // Skip to: 2781 + /* 2739 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 2742 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 2765 + /* 2747 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 182, + 20, + 0, // Skip to: 8056 + /* 2754 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 175, + 20, + 0, // Skip to: 8056 + /* 2761 */ MCD_OPC_Decode, + 248, + 5, + 12, // Opcode: WRTBRrr + /* 2765 */ MCD_OPC_FilterValue, + 1, + 166, + 20, + 0, // Skip to: 8056 + /* 2770 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 159, + 20, + 0, // Skip to: 8056 + /* 2777 */ MCD_OPC_Decode, + 247, + 5, + 13, // Opcode: WRTBRri + /* 2781 */ MCD_OPC_FilterValue, + 52, + 43, + 3, + 0, // Skip to: 3597 + /* 2786 */ MCD_OPC_ExtractField, + 5, + 9, // Inst{13-5} ... + /* 2789 */ MCD_OPC_FilterValue, + 1, + 11, + 0, + 0, // Skip to: 2805 + /* 2794 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 135, + 20, + 0, // Skip to: 8056 + /* 2801 */ MCD_OPC_Decode, + 171, + 3, + 32, // Opcode: FMOVS + /* 2805 */ MCD_OPC_FilterValue, + 2, + 16, + 0, + 0, // Skip to: 2826 + /* 2810 */ MCD_OPC_CheckPredicate, + 0, + 121, + 20, + 0, // Skip to: 8056 + /* 2815 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 114, + 20, + 0, // Skip to: 8056 + /* 2822 */ MCD_OPC_Decode, + 145, + 3, + 33, // Opcode: FMOVD + /* 2826 */ MCD_OPC_FilterValue, + 3, + 16, + 0, + 0, // Skip to: 2847 + /* 2831 */ MCD_OPC_CheckPredicate, + 0, + 100, + 20, + 0, // Skip to: 8056 + /* 2836 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 93, + 20, + 0, // Skip to: 8056 + /* 2843 */ MCD_OPC_Decode, + 149, + 3, + 34, // Opcode: FMOVQ + /* 2847 */ MCD_OPC_FilterValue, + 5, + 11, + 0, + 0, // Skip to: 2863 + /* 2852 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 77, + 20, + 0, // Skip to: 8056 + /* 2859 */ MCD_OPC_Decode, + 191, + 3, + 32, // Opcode: FNEGS + /* 2863 */ MCD_OPC_FilterValue, + 6, + 16, + 0, + 0, // Skip to: 2884 + /* 2868 */ MCD_OPC_CheckPredicate, + 0, + 63, + 20, + 0, // Skip to: 8056 + /* 2873 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 56, + 20, + 0, // Skip to: 8056 + /* 2880 */ MCD_OPC_Decode, + 189, + 3, + 33, // Opcode: FNEGD + /* 2884 */ MCD_OPC_FilterValue, + 7, + 16, + 0, + 0, // Skip to: 2905 + /* 2889 */ MCD_OPC_CheckPredicate, + 0, + 42, + 20, + 0, // Skip to: 8056 + /* 2894 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 35, + 20, + 0, // Skip to: 8056 + /* 2901 */ MCD_OPC_Decode, + 190, + 3, + 34, // Opcode: FNEGQ + /* 2905 */ MCD_OPC_FilterValue, + 9, + 11, + 0, + 0, // Skip to: 2921 + /* 2910 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 19, + 20, + 0, // Skip to: 8056 + /* 2917 */ MCD_OPC_Decode, + 225, + 2, + 32, // Opcode: FABSS + /* 2921 */ MCD_OPC_FilterValue, + 10, + 16, + 0, + 0, // Skip to: 2942 + /* 2926 */ MCD_OPC_CheckPredicate, + 0, + 5, + 20, + 0, // Skip to: 8056 + /* 2931 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 254, + 19, + 0, // Skip to: 8056 + /* 2938 */ MCD_OPC_Decode, + 223, + 2, + 33, // Opcode: FABSD + /* 2942 */ MCD_OPC_FilterValue, + 11, + 16, + 0, + 0, // Skip to: 2963 + /* 2947 */ MCD_OPC_CheckPredicate, + 0, + 240, + 19, + 0, // Skip to: 8056 + /* 2952 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 233, + 19, + 0, // Skip to: 8056 + /* 2959 */ MCD_OPC_Decode, + 224, + 2, + 34, // Opcode: FABSQ + /* 2963 */ MCD_OPC_FilterValue, + 41, + 11, + 0, + 0, // Skip to: 2979 + /* 2968 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 217, + 19, + 0, // Skip to: 8056 + /* 2975 */ MCD_OPC_Decode, + 235, + 3, + 32, // Opcode: FSQRTS + /* 2979 */ MCD_OPC_FilterValue, + 42, + 11, + 0, + 0, // Skip to: 2995 + /* 2984 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 201, + 19, + 0, // Skip to: 8056 + /* 2991 */ MCD_OPC_Decode, + 233, + 3, + 33, // Opcode: FSQRTD + /* 2995 */ MCD_OPC_FilterValue, + 43, + 11, + 0, + 0, // Skip to: 3011 + /* 3000 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 185, + 19, + 0, // Skip to: 8056 + /* 3007 */ MCD_OPC_Decode, + 234, + 3, + 34, // Opcode: FSQRTQ + /* 3011 */ MCD_OPC_FilterValue, + 65, + 4, + 0, + 0, // Skip to: 3020 + /* 3016 */ MCD_OPC_Decode, + 228, + 2, + 35, // Opcode: FADDS + /* 3020 */ MCD_OPC_FilterValue, + 66, + 4, + 0, + 0, // Skip to: 3029 + /* 3025 */ MCD_OPC_Decode, + 226, + 2, + 36, // Opcode: FADDD + /* 3029 */ MCD_OPC_FilterValue, + 67, + 4, + 0, + 0, // Skip to: 3038 + /* 3034 */ MCD_OPC_Decode, + 227, + 2, + 37, // Opcode: FADDQ + /* 3038 */ MCD_OPC_FilterValue, + 69, + 4, + 0, + 0, // Skip to: 3047 + /* 3043 */ MCD_OPC_Decode, + 250, + 3, + 35, // Opcode: FSUBS + /* 3047 */ MCD_OPC_FilterValue, + 70, + 4, + 0, + 0, // Skip to: 3056 + /* 3052 */ MCD_OPC_Decode, + 248, + 3, + 36, // Opcode: FSUBD + /* 3056 */ MCD_OPC_FilterValue, + 71, + 4, + 0, + 0, // Skip to: 3065 + /* 3061 */ MCD_OPC_Decode, + 249, + 3, + 37, // Opcode: FSUBQ + /* 3065 */ MCD_OPC_FilterValue, + 73, + 4, + 0, + 0, // Skip to: 3074 + /* 3070 */ MCD_OPC_Decode, + 184, + 3, + 35, // Opcode: FMULS + /* 3074 */ MCD_OPC_FilterValue, + 74, + 4, + 0, + 0, // Skip to: 3083 + /* 3079 */ MCD_OPC_Decode, + 180, + 3, + 36, // Opcode: FMULD + /* 3083 */ MCD_OPC_FilterValue, + 75, + 4, + 0, + 0, // Skip to: 3092 + /* 3088 */ MCD_OPC_Decode, + 183, + 3, + 37, // Opcode: FMULQ + /* 3092 */ MCD_OPC_FilterValue, + 77, + 4, + 0, + 0, // Skip to: 3101 + /* 3097 */ MCD_OPC_Decode, + 252, + 2, + 35, // Opcode: FDIVS + /* 3101 */ MCD_OPC_FilterValue, + 78, + 4, + 0, + 0, // Skip to: 3110 + /* 3106 */ MCD_OPC_Decode, + 250, + 2, + 36, // Opcode: FDIVD + /* 3110 */ MCD_OPC_FilterValue, + 79, + 4, + 0, + 0, // Skip to: 3119 + /* 3115 */ MCD_OPC_Decode, + 251, + 2, + 37, // Opcode: FDIVQ + /* 3119 */ MCD_OPC_FilterValue, + 81, + 9, + 0, + 0, // Skip to: 3133 + /* 3124 */ MCD_OPC_CheckPredicate, + 2, + 63, + 19, + 0, // Skip to: 8056 + /* 3129 */ MCD_OPC_Decode, + 186, + 3, + 36, // Opcode: FNADDS + /* 3133 */ MCD_OPC_FilterValue, + 82, + 9, + 0, + 0, // Skip to: 3147 + /* 3138 */ MCD_OPC_CheckPredicate, + 2, + 49, + 19, + 0, // Skip to: 8056 + /* 3143 */ MCD_OPC_Decode, + 185, + 3, + 36, // Opcode: FNADDD + /* 3147 */ MCD_OPC_FilterValue, + 89, + 9, + 0, + 0, // Skip to: 3161 + /* 3152 */ MCD_OPC_CheckPredicate, + 2, + 35, + 19, + 0, // Skip to: 8056 + /* 3157 */ MCD_OPC_Decode, + 195, + 3, + 36, // Opcode: FNMULS + /* 3161 */ MCD_OPC_FilterValue, + 90, + 9, + 0, + 0, // Skip to: 3175 + /* 3166 */ MCD_OPC_CheckPredicate, + 2, + 21, + 19, + 0, // Skip to: 8056 + /* 3171 */ MCD_OPC_Decode, + 194, + 3, + 36, // Opcode: FNMULD + /* 3175 */ MCD_OPC_FilterValue, + 97, + 9, + 0, + 0, // Skip to: 3189 + /* 3180 */ MCD_OPC_CheckPredicate, + 2, + 7, + 19, + 0, // Skip to: 8056 + /* 3185 */ MCD_OPC_Decode, + 132, + 3, + 36, // Opcode: FHADDS + /* 3189 */ MCD_OPC_FilterValue, + 98, + 9, + 0, + 0, // Skip to: 3203 + /* 3194 */ MCD_OPC_CheckPredicate, + 2, + 249, + 18, + 0, // Skip to: 8056 + /* 3199 */ MCD_OPC_Decode, + 131, + 3, + 36, // Opcode: FHADDD + /* 3203 */ MCD_OPC_FilterValue, + 101, + 9, + 0, + 0, // Skip to: 3217 + /* 3208 */ MCD_OPC_CheckPredicate, + 2, + 235, + 18, + 0, // Skip to: 8056 + /* 3213 */ MCD_OPC_Decode, + 134, + 3, + 36, // Opcode: FHSUBS + /* 3217 */ MCD_OPC_FilterValue, + 102, + 9, + 0, + 0, // Skip to: 3231 + /* 3222 */ MCD_OPC_CheckPredicate, + 2, + 221, + 18, + 0, // Skip to: 8056 + /* 3227 */ MCD_OPC_Decode, + 133, + 3, + 36, // Opcode: FHSUBD + /* 3231 */ MCD_OPC_FilterValue, + 105, + 4, + 0, + 0, // Skip to: 3240 + /* 3236 */ MCD_OPC_Decode, + 232, + 3, + 38, // Opcode: FSMULD + /* 3240 */ MCD_OPC_FilterValue, + 110, + 4, + 0, + 0, // Skip to: 3249 + /* 3245 */ MCD_OPC_Decode, + 253, + 2, + 39, // Opcode: FDMULQ + /* 3249 */ MCD_OPC_FilterValue, + 113, + 9, + 0, + 0, // Skip to: 3263 + /* 3254 */ MCD_OPC_CheckPredicate, + 2, + 189, + 18, + 0, // Skip to: 8056 + /* 3259 */ MCD_OPC_Decode, + 193, + 3, + 36, // Opcode: FNHADDS + /* 3263 */ MCD_OPC_FilterValue, + 114, + 9, + 0, + 0, // Skip to: 3277 + /* 3268 */ MCD_OPC_CheckPredicate, + 2, + 175, + 18, + 0, // Skip to: 8056 + /* 3273 */ MCD_OPC_Decode, + 192, + 3, + 36, // Opcode: FNHADDD + /* 3277 */ MCD_OPC_FilterValue, + 121, + 9, + 0, + 0, // Skip to: 3291 + /* 3282 */ MCD_OPC_CheckPredicate, + 2, + 161, + 18, + 0, // Skip to: 8056 + /* 3287 */ MCD_OPC_Decode, + 202, + 3, + 36, // Opcode: FNSMULD + /* 3291 */ MCD_OPC_FilterValue, + 129, + 1, + 11, + 0, + 0, // Skip to: 3308 + /* 3297 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 144, + 18, + 0, // Skip to: 8056 + /* 3304 */ MCD_OPC_Decode, + 247, + 3, + 40, // Opcode: FSTOX + /* 3308 */ MCD_OPC_FilterValue, + 130, + 1, + 11, + 0, + 0, // Skip to: 3325 + /* 3314 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 127, + 18, + 0, // Skip to: 8056 + /* 3321 */ MCD_OPC_Decode, + 129, + 3, + 33, // Opcode: FDTOX + /* 3325 */ MCD_OPC_FilterValue, + 131, + 1, + 11, + 0, + 0, // Skip to: 3342 + /* 3331 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 110, + 18, + 0, // Skip to: 8056 + /* 3338 */ MCD_OPC_Decode, + 227, + 3, + 41, // Opcode: FQTOX + /* 3342 */ MCD_OPC_FilterValue, + 132, + 1, + 11, + 0, + 0, // Skip to: 3359 + /* 3348 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 93, + 18, + 0, // Skip to: 8056 + /* 3355 */ MCD_OPC_Decode, + 129, + 4, + 42, // Opcode: FXTOS + /* 3359 */ MCD_OPC_FilterValue, + 136, + 1, + 11, + 0, + 0, // Skip to: 3376 + /* 3365 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 76, + 18, + 0, // Skip to: 8056 + /* 3372 */ MCD_OPC_Decode, + 255, + 3, + 33, // Opcode: FXTOD + /* 3376 */ MCD_OPC_FilterValue, + 140, + 1, + 11, + 0, + 0, // Skip to: 3393 + /* 3382 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 59, + 18, + 0, // Skip to: 8056 + /* 3389 */ MCD_OPC_Decode, + 128, + 4, + 43, // Opcode: FXTOQ + /* 3393 */ MCD_OPC_FilterValue, + 196, + 1, + 11, + 0, + 0, // Skip to: 3410 + /* 3399 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 42, + 18, + 0, // Skip to: 8056 + /* 3406 */ MCD_OPC_Decode, + 137, + 3, + 32, // Opcode: FITOS + /* 3410 */ MCD_OPC_FilterValue, + 198, + 1, + 11, + 0, + 0, // Skip to: 3427 + /* 3416 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 25, + 18, + 0, // Skip to: 8056 + /* 3423 */ MCD_OPC_Decode, + 128, + 3, + 42, // Opcode: FDTOS + /* 3427 */ MCD_OPC_FilterValue, + 199, + 1, + 11, + 0, + 0, // Skip to: 3444 + /* 3433 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 8, + 18, + 0, // Skip to: 8056 + /* 3440 */ MCD_OPC_Decode, + 226, + 3, + 44, // Opcode: FQTOS + /* 3444 */ MCD_OPC_FilterValue, + 200, + 1, + 11, + 0, + 0, // Skip to: 3461 + /* 3450 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 247, + 17, + 0, // Skip to: 8056 + /* 3457 */ MCD_OPC_Decode, + 135, + 3, + 40, // Opcode: FITOD + /* 3461 */ MCD_OPC_FilterValue, + 201, + 1, + 11, + 0, + 0, // Skip to: 3478 + /* 3467 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 230, + 17, + 0, // Skip to: 8056 + /* 3474 */ MCD_OPC_Decode, + 244, + 3, + 40, // Opcode: FSTOD + /* 3478 */ MCD_OPC_FilterValue, + 203, + 1, + 11, + 0, + 0, // Skip to: 3495 + /* 3484 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 213, + 17, + 0, // Skip to: 8056 + /* 3491 */ MCD_OPC_Decode, + 224, + 3, + 41, // Opcode: FQTOD + /* 3495 */ MCD_OPC_FilterValue, + 204, + 1, + 11, + 0, + 0, // Skip to: 3512 + /* 3501 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 196, + 17, + 0, // Skip to: 8056 + /* 3508 */ MCD_OPC_Decode, + 136, + 3, + 45, // Opcode: FITOQ + /* 3512 */ MCD_OPC_FilterValue, + 205, + 1, + 11, + 0, + 0, // Skip to: 3529 + /* 3518 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 179, + 17, + 0, // Skip to: 8056 + /* 3525 */ MCD_OPC_Decode, + 246, + 3, + 45, // Opcode: FSTOQ + /* 3529 */ MCD_OPC_FilterValue, + 206, + 1, + 11, + 0, + 0, // Skip to: 3546 + /* 3535 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 162, + 17, + 0, // Skip to: 8056 + /* 3542 */ MCD_OPC_Decode, + 255, + 2, + 43, // Opcode: FDTOQ + /* 3546 */ MCD_OPC_FilterValue, + 209, + 1, + 11, + 0, + 0, // Skip to: 3563 + /* 3552 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 145, + 17, + 0, // Skip to: 8056 + /* 3559 */ MCD_OPC_Decode, + 245, + 3, + 32, // Opcode: FSTOI + /* 3563 */ MCD_OPC_FilterValue, + 210, + 1, + 11, + 0, + 0, // Skip to: 3580 + /* 3569 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 128, + 17, + 0, // Skip to: 8056 + /* 3576 */ MCD_OPC_Decode, + 254, + 2, + 42, // Opcode: FDTOI + /* 3580 */ MCD_OPC_FilterValue, + 211, + 1, + 118, + 17, + 0, // Skip to: 8056 + /* 3586 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 111, + 17, + 0, // Skip to: 8056 + /* 3593 */ MCD_OPC_Decode, + 225, + 3, + 44, // Opcode: FQTOI + /* 3597 */ MCD_OPC_FilterValue, + 53, + 160, + 2, + 0, // Skip to: 4274 + /* 3602 */ MCD_OPC_ExtractField, + 5, + 6, // Inst{10-5} ... + /* 3605 */ MCD_OPC_FilterValue, + 1, + 86, + 0, + 0, // Skip to: 3696 + /* 3610 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3613 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 3651 + /* 3618 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 3621 */ MCD_OPC_FilterValue, + 0, + 78, + 17, + 0, // Skip to: 8056 + /* 3626 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 3642 + /* 3631 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 3642 + /* 3638 */ MCD_OPC_Decode, + 172, + 3, + 46, // Opcode: FMOVS_FCC + /* 3642 */ MCD_OPC_CheckPredicate, + 0, + 57, + 17, + 0, // Skip to: 8056 + /* 3647 */ MCD_OPC_Decode, + 238, + 5, + 47, // Opcode: V9FMOVS_FCC + /* 3651 */ MCD_OPC_FilterValue, + 1, + 48, + 17, + 0, // Skip to: 8056 + /* 3656 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 3659 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3680 + /* 3664 */ MCD_OPC_CheckPredicate, + 0, + 35, + 17, + 0, // Skip to: 8056 + /* 3669 */ MCD_OPC_CheckField, + 18, + 1, + 0, + 28, + 17, + 0, // Skip to: 8056 + /* 3676 */ MCD_OPC_Decode, + 173, + 3, + 46, // Opcode: FMOVS_ICC + /* 3680 */ MCD_OPC_FilterValue, + 2, + 19, + 17, + 0, // Skip to: 8056 + /* 3685 */ MCD_OPC_CheckField, + 18, + 1, + 0, + 12, + 17, + 0, // Skip to: 8056 + /* 3692 */ MCD_OPC_Decode, + 174, + 3, + 46, // Opcode: FMOVS_XCC + /* 3696 */ MCD_OPC_FilterValue, + 2, + 86, + 0, + 0, // Skip to: 3787 + /* 3701 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3704 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 3742 + /* 3709 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 3712 */ MCD_OPC_FilterValue, + 0, + 243, + 16, + 0, // Skip to: 8056 + /* 3717 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 3733 + /* 3722 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 3733 + /* 3729 */ MCD_OPC_Decode, + 146, + 3, + 48, // Opcode: FMOVD_FCC + /* 3733 */ MCD_OPC_CheckPredicate, + 0, + 222, + 16, + 0, // Skip to: 8056 + /* 3738 */ MCD_OPC_Decode, + 236, + 5, + 49, // Opcode: V9FMOVD_FCC + /* 3742 */ MCD_OPC_FilterValue, + 1, + 213, + 16, + 0, // Skip to: 8056 + /* 3747 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 3750 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3771 + /* 3755 */ MCD_OPC_CheckPredicate, + 0, + 200, + 16, + 0, // Skip to: 8056 + /* 3760 */ MCD_OPC_CheckField, + 18, + 1, + 0, + 193, + 16, + 0, // Skip to: 8056 + /* 3767 */ MCD_OPC_Decode, + 147, + 3, + 48, // Opcode: FMOVD_ICC + /* 3771 */ MCD_OPC_FilterValue, + 2, + 184, + 16, + 0, // Skip to: 8056 + /* 3776 */ MCD_OPC_CheckField, + 18, + 1, + 0, + 177, + 16, + 0, // Skip to: 8056 + /* 3783 */ MCD_OPC_Decode, + 148, + 3, + 48, // Opcode: FMOVD_XCC + /* 3787 */ MCD_OPC_FilterValue, + 3, + 86, + 0, + 0, // Skip to: 3878 + /* 3792 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 3795 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 3833 + /* 3800 */ MCD_OPC_ExtractField, + 18, + 1, // Inst{18} ... + /* 3803 */ MCD_OPC_FilterValue, + 0, + 152, + 16, + 0, // Skip to: 8056 + /* 3808 */ MCD_OPC_CheckPredicate, + 0, + 11, + 0, + 0, // Skip to: 3824 + /* 3813 */ MCD_OPC_CheckField, + 11, + 2, + 0, + 4, + 0, + 0, // Skip to: 3824 + /* 3820 */ MCD_OPC_Decode, + 150, + 3, + 50, // Opcode: FMOVQ_FCC + /* 3824 */ MCD_OPC_CheckPredicate, + 0, + 131, + 16, + 0, // Skip to: 8056 + /* 3829 */ MCD_OPC_Decode, + 237, + 5, + 51, // Opcode: V9FMOVQ_FCC + /* 3833 */ MCD_OPC_FilterValue, + 1, + 122, + 16, + 0, // Skip to: 8056 + /* 3838 */ MCD_OPC_ExtractField, + 11, + 2, // Inst{12-11} ... + /* 3841 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 3862 + /* 3846 */ MCD_OPC_CheckPredicate, + 0, + 109, + 16, + 0, // Skip to: 8056 + /* 3851 */ MCD_OPC_CheckField, + 18, + 1, + 0, + 102, + 16, + 0, // Skip to: 8056 + /* 3858 */ MCD_OPC_Decode, + 151, + 3, + 50, // Opcode: FMOVQ_ICC + /* 3862 */ MCD_OPC_FilterValue, + 2, + 93, + 16, + 0, // Skip to: 8056 + /* 3867 */ MCD_OPC_CheckField, + 18, + 1, + 0, + 86, + 16, + 0, // Skip to: 8056 + /* 3874 */ MCD_OPC_Decode, + 152, + 3, + 50, // Opcode: FMOVQ_XCC + /* 3878 */ MCD_OPC_FilterValue, + 5, + 31, + 0, + 0, // Skip to: 3914 + /* 3883 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 3886 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3900 + /* 3891 */ MCD_OPC_CheckPredicate, + 0, + 64, + 16, + 0, // Skip to: 8056 + /* 3896 */ MCD_OPC_Decode, + 161, + 3, + 52, // Opcode: FMOVRLEZS + /* 3900 */ MCD_OPC_FilterValue, + 3, + 55, + 16, + 0, // Skip to: 8056 + /* 3905 */ MCD_OPC_CheckPredicate, + 0, + 50, + 16, + 0, // Skip to: 8056 + /* 3910 */ MCD_OPC_Decode, + 158, + 3, + 52, // Opcode: FMOVRGZS + /* 3914 */ MCD_OPC_FilterValue, + 6, + 31, + 0, + 0, // Skip to: 3950 + /* 3919 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 3922 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3936 + /* 3927 */ MCD_OPC_CheckPredicate, + 0, + 28, + 16, + 0, // Skip to: 8056 + /* 3932 */ MCD_OPC_Decode, + 159, + 3, + 52, // Opcode: FMOVRLEZD + /* 3936 */ MCD_OPC_FilterValue, + 3, + 19, + 16, + 0, // Skip to: 8056 + /* 3941 */ MCD_OPC_CheckPredicate, + 0, + 14, + 16, + 0, // Skip to: 8056 + /* 3946 */ MCD_OPC_Decode, + 156, + 3, + 52, // Opcode: FMOVRGZD + /* 3950 */ MCD_OPC_FilterValue, + 7, + 31, + 0, + 0, // Skip to: 3986 + /* 3955 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 3958 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 3972 + /* 3963 */ MCD_OPC_CheckPredicate, + 0, + 248, + 15, + 0, // Skip to: 8056 + /* 3968 */ MCD_OPC_Decode, + 160, + 3, + 52, // Opcode: FMOVRLEZQ + /* 3972 */ MCD_OPC_FilterValue, + 3, + 239, + 15, + 0, // Skip to: 8056 + /* 3977 */ MCD_OPC_CheckPredicate, + 0, + 234, + 15, + 0, // Skip to: 8056 + /* 3982 */ MCD_OPC_Decode, + 157, + 3, + 52, // Opcode: FMOVRGZQ + /* 3986 */ MCD_OPC_FilterValue, + 17, + 11, + 0, + 0, // Skip to: 4002 + /* 3991 */ MCD_OPC_CheckField, + 11, + 3, + 1, + 218, + 15, + 0, // Skip to: 8056 + /* 3998 */ MCD_OPC_Decode, + 235, + 5, + 53, // Opcode: V9FCMPS + /* 4002 */ MCD_OPC_FilterValue, + 18, + 11, + 0, + 0, // Skip to: 4018 + /* 4007 */ MCD_OPC_CheckField, + 11, + 3, + 1, + 202, + 15, + 0, // Skip to: 8056 + /* 4014 */ MCD_OPC_Decode, + 230, + 5, + 54, // Opcode: V9FCMPD + /* 4018 */ MCD_OPC_FilterValue, + 19, + 11, + 0, + 0, // Skip to: 4034 + /* 4023 */ MCD_OPC_CheckField, + 11, + 3, + 1, + 186, + 15, + 0, // Skip to: 8056 + /* 4030 */ MCD_OPC_Decode, + 234, + 5, + 55, // Opcode: V9FCMPQ + /* 4034 */ MCD_OPC_FilterValue, + 21, + 11, + 0, + 0, // Skip to: 4050 + /* 4039 */ MCD_OPC_CheckField, + 11, + 3, + 1, + 170, + 15, + 0, // Skip to: 8056 + /* 4046 */ MCD_OPC_Decode, + 233, + 5, + 53, // Opcode: V9FCMPES + /* 4050 */ MCD_OPC_FilterValue, + 22, + 11, + 0, + 0, // Skip to: 4066 + /* 4055 */ MCD_OPC_CheckField, + 11, + 3, + 1, + 154, + 15, + 0, // Skip to: 8056 + /* 4062 */ MCD_OPC_Decode, + 231, + 5, + 54, // Opcode: V9FCMPED + /* 4066 */ MCD_OPC_FilterValue, + 23, + 11, + 0, + 0, // Skip to: 4082 + /* 4071 */ MCD_OPC_CheckField, + 11, + 3, + 1, + 138, + 15, + 0, // Skip to: 8056 + /* 4078 */ MCD_OPC_Decode, + 232, + 5, + 55, // Opcode: V9FCMPEQ + /* 4082 */ MCD_OPC_FilterValue, + 37, + 59, + 0, + 0, // Skip to: 4146 + /* 4087 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 4090 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4104 + /* 4095 */ MCD_OPC_CheckPredicate, + 0, + 116, + 15, + 0, // Skip to: 8056 + /* 4100 */ MCD_OPC_Decode, + 170, + 3, + 52, // Opcode: FMOVRZS + /* 4104 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4118 + /* 4109 */ MCD_OPC_CheckPredicate, + 0, + 102, + 15, + 0, // Skip to: 8056 + /* 4114 */ MCD_OPC_Decode, + 164, + 3, + 52, // Opcode: FMOVRLZS + /* 4118 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4132 + /* 4123 */ MCD_OPC_CheckPredicate, + 0, + 88, + 15, + 0, // Skip to: 8056 + /* 4128 */ MCD_OPC_Decode, + 167, + 3, + 52, // Opcode: FMOVRNZS + /* 4132 */ MCD_OPC_FilterValue, + 3, + 79, + 15, + 0, // Skip to: 8056 + /* 4137 */ MCD_OPC_CheckPredicate, + 0, + 74, + 15, + 0, // Skip to: 8056 + /* 4142 */ MCD_OPC_Decode, + 155, + 3, + 52, // Opcode: FMOVRGEZS + /* 4146 */ MCD_OPC_FilterValue, + 38, + 59, + 0, + 0, // Skip to: 4210 + /* 4151 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 4154 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4168 + /* 4159 */ MCD_OPC_CheckPredicate, + 0, + 52, + 15, + 0, // Skip to: 8056 + /* 4164 */ MCD_OPC_Decode, + 168, + 3, + 52, // Opcode: FMOVRZD + /* 4168 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4182 + /* 4173 */ MCD_OPC_CheckPredicate, + 0, + 38, + 15, + 0, // Skip to: 8056 + /* 4178 */ MCD_OPC_Decode, + 162, + 3, + 52, // Opcode: FMOVRLZD + /* 4182 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4196 + /* 4187 */ MCD_OPC_CheckPredicate, + 0, + 24, + 15, + 0, // Skip to: 8056 + /* 4192 */ MCD_OPC_Decode, + 165, + 3, + 52, // Opcode: FMOVRNZD + /* 4196 */ MCD_OPC_FilterValue, + 3, + 15, + 15, + 0, // Skip to: 8056 + /* 4201 */ MCD_OPC_CheckPredicate, + 0, + 10, + 15, + 0, // Skip to: 8056 + /* 4206 */ MCD_OPC_Decode, + 153, + 3, + 52, // Opcode: FMOVRGEZD + /* 4210 */ MCD_OPC_FilterValue, + 39, + 1, + 15, + 0, // Skip to: 8056 + /* 4215 */ MCD_OPC_ExtractField, + 11, + 3, // Inst{13-11} ... + /* 4218 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4232 + /* 4223 */ MCD_OPC_CheckPredicate, + 0, + 244, + 14, + 0, // Skip to: 8056 + /* 4228 */ MCD_OPC_Decode, + 169, + 3, + 52, // Opcode: FMOVRZQ + /* 4232 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4246 + /* 4237 */ MCD_OPC_CheckPredicate, + 0, + 230, + 14, + 0, // Skip to: 8056 + /* 4242 */ MCD_OPC_Decode, + 163, + 3, + 52, // Opcode: FMOVRLZQ + /* 4246 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4260 + /* 4251 */ MCD_OPC_CheckPredicate, + 0, + 216, + 14, + 0, // Skip to: 8056 + /* 4256 */ MCD_OPC_Decode, + 166, + 3, + 52, // Opcode: FMOVRNZQ + /* 4260 */ MCD_OPC_FilterValue, + 3, + 207, + 14, + 0, // Skip to: 8056 + /* 4265 */ MCD_OPC_CheckPredicate, + 0, + 202, + 14, + 0, // Skip to: 8056 + /* 4270 */ MCD_OPC_Decode, + 154, + 3, + 52, // Opcode: FMOVRGEZQ + /* 4274 */ MCD_OPC_FilterValue, + 54, + 35, + 7, + 0, // Skip to: 6106 + /* 4279 */ MCD_OPC_ExtractField, + 5, + 9, // Inst{13-5} ... + /* 4282 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 4296 + /* 4287 */ MCD_OPC_CheckPredicate, + 3, + 180, + 14, + 0, // Skip to: 8056 + /* 4292 */ MCD_OPC_Decode, + 219, + 2, + 10, // Opcode: EDGE8 + /* 4296 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 4310 + /* 4301 */ MCD_OPC_CheckPredicate, + 4, + 166, + 14, + 0, // Skip to: 8056 + /* 4306 */ MCD_OPC_Decode, + 222, + 2, + 10, // Opcode: EDGE8N + /* 4310 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 4324 + /* 4315 */ MCD_OPC_CheckPredicate, + 3, + 152, + 14, + 0, // Skip to: 8056 + /* 4320 */ MCD_OPC_Decode, + 220, + 2, + 10, // Opcode: EDGE8L + /* 4324 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 4338 + /* 4329 */ MCD_OPC_CheckPredicate, + 4, + 138, + 14, + 0, // Skip to: 8056 + /* 4334 */ MCD_OPC_Decode, + 221, + 2, + 10, // Opcode: EDGE8LN + /* 4338 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 4352 + /* 4343 */ MCD_OPC_CheckPredicate, + 3, + 124, + 14, + 0, // Skip to: 8056 + /* 4348 */ MCD_OPC_Decode, + 211, + 2, + 10, // Opcode: EDGE16 + /* 4352 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 4366 + /* 4357 */ MCD_OPC_CheckPredicate, + 4, + 110, + 14, + 0, // Skip to: 8056 + /* 4362 */ MCD_OPC_Decode, + 214, + 2, + 10, // Opcode: EDGE16N + /* 4366 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 4380 + /* 4371 */ MCD_OPC_CheckPredicate, + 3, + 96, + 14, + 0, // Skip to: 8056 + /* 4376 */ MCD_OPC_Decode, + 212, + 2, + 10, // Opcode: EDGE16L + /* 4380 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 4394 + /* 4385 */ MCD_OPC_CheckPredicate, + 4, + 82, + 14, + 0, // Skip to: 8056 + /* 4390 */ MCD_OPC_Decode, + 213, + 2, + 10, // Opcode: EDGE16LN + /* 4394 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 4408 + /* 4399 */ MCD_OPC_CheckPredicate, + 3, + 68, + 14, + 0, // Skip to: 8056 + /* 4404 */ MCD_OPC_Decode, + 215, + 2, + 10, // Opcode: EDGE32 + /* 4408 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 4422 + /* 4413 */ MCD_OPC_CheckPredicate, + 4, + 54, + 14, + 0, // Skip to: 8056 + /* 4418 */ MCD_OPC_Decode, + 218, + 2, + 10, // Opcode: EDGE32N + /* 4422 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 4436 + /* 4427 */ MCD_OPC_CheckPredicate, + 3, + 40, + 14, + 0, // Skip to: 8056 + /* 4432 */ MCD_OPC_Decode, + 216, + 2, + 10, // Opcode: EDGE32L + /* 4436 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 4450 + /* 4441 */ MCD_OPC_CheckPredicate, + 4, + 26, + 14, + 0, // Skip to: 8056 + /* 4446 */ MCD_OPC_Decode, + 217, + 2, + 10, // Opcode: EDGE32LN + /* 4450 */ MCD_OPC_FilterValue, + 16, + 9, + 0, + 0, // Skip to: 4464 + /* 4455 */ MCD_OPC_CheckPredicate, + 3, + 12, + 14, + 0, // Skip to: 8056 + /* 4460 */ MCD_OPC_Decode, + 153, + 2, + 10, // Opcode: ARRAY8 + /* 4464 */ MCD_OPC_FilterValue, + 17, + 9, + 0, + 0, // Skip to: 4478 + /* 4469 */ MCD_OPC_CheckPredicate, + 2, + 254, + 13, + 0, // Skip to: 8056 + /* 4474 */ MCD_OPC_Decode, + 132, + 2, + 10, // Opcode: ADDXC + /* 4478 */ MCD_OPC_FilterValue, + 18, + 9, + 0, + 0, // Skip to: 4492 + /* 4483 */ MCD_OPC_CheckPredicate, + 3, + 240, + 13, + 0, // Skip to: 8056 + /* 4488 */ MCD_OPC_Decode, + 151, + 2, + 10, // Opcode: ARRAY16 + /* 4492 */ MCD_OPC_FilterValue, + 19, + 9, + 0, + 0, // Skip to: 4506 + /* 4497 */ MCD_OPC_CheckPredicate, + 2, + 226, + 13, + 0, // Skip to: 8056 + /* 4502 */ MCD_OPC_Decode, + 133, + 2, + 10, // Opcode: ADDXCCC + /* 4506 */ MCD_OPC_FilterValue, + 20, + 9, + 0, + 0, // Skip to: 4520 + /* 4511 */ MCD_OPC_CheckPredicate, + 3, + 212, + 13, + 0, // Skip to: 8056 + /* 4516 */ MCD_OPC_Decode, + 152, + 2, + 10, // Opcode: ARRAY32 + /* 4520 */ MCD_OPC_FilterValue, + 22, + 9, + 0, + 0, // Skip to: 4534 + /* 4525 */ MCD_OPC_CheckPredicate, + 2, + 198, + 13, + 0, // Skip to: 8056 + /* 4530 */ MCD_OPC_Decode, + 226, + 5, + 10, // Opcode: UMULXHI + /* 4534 */ MCD_OPC_FilterValue, + 23, + 16, + 0, + 0, // Skip to: 4555 + /* 4539 */ MCD_OPC_CheckPredicate, + 2, + 184, + 13, + 0, // Skip to: 8056 + /* 4544 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 177, + 13, + 0, // Skip to: 8056 + /* 4551 */ MCD_OPC_Decode, + 180, + 4, + 56, // Opcode: LZCNT + /* 4555 */ MCD_OPC_FilterValue, + 24, + 9, + 0, + 0, // Skip to: 4569 + /* 4560 */ MCD_OPC_CheckPredicate, + 3, + 163, + 13, + 0, // Skip to: 8056 + /* 4565 */ MCD_OPC_Decode, + 138, + 2, + 10, // Opcode: ALIGNADDR + /* 4569 */ MCD_OPC_FilterValue, + 25, + 9, + 0, + 0, // Skip to: 4583 + /* 4574 */ MCD_OPC_CheckPredicate, + 4, + 149, + 13, + 0, // Skip to: 8056 + /* 4579 */ MCD_OPC_Decode, + 159, + 2, + 10, // Opcode: BMASK + /* 4583 */ MCD_OPC_FilterValue, + 26, + 9, + 0, + 0, // Skip to: 4597 + /* 4588 */ MCD_OPC_CheckPredicate, + 3, + 135, + 13, + 0, // Skip to: 8056 + /* 4593 */ MCD_OPC_Decode, + 139, + 2, + 10, // Opcode: ALIGNADDRL + /* 4597 */ MCD_OPC_FilterValue, + 27, + 23, + 0, + 0, // Skip to: 4625 + /* 4602 */ MCD_OPC_CheckPredicate, + 2, + 121, + 13, + 0, // Skip to: 8056 + /* 4607 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 114, + 13, + 0, // Skip to: 8056 + /* 4614 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 107, + 13, + 0, // Skip to: 8056 + /* 4621 */ MCD_OPC_Decode, + 208, + 2, + 57, // Opcode: CMASK8 + /* 4625 */ MCD_OPC_FilterValue, + 28, + 9, + 0, + 0, // Skip to: 4639 + /* 4630 */ MCD_OPC_CheckPredicate, + 4, + 93, + 13, + 0, // Skip to: 8056 + /* 4635 */ MCD_OPC_Decode, + 196, + 2, + 36, // Opcode: BSHUFFLE + /* 4639 */ MCD_OPC_FilterValue, + 29, + 23, + 0, + 0, // Skip to: 4667 + /* 4644 */ MCD_OPC_CheckPredicate, + 2, + 79, + 13, + 0, // Skip to: 8056 + /* 4649 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 72, + 13, + 0, // Skip to: 8056 + /* 4656 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 65, + 13, + 0, // Skip to: 8056 + /* 4663 */ MCD_OPC_Decode, + 206, + 2, + 57, // Opcode: CMASK16 + /* 4667 */ MCD_OPC_FilterValue, + 31, + 23, + 0, + 0, // Skip to: 4695 + /* 4672 */ MCD_OPC_CheckPredicate, + 2, + 51, + 13, + 0, // Skip to: 8056 + /* 4677 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 44, + 13, + 0, // Skip to: 8056 + /* 4684 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 37, + 13, + 0, // Skip to: 8056 + /* 4691 */ MCD_OPC_Decode, + 207, + 2, + 57, // Opcode: CMASK32 + /* 4695 */ MCD_OPC_FilterValue, + 32, + 9, + 0, + 0, // Skip to: 4709 + /* 4700 */ MCD_OPC_CheckPredicate, + 3, + 23, + 13, + 0, // Skip to: 8056 + /* 4705 */ MCD_OPC_Decode, + 244, + 2, + 58, // Opcode: FCMPLE16 + /* 4709 */ MCD_OPC_FilterValue, + 33, + 9, + 0, + 0, // Skip to: 4723 + /* 4714 */ MCD_OPC_CheckPredicate, + 2, + 9, + 13, + 0, // Skip to: 8056 + /* 4719 */ MCD_OPC_Decode, + 230, + 3, + 36, // Opcode: FSLL16 + /* 4723 */ MCD_OPC_FilterValue, + 34, + 9, + 0, + 0, // Skip to: 4737 + /* 4728 */ MCD_OPC_CheckPredicate, + 3, + 251, + 12, + 0, // Skip to: 8056 + /* 4733 */ MCD_OPC_Decode, + 246, + 2, + 58, // Opcode: FCMPNE16 + /* 4737 */ MCD_OPC_FilterValue, + 35, + 9, + 0, + 0, // Skip to: 4751 + /* 4742 */ MCD_OPC_CheckPredicate, + 2, + 237, + 12, + 0, // Skip to: 8056 + /* 4747 */ MCD_OPC_Decode, + 242, + 3, + 36, // Opcode: FSRL16 + /* 4751 */ MCD_OPC_FilterValue, + 36, + 9, + 0, + 0, // Skip to: 4765 + /* 4756 */ MCD_OPC_CheckPredicate, + 3, + 223, + 12, + 0, // Skip to: 8056 + /* 4761 */ MCD_OPC_Decode, + 245, + 2, + 58, // Opcode: FCMPLE32 + /* 4765 */ MCD_OPC_FilterValue, + 37, + 9, + 0, + 0, // Skip to: 4779 + /* 4770 */ MCD_OPC_CheckPredicate, + 2, + 209, + 12, + 0, // Skip to: 8056 + /* 4775 */ MCD_OPC_Decode, + 231, + 3, + 36, // Opcode: FSLL32 + /* 4779 */ MCD_OPC_FilterValue, + 38, + 9, + 0, + 0, // Skip to: 4793 + /* 4784 */ MCD_OPC_CheckPredicate, + 3, + 195, + 12, + 0, // Skip to: 8056 + /* 4789 */ MCD_OPC_Decode, + 247, + 2, + 58, // Opcode: FCMPNE32 + /* 4793 */ MCD_OPC_FilterValue, + 39, + 9, + 0, + 0, // Skip to: 4807 + /* 4798 */ MCD_OPC_CheckPredicate, + 2, + 181, + 12, + 0, // Skip to: 8056 + /* 4803 */ MCD_OPC_Decode, + 243, + 3, + 36, // Opcode: FSRL32 + /* 4807 */ MCD_OPC_FilterValue, + 40, + 9, + 0, + 0, // Skip to: 4821 + /* 4812 */ MCD_OPC_CheckPredicate, + 3, + 167, + 12, + 0, // Skip to: 8056 + /* 4817 */ MCD_OPC_Decode, + 242, + 2, + 58, // Opcode: FCMPGT16 + /* 4821 */ MCD_OPC_FilterValue, + 41, + 9, + 0, + 0, // Skip to: 4835 + /* 4826 */ MCD_OPC_CheckPredicate, + 2, + 153, + 12, + 0, // Skip to: 8056 + /* 4831 */ MCD_OPC_Decode, + 228, + 3, + 36, // Opcode: FSLAS16 + /* 4835 */ MCD_OPC_FilterValue, + 42, + 9, + 0, + 0, // Skip to: 4849 + /* 4840 */ MCD_OPC_CheckPredicate, + 3, + 139, + 12, + 0, // Skip to: 8056 + /* 4845 */ MCD_OPC_Decode, + 240, + 2, + 58, // Opcode: FCMPEQ16 + /* 4849 */ MCD_OPC_FilterValue, + 43, + 9, + 0, + 0, // Skip to: 4863 + /* 4854 */ MCD_OPC_CheckPredicate, + 2, + 125, + 12, + 0, // Skip to: 8056 + /* 4859 */ MCD_OPC_Decode, + 236, + 3, + 36, // Opcode: FSRA16 + /* 4863 */ MCD_OPC_FilterValue, + 44, + 9, + 0, + 0, // Skip to: 4877 + /* 4868 */ MCD_OPC_CheckPredicate, + 3, + 111, + 12, + 0, // Skip to: 8056 + /* 4873 */ MCD_OPC_Decode, + 243, + 2, + 58, // Opcode: FCMPGT32 + /* 4877 */ MCD_OPC_FilterValue, + 45, + 9, + 0, + 0, // Skip to: 4891 + /* 4882 */ MCD_OPC_CheckPredicate, + 2, + 97, + 12, + 0, // Skip to: 8056 + /* 4887 */ MCD_OPC_Decode, + 229, + 3, + 36, // Opcode: FSLAS32 + /* 4891 */ MCD_OPC_FilterValue, + 46, + 9, + 0, + 0, // Skip to: 4905 + /* 4896 */ MCD_OPC_CheckPredicate, + 3, + 83, + 12, + 0, // Skip to: 8056 + /* 4901 */ MCD_OPC_Decode, + 241, + 2, + 58, // Opcode: FCMPEQ32 + /* 4905 */ MCD_OPC_FilterValue, + 47, + 9, + 0, + 0, // Skip to: 4919 + /* 4910 */ MCD_OPC_CheckPredicate, + 2, + 69, + 12, + 0, // Skip to: 8056 + /* 4915 */ MCD_OPC_Decode, + 237, + 3, + 36, // Opcode: FSRA32 + /* 4919 */ MCD_OPC_FilterValue, + 49, + 9, + 0, + 0, // Skip to: 4933 + /* 4924 */ MCD_OPC_CheckPredicate, + 3, + 55, + 12, + 0, // Skip to: 8056 + /* 4929 */ MCD_OPC_Decode, + 177, + 3, + 36, // Opcode: FMUL8X16 + /* 4933 */ MCD_OPC_FilterValue, + 51, + 9, + 0, + 0, // Skip to: 4947 + /* 4938 */ MCD_OPC_CheckPredicate, + 3, + 41, + 12, + 0, // Skip to: 8056 + /* 4943 */ MCD_OPC_Decode, + 179, + 3, + 36, // Opcode: FMUL8X16AU + /* 4947 */ MCD_OPC_FilterValue, + 53, + 9, + 0, + 0, // Skip to: 4961 + /* 4952 */ MCD_OPC_CheckPredicate, + 3, + 27, + 12, + 0, // Skip to: 8056 + /* 4957 */ MCD_OPC_Decode, + 178, + 3, + 36, // Opcode: FMUL8X16AL + /* 4961 */ MCD_OPC_FilterValue, + 54, + 9, + 0, + 0, // Skip to: 4975 + /* 4966 */ MCD_OPC_CheckPredicate, + 3, + 13, + 12, + 0, // Skip to: 8056 + /* 4971 */ MCD_OPC_Decode, + 175, + 3, + 36, // Opcode: FMUL8SUX16 + /* 4975 */ MCD_OPC_FilterValue, + 55, + 9, + 0, + 0, // Skip to: 4989 + /* 4980 */ MCD_OPC_CheckPredicate, + 3, + 255, + 11, + 0, // Skip to: 8056 + /* 4985 */ MCD_OPC_Decode, + 176, + 3, + 36, // Opcode: FMUL8ULX16 + /* 4989 */ MCD_OPC_FilterValue, + 56, + 9, + 0, + 0, // Skip to: 5003 + /* 4994 */ MCD_OPC_CheckPredicate, + 3, + 241, + 11, + 0, // Skip to: 8056 + /* 4999 */ MCD_OPC_Decode, + 181, + 3, + 36, // Opcode: FMULD8SUX16 + /* 5003 */ MCD_OPC_FilterValue, + 57, + 9, + 0, + 0, // Skip to: 5017 + /* 5008 */ MCD_OPC_CheckPredicate, + 3, + 227, + 11, + 0, // Skip to: 8056 + /* 5013 */ MCD_OPC_Decode, + 182, + 3, + 36, // Opcode: FMULD8ULX16 + /* 5017 */ MCD_OPC_FilterValue, + 58, + 9, + 0, + 0, // Skip to: 5031 + /* 5022 */ MCD_OPC_CheckPredicate, + 3, + 213, + 11, + 0, // Skip to: 8056 + /* 5027 */ MCD_OPC_Decode, + 212, + 3, + 36, // Opcode: FPACK32 + /* 5031 */ MCD_OPC_FilterValue, + 59, + 16, + 0, + 0, // Skip to: 5052 + /* 5036 */ MCD_OPC_CheckPredicate, + 3, + 199, + 11, + 0, // Skip to: 8056 + /* 5041 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 192, + 11, + 0, // Skip to: 8056 + /* 5048 */ MCD_OPC_Decode, + 211, + 3, + 33, // Opcode: FPACK16 + /* 5052 */ MCD_OPC_FilterValue, + 61, + 16, + 0, + 0, // Skip to: 5073 + /* 5057 */ MCD_OPC_CheckPredicate, + 3, + 178, + 11, + 0, // Skip to: 8056 + /* 5062 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 171, + 11, + 0, // Skip to: 8056 + /* 5069 */ MCD_OPC_Decode, + 213, + 3, + 33, // Opcode: FPACKFIX + /* 5073 */ MCD_OPC_FilterValue, + 62, + 9, + 0, + 0, // Skip to: 5087 + /* 5078 */ MCD_OPC_CheckPredicate, + 3, + 157, + 11, + 0, // Skip to: 8056 + /* 5083 */ MCD_OPC_Decode, + 221, + 4, + 36, // Opcode: PDIST + /* 5087 */ MCD_OPC_FilterValue, + 63, + 9, + 0, + 0, // Skip to: 5101 + /* 5092 */ MCD_OPC_CheckPredicate, + 2, + 143, + 11, + 0, // Skip to: 8056 + /* 5097 */ MCD_OPC_Decode, + 222, + 4, + 36, // Opcode: PDISTN + /* 5101 */ MCD_OPC_FilterValue, + 64, + 9, + 0, + 0, // Skip to: 5115 + /* 5106 */ MCD_OPC_CheckPredicate, + 2, + 129, + 11, + 0, // Skip to: 8056 + /* 5111 */ MCD_OPC_Decode, + 144, + 3, + 36, // Opcode: FMEAN16 + /* 5115 */ MCD_OPC_FilterValue, + 66, + 9, + 0, + 0, // Skip to: 5129 + /* 5120 */ MCD_OPC_CheckPredicate, + 2, + 115, + 11, + 0, // Skip to: 8056 + /* 5125 */ MCD_OPC_Decode, + 218, + 3, + 36, // Opcode: FPADD64 + /* 5129 */ MCD_OPC_FilterValue, + 68, + 9, + 0, + 0, // Skip to: 5143 + /* 5134 */ MCD_OPC_CheckPredicate, + 2, + 101, + 11, + 0, // Skip to: 8056 + /* 5139 */ MCD_OPC_Decode, + 238, + 2, + 36, // Opcode: FCHKSM16 + /* 5143 */ MCD_OPC_FilterValue, + 72, + 9, + 0, + 0, // Skip to: 5157 + /* 5148 */ MCD_OPC_CheckPredicate, + 3, + 87, + 11, + 0, // Skip to: 8056 + /* 5153 */ MCD_OPC_Decode, + 229, + 2, + 36, // Opcode: FALIGNADATA + /* 5157 */ MCD_OPC_FilterValue, + 75, + 9, + 0, + 0, // Skip to: 5171 + /* 5162 */ MCD_OPC_CheckPredicate, + 3, + 73, + 11, + 0, // Skip to: 8056 + /* 5167 */ MCD_OPC_Decode, + 219, + 3, + 36, // Opcode: FPMERGE + /* 5171 */ MCD_OPC_FilterValue, + 77, + 16, + 0, + 0, // Skip to: 5192 + /* 5176 */ MCD_OPC_CheckPredicate, + 3, + 59, + 11, + 0, // Skip to: 8056 + /* 5181 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 52, + 11, + 0, // Skip to: 8056 + /* 5188 */ MCD_OPC_Decode, + 130, + 3, + 33, // Opcode: FEXPAND + /* 5192 */ MCD_OPC_FilterValue, + 80, + 9, + 0, + 0, // Skip to: 5206 + /* 5197 */ MCD_OPC_CheckPredicate, + 3, + 38, + 11, + 0, // Skip to: 8056 + /* 5202 */ MCD_OPC_Decode, + 214, + 3, + 36, // Opcode: FPADD16 + /* 5206 */ MCD_OPC_FilterValue, + 81, + 9, + 0, + 0, // Skip to: 5220 + /* 5211 */ MCD_OPC_CheckPredicate, + 3, + 24, + 11, + 0, // Skip to: 8056 + /* 5216 */ MCD_OPC_Decode, + 215, + 3, + 36, // Opcode: FPADD16S + /* 5220 */ MCD_OPC_FilterValue, + 82, + 9, + 0, + 0, // Skip to: 5234 + /* 5225 */ MCD_OPC_CheckPredicate, + 3, + 10, + 11, + 0, // Skip to: 8056 + /* 5230 */ MCD_OPC_Decode, + 216, + 3, + 36, // Opcode: FPADD32 + /* 5234 */ MCD_OPC_FilterValue, + 83, + 9, + 0, + 0, // Skip to: 5248 + /* 5239 */ MCD_OPC_CheckPredicate, + 3, + 252, + 10, + 0, // Skip to: 8056 + /* 5244 */ MCD_OPC_Decode, + 217, + 3, + 36, // Opcode: FPADD32S + /* 5248 */ MCD_OPC_FilterValue, + 84, + 9, + 0, + 0, // Skip to: 5262 + /* 5253 */ MCD_OPC_CheckPredicate, + 3, + 238, + 10, + 0, // Skip to: 8056 + /* 5258 */ MCD_OPC_Decode, + 220, + 3, + 36, // Opcode: FPSUB16 + /* 5262 */ MCD_OPC_FilterValue, + 85, + 9, + 0, + 0, // Skip to: 5276 + /* 5267 */ MCD_OPC_CheckPredicate, + 3, + 224, + 10, + 0, // Skip to: 8056 + /* 5272 */ MCD_OPC_Decode, + 221, + 3, + 36, // Opcode: FPSUB16S + /* 5276 */ MCD_OPC_FilterValue, + 86, + 9, + 0, + 0, // Skip to: 5290 + /* 5281 */ MCD_OPC_CheckPredicate, + 3, + 210, + 10, + 0, // Skip to: 8056 + /* 5286 */ MCD_OPC_Decode, + 222, + 3, + 36, // Opcode: FPSUB32 + /* 5290 */ MCD_OPC_FilterValue, + 87, + 9, + 0, + 0, // Skip to: 5304 + /* 5295 */ MCD_OPC_CheckPredicate, + 3, + 196, + 10, + 0, // Skip to: 8056 + /* 5300 */ MCD_OPC_Decode, + 223, + 3, + 36, // Opcode: FPSUB32S + /* 5304 */ MCD_OPC_FilterValue, + 96, + 23, + 0, + 0, // Skip to: 5332 + /* 5309 */ MCD_OPC_CheckPredicate, + 3, + 182, + 10, + 0, // Skip to: 8056 + /* 5314 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 175, + 10, + 0, // Skip to: 8056 + /* 5321 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 168, + 10, + 0, // Skip to: 8056 + /* 5328 */ MCD_OPC_Decode, + 130, + 4, + 59, // Opcode: FZERO + /* 5332 */ MCD_OPC_FilterValue, + 97, + 23, + 0, + 0, // Skip to: 5360 + /* 5337 */ MCD_OPC_CheckPredicate, + 3, + 154, + 10, + 0, // Skip to: 8056 + /* 5342 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 147, + 10, + 0, // Skip to: 8056 + /* 5349 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 140, + 10, + 0, // Skip to: 8056 + /* 5356 */ MCD_OPC_Decode, + 131, + 4, + 60, // Opcode: FZEROS + /* 5360 */ MCD_OPC_FilterValue, + 98, + 9, + 0, + 0, // Skip to: 5374 + /* 5365 */ MCD_OPC_CheckPredicate, + 3, + 126, + 10, + 0, // Skip to: 8056 + /* 5370 */ MCD_OPC_Decode, + 196, + 3, + 36, // Opcode: FNOR + /* 5374 */ MCD_OPC_FilterValue, + 99, + 9, + 0, + 0, // Skip to: 5388 + /* 5379 */ MCD_OPC_CheckPredicate, + 3, + 112, + 10, + 0, // Skip to: 8056 + /* 5384 */ MCD_OPC_Decode, + 197, + 3, + 35, // Opcode: FNORS + /* 5388 */ MCD_OPC_FilterValue, + 100, + 9, + 0, + 0, // Skip to: 5402 + /* 5393 */ MCD_OPC_CheckPredicate, + 3, + 98, + 10, + 0, // Skip to: 8056 + /* 5398 */ MCD_OPC_Decode, + 233, + 2, + 36, // Opcode: FANDNOT2 + /* 5402 */ MCD_OPC_FilterValue, + 101, + 9, + 0, + 0, // Skip to: 5416 + /* 5407 */ MCD_OPC_CheckPredicate, + 3, + 84, + 10, + 0, // Skip to: 8056 + /* 5412 */ MCD_OPC_Decode, + 234, + 2, + 35, // Opcode: FANDNOT2S + /* 5416 */ MCD_OPC_FilterValue, + 102, + 16, + 0, + 0, // Skip to: 5437 + /* 5421 */ MCD_OPC_CheckPredicate, + 3, + 70, + 10, + 0, // Skip to: 8056 + /* 5426 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 63, + 10, + 0, // Skip to: 8056 + /* 5433 */ MCD_OPC_Decode, + 200, + 3, + 33, // Opcode: FNOT2 + /* 5437 */ MCD_OPC_FilterValue, + 103, + 16, + 0, + 0, // Skip to: 5458 + /* 5442 */ MCD_OPC_CheckPredicate, + 3, + 49, + 10, + 0, // Skip to: 8056 + /* 5447 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 42, + 10, + 0, // Skip to: 8056 + /* 5454 */ MCD_OPC_Decode, + 201, + 3, + 32, // Opcode: FNOT2S + /* 5458 */ MCD_OPC_FilterValue, + 104, + 9, + 0, + 0, // Skip to: 5472 + /* 5463 */ MCD_OPC_CheckPredicate, + 3, + 28, + 10, + 0, // Skip to: 8056 + /* 5468 */ MCD_OPC_Decode, + 231, + 2, + 36, // Opcode: FANDNOT1 + /* 5472 */ MCD_OPC_FilterValue, + 105, + 9, + 0, + 0, // Skip to: 5486 + /* 5477 */ MCD_OPC_CheckPredicate, + 3, + 14, + 10, + 0, // Skip to: 8056 + /* 5482 */ MCD_OPC_Decode, + 232, + 2, + 35, // Opcode: FANDNOT1S + /* 5486 */ MCD_OPC_FilterValue, + 106, + 16, + 0, + 0, // Skip to: 5507 + /* 5491 */ MCD_OPC_CheckPredicate, + 3, + 0, + 10, + 0, // Skip to: 8056 + /* 5496 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 249, + 9, + 0, // Skip to: 8056 + /* 5503 */ MCD_OPC_Decode, + 198, + 3, + 61, // Opcode: FNOT1 + /* 5507 */ MCD_OPC_FilterValue, + 107, + 16, + 0, + 0, // Skip to: 5528 + /* 5512 */ MCD_OPC_CheckPredicate, + 3, + 235, + 9, + 0, // Skip to: 8056 + /* 5517 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 228, + 9, + 0, // Skip to: 8056 + /* 5524 */ MCD_OPC_Decode, + 199, + 3, + 62, // Opcode: FNOT1S + /* 5528 */ MCD_OPC_FilterValue, + 108, + 9, + 0, + 0, // Skip to: 5542 + /* 5533 */ MCD_OPC_CheckPredicate, + 3, + 214, + 9, + 0, // Skip to: 8056 + /* 5538 */ MCD_OPC_Decode, + 253, + 3, + 36, // Opcode: FXOR + /* 5542 */ MCD_OPC_FilterValue, + 109, + 9, + 0, + 0, // Skip to: 5556 + /* 5547 */ MCD_OPC_CheckPredicate, + 3, + 200, + 9, + 0, // Skip to: 8056 + /* 5552 */ MCD_OPC_Decode, + 254, + 3, + 35, // Opcode: FXORS + /* 5556 */ MCD_OPC_FilterValue, + 110, + 9, + 0, + 0, // Skip to: 5570 + /* 5561 */ MCD_OPC_CheckPredicate, + 3, + 186, + 9, + 0, // Skip to: 8056 + /* 5566 */ MCD_OPC_Decode, + 187, + 3, + 36, // Opcode: FNAND + /* 5570 */ MCD_OPC_FilterValue, + 111, + 9, + 0, + 0, // Skip to: 5584 + /* 5575 */ MCD_OPC_CheckPredicate, + 3, + 172, + 9, + 0, // Skip to: 8056 + /* 5580 */ MCD_OPC_Decode, + 188, + 3, + 35, // Opcode: FNANDS + /* 5584 */ MCD_OPC_FilterValue, + 112, + 9, + 0, + 0, // Skip to: 5598 + /* 5589 */ MCD_OPC_CheckPredicate, + 3, + 158, + 9, + 0, // Skip to: 8056 + /* 5594 */ MCD_OPC_Decode, + 230, + 2, + 36, // Opcode: FAND + /* 5598 */ MCD_OPC_FilterValue, + 113, + 9, + 0, + 0, // Skip to: 5612 + /* 5603 */ MCD_OPC_CheckPredicate, + 3, + 144, + 9, + 0, // Skip to: 8056 + /* 5608 */ MCD_OPC_Decode, + 235, + 2, + 35, // Opcode: FANDS + /* 5612 */ MCD_OPC_FilterValue, + 114, + 9, + 0, + 0, // Skip to: 5626 + /* 5617 */ MCD_OPC_CheckPredicate, + 3, + 130, + 9, + 0, // Skip to: 8056 + /* 5622 */ MCD_OPC_Decode, + 251, + 3, + 36, // Opcode: FXNOR + /* 5626 */ MCD_OPC_FilterValue, + 115, + 9, + 0, + 0, // Skip to: 5640 + /* 5631 */ MCD_OPC_CheckPredicate, + 3, + 116, + 9, + 0, // Skip to: 8056 + /* 5636 */ MCD_OPC_Decode, + 252, + 3, + 35, // Opcode: FXNORS + /* 5640 */ MCD_OPC_FilterValue, + 116, + 16, + 0, + 0, // Skip to: 5661 + /* 5645 */ MCD_OPC_CheckPredicate, + 3, + 102, + 9, + 0, // Skip to: 8056 + /* 5650 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 95, + 9, + 0, // Skip to: 8056 + /* 5657 */ MCD_OPC_Decode, + 238, + 3, + 61, // Opcode: FSRC1 + /* 5661 */ MCD_OPC_FilterValue, + 117, + 16, + 0, + 0, // Skip to: 5682 + /* 5666 */ MCD_OPC_CheckPredicate, + 3, + 81, + 9, + 0, // Skip to: 8056 + /* 5671 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 74, + 9, + 0, // Skip to: 8056 + /* 5678 */ MCD_OPC_Decode, + 239, + 3, + 62, // Opcode: FSRC1S + /* 5682 */ MCD_OPC_FilterValue, + 118, + 9, + 0, + 0, // Skip to: 5696 + /* 5687 */ MCD_OPC_CheckPredicate, + 3, + 60, + 9, + 0, // Skip to: 8056 + /* 5692 */ MCD_OPC_Decode, + 208, + 3, + 36, // Opcode: FORNOT2 + /* 5696 */ MCD_OPC_FilterValue, + 119, + 9, + 0, + 0, // Skip to: 5710 + /* 5701 */ MCD_OPC_CheckPredicate, + 3, + 46, + 9, + 0, // Skip to: 8056 + /* 5706 */ MCD_OPC_Decode, + 209, + 3, + 35, // Opcode: FORNOT2S + /* 5710 */ MCD_OPC_FilterValue, + 120, + 16, + 0, + 0, // Skip to: 5731 + /* 5715 */ MCD_OPC_CheckPredicate, + 3, + 32, + 9, + 0, // Skip to: 8056 + /* 5720 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 25, + 9, + 0, // Skip to: 8056 + /* 5727 */ MCD_OPC_Decode, + 240, + 3, + 33, // Opcode: FSRC2 + /* 5731 */ MCD_OPC_FilterValue, + 121, + 16, + 0, + 0, // Skip to: 5752 + /* 5736 */ MCD_OPC_CheckPredicate, + 3, + 11, + 9, + 0, // Skip to: 8056 + /* 5741 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 4, + 9, + 0, // Skip to: 8056 + /* 5748 */ MCD_OPC_Decode, + 241, + 3, + 32, // Opcode: FSRC2S + /* 5752 */ MCD_OPC_FilterValue, + 122, + 9, + 0, + 0, // Skip to: 5766 + /* 5757 */ MCD_OPC_CheckPredicate, + 3, + 246, + 8, + 0, // Skip to: 8056 + /* 5762 */ MCD_OPC_Decode, + 206, + 3, + 36, // Opcode: FORNOT1 + /* 5766 */ MCD_OPC_FilterValue, + 123, + 9, + 0, + 0, // Skip to: 5780 + /* 5771 */ MCD_OPC_CheckPredicate, + 3, + 232, + 8, + 0, // Skip to: 8056 + /* 5776 */ MCD_OPC_Decode, + 207, + 3, + 35, // Opcode: FORNOT1S + /* 5780 */ MCD_OPC_FilterValue, + 124, + 9, + 0, + 0, // Skip to: 5794 + /* 5785 */ MCD_OPC_CheckPredicate, + 3, + 218, + 8, + 0, // Skip to: 8056 + /* 5790 */ MCD_OPC_Decode, + 205, + 3, + 36, // Opcode: FOR + /* 5794 */ MCD_OPC_FilterValue, + 125, + 9, + 0, + 0, // Skip to: 5808 + /* 5799 */ MCD_OPC_CheckPredicate, + 3, + 204, + 8, + 0, // Skip to: 8056 + /* 5804 */ MCD_OPC_Decode, + 210, + 3, + 35, // Opcode: FORS + /* 5808 */ MCD_OPC_FilterValue, + 126, + 23, + 0, + 0, // Skip to: 5836 + /* 5813 */ MCD_OPC_CheckPredicate, + 3, + 190, + 8, + 0, // Skip to: 8056 + /* 5818 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 183, + 8, + 0, // Skip to: 8056 + /* 5825 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 176, + 8, + 0, // Skip to: 8056 + /* 5832 */ MCD_OPC_Decode, + 203, + 3, + 59, // Opcode: FONE + /* 5836 */ MCD_OPC_FilterValue, + 127, + 23, + 0, + 0, // Skip to: 5864 + /* 5841 */ MCD_OPC_CheckPredicate, + 3, + 162, + 8, + 0, // Skip to: 8056 + /* 5846 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 155, + 8, + 0, // Skip to: 8056 + /* 5853 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 148, + 8, + 0, // Skip to: 8056 + /* 5860 */ MCD_OPC_Decode, + 204, + 3, + 60, // Opcode: FONES + /* 5864 */ MCD_OPC_FilterValue, + 128, + 1, + 30, + 0, + 0, // Skip to: 5900 + /* 5870 */ MCD_OPC_CheckPredicate, + 3, + 133, + 8, + 0, // Skip to: 8056 + /* 5875 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 126, + 8, + 0, // Skip to: 8056 + /* 5882 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 119, + 8, + 0, // Skip to: 8056 + /* 5889 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 112, + 8, + 0, // Skip to: 8056 + /* 5896 */ MCD_OPC_Decode, + 250, + 4, + 4, // Opcode: SHUTDOWN + /* 5900 */ MCD_OPC_FilterValue, + 129, + 1, + 30, + 0, + 0, // Skip to: 5936 + /* 5906 */ MCD_OPC_CheckPredicate, + 4, + 97, + 8, + 0, // Skip to: 8056 + /* 5911 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 90, + 8, + 0, // Skip to: 8056 + /* 5918 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 83, + 8, + 0, // Skip to: 8056 + /* 5925 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 76, + 8, + 0, // Skip to: 8056 + /* 5932 */ MCD_OPC_Decode, + 251, + 4, + 4, // Opcode: SIAM + /* 5936 */ MCD_OPC_FilterValue, + 144, + 2, + 16, + 0, + 0, // Skip to: 5958 + /* 5942 */ MCD_OPC_CheckPredicate, + 2, + 61, + 8, + 0, // Skip to: 8056 + /* 5947 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 54, + 8, + 0, // Skip to: 8056 + /* 5954 */ MCD_OPC_Decode, + 182, + 4, + 63, // Opcode: MOVDTOX + /* 5958 */ MCD_OPC_FilterValue, + 145, + 2, + 16, + 0, + 0, // Skip to: 5980 + /* 5964 */ MCD_OPC_CheckPredicate, + 2, + 39, + 8, + 0, // Skip to: 8056 + /* 5969 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 32, + 8, + 0, // Skip to: 8056 + /* 5976 */ MCD_OPC_Decode, + 200, + 4, + 63, // Opcode: MOVSTOUW + /* 5980 */ MCD_OPC_FilterValue, + 147, + 2, + 16, + 0, + 0, // Skip to: 6002 + /* 5986 */ MCD_OPC_CheckPredicate, + 2, + 17, + 8, + 0, // Skip to: 8056 + /* 5991 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 10, + 8, + 0, // Skip to: 8056 + /* 5998 */ MCD_OPC_Decode, + 199, + 4, + 63, // Opcode: MOVSTOSW + /* 6002 */ MCD_OPC_FilterValue, + 149, + 2, + 9, + 0, + 0, // Skip to: 6017 + /* 6008 */ MCD_OPC_CheckPredicate, + 2, + 251, + 7, + 0, // Skip to: 8056 + /* 6013 */ MCD_OPC_Decode, + 251, + 5, + 10, // Opcode: XMULX + /* 6017 */ MCD_OPC_FilterValue, + 151, + 2, + 9, + 0, + 0, // Skip to: 6032 + /* 6023 */ MCD_OPC_CheckPredicate, + 2, + 236, + 7, + 0, // Skip to: 8056 + /* 6028 */ MCD_OPC_Decode, + 252, + 5, + 10, // Opcode: XMULXHI + /* 6032 */ MCD_OPC_FilterValue, + 152, + 2, + 16, + 0, + 0, // Skip to: 6054 + /* 6038 */ MCD_OPC_CheckPredicate, + 2, + 221, + 7, + 0, // Skip to: 8056 + /* 6043 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 214, + 7, + 0, // Skip to: 8056 + /* 6050 */ MCD_OPC_Decode, + 204, + 4, + 64, // Opcode: MOVXTOD + /* 6054 */ MCD_OPC_FilterValue, + 153, + 2, + 16, + 0, + 0, // Skip to: 6076 + /* 6060 */ MCD_OPC_CheckPredicate, + 2, + 199, + 7, + 0, // Skip to: 8056 + /* 6065 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 192, + 7, + 0, // Skip to: 8056 + /* 6072 */ MCD_OPC_Decode, + 201, + 4, + 64, // Opcode: MOVWTOS + /* 6076 */ MCD_OPC_FilterValue, + 209, + 2, + 9, + 0, + 0, // Skip to: 6091 + /* 6082 */ MCD_OPC_CheckPredicate, + 2, + 177, + 7, + 0, // Skip to: 8056 + /* 6087 */ MCD_OPC_Decode, + 139, + 3, + 54, // Opcode: FLCMPS + /* 6091 */ MCD_OPC_FilterValue, + 210, + 2, + 167, + 7, + 0, // Skip to: 8056 + /* 6097 */ MCD_OPC_CheckPredicate, + 2, + 162, + 7, + 0, // Skip to: 8056 + /* 6102 */ MCD_OPC_Decode, + 138, + 3, + 54, // Opcode: FLCMPD + /* 6106 */ MCD_OPC_FilterValue, + 56, + 28, + 0, + 0, // Skip to: 6139 + /* 6111 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6114 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6130 + /* 6119 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 138, + 7, + 0, // Skip to: 8056 + /* 6126 */ MCD_OPC_Decode, + 133, + 4, + 65, // Opcode: JMPLrr + /* 6130 */ MCD_OPC_FilterValue, + 1, + 129, + 7, + 0, // Skip to: 8056 + /* 6135 */ MCD_OPC_Decode, + 132, + 4, + 65, // Opcode: JMPLri + /* 6139 */ MCD_OPC_FilterValue, + 57, + 42, + 0, + 0, // Skip to: 6186 + /* 6144 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6147 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 6170 + /* 6152 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 105, + 7, + 0, // Skip to: 8056 + /* 6159 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 98, + 7, + 0, // Skip to: 8056 + /* 6166 */ MCD_OPC_Decode, + 239, + 4, + 66, // Opcode: RETTrr + /* 6170 */ MCD_OPC_FilterValue, + 1, + 89, + 7, + 0, // Skip to: 8056 + /* 6175 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 82, + 7, + 0, // Skip to: 8056 + /* 6182 */ MCD_OPC_Decode, + 238, + 4, + 66, // Opcode: RETTri + /* 6186 */ MCD_OPC_FilterValue, + 58, + 119, + 0, + 0, // Skip to: 6310 + /* 6191 */ MCD_OPC_ExtractField, + 8, + 6, // Inst{13-8} ... + /* 6194 */ MCD_OPC_FilterValue, + 16, + 18, + 0, + 0, // Skip to: 6217 + /* 6199 */ MCD_OPC_CheckField, + 29, + 1, + 0, + 58, + 7, + 0, // Skip to: 8056 + /* 6206 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 51, + 7, + 0, // Skip to: 8056 + /* 6213 */ MCD_OPC_Decode, + 215, + 5, + 67, // Opcode: TXCCrr + /* 6217 */ MCD_OPC_FilterValue, + 32, + 72, + 0, + 0, // Skip to: 6294 + /* 6222 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 6225 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 6248 + /* 6230 */ MCD_OPC_CheckField, + 25, + 5, + 8, + 27, + 7, + 0, // Skip to: 8056 + /* 6237 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 20, + 7, + 0, // Skip to: 8056 + /* 6244 */ MCD_OPC_Decode, + 194, + 5, + 4, // Opcode: TA1 + /* 6248 */ MCD_OPC_FilterValue, + 3, + 18, + 0, + 0, // Skip to: 6271 + /* 6253 */ MCD_OPC_CheckField, + 25, + 5, + 8, + 4, + 7, + 0, // Skip to: 8056 + /* 6260 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 253, + 6, + 0, // Skip to: 8056 + /* 6267 */ MCD_OPC_Decode, + 195, + 5, + 4, // Opcode: TA3 + /* 6271 */ MCD_OPC_FilterValue, + 5, + 244, + 6, + 0, // Skip to: 8056 + /* 6276 */ MCD_OPC_CheckField, + 25, + 5, + 8, + 237, + 6, + 0, // Skip to: 8056 + /* 6283 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 230, + 6, + 0, // Skip to: 8056 + /* 6290 */ MCD_OPC_Decode, + 196, + 5, + 4, // Opcode: TA5 + /* 6294 */ MCD_OPC_FilterValue, + 48, + 221, + 6, + 0, // Skip to: 8056 + /* 6299 */ MCD_OPC_CheckField, + 29, + 1, + 0, + 214, + 6, + 0, // Skip to: 8056 + /* 6306 */ MCD_OPC_Decode, + 214, + 5, + 68, // Opcode: TXCCri + /* 6310 */ MCD_OPC_FilterValue, + 59, + 62, + 0, + 0, // Skip to: 6377 + /* 6315 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6318 */ MCD_OPC_FilterValue, + 0, + 38, + 0, + 0, // Skip to: 6361 + /* 6323 */ MCD_OPC_ExtractField, + 5, + 8, // Inst{12-5} ... + /* 6326 */ MCD_OPC_FilterValue, + 0, + 189, + 6, + 0, // Skip to: 8056 + /* 6331 */ MCD_OPC_ExtractField, + 25, + 5, // Inst{29-25} ... + /* 6334 */ MCD_OPC_FilterValue, + 0, + 181, + 6, + 0, // Skip to: 8056 + /* 6339 */ MCD_OPC_CheckField, + 14, + 5, + 0, + 11, + 0, + 0, // Skip to: 6357 + /* 6346 */ MCD_OPC_CheckField, + 0, + 5, + 0, + 4, + 0, + 0, // Skip to: 6357 + /* 6353 */ MCD_OPC_Decode, + 140, + 3, + 4, // Opcode: FLUSH + /* 6357 */ MCD_OPC_Decode, + 143, + 3, + 4, // Opcode: FLUSHrr + /* 6361 */ MCD_OPC_FilterValue, + 1, + 154, + 6, + 0, // Skip to: 8056 + /* 6366 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 147, + 6, + 0, // Skip to: 8056 + /* 6373 */ MCD_OPC_Decode, + 142, + 3, + 4, // Opcode: FLUSHri + /* 6377 */ MCD_OPC_FilterValue, + 60, + 28, + 0, + 0, // Skip to: 6410 + /* 6382 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6385 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6401 + /* 6390 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 123, + 6, + 0, // Skip to: 8056 + /* 6397 */ MCD_OPC_Decode, + 241, + 4, + 8, // Opcode: SAVErr + /* 6401 */ MCD_OPC_FilterValue, + 1, + 114, + 6, + 0, // Skip to: 8056 + /* 6406 */ MCD_OPC_Decode, + 240, + 4, + 9, // Opcode: SAVEri + /* 6410 */ MCD_OPC_FilterValue, + 61, + 28, + 0, + 0, // Skip to: 6443 + /* 6415 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6418 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6434 + /* 6423 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 90, + 6, + 0, // Skip to: 8056 + /* 6430 */ MCD_OPC_Decode, + 235, + 4, + 8, // Opcode: RESTORErr + /* 6434 */ MCD_OPC_FilterValue, + 1, + 81, + 6, + 0, // Skip to: 8056 + /* 6439 */ MCD_OPC_Decode, + 234, + 4, + 9, // Opcode: RESTOREri + /* 6443 */ MCD_OPC_FilterValue, + 62, + 28, + 0, + 0, // Skip to: 6476 + /* 6448 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6451 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6467 + /* 6456 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 57, + 6, + 0, // Skip to: 8056 + /* 6463 */ MCD_OPC_Decode, + 223, + 5, + 8, // Opcode: UMACrr + /* 6467 */ MCD_OPC_FilterValue, + 1, + 48, + 6, + 0, // Skip to: 8056 + /* 6472 */ MCD_OPC_Decode, + 222, + 5, + 9, // Opcode: UMACri + /* 6476 */ MCD_OPC_FilterValue, + 63, + 39, + 6, + 0, // Skip to: 8056 + /* 6481 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6484 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6500 + /* 6489 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 24, + 6, + 0, // Skip to: 8056 + /* 6496 */ MCD_OPC_Decode, + 130, + 5, + 8, // Opcode: SMACrr + /* 6500 */ MCD_OPC_FilterValue, + 1, + 15, + 6, + 0, // Skip to: 8056 + /* 6505 */ MCD_OPC_Decode, + 129, + 5, + 9, // Opcode: SMACri + /* 6509 */ MCD_OPC_FilterValue, + 3, + 6, + 6, + 0, // Skip to: 8056 + /* 6514 */ MCD_OPC_ExtractField, + 19, + 6, // Inst{24-19} ... + /* 6517 */ MCD_OPC_FilterValue, + 0, + 28, + 0, + 0, // Skip to: 6550 + /* 6522 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6525 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6541 + /* 6530 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 239, + 5, + 0, // Skip to: 8056 + /* 6537 */ MCD_OPC_Decode, + 177, + 4, + 69, // Opcode: LDrr + /* 6541 */ MCD_OPC_FilterValue, + 1, + 230, + 5, + 0, // Skip to: 8056 + /* 6546 */ MCD_OPC_Decode, + 176, + 4, + 69, // Opcode: LDri + /* 6550 */ MCD_OPC_FilterValue, + 1, + 28, + 0, + 0, // Skip to: 6583 + /* 6555 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6558 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6574 + /* 6563 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 206, + 5, + 0, // Skip to: 8056 + /* 6570 */ MCD_OPC_Decode, + 168, + 4, + 69, // Opcode: LDUBrr + /* 6574 */ MCD_OPC_FilterValue, + 1, + 197, + 5, + 0, // Skip to: 8056 + /* 6579 */ MCD_OPC_Decode, + 167, + 4, + 69, // Opcode: LDUBri + /* 6583 */ MCD_OPC_FilterValue, + 2, + 28, + 0, + 0, // Skip to: 6616 + /* 6588 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6591 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6607 + /* 6596 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 173, + 5, + 0, // Skip to: 8056 + /* 6603 */ MCD_OPC_Decode, + 171, + 4, + 69, // Opcode: LDUHrr + /* 6607 */ MCD_OPC_FilterValue, + 1, + 164, + 5, + 0, // Skip to: 8056 + /* 6612 */ MCD_OPC_Decode, + 170, + 4, + 69, // Opcode: LDUHri + /* 6616 */ MCD_OPC_FilterValue, + 3, + 28, + 0, + 0, // Skip to: 6649 + /* 6621 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6624 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6640 + /* 6629 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 140, + 5, + 0, // Skip to: 8056 + /* 6636 */ MCD_OPC_Decode, + 146, + 4, + 70, // Opcode: LDDrr + /* 6640 */ MCD_OPC_FilterValue, + 1, + 131, + 5, + 0, // Skip to: 8056 + /* 6645 */ MCD_OPC_Decode, + 145, + 4, + 70, // Opcode: LDDri + /* 6649 */ MCD_OPC_FilterValue, + 4, + 28, + 0, + 0, // Skip to: 6682 + /* 6654 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6657 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6673 + /* 6662 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 107, + 5, + 0, // Skip to: 8056 + /* 6669 */ MCD_OPC_Decode, + 180, + 5, + 71, // Opcode: STrr + /* 6673 */ MCD_OPC_FilterValue, + 1, + 98, + 5, + 0, // Skip to: 8056 + /* 6678 */ MCD_OPC_Decode, + 179, + 5, + 71, // Opcode: STri + /* 6682 */ MCD_OPC_FilterValue, + 5, + 28, + 0, + 0, // Skip to: 6715 + /* 6687 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6690 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6706 + /* 6695 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 74, + 5, + 0, // Skip to: 8056 + /* 6702 */ MCD_OPC_Decode, + 147, + 5, + 71, // Opcode: STBrr + /* 6706 */ MCD_OPC_FilterValue, + 1, + 65, + 5, + 0, // Skip to: 8056 + /* 6711 */ MCD_OPC_Decode, + 146, + 5, + 71, // Opcode: STBri + /* 6715 */ MCD_OPC_FilterValue, + 6, + 28, + 0, + 0, // Skip to: 6748 + /* 6720 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6723 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6739 + /* 6728 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 41, + 5, + 0, // Skip to: 8056 + /* 6735 */ MCD_OPC_Decode, + 171, + 5, + 71, // Opcode: STHrr + /* 6739 */ MCD_OPC_FilterValue, + 1, + 32, + 5, + 0, // Skip to: 8056 + /* 6744 */ MCD_OPC_Decode, + 170, + 5, + 71, // Opcode: STHri + /* 6748 */ MCD_OPC_FilterValue, + 7, + 28, + 0, + 0, // Skip to: 6781 + /* 6753 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6756 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6772 + /* 6761 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 8, + 5, + 0, // Skip to: 8056 + /* 6768 */ MCD_OPC_Decode, + 163, + 5, + 72, // Opcode: STDrr + /* 6772 */ MCD_OPC_FilterValue, + 1, + 255, + 4, + 0, // Skip to: 8056 + /* 6777 */ MCD_OPC_Decode, + 162, + 5, + 72, // Opcode: STDri + /* 6781 */ MCD_OPC_FilterValue, + 8, + 28, + 0, + 0, // Skip to: 6814 + /* 6786 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6789 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6805 + /* 6794 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 231, + 4, + 0, // Skip to: 8056 + /* 6801 */ MCD_OPC_Decode, + 165, + 4, + 69, // Opcode: LDSWrr + /* 6805 */ MCD_OPC_FilterValue, + 1, + 222, + 4, + 0, // Skip to: 8056 + /* 6810 */ MCD_OPC_Decode, + 164, + 4, + 69, // Opcode: LDSWri + /* 6814 */ MCD_OPC_FilterValue, + 9, + 28, + 0, + 0, // Skip to: 6847 + /* 6819 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6822 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6838 + /* 6827 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 198, + 4, + 0, // Skip to: 8056 + /* 6834 */ MCD_OPC_Decode, + 157, + 4, + 69, // Opcode: LDSBrr + /* 6838 */ MCD_OPC_FilterValue, + 1, + 189, + 4, + 0, // Skip to: 8056 + /* 6843 */ MCD_OPC_Decode, + 156, + 4, + 69, // Opcode: LDSBri + /* 6847 */ MCD_OPC_FilterValue, + 10, + 28, + 0, + 0, // Skip to: 6880 + /* 6852 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6855 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6871 + /* 6860 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 165, + 4, + 0, // Skip to: 8056 + /* 6867 */ MCD_OPC_Decode, + 160, + 4, + 69, // Opcode: LDSHrr + /* 6871 */ MCD_OPC_FilterValue, + 1, + 156, + 4, + 0, // Skip to: 8056 + /* 6876 */ MCD_OPC_Decode, + 159, + 4, + 69, // Opcode: LDSHri + /* 6880 */ MCD_OPC_FilterValue, + 11, + 28, + 0, + 0, // Skip to: 6913 + /* 6885 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6888 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6904 + /* 6893 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 132, + 4, + 0, // Skip to: 8056 + /* 6900 */ MCD_OPC_Decode, + 175, + 4, + 69, // Opcode: LDXrr + /* 6904 */ MCD_OPC_FilterValue, + 1, + 123, + 4, + 0, // Skip to: 8056 + /* 6909 */ MCD_OPC_Decode, + 174, + 4, + 69, // Opcode: LDXri + /* 6913 */ MCD_OPC_FilterValue, + 13, + 28, + 0, + 0, // Skip to: 6946 + /* 6918 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6921 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6937 + /* 6926 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 99, + 4, + 0, // Skip to: 8056 + /* 6933 */ MCD_OPC_Decode, + 163, + 4, + 4, // Opcode: LDSTUBrr + /* 6937 */ MCD_OPC_FilterValue, + 1, + 90, + 4, + 0, // Skip to: 8056 + /* 6942 */ MCD_OPC_Decode, + 162, + 4, + 4, // Opcode: LDSTUBri + /* 6946 */ MCD_OPC_FilterValue, + 14, + 28, + 0, + 0, // Skip to: 6979 + /* 6951 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6954 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6970 + /* 6959 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 66, + 4, + 0, // Skip to: 8056 + /* 6966 */ MCD_OPC_Decode, + 178, + 5, + 71, // Opcode: STXrr + /* 6970 */ MCD_OPC_FilterValue, + 1, + 57, + 4, + 0, // Skip to: 8056 + /* 6975 */ MCD_OPC_Decode, + 177, + 5, + 71, // Opcode: STXri + /* 6979 */ MCD_OPC_FilterValue, + 15, + 28, + 0, + 0, // Skip to: 7012 + /* 6984 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 6987 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 7003 + /* 6992 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 33, + 4, + 0, // Skip to: 8056 + /* 6999 */ MCD_OPC_Decode, + 193, + 5, + 73, // Opcode: SWAPrr + /* 7003 */ MCD_OPC_FilterValue, + 1, + 24, + 4, + 0, // Skip to: 8056 + /* 7008 */ MCD_OPC_Decode, + 192, + 5, + 73, // Opcode: SWAPri + /* 7012 */ MCD_OPC_FilterValue, + 16, + 11, + 0, + 0, // Skip to: 7028 + /* 7017 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 8, + 4, + 0, // Skip to: 8056 + /* 7024 */ MCD_OPC_Decode, + 134, + 4, + 69, // Opcode: LDArr + /* 7028 */ MCD_OPC_FilterValue, + 17, + 11, + 0, + 0, // Skip to: 7044 + /* 7033 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 248, + 3, + 0, // Skip to: 8056 + /* 7040 */ MCD_OPC_Decode, + 166, + 4, + 69, // Opcode: LDUBArr + /* 7044 */ MCD_OPC_FilterValue, + 18, + 11, + 0, + 0, // Skip to: 7060 + /* 7049 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 232, + 3, + 0, // Skip to: 8056 + /* 7056 */ MCD_OPC_Decode, + 169, + 4, + 69, // Opcode: LDUHArr + /* 7060 */ MCD_OPC_FilterValue, + 19, + 11, + 0, + 0, // Skip to: 7076 + /* 7065 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 216, + 3, + 0, // Skip to: 8056 + /* 7072 */ MCD_OPC_Decode, + 139, + 4, + 70, // Opcode: LDDArr + /* 7076 */ MCD_OPC_FilterValue, + 20, + 11, + 0, + 0, // Skip to: 7092 + /* 7081 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 200, + 3, + 0, // Skip to: 8056 + /* 7088 */ MCD_OPC_Decode, + 143, + 5, + 71, // Opcode: STArr + /* 7092 */ MCD_OPC_FilterValue, + 21, + 11, + 0, + 0, // Skip to: 7108 + /* 7097 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 184, + 3, + 0, // Skip to: 8056 + /* 7104 */ MCD_OPC_Decode, + 145, + 5, + 71, // Opcode: STBArr + /* 7108 */ MCD_OPC_FilterValue, + 22, + 11, + 0, + 0, // Skip to: 7124 + /* 7113 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 168, + 3, + 0, // Skip to: 8056 + /* 7120 */ MCD_OPC_Decode, + 169, + 5, + 71, // Opcode: STHArr + /* 7124 */ MCD_OPC_FilterValue, + 23, + 11, + 0, + 0, // Skip to: 7140 + /* 7129 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 152, + 3, + 0, // Skip to: 8056 + /* 7136 */ MCD_OPC_Decode, + 152, + 5, + 72, // Opcode: STDArr + /* 7140 */ MCD_OPC_FilterValue, + 25, + 11, + 0, + 0, // Skip to: 7156 + /* 7145 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 136, + 3, + 0, // Skip to: 8056 + /* 7152 */ MCD_OPC_Decode, + 155, + 4, + 69, // Opcode: LDSBArr + /* 7156 */ MCD_OPC_FilterValue, + 26, + 11, + 0, + 0, // Skip to: 7172 + /* 7161 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 120, + 3, + 0, // Skip to: 8056 + /* 7168 */ MCD_OPC_Decode, + 158, + 4, + 69, // Opcode: LDSHArr + /* 7172 */ MCD_OPC_FilterValue, + 29, + 11, + 0, + 0, // Skip to: 7188 + /* 7177 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 104, + 3, + 0, // Skip to: 8056 + /* 7184 */ MCD_OPC_Decode, + 161, + 4, + 74, // Opcode: LDSTUBArr + /* 7188 */ MCD_OPC_FilterValue, + 31, + 11, + 0, + 0, // Skip to: 7204 + /* 7193 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 88, + 3, + 0, // Skip to: 8056 + /* 7200 */ MCD_OPC_Decode, + 191, + 5, + 73, // Opcode: SWAPArr + /* 7204 */ MCD_OPC_FilterValue, + 32, + 28, + 0, + 0, // Skip to: 7237 + /* 7209 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7212 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 7228 + /* 7217 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 64, + 3, + 0, // Skip to: 8056 + /* 7224 */ MCD_OPC_Decode, + 151, + 4, + 75, // Opcode: LDFrr + /* 7228 */ MCD_OPC_FilterValue, + 1, + 55, + 3, + 0, // Skip to: 8056 + /* 7233 */ MCD_OPC_Decode, + 150, + 4, + 75, // Opcode: LDFri + /* 7237 */ MCD_OPC_FilterValue, + 33, + 79, + 0, + 0, // Skip to: 7321 + /* 7242 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7245 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 7290 + /* 7250 */ MCD_OPC_ExtractField, + 25, + 5, // Inst{29-25} ... + /* 7253 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 7269 + /* 7258 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 23, + 3, + 0, // Skip to: 8056 + /* 7265 */ MCD_OPC_Decode, + 149, + 4, + 75, // Opcode: LDFSRrr + /* 7269 */ MCD_OPC_FilterValue, + 1, + 14, + 3, + 0, // Skip to: 8056 + /* 7274 */ MCD_OPC_CheckPredicate, + 0, + 9, + 3, + 0, // Skip to: 8056 + /* 7279 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 2, + 3, + 0, // Skip to: 8056 + /* 7286 */ MCD_OPC_Decode, + 173, + 4, + 75, // Opcode: LDXFSRrr + /* 7290 */ MCD_OPC_FilterValue, + 1, + 249, + 2, + 0, // Skip to: 8056 + /* 7295 */ MCD_OPC_ExtractField, + 25, + 5, // Inst{29-25} ... + /* 7298 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 7307 + /* 7303 */ MCD_OPC_Decode, + 148, + 4, + 75, // Opcode: LDFSRri + /* 7307 */ MCD_OPC_FilterValue, + 1, + 232, + 2, + 0, // Skip to: 8056 + /* 7312 */ MCD_OPC_CheckPredicate, + 0, + 227, + 2, + 0, // Skip to: 8056 + /* 7317 */ MCD_OPC_Decode, + 172, + 4, + 75, // Opcode: LDXFSRri + /* 7321 */ MCD_OPC_FilterValue, + 34, + 38, + 0, + 0, // Skip to: 7364 + /* 7326 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7329 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 7350 + /* 7334 */ MCD_OPC_CheckPredicate, + 0, + 205, + 2, + 0, // Skip to: 8056 + /* 7339 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 198, + 2, + 0, // Skip to: 8056 + /* 7346 */ MCD_OPC_Decode, + 154, + 4, + 76, // Opcode: LDQFrr + /* 7350 */ MCD_OPC_FilterValue, + 1, + 189, + 2, + 0, // Skip to: 8056 + /* 7355 */ MCD_OPC_CheckPredicate, + 0, + 184, + 2, + 0, // Skip to: 8056 + /* 7360 */ MCD_OPC_Decode, + 153, + 4, + 76, // Opcode: LDQFri + /* 7364 */ MCD_OPC_FilterValue, + 35, + 28, + 0, + 0, // Skip to: 7397 + /* 7369 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7372 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 7388 + /* 7377 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 160, + 2, + 0, // Skip to: 8056 + /* 7384 */ MCD_OPC_Decode, + 144, + 4, + 77, // Opcode: LDDFrr + /* 7388 */ MCD_OPC_FilterValue, + 1, + 151, + 2, + 0, // Skip to: 8056 + /* 7393 */ MCD_OPC_Decode, + 143, + 4, + 77, // Opcode: LDDFri + /* 7397 */ MCD_OPC_FilterValue, + 36, + 28, + 0, + 0, // Skip to: 7430 + /* 7402 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7405 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 7421 + /* 7410 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 127, + 2, + 0, // Skip to: 8056 + /* 7417 */ MCD_OPC_Decode, + 168, + 5, + 78, // Opcode: STFrr + /* 7421 */ MCD_OPC_FilterValue, + 1, + 118, + 2, + 0, // Skip to: 8056 + /* 7426 */ MCD_OPC_Decode, + 167, + 5, + 78, // Opcode: STFri + /* 7430 */ MCD_OPC_FilterValue, + 37, + 79, + 0, + 0, // Skip to: 7514 + /* 7435 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7438 */ MCD_OPC_FilterValue, + 0, + 40, + 0, + 0, // Skip to: 7483 + /* 7443 */ MCD_OPC_ExtractField, + 25, + 5, // Inst{29-25} ... + /* 7446 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 7462 + /* 7451 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 86, + 2, + 0, // Skip to: 8056 + /* 7458 */ MCD_OPC_Decode, + 166, + 5, + 78, // Opcode: STFSRrr + /* 7462 */ MCD_OPC_FilterValue, + 1, + 77, + 2, + 0, // Skip to: 8056 + /* 7467 */ MCD_OPC_CheckPredicate, + 0, + 72, + 2, + 0, // Skip to: 8056 + /* 7472 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 65, + 2, + 0, // Skip to: 8056 + /* 7479 */ MCD_OPC_Decode, + 176, + 5, + 78, // Opcode: STXFSRrr + /* 7483 */ MCD_OPC_FilterValue, + 1, + 56, + 2, + 0, // Skip to: 8056 + /* 7488 */ MCD_OPC_ExtractField, + 25, + 5, // Inst{29-25} ... + /* 7491 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 7500 + /* 7496 */ MCD_OPC_Decode, + 165, + 5, + 78, // Opcode: STFSRri + /* 7500 */ MCD_OPC_FilterValue, + 1, + 39, + 2, + 0, // Skip to: 8056 + /* 7505 */ MCD_OPC_CheckPredicate, + 0, + 34, + 2, + 0, // Skip to: 8056 + /* 7510 */ MCD_OPC_Decode, + 175, + 5, + 78, // Opcode: STXFSRri + /* 7514 */ MCD_OPC_FilterValue, + 38, + 61, + 0, + 0, // Skip to: 7580 + /* 7519 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7522 */ MCD_OPC_FilterValue, + 0, + 28, + 0, + 0, // Skip to: 7555 + /* 7527 */ MCD_OPC_ExtractField, + 5, + 8, // Inst{12-5} ... + /* 7530 */ MCD_OPC_FilterValue, + 0, + 9, + 2, + 0, // Skip to: 8056 + /* 7535 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 4, + 0, + 0, // Skip to: 7546 + /* 7542 */ MCD_OPC_Decode, + 159, + 5, + 78, // Opcode: STDFQrr + /* 7546 */ MCD_OPC_CheckPredicate, + 0, + 249, + 1, + 0, // Skip to: 8056 + /* 7551 */ MCD_OPC_Decode, + 174, + 5, + 79, // Opcode: STQFrr + /* 7555 */ MCD_OPC_FilterValue, + 1, + 240, + 1, + 0, // Skip to: 8056 + /* 7560 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 4, + 0, + 0, // Skip to: 7571 + /* 7567 */ MCD_OPC_Decode, + 158, + 5, + 78, // Opcode: STDFQri + /* 7571 */ MCD_OPC_CheckPredicate, + 0, + 224, + 1, + 0, // Skip to: 8056 + /* 7576 */ MCD_OPC_Decode, + 173, + 5, + 79, // Opcode: STQFri + /* 7580 */ MCD_OPC_FilterValue, + 39, + 28, + 0, + 0, // Skip to: 7613 + /* 7585 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7588 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 7604 + /* 7593 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 200, + 1, + 0, // Skip to: 8056 + /* 7600 */ MCD_OPC_Decode, + 161, + 5, + 80, // Opcode: STDFrr + /* 7604 */ MCD_OPC_FilterValue, + 1, + 191, + 1, + 0, // Skip to: 8056 + /* 7609 */ MCD_OPC_Decode, + 160, + 5, + 80, // Opcode: STDFri + /* 7613 */ MCD_OPC_FilterValue, + 45, + 38, + 0, + 0, // Skip to: 7656 + /* 7618 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7621 */ MCD_OPC_FilterValue, + 0, + 16, + 0, + 0, // Skip to: 7642 + /* 7626 */ MCD_OPC_CheckPredicate, + 0, + 169, + 1, + 0, // Skip to: 8056 + /* 7631 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 162, + 1, + 0, // Skip to: 8056 + /* 7638 */ MCD_OPC_Decode, + 225, + 4, + 81, // Opcode: PREFETCHr + /* 7642 */ MCD_OPC_FilterValue, + 1, + 153, + 1, + 0, // Skip to: 8056 + /* 7647 */ MCD_OPC_CheckPredicate, + 0, + 148, + 1, + 0, // Skip to: 8056 + /* 7652 */ MCD_OPC_Decode, + 224, + 4, + 81, // Opcode: PREFETCHi + /* 7656 */ MCD_OPC_FilterValue, + 48, + 37, + 0, + 0, // Skip to: 7698 + /* 7661 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7664 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 7689 + /* 7669 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 4, + 0, + 0, // Skip to: 7680 + /* 7676 */ MCD_OPC_Decode, + 138, + 4, + 82, // Opcode: LDCrr + /* 7680 */ MCD_OPC_CheckPredicate, + 0, + 115, + 1, + 0, // Skip to: 8056 + /* 7685 */ MCD_OPC_Decode, + 147, + 4, + 75, // Opcode: LDFArr + /* 7689 */ MCD_OPC_FilterValue, + 1, + 106, + 1, + 0, // Skip to: 8056 + /* 7694 */ MCD_OPC_Decode, + 137, + 4, + 82, // Opcode: LDCri + /* 7698 */ MCD_OPC_FilterValue, + 49, + 42, + 0, + 0, // Skip to: 7745 + /* 7703 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7706 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 7729 + /* 7711 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 82, + 1, + 0, // Skip to: 8056 + /* 7718 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 75, + 1, + 0, // Skip to: 8056 + /* 7725 */ MCD_OPC_Decode, + 136, + 4, + 82, // Opcode: LDCSRrr + /* 7729 */ MCD_OPC_FilterValue, + 1, + 66, + 1, + 0, // Skip to: 8056 + /* 7734 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 59, + 1, + 0, // Skip to: 8056 + /* 7741 */ MCD_OPC_Decode, + 135, + 4, + 82, // Opcode: LDCSRri + /* 7745 */ MCD_OPC_FilterValue, + 50, + 16, + 0, + 0, // Skip to: 7766 + /* 7750 */ MCD_OPC_CheckPredicate, + 0, + 45, + 1, + 0, // Skip to: 8056 + /* 7755 */ MCD_OPC_CheckField, + 13, + 1, + 0, + 38, + 1, + 0, // Skip to: 8056 + /* 7762 */ MCD_OPC_Decode, + 152, + 4, + 76, // Opcode: LDQFArr + /* 7766 */ MCD_OPC_FilterValue, + 51, + 37, + 0, + 0, // Skip to: 7808 + /* 7771 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7774 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 7799 + /* 7779 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 4, + 0, + 0, // Skip to: 7790 + /* 7786 */ MCD_OPC_Decode, + 141, + 4, + 83, // Opcode: LDDCrr + /* 7790 */ MCD_OPC_CheckPredicate, + 0, + 5, + 1, + 0, // Skip to: 8056 + /* 7795 */ MCD_OPC_Decode, + 142, + 4, + 77, // Opcode: LDDFArr + /* 7799 */ MCD_OPC_FilterValue, + 1, + 252, + 0, + 0, // Skip to: 8056 + /* 7804 */ MCD_OPC_Decode, + 140, + 4, + 83, // Opcode: LDDCri + /* 7808 */ MCD_OPC_FilterValue, + 52, + 37, + 0, + 0, // Skip to: 7850 + /* 7813 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7816 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 7841 + /* 7821 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 4, + 0, + 0, // Skip to: 7832 + /* 7828 */ MCD_OPC_Decode, + 151, + 5, + 84, // Opcode: STCrr + /* 7832 */ MCD_OPC_CheckPredicate, + 0, + 219, + 0, + 0, // Skip to: 8056 + /* 7837 */ MCD_OPC_Decode, + 164, + 5, + 78, // Opcode: STFArr + /* 7841 */ MCD_OPC_FilterValue, + 1, + 210, + 0, + 0, // Skip to: 8056 + /* 7846 */ MCD_OPC_Decode, + 150, + 5, + 84, // Opcode: STCri + /* 7850 */ MCD_OPC_FilterValue, + 53, + 42, + 0, + 0, // Skip to: 7897 + /* 7855 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7858 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 7881 + /* 7863 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 186, + 0, + 0, // Skip to: 8056 + /* 7870 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 179, + 0, + 0, // Skip to: 8056 + /* 7877 */ MCD_OPC_Decode, + 149, + 5, + 84, // Opcode: STCSRrr + /* 7881 */ MCD_OPC_FilterValue, + 1, + 170, + 0, + 0, // Skip to: 8056 + /* 7886 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 163, + 0, + 0, // Skip to: 8056 + /* 7893 */ MCD_OPC_Decode, + 148, + 5, + 84, // Opcode: STCSRri + /* 7897 */ MCD_OPC_FilterValue, + 54, + 51, + 0, + 0, // Skip to: 7953 + /* 7902 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7905 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 7937 + /* 7910 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 11, + 0, + 0, // Skip to: 7928 + /* 7917 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 4, + 0, + 0, // Skip to: 7928 + /* 7924 */ MCD_OPC_Decode, + 154, + 5, + 84, // Opcode: STDCQrr + /* 7928 */ MCD_OPC_CheckPredicate, + 0, + 123, + 0, + 0, // Skip to: 8056 + /* 7933 */ MCD_OPC_Decode, + 172, + 5, + 79, // Opcode: STQFArr + /* 7937 */ MCD_OPC_FilterValue, + 1, + 114, + 0, + 0, // Skip to: 8056 + /* 7942 */ MCD_OPC_CheckField, + 25, + 5, + 0, + 107, + 0, + 0, // Skip to: 8056 + /* 7949 */ MCD_OPC_Decode, + 153, + 5, + 84, // Opcode: STDCQri + /* 7953 */ MCD_OPC_FilterValue, + 55, + 37, + 0, + 0, // Skip to: 7995 + /* 7958 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 7961 */ MCD_OPC_FilterValue, + 0, + 20, + 0, + 0, // Skip to: 7986 + /* 7966 */ MCD_OPC_CheckField, + 5, + 8, + 0, + 4, + 0, + 0, // Skip to: 7977 + /* 7973 */ MCD_OPC_Decode, + 156, + 5, + 85, // Opcode: STDCrr + /* 7977 */ MCD_OPC_CheckPredicate, + 0, + 74, + 0, + 0, // Skip to: 8056 + /* 7982 */ MCD_OPC_Decode, + 157, + 5, + 80, // Opcode: STDFArr + /* 7986 */ MCD_OPC_FilterValue, + 1, + 65, + 0, + 0, // Skip to: 8056 + /* 7991 */ MCD_OPC_Decode, + 155, + 5, + 85, // Opcode: STDCri + /* 7995 */ MCD_OPC_FilterValue, + 60, + 39, + 0, + 0, // Skip to: 8039 + /* 8000 */ MCD_OPC_ExtractField, + 13, + 1, // Inst{13} ... + /* 8003 */ MCD_OPC_FilterValue, + 0, + 48, + 0, + 0, // Skip to: 8056 + /* 8008 */ MCD_OPC_ExtractField, + 5, + 8, // Inst{12-5} ... + /* 8011 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 8020 + /* 8016 */ MCD_OPC_Decode, + 200, + 2, + 86, // Opcode: CASAasi10 + /* 8020 */ MCD_OPC_FilterValue, + 128, + 1, + 9, + 0, + 0, // Skip to: 8035 + /* 8026 */ MCD_OPC_CheckPredicate, + 0, + 4, + 0, + 0, // Skip to: 8035 + /* 8031 */ MCD_OPC_Decode, + 203, + 2, + 86, // Opcode: CASrr + /* 8035 */ MCD_OPC_Decode, + 201, + 2, + 87, // Opcode: CASArr + /* 8039 */ MCD_OPC_FilterValue, + 62, + 12, + 0, + 0, // Skip to: 8056 + /* 8044 */ MCD_OPC_CheckField, + 5, + 9, + 128, + 1, + 4, + 0, + 0, // Skip to: 8056 + /* 8052 */ MCD_OPC_Decode, + 202, + 2, + 88, // Opcode: CASXrr + /* 8056 */ MCD_OPC_Fail, + 0}; + +static const uint8_t DecoderTableSparcV832[] = { + /* 0 */ MCD_OPC_ExtractField, 8, 6, // Inst{13-8} ... + /* 3 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 33 + /* 8 */ MCD_OPC_CheckField, 29, 3, 4, 41, 0, 0, // Skip to: 56 + /* 15 */ MCD_OPC_CheckField, 19, 6, 58, 34, 0, 0, // Skip to: 56 + /* 22 */ MCD_OPC_CheckField, 5, 3, 0, 27, 0, 0, // Skip to: 56 + /* 29 */ MCD_OPC_Decode, 209, 5, 89, // Opcode: TRAPrr + /* 33 */ MCD_OPC_FilterValue, 32, 18, 0, 0, // Skip to: 56 + /* 38 */ MCD_OPC_CheckField, 29, 3, 4, 11, 0, 0, // Skip to: 56 + /* 45 */ MCD_OPC_CheckField, 19, 6, 58, 4, 0, 0, // Skip to: 56 + /* 52 */ MCD_OPC_Decode, 208, 5, 89, // Opcode: TRAPri + /* 56 */ MCD_OPC_Fail, 0}; -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ +static const uint8_t DecoderTableSparcV932[] = { + /* 0 */ MCD_OPC_ExtractField, + 8, + 6, // Inst{13-8} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 30, + 0, + 0, // Skip to: 38 + /* 8 */ MCD_OPC_CheckPredicate, + 0, + 53, + 0, + 0, // Skip to: 66 + /* 13 */ MCD_OPC_CheckField, + 29, + 3, + 4, + 46, + 0, + 0, // Skip to: 66 + /* 20 */ MCD_OPC_CheckField, + 19, + 6, + 58, + 39, + 0, + 0, // Skip to: 66 + /* 27 */ MCD_OPC_CheckField, + 5, + 3, + 0, + 32, + 0, + 0, // Skip to: 66 + /* 34 */ MCD_OPC_Decode, + 202, + 5, + 89, // Opcode: TICCrr + /* 38 */ MCD_OPC_FilterValue, + 32, + 23, + 0, + 0, // Skip to: 66 + /* 43 */ MCD_OPC_CheckPredicate, + 0, + 18, + 0, + 0, // Skip to: 66 + /* 48 */ MCD_OPC_CheckField, + 29, + 3, + 4, + 11, + 0, + 0, // Skip to: 66 + /* 55 */ MCD_OPC_CheckField, + 19, + 6, + 58, + 4, + 0, + 0, // Skip to: 66 + /* 62 */ MCD_OPC_Decode, + 201, + 5, + 89, // Opcode: TICCri + /* 66 */ MCD_OPC_Fail, + 0}; + +static bool getbool(uint64_t b) { return b != 0; } +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { - default: // llvm_unreachable("Invalid index!"); + default: + llvm_unreachable("Invalid index!"); + case 0: + return getbool(checkFeatureRequired(Bits, Sparc_FeatureV9, 1)); + case 1: + return getbool(checkFeatureRequired(Bits, Sparc_FeaturePWRPSR, 1)); + case 2: + return getbool(checkFeatureRequired(Bits, Sparc_FeatureVIS3, 1)); + case 3: + return getbool(checkFeatureRequired(Bits, Sparc_FeatureVIS, 1)); + case 4: + return getbool(checkFeatureRequired(Bits, Sparc_FeatureVIS2, 1)); + } +} + +#define DecodeToMCInst(fname, fieldname, InsnType) \ + static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, \ + MCInst *MI, uint64_t Address, bool *Decoder) { \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + llvm_unreachable("Invalid index!"); \ + case 0: \ + tmp = fieldname(insn, 0, 22); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 1: \ + tmp = fieldname(insn, 0, 19); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 2: \ + tmp = fieldname(insn, 0, 22); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 3: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 14) << 0; \ + tmp |= fieldname(insn, 20, 2) << 14; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 4: \ + return S; \ + case 5: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 22); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 6: \ + tmp = fieldname(insn, 0, 19); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 7: \ + tmp = fieldname(insn, 0, 30); \ + if (DecodeCall(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 8: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 9: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 10: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 11: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 13); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 12: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 13: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 14: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 15: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 16: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 17: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 0, 13); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 20: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodePRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 21: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 22: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 23: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 11); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 24: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 11); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 25: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 26: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 27: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodePRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 31: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodePRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 13); \ + if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 34: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 35: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 37: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 41: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 42: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 45: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 46: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 47: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 48: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 49: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 50: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 51: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 11, 2); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 52: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 53: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 55: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 57: \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 58: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 59: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 60: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 61: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 62: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 64: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 65: \ + if (DecodeJMPL(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 66: \ + if (DecodeReturn(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 68: \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 25, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 69: \ + if (DecodeLoadInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 70: \ + if (DecodeLoadIntPair(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 71: \ + if (DecodeStoreInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 72: \ + if (DecodeStoreIntPair(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 73: \ + if (DecodeSWAP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 74: \ + tmp = fieldname(insn, 5, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 75: \ + if (DecodeLoadFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 76: \ + if (DecodeLoadQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 77: \ + if (DecodeLoadDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 78: \ + if (DecodeStoreFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 79: \ + if (DecodeStoreQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 80: \ + if (DecodeStoreDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 25, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 82: \ + if (DecodeLoadCP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 83: \ + if (DecodeLoadCPPair(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 84: \ + if (DecodeStoreCP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 85: \ + if (DecodeStoreCPPair(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 86: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 87: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 5, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 88: \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 14, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 25, 5); \ + if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 89: \ + if (DecodeTRAP(MI, insn, Address, Decoder) == MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + } \ + } + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ + static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + MCRegisterInfo *MRI, int feature) { \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, feature))) \ + Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could \ + * be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ + } + +FieldFromInstruction(fieldFromInstruction, uint32_t) + DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) + DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) + +#endif // MIPS_GET_DISASSEMBLER +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +#define SP_CANRESTORE 1 +#define SP_CANSAVE 2 +#define SP_CLEANWIN 3 +#define SP_CPQ 4 +#define SP_CPSR 5 +#define SP_CWP 6 +#define SP_FQ 7 +#define SP_FSR 8 +#define SP_ICC 9 +#define SP_OTHERWIN 10 +#define SP_PC 11 +#define SP_PIL 12 +#define SP_PSR 13 +#define SP_PSTATE 14 +#define SP_TBA 15 +#define SP_TBR 16 +#define SP_TICK 17 +#define SP_TL 18 +#define SP_TNPC 19 +#define SP_TPC 20 +#define SP_TSTATE 21 +#define SP_TT 22 +#define SP_WIM 23 +#define SP_WSTATE 24 +#define SP_Y 25 +#define SP_ASR1 26 +#define SP_ASR2 27 +#define SP_ASR3 28 +#define SP_ASR4 29 +#define SP_ASR5 30 +#define SP_ASR6 31 +#define SP_ASR7 32 +#define SP_ASR8 33 +#define SP_ASR9 34 +#define SP_ASR10 35 +#define SP_ASR11 36 +#define SP_ASR12 37 +#define SP_ASR13 38 +#define SP_ASR14 39 +#define SP_ASR15 40 +#define SP_ASR16 41 +#define SP_ASR17 42 +#define SP_ASR18 43 +#define SP_ASR19 44 +#define SP_ASR20 45 +#define SP_ASR21 46 +#define SP_ASR22 47 +#define SP_ASR23 48 +#define SP_ASR24 49 +#define SP_ASR25 50 +#define SP_ASR26 51 +#define SP_ASR27 52 +#define SP_ASR28 53 +#define SP_ASR29 54 +#define SP_ASR30 55 +#define SP_ASR31 56 +#define SP_C0 57 +#define SP_C1 58 +#define SP_C2 59 +#define SP_C3 60 +#define SP_C4 61 +#define SP_C5 62 +#define SP_C6 63 +#define SP_C7 64 +#define SP_C8 65 +#define SP_C9 66 +#define SP_C10 67 +#define SP_C11 68 +#define SP_C12 69 +#define SP_C13 70 +#define SP_C14 71 +#define SP_C15 72 +#define SP_C16 73 +#define SP_C17 74 +#define SP_C18 75 +#define SP_C19 76 +#define SP_C20 77 +#define SP_C21 78 +#define SP_C22 79 +#define SP_C23 80 +#define SP_C24 81 +#define SP_C25 82 +#define SP_C26 83 +#define SP_C27 84 +#define SP_C28 85 +#define SP_C29 86 +#define SP_C30 87 +#define SP_C31 88 +#define SP_D0 89 +#define SP_D1 90 +#define SP_D2 91 +#define SP_D3 92 +#define SP_D4 93 +#define SP_D5 94 +#define SP_D6 95 +#define SP_D7 96 +#define SP_D8 97 +#define SP_D9 98 +#define SP_D10 99 +#define SP_D11 100 +#define SP_D12 101 +#define SP_D13 102 +#define SP_D14 103 +#define SP_D15 104 +#define SP_D16 105 +#define SP_D17 106 +#define SP_D18 107 +#define SP_D19 108 +#define SP_D20 109 +#define SP_D21 110 +#define SP_D22 111 +#define SP_D23 112 +#define SP_D24 113 +#define SP_D25 114 +#define SP_D26 115 +#define SP_D27 116 +#define SP_D28 117 +#define SP_D29 118 +#define SP_D30 119 +#define SP_D31 120 +#define SP_F0 121 +#define SP_F1 122 +#define SP_F2 123 +#define SP_F3 124 +#define SP_F4 125 +#define SP_F5 126 +#define SP_F6 127 +#define SP_F7 128 +#define SP_F8 129 +#define SP_F9 130 +#define SP_F10 131 +#define SP_F11 132 +#define SP_F12 133 +#define SP_F13 134 +#define SP_F14 135 +#define SP_F15 136 +#define SP_F16 137 +#define SP_F17 138 +#define SP_F18 139 +#define SP_F19 140 +#define SP_F20 141 +#define SP_F21 142 +#define SP_F22 143 +#define SP_F23 144 +#define SP_F24 145 +#define SP_F25 146 +#define SP_F26 147 +#define SP_F27 148 +#define SP_F28 149 +#define SP_F29 150 +#define SP_F30 151 +#define SP_F31 152 +#define SP_FCC0 153 +#define SP_FCC1 154 +#define SP_FCC2 155 +#define SP_FCC3 156 +#define SP_G0 157 +#define SP_G1 158 +#define SP_G2 159 +#define SP_G3 160 +#define SP_G4 161 +#define SP_G5 162 +#define SP_G6 163 +#define SP_G7 164 +#define SP_I0 165 +#define SP_I1 166 +#define SP_I2 167 +#define SP_I3 168 +#define SP_I4 169 +#define SP_I5 170 +#define SP_I6 171 +#define SP_I7 172 +#define SP_L0 173 +#define SP_L1 174 +#define SP_L2 175 +#define SP_L3 176 +#define SP_L4 177 +#define SP_L5 178 +#define SP_L6 179 +#define SP_L7 180 +#define SP_O0 181 +#define SP_O1 182 +#define SP_O2 183 +#define SP_O3 184 +#define SP_O4 185 +#define SP_O5 186 +#define SP_O6 187 +#define SP_O7 188 +#define SP_Q0 189 +#define SP_Q1 190 +#define SP_Q2 191 +#define SP_Q3 192 +#define SP_Q4 193 +#define SP_Q5 194 +#define SP_Q6 195 +#define SP_Q7 196 +#define SP_Q8 197 +#define SP_Q9 198 +#define SP_Q10 199 +#define SP_Q11 200 +#define SP_Q12 201 +#define SP_Q13 202 +#define SP_Q14 203 +#define SP_Q15 204 +#define SP_C0_C1 205 +#define SP_C2_C3 206 +#define SP_C4_C5 207 +#define SP_C6_C7 208 +#define SP_C8_C9 209 +#define SP_C10_C11 210 +#define SP_C12_C13 211 +#define SP_C14_C15 212 +#define SP_C16_C17 213 +#define SP_C18_C19 214 +#define SP_C20_C21 215 +#define SP_C22_C23 216 +#define SP_C24_C25 217 +#define SP_C26_C27 218 +#define SP_C28_C29 219 +#define SP_C30_C31 220 +#define SP_G0_G1 221 +#define SP_G2_G3 222 +#define SP_G4_G5 223 +#define SP_G6_G7 224 +#define SP_I0_I1 225 +#define SP_I2_I3 226 +#define SP_I4_I5 227 +#define SP_I6_I7 228 +#define SP_L0_L1 229 +#define SP_L2_L3 230 +#define SP_L4_L5 231 +#define SP_L6_L7 232 +#define SP_O0_O1 233 +#define SP_O2_O3 234 +#define SP_O4_O5 235 +#define SP_O6_O7 236 +#define SP_NUM_TARGET_REGS 237 + +// Register classes + +#define SP_FCCRegsRegClassID 0 +#define SP_ASRRegsRegClassID 1 +#define SP_CoprocRegsRegClassID 2 +#define SP_FPRegsRegClassID 3 +#define SP_IntRegsRegClassID 4 +#define SP_DFPRegsRegClassID 5 +#define SP_I64RegsRegClassID 6 +#define SP_CoprocPairRegClassID 7 +#define SP_IntPairRegClassID 8 +#define SP_LowDFPRegsRegClassID 9 +#define SP_PRRegsRegClassID 10 +#define SP_QFPRegsRegClassID 11 +#define SP_LowQFPRegsRegClassID 12 + +#endif // GET_REGINFO_ENUM + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +#define SP_PHI 0 +#define SP_INLINEASM 1 +#define SP_INLINEASM_BR 2 +#define SP_CFI_INSTRUCTION 3 +#define SP_EH_LABEL 4 +#define SP_GC_LABEL 5 +#define SP_ANNOTATION_LABEL 6 +#define SP_KILL 7 +#define SP_EXTRACT_SUBREG 8 +#define SP_INSERT_SUBREG 9 +#define SP_IMPLICIT_DEF 10 +#define SP_SUBREG_TO_REG 11 +#define SP_COPY_TO_REGCLASS 12 +#define SP_DBG_VALUE 13 +#define SP_DBG_VALUE_LIST 14 +#define SP_DBG_INSTR_REF 15 +#define SP_DBG_PHI 16 +#define SP_DBG_LABEL 17 +#define SP_REG_SEQUENCE 18 +#define SP_COPY 19 +#define SP_BUNDLE 20 +#define SP_LIFETIME_START 21 +#define SP_LIFETIME_END 22 +#define SP_PSEUDO_PROBE 23 +#define SP_ARITH_FENCE 24 +#define SP_STACKMAP 25 +#define SP_FENTRY_CALL 26 +#define SP_PATCHPOINT 27 +#define SP_LOAD_STACK_GUARD 28 +#define SP_PREALLOCATED_SETUP 29 +#define SP_PREALLOCATED_ARG 30 +#define SP_STATEPOINT 31 +#define SP_LOCAL_ESCAPE 32 +#define SP_FAULTING_OP 33 +#define SP_PATCHABLE_OP 34 +#define SP_PATCHABLE_FUNCTION_ENTER 35 +#define SP_PATCHABLE_RET 36 +#define SP_PATCHABLE_FUNCTION_EXIT 37 +#define SP_PATCHABLE_TAIL_CALL 38 +#define SP_PATCHABLE_EVENT_CALL 39 +#define SP_PATCHABLE_TYPED_EVENT_CALL 40 +#define SP_ICALL_BRANCH_FUNNEL 41 +#define SP_G_ASSERT_SEXT 42 +#define SP_G_ASSERT_ZEXT 43 +#define SP_G_ADD 44 +#define SP_G_SUB 45 +#define SP_G_MUL 46 +#define SP_G_SDIV 47 +#define SP_G_UDIV 48 +#define SP_G_SREM 49 +#define SP_G_UREM 50 +#define SP_G_SDIVREM 51 +#define SP_G_UDIVREM 52 +#define SP_G_AND 53 +#define SP_G_OR 54 +#define SP_G_XOR 55 +#define SP_G_IMPLICIT_DEF 56 +#define SP_G_PHI 57 +#define SP_G_FRAME_INDEX 58 +#define SP_G_GLOBAL_VALUE 59 +#define SP_G_EXTRACT 60 +#define SP_G_UNMERGE_VALUES 61 +#define SP_G_INSERT 62 +#define SP_G_MERGE_VALUES 63 +#define SP_G_BUILD_VECTOR 64 +#define SP_G_BUILD_VECTOR_TRUNC 65 +#define SP_G_CONCAT_VECTORS 66 +#define SP_G_PTRTOINT 67 +#define SP_G_INTTOPTR 68 +#define SP_G_BITCAST 69 +#define SP_G_FREEZE 70 +#define SP_G_INTRINSIC_TRUNC 71 +#define SP_G_INTRINSIC_ROUND 72 +#define SP_G_INTRINSIC_LRINT 73 +#define SP_G_INTRINSIC_ROUNDEVEN 74 +#define SP_G_READCYCLECOUNTER 75 +#define SP_G_LOAD 76 +#define SP_G_SEXTLOAD 77 +#define SP_G_ZEXTLOAD 78 +#define SP_G_INDEXED_LOAD 79 +#define SP_G_INDEXED_SEXTLOAD 80 +#define SP_G_INDEXED_ZEXTLOAD 81 +#define SP_G_STORE 82 +#define SP_G_INDEXED_STORE 83 +#define SP_G_ATOMIC_CMPXCHG_WITH_SUCCESS 84 +#define SP_G_ATOMIC_CMPXCHG 85 +#define SP_G_ATOMICRMW_XCHG 86 +#define SP_G_ATOMICRMW_ADD 87 +#define SP_G_ATOMICRMW_SUB 88 +#define SP_G_ATOMICRMW_AND 89 +#define SP_G_ATOMICRMW_NAND 90 +#define SP_G_ATOMICRMW_OR 91 +#define SP_G_ATOMICRMW_XOR 92 +#define SP_G_ATOMICRMW_MAX 93 +#define SP_G_ATOMICRMW_MIN 94 +#define SP_G_ATOMICRMW_UMAX 95 +#define SP_G_ATOMICRMW_UMIN 96 +#define SP_G_ATOMICRMW_FADD 97 +#define SP_G_ATOMICRMW_FSUB 98 +#define SP_G_FENCE 99 +#define SP_G_BRCOND 100 +#define SP_G_BRINDIRECT 101 +#define SP_G_INTRINSIC 102 +#define SP_G_INTRINSIC_W_SIDE_EFFECTS 103 +#define SP_G_ANYEXT 104 +#define SP_G_TRUNC 105 +#define SP_G_CONSTANT 106 +#define SP_G_FCONSTANT 107 +#define SP_G_VASTART 108 +#define SP_G_VAARG 109 +#define SP_G_SEXT 110 +#define SP_G_SEXT_INREG 111 +#define SP_G_ZEXT 112 +#define SP_G_SHL 113 +#define SP_G_LSHR 114 +#define SP_G_ASHR 115 +#define SP_G_FSHL 116 +#define SP_G_FSHR 117 +#define SP_G_ROTR 118 +#define SP_G_ROTL 119 +#define SP_G_ICMP 120 +#define SP_G_FCMP 121 +#define SP_G_SELECT 122 +#define SP_G_UADDO 123 +#define SP_G_UADDE 124 +#define SP_G_USUBO 125 +#define SP_G_USUBE 126 +#define SP_G_SADDO 127 +#define SP_G_SADDE 128 +#define SP_G_SSUBO 129 +#define SP_G_SSUBE 130 +#define SP_G_UMULO 131 +#define SP_G_SMULO 132 +#define SP_G_UMULH 133 +#define SP_G_SMULH 134 +#define SP_G_UADDSAT 135 +#define SP_G_SADDSAT 136 +#define SP_G_USUBSAT 137 +#define SP_G_SSUBSAT 138 +#define SP_G_USHLSAT 139 +#define SP_G_SSHLSAT 140 +#define SP_G_SMULFIX 141 +#define SP_G_UMULFIX 142 +#define SP_G_SMULFIXSAT 143 +#define SP_G_UMULFIXSAT 144 +#define SP_G_SDIVFIX 145 +#define SP_G_UDIVFIX 146 +#define SP_G_SDIVFIXSAT 147 +#define SP_G_UDIVFIXSAT 148 +#define SP_G_FADD 149 +#define SP_G_FSUB 150 +#define SP_G_FMUL 151 +#define SP_G_FMA 152 +#define SP_G_FMAD 153 +#define SP_G_FDIV 154 +#define SP_G_FREM 155 +#define SP_G_FPOW 156 +#define SP_G_FPOWI 157 +#define SP_G_FEXP 158 +#define SP_G_FEXP2 159 +#define SP_G_FLOG 160 +#define SP_G_FLOG2 161 +#define SP_G_FLOG10 162 +#define SP_G_FNEG 163 +#define SP_G_FPEXT 164 +#define SP_G_FPTRUNC 165 +#define SP_G_FPTOSI 166 +#define SP_G_FPTOUI 167 +#define SP_G_SITOFP 168 +#define SP_G_UITOFP 169 +#define SP_G_FABS 170 +#define SP_G_FCOPYSIGN 171 +#define SP_G_FCANONICALIZE 172 +#define SP_G_FMINNUM 173 +#define SP_G_FMAXNUM 174 +#define SP_G_FMINNUM_IEEE 175 +#define SP_G_FMAXNUM_IEEE 176 +#define SP_G_FMINIMUM 177 +#define SP_G_FMAXIMUM 178 +#define SP_G_PTR_ADD 179 +#define SP_G_PTRMASK 180 +#define SP_G_SMIN 181 +#define SP_G_SMAX 182 +#define SP_G_UMIN 183 +#define SP_G_UMAX 184 +#define SP_G_ABS 185 +#define SP_G_LROUND 186 +#define SP_G_LLROUND 187 +#define SP_G_BR 188 +#define SP_G_BRJT 189 +#define SP_G_INSERT_VECTOR_ELT 190 +#define SP_G_EXTRACT_VECTOR_ELT 191 +#define SP_G_SHUFFLE_VECTOR 192 +#define SP_G_CTTZ 193 +#define SP_G_CTTZ_ZERO_UNDEF 194 +#define SP_G_CTLZ 195 +#define SP_G_CTLZ_ZERO_UNDEF 196 +#define SP_G_CTPOP 197 +#define SP_G_BSWAP 198 +#define SP_G_BITREVERSE 199 +#define SP_G_FCEIL 200 +#define SP_G_FCOS 201 +#define SP_G_FSIN 202 +#define SP_G_FSQRT 203 +#define SP_G_FFLOOR 204 +#define SP_G_FRINT 205 +#define SP_G_FNEARBYINT 206 +#define SP_G_ADDRSPACE_CAST 207 +#define SP_G_BLOCK_ADDR 208 +#define SP_G_JUMP_TABLE 209 +#define SP_G_DYN_STACKALLOC 210 +#define SP_G_STRICT_FADD 211 +#define SP_G_STRICT_FSUB 212 +#define SP_G_STRICT_FMUL 213 +#define SP_G_STRICT_FDIV 214 +#define SP_G_STRICT_FREM 215 +#define SP_G_STRICT_FMA 216 +#define SP_G_STRICT_FSQRT 217 +#define SP_G_READ_REGISTER 218 +#define SP_G_WRITE_REGISTER 219 +#define SP_G_MEMCPY 220 +#define SP_G_MEMCPY_INLINE 221 +#define SP_G_MEMMOVE 222 +#define SP_G_MEMSET 223 +#define SP_G_BZERO 224 +#define SP_G_VECREDUCE_SEQ_FADD 225 +#define SP_G_VECREDUCE_SEQ_FMUL 226 +#define SP_G_VECREDUCE_FADD 227 +#define SP_G_VECREDUCE_FMUL 228 +#define SP_G_VECREDUCE_FMAX 229 +#define SP_G_VECREDUCE_FMIN 230 +#define SP_G_VECREDUCE_ADD 231 +#define SP_G_VECREDUCE_MUL 232 +#define SP_G_VECREDUCE_AND 233 +#define SP_G_VECREDUCE_OR 234 +#define SP_G_VECREDUCE_XOR 235 +#define SP_G_VECREDUCE_SMAX 236 +#define SP_G_VECREDUCE_SMIN 237 +#define SP_G_VECREDUCE_UMAX 238 +#define SP_G_VECREDUCE_UMIN 239 +#define SP_G_SBFX 240 +#define SP_G_UBFX 241 +#define SP_ADJCALLSTACKDOWN 242 +#define SP_ADJCALLSTACKUP 243 +#define SP_GETPCX 244 +#define SP_SELECT_CC_DFP_FCC 245 +#define SP_SELECT_CC_DFP_ICC 246 +#define SP_SELECT_CC_FP_FCC 247 +#define SP_SELECT_CC_FP_ICC 248 +#define SP_SELECT_CC_Int_FCC 249 +#define SP_SELECT_CC_Int_ICC 250 +#define SP_SELECT_CC_QFP_FCC 251 +#define SP_SELECT_CC_QFP_ICC 252 +#define SP_SET 253 +#define SP_ADDCCri 254 +#define SP_ADDCCrr 255 +#define SP_ADDCri 256 +#define SP_ADDCrr 257 +#define SP_ADDEri 258 +#define SP_ADDErr 259 +#define SP_ADDXC 260 +#define SP_ADDXCCC 261 +#define SP_ADDXri 262 +#define SP_ADDXrr 263 +#define SP_ADDri 264 +#define SP_ADDrr 265 +#define SP_ALIGNADDR 266 +#define SP_ALIGNADDRL 267 +#define SP_ANDCCri 268 +#define SP_ANDCCrr 269 +#define SP_ANDNCCri 270 +#define SP_ANDNCCrr 271 +#define SP_ANDNri 272 +#define SP_ANDNrr 273 +#define SP_ANDXNrr 274 +#define SP_ANDXri 275 +#define SP_ANDXrr 276 +#define SP_ANDri 277 +#define SP_ANDrr 278 +#define SP_ARRAY16 279 +#define SP_ARRAY32 280 +#define SP_ARRAY8 281 +#define SP_BA 282 +#define SP_BCOND 283 +#define SP_BCONDA 284 +#define SP_BINDri 285 +#define SP_BINDrr 286 +#define SP_BMASK 287 +#define SP_BPFCC 288 +#define SP_BPFCCA 289 +#define SP_BPFCCANT 290 +#define SP_BPFCCNT 291 +#define SP_BPGEZapn 292 +#define SP_BPGEZapt 293 +#define SP_BPGEZnapn 294 +#define SP_BPGEZnapt 295 +#define SP_BPGZapn 296 +#define SP_BPGZapt 297 +#define SP_BPGZnapn 298 +#define SP_BPGZnapt 299 +#define SP_BPICC 300 +#define SP_BPICCA 301 +#define SP_BPICCANT 302 +#define SP_BPICCNT 303 +#define SP_BPLEZapn 304 +#define SP_BPLEZapt 305 +#define SP_BPLEZnapn 306 +#define SP_BPLEZnapt 307 +#define SP_BPLZapn 308 +#define SP_BPLZapt 309 +#define SP_BPLZnapn 310 +#define SP_BPLZnapt 311 +#define SP_BPNZapn 312 +#define SP_BPNZapt 313 +#define SP_BPNZnapn 314 +#define SP_BPNZnapt 315 +#define SP_BPXCC 316 +#define SP_BPXCCA 317 +#define SP_BPXCCANT 318 +#define SP_BPXCCNT 319 +#define SP_BPZapn 320 +#define SP_BPZapt 321 +#define SP_BPZnapn 322 +#define SP_BPZnapt 323 +#define SP_BSHUFFLE 324 +#define SP_CALL 325 +#define SP_CALLri 326 +#define SP_CALLrr 327 +#define SP_CASAasi10 328 +#define SP_CASArr 329 +#define SP_CASXrr 330 +#define SP_CASrr 331 +#define SP_CBCOND 332 +#define SP_CBCONDA 333 +#define SP_CMASK16 334 +#define SP_CMASK32 335 +#define SP_CMASK8 336 +#define SP_CMPri 337 +#define SP_CMPrr 338 +#define SP_EDGE16 339 +#define SP_EDGE16L 340 +#define SP_EDGE16LN 341 +#define SP_EDGE16N 342 +#define SP_EDGE32 343 +#define SP_EDGE32L 344 +#define SP_EDGE32LN 345 +#define SP_EDGE32N 346 +#define SP_EDGE8 347 +#define SP_EDGE8L 348 +#define SP_EDGE8LN 349 +#define SP_EDGE8N 350 +#define SP_FABSD 351 +#define SP_FABSQ 352 +#define SP_FABSS 353 +#define SP_FADDD 354 +#define SP_FADDQ 355 +#define SP_FADDS 356 +#define SP_FALIGNADATA 357 +#define SP_FAND 358 +#define SP_FANDNOT1 359 +#define SP_FANDNOT1S 360 +#define SP_FANDNOT2 361 +#define SP_FANDNOT2S 362 +#define SP_FANDS 363 +#define SP_FBCOND 364 +#define SP_FBCONDA 365 +#define SP_FCHKSM16 366 +#define SP_FCMPD 367 +#define SP_FCMPEQ16 368 +#define SP_FCMPEQ32 369 +#define SP_FCMPGT16 370 +#define SP_FCMPGT32 371 +#define SP_FCMPLE16 372 +#define SP_FCMPLE32 373 +#define SP_FCMPNE16 374 +#define SP_FCMPNE32 375 +#define SP_FCMPQ 376 +#define SP_FCMPS 377 +#define SP_FDIVD 378 +#define SP_FDIVQ 379 +#define SP_FDIVS 380 +#define SP_FDMULQ 381 +#define SP_FDTOI 382 +#define SP_FDTOQ 383 +#define SP_FDTOS 384 +#define SP_FDTOX 385 +#define SP_FEXPAND 386 +#define SP_FHADDD 387 +#define SP_FHADDS 388 +#define SP_FHSUBD 389 +#define SP_FHSUBS 390 +#define SP_FITOD 391 +#define SP_FITOQ 392 +#define SP_FITOS 393 +#define SP_FLCMPD 394 +#define SP_FLCMPS 395 +#define SP_FLUSH 396 +#define SP_FLUSHW 397 +#define SP_FLUSHri 398 +#define SP_FLUSHrr 399 +#define SP_FMEAN16 400 +#define SP_FMOVD 401 +#define SP_FMOVD_FCC 402 +#define SP_FMOVD_ICC 403 +#define SP_FMOVD_XCC 404 +#define SP_FMOVQ 405 +#define SP_FMOVQ_FCC 406 +#define SP_FMOVQ_ICC 407 +#define SP_FMOVQ_XCC 408 +#define SP_FMOVRGEZD 409 +#define SP_FMOVRGEZQ 410 +#define SP_FMOVRGEZS 411 +#define SP_FMOVRGZD 412 +#define SP_FMOVRGZQ 413 +#define SP_FMOVRGZS 414 +#define SP_FMOVRLEZD 415 +#define SP_FMOVRLEZQ 416 +#define SP_FMOVRLEZS 417 +#define SP_FMOVRLZD 418 +#define SP_FMOVRLZQ 419 +#define SP_FMOVRLZS 420 +#define SP_FMOVRNZD 421 +#define SP_FMOVRNZQ 422 +#define SP_FMOVRNZS 423 +#define SP_FMOVRZD 424 +#define SP_FMOVRZQ 425 +#define SP_FMOVRZS 426 +#define SP_FMOVS 427 +#define SP_FMOVS_FCC 428 +#define SP_FMOVS_ICC 429 +#define SP_FMOVS_XCC 430 +#define SP_FMUL8SUX16 431 +#define SP_FMUL8ULX16 432 +#define SP_FMUL8X16 433 +#define SP_FMUL8X16AL 434 +#define SP_FMUL8X16AU 435 +#define SP_FMULD 436 +#define SP_FMULD8SUX16 437 +#define SP_FMULD8ULX16 438 +#define SP_FMULQ 439 +#define SP_FMULS 440 +#define SP_FNADDD 441 +#define SP_FNADDS 442 +#define SP_FNAND 443 +#define SP_FNANDS 444 +#define SP_FNEGD 445 +#define SP_FNEGQ 446 +#define SP_FNEGS 447 +#define SP_FNHADDD 448 +#define SP_FNHADDS 449 +#define SP_FNMULD 450 +#define SP_FNMULS 451 +#define SP_FNOR 452 +#define SP_FNORS 453 +#define SP_FNOT1 454 +#define SP_FNOT1S 455 +#define SP_FNOT2 456 +#define SP_FNOT2S 457 +#define SP_FNSMULD 458 +#define SP_FONE 459 +#define SP_FONES 460 +#define SP_FOR 461 +#define SP_FORNOT1 462 +#define SP_FORNOT1S 463 +#define SP_FORNOT2 464 +#define SP_FORNOT2S 465 +#define SP_FORS 466 +#define SP_FPACK16 467 +#define SP_FPACK32 468 +#define SP_FPACKFIX 469 +#define SP_FPADD16 470 +#define SP_FPADD16S 471 +#define SP_FPADD32 472 +#define SP_FPADD32S 473 +#define SP_FPADD64 474 +#define SP_FPMERGE 475 +#define SP_FPSUB16 476 +#define SP_FPSUB16S 477 +#define SP_FPSUB32 478 +#define SP_FPSUB32S 479 +#define SP_FQTOD 480 +#define SP_FQTOI 481 +#define SP_FQTOS 482 +#define SP_FQTOX 483 +#define SP_FSLAS16 484 +#define SP_FSLAS32 485 +#define SP_FSLL16 486 +#define SP_FSLL32 487 +#define SP_FSMULD 488 +#define SP_FSQRTD 489 +#define SP_FSQRTQ 490 +#define SP_FSQRTS 491 +#define SP_FSRA16 492 +#define SP_FSRA32 493 +#define SP_FSRC1 494 +#define SP_FSRC1S 495 +#define SP_FSRC2 496 +#define SP_FSRC2S 497 +#define SP_FSRL16 498 +#define SP_FSRL32 499 +#define SP_FSTOD 500 +#define SP_FSTOI 501 +#define SP_FSTOQ 502 +#define SP_FSTOX 503 +#define SP_FSUBD 504 +#define SP_FSUBQ 505 +#define SP_FSUBS 506 +#define SP_FXNOR 507 +#define SP_FXNORS 508 +#define SP_FXOR 509 +#define SP_FXORS 510 +#define SP_FXTOD 511 +#define SP_FXTOQ 512 +#define SP_FXTOS 513 +#define SP_FZERO 514 +#define SP_FZEROS 515 +#define SP_JMPLri 516 +#define SP_JMPLrr 517 +#define SP_LDArr 518 +#define SP_LDCSRri 519 +#define SP_LDCSRrr 520 +#define SP_LDCri 521 +#define SP_LDCrr 522 +#define SP_LDDArr 523 +#define SP_LDDCri 524 +#define SP_LDDCrr 525 +#define SP_LDDFArr 526 +#define SP_LDDFri 527 +#define SP_LDDFrr 528 +#define SP_LDDri 529 +#define SP_LDDrr 530 +#define SP_LDFArr 531 +#define SP_LDFSRri 532 +#define SP_LDFSRrr 533 +#define SP_LDFri 534 +#define SP_LDFrr 535 +#define SP_LDQFArr 536 +#define SP_LDQFri 537 +#define SP_LDQFrr 538 +#define SP_LDSBArr 539 +#define SP_LDSBri 540 +#define SP_LDSBrr 541 +#define SP_LDSHArr 542 +#define SP_LDSHri 543 +#define SP_LDSHrr 544 +#define SP_LDSTUBArr 545 +#define SP_LDSTUBri 546 +#define SP_LDSTUBrr 547 +#define SP_LDSWri 548 +#define SP_LDSWrr 549 +#define SP_LDUBArr 550 +#define SP_LDUBri 551 +#define SP_LDUBrr 552 +#define SP_LDUHArr 553 +#define SP_LDUHri 554 +#define SP_LDUHrr 555 +#define SP_LDXFSRri 556 +#define SP_LDXFSRrr 557 +#define SP_LDXri 558 +#define SP_LDXrr 559 +#define SP_LDri 560 +#define SP_LDrr 561 +#define SP_LEAX_ADDri 562 +#define SP_LEA_ADDri 563 +#define SP_LZCNT 564 +#define SP_MEMBARi 565 +#define SP_MOVDTOX 566 +#define SP_MOVFCCri 567 +#define SP_MOVFCCrr 568 +#define SP_MOVICCri 569 +#define SP_MOVICCrr 570 +#define SP_MOVRGEZri 571 +#define SP_MOVRGEZrr 572 +#define SP_MOVRGZri 573 +#define SP_MOVRGZrr 574 +#define SP_MOVRLEZri 575 +#define SP_MOVRLEZrr 576 +#define SP_MOVRLZri 577 +#define SP_MOVRLZrr 578 +#define SP_MOVRNZri 579 +#define SP_MOVRNZrr 580 +#define SP_MOVRRZri 581 +#define SP_MOVRRZrr 582 +#define SP_MOVSTOSW 583 +#define SP_MOVSTOUW 584 +#define SP_MOVWTOS 585 +#define SP_MOVXCCri 586 +#define SP_MOVXCCrr 587 +#define SP_MOVXTOD 588 +#define SP_MULSCCri 589 +#define SP_MULSCCrr 590 +#define SP_MULXri 591 +#define SP_MULXrr 592 +#define SP_NOP 593 +#define SP_ORCCri 594 +#define SP_ORCCrr 595 +#define SP_ORNCCri 596 +#define SP_ORNCCrr 597 +#define SP_ORNri 598 +#define SP_ORNrr 599 +#define SP_ORXNrr 600 +#define SP_ORXri 601 +#define SP_ORXrr 602 +#define SP_ORri 603 +#define SP_ORrr 604 +#define SP_PDIST 605 +#define SP_PDISTN 606 +#define SP_POPCrr 607 +#define SP_PREFETCHi 608 +#define SP_PREFETCHr 609 +#define SP_PWRPSRri 610 +#define SP_PWRPSRrr 611 +#define SP_RDASR 612 +#define SP_RDPC 613 +#define SP_RDPR 614 +#define SP_RDPSR 615 +#define SP_RDTBR 616 +#define SP_RDWIM 617 +#define SP_RESTOREri 618 +#define SP_RESTORErr 619 +#define SP_RET 620 +#define SP_RETL 621 +#define SP_RETTri 622 +#define SP_RETTrr 623 +#define SP_SAVEri 624 +#define SP_SAVErr 625 +#define SP_SDIVCCri 626 +#define SP_SDIVCCrr 627 +#define SP_SDIVXri 628 +#define SP_SDIVXrr 629 +#define SP_SDIVri 630 +#define SP_SDIVrr 631 +#define SP_SETHIXi 632 +#define SP_SETHIi 633 +#define SP_SHUTDOWN 634 +#define SP_SIAM 635 +#define SP_SIR 636 +#define SP_SLLXri 637 +#define SP_SLLXrr 638 +#define SP_SLLri 639 +#define SP_SLLrr 640 +#define SP_SMACri 641 +#define SP_SMACrr 642 +#define SP_SMULCCri 643 +#define SP_SMULCCrr 644 +#define SP_SMULri 645 +#define SP_SMULrr 646 +#define SP_SRAXri 647 +#define SP_SRAXrr 648 +#define SP_SRAri 649 +#define SP_SRArr 650 +#define SP_SRLXri 651 +#define SP_SRLXrr 652 +#define SP_SRLri 653 +#define SP_SRLrr 654 +#define SP_STArr 655 +#define SP_STBAR 656 +#define SP_STBArr 657 +#define SP_STBri 658 +#define SP_STBrr 659 +#define SP_STCSRri 660 +#define SP_STCSRrr 661 +#define SP_STCri 662 +#define SP_STCrr 663 +#define SP_STDArr 664 +#define SP_STDCQri 665 +#define SP_STDCQrr 666 +#define SP_STDCri 667 +#define SP_STDCrr 668 +#define SP_STDFArr 669 +#define SP_STDFQri 670 +#define SP_STDFQrr 671 +#define SP_STDFri 672 +#define SP_STDFrr 673 +#define SP_STDri 674 +#define SP_STDrr 675 +#define SP_STFArr 676 +#define SP_STFSRri 677 +#define SP_STFSRrr 678 +#define SP_STFri 679 +#define SP_STFrr 680 +#define SP_STHArr 681 +#define SP_STHri 682 +#define SP_STHrr 683 +#define SP_STQFArr 684 +#define SP_STQFri 685 +#define SP_STQFrr 686 +#define SP_STXFSRri 687 +#define SP_STXFSRrr 688 +#define SP_STXri 689 +#define SP_STXrr 690 +#define SP_STri 691 +#define SP_STrr 692 +#define SP_SUBCCri 693 +#define SP_SUBCCrr 694 +#define SP_SUBCri 695 +#define SP_SUBCrr 696 +#define SP_SUBEri 697 +#define SP_SUBErr 698 +#define SP_SUBXri 699 +#define SP_SUBXrr 700 +#define SP_SUBri 701 +#define SP_SUBrr 702 +#define SP_SWAPArr 703 +#define SP_SWAPri 704 +#define SP_SWAPrr 705 +#define SP_TA1 706 +#define SP_TA3 707 +#define SP_TA5 708 +#define SP_TADDCCTVri 709 +#define SP_TADDCCTVrr 710 +#define SP_TADDCCri 711 +#define SP_TADDCCrr 712 +#define SP_TICCri 713 +#define SP_TICCrr 714 +#define SP_TLS_ADDXrr 715 +#define SP_TLS_ADDrr 716 +#define SP_TLS_CALL 717 +#define SP_TLS_LDXrr 718 +#define SP_TLS_LDrr 719 +#define SP_TRAPri 720 +#define SP_TRAPrr 721 +#define SP_TSUBCCTVri 722 +#define SP_TSUBCCTVrr 723 +#define SP_TSUBCCri 724 +#define SP_TSUBCCrr 725 +#define SP_TXCCri 726 +#define SP_TXCCrr 727 +#define SP_UDIVCCri 728 +#define SP_UDIVCCrr 729 +#define SP_UDIVXri 730 +#define SP_UDIVXrr 731 +#define SP_UDIVri 732 +#define SP_UDIVrr 733 +#define SP_UMACri 734 +#define SP_UMACrr 735 +#define SP_UMULCCri 736 +#define SP_UMULCCrr 737 +#define SP_UMULXHI 738 +#define SP_UMULri 739 +#define SP_UMULrr 740 +#define SP_UNIMP 741 +#define SP_V9FCMPD 742 +#define SP_V9FCMPED 743 +#define SP_V9FCMPEQ 744 +#define SP_V9FCMPES 745 +#define SP_V9FCMPQ 746 +#define SP_V9FCMPS 747 +#define SP_V9FMOVD_FCC 748 +#define SP_V9FMOVQ_FCC 749 +#define SP_V9FMOVS_FCC 750 +#define SP_V9MOVFCCri 751 +#define SP_V9MOVFCCrr 752 +#define SP_WRASRri 753 +#define SP_WRASRrr 754 +#define SP_WRPRri 755 +#define SP_WRPRrr 756 +#define SP_WRPSRri 757 +#define SP_WRPSRrr 758 +#define SP_WRTBRri 759 +#define SP_WRTBRrr 760 +#define SP_WRWIMri 761 +#define SP_WRWIMrr 762 +#define SP_XMULX 763 +#define SP_XMULXHI 764 +#define SP_XNORCCri 765 +#define SP_XNORCCrr 766 +#define SP_XNORXrr 767 +#define SP_XNORri 768 +#define SP_XNORrr 769 +#define SP_XORCCri 770 +#define SP_XORCCrr 771 +#define SP_XORXri 772 +#define SP_XORXrr 773 +#define SP_XORri 774 +#define SP_XORrr 775 +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_REGINFO_EXTRA +#undef GET_REGINFO_EXTRA + + // Subregister indices + + enum { + NoSubRegister, + SP_sub_even, // 1 + SP_sub_even64, // 2 + SP_sub_odd, // 3 + SP_sub_odd64, // 4 + SP_sub_odd64_then_sub_even, // 5 + SP_sub_odd64_then_sub_odd, // 6 + SP_NUM_TARGET_SUBREGS + }; +#endif // GET_REGINFO_EXTRA + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg SparcRegDiffLists[] = { + /* 0 */ 64868, 1, 1, 1, 0, + /* 5 */ 32, 1, 0, + /* 8 */ 65436, 32, 1, 65504, 33, 1, 0, + /* 15 */ 34, 1, 0, + /* 18 */ 65437, 34, 1, 65502, 35, 1, 0, + /* 25 */ 36, 1, 0, + /* 28 */ 65438, 36, 1, 65500, 37, 1, 0, + /* 35 */ 38, 1, 0, + /* 38 */ 65439, 38, 1, 65498, 39, 1, 0, + /* 45 */ 40, 1, 0, + /* 48 */ 65440, 40, 1, 65496, 41, 1, 0, + /* 55 */ 42, 1, 0, + /* 58 */ 65441, 42, 1, 65494, 43, 1, 0, + /* 65 */ 44, 1, 0, + /* 68 */ 65442, 44, 1, 65492, 45, 1, 0, + /* 75 */ 46, 1, 0, + /* 78 */ 65443, 46, 1, 65490, 47, 1, 0, + /* 85 */ 65182, 1, 0, + /* 88 */ 65234, 1, 0, + /* 91 */ 65262, 1, 0, + /* 94 */ 65388, 1, 0, + /* 97 */ 65389, 1, 0, + /* 100 */ 65390, 1, 0, + /* 103 */ 65391, 1, 0, + /* 106 */ 65392, 1, 0, + /* 109 */ 65393, 1, 0, + /* 112 */ 65394, 1, 0, + /* 115 */ 65395, 1, 0, + /* 118 */ 65396, 1, 0, + /* 121 */ 65397, 1, 0, + /* 124 */ 65398, 1, 0, + /* 127 */ 65399, 1, 0, + /* 130 */ 65400, 1, 0, + /* 133 */ 65401, 1, 0, + /* 136 */ 65402, 1, 0, + /* 139 */ 65403, 1, 0, + /* 142 */ 65444, 1, 0, + /* 145 */ 65445, 1, 0, + /* 148 */ 65446, 1, 0, + /* 151 */ 65447, 1, 0, + /* 154 */ 65448, 1, 0, + /* 157 */ 65449, 1, 0, + /* 160 */ 65450, 1, 0, + /* 163 */ 65451, 1, 0, + /* 166 */ 65472, 1, 0, + /* 169 */ 65473, 1, 0, + /* 172 */ 65474, 1, 0, + /* 175 */ 65475, 1, 0, + /* 178 */ 65476, 1, 0, + /* 181 */ 65477, 1, 0, + /* 184 */ 65478, 1, 0, + /* 187 */ 65479, 1, 0, + /* 190 */ 65480, 1, 0, + /* 193 */ 65481, 1, 0, + /* 196 */ 65482, 1, 0, + /* 199 */ 65483, 1, 0, + /* 202 */ 65484, 1, 0, + /* 205 */ 65485, 1, 0, + /* 208 */ 65486, 1, 0, + /* 211 */ 65487, 1, 0, + /* 214 */ 15, 0, + /* 216 */ 48, 0, + /* 218 */ 49, 0, + /* 220 */ 50, 0, + /* 222 */ 51, 0, + /* 224 */ 52, 0, + /* 226 */ 53, 0, + /* 228 */ 54, 0, + /* 230 */ 55, 0, + /* 232 */ 56, 0, + /* 234 */ 57, 0, + /* 236 */ 58, 0, + /* 238 */ 59, 0, + /* 240 */ 60, 0, + /* 242 */ 61, 0, + /* 244 */ 62, 0, + /* 246 */ 63, 0, + /* 248 */ 64, 0, + /* 250 */ 84, 0, + /* 252 */ 85, 0, + /* 254 */ 86, 0, + /* 256 */ 87, 0, + /* 258 */ 88, 0, + /* 260 */ 89, 0, + /* 262 */ 90, 0, + /* 264 */ 91, 0, + /* 266 */ 65488, 92, 0, + /* 269 */ 65489, 92, 0, + /* 272 */ 65489, 93, 0, + /* 275 */ 65490, 93, 0, + /* 278 */ 65491, 93, 0, + /* 281 */ 65491, 94, 0, + /* 284 */ 65492, 94, 0, + /* 287 */ 65493, 94, 0, + /* 290 */ 65493, 95, 0, + /* 293 */ 65494, 95, 0, + /* 296 */ 65495, 95, 0, + /* 299 */ 65495, 96, 0, + /* 302 */ 65496, 96, 0, + /* 305 */ 65497, 96, 0, + /* 308 */ 65497, 97, 0, + /* 311 */ 65498, 97, 0, + /* 314 */ 65499, 97, 0, + /* 317 */ 65499, 98, 0, + /* 320 */ 65500, 98, 0, + /* 323 */ 65501, 98, 0, + /* 326 */ 65501, 99, 0, + /* 329 */ 65502, 99, 0, + /* 332 */ 65503, 99, 0, + /* 335 */ 65503, 100, 0, + /* 338 */ 65504, 100, 0, + /* 341 */ 132, 0, + /* 343 */ 133, 0, + /* 345 */ 134, 0, + /* 347 */ 135, 0, + /* 349 */ 136, 0, + /* 351 */ 137, 0, + /* 353 */ 138, 0, + /* 355 */ 139, 0, + /* 357 */ 140, 0, + /* 359 */ 141, 0, + /* 361 */ 142, 0, + /* 363 */ 143, 0, + /* 365 */ 144, 0, + /* 367 */ 145, 0, + /* 369 */ 146, 0, + /* 371 */ 147, 0, + /* 373 */ 148, 0, + /* 375 */ 65503, 0, + /* 377 */ 65519, 0, + /* 379 */ 65535, 0, +}; + +static const uint16_t SparcSubRegIdxLists[] = { + /* 0 */ 1, 3, 0, + /* 3 */ 2, 4, 0, + /* 6 */ 2, 1, 3, 4, 5, 6, 0, +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char SparcRegStrings[] = { + /* 0 */ "C10\0" + /* 4 */ "D10\0" + /* 8 */ "F10\0" + /* 12 */ "Q10\0" + /* 16 */ "ASR10\0" + /* 22 */ "C20\0" + /* 26 */ "D20\0" + /* 30 */ "F20\0" + /* 34 */ "ASR20\0" + /* 40 */ "C30\0" + /* 44 */ "D30\0" + /* 48 */ "F30\0" + /* 52 */ "ASR30\0" + /* 58 */ "FCC0\0" + /* 63 */ "D0\0" + /* 66 */ "F0\0" + /* 69 */ "G0\0" + /* 72 */ "I0\0" + /* 75 */ "L0\0" + /* 78 */ "O0\0" + /* 81 */ "Q0\0" + /* 84 */ "C10_C11\0" + /* 92 */ "D11\0" + /* 96 */ "F11\0" + /* 100 */ "Q11\0" + /* 104 */ "ASR11\0" + /* 110 */ "C20_C21\0" + /* 118 */ "D21\0" + /* 122 */ "F21\0" + /* 126 */ "ASR21\0" + /* 132 */ "C30_C31\0" + /* 140 */ "D31\0" + /* 144 */ "F31\0" + /* 148 */ "ASR31\0" + /* 154 */ "FCC1\0" + /* 159 */ "C0_C1\0" + /* 165 */ "D1\0" + /* 168 */ "F1\0" + /* 171 */ "G0_G1\0" + /* 177 */ "I0_I1\0" + /* 183 */ "L0_L1\0" + /* 189 */ "O0_O1\0" + /* 195 */ "Q1\0" + /* 198 */ "ASR1\0" + /* 203 */ "C12\0" + /* 207 */ "D12\0" + /* 211 */ "F12\0" + /* 215 */ "Q12\0" + /* 219 */ "ASR12\0" + /* 225 */ "C22\0" + /* 229 */ "D22\0" + /* 233 */ "F22\0" + /* 237 */ "ASR22\0" + /* 243 */ "FCC2\0" + /* 248 */ "D2\0" + /* 251 */ "F2\0" + /* 254 */ "G2\0" + /* 257 */ "I2\0" + /* 260 */ "L2\0" + /* 263 */ "O2\0" + /* 266 */ "Q2\0" + /* 269 */ "ASR2\0" + /* 274 */ "C12_C13\0" + /* 282 */ "D13\0" + /* 286 */ "F13\0" + /* 290 */ "Q13\0" + /* 294 */ "ASR13\0" + /* 300 */ "C22_C23\0" + /* 308 */ "D23\0" + /* 312 */ "F23\0" + /* 316 */ "ASR23\0" + /* 322 */ "FCC3\0" + /* 327 */ "C2_C3\0" + /* 333 */ "D3\0" + /* 336 */ "F3\0" + /* 339 */ "G2_G3\0" + /* 345 */ "I2_I3\0" + /* 351 */ "L2_L3\0" + /* 357 */ "O2_O3\0" + /* 363 */ "Q3\0" + /* 366 */ "ASR3\0" + /* 371 */ "C14\0" + /* 375 */ "D14\0" + /* 379 */ "F14\0" + /* 383 */ "Q14\0" + /* 387 */ "ASR14\0" + /* 393 */ "C24\0" + /* 397 */ "D24\0" + /* 401 */ "F24\0" + /* 405 */ "ASR24\0" + /* 411 */ "C4\0" + /* 414 */ "D4\0" + /* 417 */ "F4\0" + /* 420 */ "G4\0" + /* 423 */ "I4\0" + /* 426 */ "L4\0" + /* 429 */ "O4\0" + /* 432 */ "Q4\0" + /* 435 */ "ASR4\0" + /* 440 */ "C14_C15\0" + /* 448 */ "D15\0" + /* 452 */ "F15\0" + /* 456 */ "Q15\0" + /* 460 */ "ASR15\0" + /* 466 */ "C24_C25\0" + /* 474 */ "D25\0" + /* 478 */ "F25\0" + /* 482 */ "ASR25\0" + /* 488 */ "C4_C5\0" + /* 494 */ "D5\0" + /* 497 */ "F5\0" + /* 500 */ "G4_G5\0" + /* 506 */ "I4_I5\0" + /* 512 */ "L4_L5\0" + /* 518 */ "O4_O5\0" + /* 524 */ "Q5\0" + /* 527 */ "ASR5\0" + /* 532 */ "C16\0" + /* 536 */ "D16\0" + /* 540 */ "F16\0" + /* 544 */ "ASR16\0" + /* 550 */ "C26\0" + /* 554 */ "D26\0" + /* 558 */ "F26\0" + /* 562 */ "ASR26\0" + /* 568 */ "C6\0" + /* 571 */ "D6\0" + /* 574 */ "F6\0" + /* 577 */ "G6\0" + /* 580 */ "I6\0" + /* 583 */ "L6\0" + /* 586 */ "O6\0" + /* 589 */ "Q6\0" + /* 592 */ "ASR6\0" + /* 597 */ "C16_C17\0" + /* 605 */ "D17\0" + /* 609 */ "F17\0" + /* 613 */ "ASR17\0" + /* 619 */ "C26_C27\0" + /* 627 */ "D27\0" + /* 631 */ "F27\0" + /* 635 */ "ASR27\0" + /* 641 */ "C6_C7\0" + /* 647 */ "D7\0" + /* 650 */ "F7\0" + /* 653 */ "G6_G7\0" + /* 659 */ "I6_I7\0" + /* 665 */ "L6_L7\0" + /* 671 */ "O6_O7\0" + /* 677 */ "Q7\0" + /* 680 */ "ASR7\0" + /* 685 */ "C18\0" + /* 689 */ "D18\0" + /* 693 */ "F18\0" + /* 697 */ "ASR18\0" + /* 703 */ "C28\0" + /* 707 */ "D28\0" + /* 711 */ "F28\0" + /* 715 */ "ASR28\0" + /* 721 */ "C8\0" + /* 724 */ "D8\0" + /* 727 */ "F8\0" + /* 730 */ "Q8\0" + /* 733 */ "ASR8\0" + /* 738 */ "C18_C19\0" + /* 746 */ "D19\0" + /* 750 */ "F19\0" + /* 754 */ "ASR19\0" + /* 760 */ "C28_C29\0" + /* 768 */ "D29\0" + /* 772 */ "F29\0" + /* 776 */ "ASR29\0" + /* 782 */ "C8_C9\0" + /* 788 */ "D9\0" + /* 791 */ "F9\0" + /* 794 */ "Q9\0" + /* 797 */ "ASR9\0" + /* 802 */ "TBA\0" + /* 806 */ "ICC\0" + /* 810 */ "TNPC\0" + /* 815 */ "TPC\0" + /* 819 */ "CANRESTORE\0" + /* 830 */ "PSTATE\0" + /* 837 */ "TSTATE\0" + /* 844 */ "WSTATE\0" + /* 851 */ "CANSAVE\0" + /* 859 */ "TICK\0" + /* 864 */ "PIL\0" + /* 868 */ "TL\0" + /* 871 */ "WIM\0" + /* 875 */ "CLEANWIN\0" + /* 884 */ "OTHERWIN\0" + /* 893 */ "CWP\0" + /* 897 */ "FQ\0" + /* 900 */ "CPQ\0" + /* 904 */ "TBR\0" + /* 908 */ "FSR\0" + /* 912 */ "CPSR\0" + /* 917 */ "TT\0" + /* 920 */ "Y\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterDesc SparcRegDesc[] = { + // Descriptors + {3, 0, 0, 0, 0, 0}, {819, 4, 4, 2, 6065, 91}, + {851, 4, 4, 2, 6065, 91}, {875, 4, 4, 2, 6065, 334}, + {900, 4, 4, 2, 6065, 129}, {912, 4, 4, 2, 6065, 352}, + {893, 4, 4, 2, 6065, 3}, {897, 4, 4, 2, 6065, 290}, + {908, 4, 4, 2, 6065, 350}, {806, 4, 4, 2, 6065, 260}, + {884, 4, 4, 2, 6065, 269}, {812, 4, 4, 2, 6065, 356}, + {864, 4, 4, 2, 6065, 358}, {913, 4, 4, 2, 6065, 354}, + {830, 4, 4, 2, 6065, 86}, {802, 4, 4, 2, 6065, 6}, + {904, 4, 4, 2, 6065, 3}, {859, 4, 4, 2, 6065, 284}, + {868, 4, 4, 2, 6065, 17}, {810, 4, 4, 2, 6065, 286}, + {815, 4, 4, 2, 6065, 288}, {837, 4, 4, 2, 6065, 134}, + {917, 4, 4, 2, 6065, 136}, {871, 4, 4, 2, 6065, 138}, + {844, 4, 4, 2, 6065, 3}, {920, 4, 4, 2, 6065, 3}, + {198, 4, 4, 2, 6065, 3}, {269, 4, 4, 2, 6065, 324}, + {366, 4, 4, 2, 6065, 329}, {435, 4, 4, 2, 6065, 21}, + {527, 4, 4, 2, 6065, 350}, {592, 4, 4, 2, 6065, 86}, + {680, 4, 4, 2, 6065, 140}, {733, 4, 4, 2, 6065, 38}, + {797, 4, 4, 2, 6065, 125}, {16, 4, 4, 2, 6065, 64}, + {104, 4, 4, 2, 6065, 47}, {219, 4, 4, 2, 6065, 209}, + {294, 4, 4, 2, 6065, 275}, {387, 4, 4, 2, 6065, 86}, + {460, 4, 4, 2, 6065, 91}, {544, 4, 4, 2, 6065, 273}, + {613, 4, 4, 2, 6065, 3}, {697, 4, 4, 2, 6065, 271}, + {754, 4, 4, 2, 6065, 3}, {34, 4, 4, 2, 6065, 3}, + {126, 4, 4, 2, 6065, 311}, {237, 4, 4, 2, 6065, 40}, + {316, 4, 4, 2, 6065, 77}, {405, 4, 4, 2, 6065, 280}, + {482, 4, 4, 2, 6065, 350}, {562, 4, 4, 2, 6065, 313}, + {635, 4, 4, 2, 6065, 318}, {715, 4, 4, 2, 6065, 40}, + {776, 4, 4, 2, 6065, 267}, {52, 4, 4, 2, 6065, 3}, + {148, 4, 4, 2, 6065, 91}, {60, 4, 373, 2, 6065, 320}, + {156, 4, 371, 2, 6065, 3}, {245, 4, 371, 2, 6065, 66}, + {324, 4, 369, 2, 6065, 350}, {411, 4, 369, 2, 6065, 336}, + {491, 4, 367, 2, 6065, 280}, {568, 4, 367, 2, 6065, 68}, + {644, 4, 365, 2, 6065, 322}, {721, 4, 365, 2, 6065, 336}, + {785, 4, 363, 2, 6065, 91}, {0, 4, 363, 2, 6065, 64}, + {88, 4, 361, 2, 6065, 91}, {203, 4, 361, 2, 6065, 3}, + {278, 4, 359, 2, 6065, 91}, {371, 4, 359, 2, 6065, 3}, + {444, 4, 357, 2, 6065, 91}, {532, 4, 357, 2, 6065, 294}, + {601, 4, 355, 2, 6065, 292}, {685, 4, 355, 2, 6065, 40}, + {742, 4, 353, 2, 6065, 3}, {22, 4, 353, 2, 6065, 91}, + {114, 4, 351, 2, 6065, 296}, {225, 4, 351, 2, 6065, 88}, + {304, 4, 349, 2, 6065, 6}, {393, 4, 349, 2, 6065, 3}, + {470, 4, 347, 2, 6065, 298}, {550, 4, 347, 2, 6065, 91}, + {623, 4, 345, 2, 6065, 300}, {703, 4, 345, 2, 6065, 82}, + {764, 4, 343, 2, 6065, 15}, {40, 4, 343, 2, 6065, 91}, + {136, 4, 341, 2, 6065, 282}, {63, 5, 336, 0, 2370, 93}, + {165, 12, 327, 0, 2370, 56}, {248, 15, 327, 0, 2370, 305}, + {333, 22, 318, 0, 2370, 101}, {414, 25, 318, 0, 2370, 44}, + {494, 32, 309, 0, 2370, 302}, {571, 35, 309, 0, 2370, 104}, + {647, 42, 300, 0, 2370, 308}, {724, 45, 300, 0, 2370, 347}, + {788, 52, 291, 0, 2370, 79}, {4, 55, 291, 0, 2370, 326}, + {92, 62, 282, 0, 2370, 338}, {207, 65, 282, 0, 2370, 315}, + {282, 72, 273, 0, 2370, 111}, {375, 75, 273, 0, 2370, 148}, + {448, 82, 267, 0, 2370, 93}, {536, 4, 267, 2, 3425, 109}, + {605, 4, 264, 2, 3425, 118}, {689, 4, 264, 2, 3425, 142}, + {746, 4, 262, 2, 3425, 151}, {26, 4, 262, 2, 3425, 91}, + {118, 4, 260, 2, 3425, 153}, {229, 4, 260, 2, 3425, 91}, + {308, 4, 258, 2, 3425, 3}, {397, 4, 258, 2, 3425, 86}, + {474, 4, 256, 2, 3425, 160}, {554, 4, 256, 2, 3425, 91}, + {627, 4, 254, 2, 3425, 162}, {707, 4, 254, 2, 3425, 146}, + {768, 4, 252, 2, 3425, 91}, {44, 4, 252, 2, 3425, 166}, + {140, 4, 250, 2, 3425, 42}, {66, 4, 338, 2, 6001, 107}, + {168, 4, 335, 2, 6001, 164}, {251, 4, 332, 2, 6001, 164}, + {336, 4, 329, 2, 6001, 91}, {417, 4, 329, 2, 6001, 91}, + {497, 4, 326, 2, 6001, 9}, {574, 4, 323, 2, 6001, 91}, + {650, 4, 320, 2, 6001, 176}, {727, 4, 320, 2, 6001, 140}, + {791, 4, 317, 2, 6001, 3}, {8, 4, 314, 2, 6001, 350}, + {96, 4, 311, 2, 6001, 3}, {211, 4, 311, 2, 6001, 178}, + {286, 4, 308, 2, 6001, 180}, {379, 4, 305, 2, 6001, 182}, + {452, 4, 302, 2, 6001, 40}, {540, 4, 302, 2, 6001, 3}, + {609, 4, 299, 2, 6001, 6}, {693, 4, 296, 2, 6001, 3}, + {750, 4, 293, 2, 6001, 77}, {30, 4, 293, 2, 6001, 184}, + {122, 4, 290, 2, 6001, 91}, {233, 4, 287, 2, 6001, 186}, + {312, 4, 284, 2, 6001, 91}, {401, 4, 284, 2, 6001, 74}, + {478, 4, 281, 2, 6001, 84}, {558, 4, 278, 2, 6001, 3}, + {631, 4, 275, 2, 6001, 188}, {711, 4, 275, 2, 6001, 49}, + {772, 4, 272, 2, 6001, 42}, {48, 4, 269, 2, 6001, 62}, + {144, 4, 266, 2, 6001, 193}, {58, 4, 4, 2, 6033, 3}, + {154, 4, 4, 2, 6033, 54}, {243, 4, 4, 2, 6033, 197}, + {322, 4, 4, 2, 6033, 195}, {69, 4, 248, 2, 6033, 144}, + {174, 4, 246, 2, 6033, 114}, {254, 4, 246, 2, 6033, 120}, + {342, 4, 244, 2, 6033, 127}, {420, 4, 244, 2, 6033, 3}, + {503, 4, 242, 2, 6033, 3}, {577, 4, 242, 2, 6033, 3}, + {656, 4, 240, 2, 6033, 116}, {72, 4, 240, 2, 6033, 3}, + {180, 4, 238, 2, 6033, 199}, {257, 4, 238, 2, 6033, 207}, + {348, 4, 236, 2, 6033, 203}, {423, 4, 236, 2, 6033, 19}, + {509, 4, 234, 2, 6033, 15}, {580, 4, 234, 2, 6033, 211}, + {662, 4, 232, 2, 6033, 21}, {75, 4, 232, 2, 6033, 201}, + {186, 4, 230, 2, 6033, 3}, {260, 4, 230, 2, 6033, 205}, + {354, 4, 228, 2, 6033, 3}, {426, 4, 228, 2, 6033, 215}, + {515, 4, 226, 2, 6033, 213}, {583, 4, 226, 2, 6033, 70}, + {668, 4, 224, 2, 6033, 217}, {78, 4, 224, 2, 6033, 12}, + {192, 4, 222, 2, 6033, 72}, {263, 4, 222, 2, 6033, 3}, + {360, 4, 220, 2, 6033, 221}, {429, 4, 220, 2, 6033, 219}, + {521, 4, 218, 2, 6033, 3}, {586, 4, 218, 2, 6033, 3}, + {674, 4, 216, 2, 6033, 3}, {81, 8, 4, 6, 4, 26}, + {195, 18, 4, 6, 4, 0}, {266, 28, 4, 6, 4, 223}, + {363, 38, 4, 6, 4, 228}, {432, 48, 4, 6, 4, 168}, + {524, 58, 4, 6, 4, 155}, {589, 68, 4, 6, 4, 96}, + {677, 78, 4, 6, 4, 262}, {730, 142, 4, 3, 1458, 331}, + {794, 145, 4, 3, 1458, 190}, {12, 148, 4, 3, 1458, 28}, + {100, 151, 4, 3, 1458, 2}, {215, 154, 4, 3, 1458, 233}, + {290, 157, 4, 3, 1458, 236}, {383, 160, 4, 3, 1458, 2}, + {456, 163, 4, 3, 1458, 34}, {159, 94, 4, 0, 1362, 239}, + {327, 97, 4, 0, 1362, 131}, {488, 100, 4, 0, 1362, 23}, + {641, 103, 4, 0, 1362, 14}, {782, 106, 4, 0, 1362, 93}, + {84, 109, 4, 0, 1362, 93}, {274, 112, 4, 0, 1362, 242}, + {440, 115, 4, 0, 1362, 31}, {597, 118, 4, 0, 1362, 8}, + {738, 121, 4, 0, 1362, 122}, {110, 124, 4, 0, 1362, 277}, + {300, 127, 4, 0, 1362, 173}, {466, 130, 4, 0, 1362, 344}, + {619, 133, 4, 0, 1362, 2}, {760, 136, 4, 0, 1362, 59}, + {132, 139, 4, 0, 1362, 11}, {171, 166, 4, 0, 1410, 37}, + {339, 169, 4, 0, 1410, 93}, {500, 172, 4, 0, 1410, 245}, + {653, 175, 4, 0, 1410, 93}, {177, 178, 4, 0, 1410, 248}, + {345, 181, 4, 0, 1410, 93}, {506, 184, 4, 0, 1410, 251}, + {659, 187, 4, 0, 1410, 341}, {183, 190, 4, 0, 1410, 23}, + {351, 193, 4, 0, 1410, 51}, {512, 196, 4, 0, 1410, 5}, + {665, 199, 4, 0, 1410, 254}, {189, 202, 4, 0, 1410, 90}, + {357, 205, 4, 0, 1410, 257}, {518, 208, 4, 0, 1410, 76}, + {671, 211, 4, 0, 1410, 2}, +}; + +// FCCRegs Register Class... +static const MCPhysReg FCCRegs[] = { + SP_FCC0, + SP_FCC1, + SP_FCC2, + SP_FCC3, +}; + +// FCCRegs Bit set. +static const uint8_t FCCRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, +}; + +// ASRRegs Register Class... +static const MCPhysReg ASRRegs[] = { + SP_Y, SP_ASR1, SP_ASR2, SP_ASR3, SP_ASR4, SP_ASR5, SP_ASR6, + SP_ASR7, SP_ASR8, SP_ASR9, SP_ASR10, SP_ASR11, SP_ASR12, SP_ASR13, + SP_ASR14, SP_ASR15, SP_ASR16, SP_ASR17, SP_ASR18, SP_ASR19, SP_ASR20, + SP_ASR21, SP_ASR22, SP_ASR23, SP_ASR24, SP_ASR25, SP_ASR26, SP_ASR27, + SP_ASR28, SP_ASR29, SP_ASR30, SP_ASR31, +}; + +// ASRRegs Bit set. +static const uint8_t ASRRegsBits[] = { + 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// CoprocRegs Register Class... +static const MCPhysReg CoprocRegs[] = { + SP_C0, SP_C1, SP_C2, SP_C3, SP_C4, SP_C5, SP_C6, SP_C7, + SP_C8, SP_C9, SP_C10, SP_C11, SP_C12, SP_C13, SP_C14, SP_C15, + SP_C16, SP_C17, SP_C18, SP_C19, SP_C20, SP_C21, SP_C22, SP_C23, + SP_C24, SP_C25, SP_C26, SP_C27, SP_C28, SP_C29, SP_C30, SP_C31, +}; + +// CoprocRegs Bit set. +static const uint8_t CoprocRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// FPRegs Register Class... +static const MCPhysReg FPRegs[] = { + SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, + SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, + SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, + SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31, +}; + +// FPRegs Bit set. +static const uint8_t FPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// IntRegs Register Class... +static const MCPhysReg IntRegs[] = { + SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, + SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, + SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, +}; + +// IntRegs Bit set. +static const uint8_t IntRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, +}; + +// DFPRegs Register Class... +static const MCPhysReg DFPRegs[] = { + SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, + SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, + SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, + SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31, +}; + +// DFPRegs Bit set. +static const uint8_t DFPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, +}; + +// I64Regs Register Class... +static const MCPhysReg I64Regs[] = { + SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, + SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, + SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, +}; + +// I64Regs Bit set. +static const uint8_t I64RegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, +}; + +// CoprocPair Register Class... +static const MCPhysReg CoprocPair[] = { + SP_C0_C1, SP_C2_C3, SP_C4_C5, SP_C6_C7, SP_C8_C9, SP_C10_C11, + SP_C12_C13, SP_C14_C15, SP_C16_C17, SP_C18_C19, SP_C20_C21, SP_C22_C23, + SP_C24_C25, SP_C26_C27, SP_C28_C29, SP_C30_C31, +}; + +// CoprocPair Bit set. +static const uint8_t CoprocPairBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, +}; + +// IntPair Register Class... +static const MCPhysReg IntPair[] = { + SP_I0_I1, SP_I2_I3, SP_I4_I5, SP_I6_I7, SP_G0_G1, SP_G2_G3, + SP_G4_G5, SP_G6_G7, SP_L0_L1, SP_L2_L3, SP_L4_L5, SP_L6_L7, + SP_O0_O1, SP_O2_O3, SP_O4_O5, SP_O6_O7, +}; + +// IntPair Bit set. +static const uint8_t IntPairBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, +}; + +// LowDFPRegs Register Class... +static const MCPhysReg LowDFPRegs[] = { + SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, + SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, +}; + +// LowDFPRegs Bit set. +static const uint8_t LowDFPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, +}; + +// PRRegs Register Class... +static const MCPhysReg PRRegs[] = { + SP_TPC, SP_TNPC, SP_TSTATE, SP_TT, SP_TICK, + SP_TBA, SP_PSTATE, SP_TL, SP_PIL, SP_CWP, + SP_CANSAVE, SP_CANRESTORE, SP_CLEANWIN, SP_OTHERWIN, SP_WSTATE, +}; + +// PRRegs Bit set. +static const uint8_t PRRegsBits[] = { + 0x4e, + 0xd4, + 0x7e, + 0x01, +}; + +// QFPRegs Register Class... +static const MCPhysReg QFPRegs[] = { + SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, + SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15, +}; + +// QFPRegs Bit set. +static const uint8_t QFPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, +}; + +// LowQFPRegs Register Class... +static const MCPhysReg LowQFPRegs[] = { + SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, +}; + +// LowQFPRegs Bit set. +static const uint8_t LowQFPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, +}; + +// end of register classes misc + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char SparcRegClassStrings[] = { + /* 0 */ "CoprocPair\0" + /* 11 */ "IntPair\0" + /* 19 */ "I64Regs\0" + /* 27 */ "FCCRegs\0" + /* 35 */ "LowDFPRegs\0" + /* 46 */ "LowQFPRegs\0" + /* 57 */ "PRRegs\0" + /* 64 */ "ASRRegs\0" + /* 72 */ "CoprocRegs\0" + /* 83 */ "IntRegs\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterClass SparcMCRegisterClasses[] = { + {FCCRegs, FCCRegsBits, sizeof(FCCRegsBits)}, + {ASRRegs, ASRRegsBits, sizeof(ASRRegsBits)}, + {CoprocRegs, CoprocRegsBits, sizeof(CoprocRegsBits)}, + {FPRegs, FPRegsBits, sizeof(FPRegsBits)}, + {IntRegs, IntRegsBits, sizeof(IntRegsBits)}, + {DFPRegs, DFPRegsBits, sizeof(DFPRegsBits)}, + {I64Regs, I64RegsBits, sizeof(I64RegsBits)}, + {CoprocPair, CoprocPairBits, sizeof(CoprocPairBits)}, + {IntPair, IntPairBits, sizeof(IntPairBits)}, + {LowDFPRegs, LowDFPRegsBits, sizeof(LowDFPRegsBits)}, + {PRRegs, PRRegsBits, sizeof(PRRegsBits)}, + {QFPRegs, QFPRegsBits, sizeof(QFPRegsBits)}, + {LowQFPRegs, LowQFPRegsBits, sizeof(LowQFPRegsBits)}, +}; + +#endif // GET_REGINFO_MC_DESC + +#ifdef GET_ASM_WRITER +#undef GET_ASM_WRITER + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +typedef struct MCMnemonic { + const char *first; + uint64_t second; +} MCMnemonic; + +static MCMnemonic createMnemonic(const char *first, uint64_t second) { + MCMnemonic mnemonic; + mnemonic.first = first; + mnemonic.second = second; + return mnemonic; +} + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +MCMnemonic Sparc_getMnemonic(const MCInst *MI) { + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "rd %pc, \0" + /* 9 */ "rd %wim, \0" + /* 19 */ "rd %tbr, \0" + /* 29 */ "rd %psr, \0" + /* 39 */ "fsrc1 \0" + /* 46 */ "fandnot1 \0" + /* 56 */ "fnot1 \0" + /* 63 */ "fornot1 \0" + /* 72 */ "fsra32 \0" + /* 80 */ "fpsub32 \0" + /* 89 */ "fpadd32 \0" + /* 98 */ "edge32 \0" + /* 106 */ "fcmple32 \0" + /* 116 */ "fcmpne32 \0" + /* 126 */ "fpack32 \0" + /* 135 */ "cmask32 \0" + /* 144 */ "fsll32 \0" + /* 152 */ "fsrl32 \0" + /* 160 */ "fcmpeq32 \0" + /* 170 */ "fslas32 \0" + /* 179 */ "fcmpgt32 \0" + /* 189 */ "array32 \0" + /* 198 */ "fsrc2 \0" + /* 205 */ "fandnot2 \0" + /* 215 */ "fnot2 \0" + /* 222 */ "fornot2 \0" + /* 231 */ "fpadd64 \0" + /* 240 */ "fsra16 \0" + /* 248 */ "fpsub16 \0" + /* 257 */ "fpadd16 \0" + /* 266 */ "edge16 \0" + /* 274 */ "fcmple16 \0" + /* 284 */ "fcmpne16 \0" + /* 294 */ "fpack16 \0" + /* 303 */ "cmask16 \0" + /* 312 */ "fsll16 \0" + /* 320 */ "fsrl16 \0" + /* 328 */ "fchksm16 \0" + /* 338 */ "fmean16 \0" + /* 347 */ "fcmpeq16 \0" + /* 357 */ "fslas16 \0" + /* 366 */ "fcmpgt16 \0" + /* 376 */ "fmul8x16 \0" + /* 386 */ "fmuld8ulx16 \0" + /* 399 */ "fmul8ulx16 \0" + /* 411 */ "fmuld8sux16 \0" + /* 424 */ "fmul8sux16 \0" + /* 436 */ "array16 \0" + /* 445 */ "edge8 \0" + /* 452 */ "cmask8 \0" + /* 460 */ "array8 \0" + /* 468 */ "!ADJCALLSTACKDOWN \0" + /* 487 */ "!ADJCALLSTACKUP \0" + /* 504 */ "fpsub32S \0" + /* 514 */ "fpsub16S \0" + /* 524 */ "brgez,a \0" + /* 533 */ "brlez,a \0" + /* 542 */ "brgz,a \0" + /* 550 */ "brlz,a \0" + /* 558 */ "brnz,a \0" + /* 566 */ "brz,a \0" + /* 573 */ "stba \0" + /* 579 */ "stda \0" + /* 585 */ "stha \0" + /* 591 */ "stqa \0" + /* 597 */ "sra \0" + /* 602 */ "faligndata \0" + /* 614 */ "sta \0" + /* 619 */ "stb \0" + /* 624 */ "sub \0" + /* 629 */ "smac \0" + /* 635 */ "umac \0" + /* 641 */ "tsubcc \0" + /* 649 */ "addxccc \0" + /* 658 */ "taddcc \0" + /* 666 */ "andcc \0" + /* 673 */ "smulcc \0" + /* 681 */ "umulcc \0" + /* 689 */ "andncc \0" + /* 697 */ "orncc \0" + /* 704 */ "xnorcc \0" + /* 712 */ "xorcc \0" + /* 719 */ "mulscc \0" + /* 727 */ "sdivcc \0" + /* 735 */ "udivcc \0" + /* 743 */ "subxcc \0" + /* 751 */ "addxcc \0" + /* 759 */ "popc \0" + /* 765 */ "addxc \0" + /* 772 */ "fsubd \0" + /* 779 */ "fhsubd \0" + /* 787 */ "add \0" + /* 792 */ "faddd \0" + /* 799 */ "fhaddd \0" + /* 807 */ "fnhaddd \0" + /* 816 */ "fnaddd \0" + /* 824 */ "fcmped \0" + /* 832 */ "fnegd \0" + /* 839 */ "fmuld \0" + /* 846 */ "fsmuld \0" + /* 854 */ "fand \0" + /* 860 */ "fnand \0" + /* 867 */ "fexpand \0" + /* 876 */ "fitod \0" + /* 883 */ "fqtod \0" + /* 890 */ "fstod \0" + /* 897 */ "fxtod \0" + /* 904 */ "fcmpd \0" + /* 911 */ "flcmpd \0" + /* 919 */ "rd \0" + /* 923 */ "fabsd \0" + /* 930 */ "fsqrtd \0" + /* 938 */ "std \0" + /* 943 */ "fdivd \0" + /* 950 */ "fmovd \0" + /* 957 */ "fpmerge \0" + /* 966 */ "bshuffle \0" + /* 976 */ "fone \0" + /* 982 */ "restore \0" + /* 991 */ "save \0" + /* 997 */ "flush \0" + /* 1004 */ "sth \0" + /* 1009 */ "sethi \0" + /* 1016 */ "umulxhi \0" + /* 1025 */ "xmulxhi \0" + /* 1034 */ "fdtoi \0" + /* 1041 */ "fqtoi \0" + /* 1048 */ "fstoi \0" + /* 1055 */ "bmask \0" + /* 1062 */ "edge32l \0" + /* 1071 */ "edge16l \0" + /* 1080 */ "edge8l \0" + /* 1088 */ "fmul8x16al \0" + /* 1100 */ "call \0" + /* 1106 */ "sll \0" + /* 1111 */ "jmpl \0" + /* 1117 */ "alignaddrl \0" + /* 1129 */ "srl \0" + /* 1134 */ "smul \0" + /* 1140 */ "umul \0" + /* 1146 */ "edge32n \0" + /* 1155 */ "edge16n \0" + /* 1164 */ "edge8n \0" + /* 1172 */ "andn \0" + /* 1178 */ "edge32ln \0" + /* 1188 */ "edge16ln \0" + /* 1198 */ "edge8ln \0" + /* 1207 */ "brgez,a,pn \0" + /* 1219 */ "brlez,a,pn \0" + /* 1231 */ "brgz,a,pn \0" + /* 1242 */ "brlz,a,pn \0" + /* 1253 */ "brnz,a,pn \0" + /* 1264 */ "brz,a,pn \0" + /* 1274 */ "brgez,pn \0" + /* 1284 */ "brlez,pn \0" + /* 1294 */ "brgz,pn \0" + /* 1303 */ "brlz,pn \0" + /* 1312 */ "brnz,pn \0" + /* 1321 */ "brz,pn \0" + /* 1329 */ "orn \0" + /* 1334 */ "pdistn \0" + /* 1342 */ "fzero \0" + /* 1349 */ "cmp \0" + /* 1354 */ "unimp \0" + /* 1361 */ "jmp \0" + /* 1366 */ "fsubq \0" + /* 1373 */ "faddq \0" + /* 1380 */ "fcmpeq \0" + /* 1388 */ "fnegq \0" + /* 1395 */ "fdmulq \0" + /* 1403 */ "fmulq \0" + /* 1410 */ "fdtoq \0" + /* 1417 */ "fitoq \0" + /* 1424 */ "fstoq \0" + /* 1431 */ "fxtoq \0" + /* 1438 */ "fcmpq \0" + /* 1445 */ "fabsq \0" + /* 1452 */ "fsqrtq \0" + /* 1460 */ "stq \0" + /* 1465 */ "fdivq \0" + /* 1472 */ "fmovq \0" + /* 1479 */ "membar \0" + /* 1487 */ "alignaddr \0" + /* 1498 */ "sir \0" + /* 1503 */ "for \0" + /* 1508 */ "fnor \0" + /* 1514 */ "fxnor \0" + /* 1521 */ "fxor \0" + /* 1527 */ "rdpr \0" + /* 1533 */ "wrpr \0" + /* 1539 */ "pwr \0" + /* 1544 */ "fsrc1s \0" + /* 1552 */ "fandnot1s \0" + /* 1563 */ "fnot1s \0" + /* 1571 */ "fornot1s \0" + /* 1581 */ "fpadd32s \0" + /* 1591 */ "fsrc2s \0" + /* 1599 */ "fandnot2s \0" + /* 1610 */ "fnot2s \0" + /* 1618 */ "fornot2s \0" + /* 1628 */ "fpadd16s \0" + /* 1638 */ "fsubs \0" + /* 1645 */ "fhsubs \0" + /* 1653 */ "fadds \0" + /* 1660 */ "fhadds \0" + /* 1668 */ "fnhadds \0" + /* 1677 */ "fnadds \0" + /* 1685 */ "fands \0" + /* 1692 */ "fnands \0" + /* 1700 */ "fones \0" + /* 1707 */ "fcmpes \0" + /* 1715 */ "fnegs \0" + /* 1722 */ "fmuls \0" + /* 1729 */ "fzeros \0" + /* 1737 */ "fdtos \0" + /* 1744 */ "fitos \0" + /* 1751 */ "fqtos \0" + /* 1758 */ "fxtos \0" + /* 1765 */ "fcmps \0" + /* 1772 */ "flcmps \0" + /* 1780 */ "fors \0" + /* 1786 */ "fnors \0" + /* 1793 */ "fxnors \0" + /* 1801 */ "fxors \0" + /* 1808 */ "fabss \0" + /* 1815 */ "fsqrts \0" + /* 1823 */ "fdivs \0" + /* 1830 */ "fmovs \0" + /* 1837 */ "set \0" + /* 1842 */ "lzcnt \0" + /* 1849 */ "pdist \0" + /* 1856 */ "rett \0" + /* 1862 */ "fmul8x16au \0" + /* 1874 */ "sdiv \0" + /* 1880 */ "udiv \0" + /* 1886 */ "tsubcctv \0" + /* 1896 */ "taddcctv \0" + /* 1906 */ "movstosw \0" + /* 1916 */ "movstouw \0" + /* 1926 */ "srax \0" + /* 1932 */ "subx \0" + /* 1938 */ "addx \0" + /* 1944 */ "fpackfix \0" + /* 1954 */ "sllx \0" + /* 1960 */ "srlx \0" + /* 1966 */ "xmulx \0" + /* 1973 */ "fdtox \0" + /* 1980 */ "movdtox \0" + /* 1989 */ "fqtox \0" + /* 1996 */ "fstox \0" + /* 2003 */ "stx \0" + /* 2008 */ "sdivx \0" + /* 2015 */ "udivx \0" + /* 2022 */ "fmovrdz \0" + /* 2031 */ "fmovrdgez \0" + /* 2042 */ "fmovrqgez \0" + /* 2053 */ "brgez \0" + /* 2060 */ "movrgez \0" + /* 2069 */ "fmovrsgez \0" + /* 2080 */ "fmovrdlez \0" + /* 2091 */ "fmovrqlez \0" + /* 2102 */ "brlez \0" + /* 2109 */ "movrlez \0" + /* 2118 */ "fmovrslez \0" + /* 2129 */ "fmovrdgz \0" + /* 2139 */ "fmovrqgz \0" + /* 2149 */ "brgz \0" + /* 2155 */ "movrgz \0" + /* 2163 */ "fmovrsgz \0" + /* 2173 */ "fmovrdlz \0" + /* 2183 */ "fmovrqlz \0" + /* 2193 */ "brlz \0" + /* 2199 */ "movrlz \0" + /* 2207 */ "fmovrslz \0" + /* 2217 */ "fmovrdnz \0" + /* 2227 */ "fmovrqnz \0" + /* 2237 */ "brnz \0" + /* 2243 */ "movrnz \0" + /* 2251 */ "fmovrsnz \0" + /* 2261 */ "fmovrqz \0" + /* 2270 */ "brz \0" + /* 2275 */ "movrz \0" + /* 2282 */ "fmovrsz \0" + /* 2291 */ "; SELECT_CC_DFP_FCC PSEUDO!\0" + /* 2319 */ "; SELECT_CC_QFP_FCC PSEUDO!\0" + /* 2347 */ "; SELECT_CC_FP_FCC PSEUDO!\0" + /* 2374 */ "; SELECT_CC_Int_FCC PSEUDO!\0" + /* 2402 */ "; SELECT_CC_DFP_ICC PSEUDO!\0" + /* 2430 */ "; SELECT_CC_QFP_ICC PSEUDO!\0" + /* 2458 */ "; SELECT_CC_FP_ICC PSEUDO!\0" + /* 2485 */ "; SELECT_CC_Int_ICC PSEUDO!\0" + /* 2513 */ "jmp %i7+\0" + /* 2522 */ "jmp %o7+\0" + /* 2531 */ "# XRay Function Patchable RET.\0" + /* 2562 */ "# XRay Typed Event Log.\0" + /* 2586 */ "# XRay Custom Event Log.\0" + /* 2611 */ "# XRay Function Enter.\0" + /* 2634 */ "# XRay Tail Call Exit.\0" + /* 2657 */ "# XRay Function Exit.\0" + /* 2679 */ "flush %g0\0" + /* 2689 */ "ta 1\0" + /* 2694 */ "ta 3\0" + /* 2699 */ "ta 5\0" + /* 2704 */ "LIFETIME_END\0" + /* 2717 */ "PSEUDO_PROBE\0" + /* 2730 */ "BUNDLE\0" + /* 2737 */ "DBG_VALUE\0" + /* 2747 */ "DBG_INSTR_REF\0" + /* 2761 */ "DBG_PHI\0" + /* 2769 */ "DBG_LABEL\0" + /* 2779 */ "LIFETIME_START\0" + /* 2794 */ "DBG_VALUE_LIST\0" + /* 2809 */ "std %cq, [\0" + /* 2820 */ "std %fq, [\0" + /* 2831 */ "st %csr, [\0" + /* 2842 */ "st %fsr, [\0" + /* 2853 */ "stx %fsr, [\0" + /* 2865 */ "ldsba [\0" + /* 2873 */ "lduba [\0" + /* 2881 */ "ldstuba [\0" + /* 2891 */ "ldda [\0" + /* 2898 */ "lda [\0" + /* 2904 */ "ldsha [\0" + /* 2912 */ "lduha [\0" + /* 2920 */ "swapa [\0" + /* 2928 */ "ldqa [\0" + /* 2935 */ "casa [\0" + /* 2942 */ "ldsb [\0" + /* 2949 */ "ldub [\0" + /* 2956 */ "ldstub [\0" + /* 2965 */ "ldd [\0" + /* 2971 */ "ld [\0" + /* 2976 */ "prefetch [\0" + /* 2987 */ "ldsh [\0" + /* 2994 */ "lduh [\0" + /* 3001 */ "swap [\0" + /* 3008 */ "ldq [\0" + /* 3014 */ "cas [\0" + /* 3020 */ "ldsw [\0" + /* 3027 */ "ldx [\0" + /* 3033 */ "casx [\0" + /* 3040 */ "cb\0" + /* 3043 */ "fb\0" + /* 3046 */ "fmovd\0" + /* 3052 */ "# FEntry call\0" + /* 3066 */ "siam\0" + /* 3071 */ "shutdown\0" + /* 3080 */ "nop\0" + /* 3084 */ "fmovq\0" + /* 3090 */ "stbar\0" + /* 3096 */ "fmovs\0" + /* 3102 */ "t\0" + /* 3104 */ "mov\0" + /* 3108 */ "flushw\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 2738U, // DBG_VALUE + 2795U, // DBG_VALUE_LIST + 2748U, // DBG_INSTR_REF + 2762U, // DBG_PHI + 2770U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 2731U, // BUNDLE + 2780U, // LIFETIME_START + 2705U, // LIFETIME_END + 2718U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 3053U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 2612U, // PATCHABLE_FUNCTION_ENTER + 2532U, // PATCHABLE_RET + 2658U, // PATCHABLE_FUNCTION_EXIT + 2635U, // PATCHABLE_TAIL_CALL + 2587U, // PATCHABLE_EVENT_CALL + 2563U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 4565U, // ADJCALLSTACKDOWN + 70120U, // ADJCALLSTACKUP + 8201U, // GETPCX + 2292U, // SELECT_CC_DFP_FCC + 2403U, // SELECT_CC_DFP_ICC + 2348U, // SELECT_CC_FP_FCC + 2459U, // SELECT_CC_FP_ICC + 2375U, // SELECT_CC_Int_FCC + 2486U, // SELECT_CC_Int_ICC + 2320U, // SELECT_CC_QFP_FCC + 2431U, // SELECT_CC_QFP_ICC + 2111278U, // SET + 20984468U, // ADDCCri + 20984468U, // ADDCCrr + 20985747U, // ADDCri + 20985747U, // ADDCrr + 20984560U, // ADDEri + 20984560U, // ADDErr + 20984574U, // ADDXC + 20984458U, // ADDXCCC + 20984596U, // ADDXri + 20984596U, // ADDXrr + 20984596U, // ADDri + 20984596U, // ADDrr + 20985296U, // ALIGNADDR + 20984926U, // ALIGNADDRL + 20984475U, // ANDCCri + 20984475U, // ANDCCrr + 20984498U, // ANDNCCri + 20984498U, // ANDNCCrr + 20984981U, // ANDNri + 20984981U, // ANDNrr + 20984981U, // ANDXNrr + 20984664U, // ANDXri + 20984664U, // ANDXrr + 20984664U, // ANDri + 20984664U, // ANDrr + 20984245U, // ARRAY16 + 20983998U, // ARRAY32 + 20984269U, // ARRAY8 + 70208U, // BA + 2247650U, // BCOND + 2313186U, // BCONDA + 87378U, // BINDri + 87378U, // BINDrr + 20984864U, // BMASK + 21122020U, // BPFCC + 21187556U, // BPFCCA + 281572U, // BPFCCANT + 347108U, // BPFCCNT + 5304U, // BPGEZapn + 4621U, // BPGEZapt + 5371U, // BPGEZnapn + 6150U, // BPGEZnapt + 5328U, // BPGZapn + 4639U, // BPGZapt + 5391U, // BPGZnapn + 6246U, // BPGZnapt + 2509794U, // BPICC + 478178U, // BPICCA + 543714U, // BPICCANT + 609250U, // BPICCNT + 5316U, // BPLEZapn + 4630U, // BPLEZapt + 5381U, // BPLEZnapn + 6199U, // BPLEZnapt + 5339U, // BPLZapn + 4647U, // BPLZapt + 5400U, // BPLZnapn + 6290U, // BPLZnapt + 5350U, // BPNZapn + 4655U, // BPNZapt + 5409U, // BPNZnapn + 6334U, // BPNZnapt + 2771938U, // BPXCC + 740322U, // BPXCCA + 805858U, // BPXCCANT + 871394U, // BPXCCNT + 5361U, // BPZapn + 4663U, // BPZapt + 5418U, // BPZnapn + 6367U, // BPZnapt + 20984775U, // BSHUFFLE + 70733U, // CALL + 87117U, // CALLri + 87117U, // CALLrr + 932728U, // CASAasi10 + 7289720U, // CASArr + 22035418U, // CASXrr + 22035399U, // CASrr + 2247649U, // CBCOND + 2313185U, // CBCONDA + 69936U, // CMASK16 + 69768U, // CMASK32 + 70085U, // CMASK8 + 5446U, // CMPri + 5446U, // CMPrr + 20984075U, // EDGE16 + 20984880U, // EDGE16L + 20984997U, // EDGE16LN + 20984964U, // EDGE16N + 20983907U, // EDGE32 + 20984871U, // EDGE32L + 20984987U, // EDGE32LN + 20984955U, // EDGE32N + 20984254U, // EDGE8 + 20984889U, // EDGE8L + 20985007U, // EDGE8LN + 20984973U, // EDGE8N + 2110364U, // FABSD + 2110886U, // FABSQ + 2111249U, // FABSS + 20984601U, // FADDD + 20985182U, // FADDQ + 20985462U, // FADDS + 20984411U, // FALIGNADATA + 20984663U, // FAND + 20983855U, // FANDNOT1 + 20985361U, // FANDNOT1S + 20984014U, // FANDNOT2 + 20985408U, // FANDNOT2S + 20985494U, // FANDS + 2247652U, // FBCOND + 2313188U, // FBCONDA + 20984137U, // FCHKSM16 + 5001U, // FCMPD + 20984156U, // FCMPEQ16 + 20983969U, // FCMPEQ32 + 20984175U, // FCMPGT16 + 20983988U, // FCMPGT32 + 20984083U, // FCMPLE16 + 20983915U, // FCMPLE32 + 20984093U, // FCMPNE16 + 20983925U, // FCMPNE32 + 5535U, // FCMPQ + 5862U, // FCMPS + 20984752U, // FDIVD + 20985274U, // FDIVQ + 20985632U, // FDIVS + 20985204U, // FDMULQ + 2110475U, // FDTOI + 2110851U, // FDTOQ + 2111178U, // FDTOS + 2111414U, // FDTOX + 2110308U, // FEXPAND + 20984608U, // FHADDD + 20985469U, // FHADDS + 20984588U, // FHSUBD + 20985454U, // FHSUBS + 2110317U, // FITOD + 2110858U, // FITOQ + 2111185U, // FITOS + 150999952U, // FLCMPD + 151000813U, // FLCMPS + 2680U, // FLUSH + 3109U, // FLUSHW + 87014U, // FLUSHri + 87014U, // FLUSHrr + 20984147U, // FMEAN16 + 2110391U, // FMOVD + 1141735U, // FMOVD_FCC + 17198055U, // FMOVD_ICC + 17460199U, // FMOVD_XCC + 2110913U, // FMOVQ + 1141773U, // FMOVQ_FCC + 17198093U, // FMOVQ_ICC + 17460237U, // FMOVQ_XCC + 20985840U, // FMOVRGEZD + 20985851U, // FMOVRGEZQ + 20985878U, // FMOVRGEZS + 20985938U, // FMOVRGZD + 20985948U, // FMOVRGZQ + 20985972U, // FMOVRGZS + 20985889U, // FMOVRLEZD + 20985900U, // FMOVRLEZQ + 20985927U, // FMOVRLEZS + 20985982U, // FMOVRLZD + 20985992U, // FMOVRLZQ + 20986016U, // FMOVRLZS + 20986026U, // FMOVRNZD + 20986036U, // FMOVRNZQ + 20986060U, // FMOVRNZS + 20985831U, // FMOVRZD + 20986070U, // FMOVRZQ + 20986091U, // FMOVRZS + 2111271U, // FMOVS + 1141785U, // FMOVS_FCC + 17198105U, // FMOVS_ICC + 17460249U, // FMOVS_XCC + 20984233U, // FMUL8SUX16 + 20984208U, // FMUL8ULX16 + 20984185U, // FMUL8X16 + 20984897U, // FMUL8X16AL + 20985671U, // FMUL8X16AU + 20984648U, // FMULD + 20984220U, // FMULD8SUX16 + 20984195U, // FMULD8ULX16 + 20985212U, // FMULQ + 20985531U, // FMULS + 20984625U, // FNADDD + 20985486U, // FNADDS + 20984669U, // FNAND + 20985501U, // FNANDS + 2110273U, // FNEGD + 2110829U, // FNEGQ + 2111156U, // FNEGS + 20984616U, // FNHADDD + 20985477U, // FNHADDS + 20984616U, // FNMULD + 20985477U, // FNMULS + 20985317U, // FNOR + 20985595U, // FNORS + 2109497U, // FNOT1 + 2111004U, // FNOT1S + 2109656U, // FNOT2 + 2111051U, // FNOT2S + 20985477U, // FNSMULD + 70609U, // FONE + 71333U, // FONES + 20985312U, // FOR + 20983872U, // FORNOT1 + 20985380U, // FORNOT1S + 20984031U, // FORNOT2 + 20985427U, // FORNOT2S + 20985589U, // FORS + 2109735U, // FPACK16 + 20983935U, // FPACK32 + 2111385U, // FPACKFIX + 20984066U, // FPADD16 + 20985437U, // FPADD16S + 20983898U, // FPADD32 + 20985390U, // FPADD32S + 20984040U, // FPADD64 + 20984766U, // FPMERGE + 20984057U, // FPSUB16 + 20984323U, // FPSUB16S + 20983889U, // FPSUB32 + 20984313U, // FPSUB32S + 2110324U, // FQTOD + 2110482U, // FQTOI + 2111192U, // FQTOS + 2111430U, // FQTOX + 20984166U, // FSLAS16 + 20983979U, // FSLAS32 + 20984121U, // FSLL16 + 20983953U, // FSLL32 + 20984655U, // FSMULD + 2110371U, // FSQRTD + 2110893U, // FSQRTQ + 2111256U, // FSQRTS + 20984049U, // FSRA16 + 20983881U, // FSRA32 + 2109480U, // FSRC1 + 2110985U, // FSRC1S + 2109639U, // FSRC2 + 2111032U, // FSRC2S + 20984129U, // FSRL16 + 20983961U, // FSRL32 + 2110331U, // FSTOD + 2110489U, // FSTOI + 2110865U, // FSTOQ + 2111437U, // FSTOX + 20984581U, // FSUBD + 20985175U, // FSUBQ + 20985447U, // FSUBS + 20985323U, // FXNOR + 20985602U, // FXNORS + 20985330U, // FXOR + 20985610U, // FXORS + 2110338U, // FXTOD + 2110872U, // FXTOQ + 2111199U, // FXTOS + 70975U, // FZERO + 71362U, // FZEROS + 2126936U, // JMPLri + 2126936U, // JMPLrr + 26180435U, // LDArr + 1203100U, // LDCSRri + 1203100U, // LDCSRrr + 3177372U, // LDCri + 3177372U, // LDCrr + 26180428U, // LDDArr + 3177366U, // LDDCri + 3177366U, // LDDCrr + 26180428U, // LDDFArr + 3177366U, // LDDFri + 3177366U, // LDDFrr + 3177366U, // LDDri + 3177366U, // LDDrr + 26180435U, // LDFArr + 1268636U, // LDFSRri + 1268636U, // LDFSRrr + 3177372U, // LDFri + 3177372U, // LDFrr + 26180465U, // LDQFArr + 3177409U, // LDQFri + 3177409U, // LDQFrr + 26180402U, // LDSBArr + 3177343U, // LDSBri + 3177343U, // LDSBrr + 26180441U, // LDSHArr + 3177388U, // LDSHri + 3177388U, // LDSHrr + 26180418U, // LDSTUBArr + 3177357U, // LDSTUBri + 3177357U, // LDSTUBrr + 3177421U, // LDSWri + 3177421U, // LDSWrr + 26180410U, // LDUBArr + 3177350U, // LDUBri + 3177350U, // LDUBrr + 26180449U, // LDUHArr + 3177395U, // LDUHri + 3177395U, // LDUHrr + 1268692U, // LDXFSRri + 1268692U, // LDXFSRrr + 3177428U, // LDXri + 3177428U, // LDXrr + 3177372U, // LDri + 3177372U, // LDrr + 33556U, // LEAX_ADDri + 33556U, // LEA_ADDri + 2111283U, // LZCNT + 38344U, // MEMBARi + 2111421U, // MOVDTOX + 1141793U, // MOVFCCri + 1141793U, // MOVFCCrr + 17198113U, // MOVICCri + 17198113U, // MOVICCrr + 20985869U, // MOVRGEZri + 20985869U, // MOVRGEZrr + 20985964U, // MOVRGZri + 20985964U, // MOVRGZrr + 20985918U, // MOVRLEZri + 20985918U, // MOVRLEZrr + 20986008U, // MOVRLZri + 20986008U, // MOVRLZrr + 20986052U, // MOVRNZri + 20986052U, // MOVRNZrr + 20986084U, // MOVRRZri + 20986084U, // MOVRRZrr + 2111347U, // MOVSTOSW + 2111357U, // MOVSTOUW + 2111421U, // MOVWTOS + 17460257U, // MOVXCCri + 17460257U, // MOVXCCrr + 2111421U, // MOVXTOD + 20984528U, // MULSCCri + 20984528U, // MULSCCrr + 20985776U, // MULXri + 20985776U, // MULXrr + 3081U, // NOP + 20984515U, // ORCCri + 20984515U, // ORCCrr + 20984506U, // ORNCCri + 20984506U, // ORNCCrr + 20985138U, // ORNri + 20985138U, // ORNrr + 20985138U, // ORXNrr + 20985313U, // ORXri + 20985313U, // ORXrr + 20985313U, // ORri + 20985313U, // ORrr + 20985658U, // PDIST + 20985143U, // PDISTN + 2110200U, // POPCrr + 5266337U, // PREFETCHi + 5266337U, // PREFETCHr + 33560068U, // PWRPSRri + 33560068U, // PWRPSRrr + 2110360U, // RDASR + 69633U, // RDPC + 2110968U, // RDPR + 69662U, // RDPSR + 69652U, // RDTBR + 69642U, // RDWIM + 20984791U, // RESTOREri + 20984791U, // RESTORErr + 72146U, // RET + 72155U, // RETL + 87873U, // RETTri + 87873U, // RETTrr + 20984800U, // SAVEri + 20984800U, // SAVErr + 20984536U, // SDIVCCri + 20984536U, // SDIVCCrr + 20985817U, // SDIVXri + 20985817U, // SDIVXrr + 20985683U, // SDIVri + 20985683U, // SDIVrr + 2110450U, // SETHIXi + 2110450U, // SETHIi + 3072U, // SHUTDOWN + 3067U, // SIAM + 71131U, // SIR + 20985763U, // SLLXri + 20985763U, // SLLXrr + 20984915U, // SLLri + 20984915U, // SLLrr + 20984438U, // SMACri + 20984438U, // SMACrr + 20984482U, // SMULCCri + 20984482U, // SMULCCrr + 20984943U, // SMULri + 20984943U, // SMULrr + 20985735U, // SRAXri + 20985735U, // SRAXrr + 20984406U, // SRAri + 20984406U, // SRArr + 20985769U, // SRLXri + 20985769U, // SRLXrr + 20984938U, // SRLri + 20984938U, // SRLrr + 9413223U, // STArr + 3091U, // STBAR + 9413182U, // STBArr + 1352300U, // STBri + 1352300U, // STBrr + 1334032U, // STCSRri + 1334032U, // STCSRrr + 1353533U, // STCri + 1353533U, // STCrr + 9413188U, // STDArr + 1334010U, // STDCQri + 1334010U, // STDCQrr + 1352619U, // STDCri + 1352619U, // STDCrr + 9413188U, // STDFArr + 1334021U, // STDFQri + 1334021U, // STDFQrr + 1352619U, // STDFri + 1352619U, // STDFrr + 1352619U, // STDri + 1352619U, // STDrr + 9413223U, // STFArr + 1334043U, // STFSRri + 1334043U, // STFSRrr + 1353533U, // STFri + 1353533U, // STFrr + 9413194U, // STHArr + 1352685U, // STHri + 1352685U, // STHrr + 9413200U, // STQFArr + 1353141U, // STQFri + 1353141U, // STQFrr + 1334054U, // STXFSRri + 1334054U, // STXFSRrr + 1353684U, // STXri + 1353684U, // STXrr + 1353533U, // STri + 1353533U, // STrr + 20984451U, // SUBCCri + 20984451U, // SUBCCrr + 20985741U, // SUBCri + 20985741U, // SUBCrr + 20984552U, // SUBEri + 20984552U, // SUBErr + 20984433U, // SUBXri + 20984433U, // SUBXrr + 20984433U, // SUBri + 20984433U, // SUBrr + 26180457U, // SWAPArr + 3177402U, // SWAPri + 3177402U, // SWAPrr + 2690U, // TA1 + 2695U, // TA3 + 2700U, // TA5 + 20985705U, // TADDCCTVri + 20985705U, // TADDCCTVrr + 20984467U, // TADDCCri + 20984467U, // TADDCCrr + 52870175U, // TICCri + 52870175U, // TICCrr + 557855508U, // TLS_ADDXrr + 557855508U, // TLS_ADDrr + 5197U, // TLS_CALL + 288390100U, // TLS_LDXrr + 288390044U, // TLS_LDrr + 52608031U, // TRAPri + 52608031U, // TRAPrr + 20985695U, // TSUBCCTVri + 20985695U, // TSUBCCTVrr + 20984450U, // TSUBCCri + 20984450U, // TSUBCCrr + 53132319U, // TXCCri + 53132319U, // TXCCrr + 20984544U, // UDIVCCri + 20984544U, // UDIVCCrr + 20985824U, // UDIVXri + 20985824U, // UDIVXrr + 20985689U, // UDIVri + 20985689U, // UDIVrr + 20984444U, // UMACri + 20984444U, // UMACrr + 20984490U, // UMULCCri + 20984490U, // UMULCCrr + 20984825U, // UMULXHI + 20984949U, // UMULri + 20984949U, // UMULrr + 70987U, // UNIMP + 150999945U, // V9FCMPD + 150999865U, // V9FCMPED + 151000421U, // V9FCMPEQ + 151000748U, // V9FCMPES + 151000479U, // V9FCMPQ + 151000806U, // V9FCMPS + 52199U, // V9FMOVD_FCC + 52237U, // V9FMOVQ_FCC + 52249U, // V9FMOVS_FCC + 52257U, // V9MOVFCCri + 52257U, // V9MOVFCCrr + 20985349U, // WRASRri + 20985349U, // WRASRrr + 20985342U, // WRPRri + 20985342U, // WRPRrr + 33560069U, // WRPSRri + 33560069U, // WRPSRrr + 67114501U, // WRTBRri + 67114501U, // WRTBRrr + 83891717U, // WRWIMri + 83891717U, // WRWIMrr + 20985775U, // XMULX + 20984834U, // XMULXHI + 20984513U, // XNORCCri + 20984513U, // XNORCCrr + 20985324U, // XNORXrr + 20985324U, // XNORri + 20985324U, // XNORrr + 20984521U, // XORCCri + 20984521U, // XORCCrr + 20985331U, // XORXri + 20985331U, // XORXrr + 20985331U, // XORri + 20985331U, // XORrr + }; + + // Emit the opcode for the instruction. + uint32_t Bits = 0; + Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; + return createMnemonic(AsmStrs + (Bits & 4095) - 1, Bits); +} +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) { + MCMnemonic MnemonicInfo = Sparc_getMnemonic(MI); + +#ifndef CAPSTONE_DIET + + SStream_concat0(O, MnemonicInfo.first); +#endif + + uint32_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 4 bits for 13 unique commands. + switch ((Bits >> 12) & 15) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 2: + // GETPCX + printGetPCX /* printGetPCX (+ ) */ (MI, 0, O); + return; + break; + case 3: + // SET, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC,... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 4: + // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA... + printCCOperand /* printCCOperand (+ ) */ (MI, 1, O); + break; + case 5: + // BINDri, BINDrr, CALLri, CALLrr, FLUSHri, FLUSHrr, LDCSRri, LDCSRrr, LD... + printMemOperand /* printMemOperand (+ ) */ (MI, 0, O, ""); + break; + case 6: + // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV... + printCCOperand /* printCCOperand (+ ) */ (MI, 3, O); + break; + case 7: + // JMPLri, JMPLrr, LDArr, LDCri, LDCrr, LDDArr, LDDCri, LDDCrr, LDDFArr, ... + printMemOperand /* printMemOperand (+ ) */ (MI, 1, O, ""); + break; + case 8: + // LEAX_ADDri, LEA_ADDri + printMemOperand /* printMemOperand (+ arith) */ (MI, 1, O, "arith"); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 9: + // MEMBARi + printMembarTag /* printMembarTag (+ ) */ (MI, 0, O); + return; + break; + case 10: + // STArr, STBArr, STBri, STBrr, STCri, STCrr, STDArr, STDCri, STDCrr, STD... + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", ["); + printMemOperand /* printMemOperand (+ ) */ (MI, 0, O, ""); + break; + case 11: + // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr + printCCOperand /* printCCOperand (+ ) */ (MI, 2, O); + break; + case 12: + // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr + printCCOperand /* printCCOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, " "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + } + + // Fragment 1 encoded into 5 bits for 21 unique commands. + switch ((Bits >> 16) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADJCALLSTACKDOWN, SET, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDEr... + SStream_concat0(O, ", "); + break; + case 1: + // ADJCALLSTACKUP, BA, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMA... + return; + break; + case 2: + // BCOND, BPFCC, CBCOND, FBCOND, TRAPri, TRAPrr + SStream_concat0(O, " "); + break; + case 3: + // BCONDA, BPFCCA, CBCONDA, FBCONDA + SStream_concat0(O, ",a "); + break; + case 4: + // BPFCCANT + SStream_concat0(O, ",a,pn "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 5: + // BPFCCNT + SStream_concat0(O, ",pn "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 6: + // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI... + SStream_concat0(O, " %icc, "); + break; + case 7: + // BPICCA + SStream_concat0(O, ",a %icc, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 8: + // BPICCANT + SStream_concat0(O, ",a,pn %icc, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 9: + // BPICCNT + SStream_concat0(O, ",pn %icc, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 10: + // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX... + SStream_concat0(O, " %xcc, "); + break; + case 11: + // BPXCCA + SStream_concat0(O, ",a %xcc, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 12: + // BPXCCANT + SStream_concat0(O, ",a,pn %xcc, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 13: + // BPXCCNT + SStream_concat0(O, ",pn %xcc, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 14: + // CASAasi10 + SStream_concat0(O, "] 10, "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 15: + // CASArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDS... + SStream_concat0(O, "] "); + break; + case 16: + // CASXrr, CASrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, LDDri, LD... + SStream_concat0(O, "], "); + break; + case 17: + // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr + SStream_concat0(O, " %fcc0, "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 18: + // LDCSRri, LDCSRrr + SStream_concat0(O, "], %csr"); + return; + break; + case 19: + // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr + SStream_concat0(O, "], %fsr"); + return; + break; + case 20: + // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri... + SStream_concat0(O, "]"); + return; + break; + } + + // Fragment 2 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 21) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADJCALLSTACKDOWN, BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, B... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 1: + // SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, FABSD, FABSQ, FABSS... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 2: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 3: + // CASArr + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 4: + // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + } + + // Fragment 3 encoded into 3 bits for 6 unique commands. + switch ((Bits >> 24) & 7) { + default: + llvm_unreachable("Invalid command number."); case 0: - return getbool(Bits & Sparc_FeatureV9); + // ADJCALLSTACKDOWN, SET, BCOND, BCONDA, BPGEZapn, BPGEZapt, BPGEZnapn, B... + return; + break; case 1: - return getbool(Bits & Sparc_FeatureVIS3); + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + SStream_concat0(O, ", "); + break; case 2: - return getbool(Bits & Sparc_FeatureVIS); + // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr + SStream_concat0(O, ", %psr"); + return; + break; case 3: - return getbool(Bits & Sparc_FeatureVIS2); + // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr + SStream_concat0(O, " + "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 4: + // WRTBRri, WRTBRrr + SStream_concat0(O, ", %tbr"); + return; + break; + case 5: + // WRWIMri, WRWIMrr + SStream_concat0(O, ", %wim"); + return; + break; + } + + // Fragment 4 encoded into 2 bits for 3 unique commands. + switch ((Bits >> 27) & 3) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 1: + // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP... + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 2: + // TLS_LDXrr, TLS_LDrr + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + } + + // Fragment 5 encoded into 1 bits for 2 unique commands. + if ((Bits >> 29) & 1) { + // TLS_ADDXrr, TLS_ADDrr + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + } else { + // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... + return; } } -#define DecodeToMCInst(fname,fieldname, InsnType) \ -static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, const void *Decoder) \ -{ \ - InsnType tmp; \ - switch (Idx) { \ - default: \ - case 0: \ - tmp = fieldname(insn, 0, 22); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 1: \ - tmp = fieldname(insn, 0, 19); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 25, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 2: \ - tmp = fieldname(insn, 0, 22); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 25, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 3: \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 14) << 0; \ - tmp |= fieldname(insn, 20, 2) << 14; \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 4: \ - return S; \ - case 5: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 22); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 6: \ - tmp = fieldname(insn, 0, 19); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 25, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 20, 2); \ - if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 7: \ - tmp = fieldname(insn, 0, 30); \ - if (DecodeCall(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 8: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 9: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 13); \ - if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 10: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 11: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 13); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 12: \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 13: \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 13); \ - if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 14: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 15: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 16: \ - tmp = fieldname(insn, 0, 13); \ - if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 17: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 18: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 19: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 11); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 20: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 11); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 21: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 22: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 23: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 24: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 25: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 26: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 27: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 28: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 29: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 30: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 31: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 32: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 33: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 34: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 35: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 36: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 37: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 38: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 39: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 40: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 41: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 42: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 2); \ - if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 43: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 44: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 45: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 46: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 47: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 48: \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 49: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 50: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 51: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 52: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 53: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 54: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 55: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 56: \ - if (DecodeJMPL(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 57: \ - if (DecodeReturn(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 58: \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 59: \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 8); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 25, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 60: \ - if (DecodeLoadInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 61: \ - if (DecodeStoreInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 62: \ - if (DecodeSWAP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 63: \ - if (DecodeLoadFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 64: \ - if (DecodeLoadQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 65: \ - if (DecodeLoadDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 66: \ - if (DecodeStoreFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 67: \ - if (DecodeStoreQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 68: \ - if (DecodeStoreDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 69: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 70: \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 25, 5); \ - if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - } \ +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo) { + assert(RegNo && RegNo < 237 && "Invalid register number!"); + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = {/* 0 */ "C10\0" + /* 4 */ "F10\0" + /* 8 */ "ASR10\0" + /* 14 */ "C20\0" + /* 18 */ "F20\0" + /* 22 */ "ASR20\0" + /* 28 */ "C30\0" + /* 32 */ "F30\0" + /* 36 */ "ASR30\0" + /* 42 */ "F40\0" + /* 46 */ "F50\0" + /* 50 */ "F60\0" + /* 54 */ "FCC0\0" + /* 59 */ "F0\0" + /* 62 */ "G0\0" + /* 65 */ "I0\0" + /* 68 */ "L0\0" + /* 71 */ "O0\0" + /* 74 */ "C11\0" + /* 78 */ "F11\0" + /* 82 */ "ASR11\0" + /* 88 */ "C21\0" + /* 92 */ "F21\0" + /* 96 */ "ASR21\0" + /* 102 */ "C31\0" + /* 106 */ "F31\0" + /* 110 */ "ASR31\0" + /* 116 */ "FCC1\0" + /* 121 */ "F1\0" + /* 124 */ "G1\0" + /* 127 */ "I1\0" + /* 130 */ "L1\0" + /* 133 */ "O1\0" + /* 136 */ "ASR1\0" + /* 141 */ "C12\0" + /* 145 */ "F12\0" + /* 149 */ "ASR12\0" + /* 155 */ "C22\0" + /* 159 */ "F22\0" + /* 163 */ "ASR22\0" + /* 169 */ "F32\0" + /* 173 */ "F42\0" + /* 177 */ "F52\0" + /* 181 */ "F62\0" + /* 185 */ "FCC2\0" + /* 190 */ "F2\0" + /* 193 */ "G2\0" + /* 196 */ "I2\0" + /* 199 */ "L2\0" + /* 202 */ "O2\0" + /* 205 */ "ASR2\0" + /* 210 */ "C13\0" + /* 214 */ "F13\0" + /* 218 */ "ASR13\0" + /* 224 */ "C23\0" + /* 228 */ "F23\0" + /* 232 */ "ASR23\0" + /* 238 */ "FCC3\0" + /* 243 */ "F3\0" + /* 246 */ "G3\0" + /* 249 */ "I3\0" + /* 252 */ "L3\0" + /* 255 */ "O3\0" + /* 258 */ "ASR3\0" + /* 263 */ "C14\0" + /* 267 */ "F14\0" + /* 271 */ "ASR14\0" + /* 277 */ "C24\0" + /* 281 */ "F24\0" + /* 285 */ "ASR24\0" + /* 291 */ "F34\0" + /* 295 */ "F44\0" + /* 299 */ "F54\0" + /* 303 */ "C4\0" + /* 306 */ "F4\0" + /* 309 */ "G4\0" + /* 312 */ "I4\0" + /* 315 */ "L4\0" + /* 318 */ "O4\0" + /* 321 */ "ASR4\0" + /* 326 */ "C15\0" + /* 330 */ "F15\0" + /* 334 */ "ASR15\0" + /* 340 */ "C25\0" + /* 344 */ "F25\0" + /* 348 */ "ASR25\0" + /* 354 */ "C5\0" + /* 357 */ "F5\0" + /* 360 */ "G5\0" + /* 363 */ "I5\0" + /* 366 */ "L5\0" + /* 369 */ "O5\0" + /* 372 */ "ASR5\0" + /* 377 */ "C16\0" + /* 381 */ "F16\0" + /* 385 */ "ASR16\0" + /* 391 */ "C26\0" + /* 395 */ "F26\0" + /* 399 */ "ASR26\0" + /* 405 */ "F36\0" + /* 409 */ "F46\0" + /* 413 */ "F56\0" + /* 417 */ "C6\0" + /* 420 */ "F6\0" + /* 423 */ "G6\0" + /* 426 */ "I6\0" + /* 429 */ "L6\0" + /* 432 */ "O6\0" + /* 435 */ "ASR6\0" + /* 440 */ "C17\0" + /* 444 */ "F17\0" + /* 448 */ "ASR17\0" + /* 454 */ "C27\0" + /* 458 */ "F27\0" + /* 462 */ "ASR27\0" + /* 468 */ "C7\0" + /* 471 */ "F7\0" + /* 474 */ "G7\0" + /* 477 */ "I7\0" + /* 480 */ "L7\0" + /* 483 */ "O7\0" + /* 486 */ "ASR7\0" + /* 491 */ "C18\0" + /* 495 */ "F18\0" + /* 499 */ "ASR18\0" + /* 505 */ "C28\0" + /* 509 */ "F28\0" + /* 513 */ "ASR28\0" + /* 519 */ "F38\0" + /* 523 */ "F48\0" + /* 527 */ "F58\0" + /* 531 */ "C8\0" + /* 534 */ "F8\0" + /* 537 */ "ASR8\0" + /* 542 */ "C19\0" + /* 546 */ "F19\0" + /* 550 */ "ASR19\0" + /* 556 */ "C29\0" + /* 560 */ "F29\0" + /* 564 */ "ASR29\0" + /* 570 */ "C9\0" + /* 573 */ "F9\0" + /* 576 */ "ASR9\0" + /* 581 */ "TBA\0" + /* 585 */ "ICC\0" + /* 589 */ "TNPC\0" + /* 594 */ "TPC\0" + /* 598 */ "CANRESTORE\0" + /* 609 */ "PSTATE\0" + /* 616 */ "TSTATE\0" + /* 623 */ "WSTATE\0" + /* 630 */ "CANSAVE\0" + /* 638 */ "TICK\0" + /* 643 */ "PIL\0" + /* 647 */ "TL\0" + /* 650 */ "WIM\0" + /* 654 */ "CLEANWIN\0" + /* 663 */ "OTHERWIN\0" + /* 672 */ "FP\0" + /* 675 */ "SP\0" + /* 678 */ "CWP\0" + /* 682 */ "FQ\0" + /* 685 */ "CPQ\0" + /* 689 */ "TBR\0" + /* 693 */ "FSR\0" + /* 697 */ "CPSR\0" + /* 702 */ "TT\0" + /* 705 */ "Y\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint16_t RegAsmOffset[] = { + 598, 630, 654, 685, 697, 678, 682, 693, 585, 663, 591, 643, 698, 609, 581, + 689, 638, 647, 589, 594, 616, 702, 650, 623, 705, 136, 205, 258, 321, 372, + 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385, 448, 499, 550, 22, + 96, 163, 232, 285, 348, 399, 462, 513, 564, 36, 110, 56, 118, 187, 240, + 303, 354, 417, 468, 531, 570, 0, 74, 141, 210, 263, 326, 377, 440, 491, + 542, 14, 88, 155, 224, 277, 340, 391, 454, 505, 556, 28, 102, 59, 190, + 306, 420, 534, 4, 145, 267, 381, 495, 18, 159, 281, 395, 509, 32, 169, + 291, 405, 519, 42, 173, 295, 409, 523, 46, 177, 299, 413, 527, 50, 181, + 59, 121, 190, 243, 306, 357, 420, 471, 534, 573, 4, 78, 145, 214, 267, + 330, 381, 444, 495, 546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, + 32, 106, 54, 116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, + 127, 196, 249, 312, 363, 672, 477, 68, 130, 199, 252, 315, 366, 429, 480, + 71, 133, 202, 255, 318, 369, 675, 483, 59, 306, 534, 145, 381, 18, 281, + 509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531, 0, + 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309, 423, 65, + 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432, + }; + + assert(*(AsmStrs + RegAsmOffset[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrs + RegAsmOffset[RegNo - 1]; } +#endif +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +static char *printAliasInstr(MCInst *MI, SStream *OS) { + static const PatternsForOpcode OpToPatterns[] = { + {SP_BCOND, 0, 16}, {SP_BCONDA, 16, 16}, + {SP_BPFCCANT, 32, 16}, {SP_BPFCCNT, 48, 16}, + {SP_BPICCANT, 64, 16}, {SP_BPICCNT, 80, 16}, + {SP_BPXCCANT, 96, 16}, {SP_BPXCCNT, 112, 16}, + {SP_FMOVD_ICC, 128, 16}, {SP_FMOVD_XCC, 144, 16}, + {SP_FMOVQ_ICC, 160, 16}, {SP_FMOVQ_XCC, 176, 16}, + {SP_FMOVS_ICC, 192, 16}, {SP_FMOVS_XCC, 208, 16}, + {SP_MOVICCri, 224, 16}, {SP_MOVICCrr, 240, 16}, + {SP_MOVXCCri, 256, 16}, {SP_MOVXCCrr, 272, 16}, + {SP_ORCCrr, 288, 1}, {SP_ORri, 289, 1}, + {SP_ORrr, 290, 1}, {SP_RESTORErr, 291, 1}, + {SP_RET, 292, 1}, {SP_RETL, 293, 1}, + {SP_SAVErr, 294, 1}, {SP_TICCri, 295, 32}, + {SP_TICCrr, 327, 32}, {SP_TRAPri, 359, 32}, + {SP_TRAPrr, 391, 32}, {SP_TXCCri, 423, 32}, + {SP_TXCCrr, 455, 32}, {SP_V9FCMPD, 487, 1}, + {SP_V9FCMPED, 488, 1}, {SP_V9FCMPEQ, 489, 1}, + {SP_V9FCMPES, 490, 1}, {SP_V9FCMPQ, 491, 1}, + {SP_V9FCMPS, 492, 1}, {SP_V9FMOVD_FCC, 493, 16}, + {SP_V9FMOVQ_FCC, 509, 16}, {SP_V9FMOVS_FCC, 525, 16}, + {SP_V9MOVFCCri, 541, 16}, {SP_V9MOVFCCrr, 557, 16}, + }; -#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ -{ \ - uint64_t Bits = getFeatureBits(feature); \ - const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0, ExpectedValue; \ - DecodeStatus S = MCDisassembler_Success; \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail; \ - for (;;) { \ - switch (*Ptr) { \ - default: \ - return MCDisassembler_Fail; \ - case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - ++Ptr; \ - CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ - break; \ - } \ - case MCD_OPC_FilterValue: { \ - Val = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (Val != CurFieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (ExpectedValue != FieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckPredicate: { \ - PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - Pred = checkDecoderPredicate(PIdx, Bits); \ - if (!Pred) \ - Ptr += NumToSkip; \ - (void)Pred; \ - break; \ - } \ - case MCD_OPC_Decode: { \ - Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - MCInst_setOpcode(MI, Opc); \ - return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ - } \ - case MCD_OPC_SoftFail: { \ - PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ - if (Fail) \ - S = MCDisassembler_SoftFail; \ - break; \ - } \ - case MCD_OPC_Fail: { \ - return MCDisassembler_Fail; \ - } \ - } \ - } \ + static const AliasPattern Patterns[] = { + // SP::BCOND - 0 + {0, 0, 2, 2}, + {6, 2, 2, 2}, + {12, 4, 2, 2}, + {19, 6, 2, 2}, + {25, 8, 2, 2}, + {31, 10, 2, 2}, + {38, 12, 2, 2}, + {45, 14, 2, 2}, + {51, 16, 2, 2}, + {58, 18, 2, 2}, + {66, 20, 2, 2}, + {73, 22, 2, 2}, + {80, 24, 2, 2}, + {88, 26, 2, 2}, + {96, 28, 2, 2}, + {103, 30, 2, 2}, + // SP::BCONDA - 16 + {110, 32, 2, 2}, + {118, 34, 2, 2}, + {126, 36, 2, 2}, + {135, 38, 2, 2}, + {143, 40, 2, 2}, + {151, 42, 2, 2}, + {160, 44, 2, 2}, + {169, 46, 2, 2}, + {177, 48, 2, 2}, + {186, 50, 2, 2}, + {196, 52, 2, 2}, + {205, 54, 2, 2}, + {214, 56, 2, 2}, + {224, 58, 2, 2}, + {234, 60, 2, 2}, + {243, 62, 2, 2}, + // SP::BPFCCANT - 32 + {252, 64, 3, 4}, + {268, 68, 3, 4}, + {284, 72, 3, 4}, + {300, 76, 3, 4}, + {316, 80, 3, 4}, + {333, 84, 3, 4}, + {349, 88, 3, 4}, + {366, 92, 3, 4}, + {383, 96, 3, 4}, + {400, 100, 3, 4}, + {416, 104, 3, 4}, + {433, 108, 3, 4}, + {450, 112, 3, 4}, + {468, 116, 3, 4}, + {485, 120, 3, 4}, + {503, 124, 3, 4}, + // SP::BPFCCNT - 48 + {519, 128, 3, 4}, + {533, 132, 3, 4}, + {547, 136, 3, 4}, + {561, 140, 3, 4}, + {575, 144, 3, 4}, + {590, 148, 3, 4}, + {604, 152, 3, 4}, + {619, 156, 3, 4}, + {634, 160, 3, 4}, + {649, 164, 3, 4}, + {663, 168, 3, 4}, + {678, 172, 3, 4}, + {693, 176, 3, 4}, + {709, 180, 3, 4}, + {724, 184, 3, 4}, + {740, 188, 3, 4}, + // SP::BPICCANT - 64 + {754, 192, 2, 3}, + {771, 195, 2, 3}, + {788, 198, 2, 3}, + {806, 201, 2, 3}, + {823, 204, 2, 3}, + {840, 207, 2, 3}, + {858, 210, 2, 3}, + {876, 213, 2, 3}, + {893, 216, 2, 3}, + {911, 219, 2, 3}, + {930, 222, 2, 3}, + {948, 225, 2, 3}, + {966, 228, 2, 3}, + {985, 231, 2, 3}, + {1004, 234, 2, 3}, + {1022, 237, 2, 3}, + // SP::BPICCNT - 80 + {1040, 240, 2, 3}, + {1055, 243, 2, 3}, + {1070, 246, 2, 3}, + {1086, 249, 2, 3}, + {1101, 252, 2, 3}, + {1116, 255, 2, 3}, + {1132, 258, 2, 3}, + {1148, 261, 2, 3}, + {1163, 264, 2, 3}, + {1179, 267, 2, 3}, + {1196, 270, 2, 3}, + {1212, 273, 2, 3}, + {1228, 276, 2, 3}, + {1245, 279, 2, 3}, + {1262, 282, 2, 3}, + {1278, 285, 2, 3}, + // SP::BPXCCANT - 96 + {1294, 288, 2, 2}, + {1311, 290, 2, 2}, + {1328, 292, 2, 2}, + {1346, 294, 2, 2}, + {1363, 296, 2, 2}, + {1380, 298, 2, 2}, + {1398, 300, 2, 2}, + {1416, 302, 2, 2}, + {1433, 304, 2, 2}, + {1451, 306, 2, 2}, + {1470, 308, 2, 2}, + {1488, 310, 2, 2}, + {1506, 312, 2, 2}, + {1525, 314, 2, 2}, + {1544, 316, 2, 2}, + {1562, 318, 2, 2}, + // SP::BPXCCNT - 112 + {1580, 320, 2, 2}, + {1595, 322, 2, 2}, + {1610, 324, 2, 2}, + {1626, 326, 2, 2}, + {1641, 328, 2, 2}, + {1656, 330, 2, 2}, + {1672, 332, 2, 2}, + {1688, 334, 2, 2}, + {1703, 336, 2, 2}, + {1719, 338, 2, 2}, + {1736, 340, 2, 2}, + {1752, 342, 2, 2}, + {1768, 344, 2, 2}, + {1785, 346, 2, 2}, + {1802, 348, 2, 2}, + {1818, 350, 2, 2}, + // SP::FMOVD_ICC - 128 + {1834, 352, 4, 5}, + {1854, 357, 4, 5}, + {1874, 362, 4, 5}, + {1895, 367, 4, 5}, + {1915, 372, 4, 5}, + {1935, 377, 4, 5}, + {1956, 382, 4, 5}, + {1977, 387, 4, 5}, + {1997, 392, 4, 5}, + {2018, 397, 4, 5}, + {2040, 402, 4, 5}, + {2061, 407, 4, 5}, + {2082, 412, 4, 5}, + {2104, 417, 4, 5}, + {2126, 422, 4, 5}, + {2147, 427, 4, 5}, + // SP::FMOVD_XCC - 144 + {2168, 432, 4, 4}, + {2188, 436, 4, 4}, + {2208, 440, 4, 4}, + {2229, 444, 4, 4}, + {2249, 448, 4, 4}, + {2269, 452, 4, 4}, + {2290, 456, 4, 4}, + {2311, 460, 4, 4}, + {2331, 464, 4, 4}, + {2352, 468, 4, 4}, + {2374, 472, 4, 4}, + {2395, 476, 4, 4}, + {2416, 480, 4, 4}, + {2438, 484, 4, 4}, + {2460, 488, 4, 4}, + {2481, 492, 4, 4}, + // SP::FMOVQ_ICC - 160 + {2502, 496, 4, 5}, + {2522, 501, 4, 5}, + {2542, 506, 4, 5}, + {2563, 511, 4, 5}, + {2583, 516, 4, 5}, + {2603, 521, 4, 5}, + {2624, 526, 4, 5}, + {2645, 531, 4, 5}, + {2665, 536, 4, 5}, + {2686, 541, 4, 5}, + {2708, 546, 4, 5}, + {2729, 551, 4, 5}, + {2750, 556, 4, 5}, + {2772, 561, 4, 5}, + {2794, 566, 4, 5}, + {2815, 571, 4, 5}, + // SP::FMOVQ_XCC - 176 + {2836, 576, 4, 4}, + {2856, 580, 4, 4}, + {2876, 584, 4, 4}, + {2897, 588, 4, 4}, + {2917, 592, 4, 4}, + {2937, 596, 4, 4}, + {2958, 600, 4, 4}, + {2979, 604, 4, 4}, + {2999, 608, 4, 4}, + {3020, 612, 4, 4}, + {3042, 616, 4, 4}, + {3063, 620, 4, 4}, + {3084, 624, 4, 4}, + {3106, 628, 4, 4}, + {3128, 632, 4, 4}, + {3149, 636, 4, 4}, + // SP::FMOVS_ICC - 192 + {3170, 640, 4, 5}, + {3190, 645, 4, 5}, + {3210, 650, 4, 5}, + {3231, 655, 4, 5}, + {3251, 660, 4, 5}, + {3271, 665, 4, 5}, + {3292, 670, 4, 5}, + {3313, 675, 4, 5}, + {3333, 680, 4, 5}, + {3354, 685, 4, 5}, + {3376, 690, 4, 5}, + {3397, 695, 4, 5}, + {3418, 700, 4, 5}, + {3440, 705, 4, 5}, + {3462, 710, 4, 5}, + {3483, 715, 4, 5}, + // SP::FMOVS_XCC - 208 + {3504, 720, 4, 4}, + {3524, 724, 4, 4}, + {3544, 728, 4, 4}, + {3565, 732, 4, 4}, + {3585, 736, 4, 4}, + {3605, 740, 4, 4}, + {3626, 744, 4, 4}, + {3647, 748, 4, 4}, + {3667, 752, 4, 4}, + {3688, 756, 4, 4}, + {3710, 760, 4, 4}, + {3731, 764, 4, 4}, + {3752, 768, 4, 4}, + {3774, 772, 4, 4}, + {3796, 776, 4, 4}, + {3817, 780, 4, 4}, + // SP::MOVICCri - 224 + {3838, 784, 4, 5}, + {3856, 789, 4, 5}, + {3874, 794, 4, 5}, + {3893, 799, 4, 5}, + {3911, 804, 4, 5}, + {3929, 809, 4, 5}, + {3948, 814, 4, 5}, + {3967, 819, 4, 5}, + {3985, 824, 4, 5}, + {4004, 829, 4, 5}, + {4024, 834, 4, 5}, + {4043, 839, 4, 5}, + {4062, 844, 4, 5}, + {4082, 849, 4, 5}, + {4102, 854, 4, 5}, + {4121, 859, 4, 5}, + // SP::MOVICCrr - 240 + {3838, 864, 4, 5}, + {3856, 869, 4, 5}, + {3874, 874, 4, 5}, + {3893, 879, 4, 5}, + {3911, 884, 4, 5}, + {3929, 889, 4, 5}, + {3948, 894, 4, 5}, + {3967, 899, 4, 5}, + {3985, 904, 4, 5}, + {4004, 909, 4, 5}, + {4024, 914, 4, 5}, + {4043, 919, 4, 5}, + {4062, 924, 4, 5}, + {4082, 929, 4, 5}, + {4102, 934, 4, 5}, + {4121, 939, 4, 5}, + // SP::MOVXCCri - 256 + {4140, 944, 4, 4}, + {4158, 948, 4, 4}, + {4176, 952, 4, 4}, + {4195, 956, 4, 4}, + {4213, 960, 4, 4}, + {4231, 964, 4, 4}, + {4250, 968, 4, 4}, + {4269, 972, 4, 4}, + {4287, 976, 4, 4}, + {4306, 980, 4, 4}, + {4326, 984, 4, 4}, + {4345, 988, 4, 4}, + {4364, 992, 4, 4}, + {4384, 996, 4, 4}, + {4404, 1000, 4, 4}, + {4423, 1004, 4, 4}, + // SP::MOVXCCrr - 272 + {4140, 1008, 4, 4}, + {4158, 1012, 4, 4}, + {4176, 1016, 4, 4}, + {4195, 1020, 4, 4}, + {4213, 1024, 4, 4}, + {4231, 1028, 4, 4}, + {4250, 1032, 4, 4}, + {4269, 1036, 4, 4}, + {4287, 1040, 4, 4}, + {4306, 1044, 4, 4}, + {4326, 1048, 4, 4}, + {4345, 1052, 4, 4}, + {4364, 1056, 4, 4}, + {4384, 1060, 4, 4}, + {4404, 1064, 4, 4}, + {4423, 1068, 4, 4}, + // SP::ORCCrr - 288 + {4442, 1072, 3, 3}, + // SP::ORri - 289 + {4449, 1075, 3, 2}, + // SP::ORrr - 290 + {4449, 1077, 3, 3}, + // SP::RESTORErr - 291 + {4460, 1080, 3, 3}, + // SP::RET - 292 + {4468, 1083, 1, 1}, + // SP::RETL - 293 + {4472, 1084, 1, 1}, + // SP::SAVErr - 294 + {4477, 1085, 3, 3}, + // SP::TICCri - 295 + {4482, 1088, 3, 4}, + {4494, 1092, 3, 4}, + {4511, 1096, 3, 4}, + {4523, 1100, 3, 4}, + {4540, 1104, 3, 4}, + {4553, 1108, 3, 4}, + {4571, 1112, 3, 4}, + {4583, 1116, 3, 4}, + {4600, 1120, 3, 4}, + {4612, 1124, 3, 4}, + {4629, 1128, 3, 4}, + {4642, 1132, 3, 4}, + {4660, 1136, 3, 4}, + {4673, 1140, 3, 4}, + {4691, 1144, 3, 4}, + {4703, 1148, 3, 4}, + {4720, 1152, 3, 4}, + {4733, 1156, 3, 4}, + {4751, 1160, 3, 4}, + {4765, 1164, 3, 4}, + {4784, 1168, 3, 4}, + {4797, 1172, 3, 4}, + {4815, 1176, 3, 4}, + {4828, 1180, 3, 4}, + {4846, 1184, 3, 4}, + {4860, 1188, 3, 4}, + {4879, 1192, 3, 4}, + {4893, 1196, 3, 4}, + {4912, 1200, 3, 4}, + {4925, 1204, 3, 4}, + {4943, 1208, 3, 4}, + {4956, 1212, 3, 4}, + // SP::TICCrr - 327 + {4482, 1216, 3, 4}, + {4494, 1220, 3, 4}, + {4511, 1224, 3, 4}, + {4523, 1228, 3, 4}, + {4540, 1232, 3, 4}, + {4553, 1236, 3, 4}, + {4571, 1240, 3, 4}, + {4583, 1244, 3, 4}, + {4600, 1248, 3, 4}, + {4612, 1252, 3, 4}, + {4629, 1256, 3, 4}, + {4642, 1260, 3, 4}, + {4660, 1264, 3, 4}, + {4673, 1268, 3, 4}, + {4691, 1272, 3, 4}, + {4703, 1276, 3, 4}, + {4720, 1280, 3, 4}, + {4733, 1284, 3, 4}, + {4751, 1288, 3, 4}, + {4765, 1292, 3, 4}, + {4784, 1296, 3, 4}, + {4797, 1300, 3, 4}, + {4815, 1304, 3, 4}, + {4828, 1308, 3, 4}, + {4846, 1312, 3, 4}, + {4860, 1316, 3, 4}, + {4879, 1320, 3, 4}, + {4893, 1324, 3, 4}, + {4912, 1328, 3, 4}, + {4925, 1332, 3, 4}, + {4943, 1336, 3, 4}, + {4956, 1340, 3, 4}, + // SP::TRAPri - 359 + {4974, 1344, 3, 3}, + {4980, 1347, 3, 3}, + {4991, 1350, 3, 3}, + {4997, 1353, 3, 3}, + {5008, 1356, 3, 3}, + {5015, 1359, 3, 3}, + {5027, 1362, 3, 3}, + {5033, 1365, 3, 3}, + {5044, 1368, 3, 3}, + {5050, 1371, 3, 3}, + {5061, 1374, 3, 3}, + {5068, 1377, 3, 3}, + {5080, 1380, 3, 3}, + {5087, 1383, 3, 3}, + {5099, 1386, 3, 3}, + {5105, 1389, 3, 3}, + {5116, 1392, 3, 3}, + {5123, 1395, 3, 3}, + {5135, 1398, 3, 3}, + {5143, 1401, 3, 3}, + {5156, 1404, 3, 3}, + {5163, 1407, 3, 3}, + {5175, 1410, 3, 3}, + {5182, 1413, 3, 3}, + {5194, 1416, 3, 3}, + {5202, 1419, 3, 3}, + {5215, 1422, 3, 3}, + {5223, 1425, 3, 3}, + {5236, 1428, 3, 3}, + {5243, 1431, 3, 3}, + {5255, 1434, 3, 3}, + {5262, 1437, 3, 3}, + // SP::TRAPrr - 391 + {4974, 1440, 3, 3}, + {4980, 1443, 3, 3}, + {4991, 1446, 3, 3}, + {4997, 1449, 3, 3}, + {5008, 1452, 3, 3}, + {5015, 1455, 3, 3}, + {5027, 1458, 3, 3}, + {5033, 1461, 3, 3}, + {5044, 1464, 3, 3}, + {5050, 1467, 3, 3}, + {5061, 1470, 3, 3}, + {5068, 1473, 3, 3}, + {5080, 1476, 3, 3}, + {5087, 1479, 3, 3}, + {5099, 1482, 3, 3}, + {5105, 1485, 3, 3}, + {5116, 1488, 3, 3}, + {5123, 1491, 3, 3}, + {5135, 1494, 3, 3}, + {5143, 1497, 3, 3}, + {5156, 1500, 3, 3}, + {5163, 1503, 3, 3}, + {5175, 1506, 3, 3}, + {5182, 1509, 3, 3}, + {5194, 1512, 3, 3}, + {5202, 1515, 3, 3}, + {5215, 1518, 3, 3}, + {5223, 1521, 3, 3}, + {5236, 1524, 3, 3}, + {5243, 1527, 3, 3}, + {5255, 1530, 3, 3}, + {5262, 1533, 3, 3}, + // SP::TXCCri - 423 + {5274, 1536, 3, 4}, + {5286, 1540, 3, 4}, + {5303, 1544, 3, 4}, + {5315, 1548, 3, 4}, + {5332, 1552, 3, 4}, + {5345, 1556, 3, 4}, + {5363, 1560, 3, 4}, + {5375, 1564, 3, 4}, + {5392, 1568, 3, 4}, + {5404, 1572, 3, 4}, + {5421, 1576, 3, 4}, + {5434, 1580, 3, 4}, + {5452, 1584, 3, 4}, + {5465, 1588, 3, 4}, + {5483, 1592, 3, 4}, + {5495, 1596, 3, 4}, + {5512, 1600, 3, 4}, + {5525, 1604, 3, 4}, + {5543, 1608, 3, 4}, + {5557, 1612, 3, 4}, + {5576, 1616, 3, 4}, + {5589, 1620, 3, 4}, + {5607, 1624, 3, 4}, + {5620, 1628, 3, 4}, + {5638, 1632, 3, 4}, + {5652, 1636, 3, 4}, + {5671, 1640, 3, 4}, + {5685, 1644, 3, 4}, + {5704, 1648, 3, 4}, + {5717, 1652, 3, 4}, + {5735, 1656, 3, 4}, + {5748, 1660, 3, 4}, + // SP::TXCCrr - 455 + {5274, 1664, 3, 4}, + {5286, 1668, 3, 4}, + {5303, 1672, 3, 4}, + {5315, 1676, 3, 4}, + {5332, 1680, 3, 4}, + {5345, 1684, 3, 4}, + {5363, 1688, 3, 4}, + {5375, 1692, 3, 4}, + {5392, 1696, 3, 4}, + {5404, 1700, 3, 4}, + {5421, 1704, 3, 4}, + {5434, 1708, 3, 4}, + {5452, 1712, 3, 4}, + {5465, 1716, 3, 4}, + {5483, 1720, 3, 4}, + {5495, 1724, 3, 4}, + {5512, 1728, 3, 4}, + {5525, 1732, 3, 4}, + {5543, 1736, 3, 4}, + {5557, 1740, 3, 4}, + {5576, 1744, 3, 4}, + {5589, 1748, 3, 4}, + {5607, 1752, 3, 4}, + {5620, 1756, 3, 4}, + {5638, 1760, 3, 4}, + {5652, 1764, 3, 4}, + {5671, 1768, 3, 4}, + {5685, 1772, 3, 4}, + {5704, 1776, 3, 4}, + {5717, 1780, 3, 4}, + {5735, 1784, 3, 4}, + {5748, 1788, 3, 4}, + // SP::V9FCMPD - 487 + {5766, 1792, 3, 3}, + // SP::V9FCMPED - 488 + {5779, 1795, 3, 3}, + // SP::V9FCMPEQ - 489 + {5793, 1798, 3, 3}, + // SP::V9FCMPES - 490 + {5807, 1801, 3, 3}, + // SP::V9FCMPQ - 491 + {5821, 1804, 3, 3}, + // SP::V9FCMPS - 492 + {5834, 1807, 3, 3}, + // SP::V9FMOVD_FCC - 493 + {5847, 1810, 5, 6}, + {5865, 1816, 5, 6}, + {5883, 1822, 5, 6}, + {5901, 1828, 5, 6}, + {5919, 1834, 5, 6}, + {5938, 1840, 5, 6}, + {5956, 1846, 5, 6}, + {5975, 1852, 5, 6}, + {5994, 1858, 5, 6}, + {6013, 1864, 5, 6}, + {6031, 1870, 5, 6}, + {6050, 1876, 5, 6}, + {6069, 1882, 5, 6}, + {6089, 1888, 5, 6}, + {6108, 1894, 5, 6}, + {6128, 1900, 5, 6}, + // SP::V9FMOVQ_FCC - 509 + {6146, 1906, 5, 6}, + {6164, 1912, 5, 6}, + {6182, 1918, 5, 6}, + {6200, 1924, 5, 6}, + {6218, 1930, 5, 6}, + {6237, 1936, 5, 6}, + {6255, 1942, 5, 6}, + {6274, 1948, 5, 6}, + {6293, 1954, 5, 6}, + {6312, 1960, 5, 6}, + {6330, 1966, 5, 6}, + {6349, 1972, 5, 6}, + {6368, 1978, 5, 6}, + {6388, 1984, 5, 6}, + {6407, 1990, 5, 6}, + {6427, 1996, 5, 6}, + // SP::V9FMOVS_FCC - 525 + {6445, 2002, 5, 6}, + {6463, 2008, 5, 6}, + {6481, 2014, 5, 6}, + {6499, 2020, 5, 6}, + {6517, 2026, 5, 6}, + {6536, 2032, 5, 6}, + {6554, 2038, 5, 6}, + {6573, 2044, 5, 6}, + {6592, 2050, 5, 6}, + {6611, 2056, 5, 6}, + {6629, 2062, 5, 6}, + {6648, 2068, 5, 6}, + {6667, 2074, 5, 6}, + {6687, 2080, 5, 6}, + {6706, 2086, 5, 6}, + {6726, 2092, 5, 6}, + // SP::V9MOVFCCri - 541 + {6744, 2098, 5, 6}, + {6760, 2104, 5, 6}, + {6776, 2110, 5, 6}, + {6792, 2116, 5, 6}, + {6808, 2122, 5, 6}, + {6825, 2128, 5, 6}, + {6841, 2134, 5, 6}, + {6858, 2140, 5, 6}, + {6875, 2146, 5, 6}, + {6892, 2152, 5, 6}, + {6908, 2158, 5, 6}, + {6925, 2164, 5, 6}, + {6942, 2170, 5, 6}, + {6960, 2176, 5, 6}, + {6977, 2182, 5, 6}, + {6995, 2188, 5, 6}, + // SP::V9MOVFCCrr - 557 + {6744, 2194, 5, 6}, + {6760, 2200, 5, 6}, + {6776, 2206, 5, 6}, + {6792, 2212, 5, 6}, + {6808, 2218, 5, 6}, + {6825, 2224, 5, 6}, + {6841, 2230, 5, 6}, + {6858, 2236, 5, 6}, + {6875, 2242, 5, 6}, + {6892, 2248, 5, 6}, + {6908, 2254, 5, 6}, + {6925, 2260, 5, 6}, + {6942, 2266, 5, 6}, + {6960, 2272, 5, 6}, + {6977, 2278, 5, 6}, + {6995, 2284, 5, 6}, + }; + + static const AliasPatternCond Conds[] = { + // (BCOND brtarget:$imm, 8) - 0 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (BCOND brtarget:$imm, 0) - 2 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BCOND brtarget:$imm, 9) - 4 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (BCOND brtarget:$imm, 1) - 6 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (BCOND brtarget:$imm, 10) - 8 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (BCOND brtarget:$imm, 2) - 10 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (BCOND brtarget:$imm, 11) - 12 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (BCOND brtarget:$imm, 3) - 14 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (BCOND brtarget:$imm, 12) - 16 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (BCOND brtarget:$imm, 4) - 18 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (BCOND brtarget:$imm, 13) - 20 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (BCOND brtarget:$imm, 5) - 22 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (BCOND brtarget:$imm, 14) - 24 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (BCOND brtarget:$imm, 6) - 26 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (BCOND brtarget:$imm, 15) - 28 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (BCOND brtarget:$imm, 7) - 30 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (BCONDA brtarget:$imm, 8) - 32 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (BCONDA brtarget:$imm, 0) - 34 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BCONDA brtarget:$imm, 9) - 36 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (BCONDA brtarget:$imm, 1) - 38 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (BCONDA brtarget:$imm, 10) - 40 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (BCONDA brtarget:$imm, 2) - 42 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (BCONDA brtarget:$imm, 11) - 44 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (BCONDA brtarget:$imm, 3) - 46 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (BCONDA brtarget:$imm, 12) - 48 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (BCONDA brtarget:$imm, 4) - 50 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (BCONDA brtarget:$imm, 13) - 52 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (BCONDA brtarget:$imm, 5) - 54 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (BCONDA brtarget:$imm, 14) - 56 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (BCONDA brtarget:$imm, 6) - 58 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (BCONDA brtarget:$imm, 15) - 60 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (BCONDA brtarget:$imm, 7) - 62 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 8) - 192 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 0) - 195 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 9) - 198 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 1) - 201 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 10) - 204 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 2) - 207 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 11) - 210 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 3) - 213 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 12) - 216 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 4) - 219 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 13) - 222 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 5) - 225 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 14) - 228 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 6) - 231 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 15) - 234 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCANT brtarget:$imm, 7) - 237 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 8) - 240 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 0) - 243 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 9) - 246 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 1) - 249 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 10) - 252 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 2) - 255 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 11) - 258 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 3) - 261 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 12) - 264 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 4) - 267 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 13) - 270 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 5) - 273 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 14) - 276 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 6) - 279 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 15) - 282 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPICCNT brtarget:$imm, 7) - 285 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (BPXCCANT brtarget:$imm, 8) - 288 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (BPXCCANT brtarget:$imm, 0) - 290 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BPXCCANT brtarget:$imm, 9) - 292 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (BPXCCANT brtarget:$imm, 1) - 294 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (BPXCCANT brtarget:$imm, 10) - 296 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (BPXCCANT brtarget:$imm, 2) - 298 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (BPXCCANT brtarget:$imm, 11) - 300 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (BPXCCANT brtarget:$imm, 3) - 302 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (BPXCCANT brtarget:$imm, 12) - 304 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (BPXCCANT brtarget:$imm, 4) - 306 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (BPXCCANT brtarget:$imm, 13) - 308 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (BPXCCANT brtarget:$imm, 5) - 310 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (BPXCCANT brtarget:$imm, 14) - 312 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (BPXCCANT brtarget:$imm, 6) - 314 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (BPXCCANT brtarget:$imm, 15) - 316 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (BPXCCANT brtarget:$imm, 7) - 318 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (BPXCCNT brtarget:$imm, 8) - 320 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (BPXCCNT brtarget:$imm, 0) - 322 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (BPXCCNT brtarget:$imm, 9) - 324 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (BPXCCNT brtarget:$imm, 1) - 326 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (BPXCCNT brtarget:$imm, 10) - 328 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (BPXCCNT brtarget:$imm, 2) - 330 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (BPXCCNT brtarget:$imm, 11) - 332 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (BPXCCNT brtarget:$imm, 3) - 334 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (BPXCCNT brtarget:$imm, 12) - 336 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (BPXCCNT brtarget:$imm, 4) - 338 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (BPXCCNT brtarget:$imm, 13) - 340 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (BPXCCNT brtarget:$imm, 5) - 342 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (BPXCCNT brtarget:$imm, 14) - 344 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (BPXCCNT brtarget:$imm, 6) - 346 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (BPXCCNT brtarget:$imm, 15) - 348 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (BPXCCNT brtarget:$imm, 7) - 350 + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 352 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 357 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 362 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 367 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 372 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 377 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 382 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 387 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 392 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 397 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 402 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 407 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 412 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 417 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 422 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 427 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) - 432 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) - 436 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) - 440 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) - 444 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) - 448 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) - 452 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) - 456 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) - 460 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) - 464 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) - 468 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) - 472 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) - 476 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) - 480 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) - 484 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) - 488 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) - 492 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 496 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 501 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 506 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 511 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 516 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 521 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 526 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 531 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 536 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 541 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 546 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 551 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 556 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 561 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 566 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 571 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) - 576 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) - 580 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) - 584 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) - 588 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) - 592 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) - 596 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) - 600 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) - 604 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) - 608 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) - 612 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) - 616 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) - 620 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) - 624 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) - 628 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) - 632 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) - 636 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 640 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 645 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 650 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 655 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 660 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 665 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 670 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 675 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 680 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 685 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 690 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 695 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 700 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 705 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 710 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 715 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) - 720 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) - 724 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) - 728 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) - 732 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) - 736 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) - 740 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) - 744 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) - 748 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) - 752 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) - 756 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) - 760 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) - 764 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) - 768 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) - 772 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) - 776 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) - 780 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 784 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 789 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 794 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 799 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 804 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 809 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 814 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 819 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 824 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 829 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 834 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 839 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 844 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 849 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 854 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 859 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 864 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 869 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 874 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 879 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 884 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 889 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 894 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 899 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 904 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 909 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 914 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 919 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 924 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 929 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 934 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 939 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) - 944 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) - 948 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) - 952 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) - 956 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) - 960 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) - 964 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) - 968 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) - 972 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) - 976 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) - 980 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) - 984 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) - 988 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) - 992 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) - 996 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) - 1000 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) - 1004 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1008 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1012 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1016 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1020 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1024 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1028 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1032 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1036 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1040 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1044 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1048 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1052 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1056 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1060 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1064 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1068 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (ORCCrr G0, IntRegs:$rs2, G0) - 1072 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Reg, SP_G0}, + // (ORri IntRegs:$rd, G0, i32imm:$simm13) - 1075 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Reg, SP_G0}, + // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1077 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + // (RESTORErr G0, G0, G0) - 1080 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Reg, SP_G0}, + // (RET 8) - 1083 + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (RETL 8) - 1084 + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (SAVErr G0, G0, G0) - 1085 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Reg, SP_G0}, + // (TICCri G0, i32imm:$imm, 8) - 1088 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1092 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 0) - 1096 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1100 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 9) - 1104 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1108 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 1) - 1112 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1116 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 10) - 1120 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1124 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 2) - 1128 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1132 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 11) - 1136 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1140 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 3) - 1144 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1148 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 12) - 1152 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1156 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 4) - 1160 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1164 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 13) - 1168 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1172 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 5) - 1176 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1180 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 14) - 1184 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1188 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 6) - 1192 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1196 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 15) - 1200 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 1204 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri G0, i32imm:$imm, 7) - 1208 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 1212 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 8) - 1216 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1220 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 0) - 1224 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1228 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 9) - 1232 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1236 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 1) - 1240 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1244 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 10) - 1248 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1252 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 2) - 1256 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1260 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 11) - 1264 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1268 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 3) - 1272 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1276 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 12) - 1280 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1284 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 4) - 1288 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1292 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 13) - 1296 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1300 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 5) - 1304 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1308 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 14) - 1312 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1316 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 6) - 1320 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1324 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 15) - 1328 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1332 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr G0, IntRegs:$rs2, 7) - 1336 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1340 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TRAPri G0, i32imm:$imm, 8) - 1344 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 1347 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (TRAPri G0, i32imm:$imm, 0) - 1350 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 1353 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TRAPri G0, i32imm:$imm, 9) - 1356 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 1359 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (TRAPri G0, i32imm:$imm, 1) - 1362 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 1365 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (TRAPri G0, i32imm:$imm, 10) - 1368 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 1371 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (TRAPri G0, i32imm:$imm, 2) - 1374 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 1377 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (TRAPri G0, i32imm:$imm, 11) - 1380 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 1383 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (TRAPri G0, i32imm:$imm, 3) - 1386 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 1389 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (TRAPri G0, i32imm:$imm, 12) - 1392 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 1395 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (TRAPri G0, i32imm:$imm, 4) - 1398 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 1401 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (TRAPri G0, i32imm:$imm, 13) - 1404 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 1407 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (TRAPri G0, i32imm:$imm, 5) - 1410 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 1413 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (TRAPri G0, i32imm:$imm, 14) - 1416 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 1419 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (TRAPri G0, i32imm:$imm, 6) - 1422 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 1425 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (TRAPri G0, i32imm:$imm, 15) - 1428 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 1431 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (TRAPri G0, i32imm:$imm, 7) - 1434 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 1437 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (TRAPrr G0, IntRegs:$rs1, 8) - 1440 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1443 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + // (TRAPrr G0, IntRegs:$rs1, 0) - 1446 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1449 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (TRAPrr G0, IntRegs:$rs1, 9) - 1452 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1455 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + // (TRAPrr G0, IntRegs:$rs1, 1) - 1458 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1461 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + // (TRAPrr G0, IntRegs:$rs1, 10) - 1464 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1467 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + // (TRAPrr G0, IntRegs:$rs1, 2) - 1470 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1473 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + // (TRAPrr G0, IntRegs:$rs1, 11) - 1476 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1479 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + // (TRAPrr G0, IntRegs:$rs1, 3) - 1482 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1485 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + // (TRAPrr G0, IntRegs:$rs1, 12) - 1488 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1491 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + // (TRAPrr G0, IntRegs:$rs1, 4) - 1494 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1497 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + // (TRAPrr G0, IntRegs:$rs1, 13) - 1500 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1503 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + // (TRAPrr G0, IntRegs:$rs1, 5) - 1506 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1509 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + // (TRAPrr G0, IntRegs:$rs1, 14) - 1512 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1515 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + // (TRAPrr G0, IntRegs:$rs1, 6) - 1518 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1521 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + // (TRAPrr G0, IntRegs:$rs1, 15) - 1524 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1527 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + // (TRAPrr G0, IntRegs:$rs1, 7) - 1530 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1533 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + // (TXCCri G0, i32imm:$imm, 8) - 1536 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 1540 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 0) - 1544 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 1548 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 9) - 1552 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 1556 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 1) - 1560 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 1564 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 10) - 1568 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 1572 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 2) - 1576 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 1580 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 11) - 1584 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 1588 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 3) - 1592 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 1596 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 12) - 1600 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 1604 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 4) - 1608 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 1612 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 13) - 1616 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 1620 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 5) - 1624 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 1628 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 14) - 1632 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 1636 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 6) - 1640 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 1644 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 15) - 1648 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 1652 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri G0, i32imm:$imm, 7) - 1656 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 1660 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 8) - 1664 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1668 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 0) - 1672 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1676 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 9) - 1680 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1684 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 1) - 1688 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1692 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 10) - 1696 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1700 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 2) - 1704 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1708 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 11) - 1712 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1716 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 3) - 1720 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1724 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 12) - 1728 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1732 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 4) - 1736 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1740 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 13) - 1744 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1748 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 5) - 1752 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1756 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 14) - 1760 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1764 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 6) - 1768 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1772 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 15) - 1776 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1780 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr G0, IntRegs:$rs2, 7) - 1784 + {AliasPatternCond_K_Reg, SP_G0}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1788 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 1792 + {AliasPatternCond_K_Reg, SP_FCC0}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 1795 + {AliasPatternCond_K_Reg, SP_FCC0}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 1798 + {AliasPatternCond_K_Reg, SP_FCC0}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 1801 + {AliasPatternCond_K_Reg, SP_FCC0}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 1804 + {AliasPatternCond_K_Reg, SP_FCC0}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 1807 + {AliasPatternCond_K_Reg, SP_FCC0}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 1810 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 1816 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 1822 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 1828 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 1834 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 1840 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 1846 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 1852 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 1858 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 1864 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 1870 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 1876 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 1882 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 1888 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 1894 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 1900 + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_DFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 1906 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 1912 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 1918 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 1924 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 1930 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 1936 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 1942 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 1948 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 1954 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 1960 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 1966 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 1972 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 1978 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 1984 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 1990 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 1996 + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_QFPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 2002 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 2008 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 2014 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 2020 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 2026 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 2032 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 2038 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 2044 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 2050 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 2056 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 2062 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 2068 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 2074 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 2080 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 2086 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 2092 + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FPRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 2098 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 2104 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 2110 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 2116 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 2122 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 2128 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 2134 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 2140 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 2146 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 2152 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 2158 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 2164 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 2170 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 2176 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 2182 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 2188 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 2194 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)8}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 2200 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 2206 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)7}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 2212 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)6}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 2218 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)5}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 2224 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)4}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 2230 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)3}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 2236 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)2}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 2242 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)1}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 2248 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)9}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 2254 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)10}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 2260 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)11}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 2266 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)12}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 2272 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)13}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 2278 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)14}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 2284 + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_FCCRegsRegClassID}, + {AliasPatternCond_K_RegClass, SP_IntRegsRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)15}, + {AliasPatternCond_K_Feature, Sparc_FeatureV9}, + }; + + static const char *AsmStrings[] = { + /* 0 */ "ba $\x01\0" + /* 6 */ "bn $\x01\0" + /* 12 */ "bne $\x01\0" + /* 19 */ "be $\x01\0" + /* 25 */ "bg $\x01\0" + /* 31 */ "ble $\x01\0" + /* 38 */ "bge $\x01\0" + /* 45 */ "bl $\x01\0" + /* 51 */ "bgu $\x01\0" + /* 58 */ "bleu $\x01\0" + /* 66 */ "bcc $\x01\0" + /* 73 */ "bcs $\x01\0" + /* 80 */ "bpos $\x01\0" + /* 88 */ "bneg $\x01\0" + /* 96 */ "bvc $\x01\0" + /* 103 */ "bvs $\x01\0" + /* 110 */ "ba,a $\x01\0" + /* 118 */ "bn,a $\x01\0" + /* 126 */ "bne,a $\x01\0" + /* 135 */ "be,a $\x01\0" + /* 143 */ "bg,a $\x01\0" + /* 151 */ "ble,a $\x01\0" + /* 160 */ "bge,a $\x01\0" + /* 169 */ "bl,a $\x01\0" + /* 177 */ "bgu,a $\x01\0" + /* 186 */ "bleu,a $\x01\0" + /* 196 */ "bcc,a $\x01\0" + /* 205 */ "bcs,a $\x01\0" + /* 214 */ "bpos,a $\x01\0" + /* 224 */ "bneg,a $\x01\0" + /* 234 */ "bvc,a $\x01\0" + /* 243 */ "bvs,a $\x01\0" + /* 252 */ "fba,a,pn $\x03, $\x01\0" + /* 268 */ "fbn,a,pn $\x03, $\x01\0" + /* 284 */ "fbu,a,pn $\x03, $\x01\0" + /* 300 */ "fbg,a,pn $\x03, $\x01\0" + /* 316 */ "fbug,a,pn $\x03, $\x01\0" + /* 333 */ "fbl,a,pn $\x03, $\x01\0" + /* 349 */ "fbul,a,pn $\x03, $\x01\0" + /* 366 */ "fblg,a,pn $\x03, $\x01\0" + /* 383 */ "fbne,a,pn $\x03, $\x01\0" + /* 400 */ "fbe,a,pn $\x03, $\x01\0" + /* 416 */ "fbue,a,pn $\x03, $\x01\0" + /* 433 */ "fbge,a,pn $\x03, $\x01\0" + /* 450 */ "fbuge,a,pn $\x03, $\x01\0" + /* 468 */ "fble,a,pn $\x03, $\x01\0" + /* 485 */ "fbule,a,pn $\x03, $\x01\0" + /* 503 */ "fbo,a,pn $\x03, $\x01\0" + /* 519 */ "fba,pn $\x03, $\x01\0" + /* 533 */ "fbn,pn $\x03, $\x01\0" + /* 547 */ "fbu,pn $\x03, $\x01\0" + /* 561 */ "fbg,pn $\x03, $\x01\0" + /* 575 */ "fbug,pn $\x03, $\x01\0" + /* 590 */ "fbl,pn $\x03, $\x01\0" + /* 604 */ "fbul,pn $\x03, $\x01\0" + /* 619 */ "fblg,pn $\x03, $\x01\0" + /* 634 */ "fbne,pn $\x03, $\x01\0" + /* 649 */ "fbe,pn $\x03, $\x01\0" + /* 663 */ "fbue,pn $\x03, $\x01\0" + /* 678 */ "fbge,pn $\x03, $\x01\0" + /* 693 */ "fbuge,pn $\x03, $\x01\0" + /* 709 */ "fble,pn $\x03, $\x01\0" + /* 724 */ "fbule,pn $\x03, $\x01\0" + /* 740 */ "fbo,pn $\x03, $\x01\0" + /* 754 */ "ba,a,pn %icc, $\x01\0" + /* 771 */ "bn,a,pn %icc, $\x01\0" + /* 788 */ "bne,a,pn %icc, $\x01\0" + /* 806 */ "be,a,pn %icc, $\x01\0" + /* 823 */ "bg,a,pn %icc, $\x01\0" + /* 840 */ "ble,a,pn %icc, $\x01\0" + /* 858 */ "bge,a,pn %icc, $\x01\0" + /* 876 */ "bl,a,pn %icc, $\x01\0" + /* 893 */ "bgu,a,pn %icc, $\x01\0" + /* 911 */ "bleu,a,pn %icc, $\x01\0" + /* 930 */ "bcc,a,pn %icc, $\x01\0" + /* 948 */ "bcs,a,pn %icc, $\x01\0" + /* 966 */ "bpos,a,pn %icc, $\x01\0" + /* 985 */ "bneg,a,pn %icc, $\x01\0" + /* 1004 */ "bvc,a,pn %icc, $\x01\0" + /* 1022 */ "bvs,a,pn %icc, $\x01\0" + /* 1040 */ "ba,pn %icc, $\x01\0" + /* 1055 */ "bn,pn %icc, $\x01\0" + /* 1070 */ "bne,pn %icc, $\x01\0" + /* 1086 */ "be,pn %icc, $\x01\0" + /* 1101 */ "bg,pn %icc, $\x01\0" + /* 1116 */ "ble,pn %icc, $\x01\0" + /* 1132 */ "bge,pn %icc, $\x01\0" + /* 1148 */ "bl,pn %icc, $\x01\0" + /* 1163 */ "bgu,pn %icc, $\x01\0" + /* 1179 */ "bleu,pn %icc, $\x01\0" + /* 1196 */ "bcc,pn %icc, $\x01\0" + /* 1212 */ "bcs,pn %icc, $\x01\0" + /* 1228 */ "bpos,pn %icc, $\x01\0" + /* 1245 */ "bneg,pn %icc, $\x01\0" + /* 1262 */ "bvc,pn %icc, $\x01\0" + /* 1278 */ "bvs,pn %icc, $\x01\0" + /* 1294 */ "ba,a,pn %xcc, $\x01\0" + /* 1311 */ "bn,a,pn %xcc, $\x01\0" + /* 1328 */ "bne,a,pn %xcc, $\x01\0" + /* 1346 */ "be,a,pn %xcc, $\x01\0" + /* 1363 */ "bg,a,pn %xcc, $\x01\0" + /* 1380 */ "ble,a,pn %xcc, $\x01\0" + /* 1398 */ "bge,a,pn %xcc, $\x01\0" + /* 1416 */ "bl,a,pn %xcc, $\x01\0" + /* 1433 */ "bgu,a,pn %xcc, $\x01\0" + /* 1451 */ "bleu,a,pn %xcc, $\x01\0" + /* 1470 */ "bcc,a,pn %xcc, $\x01\0" + /* 1488 */ "bcs,a,pn %xcc, $\x01\0" + /* 1506 */ "bpos,a,pn %xcc, $\x01\0" + /* 1525 */ "bneg,a,pn %xcc, $\x01\0" + /* 1544 */ "bvc,a,pn %xcc, $\x01\0" + /* 1562 */ "bvs,a,pn %xcc, $\x01\0" + /* 1580 */ "ba,pn %xcc, $\x01\0" + /* 1595 */ "bn,pn %xcc, $\x01\0" + /* 1610 */ "bne,pn %xcc, $\x01\0" + /* 1626 */ "be,pn %xcc, $\x01\0" + /* 1641 */ "bg,pn %xcc, $\x01\0" + /* 1656 */ "ble,pn %xcc, $\x01\0" + /* 1672 */ "bge,pn %xcc, $\x01\0" + /* 1688 */ "bl,pn %xcc, $\x01\0" + /* 1703 */ "bgu,pn %xcc, $\x01\0" + /* 1719 */ "bleu,pn %xcc, $\x01\0" + /* 1736 */ "bcc,pn %xcc, $\x01\0" + /* 1752 */ "bcs,pn %xcc, $\x01\0" + /* 1768 */ "bpos,pn %xcc, $\x01\0" + /* 1785 */ "bneg,pn %xcc, $\x01\0" + /* 1802 */ "bvc,pn %xcc, $\x01\0" + /* 1818 */ "bvs,pn %xcc, $\x01\0" + /* 1834 */ "fmovda %icc, $\x02, $\x01\0" + /* 1854 */ "fmovdn %icc, $\x02, $\x01\0" + /* 1874 */ "fmovdne %icc, $\x02, $\x01\0" + /* 1895 */ "fmovde %icc, $\x02, $\x01\0" + /* 1915 */ "fmovdg %icc, $\x02, $\x01\0" + /* 1935 */ "fmovdle %icc, $\x02, $\x01\0" + /* 1956 */ "fmovdge %icc, $\x02, $\x01\0" + /* 1977 */ "fmovdl %icc, $\x02, $\x01\0" + /* 1997 */ "fmovdgu %icc, $\x02, $\x01\0" + /* 2018 */ "fmovdleu %icc, $\x02, $\x01\0" + /* 2040 */ "fmovdcc %icc, $\x02, $\x01\0" + /* 2061 */ "fmovdcs %icc, $\x02, $\x01\0" + /* 2082 */ "fmovdpos %icc, $\x02, $\x01\0" + /* 2104 */ "fmovdneg %icc, $\x02, $\x01\0" + /* 2126 */ "fmovdvc %icc, $\x02, $\x01\0" + /* 2147 */ "fmovdvs %icc, $\x02, $\x01\0" + /* 2168 */ "fmovda %xcc, $\x02, $\x01\0" + /* 2188 */ "fmovdn %xcc, $\x02, $\x01\0" + /* 2208 */ "fmovdne %xcc, $\x02, $\x01\0" + /* 2229 */ "fmovde %xcc, $\x02, $\x01\0" + /* 2249 */ "fmovdg %xcc, $\x02, $\x01\0" + /* 2269 */ "fmovdle %xcc, $\x02, $\x01\0" + /* 2290 */ "fmovdge %xcc, $\x02, $\x01\0" + /* 2311 */ "fmovdl %xcc, $\x02, $\x01\0" + /* 2331 */ "fmovdgu %xcc, $\x02, $\x01\0" + /* 2352 */ "fmovdleu %xcc, $\x02, $\x01\0" + /* 2374 */ "fmovdcc %xcc, $\x02, $\x01\0" + /* 2395 */ "fmovdcs %xcc, $\x02, $\x01\0" + /* 2416 */ "fmovdpos %xcc, $\x02, $\x01\0" + /* 2438 */ "fmovdneg %xcc, $\x02, $\x01\0" + /* 2460 */ "fmovdvc %xcc, $\x02, $\x01\0" + /* 2481 */ "fmovdvs %xcc, $\x02, $\x01\0" + /* 2502 */ "fmovqa %icc, $\x02, $\x01\0" + /* 2522 */ "fmovqn %icc, $\x02, $\x01\0" + /* 2542 */ "fmovqne %icc, $\x02, $\x01\0" + /* 2563 */ "fmovqe %icc, $\x02, $\x01\0" + /* 2583 */ "fmovqg %icc, $\x02, $\x01\0" + /* 2603 */ "fmovqle %icc, $\x02, $\x01\0" + /* 2624 */ "fmovqge %icc, $\x02, $\x01\0" + /* 2645 */ "fmovql %icc, $\x02, $\x01\0" + /* 2665 */ "fmovqgu %icc, $\x02, $\x01\0" + /* 2686 */ "fmovqleu %icc, $\x02, $\x01\0" + /* 2708 */ "fmovqcc %icc, $\x02, $\x01\0" + /* 2729 */ "fmovqcs %icc, $\x02, $\x01\0" + /* 2750 */ "fmovqpos %icc, $\x02, $\x01\0" + /* 2772 */ "fmovqneg %icc, $\x02, $\x01\0" + /* 2794 */ "fmovqvc %icc, $\x02, $\x01\0" + /* 2815 */ "fmovqvs %icc, $\x02, $\x01\0" + /* 2836 */ "fmovqa %xcc, $\x02, $\x01\0" + /* 2856 */ "fmovqn %xcc, $\x02, $\x01\0" + /* 2876 */ "fmovqne %xcc, $\x02, $\x01\0" + /* 2897 */ "fmovqe %xcc, $\x02, $\x01\0" + /* 2917 */ "fmovqg %xcc, $\x02, $\x01\0" + /* 2937 */ "fmovqle %xcc, $\x02, $\x01\0" + /* 2958 */ "fmovqge %xcc, $\x02, $\x01\0" + /* 2979 */ "fmovql %xcc, $\x02, $\x01\0" + /* 2999 */ "fmovqgu %xcc, $\x02, $\x01\0" + /* 3020 */ "fmovqleu %xcc, $\x02, $\x01\0" + /* 3042 */ "fmovqcc %xcc, $\x02, $\x01\0" + /* 3063 */ "fmovqcs %xcc, $\x02, $\x01\0" + /* 3084 */ "fmovqpos %xcc, $\x02, $\x01\0" + /* 3106 */ "fmovqneg %xcc, $\x02, $\x01\0" + /* 3128 */ "fmovqvc %xcc, $\x02, $\x01\0" + /* 3149 */ "fmovqvs %xcc, $\x02, $\x01\0" + /* 3170 */ "fmovsa %icc, $\x02, $\x01\0" + /* 3190 */ "fmovsn %icc, $\x02, $\x01\0" + /* 3210 */ "fmovsne %icc, $\x02, $\x01\0" + /* 3231 */ "fmovse %icc, $\x02, $\x01\0" + /* 3251 */ "fmovsg %icc, $\x02, $\x01\0" + /* 3271 */ "fmovsle %icc, $\x02, $\x01\0" + /* 3292 */ "fmovsge %icc, $\x02, $\x01\0" + /* 3313 */ "fmovsl %icc, $\x02, $\x01\0" + /* 3333 */ "fmovsgu %icc, $\x02, $\x01\0" + /* 3354 */ "fmovsleu %icc, $\x02, $\x01\0" + /* 3376 */ "fmovscc %icc, $\x02, $\x01\0" + /* 3397 */ "fmovscs %icc, $\x02, $\x01\0" + /* 3418 */ "fmovspos %icc, $\x02, $\x01\0" + /* 3440 */ "fmovsneg %icc, $\x02, $\x01\0" + /* 3462 */ "fmovsvc %icc, $\x02, $\x01\0" + /* 3483 */ "fmovsvs %icc, $\x02, $\x01\0" + /* 3504 */ "fmovsa %xcc, $\x02, $\x01\0" + /* 3524 */ "fmovsn %xcc, $\x02, $\x01\0" + /* 3544 */ "fmovsne %xcc, $\x02, $\x01\0" + /* 3565 */ "fmovse %xcc, $\x02, $\x01\0" + /* 3585 */ "fmovsg %xcc, $\x02, $\x01\0" + /* 3605 */ "fmovsle %xcc, $\x02, $\x01\0" + /* 3626 */ "fmovsge %xcc, $\x02, $\x01\0" + /* 3647 */ "fmovsl %xcc, $\x02, $\x01\0" + /* 3667 */ "fmovsgu %xcc, $\x02, $\x01\0" + /* 3688 */ "fmovsleu %xcc, $\x02, $\x01\0" + /* 3710 */ "fmovscc %xcc, $\x02, $\x01\0" + /* 3731 */ "fmovscs %xcc, $\x02, $\x01\0" + /* 3752 */ "fmovspos %xcc, $\x02, $\x01\0" + /* 3774 */ "fmovsneg %xcc, $\x02, $\x01\0" + /* 3796 */ "fmovsvc %xcc, $\x02, $\x01\0" + /* 3817 */ "fmovsvs %xcc, $\x02, $\x01\0" + /* 3838 */ "mova %icc, $\x02, $\x01\0" + /* 3856 */ "movn %icc, $\x02, $\x01\0" + /* 3874 */ "movne %icc, $\x02, $\x01\0" + /* 3893 */ "move %icc, $\x02, $\x01\0" + /* 3911 */ "movg %icc, $\x02, $\x01\0" + /* 3929 */ "movle %icc, $\x02, $\x01\0" + /* 3948 */ "movge %icc, $\x02, $\x01\0" + /* 3967 */ "movl %icc, $\x02, $\x01\0" + /* 3985 */ "movgu %icc, $\x02, $\x01\0" + /* 4004 */ "movleu %icc, $\x02, $\x01\0" + /* 4024 */ "movcc %icc, $\x02, $\x01\0" + /* 4043 */ "movcs %icc, $\x02, $\x01\0" + /* 4062 */ "movpos %icc, $\x02, $\x01\0" + /* 4082 */ "movneg %icc, $\x02, $\x01\0" + /* 4102 */ "movvc %icc, $\x02, $\x01\0" + /* 4121 */ "movvs %icc, $\x02, $\x01\0" + /* 4140 */ "mova %xcc, $\x02, $\x01\0" + /* 4158 */ "movn %xcc, $\x02, $\x01\0" + /* 4176 */ "movne %xcc, $\x02, $\x01\0" + /* 4195 */ "move %xcc, $\x02, $\x01\0" + /* 4213 */ "movg %xcc, $\x02, $\x01\0" + /* 4231 */ "movle %xcc, $\x02, $\x01\0" + /* 4250 */ "movge %xcc, $\x02, $\x01\0" + /* 4269 */ "movl %xcc, $\x02, $\x01\0" + /* 4287 */ "movgu %xcc, $\x02, $\x01\0" + /* 4306 */ "movleu %xcc, $\x02, $\x01\0" + /* 4326 */ "movcc %xcc, $\x02, $\x01\0" + /* 4345 */ "movcs %xcc, $\x02, $\x01\0" + /* 4364 */ "movpos %xcc, $\x02, $\x01\0" + /* 4384 */ "movneg %xcc, $\x02, $\x01\0" + /* 4404 */ "movvc %xcc, $\x02, $\x01\0" + /* 4423 */ "movvs %xcc, $\x02, $\x01\0" + /* 4442 */ "tst $\x02\0" + /* 4449 */ "mov $\x03, $\x01\0" + /* 4460 */ "restore\0" + /* 4468 */ "ret\0" + /* 4472 */ "retl\0" + /* 4477 */ "save\0" + /* 4482 */ "ta %icc, $\x02\0" + /* 4494 */ "ta %icc, $\x01 + $\x02\0" + /* 4511 */ "tn %icc, $\x02\0" + /* 4523 */ "tn %icc, $\x01 + $\x02\0" + /* 4540 */ "tne %icc, $\x02\0" + /* 4553 */ "tne %icc, $\x01 + $\x02\0" + /* 4571 */ "te %icc, $\x02\0" + /* 4583 */ "te %icc, $\x01 + $\x02\0" + /* 4600 */ "tg %icc, $\x02\0" + /* 4612 */ "tg %icc, $\x01 + $\x02\0" + /* 4629 */ "tle %icc, $\x02\0" + /* 4642 */ "tle %icc, $\x01 + $\x02\0" + /* 4660 */ "tge %icc, $\x02\0" + /* 4673 */ "tge %icc, $\x01 + $\x02\0" + /* 4691 */ "tl %icc, $\x02\0" + /* 4703 */ "tl %icc, $\x01 + $\x02\0" + /* 4720 */ "tgu %icc, $\x02\0" + /* 4733 */ "tgu %icc, $\x01 + $\x02\0" + /* 4751 */ "tleu %icc, $\x02\0" + /* 4765 */ "tleu %icc, $\x01 + $\x02\0" + /* 4784 */ "tcc %icc, $\x02\0" + /* 4797 */ "tcc %icc, $\x01 + $\x02\0" + /* 4815 */ "tcs %icc, $\x02\0" + /* 4828 */ "tcs %icc, $\x01 + $\x02\0" + /* 4846 */ "tpos %icc, $\x02\0" + /* 4860 */ "tpos %icc, $\x01 + $\x02\0" + /* 4879 */ "tneg %icc, $\x02\0" + /* 4893 */ "tneg %icc, $\x01 + $\x02\0" + /* 4912 */ "tvc %icc, $\x02\0" + /* 4925 */ "tvc %icc, $\x01 + $\x02\0" + /* 4943 */ "tvs %icc, $\x02\0" + /* 4956 */ "tvs %icc, $\x01 + $\x02\0" + /* 4974 */ "ta $\x02\0" + /* 4980 */ "ta $\x01 + $\x02\0" + /* 4991 */ "tn $\x02\0" + /* 4997 */ "tn $\x01 + $\x02\0" + /* 5008 */ "tne $\x02\0" + /* 5015 */ "tne $\x01 + $\x02\0" + /* 5027 */ "te $\x02\0" + /* 5033 */ "te $\x01 + $\x02\0" + /* 5044 */ "tg $\x02\0" + /* 5050 */ "tg $\x01 + $\x02\0" + /* 5061 */ "tle $\x02\0" + /* 5068 */ "tle $\x01 + $\x02\0" + /* 5080 */ "tge $\x02\0" + /* 5087 */ "tge $\x01 + $\x02\0" + /* 5099 */ "tl $\x02\0" + /* 5105 */ "tl $\x01 + $\x02\0" + /* 5116 */ "tgu $\x02\0" + /* 5123 */ "tgu $\x01 + $\x02\0" + /* 5135 */ "tleu $\x02\0" + /* 5143 */ "tleu $\x01 + $\x02\0" + /* 5156 */ "tcc $\x02\0" + /* 5163 */ "tcc $\x01 + $\x02\0" + /* 5175 */ "tcs $\x02\0" + /* 5182 */ "tcs $\x01 + $\x02\0" + /* 5194 */ "tpos $\x02\0" + /* 5202 */ "tpos $\x01 + $\x02\0" + /* 5215 */ "tneg $\x02\0" + /* 5223 */ "tneg $\x01 + $\x02\0" + /* 5236 */ "tvc $\x02\0" + /* 5243 */ "tvc $\x01 + $\x02\0" + /* 5255 */ "tvs $\x02\0" + /* 5262 */ "tvs $\x01 + $\x02\0" + /* 5274 */ "ta %xcc, $\x02\0" + /* 5286 */ "ta %xcc, $\x01 + $\x02\0" + /* 5303 */ "tn %xcc, $\x02\0" + /* 5315 */ "tn %xcc, $\x01 + $\x02\0" + /* 5332 */ "tne %xcc, $\x02\0" + /* 5345 */ "tne %xcc, $\x01 + $\x02\0" + /* 5363 */ "te %xcc, $\x02\0" + /* 5375 */ "te %xcc, $\x01 + $\x02\0" + /* 5392 */ "tg %xcc, $\x02\0" + /* 5404 */ "tg %xcc, $\x01 + $\x02\0" + /* 5421 */ "tle %xcc, $\x02\0" + /* 5434 */ "tle %xcc, $\x01 + $\x02\0" + /* 5452 */ "tge %xcc, $\x02\0" + /* 5465 */ "tge %xcc, $\x01 + $\x02\0" + /* 5483 */ "tl %xcc, $\x02\0" + /* 5495 */ "tl %xcc, $\x01 + $\x02\0" + /* 5512 */ "tgu %xcc, $\x02\0" + /* 5525 */ "tgu %xcc, $\x01 + $\x02\0" + /* 5543 */ "tleu %xcc, $\x02\0" + /* 5557 */ "tleu %xcc, $\x01 + $\x02\0" + /* 5576 */ "tcc %xcc, $\x02\0" + /* 5589 */ "tcc %xcc, $\x01 + $\x02\0" + /* 5607 */ "tcs %xcc, $\x02\0" + /* 5620 */ "tcs %xcc, $\x01 + $\x02\0" + /* 5638 */ "tpos %xcc, $\x02\0" + /* 5652 */ "tpos %xcc, $\x01 + $\x02\0" + /* 5671 */ "tneg %xcc, $\x02\0" + /* 5685 */ "tneg %xcc, $\x01 + $\x02\0" + /* 5704 */ "tvc %xcc, $\x02\0" + /* 5717 */ "tvc %xcc, $\x01 + $\x02\0" + /* 5735 */ "tvs %xcc, $\x02\0" + /* 5748 */ "tvs %xcc, $\x01 + $\x02\0" + /* 5766 */ "fcmpd $\x02, $\x03\0" + /* 5779 */ "fcmped $\x02, $\x03\0" + /* 5793 */ "fcmpeq $\x02, $\x03\0" + /* 5807 */ "fcmpes $\x02, $\x03\0" + /* 5821 */ "fcmpq $\x02, $\x03\0" + /* 5834 */ "fcmps $\x02, $\x03\0" + /* 5847 */ "fmovda $\x02, $\x03, $\x01\0" + /* 5865 */ "fmovdn $\x02, $\x03, $\x01\0" + /* 5883 */ "fmovdu $\x02, $\x03, $\x01\0" + /* 5901 */ "fmovdg $\x02, $\x03, $\x01\0" + /* 5919 */ "fmovdug $\x02, $\x03, $\x01\0" + /* 5938 */ "fmovdl $\x02, $\x03, $\x01\0" + /* 5956 */ "fmovdul $\x02, $\x03, $\x01\0" + /* 5975 */ "fmovdlg $\x02, $\x03, $\x01\0" + /* 5994 */ "fmovdne $\x02, $\x03, $\x01\0" + /* 6013 */ "fmovde $\x02, $\x03, $\x01\0" + /* 6031 */ "fmovdue $\x02, $\x03, $\x01\0" + /* 6050 */ "fmovdge $\x02, $\x03, $\x01\0" + /* 6069 */ "fmovduge $\x02, $\x03, $\x01\0" + /* 6089 */ "fmovdle $\x02, $\x03, $\x01\0" + /* 6108 */ "fmovdule $\x02, $\x03, $\x01\0" + /* 6128 */ "fmovdo $\x02, $\x03, $\x01\0" + /* 6146 */ "fmovqa $\x02, $\x03, $\x01\0" + /* 6164 */ "fmovqn $\x02, $\x03, $\x01\0" + /* 6182 */ "fmovqu $\x02, $\x03, $\x01\0" + /* 6200 */ "fmovqg $\x02, $\x03, $\x01\0" + /* 6218 */ "fmovqug $\x02, $\x03, $\x01\0" + /* 6237 */ "fmovql $\x02, $\x03, $\x01\0" + /* 6255 */ "fmovqul $\x02, $\x03, $\x01\0" + /* 6274 */ "fmovqlg $\x02, $\x03, $\x01\0" + /* 6293 */ "fmovqne $\x02, $\x03, $\x01\0" + /* 6312 */ "fmovqe $\x02, $\x03, $\x01\0" + /* 6330 */ "fmovque $\x02, $\x03, $\x01\0" + /* 6349 */ "fmovqge $\x02, $\x03, $\x01\0" + /* 6368 */ "fmovquge $\x02, $\x03, $\x01\0" + /* 6388 */ "fmovqle $\x02, $\x03, $\x01\0" + /* 6407 */ "fmovqule $\x02, $\x03, $\x01\0" + /* 6427 */ "fmovqo $\x02, $\x03, $\x01\0" + /* 6445 */ "fmovsa $\x02, $\x03, $\x01\0" + /* 6463 */ "fmovsn $\x02, $\x03, $\x01\0" + /* 6481 */ "fmovsu $\x02, $\x03, $\x01\0" + /* 6499 */ "fmovsg $\x02, $\x03, $\x01\0" + /* 6517 */ "fmovsug $\x02, $\x03, $\x01\0" + /* 6536 */ "fmovsl $\x02, $\x03, $\x01\0" + /* 6554 */ "fmovsul $\x02, $\x03, $\x01\0" + /* 6573 */ "fmovslg $\x02, $\x03, $\x01\0" + /* 6592 */ "fmovsne $\x02, $\x03, $\x01\0" + /* 6611 */ "fmovse $\x02, $\x03, $\x01\0" + /* 6629 */ "fmovsue $\x02, $\x03, $\x01\0" + /* 6648 */ "fmovsge $\x02, $\x03, $\x01\0" + /* 6667 */ "fmovsuge $\x02, $\x03, $\x01\0" + /* 6687 */ "fmovsle $\x02, $\x03, $\x01\0" + /* 6706 */ "fmovsule $\x02, $\x03, $\x01\0" + /* 6726 */ "fmovso $\x02, $\x03, $\x01\0" + /* 6744 */ "mova $\x02, $\x03, $\x01\0" + /* 6760 */ "movn $\x02, $\x03, $\x01\0" + /* 6776 */ "movu $\x02, $\x03, $\x01\0" + /* 6792 */ "movg $\x02, $\x03, $\x01\0" + /* 6808 */ "movug $\x02, $\x03, $\x01\0" + /* 6825 */ "movl $\x02, $\x03, $\x01\0" + /* 6841 */ "movul $\x02, $\x03, $\x01\0" + /* 6858 */ "movlg $\x02, $\x03, $\x01\0" + /* 6875 */ "movne $\x02, $\x03, $\x01\0" + /* 6892 */ "move $\x02, $\x03, $\x01\0" + /* 6908 */ "movue $\x02, $\x03, $\x01\0" + /* 6925 */ "movge $\x02, $\x03, $\x01\0" + /* 6942 */ "movuge $\x02, $\x03, $\x01\0" + /* 6960 */ "movle $\x02, $\x03, $\x01\0" + /* 6977 */ "movule $\x02, $\x03, $\x01\0" + /* 6995 */ "movo $\x02, $\x03, $\x01\0"}; + + const char *AsmString = MCInstPrinter_matchAliasPatterns( + MI, OpToPatterns, Patterns, Conds, AsmStrings, 42); + if (!AsmString) + return false; + + char *tmpString = cs_strdup(AsmString); + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, "\t"); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, *(tmpString + (I++))); + } + } while (AsmString[I] != '\0'); + } + + return tmpString; } -FieldFromInstruction(fieldFromInstruction_4, uint32_t) -DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) -DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { + llvm_unreachable("Unknown PrintMethod kind"); +} + +#endif // PRINT_ALIAS_INSTR +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo3[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo4[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo5[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo6[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo7[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo8[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo9[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo10[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo11[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo12[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo13[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo14[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo15[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo16[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo17[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo18[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo19[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo20[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo21[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo22[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo23[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo24[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo25[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo26[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo27[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo28[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo29[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo30[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo31[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo32[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo33[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo34[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo35[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo36[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo37[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo38[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo39[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo40[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo41[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo42[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo43[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo44[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo45[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo46[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo47[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo48[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo49[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo50[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo51[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo52[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo53[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo54[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_FCCRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo55[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo56[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo57[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo58[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo59[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo60[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo61[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo62[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo63[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo64[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo65[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo66[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo67[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo68[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo69[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo70[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo71[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo72[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo73[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo74[] = { + {SP_FCCRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo75[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo76[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo77[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo78[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo79[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo80[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo81[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo82[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo83[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo84[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo85[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo86[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo87[] = { + {SP_CoprocRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo88[] = { + {SP_CoprocRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo89[] = { + {SP_IntPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo90[] = { + {SP_CoprocPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo91[] = { + {SP_CoprocPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo92[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo93[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo94[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo95[] = { + {SP_IntPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo96[] = { + {SP_IntPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo97[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo98[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo99[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo100[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo101[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo102[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo103[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo104[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo105[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo106[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo107[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo108[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo109[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo110[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo111[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo112[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo113[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo114[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_ASRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo115[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo116[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_PRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo117[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo118[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_ASRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo119[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_ASRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo120[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo121[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo122[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo123[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_CoprocRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo124[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_CoprocRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo125[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_IntPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo126[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_CoprocPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo127[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_CoprocPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo128[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo129[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo130[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo131[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_IntPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo132[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_IntPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo133[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo134[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo135[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo136[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo137[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo138[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo139[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo140[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo141[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo142[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo143[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo144[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo145[] = { + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_I64RegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo146[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo147[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo148[] = { + {SP_FCCRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo149[] = { + {SP_FCCRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo150[] = { + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FCCRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_DFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo151[] = { + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FCCRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_QFPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo152[] = { + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FCCRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FPRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo153[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FCCRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo154[] = { + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_FCCRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo155[] = { + {SP_ASRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo156[] = { + {SP_ASRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo157[] = { + {SP_PRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo158[] = { + {SP_PRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SP_IntRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; + +extern const MCInstrDesc SparcInsts[] = { + {1, OperandInfo2}, // Inst #0 = PHI + {0, NULL}, // Inst #1 = INLINEASM + {0, NULL}, // Inst #2 = INLINEASM_BR + {1, OperandInfo3}, // Inst #3 = CFI_INSTRUCTION + {1, OperandInfo3}, // Inst #4 = EH_LABEL + {1, OperandInfo3}, // Inst #5 = GC_LABEL + {1, OperandInfo3}, // Inst #6 = ANNOTATION_LABEL + {0, NULL}, // Inst #7 = KILL + {3, OperandInfo4}, // Inst #8 = EXTRACT_SUBREG + {4, OperandInfo5}, // Inst #9 = INSERT_SUBREG + {1, OperandInfo2}, // Inst #10 = IMPLICIT_DEF + {4, OperandInfo6}, // Inst #11 = SUBREG_TO_REG + {3, OperandInfo4}, // Inst #12 = COPY_TO_REGCLASS + {0, NULL}, // Inst #13 = DBG_VALUE + {0, NULL}, // Inst #14 = DBG_VALUE_LIST + {0, NULL}, // Inst #15 = DBG_INSTR_REF + {0, NULL}, // Inst #16 = DBG_PHI + {1, OperandInfo2}, // Inst #17 = DBG_LABEL + {2, OperandInfo7}, // Inst #18 = REG_SEQUENCE + {2, OperandInfo7}, // Inst #19 = COPY + {0, NULL}, // Inst #20 = BUNDLE + {1, OperandInfo3}, // Inst #21 = LIFETIME_START + {1, OperandInfo3}, // Inst #22 = LIFETIME_END + {4, OperandInfo8}, // Inst #23 = PSEUDO_PROBE + {2, OperandInfo9}, // Inst #24 = ARITH_FENCE + {2, OperandInfo10}, // Inst #25 = STACKMAP + {0, NULL}, // Inst #26 = FENTRY_CALL + {6, OperandInfo11}, // Inst #27 = PATCHPOINT + {1, OperandInfo12}, // Inst #28 = LOAD_STACK_GUARD + {1, OperandInfo3}, // Inst #29 = PREALLOCATED_SETUP + {3, OperandInfo13}, // Inst #30 = PREALLOCATED_ARG + {0, NULL}, // Inst #31 = STATEPOINT + {2, OperandInfo14}, // Inst #32 = LOCAL_ESCAPE + {1, OperandInfo2}, // Inst #33 = FAULTING_OP + {0, NULL}, // Inst #34 = PATCHABLE_OP + {0, NULL}, // Inst #35 = PATCHABLE_FUNCTION_ENTER + {0, NULL}, // Inst #36 = PATCHABLE_RET + {0, NULL}, // Inst #37 = PATCHABLE_FUNCTION_EXIT + {0, NULL}, // Inst #38 = PATCHABLE_TAIL_CALL + {2, OperandInfo15}, // Inst #39 = PATCHABLE_EVENT_CALL + {3, OperandInfo16}, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + {0, NULL}, // Inst #41 = ICALL_BRANCH_FUNNEL + {3, OperandInfo17}, // Inst #42 = G_ASSERT_SEXT + {3, OperandInfo17}, // Inst #43 = G_ASSERT_ZEXT + {3, OperandInfo18}, // Inst #44 = G_ADD + {3, OperandInfo18}, // Inst #45 = G_SUB + {3, OperandInfo18}, // Inst #46 = G_MUL + {3, OperandInfo18}, // Inst #47 = G_SDIV + {3, OperandInfo18}, // Inst #48 = G_UDIV + {3, OperandInfo18}, // Inst #49 = G_SREM + {3, OperandInfo18}, // Inst #50 = G_UREM + {4, OperandInfo19}, // Inst #51 = G_SDIVREM + {4, OperandInfo19}, // Inst #52 = G_UDIVREM + {3, OperandInfo18}, // Inst #53 = G_AND + {3, OperandInfo18}, // Inst #54 = G_OR + {3, OperandInfo18}, // Inst #55 = G_XOR + {1, OperandInfo20}, // Inst #56 = G_IMPLICIT_DEF + {1, OperandInfo20}, // Inst #57 = G_PHI + {2, OperandInfo21}, // Inst #58 = G_FRAME_INDEX + {2, OperandInfo21}, // Inst #59 = G_GLOBAL_VALUE + {3, OperandInfo22}, // Inst #60 = G_EXTRACT + {2, OperandInfo23}, // Inst #61 = G_UNMERGE_VALUES + {4, OperandInfo24}, // Inst #62 = G_INSERT + {2, OperandInfo23}, // Inst #63 = G_MERGE_VALUES + {2, OperandInfo23}, // Inst #64 = G_BUILD_VECTOR + {2, OperandInfo23}, // Inst #65 = G_BUILD_VECTOR_TRUNC + {2, OperandInfo23}, // Inst #66 = G_CONCAT_VECTORS + {2, OperandInfo23}, // Inst #67 = G_PTRTOINT + {2, OperandInfo23}, // Inst #68 = G_INTTOPTR + {2, OperandInfo23}, // Inst #69 = G_BITCAST + {2, OperandInfo25}, // Inst #70 = G_FREEZE + {2, OperandInfo25}, // Inst #71 = G_INTRINSIC_TRUNC + {2, OperandInfo25}, // Inst #72 = G_INTRINSIC_ROUND + {2, OperandInfo23}, // Inst #73 = G_INTRINSIC_LRINT + {2, OperandInfo25}, // Inst #74 = G_INTRINSIC_ROUNDEVEN + {1, OperandInfo20}, // Inst #75 = G_READCYCLECOUNTER + {2, OperandInfo23}, // Inst #76 = G_LOAD + {2, OperandInfo23}, // Inst #77 = G_SEXTLOAD + {2, OperandInfo23}, // Inst #78 = G_ZEXTLOAD + {5, OperandInfo26}, // Inst #79 = G_INDEXED_LOAD + {5, OperandInfo26}, // Inst #80 = G_INDEXED_SEXTLOAD + {5, OperandInfo26}, // Inst #81 = G_INDEXED_ZEXTLOAD + {2, OperandInfo23}, // Inst #82 = G_STORE + {5, OperandInfo27}, // Inst #83 = G_INDEXED_STORE + {5, OperandInfo28}, // Inst #84 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + {4, OperandInfo29}, // Inst #85 = G_ATOMIC_CMPXCHG + {3, OperandInfo30}, // Inst #86 = G_ATOMICRMW_XCHG + {3, OperandInfo30}, // Inst #87 = G_ATOMICRMW_ADD + {3, OperandInfo30}, // Inst #88 = G_ATOMICRMW_SUB + {3, OperandInfo30}, // Inst #89 = G_ATOMICRMW_AND + {3, OperandInfo30}, // Inst #90 = G_ATOMICRMW_NAND + {3, OperandInfo30}, // Inst #91 = G_ATOMICRMW_OR + {3, OperandInfo30}, // Inst #92 = G_ATOMICRMW_XOR + {3, OperandInfo30}, // Inst #93 = G_ATOMICRMW_MAX + {3, OperandInfo30}, // Inst #94 = G_ATOMICRMW_MIN + {3, OperandInfo30}, // Inst #95 = G_ATOMICRMW_UMAX + {3, OperandInfo30}, // Inst #96 = G_ATOMICRMW_UMIN + {3, OperandInfo30}, // Inst #97 = G_ATOMICRMW_FADD + {3, OperandInfo30}, // Inst #98 = G_ATOMICRMW_FSUB + {2, OperandInfo10}, // Inst #99 = G_FENCE + {2, OperandInfo21}, // Inst #100 = G_BRCOND + {1, OperandInfo20}, // Inst #101 = G_BRINDIRECT + {1, OperandInfo2}, // Inst #102 = G_INTRINSIC + {1, OperandInfo2}, // Inst #103 = G_INTRINSIC_W_SIDE_EFFECTS + {2, OperandInfo23}, // Inst #104 = G_ANYEXT + {2, OperandInfo23}, // Inst #105 = G_TRUNC + {2, OperandInfo21}, // Inst #106 = G_CONSTANT + {2, OperandInfo21}, // Inst #107 = G_FCONSTANT + {1, OperandInfo20}, // Inst #108 = G_VASTART + {3, OperandInfo31}, // Inst #109 = G_VAARG + {2, OperandInfo23}, // Inst #110 = G_SEXT + {3, OperandInfo17}, // Inst #111 = G_SEXT_INREG + {2, OperandInfo23}, // Inst #112 = G_ZEXT + {3, OperandInfo32}, // Inst #113 = G_SHL + {3, OperandInfo32}, // Inst #114 = G_LSHR + {3, OperandInfo32}, // Inst #115 = G_ASHR + {4, OperandInfo33}, // Inst #116 = G_FSHL + {4, OperandInfo33}, // Inst #117 = G_FSHR + {3, OperandInfo32}, // Inst #118 = G_ROTR + {3, OperandInfo32}, // Inst #119 = G_ROTL + {4, OperandInfo34}, // Inst #120 = G_ICMP + {4, OperandInfo34}, // Inst #121 = G_FCMP + {4, OperandInfo29}, // Inst #122 = G_SELECT + {4, OperandInfo29}, // Inst #123 = G_UADDO + {5, OperandInfo35}, // Inst #124 = G_UADDE + {4, OperandInfo29}, // Inst #125 = G_USUBO + {5, OperandInfo35}, // Inst #126 = G_USUBE + {4, OperandInfo29}, // Inst #127 = G_SADDO + {5, OperandInfo35}, // Inst #128 = G_SADDE + {4, OperandInfo29}, // Inst #129 = G_SSUBO + {5, OperandInfo35}, // Inst #130 = G_SSUBE + {4, OperandInfo29}, // Inst #131 = G_UMULO + {4, OperandInfo29}, // Inst #132 = G_SMULO + {3, OperandInfo18}, // Inst #133 = G_UMULH + {3, OperandInfo18}, // Inst #134 = G_SMULH + {3, OperandInfo18}, // Inst #135 = G_UADDSAT + {3, OperandInfo18}, // Inst #136 = G_SADDSAT + {3, OperandInfo18}, // Inst #137 = G_USUBSAT + {3, OperandInfo18}, // Inst #138 = G_SSUBSAT + {3, OperandInfo32}, // Inst #139 = G_USHLSAT + {3, OperandInfo32}, // Inst #140 = G_SSHLSAT + {4, OperandInfo36}, // Inst #141 = G_SMULFIX + {4, OperandInfo36}, // Inst #142 = G_UMULFIX + {4, OperandInfo36}, // Inst #143 = G_SMULFIXSAT + {4, OperandInfo36}, // Inst #144 = G_UMULFIXSAT + {4, OperandInfo36}, // Inst #145 = G_SDIVFIX + {4, OperandInfo36}, // Inst #146 = G_UDIVFIX + {4, OperandInfo36}, // Inst #147 = G_SDIVFIXSAT + {4, OperandInfo36}, // Inst #148 = G_UDIVFIXSAT + {3, OperandInfo18}, // Inst #149 = G_FADD + {3, OperandInfo18}, // Inst #150 = G_FSUB + {3, OperandInfo18}, // Inst #151 = G_FMUL + {4, OperandInfo19}, // Inst #152 = G_FMA + {4, OperandInfo19}, // Inst #153 = G_FMAD + {3, OperandInfo18}, // Inst #154 = G_FDIV + {3, OperandInfo18}, // Inst #155 = G_FREM + {3, OperandInfo18}, // Inst #156 = G_FPOW + {3, OperandInfo32}, // Inst #157 = G_FPOWI + {2, OperandInfo25}, // Inst #158 = G_FEXP + {2, OperandInfo25}, // Inst #159 = G_FEXP2 + {2, OperandInfo25}, // Inst #160 = G_FLOG + {2, OperandInfo25}, // Inst #161 = G_FLOG2 + {2, OperandInfo25}, // Inst #162 = G_FLOG10 + {2, OperandInfo25}, // Inst #163 = G_FNEG + {2, OperandInfo23}, // Inst #164 = G_FPEXT + {2, OperandInfo23}, // Inst #165 = G_FPTRUNC + {2, OperandInfo23}, // Inst #166 = G_FPTOSI + {2, OperandInfo23}, // Inst #167 = G_FPTOUI + {2, OperandInfo23}, // Inst #168 = G_SITOFP + {2, OperandInfo23}, // Inst #169 = G_UITOFP + {2, OperandInfo25}, // Inst #170 = G_FABS + {3, OperandInfo32}, // Inst #171 = G_FCOPYSIGN + {2, OperandInfo25}, // Inst #172 = G_FCANONICALIZE + {3, OperandInfo18}, // Inst #173 = G_FMINNUM + {3, OperandInfo18}, // Inst #174 = G_FMAXNUM + {3, OperandInfo18}, // Inst #175 = G_FMINNUM_IEEE + {3, OperandInfo18}, // Inst #176 = G_FMAXNUM_IEEE + {3, OperandInfo18}, // Inst #177 = G_FMINIMUM + {3, OperandInfo18}, // Inst #178 = G_FMAXIMUM + {3, OperandInfo32}, // Inst #179 = G_PTR_ADD + {3, OperandInfo32}, // Inst #180 = G_PTRMASK + {3, OperandInfo18}, // Inst #181 = G_SMIN + {3, OperandInfo18}, // Inst #182 = G_SMAX + {3, OperandInfo18}, // Inst #183 = G_UMIN + {3, OperandInfo18}, // Inst #184 = G_UMAX + {2, OperandInfo25}, // Inst #185 = G_ABS + {2, OperandInfo23}, // Inst #186 = G_LROUND + {2, OperandInfo23}, // Inst #187 = G_LLROUND + {1, OperandInfo2}, // Inst #188 = G_BR + {3, OperandInfo37}, // Inst #189 = G_BRJT + {4, OperandInfo38}, // Inst #190 = G_INSERT_VECTOR_ELT + {3, OperandInfo39}, // Inst #191 = G_EXTRACT_VECTOR_ELT + {4, OperandInfo40}, // Inst #192 = G_SHUFFLE_VECTOR + {2, OperandInfo23}, // Inst #193 = G_CTTZ + {2, OperandInfo23}, // Inst #194 = G_CTTZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #195 = G_CTLZ + {2, OperandInfo23}, // Inst #196 = G_CTLZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #197 = G_CTPOP + {2, OperandInfo25}, // Inst #198 = G_BSWAP + {2, OperandInfo25}, // Inst #199 = G_BITREVERSE + {2, OperandInfo25}, // Inst #200 = G_FCEIL + {2, OperandInfo25}, // Inst #201 = G_FCOS + {2, OperandInfo25}, // Inst #202 = G_FSIN + {2, OperandInfo25}, // Inst #203 = G_FSQRT + {2, OperandInfo25}, // Inst #204 = G_FFLOOR + {2, OperandInfo25}, // Inst #205 = G_FRINT + {2, OperandInfo25}, // Inst #206 = G_FNEARBYINT + {2, OperandInfo23}, // Inst #207 = G_ADDRSPACE_CAST + {2, OperandInfo21}, // Inst #208 = G_BLOCK_ADDR + {2, OperandInfo21}, // Inst #209 = G_JUMP_TABLE + {3, OperandInfo22}, // Inst #210 = G_DYN_STACKALLOC + {3, OperandInfo18}, // Inst #211 = G_STRICT_FADD + {3, OperandInfo18}, // Inst #212 = G_STRICT_FSUB + {3, OperandInfo18}, // Inst #213 = G_STRICT_FMUL + {3, OperandInfo18}, // Inst #214 = G_STRICT_FDIV + {3, OperandInfo18}, // Inst #215 = G_STRICT_FREM + {4, OperandInfo19}, // Inst #216 = G_STRICT_FMA + {2, OperandInfo25}, // Inst #217 = G_STRICT_FSQRT + {2, OperandInfo21}, // Inst #218 = G_READ_REGISTER + {2, OperandInfo41}, // Inst #219 = G_WRITE_REGISTER + {4, OperandInfo42}, // Inst #220 = G_MEMCPY + {3, OperandInfo39}, // Inst #221 = G_MEMCPY_INLINE + {4, OperandInfo42}, // Inst #222 = G_MEMMOVE + {4, OperandInfo42}, // Inst #223 = G_MEMSET + {3, OperandInfo22}, // Inst #224 = G_BZERO + {3, OperandInfo39}, // Inst #225 = G_VECREDUCE_SEQ_FADD + {3, OperandInfo39}, // Inst #226 = G_VECREDUCE_SEQ_FMUL + {2, OperandInfo23}, // Inst #227 = G_VECREDUCE_FADD + {2, OperandInfo23}, // Inst #228 = G_VECREDUCE_FMUL + {2, OperandInfo23}, // Inst #229 = G_VECREDUCE_FMAX + {2, OperandInfo23}, // Inst #230 = G_VECREDUCE_FMIN + {2, OperandInfo23}, // Inst #231 = G_VECREDUCE_ADD + {2, OperandInfo23}, // Inst #232 = G_VECREDUCE_MUL + {2, OperandInfo23}, // Inst #233 = G_VECREDUCE_AND + {2, OperandInfo23}, // Inst #234 = G_VECREDUCE_OR + {2, OperandInfo23}, // Inst #235 = G_VECREDUCE_XOR + {2, OperandInfo23}, // Inst #236 = G_VECREDUCE_SMAX + {2, OperandInfo23}, // Inst #237 = G_VECREDUCE_SMIN + {2, OperandInfo23}, // Inst #238 = G_VECREDUCE_UMAX + {2, OperandInfo23}, // Inst #239 = G_VECREDUCE_UMIN + {4, OperandInfo43}, // Inst #240 = G_SBFX + {4, OperandInfo43}, // Inst #241 = G_UBFX + {2, OperandInfo10}, // Inst #242 = ADJCALLSTACKDOWN + {2, OperandInfo10}, // Inst #243 = ADJCALLSTACKUP + {1, OperandInfo2}, // Inst #244 = GETPCX + {4, OperandInfo44}, // Inst #245 = SELECT_CC_DFP_FCC + {4, OperandInfo44}, // Inst #246 = SELECT_CC_DFP_ICC + {4, OperandInfo45}, // Inst #247 = SELECT_CC_FP_FCC + {4, OperandInfo45}, // Inst #248 = SELECT_CC_FP_ICC + {4, OperandInfo46}, // Inst #249 = SELECT_CC_Int_FCC + {4, OperandInfo46}, // Inst #250 = SELECT_CC_Int_ICC + {4, OperandInfo47}, // Inst #251 = SELECT_CC_QFP_FCC + {4, OperandInfo47}, // Inst #252 = SELECT_CC_QFP_ICC + {2, OperandInfo48}, // Inst #253 = SET + {3, OperandInfo49}, // Inst #254 = ADDCCri + {3, OperandInfo50}, // Inst #255 = ADDCCrr + {3, OperandInfo49}, // Inst #256 = ADDCri + {3, OperandInfo50}, // Inst #257 = ADDCrr + {3, OperandInfo49}, // Inst #258 = ADDEri + {3, OperandInfo50}, // Inst #259 = ADDErr + {3, OperandInfo51}, // Inst #260 = ADDXC + {3, OperandInfo51}, // Inst #261 = ADDXCCC + {3, OperandInfo52}, // Inst #262 = ADDXri + {3, OperandInfo51}, // Inst #263 = ADDXrr + {3, OperandInfo49}, // Inst #264 = ADDri + {3, OperandInfo50}, // Inst #265 = ADDrr + {3, OperandInfo51}, // Inst #266 = ALIGNADDR + {3, OperandInfo51}, // Inst #267 = ALIGNADDRL + {3, OperandInfo49}, // Inst #268 = ANDCCri + {3, OperandInfo50}, // Inst #269 = ANDCCrr + {3, OperandInfo49}, // Inst #270 = ANDNCCri + {3, OperandInfo50}, // Inst #271 = ANDNCCrr + {3, OperandInfo49}, // Inst #272 = ANDNri + {3, OperandInfo50}, // Inst #273 = ANDNrr + {3, OperandInfo51}, // Inst #274 = ANDXNrr + {3, OperandInfo52}, // Inst #275 = ANDXri + {3, OperandInfo51}, // Inst #276 = ANDXrr + {3, OperandInfo49}, // Inst #277 = ANDri + {3, OperandInfo50}, // Inst #278 = ANDrr + {3, OperandInfo51}, // Inst #279 = ARRAY16 + {3, OperandInfo51}, // Inst #280 = ARRAY32 + {3, OperandInfo51}, // Inst #281 = ARRAY8 + {1, OperandInfo2}, // Inst #282 = BA + {2, OperandInfo7}, // Inst #283 = BCOND + {2, OperandInfo7}, // Inst #284 = BCONDA + {2, OperandInfo15}, // Inst #285 = BINDri + {2, OperandInfo53}, // Inst #286 = BINDrr + {3, OperandInfo51}, // Inst #287 = BMASK + {3, OperandInfo54}, // Inst #288 = BPFCC + {3, OperandInfo54}, // Inst #289 = BPFCCA + {3, OperandInfo54}, // Inst #290 = BPFCCANT + {3, OperandInfo54}, // Inst #291 = BPFCCNT + {2, OperandInfo55}, // Inst #292 = BPGEZapn + {2, OperandInfo55}, // Inst #293 = BPGEZapt + {2, OperandInfo55}, // Inst #294 = BPGEZnapn + {2, OperandInfo55}, // Inst #295 = BPGEZnapt + {2, OperandInfo55}, // Inst #296 = BPGZapn + {2, OperandInfo55}, // Inst #297 = BPGZapt + {2, OperandInfo55}, // Inst #298 = BPGZnapn + {2, OperandInfo55}, // Inst #299 = BPGZnapt + {2, OperandInfo7}, // Inst #300 = BPICC + {2, OperandInfo7}, // Inst #301 = BPICCA + {2, OperandInfo7}, // Inst #302 = BPICCANT + {2, OperandInfo7}, // Inst #303 = BPICCNT + {2, OperandInfo55}, // Inst #304 = BPLEZapn + {2, OperandInfo55}, // Inst #305 = BPLEZapt + {2, OperandInfo55}, // Inst #306 = BPLEZnapn + {2, OperandInfo55}, // Inst #307 = BPLEZnapt + {2, OperandInfo55}, // Inst #308 = BPLZapn + {2, OperandInfo55}, // Inst #309 = BPLZapt + {2, OperandInfo55}, // Inst #310 = BPLZnapn + {2, OperandInfo55}, // Inst #311 = BPLZnapt + {2, OperandInfo55}, // Inst #312 = BPNZapn + {2, OperandInfo55}, // Inst #313 = BPNZapt + {2, OperandInfo55}, // Inst #314 = BPNZnapn + {2, OperandInfo55}, // Inst #315 = BPNZnapt + {2, OperandInfo7}, // Inst #316 = BPXCC + {2, OperandInfo7}, // Inst #317 = BPXCCA + {2, OperandInfo7}, // Inst #318 = BPXCCANT + {2, OperandInfo7}, // Inst #319 = BPXCCNT + {2, OperandInfo55}, // Inst #320 = BPZapn + {2, OperandInfo55}, // Inst #321 = BPZapt + {2, OperandInfo55}, // Inst #322 = BPZnapn + {2, OperandInfo55}, // Inst #323 = BPZnapt + {3, OperandInfo56}, // Inst #324 = BSHUFFLE + {1, OperandInfo2}, // Inst #325 = CALL + {2, OperandInfo15}, // Inst #326 = CALLri + {2, OperandInfo53}, // Inst #327 = CALLrr + {4, OperandInfo57}, // Inst #328 = CASAasi10 + {5, OperandInfo58}, // Inst #329 = CASArr + {4, OperandInfo59}, // Inst #330 = CASXrr + {4, OperandInfo57}, // Inst #331 = CASrr + {2, OperandInfo7}, // Inst #332 = CBCOND + {2, OperandInfo7}, // Inst #333 = CBCONDA + {1, OperandInfo60}, // Inst #334 = CMASK16 + {1, OperandInfo60}, // Inst #335 = CMASK32 + {1, OperandInfo60}, // Inst #336 = CMASK8 + {2, OperandInfo61}, // Inst #337 = CMPri + {2, OperandInfo62}, // Inst #338 = CMPrr + {3, OperandInfo51}, // Inst #339 = EDGE16 + {3, OperandInfo51}, // Inst #340 = EDGE16L + {3, OperandInfo51}, // Inst #341 = EDGE16LN + {3, OperandInfo51}, // Inst #342 = EDGE16N + {3, OperandInfo51}, // Inst #343 = EDGE32 + {3, OperandInfo51}, // Inst #344 = EDGE32L + {3, OperandInfo51}, // Inst #345 = EDGE32LN + {3, OperandInfo51}, // Inst #346 = EDGE32N + {3, OperandInfo51}, // Inst #347 = EDGE8 + {3, OperandInfo51}, // Inst #348 = EDGE8L + {3, OperandInfo51}, // Inst #349 = EDGE8LN + {3, OperandInfo51}, // Inst #350 = EDGE8N + {2, OperandInfo63}, // Inst #351 = FABSD + {2, OperandInfo64}, // Inst #352 = FABSQ + {2, OperandInfo65}, // Inst #353 = FABSS + {3, OperandInfo56}, // Inst #354 = FADDD + {3, OperandInfo66}, // Inst #355 = FADDQ + {3, OperandInfo67}, // Inst #356 = FADDS + {3, OperandInfo56}, // Inst #357 = FALIGNADATA + {3, OperandInfo56}, // Inst #358 = FAND + {3, OperandInfo56}, // Inst #359 = FANDNOT1 + {3, OperandInfo67}, // Inst #360 = FANDNOT1S + {3, OperandInfo56}, // Inst #361 = FANDNOT2 + {3, OperandInfo67}, // Inst #362 = FANDNOT2S + {3, OperandInfo67}, // Inst #363 = FANDS + {2, OperandInfo7}, // Inst #364 = FBCOND + {2, OperandInfo7}, // Inst #365 = FBCONDA + {3, OperandInfo56}, // Inst #366 = FCHKSM16 + {2, OperandInfo63}, // Inst #367 = FCMPD + {3, OperandInfo68}, // Inst #368 = FCMPEQ16 + {3, OperandInfo68}, // Inst #369 = FCMPEQ32 + {3, OperandInfo68}, // Inst #370 = FCMPGT16 + {3, OperandInfo68}, // Inst #371 = FCMPGT32 + {3, OperandInfo68}, // Inst #372 = FCMPLE16 + {3, OperandInfo68}, // Inst #373 = FCMPLE32 + {3, OperandInfo68}, // Inst #374 = FCMPNE16 + {3, OperandInfo68}, // Inst #375 = FCMPNE32 + {2, OperandInfo64}, // Inst #376 = FCMPQ + {2, OperandInfo65}, // Inst #377 = FCMPS + {3, OperandInfo56}, // Inst #378 = FDIVD + {3, OperandInfo66}, // Inst #379 = FDIVQ + {3, OperandInfo67}, // Inst #380 = FDIVS + {3, OperandInfo69}, // Inst #381 = FDMULQ + {2, OperandInfo70}, // Inst #382 = FDTOI + {2, OperandInfo71}, // Inst #383 = FDTOQ + {2, OperandInfo70}, // Inst #384 = FDTOS + {2, OperandInfo63}, // Inst #385 = FDTOX + {2, OperandInfo63}, // Inst #386 = FEXPAND + {3, OperandInfo56}, // Inst #387 = FHADDD + {3, OperandInfo56}, // Inst #388 = FHADDS + {3, OperandInfo56}, // Inst #389 = FHSUBD + {3, OperandInfo56}, // Inst #390 = FHSUBS + {2, OperandInfo72}, // Inst #391 = FITOD + {2, OperandInfo73}, // Inst #392 = FITOQ + {2, OperandInfo65}, // Inst #393 = FITOS + {3, OperandInfo74}, // Inst #394 = FLCMPD + {3, OperandInfo74}, // Inst #395 = FLCMPS + {0, NULL}, // Inst #396 = FLUSH + {0, NULL}, // Inst #397 = FLUSHW + {2, OperandInfo15}, // Inst #398 = FLUSHri + {2, OperandInfo53}, // Inst #399 = FLUSHrr + {3, OperandInfo56}, // Inst #400 = FMEAN16 + {2, OperandInfo63}, // Inst #401 = FMOVD + {4, OperandInfo75}, // Inst #402 = FMOVD_FCC + {4, OperandInfo75}, // Inst #403 = FMOVD_ICC + {4, OperandInfo75}, // Inst #404 = FMOVD_XCC + {2, OperandInfo64}, // Inst #405 = FMOVQ + {4, OperandInfo76}, // Inst #406 = FMOVQ_FCC + {4, OperandInfo76}, // Inst #407 = FMOVQ_ICC + {4, OperandInfo76}, // Inst #408 = FMOVQ_XCC + {3, OperandInfo77}, // Inst #409 = FMOVRGEZD + {3, OperandInfo77}, // Inst #410 = FMOVRGEZQ + {3, OperandInfo77}, // Inst #411 = FMOVRGEZS + {3, OperandInfo77}, // Inst #412 = FMOVRGZD + {3, OperandInfo77}, // Inst #413 = FMOVRGZQ + {3, OperandInfo77}, // Inst #414 = FMOVRGZS + {3, OperandInfo77}, // Inst #415 = FMOVRLEZD + {3, OperandInfo77}, // Inst #416 = FMOVRLEZQ + {3, OperandInfo77}, // Inst #417 = FMOVRLEZS + {3, OperandInfo77}, // Inst #418 = FMOVRLZD + {3, OperandInfo77}, // Inst #419 = FMOVRLZQ + {3, OperandInfo77}, // Inst #420 = FMOVRLZS + {3, OperandInfo77}, // Inst #421 = FMOVRNZD + {3, OperandInfo77}, // Inst #422 = FMOVRNZQ + {3, OperandInfo77}, // Inst #423 = FMOVRNZS + {3, OperandInfo77}, // Inst #424 = FMOVRZD + {3, OperandInfo77}, // Inst #425 = FMOVRZQ + {3, OperandInfo77}, // Inst #426 = FMOVRZS + {2, OperandInfo65}, // Inst #427 = FMOVS + {4, OperandInfo78}, // Inst #428 = FMOVS_FCC + {4, OperandInfo78}, // Inst #429 = FMOVS_ICC + {4, OperandInfo78}, // Inst #430 = FMOVS_XCC + {3, OperandInfo56}, // Inst #431 = FMUL8SUX16 + {3, OperandInfo56}, // Inst #432 = FMUL8ULX16 + {3, OperandInfo56}, // Inst #433 = FMUL8X16 + {3, OperandInfo56}, // Inst #434 = FMUL8X16AL + {3, OperandInfo56}, // Inst #435 = FMUL8X16AU + {3, OperandInfo56}, // Inst #436 = FMULD + {3, OperandInfo56}, // Inst #437 = FMULD8SUX16 + {3, OperandInfo56}, // Inst #438 = FMULD8ULX16 + {3, OperandInfo66}, // Inst #439 = FMULQ + {3, OperandInfo67}, // Inst #440 = FMULS + {3, OperandInfo56}, // Inst #441 = FNADDD + {3, OperandInfo56}, // Inst #442 = FNADDS + {3, OperandInfo56}, // Inst #443 = FNAND + {3, OperandInfo67}, // Inst #444 = FNANDS + {2, OperandInfo63}, // Inst #445 = FNEGD + {2, OperandInfo64}, // Inst #446 = FNEGQ + {2, OperandInfo65}, // Inst #447 = FNEGS + {3, OperandInfo56}, // Inst #448 = FNHADDD + {3, OperandInfo56}, // Inst #449 = FNHADDS + {3, OperandInfo56}, // Inst #450 = FNMULD + {3, OperandInfo56}, // Inst #451 = FNMULS + {3, OperandInfo56}, // Inst #452 = FNOR + {3, OperandInfo67}, // Inst #453 = FNORS + {2, OperandInfo63}, // Inst #454 = FNOT1 + {2, OperandInfo65}, // Inst #455 = FNOT1S + {2, OperandInfo63}, // Inst #456 = FNOT2 + {2, OperandInfo65}, // Inst #457 = FNOT2S + {3, OperandInfo56}, // Inst #458 = FNSMULD + {2, OperandInfo79}, // Inst #459 = FONE + {2, OperandInfo80}, // Inst #460 = FONES + {3, OperandInfo56}, // Inst #461 = FOR + {3, OperandInfo56}, // Inst #462 = FORNOT1 + {3, OperandInfo67}, // Inst #463 = FORNOT1S + {3, OperandInfo56}, // Inst #464 = FORNOT2 + {3, OperandInfo67}, // Inst #465 = FORNOT2S + {3, OperandInfo67}, // Inst #466 = FORS + {2, OperandInfo63}, // Inst #467 = FPACK16 + {3, OperandInfo56}, // Inst #468 = FPACK32 + {2, OperandInfo63}, // Inst #469 = FPACKFIX + {3, OperandInfo56}, // Inst #470 = FPADD16 + {3, OperandInfo56}, // Inst #471 = FPADD16S + {3, OperandInfo56}, // Inst #472 = FPADD32 + {3, OperandInfo56}, // Inst #473 = FPADD32S + {3, OperandInfo56}, // Inst #474 = FPADD64 + {3, OperandInfo56}, // Inst #475 = FPMERGE + {3, OperandInfo56}, // Inst #476 = FPSUB16 + {3, OperandInfo56}, // Inst #477 = FPSUB16S + {3, OperandInfo56}, // Inst #478 = FPSUB32 + {3, OperandInfo56}, // Inst #479 = FPSUB32S + {2, OperandInfo81}, // Inst #480 = FQTOD + {2, OperandInfo82}, // Inst #481 = FQTOI + {2, OperandInfo82}, // Inst #482 = FQTOS + {2, OperandInfo81}, // Inst #483 = FQTOX + {3, OperandInfo56}, // Inst #484 = FSLAS16 + {3, OperandInfo56}, // Inst #485 = FSLAS32 + {3, OperandInfo56}, // Inst #486 = FSLL16 + {3, OperandInfo56}, // Inst #487 = FSLL32 + {3, OperandInfo83}, // Inst #488 = FSMULD + {2, OperandInfo63}, // Inst #489 = FSQRTD + {2, OperandInfo64}, // Inst #490 = FSQRTQ + {2, OperandInfo65}, // Inst #491 = FSQRTS + {3, OperandInfo56}, // Inst #492 = FSRA16 + {3, OperandInfo56}, // Inst #493 = FSRA32 + {2, OperandInfo63}, // Inst #494 = FSRC1 + {2, OperandInfo65}, // Inst #495 = FSRC1S + {2, OperandInfo63}, // Inst #496 = FSRC2 + {2, OperandInfo65}, // Inst #497 = FSRC2S + {3, OperandInfo56}, // Inst #498 = FSRL16 + {3, OperandInfo56}, // Inst #499 = FSRL32 + {2, OperandInfo72}, // Inst #500 = FSTOD + {2, OperandInfo65}, // Inst #501 = FSTOI + {2, OperandInfo73}, // Inst #502 = FSTOQ + {2, OperandInfo72}, // Inst #503 = FSTOX + {3, OperandInfo56}, // Inst #504 = FSUBD + {3, OperandInfo66}, // Inst #505 = FSUBQ + {3, OperandInfo67}, // Inst #506 = FSUBS + {3, OperandInfo56}, // Inst #507 = FXNOR + {3, OperandInfo67}, // Inst #508 = FXNORS + {3, OperandInfo56}, // Inst #509 = FXOR + {3, OperandInfo67}, // Inst #510 = FXORS + {2, OperandInfo63}, // Inst #511 = FXTOD + {2, OperandInfo71}, // Inst #512 = FXTOQ + {2, OperandInfo70}, // Inst #513 = FXTOS + {2, OperandInfo79}, // Inst #514 = FZERO + {2, OperandInfo80}, // Inst #515 = FZEROS + {3, OperandInfo84}, // Inst #516 = JMPLri + {3, OperandInfo85}, // Inst #517 = JMPLrr + {4, OperandInfo86}, // Inst #518 = LDArr + {2, OperandInfo15}, // Inst #519 = LDCSRri + {2, OperandInfo53}, // Inst #520 = LDCSRrr + {3, OperandInfo87}, // Inst #521 = LDCri + {3, OperandInfo88}, // Inst #522 = LDCrr + {4, OperandInfo89}, // Inst #523 = LDDArr + {3, OperandInfo90}, // Inst #524 = LDDCri + {3, OperandInfo91}, // Inst #525 = LDDCrr + {4, OperandInfo92}, // Inst #526 = LDDFArr + {3, OperandInfo93}, // Inst #527 = LDDFri + {3, OperandInfo94}, // Inst #528 = LDDFrr + {3, OperandInfo95}, // Inst #529 = LDDri + {3, OperandInfo96}, // Inst #530 = LDDrr + {4, OperandInfo97}, // Inst #531 = LDFArr + {2, OperandInfo15}, // Inst #532 = LDFSRri + {2, OperandInfo53}, // Inst #533 = LDFSRrr + {3, OperandInfo98}, // Inst #534 = LDFri + {3, OperandInfo99}, // Inst #535 = LDFrr + {4, OperandInfo100}, // Inst #536 = LDQFArr + {3, OperandInfo101}, // Inst #537 = LDQFri + {3, OperandInfo102}, // Inst #538 = LDQFrr + {4, OperandInfo86}, // Inst #539 = LDSBArr + {3, OperandInfo84}, // Inst #540 = LDSBri + {3, OperandInfo85}, // Inst #541 = LDSBrr + {4, OperandInfo86}, // Inst #542 = LDSHArr + {3, OperandInfo84}, // Inst #543 = LDSHri + {3, OperandInfo85}, // Inst #544 = LDSHrr + {4, OperandInfo86}, // Inst #545 = LDSTUBArr + {3, OperandInfo84}, // Inst #546 = LDSTUBri + {3, OperandInfo85}, // Inst #547 = LDSTUBrr + {3, OperandInfo103}, // Inst #548 = LDSWri + {3, OperandInfo104}, // Inst #549 = LDSWrr + {4, OperandInfo86}, // Inst #550 = LDUBArr + {3, OperandInfo84}, // Inst #551 = LDUBri + {3, OperandInfo85}, // Inst #552 = LDUBrr + {4, OperandInfo86}, // Inst #553 = LDUHArr + {3, OperandInfo84}, // Inst #554 = LDUHri + {3, OperandInfo85}, // Inst #555 = LDUHrr + {2, OperandInfo15}, // Inst #556 = LDXFSRri + {2, OperandInfo53}, // Inst #557 = LDXFSRrr + {3, OperandInfo103}, // Inst #558 = LDXri + {3, OperandInfo104}, // Inst #559 = LDXrr + {3, OperandInfo84}, // Inst #560 = LDri + {3, OperandInfo85}, // Inst #561 = LDrr + {3, OperandInfo103}, // Inst #562 = LEAX_ADDri + {3, OperandInfo84}, // Inst #563 = LEA_ADDri + {2, OperandInfo105}, // Inst #564 = LZCNT + {1, OperandInfo2}, // Inst #565 = MEMBARi + {2, OperandInfo106}, // Inst #566 = MOVDTOX + {4, OperandInfo107}, // Inst #567 = MOVFCCri + {4, OperandInfo108}, // Inst #568 = MOVFCCrr + {4, OperandInfo107}, // Inst #569 = MOVICCri + {4, OperandInfo108}, // Inst #570 = MOVICCrr + {3, OperandInfo52}, // Inst #571 = MOVRGEZri + {3, OperandInfo109}, // Inst #572 = MOVRGEZrr + {3, OperandInfo52}, // Inst #573 = MOVRGZri + {3, OperandInfo109}, // Inst #574 = MOVRGZrr + {3, OperandInfo52}, // Inst #575 = MOVRLEZri + {3, OperandInfo109}, // Inst #576 = MOVRLEZrr + {3, OperandInfo52}, // Inst #577 = MOVRLZri + {3, OperandInfo109}, // Inst #578 = MOVRLZrr + {3, OperandInfo52}, // Inst #579 = MOVRNZri + {3, OperandInfo109}, // Inst #580 = MOVRNZrr + {3, OperandInfo52}, // Inst #581 = MOVRRZri + {3, OperandInfo109}, // Inst #582 = MOVRRZrr + {2, OperandInfo106}, // Inst #583 = MOVSTOSW + {2, OperandInfo106}, // Inst #584 = MOVSTOUW + {2, OperandInfo110}, // Inst #585 = MOVWTOS + {4, OperandInfo107}, // Inst #586 = MOVXCCri + {4, OperandInfo108}, // Inst #587 = MOVXCCrr + {2, OperandInfo110}, // Inst #588 = MOVXTOD + {3, OperandInfo49}, // Inst #589 = MULSCCri + {3, OperandInfo50}, // Inst #590 = MULSCCrr + {3, OperandInfo111}, // Inst #591 = MULXri + {3, OperandInfo51}, // Inst #592 = MULXrr + {0, NULL}, // Inst #593 = NOP + {3, OperandInfo49}, // Inst #594 = ORCCri + {3, OperandInfo50}, // Inst #595 = ORCCrr + {3, OperandInfo49}, // Inst #596 = ORNCCri + {3, OperandInfo50}, // Inst #597 = ORNCCrr + {3, OperandInfo49}, // Inst #598 = ORNri + {3, OperandInfo50}, // Inst #599 = ORNrr + {3, OperandInfo51}, // Inst #600 = ORXNrr + {3, OperandInfo52}, // Inst #601 = ORXri + {3, OperandInfo51}, // Inst #602 = ORXrr + {3, OperandInfo49}, // Inst #603 = ORri + {3, OperandInfo50}, // Inst #604 = ORrr + {3, OperandInfo56}, // Inst #605 = PDIST + {3, OperandInfo56}, // Inst #606 = PDISTN + {2, OperandInfo62}, // Inst #607 = POPCrr + {3, OperandInfo112}, // Inst #608 = PREFETCHi + {3, OperandInfo113}, // Inst #609 = PREFETCHr + {2, OperandInfo61}, // Inst #610 = PWRPSRri + {2, OperandInfo62}, // Inst #611 = PWRPSRrr + {2, OperandInfo114}, // Inst #612 = RDASR + {1, OperandInfo115}, // Inst #613 = RDPC + {2, OperandInfo116}, // Inst #614 = RDPR + {1, OperandInfo115}, // Inst #615 = RDPSR + {1, OperandInfo115}, // Inst #616 = RDTBR + {1, OperandInfo115}, // Inst #617 = RDWIM + {3, OperandInfo49}, // Inst #618 = RESTOREri + {3, OperandInfo50}, // Inst #619 = RESTORErr + {1, OperandInfo3}, // Inst #620 = RET + {1, OperandInfo3}, // Inst #621 = RETL + {2, OperandInfo15}, // Inst #622 = RETTri + {2, OperandInfo53}, // Inst #623 = RETTrr + {3, OperandInfo49}, // Inst #624 = SAVEri + {3, OperandInfo50}, // Inst #625 = SAVErr + {3, OperandInfo49}, // Inst #626 = SDIVCCri + {3, OperandInfo50}, // Inst #627 = SDIVCCrr + {3, OperandInfo111}, // Inst #628 = SDIVXri + {3, OperandInfo51}, // Inst #629 = SDIVXrr + {3, OperandInfo49}, // Inst #630 = SDIVri + {3, OperandInfo50}, // Inst #631 = SDIVrr + {2, OperandInfo48}, // Inst #632 = SETHIXi + {2, OperandInfo48}, // Inst #633 = SETHIi + {0, NULL}, // Inst #634 = SHUTDOWN + {0, NULL}, // Inst #635 = SIAM + {1, OperandInfo2}, // Inst #636 = SIR + {3, OperandInfo117}, // Inst #637 = SLLXri + {3, OperandInfo109}, // Inst #638 = SLLXrr + {3, OperandInfo49}, // Inst #639 = SLLri + {3, OperandInfo50}, // Inst #640 = SLLrr + {4, OperandInfo118}, // Inst #641 = SMACri + {4, OperandInfo119}, // Inst #642 = SMACrr + {3, OperandInfo49}, // Inst #643 = SMULCCri + {3, OperandInfo50}, // Inst #644 = SMULCCrr + {3, OperandInfo49}, // Inst #645 = SMULri + {3, OperandInfo50}, // Inst #646 = SMULrr + {3, OperandInfo117}, // Inst #647 = SRAXri + {3, OperandInfo109}, // Inst #648 = SRAXrr + {3, OperandInfo49}, // Inst #649 = SRAri + {3, OperandInfo50}, // Inst #650 = SRArr + {3, OperandInfo117}, // Inst #651 = SRLXri + {3, OperandInfo109}, // Inst #652 = SRLXrr + {3, OperandInfo49}, // Inst #653 = SRLri + {3, OperandInfo50}, // Inst #654 = SRLrr + {4, OperandInfo120}, // Inst #655 = STArr + {0, NULL}, // Inst #656 = STBAR + {4, OperandInfo120}, // Inst #657 = STBArr + {3, OperandInfo121}, // Inst #658 = STBri + {3, OperandInfo122}, // Inst #659 = STBrr + {2, OperandInfo15}, // Inst #660 = STCSRri + {2, OperandInfo53}, // Inst #661 = STCSRrr + {3, OperandInfo123}, // Inst #662 = STCri + {3, OperandInfo124}, // Inst #663 = STCrr + {4, OperandInfo125}, // Inst #664 = STDArr + {2, OperandInfo15}, // Inst #665 = STDCQri + {2, OperandInfo53}, // Inst #666 = STDCQrr + {3, OperandInfo126}, // Inst #667 = STDCri + {3, OperandInfo127}, // Inst #668 = STDCrr + {4, OperandInfo128}, // Inst #669 = STDFArr + {2, OperandInfo15}, // Inst #670 = STDFQri + {2, OperandInfo53}, // Inst #671 = STDFQrr + {3, OperandInfo129}, // Inst #672 = STDFri + {3, OperandInfo130}, // Inst #673 = STDFrr + {3, OperandInfo131}, // Inst #674 = STDri + {3, OperandInfo132}, // Inst #675 = STDrr + {4, OperandInfo133}, // Inst #676 = STFArr + {2, OperandInfo15}, // Inst #677 = STFSRri + {2, OperandInfo53}, // Inst #678 = STFSRrr + {3, OperandInfo134}, // Inst #679 = STFri + {3, OperandInfo135}, // Inst #680 = STFrr + {4, OperandInfo120}, // Inst #681 = STHArr + {3, OperandInfo121}, // Inst #682 = STHri + {3, OperandInfo122}, // Inst #683 = STHrr + {4, OperandInfo136}, // Inst #684 = STQFArr + {3, OperandInfo137}, // Inst #685 = STQFri + {3, OperandInfo138}, // Inst #686 = STQFrr + {2, OperandInfo15}, // Inst #687 = STXFSRri + {2, OperandInfo53}, // Inst #688 = STXFSRrr + {3, OperandInfo139}, // Inst #689 = STXri + {3, OperandInfo140}, // Inst #690 = STXrr + {3, OperandInfo121}, // Inst #691 = STri + {3, OperandInfo122}, // Inst #692 = STrr + {3, OperandInfo49}, // Inst #693 = SUBCCri + {3, OperandInfo50}, // Inst #694 = SUBCCrr + {3, OperandInfo49}, // Inst #695 = SUBCri + {3, OperandInfo50}, // Inst #696 = SUBCrr + {3, OperandInfo49}, // Inst #697 = SUBEri + {3, OperandInfo50}, // Inst #698 = SUBErr + {3, OperandInfo52}, // Inst #699 = SUBXri + {3, OperandInfo51}, // Inst #700 = SUBXrr + {3, OperandInfo49}, // Inst #701 = SUBri + {3, OperandInfo50}, // Inst #702 = SUBrr + {5, OperandInfo141}, // Inst #703 = SWAPArr + {4, OperandInfo142}, // Inst #704 = SWAPri + {4, OperandInfo143}, // Inst #705 = SWAPrr + {0, NULL}, // Inst #706 = TA1 + {0, NULL}, // Inst #707 = TA3 + {0, NULL}, // Inst #708 = TA5 + {3, OperandInfo49}, // Inst #709 = TADDCCTVri + {3, OperandInfo50}, // Inst #710 = TADDCCTVrr + {3, OperandInfo49}, // Inst #711 = TADDCCri + {3, OperandInfo50}, // Inst #712 = TADDCCrr + {3, OperandInfo144}, // Inst #713 = TICCri + {3, OperandInfo49}, // Inst #714 = TICCrr + {4, OperandInfo145}, // Inst #715 = TLS_ADDXrr + {4, OperandInfo146}, // Inst #716 = TLS_ADDrr + {2, OperandInfo7}, // Inst #717 = TLS_CALL + {4, OperandInfo147}, // Inst #718 = TLS_LDXrr + {4, OperandInfo147}, // Inst #719 = TLS_LDrr + {3, OperandInfo144}, // Inst #720 = TRAPri + {3, OperandInfo49}, // Inst #721 = TRAPrr + {3, OperandInfo49}, // Inst #722 = TSUBCCTVri + {3, OperandInfo50}, // Inst #723 = TSUBCCTVrr + {3, OperandInfo49}, // Inst #724 = TSUBCCri + {3, OperandInfo50}, // Inst #725 = TSUBCCrr + {3, OperandInfo144}, // Inst #726 = TXCCri + {3, OperandInfo49}, // Inst #727 = TXCCrr + {3, OperandInfo49}, // Inst #728 = UDIVCCri + {3, OperandInfo50}, // Inst #729 = UDIVCCrr + {3, OperandInfo111}, // Inst #730 = UDIVXri + {3, OperandInfo51}, // Inst #731 = UDIVXrr + {3, OperandInfo49}, // Inst #732 = UDIVri + {3, OperandInfo50}, // Inst #733 = UDIVrr + {4, OperandInfo118}, // Inst #734 = UMACri + {4, OperandInfo119}, // Inst #735 = UMACrr + {3, OperandInfo49}, // Inst #736 = UMULCCri + {3, OperandInfo50}, // Inst #737 = UMULCCrr + {3, OperandInfo51}, // Inst #738 = UMULXHI + {3, OperandInfo49}, // Inst #739 = UMULri + {3, OperandInfo50}, // Inst #740 = UMULrr + {1, OperandInfo3}, // Inst #741 = UNIMP + {3, OperandInfo74}, // Inst #742 = V9FCMPD + {3, OperandInfo74}, // Inst #743 = V9FCMPED + {3, OperandInfo148}, // Inst #744 = V9FCMPEQ + {3, OperandInfo149}, // Inst #745 = V9FCMPES + {3, OperandInfo148}, // Inst #746 = V9FCMPQ + {3, OperandInfo149}, // Inst #747 = V9FCMPS + {5, OperandInfo150}, // Inst #748 = V9FMOVD_FCC + {5, OperandInfo151}, // Inst #749 = V9FMOVQ_FCC + {5, OperandInfo152}, // Inst #750 = V9FMOVS_FCC + {5, OperandInfo153}, // Inst #751 = V9MOVFCCri + {5, OperandInfo154}, // Inst #752 = V9MOVFCCrr + {3, OperandInfo155}, // Inst #753 = WRASRri + {3, OperandInfo156}, // Inst #754 = WRASRrr + {3, OperandInfo157}, // Inst #755 = WRPRri + {3, OperandInfo158}, // Inst #756 = WRPRrr + {2, OperandInfo61}, // Inst #757 = WRPSRri + {2, OperandInfo62}, // Inst #758 = WRPSRrr + {2, OperandInfo61}, // Inst #759 = WRTBRri + {2, OperandInfo62}, // Inst #760 = WRTBRrr + {2, OperandInfo61}, // Inst #761 = WRWIMri + {2, OperandInfo62}, // Inst #762 = WRWIMrr + {3, OperandInfo51}, // Inst #763 = XMULX + {3, OperandInfo51}, // Inst #764 = XMULXHI + {3, OperandInfo49}, // Inst #765 = XNORCCri + {3, OperandInfo50}, // Inst #766 = XNORCCrr + {3, OperandInfo51}, // Inst #767 = XNORXrr + {3, OperandInfo49}, // Inst #768 = XNORri + {3, OperandInfo50}, // Inst #769 = XNORrr + {3, OperandInfo49}, // Inst #770 = XORCCri + {3, OperandInfo50}, // Inst #771 = XORCCrr + {3, OperandInfo52}, // Inst #772 = XORXri + {3, OperandInfo51}, // Inst #773 = XORXrr + {3, OperandInfo49}, // Inst #774 = XORri + {3, OperandInfo50}, // Inst #775 = XORrr +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +extern const char SparcInstrNameData[] = { + /* 0 */ "G_FLOG10\0" + /* 9 */ "CASAasi10\0" + /* 19 */ "TA1\0" + /* 23 */ "FSRC1\0" + /* 29 */ "FANDNOT1\0" + /* 38 */ "FNOT1\0" + /* 44 */ "FORNOT1\0" + /* 52 */ "FSRA32\0" + /* 59 */ "FPSUB32\0" + /* 67 */ "FPADD32\0" + /* 75 */ "EDGE32\0" + /* 82 */ "FCMPLE32\0" + /* 91 */ "FCMPNE32\0" + /* 100 */ "FPACK32\0" + /* 108 */ "CMASK32\0" + /* 116 */ "FSLL32\0" + /* 123 */ "FSRL32\0" + /* 130 */ "FCMPEQ32\0" + /* 139 */ "FSLAS32\0" + /* 147 */ "FCMPGT32\0" + /* 156 */ "ARRAY32\0" + /* 164 */ "FSRC2\0" + /* 170 */ "G_FLOG2\0" + /* 178 */ "G_FEXP2\0" + /* 186 */ "FANDNOT2\0" + /* 195 */ "FNOT2\0" + /* 201 */ "FORNOT2\0" + /* 209 */ "TA3\0" + /* 213 */ "FPADD64\0" + /* 221 */ "TA5\0" + /* 225 */ "FSRA16\0" + /* 232 */ "FPSUB16\0" + /* 240 */ "FPADD16\0" + /* 248 */ "EDGE16\0" + /* 255 */ "FCMPLE16\0" + /* 264 */ "FCMPNE16\0" + /* 273 */ "FPACK16\0" + /* 281 */ "CMASK16\0" + /* 289 */ "FSLL16\0" + /* 296 */ "FSRL16\0" + /* 303 */ "FCHKSM16\0" + /* 312 */ "FMEAN16\0" + /* 320 */ "FCMPEQ16\0" + /* 329 */ "FSLAS16\0" + /* 337 */ "FCMPGT16\0" + /* 346 */ "FMUL8X16\0" + /* 355 */ "FMULD8ULX16\0" + /* 367 */ "FMUL8ULX16\0" + /* 378 */ "FMULD8SUX16\0" + /* 390 */ "FMUL8SUX16\0" + /* 401 */ "ARRAY16\0" + /* 409 */ "EDGE8\0" + /* 415 */ "CMASK8\0" + /* 422 */ "ARRAY8\0" + /* 429 */ "BA\0" + /* 432 */ "BPFCCA\0" + /* 439 */ "BPICCA\0" + /* 446 */ "BPXCCA\0" + /* 453 */ "CBCONDA\0" + /* 461 */ "FBCONDA\0" + /* 469 */ "G_FMA\0" + /* 475 */ "G_STRICT_FMA\0" + /* 488 */ "FALIGNADATA\0" + /* 500 */ "G_FSUB\0" + /* 507 */ "G_STRICT_FSUB\0" + /* 521 */ "G_ATOMICRMW_FSUB\0" + /* 538 */ "G_SUB\0" + /* 544 */ "G_ATOMICRMW_SUB\0" + /* 560 */ "ADDXCCC\0" + /* 568 */ "BPFCC\0" + /* 574 */ "V9FMOVD_FCC\0" + /* 586 */ "SELECT_CC_DFP_FCC\0" + /* 604 */ "SELECT_CC_QFP_FCC\0" + /* 622 */ "SELECT_CC_FP_FCC\0" + /* 639 */ "V9FMOVQ_FCC\0" + /* 651 */ "V9FMOVS_FCC\0" + /* 663 */ "SELECT_CC_Int_FCC\0" + /* 681 */ "BPICC\0" + /* 687 */ "FMOVD_ICC\0" + /* 697 */ "SELECT_CC_DFP_ICC\0" + /* 715 */ "SELECT_CC_QFP_ICC\0" + /* 733 */ "SELECT_CC_FP_ICC\0" + /* 750 */ "FMOVQ_ICC\0" + /* 760 */ "FMOVS_ICC\0" + /* 770 */ "SELECT_CC_Int_ICC\0" + /* 788 */ "BPXCC\0" + /* 794 */ "FMOVD_XCC\0" + /* 804 */ "FMOVQ_XCC\0" + /* 814 */ "FMOVS_XCC\0" + /* 824 */ "G_INTRINSIC\0" + /* 836 */ "G_FPTRUNC\0" + /* 846 */ "G_INTRINSIC_TRUNC\0" + /* 864 */ "G_TRUNC\0" + /* 872 */ "G_BUILD_VECTOR_TRUNC\0" + /* 893 */ "G_DYN_STACKALLOC\0" + /* 910 */ "RDPC\0" + /* 915 */ "ADDXC\0" + /* 921 */ "G_FMAD\0" + /* 928 */ "G_INDEXED_SEXTLOAD\0" + /* 947 */ "G_SEXTLOAD\0" + /* 958 */ "G_INDEXED_ZEXTLOAD\0" + /* 977 */ "G_ZEXTLOAD\0" + /* 988 */ "G_INDEXED_LOAD\0" + /* 1003 */ "G_LOAD\0" + /* 1010 */ "FSUBD\0" + /* 1016 */ "FHSUBD\0" + /* 1023 */ "G_VECREDUCE_FADD\0" + /* 1040 */ "G_FADD\0" + /* 1047 */ "G_VECREDUCE_SEQ_FADD\0" + /* 1068 */ "G_STRICT_FADD\0" + /* 1082 */ "G_ATOMICRMW_FADD\0" + /* 1099 */ "G_VECREDUCE_ADD\0" + /* 1115 */ "G_ADD\0" + /* 1121 */ "G_PTR_ADD\0" + /* 1131 */ "G_ATOMICRMW_ADD\0" + /* 1147 */ "FADDD\0" + /* 1153 */ "FHADDD\0" + /* 1160 */ "FNHADDD\0" + /* 1168 */ "FNADDD\0" + /* 1175 */ "V9FCMPED\0" + /* 1184 */ "FNEGD\0" + /* 1190 */ "FMULD\0" + /* 1196 */ "FNMULD\0" + /* 1203 */ "FSMULD\0" + /* 1210 */ "FNSMULD\0" + /* 1218 */ "FAND\0" + /* 1223 */ "FNAND\0" + /* 1229 */ "G_ATOMICRMW_NAND\0" + /* 1246 */ "FEXPAND\0" + /* 1254 */ "G_VECREDUCE_AND\0" + /* 1270 */ "G_AND\0" + /* 1276 */ "G_ATOMICRMW_AND\0" + /* 1292 */ "LIFETIME_END\0" + /* 1305 */ "CBCOND\0" + /* 1312 */ "FBCOND\0" + /* 1319 */ "G_BRCOND\0" + /* 1328 */ "G_LLROUND\0" + /* 1338 */ "G_LROUND\0" + /* 1347 */ "G_INTRINSIC_ROUND\0" + /* 1365 */ "FITOD\0" + /* 1371 */ "FQTOD\0" + /* 1377 */ "FSTOD\0" + /* 1383 */ "FXTOD\0" + /* 1389 */ "MOVXTOD\0" + /* 1397 */ "V9FCMPD\0" + /* 1405 */ "FLCMPD\0" + /* 1412 */ "LOAD_STACK_GUARD\0" + /* 1429 */ "FABSD\0" + /* 1435 */ "FSQRTD\0" + /* 1442 */ "FDIVD\0" + /* 1448 */ "FMOVD\0" + /* 1454 */ "FMOVRGEZD\0" + /* 1464 */ "FMOVRLEZD\0" + /* 1474 */ "FMOVRGZD\0" + /* 1483 */ "FMOVRLZD\0" + /* 1492 */ "FMOVRNZD\0" + /* 1501 */ "FMOVRZD\0" + /* 1509 */ "PSEUDO_PROBE\0" + /* 1522 */ "G_SSUBE\0" + /* 1530 */ "G_USUBE\0" + /* 1538 */ "G_FENCE\0" + /* 1546 */ "ARITH_FENCE\0" + /* 1558 */ "REG_SEQUENCE\0" + /* 1571 */ "G_SADDE\0" + /* 1579 */ "G_UADDE\0" + /* 1587 */ "G_FMINNUM_IEEE\0" + /* 1602 */ "G_FMAXNUM_IEEE\0" + /* 1617 */ "FPMERGE\0" + /* 1625 */ "G_JUMP_TABLE\0" + /* 1638 */ "BUNDLE\0" + /* 1645 */ "BSHUFFLE\0" + /* 1654 */ "G_MEMCPY_INLINE\0" + /* 1670 */ "FONE\0" + /* 1675 */ "LOCAL_ESCAPE\0" + /* 1688 */ "G_INDEXED_STORE\0" + /* 1704 */ "G_STORE\0" + /* 1712 */ "G_BITREVERSE\0" + /* 1725 */ "DBG_VALUE\0" + /* 1735 */ "G_GLOBAL_VALUE\0" + /* 1750 */ "G_MEMMOVE\0" + /* 1760 */ "G_FREEZE\0" + /* 1769 */ "G_FCANONICALIZE\0" + /* 1785 */ "G_CTLZ_ZERO_UNDEF\0" + /* 1803 */ "G_CTTZ_ZERO_UNDEF\0" + /* 1821 */ "G_IMPLICIT_DEF\0" + /* 1836 */ "DBG_INSTR_REF\0" + /* 1850 */ "G_FNEG\0" + /* 1857 */ "EXTRACT_SUBREG\0" + /* 1872 */ "INSERT_SUBREG\0" + /* 1886 */ "G_SEXT_INREG\0" + /* 1899 */ "SUBREG_TO_REG\0" + /* 1913 */ "G_ATOMIC_CMPXCHG\0" + /* 1930 */ "G_ATOMICRMW_XCHG\0" + /* 1947 */ "G_FLOG\0" + /* 1954 */ "G_VAARG\0" + /* 1962 */ "PREALLOCATED_ARG\0" + /* 1979 */ "G_SMULH\0" + /* 1987 */ "G_UMULH\0" + /* 1995 */ "FLUSH\0" + /* 2001 */ "DBG_PHI\0" + /* 2009 */ "UMULXHI\0" + /* 2017 */ "XMULXHI\0" + /* 2025 */ "FDTOI\0" + /* 2031 */ "FQTOI\0" + /* 2037 */ "FSTOI\0" + /* 2043 */ "G_FPTOSI\0" + /* 2052 */ "G_FPTOUI\0" + /* 2061 */ "G_FPOWI\0" + /* 2069 */ "BMASK\0" + /* 2075 */ "G_PTRMASK\0" + /* 2085 */ "EDGE32L\0" + /* 2093 */ "EDGE16L\0" + /* 2101 */ "EDGE8L\0" + /* 2108 */ "FMUL8X16AL\0" + /* 2119 */ "GC_LABEL\0" + /* 2128 */ "DBG_LABEL\0" + /* 2138 */ "EH_LABEL\0" + /* 2147 */ "ANNOTATION_LABEL\0" + /* 2164 */ "ICALL_BRANCH_FUNNEL\0" + /* 2184 */ "G_FSHL\0" + /* 2191 */ "G_SHL\0" + /* 2197 */ "G_FCEIL\0" + /* 2205 */ "PATCHABLE_TAIL_CALL\0" + /* 2225 */ "TLS_CALL\0" + /* 2234 */ "PATCHABLE_TYPED_EVENT_CALL\0" + /* 2261 */ "PATCHABLE_EVENT_CALL\0" + /* 2282 */ "FENTRY_CALL\0" + /* 2294 */ "KILL\0" + /* 2299 */ "ALIGNADDRL\0" + /* 2310 */ "RETL\0" + /* 2315 */ "G_ROTL\0" + /* 2322 */ "G_VECREDUCE_FMUL\0" + /* 2339 */ "G_FMUL\0" + /* 2346 */ "G_VECREDUCE_SEQ_FMUL\0" + /* 2367 */ "G_STRICT_FMUL\0" + /* 2381 */ "G_VECREDUCE_MUL\0" + /* 2397 */ "G_MUL\0" + /* 2403 */ "SIAM\0" + /* 2408 */ "G_FREM\0" + /* 2415 */ "G_STRICT_FREM\0" + /* 2429 */ "G_SREM\0" + /* 2436 */ "G_UREM\0" + /* 2443 */ "G_SDIVREM\0" + /* 2453 */ "G_UDIVREM\0" + /* 2463 */ "RDWIM\0" + /* 2469 */ "INLINEASM\0" + /* 2479 */ "G_FMINIMUM\0" + /* 2490 */ "G_FMAXIMUM\0" + /* 2501 */ "G_FMINNUM\0" + /* 2511 */ "G_FMAXNUM\0" + /* 2521 */ "EDGE32N\0" + /* 2529 */ "EDGE16N\0" + /* 2537 */ "EDGE8N\0" + /* 2544 */ "G_INTRINSIC_ROUNDEVEN\0" + /* 2566 */ "G_FCOPYSIGN\0" + /* 2578 */ "G_VECREDUCE_FMIN\0" + /* 2595 */ "G_VECREDUCE_SMIN\0" + /* 2612 */ "G_SMIN\0" + /* 2619 */ "G_VECREDUCE_UMIN\0" + /* 2636 */ "G_UMIN\0" + /* 2643 */ "G_ATOMICRMW_UMIN\0" + /* 2660 */ "G_ATOMICRMW_MIN\0" + /* 2676 */ "G_FSIN\0" + /* 2683 */ "EDGE32LN\0" + /* 2692 */ "EDGE16LN\0" + /* 2701 */ "EDGE8LN\0" + /* 2709 */ "CFI_INSTRUCTION\0" + /* 2725 */ "PDISTN\0" + /* 2732 */ "ADJCALLSTACKDOWN\0" + /* 2749 */ "SHUTDOWN\0" + /* 2758 */ "G_SSUBO\0" + /* 2766 */ "G_USUBO\0" + /* 2774 */ "G_SADDO\0" + /* 2782 */ "G_UADDO\0" + /* 2790 */ "G_SMULO\0" + /* 2798 */ "G_UMULO\0" + /* 2806 */ "G_BZERO\0" + /* 2814 */ "FZERO\0" + /* 2820 */ "STACKMAP\0" + /* 2829 */ "G_BSWAP\0" + /* 2837 */ "G_SITOFP\0" + /* 2846 */ "G_UITOFP\0" + /* 2855 */ "G_FCMP\0" + /* 2862 */ "G_ICMP\0" + /* 2869 */ "UNIMP\0" + /* 2875 */ "NOP\0" + /* 2879 */ "G_CTPOP\0" + /* 2887 */ "PATCHABLE_OP\0" + /* 2900 */ "FAULTING_OP\0" + /* 2912 */ "ADJCALLSTACKUP\0" + /* 2927 */ "PREALLOCATED_SETUP\0" + /* 2946 */ "G_FEXP\0" + /* 2953 */ "FSUBQ\0" + /* 2959 */ "FADDQ\0" + /* 2965 */ "V9FCMPEQ\0" + /* 2974 */ "FNEGQ\0" + /* 2980 */ "FDMULQ\0" + /* 2987 */ "FMULQ\0" + /* 2993 */ "FDTOQ\0" + /* 2999 */ "FITOQ\0" + /* 3005 */ "FSTOQ\0" + /* 3011 */ "FXTOQ\0" + /* 3017 */ "V9FCMPQ\0" + /* 3025 */ "FABSQ\0" + /* 3031 */ "FSQRTQ\0" + /* 3038 */ "FDIVQ\0" + /* 3044 */ "FMOVQ\0" + /* 3050 */ "FMOVRGEZQ\0" + /* 3060 */ "FMOVRLEZQ\0" + /* 3070 */ "FMOVRGZQ\0" + /* 3079 */ "FMOVRLZQ\0" + /* 3088 */ "FMOVRNZQ\0" + /* 3097 */ "FMOVRZQ\0" + /* 3105 */ "STBAR\0" + /* 3111 */ "RDTBR\0" + /* 3117 */ "G_BR\0" + /* 3122 */ "INLINEASM_BR\0" + /* 3135 */ "ALIGNADDR\0" + /* 3145 */ "G_BLOCK_ADDR\0" + /* 3158 */ "PATCHABLE_FUNCTION_ENTER\0" + /* 3183 */ "G_READCYCLECOUNTER\0" + /* 3202 */ "G_READ_REGISTER\0" + /* 3218 */ "G_WRITE_REGISTER\0" + /* 3235 */ "G_ASHR\0" + /* 3242 */ "G_FSHR\0" + /* 3249 */ "G_LSHR\0" + /* 3256 */ "SIR\0" + /* 3260 */ "FOR\0" + /* 3264 */ "FNOR\0" + /* 3269 */ "FXNOR\0" + /* 3275 */ "G_FFLOOR\0" + /* 3284 */ "G_BUILD_VECTOR\0" + /* 3299 */ "G_SHUFFLE_VECTOR\0" + /* 3316 */ "FXOR\0" + /* 3321 */ "G_VECREDUCE_XOR\0" + /* 3337 */ "G_XOR\0" + /* 3343 */ "G_ATOMICRMW_XOR\0" + /* 3359 */ "G_VECREDUCE_OR\0" + /* 3374 */ "G_OR\0" + /* 3379 */ "G_ATOMICRMW_OR\0" + /* 3394 */ "RDPR\0" + /* 3399 */ "RDASR\0" + /* 3405 */ "RDPSR\0" + /* 3411 */ "G_ROTR\0" + /* 3418 */ "G_INTTOPTR\0" + /* 3429 */ "FSRC1S\0" + /* 3436 */ "FANDNOT1S\0" + /* 3446 */ "FNOT1S\0" + /* 3453 */ "FORNOT1S\0" + /* 3462 */ "FPSUB32S\0" + /* 3471 */ "FPADD32S\0" + /* 3480 */ "FSRC2S\0" + /* 3487 */ "FANDNOT2S\0" + /* 3497 */ "FNOT2S\0" + /* 3504 */ "FORNOT2S\0" + /* 3513 */ "FPSUB16S\0" + /* 3522 */ "FPADD16S\0" + /* 3531 */ "G_FABS\0" + /* 3538 */ "G_ABS\0" + /* 3544 */ "FSUBS\0" + /* 3550 */ "FHSUBS\0" + /* 3557 */ "FADDS\0" + /* 3563 */ "FHADDS\0" + /* 3570 */ "FNHADDS\0" + /* 3578 */ "FNADDS\0" + /* 3585 */ "FANDS\0" + /* 3591 */ "FNANDS\0" + /* 3598 */ "FONES\0" + /* 3604 */ "V9FCMPES\0" + /* 3613 */ "G_UNMERGE_VALUES\0" + /* 3630 */ "G_MERGE_VALUES\0" + /* 3645 */ "FNEGS\0" + /* 3651 */ "FMULS\0" + /* 3657 */ "FNMULS\0" + /* 3664 */ "G_FCOS\0" + /* 3671 */ "FZEROS\0" + /* 3678 */ "FDTOS\0" + /* 3684 */ "FITOS\0" + /* 3690 */ "FQTOS\0" + /* 3696 */ "MOVWTOS\0" + /* 3704 */ "FXTOS\0" + /* 3710 */ "V9FCMPS\0" + /* 3718 */ "FLCMPS\0" + /* 3725 */ "FORS\0" + /* 3730 */ "FNORS\0" + /* 3736 */ "FXNORS\0" + /* 3743 */ "G_CONCAT_VECTORS\0" + /* 3760 */ "FXORS\0" + /* 3766 */ "COPY_TO_REGCLASS\0" + /* 3783 */ "FABSS\0" + /* 3789 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" + /* 3819 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" + /* 3846 */ "FSQRTS\0" + /* 3853 */ "FDIVS\0" + /* 3859 */ "FMOVS\0" + /* 3865 */ "FMOVRGEZS\0" + /* 3875 */ "FMOVRLEZS\0" + /* 3885 */ "FMOVRGZS\0" + /* 3894 */ "FMOVRLZS\0" + /* 3903 */ "FMOVRNZS\0" + /* 3912 */ "FMOVRZS\0" + /* 3920 */ "G_SSUBSAT\0" + /* 3930 */ "G_USUBSAT\0" + /* 3940 */ "G_SADDSAT\0" + /* 3950 */ "G_UADDSAT\0" + /* 3960 */ "G_SSHLSAT\0" + /* 3970 */ "G_USHLSAT\0" + /* 3980 */ "G_SMULFIXSAT\0" + /* 3993 */ "G_UMULFIXSAT\0" + /* 4006 */ "G_SDIVFIXSAT\0" + /* 4019 */ "G_UDIVFIXSAT\0" + /* 4032 */ "G_EXTRACT\0" + /* 4042 */ "G_SELECT\0" + /* 4051 */ "G_BRINDIRECT\0" + /* 4064 */ "PATCHABLE_RET\0" + /* 4078 */ "G_MEMSET\0" + /* 4087 */ "PATCHABLE_FUNCTION_EXIT\0" + /* 4111 */ "G_BRJT\0" + /* 4118 */ "G_EXTRACT_VECTOR_ELT\0" + /* 4139 */ "G_INSERT_VECTOR_ELT\0" + /* 4159 */ "BPFCCANT\0" + /* 4168 */ "BPICCANT\0" + /* 4177 */ "BPXCCANT\0" + /* 4186 */ "G_FCONSTANT\0" + /* 4198 */ "G_CONSTANT\0" + /* 4209 */ "BPFCCNT\0" + /* 4217 */ "BPICCNT\0" + /* 4225 */ "BPXCCNT\0" + /* 4233 */ "LZCNT\0" + /* 4239 */ "STATEPOINT\0" + /* 4250 */ "PATCHPOINT\0" + /* 4261 */ "G_PTRTOINT\0" + /* 4272 */ "G_FRINT\0" + /* 4280 */ "G_INTRINSIC_LRINT\0" + /* 4298 */ "G_FNEARBYINT\0" + /* 4311 */ "G_VASTART\0" + /* 4321 */ "LIFETIME_START\0" + /* 4336 */ "G_INSERT\0" + /* 4345 */ "G_FSQRT\0" + /* 4353 */ "G_STRICT_FSQRT\0" + /* 4368 */ "G_BITCAST\0" + /* 4378 */ "G_ADDRSPACE_CAST\0" + /* 4395 */ "PDIST\0" + /* 4401 */ "DBG_VALUE_LIST\0" + /* 4416 */ "G_FPEXT\0" + /* 4424 */ "G_SEXT\0" + /* 4431 */ "G_ASSERT_SEXT\0" + /* 4445 */ "G_ANYEXT\0" + /* 4454 */ "G_ZEXT\0" + /* 4461 */ "G_ASSERT_ZEXT\0" + /* 4475 */ "FMUL8X16AU\0" + /* 4486 */ "G_FDIV\0" + /* 4493 */ "G_STRICT_FDIV\0" + /* 4507 */ "G_SDIV\0" + /* 4514 */ "G_UDIV\0" + /* 4521 */ "FLUSHW\0" + /* 4528 */ "G_FPOW\0" + /* 4535 */ "MOVSTOSW\0" + /* 4544 */ "MOVSTOUW\0" + /* 4553 */ "G_VECREDUCE_FMAX\0" + /* 4570 */ "G_VECREDUCE_SMAX\0" + /* 4587 */ "G_SMAX\0" + /* 4594 */ "G_VECREDUCE_UMAX\0" + /* 4611 */ "G_UMAX\0" + /* 4618 */ "G_ATOMICRMW_UMAX\0" + /* 4635 */ "G_ATOMICRMW_MAX\0" + /* 4651 */ "GETPCX\0" + /* 4658 */ "G_FRAME_INDEX\0" + /* 4672 */ "G_SBFX\0" + /* 4679 */ "G_UBFX\0" + /* 4686 */ "FPACKFIX\0" + /* 4695 */ "G_SMULFIX\0" + /* 4705 */ "G_UMULFIX\0" + /* 4715 */ "G_SDIVFIX\0" + /* 4725 */ "G_UDIVFIX\0" + /* 4735 */ "XMULX\0" + /* 4741 */ "FDTOX\0" + /* 4747 */ "MOVDTOX\0" + /* 4755 */ "FQTOX\0" + /* 4761 */ "FSTOX\0" + /* 4767 */ "G_MEMCPY\0" + /* 4776 */ "COPY\0" + /* 4781 */ "G_CTLZ\0" + /* 4788 */ "G_CTTZ\0" + /* 4795 */ "PREFETCHi\0" + /* 4805 */ "SETHIi\0" + /* 4812 */ "MEMBARi\0" + /* 4820 */ "SETHIXi\0" + /* 4828 */ "SRAri\0" + /* 4834 */ "LDSBri\0" + /* 4841 */ "STBri\0" + /* 4847 */ "LDUBri\0" + /* 4854 */ "SUBri\0" + /* 4860 */ "LDSTUBri\0" + /* 4869 */ "SMACri\0" + /* 4876 */ "UMACri\0" + /* 4883 */ "SUBCri\0" + /* 4890 */ "TSUBCCri\0" + /* 4899 */ "TADDCCri\0" + /* 4908 */ "ANDCCri\0" + /* 4916 */ "V9MOVFCCri\0" + /* 4927 */ "TICCri\0" + /* 4934 */ "MOVICCri\0" + /* 4943 */ "SMULCCri\0" + /* 4952 */ "UMULCCri\0" + /* 4961 */ "ANDNCCri\0" + /* 4970 */ "ORNCCri\0" + /* 4978 */ "XNORCCri\0" + /* 4987 */ "XORCCri\0" + /* 4995 */ "MULSCCri\0" + /* 5004 */ "SDIVCCri\0" + /* 5013 */ "UDIVCCri\0" + /* 5022 */ "TXCCri\0" + /* 5029 */ "MOVXCCri\0" + /* 5038 */ "ADDCri\0" + /* 5045 */ "LDDCri\0" + /* 5052 */ "LDCri\0" + /* 5058 */ "STDCri\0" + /* 5065 */ "STCri\0" + /* 5071 */ "LEA_ADDri\0" + /* 5081 */ "LEAX_ADDri\0" + /* 5092 */ "LDDri\0" + /* 5098 */ "LDri\0" + /* 5103 */ "ANDri\0" + /* 5109 */ "BINDri\0" + /* 5116 */ "STDri\0" + /* 5122 */ "SUBEri\0" + /* 5129 */ "ADDEri\0" + /* 5136 */ "RESTOREri\0" + /* 5146 */ "SAVEri\0" + /* 5153 */ "LDDFri\0" + /* 5160 */ "LDFri\0" + /* 5166 */ "STDFri\0" + /* 5173 */ "LDQFri\0" + /* 5180 */ "STQFri\0" + /* 5187 */ "STFri\0" + /* 5193 */ "LDSHri\0" + /* 5200 */ "FLUSHri\0" + /* 5208 */ "STHri\0" + /* 5214 */ "LDUHri\0" + /* 5221 */ "CALLri\0" + /* 5228 */ "SLLri\0" + /* 5234 */ "JMPLri\0" + /* 5241 */ "SRLri\0" + /* 5247 */ "SMULri\0" + /* 5254 */ "UMULri\0" + /* 5261 */ "WRWIMri\0" + /* 5269 */ "ANDNri\0" + /* 5276 */ "ORNri\0" + /* 5282 */ "TRAPri\0" + /* 5289 */ "SWAPri\0" + /* 5296 */ "CMPri\0" + /* 5302 */ "STDCQri\0" + /* 5310 */ "STDFQri\0" + /* 5318 */ "WRTBRri\0" + /* 5326 */ "XNORri\0" + /* 5333 */ "XORri\0" + /* 5339 */ "WRPRri\0" + /* 5346 */ "WRASRri\0" + /* 5354 */ "LDCSRri\0" + /* 5362 */ "STCSRri\0" + /* 5370 */ "LDFSRri\0" + /* 5378 */ "STFSRri\0" + /* 5386 */ "LDXFSRri\0" + /* 5395 */ "STXFSRri\0" + /* 5404 */ "PWRPSRri\0" + /* 5413 */ "STri\0" + /* 5418 */ "RETTri\0" + /* 5425 */ "SDIVri\0" + /* 5432 */ "UDIVri\0" + /* 5439 */ "TSUBCCTVri\0" + /* 5450 */ "TADDCCTVri\0" + /* 5461 */ "LDSWri\0" + /* 5468 */ "SRAXri\0" + /* 5475 */ "SUBXri\0" + /* 5482 */ "ADDXri\0" + /* 5489 */ "LDXri\0" + /* 5495 */ "ANDXri\0" + /* 5502 */ "SLLXri\0" + /* 5509 */ "SRLXri\0" + /* 5516 */ "MULXri\0" + /* 5523 */ "XORXri\0" + /* 5530 */ "STXri\0" + /* 5536 */ "SDIVXri\0" + /* 5544 */ "UDIVXri\0" + /* 5552 */ "MOVRGEZri\0" + /* 5562 */ "MOVRLEZri\0" + /* 5572 */ "MOVRGZri\0" + /* 5581 */ "MOVRLZri\0" + /* 5590 */ "MOVRNZri\0" + /* 5599 */ "MOVRRZri\0" + /* 5608 */ "BPGEZapn\0" + /* 5617 */ "BPLEZapn\0" + /* 5626 */ "BPGZapn\0" + /* 5634 */ "BPLZapn\0" + /* 5642 */ "BPNZapn\0" + /* 5650 */ "BPZapn\0" + /* 5657 */ "BPGEZnapn\0" + /* 5667 */ "BPLEZnapn\0" + /* 5677 */ "BPGZnapn\0" + /* 5686 */ "BPLZnapn\0" + /* 5695 */ "BPNZnapn\0" + /* 5704 */ "BPZnapn\0" + /* 5712 */ "PREFETCHr\0" + /* 5722 */ "LDSBArr\0" + /* 5730 */ "STBArr\0" + /* 5737 */ "LDUBArr\0" + /* 5745 */ "LDSTUBArr\0" + /* 5755 */ "LDDArr\0" + /* 5762 */ "LDArr\0" + /* 5768 */ "STDArr\0" + /* 5775 */ "LDDFArr\0" + /* 5783 */ "LDFArr\0" + /* 5790 */ "STDFArr\0" + /* 5798 */ "LDQFArr\0" + /* 5806 */ "STQFArr\0" + /* 5814 */ "STFArr\0" + /* 5821 */ "LDSHArr\0" + /* 5829 */ "STHArr\0" + /* 5836 */ "LDUHArr\0" + /* 5844 */ "SWAPArr\0" + /* 5852 */ "SRArr\0" + /* 5858 */ "CASArr\0" + /* 5865 */ "STArr\0" + /* 5871 */ "LDSBrr\0" + /* 5878 */ "STBrr\0" + /* 5884 */ "LDUBrr\0" + /* 5891 */ "SUBrr\0" + /* 5897 */ "LDSTUBrr\0" + /* 5906 */ "SMACrr\0" + /* 5913 */ "UMACrr\0" + /* 5920 */ "SUBCrr\0" + /* 5927 */ "TSUBCCrr\0" + /* 5936 */ "TADDCCrr\0" + /* 5945 */ "ANDCCrr\0" + /* 5953 */ "V9MOVFCCrr\0" + /* 5964 */ "TICCrr\0" + /* 5971 */ "MOVICCrr\0" + /* 5980 */ "SMULCCrr\0" + /* 5989 */ "UMULCCrr\0" + /* 5998 */ "ANDNCCrr\0" + /* 6007 */ "ORNCCrr\0" + /* 6015 */ "XNORCCrr\0" + /* 6024 */ "XORCCrr\0" + /* 6032 */ "MULSCCrr\0" + /* 6041 */ "SDIVCCrr\0" + /* 6050 */ "UDIVCCrr\0" + /* 6059 */ "TXCCrr\0" + /* 6066 */ "MOVXCCrr\0" + /* 6075 */ "ADDCrr\0" + /* 6082 */ "LDDCrr\0" + /* 6089 */ "LDCrr\0" + /* 6095 */ "STDCrr\0" + /* 6102 */ "POPCrr\0" + /* 6109 */ "STCrr\0" + /* 6115 */ "TLS_ADDrr\0" + /* 6125 */ "LDDrr\0" + /* 6131 */ "TLS_LDrr\0" + /* 6140 */ "ANDrr\0" + /* 6146 */ "BINDrr\0" + /* 6153 */ "STDrr\0" + /* 6159 */ "SUBErr\0" + /* 6166 */ "ADDErr\0" + /* 6173 */ "RESTORErr\0" + /* 6183 */ "SAVErr\0" + /* 6190 */ "LDDFrr\0" + /* 6197 */ "LDFrr\0" + /* 6203 */ "STDFrr\0" + /* 6210 */ "LDQFrr\0" + /* 6217 */ "STQFrr\0" + /* 6224 */ "STFrr\0" + /* 6230 */ "LDSHrr\0" + /* 6237 */ "FLUSHrr\0" + /* 6245 */ "STHrr\0" + /* 6251 */ "LDUHrr\0" + /* 6258 */ "CALLrr\0" + /* 6265 */ "SLLrr\0" + /* 6271 */ "JMPLrr\0" + /* 6278 */ "SRLrr\0" + /* 6284 */ "SMULrr\0" + /* 6291 */ "UMULrr\0" + /* 6298 */ "WRWIMrr\0" + /* 6306 */ "ANDNrr\0" + /* 6313 */ "ORNrr\0" + /* 6319 */ "ANDXNrr\0" + /* 6327 */ "ORXNrr\0" + /* 6334 */ "TRAPrr\0" + /* 6341 */ "SWAPrr\0" + /* 6348 */ "CMPrr\0" + /* 6354 */ "STDCQrr\0" + /* 6362 */ "STDFQrr\0" + /* 6370 */ "WRTBRrr\0" + /* 6378 */ "XNORrr\0" + /* 6385 */ "XORrr\0" + /* 6391 */ "WRPRrr\0" + /* 6398 */ "WRASRrr\0" + /* 6406 */ "LDCSRrr\0" + /* 6414 */ "STCSRrr\0" + /* 6422 */ "LDFSRrr\0" + /* 6430 */ "STFSRrr\0" + /* 6438 */ "LDXFSRrr\0" + /* 6447 */ "STXFSRrr\0" + /* 6456 */ "PWRPSRrr\0" + /* 6465 */ "CASrr\0" + /* 6471 */ "STrr\0" + /* 6476 */ "RETTrr\0" + /* 6483 */ "SDIVrr\0" + /* 6490 */ "UDIVrr\0" + /* 6497 */ "TSUBCCTVrr\0" + /* 6508 */ "TADDCCTVrr\0" + /* 6519 */ "LDSWrr\0" + /* 6526 */ "SRAXrr\0" + /* 6533 */ "SUBXrr\0" + /* 6540 */ "TLS_ADDXrr\0" + /* 6551 */ "TLS_LDXrr\0" + /* 6561 */ "ANDXrr\0" + /* 6568 */ "SLLXrr\0" + /* 6575 */ "SRLXrr\0" + /* 6582 */ "MULXrr\0" + /* 6589 */ "XNORXrr\0" + /* 6597 */ "XORXrr\0" + /* 6604 */ "CASXrr\0" + /* 6611 */ "STXrr\0" + /* 6617 */ "SDIVXrr\0" + /* 6625 */ "UDIVXrr\0" + /* 6633 */ "MOVRGEZrr\0" + /* 6643 */ "MOVRLEZrr\0" + /* 6653 */ "MOVRGZrr\0" + /* 6662 */ "MOVRLZrr\0" + /* 6671 */ "MOVRNZrr\0" + /* 6680 */ "MOVRRZrr\0" + /* 6689 */ "BPGEZapt\0" + /* 6698 */ "BPLEZapt\0" + /* 6707 */ "BPGZapt\0" + /* 6715 */ "BPLZapt\0" + /* 6723 */ "BPNZapt\0" + /* 6731 */ "BPZapt\0" + /* 6738 */ "BPGEZnapt\0" + /* 6748 */ "BPLEZnapt\0" + /* 6758 */ "BPGZnapt\0" + /* 6767 */ "BPLZnapt\0" + /* 6776 */ "BPNZnapt\0" + /* 6785 */ "BPZnapt\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern const unsigned SparcInstrNameIndices[] = { + 2005U, 2469U, 3122U, 2709U, 2138U, 2119U, 2147U, 2294U, 1857U, 1872U, 1823U, + 1899U, 3766U, 1725U, 4401U, 1836U, 2001U, 2128U, 1558U, 4776U, 1638U, 4321U, + 1292U, 1509U, 1546U, 2820U, 2282U, 4250U, 1412U, 2927U, 1962U, 4239U, 1675U, + 2900U, 2887U, 3158U, 4064U, 4087U, 2205U, 2261U, 2234U, 2164U, 4431U, 4461U, + 1115U, 538U, 2397U, 4507U, 4514U, 2429U, 2436U, 2443U, 2453U, 1270U, 3374U, + 3337U, 1821U, 2003U, 4658U, 1735U, 4032U, 3613U, 4336U, 3630U, 3284U, 872U, + 3743U, 4261U, 3418U, 4368U, 1760U, 846U, 1347U, 4280U, 2544U, 3183U, 1003U, + 947U, 977U, 988U, 928U, 958U, 1704U, 1688U, 3789U, 1913U, 1930U, 1131U, + 544U, 1276U, 1229U, 3379U, 3343U, 4635U, 2660U, 4618U, 2643U, 1082U, 521U, + 1538U, 1319U, 4051U, 824U, 3819U, 4445U, 864U, 4198U, 4186U, 4311U, 1954U, + 4424U, 1886U, 4454U, 2191U, 3249U, 3235U, 2184U, 3242U, 3411U, 2315U, 2862U, + 2855U, 4042U, 2782U, 1579U, 2766U, 1530U, 2774U, 1571U, 2758U, 1522U, 2798U, + 2790U, 1987U, 1979U, 3950U, 3940U, 3930U, 3920U, 3970U, 3960U, 4695U, 4705U, + 3980U, 3993U, 4715U, 4725U, 4006U, 4019U, 1040U, 500U, 2339U, 469U, 921U, + 4486U, 2408U, 4528U, 2061U, 2946U, 178U, 1947U, 170U, 0U, 1850U, 4416U, + 836U, 2043U, 2052U, 2837U, 2846U, 3531U, 2566U, 1769U, 2501U, 2511U, 1587U, + 1602U, 2479U, 2490U, 1121U, 2075U, 2612U, 4587U, 2636U, 4611U, 3538U, 1338U, + 1328U, 3117U, 4111U, 4139U, 4118U, 3299U, 4788U, 1803U, 4781U, 1785U, 2879U, + 2829U, 1712U, 2197U, 3664U, 2676U, 4345U, 3275U, 4272U, 4298U, 4378U, 3145U, + 1625U, 893U, 1068U, 507U, 2367U, 4493U, 2415U, 475U, 4353U, 3202U, 3218U, + 4767U, 1654U, 1750U, 4078U, 2806U, 1047U, 2346U, 1023U, 2322U, 4553U, 2578U, + 1099U, 2381U, 1254U, 3359U, 3321U, 4570U, 2595U, 4594U, 2619U, 4672U, 4679U, + 2732U, 2912U, 4651U, 586U, 697U, 622U, 733U, 663U, 770U, 604U, 715U, + 4083U, 4900U, 5937U, 5038U, 6075U, 5129U, 6166U, 915U, 560U, 5482U, 6544U, + 5075U, 6119U, 3135U, 2299U, 4908U, 5945U, 4961U, 5998U, 5269U, 6306U, 6319U, + 5495U, 6561U, 5103U, 6140U, 401U, 156U, 422U, 429U, 1306U, 454U, 5109U, + 6146U, 2069U, 568U, 432U, 4159U, 4209U, 5608U, 6689U, 5657U, 6738U, 5626U, + 6707U, 5677U, 6758U, 681U, 439U, 4168U, 4217U, 5617U, 6698U, 5667U, 6748U, + 5634U, 6715U, 5686U, 6767U, 5642U, 6723U, 5695U, 6776U, 788U, 446U, 4177U, + 4225U, 5650U, 6731U, 5704U, 6785U, 1645U, 2220U, 5221U, 6258U, 9U, 5858U, + 6604U, 6465U, 1305U, 453U, 281U, 108U, 415U, 5296U, 6348U, 248U, 2093U, + 2692U, 2529U, 75U, 2085U, 2683U, 2521U, 409U, 2101U, 2701U, 2537U, 1429U, + 3025U, 3783U, 1147U, 2959U, 3557U, 488U, 1218U, 29U, 3436U, 186U, 3487U, + 3585U, 1312U, 461U, 303U, 1399U, 320U, 130U, 337U, 147U, 255U, 82U, + 264U, 91U, 3019U, 3712U, 1442U, 3038U, 3853U, 2980U, 2025U, 2993U, 3678U, + 4741U, 1246U, 1153U, 3563U, 1016U, 3550U, 1365U, 2999U, 3684U, 1405U, 3718U, + 1995U, 4521U, 5200U, 6237U, 312U, 1448U, 576U, 687U, 794U, 3044U, 641U, + 750U, 804U, 1454U, 3050U, 3865U, 1474U, 3070U, 3885U, 1464U, 3060U, 3875U, + 1483U, 3079U, 3894U, 1492U, 3088U, 3903U, 1501U, 3097U, 3912U, 3859U, 653U, + 760U, 814U, 390U, 367U, 346U, 2108U, 4475U, 1190U, 378U, 355U, 2987U, + 3651U, 1168U, 3578U, 1223U, 3591U, 1184U, 2974U, 3645U, 1160U, 3570U, 1196U, + 3657U, 3264U, 3730U, 38U, 3446U, 195U, 3497U, 1210U, 1670U, 3598U, 3260U, + 44U, 3453U, 201U, 3504U, 3725U, 273U, 100U, 4686U, 240U, 3522U, 67U, + 3471U, 213U, 1617U, 232U, 3513U, 59U, 3462U, 1371U, 2031U, 3690U, 4755U, + 329U, 139U, 289U, 116U, 1203U, 1435U, 3031U, 3846U, 225U, 52U, 23U, + 3429U, 164U, 3480U, 296U, 123U, 1377U, 2037U, 3005U, 4761U, 1010U, 2953U, + 3544U, 3269U, 3736U, 3316U, 3760U, 1383U, 3011U, 3704U, 2814U, 3671U, 5234U, + 6271U, 5762U, 5354U, 6406U, 5052U, 6089U, 5755U, 5045U, 6082U, 5775U, 5153U, + 6190U, 5092U, 6125U, 5783U, 5370U, 6422U, 5160U, 6197U, 5798U, 5173U, 6210U, + 5722U, 4834U, 5871U, 5821U, 5193U, 6230U, 5745U, 4860U, 5897U, 5461U, 6519U, + 5737U, 4847U, 5884U, 5836U, 5214U, 6251U, 5386U, 6438U, 5489U, 6555U, 5098U, + 6135U, 5081U, 5071U, 4233U, 4812U, 4747U, 4918U, 5955U, 4934U, 5971U, 5552U, + 6633U, 5572U, 6653U, 5562U, 6643U, 5581U, 6662U, 5590U, 6671U, 5599U, 6680U, + 4535U, 4544U, 3696U, 5029U, 6066U, 1389U, 4995U, 6032U, 5516U, 6582U, 2875U, + 4980U, 6017U, 4970U, 6007U, 5276U, 6313U, 6327U, 5524U, 6591U, 5328U, 6380U, + 4395U, 2725U, 6102U, 4795U, 5712U, 5404U, 6456U, 3399U, 910U, 3394U, 3405U, + 3111U, 2463U, 5136U, 6173U, 4074U, 2310U, 5418U, 6476U, 5146U, 6183U, 5004U, + 6041U, 5536U, 6617U, 5425U, 6483U, 4820U, 4805U, 2749U, 2403U, 3256U, 5502U, + 6568U, 5228U, 6265U, 4869U, 5906U, 4943U, 5980U, 5247U, 6284U, 5468U, 6526U, + 4828U, 5852U, 5509U, 6575U, 5241U, 6278U, 5865U, 3105U, 5730U, 4841U, 5878U, + 5362U, 6414U, 5065U, 6109U, 5768U, 5302U, 6354U, 5058U, 6095U, 5790U, 5310U, + 6362U, 5166U, 6203U, 5116U, 6153U, 5814U, 5378U, 6430U, 5187U, 6224U, 5829U, + 5208U, 6245U, 5806U, 5180U, 6217U, 5395U, 6447U, 5530U, 6611U, 5413U, 6471U, + 4891U, 5928U, 4883U, 5920U, 5122U, 6159U, 5475U, 6533U, 4854U, 5891U, 5844U, + 5289U, 6341U, 19U, 209U, 221U, 5450U, 6508U, 4899U, 5936U, 4927U, 5964U, + 6540U, 6115U, 2225U, 6551U, 6131U, 5282U, 6334U, 5439U, 6497U, 4890U, 5927U, + 5022U, 6059U, 5013U, 6050U, 5544U, 6625U, 5432U, 6490U, 4876U, 5913U, 4952U, + 5989U, 2009U, 5254U, 6291U, 2869U, 1397U, 1175U, 2965U, 3604U, 3017U, 3710U, + 574U, 639U, 651U, 4916U, 5953U, 5346U, 6398U, 5339U, 6391U, 5405U, 6457U, + 5318U, 6370U, 5261U, 6298U, 4735U, 2017U, 4978U, 6015U, 6589U, 5326U, 6378U, + 4987U, 6024U, 5523U, 6597U, 5333U, 6385U, +}; + +#endif // GET_INSTRINFO_MC_DESC diff --git a/arch/Sparc/SparcGenInstrInfo.inc b/arch/Sparc/SparcGenInstrInfo.inc index 89bf034785..02eb411102 100644 --- a/arch/Sparc/SparcGenInstrInfo.inc +++ b/arch/Sparc/SparcGenInstrInfo.inc @@ -9,506 +9,505 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ - #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { - SP_PHI = 0, - SP_INLINEASM = 1, - SP_CFI_INSTRUCTION = 2, - SP_EH_LABEL = 3, - SP_GC_LABEL = 4, - SP_KILL = 5, - SP_EXTRACT_SUBREG = 6, - SP_INSERT_SUBREG = 7, - SP_IMPLICIT_DEF = 8, - SP_SUBREG_TO_REG = 9, - SP_COPY_TO_REGCLASS = 10, - SP_DBG_VALUE = 11, - SP_REG_SEQUENCE = 12, - SP_COPY = 13, - SP_BUNDLE = 14, - SP_LIFETIME_START = 15, - SP_LIFETIME_END = 16, - SP_STACKMAP = 17, - SP_PATCHPOINT = 18, - SP_LOAD_STACK_GUARD = 19, - SP_STATEPOINT = 20, - SP_FRAME_ALLOC = 21, - SP_ADDCCri = 22, - SP_ADDCCrr = 23, - SP_ADDCri = 24, - SP_ADDCrr = 25, - SP_ADDEri = 26, - SP_ADDErr = 27, - SP_ADDXC = 28, - SP_ADDXCCC = 29, - SP_ADDXri = 30, - SP_ADDXrr = 31, - SP_ADDri = 32, - SP_ADDrr = 33, - SP_ADJCALLSTACKDOWN = 34, - SP_ADJCALLSTACKUP = 35, - SP_ALIGNADDR = 36, - SP_ALIGNADDRL = 37, - SP_ANDCCri = 38, - SP_ANDCCrr = 39, - SP_ANDNCCri = 40, - SP_ANDNCCrr = 41, - SP_ANDNri = 42, - SP_ANDNrr = 43, - SP_ANDXNrr = 44, - SP_ANDXri = 45, - SP_ANDXrr = 46, - SP_ANDri = 47, - SP_ANDrr = 48, - SP_ARRAY16 = 49, - SP_ARRAY32 = 50, - SP_ARRAY8 = 51, - SP_ATOMIC_LOAD_ADD_32 = 52, - SP_ATOMIC_LOAD_ADD_64 = 53, - SP_ATOMIC_LOAD_AND_32 = 54, - SP_ATOMIC_LOAD_AND_64 = 55, - SP_ATOMIC_LOAD_MAX_32 = 56, - SP_ATOMIC_LOAD_MAX_64 = 57, - SP_ATOMIC_LOAD_MIN_32 = 58, - SP_ATOMIC_LOAD_MIN_64 = 59, - SP_ATOMIC_LOAD_NAND_32 = 60, - SP_ATOMIC_LOAD_NAND_64 = 61, - SP_ATOMIC_LOAD_OR_32 = 62, - SP_ATOMIC_LOAD_OR_64 = 63, - SP_ATOMIC_LOAD_SUB_32 = 64, - SP_ATOMIC_LOAD_SUB_64 = 65, - SP_ATOMIC_LOAD_UMAX_32 = 66, - SP_ATOMIC_LOAD_UMAX_64 = 67, - SP_ATOMIC_LOAD_UMIN_32 = 68, - SP_ATOMIC_LOAD_UMIN_64 = 69, - SP_ATOMIC_LOAD_XOR_32 = 70, - SP_ATOMIC_LOAD_XOR_64 = 71, - SP_ATOMIC_SWAP_64 = 72, - SP_BA = 73, - SP_BCOND = 74, - SP_BCONDA = 75, - SP_BINDri = 76, - SP_BINDrr = 77, - SP_BMASK = 78, - SP_BPFCC = 79, - SP_BPFCCA = 80, - SP_BPFCCANT = 81, - SP_BPFCCNT = 82, - SP_BPGEZapn = 83, - SP_BPGEZapt = 84, - SP_BPGEZnapn = 85, - SP_BPGEZnapt = 86, - SP_BPGZapn = 87, - SP_BPGZapt = 88, - SP_BPGZnapn = 89, - SP_BPGZnapt = 90, - SP_BPICC = 91, - SP_BPICCA = 92, - SP_BPICCANT = 93, - SP_BPICCNT = 94, - SP_BPLEZapn = 95, - SP_BPLEZapt = 96, - SP_BPLEZnapn = 97, - SP_BPLEZnapt = 98, - SP_BPLZapn = 99, - SP_BPLZapt = 100, - SP_BPLZnapn = 101, - SP_BPLZnapt = 102, - SP_BPNZapn = 103, - SP_BPNZapt = 104, - SP_BPNZnapn = 105, - SP_BPNZnapt = 106, - SP_BPXCC = 107, - SP_BPXCCA = 108, - SP_BPXCCANT = 109, - SP_BPXCCNT = 110, - SP_BPZapn = 111, - SP_BPZapt = 112, - SP_BPZnapn = 113, - SP_BPZnapt = 114, - SP_BSHUFFLE = 115, - SP_CALL = 116, - SP_CALLri = 117, - SP_CALLrr = 118, - SP_CASXrr = 119, - SP_CASrr = 120, - SP_CMASK16 = 121, - SP_CMASK32 = 122, - SP_CMASK8 = 123, - SP_CMPri = 124, - SP_CMPrr = 125, - SP_EDGE16 = 126, - SP_EDGE16L = 127, - SP_EDGE16LN = 128, - SP_EDGE16N = 129, - SP_EDGE32 = 130, - SP_EDGE32L = 131, - SP_EDGE32LN = 132, - SP_EDGE32N = 133, - SP_EDGE8 = 134, - SP_EDGE8L = 135, - SP_EDGE8LN = 136, - SP_EDGE8N = 137, - SP_FABSD = 138, - SP_FABSQ = 139, - SP_FABSS = 140, - SP_FADDD = 141, - SP_FADDQ = 142, - SP_FADDS = 143, - SP_FALIGNADATA = 144, - SP_FAND = 145, - SP_FANDNOT1 = 146, - SP_FANDNOT1S = 147, - SP_FANDNOT2 = 148, - SP_FANDNOT2S = 149, - SP_FANDS = 150, - SP_FBCOND = 151, - SP_FBCONDA = 152, - SP_FCHKSM16 = 153, - SP_FCMPD = 154, - SP_FCMPEQ16 = 155, - SP_FCMPEQ32 = 156, - SP_FCMPGT16 = 157, - SP_FCMPGT32 = 158, - SP_FCMPLE16 = 159, - SP_FCMPLE32 = 160, - SP_FCMPNE16 = 161, - SP_FCMPNE32 = 162, - SP_FCMPQ = 163, - SP_FCMPS = 164, - SP_FDIVD = 165, - SP_FDIVQ = 166, - SP_FDIVS = 167, - SP_FDMULQ = 168, - SP_FDTOI = 169, - SP_FDTOQ = 170, - SP_FDTOS = 171, - SP_FDTOX = 172, - SP_FEXPAND = 173, - SP_FHADDD = 174, - SP_FHADDS = 175, - SP_FHSUBD = 176, - SP_FHSUBS = 177, - SP_FITOD = 178, - SP_FITOQ = 179, - SP_FITOS = 180, - SP_FLCMPD = 181, - SP_FLCMPS = 182, - SP_FLUSHW = 183, - SP_FMEAN16 = 184, - SP_FMOVD = 185, - SP_FMOVD_FCC = 186, - SP_FMOVD_ICC = 187, - SP_FMOVD_XCC = 188, - SP_FMOVQ = 189, - SP_FMOVQ_FCC = 190, - SP_FMOVQ_ICC = 191, - SP_FMOVQ_XCC = 192, - SP_FMOVRGEZD = 193, - SP_FMOVRGEZQ = 194, - SP_FMOVRGEZS = 195, - SP_FMOVRGZD = 196, - SP_FMOVRGZQ = 197, - SP_FMOVRGZS = 198, - SP_FMOVRLEZD = 199, - SP_FMOVRLEZQ = 200, - SP_FMOVRLEZS = 201, - SP_FMOVRLZD = 202, - SP_FMOVRLZQ = 203, - SP_FMOVRLZS = 204, - SP_FMOVRNZD = 205, - SP_FMOVRNZQ = 206, - SP_FMOVRNZS = 207, - SP_FMOVRZD = 208, - SP_FMOVRZQ = 209, - SP_FMOVRZS = 210, - SP_FMOVS = 211, - SP_FMOVS_FCC = 212, - SP_FMOVS_ICC = 213, - SP_FMOVS_XCC = 214, - SP_FMUL8SUX16 = 215, - SP_FMUL8ULX16 = 216, - SP_FMUL8X16 = 217, - SP_FMUL8X16AL = 218, - SP_FMUL8X16AU = 219, - SP_FMULD = 220, - SP_FMULD8SUX16 = 221, - SP_FMULD8ULX16 = 222, - SP_FMULQ = 223, - SP_FMULS = 224, - SP_FNADDD = 225, - SP_FNADDS = 226, - SP_FNAND = 227, - SP_FNANDS = 228, - SP_FNEGD = 229, - SP_FNEGQ = 230, - SP_FNEGS = 231, - SP_FNHADDD = 232, - SP_FNHADDS = 233, - SP_FNMULD = 234, - SP_FNMULS = 235, - SP_FNOR = 236, - SP_FNORS = 237, - SP_FNOT1 = 238, - SP_FNOT1S = 239, - SP_FNOT2 = 240, - SP_FNOT2S = 241, - SP_FNSMULD = 242, - SP_FONE = 243, - SP_FONES = 244, - SP_FOR = 245, - SP_FORNOT1 = 246, - SP_FORNOT1S = 247, - SP_FORNOT2 = 248, - SP_FORNOT2S = 249, - SP_FORS = 250, - SP_FPACK16 = 251, - SP_FPACK32 = 252, - SP_FPACKFIX = 253, - SP_FPADD16 = 254, - SP_FPADD16S = 255, - SP_FPADD32 = 256, - SP_FPADD32S = 257, - SP_FPADD64 = 258, - SP_FPMERGE = 259, - SP_FPSUB16 = 260, - SP_FPSUB16S = 261, - SP_FPSUB32 = 262, - SP_FPSUB32S = 263, - SP_FQTOD = 264, - SP_FQTOI = 265, - SP_FQTOS = 266, - SP_FQTOX = 267, - SP_FSLAS16 = 268, - SP_FSLAS32 = 269, - SP_FSLL16 = 270, - SP_FSLL32 = 271, - SP_FSMULD = 272, - SP_FSQRTD = 273, - SP_FSQRTQ = 274, - SP_FSQRTS = 275, - SP_FSRA16 = 276, - SP_FSRA32 = 277, - SP_FSRC1 = 278, - SP_FSRC1S = 279, - SP_FSRC2 = 280, - SP_FSRC2S = 281, - SP_FSRL16 = 282, - SP_FSRL32 = 283, - SP_FSTOD = 284, - SP_FSTOI = 285, - SP_FSTOQ = 286, - SP_FSTOX = 287, - SP_FSUBD = 288, - SP_FSUBQ = 289, - SP_FSUBS = 290, - SP_FXNOR = 291, - SP_FXNORS = 292, - SP_FXOR = 293, - SP_FXORS = 294, - SP_FXTOD = 295, - SP_FXTOQ = 296, - SP_FXTOS = 297, - SP_FZERO = 298, - SP_FZEROS = 299, - SP_GETPCX = 300, - SP_JMPLri = 301, - SP_JMPLrr = 302, - SP_LDDFri = 303, - SP_LDDFrr = 304, - SP_LDFri = 305, - SP_LDFrr = 306, - SP_LDQFri = 307, - SP_LDQFrr = 308, - SP_LDSBri = 309, - SP_LDSBrr = 310, - SP_LDSHri = 311, - SP_LDSHrr = 312, - SP_LDSWri = 313, - SP_LDSWrr = 314, - SP_LDUBri = 315, - SP_LDUBrr = 316, - SP_LDUHri = 317, - SP_LDUHrr = 318, - SP_LDXri = 319, - SP_LDXrr = 320, - SP_LDri = 321, - SP_LDrr = 322, - SP_LEAX_ADDri = 323, - SP_LEA_ADDri = 324, - SP_LZCNT = 325, - SP_MEMBARi = 326, - SP_MOVDTOX = 327, - SP_MOVFCCri = 328, - SP_MOVFCCrr = 329, - SP_MOVICCri = 330, - SP_MOVICCrr = 331, - SP_MOVRGEZri = 332, - SP_MOVRGEZrr = 333, - SP_MOVRGZri = 334, - SP_MOVRGZrr = 335, - SP_MOVRLEZri = 336, - SP_MOVRLEZrr = 337, - SP_MOVRLZri = 338, - SP_MOVRLZrr = 339, - SP_MOVRNZri = 340, - SP_MOVRNZrr = 341, - SP_MOVRRZri = 342, - SP_MOVRRZrr = 343, - SP_MOVSTOSW = 344, - SP_MOVSTOUW = 345, - SP_MOVWTOS = 346, - SP_MOVXCCri = 347, - SP_MOVXCCrr = 348, - SP_MOVXTOD = 349, - SP_MULXri = 350, - SP_MULXrr = 351, - SP_NOP = 352, - SP_ORCCri = 353, - SP_ORCCrr = 354, - SP_ORNCCri = 355, - SP_ORNCCrr = 356, - SP_ORNri = 357, - SP_ORNrr = 358, - SP_ORXNrr = 359, - SP_ORXri = 360, - SP_ORXrr = 361, - SP_ORri = 362, - SP_ORrr = 363, - SP_PDIST = 364, - SP_PDISTN = 365, - SP_POPCrr = 366, - SP_RDY = 367, - SP_RESTOREri = 368, - SP_RESTORErr = 369, - SP_RET = 370, - SP_RETL = 371, - SP_RETTri = 372, - SP_RETTrr = 373, - SP_SAVEri = 374, - SP_SAVErr = 375, - SP_SDIVCCri = 376, - SP_SDIVCCrr = 377, - SP_SDIVXri = 378, - SP_SDIVXrr = 379, - SP_SDIVri = 380, - SP_SDIVrr = 381, - SP_SELECT_CC_DFP_FCC = 382, - SP_SELECT_CC_DFP_ICC = 383, - SP_SELECT_CC_FP_FCC = 384, - SP_SELECT_CC_FP_ICC = 385, - SP_SELECT_CC_Int_FCC = 386, - SP_SELECT_CC_Int_ICC = 387, - SP_SELECT_CC_QFP_FCC = 388, - SP_SELECT_CC_QFP_ICC = 389, - SP_SETHIXi = 390, - SP_SETHIi = 391, - SP_SHUTDOWN = 392, - SP_SIAM = 393, - SP_SLLXri = 394, - SP_SLLXrr = 395, - SP_SLLri = 396, - SP_SLLrr = 397, - SP_SMULCCri = 398, - SP_SMULCCrr = 399, - SP_SMULri = 400, - SP_SMULrr = 401, - SP_SRAXri = 402, - SP_SRAXrr = 403, - SP_SRAri = 404, - SP_SRArr = 405, - SP_SRLXri = 406, - SP_SRLXrr = 407, - SP_SRLri = 408, - SP_SRLrr = 409, - SP_STBAR = 410, - SP_STBri = 411, - SP_STBrr = 412, - SP_STDFri = 413, - SP_STDFrr = 414, - SP_STFri = 415, - SP_STFrr = 416, - SP_STHri = 417, - SP_STHrr = 418, - SP_STQFri = 419, - SP_STQFrr = 420, - SP_STXri = 421, - SP_STXrr = 422, - SP_STri = 423, - SP_STrr = 424, - SP_SUBCCri = 425, - SP_SUBCCrr = 426, - SP_SUBCri = 427, - SP_SUBCrr = 428, - SP_SUBEri = 429, - SP_SUBErr = 430, - SP_SUBXri = 431, - SP_SUBXrr = 432, - SP_SUBri = 433, - SP_SUBrr = 434, - SP_SWAPri = 435, - SP_SWAPrr = 436, - SP_TA3 = 437, - SP_TA5 = 438, - SP_TADDCCTVri = 439, - SP_TADDCCTVrr = 440, - SP_TADDCCri = 441, - SP_TADDCCrr = 442, - SP_TICCri = 443, - SP_TICCrr = 444, - SP_TLS_ADDXrr = 445, - SP_TLS_ADDrr = 446, - SP_TLS_CALL = 447, - SP_TLS_LDXrr = 448, - SP_TLS_LDrr = 449, - SP_TSUBCCTVri = 450, - SP_TSUBCCTVrr = 451, - SP_TSUBCCri = 452, - SP_TSUBCCrr = 453, - SP_TXCCri = 454, - SP_TXCCrr = 455, - SP_UDIVCCri = 456, - SP_UDIVCCrr = 457, - SP_UDIVXri = 458, - SP_UDIVXrr = 459, - SP_UDIVri = 460, - SP_UDIVrr = 461, - SP_UMULCCri = 462, - SP_UMULCCrr = 463, - SP_UMULXHI = 464, - SP_UMULri = 465, - SP_UMULrr = 466, - SP_UNIMP = 467, - SP_V9FCMPD = 468, - SP_V9FCMPED = 469, - SP_V9FCMPEQ = 470, - SP_V9FCMPES = 471, - SP_V9FCMPQ = 472, - SP_V9FCMPS = 473, - SP_V9FMOVD_FCC = 474, - SP_V9FMOVQ_FCC = 475, - SP_V9FMOVS_FCC = 476, - SP_V9MOVFCCri = 477, - SP_V9MOVFCCrr = 478, - SP_WRYri = 479, - SP_WRYrr = 480, - SP_XMULX = 481, - SP_XMULXHI = 482, - SP_XNORCCri = 483, - SP_XNORCCrr = 484, - SP_XNORXrr = 485, - SP_XNORri = 486, - SP_XNORrr = 487, - SP_XORCCri = 488, - SP_XORCCrr = 489, - SP_XORXri = 490, - SP_XORXrr = 491, - SP_XORri = 492, - SP_XORrr = 493, - SP_INSTRUCTION_LIST_END = 494 + SP_PHI = 0, + SP_INLINEASM = 1, + SP_CFI_INSTRUCTION = 2, + SP_EH_LABEL = 3, + SP_GC_LABEL = 4, + SP_KILL = 5, + SP_EXTRACT_SUBREG = 6, + SP_INSERT_SUBREG = 7, + SP_IMPLICIT_DEF = 8, + SP_SUBREG_TO_REG = 9, + SP_COPY_TO_REGCLASS = 10, + SP_DBG_VALUE = 11, + SP_REG_SEQUENCE = 12, + SP_COPY = 13, + SP_BUNDLE = 14, + SP_LIFETIME_START = 15, + SP_LIFETIME_END = 16, + SP_STACKMAP = 17, + SP_PATCHPOINT = 18, + SP_LOAD_STACK_GUARD = 19, + SP_STATEPOINT = 20, + SP_FRAME_ALLOC = 21, + SP_ADDCCri = 22, + SP_ADDCCrr = 23, + SP_ADDCri = 24, + SP_ADDCrr = 25, + SP_ADDEri = 26, + SP_ADDErr = 27, + SP_ADDXC = 28, + SP_ADDXCCC = 29, + SP_ADDXri = 30, + SP_ADDXrr = 31, + SP_ADDri = 32, + SP_ADDrr = 33, + SP_ADJCALLSTACKDOWN = 34, + SP_ADJCALLSTACKUP = 35, + SP_ALIGNADDR = 36, + SP_ALIGNADDRL = 37, + SP_ANDCCri = 38, + SP_ANDCCrr = 39, + SP_ANDNCCri = 40, + SP_ANDNCCrr = 41, + SP_ANDNri = 42, + SP_ANDNrr = 43, + SP_ANDXNrr = 44, + SP_ANDXri = 45, + SP_ANDXrr = 46, + SP_ANDri = 47, + SP_ANDrr = 48, + SP_ARRAY16 = 49, + SP_ARRAY32 = 50, + SP_ARRAY8 = 51, + SP_ATOMIC_LOAD_ADD_32 = 52, + SP_ATOMIC_LOAD_ADD_64 = 53, + SP_ATOMIC_LOAD_AND_32 = 54, + SP_ATOMIC_LOAD_AND_64 = 55, + SP_ATOMIC_LOAD_MAX_32 = 56, + SP_ATOMIC_LOAD_MAX_64 = 57, + SP_ATOMIC_LOAD_MIN_32 = 58, + SP_ATOMIC_LOAD_MIN_64 = 59, + SP_ATOMIC_LOAD_NAND_32 = 60, + SP_ATOMIC_LOAD_NAND_64 = 61, + SP_ATOMIC_LOAD_OR_32 = 62, + SP_ATOMIC_LOAD_OR_64 = 63, + SP_ATOMIC_LOAD_SUB_32 = 64, + SP_ATOMIC_LOAD_SUB_64 = 65, + SP_ATOMIC_LOAD_UMAX_32 = 66, + SP_ATOMIC_LOAD_UMAX_64 = 67, + SP_ATOMIC_LOAD_UMIN_32 = 68, + SP_ATOMIC_LOAD_UMIN_64 = 69, + SP_ATOMIC_LOAD_XOR_32 = 70, + SP_ATOMIC_LOAD_XOR_64 = 71, + SP_ATOMIC_SWAP_64 = 72, + SP_BA = 73, + SP_BCOND = 74, + SP_BCONDA = 75, + SP_BINDri = 76, + SP_BINDrr = 77, + SP_BMASK = 78, + SP_BPFCC = 79, + SP_BPFCCA = 80, + SP_BPFCCANT = 81, + SP_BPFCCNT = 82, + SP_BPGEZapn = 83, + SP_BPGEZapt = 84, + SP_BPGEZnapn = 85, + SP_BPGEZnapt = 86, + SP_BPGZapn = 87, + SP_BPGZapt = 88, + SP_BPGZnapn = 89, + SP_BPGZnapt = 90, + SP_BPICC = 91, + SP_BPICCA = 92, + SP_BPICCANT = 93, + SP_BPICCNT = 94, + SP_BPLEZapn = 95, + SP_BPLEZapt = 96, + SP_BPLEZnapn = 97, + SP_BPLEZnapt = 98, + SP_BPLZapn = 99, + SP_BPLZapt = 100, + SP_BPLZnapn = 101, + SP_BPLZnapt = 102, + SP_BPNZapn = 103, + SP_BPNZapt = 104, + SP_BPNZnapn = 105, + SP_BPNZnapt = 106, + SP_BPXCC = 107, + SP_BPXCCA = 108, + SP_BPXCCANT = 109, + SP_BPXCCNT = 110, + SP_BPZapn = 111, + SP_BPZapt = 112, + SP_BPZnapn = 113, + SP_BPZnapt = 114, + SP_BSHUFFLE = 115, + SP_CALL = 116, + SP_CALLri = 117, + SP_CALLrr = 118, + SP_CASXrr = 119, + SP_CASrr = 120, + SP_CMASK16 = 121, + SP_CMASK32 = 122, + SP_CMASK8 = 123, + SP_CMPri = 124, + SP_CMPrr = 125, + SP_EDGE16 = 126, + SP_EDGE16L = 127, + SP_EDGE16LN = 128, + SP_EDGE16N = 129, + SP_EDGE32 = 130, + SP_EDGE32L = 131, + SP_EDGE32LN = 132, + SP_EDGE32N = 133, + SP_EDGE8 = 134, + SP_EDGE8L = 135, + SP_EDGE8LN = 136, + SP_EDGE8N = 137, + SP_FABSD = 138, + SP_FABSQ = 139, + SP_FABSS = 140, + SP_FADDD = 141, + SP_FADDQ = 142, + SP_FADDS = 143, + SP_FALIGNADATA = 144, + SP_FAND = 145, + SP_FANDNOT1 = 146, + SP_FANDNOT1S = 147, + SP_FANDNOT2 = 148, + SP_FANDNOT2S = 149, + SP_FANDS = 150, + SP_FBCOND = 151, + SP_FBCONDA = 152, + SP_FCHKSM16 = 153, + SP_FCMPD = 154, + SP_FCMPEQ16 = 155, + SP_FCMPEQ32 = 156, + SP_FCMPGT16 = 157, + SP_FCMPGT32 = 158, + SP_FCMPLE16 = 159, + SP_FCMPLE32 = 160, + SP_FCMPNE16 = 161, + SP_FCMPNE32 = 162, + SP_FCMPQ = 163, + SP_FCMPS = 164, + SP_FDIVD = 165, + SP_FDIVQ = 166, + SP_FDIVS = 167, + SP_FDMULQ = 168, + SP_FDTOI = 169, + SP_FDTOQ = 170, + SP_FDTOS = 171, + SP_FDTOX = 172, + SP_FEXPAND = 173, + SP_FHADDD = 174, + SP_FHADDS = 175, + SP_FHSUBD = 176, + SP_FHSUBS = 177, + SP_FITOD = 178, + SP_FITOQ = 179, + SP_FITOS = 180, + SP_FLCMPD = 181, + SP_FLCMPS = 182, + SP_FLUSHW = 183, + SP_FMEAN16 = 184, + SP_FMOVD = 185, + SP_FMOVD_FCC = 186, + SP_FMOVD_ICC = 187, + SP_FMOVD_XCC = 188, + SP_FMOVQ = 189, + SP_FMOVQ_FCC = 190, + SP_FMOVQ_ICC = 191, + SP_FMOVQ_XCC = 192, + SP_FMOVRGEZD = 193, + SP_FMOVRGEZQ = 194, + SP_FMOVRGEZS = 195, + SP_FMOVRGZD = 196, + SP_FMOVRGZQ = 197, + SP_FMOVRGZS = 198, + SP_FMOVRLEZD = 199, + SP_FMOVRLEZQ = 200, + SP_FMOVRLEZS = 201, + SP_FMOVRLZD = 202, + SP_FMOVRLZQ = 203, + SP_FMOVRLZS = 204, + SP_FMOVRNZD = 205, + SP_FMOVRNZQ = 206, + SP_FMOVRNZS = 207, + SP_FMOVRZD = 208, + SP_FMOVRZQ = 209, + SP_FMOVRZS = 210, + SP_FMOVS = 211, + SP_FMOVS_FCC = 212, + SP_FMOVS_ICC = 213, + SP_FMOVS_XCC = 214, + SP_FMUL8SUX16 = 215, + SP_FMUL8ULX16 = 216, + SP_FMUL8X16 = 217, + SP_FMUL8X16AL = 218, + SP_FMUL8X16AU = 219, + SP_FMULD = 220, + SP_FMULD8SUX16 = 221, + SP_FMULD8ULX16 = 222, + SP_FMULQ = 223, + SP_FMULS = 224, + SP_FNADDD = 225, + SP_FNADDS = 226, + SP_FNAND = 227, + SP_FNANDS = 228, + SP_FNEGD = 229, + SP_FNEGQ = 230, + SP_FNEGS = 231, + SP_FNHADDD = 232, + SP_FNHADDS = 233, + SP_FNMULD = 234, + SP_FNMULS = 235, + SP_FNOR = 236, + SP_FNORS = 237, + SP_FNOT1 = 238, + SP_FNOT1S = 239, + SP_FNOT2 = 240, + SP_FNOT2S = 241, + SP_FNSMULD = 242, + SP_FONE = 243, + SP_FONES = 244, + SP_FOR = 245, + SP_FORNOT1 = 246, + SP_FORNOT1S = 247, + SP_FORNOT2 = 248, + SP_FORNOT2S = 249, + SP_FORS = 250, + SP_FPACK16 = 251, + SP_FPACK32 = 252, + SP_FPACKFIX = 253, + SP_FPADD16 = 254, + SP_FPADD16S = 255, + SP_FPADD32 = 256, + SP_FPADD32S = 257, + SP_FPADD64 = 258, + SP_FPMERGE = 259, + SP_FPSUB16 = 260, + SP_FPSUB16S = 261, + SP_FPSUB32 = 262, + SP_FPSUB32S = 263, + SP_FQTOD = 264, + SP_FQTOI = 265, + SP_FQTOS = 266, + SP_FQTOX = 267, + SP_FSLAS16 = 268, + SP_FSLAS32 = 269, + SP_FSLL16 = 270, + SP_FSLL32 = 271, + SP_FSMULD = 272, + SP_FSQRTD = 273, + SP_FSQRTQ = 274, + SP_FSQRTS = 275, + SP_FSRA16 = 276, + SP_FSRA32 = 277, + SP_FSRC1 = 278, + SP_FSRC1S = 279, + SP_FSRC2 = 280, + SP_FSRC2S = 281, + SP_FSRL16 = 282, + SP_FSRL32 = 283, + SP_FSTOD = 284, + SP_FSTOI = 285, + SP_FSTOQ = 286, + SP_FSTOX = 287, + SP_FSUBD = 288, + SP_FSUBQ = 289, + SP_FSUBS = 290, + SP_FXNOR = 291, + SP_FXNORS = 292, + SP_FXOR = 293, + SP_FXORS = 294, + SP_FXTOD = 295, + SP_FXTOQ = 296, + SP_FXTOS = 297, + SP_FZERO = 298, + SP_FZEROS = 299, + SP_GETPCX = 300, + SP_JMPLri = 301, + SP_JMPLrr = 302, + SP_LDDFri = 303, + SP_LDDFrr = 304, + SP_LDFri = 305, + SP_LDFrr = 306, + SP_LDQFri = 307, + SP_LDQFrr = 308, + SP_LDSBri = 309, + SP_LDSBrr = 310, + SP_LDSHri = 311, + SP_LDSHrr = 312, + SP_LDSWri = 313, + SP_LDSWrr = 314, + SP_LDUBri = 315, + SP_LDUBrr = 316, + SP_LDUHri = 317, + SP_LDUHrr = 318, + SP_LDXri = 319, + SP_LDXrr = 320, + SP_LDri = 321, + SP_LDrr = 322, + SP_LEAX_ADDri = 323, + SP_LEA_ADDri = 324, + SP_LZCNT = 325, + SP_MEMBARi = 326, + SP_MOVDTOX = 327, + SP_MOVFCCri = 328, + SP_MOVFCCrr = 329, + SP_MOVICCri = 330, + SP_MOVICCrr = 331, + SP_MOVRGEZri = 332, + SP_MOVRGEZrr = 333, + SP_MOVRGZri = 334, + SP_MOVRGZrr = 335, + SP_MOVRLEZri = 336, + SP_MOVRLEZrr = 337, + SP_MOVRLZri = 338, + SP_MOVRLZrr = 339, + SP_MOVRNZri = 340, + SP_MOVRNZrr = 341, + SP_MOVRRZri = 342, + SP_MOVRRZrr = 343, + SP_MOVSTOSW = 344, + SP_MOVSTOUW = 345, + SP_MOVWTOS = 346, + SP_MOVXCCri = 347, + SP_MOVXCCrr = 348, + SP_MOVXTOD = 349, + SP_MULXri = 350, + SP_MULXrr = 351, + SP_NOP = 352, + SP_ORCCri = 353, + SP_ORCCrr = 354, + SP_ORNCCri = 355, + SP_ORNCCrr = 356, + SP_ORNri = 357, + SP_ORNrr = 358, + SP_ORXNrr = 359, + SP_ORXri = 360, + SP_ORXrr = 361, + SP_ORri = 362, + SP_ORrr = 363, + SP_PDIST = 364, + SP_PDISTN = 365, + SP_POPCrr = 366, + SP_RDY = 367, + SP_RESTOREri = 368, + SP_RESTORErr = 369, + SP_RET = 370, + SP_RETL = 371, + SP_RETTri = 372, + SP_RETTrr = 373, + SP_SAVEri = 374, + SP_SAVErr = 375, + SP_SDIVCCri = 376, + SP_SDIVCCrr = 377, + SP_SDIVXri = 378, + SP_SDIVXrr = 379, + SP_SDIVri = 380, + SP_SDIVrr = 381, + SP_SELECT_CC_DFP_FCC = 382, + SP_SELECT_CC_DFP_ICC = 383, + SP_SELECT_CC_FP_FCC = 384, + SP_SELECT_CC_FP_ICC = 385, + SP_SELECT_CC_Int_FCC = 386, + SP_SELECT_CC_Int_ICC = 387, + SP_SELECT_CC_QFP_FCC = 388, + SP_SELECT_CC_QFP_ICC = 389, + SP_SETHIXi = 390, + SP_SETHIi = 391, + SP_SHUTDOWN = 392, + SP_SIAM = 393, + SP_SLLXri = 394, + SP_SLLXrr = 395, + SP_SLLri = 396, + SP_SLLrr = 397, + SP_SMULCCri = 398, + SP_SMULCCrr = 399, + SP_SMULri = 400, + SP_SMULrr = 401, + SP_SRAXri = 402, + SP_SRAXrr = 403, + SP_SRAri = 404, + SP_SRArr = 405, + SP_SRLXri = 406, + SP_SRLXrr = 407, + SP_SRLri = 408, + SP_SRLrr = 409, + SP_STBAR = 410, + SP_STBri = 411, + SP_STBrr = 412, + SP_STDFri = 413, + SP_STDFrr = 414, + SP_STFri = 415, + SP_STFrr = 416, + SP_STHri = 417, + SP_STHrr = 418, + SP_STQFri = 419, + SP_STQFrr = 420, + SP_STXri = 421, + SP_STXrr = 422, + SP_STri = 423, + SP_STrr = 424, + SP_SUBCCri = 425, + SP_SUBCCrr = 426, + SP_SUBCri = 427, + SP_SUBCrr = 428, + SP_SUBEri = 429, + SP_SUBErr = 430, + SP_SUBXri = 431, + SP_SUBXrr = 432, + SP_SUBri = 433, + SP_SUBrr = 434, + SP_SWAPri = 435, + SP_SWAPrr = 436, + SP_TA3 = 437, + SP_TA5 = 438, + SP_TADDCCTVri = 439, + SP_TADDCCTVrr = 440, + SP_TADDCCri = 441, + SP_TADDCCrr = 442, + SP_TICCri = 443, + SP_TICCrr = 444, + SP_TLS_ADDXrr = 445, + SP_TLS_ADDrr = 446, + SP_TLS_CALL = 447, + SP_TLS_LDXrr = 448, + SP_TLS_LDrr = 449, + SP_TSUBCCTVri = 450, + SP_TSUBCCTVrr = 451, + SP_TSUBCCri = 452, + SP_TSUBCCrr = 453, + SP_TXCCri = 454, + SP_TXCCrr = 455, + SP_UDIVCCri = 456, + SP_UDIVCCrr = 457, + SP_UDIVXri = 458, + SP_UDIVXrr = 459, + SP_UDIVri = 460, + SP_UDIVrr = 461, + SP_UMULCCri = 462, + SP_UMULCCrr = 463, + SP_UMULXHI = 464, + SP_UMULri = 465, + SP_UMULrr = 466, + SP_UNIMP = 467, + SP_V9FCMPD = 468, + SP_V9FCMPED = 469, + SP_V9FCMPEQ = 470, + SP_V9FCMPES = 471, + SP_V9FCMPQ = 472, + SP_V9FCMPS = 473, + SP_V9FMOVD_FCC = 474, + SP_V9FMOVQ_FCC = 475, + SP_V9FMOVS_FCC = 476, + SP_V9MOVFCCri = 477, + SP_V9MOVFCCrr = 478, + SP_WRYri = 479, + SP_WRYrr = 480, + SP_XMULX = 481, + SP_XMULXHI = 482, + SP_XNORCCri = 483, + SP_XNORCCrr = 484, + SP_XNORXrr = 485, + SP_XNORri = 486, + SP_XNORrr = 487, + SP_XORCCri = 488, + SP_XORCCrr = 489, + SP_XORXri = 490, + SP_XORXrr = 491, + SP_XORri = 492, + SP_XORrr = 493, + SP_INSTRUCTION_LIST_END = 494 }; #endif // GET_INSTRINFO_ENUM diff --git a/arch/Sparc/SparcGenRegisterInfo.inc b/arch/Sparc/SparcGenRegisterInfo.inc index 8b51efca07..c045de8562 100644 --- a/arch/Sparc/SparcGenRegisterInfo.inc +++ b/arch/Sparc/SparcGenRegisterInfo.inc @@ -9,7 +9,6 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ - #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM @@ -133,7 +132,7 @@ enum { SP_Q13 = 116, SP_Q14 = 117, SP_Q15 = 118, - SP_NUM_TARGET_REGS // 119 + SP_NUM_TARGET_REGS // 119 }; // Register classes @@ -158,294 +157,258 @@ enum { |* *| \*===----------------------------------------------------------------------===*/ - #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg SparcRegDiffLists[] = { - /* 0 */ 65126, 1, 1, 1, 0, - /* 5 */ 32, 1, 0, - /* 8 */ 65436, 32, 1, 65504, 33, 1, 0, - /* 15 */ 34, 1, 0, - /* 18 */ 65437, 34, 1, 65502, 35, 1, 0, - /* 25 */ 36, 1, 0, - /* 28 */ 65438, 36, 1, 65500, 37, 1, 0, - /* 35 */ 38, 1, 0, - /* 38 */ 65439, 38, 1, 65498, 39, 1, 0, - /* 45 */ 40, 1, 0, - /* 48 */ 65440, 40, 1, 65496, 41, 1, 0, - /* 55 */ 42, 1, 0, - /* 58 */ 65441, 42, 1, 65494, 43, 1, 0, - /* 65 */ 44, 1, 0, - /* 68 */ 65442, 44, 1, 65492, 45, 1, 0, - /* 75 */ 46, 1, 0, - /* 78 */ 65443, 46, 1, 65490, 47, 1, 0, - /* 85 */ 65348, 1, 0, - /* 88 */ 65444, 1, 0, - /* 91 */ 65445, 1, 0, - /* 94 */ 65446, 1, 0, - /* 97 */ 65447, 1, 0, - /* 100 */ 65448, 1, 0, - /* 103 */ 65449, 1, 0, - /* 106 */ 65450, 1, 0, - /* 109 */ 65451, 1, 0, - /* 112 */ 65532, 1, 0, - /* 115 */ 15, 0, - /* 117 */ 84, 0, - /* 119 */ 85, 0, - /* 121 */ 86, 0, - /* 123 */ 87, 0, - /* 125 */ 88, 0, - /* 127 */ 89, 0, - /* 129 */ 90, 0, - /* 131 */ 91, 0, - /* 133 */ 65488, 92, 0, - /* 136 */ 65489, 92, 0, - /* 139 */ 65489, 93, 0, - /* 142 */ 65490, 93, 0, - /* 145 */ 65491, 93, 0, - /* 148 */ 65491, 94, 0, - /* 151 */ 65492, 94, 0, - /* 154 */ 65493, 94, 0, - /* 157 */ 65493, 95, 0, - /* 160 */ 65494, 95, 0, - /* 163 */ 65495, 95, 0, - /* 166 */ 65495, 96, 0, - /* 169 */ 65496, 96, 0, - /* 172 */ 65497, 96, 0, - /* 175 */ 65497, 97, 0, - /* 178 */ 65498, 97, 0, - /* 181 */ 65499, 97, 0, - /* 184 */ 65499, 98, 0, - /* 187 */ 65500, 98, 0, - /* 190 */ 65501, 98, 0, - /* 193 */ 65501, 99, 0, - /* 196 */ 65502, 99, 0, - /* 199 */ 65503, 99, 0, - /* 202 */ 65503, 100, 0, - /* 205 */ 65504, 100, 0, - /* 208 */ 65503, 0, - /* 210 */ 65519, 0, - /* 212 */ 65535, 0, + /* 0 */ 65126, 1, 1, 1, 0, + /* 5 */ 32, 1, 0, + /* 8 */ 65436, 32, 1, 65504, 33, 1, 0, + /* 15 */ 34, 1, 0, + /* 18 */ 65437, 34, 1, 65502, 35, 1, 0, + /* 25 */ 36, 1, 0, + /* 28 */ 65438, 36, 1, 65500, 37, 1, 0, + /* 35 */ 38, 1, 0, + /* 38 */ 65439, 38, 1, 65498, 39, 1, 0, + /* 45 */ 40, 1, 0, + /* 48 */ 65440, 40, 1, 65496, 41, 1, 0, + /* 55 */ 42, 1, 0, + /* 58 */ 65441, 42, 1, 65494, 43, 1, 0, + /* 65 */ 44, 1, 0, + /* 68 */ 65442, 44, 1, 65492, 45, 1, 0, + /* 75 */ 46, 1, 0, + /* 78 */ 65443, 46, 1, 65490, 47, 1, 0, + /* 85 */ 65348, 1, 0, + /* 88 */ 65444, 1, 0, + /* 91 */ 65445, 1, 0, + /* 94 */ 65446, 1, 0, + /* 97 */ 65447, 1, 0, + /* 100 */ 65448, 1, 0, + /* 103 */ 65449, 1, 0, + /* 106 */ 65450, 1, 0, + /* 109 */ 65451, 1, 0, + /* 112 */ 65532, 1, 0, + /* 115 */ 15, 0, + /* 117 */ 84, 0, + /* 119 */ 85, 0, + /* 121 */ 86, 0, + /* 123 */ 87, 0, + /* 125 */ 88, 0, + /* 127 */ 89, 0, + /* 129 */ 90, 0, + /* 131 */ 91, 0, + /* 133 */ 65488, 92, 0, + /* 136 */ 65489, 92, 0, + /* 139 */ 65489, 93, 0, + /* 142 */ 65490, 93, 0, + /* 145 */ 65491, 93, 0, + /* 148 */ 65491, 94, 0, + /* 151 */ 65492, 94, 0, + /* 154 */ 65493, 94, 0, + /* 157 */ 65493, 95, 0, + /* 160 */ 65494, 95, 0, + /* 163 */ 65495, 95, 0, + /* 166 */ 65495, 96, 0, + /* 169 */ 65496, 96, 0, + /* 172 */ 65497, 96, 0, + /* 175 */ 65497, 97, 0, + /* 178 */ 65498, 97, 0, + /* 181 */ 65499, 97, 0, + /* 184 */ 65499, 98, 0, + /* 187 */ 65500, 98, 0, + /* 190 */ 65501, 98, 0, + /* 193 */ 65501, 99, 0, + /* 196 */ 65502, 99, 0, + /* 199 */ 65503, 99, 0, + /* 202 */ 65503, 100, 0, + /* 205 */ 65504, 100, 0, + /* 208 */ 65503, 0, + /* 210 */ 65519, 0, + /* 212 */ 65535, 0, }; static const uint16_t SparcSubRegIdxLists[] = { - /* 0 */ 1, 3, 0, - /* 3 */ 2, 4, 0, - /* 6 */ 2, 1, 3, 4, 5, 6, 0, + /* 0 */ 1, 3, 0, + /* 3 */ 2, 4, 0, + /* 6 */ 2, 1, 3, 4, 5, 6, 0, }; -static const MCRegisterDesc SparcRegDesc[] = { // Descriptors - { 3, 0, 0, 0, 0, 0 }, - { 406, 4, 4, 2, 3393, 0 }, - { 410, 4, 4, 2, 3393, 0 }, - { 33, 5, 203, 0, 1794, 2 }, - { 87, 12, 194, 0, 1794, 2 }, - { 133, 15, 194, 0, 1794, 2 }, - { 179, 22, 185, 0, 1794, 2 }, - { 220, 25, 185, 0, 1794, 2 }, - { 261, 32, 176, 0, 1794, 2 }, - { 298, 35, 176, 0, 1794, 2 }, - { 335, 42, 167, 0, 1794, 2 }, - { 372, 45, 167, 0, 1794, 2 }, - { 397, 52, 158, 0, 1794, 2 }, - { 0, 55, 158, 0, 1794, 2 }, - { 54, 62, 149, 0, 1794, 2 }, - { 108, 65, 149, 0, 1794, 2 }, - { 154, 72, 140, 0, 1794, 2 }, - { 200, 75, 140, 0, 1794, 2 }, - { 241, 82, 134, 0, 1794, 2 }, - { 282, 4, 134, 2, 1841, 0 }, - { 319, 4, 131, 2, 1841, 0 }, - { 356, 4, 131, 2, 1841, 0 }, - { 381, 4, 129, 2, 1841, 0 }, - { 12, 4, 129, 2, 1841, 0 }, - { 66, 4, 127, 2, 1841, 0 }, - { 120, 4, 127, 2, 1841, 0 }, - { 166, 4, 125, 2, 1841, 0 }, - { 212, 4, 125, 2, 1841, 0 }, - { 253, 4, 123, 2, 1841, 0 }, - { 290, 4, 123, 2, 1841, 0 }, - { 327, 4, 121, 2, 1841, 0 }, - { 364, 4, 121, 2, 1841, 0 }, - { 389, 4, 119, 2, 1841, 0 }, - { 20, 4, 119, 2, 1841, 0 }, - { 74, 4, 117, 2, 1841, 0 }, - { 36, 4, 205, 2, 3329, 0 }, - { 90, 4, 202, 2, 3329, 0 }, - { 136, 4, 199, 2, 3329, 0 }, - { 182, 4, 196, 2, 3329, 0 }, - { 223, 4, 196, 2, 3329, 0 }, - { 264, 4, 193, 2, 3329, 0 }, - { 301, 4, 190, 2, 3329, 0 }, - { 338, 4, 187, 2, 3329, 0 }, - { 375, 4, 187, 2, 3329, 0 }, - { 400, 4, 184, 2, 3329, 0 }, - { 4, 4, 181, 2, 3329, 0 }, - { 58, 4, 178, 2, 3329, 0 }, - { 112, 4, 178, 2, 3329, 0 }, - { 158, 4, 175, 2, 3329, 0 }, - { 204, 4, 172, 2, 3329, 0 }, - { 245, 4, 169, 2, 3329, 0 }, - { 286, 4, 169, 2, 3329, 0 }, - { 323, 4, 166, 2, 3329, 0 }, - { 360, 4, 163, 2, 3329, 0 }, - { 385, 4, 160, 2, 3329, 0 }, - { 16, 4, 160, 2, 3329, 0 }, - { 70, 4, 157, 2, 3329, 0 }, - { 124, 4, 154, 2, 3329, 0 }, - { 170, 4, 151, 2, 3329, 0 }, - { 216, 4, 151, 2, 3329, 0 }, - { 257, 4, 148, 2, 3329, 0 }, - { 294, 4, 145, 2, 3329, 0 }, - { 331, 4, 142, 2, 3329, 0 }, - { 368, 4, 142, 2, 3329, 0 }, - { 393, 4, 139, 2, 3329, 0 }, - { 24, 4, 136, 2, 3329, 0 }, - { 78, 4, 133, 2, 3329, 0 }, - { 28, 4, 4, 2, 3361, 0 }, - { 82, 4, 4, 2, 3361, 0 }, - { 128, 4, 4, 2, 3361, 0 }, - { 174, 4, 4, 2, 3361, 0 }, - { 39, 4, 4, 2, 3361, 0 }, - { 93, 4, 4, 2, 3361, 0 }, - { 139, 4, 4, 2, 3361, 0 }, - { 185, 4, 4, 2, 3361, 0 }, - { 226, 4, 4, 2, 3361, 0 }, - { 267, 4, 4, 2, 3361, 0 }, - { 304, 4, 4, 2, 3361, 0 }, - { 341, 4, 4, 2, 3361, 0 }, - { 42, 4, 4, 2, 3361, 0 }, - { 96, 4, 4, 2, 3361, 0 }, - { 142, 4, 4, 2, 3361, 0 }, - { 188, 4, 4, 2, 3361, 0 }, - { 229, 4, 4, 2, 3361, 0 }, - { 270, 4, 4, 2, 3361, 0 }, - { 307, 4, 4, 2, 3361, 0 }, - { 344, 4, 4, 2, 3361, 0 }, - { 45, 4, 4, 2, 3361, 0 }, - { 99, 4, 4, 2, 3361, 0 }, - { 145, 4, 4, 2, 3361, 0 }, - { 191, 4, 4, 2, 3361, 0 }, - { 232, 4, 4, 2, 3361, 0 }, - { 273, 4, 4, 2, 3361, 0 }, - { 310, 4, 4, 2, 3361, 0 }, - { 347, 4, 4, 2, 3361, 0 }, - { 48, 4, 4, 2, 3361, 0 }, - { 102, 4, 4, 2, 3361, 0 }, - { 148, 4, 4, 2, 3361, 0 }, - { 194, 4, 4, 2, 3361, 0 }, - { 235, 4, 4, 2, 3361, 0 }, - { 276, 4, 4, 2, 3361, 0 }, - { 313, 4, 4, 2, 3361, 0 }, - { 350, 4, 4, 2, 3361, 0 }, - { 51, 8, 4, 6, 4, 5 }, - { 105, 18, 4, 6, 4, 5 }, - { 151, 28, 4, 6, 4, 5 }, - { 197, 38, 4, 6, 4, 5 }, - { 238, 48, 4, 6, 4, 5 }, - { 279, 58, 4, 6, 4, 5 }, - { 316, 68, 4, 6, 4, 5 }, - { 353, 78, 4, 6, 4, 5 }, - { 378, 88, 4, 3, 1362, 10 }, - { 403, 91, 4, 3, 1362, 10 }, - { 8, 94, 4, 3, 1362, 10 }, - { 62, 97, 4, 3, 1362, 10 }, - { 116, 100, 4, 3, 1362, 10 }, - { 162, 103, 4, 3, 1362, 10 }, - { 208, 106, 4, 3, 1362, 10 }, - { 249, 109, 4, 3, 1362, 10 }, +static const MCRegisterDesc SparcRegDesc[] = { + // Descriptors + {3, 0, 0, 0, 0, 0}, {406, 4, 4, 2, 3393, 0}, + {410, 4, 4, 2, 3393, 0}, {33, 5, 203, 0, 1794, 2}, + {87, 12, 194, 0, 1794, 2}, {133, 15, 194, 0, 1794, 2}, + {179, 22, 185, 0, 1794, 2}, {220, 25, 185, 0, 1794, 2}, + {261, 32, 176, 0, 1794, 2}, {298, 35, 176, 0, 1794, 2}, + {335, 42, 167, 0, 1794, 2}, {372, 45, 167, 0, 1794, 2}, + {397, 52, 158, 0, 1794, 2}, {0, 55, 158, 0, 1794, 2}, + {54, 62, 149, 0, 1794, 2}, {108, 65, 149, 0, 1794, 2}, + {154, 72, 140, 0, 1794, 2}, {200, 75, 140, 0, 1794, 2}, + {241, 82, 134, 0, 1794, 2}, {282, 4, 134, 2, 1841, 0}, + {319, 4, 131, 2, 1841, 0}, {356, 4, 131, 2, 1841, 0}, + {381, 4, 129, 2, 1841, 0}, {12, 4, 129, 2, 1841, 0}, + {66, 4, 127, 2, 1841, 0}, {120, 4, 127, 2, 1841, 0}, + {166, 4, 125, 2, 1841, 0}, {212, 4, 125, 2, 1841, 0}, + {253, 4, 123, 2, 1841, 0}, {290, 4, 123, 2, 1841, 0}, + {327, 4, 121, 2, 1841, 0}, {364, 4, 121, 2, 1841, 0}, + {389, 4, 119, 2, 1841, 0}, {20, 4, 119, 2, 1841, 0}, + {74, 4, 117, 2, 1841, 0}, {36, 4, 205, 2, 3329, 0}, + {90, 4, 202, 2, 3329, 0}, {136, 4, 199, 2, 3329, 0}, + {182, 4, 196, 2, 3329, 0}, {223, 4, 196, 2, 3329, 0}, + {264, 4, 193, 2, 3329, 0}, {301, 4, 190, 2, 3329, 0}, + {338, 4, 187, 2, 3329, 0}, {375, 4, 187, 2, 3329, 0}, + {400, 4, 184, 2, 3329, 0}, {4, 4, 181, 2, 3329, 0}, + {58, 4, 178, 2, 3329, 0}, {112, 4, 178, 2, 3329, 0}, + {158, 4, 175, 2, 3329, 0}, {204, 4, 172, 2, 3329, 0}, + {245, 4, 169, 2, 3329, 0}, {286, 4, 169, 2, 3329, 0}, + {323, 4, 166, 2, 3329, 0}, {360, 4, 163, 2, 3329, 0}, + {385, 4, 160, 2, 3329, 0}, {16, 4, 160, 2, 3329, 0}, + {70, 4, 157, 2, 3329, 0}, {124, 4, 154, 2, 3329, 0}, + {170, 4, 151, 2, 3329, 0}, {216, 4, 151, 2, 3329, 0}, + {257, 4, 148, 2, 3329, 0}, {294, 4, 145, 2, 3329, 0}, + {331, 4, 142, 2, 3329, 0}, {368, 4, 142, 2, 3329, 0}, + {393, 4, 139, 2, 3329, 0}, {24, 4, 136, 2, 3329, 0}, + {78, 4, 133, 2, 3329, 0}, {28, 4, 4, 2, 3361, 0}, + {82, 4, 4, 2, 3361, 0}, {128, 4, 4, 2, 3361, 0}, + {174, 4, 4, 2, 3361, 0}, {39, 4, 4, 2, 3361, 0}, + {93, 4, 4, 2, 3361, 0}, {139, 4, 4, 2, 3361, 0}, + {185, 4, 4, 2, 3361, 0}, {226, 4, 4, 2, 3361, 0}, + {267, 4, 4, 2, 3361, 0}, {304, 4, 4, 2, 3361, 0}, + {341, 4, 4, 2, 3361, 0}, {42, 4, 4, 2, 3361, 0}, + {96, 4, 4, 2, 3361, 0}, {142, 4, 4, 2, 3361, 0}, + {188, 4, 4, 2, 3361, 0}, {229, 4, 4, 2, 3361, 0}, + {270, 4, 4, 2, 3361, 0}, {307, 4, 4, 2, 3361, 0}, + {344, 4, 4, 2, 3361, 0}, {45, 4, 4, 2, 3361, 0}, + {99, 4, 4, 2, 3361, 0}, {145, 4, 4, 2, 3361, 0}, + {191, 4, 4, 2, 3361, 0}, {232, 4, 4, 2, 3361, 0}, + {273, 4, 4, 2, 3361, 0}, {310, 4, 4, 2, 3361, 0}, + {347, 4, 4, 2, 3361, 0}, {48, 4, 4, 2, 3361, 0}, + {102, 4, 4, 2, 3361, 0}, {148, 4, 4, 2, 3361, 0}, + {194, 4, 4, 2, 3361, 0}, {235, 4, 4, 2, 3361, 0}, + {276, 4, 4, 2, 3361, 0}, {313, 4, 4, 2, 3361, 0}, + {350, 4, 4, 2, 3361, 0}, {51, 8, 4, 6, 4, 5}, + {105, 18, 4, 6, 4, 5}, {151, 28, 4, 6, 4, 5}, + {197, 38, 4, 6, 4, 5}, {238, 48, 4, 6, 4, 5}, + {279, 58, 4, 6, 4, 5}, {316, 68, 4, 6, 4, 5}, + {353, 78, 4, 6, 4, 5}, {378, 88, 4, 3, 1362, 10}, + {403, 91, 4, 3, 1362, 10}, {8, 94, 4, 3, 1362, 10}, + {62, 97, 4, 3, 1362, 10}, {116, 100, 4, 3, 1362, 10}, + {162, 103, 4, 3, 1362, 10}, {208, 106, 4, 3, 1362, 10}, + {249, 109, 4, 3, 1362, 10}, }; - // FCCRegs Register Class... - static const MCPhysReg FCCRegs[] = { - SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3, - }; +// FCCRegs Register Class... +static const MCPhysReg FCCRegs[] = { + SP_FCC0, + SP_FCC1, + SP_FCC2, + SP_FCC3, +}; - // FCCRegs Bit set. - static const uint8_t FCCRegsBits[] = { +// FCCRegs Bit set. +static const uint8_t FCCRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, - }; +}; - // FPRegs Register Class... - static const MCPhysReg FPRegs[] = { - SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31, - }; +// FPRegs Register Class... +static const MCPhysReg FPRegs[] = { + SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, + SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, + SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, + SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31, +}; - // FPRegs Bit set. - static const uint8_t FPRegsBits[] = { +// FPRegs Bit set. +static const uint8_t FPRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, - }; +}; - // IntRegs Register Class... - static const MCPhysReg IntRegs[] = { - SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, - }; +// IntRegs Register Class... +static const MCPhysReg IntRegs[] = { + SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, + SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, + SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, +}; - // IntRegs Bit set. - static const uint8_t IntRegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, - }; +// IntRegs Bit set. +static const uint8_t IntRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, +}; - // DFPRegs Register Class... - static const MCPhysReg DFPRegs[] = { - SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31, - }; +// DFPRegs Register Class... +static const MCPhysReg DFPRegs[] = { + SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, + SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, + SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, + SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31, +}; - // DFPRegs Bit set. - static const uint8_t DFPRegsBits[] = { +// DFPRegs Bit set. +static const uint8_t DFPRegsBits[] = { 0xf8, 0xff, 0xff, 0xff, 0x07, - }; +}; - // I64Regs Register Class... - static const MCPhysReg I64Regs[] = { - SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, - }; +// I64Regs Register Class... +static const MCPhysReg I64Regs[] = { + SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, + SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, + SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, +}; - // I64Regs Bit set. - static const uint8_t I64RegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, - }; +// I64Regs Bit set. +static const uint8_t I64RegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, +}; - // DFPRegs_with_sub_even Register Class... - static const MCPhysReg DFPRegs_with_sub_even[] = { - SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, - }; +// DFPRegs_with_sub_even Register Class... +static const MCPhysReg DFPRegs_with_sub_even[] = { + SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, + SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, +}; - // DFPRegs_with_sub_even Bit set. - static const uint8_t DFPRegs_with_sub_evenBits[] = { - 0xf8, 0xff, 0x07, - }; +// DFPRegs_with_sub_even Bit set. +static const uint8_t DFPRegs_with_sub_evenBits[] = { + 0xf8, + 0xff, + 0x07, +}; - // QFPRegs Register Class... - static const MCPhysReg QFPRegs[] = { - SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15, - }; +// QFPRegs Register Class... +static const MCPhysReg QFPRegs[] = { + SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, + SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15, +}; - // QFPRegs Bit set. - static const uint8_t QFPRegsBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, - }; +// QFPRegs Bit set. +static const uint8_t QFPRegsBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, +}; - // QFPRegs_with_sub_even Register Class... - static const MCPhysReg QFPRegs_with_sub_even[] = { +// QFPRegs_with_sub_even Register Class... +static const MCPhysReg QFPRegs_with_sub_even[] = { SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, - }; +}; - // QFPRegs_with_sub_even Bit set. - static const uint8_t QFPRegs_with_sub_evenBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, - }; +// QFPRegs_with_sub_even Bit set. +static const uint8_t QFPRegs_with_sub_evenBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, +}; static const MCRegisterClass SparcMCRegisterClasses[] = { - { FCCRegs, FCCRegsBits, sizeof(FCCRegsBits) }, - { FPRegs, FPRegsBits, sizeof(FPRegsBits) }, - { IntRegs, IntRegsBits, sizeof(IntRegsBits) }, - { DFPRegs, DFPRegsBits, sizeof(DFPRegsBits) }, - { I64Regs, I64RegsBits, sizeof(I64RegsBits) }, - { DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, sizeof(DFPRegs_with_sub_evenBits) }, - { QFPRegs, QFPRegsBits, sizeof(QFPRegsBits) }, - { QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, sizeof(QFPRegs_with_sub_evenBits) }, + {FCCRegs, FCCRegsBits, sizeof(FCCRegsBits)}, + {FPRegs, FPRegsBits, sizeof(FPRegsBits)}, + {IntRegs, IntRegsBits, sizeof(IntRegsBits)}, + {DFPRegs, DFPRegsBits, sizeof(DFPRegsBits)}, + {I64Regs, I64RegsBits, sizeof(I64RegsBits)}, + {DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, + sizeof(DFPRegs_with_sub_evenBits)}, + {QFPRegs, QFPRegsBits, sizeof(QFPRegsBits)}, + {QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, + sizeof(QFPRegs_with_sub_evenBits)}, }; #endif // GET_REGINFO_MC_DESC diff --git a/arch/Sparc/SparcGenSubtargetInfo.inc b/arch/Sparc/SparcGenSubtargetInfo.inc index e7bd53ac21..8c236d0e71 100644 --- a/arch/Sparc/SparcGenSubtargetInfo.inc +++ b/arch/Sparc/SparcGenSubtargetInfo.inc @@ -9,19 +9,17 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ - #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM enum { - Sparc_FeatureHardQuad = 1ULL << 0, - Sparc_FeatureV8Deprecated = 1ULL << 1, - Sparc_FeatureV9 = 1ULL << 2, - Sparc_FeatureVIS = 1ULL << 3, - Sparc_FeatureVIS2 = 1ULL << 4, - Sparc_FeatureVIS3 = 1ULL << 5, - Sparc_UsePopc = 1ULL << 6 + Sparc_FeatureHardQuad = 1ULL << 0, + Sparc_FeatureV8Deprecated = 1ULL << 1, + Sparc_FeatureV9 = 1ULL << 2, + Sparc_FeatureVIS = 1ULL << 3, + Sparc_FeatureVIS2 = 1ULL << 4, + Sparc_FeatureVIS3 = 1ULL << 5, + Sparc_UsePopc = 1ULL << 6 }; #endif // GET_SUBTARGETINFO_ENUM - diff --git a/arch/Sparc/SparcInstPrinter.c b/arch/Sparc/SparcInstPrinter.c index da83187441..d258df2a0b 100644 --- a/arch/Sparc/SparcInstPrinter.c +++ b/arch/Sparc/SparcInstPrinter.c @@ -1,4 +1,5 @@ -//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===// +//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax +//--------===// // // The LLVM Compiler Infrastructure // @@ -20,430 +21,506 @@ #define _CRT_SECURE_NO_WARNINGS #endif -#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) -#pragma warning(disable:28719) // disable MSVC's warning on strncpy() +#if defined(WIN32) || defined(WIN64) || defined(_WIN32) || defined(_WIN64) +#pragma warning(disable : 28719) // disable MSVC's warning on strncpy() #endif +#include #include #include #include -#include -#include "SparcInstPrinter.h" #include "../../MCInst.h" -#include "../../utils.h" -#include "../../SStream.h" +#include "../../MCInstPrinter.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" +#include "../../SStream.h" +#include "../../utils.h" +#include "SparcInstPrinter.h" #include "SparcMapping.h" #include "Sparc.h" static const char *getRegisterName(unsigned RegNo); -static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); -static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier); +static void printInstruction(MCInst *MI, SStream *O); +static void printMemOperand(MCInst *MI, int opNum, SStream *O, + const char *Modifier); static void printOperand(MCInst *MI, int opNum, SStream *O); -static void Sparc_add_hint(MCInst *MI, unsigned int hint) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->sparc.hint = hint; - } -} +static void printCCOperand(MCInst *MI, int opNum, SStream *O); + +static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O); + +static void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +void printMembarTag(const MCInst *MI, int opNum, SStream *O) { + static const char *const TagNames[] = { + "#LoadLoad", "#StoreLoad", "#LoadStore", "#StoreStore", + "#Lookaside", "#MemIssue", "#Sync"}; + + unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, opNum)); -static void Sparc_add_reg(MCInst *MI, unsigned int reg) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; - MI->flat_insn->detail->sparc.op_count++; - } + if (Imm > 127) { + SStream_concat(O, "%u", Imm); + return; + } + + bool First = true; + for (unsigned i = 0; i < sizeof(TagNames) / sizeof(char *); i++) { + if (Imm & (1 << i)) { + SStream_concat0(O, First ? "" : " | "); + SStream_concat0(O, TagNames[i]); + First = false; + } + } } -static void set_mem_access(MCInst *MI, bool status) -{ - if (MI->csh->detail != CS_OPT_ON) - return; - - MI->csh->doing_mem = status; - - if (status) { - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM; - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID; - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0; - } else { - // done, create the next operand slot - MI->flat_insn->detail->sparc.op_count++; - } +#define GET_INSTRINFO_ENUM +#define PRINT_ALIAS_INSTR +#define GET_REGINFO_ENUM +#define GET_ASM_WRITER +#include "SparcGenDisassemblerTables.inc" + +static void Sparc_add_hint(MCInst *MI, unsigned int hint) { + if (MI->csh->detail) { + MI->flat_insn->detail->sparc.hint = hint; + } } -void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) -{ - if (((cs_struct *)ud)->detail != CS_OPT_ON) - return; - - // fix up some instructions - if (insn->id == SPARC_INS_CASX) { - // first op is actually a memop, not regop - insn->detail->sparc.operands[0].type = SPARC_OP_MEM; - insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg; - insn->detail->sparc.operands[0].mem.disp = 0; - } +static void Sparc_add_reg(MCInst *MI, unsigned int reg) { + if (MI->csh->detail) { + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count] + .type = SPARC_OP_REG; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count] + .reg = reg; + MI->flat_insn->detail->sparc.op_count++; + } } -static void printRegName(SStream *OS, unsigned RegNo) -{ - SStream_concat0(OS, "%"); - SStream_concat0(OS, getRegisterName(RegNo)); +static void set_mem_access(MCInst *MI, bool status) { + if (MI->csh->detail != CS_OPT_ON) + return; + + MI->csh->doing_mem = status; + + if (status) { + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count] + .type = SPARC_OP_MEM; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count] + .mem.base = SPARC_REG_INVALID; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count] + .mem.disp = 0; + } else { + // done, create the next operand slot + MI->flat_insn->detail->sparc.op_count++; + } } -#define GET_INSTRINFO_ENUM -#include "SparcGenInstrInfo.inc" +void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + + // fix up some instructions + if (insn->id == SPARC_INS_CASX) { + // first op is actually a memop, not regop + insn->detail->sparc.operands[0].type = SPARC_OP_MEM; + insn->detail->sparc.operands[0].mem.base = + (uint8_t)insn->detail->sparc.operands[0].reg; + insn->detail->sparc.operands[0].mem.disp = 0; + } +} -#define GET_REGINFO_ENUM -#include "SparcGenRegisterInfo.inc" - -static bool printSparcAliasInstr(MCInst *MI, SStream *O) -{ - switch (MCInst_getOpcode(MI)) { - default: return false; - case SP_JMPLrr: - case SP_JMPLri: - if (MCInst_getNumOperands(MI) != 3) - return false; - if (!MCOperand_isReg(MCInst_getOperand(MI, 0))) - return false; - - switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) { - default: return false; - case SP_G0: // jmp $addr | ret | retl - if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { - switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) { - default: break; - case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true; - case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true; - } - } - - SStream_concat0(O, "jmp\t"); - MCInst_setOpcodePub(MI, SPARC_INS_JMP); - printMemOperand(MI, 1, O, NULL); - return true; - case SP_O7: // call $addr - SStream_concat0(O, "call "); - MCInst_setOpcodePub(MI, SPARC_INS_CALL); - printMemOperand(MI, 1, O, NULL); - return true; - } - case SP_V9FCMPS: - case SP_V9FCMPD: - case SP_V9FCMPQ: - case SP_V9FCMPES: - case SP_V9FCMPED: - case SP_V9FCMPEQ: - if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) || - (!MCOperand_isReg(MCInst_getOperand(MI, 0))) || - (MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0)) - return false; - // if V8, skip printing %fcc0. - switch(MCInst_getOpcode(MI)) { - default: - case SP_V9FCMPS: SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break; - case SP_V9FCMPD: SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break; - case SP_V9FCMPQ: SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break; - case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break; - case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break; - case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break; - } - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); - return true; - } +static void printRegName(SStream *OS, unsigned RegNo) { + SStream_concat0(OS, "%"); + const char *Name = Sparc_reg_name(0, RegNo); + if (Name) + SStream_concat0(OS, Name); + else + SStream_concat0(OS, getRegisterName(RegNo)); } -static void printOperand(MCInst *MI, int opNum, SStream *O) -{ - int64_t Imm; - unsigned reg; - MCOperand *MO = MCInst_getOperand(MI, opNum); - - if (MCOperand_isReg(MO)) { - reg = MCOperand_getReg(MO); - printRegName(O, reg); - reg = Sparc_map_register(reg); - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base) - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg; - else - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg; - } else { - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; - MI->flat_insn->detail->sparc.op_count++; - } - } - - return; - } - - if (MCOperand_isImm(MO)) { - Imm = (int)MCOperand_getImm(MO); - - // Conditional branches displacements needs to be signextended to be - // able to jump backwards. - // - // Displacements are measured as the number of instructions forward or - // backward, so they need to be multiplied by 4 - switch (MI->Opcode) { - case SP_CALL: - // Imm = SignExtend32(Imm, 30); - Imm += MI->address; - break; - - // Branch on integer condition with prediction (BPcc) - // Branch on floating point condition with prediction (FBPfcc) - case SP_BPICC: - case SP_BPICCA: - case SP_BPICCANT: - case SP_BPICCNT: - case SP_BPXCC: - case SP_BPXCCA: - case SP_BPXCCANT: - case SP_BPXCCNT: - case SP_BPFCC: - case SP_BPFCCA: - case SP_BPFCCANT: - case SP_BPFCCNT: - Imm = SignExtend32(Imm, 19); - Imm = MI->address + Imm * 4; - break; - - // Branch on integer condition (Bicc) - // Branch on floating point condition (FBfcc) - case SP_BA: - case SP_BCOND: - case SP_BCONDA: - case SP_FBCOND: - case SP_FBCONDA: - Imm = SignExtend32(Imm, 22); - Imm = MI->address + Imm * 4; - break; - - // Branch on integer register with prediction (BPr) - case SP_BPGEZapn: - case SP_BPGEZapt: - case SP_BPGEZnapn: - case SP_BPGEZnapt: - case SP_BPGZapn: - case SP_BPGZapt: - case SP_BPGZnapn: - case SP_BPGZnapt: - case SP_BPLEZapn: - case SP_BPLEZapt: - case SP_BPLEZnapn: - case SP_BPLEZnapt: - case SP_BPLZapn: - case SP_BPLZapt: - case SP_BPLZnapn: - case SP_BPLZnapt: - case SP_BPNZapn: - case SP_BPNZapt: - case SP_BPNZnapn: - case SP_BPNZnapt: - case SP_BPZapn: - case SP_BPZapt: - case SP_BPZnapn: - case SP_BPZnapt: - Imm = SignExtend32(Imm, 16); - Imm = MI->address + Imm * 4; - break; - } - - printInt64(O, Imm); - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm; - } else { - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM; - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm; - MI->flat_insn->detail->sparc.op_count++; - } - } - } - - return; +static bool printSparcAliasInstr(MCInst *MI, SStream *O) { + switch (MCInst_getOpcode(MI)) { + default: + return false; + case SP_JMPLrr: + case SP_JMPLri: + if (MCInst_getNumOperands(MI) != 3) + return false; + if (!MCOperand_isReg(MCInst_getOperand(MI, 0))) + return false; + + switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) { + default: + return false; + case SP_G0: // jmp $addr | ret | retl + if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { + switch (MCOperand_getReg(MCInst_getOperand(MI, 1))) { + default: + break; + case SP_I7: + SStream_concat0(O, "ret"); + MCInst_setOpcodePub(MI, SPARC_INS_RET); + return true; + case SP_O7: + SStream_concat0(O, "retl"); + MCInst_setOpcodePub(MI, SPARC_INS_RETL); + return true; + } + } + + SStream_concat0(O, "jmp\t"); + MCInst_setOpcodePub(MI, SPARC_INS_JMP); + printMemOperand(MI, 1, O, NULL); + return true; + case SP_O7: // call $addr + SStream_concat0(O, "call "); + MCInst_setOpcodePub(MI, SPARC_INS_CALL); + printMemOperand(MI, 1, O, NULL); + return true; + } + case SP_V9FCMPS: + case SP_V9FCMPD: + case SP_V9FCMPQ: + case SP_V9FCMPES: + case SP_V9FCMPED: + case SP_V9FCMPEQ: + if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) || + (!MCOperand_isReg(MCInst_getOperand(MI, 0))) || + (MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0)) + return false; + // if V8, skip printing %fcc0. + switch (MCInst_getOpcode(MI)) { + default: + case SP_V9FCMPS: + SStream_concat0(O, "fcmps\t"); + MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); + break; + case SP_V9FCMPD: + SStream_concat0(O, "fcmpd\t"); + MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); + break; + case SP_V9FCMPQ: + SStream_concat0(O, "fcmpq\t"); + MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); + break; + case SP_V9FCMPES: + SStream_concat0(O, "fcmpes\t"); + MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); + break; + case SP_V9FCMPED: + SStream_concat0(O, "fcmped\t"); + MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); + break; + case SP_V9FCMPEQ: + SStream_concat0(O, "fcmpeq\t"); + MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); + break; + } + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return true; + } } -static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier) -{ - MCOperand *MO; +static void printOperand(MCInst *MI, int opNum, SStream *O) { + int64_t Imm; + unsigned reg; + MCOperand *MO = MCInst_getOperand(MI, opNum); + + if (MCOperand_isReg(MO)) { + reg = MCOperand_getReg(MO); + printRegName(O, reg); + // reg = Sparc_map_register(reg); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + if (MI->flat_insn->detail->sparc + .operands[MI->flat_insn->detail->sparc.op_count] + .mem.base) + MI->flat_insn->detail->sparc + .operands[MI->flat_insn->detail->sparc.op_count] + .mem.index = (uint8_t)reg; + else + MI->flat_insn->detail->sparc + .operands[MI->flat_insn->detail->sparc.op_count] + .mem.base = (uint8_t)reg; + } else { + MI->flat_insn->detail->sparc + .operands[MI->flat_insn->detail->sparc.op_count] + .type = SPARC_OP_REG; + MI->flat_insn->detail->sparc + .operands[MI->flat_insn->detail->sparc.op_count] + .reg = reg; + MI->flat_insn->detail->sparc.op_count++; + } + } + + return; + } + + if (MCOperand_isImm(MO)) { + Imm = (int)MCOperand_getImm(MO); + + // Conditional branches displacements needs to be signextended to be + // able to jump backwards. + // + // Displacements are measured as the number of instructions forward or + // backward, so they need to be multiplied by 4 + switch (MI->Opcode) { + case SP_CALL: + // Imm = SignExtend32(Imm, 30); + Imm += MI->address; + break; + + // Branch on integer condition with prediction (BPcc) + // Branch on floating point condition with prediction (FBPfcc) + case SP_BPICC: + case SP_BPICCA: + case SP_BPICCANT: + case SP_BPICCNT: + case SP_BPXCC: + case SP_BPXCCA: + case SP_BPXCCANT: + case SP_BPXCCNT: + case SP_BPFCC: + case SP_BPFCCA: + case SP_BPFCCANT: + case SP_BPFCCNT: + Imm = SignExtend32(Imm, 19); + Imm = MI->address + Imm * 4; + break; + + // Branch on integer condition (Bicc) + // Branch on floating point condition (FBfcc) + case SP_BA: + case SP_BCOND: + case SP_BCONDA: + case SP_FBCOND: + case SP_FBCONDA: + Imm = SignExtend32(Imm, 22); + Imm = MI->address + Imm * 4; + break; + + // Branch on integer register with prediction (BPr) + case SP_BPGEZapn: + case SP_BPGEZapt: + case SP_BPGEZnapn: + case SP_BPGEZnapt: + case SP_BPGZapn: + case SP_BPGZapt: + case SP_BPGZnapn: + case SP_BPGZnapt: + case SP_BPLEZapn: + case SP_BPLEZapt: + case SP_BPLEZnapn: + case SP_BPLEZnapt: + case SP_BPLZapn: + case SP_BPLZapt: + case SP_BPLZnapn: + case SP_BPLZnapt: + case SP_BPNZapn: + case SP_BPNZapt: + case SP_BPNZnapn: + case SP_BPNZnapt: + case SP_BPZapn: + case SP_BPZapt: + case SP_BPZnapn: + case SP_BPZnapt: + Imm = SignExtend32(Imm, 16); + Imm = MI->address + Imm * 4; + break; + } + + printInt64(O, Imm); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->sparc + .operands[MI->flat_insn->detail->sparc.op_count] + .mem.disp = Imm; + } else { + MI->flat_insn->detail->sparc + .operands[MI->flat_insn->detail->sparc.op_count] + .type = SPARC_OP_IMM; + MI->flat_insn->detail->sparc + .operands[MI->flat_insn->detail->sparc.op_count] + .imm = Imm; + MI->flat_insn->detail->sparc.op_count++; + } + } + } + + return; +} - set_mem_access(MI, true); - printOperand(MI, opNum, O); +static void printMemOperand(MCInst *MI, int opNum, SStream *O, + const char *Modifier) { + MCOperand *MO; - // If this is an ADD operand, emit it like normal operands. - if (Modifier && !strcmp(Modifier, "arith")) { - SStream_concat0(O, ", "); - printOperand(MI, opNum + 1, O); - set_mem_access(MI, false); - return; - } + set_mem_access(MI, true); + printOperand(MI, opNum, O); - MO = MCInst_getOperand(MI, opNum + 1); + // If this is an ADD operand, emit it like normal operands. + if (Modifier && !strcmp(Modifier, "arith")) { + SStream_concat0(O, ", "); + printOperand(MI, opNum + 1, O); + set_mem_access(MI, false); + return; + } - if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) { - set_mem_access(MI, false); - return; // don't print "+%g0" - } + MO = MCInst_getOperand(MI, opNum + 1); - if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) { - set_mem_access(MI, false); - return; // don't print "+0" - } + if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) { + set_mem_access(MI, false); + return; // don't print "+%g0" + } - SStream_concat0(O, "+"); // qq + if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) { + set_mem_access(MI, false); + return; // don't print "+0" + } - printOperand(MI, opNum + 1, O); - set_mem_access(MI, false); -} + SStream_concat0(O, "+"); // qq -static void printCCOperand(MCInst *MI, int opNum, SStream *O) -{ - int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256; - - switch (MCInst_getOpcode(MI)) { - default: break; - case SP_FBCOND: - case SP_FBCONDA: - case SP_BPFCC: - case SP_BPFCCA: - case SP_BPFCCNT: - case SP_BPFCCANT: - case SP_MOVFCCrr: case SP_V9MOVFCCrr: - case SP_MOVFCCri: case SP_V9MOVFCCri: - case SP_FMOVS_FCC: case SP_V9FMOVS_FCC: - case SP_FMOVD_FCC: case SP_V9FMOVD_FCC: - case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC: - // Make sure CC is a fp conditional flag. - CC = (CC < 16+256) ? (CC + 16) : CC; - break; - } - - SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC)); - - if (MI->csh->detail) - MI->flat_insn->detail->sparc.cc = (sparc_cc)CC; + printOperand(MI, opNum + 1, O); + set_mem_access(MI, false); } - -static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O) -{ - return true; +static void printCCOperand(MCInst *MI, int opNum, SStream *O) { + int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256; + + switch (MCInst_getOpcode(MI)) { + default: + break; + case SP_FBCOND: + case SP_FBCONDA: + case SP_BPFCC: + case SP_BPFCCA: + case SP_BPFCCNT: + case SP_BPFCCANT: + case SP_MOVFCCrr: + case SP_V9MOVFCCrr: + case SP_MOVFCCri: + case SP_V9MOVFCCri: + case SP_FMOVS_FCC: + case SP_V9FMOVS_FCC: + case SP_FMOVD_FCC: + case SP_V9FMOVD_FCC: + case SP_FMOVQ_FCC: + case SP_V9FMOVQ_FCC: + // Make sure CC is a fp conditional flag. + CC = (CC < 16 + 256) ? (CC + 16) : CC; + break; + } + + SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC)); + + if (MI->csh->detail) + MI->flat_insn->detail->sparc.cc = (sparc_cc)CC; } - -#define PRINT_ALIAS_INSTR -#include "SparcGenAsmWriter.inc" - -void Sparc_printInst(MCInst *MI, SStream *O, void *Info) -{ - char *mnem, *p; - char instr[64]; // Sparc has no instruction this long - - mnem = printAliasInstr(MI, O, Info); - if (mnem) { - // fixup instruction id due to the change in alias instruction - strncpy(instr, mnem, sizeof(instr)); - instr[sizeof(instr) - 1] = '\0'; - // does this contains hint with a coma? - p = strchr(instr, ','); - if (p) - *p = '\0'; // now instr only has instruction mnemonic - MCInst_setOpcodePub(MI, Sparc_map_insn(instr)); - switch(MCInst_getOpcode(MI)) { - case SP_BCOND: - case SP_BCONDA: - case SP_BPICCANT: - case SP_BPICCNT: - case SP_BPXCCANT: - case SP_BPXCCNT: - case SP_TXCCri: - case SP_TXCCrr: - if (MI->csh->detail) { - // skip 'b', 't' - MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1); - MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); - } - break; - case SP_BPFCCANT: - case SP_BPFCCNT: - if (MI->csh->detail) { - // skip 'fb' - MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2); - MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); - } - break; - case SP_FMOVD_ICC: - case SP_FMOVD_XCC: - case SP_FMOVQ_ICC: - case SP_FMOVQ_XCC: - case SP_FMOVS_ICC: - case SP_FMOVS_XCC: - if (MI->csh->detail) { - // skip 'fmovd', 'fmovq', 'fmovs' - MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5); - MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); - } - break; - case SP_MOVICCri: - case SP_MOVICCrr: - case SP_MOVXCCri: - case SP_MOVXCCrr: - if (MI->csh->detail) { - // skip 'mov' - MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3); - MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); - } - break; - case SP_V9FMOVD_FCC: - case SP_V9FMOVQ_FCC: - case SP_V9FMOVS_FCC: - if (MI->csh->detail) { - // skip 'fmovd', 'fmovq', 'fmovs' - MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5); - MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); - } - break; - case SP_V9MOVFCCri: - case SP_V9MOVFCCrr: - if (MI->csh->detail) { - // skip 'mov' - MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3); - MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); - } - break; - default: - break; - } - cs_mem_free(mnem); - } else { - if (!printSparcAliasInstr(MI, O)) - printInstruction(MI, O, NULL); - } +static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O) { return true; } + +void Sparc_printInst(MCInst *MI, SStream *O, void *Info) { + char *mnem, *p; + char instr[64]; // Sparc has no instruction this long + + MRI = Info; + + mnem = printAliasInstr(MI, O); + if (mnem) { + // fixup instruction id due to the change in alias instruction + strncpy(instr, mnem, sizeof(instr)); + instr[sizeof(instr) - 1] = '\0'; + // does this contains hint with a coma? + p = strchr(instr, ','); + if (p) + *p = '\0'; // now instr only has instruction mnemonic + MCInst_setOpcodePub(MI, Sparc_map_insn(instr)); + switch (MCInst_getOpcode(MI)) { + case SP_BCOND: + case SP_BCONDA: + case SP_BPICCANT: + case SP_BPICCNT: + case SP_BPXCCANT: + case SP_BPXCCNT: + case SP_TXCCri: + case SP_TXCCrr: + if (MI->csh->detail) { + // skip 'b', 't' + MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_BPFCCANT: + case SP_BPFCCNT: + if (MI->csh->detail) { + // skip 'fb' + MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_FMOVD_ICC: + case SP_FMOVD_XCC: + case SP_FMOVQ_ICC: + case SP_FMOVQ_XCC: + case SP_FMOVS_ICC: + case SP_FMOVS_XCC: + if (MI->csh->detail) { + // skip 'fmovd', 'fmovq', 'fmovs' + MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_MOVICCri: + case SP_MOVICCrr: + case SP_MOVXCCri: + case SP_MOVXCCrr: + if (MI->csh->detail) { + // skip 'mov' + MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_V9FMOVD_FCC: + case SP_V9FMOVQ_FCC: + case SP_V9FMOVS_FCC: + if (MI->csh->detail) { + // skip 'fmovd', 'fmovq', 'fmovs' + MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + case SP_V9MOVFCCri: + case SP_V9MOVFCCrr: + if (MI->csh->detail) { + // skip 'mov' + MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3); + MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); + } + break; + default: + break; + } + cs_mem_free(mnem); + } else { + if (!printSparcAliasInstr(MI, O)) + printInstruction(MI, O); + } } -void Sparc_addReg(MCInst *MI, int reg) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; - MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; - MI->flat_insn->detail->sparc.op_count++; - } +void Sparc_addReg(MCInst *MI, int reg) { + if (MI->csh->detail) { + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count] + .type = SPARC_OP_REG; + MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count] + .reg = reg; + MI->flat_insn->detail->sparc.op_count++; + } } #endif diff --git a/arch/Sparc/SparcMapping.c b/arch/Sparc/SparcMapping.c index f86fb33eb9..ede6bde204 100644 --- a/arch/Sparc/SparcMapping.c +++ b/arch/Sparc/SparcMapping.c @@ -3,7 +3,7 @@ #ifdef CAPSTONE_HAS_SPARC -#include // debug +#include // debug #include #include "../../utils.h" @@ -11,655 +11,785 @@ #include "SparcMapping.h" #define GET_INSTRINFO_ENUM +#define GET_REGINFO_ENUM +#include "SparcGenDisassemblerTables.inc" #include "SparcGenInstrInfo.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { - { SPARC_REG_INVALID, NULL }, - - { SPARC_REG_F0, "f0"}, - { SPARC_REG_F1, "f1"}, - { SPARC_REG_F2, "f2"}, - { SPARC_REG_F3, "f3"}, - { SPARC_REG_F4, "f4"}, - { SPARC_REG_F5, "f5"}, - { SPARC_REG_F6, "f6"}, - { SPARC_REG_F7, "f7"}, - { SPARC_REG_F8, "f8"}, - { SPARC_REG_F9, "f9"}, - { SPARC_REG_F10, "f10"}, - { SPARC_REG_F11, "f11"}, - { SPARC_REG_F12, "f12"}, - { SPARC_REG_F13, "f13"}, - { SPARC_REG_F14, "f14"}, - { SPARC_REG_F15, "f15"}, - { SPARC_REG_F16, "f16"}, - { SPARC_REG_F17, "f17"}, - { SPARC_REG_F18, "f18"}, - { SPARC_REG_F19, "f19"}, - { SPARC_REG_F20, "f20"}, - { SPARC_REG_F21, "f21"}, - { SPARC_REG_F22, "f22"}, - { SPARC_REG_F23, "f23"}, - { SPARC_REG_F24, "f24"}, - { SPARC_REG_F25, "f25"}, - { SPARC_REG_F26, "f26"}, - { SPARC_REG_F27, "f27"}, - { SPARC_REG_F28, "f28"}, - { SPARC_REG_F29, "f29"}, - { SPARC_REG_F30, "f30"}, - { SPARC_REG_F31, "f31"}, - { SPARC_REG_F32, "f32"}, - { SPARC_REG_F34, "f34"}, - { SPARC_REG_F36, "f36"}, - { SPARC_REG_F38, "f38"}, - { SPARC_REG_F40, "f40"}, - { SPARC_REG_F42, "f42"}, - { SPARC_REG_F44, "f44"}, - { SPARC_REG_F46, "f46"}, - { SPARC_REG_F48, "f48"}, - { SPARC_REG_F50, "f50"}, - { SPARC_REG_F52, "f52"}, - { SPARC_REG_F54, "f54"}, - { SPARC_REG_F56, "f56"}, - { SPARC_REG_F58, "f58"}, - { SPARC_REG_F60, "f60"}, - { SPARC_REG_F62, "f62"}, - { SPARC_REG_FCC0, "fcc0"}, - { SPARC_REG_FCC1, "fcc1"}, - { SPARC_REG_FCC2, "fcc2"}, - { SPARC_REG_FCC3, "fcc3"}, - { SPARC_REG_FP, "fp"}, - { SPARC_REG_G0, "g0"}, - { SPARC_REG_G1, "g1"}, - { SPARC_REG_G2, "g2"}, - { SPARC_REG_G3, "g3"}, - { SPARC_REG_G4, "g4"}, - { SPARC_REG_G5, "g5"}, - { SPARC_REG_G6, "g6"}, - { SPARC_REG_G7, "g7"}, - { SPARC_REG_I0, "i0"}, - { SPARC_REG_I1, "i1"}, - { SPARC_REG_I2, "i2"}, - { SPARC_REG_I3, "i3"}, - { SPARC_REG_I4, "i4"}, - { SPARC_REG_I5, "i5"}, - { SPARC_REG_I7, "i7"}, - { SPARC_REG_ICC, "icc"}, - { SPARC_REG_L0, "l0"}, - { SPARC_REG_L1, "l1"}, - { SPARC_REG_L2, "l2"}, - { SPARC_REG_L3, "l3"}, - { SPARC_REG_L4, "l4"}, - { SPARC_REG_L5, "l5"}, - { SPARC_REG_L6, "l6"}, - { SPARC_REG_L7, "l7"}, - { SPARC_REG_O0, "o0"}, - { SPARC_REG_O1, "o1"}, - { SPARC_REG_O2, "o2"}, - { SPARC_REG_O3, "o3"}, - { SPARC_REG_O4, "o4"}, - { SPARC_REG_O5, "o5"}, - { SPARC_REG_O7, "o7"}, - { SPARC_REG_SP, "sp"}, - { SPARC_REG_Y, "y"}, - - // special registers - { SPARC_REG_XCC, "xcc"}, + {SPARC_REG_INVALID, NULL}, + + {SP_F0, "f0"}, + {SP_F1, "f1"}, + {SP_F2, "f2"}, + {SP_F3, "f3"}, + {SP_F4, "f4"}, + {SP_F5, "f5"}, + {SP_F6, "f6"}, + {SP_F7, "f7"}, + {SP_F8, "f8"}, + {SP_F9, "f9"}, + {SP_F10, "f10"}, + {SP_F11, "f11"}, + {SP_F12, "f12"}, + {SP_F13, "f13"}, + {SP_F14, "f14"}, + {SP_F15, "f15"}, + {SP_F16, "f16"}, + {SP_F17, "f17"}, + {SP_F18, "f18"}, + {SP_F19, "f19"}, + {SP_F20, "f20"}, + {SP_F21, "f21"}, + {SP_F22, "f22"}, + {SP_F23, "f23"}, + {SP_F24, "f24"}, + {SP_F25, "f25"}, + {SP_F26, "f26"}, + {SP_F27, "f27"}, + {SP_F28, "f28"}, + {SP_F29, "f29"}, + {SP_F30, "f30"}, + {SP_F31, "f31"}, + {SP_D0, "f0"}, + {SP_D1, "f2"}, + {SP_D2, "f4"}, + {SP_D3, "f6"}, + {SP_D4, "f8"}, + {SP_D5, "f10"}, + {SP_D6, "f12"}, + {SP_D7, "f14"}, + {SP_D8, "f16"}, + {SP_D9, "f18"}, + {SP_D10, "f20"}, + {SP_D11, "f22"}, + {SP_D12, "f24"}, + {SP_D13, "f26"}, + {SP_D14, "f28"}, + {SP_D15, "f30"}, + {SP_D16, "f32"}, + {SP_D17, "f34"}, + {SP_D18, "f36"}, + {SP_D19, "f38"}, + {SP_D20, "f40"}, + {SP_D21, "f42"}, + {SP_D22, "f44"}, + {SP_D23, "f46"}, + {SP_D24, "f48"}, + {SP_D25, "f50"}, + {SP_D26, "f52"}, + {SP_D27, "f54"}, + {SP_D28, "f56"}, + {SP_D29, "f58"}, + {SP_D30, "f60"}, + {SP_D31, "f62"}, + {SP_Q0, "f0"}, + {SP_Q1, "f4"}, + {SP_Q2, "f8"}, + {SP_Q3, "f12"}, + {SP_Q4, "f16"}, + {SP_Q5, "f20"}, + {SP_Q6, "f24"}, + {SP_Q7, "f28"}, + {SP_Q8, "f32"}, + {SP_Q9, "f36"}, + {SP_Q10, "f40"}, + {SP_Q11, "f44"}, + {SP_Q12, "f48"}, + {SP_Q13, "f52"}, + {SP_Q14, "f56"}, + {SP_Q15, "f60"}, + // { SP_F32, "f32"}, + // { SP_F34, "f34"}, + // { SP_F36, "f36"}, + // { SP_F38, "f38"}, + // { SP_F40, "f40"}, + // { SP_F42, "f42"}, + // { SP_F44, "f44"}, + // { SP_F46, "f46"}, + // { SP_F48, "f48"}, + // { SP_F50, "f50"}, + // { SP_F52, "f52"}, + // { SP_F54, "f54"}, + // { SP_F56, "f56"}, + // { SP_F58, "f58"}, + // { SP_F60, "f60"}, + // { SP_F62, "f62"}, + {SP_FCC0, "fcc0"}, + {SP_FCC1, "fcc1"}, + {SP_FCC2, "fcc2"}, + {SP_FCC3, "fcc3"}, + {SP_I6, "fp"}, + {SP_G0, "g0"}, + {SP_G1, "g1"}, + {SP_G2, "g2"}, + {SP_G3, "g3"}, + {SP_G4, "g4"}, + {SP_G5, "g5"}, + {SP_G6, "g6"}, + {SP_G7, "g7"}, + {SP_I0, "i0"}, + {SP_I1, "i1"}, + {SP_I2, "i2"}, + {SP_I3, "i3"}, + {SP_I4, "i4"}, + {SP_I5, "i5"}, + {SP_I7, "i7"}, + {SP_ICC, "icc"}, + {SP_L0, "l0"}, + {SP_L1, "l1"}, + {SP_L2, "l2"}, + {SP_L3, "l3"}, + {SP_L4, "l4"}, + {SP_L5, "l5"}, + {SP_L6, "l6"}, + {SP_L7, "l7"}, + {SP_O0, "o0"}, + {SP_O1, "o1"}, + {SP_O2, "o2"}, + {SP_O3, "o3"}, + {SP_O4, "o4"}, + {SP_O5, "o5"}, + {SP_O7, "o7"}, + {SP_O6, "sp"}, + {SP_Y, "y"}, + + // special registers + // { SP_XCC, "xcc"}, }; #endif -const char *Sparc_reg_name(csh handle, unsigned int reg) -{ +const char *Sparc_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; - - return reg_name_maps[reg].name; + for (int i = 0; i < ARR_SIZE(reg_name_maps); i++) { + if (reg_name_maps[i].id == reg) { + return reg_name_maps[i].name; + } + } + + // invalid + return "invalid"; #else - return NULL; + return NULL; #endif } static const insn_map insns[] = { - // dummy item - { - 0, 0, + // dummy item + {0, + 0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif - }, + }, #include "SparcMappingInsn.inc" }; static struct hint_map { - unsigned int id; - uint8_t hints; + unsigned int id; + uint8_t hints; } const insn_hints[] = { - { SP_BPGEZapn, SPARC_HINT_A | SPARC_HINT_PN }, - { SP_BPGEZapt, SPARC_HINT_A | SPARC_HINT_PT }, - { SP_BPGEZnapn, SPARC_HINT_PN }, - { SP_BPGZapn, SPARC_HINT_A | SPARC_HINT_PN }, - { SP_BPGZapt, SPARC_HINT_A | SPARC_HINT_PT }, - { SP_BPGZnapn, SPARC_HINT_PN }, - { SP_BPLEZapn, SPARC_HINT_A | SPARC_HINT_PN }, - { SP_BPLEZapt, SPARC_HINT_A | SPARC_HINT_PT }, - { SP_BPLEZnapn, SPARC_HINT_PN }, - { SP_BPLZapn, SPARC_HINT_A | SPARC_HINT_PN }, - { SP_BPLZapt, SPARC_HINT_A | SPARC_HINT_PT }, - { SP_BPLZnapn, SPARC_HINT_PN }, - { SP_BPNZapn, SPARC_HINT_A | SPARC_HINT_PN }, - { SP_BPNZapt, SPARC_HINT_A | SPARC_HINT_PT }, - { SP_BPNZnapn, SPARC_HINT_PN }, - { SP_BPZapn, SPARC_HINT_A | SPARC_HINT_PN }, - { SP_BPZapt, SPARC_HINT_A | SPARC_HINT_PT }, - { SP_BPZnapn, SPARC_HINT_PN }, + {SP_BPGEZapn, SPARC_HINT_A | SPARC_HINT_PN}, + {SP_BPGEZapt, SPARC_HINT_A | SPARC_HINT_PT}, + {SP_BPGEZnapn, SPARC_HINT_PN}, + {SP_BPGZapn, SPARC_HINT_A | SPARC_HINT_PN}, + {SP_BPGZapt, SPARC_HINT_A | SPARC_HINT_PT}, + {SP_BPGZnapn, SPARC_HINT_PN}, + {SP_BPLEZapn, SPARC_HINT_A | SPARC_HINT_PN}, + {SP_BPLEZapt, SPARC_HINT_A | SPARC_HINT_PT}, + {SP_BPLEZnapn, SPARC_HINT_PN}, + {SP_BPLZapn, SPARC_HINT_A | SPARC_HINT_PN}, + {SP_BPLZapt, SPARC_HINT_A | SPARC_HINT_PT}, + {SP_BPLZnapn, SPARC_HINT_PN}, + {SP_BPNZapn, SPARC_HINT_A | SPARC_HINT_PN}, + {SP_BPNZapt, SPARC_HINT_A | SPARC_HINT_PT}, + {SP_BPNZnapn, SPARC_HINT_PN}, + {SP_BPZapn, SPARC_HINT_A | SPARC_HINT_PN}, + {SP_BPZapt, SPARC_HINT_A | SPARC_HINT_PT}, + {SP_BPZnapn, SPARC_HINT_PN}, }; // given internal insn id, return public instruction info -void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) -{ - unsigned short i; +void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { + unsigned short i; - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; - if (h->detail) { + if (h->detail) { #ifndef CAPSTONE_DIET - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); - - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); - - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = SPARC_GRP_JUMP; - insn->detail->groups_count++; - } + memcpy(insn->detail->regs_read, insns[i].regs_use, + sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = + (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, + sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = + (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = SPARC_GRP_JUMP; + insn->detail->groups_count++; + } #endif - // hint code - for (i = 0; i < ARR_SIZE(insn_hints); i++) { - if (id == insn_hints[i].id) { - insn->detail->sparc.hint = insn_hints[i].hints; - break; - } - } - } - } + // hint code + for (i = 0; i < ARR_SIZE(insn_hints); i++) { + if (id == insn_hints[i].id) { + insn->detail->sparc.hint = insn_hints[i].hints; + break; + } + } + } + } } static const name_map insn_name_maps[] = { - { SPARC_INS_INVALID, NULL }, - - { SPARC_INS_ADDCC, "addcc" }, - { SPARC_INS_ADDX, "addx" }, - { SPARC_INS_ADDXCC, "addxcc" }, - { SPARC_INS_ADDXC, "addxc" }, - { SPARC_INS_ADDXCCC, "addxccc" }, - { SPARC_INS_ADD, "add" }, - { SPARC_INS_ALIGNADDR, "alignaddr" }, - { SPARC_INS_ALIGNADDRL, "alignaddrl" }, - { SPARC_INS_ANDCC, "andcc" }, - { SPARC_INS_ANDNCC, "andncc" }, - { SPARC_INS_ANDN, "andn" }, - { SPARC_INS_AND, "and" }, - { SPARC_INS_ARRAY16, "array16" }, - { SPARC_INS_ARRAY32, "array32" }, - { SPARC_INS_ARRAY8, "array8" }, - { SPARC_INS_B, "b" }, - { SPARC_INS_JMP, "jmp" }, - { SPARC_INS_BMASK, "bmask" }, - { SPARC_INS_FB, "fb" }, - { SPARC_INS_BRGEZ, "brgez" }, - { SPARC_INS_BRGZ, "brgz" }, - { SPARC_INS_BRLEZ, "brlez" }, - { SPARC_INS_BRLZ, "brlz" }, - { SPARC_INS_BRNZ, "brnz" }, - { SPARC_INS_BRZ, "brz" }, - { SPARC_INS_BSHUFFLE, "bshuffle" }, - { SPARC_INS_CALL, "call" }, - { SPARC_INS_CASX, "casx" }, - { SPARC_INS_CAS, "cas" }, - { SPARC_INS_CMASK16, "cmask16" }, - { SPARC_INS_CMASK32, "cmask32" }, - { SPARC_INS_CMASK8, "cmask8" }, - { SPARC_INS_CMP, "cmp" }, - { SPARC_INS_EDGE16, "edge16" }, - { SPARC_INS_EDGE16L, "edge16l" }, - { SPARC_INS_EDGE16LN, "edge16ln" }, - { SPARC_INS_EDGE16N, "edge16n" }, - { SPARC_INS_EDGE32, "edge32" }, - { SPARC_INS_EDGE32L, "edge32l" }, - { SPARC_INS_EDGE32LN, "edge32ln" }, - { SPARC_INS_EDGE32N, "edge32n" }, - { SPARC_INS_EDGE8, "edge8" }, - { SPARC_INS_EDGE8L, "edge8l" }, - { SPARC_INS_EDGE8LN, "edge8ln" }, - { SPARC_INS_EDGE8N, "edge8n" }, - { SPARC_INS_FABSD, "fabsd" }, - { SPARC_INS_FABSQ, "fabsq" }, - { SPARC_INS_FABSS, "fabss" }, - { SPARC_INS_FADDD, "faddd" }, - { SPARC_INS_FADDQ, "faddq" }, - { SPARC_INS_FADDS, "fadds" }, - { SPARC_INS_FALIGNDATA, "faligndata" }, - { SPARC_INS_FAND, "fand" }, - { SPARC_INS_FANDNOT1, "fandnot1" }, - { SPARC_INS_FANDNOT1S, "fandnot1s" }, - { SPARC_INS_FANDNOT2, "fandnot2" }, - { SPARC_INS_FANDNOT2S, "fandnot2s" }, - { SPARC_INS_FANDS, "fands" }, - { SPARC_INS_FCHKSM16, "fchksm16" }, - { SPARC_INS_FCMPD, "fcmpd" }, - { SPARC_INS_FCMPEQ16, "fcmpeq16" }, - { SPARC_INS_FCMPEQ32, "fcmpeq32" }, - { SPARC_INS_FCMPGT16, "fcmpgt16" }, - { SPARC_INS_FCMPGT32, "fcmpgt32" }, - { SPARC_INS_FCMPLE16, "fcmple16" }, - { SPARC_INS_FCMPLE32, "fcmple32" }, - { SPARC_INS_FCMPNE16, "fcmpne16" }, - { SPARC_INS_FCMPNE32, "fcmpne32" }, - { SPARC_INS_FCMPQ, "fcmpq" }, - { SPARC_INS_FCMPS, "fcmps" }, - { SPARC_INS_FDIVD, "fdivd" }, - { SPARC_INS_FDIVQ, "fdivq" }, - { SPARC_INS_FDIVS, "fdivs" }, - { SPARC_INS_FDMULQ, "fdmulq" }, - { SPARC_INS_FDTOI, "fdtoi" }, - { SPARC_INS_FDTOQ, "fdtoq" }, - { SPARC_INS_FDTOS, "fdtos" }, - { SPARC_INS_FDTOX, "fdtox" }, - { SPARC_INS_FEXPAND, "fexpand" }, - { SPARC_INS_FHADDD, "fhaddd" }, - { SPARC_INS_FHADDS, "fhadds" }, - { SPARC_INS_FHSUBD, "fhsubd" }, - { SPARC_INS_FHSUBS, "fhsubs" }, - { SPARC_INS_FITOD, "fitod" }, - { SPARC_INS_FITOQ, "fitoq" }, - { SPARC_INS_FITOS, "fitos" }, - { SPARC_INS_FLCMPD, "flcmpd" }, - { SPARC_INS_FLCMPS, "flcmps" }, - { SPARC_INS_FLUSHW, "flushw" }, - { SPARC_INS_FMEAN16, "fmean16" }, - { SPARC_INS_FMOVD, "fmovd" }, - { SPARC_INS_FMOVQ, "fmovq" }, - { SPARC_INS_FMOVRDGEZ, "fmovrdgez" }, - { SPARC_INS_FMOVRQGEZ, "fmovrqgez" }, - { SPARC_INS_FMOVRSGEZ, "fmovrsgez" }, - { SPARC_INS_FMOVRDGZ, "fmovrdgz" }, - { SPARC_INS_FMOVRQGZ, "fmovrqgz" }, - { SPARC_INS_FMOVRSGZ, "fmovrsgz" }, - { SPARC_INS_FMOVRDLEZ, "fmovrdlez" }, - { SPARC_INS_FMOVRQLEZ, "fmovrqlez" }, - { SPARC_INS_FMOVRSLEZ, "fmovrslez" }, - { SPARC_INS_FMOVRDLZ, "fmovrdlz" }, - { SPARC_INS_FMOVRQLZ, "fmovrqlz" }, - { SPARC_INS_FMOVRSLZ, "fmovrslz" }, - { SPARC_INS_FMOVRDNZ, "fmovrdnz" }, - { SPARC_INS_FMOVRQNZ, "fmovrqnz" }, - { SPARC_INS_FMOVRSNZ, "fmovrsnz" }, - { SPARC_INS_FMOVRDZ, "fmovrdz" }, - { SPARC_INS_FMOVRQZ, "fmovrqz" }, - { SPARC_INS_FMOVRSZ, "fmovrsz" }, - { SPARC_INS_FMOVS, "fmovs" }, - { SPARC_INS_FMUL8SUX16, "fmul8sux16" }, - { SPARC_INS_FMUL8ULX16, "fmul8ulx16" }, - { SPARC_INS_FMUL8X16, "fmul8x16" }, - { SPARC_INS_FMUL8X16AL, "fmul8x16al" }, - { SPARC_INS_FMUL8X16AU, "fmul8x16au" }, - { SPARC_INS_FMULD, "fmuld" }, - { SPARC_INS_FMULD8SUX16, "fmuld8sux16" }, - { SPARC_INS_FMULD8ULX16, "fmuld8ulx16" }, - { SPARC_INS_FMULQ, "fmulq" }, - { SPARC_INS_FMULS, "fmuls" }, - { SPARC_INS_FNADDD, "fnaddd" }, - { SPARC_INS_FNADDS, "fnadds" }, - { SPARC_INS_FNAND, "fnand" }, - { SPARC_INS_FNANDS, "fnands" }, - { SPARC_INS_FNEGD, "fnegd" }, - { SPARC_INS_FNEGQ, "fnegq" }, - { SPARC_INS_FNEGS, "fnegs" }, - { SPARC_INS_FNHADDD, "fnhaddd" }, - { SPARC_INS_FNHADDS, "fnhadds" }, - { SPARC_INS_FNOR, "fnor" }, - { SPARC_INS_FNORS, "fnors" }, - { SPARC_INS_FNOT1, "fnot1" }, - { SPARC_INS_FNOT1S, "fnot1s" }, - { SPARC_INS_FNOT2, "fnot2" }, - { SPARC_INS_FNOT2S, "fnot2s" }, - { SPARC_INS_FONE, "fone" }, - { SPARC_INS_FONES, "fones" }, - { SPARC_INS_FOR, "for" }, - { SPARC_INS_FORNOT1, "fornot1" }, - { SPARC_INS_FORNOT1S, "fornot1s" }, - { SPARC_INS_FORNOT2, "fornot2" }, - { SPARC_INS_FORNOT2S, "fornot2s" }, - { SPARC_INS_FORS, "fors" }, - { SPARC_INS_FPACK16, "fpack16" }, - { SPARC_INS_FPACK32, "fpack32" }, - { SPARC_INS_FPACKFIX, "fpackfix" }, - { SPARC_INS_FPADD16, "fpadd16" }, - { SPARC_INS_FPADD16S, "fpadd16s" }, - { SPARC_INS_FPADD32, "fpadd32" }, - { SPARC_INS_FPADD32S, "fpadd32s" }, - { SPARC_INS_FPADD64, "fpadd64" }, - { SPARC_INS_FPMERGE, "fpmerge" }, - { SPARC_INS_FPSUB16, "fpsub16" }, - { SPARC_INS_FPSUB16S, "fpsub16s" }, - { SPARC_INS_FPSUB32, "fpsub32" }, - { SPARC_INS_FPSUB32S, "fpsub32s" }, - { SPARC_INS_FQTOD, "fqtod" }, - { SPARC_INS_FQTOI, "fqtoi" }, - { SPARC_INS_FQTOS, "fqtos" }, - { SPARC_INS_FQTOX, "fqtox" }, - { SPARC_INS_FSLAS16, "fslas16" }, - { SPARC_INS_FSLAS32, "fslas32" }, - { SPARC_INS_FSLL16, "fsll16" }, - { SPARC_INS_FSLL32, "fsll32" }, - { SPARC_INS_FSMULD, "fsmuld" }, - { SPARC_INS_FSQRTD, "fsqrtd" }, - { SPARC_INS_FSQRTQ, "fsqrtq" }, - { SPARC_INS_FSQRTS, "fsqrts" }, - { SPARC_INS_FSRA16, "fsra16" }, - { SPARC_INS_FSRA32, "fsra32" }, - { SPARC_INS_FSRC1, "fsrc1" }, - { SPARC_INS_FSRC1S, "fsrc1s" }, - { SPARC_INS_FSRC2, "fsrc2" }, - { SPARC_INS_FSRC2S, "fsrc2s" }, - { SPARC_INS_FSRL16, "fsrl16" }, - { SPARC_INS_FSRL32, "fsrl32" }, - { SPARC_INS_FSTOD, "fstod" }, - { SPARC_INS_FSTOI, "fstoi" }, - { SPARC_INS_FSTOQ, "fstoq" }, - { SPARC_INS_FSTOX, "fstox" }, - { SPARC_INS_FSUBD, "fsubd" }, - { SPARC_INS_FSUBQ, "fsubq" }, - { SPARC_INS_FSUBS, "fsubs" }, - { SPARC_INS_FXNOR, "fxnor" }, - { SPARC_INS_FXNORS, "fxnors" }, - { SPARC_INS_FXOR, "fxor" }, - { SPARC_INS_FXORS, "fxors" }, - { SPARC_INS_FXTOD, "fxtod" }, - { SPARC_INS_FXTOQ, "fxtoq" }, - { SPARC_INS_FXTOS, "fxtos" }, - { SPARC_INS_FZERO, "fzero" }, - { SPARC_INS_FZEROS, "fzeros" }, - { SPARC_INS_JMPL, "jmpl" }, - { SPARC_INS_LDD, "ldd" }, - { SPARC_INS_LD, "ld" }, - { SPARC_INS_LDQ, "ldq" }, - { SPARC_INS_LDSB, "ldsb" }, - { SPARC_INS_LDSH, "ldsh" }, - { SPARC_INS_LDSW, "ldsw" }, - { SPARC_INS_LDUB, "ldub" }, - { SPARC_INS_LDUH, "lduh" }, - { SPARC_INS_LDX, "ldx" }, - { SPARC_INS_LZCNT, "lzcnt" }, - { SPARC_INS_MEMBAR, "membar" }, - { SPARC_INS_MOVDTOX, "movdtox" }, - { SPARC_INS_MOV, "mov" }, - { SPARC_INS_MOVRGEZ, "movrgez" }, - { SPARC_INS_MOVRGZ, "movrgz" }, - { SPARC_INS_MOVRLEZ, "movrlez" }, - { SPARC_INS_MOVRLZ, "movrlz" }, - { SPARC_INS_MOVRNZ, "movrnz" }, - { SPARC_INS_MOVRZ, "movrz" }, - { SPARC_INS_MOVSTOSW, "movstosw" }, - { SPARC_INS_MOVSTOUW, "movstouw" }, - { SPARC_INS_MULX, "mulx" }, - { SPARC_INS_NOP, "nop" }, - { SPARC_INS_ORCC, "orcc" }, - { SPARC_INS_ORNCC, "orncc" }, - { SPARC_INS_ORN, "orn" }, - { SPARC_INS_OR, "or" }, - { SPARC_INS_PDIST, "pdist" }, - { SPARC_INS_PDISTN, "pdistn" }, - { SPARC_INS_POPC, "popc" }, - { SPARC_INS_RD, "rd" }, - { SPARC_INS_RESTORE, "restore" }, - { SPARC_INS_RETT, "rett" }, - { SPARC_INS_SAVE, "save" }, - { SPARC_INS_SDIVCC, "sdivcc" }, - { SPARC_INS_SDIVX, "sdivx" }, - { SPARC_INS_SDIV, "sdiv" }, - { SPARC_INS_SETHI, "sethi" }, - { SPARC_INS_SHUTDOWN, "shutdown" }, - { SPARC_INS_SIAM, "siam" }, - { SPARC_INS_SLLX, "sllx" }, - { SPARC_INS_SLL, "sll" }, - { SPARC_INS_SMULCC, "smulcc" }, - { SPARC_INS_SMUL, "smul" }, - { SPARC_INS_SRAX, "srax" }, - { SPARC_INS_SRA, "sra" }, - { SPARC_INS_SRLX, "srlx" }, - { SPARC_INS_SRL, "srl" }, - { SPARC_INS_STBAR, "stbar" }, - { SPARC_INS_STB, "stb" }, - { SPARC_INS_STD, "std" }, - { SPARC_INS_ST, "st" }, - { SPARC_INS_STH, "sth" }, - { SPARC_INS_STQ, "stq" }, - { SPARC_INS_STX, "stx" }, - { SPARC_INS_SUBCC, "subcc" }, - { SPARC_INS_SUBX, "subx" }, - { SPARC_INS_SUBXCC, "subxcc" }, - { SPARC_INS_SUB, "sub" }, - { SPARC_INS_SWAP, "swap" }, - { SPARC_INS_TADDCCTV, "taddcctv" }, - { SPARC_INS_TADDCC, "taddcc" }, - { SPARC_INS_T, "t" }, - { SPARC_INS_TSUBCCTV, "tsubcctv" }, - { SPARC_INS_TSUBCC, "tsubcc" }, - { SPARC_INS_UDIVCC, "udivcc" }, - { SPARC_INS_UDIVX, "udivx" }, - { SPARC_INS_UDIV, "udiv" }, - { SPARC_INS_UMULCC, "umulcc" }, - { SPARC_INS_UMULXHI, "umulxhi" }, - { SPARC_INS_UMUL, "umul" }, - { SPARC_INS_UNIMP, "unimp" }, - { SPARC_INS_FCMPED, "fcmped" }, - { SPARC_INS_FCMPEQ, "fcmpeq" }, - { SPARC_INS_FCMPES, "fcmpes" }, - { SPARC_INS_WR, "wr" }, - { SPARC_INS_XMULX, "xmulx" }, - { SPARC_INS_XMULXHI, "xmulxhi" }, - { SPARC_INS_XNORCC, "xnorcc" }, - { SPARC_INS_XNOR, "xnor" }, - { SPARC_INS_XORCC, "xorcc" }, - { SPARC_INS_XOR, "xor" }, - - // alias instructions - { SPARC_INS_RET, "ret" }, - { SPARC_INS_RETL, "retl" }, + {SPARC_INS_INVALID, NULL}, + + {SPARC_INS_ADDCC, "addcc"}, + {SPARC_INS_ADDX, "addx"}, + {SPARC_INS_ADDXCC, "addxcc"}, + {SPARC_INS_ADDXC, "addxc"}, + {SPARC_INS_ADDXCCC, "addxccc"}, + {SPARC_INS_ADD, "add"}, + {SPARC_INS_ALIGNADDR, "alignaddr"}, + {SPARC_INS_ALIGNADDRL, "alignaddrl"}, + {SPARC_INS_ANDCC, "andcc"}, + {SPARC_INS_ANDNCC, "andncc"}, + {SPARC_INS_ANDN, "andn"}, + {SPARC_INS_AND, "and"}, + {SPARC_INS_ARRAY16, "array16"}, + {SPARC_INS_ARRAY32, "array32"}, + {SPARC_INS_ARRAY8, "array8"}, + {SPARC_INS_B, "b"}, + {SPARC_INS_JMP, "jmp"}, + {SPARC_INS_BMASK, "bmask"}, + {SPARC_INS_FB, "fb"}, + {SPARC_INS_BRGEZ, "brgez"}, + {SPARC_INS_BRGZ, "brgz"}, + {SPARC_INS_BRLEZ, "brlez"}, + {SPARC_INS_BRLZ, "brlz"}, + {SPARC_INS_BRNZ, "brnz"}, + {SPARC_INS_BRZ, "brz"}, + {SPARC_INS_BSHUFFLE, "bshuffle"}, + {SPARC_INS_CALL, "call"}, + {SPARC_INS_CASX, "casx"}, + {SPARC_INS_CAS, "cas"}, + {SPARC_INS_CMASK16, "cmask16"}, + {SPARC_INS_CMASK32, "cmask32"}, + {SPARC_INS_CMASK8, "cmask8"}, + {SPARC_INS_CMP, "cmp"}, + {SPARC_INS_EDGE16, "edge16"}, + {SPARC_INS_EDGE16L, "edge16l"}, + {SPARC_INS_EDGE16LN, "edge16ln"}, + {SPARC_INS_EDGE16N, "edge16n"}, + {SPARC_INS_EDGE32, "edge32"}, + {SPARC_INS_EDGE32L, "edge32l"}, + {SPARC_INS_EDGE32LN, "edge32ln"}, + {SPARC_INS_EDGE32N, "edge32n"}, + {SPARC_INS_EDGE8, "edge8"}, + {SPARC_INS_EDGE8L, "edge8l"}, + {SPARC_INS_EDGE8LN, "edge8ln"}, + {SPARC_INS_EDGE8N, "edge8n"}, + {SPARC_INS_FABSD, "fabsd"}, + {SPARC_INS_FABSQ, "fabsq"}, + {SPARC_INS_FABSS, "fabss"}, + {SPARC_INS_FADDD, "faddd"}, + {SPARC_INS_FADDQ, "faddq"}, + {SPARC_INS_FADDS, "fadds"}, + {SPARC_INS_FALIGNDATA, "faligndata"}, + {SPARC_INS_FAND, "fand"}, + {SPARC_INS_FANDNOT1, "fandnot1"}, + {SPARC_INS_FANDNOT1S, "fandnot1s"}, + {SPARC_INS_FANDNOT2, "fandnot2"}, + {SPARC_INS_FANDNOT2S, "fandnot2s"}, + {SPARC_INS_FANDS, "fands"}, + {SPARC_INS_FCHKSM16, "fchksm16"}, + {SPARC_INS_FCMPD, "fcmpd"}, + {SPARC_INS_FCMPEQ16, "fcmpeq16"}, + {SPARC_INS_FCMPEQ32, "fcmpeq32"}, + {SPARC_INS_FCMPGT16, "fcmpgt16"}, + {SPARC_INS_FCMPGT32, "fcmpgt32"}, + {SPARC_INS_FCMPLE16, "fcmple16"}, + {SPARC_INS_FCMPLE32, "fcmple32"}, + {SPARC_INS_FCMPNE16, "fcmpne16"}, + {SPARC_INS_FCMPNE32, "fcmpne32"}, + {SPARC_INS_FCMPQ, "fcmpq"}, + {SPARC_INS_FCMPS, "fcmps"}, + {SPARC_INS_FDIVD, "fdivd"}, + {SPARC_INS_FDIVQ, "fdivq"}, + {SPARC_INS_FDIVS, "fdivs"}, + {SPARC_INS_FDMULQ, "fdmulq"}, + {SPARC_INS_FDTOI, "fdtoi"}, + {SPARC_INS_FDTOQ, "fdtoq"}, + {SPARC_INS_FDTOS, "fdtos"}, + {SPARC_INS_FDTOX, "fdtox"}, + {SPARC_INS_FEXPAND, "fexpand"}, + {SPARC_INS_FHADDD, "fhaddd"}, + {SPARC_INS_FHADDS, "fhadds"}, + {SPARC_INS_FHSUBD, "fhsubd"}, + {SPARC_INS_FHSUBS, "fhsubs"}, + {SPARC_INS_FITOD, "fitod"}, + {SPARC_INS_FITOQ, "fitoq"}, + {SPARC_INS_FITOS, "fitos"}, + {SPARC_INS_FLCMPD, "flcmpd"}, + {SPARC_INS_FLCMPS, "flcmps"}, + {SPARC_INS_FLUSHW, "flushw"}, + {SPARC_INS_FMEAN16, "fmean16"}, + {SPARC_INS_FMOVD, "fmovd"}, + {SPARC_INS_FMOVQ, "fmovq"}, + {SPARC_INS_FMOVRDGEZ, "fmovrdgez"}, + {SPARC_INS_FMOVRQGEZ, "fmovrqgez"}, + {SPARC_INS_FMOVRSGEZ, "fmovrsgez"}, + {SPARC_INS_FMOVRDGZ, "fmovrdgz"}, + {SPARC_INS_FMOVRQGZ, "fmovrqgz"}, + {SPARC_INS_FMOVRSGZ, "fmovrsgz"}, + {SPARC_INS_FMOVRDLEZ, "fmovrdlez"}, + {SPARC_INS_FMOVRQLEZ, "fmovrqlez"}, + {SPARC_INS_FMOVRSLEZ, "fmovrslez"}, + {SPARC_INS_FMOVRDLZ, "fmovrdlz"}, + {SPARC_INS_FMOVRQLZ, "fmovrqlz"}, + {SPARC_INS_FMOVRSLZ, "fmovrslz"}, + {SPARC_INS_FMOVRDNZ, "fmovrdnz"}, + {SPARC_INS_FMOVRQNZ, "fmovrqnz"}, + {SPARC_INS_FMOVRSNZ, "fmovrsnz"}, + {SPARC_INS_FMOVRDZ, "fmovrdz"}, + {SPARC_INS_FMOVRQZ, "fmovrqz"}, + {SPARC_INS_FMOVRSZ, "fmovrsz"}, + {SPARC_INS_FMOVS, "fmovs"}, + {SPARC_INS_FMUL8SUX16, "fmul8sux16"}, + {SPARC_INS_FMUL8ULX16, "fmul8ulx16"}, + {SPARC_INS_FMUL8X16, "fmul8x16"}, + {SPARC_INS_FMUL8X16AL, "fmul8x16al"}, + {SPARC_INS_FMUL8X16AU, "fmul8x16au"}, + {SPARC_INS_FMULD, "fmuld"}, + {SPARC_INS_FMULD8SUX16, "fmuld8sux16"}, + {SPARC_INS_FMULD8ULX16, "fmuld8ulx16"}, + {SPARC_INS_FMULQ, "fmulq"}, + {SPARC_INS_FMULS, "fmuls"}, + {SPARC_INS_FNADDD, "fnaddd"}, + {SPARC_INS_FNADDS, "fnadds"}, + {SPARC_INS_FNAND, "fnand"}, + {SPARC_INS_FNANDS, "fnands"}, + {SPARC_INS_FNEGD, "fnegd"}, + {SPARC_INS_FNEGQ, "fnegq"}, + {SPARC_INS_FNEGS, "fnegs"}, + {SPARC_INS_FNHADDD, "fnhaddd"}, + {SPARC_INS_FNHADDS, "fnhadds"}, + {SPARC_INS_FNOR, "fnor"}, + {SPARC_INS_FNORS, "fnors"}, + {SPARC_INS_FNOT1, "fnot1"}, + {SPARC_INS_FNOT1S, "fnot1s"}, + {SPARC_INS_FNOT2, "fnot2"}, + {SPARC_INS_FNOT2S, "fnot2s"}, + {SPARC_INS_FONE, "fone"}, + {SPARC_INS_FONES, "fones"}, + {SPARC_INS_FOR, "for"}, + {SPARC_INS_FORNOT1, "fornot1"}, + {SPARC_INS_FORNOT1S, "fornot1s"}, + {SPARC_INS_FORNOT2, "fornot2"}, + {SPARC_INS_FORNOT2S, "fornot2s"}, + {SPARC_INS_FORS, "fors"}, + {SPARC_INS_FPACK16, "fpack16"}, + {SPARC_INS_FPACK32, "fpack32"}, + {SPARC_INS_FPACKFIX, "fpackfix"}, + {SPARC_INS_FPADD16, "fpadd16"}, + {SPARC_INS_FPADD16S, "fpadd16s"}, + {SPARC_INS_FPADD32, "fpadd32"}, + {SPARC_INS_FPADD32S, "fpadd32s"}, + {SPARC_INS_FPADD64, "fpadd64"}, + {SPARC_INS_FPMERGE, "fpmerge"}, + {SPARC_INS_FPSUB16, "fpsub16"}, + {SPARC_INS_FPSUB16S, "fpsub16s"}, + {SPARC_INS_FPSUB32, "fpsub32"}, + {SPARC_INS_FPSUB32S, "fpsub32s"}, + {SPARC_INS_FQTOD, "fqtod"}, + {SPARC_INS_FQTOI, "fqtoi"}, + {SPARC_INS_FQTOS, "fqtos"}, + {SPARC_INS_FQTOX, "fqtox"}, + {SPARC_INS_FSLAS16, "fslas16"}, + {SPARC_INS_FSLAS32, "fslas32"}, + {SPARC_INS_FSLL16, "fsll16"}, + {SPARC_INS_FSLL32, "fsll32"}, + {SPARC_INS_FSMULD, "fsmuld"}, + {SPARC_INS_FSQRTD, "fsqrtd"}, + {SPARC_INS_FSQRTQ, "fsqrtq"}, + {SPARC_INS_FSQRTS, "fsqrts"}, + {SPARC_INS_FSRA16, "fsra16"}, + {SPARC_INS_FSRA32, "fsra32"}, + {SPARC_INS_FSRC1, "fsrc1"}, + {SPARC_INS_FSRC1S, "fsrc1s"}, + {SPARC_INS_FSRC2, "fsrc2"}, + {SPARC_INS_FSRC2S, "fsrc2s"}, + {SPARC_INS_FSRL16, "fsrl16"}, + {SPARC_INS_FSRL32, "fsrl32"}, + {SPARC_INS_FSTOD, "fstod"}, + {SPARC_INS_FSTOI, "fstoi"}, + {SPARC_INS_FSTOQ, "fstoq"}, + {SPARC_INS_FSTOX, "fstox"}, + {SPARC_INS_FSUBD, "fsubd"}, + {SPARC_INS_FSUBQ, "fsubq"}, + {SPARC_INS_FSUBS, "fsubs"}, + {SPARC_INS_FXNOR, "fxnor"}, + {SPARC_INS_FXNORS, "fxnors"}, + {SPARC_INS_FXOR, "fxor"}, + {SPARC_INS_FXORS, "fxors"}, + {SPARC_INS_FXTOD, "fxtod"}, + {SPARC_INS_FXTOQ, "fxtoq"}, + {SPARC_INS_FXTOS, "fxtos"}, + {SPARC_INS_FZERO, "fzero"}, + {SPARC_INS_FZEROS, "fzeros"}, + {SPARC_INS_JMPL, "jmpl"}, + {SPARC_INS_LDD, "ldd"}, + {SPARC_INS_LD, "ld"}, + {SPARC_INS_LDQ, "ldq"}, + {SPARC_INS_LDSB, "ldsb"}, + {SPARC_INS_LDSH, "ldsh"}, + {SPARC_INS_LDSW, "ldsw"}, + {SPARC_INS_LDUB, "ldub"}, + {SPARC_INS_LDUH, "lduh"}, + {SPARC_INS_LDX, "ldx"}, + {SPARC_INS_LZCNT, "lzcnt"}, + {SPARC_INS_MEMBAR, "membar"}, + {SPARC_INS_MOVDTOX, "movdtox"}, + {SPARC_INS_MOV, "mov"}, + {SPARC_INS_MOVRGEZ, "movrgez"}, + {SPARC_INS_MOVRGZ, "movrgz"}, + {SPARC_INS_MOVRLEZ, "movrlez"}, + {SPARC_INS_MOVRLZ, "movrlz"}, + {SPARC_INS_MOVRNZ, "movrnz"}, + {SPARC_INS_MOVRZ, "movrz"}, + {SPARC_INS_MOVSTOSW, "movstosw"}, + {SPARC_INS_MOVSTOUW, "movstouw"}, + {SPARC_INS_MULX, "mulx"}, + {SPARC_INS_NOP, "nop"}, + {SPARC_INS_ORCC, "orcc"}, + {SPARC_INS_ORNCC, "orncc"}, + {SPARC_INS_ORN, "orn"}, + {SPARC_INS_OR, "or"}, + {SPARC_INS_PDIST, "pdist"}, + {SPARC_INS_PDISTN, "pdistn"}, + {SPARC_INS_POPC, "popc"}, + {SPARC_INS_RD, "rd"}, + {SPARC_INS_RESTORE, "restore"}, + {SPARC_INS_RETT, "rett"}, + {SPARC_INS_SAVE, "save"}, + {SPARC_INS_SDIVCC, "sdivcc"}, + {SPARC_INS_SDIVX, "sdivx"}, + {SPARC_INS_SDIV, "sdiv"}, + {SPARC_INS_SETHI, "sethi"}, + {SPARC_INS_SHUTDOWN, "shutdown"}, + {SPARC_INS_SIAM, "siam"}, + {SPARC_INS_SLLX, "sllx"}, + {SPARC_INS_SLL, "sll"}, + {SPARC_INS_SMULCC, "smulcc"}, + {SPARC_INS_SMUL, "smul"}, + {SPARC_INS_SRAX, "srax"}, + {SPARC_INS_SRA, "sra"}, + {SPARC_INS_SRLX, "srlx"}, + {SPARC_INS_SRL, "srl"}, + {SPARC_INS_STBAR, "stbar"}, + {SPARC_INS_STB, "stb"}, + {SPARC_INS_STD, "std"}, + {SPARC_INS_ST, "st"}, + {SPARC_INS_STH, "sth"}, + {SPARC_INS_STQ, "stq"}, + {SPARC_INS_STX, "stx"}, + {SPARC_INS_SUBCC, "subcc"}, + {SPARC_INS_SUBX, "subx"}, + {SPARC_INS_SUBXCC, "subxcc"}, + {SPARC_INS_SUB, "sub"}, + {SPARC_INS_SWAP, "swap"}, + {SPARC_INS_TADDCCTV, "taddcctv"}, + {SPARC_INS_TADDCC, "taddcc"}, + {SPARC_INS_T, "t"}, + {SPARC_INS_TSUBCCTV, "tsubcctv"}, + {SPARC_INS_TSUBCC, "tsubcc"}, + {SPARC_INS_UDIVCC, "udivcc"}, + {SPARC_INS_UDIVX, "udivx"}, + {SPARC_INS_UDIV, "udiv"}, + {SPARC_INS_UMULCC, "umulcc"}, + {SPARC_INS_UMULXHI, "umulxhi"}, + {SPARC_INS_UMUL, "umul"}, + {SPARC_INS_UNIMP, "unimp"}, + {SPARC_INS_FCMPED, "fcmped"}, + {SPARC_INS_FCMPEQ, "fcmpeq"}, + {SPARC_INS_FCMPES, "fcmpes"}, + {SPARC_INS_WR, "wr"}, + {SPARC_INS_XMULX, "xmulx"}, + {SPARC_INS_XMULXHI, "xmulxhi"}, + {SPARC_INS_XNORCC, "xnorcc"}, + {SPARC_INS_XNOR, "xnor"}, + {SPARC_INS_XORCC, "xorcc"}, + {SPARC_INS_XOR, "xor"}, + + // alias instructions + {SPARC_INS_RET, "ret"}, + {SPARC_INS_RETL, "retl"}, }; #ifndef CAPSTONE_DIET // special alias insn -static const name_map alias_insn_names[] = { - { 0, NULL } -}; +static const name_map alias_insn_names[] = {{0, NULL}}; #endif -const char *Sparc_insn_name(csh handle, unsigned int id) -{ +const char *Sparc_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - unsigned int i; + unsigned int i; - if (id >= SPARC_INS_ENDING) - return NULL; + if (id >= SPARC_INS_ENDING) + return NULL; - // handle special alias first - for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { - if (alias_insn_names[i].id == id) - return alias_insn_names[i].name; - } + // handle special alias first + for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { + if (alias_insn_names[i].id == id) + return alias_insn_names[i].name; + } - return insn_name_maps[id].name; + return insn_name_maps[id].name; #else - return NULL; + return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { - // generic groups - { SPARC_GRP_INVALID, NULL }, - { SPARC_GRP_JUMP, "jump" }, - - // architecture-specific groups - { SPARC_GRP_HARDQUAD, "hardquad" }, - { SPARC_GRP_V9, "v9" }, - { SPARC_GRP_VIS, "vis" }, - { SPARC_GRP_VIS2, "vis2" }, - { SPARC_GRP_VIS3, "vis3" }, - { SPARC_GRP_32BIT, "32bit" }, - { SPARC_GRP_64BIT, "64bit" }, + // generic groups + {SPARC_GRP_INVALID, NULL}, + {SPARC_GRP_JUMP, "jump"}, + + // architecture-specific groups + {SPARC_GRP_HARDQUAD, "hardquad"}, + {SPARC_GRP_V9, "v9"}, + {SPARC_GRP_VIS, "vis"}, + {SPARC_GRP_VIS2, "vis2"}, + {SPARC_GRP_VIS3, "vis3"}, + {SPARC_GRP_32BIT, "32bit"}, + {SPARC_GRP_64BIT, "64bit"}, }; #endif -const char *Sparc_group_name(csh handle, unsigned int id) -{ +const char *Sparc_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else - return NULL; + return NULL; #endif } // map internal raw register to 'public' register -sparc_reg Sparc_map_register(unsigned int r) -{ - static const unsigned int map[] = { 0, - SPARC_REG_ICC, SPARC_REG_Y, SPARC_REG_F0, SPARC_REG_F2, SPARC_REG_F4, - SPARC_REG_F6, SPARC_REG_F8, SPARC_REG_F10, SPARC_REG_F12, SPARC_REG_F14, - SPARC_REG_F16, SPARC_REG_F18, SPARC_REG_F20, SPARC_REG_F22, SPARC_REG_F24, - SPARC_REG_F26, SPARC_REG_F28, SPARC_REG_F30, SPARC_REG_F32, SPARC_REG_F34, - SPARC_REG_F36, SPARC_REG_F38, SPARC_REG_F40, SPARC_REG_F42, SPARC_REG_F44, - SPARC_REG_F46, SPARC_REG_F48, SPARC_REG_F50, SPARC_REG_F52, SPARC_REG_F54, - SPARC_REG_F56, SPARC_REG_F58, SPARC_REG_F60, SPARC_REG_F62, SPARC_REG_F0, - SPARC_REG_F1, SPARC_REG_F2, SPARC_REG_F3, SPARC_REG_F4, SPARC_REG_F5, - SPARC_REG_F6, SPARC_REG_F7, SPARC_REG_F8, SPARC_REG_F9, SPARC_REG_F10, - SPARC_REG_F11, SPARC_REG_F12, SPARC_REG_F13, SPARC_REG_F14, SPARC_REG_F15, - SPARC_REG_F16, SPARC_REG_F17, SPARC_REG_F18, SPARC_REG_F19, SPARC_REG_F20, - SPARC_REG_F21, SPARC_REG_F22, SPARC_REG_F23, SPARC_REG_F24, SPARC_REG_F25, - SPARC_REG_F26, SPARC_REG_F27, SPARC_REG_F28, SPARC_REG_F29, SPARC_REG_F30, - SPARC_REG_F31, SPARC_REG_FCC0, SPARC_REG_FCC1, SPARC_REG_FCC2, SPARC_REG_FCC3, - SPARC_REG_G0, SPARC_REG_G1, SPARC_REG_G2, SPARC_REG_G3, SPARC_REG_G4, - SPARC_REG_G5, SPARC_REG_G6, SPARC_REG_G7, SPARC_REG_I0, SPARC_REG_I1, - SPARC_REG_I2, SPARC_REG_I3, SPARC_REG_I4, SPARC_REG_I5, SPARC_REG_FP, - SPARC_REG_I7, SPARC_REG_L0, SPARC_REG_L1, SPARC_REG_L2, SPARC_REG_L3, - SPARC_REG_L4, SPARC_REG_L5, SPARC_REG_L6, SPARC_REG_L7, SPARC_REG_O0, - SPARC_REG_O1, SPARC_REG_O2, SPARC_REG_O3, SPARC_REG_O4, SPARC_REG_O5, - SPARC_REG_SP, SPARC_REG_O7, SPARC_REG_F0, SPARC_REG_F4, SPARC_REG_F8, - SPARC_REG_F12, SPARC_REG_F16, SPARC_REG_F20, SPARC_REG_F24, SPARC_REG_F28, - SPARC_REG_F32, SPARC_REG_F36, SPARC_REG_F40, SPARC_REG_F44, SPARC_REG_F48, - SPARC_REG_F52, SPARC_REG_F56, SPARC_REG_F60, - }; - - if (r < ARR_SIZE(map)) - return map[r]; - - // cannot find this register - return 0; +sparc_reg Sparc_map_register(unsigned int r) { + static const unsigned int map[] = { + 0, + SPARC_REG_ICC, + SPARC_REG_Y, + SPARC_REG_F0, + SPARC_REG_F2, + SPARC_REG_F4, + SPARC_REG_F6, + SPARC_REG_F8, + SPARC_REG_F10, + SPARC_REG_F12, + SPARC_REG_F14, + SPARC_REG_F16, + SPARC_REG_F18, + SPARC_REG_F20, + SPARC_REG_F22, + SPARC_REG_F24, + SPARC_REG_F26, + SPARC_REG_F28, + SPARC_REG_F30, + SPARC_REG_F32, + SPARC_REG_F34, + SPARC_REG_F36, + SPARC_REG_F38, + SPARC_REG_F40, + SPARC_REG_F42, + SPARC_REG_F44, + SPARC_REG_F46, + SPARC_REG_F48, + SPARC_REG_F50, + SPARC_REG_F52, + SPARC_REG_F54, + SPARC_REG_F56, + SPARC_REG_F58, + SPARC_REG_F60, + SPARC_REG_F62, + SPARC_REG_F0, + SPARC_REG_F1, + SPARC_REG_F2, + SPARC_REG_F3, + SPARC_REG_F4, + SPARC_REG_F5, + SPARC_REG_F6, + SPARC_REG_F7, + SPARC_REG_F8, + SPARC_REG_F9, + SPARC_REG_F10, + SPARC_REG_F11, + SPARC_REG_F12, + SPARC_REG_F13, + SPARC_REG_F14, + SPARC_REG_F15, + SPARC_REG_F16, + SPARC_REG_F17, + SPARC_REG_F18, + SPARC_REG_F19, + SPARC_REG_F20, + SPARC_REG_F21, + SPARC_REG_F22, + SPARC_REG_F23, + SPARC_REG_F24, + SPARC_REG_F25, + SPARC_REG_F26, + SPARC_REG_F27, + SPARC_REG_F28, + SPARC_REG_F29, + SPARC_REG_F30, + SPARC_REG_F31, + SPARC_REG_FCC0, + SPARC_REG_FCC1, + SPARC_REG_FCC2, + SPARC_REG_FCC3, + SPARC_REG_G0, + SPARC_REG_G1, + SPARC_REG_G2, + SPARC_REG_G3, + SPARC_REG_G4, + SPARC_REG_G5, + SPARC_REG_G6, + SPARC_REG_G7, + SPARC_REG_I0, + SPARC_REG_I1, + SPARC_REG_I2, + SPARC_REG_I3, + SPARC_REG_I4, + SPARC_REG_I5, + SPARC_REG_FP, + SPARC_REG_I7, + SPARC_REG_L0, + SPARC_REG_L1, + SPARC_REG_L2, + SPARC_REG_L3, + SPARC_REG_L4, + SPARC_REG_L5, + SPARC_REG_L6, + SPARC_REG_L7, + SPARC_REG_O0, + SPARC_REG_O1, + SPARC_REG_O2, + SPARC_REG_O3, + SPARC_REG_O4, + SPARC_REG_O5, + SPARC_REG_SP, + SPARC_REG_O7, + SPARC_REG_F0, + SPARC_REG_F4, + SPARC_REG_F8, + SPARC_REG_F12, + SPARC_REG_F16, + SPARC_REG_F20, + SPARC_REG_F24, + SPARC_REG_F28, + SPARC_REG_F32, + SPARC_REG_F36, + SPARC_REG_F40, + SPARC_REG_F44, + SPARC_REG_F48, + SPARC_REG_F52, + SPARC_REG_F56, + SPARC_REG_F60, + }; + + if (r < ARR_SIZE(map)) + return map[r]; + + // cannot find this register + return 0; } // map instruction name to instruction ID (public) -sparc_reg Sparc_map_insn(const char *name) -{ - unsigned int i; +sparc_reg Sparc_map_insn(const char *name) { + unsigned int i; - // NOTE: skip first NULL name in insn_name_maps - i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + // NOTE: skip first NULL name in insn_name_maps + i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); - return (i != -1)? i : SPARC_REG_INVALID; + return (i != -1) ? i : SPARC_REG_INVALID; } // NOTE: put strings in the order of string length since // we are going to compare with mnemonic to find out CC static const name_map alias_icc_maps[] = { - { SPARC_CC_ICC_LEU, "leu" }, - { SPARC_CC_ICC_POS, "pos" }, - { SPARC_CC_ICC_NEG, "neg" }, - { SPARC_CC_ICC_NE, "ne" }, - { SPARC_CC_ICC_LE, "le" }, - { SPARC_CC_ICC_GE, "ge" }, - { SPARC_CC_ICC_GU, "gu" }, - { SPARC_CC_ICC_CC, "cc" }, - { SPARC_CC_ICC_CS, "cs" }, - { SPARC_CC_ICC_VC, "vc" }, - { SPARC_CC_ICC_VS, "vs" }, - { SPARC_CC_ICC_A, "a" }, - { SPARC_CC_ICC_N, "n" }, - { SPARC_CC_ICC_E, "e" }, - { SPARC_CC_ICC_G, "g" }, - { SPARC_CC_ICC_L, "l" }, + {SPARC_CC_ICC_LEU, "leu"}, {SPARC_CC_ICC_POS, "pos"}, + {SPARC_CC_ICC_NEG, "neg"}, {SPARC_CC_ICC_NE, "ne"}, + {SPARC_CC_ICC_LE, "le"}, {SPARC_CC_ICC_GE, "ge"}, + {SPARC_CC_ICC_GU, "gu"}, {SPARC_CC_ICC_CC, "cc"}, + {SPARC_CC_ICC_CS, "cs"}, {SPARC_CC_ICC_VC, "vc"}, + {SPARC_CC_ICC_VS, "vs"}, {SPARC_CC_ICC_A, "a"}, + {SPARC_CC_ICC_N, "n"}, {SPARC_CC_ICC_E, "e"}, + {SPARC_CC_ICC_G, "g"}, {SPARC_CC_ICC_L, "l"}, }; static const name_map alias_fcc_maps[] = { - { SPARC_CC_FCC_UGE, "uge" }, - { SPARC_CC_FCC_ULE, "ule" }, - { SPARC_CC_FCC_UG, "ug" }, - { SPARC_CC_FCC_UL, "ul" }, - { SPARC_CC_FCC_LG, "lg" }, - { SPARC_CC_FCC_NE, "ne" }, - { SPARC_CC_FCC_UE, "ue" }, - { SPARC_CC_FCC_GE, "ge" }, - { SPARC_CC_FCC_LE, "le" }, - { SPARC_CC_FCC_A, "a" }, - { SPARC_CC_FCC_N, "n" }, - { SPARC_CC_FCC_U, "u" }, - { SPARC_CC_FCC_G, "g" }, - { SPARC_CC_FCC_L, "l" }, - { SPARC_CC_FCC_E, "e" }, - { SPARC_CC_FCC_O, "o" }, + {SPARC_CC_FCC_UGE, "uge"}, {SPARC_CC_FCC_ULE, "ule"}, + {SPARC_CC_FCC_UG, "ug"}, {SPARC_CC_FCC_UL, "ul"}, + {SPARC_CC_FCC_LG, "lg"}, {SPARC_CC_FCC_NE, "ne"}, + {SPARC_CC_FCC_UE, "ue"}, {SPARC_CC_FCC_GE, "ge"}, + {SPARC_CC_FCC_LE, "le"}, {SPARC_CC_FCC_A, "a"}, + {SPARC_CC_FCC_N, "n"}, {SPARC_CC_FCC_U, "u"}, + {SPARC_CC_FCC_G, "g"}, {SPARC_CC_FCC_L, "l"}, + {SPARC_CC_FCC_E, "e"}, {SPARC_CC_FCC_O, "o"}, }; // map CC string to CC id -sparc_cc Sparc_map_ICC(const char *name) -{ - unsigned int i; +sparc_cc Sparc_map_ICC(const char *name) { + unsigned int i; - i = name2id(alias_icc_maps, ARR_SIZE(alias_icc_maps), name); + i = name2id(alias_icc_maps, ARR_SIZE(alias_icc_maps), name); - return (i != -1)? i : SPARC_CC_INVALID; + return (i != -1) ? i : SPARC_CC_INVALID; } -sparc_cc Sparc_map_FCC(const char *name) -{ - unsigned int i; +sparc_cc Sparc_map_FCC(const char *name) { + unsigned int i; - i = name2id(alias_fcc_maps, ARR_SIZE(alias_fcc_maps), name); + i = name2id(alias_fcc_maps, ARR_SIZE(alias_fcc_maps), name); - return (i != -1)? i : SPARC_CC_INVALID; + return (i != -1) ? i : SPARC_CC_INVALID; } static const name_map hint_maps[] = { - { SPARC_HINT_A, ",a" }, - { SPARC_HINT_A | SPARC_HINT_PN, ",a,pn" }, - { SPARC_HINT_PN, ",pn" }, + {SPARC_HINT_A, ",a"}, + {SPARC_HINT_A | SPARC_HINT_PN, ",a,pn"}, + {SPARC_HINT_PN, ",pn"}, }; -sparc_hint Sparc_map_hint(const char *name) -{ - size_t i, l1, l2; - - l1 = strlen(name); - for(i = 0; i < ARR_SIZE(hint_maps); i++) { - l2 = strlen(hint_maps[i].name); - if (l1 > l2) { - // compare the last part of @name with this hint string - if (!strcmp(hint_maps[i].name, name + (l1 - l2))) - return hint_maps[i].id; - } - } - - return SPARC_HINT_INVALID; +sparc_hint Sparc_map_hint(const char *name) { + size_t i, l1, l2; + + l1 = strlen(name); + for (i = 0; i < ARR_SIZE(hint_maps); i++) { + l2 = strlen(hint_maps[i].name); + if (l1 > l2) { + // compare the last part of @name with this hint string + if (!strcmp(hint_maps[i].name, name + (l1 - l2))) + return hint_maps[i].id; + } + } + + return SPARC_HINT_INVALID; } #endif diff --git a/arch/Sparc/SparcMapping.h b/arch/Sparc/SparcMapping.h index 1c8c1b19d6..c7baa5aff7 100644 --- a/arch/Sparc/SparcMapping.h +++ b/arch/Sparc/SparcMapping.h @@ -31,4 +31,3 @@ sparc_cc Sparc_map_FCC(const char *name); sparc_hint Sparc_map_hint(const char *name); #endif - diff --git a/arch/Sparc/SparcMappingInsn.inc b/arch/Sparc/SparcMappingInsn.inc index 6c97afc79d..2f7fe85b0c 100644 --- a/arch/Sparc/SparcMappingInsn.inc +++ b/arch/Sparc/SparcMappingInsn.inc @@ -1,2643 +1,3848 @@ // This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh -{ - SP_ADDCCri, SPARC_INS_ADDCC, +{SP_ADDCCri, SPARC_INS_ADDCC, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif }, -{ - SP_ADDCCrr, SPARC_INS_ADDCC, + {SP_ADDCCrr, SPARC_INS_ADDCC, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_ADDCri, SPARC_INS_ADDX, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ADDCrr, SPARC_INS_ADDX, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ADDEri, SPARC_INS_ADDXCC, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ADDErr, SPARC_INS_ADDXCC, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ADDXC, SPARC_INS_ADDXC, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_ADDXCCC, SPARC_INS_ADDXCCC, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_ADDXri, SPARC_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_ADDXrr, SPARC_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_ADDri, SPARC_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ADDrr, SPARC_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ALIGNADDR, SPARC_INS_ALIGNADDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_ALIGNADDRL, SPARC_INS_ALIGNADDRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_ANDCCri, SPARC_INS_ANDCC, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ANDCCrr, SPARC_INS_ANDCC, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ANDNCCri, SPARC_INS_ANDNCC, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ANDNCCrr, SPARC_INS_ANDNCC, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ANDNri, SPARC_INS_ANDN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ANDNrr, SPARC_INS_ANDN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ANDXNrr, SPARC_INS_ANDN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_ANDXri, SPARC_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_ANDXrr, SPARC_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_ANDri, SPARC_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ANDrr, SPARC_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ARRAY16, SPARC_INS_ARRAY16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_ARRAY32, SPARC_INS_ARRAY32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_ARRAY8, SPARC_INS_ARRAY8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_BA, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SP_BCOND, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SP_BCONDA, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SP_BINDri, SPARC_INS_JMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SP_BINDrr, SPARC_INS_JMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SP_BMASK, SPARC_INS_BMASK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 -#endif -}, -{ - SP_BPFCC, SPARC_INS_FB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 -#endif -}, -{ - SP_BPFCCA, SPARC_INS_FB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 -#endif -}, -{ - SP_BPFCCANT, SPARC_INS_FB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 -#endif -}, -{ - SP_BPFCCNT, SPARC_INS_FB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 -#endif -}, -{ - SP_BPGEZapn, SPARC_INS_BRGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPGEZapt, SPARC_INS_BRGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPGEZnapn, SPARC_INS_BRGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPGEZnapt, SPARC_INS_BRGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPGZapn, SPARC_INS_BRGZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPGZapt, SPARC_INS_BRGZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPGZnapn, SPARC_INS_BRGZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPGZnapt, SPARC_INS_BRGZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPICC, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 -#endif -}, -{ - SP_BPICCA, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 -#endif -}, -{ - SP_BPICCANT, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 -#endif -}, -{ - SP_BPICCNT, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 -#endif -}, -{ - SP_BPLEZapn, SPARC_INS_BRLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPLEZapt, SPARC_INS_BRLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPLEZnapn, SPARC_INS_BRLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPLEZnapt, SPARC_INS_BRLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPLZapn, SPARC_INS_BRLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPLZapt, SPARC_INS_BRLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPLZnapn, SPARC_INS_BRLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPLZnapt, SPARC_INS_BRLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPNZapn, SPARC_INS_BRNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPNZapt, SPARC_INS_BRNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPNZnapn, SPARC_INS_BRNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPNZnapt, SPARC_INS_BRNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPXCC, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPXCCA, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPXCCANT, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPXCCNT, SPARC_INS_B, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPZapn, SPARC_INS_BRZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPZapt, SPARC_INS_BRZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPZnapn, SPARC_INS_BRZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BPZnapt, SPARC_INS_BRZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 -#endif -}, -{ - SP_BSHUFFLE, SPARC_INS_BSHUFFLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 -#endif -}, -{ - SP_CALL, SPARC_INS_CALL, -#ifndef CAPSTONE_DIET - { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_CALLri, SPARC_INS_CALL, -#ifndef CAPSTONE_DIET - { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_CALLrr, SPARC_INS_CALL, -#ifndef CAPSTONE_DIET - { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_CASXrr, SPARC_INS_CASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_CASrr, SPARC_INS_CAS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_CMASK16, SPARC_INS_CMASK16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_CMASK32, SPARC_INS_CMASK32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_CMASK8, SPARC_INS_CMASK8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_CMPri, SPARC_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_CMPrr, SPARC_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_EDGE16, SPARC_INS_EDGE16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE16L, SPARC_INS_EDGE16L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE16LN, SPARC_INS_EDGE16LN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE16N, SPARC_INS_EDGE16N, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE32, SPARC_INS_EDGE32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE32L, SPARC_INS_EDGE32L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE32LN, SPARC_INS_EDGE32LN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE32N, SPARC_INS_EDGE32N, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE8, SPARC_INS_EDGE8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE8L, SPARC_INS_EDGE8L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE8LN, SPARC_INS_EDGE8LN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 -#endif -}, -{ - SP_EDGE8N, SPARC_INS_EDGE8N, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 -#endif -}, -{ - SP_FABSD, SPARC_INS_FABSD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FABSQ, SPARC_INS_FABSQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FABSS, SPARC_INS_FABSS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FADDD, SPARC_INS_FADDD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FADDQ, SPARC_INS_FADDQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FADDS, SPARC_INS_FADDS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FALIGNADATA, SPARC_INS_FALIGNDATA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FAND, SPARC_INS_FAND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FANDNOT1, SPARC_INS_FANDNOT1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FANDNOT1S, SPARC_INS_FANDNOT1S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FANDNOT2, SPARC_INS_FANDNOT2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FANDNOT2S, SPARC_INS_FANDNOT2S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FANDS, SPARC_INS_FANDS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FBCOND, SPARC_INS_FB, -#ifndef CAPSTONE_DIET - { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SP_FBCONDA, SPARC_INS_FB, -#ifndef CAPSTONE_DIET - { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SP_FCHKSM16, SPARC_INS_FCHKSM16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPD, SPARC_INS_FCMPD, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FCMPEQ16, SPARC_INS_FCMPEQ16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPEQ32, SPARC_INS_FCMPEQ32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPGT16, SPARC_INS_FCMPGT16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPGT32, SPARC_INS_FCMPGT32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPLE16, SPARC_INS_FCMPLE16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPLE32, SPARC_INS_FCMPLE32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPNE16, SPARC_INS_FCMPNE16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPNE32, SPARC_INS_FCMPNE32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPQ, SPARC_INS_FCMPQ, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_FCC0, 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FCMPS, SPARC_INS_FCMPS, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FDIVD, SPARC_INS_FDIVD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FDIVQ, SPARC_INS_FDIVQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FDIVS, SPARC_INS_FDIVS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FDMULQ, SPARC_INS_FDMULQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FDTOI, SPARC_INS_FDTOI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FDTOQ, SPARC_INS_FDTOQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FDTOS, SPARC_INS_FDTOS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FDTOX, SPARC_INS_FDTOX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_FEXPAND, SPARC_INS_FEXPAND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FHADDD, SPARC_INS_FHADDD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FHADDS, SPARC_INS_FHADDS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FHSUBD, SPARC_INS_FHSUBD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FHSUBS, SPARC_INS_FHSUBS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FITOD, SPARC_INS_FITOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FITOQ, SPARC_INS_FITOQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FITOS, SPARC_INS_FITOS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FLCMPD, SPARC_INS_FLCMPD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FLCMPS, SPARC_INS_FLCMPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FLUSHW, SPARC_INS_FLUSHW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMEAN16, SPARC_INS_FMEAN16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVD, SPARC_INS_FMOVD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVD_FCC, SPARC_INS_FMOVD, -#ifndef CAPSTONE_DIET - { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVD_ICC, SPARC_INS_FMOVD, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVD_XCC, SPARC_INS_FMOVD, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVQ, SPARC_INS_FMOVQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVQ_FCC, SPARC_INS_FMOVQ, -#ifndef CAPSTONE_DIET - { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVQ_ICC, SPARC_INS_FMOVQ, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVQ_XCC, SPARC_INS_FMOVQ, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRGEZD, SPARC_INS_FMOVRDGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRGEZQ, SPARC_INS_FMOVRQGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRGEZS, SPARC_INS_FMOVRSGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRGZD, SPARC_INS_FMOVRDGZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRGZQ, SPARC_INS_FMOVRQGZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRGZS, SPARC_INS_FMOVRSGZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRLEZD, SPARC_INS_FMOVRDLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRLEZQ, SPARC_INS_FMOVRQLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRLEZS, SPARC_INS_FMOVRSLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRLZD, SPARC_INS_FMOVRDLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRLZQ, SPARC_INS_FMOVRQLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRLZS, SPARC_INS_FMOVRSLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRNZD, SPARC_INS_FMOVRDNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRNZQ, SPARC_INS_FMOVRQNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRNZS, SPARC_INS_FMOVRSNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRZD, SPARC_INS_FMOVRDZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRZQ, SPARC_INS_FMOVRQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVRZS, SPARC_INS_FMOVRSZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVS, SPARC_INS_FMOVS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FMOVS_FCC, SPARC_INS_FMOVS, -#ifndef CAPSTONE_DIET - { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVS_ICC, SPARC_INS_FMOVS, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FMOVS_XCC, SPARC_INS_FMOVS, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_FMUL8SUX16, SPARC_INS_FMUL8SUX16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FMUL8ULX16, SPARC_INS_FMUL8ULX16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FMUL8X16, SPARC_INS_FMUL8X16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FMUL8X16AL, SPARC_INS_FMUL8X16AL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FMUL8X16AU, SPARC_INS_FMUL8X16AU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FMULD, SPARC_INS_FMULD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FMULD8SUX16, SPARC_INS_FMULD8SUX16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FMULD8ULX16, SPARC_INS_FMULD8ULX16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FMULQ, SPARC_INS_FMULQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FMULS, SPARC_INS_FMULS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FNADDD, SPARC_INS_FNADDD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FNADDS, SPARC_INS_FNADDS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FNAND, SPARC_INS_FNAND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FNANDS, SPARC_INS_FNANDS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FNEGD, SPARC_INS_FNEGD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FNEGQ, SPARC_INS_FNEGQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_FNEGS, SPARC_INS_FNEGS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FNHADDD, SPARC_INS_FNHADDD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FNHADDS, SPARC_INS_FNHADDS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FNMULD, SPARC_INS_FNHADDD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FNMULS, SPARC_INS_FNHADDS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FNOR, SPARC_INS_FNOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FNORS, SPARC_INS_FNORS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FNOT1, SPARC_INS_FNOT1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FNOT1S, SPARC_INS_FNOT1S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FNOT2, SPARC_INS_FNOT2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FNOT2S, SPARC_INS_FNOT2S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FNSMULD, SPARC_INS_FNHADDS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FONE, SPARC_INS_FONE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FONES, SPARC_INS_FONES, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FOR, SPARC_INS_FOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FORNOT1, SPARC_INS_FORNOT1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FORNOT1S, SPARC_INS_FORNOT1S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FORNOT2, SPARC_INS_FORNOT2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FORNOT2S, SPARC_INS_FORNOT2S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FORS, SPARC_INS_FORS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPACK16, SPARC_INS_FPACK16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPACK32, SPARC_INS_FPACK32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPACKFIX, SPARC_INS_FPACKFIX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPADD16, SPARC_INS_FPADD16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPADD16S, SPARC_INS_FPADD16S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPADD32, SPARC_INS_FPADD32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPADD32S, SPARC_INS_FPADD32S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPADD64, SPARC_INS_FPADD64, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FPMERGE, SPARC_INS_FPMERGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPSUB16, SPARC_INS_FPSUB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPSUB16S, SPARC_INS_FPSUB16S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPSUB32, SPARC_INS_FPSUB32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FPSUB32S, SPARC_INS_FPSUB32S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FQTOD, SPARC_INS_FQTOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FQTOI, SPARC_INS_FQTOI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FQTOS, SPARC_INS_FQTOS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FQTOX, SPARC_INS_FQTOX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_FSLAS16, SPARC_INS_FSLAS16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FSLAS32, SPARC_INS_FSLAS32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FSLL16, SPARC_INS_FSLL16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FSLL32, SPARC_INS_FSLL32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FSMULD, SPARC_INS_FSMULD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FSQRTD, SPARC_INS_FSQRTD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FSQRTQ, SPARC_INS_FSQRTQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FSQRTS, SPARC_INS_FSQRTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FSRA16, SPARC_INS_FSRA16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FSRA32, SPARC_INS_FSRA32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FSRC1, SPARC_INS_FSRC1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FSRC1S, SPARC_INS_FSRC1S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FSRC2, SPARC_INS_FSRC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FSRC2S, SPARC_INS_FSRC2S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FSRL16, SPARC_INS_FSRL16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FSRL32, SPARC_INS_FSRL32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_FSTOD, SPARC_INS_FSTOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FSTOI, SPARC_INS_FSTOI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FSTOQ, SPARC_INS_FSTOQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FSTOX, SPARC_INS_FSTOX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_FSUBD, SPARC_INS_FSUBD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FSUBQ, SPARC_INS_FSUBQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_FSUBS, SPARC_INS_FSUBS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_FXNOR, SPARC_INS_FXNOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FXNORS, SPARC_INS_FXNORS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FXOR, SPARC_INS_FXOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FXORS, SPARC_INS_FXORS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FXTOD, SPARC_INS_FXTOD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_FXTOQ, SPARC_INS_FXTOQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_FXTOS, SPARC_INS_FXTOS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_FZERO, SPARC_INS_FZERO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_FZEROS, SPARC_INS_FZEROS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_JMPLri, SPARC_INS_JMPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_JMPLrr, SPARC_INS_JMPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDDFri, SPARC_INS_LDD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDDFrr, SPARC_INS_LDD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDFri, SPARC_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDFrr, SPARC_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDQFri, SPARC_INS_LDQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_LDQFrr, SPARC_INS_LDQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 -#endif -}, -{ - SP_LDSBri, SPARC_INS_LDSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDSBrr, SPARC_INS_LDSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDSHri, SPARC_INS_LDSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDSHrr, SPARC_INS_LDSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDSWri, SPARC_INS_LDSW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_LDSWrr, SPARC_INS_LDSW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_LDUBri, SPARC_INS_LDUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDUBrr, SPARC_INS_LDUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDUHri, SPARC_INS_LDUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDUHrr, SPARC_INS_LDUH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDXri, SPARC_INS_LDX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_LDXrr, SPARC_INS_LDX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_LDri, SPARC_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_LDrr, SPARC_INS_LD, + }, + {SP_ADDCri, + SPARC_INS_ADDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {0}, + {0}, + 0, + 0 #endif -}, -{ - SP_LEAX_ADDri, SPARC_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_LEA_ADDri, SPARC_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_32BIT, 0 }, 0, 0 -#endif -}, -{ - SP_LZCNT, SPARC_INS_LZCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_MEMBARi, SPARC_INS_MEMBAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_MOVDTOX, SPARC_INS_MOVDTOX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_MOVFCCri, SPARC_INS_MOV, -#ifndef CAPSTONE_DIET - { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_MOVFCCrr, SPARC_INS_MOV, -#ifndef CAPSTONE_DIET - { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_MOVICCri, SPARC_INS_MOV, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_MOVICCrr, SPARC_INS_MOV, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRGEZri, SPARC_INS_MOVRGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRGEZrr, SPARC_INS_MOVRGEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRGZri, SPARC_INS_MOVRGZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRGZrr, SPARC_INS_MOVRGZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRLEZri, SPARC_INS_MOVRLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRLEZrr, SPARC_INS_MOVRLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRLZri, SPARC_INS_MOVRLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRLZrr, SPARC_INS_MOVRLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRNZri, SPARC_INS_MOVRNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRNZrr, SPARC_INS_MOVRNZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRRZri, SPARC_INS_MOVRZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVRRZrr, SPARC_INS_MOVRZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVSTOSW, SPARC_INS_MOVSTOSW, + }, + {SP_ADDCrr, + SPARC_INS_ADDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {0}, + {0}, + 0, + 0 #endif -}, -{ - SP_MOVSTOUW, SPARC_INS_MOVSTOUW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_MOVWTOS, SPARC_INS_MOVDTOX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_MOVXCCri, SPARC_INS_MOV, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVXCCrr, SPARC_INS_MOV, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MOVXTOD, SPARC_INS_MOVDTOX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 -#endif -}, -{ - SP_MULXri, SPARC_INS_MULX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_MULXrr, SPARC_INS_MULX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_NOP, SPARC_INS_NOP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ORCCri, SPARC_INS_ORCC, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ORCCrr, SPARC_INS_ORCC, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ORNCCri, SPARC_INS_ORNCC, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ORNCCrr, SPARC_INS_ORNCC, -#ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ORNri, SPARC_INS_ORN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ORNrr, SPARC_INS_ORN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ORXNrr, SPARC_INS_ORN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_ORXri, SPARC_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_ORXrr, SPARC_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_ORri, SPARC_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_ORrr, SPARC_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_PDIST, SPARC_INS_PDIST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 -#endif -}, -{ - SP_PDISTN, SPARC_INS_PDISTN, + }, + {SP_ADDEri, + SPARC_INS_ADDXCC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 #endif -}, -{ - SP_POPCrr, SPARC_INS_POPC, + }, + {SP_ADDErr, + SPARC_INS_ADDXCC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 #endif -}, -{ - SP_RDY, SPARC_INS_RD, + }, + {SP_ADDXC, + SPARC_INS_ADDXC, #ifndef CAPSTONE_DIET - { SPARC_REG_Y, 0 }, { 0 }, { 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 #endif -}, -{ - SP_RESTOREri, SPARC_INS_RESTORE, + }, + {SP_ADDXCCC, + SPARC_INS_ADDXCCC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {SPARC_REG_ICC, 0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 #endif -}, -{ - SP_RESTORErr, SPARC_INS_RESTORE, + }, + {SP_ADDXri, SPARC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_RET, SPARC_INS_JMP, + }, + {SP_ADDXrr, SPARC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_RETL, SPARC_INS_JMP, + }, + {SP_ADDri, SPARC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_RETTri, SPARC_INS_RETT, + }, + {SP_ADDrr, SPARC_INS_ADD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_RETTrr, SPARC_INS_RETT, + }, + {SP_ALIGNADDR, + SPARC_INS_ALIGNADDR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 #endif -}, -{ - SP_SAVEri, SPARC_INS_SAVE, + }, + {SP_ALIGNADDRL, + SPARC_INS_ALIGNADDRL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 #endif -}, -{ - SP_SAVErr, SPARC_INS_SAVE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + }, + {SP_ANDCCri, SPARC_INS_ANDCC, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_SDIVCCri, SPARC_INS_SDIVCC, + }, + {SP_ANDCCrr, SPARC_INS_ANDCC, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 +#endif + }, + {SP_ANDNCCri, + SPARC_INS_ANDNCC, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 #endif -}, -{ - SP_SDIVCCrr, SPARC_INS_SDIVCC, + }, + {SP_ANDNCCrr, + SPARC_INS_ANDNCC, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 #endif -}, -{ - SP_SDIVXri, SPARC_INS_SDIVX, + }, + {SP_ANDNri, SPARC_INS_ANDN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_SDIVXrr, SPARC_INS_SDIVX, + }, + {SP_ANDNrr, SPARC_INS_ANDN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_SDIVri, SPARC_INS_SDIV, + }, + {SP_ANDXNrr, + SPARC_INS_ANDN, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_SDIVrr, SPARC_INS_SDIV, + }, + {SP_ANDXri, SPARC_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_SETHIXi, SPARC_INS_SETHI, + }, + {SP_ANDXrr, SPARC_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_SETHIi, SPARC_INS_SETHI, + }, + {SP_ANDri, SPARC_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_SHUTDOWN, SPARC_INS_SHUTDOWN, + }, + {SP_ANDrr, SPARC_INS_AND, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_SIAM, SPARC_INS_SIAM, + }, + {SP_ARRAY16, + SPARC_INS_ARRAY16, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 #endif -}, -{ - SP_SLLXri, SPARC_INS_SLLX, + }, + {SP_ARRAY32, + SPARC_INS_ARRAY32, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 #endif -}, -{ - SP_SLLXrr, SPARC_INS_SLLX, + }, + {SP_ARRAY8, + SPARC_INS_ARRAY8, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 #endif -}, -{ - SP_SLLri, SPARC_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + }, + {SP_BA, SPARC_INS_B, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 1, + 0 #endif -}, -{ - SP_SLLrr, SPARC_INS_SLL, + }, + {SP_BCOND, + SPARC_INS_B, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {0}, + {0}, + 1, + 0 #endif -}, -{ - SP_SMULCCri, SPARC_INS_SMULCC, + }, + {SP_BCONDA, + SPARC_INS_B, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_SMULCCrr, SPARC_INS_SMULCC, + {SPARC_REG_ICC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SP_BINDri, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 1, + 1 +#endif + }, + {SP_BINDrr, SPARC_INS_JMP, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 1, + 1 +#endif + }, + {SP_BMASK, + SPARC_INS_BMASK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS2, 0}, + 0, + 0 +#endif + }, + {SP_BPFCC, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + {0}, {0}, {SPARC_GRP_V9, 0}, 1, + 0 +#endif + }, + {SP_BPFCCA, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + {0}, {0}, {SPARC_GRP_V9, 0}, 1, + 0 +#endif + }, + {SP_BPFCCANT, + SPARC_INS_FB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 1, + 0 +#endif + }, + {SP_BPFCCNT, SPARC_INS_FB, +#ifndef CAPSTONE_DIET + {0}, {0}, {SPARC_GRP_V9, 0}, 1, + 0 +#endif + }, + {SP_BPGEZapn, + SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPGEZapt, + SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPGEZnapn, + SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPGEZnapt, + SPARC_INS_BRGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPGZapn, + SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPGZapt, + SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPGZnapn, + SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPGZnapt, + SPARC_INS_BRGZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPICC, + SPARC_INS_B, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 1, + 0 +#endif + }, + {SP_BPICCA, + SPARC_INS_B, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 1, + 0 +#endif + }, + {SP_BPICCANT, + SPARC_INS_B, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 1, + 0 +#endif + }, + {SP_BPICCNT, + SPARC_INS_B, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 1, + 0 +#endif + }, + {SP_BPLEZapn, + SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPLEZapt, + SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPLEZnapn, + SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPLEZnapt, + SPARC_INS_BRLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPLZapn, + SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPLZapt, + SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPLZnapn, + SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPLZnapt, + SPARC_INS_BRLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPNZapn, + SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPNZapt, + SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPNZnapn, + SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPNZnapt, + SPARC_INS_BRNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPXCC, + SPARC_INS_B, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPXCCA, + SPARC_INS_B, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPXCCANT, + SPARC_INS_B, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPXCCNT, + SPARC_INS_B, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 1, + 0 +#endif + }, + {SP_BPZapn, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + {0}, {0}, {SPARC_GRP_64BIT, 0}, 1, + 0 +#endif + }, + {SP_BPZapt, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + {0}, {0}, {SPARC_GRP_64BIT, 0}, 1, + 0 +#endif + }, + {SP_BPZnapn, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + {0}, {0}, {SPARC_GRP_64BIT, 0}, 1, + 0 +#endif + }, + {SP_BPZnapt, SPARC_INS_BRZ, +#ifndef CAPSTONE_DIET + {0}, {0}, {SPARC_GRP_64BIT, 0}, 1, + 0 +#endif + }, + {SP_BSHUFFLE, + SPARC_INS_BSHUFFLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS2, 0}, + 0, + 0 +#endif + }, + {SP_CALL, + SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + {SPARC_REG_O6, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_CALLri, + SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + {SPARC_REG_O6, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_CALLrr, + SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + {SPARC_REG_O6, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_CASXrr, + SPARC_INS_CASX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_CASrr, SPARC_INS_CAS, +#ifndef CAPSTONE_DIET + {0}, {0}, {SPARC_GRP_V9, 0}, 0, + 0 +#endif + }, + {SP_CMASK16, + SPARC_INS_CMASK16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_CMASK32, + SPARC_INS_CMASK32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_CMASK8, + SPARC_INS_CMASK8, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_CMPri, SPARC_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 +#endif + }, + {SP_CMPrr, SPARC_INS_CMP, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 +#endif + }, + {SP_EDGE16, + SPARC_INS_EDGE16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_EDGE16L, + SPARC_INS_EDGE16L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_EDGE16LN, + SPARC_INS_EDGE16LN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS2, 0}, + 0, + 0 +#endif + }, + {SP_EDGE16N, + SPARC_INS_EDGE16N, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS2, 0}, + 0, + 0 +#endif + }, + {SP_EDGE32, + SPARC_INS_EDGE32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_EDGE32L, + SPARC_INS_EDGE32L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_EDGE32LN, + SPARC_INS_EDGE32LN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS2, 0}, + 0, + 0 +#endif + }, + {SP_EDGE32N, + SPARC_INS_EDGE32N, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS2, 0}, + 0, + 0 +#endif + }, + {SP_EDGE8, + SPARC_INS_EDGE8, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_EDGE8L, + SPARC_INS_EDGE8L, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_EDGE8LN, + SPARC_INS_EDGE8LN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS2, 0}, + 0, + 0 +#endif + }, + {SP_EDGE8N, + SPARC_INS_EDGE8N, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS2, 0}, + 0, + 0 +#endif + }, + {SP_FABSD, + SPARC_INS_FABSD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FABSQ, + SPARC_INS_FABSQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FABSS, SPARC_INS_FABSS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FADDD, SPARC_INS_FADDD, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FADDQ, + SPARC_INS_FADDQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FADDS, SPARC_INS_FADDS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FALIGNADATA, + SPARC_INS_FALIGNDATA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FAND, + SPARC_INS_FAND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FANDNOT1, + SPARC_INS_FANDNOT1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FANDNOT1S, + SPARC_INS_FANDNOT1S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FANDNOT2, + SPARC_INS_FANDNOT2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FANDNOT2S, + SPARC_INS_FANDNOT2S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FANDS, + SPARC_INS_FANDS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FBCOND, + SPARC_INS_FB, +#ifndef CAPSTONE_DIET + {SPARC_REG_FCC0, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SP_FBCONDA, + SPARC_INS_FB, +#ifndef CAPSTONE_DIET + {SPARC_REG_FCC0, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SP_FCHKSM16, + SPARC_INS_FCHKSM16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FCMPD, SPARC_INS_FCMPD, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_FCC0, 0}, {0}, 0, + 0 +#endif + }, + {SP_FCMPEQ16, + SPARC_INS_FCMPEQ16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FCMPEQ32, + SPARC_INS_FCMPEQ32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FCMPGT16, + SPARC_INS_FCMPGT16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FCMPGT32, + SPARC_INS_FCMPGT32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FCMPLE16, + SPARC_INS_FCMPLE16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FCMPLE32, + SPARC_INS_FCMPLE32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FCMPNE16, + SPARC_INS_FCMPNE16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FCMPNE32, + SPARC_INS_FCMPNE32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FCMPQ, SPARC_INS_FCMPQ, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_FCC0, 0}, {SPARC_GRP_HARDQUAD, 0}, 0, + 0 +#endif + }, + {SP_FCMPS, SPARC_INS_FCMPS, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_FCC0, 0}, {0}, 0, + 0 +#endif + }, + {SP_FDIVD, SPARC_INS_FDIVD, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FDIVQ, + SPARC_INS_FDIVQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FDIVS, SPARC_INS_FDIVS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FDMULQ, + SPARC_INS_FDMULQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FDTOI, SPARC_INS_FDTOI, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FDTOQ, + SPARC_INS_FDTOQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FDTOS, SPARC_INS_FDTOS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FDTOX, + SPARC_INS_FDTOX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_FEXPAND, + SPARC_INS_FEXPAND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FHADDD, + SPARC_INS_FHADDD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FHADDS, + SPARC_INS_FHADDS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FHSUBD, + SPARC_INS_FHSUBD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FHSUBS, + SPARC_INS_FHSUBS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FITOD, SPARC_INS_FITOD, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FITOQ, + SPARC_INS_FITOQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FITOS, SPARC_INS_FITOS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FLCMPD, + SPARC_INS_FLCMPD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FLCMPS, + SPARC_INS_FLCMPS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FLUSHW, + SPARC_INS_FLUSHW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMEAN16, + SPARC_INS_FMEAN16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FMOVD, + SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVD_FCC, + SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + {SPARC_REG_FCC0, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVD_ICC, + SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVD_XCC, + SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_FMOVQ, + SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVQ_FCC, + SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + {SPARC_REG_FCC0, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVQ_ICC, + SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVQ_XCC, + SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRGEZD, + SPARC_INS_FMOVRDGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRGEZQ, + SPARC_INS_FMOVRQGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRGEZS, + SPARC_INS_FMOVRSGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRGZD, + SPARC_INS_FMOVRDGZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRGZQ, + SPARC_INS_FMOVRQGZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRGZS, + SPARC_INS_FMOVRSGZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRLEZD, + SPARC_INS_FMOVRDLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRLEZQ, + SPARC_INS_FMOVRQLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRLEZS, + SPARC_INS_FMOVRSLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRLZD, + SPARC_INS_FMOVRDLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRLZQ, + SPARC_INS_FMOVRQLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRLZS, + SPARC_INS_FMOVRSLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRNZD, + SPARC_INS_FMOVRDNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRNZQ, + SPARC_INS_FMOVRQNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRNZS, + SPARC_INS_FMOVRSNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRZD, + SPARC_INS_FMOVRDZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRZQ, + SPARC_INS_FMOVRQZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVRZS, + SPARC_INS_FMOVRSZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVS, SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FMOVS_FCC, + SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + {SPARC_REG_FCC0, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVS_ICC, + SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FMOVS_XCC, + SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_FMUL8SUX16, + SPARC_INS_FMUL8SUX16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FMUL8ULX16, + SPARC_INS_FMUL8ULX16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FMUL8X16, + SPARC_INS_FMUL8X16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FMUL8X16AL, + SPARC_INS_FMUL8X16AL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FMUL8X16AU, + SPARC_INS_FMUL8X16AU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FMULD, SPARC_INS_FMULD, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FMULD8SUX16, + SPARC_INS_FMULD8SUX16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FMULD8ULX16, + SPARC_INS_FMULD8ULX16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FMULQ, + SPARC_INS_FMULQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FMULS, SPARC_INS_FMULS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FNADDD, + SPARC_INS_FNADDD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FNADDS, + SPARC_INS_FNADDS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FNAND, + SPARC_INS_FNAND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FNANDS, + SPARC_INS_FNANDS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FNEGD, + SPARC_INS_FNEGD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FNEGQ, + SPARC_INS_FNEGQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_FNEGS, SPARC_INS_FNEGS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FNHADDD, + SPARC_INS_FNHADDD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FNHADDS, + SPARC_INS_FNHADDS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FNMULD, + SPARC_INS_FNHADDD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FNMULS, + SPARC_INS_FNHADDS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FNOR, + SPARC_INS_FNOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FNORS, + SPARC_INS_FNORS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FNOT1, + SPARC_INS_FNOT1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FNOT1S, + SPARC_INS_FNOT1S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FNOT2, + SPARC_INS_FNOT2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FNOT2S, + SPARC_INS_FNOT2S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FNSMULD, + SPARC_INS_FNHADDS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FONE, + SPARC_INS_FONE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FONES, + SPARC_INS_FONES, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FOR, SPARC_INS_FOR, +#ifndef CAPSTONE_DIET + {0}, {0}, {SPARC_GRP_VIS, 0}, 0, + 0 +#endif + }, + {SP_FORNOT1, + SPARC_INS_FORNOT1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FORNOT1S, + SPARC_INS_FORNOT1S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FORNOT2, + SPARC_INS_FORNOT2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FORNOT2S, + SPARC_INS_FORNOT2S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FORS, + SPARC_INS_FORS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPACK16, + SPARC_INS_FPACK16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPACK32, + SPARC_INS_FPACK32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPACKFIX, + SPARC_INS_FPACKFIX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPADD16, + SPARC_INS_FPADD16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPADD16S, + SPARC_INS_FPADD16S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPADD32, + SPARC_INS_FPADD32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPADD32S, + SPARC_INS_FPADD32S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPADD64, + SPARC_INS_FPADD64, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FPMERGE, + SPARC_INS_FPMERGE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPSUB16, + SPARC_INS_FPSUB16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPSUB16S, + SPARC_INS_FPSUB16S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPSUB32, + SPARC_INS_FPSUB32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FPSUB32S, + SPARC_INS_FPSUB32S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FQTOD, + SPARC_INS_FQTOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FQTOI, + SPARC_INS_FQTOI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FQTOS, + SPARC_INS_FQTOS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FQTOX, + SPARC_INS_FQTOX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_FSLAS16, + SPARC_INS_FSLAS16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FSLAS32, + SPARC_INS_FSLAS32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FSLL16, + SPARC_INS_FSLL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FSLL32, + SPARC_INS_FSLL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FSMULD, SPARC_INS_FSMULD, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FSQRTD, SPARC_INS_FSQRTD, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FSQRTQ, + SPARC_INS_FSQRTQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FSQRTS, SPARC_INS_FSQRTS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FSRA16, + SPARC_INS_FSRA16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FSRA32, + SPARC_INS_FSRA32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FSRC1, + SPARC_INS_FSRC1, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FSRC1S, + SPARC_INS_FSRC1S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FSRC2, + SPARC_INS_FSRC2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FSRC2S, + SPARC_INS_FSRC2S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FSRL16, + SPARC_INS_FSRL16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FSRL32, + SPARC_INS_FSRL32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_FSTOD, SPARC_INS_FSTOD, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FSTOI, SPARC_INS_FSTOI, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FSTOQ, + SPARC_INS_FSTOQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FSTOX, + SPARC_INS_FSTOX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_FSUBD, SPARC_INS_FSUBD, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FSUBQ, + SPARC_INS_FSUBQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_FSUBS, SPARC_INS_FSUBS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_FXNOR, + SPARC_INS_FXNOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FXNORS, + SPARC_INS_FXNORS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FXOR, + SPARC_INS_FXOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FXORS, + SPARC_INS_FXORS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FXTOD, + SPARC_INS_FXTOD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_FXTOQ, + SPARC_INS_FXTOQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_FXTOS, + SPARC_INS_FXTOS, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_SMULri, SPARC_INS_SMUL, + }, + {SP_FZERO, + SPARC_INS_FZERO, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_SMULrr, SPARC_INS_SMUL, + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_FZEROS, + SPARC_INS_FZEROS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_JMPLri, SPARC_INS_JMPL, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_SRAXri, SPARC_INS_SRAX, + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_JMPLrr, SPARC_INS_JMPL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_SRAXrr, SPARC_INS_SRAX, + }, + {SP_LDDFri, SPARC_INS_LDD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_SRAri, SPARC_INS_SRA, + }, + {SP_LDDFrr, SPARC_INS_LDD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_SRArr, SPARC_INS_SRA, + }, + {SP_LDFri, SPARC_INS_LD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_SRLXri, SPARC_INS_SRLX, + }, + {SP_LDFrr, SPARC_INS_LD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_SRLXrr, SPARC_INS_SRLX, + }, + {SP_LDQFri, SPARC_INS_LDQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0}, 0, + 0 #endif -}, -{ - SP_SRLri, SPARC_INS_SRL, + }, + {SP_LDQFrr, SPARC_INS_LDQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0}, 0, + 0 #endif -}, -{ - SP_SRLrr, SPARC_INS_SRL, + }, + {SP_LDSBri, SPARC_INS_LDSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_STBAR, SPARC_INS_STBAR, + }, + {SP_LDSBrr, SPARC_INS_LDSB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_STBri, SPARC_INS_STB, + }, + {SP_LDSHri, SPARC_INS_LDSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_STBrr, SPARC_INS_STB, + }, + {SP_LDSHrr, SPARC_INS_LDSH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_STDFri, SPARC_INS_STD, + }, + {SP_LDSWri, + SPARC_INS_LDSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_STDFrr, SPARC_INS_STD, + }, + {SP_LDSWrr, + SPARC_INS_LDSW, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_STFri, SPARC_INS_ST, + }, + {SP_LDUBri, SPARC_INS_LDUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_STFrr, SPARC_INS_ST, + }, + {SP_LDUBrr, SPARC_INS_LDUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_STHri, SPARC_INS_STH, + }, + {SP_LDUHri, SPARC_INS_LDUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_STHrr, SPARC_INS_STH, + }, + {SP_LDUHrr, SPARC_INS_LDUH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_STQFri, SPARC_INS_STQ, + }, + {SP_LDXri, SPARC_INS_LDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_STQFrr, SPARC_INS_STQ, + }, + {SP_LDXrr, SPARC_INS_LDX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_STXri, SPARC_INS_STX, + }, + {SP_LDri, SPARC_INS_LD, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_STXrr, SPARC_INS_STX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + }, + {SP_LDrr, SPARC_INS_LD, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SP_LEAX_ADDri, + SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_LEA_ADDri, + SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_32BIT, 0}, + 0, + 0 +#endif + }, + {SP_LZCNT, + SPARC_INS_LZCNT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_MEMBARi, + SPARC_INS_MEMBAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_MOVDTOX, + SPARC_INS_MOVDTOX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_MOVFCCri, + SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + {SPARC_REG_FCC0, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_MOVFCCrr, + SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + {SPARC_REG_FCC0, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_MOVICCri, + SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_MOVICCrr, + SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_MOVRGEZri, + SPARC_INS_MOVRGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRGEZrr, + SPARC_INS_MOVRGEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRGZri, + SPARC_INS_MOVRGZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRGZrr, + SPARC_INS_MOVRGZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRLEZri, + SPARC_INS_MOVRLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRLEZrr, + SPARC_INS_MOVRLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRLZri, + SPARC_INS_MOVRLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRLZrr, + SPARC_INS_MOVRLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRNZri, + SPARC_INS_MOVRNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRNZrr, + SPARC_INS_MOVRNZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRRZri, + SPARC_INS_MOVRZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVRRZrr, + SPARC_INS_MOVRZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVSTOSW, + SPARC_INS_MOVSTOSW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_MOVSTOUW, + SPARC_INS_MOVSTOUW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_MOVWTOS, + SPARC_INS_MOVDTOX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_MOVXCCri, + SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_MOVXCCrr, + SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_STri, SPARC_INS_ST, + }, + {SP_MOVXTOD, + SPARC_INS_MOVDTOX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 #endif -}, -{ - SP_STrr, SPARC_INS_ST, + }, + {SP_MULXri, + SPARC_INS_MULX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_SUBCCri, SPARC_INS_SUBCC, + }, + {SP_MULXrr, + SPARC_INS_MULX, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_SUBCCrr, SPARC_INS_SUBCC, + }, + {SP_NOP, SPARC_INS_NOP, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_SUBCri, SPARC_INS_SUBX, + }, + {SP_ORCCri, SPARC_INS_ORCC, #ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_SUBCrr, SPARC_INS_SUBX, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 + }, + {SP_ORCCrr, SPARC_INS_ORCC, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_SUBEri, SPARC_INS_SUBXCC, -#ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + }, + {SP_ORNCCri, SPARC_INS_ORNCC, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_SUBErr, SPARC_INS_SUBXCC, + }, + {SP_ORNCCrr, SPARC_INS_ORNCC, #ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_SUBXri, SPARC_INS_SUB, + }, + {SP_ORNri, SPARC_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_SUBXrr, SPARC_INS_SUB, + }, + {SP_ORNrr, SPARC_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_SUBri, SPARC_INS_SUB, + }, + {SP_ORXNrr, SPARC_INS_ORN, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_SUBrr, SPARC_INS_SUB, + }, + {SP_ORXri, SPARC_INS_OR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_SWAPri, SPARC_INS_SWAP, + }, + {SP_ORXrr, SPARC_INS_OR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_SWAPrr, SPARC_INS_SWAP, + }, + {SP_ORri, SPARC_INS_OR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_TA3, SPARC_INS_T, + }, + {SP_ORrr, SPARC_INS_OR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_TA5, SPARC_INS_T, + }, + {SP_PDIST, + SPARC_INS_PDIST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 #endif -}, -{ - SP_TADDCCTVri, SPARC_INS_TADDCCTV, + }, + {SP_PDISTN, + SPARC_INS_PDISTN, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 #endif -}, -{ - SP_TADDCCTVrr, SPARC_INS_TADDCCTV, + }, + {SP_POPCrr, + SPARC_INS_POPC, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 #endif -}, -{ - SP_TADDCCri, SPARC_INS_TADDCC, + }, + {SP_RESTOREri, + SPARC_INS_RESTORE, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, -{ - SP_TADDCCrr, SPARC_INS_TADDCC, + }, + {SP_RESTORErr, + SPARC_INS_RESTORE, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif -}, -{ - SP_TICCri, SPARC_INS_T, + }, + {SP_RET, SPARC_INS_JMP, #ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_TICCrr, SPARC_INS_T, + }, + {SP_RETL, SPARC_INS_JMP, #ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_TLS_ADDXrr, SPARC_INS_ADD, + }, + {SP_RETTri, SPARC_INS_RETT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_TLS_ADDrr, SPARC_INS_ADD, + }, + {SP_RETTrr, SPARC_INS_RETT, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_TLS_CALL, SPARC_INS_CALL, + }, + {SP_SAVEri, SPARC_INS_SAVE, #ifndef CAPSTONE_DIET - { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_SAVErr, SPARC_INS_SAVE, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_SDIVCCri, + SPARC_INS_SDIVCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_Y, SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_SDIVCCrr, + SPARC_INS_SDIVCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_Y, SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_SDIVXri, + SPARC_INS_SDIVX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_SDIVXrr, + SPARC_INS_SDIVX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_SDIVri, SPARC_INS_SDIV, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_Y, 0}, {0}, 0, + 0 +#endif + }, + {SP_SDIVrr, SPARC_INS_SDIV, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_Y, 0}, {0}, 0, + 0 +#endif + }, + {SP_SETHIXi, + SPARC_INS_SETHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_SETHIi, SPARC_INS_SETHI, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_SHUTDOWN, + SPARC_INS_SHUTDOWN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS, 0}, + 0, + 0 +#endif + }, + {SP_SIAM, + SPARC_INS_SIAM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS2, 0}, + 0, + 0 +#endif + }, + {SP_SLLXri, + SPARC_INS_SLLX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_SLLXrr, + SPARC_INS_SLLX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_SLLri, SPARC_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SP_SLLrr, SPARC_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SP_SMULCCri, + SPARC_INS_SMULCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_Y, SPARC_REG_ICC, 0}, + {0}, + 0, + 0 #endif -}, -{ - SP_TLS_LDXrr, SPARC_INS_LDX, + }, + {SP_SMULCCrr, + SPARC_INS_SMULCC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, + {SPARC_REG_Y, SPARC_REG_ICC, 0}, + {0}, + 0, + 0 #endif -}, -{ - SP_TLS_LDrr, SPARC_INS_LD, + }, + {SP_SMULri, SPARC_INS_SMUL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {SPARC_REG_Y, 0}, {0}, 0, + 0 #endif -}, -{ - SP_TSUBCCTVri, SPARC_INS_TSUBCCTV, + }, + {SP_SMULrr, SPARC_INS_SMUL, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {SPARC_REG_Y, 0}, {0}, 0, + 0 #endif -}, -{ - SP_TSUBCCTVrr, SPARC_INS_TSUBCCTV, + }, + {SP_SRAXri, + SPARC_INS_SRAX, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_TSUBCCri, SPARC_INS_TSUBCC, + }, + {SP_SRAXrr, + SPARC_INS_SRAX, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_TSUBCCrr, SPARC_INS_TSUBCC, + }, + {SP_SRAri, SPARC_INS_SRA, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_TXCCri, SPARC_INS_T, + }, + {SP_SRArr, SPARC_INS_SRA, #ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_TXCCrr, SPARC_INS_T, + }, + {SP_SRLXri, + SPARC_INS_SRLX, #ifndef CAPSTONE_DIET - { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_UDIVCCri, SPARC_INS_UDIVCC, + }, + {SP_SRLXrr, + SPARC_INS_SRLX, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 #endif -}, -{ - SP_UDIVCCrr, SPARC_INS_UDIVCC, + }, + {SP_SRLri, SPARC_INS_SRL, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_UDIVXri, SPARC_INS_UDIVX, + }, + {SP_SRLrr, SPARC_INS_SRL, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_UDIVXrr, SPARC_INS_UDIVX, + }, + {SP_STBAR, SPARC_INS_STBAR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_UDIVri, SPARC_INS_UDIV, + }, + {SP_STBri, SPARC_INS_STB, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_UDIVrr, SPARC_INS_UDIV, + }, + {SP_STBrr, SPARC_INS_STB, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_UMULCCri, SPARC_INS_UMULCC, + }, + {SP_STDFri, SPARC_INS_STD, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_UMULCCrr, SPARC_INS_UMULCC, + }, + {SP_STDFrr, SPARC_INS_STD, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_UMULXHI, SPARC_INS_UMULXHI, + }, + {SP_STFri, SPARC_INS_ST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_UMULri, SPARC_INS_UMUL, + }, + {SP_STFrr, SPARC_INS_ST, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_UMULrr, SPARC_INS_UMUL, + }, + {SP_STHri, SPARC_INS_STH, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_UNIMP, SPARC_INS_UNIMP, + }, + {SP_STHrr, SPARC_INS_STH, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_V9FCMPD, SPARC_INS_FCMPD, + }, + {SP_STQFri, SPARC_INS_STQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0}, 0, + 0 #endif -}, -{ - SP_V9FCMPED, SPARC_INS_FCMPED, + }, + {SP_STQFrr, SPARC_INS_STQ, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0}, 0, + 0 #endif -}, -{ - SP_V9FCMPEQ, SPARC_INS_FCMPEQ, + }, + {SP_STXri, SPARC_INS_STX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_V9FCMPES, SPARC_INS_FCMPES, + }, + {SP_STXrr, SPARC_INS_STX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_V9FCMPQ, SPARC_INS_FCMPQ, + }, + {SP_STri, SPARC_INS_ST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_V9FCMPS, SPARC_INS_FCMPS, + }, + {SP_STrr, SPARC_INS_ST, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_V9FMOVD_FCC, SPARC_INS_FMOVD, + }, + {SP_SUBCCri, SPARC_INS_SUBCC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_V9FMOVQ_FCC, SPARC_INS_FMOVQ, + }, + {SP_SUBCCrr, SPARC_INS_SUBCC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_V9FMOVS_FCC, SPARC_INS_FMOVS, + }, + {SP_SUBCri, + SPARC_INS_SUBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {0}, + {0}, + 0, + 0 #endif -}, -{ - SP_V9MOVFCCri, SPARC_INS_MOV, + }, + {SP_SUBCrr, + SPARC_INS_SUBX, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {0}, + {0}, + 0, + 0 #endif -}, -{ - SP_V9MOVFCCrr, SPARC_INS_MOV, + }, + {SP_SUBEri, + SPARC_INS_SUBXCC, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 #endif -}, -{ - SP_WRYri, SPARC_INS_WR, + }, + {SP_SUBErr, + SPARC_INS_SUBXCC, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 + {SPARC_REG_ICC, 0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 #endif -}, -{ - SP_WRYrr, SPARC_INS_WR, + }, + {SP_SUBXri, SPARC_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_XMULX, SPARC_INS_XMULX, + }, + {SP_SUBXrr, SPARC_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_XMULXHI, SPARC_INS_XMULXHI, + }, + {SP_SUBri, SPARC_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_XNORCCri, SPARC_INS_XNORCC, + }, + {SP_SUBrr, SPARC_INS_SUB, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_XNORCCrr, SPARC_INS_XNORCC, + }, + {SP_SWAPri, SPARC_INS_SWAP, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_XNORXrr, SPARC_INS_XNOR, + }, + {SP_SWAPrr, SPARC_INS_SWAP, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 -#endif -}, -{ - SP_XNORri, SPARC_INS_XNOR, + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_TA3, SPARC_INS_T, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SP_TA5, SPARC_INS_T, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SP_TADDCCTVri, + SPARC_INS_TADDCCTV, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_TADDCCTVrr, + SPARC_INS_TADDCCTV, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_TADDCCri, + SPARC_INS_TADDCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_TADDCCrr, + SPARC_INS_TADDCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_TICCri, + SPARC_INS_T, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_TICCrr, + SPARC_INS_T, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_TLS_ADDXrr, + SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_TLS_ADDrr, + SPARC_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_TLS_CALL, + SPARC_INS_CALL, +#ifndef CAPSTONE_DIET + {SPARC_REG_O6, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_TLS_LDXrr, + SPARC_INS_LDX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_TLS_LDrr, + SPARC_INS_LD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_TSUBCCTVri, + SPARC_INS_TSUBCCTV, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_TSUBCCTVrr, + SPARC_INS_TSUBCCTV, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_TSUBCCri, + SPARC_INS_TSUBCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_TSUBCCrr, + SPARC_INS_TSUBCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_TXCCri, + SPARC_INS_T, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_TXCCrr, + SPARC_INS_T, +#ifndef CAPSTONE_DIET + {SPARC_REG_ICC, 0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_UDIVCCri, + SPARC_INS_UDIVCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_Y, SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_UDIVCCrr, + SPARC_INS_UDIVCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_Y, SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_UDIVXri, + SPARC_INS_UDIVX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_UDIVXrr, + SPARC_INS_UDIVX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_UDIVri, SPARC_INS_UDIV, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_Y, 0}, {0}, 0, + 0 +#endif + }, + {SP_UDIVrr, SPARC_INS_UDIV, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_Y, 0}, {0}, 0, + 0 +#endif + }, + {SP_UMULCCri, + SPARC_INS_UMULCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_Y, SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_UMULCCrr, + SPARC_INS_UMULCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_Y, SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_UMULXHI, + SPARC_INS_UMULXHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_UMULri, SPARC_INS_UMUL, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_Y, 0}, {0}, 0, + 0 +#endif + }, + {SP_UMULrr, SPARC_INS_UMUL, +#ifndef CAPSTONE_DIET + {0}, {SPARC_REG_Y, 0}, {0}, 0, + 0 +#endif + }, + {SP_UNIMP, SPARC_INS_UNIMP, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_V9FCMPD, SPARC_INS_FCMPD, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_V9FCMPED, + SPARC_INS_FCMPED, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_V9FCMPEQ, + SPARC_INS_FCMPEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_V9FCMPES, + SPARC_INS_FCMPES, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SP_V9FCMPQ, + SPARC_INS_FCMPQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_HARDQUAD, 0}, + 0, + 0 +#endif + }, + {SP_V9FCMPS, SPARC_INS_FCMPS, +#ifndef CAPSTONE_DIET + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_V9FMOVD_FCC, + SPARC_INS_FMOVD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_V9FMOVQ_FCC, + SPARC_INS_FMOVQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_V9FMOVS_FCC, + SPARC_INS_FMOVS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_V9MOVFCCri, + SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_V9MOVFCCrr, + SPARC_INS_MOV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_V9, 0}, + 0, + 0 +#endif + }, + {SP_XMULX, + SPARC_INS_XMULX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_VIS3, 0}, + 0, + 0 +#endif + }, + {SP_XNORCCri, + SPARC_INS_XNORCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_XNORCCrr, + SPARC_INS_XNORCC, +#ifndef CAPSTONE_DIET + {0}, + {SPARC_REG_ICC, 0}, + {0}, + 0, + 0 +#endif + }, + {SP_XNORXrr, + SPARC_INS_XNOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SPARC_GRP_64BIT, 0}, + 0, + 0 +#endif + }, + {SP_XNORri, SPARC_INS_XNOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SP_XNORrr, SPARC_INS_XNOR, + {0}, {0}, + {0}, 0, + 0 +#endif + }, + {SP_XNORrr, SPARC_INS_XNOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, + {0}, 0, + 0 #endif -}, -{ - SP_XORCCri, SPARC_INS_XORCC, + }, + {SP_XORCCri, SPARC_INS_XORCC, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_XORCCrr, SPARC_INS_XORCC, + }, + {SP_XORCCrr, SPARC_INS_XORCC, #ifndef CAPSTONE_DIET - { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 + {0}, {SPARC_REG_ICC, 0}, {0}, 0, + 0 #endif -}, -{ - SP_XORXri, SPARC_INS_XOR, + }, + {SP_XORXri, SPARC_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_XORXrr, SPARC_INS_XOR, + }, + {SP_XORXrr, SPARC_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 + {0}, {0}, {SPARC_GRP_64BIT, 0}, 0, + 0 #endif -}, -{ - SP_XORri, SPARC_INS_XOR, + }, + {SP_XORri, SPARC_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, -{ - SP_XORrr, SPARC_INS_XOR, + }, + {SP_XORrr, SPARC_INS_XOR, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, {0}, {0}, 0, + 0 #endif -}, + }, diff --git a/arch/Sparc/SparcModule.c b/arch/Sparc/SparcModule.c index 88a0a9e8ca..ef663db4d8 100644 --- a/arch/Sparc/SparcModule.c +++ b/arch/Sparc/SparcModule.c @@ -3,43 +3,41 @@ #ifdef CAPSTONE_HAS_SPARC -#include "../../utils.h" +#include "SparcModule.h" #include "../../MCRegisterInfo.h" +#include "../../utils.h" #include "SparcDisassembler.h" #include "SparcInstPrinter.h" #include "SparcMapping.h" -#include "SparcModule.h" -cs_err Sparc_global_init(cs_struct *ud) -{ - MCRegisterInfo *mri; - mri = cs_mem_malloc(sizeof(*mri)); +cs_err Sparc_global_init(cs_struct *ud) { + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); - Sparc_init(mri); - ud->printer = Sparc_printInst; - ud->printer_info = mri; - ud->getinsn_info = mri; - ud->disasm = Sparc_getInstruction; - ud->post_printer = Sparc_post_printer; + Sparc_init(mri); + ud->printer = Sparc_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = Sparc_getInstruction; + ud->post_printer = Sparc_post_printer; - ud->reg_name = Sparc_reg_name; - ud->insn_id = Sparc_get_insn_id; - ud->insn_name = Sparc_insn_name; - ud->group_name = Sparc_group_name; + ud->reg_name = Sparc_reg_name; + ud->insn_id = Sparc_get_insn_id; + ud->insn_name = Sparc_insn_name; + ud->group_name = Sparc_group_name; - return CS_ERR_OK; + return CS_ERR_OK; } -cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value) -{ - if (type == CS_OPT_SYNTAX) - handle->syntax = (int) value; +cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value) { + if (type == CS_OPT_SYNTAX) + handle->syntax = (int)value; - if (type == CS_OPT_MODE) { - handle->mode = (cs_mode)value; - } + if (type == CS_OPT_MODE) { + handle->mode = (cs_mode)value; + } - return CS_ERR_OK; + return CS_ERR_OK; } #endif diff --git a/arch/SystemZ/CapstoneSystemZModule.h b/arch/SystemZ/CapstoneSystemZModule.h new file mode 100644 index 0000000000..e7e1683ac5 --- /dev/null +++ b/arch/SystemZ/CapstoneSystemZModule.h @@ -0,0 +1,539 @@ +// +// Created by Phosphorus15 on 2021/7/14. +// + +#ifndef CAPSTONE_CAPSTONESYSTEMZMODULE_H +#define CAPSTONE_CAPSTONESYSTEMZMODULE_H + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} + +static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, + const unsigned *Regs, unsigned Size); + +static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, void *); + +static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, int N); + +static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, int N); + +static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, bool isBranch, void *, + int N); + +static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *); + +static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs); + +static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs); + +static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs); + +static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs); + +static DecodeStatus decodeBDLAddr12Len4Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs); + +static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs); + +static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs); + +static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs); + +static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, void *); + +static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, void *); + +static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, void *); + +static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, void *); + +static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, void *); + +static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, void *); + +static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, + uint64_t Field, + uint64_t Address, void *); + +static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, + uint64_t Field, + uint64_t Address, void *); + +static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, void *); + +static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, void *); + +#define GET_REGINFO_ENUM +#define GET_INSTRINFO_ENUM +#define MIPS_GET_DISASSEMBLER +#define GET_REGINFO_MC_DESC +#include "SystemZGenDisassemblerTables.inc" + +FieldFromInstruction(fieldFromInstruction_4, uint64_t) + DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint64_t) + DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, + decodeToMCInst_4, uint64_t) + + static DecodeStatus + decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs, + unsigned Size) { + assert(RegNo < Size && "Invalid register"); + RegNo = Regs[RegNo]; + if (RegNo == 0) + return MCDisassembler_Fail; + MCOperand_CreateReg0(Inst, RegNo); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs, 16); +} + +static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs, 16); +} + +static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs, 16); +} + +static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs, 16); +} + +static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs, 16); +} + +static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs, 16); +} + +static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs, 16); +} + +static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs, 16); +} + +static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs, 32); +} + +static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs, 32); +} + +static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs, 32); +} + +static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs, 16); +} + +static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, + uint64_t Address, + void *Decoder) { + return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs, 16); +} + +static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, int N) { + // if (!isUInt(Imm, N)) + // return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, Imm); + return MCDisassembler_Success; +} + +static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, int N) { + // if (!isUInt(Imm, N)) + // return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeUImmOperand(Inst, Imm, 1); +} + +static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeUImmOperand(Inst, Imm, 2); +} + +static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeUImmOperand(Inst, Imm, 3); +} + +static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeUImmOperand(Inst, Imm, 4); +} + +static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeUImmOperand(Inst, Imm, 6); +} + +static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeUImmOperand(Inst, Imm, 8); +} + +static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeUImmOperand(Inst, Imm, 12); +} + +static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeUImmOperand(Inst, Imm, 16); +} + +static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeUImmOperand(Inst, Imm, 32); +} + +static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeSImmOperand(Inst, Imm, 8); +} + +static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeSImmOperand(Inst, Imm, 16); +} + +static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodeSImmOperand(Inst, Imm, 32); +} + +static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, bool isBranch, + void *Decoder, int N) { + // assert(isUInt(Imm, N) && "Invalid PC-relative offset"); + uint64_t Value = SignExtend64(Imm, N) * 2 + Address; + + // if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, N / 8, + // Inst, Decoder)) + MCOperand_CreateImm0(Inst, Value); + + return MCDisassembler_Success; +} + +static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, + void *Decoder) { + return decodePCDBLOperand(Inst, Imm, Address, true, Decoder, 12); +} + +static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, + void *Decoder) { + return decodePCDBLOperand(Inst, Imm, Address, true, Decoder, 16); +} + +static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, + void *Decoder) { + return decodePCDBLOperand(Inst, Imm, Address, true, Decoder, 24); +} + +static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, + void *Decoder) { + return decodePCDBLOperand(Inst, Imm, Address, true, Decoder, 32); +} + +static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm, + uint64_t Address, void *Decoder) { + return decodePCDBLOperand(Inst, Imm, Address, false, Decoder, 32); +} + +static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Base = Field >> 12; + uint64_t Disp = Field & 0xfff; + assert(Base < 16 && "Invalid BDAddr12"); + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Base = Field >> 20; + uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); + // assert(Base < 16 && "Invalid BDAddr20"); + + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Index = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + assert(Index < 16 && "Invalid BDXAddr12"); + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Index = Field >> 24; + uint64_t Base = (Field >> 20) & 0xf; + uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); + assert(Index < 16 && "Invalid BDXAddr20"); + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); + MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDLAddr12Len4Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Length = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + assert(Length < 16 && "Invalid BDLAddr12Len4"); + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateImm0(Inst, Length + 1); + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Length = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + assert(Length < 256 && "Invalid BDLAddr12Len8"); + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateImm0(Inst, Length + 1); + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Length = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + assert(Length < 16 && "Invalid BDRAddr12"); + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateReg0(Inst, Regs[Length]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field, + const unsigned *Regs) { + uint64_t Index = Field >> 16; + uint64_t Base = (Field >> 12) & 0xf; + uint64_t Disp = Field & 0xfff; + assert(Index < 32 && "Invalid BDVAddr12"); + MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); + MCOperand_CreateImm0(Inst, Disp); + MCOperand_CreateReg0(Inst, SystemZMC_VR128Regs[Index]); + return MCDisassembler_Success; +} + +static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR32Regs); +} + +static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR32Regs); +} + +static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDXAddr12Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDXAddr20Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, + uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDLAddr12Len4Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, + uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDRAddr12Operand(Inst, Field, SystemZMC_GR64Regs); +} + +static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field, + uint64_t Address, + void *Decoder) { + return decodeBDVAddr12Operand(Inst, Field, SystemZMC_GR64Regs); +} + +#endif // CAPSTONE_CAPSTONESYSTEMZMODULE_H diff --git a/arch/SystemZ/SystemZDisassembler.c b/arch/SystemZ/SystemZDisassembler.c index a64a85c4d7..41da18b622 100644 --- a/arch/SystemZ/SystemZDisassembler.c +++ b/arch/SystemZ/SystemZDisassembler.c @@ -1,4 +1,5 @@ -//===------ SystemZDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// +//===------ SystemZDisassembler.cpp - Disassembler for PowerPC ------*- C++ +//-*-===// // // The LLVM Compiler Infrastructure // @@ -12,7 +13,7 @@ #ifdef CAPSTONE_HAS_SYSZ -#include // DEBUG +#include // DEBUG #include #include @@ -21,464 +22,89 @@ #include "SystemZDisassembler.h" +#include "../../MCDisassembler.h" +#include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" -#include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" -#include "../../MCDisassembler.h" #include "../../MathExtras.h" #include "SystemZMCTargetDesc.h" -static uint64_t getFeatureBits(int mode) -{ - // support everything - return (uint64_t)-1; -} - -static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) -{ - //assert(RegNo < 16 && "Invalid register"); - RegNo = Regs[RegNo]; - if (RegNo == 0) - return MCDisassembler_Fail; - - MCOperand_CreateReg0(Inst, (unsigned)RegNo); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs); -} - -static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs); -} - -static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); -} - -static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs); -} - -static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); -} - -static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs); -} - -static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs); -} - -static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs); -} - -static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs); -} - -static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs); -} - -static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs); -} - -static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs); -} - -static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs); -} - -static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm) -{ - //assert(isUInt(Imm) && "Invalid immediate"); - MCOperand_CreateImm0(Inst, Imm); - return MCDisassembler_Success; -} - -static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N) -{ - //assert(isUInt(Imm) && "Invalid immediate"); - MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); - return MCDisassembler_Success; -} - -static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeUImmOperand(Inst, Imm); -} - -static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeSImmOperand(Inst, Imm, 8); -} - -static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeSImmOperand(Inst, Imm, 16); -} - -static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) -{ - return decodeSImmOperand(Inst, Imm, 32); -} - -static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, unsigned N) -{ - //assert(isUInt(Imm) && "Invalid PC-relative offset"); - MCOperand_CreateImm0(Inst, SignExtend64(Imm, N) * 2 + Address); - return MCDisassembler_Success; -} - -static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) -{ - return decodePCDBLOperand(Inst, Imm, Address, 12); -} - -static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) -{ - return decodePCDBLOperand(Inst, Imm, Address, 16); -} - -static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) -{ - return decodePCDBLOperand(Inst, Imm, Address, 24); -} - -static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) -{ - return decodePCDBLOperand(Inst, Imm, Address, 32); -} - -static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) -{ - return decodePCDBLOperand(Inst, Imm, Address, 32); -} - -static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Base = Field >> 12; - uint64_t Disp = Field & 0xfff; - //assert(Base < 16 && "Invalid BDAddr12"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Base = Field >> 20; - uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); - //assert(Base < 16 && "Invalid BDAddr20"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Index = Field >> 16; - uint64_t Base = (Field >> 12) & 0xf; - uint64_t Disp = Field & 0xfff; - - //assert(Index < 16 && "Invalid BDXAddr12"); - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Index = Field >> 24; - uint64_t Base = (Field >> 20) & 0xf; - uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); - - //assert(Index < 16 && "Invalid BDXAddr20"); - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); - MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Length = Field >> 16; - uint64_t Base = (Field >> 12) & 0xf; - uint64_t Disp = Field & 0xfff; - //assert(Length < 256 && "Invalid BDLAddr12Len8"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - MCOperand_CreateImm0(Inst, Length + 1); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Length = Field >> 16; - uint64_t Base = (Field >> 12) & 0xf; - uint64_t Disp = Field & 0xfff; - //assert(Length < 16 && "Invalid BDRAddr12"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - MCOperand_CreateReg0(Inst, Regs[Length]); - - return MCDisassembler_Success; +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require) { + // extended from original arm module + return Require; } -static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field, - const unsigned *Regs) -{ - uint64_t Index = Field >> 16; - uint64_t Base = (Field >> 12) & 0xf; - uint64_t Disp = Field & 0xfff; - //assert(Index < 32 && "Invalid BDVAddr12"); - - MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); - MCOperand_CreateImm0(Inst, Disp); - MCOperand_CreateReg0(Inst, SystemZMC_VR128Regs[Index]); - - return MCDisassembler_Success; -} - -static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR32Regs); -} - -static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR32Regs); -} - -static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDXAddr12Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDXAddr20Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDRAddr12Operand(Inst, Field, SystemZMC_GR64Regs); -} - -static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field, - uint64_t Address, const void *Decoder) -{ - return decodeBDVAddr12Operand(Inst, Field, SystemZMC_GR64Regs); -} - - #define GET_SUBTARGETINFO_ENUM #include "SystemZGenSubtargetInfo.inc" -#include "SystemZGenDisassemblerTables.inc" -bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, - uint16_t *size, uint64_t address, void *info) -{ - uint64_t Inst; - const uint8_t *Table; - uint16_t I; - - // The top 2 bits of the first byte specify the size. - if (*code < 0x40) { - *size = 2; - Table = DecoderTable16; - } else if (*code < 0xc0) { - *size = 4; - Table = DecoderTable32; - } else { - *size = 6; - Table = DecoderTable48; - } - - if (code_len < *size) - // short of input data - return false; - - if (MI->flat_insn->detail) { - memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sysz)+sizeof(cs_sysz)); - } - - // Construct the instruction. - Inst = 0; - for (I = 0; I < *size; ++I) - Inst = (Inst << 8) | code[I]; - - return decodeInstruction(Table, MI, Inst, address, info, 0); -} - -#define GET_REGINFO_ENUM -#define GET_REGINFO_MC_DESC -#include "SystemZGenRegisterInfo.inc" -void SystemZ_init(MCRegisterInfo *MRI) -{ - /* - InitMCRegisterInfo(SystemZRegDesc, 98, RA, PC, - SystemZMCRegisterClasses, 12, - SystemZRegUnitRoots, - 49, - SystemZRegDiffLists, - SystemZRegStrings, - SystemZSubRegIdxLists, - 7, - SystemZSubRegIdxRanges, - SystemZRegEncodingTable); - */ - MCRegisterInfo_InitMCRegisterInfo(MRI, SystemZRegDesc, 194, - 0, 0, - SystemZMCRegisterClasses, 21, - 0, 0, - SystemZRegDiffLists, - 0, - SystemZSubRegIdxLists, 7, - 0); +#include "CapstoneSystemZModule.h" + +static uint64_t getFeatureBits(int mode) { + // support everything + return (uint64_t)-1; +} + +bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, uint64_t address, + void *info) { + uint64_t Inst; + const uint8_t *Table; + uint16_t I; + + // The top 2 bits of the first byte specify the size. + if (*code < 0x40) { + *size = 2; + Table = DecoderTable16; + } else if (*code < 0xc0) { + *size = 4; + Table = DecoderTable32; + } else { + *size = 6; + Table = DecoderTable48; + } + + if (code_len < *size) + // short of input data + return false; + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, + offsetof(cs_detail, sysz) + sizeof(cs_sysz)); + } + + // Construct the instruction. + Inst = 0; + for (I = 0; I < *size; ++I) + Inst = (Inst << 8) | code[I]; + + if (*size > 4) + return decodeInstruction_4(Table, MI, Inst, address, info, 0); + + return decodeInstruction(Table, MI, Inst, address, info, 0); +} + +void SystemZ_init(MCRegisterInfo *MRI) { + /* + InitMCRegisterInfo(SystemZRegDesc, 98, RA, PC, + SystemZMCRegisterClasses, 12, + SystemZRegUnitRoots, + 49, + SystemZRegDiffLists, + SystemZRegStrings, + SystemZSubRegIdxLists, + 7, + SystemZSubRegIdxRanges, + SystemZRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo( + MRI, SystemZRegDesc, ARR_SIZE(SystemZRegDesc), 0, 0, + SystemZMCRegisterClasses, ARR_SIZE(SystemZMCRegisterClasses), 0, 0, + SystemZRegDiffLists, 0, SystemZSubRegIdxLists, + ARR_SIZE(SystemZSubRegIdxLists), 0); } #endif diff --git a/arch/SystemZ/SystemZDisassembler.h b/arch/SystemZ/SystemZDisassembler.h index 8b6e540551..bc355db795 100644 --- a/arch/SystemZ/SystemZDisassembler.h +++ b/arch/SystemZ/SystemZDisassembler.h @@ -4,14 +4,14 @@ #ifndef CS_SYSZDISASSEMBLER_H #define CS_SYSZDISASSEMBLER_H -#include "capstone/capstone.h" -#include "../../MCRegisterInfo.h" #include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "capstone/capstone.h" void SystemZ_init(MCRegisterInfo *MRI); bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); + MCInst *instr, uint16_t *size, uint64_t address, + void *info); #endif - diff --git a/arch/SystemZ/SystemZGenAsmWriter.inc b/arch/SystemZ/SystemZGenAsmWriter.inc index 149d07f363..41e8787a6c 100644 --- a/arch/SystemZ/SystemZGenAsmWriter.inc +++ b/arch/SystemZ/SystemZGenAsmWriter.inc @@ -9,10628 +9,24137 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ -#include // debug #include - +#include // debug /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) -{ +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'c', 'u', '2', '1', 9, 0, - /* 6 */ 'c', 'u', '4', '1', 9, 0, - /* 12 */ 'c', 'u', '1', '2', 9, 0, - /* 18 */ 'c', 'u', '4', '2', 9, 0, - /* 24 */ 'c', 'u', '1', '4', 9, 0, - /* 30 */ 'c', 'u', '2', '4', 9, 0, - /* 36 */ 't', 'r', 'a', 'p', '4', 9, 0, - /* 43 */ 'l', 'a', 'a', 9, 0, - /* 48 */ 's', 'l', 'd', 'a', 9, 0, - /* 54 */ 's', 'r', 'd', 'a', 9, 0, - /* 60 */ 'e', 's', 'e', 'a', 9, 0, - /* 66 */ 'l', 'p', 't', 'e', 'a', 9, 0, - /* 73 */ 'v', 'f', 'a', 9, 0, - /* 78 */ 's', 'i', 'g', 'a', 9, 0, - /* 84 */ 'e', 'c', 'p', 'g', 'a', 9, 0, - /* 91 */ 'u', 'n', 'p', 'k', 'a', 9, 0, - /* 98 */ 's', 'p', 'k', 'a', 9, 0, - /* 104 */ 's', 'l', 'a', 9, 0, - /* 109 */ 'v', 'g', 'f', 'm', 'a', 9, 0, - /* 116 */ 'v', 'f', 'm', 'a', 9, 0, - /* 122 */ 'k', 'm', 'a', 9, 0, - /* 127 */ 'v', 'f', 'n', 'm', 'a', 9, 0, - /* 134 */ 'p', 'p', 'a', 9, 0, - /* 139 */ 'l', 'e', 'd', 'b', 'r', 'a', 9, 0, - /* 147 */ 'c', 'f', 'd', 'b', 'r', 'a', 9, 0, - /* 155 */ 'c', 'g', 'd', 'b', 'r', 'a', 9, 0, - /* 163 */ 'f', 'i', 'd', 'b', 'r', 'a', 9, 0, - /* 171 */ 'c', 'f', 'e', 'b', 'r', 'a', 9, 0, - /* 179 */ 'c', 'g', 'e', 'b', 'r', 'a', 9, 0, - /* 187 */ 'f', 'i', 'e', 'b', 'r', 'a', 9, 0, - /* 195 */ 'c', 'd', 'f', 'b', 'r', 'a', 9, 0, - /* 203 */ 'c', 'e', 'f', 'b', 'r', 'a', 9, 0, - /* 211 */ 'c', 'x', 'f', 'b', 'r', 'a', 9, 0, - /* 219 */ 'c', 'd', 'g', 'b', 'r', 'a', 9, 0, - /* 227 */ 'c', 'e', 'g', 'b', 'r', 'a', 9, 0, - /* 235 */ 'c', 'x', 'g', 'b', 'r', 'a', 9, 0, - /* 243 */ 'l', 'd', 'x', 'b', 'r', 'a', 9, 0, - /* 251 */ 'l', 'e', 'x', 'b', 'r', 'a', 9, 0, - /* 259 */ 'c', 'f', 'x', 'b', 'r', 'a', 9, 0, - /* 267 */ 'c', 'g', 'x', 'b', 'r', 'a', 9, 0, - /* 275 */ 'f', 'i', 'x', 'b', 'r', 'a', 9, 0, - /* 283 */ 'l', 'r', 'a', 9, 0, - /* 288 */ 'v', 'e', 's', 'r', 'a', 9, 0, - /* 295 */ 'v', 's', 'r', 'a', 9, 0, - /* 301 */ 'a', 'd', 't', 'r', 'a', 9, 0, - /* 308 */ 'd', 'd', 't', 'r', 'a', 9, 0, - /* 315 */ 'c', 'g', 'd', 't', 'r', 'a', 9, 0, - /* 323 */ 'm', 'd', 't', 'r', 'a', 9, 0, - /* 330 */ 's', 'd', 't', 'r', 'a', 9, 0, - /* 337 */ 'c', 'd', 'g', 't', 'r', 'a', 9, 0, - /* 345 */ 'c', 'x', 'g', 't', 'r', 'a', 9, 0, - /* 353 */ 'a', 'x', 't', 'r', 'a', 9, 0, - /* 360 */ 'd', 'x', 't', 'r', 'a', 9, 0, - /* 367 */ 'c', 'g', 'x', 't', 'r', 'a', 9, 0, - /* 375 */ 'm', 'x', 't', 'r', 'a', 9, 0, - /* 382 */ 's', 'x', 't', 'r', 'a', 9, 0, - /* 389 */ 'l', 'u', 'r', 'a', 9, 0, - /* 395 */ 's', 't', 'u', 'r', 'a', 9, 0, - /* 402 */ 'b', 's', 'a', 9, 0, - /* 407 */ 'e', 's', 't', 'a', 9, 0, - /* 413 */ 'm', 's', 't', 'a', 9, 0, - /* 419 */ 'v', 'a', 9, 0, - /* 423 */ 'c', 'p', 'y', 'a', 9, 0, - /* 429 */ 'v', 'g', 'f', 'm', 'a', 'b', 9, 0, - /* 437 */ 'v', 'e', 's', 'r', 'a', 'b', 9, 0, - /* 445 */ 'v', 's', 'r', 'a', 'b', 9, 0, - /* 452 */ 'v', 'a', 'b', 9, 0, - /* 457 */ 'l', 'c', 'b', 'b', 9, 0, - /* 463 */ 'v', 'l', 'b', 'b', 9, 0, - /* 469 */ 'v', 'a', 'c', 'c', 'b', 9, 0, - /* 476 */ 'v', 'e', 'c', 'b', 9, 0, - /* 482 */ 'v', 'l', 'c', 'b', 9, 0, - /* 488 */ 'v', 's', 't', 'r', 'c', 'b', 9, 0, - /* 496 */ 'v', 'f', 'a', 'd', 'b', 9, 0, - /* 503 */ 'w', 'f', 'a', 'd', 'b', 9, 0, - /* 510 */ 'v', 'f', 'm', 'a', 'd', 'b', 9, 0, - /* 518 */ 'w', 'f', 'm', 'a', 'd', 'b', 9, 0, - /* 526 */ 'v', 'f', 'n', 'm', 'a', 'd', 'b', 9, 0, - /* 535 */ 'w', 'f', 'n', 'm', 'a', 'd', 'b', 9, 0, - /* 544 */ 'w', 'f', 'c', 'd', 'b', 9, 0, - /* 551 */ 'v', 'f', 'l', 'c', 'd', 'b', 9, 0, - /* 559 */ 'w', 'f', 'l', 'c', 'd', 'b', 9, 0, - /* 567 */ 't', 'c', 'd', 'b', 9, 0, - /* 573 */ 'v', 'f', 'd', 'd', 'b', 9, 0, - /* 580 */ 'w', 'f', 'd', 'd', 'b', 9, 0, - /* 587 */ 'v', 'f', 'c', 'e', 'd', 'b', 9, 0, - /* 595 */ 'w', 'f', 'c', 'e', 'd', 'b', 9, 0, - /* 603 */ 'v', 'f', 'c', 'h', 'e', 'd', 'b', 9, 0, - /* 612 */ 'w', 'f', 'c', 'h', 'e', 'd', 'b', 9, 0, - /* 621 */ 'v', 'f', 'k', 'h', 'e', 'd', 'b', 9, 0, - /* 630 */ 'w', 'f', 'k', 'h', 'e', 'd', 'b', 9, 0, - /* 639 */ 'v', 'f', 'k', 'e', 'd', 'b', 9, 0, - /* 647 */ 'w', 'f', 'k', 'e', 'd', 'b', 9, 0, - /* 655 */ 'v', 'l', 'e', 'd', 'b', 9, 0, - /* 662 */ 'w', 'l', 'e', 'd', 'b', 9, 0, - /* 669 */ 'v', 'c', 'g', 'd', 'b', 9, 0, - /* 676 */ 'w', 'c', 'g', 'd', 'b', 9, 0, - /* 683 */ 'v', 'c', 'l', 'g', 'd', 'b', 9, 0, - /* 691 */ 'w', 'c', 'l', 'g', 'd', 'b', 9, 0, - /* 699 */ 'v', 'f', 'c', 'h', 'd', 'b', 9, 0, - /* 707 */ 'w', 'f', 'c', 'h', 'd', 'b', 9, 0, - /* 715 */ 'v', 'f', 'k', 'h', 'd', 'b', 9, 0, - /* 723 */ 'w', 'f', 'k', 'h', 'd', 'b', 9, 0, - /* 731 */ 'v', 'f', 't', 'c', 'i', 'd', 'b', 9, 0, - /* 740 */ 'w', 'f', 't', 'c', 'i', 'd', 'b', 9, 0, - /* 749 */ 'v', 'f', 'i', 'd', 'b', 9, 0, - /* 756 */ 'w', 'f', 'i', 'd', 'b', 9, 0, - /* 763 */ 'w', 'f', 'k', 'd', 'b', 9, 0, - /* 770 */ 'v', 's', 'l', 'd', 'b', 9, 0, - /* 777 */ 'v', 'f', 'm', 'd', 'b', 9, 0, - /* 784 */ 'w', 'f', 'm', 'd', 'b', 9, 0, - /* 791 */ 'v', 'f', 'm', 'i', 'n', 'd', 'b', 9, 0, - /* 800 */ 'w', 'f', 'm', 'i', 'n', 'd', 'b', 9, 0, - /* 809 */ 'v', 'f', 'l', 'n', 'd', 'b', 9, 0, - /* 817 */ 'w', 'f', 'l', 'n', 'd', 'b', 9, 0, - /* 825 */ 'v', 'f', 'p', 's', 'o', 'd', 'b', 9, 0, - /* 834 */ 'w', 'f', 'p', 's', 'o', 'd', 'b', 9, 0, - /* 843 */ 'v', 'f', 'l', 'p', 'd', 'b', 9, 0, - /* 851 */ 'w', 'f', 'l', 'p', 'd', 'b', 9, 0, - /* 859 */ 'v', 'f', 's', 'q', 'd', 'b', 9, 0, - /* 867 */ 'w', 'f', 's', 'q', 'd', 'b', 9, 0, - /* 875 */ 'v', 'f', 's', 'd', 'b', 9, 0, - /* 882 */ 'w', 'f', 's', 'd', 'b', 9, 0, - /* 889 */ 'v', 'f', 'm', 's', 'd', 'b', 9, 0, - /* 897 */ 'w', 'f', 'm', 's', 'd', 'b', 9, 0, - /* 905 */ 'v', 'f', 'n', 'm', 's', 'd', 'b', 9, 0, - /* 914 */ 'w', 'f', 'n', 'm', 's', 'd', 'b', 9, 0, - /* 923 */ 'v', 'f', 'm', 'a', 'x', 'd', 'b', 9, 0, - /* 932 */ 'w', 'f', 'm', 'a', 'x', 'd', 'b', 9, 0, - /* 941 */ 'l', 'x', 'd', 'b', 9, 0, - /* 947 */ 'm', 'x', 'd', 'b', 9, 0, - /* 953 */ 'v', 'f', 'a', 'e', 'b', 9, 0, - /* 960 */ 'v', 'm', 'a', 'e', 'b', 9, 0, - /* 967 */ 't', 'c', 'e', 'b', 9, 0, - /* 973 */ 'v', 'l', 'd', 'e', 'b', 9, 0, - /* 980 */ 'w', 'l', 'd', 'e', 'b', 9, 0, - /* 987 */ 'm', 'd', 'e', 'b', 9, 0, - /* 993 */ 'v', 'f', 'e', 'e', 'b', 9, 0, - /* 1000 */ 'm', 'e', 'e', 'b', 9, 0, - /* 1006 */ 'k', 'e', 'b', 9, 0, - /* 1011 */ 'v', 'm', 'a', 'l', 'e', 'b', 9, 0, - /* 1019 */ 'v', 'm', 'l', 'e', 'b', 9, 0, - /* 1026 */ 'v', 'l', 'e', 'b', 9, 0, - /* 1032 */ 'v', 'm', 'e', 'b', 9, 0, - /* 1038 */ 'v', 'f', 'e', 'n', 'e', 'b', 9, 0, - /* 1046 */ 's', 'q', 'e', 'b', 9, 0, - /* 1052 */ 'm', 's', 'e', 'b', 9, 0, - /* 1058 */ 'v', 's', 't', 'e', 'b', 9, 0, - /* 1065 */ 'l', 'x', 'e', 'b', 9, 0, - /* 1071 */ 'v', 'c', 'd', 'g', 'b', 9, 0, - /* 1078 */ 'w', 'c', 'd', 'g', 'b', 9, 0, - /* 1085 */ 'v', 's', 'e', 'g', 'b', 9, 0, - /* 1092 */ 'v', 'c', 'd', 'l', 'g', 'b', 9, 0, - /* 1100 */ 'w', 'c', 'd', 'l', 'g', 'b', 9, 0, - /* 1108 */ 'v', 'a', 'v', 'g', 'b', 9, 0, - /* 1115 */ 'v', 'l', 'v', 'g', 'b', 9, 0, - /* 1122 */ 'v', 'm', 'a', 'h', 'b', 9, 0, - /* 1129 */ 'v', 'c', 'h', 'b', 9, 0, - /* 1135 */ 'v', 'm', 'a', 'l', 'h', 'b', 9, 0, - /* 1143 */ 'v', 'm', 'l', 'h', 'b', 9, 0, - /* 1150 */ 'v', 'u', 'p', 'l', 'h', 'b', 9, 0, - /* 1158 */ 'v', 'm', 'h', 'b', 9, 0, - /* 1164 */ 'v', 'u', 'p', 'h', 'b', 9, 0, - /* 1171 */ 'v', 'm', 'r', 'h', 'b', 9, 0, - /* 1178 */ 'v', 's', 'c', 'b', 'i', 'b', 9, 0, - /* 1186 */ 'c', 'i', 'b', 9, 0, - /* 1191 */ 'v', 'l', 'e', 'i', 'b', 9, 0, - /* 1198 */ 'c', 'g', 'i', 'b', 9, 0, - /* 1204 */ 'c', 'l', 'g', 'i', 'b', 9, 0, - /* 1211 */ 'c', 'l', 'i', 'b', 9, 0, - /* 1217 */ 'v', 'r', 'e', 'p', 'i', 'b', 9, 0, - /* 1225 */ 'v', 'm', 'a', 'l', 'b', 9, 0, - /* 1232 */ 'v', 'e', 'c', 'l', 'b', 9, 0, - /* 1239 */ 'v', 'a', 'v', 'g', 'l', 'b', 9, 0, - /* 1247 */ 'v', 'c', 'h', 'l', 'b', 9, 0, - /* 1254 */ 'v', 'u', 'p', 'l', 'l', 'b', 9, 0, - /* 1262 */ 'v', 'e', 'r', 'l', 'l', 'b', 9, 0, - /* 1270 */ 'v', 'm', 'l', 'b', 9, 0, - /* 1276 */ 'v', 'm', 'n', 'l', 'b', 9, 0, - /* 1283 */ 'v', 'u', 'p', 'l', 'b', 9, 0, - /* 1290 */ 'v', 'm', 'r', 'l', 'b', 9, 0, - /* 1297 */ 'v', 'e', 's', 'r', 'l', 'b', 9, 0, - /* 1305 */ 'v', 's', 'r', 'l', 'b', 9, 0, - /* 1312 */ 'v', 'e', 's', 'l', 'b', 9, 0, - /* 1319 */ 'v', 's', 'l', 'b', 9, 0, - /* 1325 */ 'v', 'm', 'x', 'l', 'b', 9, 0, - /* 1332 */ 'v', 'g', 'f', 'm', 'b', 9, 0, - /* 1339 */ 'v', 'g', 'm', 'b', 9, 0, - /* 1345 */ 'v', 'e', 'r', 'i', 'm', 'b', 9, 0, - /* 1353 */ 's', 'r', 'n', 'm', 'b', 9, 0, - /* 1360 */ 'v', 's', 'u', 'm', 'b', 9, 0, - /* 1367 */ 'v', 'm', 'n', 'b', 9, 0, - /* 1373 */ 'v', 'm', 'a', 'o', 'b', 9, 0, - /* 1380 */ 'v', 'm', 'a', 'l', 'o', 'b', 9, 0, - /* 1388 */ 'v', 'm', 'l', 'o', 'b', 9, 0, - /* 1395 */ 'v', 'm', 'o', 'b', 9, 0, - /* 1401 */ 'v', 'l', 'r', 'e', 'p', 'b', 9, 0, - /* 1409 */ 'v', 'r', 'e', 'p', 'b', 9, 0, - /* 1416 */ 'v', 'l', 'p', 'b', 9, 0, - /* 1422 */ 'v', 'c', 'e', 'q', 'b', 9, 0, - /* 1429 */ 'c', 'r', 'b', 9, 0, - /* 1434 */ 'c', 'g', 'r', 'b', 9, 0, - /* 1440 */ 'c', 'l', 'g', 'r', 'b', 9, 0, - /* 1447 */ 'c', 'l', 'r', 'b', 9, 0, - /* 1453 */ 'v', 'i', 's', 't', 'r', 'b', 9, 0, - /* 1461 */ 'v', 'f', 'a', 's', 'b', 9, 0, - /* 1468 */ 'w', 'f', 'a', 's', 'b', 9, 0, - /* 1475 */ 'v', 'f', 'm', 'a', 's', 'b', 9, 0, - /* 1483 */ 'w', 'f', 'm', 'a', 's', 'b', 9, 0, - /* 1491 */ 'v', 'f', 'n', 'm', 'a', 's', 'b', 9, 0, - /* 1500 */ 'w', 'f', 'n', 'm', 'a', 's', 'b', 9, 0, - /* 1509 */ 'w', 'f', 'c', 's', 'b', 9, 0, - /* 1516 */ 'v', 'f', 'l', 'c', 's', 'b', 9, 0, - /* 1524 */ 'w', 'f', 'l', 'c', 's', 'b', 9, 0, - /* 1532 */ 'v', 'f', 'd', 's', 'b', 9, 0, - /* 1539 */ 'w', 'f', 'd', 's', 'b', 9, 0, - /* 1546 */ 'v', 'f', 'c', 'e', 's', 'b', 9, 0, - /* 1554 */ 'w', 'f', 'c', 'e', 's', 'b', 9, 0, - /* 1562 */ 'v', 'f', 'c', 'h', 'e', 's', 'b', 9, 0, - /* 1571 */ 'w', 'f', 'c', 'h', 'e', 's', 'b', 9, 0, - /* 1580 */ 'v', 'f', 'k', 'h', 'e', 's', 'b', 9, 0, - /* 1589 */ 'w', 'f', 'k', 'h', 'e', 's', 'b', 9, 0, - /* 1598 */ 'v', 'f', 'k', 'e', 's', 'b', 9, 0, - /* 1606 */ 'w', 'f', 'k', 'e', 's', 'b', 9, 0, - /* 1614 */ 'v', 'f', 'c', 'h', 's', 'b', 9, 0, - /* 1622 */ 'w', 'f', 'c', 'h', 's', 'b', 9, 0, - /* 1630 */ 'v', 'f', 'k', 'h', 's', 'b', 9, 0, - /* 1638 */ 'w', 'f', 'k', 'h', 's', 'b', 9, 0, - /* 1646 */ 'v', 'f', 't', 'c', 'i', 's', 'b', 9, 0, - /* 1655 */ 'w', 'f', 't', 'c', 'i', 's', 'b', 9, 0, - /* 1664 */ 'v', 'f', 'i', 's', 'b', 9, 0, - /* 1671 */ 'w', 'f', 'i', 's', 'b', 9, 0, - /* 1678 */ 'w', 'f', 'k', 's', 'b', 9, 0, - /* 1685 */ 'v', 'f', 'm', 's', 'b', 9, 0, - /* 1692 */ 'w', 'f', 'm', 's', 'b', 9, 0, - /* 1699 */ 'v', 'f', 'm', 'i', 'n', 's', 'b', 9, 0, - /* 1708 */ 'w', 'f', 'm', 'i', 'n', 's', 'b', 9, 0, - /* 1717 */ 'v', 'f', 'l', 'n', 's', 'b', 9, 0, - /* 1725 */ 'w', 'f', 'l', 'n', 's', 'b', 9, 0, - /* 1733 */ 'v', 'f', 'p', 's', 'o', 's', 'b', 9, 0, - /* 1742 */ 'w', 'f', 'p', 's', 'o', 's', 'b', 9, 0, - /* 1751 */ 'v', 'f', 'l', 'p', 's', 'b', 9, 0, - /* 1759 */ 'w', 'f', 'l', 'p', 's', 'b', 9, 0, - /* 1767 */ 'v', 'f', 's', 'q', 's', 'b', 9, 0, - /* 1775 */ 'w', 'f', 's', 'q', 's', 'b', 9, 0, - /* 1783 */ 'v', 'f', 's', 's', 'b', 9, 0, - /* 1790 */ 'w', 'f', 's', 's', 'b', 9, 0, - /* 1797 */ 'v', 'f', 'm', 's', 's', 'b', 9, 0, - /* 1805 */ 'w', 'f', 'm', 's', 's', 'b', 9, 0, - /* 1813 */ 'v', 'f', 'n', 'm', 's', 's', 'b', 9, 0, - /* 1822 */ 'w', 'f', 'n', 'm', 's', 's', 'b', 9, 0, - /* 1831 */ 'v', 's', 'b', 9, 0, - /* 1836 */ 'v', 'f', 'm', 'a', 'x', 's', 'b', 9, 0, - /* 1845 */ 'w', 'f', 'm', 'a', 'x', 's', 'b', 9, 0, - /* 1854 */ 'v', 'p', 'o', 'p', 'c', 't', 'b', 9, 0, - /* 1863 */ 'v', 'e', 's', 'r', 'a', 'v', 'b', 9, 0, - /* 1872 */ 'v', 'c', 'v', 'b', 9, 0, - /* 1878 */ 'v', 'l', 'g', 'v', 'b', 9, 0, - /* 1885 */ 'v', 'e', 'r', 'l', 'l', 'v', 'b', 9, 0, - /* 1894 */ 'v', 'e', 's', 'r', 'l', 'v', 'b', 9, 0, - /* 1903 */ 'v', 'e', 's', 'l', 'v', 'b', 9, 0, - /* 1911 */ 'w', 'f', 'a', 'x', 'b', 9, 0, - /* 1918 */ 'w', 'f', 'm', 'a', 'x', 'b', 9, 0, - /* 1926 */ 'w', 'f', 'n', 'm', 'a', 'x', 'b', 9, 0, - /* 1935 */ 'w', 'f', 'c', 'x', 'b', 9, 0, - /* 1942 */ 'w', 'f', 'l', 'c', 'x', 'b', 9, 0, - /* 1950 */ 't', 'c', 'x', 'b', 9, 0, - /* 1956 */ 'w', 'f', 'd', 'x', 'b', 9, 0, - /* 1963 */ 'w', 'f', 'c', 'e', 'x', 'b', 9, 0, - /* 1971 */ 'w', 'f', 'c', 'h', 'e', 'x', 'b', 9, 0, - /* 1980 */ 'w', 'f', 'k', 'h', 'e', 'x', 'b', 9, 0, - /* 1989 */ 'w', 'f', 'k', 'e', 'x', 'b', 9, 0, - /* 1997 */ 'w', 'f', 'c', 'h', 'x', 'b', 9, 0, - /* 2005 */ 'w', 'f', 'k', 'h', 'x', 'b', 9, 0, - /* 2013 */ 'w', 'f', 't', 'c', 'i', 'x', 'b', 9, 0, - /* 2022 */ 'w', 'f', 'i', 'x', 'b', 9, 0, - /* 2029 */ 'w', 'f', 'k', 'x', 'b', 9, 0, - /* 2036 */ 'w', 'f', 'm', 'x', 'b', 9, 0, - /* 2043 */ 'v', 'm', 'x', 'b', 9, 0, - /* 2049 */ 'w', 'f', 'm', 'i', 'n', 'x', 'b', 9, 0, - /* 2058 */ 'w', 'f', 'l', 'n', 'x', 'b', 9, 0, - /* 2066 */ 'w', 'f', 'p', 's', 'o', 'x', 'b', 9, 0, - /* 2075 */ 'w', 'f', 'l', 'p', 'x', 'b', 9, 0, - /* 2083 */ 'w', 'f', 's', 'q', 'x', 'b', 9, 0, - /* 2091 */ 'w', 'f', 's', 'x', 'b', 9, 0, - /* 2098 */ 'w', 'f', 'm', 's', 'x', 'b', 9, 0, - /* 2106 */ 'w', 'f', 'n', 'm', 's', 'x', 'b', 9, 0, - /* 2115 */ 'w', 'f', 'm', 'a', 'x', 'x', 'b', 9, 0, - /* 2124 */ 'v', 's', 't', 'r', 'c', 'z', 'b', 9, 0, - /* 2133 */ 'v', 'f', 'a', 'e', 'z', 'b', 9, 0, - /* 2141 */ 'v', 'f', 'e', 'e', 'z', 'b', 9, 0, - /* 2149 */ 'v', 'l', 'l', 'e', 'z', 'b', 9, 0, - /* 2157 */ 'v', 'f', 'e', 'n', 'e', 'z', 'b', 9, 0, - /* 2166 */ 'v', 'c', 'l', 'z', 'b', 9, 0, - /* 2173 */ 'v', 'c', 't', 'z', 'b', 9, 0, - /* 2180 */ 'i', 'a', 'c', 9, 0, - /* 2185 */ 'k', 'm', 'a', 'c', 9, 0, - /* 2191 */ 's', 'a', 'c', 9, 0, - /* 2196 */ 'v', 'a', 'c', 9, 0, - /* 2201 */ 'b', 'c', 9, 0, - /* 2205 */ 'v', 'a', 'c', 'c', 9, 0, - /* 2211 */ 'v', 'a', 'c', 'c', 'c', 9, 0, - /* 2218 */ 'v', 'e', 'c', 9, 0, - /* 2223 */ 'c', 'f', 'c', 9, 0, - /* 2228 */ 'w', 'f', 'c', 9, 0, - /* 2233 */ 'l', 'l', 'g', 'c', 9, 0, - /* 2239 */ 'm', 's', 'g', 'c', 9, 0, - /* 2245 */ 'b', 'i', 'c', 9, 0, - /* 2250 */ 's', 'c', 'k', 'c', 9, 0, - /* 2256 */ 's', 't', 'c', 'k', 'c', 9, 0, - /* 2263 */ 'm', 's', 'g', 'r', 'k', 'c', 9, 0, - /* 2271 */ 'm', 's', 'r', 'k', 'c', 9, 0, - /* 2278 */ 'a', 'l', 'c', 9, 0, - /* 2283 */ 'c', 'l', 'c', 9, 0, - /* 2288 */ 'l', 'l', 'c', 9, 0, - /* 2293 */ 'v', 'l', 'c', 9, 0, - /* 2298 */ 'k', 'm', 'c', 9, 0, - /* 2303 */ 't', 'b', 'e', 'g', 'i', 'n', 'c', 9, 0, - /* 2312 */ 'v', 'n', 'c', 9, 0, - /* 2317 */ 'l', 'o', 'c', 9, 0, - /* 2322 */ 's', 't', 'o', 'c', 9, 0, - /* 2328 */ 'v', 'o', 'c', 9, 0, - /* 2333 */ 'e', 'f', 'p', 'c', 9, 0, - /* 2339 */ 'l', 'f', 'p', 'c', 9, 0, - /* 2345 */ 's', 'f', 'p', 'c', 9, 0, - /* 2351 */ 's', 't', 'f', 'p', 'c', 9, 0, - /* 2358 */ 'b', 'r', 'c', 9, 0, - /* 2363 */ 'v', 's', 't', 'r', 'c', 9, 0, - /* 2370 */ 'l', 'g', 's', 'c', 9, 0, - /* 2376 */ 's', 't', 'g', 's', 'c', 9, 0, - /* 2383 */ 'm', 's', 'c', 9, 0, - /* 2388 */ 'c', 'm', 'p', 's', 'c', 9, 0, - /* 2395 */ 's', 't', 'c', 9, 0, - /* 2400 */ 'm', 'v', 'c', 9, 0, - /* 2405 */ 's', 'v', 'c', 9, 0, - /* 2410 */ 'x', 'c', 9, 0, - /* 2414 */ 'm', 'a', 'd', 9, 0, - /* 2419 */ 'c', 'd', 9, 0, - /* 2423 */ 'd', 'd', 9, 0, - /* 2427 */ 'v', 'l', 'e', 'd', 9, 0, - /* 2433 */ 'p', 'f', 'd', 9, 0, - /* 2438 */ 'v', 'f', 'd', 9, 0, - /* 2443 */ 'v', 'c', 'g', 'd', 9, 0, - /* 2449 */ 'v', 'c', 'l', 'g', 'd', 9, 0, - /* 2456 */ 'w', 'f', 'l', 'l', 'd', 9, 0, - /* 2463 */ 'k', 'i', 'm', 'd', 9, 0, - /* 2469 */ 'k', 'l', 'm', 'd', 9, 0, - /* 2475 */ 'e', 't', 'n', 'd', 9, 0, - /* 2481 */ 'l', 'p', 'd', 9, 0, - /* 2486 */ 's', 'q', 'd', 9, 0, - /* 2491 */ 'v', 'f', 'l', 'r', 'd', 9, 0, - /* 2498 */ 'w', 'f', 'l', 'r', 'd', 9, 0, - /* 2505 */ 'm', 's', 'd', 9, 0, - /* 2510 */ 's', 't', 'd', 9, 0, - /* 2515 */ 'v', 'c', 'v', 'd', 9, 0, - /* 2521 */ 'l', 'x', 'd', 9, 0, - /* 2526 */ 'm', 'x', 'd', 9, 0, - /* 2531 */ 'v', 'f', 'a', 'e', 9, 0, - /* 2537 */ 'l', 'a', 'e', 9, 0, - /* 2542 */ 'v', 'm', 'a', 'e', 9, 0, - /* 2548 */ 'c', 'i', 'b', 'e', 9, 0, - /* 2554 */ 'c', 'g', 'i', 'b', 'e', 9, 0, - /* 2561 */ 'c', 'l', 'g', 'i', 'b', 'e', 9, 0, - /* 2569 */ 'c', 'l', 'i', 'b', 'e', 9, 0, - /* 2576 */ 'c', 'r', 'b', 'e', 9, 0, - /* 2582 */ 'c', 'g', 'r', 'b', 'e', 9, 0, - /* 2589 */ 'c', 'l', 'g', 'r', 'b', 'e', 9, 0, - /* 2597 */ 'c', 'l', 'r', 'b', 'e', 9, 0, - /* 2604 */ 'r', 'r', 'b', 'e', 9, 0, - /* 2610 */ 't', 'r', 'a', 'c', 'e', 9, 0, - /* 2617 */ 'v', 'f', 'c', 'e', 9, 0, - /* 2623 */ 'l', 'o', 'c', 'e', 9, 0, - /* 2629 */ 's', 't', 'o', 'c', 'e', 9, 0, - /* 2636 */ 'v', 'l', 'd', 'e', 9, 0, - /* 2642 */ 'm', 'd', 'e', 9, 0, - /* 2647 */ 'v', 'f', 'e', 'e', 9, 0, - /* 2653 */ 'm', 'e', 'e', 9, 0, - /* 2658 */ 'l', 'o', 'c', 'g', 'e', 9, 0, - /* 2665 */ 's', 't', 'o', 'c', 'g', 'e', 9, 0, - /* 2673 */ 'j', 'g', 'e', 9, 0, - /* 2678 */ 'c', 'i', 'b', 'h', 'e', 9, 0, - /* 2685 */ 'c', 'g', 'i', 'b', 'h', 'e', 9, 0, - /* 2693 */ 'c', 'l', 'g', 'i', 'b', 'h', 'e', 9, 0, - /* 2702 */ 'c', 'l', 'i', 'b', 'h', 'e', 9, 0, - /* 2710 */ 'c', 'r', 'b', 'h', 'e', 9, 0, - /* 2717 */ 'c', 'g', 'r', 'b', 'h', 'e', 9, 0, - /* 2725 */ 'c', 'l', 'g', 'r', 'b', 'h', 'e', 9, 0, - /* 2734 */ 'c', 'l', 'r', 'b', 'h', 'e', 9, 0, - /* 2742 */ 'v', 'f', 'c', 'h', 'e', 9, 0, - /* 2749 */ 'l', 'o', 'c', 'h', 'e', 9, 0, - /* 2756 */ 's', 't', 'o', 'c', 'h', 'e', 9, 0, - /* 2764 */ 'l', 'o', 'c', 'f', 'h', 'e', 9, 0, - /* 2772 */ 's', 't', 'o', 'c', 'f', 'h', 'e', 9, 0, - /* 2781 */ 'l', 'o', 'c', 'g', 'h', 'e', 9, 0, - /* 2789 */ 's', 't', 'o', 'c', 'g', 'h', 'e', 9, 0, - /* 2798 */ 'j', 'g', 'h', 'e', 9, 0, - /* 2804 */ 'l', 'o', 'c', 'f', 'h', 'h', 'e', 9, 0, - /* 2813 */ 's', 't', 'o', 'c', 'f', 'h', 'h', 'e', 9, 0, - /* 2823 */ 'b', 'i', 'h', 'e', 9, 0, - /* 2829 */ 'l', 'o', 'c', 'h', 'i', 'h', 'e', 9, 0, - /* 2838 */ 'l', 'o', 'c', 'g', 'h', 'i', 'h', 'e', 9, 0, - /* 2848 */ 'l', 'o', 'c', 'h', 'h', 'i', 'h', 'e', 9, 0, - /* 2858 */ 'c', 'i', 'j', 'h', 'e', 9, 0, - /* 2865 */ 'c', 'g', 'i', 'j', 'h', 'e', 9, 0, - /* 2873 */ 'c', 'l', 'g', 'i', 'j', 'h', 'e', 9, 0, - /* 2882 */ 'c', 'l', 'i', 'j', 'h', 'e', 9, 0, - /* 2890 */ 'c', 'r', 'j', 'h', 'e', 9, 0, - /* 2897 */ 'c', 'g', 'r', 'j', 'h', 'e', 9, 0, - /* 2905 */ 'c', 'l', 'g', 'r', 'j', 'h', 'e', 9, 0, - /* 2914 */ 'c', 'l', 'r', 'j', 'h', 'e', 9, 0, - /* 2922 */ 'c', 'i', 'b', 'n', 'h', 'e', 9, 0, - /* 2930 */ 'c', 'g', 'i', 'b', 'n', 'h', 'e', 9, 0, - /* 2939 */ 'c', 'l', 'g', 'i', 'b', 'n', 'h', 'e', 9, 0, - /* 2949 */ 'c', 'l', 'i', 'b', 'n', 'h', 'e', 9, 0, - /* 2958 */ 'c', 'r', 'b', 'n', 'h', 'e', 9, 0, - /* 2966 */ 'c', 'g', 'r', 'b', 'n', 'h', 'e', 9, 0, - /* 2975 */ 'c', 'l', 'g', 'r', 'b', 'n', 'h', 'e', 9, 0, - /* 2985 */ 'c', 'l', 'r', 'b', 'n', 'h', 'e', 9, 0, - /* 2994 */ 'l', 'o', 'c', 'n', 'h', 'e', 9, 0, - /* 3002 */ 's', 't', 'o', 'c', 'n', 'h', 'e', 9, 0, - /* 3011 */ 'l', 'o', 'c', 'g', 'n', 'h', 'e', 9, 0, - /* 3020 */ 's', 't', 'o', 'c', 'g', 'n', 'h', 'e', 9, 0, - /* 3030 */ 'j', 'g', 'n', 'h', 'e', 9, 0, - /* 3037 */ 'l', 'o', 'c', 'f', 'h', 'n', 'h', 'e', 9, 0, - /* 3047 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'h', 'e', 9, 0, - /* 3058 */ 'b', 'i', 'n', 'h', 'e', 9, 0, - /* 3065 */ 'l', 'o', 'c', 'h', 'i', 'n', 'h', 'e', 9, 0, - /* 3075 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'h', 'e', 9, 0, - /* 3086 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'h', 'e', 9, 0, - /* 3097 */ 'c', 'i', 'j', 'n', 'h', 'e', 9, 0, - /* 3105 */ 'c', 'g', 'i', 'j', 'n', 'h', 'e', 9, 0, - /* 3114 */ 'c', 'l', 'g', 'i', 'j', 'n', 'h', 'e', 9, 0, - /* 3124 */ 'c', 'l', 'i', 'j', 'n', 'h', 'e', 9, 0, - /* 3133 */ 'c', 'r', 'j', 'n', 'h', 'e', 9, 0, - /* 3141 */ 'c', 'g', 'r', 'j', 'n', 'h', 'e', 9, 0, - /* 3150 */ 'c', 'l', 'g', 'r', 'j', 'n', 'h', 'e', 9, 0, - /* 3160 */ 'c', 'l', 'r', 'j', 'n', 'h', 'e', 9, 0, - /* 3169 */ 'l', 'o', 'c', 'r', 'n', 'h', 'e', 9, 0, - /* 3178 */ 'l', 'o', 'c', 'g', 'r', 'n', 'h', 'e', 9, 0, - /* 3188 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'h', 'e', 9, 0, - /* 3199 */ 'c', 'l', 'g', 't', 'n', 'h', 'e', 9, 0, - /* 3208 */ 'c', 'i', 't', 'n', 'h', 'e', 9, 0, - /* 3216 */ 'c', 'l', 'f', 'i', 't', 'n', 'h', 'e', 9, 0, - /* 3226 */ 'c', 'g', 'i', 't', 'n', 'h', 'e', 9, 0, - /* 3235 */ 'c', 'l', 'g', 'i', 't', 'n', 'h', 'e', 9, 0, - /* 3245 */ 'c', 'l', 't', 'n', 'h', 'e', 9, 0, - /* 3253 */ 'c', 'r', 't', 'n', 'h', 'e', 9, 0, - /* 3261 */ 'c', 'g', 'r', 't', 'n', 'h', 'e', 9, 0, - /* 3270 */ 'c', 'l', 'g', 'r', 't', 'n', 'h', 'e', 9, 0, - /* 3280 */ 'c', 'l', 'r', 't', 'n', 'h', 'e', 9, 0, - /* 3289 */ 'l', 'o', 'c', 'r', 'h', 'e', 9, 0, - /* 3297 */ 'l', 'o', 'c', 'g', 'r', 'h', 'e', 9, 0, - /* 3306 */ 'l', 'o', 'c', 'f', 'h', 'r', 'h', 'e', 9, 0, - /* 3316 */ 'c', 'l', 'g', 't', 'h', 'e', 9, 0, - /* 3324 */ 'c', 'i', 't', 'h', 'e', 9, 0, - /* 3331 */ 'c', 'l', 'f', 'i', 't', 'h', 'e', 9, 0, - /* 3340 */ 'c', 'g', 'i', 't', 'h', 'e', 9, 0, - /* 3348 */ 'c', 'l', 'g', 'i', 't', 'h', 'e', 9, 0, - /* 3357 */ 'c', 'l', 't', 'h', 'e', 9, 0, - /* 3364 */ 'c', 'r', 't', 'h', 'e', 9, 0, - /* 3371 */ 'c', 'g', 'r', 't', 'h', 'e', 9, 0, - /* 3379 */ 'c', 'l', 'g', 'r', 't', 'h', 'e', 9, 0, - /* 3388 */ 'c', 'l', 'r', 't', 'h', 'e', 9, 0, - /* 3396 */ 'b', 'i', 'e', 9, 0, - /* 3401 */ 'l', 'o', 'c', 'h', 'i', 'e', 9, 0, - /* 3409 */ 'l', 'o', 'c', 'g', 'h', 'i', 'e', 9, 0, - /* 3418 */ 'l', 'o', 'c', 'h', 'h', 'i', 'e', 9, 0, - /* 3427 */ 's', 'i', 'e', 9, 0, - /* 3432 */ 'c', 'i', 'j', 'e', 9, 0, - /* 3438 */ 'c', 'g', 'i', 'j', 'e', 9, 0, - /* 3445 */ 'c', 'l', 'g', 'i', 'j', 'e', 9, 0, - /* 3453 */ 'c', 'l', 'i', 'j', 'e', 9, 0, - /* 3460 */ 'c', 'r', 'j', 'e', 9, 0, - /* 3466 */ 'c', 'g', 'r', 'j', 'e', 9, 0, - /* 3473 */ 'c', 'l', 'g', 'r', 'j', 'e', 9, 0, - /* 3481 */ 'c', 'l', 'r', 'j', 'e', 9, 0, - /* 3488 */ 's', 't', 'c', 'k', 'e', 9, 0, - /* 3495 */ 'i', 's', 'k', 'e', 9, 0, - /* 3501 */ 's', 's', 'k', 'e', 9, 0, - /* 3507 */ 'v', 'm', 'a', 'l', 'e', 9, 0, - /* 3514 */ 'c', 'i', 'b', 'l', 'e', 9, 0, - /* 3521 */ 'c', 'g', 'i', 'b', 'l', 'e', 9, 0, - /* 3529 */ 'c', 'l', 'g', 'i', 'b', 'l', 'e', 9, 0, - /* 3538 */ 'c', 'l', 'i', 'b', 'l', 'e', 9, 0, - /* 3546 */ 'c', 'r', 'b', 'l', 'e', 9, 0, - /* 3553 */ 'c', 'g', 'r', 'b', 'l', 'e', 9, 0, - /* 3561 */ 'c', 'l', 'g', 'r', 'b', 'l', 'e', 9, 0, - /* 3570 */ 'c', 'l', 'r', 'b', 'l', 'e', 9, 0, - /* 3578 */ 'c', 'l', 'c', 'l', 'e', 9, 0, - /* 3585 */ 'l', 'o', 'c', 'l', 'e', 9, 0, - /* 3592 */ 's', 't', 'o', 'c', 'l', 'e', 9, 0, - /* 3600 */ 'm', 'v', 'c', 'l', 'e', 9, 0, - /* 3607 */ 's', 't', 'f', 'l', 'e', 9, 0, - /* 3614 */ 'l', 'o', 'c', 'g', 'l', 'e', 9, 0, - /* 3622 */ 's', 't', 'o', 'c', 'g', 'l', 'e', 9, 0, - /* 3631 */ 'j', 'g', 'l', 'e', 9, 0, - /* 3637 */ 'l', 'o', 'c', 'f', 'h', 'l', 'e', 9, 0, - /* 3646 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 'e', 9, 0, - /* 3656 */ 'b', 'i', 'l', 'e', 9, 0, - /* 3662 */ 'l', 'o', 'c', 'h', 'i', 'l', 'e', 9, 0, - /* 3671 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 'e', 9, 0, - /* 3681 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 'e', 9, 0, - /* 3691 */ 'c', 'i', 'j', 'l', 'e', 9, 0, - /* 3698 */ 'c', 'g', 'i', 'j', 'l', 'e', 9, 0, - /* 3706 */ 'c', 'l', 'g', 'i', 'j', 'l', 'e', 9, 0, - /* 3715 */ 'c', 'l', 'i', 'j', 'l', 'e', 9, 0, - /* 3723 */ 'c', 'r', 'j', 'l', 'e', 9, 0, - /* 3730 */ 'c', 'g', 'r', 'j', 'l', 'e', 9, 0, - /* 3738 */ 'c', 'l', 'g', 'r', 'j', 'l', 'e', 9, 0, - /* 3747 */ 'c', 'l', 'r', 'j', 'l', 'e', 9, 0, - /* 3755 */ 'v', 'm', 'l', 'e', 9, 0, - /* 3761 */ 'c', 'i', 'b', 'n', 'l', 'e', 9, 0, - /* 3769 */ 'c', 'g', 'i', 'b', 'n', 'l', 'e', 9, 0, - /* 3778 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 'e', 9, 0, - /* 3788 */ 'c', 'l', 'i', 'b', 'n', 'l', 'e', 9, 0, - /* 3797 */ 'c', 'r', 'b', 'n', 'l', 'e', 9, 0, - /* 3805 */ 'c', 'g', 'r', 'b', 'n', 'l', 'e', 9, 0, - /* 3814 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 'e', 9, 0, - /* 3824 */ 'c', 'l', 'r', 'b', 'n', 'l', 'e', 9, 0, - /* 3833 */ 'l', 'o', 'c', 'n', 'l', 'e', 9, 0, - /* 3841 */ 's', 't', 'o', 'c', 'n', 'l', 'e', 9, 0, - /* 3850 */ 'l', 'o', 'c', 'g', 'n', 'l', 'e', 9, 0, - /* 3859 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 'e', 9, 0, - /* 3869 */ 'j', 'g', 'n', 'l', 'e', 9, 0, - /* 3876 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 'e', 9, 0, - /* 3886 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 'e', 9, 0, - /* 3897 */ 'b', 'i', 'n', 'l', 'e', 9, 0, - /* 3904 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 'e', 9, 0, - /* 3914 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 'e', 9, 0, - /* 3925 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 'e', 9, 0, - /* 3936 */ 'c', 'i', 'j', 'n', 'l', 'e', 9, 0, - /* 3944 */ 'c', 'g', 'i', 'j', 'n', 'l', 'e', 9, 0, - /* 3953 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 'e', 9, 0, - /* 3963 */ 'c', 'l', 'i', 'j', 'n', 'l', 'e', 9, 0, - /* 3972 */ 'c', 'r', 'j', 'n', 'l', 'e', 9, 0, - /* 3980 */ 'c', 'g', 'r', 'j', 'n', 'l', 'e', 9, 0, - /* 3989 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 'e', 9, 0, - /* 3999 */ 'c', 'l', 'r', 'j', 'n', 'l', 'e', 9, 0, - /* 4008 */ 'l', 'o', 'c', 'r', 'n', 'l', 'e', 9, 0, - /* 4017 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 'e', 9, 0, - /* 4027 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 'e', 9, 0, - /* 4038 */ 'c', 'l', 'g', 't', 'n', 'l', 'e', 9, 0, - /* 4047 */ 'c', 'i', 't', 'n', 'l', 'e', 9, 0, - /* 4055 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 'e', 9, 0, - /* 4065 */ 'c', 'g', 'i', 't', 'n', 'l', 'e', 9, 0, - /* 4074 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 'e', 9, 0, - /* 4084 */ 'c', 'l', 't', 'n', 'l', 'e', 9, 0, - /* 4092 */ 'c', 'r', 't', 'n', 'l', 'e', 9, 0, - /* 4100 */ 'c', 'g', 'r', 't', 'n', 'l', 'e', 9, 0, - /* 4109 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 'e', 9, 0, - /* 4119 */ 'c', 'l', 'r', 't', 'n', 'l', 'e', 9, 0, - /* 4128 */ 'l', 'o', 'c', 'r', 'l', 'e', 9, 0, - /* 4136 */ 'l', 'o', 'c', 'g', 'r', 'l', 'e', 9, 0, - /* 4145 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 'e', 9, 0, - /* 4155 */ 'c', 'l', 'g', 't', 'l', 'e', 9, 0, - /* 4163 */ 'c', 'i', 't', 'l', 'e', 9, 0, - /* 4170 */ 'c', 'l', 'f', 'i', 't', 'l', 'e', 9, 0, - /* 4179 */ 'c', 'g', 'i', 't', 'l', 'e', 9, 0, - /* 4187 */ 'c', 'l', 'g', 'i', 't', 'l', 'e', 9, 0, - /* 4196 */ 'c', 'l', 't', 'l', 'e', 9, 0, - /* 4203 */ 'c', 'r', 't', 'l', 'e', 9, 0, - /* 4210 */ 'c', 'g', 'r', 't', 'l', 'e', 9, 0, - /* 4218 */ 'c', 'l', 'g', 'r', 't', 'l', 'e', 9, 0, - /* 4227 */ 'c', 'l', 'r', 't', 'l', 'e', 9, 0, - /* 4235 */ 'b', 'x', 'l', 'e', 9, 0, - /* 4241 */ 'b', 'r', 'x', 'l', 'e', 9, 0, - /* 4248 */ 'v', 'm', 'e', 9, 0, - /* 4253 */ 'c', 'i', 'b', 'n', 'e', 9, 0, - /* 4260 */ 'c', 'g', 'i', 'b', 'n', 'e', 9, 0, - /* 4268 */ 'c', 'l', 'g', 'i', 'b', 'n', 'e', 9, 0, - /* 4277 */ 'c', 'l', 'i', 'b', 'n', 'e', 9, 0, - /* 4285 */ 'c', 'r', 'b', 'n', 'e', 9, 0, - /* 4292 */ 'c', 'g', 'r', 'b', 'n', 'e', 9, 0, - /* 4300 */ 'c', 'l', 'g', 'r', 'b', 'n', 'e', 9, 0, - /* 4309 */ 'c', 'l', 'r', 'b', 'n', 'e', 9, 0, - /* 4317 */ 'l', 'o', 'c', 'n', 'e', 9, 0, - /* 4324 */ 's', 't', 'o', 'c', 'n', 'e', 9, 0, - /* 4332 */ 'v', 'f', 'e', 'n', 'e', 9, 0, - /* 4339 */ 'l', 'o', 'c', 'g', 'n', 'e', 9, 0, - /* 4347 */ 's', 't', 'o', 'c', 'g', 'n', 'e', 9, 0, - /* 4356 */ 'j', 'g', 'n', 'e', 9, 0, - /* 4362 */ 'l', 'o', 'c', 'f', 'h', 'n', 'e', 9, 0, - /* 4371 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'e', 9, 0, - /* 4381 */ 'b', 'i', 'n', 'e', 9, 0, - /* 4387 */ 'l', 'o', 'c', 'h', 'i', 'n', 'e', 9, 0, - /* 4396 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'e', 9, 0, - /* 4406 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'e', 9, 0, - /* 4416 */ 'c', 'i', 'j', 'n', 'e', 9, 0, - /* 4423 */ 'c', 'g', 'i', 'j', 'n', 'e', 9, 0, - /* 4431 */ 'c', 'l', 'g', 'i', 'j', 'n', 'e', 9, 0, - /* 4440 */ 'c', 'l', 'i', 'j', 'n', 'e', 9, 0, - /* 4448 */ 'c', 'r', 'j', 'n', 'e', 9, 0, - /* 4455 */ 'c', 'g', 'r', 'j', 'n', 'e', 9, 0, - /* 4463 */ 'c', 'l', 'g', 'r', 'j', 'n', 'e', 9, 0, - /* 4472 */ 'c', 'l', 'r', 'j', 'n', 'e', 9, 0, - /* 4480 */ 'v', 'o', 'n', 'e', 9, 0, - /* 4486 */ 'l', 'o', 'c', 'r', 'n', 'e', 9, 0, - /* 4494 */ 'l', 'o', 'c', 'g', 'r', 'n', 'e', 9, 0, - /* 4503 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'e', 9, 0, - /* 4513 */ 'c', 'l', 'g', 't', 'n', 'e', 9, 0, - /* 4521 */ 'c', 'i', 't', 'n', 'e', 9, 0, - /* 4528 */ 'c', 'l', 'f', 'i', 't', 'n', 'e', 9, 0, - /* 4537 */ 'c', 'g', 'i', 't', 'n', 'e', 9, 0, - /* 4545 */ 'c', 'l', 'g', 'i', 't', 'n', 'e', 9, 0, - /* 4554 */ 'c', 'l', 't', 'n', 'e', 9, 0, - /* 4561 */ 'c', 'r', 't', 'n', 'e', 9, 0, - /* 4568 */ 'c', 'g', 'r', 't', 'n', 'e', 9, 0, - /* 4576 */ 'c', 'l', 'g', 'r', 't', 'n', 'e', 9, 0, - /* 4585 */ 'c', 'l', 'r', 't', 'n', 'e', 9, 0, - /* 4593 */ 's', 'q', 'e', 9, 0, - /* 4598 */ 'l', 'o', 'c', 'r', 'e', 9, 0, - /* 4605 */ 'l', 'o', 'c', 'g', 'r', 'e', 9, 0, - /* 4613 */ 'l', 'o', 'c', 'f', 'h', 'r', 'e', 9, 0, - /* 4622 */ 't', 'r', 't', 'r', 'e', 9, 0, - /* 4629 */ 'm', 's', 'e', 9, 0, - /* 4634 */ 'c', 'u', 's', 'e', 9, 0, - /* 4640 */ 'i', 'd', 't', 'e', 9, 0, - /* 4646 */ 'c', 'r', 'd', 't', 'e', 9, 0, - /* 4653 */ 'c', 'l', 'g', 't', 'e', 9, 0, - /* 4660 */ 'c', 'i', 't', 'e', 9, 0, - /* 4666 */ 'c', 'l', 'f', 'i', 't', 'e', 9, 0, - /* 4674 */ 'c', 'g', 'i', 't', 'e', 9, 0, - /* 4681 */ 'c', 'l', 'g', 'i', 't', 'e', 9, 0, - /* 4689 */ 'c', 'l', 't', 'e', 9, 0, - /* 4695 */ 'i', 'p', 't', 'e', 9, 0, - /* 4701 */ 'c', 'r', 't', 'e', 9, 0, - /* 4707 */ 'c', 'g', 'r', 't', 'e', 9, 0, - /* 4714 */ 'c', 'l', 'g', 'r', 't', 'e', 9, 0, - /* 4722 */ 'c', 'l', 'r', 't', 'e', 9, 0, - /* 4729 */ 't', 'r', 't', 'e', 9, 0, - /* 4735 */ 's', 't', 'e', 9, 0, - /* 4740 */ 'l', 'p', 's', 'w', 'e', 9, 0, - /* 4747 */ 'l', 'x', 'e', 9, 0, - /* 4752 */ 'v', 'g', 'f', 'm', 'a', 'f', 9, 0, - /* 4760 */ 'v', 'e', 's', 'r', 'a', 'f', 9, 0, - /* 4768 */ 'v', 'a', 'f', 9, 0, - /* 4773 */ 's', 'a', 'c', 'f', 9, 0, - /* 4779 */ 'v', 'a', 'c', 'c', 'f', 9, 0, - /* 4786 */ 'v', 'e', 'c', 'f', 9, 0, - /* 4792 */ 'v', 'l', 'c', 'f', 9, 0, - /* 4798 */ 'v', 's', 't', 'r', 'c', 'f', 9, 0, - /* 4806 */ 'v', 'f', 'a', 'e', 'f', 9, 0, - /* 4813 */ 'v', 'm', 'a', 'e', 'f', 9, 0, - /* 4820 */ 'v', 's', 'c', 'e', 'f', 9, 0, - /* 4827 */ 'v', 'f', 'e', 'e', 'f', 9, 0, - /* 4834 */ 'v', 'g', 'e', 'f', 9, 0, - /* 4840 */ 'v', 'm', 'a', 'l', 'e', 'f', 9, 0, - /* 4848 */ 'v', 'm', 'l', 'e', 'f', 9, 0, - /* 4855 */ 'v', 'l', 'e', 'f', 9, 0, - /* 4861 */ 'v', 'm', 'e', 'f', 9, 0, - /* 4867 */ 'v', 'f', 'e', 'n', 'e', 'f', 9, 0, - /* 4875 */ 'v', 's', 't', 'e', 'f', 9, 0, - /* 4882 */ 'a', 'g', 'f', 9, 0, - /* 4887 */ 'c', 'g', 'f', 9, 0, - /* 4892 */ 'v', 's', 'e', 'g', 'f', 9, 0, - /* 4899 */ 'a', 'l', 'g', 'f', 9, 0, - /* 4905 */ 'c', 'l', 'g', 'f', 9, 0, - /* 4911 */ 'l', 'l', 'g', 'f', 9, 0, - /* 4917 */ 's', 'l', 'g', 'f', 9, 0, - /* 4923 */ 'v', 's', 'u', 'm', 'g', 'f', 9, 0, - /* 4931 */ 'l', 'l', 'z', 'r', 'g', 'f', 9, 0, - /* 4939 */ 'd', 's', 'g', 'f', 9, 0, - /* 4945 */ 'm', 's', 'g', 'f', 9, 0, - /* 4951 */ 'l', 't', 'g', 'f', 9, 0, - /* 4957 */ 'v', 'a', 'v', 'g', 'f', 9, 0, - /* 4964 */ 'v', 'l', 'v', 'g', 'f', 9, 0, - /* 4971 */ 'v', 'm', 'a', 'h', 'f', 9, 0, - /* 4978 */ 'v', 'c', 'h', 'f', 9, 0, - /* 4984 */ 'i', 'i', 'h', 'f', 9, 0, - /* 4990 */ 'l', 'l', 'i', 'h', 'f', 9, 0, - /* 4997 */ 'n', 'i', 'h', 'f', 9, 0, - /* 5003 */ 'o', 'i', 'h', 'f', 9, 0, - /* 5009 */ 'x', 'i', 'h', 'f', 9, 0, - /* 5015 */ 'v', 'm', 'a', 'l', 'h', 'f', 9, 0, - /* 5023 */ 'c', 'l', 'h', 'f', 9, 0, - /* 5029 */ 'v', 'm', 'l', 'h', 'f', 9, 0, - /* 5036 */ 'v', 'u', 'p', 'l', 'h', 'f', 9, 0, - /* 5044 */ 'v', 'm', 'h', 'f', 9, 0, - /* 5050 */ 'v', 'u', 'p', 'h', 'f', 9, 0, - /* 5057 */ 'v', 'm', 'r', 'h', 'f', 9, 0, - /* 5064 */ 'v', 's', 'c', 'b', 'i', 'f', 9, 0, - /* 5072 */ 'v', 'l', 'e', 'i', 'f', 9, 0, - /* 5079 */ 'v', 'r', 'e', 'p', 'i', 'f', 9, 0, - /* 5087 */ 's', 't', 'c', 'k', 'f', 9, 0, - /* 5094 */ 'v', 'p', 'k', 'f', 9, 0, - /* 5100 */ 'v', 'm', 'a', 'l', 'f', 9, 0, - /* 5107 */ 'v', 'e', 'c', 'l', 'f', 9, 0, - /* 5114 */ 'v', 'a', 'v', 'g', 'l', 'f', 9, 0, - /* 5122 */ 'v', 'c', 'h', 'l', 'f', 9, 0, - /* 5129 */ 'i', 'i', 'l', 'f', 9, 0, - /* 5135 */ 'l', 'l', 'i', 'l', 'f', 9, 0, - /* 5142 */ 'n', 'i', 'l', 'f', 9, 0, - /* 5148 */ 'o', 'i', 'l', 'f', 9, 0, - /* 5154 */ 'x', 'i', 'l', 'f', 9, 0, - /* 5160 */ 'v', 'u', 'p', 'l', 'l', 'f', 9, 0, - /* 5168 */ 'v', 'e', 'r', 'l', 'l', 'f', 9, 0, - /* 5176 */ 'v', 'm', 'l', 'f', 9, 0, - /* 5182 */ 'v', 'm', 'n', 'l', 'f', 9, 0, - /* 5189 */ 'v', 'u', 'p', 'l', 'f', 9, 0, - /* 5196 */ 'v', 'm', 'r', 'l', 'f', 9, 0, - /* 5203 */ 'v', 'e', 's', 'r', 'l', 'f', 9, 0, - /* 5211 */ 'v', 'e', 's', 'l', 'f', 9, 0, - /* 5218 */ 'v', 'm', 'x', 'l', 'f', 9, 0, - /* 5225 */ 'v', 'l', 'l', 'e', 'z', 'l', 'f', 9, 0, - /* 5234 */ 'v', 'g', 'f', 'm', 'f', 9, 0, - /* 5241 */ 'p', 'f', 'm', 'f', 9, 0, - /* 5247 */ 'v', 'g', 'm', 'f', 9, 0, - /* 5253 */ 'v', 'e', 'r', 'i', 'm', 'f', 9, 0, - /* 5261 */ 'k', 'm', 'f', 9, 0, - /* 5266 */ 'v', 'm', 'n', 'f', 9, 0, - /* 5272 */ 'v', 'm', 'a', 'o', 'f', 9, 0, - /* 5279 */ 'v', 'm', 'a', 'l', 'o', 'f', 9, 0, - /* 5287 */ 'v', 'm', 'l', 'o', 'f', 9, 0, - /* 5294 */ 'v', 'm', 'o', 'f', 9, 0, - /* 5300 */ 'v', 'l', 'r', 'e', 'p', 'f', 9, 0, - /* 5308 */ 'v', 'r', 'e', 'p', 'f', 9, 0, - /* 5315 */ 'v', 'l', 'p', 'f', 9, 0, - /* 5321 */ 'v', 'c', 'e', 'q', 'f', 9, 0, - /* 5328 */ 'v', 's', 'u', 'm', 'q', 'f', 9, 0, - /* 5336 */ 'v', 'i', 's', 't', 'r', 'f', 9, 0, - /* 5344 */ 'l', 'z', 'r', 'f', 9, 0, - /* 5350 */ 'v', 'p', 'k', 's', 'f', 9, 0, - /* 5357 */ 'v', 'p', 'k', 'l', 's', 'f', 9, 0, - /* 5365 */ 'v', 's', 'f', 9, 0, - /* 5370 */ 'v', 'p', 'o', 'p', 'c', 't', 'f', 9, 0, - /* 5379 */ 'p', 't', 'f', 9, 0, - /* 5384 */ 'c', 'u', 'u', 't', 'f', 9, 0, - /* 5391 */ 'v', 'e', 's', 'r', 'a', 'v', 'f', 9, 0, - /* 5400 */ 'v', 'l', 'g', 'v', 'f', 9, 0, - /* 5407 */ 'v', 'e', 'r', 'l', 'l', 'v', 'f', 9, 0, - /* 5416 */ 'v', 'e', 's', 'r', 'l', 'v', 'f', 9, 0, - /* 5425 */ 'v', 'e', 's', 'l', 'v', 'f', 9, 0, - /* 5433 */ 'v', 'm', 'x', 'f', 9, 0, - /* 5439 */ 'v', 's', 't', 'r', 'c', 'z', 'f', 9, 0, - /* 5448 */ 'v', 'f', 'a', 'e', 'z', 'f', 9, 0, - /* 5456 */ 'v', 'f', 'e', 'e', 'z', 'f', 9, 0, - /* 5464 */ 'v', 'l', 'l', 'e', 'z', 'f', 9, 0, - /* 5472 */ 'v', 'f', 'e', 'n', 'e', 'z', 'f', 9, 0, - /* 5481 */ 'v', 'c', 'l', 'z', 'f', 9, 0, - /* 5488 */ 'v', 'c', 't', 'z', 'f', 9, 0, - /* 5495 */ 'l', 'a', 'a', 'g', 9, 0, - /* 5501 */ 'e', 'c', 'a', 'g', 9, 0, - /* 5507 */ 'd', 'i', 'a', 'g', 9, 0, - /* 5513 */ 's', 'l', 'a', 'g', 9, 0, - /* 5519 */ 'v', 'g', 'f', 'm', 'a', 'g', 9, 0, - /* 5527 */ 'l', 'r', 'a', 'g', 9, 0, - /* 5533 */ 'v', 'e', 's', 'r', 'a', 'g', 9, 0, - /* 5541 */ 's', 't', 'r', 'a', 'g', 9, 0, - /* 5548 */ 'l', 'u', 'r', 'a', 'g', 9, 0, - /* 5555 */ 'v', 'a', 'g', 9, 0, - /* 5560 */ 's', 'l', 'b', 'g', 9, 0, - /* 5566 */ 'r', 'i', 's', 'b', 'g', 9, 0, - /* 5573 */ 'r', 'n', 's', 'b', 'g', 9, 0, - /* 5580 */ 'r', 'o', 's', 'b', 'g', 9, 0, - /* 5587 */ 'r', 'x', 's', 'b', 'g', 9, 0, - /* 5594 */ 'v', 'c', 'v', 'b', 'g', 9, 0, - /* 5601 */ 't', 'r', 'a', 'c', 'g', 9, 0, - /* 5608 */ 'v', 'a', 'c', 'c', 'g', 9, 0, - /* 5615 */ 'v', 'e', 'c', 'g', 9, 0, - /* 5621 */ 'a', 'l', 'c', 'g', 9, 0, - /* 5627 */ 'v', 'l', 'c', 'g', 9, 0, - /* 5633 */ 'l', 'o', 'c', 'g', 9, 0, - /* 5639 */ 's', 't', 'o', 'c', 'g', 9, 0, - /* 5646 */ 'v', 'c', 'd', 'g', 9, 0, - /* 5652 */ 'l', 'p', 'd', 'g', 9, 0, - /* 5658 */ 'v', 'c', 'v', 'd', 'g', 9, 0, - /* 5665 */ 'v', 's', 'c', 'e', 'g', 9, 0, - /* 5672 */ 'v', 'g', 'e', 'g', 9, 0, - /* 5678 */ 'v', 'l', 'e', 'g', 9, 0, - /* 5684 */ 'b', 'x', 'l', 'e', 'g', 9, 0, - /* 5691 */ 'e', 'r', 'e', 'g', 9, 0, - /* 5697 */ 'v', 's', 'e', 'g', 9, 0, - /* 5703 */ 'v', 's', 't', 'e', 'g', 9, 0, - /* 5710 */ 'e', 'r', 'e', 'g', 'g', 9, 0, - /* 5717 */ 'l', 'g', 'g', 9, 0, - /* 5722 */ 'v', 'a', 'v', 'g', 'g', 9, 0, - /* 5729 */ 'v', 'l', 'v', 'g', 'g', 9, 0, - /* 5736 */ 'r', 'i', 's', 'b', 'h', 'g', 9, 0, - /* 5744 */ 'v', 'c', 'h', 'g', 9, 0, - /* 5750 */ 'v', 'm', 'r', 'h', 'g', 9, 0, - /* 5757 */ 'b', 'x', 'h', 'g', 9, 0, - /* 5763 */ 'b', 'r', 'x', 'h', 'g', 9, 0, - /* 5770 */ 'v', 's', 'c', 'b', 'i', 'g', 9, 0, - /* 5778 */ 'v', 'l', 'e', 'i', 'g', 9, 0, - /* 5785 */ 'v', 'r', 'e', 'p', 'i', 'g', 9, 0, - /* 5793 */ 'j', 'g', 9, 0, - /* 5797 */ 'v', 'p', 'k', 'g', 9, 0, - /* 5803 */ 'l', 'a', 'a', 'l', 'g', 9, 0, - /* 5810 */ 'r', 'i', 's', 'b', 'l', 'g', 9, 0, - /* 5818 */ 'v', 'e', 'c', 'l', 'g', 9, 0, - /* 5825 */ 'v', 'c', 'd', 'l', 'g', 9, 0, - /* 5832 */ 'v', 'a', 'v', 'g', 'l', 'g', 9, 0, - /* 5840 */ 'v', 'c', 'h', 'l', 'g', 9, 0, - /* 5847 */ 'v', 'e', 'r', 'l', 'l', 'g', 9, 0, - /* 5855 */ 's', 'l', 'l', 'g', 9, 0, - /* 5861 */ 'm', 'l', 'g', 9, 0, - /* 5866 */ 'v', 'm', 'n', 'l', 'g', 9, 0, - /* 5873 */ 'v', 'm', 'r', 'l', 'g', 9, 0, - /* 5880 */ 'v', 'e', 's', 'r', 'l', 'g', 9, 0, - /* 5888 */ 'v', 'e', 's', 'l', 'g', 9, 0, - /* 5895 */ 'v', 'm', 's', 'l', 'g', 9, 0, - /* 5902 */ 'l', 'c', 't', 'l', 'g', 9, 0, - /* 5909 */ 'v', 'm', 'x', 'l', 'g', 9, 0, - /* 5916 */ 'b', 'r', 'x', 'l', 'g', 9, 0, - /* 5923 */ 'v', 'g', 'f', 'm', 'g', 9, 0, - /* 5930 */ 'v', 'g', 'm', 'g', 9, 0, - /* 5936 */ 'v', 'e', 'r', 'i', 'm', 'g', 9, 0, - /* 5944 */ 'l', 'm', 'g', 9, 0, - /* 5949 */ 's', 't', 'm', 'g', 9, 0, - /* 5955 */ 'v', 's', 'u', 'm', 'g', 9, 0, - /* 5962 */ 'l', 'a', 'n', 'g', 9, 0, - /* 5968 */ 'v', 'm', 'n', 'g', 9, 0, - /* 5974 */ 'l', 'a', 'o', 'g', 9, 0, - /* 5980 */ 'v', 'l', 'r', 'e', 'p', 'g', 9, 0, - /* 5988 */ 'v', 'r', 'e', 'p', 'g', 9, 0, - /* 5995 */ 'v', 'l', 'p', 'g', 9, 0, - /* 6001 */ 'c', 's', 'p', 'g', 9, 0, - /* 6007 */ 'm', 'v', 'p', 'g', 9, 0, - /* 6013 */ 'v', 'c', 'e', 'q', 'g', 9, 0, - /* 6020 */ 'v', 's', 'u', 'm', 'q', 'g', 9, 0, - /* 6028 */ 's', 't', 'u', 'r', 'g', 9, 0, - /* 6035 */ 'l', 'z', 'r', 'g', 9, 0, - /* 6041 */ 'b', 's', 'g', 9, 0, - /* 6046 */ 'c', 's', 'g', 9, 0, - /* 6051 */ 'c', 'd', 's', 'g', 9, 0, - /* 6057 */ 'l', 'l', 'g', 'f', 's', 'g', 9, 0, - /* 6065 */ 'v', 'p', 'k', 's', 'g', 9, 0, - /* 6072 */ 'v', 'p', 'k', 'l', 's', 'g', 9, 0, - /* 6080 */ 'm', 's', 'g', 9, 0, - /* 6085 */ 'v', 's', 'g', 9, 0, - /* 6090 */ 'b', 'c', 't', 'g', 9, 0, - /* 6096 */ 'e', 'c', 't', 'g', 9, 0, - /* 6102 */ 'v', 'p', 'o', 'p', 'c', 't', 'g', 9, 0, - /* 6111 */ 'b', 'r', 'c', 't', 'g', 9, 0, - /* 6118 */ 's', 't', 'c', 't', 'g', 9, 0, - /* 6125 */ 'l', 't', 'g', 9, 0, - /* 6130 */ 'n', 't', 's', 't', 'g', 9, 0, - /* 6137 */ 'v', 'e', 's', 'r', 'a', 'v', 'g', 9, 0, - /* 6146 */ 'v', 'a', 'v', 'g', 9, 0, - /* 6152 */ 'v', 'l', 'g', 'v', 'g', 9, 0, - /* 6159 */ 'v', 'e', 'r', 'l', 'l', 'v', 'g', 9, 0, - /* 6168 */ 'v', 'e', 's', 'r', 'l', 'v', 'g', 9, 0, - /* 6177 */ 'v', 'e', 's', 'l', 'v', 'g', 9, 0, - /* 6185 */ 'v', 'l', 'v', 'g', 9, 0, - /* 6191 */ 'l', 'r', 'v', 'g', 9, 0, - /* 6197 */ 's', 't', 'r', 'v', 'g', 9, 0, - /* 6204 */ 'l', 'a', 'x', 'g', 9, 0, - /* 6210 */ 'v', 'm', 'x', 'g', 9, 0, - /* 6216 */ 'v', 'l', 'l', 'e', 'z', 'g', 9, 0, - /* 6224 */ 'v', 'c', 'l', 'z', 'g', 9, 0, - /* 6231 */ 'v', 'c', 't', 'z', 'g', 9, 0, - /* 6238 */ 'v', 'g', 'f', 'm', 'a', 'h', 9, 0, - /* 6246 */ 'v', 'm', 'a', 'h', 9, 0, - /* 6252 */ 'v', 'e', 's', 'r', 'a', 'h', 9, 0, - /* 6260 */ 'v', 'a', 'h', 9, 0, - /* 6265 */ 'c', 'i', 'b', 'h', 9, 0, - /* 6271 */ 'c', 'g', 'i', 'b', 'h', 9, 0, - /* 6278 */ 'c', 'l', 'g', 'i', 'b', 'h', 9, 0, - /* 6286 */ 'c', 'l', 'i', 'b', 'h', 9, 0, - /* 6293 */ 'l', 'b', 'h', 9, 0, - /* 6298 */ 'c', 'r', 'b', 'h', 9, 0, - /* 6304 */ 'c', 'g', 'r', 'b', 'h', 9, 0, - /* 6311 */ 'c', 'l', 'g', 'r', 'b', 'h', 9, 0, - /* 6319 */ 'c', 'l', 'r', 'b', 'h', 9, 0, - /* 6326 */ 'v', 'a', 'c', 'c', 'h', 9, 0, - /* 6333 */ 'v', 'e', 'c', 'h', 9, 0, - /* 6339 */ 'v', 'f', 'c', 'h', 9, 0, - /* 6345 */ 'l', 'l', 'c', 'h', 9, 0, - /* 6351 */ 'v', 'l', 'c', 'h', 9, 0, - /* 6357 */ 'l', 'o', 'c', 'h', 9, 0, - /* 6363 */ 's', 't', 'o', 'c', 'h', 9, 0, - /* 6370 */ 'v', 's', 't', 'r', 'c', 'h', 9, 0, - /* 6378 */ 'm', 's', 'c', 'h', 9, 0, - /* 6384 */ 's', 's', 'c', 'h', 9, 0, - /* 6390 */ 's', 't', 's', 'c', 'h', 9, 0, - /* 6397 */ 's', 't', 'c', 'h', 9, 0, - /* 6403 */ 'v', 'c', 'h', 9, 0, - /* 6408 */ 'v', 'f', 'a', 'e', 'h', 9, 0, - /* 6415 */ 'v', 'm', 'a', 'e', 'h', 9, 0, - /* 6422 */ 'v', 'f', 'e', 'e', 'h', 9, 0, - /* 6429 */ 'v', 'm', 'a', 'l', 'e', 'h', 9, 0, - /* 6437 */ 'v', 'm', 'l', 'e', 'h', 9, 0, - /* 6444 */ 'v', 'l', 'e', 'h', 9, 0, - /* 6450 */ 'v', 'm', 'e', 'h', 9, 0, - /* 6456 */ 'v', 'f', 'e', 'n', 'e', 'h', 9, 0, - /* 6464 */ 'v', 's', 't', 'e', 'h', 9, 0, - /* 6471 */ 'l', 'o', 'c', 'f', 'h', 9, 0, - /* 6478 */ 's', 't', 'o', 'c', 'f', 'h', 9, 0, - /* 6486 */ 'l', 'f', 'h', 9, 0, - /* 6491 */ 's', 't', 'f', 'h', 9, 0, - /* 6497 */ 'a', 'g', 'h', 9, 0, - /* 6502 */ 'l', 'o', 'c', 'g', 'h', 9, 0, - /* 6509 */ 's', 't', 'o', 'c', 'g', 'h', 9, 0, - /* 6517 */ 'v', 's', 'e', 'g', 'h', 9, 0, - /* 6524 */ 'j', 'g', 'h', 9, 0, - /* 6529 */ 'l', 'l', 'g', 'h', 9, 0, - /* 6535 */ 'v', 's', 'u', 'm', 'g', 'h', 9, 0, - /* 6543 */ 's', 'g', 'h', 9, 0, - /* 6548 */ 'v', 'a', 'v', 'g', 'h', 9, 0, - /* 6555 */ 'v', 'l', 'v', 'g', 'h', 9, 0, - /* 6562 */ 'v', 'm', 'a', 'h', 'h', 9, 0, - /* 6569 */ 'v', 'c', 'h', 'h', 9, 0, - /* 6575 */ 'l', 'o', 'c', 'f', 'h', 'h', 9, 0, - /* 6583 */ 's', 't', 'o', 'c', 'f', 'h', 'h', 9, 0, - /* 6592 */ 'i', 'i', 'h', 'h', 9, 0, - /* 6598 */ 'l', 'l', 'i', 'h', 'h', 9, 0, - /* 6605 */ 'n', 'i', 'h', 'h', 9, 0, - /* 6611 */ 'o', 'i', 'h', 'h', 9, 0, - /* 6617 */ 'v', 'm', 'a', 'l', 'h', 'h', 9, 0, - /* 6625 */ 'l', 'l', 'h', 'h', 9, 0, - /* 6631 */ 'v', 'm', 'l', 'h', 'h', 9, 0, - /* 6638 */ 'v', 'u', 'p', 'l', 'h', 'h', 9, 0, - /* 6646 */ 't', 'm', 'h', 'h', 9, 0, - /* 6652 */ 'v', 'm', 'h', 'h', 9, 0, - /* 6658 */ 'v', 'u', 'p', 'h', 'h', 9, 0, - /* 6665 */ 'v', 'm', 'r', 'h', 'h', 9, 0, - /* 6672 */ 's', 't', 'h', 'h', 9, 0, - /* 6678 */ 'a', 'i', 'h', 9, 0, - /* 6683 */ 'v', 's', 'c', 'b', 'i', 'h', 9, 0, - /* 6691 */ 'c', 'i', 'h', 9, 0, - /* 6696 */ 'v', 'l', 'e', 'i', 'h', 9, 0, - /* 6703 */ 'l', 'o', 'c', 'h', 'i', 'h', 9, 0, - /* 6711 */ 'l', 'o', 'c', 'g', 'h', 'i', 'h', 9, 0, - /* 6720 */ 'l', 'o', 'c', 'h', 'h', 'i', 'h', 9, 0, - /* 6729 */ 'c', 'l', 'i', 'h', 9, 0, - /* 6735 */ 'v', 'r', 'e', 'p', 'i', 'h', 9, 0, - /* 6743 */ 'a', 'l', 's', 'i', 'h', 9, 0, - /* 6750 */ 'c', 'i', 'j', 'h', 9, 0, - /* 6756 */ 'c', 'g', 'i', 'j', 'h', 9, 0, - /* 6763 */ 'c', 'l', 'g', 'i', 'j', 'h', 9, 0, - /* 6771 */ 'c', 'l', 'i', 'j', 'h', 9, 0, - /* 6778 */ 'c', 'r', 'j', 'h', 9, 0, - /* 6784 */ 'c', 'g', 'r', 'j', 'h', 9, 0, - /* 6791 */ 'c', 'l', 'g', 'r', 'j', 'h', 9, 0, - /* 6799 */ 'c', 'l', 'r', 'j', 'h', 9, 0, - /* 6806 */ 'v', 'p', 'k', 'h', 9, 0, - /* 6812 */ 'v', 'm', 'a', 'l', 'h', 9, 0, - /* 6819 */ 'c', 'i', 'b', 'l', 'h', 9, 0, - /* 6826 */ 'c', 'g', 'i', 'b', 'l', 'h', 9, 0, - /* 6834 */ 'c', 'l', 'g', 'i', 'b', 'l', 'h', 9, 0, - /* 6843 */ 'c', 'l', 'i', 'b', 'l', 'h', 9, 0, - /* 6851 */ 'c', 'r', 'b', 'l', 'h', 9, 0, - /* 6858 */ 'c', 'g', 'r', 'b', 'l', 'h', 9, 0, - /* 6866 */ 'c', 'l', 'g', 'r', 'b', 'l', 'h', 9, 0, - /* 6875 */ 'c', 'l', 'r', 'b', 'l', 'h', 9, 0, - /* 6883 */ 'v', 'e', 'c', 'l', 'h', 9, 0, - /* 6890 */ 'l', 'o', 'c', 'l', 'h', 9, 0, - /* 6897 */ 's', 't', 'o', 'c', 'l', 'h', 9, 0, - /* 6905 */ 'l', 'o', 'c', 'g', 'l', 'h', 9, 0, - /* 6913 */ 's', 't', 'o', 'c', 'g', 'l', 'h', 9, 0, - /* 6922 */ 'j', 'g', 'l', 'h', 9, 0, - /* 6928 */ 'v', 'a', 'v', 'g', 'l', 'h', 9, 0, - /* 6936 */ 'v', 'c', 'h', 'l', 'h', 9, 0, - /* 6943 */ 'l', 'o', 'c', 'f', 'h', 'l', 'h', 9, 0, - /* 6952 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 'h', 9, 0, - /* 6962 */ 'b', 'i', 'l', 'h', 9, 0, - /* 6968 */ 'l', 'o', 'c', 'h', 'i', 'l', 'h', 9, 0, - /* 6977 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 'h', 9, 0, - /* 6987 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 'h', 9, 0, - /* 6997 */ 'i', 'i', 'l', 'h', 9, 0, - /* 7003 */ 'l', 'l', 'i', 'l', 'h', 9, 0, - /* 7010 */ 'n', 'i', 'l', 'h', 9, 0, - /* 7016 */ 'o', 'i', 'l', 'h', 9, 0, - /* 7022 */ 'c', 'i', 'j', 'l', 'h', 9, 0, - /* 7029 */ 'c', 'g', 'i', 'j', 'l', 'h', 9, 0, - /* 7037 */ 'c', 'l', 'g', 'i', 'j', 'l', 'h', 9, 0, - /* 7046 */ 'c', 'l', 'i', 'j', 'l', 'h', 9, 0, - /* 7054 */ 'c', 'r', 'j', 'l', 'h', 9, 0, - /* 7061 */ 'c', 'g', 'r', 'j', 'l', 'h', 9, 0, - /* 7069 */ 'c', 'l', 'g', 'r', 'j', 'l', 'h', 9, 0, - /* 7078 */ 'c', 'l', 'r', 'j', 'l', 'h', 9, 0, - /* 7086 */ 'v', 'u', 'p', 'l', 'l', 'h', 9, 0, - /* 7094 */ 'v', 'e', 'r', 'l', 'l', 'h', 9, 0, - /* 7102 */ 't', 'm', 'l', 'h', 9, 0, - /* 7108 */ 'v', 'm', 'l', 'h', 9, 0, - /* 7114 */ 'c', 'i', 'b', 'n', 'l', 'h', 9, 0, - /* 7122 */ 'c', 'g', 'i', 'b', 'n', 'l', 'h', 9, 0, - /* 7131 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 'h', 9, 0, - /* 7141 */ 'c', 'l', 'i', 'b', 'n', 'l', 'h', 9, 0, - /* 7150 */ 'c', 'r', 'b', 'n', 'l', 'h', 9, 0, - /* 7158 */ 'c', 'g', 'r', 'b', 'n', 'l', 'h', 9, 0, - /* 7167 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 'h', 9, 0, - /* 7177 */ 'c', 'l', 'r', 'b', 'n', 'l', 'h', 9, 0, - /* 7186 */ 'l', 'o', 'c', 'n', 'l', 'h', 9, 0, - /* 7194 */ 's', 't', 'o', 'c', 'n', 'l', 'h', 9, 0, - /* 7203 */ 'l', 'o', 'c', 'g', 'n', 'l', 'h', 9, 0, - /* 7212 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 'h', 9, 0, - /* 7222 */ 'j', 'g', 'n', 'l', 'h', 9, 0, - /* 7229 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 'h', 9, 0, - /* 7239 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 'h', 9, 0, - /* 7250 */ 'b', 'i', 'n', 'l', 'h', 9, 0, - /* 7257 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 'h', 9, 0, - /* 7267 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 'h', 9, 0, - /* 7278 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 'h', 9, 0, - /* 7289 */ 'c', 'i', 'j', 'n', 'l', 'h', 9, 0, - /* 7297 */ 'c', 'g', 'i', 'j', 'n', 'l', 'h', 9, 0, - /* 7306 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 'h', 9, 0, - /* 7316 */ 'c', 'l', 'i', 'j', 'n', 'l', 'h', 9, 0, - /* 7325 */ 'c', 'r', 'j', 'n', 'l', 'h', 9, 0, - /* 7333 */ 'c', 'g', 'r', 'j', 'n', 'l', 'h', 9, 0, - /* 7342 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 'h', 9, 0, - /* 7352 */ 'c', 'l', 'r', 'j', 'n', 'l', 'h', 9, 0, - /* 7361 */ 'v', 'm', 'n', 'l', 'h', 9, 0, - /* 7368 */ 'l', 'o', 'c', 'r', 'n', 'l', 'h', 9, 0, - /* 7377 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 'h', 9, 0, - /* 7387 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 'h', 9, 0, - /* 7398 */ 'c', 'l', 'g', 't', 'n', 'l', 'h', 9, 0, - /* 7407 */ 'c', 'i', 't', 'n', 'l', 'h', 9, 0, - /* 7415 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 'h', 9, 0, - /* 7425 */ 'c', 'g', 'i', 't', 'n', 'l', 'h', 9, 0, - /* 7434 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 'h', 9, 0, - /* 7444 */ 'c', 'l', 't', 'n', 'l', 'h', 9, 0, - /* 7452 */ 'c', 'r', 't', 'n', 'l', 'h', 9, 0, - /* 7460 */ 'c', 'g', 'r', 't', 'n', 'l', 'h', 9, 0, - /* 7469 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 'h', 9, 0, - /* 7479 */ 'c', 'l', 'r', 't', 'n', 'l', 'h', 9, 0, - /* 7488 */ 'v', 'u', 'p', 'l', 'h', 9, 0, - /* 7495 */ 'l', 'o', 'c', 'r', 'l', 'h', 9, 0, - /* 7503 */ 'l', 'o', 'c', 'g', 'r', 'l', 'h', 9, 0, - /* 7512 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 'h', 9, 0, - /* 7522 */ 'v', 'm', 'r', 'l', 'h', 9, 0, - /* 7529 */ 'v', 'e', 's', 'r', 'l', 'h', 9, 0, - /* 7537 */ 'v', 'e', 's', 'l', 'h', 9, 0, - /* 7544 */ 'c', 'l', 'g', 't', 'l', 'h', 9, 0, - /* 7552 */ 'c', 'i', 't', 'l', 'h', 9, 0, - /* 7559 */ 'c', 'l', 'f', 'i', 't', 'l', 'h', 9, 0, - /* 7568 */ 'c', 'g', 'i', 't', 'l', 'h', 9, 0, - /* 7576 */ 'c', 'l', 'g', 'i', 't', 'l', 'h', 9, 0, - /* 7585 */ 'c', 'l', 't', 'l', 'h', 9, 0, - /* 7592 */ 'c', 'r', 't', 'l', 'h', 9, 0, - /* 7599 */ 'c', 'g', 'r', 't', 'l', 'h', 9, 0, - /* 7607 */ 'c', 'l', 'g', 'r', 't', 'l', 'h', 9, 0, - /* 7616 */ 'c', 'l', 'r', 't', 'l', 'h', 9, 0, - /* 7624 */ 'v', 'm', 'x', 'l', 'h', 9, 0, - /* 7631 */ 'i', 'c', 'm', 'h', 9, 0, - /* 7637 */ 's', 't', 'c', 'm', 'h', 9, 0, - /* 7644 */ 'v', 'g', 'f', 'm', 'h', 9, 0, - /* 7651 */ 'v', 'g', 'm', 'h', 9, 0, - /* 7657 */ 'v', 'e', 'r', 'i', 'm', 'h', 9, 0, - /* 7665 */ 'c', 'l', 'm', 'h', 9, 0, - /* 7671 */ 's', 't', 'm', 'h', 9, 0, - /* 7677 */ 'v', 's', 'u', 'm', 'h', 9, 0, - /* 7684 */ 'v', 'm', 'h', 9, 0, - /* 7689 */ 'c', 'i', 'b', 'n', 'h', 9, 0, - /* 7696 */ 'c', 'g', 'i', 'b', 'n', 'h', 9, 0, - /* 7704 */ 'c', 'l', 'g', 'i', 'b', 'n', 'h', 9, 0, - /* 7713 */ 'c', 'l', 'i', 'b', 'n', 'h', 9, 0, - /* 7721 */ 'c', 'r', 'b', 'n', 'h', 9, 0, - /* 7728 */ 'c', 'g', 'r', 'b', 'n', 'h', 9, 0, - /* 7736 */ 'c', 'l', 'g', 'r', 'b', 'n', 'h', 9, 0, - /* 7745 */ 'c', 'l', 'r', 'b', 'n', 'h', 9, 0, - /* 7753 */ 'l', 'o', 'c', 'n', 'h', 9, 0, - /* 7760 */ 's', 't', 'o', 'c', 'n', 'h', 9, 0, - /* 7768 */ 'l', 'o', 'c', 'g', 'n', 'h', 9, 0, - /* 7776 */ 's', 't', 'o', 'c', 'g', 'n', 'h', 9, 0, - /* 7785 */ 'j', 'g', 'n', 'h', 9, 0, - /* 7791 */ 'l', 'o', 'c', 'f', 'h', 'n', 'h', 9, 0, - /* 7800 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'h', 9, 0, - /* 7810 */ 'b', 'i', 'n', 'h', 9, 0, - /* 7816 */ 'l', 'o', 'c', 'h', 'i', 'n', 'h', 9, 0, - /* 7825 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'h', 9, 0, - /* 7835 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'h', 9, 0, - /* 7845 */ 'c', 'i', 'j', 'n', 'h', 9, 0, - /* 7852 */ 'c', 'g', 'i', 'j', 'n', 'h', 9, 0, - /* 7860 */ 'c', 'l', 'g', 'i', 'j', 'n', 'h', 9, 0, - /* 7869 */ 'c', 'l', 'i', 'j', 'n', 'h', 9, 0, - /* 7877 */ 'c', 'r', 'j', 'n', 'h', 9, 0, - /* 7884 */ 'c', 'g', 'r', 'j', 'n', 'h', 9, 0, - /* 7892 */ 'c', 'l', 'g', 'r', 'j', 'n', 'h', 9, 0, - /* 7901 */ 'c', 'l', 'r', 'j', 'n', 'h', 9, 0, - /* 7909 */ 'v', 'm', 'n', 'h', 9, 0, - /* 7915 */ 'l', 'o', 'c', 'r', 'n', 'h', 9, 0, - /* 7923 */ 'l', 'o', 'c', 'g', 'r', 'n', 'h', 9, 0, - /* 7932 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'h', 9, 0, - /* 7942 */ 'c', 'l', 'g', 't', 'n', 'h', 9, 0, - /* 7950 */ 'c', 'i', 't', 'n', 'h', 9, 0, - /* 7957 */ 'c', 'l', 'f', 'i', 't', 'n', 'h', 9, 0, - /* 7966 */ 'c', 'g', 'i', 't', 'n', 'h', 9, 0, - /* 7974 */ 'c', 'l', 'g', 'i', 't', 'n', 'h', 9, 0, - /* 7983 */ 'c', 'l', 't', 'n', 'h', 9, 0, - /* 7990 */ 'c', 'r', 't', 'n', 'h', 9, 0, - /* 7997 */ 'c', 'g', 'r', 't', 'n', 'h', 9, 0, - /* 8005 */ 'c', 'l', 'g', 'r', 't', 'n', 'h', 9, 0, - /* 8014 */ 'c', 'l', 'r', 't', 'n', 'h', 9, 0, - /* 8022 */ 'v', 'm', 'a', 'o', 'h', 9, 0, - /* 8029 */ 'v', 'm', 'a', 'l', 'o', 'h', 9, 0, - /* 8037 */ 'v', 'm', 'l', 'o', 'h', 9, 0, - /* 8044 */ 'v', 'm', 'o', 'h', 9, 0, - /* 8050 */ 'v', 'l', 'r', 'e', 'p', 'h', 9, 0, - /* 8058 */ 'v', 'r', 'e', 'p', 'h', 9, 0, - /* 8065 */ 'v', 'l', 'p', 'h', 9, 0, - /* 8071 */ 'v', 'u', 'p', 'h', 9, 0, - /* 8077 */ 'v', 'c', 'e', 'q', 'h', 9, 0, - /* 8084 */ 'l', 'o', 'c', 'r', 'h', 9, 0, - /* 8091 */ 'l', 'o', 'c', 'g', 'r', 'h', 9, 0, - /* 8099 */ 'l', 'o', 'c', 'f', 'h', 'r', 'h', 9, 0, - /* 8108 */ 'v', 'm', 'r', 'h', 9, 0, - /* 8114 */ 'v', 'i', 's', 't', 'r', 'h', 9, 0, - /* 8122 */ 'v', 'p', 'k', 's', 'h', 9, 0, - /* 8129 */ 'v', 'p', 'k', 'l', 's', 'h', 9, 0, - /* 8137 */ 'v', 's', 'h', 9, 0, - /* 8142 */ 'v', 'p', 'o', 'p', 'c', 't', 'h', 9, 0, - /* 8151 */ 'b', 'r', 'c', 't', 'h', 9, 0, - /* 8158 */ 'c', 'l', 'g', 't', 'h', 9, 0, - /* 8165 */ 'c', 'i', 't', 'h', 9, 0, - /* 8171 */ 'c', 'l', 'f', 'i', 't', 'h', 9, 0, - /* 8179 */ 'c', 'g', 'i', 't', 'h', 9, 0, - /* 8186 */ 'c', 'l', 'g', 'i', 't', 'h', 9, 0, - /* 8194 */ 'c', 'l', 't', 'h', 9, 0, - /* 8200 */ 'c', 'r', 't', 'h', 9, 0, - /* 8206 */ 'c', 'g', 'r', 't', 'h', 9, 0, - /* 8213 */ 'c', 'l', 'g', 'r', 't', 'h', 9, 0, - /* 8221 */ 'c', 'l', 'r', 't', 'h', 9, 0, - /* 8228 */ 's', 't', 'h', 9, 0, - /* 8233 */ 'v', 'e', 's', 'r', 'a', 'v', 'h', 9, 0, - /* 8242 */ 'v', 'l', 'g', 'v', 'h', 9, 0, - /* 8249 */ 'v', 'e', 'r', 'l', 'l', 'v', 'h', 9, 0, - /* 8258 */ 'v', 'e', 's', 'r', 'l', 'v', 'h', 9, 0, - /* 8267 */ 'v', 'e', 's', 'l', 'v', 'h', 9, 0, - /* 8275 */ 'l', 'r', 'v', 'h', 9, 0, - /* 8281 */ 's', 't', 'r', 'v', 'h', 9, 0, - /* 8288 */ 'b', 'x', 'h', 9, 0, - /* 8293 */ 'v', 'm', 'x', 'h', 9, 0, - /* 8299 */ 'b', 'r', 'x', 'h', 9, 0, - /* 8305 */ 'm', 'a', 'y', 'h', 9, 0, - /* 8311 */ 'm', 'y', 'h', 9, 0, - /* 8316 */ 'v', 's', 't', 'r', 'c', 'z', 'h', 9, 0, - /* 8325 */ 'v', 'f', 'a', 'e', 'z', 'h', 9, 0, - /* 8333 */ 'v', 'f', 'e', 'e', 'z', 'h', 9, 0, - /* 8341 */ 'v', 'l', 'l', 'e', 'z', 'h', 9, 0, - /* 8349 */ 'v', 'f', 'e', 'n', 'e', 'z', 'h', 9, 0, - /* 8358 */ 'v', 'c', 'l', 'z', 'h', 9, 0, - /* 8365 */ 'v', 'c', 't', 'z', 'h', 9, 0, - /* 8372 */ 'n', 'i', 'a', 'i', 9, 0, - /* 8378 */ 'v', 's', 'b', 'c', 'b', 'i', 9, 0, - /* 8386 */ 'v', 's', 'c', 'b', 'i', 9, 0, - /* 8393 */ 'v', 's', 'b', 'i', 9, 0, - /* 8399 */ 'v', 'f', 't', 'c', 'i', 9, 0, - /* 8406 */ 'v', 'p', 'd', 'i', 9, 0, - /* 8412 */ 'a', 'f', 'i', 9, 0, - /* 8417 */ 'c', 'f', 'i', 9, 0, - /* 8422 */ 'a', 'g', 'f', 'i', 9, 0, - /* 8428 */ 'c', 'g', 'f', 'i', 9, 0, - /* 8434 */ 'a', 'l', 'g', 'f', 'i', 9, 0, - /* 8441 */ 'c', 'l', 'g', 'f', 'i', 9, 0, - /* 8448 */ 's', 'l', 'g', 'f', 'i', 9, 0, - /* 8455 */ 'm', 's', 'g', 'f', 'i', 9, 0, - /* 8462 */ 'a', 'l', 'f', 'i', 9, 0, - /* 8468 */ 'c', 'l', 'f', 'i', 9, 0, - /* 8474 */ 's', 'l', 'f', 'i', 9, 0, - /* 8480 */ 'm', 's', 'f', 'i', 9, 0, - /* 8486 */ 'v', 'f', 'i', 9, 0, - /* 8491 */ 'a', 'h', 'i', 9, 0, - /* 8496 */ 'l', 'o', 'c', 'h', 'i', 9, 0, - /* 8503 */ 'a', 'g', 'h', 'i', 9, 0, - /* 8509 */ 'l', 'o', 'c', 'g', 'h', 'i', 9, 0, - /* 8517 */ 'l', 'g', 'h', 'i', 9, 0, - /* 8523 */ 'm', 'g', 'h', 'i', 9, 0, - /* 8529 */ 'm', 'v', 'g', 'h', 'i', 9, 0, - /* 8536 */ 'l', 'o', 'c', 'h', 'h', 'i', 9, 0, - /* 8544 */ 'm', 'v', 'h', 'h', 'i', 9, 0, - /* 8551 */ 'l', 'h', 'i', 9, 0, - /* 8556 */ 'm', 'h', 'i', 9, 0, - /* 8561 */ 'm', 'v', 'h', 'i', 9, 0, - /* 8567 */ 'c', 'l', 'i', 9, 0, - /* 8572 */ 'n', 'i', 9, 0, - /* 8576 */ 'o', 'i', 9, 0, - /* 8580 */ 'v', 'r', 'e', 'p', 'i', 9, 0, - /* 8587 */ 't', 'p', 'i', 9, 0, - /* 8592 */ 'q', 'c', 't', 'r', 'i', 9, 0, - /* 8599 */ 'a', 's', 'i', 9, 0, - /* 8604 */ 'a', 'g', 's', 'i', 9, 0, - /* 8610 */ 'a', 'l', 'g', 's', 'i', 9, 0, - /* 8617 */ 'c', 'h', 's', 'i', 9, 0, - /* 8623 */ 'c', 'l', 'f', 'h', 's', 'i', 9, 0, - /* 8631 */ 'c', 'g', 'h', 's', 'i', 9, 0, - /* 8638 */ 'c', 'l', 'g', 'h', 's', 'i', 9, 0, - /* 8646 */ 'c', 'h', 'h', 's', 'i', 9, 0, - /* 8653 */ 'c', 'l', 'h', 'h', 's', 'i', 9, 0, - /* 8661 */ 'a', 'l', 's', 'i', 9, 0, - /* 8667 */ 'q', 's', 'i', 9, 0, - /* 8672 */ 's', 't', 's', 'i', 9, 0, - /* 8678 */ 'p', 't', 'i', 9, 0, - /* 8683 */ 'm', 'v', 'i', 9, 0, - /* 8688 */ 'x', 'i', 9, 0, - /* 8692 */ 'c', 'i', 'j', 9, 0, - /* 8697 */ 'c', 'g', 'i', 'j', 9, 0, - /* 8703 */ 'c', 'l', 'g', 'i', 'j', 9, 0, - /* 8710 */ 'c', 'l', 'i', 'j', 9, 0, - /* 8716 */ 'c', 'r', 'j', 9, 0, - /* 8721 */ 'c', 'g', 'r', 'j', 9, 0, - /* 8727 */ 'c', 'l', 'g', 'r', 'j', 9, 0, - /* 8734 */ 'c', 'l', 'r', 'j', 9, 0, - /* 8740 */ 's', 'l', 'a', 'k', 9, 0, - /* 8746 */ 's', 'r', 'a', 'k', 9, 0, - /* 8752 */ 'p', 'a', 'c', 'k', 9, 0, - /* 8758 */ 's', 'c', 'k', 9, 0, - /* 8763 */ 's', 't', 'c', 'k', 9, 0, - /* 8769 */ 'm', 'v', 'c', 'k', 9, 0, - /* 8775 */ 'm', 'v', 'c', 'd', 'k', 9, 0, - /* 8782 */ 'w', 'f', 'k', 9, 0, - /* 8787 */ 'a', 'h', 'i', 'k', 9, 0, - /* 8793 */ 'a', 'g', 'h', 'i', 'k', 9, 0, - /* 8800 */ 'a', 'l', 'g', 'h', 's', 'i', 'k', 9, 0, - /* 8809 */ 'a', 'l', 'h', 's', 'i', 'k', 9, 0, - /* 8817 */ 's', 'l', 'l', 'k', 9, 0, - /* 8823 */ 's', 'r', 'l', 'k', 9, 0, - /* 8829 */ 'e', 'd', 'm', 'k', 9, 0, - /* 8835 */ 'u', 'n', 'p', 'k', 9, 0, - /* 8841 */ 'v', 'p', 'k', 9, 0, - /* 8846 */ 'a', 'r', 'k', 9, 0, - /* 8851 */ 'a', 'g', 'r', 'k', 9, 0, - /* 8857 */ 'a', 'l', 'g', 'r', 'k', 9, 0, - /* 8864 */ 's', 'l', 'g', 'r', 'k', 9, 0, - /* 8871 */ 'm', 'g', 'r', 'k', 9, 0, - /* 8877 */ 'n', 'g', 'r', 'k', 9, 0, - /* 8883 */ 'o', 'g', 'r', 'k', 9, 0, - /* 8889 */ 's', 'g', 'r', 'k', 9, 0, - /* 8895 */ 'x', 'g', 'r', 'k', 9, 0, - /* 8901 */ 'a', 'l', 'r', 'k', 9, 0, - /* 8907 */ 's', 'l', 'r', 'k', 9, 0, - /* 8913 */ 'n', 'r', 'k', 9, 0, - /* 8918 */ 'o', 'r', 'k', 9, 0, - /* 8923 */ 's', 'r', 'k', 9, 0, - /* 8928 */ 'x', 'r', 'k', 9, 0, - /* 8933 */ 'm', 'v', 'c', 's', 'k', 9, 0, - /* 8940 */ 'i', 'v', 's', 'k', 9, 0, - /* 8946 */ 'l', 'a', 'a', 'l', 9, 0, - /* 8952 */ 'b', 'a', 'l', 9, 0, - /* 8957 */ 'v', 'm', 'a', 'l', 9, 0, - /* 8963 */ 'c', 'i', 'b', 'l', 9, 0, - /* 8969 */ 'c', 'g', 'i', 'b', 'l', 9, 0, - /* 8976 */ 'c', 'l', 'g', 'i', 'b', 'l', 9, 0, - /* 8984 */ 'c', 'l', 'i', 'b', 'l', 9, 0, - /* 8991 */ 'c', 'r', 'b', 'l', 9, 0, - /* 8997 */ 'c', 'g', 'r', 'b', 'l', 9, 0, - /* 9004 */ 'c', 'l', 'g', 'r', 'b', 'l', 9, 0, - /* 9012 */ 'c', 'l', 'r', 'b', 'l', 9, 0, - /* 9019 */ 'v', 'e', 'c', 'l', 9, 0, - /* 9025 */ 'c', 'l', 'c', 'l', 9, 0, - /* 9031 */ 'l', 'o', 'c', 'l', 9, 0, - /* 9037 */ 's', 't', 'o', 'c', 'l', 9, 0, - /* 9044 */ 'b', 'r', 'c', 'l', 9, 0, - /* 9050 */ 'm', 'v', 'c', 'l', 9, 0, - /* 9056 */ 's', 'l', 'd', 'l', 9, 0, - /* 9062 */ 's', 'r', 'd', 'l', 9, 0, - /* 9068 */ 'v', 's', 'e', 'l', 9, 0, - /* 9074 */ 's', 't', 'f', 'l', 9, 0, - /* 9080 */ 'l', 'o', 'c', 'g', 'l', 9, 0, - /* 9087 */ 's', 't', 'o', 'c', 'g', 'l', 9, 0, - /* 9095 */ 'j', 'g', 'l', 9, 0, - /* 9100 */ 'v', 'a', 'v', 'g', 'l', 9, 0, - /* 9107 */ 'v', 'c', 'h', 'l', 9, 0, - /* 9113 */ 'l', 'o', 'c', 'f', 'h', 'l', 9, 0, - /* 9121 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 9, 0, - /* 9130 */ 'i', 'i', 'h', 'l', 9, 0, - /* 9136 */ 'l', 'l', 'i', 'h', 'l', 9, 0, - /* 9143 */ 'n', 'i', 'h', 'l', 9, 0, - /* 9149 */ 'o', 'i', 'h', 'l', 9, 0, - /* 9155 */ 't', 'm', 'h', 'l', 9, 0, - /* 9161 */ 'b', 'i', 'l', 9, 0, - /* 9166 */ 'l', 'o', 'c', 'h', 'i', 'l', 9, 0, - /* 9174 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 9, 0, - /* 9183 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 9, 0, - /* 9192 */ 'c', 'i', 'j', 'l', 9, 0, - /* 9198 */ 'c', 'g', 'i', 'j', 'l', 9, 0, - /* 9205 */ 'c', 'l', 'g', 'i', 'j', 'l', 9, 0, - /* 9213 */ 'c', 'l', 'i', 'j', 'l', 9, 0, - /* 9220 */ 'c', 'r', 'j', 'l', 9, 0, - /* 9226 */ 'c', 'g', 'r', 'j', 'l', 9, 0, - /* 9233 */ 'c', 'l', 'g', 'r', 'j', 'l', 9, 0, - /* 9241 */ 'c', 'l', 'r', 'j', 'l', 9, 0, - /* 9248 */ 'v', 'f', 'l', 'l', 9, 0, - /* 9254 */ 'i', 'i', 'l', 'l', 9, 0, - /* 9260 */ 'l', 'l', 'i', 'l', 'l', 9, 0, - /* 9267 */ 'n', 'i', 'l', 'l', 9, 0, - /* 9273 */ 'o', 'i', 'l', 'l', 9, 0, - /* 9279 */ 't', 'm', 'l', 'l', 9, 0, - /* 9285 */ 'v', 'u', 'p', 'l', 'l', 9, 0, - /* 9292 */ 'v', 'e', 'r', 'l', 'l', 9, 0, - /* 9299 */ 's', 'l', 'l', 9, 0, - /* 9304 */ 'v', 'l', 'l', 9, 0, - /* 9309 */ 'v', 'm', 'l', 9, 0, - /* 9314 */ 'c', 'i', 'b', 'n', 'l', 9, 0, - /* 9321 */ 'c', 'g', 'i', 'b', 'n', 'l', 9, 0, - /* 9329 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 9, 0, - /* 9338 */ 'c', 'l', 'i', 'b', 'n', 'l', 9, 0, - /* 9346 */ 'c', 'r', 'b', 'n', 'l', 9, 0, - /* 9353 */ 'c', 'g', 'r', 'b', 'n', 'l', 9, 0, - /* 9361 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 9, 0, - /* 9370 */ 'c', 'l', 'r', 'b', 'n', 'l', 9, 0, - /* 9378 */ 'l', 'o', 'c', 'n', 'l', 9, 0, - /* 9385 */ 's', 't', 'o', 'c', 'n', 'l', 9, 0, - /* 9393 */ 'l', 'o', 'c', 'g', 'n', 'l', 9, 0, - /* 9401 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 9, 0, - /* 9410 */ 'j', 'g', 'n', 'l', 9, 0, - /* 9416 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 9, 0, - /* 9425 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 9, 0, - /* 9435 */ 'b', 'i', 'n', 'l', 9, 0, - /* 9441 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 9, 0, - /* 9450 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 9, 0, - /* 9460 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 9, 0, - /* 9470 */ 'c', 'i', 'j', 'n', 'l', 9, 0, - /* 9477 */ 'c', 'g', 'i', 'j', 'n', 'l', 9, 0, - /* 9485 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 9, 0, - /* 9494 */ 'c', 'l', 'i', 'j', 'n', 'l', 9, 0, - /* 9502 */ 'c', 'r', 'j', 'n', 'l', 9, 0, - /* 9509 */ 'c', 'g', 'r', 'j', 'n', 'l', 9, 0, - /* 9517 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 9, 0, - /* 9526 */ 'c', 'l', 'r', 'j', 'n', 'l', 9, 0, - /* 9534 */ 'v', 'm', 'n', 'l', 9, 0, - /* 9540 */ 'l', 'o', 'c', 'r', 'n', 'l', 9, 0, - /* 9548 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 9, 0, - /* 9557 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 9, 0, - /* 9567 */ 'c', 'l', 'g', 't', 'n', 'l', 9, 0, - /* 9575 */ 'c', 'i', 't', 'n', 'l', 9, 0, - /* 9582 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 9, 0, - /* 9591 */ 'c', 'g', 'i', 't', 'n', 'l', 9, 0, - /* 9599 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 9, 0, - /* 9608 */ 'c', 'l', 't', 'n', 'l', 9, 0, - /* 9615 */ 'c', 'r', 't', 'n', 'l', 9, 0, - /* 9622 */ 'c', 'g', 'r', 't', 'n', 'l', 9, 0, - /* 9630 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 9, 0, - /* 9639 */ 'c', 'l', 'r', 't', 'n', 'l', 9, 0, - /* 9647 */ 'v', 'u', 'p', 'l', 9, 0, - /* 9653 */ 'l', 'a', 'r', 'l', 9, 0, - /* 9659 */ 'l', 'o', 'c', 'r', 'l', 9, 0, - /* 9666 */ 'p', 'f', 'd', 'r', 'l', 9, 0, - /* 9673 */ 'c', 'g', 'f', 'r', 'l', 9, 0, - /* 9680 */ 'c', 'l', 'g', 'f', 'r', 'l', 9, 0, - /* 9688 */ 'l', 'l', 'g', 'f', 'r', 'l', 9, 0, - /* 9696 */ 'l', 'o', 'c', 'g', 'r', 'l', 9, 0, - /* 9704 */ 'c', 'l', 'g', 'r', 'l', 9, 0, - /* 9711 */ 's', 't', 'g', 'r', 'l', 9, 0, - /* 9718 */ 'c', 'h', 'r', 'l', 9, 0, - /* 9724 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 9, 0, - /* 9733 */ 'c', 'g', 'h', 'r', 'l', 9, 0, - /* 9740 */ 'c', 'l', 'g', 'h', 'r', 'l', 9, 0, - /* 9748 */ 'l', 'l', 'g', 'h', 'r', 'l', 9, 0, - /* 9756 */ 'c', 'l', 'h', 'r', 'l', 9, 0, - /* 9763 */ 'l', 'l', 'h', 'r', 'l', 9, 0, - /* 9770 */ 's', 't', 'h', 'r', 'l', 9, 0, - /* 9777 */ 'c', 'l', 'r', 'l', 9, 0, - /* 9783 */ 'v', 'l', 'r', 'l', 9, 0, - /* 9789 */ 'v', 'm', 'r', 'l', 9, 0, - /* 9795 */ 'v', 'e', 's', 'r', 'l', 9, 0, - /* 9802 */ 'v', 's', 'r', 'l', 9, 0, - /* 9808 */ 'v', 's', 't', 'r', 'l', 9, 0, - /* 9815 */ 'e', 'x', 'r', 'l', 9, 0, - /* 9821 */ 'b', 'r', 'a', 's', 'l', 9, 0, - /* 9828 */ 'v', 'e', 's', 'l', 9, 0, - /* 9834 */ 'v', 'm', 's', 'l', 9, 0, - /* 9840 */ 'v', 's', 'l', 9, 0, - /* 9845 */ 'l', 'c', 'c', 't', 'l', 9, 0, - /* 9852 */ 'l', 'c', 't', 'l', 9, 0, - /* 9858 */ 'l', 'p', 'c', 't', 'l', 9, 0, - /* 9865 */ 'l', 's', 'c', 't', 'l', 9, 0, - /* 9872 */ 's', 't', 'c', 't', 'l', 9, 0, - /* 9879 */ 'c', 'l', 'g', 't', 'l', 9, 0, - /* 9886 */ 'c', 'i', 't', 'l', 9, 0, - /* 9892 */ 'c', 'l', 'f', 'i', 't', 'l', 9, 0, - /* 9900 */ 'c', 'g', 'i', 't', 'l', 9, 0, - /* 9907 */ 'c', 'l', 'g', 'i', 't', 'l', 9, 0, - /* 9915 */ 'c', 'l', 't', 'l', 9, 0, - /* 9921 */ 'c', 'r', 't', 'l', 9, 0, - /* 9927 */ 'c', 'g', 'r', 't', 'l', 9, 0, - /* 9934 */ 'c', 'l', 'g', 'r', 't', 'l', 9, 0, - /* 9942 */ 'c', 'l', 'r', 't', 'l', 9, 0, - /* 9949 */ 'v', 's', 't', 'l', 9, 0, - /* 9955 */ 'v', 'l', 9, 0, - /* 9959 */ 'v', 'm', 'x', 'l', 9, 0, - /* 9965 */ 'm', 'a', 'y', 'l', 9, 0, - /* 9971 */ 'm', 'y', 'l', 9, 0, - /* 9976 */ 'l', 'a', 'm', 9, 0, - /* 9981 */ 's', 't', 'a', 'm', 9, 0, - /* 9987 */ 'v', 'g', 'b', 'm', 9, 0, - /* 9993 */ 'i', 'r', 'b', 'm', 9, 0, - /* 9999 */ 'r', 'r', 'b', 'm', 9, 0, - /* 10005 */ 'i', 'c', 'm', 9, 0, - /* 10010 */ 'l', 'o', 'c', 'm', 9, 0, - /* 10016 */ 's', 't', 'o', 'c', 'm', 9, 0, - /* 10023 */ 's', 't', 'c', 'm', 9, 0, - /* 10029 */ 'v', 'g', 'f', 'm', 9, 0, - /* 10035 */ 'v', 'f', 'm', 9, 0, - /* 10040 */ 'l', 'o', 'c', 'g', 'm', 9, 0, - /* 10047 */ 's', 't', 'o', 'c', 'g', 'm', 9, 0, - /* 10055 */ 'j', 'g', 'm', 9, 0, - /* 10060 */ 'v', 'g', 'm', 9, 0, - /* 10065 */ 'l', 'o', 'c', 'f', 'h', 'm', 9, 0, - /* 10073 */ 's', 't', 'o', 'c', 'f', 'h', 'm', 9, 0, - /* 10082 */ 'b', 'i', 'm', 9, 0, - /* 10087 */ 'l', 'o', 'c', 'h', 'i', 'm', 9, 0, - /* 10095 */ 'l', 'o', 'c', 'g', 'h', 'i', 'm', 9, 0, - /* 10104 */ 'l', 'o', 'c', 'h', 'h', 'i', 'm', 9, 0, - /* 10113 */ 'v', 'e', 'r', 'i', 'm', 9, 0, - /* 10120 */ 'j', 'm', 9, 0, - /* 10124 */ 'k', 'm', 9, 0, - /* 10128 */ 'c', 'l', 'm', 9, 0, - /* 10133 */ 'v', 'l', 'm', 9, 0, - /* 10138 */ 'b', 'n', 'm', 9, 0, - /* 10143 */ 'l', 'o', 'c', 'n', 'm', 9, 0, - /* 10150 */ 's', 't', 'o', 'c', 'n', 'm', 9, 0, - /* 10158 */ 'l', 'o', 'c', 'g', 'n', 'm', 9, 0, - /* 10166 */ 's', 't', 'o', 'c', 'g', 'n', 'm', 9, 0, - /* 10175 */ 'j', 'g', 'n', 'm', 9, 0, - /* 10181 */ 'l', 'o', 'c', 'f', 'h', 'n', 'm', 9, 0, - /* 10190 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'm', 9, 0, - /* 10200 */ 'b', 'i', 'n', 'm', 9, 0, - /* 10206 */ 'l', 'o', 'c', 'h', 'i', 'n', 'm', 9, 0, - /* 10215 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'm', 9, 0, - /* 10225 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'm', 9, 0, - /* 10235 */ 'j', 'n', 'm', 9, 0, - /* 10240 */ 'l', 'o', 'c', 'r', 'n', 'm', 9, 0, - /* 10248 */ 'l', 'o', 'c', 'g', 'r', 'n', 'm', 9, 0, - /* 10257 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'm', 9, 0, - /* 10267 */ 's', 'r', 'n', 'm', 9, 0, - /* 10273 */ 'i', 'p', 'm', 9, 0, - /* 10278 */ 's', 'p', 'm', 9, 0, - /* 10283 */ 'l', 'o', 'c', 'r', 'm', 9, 0, - /* 10290 */ 'v', 'b', 'p', 'e', 'r', 'm', 9, 0, - /* 10298 */ 'v', 'p', 'e', 'r', 'm', 9, 0, - /* 10305 */ 'l', 'o', 'c', 'g', 'r', 'm', 9, 0, - /* 10313 */ 'l', 'o', 'c', 'f', 'h', 'r', 'm', 9, 0, - /* 10322 */ 'b', 's', 'm', 9, 0, - /* 10327 */ 'v', 'c', 'k', 's', 'm', 9, 0, - /* 10334 */ 's', 't', 'n', 's', 'm', 9, 0, - /* 10341 */ 's', 't', 'o', 's', 'm', 9, 0, - /* 10348 */ 'b', 'a', 's', 's', 'm', 9, 0, - /* 10355 */ 'v', 's', 't', 'm', 9, 0, - /* 10361 */ 'v', 't', 'm', 9, 0, - /* 10366 */ 'v', 's', 'u', 'm', 9, 0, - /* 10372 */ 'l', 'a', 'n', 9, 0, - /* 10377 */ 'r', 'i', 's', 'b', 'g', 'n', 9, 0, - /* 10385 */ 'a', 'l', 's', 'i', 'h', 'n', 9, 0, - /* 10393 */ 'm', 'v', 'c', 'i', 'n', 9, 0, - /* 10400 */ 't', 'b', 'e', 'g', 'i', 'n', 9, 0, - /* 10408 */ 'p', 'g', 'i', 'n', 9, 0, - /* 10414 */ 'v', 'f', 'm', 'i', 'n', 9, 0, - /* 10421 */ 'v', 'm', 'n', 9, 0, - /* 10426 */ 'v', 'n', 'n', 9, 0, - /* 10431 */ 'm', 'v', 'n', 9, 0, - /* 10436 */ 'l', 'a', 'o', 9, 0, - /* 10441 */ 'v', 'm', 'a', 'o', 9, 0, - /* 10447 */ 'b', 'o', 9, 0, - /* 10451 */ 'l', 'o', 'c', 'o', 9, 0, - /* 10457 */ 's', 't', 'o', 'c', 'o', 9, 0, - /* 10464 */ 'l', 'o', 'c', 'g', 'o', 9, 0, - /* 10471 */ 's', 't', 'o', 'c', 'g', 'o', 9, 0, - /* 10479 */ 'j', 'g', 'o', 9, 0, - /* 10484 */ 'l', 'o', 'c', 'f', 'h', 'o', 9, 0, - /* 10492 */ 's', 't', 'o', 'c', 'f', 'h', 'o', 9, 0, - /* 10501 */ 'b', 'i', 'o', 9, 0, - /* 10506 */ 'l', 'o', 'c', 'h', 'i', 'o', 9, 0, - /* 10514 */ 'l', 'o', 'c', 'g', 'h', 'i', 'o', 9, 0, - /* 10523 */ 'l', 'o', 'c', 'h', 'h', 'i', 'o', 9, 0, - /* 10532 */ 'j', 'o', 9, 0, - /* 10536 */ 'v', 'm', 'a', 'l', 'o', 9, 0, - /* 10543 */ 'v', 'm', 'l', 'o', 9, 0, - /* 10549 */ 'p', 'l', 'o', 9, 0, - /* 10554 */ 'k', 'm', 'o', 9, 0, - /* 10559 */ 'v', 'm', 'o', 9, 0, - /* 10564 */ 'b', 'n', 'o', 9, 0, - /* 10569 */ 'l', 'o', 'c', 'n', 'o', 9, 0, - /* 10576 */ 's', 't', 'o', 'c', 'n', 'o', 9, 0, - /* 10584 */ 'l', 'o', 'c', 'g', 'n', 'o', 9, 0, - /* 10592 */ 's', 't', 'o', 'c', 'g', 'n', 'o', 9, 0, - /* 10601 */ 'j', 'g', 'n', 'o', 9, 0, - /* 10607 */ 'l', 'o', 'c', 'f', 'h', 'n', 'o', 9, 0, - /* 10616 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'o', 9, 0, - /* 10626 */ 'b', 'i', 'n', 'o', 9, 0, - /* 10632 */ 'l', 'o', 'c', 'h', 'i', 'n', 'o', 9, 0, - /* 10641 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'o', 9, 0, - /* 10651 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'o', 9, 0, - /* 10661 */ 'j', 'n', 'o', 9, 0, - /* 10666 */ 'p', 'p', 'n', 'o', 9, 0, - /* 10672 */ 'l', 'o', 'c', 'r', 'n', 'o', 9, 0, - /* 10680 */ 'l', 'o', 'c', 'g', 'r', 'n', 'o', 9, 0, - /* 10689 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'o', 9, 0, - /* 10699 */ 'p', 'r', 'n', 'o', 9, 0, - /* 10705 */ 'v', 'n', 'o', 9, 0, - /* 10710 */ 't', 'r', 'o', 'o', 9, 0, - /* 10716 */ 'l', 'o', 'c', 'r', 'o', 9, 0, - /* 10723 */ 'v', 'z', 'e', 'r', 'o', 9, 0, - /* 10730 */ 'l', 'o', 'c', 'g', 'r', 'o', 9, 0, - /* 10738 */ 'l', 'o', 'c', 'f', 'h', 'r', 'o', 9, 0, - /* 10747 */ 'v', 'f', 'p', 's', 'o', 9, 0, - /* 10754 */ 't', 'r', 't', 'o', 9, 0, - /* 10760 */ 'm', 'v', 'o', 9, 0, - /* 10765 */ 's', 't', 'a', 'p', 9, 0, - /* 10771 */ 'v', 'a', 'p', 9, 0, - /* 10776 */ 'z', 'a', 'p', 9, 0, - /* 10781 */ 'b', 'p', 9, 0, - /* 10785 */ 'l', 'o', 'c', 'p', 9, 0, - /* 10791 */ 's', 't', 'o', 'c', 'p', 9, 0, - /* 10798 */ 'm', 'v', 'c', 'p', 9, 0, - /* 10804 */ 's', 't', 'i', 'd', 'p', 9, 0, - /* 10811 */ 'v', 's', 'd', 'p', 9, 0, - /* 10817 */ 'v', 'd', 'p', 9, 0, - /* 10822 */ 'v', 'l', 'r', 'e', 'p', 9, 0, - /* 10829 */ 'v', 'r', 'e', 'p', 9, 0, - /* 10835 */ 'l', 'o', 'c', 'g', 'p', 9, 0, - /* 10842 */ 's', 't', 'o', 'c', 'g', 'p', 9, 0, - /* 10850 */ 's', 'i', 'g', 'p', 9, 0, - /* 10856 */ 'j', 'g', 'p', 9, 0, - /* 10861 */ 'v', 'l', 'v', 'g', 'p', 9, 0, - /* 10868 */ 'l', 'o', 'c', 'f', 'h', 'p', 9, 0, - /* 10876 */ 's', 't', 'o', 'c', 'f', 'h', 'p', 9, 0, - /* 10885 */ 'b', 'i', 'p', 9, 0, - /* 10890 */ 'l', 'o', 'c', 'h', 'i', 'p', 9, 0, - /* 10898 */ 'l', 'o', 'c', 'g', 'h', 'i', 'p', 9, 0, - /* 10907 */ 'l', 'o', 'c', 'h', 'h', 'i', 'p', 9, 0, - /* 10916 */ 'v', 'l', 'i', 'p', 9, 0, - /* 10922 */ 'j', 'p', 9, 0, - /* 10926 */ 'v', 'l', 'p', 9, 0, - /* 10931 */ 'v', 'm', 'p', 9, 0, - /* 10936 */ 'b', 'n', 'p', 9, 0, - /* 10941 */ 'l', 'o', 'c', 'n', 'p', 9, 0, - /* 10948 */ 's', 't', 'o', 'c', 'n', 'p', 9, 0, - /* 10956 */ 'l', 'o', 'c', 'g', 'n', 'p', 9, 0, - /* 10964 */ 's', 't', 'o', 'c', 'g', 'n', 'p', 9, 0, - /* 10973 */ 'j', 'g', 'n', 'p', 9, 0, - /* 10979 */ 'l', 'o', 'c', 'f', 'h', 'n', 'p', 9, 0, - /* 10988 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'p', 9, 0, - /* 10998 */ 'b', 'i', 'n', 'p', 9, 0, - /* 11004 */ 'l', 'o', 'c', 'h', 'i', 'n', 'p', 9, 0, - /* 11013 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'p', 9, 0, - /* 11023 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'p', 9, 0, - /* 11033 */ 'j', 'n', 'p', 9, 0, - /* 11038 */ 'l', 'o', 'c', 'r', 'n', 'p', 9, 0, - /* 11046 */ 'l', 'o', 'c', 'g', 'r', 'n', 'p', 9, 0, - /* 11055 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'p', 9, 0, - /* 11065 */ 'v', 'p', 's', 'o', 'p', 9, 0, - /* 11072 */ 'b', 'p', 'p', 9, 0, - /* 11077 */ 'l', 'p', 'p', 9, 0, - /* 11082 */ 'l', 'o', 'c', 'r', 'p', 9, 0, - /* 11089 */ 'l', 'o', 'c', 'g', 'r', 'p', 9, 0, - /* 11097 */ 'l', 'o', 'c', 'f', 'h', 'r', 'p', 9, 0, - /* 11106 */ 'b', 'p', 'r', 'p', 9, 0, - /* 11112 */ 'v', 's', 'r', 'p', 9, 0, - /* 11118 */ 'v', 'r', 'p', 9, 0, - /* 11123 */ 'l', 'a', 's', 'p', 9, 0, - /* 11129 */ 'c', 's', 'p', 9, 0, - /* 11134 */ 'v', 'm', 's', 'p', 9, 0, - /* 11140 */ 'v', 's', 'p', 9, 0, - /* 11145 */ 'v', 't', 'p', 9, 0, - /* 11150 */ 'v', 'a', 'q', 9, 0, - /* 11155 */ 'v', 'a', 'c', 'q', 9, 0, - /* 11161 */ 'v', 'a', 'c', 'c', 'q', 9, 0, - /* 11168 */ 'v', 'a', 'c', 'c', 'c', 'q', 9, 0, - /* 11176 */ 'v', 'c', 'e', 'q', 9, 0, - /* 11182 */ 'v', 's', 'b', 'c', 'b', 'i', 'q', 9, 0, - /* 11191 */ 'v', 's', 'c', 'b', 'i', 'q', 9, 0, - /* 11199 */ 'v', 's', 'b', 'i', 'q', 9, 0, - /* 11206 */ 'v', 's', 'u', 'm', 'q', 9, 0, - /* 11213 */ 'l', 'p', 'q', 9, 0, - /* 11218 */ 's', 't', 'p', 'q', 9, 0, - /* 11224 */ 'v', 'f', 's', 'q', 9, 0, - /* 11230 */ 'v', 's', 'q', 9, 0, - /* 11235 */ 'e', 'a', 'r', 9, 0, - /* 11240 */ 'e', 'p', 'a', 'r', 9, 0, - /* 11246 */ 'e', 's', 'a', 'r', 9, 0, - /* 11252 */ 's', 's', 'a', 'r', 9, 0, - /* 11258 */ 't', 'a', 'r', 9, 0, - /* 11263 */ 'm', 'a', 'd', 'b', 'r', 9, 0, - /* 11270 */ 'l', 'c', 'd', 'b', 'r', 9, 0, - /* 11277 */ 'd', 'd', 'b', 'r', 9, 0, - /* 11283 */ 'l', 'e', 'd', 'b', 'r', 9, 0, - /* 11290 */ 'c', 'f', 'd', 'b', 'r', 9, 0, - /* 11297 */ 'c', 'l', 'f', 'd', 'b', 'r', 9, 0, - /* 11305 */ 'c', 'g', 'd', 'b', 'r', 9, 0, - /* 11312 */ 'c', 'l', 'g', 'd', 'b', 'r', 9, 0, - /* 11320 */ 'd', 'i', 'd', 'b', 'r', 9, 0, - /* 11327 */ 'f', 'i', 'd', 'b', 'r', 9, 0, - /* 11334 */ 'k', 'd', 'b', 'r', 9, 0, - /* 11340 */ 'm', 'd', 'b', 'r', 9, 0, - /* 11346 */ 'l', 'n', 'd', 'b', 'r', 9, 0, - /* 11353 */ 'l', 'p', 'd', 'b', 'r', 9, 0, - /* 11360 */ 's', 'q', 'd', 'b', 'r', 9, 0, - /* 11367 */ 'm', 's', 'd', 'b', 'r', 9, 0, - /* 11374 */ 'l', 't', 'd', 'b', 'r', 9, 0, - /* 11381 */ 'l', 'x', 'd', 'b', 'r', 9, 0, - /* 11388 */ 'm', 'x', 'd', 'b', 'r', 9, 0, - /* 11395 */ 'm', 'a', 'e', 'b', 'r', 9, 0, - /* 11402 */ 'l', 'c', 'e', 'b', 'r', 9, 0, - /* 11409 */ 'l', 'd', 'e', 'b', 'r', 9, 0, - /* 11416 */ 'm', 'd', 'e', 'b', 'r', 9, 0, - /* 11423 */ 'm', 'e', 'e', 'b', 'r', 9, 0, - /* 11430 */ 'c', 'f', 'e', 'b', 'r', 9, 0, - /* 11437 */ 'c', 'l', 'f', 'e', 'b', 'r', 9, 0, - /* 11445 */ 'c', 'g', 'e', 'b', 'r', 9, 0, - /* 11452 */ 'c', 'l', 'g', 'e', 'b', 'r', 9, 0, - /* 11460 */ 'd', 'i', 'e', 'b', 'r', 9, 0, - /* 11467 */ 'f', 'i', 'e', 'b', 'r', 9, 0, - /* 11474 */ 'k', 'e', 'b', 'r', 9, 0, - /* 11480 */ 'l', 'n', 'e', 'b', 'r', 9, 0, - /* 11487 */ 'l', 'p', 'e', 'b', 'r', 9, 0, - /* 11494 */ 's', 'q', 'e', 'b', 'r', 9, 0, - /* 11501 */ 'm', 's', 'e', 'b', 'r', 9, 0, - /* 11508 */ 'l', 't', 'e', 'b', 'r', 9, 0, - /* 11515 */ 'l', 'x', 'e', 'b', 'r', 9, 0, - /* 11522 */ 'c', 'd', 'f', 'b', 'r', 9, 0, - /* 11529 */ 'c', 'e', 'f', 'b', 'r', 9, 0, - /* 11536 */ 'c', 'd', 'l', 'f', 'b', 'r', 9, 0, - /* 11544 */ 'c', 'e', 'l', 'f', 'b', 'r', 9, 0, - /* 11552 */ 'c', 'x', 'l', 'f', 'b', 'r', 9, 0, - /* 11560 */ 'c', 'x', 'f', 'b', 'r', 9, 0, - /* 11567 */ 'c', 'd', 'g', 'b', 'r', 9, 0, - /* 11574 */ 'c', 'e', 'g', 'b', 'r', 9, 0, - /* 11581 */ 'c', 'd', 'l', 'g', 'b', 'r', 9, 0, - /* 11589 */ 'c', 'e', 'l', 'g', 'b', 'r', 9, 0, - /* 11597 */ 'c', 'x', 'l', 'g', 'b', 'r', 9, 0, - /* 11605 */ 'c', 'x', 'g', 'b', 'r', 9, 0, - /* 11612 */ 's', 'l', 'b', 'r', 9, 0, - /* 11618 */ 'a', 'x', 'b', 'r', 9, 0, - /* 11624 */ 'l', 'c', 'x', 'b', 'r', 9, 0, - /* 11631 */ 'l', 'd', 'x', 'b', 'r', 9, 0, - /* 11638 */ 'l', 'e', 'x', 'b', 'r', 9, 0, - /* 11645 */ 'c', 'f', 'x', 'b', 'r', 9, 0, - /* 11652 */ 'c', 'l', 'f', 'x', 'b', 'r', 9, 0, - /* 11660 */ 'c', 'g', 'x', 'b', 'r', 9, 0, - /* 11667 */ 'c', 'l', 'g', 'x', 'b', 'r', 9, 0, - /* 11675 */ 'f', 'i', 'x', 'b', 'r', 9, 0, - /* 11682 */ 'k', 'x', 'b', 'r', 9, 0, - /* 11688 */ 'm', 'x', 'b', 'r', 9, 0, - /* 11694 */ 'l', 'n', 'x', 'b', 'r', 9, 0, - /* 11701 */ 'l', 'p', 'x', 'b', 'r', 9, 0, - /* 11708 */ 's', 'q', 'x', 'b', 'r', 9, 0, - /* 11715 */ 's', 'x', 'b', 'r', 9, 0, - /* 11721 */ 'l', 't', 'x', 'b', 'r', 9, 0, - /* 11728 */ 'b', 'c', 'r', 9, 0, - /* 11733 */ 'l', 'l', 'g', 'c', 'r', 9, 0, - /* 11740 */ 'a', 'l', 'c', 'r', 9, 0, - /* 11746 */ 'l', 'l', 'c', 'r', 9, 0, - /* 11752 */ 'l', 'o', 'c', 'r', 9, 0, - /* 11758 */ 'm', 'a', 'd', 'r', 9, 0, - /* 11764 */ 't', 'b', 'd', 'r', 9, 0, - /* 11770 */ 'l', 'c', 'd', 'r', 9, 0, - /* 11776 */ 'd', 'd', 'r', 9, 0, - /* 11781 */ 't', 'b', 'e', 'd', 'r', 9, 0, - /* 11788 */ 'l', 'e', 'd', 'r', 9, 0, - /* 11794 */ 'c', 'f', 'd', 'r', 9, 0, - /* 11800 */ 'c', 'g', 'd', 'r', 9, 0, - /* 11806 */ 'l', 'g', 'd', 'r', 9, 0, - /* 11812 */ 't', 'h', 'd', 'r', 9, 0, - /* 11818 */ 'f', 'i', 'd', 'r', 9, 0, - /* 11824 */ 'l', 'd', 'r', 9, 0, - /* 11829 */ 'm', 'd', 'r', 9, 0, - /* 11834 */ 'l', 'n', 'd', 'r', 9, 0, - /* 11840 */ 'l', 'p', 'd', 'r', 9, 0, - /* 11846 */ 's', 'q', 'd', 'r', 9, 0, - /* 11852 */ 'l', 'r', 'd', 'r', 9, 0, - /* 11858 */ 'm', 's', 'd', 'r', 9, 0, - /* 11864 */ 'c', 'p', 's', 'd', 'r', 9, 0, - /* 11871 */ 'l', 't', 'd', 'r', 9, 0, - /* 11877 */ 'l', 'x', 'd', 'r', 9, 0, - /* 11883 */ 'm', 'x', 'd', 'r', 9, 0, - /* 11889 */ 'l', 'z', 'd', 'r', 9, 0, - /* 11895 */ 'm', 'a', 'e', 'r', 9, 0, - /* 11901 */ 'b', 'e', 'r', 9, 0, - /* 11906 */ 'l', 'c', 'e', 'r', 9, 0, - /* 11912 */ 't', 'h', 'd', 'e', 'r', 9, 0, - /* 11919 */ 'l', 'd', 'e', 'r', 9, 0, - /* 11925 */ 'm', 'd', 'e', 'r', 9, 0, - /* 11931 */ 'm', 'e', 'e', 'r', 9, 0, - /* 11937 */ 'c', 'f', 'e', 'r', 9, 0, - /* 11943 */ 'c', 'g', 'e', 'r', 9, 0, - /* 11949 */ 'b', 'h', 'e', 'r', 9, 0, - /* 11955 */ 'b', 'n', 'h', 'e', 'r', 9, 0, - /* 11962 */ 'f', 'i', 'e', 'r', 9, 0, - /* 11968 */ 'b', 'l', 'e', 'r', 9, 0, - /* 11974 */ 'b', 'n', 'l', 'e', 'r', 9, 0, - /* 11981 */ 'm', 'e', 'r', 9, 0, - /* 11986 */ 'b', 'n', 'e', 'r', 9, 0, - /* 11992 */ 'l', 'n', 'e', 'r', 9, 0, - /* 11998 */ 'l', 'p', 'e', 'r', 9, 0, - /* 12004 */ 's', 'q', 'e', 'r', 9, 0, - /* 12010 */ 'l', 'r', 'e', 'r', 9, 0, - /* 12016 */ 'm', 's', 'e', 'r', 9, 0, - /* 12022 */ 'l', 't', 'e', 'r', 9, 0, - /* 12028 */ 'l', 'x', 'e', 'r', 9, 0, - /* 12034 */ 'l', 'z', 'e', 'r', 9, 0, - /* 12040 */ 'l', 'c', 'd', 'f', 'r', 9, 0, - /* 12047 */ 'l', 'n', 'd', 'f', 'r', 9, 0, - /* 12054 */ 'l', 'p', 'd', 'f', 'r', 9, 0, - /* 12061 */ 'c', 'e', 'f', 'r', 9, 0, - /* 12067 */ 'a', 'g', 'f', 'r', 9, 0, - /* 12073 */ 'l', 'c', 'g', 'f', 'r', 9, 0, - /* 12080 */ 'a', 'l', 'g', 'f', 'r', 9, 0, - /* 12087 */ 'c', 'l', 'g', 'f', 'r', 9, 0, - /* 12094 */ 'l', 'l', 'g', 'f', 'r', 9, 0, - /* 12101 */ 's', 'l', 'g', 'f', 'r', 9, 0, - /* 12108 */ 'l', 'n', 'g', 'f', 'r', 9, 0, - /* 12115 */ 'l', 'p', 'g', 'f', 'r', 9, 0, - /* 12122 */ 'd', 's', 'g', 'f', 'r', 9, 0, - /* 12129 */ 'm', 's', 'g', 'f', 'r', 9, 0, - /* 12136 */ 'l', 't', 'g', 'f', 'r', 9, 0, - /* 12143 */ 'c', 'x', 'f', 'r', 9, 0, - /* 12149 */ 'a', 'g', 'r', 9, 0, - /* 12154 */ 's', 'l', 'b', 'g', 'r', 9, 0, - /* 12161 */ 'a', 'l', 'c', 'g', 'r', 9, 0, - /* 12168 */ 'l', 'o', 'c', 'g', 'r', 9, 0, - /* 12175 */ 'c', 'd', 'g', 'r', 9, 0, - /* 12181 */ 'l', 'd', 'g', 'r', 9, 0, - /* 12187 */ 'c', 'e', 'g', 'r', 9, 0, - /* 12193 */ 'a', 'l', 'g', 'r', 9, 0, - /* 12199 */ 'c', 'l', 'g', 'r', 9, 0, - /* 12205 */ 'd', 'l', 'g', 'r', 9, 0, - /* 12211 */ 'm', 'l', 'g', 'r', 9, 0, - /* 12217 */ 's', 'l', 'g', 'r', 9, 0, - /* 12223 */ 'l', 'n', 'g', 'r', 9, 0, - /* 12229 */ 'f', 'l', 'o', 'g', 'r', 9, 0, - /* 12236 */ 'l', 'p', 'g', 'r', 9, 0, - /* 12242 */ 'd', 's', 'g', 'r', 9, 0, - /* 12248 */ 'm', 's', 'g', 'r', 9, 0, - /* 12254 */ 'b', 'c', 't', 'g', 'r', 9, 0, - /* 12261 */ 'l', 't', 'g', 'r', 9, 0, - /* 12267 */ 'l', 'r', 'v', 'g', 'r', 9, 0, - /* 12274 */ 'c', 'x', 'g', 'r', 9, 0, - /* 12280 */ 'b', 'h', 'r', 9, 0, - /* 12285 */ 'l', 'o', 'c', 'f', 'h', 'r', 9, 0, - /* 12293 */ 'l', 'l', 'g', 'h', 'r', 9, 0, - /* 12300 */ 'c', 'h', 'h', 'r', 9, 0, - /* 12306 */ 'a', 'h', 'h', 'h', 'r', 9, 0, - /* 12313 */ 'a', 'l', 'h', 'h', 'h', 'r', 9, 0, - /* 12321 */ 's', 'l', 'h', 'h', 'h', 'r', 9, 0, - /* 12329 */ 's', 'h', 'h', 'h', 'r', 9, 0, - /* 12336 */ 'c', 'l', 'h', 'h', 'r', 9, 0, - /* 12343 */ 'b', 'l', 'h', 'r', 9, 0, - /* 12349 */ 'l', 'l', 'h', 'r', 9, 0, - /* 12355 */ 'b', 'n', 'l', 'h', 'r', 9, 0, - /* 12362 */ 'b', 'n', 'h', 'r', 9, 0, - /* 12368 */ 'm', 'a', 'y', 'h', 'r', 9, 0, - /* 12375 */ 'm', 'y', 'h', 'r', 9, 0, - /* 12381 */ 'e', 'p', 'a', 'i', 'r', 9, 0, - /* 12388 */ 'e', 's', 'a', 'i', 'r', 9, 0, - /* 12395 */ 's', 's', 'a', 'i', 'r', 9, 0, - /* 12402 */ 'b', 'a', 'k', 'r', 9, 0, - /* 12408 */ 'b', 'a', 'l', 'r', 9, 0, - /* 12414 */ 'b', 'l', 'r', 9, 0, - /* 12419 */ 'c', 'l', 'r', 9, 0, - /* 12424 */ 'd', 'l', 'r', 9, 0, - /* 12429 */ 'v', 'f', 'l', 'r', 9, 0, - /* 12435 */ 'c', 'h', 'l', 'r', 9, 0, - /* 12441 */ 'a', 'h', 'h', 'l', 'r', 9, 0, - /* 12448 */ 'a', 'l', 'h', 'h', 'l', 'r', 9, 0, - /* 12456 */ 's', 'l', 'h', 'h', 'l', 'r', 9, 0, - /* 12464 */ 's', 'h', 'h', 'l', 'r', 9, 0, - /* 12471 */ 'c', 'l', 'h', 'l', 'r', 9, 0, - /* 12478 */ 'm', 'l', 'r', 9, 0, - /* 12483 */ 'b', 'n', 'l', 'r', 9, 0, - /* 12489 */ 'v', 'l', 'r', 'l', 'r', 9, 0, - /* 12496 */ 'v', 's', 't', 'r', 'l', 'r', 9, 0, - /* 12504 */ 's', 'l', 'r', 9, 0, - /* 12509 */ 'v', 'l', 'r', 9, 0, - /* 12514 */ 'm', 'a', 'y', 'l', 'r', 9, 0, - /* 12521 */ 'm', 'y', 'l', 'r', 9, 0, - /* 12527 */ 'b', 'm', 'r', 9, 0, - /* 12532 */ 'b', 'n', 'm', 'r', 9, 0, - /* 12538 */ 'l', 'n', 'r', 9, 0, - /* 12543 */ 'b', 'o', 'r', 9, 0, - /* 12548 */ 'b', 'n', 'o', 'r', 9, 0, - /* 12554 */ 'b', 'p', 'r', 9, 0, - /* 12559 */ 'l', 'p', 'r', 9, 0, - /* 12564 */ 'b', 'n', 'p', 'r', 9, 0, - /* 12570 */ 'b', 'a', 's', 'r', 9, 0, - /* 12576 */ 's', 'f', 'a', 's', 'r', 9, 0, - /* 12583 */ 'm', 's', 'r', 9, 0, - /* 12588 */ 'b', 'c', 't', 'r', 9, 0, - /* 12594 */ 'e', 'c', 'c', 't', 'r', 9, 0, - /* 12601 */ 's', 'c', 'c', 't', 'r', 9, 0, - /* 12608 */ 'k', 'm', 'c', 't', 'r', 9, 0, - /* 12615 */ 'e', 'p', 'c', 't', 'r', 9, 0, - /* 12622 */ 's', 'p', 'c', 't', 'r', 9, 0, - /* 12629 */ 'q', 'a', 'd', 't', 'r', 9, 0, - /* 12636 */ 'c', 'd', 't', 'r', 9, 0, - /* 12642 */ 'd', 'd', 't', 'r', 9, 0, - /* 12648 */ 'c', 'e', 'd', 't', 'r', 9, 0, - /* 12655 */ 'e', 'e', 'd', 't', 'r', 9, 0, - /* 12662 */ 'i', 'e', 'd', 't', 'r', 9, 0, - /* 12669 */ 'l', 'e', 'd', 't', 'r', 9, 0, - /* 12676 */ 'c', 'f', 'd', 't', 'r', 9, 0, - /* 12683 */ 'c', 'l', 'f', 'd', 't', 'r', 9, 0, - /* 12691 */ 'c', 'g', 'd', 't', 'r', 9, 0, - /* 12698 */ 'c', 'l', 'g', 'd', 't', 'r', 9, 0, - /* 12706 */ 'f', 'i', 'd', 't', 'r', 9, 0, - /* 12713 */ 'k', 'd', 't', 'r', 9, 0, - /* 12719 */ 'm', 'd', 't', 'r', 9, 0, - /* 12725 */ 'r', 'r', 'd', 't', 'r', 9, 0, - /* 12732 */ 'c', 's', 'd', 't', 'r', 9, 0, - /* 12739 */ 'e', 's', 'd', 't', 'r', 9, 0, - /* 12746 */ 'l', 't', 'd', 't', 'r', 9, 0, - /* 12753 */ 'c', 'u', 'd', 't', 'r', 9, 0, - /* 12760 */ 'l', 'x', 'd', 't', 'r', 9, 0, - /* 12767 */ 'l', 'd', 'e', 't', 'r', 9, 0, - /* 12774 */ 'c', 'd', 'f', 't', 'r', 9, 0, - /* 12781 */ 'c', 'd', 'l', 'f', 't', 'r', 9, 0, - /* 12789 */ 'c', 'x', 'l', 'f', 't', 'r', 9, 0, - /* 12797 */ 'c', 'x', 'f', 't', 'r', 9, 0, - /* 12804 */ 'c', 'd', 'g', 't', 'r', 9, 0, - /* 12811 */ 'c', 'd', 'l', 'g', 't', 'r', 9, 0, - /* 12819 */ 'l', 'l', 'g', 't', 'r', 9, 0, - /* 12826 */ 'c', 'x', 'l', 'g', 't', 'r', 9, 0, - /* 12834 */ 'c', 'x', 'g', 't', 'r', 9, 0, - /* 12841 */ 'l', 't', 'r', 9, 0, - /* 12846 */ 't', 'r', 't', 'r', 9, 0, - /* 12852 */ 'c', 'd', 's', 't', 'r', 9, 0, - /* 12859 */ 'v', 'i', 's', 't', 'r', 9, 0, - /* 12866 */ 'c', 'x', 's', 't', 'r', 9, 0, - /* 12873 */ 'c', 'd', 'u', 't', 'r', 9, 0, - /* 12880 */ 'c', 'x', 'u', 't', 'r', 9, 0, - /* 12887 */ 'q', 'a', 'x', 't', 'r', 9, 0, - /* 12894 */ 'c', 'x', 't', 'r', 9, 0, - /* 12900 */ 'l', 'd', 'x', 't', 'r', 9, 0, - /* 12907 */ 'c', 'e', 'x', 't', 'r', 9, 0, - /* 12914 */ 'e', 'e', 'x', 't', 'r', 9, 0, - /* 12921 */ 'i', 'e', 'x', 't', 'r', 9, 0, - /* 12928 */ 'c', 'f', 'x', 't', 'r', 9, 0, - /* 12935 */ 'c', 'l', 'f', 'x', 't', 'r', 9, 0, - /* 12943 */ 'c', 'g', 'x', 't', 'r', 9, 0, - /* 12950 */ 'c', 'l', 'g', 'x', 't', 'r', 9, 0, - /* 12958 */ 'f', 'i', 'x', 't', 'r', 9, 0, - /* 12965 */ 'k', 'x', 't', 'r', 9, 0, - /* 12971 */ 'm', 'x', 't', 'r', 9, 0, - /* 12977 */ 'r', 'r', 'x', 't', 'r', 9, 0, - /* 12984 */ 'c', 's', 'x', 't', 'r', 9, 0, - /* 12991 */ 'e', 's', 'x', 't', 'r', 9, 0, - /* 12998 */ 'l', 't', 'x', 't', 'r', 9, 0, - /* 13005 */ 'c', 'u', 'x', 't', 'r', 9, 0, - /* 13012 */ 'a', 'u', 'r', 9, 0, - /* 13017 */ 's', 'u', 'r', 9, 0, - /* 13022 */ 'l', 'r', 'v', 'r', 9, 0, - /* 13028 */ 'a', 'w', 'r', 9, 0, - /* 13033 */ 's', 'w', 'r', 9, 0, - /* 13038 */ 'a', 'x', 'r', 9, 0, - /* 13043 */ 'l', 'c', 'x', 'r', 9, 0, - /* 13049 */ 'l', 'd', 'x', 'r', 9, 0, - /* 13055 */ 'l', 'e', 'x', 'r', 9, 0, - /* 13061 */ 'c', 'f', 'x', 'r', 9, 0, - /* 13067 */ 'c', 'g', 'x', 'r', 9, 0, - /* 13073 */ 'f', 'i', 'x', 'r', 9, 0, - /* 13079 */ 'l', 'x', 'r', 9, 0, - /* 13084 */ 'm', 'x', 'r', 9, 0, - /* 13089 */ 'l', 'n', 'x', 'r', 9, 0, - /* 13095 */ 'l', 'p', 'x', 'r', 9, 0, - /* 13101 */ 's', 'q', 'x', 'r', 9, 0, - /* 13107 */ 's', 'x', 'r', 9, 0, - /* 13112 */ 'l', 't', 'x', 'r', 9, 0, - /* 13118 */ 'l', 'z', 'x', 'r', 9, 0, - /* 13124 */ 'm', 'a', 'y', 'r', 9, 0, - /* 13130 */ 'm', 'y', 'r', 9, 0, - /* 13135 */ 'b', 'z', 'r', 9, 0, - /* 13140 */ 'b', 'n', 'z', 'r', 9, 0, - /* 13146 */ 'b', 'a', 's', 9, 0, - /* 13151 */ 'l', 'f', 'a', 's', 9, 0, - /* 13157 */ 'b', 'r', 'a', 's', 9, 0, - /* 13163 */ 'v', 's', 't', 'r', 'c', 'b', 's', 9, 0, - /* 13172 */ 'v', 'f', 'c', 'e', 'd', 'b', 's', 9, 0, - /* 13181 */ 'w', 'f', 'c', 'e', 'd', 'b', 's', 9, 0, - /* 13190 */ 'v', 'f', 'c', 'h', 'e', 'd', 'b', 's', 9, 0, - /* 13200 */ 'w', 'f', 'c', 'h', 'e', 'd', 'b', 's', 9, 0, - /* 13210 */ 'v', 'f', 'k', 'h', 'e', 'd', 'b', 's', 9, 0, - /* 13220 */ 'w', 'f', 'k', 'h', 'e', 'd', 'b', 's', 9, 0, - /* 13230 */ 'v', 'f', 'k', 'e', 'd', 'b', 's', 9, 0, - /* 13239 */ 'w', 'f', 'k', 'e', 'd', 'b', 's', 9, 0, - /* 13248 */ 'v', 'f', 'c', 'h', 'd', 'b', 's', 9, 0, - /* 13257 */ 'w', 'f', 'c', 'h', 'd', 'b', 's', 9, 0, - /* 13266 */ 'v', 'f', 'k', 'h', 'd', 'b', 's', 9, 0, - /* 13275 */ 'w', 'f', 'k', 'h', 'd', 'b', 's', 9, 0, - /* 13284 */ 'v', 'f', 'a', 'e', 'b', 's', 9, 0, - /* 13292 */ 'v', 'f', 'e', 'e', 'b', 's', 9, 0, - /* 13300 */ 'v', 'f', 'e', 'n', 'e', 'b', 's', 9, 0, - /* 13309 */ 'v', 'c', 'h', 'b', 's', 9, 0, - /* 13316 */ 'v', 'c', 'h', 'l', 'b', 's', 9, 0, - /* 13324 */ 'v', 'c', 'e', 'q', 'b', 's', 9, 0, - /* 13332 */ 'v', 'i', 's', 't', 'r', 'b', 's', 9, 0, - /* 13341 */ 'v', 'f', 'c', 'e', 's', 'b', 's', 9, 0, - /* 13350 */ 'w', 'f', 'c', 'e', 's', 'b', 's', 9, 0, - /* 13359 */ 'v', 'f', 'c', 'h', 'e', 's', 'b', 's', 9, 0, - /* 13369 */ 'w', 'f', 'c', 'h', 'e', 's', 'b', 's', 9, 0, - /* 13379 */ 'v', 'f', 'k', 'h', 'e', 's', 'b', 's', 9, 0, - /* 13389 */ 'w', 'f', 'k', 'h', 'e', 's', 'b', 's', 9, 0, - /* 13399 */ 'v', 'f', 'k', 'e', 's', 'b', 's', 9, 0, - /* 13408 */ 'w', 'f', 'k', 'e', 's', 'b', 's', 9, 0, - /* 13417 */ 'v', 'f', 'c', 'h', 's', 'b', 's', 9, 0, - /* 13426 */ 'w', 'f', 'c', 'h', 's', 'b', 's', 9, 0, - /* 13435 */ 'v', 'f', 'k', 'h', 's', 'b', 's', 9, 0, - /* 13444 */ 'w', 'f', 'k', 'h', 's', 'b', 's', 9, 0, - /* 13453 */ 'w', 'f', 'c', 'e', 'x', 'b', 's', 9, 0, - /* 13462 */ 'w', 'f', 'c', 'h', 'e', 'x', 'b', 's', 9, 0, - /* 13472 */ 'w', 'f', 'k', 'h', 'e', 'x', 'b', 's', 9, 0, - /* 13482 */ 'w', 'f', 'k', 'e', 'x', 'b', 's', 9, 0, - /* 13491 */ 'w', 'f', 'c', 'h', 'x', 'b', 's', 9, 0, - /* 13500 */ 'w', 'f', 'k', 'h', 'x', 'b', 's', 9, 0, - /* 13509 */ 'v', 's', 't', 'r', 'c', 'z', 'b', 's', 9, 0, - /* 13519 */ 'v', 'f', 'a', 'e', 'z', 'b', 's', 9, 0, - /* 13528 */ 'v', 'f', 'e', 'e', 'z', 'b', 's', 9, 0, - /* 13537 */ 'v', 'f', 'e', 'n', 'e', 'z', 'b', 's', 9, 0, - /* 13547 */ 'm', 'v', 'c', 's', 9, 0, - /* 13553 */ 'c', 'd', 's', 9, 0, - /* 13558 */ 'v', 's', 't', 'r', 'c', 'f', 's', 9, 0, - /* 13567 */ 'v', 'f', 'a', 'e', 'f', 's', 9, 0, - /* 13575 */ 'v', 'f', 'e', 'e', 'f', 's', 9, 0, - /* 13583 */ 'v', 'f', 'e', 'n', 'e', 'f', 's', 9, 0, - /* 13592 */ 'v', 'c', 'h', 'f', 's', 9, 0, - /* 13599 */ 'v', 'c', 'h', 'l', 'f', 's', 9, 0, - /* 13607 */ 'v', 'c', 'e', 'q', 'f', 's', 9, 0, - /* 13615 */ 'v', 'i', 's', 't', 'r', 'f', 's', 9, 0, - /* 13624 */ 'v', 'p', 'k', 's', 'f', 's', 9, 0, - /* 13632 */ 'v', 'p', 'k', 'l', 's', 'f', 's', 9, 0, - /* 13641 */ 'v', 'f', 's', 9, 0, - /* 13646 */ 'v', 's', 't', 'r', 'c', 'z', 'f', 's', 9, 0, - /* 13656 */ 'v', 'f', 'a', 'e', 'z', 'f', 's', 9, 0, - /* 13665 */ 'v', 'f', 'e', 'e', 'z', 'f', 's', 9, 0, - /* 13674 */ 'v', 'f', 'e', 'n', 'e', 'z', 'f', 's', 9, 0, - /* 13684 */ 'v', 'c', 'h', 'g', 's', 9, 0, - /* 13691 */ 'v', 'c', 'h', 'l', 'g', 's', 9, 0, - /* 13699 */ 'v', 'c', 'e', 'q', 'g', 's', 9, 0, - /* 13707 */ 'v', 'p', 'k', 's', 'g', 's', 9, 0, - /* 13715 */ 'v', 'p', 'k', 'l', 's', 'g', 's', 9, 0, - /* 13724 */ 'v', 's', 't', 'r', 'c', 'h', 's', 9, 0, - /* 13733 */ 'v', 'f', 'a', 'e', 'h', 's', 9, 0, - /* 13741 */ 'v', 'f', 'e', 'e', 'h', 's', 9, 0, - /* 13749 */ 'v', 'f', 'e', 'n', 'e', 'h', 's', 9, 0, - /* 13758 */ 'v', 'c', 'h', 'h', 's', 9, 0, - /* 13765 */ 'v', 'c', 'h', 'l', 'h', 's', 9, 0, - /* 13773 */ 'v', 'c', 'e', 'q', 'h', 's', 9, 0, - /* 13781 */ 'v', 'i', 's', 't', 'r', 'h', 's', 9, 0, - /* 13790 */ 'v', 'p', 'k', 's', 'h', 's', 9, 0, - /* 13798 */ 'v', 'p', 'k', 'l', 's', 'h', 's', 9, 0, - /* 13807 */ 'v', 's', 't', 'r', 'c', 'z', 'h', 's', 9, 0, - /* 13817 */ 'v', 'f', 'a', 'e', 'z', 'h', 's', 9, 0, - /* 13826 */ 'v', 'f', 'e', 'e', 'z', 'h', 's', 9, 0, - /* 13835 */ 'v', 'f', 'e', 'n', 'e', 'z', 'h', 's', 9, 0, - /* 13845 */ 'v', 'p', 'k', 's', 9, 0, - /* 13851 */ 'v', 'p', 'k', 'l', 's', 9, 0, - /* 13858 */ 'v', 'f', 'l', 'l', 's', 9, 0, - /* 13865 */ 'w', 'f', 'l', 'l', 's', 9, 0, - /* 13872 */ 'v', 'f', 'm', 's', 9, 0, - /* 13878 */ 'v', 'f', 'n', 'm', 's', 9, 0, - /* 13885 */ 'm', 'v', 'c', 'o', 's', 9, 0, - /* 13892 */ 's', 't', 'c', 'p', 's', 9, 0, - /* 13899 */ 't', 's', 9, 0, - /* 13903 */ 'v', 's', 9, 0, - /* 13907 */ 'l', 'l', 'g', 'f', 'a', 't', 9, 0, - /* 13915 */ 'l', 'g', 'a', 't', 9, 0, - /* 13921 */ 'l', 'f', 'h', 'a', 't', 9, 0, - /* 13928 */ 'l', 'a', 't', 9, 0, - /* 13933 */ 'l', 'l', 'g', 't', 'a', 't', 9, 0, - /* 13941 */ 'b', 'c', 't', 9, 0, - /* 13946 */ 'v', 'p', 'o', 'p', 'c', 't', 9, 0, - /* 13954 */ 'b', 'r', 'c', 't', 9, 0, - /* 13960 */ 't', 'd', 'c', 'd', 't', 9, 0, - /* 13967 */ 't', 'd', 'g', 'd', 't', 9, 0, - /* 13974 */ 's', 'l', 'd', 't', 9, 0, - /* 13980 */ 'c', 'p', 'd', 't', 9, 0, - /* 13986 */ 's', 'r', 'd', 't', 9, 0, - /* 13992 */ 'c', 'z', 'd', 't', 9, 0, - /* 13998 */ 't', 'd', 'c', 'e', 't', 9, 0, - /* 14005 */ 't', 'd', 'g', 'e', 't', 9, 0, - /* 14012 */ 'c', 'l', 'g', 't', 9, 0, - /* 14018 */ 'l', 'l', 'g', 't', 9, 0, - /* 14024 */ 'c', 'i', 't', 9, 0, - /* 14029 */ 'c', 'l', 'f', 'i', 't', 9, 0, - /* 14036 */ 'c', 'g', 'i', 't', 9, 0, - /* 14042 */ 'c', 'l', 'g', 'i', 't', 9, 0, - /* 14049 */ 'c', 'l', 't', 9, 0, - /* 14054 */ 's', 'r', 'n', 'm', 't', 9, 0, - /* 14061 */ 'p', 'o', 'p', 'c', 'n', 't', 9, 0, - /* 14069 */ 't', 'p', 'r', 'o', 't', 9, 0, - /* 14076 */ 't', 'r', 'o', 't', 9, 0, - /* 14082 */ 'c', 'd', 'p', 't', 9, 0, - /* 14088 */ 's', 'p', 't', 9, 0, - /* 14093 */ 's', 't', 'p', 't', 9, 0, - /* 14099 */ 'c', 'x', 'p', 't', 9, 0, - /* 14105 */ 'c', 'r', 't', 9, 0, - /* 14110 */ 'c', 'g', 'r', 't', 9, 0, - /* 14116 */ 'c', 'l', 'g', 'r', 't', 9, 0, - /* 14123 */ 'c', 'l', 'r', 't', 9, 0, - /* 14129 */ 't', 'a', 'b', 'o', 'r', 't', 9, 0, - /* 14137 */ 't', 'r', 't', 9, 0, - /* 14142 */ 'c', 'l', 's', 't', 9, 0, - /* 14148 */ 's', 'r', 's', 't', 9, 0, - /* 14154 */ 'c', 's', 's', 't', 9, 0, - /* 14160 */ 'm', 'v', 's', 't', 9, 0, - /* 14166 */ 't', 'r', 't', 't', 9, 0, - /* 14172 */ 'p', 'g', 'o', 'u', 't', 9, 0, - /* 14179 */ 't', 'd', 'c', 'x', 't', 9, 0, - /* 14186 */ 't', 'd', 'g', 'x', 't', 9, 0, - /* 14193 */ 's', 'l', 'x', 't', 9, 0, - /* 14199 */ 'c', 'p', 'x', 't', 9, 0, - /* 14205 */ 's', 'r', 'x', 't', 9, 0, - /* 14211 */ 'c', 'z', 'x', 't', 9, 0, - /* 14217 */ 'c', 'd', 'z', 't', 9, 0, - /* 14223 */ 'c', 'x', 'z', 't', 9, 0, - /* 14229 */ 'a', 'u', 9, 0, - /* 14233 */ 'c', 'u', 't', 'f', 'u', 9, 0, - /* 14240 */ 'u', 'n', 'p', 'k', 'u', 9, 0, - /* 14247 */ 'c', 'l', 'c', 'l', 'u', 9, 0, - /* 14254 */ 'm', 'v', 'c', 'l', 'u', 9, 0, - /* 14261 */ 's', 'u', 9, 0, - /* 14265 */ 's', 'r', 's', 't', 'u', 9, 0, - /* 14272 */ 'v', 'e', 's', 'r', 'a', 'v', 9, 0, - /* 14280 */ 'v', 'l', 'g', 'v', 9, 0, - /* 14286 */ 'v', 'e', 'r', 'l', 'l', 'v', 9, 0, - /* 14294 */ 'v', 'e', 's', 'r', 'l', 'v', 9, 0, - /* 14302 */ 'v', 'e', 's', 'l', 'v', 9, 0, - /* 14309 */ 'l', 'r', 'v', 9, 0, - /* 14314 */ 's', 't', 'r', 'v', 9, 0, - /* 14320 */ 'a', 'w', 9, 0, - /* 14324 */ 'v', 'm', 'a', 'l', 'h', 'w', 9, 0, - /* 14332 */ 'v', 'm', 'l', 'h', 'w', 9, 0, - /* 14339 */ 'v', 'u', 'p', 'l', 'h', 'w', 9, 0, - /* 14347 */ 's', 't', 'c', 'r', 'w', 9, 0, - /* 14354 */ 'e', 'p', 's', 'w', 9, 0, - /* 14360 */ 'l', 'p', 's', 'w', 9, 0, - /* 14366 */ 'l', 'a', 'x', 9, 0, - /* 14371 */ 'v', 'f', 'm', 'a', 'x', 9, 0, - /* 14378 */ 'e', 'x', 9, 0, - /* 14382 */ 'v', 'm', 'x', 9, 0, - /* 14387 */ 'v', 'n', 'x', 9, 0, - /* 14392 */ 's', 'p', 'x', 9, 0, - /* 14397 */ 's', 't', 'p', 'x', 9, 0, - /* 14403 */ 'w', 'f', 'l', 'r', 'x', 9, 0, - /* 14410 */ 'v', 'x', 9, 0, - /* 14414 */ 'l', 'a', 'y', 9, 0, - /* 14419 */ 'm', 'a', 'y', 9, 0, - /* 14424 */ 'l', 'r', 'a', 'y', 9, 0, - /* 14430 */ 'c', 'v', 'b', 'y', 9, 0, - /* 14436 */ 'i', 'c', 'y', 9, 0, - /* 14441 */ 's', 't', 'c', 'y', 9, 0, - /* 14447 */ 'l', 'd', 'y', 9, 0, - /* 14452 */ 's', 't', 'd', 'y', 9, 0, - /* 14458 */ 'c', 'v', 'd', 'y', 9, 0, - /* 14464 */ 'l', 'a', 'e', 'y', 9, 0, - /* 14470 */ 'l', 'e', 'y', 9, 0, - /* 14475 */ 's', 't', 'e', 'y', 9, 0, - /* 14481 */ 'm', 'f', 'y', 9, 0, - /* 14486 */ 'a', 'h', 'y', 9, 0, - /* 14491 */ 'c', 'h', 'y', 9, 0, - /* 14496 */ 'l', 'h', 'y', 9, 0, - /* 14501 */ 'm', 'h', 'y', 9, 0, - /* 14506 */ 's', 'h', 'y', 9, 0, - /* 14511 */ 's', 't', 'h', 'y', 9, 0, - /* 14517 */ 'c', 'l', 'i', 'y', 9, 0, - /* 14523 */ 'n', 'i', 'y', 9, 0, - /* 14528 */ 'o', 'i', 'y', 9, 0, - /* 14533 */ 'm', 'v', 'i', 'y', 9, 0, - /* 14539 */ 'x', 'i', 'y', 9, 0, - /* 14544 */ 'a', 'l', 'y', 9, 0, - /* 14549 */ 'c', 'l', 'y', 9, 0, - /* 14554 */ 's', 'l', 'y', 9, 0, - /* 14559 */ 'l', 'a', 'm', 'y', 9, 0, - /* 14565 */ 's', 't', 'a', 'm', 'y', 9, 0, - /* 14572 */ 'i', 'c', 'm', 'y', 9, 0, - /* 14578 */ 's', 't', 'c', 'm', 'y', 9, 0, - /* 14585 */ 'c', 'l', 'm', 'y', 9, 0, - /* 14591 */ 's', 't', 'm', 'y', 9, 0, - /* 14597 */ 'n', 'y', 9, 0, - /* 14601 */ 'o', 'y', 9, 0, - /* 14605 */ 'c', 's', 'y', 9, 0, - /* 14610 */ 'c', 'd', 's', 'y', 9, 0, - /* 14616 */ 'm', 's', 'y', 9, 0, - /* 14621 */ 's', 't', 'y', 9, 0, - /* 14626 */ 'x', 'y', 9, 0, - /* 14630 */ 'b', 'z', 9, 0, - /* 14634 */ 'l', 'o', 'c', 'z', 9, 0, - /* 14640 */ 's', 't', 'o', 'c', 'z', 9, 0, - /* 14647 */ 'v', 'l', 'l', 'e', 'z', 9, 0, - /* 14654 */ 'l', 'o', 'c', 'g', 'z', 9, 0, - /* 14661 */ 's', 't', 'o', 'c', 'g', 'z', 9, 0, - /* 14669 */ 'j', 'g', 'z', 9, 0, - /* 14674 */ 'l', 'o', 'c', 'f', 'h', 'z', 9, 0, - /* 14682 */ 's', 't', 'o', 'c', 'f', 'h', 'z', 9, 0, - /* 14691 */ 'b', 'i', 'z', 9, 0, - /* 14696 */ 'l', 'o', 'c', 'h', 'i', 'z', 9, 0, - /* 14704 */ 'l', 'o', 'c', 'g', 'h', 'i', 'z', 9, 0, - /* 14713 */ 'l', 'o', 'c', 'h', 'h', 'i', 'z', 9, 0, - /* 14722 */ 'j', 'z', 9, 0, - /* 14726 */ 'v', 'u', 'p', 'k', 'z', 9, 0, - /* 14733 */ 'v', 'p', 'k', 'z', 9, 0, - /* 14739 */ 'v', 'c', 'l', 'z', 9, 0, - /* 14745 */ 'b', 'n', 'z', 9, 0, - /* 14750 */ 'l', 'o', 'c', 'n', 'z', 9, 0, - /* 14757 */ 's', 't', 'o', 'c', 'n', 'z', 9, 0, - /* 14765 */ 'l', 'o', 'c', 'g', 'n', 'z', 9, 0, - /* 14773 */ 's', 't', 'o', 'c', 'g', 'n', 'z', 9, 0, - /* 14782 */ 'j', 'g', 'n', 'z', 9, 0, - /* 14788 */ 'l', 'o', 'c', 'f', 'h', 'n', 'z', 9, 0, - /* 14797 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'z', 9, 0, - /* 14807 */ 'b', 'i', 'n', 'z', 9, 0, - /* 14813 */ 'l', 'o', 'c', 'h', 'i', 'n', 'z', 9, 0, - /* 14822 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'z', 9, 0, - /* 14832 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'z', 9, 0, - /* 14842 */ 'j', 'n', 'z', 9, 0, - /* 14847 */ 'l', 'o', 'c', 'r', 'n', 'z', 9, 0, - /* 14855 */ 'l', 'o', 'c', 'g', 'r', 'n', 'z', 9, 0, - /* 14864 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'z', 9, 0, - /* 14874 */ 'l', 'o', 'c', 'r', 'z', 9, 0, - /* 14881 */ 'l', 'o', 'c', 'g', 'r', 'z', 9, 0, - /* 14889 */ 'l', 'o', 'c', 'f', 'h', 'r', 'z', 9, 0, - /* 14898 */ 'v', 'c', 't', 'z', 9, 0, - /* 14904 */ 'm', 'v', 'z', 9, 0, - /* 14909 */ '.', 'i', 'n', 's', 'n', 32, 'e', ',', 0, - /* 14918 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 'e', ',', 0, - /* 14929 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', 'e', ',', 0, - /* 14940 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', 'e', ',', 0, - /* 14951 */ '.', 'i', 'n', 's', 'n', 32, 's', 's', 'e', ',', 0, - /* 14962 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', 'e', ',', 0, - /* 14973 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', 'f', ',', 0, - /* 14984 */ '.', 'i', 'n', 's', 'n', 32, 's', 's', 'f', ',', 0, - /* 14995 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', 'f', ',', 0, - /* 15006 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', ',', 0, - /* 15016 */ '.', 'i', 'n', 's', 'n', 32, 's', 'i', ',', 0, - /* 15026 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', 'i', ',', 0, - /* 15037 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 'l', ',', 0, - /* 15048 */ '.', 'i', 'n', 's', 'n', 32, 's', 'i', 'l', ',', 0, - /* 15059 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', ',', 0, - /* 15069 */ '.', 'i', 'n', 's', 'n', 32, 's', ',', 0, - /* 15078 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 's', ',', 0, - /* 15089 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', ',', 0, - /* 15099 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', 's', ',', 0, - /* 15110 */ '.', 'i', 'n', 's', 'n', 32, 's', 's', ',', 0, - /* 15120 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 'l', 'u', ',', 0, - /* 15132 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', ',', 0, - /* 15142 */ '.', 'i', 'n', 's', 'n', 32, 's', 'i', 'y', ',', 0, - /* 15153 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', 'y', ',', 0, - /* 15164 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', 'y', ',', 0, - /* 15175 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, - /* 15206 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 15230 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 15255 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, - /* 15278 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, - /* 15301 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, - /* 15323 */ 's', 'a', 'm', '3', '1', 0, - /* 15329 */ 't', 'r', 'a', 'p', '2', 0, - /* 15335 */ 's', 'a', 'm', '2', '4', 0, - /* 15341 */ 's', 'a', 'm', '6', '4', 0, - /* 15347 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 15360 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 15367 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 15377 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, - /* 15387 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 15402 */ 'c', 'i', 'b', 0, - /* 15406 */ 'c', 'g', 'i', 'b', 0, - /* 15411 */ 'c', 'l', 'g', 'i', 'b', 0, - /* 15417 */ 'c', 'l', 'i', 'b', 0, - /* 15422 */ 'p', 'a', 'l', 'b', 0, - /* 15427 */ 'p', 't', 'l', 'b', 0, - /* 15432 */ 'c', 'r', 'b', 0, - /* 15436 */ 'c', 'g', 'r', 'b', 0, - /* 15441 */ 'c', 'l', 'g', 'r', 'b', 0, - /* 15447 */ 'c', 'l', 'r', 'b', 0, - /* 15452 */ 'p', 'c', 'c', 0, - /* 15456 */ 'l', 'o', 'c', 0, - /* 15460 */ 's', 't', 'o', 'c', 0, - /* 15465 */ 't', 'e', 'n', 'd', 0, - /* 15470 */ 'p', 't', 'f', 'f', 0, - /* 15475 */ 's', 'c', 'k', 'p', 'f', 0, - /* 15481 */ 'l', 'o', 'c', 'g', 0, - /* 15486 */ 's', 't', 'o', 'c', 'g', 0, - /* 15492 */ 'j', 'g', 0, - /* 15495 */ 'c', 's', 'c', 'h', 0, - /* 15500 */ 'h', 's', 'c', 'h', 0, - /* 15505 */ 'r', 's', 'c', 'h', 0, - /* 15510 */ 'x', 's', 'c', 'h', 0, - /* 15515 */ 'l', 'o', 'c', 'f', 'h', 0, - /* 15521 */ 's', 't', 'o', 'c', 'f', 'h', 0, - /* 15528 */ 'b', 'i', 0, - /* 15531 */ 'l', 'o', 'c', 'h', 'i', 0, - /* 15537 */ 'l', 'o', 'c', 'g', 'h', 'i', 0, - /* 15544 */ 'l', 'o', 'c', 'h', 'h', 'i', 0, - /* 15551 */ 'c', 'i', 'j', 0, - /* 15555 */ 'c', 'g', 'i', 'j', 0, - /* 15560 */ 'c', 'l', 'g', 'i', 'j', 0, - /* 15566 */ 'c', 'l', 'i', 'j', 0, - /* 15571 */ 'c', 'r', 'j', 0, - /* 15575 */ 'c', 'g', 'r', 'j', 0, - /* 15580 */ 'c', 'l', 'g', 'r', 'j', 0, - /* 15586 */ 'c', 'l', 'r', 'j', 0, - /* 15591 */ 'i', 'p', 'k', 0, - /* 15595 */ 's', 'a', 'l', 0, - /* 15599 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, - /* 15613 */ 't', 'a', 'm', 0, - /* 15617 */ 's', 'c', 'h', 'm', 0, - /* 15622 */ 'p', 'c', 'k', 'm', 'o', 0, - /* 15628 */ 'p', 'f', 'p', 'o', 0, - /* 15633 */ 'r', 'c', 'h', 'p', 0, - /* 15638 */ 'l', 'o', 'c', 'r', 0, - /* 15643 */ 'l', 'o', 'c', 'g', 'r', 0, - /* 15649 */ 'l', 'o', 'c', 'f', 'h', 'r', 0, - /* 15656 */ 'p', 'r', 0, - /* 15659 */ 'c', 'l', 'g', 't', 0, - /* 15664 */ 'c', 'i', 't', 0, - /* 15668 */ 'c', 'l', 'f', 'i', 't', 0, - /* 15674 */ 'c', 'g', 'i', 't', 0, - /* 15679 */ 'c', 'l', 'g', 'i', 't', 0, - /* 15685 */ 'c', 'l', 't', 0, - /* 15689 */ 'u', 'p', 't', 0, - /* 15693 */ 'c', 'r', 't', 0, - /* 15697 */ 'c', 'g', 'r', 't', 0, - /* 15702 */ 'c', 'l', 'g', 'r', 't', 0, - /* 15708 */ 'c', 'l', 'r', 't', 0, + /* 0 */ 'c', + 'u', + '2', + '1', + 9, + 0, + /* 6 */ 'c', + 'u', + '4', + '1', + 9, + 0, + /* 12 */ 'c', + 'u', + '1', + '2', + 9, + 0, + /* 18 */ 'c', + 'u', + '4', + '2', + 9, + 0, + /* 24 */ 'c', + 'u', + '1', + '4', + 9, + 0, + /* 30 */ 'c', + 'u', + '2', + '4', + 9, + 0, + /* 36 */ 't', + 'r', + 'a', + 'p', + '4', + 9, + 0, + /* 43 */ 'l', + 'a', + 'a', + 9, + 0, + /* 48 */ 's', + 'l', + 'd', + 'a', + 9, + 0, + /* 54 */ 's', + 'r', + 'd', + 'a', + 9, + 0, + /* 60 */ 'e', + 's', + 'e', + 'a', + 9, + 0, + /* 66 */ 'l', + 'p', + 't', + 'e', + 'a', + 9, + 0, + /* 73 */ 'v', + 'f', + 'a', + 9, + 0, + /* 78 */ 's', + 'i', + 'g', + 'a', + 9, + 0, + /* 84 */ 'e', + 'c', + 'p', + 'g', + 'a', + 9, + 0, + /* 91 */ 'u', + 'n', + 'p', + 'k', + 'a', + 9, + 0, + /* 98 */ 's', + 'p', + 'k', + 'a', + 9, + 0, + /* 104 */ 's', + 'l', + 'a', + 9, + 0, + /* 109 */ 'v', + 'g', + 'f', + 'm', + 'a', + 9, + 0, + /* 116 */ 'v', + 'f', + 'm', + 'a', + 9, + 0, + /* 122 */ 'k', + 'm', + 'a', + 9, + 0, + /* 127 */ 'v', + 'f', + 'n', + 'm', + 'a', + 9, + 0, + /* 134 */ 'p', + 'p', + 'a', + 9, + 0, + /* 139 */ 'l', + 'e', + 'd', + 'b', + 'r', + 'a', + 9, + 0, + /* 147 */ 'c', + 'f', + 'd', + 'b', + 'r', + 'a', + 9, + 0, + /* 155 */ 'c', + 'g', + 'd', + 'b', + 'r', + 'a', + 9, + 0, + /* 163 */ 'f', + 'i', + 'd', + 'b', + 'r', + 'a', + 9, + 0, + /* 171 */ 'c', + 'f', + 'e', + 'b', + 'r', + 'a', + 9, + 0, + /* 179 */ 'c', + 'g', + 'e', + 'b', + 'r', + 'a', + 9, + 0, + /* 187 */ 'f', + 'i', + 'e', + 'b', + 'r', + 'a', + 9, + 0, + /* 195 */ 'c', + 'd', + 'f', + 'b', + 'r', + 'a', + 9, + 0, + /* 203 */ 'c', + 'e', + 'f', + 'b', + 'r', + 'a', + 9, + 0, + /* 211 */ 'c', + 'x', + 'f', + 'b', + 'r', + 'a', + 9, + 0, + /* 219 */ 'c', + 'd', + 'g', + 'b', + 'r', + 'a', + 9, + 0, + /* 227 */ 'c', + 'e', + 'g', + 'b', + 'r', + 'a', + 9, + 0, + /* 235 */ 'c', + 'x', + 'g', + 'b', + 'r', + 'a', + 9, + 0, + /* 243 */ 'l', + 'd', + 'x', + 'b', + 'r', + 'a', + 9, + 0, + /* 251 */ 'l', + 'e', + 'x', + 'b', + 'r', + 'a', + 9, + 0, + /* 259 */ 'c', + 'f', + 'x', + 'b', + 'r', + 'a', + 9, + 0, + /* 267 */ 'c', + 'g', + 'x', + 'b', + 'r', + 'a', + 9, + 0, + /* 275 */ 'f', + 'i', + 'x', + 'b', + 'r', + 'a', + 9, + 0, + /* 283 */ 'l', + 'r', + 'a', + 9, + 0, + /* 288 */ 'v', + 'e', + 's', + 'r', + 'a', + 9, + 0, + /* 295 */ 'v', + 's', + 'r', + 'a', + 9, + 0, + /* 301 */ 'a', + 'd', + 't', + 'r', + 'a', + 9, + 0, + /* 308 */ 'd', + 'd', + 't', + 'r', + 'a', + 9, + 0, + /* 315 */ 'c', + 'g', + 'd', + 't', + 'r', + 'a', + 9, + 0, + /* 323 */ 'm', + 'd', + 't', + 'r', + 'a', + 9, + 0, + /* 330 */ 's', + 'd', + 't', + 'r', + 'a', + 9, + 0, + /* 337 */ 'c', + 'd', + 'g', + 't', + 'r', + 'a', + 9, + 0, + /* 345 */ 'c', + 'x', + 'g', + 't', + 'r', + 'a', + 9, + 0, + /* 353 */ 'a', + 'x', + 't', + 'r', + 'a', + 9, + 0, + /* 360 */ 'd', + 'x', + 't', + 'r', + 'a', + 9, + 0, + /* 367 */ 'c', + 'g', + 'x', + 't', + 'r', + 'a', + 9, + 0, + /* 375 */ 'm', + 'x', + 't', + 'r', + 'a', + 9, + 0, + /* 382 */ 's', + 'x', + 't', + 'r', + 'a', + 9, + 0, + /* 389 */ 'l', + 'u', + 'r', + 'a', + 9, + 0, + /* 395 */ 's', + 't', + 'u', + 'r', + 'a', + 9, + 0, + /* 402 */ 'b', + 's', + 'a', + 9, + 0, + /* 407 */ 'e', + 's', + 't', + 'a', + 9, + 0, + /* 413 */ 'm', + 's', + 't', + 'a', + 9, + 0, + /* 419 */ 'v', + 'a', + 9, + 0, + /* 423 */ 'c', + 'p', + 'y', + 'a', + 9, + 0, + /* 429 */ 'v', + 'g', + 'f', + 'm', + 'a', + 'b', + 9, + 0, + /* 437 */ 'v', + 'e', + 's', + 'r', + 'a', + 'b', + 9, + 0, + /* 445 */ 'v', + 's', + 'r', + 'a', + 'b', + 9, + 0, + /* 452 */ 'v', + 'a', + 'b', + 9, + 0, + /* 457 */ 'l', + 'c', + 'b', + 'b', + 9, + 0, + /* 463 */ 'v', + 'l', + 'b', + 'b', + 9, + 0, + /* 469 */ 'v', + 'a', + 'c', + 'c', + 'b', + 9, + 0, + /* 476 */ 'v', + 'e', + 'c', + 'b', + 9, + 0, + /* 482 */ 'v', + 'l', + 'c', + 'b', + 9, + 0, + /* 488 */ 'v', + 's', + 't', + 'r', + 'c', + 'b', + 9, + 0, + /* 496 */ 'v', + 'f', + 'a', + 'd', + 'b', + 9, + 0, + /* 503 */ 'w', + 'f', + 'a', + 'd', + 'b', + 9, + 0, + /* 510 */ 'v', + 'f', + 'm', + 'a', + 'd', + 'b', + 9, + 0, + /* 518 */ 'w', + 'f', + 'm', + 'a', + 'd', + 'b', + 9, + 0, + /* 526 */ 'v', + 'f', + 'n', + 'm', + 'a', + 'd', + 'b', + 9, + 0, + /* 535 */ 'w', + 'f', + 'n', + 'm', + 'a', + 'd', + 'b', + 9, + 0, + /* 544 */ 'w', + 'f', + 'c', + 'd', + 'b', + 9, + 0, + /* 551 */ 'v', + 'f', + 'l', + 'c', + 'd', + 'b', + 9, + 0, + /* 559 */ 'w', + 'f', + 'l', + 'c', + 'd', + 'b', + 9, + 0, + /* 567 */ 't', + 'c', + 'd', + 'b', + 9, + 0, + /* 573 */ 'v', + 'f', + 'd', + 'd', + 'b', + 9, + 0, + /* 580 */ 'w', + 'f', + 'd', + 'd', + 'b', + 9, + 0, + /* 587 */ 'v', + 'f', + 'c', + 'e', + 'd', + 'b', + 9, + 0, + /* 595 */ 'w', + 'f', + 'c', + 'e', + 'd', + 'b', + 9, + 0, + /* 603 */ 'v', + 'f', + 'c', + 'h', + 'e', + 'd', + 'b', + 9, + 0, + /* 612 */ 'w', + 'f', + 'c', + 'h', + 'e', + 'd', + 'b', + 9, + 0, + /* 621 */ 'v', + 'f', + 'k', + 'h', + 'e', + 'd', + 'b', + 9, + 0, + /* 630 */ 'w', + 'f', + 'k', + 'h', + 'e', + 'd', + 'b', + 9, + 0, + /* 639 */ 'v', + 'f', + 'k', + 'e', + 'd', + 'b', + 9, + 0, + /* 647 */ 'w', + 'f', + 'k', + 'e', + 'd', + 'b', + 9, + 0, + /* 655 */ 'v', + 'l', + 'e', + 'd', + 'b', + 9, + 0, + /* 662 */ 'w', + 'l', + 'e', + 'd', + 'b', + 9, + 0, + /* 669 */ 'v', + 'c', + 'g', + 'd', + 'b', + 9, + 0, + /* 676 */ 'w', + 'c', + 'g', + 'd', + 'b', + 9, + 0, + /* 683 */ 'v', + 'c', + 'l', + 'g', + 'd', + 'b', + 9, + 0, + /* 691 */ 'w', + 'c', + 'l', + 'g', + 'd', + 'b', + 9, + 0, + /* 699 */ 'v', + 'f', + 'c', + 'h', + 'd', + 'b', + 9, + 0, + /* 707 */ 'w', + 'f', + 'c', + 'h', + 'd', + 'b', + 9, + 0, + /* 715 */ 'v', + 'f', + 'k', + 'h', + 'd', + 'b', + 9, + 0, + /* 723 */ 'w', + 'f', + 'k', + 'h', + 'd', + 'b', + 9, + 0, + /* 731 */ 'v', + 'f', + 't', + 'c', + 'i', + 'd', + 'b', + 9, + 0, + /* 740 */ 'w', + 'f', + 't', + 'c', + 'i', + 'd', + 'b', + 9, + 0, + /* 749 */ 'v', + 'f', + 'i', + 'd', + 'b', + 9, + 0, + /* 756 */ 'w', + 'f', + 'i', + 'd', + 'b', + 9, + 0, + /* 763 */ 'w', + 'f', + 'k', + 'd', + 'b', + 9, + 0, + /* 770 */ 'v', + 's', + 'l', + 'd', + 'b', + 9, + 0, + /* 777 */ 'v', + 'f', + 'm', + 'd', + 'b', + 9, + 0, + /* 784 */ 'w', + 'f', + 'm', + 'd', + 'b', + 9, + 0, + /* 791 */ 'v', + 'f', + 'm', + 'i', + 'n', + 'd', + 'b', + 9, + 0, + /* 800 */ 'w', + 'f', + 'm', + 'i', + 'n', + 'd', + 'b', + 9, + 0, + /* 809 */ 'v', + 'f', + 'l', + 'n', + 'd', + 'b', + 9, + 0, + /* 817 */ 'w', + 'f', + 'l', + 'n', + 'd', + 'b', + 9, + 0, + /* 825 */ 'v', + 'f', + 'p', + 's', + 'o', + 'd', + 'b', + 9, + 0, + /* 834 */ 'w', + 'f', + 'p', + 's', + 'o', + 'd', + 'b', + 9, + 0, + /* 843 */ 'v', + 'f', + 'l', + 'p', + 'd', + 'b', + 9, + 0, + /* 851 */ 'w', + 'f', + 'l', + 'p', + 'd', + 'b', + 9, + 0, + /* 859 */ 'v', + 'f', + 's', + 'q', + 'd', + 'b', + 9, + 0, + /* 867 */ 'w', + 'f', + 's', + 'q', + 'd', + 'b', + 9, + 0, + /* 875 */ 'v', + 'f', + 's', + 'd', + 'b', + 9, + 0, + /* 882 */ 'w', + 'f', + 's', + 'd', + 'b', + 9, + 0, + /* 889 */ 'v', + 'f', + 'm', + 's', + 'd', + 'b', + 9, + 0, + /* 897 */ 'w', + 'f', + 'm', + 's', + 'd', + 'b', + 9, + 0, + /* 905 */ 'v', + 'f', + 'n', + 'm', + 's', + 'd', + 'b', + 9, + 0, + /* 914 */ 'w', + 'f', + 'n', + 'm', + 's', + 'd', + 'b', + 9, + 0, + /* 923 */ 'v', + 'f', + 'm', + 'a', + 'x', + 'd', + 'b', + 9, + 0, + /* 932 */ 'w', + 'f', + 'm', + 'a', + 'x', + 'd', + 'b', + 9, + 0, + /* 941 */ 'l', + 'x', + 'd', + 'b', + 9, + 0, + /* 947 */ 'm', + 'x', + 'd', + 'b', + 9, + 0, + /* 953 */ 'v', + 'f', + 'a', + 'e', + 'b', + 9, + 0, + /* 960 */ 'v', + 'm', + 'a', + 'e', + 'b', + 9, + 0, + /* 967 */ 't', + 'c', + 'e', + 'b', + 9, + 0, + /* 973 */ 'v', + 'l', + 'd', + 'e', + 'b', + 9, + 0, + /* 980 */ 'w', + 'l', + 'd', + 'e', + 'b', + 9, + 0, + /* 987 */ 'm', + 'd', + 'e', + 'b', + 9, + 0, + /* 993 */ 'v', + 'f', + 'e', + 'e', + 'b', + 9, + 0, + /* 1000 */ 'm', + 'e', + 'e', + 'b', + 9, + 0, + /* 1006 */ 'k', + 'e', + 'b', + 9, + 0, + /* 1011 */ 'v', + 'm', + 'a', + 'l', + 'e', + 'b', + 9, + 0, + /* 1019 */ 'v', + 'm', + 'l', + 'e', + 'b', + 9, + 0, + /* 1026 */ 'v', + 'l', + 'e', + 'b', + 9, + 0, + /* 1032 */ 'v', + 'm', + 'e', + 'b', + 9, + 0, + /* 1038 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'b', + 9, + 0, + /* 1046 */ 's', + 'q', + 'e', + 'b', + 9, + 0, + /* 1052 */ 'm', + 's', + 'e', + 'b', + 9, + 0, + /* 1058 */ 'v', + 's', + 't', + 'e', + 'b', + 9, + 0, + /* 1065 */ 'l', + 'x', + 'e', + 'b', + 9, + 0, + /* 1071 */ 'v', + 'c', + 'd', + 'g', + 'b', + 9, + 0, + /* 1078 */ 'w', + 'c', + 'd', + 'g', + 'b', + 9, + 0, + /* 1085 */ 'v', + 's', + 'e', + 'g', + 'b', + 9, + 0, + /* 1092 */ 'v', + 'c', + 'd', + 'l', + 'g', + 'b', + 9, + 0, + /* 1100 */ 'w', + 'c', + 'd', + 'l', + 'g', + 'b', + 9, + 0, + /* 1108 */ 'v', + 'a', + 'v', + 'g', + 'b', + 9, + 0, + /* 1115 */ 'v', + 'l', + 'v', + 'g', + 'b', + 9, + 0, + /* 1122 */ 'v', + 'm', + 'a', + 'h', + 'b', + 9, + 0, + /* 1129 */ 'v', + 'c', + 'h', + 'b', + 9, + 0, + /* 1135 */ 'v', + 'm', + 'a', + 'l', + 'h', + 'b', + 9, + 0, + /* 1143 */ 'v', + 'm', + 'l', + 'h', + 'b', + 9, + 0, + /* 1150 */ 'v', + 'u', + 'p', + 'l', + 'h', + 'b', + 9, + 0, + /* 1158 */ 'v', + 'm', + 'h', + 'b', + 9, + 0, + /* 1164 */ 'v', + 'u', + 'p', + 'h', + 'b', + 9, + 0, + /* 1171 */ 'v', + 'm', + 'r', + 'h', + 'b', + 9, + 0, + /* 1178 */ 'v', + 's', + 'c', + 'b', + 'i', + 'b', + 9, + 0, + /* 1186 */ 'c', + 'i', + 'b', + 9, + 0, + /* 1191 */ 'v', + 'l', + 'e', + 'i', + 'b', + 9, + 0, + /* 1198 */ 'c', + 'g', + 'i', + 'b', + 9, + 0, + /* 1204 */ 'c', + 'l', + 'g', + 'i', + 'b', + 9, + 0, + /* 1211 */ 'c', + 'l', + 'i', + 'b', + 9, + 0, + /* 1217 */ 'v', + 'r', + 'e', + 'p', + 'i', + 'b', + 9, + 0, + /* 1225 */ 'v', + 'm', + 'a', + 'l', + 'b', + 9, + 0, + /* 1232 */ 'v', + 'e', + 'c', + 'l', + 'b', + 9, + 0, + /* 1239 */ 'v', + 'a', + 'v', + 'g', + 'l', + 'b', + 9, + 0, + /* 1247 */ 'v', + 'c', + 'h', + 'l', + 'b', + 9, + 0, + /* 1254 */ 'v', + 'u', + 'p', + 'l', + 'l', + 'b', + 9, + 0, + /* 1262 */ 'v', + 'e', + 'r', + 'l', + 'l', + 'b', + 9, + 0, + /* 1270 */ 'v', + 'm', + 'l', + 'b', + 9, + 0, + /* 1276 */ 'v', + 'm', + 'n', + 'l', + 'b', + 9, + 0, + /* 1283 */ 'v', + 'u', + 'p', + 'l', + 'b', + 9, + 0, + /* 1290 */ 'v', + 'm', + 'r', + 'l', + 'b', + 9, + 0, + /* 1297 */ 'v', + 'e', + 's', + 'r', + 'l', + 'b', + 9, + 0, + /* 1305 */ 'v', + 's', + 'r', + 'l', + 'b', + 9, + 0, + /* 1312 */ 'v', + 'e', + 's', + 'l', + 'b', + 9, + 0, + /* 1319 */ 'v', + 's', + 'l', + 'b', + 9, + 0, + /* 1325 */ 'v', + 'm', + 'x', + 'l', + 'b', + 9, + 0, + /* 1332 */ 'v', + 'g', + 'f', + 'm', + 'b', + 9, + 0, + /* 1339 */ 'v', + 'g', + 'm', + 'b', + 9, + 0, + /* 1345 */ 'v', + 'e', + 'r', + 'i', + 'm', + 'b', + 9, + 0, + /* 1353 */ 's', + 'r', + 'n', + 'm', + 'b', + 9, + 0, + /* 1360 */ 'v', + 's', + 'u', + 'm', + 'b', + 9, + 0, + /* 1367 */ 'v', + 'm', + 'n', + 'b', + 9, + 0, + /* 1373 */ 'v', + 'm', + 'a', + 'o', + 'b', + 9, + 0, + /* 1380 */ 'v', + 'm', + 'a', + 'l', + 'o', + 'b', + 9, + 0, + /* 1388 */ 'v', + 'm', + 'l', + 'o', + 'b', + 9, + 0, + /* 1395 */ 'v', + 'm', + 'o', + 'b', + 9, + 0, + /* 1401 */ 'v', + 'l', + 'r', + 'e', + 'p', + 'b', + 9, + 0, + /* 1409 */ 'v', + 'r', + 'e', + 'p', + 'b', + 9, + 0, + /* 1416 */ 'v', + 'l', + 'p', + 'b', + 9, + 0, + /* 1422 */ 'v', + 'c', + 'e', + 'q', + 'b', + 9, + 0, + /* 1429 */ 'c', + 'r', + 'b', + 9, + 0, + /* 1434 */ 'c', + 'g', + 'r', + 'b', + 9, + 0, + /* 1440 */ 'c', + 'l', + 'g', + 'r', + 'b', + 9, + 0, + /* 1447 */ 'c', + 'l', + 'r', + 'b', + 9, + 0, + /* 1453 */ 'v', + 'i', + 's', + 't', + 'r', + 'b', + 9, + 0, + /* 1461 */ 'v', + 'f', + 'a', + 's', + 'b', + 9, + 0, + /* 1468 */ 'w', + 'f', + 'a', + 's', + 'b', + 9, + 0, + /* 1475 */ 'v', + 'f', + 'm', + 'a', + 's', + 'b', + 9, + 0, + /* 1483 */ 'w', + 'f', + 'm', + 'a', + 's', + 'b', + 9, + 0, + /* 1491 */ 'v', + 'f', + 'n', + 'm', + 'a', + 's', + 'b', + 9, + 0, + /* 1500 */ 'w', + 'f', + 'n', + 'm', + 'a', + 's', + 'b', + 9, + 0, + /* 1509 */ 'w', + 'f', + 'c', + 's', + 'b', + 9, + 0, + /* 1516 */ 'v', + 'f', + 'l', + 'c', + 's', + 'b', + 9, + 0, + /* 1524 */ 'w', + 'f', + 'l', + 'c', + 's', + 'b', + 9, + 0, + /* 1532 */ 'v', + 'f', + 'd', + 's', + 'b', + 9, + 0, + /* 1539 */ 'w', + 'f', + 'd', + 's', + 'b', + 9, + 0, + /* 1546 */ 'v', + 'f', + 'c', + 'e', + 's', + 'b', + 9, + 0, + /* 1554 */ 'w', + 'f', + 'c', + 'e', + 's', + 'b', + 9, + 0, + /* 1562 */ 'v', + 'f', + 'c', + 'h', + 'e', + 's', + 'b', + 9, + 0, + /* 1571 */ 'w', + 'f', + 'c', + 'h', + 'e', + 's', + 'b', + 9, + 0, + /* 1580 */ 'v', + 'f', + 'k', + 'h', + 'e', + 's', + 'b', + 9, + 0, + /* 1589 */ 'w', + 'f', + 'k', + 'h', + 'e', + 's', + 'b', + 9, + 0, + /* 1598 */ 'v', + 'f', + 'k', + 'e', + 's', + 'b', + 9, + 0, + /* 1606 */ 'w', + 'f', + 'k', + 'e', + 's', + 'b', + 9, + 0, + /* 1614 */ 'v', + 'f', + 'c', + 'h', + 's', + 'b', + 9, + 0, + /* 1622 */ 'w', + 'f', + 'c', + 'h', + 's', + 'b', + 9, + 0, + /* 1630 */ 'v', + 'f', + 'k', + 'h', + 's', + 'b', + 9, + 0, + /* 1638 */ 'w', + 'f', + 'k', + 'h', + 's', + 'b', + 9, + 0, + /* 1646 */ 'v', + 'f', + 't', + 'c', + 'i', + 's', + 'b', + 9, + 0, + /* 1655 */ 'w', + 'f', + 't', + 'c', + 'i', + 's', + 'b', + 9, + 0, + /* 1664 */ 'v', + 'f', + 'i', + 's', + 'b', + 9, + 0, + /* 1671 */ 'w', + 'f', + 'i', + 's', + 'b', + 9, + 0, + /* 1678 */ 'w', + 'f', + 'k', + 's', + 'b', + 9, + 0, + /* 1685 */ 'v', + 'f', + 'm', + 's', + 'b', + 9, + 0, + /* 1692 */ 'w', + 'f', + 'm', + 's', + 'b', + 9, + 0, + /* 1699 */ 'v', + 'f', + 'm', + 'i', + 'n', + 's', + 'b', + 9, + 0, + /* 1708 */ 'w', + 'f', + 'm', + 'i', + 'n', + 's', + 'b', + 9, + 0, + /* 1717 */ 'v', + 'f', + 'l', + 'n', + 's', + 'b', + 9, + 0, + /* 1725 */ 'w', + 'f', + 'l', + 'n', + 's', + 'b', + 9, + 0, + /* 1733 */ 'v', + 'f', + 'p', + 's', + 'o', + 's', + 'b', + 9, + 0, + /* 1742 */ 'w', + 'f', + 'p', + 's', + 'o', + 's', + 'b', + 9, + 0, + /* 1751 */ 'v', + 'f', + 'l', + 'p', + 's', + 'b', + 9, + 0, + /* 1759 */ 'w', + 'f', + 'l', + 'p', + 's', + 'b', + 9, + 0, + /* 1767 */ 'v', + 'f', + 's', + 'q', + 's', + 'b', + 9, + 0, + /* 1775 */ 'w', + 'f', + 's', + 'q', + 's', + 'b', + 9, + 0, + /* 1783 */ 'v', + 'f', + 's', + 's', + 'b', + 9, + 0, + /* 1790 */ 'w', + 'f', + 's', + 's', + 'b', + 9, + 0, + /* 1797 */ 'v', + 'f', + 'm', + 's', + 's', + 'b', + 9, + 0, + /* 1805 */ 'w', + 'f', + 'm', + 's', + 's', + 'b', + 9, + 0, + /* 1813 */ 'v', + 'f', + 'n', + 'm', + 's', + 's', + 'b', + 9, + 0, + /* 1822 */ 'w', + 'f', + 'n', + 'm', + 's', + 's', + 'b', + 9, + 0, + /* 1831 */ 'v', + 's', + 'b', + 9, + 0, + /* 1836 */ 'v', + 'f', + 'm', + 'a', + 'x', + 's', + 'b', + 9, + 0, + /* 1845 */ 'w', + 'f', + 'm', + 'a', + 'x', + 's', + 'b', + 9, + 0, + /* 1854 */ 'v', + 'p', + 'o', + 'p', + 'c', + 't', + 'b', + 9, + 0, + /* 1863 */ 'v', + 'e', + 's', + 'r', + 'a', + 'v', + 'b', + 9, + 0, + /* 1872 */ 'v', + 'c', + 'v', + 'b', + 9, + 0, + /* 1878 */ 'v', + 'l', + 'g', + 'v', + 'b', + 9, + 0, + /* 1885 */ 'v', + 'e', + 'r', + 'l', + 'l', + 'v', + 'b', + 9, + 0, + /* 1894 */ 'v', + 'e', + 's', + 'r', + 'l', + 'v', + 'b', + 9, + 0, + /* 1903 */ 'v', + 'e', + 's', + 'l', + 'v', + 'b', + 9, + 0, + /* 1911 */ 'w', + 'f', + 'a', + 'x', + 'b', + 9, + 0, + /* 1918 */ 'w', + 'f', + 'm', + 'a', + 'x', + 'b', + 9, + 0, + /* 1926 */ 'w', + 'f', + 'n', + 'm', + 'a', + 'x', + 'b', + 9, + 0, + /* 1935 */ 'w', + 'f', + 'c', + 'x', + 'b', + 9, + 0, + /* 1942 */ 'w', + 'f', + 'l', + 'c', + 'x', + 'b', + 9, + 0, + /* 1950 */ 't', + 'c', + 'x', + 'b', + 9, + 0, + /* 1956 */ 'w', + 'f', + 'd', + 'x', + 'b', + 9, + 0, + /* 1963 */ 'w', + 'f', + 'c', + 'e', + 'x', + 'b', + 9, + 0, + /* 1971 */ 'w', + 'f', + 'c', + 'h', + 'e', + 'x', + 'b', + 9, + 0, + /* 1980 */ 'w', + 'f', + 'k', + 'h', + 'e', + 'x', + 'b', + 9, + 0, + /* 1989 */ 'w', + 'f', + 'k', + 'e', + 'x', + 'b', + 9, + 0, + /* 1997 */ 'w', + 'f', + 'c', + 'h', + 'x', + 'b', + 9, + 0, + /* 2005 */ 'w', + 'f', + 'k', + 'h', + 'x', + 'b', + 9, + 0, + /* 2013 */ 'w', + 'f', + 't', + 'c', + 'i', + 'x', + 'b', + 9, + 0, + /* 2022 */ 'w', + 'f', + 'i', + 'x', + 'b', + 9, + 0, + /* 2029 */ 'w', + 'f', + 'k', + 'x', + 'b', + 9, + 0, + /* 2036 */ 'w', + 'f', + 'm', + 'x', + 'b', + 9, + 0, + /* 2043 */ 'v', + 'm', + 'x', + 'b', + 9, + 0, + /* 2049 */ 'w', + 'f', + 'm', + 'i', + 'n', + 'x', + 'b', + 9, + 0, + /* 2058 */ 'w', + 'f', + 'l', + 'n', + 'x', + 'b', + 9, + 0, + /* 2066 */ 'w', + 'f', + 'p', + 's', + 'o', + 'x', + 'b', + 9, + 0, + /* 2075 */ 'w', + 'f', + 'l', + 'p', + 'x', + 'b', + 9, + 0, + /* 2083 */ 'w', + 'f', + 's', + 'q', + 'x', + 'b', + 9, + 0, + /* 2091 */ 'w', + 'f', + 's', + 'x', + 'b', + 9, + 0, + /* 2098 */ 'w', + 'f', + 'm', + 's', + 'x', + 'b', + 9, + 0, + /* 2106 */ 'w', + 'f', + 'n', + 'm', + 's', + 'x', + 'b', + 9, + 0, + /* 2115 */ 'w', + 'f', + 'm', + 'a', + 'x', + 'x', + 'b', + 9, + 0, + /* 2124 */ 'v', + 's', + 't', + 'r', + 'c', + 'z', + 'b', + 9, + 0, + /* 2133 */ 'v', + 'f', + 'a', + 'e', + 'z', + 'b', + 9, + 0, + /* 2141 */ 'v', + 'f', + 'e', + 'e', + 'z', + 'b', + 9, + 0, + /* 2149 */ 'v', + 'l', + 'l', + 'e', + 'z', + 'b', + 9, + 0, + /* 2157 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'z', + 'b', + 9, + 0, + /* 2166 */ 'v', + 'c', + 'l', + 'z', + 'b', + 9, + 0, + /* 2173 */ 'v', + 'c', + 't', + 'z', + 'b', + 9, + 0, + /* 2180 */ 'i', + 'a', + 'c', + 9, + 0, + /* 2185 */ 'k', + 'm', + 'a', + 'c', + 9, + 0, + /* 2191 */ 's', + 'a', + 'c', + 9, + 0, + /* 2196 */ 'v', + 'a', + 'c', + 9, + 0, + /* 2201 */ 'b', + 'c', + 9, + 0, + /* 2205 */ 'v', + 'a', + 'c', + 'c', + 9, + 0, + /* 2211 */ 'v', + 'a', + 'c', + 'c', + 'c', + 9, + 0, + /* 2218 */ 'v', + 'e', + 'c', + 9, + 0, + /* 2223 */ 'c', + 'f', + 'c', + 9, + 0, + /* 2228 */ 'w', + 'f', + 'c', + 9, + 0, + /* 2233 */ 'l', + 'l', + 'g', + 'c', + 9, + 0, + /* 2239 */ 'm', + 's', + 'g', + 'c', + 9, + 0, + /* 2245 */ 'b', + 'i', + 'c', + 9, + 0, + /* 2250 */ 's', + 'c', + 'k', + 'c', + 9, + 0, + /* 2256 */ 's', + 't', + 'c', + 'k', + 'c', + 9, + 0, + /* 2263 */ 'm', + 's', + 'g', + 'r', + 'k', + 'c', + 9, + 0, + /* 2271 */ 'm', + 's', + 'r', + 'k', + 'c', + 9, + 0, + /* 2278 */ 'a', + 'l', + 'c', + 9, + 0, + /* 2283 */ 'c', + 'l', + 'c', + 9, + 0, + /* 2288 */ 'l', + 'l', + 'c', + 9, + 0, + /* 2293 */ 'v', + 'l', + 'c', + 9, + 0, + /* 2298 */ 'k', + 'm', + 'c', + 9, + 0, + /* 2303 */ 't', + 'b', + 'e', + 'g', + 'i', + 'n', + 'c', + 9, + 0, + /* 2312 */ 'v', + 'n', + 'c', + 9, + 0, + /* 2317 */ 'l', + 'o', + 'c', + 9, + 0, + /* 2322 */ 's', + 't', + 'o', + 'c', + 9, + 0, + /* 2328 */ 'v', + 'o', + 'c', + 9, + 0, + /* 2333 */ 'e', + 'f', + 'p', + 'c', + 9, + 0, + /* 2339 */ 'l', + 'f', + 'p', + 'c', + 9, + 0, + /* 2345 */ 's', + 'f', + 'p', + 'c', + 9, + 0, + /* 2351 */ 's', + 't', + 'f', + 'p', + 'c', + 9, + 0, + /* 2358 */ 'b', + 'r', + 'c', + 9, + 0, + /* 2363 */ 'v', + 's', + 't', + 'r', + 'c', + 9, + 0, + /* 2370 */ 'l', + 'g', + 's', + 'c', + 9, + 0, + /* 2376 */ 's', + 't', + 'g', + 's', + 'c', + 9, + 0, + /* 2383 */ 'm', + 's', + 'c', + 9, + 0, + /* 2388 */ 'c', + 'm', + 'p', + 's', + 'c', + 9, + 0, + /* 2395 */ 's', + 't', + 'c', + 9, + 0, + /* 2400 */ 'm', + 'v', + 'c', + 9, + 0, + /* 2405 */ 's', + 'v', + 'c', + 9, + 0, + /* 2410 */ 'x', + 'c', + 9, + 0, + /* 2414 */ 'm', + 'a', + 'd', + 9, + 0, + /* 2419 */ 'c', + 'd', + 9, + 0, + /* 2423 */ 'd', + 'd', + 9, + 0, + /* 2427 */ 'v', + 'l', + 'e', + 'd', + 9, + 0, + /* 2433 */ 'p', + 'f', + 'd', + 9, + 0, + /* 2438 */ 'v', + 'f', + 'd', + 9, + 0, + /* 2443 */ 'v', + 'c', + 'g', + 'd', + 9, + 0, + /* 2449 */ 'v', + 'c', + 'l', + 'g', + 'd', + 9, + 0, + /* 2456 */ 'w', + 'f', + 'l', + 'l', + 'd', + 9, + 0, + /* 2463 */ 'k', + 'i', + 'm', + 'd', + 9, + 0, + /* 2469 */ 'k', + 'l', + 'm', + 'd', + 9, + 0, + /* 2475 */ 'e', + 't', + 'n', + 'd', + 9, + 0, + /* 2481 */ 'l', + 'p', + 'd', + 9, + 0, + /* 2486 */ 's', + 'q', + 'd', + 9, + 0, + /* 2491 */ 'v', + 'f', + 'l', + 'r', + 'd', + 9, + 0, + /* 2498 */ 'w', + 'f', + 'l', + 'r', + 'd', + 9, + 0, + /* 2505 */ 'm', + 's', + 'd', + 9, + 0, + /* 2510 */ 's', + 't', + 'd', + 9, + 0, + /* 2515 */ 'v', + 'c', + 'v', + 'd', + 9, + 0, + /* 2521 */ 'l', + 'x', + 'd', + 9, + 0, + /* 2526 */ 'm', + 'x', + 'd', + 9, + 0, + /* 2531 */ 'v', + 'f', + 'a', + 'e', + 9, + 0, + /* 2537 */ 'l', + 'a', + 'e', + 9, + 0, + /* 2542 */ 'v', + 'm', + 'a', + 'e', + 9, + 0, + /* 2548 */ 'c', + 'i', + 'b', + 'e', + 9, + 0, + /* 2554 */ 'c', + 'g', + 'i', + 'b', + 'e', + 9, + 0, + /* 2561 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'e', + 9, + 0, + /* 2569 */ 'c', + 'l', + 'i', + 'b', + 'e', + 9, + 0, + /* 2576 */ 'c', + 'r', + 'b', + 'e', + 9, + 0, + /* 2582 */ 'c', + 'g', + 'r', + 'b', + 'e', + 9, + 0, + /* 2589 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'e', + 9, + 0, + /* 2597 */ 'c', + 'l', + 'r', + 'b', + 'e', + 9, + 0, + /* 2604 */ 'r', + 'r', + 'b', + 'e', + 9, + 0, + /* 2610 */ 't', + 'r', + 'a', + 'c', + 'e', + 9, + 0, + /* 2617 */ 'v', + 'f', + 'c', + 'e', + 9, + 0, + /* 2623 */ 'l', + 'o', + 'c', + 'e', + 9, + 0, + /* 2629 */ 's', + 't', + 'o', + 'c', + 'e', + 9, + 0, + /* 2636 */ 'v', + 'l', + 'd', + 'e', + 9, + 0, + /* 2642 */ 'm', + 'd', + 'e', + 9, + 0, + /* 2647 */ 'v', + 'f', + 'e', + 'e', + 9, + 0, + /* 2653 */ 'm', + 'e', + 'e', + 9, + 0, + /* 2658 */ 'l', + 'o', + 'c', + 'g', + 'e', + 9, + 0, + /* 2665 */ 's', + 't', + 'o', + 'c', + 'g', + 'e', + 9, + 0, + /* 2673 */ 'j', + 'g', + 'e', + 9, + 0, + /* 2678 */ 'c', + 'i', + 'b', + 'h', + 'e', + 9, + 0, + /* 2685 */ 'c', + 'g', + 'i', + 'b', + 'h', + 'e', + 9, + 0, + /* 2693 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'h', + 'e', + 9, + 0, + /* 2702 */ 'c', + 'l', + 'i', + 'b', + 'h', + 'e', + 9, + 0, + /* 2710 */ 'c', + 'r', + 'b', + 'h', + 'e', + 9, + 0, + /* 2717 */ 'c', + 'g', + 'r', + 'b', + 'h', + 'e', + 9, + 0, + /* 2725 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'h', + 'e', + 9, + 0, + /* 2734 */ 'c', + 'l', + 'r', + 'b', + 'h', + 'e', + 9, + 0, + /* 2742 */ 'v', + 'f', + 'c', + 'h', + 'e', + 9, + 0, + /* 2749 */ 'l', + 'o', + 'c', + 'h', + 'e', + 9, + 0, + /* 2756 */ 's', + 't', + 'o', + 'c', + 'h', + 'e', + 9, + 0, + /* 2764 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'e', + 9, + 0, + /* 2772 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'e', + 9, + 0, + /* 2781 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'e', + 9, + 0, + /* 2789 */ 's', + 't', + 'o', + 'c', + 'g', + 'h', + 'e', + 9, + 0, + /* 2798 */ 'j', + 'g', + 'h', + 'e', + 9, + 0, + /* 2804 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'h', + 'e', + 9, + 0, + /* 2813 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'h', + 'e', + 9, + 0, + /* 2823 */ 'b', + 'i', + 'h', + 'e', + 9, + 0, + /* 2829 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'h', + 'e', + 9, + 0, + /* 2838 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'h', + 'e', + 9, + 0, + /* 2848 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'h', + 'e', + 9, + 0, + /* 2858 */ 'c', + 'i', + 'j', + 'h', + 'e', + 9, + 0, + /* 2865 */ 'c', + 'g', + 'i', + 'j', + 'h', + 'e', + 9, + 0, + /* 2873 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'h', + 'e', + 9, + 0, + /* 2882 */ 'c', + 'l', + 'i', + 'j', + 'h', + 'e', + 9, + 0, + /* 2890 */ 'c', + 'r', + 'j', + 'h', + 'e', + 9, + 0, + /* 2897 */ 'c', + 'g', + 'r', + 'j', + 'h', + 'e', + 9, + 0, + /* 2905 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'h', + 'e', + 9, + 0, + /* 2914 */ 'c', + 'l', + 'r', + 'j', + 'h', + 'e', + 9, + 0, + /* 2922 */ 'c', + 'i', + 'b', + 'n', + 'h', + 'e', + 9, + 0, + /* 2930 */ 'c', + 'g', + 'i', + 'b', + 'n', + 'h', + 'e', + 9, + 0, + /* 2939 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'n', + 'h', + 'e', + 9, + 0, + /* 2949 */ 'c', + 'l', + 'i', + 'b', + 'n', + 'h', + 'e', + 9, + 0, + /* 2958 */ 'c', + 'r', + 'b', + 'n', + 'h', + 'e', + 9, + 0, + /* 2966 */ 'c', + 'g', + 'r', + 'b', + 'n', + 'h', + 'e', + 9, + 0, + /* 2975 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'n', + 'h', + 'e', + 9, + 0, + /* 2985 */ 'c', + 'l', + 'r', + 'b', + 'n', + 'h', + 'e', + 9, + 0, + /* 2994 */ 'l', + 'o', + 'c', + 'n', + 'h', + 'e', + 9, + 0, + /* 3002 */ 's', + 't', + 'o', + 'c', + 'n', + 'h', + 'e', + 9, + 0, + /* 3011 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'h', + 'e', + 9, + 0, + /* 3020 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'h', + 'e', + 9, + 0, + /* 3030 */ 'j', + 'g', + 'n', + 'h', + 'e', + 9, + 0, + /* 3037 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'h', + 'e', + 9, + 0, + /* 3047 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'h', + 'e', + 9, + 0, + /* 3058 */ 'b', + 'i', + 'n', + 'h', + 'e', + 9, + 0, + /* 3065 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'h', + 'e', + 9, + 0, + /* 3075 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'h', + 'e', + 9, + 0, + /* 3086 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'h', + 'e', + 9, + 0, + /* 3097 */ 'c', + 'i', + 'j', + 'n', + 'h', + 'e', + 9, + 0, + /* 3105 */ 'c', + 'g', + 'i', + 'j', + 'n', + 'h', + 'e', + 9, + 0, + /* 3114 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'n', + 'h', + 'e', + 9, + 0, + /* 3124 */ 'c', + 'l', + 'i', + 'j', + 'n', + 'h', + 'e', + 9, + 0, + /* 3133 */ 'c', + 'r', + 'j', + 'n', + 'h', + 'e', + 9, + 0, + /* 3141 */ 'c', + 'g', + 'r', + 'j', + 'n', + 'h', + 'e', + 9, + 0, + /* 3150 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'n', + 'h', + 'e', + 9, + 0, + /* 3160 */ 'c', + 'l', + 'r', + 'j', + 'n', + 'h', + 'e', + 9, + 0, + /* 3169 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'h', + 'e', + 9, + 0, + /* 3178 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'h', + 'e', + 9, + 0, + /* 3188 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'h', + 'e', + 9, + 0, + /* 3199 */ 'c', + 'l', + 'g', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3208 */ 'c', + 'i', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3216 */ 'c', + 'l', + 'f', + 'i', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3226 */ 'c', + 'g', + 'i', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3235 */ 'c', + 'l', + 'g', + 'i', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3245 */ 'c', + 'l', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3253 */ 'c', + 'r', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3261 */ 'c', + 'g', + 'r', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3270 */ 'c', + 'l', + 'g', + 'r', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3280 */ 'c', + 'l', + 'r', + 't', + 'n', + 'h', + 'e', + 9, + 0, + /* 3289 */ 'l', + 'o', + 'c', + 'r', + 'h', + 'e', + 9, + 0, + /* 3297 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'h', + 'e', + 9, + 0, + /* 3306 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'h', + 'e', + 9, + 0, + /* 3316 */ 'c', + 'l', + 'g', + 't', + 'h', + 'e', + 9, + 0, + /* 3324 */ 'c', + 'i', + 't', + 'h', + 'e', + 9, + 0, + /* 3331 */ 'c', + 'l', + 'f', + 'i', + 't', + 'h', + 'e', + 9, + 0, + /* 3340 */ 'c', + 'g', + 'i', + 't', + 'h', + 'e', + 9, + 0, + /* 3348 */ 'c', + 'l', + 'g', + 'i', + 't', + 'h', + 'e', + 9, + 0, + /* 3357 */ 'c', + 'l', + 't', + 'h', + 'e', + 9, + 0, + /* 3364 */ 'c', + 'r', + 't', + 'h', + 'e', + 9, + 0, + /* 3371 */ 'c', + 'g', + 'r', + 't', + 'h', + 'e', + 9, + 0, + /* 3379 */ 'c', + 'l', + 'g', + 'r', + 't', + 'h', + 'e', + 9, + 0, + /* 3388 */ 'c', + 'l', + 'r', + 't', + 'h', + 'e', + 9, + 0, + /* 3396 */ 'b', + 'i', + 'e', + 9, + 0, + /* 3401 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'e', + 9, + 0, + /* 3409 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'e', + 9, + 0, + /* 3418 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'e', + 9, + 0, + /* 3427 */ 's', + 'i', + 'e', + 9, + 0, + /* 3432 */ 'c', + 'i', + 'j', + 'e', + 9, + 0, + /* 3438 */ 'c', + 'g', + 'i', + 'j', + 'e', + 9, + 0, + /* 3445 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'e', + 9, + 0, + /* 3453 */ 'c', + 'l', + 'i', + 'j', + 'e', + 9, + 0, + /* 3460 */ 'c', + 'r', + 'j', + 'e', + 9, + 0, + /* 3466 */ 'c', + 'g', + 'r', + 'j', + 'e', + 9, + 0, + /* 3473 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'e', + 9, + 0, + /* 3481 */ 'c', + 'l', + 'r', + 'j', + 'e', + 9, + 0, + /* 3488 */ 's', + 't', + 'c', + 'k', + 'e', + 9, + 0, + /* 3495 */ 'i', + 's', + 'k', + 'e', + 9, + 0, + /* 3501 */ 's', + 's', + 'k', + 'e', + 9, + 0, + /* 3507 */ 'v', + 'm', + 'a', + 'l', + 'e', + 9, + 0, + /* 3514 */ 'c', + 'i', + 'b', + 'l', + 'e', + 9, + 0, + /* 3521 */ 'c', + 'g', + 'i', + 'b', + 'l', + 'e', + 9, + 0, + /* 3529 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'l', + 'e', + 9, + 0, + /* 3538 */ 'c', + 'l', + 'i', + 'b', + 'l', + 'e', + 9, + 0, + /* 3546 */ 'c', + 'r', + 'b', + 'l', + 'e', + 9, + 0, + /* 3553 */ 'c', + 'g', + 'r', + 'b', + 'l', + 'e', + 9, + 0, + /* 3561 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'l', + 'e', + 9, + 0, + /* 3570 */ 'c', + 'l', + 'r', + 'b', + 'l', + 'e', + 9, + 0, + /* 3578 */ 'c', + 'l', + 'c', + 'l', + 'e', + 9, + 0, + /* 3585 */ 'l', + 'o', + 'c', + 'l', + 'e', + 9, + 0, + /* 3592 */ 's', + 't', + 'o', + 'c', + 'l', + 'e', + 9, + 0, + /* 3600 */ 'm', + 'v', + 'c', + 'l', + 'e', + 9, + 0, + /* 3607 */ 's', + 't', + 'f', + 'l', + 'e', + 9, + 0, + /* 3614 */ 'l', + 'o', + 'c', + 'g', + 'l', + 'e', + 9, + 0, + /* 3622 */ 's', + 't', + 'o', + 'c', + 'g', + 'l', + 'e', + 9, + 0, + /* 3631 */ 'j', + 'g', + 'l', + 'e', + 9, + 0, + /* 3637 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'l', + 'e', + 9, + 0, + /* 3646 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'l', + 'e', + 9, + 0, + /* 3656 */ 'b', + 'i', + 'l', + 'e', + 9, + 0, + /* 3662 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'l', + 'e', + 9, + 0, + /* 3671 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'l', + 'e', + 9, + 0, + /* 3681 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'l', + 'e', + 9, + 0, + /* 3691 */ 'c', + 'i', + 'j', + 'l', + 'e', + 9, + 0, + /* 3698 */ 'c', + 'g', + 'i', + 'j', + 'l', + 'e', + 9, + 0, + /* 3706 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'l', + 'e', + 9, + 0, + /* 3715 */ 'c', + 'l', + 'i', + 'j', + 'l', + 'e', + 9, + 0, + /* 3723 */ 'c', + 'r', + 'j', + 'l', + 'e', + 9, + 0, + /* 3730 */ 'c', + 'g', + 'r', + 'j', + 'l', + 'e', + 9, + 0, + /* 3738 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'l', + 'e', + 9, + 0, + /* 3747 */ 'c', + 'l', + 'r', + 'j', + 'l', + 'e', + 9, + 0, + /* 3755 */ 'v', + 'm', + 'l', + 'e', + 9, + 0, + /* 3761 */ 'c', + 'i', + 'b', + 'n', + 'l', + 'e', + 9, + 0, + /* 3769 */ 'c', + 'g', + 'i', + 'b', + 'n', + 'l', + 'e', + 9, + 0, + /* 3778 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'n', + 'l', + 'e', + 9, + 0, + /* 3788 */ 'c', + 'l', + 'i', + 'b', + 'n', + 'l', + 'e', + 9, + 0, + /* 3797 */ 'c', + 'r', + 'b', + 'n', + 'l', + 'e', + 9, + 0, + /* 3805 */ 'c', + 'g', + 'r', + 'b', + 'n', + 'l', + 'e', + 9, + 0, + /* 3814 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'n', + 'l', + 'e', + 9, + 0, + /* 3824 */ 'c', + 'l', + 'r', + 'b', + 'n', + 'l', + 'e', + 9, + 0, + /* 3833 */ 'l', + 'o', + 'c', + 'n', + 'l', + 'e', + 9, + 0, + /* 3841 */ 's', + 't', + 'o', + 'c', + 'n', + 'l', + 'e', + 9, + 0, + /* 3850 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'l', + 'e', + 9, + 0, + /* 3859 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'l', + 'e', + 9, + 0, + /* 3869 */ 'j', + 'g', + 'n', + 'l', + 'e', + 9, + 0, + /* 3876 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'l', + 'e', + 9, + 0, + /* 3886 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'l', + 'e', + 9, + 0, + /* 3897 */ 'b', + 'i', + 'n', + 'l', + 'e', + 9, + 0, + /* 3904 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'l', + 'e', + 9, + 0, + /* 3914 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'l', + 'e', + 9, + 0, + /* 3925 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'l', + 'e', + 9, + 0, + /* 3936 */ 'c', + 'i', + 'j', + 'n', + 'l', + 'e', + 9, + 0, + /* 3944 */ 'c', + 'g', + 'i', + 'j', + 'n', + 'l', + 'e', + 9, + 0, + /* 3953 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'n', + 'l', + 'e', + 9, + 0, + /* 3963 */ 'c', + 'l', + 'i', + 'j', + 'n', + 'l', + 'e', + 9, + 0, + /* 3972 */ 'c', + 'r', + 'j', + 'n', + 'l', + 'e', + 9, + 0, + /* 3980 */ 'c', + 'g', + 'r', + 'j', + 'n', + 'l', + 'e', + 9, + 0, + /* 3989 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'n', + 'l', + 'e', + 9, + 0, + /* 3999 */ 'c', + 'l', + 'r', + 'j', + 'n', + 'l', + 'e', + 9, + 0, + /* 4008 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'l', + 'e', + 9, + 0, + /* 4017 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'l', + 'e', + 9, + 0, + /* 4027 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'l', + 'e', + 9, + 0, + /* 4038 */ 'c', + 'l', + 'g', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4047 */ 'c', + 'i', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4055 */ 'c', + 'l', + 'f', + 'i', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4065 */ 'c', + 'g', + 'i', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4074 */ 'c', + 'l', + 'g', + 'i', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4084 */ 'c', + 'l', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4092 */ 'c', + 'r', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4100 */ 'c', + 'g', + 'r', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4109 */ 'c', + 'l', + 'g', + 'r', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4119 */ 'c', + 'l', + 'r', + 't', + 'n', + 'l', + 'e', + 9, + 0, + /* 4128 */ 'l', + 'o', + 'c', + 'r', + 'l', + 'e', + 9, + 0, + /* 4136 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'l', + 'e', + 9, + 0, + /* 4145 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'l', + 'e', + 9, + 0, + /* 4155 */ 'c', + 'l', + 'g', + 't', + 'l', + 'e', + 9, + 0, + /* 4163 */ 'c', + 'i', + 't', + 'l', + 'e', + 9, + 0, + /* 4170 */ 'c', + 'l', + 'f', + 'i', + 't', + 'l', + 'e', + 9, + 0, + /* 4179 */ 'c', + 'g', + 'i', + 't', + 'l', + 'e', + 9, + 0, + /* 4187 */ 'c', + 'l', + 'g', + 'i', + 't', + 'l', + 'e', + 9, + 0, + /* 4196 */ 'c', + 'l', + 't', + 'l', + 'e', + 9, + 0, + /* 4203 */ 'c', + 'r', + 't', + 'l', + 'e', + 9, + 0, + /* 4210 */ 'c', + 'g', + 'r', + 't', + 'l', + 'e', + 9, + 0, + /* 4218 */ 'c', + 'l', + 'g', + 'r', + 't', + 'l', + 'e', + 9, + 0, + /* 4227 */ 'c', + 'l', + 'r', + 't', + 'l', + 'e', + 9, + 0, + /* 4235 */ 'b', + 'x', + 'l', + 'e', + 9, + 0, + /* 4241 */ 'b', + 'r', + 'x', + 'l', + 'e', + 9, + 0, + /* 4248 */ 'v', + 'm', + 'e', + 9, + 0, + /* 4253 */ 'c', + 'i', + 'b', + 'n', + 'e', + 9, + 0, + /* 4260 */ 'c', + 'g', + 'i', + 'b', + 'n', + 'e', + 9, + 0, + /* 4268 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'n', + 'e', + 9, + 0, + /* 4277 */ 'c', + 'l', + 'i', + 'b', + 'n', + 'e', + 9, + 0, + /* 4285 */ 'c', + 'r', + 'b', + 'n', + 'e', + 9, + 0, + /* 4292 */ 'c', + 'g', + 'r', + 'b', + 'n', + 'e', + 9, + 0, + /* 4300 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'n', + 'e', + 9, + 0, + /* 4309 */ 'c', + 'l', + 'r', + 'b', + 'n', + 'e', + 9, + 0, + /* 4317 */ 'l', + 'o', + 'c', + 'n', + 'e', + 9, + 0, + /* 4324 */ 's', + 't', + 'o', + 'c', + 'n', + 'e', + 9, + 0, + /* 4332 */ 'v', + 'f', + 'e', + 'n', + 'e', + 9, + 0, + /* 4339 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'e', + 9, + 0, + /* 4347 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'e', + 9, + 0, + /* 4356 */ 'j', + 'g', + 'n', + 'e', + 9, + 0, + /* 4362 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'e', + 9, + 0, + /* 4371 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'e', + 9, + 0, + /* 4381 */ 'b', + 'i', + 'n', + 'e', + 9, + 0, + /* 4387 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'e', + 9, + 0, + /* 4396 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'e', + 9, + 0, + /* 4406 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'e', + 9, + 0, + /* 4416 */ 'c', + 'i', + 'j', + 'n', + 'e', + 9, + 0, + /* 4423 */ 'c', + 'g', + 'i', + 'j', + 'n', + 'e', + 9, + 0, + /* 4431 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'n', + 'e', + 9, + 0, + /* 4440 */ 'c', + 'l', + 'i', + 'j', + 'n', + 'e', + 9, + 0, + /* 4448 */ 'c', + 'r', + 'j', + 'n', + 'e', + 9, + 0, + /* 4455 */ 'c', + 'g', + 'r', + 'j', + 'n', + 'e', + 9, + 0, + /* 4463 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'n', + 'e', + 9, + 0, + /* 4472 */ 'c', + 'l', + 'r', + 'j', + 'n', + 'e', + 9, + 0, + /* 4480 */ 'v', + 'o', + 'n', + 'e', + 9, + 0, + /* 4486 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'e', + 9, + 0, + /* 4494 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'e', + 9, + 0, + /* 4503 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'e', + 9, + 0, + /* 4513 */ 'c', + 'l', + 'g', + 't', + 'n', + 'e', + 9, + 0, + /* 4521 */ 'c', + 'i', + 't', + 'n', + 'e', + 9, + 0, + /* 4528 */ 'c', + 'l', + 'f', + 'i', + 't', + 'n', + 'e', + 9, + 0, + /* 4537 */ 'c', + 'g', + 'i', + 't', + 'n', + 'e', + 9, + 0, + /* 4545 */ 'c', + 'l', + 'g', + 'i', + 't', + 'n', + 'e', + 9, + 0, + /* 4554 */ 'c', + 'l', + 't', + 'n', + 'e', + 9, + 0, + /* 4561 */ 'c', + 'r', + 't', + 'n', + 'e', + 9, + 0, + /* 4568 */ 'c', + 'g', + 'r', + 't', + 'n', + 'e', + 9, + 0, + /* 4576 */ 'c', + 'l', + 'g', + 'r', + 't', + 'n', + 'e', + 9, + 0, + /* 4585 */ 'c', + 'l', + 'r', + 't', + 'n', + 'e', + 9, + 0, + /* 4593 */ 's', + 'q', + 'e', + 9, + 0, + /* 4598 */ 'l', + 'o', + 'c', + 'r', + 'e', + 9, + 0, + /* 4605 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'e', + 9, + 0, + /* 4613 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'e', + 9, + 0, + /* 4622 */ 't', + 'r', + 't', + 'r', + 'e', + 9, + 0, + /* 4629 */ 'm', + 's', + 'e', + 9, + 0, + /* 4634 */ 'c', + 'u', + 's', + 'e', + 9, + 0, + /* 4640 */ 'i', + 'd', + 't', + 'e', + 9, + 0, + /* 4646 */ 'c', + 'r', + 'd', + 't', + 'e', + 9, + 0, + /* 4653 */ 'c', + 'l', + 'g', + 't', + 'e', + 9, + 0, + /* 4660 */ 'c', + 'i', + 't', + 'e', + 9, + 0, + /* 4666 */ 'c', + 'l', + 'f', + 'i', + 't', + 'e', + 9, + 0, + /* 4674 */ 'c', + 'g', + 'i', + 't', + 'e', + 9, + 0, + /* 4681 */ 'c', + 'l', + 'g', + 'i', + 't', + 'e', + 9, + 0, + /* 4689 */ 'c', + 'l', + 't', + 'e', + 9, + 0, + /* 4695 */ 'i', + 'p', + 't', + 'e', + 9, + 0, + /* 4701 */ 'c', + 'r', + 't', + 'e', + 9, + 0, + /* 4707 */ 'c', + 'g', + 'r', + 't', + 'e', + 9, + 0, + /* 4714 */ 'c', + 'l', + 'g', + 'r', + 't', + 'e', + 9, + 0, + /* 4722 */ 'c', + 'l', + 'r', + 't', + 'e', + 9, + 0, + /* 4729 */ 't', + 'r', + 't', + 'e', + 9, + 0, + /* 4735 */ 's', + 't', + 'e', + 9, + 0, + /* 4740 */ 'l', + 'p', + 's', + 'w', + 'e', + 9, + 0, + /* 4747 */ 'l', + 'x', + 'e', + 9, + 0, + /* 4752 */ 'v', + 'g', + 'f', + 'm', + 'a', + 'f', + 9, + 0, + /* 4760 */ 'v', + 'e', + 's', + 'r', + 'a', + 'f', + 9, + 0, + /* 4768 */ 'v', + 'a', + 'f', + 9, + 0, + /* 4773 */ 's', + 'a', + 'c', + 'f', + 9, + 0, + /* 4779 */ 'v', + 'a', + 'c', + 'c', + 'f', + 9, + 0, + /* 4786 */ 'v', + 'e', + 'c', + 'f', + 9, + 0, + /* 4792 */ 'v', + 'l', + 'c', + 'f', + 9, + 0, + /* 4798 */ 'v', + 's', + 't', + 'r', + 'c', + 'f', + 9, + 0, + /* 4806 */ 'v', + 'f', + 'a', + 'e', + 'f', + 9, + 0, + /* 4813 */ 'v', + 'm', + 'a', + 'e', + 'f', + 9, + 0, + /* 4820 */ 'v', + 's', + 'c', + 'e', + 'f', + 9, + 0, + /* 4827 */ 'v', + 'f', + 'e', + 'e', + 'f', + 9, + 0, + /* 4834 */ 'v', + 'g', + 'e', + 'f', + 9, + 0, + /* 4840 */ 'v', + 'm', + 'a', + 'l', + 'e', + 'f', + 9, + 0, + /* 4848 */ 'v', + 'm', + 'l', + 'e', + 'f', + 9, + 0, + /* 4855 */ 'v', + 'l', + 'e', + 'f', + 9, + 0, + /* 4861 */ 'v', + 'm', + 'e', + 'f', + 9, + 0, + /* 4867 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'f', + 9, + 0, + /* 4875 */ 'v', + 's', + 't', + 'e', + 'f', + 9, + 0, + /* 4882 */ 'a', + 'g', + 'f', + 9, + 0, + /* 4887 */ 'c', + 'g', + 'f', + 9, + 0, + /* 4892 */ 'v', + 's', + 'e', + 'g', + 'f', + 9, + 0, + /* 4899 */ 'a', + 'l', + 'g', + 'f', + 9, + 0, + /* 4905 */ 'c', + 'l', + 'g', + 'f', + 9, + 0, + /* 4911 */ 'l', + 'l', + 'g', + 'f', + 9, + 0, + /* 4917 */ 's', + 'l', + 'g', + 'f', + 9, + 0, + /* 4923 */ 'v', + 's', + 'u', + 'm', + 'g', + 'f', + 9, + 0, + /* 4931 */ 'l', + 'l', + 'z', + 'r', + 'g', + 'f', + 9, + 0, + /* 4939 */ 'd', + 's', + 'g', + 'f', + 9, + 0, + /* 4945 */ 'm', + 's', + 'g', + 'f', + 9, + 0, + /* 4951 */ 'l', + 't', + 'g', + 'f', + 9, + 0, + /* 4957 */ 'v', + 'a', + 'v', + 'g', + 'f', + 9, + 0, + /* 4964 */ 'v', + 'l', + 'v', + 'g', + 'f', + 9, + 0, + /* 4971 */ 'v', + 'm', + 'a', + 'h', + 'f', + 9, + 0, + /* 4978 */ 'v', + 'c', + 'h', + 'f', + 9, + 0, + /* 4984 */ 'i', + 'i', + 'h', + 'f', + 9, + 0, + /* 4990 */ 'l', + 'l', + 'i', + 'h', + 'f', + 9, + 0, + /* 4997 */ 'n', + 'i', + 'h', + 'f', + 9, + 0, + /* 5003 */ 'o', + 'i', + 'h', + 'f', + 9, + 0, + /* 5009 */ 'x', + 'i', + 'h', + 'f', + 9, + 0, + /* 5015 */ 'v', + 'm', + 'a', + 'l', + 'h', + 'f', + 9, + 0, + /* 5023 */ 'c', + 'l', + 'h', + 'f', + 9, + 0, + /* 5029 */ 'v', + 'm', + 'l', + 'h', + 'f', + 9, + 0, + /* 5036 */ 'v', + 'u', + 'p', + 'l', + 'h', + 'f', + 9, + 0, + /* 5044 */ 'v', + 'm', + 'h', + 'f', + 9, + 0, + /* 5050 */ 'v', + 'u', + 'p', + 'h', + 'f', + 9, + 0, + /* 5057 */ 'v', + 'm', + 'r', + 'h', + 'f', + 9, + 0, + /* 5064 */ 'v', + 's', + 'c', + 'b', + 'i', + 'f', + 9, + 0, + /* 5072 */ 'v', + 'l', + 'e', + 'i', + 'f', + 9, + 0, + /* 5079 */ 'v', + 'r', + 'e', + 'p', + 'i', + 'f', + 9, + 0, + /* 5087 */ 's', + 't', + 'c', + 'k', + 'f', + 9, + 0, + /* 5094 */ 'v', + 'p', + 'k', + 'f', + 9, + 0, + /* 5100 */ 'v', + 'm', + 'a', + 'l', + 'f', + 9, + 0, + /* 5107 */ 'v', + 'e', + 'c', + 'l', + 'f', + 9, + 0, + /* 5114 */ 'v', + 'a', + 'v', + 'g', + 'l', + 'f', + 9, + 0, + /* 5122 */ 'v', + 'c', + 'h', + 'l', + 'f', + 9, + 0, + /* 5129 */ 'i', + 'i', + 'l', + 'f', + 9, + 0, + /* 5135 */ 'l', + 'l', + 'i', + 'l', + 'f', + 9, + 0, + /* 5142 */ 'n', + 'i', + 'l', + 'f', + 9, + 0, + /* 5148 */ 'o', + 'i', + 'l', + 'f', + 9, + 0, + /* 5154 */ 'x', + 'i', + 'l', + 'f', + 9, + 0, + /* 5160 */ 'v', + 'u', + 'p', + 'l', + 'l', + 'f', + 9, + 0, + /* 5168 */ 'v', + 'e', + 'r', + 'l', + 'l', + 'f', + 9, + 0, + /* 5176 */ 'v', + 'm', + 'l', + 'f', + 9, + 0, + /* 5182 */ 'v', + 'm', + 'n', + 'l', + 'f', + 9, + 0, + /* 5189 */ 'v', + 'u', + 'p', + 'l', + 'f', + 9, + 0, + /* 5196 */ 'v', + 'm', + 'r', + 'l', + 'f', + 9, + 0, + /* 5203 */ 'v', + 'e', + 's', + 'r', + 'l', + 'f', + 9, + 0, + /* 5211 */ 'v', + 'e', + 's', + 'l', + 'f', + 9, + 0, + /* 5218 */ 'v', + 'm', + 'x', + 'l', + 'f', + 9, + 0, + /* 5225 */ 'v', + 'l', + 'l', + 'e', + 'z', + 'l', + 'f', + 9, + 0, + /* 5234 */ 'v', + 'g', + 'f', + 'm', + 'f', + 9, + 0, + /* 5241 */ 'p', + 'f', + 'm', + 'f', + 9, + 0, + /* 5247 */ 'v', + 'g', + 'm', + 'f', + 9, + 0, + /* 5253 */ 'v', + 'e', + 'r', + 'i', + 'm', + 'f', + 9, + 0, + /* 5261 */ 'k', + 'm', + 'f', + 9, + 0, + /* 5266 */ 'v', + 'm', + 'n', + 'f', + 9, + 0, + /* 5272 */ 'v', + 'm', + 'a', + 'o', + 'f', + 9, + 0, + /* 5279 */ 'v', + 'm', + 'a', + 'l', + 'o', + 'f', + 9, + 0, + /* 5287 */ 'v', + 'm', + 'l', + 'o', + 'f', + 9, + 0, + /* 5294 */ 'v', + 'm', + 'o', + 'f', + 9, + 0, + /* 5300 */ 'v', + 'l', + 'r', + 'e', + 'p', + 'f', + 9, + 0, + /* 5308 */ 'v', + 'r', + 'e', + 'p', + 'f', + 9, + 0, + /* 5315 */ 'v', + 'l', + 'p', + 'f', + 9, + 0, + /* 5321 */ 'v', + 'c', + 'e', + 'q', + 'f', + 9, + 0, + /* 5328 */ 'v', + 's', + 'u', + 'm', + 'q', + 'f', + 9, + 0, + /* 5336 */ 'v', + 'i', + 's', + 't', + 'r', + 'f', + 9, + 0, + /* 5344 */ 'l', + 'z', + 'r', + 'f', + 9, + 0, + /* 5350 */ 'v', + 'p', + 'k', + 's', + 'f', + 9, + 0, + /* 5357 */ 'v', + 'p', + 'k', + 'l', + 's', + 'f', + 9, + 0, + /* 5365 */ 'v', + 's', + 'f', + 9, + 0, + /* 5370 */ 'v', + 'p', + 'o', + 'p', + 'c', + 't', + 'f', + 9, + 0, + /* 5379 */ 'p', + 't', + 'f', + 9, + 0, + /* 5384 */ 'c', + 'u', + 'u', + 't', + 'f', + 9, + 0, + /* 5391 */ 'v', + 'e', + 's', + 'r', + 'a', + 'v', + 'f', + 9, + 0, + /* 5400 */ 'v', + 'l', + 'g', + 'v', + 'f', + 9, + 0, + /* 5407 */ 'v', + 'e', + 'r', + 'l', + 'l', + 'v', + 'f', + 9, + 0, + /* 5416 */ 'v', + 'e', + 's', + 'r', + 'l', + 'v', + 'f', + 9, + 0, + /* 5425 */ 'v', + 'e', + 's', + 'l', + 'v', + 'f', + 9, + 0, + /* 5433 */ 'v', + 'm', + 'x', + 'f', + 9, + 0, + /* 5439 */ 'v', + 's', + 't', + 'r', + 'c', + 'z', + 'f', + 9, + 0, + /* 5448 */ 'v', + 'f', + 'a', + 'e', + 'z', + 'f', + 9, + 0, + /* 5456 */ 'v', + 'f', + 'e', + 'e', + 'z', + 'f', + 9, + 0, + /* 5464 */ 'v', + 'l', + 'l', + 'e', + 'z', + 'f', + 9, + 0, + /* 5472 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'z', + 'f', + 9, + 0, + /* 5481 */ 'v', + 'c', + 'l', + 'z', + 'f', + 9, + 0, + /* 5488 */ 'v', + 'c', + 't', + 'z', + 'f', + 9, + 0, + /* 5495 */ 'l', + 'a', + 'a', + 'g', + 9, + 0, + /* 5501 */ 'e', + 'c', + 'a', + 'g', + 9, + 0, + /* 5507 */ 'd', + 'i', + 'a', + 'g', + 9, + 0, + /* 5513 */ 's', + 'l', + 'a', + 'g', + 9, + 0, + /* 5519 */ 'v', + 'g', + 'f', + 'm', + 'a', + 'g', + 9, + 0, + /* 5527 */ 'l', + 'r', + 'a', + 'g', + 9, + 0, + /* 5533 */ 'v', + 'e', + 's', + 'r', + 'a', + 'g', + 9, + 0, + /* 5541 */ 's', + 't', + 'r', + 'a', + 'g', + 9, + 0, + /* 5548 */ 'l', + 'u', + 'r', + 'a', + 'g', + 9, + 0, + /* 5555 */ 'v', + 'a', + 'g', + 9, + 0, + /* 5560 */ 's', + 'l', + 'b', + 'g', + 9, + 0, + /* 5566 */ 'r', + 'i', + 's', + 'b', + 'g', + 9, + 0, + /* 5573 */ 'r', + 'n', + 's', + 'b', + 'g', + 9, + 0, + /* 5580 */ 'r', + 'o', + 's', + 'b', + 'g', + 9, + 0, + /* 5587 */ 'r', + 'x', + 's', + 'b', + 'g', + 9, + 0, + /* 5594 */ 'v', + 'c', + 'v', + 'b', + 'g', + 9, + 0, + /* 5601 */ 't', + 'r', + 'a', + 'c', + 'g', + 9, + 0, + /* 5608 */ 'v', + 'a', + 'c', + 'c', + 'g', + 9, + 0, + /* 5615 */ 'v', + 'e', + 'c', + 'g', + 9, + 0, + /* 5621 */ 'a', + 'l', + 'c', + 'g', + 9, + 0, + /* 5627 */ 'v', + 'l', + 'c', + 'g', + 9, + 0, + /* 5633 */ 'l', + 'o', + 'c', + 'g', + 9, + 0, + /* 5639 */ 's', + 't', + 'o', + 'c', + 'g', + 9, + 0, + /* 5646 */ 'v', + 'c', + 'd', + 'g', + 9, + 0, + /* 5652 */ 'l', + 'p', + 'd', + 'g', + 9, + 0, + /* 5658 */ 'v', + 'c', + 'v', + 'd', + 'g', + 9, + 0, + /* 5665 */ 'v', + 's', + 'c', + 'e', + 'g', + 9, + 0, + /* 5672 */ 'v', + 'g', + 'e', + 'g', + 9, + 0, + /* 5678 */ 'v', + 'l', + 'e', + 'g', + 9, + 0, + /* 5684 */ 'b', + 'x', + 'l', + 'e', + 'g', + 9, + 0, + /* 5691 */ 'e', + 'r', + 'e', + 'g', + 9, + 0, + /* 5697 */ 'v', + 's', + 'e', + 'g', + 9, + 0, + /* 5703 */ 'v', + 's', + 't', + 'e', + 'g', + 9, + 0, + /* 5710 */ 'e', + 'r', + 'e', + 'g', + 'g', + 9, + 0, + /* 5717 */ 'l', + 'g', + 'g', + 9, + 0, + /* 5722 */ 'v', + 'a', + 'v', + 'g', + 'g', + 9, + 0, + /* 5729 */ 'v', + 'l', + 'v', + 'g', + 'g', + 9, + 0, + /* 5736 */ 'r', + 'i', + 's', + 'b', + 'h', + 'g', + 9, + 0, + /* 5744 */ 'v', + 'c', + 'h', + 'g', + 9, + 0, + /* 5750 */ 'v', + 'm', + 'r', + 'h', + 'g', + 9, + 0, + /* 5757 */ 'b', + 'x', + 'h', + 'g', + 9, + 0, + /* 5763 */ 'b', + 'r', + 'x', + 'h', + 'g', + 9, + 0, + /* 5770 */ 'v', + 's', + 'c', + 'b', + 'i', + 'g', + 9, + 0, + /* 5778 */ 'v', + 'l', + 'e', + 'i', + 'g', + 9, + 0, + /* 5785 */ 'v', + 'r', + 'e', + 'p', + 'i', + 'g', + 9, + 0, + /* 5793 */ 'j', + 'g', + 9, + 0, + /* 5797 */ 'v', + 'p', + 'k', + 'g', + 9, + 0, + /* 5803 */ 'l', + 'a', + 'a', + 'l', + 'g', + 9, + 0, + /* 5810 */ 'r', + 'i', + 's', + 'b', + 'l', + 'g', + 9, + 0, + /* 5818 */ 'v', + 'e', + 'c', + 'l', + 'g', + 9, + 0, + /* 5825 */ 'v', + 'c', + 'd', + 'l', + 'g', + 9, + 0, + /* 5832 */ 'v', + 'a', + 'v', + 'g', + 'l', + 'g', + 9, + 0, + /* 5840 */ 'v', + 'c', + 'h', + 'l', + 'g', + 9, + 0, + /* 5847 */ 'v', + 'e', + 'r', + 'l', + 'l', + 'g', + 9, + 0, + /* 5855 */ 's', + 'l', + 'l', + 'g', + 9, + 0, + /* 5861 */ 'm', + 'l', + 'g', + 9, + 0, + /* 5866 */ 'v', + 'm', + 'n', + 'l', + 'g', + 9, + 0, + /* 5873 */ 'v', + 'm', + 'r', + 'l', + 'g', + 9, + 0, + /* 5880 */ 'v', + 'e', + 's', + 'r', + 'l', + 'g', + 9, + 0, + /* 5888 */ 'v', + 'e', + 's', + 'l', + 'g', + 9, + 0, + /* 5895 */ 'v', + 'm', + 's', + 'l', + 'g', + 9, + 0, + /* 5902 */ 'l', + 'c', + 't', + 'l', + 'g', + 9, + 0, + /* 5909 */ 'v', + 'm', + 'x', + 'l', + 'g', + 9, + 0, + /* 5916 */ 'b', + 'r', + 'x', + 'l', + 'g', + 9, + 0, + /* 5923 */ 'v', + 'g', + 'f', + 'm', + 'g', + 9, + 0, + /* 5930 */ 'v', + 'g', + 'm', + 'g', + 9, + 0, + /* 5936 */ 'v', + 'e', + 'r', + 'i', + 'm', + 'g', + 9, + 0, + /* 5944 */ 'l', + 'm', + 'g', + 9, + 0, + /* 5949 */ 's', + 't', + 'm', + 'g', + 9, + 0, + /* 5955 */ 'v', + 's', + 'u', + 'm', + 'g', + 9, + 0, + /* 5962 */ 'l', + 'a', + 'n', + 'g', + 9, + 0, + /* 5968 */ 'v', + 'm', + 'n', + 'g', + 9, + 0, + /* 5974 */ 'l', + 'a', + 'o', + 'g', + 9, + 0, + /* 5980 */ 'v', + 'l', + 'r', + 'e', + 'p', + 'g', + 9, + 0, + /* 5988 */ 'v', + 'r', + 'e', + 'p', + 'g', + 9, + 0, + /* 5995 */ 'v', + 'l', + 'p', + 'g', + 9, + 0, + /* 6001 */ 'c', + 's', + 'p', + 'g', + 9, + 0, + /* 6007 */ 'm', + 'v', + 'p', + 'g', + 9, + 0, + /* 6013 */ 'v', + 'c', + 'e', + 'q', + 'g', + 9, + 0, + /* 6020 */ 'v', + 's', + 'u', + 'm', + 'q', + 'g', + 9, + 0, + /* 6028 */ 's', + 't', + 'u', + 'r', + 'g', + 9, + 0, + /* 6035 */ 'l', + 'z', + 'r', + 'g', + 9, + 0, + /* 6041 */ 'b', + 's', + 'g', + 9, + 0, + /* 6046 */ 'c', + 's', + 'g', + 9, + 0, + /* 6051 */ 'c', + 'd', + 's', + 'g', + 9, + 0, + /* 6057 */ 'l', + 'l', + 'g', + 'f', + 's', + 'g', + 9, + 0, + /* 6065 */ 'v', + 'p', + 'k', + 's', + 'g', + 9, + 0, + /* 6072 */ 'v', + 'p', + 'k', + 'l', + 's', + 'g', + 9, + 0, + /* 6080 */ 'm', + 's', + 'g', + 9, + 0, + /* 6085 */ 'v', + 's', + 'g', + 9, + 0, + /* 6090 */ 'b', + 'c', + 't', + 'g', + 9, + 0, + /* 6096 */ 'e', + 'c', + 't', + 'g', + 9, + 0, + /* 6102 */ 'v', + 'p', + 'o', + 'p', + 'c', + 't', + 'g', + 9, + 0, + /* 6111 */ 'b', + 'r', + 'c', + 't', + 'g', + 9, + 0, + /* 6118 */ 's', + 't', + 'c', + 't', + 'g', + 9, + 0, + /* 6125 */ 'l', + 't', + 'g', + 9, + 0, + /* 6130 */ 'n', + 't', + 's', + 't', + 'g', + 9, + 0, + /* 6137 */ 'v', + 'e', + 's', + 'r', + 'a', + 'v', + 'g', + 9, + 0, + /* 6146 */ 'v', + 'a', + 'v', + 'g', + 9, + 0, + /* 6152 */ 'v', + 'l', + 'g', + 'v', + 'g', + 9, + 0, + /* 6159 */ 'v', + 'e', + 'r', + 'l', + 'l', + 'v', + 'g', + 9, + 0, + /* 6168 */ 'v', + 'e', + 's', + 'r', + 'l', + 'v', + 'g', + 9, + 0, + /* 6177 */ 'v', + 'e', + 's', + 'l', + 'v', + 'g', + 9, + 0, + /* 6185 */ 'v', + 'l', + 'v', + 'g', + 9, + 0, + /* 6191 */ 'l', + 'r', + 'v', + 'g', + 9, + 0, + /* 6197 */ 's', + 't', + 'r', + 'v', + 'g', + 9, + 0, + /* 6204 */ 'l', + 'a', + 'x', + 'g', + 9, + 0, + /* 6210 */ 'v', + 'm', + 'x', + 'g', + 9, + 0, + /* 6216 */ 'v', + 'l', + 'l', + 'e', + 'z', + 'g', + 9, + 0, + /* 6224 */ 'v', + 'c', + 'l', + 'z', + 'g', + 9, + 0, + /* 6231 */ 'v', + 'c', + 't', + 'z', + 'g', + 9, + 0, + /* 6238 */ 'v', + 'g', + 'f', + 'm', + 'a', + 'h', + 9, + 0, + /* 6246 */ 'v', + 'm', + 'a', + 'h', + 9, + 0, + /* 6252 */ 'v', + 'e', + 's', + 'r', + 'a', + 'h', + 9, + 0, + /* 6260 */ 'v', + 'a', + 'h', + 9, + 0, + /* 6265 */ 'c', + 'i', + 'b', + 'h', + 9, + 0, + /* 6271 */ 'c', + 'g', + 'i', + 'b', + 'h', + 9, + 0, + /* 6278 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'h', + 9, + 0, + /* 6286 */ 'c', + 'l', + 'i', + 'b', + 'h', + 9, + 0, + /* 6293 */ 'l', + 'b', + 'h', + 9, + 0, + /* 6298 */ 'c', + 'r', + 'b', + 'h', + 9, + 0, + /* 6304 */ 'c', + 'g', + 'r', + 'b', + 'h', + 9, + 0, + /* 6311 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'h', + 9, + 0, + /* 6319 */ 'c', + 'l', + 'r', + 'b', + 'h', + 9, + 0, + /* 6326 */ 'v', + 'a', + 'c', + 'c', + 'h', + 9, + 0, + /* 6333 */ 'v', + 'e', + 'c', + 'h', + 9, + 0, + /* 6339 */ 'v', + 'f', + 'c', + 'h', + 9, + 0, + /* 6345 */ 'l', + 'l', + 'c', + 'h', + 9, + 0, + /* 6351 */ 'v', + 'l', + 'c', + 'h', + 9, + 0, + /* 6357 */ 'l', + 'o', + 'c', + 'h', + 9, + 0, + /* 6363 */ 's', + 't', + 'o', + 'c', + 'h', + 9, + 0, + /* 6370 */ 'v', + 's', + 't', + 'r', + 'c', + 'h', + 9, + 0, + /* 6378 */ 'm', + 's', + 'c', + 'h', + 9, + 0, + /* 6384 */ 's', + 's', + 'c', + 'h', + 9, + 0, + /* 6390 */ 's', + 't', + 's', + 'c', + 'h', + 9, + 0, + /* 6397 */ 's', + 't', + 'c', + 'h', + 9, + 0, + /* 6403 */ 'v', + 'c', + 'h', + 9, + 0, + /* 6408 */ 'v', + 'f', + 'a', + 'e', + 'h', + 9, + 0, + /* 6415 */ 'v', + 'm', + 'a', + 'e', + 'h', + 9, + 0, + /* 6422 */ 'v', + 'f', + 'e', + 'e', + 'h', + 9, + 0, + /* 6429 */ 'v', + 'm', + 'a', + 'l', + 'e', + 'h', + 9, + 0, + /* 6437 */ 'v', + 'm', + 'l', + 'e', + 'h', + 9, + 0, + /* 6444 */ 'v', + 'l', + 'e', + 'h', + 9, + 0, + /* 6450 */ 'v', + 'm', + 'e', + 'h', + 9, + 0, + /* 6456 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'h', + 9, + 0, + /* 6464 */ 'v', + 's', + 't', + 'e', + 'h', + 9, + 0, + /* 6471 */ 'l', + 'o', + 'c', + 'f', + 'h', + 9, + 0, + /* 6478 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 9, + 0, + /* 6486 */ 'l', + 'f', + 'h', + 9, + 0, + /* 6491 */ 's', + 't', + 'f', + 'h', + 9, + 0, + /* 6497 */ 'a', + 'g', + 'h', + 9, + 0, + /* 6502 */ 'l', + 'o', + 'c', + 'g', + 'h', + 9, + 0, + /* 6509 */ 's', + 't', + 'o', + 'c', + 'g', + 'h', + 9, + 0, + /* 6517 */ 'v', + 's', + 'e', + 'g', + 'h', + 9, + 0, + /* 6524 */ 'j', + 'g', + 'h', + 9, + 0, + /* 6529 */ 'l', + 'l', + 'g', + 'h', + 9, + 0, + /* 6535 */ 'v', + 's', + 'u', + 'm', + 'g', + 'h', + 9, + 0, + /* 6543 */ 's', + 'g', + 'h', + 9, + 0, + /* 6548 */ 'v', + 'a', + 'v', + 'g', + 'h', + 9, + 0, + /* 6555 */ 'v', + 'l', + 'v', + 'g', + 'h', + 9, + 0, + /* 6562 */ 'v', + 'm', + 'a', + 'h', + 'h', + 9, + 0, + /* 6569 */ 'v', + 'c', + 'h', + 'h', + 9, + 0, + /* 6575 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'h', + 9, + 0, + /* 6583 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'h', + 9, + 0, + /* 6592 */ 'i', + 'i', + 'h', + 'h', + 9, + 0, + /* 6598 */ 'l', + 'l', + 'i', + 'h', + 'h', + 9, + 0, + /* 6605 */ 'n', + 'i', + 'h', + 'h', + 9, + 0, + /* 6611 */ 'o', + 'i', + 'h', + 'h', + 9, + 0, + /* 6617 */ 'v', + 'm', + 'a', + 'l', + 'h', + 'h', + 9, + 0, + /* 6625 */ 'l', + 'l', + 'h', + 'h', + 9, + 0, + /* 6631 */ 'v', + 'm', + 'l', + 'h', + 'h', + 9, + 0, + /* 6638 */ 'v', + 'u', + 'p', + 'l', + 'h', + 'h', + 9, + 0, + /* 6646 */ 't', + 'm', + 'h', + 'h', + 9, + 0, + /* 6652 */ 'v', + 'm', + 'h', + 'h', + 9, + 0, + /* 6658 */ 'v', + 'u', + 'p', + 'h', + 'h', + 9, + 0, + /* 6665 */ 'v', + 'm', + 'r', + 'h', + 'h', + 9, + 0, + /* 6672 */ 's', + 't', + 'h', + 'h', + 9, + 0, + /* 6678 */ 'a', + 'i', + 'h', + 9, + 0, + /* 6683 */ 'v', + 's', + 'c', + 'b', + 'i', + 'h', + 9, + 0, + /* 6691 */ 'c', + 'i', + 'h', + 9, + 0, + /* 6696 */ 'v', + 'l', + 'e', + 'i', + 'h', + 9, + 0, + /* 6703 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'h', + 9, + 0, + /* 6711 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'h', + 9, + 0, + /* 6720 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'h', + 9, + 0, + /* 6729 */ 'c', + 'l', + 'i', + 'h', + 9, + 0, + /* 6735 */ 'v', + 'r', + 'e', + 'p', + 'i', + 'h', + 9, + 0, + /* 6743 */ 'a', + 'l', + 's', + 'i', + 'h', + 9, + 0, + /* 6750 */ 'c', + 'i', + 'j', + 'h', + 9, + 0, + /* 6756 */ 'c', + 'g', + 'i', + 'j', + 'h', + 9, + 0, + /* 6763 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'h', + 9, + 0, + /* 6771 */ 'c', + 'l', + 'i', + 'j', + 'h', + 9, + 0, + /* 6778 */ 'c', + 'r', + 'j', + 'h', + 9, + 0, + /* 6784 */ 'c', + 'g', + 'r', + 'j', + 'h', + 9, + 0, + /* 6791 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'h', + 9, + 0, + /* 6799 */ 'c', + 'l', + 'r', + 'j', + 'h', + 9, + 0, + /* 6806 */ 'v', + 'p', + 'k', + 'h', + 9, + 0, + /* 6812 */ 'v', + 'm', + 'a', + 'l', + 'h', + 9, + 0, + /* 6819 */ 'c', + 'i', + 'b', + 'l', + 'h', + 9, + 0, + /* 6826 */ 'c', + 'g', + 'i', + 'b', + 'l', + 'h', + 9, + 0, + /* 6834 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'l', + 'h', + 9, + 0, + /* 6843 */ 'c', + 'l', + 'i', + 'b', + 'l', + 'h', + 9, + 0, + /* 6851 */ 'c', + 'r', + 'b', + 'l', + 'h', + 9, + 0, + /* 6858 */ 'c', + 'g', + 'r', + 'b', + 'l', + 'h', + 9, + 0, + /* 6866 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'l', + 'h', + 9, + 0, + /* 6875 */ 'c', + 'l', + 'r', + 'b', + 'l', + 'h', + 9, + 0, + /* 6883 */ 'v', + 'e', + 'c', + 'l', + 'h', + 9, + 0, + /* 6890 */ 'l', + 'o', + 'c', + 'l', + 'h', + 9, + 0, + /* 6897 */ 's', + 't', + 'o', + 'c', + 'l', + 'h', + 9, + 0, + /* 6905 */ 'l', + 'o', + 'c', + 'g', + 'l', + 'h', + 9, + 0, + /* 6913 */ 's', + 't', + 'o', + 'c', + 'g', + 'l', + 'h', + 9, + 0, + /* 6922 */ 'j', + 'g', + 'l', + 'h', + 9, + 0, + /* 6928 */ 'v', + 'a', + 'v', + 'g', + 'l', + 'h', + 9, + 0, + /* 6936 */ 'v', + 'c', + 'h', + 'l', + 'h', + 9, + 0, + /* 6943 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'l', + 'h', + 9, + 0, + /* 6952 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'l', + 'h', + 9, + 0, + /* 6962 */ 'b', + 'i', + 'l', + 'h', + 9, + 0, + /* 6968 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'l', + 'h', + 9, + 0, + /* 6977 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'l', + 'h', + 9, + 0, + /* 6987 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'l', + 'h', + 9, + 0, + /* 6997 */ 'i', + 'i', + 'l', + 'h', + 9, + 0, + /* 7003 */ 'l', + 'l', + 'i', + 'l', + 'h', + 9, + 0, + /* 7010 */ 'n', + 'i', + 'l', + 'h', + 9, + 0, + /* 7016 */ 'o', + 'i', + 'l', + 'h', + 9, + 0, + /* 7022 */ 'c', + 'i', + 'j', + 'l', + 'h', + 9, + 0, + /* 7029 */ 'c', + 'g', + 'i', + 'j', + 'l', + 'h', + 9, + 0, + /* 7037 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'l', + 'h', + 9, + 0, + /* 7046 */ 'c', + 'l', + 'i', + 'j', + 'l', + 'h', + 9, + 0, + /* 7054 */ 'c', + 'r', + 'j', + 'l', + 'h', + 9, + 0, + /* 7061 */ 'c', + 'g', + 'r', + 'j', + 'l', + 'h', + 9, + 0, + /* 7069 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'l', + 'h', + 9, + 0, + /* 7078 */ 'c', + 'l', + 'r', + 'j', + 'l', + 'h', + 9, + 0, + /* 7086 */ 'v', + 'u', + 'p', + 'l', + 'l', + 'h', + 9, + 0, + /* 7094 */ 'v', + 'e', + 'r', + 'l', + 'l', + 'h', + 9, + 0, + /* 7102 */ 't', + 'm', + 'l', + 'h', + 9, + 0, + /* 7108 */ 'v', + 'm', + 'l', + 'h', + 9, + 0, + /* 7114 */ 'c', + 'i', + 'b', + 'n', + 'l', + 'h', + 9, + 0, + /* 7122 */ 'c', + 'g', + 'i', + 'b', + 'n', + 'l', + 'h', + 9, + 0, + /* 7131 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'n', + 'l', + 'h', + 9, + 0, + /* 7141 */ 'c', + 'l', + 'i', + 'b', + 'n', + 'l', + 'h', + 9, + 0, + /* 7150 */ 'c', + 'r', + 'b', + 'n', + 'l', + 'h', + 9, + 0, + /* 7158 */ 'c', + 'g', + 'r', + 'b', + 'n', + 'l', + 'h', + 9, + 0, + /* 7167 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'n', + 'l', + 'h', + 9, + 0, + /* 7177 */ 'c', + 'l', + 'r', + 'b', + 'n', + 'l', + 'h', + 9, + 0, + /* 7186 */ 'l', + 'o', + 'c', + 'n', + 'l', + 'h', + 9, + 0, + /* 7194 */ 's', + 't', + 'o', + 'c', + 'n', + 'l', + 'h', + 9, + 0, + /* 7203 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'l', + 'h', + 9, + 0, + /* 7212 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'l', + 'h', + 9, + 0, + /* 7222 */ 'j', + 'g', + 'n', + 'l', + 'h', + 9, + 0, + /* 7229 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'l', + 'h', + 9, + 0, + /* 7239 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'l', + 'h', + 9, + 0, + /* 7250 */ 'b', + 'i', + 'n', + 'l', + 'h', + 9, + 0, + /* 7257 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'l', + 'h', + 9, + 0, + /* 7267 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'l', + 'h', + 9, + 0, + /* 7278 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'l', + 'h', + 9, + 0, + /* 7289 */ 'c', + 'i', + 'j', + 'n', + 'l', + 'h', + 9, + 0, + /* 7297 */ 'c', + 'g', + 'i', + 'j', + 'n', + 'l', + 'h', + 9, + 0, + /* 7306 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'n', + 'l', + 'h', + 9, + 0, + /* 7316 */ 'c', + 'l', + 'i', + 'j', + 'n', + 'l', + 'h', + 9, + 0, + /* 7325 */ 'c', + 'r', + 'j', + 'n', + 'l', + 'h', + 9, + 0, + /* 7333 */ 'c', + 'g', + 'r', + 'j', + 'n', + 'l', + 'h', + 9, + 0, + /* 7342 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'n', + 'l', + 'h', + 9, + 0, + /* 7352 */ 'c', + 'l', + 'r', + 'j', + 'n', + 'l', + 'h', + 9, + 0, + /* 7361 */ 'v', + 'm', + 'n', + 'l', + 'h', + 9, + 0, + /* 7368 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'l', + 'h', + 9, + 0, + /* 7377 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'l', + 'h', + 9, + 0, + /* 7387 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'l', + 'h', + 9, + 0, + /* 7398 */ 'c', + 'l', + 'g', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7407 */ 'c', + 'i', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7415 */ 'c', + 'l', + 'f', + 'i', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7425 */ 'c', + 'g', + 'i', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7434 */ 'c', + 'l', + 'g', + 'i', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7444 */ 'c', + 'l', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7452 */ 'c', + 'r', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7460 */ 'c', + 'g', + 'r', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7469 */ 'c', + 'l', + 'g', + 'r', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7479 */ 'c', + 'l', + 'r', + 't', + 'n', + 'l', + 'h', + 9, + 0, + /* 7488 */ 'v', + 'u', + 'p', + 'l', + 'h', + 9, + 0, + /* 7495 */ 'l', + 'o', + 'c', + 'r', + 'l', + 'h', + 9, + 0, + /* 7503 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'l', + 'h', + 9, + 0, + /* 7512 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'l', + 'h', + 9, + 0, + /* 7522 */ 'v', + 'm', + 'r', + 'l', + 'h', + 9, + 0, + /* 7529 */ 'v', + 'e', + 's', + 'r', + 'l', + 'h', + 9, + 0, + /* 7537 */ 'v', + 'e', + 's', + 'l', + 'h', + 9, + 0, + /* 7544 */ 'c', + 'l', + 'g', + 't', + 'l', + 'h', + 9, + 0, + /* 7552 */ 'c', + 'i', + 't', + 'l', + 'h', + 9, + 0, + /* 7559 */ 'c', + 'l', + 'f', + 'i', + 't', + 'l', + 'h', + 9, + 0, + /* 7568 */ 'c', + 'g', + 'i', + 't', + 'l', + 'h', + 9, + 0, + /* 7576 */ 'c', + 'l', + 'g', + 'i', + 't', + 'l', + 'h', + 9, + 0, + /* 7585 */ 'c', + 'l', + 't', + 'l', + 'h', + 9, + 0, + /* 7592 */ 'c', + 'r', + 't', + 'l', + 'h', + 9, + 0, + /* 7599 */ 'c', + 'g', + 'r', + 't', + 'l', + 'h', + 9, + 0, + /* 7607 */ 'c', + 'l', + 'g', + 'r', + 't', + 'l', + 'h', + 9, + 0, + /* 7616 */ 'c', + 'l', + 'r', + 't', + 'l', + 'h', + 9, + 0, + /* 7624 */ 'v', + 'm', + 'x', + 'l', + 'h', + 9, + 0, + /* 7631 */ 'i', + 'c', + 'm', + 'h', + 9, + 0, + /* 7637 */ 's', + 't', + 'c', + 'm', + 'h', + 9, + 0, + /* 7644 */ 'v', + 'g', + 'f', + 'm', + 'h', + 9, + 0, + /* 7651 */ 'v', + 'g', + 'm', + 'h', + 9, + 0, + /* 7657 */ 'v', + 'e', + 'r', + 'i', + 'm', + 'h', + 9, + 0, + /* 7665 */ 'c', + 'l', + 'm', + 'h', + 9, + 0, + /* 7671 */ 's', + 't', + 'm', + 'h', + 9, + 0, + /* 7677 */ 'v', + 's', + 'u', + 'm', + 'h', + 9, + 0, + /* 7684 */ 'v', + 'm', + 'h', + 9, + 0, + /* 7689 */ 'c', + 'i', + 'b', + 'n', + 'h', + 9, + 0, + /* 7696 */ 'c', + 'g', + 'i', + 'b', + 'n', + 'h', + 9, + 0, + /* 7704 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'n', + 'h', + 9, + 0, + /* 7713 */ 'c', + 'l', + 'i', + 'b', + 'n', + 'h', + 9, + 0, + /* 7721 */ 'c', + 'r', + 'b', + 'n', + 'h', + 9, + 0, + /* 7728 */ 'c', + 'g', + 'r', + 'b', + 'n', + 'h', + 9, + 0, + /* 7736 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'n', + 'h', + 9, + 0, + /* 7745 */ 'c', + 'l', + 'r', + 'b', + 'n', + 'h', + 9, + 0, + /* 7753 */ 'l', + 'o', + 'c', + 'n', + 'h', + 9, + 0, + /* 7760 */ 's', + 't', + 'o', + 'c', + 'n', + 'h', + 9, + 0, + /* 7768 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'h', + 9, + 0, + /* 7776 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'h', + 9, + 0, + /* 7785 */ 'j', + 'g', + 'n', + 'h', + 9, + 0, + /* 7791 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'h', + 9, + 0, + /* 7800 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'h', + 9, + 0, + /* 7810 */ 'b', + 'i', + 'n', + 'h', + 9, + 0, + /* 7816 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'h', + 9, + 0, + /* 7825 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'h', + 9, + 0, + /* 7835 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'h', + 9, + 0, + /* 7845 */ 'c', + 'i', + 'j', + 'n', + 'h', + 9, + 0, + /* 7852 */ 'c', + 'g', + 'i', + 'j', + 'n', + 'h', + 9, + 0, + /* 7860 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'n', + 'h', + 9, + 0, + /* 7869 */ 'c', + 'l', + 'i', + 'j', + 'n', + 'h', + 9, + 0, + /* 7877 */ 'c', + 'r', + 'j', + 'n', + 'h', + 9, + 0, + /* 7884 */ 'c', + 'g', + 'r', + 'j', + 'n', + 'h', + 9, + 0, + /* 7892 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'n', + 'h', + 9, + 0, + /* 7901 */ 'c', + 'l', + 'r', + 'j', + 'n', + 'h', + 9, + 0, + /* 7909 */ 'v', + 'm', + 'n', + 'h', + 9, + 0, + /* 7915 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'h', + 9, + 0, + /* 7923 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'h', + 9, + 0, + /* 7932 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'h', + 9, + 0, + /* 7942 */ 'c', + 'l', + 'g', + 't', + 'n', + 'h', + 9, + 0, + /* 7950 */ 'c', + 'i', + 't', + 'n', + 'h', + 9, + 0, + /* 7957 */ 'c', + 'l', + 'f', + 'i', + 't', + 'n', + 'h', + 9, + 0, + /* 7966 */ 'c', + 'g', + 'i', + 't', + 'n', + 'h', + 9, + 0, + /* 7974 */ 'c', + 'l', + 'g', + 'i', + 't', + 'n', + 'h', + 9, + 0, + /* 7983 */ 'c', + 'l', + 't', + 'n', + 'h', + 9, + 0, + /* 7990 */ 'c', + 'r', + 't', + 'n', + 'h', + 9, + 0, + /* 7997 */ 'c', + 'g', + 'r', + 't', + 'n', + 'h', + 9, + 0, + /* 8005 */ 'c', + 'l', + 'g', + 'r', + 't', + 'n', + 'h', + 9, + 0, + /* 8014 */ 'c', + 'l', + 'r', + 't', + 'n', + 'h', + 9, + 0, + /* 8022 */ 'v', + 'm', + 'a', + 'o', + 'h', + 9, + 0, + /* 8029 */ 'v', + 'm', + 'a', + 'l', + 'o', + 'h', + 9, + 0, + /* 8037 */ 'v', + 'm', + 'l', + 'o', + 'h', + 9, + 0, + /* 8044 */ 'v', + 'm', + 'o', + 'h', + 9, + 0, + /* 8050 */ 'v', + 'l', + 'r', + 'e', + 'p', + 'h', + 9, + 0, + /* 8058 */ 'v', + 'r', + 'e', + 'p', + 'h', + 9, + 0, + /* 8065 */ 'v', + 'l', + 'p', + 'h', + 9, + 0, + /* 8071 */ 'v', + 'u', + 'p', + 'h', + 9, + 0, + /* 8077 */ 'v', + 'c', + 'e', + 'q', + 'h', + 9, + 0, + /* 8084 */ 'l', + 'o', + 'c', + 'r', + 'h', + 9, + 0, + /* 8091 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'h', + 9, + 0, + /* 8099 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'h', + 9, + 0, + /* 8108 */ 'v', + 'm', + 'r', + 'h', + 9, + 0, + /* 8114 */ 'v', + 'i', + 's', + 't', + 'r', + 'h', + 9, + 0, + /* 8122 */ 'v', + 'p', + 'k', + 's', + 'h', + 9, + 0, + /* 8129 */ 'v', + 'p', + 'k', + 'l', + 's', + 'h', + 9, + 0, + /* 8137 */ 'v', + 's', + 'h', + 9, + 0, + /* 8142 */ 'v', + 'p', + 'o', + 'p', + 'c', + 't', + 'h', + 9, + 0, + /* 8151 */ 'b', + 'r', + 'c', + 't', + 'h', + 9, + 0, + /* 8158 */ 'c', + 'l', + 'g', + 't', + 'h', + 9, + 0, + /* 8165 */ 'c', + 'i', + 't', + 'h', + 9, + 0, + /* 8171 */ 'c', + 'l', + 'f', + 'i', + 't', + 'h', + 9, + 0, + /* 8179 */ 'c', + 'g', + 'i', + 't', + 'h', + 9, + 0, + /* 8186 */ 'c', + 'l', + 'g', + 'i', + 't', + 'h', + 9, + 0, + /* 8194 */ 'c', + 'l', + 't', + 'h', + 9, + 0, + /* 8200 */ 'c', + 'r', + 't', + 'h', + 9, + 0, + /* 8206 */ 'c', + 'g', + 'r', + 't', + 'h', + 9, + 0, + /* 8213 */ 'c', + 'l', + 'g', + 'r', + 't', + 'h', + 9, + 0, + /* 8221 */ 'c', + 'l', + 'r', + 't', + 'h', + 9, + 0, + /* 8228 */ 's', + 't', + 'h', + 9, + 0, + /* 8233 */ 'v', + 'e', + 's', + 'r', + 'a', + 'v', + 'h', + 9, + 0, + /* 8242 */ 'v', + 'l', + 'g', + 'v', + 'h', + 9, + 0, + /* 8249 */ 'v', + 'e', + 'r', + 'l', + 'l', + 'v', + 'h', + 9, + 0, + /* 8258 */ 'v', + 'e', + 's', + 'r', + 'l', + 'v', + 'h', + 9, + 0, + /* 8267 */ 'v', + 'e', + 's', + 'l', + 'v', + 'h', + 9, + 0, + /* 8275 */ 'l', + 'r', + 'v', + 'h', + 9, + 0, + /* 8281 */ 's', + 't', + 'r', + 'v', + 'h', + 9, + 0, + /* 8288 */ 'b', + 'x', + 'h', + 9, + 0, + /* 8293 */ 'v', + 'm', + 'x', + 'h', + 9, + 0, + /* 8299 */ 'b', + 'r', + 'x', + 'h', + 9, + 0, + /* 8305 */ 'm', + 'a', + 'y', + 'h', + 9, + 0, + /* 8311 */ 'm', + 'y', + 'h', + 9, + 0, + /* 8316 */ 'v', + 's', + 't', + 'r', + 'c', + 'z', + 'h', + 9, + 0, + /* 8325 */ 'v', + 'f', + 'a', + 'e', + 'z', + 'h', + 9, + 0, + /* 8333 */ 'v', + 'f', + 'e', + 'e', + 'z', + 'h', + 9, + 0, + /* 8341 */ 'v', + 'l', + 'l', + 'e', + 'z', + 'h', + 9, + 0, + /* 8349 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'z', + 'h', + 9, + 0, + /* 8358 */ 'v', + 'c', + 'l', + 'z', + 'h', + 9, + 0, + /* 8365 */ 'v', + 'c', + 't', + 'z', + 'h', + 9, + 0, + /* 8372 */ 'n', + 'i', + 'a', + 'i', + 9, + 0, + /* 8378 */ 'v', + 's', + 'b', + 'c', + 'b', + 'i', + 9, + 0, + /* 8386 */ 'v', + 's', + 'c', + 'b', + 'i', + 9, + 0, + /* 8393 */ 'v', + 's', + 'b', + 'i', + 9, + 0, + /* 8399 */ 'v', + 'f', + 't', + 'c', + 'i', + 9, + 0, + /* 8406 */ 'v', + 'p', + 'd', + 'i', + 9, + 0, + /* 8412 */ 'a', + 'f', + 'i', + 9, + 0, + /* 8417 */ 'c', + 'f', + 'i', + 9, + 0, + /* 8422 */ 'a', + 'g', + 'f', + 'i', + 9, + 0, + /* 8428 */ 'c', + 'g', + 'f', + 'i', + 9, + 0, + /* 8434 */ 'a', + 'l', + 'g', + 'f', + 'i', + 9, + 0, + /* 8441 */ 'c', + 'l', + 'g', + 'f', + 'i', + 9, + 0, + /* 8448 */ 's', + 'l', + 'g', + 'f', + 'i', + 9, + 0, + /* 8455 */ 'm', + 's', + 'g', + 'f', + 'i', + 9, + 0, + /* 8462 */ 'a', + 'l', + 'f', + 'i', + 9, + 0, + /* 8468 */ 'c', + 'l', + 'f', + 'i', + 9, + 0, + /* 8474 */ 's', + 'l', + 'f', + 'i', + 9, + 0, + /* 8480 */ 'm', + 's', + 'f', + 'i', + 9, + 0, + /* 8486 */ 'v', + 'f', + 'i', + 9, + 0, + /* 8491 */ 'a', + 'h', + 'i', + 9, + 0, + /* 8496 */ 'l', + 'o', + 'c', + 'h', + 'i', + 9, + 0, + /* 8503 */ 'a', + 'g', + 'h', + 'i', + 9, + 0, + /* 8509 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 9, + 0, + /* 8517 */ 'l', + 'g', + 'h', + 'i', + 9, + 0, + /* 8523 */ 'm', + 'g', + 'h', + 'i', + 9, + 0, + /* 8529 */ 'm', + 'v', + 'g', + 'h', + 'i', + 9, + 0, + /* 8536 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 9, + 0, + /* 8544 */ 'm', + 'v', + 'h', + 'h', + 'i', + 9, + 0, + /* 8551 */ 'l', + 'h', + 'i', + 9, + 0, + /* 8556 */ 'm', + 'h', + 'i', + 9, + 0, + /* 8561 */ 'm', + 'v', + 'h', + 'i', + 9, + 0, + /* 8567 */ 'c', + 'l', + 'i', + 9, + 0, + /* 8572 */ 'n', + 'i', + 9, + 0, + /* 8576 */ 'o', + 'i', + 9, + 0, + /* 8580 */ 'v', + 'r', + 'e', + 'p', + 'i', + 9, + 0, + /* 8587 */ 't', + 'p', + 'i', + 9, + 0, + /* 8592 */ 'q', + 'c', + 't', + 'r', + 'i', + 9, + 0, + /* 8599 */ 'a', + 's', + 'i', + 9, + 0, + /* 8604 */ 'a', + 'g', + 's', + 'i', + 9, + 0, + /* 8610 */ 'a', + 'l', + 'g', + 's', + 'i', + 9, + 0, + /* 8617 */ 'c', + 'h', + 's', + 'i', + 9, + 0, + /* 8623 */ 'c', + 'l', + 'f', + 'h', + 's', + 'i', + 9, + 0, + /* 8631 */ 'c', + 'g', + 'h', + 's', + 'i', + 9, + 0, + /* 8638 */ 'c', + 'l', + 'g', + 'h', + 's', + 'i', + 9, + 0, + /* 8646 */ 'c', + 'h', + 'h', + 's', + 'i', + 9, + 0, + /* 8653 */ 'c', + 'l', + 'h', + 'h', + 's', + 'i', + 9, + 0, + /* 8661 */ 'a', + 'l', + 's', + 'i', + 9, + 0, + /* 8667 */ 'q', + 's', + 'i', + 9, + 0, + /* 8672 */ 's', + 't', + 's', + 'i', + 9, + 0, + /* 8678 */ 'p', + 't', + 'i', + 9, + 0, + /* 8683 */ 'm', + 'v', + 'i', + 9, + 0, + /* 8688 */ 'x', + 'i', + 9, + 0, + /* 8692 */ 'c', + 'i', + 'j', + 9, + 0, + /* 8697 */ 'c', + 'g', + 'i', + 'j', + 9, + 0, + /* 8703 */ 'c', + 'l', + 'g', + 'i', + 'j', + 9, + 0, + /* 8710 */ 'c', + 'l', + 'i', + 'j', + 9, + 0, + /* 8716 */ 'c', + 'r', + 'j', + 9, + 0, + /* 8721 */ 'c', + 'g', + 'r', + 'j', + 9, + 0, + /* 8727 */ 'c', + 'l', + 'g', + 'r', + 'j', + 9, + 0, + /* 8734 */ 'c', + 'l', + 'r', + 'j', + 9, + 0, + /* 8740 */ 's', + 'l', + 'a', + 'k', + 9, + 0, + /* 8746 */ 's', + 'r', + 'a', + 'k', + 9, + 0, + /* 8752 */ 'p', + 'a', + 'c', + 'k', + 9, + 0, + /* 8758 */ 's', + 'c', + 'k', + 9, + 0, + /* 8763 */ 's', + 't', + 'c', + 'k', + 9, + 0, + /* 8769 */ 'm', + 'v', + 'c', + 'k', + 9, + 0, + /* 8775 */ 'm', + 'v', + 'c', + 'd', + 'k', + 9, + 0, + /* 8782 */ 'w', + 'f', + 'k', + 9, + 0, + /* 8787 */ 'a', + 'h', + 'i', + 'k', + 9, + 0, + /* 8793 */ 'a', + 'g', + 'h', + 'i', + 'k', + 9, + 0, + /* 8800 */ 'a', + 'l', + 'g', + 'h', + 's', + 'i', + 'k', + 9, + 0, + /* 8809 */ 'a', + 'l', + 'h', + 's', + 'i', + 'k', + 9, + 0, + /* 8817 */ 's', + 'l', + 'l', + 'k', + 9, + 0, + /* 8823 */ 's', + 'r', + 'l', + 'k', + 9, + 0, + /* 8829 */ 'e', + 'd', + 'm', + 'k', + 9, + 0, + /* 8835 */ 'u', + 'n', + 'p', + 'k', + 9, + 0, + /* 8841 */ 'v', + 'p', + 'k', + 9, + 0, + /* 8846 */ 'a', + 'r', + 'k', + 9, + 0, + /* 8851 */ 'a', + 'g', + 'r', + 'k', + 9, + 0, + /* 8857 */ 'a', + 'l', + 'g', + 'r', + 'k', + 9, + 0, + /* 8864 */ 's', + 'l', + 'g', + 'r', + 'k', + 9, + 0, + /* 8871 */ 'm', + 'g', + 'r', + 'k', + 9, + 0, + /* 8877 */ 'n', + 'g', + 'r', + 'k', + 9, + 0, + /* 8883 */ 'o', + 'g', + 'r', + 'k', + 9, + 0, + /* 8889 */ 's', + 'g', + 'r', + 'k', + 9, + 0, + /* 8895 */ 'x', + 'g', + 'r', + 'k', + 9, + 0, + /* 8901 */ 'a', + 'l', + 'r', + 'k', + 9, + 0, + /* 8907 */ 's', + 'l', + 'r', + 'k', + 9, + 0, + /* 8913 */ 'n', + 'r', + 'k', + 9, + 0, + /* 8918 */ 'o', + 'r', + 'k', + 9, + 0, + /* 8923 */ 's', + 'r', + 'k', + 9, + 0, + /* 8928 */ 'x', + 'r', + 'k', + 9, + 0, + /* 8933 */ 'm', + 'v', + 'c', + 's', + 'k', + 9, + 0, + /* 8940 */ 'i', + 'v', + 's', + 'k', + 9, + 0, + /* 8946 */ 'l', + 'a', + 'a', + 'l', + 9, + 0, + /* 8952 */ 'b', + 'a', + 'l', + 9, + 0, + /* 8957 */ 'v', + 'm', + 'a', + 'l', + 9, + 0, + /* 8963 */ 'c', + 'i', + 'b', + 'l', + 9, + 0, + /* 8969 */ 'c', + 'g', + 'i', + 'b', + 'l', + 9, + 0, + /* 8976 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'l', + 9, + 0, + /* 8984 */ 'c', + 'l', + 'i', + 'b', + 'l', + 9, + 0, + /* 8991 */ 'c', + 'r', + 'b', + 'l', + 9, + 0, + /* 8997 */ 'c', + 'g', + 'r', + 'b', + 'l', + 9, + 0, + /* 9004 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'l', + 9, + 0, + /* 9012 */ 'c', + 'l', + 'r', + 'b', + 'l', + 9, + 0, + /* 9019 */ 'v', + 'e', + 'c', + 'l', + 9, + 0, + /* 9025 */ 'c', + 'l', + 'c', + 'l', + 9, + 0, + /* 9031 */ 'l', + 'o', + 'c', + 'l', + 9, + 0, + /* 9037 */ 's', + 't', + 'o', + 'c', + 'l', + 9, + 0, + /* 9044 */ 'b', + 'r', + 'c', + 'l', + 9, + 0, + /* 9050 */ 'm', + 'v', + 'c', + 'l', + 9, + 0, + /* 9056 */ 's', + 'l', + 'd', + 'l', + 9, + 0, + /* 9062 */ 's', + 'r', + 'd', + 'l', + 9, + 0, + /* 9068 */ 'v', + 's', + 'e', + 'l', + 9, + 0, + /* 9074 */ 's', + 't', + 'f', + 'l', + 9, + 0, + /* 9080 */ 'l', + 'o', + 'c', + 'g', + 'l', + 9, + 0, + /* 9087 */ 's', + 't', + 'o', + 'c', + 'g', + 'l', + 9, + 0, + /* 9095 */ 'j', + 'g', + 'l', + 9, + 0, + /* 9100 */ 'v', + 'a', + 'v', + 'g', + 'l', + 9, + 0, + /* 9107 */ 'v', + 'c', + 'h', + 'l', + 9, + 0, + /* 9113 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'l', + 9, + 0, + /* 9121 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'l', + 9, + 0, + /* 9130 */ 'i', + 'i', + 'h', + 'l', + 9, + 0, + /* 9136 */ 'l', + 'l', + 'i', + 'h', + 'l', + 9, + 0, + /* 9143 */ 'n', + 'i', + 'h', + 'l', + 9, + 0, + /* 9149 */ 'o', + 'i', + 'h', + 'l', + 9, + 0, + /* 9155 */ 't', + 'm', + 'h', + 'l', + 9, + 0, + /* 9161 */ 'b', + 'i', + 'l', + 9, + 0, + /* 9166 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'l', + 9, + 0, + /* 9174 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'l', + 9, + 0, + /* 9183 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'l', + 9, + 0, + /* 9192 */ 'c', + 'i', + 'j', + 'l', + 9, + 0, + /* 9198 */ 'c', + 'g', + 'i', + 'j', + 'l', + 9, + 0, + /* 9205 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'l', + 9, + 0, + /* 9213 */ 'c', + 'l', + 'i', + 'j', + 'l', + 9, + 0, + /* 9220 */ 'c', + 'r', + 'j', + 'l', + 9, + 0, + /* 9226 */ 'c', + 'g', + 'r', + 'j', + 'l', + 9, + 0, + /* 9233 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'l', + 9, + 0, + /* 9241 */ 'c', + 'l', + 'r', + 'j', + 'l', + 9, + 0, + /* 9248 */ 'v', + 'f', + 'l', + 'l', + 9, + 0, + /* 9254 */ 'i', + 'i', + 'l', + 'l', + 9, + 0, + /* 9260 */ 'l', + 'l', + 'i', + 'l', + 'l', + 9, + 0, + /* 9267 */ 'n', + 'i', + 'l', + 'l', + 9, + 0, + /* 9273 */ 'o', + 'i', + 'l', + 'l', + 9, + 0, + /* 9279 */ 't', + 'm', + 'l', + 'l', + 9, + 0, + /* 9285 */ 'v', + 'u', + 'p', + 'l', + 'l', + 9, + 0, + /* 9292 */ 'v', + 'e', + 'r', + 'l', + 'l', + 9, + 0, + /* 9299 */ 's', + 'l', + 'l', + 9, + 0, + /* 9304 */ 'v', + 'l', + 'l', + 9, + 0, + /* 9309 */ 'v', + 'm', + 'l', + 9, + 0, + /* 9314 */ 'c', + 'i', + 'b', + 'n', + 'l', + 9, + 0, + /* 9321 */ 'c', + 'g', + 'i', + 'b', + 'n', + 'l', + 9, + 0, + /* 9329 */ 'c', + 'l', + 'g', + 'i', + 'b', + 'n', + 'l', + 9, + 0, + /* 9338 */ 'c', + 'l', + 'i', + 'b', + 'n', + 'l', + 9, + 0, + /* 9346 */ 'c', + 'r', + 'b', + 'n', + 'l', + 9, + 0, + /* 9353 */ 'c', + 'g', + 'r', + 'b', + 'n', + 'l', + 9, + 0, + /* 9361 */ 'c', + 'l', + 'g', + 'r', + 'b', + 'n', + 'l', + 9, + 0, + /* 9370 */ 'c', + 'l', + 'r', + 'b', + 'n', + 'l', + 9, + 0, + /* 9378 */ 'l', + 'o', + 'c', + 'n', + 'l', + 9, + 0, + /* 9385 */ 's', + 't', + 'o', + 'c', + 'n', + 'l', + 9, + 0, + /* 9393 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'l', + 9, + 0, + /* 9401 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'l', + 9, + 0, + /* 9410 */ 'j', + 'g', + 'n', + 'l', + 9, + 0, + /* 9416 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'l', + 9, + 0, + /* 9425 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'l', + 9, + 0, + /* 9435 */ 'b', + 'i', + 'n', + 'l', + 9, + 0, + /* 9441 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'l', + 9, + 0, + /* 9450 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'l', + 9, + 0, + /* 9460 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'l', + 9, + 0, + /* 9470 */ 'c', + 'i', + 'j', + 'n', + 'l', + 9, + 0, + /* 9477 */ 'c', + 'g', + 'i', + 'j', + 'n', + 'l', + 9, + 0, + /* 9485 */ 'c', + 'l', + 'g', + 'i', + 'j', + 'n', + 'l', + 9, + 0, + /* 9494 */ 'c', + 'l', + 'i', + 'j', + 'n', + 'l', + 9, + 0, + /* 9502 */ 'c', + 'r', + 'j', + 'n', + 'l', + 9, + 0, + /* 9509 */ 'c', + 'g', + 'r', + 'j', + 'n', + 'l', + 9, + 0, + /* 9517 */ 'c', + 'l', + 'g', + 'r', + 'j', + 'n', + 'l', + 9, + 0, + /* 9526 */ 'c', + 'l', + 'r', + 'j', + 'n', + 'l', + 9, + 0, + /* 9534 */ 'v', + 'm', + 'n', + 'l', + 9, + 0, + /* 9540 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'l', + 9, + 0, + /* 9548 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'l', + 9, + 0, + /* 9557 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'l', + 9, + 0, + /* 9567 */ 'c', + 'l', + 'g', + 't', + 'n', + 'l', + 9, + 0, + /* 9575 */ 'c', + 'i', + 't', + 'n', + 'l', + 9, + 0, + /* 9582 */ 'c', + 'l', + 'f', + 'i', + 't', + 'n', + 'l', + 9, + 0, + /* 9591 */ 'c', + 'g', + 'i', + 't', + 'n', + 'l', + 9, + 0, + /* 9599 */ 'c', + 'l', + 'g', + 'i', + 't', + 'n', + 'l', + 9, + 0, + /* 9608 */ 'c', + 'l', + 't', + 'n', + 'l', + 9, + 0, + /* 9615 */ 'c', + 'r', + 't', + 'n', + 'l', + 9, + 0, + /* 9622 */ 'c', + 'g', + 'r', + 't', + 'n', + 'l', + 9, + 0, + /* 9630 */ 'c', + 'l', + 'g', + 'r', + 't', + 'n', + 'l', + 9, + 0, + /* 9639 */ 'c', + 'l', + 'r', + 't', + 'n', + 'l', + 9, + 0, + /* 9647 */ 'v', + 'u', + 'p', + 'l', + 9, + 0, + /* 9653 */ 'l', + 'a', + 'r', + 'l', + 9, + 0, + /* 9659 */ 'l', + 'o', + 'c', + 'r', + 'l', + 9, + 0, + /* 9666 */ 'p', + 'f', + 'd', + 'r', + 'l', + 9, + 0, + /* 9673 */ 'c', + 'g', + 'f', + 'r', + 'l', + 9, + 0, + /* 9680 */ 'c', + 'l', + 'g', + 'f', + 'r', + 'l', + 9, + 0, + /* 9688 */ 'l', + 'l', + 'g', + 'f', + 'r', + 'l', + 9, + 0, + /* 9696 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'l', + 9, + 0, + /* 9704 */ 'c', + 'l', + 'g', + 'r', + 'l', + 9, + 0, + /* 9711 */ 's', + 't', + 'g', + 'r', + 'l', + 9, + 0, + /* 9718 */ 'c', + 'h', + 'r', + 'l', + 9, + 0, + /* 9724 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'l', + 9, + 0, + /* 9733 */ 'c', + 'g', + 'h', + 'r', + 'l', + 9, + 0, + /* 9740 */ 'c', + 'l', + 'g', + 'h', + 'r', + 'l', + 9, + 0, + /* 9748 */ 'l', + 'l', + 'g', + 'h', + 'r', + 'l', + 9, + 0, + /* 9756 */ 'c', + 'l', + 'h', + 'r', + 'l', + 9, + 0, + /* 9763 */ 'l', + 'l', + 'h', + 'r', + 'l', + 9, + 0, + /* 9770 */ 's', + 't', + 'h', + 'r', + 'l', + 9, + 0, + /* 9777 */ 'c', + 'l', + 'r', + 'l', + 9, + 0, + /* 9783 */ 'v', + 'l', + 'r', + 'l', + 9, + 0, + /* 9789 */ 'v', + 'm', + 'r', + 'l', + 9, + 0, + /* 9795 */ 'v', + 'e', + 's', + 'r', + 'l', + 9, + 0, + /* 9802 */ 'v', + 's', + 'r', + 'l', + 9, + 0, + /* 9808 */ 'v', + 's', + 't', + 'r', + 'l', + 9, + 0, + /* 9815 */ 'e', + 'x', + 'r', + 'l', + 9, + 0, + /* 9821 */ 'b', + 'r', + 'a', + 's', + 'l', + 9, + 0, + /* 9828 */ 'v', + 'e', + 's', + 'l', + 9, + 0, + /* 9834 */ 'v', + 'm', + 's', + 'l', + 9, + 0, + /* 9840 */ 'v', + 's', + 'l', + 9, + 0, + /* 9845 */ 'l', + 'c', + 'c', + 't', + 'l', + 9, + 0, + /* 9852 */ 'l', + 'c', + 't', + 'l', + 9, + 0, + /* 9858 */ 'l', + 'p', + 'c', + 't', + 'l', + 9, + 0, + /* 9865 */ 'l', + 's', + 'c', + 't', + 'l', + 9, + 0, + /* 9872 */ 's', + 't', + 'c', + 't', + 'l', + 9, + 0, + /* 9879 */ 'c', + 'l', + 'g', + 't', + 'l', + 9, + 0, + /* 9886 */ 'c', + 'i', + 't', + 'l', + 9, + 0, + /* 9892 */ 'c', + 'l', + 'f', + 'i', + 't', + 'l', + 9, + 0, + /* 9900 */ 'c', + 'g', + 'i', + 't', + 'l', + 9, + 0, + /* 9907 */ 'c', + 'l', + 'g', + 'i', + 't', + 'l', + 9, + 0, + /* 9915 */ 'c', + 'l', + 't', + 'l', + 9, + 0, + /* 9921 */ 'c', + 'r', + 't', + 'l', + 9, + 0, + /* 9927 */ 'c', + 'g', + 'r', + 't', + 'l', + 9, + 0, + /* 9934 */ 'c', + 'l', + 'g', + 'r', + 't', + 'l', + 9, + 0, + /* 9942 */ 'c', + 'l', + 'r', + 't', + 'l', + 9, + 0, + /* 9949 */ 'v', + 's', + 't', + 'l', + 9, + 0, + /* 9955 */ 'v', + 'l', + 9, + 0, + /* 9959 */ 'v', + 'm', + 'x', + 'l', + 9, + 0, + /* 9965 */ 'm', + 'a', + 'y', + 'l', + 9, + 0, + /* 9971 */ 'm', + 'y', + 'l', + 9, + 0, + /* 9976 */ 'l', + 'a', + 'm', + 9, + 0, + /* 9981 */ 's', + 't', + 'a', + 'm', + 9, + 0, + /* 9987 */ 'v', + 'g', + 'b', + 'm', + 9, + 0, + /* 9993 */ 'i', + 'r', + 'b', + 'm', + 9, + 0, + /* 9999 */ 'r', + 'r', + 'b', + 'm', + 9, + 0, + /* 10005 */ 'i', + 'c', + 'm', + 9, + 0, + /* 10010 */ 'l', + 'o', + 'c', + 'm', + 9, + 0, + /* 10016 */ 's', + 't', + 'o', + 'c', + 'm', + 9, + 0, + /* 10023 */ 's', + 't', + 'c', + 'm', + 9, + 0, + /* 10029 */ 'v', + 'g', + 'f', + 'm', + 9, + 0, + /* 10035 */ 'v', + 'f', + 'm', + 9, + 0, + /* 10040 */ 'l', + 'o', + 'c', + 'g', + 'm', + 9, + 0, + /* 10047 */ 's', + 't', + 'o', + 'c', + 'g', + 'm', + 9, + 0, + /* 10055 */ 'j', + 'g', + 'm', + 9, + 0, + /* 10060 */ 'v', + 'g', + 'm', + 9, + 0, + /* 10065 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'm', + 9, + 0, + /* 10073 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'm', + 9, + 0, + /* 10082 */ 'b', + 'i', + 'm', + 9, + 0, + /* 10087 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'm', + 9, + 0, + /* 10095 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'm', + 9, + 0, + /* 10104 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'm', + 9, + 0, + /* 10113 */ 'v', + 'e', + 'r', + 'i', + 'm', + 9, + 0, + /* 10120 */ 'j', + 'm', + 9, + 0, + /* 10124 */ 'k', + 'm', + 9, + 0, + /* 10128 */ 'c', + 'l', + 'm', + 9, + 0, + /* 10133 */ 'v', + 'l', + 'm', + 9, + 0, + /* 10138 */ 'b', + 'n', + 'm', + 9, + 0, + /* 10143 */ 'l', + 'o', + 'c', + 'n', + 'm', + 9, + 0, + /* 10150 */ 's', + 't', + 'o', + 'c', + 'n', + 'm', + 9, + 0, + /* 10158 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'm', + 9, + 0, + /* 10166 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'm', + 9, + 0, + /* 10175 */ 'j', + 'g', + 'n', + 'm', + 9, + 0, + /* 10181 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'm', + 9, + 0, + /* 10190 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'm', + 9, + 0, + /* 10200 */ 'b', + 'i', + 'n', + 'm', + 9, + 0, + /* 10206 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'm', + 9, + 0, + /* 10215 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'm', + 9, + 0, + /* 10225 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'm', + 9, + 0, + /* 10235 */ 'j', + 'n', + 'm', + 9, + 0, + /* 10240 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'm', + 9, + 0, + /* 10248 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'm', + 9, + 0, + /* 10257 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'm', + 9, + 0, + /* 10267 */ 's', + 'r', + 'n', + 'm', + 9, + 0, + /* 10273 */ 'i', + 'p', + 'm', + 9, + 0, + /* 10278 */ 's', + 'p', + 'm', + 9, + 0, + /* 10283 */ 'l', + 'o', + 'c', + 'r', + 'm', + 9, + 0, + /* 10290 */ 'v', + 'b', + 'p', + 'e', + 'r', + 'm', + 9, + 0, + /* 10298 */ 'v', + 'p', + 'e', + 'r', + 'm', + 9, + 0, + /* 10305 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'm', + 9, + 0, + /* 10313 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'm', + 9, + 0, + /* 10322 */ 'b', + 's', + 'm', + 9, + 0, + /* 10327 */ 'v', + 'c', + 'k', + 's', + 'm', + 9, + 0, + /* 10334 */ 's', + 't', + 'n', + 's', + 'm', + 9, + 0, + /* 10341 */ 's', + 't', + 'o', + 's', + 'm', + 9, + 0, + /* 10348 */ 'b', + 'a', + 's', + 's', + 'm', + 9, + 0, + /* 10355 */ 'v', + 's', + 't', + 'm', + 9, + 0, + /* 10361 */ 'v', + 't', + 'm', + 9, + 0, + /* 10366 */ 'v', + 's', + 'u', + 'm', + 9, + 0, + /* 10372 */ 'l', + 'a', + 'n', + 9, + 0, + /* 10377 */ 'r', + 'i', + 's', + 'b', + 'g', + 'n', + 9, + 0, + /* 10385 */ 'a', + 'l', + 's', + 'i', + 'h', + 'n', + 9, + 0, + /* 10393 */ 'm', + 'v', + 'c', + 'i', + 'n', + 9, + 0, + /* 10400 */ 't', + 'b', + 'e', + 'g', + 'i', + 'n', + 9, + 0, + /* 10408 */ 'p', + 'g', + 'i', + 'n', + 9, + 0, + /* 10414 */ 'v', + 'f', + 'm', + 'i', + 'n', + 9, + 0, + /* 10421 */ 'v', + 'm', + 'n', + 9, + 0, + /* 10426 */ 'v', + 'n', + 'n', + 9, + 0, + /* 10431 */ 'm', + 'v', + 'n', + 9, + 0, + /* 10436 */ 'l', + 'a', + 'o', + 9, + 0, + /* 10441 */ 'v', + 'm', + 'a', + 'o', + 9, + 0, + /* 10447 */ 'b', + 'o', + 9, + 0, + /* 10451 */ 'l', + 'o', + 'c', + 'o', + 9, + 0, + /* 10457 */ 's', + 't', + 'o', + 'c', + 'o', + 9, + 0, + /* 10464 */ 'l', + 'o', + 'c', + 'g', + 'o', + 9, + 0, + /* 10471 */ 's', + 't', + 'o', + 'c', + 'g', + 'o', + 9, + 0, + /* 10479 */ 'j', + 'g', + 'o', + 9, + 0, + /* 10484 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'o', + 9, + 0, + /* 10492 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'o', + 9, + 0, + /* 10501 */ 'b', + 'i', + 'o', + 9, + 0, + /* 10506 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'o', + 9, + 0, + /* 10514 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'o', + 9, + 0, + /* 10523 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'o', + 9, + 0, + /* 10532 */ 'j', + 'o', + 9, + 0, + /* 10536 */ 'v', + 'm', + 'a', + 'l', + 'o', + 9, + 0, + /* 10543 */ 'v', + 'm', + 'l', + 'o', + 9, + 0, + /* 10549 */ 'p', + 'l', + 'o', + 9, + 0, + /* 10554 */ 'k', + 'm', + 'o', + 9, + 0, + /* 10559 */ 'v', + 'm', + 'o', + 9, + 0, + /* 10564 */ 'b', + 'n', + 'o', + 9, + 0, + /* 10569 */ 'l', + 'o', + 'c', + 'n', + 'o', + 9, + 0, + /* 10576 */ 's', + 't', + 'o', + 'c', + 'n', + 'o', + 9, + 0, + /* 10584 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'o', + 9, + 0, + /* 10592 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'o', + 9, + 0, + /* 10601 */ 'j', + 'g', + 'n', + 'o', + 9, + 0, + /* 10607 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'o', + 9, + 0, + /* 10616 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'o', + 9, + 0, + /* 10626 */ 'b', + 'i', + 'n', + 'o', + 9, + 0, + /* 10632 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'o', + 9, + 0, + /* 10641 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'o', + 9, + 0, + /* 10651 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'o', + 9, + 0, + /* 10661 */ 'j', + 'n', + 'o', + 9, + 0, + /* 10666 */ 'p', + 'p', + 'n', + 'o', + 9, + 0, + /* 10672 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'o', + 9, + 0, + /* 10680 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'o', + 9, + 0, + /* 10689 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'o', + 9, + 0, + /* 10699 */ 'p', + 'r', + 'n', + 'o', + 9, + 0, + /* 10705 */ 'v', + 'n', + 'o', + 9, + 0, + /* 10710 */ 't', + 'r', + 'o', + 'o', + 9, + 0, + /* 10716 */ 'l', + 'o', + 'c', + 'r', + 'o', + 9, + 0, + /* 10723 */ 'v', + 'z', + 'e', + 'r', + 'o', + 9, + 0, + /* 10730 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'o', + 9, + 0, + /* 10738 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'o', + 9, + 0, + /* 10747 */ 'v', + 'f', + 'p', + 's', + 'o', + 9, + 0, + /* 10754 */ 't', + 'r', + 't', + 'o', + 9, + 0, + /* 10760 */ 'm', + 'v', + 'o', + 9, + 0, + /* 10765 */ 's', + 't', + 'a', + 'p', + 9, + 0, + /* 10771 */ 'v', + 'a', + 'p', + 9, + 0, + /* 10776 */ 'z', + 'a', + 'p', + 9, + 0, + /* 10781 */ 'b', + 'p', + 9, + 0, + /* 10785 */ 'l', + 'o', + 'c', + 'p', + 9, + 0, + /* 10791 */ 's', + 't', + 'o', + 'c', + 'p', + 9, + 0, + /* 10798 */ 'm', + 'v', + 'c', + 'p', + 9, + 0, + /* 10804 */ 's', + 't', + 'i', + 'd', + 'p', + 9, + 0, + /* 10811 */ 'v', + 's', + 'd', + 'p', + 9, + 0, + /* 10817 */ 'v', + 'd', + 'p', + 9, + 0, + /* 10822 */ 'v', + 'l', + 'r', + 'e', + 'p', + 9, + 0, + /* 10829 */ 'v', + 'r', + 'e', + 'p', + 9, + 0, + /* 10835 */ 'l', + 'o', + 'c', + 'g', + 'p', + 9, + 0, + /* 10842 */ 's', + 't', + 'o', + 'c', + 'g', + 'p', + 9, + 0, + /* 10850 */ 's', + 'i', + 'g', + 'p', + 9, + 0, + /* 10856 */ 'j', + 'g', + 'p', + 9, + 0, + /* 10861 */ 'v', + 'l', + 'v', + 'g', + 'p', + 9, + 0, + /* 10868 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'p', + 9, + 0, + /* 10876 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'p', + 9, + 0, + /* 10885 */ 'b', + 'i', + 'p', + 9, + 0, + /* 10890 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'p', + 9, + 0, + /* 10898 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'p', + 9, + 0, + /* 10907 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'p', + 9, + 0, + /* 10916 */ 'v', + 'l', + 'i', + 'p', + 9, + 0, + /* 10922 */ 'j', + 'p', + 9, + 0, + /* 10926 */ 'v', + 'l', + 'p', + 9, + 0, + /* 10931 */ 'v', + 'm', + 'p', + 9, + 0, + /* 10936 */ 'b', + 'n', + 'p', + 9, + 0, + /* 10941 */ 'l', + 'o', + 'c', + 'n', + 'p', + 9, + 0, + /* 10948 */ 's', + 't', + 'o', + 'c', + 'n', + 'p', + 9, + 0, + /* 10956 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'p', + 9, + 0, + /* 10964 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'p', + 9, + 0, + /* 10973 */ 'j', + 'g', + 'n', + 'p', + 9, + 0, + /* 10979 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'p', + 9, + 0, + /* 10988 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'p', + 9, + 0, + /* 10998 */ 'b', + 'i', + 'n', + 'p', + 9, + 0, + /* 11004 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'p', + 9, + 0, + /* 11013 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'p', + 9, + 0, + /* 11023 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'p', + 9, + 0, + /* 11033 */ 'j', + 'n', + 'p', + 9, + 0, + /* 11038 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'p', + 9, + 0, + /* 11046 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'p', + 9, + 0, + /* 11055 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'p', + 9, + 0, + /* 11065 */ 'v', + 'p', + 's', + 'o', + 'p', + 9, + 0, + /* 11072 */ 'b', + 'p', + 'p', + 9, + 0, + /* 11077 */ 'l', + 'p', + 'p', + 9, + 0, + /* 11082 */ 'l', + 'o', + 'c', + 'r', + 'p', + 9, + 0, + /* 11089 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'p', + 9, + 0, + /* 11097 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'p', + 9, + 0, + /* 11106 */ 'b', + 'p', + 'r', + 'p', + 9, + 0, + /* 11112 */ 'v', + 's', + 'r', + 'p', + 9, + 0, + /* 11118 */ 'v', + 'r', + 'p', + 9, + 0, + /* 11123 */ 'l', + 'a', + 's', + 'p', + 9, + 0, + /* 11129 */ 'c', + 's', + 'p', + 9, + 0, + /* 11134 */ 'v', + 'm', + 's', + 'p', + 9, + 0, + /* 11140 */ 'v', + 's', + 'p', + 9, + 0, + /* 11145 */ 'v', + 't', + 'p', + 9, + 0, + /* 11150 */ 'v', + 'a', + 'q', + 9, + 0, + /* 11155 */ 'v', + 'a', + 'c', + 'q', + 9, + 0, + /* 11161 */ 'v', + 'a', + 'c', + 'c', + 'q', + 9, + 0, + /* 11168 */ 'v', + 'a', + 'c', + 'c', + 'c', + 'q', + 9, + 0, + /* 11176 */ 'v', + 'c', + 'e', + 'q', + 9, + 0, + /* 11182 */ 'v', + 's', + 'b', + 'c', + 'b', + 'i', + 'q', + 9, + 0, + /* 11191 */ 'v', + 's', + 'c', + 'b', + 'i', + 'q', + 9, + 0, + /* 11199 */ 'v', + 's', + 'b', + 'i', + 'q', + 9, + 0, + /* 11206 */ 'v', + 's', + 'u', + 'm', + 'q', + 9, + 0, + /* 11213 */ 'l', + 'p', + 'q', + 9, + 0, + /* 11218 */ 's', + 't', + 'p', + 'q', + 9, + 0, + /* 11224 */ 'v', + 'f', + 's', + 'q', + 9, + 0, + /* 11230 */ 'v', + 's', + 'q', + 9, + 0, + /* 11235 */ 'e', + 'a', + 'r', + 9, + 0, + /* 11240 */ 'e', + 'p', + 'a', + 'r', + 9, + 0, + /* 11246 */ 'e', + 's', + 'a', + 'r', + 9, + 0, + /* 11252 */ 's', + 's', + 'a', + 'r', + 9, + 0, + /* 11258 */ 't', + 'a', + 'r', + 9, + 0, + /* 11263 */ 'm', + 'a', + 'd', + 'b', + 'r', + 9, + 0, + /* 11270 */ 'l', + 'c', + 'd', + 'b', + 'r', + 9, + 0, + /* 11277 */ 'd', + 'd', + 'b', + 'r', + 9, + 0, + /* 11283 */ 'l', + 'e', + 'd', + 'b', + 'r', + 9, + 0, + /* 11290 */ 'c', + 'f', + 'd', + 'b', + 'r', + 9, + 0, + /* 11297 */ 'c', + 'l', + 'f', + 'd', + 'b', + 'r', + 9, + 0, + /* 11305 */ 'c', + 'g', + 'd', + 'b', + 'r', + 9, + 0, + /* 11312 */ 'c', + 'l', + 'g', + 'd', + 'b', + 'r', + 9, + 0, + /* 11320 */ 'd', + 'i', + 'd', + 'b', + 'r', + 9, + 0, + /* 11327 */ 'f', + 'i', + 'd', + 'b', + 'r', + 9, + 0, + /* 11334 */ 'k', + 'd', + 'b', + 'r', + 9, + 0, + /* 11340 */ 'm', + 'd', + 'b', + 'r', + 9, + 0, + /* 11346 */ 'l', + 'n', + 'd', + 'b', + 'r', + 9, + 0, + /* 11353 */ 'l', + 'p', + 'd', + 'b', + 'r', + 9, + 0, + /* 11360 */ 's', + 'q', + 'd', + 'b', + 'r', + 9, + 0, + /* 11367 */ 'm', + 's', + 'd', + 'b', + 'r', + 9, + 0, + /* 11374 */ 'l', + 't', + 'd', + 'b', + 'r', + 9, + 0, + /* 11381 */ 'l', + 'x', + 'd', + 'b', + 'r', + 9, + 0, + /* 11388 */ 'm', + 'x', + 'd', + 'b', + 'r', + 9, + 0, + /* 11395 */ 'm', + 'a', + 'e', + 'b', + 'r', + 9, + 0, + /* 11402 */ 'l', + 'c', + 'e', + 'b', + 'r', + 9, + 0, + /* 11409 */ 'l', + 'd', + 'e', + 'b', + 'r', + 9, + 0, + /* 11416 */ 'm', + 'd', + 'e', + 'b', + 'r', + 9, + 0, + /* 11423 */ 'm', + 'e', + 'e', + 'b', + 'r', + 9, + 0, + /* 11430 */ 'c', + 'f', + 'e', + 'b', + 'r', + 9, + 0, + /* 11437 */ 'c', + 'l', + 'f', + 'e', + 'b', + 'r', + 9, + 0, + /* 11445 */ 'c', + 'g', + 'e', + 'b', + 'r', + 9, + 0, + /* 11452 */ 'c', + 'l', + 'g', + 'e', + 'b', + 'r', + 9, + 0, + /* 11460 */ 'd', + 'i', + 'e', + 'b', + 'r', + 9, + 0, + /* 11467 */ 'f', + 'i', + 'e', + 'b', + 'r', + 9, + 0, + /* 11474 */ 'k', + 'e', + 'b', + 'r', + 9, + 0, + /* 11480 */ 'l', + 'n', + 'e', + 'b', + 'r', + 9, + 0, + /* 11487 */ 'l', + 'p', + 'e', + 'b', + 'r', + 9, + 0, + /* 11494 */ 's', + 'q', + 'e', + 'b', + 'r', + 9, + 0, + /* 11501 */ 'm', + 's', + 'e', + 'b', + 'r', + 9, + 0, + /* 11508 */ 'l', + 't', + 'e', + 'b', + 'r', + 9, + 0, + /* 11515 */ 'l', + 'x', + 'e', + 'b', + 'r', + 9, + 0, + /* 11522 */ 'c', + 'd', + 'f', + 'b', + 'r', + 9, + 0, + /* 11529 */ 'c', + 'e', + 'f', + 'b', + 'r', + 9, + 0, + /* 11536 */ 'c', + 'd', + 'l', + 'f', + 'b', + 'r', + 9, + 0, + /* 11544 */ 'c', + 'e', + 'l', + 'f', + 'b', + 'r', + 9, + 0, + /* 11552 */ 'c', + 'x', + 'l', + 'f', + 'b', + 'r', + 9, + 0, + /* 11560 */ 'c', + 'x', + 'f', + 'b', + 'r', + 9, + 0, + /* 11567 */ 'c', + 'd', + 'g', + 'b', + 'r', + 9, + 0, + /* 11574 */ 'c', + 'e', + 'g', + 'b', + 'r', + 9, + 0, + /* 11581 */ 'c', + 'd', + 'l', + 'g', + 'b', + 'r', + 9, + 0, + /* 11589 */ 'c', + 'e', + 'l', + 'g', + 'b', + 'r', + 9, + 0, + /* 11597 */ 'c', + 'x', + 'l', + 'g', + 'b', + 'r', + 9, + 0, + /* 11605 */ 'c', + 'x', + 'g', + 'b', + 'r', + 9, + 0, + /* 11612 */ 's', + 'l', + 'b', + 'r', + 9, + 0, + /* 11618 */ 'a', + 'x', + 'b', + 'r', + 9, + 0, + /* 11624 */ 'l', + 'c', + 'x', + 'b', + 'r', + 9, + 0, + /* 11631 */ 'l', + 'd', + 'x', + 'b', + 'r', + 9, + 0, + /* 11638 */ 'l', + 'e', + 'x', + 'b', + 'r', + 9, + 0, + /* 11645 */ 'c', + 'f', + 'x', + 'b', + 'r', + 9, + 0, + /* 11652 */ 'c', + 'l', + 'f', + 'x', + 'b', + 'r', + 9, + 0, + /* 11660 */ 'c', + 'g', + 'x', + 'b', + 'r', + 9, + 0, + /* 11667 */ 'c', + 'l', + 'g', + 'x', + 'b', + 'r', + 9, + 0, + /* 11675 */ 'f', + 'i', + 'x', + 'b', + 'r', + 9, + 0, + /* 11682 */ 'k', + 'x', + 'b', + 'r', + 9, + 0, + /* 11688 */ 'm', + 'x', + 'b', + 'r', + 9, + 0, + /* 11694 */ 'l', + 'n', + 'x', + 'b', + 'r', + 9, + 0, + /* 11701 */ 'l', + 'p', + 'x', + 'b', + 'r', + 9, + 0, + /* 11708 */ 's', + 'q', + 'x', + 'b', + 'r', + 9, + 0, + /* 11715 */ 's', + 'x', + 'b', + 'r', + 9, + 0, + /* 11721 */ 'l', + 't', + 'x', + 'b', + 'r', + 9, + 0, + /* 11728 */ 'b', + 'c', + 'r', + 9, + 0, + /* 11733 */ 'l', + 'l', + 'g', + 'c', + 'r', + 9, + 0, + /* 11740 */ 'a', + 'l', + 'c', + 'r', + 9, + 0, + /* 11746 */ 'l', + 'l', + 'c', + 'r', + 9, + 0, + /* 11752 */ 'l', + 'o', + 'c', + 'r', + 9, + 0, + /* 11758 */ 'm', + 'a', + 'd', + 'r', + 9, + 0, + /* 11764 */ 't', + 'b', + 'd', + 'r', + 9, + 0, + /* 11770 */ 'l', + 'c', + 'd', + 'r', + 9, + 0, + /* 11776 */ 'd', + 'd', + 'r', + 9, + 0, + /* 11781 */ 't', + 'b', + 'e', + 'd', + 'r', + 9, + 0, + /* 11788 */ 'l', + 'e', + 'd', + 'r', + 9, + 0, + /* 11794 */ 'c', + 'f', + 'd', + 'r', + 9, + 0, + /* 11800 */ 'c', + 'g', + 'd', + 'r', + 9, + 0, + /* 11806 */ 'l', + 'g', + 'd', + 'r', + 9, + 0, + /* 11812 */ 't', + 'h', + 'd', + 'r', + 9, + 0, + /* 11818 */ 'f', + 'i', + 'd', + 'r', + 9, + 0, + /* 11824 */ 'l', + 'd', + 'r', + 9, + 0, + /* 11829 */ 'm', + 'd', + 'r', + 9, + 0, + /* 11834 */ 'l', + 'n', + 'd', + 'r', + 9, + 0, + /* 11840 */ 'l', + 'p', + 'd', + 'r', + 9, + 0, + /* 11846 */ 's', + 'q', + 'd', + 'r', + 9, + 0, + /* 11852 */ 'l', + 'r', + 'd', + 'r', + 9, + 0, + /* 11858 */ 'm', + 's', + 'd', + 'r', + 9, + 0, + /* 11864 */ 'c', + 'p', + 's', + 'd', + 'r', + 9, + 0, + /* 11871 */ 'l', + 't', + 'd', + 'r', + 9, + 0, + /* 11877 */ 'l', + 'x', + 'd', + 'r', + 9, + 0, + /* 11883 */ 'm', + 'x', + 'd', + 'r', + 9, + 0, + /* 11889 */ 'l', + 'z', + 'd', + 'r', + 9, + 0, + /* 11895 */ 'm', + 'a', + 'e', + 'r', + 9, + 0, + /* 11901 */ 'b', + 'e', + 'r', + 9, + 0, + /* 11906 */ 'l', + 'c', + 'e', + 'r', + 9, + 0, + /* 11912 */ 't', + 'h', + 'd', + 'e', + 'r', + 9, + 0, + /* 11919 */ 'l', + 'd', + 'e', + 'r', + 9, + 0, + /* 11925 */ 'm', + 'd', + 'e', + 'r', + 9, + 0, + /* 11931 */ 'm', + 'e', + 'e', + 'r', + 9, + 0, + /* 11937 */ 'c', + 'f', + 'e', + 'r', + 9, + 0, + /* 11943 */ 'c', + 'g', + 'e', + 'r', + 9, + 0, + /* 11949 */ 'b', + 'h', + 'e', + 'r', + 9, + 0, + /* 11955 */ 'b', + 'n', + 'h', + 'e', + 'r', + 9, + 0, + /* 11962 */ 'f', + 'i', + 'e', + 'r', + 9, + 0, + /* 11968 */ 'b', + 'l', + 'e', + 'r', + 9, + 0, + /* 11974 */ 'b', + 'n', + 'l', + 'e', + 'r', + 9, + 0, + /* 11981 */ 'm', + 'e', + 'r', + 9, + 0, + /* 11986 */ 'b', + 'n', + 'e', + 'r', + 9, + 0, + /* 11992 */ 'l', + 'n', + 'e', + 'r', + 9, + 0, + /* 11998 */ 'l', + 'p', + 'e', + 'r', + 9, + 0, + /* 12004 */ 's', + 'q', + 'e', + 'r', + 9, + 0, + /* 12010 */ 'l', + 'r', + 'e', + 'r', + 9, + 0, + /* 12016 */ 'm', + 's', + 'e', + 'r', + 9, + 0, + /* 12022 */ 'l', + 't', + 'e', + 'r', + 9, + 0, + /* 12028 */ 'l', + 'x', + 'e', + 'r', + 9, + 0, + /* 12034 */ 'l', + 'z', + 'e', + 'r', + 9, + 0, + /* 12040 */ 'l', + 'c', + 'd', + 'f', + 'r', + 9, + 0, + /* 12047 */ 'l', + 'n', + 'd', + 'f', + 'r', + 9, + 0, + /* 12054 */ 'l', + 'p', + 'd', + 'f', + 'r', + 9, + 0, + /* 12061 */ 'c', + 'e', + 'f', + 'r', + 9, + 0, + /* 12067 */ 'a', + 'g', + 'f', + 'r', + 9, + 0, + /* 12073 */ 'l', + 'c', + 'g', + 'f', + 'r', + 9, + 0, + /* 12080 */ 'a', + 'l', + 'g', + 'f', + 'r', + 9, + 0, + /* 12087 */ 'c', + 'l', + 'g', + 'f', + 'r', + 9, + 0, + /* 12094 */ 'l', + 'l', + 'g', + 'f', + 'r', + 9, + 0, + /* 12101 */ 's', + 'l', + 'g', + 'f', + 'r', + 9, + 0, + /* 12108 */ 'l', + 'n', + 'g', + 'f', + 'r', + 9, + 0, + /* 12115 */ 'l', + 'p', + 'g', + 'f', + 'r', + 9, + 0, + /* 12122 */ 'd', + 's', + 'g', + 'f', + 'r', + 9, + 0, + /* 12129 */ 'm', + 's', + 'g', + 'f', + 'r', + 9, + 0, + /* 12136 */ 'l', + 't', + 'g', + 'f', + 'r', + 9, + 0, + /* 12143 */ 'c', + 'x', + 'f', + 'r', + 9, + 0, + /* 12149 */ 'a', + 'g', + 'r', + 9, + 0, + /* 12154 */ 's', + 'l', + 'b', + 'g', + 'r', + 9, + 0, + /* 12161 */ 'a', + 'l', + 'c', + 'g', + 'r', + 9, + 0, + /* 12168 */ 'l', + 'o', + 'c', + 'g', + 'r', + 9, + 0, + /* 12175 */ 'c', + 'd', + 'g', + 'r', + 9, + 0, + /* 12181 */ 'l', + 'd', + 'g', + 'r', + 9, + 0, + /* 12187 */ 'c', + 'e', + 'g', + 'r', + 9, + 0, + /* 12193 */ 'a', + 'l', + 'g', + 'r', + 9, + 0, + /* 12199 */ 'c', + 'l', + 'g', + 'r', + 9, + 0, + /* 12205 */ 'd', + 'l', + 'g', + 'r', + 9, + 0, + /* 12211 */ 'm', + 'l', + 'g', + 'r', + 9, + 0, + /* 12217 */ 's', + 'l', + 'g', + 'r', + 9, + 0, + /* 12223 */ 'l', + 'n', + 'g', + 'r', + 9, + 0, + /* 12229 */ 'f', + 'l', + 'o', + 'g', + 'r', + 9, + 0, + /* 12236 */ 'l', + 'p', + 'g', + 'r', + 9, + 0, + /* 12242 */ 'd', + 's', + 'g', + 'r', + 9, + 0, + /* 12248 */ 'm', + 's', + 'g', + 'r', + 9, + 0, + /* 12254 */ 'b', + 'c', + 't', + 'g', + 'r', + 9, + 0, + /* 12261 */ 'l', + 't', + 'g', + 'r', + 9, + 0, + /* 12267 */ 'l', + 'r', + 'v', + 'g', + 'r', + 9, + 0, + /* 12274 */ 'c', + 'x', + 'g', + 'r', + 9, + 0, + /* 12280 */ 'b', + 'h', + 'r', + 9, + 0, + /* 12285 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 9, + 0, + /* 12293 */ 'l', + 'l', + 'g', + 'h', + 'r', + 9, + 0, + /* 12300 */ 'c', + 'h', + 'h', + 'r', + 9, + 0, + /* 12306 */ 'a', + 'h', + 'h', + 'h', + 'r', + 9, + 0, + /* 12313 */ 'a', + 'l', + 'h', + 'h', + 'h', + 'r', + 9, + 0, + /* 12321 */ 's', + 'l', + 'h', + 'h', + 'h', + 'r', + 9, + 0, + /* 12329 */ 's', + 'h', + 'h', + 'h', + 'r', + 9, + 0, + /* 12336 */ 'c', + 'l', + 'h', + 'h', + 'r', + 9, + 0, + /* 12343 */ 'b', + 'l', + 'h', + 'r', + 9, + 0, + /* 12349 */ 'l', + 'l', + 'h', + 'r', + 9, + 0, + /* 12355 */ 'b', + 'n', + 'l', + 'h', + 'r', + 9, + 0, + /* 12362 */ 'b', + 'n', + 'h', + 'r', + 9, + 0, + /* 12368 */ 'm', + 'a', + 'y', + 'h', + 'r', + 9, + 0, + /* 12375 */ 'm', + 'y', + 'h', + 'r', + 9, + 0, + /* 12381 */ 'e', + 'p', + 'a', + 'i', + 'r', + 9, + 0, + /* 12388 */ 'e', + 's', + 'a', + 'i', + 'r', + 9, + 0, + /* 12395 */ 's', + 's', + 'a', + 'i', + 'r', + 9, + 0, + /* 12402 */ 'b', + 'a', + 'k', + 'r', + 9, + 0, + /* 12408 */ 'b', + 'a', + 'l', + 'r', + 9, + 0, + /* 12414 */ 'b', + 'l', + 'r', + 9, + 0, + /* 12419 */ 'c', + 'l', + 'r', + 9, + 0, + /* 12424 */ 'd', + 'l', + 'r', + 9, + 0, + /* 12429 */ 'v', + 'f', + 'l', + 'r', + 9, + 0, + /* 12435 */ 'c', + 'h', + 'l', + 'r', + 9, + 0, + /* 12441 */ 'a', + 'h', + 'h', + 'l', + 'r', + 9, + 0, + /* 12448 */ 'a', + 'l', + 'h', + 'h', + 'l', + 'r', + 9, + 0, + /* 12456 */ 's', + 'l', + 'h', + 'h', + 'l', + 'r', + 9, + 0, + /* 12464 */ 's', + 'h', + 'h', + 'l', + 'r', + 9, + 0, + /* 12471 */ 'c', + 'l', + 'h', + 'l', + 'r', + 9, + 0, + /* 12478 */ 'm', + 'l', + 'r', + 9, + 0, + /* 12483 */ 'b', + 'n', + 'l', + 'r', + 9, + 0, + /* 12489 */ 'v', + 'l', + 'r', + 'l', + 'r', + 9, + 0, + /* 12496 */ 'v', + 's', + 't', + 'r', + 'l', + 'r', + 9, + 0, + /* 12504 */ 's', + 'l', + 'r', + 9, + 0, + /* 12509 */ 'v', + 'l', + 'r', + 9, + 0, + /* 12514 */ 'm', + 'a', + 'y', + 'l', + 'r', + 9, + 0, + /* 12521 */ 'm', + 'y', + 'l', + 'r', + 9, + 0, + /* 12527 */ 'b', + 'm', + 'r', + 9, + 0, + /* 12532 */ 'b', + 'n', + 'm', + 'r', + 9, + 0, + /* 12538 */ 'l', + 'n', + 'r', + 9, + 0, + /* 12543 */ 'b', + 'o', + 'r', + 9, + 0, + /* 12548 */ 'b', + 'n', + 'o', + 'r', + 9, + 0, + /* 12554 */ 'b', + 'p', + 'r', + 9, + 0, + /* 12559 */ 'l', + 'p', + 'r', + 9, + 0, + /* 12564 */ 'b', + 'n', + 'p', + 'r', + 9, + 0, + /* 12570 */ 'b', + 'a', + 's', + 'r', + 9, + 0, + /* 12576 */ 's', + 'f', + 'a', + 's', + 'r', + 9, + 0, + /* 12583 */ 'm', + 's', + 'r', + 9, + 0, + /* 12588 */ 'b', + 'c', + 't', + 'r', + 9, + 0, + /* 12594 */ 'e', + 'c', + 'c', + 't', + 'r', + 9, + 0, + /* 12601 */ 's', + 'c', + 'c', + 't', + 'r', + 9, + 0, + /* 12608 */ 'k', + 'm', + 'c', + 't', + 'r', + 9, + 0, + /* 12615 */ 'e', + 'p', + 'c', + 't', + 'r', + 9, + 0, + /* 12622 */ 's', + 'p', + 'c', + 't', + 'r', + 9, + 0, + /* 12629 */ 'q', + 'a', + 'd', + 't', + 'r', + 9, + 0, + /* 12636 */ 'c', + 'd', + 't', + 'r', + 9, + 0, + /* 12642 */ 'd', + 'd', + 't', + 'r', + 9, + 0, + /* 12648 */ 'c', + 'e', + 'd', + 't', + 'r', + 9, + 0, + /* 12655 */ 'e', + 'e', + 'd', + 't', + 'r', + 9, + 0, + /* 12662 */ 'i', + 'e', + 'd', + 't', + 'r', + 9, + 0, + /* 12669 */ 'l', + 'e', + 'd', + 't', + 'r', + 9, + 0, + /* 12676 */ 'c', + 'f', + 'd', + 't', + 'r', + 9, + 0, + /* 12683 */ 'c', + 'l', + 'f', + 'd', + 't', + 'r', + 9, + 0, + /* 12691 */ 'c', + 'g', + 'd', + 't', + 'r', + 9, + 0, + /* 12698 */ 'c', + 'l', + 'g', + 'd', + 't', + 'r', + 9, + 0, + /* 12706 */ 'f', + 'i', + 'd', + 't', + 'r', + 9, + 0, + /* 12713 */ 'k', + 'd', + 't', + 'r', + 9, + 0, + /* 12719 */ 'm', + 'd', + 't', + 'r', + 9, + 0, + /* 12725 */ 'r', + 'r', + 'd', + 't', + 'r', + 9, + 0, + /* 12732 */ 'c', + 's', + 'd', + 't', + 'r', + 9, + 0, + /* 12739 */ 'e', + 's', + 'd', + 't', + 'r', + 9, + 0, + /* 12746 */ 'l', + 't', + 'd', + 't', + 'r', + 9, + 0, + /* 12753 */ 'c', + 'u', + 'd', + 't', + 'r', + 9, + 0, + /* 12760 */ 'l', + 'x', + 'd', + 't', + 'r', + 9, + 0, + /* 12767 */ 'l', + 'd', + 'e', + 't', + 'r', + 9, + 0, + /* 12774 */ 'c', + 'd', + 'f', + 't', + 'r', + 9, + 0, + /* 12781 */ 'c', + 'd', + 'l', + 'f', + 't', + 'r', + 9, + 0, + /* 12789 */ 'c', + 'x', + 'l', + 'f', + 't', + 'r', + 9, + 0, + /* 12797 */ 'c', + 'x', + 'f', + 't', + 'r', + 9, + 0, + /* 12804 */ 'c', + 'd', + 'g', + 't', + 'r', + 9, + 0, + /* 12811 */ 'c', + 'd', + 'l', + 'g', + 't', + 'r', + 9, + 0, + /* 12819 */ 'l', + 'l', + 'g', + 't', + 'r', + 9, + 0, + /* 12826 */ 'c', + 'x', + 'l', + 'g', + 't', + 'r', + 9, + 0, + /* 12834 */ 'c', + 'x', + 'g', + 't', + 'r', + 9, + 0, + /* 12841 */ 'l', + 't', + 'r', + 9, + 0, + /* 12846 */ 't', + 'r', + 't', + 'r', + 9, + 0, + /* 12852 */ 'c', + 'd', + 's', + 't', + 'r', + 9, + 0, + /* 12859 */ 'v', + 'i', + 's', + 't', + 'r', + 9, + 0, + /* 12866 */ 'c', + 'x', + 's', + 't', + 'r', + 9, + 0, + /* 12873 */ 'c', + 'd', + 'u', + 't', + 'r', + 9, + 0, + /* 12880 */ 'c', + 'x', + 'u', + 't', + 'r', + 9, + 0, + /* 12887 */ 'q', + 'a', + 'x', + 't', + 'r', + 9, + 0, + /* 12894 */ 'c', + 'x', + 't', + 'r', + 9, + 0, + /* 12900 */ 'l', + 'd', + 'x', + 't', + 'r', + 9, + 0, + /* 12907 */ 'c', + 'e', + 'x', + 't', + 'r', + 9, + 0, + /* 12914 */ 'e', + 'e', + 'x', + 't', + 'r', + 9, + 0, + /* 12921 */ 'i', + 'e', + 'x', + 't', + 'r', + 9, + 0, + /* 12928 */ 'c', + 'f', + 'x', + 't', + 'r', + 9, + 0, + /* 12935 */ 'c', + 'l', + 'f', + 'x', + 't', + 'r', + 9, + 0, + /* 12943 */ 'c', + 'g', + 'x', + 't', + 'r', + 9, + 0, + /* 12950 */ 'c', + 'l', + 'g', + 'x', + 't', + 'r', + 9, + 0, + /* 12958 */ 'f', + 'i', + 'x', + 't', + 'r', + 9, + 0, + /* 12965 */ 'k', + 'x', + 't', + 'r', + 9, + 0, + /* 12971 */ 'm', + 'x', + 't', + 'r', + 9, + 0, + /* 12977 */ 'r', + 'r', + 'x', + 't', + 'r', + 9, + 0, + /* 12984 */ 'c', + 's', + 'x', + 't', + 'r', + 9, + 0, + /* 12991 */ 'e', + 's', + 'x', + 't', + 'r', + 9, + 0, + /* 12998 */ 'l', + 't', + 'x', + 't', + 'r', + 9, + 0, + /* 13005 */ 'c', + 'u', + 'x', + 't', + 'r', + 9, + 0, + /* 13012 */ 'a', + 'u', + 'r', + 9, + 0, + /* 13017 */ 's', + 'u', + 'r', + 9, + 0, + /* 13022 */ 'l', + 'r', + 'v', + 'r', + 9, + 0, + /* 13028 */ 'a', + 'w', + 'r', + 9, + 0, + /* 13033 */ 's', + 'w', + 'r', + 9, + 0, + /* 13038 */ 'a', + 'x', + 'r', + 9, + 0, + /* 13043 */ 'l', + 'c', + 'x', + 'r', + 9, + 0, + /* 13049 */ 'l', + 'd', + 'x', + 'r', + 9, + 0, + /* 13055 */ 'l', + 'e', + 'x', + 'r', + 9, + 0, + /* 13061 */ 'c', + 'f', + 'x', + 'r', + 9, + 0, + /* 13067 */ 'c', + 'g', + 'x', + 'r', + 9, + 0, + /* 13073 */ 'f', + 'i', + 'x', + 'r', + 9, + 0, + /* 13079 */ 'l', + 'x', + 'r', + 9, + 0, + /* 13084 */ 'm', + 'x', + 'r', + 9, + 0, + /* 13089 */ 'l', + 'n', + 'x', + 'r', + 9, + 0, + /* 13095 */ 'l', + 'p', + 'x', + 'r', + 9, + 0, + /* 13101 */ 's', + 'q', + 'x', + 'r', + 9, + 0, + /* 13107 */ 's', + 'x', + 'r', + 9, + 0, + /* 13112 */ 'l', + 't', + 'x', + 'r', + 9, + 0, + /* 13118 */ 'l', + 'z', + 'x', + 'r', + 9, + 0, + /* 13124 */ 'm', + 'a', + 'y', + 'r', + 9, + 0, + /* 13130 */ 'm', + 'y', + 'r', + 9, + 0, + /* 13135 */ 'b', + 'z', + 'r', + 9, + 0, + /* 13140 */ 'b', + 'n', + 'z', + 'r', + 9, + 0, + /* 13146 */ 'b', + 'a', + 's', + 9, + 0, + /* 13151 */ 'l', + 'f', + 'a', + 's', + 9, + 0, + /* 13157 */ 'b', + 'r', + 'a', + 's', + 9, + 0, + /* 13163 */ 'v', + 's', + 't', + 'r', + 'c', + 'b', + 's', + 9, + 0, + /* 13172 */ 'v', + 'f', + 'c', + 'e', + 'd', + 'b', + 's', + 9, + 0, + /* 13181 */ 'w', + 'f', + 'c', + 'e', + 'd', + 'b', + 's', + 9, + 0, + /* 13190 */ 'v', + 'f', + 'c', + 'h', + 'e', + 'd', + 'b', + 's', + 9, + 0, + /* 13200 */ 'w', + 'f', + 'c', + 'h', + 'e', + 'd', + 'b', + 's', + 9, + 0, + /* 13210 */ 'v', + 'f', + 'k', + 'h', + 'e', + 'd', + 'b', + 's', + 9, + 0, + /* 13220 */ 'w', + 'f', + 'k', + 'h', + 'e', + 'd', + 'b', + 's', + 9, + 0, + /* 13230 */ 'v', + 'f', + 'k', + 'e', + 'd', + 'b', + 's', + 9, + 0, + /* 13239 */ 'w', + 'f', + 'k', + 'e', + 'd', + 'b', + 's', + 9, + 0, + /* 13248 */ 'v', + 'f', + 'c', + 'h', + 'd', + 'b', + 's', + 9, + 0, + /* 13257 */ 'w', + 'f', + 'c', + 'h', + 'd', + 'b', + 's', + 9, + 0, + /* 13266 */ 'v', + 'f', + 'k', + 'h', + 'd', + 'b', + 's', + 9, + 0, + /* 13275 */ 'w', + 'f', + 'k', + 'h', + 'd', + 'b', + 's', + 9, + 0, + /* 13284 */ 'v', + 'f', + 'a', + 'e', + 'b', + 's', + 9, + 0, + /* 13292 */ 'v', + 'f', + 'e', + 'e', + 'b', + 's', + 9, + 0, + /* 13300 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'b', + 's', + 9, + 0, + /* 13309 */ 'v', + 'c', + 'h', + 'b', + 's', + 9, + 0, + /* 13316 */ 'v', + 'c', + 'h', + 'l', + 'b', + 's', + 9, + 0, + /* 13324 */ 'v', + 'c', + 'e', + 'q', + 'b', + 's', + 9, + 0, + /* 13332 */ 'v', + 'i', + 's', + 't', + 'r', + 'b', + 's', + 9, + 0, + /* 13341 */ 'v', + 'f', + 'c', + 'e', + 's', + 'b', + 's', + 9, + 0, + /* 13350 */ 'w', + 'f', + 'c', + 'e', + 's', + 'b', + 's', + 9, + 0, + /* 13359 */ 'v', + 'f', + 'c', + 'h', + 'e', + 's', + 'b', + 's', + 9, + 0, + /* 13369 */ 'w', + 'f', + 'c', + 'h', + 'e', + 's', + 'b', + 's', + 9, + 0, + /* 13379 */ 'v', + 'f', + 'k', + 'h', + 'e', + 's', + 'b', + 's', + 9, + 0, + /* 13389 */ 'w', + 'f', + 'k', + 'h', + 'e', + 's', + 'b', + 's', + 9, + 0, + /* 13399 */ 'v', + 'f', + 'k', + 'e', + 's', + 'b', + 's', + 9, + 0, + /* 13408 */ 'w', + 'f', + 'k', + 'e', + 's', + 'b', + 's', + 9, + 0, + /* 13417 */ 'v', + 'f', + 'c', + 'h', + 's', + 'b', + 's', + 9, + 0, + /* 13426 */ 'w', + 'f', + 'c', + 'h', + 's', + 'b', + 's', + 9, + 0, + /* 13435 */ 'v', + 'f', + 'k', + 'h', + 's', + 'b', + 's', + 9, + 0, + /* 13444 */ 'w', + 'f', + 'k', + 'h', + 's', + 'b', + 's', + 9, + 0, + /* 13453 */ 'w', + 'f', + 'c', + 'e', + 'x', + 'b', + 's', + 9, + 0, + /* 13462 */ 'w', + 'f', + 'c', + 'h', + 'e', + 'x', + 'b', + 's', + 9, + 0, + /* 13472 */ 'w', + 'f', + 'k', + 'h', + 'e', + 'x', + 'b', + 's', + 9, + 0, + /* 13482 */ 'w', + 'f', + 'k', + 'e', + 'x', + 'b', + 's', + 9, + 0, + /* 13491 */ 'w', + 'f', + 'c', + 'h', + 'x', + 'b', + 's', + 9, + 0, + /* 13500 */ 'w', + 'f', + 'k', + 'h', + 'x', + 'b', + 's', + 9, + 0, + /* 13509 */ 'v', + 's', + 't', + 'r', + 'c', + 'z', + 'b', + 's', + 9, + 0, + /* 13519 */ 'v', + 'f', + 'a', + 'e', + 'z', + 'b', + 's', + 9, + 0, + /* 13528 */ 'v', + 'f', + 'e', + 'e', + 'z', + 'b', + 's', + 9, + 0, + /* 13537 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'z', + 'b', + 's', + 9, + 0, + /* 13547 */ 'm', + 'v', + 'c', + 's', + 9, + 0, + /* 13553 */ 'c', + 'd', + 's', + 9, + 0, + /* 13558 */ 'v', + 's', + 't', + 'r', + 'c', + 'f', + 's', + 9, + 0, + /* 13567 */ 'v', + 'f', + 'a', + 'e', + 'f', + 's', + 9, + 0, + /* 13575 */ 'v', + 'f', + 'e', + 'e', + 'f', + 's', + 9, + 0, + /* 13583 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'f', + 's', + 9, + 0, + /* 13592 */ 'v', + 'c', + 'h', + 'f', + 's', + 9, + 0, + /* 13599 */ 'v', + 'c', + 'h', + 'l', + 'f', + 's', + 9, + 0, + /* 13607 */ 'v', + 'c', + 'e', + 'q', + 'f', + 's', + 9, + 0, + /* 13615 */ 'v', + 'i', + 's', + 't', + 'r', + 'f', + 's', + 9, + 0, + /* 13624 */ 'v', + 'p', + 'k', + 's', + 'f', + 's', + 9, + 0, + /* 13632 */ 'v', + 'p', + 'k', + 'l', + 's', + 'f', + 's', + 9, + 0, + /* 13641 */ 'v', + 'f', + 's', + 9, + 0, + /* 13646 */ 'v', + 's', + 't', + 'r', + 'c', + 'z', + 'f', + 's', + 9, + 0, + /* 13656 */ 'v', + 'f', + 'a', + 'e', + 'z', + 'f', + 's', + 9, + 0, + /* 13665 */ 'v', + 'f', + 'e', + 'e', + 'z', + 'f', + 's', + 9, + 0, + /* 13674 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'z', + 'f', + 's', + 9, + 0, + /* 13684 */ 'v', + 'c', + 'h', + 'g', + 's', + 9, + 0, + /* 13691 */ 'v', + 'c', + 'h', + 'l', + 'g', + 's', + 9, + 0, + /* 13699 */ 'v', + 'c', + 'e', + 'q', + 'g', + 's', + 9, + 0, + /* 13707 */ 'v', + 'p', + 'k', + 's', + 'g', + 's', + 9, + 0, + /* 13715 */ 'v', + 'p', + 'k', + 'l', + 's', + 'g', + 's', + 9, + 0, + /* 13724 */ 'v', + 's', + 't', + 'r', + 'c', + 'h', + 's', + 9, + 0, + /* 13733 */ 'v', + 'f', + 'a', + 'e', + 'h', + 's', + 9, + 0, + /* 13741 */ 'v', + 'f', + 'e', + 'e', + 'h', + 's', + 9, + 0, + /* 13749 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'h', + 's', + 9, + 0, + /* 13758 */ 'v', + 'c', + 'h', + 'h', + 's', + 9, + 0, + /* 13765 */ 'v', + 'c', + 'h', + 'l', + 'h', + 's', + 9, + 0, + /* 13773 */ 'v', + 'c', + 'e', + 'q', + 'h', + 's', + 9, + 0, + /* 13781 */ 'v', + 'i', + 's', + 't', + 'r', + 'h', + 's', + 9, + 0, + /* 13790 */ 'v', + 'p', + 'k', + 's', + 'h', + 's', + 9, + 0, + /* 13798 */ 'v', + 'p', + 'k', + 'l', + 's', + 'h', + 's', + 9, + 0, + /* 13807 */ 'v', + 's', + 't', + 'r', + 'c', + 'z', + 'h', + 's', + 9, + 0, + /* 13817 */ 'v', + 'f', + 'a', + 'e', + 'z', + 'h', + 's', + 9, + 0, + /* 13826 */ 'v', + 'f', + 'e', + 'e', + 'z', + 'h', + 's', + 9, + 0, + /* 13835 */ 'v', + 'f', + 'e', + 'n', + 'e', + 'z', + 'h', + 's', + 9, + 0, + /* 13845 */ 'v', + 'p', + 'k', + 's', + 9, + 0, + /* 13851 */ 'v', + 'p', + 'k', + 'l', + 's', + 9, + 0, + /* 13858 */ 'v', + 'f', + 'l', + 'l', + 's', + 9, + 0, + /* 13865 */ 'w', + 'f', + 'l', + 'l', + 's', + 9, + 0, + /* 13872 */ 'v', + 'f', + 'm', + 's', + 9, + 0, + /* 13878 */ 'v', + 'f', + 'n', + 'm', + 's', + 9, + 0, + /* 13885 */ 'm', + 'v', + 'c', + 'o', + 's', + 9, + 0, + /* 13892 */ 's', + 't', + 'c', + 'p', + 's', + 9, + 0, + /* 13899 */ 't', + 's', + 9, + 0, + /* 13903 */ 'v', + 's', + 9, + 0, + /* 13907 */ 'l', + 'l', + 'g', + 'f', + 'a', + 't', + 9, + 0, + /* 13915 */ 'l', + 'g', + 'a', + 't', + 9, + 0, + /* 13921 */ 'l', + 'f', + 'h', + 'a', + 't', + 9, + 0, + /* 13928 */ 'l', + 'a', + 't', + 9, + 0, + /* 13933 */ 'l', + 'l', + 'g', + 't', + 'a', + 't', + 9, + 0, + /* 13941 */ 'b', + 'c', + 't', + 9, + 0, + /* 13946 */ 'v', + 'p', + 'o', + 'p', + 'c', + 't', + 9, + 0, + /* 13954 */ 'b', + 'r', + 'c', + 't', + 9, + 0, + /* 13960 */ 't', + 'd', + 'c', + 'd', + 't', + 9, + 0, + /* 13967 */ 't', + 'd', + 'g', + 'd', + 't', + 9, + 0, + /* 13974 */ 's', + 'l', + 'd', + 't', + 9, + 0, + /* 13980 */ 'c', + 'p', + 'd', + 't', + 9, + 0, + /* 13986 */ 's', + 'r', + 'd', + 't', + 9, + 0, + /* 13992 */ 'c', + 'z', + 'd', + 't', + 9, + 0, + /* 13998 */ 't', + 'd', + 'c', + 'e', + 't', + 9, + 0, + /* 14005 */ 't', + 'd', + 'g', + 'e', + 't', + 9, + 0, + /* 14012 */ 'c', + 'l', + 'g', + 't', + 9, + 0, + /* 14018 */ 'l', + 'l', + 'g', + 't', + 9, + 0, + /* 14024 */ 'c', + 'i', + 't', + 9, + 0, + /* 14029 */ 'c', + 'l', + 'f', + 'i', + 't', + 9, + 0, + /* 14036 */ 'c', + 'g', + 'i', + 't', + 9, + 0, + /* 14042 */ 'c', + 'l', + 'g', + 'i', + 't', + 9, + 0, + /* 14049 */ 'c', + 'l', + 't', + 9, + 0, + /* 14054 */ 's', + 'r', + 'n', + 'm', + 't', + 9, + 0, + /* 14061 */ 'p', + 'o', + 'p', + 'c', + 'n', + 't', + 9, + 0, + /* 14069 */ 't', + 'p', + 'r', + 'o', + 't', + 9, + 0, + /* 14076 */ 't', + 'r', + 'o', + 't', + 9, + 0, + /* 14082 */ 'c', + 'd', + 'p', + 't', + 9, + 0, + /* 14088 */ 's', + 'p', + 't', + 9, + 0, + /* 14093 */ 's', + 't', + 'p', + 't', + 9, + 0, + /* 14099 */ 'c', + 'x', + 'p', + 't', + 9, + 0, + /* 14105 */ 'c', + 'r', + 't', + 9, + 0, + /* 14110 */ 'c', + 'g', + 'r', + 't', + 9, + 0, + /* 14116 */ 'c', + 'l', + 'g', + 'r', + 't', + 9, + 0, + /* 14123 */ 'c', + 'l', + 'r', + 't', + 9, + 0, + /* 14129 */ 't', + 'a', + 'b', + 'o', + 'r', + 't', + 9, + 0, + /* 14137 */ 't', + 'r', + 't', + 9, + 0, + /* 14142 */ 'c', + 'l', + 's', + 't', + 9, + 0, + /* 14148 */ 's', + 'r', + 's', + 't', + 9, + 0, + /* 14154 */ 'c', + 's', + 's', + 't', + 9, + 0, + /* 14160 */ 'm', + 'v', + 's', + 't', + 9, + 0, + /* 14166 */ 't', + 'r', + 't', + 't', + 9, + 0, + /* 14172 */ 'p', + 'g', + 'o', + 'u', + 't', + 9, + 0, + /* 14179 */ 't', + 'd', + 'c', + 'x', + 't', + 9, + 0, + /* 14186 */ 't', + 'd', + 'g', + 'x', + 't', + 9, + 0, + /* 14193 */ 's', + 'l', + 'x', + 't', + 9, + 0, + /* 14199 */ 'c', + 'p', + 'x', + 't', + 9, + 0, + /* 14205 */ 's', + 'r', + 'x', + 't', + 9, + 0, + /* 14211 */ 'c', + 'z', + 'x', + 't', + 9, + 0, + /* 14217 */ 'c', + 'd', + 'z', + 't', + 9, + 0, + /* 14223 */ 'c', + 'x', + 'z', + 't', + 9, + 0, + /* 14229 */ 'a', + 'u', + 9, + 0, + /* 14233 */ 'c', + 'u', + 't', + 'f', + 'u', + 9, + 0, + /* 14240 */ 'u', + 'n', + 'p', + 'k', + 'u', + 9, + 0, + /* 14247 */ 'c', + 'l', + 'c', + 'l', + 'u', + 9, + 0, + /* 14254 */ 'm', + 'v', + 'c', + 'l', + 'u', + 9, + 0, + /* 14261 */ 's', + 'u', + 9, + 0, + /* 14265 */ 's', + 'r', + 's', + 't', + 'u', + 9, + 0, + /* 14272 */ 'v', + 'e', + 's', + 'r', + 'a', + 'v', + 9, + 0, + /* 14280 */ 'v', + 'l', + 'g', + 'v', + 9, + 0, + /* 14286 */ 'v', + 'e', + 'r', + 'l', + 'l', + 'v', + 9, + 0, + /* 14294 */ 'v', + 'e', + 's', + 'r', + 'l', + 'v', + 9, + 0, + /* 14302 */ 'v', + 'e', + 's', + 'l', + 'v', + 9, + 0, + /* 14309 */ 'l', + 'r', + 'v', + 9, + 0, + /* 14314 */ 's', + 't', + 'r', + 'v', + 9, + 0, + /* 14320 */ 'a', + 'w', + 9, + 0, + /* 14324 */ 'v', + 'm', + 'a', + 'l', + 'h', + 'w', + 9, + 0, + /* 14332 */ 'v', + 'm', + 'l', + 'h', + 'w', + 9, + 0, + /* 14339 */ 'v', + 'u', + 'p', + 'l', + 'h', + 'w', + 9, + 0, + /* 14347 */ 's', + 't', + 'c', + 'r', + 'w', + 9, + 0, + /* 14354 */ 'e', + 'p', + 's', + 'w', + 9, + 0, + /* 14360 */ 'l', + 'p', + 's', + 'w', + 9, + 0, + /* 14366 */ 'l', + 'a', + 'x', + 9, + 0, + /* 14371 */ 'v', + 'f', + 'm', + 'a', + 'x', + 9, + 0, + /* 14378 */ 'e', + 'x', + 9, + 0, + /* 14382 */ 'v', + 'm', + 'x', + 9, + 0, + /* 14387 */ 'v', + 'n', + 'x', + 9, + 0, + /* 14392 */ 's', + 'p', + 'x', + 9, + 0, + /* 14397 */ 's', + 't', + 'p', + 'x', + 9, + 0, + /* 14403 */ 'w', + 'f', + 'l', + 'r', + 'x', + 9, + 0, + /* 14410 */ 'v', + 'x', + 9, + 0, + /* 14414 */ 'l', + 'a', + 'y', + 9, + 0, + /* 14419 */ 'm', + 'a', + 'y', + 9, + 0, + /* 14424 */ 'l', + 'r', + 'a', + 'y', + 9, + 0, + /* 14430 */ 'c', + 'v', + 'b', + 'y', + 9, + 0, + /* 14436 */ 'i', + 'c', + 'y', + 9, + 0, + /* 14441 */ 's', + 't', + 'c', + 'y', + 9, + 0, + /* 14447 */ 'l', + 'd', + 'y', + 9, + 0, + /* 14452 */ 's', + 't', + 'd', + 'y', + 9, + 0, + /* 14458 */ 'c', + 'v', + 'd', + 'y', + 9, + 0, + /* 14464 */ 'l', + 'a', + 'e', + 'y', + 9, + 0, + /* 14470 */ 'l', + 'e', + 'y', + 9, + 0, + /* 14475 */ 's', + 't', + 'e', + 'y', + 9, + 0, + /* 14481 */ 'm', + 'f', + 'y', + 9, + 0, + /* 14486 */ 'a', + 'h', + 'y', + 9, + 0, + /* 14491 */ 'c', + 'h', + 'y', + 9, + 0, + /* 14496 */ 'l', + 'h', + 'y', + 9, + 0, + /* 14501 */ 'm', + 'h', + 'y', + 9, + 0, + /* 14506 */ 's', + 'h', + 'y', + 9, + 0, + /* 14511 */ 's', + 't', + 'h', + 'y', + 9, + 0, + /* 14517 */ 'c', + 'l', + 'i', + 'y', + 9, + 0, + /* 14523 */ 'n', + 'i', + 'y', + 9, + 0, + /* 14528 */ 'o', + 'i', + 'y', + 9, + 0, + /* 14533 */ 'm', + 'v', + 'i', + 'y', + 9, + 0, + /* 14539 */ 'x', + 'i', + 'y', + 9, + 0, + /* 14544 */ 'a', + 'l', + 'y', + 9, + 0, + /* 14549 */ 'c', + 'l', + 'y', + 9, + 0, + /* 14554 */ 's', + 'l', + 'y', + 9, + 0, + /* 14559 */ 'l', + 'a', + 'm', + 'y', + 9, + 0, + /* 14565 */ 's', + 't', + 'a', + 'm', + 'y', + 9, + 0, + /* 14572 */ 'i', + 'c', + 'm', + 'y', + 9, + 0, + /* 14578 */ 's', + 't', + 'c', + 'm', + 'y', + 9, + 0, + /* 14585 */ 'c', + 'l', + 'm', + 'y', + 9, + 0, + /* 14591 */ 's', + 't', + 'm', + 'y', + 9, + 0, + /* 14597 */ 'n', + 'y', + 9, + 0, + /* 14601 */ 'o', + 'y', + 9, + 0, + /* 14605 */ 'c', + 's', + 'y', + 9, + 0, + /* 14610 */ 'c', + 'd', + 's', + 'y', + 9, + 0, + /* 14616 */ 'm', + 's', + 'y', + 9, + 0, + /* 14621 */ 's', + 't', + 'y', + 9, + 0, + /* 14626 */ 'x', + 'y', + 9, + 0, + /* 14630 */ 'b', + 'z', + 9, + 0, + /* 14634 */ 'l', + 'o', + 'c', + 'z', + 9, + 0, + /* 14640 */ 's', + 't', + 'o', + 'c', + 'z', + 9, + 0, + /* 14647 */ 'v', + 'l', + 'l', + 'e', + 'z', + 9, + 0, + /* 14654 */ 'l', + 'o', + 'c', + 'g', + 'z', + 9, + 0, + /* 14661 */ 's', + 't', + 'o', + 'c', + 'g', + 'z', + 9, + 0, + /* 14669 */ 'j', + 'g', + 'z', + 9, + 0, + /* 14674 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'z', + 9, + 0, + /* 14682 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'z', + 9, + 0, + /* 14691 */ 'b', + 'i', + 'z', + 9, + 0, + /* 14696 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'z', + 9, + 0, + /* 14704 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'z', + 9, + 0, + /* 14713 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'z', + 9, + 0, + /* 14722 */ 'j', + 'z', + 9, + 0, + /* 14726 */ 'v', + 'u', + 'p', + 'k', + 'z', + 9, + 0, + /* 14733 */ 'v', + 'p', + 'k', + 'z', + 9, + 0, + /* 14739 */ 'v', + 'c', + 'l', + 'z', + 9, + 0, + /* 14745 */ 'b', + 'n', + 'z', + 9, + 0, + /* 14750 */ 'l', + 'o', + 'c', + 'n', + 'z', + 9, + 0, + /* 14757 */ 's', + 't', + 'o', + 'c', + 'n', + 'z', + 9, + 0, + /* 14765 */ 'l', + 'o', + 'c', + 'g', + 'n', + 'z', + 9, + 0, + /* 14773 */ 's', + 't', + 'o', + 'c', + 'g', + 'n', + 'z', + 9, + 0, + /* 14782 */ 'j', + 'g', + 'n', + 'z', + 9, + 0, + /* 14788 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'n', + 'z', + 9, + 0, + /* 14797 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 'n', + 'z', + 9, + 0, + /* 14807 */ 'b', + 'i', + 'n', + 'z', + 9, + 0, + /* 14813 */ 'l', + 'o', + 'c', + 'h', + 'i', + 'n', + 'z', + 9, + 0, + /* 14822 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 'n', + 'z', + 9, + 0, + /* 14832 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 'n', + 'z', + 9, + 0, + /* 14842 */ 'j', + 'n', + 'z', + 9, + 0, + /* 14847 */ 'l', + 'o', + 'c', + 'r', + 'n', + 'z', + 9, + 0, + /* 14855 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'n', + 'z', + 9, + 0, + /* 14864 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'n', + 'z', + 9, + 0, + /* 14874 */ 'l', + 'o', + 'c', + 'r', + 'z', + 9, + 0, + /* 14881 */ 'l', + 'o', + 'c', + 'g', + 'r', + 'z', + 9, + 0, + /* 14889 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 'z', + 9, + 0, + /* 14898 */ 'v', + 'c', + 't', + 'z', + 9, + 0, + /* 14904 */ 'm', + 'v', + 'z', + 9, + 0, + /* 14909 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'e', + ',', + 0, + /* 14918 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'i', + 'e', + ',', + 0, + /* 14929 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'r', + 'e', + ',', + 0, + /* 14940 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 's', + 'e', + ',', + 0, + /* 14951 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 's', + 's', + 'e', + ',', + 0, + /* 14962 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'x', + 'e', + ',', + 0, + /* 14973 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'r', + 'f', + ',', + 0, + /* 14984 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 's', + 's', + 'f', + ',', + 0, + /* 14995 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'x', + 'f', + ',', + 0, + /* 15006 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'i', + ',', + 0, + /* 15016 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 's', + 'i', + ',', + 0, + /* 15026 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 's', + 'i', + ',', + 0, + /* 15037 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'i', + 'l', + ',', + 0, + /* 15048 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 's', + 'i', + 'l', + ',', + 0, + /* 15059 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'r', + ',', + 0, + /* 15069 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 's', + ',', + 0, + /* 15078 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'i', + 's', + ',', + 0, + /* 15089 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 's', + ',', + 0, + /* 15099 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'r', + 's', + ',', + 0, + /* 15110 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 's', + 's', + ',', + 0, + /* 15120 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'i', + 'l', + 'u', + ',', + 0, + /* 15132 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'x', + ',', + 0, + /* 15142 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 's', + 'i', + 'y', + ',', + 0, + /* 15153 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 's', + 'y', + ',', + 0, + /* 15164 */ '.', + 'i', + 'n', + 's', + 'n', + 32, + 'r', + 'x', + 'y', + ',', + 0, + /* 15175 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'P', + 'a', + 't', + 'c', + 'h', + 'a', + 'b', + 'l', + 'e', + 32, + 'R', + 'E', + 'T', + '.', + 0, + /* 15206 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'y', + 'p', + 'e', + 'd', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 15230 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'C', + 'u', + 's', + 't', + 'o', + 'm', + 32, + 'E', + 'v', + 'e', + 'n', + 't', + 32, + 'L', + 'o', + 'g', + '.', + 0, + /* 15255 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'n', + 't', + 'e', + 'r', + '.', + 0, + /* 15278 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'T', + 'a', + 'i', + 'l', + 32, + 'C', + 'a', + 'l', + 'l', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 15301 */ '#', + 32, + 'X', + 'R', + 'a', + 'y', + 32, + 'F', + 'u', + 'n', + 'c', + 't', + 'i', + 'o', + 'n', + 32, + 'E', + 'x', + 'i', + 't', + '.', + 0, + /* 15323 */ 's', + 'a', + 'm', + '3', + '1', + 0, + /* 15329 */ 't', + 'r', + 'a', + 'p', + '2', + 0, + /* 15335 */ 's', + 'a', + 'm', + '2', + '4', + 0, + /* 15341 */ 's', + 'a', + 'm', + '6', + '4', + 0, + /* 15347 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'E', + 'N', + 'D', + 0, + /* 15360 */ 'B', + 'U', + 'N', + 'D', + 'L', + 'E', + 0, + /* 15367 */ 'D', + 'B', + 'G', + '_', + 'V', + 'A', + 'L', + 'U', + 'E', + 0, + /* 15377 */ 'D', + 'B', + 'G', + '_', + 'L', + 'A', + 'B', + 'E', + 'L', + 0, + /* 15387 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'S', + 'T', + 'A', + 'R', + 'T', + 0, + /* 15402 */ 'c', + 'i', + 'b', + 0, + /* 15406 */ 'c', + 'g', + 'i', + 'b', + 0, + /* 15411 */ 'c', + 'l', + 'g', + 'i', + 'b', + 0, + /* 15417 */ 'c', + 'l', + 'i', + 'b', + 0, + /* 15422 */ 'p', + 'a', + 'l', + 'b', + 0, + /* 15427 */ 'p', + 't', + 'l', + 'b', + 0, + /* 15432 */ 'c', + 'r', + 'b', + 0, + /* 15436 */ 'c', + 'g', + 'r', + 'b', + 0, + /* 15441 */ 'c', + 'l', + 'g', + 'r', + 'b', + 0, + /* 15447 */ 'c', + 'l', + 'r', + 'b', + 0, + /* 15452 */ 'p', + 'c', + 'c', + 0, + /* 15456 */ 'l', + 'o', + 'c', + 0, + /* 15460 */ 's', + 't', + 'o', + 'c', + 0, + /* 15465 */ 't', + 'e', + 'n', + 'd', + 0, + /* 15470 */ 'p', + 't', + 'f', + 'f', + 0, + /* 15475 */ 's', + 'c', + 'k', + 'p', + 'f', + 0, + /* 15481 */ 'l', + 'o', + 'c', + 'g', + 0, + /* 15486 */ 's', + 't', + 'o', + 'c', + 'g', + 0, + /* 15492 */ 'j', + 'g', + 0, + /* 15495 */ 'c', + 's', + 'c', + 'h', + 0, + /* 15500 */ 'h', + 's', + 'c', + 'h', + 0, + /* 15505 */ 'r', + 's', + 'c', + 'h', + 0, + /* 15510 */ 'x', + 's', + 'c', + 'h', + 0, + /* 15515 */ 'l', + 'o', + 'c', + 'f', + 'h', + 0, + /* 15521 */ 's', + 't', + 'o', + 'c', + 'f', + 'h', + 0, + /* 15528 */ 'b', + 'i', + 0, + /* 15531 */ 'l', + 'o', + 'c', + 'h', + 'i', + 0, + /* 15537 */ 'l', + 'o', + 'c', + 'g', + 'h', + 'i', + 0, + /* 15544 */ 'l', + 'o', + 'c', + 'h', + 'h', + 'i', + 0, + /* 15551 */ 'c', + 'i', + 'j', + 0, + /* 15555 */ 'c', + 'g', + 'i', + 'j', + 0, + /* 15560 */ 'c', + 'l', + 'g', + 'i', + 'j', + 0, + /* 15566 */ 'c', + 'l', + 'i', + 'j', + 0, + /* 15571 */ 'c', + 'r', + 'j', + 0, + /* 15575 */ 'c', + 'g', + 'r', + 'j', + 0, + /* 15580 */ 'c', + 'l', + 'g', + 'r', + 'j', + 0, + /* 15586 */ 'c', + 'l', + 'r', + 'j', + 0, + /* 15591 */ 'i', + 'p', + 'k', + 0, + /* 15595 */ 's', + 'a', + 'l', + 0, + /* 15599 */ '#', + 32, + 'F', + 'E', + 'n', + 't', + 'r', + 'y', + 32, + 'c', + 'a', + 'l', + 'l', + 0, + /* 15613 */ 't', + 'a', + 'm', + 0, + /* 15617 */ 's', + 'c', + 'h', + 'm', + 0, + /* 15622 */ 'p', + 'c', + 'k', + 'm', + 'o', + 0, + /* 15628 */ 'p', + 'f', + 'p', + 'o', + 0, + /* 15633 */ 'r', + 'c', + 'h', + 'p', + 0, + /* 15638 */ 'l', + 'o', + 'c', + 'r', + 0, + /* 15643 */ 'l', + 'o', + 'c', + 'g', + 'r', + 0, + /* 15649 */ 'l', + 'o', + 'c', + 'f', + 'h', + 'r', + 0, + /* 15656 */ 'p', + 'r', + 0, + /* 15659 */ 'c', + 'l', + 'g', + 't', + 0, + /* 15664 */ 'c', + 'i', + 't', + 0, + /* 15668 */ 'c', + 'l', + 'f', + 'i', + 't', + 0, + /* 15674 */ 'c', + 'g', + 'i', + 't', + 0, + /* 15679 */ 'c', + 'l', + 'g', + 'i', + 't', + 0, + /* 15685 */ 'c', + 'l', + 't', + 0, + /* 15689 */ 'u', + 'p', + 't', + 0, + /* 15693 */ 'c', + 'r', + 't', + 0, + /* 15697 */ 'c', + 'g', + 'r', + 't', + 0, + /* 15702 */ 'c', + 'l', + 'g', + 'r', + 't', + 0, + /* 15708 */ 'c', + 'l', + 'r', + 't', + 0, }; #endif static const uint32_t OpInfo0[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 15368U, // DBG_VALUE - 15378U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 15361U, // BUNDLE - 15388U, // LIFETIME_START - 15348U, // LIFETIME_END - 0U, // STACKMAP - 15600U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 15256U, // PATCHABLE_FUNCTION_ENTER - 15176U, // PATCHABLE_RET - 15302U, // PATCHABLE_FUNCTION_EXIT - 15279U, // PATCHABLE_TAIL_CALL - 15231U, // PATCHABLE_EVENT_CALL - 15207U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDE - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SSUBO - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_BSWAP - 0U, // G_ADDRSPACE_CAST - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 0U, // ADJDYNALLOC - 0U, // AEXT128 - 0U, // AFIMux - 0U, // AHIMux - 0U, // AHIMuxK - 0U, // ATOMIC_CMP_SWAPW - 0U, // ATOMIC_LOADW_AFI - 0U, // ATOMIC_LOADW_AR - 0U, // ATOMIC_LOADW_MAX - 0U, // ATOMIC_LOADW_MIN - 0U, // ATOMIC_LOADW_NILH - 0U, // ATOMIC_LOADW_NILHi - 0U, // ATOMIC_LOADW_NR - 0U, // ATOMIC_LOADW_NRi - 0U, // ATOMIC_LOADW_OILH - 0U, // ATOMIC_LOADW_OR - 0U, // ATOMIC_LOADW_SR - 0U, // ATOMIC_LOADW_UMAX - 0U, // ATOMIC_LOADW_UMIN - 0U, // ATOMIC_LOADW_XILF - 0U, // ATOMIC_LOADW_XR - 0U, // ATOMIC_LOAD_AFI - 0U, // ATOMIC_LOAD_AGFI - 0U, // ATOMIC_LOAD_AGHI - 0U, // ATOMIC_LOAD_AGR - 0U, // ATOMIC_LOAD_AHI - 0U, // ATOMIC_LOAD_AR - 0U, // ATOMIC_LOAD_MAX_32 - 0U, // ATOMIC_LOAD_MAX_64 - 0U, // ATOMIC_LOAD_MIN_32 - 0U, // ATOMIC_LOAD_MIN_64 - 0U, // ATOMIC_LOAD_NGR - 0U, // ATOMIC_LOAD_NGRi - 0U, // ATOMIC_LOAD_NIHF64 - 0U, // ATOMIC_LOAD_NIHF64i - 0U, // ATOMIC_LOAD_NIHH64 - 0U, // ATOMIC_LOAD_NIHH64i - 0U, // ATOMIC_LOAD_NIHL64 - 0U, // ATOMIC_LOAD_NIHL64i - 0U, // ATOMIC_LOAD_NILF - 0U, // ATOMIC_LOAD_NILF64 - 0U, // ATOMIC_LOAD_NILF64i - 0U, // ATOMIC_LOAD_NILFi - 0U, // ATOMIC_LOAD_NILH - 0U, // ATOMIC_LOAD_NILH64 - 0U, // ATOMIC_LOAD_NILH64i - 0U, // ATOMIC_LOAD_NILHi - 0U, // ATOMIC_LOAD_NILL - 0U, // ATOMIC_LOAD_NILL64 - 0U, // ATOMIC_LOAD_NILL64i - 0U, // ATOMIC_LOAD_NILLi - 0U, // ATOMIC_LOAD_NR - 0U, // ATOMIC_LOAD_NRi - 0U, // ATOMIC_LOAD_OGR - 0U, // ATOMIC_LOAD_OIHF64 - 0U, // ATOMIC_LOAD_OIHH64 - 0U, // ATOMIC_LOAD_OIHL64 - 0U, // ATOMIC_LOAD_OILF - 0U, // ATOMIC_LOAD_OILF64 - 0U, // ATOMIC_LOAD_OILH - 0U, // ATOMIC_LOAD_OILH64 - 0U, // ATOMIC_LOAD_OILL - 0U, // ATOMIC_LOAD_OILL64 - 0U, // ATOMIC_LOAD_OR - 0U, // ATOMIC_LOAD_SGR - 0U, // ATOMIC_LOAD_SR - 0U, // ATOMIC_LOAD_UMAX_32 - 0U, // ATOMIC_LOAD_UMAX_64 - 0U, // ATOMIC_LOAD_UMIN_32 - 0U, // ATOMIC_LOAD_UMIN_64 - 0U, // ATOMIC_LOAD_XGR - 0U, // ATOMIC_LOAD_XIHF64 - 0U, // ATOMIC_LOAD_XILF - 0U, // ATOMIC_LOAD_XILF64 - 0U, // ATOMIC_LOAD_XR - 0U, // ATOMIC_SWAPW - 0U, // ATOMIC_SWAP_32 - 0U, // ATOMIC_SWAP_64 - 0U, // CFIMux - 0U, // CGIBCall - 0U, // CGIBReturn - 0U, // CGRBCall - 0U, // CGRBReturn - 0U, // CHIMux - 0U, // CIBCall - 0U, // CIBReturn - 0U, // CLCLoop - 0U, // CLCSequence - 0U, // CLFIMux - 0U, // CLGIBCall - 0U, // CLGIBReturn - 0U, // CLGRBCall - 0U, // CLGRBReturn - 0U, // CLIBCall - 0U, // CLIBReturn - 0U, // CLMux - 0U, // CLRBCall - 0U, // CLRBReturn - 0U, // CLSTLoop - 0U, // CMux - 0U, // CRBCall - 0U, // CRBReturn - 0U, // CallBASR - 0U, // CallBCR - 0U, // CallBR - 0U, // CallBRASL - 0U, // CallBRCL - 0U, // CallJG - 0U, // CondReturn - 0U, // CondStore16 - 0U, // CondStore16Inv - 0U, // CondStore16Mux - 0U, // CondStore16MuxInv - 0U, // CondStore32 - 0U, // CondStore32Inv - 0U, // CondStore32Mux - 0U, // CondStore32MuxInv - 0U, // CondStore64 - 0U, // CondStore64Inv - 0U, // CondStore8 - 0U, // CondStore8Inv - 0U, // CondStore8Mux - 0U, // CondStore8MuxInv - 0U, // CondStoreF32 - 0U, // CondStoreF32Inv - 0U, // CondStoreF64 - 0U, // CondStoreF64Inv - 0U, // CondTrap - 0U, // GOT - 0U, // IIFMux - 0U, // IIHF64 - 0U, // IIHH64 - 0U, // IIHL64 - 0U, // IIHMux - 0U, // IILF64 - 0U, // IILH64 - 0U, // IILL64 - 0U, // IILMux - 0U, // L128 - 0U, // LBMux - 0U, // LEFR - 0U, // LFER - 0U, // LHIMux - 0U, // LHMux - 0U, // LLCMux - 0U, // LLCRMux - 0U, // LLHMux - 0U, // LLHRMux - 0U, // LMux - 0U, // LOCHIMux - 0U, // LOCMux - 0U, // LOCRMux - 0U, // LRMux - 0U, // LTDBRCompare_VecPseudo - 0U, // LTEBRCompare_VecPseudo - 0U, // LTXBRCompare_VecPseudo - 0U, // LX - 0U, // MVCLoop - 0U, // MVCSequence - 0U, // MVSTLoop - 0U, // MemBarrier - 0U, // NCLoop - 0U, // NCSequence - 0U, // NIFMux - 0U, // NIHF64 - 0U, // NIHH64 - 0U, // NIHL64 - 0U, // NIHMux - 0U, // NILF64 - 0U, // NILH64 - 0U, // NILL64 - 0U, // NILMux - 0U, // OCLoop - 0U, // OCSequence - 0U, // OIFMux - 0U, // OIHF64 - 0U, // OIHH64 - 0U, // OIHL64 - 0U, // OIHMux - 0U, // OILF64 - 0U, // OILH64 - 0U, // OILL64 - 0U, // OILMux - 0U, // PAIR128 - 0U, // RISBHH - 0U, // RISBHL - 0U, // RISBLH - 0U, // RISBLL - 0U, // RISBMux - 0U, // Return - 0U, // SRSTLoop - 0U, // ST128 - 0U, // STCMux - 0U, // STHMux - 0U, // STMux - 0U, // STOCMux - 0U, // STX - 0U, // Select32 - 0U, // Select64 - 0U, // SelectF128 - 0U, // SelectF32 - 0U, // SelectF64 - 0U, // SelectVR128 - 0U, // SelectVR32 - 0U, // SelectVR64 - 0U, // Serialize - 0U, // TBEGIN_nofloat - 0U, // TLS_GDCALL - 0U, // TLS_LDCALL - 0U, // TMHH64 - 0U, // TMHL64 - 0U, // TMHMux - 0U, // TMLH64 - 0U, // TMLL64 - 0U, // TMLMux - 0U, // Trap - 0U, // VL32 - 0U, // VL64 - 0U, // VLR32 - 0U, // VLR64 - 0U, // VLVGP32 - 0U, // VST32 - 0U, // VST64 - 0U, // XCLoop - 0U, // XCSequence - 0U, // XIFMux - 0U, // XIHF64 - 0U, // XILF64 - 0U, // ZEXT128 - 16430U, // A - 18800U, // AD - 16883U, // ADB - 16804865U, // ADBR - 16805360U, // ADR - 1107325271U, // ADTR - 1107312942U, // ADTRA - 18918U, // AE - 17340U, // AEB - 16804997U, // AEBR - 16805497U, // AER - 50356445U, // AFI - 21882U, // AG - 21267U, // AGF - 50356455U, // AGFI - 16805668U, // AGFR - 22882U, // AGH - 67133752U, // AGHI - 1107321434U, // AGHIK - 16805750U, // AGR - 1107321492U, // AGRK - 83927453U, // AGSI - 22627U, // AH - 1107324947U, // AHHHR - 1107325082U, // AHHLR - 67133740U, // AHI - 1107321428U, // AHIK - 30871U, // AHY - 50354711U, // AIH - 25333U, // AL - 18663U, // ALC - 22006U, // ALCG - 16805762U, // ALCGR - 16805341U, // ALCR - 100688143U, // ALFI - 22190U, // ALG - 21284U, // ALGF - 100688115U, // ALGFI - 16805681U, // ALGFR - 1107321441U, // ALGHSIK - 16805794U, // ALGR - 1107321498U, // ALGRK - 83927459U, // ALGSI - 1107324954U, // ALHHHR - 1107325089U, // ALHHLR - 1107321450U, // ALHSIK - 16806010U, // ALR - 1107321542U, // ALRK - 83927510U, // ALSI - 50354776U, // ALSIH - 50358418U, // ALSIHN - 30929U, // ALY - 117500432U, // AP - 16804837U, // AR - 1107321487U, // ARK - 83927448U, // ASI - 30614U, // AU - 16806613U, // AUR - 30705U, // AW - 16806629U, // AWR - 16805219U, // AXBR - 16806639U, // AXR - 1107325529U, // AXTR - 1107312994U, // AXTRA - 30800U, // AY - 65971U, // B - 33583219U, // BAKR - 134243065U, // BAL - 33583225U, // BALR - 134247259U, // BAS - 33583387U, // BASR - 33581165U, // BASSM - 68087U, // BAsmE - 71804U, // BAsmH - 68217U, // BAsmHE - 74502U, // BAsmL - 69053U, // BAsmLE - 72358U, // BAsmLH - 75526U, // BAsmM - 69792U, // BAsmNE - 73228U, // BAsmNH - 68461U, // BAsmNHE - 74853U, // BAsmNL - 69300U, // BAsmNLE - 72653U, // BAsmNLH - 75675U, // BAsmNM - 76101U, // BAsmNO - 76473U, // BAsmNP - 80282U, // BAsmNZ - 75984U, // BAsmO - 76318U, // BAsmP - 80167U, // BAsmZ - 621613U, // BC - 1149082U, // BCAsm - 1670189U, // BCR - 153202129U, // BCRAsm - 30326U, // BCT - 22475U, // BCTG - 16805855U, // BCTGR - 16806189U, // BCTR - 73919U, // BI - 68933U, // BIAsmE - 72223U, // BIAsmH - 68360U, // BIAsmHE - 74698U, // BIAsmL - 69193U, // BIAsmLE - 72499U, // BIAsmLH - 75619U, // BIAsmM - 69918U, // BIAsmNE - 73347U, // BIAsmNH - 68595U, // BIAsmNHE - 74972U, // BIAsmNL - 69434U, // BIAsmNLE - 72787U, // BIAsmNLH - 75737U, // BIAsmNM - 76163U, // BIAsmNO - 76535U, // BIAsmNP - 80344U, // BIAsmNZ - 76038U, // BIAsmO - 76422U, // BIAsmP - 80228U, // BIAsmZ - 621737U, // BIC - 1149126U, // BICAsm - 2317986625U, // BPP - 3391728483U, // BPRP - 3173379U, // BR - 184578918U, // BRAS - 184575582U, // BRASL - 3174014U, // BRAsmE - 3174393U, // BRAsmH - 3174062U, // BRAsmHE - 3174527U, // BRAsmL - 3174081U, // BRAsmLE - 3174456U, // BRAsmLH - 3174640U, // BRAsmM - 3174099U, // BRAsmNE - 3174475U, // BRAsmNH - 3174068U, // BRAsmNHE - 3174596U, // BRAsmNL - 3174087U, // BRAsmNLE - 3174468U, // BRAsmNLH - 3174645U, // BRAsmNM - 3174661U, // BRAsmNO - 3174677U, // BRAsmNP - 3175253U, // BRAsmNZ - 3174656U, // BRAsmO - 3174667U, // BRAsmP - 3175248U, // BRAsmZ - 201948354U, // BRC - 153717047U, // BRCAsm - 201948293U, // BRCL - 153723733U, // BRCLAsm - 201356931U, // BRCT - 201349088U, // BRCTG - 201351128U, // BRCTH - 1090543724U, // BRXH - 1090541188U, // BRXHG - 1090539666U, // BRXLE - 1090541341U, // BRXLG - 33571219U, // BSA - 33576858U, // BSG - 33581139U, // BSM - 1090543713U, // BXH - 1090541182U, // BXHG - 1090539660U, // BXLE - 1090541109U, // BXLEG - 134236295U, // C - 134236532U, // CD - 134234659U, // CDB - 33582088U, // CDBR - 33582339U, // CDFBR - 218120388U, // CDFBRA - 33582858U, // CDFR - 218132967U, // CDFTR - 33582384U, // CDGBR - 218120412U, // CDGBRA - 33582992U, // CDGR - 33583621U, // CDGTR - 218120530U, // CDGTRA - 218131729U, // CDLFBR - 218132974U, // CDLFTR - 218131774U, // CDLGBR - 218133004U, // CDLGTR - 234911491U, // CDPT - 33582588U, // CDR - 1090548978U, // CDS - 1090541476U, // CDSG - 33583669U, // CDSTR - 1090550035U, // CDSY - 33583453U, // CDTR - 33583690U, // CDUTR - 234911626U, // CDZT - 134236726U, // CE - 134235081U, // CEB - 33582220U, // CEBR - 33583465U, // CEDTR - 33582346U, // CEFBR - 218120396U, // CEFBRA - 33582878U, // CEFR - 33582391U, // CEGBR - 218120420U, // CEGBRA - 33583004U, // CEGR - 218131737U, // CELFBR - 218131782U, // CELGBR - 33582724U, // CER - 33583724U, // CEXTR - 3180720U, // CFC - 218131483U, // CFDBR - 218120340U, // CFDBRA - 218131987U, // CFDR - 218132869U, // CFDTR - 218131623U, // CFEBR - 218120364U, // CFEBRA - 218132130U, // CFER - 251683042U, // CFI - 218131838U, // CFXBR - 218120452U, // CFXBRA - 218133254U, // CFXR - 218133121U, // CFXTR - 134239717U, // CG - 218131498U, // CGDBR - 218120348U, // CGDBRA - 218131993U, // CGDR - 218132884U, // CGDTR - 218120508U, // CGDTRA - 218131638U, // CGEBR - 218120372U, // CGEBRA - 218132136U, // CGER - 134239000U, // CGF - 251683053U, // CGFI - 33582891U, // CGFR - 268461514U, // CGFRL - 134240617U, // CGH - 285237568U, // CGHI - 268461574U, // CGHRL - 67150264U, // CGHSI - 305789999U, // CGIB - 1392526511U, // CGIBAsm - 2466269691U, // CGIBAsmE - 2466273408U, // CGIBAsmH - 2466269822U, // CGIBAsmHE - 2466276106U, // CGIBAsmL - 2466270658U, // CGIBAsmLE - 2466273963U, // CGIBAsmLH - 2466271397U, // CGIBAsmNE - 2466274833U, // CGIBAsmNH - 2466270067U, // CGIBAsmNHE - 2466276458U, // CGIBAsmNL - 2466270906U, // CGIBAsmNLE - 2466274259U, // CGIBAsmNLH - 339344580U, // CGIJ - 1392534010U, // CGIJAsm - 3540012399U, // CGIJAsmE - 3540015717U, // CGIJAsmH - 3540011826U, // CGIJAsmHE - 3540018159U, // CGIJAsmL - 3540012659U, // CGIJAsmLE - 3540015990U, // CGIJAsmLH - 3540013384U, // CGIJAsmNE - 3540016813U, // CGIJAsmNH - 3540012066U, // CGIJAsmNHE - 3540018438U, // CGIJAsmNL - 3540012905U, // CGIJAsmNLE - 3540016258U, // CGIJAsmNLH - 4324667U, // CGIT - 1358984917U, // CGITAsm - 285233731U, // CGITAsmE - 285237236U, // CGITAsmH - 285232397U, // CGITAsmHE - 285238957U, // CGITAsmL - 285233236U, // CGITAsmLE - 285236625U, // CGITAsmLH - 285233594U, // CGITAsmNE - 285237023U, // CGITAsmNH - 285232283U, // CGITAsmNHE - 285238648U, // CGITAsmNL - 285233122U, // CGITAsmNLE - 285236482U, // CGITAsmNLH - 33582980U, // CGR - 3391224909U, // CGRB - 1107314075U, // CGRBAsm - 1107315223U, // CGRBAsmE - 1107318945U, // CGRBAsmH - 1107315358U, // CGRBAsmHE - 1107321638U, // CGRBAsmL - 1107316194U, // CGRBAsmLE - 1107319499U, // CGRBAsmLH - 1107316933U, // CGRBAsmNE - 1107320369U, // CGRBAsmNH - 1107315607U, // CGRBAsmNHE - 1107321994U, // CGRBAsmNL - 1107316446U, // CGRBAsmNLE - 1107319799U, // CGRBAsmNLH - 169999576U, // CGRJ - 1107321362U, // CGRJAsm - 1107316107U, // CGRJAsmE - 1107319425U, // CGRJAsmH - 1107315538U, // CGRJAsmHE - 1107321867U, // CGRJAsmL - 1107316371U, // CGRJAsmLE - 1107319702U, // CGRJAsmLH - 1107317096U, // CGRJAsmNE - 1107320525U, // CGRJAsmNH - 1107315782U, // CGRJAsmNHE - 1107322150U, // CGRJAsmNL - 1107316621U, // CGRJAsmNLE - 1107319974U, // CGRJAsmNLH - 268461539U, // CGRL - 153222482U, // CGRT - 1107326751U, // CGRTAsm - 33575524U, // CGRTAsmE - 33579023U, // CGRTAsmH - 33574188U, // CGRTAsmHE - 33580744U, // CGRTAsmL - 33575027U, // CGRTAsmLE - 33578416U, // CGRTAsmLH - 33575385U, // CGRTAsmNE - 33578814U, // CGRTAsmNH - 33574078U, // CGRTAsmNHE - 33580439U, // CGRTAsmNL - 33574917U, // CGRTAsmNLE - 33578277U, // CGRTAsmNLH - 218131853U, // CGXBR - 218120460U, // CGXBRA - 218133260U, // CGXR - 218133136U, // CGXTR - 218120560U, // CGXTRA - 134240442U, // CH - 134239092U, // CHF - 33583117U, // CHHR - 67150279U, // CHHSI - 285237555U, // CHI - 33583252U, // CHLR - 268461559U, // CHRL - 67150250U, // CHSI - 134248604U, // CHY - 305789995U, // CIB - 1392526499U, // CIBAsm - 2466269685U, // CIBAsmE - 2466273402U, // CIBAsmH - 2466269815U, // CIBAsmHE - 2466276100U, // CIBAsmL - 2466270651U, // CIBAsmLE - 2466273956U, // CIBAsmLH - 2466271390U, // CIBAsmNE - 2466274826U, // CIBAsmNH - 2466270059U, // CIBAsmNHE - 2466276451U, // CIBAsmNL - 2466270898U, // CIBAsmNLE - 2466274251U, // CIBAsmNLH - 251681316U, // CIH - 339344576U, // CIJ - 1392534005U, // CIJAsm - 3540012393U, // CIJAsmE - 3540015711U, // CIJAsmH - 3540011819U, // CIJAsmHE - 3540018153U, // CIJAsmL - 3540012652U, // CIJAsmLE - 3540015983U, // CIJAsmLH - 3540013377U, // CIJAsmNE - 3540016806U, // CIJAsmNH - 3540012058U, // CIJAsmNHE - 3540018431U, // CIJAsmNL - 3540012897U, // CIJAsmNLE - 3540016250U, // CIJAsmNLH - 4324657U, // CIT - 1358984905U, // CITAsm - 285233717U, // CITAsmE - 285237222U, // CITAsmH - 285232381U, // CITAsmHE - 285238943U, // CITAsmL - 285233220U, // CITAsmLE - 285236609U, // CITAsmLH - 285233578U, // CITAsmNE - 285237007U, // CITAsmNH - 285232265U, // CITAsmNHE - 285238632U, // CITAsmNL - 285233104U, // CITAsmNLE - 285236464U, // CITAsmNLH - 33581145U, // CKSM - 134243134U, // CL - 302041324U, // CLC - 33579842U, // CLCL - 1107316219U, // CLCLE - 1107326888U, // CLCLU - 218131490U, // CLFDBR - 218132876U, // CLFDTR - 218131630U, // CLFEBR - 352362928U, // CLFHSI - 369123605U, // CLFI - 4848949U, // CLFIT - 1459648206U, // CLFITAsm - 385897019U, // CLFITAsmE - 385900524U, // CLFITAsmH - 385895684U, // CLFITAsmHE - 385902245U, // CLFITAsmL - 385896523U, // CLFITAsmLE - 385899912U, // CLFITAsmLH - 385896881U, // CLFITAsmNE - 385900310U, // CLFITAsmNH - 385895569U, // CLFITAsmNHE - 385901935U, // CLFITAsmNL - 385896408U, // CLFITAsmNLE - 385899768U, // CLFITAsmNLH - 218131845U, // CLFXBR - 218133128U, // CLFXTR - 134239933U, // CLG - 218131505U, // CLGDBR - 218132891U, // CLGDTR - 218131645U, // CLGEBR - 134239018U, // CLGF - 369123578U, // CLGFI - 33582904U, // CLGFR - 268461521U, // CLGFRL - 268461581U, // CLGHRL - 352362943U, // CLGHSI - 307362868U, // CLGIB - 1476412597U, // CLGIBAsm - 2550155778U, // CLGIBAsmE - 2550159495U, // CLGIBAsmH - 2550155910U, // CLGIBAsmHE - 2550162193U, // CLGIBAsmL - 2550156746U, // CLGIBAsmLE - 2550160051U, // CLGIBAsmLH - 2550157485U, // CLGIBAsmNE - 2550160921U, // CLGIBAsmNH - 2550156156U, // CLGIBAsmNHE - 2550162546U, // CLGIBAsmNL - 2550156995U, // CLGIBAsmNLE - 2550160348U, // CLGIBAsmNLH - 340917449U, // CLGIJ - 1476420096U, // CLGIJAsm - 3623898486U, // CLGIJAsmE - 3623901804U, // CLGIJAsmH - 3623897914U, // CLGIJAsmHE - 3623904246U, // CLGIJAsmL - 3623898747U, // CLGIJAsmLE - 3623902078U, // CLGIJAsmLH - 3623899472U, // CLGIJAsmNE - 3623902901U, // CLGIJAsmNH - 3623898155U, // CLGIJAsmNHE - 3623904526U, // CLGIJAsmNL - 3623898994U, // CLGIJAsmNLE - 3623902347U, // CLGIJAsmNLH - 4848960U, // CLGIT - 1459648219U, // CLGITAsm - 385897034U, // CLGITAsmE - 385900539U, // CLGITAsmH - 385895701U, // CLGITAsmHE - 385902260U, // CLGITAsmL - 385896540U, // CLGITAsmLE - 385899929U, // CLGITAsmLH - 385896898U, // CLGITAsmNE - 385900327U, // CLGITAsmNH - 385895588U, // CLGITAsmNHE - 385901952U, // CLGITAsmNL - 385896427U, // CLGITAsmNLE - 385899787U, // CLGITAsmNLH - 33583016U, // CLGR - 3391224914U, // CLGRB - 1107314081U, // CLGRBAsm - 1107315230U, // CLGRBAsmE - 1107318952U, // CLGRBAsmH - 1107315366U, // CLGRBAsmHE - 1107321645U, // CLGRBAsmL - 1107316202U, // CLGRBAsmLE - 1107319507U, // CLGRBAsmLH - 1107316941U, // CLGRBAsmNE - 1107320377U, // CLGRBAsmNH - 1107315616U, // CLGRBAsmNHE - 1107322002U, // CLGRBAsmNL - 1107316455U, // CLGRBAsmNLE - 1107319808U, // CLGRBAsmNLH - 169999581U, // CLGRJ - 1107321368U, // CLGRJAsm - 1107316114U, // CLGRJAsmE - 1107319432U, // CLGRJAsmH - 1107315546U, // CLGRJAsmHE - 1107321874U, // CLGRJAsmL - 1107316379U, // CLGRJAsmLE - 1107319710U, // CLGRJAsmLH - 1107317104U, // CLGRJAsmNE - 1107320533U, // CLGRJAsmNH - 1107315791U, // CLGRJAsmNHE - 1107322158U, // CLGRJAsmNL - 1107316630U, // CLGRJAsmNLE - 1107319983U, // CLGRJAsmNLH - 268461545U, // CLGRL - 153222487U, // CLGRT - 1107326757U, // CLGRTAsm - 33575531U, // CLGRTAsmE - 33579030U, // CLGRTAsmH - 33574196U, // CLGRTAsmHE - 33580751U, // CLGRTAsmL - 33575035U, // CLGRTAsmLE - 33578424U, // CLGRTAsmLH - 33575393U, // CLGRTAsmNE - 33578822U, // CLGRTAsmNH - 33574087U, // CLGRTAsmNHE - 33580447U, // CLGRTAsmNL - 33574926U, // CLGRTAsmNLE - 33578286U, // CLGRTAsmNLH - 146732U, // CLGT - 1493202621U, // CLGTAsm - 436228654U, // CLGTAsmE - 436232159U, // CLGTAsmH - 436227317U, // CLGTAsmHE - 436233880U, // CLGTAsmL - 436228156U, // CLGTAsmLE - 436231545U, // CLGTAsmLH - 436228514U, // CLGTAsmNE - 436231943U, // CLGTAsmNH - 436227200U, // CLGTAsmNHE - 436233568U, // CLGTAsmNL - 436228039U, // CLGTAsmNLE - 436231399U, // CLGTAsmNLH - 218131860U, // CLGXBR - 218133143U, // CLGXTR - 134239136U, // CLHF - 33583153U, // CLHHR - 352362958U, // CLHHSI - 33583288U, // CLHLR - 268461597U, // CLHRL - 453026168U, // CLI - 307362874U, // CLIB - 1476412604U, // CLIBAsm - 2550155786U, // CLIBAsmE - 2550159503U, // CLIBAsmH - 2550155919U, // CLIBAsmHE - 2550162201U, // CLIBAsmL - 2550156755U, // CLIBAsmLE - 2550160060U, // CLIBAsmLH - 2550157494U, // CLIBAsmNE - 2550160930U, // CLIBAsmNH - 2550156166U, // CLIBAsmNHE - 2550162555U, // CLIBAsmNL - 2550157005U, // CLIBAsmNLE - 2550160358U, // CLIBAsmNLH - 369121866U, // CLIH - 340917455U, // CLIJ - 1476420103U, // CLIJAsm - 3623898494U, // CLIJAsmE - 3623901812U, // CLIJAsmH - 3623897923U, // CLIJAsmHE - 3623904254U, // CLIJAsmL - 3623898756U, // CLIJAsmLE - 3623902087U, // CLIJAsmLH - 3623899481U, // CLIJAsmNE - 3623902910U, // CLIJAsmNH - 3623898165U, // CLIJAsmNHE - 3623904535U, // CLIJAsmNL - 3623899004U, // CLIJAsmNLE - 3623902357U, // CLIJAsmNLH - 453032118U, // CLIY - 2365613969U, // CLM - 2365611506U, // CLMH - 2365618426U, // CLMY - 33583236U, // CLR - 3391224920U, // CLRB - 1107314088U, // CLRBAsm - 1107315238U, // CLRBAsmE - 1107318960U, // CLRBAsmH - 1107315375U, // CLRBAsmHE - 1107321653U, // CLRBAsmL - 1107316211U, // CLRBAsmLE - 1107319516U, // CLRBAsmLH - 1107316950U, // CLRBAsmNE - 1107320386U, // CLRBAsmNH - 1107315626U, // CLRBAsmNHE - 1107322011U, // CLRBAsmNL - 1107316465U, // CLRBAsmNLE - 1107319818U, // CLRBAsmNLH - 169999587U, // CLRJ - 1107321375U, // CLRJAsm - 1107316122U, // CLRJAsmE - 1107319440U, // CLRJAsmH - 1107315555U, // CLRJAsmHE - 1107321882U, // CLRJAsmL - 1107316388U, // CLRJAsmLE - 1107319719U, // CLRJAsmLH - 1107317113U, // CLRJAsmNE - 1107320542U, // CLRJAsmNH - 1107315801U, // CLRJAsmNHE - 1107322167U, // CLRJAsmNL - 1107316640U, // CLRJAsmNLE - 1107319993U, // CLRJAsmNLH - 268461618U, // CLRL - 153222493U, // CLRT - 1107326764U, // CLRTAsm - 33575539U, // CLRTAsmE - 33579038U, // CLRTAsmH - 33574205U, // CLRTAsmHE - 33580759U, // CLRTAsmL - 33575044U, // CLRTAsmLE - 33578433U, // CLRTAsmLH - 33575402U, // CLRTAsmNE - 33578831U, // CLRTAsmNH - 33574097U, // CLRTAsmNHE - 33580456U, // CLRTAsmNL - 33574936U, // CLRTAsmNLE - 33578296U, // CLRTAsmNLH - 33584959U, // CLST - 146758U, // CLT - 1493202658U, // CLTAsm - 436228690U, // CLTAsmE - 436232195U, // CLTAsmH - 436227358U, // CLTAsmHE - 436233916U, // CLTAsmL - 436228197U, // CLTAsmLE - 436231586U, // CLTAsmLH - 436228555U, // CLTAsmNE - 436231984U, // CLTAsmNH - 436227246U, // CLTAsmNHE - 436233609U, // CLTAsmNL - 436228085U, // CLTAsmNLE - 436231445U, // CLTAsmNLH - 134248662U, // CLY - 33573205U, // CMPSC - 117500452U, // CP - 234911389U, // CPDT - 1090547289U, // CPSDRdd - 1090547289U, // CPSDRds - 1090547289U, // CPSDRsd - 1090547289U, // CPSDRss - 234911608U, // CPXT - 33571240U, // CPYA - 33582546U, // CR - 3391224905U, // CRB - 1107314070U, // CRBAsm - 1107315217U, // CRBAsmE - 1107318939U, // CRBAsmH - 1107315351U, // CRBAsmHE - 1107321632U, // CRBAsmL - 1107316187U, // CRBAsmLE - 1107319492U, // CRBAsmLH - 1107316926U, // CRBAsmNE - 1107320362U, // CRBAsmNH - 1107315599U, // CRBAsmNHE - 1107321987U, // CRBAsmNL - 1107316438U, // CRBAsmNLE - 1107319791U, // CRBAsmNLH - 1090540071U, // CRDTE - 1090540071U, // CRDTEOpt - 169999572U, // CRJ - 1107321357U, // CRJAsm - 1107316101U, // CRJAsmE - 1107319419U, // CRJAsmH - 1107315531U, // CRJAsmHE - 1107321861U, // CRJAsmL - 1107316364U, // CRJAsmLE - 1107319695U, // CRJAsmLH - 1107317089U, // CRJAsmNE - 1107320518U, // CRJAsmNH - 1107315774U, // CRJAsmNHE - 1107322143U, // CRJAsmNL - 1107316613U, // CRJAsmNLE - 1107319966U, // CRJAsmNLH - 268461502U, // CRL - 153222478U, // CRT - 1107326746U, // CRTAsm - 33575518U, // CRTAsmE - 33579017U, // CRTAsmH - 33574181U, // CRTAsmHE - 33580738U, // CRTAsmL - 33575020U, // CRTAsmLE - 33578409U, // CRTAsmLH - 33575378U, // CRTAsmNE - 33578807U, // CRTAsmNH - 33574070U, // CRTAsmNHE - 33580432U, // CRTAsmNL - 33574909U, // CRTAsmNLE - 33578269U, // CRTAsmNLH - 1090548974U, // CS - 15496U, // CSCH - 1107325373U, // CSDTR - 1090541471U, // CSG - 16804730U, // CSP - 16799602U, // CSPG - 1543550795U, // CSST - 1107325625U, // CSXTR - 1090550030U, // CSY - 1107312653U, // CU12 - 33570829U, // CU12Opt - 1107312665U, // CU14 - 33570841U, // CU14Opt - 1107312641U, // CU21 - 33570817U, // CU21Opt - 1107312671U, // CU24 - 33570847U, // CU24Opt - 33570823U, // CU41 - 33570835U, // CU42 - 33583570U, // CUDTR - 33575451U, // CUSE - 1107326874U, // CUTFU - 33585050U, // CUTFUOpt - 1107318025U, // CUUTF - 33576201U, // CUUTFOpt - 33583822U, // CUXTR - 18258U, // CVB - 21980U, // CVBG - 30815U, // CVBY - 134236629U, // CVD - 134239772U, // CVDG - 134248571U, // CVDY - 33582442U, // CXBR - 33582377U, // CXFBR - 218120404U, // CXFBRA - 33582960U, // CXFR - 218132990U, // CXFTR - 33582422U, // CXGBR - 218120428U, // CXGBRA - 33583091U, // CXGR - 33583651U, // CXGTR - 218120538U, // CXGTRA - 218131745U, // CXLFBR - 218132982U, // CXLFTR - 218131790U, // CXLGBR - 218133019U, // CXLGTR - 234911508U, // CXPT - 33583861U, // CXR - 33583683U, // CXSTR - 33583711U, // CXTR - 33583697U, // CXUTR - 234911632U, // CXZT - 134248550U, // CY - 234911401U, // CZDT - 234911620U, // CZXT - 18801U, // D - 18808U, // DD - 16960U, // DDB - 16804878U, // DDBR - 16805377U, // DDR - 1107325283U, // DDTR - 1107312949U, // DDTRA - 19023U, // DE - 17360U, // DEB - 16805011U, // DEBR - 16805515U, // DER - 1107318148U, // DIAG - 1107323961U, // DIDBR - 1107324101U, // DIEBR - 25443U, // DL - 22212U, // DLG - 16805806U, // DLGR - 16806025U, // DLR - 117500472U, // DP - 16805361U, // DR - 22437U, // DSG - 21324U, // DSGF - 16805723U, // DSGFR - 16805843U, // DSGR - 16805233U, // DXBR - 16806651U, // DXR - 1107325542U, // DXTR - 1107313001U, // DXTRA - 33582052U, // EAR - 1107318142U, // ECAG - 33583411U, // ECCTR - 33570901U, // ECPGA - 1543542737U, // ECTG - 302041470U, // ED - 302047870U, // EDMK - 33583472U, // EEDTR - 33583731U, // EEXTR - 3164446U, // EFPC - 3174494U, // EPAIR - 3173353U, // EPAR - 33583432U, // EPCTR - 33585171U, // EPSW - 33576508U, // EREG - 33576527U, // EREGG - 3174501U, // ESAIR - 3173359U, // ESAR - 33583556U, // ESDTR - 3162173U, // ESEA - 33571224U, // ESTA - 33583808U, // ESXTR - 3164588U, // ETND - 134248491U, // EX - 268461656U, // EXRL - 218131520U, // FIDBR - 218120356U, // FIDBRA - 33582635U, // FIDR - 218132899U, // FIDTR - 218131660U, // FIEBR - 218120380U, // FIEBRA - 33582779U, // FIER - 218131868U, // FIXBR - 218120468U, // FIXBRA - 33583890U, // FIXR - 218133151U, // FIXTR - 33583046U, // FLOGR - 33582630U, // HDR - 33582767U, // HER - 15501U, // HSCH - 3164293U, // IAC - 18631U, // IC - 18631U, // IC32 - 30821U, // IC32Y - 486565654U, // ICM - 486563280U, // ICMH - 486570221U, // ICMY - 30821U, // ICY - 1090540065U, // IDTE - 1090540065U, // IDTEOpt - 1090548087U, // IEDTR - 1090548346U, // IEXTR - 369120121U, // IIHF - 352344513U, // IIHH - 352347051U, // IIHL - 369120266U, // IILF - 352344918U, // IILH - 352347175U, // IILL - 15592U, // IPK - 3172386U, // IPM - 1107317336U, // IPTE - 1107317336U, // IPTEOpt - 33575512U, // IPTEOptOpt - 33580810U, // IRBM - 16797096U, // ISKE - 16802541U, // IVSK - 3308094U, // InsnE - 1579334303U, // InsnRI - 505608775U, // InsnRIE - 3726834366U, // InsnRIL - 2653092625U, // InsnRILU - 3726834407U, // InsnRIS - 5929684U, // InsnRR - 505592402U, // InsnRRE - 505592446U, // InsnRRF - 505608956U, // InsnRRS - 505592562U, // InsnRS - 505608797U, // InsnRSE - 505608883U, // InsnRSI - 505609010U, // InsnRSY - 2653076253U, // InsnRX - 2653092467U, // InsnRXE - 505608852U, // InsnRXF - 2653092669U, // InsnRXY - 157465310U, // InsnS - 509786793U, // InsnSI - 1583545033U, // InsnSIL - 2657286951U, // InsnSIY - 7011079U, // InsnSS - 3731028584U, // InsnSSE - 3731028617U, // InsnSSF - 205303U, // J - 200043U, // JAsmE - 203361U, // JAsmH - 199469U, // JAsmHE - 205803U, // JAsmL - 200302U, // JAsmLE - 203633U, // JAsmLH - 206729U, // JAsmM - 201027U, // JAsmNE - 204456U, // JAsmNH - 199708U, // JAsmNHE - 206081U, // JAsmNL - 200547U, // JAsmNLE - 203900U, // JAsmNLH - 206844U, // JAsmNM - 207270U, // JAsmNO - 207642U, // JAsmNP - 211451U, // JAsmNZ - 207141U, // JAsmO - 207531U, // JAsmP - 211331U, // JAsmZ - 202402U, // JG - 199282U, // JGAsmE - 203133U, // JGAsmH - 199407U, // JGAsmHE - 205704U, // JGAsmL - 200240U, // JGAsmLE - 203531U, // JGAsmLH - 206664U, // JGAsmM - 200965U, // JGAsmNE - 204394U, // JGAsmNH - 199639U, // JGAsmNHE - 206019U, // JGAsmNL - 200478U, // JGAsmNLE - 203831U, // JGAsmNLH - 206784U, // JGAsmNM - 207210U, // JGAsmNO - 207582U, // JGAsmNP - 211391U, // JGAsmNZ - 207088U, // JGAsmO - 207465U, // JGAsmP - 211278U, // JGAsmZ - 134234878U, // KDB - 33582151U, // KDBR - 33583530U, // KDTR - 134235119U, // KEB - 33582291U, // KEBR - 3361184U, // KIMD - 3361190U, // KLMD - 33580941U, // KM - 1090535547U, // KMA - 3360906U, // KMAC - 33573115U, // KMC - 1090548033U, // KMCTR - 33576078U, // KMF - 33581371U, // KMO - 33582499U, // KXBR - 33583782U, // KXTR - 134243062U, // L - 134234218U, // LA - 1107312684U, // LAA - 1107318136U, // LAAG - 1107321587U, // LAAL - 1107318444U, // LAALG - 134236650U, // LAE - 134248577U, // LAEY - 1107322617U, // LAM - 1107327200U, // LAMY - 1107323013U, // LAN - 1107318603U, // LANG - 1107323077U, // LAO - 1107318615U, // LAOG - 268461494U, // LARL - 469805940U, // LASP - 134248041U, // LAT - 1107327007U, // LAX - 1107318845U, // LAXG - 134248527U, // LAY - 134235341U, // LB - 134240406U, // LBH - 33582430U, // LBR - 1207976394U, // LCBB - 3188342U, // LCCTL - 33582087U, // LCDBR - 33582857U, // LCDFR - 33582857U, // LCDFR_32 - 33582587U, // LCDR - 33582219U, // LCEBR - 33582723U, // LCER - 33582890U, // LCGFR - 33582979U, // LCGR - 33582558U, // LCR - 1107322493U, // LCTL - 1107318543U, // LCTLG - 33582441U, // LCXBR - 33583860U, // LCXR - 134236572U, // LD - 134236750U, // LDE - 134236750U, // LDE32 - 134235087U, // LDEB - 33582226U, // LDEBR - 33582736U, // LDER - 1107325408U, // LDETR - 33582998U, // LDGR - 33582641U, // LDR - 33582641U, // LDR32 - 33582448U, // LDXBR - 218120436U, // LDXBRA - 33583866U, // LDXR - 218133093U, // LDXTR - 134248560U, // LDY - 134237623U, // LE - 33582100U, // LEDBR - 218120332U, // LEDBRA - 33582605U, // LEDR - 218132862U, // LEDTR - 33582786U, // LER - 33582455U, // LEXBR - 218120444U, // LEXBRA - 33583872U, // LEXR - 134248583U, // LEY - 3191648U, // LFAS - 134240599U, // LFH - 134248034U, // LFHAT - 3180836U, // LFPC - 134239919U, // LG - 134248028U, // LGAT - 134235208U, // LGB - 33582400U, // LGBR - 33582623U, // LGDR - 134239013U, // LGF - 251683060U, // LGFI - 33582898U, // LGFR - 268461522U, // LGFRL - 134239830U, // LGG - 134240643U, // LGH - 285237574U, // LGHI - 33583111U, // LGHR - 268461582U, // LGHRL - 33583011U, // LGR - 268461546U, // LGRL - 134236483U, // LGSC - 134240928U, // LH - 134240733U, // LHH - 285237608U, // LHI - 33583161U, // LHR - 268461598U, // LHRL - 134248609U, // LHY - 134236401U, // LLC - 134240458U, // LLCH - 33582563U, // LLCR - 134236346U, // LLGC - 33582550U, // LLGCR - 134239024U, // LLGF - 134248020U, // LLGFAT - 33582911U, // LLGFR - 268461529U, // LLGFRL - 134240170U, // LLGFSG - 134240642U, // LLGH - 33583110U, // LLGHR - 268461589U, // LLGHRL - 134248131U, // LLGT - 134248046U, // LLGTAT - 33583636U, // LLGTR - 134241202U, // LLH - 134240738U, // LLHH - 33583166U, // LLHR - 268461604U, // LLHRL - 369120127U, // LLIHF - 385898951U, // LLIHH - 385901489U, // LLIHL - 369120272U, // LLILF - 385899356U, // LLILH - 385901613U, // LLILL - 134239044U, // LLZRGF - 1107322770U, // LM - 1107315111U, // LMD - 1107318585U, // LMG - 1107320307U, // LMH - 1107327227U, // LMY - 33582163U, // LNDBR - 33582864U, // LNDFR - 33582864U, // LNDFR_32 - 33582651U, // LNDR - 33582297U, // LNEBR - 33582809U, // LNER - 33582925U, // LNGFR - 33583040U, // LNGR - 33583355U, // LNR - 33582511U, // LNXBR - 33583906U, // LNXR - 244833U, // LOC - 1543522574U, // LOCAsm - 469781056U, // LOCAsmE - 469784790U, // LOCAsmH - 469781182U, // LOCAsmHE - 469787464U, // LOCAsmL - 469782018U, // LOCAsmLE - 469785323U, // LOCAsmLH - 469788443U, // LOCAsmM - 469782750U, // LOCAsmNE - 469786186U, // LOCAsmNH - 469781427U, // LOCAsmNHE - 469787811U, // LOCAsmNL - 469782266U, // LOCAsmNLE - 469785619U, // LOCAsmNLH - 469788576U, // LOCAsmNM - 469789002U, // LOCAsmNO - 469789374U, // LOCAsmNP - 469793183U, // LOCAsmNZ - 469788884U, // LOCAsmO - 469789218U, // LOCAsmP - 469793067U, // LOCAsmZ - 244892U, // LOCFH - 1543526728U, // LOCFHAsm - 469781197U, // LOCFHAsmE - 469785008U, // LOCFHAsmH - 469781237U, // LOCFHAsmHE - 469787546U, // LOCFHAsmL - 469782070U, // LOCFHAsmLE - 469785376U, // LOCFHAsmLH - 469788498U, // LOCFHAsmM - 469782795U, // LOCFHAsmNE - 469786224U, // LOCFHAsmNH - 469781470U, // LOCFHAsmNHE - 469787849U, // LOCFHAsmNL - 469782309U, // LOCFHAsmNLE - 469785662U, // LOCFHAsmNLH - 469788614U, // LOCFHAsmNM - 469789040U, // LOCFHAsmNO - 469789412U, // LOCFHAsmNP - 469793221U, // LOCFHAsmNZ - 469788917U, // LOCFHAsmO - 469789301U, // LOCFHAsmP - 469793107U, // LOCFHAsmZ - 7601442U, // LOCFHR - 1090547710U, // LOCFHRAsm - 16798214U, // LOCFHRAsmE - 16801700U, // LOCFHRAsmH - 16796907U, // LOCFHRAsmHE - 16803325U, // LOCFHRAsmL - 16797746U, // LOCFHRAsmLE - 16801113U, // LOCFHRAsmLH - 16803914U, // LOCFHRAsmM - 16798104U, // LOCFHRAsmNE - 16801533U, // LOCFHRAsmNH - 16796789U, // LOCFHRAsmNHE - 16803158U, // LOCFHRAsmNL - 16797628U, // LOCFHRAsmNLE - 16800988U, // LOCFHRAsmNLH - 16803858U, // LOCFHRAsmNM - 16804290U, // LOCFHRAsmNO - 16804656U, // LOCFHRAsmNP - 16808465U, // LOCFHRAsmNZ - 16804339U, // LOCFHRAsmO - 16804698U, // LOCFHRAsmP - 16808490U, // LOCFHRAsmZ - 244858U, // LOCG - 1543525890U, // LOCGAsm - 469781091U, // LOCGAsmE - 469784935U, // LOCGAsmH - 469781214U, // LOCGAsmHE - 469787513U, // LOCGAsmL - 469782047U, // LOCGAsmLE - 469785338U, // LOCGAsmLH - 469788473U, // LOCGAsmM - 469782772U, // LOCGAsmNE - 469786201U, // LOCGAsmNH - 469781444U, // LOCGAsmNHE - 469787826U, // LOCGAsmNL - 469782283U, // LOCGAsmNLE - 469785636U, // LOCGAsmNLH - 469788591U, // LOCGAsmNM - 469789017U, // LOCGAsmNO - 469789389U, // LOCGAsmNP - 469793198U, // LOCGAsmNZ - 469788897U, // LOCGAsmO - 469789268U, // LOCGAsmP - 469793087U, // LOCGAsmZ - 8125618U, // LOCGHI - 1140875582U, // LOCGHIAsm - 67128658U, // LOCGHIAsmE - 67131960U, // LOCGHIAsmH - 67128087U, // LOCGHIAsmHE - 67134423U, // LOCGHIAsmL - 67128920U, // LOCGHIAsmLE - 67132226U, // LOCGHIAsmLH - 67135344U, // LOCGHIAsmM - 67129645U, // LOCGHIAsmNE - 67133074U, // LOCGHIAsmNH - 67128324U, // LOCGHIAsmNHE - 67134699U, // LOCGHIAsmNL - 67129163U, // LOCGHIAsmNLE - 67132516U, // LOCGHIAsmNLH - 67135464U, // LOCGHIAsmNM - 67135890U, // LOCGHIAsmNO - 67136262U, // LOCGHIAsmNP - 67140071U, // LOCGHIAsmNZ - 67135763U, // LOCGHIAsmO - 67136147U, // LOCGHIAsmP - 67139953U, // LOCGHIAsmZ - 7601436U, // LOCGR - 1090547593U, // LOCGRAsm - 16798206U, // LOCGRAsmE - 16801692U, // LOCGRAsmH - 16796898U, // LOCGRAsmHE - 16803297U, // LOCGRAsmL - 16797737U, // LOCGRAsmLE - 16801104U, // LOCGRAsmLH - 16803906U, // LOCGRAsmM - 16798095U, // LOCGRAsmNE - 16801524U, // LOCGRAsmNH - 16796779U, // LOCGRAsmNHE - 16803149U, // LOCGRAsmNL - 16797618U, // LOCGRAsmNLE - 16800978U, // LOCGRAsmNLH - 16803849U, // LOCGRAsmNM - 16804281U, // LOCGRAsmNO - 16804647U, // LOCGRAsmNP - 16808456U, // LOCGRAsmNZ - 16804331U, // LOCGRAsmO - 16804690U, // LOCGRAsmP - 16808482U, // LOCGRAsmZ - 8125625U, // LOCHHI - 1140875609U, // LOCHHIAsm - 67128667U, // LOCHHIAsmE - 67131969U, // LOCHHIAsmH - 67128097U, // LOCHHIAsmHE - 67134432U, // LOCHHIAsmL - 67128930U, // LOCHHIAsmLE - 67132236U, // LOCHHIAsmLH - 67135353U, // LOCHHIAsmM - 67129655U, // LOCHHIAsmNE - 67133084U, // LOCHHIAsmNH - 67128335U, // LOCHHIAsmNHE - 67134709U, // LOCHHIAsmNL - 67129174U, // LOCHHIAsmNLE - 67132527U, // LOCHHIAsmNLH - 67135474U, // LOCHHIAsmNM - 67135900U, // LOCHHIAsmNO - 67136272U, // LOCHHIAsmNP - 67140081U, // LOCHHIAsmNZ - 67135772U, // LOCHHIAsmO - 67136156U, // LOCHHIAsmP - 67139962U, // LOCHHIAsmZ - 8125612U, // LOCHI - 1140875569U, // LOCHIAsm - 67128650U, // LOCHIAsmE - 67131952U, // LOCHIAsmH - 67128078U, // LOCHIAsmHE - 67134415U, // LOCHIAsmL - 67128911U, // LOCHIAsmLE - 67132217U, // LOCHIAsmLH - 67135336U, // LOCHIAsmM - 67129636U, // LOCHIAsmNE - 67133065U, // LOCHIAsmNH - 67128314U, // LOCHIAsmNHE - 67134690U, // LOCHIAsmNL - 67129153U, // LOCHIAsmNLE - 67132506U, // LOCHIAsmNLH - 67135455U, // LOCHIAsmNM - 67135881U, // LOCHIAsmNO - 67136253U, // LOCHIAsmNP - 67140062U, // LOCHIAsmNZ - 67135755U, // LOCHIAsmO - 67136139U, // LOCHIAsmP - 67139945U, // LOCHIAsmZ - 7601431U, // LOCR - 1090547177U, // LOCRAsm - 16798199U, // LOCRAsmE - 16801685U, // LOCRAsmH - 16796890U, // LOCRAsmHE - 16803260U, // LOCRAsmL - 16797729U, // LOCRAsmLE - 16801096U, // LOCRAsmLH - 16803884U, // LOCRAsmM - 16798087U, // LOCRAsmNE - 16801516U, // LOCRAsmNH - 16796770U, // LOCRAsmNHE - 16803141U, // LOCRAsmNL - 16797609U, // LOCRAsmNLE - 16800969U, // LOCRAsmNLH - 16803841U, // LOCRAsmNM - 16804273U, // LOCRAsmNO - 16804639U, // LOCRAsmNP - 16808448U, // LOCRAsmNZ - 16804317U, // LOCRAsmO - 16804683U, // LOCRAsmP - 16808475U, // LOCRAsmZ - 3188355U, // LPCTL - 1509968306U, // LPD - 33582170U, // LPDBR - 33582871U, // LPDFR - 33582871U, // LPDFR_32 - 1509971477U, // LPDG - 33582657U, // LPDR - 33582304U, // LPEBR - 33582815U, // LPER - 33582932U, // LPGFR - 33583053U, // LPGR - 3189574U, // LPP - 134245326U, // LPQ - 33583376U, // LPR - 3192857U, // LPSW - 3183237U, // LPSWE - 1107312707U, // LPTEA - 33582518U, // LPXBR - 33583912U, // LPXR - 33583227U, // LR - 134234396U, // LRA - 134239640U, // LRAG - 134248537U, // LRAY - 33582669U, // LRDR - 33582827U, // LRER - 268461619U, // LRL - 134248422U, // LRV - 134240304U, // LRVG - 33583084U, // LRVGR - 134242388U, // LRVH - 33583839U, // LRVR - 3188362U, // LSCTL - 134248163U, // LT - 33582191U, // LTDBR - 33582191U, // LTDBRCompare - 33582688U, // LTDR - 33583563U, // LTDTR - 33582325U, // LTEBR - 33582325U, // LTEBRCompare - 33582839U, // LTER - 134240238U, // LTG - 134239064U, // LTGF - 33582953U, // LTGFR - 33583078U, // LTGR - 33583658U, // LTR - 33582538U, // LTXBR - 33582538U, // LTXBRCompare - 33583929U, // LTXR - 33583815U, // LTXTR - 33571206U, // LURA - 33576365U, // LURAG - 134236634U, // LXD - 134235054U, // LXDB - 33582198U, // LXDBR - 33582694U, // LXDR - 1107325401U, // LXDTR - 134238860U, // LXE - 134235178U, // LXEB - 33582332U, // LXEBR - 33582845U, // LXER - 33583896U, // LXR - 134248658U, // LY - 3174002U, // LZDR - 3174147U, // LZER - 134239457U, // LZRF - 134240148U, // LZRG - 3175231U, // LZXR - 26363U, // M - 1090537839U, // MAD - 1090535937U, // MADB - 1090546688U, // MADBR - 1090547183U, // MADR - 1090537968U, // MAE - 1090536386U, // MAEB - 1090546820U, // MAEBR - 1090547320U, // MAER - 1090549844U, // MAY - 1090543730U, // MAYH - 1090547793U, // MAYHR - 1090545390U, // MAYL - 1090547939U, // MAYLR - 1090548549U, // MAYR - 453019900U, // MC - 18850U, // MD - 17164U, // MDB - 16804941U, // MDBR - 19027U, // MDE - 17372U, // MDEB - 16805017U, // MDEBR - 16805526U, // MDER - 16805430U, // MDR - 1107325360U, // MDTR - 1107312964U, // MDTRA - 20634U, // ME - 19038U, // MEE - 17385U, // MEEB - 16805024U, // MEEBR - 16805532U, // MEER - 16805582U, // MER - 30866U, // MFY - 22311U, // MG - 22923U, // MGH - 67133772U, // MGHI - 1107321512U, // MGRK - 24018U, // MH - 67133805U, // MHI - 30886U, // MHY - 25695U, // ML - 22246U, // MLG - 16805812U, // MLGR - 16806079U, // MLR - 117500597U, // MP - 16806129U, // MR - 30259U, // MS - 18768U, // MSC - 3184875U, // MSCH - 1090537930U, // MSD - 1090536316U, // MSDB - 1090546792U, // MSDBR - 1090547283U, // MSDR - 1090540054U, // MSE - 1090536477U, // MSEB - 1090546926U, // MSEBR - 1090547441U, // MSER - 50356513U, // MSFI - 22465U, // MSG - 18624U, // MSGC - 21330U, // MSGF - 50356488U, // MSGFI - 16805730U, // MSGFR - 16805849U, // MSGR - 1107314904U, // MSGRKC - 16806184U, // MSR - 1107314912U, // MSRKC - 3162526U, // MSTA - 31001U, // MSY - 302041441U, // MVC - 469803592U, // MVCDK - 302049434U, // MVCIN - 270914U, // MVCK - 33579867U, // MVCL - 1107316241U, // MVCLE - 1107326895U, // MVCLU - 1543550526U, // MVCOS - 272943U, // MVCP - 275692U, // MVCS - 469803750U, // MVCSK - 67150162U, // MVGHI - 67150177U, // MVHHI - 67150194U, // MVHI - 453026284U, // MVI - 453032134U, // MVIY - 302049472U, // MVN - 117500425U, // MVO - 33576824U, // MVPG - 33584977U, // MVST - 302053945U, // MVZ - 16805289U, // MXBR - 18911U, // MXD - 17332U, // MXDB - 16804989U, // MXDBR - 16805484U, // MXDR - 16806685U, // MXR - 1107325612U, // MXTR - 1107313016U, // MXTRA - 1107327202U, // MY - 1107320952U, // MYH - 1107325016U, // MYHR - 1107322612U, // MYL - 1107325162U, // MYLR - 1107325771U, // MYR - 26759U, // N - 302041349U, // NC - 22349U, // NG - 16805825U, // NGR - 1107321518U, // NGRK - 453026173U, // NI - 8495285U, // NIAI - 100684678U, // NIHF - 352344526U, // NIHH - 352347064U, // NIHL - 100684823U, // NILF - 352344931U, // NILH - 352347188U, // NILL - 453032124U, // NIY - 16806140U, // NR - 1107321554U, // NRK - 134240243U, // NTSTG - 30982U, // NY - 26823U, // O - 302041359U, // OC - 22361U, // OG - 16805832U, // OGR - 1107321524U, // OGRK - 453026177U, // OI - 100684684U, // OIHF - 352344532U, // OIHH - 352347070U, // OIHL - 100684829U, // OILF - 352344937U, // OILH - 352347194U, // OILL - 453032129U, // OIY - 16806145U, // OR - 1107321559U, // ORK - 30986U, // OY - 117498417U, // PACK - 15423U, // PALB - 3180832U, // PC - 15453U, // PCC - 15623U, // PCKMO - 1149314U, // PFD - 153724355U, // PFDRL - 3363962U, // PFMF - 15629U, // PFPO - 33581225U, // PGIN - 33584989U, // PGOUT - 520126558U, // PKA - 520140707U, // PKU - 1509976374U, // PLO - 33584878U, // POPCNT - 1107312775U, // PPA - 33581483U, // PPNO - 15657U, // PR - 33581516U, // PRNO - 33584901U, // PT - 3167492U, // PTF - 15471U, // PTFF - 33579495U, // PTI - 15428U, // PTLB - 1107325270U, // QADTR - 1107325528U, // QAXTR - 3187089U, // QCTRI - 3187164U, // QSI - 15634U, // RCHP - 1090540991U, // RISBG - 1090540991U, // RISBG32 - 1090545802U, // RISBGN - 1090541161U, // RISBHG - 1090541235U, // RISBLG - 1107321935U, // RLL - 1107318490U, // RLLG - 1090540998U, // RNSBG - 1090541005U, // ROSBG - 3189582U, // RP - 33573421U, // RRBE - 33580816U, // RRBM - 1107325366U, // RRDTR - 1107325618U, // RRXTR - 15506U, // RSCH - 1090541012U, // RXSBG - 29533U, // S - 3180688U, // SAC - 3183270U, // SACF - 15596U, // SAL - 15336U, // SAM24 - 15324U, // SAM31 - 15342U, // SAM64 - 33582064U, // SAR - 33583418U, // SCCTR - 15618U, // SCHM - 3187255U, // SCK - 3180747U, // SCKC - 15476U, // SCKPF - 18891U, // SD - 17262U, // SDB - 16804969U, // SDBR - 16805460U, // SDR - 1107325374U, // SDTR - 1107312971U, // SDTRA - 21015U, // SE - 17438U, // SEB - 16805103U, // SEBR - 16805618U, // SER - 3174689U, // SFASR - 3164458U, // SFPC - 22427U, // SG - 21325U, // SGF - 16805724U, // SGFR - 22928U, // SGH - 16805844U, // SGR - 1107321530U, // SGRK - 24510U, // SH - 1107324970U, // SHHHR - 1107325105U, // SHHLR - 30891U, // SHY - 3181924U, // SIE - 3178575U, // SIGA - 1107323491U, // SIGP - 26209U, // SL - 469778537U, // SLA - 1107318154U, // SLAG - 1107321381U, // SLAK - 17699U, // SLB - 21945U, // SLBG - 16805755U, // SLBGR - 16805213U, // SLBR - 469778481U, // SLDA - 469787489U, // SLDL - 1107326615U, // SLDT - 100688155U, // SLFI - 22275U, // SLG - 21302U, // SLGF - 100688129U, // SLGFI - 16805702U, // SLGFR - 16805818U, // SLGR - 1107321505U, // SLGRK - 1107324962U, // SLHHHR - 1107325097U, // SLHHLR - 469787732U, // SLL - 1107318496U, // SLLG - 1107321458U, // SLLK - 16806105U, // SLR - 1107321548U, // SLRK - 1107326834U, // SLXT - 30939U, // SLY - 117500790U, // SP - 33583439U, // SPCTR - 3178595U, // SPKA - 3172391U, // SPM - 3192585U, // SPT - 3192889U, // SPX - 134236599U, // SQD - 134234974U, // SQDB - 33582177U, // SQDBR - 33582663U, // SQDR - 134238706U, // SQE - 134235159U, // SQEB - 33582311U, // SQEBR - 33582821U, // SQER - 33582525U, // SQXBR - 33583918U, // SQXR - 16806173U, // SR - 469778723U, // SRA - 1107318176U, // SRAG - 1107321387U, // SRAK - 469778487U, // SRDA - 469787495U, // SRDL - 1107326627U, // SRDT - 1107321564U, // SRK - 469788230U, // SRL - 1107318523U, // SRLG - 1107321464U, // SRLK - 3188764U, // SRNM - 3179850U, // SRNMB - 3192551U, // SRNMT - 1375791978U, // SRP - 33584965U, // SRST - 33585082U, // SRSTU - 1107326846U, // SRXT - 3174508U, // SSAIR - 3173365U, // SSAR - 3184881U, // SSCH - 1107316142U, // SSKE - 33574318U, // SSKEOpt - 3188847U, // SSM - 134248257U, // ST - 1107322622U, // STAM - 1107327206U, // STAMY - 3189262U, // STAP - 134236508U, // STC - 134240510U, // STCH - 3187260U, // STCK - 3180753U, // STCKC - 3181985U, // STCKE - 3183584U, // STCKF - 2365613864U, // STCM - 2365611478U, // STCMH - 2365618419U, // STCMY - 3192389U, // STCPS - 3192844U, // STCRW - 1107318759U, // STCTG - 1107322513U, // STCTL - 134248554U, // STCY - 134236623U, // STD - 134248565U, // STDY - 134238848U, // STE - 134248588U, // STEY - 134240604U, // STFH - 3187571U, // STFL - 3182104U, // STFLE - 3180848U, // STFPC - 134240245U, // STG - 268461552U, // STGRL - 134236489U, // STGSC - 134242341U, // STH - 134240785U, // STHH - 268461611U, // STHRL - 134248624U, // STHY - 3189301U, // STIDP - 1107322997U, // STM - 1107318590U, // STMG - 1107320312U, // STMH - 1107327232U, // STMY - 453027935U, // STNSM - 157547621U, // STOC - 1509968147U, // STOCAsm - 436226630U, // STOCAsmE - 436230364U, // STOCAsmH - 436226757U, // STOCAsmHE - 436233038U, // STOCAsmL - 436227593U, // STOCAsmLE - 436230898U, // STOCAsmLH - 436234017U, // STOCAsmM - 436228325U, // STOCAsmNE - 436231761U, // STOCAsmNH - 436227003U, // STOCAsmNHE - 436233386U, // STOCAsmNL - 436227842U, // STOCAsmNLE - 436231195U, // STOCAsmNLH - 436234151U, // STOCAsmNM - 436234577U, // STOCAsmNO - 436234949U, // STOCAsmNP - 436238758U, // STOCAsmNZ - 436234458U, // STOCAsmO - 436234792U, // STOCAsmP - 436238641U, // STOCAsmZ - 157547682U, // STOCFH - 1509972303U, // STOCFHAsm - 436226773U, // STOCFHAsmE - 436230584U, // STOCFHAsmH - 436226814U, // STOCFHAsmHE - 436233122U, // STOCFHAsmL - 436227647U, // STOCFHAsmLE - 436230953U, // STOCFHAsmLH - 436234074U, // STOCFHAsmM - 436228372U, // STOCFHAsmNE - 436231801U, // STOCFHAsmNH - 436227048U, // STOCFHAsmNHE - 436233426U, // STOCFHAsmNL - 436227887U, // STOCFHAsmNLE - 436231240U, // STOCFHAsmNLH - 436234191U, // STOCFHAsmNM - 436234617U, // STOCFHAsmNO - 436234989U, // STOCFHAsmNP - 436238798U, // STOCFHAsmNZ - 436234493U, // STOCFHAsmO - 436234877U, // STOCFHAsmP - 436238683U, // STOCFHAsmZ - 157547647U, // STOCG - 1509971464U, // STOCGAsm - 436226666U, // STOCGAsmE - 436230510U, // STOCGAsmH - 436226790U, // STOCGAsmHE - 436233088U, // STOCGAsmL - 436227623U, // STOCGAsmLE - 436230914U, // STOCGAsmLH - 436234048U, // STOCGAsmM - 436228348U, // STOCGAsmNE - 436231777U, // STOCGAsmNH - 436227021U, // STOCGAsmNHE - 436233402U, // STOCGAsmNL - 436227860U, // STOCGAsmNLE - 436231213U, // STOCGAsmNLH - 436234167U, // STOCGAsmNM - 436234593U, // STOCGAsmNO - 436234965U, // STOCGAsmNP - 436238774U, // STOCGAsmNZ - 436234472U, // STOCGAsmO - 436234843U, // STOCGAsmP - 436238662U, // STOCGAsmZ - 453027942U, // STOSM - 134245331U, // STPQ - 3192590U, // STPT - 3192894U, // STPX - 469800358U, // STRAG - 268461650U, // STRL - 134248427U, // STRV - 134240310U, // STRVG - 134242394U, // STRVH - 3184887U, // STSCH - 3187169U, // STSI - 33571212U, // STURA - 33576845U, // STURG - 134248734U, // STY - 30646U, // SU - 16806618U, // SUR - 280934U, // SVC - 30741U, // SW - 16806634U, // SWR - 16805316U, // SXBR - 16806708U, // SXR - 1107325626U, // SXTR - 1107313023U, // SXTRA - 30991U, // SY - 3192626U, // TABORT - 15614U, // TAM - 33582075U, // TAR - 33572676U, // TB - 218131957U, // TBDR - 218131974U, // TBEDR - 352364705U, // TBEGIN - 352356608U, // TBEGINC - 134234680U, // TCDB - 134235080U, // TCEB - 134236063U, // TCXB - 134248073U, // TDCDT - 134248111U, // TDCET - 134248292U, // TDCXT - 134248080U, // TDGDT - 134248118U, // TDGET - 134248299U, // TDGXT - 15466U, // TEND - 33582729U, // THDER - 33582629U, // THDR - 453027958U, // TM - 385898999U, // TMHH - 385901508U, // TMHL - 385899455U, // TMLH - 385901632U, // TMLL - 453032193U, // TMY - 3206027U, // TP - 3187084U, // TPI - 469808886U, // TPROT - 302051631U, // TR - 1107315251U, // TRACE - 1107318242U, // TRACG - 15330U, // TRAP2 - 3178533U, // TRAP4 - 33575441U, // TRE - 1107323351U, // TROO - 33581527U, // TROOOpt - 1107326717U, // TROT - 33584893U, // TROTOpt - 302053178U, // TRT - 419648122U, // TRTE - 3363450U, // TRTEOpt - 1107323395U, // TRTO - 33581571U, // TRTOOpt - 302051887U, // TRTR - 419648015U, // TRTRE - 3363343U, // TRTREOpt - 1107326807U, // TRTT - 33584983U, // TRTTOpt - 3192396U, // TS - 3184888U, // TSCH - 117498500U, // UNPK - 302039132U, // UNPKA - 302053281U, // UNPKU - 15690U, // UPT - 1107313060U, // VA - 1107313093U, // VAB - 1107314837U, // VAC - 1107314846U, // VACC - 1107313110U, // VACCB - 1107314852U, // VACCC - 1107323809U, // VACCCQ - 1107317420U, // VACCF - 1107318249U, // VACCG - 1107318967U, // VACCH - 1107323802U, // VACCQ - 1107323796U, // VACQ - 1107317409U, // VAF - 1107318196U, // VAG - 1107318901U, // VAH - 1107323412U, // VAP - 1107323791U, // VAQ - 1107318787U, // VAVG - 1107313749U, // VAVGB - 1107317598U, // VAVGF - 1107318363U, // VAVGG - 1107319189U, // VAVGH - 1107321741U, // VAVGL - 1107313880U, // VAVGLB - 1107317755U, // VAVGLF - 1107318473U, // VAVGLG - 1107319569U, // VAVGLH - 1107322931U, // VBPERM - 1107318287U, // VCDG - 1107313712U, // VCDGB - 1107318466U, // VCDLG - 1107313733U, // VCDLGB - 1107323817U, // VCEQ - 1107314063U, // VCEQB - 1107325965U, // VCEQBS - 1107317962U, // VCEQF - 1107326248U, // VCEQFS - 1107318654U, // VCEQG - 1107326340U, // VCEQGS - 1107320718U, // VCEQH - 1107326414U, // VCEQHS - 1107315084U, // VCGD - 1107313310U, // VCGDB - 1107319044U, // VCH - 1107313770U, // VCHB - 1107325950U, // VCHBS - 1107317619U, // VCHF - 1107326233U, // VCHFS - 1107318385U, // VCHG - 1107326325U, // VCHGS - 1107319210U, // VCHH - 1107326399U, // VCHHS - 1107321748U, // VCHL - 1107313888U, // VCHLB - 1107325957U, // VCHLBS - 1107317763U, // VCHLF - 1107326240U, // VCHLFS - 1107318481U, // VCHLG - 1107326332U, // VCHLGS - 1107319577U, // VCHLH - 1107326406U, // VCHLHS - 1107322968U, // VCKSM - 1107315090U, // VCLGD - 1107313324U, // VCLGDB - 1107327380U, // VCLZ - 33572983U, // VCLZB - 33576298U, // VCLZF - 33577041U, // VCLZG - 33579175U, // VCLZH - 1107323440U, // VCP - 1107327539U, // VCTZ - 33572990U, // VCTZB - 33576305U, // VCTZF - 33577048U, // VCTZG - 33579182U, // VCTZH - 1107314513U, // VCVB - 1107318235U, // VCVBG - 1107315156U, // VCVD - 1107318299U, // VCVDG - 1107323458U, // VDP - 1107314859U, // VEC - 33571293U, // VECB - 33575603U, // VECF - 33576432U, // VECG - 33577150U, // VECH - 1107321660U, // VECL - 33572049U, // VECLB - 33575924U, // VECLF - 33576635U, // VECLG - 33577700U, // VECLH - 1090545538U, // VERIM - 1090536770U, // VERIMB - 1090540678U, // VERIMF - 1090541361U, // VERIMG - 1090543082U, // VERIMH - 1107321933U, // VERLL - 1107313903U, // VERLLB - 1107317809U, // VERLLF - 1107318488U, // VERLLG - 1107319735U, // VERLLH - 1107326927U, // VERLLV - 1107314526U, // VERLLVB - 1107318048U, // VERLLVF - 1107318800U, // VERLLVG - 1107320890U, // VERLLVH - 1107322469U, // VESL - 1107313953U, // VESLB - 1107317852U, // VESLF - 1107318529U, // VESLG - 1107320178U, // VESLH - 1107326943U, // VESLV - 1107314544U, // VESLVB - 1107318066U, // VESLVF - 1107318818U, // VESLVG - 1107320908U, // VESLVH - 1107312929U, // VESRA - 1107313078U, // VESRAB - 1107317401U, // VESRAF - 1107318174U, // VESRAG - 1107318893U, // VESRAH - 1107326913U, // VESRAV - 1107314504U, // VESRAVB - 1107318032U, // VESRAVF - 1107318778U, // VESRAVG - 1107320874U, // VESRAVH - 1107322436U, // VESRL - 1107313938U, // VESRLB - 1107317844U, // VESRLF - 1107318521U, // VESRLG - 1107320170U, // VESRLH - 1107326935U, // VESRLV - 1107314535U, // VESRLVB - 1107318057U, // VESRLVF - 1107318809U, // VESRLVG - 1107320899U, // VESRLVH - 1107312714U, // VFA - 1107313137U, // VFADB - 1107315172U, // VFAE - 1107313594U, // VFAEB - 1107325925U, // VFAEBS - 1107317447U, // VFAEF - 1107326208U, // VFAEFS - 1107319049U, // VFAEH - 1107326374U, // VFAEHS - 1107314774U, // VFAEZB - 1107326160U, // VFAEZBS - 1107318089U, // VFAEZF - 1107326297U, // VFAEZFS - 1107320966U, // VFAEZH - 1107326458U, // VFAEZHS - 1107314102U, // VFASB - 1107315258U, // VFCE - 1107313228U, // VFCEDB - 1107325813U, // VFCEDBS - 1107314187U, // VFCESB - 1107325982U, // VFCESBS - 1107318980U, // VFCH - 1107313340U, // VFCHDB - 1107325889U, // VFCHDBS - 1107315383U, // VFCHE - 1107313244U, // VFCHEDB - 1107325831U, // VFCHEDBS - 1107314203U, // VFCHESB - 1107326000U, // VFCHESBS - 1107314255U, // VFCHSB - 1107326058U, // VFCHSBS - 1107315079U, // VFD - 1107313214U, // VFDDB - 1107314173U, // VFDSB - 1107315288U, // VFEE - 1107313634U, // VFEEB - 1107325933U, // VFEEBS - 1107317468U, // VFEEF - 1107326216U, // VFEEFS - 1107319063U, // VFEEH - 1107326382U, // VFEEHS - 1107314782U, // VFEEZB - 1107326169U, // VFEEZBS - 1107318097U, // VFEEZF - 1107326306U, // VFEEZFS - 1107320974U, // VFEEZH - 1107326467U, // VFEEZHS - 1107316973U, // VFENE - 1107313679U, // VFENEB - 1107325941U, // VFENEBS - 1107317508U, // VFENEF - 1107326224U, // VFENEFS - 1107319097U, // VFENEH - 1107326390U, // VFENEHS - 1107314798U, // VFENEZB - 1107326178U, // VFENEZBS - 1107318113U, // VFENEZF - 1107326315U, // VFENEZFS - 1107320990U, // VFENEZH - 1107326476U, // VFENEZHS - 1107321127U, // VFI - 1107313390U, // VFIDB - 1107314305U, // VFISB - 1107313280U, // VFKEDB - 1107325871U, // VFKEDBS - 1107314239U, // VFKESB - 1107326040U, // VFKESBS - 1107313356U, // VFKHDB - 1107325907U, // VFKHDBS - 1107313262U, // VFKHEDB - 1107325851U, // VFKHEDBS - 1107314221U, // VFKHESB - 1107326020U, // VFKHESBS - 1107314271U, // VFKHSB - 1107326076U, // VFKHSBS - 33571368U, // VFLCDB - 33572333U, // VFLCSB - 1107321889U, // VFLL - 33584675U, // VFLLS - 33571626U, // VFLNDB - 33572534U, // VFLNSB - 33571660U, // VFLPDB - 33572568U, // VFLPSB - 1107325070U, // VFLR - 1107315132U, // VFLRD - 1107322676U, // VFM - 1107312757U, // VFMA - 1107313151U, // VFMADB - 1107314116U, // VFMASB - 1107327012U, // VFMAX - 1107313564U, // VFMAXDB - 1107314477U, // VFMAXSB - 1107313418U, // VFMDB - 1107323055U, // VFMIN - 1107313432U, // VFMINDB - 1107314340U, // VFMINSB - 1107326513U, // VFMS - 1107314326U, // VFMSB - 1107313530U, // VFMSDB - 1107314438U, // VFMSSB - 1107312768U, // VFNMA - 1107313167U, // VFNMADB - 1107314132U, // VFNMASB - 1107326519U, // VFNMS - 1107313546U, // VFNMSDB - 1107314454U, // VFNMSSB - 1107323388U, // VFPSO - 1107313466U, // VFPSODB - 1107314374U, // VFPSOSB - 1107326282U, // VFS - 1107313516U, // VFSDB - 1107323865U, // VFSQ - 33571676U, // VFSQDB - 33572584U, // VFSQSB - 1107314424U, // VFSSB - 1107321040U, // VFTCI - 1107313372U, // VFTCIDB - 1107314287U, // VFTCISB - 385902340U, // VGBM - 3758117603U, // VGEF - 536892969U, // VGEG - 1107322670U, // VGFM - 1107312750U, // VGFMA - 1107313070U, // VGFMAB - 1107317393U, // VGFMAF - 1107318160U, // VGFMAG - 1107318879U, // VGFMAH - 1107313973U, // VGFMB - 1107317875U, // VGFMF - 1107318564U, // VGFMG - 1107320285U, // VGFMH - 1476421453U, // VGM - 1476412732U, // VGMB - 1476416640U, // VGMF - 1476417323U, // VGMG - 1476419044U, // VGMH - 1107325500U, // VISTR - 1107314094U, // VISTRB - 33584149U, // VISTRBS - 1107317977U, // VISTRF - 33584432U, // VISTRFS - 1107320755U, // VISTRH - 33584598U, // VISTRHS - 134244068U, // VL - 1207976400U, // VLBB - 1107314934U, // VLC - 33571299U, // VLCB - 33575609U, // VLCF - 33576444U, // VLCG - 33577168U, // VLCH - 1107315277U, // VLDE - 33571790U, // VLDEB - 1073759235U, // VLEB - 1107315068U, // VLED - 1107313296U, // VLEDB - 1073763064U, // VLEF - 1073763887U, // VLEG - 1073764653U, // VLEH - 1140868264U, // VLEIB - 1140872145U, // VLEIF - 1140872851U, // VLEIG - 1140873769U, // VLEIH - 1107326921U, // VLGV - 1107314519U, // VLGVB - 1107318041U, // VLGVF - 1107318793U, // VLGVG - 1107320883U, // VLGVH - 1459645093U, // VLIP - 1107321945U, // VLL - 1207990584U, // VLLEZ - 134236262U, // VLLEZB - 134239577U, // VLLEZF - 134240329U, // VLLEZG - 134242454U, // VLLEZH - 134239338U, // VLLEZLF - 1107322774U, // VLM - 1107323567U, // VLP - 33572233U, // VLPB - 33576132U, // VLPF - 33576812U, // VLPG - 33578882U, // VLPH - 33583326U, // VLR - 1207986759U, // VLREP - 134235514U, // VLREPB - 134239413U, // VLREPF - 134240093U, // VLREPG - 134242163U, // VLREPH - 1509975608U, // VLRL - 1107325130U, // VLRLR - 1090541610U, // VLVG - 1090536540U, // VLVGB - 1090540389U, // VLVGF - 1090541154U, // VLVGG - 1090541980U, // VLVGH - 1107323502U, // VLVGP - 1107315183U, // VMAE - 1107313601U, // VMAEB - 1107317454U, // VMAEF - 1107319056U, // VMAEH - 1107318887U, // VMAH - 1107313763U, // VMAHB - 1107317612U, // VMAHF - 1107319203U, // VMAHH - 1107321598U, // VMAL - 1107313866U, // VMALB - 1107316148U, // VMALE - 1107313652U, // VMALEB - 1107317481U, // VMALEF - 1107319070U, // VMALEH - 1107317741U, // VMALF - 1107319453U, // VMALH - 1107313776U, // VMALHB - 1107317656U, // VMALHF - 1107319258U, // VMALHH - 1107326965U, // VMALHW - 1107323177U, // VMALO - 1107314021U, // VMALOB - 1107317920U, // VMALOF - 1107320670U, // VMALOH - 1107323082U, // VMAO - 1107314014U, // VMAOB - 1107317913U, // VMAOF - 1107320663U, // VMAOH - 1107316889U, // VME - 1107313673U, // VMEB - 1107317502U, // VMEF - 1107319091U, // VMEH - 1107320325U, // VMH - 1107313799U, // VMHB - 1107317685U, // VMHF - 1107319293U, // VMHH - 1107321950U, // VML - 1107313911U, // VMLB - 1107316396U, // VMLE - 1107313660U, // VMLEB - 1107317489U, // VMLEF - 1107319078U, // VMLEH - 1107317817U, // VMLF - 1107319749U, // VMLH - 1107313784U, // VMLHB - 1107317670U, // VMLHF - 1107319272U, // VMLHH - 1107326973U, // VMLHW - 1107323184U, // VMLO - 1107314029U, // VMLOB - 1107317928U, // VMLOF - 1107320678U, // VMLOH - 1107323062U, // VMN - 1107314008U, // VMNB - 1107317907U, // VMNF - 1107318609U, // VMNG - 1107320550U, // VMNH - 1107322175U, // VMNL - 1107313917U, // VMNLB - 1107317823U, // VMNLF - 1107318507U, // VMNLG - 1107320002U, // VMNLH - 1107323200U, // VMO - 1107314036U, // VMOB - 1107317935U, // VMOF - 1107320685U, // VMOH - 1107323572U, // VMP - 1107320749U, // VMRH - 1107313812U, // VMRHB - 1107317698U, // VMRHF - 1107318391U, // VMRHG - 1107319306U, // VMRHH - 1107322430U, // VMRL - 1107313931U, // VMRLB - 1107317837U, // VMRLF - 1107318514U, // VMRLG - 1107320163U, // VMRLH - 1107322475U, // VMSL - 1107318536U, // VMSLG - 1107323775U, // VMSP - 1107327023U, // VMX - 1107314684U, // VMXB - 1107318074U, // VMXF - 1107318851U, // VMXG - 1107320934U, // VMXH - 1107322600U, // VMXL - 1107313966U, // VMXLB - 1107317859U, // VMXLF - 1107318550U, // VMXLG - 1107320265U, // VMXLH - 1107323073U, // VN - 1107314953U, // VNC - 1107323067U, // VNN - 1107323346U, // VNO - 1107327028U, // VNX - 1107323402U, // VO - 1107314969U, // VOC - 3166593U, // VONE - 1107321047U, // VPDI - 1107322939U, // VPERM - 1107321482U, // VPK - 1107317735U, // VPKF - 1107318438U, // VPKG - 1107319447U, // VPKH - 1107326492U, // VPKLS - 1107317998U, // VPKLSF - 1107326273U, // VPKLSFS - 1107318713U, // VPKLSG - 1107326356U, // VPKLSGS - 1107320770U, // VPKLSH - 1107326439U, // VPKLSHS - 1107326486U, // VPKS - 1107317991U, // VPKSF - 1107326265U, // VPKSFS - 1107318706U, // VPKSG - 1107326348U, // VPKSGS - 1107320763U, // VPKSH - 1107326431U, // VPKSHS - 1509980558U, // VPKZ - 1107326587U, // VPOPCT - 33572671U, // VPOPCTB - 33576187U, // VPOPCTF - 33576919U, // VPOPCTG - 33578959U, // VPOPCTH - 1107323706U, // VPSOP - 1107323470U, // VREP - 1107314050U, // VREPB - 1107317949U, // VREPF - 1107318629U, // VREPG - 1107320699U, // VREPH - 1358979461U, // VREPI - 285230274U, // VREPIB - 285234136U, // VREPIF - 285234842U, // VREPIG - 285235792U, // VREPIH - 1107323759U, // VRP - 1107326544U, // VS - 1107314472U, // VSB - 1107321019U, // VSBCBI - 1107323823U, // VSBCBIQ - 1107321034U, // VSBI - 1107323840U, // VSBIQ - 1107321027U, // VSCBI - 1107313819U, // VSCBIB - 1107317705U, // VSCBIF - 1107318411U, // VSCBIG - 1107319324U, // VSCBIH - 1107323832U, // VSCBIQ - 2701152981U, // VSCEF - 3774895650U, // VSCEG - 1107323452U, // VSDP - 1107318338U, // VSEG - 33571902U, // VSEGB - 33575709U, // VSEGF - 33577334U, // VSEGH - 1107321709U, // VSEL - 1107318006U, // VSF - 1107318726U, // VSG - 1107320778U, // VSH - 1107322481U, // VSL - 1107313960U, // VSLB - 1107313411U, // VSLDB - 1107323781U, // VSP - 1107323871U, // VSQ - 1107312936U, // VSRA - 1107313086U, // VSRAB - 1107322443U, // VSRL - 1107313946U, // VSRLB - 1107323753U, // VSRP - 134248274U, // VST - 1207976995U, // VSTEB - 1207980812U, // VSTEF - 1207981640U, // VSTEG - 1207982401U, // VSTEH - 1107322590U, // VSTL - 1107322996U, // VSTM - 1107315004U, // VSTRC - 1107313129U, // VSTRCB - 1107325804U, // VSTRCBS - 1107317439U, // VSTRCF - 1107326199U, // VSTRCFS - 1107319011U, // VSTRCH - 1107326365U, // VSTRCHS - 1107314765U, // VSTRCZB - 1107326150U, // VSTRCZBS - 1107318080U, // VSTRCZF - 1107326287U, // VSTRCZFS - 1107320957U, // VSTRCZH - 1107326448U, // VSTRCZHS - 1509975633U, // VSTRL - 1107325137U, // VSTRLR - 1107323007U, // VSUM - 1107314001U, // VSUMB - 1107318596U, // VSUMG - 1107317564U, // VSUMGF - 1107319176U, // VSUMGH - 1107320318U, // VSUMH - 1107323847U, // VSUMQ - 1107317969U, // VSUMQF - 1107318661U, // VSUMQG - 33581178U, // VTM - 3173258U, // VTP - 1107320712U, // VUPH - 33571981U, // VUPHB - 33575867U, // VUPHF - 33577475U, // VUPHH - 1509980551U, // VUPKZ - 1107322288U, // VUPL - 33572100U, // VUPLB - 33576006U, // VUPLF - 1107320129U, // VUPLH - 33571967U, // VUPLHB - 33575853U, // VUPLHF - 33577455U, // VUPLHH - 33585156U, // VUPLHW - 1107321926U, // VUPLL - 33572071U, // VUPLLB - 33575977U, // VUPLLF - 33577903U, // VUPLLH - 1107327051U, // VX - 3172836U, // VZERO - 1107313719U, // WCDGB - 1107313741U, // WCDLGB - 1107313317U, // WCGDB - 1107313332U, // WCLGDB - 1107313144U, // WFADB - 1107314109U, // WFASB - 1107314552U, // WFAXB - 1107314869U, // WFC - 33571361U, // WFCDB - 1107313236U, // WFCEDB - 1107325822U, // WFCEDBS - 1107314195U, // WFCESB - 1107325991U, // WFCESBS - 1107314604U, // WFCEXB - 1107326094U, // WFCEXBS - 1107313348U, // WFCHDB - 1107325898U, // WFCHDBS - 1107313253U, // WFCHEDB - 1107325841U, // WFCHEDBS - 1107314212U, // WFCHESB - 1107326010U, // WFCHESBS - 1107314612U, // WFCHEXB - 1107326103U, // WFCHEXBS - 1107314263U, // WFCHSB - 1107326067U, // WFCHSBS - 1107314638U, // WFCHXB - 1107326132U, // WFCHXBS - 33572326U, // WFCSB - 33572752U, // WFCXB - 1107313221U, // WFDDB - 1107314180U, // WFDSB - 1107314597U, // WFDXB - 1107313397U, // WFIDB - 1107314312U, // WFISB - 1107314663U, // WFIXB - 1107321423U, // WFK - 33571580U, // WFKDB - 1107313288U, // WFKEDB - 1107325880U, // WFKEDBS - 1107314247U, // WFKESB - 1107326049U, // WFKESBS - 1107314630U, // WFKEXB - 1107326123U, // WFKEXBS - 1107313364U, // WFKHDB - 1107325916U, // WFKHDBS - 1107313271U, // WFKHEDB - 1107325861U, // WFKHEDBS - 1107314230U, // WFKHESB - 1107326030U, // WFKHESBS - 1107314621U, // WFKHEXB - 1107326113U, // WFKHEXBS - 1107314279U, // WFKHSB - 1107326085U, // WFKHSBS - 1107314646U, // WFKHXB - 1107326141U, // WFKHXBS - 33572495U, // WFKSB - 33572846U, // WFKXB - 33571376U, // WFLCDB - 33572341U, // WFLCSB - 33572759U, // WFLCXB - 33573273U, // WFLLD - 33584682U, // WFLLS - 33571634U, // WFLNDB - 33572542U, // WFLNSB - 33572875U, // WFLNXB - 33571668U, // WFLPDB - 33572576U, // WFLPSB - 33572892U, // WFLPXB - 1107315139U, // WFLRD - 1107327044U, // WFLRX - 1107313159U, // WFMADB - 1107314124U, // WFMASB - 1107314559U, // WFMAXB - 1107313573U, // WFMAXDB - 1107314486U, // WFMAXSB - 1107314756U, // WFMAXXB - 1107313425U, // WFMDB - 1107313441U, // WFMINDB - 1107314349U, // WFMINSB - 1107314690U, // WFMINXB - 1107314333U, // WFMSB - 1107313538U, // WFMSDB - 1107314446U, // WFMSSB - 1107314739U, // WFMSXB - 1107314677U, // WFMXB - 1107313176U, // WFNMADB - 1107314141U, // WFNMASB - 1107314567U, // WFNMAXB - 1107313555U, // WFNMSDB - 1107314463U, // WFNMSSB - 1107314747U, // WFNMSXB - 1107313475U, // WFPSODB - 1107314383U, // WFPSOSB - 1107314707U, // WFPSOXB - 1107313523U, // WFSDB - 33571684U, // WFSQDB - 33572592U, // WFSQSB - 33572900U, // WFSQXB - 1107314431U, // WFSSB - 1107314732U, // WFSXB - 1107313381U, // WFTCIDB - 1107314296U, // WFTCISB - 1107314654U, // WFTCIXB - 33571797U, // WLDEB - 1107313303U, // WLEDB - 30753U, // X - 302041451U, // XC - 22591U, // XG - 16805876U, // XGR - 1107321536U, // XGRK - 453026289U, // XI - 100684690U, // XIHF - 100684835U, // XILF - 453032140U, // XIY - 16806640U, // XR - 1107321569U, // XRK - 15511U, // XSCH - 31011U, // XY - 117500441U, // ZAP + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 15368U, // DBG_VALUE + 15378U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 15361U, // BUNDLE + 15388U, // LIFETIME_START + 15348U, // LIFETIME_END + 0U, // STACKMAP + 15600U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 15256U, // PATCHABLE_FUNCTION_ENTER + 15176U, // PATCHABLE_RET + 15302U, // PATCHABLE_FUNCTION_EXIT + 15279U, // PATCHABLE_TAIL_CALL + 15231U, // PATCHABLE_EVENT_CALL + 15207U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADJDYNALLOC + 0U, // AEXT128 + 0U, // AFIMux + 0U, // AHIMux + 0U, // AHIMuxK + 0U, // ATOMIC_CMP_SWAPW + 0U, // ATOMIC_LOADW_AFI + 0U, // ATOMIC_LOADW_AR + 0U, // ATOMIC_LOADW_MAX + 0U, // ATOMIC_LOADW_MIN + 0U, // ATOMIC_LOADW_NILH + 0U, // ATOMIC_LOADW_NILHi + 0U, // ATOMIC_LOADW_NR + 0U, // ATOMIC_LOADW_NRi + 0U, // ATOMIC_LOADW_OILH + 0U, // ATOMIC_LOADW_OR + 0U, // ATOMIC_LOADW_SR + 0U, // ATOMIC_LOADW_UMAX + 0U, // ATOMIC_LOADW_UMIN + 0U, // ATOMIC_LOADW_XILF + 0U, // ATOMIC_LOADW_XR + 0U, // ATOMIC_LOAD_AFI + 0U, // ATOMIC_LOAD_AGFI + 0U, // ATOMIC_LOAD_AGHI + 0U, // ATOMIC_LOAD_AGR + 0U, // ATOMIC_LOAD_AHI + 0U, // ATOMIC_LOAD_AR + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NGR + 0U, // ATOMIC_LOAD_NGRi + 0U, // ATOMIC_LOAD_NIHF64 + 0U, // ATOMIC_LOAD_NIHF64i + 0U, // ATOMIC_LOAD_NIHH64 + 0U, // ATOMIC_LOAD_NIHH64i + 0U, // ATOMIC_LOAD_NIHL64 + 0U, // ATOMIC_LOAD_NIHL64i + 0U, // ATOMIC_LOAD_NILF + 0U, // ATOMIC_LOAD_NILF64 + 0U, // ATOMIC_LOAD_NILF64i + 0U, // ATOMIC_LOAD_NILFi + 0U, // ATOMIC_LOAD_NILH + 0U, // ATOMIC_LOAD_NILH64 + 0U, // ATOMIC_LOAD_NILH64i + 0U, // ATOMIC_LOAD_NILHi + 0U, // ATOMIC_LOAD_NILL + 0U, // ATOMIC_LOAD_NILL64 + 0U, // ATOMIC_LOAD_NILL64i + 0U, // ATOMIC_LOAD_NILLi + 0U, // ATOMIC_LOAD_NR + 0U, // ATOMIC_LOAD_NRi + 0U, // ATOMIC_LOAD_OGR + 0U, // ATOMIC_LOAD_OIHF64 + 0U, // ATOMIC_LOAD_OIHH64 + 0U, // ATOMIC_LOAD_OIHL64 + 0U, // ATOMIC_LOAD_OILF + 0U, // ATOMIC_LOAD_OILF64 + 0U, // ATOMIC_LOAD_OILH + 0U, // ATOMIC_LOAD_OILH64 + 0U, // ATOMIC_LOAD_OILL + 0U, // ATOMIC_LOAD_OILL64 + 0U, // ATOMIC_LOAD_OR + 0U, // ATOMIC_LOAD_SGR + 0U, // ATOMIC_LOAD_SR + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XGR + 0U, // ATOMIC_LOAD_XIHF64 + 0U, // ATOMIC_LOAD_XILF + 0U, // ATOMIC_LOAD_XILF64 + 0U, // ATOMIC_LOAD_XR + 0U, // ATOMIC_SWAPW + 0U, // ATOMIC_SWAP_32 + 0U, // ATOMIC_SWAP_64 + 0U, // CFIMux + 0U, // CGIBCall + 0U, // CGIBReturn + 0U, // CGRBCall + 0U, // CGRBReturn + 0U, // CHIMux + 0U, // CIBCall + 0U, // CIBReturn + 0U, // CLCLoop + 0U, // CLCSequence + 0U, // CLFIMux + 0U, // CLGIBCall + 0U, // CLGIBReturn + 0U, // CLGRBCall + 0U, // CLGRBReturn + 0U, // CLIBCall + 0U, // CLIBReturn + 0U, // CLMux + 0U, // CLRBCall + 0U, // CLRBReturn + 0U, // CLSTLoop + 0U, // CMux + 0U, // CRBCall + 0U, // CRBReturn + 0U, // CallBASR + 0U, // CallBCR + 0U, // CallBR + 0U, // CallBRASL + 0U, // CallBRCL + 0U, // CallJG + 0U, // CondReturn + 0U, // CondStore16 + 0U, // CondStore16Inv + 0U, // CondStore16Mux + 0U, // CondStore16MuxInv + 0U, // CondStore32 + 0U, // CondStore32Inv + 0U, // CondStore32Mux + 0U, // CondStore32MuxInv + 0U, // CondStore64 + 0U, // CondStore64Inv + 0U, // CondStore8 + 0U, // CondStore8Inv + 0U, // CondStore8Mux + 0U, // CondStore8MuxInv + 0U, // CondStoreF32 + 0U, // CondStoreF32Inv + 0U, // CondStoreF64 + 0U, // CondStoreF64Inv + 0U, // CondTrap + 0U, // GOT + 0U, // IIFMux + 0U, // IIHF64 + 0U, // IIHH64 + 0U, // IIHL64 + 0U, // IIHMux + 0U, // IILF64 + 0U, // IILH64 + 0U, // IILL64 + 0U, // IILMux + 0U, // L128 + 0U, // LBMux + 0U, // LEFR + 0U, // LFER + 0U, // LHIMux + 0U, // LHMux + 0U, // LLCMux + 0U, // LLCRMux + 0U, // LLHMux + 0U, // LLHRMux + 0U, // LMux + 0U, // LOCHIMux + 0U, // LOCMux + 0U, // LOCRMux + 0U, // LRMux + 0U, // LTDBRCompare_VecPseudo + 0U, // LTEBRCompare_VecPseudo + 0U, // LTXBRCompare_VecPseudo + 0U, // LX + 0U, // MVCLoop + 0U, // MVCSequence + 0U, // MVSTLoop + 0U, // MemBarrier + 0U, // NCLoop + 0U, // NCSequence + 0U, // NIFMux + 0U, // NIHF64 + 0U, // NIHH64 + 0U, // NIHL64 + 0U, // NIHMux + 0U, // NILF64 + 0U, // NILH64 + 0U, // NILL64 + 0U, // NILMux + 0U, // OCLoop + 0U, // OCSequence + 0U, // OIFMux + 0U, // OIHF64 + 0U, // OIHH64 + 0U, // OIHL64 + 0U, // OIHMux + 0U, // OILF64 + 0U, // OILH64 + 0U, // OILL64 + 0U, // OILMux + 0U, // PAIR128 + 0U, // RISBHH + 0U, // RISBHL + 0U, // RISBLH + 0U, // RISBLL + 0U, // RISBMux + 0U, // Return + 0U, // SRSTLoop + 0U, // ST128 + 0U, // STCMux + 0U, // STHMux + 0U, // STMux + 0U, // STOCMux + 0U, // STX + 0U, // Select32 + 0U, // Select64 + 0U, // SelectF128 + 0U, // SelectF32 + 0U, // SelectF64 + 0U, // SelectVR128 + 0U, // SelectVR32 + 0U, // SelectVR64 + 0U, // Serialize + 0U, // TBEGIN_nofloat + 0U, // TLS_GDCALL + 0U, // TLS_LDCALL + 0U, // TMHH64 + 0U, // TMHL64 + 0U, // TMHMux + 0U, // TMLH64 + 0U, // TMLL64 + 0U, // TMLMux + 0U, // Trap + 0U, // VL32 + 0U, // VL64 + 0U, // VLR32 + 0U, // VLR64 + 0U, // VLVGP32 + 0U, // VST32 + 0U, // VST64 + 0U, // XCLoop + 0U, // XCSequence + 0U, // XIFMux + 0U, // XIHF64 + 0U, // XILF64 + 0U, // ZEXT128 + 16430U, // A + 18800U, // AD + 16883U, // ADB + 16804865U, // ADBR + 16805360U, // ADR + 1107325271U, // ADTR + 1107312942U, // ADTRA + 18918U, // AE + 17340U, // AEB + 16804997U, // AEBR + 16805497U, // AER + 50356445U, // AFI + 21882U, // AG + 21267U, // AGF + 50356455U, // AGFI + 16805668U, // AGFR + 22882U, // AGH + 67133752U, // AGHI + 1107321434U, // AGHIK + 16805750U, // AGR + 1107321492U, // AGRK + 83927453U, // AGSI + 22627U, // AH + 1107324947U, // AHHHR + 1107325082U, // AHHLR + 67133740U, // AHI + 1107321428U, // AHIK + 30871U, // AHY + 50354711U, // AIH + 25333U, // AL + 18663U, // ALC + 22006U, // ALCG + 16805762U, // ALCGR + 16805341U, // ALCR + 100688143U, // ALFI + 22190U, // ALG + 21284U, // ALGF + 100688115U, // ALGFI + 16805681U, // ALGFR + 1107321441U, // ALGHSIK + 16805794U, // ALGR + 1107321498U, // ALGRK + 83927459U, // ALGSI + 1107324954U, // ALHHHR + 1107325089U, // ALHHLR + 1107321450U, // ALHSIK + 16806010U, // ALR + 1107321542U, // ALRK + 83927510U, // ALSI + 50354776U, // ALSIH + 50358418U, // ALSIHN + 30929U, // ALY + 117500432U, // AP + 16804837U, // AR + 1107321487U, // ARK + 83927448U, // ASI + 30614U, // AU + 16806613U, // AUR + 30705U, // AW + 16806629U, // AWR + 16805219U, // AXBR + 16806639U, // AXR + 1107325529U, // AXTR + 1107312994U, // AXTRA + 30800U, // AY + 65971U, // B + 33583219U, // BAKR + 134243065U, // BAL + 33583225U, // BALR + 134247259U, // BAS + 33583387U, // BASR + 33581165U, // BASSM + 68087U, // BAsmE + 71804U, // BAsmH + 68217U, // BAsmHE + 74502U, // BAsmL + 69053U, // BAsmLE + 72358U, // BAsmLH + 75526U, // BAsmM + 69792U, // BAsmNE + 73228U, // BAsmNH + 68461U, // BAsmNHE + 74853U, // BAsmNL + 69300U, // BAsmNLE + 72653U, // BAsmNLH + 75675U, // BAsmNM + 76101U, // BAsmNO + 76473U, // BAsmNP + 80282U, // BAsmNZ + 75984U, // BAsmO + 76318U, // BAsmP + 80167U, // BAsmZ + 621613U, // BC + 1149082U, // BCAsm + 1670189U, // BCR + 153202129U, // BCRAsm + 30326U, // BCT + 22475U, // BCTG + 16805855U, // BCTGR + 16806189U, // BCTR + 73919U, // BI + 68933U, // BIAsmE + 72223U, // BIAsmH + 68360U, // BIAsmHE + 74698U, // BIAsmL + 69193U, // BIAsmLE + 72499U, // BIAsmLH + 75619U, // BIAsmM + 69918U, // BIAsmNE + 73347U, // BIAsmNH + 68595U, // BIAsmNHE + 74972U, // BIAsmNL + 69434U, // BIAsmNLE + 72787U, // BIAsmNLH + 75737U, // BIAsmNM + 76163U, // BIAsmNO + 76535U, // BIAsmNP + 80344U, // BIAsmNZ + 76038U, // BIAsmO + 76422U, // BIAsmP + 80228U, // BIAsmZ + 621737U, // BIC + 1149126U, // BICAsm + 2317986625U, // BPP + 3391728483U, // BPRP + 3173379U, // BR + 184578918U, // BRAS + 184575582U, // BRASL + 3174014U, // BRAsmE + 3174393U, // BRAsmH + 3174062U, // BRAsmHE + 3174527U, // BRAsmL + 3174081U, // BRAsmLE + 3174456U, // BRAsmLH + 3174640U, // BRAsmM + 3174099U, // BRAsmNE + 3174475U, // BRAsmNH + 3174068U, // BRAsmNHE + 3174596U, // BRAsmNL + 3174087U, // BRAsmNLE + 3174468U, // BRAsmNLH + 3174645U, // BRAsmNM + 3174661U, // BRAsmNO + 3174677U, // BRAsmNP + 3175253U, // BRAsmNZ + 3174656U, // BRAsmO + 3174667U, // BRAsmP + 3175248U, // BRAsmZ + 201948354U, // BRC + 153717047U, // BRCAsm + 201948293U, // BRCL + 153723733U, // BRCLAsm + 201356931U, // BRCT + 201349088U, // BRCTG + 201351128U, // BRCTH + 1090543724U, // BRXH + 1090541188U, // BRXHG + 1090539666U, // BRXLE + 1090541341U, // BRXLG + 33571219U, // BSA + 33576858U, // BSG + 33581139U, // BSM + 1090543713U, // BXH + 1090541182U, // BXHG + 1090539660U, // BXLE + 1090541109U, // BXLEG + 134236295U, // C + 134236532U, // CD + 134234659U, // CDB + 33582088U, // CDBR + 33582339U, // CDFBR + 218120388U, // CDFBRA + 33582858U, // CDFR + 218132967U, // CDFTR + 33582384U, // CDGBR + 218120412U, // CDGBRA + 33582992U, // CDGR + 33583621U, // CDGTR + 218120530U, // CDGTRA + 218131729U, // CDLFBR + 218132974U, // CDLFTR + 218131774U, // CDLGBR + 218133004U, // CDLGTR + 234911491U, // CDPT + 33582588U, // CDR + 1090548978U, // CDS + 1090541476U, // CDSG + 33583669U, // CDSTR + 1090550035U, // CDSY + 33583453U, // CDTR + 33583690U, // CDUTR + 234911626U, // CDZT + 134236726U, // CE + 134235081U, // CEB + 33582220U, // CEBR + 33583465U, // CEDTR + 33582346U, // CEFBR + 218120396U, // CEFBRA + 33582878U, // CEFR + 33582391U, // CEGBR + 218120420U, // CEGBRA + 33583004U, // CEGR + 218131737U, // CELFBR + 218131782U, // CELGBR + 33582724U, // CER + 33583724U, // CEXTR + 3180720U, // CFC + 218131483U, // CFDBR + 218120340U, // CFDBRA + 218131987U, // CFDR + 218132869U, // CFDTR + 218131623U, // CFEBR + 218120364U, // CFEBRA + 218132130U, // CFER + 251683042U, // CFI + 218131838U, // CFXBR + 218120452U, // CFXBRA + 218133254U, // CFXR + 218133121U, // CFXTR + 134239717U, // CG + 218131498U, // CGDBR + 218120348U, // CGDBRA + 218131993U, // CGDR + 218132884U, // CGDTR + 218120508U, // CGDTRA + 218131638U, // CGEBR + 218120372U, // CGEBRA + 218132136U, // CGER + 134239000U, // CGF + 251683053U, // CGFI + 33582891U, // CGFR + 268461514U, // CGFRL + 134240617U, // CGH + 285237568U, // CGHI + 268461574U, // CGHRL + 67150264U, // CGHSI + 305789999U, // CGIB + 1392526511U, // CGIBAsm + 2466269691U, // CGIBAsmE + 2466273408U, // CGIBAsmH + 2466269822U, // CGIBAsmHE + 2466276106U, // CGIBAsmL + 2466270658U, // CGIBAsmLE + 2466273963U, // CGIBAsmLH + 2466271397U, // CGIBAsmNE + 2466274833U, // CGIBAsmNH + 2466270067U, // CGIBAsmNHE + 2466276458U, // CGIBAsmNL + 2466270906U, // CGIBAsmNLE + 2466274259U, // CGIBAsmNLH + 339344580U, // CGIJ + 1392534010U, // CGIJAsm + 3540012399U, // CGIJAsmE + 3540015717U, // CGIJAsmH + 3540011826U, // CGIJAsmHE + 3540018159U, // CGIJAsmL + 3540012659U, // CGIJAsmLE + 3540015990U, // CGIJAsmLH + 3540013384U, // CGIJAsmNE + 3540016813U, // CGIJAsmNH + 3540012066U, // CGIJAsmNHE + 3540018438U, // CGIJAsmNL + 3540012905U, // CGIJAsmNLE + 3540016258U, // CGIJAsmNLH + 4324667U, // CGIT + 1358984917U, // CGITAsm + 285233731U, // CGITAsmE + 285237236U, // CGITAsmH + 285232397U, // CGITAsmHE + 285238957U, // CGITAsmL + 285233236U, // CGITAsmLE + 285236625U, // CGITAsmLH + 285233594U, // CGITAsmNE + 285237023U, // CGITAsmNH + 285232283U, // CGITAsmNHE + 285238648U, // CGITAsmNL + 285233122U, // CGITAsmNLE + 285236482U, // CGITAsmNLH + 33582980U, // CGR + 3391224909U, // CGRB + 1107314075U, // CGRBAsm + 1107315223U, // CGRBAsmE + 1107318945U, // CGRBAsmH + 1107315358U, // CGRBAsmHE + 1107321638U, // CGRBAsmL + 1107316194U, // CGRBAsmLE + 1107319499U, // CGRBAsmLH + 1107316933U, // CGRBAsmNE + 1107320369U, // CGRBAsmNH + 1107315607U, // CGRBAsmNHE + 1107321994U, // CGRBAsmNL + 1107316446U, // CGRBAsmNLE + 1107319799U, // CGRBAsmNLH + 169999576U, // CGRJ + 1107321362U, // CGRJAsm + 1107316107U, // CGRJAsmE + 1107319425U, // CGRJAsmH + 1107315538U, // CGRJAsmHE + 1107321867U, // CGRJAsmL + 1107316371U, // CGRJAsmLE + 1107319702U, // CGRJAsmLH + 1107317096U, // CGRJAsmNE + 1107320525U, // CGRJAsmNH + 1107315782U, // CGRJAsmNHE + 1107322150U, // CGRJAsmNL + 1107316621U, // CGRJAsmNLE + 1107319974U, // CGRJAsmNLH + 268461539U, // CGRL + 153222482U, // CGRT + 1107326751U, // CGRTAsm + 33575524U, // CGRTAsmE + 33579023U, // CGRTAsmH + 33574188U, // CGRTAsmHE + 33580744U, // CGRTAsmL + 33575027U, // CGRTAsmLE + 33578416U, // CGRTAsmLH + 33575385U, // CGRTAsmNE + 33578814U, // CGRTAsmNH + 33574078U, // CGRTAsmNHE + 33580439U, // CGRTAsmNL + 33574917U, // CGRTAsmNLE + 33578277U, // CGRTAsmNLH + 218131853U, // CGXBR + 218120460U, // CGXBRA + 218133260U, // CGXR + 218133136U, // CGXTR + 218120560U, // CGXTRA + 134240442U, // CH + 134239092U, // CHF + 33583117U, // CHHR + 67150279U, // CHHSI + 285237555U, // CHI + 33583252U, // CHLR + 268461559U, // CHRL + 67150250U, // CHSI + 134248604U, // CHY + 305789995U, // CIB + 1392526499U, // CIBAsm + 2466269685U, // CIBAsmE + 2466273402U, // CIBAsmH + 2466269815U, // CIBAsmHE + 2466276100U, // CIBAsmL + 2466270651U, // CIBAsmLE + 2466273956U, // CIBAsmLH + 2466271390U, // CIBAsmNE + 2466274826U, // CIBAsmNH + 2466270059U, // CIBAsmNHE + 2466276451U, // CIBAsmNL + 2466270898U, // CIBAsmNLE + 2466274251U, // CIBAsmNLH + 251681316U, // CIH + 339344576U, // CIJ + 1392534005U, // CIJAsm + 3540012393U, // CIJAsmE + 3540015711U, // CIJAsmH + 3540011819U, // CIJAsmHE + 3540018153U, // CIJAsmL + 3540012652U, // CIJAsmLE + 3540015983U, // CIJAsmLH + 3540013377U, // CIJAsmNE + 3540016806U, // CIJAsmNH + 3540012058U, // CIJAsmNHE + 3540018431U, // CIJAsmNL + 3540012897U, // CIJAsmNLE + 3540016250U, // CIJAsmNLH + 4324657U, // CIT + 1358984905U, // CITAsm + 285233717U, // CITAsmE + 285237222U, // CITAsmH + 285232381U, // CITAsmHE + 285238943U, // CITAsmL + 285233220U, // CITAsmLE + 285236609U, // CITAsmLH + 285233578U, // CITAsmNE + 285237007U, // CITAsmNH + 285232265U, // CITAsmNHE + 285238632U, // CITAsmNL + 285233104U, // CITAsmNLE + 285236464U, // CITAsmNLH + 33581145U, // CKSM + 134243134U, // CL + 302041324U, // CLC + 33579842U, // CLCL + 1107316219U, // CLCLE + 1107326888U, // CLCLU + 218131490U, // CLFDBR + 218132876U, // CLFDTR + 218131630U, // CLFEBR + 352362928U, // CLFHSI + 369123605U, // CLFI + 4848949U, // CLFIT + 1459648206U, // CLFITAsm + 385897019U, // CLFITAsmE + 385900524U, // CLFITAsmH + 385895684U, // CLFITAsmHE + 385902245U, // CLFITAsmL + 385896523U, // CLFITAsmLE + 385899912U, // CLFITAsmLH + 385896881U, // CLFITAsmNE + 385900310U, // CLFITAsmNH + 385895569U, // CLFITAsmNHE + 385901935U, // CLFITAsmNL + 385896408U, // CLFITAsmNLE + 385899768U, // CLFITAsmNLH + 218131845U, // CLFXBR + 218133128U, // CLFXTR + 134239933U, // CLG + 218131505U, // CLGDBR + 218132891U, // CLGDTR + 218131645U, // CLGEBR + 134239018U, // CLGF + 369123578U, // CLGFI + 33582904U, // CLGFR + 268461521U, // CLGFRL + 268461581U, // CLGHRL + 352362943U, // CLGHSI + 307362868U, // CLGIB + 1476412597U, // CLGIBAsm + 2550155778U, // CLGIBAsmE + 2550159495U, // CLGIBAsmH + 2550155910U, // CLGIBAsmHE + 2550162193U, // CLGIBAsmL + 2550156746U, // CLGIBAsmLE + 2550160051U, // CLGIBAsmLH + 2550157485U, // CLGIBAsmNE + 2550160921U, // CLGIBAsmNH + 2550156156U, // CLGIBAsmNHE + 2550162546U, // CLGIBAsmNL + 2550156995U, // CLGIBAsmNLE + 2550160348U, // CLGIBAsmNLH + 340917449U, // CLGIJ + 1476420096U, // CLGIJAsm + 3623898486U, // CLGIJAsmE + 3623901804U, // CLGIJAsmH + 3623897914U, // CLGIJAsmHE + 3623904246U, // CLGIJAsmL + 3623898747U, // CLGIJAsmLE + 3623902078U, // CLGIJAsmLH + 3623899472U, // CLGIJAsmNE + 3623902901U, // CLGIJAsmNH + 3623898155U, // CLGIJAsmNHE + 3623904526U, // CLGIJAsmNL + 3623898994U, // CLGIJAsmNLE + 3623902347U, // CLGIJAsmNLH + 4848960U, // CLGIT + 1459648219U, // CLGITAsm + 385897034U, // CLGITAsmE + 385900539U, // CLGITAsmH + 385895701U, // CLGITAsmHE + 385902260U, // CLGITAsmL + 385896540U, // CLGITAsmLE + 385899929U, // CLGITAsmLH + 385896898U, // CLGITAsmNE + 385900327U, // CLGITAsmNH + 385895588U, // CLGITAsmNHE + 385901952U, // CLGITAsmNL + 385896427U, // CLGITAsmNLE + 385899787U, // CLGITAsmNLH + 33583016U, // CLGR + 3391224914U, // CLGRB + 1107314081U, // CLGRBAsm + 1107315230U, // CLGRBAsmE + 1107318952U, // CLGRBAsmH + 1107315366U, // CLGRBAsmHE + 1107321645U, // CLGRBAsmL + 1107316202U, // CLGRBAsmLE + 1107319507U, // CLGRBAsmLH + 1107316941U, // CLGRBAsmNE + 1107320377U, // CLGRBAsmNH + 1107315616U, // CLGRBAsmNHE + 1107322002U, // CLGRBAsmNL + 1107316455U, // CLGRBAsmNLE + 1107319808U, // CLGRBAsmNLH + 169999581U, // CLGRJ + 1107321368U, // CLGRJAsm + 1107316114U, // CLGRJAsmE + 1107319432U, // CLGRJAsmH + 1107315546U, // CLGRJAsmHE + 1107321874U, // CLGRJAsmL + 1107316379U, // CLGRJAsmLE + 1107319710U, // CLGRJAsmLH + 1107317104U, // CLGRJAsmNE + 1107320533U, // CLGRJAsmNH + 1107315791U, // CLGRJAsmNHE + 1107322158U, // CLGRJAsmNL + 1107316630U, // CLGRJAsmNLE + 1107319983U, // CLGRJAsmNLH + 268461545U, // CLGRL + 153222487U, // CLGRT + 1107326757U, // CLGRTAsm + 33575531U, // CLGRTAsmE + 33579030U, // CLGRTAsmH + 33574196U, // CLGRTAsmHE + 33580751U, // CLGRTAsmL + 33575035U, // CLGRTAsmLE + 33578424U, // CLGRTAsmLH + 33575393U, // CLGRTAsmNE + 33578822U, // CLGRTAsmNH + 33574087U, // CLGRTAsmNHE + 33580447U, // CLGRTAsmNL + 33574926U, // CLGRTAsmNLE + 33578286U, // CLGRTAsmNLH + 146732U, // CLGT + 1493202621U, // CLGTAsm + 436228654U, // CLGTAsmE + 436232159U, // CLGTAsmH + 436227317U, // CLGTAsmHE + 436233880U, // CLGTAsmL + 436228156U, // CLGTAsmLE + 436231545U, // CLGTAsmLH + 436228514U, // CLGTAsmNE + 436231943U, // CLGTAsmNH + 436227200U, // CLGTAsmNHE + 436233568U, // CLGTAsmNL + 436228039U, // CLGTAsmNLE + 436231399U, // CLGTAsmNLH + 218131860U, // CLGXBR + 218133143U, // CLGXTR + 134239136U, // CLHF + 33583153U, // CLHHR + 352362958U, // CLHHSI + 33583288U, // CLHLR + 268461597U, // CLHRL + 453026168U, // CLI + 307362874U, // CLIB + 1476412604U, // CLIBAsm + 2550155786U, // CLIBAsmE + 2550159503U, // CLIBAsmH + 2550155919U, // CLIBAsmHE + 2550162201U, // CLIBAsmL + 2550156755U, // CLIBAsmLE + 2550160060U, // CLIBAsmLH + 2550157494U, // CLIBAsmNE + 2550160930U, // CLIBAsmNH + 2550156166U, // CLIBAsmNHE + 2550162555U, // CLIBAsmNL + 2550157005U, // CLIBAsmNLE + 2550160358U, // CLIBAsmNLH + 369121866U, // CLIH + 340917455U, // CLIJ + 1476420103U, // CLIJAsm + 3623898494U, // CLIJAsmE + 3623901812U, // CLIJAsmH + 3623897923U, // CLIJAsmHE + 3623904254U, // CLIJAsmL + 3623898756U, // CLIJAsmLE + 3623902087U, // CLIJAsmLH + 3623899481U, // CLIJAsmNE + 3623902910U, // CLIJAsmNH + 3623898165U, // CLIJAsmNHE + 3623904535U, // CLIJAsmNL + 3623899004U, // CLIJAsmNLE + 3623902357U, // CLIJAsmNLH + 453032118U, // CLIY + 2365613969U, // CLM + 2365611506U, // CLMH + 2365618426U, // CLMY + 33583236U, // CLR + 3391224920U, // CLRB + 1107314088U, // CLRBAsm + 1107315238U, // CLRBAsmE + 1107318960U, // CLRBAsmH + 1107315375U, // CLRBAsmHE + 1107321653U, // CLRBAsmL + 1107316211U, // CLRBAsmLE + 1107319516U, // CLRBAsmLH + 1107316950U, // CLRBAsmNE + 1107320386U, // CLRBAsmNH + 1107315626U, // CLRBAsmNHE + 1107322011U, // CLRBAsmNL + 1107316465U, // CLRBAsmNLE + 1107319818U, // CLRBAsmNLH + 169999587U, // CLRJ + 1107321375U, // CLRJAsm + 1107316122U, // CLRJAsmE + 1107319440U, // CLRJAsmH + 1107315555U, // CLRJAsmHE + 1107321882U, // CLRJAsmL + 1107316388U, // CLRJAsmLE + 1107319719U, // CLRJAsmLH + 1107317113U, // CLRJAsmNE + 1107320542U, // CLRJAsmNH + 1107315801U, // CLRJAsmNHE + 1107322167U, // CLRJAsmNL + 1107316640U, // CLRJAsmNLE + 1107319993U, // CLRJAsmNLH + 268461618U, // CLRL + 153222493U, // CLRT + 1107326764U, // CLRTAsm + 33575539U, // CLRTAsmE + 33579038U, // CLRTAsmH + 33574205U, // CLRTAsmHE + 33580759U, // CLRTAsmL + 33575044U, // CLRTAsmLE + 33578433U, // CLRTAsmLH + 33575402U, // CLRTAsmNE + 33578831U, // CLRTAsmNH + 33574097U, // CLRTAsmNHE + 33580456U, // CLRTAsmNL + 33574936U, // CLRTAsmNLE + 33578296U, // CLRTAsmNLH + 33584959U, // CLST + 146758U, // CLT + 1493202658U, // CLTAsm + 436228690U, // CLTAsmE + 436232195U, // CLTAsmH + 436227358U, // CLTAsmHE + 436233916U, // CLTAsmL + 436228197U, // CLTAsmLE + 436231586U, // CLTAsmLH + 436228555U, // CLTAsmNE + 436231984U, // CLTAsmNH + 436227246U, // CLTAsmNHE + 436233609U, // CLTAsmNL + 436228085U, // CLTAsmNLE + 436231445U, // CLTAsmNLH + 134248662U, // CLY + 33573205U, // CMPSC + 117500452U, // CP + 234911389U, // CPDT + 1090547289U, // CPSDRdd + 1090547289U, // CPSDRds + 1090547289U, // CPSDRsd + 1090547289U, // CPSDRss + 234911608U, // CPXT + 33571240U, // CPYA + 33582546U, // CR + 3391224905U, // CRB + 1107314070U, // CRBAsm + 1107315217U, // CRBAsmE + 1107318939U, // CRBAsmH + 1107315351U, // CRBAsmHE + 1107321632U, // CRBAsmL + 1107316187U, // CRBAsmLE + 1107319492U, // CRBAsmLH + 1107316926U, // CRBAsmNE + 1107320362U, // CRBAsmNH + 1107315599U, // CRBAsmNHE + 1107321987U, // CRBAsmNL + 1107316438U, // CRBAsmNLE + 1107319791U, // CRBAsmNLH + 1090540071U, // CRDTE + 1090540071U, // CRDTEOpt + 169999572U, // CRJ + 1107321357U, // CRJAsm + 1107316101U, // CRJAsmE + 1107319419U, // CRJAsmH + 1107315531U, // CRJAsmHE + 1107321861U, // CRJAsmL + 1107316364U, // CRJAsmLE + 1107319695U, // CRJAsmLH + 1107317089U, // CRJAsmNE + 1107320518U, // CRJAsmNH + 1107315774U, // CRJAsmNHE + 1107322143U, // CRJAsmNL + 1107316613U, // CRJAsmNLE + 1107319966U, // CRJAsmNLH + 268461502U, // CRL + 153222478U, // CRT + 1107326746U, // CRTAsm + 33575518U, // CRTAsmE + 33579017U, // CRTAsmH + 33574181U, // CRTAsmHE + 33580738U, // CRTAsmL + 33575020U, // CRTAsmLE + 33578409U, // CRTAsmLH + 33575378U, // CRTAsmNE + 33578807U, // CRTAsmNH + 33574070U, // CRTAsmNHE + 33580432U, // CRTAsmNL + 33574909U, // CRTAsmNLE + 33578269U, // CRTAsmNLH + 1090548974U, // CS + 15496U, // CSCH + 1107325373U, // CSDTR + 1090541471U, // CSG + 16804730U, // CSP + 16799602U, // CSPG + 1543550795U, // CSST + 1107325625U, // CSXTR + 1090550030U, // CSY + 1107312653U, // CU12 + 33570829U, // CU12Opt + 1107312665U, // CU14 + 33570841U, // CU14Opt + 1107312641U, // CU21 + 33570817U, // CU21Opt + 1107312671U, // CU24 + 33570847U, // CU24Opt + 33570823U, // CU41 + 33570835U, // CU42 + 33583570U, // CUDTR + 33575451U, // CUSE + 1107326874U, // CUTFU + 33585050U, // CUTFUOpt + 1107318025U, // CUUTF + 33576201U, // CUUTFOpt + 33583822U, // CUXTR + 18258U, // CVB + 21980U, // CVBG + 30815U, // CVBY + 134236629U, // CVD + 134239772U, // CVDG + 134248571U, // CVDY + 33582442U, // CXBR + 33582377U, // CXFBR + 218120404U, // CXFBRA + 33582960U, // CXFR + 218132990U, // CXFTR + 33582422U, // CXGBR + 218120428U, // CXGBRA + 33583091U, // CXGR + 33583651U, // CXGTR + 218120538U, // CXGTRA + 218131745U, // CXLFBR + 218132982U, // CXLFTR + 218131790U, // CXLGBR + 218133019U, // CXLGTR + 234911508U, // CXPT + 33583861U, // CXR + 33583683U, // CXSTR + 33583711U, // CXTR + 33583697U, // CXUTR + 234911632U, // CXZT + 134248550U, // CY + 234911401U, // CZDT + 234911620U, // CZXT + 18801U, // D + 18808U, // DD + 16960U, // DDB + 16804878U, // DDBR + 16805377U, // DDR + 1107325283U, // DDTR + 1107312949U, // DDTRA + 19023U, // DE + 17360U, // DEB + 16805011U, // DEBR + 16805515U, // DER + 1107318148U, // DIAG + 1107323961U, // DIDBR + 1107324101U, // DIEBR + 25443U, // DL + 22212U, // DLG + 16805806U, // DLGR + 16806025U, // DLR + 117500472U, // DP + 16805361U, // DR + 22437U, // DSG + 21324U, // DSGF + 16805723U, // DSGFR + 16805843U, // DSGR + 16805233U, // DXBR + 16806651U, // DXR + 1107325542U, // DXTR + 1107313001U, // DXTRA + 33582052U, // EAR + 1107318142U, // ECAG + 33583411U, // ECCTR + 33570901U, // ECPGA + 1543542737U, // ECTG + 302041470U, // ED + 302047870U, // EDMK + 33583472U, // EEDTR + 33583731U, // EEXTR + 3164446U, // EFPC + 3174494U, // EPAIR + 3173353U, // EPAR + 33583432U, // EPCTR + 33585171U, // EPSW + 33576508U, // EREG + 33576527U, // EREGG + 3174501U, // ESAIR + 3173359U, // ESAR + 33583556U, // ESDTR + 3162173U, // ESEA + 33571224U, // ESTA + 33583808U, // ESXTR + 3164588U, // ETND + 134248491U, // EX + 268461656U, // EXRL + 218131520U, // FIDBR + 218120356U, // FIDBRA + 33582635U, // FIDR + 218132899U, // FIDTR + 218131660U, // FIEBR + 218120380U, // FIEBRA + 33582779U, // FIER + 218131868U, // FIXBR + 218120468U, // FIXBRA + 33583890U, // FIXR + 218133151U, // FIXTR + 33583046U, // FLOGR + 33582630U, // HDR + 33582767U, // HER + 15501U, // HSCH + 3164293U, // IAC + 18631U, // IC + 18631U, // IC32 + 30821U, // IC32Y + 486565654U, // ICM + 486563280U, // ICMH + 486570221U, // ICMY + 30821U, // ICY + 1090540065U, // IDTE + 1090540065U, // IDTEOpt + 1090548087U, // IEDTR + 1090548346U, // IEXTR + 369120121U, // IIHF + 352344513U, // IIHH + 352347051U, // IIHL + 369120266U, // IILF + 352344918U, // IILH + 352347175U, // IILL + 15592U, // IPK + 3172386U, // IPM + 1107317336U, // IPTE + 1107317336U, // IPTEOpt + 33575512U, // IPTEOptOpt + 33580810U, // IRBM + 16797096U, // ISKE + 16802541U, // IVSK + 3308094U, // InsnE + 1579334303U, // InsnRI + 505608775U, // InsnRIE + 3726834366U, // InsnRIL + 2653092625U, // InsnRILU + 3726834407U, // InsnRIS + 5929684U, // InsnRR + 505592402U, // InsnRRE + 505592446U, // InsnRRF + 505608956U, // InsnRRS + 505592562U, // InsnRS + 505608797U, // InsnRSE + 505608883U, // InsnRSI + 505609010U, // InsnRSY + 2653076253U, // InsnRX + 2653092467U, // InsnRXE + 505608852U, // InsnRXF + 2653092669U, // InsnRXY + 157465310U, // InsnS + 509786793U, // InsnSI + 1583545033U, // InsnSIL + 2657286951U, // InsnSIY + 7011079U, // InsnSS + 3731028584U, // InsnSSE + 3731028617U, // InsnSSF + 205303U, // J + 200043U, // JAsmE + 203361U, // JAsmH + 199469U, // JAsmHE + 205803U, // JAsmL + 200302U, // JAsmLE + 203633U, // JAsmLH + 206729U, // JAsmM + 201027U, // JAsmNE + 204456U, // JAsmNH + 199708U, // JAsmNHE + 206081U, // JAsmNL + 200547U, // JAsmNLE + 203900U, // JAsmNLH + 206844U, // JAsmNM + 207270U, // JAsmNO + 207642U, // JAsmNP + 211451U, // JAsmNZ + 207141U, // JAsmO + 207531U, // JAsmP + 211331U, // JAsmZ + 202402U, // JG + 199282U, // JGAsmE + 203133U, // JGAsmH + 199407U, // JGAsmHE + 205704U, // JGAsmL + 200240U, // JGAsmLE + 203531U, // JGAsmLH + 206664U, // JGAsmM + 200965U, // JGAsmNE + 204394U, // JGAsmNH + 199639U, // JGAsmNHE + 206019U, // JGAsmNL + 200478U, // JGAsmNLE + 203831U, // JGAsmNLH + 206784U, // JGAsmNM + 207210U, // JGAsmNO + 207582U, // JGAsmNP + 211391U, // JGAsmNZ + 207088U, // JGAsmO + 207465U, // JGAsmP + 211278U, // JGAsmZ + 134234878U, // KDB + 33582151U, // KDBR + 33583530U, // KDTR + 134235119U, // KEB + 33582291U, // KEBR + 3361184U, // KIMD + 3361190U, // KLMD + 33580941U, // KM + 1090535547U, // KMA + 3360906U, // KMAC + 33573115U, // KMC + 1090548033U, // KMCTR + 33576078U, // KMF + 33581371U, // KMO + 33582499U, // KXBR + 33583782U, // KXTR + 134243062U, // L + 134234218U, // LA + 1107312684U, // LAA + 1107318136U, // LAAG + 1107321587U, // LAAL + 1107318444U, // LAALG + 134236650U, // LAE + 134248577U, // LAEY + 1107322617U, // LAM + 1107327200U, // LAMY + 1107323013U, // LAN + 1107318603U, // LANG + 1107323077U, // LAO + 1107318615U, // LAOG + 268461494U, // LARL + 469805940U, // LASP + 134248041U, // LAT + 1107327007U, // LAX + 1107318845U, // LAXG + 134248527U, // LAY + 134235341U, // LB + 134240406U, // LBH + 33582430U, // LBR + 1207976394U, // LCBB + 3188342U, // LCCTL + 33582087U, // LCDBR + 33582857U, // LCDFR + 33582857U, // LCDFR_32 + 33582587U, // LCDR + 33582219U, // LCEBR + 33582723U, // LCER + 33582890U, // LCGFR + 33582979U, // LCGR + 33582558U, // LCR + 1107322493U, // LCTL + 1107318543U, // LCTLG + 33582441U, // LCXBR + 33583860U, // LCXR + 134236572U, // LD + 134236750U, // LDE + 134236750U, // LDE32 + 134235087U, // LDEB + 33582226U, // LDEBR + 33582736U, // LDER + 1107325408U, // LDETR + 33582998U, // LDGR + 33582641U, // LDR + 33582641U, // LDR32 + 33582448U, // LDXBR + 218120436U, // LDXBRA + 33583866U, // LDXR + 218133093U, // LDXTR + 134248560U, // LDY + 134237623U, // LE + 33582100U, // LEDBR + 218120332U, // LEDBRA + 33582605U, // LEDR + 218132862U, // LEDTR + 33582786U, // LER + 33582455U, // LEXBR + 218120444U, // LEXBRA + 33583872U, // LEXR + 134248583U, // LEY + 3191648U, // LFAS + 134240599U, // LFH + 134248034U, // LFHAT + 3180836U, // LFPC + 134239919U, // LG + 134248028U, // LGAT + 134235208U, // LGB + 33582400U, // LGBR + 33582623U, // LGDR + 134239013U, // LGF + 251683060U, // LGFI + 33582898U, // LGFR + 268461522U, // LGFRL + 134239830U, // LGG + 134240643U, // LGH + 285237574U, // LGHI + 33583111U, // LGHR + 268461582U, // LGHRL + 33583011U, // LGR + 268461546U, // LGRL + 134236483U, // LGSC + 134240928U, // LH + 134240733U, // LHH + 285237608U, // LHI + 33583161U, // LHR + 268461598U, // LHRL + 134248609U, // LHY + 134236401U, // LLC + 134240458U, // LLCH + 33582563U, // LLCR + 134236346U, // LLGC + 33582550U, // LLGCR + 134239024U, // LLGF + 134248020U, // LLGFAT + 33582911U, // LLGFR + 268461529U, // LLGFRL + 134240170U, // LLGFSG + 134240642U, // LLGH + 33583110U, // LLGHR + 268461589U, // LLGHRL + 134248131U, // LLGT + 134248046U, // LLGTAT + 33583636U, // LLGTR + 134241202U, // LLH + 134240738U, // LLHH + 33583166U, // LLHR + 268461604U, // LLHRL + 369120127U, // LLIHF + 385898951U, // LLIHH + 385901489U, // LLIHL + 369120272U, // LLILF + 385899356U, // LLILH + 385901613U, // LLILL + 134239044U, // LLZRGF + 1107322770U, // LM + 1107315111U, // LMD + 1107318585U, // LMG + 1107320307U, // LMH + 1107327227U, // LMY + 33582163U, // LNDBR + 33582864U, // LNDFR + 33582864U, // LNDFR_32 + 33582651U, // LNDR + 33582297U, // LNEBR + 33582809U, // LNER + 33582925U, // LNGFR + 33583040U, // LNGR + 33583355U, // LNR + 33582511U, // LNXBR + 33583906U, // LNXR + 244833U, // LOC + 1543522574U, // LOCAsm + 469781056U, // LOCAsmE + 469784790U, // LOCAsmH + 469781182U, // LOCAsmHE + 469787464U, // LOCAsmL + 469782018U, // LOCAsmLE + 469785323U, // LOCAsmLH + 469788443U, // LOCAsmM + 469782750U, // LOCAsmNE + 469786186U, // LOCAsmNH + 469781427U, // LOCAsmNHE + 469787811U, // LOCAsmNL + 469782266U, // LOCAsmNLE + 469785619U, // LOCAsmNLH + 469788576U, // LOCAsmNM + 469789002U, // LOCAsmNO + 469789374U, // LOCAsmNP + 469793183U, // LOCAsmNZ + 469788884U, // LOCAsmO + 469789218U, // LOCAsmP + 469793067U, // LOCAsmZ + 244892U, // LOCFH + 1543526728U, // LOCFHAsm + 469781197U, // LOCFHAsmE + 469785008U, // LOCFHAsmH + 469781237U, // LOCFHAsmHE + 469787546U, // LOCFHAsmL + 469782070U, // LOCFHAsmLE + 469785376U, // LOCFHAsmLH + 469788498U, // LOCFHAsmM + 469782795U, // LOCFHAsmNE + 469786224U, // LOCFHAsmNH + 469781470U, // LOCFHAsmNHE + 469787849U, // LOCFHAsmNL + 469782309U, // LOCFHAsmNLE + 469785662U, // LOCFHAsmNLH + 469788614U, // LOCFHAsmNM + 469789040U, // LOCFHAsmNO + 469789412U, // LOCFHAsmNP + 469793221U, // LOCFHAsmNZ + 469788917U, // LOCFHAsmO + 469789301U, // LOCFHAsmP + 469793107U, // LOCFHAsmZ + 7601442U, // LOCFHR + 1090547710U, // LOCFHRAsm + 16798214U, // LOCFHRAsmE + 16801700U, // LOCFHRAsmH + 16796907U, // LOCFHRAsmHE + 16803325U, // LOCFHRAsmL + 16797746U, // LOCFHRAsmLE + 16801113U, // LOCFHRAsmLH + 16803914U, // LOCFHRAsmM + 16798104U, // LOCFHRAsmNE + 16801533U, // LOCFHRAsmNH + 16796789U, // LOCFHRAsmNHE + 16803158U, // LOCFHRAsmNL + 16797628U, // LOCFHRAsmNLE + 16800988U, // LOCFHRAsmNLH + 16803858U, // LOCFHRAsmNM + 16804290U, // LOCFHRAsmNO + 16804656U, // LOCFHRAsmNP + 16808465U, // LOCFHRAsmNZ + 16804339U, // LOCFHRAsmO + 16804698U, // LOCFHRAsmP + 16808490U, // LOCFHRAsmZ + 244858U, // LOCG + 1543525890U, // LOCGAsm + 469781091U, // LOCGAsmE + 469784935U, // LOCGAsmH + 469781214U, // LOCGAsmHE + 469787513U, // LOCGAsmL + 469782047U, // LOCGAsmLE + 469785338U, // LOCGAsmLH + 469788473U, // LOCGAsmM + 469782772U, // LOCGAsmNE + 469786201U, // LOCGAsmNH + 469781444U, // LOCGAsmNHE + 469787826U, // LOCGAsmNL + 469782283U, // LOCGAsmNLE + 469785636U, // LOCGAsmNLH + 469788591U, // LOCGAsmNM + 469789017U, // LOCGAsmNO + 469789389U, // LOCGAsmNP + 469793198U, // LOCGAsmNZ + 469788897U, // LOCGAsmO + 469789268U, // LOCGAsmP + 469793087U, // LOCGAsmZ + 8125618U, // LOCGHI + 1140875582U, // LOCGHIAsm + 67128658U, // LOCGHIAsmE + 67131960U, // LOCGHIAsmH + 67128087U, // LOCGHIAsmHE + 67134423U, // LOCGHIAsmL + 67128920U, // LOCGHIAsmLE + 67132226U, // LOCGHIAsmLH + 67135344U, // LOCGHIAsmM + 67129645U, // LOCGHIAsmNE + 67133074U, // LOCGHIAsmNH + 67128324U, // LOCGHIAsmNHE + 67134699U, // LOCGHIAsmNL + 67129163U, // LOCGHIAsmNLE + 67132516U, // LOCGHIAsmNLH + 67135464U, // LOCGHIAsmNM + 67135890U, // LOCGHIAsmNO + 67136262U, // LOCGHIAsmNP + 67140071U, // LOCGHIAsmNZ + 67135763U, // LOCGHIAsmO + 67136147U, // LOCGHIAsmP + 67139953U, // LOCGHIAsmZ + 7601436U, // LOCGR + 1090547593U, // LOCGRAsm + 16798206U, // LOCGRAsmE + 16801692U, // LOCGRAsmH + 16796898U, // LOCGRAsmHE + 16803297U, // LOCGRAsmL + 16797737U, // LOCGRAsmLE + 16801104U, // LOCGRAsmLH + 16803906U, // LOCGRAsmM + 16798095U, // LOCGRAsmNE + 16801524U, // LOCGRAsmNH + 16796779U, // LOCGRAsmNHE + 16803149U, // LOCGRAsmNL + 16797618U, // LOCGRAsmNLE + 16800978U, // LOCGRAsmNLH + 16803849U, // LOCGRAsmNM + 16804281U, // LOCGRAsmNO + 16804647U, // LOCGRAsmNP + 16808456U, // LOCGRAsmNZ + 16804331U, // LOCGRAsmO + 16804690U, // LOCGRAsmP + 16808482U, // LOCGRAsmZ + 8125625U, // LOCHHI + 1140875609U, // LOCHHIAsm + 67128667U, // LOCHHIAsmE + 67131969U, // LOCHHIAsmH + 67128097U, // LOCHHIAsmHE + 67134432U, // LOCHHIAsmL + 67128930U, // LOCHHIAsmLE + 67132236U, // LOCHHIAsmLH + 67135353U, // LOCHHIAsmM + 67129655U, // LOCHHIAsmNE + 67133084U, // LOCHHIAsmNH + 67128335U, // LOCHHIAsmNHE + 67134709U, // LOCHHIAsmNL + 67129174U, // LOCHHIAsmNLE + 67132527U, // LOCHHIAsmNLH + 67135474U, // LOCHHIAsmNM + 67135900U, // LOCHHIAsmNO + 67136272U, // LOCHHIAsmNP + 67140081U, // LOCHHIAsmNZ + 67135772U, // LOCHHIAsmO + 67136156U, // LOCHHIAsmP + 67139962U, // LOCHHIAsmZ + 8125612U, // LOCHI + 1140875569U, // LOCHIAsm + 67128650U, // LOCHIAsmE + 67131952U, // LOCHIAsmH + 67128078U, // LOCHIAsmHE + 67134415U, // LOCHIAsmL + 67128911U, // LOCHIAsmLE + 67132217U, // LOCHIAsmLH + 67135336U, // LOCHIAsmM + 67129636U, // LOCHIAsmNE + 67133065U, // LOCHIAsmNH + 67128314U, // LOCHIAsmNHE + 67134690U, // LOCHIAsmNL + 67129153U, // LOCHIAsmNLE + 67132506U, // LOCHIAsmNLH + 67135455U, // LOCHIAsmNM + 67135881U, // LOCHIAsmNO + 67136253U, // LOCHIAsmNP + 67140062U, // LOCHIAsmNZ + 67135755U, // LOCHIAsmO + 67136139U, // LOCHIAsmP + 67139945U, // LOCHIAsmZ + 7601431U, // LOCR + 1090547177U, // LOCRAsm + 16798199U, // LOCRAsmE + 16801685U, // LOCRAsmH + 16796890U, // LOCRAsmHE + 16803260U, // LOCRAsmL + 16797729U, // LOCRAsmLE + 16801096U, // LOCRAsmLH + 16803884U, // LOCRAsmM + 16798087U, // LOCRAsmNE + 16801516U, // LOCRAsmNH + 16796770U, // LOCRAsmNHE + 16803141U, // LOCRAsmNL + 16797609U, // LOCRAsmNLE + 16800969U, // LOCRAsmNLH + 16803841U, // LOCRAsmNM + 16804273U, // LOCRAsmNO + 16804639U, // LOCRAsmNP + 16808448U, // LOCRAsmNZ + 16804317U, // LOCRAsmO + 16804683U, // LOCRAsmP + 16808475U, // LOCRAsmZ + 3188355U, // LPCTL + 1509968306U, // LPD + 33582170U, // LPDBR + 33582871U, // LPDFR + 33582871U, // LPDFR_32 + 1509971477U, // LPDG + 33582657U, // LPDR + 33582304U, // LPEBR + 33582815U, // LPER + 33582932U, // LPGFR + 33583053U, // LPGR + 3189574U, // LPP + 134245326U, // LPQ + 33583376U, // LPR + 3192857U, // LPSW + 3183237U, // LPSWE + 1107312707U, // LPTEA + 33582518U, // LPXBR + 33583912U, // LPXR + 33583227U, // LR + 134234396U, // LRA + 134239640U, // LRAG + 134248537U, // LRAY + 33582669U, // LRDR + 33582827U, // LRER + 268461619U, // LRL + 134248422U, // LRV + 134240304U, // LRVG + 33583084U, // LRVGR + 134242388U, // LRVH + 33583839U, // LRVR + 3188362U, // LSCTL + 134248163U, // LT + 33582191U, // LTDBR + 33582191U, // LTDBRCompare + 33582688U, // LTDR + 33583563U, // LTDTR + 33582325U, // LTEBR + 33582325U, // LTEBRCompare + 33582839U, // LTER + 134240238U, // LTG + 134239064U, // LTGF + 33582953U, // LTGFR + 33583078U, // LTGR + 33583658U, // LTR + 33582538U, // LTXBR + 33582538U, // LTXBRCompare + 33583929U, // LTXR + 33583815U, // LTXTR + 33571206U, // LURA + 33576365U, // LURAG + 134236634U, // LXD + 134235054U, // LXDB + 33582198U, // LXDBR + 33582694U, // LXDR + 1107325401U, // LXDTR + 134238860U, // LXE + 134235178U, // LXEB + 33582332U, // LXEBR + 33582845U, // LXER + 33583896U, // LXR + 134248658U, // LY + 3174002U, // LZDR + 3174147U, // LZER + 134239457U, // LZRF + 134240148U, // LZRG + 3175231U, // LZXR + 26363U, // M + 1090537839U, // MAD + 1090535937U, // MADB + 1090546688U, // MADBR + 1090547183U, // MADR + 1090537968U, // MAE + 1090536386U, // MAEB + 1090546820U, // MAEBR + 1090547320U, // MAER + 1090549844U, // MAY + 1090543730U, // MAYH + 1090547793U, // MAYHR + 1090545390U, // MAYL + 1090547939U, // MAYLR + 1090548549U, // MAYR + 453019900U, // MC + 18850U, // MD + 17164U, // MDB + 16804941U, // MDBR + 19027U, // MDE + 17372U, // MDEB + 16805017U, // MDEBR + 16805526U, // MDER + 16805430U, // MDR + 1107325360U, // MDTR + 1107312964U, // MDTRA + 20634U, // ME + 19038U, // MEE + 17385U, // MEEB + 16805024U, // MEEBR + 16805532U, // MEER + 16805582U, // MER + 30866U, // MFY + 22311U, // MG + 22923U, // MGH + 67133772U, // MGHI + 1107321512U, // MGRK + 24018U, // MH + 67133805U, // MHI + 30886U, // MHY + 25695U, // ML + 22246U, // MLG + 16805812U, // MLGR + 16806079U, // MLR + 117500597U, // MP + 16806129U, // MR + 30259U, // MS + 18768U, // MSC + 3184875U, // MSCH + 1090537930U, // MSD + 1090536316U, // MSDB + 1090546792U, // MSDBR + 1090547283U, // MSDR + 1090540054U, // MSE + 1090536477U, // MSEB + 1090546926U, // MSEBR + 1090547441U, // MSER + 50356513U, // MSFI + 22465U, // MSG + 18624U, // MSGC + 21330U, // MSGF + 50356488U, // MSGFI + 16805730U, // MSGFR + 16805849U, // MSGR + 1107314904U, // MSGRKC + 16806184U, // MSR + 1107314912U, // MSRKC + 3162526U, // MSTA + 31001U, // MSY + 302041441U, // MVC + 469803592U, // MVCDK + 302049434U, // MVCIN + 270914U, // MVCK + 33579867U, // MVCL + 1107316241U, // MVCLE + 1107326895U, // MVCLU + 1543550526U, // MVCOS + 272943U, // MVCP + 275692U, // MVCS + 469803750U, // MVCSK + 67150162U, // MVGHI + 67150177U, // MVHHI + 67150194U, // MVHI + 453026284U, // MVI + 453032134U, // MVIY + 302049472U, // MVN + 117500425U, // MVO + 33576824U, // MVPG + 33584977U, // MVST + 302053945U, // MVZ + 16805289U, // MXBR + 18911U, // MXD + 17332U, // MXDB + 16804989U, // MXDBR + 16805484U, // MXDR + 16806685U, // MXR + 1107325612U, // MXTR + 1107313016U, // MXTRA + 1107327202U, // MY + 1107320952U, // MYH + 1107325016U, // MYHR + 1107322612U, // MYL + 1107325162U, // MYLR + 1107325771U, // MYR + 26759U, // N + 302041349U, // NC + 22349U, // NG + 16805825U, // NGR + 1107321518U, // NGRK + 453026173U, // NI + 8495285U, // NIAI + 100684678U, // NIHF + 352344526U, // NIHH + 352347064U, // NIHL + 100684823U, // NILF + 352344931U, // NILH + 352347188U, // NILL + 453032124U, // NIY + 16806140U, // NR + 1107321554U, // NRK + 134240243U, // NTSTG + 30982U, // NY + 26823U, // O + 302041359U, // OC + 22361U, // OG + 16805832U, // OGR + 1107321524U, // OGRK + 453026177U, // OI + 100684684U, // OIHF + 352344532U, // OIHH + 352347070U, // OIHL + 100684829U, // OILF + 352344937U, // OILH + 352347194U, // OILL + 453032129U, // OIY + 16806145U, // OR + 1107321559U, // ORK + 30986U, // OY + 117498417U, // PACK + 15423U, // PALB + 3180832U, // PC + 15453U, // PCC + 15623U, // PCKMO + 1149314U, // PFD + 153724355U, // PFDRL + 3363962U, // PFMF + 15629U, // PFPO + 33581225U, // PGIN + 33584989U, // PGOUT + 520126558U, // PKA + 520140707U, // PKU + 1509976374U, // PLO + 33584878U, // POPCNT + 1107312775U, // PPA + 33581483U, // PPNO + 15657U, // PR + 33581516U, // PRNO + 33584901U, // PT + 3167492U, // PTF + 15471U, // PTFF + 33579495U, // PTI + 15428U, // PTLB + 1107325270U, // QADTR + 1107325528U, // QAXTR + 3187089U, // QCTRI + 3187164U, // QSI + 15634U, // RCHP + 1090540991U, // RISBG + 1090540991U, // RISBG32 + 1090545802U, // RISBGN + 1090541161U, // RISBHG + 1090541235U, // RISBLG + 1107321935U, // RLL + 1107318490U, // RLLG + 1090540998U, // RNSBG + 1090541005U, // ROSBG + 3189582U, // RP + 33573421U, // RRBE + 33580816U, // RRBM + 1107325366U, // RRDTR + 1107325618U, // RRXTR + 15506U, // RSCH + 1090541012U, // RXSBG + 29533U, // S + 3180688U, // SAC + 3183270U, // SACF + 15596U, // SAL + 15336U, // SAM24 + 15324U, // SAM31 + 15342U, // SAM64 + 33582064U, // SAR + 33583418U, // SCCTR + 15618U, // SCHM + 3187255U, // SCK + 3180747U, // SCKC + 15476U, // SCKPF + 18891U, // SD + 17262U, // SDB + 16804969U, // SDBR + 16805460U, // SDR + 1107325374U, // SDTR + 1107312971U, // SDTRA + 21015U, // SE + 17438U, // SEB + 16805103U, // SEBR + 16805618U, // SER + 3174689U, // SFASR + 3164458U, // SFPC + 22427U, // SG + 21325U, // SGF + 16805724U, // SGFR + 22928U, // SGH + 16805844U, // SGR + 1107321530U, // SGRK + 24510U, // SH + 1107324970U, // SHHHR + 1107325105U, // SHHLR + 30891U, // SHY + 3181924U, // SIE + 3178575U, // SIGA + 1107323491U, // SIGP + 26209U, // SL + 469778537U, // SLA + 1107318154U, // SLAG + 1107321381U, // SLAK + 17699U, // SLB + 21945U, // SLBG + 16805755U, // SLBGR + 16805213U, // SLBR + 469778481U, // SLDA + 469787489U, // SLDL + 1107326615U, // SLDT + 100688155U, // SLFI + 22275U, // SLG + 21302U, // SLGF + 100688129U, // SLGFI + 16805702U, // SLGFR + 16805818U, // SLGR + 1107321505U, // SLGRK + 1107324962U, // SLHHHR + 1107325097U, // SLHHLR + 469787732U, // SLL + 1107318496U, // SLLG + 1107321458U, // SLLK + 16806105U, // SLR + 1107321548U, // SLRK + 1107326834U, // SLXT + 30939U, // SLY + 117500790U, // SP + 33583439U, // SPCTR + 3178595U, // SPKA + 3172391U, // SPM + 3192585U, // SPT + 3192889U, // SPX + 134236599U, // SQD + 134234974U, // SQDB + 33582177U, // SQDBR + 33582663U, // SQDR + 134238706U, // SQE + 134235159U, // SQEB + 33582311U, // SQEBR + 33582821U, // SQER + 33582525U, // SQXBR + 33583918U, // SQXR + 16806173U, // SR + 469778723U, // SRA + 1107318176U, // SRAG + 1107321387U, // SRAK + 469778487U, // SRDA + 469787495U, // SRDL + 1107326627U, // SRDT + 1107321564U, // SRK + 469788230U, // SRL + 1107318523U, // SRLG + 1107321464U, // SRLK + 3188764U, // SRNM + 3179850U, // SRNMB + 3192551U, // SRNMT + 1375791978U, // SRP + 33584965U, // SRST + 33585082U, // SRSTU + 1107326846U, // SRXT + 3174508U, // SSAIR + 3173365U, // SSAR + 3184881U, // SSCH + 1107316142U, // SSKE + 33574318U, // SSKEOpt + 3188847U, // SSM + 134248257U, // ST + 1107322622U, // STAM + 1107327206U, // STAMY + 3189262U, // STAP + 134236508U, // STC + 134240510U, // STCH + 3187260U, // STCK + 3180753U, // STCKC + 3181985U, // STCKE + 3183584U, // STCKF + 2365613864U, // STCM + 2365611478U, // STCMH + 2365618419U, // STCMY + 3192389U, // STCPS + 3192844U, // STCRW + 1107318759U, // STCTG + 1107322513U, // STCTL + 134248554U, // STCY + 134236623U, // STD + 134248565U, // STDY + 134238848U, // STE + 134248588U, // STEY + 134240604U, // STFH + 3187571U, // STFL + 3182104U, // STFLE + 3180848U, // STFPC + 134240245U, // STG + 268461552U, // STGRL + 134236489U, // STGSC + 134242341U, // STH + 134240785U, // STHH + 268461611U, // STHRL + 134248624U, // STHY + 3189301U, // STIDP + 1107322997U, // STM + 1107318590U, // STMG + 1107320312U, // STMH + 1107327232U, // STMY + 453027935U, // STNSM + 157547621U, // STOC + 1509968147U, // STOCAsm + 436226630U, // STOCAsmE + 436230364U, // STOCAsmH + 436226757U, // STOCAsmHE + 436233038U, // STOCAsmL + 436227593U, // STOCAsmLE + 436230898U, // STOCAsmLH + 436234017U, // STOCAsmM + 436228325U, // STOCAsmNE + 436231761U, // STOCAsmNH + 436227003U, // STOCAsmNHE + 436233386U, // STOCAsmNL + 436227842U, // STOCAsmNLE + 436231195U, // STOCAsmNLH + 436234151U, // STOCAsmNM + 436234577U, // STOCAsmNO + 436234949U, // STOCAsmNP + 436238758U, // STOCAsmNZ + 436234458U, // STOCAsmO + 436234792U, // STOCAsmP + 436238641U, // STOCAsmZ + 157547682U, // STOCFH + 1509972303U, // STOCFHAsm + 436226773U, // STOCFHAsmE + 436230584U, // STOCFHAsmH + 436226814U, // STOCFHAsmHE + 436233122U, // STOCFHAsmL + 436227647U, // STOCFHAsmLE + 436230953U, // STOCFHAsmLH + 436234074U, // STOCFHAsmM + 436228372U, // STOCFHAsmNE + 436231801U, // STOCFHAsmNH + 436227048U, // STOCFHAsmNHE + 436233426U, // STOCFHAsmNL + 436227887U, // STOCFHAsmNLE + 436231240U, // STOCFHAsmNLH + 436234191U, // STOCFHAsmNM + 436234617U, // STOCFHAsmNO + 436234989U, // STOCFHAsmNP + 436238798U, // STOCFHAsmNZ + 436234493U, // STOCFHAsmO + 436234877U, // STOCFHAsmP + 436238683U, // STOCFHAsmZ + 157547647U, // STOCG + 1509971464U, // STOCGAsm + 436226666U, // STOCGAsmE + 436230510U, // STOCGAsmH + 436226790U, // STOCGAsmHE + 436233088U, // STOCGAsmL + 436227623U, // STOCGAsmLE + 436230914U, // STOCGAsmLH + 436234048U, // STOCGAsmM + 436228348U, // STOCGAsmNE + 436231777U, // STOCGAsmNH + 436227021U, // STOCGAsmNHE + 436233402U, // STOCGAsmNL + 436227860U, // STOCGAsmNLE + 436231213U, // STOCGAsmNLH + 436234167U, // STOCGAsmNM + 436234593U, // STOCGAsmNO + 436234965U, // STOCGAsmNP + 436238774U, // STOCGAsmNZ + 436234472U, // STOCGAsmO + 436234843U, // STOCGAsmP + 436238662U, // STOCGAsmZ + 453027942U, // STOSM + 134245331U, // STPQ + 3192590U, // STPT + 3192894U, // STPX + 469800358U, // STRAG + 268461650U, // STRL + 134248427U, // STRV + 134240310U, // STRVG + 134242394U, // STRVH + 3184887U, // STSCH + 3187169U, // STSI + 33571212U, // STURA + 33576845U, // STURG + 134248734U, // STY + 30646U, // SU + 16806618U, // SUR + 280934U, // SVC + 30741U, // SW + 16806634U, // SWR + 16805316U, // SXBR + 16806708U, // SXR + 1107325626U, // SXTR + 1107313023U, // SXTRA + 30991U, // SY + 3192626U, // TABORT + 15614U, // TAM + 33582075U, // TAR + 33572676U, // TB + 218131957U, // TBDR + 218131974U, // TBEDR + 352364705U, // TBEGIN + 352356608U, // TBEGINC + 134234680U, // TCDB + 134235080U, // TCEB + 134236063U, // TCXB + 134248073U, // TDCDT + 134248111U, // TDCET + 134248292U, // TDCXT + 134248080U, // TDGDT + 134248118U, // TDGET + 134248299U, // TDGXT + 15466U, // TEND + 33582729U, // THDER + 33582629U, // THDR + 453027958U, // TM + 385898999U, // TMHH + 385901508U, // TMHL + 385899455U, // TMLH + 385901632U, // TMLL + 453032193U, // TMY + 3206027U, // TP + 3187084U, // TPI + 469808886U, // TPROT + 302051631U, // TR + 1107315251U, // TRACE + 1107318242U, // TRACG + 15330U, // TRAP2 + 3178533U, // TRAP4 + 33575441U, // TRE + 1107323351U, // TROO + 33581527U, // TROOOpt + 1107326717U, // TROT + 33584893U, // TROTOpt + 302053178U, // TRT + 419648122U, // TRTE + 3363450U, // TRTEOpt + 1107323395U, // TRTO + 33581571U, // TRTOOpt + 302051887U, // TRTR + 419648015U, // TRTRE + 3363343U, // TRTREOpt + 1107326807U, // TRTT + 33584983U, // TRTTOpt + 3192396U, // TS + 3184888U, // TSCH + 117498500U, // UNPK + 302039132U, // UNPKA + 302053281U, // UNPKU + 15690U, // UPT + 1107313060U, // VA + 1107313093U, // VAB + 1107314837U, // VAC + 1107314846U, // VACC + 1107313110U, // VACCB + 1107314852U, // VACCC + 1107323809U, // VACCCQ + 1107317420U, // VACCF + 1107318249U, // VACCG + 1107318967U, // VACCH + 1107323802U, // VACCQ + 1107323796U, // VACQ + 1107317409U, // VAF + 1107318196U, // VAG + 1107318901U, // VAH + 1107323412U, // VAP + 1107323791U, // VAQ + 1107318787U, // VAVG + 1107313749U, // VAVGB + 1107317598U, // VAVGF + 1107318363U, // VAVGG + 1107319189U, // VAVGH + 1107321741U, // VAVGL + 1107313880U, // VAVGLB + 1107317755U, // VAVGLF + 1107318473U, // VAVGLG + 1107319569U, // VAVGLH + 1107322931U, // VBPERM + 1107318287U, // VCDG + 1107313712U, // VCDGB + 1107318466U, // VCDLG + 1107313733U, // VCDLGB + 1107323817U, // VCEQ + 1107314063U, // VCEQB + 1107325965U, // VCEQBS + 1107317962U, // VCEQF + 1107326248U, // VCEQFS + 1107318654U, // VCEQG + 1107326340U, // VCEQGS + 1107320718U, // VCEQH + 1107326414U, // VCEQHS + 1107315084U, // VCGD + 1107313310U, // VCGDB + 1107319044U, // VCH + 1107313770U, // VCHB + 1107325950U, // VCHBS + 1107317619U, // VCHF + 1107326233U, // VCHFS + 1107318385U, // VCHG + 1107326325U, // VCHGS + 1107319210U, // VCHH + 1107326399U, // VCHHS + 1107321748U, // VCHL + 1107313888U, // VCHLB + 1107325957U, // VCHLBS + 1107317763U, // VCHLF + 1107326240U, // VCHLFS + 1107318481U, // VCHLG + 1107326332U, // VCHLGS + 1107319577U, // VCHLH + 1107326406U, // VCHLHS + 1107322968U, // VCKSM + 1107315090U, // VCLGD + 1107313324U, // VCLGDB + 1107327380U, // VCLZ + 33572983U, // VCLZB + 33576298U, // VCLZF + 33577041U, // VCLZG + 33579175U, // VCLZH + 1107323440U, // VCP + 1107327539U, // VCTZ + 33572990U, // VCTZB + 33576305U, // VCTZF + 33577048U, // VCTZG + 33579182U, // VCTZH + 1107314513U, // VCVB + 1107318235U, // VCVBG + 1107315156U, // VCVD + 1107318299U, // VCVDG + 1107323458U, // VDP + 1107314859U, // VEC + 33571293U, // VECB + 33575603U, // VECF + 33576432U, // VECG + 33577150U, // VECH + 1107321660U, // VECL + 33572049U, // VECLB + 33575924U, // VECLF + 33576635U, // VECLG + 33577700U, // VECLH + 1090545538U, // VERIM + 1090536770U, // VERIMB + 1090540678U, // VERIMF + 1090541361U, // VERIMG + 1090543082U, // VERIMH + 1107321933U, // VERLL + 1107313903U, // VERLLB + 1107317809U, // VERLLF + 1107318488U, // VERLLG + 1107319735U, // VERLLH + 1107326927U, // VERLLV + 1107314526U, // VERLLVB + 1107318048U, // VERLLVF + 1107318800U, // VERLLVG + 1107320890U, // VERLLVH + 1107322469U, // VESL + 1107313953U, // VESLB + 1107317852U, // VESLF + 1107318529U, // VESLG + 1107320178U, // VESLH + 1107326943U, // VESLV + 1107314544U, // VESLVB + 1107318066U, // VESLVF + 1107318818U, // VESLVG + 1107320908U, // VESLVH + 1107312929U, // VESRA + 1107313078U, // VESRAB + 1107317401U, // VESRAF + 1107318174U, // VESRAG + 1107318893U, // VESRAH + 1107326913U, // VESRAV + 1107314504U, // VESRAVB + 1107318032U, // VESRAVF + 1107318778U, // VESRAVG + 1107320874U, // VESRAVH + 1107322436U, // VESRL + 1107313938U, // VESRLB + 1107317844U, // VESRLF + 1107318521U, // VESRLG + 1107320170U, // VESRLH + 1107326935U, // VESRLV + 1107314535U, // VESRLVB + 1107318057U, // VESRLVF + 1107318809U, // VESRLVG + 1107320899U, // VESRLVH + 1107312714U, // VFA + 1107313137U, // VFADB + 1107315172U, // VFAE + 1107313594U, // VFAEB + 1107325925U, // VFAEBS + 1107317447U, // VFAEF + 1107326208U, // VFAEFS + 1107319049U, // VFAEH + 1107326374U, // VFAEHS + 1107314774U, // VFAEZB + 1107326160U, // VFAEZBS + 1107318089U, // VFAEZF + 1107326297U, // VFAEZFS + 1107320966U, // VFAEZH + 1107326458U, // VFAEZHS + 1107314102U, // VFASB + 1107315258U, // VFCE + 1107313228U, // VFCEDB + 1107325813U, // VFCEDBS + 1107314187U, // VFCESB + 1107325982U, // VFCESBS + 1107318980U, // VFCH + 1107313340U, // VFCHDB + 1107325889U, // VFCHDBS + 1107315383U, // VFCHE + 1107313244U, // VFCHEDB + 1107325831U, // VFCHEDBS + 1107314203U, // VFCHESB + 1107326000U, // VFCHESBS + 1107314255U, // VFCHSB + 1107326058U, // VFCHSBS + 1107315079U, // VFD + 1107313214U, // VFDDB + 1107314173U, // VFDSB + 1107315288U, // VFEE + 1107313634U, // VFEEB + 1107325933U, // VFEEBS + 1107317468U, // VFEEF + 1107326216U, // VFEEFS + 1107319063U, // VFEEH + 1107326382U, // VFEEHS + 1107314782U, // VFEEZB + 1107326169U, // VFEEZBS + 1107318097U, // VFEEZF + 1107326306U, // VFEEZFS + 1107320974U, // VFEEZH + 1107326467U, // VFEEZHS + 1107316973U, // VFENE + 1107313679U, // VFENEB + 1107325941U, // VFENEBS + 1107317508U, // VFENEF + 1107326224U, // VFENEFS + 1107319097U, // VFENEH + 1107326390U, // VFENEHS + 1107314798U, // VFENEZB + 1107326178U, // VFENEZBS + 1107318113U, // VFENEZF + 1107326315U, // VFENEZFS + 1107320990U, // VFENEZH + 1107326476U, // VFENEZHS + 1107321127U, // VFI + 1107313390U, // VFIDB + 1107314305U, // VFISB + 1107313280U, // VFKEDB + 1107325871U, // VFKEDBS + 1107314239U, // VFKESB + 1107326040U, // VFKESBS + 1107313356U, // VFKHDB + 1107325907U, // VFKHDBS + 1107313262U, // VFKHEDB + 1107325851U, // VFKHEDBS + 1107314221U, // VFKHESB + 1107326020U, // VFKHESBS + 1107314271U, // VFKHSB + 1107326076U, // VFKHSBS + 33571368U, // VFLCDB + 33572333U, // VFLCSB + 1107321889U, // VFLL + 33584675U, // VFLLS + 33571626U, // VFLNDB + 33572534U, // VFLNSB + 33571660U, // VFLPDB + 33572568U, // VFLPSB + 1107325070U, // VFLR + 1107315132U, // VFLRD + 1107322676U, // VFM + 1107312757U, // VFMA + 1107313151U, // VFMADB + 1107314116U, // VFMASB + 1107327012U, // VFMAX + 1107313564U, // VFMAXDB + 1107314477U, // VFMAXSB + 1107313418U, // VFMDB + 1107323055U, // VFMIN + 1107313432U, // VFMINDB + 1107314340U, // VFMINSB + 1107326513U, // VFMS + 1107314326U, // VFMSB + 1107313530U, // VFMSDB + 1107314438U, // VFMSSB + 1107312768U, // VFNMA + 1107313167U, // VFNMADB + 1107314132U, // VFNMASB + 1107326519U, // VFNMS + 1107313546U, // VFNMSDB + 1107314454U, // VFNMSSB + 1107323388U, // VFPSO + 1107313466U, // VFPSODB + 1107314374U, // VFPSOSB + 1107326282U, // VFS + 1107313516U, // VFSDB + 1107323865U, // VFSQ + 33571676U, // VFSQDB + 33572584U, // VFSQSB + 1107314424U, // VFSSB + 1107321040U, // VFTCI + 1107313372U, // VFTCIDB + 1107314287U, // VFTCISB + 385902340U, // VGBM + 3758117603U, // VGEF + 536892969U, // VGEG + 1107322670U, // VGFM + 1107312750U, // VGFMA + 1107313070U, // VGFMAB + 1107317393U, // VGFMAF + 1107318160U, // VGFMAG + 1107318879U, // VGFMAH + 1107313973U, // VGFMB + 1107317875U, // VGFMF + 1107318564U, // VGFMG + 1107320285U, // VGFMH + 1476421453U, // VGM + 1476412732U, // VGMB + 1476416640U, // VGMF + 1476417323U, // VGMG + 1476419044U, // VGMH + 1107325500U, // VISTR + 1107314094U, // VISTRB + 33584149U, // VISTRBS + 1107317977U, // VISTRF + 33584432U, // VISTRFS + 1107320755U, // VISTRH + 33584598U, // VISTRHS + 134244068U, // VL + 1207976400U, // VLBB + 1107314934U, // VLC + 33571299U, // VLCB + 33575609U, // VLCF + 33576444U, // VLCG + 33577168U, // VLCH + 1107315277U, // VLDE + 33571790U, // VLDEB + 1073759235U, // VLEB + 1107315068U, // VLED + 1107313296U, // VLEDB + 1073763064U, // VLEF + 1073763887U, // VLEG + 1073764653U, // VLEH + 1140868264U, // VLEIB + 1140872145U, // VLEIF + 1140872851U, // VLEIG + 1140873769U, // VLEIH + 1107326921U, // VLGV + 1107314519U, // VLGVB + 1107318041U, // VLGVF + 1107318793U, // VLGVG + 1107320883U, // VLGVH + 1459645093U, // VLIP + 1107321945U, // VLL + 1207990584U, // VLLEZ + 134236262U, // VLLEZB + 134239577U, // VLLEZF + 134240329U, // VLLEZG + 134242454U, // VLLEZH + 134239338U, // VLLEZLF + 1107322774U, // VLM + 1107323567U, // VLP + 33572233U, // VLPB + 33576132U, // VLPF + 33576812U, // VLPG + 33578882U, // VLPH + 33583326U, // VLR + 1207986759U, // VLREP + 134235514U, // VLREPB + 134239413U, // VLREPF + 134240093U, // VLREPG + 134242163U, // VLREPH + 1509975608U, // VLRL + 1107325130U, // VLRLR + 1090541610U, // VLVG + 1090536540U, // VLVGB + 1090540389U, // VLVGF + 1090541154U, // VLVGG + 1090541980U, // VLVGH + 1107323502U, // VLVGP + 1107315183U, // VMAE + 1107313601U, // VMAEB + 1107317454U, // VMAEF + 1107319056U, // VMAEH + 1107318887U, // VMAH + 1107313763U, // VMAHB + 1107317612U, // VMAHF + 1107319203U, // VMAHH + 1107321598U, // VMAL + 1107313866U, // VMALB + 1107316148U, // VMALE + 1107313652U, // VMALEB + 1107317481U, // VMALEF + 1107319070U, // VMALEH + 1107317741U, // VMALF + 1107319453U, // VMALH + 1107313776U, // VMALHB + 1107317656U, // VMALHF + 1107319258U, // VMALHH + 1107326965U, // VMALHW + 1107323177U, // VMALO + 1107314021U, // VMALOB + 1107317920U, // VMALOF + 1107320670U, // VMALOH + 1107323082U, // VMAO + 1107314014U, // VMAOB + 1107317913U, // VMAOF + 1107320663U, // VMAOH + 1107316889U, // VME + 1107313673U, // VMEB + 1107317502U, // VMEF + 1107319091U, // VMEH + 1107320325U, // VMH + 1107313799U, // VMHB + 1107317685U, // VMHF + 1107319293U, // VMHH + 1107321950U, // VML + 1107313911U, // VMLB + 1107316396U, // VMLE + 1107313660U, // VMLEB + 1107317489U, // VMLEF + 1107319078U, // VMLEH + 1107317817U, // VMLF + 1107319749U, // VMLH + 1107313784U, // VMLHB + 1107317670U, // VMLHF + 1107319272U, // VMLHH + 1107326973U, // VMLHW + 1107323184U, // VMLO + 1107314029U, // VMLOB + 1107317928U, // VMLOF + 1107320678U, // VMLOH + 1107323062U, // VMN + 1107314008U, // VMNB + 1107317907U, // VMNF + 1107318609U, // VMNG + 1107320550U, // VMNH + 1107322175U, // VMNL + 1107313917U, // VMNLB + 1107317823U, // VMNLF + 1107318507U, // VMNLG + 1107320002U, // VMNLH + 1107323200U, // VMO + 1107314036U, // VMOB + 1107317935U, // VMOF + 1107320685U, // VMOH + 1107323572U, // VMP + 1107320749U, // VMRH + 1107313812U, // VMRHB + 1107317698U, // VMRHF + 1107318391U, // VMRHG + 1107319306U, // VMRHH + 1107322430U, // VMRL + 1107313931U, // VMRLB + 1107317837U, // VMRLF + 1107318514U, // VMRLG + 1107320163U, // VMRLH + 1107322475U, // VMSL + 1107318536U, // VMSLG + 1107323775U, // VMSP + 1107327023U, // VMX + 1107314684U, // VMXB + 1107318074U, // VMXF + 1107318851U, // VMXG + 1107320934U, // VMXH + 1107322600U, // VMXL + 1107313966U, // VMXLB + 1107317859U, // VMXLF + 1107318550U, // VMXLG + 1107320265U, // VMXLH + 1107323073U, // VN + 1107314953U, // VNC + 1107323067U, // VNN + 1107323346U, // VNO + 1107327028U, // VNX + 1107323402U, // VO + 1107314969U, // VOC + 3166593U, // VONE + 1107321047U, // VPDI + 1107322939U, // VPERM + 1107321482U, // VPK + 1107317735U, // VPKF + 1107318438U, // VPKG + 1107319447U, // VPKH + 1107326492U, // VPKLS + 1107317998U, // VPKLSF + 1107326273U, // VPKLSFS + 1107318713U, // VPKLSG + 1107326356U, // VPKLSGS + 1107320770U, // VPKLSH + 1107326439U, // VPKLSHS + 1107326486U, // VPKS + 1107317991U, // VPKSF + 1107326265U, // VPKSFS + 1107318706U, // VPKSG + 1107326348U, // VPKSGS + 1107320763U, // VPKSH + 1107326431U, // VPKSHS + 1509980558U, // VPKZ + 1107326587U, // VPOPCT + 33572671U, // VPOPCTB + 33576187U, // VPOPCTF + 33576919U, // VPOPCTG + 33578959U, // VPOPCTH + 1107323706U, // VPSOP + 1107323470U, // VREP + 1107314050U, // VREPB + 1107317949U, // VREPF + 1107318629U, // VREPG + 1107320699U, // VREPH + 1358979461U, // VREPI + 285230274U, // VREPIB + 285234136U, // VREPIF + 285234842U, // VREPIG + 285235792U, // VREPIH + 1107323759U, // VRP + 1107326544U, // VS + 1107314472U, // VSB + 1107321019U, // VSBCBI + 1107323823U, // VSBCBIQ + 1107321034U, // VSBI + 1107323840U, // VSBIQ + 1107321027U, // VSCBI + 1107313819U, // VSCBIB + 1107317705U, // VSCBIF + 1107318411U, // VSCBIG + 1107319324U, // VSCBIH + 1107323832U, // VSCBIQ + 2701152981U, // VSCEF + 3774895650U, // VSCEG + 1107323452U, // VSDP + 1107318338U, // VSEG + 33571902U, // VSEGB + 33575709U, // VSEGF + 33577334U, // VSEGH + 1107321709U, // VSEL + 1107318006U, // VSF + 1107318726U, // VSG + 1107320778U, // VSH + 1107322481U, // VSL + 1107313960U, // VSLB + 1107313411U, // VSLDB + 1107323781U, // VSP + 1107323871U, // VSQ + 1107312936U, // VSRA + 1107313086U, // VSRAB + 1107322443U, // VSRL + 1107313946U, // VSRLB + 1107323753U, // VSRP + 134248274U, // VST + 1207976995U, // VSTEB + 1207980812U, // VSTEF + 1207981640U, // VSTEG + 1207982401U, // VSTEH + 1107322590U, // VSTL + 1107322996U, // VSTM + 1107315004U, // VSTRC + 1107313129U, // VSTRCB + 1107325804U, // VSTRCBS + 1107317439U, // VSTRCF + 1107326199U, // VSTRCFS + 1107319011U, // VSTRCH + 1107326365U, // VSTRCHS + 1107314765U, // VSTRCZB + 1107326150U, // VSTRCZBS + 1107318080U, // VSTRCZF + 1107326287U, // VSTRCZFS + 1107320957U, // VSTRCZH + 1107326448U, // VSTRCZHS + 1509975633U, // VSTRL + 1107325137U, // VSTRLR + 1107323007U, // VSUM + 1107314001U, // VSUMB + 1107318596U, // VSUMG + 1107317564U, // VSUMGF + 1107319176U, // VSUMGH + 1107320318U, // VSUMH + 1107323847U, // VSUMQ + 1107317969U, // VSUMQF + 1107318661U, // VSUMQG + 33581178U, // VTM + 3173258U, // VTP + 1107320712U, // VUPH + 33571981U, // VUPHB + 33575867U, // VUPHF + 33577475U, // VUPHH + 1509980551U, // VUPKZ + 1107322288U, // VUPL + 33572100U, // VUPLB + 33576006U, // VUPLF + 1107320129U, // VUPLH + 33571967U, // VUPLHB + 33575853U, // VUPLHF + 33577455U, // VUPLHH + 33585156U, // VUPLHW + 1107321926U, // VUPLL + 33572071U, // VUPLLB + 33575977U, // VUPLLF + 33577903U, // VUPLLH + 1107327051U, // VX + 3172836U, // VZERO + 1107313719U, // WCDGB + 1107313741U, // WCDLGB + 1107313317U, // WCGDB + 1107313332U, // WCLGDB + 1107313144U, // WFADB + 1107314109U, // WFASB + 1107314552U, // WFAXB + 1107314869U, // WFC + 33571361U, // WFCDB + 1107313236U, // WFCEDB + 1107325822U, // WFCEDBS + 1107314195U, // WFCESB + 1107325991U, // WFCESBS + 1107314604U, // WFCEXB + 1107326094U, // WFCEXBS + 1107313348U, // WFCHDB + 1107325898U, // WFCHDBS + 1107313253U, // WFCHEDB + 1107325841U, // WFCHEDBS + 1107314212U, // WFCHESB + 1107326010U, // WFCHESBS + 1107314612U, // WFCHEXB + 1107326103U, // WFCHEXBS + 1107314263U, // WFCHSB + 1107326067U, // WFCHSBS + 1107314638U, // WFCHXB + 1107326132U, // WFCHXBS + 33572326U, // WFCSB + 33572752U, // WFCXB + 1107313221U, // WFDDB + 1107314180U, // WFDSB + 1107314597U, // WFDXB + 1107313397U, // WFIDB + 1107314312U, // WFISB + 1107314663U, // WFIXB + 1107321423U, // WFK + 33571580U, // WFKDB + 1107313288U, // WFKEDB + 1107325880U, // WFKEDBS + 1107314247U, // WFKESB + 1107326049U, // WFKESBS + 1107314630U, // WFKEXB + 1107326123U, // WFKEXBS + 1107313364U, // WFKHDB + 1107325916U, // WFKHDBS + 1107313271U, // WFKHEDB + 1107325861U, // WFKHEDBS + 1107314230U, // WFKHESB + 1107326030U, // WFKHESBS + 1107314621U, // WFKHEXB + 1107326113U, // WFKHEXBS + 1107314279U, // WFKHSB + 1107326085U, // WFKHSBS + 1107314646U, // WFKHXB + 1107326141U, // WFKHXBS + 33572495U, // WFKSB + 33572846U, // WFKXB + 33571376U, // WFLCDB + 33572341U, // WFLCSB + 33572759U, // WFLCXB + 33573273U, // WFLLD + 33584682U, // WFLLS + 33571634U, // WFLNDB + 33572542U, // WFLNSB + 33572875U, // WFLNXB + 33571668U, // WFLPDB + 33572576U, // WFLPSB + 33572892U, // WFLPXB + 1107315139U, // WFLRD + 1107327044U, // WFLRX + 1107313159U, // WFMADB + 1107314124U, // WFMASB + 1107314559U, // WFMAXB + 1107313573U, // WFMAXDB + 1107314486U, // WFMAXSB + 1107314756U, // WFMAXXB + 1107313425U, // WFMDB + 1107313441U, // WFMINDB + 1107314349U, // WFMINSB + 1107314690U, // WFMINXB + 1107314333U, // WFMSB + 1107313538U, // WFMSDB + 1107314446U, // WFMSSB + 1107314739U, // WFMSXB + 1107314677U, // WFMXB + 1107313176U, // WFNMADB + 1107314141U, // WFNMASB + 1107314567U, // WFNMAXB + 1107313555U, // WFNMSDB + 1107314463U, // WFNMSSB + 1107314747U, // WFNMSXB + 1107313475U, // WFPSODB + 1107314383U, // WFPSOSB + 1107314707U, // WFPSOXB + 1107313523U, // WFSDB + 33571684U, // WFSQDB + 33572592U, // WFSQSB + 33572900U, // WFSQXB + 1107314431U, // WFSSB + 1107314732U, // WFSXB + 1107313381U, // WFTCIDB + 1107314296U, // WFTCISB + 1107314654U, // WFTCIXB + 33571797U, // WLDEB + 1107313303U, // WLEDB + 30753U, // X + 302041451U, // XC + 22591U, // XG + 16805876U, // XGR + 1107321536U, // XGRK + 453026289U, // XI + 100684690U, // XIHF + 100684835U, // XILF + 453032140U, // XIY + 16806640U, // XR + 1107321569U, // XRK + 15511U, // XSCH + 31011U, // XY + 117500441U, // ZAP }; static const uint16_t OpInfo1[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 0U, // DBG_VALUE - 0U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 0U, // BUNDLE - 0U, // LIFETIME_START - 0U, // LIFETIME_END - 0U, // STACKMAP - 0U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 0U, // PATCHABLE_FUNCTION_ENTER - 0U, // PATCHABLE_RET - 0U, // PATCHABLE_FUNCTION_EXIT - 0U, // PATCHABLE_TAIL_CALL - 0U, // PATCHABLE_EVENT_CALL - 0U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDE - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SSUBO - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_BSWAP - 0U, // G_ADDRSPACE_CAST - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 0U, // ADJDYNALLOC - 0U, // AEXT128 - 0U, // AFIMux - 0U, // AHIMux - 0U, // AHIMuxK - 0U, // ATOMIC_CMP_SWAPW - 0U, // ATOMIC_LOADW_AFI - 0U, // ATOMIC_LOADW_AR - 0U, // ATOMIC_LOADW_MAX - 0U, // ATOMIC_LOADW_MIN - 0U, // ATOMIC_LOADW_NILH - 0U, // ATOMIC_LOADW_NILHi - 0U, // ATOMIC_LOADW_NR - 0U, // ATOMIC_LOADW_NRi - 0U, // ATOMIC_LOADW_OILH - 0U, // ATOMIC_LOADW_OR - 0U, // ATOMIC_LOADW_SR - 0U, // ATOMIC_LOADW_UMAX - 0U, // ATOMIC_LOADW_UMIN - 0U, // ATOMIC_LOADW_XILF - 0U, // ATOMIC_LOADW_XR - 0U, // ATOMIC_LOAD_AFI - 0U, // ATOMIC_LOAD_AGFI - 0U, // ATOMIC_LOAD_AGHI - 0U, // ATOMIC_LOAD_AGR - 0U, // ATOMIC_LOAD_AHI - 0U, // ATOMIC_LOAD_AR - 0U, // ATOMIC_LOAD_MAX_32 - 0U, // ATOMIC_LOAD_MAX_64 - 0U, // ATOMIC_LOAD_MIN_32 - 0U, // ATOMIC_LOAD_MIN_64 - 0U, // ATOMIC_LOAD_NGR - 0U, // ATOMIC_LOAD_NGRi - 0U, // ATOMIC_LOAD_NIHF64 - 0U, // ATOMIC_LOAD_NIHF64i - 0U, // ATOMIC_LOAD_NIHH64 - 0U, // ATOMIC_LOAD_NIHH64i - 0U, // ATOMIC_LOAD_NIHL64 - 0U, // ATOMIC_LOAD_NIHL64i - 0U, // ATOMIC_LOAD_NILF - 0U, // ATOMIC_LOAD_NILF64 - 0U, // ATOMIC_LOAD_NILF64i - 0U, // ATOMIC_LOAD_NILFi - 0U, // ATOMIC_LOAD_NILH - 0U, // ATOMIC_LOAD_NILH64 - 0U, // ATOMIC_LOAD_NILH64i - 0U, // ATOMIC_LOAD_NILHi - 0U, // ATOMIC_LOAD_NILL - 0U, // ATOMIC_LOAD_NILL64 - 0U, // ATOMIC_LOAD_NILL64i - 0U, // ATOMIC_LOAD_NILLi - 0U, // ATOMIC_LOAD_NR - 0U, // ATOMIC_LOAD_NRi - 0U, // ATOMIC_LOAD_OGR - 0U, // ATOMIC_LOAD_OIHF64 - 0U, // ATOMIC_LOAD_OIHH64 - 0U, // ATOMIC_LOAD_OIHL64 - 0U, // ATOMIC_LOAD_OILF - 0U, // ATOMIC_LOAD_OILF64 - 0U, // ATOMIC_LOAD_OILH - 0U, // ATOMIC_LOAD_OILH64 - 0U, // ATOMIC_LOAD_OILL - 0U, // ATOMIC_LOAD_OILL64 - 0U, // ATOMIC_LOAD_OR - 0U, // ATOMIC_LOAD_SGR - 0U, // ATOMIC_LOAD_SR - 0U, // ATOMIC_LOAD_UMAX_32 - 0U, // ATOMIC_LOAD_UMAX_64 - 0U, // ATOMIC_LOAD_UMIN_32 - 0U, // ATOMIC_LOAD_UMIN_64 - 0U, // ATOMIC_LOAD_XGR - 0U, // ATOMIC_LOAD_XIHF64 - 0U, // ATOMIC_LOAD_XILF - 0U, // ATOMIC_LOAD_XILF64 - 0U, // ATOMIC_LOAD_XR - 0U, // ATOMIC_SWAPW - 0U, // ATOMIC_SWAP_32 - 0U, // ATOMIC_SWAP_64 - 0U, // CFIMux - 0U, // CGIBCall - 0U, // CGIBReturn - 0U, // CGRBCall - 0U, // CGRBReturn - 0U, // CHIMux - 0U, // CIBCall - 0U, // CIBReturn - 0U, // CLCLoop - 0U, // CLCSequence - 0U, // CLFIMux - 0U, // CLGIBCall - 0U, // CLGIBReturn - 0U, // CLGRBCall - 0U, // CLGRBReturn - 0U, // CLIBCall - 0U, // CLIBReturn - 0U, // CLMux - 0U, // CLRBCall - 0U, // CLRBReturn - 0U, // CLSTLoop - 0U, // CMux - 0U, // CRBCall - 0U, // CRBReturn - 0U, // CallBASR - 0U, // CallBCR - 0U, // CallBR - 0U, // CallBRASL - 0U, // CallBRCL - 0U, // CallJG - 0U, // CondReturn - 0U, // CondStore16 - 0U, // CondStore16Inv - 0U, // CondStore16Mux - 0U, // CondStore16MuxInv - 0U, // CondStore32 - 0U, // CondStore32Inv - 0U, // CondStore32Mux - 0U, // CondStore32MuxInv - 0U, // CondStore64 - 0U, // CondStore64Inv - 0U, // CondStore8 - 0U, // CondStore8Inv - 0U, // CondStore8Mux - 0U, // CondStore8MuxInv - 0U, // CondStoreF32 - 0U, // CondStoreF32Inv - 0U, // CondStoreF64 - 0U, // CondStoreF64Inv - 0U, // CondTrap - 0U, // GOT - 0U, // IIFMux - 0U, // IIHF64 - 0U, // IIHH64 - 0U, // IIHL64 - 0U, // IIHMux - 0U, // IILF64 - 0U, // IILH64 - 0U, // IILL64 - 0U, // IILMux - 0U, // L128 - 0U, // LBMux - 0U, // LEFR - 0U, // LFER - 0U, // LHIMux - 0U, // LHMux - 0U, // LLCMux - 0U, // LLCRMux - 0U, // LLHMux - 0U, // LLHRMux - 0U, // LMux - 0U, // LOCHIMux - 0U, // LOCMux - 0U, // LOCRMux - 0U, // LRMux - 0U, // LTDBRCompare_VecPseudo - 0U, // LTEBRCompare_VecPseudo - 0U, // LTXBRCompare_VecPseudo - 0U, // LX - 0U, // MVCLoop - 0U, // MVCSequence - 0U, // MVSTLoop - 0U, // MemBarrier - 0U, // NCLoop - 0U, // NCSequence - 0U, // NIFMux - 0U, // NIHF64 - 0U, // NIHH64 - 0U, // NIHL64 - 0U, // NIHMux - 0U, // NILF64 - 0U, // NILH64 - 0U, // NILL64 - 0U, // NILMux - 0U, // OCLoop - 0U, // OCSequence - 0U, // OIFMux - 0U, // OIHF64 - 0U, // OIHH64 - 0U, // OIHL64 - 0U, // OIHMux - 0U, // OILF64 - 0U, // OILH64 - 0U, // OILL64 - 0U, // OILMux - 0U, // PAIR128 - 0U, // RISBHH - 0U, // RISBHL - 0U, // RISBLH - 0U, // RISBLL - 0U, // RISBMux - 0U, // Return - 0U, // SRSTLoop - 0U, // ST128 - 0U, // STCMux - 0U, // STHMux - 0U, // STMux - 0U, // STOCMux - 0U, // STX - 0U, // Select32 - 0U, // Select64 - 0U, // SelectF128 - 0U, // SelectF32 - 0U, // SelectF64 - 0U, // SelectVR128 - 0U, // SelectVR32 - 0U, // SelectVR64 - 0U, // Serialize - 0U, // TBEGIN_nofloat - 0U, // TLS_GDCALL - 0U, // TLS_LDCALL - 0U, // TMHH64 - 0U, // TMHL64 - 0U, // TMHMux - 0U, // TMLH64 - 0U, // TMLL64 - 0U, // TMLMux - 0U, // Trap - 0U, // VL32 - 0U, // VL64 - 0U, // VLR32 - 0U, // VLR64 - 0U, // VLVGP32 - 0U, // VST32 - 0U, // VST64 - 0U, // XCLoop - 0U, // XCSequence - 0U, // XIFMux - 0U, // XIHF64 - 0U, // XILF64 - 0U, // ZEXT128 - 0U, // A - 0U, // AD - 0U, // ADB - 0U, // ADBR - 0U, // ADR - 0U, // ADTR - 512U, // ADTRA - 0U, // AE - 0U, // AEB - 0U, // AEBR - 0U, // AER - 0U, // AFI - 0U, // AG - 0U, // AGF - 0U, // AGFI - 0U, // AGFR - 0U, // AGH - 0U, // AGHI - 8U, // AGHIK - 0U, // AGR - 0U, // AGRK - 0U, // AGSI - 0U, // AH - 0U, // AHHHR - 0U, // AHHLR - 0U, // AHI - 8U, // AHIK - 0U, // AHY - 0U, // AIH - 0U, // AL - 0U, // ALC - 0U, // ALCG - 0U, // ALCGR - 0U, // ALCR - 0U, // ALFI - 0U, // ALG - 0U, // ALGF - 0U, // ALGFI - 0U, // ALGFR - 8U, // ALGHSIK - 0U, // ALGR - 0U, // ALGRK - 0U, // ALGSI - 0U, // ALHHHR - 0U, // ALHHLR - 8U, // ALHSIK - 0U, // ALR - 0U, // ALRK - 0U, // ALSI - 0U, // ALSIH - 0U, // ALSIHN - 0U, // ALY - 0U, // AP - 0U, // AR - 0U, // ARK - 0U, // ASI - 0U, // AU - 0U, // AUR - 0U, // AW - 0U, // AWR - 0U, // AXBR - 0U, // AXR - 0U, // AXTR - 512U, // AXTRA - 0U, // AY - 0U, // B - 0U, // BAKR - 0U, // BAL - 0U, // BALR - 0U, // BAS - 0U, // BASR - 0U, // BASSM - 0U, // BAsmE - 0U, // BAsmH - 0U, // BAsmHE - 0U, // BAsmL - 0U, // BAsmLE - 0U, // BAsmLH - 0U, // BAsmM - 0U, // BAsmNE - 0U, // BAsmNH - 0U, // BAsmNHE - 0U, // BAsmNL - 0U, // BAsmNLE - 0U, // BAsmNLH - 0U, // BAsmNM - 0U, // BAsmNO - 0U, // BAsmNP - 0U, // BAsmNZ - 0U, // BAsmO - 0U, // BAsmP - 0U, // BAsmZ - 0U, // BC - 0U, // BCAsm - 0U, // BCR - 0U, // BCRAsm - 0U, // BCT - 0U, // BCTG - 0U, // BCTGR - 0U, // BCTR - 0U, // BI - 0U, // BIAsmE - 0U, // BIAsmH - 0U, // BIAsmHE - 0U, // BIAsmL - 0U, // BIAsmLE - 0U, // BIAsmLH - 0U, // BIAsmM - 0U, // BIAsmNE - 0U, // BIAsmNH - 0U, // BIAsmNHE - 0U, // BIAsmNL - 0U, // BIAsmNLE - 0U, // BIAsmNLH - 0U, // BIAsmNM - 0U, // BIAsmNO - 0U, // BIAsmNP - 0U, // BIAsmNZ - 0U, // BIAsmO - 0U, // BIAsmP - 0U, // BIAsmZ - 0U, // BIC - 0U, // BICAsm - 0U, // BPP - 0U, // BPRP - 0U, // BR - 0U, // BRAS - 0U, // BRASL - 0U, // BRAsmE - 0U, // BRAsmH - 0U, // BRAsmHE - 0U, // BRAsmL - 0U, // BRAsmLE - 0U, // BRAsmLH - 0U, // BRAsmM - 0U, // BRAsmNE - 0U, // BRAsmNH - 0U, // BRAsmNHE - 0U, // BRAsmNL - 0U, // BRAsmNLE - 0U, // BRAsmNLH - 0U, // BRAsmNM - 0U, // BRAsmNO - 0U, // BRAsmNP - 0U, // BRAsmNZ - 0U, // BRAsmO - 0U, // BRAsmP - 0U, // BRAsmZ - 0U, // BRC - 0U, // BRCAsm - 0U, // BRCL - 0U, // BRCLAsm - 0U, // BRCT - 0U, // BRCTG - 0U, // BRCTH - 16U, // BRXH - 16U, // BRXHG - 16U, // BRXLE - 16U, // BRXLG - 0U, // BSA - 0U, // BSG - 0U, // BSM - 24U, // BXH - 24U, // BXHG - 24U, // BXLE - 24U, // BXLEG - 0U, // C - 0U, // CD - 0U, // CDB - 0U, // CDBR - 0U, // CDFBR - 33U, // CDFBRA - 0U, // CDFR - 33U, // CDFTR - 0U, // CDGBR - 33U, // CDGBRA - 0U, // CDGR - 0U, // CDGTR - 33U, // CDGTRA - 33U, // CDLFBR - 33U, // CDLFTR - 33U, // CDLGBR - 33U, // CDLGTR - 0U, // CDPT - 0U, // CDR - 24U, // CDS - 24U, // CDSG - 0U, // CDSTR - 24U, // CDSY - 0U, // CDTR - 0U, // CDUTR - 0U, // CDZT - 0U, // CE - 0U, // CEB - 0U, // CEBR - 0U, // CEDTR - 0U, // CEFBR - 33U, // CEFBRA - 0U, // CEFR - 0U, // CEGBR - 33U, // CEGBRA - 0U, // CEGR - 33U, // CELFBR - 33U, // CELGBR - 0U, // CER - 0U, // CEXTR - 0U, // CFC - 41U, // CFDBR - 33U, // CFDBRA - 41U, // CFDR - 33U, // CFDTR - 41U, // CFEBR - 33U, // CFEBRA - 41U, // CFER - 0U, // CFI - 41U, // CFXBR - 33U, // CFXBRA - 41U, // CFXR - 33U, // CFXTR - 0U, // CG - 41U, // CGDBR - 33U, // CGDBRA - 41U, // CGDR - 41U, // CGDTR - 33U, // CGDTRA - 41U, // CGEBR - 33U, // CGEBRA - 41U, // CGER - 0U, // CGF - 0U, // CGFI - 0U, // CGFR - 0U, // CGFRL - 0U, // CGH - 0U, // CGHI - 0U, // CGHRL - 0U, // CGHSI - 0U, // CGIB - 25U, // CGIBAsm - 1U, // CGIBAsmE - 1U, // CGIBAsmH - 1U, // CGIBAsmHE - 1U, // CGIBAsmL - 1U, // CGIBAsmLE - 1U, // CGIBAsmLH - 1U, // CGIBAsmNE - 1U, // CGIBAsmNH - 1U, // CGIBAsmNHE - 1U, // CGIBAsmNL - 1U, // CGIBAsmNLE - 1U, // CGIBAsmNLH - 0U, // CGIJ - 17U, // CGIJAsm - 0U, // CGIJAsmE - 0U, // CGIJAsmH - 0U, // CGIJAsmHE - 0U, // CGIJAsmL - 0U, // CGIJAsmLE - 0U, // CGIJAsmLH - 0U, // CGIJAsmNE - 0U, // CGIJAsmNH - 0U, // CGIJAsmNHE - 0U, // CGIJAsmNL - 0U, // CGIJAsmNLE - 0U, // CGIJAsmNLH - 0U, // CGIT - 48U, // CGITAsm - 0U, // CGITAsmE - 0U, // CGITAsmH - 0U, // CGITAsmHE - 0U, // CGITAsmL - 0U, // CGITAsmLE - 0U, // CGITAsmLH - 0U, // CGITAsmNE - 0U, // CGITAsmNH - 0U, // CGITAsmNHE - 0U, // CGITAsmNL - 0U, // CGITAsmNLE - 0U, // CGITAsmNLH - 0U, // CGR - 41U, // CGRB - 8752U, // CGRBAsm - 56U, // CGRBAsmE - 56U, // CGRBAsmH - 56U, // CGRBAsmHE - 56U, // CGRBAsmL - 56U, // CGRBAsmLE - 56U, // CGRBAsmLH - 56U, // CGRBAsmNE - 56U, // CGRBAsmNH - 56U, // CGRBAsmNHE - 56U, // CGRBAsmNL - 56U, // CGRBAsmNLE - 56U, // CGRBAsmNLH - 2U, // CGRJ - 16944U, // CGRJAsm - 64U, // CGRJAsmE - 64U, // CGRJAsmH - 64U, // CGRJAsmHE - 64U, // CGRJAsmL - 64U, // CGRJAsmLE - 64U, // CGRJAsmLH - 64U, // CGRJAsmNE - 64U, // CGRJAsmNH - 64U, // CGRJAsmNHE - 64U, // CGRJAsmNL - 64U, // CGRJAsmNLE - 64U, // CGRJAsmNLH - 0U, // CGRL - 0U, // CGRT - 48U, // CGRTAsm - 0U, // CGRTAsmE - 0U, // CGRTAsmH - 0U, // CGRTAsmHE - 0U, // CGRTAsmL - 0U, // CGRTAsmLE - 0U, // CGRTAsmLH - 0U, // CGRTAsmNE - 0U, // CGRTAsmNH - 0U, // CGRTAsmNHE - 0U, // CGRTAsmNL - 0U, // CGRTAsmNLE - 0U, // CGRTAsmNLH - 41U, // CGXBR - 33U, // CGXBRA - 41U, // CGXR - 41U, // CGXTR - 33U, // CGXTRA - 0U, // CH - 0U, // CHF - 0U, // CHHR - 0U, // CHHSI - 0U, // CHI - 0U, // CHLR - 0U, // CHRL - 0U, // CHSI - 0U, // CHY - 0U, // CIB - 25U, // CIBAsm - 1U, // CIBAsmE - 1U, // CIBAsmH - 1U, // CIBAsmHE - 1U, // CIBAsmL - 1U, // CIBAsmLE - 1U, // CIBAsmLH - 1U, // CIBAsmNE - 1U, // CIBAsmNH - 1U, // CIBAsmNHE - 1U, // CIBAsmNL - 1U, // CIBAsmNLE - 1U, // CIBAsmNLH - 0U, // CIH - 0U, // CIJ - 17U, // CIJAsm - 0U, // CIJAsmE - 0U, // CIJAsmH - 0U, // CIJAsmHE - 0U, // CIJAsmL - 0U, // CIJAsmLE - 0U, // CIJAsmLH - 0U, // CIJAsmNE - 0U, // CIJAsmNH - 0U, // CIJAsmNHE - 0U, // CIJAsmNL - 0U, // CIJAsmNLE - 0U, // CIJAsmNLH - 0U, // CIT - 48U, // CITAsm - 0U, // CITAsmE - 0U, // CITAsmH - 0U, // CITAsmHE - 0U, // CITAsmL - 0U, // CITAsmLE - 0U, // CITAsmLH - 0U, // CITAsmNE - 0U, // CITAsmNH - 0U, // CITAsmNHE - 0U, // CITAsmNL - 0U, // CITAsmNLE - 0U, // CITAsmNLH - 0U, // CKSM - 0U, // CL - 0U, // CLC - 0U, // CLCL - 72U, // CLCLE - 72U, // CLCLU - 33U, // CLFDBR - 33U, // CLFDTR - 33U, // CLFEBR - 0U, // CLFHSI - 0U, // CLFI - 0U, // CLFIT - 48U, // CLFITAsm - 0U, // CLFITAsmE - 0U, // CLFITAsmH - 0U, // CLFITAsmHE - 0U, // CLFITAsmL - 0U, // CLFITAsmLE - 0U, // CLFITAsmLH - 0U, // CLFITAsmNE - 0U, // CLFITAsmNH - 0U, // CLFITAsmNHE - 0U, // CLFITAsmNL - 0U, // CLFITAsmNLE - 0U, // CLFITAsmNLH - 33U, // CLFXBR - 33U, // CLFXTR - 0U, // CLG - 33U, // CLGDBR - 33U, // CLGDTR - 33U, // CLGEBR - 0U, // CLGF - 0U, // CLGFI - 0U, // CLGFR - 0U, // CLGFRL - 0U, // CLGHRL - 0U, // CLGHSI - 0U, // CLGIB - 25U, // CLGIBAsm - 1U, // CLGIBAsmE - 1U, // CLGIBAsmH - 1U, // CLGIBAsmHE - 1U, // CLGIBAsmL - 1U, // CLGIBAsmLE - 1U, // CLGIBAsmLH - 1U, // CLGIBAsmNE - 1U, // CLGIBAsmNH - 1U, // CLGIBAsmNHE - 1U, // CLGIBAsmNL - 1U, // CLGIBAsmNLE - 1U, // CLGIBAsmNLH - 0U, // CLGIJ - 17U, // CLGIJAsm - 0U, // CLGIJAsmE - 0U, // CLGIJAsmH - 0U, // CLGIJAsmHE - 0U, // CLGIJAsmL - 0U, // CLGIJAsmLE - 0U, // CLGIJAsmLH - 0U, // CLGIJAsmNE - 0U, // CLGIJAsmNH - 0U, // CLGIJAsmNHE - 0U, // CLGIJAsmNL - 0U, // CLGIJAsmNLE - 0U, // CLGIJAsmNLH - 0U, // CLGIT - 48U, // CLGITAsm - 0U, // CLGITAsmE - 0U, // CLGITAsmH - 0U, // CLGITAsmHE - 0U, // CLGITAsmL - 0U, // CLGITAsmLE - 0U, // CLGITAsmLH - 0U, // CLGITAsmNE - 0U, // CLGITAsmNH - 0U, // CLGITAsmNHE - 0U, // CLGITAsmNL - 0U, // CLGITAsmNLE - 0U, // CLGITAsmNLH - 0U, // CLGR - 41U, // CLGRB - 8752U, // CLGRBAsm - 56U, // CLGRBAsmE - 56U, // CLGRBAsmH - 56U, // CLGRBAsmHE - 56U, // CLGRBAsmL - 56U, // CLGRBAsmLE - 56U, // CLGRBAsmLH - 56U, // CLGRBAsmNE - 56U, // CLGRBAsmNH - 56U, // CLGRBAsmNHE - 56U, // CLGRBAsmNL - 56U, // CLGRBAsmNLE - 56U, // CLGRBAsmNLH - 2U, // CLGRJ - 16944U, // CLGRJAsm - 64U, // CLGRJAsmE - 64U, // CLGRJAsmH - 64U, // CLGRJAsmHE - 64U, // CLGRJAsmL - 64U, // CLGRJAsmLE - 64U, // CLGRJAsmLH - 64U, // CLGRJAsmNE - 64U, // CLGRJAsmNH - 64U, // CLGRJAsmNHE - 64U, // CLGRJAsmNL - 64U, // CLGRJAsmNLE - 64U, // CLGRJAsmNLH - 0U, // CLGRL - 0U, // CLGRT - 48U, // CLGRTAsm - 0U, // CLGRTAsmE - 0U, // CLGRTAsmH - 0U, // CLGRTAsmHE - 0U, // CLGRTAsmL - 0U, // CLGRTAsmLE - 0U, // CLGRTAsmLH - 0U, // CLGRTAsmNE - 0U, // CLGRTAsmNH - 0U, // CLGRTAsmNHE - 0U, // CLGRTAsmNL - 0U, // CLGRTAsmNLE - 0U, // CLGRTAsmNLH - 0U, // CLGT - 80U, // CLGTAsm - 0U, // CLGTAsmE - 0U, // CLGTAsmH - 0U, // CLGTAsmHE - 0U, // CLGTAsmL - 0U, // CLGTAsmLE - 0U, // CLGTAsmLH - 0U, // CLGTAsmNE - 0U, // CLGTAsmNH - 0U, // CLGTAsmNHE - 0U, // CLGTAsmNL - 0U, // CLGTAsmNLE - 0U, // CLGTAsmNLH - 33U, // CLGXBR - 33U, // CLGXTR - 0U, // CLHF - 0U, // CLHHR - 0U, // CLHHSI - 0U, // CLHLR - 0U, // CLHRL - 0U, // CLI - 0U, // CLIB - 25U, // CLIBAsm - 1U, // CLIBAsmE - 1U, // CLIBAsmH - 1U, // CLIBAsmHE - 1U, // CLIBAsmL - 1U, // CLIBAsmLE - 1U, // CLIBAsmLH - 1U, // CLIBAsmNE - 1U, // CLIBAsmNH - 1U, // CLIBAsmNHE - 1U, // CLIBAsmNL - 1U, // CLIBAsmNLE - 1U, // CLIBAsmNLH - 0U, // CLIH - 0U, // CLIJ - 17U, // CLIJAsm - 0U, // CLIJAsmE - 0U, // CLIJAsmH - 0U, // CLIJAsmHE - 0U, // CLIJAsmL - 0U, // CLIJAsmLE - 0U, // CLIJAsmLH - 0U, // CLIJAsmNE - 0U, // CLIJAsmNH - 0U, // CLIJAsmNHE - 0U, // CLIJAsmNL - 0U, // CLIJAsmNLE - 0U, // CLIJAsmNLH - 0U, // CLIY - 1U, // CLM - 1U, // CLMH - 1U, // CLMY - 0U, // CLR - 41U, // CLRB - 8752U, // CLRBAsm - 56U, // CLRBAsmE - 56U, // CLRBAsmH - 56U, // CLRBAsmHE - 56U, // CLRBAsmL - 56U, // CLRBAsmLE - 56U, // CLRBAsmLH - 56U, // CLRBAsmNE - 56U, // CLRBAsmNH - 56U, // CLRBAsmNHE - 56U, // CLRBAsmNL - 56U, // CLRBAsmNLE - 56U, // CLRBAsmNLH - 2U, // CLRJ - 16944U, // CLRJAsm - 64U, // CLRJAsmE - 64U, // CLRJAsmH - 64U, // CLRJAsmHE - 64U, // CLRJAsmL - 64U, // CLRJAsmLE - 64U, // CLRJAsmLH - 64U, // CLRJAsmNE - 64U, // CLRJAsmNH - 64U, // CLRJAsmNHE - 64U, // CLRJAsmNL - 64U, // CLRJAsmNLE - 64U, // CLRJAsmNLH - 0U, // CLRL - 0U, // CLRT - 48U, // CLRTAsm - 0U, // CLRTAsmE - 0U, // CLRTAsmH - 0U, // CLRTAsmHE - 0U, // CLRTAsmL - 0U, // CLRTAsmLE - 0U, // CLRTAsmLH - 0U, // CLRTAsmNE - 0U, // CLRTAsmNH - 0U, // CLRTAsmNHE - 0U, // CLRTAsmNL - 0U, // CLRTAsmNLE - 0U, // CLRTAsmNLH - 0U, // CLST - 0U, // CLT - 80U, // CLTAsm - 0U, // CLTAsmE - 0U, // CLTAsmH - 0U, // CLTAsmHE - 0U, // CLTAsmL - 0U, // CLTAsmLE - 0U, // CLTAsmLH - 0U, // CLTAsmNE - 0U, // CLTAsmNH - 0U, // CLTAsmNHE - 0U, // CLTAsmNL - 0U, // CLTAsmNLE - 0U, // CLTAsmNLH - 0U, // CLY - 0U, // CMPSC - 0U, // CP - 0U, // CPDT - 88U, // CPSDRdd - 88U, // CPSDRds - 88U, // CPSDRsd - 88U, // CPSDRss - 0U, // CPXT - 0U, // CPYA - 0U, // CR - 41U, // CRB - 8752U, // CRBAsm - 56U, // CRBAsmE - 56U, // CRBAsmH - 56U, // CRBAsmHE - 56U, // CRBAsmL - 56U, // CRBAsmLE - 56U, // CRBAsmLH - 56U, // CRBAsmNE - 56U, // CRBAsmNH - 56U, // CRBAsmNHE - 56U, // CRBAsmNL - 56U, // CRBAsmNLE - 56U, // CRBAsmNLH - 600U, // CRDTE - 88U, // CRDTEOpt - 2U, // CRJ - 16944U, // CRJAsm - 64U, // CRJAsmE - 64U, // CRJAsmH - 64U, // CRJAsmHE - 64U, // CRJAsmL - 64U, // CRJAsmLE - 64U, // CRJAsmLH - 64U, // CRJAsmNE - 64U, // CRJAsmNH - 64U, // CRJAsmNHE - 64U, // CRJAsmNL - 64U, // CRJAsmNLE - 64U, // CRJAsmNLH - 0U, // CRL - 0U, // CRT - 48U, // CRTAsm - 0U, // CRTAsmE - 0U, // CRTAsmH - 0U, // CRTAsmHE - 0U, // CRTAsmL - 0U, // CRTAsmLE - 0U, // CRTAsmLH - 0U, // CRTAsmNE - 0U, // CRTAsmNH - 0U, // CRTAsmNHE - 0U, // CRTAsmNL - 0U, // CRTAsmNLE - 0U, // CRTAsmNLH - 24U, // CS - 0U, // CSCH - 48U, // CSDTR - 24U, // CSG - 0U, // CSP - 0U, // CSPG - 96U, // CSST - 48U, // CSXTR - 24U, // CSY - 104U, // CU12 - 0U, // CU12Opt - 104U, // CU14 - 0U, // CU14Opt - 104U, // CU21 - 0U, // CU21Opt - 104U, // CU24 - 0U, // CU24Opt - 0U, // CU41 - 0U, // CU42 - 0U, // CUDTR - 0U, // CUSE - 104U, // CUTFU - 0U, // CUTFUOpt - 104U, // CUUTF - 0U, // CUUTFOpt - 0U, // CUXTR - 0U, // CVB - 0U, // CVBG - 0U, // CVBY - 0U, // CVD - 0U, // CVDG - 0U, // CVDY - 0U, // CXBR - 0U, // CXFBR - 33U, // CXFBRA - 0U, // CXFR - 33U, // CXFTR - 0U, // CXGBR - 33U, // CXGBRA - 0U, // CXGR - 0U, // CXGTR - 33U, // CXGTRA - 33U, // CXLFBR - 33U, // CXLFTR - 33U, // CXLGBR - 33U, // CXLGTR - 0U, // CXPT - 0U, // CXR - 0U, // CXSTR - 0U, // CXTR - 0U, // CXUTR - 0U, // CXZT - 0U, // CY - 0U, // CZDT - 0U, // CZXT - 0U, // D - 0U, // DD - 0U, // DDB - 0U, // DDBR - 0U, // DDR - 0U, // DDTR - 512U, // DDTRA - 0U, // DE - 0U, // DEB - 0U, // DEBR - 0U, // DER - 56U, // DIAG - 25200U, // DIDBR - 25200U, // DIEBR - 0U, // DL - 0U, // DLG - 0U, // DLGR - 0U, // DLR - 0U, // DP - 0U, // DR - 0U, // DSG - 0U, // DSGF - 0U, // DSGFR - 0U, // DSGR - 0U, // DXBR - 0U, // DXR - 0U, // DXTR - 512U, // DXTRA - 0U, // EAR - 56U, // ECAG - 0U, // ECCTR - 0U, // ECPGA - 96U, // ECTG - 0U, // ED - 0U, // EDMK - 0U, // EEDTR - 0U, // EEXTR - 0U, // EFPC - 0U, // EPAIR - 0U, // EPAR - 0U, // EPCTR - 0U, // EPSW - 0U, // EREG - 0U, // EREGG - 0U, // ESAIR - 0U, // ESAR - 0U, // ESDTR - 0U, // ESEA - 0U, // ESTA - 0U, // ESXTR - 0U, // ETND - 0U, // EX - 0U, // EXRL - 41U, // FIDBR - 33U, // FIDBRA - 0U, // FIDR - 33U, // FIDTR - 41U, // FIEBR - 33U, // FIEBRA - 0U, // FIER - 41U, // FIXBR - 33U, // FIXBRA - 0U, // FIXR - 33U, // FIXTR - 0U, // FLOGR - 0U, // HDR - 0U, // HER - 0U, // HSCH - 0U, // IAC - 0U, // IC - 0U, // IC32 - 0U, // IC32Y - 0U, // ICM - 0U, // ICMH - 0U, // ICMY - 0U, // ICY - 600U, // IDTE - 88U, // IDTEOpt - 88U, // IEDTR - 88U, // IEXTR - 0U, // IIHF - 0U, // IIHH - 0U, // IIHL - 0U, // IILF - 0U, // IILH - 0U, // IILL - 0U, // IPK - 0U, // IPM - 512U, // IPTE - 0U, // IPTEOpt - 0U, // IPTEOptOpt - 0U, // IRBM - 0U, // ISKE - 0U, // IVSK - 0U, // InsnE - 2U, // InsnRI - 1145U, // InsnRIE - 0U, // InsnRIL - 2U, // InsnRILU - 2U, // InsnRIS - 0U, // InsnRR - 41U, // InsnRRE - 1657U, // InsnRRF - 34937U, // InsnRRS - 2681U, // InsnRS - 2681U, // InsnRSE - 1145U, // InsnRSI - 2681U, // InsnRSY - 0U, // InsnRX - 0U, // InsnRXE - 3193U, // InsnRXF - 0U, // InsnRXY - 0U, // InsnS - 3U, // InsnSI - 3U, // InsnSIL - 3U, // InsnSIY - 0U, // InsnSS - 41U, // InsnSSE - 3705U, // InsnSSF - 0U, // J - 0U, // JAsmE - 0U, // JAsmH - 0U, // JAsmHE - 0U, // JAsmL - 0U, // JAsmLE - 0U, // JAsmLH - 0U, // JAsmM - 0U, // JAsmNE - 0U, // JAsmNH - 0U, // JAsmNHE - 0U, // JAsmNL - 0U, // JAsmNLE - 0U, // JAsmNLH - 0U, // JAsmNM - 0U, // JAsmNO - 0U, // JAsmNP - 0U, // JAsmNZ - 0U, // JAsmO - 0U, // JAsmP - 0U, // JAsmZ - 0U, // JG - 0U, // JGAsmE - 0U, // JGAsmH - 0U, // JGAsmHE - 0U, // JGAsmL - 0U, // JGAsmLE - 0U, // JGAsmLH - 0U, // JGAsmM - 0U, // JGAsmNE - 0U, // JGAsmNH - 0U, // JGAsmNHE - 0U, // JGAsmNL - 0U, // JGAsmNLE - 0U, // JGAsmNLH - 0U, // JGAsmNM - 0U, // JGAsmNO - 0U, // JGAsmNP - 0U, // JGAsmNZ - 0U, // JGAsmO - 0U, // JGAsmP - 0U, // JGAsmZ - 0U, // KDB - 0U, // KDBR - 0U, // KDTR - 0U, // KEB - 0U, // KEBR - 0U, // KIMD - 0U, // KLMD - 0U, // KM - 88U, // KMA - 0U, // KMAC - 0U, // KMC - 88U, // KMCTR - 0U, // KMF - 0U, // KMO - 0U, // KXBR - 0U, // KXTR - 0U, // L - 0U, // LA - 56U, // LAA - 56U, // LAAG - 56U, // LAAL - 56U, // LAALG - 0U, // LAE - 0U, // LAEY - 56U, // LAM - 56U, // LAMY - 56U, // LAN - 56U, // LANG - 56U, // LAO - 56U, // LAOG - 0U, // LARL - 0U, // LASP - 0U, // LAT - 56U, // LAX - 56U, // LAXG - 0U, // LAY - 0U, // LB - 0U, // LBH - 0U, // LBR - 104U, // LCBB - 0U, // LCCTL - 0U, // LCDBR - 0U, // LCDFR - 0U, // LCDFR_32 - 0U, // LCDR - 0U, // LCEBR - 0U, // LCER - 0U, // LCGFR - 0U, // LCGR - 0U, // LCR - 56U, // LCTL - 56U, // LCTLG - 0U, // LCXBR - 0U, // LCXR - 0U, // LD - 0U, // LDE - 0U, // LDE32 - 0U, // LDEB - 0U, // LDEBR - 0U, // LDER - 48U, // LDETR - 0U, // LDGR - 0U, // LDR - 0U, // LDR32 - 0U, // LDXBR - 33U, // LDXBRA - 0U, // LDXR - 33U, // LDXTR - 0U, // LDY - 0U, // LE - 0U, // LEDBR - 33U, // LEDBRA - 0U, // LEDR - 33U, // LEDTR - 0U, // LER - 0U, // LEXBR - 33U, // LEXBRA - 0U, // LEXR - 0U, // LEY - 0U, // LFAS - 0U, // LFH - 0U, // LFHAT - 0U, // LFPC - 0U, // LG - 0U, // LGAT - 0U, // LGB - 0U, // LGBR - 0U, // LGDR - 0U, // LGF - 0U, // LGFI - 0U, // LGFR - 0U, // LGFRL - 0U, // LGG - 0U, // LGH - 0U, // LGHI - 0U, // LGHR - 0U, // LGHRL - 0U, // LGR - 0U, // LGRL - 0U, // LGSC - 0U, // LH - 0U, // LHH - 0U, // LHI - 0U, // LHR - 0U, // LHRL - 0U, // LHY - 0U, // LLC - 0U, // LLCH - 0U, // LLCR - 0U, // LLGC - 0U, // LLGCR - 0U, // LLGF - 0U, // LLGFAT - 0U, // LLGFR - 0U, // LLGFRL - 0U, // LLGFSG - 0U, // LLGH - 0U, // LLGHR - 0U, // LLGHRL - 0U, // LLGT - 0U, // LLGTAT - 0U, // LLGTR - 0U, // LLH - 0U, // LLHH - 0U, // LLHR - 0U, // LLHRL - 0U, // LLIHF - 0U, // LLIHH - 0U, // LLIHL - 0U, // LLILF - 0U, // LLILH - 0U, // LLILL - 0U, // LLZRGF - 56U, // LM - 41528U, // LMD - 56U, // LMG - 56U, // LMH - 56U, // LMY - 0U, // LNDBR - 0U, // LNDFR - 0U, // LNDFR_32 - 0U, // LNDR - 0U, // LNEBR - 0U, // LNER - 0U, // LNGFR - 0U, // LNGR - 0U, // LNR - 0U, // LNXBR - 0U, // LNXR - 0U, // LOC - 104U, // LOCAsm - 0U, // LOCAsmE - 0U, // LOCAsmH - 0U, // LOCAsmHE - 0U, // LOCAsmL - 0U, // LOCAsmLE - 0U, // LOCAsmLH - 0U, // LOCAsmM - 0U, // LOCAsmNE - 0U, // LOCAsmNH - 0U, // LOCAsmNHE - 0U, // LOCAsmNL - 0U, // LOCAsmNLE - 0U, // LOCAsmNLH - 0U, // LOCAsmNM - 0U, // LOCAsmNO - 0U, // LOCAsmNP - 0U, // LOCAsmNZ - 0U, // LOCAsmO - 0U, // LOCAsmP - 0U, // LOCAsmZ - 0U, // LOCFH - 104U, // LOCFHAsm - 0U, // LOCFHAsmE - 0U, // LOCFHAsmH - 0U, // LOCFHAsmHE - 0U, // LOCFHAsmL - 0U, // LOCFHAsmLE - 0U, // LOCFHAsmLH - 0U, // LOCFHAsmM - 0U, // LOCFHAsmNE - 0U, // LOCFHAsmNH - 0U, // LOCFHAsmNHE - 0U, // LOCFHAsmNL - 0U, // LOCFHAsmNLE - 0U, // LOCFHAsmNLH - 0U, // LOCFHAsmNM - 0U, // LOCFHAsmNO - 0U, // LOCFHAsmNP - 0U, // LOCFHAsmNZ - 0U, // LOCFHAsmO - 0U, // LOCFHAsmP - 0U, // LOCFHAsmZ - 0U, // LOCFHR - 128U, // LOCFHRAsm - 0U, // LOCFHRAsmE - 0U, // LOCFHRAsmH - 0U, // LOCFHRAsmHE - 0U, // LOCFHRAsmL - 0U, // LOCFHRAsmLE - 0U, // LOCFHRAsmLH - 0U, // LOCFHRAsmM - 0U, // LOCFHRAsmNE - 0U, // LOCFHRAsmNH - 0U, // LOCFHRAsmNHE - 0U, // LOCFHRAsmNL - 0U, // LOCFHRAsmNLE - 0U, // LOCFHRAsmNLH - 0U, // LOCFHRAsmNM - 0U, // LOCFHRAsmNO - 0U, // LOCFHRAsmNP - 0U, // LOCFHRAsmNZ - 0U, // LOCFHRAsmO - 0U, // LOCFHRAsmP - 0U, // LOCFHRAsmZ - 0U, // LOCG - 104U, // LOCGAsm - 0U, // LOCGAsmE - 0U, // LOCGAsmH - 0U, // LOCGAsmHE - 0U, // LOCGAsmL - 0U, // LOCGAsmLE - 0U, // LOCGAsmLH - 0U, // LOCGAsmM - 0U, // LOCGAsmNE - 0U, // LOCGAsmNH - 0U, // LOCGAsmNHE - 0U, // LOCGAsmNL - 0U, // LOCGAsmNLE - 0U, // LOCGAsmNLH - 0U, // LOCGAsmNM - 0U, // LOCGAsmNO - 0U, // LOCGAsmNP - 0U, // LOCGAsmNZ - 0U, // LOCGAsmO - 0U, // LOCGAsmP - 0U, // LOCGAsmZ - 0U, // LOCGHI - 128U, // LOCGHIAsm - 0U, // LOCGHIAsmE - 0U, // LOCGHIAsmH - 0U, // LOCGHIAsmHE - 0U, // LOCGHIAsmL - 0U, // LOCGHIAsmLE - 0U, // LOCGHIAsmLH - 0U, // LOCGHIAsmM - 0U, // LOCGHIAsmNE - 0U, // LOCGHIAsmNH - 0U, // LOCGHIAsmNHE - 0U, // LOCGHIAsmNL - 0U, // LOCGHIAsmNLE - 0U, // LOCGHIAsmNLH - 0U, // LOCGHIAsmNM - 0U, // LOCGHIAsmNO - 0U, // LOCGHIAsmNP - 0U, // LOCGHIAsmNZ - 0U, // LOCGHIAsmO - 0U, // LOCGHIAsmP - 0U, // LOCGHIAsmZ - 0U, // LOCGR - 128U, // LOCGRAsm - 0U, // LOCGRAsmE - 0U, // LOCGRAsmH - 0U, // LOCGRAsmHE - 0U, // LOCGRAsmL - 0U, // LOCGRAsmLE - 0U, // LOCGRAsmLH - 0U, // LOCGRAsmM - 0U, // LOCGRAsmNE - 0U, // LOCGRAsmNH - 0U, // LOCGRAsmNHE - 0U, // LOCGRAsmNL - 0U, // LOCGRAsmNLE - 0U, // LOCGRAsmNLH - 0U, // LOCGRAsmNM - 0U, // LOCGRAsmNO - 0U, // LOCGRAsmNP - 0U, // LOCGRAsmNZ - 0U, // LOCGRAsmO - 0U, // LOCGRAsmP - 0U, // LOCGRAsmZ - 0U, // LOCHHI - 128U, // LOCHHIAsm - 0U, // LOCHHIAsmE - 0U, // LOCHHIAsmH - 0U, // LOCHHIAsmHE - 0U, // LOCHHIAsmL - 0U, // LOCHHIAsmLE - 0U, // LOCHHIAsmLH - 0U, // LOCHHIAsmM - 0U, // LOCHHIAsmNE - 0U, // LOCHHIAsmNH - 0U, // LOCHHIAsmNHE - 0U, // LOCHHIAsmNL - 0U, // LOCHHIAsmNLE - 0U, // LOCHHIAsmNLH - 0U, // LOCHHIAsmNM - 0U, // LOCHHIAsmNO - 0U, // LOCHHIAsmNP - 0U, // LOCHHIAsmNZ - 0U, // LOCHHIAsmO - 0U, // LOCHHIAsmP - 0U, // LOCHHIAsmZ - 0U, // LOCHI - 128U, // LOCHIAsm - 0U, // LOCHIAsmE - 0U, // LOCHIAsmH - 0U, // LOCHIAsmHE - 0U, // LOCHIAsmL - 0U, // LOCHIAsmLE - 0U, // LOCHIAsmLH - 0U, // LOCHIAsmM - 0U, // LOCHIAsmNE - 0U, // LOCHIAsmNH - 0U, // LOCHIAsmNHE - 0U, // LOCHIAsmNL - 0U, // LOCHIAsmNLE - 0U, // LOCHIAsmNLH - 0U, // LOCHIAsmNM - 0U, // LOCHIAsmNO - 0U, // LOCHIAsmNP - 0U, // LOCHIAsmNZ - 0U, // LOCHIAsmO - 0U, // LOCHIAsmP - 0U, // LOCHIAsmZ - 0U, // LOCR - 128U, // LOCRAsm - 0U, // LOCRAsmE - 0U, // LOCRAsmH - 0U, // LOCRAsmHE - 0U, // LOCRAsmL - 0U, // LOCRAsmLE - 0U, // LOCRAsmLH - 0U, // LOCRAsmM - 0U, // LOCRAsmNE - 0U, // LOCRAsmNH - 0U, // LOCRAsmNHE - 0U, // LOCRAsmNL - 0U, // LOCRAsmNLE - 0U, // LOCRAsmNLH - 0U, // LOCRAsmNM - 0U, // LOCRAsmNO - 0U, // LOCRAsmNP - 0U, // LOCRAsmNZ - 0U, // LOCRAsmO - 0U, // LOCRAsmP - 0U, // LOCRAsmZ - 0U, // LPCTL - 24U, // LPD - 0U, // LPDBR - 0U, // LPDFR - 0U, // LPDFR_32 - 24U, // LPDG - 0U, // LPDR - 0U, // LPEBR - 0U, // LPER - 0U, // LPGFR - 0U, // LPGR - 0U, // LPP - 0U, // LPQ - 0U, // LPR - 0U, // LPSW - 0U, // LPSWE - 25200U, // LPTEA - 0U, // LPXBR - 0U, // LPXR - 0U, // LR - 0U, // LRA - 0U, // LRAG - 0U, // LRAY - 0U, // LRDR - 0U, // LRER - 0U, // LRL - 0U, // LRV - 0U, // LRVG - 0U, // LRVGR - 0U, // LRVH - 0U, // LRVR - 0U, // LSCTL - 0U, // LT - 0U, // LTDBR - 0U, // LTDBRCompare - 0U, // LTDR - 0U, // LTDTR - 0U, // LTEBR - 0U, // LTEBRCompare - 0U, // LTER - 0U, // LTG - 0U, // LTGF - 0U, // LTGFR - 0U, // LTGR - 0U, // LTR - 0U, // LTXBR - 0U, // LTXBRCompare - 0U, // LTXR - 0U, // LTXTR - 0U, // LURA - 0U, // LURAG - 0U, // LXD - 0U, // LXDB - 0U, // LXDBR - 0U, // LXDR - 48U, // LXDTR - 0U, // LXE - 0U, // LXEB - 0U, // LXEBR - 0U, // LXER - 0U, // LXR - 0U, // LY - 0U, // LZDR - 0U, // LZER - 0U, // LZRF - 0U, // LZRG - 0U, // LZXR - 0U, // M - 136U, // MAD - 136U, // MADB - 112U, // MADBR - 112U, // MADR - 136U, // MAE - 136U, // MAEB - 112U, // MAEBR - 112U, // MAER - 136U, // MAY - 136U, // MAYH - 112U, // MAYHR - 136U, // MAYL - 112U, // MAYLR - 112U, // MAYR - 0U, // MC - 0U, // MD - 0U, // MDB - 0U, // MDBR - 0U, // MDE - 0U, // MDEB - 0U, // MDEBR - 0U, // MDER - 0U, // MDR - 0U, // MDTR - 512U, // MDTRA - 0U, // ME - 0U, // MEE - 0U, // MEEB - 0U, // MEEBR - 0U, // MEER - 0U, // MER - 0U, // MFY - 0U, // MG - 0U, // MGH - 0U, // MGHI - 0U, // MGRK - 0U, // MH - 0U, // MHI - 0U, // MHY - 0U, // ML - 0U, // MLG - 0U, // MLGR - 0U, // MLR - 0U, // MP - 0U, // MR - 0U, // MS - 0U, // MSC - 0U, // MSCH - 136U, // MSD - 136U, // MSDB - 112U, // MSDBR - 112U, // MSDR - 136U, // MSE - 136U, // MSEB - 112U, // MSEBR - 112U, // MSER - 0U, // MSFI - 0U, // MSG - 0U, // MSGC - 0U, // MSGF - 0U, // MSGFI - 0U, // MSGFR - 0U, // MSGR - 0U, // MSGRKC - 0U, // MSR - 0U, // MSRKC - 0U, // MSTA - 0U, // MSY - 0U, // MVC - 0U, // MVCDK - 0U, // MVCIN - 0U, // MVCK - 0U, // MVCL - 72U, // MVCLE - 72U, // MVCLU - 96U, // MVCOS - 0U, // MVCP - 0U, // MVCS - 0U, // MVCSK - 0U, // MVGHI - 0U, // MVHHI - 0U, // MVHI - 0U, // MVI - 0U, // MVIY - 0U, // MVN - 0U, // MVO - 0U, // MVPG - 0U, // MVST - 0U, // MVZ - 0U, // MXBR - 0U, // MXD - 0U, // MXDB - 0U, // MXDBR - 0U, // MXDR - 0U, // MXR - 0U, // MXTR - 512U, // MXTRA - 144U, // MY - 144U, // MYH - 0U, // MYHR - 144U, // MYL - 0U, // MYLR - 0U, // MYR - 0U, // N - 0U, // NC - 0U, // NG - 0U, // NGR - 0U, // NGRK - 0U, // NI - 0U, // NIAI - 0U, // NIHF - 0U, // NIHH - 0U, // NIHL - 0U, // NILF - 0U, // NILH - 0U, // NILL - 0U, // NIY - 0U, // NR - 0U, // NRK - 0U, // NTSTG - 0U, // NY - 0U, // O - 0U, // OC - 0U, // OG - 0U, // OGR - 0U, // OGRK - 0U, // OI - 0U, // OIHF - 0U, // OIHH - 0U, // OIHL - 0U, // OILF - 0U, // OILH - 0U, // OILL - 0U, // OIY - 0U, // OR - 0U, // ORK - 0U, // OY - 0U, // PACK - 0U, // PALB - 0U, // PC - 0U, // PCC - 0U, // PCKMO - 0U, // PFD - 0U, // PFDRL - 0U, // PFMF - 0U, // PFPO - 0U, // PGIN - 0U, // PGOUT - 0U, // PKA - 0U, // PKU - 41584U, // PLO - 0U, // POPCNT - 48U, // PPA - 0U, // PPNO - 0U, // PR - 0U, // PRNO - 0U, // PT - 0U, // PTF - 0U, // PTFF - 0U, // PTI - 0U, // PTLB - 25200U, // QADTR - 25200U, // QAXTR - 0U, // QCTRI - 0U, // QSI - 0U, // RCHP - 49816U, // RISBG - 49816U, // RISBG32 - 49816U, // RISBGN - 49816U, // RISBHG - 49816U, // RISBLG - 56U, // RLL - 56U, // RLLG - 49816U, // RNSBG - 49816U, // ROSBG - 0U, // RP - 0U, // RRBE - 0U, // RRBM - 25200U, // RRDTR - 25200U, // RRXTR - 0U, // RSCH - 49816U, // RXSBG - 0U, // S - 0U, // SAC - 0U, // SACF - 0U, // SAL - 0U, // SAM24 - 0U, // SAM31 - 0U, // SAM64 - 0U, // SAR - 0U, // SCCTR - 0U, // SCHM - 0U, // SCK - 0U, // SCKC - 0U, // SCKPF - 0U, // SD - 0U, // SDB - 0U, // SDBR - 0U, // SDR - 0U, // SDTR - 512U, // SDTRA - 0U, // SE - 0U, // SEB - 0U, // SEBR - 0U, // SER - 0U, // SFASR - 0U, // SFPC - 0U, // SG - 0U, // SGF - 0U, // SGFR - 0U, // SGH - 0U, // SGR - 0U, // SGRK - 0U, // SH - 0U, // SHHHR - 0U, // SHHLR - 0U, // SHY - 0U, // SIE - 0U, // SIGA - 56U, // SIGP - 0U, // SL - 0U, // SLA - 56U, // SLAG - 56U, // SLAK - 0U, // SLB - 0U, // SLBG - 0U, // SLBGR - 0U, // SLBR - 0U, // SLDA - 0U, // SLDL - 144U, // SLDT - 0U, // SLFI - 0U, // SLG - 0U, // SLGF - 0U, // SLGFI - 0U, // SLGFR - 0U, // SLGR - 0U, // SLGRK - 0U, // SLHHHR - 0U, // SLHHLR - 0U, // SLL - 56U, // SLLG - 56U, // SLLK - 0U, // SLR - 0U, // SLRK - 144U, // SLXT - 0U, // SLY - 0U, // SP - 0U, // SPCTR - 0U, // SPKA - 0U, // SPM - 0U, // SPT - 0U, // SPX - 0U, // SQD - 0U, // SQDB - 0U, // SQDBR - 0U, // SQDR - 0U, // SQE - 0U, // SQEB - 0U, // SQEBR - 0U, // SQER - 0U, // SQXBR - 0U, // SQXR - 0U, // SR - 0U, // SRA - 56U, // SRAG - 56U, // SRAK - 0U, // SRDA - 0U, // SRDL - 144U, // SRDT - 0U, // SRK - 0U, // SRL - 56U, // SRLG - 56U, // SRLK - 0U, // SRNM - 0U, // SRNMB - 0U, // SRNMT - 160U, // SRP - 0U, // SRST - 0U, // SRSTU - 144U, // SRXT - 0U, // SSAIR - 0U, // SSAR - 0U, // SSCH - 48U, // SSKE - 0U, // SSKEOpt - 0U, // SSM - 0U, // ST - 56U, // STAM - 56U, // STAMY - 0U, // STAP - 0U, // STC - 0U, // STCH - 0U, // STCK - 0U, // STCKC - 0U, // STCKE - 0U, // STCKF - 1U, // STCM - 1U, // STCMH - 1U, // STCMY - 0U, // STCPS - 0U, // STCRW - 56U, // STCTG - 56U, // STCTL - 0U, // STCY - 0U, // STD - 0U, // STDY - 0U, // STE - 0U, // STEY - 0U, // STFH - 0U, // STFL - 0U, // STFLE - 0U, // STFPC - 0U, // STG - 0U, // STGRL - 0U, // STGSC - 0U, // STH - 0U, // STHH - 0U, // STHRL - 0U, // STHY - 0U, // STIDP - 56U, // STM - 56U, // STMG - 56U, // STMH - 56U, // STMY - 0U, // STNSM - 0U, // STOC - 128U, // STOCAsm - 0U, // STOCAsmE - 0U, // STOCAsmH - 0U, // STOCAsmHE - 0U, // STOCAsmL - 0U, // STOCAsmLE - 0U, // STOCAsmLH - 0U, // STOCAsmM - 0U, // STOCAsmNE - 0U, // STOCAsmNH - 0U, // STOCAsmNHE - 0U, // STOCAsmNL - 0U, // STOCAsmNLE - 0U, // STOCAsmNLH - 0U, // STOCAsmNM - 0U, // STOCAsmNO - 0U, // STOCAsmNP - 0U, // STOCAsmNZ - 0U, // STOCAsmO - 0U, // STOCAsmP - 0U, // STOCAsmZ - 0U, // STOCFH - 128U, // STOCFHAsm - 0U, // STOCFHAsmE - 0U, // STOCFHAsmH - 0U, // STOCFHAsmHE - 0U, // STOCFHAsmL - 0U, // STOCFHAsmLE - 0U, // STOCFHAsmLH - 0U, // STOCFHAsmM - 0U, // STOCFHAsmNE - 0U, // STOCFHAsmNH - 0U, // STOCFHAsmNHE - 0U, // STOCFHAsmNL - 0U, // STOCFHAsmNLE - 0U, // STOCFHAsmNLH - 0U, // STOCFHAsmNM - 0U, // STOCFHAsmNO - 0U, // STOCFHAsmNP - 0U, // STOCFHAsmNZ - 0U, // STOCFHAsmO - 0U, // STOCFHAsmP - 0U, // STOCFHAsmZ - 0U, // STOCG - 128U, // STOCGAsm - 0U, // STOCGAsmE - 0U, // STOCGAsmH - 0U, // STOCGAsmHE - 0U, // STOCGAsmL - 0U, // STOCGAsmLE - 0U, // STOCGAsmLH - 0U, // STOCGAsmM - 0U, // STOCGAsmNE - 0U, // STOCGAsmNH - 0U, // STOCGAsmNHE - 0U, // STOCGAsmNL - 0U, // STOCGAsmNLE - 0U, // STOCGAsmNLH - 0U, // STOCGAsmNM - 0U, // STOCGAsmNO - 0U, // STOCGAsmNP - 0U, // STOCGAsmNZ - 0U, // STOCGAsmO - 0U, // STOCGAsmP - 0U, // STOCGAsmZ - 0U, // STOSM - 0U, // STPQ - 0U, // STPT - 0U, // STPX - 0U, // STRAG - 0U, // STRL - 0U, // STRV - 0U, // STRVG - 0U, // STRVH - 0U, // STSCH - 0U, // STSI - 0U, // STURA - 0U, // STURG - 0U, // STY - 0U, // SU - 0U, // SUR - 0U, // SVC - 0U, // SW - 0U, // SWR - 0U, // SXBR - 0U, // SXR - 0U, // SXTR - 512U, // SXTRA - 0U, // SY - 0U, // TABORT - 0U, // TAM - 0U, // TAR - 0U, // TB - 41U, // TBDR - 41U, // TBEDR - 0U, // TBEGIN - 0U, // TBEGINC - 0U, // TCDB - 0U, // TCEB - 0U, // TCXB - 0U, // TDCDT - 0U, // TDCET - 0U, // TDCXT - 0U, // TDGDT - 0U, // TDGET - 0U, // TDGXT - 0U, // TEND - 0U, // THDER - 0U, // THDR - 0U, // TM - 0U, // TMHH - 0U, // TMHL - 0U, // TMLH - 0U, // TMLL - 0U, // TMY - 0U, // TP - 0U, // TPI - 0U, // TPROT - 0U, // TR - 56U, // TRACE - 56U, // TRACG - 0U, // TRAP2 - 0U, // TRAP4 - 0U, // TRE - 104U, // TROO - 0U, // TROOOpt - 104U, // TROT - 0U, // TROTOpt - 0U, // TRT - 0U, // TRTE - 0U, // TRTEOpt - 104U, // TRTO - 0U, // TRTOOpt - 0U, // TRTR - 0U, // TRTRE - 0U, // TRTREOpt - 104U, // TRTT - 0U, // TRTTOpt - 0U, // TS - 0U, // TSCH - 0U, // UNPK - 0U, // UNPKA - 0U, // UNPKU - 0U, // UPT - 512U, // VA - 0U, // VAB - 57856U, // VAC - 512U, // VACC - 0U, // VACCB - 57856U, // VACCC - 57856U, // VACCCQ - 0U, // VACCF - 0U, // VACCG - 0U, // VACCH - 0U, // VACCQ - 57856U, // VACQ - 0U, // VAF - 0U, // VAG - 0U, // VAH - 512U, // VAP - 0U, // VAQ - 512U, // VAVG - 0U, // VAVGB - 0U, // VAVGF - 0U, // VAVGG - 0U, // VAVGH - 512U, // VAVGL - 0U, // VAVGLB - 0U, // VAVGLF - 0U, // VAVGLG - 0U, // VAVGLH - 0U, // VBPERM - 560U, // VCDG - 560U, // VCDGB - 560U, // VCDLG - 560U, // VCDLGB - 512U, // VCEQ - 0U, // VCEQB - 0U, // VCEQBS - 0U, // VCEQF - 0U, // VCEQFS - 0U, // VCEQG - 0U, // VCEQGS - 0U, // VCEQH - 0U, // VCEQHS - 560U, // VCGD - 560U, // VCGDB - 512U, // VCH - 0U, // VCHB - 0U, // VCHBS - 0U, // VCHF - 0U, // VCHFS - 0U, // VCHG - 0U, // VCHGS - 0U, // VCHH - 0U, // VCHHS - 512U, // VCHL - 0U, // VCHLB - 0U, // VCHLBS - 0U, // VCHLF - 0U, // VCHLFS - 0U, // VCHLG - 0U, // VCHLGS - 0U, // VCHLH - 0U, // VCHLHS - 0U, // VCKSM - 560U, // VCLGD - 560U, // VCLGDB - 48U, // VCLZ - 0U, // VCLZB - 0U, // VCLZF - 0U, // VCLZG - 0U, // VCLZH - 48U, // VCP - 48U, // VCTZ - 0U, // VCTZB - 0U, // VCTZF - 0U, // VCTZG - 0U, // VCTZH - 48U, // VCVB - 48U, // VCVBG - 10408U, // VCVD - 10408U, // VCVDG - 512U, // VDP - 48U, // VEC - 0U, // VECB - 0U, // VECF - 0U, // VECG - 0U, // VECH - 48U, // VECL - 0U, // VECLB - 0U, // VECLF - 0U, // VECLG - 0U, // VECLH - 49776U, // VERIM - 49776U, // VERIMB - 49776U, // VERIMF - 49776U, // VERIMG - 49776U, // VERIMH - 25144U, // VERLL - 56U, // VERLLB - 56U, // VERLLF - 56U, // VERLLG - 56U, // VERLLH - 512U, // VERLLV - 0U, // VERLLVB - 0U, // VERLLVF - 0U, // VERLLVG - 0U, // VERLLVH - 25144U, // VESL - 56U, // VESLB - 56U, // VESLF - 56U, // VESLG - 56U, // VESLH - 512U, // VESLV - 0U, // VESLVB - 0U, // VESLVF - 0U, // VESLVG - 0U, // VESLVH - 25144U, // VESRA - 56U, // VESRAB - 56U, // VESRAF - 56U, // VESRAG - 56U, // VESRAH - 512U, // VESRAV - 0U, // VESRAVB - 0U, // VESRAVF - 0U, // VESRAVG - 0U, // VESRAVH - 25144U, // VESRL - 56U, // VESRLB - 56U, // VESRLF - 56U, // VESRLG - 56U, // VESRLH - 512U, // VESRLV - 0U, // VESRLVB - 0U, // VESRLVF - 0U, // VESRLVG - 0U, // VESRLVH - 512U, // VFA - 0U, // VFADB - 512U, // VFAE - 512U, // VFAEB - 512U, // VFAEBS - 512U, // VFAEF - 512U, // VFAEFS - 512U, // VFAEH - 512U, // VFAEHS - 512U, // VFAEZB - 512U, // VFAEZBS - 512U, // VFAEZF - 512U, // VFAEZFS - 512U, // VFAEZH - 512U, // VFAEZHS - 0U, // VFASB - 512U, // VFCE - 0U, // VFCEDB - 0U, // VFCEDBS - 0U, // VFCESB - 0U, // VFCESBS - 512U, // VFCH - 0U, // VFCHDB - 0U, // VFCHDBS - 512U, // VFCHE - 0U, // VFCHEDB - 0U, // VFCHEDBS - 0U, // VFCHESB - 0U, // VFCHESBS - 0U, // VFCHSB - 0U, // VFCHSBS - 512U, // VFD - 0U, // VFDDB - 0U, // VFDSB - 512U, // VFEE - 512U, // VFEEB - 0U, // VFEEBS - 512U, // VFEEF - 0U, // VFEEFS - 512U, // VFEEH - 0U, // VFEEHS - 0U, // VFEEZB - 0U, // VFEEZBS - 0U, // VFEEZF - 0U, // VFEEZFS - 0U, // VFEEZH - 0U, // VFEEZHS - 512U, // VFENE - 512U, // VFENEB - 0U, // VFENEBS - 512U, // VFENEF - 0U, // VFENEFS - 512U, // VFENEH - 0U, // VFENEHS - 0U, // VFENEZB - 0U, // VFENEZBS - 0U, // VFENEZF - 0U, // VFENEZFS - 0U, // VFENEZH - 0U, // VFENEZHS - 560U, // VFI - 560U, // VFIDB - 560U, // VFISB - 0U, // VFKEDB - 0U, // VFKEDBS - 0U, // VFKESB - 0U, // VFKESBS - 0U, // VFKHDB - 0U, // VFKHDBS - 0U, // VFKHEDB - 0U, // VFKHEDBS - 0U, // VFKHESB - 0U, // VFKHESBS - 0U, // VFKHSB - 0U, // VFKHSBS - 0U, // VFLCDB - 0U, // VFLCSB - 560U, // VFLL - 0U, // VFLLS - 0U, // VFLNDB - 0U, // VFLNSB - 0U, // VFLPDB - 0U, // VFLPSB - 560U, // VFLR - 560U, // VFLRD - 512U, // VFM - 57856U, // VFMA - 57856U, // VFMADB - 57856U, // VFMASB - 512U, // VFMAX - 512U, // VFMAXDB - 512U, // VFMAXSB - 0U, // VFMDB - 512U, // VFMIN - 512U, // VFMINDB - 512U, // VFMINSB - 57856U, // VFMS - 0U, // VFMSB - 57856U, // VFMSDB - 57856U, // VFMSSB - 57856U, // VFNMA - 57856U, // VFNMADB - 57856U, // VFNMASB - 57856U, // VFNMS - 57856U, // VFNMSDB - 57856U, // VFNMSSB - 560U, // VFPSO - 48U, // VFPSODB - 48U, // VFPSOSB - 512U, // VFS - 0U, // VFSDB - 560U, // VFSQ - 0U, // VFSQDB - 0U, // VFSQSB - 0U, // VFSSB - 688U, // VFTCI - 176U, // VFTCIDB - 176U, // VFTCISB - 0U, // VGBM - 3U, // VGEF - 4U, // VGEG - 512U, // VGFM - 57856U, // VGFMA - 57856U, // VGFMAB - 57856U, // VGFMAF - 57856U, // VGFMAG - 57856U, // VGFMAH - 0U, // VGFMB - 0U, // VGFMF - 0U, // VGFMG - 0U, // VGFMH - 36U, // VGM - 44U, // VGMB - 44U, // VGMF - 44U, // VGMG - 44U, // VGMH - 560U, // VISTR - 48U, // VISTRB - 0U, // VISTRBS - 48U, // VISTRF - 0U, // VISTRFS - 48U, // VISTRH - 0U, // VISTRHS - 0U, // VL - 104U, // VLBB - 48U, // VLC - 0U, // VLCB - 0U, // VLCF - 0U, // VLCG - 0U, // VLCH - 560U, // VLDE - 0U, // VLDEB - 160U, // VLEB - 560U, // VLED - 560U, // VLEDB - 184U, // VLEF - 192U, // VLEG - 200U, // VLEH - 128U, // VLEIB - 208U, // VLEIF - 216U, // VLEIG - 224U, // VLEIH - 25144U, // VLGV - 56U, // VLGVB - 56U, // VLGVF - 56U, // VLGVG - 56U, // VLGVH - 48U, // VLIP - 56U, // VLL - 104U, // VLLEZ - 0U, // VLLEZB - 0U, // VLLEZF - 0U, // VLLEZG - 0U, // VLLEZH - 0U, // VLLEZLF - 56U, // VLM - 48U, // VLP - 0U, // VLPB - 0U, // VLPF - 0U, // VLPG - 0U, // VLPH - 0U, // VLR - 104U, // VLREP - 0U, // VLREPB - 0U, // VLREPF - 0U, // VLREPG - 0U, // VLREPH - 152U, // VLRL - 56U, // VLRLR - 16920U, // VLVG - 24U, // VLVGB - 24U, // VLVGF - 24U, // VLVGG - 24U, // VLVGH - 0U, // VLVGP - 57856U, // VMAE - 57856U, // VMAEB - 57856U, // VMAEF - 57856U, // VMAEH - 57856U, // VMAH - 57856U, // VMAHB - 57856U, // VMAHF - 57856U, // VMAHH - 57856U, // VMAL - 57856U, // VMALB - 57856U, // VMALE - 57856U, // VMALEB - 57856U, // VMALEF - 57856U, // VMALEH - 57856U, // VMALF - 57856U, // VMALH - 57856U, // VMALHB - 57856U, // VMALHF - 57856U, // VMALHH - 57856U, // VMALHW - 57856U, // VMALO - 57856U, // VMALOB - 57856U, // VMALOF - 57856U, // VMALOH - 57856U, // VMAO - 57856U, // VMAOB - 57856U, // VMAOF - 57856U, // VMAOH - 512U, // VME - 0U, // VMEB - 0U, // VMEF - 0U, // VMEH - 512U, // VMH - 0U, // VMHB - 0U, // VMHF - 0U, // VMHH - 512U, // VML - 0U, // VMLB - 512U, // VMLE - 0U, // VMLEB - 0U, // VMLEF - 0U, // VMLEH - 0U, // VMLF - 512U, // VMLH - 0U, // VMLHB - 0U, // VMLHF - 0U, // VMLHH - 0U, // VMLHW - 512U, // VMLO - 0U, // VMLOB - 0U, // VMLOF - 0U, // VMLOH - 512U, // VMN - 0U, // VMNB - 0U, // VMNF - 0U, // VMNG - 0U, // VMNH - 512U, // VMNL - 0U, // VMNLB - 0U, // VMNLF - 0U, // VMNLG - 0U, // VMNLH - 512U, // VMO - 0U, // VMOB - 0U, // VMOF - 0U, // VMOH - 512U, // VMP - 512U, // VMRH - 0U, // VMRHB - 0U, // VMRHF - 0U, // VMRHG - 0U, // VMRHH - 512U, // VMRL - 0U, // VMRLB - 0U, // VMRLF - 0U, // VMRLG - 0U, // VMRLH - 57856U, // VMSL - 57856U, // VMSLG - 512U, // VMSP - 512U, // VMX - 0U, // VMXB - 0U, // VMXF - 0U, // VMXG - 0U, // VMXH - 512U, // VMXL - 0U, // VMXLB - 0U, // VMXLF - 0U, // VMXLG - 0U, // VMXLH - 0U, // VN - 0U, // VNC - 0U, // VNN - 0U, // VNO - 0U, // VNX - 0U, // VO - 0U, // VOC - 0U, // VONE - 512U, // VPDI - 57856U, // VPERM - 512U, // VPK - 0U, // VPKF - 0U, // VPKG - 0U, // VPKH - 512U, // VPKLS - 0U, // VPKLSF - 0U, // VPKLSFS - 0U, // VPKLSG - 0U, // VPKLSGS - 0U, // VPKLSH - 0U, // VPKLSHS - 512U, // VPKS - 0U, // VPKSF - 0U, // VPKSFS - 0U, // VPKSG - 0U, // VPKSGS - 0U, // VPKSH - 0U, // VPKSHS - 152U, // VPKZ - 48U, // VPOPCT - 0U, // VPOPCTB - 0U, // VPOPCTF - 0U, // VPOPCTG - 0U, // VPOPCTH - 4264U, // VPSOP - 744U, // VREP - 232U, // VREPB - 232U, // VREPF - 232U, // VREPG - 232U, // VREPH - 48U, // VREPI - 0U, // VREPIB - 0U, // VREPIF - 0U, // VREPIG - 0U, // VREPIH - 512U, // VRP - 512U, // VS - 0U, // VSB - 57856U, // VSBCBI - 57856U, // VSBCBIQ - 57856U, // VSBI - 57856U, // VSBIQ - 512U, // VSCBI - 0U, // VSCBIB - 0U, // VSCBIF - 0U, // VSCBIG - 0U, // VSCBIH - 0U, // VSCBIQ - 4U, // VSCEF - 4U, // VSCEG - 512U, // VSDP - 48U, // VSEG - 0U, // VSEGB - 0U, // VSEGF - 0U, // VSEGH - 57856U, // VSEL - 0U, // VSF - 0U, // VSG - 0U, // VSH - 0U, // VSL - 0U, // VSLB - 512U, // VSLDB - 512U, // VSP - 0U, // VSQ - 0U, // VSRA - 0U, // VSRAB - 0U, // VSRL - 0U, // VSRLB - 4264U, // VSRP - 0U, // VST - 104U, // VSTEB - 240U, // VSTEF - 248U, // VSTEG - 256U, // VSTEH - 56U, // VSTL - 56U, // VSTM - 57856U, // VSTRC - 57856U, // VSTRCB - 57856U, // VSTRCBS - 57856U, // VSTRCF - 57856U, // VSTRCFS - 57856U, // VSTRCH - 57856U, // VSTRCHS - 57856U, // VSTRCZB - 57856U, // VSTRCZBS - 57856U, // VSTRCZF - 57856U, // VSTRCZFS - 57856U, // VSTRCZH - 57856U, // VSTRCZHS - 152U, // VSTRL - 56U, // VSTRLR - 512U, // VSUM - 0U, // VSUMB - 512U, // VSUMG - 0U, // VSUMGF - 0U, // VSUMGH - 0U, // VSUMH - 512U, // VSUMQ - 0U, // VSUMQF - 0U, // VSUMQG - 0U, // VTM - 0U, // VTP - 48U, // VUPH - 0U, // VUPHB - 0U, // VUPHF - 0U, // VUPHH - 152U, // VUPKZ - 48U, // VUPL - 0U, // VUPLB - 0U, // VUPLF - 48U, // VUPLH - 0U, // VUPLHB - 0U, // VUPLHF - 0U, // VUPLHH - 0U, // VUPLHW - 48U, // VUPLL - 0U, // VUPLLB - 0U, // VUPLLF - 0U, // VUPLLH - 0U, // VX - 0U, // VZERO - 560U, // WCDGB - 560U, // WCDLGB - 560U, // WCGDB - 560U, // WCLGDB - 0U, // WFADB - 0U, // WFASB - 0U, // WFAXB - 560U, // WFC - 0U, // WFCDB - 0U, // WFCEDB - 0U, // WFCEDBS - 0U, // WFCESB - 0U, // WFCESBS - 0U, // WFCEXB - 0U, // WFCEXBS - 0U, // WFCHDB - 0U, // WFCHDBS - 0U, // WFCHEDB - 0U, // WFCHEDBS - 0U, // WFCHESB - 0U, // WFCHESBS - 0U, // WFCHEXB - 0U, // WFCHEXBS - 0U, // WFCHSB - 0U, // WFCHSBS - 0U, // WFCHXB - 0U, // WFCHXBS - 0U, // WFCSB - 0U, // WFCXB - 0U, // WFDDB - 0U, // WFDSB - 0U, // WFDXB - 560U, // WFIDB - 560U, // WFISB - 560U, // WFIXB - 560U, // WFK - 0U, // WFKDB - 0U, // WFKEDB - 0U, // WFKEDBS - 0U, // WFKESB - 0U, // WFKESBS - 0U, // WFKEXB - 0U, // WFKEXBS - 0U, // WFKHDB - 0U, // WFKHDBS - 0U, // WFKHEDB - 0U, // WFKHEDBS - 0U, // WFKHESB - 0U, // WFKHESBS - 0U, // WFKHEXB - 0U, // WFKHEXBS - 0U, // WFKHSB - 0U, // WFKHSBS - 0U, // WFKHXB - 0U, // WFKHXBS - 0U, // WFKSB - 0U, // WFKXB - 0U, // WFLCDB - 0U, // WFLCSB - 0U, // WFLCXB - 0U, // WFLLD - 0U, // WFLLS - 0U, // WFLNDB - 0U, // WFLNSB - 0U, // WFLNXB - 0U, // WFLPDB - 0U, // WFLPSB - 0U, // WFLPXB - 560U, // WFLRD - 560U, // WFLRX - 57856U, // WFMADB - 57856U, // WFMASB - 57856U, // WFMAXB - 512U, // WFMAXDB - 512U, // WFMAXSB - 512U, // WFMAXXB - 0U, // WFMDB - 512U, // WFMINDB - 512U, // WFMINSB - 512U, // WFMINXB - 0U, // WFMSB - 57856U, // WFMSDB - 57856U, // WFMSSB - 57856U, // WFMSXB - 0U, // WFMXB - 57856U, // WFNMADB - 57856U, // WFNMASB - 57856U, // WFNMAXB - 57856U, // WFNMSDB - 57856U, // WFNMSSB - 57856U, // WFNMSXB - 48U, // WFPSODB - 48U, // WFPSOSB - 48U, // WFPSOXB - 0U, // WFSDB - 0U, // WFSQDB - 0U, // WFSQSB - 0U, // WFSQXB - 0U, // WFSSB - 0U, // WFSXB - 176U, // WFTCIDB - 176U, // WFTCISB - 176U, // WFTCIXB - 0U, // WLDEB - 560U, // WLEDB - 0U, // X - 0U, // XC - 0U, // XG - 0U, // XGR - 0U, // XGRK - 0U, // XI - 0U, // XIHF - 0U, // XILF - 0U, // XIY - 0U, // XR - 0U, // XRK - 0U, // XSCH - 0U, // XY - 0U, // ZAP + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADJDYNALLOC + 0U, // AEXT128 + 0U, // AFIMux + 0U, // AHIMux + 0U, // AHIMuxK + 0U, // ATOMIC_CMP_SWAPW + 0U, // ATOMIC_LOADW_AFI + 0U, // ATOMIC_LOADW_AR + 0U, // ATOMIC_LOADW_MAX + 0U, // ATOMIC_LOADW_MIN + 0U, // ATOMIC_LOADW_NILH + 0U, // ATOMIC_LOADW_NILHi + 0U, // ATOMIC_LOADW_NR + 0U, // ATOMIC_LOADW_NRi + 0U, // ATOMIC_LOADW_OILH + 0U, // ATOMIC_LOADW_OR + 0U, // ATOMIC_LOADW_SR + 0U, // ATOMIC_LOADW_UMAX + 0U, // ATOMIC_LOADW_UMIN + 0U, // ATOMIC_LOADW_XILF + 0U, // ATOMIC_LOADW_XR + 0U, // ATOMIC_LOAD_AFI + 0U, // ATOMIC_LOAD_AGFI + 0U, // ATOMIC_LOAD_AGHI + 0U, // ATOMIC_LOAD_AGR + 0U, // ATOMIC_LOAD_AHI + 0U, // ATOMIC_LOAD_AR + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NGR + 0U, // ATOMIC_LOAD_NGRi + 0U, // ATOMIC_LOAD_NIHF64 + 0U, // ATOMIC_LOAD_NIHF64i + 0U, // ATOMIC_LOAD_NIHH64 + 0U, // ATOMIC_LOAD_NIHH64i + 0U, // ATOMIC_LOAD_NIHL64 + 0U, // ATOMIC_LOAD_NIHL64i + 0U, // ATOMIC_LOAD_NILF + 0U, // ATOMIC_LOAD_NILF64 + 0U, // ATOMIC_LOAD_NILF64i + 0U, // ATOMIC_LOAD_NILFi + 0U, // ATOMIC_LOAD_NILH + 0U, // ATOMIC_LOAD_NILH64 + 0U, // ATOMIC_LOAD_NILH64i + 0U, // ATOMIC_LOAD_NILHi + 0U, // ATOMIC_LOAD_NILL + 0U, // ATOMIC_LOAD_NILL64 + 0U, // ATOMIC_LOAD_NILL64i + 0U, // ATOMIC_LOAD_NILLi + 0U, // ATOMIC_LOAD_NR + 0U, // ATOMIC_LOAD_NRi + 0U, // ATOMIC_LOAD_OGR + 0U, // ATOMIC_LOAD_OIHF64 + 0U, // ATOMIC_LOAD_OIHH64 + 0U, // ATOMIC_LOAD_OIHL64 + 0U, // ATOMIC_LOAD_OILF + 0U, // ATOMIC_LOAD_OILF64 + 0U, // ATOMIC_LOAD_OILH + 0U, // ATOMIC_LOAD_OILH64 + 0U, // ATOMIC_LOAD_OILL + 0U, // ATOMIC_LOAD_OILL64 + 0U, // ATOMIC_LOAD_OR + 0U, // ATOMIC_LOAD_SGR + 0U, // ATOMIC_LOAD_SR + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XGR + 0U, // ATOMIC_LOAD_XIHF64 + 0U, // ATOMIC_LOAD_XILF + 0U, // ATOMIC_LOAD_XILF64 + 0U, // ATOMIC_LOAD_XR + 0U, // ATOMIC_SWAPW + 0U, // ATOMIC_SWAP_32 + 0U, // ATOMIC_SWAP_64 + 0U, // CFIMux + 0U, // CGIBCall + 0U, // CGIBReturn + 0U, // CGRBCall + 0U, // CGRBReturn + 0U, // CHIMux + 0U, // CIBCall + 0U, // CIBReturn + 0U, // CLCLoop + 0U, // CLCSequence + 0U, // CLFIMux + 0U, // CLGIBCall + 0U, // CLGIBReturn + 0U, // CLGRBCall + 0U, // CLGRBReturn + 0U, // CLIBCall + 0U, // CLIBReturn + 0U, // CLMux + 0U, // CLRBCall + 0U, // CLRBReturn + 0U, // CLSTLoop + 0U, // CMux + 0U, // CRBCall + 0U, // CRBReturn + 0U, // CallBASR + 0U, // CallBCR + 0U, // CallBR + 0U, // CallBRASL + 0U, // CallBRCL + 0U, // CallJG + 0U, // CondReturn + 0U, // CondStore16 + 0U, // CondStore16Inv + 0U, // CondStore16Mux + 0U, // CondStore16MuxInv + 0U, // CondStore32 + 0U, // CondStore32Inv + 0U, // CondStore32Mux + 0U, // CondStore32MuxInv + 0U, // CondStore64 + 0U, // CondStore64Inv + 0U, // CondStore8 + 0U, // CondStore8Inv + 0U, // CondStore8Mux + 0U, // CondStore8MuxInv + 0U, // CondStoreF32 + 0U, // CondStoreF32Inv + 0U, // CondStoreF64 + 0U, // CondStoreF64Inv + 0U, // CondTrap + 0U, // GOT + 0U, // IIFMux + 0U, // IIHF64 + 0U, // IIHH64 + 0U, // IIHL64 + 0U, // IIHMux + 0U, // IILF64 + 0U, // IILH64 + 0U, // IILL64 + 0U, // IILMux + 0U, // L128 + 0U, // LBMux + 0U, // LEFR + 0U, // LFER + 0U, // LHIMux + 0U, // LHMux + 0U, // LLCMux + 0U, // LLCRMux + 0U, // LLHMux + 0U, // LLHRMux + 0U, // LMux + 0U, // LOCHIMux + 0U, // LOCMux + 0U, // LOCRMux + 0U, // LRMux + 0U, // LTDBRCompare_VecPseudo + 0U, // LTEBRCompare_VecPseudo + 0U, // LTXBRCompare_VecPseudo + 0U, // LX + 0U, // MVCLoop + 0U, // MVCSequence + 0U, // MVSTLoop + 0U, // MemBarrier + 0U, // NCLoop + 0U, // NCSequence + 0U, // NIFMux + 0U, // NIHF64 + 0U, // NIHH64 + 0U, // NIHL64 + 0U, // NIHMux + 0U, // NILF64 + 0U, // NILH64 + 0U, // NILL64 + 0U, // NILMux + 0U, // OCLoop + 0U, // OCSequence + 0U, // OIFMux + 0U, // OIHF64 + 0U, // OIHH64 + 0U, // OIHL64 + 0U, // OIHMux + 0U, // OILF64 + 0U, // OILH64 + 0U, // OILL64 + 0U, // OILMux + 0U, // PAIR128 + 0U, // RISBHH + 0U, // RISBHL + 0U, // RISBLH + 0U, // RISBLL + 0U, // RISBMux + 0U, // Return + 0U, // SRSTLoop + 0U, // ST128 + 0U, // STCMux + 0U, // STHMux + 0U, // STMux + 0U, // STOCMux + 0U, // STX + 0U, // Select32 + 0U, // Select64 + 0U, // SelectF128 + 0U, // SelectF32 + 0U, // SelectF64 + 0U, // SelectVR128 + 0U, // SelectVR32 + 0U, // SelectVR64 + 0U, // Serialize + 0U, // TBEGIN_nofloat + 0U, // TLS_GDCALL + 0U, // TLS_LDCALL + 0U, // TMHH64 + 0U, // TMHL64 + 0U, // TMHMux + 0U, // TMLH64 + 0U, // TMLL64 + 0U, // TMLMux + 0U, // Trap + 0U, // VL32 + 0U, // VL64 + 0U, // VLR32 + 0U, // VLR64 + 0U, // VLVGP32 + 0U, // VST32 + 0U, // VST64 + 0U, // XCLoop + 0U, // XCSequence + 0U, // XIFMux + 0U, // XIHF64 + 0U, // XILF64 + 0U, // ZEXT128 + 0U, // A + 0U, // AD + 0U, // ADB + 0U, // ADBR + 0U, // ADR + 0U, // ADTR + 512U, // ADTRA + 0U, // AE + 0U, // AEB + 0U, // AEBR + 0U, // AER + 0U, // AFI + 0U, // AG + 0U, // AGF + 0U, // AGFI + 0U, // AGFR + 0U, // AGH + 0U, // AGHI + 8U, // AGHIK + 0U, // AGR + 0U, // AGRK + 0U, // AGSI + 0U, // AH + 0U, // AHHHR + 0U, // AHHLR + 0U, // AHI + 8U, // AHIK + 0U, // AHY + 0U, // AIH + 0U, // AL + 0U, // ALC + 0U, // ALCG + 0U, // ALCGR + 0U, // ALCR + 0U, // ALFI + 0U, // ALG + 0U, // ALGF + 0U, // ALGFI + 0U, // ALGFR + 8U, // ALGHSIK + 0U, // ALGR + 0U, // ALGRK + 0U, // ALGSI + 0U, // ALHHHR + 0U, // ALHHLR + 8U, // ALHSIK + 0U, // ALR + 0U, // ALRK + 0U, // ALSI + 0U, // ALSIH + 0U, // ALSIHN + 0U, // ALY + 0U, // AP + 0U, // AR + 0U, // ARK + 0U, // ASI + 0U, // AU + 0U, // AUR + 0U, // AW + 0U, // AWR + 0U, // AXBR + 0U, // AXR + 0U, // AXTR + 512U, // AXTRA + 0U, // AY + 0U, // B + 0U, // BAKR + 0U, // BAL + 0U, // BALR + 0U, // BAS + 0U, // BASR + 0U, // BASSM + 0U, // BAsmE + 0U, // BAsmH + 0U, // BAsmHE + 0U, // BAsmL + 0U, // BAsmLE + 0U, // BAsmLH + 0U, // BAsmM + 0U, // BAsmNE + 0U, // BAsmNH + 0U, // BAsmNHE + 0U, // BAsmNL + 0U, // BAsmNLE + 0U, // BAsmNLH + 0U, // BAsmNM + 0U, // BAsmNO + 0U, // BAsmNP + 0U, // BAsmNZ + 0U, // BAsmO + 0U, // BAsmP + 0U, // BAsmZ + 0U, // BC + 0U, // BCAsm + 0U, // BCR + 0U, // BCRAsm + 0U, // BCT + 0U, // BCTG + 0U, // BCTGR + 0U, // BCTR + 0U, // BI + 0U, // BIAsmE + 0U, // BIAsmH + 0U, // BIAsmHE + 0U, // BIAsmL + 0U, // BIAsmLE + 0U, // BIAsmLH + 0U, // BIAsmM + 0U, // BIAsmNE + 0U, // BIAsmNH + 0U, // BIAsmNHE + 0U, // BIAsmNL + 0U, // BIAsmNLE + 0U, // BIAsmNLH + 0U, // BIAsmNM + 0U, // BIAsmNO + 0U, // BIAsmNP + 0U, // BIAsmNZ + 0U, // BIAsmO + 0U, // BIAsmP + 0U, // BIAsmZ + 0U, // BIC + 0U, // BICAsm + 0U, // BPP + 0U, // BPRP + 0U, // BR + 0U, // BRAS + 0U, // BRASL + 0U, // BRAsmE + 0U, // BRAsmH + 0U, // BRAsmHE + 0U, // BRAsmL + 0U, // BRAsmLE + 0U, // BRAsmLH + 0U, // BRAsmM + 0U, // BRAsmNE + 0U, // BRAsmNH + 0U, // BRAsmNHE + 0U, // BRAsmNL + 0U, // BRAsmNLE + 0U, // BRAsmNLH + 0U, // BRAsmNM + 0U, // BRAsmNO + 0U, // BRAsmNP + 0U, // BRAsmNZ + 0U, // BRAsmO + 0U, // BRAsmP + 0U, // BRAsmZ + 0U, // BRC + 0U, // BRCAsm + 0U, // BRCL + 0U, // BRCLAsm + 0U, // BRCT + 0U, // BRCTG + 0U, // BRCTH + 16U, // BRXH + 16U, // BRXHG + 16U, // BRXLE + 16U, // BRXLG + 0U, // BSA + 0U, // BSG + 0U, // BSM + 24U, // BXH + 24U, // BXHG + 24U, // BXLE + 24U, // BXLEG + 0U, // C + 0U, // CD + 0U, // CDB + 0U, // CDBR + 0U, // CDFBR + 33U, // CDFBRA + 0U, // CDFR + 33U, // CDFTR + 0U, // CDGBR + 33U, // CDGBRA + 0U, // CDGR + 0U, // CDGTR + 33U, // CDGTRA + 33U, // CDLFBR + 33U, // CDLFTR + 33U, // CDLGBR + 33U, // CDLGTR + 0U, // CDPT + 0U, // CDR + 24U, // CDS + 24U, // CDSG + 0U, // CDSTR + 24U, // CDSY + 0U, // CDTR + 0U, // CDUTR + 0U, // CDZT + 0U, // CE + 0U, // CEB + 0U, // CEBR + 0U, // CEDTR + 0U, // CEFBR + 33U, // CEFBRA + 0U, // CEFR + 0U, // CEGBR + 33U, // CEGBRA + 0U, // CEGR + 33U, // CELFBR + 33U, // CELGBR + 0U, // CER + 0U, // CEXTR + 0U, // CFC + 41U, // CFDBR + 33U, // CFDBRA + 41U, // CFDR + 33U, // CFDTR + 41U, // CFEBR + 33U, // CFEBRA + 41U, // CFER + 0U, // CFI + 41U, // CFXBR + 33U, // CFXBRA + 41U, // CFXR + 33U, // CFXTR + 0U, // CG + 41U, // CGDBR + 33U, // CGDBRA + 41U, // CGDR + 41U, // CGDTR + 33U, // CGDTRA + 41U, // CGEBR + 33U, // CGEBRA + 41U, // CGER + 0U, // CGF + 0U, // CGFI + 0U, // CGFR + 0U, // CGFRL + 0U, // CGH + 0U, // CGHI + 0U, // CGHRL + 0U, // CGHSI + 0U, // CGIB + 25U, // CGIBAsm + 1U, // CGIBAsmE + 1U, // CGIBAsmH + 1U, // CGIBAsmHE + 1U, // CGIBAsmL + 1U, // CGIBAsmLE + 1U, // CGIBAsmLH + 1U, // CGIBAsmNE + 1U, // CGIBAsmNH + 1U, // CGIBAsmNHE + 1U, // CGIBAsmNL + 1U, // CGIBAsmNLE + 1U, // CGIBAsmNLH + 0U, // CGIJ + 17U, // CGIJAsm + 0U, // CGIJAsmE + 0U, // CGIJAsmH + 0U, // CGIJAsmHE + 0U, // CGIJAsmL + 0U, // CGIJAsmLE + 0U, // CGIJAsmLH + 0U, // CGIJAsmNE + 0U, // CGIJAsmNH + 0U, // CGIJAsmNHE + 0U, // CGIJAsmNL + 0U, // CGIJAsmNLE + 0U, // CGIJAsmNLH + 0U, // CGIT + 48U, // CGITAsm + 0U, // CGITAsmE + 0U, // CGITAsmH + 0U, // CGITAsmHE + 0U, // CGITAsmL + 0U, // CGITAsmLE + 0U, // CGITAsmLH + 0U, // CGITAsmNE + 0U, // CGITAsmNH + 0U, // CGITAsmNHE + 0U, // CGITAsmNL + 0U, // CGITAsmNLE + 0U, // CGITAsmNLH + 0U, // CGR + 41U, // CGRB + 8752U, // CGRBAsm + 56U, // CGRBAsmE + 56U, // CGRBAsmH + 56U, // CGRBAsmHE + 56U, // CGRBAsmL + 56U, // CGRBAsmLE + 56U, // CGRBAsmLH + 56U, // CGRBAsmNE + 56U, // CGRBAsmNH + 56U, // CGRBAsmNHE + 56U, // CGRBAsmNL + 56U, // CGRBAsmNLE + 56U, // CGRBAsmNLH + 2U, // CGRJ + 16944U, // CGRJAsm + 64U, // CGRJAsmE + 64U, // CGRJAsmH + 64U, // CGRJAsmHE + 64U, // CGRJAsmL + 64U, // CGRJAsmLE + 64U, // CGRJAsmLH + 64U, // CGRJAsmNE + 64U, // CGRJAsmNH + 64U, // CGRJAsmNHE + 64U, // CGRJAsmNL + 64U, // CGRJAsmNLE + 64U, // CGRJAsmNLH + 0U, // CGRL + 0U, // CGRT + 48U, // CGRTAsm + 0U, // CGRTAsmE + 0U, // CGRTAsmH + 0U, // CGRTAsmHE + 0U, // CGRTAsmL + 0U, // CGRTAsmLE + 0U, // CGRTAsmLH + 0U, // CGRTAsmNE + 0U, // CGRTAsmNH + 0U, // CGRTAsmNHE + 0U, // CGRTAsmNL + 0U, // CGRTAsmNLE + 0U, // CGRTAsmNLH + 41U, // CGXBR + 33U, // CGXBRA + 41U, // CGXR + 41U, // CGXTR + 33U, // CGXTRA + 0U, // CH + 0U, // CHF + 0U, // CHHR + 0U, // CHHSI + 0U, // CHI + 0U, // CHLR + 0U, // CHRL + 0U, // CHSI + 0U, // CHY + 0U, // CIB + 25U, // CIBAsm + 1U, // CIBAsmE + 1U, // CIBAsmH + 1U, // CIBAsmHE + 1U, // CIBAsmL + 1U, // CIBAsmLE + 1U, // CIBAsmLH + 1U, // CIBAsmNE + 1U, // CIBAsmNH + 1U, // CIBAsmNHE + 1U, // CIBAsmNL + 1U, // CIBAsmNLE + 1U, // CIBAsmNLH + 0U, // CIH + 0U, // CIJ + 17U, // CIJAsm + 0U, // CIJAsmE + 0U, // CIJAsmH + 0U, // CIJAsmHE + 0U, // CIJAsmL + 0U, // CIJAsmLE + 0U, // CIJAsmLH + 0U, // CIJAsmNE + 0U, // CIJAsmNH + 0U, // CIJAsmNHE + 0U, // CIJAsmNL + 0U, // CIJAsmNLE + 0U, // CIJAsmNLH + 0U, // CIT + 48U, // CITAsm + 0U, // CITAsmE + 0U, // CITAsmH + 0U, // CITAsmHE + 0U, // CITAsmL + 0U, // CITAsmLE + 0U, // CITAsmLH + 0U, // CITAsmNE + 0U, // CITAsmNH + 0U, // CITAsmNHE + 0U, // CITAsmNL + 0U, // CITAsmNLE + 0U, // CITAsmNLH + 0U, // CKSM + 0U, // CL + 0U, // CLC + 0U, // CLCL + 72U, // CLCLE + 72U, // CLCLU + 33U, // CLFDBR + 33U, // CLFDTR + 33U, // CLFEBR + 0U, // CLFHSI + 0U, // CLFI + 0U, // CLFIT + 48U, // CLFITAsm + 0U, // CLFITAsmE + 0U, // CLFITAsmH + 0U, // CLFITAsmHE + 0U, // CLFITAsmL + 0U, // CLFITAsmLE + 0U, // CLFITAsmLH + 0U, // CLFITAsmNE + 0U, // CLFITAsmNH + 0U, // CLFITAsmNHE + 0U, // CLFITAsmNL + 0U, // CLFITAsmNLE + 0U, // CLFITAsmNLH + 33U, // CLFXBR + 33U, // CLFXTR + 0U, // CLG + 33U, // CLGDBR + 33U, // CLGDTR + 33U, // CLGEBR + 0U, // CLGF + 0U, // CLGFI + 0U, // CLGFR + 0U, // CLGFRL + 0U, // CLGHRL + 0U, // CLGHSI + 0U, // CLGIB + 25U, // CLGIBAsm + 1U, // CLGIBAsmE + 1U, // CLGIBAsmH + 1U, // CLGIBAsmHE + 1U, // CLGIBAsmL + 1U, // CLGIBAsmLE + 1U, // CLGIBAsmLH + 1U, // CLGIBAsmNE + 1U, // CLGIBAsmNH + 1U, // CLGIBAsmNHE + 1U, // CLGIBAsmNL + 1U, // CLGIBAsmNLE + 1U, // CLGIBAsmNLH + 0U, // CLGIJ + 17U, // CLGIJAsm + 0U, // CLGIJAsmE + 0U, // CLGIJAsmH + 0U, // CLGIJAsmHE + 0U, // CLGIJAsmL + 0U, // CLGIJAsmLE + 0U, // CLGIJAsmLH + 0U, // CLGIJAsmNE + 0U, // CLGIJAsmNH + 0U, // CLGIJAsmNHE + 0U, // CLGIJAsmNL + 0U, // CLGIJAsmNLE + 0U, // CLGIJAsmNLH + 0U, // CLGIT + 48U, // CLGITAsm + 0U, // CLGITAsmE + 0U, // CLGITAsmH + 0U, // CLGITAsmHE + 0U, // CLGITAsmL + 0U, // CLGITAsmLE + 0U, // CLGITAsmLH + 0U, // CLGITAsmNE + 0U, // CLGITAsmNH + 0U, // CLGITAsmNHE + 0U, // CLGITAsmNL + 0U, // CLGITAsmNLE + 0U, // CLGITAsmNLH + 0U, // CLGR + 41U, // CLGRB + 8752U, // CLGRBAsm + 56U, // CLGRBAsmE + 56U, // CLGRBAsmH + 56U, // CLGRBAsmHE + 56U, // CLGRBAsmL + 56U, // CLGRBAsmLE + 56U, // CLGRBAsmLH + 56U, // CLGRBAsmNE + 56U, // CLGRBAsmNH + 56U, // CLGRBAsmNHE + 56U, // CLGRBAsmNL + 56U, // CLGRBAsmNLE + 56U, // CLGRBAsmNLH + 2U, // CLGRJ + 16944U, // CLGRJAsm + 64U, // CLGRJAsmE + 64U, // CLGRJAsmH + 64U, // CLGRJAsmHE + 64U, // CLGRJAsmL + 64U, // CLGRJAsmLE + 64U, // CLGRJAsmLH + 64U, // CLGRJAsmNE + 64U, // CLGRJAsmNH + 64U, // CLGRJAsmNHE + 64U, // CLGRJAsmNL + 64U, // CLGRJAsmNLE + 64U, // CLGRJAsmNLH + 0U, // CLGRL + 0U, // CLGRT + 48U, // CLGRTAsm + 0U, // CLGRTAsmE + 0U, // CLGRTAsmH + 0U, // CLGRTAsmHE + 0U, // CLGRTAsmL + 0U, // CLGRTAsmLE + 0U, // CLGRTAsmLH + 0U, // CLGRTAsmNE + 0U, // CLGRTAsmNH + 0U, // CLGRTAsmNHE + 0U, // CLGRTAsmNL + 0U, // CLGRTAsmNLE + 0U, // CLGRTAsmNLH + 0U, // CLGT + 80U, // CLGTAsm + 0U, // CLGTAsmE + 0U, // CLGTAsmH + 0U, // CLGTAsmHE + 0U, // CLGTAsmL + 0U, // CLGTAsmLE + 0U, // CLGTAsmLH + 0U, // CLGTAsmNE + 0U, // CLGTAsmNH + 0U, // CLGTAsmNHE + 0U, // CLGTAsmNL + 0U, // CLGTAsmNLE + 0U, // CLGTAsmNLH + 33U, // CLGXBR + 33U, // CLGXTR + 0U, // CLHF + 0U, // CLHHR + 0U, // CLHHSI + 0U, // CLHLR + 0U, // CLHRL + 0U, // CLI + 0U, // CLIB + 25U, // CLIBAsm + 1U, // CLIBAsmE + 1U, // CLIBAsmH + 1U, // CLIBAsmHE + 1U, // CLIBAsmL + 1U, // CLIBAsmLE + 1U, // CLIBAsmLH + 1U, // CLIBAsmNE + 1U, // CLIBAsmNH + 1U, // CLIBAsmNHE + 1U, // CLIBAsmNL + 1U, // CLIBAsmNLE + 1U, // CLIBAsmNLH + 0U, // CLIH + 0U, // CLIJ + 17U, // CLIJAsm + 0U, // CLIJAsmE + 0U, // CLIJAsmH + 0U, // CLIJAsmHE + 0U, // CLIJAsmL + 0U, // CLIJAsmLE + 0U, // CLIJAsmLH + 0U, // CLIJAsmNE + 0U, // CLIJAsmNH + 0U, // CLIJAsmNHE + 0U, // CLIJAsmNL + 0U, // CLIJAsmNLE + 0U, // CLIJAsmNLH + 0U, // CLIY + 1U, // CLM + 1U, // CLMH + 1U, // CLMY + 0U, // CLR + 41U, // CLRB + 8752U, // CLRBAsm + 56U, // CLRBAsmE + 56U, // CLRBAsmH + 56U, // CLRBAsmHE + 56U, // CLRBAsmL + 56U, // CLRBAsmLE + 56U, // CLRBAsmLH + 56U, // CLRBAsmNE + 56U, // CLRBAsmNH + 56U, // CLRBAsmNHE + 56U, // CLRBAsmNL + 56U, // CLRBAsmNLE + 56U, // CLRBAsmNLH + 2U, // CLRJ + 16944U, // CLRJAsm + 64U, // CLRJAsmE + 64U, // CLRJAsmH + 64U, // CLRJAsmHE + 64U, // CLRJAsmL + 64U, // CLRJAsmLE + 64U, // CLRJAsmLH + 64U, // CLRJAsmNE + 64U, // CLRJAsmNH + 64U, // CLRJAsmNHE + 64U, // CLRJAsmNL + 64U, // CLRJAsmNLE + 64U, // CLRJAsmNLH + 0U, // CLRL + 0U, // CLRT + 48U, // CLRTAsm + 0U, // CLRTAsmE + 0U, // CLRTAsmH + 0U, // CLRTAsmHE + 0U, // CLRTAsmL + 0U, // CLRTAsmLE + 0U, // CLRTAsmLH + 0U, // CLRTAsmNE + 0U, // CLRTAsmNH + 0U, // CLRTAsmNHE + 0U, // CLRTAsmNL + 0U, // CLRTAsmNLE + 0U, // CLRTAsmNLH + 0U, // CLST + 0U, // CLT + 80U, // CLTAsm + 0U, // CLTAsmE + 0U, // CLTAsmH + 0U, // CLTAsmHE + 0U, // CLTAsmL + 0U, // CLTAsmLE + 0U, // CLTAsmLH + 0U, // CLTAsmNE + 0U, // CLTAsmNH + 0U, // CLTAsmNHE + 0U, // CLTAsmNL + 0U, // CLTAsmNLE + 0U, // CLTAsmNLH + 0U, // CLY + 0U, // CMPSC + 0U, // CP + 0U, // CPDT + 88U, // CPSDRdd + 88U, // CPSDRds + 88U, // CPSDRsd + 88U, // CPSDRss + 0U, // CPXT + 0U, // CPYA + 0U, // CR + 41U, // CRB + 8752U, // CRBAsm + 56U, // CRBAsmE + 56U, // CRBAsmH + 56U, // CRBAsmHE + 56U, // CRBAsmL + 56U, // CRBAsmLE + 56U, // CRBAsmLH + 56U, // CRBAsmNE + 56U, // CRBAsmNH + 56U, // CRBAsmNHE + 56U, // CRBAsmNL + 56U, // CRBAsmNLE + 56U, // CRBAsmNLH + 600U, // CRDTE + 88U, // CRDTEOpt + 2U, // CRJ + 16944U, // CRJAsm + 64U, // CRJAsmE + 64U, // CRJAsmH + 64U, // CRJAsmHE + 64U, // CRJAsmL + 64U, // CRJAsmLE + 64U, // CRJAsmLH + 64U, // CRJAsmNE + 64U, // CRJAsmNH + 64U, // CRJAsmNHE + 64U, // CRJAsmNL + 64U, // CRJAsmNLE + 64U, // CRJAsmNLH + 0U, // CRL + 0U, // CRT + 48U, // CRTAsm + 0U, // CRTAsmE + 0U, // CRTAsmH + 0U, // CRTAsmHE + 0U, // CRTAsmL + 0U, // CRTAsmLE + 0U, // CRTAsmLH + 0U, // CRTAsmNE + 0U, // CRTAsmNH + 0U, // CRTAsmNHE + 0U, // CRTAsmNL + 0U, // CRTAsmNLE + 0U, // CRTAsmNLH + 24U, // CS + 0U, // CSCH + 48U, // CSDTR + 24U, // CSG + 0U, // CSP + 0U, // CSPG + 96U, // CSST + 48U, // CSXTR + 24U, // CSY + 104U, // CU12 + 0U, // CU12Opt + 104U, // CU14 + 0U, // CU14Opt + 104U, // CU21 + 0U, // CU21Opt + 104U, // CU24 + 0U, // CU24Opt + 0U, // CU41 + 0U, // CU42 + 0U, // CUDTR + 0U, // CUSE + 104U, // CUTFU + 0U, // CUTFUOpt + 104U, // CUUTF + 0U, // CUUTFOpt + 0U, // CUXTR + 0U, // CVB + 0U, // CVBG + 0U, // CVBY + 0U, // CVD + 0U, // CVDG + 0U, // CVDY + 0U, // CXBR + 0U, // CXFBR + 33U, // CXFBRA + 0U, // CXFR + 33U, // CXFTR + 0U, // CXGBR + 33U, // CXGBRA + 0U, // CXGR + 0U, // CXGTR + 33U, // CXGTRA + 33U, // CXLFBR + 33U, // CXLFTR + 33U, // CXLGBR + 33U, // CXLGTR + 0U, // CXPT + 0U, // CXR + 0U, // CXSTR + 0U, // CXTR + 0U, // CXUTR + 0U, // CXZT + 0U, // CY + 0U, // CZDT + 0U, // CZXT + 0U, // D + 0U, // DD + 0U, // DDB + 0U, // DDBR + 0U, // DDR + 0U, // DDTR + 512U, // DDTRA + 0U, // DE + 0U, // DEB + 0U, // DEBR + 0U, // DER + 56U, // DIAG + 25200U, // DIDBR + 25200U, // DIEBR + 0U, // DL + 0U, // DLG + 0U, // DLGR + 0U, // DLR + 0U, // DP + 0U, // DR + 0U, // DSG + 0U, // DSGF + 0U, // DSGFR + 0U, // DSGR + 0U, // DXBR + 0U, // DXR + 0U, // DXTR + 512U, // DXTRA + 0U, // EAR + 56U, // ECAG + 0U, // ECCTR + 0U, // ECPGA + 96U, // ECTG + 0U, // ED + 0U, // EDMK + 0U, // EEDTR + 0U, // EEXTR + 0U, // EFPC + 0U, // EPAIR + 0U, // EPAR + 0U, // EPCTR + 0U, // EPSW + 0U, // EREG + 0U, // EREGG + 0U, // ESAIR + 0U, // ESAR + 0U, // ESDTR + 0U, // ESEA + 0U, // ESTA + 0U, // ESXTR + 0U, // ETND + 0U, // EX + 0U, // EXRL + 41U, // FIDBR + 33U, // FIDBRA + 0U, // FIDR + 33U, // FIDTR + 41U, // FIEBR + 33U, // FIEBRA + 0U, // FIER + 41U, // FIXBR + 33U, // FIXBRA + 0U, // FIXR + 33U, // FIXTR + 0U, // FLOGR + 0U, // HDR + 0U, // HER + 0U, // HSCH + 0U, // IAC + 0U, // IC + 0U, // IC32 + 0U, // IC32Y + 0U, // ICM + 0U, // ICMH + 0U, // ICMY + 0U, // ICY + 600U, // IDTE + 88U, // IDTEOpt + 88U, // IEDTR + 88U, // IEXTR + 0U, // IIHF + 0U, // IIHH + 0U, // IIHL + 0U, // IILF + 0U, // IILH + 0U, // IILL + 0U, // IPK + 0U, // IPM + 512U, // IPTE + 0U, // IPTEOpt + 0U, // IPTEOptOpt + 0U, // IRBM + 0U, // ISKE + 0U, // IVSK + 0U, // InsnE + 2U, // InsnRI + 1145U, // InsnRIE + 0U, // InsnRIL + 2U, // InsnRILU + 2U, // InsnRIS + 0U, // InsnRR + 41U, // InsnRRE + 1657U, // InsnRRF + 34937U, // InsnRRS + 2681U, // InsnRS + 2681U, // InsnRSE + 1145U, // InsnRSI + 2681U, // InsnRSY + 0U, // InsnRX + 0U, // InsnRXE + 3193U, // InsnRXF + 0U, // InsnRXY + 0U, // InsnS + 3U, // InsnSI + 3U, // InsnSIL + 3U, // InsnSIY + 0U, // InsnSS + 41U, // InsnSSE + 3705U, // InsnSSF + 0U, // J + 0U, // JAsmE + 0U, // JAsmH + 0U, // JAsmHE + 0U, // JAsmL + 0U, // JAsmLE + 0U, // JAsmLH + 0U, // JAsmM + 0U, // JAsmNE + 0U, // JAsmNH + 0U, // JAsmNHE + 0U, // JAsmNL + 0U, // JAsmNLE + 0U, // JAsmNLH + 0U, // JAsmNM + 0U, // JAsmNO + 0U, // JAsmNP + 0U, // JAsmNZ + 0U, // JAsmO + 0U, // JAsmP + 0U, // JAsmZ + 0U, // JG + 0U, // JGAsmE + 0U, // JGAsmH + 0U, // JGAsmHE + 0U, // JGAsmL + 0U, // JGAsmLE + 0U, // JGAsmLH + 0U, // JGAsmM + 0U, // JGAsmNE + 0U, // JGAsmNH + 0U, // JGAsmNHE + 0U, // JGAsmNL + 0U, // JGAsmNLE + 0U, // JGAsmNLH + 0U, // JGAsmNM + 0U, // JGAsmNO + 0U, // JGAsmNP + 0U, // JGAsmNZ + 0U, // JGAsmO + 0U, // JGAsmP + 0U, // JGAsmZ + 0U, // KDB + 0U, // KDBR + 0U, // KDTR + 0U, // KEB + 0U, // KEBR + 0U, // KIMD + 0U, // KLMD + 0U, // KM + 88U, // KMA + 0U, // KMAC + 0U, // KMC + 88U, // KMCTR + 0U, // KMF + 0U, // KMO + 0U, // KXBR + 0U, // KXTR + 0U, // L + 0U, // LA + 56U, // LAA + 56U, // LAAG + 56U, // LAAL + 56U, // LAALG + 0U, // LAE + 0U, // LAEY + 56U, // LAM + 56U, // LAMY + 56U, // LAN + 56U, // LANG + 56U, // LAO + 56U, // LAOG + 0U, // LARL + 0U, // LASP + 0U, // LAT + 56U, // LAX + 56U, // LAXG + 0U, // LAY + 0U, // LB + 0U, // LBH + 0U, // LBR + 104U, // LCBB + 0U, // LCCTL + 0U, // LCDBR + 0U, // LCDFR + 0U, // LCDFR_32 + 0U, // LCDR + 0U, // LCEBR + 0U, // LCER + 0U, // LCGFR + 0U, // LCGR + 0U, // LCR + 56U, // LCTL + 56U, // LCTLG + 0U, // LCXBR + 0U, // LCXR + 0U, // LD + 0U, // LDE + 0U, // LDE32 + 0U, // LDEB + 0U, // LDEBR + 0U, // LDER + 48U, // LDETR + 0U, // LDGR + 0U, // LDR + 0U, // LDR32 + 0U, // LDXBR + 33U, // LDXBRA + 0U, // LDXR + 33U, // LDXTR + 0U, // LDY + 0U, // LE + 0U, // LEDBR + 33U, // LEDBRA + 0U, // LEDR + 33U, // LEDTR + 0U, // LER + 0U, // LEXBR + 33U, // LEXBRA + 0U, // LEXR + 0U, // LEY + 0U, // LFAS + 0U, // LFH + 0U, // LFHAT + 0U, // LFPC + 0U, // LG + 0U, // LGAT + 0U, // LGB + 0U, // LGBR + 0U, // LGDR + 0U, // LGF + 0U, // LGFI + 0U, // LGFR + 0U, // LGFRL + 0U, // LGG + 0U, // LGH + 0U, // LGHI + 0U, // LGHR + 0U, // LGHRL + 0U, // LGR + 0U, // LGRL + 0U, // LGSC + 0U, // LH + 0U, // LHH + 0U, // LHI + 0U, // LHR + 0U, // LHRL + 0U, // LHY + 0U, // LLC + 0U, // LLCH + 0U, // LLCR + 0U, // LLGC + 0U, // LLGCR + 0U, // LLGF + 0U, // LLGFAT + 0U, // LLGFR + 0U, // LLGFRL + 0U, // LLGFSG + 0U, // LLGH + 0U, // LLGHR + 0U, // LLGHRL + 0U, // LLGT + 0U, // LLGTAT + 0U, // LLGTR + 0U, // LLH + 0U, // LLHH + 0U, // LLHR + 0U, // LLHRL + 0U, // LLIHF + 0U, // LLIHH + 0U, // LLIHL + 0U, // LLILF + 0U, // LLILH + 0U, // LLILL + 0U, // LLZRGF + 56U, // LM + 41528U, // LMD + 56U, // LMG + 56U, // LMH + 56U, // LMY + 0U, // LNDBR + 0U, // LNDFR + 0U, // LNDFR_32 + 0U, // LNDR + 0U, // LNEBR + 0U, // LNER + 0U, // LNGFR + 0U, // LNGR + 0U, // LNR + 0U, // LNXBR + 0U, // LNXR + 0U, // LOC + 104U, // LOCAsm + 0U, // LOCAsmE + 0U, // LOCAsmH + 0U, // LOCAsmHE + 0U, // LOCAsmL + 0U, // LOCAsmLE + 0U, // LOCAsmLH + 0U, // LOCAsmM + 0U, // LOCAsmNE + 0U, // LOCAsmNH + 0U, // LOCAsmNHE + 0U, // LOCAsmNL + 0U, // LOCAsmNLE + 0U, // LOCAsmNLH + 0U, // LOCAsmNM + 0U, // LOCAsmNO + 0U, // LOCAsmNP + 0U, // LOCAsmNZ + 0U, // LOCAsmO + 0U, // LOCAsmP + 0U, // LOCAsmZ + 0U, // LOCFH + 104U, // LOCFHAsm + 0U, // LOCFHAsmE + 0U, // LOCFHAsmH + 0U, // LOCFHAsmHE + 0U, // LOCFHAsmL + 0U, // LOCFHAsmLE + 0U, // LOCFHAsmLH + 0U, // LOCFHAsmM + 0U, // LOCFHAsmNE + 0U, // LOCFHAsmNH + 0U, // LOCFHAsmNHE + 0U, // LOCFHAsmNL + 0U, // LOCFHAsmNLE + 0U, // LOCFHAsmNLH + 0U, // LOCFHAsmNM + 0U, // LOCFHAsmNO + 0U, // LOCFHAsmNP + 0U, // LOCFHAsmNZ + 0U, // LOCFHAsmO + 0U, // LOCFHAsmP + 0U, // LOCFHAsmZ + 0U, // LOCFHR + 128U, // LOCFHRAsm + 0U, // LOCFHRAsmE + 0U, // LOCFHRAsmH + 0U, // LOCFHRAsmHE + 0U, // LOCFHRAsmL + 0U, // LOCFHRAsmLE + 0U, // LOCFHRAsmLH + 0U, // LOCFHRAsmM + 0U, // LOCFHRAsmNE + 0U, // LOCFHRAsmNH + 0U, // LOCFHRAsmNHE + 0U, // LOCFHRAsmNL + 0U, // LOCFHRAsmNLE + 0U, // LOCFHRAsmNLH + 0U, // LOCFHRAsmNM + 0U, // LOCFHRAsmNO + 0U, // LOCFHRAsmNP + 0U, // LOCFHRAsmNZ + 0U, // LOCFHRAsmO + 0U, // LOCFHRAsmP + 0U, // LOCFHRAsmZ + 0U, // LOCG + 104U, // LOCGAsm + 0U, // LOCGAsmE + 0U, // LOCGAsmH + 0U, // LOCGAsmHE + 0U, // LOCGAsmL + 0U, // LOCGAsmLE + 0U, // LOCGAsmLH + 0U, // LOCGAsmM + 0U, // LOCGAsmNE + 0U, // LOCGAsmNH + 0U, // LOCGAsmNHE + 0U, // LOCGAsmNL + 0U, // LOCGAsmNLE + 0U, // LOCGAsmNLH + 0U, // LOCGAsmNM + 0U, // LOCGAsmNO + 0U, // LOCGAsmNP + 0U, // LOCGAsmNZ + 0U, // LOCGAsmO + 0U, // LOCGAsmP + 0U, // LOCGAsmZ + 0U, // LOCGHI + 128U, // LOCGHIAsm + 0U, // LOCGHIAsmE + 0U, // LOCGHIAsmH + 0U, // LOCGHIAsmHE + 0U, // LOCGHIAsmL + 0U, // LOCGHIAsmLE + 0U, // LOCGHIAsmLH + 0U, // LOCGHIAsmM + 0U, // LOCGHIAsmNE + 0U, // LOCGHIAsmNH + 0U, // LOCGHIAsmNHE + 0U, // LOCGHIAsmNL + 0U, // LOCGHIAsmNLE + 0U, // LOCGHIAsmNLH + 0U, // LOCGHIAsmNM + 0U, // LOCGHIAsmNO + 0U, // LOCGHIAsmNP + 0U, // LOCGHIAsmNZ + 0U, // LOCGHIAsmO + 0U, // LOCGHIAsmP + 0U, // LOCGHIAsmZ + 0U, // LOCGR + 128U, // LOCGRAsm + 0U, // LOCGRAsmE + 0U, // LOCGRAsmH + 0U, // LOCGRAsmHE + 0U, // LOCGRAsmL + 0U, // LOCGRAsmLE + 0U, // LOCGRAsmLH + 0U, // LOCGRAsmM + 0U, // LOCGRAsmNE + 0U, // LOCGRAsmNH + 0U, // LOCGRAsmNHE + 0U, // LOCGRAsmNL + 0U, // LOCGRAsmNLE + 0U, // LOCGRAsmNLH + 0U, // LOCGRAsmNM + 0U, // LOCGRAsmNO + 0U, // LOCGRAsmNP + 0U, // LOCGRAsmNZ + 0U, // LOCGRAsmO + 0U, // LOCGRAsmP + 0U, // LOCGRAsmZ + 0U, // LOCHHI + 128U, // LOCHHIAsm + 0U, // LOCHHIAsmE + 0U, // LOCHHIAsmH + 0U, // LOCHHIAsmHE + 0U, // LOCHHIAsmL + 0U, // LOCHHIAsmLE + 0U, // LOCHHIAsmLH + 0U, // LOCHHIAsmM + 0U, // LOCHHIAsmNE + 0U, // LOCHHIAsmNH + 0U, // LOCHHIAsmNHE + 0U, // LOCHHIAsmNL + 0U, // LOCHHIAsmNLE + 0U, // LOCHHIAsmNLH + 0U, // LOCHHIAsmNM + 0U, // LOCHHIAsmNO + 0U, // LOCHHIAsmNP + 0U, // LOCHHIAsmNZ + 0U, // LOCHHIAsmO + 0U, // LOCHHIAsmP + 0U, // LOCHHIAsmZ + 0U, // LOCHI + 128U, // LOCHIAsm + 0U, // LOCHIAsmE + 0U, // LOCHIAsmH + 0U, // LOCHIAsmHE + 0U, // LOCHIAsmL + 0U, // LOCHIAsmLE + 0U, // LOCHIAsmLH + 0U, // LOCHIAsmM + 0U, // LOCHIAsmNE + 0U, // LOCHIAsmNH + 0U, // LOCHIAsmNHE + 0U, // LOCHIAsmNL + 0U, // LOCHIAsmNLE + 0U, // LOCHIAsmNLH + 0U, // LOCHIAsmNM + 0U, // LOCHIAsmNO + 0U, // LOCHIAsmNP + 0U, // LOCHIAsmNZ + 0U, // LOCHIAsmO + 0U, // LOCHIAsmP + 0U, // LOCHIAsmZ + 0U, // LOCR + 128U, // LOCRAsm + 0U, // LOCRAsmE + 0U, // LOCRAsmH + 0U, // LOCRAsmHE + 0U, // LOCRAsmL + 0U, // LOCRAsmLE + 0U, // LOCRAsmLH + 0U, // LOCRAsmM + 0U, // LOCRAsmNE + 0U, // LOCRAsmNH + 0U, // LOCRAsmNHE + 0U, // LOCRAsmNL + 0U, // LOCRAsmNLE + 0U, // LOCRAsmNLH + 0U, // LOCRAsmNM + 0U, // LOCRAsmNO + 0U, // LOCRAsmNP + 0U, // LOCRAsmNZ + 0U, // LOCRAsmO + 0U, // LOCRAsmP + 0U, // LOCRAsmZ + 0U, // LPCTL + 24U, // LPD + 0U, // LPDBR + 0U, // LPDFR + 0U, // LPDFR_32 + 24U, // LPDG + 0U, // LPDR + 0U, // LPEBR + 0U, // LPER + 0U, // LPGFR + 0U, // LPGR + 0U, // LPP + 0U, // LPQ + 0U, // LPR + 0U, // LPSW + 0U, // LPSWE + 25200U, // LPTEA + 0U, // LPXBR + 0U, // LPXR + 0U, // LR + 0U, // LRA + 0U, // LRAG + 0U, // LRAY + 0U, // LRDR + 0U, // LRER + 0U, // LRL + 0U, // LRV + 0U, // LRVG + 0U, // LRVGR + 0U, // LRVH + 0U, // LRVR + 0U, // LSCTL + 0U, // LT + 0U, // LTDBR + 0U, // LTDBRCompare + 0U, // LTDR + 0U, // LTDTR + 0U, // LTEBR + 0U, // LTEBRCompare + 0U, // LTER + 0U, // LTG + 0U, // LTGF + 0U, // LTGFR + 0U, // LTGR + 0U, // LTR + 0U, // LTXBR + 0U, // LTXBRCompare + 0U, // LTXR + 0U, // LTXTR + 0U, // LURA + 0U, // LURAG + 0U, // LXD + 0U, // LXDB + 0U, // LXDBR + 0U, // LXDR + 48U, // LXDTR + 0U, // LXE + 0U, // LXEB + 0U, // LXEBR + 0U, // LXER + 0U, // LXR + 0U, // LY + 0U, // LZDR + 0U, // LZER + 0U, // LZRF + 0U, // LZRG + 0U, // LZXR + 0U, // M + 136U, // MAD + 136U, // MADB + 112U, // MADBR + 112U, // MADR + 136U, // MAE + 136U, // MAEB + 112U, // MAEBR + 112U, // MAER + 136U, // MAY + 136U, // MAYH + 112U, // MAYHR + 136U, // MAYL + 112U, // MAYLR + 112U, // MAYR + 0U, // MC + 0U, // MD + 0U, // MDB + 0U, // MDBR + 0U, // MDE + 0U, // MDEB + 0U, // MDEBR + 0U, // MDER + 0U, // MDR + 0U, // MDTR + 512U, // MDTRA + 0U, // ME + 0U, // MEE + 0U, // MEEB + 0U, // MEEBR + 0U, // MEER + 0U, // MER + 0U, // MFY + 0U, // MG + 0U, // MGH + 0U, // MGHI + 0U, // MGRK + 0U, // MH + 0U, // MHI + 0U, // MHY + 0U, // ML + 0U, // MLG + 0U, // MLGR + 0U, // MLR + 0U, // MP + 0U, // MR + 0U, // MS + 0U, // MSC + 0U, // MSCH + 136U, // MSD + 136U, // MSDB + 112U, // MSDBR + 112U, // MSDR + 136U, // MSE + 136U, // MSEB + 112U, // MSEBR + 112U, // MSER + 0U, // MSFI + 0U, // MSG + 0U, // MSGC + 0U, // MSGF + 0U, // MSGFI + 0U, // MSGFR + 0U, // MSGR + 0U, // MSGRKC + 0U, // MSR + 0U, // MSRKC + 0U, // MSTA + 0U, // MSY + 0U, // MVC + 0U, // MVCDK + 0U, // MVCIN + 0U, // MVCK + 0U, // MVCL + 72U, // MVCLE + 72U, // MVCLU + 96U, // MVCOS + 0U, // MVCP + 0U, // MVCS + 0U, // MVCSK + 0U, // MVGHI + 0U, // MVHHI + 0U, // MVHI + 0U, // MVI + 0U, // MVIY + 0U, // MVN + 0U, // MVO + 0U, // MVPG + 0U, // MVST + 0U, // MVZ + 0U, // MXBR + 0U, // MXD + 0U, // MXDB + 0U, // MXDBR + 0U, // MXDR + 0U, // MXR + 0U, // MXTR + 512U, // MXTRA + 144U, // MY + 144U, // MYH + 0U, // MYHR + 144U, // MYL + 0U, // MYLR + 0U, // MYR + 0U, // N + 0U, // NC + 0U, // NG + 0U, // NGR + 0U, // NGRK + 0U, // NI + 0U, // NIAI + 0U, // NIHF + 0U, // NIHH + 0U, // NIHL + 0U, // NILF + 0U, // NILH + 0U, // NILL + 0U, // NIY + 0U, // NR + 0U, // NRK + 0U, // NTSTG + 0U, // NY + 0U, // O + 0U, // OC + 0U, // OG + 0U, // OGR + 0U, // OGRK + 0U, // OI + 0U, // OIHF + 0U, // OIHH + 0U, // OIHL + 0U, // OILF + 0U, // OILH + 0U, // OILL + 0U, // OIY + 0U, // OR + 0U, // ORK + 0U, // OY + 0U, // PACK + 0U, // PALB + 0U, // PC + 0U, // PCC + 0U, // PCKMO + 0U, // PFD + 0U, // PFDRL + 0U, // PFMF + 0U, // PFPO + 0U, // PGIN + 0U, // PGOUT + 0U, // PKA + 0U, // PKU + 41584U, // PLO + 0U, // POPCNT + 48U, // PPA + 0U, // PPNO + 0U, // PR + 0U, // PRNO + 0U, // PT + 0U, // PTF + 0U, // PTFF + 0U, // PTI + 0U, // PTLB + 25200U, // QADTR + 25200U, // QAXTR + 0U, // QCTRI + 0U, // QSI + 0U, // RCHP + 49816U, // RISBG + 49816U, // RISBG32 + 49816U, // RISBGN + 49816U, // RISBHG + 49816U, // RISBLG + 56U, // RLL + 56U, // RLLG + 49816U, // RNSBG + 49816U, // ROSBG + 0U, // RP + 0U, // RRBE + 0U, // RRBM + 25200U, // RRDTR + 25200U, // RRXTR + 0U, // RSCH + 49816U, // RXSBG + 0U, // S + 0U, // SAC + 0U, // SACF + 0U, // SAL + 0U, // SAM24 + 0U, // SAM31 + 0U, // SAM64 + 0U, // SAR + 0U, // SCCTR + 0U, // SCHM + 0U, // SCK + 0U, // SCKC + 0U, // SCKPF + 0U, // SD + 0U, // SDB + 0U, // SDBR + 0U, // SDR + 0U, // SDTR + 512U, // SDTRA + 0U, // SE + 0U, // SEB + 0U, // SEBR + 0U, // SER + 0U, // SFASR + 0U, // SFPC + 0U, // SG + 0U, // SGF + 0U, // SGFR + 0U, // SGH + 0U, // SGR + 0U, // SGRK + 0U, // SH + 0U, // SHHHR + 0U, // SHHLR + 0U, // SHY + 0U, // SIE + 0U, // SIGA + 56U, // SIGP + 0U, // SL + 0U, // SLA + 56U, // SLAG + 56U, // SLAK + 0U, // SLB + 0U, // SLBG + 0U, // SLBGR + 0U, // SLBR + 0U, // SLDA + 0U, // SLDL + 144U, // SLDT + 0U, // SLFI + 0U, // SLG + 0U, // SLGF + 0U, // SLGFI + 0U, // SLGFR + 0U, // SLGR + 0U, // SLGRK + 0U, // SLHHHR + 0U, // SLHHLR + 0U, // SLL + 56U, // SLLG + 56U, // SLLK + 0U, // SLR + 0U, // SLRK + 144U, // SLXT + 0U, // SLY + 0U, // SP + 0U, // SPCTR + 0U, // SPKA + 0U, // SPM + 0U, // SPT + 0U, // SPX + 0U, // SQD + 0U, // SQDB + 0U, // SQDBR + 0U, // SQDR + 0U, // SQE + 0U, // SQEB + 0U, // SQEBR + 0U, // SQER + 0U, // SQXBR + 0U, // SQXR + 0U, // SR + 0U, // SRA + 56U, // SRAG + 56U, // SRAK + 0U, // SRDA + 0U, // SRDL + 144U, // SRDT + 0U, // SRK + 0U, // SRL + 56U, // SRLG + 56U, // SRLK + 0U, // SRNM + 0U, // SRNMB + 0U, // SRNMT + 160U, // SRP + 0U, // SRST + 0U, // SRSTU + 144U, // SRXT + 0U, // SSAIR + 0U, // SSAR + 0U, // SSCH + 48U, // SSKE + 0U, // SSKEOpt + 0U, // SSM + 0U, // ST + 56U, // STAM + 56U, // STAMY + 0U, // STAP + 0U, // STC + 0U, // STCH + 0U, // STCK + 0U, // STCKC + 0U, // STCKE + 0U, // STCKF + 1U, // STCM + 1U, // STCMH + 1U, // STCMY + 0U, // STCPS + 0U, // STCRW + 56U, // STCTG + 56U, // STCTL + 0U, // STCY + 0U, // STD + 0U, // STDY + 0U, // STE + 0U, // STEY + 0U, // STFH + 0U, // STFL + 0U, // STFLE + 0U, // STFPC + 0U, // STG + 0U, // STGRL + 0U, // STGSC + 0U, // STH + 0U, // STHH + 0U, // STHRL + 0U, // STHY + 0U, // STIDP + 56U, // STM + 56U, // STMG + 56U, // STMH + 56U, // STMY + 0U, // STNSM + 0U, // STOC + 128U, // STOCAsm + 0U, // STOCAsmE + 0U, // STOCAsmH + 0U, // STOCAsmHE + 0U, // STOCAsmL + 0U, // STOCAsmLE + 0U, // STOCAsmLH + 0U, // STOCAsmM + 0U, // STOCAsmNE + 0U, // STOCAsmNH + 0U, // STOCAsmNHE + 0U, // STOCAsmNL + 0U, // STOCAsmNLE + 0U, // STOCAsmNLH + 0U, // STOCAsmNM + 0U, // STOCAsmNO + 0U, // STOCAsmNP + 0U, // STOCAsmNZ + 0U, // STOCAsmO + 0U, // STOCAsmP + 0U, // STOCAsmZ + 0U, // STOCFH + 128U, // STOCFHAsm + 0U, // STOCFHAsmE + 0U, // STOCFHAsmH + 0U, // STOCFHAsmHE + 0U, // STOCFHAsmL + 0U, // STOCFHAsmLE + 0U, // STOCFHAsmLH + 0U, // STOCFHAsmM + 0U, // STOCFHAsmNE + 0U, // STOCFHAsmNH + 0U, // STOCFHAsmNHE + 0U, // STOCFHAsmNL + 0U, // STOCFHAsmNLE + 0U, // STOCFHAsmNLH + 0U, // STOCFHAsmNM + 0U, // STOCFHAsmNO + 0U, // STOCFHAsmNP + 0U, // STOCFHAsmNZ + 0U, // STOCFHAsmO + 0U, // STOCFHAsmP + 0U, // STOCFHAsmZ + 0U, // STOCG + 128U, // STOCGAsm + 0U, // STOCGAsmE + 0U, // STOCGAsmH + 0U, // STOCGAsmHE + 0U, // STOCGAsmL + 0U, // STOCGAsmLE + 0U, // STOCGAsmLH + 0U, // STOCGAsmM + 0U, // STOCGAsmNE + 0U, // STOCGAsmNH + 0U, // STOCGAsmNHE + 0U, // STOCGAsmNL + 0U, // STOCGAsmNLE + 0U, // STOCGAsmNLH + 0U, // STOCGAsmNM + 0U, // STOCGAsmNO + 0U, // STOCGAsmNP + 0U, // STOCGAsmNZ + 0U, // STOCGAsmO + 0U, // STOCGAsmP + 0U, // STOCGAsmZ + 0U, // STOSM + 0U, // STPQ + 0U, // STPT + 0U, // STPX + 0U, // STRAG + 0U, // STRL + 0U, // STRV + 0U, // STRVG + 0U, // STRVH + 0U, // STSCH + 0U, // STSI + 0U, // STURA + 0U, // STURG + 0U, // STY + 0U, // SU + 0U, // SUR + 0U, // SVC + 0U, // SW + 0U, // SWR + 0U, // SXBR + 0U, // SXR + 0U, // SXTR + 512U, // SXTRA + 0U, // SY + 0U, // TABORT + 0U, // TAM + 0U, // TAR + 0U, // TB + 41U, // TBDR + 41U, // TBEDR + 0U, // TBEGIN + 0U, // TBEGINC + 0U, // TCDB + 0U, // TCEB + 0U, // TCXB + 0U, // TDCDT + 0U, // TDCET + 0U, // TDCXT + 0U, // TDGDT + 0U, // TDGET + 0U, // TDGXT + 0U, // TEND + 0U, // THDER + 0U, // THDR + 0U, // TM + 0U, // TMHH + 0U, // TMHL + 0U, // TMLH + 0U, // TMLL + 0U, // TMY + 0U, // TP + 0U, // TPI + 0U, // TPROT + 0U, // TR + 56U, // TRACE + 56U, // TRACG + 0U, // TRAP2 + 0U, // TRAP4 + 0U, // TRE + 104U, // TROO + 0U, // TROOOpt + 104U, // TROT + 0U, // TROTOpt + 0U, // TRT + 0U, // TRTE + 0U, // TRTEOpt + 104U, // TRTO + 0U, // TRTOOpt + 0U, // TRTR + 0U, // TRTRE + 0U, // TRTREOpt + 104U, // TRTT + 0U, // TRTTOpt + 0U, // TS + 0U, // TSCH + 0U, // UNPK + 0U, // UNPKA + 0U, // UNPKU + 0U, // UPT + 512U, // VA + 0U, // VAB + 57856U, // VAC + 512U, // VACC + 0U, // VACCB + 57856U, // VACCC + 57856U, // VACCCQ + 0U, // VACCF + 0U, // VACCG + 0U, // VACCH + 0U, // VACCQ + 57856U, // VACQ + 0U, // VAF + 0U, // VAG + 0U, // VAH + 512U, // VAP + 0U, // VAQ + 512U, // VAVG + 0U, // VAVGB + 0U, // VAVGF + 0U, // VAVGG + 0U, // VAVGH + 512U, // VAVGL + 0U, // VAVGLB + 0U, // VAVGLF + 0U, // VAVGLG + 0U, // VAVGLH + 0U, // VBPERM + 560U, // VCDG + 560U, // VCDGB + 560U, // VCDLG + 560U, // VCDLGB + 512U, // VCEQ + 0U, // VCEQB + 0U, // VCEQBS + 0U, // VCEQF + 0U, // VCEQFS + 0U, // VCEQG + 0U, // VCEQGS + 0U, // VCEQH + 0U, // VCEQHS + 560U, // VCGD + 560U, // VCGDB + 512U, // VCH + 0U, // VCHB + 0U, // VCHBS + 0U, // VCHF + 0U, // VCHFS + 0U, // VCHG + 0U, // VCHGS + 0U, // VCHH + 0U, // VCHHS + 512U, // VCHL + 0U, // VCHLB + 0U, // VCHLBS + 0U, // VCHLF + 0U, // VCHLFS + 0U, // VCHLG + 0U, // VCHLGS + 0U, // VCHLH + 0U, // VCHLHS + 0U, // VCKSM + 560U, // VCLGD + 560U, // VCLGDB + 48U, // VCLZ + 0U, // VCLZB + 0U, // VCLZF + 0U, // VCLZG + 0U, // VCLZH + 48U, // VCP + 48U, // VCTZ + 0U, // VCTZB + 0U, // VCTZF + 0U, // VCTZG + 0U, // VCTZH + 48U, // VCVB + 48U, // VCVBG + 10408U, // VCVD + 10408U, // VCVDG + 512U, // VDP + 48U, // VEC + 0U, // VECB + 0U, // VECF + 0U, // VECG + 0U, // VECH + 48U, // VECL + 0U, // VECLB + 0U, // VECLF + 0U, // VECLG + 0U, // VECLH + 49776U, // VERIM + 49776U, // VERIMB + 49776U, // VERIMF + 49776U, // VERIMG + 49776U, // VERIMH + 25144U, // VERLL + 56U, // VERLLB + 56U, // VERLLF + 56U, // VERLLG + 56U, // VERLLH + 512U, // VERLLV + 0U, // VERLLVB + 0U, // VERLLVF + 0U, // VERLLVG + 0U, // VERLLVH + 25144U, // VESL + 56U, // VESLB + 56U, // VESLF + 56U, // VESLG + 56U, // VESLH + 512U, // VESLV + 0U, // VESLVB + 0U, // VESLVF + 0U, // VESLVG + 0U, // VESLVH + 25144U, // VESRA + 56U, // VESRAB + 56U, // VESRAF + 56U, // VESRAG + 56U, // VESRAH + 512U, // VESRAV + 0U, // VESRAVB + 0U, // VESRAVF + 0U, // VESRAVG + 0U, // VESRAVH + 25144U, // VESRL + 56U, // VESRLB + 56U, // VESRLF + 56U, // VESRLG + 56U, // VESRLH + 512U, // VESRLV + 0U, // VESRLVB + 0U, // VESRLVF + 0U, // VESRLVG + 0U, // VESRLVH + 512U, // VFA + 0U, // VFADB + 512U, // VFAE + 512U, // VFAEB + 512U, // VFAEBS + 512U, // VFAEF + 512U, // VFAEFS + 512U, // VFAEH + 512U, // VFAEHS + 512U, // VFAEZB + 512U, // VFAEZBS + 512U, // VFAEZF + 512U, // VFAEZFS + 512U, // VFAEZH + 512U, // VFAEZHS + 0U, // VFASB + 512U, // VFCE + 0U, // VFCEDB + 0U, // VFCEDBS + 0U, // VFCESB + 0U, // VFCESBS + 512U, // VFCH + 0U, // VFCHDB + 0U, // VFCHDBS + 512U, // VFCHE + 0U, // VFCHEDB + 0U, // VFCHEDBS + 0U, // VFCHESB + 0U, // VFCHESBS + 0U, // VFCHSB + 0U, // VFCHSBS + 512U, // VFD + 0U, // VFDDB + 0U, // VFDSB + 512U, // VFEE + 512U, // VFEEB + 0U, // VFEEBS + 512U, // VFEEF + 0U, // VFEEFS + 512U, // VFEEH + 0U, // VFEEHS + 0U, // VFEEZB + 0U, // VFEEZBS + 0U, // VFEEZF + 0U, // VFEEZFS + 0U, // VFEEZH + 0U, // VFEEZHS + 512U, // VFENE + 512U, // VFENEB + 0U, // VFENEBS + 512U, // VFENEF + 0U, // VFENEFS + 512U, // VFENEH + 0U, // VFENEHS + 0U, // VFENEZB + 0U, // VFENEZBS + 0U, // VFENEZF + 0U, // VFENEZFS + 0U, // VFENEZH + 0U, // VFENEZHS + 560U, // VFI + 560U, // VFIDB + 560U, // VFISB + 0U, // VFKEDB + 0U, // VFKEDBS + 0U, // VFKESB + 0U, // VFKESBS + 0U, // VFKHDB + 0U, // VFKHDBS + 0U, // VFKHEDB + 0U, // VFKHEDBS + 0U, // VFKHESB + 0U, // VFKHESBS + 0U, // VFKHSB + 0U, // VFKHSBS + 0U, // VFLCDB + 0U, // VFLCSB + 560U, // VFLL + 0U, // VFLLS + 0U, // VFLNDB + 0U, // VFLNSB + 0U, // VFLPDB + 0U, // VFLPSB + 560U, // VFLR + 560U, // VFLRD + 512U, // VFM + 57856U, // VFMA + 57856U, // VFMADB + 57856U, // VFMASB + 512U, // VFMAX + 512U, // VFMAXDB + 512U, // VFMAXSB + 0U, // VFMDB + 512U, // VFMIN + 512U, // VFMINDB + 512U, // VFMINSB + 57856U, // VFMS + 0U, // VFMSB + 57856U, // VFMSDB + 57856U, // VFMSSB + 57856U, // VFNMA + 57856U, // VFNMADB + 57856U, // VFNMASB + 57856U, // VFNMS + 57856U, // VFNMSDB + 57856U, // VFNMSSB + 560U, // VFPSO + 48U, // VFPSODB + 48U, // VFPSOSB + 512U, // VFS + 0U, // VFSDB + 560U, // VFSQ + 0U, // VFSQDB + 0U, // VFSQSB + 0U, // VFSSB + 688U, // VFTCI + 176U, // VFTCIDB + 176U, // VFTCISB + 0U, // VGBM + 3U, // VGEF + 4U, // VGEG + 512U, // VGFM + 57856U, // VGFMA + 57856U, // VGFMAB + 57856U, // VGFMAF + 57856U, // VGFMAG + 57856U, // VGFMAH + 0U, // VGFMB + 0U, // VGFMF + 0U, // VGFMG + 0U, // VGFMH + 36U, // VGM + 44U, // VGMB + 44U, // VGMF + 44U, // VGMG + 44U, // VGMH + 560U, // VISTR + 48U, // VISTRB + 0U, // VISTRBS + 48U, // VISTRF + 0U, // VISTRFS + 48U, // VISTRH + 0U, // VISTRHS + 0U, // VL + 104U, // VLBB + 48U, // VLC + 0U, // VLCB + 0U, // VLCF + 0U, // VLCG + 0U, // VLCH + 560U, // VLDE + 0U, // VLDEB + 160U, // VLEB + 560U, // VLED + 560U, // VLEDB + 184U, // VLEF + 192U, // VLEG + 200U, // VLEH + 128U, // VLEIB + 208U, // VLEIF + 216U, // VLEIG + 224U, // VLEIH + 25144U, // VLGV + 56U, // VLGVB + 56U, // VLGVF + 56U, // VLGVG + 56U, // VLGVH + 48U, // VLIP + 56U, // VLL + 104U, // VLLEZ + 0U, // VLLEZB + 0U, // VLLEZF + 0U, // VLLEZG + 0U, // VLLEZH + 0U, // VLLEZLF + 56U, // VLM + 48U, // VLP + 0U, // VLPB + 0U, // VLPF + 0U, // VLPG + 0U, // VLPH + 0U, // VLR + 104U, // VLREP + 0U, // VLREPB + 0U, // VLREPF + 0U, // VLREPG + 0U, // VLREPH + 152U, // VLRL + 56U, // VLRLR + 16920U, // VLVG + 24U, // VLVGB + 24U, // VLVGF + 24U, // VLVGG + 24U, // VLVGH + 0U, // VLVGP + 57856U, // VMAE + 57856U, // VMAEB + 57856U, // VMAEF + 57856U, // VMAEH + 57856U, // VMAH + 57856U, // VMAHB + 57856U, // VMAHF + 57856U, // VMAHH + 57856U, // VMAL + 57856U, // VMALB + 57856U, // VMALE + 57856U, // VMALEB + 57856U, // VMALEF + 57856U, // VMALEH + 57856U, // VMALF + 57856U, // VMALH + 57856U, // VMALHB + 57856U, // VMALHF + 57856U, // VMALHH + 57856U, // VMALHW + 57856U, // VMALO + 57856U, // VMALOB + 57856U, // VMALOF + 57856U, // VMALOH + 57856U, // VMAO + 57856U, // VMAOB + 57856U, // VMAOF + 57856U, // VMAOH + 512U, // VME + 0U, // VMEB + 0U, // VMEF + 0U, // VMEH + 512U, // VMH + 0U, // VMHB + 0U, // VMHF + 0U, // VMHH + 512U, // VML + 0U, // VMLB + 512U, // VMLE + 0U, // VMLEB + 0U, // VMLEF + 0U, // VMLEH + 0U, // VMLF + 512U, // VMLH + 0U, // VMLHB + 0U, // VMLHF + 0U, // VMLHH + 0U, // VMLHW + 512U, // VMLO + 0U, // VMLOB + 0U, // VMLOF + 0U, // VMLOH + 512U, // VMN + 0U, // VMNB + 0U, // VMNF + 0U, // VMNG + 0U, // VMNH + 512U, // VMNL + 0U, // VMNLB + 0U, // VMNLF + 0U, // VMNLG + 0U, // VMNLH + 512U, // VMO + 0U, // VMOB + 0U, // VMOF + 0U, // VMOH + 512U, // VMP + 512U, // VMRH + 0U, // VMRHB + 0U, // VMRHF + 0U, // VMRHG + 0U, // VMRHH + 512U, // VMRL + 0U, // VMRLB + 0U, // VMRLF + 0U, // VMRLG + 0U, // VMRLH + 57856U, // VMSL + 57856U, // VMSLG + 512U, // VMSP + 512U, // VMX + 0U, // VMXB + 0U, // VMXF + 0U, // VMXG + 0U, // VMXH + 512U, // VMXL + 0U, // VMXLB + 0U, // VMXLF + 0U, // VMXLG + 0U, // VMXLH + 0U, // VN + 0U, // VNC + 0U, // VNN + 0U, // VNO + 0U, // VNX + 0U, // VO + 0U, // VOC + 0U, // VONE + 512U, // VPDI + 57856U, // VPERM + 512U, // VPK + 0U, // VPKF + 0U, // VPKG + 0U, // VPKH + 512U, // VPKLS + 0U, // VPKLSF + 0U, // VPKLSFS + 0U, // VPKLSG + 0U, // VPKLSGS + 0U, // VPKLSH + 0U, // VPKLSHS + 512U, // VPKS + 0U, // VPKSF + 0U, // VPKSFS + 0U, // VPKSG + 0U, // VPKSGS + 0U, // VPKSH + 0U, // VPKSHS + 152U, // VPKZ + 48U, // VPOPCT + 0U, // VPOPCTB + 0U, // VPOPCTF + 0U, // VPOPCTG + 0U, // VPOPCTH + 4264U, // VPSOP + 744U, // VREP + 232U, // VREPB + 232U, // VREPF + 232U, // VREPG + 232U, // VREPH + 48U, // VREPI + 0U, // VREPIB + 0U, // VREPIF + 0U, // VREPIG + 0U, // VREPIH + 512U, // VRP + 512U, // VS + 0U, // VSB + 57856U, // VSBCBI + 57856U, // VSBCBIQ + 57856U, // VSBI + 57856U, // VSBIQ + 512U, // VSCBI + 0U, // VSCBIB + 0U, // VSCBIF + 0U, // VSCBIG + 0U, // VSCBIH + 0U, // VSCBIQ + 4U, // VSCEF + 4U, // VSCEG + 512U, // VSDP + 48U, // VSEG + 0U, // VSEGB + 0U, // VSEGF + 0U, // VSEGH + 57856U, // VSEL + 0U, // VSF + 0U, // VSG + 0U, // VSH + 0U, // VSL + 0U, // VSLB + 512U, // VSLDB + 512U, // VSP + 0U, // VSQ + 0U, // VSRA + 0U, // VSRAB + 0U, // VSRL + 0U, // VSRLB + 4264U, // VSRP + 0U, // VST + 104U, // VSTEB + 240U, // VSTEF + 248U, // VSTEG + 256U, // VSTEH + 56U, // VSTL + 56U, // VSTM + 57856U, // VSTRC + 57856U, // VSTRCB + 57856U, // VSTRCBS + 57856U, // VSTRCF + 57856U, // VSTRCFS + 57856U, // VSTRCH + 57856U, // VSTRCHS + 57856U, // VSTRCZB + 57856U, // VSTRCZBS + 57856U, // VSTRCZF + 57856U, // VSTRCZFS + 57856U, // VSTRCZH + 57856U, // VSTRCZHS + 152U, // VSTRL + 56U, // VSTRLR + 512U, // VSUM + 0U, // VSUMB + 512U, // VSUMG + 0U, // VSUMGF + 0U, // VSUMGH + 0U, // VSUMH + 512U, // VSUMQ + 0U, // VSUMQF + 0U, // VSUMQG + 0U, // VTM + 0U, // VTP + 48U, // VUPH + 0U, // VUPHB + 0U, // VUPHF + 0U, // VUPHH + 152U, // VUPKZ + 48U, // VUPL + 0U, // VUPLB + 0U, // VUPLF + 48U, // VUPLH + 0U, // VUPLHB + 0U, // VUPLHF + 0U, // VUPLHH + 0U, // VUPLHW + 48U, // VUPLL + 0U, // VUPLLB + 0U, // VUPLLF + 0U, // VUPLLH + 0U, // VX + 0U, // VZERO + 560U, // WCDGB + 560U, // WCDLGB + 560U, // WCGDB + 560U, // WCLGDB + 0U, // WFADB + 0U, // WFASB + 0U, // WFAXB + 560U, // WFC + 0U, // WFCDB + 0U, // WFCEDB + 0U, // WFCEDBS + 0U, // WFCESB + 0U, // WFCESBS + 0U, // WFCEXB + 0U, // WFCEXBS + 0U, // WFCHDB + 0U, // WFCHDBS + 0U, // WFCHEDB + 0U, // WFCHEDBS + 0U, // WFCHESB + 0U, // WFCHESBS + 0U, // WFCHEXB + 0U, // WFCHEXBS + 0U, // WFCHSB + 0U, // WFCHSBS + 0U, // WFCHXB + 0U, // WFCHXBS + 0U, // WFCSB + 0U, // WFCXB + 0U, // WFDDB + 0U, // WFDSB + 0U, // WFDXB + 560U, // WFIDB + 560U, // WFISB + 560U, // WFIXB + 560U, // WFK + 0U, // WFKDB + 0U, // WFKEDB + 0U, // WFKEDBS + 0U, // WFKESB + 0U, // WFKESBS + 0U, // WFKEXB + 0U, // WFKEXBS + 0U, // WFKHDB + 0U, // WFKHDBS + 0U, // WFKHEDB + 0U, // WFKHEDBS + 0U, // WFKHESB + 0U, // WFKHESBS + 0U, // WFKHEXB + 0U, // WFKHEXBS + 0U, // WFKHSB + 0U, // WFKHSBS + 0U, // WFKHXB + 0U, // WFKHXBS + 0U, // WFKSB + 0U, // WFKXB + 0U, // WFLCDB + 0U, // WFLCSB + 0U, // WFLCXB + 0U, // WFLLD + 0U, // WFLLS + 0U, // WFLNDB + 0U, // WFLNSB + 0U, // WFLNXB + 0U, // WFLPDB + 0U, // WFLPSB + 0U, // WFLPXB + 560U, // WFLRD + 560U, // WFLRX + 57856U, // WFMADB + 57856U, // WFMASB + 57856U, // WFMAXB + 512U, // WFMAXDB + 512U, // WFMAXSB + 512U, // WFMAXXB + 0U, // WFMDB + 512U, // WFMINDB + 512U, // WFMINSB + 512U, // WFMINXB + 0U, // WFMSB + 57856U, // WFMSDB + 57856U, // WFMSSB + 57856U, // WFMSXB + 0U, // WFMXB + 57856U, // WFNMADB + 57856U, // WFNMASB + 57856U, // WFNMAXB + 57856U, // WFNMSDB + 57856U, // WFNMSSB + 57856U, // WFNMSXB + 48U, // WFPSODB + 48U, // WFPSOSB + 48U, // WFPSOXB + 0U, // WFSDB + 0U, // WFSQDB + 0U, // WFSQSB + 0U, // WFSQXB + 0U, // WFSSB + 0U, // WFSXB + 176U, // WFTCIDB + 176U, // WFTCISB + 176U, // WFTCIXB + 0U, // WLDEB + 560U, // WLEDB + 0U, // X + 0U, // XC + 0U, // XG + 0U, // XGR + 0U, // XGRK + 0U, // XI + 0U, // XIHF + 0U, // XILF + 0U, // XIY + 0U, // XR + 0U, // XRK + 0U, // XSCH + 0U, // XY + 0U, // ZAP }; static const uint8_t OpInfo2[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 0U, // DBG_VALUE - 0U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 0U, // BUNDLE - 0U, // LIFETIME_START - 0U, // LIFETIME_END - 0U, // STACKMAP - 0U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 0U, // PATCHABLE_FUNCTION_ENTER - 0U, // PATCHABLE_RET - 0U, // PATCHABLE_FUNCTION_EXIT - 0U, // PATCHABLE_TAIL_CALL - 0U, // PATCHABLE_EVENT_CALL - 0U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDE - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SSUBO - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_BSWAP - 0U, // G_ADDRSPACE_CAST - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 0U, // ADJDYNALLOC - 0U, // AEXT128 - 0U, // AFIMux - 0U, // AHIMux - 0U, // AHIMuxK - 0U, // ATOMIC_CMP_SWAPW - 0U, // ATOMIC_LOADW_AFI - 0U, // ATOMIC_LOADW_AR - 0U, // ATOMIC_LOADW_MAX - 0U, // ATOMIC_LOADW_MIN - 0U, // ATOMIC_LOADW_NILH - 0U, // ATOMIC_LOADW_NILHi - 0U, // ATOMIC_LOADW_NR - 0U, // ATOMIC_LOADW_NRi - 0U, // ATOMIC_LOADW_OILH - 0U, // ATOMIC_LOADW_OR - 0U, // ATOMIC_LOADW_SR - 0U, // ATOMIC_LOADW_UMAX - 0U, // ATOMIC_LOADW_UMIN - 0U, // ATOMIC_LOADW_XILF - 0U, // ATOMIC_LOADW_XR - 0U, // ATOMIC_LOAD_AFI - 0U, // ATOMIC_LOAD_AGFI - 0U, // ATOMIC_LOAD_AGHI - 0U, // ATOMIC_LOAD_AGR - 0U, // ATOMIC_LOAD_AHI - 0U, // ATOMIC_LOAD_AR - 0U, // ATOMIC_LOAD_MAX_32 - 0U, // ATOMIC_LOAD_MAX_64 - 0U, // ATOMIC_LOAD_MIN_32 - 0U, // ATOMIC_LOAD_MIN_64 - 0U, // ATOMIC_LOAD_NGR - 0U, // ATOMIC_LOAD_NGRi - 0U, // ATOMIC_LOAD_NIHF64 - 0U, // ATOMIC_LOAD_NIHF64i - 0U, // ATOMIC_LOAD_NIHH64 - 0U, // ATOMIC_LOAD_NIHH64i - 0U, // ATOMIC_LOAD_NIHL64 - 0U, // ATOMIC_LOAD_NIHL64i - 0U, // ATOMIC_LOAD_NILF - 0U, // ATOMIC_LOAD_NILF64 - 0U, // ATOMIC_LOAD_NILF64i - 0U, // ATOMIC_LOAD_NILFi - 0U, // ATOMIC_LOAD_NILH - 0U, // ATOMIC_LOAD_NILH64 - 0U, // ATOMIC_LOAD_NILH64i - 0U, // ATOMIC_LOAD_NILHi - 0U, // ATOMIC_LOAD_NILL - 0U, // ATOMIC_LOAD_NILL64 - 0U, // ATOMIC_LOAD_NILL64i - 0U, // ATOMIC_LOAD_NILLi - 0U, // ATOMIC_LOAD_NR - 0U, // ATOMIC_LOAD_NRi - 0U, // ATOMIC_LOAD_OGR - 0U, // ATOMIC_LOAD_OIHF64 - 0U, // ATOMIC_LOAD_OIHH64 - 0U, // ATOMIC_LOAD_OIHL64 - 0U, // ATOMIC_LOAD_OILF - 0U, // ATOMIC_LOAD_OILF64 - 0U, // ATOMIC_LOAD_OILH - 0U, // ATOMIC_LOAD_OILH64 - 0U, // ATOMIC_LOAD_OILL - 0U, // ATOMIC_LOAD_OILL64 - 0U, // ATOMIC_LOAD_OR - 0U, // ATOMIC_LOAD_SGR - 0U, // ATOMIC_LOAD_SR - 0U, // ATOMIC_LOAD_UMAX_32 - 0U, // ATOMIC_LOAD_UMAX_64 - 0U, // ATOMIC_LOAD_UMIN_32 - 0U, // ATOMIC_LOAD_UMIN_64 - 0U, // ATOMIC_LOAD_XGR - 0U, // ATOMIC_LOAD_XIHF64 - 0U, // ATOMIC_LOAD_XILF - 0U, // ATOMIC_LOAD_XILF64 - 0U, // ATOMIC_LOAD_XR - 0U, // ATOMIC_SWAPW - 0U, // ATOMIC_SWAP_32 - 0U, // ATOMIC_SWAP_64 - 0U, // CFIMux - 0U, // CGIBCall - 0U, // CGIBReturn - 0U, // CGRBCall - 0U, // CGRBReturn - 0U, // CHIMux - 0U, // CIBCall - 0U, // CIBReturn - 0U, // CLCLoop - 0U, // CLCSequence - 0U, // CLFIMux - 0U, // CLGIBCall - 0U, // CLGIBReturn - 0U, // CLGRBCall - 0U, // CLGRBReturn - 0U, // CLIBCall - 0U, // CLIBReturn - 0U, // CLMux - 0U, // CLRBCall - 0U, // CLRBReturn - 0U, // CLSTLoop - 0U, // CMux - 0U, // CRBCall - 0U, // CRBReturn - 0U, // CallBASR - 0U, // CallBCR - 0U, // CallBR - 0U, // CallBRASL - 0U, // CallBRCL - 0U, // CallJG - 0U, // CondReturn - 0U, // CondStore16 - 0U, // CondStore16Inv - 0U, // CondStore16Mux - 0U, // CondStore16MuxInv - 0U, // CondStore32 - 0U, // CondStore32Inv - 0U, // CondStore32Mux - 0U, // CondStore32MuxInv - 0U, // CondStore64 - 0U, // CondStore64Inv - 0U, // CondStore8 - 0U, // CondStore8Inv - 0U, // CondStore8Mux - 0U, // CondStore8MuxInv - 0U, // CondStoreF32 - 0U, // CondStoreF32Inv - 0U, // CondStoreF64 - 0U, // CondStoreF64Inv - 0U, // CondTrap - 0U, // GOT - 0U, // IIFMux - 0U, // IIHF64 - 0U, // IIHH64 - 0U, // IIHL64 - 0U, // IIHMux - 0U, // IILF64 - 0U, // IILH64 - 0U, // IILL64 - 0U, // IILMux - 0U, // L128 - 0U, // LBMux - 0U, // LEFR - 0U, // LFER - 0U, // LHIMux - 0U, // LHMux - 0U, // LLCMux - 0U, // LLCRMux - 0U, // LLHMux - 0U, // LLHRMux - 0U, // LMux - 0U, // LOCHIMux - 0U, // LOCMux - 0U, // LOCRMux - 0U, // LRMux - 0U, // LTDBRCompare_VecPseudo - 0U, // LTEBRCompare_VecPseudo - 0U, // LTXBRCompare_VecPseudo - 0U, // LX - 0U, // MVCLoop - 0U, // MVCSequence - 0U, // MVSTLoop - 0U, // MemBarrier - 0U, // NCLoop - 0U, // NCSequence - 0U, // NIFMux - 0U, // NIHF64 - 0U, // NIHH64 - 0U, // NIHL64 - 0U, // NIHMux - 0U, // NILF64 - 0U, // NILH64 - 0U, // NILL64 - 0U, // NILMux - 0U, // OCLoop - 0U, // OCSequence - 0U, // OIFMux - 0U, // OIHF64 - 0U, // OIHH64 - 0U, // OIHL64 - 0U, // OIHMux - 0U, // OILF64 - 0U, // OILH64 - 0U, // OILL64 - 0U, // OILMux - 0U, // PAIR128 - 0U, // RISBHH - 0U, // RISBHL - 0U, // RISBLH - 0U, // RISBLL - 0U, // RISBMux - 0U, // Return - 0U, // SRSTLoop - 0U, // ST128 - 0U, // STCMux - 0U, // STHMux - 0U, // STMux - 0U, // STOCMux - 0U, // STX - 0U, // Select32 - 0U, // Select64 - 0U, // SelectF128 - 0U, // SelectF32 - 0U, // SelectF64 - 0U, // SelectVR128 - 0U, // SelectVR32 - 0U, // SelectVR64 - 0U, // Serialize - 0U, // TBEGIN_nofloat - 0U, // TLS_GDCALL - 0U, // TLS_LDCALL - 0U, // TMHH64 - 0U, // TMHL64 - 0U, // TMHMux - 0U, // TMLH64 - 0U, // TMLL64 - 0U, // TMLMux - 0U, // Trap - 0U, // VL32 - 0U, // VL64 - 0U, // VLR32 - 0U, // VLR64 - 0U, // VLVGP32 - 0U, // VST32 - 0U, // VST64 - 0U, // XCLoop - 0U, // XCSequence - 0U, // XIFMux - 0U, // XIHF64 - 0U, // XILF64 - 0U, // ZEXT128 - 0U, // A - 0U, // AD - 0U, // ADB - 0U, // ADBR - 0U, // ADR - 0U, // ADTR - 0U, // ADTRA - 0U, // AE - 0U, // AEB - 0U, // AEBR - 0U, // AER - 0U, // AFI - 0U, // AG - 0U, // AGF - 0U, // AGFI - 0U, // AGFR - 0U, // AGH - 0U, // AGHI - 0U, // AGHIK - 0U, // AGR - 0U, // AGRK - 0U, // AGSI - 0U, // AH - 0U, // AHHHR - 0U, // AHHLR - 0U, // AHI - 0U, // AHIK - 0U, // AHY - 0U, // AIH - 0U, // AL - 0U, // ALC - 0U, // ALCG - 0U, // ALCGR - 0U, // ALCR - 0U, // ALFI - 0U, // ALG - 0U, // ALGF - 0U, // ALGFI - 0U, // ALGFR - 0U, // ALGHSIK - 0U, // ALGR - 0U, // ALGRK - 0U, // ALGSI - 0U, // ALHHHR - 0U, // ALHHLR - 0U, // ALHSIK - 0U, // ALR - 0U, // ALRK - 0U, // ALSI - 0U, // ALSIH - 0U, // ALSIHN - 0U, // ALY - 0U, // AP - 0U, // AR - 0U, // ARK - 0U, // ASI - 0U, // AU - 0U, // AUR - 0U, // AW - 0U, // AWR - 0U, // AXBR - 0U, // AXR - 0U, // AXTR - 0U, // AXTRA - 0U, // AY - 0U, // B - 0U, // BAKR - 0U, // BAL - 0U, // BALR - 0U, // BAS - 0U, // BASR - 0U, // BASSM - 0U, // BAsmE - 0U, // BAsmH - 0U, // BAsmHE - 0U, // BAsmL - 0U, // BAsmLE - 0U, // BAsmLH - 0U, // BAsmM - 0U, // BAsmNE - 0U, // BAsmNH - 0U, // BAsmNHE - 0U, // BAsmNL - 0U, // BAsmNLE - 0U, // BAsmNLH - 0U, // BAsmNM - 0U, // BAsmNO - 0U, // BAsmNP - 0U, // BAsmNZ - 0U, // BAsmO - 0U, // BAsmP - 0U, // BAsmZ - 0U, // BC - 0U, // BCAsm - 0U, // BCR - 0U, // BCRAsm - 0U, // BCT - 0U, // BCTG - 0U, // BCTGR - 0U, // BCTR - 0U, // BI - 0U, // BIAsmE - 0U, // BIAsmH - 0U, // BIAsmHE - 0U, // BIAsmL - 0U, // BIAsmLE - 0U, // BIAsmLH - 0U, // BIAsmM - 0U, // BIAsmNE - 0U, // BIAsmNH - 0U, // BIAsmNHE - 0U, // BIAsmNL - 0U, // BIAsmNLE - 0U, // BIAsmNLH - 0U, // BIAsmNM - 0U, // BIAsmNO - 0U, // BIAsmNP - 0U, // BIAsmNZ - 0U, // BIAsmO - 0U, // BIAsmP - 0U, // BIAsmZ - 0U, // BIC - 0U, // BICAsm - 0U, // BPP - 0U, // BPRP - 0U, // BR - 0U, // BRAS - 0U, // BRASL - 0U, // BRAsmE - 0U, // BRAsmH - 0U, // BRAsmHE - 0U, // BRAsmL - 0U, // BRAsmLE - 0U, // BRAsmLH - 0U, // BRAsmM - 0U, // BRAsmNE - 0U, // BRAsmNH - 0U, // BRAsmNHE - 0U, // BRAsmNL - 0U, // BRAsmNLE - 0U, // BRAsmNLH - 0U, // BRAsmNM - 0U, // BRAsmNO - 0U, // BRAsmNP - 0U, // BRAsmNZ - 0U, // BRAsmO - 0U, // BRAsmP - 0U, // BRAsmZ - 0U, // BRC - 0U, // BRCAsm - 0U, // BRCL - 0U, // BRCLAsm - 0U, // BRCT - 0U, // BRCTG - 0U, // BRCTH - 0U, // BRXH - 0U, // BRXHG - 0U, // BRXLE - 0U, // BRXLG - 0U, // BSA - 0U, // BSG - 0U, // BSM - 0U, // BXH - 0U, // BXHG - 0U, // BXLE - 0U, // BXLEG - 0U, // C - 0U, // CD - 0U, // CDB - 0U, // CDBR - 0U, // CDFBR - 0U, // CDFBRA - 0U, // CDFR - 0U, // CDFTR - 0U, // CDGBR - 0U, // CDGBRA - 0U, // CDGR - 0U, // CDGTR - 0U, // CDGTRA - 0U, // CDLFBR - 0U, // CDLFTR - 0U, // CDLGBR - 0U, // CDLGTR - 0U, // CDPT - 0U, // CDR - 0U, // CDS - 0U, // CDSG - 0U, // CDSTR - 0U, // CDSY - 0U, // CDTR - 0U, // CDUTR - 0U, // CDZT - 0U, // CE - 0U, // CEB - 0U, // CEBR - 0U, // CEDTR - 0U, // CEFBR - 0U, // CEFBRA - 0U, // CEFR - 0U, // CEGBR - 0U, // CEGBRA - 0U, // CEGR - 0U, // CELFBR - 0U, // CELGBR - 0U, // CER - 0U, // CEXTR - 0U, // CFC - 0U, // CFDBR - 0U, // CFDBRA - 0U, // CFDR - 0U, // CFDTR - 0U, // CFEBR - 0U, // CFEBRA - 0U, // CFER - 0U, // CFI - 0U, // CFXBR - 0U, // CFXBRA - 0U, // CFXR - 0U, // CFXTR - 0U, // CG - 0U, // CGDBR - 0U, // CGDBRA - 0U, // CGDR - 0U, // CGDTR - 0U, // CGDTRA - 0U, // CGEBR - 0U, // CGEBRA - 0U, // CGER - 0U, // CGF - 0U, // CGFI - 0U, // CGFR - 0U, // CGFRL - 0U, // CGH - 0U, // CGHI - 0U, // CGHRL - 0U, // CGHSI - 0U, // CGIB - 0U, // CGIBAsm - 0U, // CGIBAsmE - 0U, // CGIBAsmH - 0U, // CGIBAsmHE - 0U, // CGIBAsmL - 0U, // CGIBAsmLE - 0U, // CGIBAsmLH - 0U, // CGIBAsmNE - 0U, // CGIBAsmNH - 0U, // CGIBAsmNHE - 0U, // CGIBAsmNL - 0U, // CGIBAsmNLE - 0U, // CGIBAsmNLH - 0U, // CGIJ - 0U, // CGIJAsm - 0U, // CGIJAsmE - 0U, // CGIJAsmH - 0U, // CGIJAsmHE - 0U, // CGIJAsmL - 0U, // CGIJAsmLE - 0U, // CGIJAsmLH - 0U, // CGIJAsmNE - 0U, // CGIJAsmNH - 0U, // CGIJAsmNHE - 0U, // CGIJAsmNL - 0U, // CGIJAsmNLE - 0U, // CGIJAsmNLH - 0U, // CGIT - 0U, // CGITAsm - 0U, // CGITAsmE - 0U, // CGITAsmH - 0U, // CGITAsmHE - 0U, // CGITAsmL - 0U, // CGITAsmLE - 0U, // CGITAsmLH - 0U, // CGITAsmNE - 0U, // CGITAsmNH - 0U, // CGITAsmNHE - 0U, // CGITAsmNL - 0U, // CGITAsmNLE - 0U, // CGITAsmNLH - 0U, // CGR - 0U, // CGRB - 0U, // CGRBAsm - 0U, // CGRBAsmE - 0U, // CGRBAsmH - 0U, // CGRBAsmHE - 0U, // CGRBAsmL - 0U, // CGRBAsmLE - 0U, // CGRBAsmLH - 0U, // CGRBAsmNE - 0U, // CGRBAsmNH - 0U, // CGRBAsmNHE - 0U, // CGRBAsmNL - 0U, // CGRBAsmNLE - 0U, // CGRBAsmNLH - 0U, // CGRJ - 0U, // CGRJAsm - 0U, // CGRJAsmE - 0U, // CGRJAsmH - 0U, // CGRJAsmHE - 0U, // CGRJAsmL - 0U, // CGRJAsmLE - 0U, // CGRJAsmLH - 0U, // CGRJAsmNE - 0U, // CGRJAsmNH - 0U, // CGRJAsmNHE - 0U, // CGRJAsmNL - 0U, // CGRJAsmNLE - 0U, // CGRJAsmNLH - 0U, // CGRL - 0U, // CGRT - 0U, // CGRTAsm - 0U, // CGRTAsmE - 0U, // CGRTAsmH - 0U, // CGRTAsmHE - 0U, // CGRTAsmL - 0U, // CGRTAsmLE - 0U, // CGRTAsmLH - 0U, // CGRTAsmNE - 0U, // CGRTAsmNH - 0U, // CGRTAsmNHE - 0U, // CGRTAsmNL - 0U, // CGRTAsmNLE - 0U, // CGRTAsmNLH - 0U, // CGXBR - 0U, // CGXBRA - 0U, // CGXR - 0U, // CGXTR - 0U, // CGXTRA - 0U, // CH - 0U, // CHF - 0U, // CHHR - 0U, // CHHSI - 0U, // CHI - 0U, // CHLR - 0U, // CHRL - 0U, // CHSI - 0U, // CHY - 0U, // CIB - 0U, // CIBAsm - 0U, // CIBAsmE - 0U, // CIBAsmH - 0U, // CIBAsmHE - 0U, // CIBAsmL - 0U, // CIBAsmLE - 0U, // CIBAsmLH - 0U, // CIBAsmNE - 0U, // CIBAsmNH - 0U, // CIBAsmNHE - 0U, // CIBAsmNL - 0U, // CIBAsmNLE - 0U, // CIBAsmNLH - 0U, // CIH - 0U, // CIJ - 0U, // CIJAsm - 0U, // CIJAsmE - 0U, // CIJAsmH - 0U, // CIJAsmHE - 0U, // CIJAsmL - 0U, // CIJAsmLE - 0U, // CIJAsmLH - 0U, // CIJAsmNE - 0U, // CIJAsmNH - 0U, // CIJAsmNHE - 0U, // CIJAsmNL - 0U, // CIJAsmNLE - 0U, // CIJAsmNLH - 0U, // CIT - 0U, // CITAsm - 0U, // CITAsmE - 0U, // CITAsmH - 0U, // CITAsmHE - 0U, // CITAsmL - 0U, // CITAsmLE - 0U, // CITAsmLH - 0U, // CITAsmNE - 0U, // CITAsmNH - 0U, // CITAsmNHE - 0U, // CITAsmNL - 0U, // CITAsmNLE - 0U, // CITAsmNLH - 0U, // CKSM - 0U, // CL - 0U, // CLC - 0U, // CLCL - 0U, // CLCLE - 0U, // CLCLU - 0U, // CLFDBR - 0U, // CLFDTR - 0U, // CLFEBR - 0U, // CLFHSI - 0U, // CLFI - 0U, // CLFIT - 0U, // CLFITAsm - 0U, // CLFITAsmE - 0U, // CLFITAsmH - 0U, // CLFITAsmHE - 0U, // CLFITAsmL - 0U, // CLFITAsmLE - 0U, // CLFITAsmLH - 0U, // CLFITAsmNE - 0U, // CLFITAsmNH - 0U, // CLFITAsmNHE - 0U, // CLFITAsmNL - 0U, // CLFITAsmNLE - 0U, // CLFITAsmNLH - 0U, // CLFXBR - 0U, // CLFXTR - 0U, // CLG - 0U, // CLGDBR - 0U, // CLGDTR - 0U, // CLGEBR - 0U, // CLGF - 0U, // CLGFI - 0U, // CLGFR - 0U, // CLGFRL - 0U, // CLGHRL - 0U, // CLGHSI - 0U, // CLGIB - 0U, // CLGIBAsm - 0U, // CLGIBAsmE - 0U, // CLGIBAsmH - 0U, // CLGIBAsmHE - 0U, // CLGIBAsmL - 0U, // CLGIBAsmLE - 0U, // CLGIBAsmLH - 0U, // CLGIBAsmNE - 0U, // CLGIBAsmNH - 0U, // CLGIBAsmNHE - 0U, // CLGIBAsmNL - 0U, // CLGIBAsmNLE - 0U, // CLGIBAsmNLH - 0U, // CLGIJ - 0U, // CLGIJAsm - 0U, // CLGIJAsmE - 0U, // CLGIJAsmH - 0U, // CLGIJAsmHE - 0U, // CLGIJAsmL - 0U, // CLGIJAsmLE - 0U, // CLGIJAsmLH - 0U, // CLGIJAsmNE - 0U, // CLGIJAsmNH - 0U, // CLGIJAsmNHE - 0U, // CLGIJAsmNL - 0U, // CLGIJAsmNLE - 0U, // CLGIJAsmNLH - 0U, // CLGIT - 0U, // CLGITAsm - 0U, // CLGITAsmE - 0U, // CLGITAsmH - 0U, // CLGITAsmHE - 0U, // CLGITAsmL - 0U, // CLGITAsmLE - 0U, // CLGITAsmLH - 0U, // CLGITAsmNE - 0U, // CLGITAsmNH - 0U, // CLGITAsmNHE - 0U, // CLGITAsmNL - 0U, // CLGITAsmNLE - 0U, // CLGITAsmNLH - 0U, // CLGR - 0U, // CLGRB - 0U, // CLGRBAsm - 0U, // CLGRBAsmE - 0U, // CLGRBAsmH - 0U, // CLGRBAsmHE - 0U, // CLGRBAsmL - 0U, // CLGRBAsmLE - 0U, // CLGRBAsmLH - 0U, // CLGRBAsmNE - 0U, // CLGRBAsmNH - 0U, // CLGRBAsmNHE - 0U, // CLGRBAsmNL - 0U, // CLGRBAsmNLE - 0U, // CLGRBAsmNLH - 0U, // CLGRJ - 0U, // CLGRJAsm - 0U, // CLGRJAsmE - 0U, // CLGRJAsmH - 0U, // CLGRJAsmHE - 0U, // CLGRJAsmL - 0U, // CLGRJAsmLE - 0U, // CLGRJAsmLH - 0U, // CLGRJAsmNE - 0U, // CLGRJAsmNH - 0U, // CLGRJAsmNHE - 0U, // CLGRJAsmNL - 0U, // CLGRJAsmNLE - 0U, // CLGRJAsmNLH - 0U, // CLGRL - 0U, // CLGRT - 0U, // CLGRTAsm - 0U, // CLGRTAsmE - 0U, // CLGRTAsmH - 0U, // CLGRTAsmHE - 0U, // CLGRTAsmL - 0U, // CLGRTAsmLE - 0U, // CLGRTAsmLH - 0U, // CLGRTAsmNE - 0U, // CLGRTAsmNH - 0U, // CLGRTAsmNHE - 0U, // CLGRTAsmNL - 0U, // CLGRTAsmNLE - 0U, // CLGRTAsmNLH - 0U, // CLGT - 0U, // CLGTAsm - 0U, // CLGTAsmE - 0U, // CLGTAsmH - 0U, // CLGTAsmHE - 0U, // CLGTAsmL - 0U, // CLGTAsmLE - 0U, // CLGTAsmLH - 0U, // CLGTAsmNE - 0U, // CLGTAsmNH - 0U, // CLGTAsmNHE - 0U, // CLGTAsmNL - 0U, // CLGTAsmNLE - 0U, // CLGTAsmNLH - 0U, // CLGXBR - 0U, // CLGXTR - 0U, // CLHF - 0U, // CLHHR - 0U, // CLHHSI - 0U, // CLHLR - 0U, // CLHRL - 0U, // CLI - 0U, // CLIB - 0U, // CLIBAsm - 0U, // CLIBAsmE - 0U, // CLIBAsmH - 0U, // CLIBAsmHE - 0U, // CLIBAsmL - 0U, // CLIBAsmLE - 0U, // CLIBAsmLH - 0U, // CLIBAsmNE - 0U, // CLIBAsmNH - 0U, // CLIBAsmNHE - 0U, // CLIBAsmNL - 0U, // CLIBAsmNLE - 0U, // CLIBAsmNLH - 0U, // CLIH - 0U, // CLIJ - 0U, // CLIJAsm - 0U, // CLIJAsmE - 0U, // CLIJAsmH - 0U, // CLIJAsmHE - 0U, // CLIJAsmL - 0U, // CLIJAsmLE - 0U, // CLIJAsmLH - 0U, // CLIJAsmNE - 0U, // CLIJAsmNH - 0U, // CLIJAsmNHE - 0U, // CLIJAsmNL - 0U, // CLIJAsmNLE - 0U, // CLIJAsmNLH - 0U, // CLIY - 0U, // CLM - 0U, // CLMH - 0U, // CLMY - 0U, // CLR - 0U, // CLRB - 0U, // CLRBAsm - 0U, // CLRBAsmE - 0U, // CLRBAsmH - 0U, // CLRBAsmHE - 0U, // CLRBAsmL - 0U, // CLRBAsmLE - 0U, // CLRBAsmLH - 0U, // CLRBAsmNE - 0U, // CLRBAsmNH - 0U, // CLRBAsmNHE - 0U, // CLRBAsmNL - 0U, // CLRBAsmNLE - 0U, // CLRBAsmNLH - 0U, // CLRJ - 0U, // CLRJAsm - 0U, // CLRJAsmE - 0U, // CLRJAsmH - 0U, // CLRJAsmHE - 0U, // CLRJAsmL - 0U, // CLRJAsmLE - 0U, // CLRJAsmLH - 0U, // CLRJAsmNE - 0U, // CLRJAsmNH - 0U, // CLRJAsmNHE - 0U, // CLRJAsmNL - 0U, // CLRJAsmNLE - 0U, // CLRJAsmNLH - 0U, // CLRL - 0U, // CLRT - 0U, // CLRTAsm - 0U, // CLRTAsmE - 0U, // CLRTAsmH - 0U, // CLRTAsmHE - 0U, // CLRTAsmL - 0U, // CLRTAsmLE - 0U, // CLRTAsmLH - 0U, // CLRTAsmNE - 0U, // CLRTAsmNH - 0U, // CLRTAsmNHE - 0U, // CLRTAsmNL - 0U, // CLRTAsmNLE - 0U, // CLRTAsmNLH - 0U, // CLST - 0U, // CLT - 0U, // CLTAsm - 0U, // CLTAsmE - 0U, // CLTAsmH - 0U, // CLTAsmHE - 0U, // CLTAsmL - 0U, // CLTAsmLE - 0U, // CLTAsmLH - 0U, // CLTAsmNE - 0U, // CLTAsmNH - 0U, // CLTAsmNHE - 0U, // CLTAsmNL - 0U, // CLTAsmNLE - 0U, // CLTAsmNLH - 0U, // CLY - 0U, // CMPSC - 0U, // CP - 0U, // CPDT - 0U, // CPSDRdd - 0U, // CPSDRds - 0U, // CPSDRsd - 0U, // CPSDRss - 0U, // CPXT - 0U, // CPYA - 0U, // CR - 0U, // CRB - 0U, // CRBAsm - 0U, // CRBAsmE - 0U, // CRBAsmH - 0U, // CRBAsmHE - 0U, // CRBAsmL - 0U, // CRBAsmLE - 0U, // CRBAsmLH - 0U, // CRBAsmNE - 0U, // CRBAsmNH - 0U, // CRBAsmNHE - 0U, // CRBAsmNL - 0U, // CRBAsmNLE - 0U, // CRBAsmNLH - 0U, // CRDTE - 0U, // CRDTEOpt - 0U, // CRJ - 0U, // CRJAsm - 0U, // CRJAsmE - 0U, // CRJAsmH - 0U, // CRJAsmHE - 0U, // CRJAsmL - 0U, // CRJAsmLE - 0U, // CRJAsmLH - 0U, // CRJAsmNE - 0U, // CRJAsmNH - 0U, // CRJAsmNHE - 0U, // CRJAsmNL - 0U, // CRJAsmNLE - 0U, // CRJAsmNLH - 0U, // CRL - 0U, // CRT - 0U, // CRTAsm - 0U, // CRTAsmE - 0U, // CRTAsmH - 0U, // CRTAsmHE - 0U, // CRTAsmL - 0U, // CRTAsmLE - 0U, // CRTAsmLH - 0U, // CRTAsmNE - 0U, // CRTAsmNH - 0U, // CRTAsmNHE - 0U, // CRTAsmNL - 0U, // CRTAsmNLE - 0U, // CRTAsmNLH - 0U, // CS - 0U, // CSCH - 0U, // CSDTR - 0U, // CSG - 0U, // CSP - 0U, // CSPG - 0U, // CSST - 0U, // CSXTR - 0U, // CSY - 0U, // CU12 - 0U, // CU12Opt - 0U, // CU14 - 0U, // CU14Opt - 0U, // CU21 - 0U, // CU21Opt - 0U, // CU24 - 0U, // CU24Opt - 0U, // CU41 - 0U, // CU42 - 0U, // CUDTR - 0U, // CUSE - 0U, // CUTFU - 0U, // CUTFUOpt - 0U, // CUUTF - 0U, // CUUTFOpt - 0U, // CUXTR - 0U, // CVB - 0U, // CVBG - 0U, // CVBY - 0U, // CVD - 0U, // CVDG - 0U, // CVDY - 0U, // CXBR - 0U, // CXFBR - 0U, // CXFBRA - 0U, // CXFR - 0U, // CXFTR - 0U, // CXGBR - 0U, // CXGBRA - 0U, // CXGR - 0U, // CXGTR - 0U, // CXGTRA - 0U, // CXLFBR - 0U, // CXLFTR - 0U, // CXLGBR - 0U, // CXLGTR - 0U, // CXPT - 0U, // CXR - 0U, // CXSTR - 0U, // CXTR - 0U, // CXUTR - 0U, // CXZT - 0U, // CY - 0U, // CZDT - 0U, // CZXT - 0U, // D - 0U, // DD - 0U, // DDB - 0U, // DDBR - 0U, // DDR - 0U, // DDTR - 0U, // DDTRA - 0U, // DE - 0U, // DEB - 0U, // DEBR - 0U, // DER - 0U, // DIAG - 0U, // DIDBR - 0U, // DIEBR - 0U, // DL - 0U, // DLG - 0U, // DLGR - 0U, // DLR - 0U, // DP - 0U, // DR - 0U, // DSG - 0U, // DSGF - 0U, // DSGFR - 0U, // DSGR - 0U, // DXBR - 0U, // DXR - 0U, // DXTR - 0U, // DXTRA - 0U, // EAR - 0U, // ECAG - 0U, // ECCTR - 0U, // ECPGA - 0U, // ECTG - 0U, // ED - 0U, // EDMK - 0U, // EEDTR - 0U, // EEXTR - 0U, // EFPC - 0U, // EPAIR - 0U, // EPAR - 0U, // EPCTR - 0U, // EPSW - 0U, // EREG - 0U, // EREGG - 0U, // ESAIR - 0U, // ESAR - 0U, // ESDTR - 0U, // ESEA - 0U, // ESTA - 0U, // ESXTR - 0U, // ETND - 0U, // EX - 0U, // EXRL - 0U, // FIDBR - 0U, // FIDBRA - 0U, // FIDR - 0U, // FIDTR - 0U, // FIEBR - 0U, // FIEBRA - 0U, // FIER - 0U, // FIXBR - 0U, // FIXBRA - 0U, // FIXR - 0U, // FIXTR - 0U, // FLOGR - 0U, // HDR - 0U, // HER - 0U, // HSCH - 0U, // IAC - 0U, // IC - 0U, // IC32 - 0U, // IC32Y - 0U, // ICM - 0U, // ICMH - 0U, // ICMY - 0U, // ICY - 0U, // IDTE - 0U, // IDTEOpt - 0U, // IEDTR - 0U, // IEXTR - 0U, // IIHF - 0U, // IIHH - 0U, // IIHL - 0U, // IILF - 0U, // IILH - 0U, // IILL - 0U, // IPK - 0U, // IPM - 0U, // IPTE - 0U, // IPTEOpt - 0U, // IPTEOptOpt - 0U, // IRBM - 0U, // ISKE - 0U, // IVSK - 0U, // InsnE - 0U, // InsnRI - 0U, // InsnRIE - 0U, // InsnRIL - 0U, // InsnRILU - 0U, // InsnRIS - 0U, // InsnRR - 0U, // InsnRRE - 0U, // InsnRRF - 0U, // InsnRRS - 0U, // InsnRS - 0U, // InsnRSE - 0U, // InsnRSI - 0U, // InsnRSY - 0U, // InsnRX - 0U, // InsnRXE - 0U, // InsnRXF - 0U, // InsnRXY - 0U, // InsnS - 0U, // InsnSI - 0U, // InsnSIL - 0U, // InsnSIY - 0U, // InsnSS - 0U, // InsnSSE - 0U, // InsnSSF - 0U, // J - 0U, // JAsmE - 0U, // JAsmH - 0U, // JAsmHE - 0U, // JAsmL - 0U, // JAsmLE - 0U, // JAsmLH - 0U, // JAsmM - 0U, // JAsmNE - 0U, // JAsmNH - 0U, // JAsmNHE - 0U, // JAsmNL - 0U, // JAsmNLE - 0U, // JAsmNLH - 0U, // JAsmNM - 0U, // JAsmNO - 0U, // JAsmNP - 0U, // JAsmNZ - 0U, // JAsmO - 0U, // JAsmP - 0U, // JAsmZ - 0U, // JG - 0U, // JGAsmE - 0U, // JGAsmH - 0U, // JGAsmHE - 0U, // JGAsmL - 0U, // JGAsmLE - 0U, // JGAsmLH - 0U, // JGAsmM - 0U, // JGAsmNE - 0U, // JGAsmNH - 0U, // JGAsmNHE - 0U, // JGAsmNL - 0U, // JGAsmNLE - 0U, // JGAsmNLH - 0U, // JGAsmNM - 0U, // JGAsmNO - 0U, // JGAsmNP - 0U, // JGAsmNZ - 0U, // JGAsmO - 0U, // JGAsmP - 0U, // JGAsmZ - 0U, // KDB - 0U, // KDBR - 0U, // KDTR - 0U, // KEB - 0U, // KEBR - 0U, // KIMD - 0U, // KLMD - 0U, // KM - 0U, // KMA - 0U, // KMAC - 0U, // KMC - 0U, // KMCTR - 0U, // KMF - 0U, // KMO - 0U, // KXBR - 0U, // KXTR - 0U, // L - 0U, // LA - 0U, // LAA - 0U, // LAAG - 0U, // LAAL - 0U, // LAALG - 0U, // LAE - 0U, // LAEY - 0U, // LAM - 0U, // LAMY - 0U, // LAN - 0U, // LANG - 0U, // LAO - 0U, // LAOG - 0U, // LARL - 0U, // LASP - 0U, // LAT - 0U, // LAX - 0U, // LAXG - 0U, // LAY - 0U, // LB - 0U, // LBH - 0U, // LBR - 0U, // LCBB - 0U, // LCCTL - 0U, // LCDBR - 0U, // LCDFR - 0U, // LCDFR_32 - 0U, // LCDR - 0U, // LCEBR - 0U, // LCER - 0U, // LCGFR - 0U, // LCGR - 0U, // LCR - 0U, // LCTL - 0U, // LCTLG - 0U, // LCXBR - 0U, // LCXR - 0U, // LD - 0U, // LDE - 0U, // LDE32 - 0U, // LDEB - 0U, // LDEBR - 0U, // LDER - 0U, // LDETR - 0U, // LDGR - 0U, // LDR - 0U, // LDR32 - 0U, // LDXBR - 0U, // LDXBRA - 0U, // LDXR - 0U, // LDXTR - 0U, // LDY - 0U, // LE - 0U, // LEDBR - 0U, // LEDBRA - 0U, // LEDR - 0U, // LEDTR - 0U, // LER - 0U, // LEXBR - 0U, // LEXBRA - 0U, // LEXR - 0U, // LEY - 0U, // LFAS - 0U, // LFH - 0U, // LFHAT - 0U, // LFPC - 0U, // LG - 0U, // LGAT - 0U, // LGB - 0U, // LGBR - 0U, // LGDR - 0U, // LGF - 0U, // LGFI - 0U, // LGFR - 0U, // LGFRL - 0U, // LGG - 0U, // LGH - 0U, // LGHI - 0U, // LGHR - 0U, // LGHRL - 0U, // LGR - 0U, // LGRL - 0U, // LGSC - 0U, // LH - 0U, // LHH - 0U, // LHI - 0U, // LHR - 0U, // LHRL - 0U, // LHY - 0U, // LLC - 0U, // LLCH - 0U, // LLCR - 0U, // LLGC - 0U, // LLGCR - 0U, // LLGF - 0U, // LLGFAT - 0U, // LLGFR - 0U, // LLGFRL - 0U, // LLGFSG - 0U, // LLGH - 0U, // LLGHR - 0U, // LLGHRL - 0U, // LLGT - 0U, // LLGTAT - 0U, // LLGTR - 0U, // LLH - 0U, // LLHH - 0U, // LLHR - 0U, // LLHRL - 0U, // LLIHF - 0U, // LLIHH - 0U, // LLIHL - 0U, // LLILF - 0U, // LLILH - 0U, // LLILL - 0U, // LLZRGF - 0U, // LM - 0U, // LMD - 0U, // LMG - 0U, // LMH - 0U, // LMY - 0U, // LNDBR - 0U, // LNDFR - 0U, // LNDFR_32 - 0U, // LNDR - 0U, // LNEBR - 0U, // LNER - 0U, // LNGFR - 0U, // LNGR - 0U, // LNR - 0U, // LNXBR - 0U, // LNXR - 0U, // LOC - 0U, // LOCAsm - 0U, // LOCAsmE - 0U, // LOCAsmH - 0U, // LOCAsmHE - 0U, // LOCAsmL - 0U, // LOCAsmLE - 0U, // LOCAsmLH - 0U, // LOCAsmM - 0U, // LOCAsmNE - 0U, // LOCAsmNH - 0U, // LOCAsmNHE - 0U, // LOCAsmNL - 0U, // LOCAsmNLE - 0U, // LOCAsmNLH - 0U, // LOCAsmNM - 0U, // LOCAsmNO - 0U, // LOCAsmNP - 0U, // LOCAsmNZ - 0U, // LOCAsmO - 0U, // LOCAsmP - 0U, // LOCAsmZ - 0U, // LOCFH - 0U, // LOCFHAsm - 0U, // LOCFHAsmE - 0U, // LOCFHAsmH - 0U, // LOCFHAsmHE - 0U, // LOCFHAsmL - 0U, // LOCFHAsmLE - 0U, // LOCFHAsmLH - 0U, // LOCFHAsmM - 0U, // LOCFHAsmNE - 0U, // LOCFHAsmNH - 0U, // LOCFHAsmNHE - 0U, // LOCFHAsmNL - 0U, // LOCFHAsmNLE - 0U, // LOCFHAsmNLH - 0U, // LOCFHAsmNM - 0U, // LOCFHAsmNO - 0U, // LOCFHAsmNP - 0U, // LOCFHAsmNZ - 0U, // LOCFHAsmO - 0U, // LOCFHAsmP - 0U, // LOCFHAsmZ - 0U, // LOCFHR - 0U, // LOCFHRAsm - 0U, // LOCFHRAsmE - 0U, // LOCFHRAsmH - 0U, // LOCFHRAsmHE - 0U, // LOCFHRAsmL - 0U, // LOCFHRAsmLE - 0U, // LOCFHRAsmLH - 0U, // LOCFHRAsmM - 0U, // LOCFHRAsmNE - 0U, // LOCFHRAsmNH - 0U, // LOCFHRAsmNHE - 0U, // LOCFHRAsmNL - 0U, // LOCFHRAsmNLE - 0U, // LOCFHRAsmNLH - 0U, // LOCFHRAsmNM - 0U, // LOCFHRAsmNO - 0U, // LOCFHRAsmNP - 0U, // LOCFHRAsmNZ - 0U, // LOCFHRAsmO - 0U, // LOCFHRAsmP - 0U, // LOCFHRAsmZ - 0U, // LOCG - 0U, // LOCGAsm - 0U, // LOCGAsmE - 0U, // LOCGAsmH - 0U, // LOCGAsmHE - 0U, // LOCGAsmL - 0U, // LOCGAsmLE - 0U, // LOCGAsmLH - 0U, // LOCGAsmM - 0U, // LOCGAsmNE - 0U, // LOCGAsmNH - 0U, // LOCGAsmNHE - 0U, // LOCGAsmNL - 0U, // LOCGAsmNLE - 0U, // LOCGAsmNLH - 0U, // LOCGAsmNM - 0U, // LOCGAsmNO - 0U, // LOCGAsmNP - 0U, // LOCGAsmNZ - 0U, // LOCGAsmO - 0U, // LOCGAsmP - 0U, // LOCGAsmZ - 0U, // LOCGHI - 0U, // LOCGHIAsm - 0U, // LOCGHIAsmE - 0U, // LOCGHIAsmH - 0U, // LOCGHIAsmHE - 0U, // LOCGHIAsmL - 0U, // LOCGHIAsmLE - 0U, // LOCGHIAsmLH - 0U, // LOCGHIAsmM - 0U, // LOCGHIAsmNE - 0U, // LOCGHIAsmNH - 0U, // LOCGHIAsmNHE - 0U, // LOCGHIAsmNL - 0U, // LOCGHIAsmNLE - 0U, // LOCGHIAsmNLH - 0U, // LOCGHIAsmNM - 0U, // LOCGHIAsmNO - 0U, // LOCGHIAsmNP - 0U, // LOCGHIAsmNZ - 0U, // LOCGHIAsmO - 0U, // LOCGHIAsmP - 0U, // LOCGHIAsmZ - 0U, // LOCGR - 0U, // LOCGRAsm - 0U, // LOCGRAsmE - 0U, // LOCGRAsmH - 0U, // LOCGRAsmHE - 0U, // LOCGRAsmL - 0U, // LOCGRAsmLE - 0U, // LOCGRAsmLH - 0U, // LOCGRAsmM - 0U, // LOCGRAsmNE - 0U, // LOCGRAsmNH - 0U, // LOCGRAsmNHE - 0U, // LOCGRAsmNL - 0U, // LOCGRAsmNLE - 0U, // LOCGRAsmNLH - 0U, // LOCGRAsmNM - 0U, // LOCGRAsmNO - 0U, // LOCGRAsmNP - 0U, // LOCGRAsmNZ - 0U, // LOCGRAsmO - 0U, // LOCGRAsmP - 0U, // LOCGRAsmZ - 0U, // LOCHHI - 0U, // LOCHHIAsm - 0U, // LOCHHIAsmE - 0U, // LOCHHIAsmH - 0U, // LOCHHIAsmHE - 0U, // LOCHHIAsmL - 0U, // LOCHHIAsmLE - 0U, // LOCHHIAsmLH - 0U, // LOCHHIAsmM - 0U, // LOCHHIAsmNE - 0U, // LOCHHIAsmNH - 0U, // LOCHHIAsmNHE - 0U, // LOCHHIAsmNL - 0U, // LOCHHIAsmNLE - 0U, // LOCHHIAsmNLH - 0U, // LOCHHIAsmNM - 0U, // LOCHHIAsmNO - 0U, // LOCHHIAsmNP - 0U, // LOCHHIAsmNZ - 0U, // LOCHHIAsmO - 0U, // LOCHHIAsmP - 0U, // LOCHHIAsmZ - 0U, // LOCHI - 0U, // LOCHIAsm - 0U, // LOCHIAsmE - 0U, // LOCHIAsmH - 0U, // LOCHIAsmHE - 0U, // LOCHIAsmL - 0U, // LOCHIAsmLE - 0U, // LOCHIAsmLH - 0U, // LOCHIAsmM - 0U, // LOCHIAsmNE - 0U, // LOCHIAsmNH - 0U, // LOCHIAsmNHE - 0U, // LOCHIAsmNL - 0U, // LOCHIAsmNLE - 0U, // LOCHIAsmNLH - 0U, // LOCHIAsmNM - 0U, // LOCHIAsmNO - 0U, // LOCHIAsmNP - 0U, // LOCHIAsmNZ - 0U, // LOCHIAsmO - 0U, // LOCHIAsmP - 0U, // LOCHIAsmZ - 0U, // LOCR - 0U, // LOCRAsm - 0U, // LOCRAsmE - 0U, // LOCRAsmH - 0U, // LOCRAsmHE - 0U, // LOCRAsmL - 0U, // LOCRAsmLE - 0U, // LOCRAsmLH - 0U, // LOCRAsmM - 0U, // LOCRAsmNE - 0U, // LOCRAsmNH - 0U, // LOCRAsmNHE - 0U, // LOCRAsmNL - 0U, // LOCRAsmNLE - 0U, // LOCRAsmNLH - 0U, // LOCRAsmNM - 0U, // LOCRAsmNO - 0U, // LOCRAsmNP - 0U, // LOCRAsmNZ - 0U, // LOCRAsmO - 0U, // LOCRAsmP - 0U, // LOCRAsmZ - 0U, // LPCTL - 0U, // LPD - 0U, // LPDBR - 0U, // LPDFR - 0U, // LPDFR_32 - 0U, // LPDG - 0U, // LPDR - 0U, // LPEBR - 0U, // LPER - 0U, // LPGFR - 0U, // LPGR - 0U, // LPP - 0U, // LPQ - 0U, // LPR - 0U, // LPSW - 0U, // LPSWE - 0U, // LPTEA - 0U, // LPXBR - 0U, // LPXR - 0U, // LR - 0U, // LRA - 0U, // LRAG - 0U, // LRAY - 0U, // LRDR - 0U, // LRER - 0U, // LRL - 0U, // LRV - 0U, // LRVG - 0U, // LRVGR - 0U, // LRVH - 0U, // LRVR - 0U, // LSCTL - 0U, // LT - 0U, // LTDBR - 0U, // LTDBRCompare - 0U, // LTDR - 0U, // LTDTR - 0U, // LTEBR - 0U, // LTEBRCompare - 0U, // LTER - 0U, // LTG - 0U, // LTGF - 0U, // LTGFR - 0U, // LTGR - 0U, // LTR - 0U, // LTXBR - 0U, // LTXBRCompare - 0U, // LTXR - 0U, // LTXTR - 0U, // LURA - 0U, // LURAG - 0U, // LXD - 0U, // LXDB - 0U, // LXDBR - 0U, // LXDR - 0U, // LXDTR - 0U, // LXE - 0U, // LXEB - 0U, // LXEBR - 0U, // LXER - 0U, // LXR - 0U, // LY - 0U, // LZDR - 0U, // LZER - 0U, // LZRF - 0U, // LZRG - 0U, // LZXR - 0U, // M - 0U, // MAD - 0U, // MADB - 0U, // MADBR - 0U, // MADR - 0U, // MAE - 0U, // MAEB - 0U, // MAEBR - 0U, // MAER - 0U, // MAY - 0U, // MAYH - 0U, // MAYHR - 0U, // MAYL - 0U, // MAYLR - 0U, // MAYR - 0U, // MC - 0U, // MD - 0U, // MDB - 0U, // MDBR - 0U, // MDE - 0U, // MDEB - 0U, // MDEBR - 0U, // MDER - 0U, // MDR - 0U, // MDTR - 0U, // MDTRA - 0U, // ME - 0U, // MEE - 0U, // MEEB - 0U, // MEEBR - 0U, // MEER - 0U, // MER - 0U, // MFY - 0U, // MG - 0U, // MGH - 0U, // MGHI - 0U, // MGRK - 0U, // MH - 0U, // MHI - 0U, // MHY - 0U, // ML - 0U, // MLG - 0U, // MLGR - 0U, // MLR - 0U, // MP - 0U, // MR - 0U, // MS - 0U, // MSC - 0U, // MSCH - 0U, // MSD - 0U, // MSDB - 0U, // MSDBR - 0U, // MSDR - 0U, // MSE - 0U, // MSEB - 0U, // MSEBR - 0U, // MSER - 0U, // MSFI - 0U, // MSG - 0U, // MSGC - 0U, // MSGF - 0U, // MSGFI - 0U, // MSGFR - 0U, // MSGR - 0U, // MSGRKC - 0U, // MSR - 0U, // MSRKC - 0U, // MSTA - 0U, // MSY - 0U, // MVC - 0U, // MVCDK - 0U, // MVCIN - 0U, // MVCK - 0U, // MVCL - 0U, // MVCLE - 0U, // MVCLU - 0U, // MVCOS - 0U, // MVCP - 0U, // MVCS - 0U, // MVCSK - 0U, // MVGHI - 0U, // MVHHI - 0U, // MVHI - 0U, // MVI - 0U, // MVIY - 0U, // MVN - 0U, // MVO - 0U, // MVPG - 0U, // MVST - 0U, // MVZ - 0U, // MXBR - 0U, // MXD - 0U, // MXDB - 0U, // MXDBR - 0U, // MXDR - 0U, // MXR - 0U, // MXTR - 0U, // MXTRA - 0U, // MY - 0U, // MYH - 0U, // MYHR - 0U, // MYL - 0U, // MYLR - 0U, // MYR - 0U, // N - 0U, // NC - 0U, // NG - 0U, // NGR - 0U, // NGRK - 0U, // NI - 0U, // NIAI - 0U, // NIHF - 0U, // NIHH - 0U, // NIHL - 0U, // NILF - 0U, // NILH - 0U, // NILL - 0U, // NIY - 0U, // NR - 0U, // NRK - 0U, // NTSTG - 0U, // NY - 0U, // O - 0U, // OC - 0U, // OG - 0U, // OGR - 0U, // OGRK - 0U, // OI - 0U, // OIHF - 0U, // OIHH - 0U, // OIHL - 0U, // OILF - 0U, // OILH - 0U, // OILL - 0U, // OIY - 0U, // OR - 0U, // ORK - 0U, // OY - 0U, // PACK - 0U, // PALB - 0U, // PC - 0U, // PCC - 0U, // PCKMO - 0U, // PFD - 0U, // PFDRL - 0U, // PFMF - 0U, // PFPO - 0U, // PGIN - 0U, // PGOUT - 0U, // PKA - 0U, // PKU - 0U, // PLO - 0U, // POPCNT - 0U, // PPA - 0U, // PPNO - 0U, // PR - 0U, // PRNO - 0U, // PT - 0U, // PTF - 0U, // PTFF - 0U, // PTI - 0U, // PTLB - 0U, // QADTR - 0U, // QAXTR - 0U, // QCTRI - 0U, // QSI - 0U, // RCHP - 2U, // RISBG - 2U, // RISBG32 - 2U, // RISBGN - 2U, // RISBHG - 2U, // RISBLG - 0U, // RLL - 0U, // RLLG - 2U, // RNSBG - 2U, // ROSBG - 0U, // RP - 0U, // RRBE - 0U, // RRBM - 0U, // RRDTR - 0U, // RRXTR - 0U, // RSCH - 2U, // RXSBG - 0U, // S - 0U, // SAC - 0U, // SACF - 0U, // SAL - 0U, // SAM24 - 0U, // SAM31 - 0U, // SAM64 - 0U, // SAR - 0U, // SCCTR - 0U, // SCHM - 0U, // SCK - 0U, // SCKC - 0U, // SCKPF - 0U, // SD - 0U, // SDB - 0U, // SDBR - 0U, // SDR - 0U, // SDTR - 0U, // SDTRA - 0U, // SE - 0U, // SEB - 0U, // SEBR - 0U, // SER - 0U, // SFASR - 0U, // SFPC - 0U, // SG - 0U, // SGF - 0U, // SGFR - 0U, // SGH - 0U, // SGR - 0U, // SGRK - 0U, // SH - 0U, // SHHHR - 0U, // SHHLR - 0U, // SHY - 0U, // SIE - 0U, // SIGA - 0U, // SIGP - 0U, // SL - 0U, // SLA - 0U, // SLAG - 0U, // SLAK - 0U, // SLB - 0U, // SLBG - 0U, // SLBGR - 0U, // SLBR - 0U, // SLDA - 0U, // SLDL - 0U, // SLDT - 0U, // SLFI - 0U, // SLG - 0U, // SLGF - 0U, // SLGFI - 0U, // SLGFR - 0U, // SLGR - 0U, // SLGRK - 0U, // SLHHHR - 0U, // SLHHLR - 0U, // SLL - 0U, // SLLG - 0U, // SLLK - 0U, // SLR - 0U, // SLRK - 0U, // SLXT - 0U, // SLY - 0U, // SP - 0U, // SPCTR - 0U, // SPKA - 0U, // SPM - 0U, // SPT - 0U, // SPX - 0U, // SQD - 0U, // SQDB - 0U, // SQDBR - 0U, // SQDR - 0U, // SQE - 0U, // SQEB - 0U, // SQEBR - 0U, // SQER - 0U, // SQXBR - 0U, // SQXR - 0U, // SR - 0U, // SRA - 0U, // SRAG - 0U, // SRAK - 0U, // SRDA - 0U, // SRDL - 0U, // SRDT - 0U, // SRK - 0U, // SRL - 0U, // SRLG - 0U, // SRLK - 0U, // SRNM - 0U, // SRNMB - 0U, // SRNMT - 0U, // SRP - 0U, // SRST - 0U, // SRSTU - 0U, // SRXT - 0U, // SSAIR - 0U, // SSAR - 0U, // SSCH - 0U, // SSKE - 0U, // SSKEOpt - 0U, // SSM - 0U, // ST - 0U, // STAM - 0U, // STAMY - 0U, // STAP - 0U, // STC - 0U, // STCH - 0U, // STCK - 0U, // STCKC - 0U, // STCKE - 0U, // STCKF - 0U, // STCM - 0U, // STCMH - 0U, // STCMY - 0U, // STCPS - 0U, // STCRW - 0U, // STCTG - 0U, // STCTL - 0U, // STCY - 0U, // STD - 0U, // STDY - 0U, // STE - 0U, // STEY - 0U, // STFH - 0U, // STFL - 0U, // STFLE - 0U, // STFPC - 0U, // STG - 0U, // STGRL - 0U, // STGSC - 0U, // STH - 0U, // STHH - 0U, // STHRL - 0U, // STHY - 0U, // STIDP - 0U, // STM - 0U, // STMG - 0U, // STMH - 0U, // STMY - 0U, // STNSM - 0U, // STOC - 0U, // STOCAsm - 0U, // STOCAsmE - 0U, // STOCAsmH - 0U, // STOCAsmHE - 0U, // STOCAsmL - 0U, // STOCAsmLE - 0U, // STOCAsmLH - 0U, // STOCAsmM - 0U, // STOCAsmNE - 0U, // STOCAsmNH - 0U, // STOCAsmNHE - 0U, // STOCAsmNL - 0U, // STOCAsmNLE - 0U, // STOCAsmNLH - 0U, // STOCAsmNM - 0U, // STOCAsmNO - 0U, // STOCAsmNP - 0U, // STOCAsmNZ - 0U, // STOCAsmO - 0U, // STOCAsmP - 0U, // STOCAsmZ - 0U, // STOCFH - 0U, // STOCFHAsm - 0U, // STOCFHAsmE - 0U, // STOCFHAsmH - 0U, // STOCFHAsmHE - 0U, // STOCFHAsmL - 0U, // STOCFHAsmLE - 0U, // STOCFHAsmLH - 0U, // STOCFHAsmM - 0U, // STOCFHAsmNE - 0U, // STOCFHAsmNH - 0U, // STOCFHAsmNHE - 0U, // STOCFHAsmNL - 0U, // STOCFHAsmNLE - 0U, // STOCFHAsmNLH - 0U, // STOCFHAsmNM - 0U, // STOCFHAsmNO - 0U, // STOCFHAsmNP - 0U, // STOCFHAsmNZ - 0U, // STOCFHAsmO - 0U, // STOCFHAsmP - 0U, // STOCFHAsmZ - 0U, // STOCG - 0U, // STOCGAsm - 0U, // STOCGAsmE - 0U, // STOCGAsmH - 0U, // STOCGAsmHE - 0U, // STOCGAsmL - 0U, // STOCGAsmLE - 0U, // STOCGAsmLH - 0U, // STOCGAsmM - 0U, // STOCGAsmNE - 0U, // STOCGAsmNH - 0U, // STOCGAsmNHE - 0U, // STOCGAsmNL - 0U, // STOCGAsmNLE - 0U, // STOCGAsmNLH - 0U, // STOCGAsmNM - 0U, // STOCGAsmNO - 0U, // STOCGAsmNP - 0U, // STOCGAsmNZ - 0U, // STOCGAsmO - 0U, // STOCGAsmP - 0U, // STOCGAsmZ - 0U, // STOSM - 0U, // STPQ - 0U, // STPT - 0U, // STPX - 0U, // STRAG - 0U, // STRL - 0U, // STRV - 0U, // STRVG - 0U, // STRVH - 0U, // STSCH - 0U, // STSI - 0U, // STURA - 0U, // STURG - 0U, // STY - 0U, // SU - 0U, // SUR - 0U, // SVC - 0U, // SW - 0U, // SWR - 0U, // SXBR - 0U, // SXR - 0U, // SXTR - 0U, // SXTRA - 0U, // SY - 0U, // TABORT - 0U, // TAM - 0U, // TAR - 0U, // TB - 0U, // TBDR - 0U, // TBEDR - 0U, // TBEGIN - 0U, // TBEGINC - 0U, // TCDB - 0U, // TCEB - 0U, // TCXB - 0U, // TDCDT - 0U, // TDCET - 0U, // TDCXT - 0U, // TDGDT - 0U, // TDGET - 0U, // TDGXT - 0U, // TEND - 0U, // THDER - 0U, // THDR - 0U, // TM - 0U, // TMHH - 0U, // TMHL - 0U, // TMLH - 0U, // TMLL - 0U, // TMY - 0U, // TP - 0U, // TPI - 0U, // TPROT - 0U, // TR - 0U, // TRACE - 0U, // TRACG - 0U, // TRAP2 - 0U, // TRAP4 - 0U, // TRE - 0U, // TROO - 0U, // TROOOpt - 0U, // TROT - 0U, // TROTOpt - 0U, // TRT - 0U, // TRTE - 0U, // TRTEOpt - 0U, // TRTO - 0U, // TRTOOpt - 0U, // TRTR - 0U, // TRTRE - 0U, // TRTREOpt - 0U, // TRTT - 0U, // TRTTOpt - 0U, // TS - 0U, // TSCH - 0U, // UNPK - 0U, // UNPKA - 0U, // UNPKU - 0U, // UPT - 0U, // VA - 0U, // VAB - 6U, // VAC - 0U, // VACC - 0U, // VACCB - 6U, // VACCC - 0U, // VACCCQ - 0U, // VACCF - 0U, // VACCG - 0U, // VACCH - 0U, // VACCQ - 0U, // VACQ - 0U, // VAF - 0U, // VAG - 0U, // VAH - 7U, // VAP - 0U, // VAQ - 0U, // VAVG - 0U, // VAVGB - 0U, // VAVGF - 0U, // VAVGG - 0U, // VAVGH - 0U, // VAVGL - 0U, // VAVGLB - 0U, // VAVGLF - 0U, // VAVGLG - 0U, // VAVGLH - 0U, // VBPERM - 6U, // VCDG - 0U, // VCDGB - 6U, // VCDLG - 0U, // VCDLGB - 6U, // VCEQ - 0U, // VCEQB - 0U, // VCEQBS - 0U, // VCEQF - 0U, // VCEQFS - 0U, // VCEQG - 0U, // VCEQGS - 0U, // VCEQH - 0U, // VCEQHS - 6U, // VCGD - 0U, // VCGDB - 6U, // VCH - 0U, // VCHB - 0U, // VCHBS - 0U, // VCHF - 0U, // VCHFS - 0U, // VCHG - 0U, // VCHGS - 0U, // VCHH - 0U, // VCHHS - 6U, // VCHL - 0U, // VCHLB - 0U, // VCHLBS - 0U, // VCHLF - 0U, // VCHLFS - 0U, // VCHLG - 0U, // VCHLGS - 0U, // VCHLH - 0U, // VCHLHS - 0U, // VCKSM - 6U, // VCLGD - 0U, // VCLGDB - 0U, // VCLZ - 0U, // VCLZB - 0U, // VCLZF - 0U, // VCLZG - 0U, // VCLZH - 0U, // VCP - 0U, // VCTZ - 0U, // VCTZB - 0U, // VCTZF - 0U, // VCTZG - 0U, // VCTZH - 0U, // VCVB - 0U, // VCVBG - 1U, // VCVD - 1U, // VCVDG - 7U, // VDP - 0U, // VEC - 0U, // VECB - 0U, // VECF - 0U, // VECG - 0U, // VECH - 0U, // VECL - 0U, // VECLB - 0U, // VECLF - 0U, // VECLG - 0U, // VECLH - 10U, // VERIM - 0U, // VERIMB - 0U, // VERIMF - 0U, // VERIMG - 0U, // VERIMH - 0U, // VERLL - 0U, // VERLLB - 0U, // VERLLF - 0U, // VERLLG - 0U, // VERLLH - 0U, // VERLLV - 0U, // VERLLVB - 0U, // VERLLVF - 0U, // VERLLVG - 0U, // VERLLVH - 0U, // VESL - 0U, // VESLB - 0U, // VESLF - 0U, // VESLG - 0U, // VESLH - 0U, // VESLV - 0U, // VESLVB - 0U, // VESLVF - 0U, // VESLVG - 0U, // VESLVH - 0U, // VESRA - 0U, // VESRAB - 0U, // VESRAF - 0U, // VESRAG - 0U, // VESRAH - 0U, // VESRAV - 0U, // VESRAVB - 0U, // VESRAVF - 0U, // VESRAVG - 0U, // VESRAVH - 0U, // VESRL - 0U, // VESRLB - 0U, // VESRLF - 0U, // VESRLG - 0U, // VESRLH - 0U, // VESRLV - 0U, // VESRLVB - 0U, // VESRLVF - 0U, // VESRLVG - 0U, // VESRLVH - 6U, // VFA - 0U, // VFADB - 6U, // VFAE - 0U, // VFAEB - 0U, // VFAEBS - 0U, // VFAEF - 0U, // VFAEFS - 0U, // VFAEH - 0U, // VFAEHS - 0U, // VFAEZB - 0U, // VFAEZBS - 0U, // VFAEZF - 0U, // VFAEZFS - 0U, // VFAEZH - 0U, // VFAEZHS - 0U, // VFASB - 22U, // VFCE - 0U, // VFCEDB - 0U, // VFCEDBS - 0U, // VFCESB - 0U, // VFCESBS - 22U, // VFCH - 0U, // VFCHDB - 0U, // VFCHDBS - 22U, // VFCHE - 0U, // VFCHEDB - 0U, // VFCHEDBS - 0U, // VFCHESB - 0U, // VFCHESBS - 0U, // VFCHSB - 0U, // VFCHSBS - 6U, // VFD - 0U, // VFDDB - 0U, // VFDSB - 6U, // VFEE - 0U, // VFEEB - 0U, // VFEEBS - 0U, // VFEEF - 0U, // VFEEFS - 0U, // VFEEH - 0U, // VFEEHS - 0U, // VFEEZB - 0U, // VFEEZBS - 0U, // VFEEZF - 0U, // VFEEZFS - 0U, // VFEEZH - 0U, // VFEEZHS - 6U, // VFENE - 0U, // VFENEB - 0U, // VFENEBS - 0U, // VFENEF - 0U, // VFENEFS - 0U, // VFENEH - 0U, // VFENEHS - 0U, // VFENEZB - 0U, // VFENEZBS - 0U, // VFENEZF - 0U, // VFENEZFS - 0U, // VFENEZH - 0U, // VFENEZHS - 6U, // VFI - 0U, // VFIDB - 0U, // VFISB - 0U, // VFKEDB - 0U, // VFKEDBS - 0U, // VFKESB - 0U, // VFKESBS - 0U, // VFKHDB - 0U, // VFKHDBS - 0U, // VFKHEDB - 0U, // VFKHEDBS - 0U, // VFKHESB - 0U, // VFKHESBS - 0U, // VFKHSB - 0U, // VFKHSBS - 0U, // VFLCDB - 0U, // VFLCSB - 0U, // VFLL - 0U, // VFLLS - 0U, // VFLNDB - 0U, // VFLNSB - 0U, // VFLPDB - 0U, // VFLPSB - 6U, // VFLR - 0U, // VFLRD - 6U, // VFM - 22U, // VFMA - 0U, // VFMADB - 0U, // VFMASB - 22U, // VFMAX - 0U, // VFMAXDB - 0U, // VFMAXSB - 0U, // VFMDB - 22U, // VFMIN - 0U, // VFMINDB - 0U, // VFMINSB - 22U, // VFMS - 0U, // VFMSB - 0U, // VFMSDB - 0U, // VFMSSB - 22U, // VFNMA - 0U, // VFNMADB - 0U, // VFNMASB - 22U, // VFNMS - 0U, // VFNMSDB - 0U, // VFNMSSB - 6U, // VFPSO - 0U, // VFPSODB - 0U, // VFPSOSB - 6U, // VFS - 0U, // VFSDB - 0U, // VFSQ - 0U, // VFSQDB - 0U, // VFSQSB - 0U, // VFSSB - 6U, // VFTCI - 0U, // VFTCIDB - 0U, // VFTCISB - 0U, // VGBM - 0U, // VGEF - 0U, // VGEG - 0U, // VGFM - 6U, // VGFMA - 0U, // VGFMAB - 0U, // VGFMAF - 0U, // VGFMAG - 0U, // VGFMAH - 0U, // VGFMB - 0U, // VGFMF - 0U, // VGFMG - 0U, // VGFMH - 0U, // VGM - 0U, // VGMB - 0U, // VGMF - 0U, // VGMG - 0U, // VGMH - 0U, // VISTR - 0U, // VISTRB - 0U, // VISTRBS - 0U, // VISTRF - 0U, // VISTRFS - 0U, // VISTRH - 0U, // VISTRHS - 0U, // VL - 0U, // VLBB - 0U, // VLC - 0U, // VLCB - 0U, // VLCF - 0U, // VLCG - 0U, // VLCH - 0U, // VLDE - 0U, // VLDEB - 0U, // VLEB - 6U, // VLED - 0U, // VLEDB - 0U, // VLEF - 0U, // VLEG - 0U, // VLEH - 0U, // VLEIB - 0U, // VLEIF - 0U, // VLEIG - 0U, // VLEIH - 0U, // VLGV - 0U, // VLGVB - 0U, // VLGVF - 0U, // VLGVG - 0U, // VLGVH - 0U, // VLIP - 0U, // VLL - 0U, // VLLEZ - 0U, // VLLEZB - 0U, // VLLEZF - 0U, // VLLEZG - 0U, // VLLEZH - 0U, // VLLEZLF - 0U, // VLM - 0U, // VLP - 0U, // VLPB - 0U, // VLPF - 0U, // VLPG - 0U, // VLPH - 0U, // VLR - 0U, // VLREP - 0U, // VLREPB - 0U, // VLREPF - 0U, // VLREPG - 0U, // VLREPH - 0U, // VLRL - 0U, // VLRLR - 1U, // VLVG - 0U, // VLVGB - 0U, // VLVGF - 0U, // VLVGG - 0U, // VLVGH - 0U, // VLVGP - 6U, // VMAE - 0U, // VMAEB - 0U, // VMAEF - 0U, // VMAEH - 6U, // VMAH - 0U, // VMAHB - 0U, // VMAHF - 0U, // VMAHH - 6U, // VMAL - 0U, // VMALB - 6U, // VMALE - 0U, // VMALEB - 0U, // VMALEF - 0U, // VMALEH - 0U, // VMALF - 6U, // VMALH - 0U, // VMALHB - 0U, // VMALHF - 0U, // VMALHH - 0U, // VMALHW - 6U, // VMALO - 0U, // VMALOB - 0U, // VMALOF - 0U, // VMALOH - 6U, // VMAO - 0U, // VMAOB - 0U, // VMAOF - 0U, // VMAOH - 0U, // VME - 0U, // VMEB - 0U, // VMEF - 0U, // VMEH - 0U, // VMH - 0U, // VMHB - 0U, // VMHF - 0U, // VMHH - 0U, // VML - 0U, // VMLB - 0U, // VMLE - 0U, // VMLEB - 0U, // VMLEF - 0U, // VMLEH - 0U, // VMLF - 0U, // VMLH - 0U, // VMLHB - 0U, // VMLHF - 0U, // VMLHH - 0U, // VMLHW - 0U, // VMLO - 0U, // VMLOB - 0U, // VMLOF - 0U, // VMLOH - 0U, // VMN - 0U, // VMNB - 0U, // VMNF - 0U, // VMNG - 0U, // VMNH - 0U, // VMNL - 0U, // VMNLB - 0U, // VMNLF - 0U, // VMNLG - 0U, // VMNLH - 0U, // VMO - 0U, // VMOB - 0U, // VMOF - 0U, // VMOH - 7U, // VMP - 0U, // VMRH - 0U, // VMRHB - 0U, // VMRHF - 0U, // VMRHG - 0U, // VMRHH - 0U, // VMRL - 0U, // VMRLB - 0U, // VMRLF - 0U, // VMRLG - 0U, // VMRLH - 22U, // VMSL - 6U, // VMSLG - 7U, // VMSP - 0U, // VMX - 0U, // VMXB - 0U, // VMXF - 0U, // VMXG - 0U, // VMXH - 0U, // VMXL - 0U, // VMXLB - 0U, // VMXLF - 0U, // VMXLG - 0U, // VMXLH - 0U, // VN - 0U, // VNC - 0U, // VNN - 0U, // VNO - 0U, // VNX - 0U, // VO - 0U, // VOC - 0U, // VONE - 0U, // VPDI - 0U, // VPERM - 0U, // VPK - 0U, // VPKF - 0U, // VPKG - 0U, // VPKH - 6U, // VPKLS - 0U, // VPKLSF - 0U, // VPKLSFS - 0U, // VPKLSG - 0U, // VPKLSGS - 0U, // VPKLSH - 0U, // VPKLSHS - 6U, // VPKS - 0U, // VPKSF - 0U, // VPKSFS - 0U, // VPKSG - 0U, // VPKSGS - 0U, // VPKSH - 0U, // VPKSHS - 0U, // VPKZ - 0U, // VPOPCT - 0U, // VPOPCTB - 0U, // VPOPCTF - 0U, // VPOPCTG - 0U, // VPOPCTH - 0U, // VPSOP - 0U, // VREP - 0U, // VREPB - 0U, // VREPF - 0U, // VREPG - 0U, // VREPH - 0U, // VREPI - 0U, // VREPIB - 0U, // VREPIF - 0U, // VREPIG - 0U, // VREPIH - 7U, // VRP - 0U, // VS - 0U, // VSB - 6U, // VSBCBI - 0U, // VSBCBIQ - 6U, // VSBI - 0U, // VSBIQ - 0U, // VSCBI - 0U, // VSCBIB - 0U, // VSCBIF - 0U, // VSCBIG - 0U, // VSCBIH - 0U, // VSCBIQ - 0U, // VSCEF - 0U, // VSCEG - 7U, // VSDP - 0U, // VSEG - 0U, // VSEGB - 0U, // VSEGF - 0U, // VSEGH - 0U, // VSEL - 0U, // VSF - 0U, // VSG - 0U, // VSH - 0U, // VSL - 0U, // VSLB - 1U, // VSLDB - 7U, // VSP - 0U, // VSQ - 0U, // VSRA - 0U, // VSRAB - 0U, // VSRL - 0U, // VSRLB - 0U, // VSRP - 0U, // VST - 0U, // VSTEB - 0U, // VSTEF - 0U, // VSTEG - 0U, // VSTEH - 0U, // VSTL - 0U, // VSTM - 22U, // VSTRC - 6U, // VSTRCB - 6U, // VSTRCBS - 6U, // VSTRCF - 6U, // VSTRCFS - 6U, // VSTRCH - 6U, // VSTRCHS - 6U, // VSTRCZB - 6U, // VSTRCZBS - 6U, // VSTRCZF - 6U, // VSTRCZFS - 6U, // VSTRCZH - 6U, // VSTRCZHS - 0U, // VSTRL - 0U, // VSTRLR - 0U, // VSUM - 0U, // VSUMB - 0U, // VSUMG - 0U, // VSUMGF - 0U, // VSUMGH - 0U, // VSUMH - 0U, // VSUMQ - 0U, // VSUMQF - 0U, // VSUMQG - 0U, // VTM - 0U, // VTP - 0U, // VUPH - 0U, // VUPHB - 0U, // VUPHF - 0U, // VUPHH - 0U, // VUPKZ - 0U, // VUPL - 0U, // VUPLB - 0U, // VUPLF - 0U, // VUPLH - 0U, // VUPLHB - 0U, // VUPLHF - 0U, // VUPLHH - 0U, // VUPLHW - 0U, // VUPLL - 0U, // VUPLLB - 0U, // VUPLLF - 0U, // VUPLLH - 0U, // VX - 0U, // VZERO - 0U, // WCDGB - 0U, // WCDLGB - 0U, // WCGDB - 0U, // WCLGDB - 0U, // WFADB - 0U, // WFASB - 0U, // WFAXB - 0U, // WFC - 0U, // WFCDB - 0U, // WFCEDB - 0U, // WFCEDBS - 0U, // WFCESB - 0U, // WFCESBS - 0U, // WFCEXB - 0U, // WFCEXBS - 0U, // WFCHDB - 0U, // WFCHDBS - 0U, // WFCHEDB - 0U, // WFCHEDBS - 0U, // WFCHESB - 0U, // WFCHESBS - 0U, // WFCHEXB - 0U, // WFCHEXBS - 0U, // WFCHSB - 0U, // WFCHSBS - 0U, // WFCHXB - 0U, // WFCHXBS - 0U, // WFCSB - 0U, // WFCXB - 0U, // WFDDB - 0U, // WFDSB - 0U, // WFDXB - 0U, // WFIDB - 0U, // WFISB - 0U, // WFIXB - 0U, // WFK - 0U, // WFKDB - 0U, // WFKEDB - 0U, // WFKEDBS - 0U, // WFKESB - 0U, // WFKESBS - 0U, // WFKEXB - 0U, // WFKEXBS - 0U, // WFKHDB - 0U, // WFKHDBS - 0U, // WFKHEDB - 0U, // WFKHEDBS - 0U, // WFKHESB - 0U, // WFKHESBS - 0U, // WFKHEXB - 0U, // WFKHEXBS - 0U, // WFKHSB - 0U, // WFKHSBS - 0U, // WFKHXB - 0U, // WFKHXBS - 0U, // WFKSB - 0U, // WFKXB - 0U, // WFLCDB - 0U, // WFLCSB - 0U, // WFLCXB - 0U, // WFLLD - 0U, // WFLLS - 0U, // WFLNDB - 0U, // WFLNSB - 0U, // WFLNXB - 0U, // WFLPDB - 0U, // WFLPSB - 0U, // WFLPXB - 0U, // WFLRD - 0U, // WFLRX - 0U, // WFMADB - 0U, // WFMASB - 0U, // WFMAXB - 0U, // WFMAXDB - 0U, // WFMAXSB - 0U, // WFMAXXB - 0U, // WFMDB - 0U, // WFMINDB - 0U, // WFMINSB - 0U, // WFMINXB - 0U, // WFMSB - 0U, // WFMSDB - 0U, // WFMSSB - 0U, // WFMSXB - 0U, // WFMXB - 0U, // WFNMADB - 0U, // WFNMASB - 0U, // WFNMAXB - 0U, // WFNMSDB - 0U, // WFNMSSB - 0U, // WFNMSXB - 0U, // WFPSODB - 0U, // WFPSOSB - 0U, // WFPSOXB - 0U, // WFSDB - 0U, // WFSQDB - 0U, // WFSQSB - 0U, // WFSQXB - 0U, // WFSSB - 0U, // WFSXB - 0U, // WFTCIDB - 0U, // WFTCISB - 0U, // WFTCIXB - 0U, // WLDEB - 0U, // WLEDB - 0U, // X - 0U, // XC - 0U, // XG - 0U, // XGR - 0U, // XGRK - 0U, // XI - 0U, // XIHF - 0U, // XILF - 0U, // XIY - 0U, // XR - 0U, // XRK - 0U, // XSCH - 0U, // XY - 0U, // ZAP + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADJDYNALLOC + 0U, // AEXT128 + 0U, // AFIMux + 0U, // AHIMux + 0U, // AHIMuxK + 0U, // ATOMIC_CMP_SWAPW + 0U, // ATOMIC_LOADW_AFI + 0U, // ATOMIC_LOADW_AR + 0U, // ATOMIC_LOADW_MAX + 0U, // ATOMIC_LOADW_MIN + 0U, // ATOMIC_LOADW_NILH + 0U, // ATOMIC_LOADW_NILHi + 0U, // ATOMIC_LOADW_NR + 0U, // ATOMIC_LOADW_NRi + 0U, // ATOMIC_LOADW_OILH + 0U, // ATOMIC_LOADW_OR + 0U, // ATOMIC_LOADW_SR + 0U, // ATOMIC_LOADW_UMAX + 0U, // ATOMIC_LOADW_UMIN + 0U, // ATOMIC_LOADW_XILF + 0U, // ATOMIC_LOADW_XR + 0U, // ATOMIC_LOAD_AFI + 0U, // ATOMIC_LOAD_AGFI + 0U, // ATOMIC_LOAD_AGHI + 0U, // ATOMIC_LOAD_AGR + 0U, // ATOMIC_LOAD_AHI + 0U, // ATOMIC_LOAD_AR + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NGR + 0U, // ATOMIC_LOAD_NGRi + 0U, // ATOMIC_LOAD_NIHF64 + 0U, // ATOMIC_LOAD_NIHF64i + 0U, // ATOMIC_LOAD_NIHH64 + 0U, // ATOMIC_LOAD_NIHH64i + 0U, // ATOMIC_LOAD_NIHL64 + 0U, // ATOMIC_LOAD_NIHL64i + 0U, // ATOMIC_LOAD_NILF + 0U, // ATOMIC_LOAD_NILF64 + 0U, // ATOMIC_LOAD_NILF64i + 0U, // ATOMIC_LOAD_NILFi + 0U, // ATOMIC_LOAD_NILH + 0U, // ATOMIC_LOAD_NILH64 + 0U, // ATOMIC_LOAD_NILH64i + 0U, // ATOMIC_LOAD_NILHi + 0U, // ATOMIC_LOAD_NILL + 0U, // ATOMIC_LOAD_NILL64 + 0U, // ATOMIC_LOAD_NILL64i + 0U, // ATOMIC_LOAD_NILLi + 0U, // ATOMIC_LOAD_NR + 0U, // ATOMIC_LOAD_NRi + 0U, // ATOMIC_LOAD_OGR + 0U, // ATOMIC_LOAD_OIHF64 + 0U, // ATOMIC_LOAD_OIHH64 + 0U, // ATOMIC_LOAD_OIHL64 + 0U, // ATOMIC_LOAD_OILF + 0U, // ATOMIC_LOAD_OILF64 + 0U, // ATOMIC_LOAD_OILH + 0U, // ATOMIC_LOAD_OILH64 + 0U, // ATOMIC_LOAD_OILL + 0U, // ATOMIC_LOAD_OILL64 + 0U, // ATOMIC_LOAD_OR + 0U, // ATOMIC_LOAD_SGR + 0U, // ATOMIC_LOAD_SR + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XGR + 0U, // ATOMIC_LOAD_XIHF64 + 0U, // ATOMIC_LOAD_XILF + 0U, // ATOMIC_LOAD_XILF64 + 0U, // ATOMIC_LOAD_XR + 0U, // ATOMIC_SWAPW + 0U, // ATOMIC_SWAP_32 + 0U, // ATOMIC_SWAP_64 + 0U, // CFIMux + 0U, // CGIBCall + 0U, // CGIBReturn + 0U, // CGRBCall + 0U, // CGRBReturn + 0U, // CHIMux + 0U, // CIBCall + 0U, // CIBReturn + 0U, // CLCLoop + 0U, // CLCSequence + 0U, // CLFIMux + 0U, // CLGIBCall + 0U, // CLGIBReturn + 0U, // CLGRBCall + 0U, // CLGRBReturn + 0U, // CLIBCall + 0U, // CLIBReturn + 0U, // CLMux + 0U, // CLRBCall + 0U, // CLRBReturn + 0U, // CLSTLoop + 0U, // CMux + 0U, // CRBCall + 0U, // CRBReturn + 0U, // CallBASR + 0U, // CallBCR + 0U, // CallBR + 0U, // CallBRASL + 0U, // CallBRCL + 0U, // CallJG + 0U, // CondReturn + 0U, // CondStore16 + 0U, // CondStore16Inv + 0U, // CondStore16Mux + 0U, // CondStore16MuxInv + 0U, // CondStore32 + 0U, // CondStore32Inv + 0U, // CondStore32Mux + 0U, // CondStore32MuxInv + 0U, // CondStore64 + 0U, // CondStore64Inv + 0U, // CondStore8 + 0U, // CondStore8Inv + 0U, // CondStore8Mux + 0U, // CondStore8MuxInv + 0U, // CondStoreF32 + 0U, // CondStoreF32Inv + 0U, // CondStoreF64 + 0U, // CondStoreF64Inv + 0U, // CondTrap + 0U, // GOT + 0U, // IIFMux + 0U, // IIHF64 + 0U, // IIHH64 + 0U, // IIHL64 + 0U, // IIHMux + 0U, // IILF64 + 0U, // IILH64 + 0U, // IILL64 + 0U, // IILMux + 0U, // L128 + 0U, // LBMux + 0U, // LEFR + 0U, // LFER + 0U, // LHIMux + 0U, // LHMux + 0U, // LLCMux + 0U, // LLCRMux + 0U, // LLHMux + 0U, // LLHRMux + 0U, // LMux + 0U, // LOCHIMux + 0U, // LOCMux + 0U, // LOCRMux + 0U, // LRMux + 0U, // LTDBRCompare_VecPseudo + 0U, // LTEBRCompare_VecPseudo + 0U, // LTXBRCompare_VecPseudo + 0U, // LX + 0U, // MVCLoop + 0U, // MVCSequence + 0U, // MVSTLoop + 0U, // MemBarrier + 0U, // NCLoop + 0U, // NCSequence + 0U, // NIFMux + 0U, // NIHF64 + 0U, // NIHH64 + 0U, // NIHL64 + 0U, // NIHMux + 0U, // NILF64 + 0U, // NILH64 + 0U, // NILL64 + 0U, // NILMux + 0U, // OCLoop + 0U, // OCSequence + 0U, // OIFMux + 0U, // OIHF64 + 0U, // OIHH64 + 0U, // OIHL64 + 0U, // OIHMux + 0U, // OILF64 + 0U, // OILH64 + 0U, // OILL64 + 0U, // OILMux + 0U, // PAIR128 + 0U, // RISBHH + 0U, // RISBHL + 0U, // RISBLH + 0U, // RISBLL + 0U, // RISBMux + 0U, // Return + 0U, // SRSTLoop + 0U, // ST128 + 0U, // STCMux + 0U, // STHMux + 0U, // STMux + 0U, // STOCMux + 0U, // STX + 0U, // Select32 + 0U, // Select64 + 0U, // SelectF128 + 0U, // SelectF32 + 0U, // SelectF64 + 0U, // SelectVR128 + 0U, // SelectVR32 + 0U, // SelectVR64 + 0U, // Serialize + 0U, // TBEGIN_nofloat + 0U, // TLS_GDCALL + 0U, // TLS_LDCALL + 0U, // TMHH64 + 0U, // TMHL64 + 0U, // TMHMux + 0U, // TMLH64 + 0U, // TMLL64 + 0U, // TMLMux + 0U, // Trap + 0U, // VL32 + 0U, // VL64 + 0U, // VLR32 + 0U, // VLR64 + 0U, // VLVGP32 + 0U, // VST32 + 0U, // VST64 + 0U, // XCLoop + 0U, // XCSequence + 0U, // XIFMux + 0U, // XIHF64 + 0U, // XILF64 + 0U, // ZEXT128 + 0U, // A + 0U, // AD + 0U, // ADB + 0U, // ADBR + 0U, // ADR + 0U, // ADTR + 0U, // ADTRA + 0U, // AE + 0U, // AEB + 0U, // AEBR + 0U, // AER + 0U, // AFI + 0U, // AG + 0U, // AGF + 0U, // AGFI + 0U, // AGFR + 0U, // AGH + 0U, // AGHI + 0U, // AGHIK + 0U, // AGR + 0U, // AGRK + 0U, // AGSI + 0U, // AH + 0U, // AHHHR + 0U, // AHHLR + 0U, // AHI + 0U, // AHIK + 0U, // AHY + 0U, // AIH + 0U, // AL + 0U, // ALC + 0U, // ALCG + 0U, // ALCGR + 0U, // ALCR + 0U, // ALFI + 0U, // ALG + 0U, // ALGF + 0U, // ALGFI + 0U, // ALGFR + 0U, // ALGHSIK + 0U, // ALGR + 0U, // ALGRK + 0U, // ALGSI + 0U, // ALHHHR + 0U, // ALHHLR + 0U, // ALHSIK + 0U, // ALR + 0U, // ALRK + 0U, // ALSI + 0U, // ALSIH + 0U, // ALSIHN + 0U, // ALY + 0U, // AP + 0U, // AR + 0U, // ARK + 0U, // ASI + 0U, // AU + 0U, // AUR + 0U, // AW + 0U, // AWR + 0U, // AXBR + 0U, // AXR + 0U, // AXTR + 0U, // AXTRA + 0U, // AY + 0U, // B + 0U, // BAKR + 0U, // BAL + 0U, // BALR + 0U, // BAS + 0U, // BASR + 0U, // BASSM + 0U, // BAsmE + 0U, // BAsmH + 0U, // BAsmHE + 0U, // BAsmL + 0U, // BAsmLE + 0U, // BAsmLH + 0U, // BAsmM + 0U, // BAsmNE + 0U, // BAsmNH + 0U, // BAsmNHE + 0U, // BAsmNL + 0U, // BAsmNLE + 0U, // BAsmNLH + 0U, // BAsmNM + 0U, // BAsmNO + 0U, // BAsmNP + 0U, // BAsmNZ + 0U, // BAsmO + 0U, // BAsmP + 0U, // BAsmZ + 0U, // BC + 0U, // BCAsm + 0U, // BCR + 0U, // BCRAsm + 0U, // BCT + 0U, // BCTG + 0U, // BCTGR + 0U, // BCTR + 0U, // BI + 0U, // BIAsmE + 0U, // BIAsmH + 0U, // BIAsmHE + 0U, // BIAsmL + 0U, // BIAsmLE + 0U, // BIAsmLH + 0U, // BIAsmM + 0U, // BIAsmNE + 0U, // BIAsmNH + 0U, // BIAsmNHE + 0U, // BIAsmNL + 0U, // BIAsmNLE + 0U, // BIAsmNLH + 0U, // BIAsmNM + 0U, // BIAsmNO + 0U, // BIAsmNP + 0U, // BIAsmNZ + 0U, // BIAsmO + 0U, // BIAsmP + 0U, // BIAsmZ + 0U, // BIC + 0U, // BICAsm + 0U, // BPP + 0U, // BPRP + 0U, // BR + 0U, // BRAS + 0U, // BRASL + 0U, // BRAsmE + 0U, // BRAsmH + 0U, // BRAsmHE + 0U, // BRAsmL + 0U, // BRAsmLE + 0U, // BRAsmLH + 0U, // BRAsmM + 0U, // BRAsmNE + 0U, // BRAsmNH + 0U, // BRAsmNHE + 0U, // BRAsmNL + 0U, // BRAsmNLE + 0U, // BRAsmNLH + 0U, // BRAsmNM + 0U, // BRAsmNO + 0U, // BRAsmNP + 0U, // BRAsmNZ + 0U, // BRAsmO + 0U, // BRAsmP + 0U, // BRAsmZ + 0U, // BRC + 0U, // BRCAsm + 0U, // BRCL + 0U, // BRCLAsm + 0U, // BRCT + 0U, // BRCTG + 0U, // BRCTH + 0U, // BRXH + 0U, // BRXHG + 0U, // BRXLE + 0U, // BRXLG + 0U, // BSA + 0U, // BSG + 0U, // BSM + 0U, // BXH + 0U, // BXHG + 0U, // BXLE + 0U, // BXLEG + 0U, // C + 0U, // CD + 0U, // CDB + 0U, // CDBR + 0U, // CDFBR + 0U, // CDFBRA + 0U, // CDFR + 0U, // CDFTR + 0U, // CDGBR + 0U, // CDGBRA + 0U, // CDGR + 0U, // CDGTR + 0U, // CDGTRA + 0U, // CDLFBR + 0U, // CDLFTR + 0U, // CDLGBR + 0U, // CDLGTR + 0U, // CDPT + 0U, // CDR + 0U, // CDS + 0U, // CDSG + 0U, // CDSTR + 0U, // CDSY + 0U, // CDTR + 0U, // CDUTR + 0U, // CDZT + 0U, // CE + 0U, // CEB + 0U, // CEBR + 0U, // CEDTR + 0U, // CEFBR + 0U, // CEFBRA + 0U, // CEFR + 0U, // CEGBR + 0U, // CEGBRA + 0U, // CEGR + 0U, // CELFBR + 0U, // CELGBR + 0U, // CER + 0U, // CEXTR + 0U, // CFC + 0U, // CFDBR + 0U, // CFDBRA + 0U, // CFDR + 0U, // CFDTR + 0U, // CFEBR + 0U, // CFEBRA + 0U, // CFER + 0U, // CFI + 0U, // CFXBR + 0U, // CFXBRA + 0U, // CFXR + 0U, // CFXTR + 0U, // CG + 0U, // CGDBR + 0U, // CGDBRA + 0U, // CGDR + 0U, // CGDTR + 0U, // CGDTRA + 0U, // CGEBR + 0U, // CGEBRA + 0U, // CGER + 0U, // CGF + 0U, // CGFI + 0U, // CGFR + 0U, // CGFRL + 0U, // CGH + 0U, // CGHI + 0U, // CGHRL + 0U, // CGHSI + 0U, // CGIB + 0U, // CGIBAsm + 0U, // CGIBAsmE + 0U, // CGIBAsmH + 0U, // CGIBAsmHE + 0U, // CGIBAsmL + 0U, // CGIBAsmLE + 0U, // CGIBAsmLH + 0U, // CGIBAsmNE + 0U, // CGIBAsmNH + 0U, // CGIBAsmNHE + 0U, // CGIBAsmNL + 0U, // CGIBAsmNLE + 0U, // CGIBAsmNLH + 0U, // CGIJ + 0U, // CGIJAsm + 0U, // CGIJAsmE + 0U, // CGIJAsmH + 0U, // CGIJAsmHE + 0U, // CGIJAsmL + 0U, // CGIJAsmLE + 0U, // CGIJAsmLH + 0U, // CGIJAsmNE + 0U, // CGIJAsmNH + 0U, // CGIJAsmNHE + 0U, // CGIJAsmNL + 0U, // CGIJAsmNLE + 0U, // CGIJAsmNLH + 0U, // CGIT + 0U, // CGITAsm + 0U, // CGITAsmE + 0U, // CGITAsmH + 0U, // CGITAsmHE + 0U, // CGITAsmL + 0U, // CGITAsmLE + 0U, // CGITAsmLH + 0U, // CGITAsmNE + 0U, // CGITAsmNH + 0U, // CGITAsmNHE + 0U, // CGITAsmNL + 0U, // CGITAsmNLE + 0U, // CGITAsmNLH + 0U, // CGR + 0U, // CGRB + 0U, // CGRBAsm + 0U, // CGRBAsmE + 0U, // CGRBAsmH + 0U, // CGRBAsmHE + 0U, // CGRBAsmL + 0U, // CGRBAsmLE + 0U, // CGRBAsmLH + 0U, // CGRBAsmNE + 0U, // CGRBAsmNH + 0U, // CGRBAsmNHE + 0U, // CGRBAsmNL + 0U, // CGRBAsmNLE + 0U, // CGRBAsmNLH + 0U, // CGRJ + 0U, // CGRJAsm + 0U, // CGRJAsmE + 0U, // CGRJAsmH + 0U, // CGRJAsmHE + 0U, // CGRJAsmL + 0U, // CGRJAsmLE + 0U, // CGRJAsmLH + 0U, // CGRJAsmNE + 0U, // CGRJAsmNH + 0U, // CGRJAsmNHE + 0U, // CGRJAsmNL + 0U, // CGRJAsmNLE + 0U, // CGRJAsmNLH + 0U, // CGRL + 0U, // CGRT + 0U, // CGRTAsm + 0U, // CGRTAsmE + 0U, // CGRTAsmH + 0U, // CGRTAsmHE + 0U, // CGRTAsmL + 0U, // CGRTAsmLE + 0U, // CGRTAsmLH + 0U, // CGRTAsmNE + 0U, // CGRTAsmNH + 0U, // CGRTAsmNHE + 0U, // CGRTAsmNL + 0U, // CGRTAsmNLE + 0U, // CGRTAsmNLH + 0U, // CGXBR + 0U, // CGXBRA + 0U, // CGXR + 0U, // CGXTR + 0U, // CGXTRA + 0U, // CH + 0U, // CHF + 0U, // CHHR + 0U, // CHHSI + 0U, // CHI + 0U, // CHLR + 0U, // CHRL + 0U, // CHSI + 0U, // CHY + 0U, // CIB + 0U, // CIBAsm + 0U, // CIBAsmE + 0U, // CIBAsmH + 0U, // CIBAsmHE + 0U, // CIBAsmL + 0U, // CIBAsmLE + 0U, // CIBAsmLH + 0U, // CIBAsmNE + 0U, // CIBAsmNH + 0U, // CIBAsmNHE + 0U, // CIBAsmNL + 0U, // CIBAsmNLE + 0U, // CIBAsmNLH + 0U, // CIH + 0U, // CIJ + 0U, // CIJAsm + 0U, // CIJAsmE + 0U, // CIJAsmH + 0U, // CIJAsmHE + 0U, // CIJAsmL + 0U, // CIJAsmLE + 0U, // CIJAsmLH + 0U, // CIJAsmNE + 0U, // CIJAsmNH + 0U, // CIJAsmNHE + 0U, // CIJAsmNL + 0U, // CIJAsmNLE + 0U, // CIJAsmNLH + 0U, // CIT + 0U, // CITAsm + 0U, // CITAsmE + 0U, // CITAsmH + 0U, // CITAsmHE + 0U, // CITAsmL + 0U, // CITAsmLE + 0U, // CITAsmLH + 0U, // CITAsmNE + 0U, // CITAsmNH + 0U, // CITAsmNHE + 0U, // CITAsmNL + 0U, // CITAsmNLE + 0U, // CITAsmNLH + 0U, // CKSM + 0U, // CL + 0U, // CLC + 0U, // CLCL + 0U, // CLCLE + 0U, // CLCLU + 0U, // CLFDBR + 0U, // CLFDTR + 0U, // CLFEBR + 0U, // CLFHSI + 0U, // CLFI + 0U, // CLFIT + 0U, // CLFITAsm + 0U, // CLFITAsmE + 0U, // CLFITAsmH + 0U, // CLFITAsmHE + 0U, // CLFITAsmL + 0U, // CLFITAsmLE + 0U, // CLFITAsmLH + 0U, // CLFITAsmNE + 0U, // CLFITAsmNH + 0U, // CLFITAsmNHE + 0U, // CLFITAsmNL + 0U, // CLFITAsmNLE + 0U, // CLFITAsmNLH + 0U, // CLFXBR + 0U, // CLFXTR + 0U, // CLG + 0U, // CLGDBR + 0U, // CLGDTR + 0U, // CLGEBR + 0U, // CLGF + 0U, // CLGFI + 0U, // CLGFR + 0U, // CLGFRL + 0U, // CLGHRL + 0U, // CLGHSI + 0U, // CLGIB + 0U, // CLGIBAsm + 0U, // CLGIBAsmE + 0U, // CLGIBAsmH + 0U, // CLGIBAsmHE + 0U, // CLGIBAsmL + 0U, // CLGIBAsmLE + 0U, // CLGIBAsmLH + 0U, // CLGIBAsmNE + 0U, // CLGIBAsmNH + 0U, // CLGIBAsmNHE + 0U, // CLGIBAsmNL + 0U, // CLGIBAsmNLE + 0U, // CLGIBAsmNLH + 0U, // CLGIJ + 0U, // CLGIJAsm + 0U, // CLGIJAsmE + 0U, // CLGIJAsmH + 0U, // CLGIJAsmHE + 0U, // CLGIJAsmL + 0U, // CLGIJAsmLE + 0U, // CLGIJAsmLH + 0U, // CLGIJAsmNE + 0U, // CLGIJAsmNH + 0U, // CLGIJAsmNHE + 0U, // CLGIJAsmNL + 0U, // CLGIJAsmNLE + 0U, // CLGIJAsmNLH + 0U, // CLGIT + 0U, // CLGITAsm + 0U, // CLGITAsmE + 0U, // CLGITAsmH + 0U, // CLGITAsmHE + 0U, // CLGITAsmL + 0U, // CLGITAsmLE + 0U, // CLGITAsmLH + 0U, // CLGITAsmNE + 0U, // CLGITAsmNH + 0U, // CLGITAsmNHE + 0U, // CLGITAsmNL + 0U, // CLGITAsmNLE + 0U, // CLGITAsmNLH + 0U, // CLGR + 0U, // CLGRB + 0U, // CLGRBAsm + 0U, // CLGRBAsmE + 0U, // CLGRBAsmH + 0U, // CLGRBAsmHE + 0U, // CLGRBAsmL + 0U, // CLGRBAsmLE + 0U, // CLGRBAsmLH + 0U, // CLGRBAsmNE + 0U, // CLGRBAsmNH + 0U, // CLGRBAsmNHE + 0U, // CLGRBAsmNL + 0U, // CLGRBAsmNLE + 0U, // CLGRBAsmNLH + 0U, // CLGRJ + 0U, // CLGRJAsm + 0U, // CLGRJAsmE + 0U, // CLGRJAsmH + 0U, // CLGRJAsmHE + 0U, // CLGRJAsmL + 0U, // CLGRJAsmLE + 0U, // CLGRJAsmLH + 0U, // CLGRJAsmNE + 0U, // CLGRJAsmNH + 0U, // CLGRJAsmNHE + 0U, // CLGRJAsmNL + 0U, // CLGRJAsmNLE + 0U, // CLGRJAsmNLH + 0U, // CLGRL + 0U, // CLGRT + 0U, // CLGRTAsm + 0U, // CLGRTAsmE + 0U, // CLGRTAsmH + 0U, // CLGRTAsmHE + 0U, // CLGRTAsmL + 0U, // CLGRTAsmLE + 0U, // CLGRTAsmLH + 0U, // CLGRTAsmNE + 0U, // CLGRTAsmNH + 0U, // CLGRTAsmNHE + 0U, // CLGRTAsmNL + 0U, // CLGRTAsmNLE + 0U, // CLGRTAsmNLH + 0U, // CLGT + 0U, // CLGTAsm + 0U, // CLGTAsmE + 0U, // CLGTAsmH + 0U, // CLGTAsmHE + 0U, // CLGTAsmL + 0U, // CLGTAsmLE + 0U, // CLGTAsmLH + 0U, // CLGTAsmNE + 0U, // CLGTAsmNH + 0U, // CLGTAsmNHE + 0U, // CLGTAsmNL + 0U, // CLGTAsmNLE + 0U, // CLGTAsmNLH + 0U, // CLGXBR + 0U, // CLGXTR + 0U, // CLHF + 0U, // CLHHR + 0U, // CLHHSI + 0U, // CLHLR + 0U, // CLHRL + 0U, // CLI + 0U, // CLIB + 0U, // CLIBAsm + 0U, // CLIBAsmE + 0U, // CLIBAsmH + 0U, // CLIBAsmHE + 0U, // CLIBAsmL + 0U, // CLIBAsmLE + 0U, // CLIBAsmLH + 0U, // CLIBAsmNE + 0U, // CLIBAsmNH + 0U, // CLIBAsmNHE + 0U, // CLIBAsmNL + 0U, // CLIBAsmNLE + 0U, // CLIBAsmNLH + 0U, // CLIH + 0U, // CLIJ + 0U, // CLIJAsm + 0U, // CLIJAsmE + 0U, // CLIJAsmH + 0U, // CLIJAsmHE + 0U, // CLIJAsmL + 0U, // CLIJAsmLE + 0U, // CLIJAsmLH + 0U, // CLIJAsmNE + 0U, // CLIJAsmNH + 0U, // CLIJAsmNHE + 0U, // CLIJAsmNL + 0U, // CLIJAsmNLE + 0U, // CLIJAsmNLH + 0U, // CLIY + 0U, // CLM + 0U, // CLMH + 0U, // CLMY + 0U, // CLR + 0U, // CLRB + 0U, // CLRBAsm + 0U, // CLRBAsmE + 0U, // CLRBAsmH + 0U, // CLRBAsmHE + 0U, // CLRBAsmL + 0U, // CLRBAsmLE + 0U, // CLRBAsmLH + 0U, // CLRBAsmNE + 0U, // CLRBAsmNH + 0U, // CLRBAsmNHE + 0U, // CLRBAsmNL + 0U, // CLRBAsmNLE + 0U, // CLRBAsmNLH + 0U, // CLRJ + 0U, // CLRJAsm + 0U, // CLRJAsmE + 0U, // CLRJAsmH + 0U, // CLRJAsmHE + 0U, // CLRJAsmL + 0U, // CLRJAsmLE + 0U, // CLRJAsmLH + 0U, // CLRJAsmNE + 0U, // CLRJAsmNH + 0U, // CLRJAsmNHE + 0U, // CLRJAsmNL + 0U, // CLRJAsmNLE + 0U, // CLRJAsmNLH + 0U, // CLRL + 0U, // CLRT + 0U, // CLRTAsm + 0U, // CLRTAsmE + 0U, // CLRTAsmH + 0U, // CLRTAsmHE + 0U, // CLRTAsmL + 0U, // CLRTAsmLE + 0U, // CLRTAsmLH + 0U, // CLRTAsmNE + 0U, // CLRTAsmNH + 0U, // CLRTAsmNHE + 0U, // CLRTAsmNL + 0U, // CLRTAsmNLE + 0U, // CLRTAsmNLH + 0U, // CLST + 0U, // CLT + 0U, // CLTAsm + 0U, // CLTAsmE + 0U, // CLTAsmH + 0U, // CLTAsmHE + 0U, // CLTAsmL + 0U, // CLTAsmLE + 0U, // CLTAsmLH + 0U, // CLTAsmNE + 0U, // CLTAsmNH + 0U, // CLTAsmNHE + 0U, // CLTAsmNL + 0U, // CLTAsmNLE + 0U, // CLTAsmNLH + 0U, // CLY + 0U, // CMPSC + 0U, // CP + 0U, // CPDT + 0U, // CPSDRdd + 0U, // CPSDRds + 0U, // CPSDRsd + 0U, // CPSDRss + 0U, // CPXT + 0U, // CPYA + 0U, // CR + 0U, // CRB + 0U, // CRBAsm + 0U, // CRBAsmE + 0U, // CRBAsmH + 0U, // CRBAsmHE + 0U, // CRBAsmL + 0U, // CRBAsmLE + 0U, // CRBAsmLH + 0U, // CRBAsmNE + 0U, // CRBAsmNH + 0U, // CRBAsmNHE + 0U, // CRBAsmNL + 0U, // CRBAsmNLE + 0U, // CRBAsmNLH + 0U, // CRDTE + 0U, // CRDTEOpt + 0U, // CRJ + 0U, // CRJAsm + 0U, // CRJAsmE + 0U, // CRJAsmH + 0U, // CRJAsmHE + 0U, // CRJAsmL + 0U, // CRJAsmLE + 0U, // CRJAsmLH + 0U, // CRJAsmNE + 0U, // CRJAsmNH + 0U, // CRJAsmNHE + 0U, // CRJAsmNL + 0U, // CRJAsmNLE + 0U, // CRJAsmNLH + 0U, // CRL + 0U, // CRT + 0U, // CRTAsm + 0U, // CRTAsmE + 0U, // CRTAsmH + 0U, // CRTAsmHE + 0U, // CRTAsmL + 0U, // CRTAsmLE + 0U, // CRTAsmLH + 0U, // CRTAsmNE + 0U, // CRTAsmNH + 0U, // CRTAsmNHE + 0U, // CRTAsmNL + 0U, // CRTAsmNLE + 0U, // CRTAsmNLH + 0U, // CS + 0U, // CSCH + 0U, // CSDTR + 0U, // CSG + 0U, // CSP + 0U, // CSPG + 0U, // CSST + 0U, // CSXTR + 0U, // CSY + 0U, // CU12 + 0U, // CU12Opt + 0U, // CU14 + 0U, // CU14Opt + 0U, // CU21 + 0U, // CU21Opt + 0U, // CU24 + 0U, // CU24Opt + 0U, // CU41 + 0U, // CU42 + 0U, // CUDTR + 0U, // CUSE + 0U, // CUTFU + 0U, // CUTFUOpt + 0U, // CUUTF + 0U, // CUUTFOpt + 0U, // CUXTR + 0U, // CVB + 0U, // CVBG + 0U, // CVBY + 0U, // CVD + 0U, // CVDG + 0U, // CVDY + 0U, // CXBR + 0U, // CXFBR + 0U, // CXFBRA + 0U, // CXFR + 0U, // CXFTR + 0U, // CXGBR + 0U, // CXGBRA + 0U, // CXGR + 0U, // CXGTR + 0U, // CXGTRA + 0U, // CXLFBR + 0U, // CXLFTR + 0U, // CXLGBR + 0U, // CXLGTR + 0U, // CXPT + 0U, // CXR + 0U, // CXSTR + 0U, // CXTR + 0U, // CXUTR + 0U, // CXZT + 0U, // CY + 0U, // CZDT + 0U, // CZXT + 0U, // D + 0U, // DD + 0U, // DDB + 0U, // DDBR + 0U, // DDR + 0U, // DDTR + 0U, // DDTRA + 0U, // DE + 0U, // DEB + 0U, // DEBR + 0U, // DER + 0U, // DIAG + 0U, // DIDBR + 0U, // DIEBR + 0U, // DL + 0U, // DLG + 0U, // DLGR + 0U, // DLR + 0U, // DP + 0U, // DR + 0U, // DSG + 0U, // DSGF + 0U, // DSGFR + 0U, // DSGR + 0U, // DXBR + 0U, // DXR + 0U, // DXTR + 0U, // DXTRA + 0U, // EAR + 0U, // ECAG + 0U, // ECCTR + 0U, // ECPGA + 0U, // ECTG + 0U, // ED + 0U, // EDMK + 0U, // EEDTR + 0U, // EEXTR + 0U, // EFPC + 0U, // EPAIR + 0U, // EPAR + 0U, // EPCTR + 0U, // EPSW + 0U, // EREG + 0U, // EREGG + 0U, // ESAIR + 0U, // ESAR + 0U, // ESDTR + 0U, // ESEA + 0U, // ESTA + 0U, // ESXTR + 0U, // ETND + 0U, // EX + 0U, // EXRL + 0U, // FIDBR + 0U, // FIDBRA + 0U, // FIDR + 0U, // FIDTR + 0U, // FIEBR + 0U, // FIEBRA + 0U, // FIER + 0U, // FIXBR + 0U, // FIXBRA + 0U, // FIXR + 0U, // FIXTR + 0U, // FLOGR + 0U, // HDR + 0U, // HER + 0U, // HSCH + 0U, // IAC + 0U, // IC + 0U, // IC32 + 0U, // IC32Y + 0U, // ICM + 0U, // ICMH + 0U, // ICMY + 0U, // ICY + 0U, // IDTE + 0U, // IDTEOpt + 0U, // IEDTR + 0U, // IEXTR + 0U, // IIHF + 0U, // IIHH + 0U, // IIHL + 0U, // IILF + 0U, // IILH + 0U, // IILL + 0U, // IPK + 0U, // IPM + 0U, // IPTE + 0U, // IPTEOpt + 0U, // IPTEOptOpt + 0U, // IRBM + 0U, // ISKE + 0U, // IVSK + 0U, // InsnE + 0U, // InsnRI + 0U, // InsnRIE + 0U, // InsnRIL + 0U, // InsnRILU + 0U, // InsnRIS + 0U, // InsnRR + 0U, // InsnRRE + 0U, // InsnRRF + 0U, // InsnRRS + 0U, // InsnRS + 0U, // InsnRSE + 0U, // InsnRSI + 0U, // InsnRSY + 0U, // InsnRX + 0U, // InsnRXE + 0U, // InsnRXF + 0U, // InsnRXY + 0U, // InsnS + 0U, // InsnSI + 0U, // InsnSIL + 0U, // InsnSIY + 0U, // InsnSS + 0U, // InsnSSE + 0U, // InsnSSF + 0U, // J + 0U, // JAsmE + 0U, // JAsmH + 0U, // JAsmHE + 0U, // JAsmL + 0U, // JAsmLE + 0U, // JAsmLH + 0U, // JAsmM + 0U, // JAsmNE + 0U, // JAsmNH + 0U, // JAsmNHE + 0U, // JAsmNL + 0U, // JAsmNLE + 0U, // JAsmNLH + 0U, // JAsmNM + 0U, // JAsmNO + 0U, // JAsmNP + 0U, // JAsmNZ + 0U, // JAsmO + 0U, // JAsmP + 0U, // JAsmZ + 0U, // JG + 0U, // JGAsmE + 0U, // JGAsmH + 0U, // JGAsmHE + 0U, // JGAsmL + 0U, // JGAsmLE + 0U, // JGAsmLH + 0U, // JGAsmM + 0U, // JGAsmNE + 0U, // JGAsmNH + 0U, // JGAsmNHE + 0U, // JGAsmNL + 0U, // JGAsmNLE + 0U, // JGAsmNLH + 0U, // JGAsmNM + 0U, // JGAsmNO + 0U, // JGAsmNP + 0U, // JGAsmNZ + 0U, // JGAsmO + 0U, // JGAsmP + 0U, // JGAsmZ + 0U, // KDB + 0U, // KDBR + 0U, // KDTR + 0U, // KEB + 0U, // KEBR + 0U, // KIMD + 0U, // KLMD + 0U, // KM + 0U, // KMA + 0U, // KMAC + 0U, // KMC + 0U, // KMCTR + 0U, // KMF + 0U, // KMO + 0U, // KXBR + 0U, // KXTR + 0U, // L + 0U, // LA + 0U, // LAA + 0U, // LAAG + 0U, // LAAL + 0U, // LAALG + 0U, // LAE + 0U, // LAEY + 0U, // LAM + 0U, // LAMY + 0U, // LAN + 0U, // LANG + 0U, // LAO + 0U, // LAOG + 0U, // LARL + 0U, // LASP + 0U, // LAT + 0U, // LAX + 0U, // LAXG + 0U, // LAY + 0U, // LB + 0U, // LBH + 0U, // LBR + 0U, // LCBB + 0U, // LCCTL + 0U, // LCDBR + 0U, // LCDFR + 0U, // LCDFR_32 + 0U, // LCDR + 0U, // LCEBR + 0U, // LCER + 0U, // LCGFR + 0U, // LCGR + 0U, // LCR + 0U, // LCTL + 0U, // LCTLG + 0U, // LCXBR + 0U, // LCXR + 0U, // LD + 0U, // LDE + 0U, // LDE32 + 0U, // LDEB + 0U, // LDEBR + 0U, // LDER + 0U, // LDETR + 0U, // LDGR + 0U, // LDR + 0U, // LDR32 + 0U, // LDXBR + 0U, // LDXBRA + 0U, // LDXR + 0U, // LDXTR + 0U, // LDY + 0U, // LE + 0U, // LEDBR + 0U, // LEDBRA + 0U, // LEDR + 0U, // LEDTR + 0U, // LER + 0U, // LEXBR + 0U, // LEXBRA + 0U, // LEXR + 0U, // LEY + 0U, // LFAS + 0U, // LFH + 0U, // LFHAT + 0U, // LFPC + 0U, // LG + 0U, // LGAT + 0U, // LGB + 0U, // LGBR + 0U, // LGDR + 0U, // LGF + 0U, // LGFI + 0U, // LGFR + 0U, // LGFRL + 0U, // LGG + 0U, // LGH + 0U, // LGHI + 0U, // LGHR + 0U, // LGHRL + 0U, // LGR + 0U, // LGRL + 0U, // LGSC + 0U, // LH + 0U, // LHH + 0U, // LHI + 0U, // LHR + 0U, // LHRL + 0U, // LHY + 0U, // LLC + 0U, // LLCH + 0U, // LLCR + 0U, // LLGC + 0U, // LLGCR + 0U, // LLGF + 0U, // LLGFAT + 0U, // LLGFR + 0U, // LLGFRL + 0U, // LLGFSG + 0U, // LLGH + 0U, // LLGHR + 0U, // LLGHRL + 0U, // LLGT + 0U, // LLGTAT + 0U, // LLGTR + 0U, // LLH + 0U, // LLHH + 0U, // LLHR + 0U, // LLHRL + 0U, // LLIHF + 0U, // LLIHH + 0U, // LLIHL + 0U, // LLILF + 0U, // LLILH + 0U, // LLILL + 0U, // LLZRGF + 0U, // LM + 0U, // LMD + 0U, // LMG + 0U, // LMH + 0U, // LMY + 0U, // LNDBR + 0U, // LNDFR + 0U, // LNDFR_32 + 0U, // LNDR + 0U, // LNEBR + 0U, // LNER + 0U, // LNGFR + 0U, // LNGR + 0U, // LNR + 0U, // LNXBR + 0U, // LNXR + 0U, // LOC + 0U, // LOCAsm + 0U, // LOCAsmE + 0U, // LOCAsmH + 0U, // LOCAsmHE + 0U, // LOCAsmL + 0U, // LOCAsmLE + 0U, // LOCAsmLH + 0U, // LOCAsmM + 0U, // LOCAsmNE + 0U, // LOCAsmNH + 0U, // LOCAsmNHE + 0U, // LOCAsmNL + 0U, // LOCAsmNLE + 0U, // LOCAsmNLH + 0U, // LOCAsmNM + 0U, // LOCAsmNO + 0U, // LOCAsmNP + 0U, // LOCAsmNZ + 0U, // LOCAsmO + 0U, // LOCAsmP + 0U, // LOCAsmZ + 0U, // LOCFH + 0U, // LOCFHAsm + 0U, // LOCFHAsmE + 0U, // LOCFHAsmH + 0U, // LOCFHAsmHE + 0U, // LOCFHAsmL + 0U, // LOCFHAsmLE + 0U, // LOCFHAsmLH + 0U, // LOCFHAsmM + 0U, // LOCFHAsmNE + 0U, // LOCFHAsmNH + 0U, // LOCFHAsmNHE + 0U, // LOCFHAsmNL + 0U, // LOCFHAsmNLE + 0U, // LOCFHAsmNLH + 0U, // LOCFHAsmNM + 0U, // LOCFHAsmNO + 0U, // LOCFHAsmNP + 0U, // LOCFHAsmNZ + 0U, // LOCFHAsmO + 0U, // LOCFHAsmP + 0U, // LOCFHAsmZ + 0U, // LOCFHR + 0U, // LOCFHRAsm + 0U, // LOCFHRAsmE + 0U, // LOCFHRAsmH + 0U, // LOCFHRAsmHE + 0U, // LOCFHRAsmL + 0U, // LOCFHRAsmLE + 0U, // LOCFHRAsmLH + 0U, // LOCFHRAsmM + 0U, // LOCFHRAsmNE + 0U, // LOCFHRAsmNH + 0U, // LOCFHRAsmNHE + 0U, // LOCFHRAsmNL + 0U, // LOCFHRAsmNLE + 0U, // LOCFHRAsmNLH + 0U, // LOCFHRAsmNM + 0U, // LOCFHRAsmNO + 0U, // LOCFHRAsmNP + 0U, // LOCFHRAsmNZ + 0U, // LOCFHRAsmO + 0U, // LOCFHRAsmP + 0U, // LOCFHRAsmZ + 0U, // LOCG + 0U, // LOCGAsm + 0U, // LOCGAsmE + 0U, // LOCGAsmH + 0U, // LOCGAsmHE + 0U, // LOCGAsmL + 0U, // LOCGAsmLE + 0U, // LOCGAsmLH + 0U, // LOCGAsmM + 0U, // LOCGAsmNE + 0U, // LOCGAsmNH + 0U, // LOCGAsmNHE + 0U, // LOCGAsmNL + 0U, // LOCGAsmNLE + 0U, // LOCGAsmNLH + 0U, // LOCGAsmNM + 0U, // LOCGAsmNO + 0U, // LOCGAsmNP + 0U, // LOCGAsmNZ + 0U, // LOCGAsmO + 0U, // LOCGAsmP + 0U, // LOCGAsmZ + 0U, // LOCGHI + 0U, // LOCGHIAsm + 0U, // LOCGHIAsmE + 0U, // LOCGHIAsmH + 0U, // LOCGHIAsmHE + 0U, // LOCGHIAsmL + 0U, // LOCGHIAsmLE + 0U, // LOCGHIAsmLH + 0U, // LOCGHIAsmM + 0U, // LOCGHIAsmNE + 0U, // LOCGHIAsmNH + 0U, // LOCGHIAsmNHE + 0U, // LOCGHIAsmNL + 0U, // LOCGHIAsmNLE + 0U, // LOCGHIAsmNLH + 0U, // LOCGHIAsmNM + 0U, // LOCGHIAsmNO + 0U, // LOCGHIAsmNP + 0U, // LOCGHIAsmNZ + 0U, // LOCGHIAsmO + 0U, // LOCGHIAsmP + 0U, // LOCGHIAsmZ + 0U, // LOCGR + 0U, // LOCGRAsm + 0U, // LOCGRAsmE + 0U, // LOCGRAsmH + 0U, // LOCGRAsmHE + 0U, // LOCGRAsmL + 0U, // LOCGRAsmLE + 0U, // LOCGRAsmLH + 0U, // LOCGRAsmM + 0U, // LOCGRAsmNE + 0U, // LOCGRAsmNH + 0U, // LOCGRAsmNHE + 0U, // LOCGRAsmNL + 0U, // LOCGRAsmNLE + 0U, // LOCGRAsmNLH + 0U, // LOCGRAsmNM + 0U, // LOCGRAsmNO + 0U, // LOCGRAsmNP + 0U, // LOCGRAsmNZ + 0U, // LOCGRAsmO + 0U, // LOCGRAsmP + 0U, // LOCGRAsmZ + 0U, // LOCHHI + 0U, // LOCHHIAsm + 0U, // LOCHHIAsmE + 0U, // LOCHHIAsmH + 0U, // LOCHHIAsmHE + 0U, // LOCHHIAsmL + 0U, // LOCHHIAsmLE + 0U, // LOCHHIAsmLH + 0U, // LOCHHIAsmM + 0U, // LOCHHIAsmNE + 0U, // LOCHHIAsmNH + 0U, // LOCHHIAsmNHE + 0U, // LOCHHIAsmNL + 0U, // LOCHHIAsmNLE + 0U, // LOCHHIAsmNLH + 0U, // LOCHHIAsmNM + 0U, // LOCHHIAsmNO + 0U, // LOCHHIAsmNP + 0U, // LOCHHIAsmNZ + 0U, // LOCHHIAsmO + 0U, // LOCHHIAsmP + 0U, // LOCHHIAsmZ + 0U, // LOCHI + 0U, // LOCHIAsm + 0U, // LOCHIAsmE + 0U, // LOCHIAsmH + 0U, // LOCHIAsmHE + 0U, // LOCHIAsmL + 0U, // LOCHIAsmLE + 0U, // LOCHIAsmLH + 0U, // LOCHIAsmM + 0U, // LOCHIAsmNE + 0U, // LOCHIAsmNH + 0U, // LOCHIAsmNHE + 0U, // LOCHIAsmNL + 0U, // LOCHIAsmNLE + 0U, // LOCHIAsmNLH + 0U, // LOCHIAsmNM + 0U, // LOCHIAsmNO + 0U, // LOCHIAsmNP + 0U, // LOCHIAsmNZ + 0U, // LOCHIAsmO + 0U, // LOCHIAsmP + 0U, // LOCHIAsmZ + 0U, // LOCR + 0U, // LOCRAsm + 0U, // LOCRAsmE + 0U, // LOCRAsmH + 0U, // LOCRAsmHE + 0U, // LOCRAsmL + 0U, // LOCRAsmLE + 0U, // LOCRAsmLH + 0U, // LOCRAsmM + 0U, // LOCRAsmNE + 0U, // LOCRAsmNH + 0U, // LOCRAsmNHE + 0U, // LOCRAsmNL + 0U, // LOCRAsmNLE + 0U, // LOCRAsmNLH + 0U, // LOCRAsmNM + 0U, // LOCRAsmNO + 0U, // LOCRAsmNP + 0U, // LOCRAsmNZ + 0U, // LOCRAsmO + 0U, // LOCRAsmP + 0U, // LOCRAsmZ + 0U, // LPCTL + 0U, // LPD + 0U, // LPDBR + 0U, // LPDFR + 0U, // LPDFR_32 + 0U, // LPDG + 0U, // LPDR + 0U, // LPEBR + 0U, // LPER + 0U, // LPGFR + 0U, // LPGR + 0U, // LPP + 0U, // LPQ + 0U, // LPR + 0U, // LPSW + 0U, // LPSWE + 0U, // LPTEA + 0U, // LPXBR + 0U, // LPXR + 0U, // LR + 0U, // LRA + 0U, // LRAG + 0U, // LRAY + 0U, // LRDR + 0U, // LRER + 0U, // LRL + 0U, // LRV + 0U, // LRVG + 0U, // LRVGR + 0U, // LRVH + 0U, // LRVR + 0U, // LSCTL + 0U, // LT + 0U, // LTDBR + 0U, // LTDBRCompare + 0U, // LTDR + 0U, // LTDTR + 0U, // LTEBR + 0U, // LTEBRCompare + 0U, // LTER + 0U, // LTG + 0U, // LTGF + 0U, // LTGFR + 0U, // LTGR + 0U, // LTR + 0U, // LTXBR + 0U, // LTXBRCompare + 0U, // LTXR + 0U, // LTXTR + 0U, // LURA + 0U, // LURAG + 0U, // LXD + 0U, // LXDB + 0U, // LXDBR + 0U, // LXDR + 0U, // LXDTR + 0U, // LXE + 0U, // LXEB + 0U, // LXEBR + 0U, // LXER + 0U, // LXR + 0U, // LY + 0U, // LZDR + 0U, // LZER + 0U, // LZRF + 0U, // LZRG + 0U, // LZXR + 0U, // M + 0U, // MAD + 0U, // MADB + 0U, // MADBR + 0U, // MADR + 0U, // MAE + 0U, // MAEB + 0U, // MAEBR + 0U, // MAER + 0U, // MAY + 0U, // MAYH + 0U, // MAYHR + 0U, // MAYL + 0U, // MAYLR + 0U, // MAYR + 0U, // MC + 0U, // MD + 0U, // MDB + 0U, // MDBR + 0U, // MDE + 0U, // MDEB + 0U, // MDEBR + 0U, // MDER + 0U, // MDR + 0U, // MDTR + 0U, // MDTRA + 0U, // ME + 0U, // MEE + 0U, // MEEB + 0U, // MEEBR + 0U, // MEER + 0U, // MER + 0U, // MFY + 0U, // MG + 0U, // MGH + 0U, // MGHI + 0U, // MGRK + 0U, // MH + 0U, // MHI + 0U, // MHY + 0U, // ML + 0U, // MLG + 0U, // MLGR + 0U, // MLR + 0U, // MP + 0U, // MR + 0U, // MS + 0U, // MSC + 0U, // MSCH + 0U, // MSD + 0U, // MSDB + 0U, // MSDBR + 0U, // MSDR + 0U, // MSE + 0U, // MSEB + 0U, // MSEBR + 0U, // MSER + 0U, // MSFI + 0U, // MSG + 0U, // MSGC + 0U, // MSGF + 0U, // MSGFI + 0U, // MSGFR + 0U, // MSGR + 0U, // MSGRKC + 0U, // MSR + 0U, // MSRKC + 0U, // MSTA + 0U, // MSY + 0U, // MVC + 0U, // MVCDK + 0U, // MVCIN + 0U, // MVCK + 0U, // MVCL + 0U, // MVCLE + 0U, // MVCLU + 0U, // MVCOS + 0U, // MVCP + 0U, // MVCS + 0U, // MVCSK + 0U, // MVGHI + 0U, // MVHHI + 0U, // MVHI + 0U, // MVI + 0U, // MVIY + 0U, // MVN + 0U, // MVO + 0U, // MVPG + 0U, // MVST + 0U, // MVZ + 0U, // MXBR + 0U, // MXD + 0U, // MXDB + 0U, // MXDBR + 0U, // MXDR + 0U, // MXR + 0U, // MXTR + 0U, // MXTRA + 0U, // MY + 0U, // MYH + 0U, // MYHR + 0U, // MYL + 0U, // MYLR + 0U, // MYR + 0U, // N + 0U, // NC + 0U, // NG + 0U, // NGR + 0U, // NGRK + 0U, // NI + 0U, // NIAI + 0U, // NIHF + 0U, // NIHH + 0U, // NIHL + 0U, // NILF + 0U, // NILH + 0U, // NILL + 0U, // NIY + 0U, // NR + 0U, // NRK + 0U, // NTSTG + 0U, // NY + 0U, // O + 0U, // OC + 0U, // OG + 0U, // OGR + 0U, // OGRK + 0U, // OI + 0U, // OIHF + 0U, // OIHH + 0U, // OIHL + 0U, // OILF + 0U, // OILH + 0U, // OILL + 0U, // OIY + 0U, // OR + 0U, // ORK + 0U, // OY + 0U, // PACK + 0U, // PALB + 0U, // PC + 0U, // PCC + 0U, // PCKMO + 0U, // PFD + 0U, // PFDRL + 0U, // PFMF + 0U, // PFPO + 0U, // PGIN + 0U, // PGOUT + 0U, // PKA + 0U, // PKU + 0U, // PLO + 0U, // POPCNT + 0U, // PPA + 0U, // PPNO + 0U, // PR + 0U, // PRNO + 0U, // PT + 0U, // PTF + 0U, // PTFF + 0U, // PTI + 0U, // PTLB + 0U, // QADTR + 0U, // QAXTR + 0U, // QCTRI + 0U, // QSI + 0U, // RCHP + 2U, // RISBG + 2U, // RISBG32 + 2U, // RISBGN + 2U, // RISBHG + 2U, // RISBLG + 0U, // RLL + 0U, // RLLG + 2U, // RNSBG + 2U, // ROSBG + 0U, // RP + 0U, // RRBE + 0U, // RRBM + 0U, // RRDTR + 0U, // RRXTR + 0U, // RSCH + 2U, // RXSBG + 0U, // S + 0U, // SAC + 0U, // SACF + 0U, // SAL + 0U, // SAM24 + 0U, // SAM31 + 0U, // SAM64 + 0U, // SAR + 0U, // SCCTR + 0U, // SCHM + 0U, // SCK + 0U, // SCKC + 0U, // SCKPF + 0U, // SD + 0U, // SDB + 0U, // SDBR + 0U, // SDR + 0U, // SDTR + 0U, // SDTRA + 0U, // SE + 0U, // SEB + 0U, // SEBR + 0U, // SER + 0U, // SFASR + 0U, // SFPC + 0U, // SG + 0U, // SGF + 0U, // SGFR + 0U, // SGH + 0U, // SGR + 0U, // SGRK + 0U, // SH + 0U, // SHHHR + 0U, // SHHLR + 0U, // SHY + 0U, // SIE + 0U, // SIGA + 0U, // SIGP + 0U, // SL + 0U, // SLA + 0U, // SLAG + 0U, // SLAK + 0U, // SLB + 0U, // SLBG + 0U, // SLBGR + 0U, // SLBR + 0U, // SLDA + 0U, // SLDL + 0U, // SLDT + 0U, // SLFI + 0U, // SLG + 0U, // SLGF + 0U, // SLGFI + 0U, // SLGFR + 0U, // SLGR + 0U, // SLGRK + 0U, // SLHHHR + 0U, // SLHHLR + 0U, // SLL + 0U, // SLLG + 0U, // SLLK + 0U, // SLR + 0U, // SLRK + 0U, // SLXT + 0U, // SLY + 0U, // SP + 0U, // SPCTR + 0U, // SPKA + 0U, // SPM + 0U, // SPT + 0U, // SPX + 0U, // SQD + 0U, // SQDB + 0U, // SQDBR + 0U, // SQDR + 0U, // SQE + 0U, // SQEB + 0U, // SQEBR + 0U, // SQER + 0U, // SQXBR + 0U, // SQXR + 0U, // SR + 0U, // SRA + 0U, // SRAG + 0U, // SRAK + 0U, // SRDA + 0U, // SRDL + 0U, // SRDT + 0U, // SRK + 0U, // SRL + 0U, // SRLG + 0U, // SRLK + 0U, // SRNM + 0U, // SRNMB + 0U, // SRNMT + 0U, // SRP + 0U, // SRST + 0U, // SRSTU + 0U, // SRXT + 0U, // SSAIR + 0U, // SSAR + 0U, // SSCH + 0U, // SSKE + 0U, // SSKEOpt + 0U, // SSM + 0U, // ST + 0U, // STAM + 0U, // STAMY + 0U, // STAP + 0U, // STC + 0U, // STCH + 0U, // STCK + 0U, // STCKC + 0U, // STCKE + 0U, // STCKF + 0U, // STCM + 0U, // STCMH + 0U, // STCMY + 0U, // STCPS + 0U, // STCRW + 0U, // STCTG + 0U, // STCTL + 0U, // STCY + 0U, // STD + 0U, // STDY + 0U, // STE + 0U, // STEY + 0U, // STFH + 0U, // STFL + 0U, // STFLE + 0U, // STFPC + 0U, // STG + 0U, // STGRL + 0U, // STGSC + 0U, // STH + 0U, // STHH + 0U, // STHRL + 0U, // STHY + 0U, // STIDP + 0U, // STM + 0U, // STMG + 0U, // STMH + 0U, // STMY + 0U, // STNSM + 0U, // STOC + 0U, // STOCAsm + 0U, // STOCAsmE + 0U, // STOCAsmH + 0U, // STOCAsmHE + 0U, // STOCAsmL + 0U, // STOCAsmLE + 0U, // STOCAsmLH + 0U, // STOCAsmM + 0U, // STOCAsmNE + 0U, // STOCAsmNH + 0U, // STOCAsmNHE + 0U, // STOCAsmNL + 0U, // STOCAsmNLE + 0U, // STOCAsmNLH + 0U, // STOCAsmNM + 0U, // STOCAsmNO + 0U, // STOCAsmNP + 0U, // STOCAsmNZ + 0U, // STOCAsmO + 0U, // STOCAsmP + 0U, // STOCAsmZ + 0U, // STOCFH + 0U, // STOCFHAsm + 0U, // STOCFHAsmE + 0U, // STOCFHAsmH + 0U, // STOCFHAsmHE + 0U, // STOCFHAsmL + 0U, // STOCFHAsmLE + 0U, // STOCFHAsmLH + 0U, // STOCFHAsmM + 0U, // STOCFHAsmNE + 0U, // STOCFHAsmNH + 0U, // STOCFHAsmNHE + 0U, // STOCFHAsmNL + 0U, // STOCFHAsmNLE + 0U, // STOCFHAsmNLH + 0U, // STOCFHAsmNM + 0U, // STOCFHAsmNO + 0U, // STOCFHAsmNP + 0U, // STOCFHAsmNZ + 0U, // STOCFHAsmO + 0U, // STOCFHAsmP + 0U, // STOCFHAsmZ + 0U, // STOCG + 0U, // STOCGAsm + 0U, // STOCGAsmE + 0U, // STOCGAsmH + 0U, // STOCGAsmHE + 0U, // STOCGAsmL + 0U, // STOCGAsmLE + 0U, // STOCGAsmLH + 0U, // STOCGAsmM + 0U, // STOCGAsmNE + 0U, // STOCGAsmNH + 0U, // STOCGAsmNHE + 0U, // STOCGAsmNL + 0U, // STOCGAsmNLE + 0U, // STOCGAsmNLH + 0U, // STOCGAsmNM + 0U, // STOCGAsmNO + 0U, // STOCGAsmNP + 0U, // STOCGAsmNZ + 0U, // STOCGAsmO + 0U, // STOCGAsmP + 0U, // STOCGAsmZ + 0U, // STOSM + 0U, // STPQ + 0U, // STPT + 0U, // STPX + 0U, // STRAG + 0U, // STRL + 0U, // STRV + 0U, // STRVG + 0U, // STRVH + 0U, // STSCH + 0U, // STSI + 0U, // STURA + 0U, // STURG + 0U, // STY + 0U, // SU + 0U, // SUR + 0U, // SVC + 0U, // SW + 0U, // SWR + 0U, // SXBR + 0U, // SXR + 0U, // SXTR + 0U, // SXTRA + 0U, // SY + 0U, // TABORT + 0U, // TAM + 0U, // TAR + 0U, // TB + 0U, // TBDR + 0U, // TBEDR + 0U, // TBEGIN + 0U, // TBEGINC + 0U, // TCDB + 0U, // TCEB + 0U, // TCXB + 0U, // TDCDT + 0U, // TDCET + 0U, // TDCXT + 0U, // TDGDT + 0U, // TDGET + 0U, // TDGXT + 0U, // TEND + 0U, // THDER + 0U, // THDR + 0U, // TM + 0U, // TMHH + 0U, // TMHL + 0U, // TMLH + 0U, // TMLL + 0U, // TMY + 0U, // TP + 0U, // TPI + 0U, // TPROT + 0U, // TR + 0U, // TRACE + 0U, // TRACG + 0U, // TRAP2 + 0U, // TRAP4 + 0U, // TRE + 0U, // TROO + 0U, // TROOOpt + 0U, // TROT + 0U, // TROTOpt + 0U, // TRT + 0U, // TRTE + 0U, // TRTEOpt + 0U, // TRTO + 0U, // TRTOOpt + 0U, // TRTR + 0U, // TRTRE + 0U, // TRTREOpt + 0U, // TRTT + 0U, // TRTTOpt + 0U, // TS + 0U, // TSCH + 0U, // UNPK + 0U, // UNPKA + 0U, // UNPKU + 0U, // UPT + 0U, // VA + 0U, // VAB + 6U, // VAC + 0U, // VACC + 0U, // VACCB + 6U, // VACCC + 0U, // VACCCQ + 0U, // VACCF + 0U, // VACCG + 0U, // VACCH + 0U, // VACCQ + 0U, // VACQ + 0U, // VAF + 0U, // VAG + 0U, // VAH + 7U, // VAP + 0U, // VAQ + 0U, // VAVG + 0U, // VAVGB + 0U, // VAVGF + 0U, // VAVGG + 0U, // VAVGH + 0U, // VAVGL + 0U, // VAVGLB + 0U, // VAVGLF + 0U, // VAVGLG + 0U, // VAVGLH + 0U, // VBPERM + 6U, // VCDG + 0U, // VCDGB + 6U, // VCDLG + 0U, // VCDLGB + 6U, // VCEQ + 0U, // VCEQB + 0U, // VCEQBS + 0U, // VCEQF + 0U, // VCEQFS + 0U, // VCEQG + 0U, // VCEQGS + 0U, // VCEQH + 0U, // VCEQHS + 6U, // VCGD + 0U, // VCGDB + 6U, // VCH + 0U, // VCHB + 0U, // VCHBS + 0U, // VCHF + 0U, // VCHFS + 0U, // VCHG + 0U, // VCHGS + 0U, // VCHH + 0U, // VCHHS + 6U, // VCHL + 0U, // VCHLB + 0U, // VCHLBS + 0U, // VCHLF + 0U, // VCHLFS + 0U, // VCHLG + 0U, // VCHLGS + 0U, // VCHLH + 0U, // VCHLHS + 0U, // VCKSM + 6U, // VCLGD + 0U, // VCLGDB + 0U, // VCLZ + 0U, // VCLZB + 0U, // VCLZF + 0U, // VCLZG + 0U, // VCLZH + 0U, // VCP + 0U, // VCTZ + 0U, // VCTZB + 0U, // VCTZF + 0U, // VCTZG + 0U, // VCTZH + 0U, // VCVB + 0U, // VCVBG + 1U, // VCVD + 1U, // VCVDG + 7U, // VDP + 0U, // VEC + 0U, // VECB + 0U, // VECF + 0U, // VECG + 0U, // VECH + 0U, // VECL + 0U, // VECLB + 0U, // VECLF + 0U, // VECLG + 0U, // VECLH + 10U, // VERIM + 0U, // VERIMB + 0U, // VERIMF + 0U, // VERIMG + 0U, // VERIMH + 0U, // VERLL + 0U, // VERLLB + 0U, // VERLLF + 0U, // VERLLG + 0U, // VERLLH + 0U, // VERLLV + 0U, // VERLLVB + 0U, // VERLLVF + 0U, // VERLLVG + 0U, // VERLLVH + 0U, // VESL + 0U, // VESLB + 0U, // VESLF + 0U, // VESLG + 0U, // VESLH + 0U, // VESLV + 0U, // VESLVB + 0U, // VESLVF + 0U, // VESLVG + 0U, // VESLVH + 0U, // VESRA + 0U, // VESRAB + 0U, // VESRAF + 0U, // VESRAG + 0U, // VESRAH + 0U, // VESRAV + 0U, // VESRAVB + 0U, // VESRAVF + 0U, // VESRAVG + 0U, // VESRAVH + 0U, // VESRL + 0U, // VESRLB + 0U, // VESRLF + 0U, // VESRLG + 0U, // VESRLH + 0U, // VESRLV + 0U, // VESRLVB + 0U, // VESRLVF + 0U, // VESRLVG + 0U, // VESRLVH + 6U, // VFA + 0U, // VFADB + 6U, // VFAE + 0U, // VFAEB + 0U, // VFAEBS + 0U, // VFAEF + 0U, // VFAEFS + 0U, // VFAEH + 0U, // VFAEHS + 0U, // VFAEZB + 0U, // VFAEZBS + 0U, // VFAEZF + 0U, // VFAEZFS + 0U, // VFAEZH + 0U, // VFAEZHS + 0U, // VFASB + 22U, // VFCE + 0U, // VFCEDB + 0U, // VFCEDBS + 0U, // VFCESB + 0U, // VFCESBS + 22U, // VFCH + 0U, // VFCHDB + 0U, // VFCHDBS + 22U, // VFCHE + 0U, // VFCHEDB + 0U, // VFCHEDBS + 0U, // VFCHESB + 0U, // VFCHESBS + 0U, // VFCHSB + 0U, // VFCHSBS + 6U, // VFD + 0U, // VFDDB + 0U, // VFDSB + 6U, // VFEE + 0U, // VFEEB + 0U, // VFEEBS + 0U, // VFEEF + 0U, // VFEEFS + 0U, // VFEEH + 0U, // VFEEHS + 0U, // VFEEZB + 0U, // VFEEZBS + 0U, // VFEEZF + 0U, // VFEEZFS + 0U, // VFEEZH + 0U, // VFEEZHS + 6U, // VFENE + 0U, // VFENEB + 0U, // VFENEBS + 0U, // VFENEF + 0U, // VFENEFS + 0U, // VFENEH + 0U, // VFENEHS + 0U, // VFENEZB + 0U, // VFENEZBS + 0U, // VFENEZF + 0U, // VFENEZFS + 0U, // VFENEZH + 0U, // VFENEZHS + 6U, // VFI + 0U, // VFIDB + 0U, // VFISB + 0U, // VFKEDB + 0U, // VFKEDBS + 0U, // VFKESB + 0U, // VFKESBS + 0U, // VFKHDB + 0U, // VFKHDBS + 0U, // VFKHEDB + 0U, // VFKHEDBS + 0U, // VFKHESB + 0U, // VFKHESBS + 0U, // VFKHSB + 0U, // VFKHSBS + 0U, // VFLCDB + 0U, // VFLCSB + 0U, // VFLL + 0U, // VFLLS + 0U, // VFLNDB + 0U, // VFLNSB + 0U, // VFLPDB + 0U, // VFLPSB + 6U, // VFLR + 0U, // VFLRD + 6U, // VFM + 22U, // VFMA + 0U, // VFMADB + 0U, // VFMASB + 22U, // VFMAX + 0U, // VFMAXDB + 0U, // VFMAXSB + 0U, // VFMDB + 22U, // VFMIN + 0U, // VFMINDB + 0U, // VFMINSB + 22U, // VFMS + 0U, // VFMSB + 0U, // VFMSDB + 0U, // VFMSSB + 22U, // VFNMA + 0U, // VFNMADB + 0U, // VFNMASB + 22U, // VFNMS + 0U, // VFNMSDB + 0U, // VFNMSSB + 6U, // VFPSO + 0U, // VFPSODB + 0U, // VFPSOSB + 6U, // VFS + 0U, // VFSDB + 0U, // VFSQ + 0U, // VFSQDB + 0U, // VFSQSB + 0U, // VFSSB + 6U, // VFTCI + 0U, // VFTCIDB + 0U, // VFTCISB + 0U, // VGBM + 0U, // VGEF + 0U, // VGEG + 0U, // VGFM + 6U, // VGFMA + 0U, // VGFMAB + 0U, // VGFMAF + 0U, // VGFMAG + 0U, // VGFMAH + 0U, // VGFMB + 0U, // VGFMF + 0U, // VGFMG + 0U, // VGFMH + 0U, // VGM + 0U, // VGMB + 0U, // VGMF + 0U, // VGMG + 0U, // VGMH + 0U, // VISTR + 0U, // VISTRB + 0U, // VISTRBS + 0U, // VISTRF + 0U, // VISTRFS + 0U, // VISTRH + 0U, // VISTRHS + 0U, // VL + 0U, // VLBB + 0U, // VLC + 0U, // VLCB + 0U, // VLCF + 0U, // VLCG + 0U, // VLCH + 0U, // VLDE + 0U, // VLDEB + 0U, // VLEB + 6U, // VLED + 0U, // VLEDB + 0U, // VLEF + 0U, // VLEG + 0U, // VLEH + 0U, // VLEIB + 0U, // VLEIF + 0U, // VLEIG + 0U, // VLEIH + 0U, // VLGV + 0U, // VLGVB + 0U, // VLGVF + 0U, // VLGVG + 0U, // VLGVH + 0U, // VLIP + 0U, // VLL + 0U, // VLLEZ + 0U, // VLLEZB + 0U, // VLLEZF + 0U, // VLLEZG + 0U, // VLLEZH + 0U, // VLLEZLF + 0U, // VLM + 0U, // VLP + 0U, // VLPB + 0U, // VLPF + 0U, // VLPG + 0U, // VLPH + 0U, // VLR + 0U, // VLREP + 0U, // VLREPB + 0U, // VLREPF + 0U, // VLREPG + 0U, // VLREPH + 0U, // VLRL + 0U, // VLRLR + 1U, // VLVG + 0U, // VLVGB + 0U, // VLVGF + 0U, // VLVGG + 0U, // VLVGH + 0U, // VLVGP + 6U, // VMAE + 0U, // VMAEB + 0U, // VMAEF + 0U, // VMAEH + 6U, // VMAH + 0U, // VMAHB + 0U, // VMAHF + 0U, // VMAHH + 6U, // VMAL + 0U, // VMALB + 6U, // VMALE + 0U, // VMALEB + 0U, // VMALEF + 0U, // VMALEH + 0U, // VMALF + 6U, // VMALH + 0U, // VMALHB + 0U, // VMALHF + 0U, // VMALHH + 0U, // VMALHW + 6U, // VMALO + 0U, // VMALOB + 0U, // VMALOF + 0U, // VMALOH + 6U, // VMAO + 0U, // VMAOB + 0U, // VMAOF + 0U, // VMAOH + 0U, // VME + 0U, // VMEB + 0U, // VMEF + 0U, // VMEH + 0U, // VMH + 0U, // VMHB + 0U, // VMHF + 0U, // VMHH + 0U, // VML + 0U, // VMLB + 0U, // VMLE + 0U, // VMLEB + 0U, // VMLEF + 0U, // VMLEH + 0U, // VMLF + 0U, // VMLH + 0U, // VMLHB + 0U, // VMLHF + 0U, // VMLHH + 0U, // VMLHW + 0U, // VMLO + 0U, // VMLOB + 0U, // VMLOF + 0U, // VMLOH + 0U, // VMN + 0U, // VMNB + 0U, // VMNF + 0U, // VMNG + 0U, // VMNH + 0U, // VMNL + 0U, // VMNLB + 0U, // VMNLF + 0U, // VMNLG + 0U, // VMNLH + 0U, // VMO + 0U, // VMOB + 0U, // VMOF + 0U, // VMOH + 7U, // VMP + 0U, // VMRH + 0U, // VMRHB + 0U, // VMRHF + 0U, // VMRHG + 0U, // VMRHH + 0U, // VMRL + 0U, // VMRLB + 0U, // VMRLF + 0U, // VMRLG + 0U, // VMRLH + 22U, // VMSL + 6U, // VMSLG + 7U, // VMSP + 0U, // VMX + 0U, // VMXB + 0U, // VMXF + 0U, // VMXG + 0U, // VMXH + 0U, // VMXL + 0U, // VMXLB + 0U, // VMXLF + 0U, // VMXLG + 0U, // VMXLH + 0U, // VN + 0U, // VNC + 0U, // VNN + 0U, // VNO + 0U, // VNX + 0U, // VO + 0U, // VOC + 0U, // VONE + 0U, // VPDI + 0U, // VPERM + 0U, // VPK + 0U, // VPKF + 0U, // VPKG + 0U, // VPKH + 6U, // VPKLS + 0U, // VPKLSF + 0U, // VPKLSFS + 0U, // VPKLSG + 0U, // VPKLSGS + 0U, // VPKLSH + 0U, // VPKLSHS + 6U, // VPKS + 0U, // VPKSF + 0U, // VPKSFS + 0U, // VPKSG + 0U, // VPKSGS + 0U, // VPKSH + 0U, // VPKSHS + 0U, // VPKZ + 0U, // VPOPCT + 0U, // VPOPCTB + 0U, // VPOPCTF + 0U, // VPOPCTG + 0U, // VPOPCTH + 0U, // VPSOP + 0U, // VREP + 0U, // VREPB + 0U, // VREPF + 0U, // VREPG + 0U, // VREPH + 0U, // VREPI + 0U, // VREPIB + 0U, // VREPIF + 0U, // VREPIG + 0U, // VREPIH + 7U, // VRP + 0U, // VS + 0U, // VSB + 6U, // VSBCBI + 0U, // VSBCBIQ + 6U, // VSBI + 0U, // VSBIQ + 0U, // VSCBI + 0U, // VSCBIB + 0U, // VSCBIF + 0U, // VSCBIG + 0U, // VSCBIH + 0U, // VSCBIQ + 0U, // VSCEF + 0U, // VSCEG + 7U, // VSDP + 0U, // VSEG + 0U, // VSEGB + 0U, // VSEGF + 0U, // VSEGH + 0U, // VSEL + 0U, // VSF + 0U, // VSG + 0U, // VSH + 0U, // VSL + 0U, // VSLB + 1U, // VSLDB + 7U, // VSP + 0U, // VSQ + 0U, // VSRA + 0U, // VSRAB + 0U, // VSRL + 0U, // VSRLB + 0U, // VSRP + 0U, // VST + 0U, // VSTEB + 0U, // VSTEF + 0U, // VSTEG + 0U, // VSTEH + 0U, // VSTL + 0U, // VSTM + 22U, // VSTRC + 6U, // VSTRCB + 6U, // VSTRCBS + 6U, // VSTRCF + 6U, // VSTRCFS + 6U, // VSTRCH + 6U, // VSTRCHS + 6U, // VSTRCZB + 6U, // VSTRCZBS + 6U, // VSTRCZF + 6U, // VSTRCZFS + 6U, // VSTRCZH + 6U, // VSTRCZHS + 0U, // VSTRL + 0U, // VSTRLR + 0U, // VSUM + 0U, // VSUMB + 0U, // VSUMG + 0U, // VSUMGF + 0U, // VSUMGH + 0U, // VSUMH + 0U, // VSUMQ + 0U, // VSUMQF + 0U, // VSUMQG + 0U, // VTM + 0U, // VTP + 0U, // VUPH + 0U, // VUPHB + 0U, // VUPHF + 0U, // VUPHH + 0U, // VUPKZ + 0U, // VUPL + 0U, // VUPLB + 0U, // VUPLF + 0U, // VUPLH + 0U, // VUPLHB + 0U, // VUPLHF + 0U, // VUPLHH + 0U, // VUPLHW + 0U, // VUPLL + 0U, // VUPLLB + 0U, // VUPLLF + 0U, // VUPLLH + 0U, // VX + 0U, // VZERO + 0U, // WCDGB + 0U, // WCDLGB + 0U, // WCGDB + 0U, // WCLGDB + 0U, // WFADB + 0U, // WFASB + 0U, // WFAXB + 0U, // WFC + 0U, // WFCDB + 0U, // WFCEDB + 0U, // WFCEDBS + 0U, // WFCESB + 0U, // WFCESBS + 0U, // WFCEXB + 0U, // WFCEXBS + 0U, // WFCHDB + 0U, // WFCHDBS + 0U, // WFCHEDB + 0U, // WFCHEDBS + 0U, // WFCHESB + 0U, // WFCHESBS + 0U, // WFCHEXB + 0U, // WFCHEXBS + 0U, // WFCHSB + 0U, // WFCHSBS + 0U, // WFCHXB + 0U, // WFCHXBS + 0U, // WFCSB + 0U, // WFCXB + 0U, // WFDDB + 0U, // WFDSB + 0U, // WFDXB + 0U, // WFIDB + 0U, // WFISB + 0U, // WFIXB + 0U, // WFK + 0U, // WFKDB + 0U, // WFKEDB + 0U, // WFKEDBS + 0U, // WFKESB + 0U, // WFKESBS + 0U, // WFKEXB + 0U, // WFKEXBS + 0U, // WFKHDB + 0U, // WFKHDBS + 0U, // WFKHEDB + 0U, // WFKHEDBS + 0U, // WFKHESB + 0U, // WFKHESBS + 0U, // WFKHEXB + 0U, // WFKHEXBS + 0U, // WFKHSB + 0U, // WFKHSBS + 0U, // WFKHXB + 0U, // WFKHXBS + 0U, // WFKSB + 0U, // WFKXB + 0U, // WFLCDB + 0U, // WFLCSB + 0U, // WFLCXB + 0U, // WFLLD + 0U, // WFLLS + 0U, // WFLNDB + 0U, // WFLNSB + 0U, // WFLNXB + 0U, // WFLPDB + 0U, // WFLPSB + 0U, // WFLPXB + 0U, // WFLRD + 0U, // WFLRX + 0U, // WFMADB + 0U, // WFMASB + 0U, // WFMAXB + 0U, // WFMAXDB + 0U, // WFMAXSB + 0U, // WFMAXXB + 0U, // WFMDB + 0U, // WFMINDB + 0U, // WFMINSB + 0U, // WFMINXB + 0U, // WFMSB + 0U, // WFMSDB + 0U, // WFMSSB + 0U, // WFMSXB + 0U, // WFMXB + 0U, // WFNMADB + 0U, // WFNMASB + 0U, // WFNMAXB + 0U, // WFNMSDB + 0U, // WFNMSSB + 0U, // WFNMSXB + 0U, // WFPSODB + 0U, // WFPSOSB + 0U, // WFPSOXB + 0U, // WFSDB + 0U, // WFSQDB + 0U, // WFSQSB + 0U, // WFSQXB + 0U, // WFSSB + 0U, // WFSXB + 0U, // WFTCIDB + 0U, // WFTCISB + 0U, // WFTCIXB + 0U, // WLDEB + 0U, // WLEDB + 0U, // X + 0U, // XC + 0U, // XG + 0U, // XGR + 0U, // XGRK + 0U, // XI + 0U, // XIHF + 0U, // XILF + 0U, // XIY + 0U, // XR + 0U, // XRK + 0U, // XSCH + 0U, // XY + 0U, // ZAP }; // Emit the opcode for the instruction. @@ -10640,10 +24149,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) Bits |= (uint64_t)OpInfo2[MCInst_getOpcode(MI)] << 48; // assert(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 16383)-1); + SStream_concat0(O, AsmStrs + (Bits & 16383) - 1); #endif - // Fragment 0 encoded into 5 bits for 18 unique commands. // printf("Fragment 0 = %" PRIu64 "\n", (Bits >> 14) & 31); switch ((Bits >> 14) & 31) { @@ -10751,7 +24259,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 1 encoded into 5 bits for 17 unique commands. // printf("Fragment 1 = %" PRIu64 "\n", (Bits >> 19) & 31); switch ((Bits >> 19) & 31) { @@ -10845,7 +24352,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 2 encoded into 6 bits for 34 unique commands. // printf("Fragment 2 = %" PRIu64 "\n", (Bits >> 24) & 63); switch ((Bits >> 24) & 63) { @@ -11012,7 +24518,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 3 encoded into 5 bits for 20 unique commands. // printf("Fragment 3 = %" PRIu64 "\n", (Bits >> 30) & 31); switch ((Bits >> 30) & 31) { @@ -11118,7 +24623,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 4 encoded into 6 bits for 33 unique commands. // printf("Fragment 4 = %" PRIu64 "\n", (Bits >> 35) & 63); switch ((Bits >> 35) & 63) { @@ -11280,7 +24784,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 5 encoded into 4 bits for 9 unique commands. // printf("Fragment 5 = %" PRIu64 "\n", (Bits >> 41) & 15); switch ((Bits >> 41) & 15) { @@ -11333,7 +24836,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 6 encoded into 4 bits for 11 unique commands. // printf("Fragment 6 = %" PRIu64 "\n", (Bits >> 45) & 15); switch ((Bits >> 45) & 15) { @@ -11391,7 +24893,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 7 encoded into 1 bits for 2 unique commands. // printf("Fragment 7 = %" PRIu64 "\n", (Bits >> 49) & 1); if ((Bits >> 49) & 1) { @@ -11402,7 +24903,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) return; } - // Fragment 8 encoded into 2 bits for 3 unique commands. // printf("Fragment 8 = %" PRIu64 "\n", (Bits >> 50) & 3); switch ((Bits >> 50) & 3) { @@ -11423,7 +24923,6 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 9 encoded into 1 bits for 2 unique commands. // printf("Fragment 9 = %" PRIu64 "\n", (Bits >> 52) & 1); if ((Bits >> 52) & 1) { @@ -11435,140 +24934,136 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCGD, VCH, VCHL, VCLGD, VDP, VFA, ... return; } - } - /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static const char *getRegisterName(unsigned RegNo) -{ +static const char *getRegisterName(unsigned RegNo) { // assert(RegNo && RegNo < 194 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'a', '1', '0', 0, - /* 4 */ 'c', '1', '0', 0, - /* 8 */ 'f', '1', '0', 0, - /* 12 */ 'r', '1', '0', 0, - /* 16 */ 'v', '1', '0', 0, - /* 20 */ 'v', '2', '0', 0, - /* 24 */ 'v', '3', '0', 0, - /* 28 */ 'a', '0', 0, - /* 31 */ 'c', '0', 0, - /* 34 */ 'f', '0', 0, - /* 37 */ 'r', '0', 0, - /* 40 */ 'v', '0', 0, - /* 43 */ 'a', '1', '1', 0, - /* 47 */ 'c', '1', '1', 0, - /* 51 */ 'f', '1', '1', 0, - /* 55 */ 'r', '1', '1', 0, - /* 59 */ 'v', '1', '1', 0, - /* 63 */ 'v', '2', '1', 0, - /* 67 */ 'v', '3', '1', 0, - /* 71 */ 'a', '1', 0, - /* 74 */ 'c', '1', 0, - /* 77 */ 'f', '1', 0, - /* 80 */ 'r', '1', 0, - /* 83 */ 'v', '1', 0, - /* 86 */ 'a', '1', '2', 0, - /* 90 */ 'c', '1', '2', 0, - /* 94 */ 'f', '1', '2', 0, - /* 98 */ 'r', '1', '2', 0, - /* 102 */ 'v', '1', '2', 0, - /* 106 */ 'v', '2', '2', 0, - /* 110 */ 'a', '2', 0, - /* 113 */ 'c', '2', 0, - /* 116 */ 'f', '2', 0, - /* 119 */ 'r', '2', 0, - /* 122 */ 'v', '2', 0, - /* 125 */ 'a', '1', '3', 0, - /* 129 */ 'c', '1', '3', 0, - /* 133 */ 'f', '1', '3', 0, - /* 137 */ 'r', '1', '3', 0, - /* 141 */ 'v', '1', '3', 0, - /* 145 */ 'v', '2', '3', 0, - /* 149 */ 'a', '3', 0, - /* 152 */ 'c', '3', 0, - /* 155 */ 'f', '3', 0, - /* 158 */ 'r', '3', 0, - /* 161 */ 'v', '3', 0, - /* 164 */ 'a', '1', '4', 0, - /* 168 */ 'c', '1', '4', 0, - /* 172 */ 'f', '1', '4', 0, - /* 176 */ 'r', '1', '4', 0, - /* 180 */ 'v', '1', '4', 0, - /* 184 */ 'v', '2', '4', 0, - /* 188 */ 'a', '4', 0, - /* 191 */ 'c', '4', 0, - /* 194 */ 'f', '4', 0, - /* 197 */ 'r', '4', 0, - /* 200 */ 'v', '4', 0, - /* 203 */ 'a', '1', '5', 0, - /* 207 */ 'c', '1', '5', 0, - /* 211 */ 'f', '1', '5', 0, - /* 215 */ 'r', '1', '5', 0, - /* 219 */ 'v', '1', '5', 0, - /* 223 */ 'v', '2', '5', 0, - /* 227 */ 'a', '5', 0, - /* 230 */ 'c', '5', 0, - /* 233 */ 'f', '5', 0, - /* 236 */ 'r', '5', 0, - /* 239 */ 'v', '5', 0, - /* 242 */ 'v', '1', '6', 0, - /* 246 */ 'v', '2', '6', 0, - /* 250 */ 'a', '6', 0, - /* 253 */ 'c', '6', 0, - /* 256 */ 'f', '6', 0, - /* 259 */ 'r', '6', 0, - /* 262 */ 'v', '6', 0, - /* 265 */ 'v', '1', '7', 0, - /* 269 */ 'v', '2', '7', 0, - /* 273 */ 'a', '7', 0, - /* 276 */ 'c', '7', 0, - /* 279 */ 'f', '7', 0, - /* 282 */ 'r', '7', 0, - /* 285 */ 'v', '7', 0, - /* 288 */ 'v', '1', '8', 0, - /* 292 */ 'v', '2', '8', 0, - /* 296 */ 'a', '8', 0, - /* 299 */ 'c', '8', 0, - /* 302 */ 'f', '8', 0, - /* 305 */ 'r', '8', 0, - /* 308 */ 'v', '8', 0, - /* 311 */ 'v', '1', '9', 0, - /* 315 */ 'v', '2', '9', 0, - /* 319 */ 'a', '9', 0, - /* 322 */ 'c', '9', 0, - /* 325 */ 'f', '9', 0, - /* 328 */ 'r', '9', 0, - /* 331 */ 'v', '9', 0, - /* 334 */ 'c', 'c', 0, + /* 0 */ 'a', '1', '0', 0, + /* 4 */ 'c', '1', '0', 0, + /* 8 */ 'f', '1', '0', 0, + /* 12 */ 'r', '1', '0', 0, + /* 16 */ 'v', '1', '0', 0, + /* 20 */ 'v', '2', '0', 0, + /* 24 */ 'v', '3', '0', 0, + /* 28 */ 'a', '0', 0, + /* 31 */ 'c', '0', 0, + /* 34 */ 'f', '0', 0, + /* 37 */ 'r', '0', 0, + /* 40 */ 'v', '0', 0, + /* 43 */ 'a', '1', '1', 0, + /* 47 */ 'c', '1', '1', 0, + /* 51 */ 'f', '1', '1', 0, + /* 55 */ 'r', '1', '1', 0, + /* 59 */ 'v', '1', '1', 0, + /* 63 */ 'v', '2', '1', 0, + /* 67 */ 'v', '3', '1', 0, + /* 71 */ 'a', '1', 0, + /* 74 */ 'c', '1', 0, + /* 77 */ 'f', '1', 0, + /* 80 */ 'r', '1', 0, + /* 83 */ 'v', '1', 0, + /* 86 */ 'a', '1', '2', 0, + /* 90 */ 'c', '1', '2', 0, + /* 94 */ 'f', '1', '2', 0, + /* 98 */ 'r', '1', '2', 0, + /* 102 */ 'v', '1', '2', 0, + /* 106 */ 'v', '2', '2', 0, + /* 110 */ 'a', '2', 0, + /* 113 */ 'c', '2', 0, + /* 116 */ 'f', '2', 0, + /* 119 */ 'r', '2', 0, + /* 122 */ 'v', '2', 0, + /* 125 */ 'a', '1', '3', 0, + /* 129 */ 'c', '1', '3', 0, + /* 133 */ 'f', '1', '3', 0, + /* 137 */ 'r', '1', '3', 0, + /* 141 */ 'v', '1', '3', 0, + /* 145 */ 'v', '2', '3', 0, + /* 149 */ 'a', '3', 0, + /* 152 */ 'c', '3', 0, + /* 155 */ 'f', '3', 0, + /* 158 */ 'r', '3', 0, + /* 161 */ 'v', '3', 0, + /* 164 */ 'a', '1', '4', 0, + /* 168 */ 'c', '1', '4', 0, + /* 172 */ 'f', '1', '4', 0, + /* 176 */ 'r', '1', '4', 0, + /* 180 */ 'v', '1', '4', 0, + /* 184 */ 'v', '2', '4', 0, + /* 188 */ 'a', '4', 0, + /* 191 */ 'c', '4', 0, + /* 194 */ 'f', '4', 0, + /* 197 */ 'r', '4', 0, + /* 200 */ 'v', '4', 0, + /* 203 */ 'a', '1', '5', 0, + /* 207 */ 'c', '1', '5', 0, + /* 211 */ 'f', '1', '5', 0, + /* 215 */ 'r', '1', '5', 0, + /* 219 */ 'v', '1', '5', 0, + /* 223 */ 'v', '2', '5', 0, + /* 227 */ 'a', '5', 0, + /* 230 */ 'c', '5', 0, + /* 233 */ 'f', '5', 0, + /* 236 */ 'r', '5', 0, + /* 239 */ 'v', '5', 0, + /* 242 */ 'v', '1', '6', 0, + /* 246 */ 'v', '2', '6', 0, + /* 250 */ 'a', '6', 0, + /* 253 */ 'c', '6', 0, + /* 256 */ 'f', '6', 0, + /* 259 */ 'r', '6', 0, + /* 262 */ 'v', '6', 0, + /* 265 */ 'v', '1', '7', 0, + /* 269 */ 'v', '2', '7', 0, + /* 273 */ 'a', '7', 0, + /* 276 */ 'c', '7', 0, + /* 279 */ 'f', '7', 0, + /* 282 */ 'r', '7', 0, + /* 285 */ 'v', '7', 0, + /* 288 */ 'v', '1', '8', 0, + /* 292 */ 'v', '2', '8', 0, + /* 296 */ 'a', '8', 0, + /* 299 */ 'c', '8', 0, + /* 302 */ 'f', '8', 0, + /* 305 */ 'r', '8', 0, + /* 308 */ 'v', '8', 0, + /* 311 */ 'v', '1', '9', 0, + /* 315 */ 'v', '2', '9', 0, + /* 319 */ 'a', '9', 0, + /* 322 */ 'c', '9', 0, + /* 325 */ 'f', '9', 0, + /* 328 */ 'r', '9', 0, + /* 331 */ 'v', '9', 0, + /* 334 */ 'c', 'c', 0, }; static const uint16_t RegAsmOffset[] = { - 334, 28, 71, 110, 149, 188, 227, 250, 273, 296, 319, 0, 43, 86, - 125, 164, 203, 31, 74, 113, 152, 191, 230, 253, 276, 299, 322, 4, - 47, 90, 129, 168, 207, 40, 83, 122, 161, 200, 239, 262, 285, 308, - 331, 16, 59, 102, 141, 180, 219, 242, 265, 288, 311, 20, 63, 106, - 145, 184, 223, 246, 269, 292, 315, 24, 67, 34, 77, 116, 155, 194, - 233, 256, 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, - 311, 20, 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 34, - 77, 194, 233, 302, 325, 94, 133, 34, 77, 116, 155, 194, 233, 256, - 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, 311, 20, - 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 37, 80, 119, - 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, 215, 37, - 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, - 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, - 137, 176, 215, 37, 119, 197, 259, 305, 12, 98, 176, + 334, 28, 71, 110, 149, 188, 227, 250, 273, 296, 319, 0, 43, 86, 125, + 164, 203, 31, 74, 113, 152, 191, 230, 253, 276, 299, 322, 4, 47, 90, + 129, 168, 207, 40, 83, 122, 161, 200, 239, 262, 285, 308, 331, 16, 59, + 102, 141, 180, 219, 242, 265, 288, 311, 20, 63, 106, 145, 184, 223, 246, + 269, 292, 315, 24, 67, 34, 77, 116, 155, 194, 233, 256, 279, 302, 325, + 8, 51, 94, 133, 172, 211, 242, 265, 288, 311, 20, 63, 106, 145, 184, + 223, 246, 269, 292, 315, 24, 67, 34, 77, 194, 233, 302, 325, 94, 133, + 34, 77, 116, 155, 194, 233, 256, 279, 302, 325, 8, 51, 94, 133, 172, + 211, 242, 265, 288, 311, 20, 63, 106, 145, 184, 223, 246, 269, 292, 315, + 24, 67, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, + 137, 176, 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, + 98, 137, 176, 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, + 55, 98, 137, 176, 215, 37, 119, 197, 259, 305, 12, 98, 176, }; - //int i; - //for (i = 0; i < sizeof(RegAsmOffset); i++) + // int i; + // for (i = 0; i < sizeof(RegAsmOffset); i++) // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); - //printf("*************************\n"); - return AsmStrs+RegAsmOffset[RegNo-1]; + // printf("*************************\n"); + return AsmStrs + RegAsmOffset[RegNo - 1]; #else return NULL; #endif diff --git a/arch/SystemZ/SystemZGenDisassemblerTables.inc b/arch/SystemZ/SystemZGenDisassemblerTables.inc index b90664ce0c..c52c6e0c46 100644 --- a/arch/SystemZ/SystemZGenDisassemblerTables.inc +++ b/arch/SystemZ/SystemZGenDisassemblerTables.inc @@ -1,10262 +1,68841 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * SystemZ Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Phosphorus15 , Year 2021 */ +/* This generator is under https://github.com/rizinorg/llvm-capstone */ +/* Automatically generated file, do not edit! */ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#include "../../MCInst.h" #include "../../LEB128.h" +#include "../../MCInst.h" + +#define SystemZ_FeatureBEAREnhancement 0ULL +#define SystemZ_FeatureDFPPackedConversion 1ULL +#define SystemZ_FeatureDFPZonedConversion 2ULL +#define SystemZ_FeatureDeflateConversion 3ULL +#define SystemZ_FeatureDistinctOps 4ULL +#define SystemZ_FeatureEnhancedDAT2 5ULL +#define SystemZ_FeatureEnhancedSort 6ULL +#define SystemZ_FeatureExecutionHint 7ULL +#define SystemZ_FeatureFPExtension 8ULL +#define SystemZ_FeatureFastSerialization 9ULL +#define SystemZ_FeatureGuardedStorage 10ULL +#define SystemZ_FeatureHighWord 11ULL +#define SystemZ_FeatureInsertReferenceBitsMultiple 12ULL +#define SystemZ_FeatureInterlockedAccess1 13ULL +#define SystemZ_FeatureLoadAndTrap 14ULL +#define SystemZ_FeatureLoadAndZeroRightmostByte 15ULL +#define SystemZ_FeatureLoadStoreOnCond 16ULL +#define SystemZ_FeatureLoadStoreOnCond2 17ULL +#define SystemZ_FeatureMessageSecurityAssist3 18ULL +#define SystemZ_FeatureMessageSecurityAssist4 19ULL +#define SystemZ_FeatureMessageSecurityAssist5 20ULL +#define SystemZ_FeatureMessageSecurityAssist7 21ULL +#define SystemZ_FeatureMessageSecurityAssist8 22ULL +#define SystemZ_FeatureMessageSecurityAssist9 23ULL +#define SystemZ_FeatureMiscellaneousExtensions 24ULL +#define SystemZ_FeatureMiscellaneousExtensions2 25ULL +#define SystemZ_FeatureMiscellaneousExtensions3 26ULL +#define SystemZ_FeatureNNPAssist 27ULL +#define SystemZ_FeaturePopulationCount 28ULL +#define SystemZ_FeatureProcessorActivityInstrumentation 29ULL +#define SystemZ_FeatureProcessorAssist 30ULL +#define SystemZ_FeatureResetDATProtection 31ULL +#define SystemZ_FeatureResetReferenceBitsMultiple 32ULL +#define SystemZ_FeatureSoftFloat 33ULL +#define SystemZ_FeatureTransactionalExecution 34ULL +#define SystemZ_FeatureVector 35ULL +#define SystemZ_FeatureVectorEnhancements1 36ULL +#define SystemZ_FeatureVectorEnhancements2 37ULL +#define SystemZ_FeatureVectorPackedDecimal 38ULL +#define SystemZ_FeatureVectorPackedDecimalEnhancement 39ULL +#define SystemZ_FeatureVectorPackedDecimalEnhancement2 40ULL +#ifdef MIPS_GET_DISASSEMBLER +#undef MIPS_GET_DISASSEMBLER // Helper function for extracting fields from encoded instructions. -#define FieldFromInstruction(fname, InsnType) \ -static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ -{ \ - InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ - fieldMask = (InsnType)(-1LL); \ - else \ - fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ - return (insn & fieldMask) >> startBit; \ -} +#define FieldFromInstruction(fname, InsnType) \ + static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ + } static const uint8_t DecoderTable16[] = { -/* 0 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... -/* 3 */ MCD_OPC_FilterValue, 1, 84, 0, // Skip to: 91 -/* 7 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 10 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 18 -/* 14 */ MCD_OPC_Decode, 149, 14, 0, // Opcode: PR -/* 18 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 26 -/* 22 */ MCD_OPC_Decode, 209, 16, 0, // Opcode: UPT -/* 26 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 34 -/* 30 */ MCD_OPC_Decode, 153, 14, 0, // Opcode: PTFF -/* 34 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 42 -/* 38 */ MCD_OPC_Decode, 189, 14, 0, // Opcode: SCKPF -/* 42 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 50 -/* 46 */ MCD_OPC_Decode, 140, 14, 0, // Opcode: PFPO -/* 50 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 58 -/* 54 */ MCD_OPC_Decode, 156, 16, 0, // Opcode: TAM -/* 58 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 66 -/* 62 */ MCD_OPC_Decode, 181, 14, 0, // Opcode: SAM24 -/* 66 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 74 -/* 70 */ MCD_OPC_Decode, 182, 14, 0, // Opcode: SAM31 -/* 74 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 82 -/* 78 */ MCD_OPC_Decode, 183, 14, 0, // Opcode: SAM64 -/* 82 */ MCD_OPC_FilterValue, 255, 1, 85, 2, // Skip to: 684 -/* 87 */ MCD_OPC_Decode, 187, 16, 0, // Opcode: TRAP2 -/* 91 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 105 -/* 95 */ MCD_OPC_CheckField, 0, 4, 0, 71, 2, // Skip to: 684 -/* 101 */ MCD_OPC_Decode, 245, 14, 1, // Opcode: SPM -/* 105 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 113 -/* 109 */ MCD_OPC_Decode, 168, 3, 2, // Opcode: BALR -/* 113 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 121 -/* 117 */ MCD_OPC_Decode, 199, 3, 3, // Opcode: BCTR -/* 121 */ MCD_OPC_FilterValue, 7, 127, 0, // Skip to: 252 -/* 125 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... -/* 128 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 136 -/* 132 */ MCD_OPC_Decode, 245, 3, 4, // Opcode: BRAsmO -/* 136 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 144 -/* 140 */ MCD_OPC_Decode, 229, 3, 4, // Opcode: BRAsmH -/* 144 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 152 -/* 148 */ MCD_OPC_Decode, 239, 3, 4, // Opcode: BRAsmNLE -/* 152 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 160 -/* 156 */ MCD_OPC_Decode, 231, 3, 4, // Opcode: BRAsmL -/* 160 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 168 -/* 164 */ MCD_OPC_Decode, 237, 3, 4, // Opcode: BRAsmNHE -/* 168 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 176 -/* 172 */ MCD_OPC_Decode, 233, 3, 4, // Opcode: BRAsmLH -/* 176 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 184 -/* 180 */ MCD_OPC_Decode, 235, 3, 4, // Opcode: BRAsmNE -/* 184 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 192 -/* 188 */ MCD_OPC_Decode, 228, 3, 4, // Opcode: BRAsmE -/* 192 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 200 -/* 196 */ MCD_OPC_Decode, 240, 3, 4, // Opcode: BRAsmNLH -/* 200 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 208 -/* 204 */ MCD_OPC_Decode, 230, 3, 4, // Opcode: BRAsmHE -/* 208 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 216 -/* 212 */ MCD_OPC_Decode, 238, 3, 4, // Opcode: BRAsmNL -/* 216 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 224 -/* 220 */ MCD_OPC_Decode, 232, 3, 4, // Opcode: BRAsmLE -/* 224 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 232 -/* 228 */ MCD_OPC_Decode, 236, 3, 4, // Opcode: BRAsmNH -/* 232 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 240 -/* 236 */ MCD_OPC_Decode, 242, 3, 4, // Opcode: BRAsmNO -/* 240 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 248 -/* 244 */ MCD_OPC_Decode, 225, 3, 4, // Opcode: BR -/* 248 */ MCD_OPC_Decode, 195, 3, 5, // Opcode: BCRAsm -/* 252 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 260 -/* 256 */ MCD_OPC_Decode, 147, 16, 6, // Opcode: SVC -/* 260 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 268 -/* 264 */ MCD_OPC_Decode, 133, 4, 2, // Opcode: BSM -/* 268 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 276 -/* 272 */ MCD_OPC_Decode, 171, 3, 2, // Opcode: BASSM -/* 276 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 284 -/* 280 */ MCD_OPC_Decode, 170, 3, 2, // Opcode: BASR -/* 284 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 292 -/* 288 */ MCD_OPC_Decode, 195, 13, 7, // Opcode: MVCL -/* 292 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 300 -/* 296 */ MCD_OPC_Decode, 226, 5, 7, // Opcode: CLCL -/* 300 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 308 -/* 304 */ MCD_OPC_Decode, 196, 12, 8, // Opcode: LPR -/* 308 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 316 -/* 312 */ MCD_OPC_Decode, 238, 10, 8, // Opcode: LNR -/* 316 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 324 -/* 320 */ MCD_OPC_Decode, 227, 12, 8, // Opcode: LTR -/* 324 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 332 -/* 328 */ MCD_OPC_Decode, 141, 10, 8, // Opcode: LCR -/* 332 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 340 -/* 336 */ MCD_OPC_Decode, 240, 13, 9, // Opcode: NR -/* 340 */ MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 348 -/* 344 */ MCD_OPC_Decode, 145, 7, 8, // Opcode: CLR -/* 348 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 356 -/* 352 */ MCD_OPC_Decode, 129, 14, 9, // Opcode: OR -/* 356 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 364 -/* 360 */ MCD_OPC_Decode, 235, 21, 9, // Opcode: XR -/* 364 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 372 -/* 368 */ MCD_OPC_Decode, 202, 12, 8, // Opcode: LR -/* 372 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 380 -/* 376 */ MCD_OPC_Decode, 214, 7, 8, // Opcode: CR -/* 380 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 388 -/* 384 */ MCD_OPC_Decode, 153, 3, 9, // Opcode: AR -/* 388 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 396 -/* 392 */ MCD_OPC_Decode, 130, 15, 9, // Opcode: SR -/* 396 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 404 -/* 400 */ MCD_OPC_Decode, 167, 13, 10, // Opcode: MR -/* 404 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 412 -/* 408 */ MCD_OPC_Decode, 206, 8, 10, // Opcode: DR -/* 412 */ MCD_OPC_FilterValue, 30, 4, 0, // Skip to: 420 -/* 416 */ MCD_OPC_Decode, 146, 3, 9, // Opcode: ALR -/* 420 */ MCD_OPC_FilterValue, 31, 4, 0, // Skip to: 428 -/* 424 */ MCD_OPC_Decode, 238, 14, 9, // Opcode: SLR -/* 428 */ MCD_OPC_FilterValue, 32, 4, 0, // Skip to: 436 -/* 432 */ MCD_OPC_Decode, 189, 12, 11, // Opcode: LPDR -/* 436 */ MCD_OPC_FilterValue, 33, 4, 0, // Skip to: 444 -/* 440 */ MCD_OPC_Decode, 233, 10, 11, // Opcode: LNDR -/* 444 */ MCD_OPC_FilterValue, 34, 4, 0, // Skip to: 452 -/* 448 */ MCD_OPC_Decode, 218, 12, 11, // Opcode: LTDR -/* 452 */ MCD_OPC_FilterValue, 35, 4, 0, // Skip to: 460 -/* 456 */ MCD_OPC_Decode, 136, 10, 11, // Opcode: LCDR -/* 460 */ MCD_OPC_FilterValue, 36, 4, 0, // Skip to: 468 -/* 464 */ MCD_OPC_Decode, 252, 8, 11, // Opcode: HDR -/* 468 */ MCD_OPC_FilterValue, 37, 4, 0, // Skip to: 476 -/* 472 */ MCD_OPC_Decode, 158, 10, 12, // Opcode: LDXR -/* 476 */ MCD_OPC_FilterValue, 38, 4, 0, // Skip to: 484 -/* 480 */ MCD_OPC_Decode, 217, 13, 13, // Opcode: MXR -/* 484 */ MCD_OPC_FilterValue, 39, 4, 0, // Skip to: 492 -/* 488 */ MCD_OPC_Decode, 216, 13, 14, // Opcode: MXDR -/* 492 */ MCD_OPC_FilterValue, 40, 4, 0, // Skip to: 500 -/* 496 */ MCD_OPC_Decode, 154, 10, 11, // Opcode: LDR -/* 500 */ MCD_OPC_FilterValue, 41, 4, 0, // Skip to: 508 -/* 504 */ MCD_OPC_Decode, 156, 4, 11, // Opcode: CDR -/* 508 */ MCD_OPC_FilterValue, 42, 4, 0, // Skip to: 516 -/* 512 */ MCD_OPC_Decode, 232, 2, 15, // Opcode: ADR -/* 516 */ MCD_OPC_FilterValue, 43, 4, 0, // Skip to: 524 -/* 520 */ MCD_OPC_Decode, 193, 14, 15, // Opcode: SDR -/* 524 */ MCD_OPC_FilterValue, 44, 4, 0, // Skip to: 532 -/* 528 */ MCD_OPC_Decode, 145, 13, 15, // Opcode: MDR -/* 532 */ MCD_OPC_FilterValue, 45, 4, 0, // Skip to: 540 -/* 536 */ MCD_OPC_Decode, 191, 8, 15, // Opcode: DDR -/* 540 */ MCD_OPC_FilterValue, 46, 4, 0, // Skip to: 548 -/* 544 */ MCD_OPC_Decode, 159, 3, 15, // Opcode: AWR -/* 548 */ MCD_OPC_FilterValue, 47, 4, 0, // Skip to: 556 -/* 552 */ MCD_OPC_Decode, 149, 16, 15, // Opcode: SWR -/* 556 */ MCD_OPC_FilterValue, 48, 4, 0, // Skip to: 564 -/* 560 */ MCD_OPC_Decode, 191, 12, 16, // Opcode: LPER -/* 564 */ MCD_OPC_FilterValue, 49, 4, 0, // Skip to: 572 -/* 568 */ MCD_OPC_Decode, 235, 10, 16, // Opcode: LNER -/* 572 */ MCD_OPC_FilterValue, 50, 4, 0, // Skip to: 580 -/* 576 */ MCD_OPC_Decode, 222, 12, 16, // Opcode: LTER -/* 580 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 588 -/* 584 */ MCD_OPC_Decode, 138, 10, 16, // Opcode: LCER -/* 588 */ MCD_OPC_FilterValue, 52, 4, 0, // Skip to: 596 -/* 592 */ MCD_OPC_Decode, 253, 8, 16, // Opcode: HER -/* 596 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 604 -/* 600 */ MCD_OPC_Decode, 164, 10, 17, // Opcode: LEDR -/* 604 */ MCD_OPC_FilterValue, 54, 4, 0, // Skip to: 612 -/* 608 */ MCD_OPC_Decode, 161, 3, 13, // Opcode: AXR -/* 612 */ MCD_OPC_FilterValue, 55, 4, 0, // Skip to: 620 -/* 616 */ MCD_OPC_Decode, 151, 16, 13, // Opcode: SXR -/* 620 */ MCD_OPC_FilterValue, 56, 4, 0, // Skip to: 628 -/* 624 */ MCD_OPC_Decode, 166, 10, 16, // Opcode: LER -/* 628 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 636 -/* 632 */ MCD_OPC_Decode, 176, 4, 16, // Opcode: CER -/* 636 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 644 -/* 640 */ MCD_OPC_Decode, 238, 2, 18, // Opcode: AER -/* 644 */ MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 652 -/* 648 */ MCD_OPC_Decode, 199, 14, 18, // Opcode: SER -/* 652 */ MCD_OPC_FilterValue, 60, 4, 0, // Skip to: 660 -/* 656 */ MCD_OPC_Decode, 144, 13, 19, // Opcode: MDER -/* 660 */ MCD_OPC_FilterValue, 61, 4, 0, // Skip to: 668 -/* 664 */ MCD_OPC_Decode, 197, 8, 18, // Opcode: DER -/* 668 */ MCD_OPC_FilterValue, 62, 4, 0, // Skip to: 676 -/* 672 */ MCD_OPC_Decode, 157, 3, 18, // Opcode: AUR -/* 676 */ MCD_OPC_FilterValue, 63, 4, 0, // Skip to: 684 -/* 680 */ MCD_OPC_Decode, 146, 16, 18, // Opcode: SUR -/* 684 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 8, + 8, // Inst{15-8} ... + /* 3 */ MCD_OPC_FilterValue, + 1, + 94, + 0, + 0, // Skip to: 102 + /* 8 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 11 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 20 + /* 16 */ MCD_OPC_Decode, + 197, + 15, + 0, // Opcode: PR + /* 20 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 29 + /* 25 */ MCD_OPC_Decode, + 200, + 18, + 0, // Opcode: UPT + /* 29 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 38 + /* 34 */ MCD_OPC_Decode, + 201, + 15, + 0, // Opcode: PTFF + /* 38 */ MCD_OPC_FilterValue, + 7, + 4, + 0, + 0, // Skip to: 47 + /* 43 */ MCD_OPC_Decode, + 240, + 15, + 0, // Opcode: SCKPF + /* 47 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 56 + /* 52 */ MCD_OPC_Decode, + 187, + 15, + 0, // Opcode: PFPO + /* 56 */ MCD_OPC_FilterValue, + 11, + 4, + 0, + 0, // Skip to: 65 + /* 61 */ MCD_OPC_Decode, + 147, + 18, + 0, // Opcode: TAM + /* 65 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 74 + /* 70 */ MCD_OPC_Decode, + 232, + 15, + 0, // Opcode: SAM24 + /* 74 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 83 + /* 79 */ MCD_OPC_Decode, + 233, + 15, + 0, // Opcode: SAM31 + /* 83 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 92 + /* 88 */ MCD_OPC_Decode, + 234, + 15, + 0, // Opcode: SAM64 + /* 92 */ MCD_OPC_FilterValue, + 255, + 1, + 159, + 2, + 0, // Skip to: 769 + /* 98 */ MCD_OPC_Decode, + 178, + 18, + 0, // Opcode: TRAP2 + /* 102 */ MCD_OPC_FilterValue, + 4, + 11, + 0, + 0, // Skip to: 118 + /* 107 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 143, + 2, + 0, // Skip to: 769 + /* 114 */ MCD_OPC_Decode, + 235, + 16, + 1, // Opcode: SPM + /* 118 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 127 + /* 123 */ MCD_OPC_Decode, + 192, + 4, + 2, // Opcode: BALR + /* 127 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 136 + /* 132 */ MCD_OPC_Decode, + 223, + 4, + 3, // Opcode: BCTR + /* 136 */ MCD_OPC_FilterValue, + 7, + 142, + 0, + 0, // Skip to: 283 + /* 141 */ MCD_OPC_ExtractField, + 4, + 4, // Inst{7-4} ... + /* 144 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 153 + /* 149 */ MCD_OPC_Decode, + 141, + 5, + 4, // Opcode: BRAsmO + /* 153 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 162 + /* 158 */ MCD_OPC_Decode, + 253, + 4, + 4, // Opcode: BRAsmH + /* 162 */ MCD_OPC_FilterValue, + 3, + 4, + 0, + 0, // Skip to: 171 + /* 167 */ MCD_OPC_Decode, + 135, + 5, + 4, // Opcode: BRAsmNLE + /* 171 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 180 + /* 176 */ MCD_OPC_Decode, + 255, + 4, + 4, // Opcode: BRAsmL + /* 180 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 189 + /* 185 */ MCD_OPC_Decode, + 133, + 5, + 4, // Opcode: BRAsmNHE + /* 189 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 198 + /* 194 */ MCD_OPC_Decode, + 129, + 5, + 4, // Opcode: BRAsmLH + /* 198 */ MCD_OPC_FilterValue, + 7, + 4, + 0, + 0, // Skip to: 207 + /* 203 */ MCD_OPC_Decode, + 131, + 5, + 4, // Opcode: BRAsmNE + /* 207 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 216 + /* 212 */ MCD_OPC_Decode, + 252, + 4, + 4, // Opcode: BRAsmE + /* 216 */ MCD_OPC_FilterValue, + 9, + 4, + 0, + 0, // Skip to: 225 + /* 221 */ MCD_OPC_Decode, + 136, + 5, + 4, // Opcode: BRAsmNLH + /* 225 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 234 + /* 230 */ MCD_OPC_Decode, + 254, + 4, + 4, // Opcode: BRAsmHE + /* 234 */ MCD_OPC_FilterValue, + 11, + 4, + 0, + 0, // Skip to: 243 + /* 239 */ MCD_OPC_Decode, + 134, + 5, + 4, // Opcode: BRAsmNL + /* 243 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 252 + /* 248 */ MCD_OPC_Decode, + 128, + 5, + 4, // Opcode: BRAsmLE + /* 252 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 261 + /* 257 */ MCD_OPC_Decode, + 132, + 5, + 4, // Opcode: BRAsmNH + /* 261 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 270 + /* 266 */ MCD_OPC_Decode, + 138, + 5, + 4, // Opcode: BRAsmNO + /* 270 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 279 + /* 275 */ MCD_OPC_Decode, + 249, + 4, + 4, // Opcode: BR + /* 279 */ MCD_OPC_Decode, + 219, + 4, + 5, // Opcode: BCRAsm + /* 283 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 292 + /* 288 */ MCD_OPC_Decode, + 138, + 18, + 6, // Opcode: SVC + /* 292 */ MCD_OPC_FilterValue, + 11, + 4, + 0, + 0, // Skip to: 301 + /* 297 */ MCD_OPC_Decode, + 157, + 5, + 2, // Opcode: BSM + /* 301 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 310 + /* 306 */ MCD_OPC_Decode, + 195, + 4, + 2, // Opcode: BASSM + /* 310 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 319 + /* 315 */ MCD_OPC_Decode, + 194, + 4, + 2, // Opcode: BASR + /* 319 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 328 + /* 324 */ MCD_OPC_Decode, + 229, + 14, + 7, // Opcode: MVCL + /* 328 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 337 + /* 333 */ MCD_OPC_Decode, + 250, + 6, + 7, // Opcode: CLCL + /* 337 */ MCD_OPC_FilterValue, + 16, + 4, + 0, + 0, // Skip to: 346 + /* 342 */ MCD_OPC_Decode, + 229, + 13, + 8, // Opcode: LPR + /* 346 */ MCD_OPC_FilterValue, + 17, + 4, + 0, + 0, // Skip to: 355 + /* 351 */ MCD_OPC_Decode, + 143, + 12, + 8, // Opcode: LNR + /* 355 */ MCD_OPC_FilterValue, + 18, + 4, + 0, + 0, // Skip to: 364 + /* 360 */ MCD_OPC_Decode, + 133, + 14, + 8, // Opcode: LTR + /* 364 */ MCD_OPC_FilterValue, + 19, + 4, + 0, + 0, // Skip to: 373 + /* 369 */ MCD_OPC_Decode, + 174, + 11, + 8, // Opcode: LCR + /* 373 */ MCD_OPC_FilterValue, + 20, + 4, + 0, + 0, // Skip to: 382 + /* 378 */ MCD_OPC_Decode, + 155, + 15, + 9, // Opcode: NR + /* 382 */ MCD_OPC_FilterValue, + 21, + 4, + 0, + 0, // Skip to: 391 + /* 387 */ MCD_OPC_Decode, + 169, + 8, + 8, // Opcode: CLR + /* 391 */ MCD_OPC_FilterValue, + 22, + 4, + 0, + 0, // Skip to: 400 + /* 396 */ MCD_OPC_Decode, + 176, + 15, + 9, // Opcode: OR + /* 400 */ MCD_OPC_FilterValue, + 23, + 4, + 0, + 0, // Skip to: 409 + /* 405 */ MCD_OPC_Decode, + 174, + 24, + 9, // Opcode: XR + /* 409 */ MCD_OPC_FilterValue, + 24, + 4, + 0, + 0, // Skip to: 418 + /* 414 */ MCD_OPC_Decode, + 236, + 13, + 8, // Opcode: LR + /* 418 */ MCD_OPC_FilterValue, + 25, + 4, + 0, + 0, // Skip to: 427 + /* 423 */ MCD_OPC_Decode, + 238, + 8, + 8, // Opcode: CR + /* 427 */ MCD_OPC_FilterValue, + 26, + 4, + 0, + 0, // Skip to: 436 + /* 432 */ MCD_OPC_Decode, + 177, + 4, + 9, // Opcode: AR + /* 436 */ MCD_OPC_FilterValue, + 27, + 4, + 0, + 0, // Skip to: 445 + /* 441 */ MCD_OPC_Decode, + 248, + 16, + 9, // Opcode: SR + /* 445 */ MCD_OPC_FilterValue, + 28, + 4, + 0, + 0, // Skip to: 454 + /* 450 */ MCD_OPC_Decode, + 201, + 14, + 10, // Opcode: MR + /* 454 */ MCD_OPC_FilterValue, + 29, + 4, + 0, + 0, // Skip to: 463 + /* 459 */ MCD_OPC_Decode, + 231, + 9, + 10, // Opcode: DR + /* 463 */ MCD_OPC_FilterValue, + 30, + 4, + 0, + 0, // Skip to: 472 + /* 468 */ MCD_OPC_Decode, + 170, + 4, + 9, // Opcode: ALR + /* 472 */ MCD_OPC_FilterValue, + 31, + 4, + 0, + 0, // Skip to: 481 + /* 477 */ MCD_OPC_Decode, + 227, + 16, + 9, // Opcode: SLR + /* 481 */ MCD_OPC_FilterValue, + 32, + 4, + 0, + 0, // Skip to: 490 + /* 486 */ MCD_OPC_Decode, + 222, + 13, + 11, // Opcode: LPDR + /* 490 */ MCD_OPC_FilterValue, + 33, + 4, + 0, + 0, // Skip to: 499 + /* 495 */ MCD_OPC_Decode, + 138, + 12, + 11, // Opcode: LNDR + /* 499 */ MCD_OPC_FilterValue, + 34, + 4, + 0, + 0, // Skip to: 508 + /* 504 */ MCD_OPC_Decode, + 252, + 13, + 11, // Opcode: LTDR + /* 508 */ MCD_OPC_FilterValue, + 35, + 4, + 0, + 0, // Skip to: 517 + /* 513 */ MCD_OPC_Decode, + 169, + 11, + 11, // Opcode: LCDR + /* 517 */ MCD_OPC_FilterValue, + 36, + 4, + 0, + 0, // Skip to: 526 + /* 522 */ MCD_OPC_Decode, + 149, + 10, + 11, // Opcode: HDR + /* 526 */ MCD_OPC_FilterValue, + 37, + 4, + 0, + 0, // Skip to: 535 + /* 531 */ MCD_OPC_Decode, + 191, + 11, + 12, // Opcode: LDXR + /* 535 */ MCD_OPC_FilterValue, + 38, + 4, + 0, + 0, // Skip to: 544 + /* 540 */ MCD_OPC_Decode, + 252, + 14, + 13, // Opcode: MXR + /* 544 */ MCD_OPC_FilterValue, + 39, + 4, + 0, + 0, // Skip to: 553 + /* 549 */ MCD_OPC_Decode, + 251, + 14, + 14, // Opcode: MXDR + /* 553 */ MCD_OPC_FilterValue, + 40, + 4, + 0, + 0, // Skip to: 562 + /* 558 */ MCD_OPC_Decode, + 187, + 11, + 11, // Opcode: LDR + /* 562 */ MCD_OPC_FilterValue, + 41, + 4, + 0, + 0, // Skip to: 571 + /* 567 */ MCD_OPC_Decode, + 180, + 5, + 11, // Opcode: CDR + /* 571 */ MCD_OPC_FilterValue, + 42, + 4, + 0, + 0, // Skip to: 580 + /* 576 */ MCD_OPC_Decode, + 128, + 4, + 15, // Opcode: ADR + /* 580 */ MCD_OPC_FilterValue, + 43, + 4, + 0, + 0, // Skip to: 589 + /* 585 */ MCD_OPC_Decode, + 244, + 15, + 15, // Opcode: SDR + /* 589 */ MCD_OPC_FilterValue, + 44, + 4, + 0, + 0, // Skip to: 598 + /* 594 */ MCD_OPC_Decode, + 179, + 14, + 15, // Opcode: MDR + /* 598 */ MCD_OPC_FilterValue, + 45, + 4, + 0, + 0, // Skip to: 607 + /* 603 */ MCD_OPC_Decode, + 215, + 9, + 15, // Opcode: DDR + /* 607 */ MCD_OPC_FilterValue, + 46, + 4, + 0, + 0, // Skip to: 616 + /* 612 */ MCD_OPC_Decode, + 183, + 4, + 15, // Opcode: AWR + /* 616 */ MCD_OPC_FilterValue, + 47, + 4, + 0, + 0, // Skip to: 625 + /* 621 */ MCD_OPC_Decode, + 140, + 18, + 15, // Opcode: SWR + /* 625 */ MCD_OPC_FilterValue, + 48, + 4, + 0, + 0, // Skip to: 634 + /* 630 */ MCD_OPC_Decode, + 224, + 13, + 16, // Opcode: LPER + /* 634 */ MCD_OPC_FilterValue, + 49, + 4, + 0, + 0, // Skip to: 643 + /* 639 */ MCD_OPC_Decode, + 140, + 12, + 16, // Opcode: LNER + /* 643 */ MCD_OPC_FilterValue, + 50, + 4, + 0, + 0, // Skip to: 652 + /* 648 */ MCD_OPC_Decode, + 128, + 14, + 16, // Opcode: LTER + /* 652 */ MCD_OPC_FilterValue, + 51, + 4, + 0, + 0, // Skip to: 661 + /* 657 */ MCD_OPC_Decode, + 171, + 11, + 16, // Opcode: LCER + /* 661 */ MCD_OPC_FilterValue, + 52, + 4, + 0, + 0, // Skip to: 670 + /* 666 */ MCD_OPC_Decode, + 150, + 10, + 16, // Opcode: HER + /* 670 */ MCD_OPC_FilterValue, + 53, + 4, + 0, + 0, // Skip to: 679 + /* 675 */ MCD_OPC_Decode, + 197, + 11, + 17, // Opcode: LEDR + /* 679 */ MCD_OPC_FilterValue, + 54, + 4, + 0, + 0, // Skip to: 688 + /* 684 */ MCD_OPC_Decode, + 185, + 4, + 13, // Opcode: AXR + /* 688 */ MCD_OPC_FilterValue, + 55, + 4, + 0, + 0, // Skip to: 697 + /* 693 */ MCD_OPC_Decode, + 142, + 18, + 13, // Opcode: SXR + /* 697 */ MCD_OPC_FilterValue, + 56, + 4, + 0, + 0, // Skip to: 706 + /* 702 */ MCD_OPC_Decode, + 199, + 11, + 16, // Opcode: LER + /* 706 */ MCD_OPC_FilterValue, + 57, + 4, + 0, + 0, // Skip to: 715 + /* 711 */ MCD_OPC_Decode, + 200, + 5, + 16, // Opcode: CER + /* 715 */ MCD_OPC_FilterValue, + 58, + 4, + 0, + 0, // Skip to: 724 + /* 720 */ MCD_OPC_Decode, + 134, + 4, + 18, // Opcode: AER + /* 724 */ MCD_OPC_FilterValue, + 59, + 4, + 0, + 0, // Skip to: 733 + /* 729 */ MCD_OPC_Decode, + 188, + 16, + 18, // Opcode: SER + /* 733 */ MCD_OPC_FilterValue, + 60, + 4, + 0, + 0, // Skip to: 742 + /* 738 */ MCD_OPC_Decode, + 178, + 14, + 19, // Opcode: MDER + /* 742 */ MCD_OPC_FilterValue, + 61, + 4, + 0, + 0, // Skip to: 751 + /* 747 */ MCD_OPC_Decode, + 221, + 9, + 18, // Opcode: DER + /* 751 */ MCD_OPC_FilterValue, + 62, + 4, + 0, + 0, // Skip to: 760 + /* 756 */ MCD_OPC_Decode, + 181, + 4, + 18, // Opcode: AUR + /* 760 */ MCD_OPC_FilterValue, + 63, + 4, + 0, + 0, // Skip to: 769 + /* 765 */ MCD_OPC_Decode, + 137, + 18, + 18, // Opcode: SUR + /* 769 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTable32[] = { -/* 0 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 3 */ MCD_OPC_FilterValue, 64, 4, 0, // Skip to: 11 -/* 7 */ MCD_OPC_Decode, 183, 15, 20, // Opcode: STH -/* 11 */ MCD_OPC_FilterValue, 65, 4, 0, // Skip to: 19 -/* 15 */ MCD_OPC_Decode, 237, 9, 21, // Opcode: LA -/* 19 */ MCD_OPC_FilterValue, 66, 4, 0, // Skip to: 27 -/* 23 */ MCD_OPC_Decode, 158, 15, 20, // Opcode: STC -/* 27 */ MCD_OPC_FilterValue, 67, 4, 0, // Skip to: 35 -/* 31 */ MCD_OPC_Decode, 128, 9, 22, // Opcode: IC -/* 35 */ MCD_OPC_FilterValue, 68, 4, 0, // Skip to: 43 -/* 39 */ MCD_OPC_Decode, 238, 8, 21, // Opcode: EX -/* 43 */ MCD_OPC_FilterValue, 69, 4, 0, // Skip to: 51 -/* 47 */ MCD_OPC_Decode, 167, 3, 21, // Opcode: BAL -/* 51 */ MCD_OPC_FilterValue, 70, 4, 0, // Skip to: 59 -/* 55 */ MCD_OPC_Decode, 196, 3, 23, // Opcode: BCT -/* 59 */ MCD_OPC_FilterValue, 71, 127, 0, // Skip to: 190 -/* 63 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 66 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 74 -/* 70 */ MCD_OPC_Decode, 189, 3, 24, // Opcode: BAsmO -/* 74 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 82 -/* 78 */ MCD_OPC_Decode, 173, 3, 24, // Opcode: BAsmH -/* 82 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 90 -/* 86 */ MCD_OPC_Decode, 183, 3, 24, // Opcode: BAsmNLE -/* 90 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 98 -/* 94 */ MCD_OPC_Decode, 175, 3, 24, // Opcode: BAsmL -/* 98 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 106 -/* 102 */ MCD_OPC_Decode, 181, 3, 24, // Opcode: BAsmNHE -/* 106 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 114 -/* 110 */ MCD_OPC_Decode, 177, 3, 24, // Opcode: BAsmLH -/* 114 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 122 -/* 118 */ MCD_OPC_Decode, 179, 3, 24, // Opcode: BAsmNE -/* 122 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 130 -/* 126 */ MCD_OPC_Decode, 172, 3, 24, // Opcode: BAsmE -/* 130 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 138 -/* 134 */ MCD_OPC_Decode, 184, 3, 24, // Opcode: BAsmNLH -/* 138 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 146 -/* 142 */ MCD_OPC_Decode, 174, 3, 24, // Opcode: BAsmHE -/* 146 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 154 -/* 150 */ MCD_OPC_Decode, 182, 3, 24, // Opcode: BAsmNL -/* 154 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 162 -/* 158 */ MCD_OPC_Decode, 176, 3, 24, // Opcode: BAsmLE -/* 162 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 170 -/* 166 */ MCD_OPC_Decode, 180, 3, 24, // Opcode: BAsmNH -/* 170 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 178 -/* 174 */ MCD_OPC_Decode, 186, 3, 24, // Opcode: BAsmNO -/* 178 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 186 -/* 182 */ MCD_OPC_Decode, 165, 3, 24, // Opcode: B -/* 186 */ MCD_OPC_Decode, 193, 3, 25, // Opcode: BCAsm -/* 190 */ MCD_OPC_FilterValue, 72, 4, 0, // Skip to: 198 -/* 194 */ MCD_OPC_Decode, 192, 10, 20, // Opcode: LH -/* 198 */ MCD_OPC_FilterValue, 73, 4, 0, // Skip to: 206 -/* 202 */ MCD_OPC_Decode, 171, 5, 20, // Opcode: CH -/* 206 */ MCD_OPC_FilterValue, 74, 4, 0, // Skip to: 214 -/* 210 */ MCD_OPC_Decode, 250, 2, 23, // Opcode: AH -/* 214 */ MCD_OPC_FilterValue, 75, 4, 0, // Skip to: 222 -/* 218 */ MCD_OPC_Decode, 208, 14, 23, // Opcode: SH -/* 222 */ MCD_OPC_FilterValue, 76, 4, 0, // Skip to: 230 -/* 226 */ MCD_OPC_Decode, 159, 13, 23, // Opcode: MH -/* 230 */ MCD_OPC_FilterValue, 77, 4, 0, // Skip to: 238 -/* 234 */ MCD_OPC_Decode, 169, 3, 21, // Opcode: BAS -/* 238 */ MCD_OPC_FilterValue, 78, 4, 0, // Skip to: 246 -/* 242 */ MCD_OPC_Decode, 161, 8, 20, // Opcode: CVD -/* 246 */ MCD_OPC_FilterValue, 79, 4, 0, // Skip to: 254 -/* 250 */ MCD_OPC_Decode, 158, 8, 23, // Opcode: CVB -/* 254 */ MCD_OPC_FilterValue, 80, 4, 0, // Skip to: 262 -/* 258 */ MCD_OPC_Decode, 154, 15, 20, // Opcode: ST -/* 262 */ MCD_OPC_FilterValue, 81, 4, 0, // Skip to: 270 -/* 266 */ MCD_OPC_Decode, 242, 9, 21, // Opcode: LAE -/* 270 */ MCD_OPC_FilterValue, 84, 4, 0, // Skip to: 278 -/* 274 */ MCD_OPC_Decode, 226, 13, 23, // Opcode: N -/* 278 */ MCD_OPC_FilterValue, 85, 4, 0, // Skip to: 286 -/* 282 */ MCD_OPC_Decode, 224, 5, 20, // Opcode: CL -/* 286 */ MCD_OPC_FilterValue, 86, 4, 0, // Skip to: 294 -/* 290 */ MCD_OPC_Decode, 244, 13, 23, // Opcode: O -/* 294 */ MCD_OPC_FilterValue, 87, 4, 0, // Skip to: 302 -/* 298 */ MCD_OPC_Decode, 226, 21, 23, // Opcode: X -/* 302 */ MCD_OPC_FilterValue, 88, 4, 0, // Skip to: 310 -/* 306 */ MCD_OPC_Decode, 236, 9, 20, // Opcode: L -/* 310 */ MCD_OPC_FilterValue, 89, 4, 0, // Skip to: 318 -/* 314 */ MCD_OPC_Decode, 138, 4, 20, // Opcode: C -/* 318 */ MCD_OPC_FilterValue, 90, 4, 0, // Skip to: 326 -/* 322 */ MCD_OPC_Decode, 228, 2, 23, // Opcode: A -/* 326 */ MCD_OPC_FilterValue, 91, 4, 0, // Skip to: 334 -/* 330 */ MCD_OPC_Decode, 177, 14, 23, // Opcode: S -/* 334 */ MCD_OPC_FilterValue, 92, 4, 0, // Skip to: 342 -/* 338 */ MCD_OPC_Decode, 250, 12, 26, // Opcode: M -/* 342 */ MCD_OPC_FilterValue, 93, 4, 0, // Skip to: 350 -/* 346 */ MCD_OPC_Decode, 187, 8, 26, // Opcode: D -/* 350 */ MCD_OPC_FilterValue, 94, 4, 0, // Skip to: 358 -/* 354 */ MCD_OPC_Decode, 129, 3, 23, // Opcode: AL -/* 358 */ MCD_OPC_FilterValue, 95, 4, 0, // Skip to: 366 -/* 362 */ MCD_OPC_Decode, 215, 14, 23, // Opcode: SL -/* 366 */ MCD_OPC_FilterValue, 96, 4, 0, // Skip to: 374 -/* 370 */ MCD_OPC_Decode, 172, 15, 27, // Opcode: STD -/* 374 */ MCD_OPC_FilterValue, 103, 4, 0, // Skip to: 382 -/* 378 */ MCD_OPC_Decode, 213, 13, 28, // Opcode: MXD -/* 382 */ MCD_OPC_FilterValue, 104, 4, 0, // Skip to: 390 -/* 386 */ MCD_OPC_Decode, 146, 10, 27, // Opcode: LD -/* 390 */ MCD_OPC_FilterValue, 105, 4, 0, // Skip to: 398 -/* 394 */ MCD_OPC_Decode, 139, 4, 27, // Opcode: CD -/* 398 */ MCD_OPC_FilterValue, 106, 4, 0, // Skip to: 406 -/* 402 */ MCD_OPC_Decode, 229, 2, 29, // Opcode: AD -/* 406 */ MCD_OPC_FilterValue, 107, 4, 0, // Skip to: 414 -/* 410 */ MCD_OPC_Decode, 190, 14, 29, // Opcode: SD -/* 414 */ MCD_OPC_FilterValue, 108, 4, 0, // Skip to: 422 -/* 418 */ MCD_OPC_Decode, 138, 13, 29, // Opcode: MD -/* 422 */ MCD_OPC_FilterValue, 109, 4, 0, // Skip to: 430 -/* 426 */ MCD_OPC_Decode, 188, 8, 29, // Opcode: DD -/* 430 */ MCD_OPC_FilterValue, 110, 4, 0, // Skip to: 438 -/* 434 */ MCD_OPC_Decode, 158, 3, 29, // Opcode: AW -/* 438 */ MCD_OPC_FilterValue, 111, 4, 0, // Skip to: 446 -/* 442 */ MCD_OPC_Decode, 148, 16, 29, // Opcode: SW -/* 446 */ MCD_OPC_FilterValue, 112, 4, 0, // Skip to: 454 -/* 450 */ MCD_OPC_Decode, 174, 15, 30, // Opcode: STE -/* 454 */ MCD_OPC_FilterValue, 113, 4, 0, // Skip to: 462 -/* 458 */ MCD_OPC_Decode, 168, 13, 23, // Opcode: MS -/* 462 */ MCD_OPC_FilterValue, 120, 4, 0, // Skip to: 470 -/* 466 */ MCD_OPC_Decode, 161, 10, 30, // Opcode: LE -/* 470 */ MCD_OPC_FilterValue, 121, 4, 0, // Skip to: 478 -/* 474 */ MCD_OPC_Decode, 164, 4, 30, // Opcode: CE -/* 478 */ MCD_OPC_FilterValue, 122, 4, 0, // Skip to: 486 -/* 482 */ MCD_OPC_Decode, 235, 2, 31, // Opcode: AE -/* 486 */ MCD_OPC_FilterValue, 123, 4, 0, // Skip to: 494 -/* 490 */ MCD_OPC_Decode, 196, 14, 31, // Opcode: SE -/* 494 */ MCD_OPC_FilterValue, 124, 4, 0, // Skip to: 502 -/* 498 */ MCD_OPC_Decode, 141, 13, 29, // Opcode: MDE -/* 502 */ MCD_OPC_FilterValue, 125, 4, 0, // Skip to: 510 -/* 506 */ MCD_OPC_Decode, 194, 8, 31, // Opcode: DE -/* 510 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 518 -/* 514 */ MCD_OPC_Decode, 156, 3, 31, // Opcode: AU -/* 518 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526 -/* 522 */ MCD_OPC_Decode, 145, 16, 31, // Opcode: SU -/* 526 */ MCD_OPC_FilterValue, 128, 1, 10, 0, // Skip to: 541 -/* 531 */ MCD_OPC_CheckField, 16, 8, 0, 67, 31, // Skip to: 8540 -/* 537 */ MCD_OPC_Decode, 153, 15, 32, // Opcode: SSM -/* 541 */ MCD_OPC_FilterValue, 130, 1, 10, 0, // Skip to: 556 -/* 546 */ MCD_OPC_CheckField, 16, 8, 0, 52, 31, // Skip to: 8540 -/* 552 */ MCD_OPC_Decode, 197, 12, 32, // Opcode: LPSW -/* 556 */ MCD_OPC_FilterValue, 131, 1, 4, 0, // Skip to: 565 -/* 561 */ MCD_OPC_Decode, 198, 8, 33, // Opcode: DIAG -/* 565 */ MCD_OPC_FilterValue, 132, 1, 4, 0, // Skip to: 574 -/* 570 */ MCD_OPC_Decode, 255, 3, 34, // Opcode: BRXH -/* 574 */ MCD_OPC_FilterValue, 133, 1, 4, 0, // Skip to: 583 -/* 579 */ MCD_OPC_Decode, 129, 4, 34, // Opcode: BRXLE -/* 583 */ MCD_OPC_FilterValue, 134, 1, 4, 0, // Skip to: 592 -/* 588 */ MCD_OPC_Decode, 134, 4, 35, // Opcode: BXH -/* 592 */ MCD_OPC_FilterValue, 135, 1, 4, 0, // Skip to: 601 -/* 597 */ MCD_OPC_Decode, 136, 4, 35, // Opcode: BXLE -/* 601 */ MCD_OPC_FilterValue, 136, 1, 10, 0, // Skip to: 616 -/* 606 */ MCD_OPC_CheckField, 16, 4, 0, 248, 30, // Skip to: 8540 -/* 612 */ MCD_OPC_Decode, 138, 15, 36, // Opcode: SRL -/* 616 */ MCD_OPC_FilterValue, 137, 1, 10, 0, // Skip to: 631 -/* 621 */ MCD_OPC_CheckField, 16, 4, 0, 233, 30, // Skip to: 8540 -/* 627 */ MCD_OPC_Decode, 235, 14, 36, // Opcode: SLL -/* 631 */ MCD_OPC_FilterValue, 138, 1, 10, 0, // Skip to: 646 -/* 636 */ MCD_OPC_CheckField, 16, 4, 0, 218, 30, // Skip to: 8540 -/* 642 */ MCD_OPC_Decode, 131, 15, 36, // Opcode: SRA -/* 646 */ MCD_OPC_FilterValue, 139, 1, 10, 0, // Skip to: 661 -/* 651 */ MCD_OPC_CheckField, 16, 4, 0, 203, 30, // Skip to: 8540 -/* 657 */ MCD_OPC_Decode, 216, 14, 36, // Opcode: SLA -/* 661 */ MCD_OPC_FilterValue, 140, 1, 10, 0, // Skip to: 676 -/* 666 */ MCD_OPC_CheckField, 16, 4, 0, 188, 30, // Skip to: 8540 -/* 672 */ MCD_OPC_Decode, 135, 15, 37, // Opcode: SRDL -/* 676 */ MCD_OPC_FilterValue, 141, 1, 10, 0, // Skip to: 691 -/* 681 */ MCD_OPC_CheckField, 16, 4, 0, 173, 30, // Skip to: 8540 -/* 687 */ MCD_OPC_Decode, 224, 14, 37, // Opcode: SLDL -/* 691 */ MCD_OPC_FilterValue, 142, 1, 10, 0, // Skip to: 706 -/* 696 */ MCD_OPC_CheckField, 16, 4, 0, 158, 30, // Skip to: 8540 -/* 702 */ MCD_OPC_Decode, 134, 15, 37, // Opcode: SRDA -/* 706 */ MCD_OPC_FilterValue, 143, 1, 10, 0, // Skip to: 721 -/* 711 */ MCD_OPC_CheckField, 16, 4, 0, 143, 30, // Skip to: 8540 -/* 717 */ MCD_OPC_Decode, 223, 14, 37, // Opcode: SLDA -/* 721 */ MCD_OPC_FilterValue, 144, 1, 4, 0, // Skip to: 730 -/* 726 */ MCD_OPC_Decode, 188, 15, 33, // Opcode: STM -/* 730 */ MCD_OPC_FilterValue, 145, 1, 4, 0, // Skip to: 739 -/* 735 */ MCD_OPC_Decode, 175, 16, 38, // Opcode: TM -/* 739 */ MCD_OPC_FilterValue, 146, 1, 4, 0, // Skip to: 748 -/* 744 */ MCD_OPC_Decode, 205, 13, 38, // Opcode: MVI -/* 748 */ MCD_OPC_FilterValue, 147, 1, 10, 0, // Skip to: 763 -/* 753 */ MCD_OPC_CheckField, 16, 8, 0, 101, 30, // Skip to: 8540 -/* 759 */ MCD_OPC_Decode, 204, 16, 32, // Opcode: TS -/* 763 */ MCD_OPC_FilterValue, 148, 1, 4, 0, // Skip to: 772 -/* 768 */ MCD_OPC_Decode, 231, 13, 38, // Opcode: NI -/* 772 */ MCD_OPC_FilterValue, 149, 1, 4, 0, // Skip to: 781 -/* 777 */ MCD_OPC_Decode, 239, 6, 38, // Opcode: CLI -/* 781 */ MCD_OPC_FilterValue, 150, 1, 4, 0, // Skip to: 790 -/* 786 */ MCD_OPC_Decode, 249, 13, 38, // Opcode: OI -/* 790 */ MCD_OPC_FilterValue, 151, 1, 4, 0, // Skip to: 799 -/* 795 */ MCD_OPC_Decode, 231, 21, 38, // Opcode: XI -/* 799 */ MCD_OPC_FilterValue, 152, 1, 4, 0, // Skip to: 808 -/* 804 */ MCD_OPC_Decode, 225, 10, 33, // Opcode: LM -/* 808 */ MCD_OPC_FilterValue, 153, 1, 4, 0, // Skip to: 817 -/* 813 */ MCD_OPC_Decode, 185, 16, 33, // Opcode: TRACE -/* 817 */ MCD_OPC_FilterValue, 154, 1, 4, 0, // Skip to: 826 -/* 822 */ MCD_OPC_Decode, 244, 9, 39, // Opcode: LAM -/* 826 */ MCD_OPC_FilterValue, 155, 1, 4, 0, // Skip to: 835 -/* 831 */ MCD_OPC_Decode, 155, 15, 39, // Opcode: STAM -/* 835 */ MCD_OPC_FilterValue, 165, 1, 131, 0, // Skip to: 971 -/* 840 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 843 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 851 -/* 847 */ MCD_OPC_Decode, 140, 9, 40, // Opcode: IIHH -/* 851 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 859 -/* 855 */ MCD_OPC_Decode, 141, 9, 40, // Opcode: IIHL -/* 859 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 867 -/* 863 */ MCD_OPC_Decode, 143, 9, 41, // Opcode: IILH -/* 867 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 875 -/* 871 */ MCD_OPC_Decode, 144, 9, 41, // Opcode: IILL -/* 875 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 883 -/* 879 */ MCD_OPC_Decode, 234, 13, 40, // Opcode: NIHH -/* 883 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 891 -/* 887 */ MCD_OPC_Decode, 235, 13, 40, // Opcode: NIHL -/* 891 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 899 -/* 895 */ MCD_OPC_Decode, 237, 13, 41, // Opcode: NILH -/* 899 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 907 -/* 903 */ MCD_OPC_Decode, 238, 13, 41, // Opcode: NILL -/* 907 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 915 -/* 911 */ MCD_OPC_Decode, 251, 13, 40, // Opcode: OIHH -/* 915 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 923 -/* 919 */ MCD_OPC_Decode, 252, 13, 40, // Opcode: OIHL -/* 923 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 931 -/* 927 */ MCD_OPC_Decode, 254, 13, 41, // Opcode: OILH -/* 931 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 939 -/* 935 */ MCD_OPC_Decode, 255, 13, 41, // Opcode: OILL -/* 939 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 947 -/* 943 */ MCD_OPC_Decode, 219, 10, 42, // Opcode: LLIHH -/* 947 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 955 -/* 951 */ MCD_OPC_Decode, 220, 10, 42, // Opcode: LLIHL -/* 955 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 963 -/* 959 */ MCD_OPC_Decode, 222, 10, 42, // Opcode: LLILH -/* 963 */ MCD_OPC_FilterValue, 15, 149, 29, // Skip to: 8540 -/* 967 */ MCD_OPC_Decode, 223, 10, 42, // Opcode: LLILL -/* 971 */ MCD_OPC_FilterValue, 167, 1, 254, 0, // Skip to: 1230 -/* 976 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 979 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 987 -/* 983 */ MCD_OPC_Decode, 178, 16, 43, // Opcode: TMLH -/* 987 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 995 -/* 991 */ MCD_OPC_Decode, 179, 16, 43, // Opcode: TMLL -/* 995 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1003 -/* 999 */ MCD_OPC_Decode, 176, 16, 44, // Opcode: TMHH -/* 1003 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1011 -/* 1007 */ MCD_OPC_Decode, 177, 16, 44, // Opcode: TMHL -/* 1011 */ MCD_OPC_FilterValue, 4, 127, 0, // Skip to: 1142 -/* 1015 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 1018 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1026 -/* 1022 */ MCD_OPC_Decode, 196, 9, 45, // Opcode: JAsmO -/* 1026 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1034 -/* 1030 */ MCD_OPC_Decode, 180, 9, 45, // Opcode: JAsmH -/* 1034 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1042 -/* 1038 */ MCD_OPC_Decode, 190, 9, 45, // Opcode: JAsmNLE -/* 1042 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1050 -/* 1046 */ MCD_OPC_Decode, 182, 9, 45, // Opcode: JAsmL -/* 1050 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1058 -/* 1054 */ MCD_OPC_Decode, 188, 9, 45, // Opcode: JAsmNHE -/* 1058 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1066 -/* 1062 */ MCD_OPC_Decode, 184, 9, 45, // Opcode: JAsmLH -/* 1066 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1074 -/* 1070 */ MCD_OPC_Decode, 186, 9, 45, // Opcode: JAsmNE -/* 1074 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1082 -/* 1078 */ MCD_OPC_Decode, 179, 9, 45, // Opcode: JAsmE -/* 1082 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1090 -/* 1086 */ MCD_OPC_Decode, 191, 9, 45, // Opcode: JAsmNLH -/* 1090 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1098 -/* 1094 */ MCD_OPC_Decode, 181, 9, 45, // Opcode: JAsmHE -/* 1098 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1106 -/* 1102 */ MCD_OPC_Decode, 189, 9, 45, // Opcode: JAsmNL -/* 1106 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1114 -/* 1110 */ MCD_OPC_Decode, 183, 9, 45, // Opcode: JAsmLE -/* 1114 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1122 -/* 1118 */ MCD_OPC_Decode, 187, 9, 45, // Opcode: JAsmNH -/* 1122 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1130 -/* 1126 */ MCD_OPC_Decode, 193, 9, 45, // Opcode: JAsmNO -/* 1130 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1138 -/* 1134 */ MCD_OPC_Decode, 178, 9, 45, // Opcode: J -/* 1138 */ MCD_OPC_Decode, 249, 3, 46, // Opcode: BRCAsm -/* 1142 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1150 -/* 1146 */ MCD_OPC_Decode, 226, 3, 47, // Opcode: BRAS -/* 1150 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1158 -/* 1154 */ MCD_OPC_Decode, 252, 3, 48, // Opcode: BRCT -/* 1158 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1166 -/* 1162 */ MCD_OPC_Decode, 253, 3, 49, // Opcode: BRCTG -/* 1166 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1174 -/* 1170 */ MCD_OPC_Decode, 194, 10, 50, // Opcode: LHI -/* 1174 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1182 -/* 1178 */ MCD_OPC_Decode, 186, 10, 51, // Opcode: LGHI -/* 1182 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1190 -/* 1186 */ MCD_OPC_Decode, 253, 2, 52, // Opcode: AHI -/* 1190 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1198 -/* 1194 */ MCD_OPC_Decode, 245, 2, 53, // Opcode: AGHI -/* 1198 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1206 -/* 1202 */ MCD_OPC_Decode, 160, 13, 52, // Opcode: MHI -/* 1206 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1214 -/* 1210 */ MCD_OPC_Decode, 157, 13, 53, // Opcode: MGHI -/* 1214 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1222 -/* 1218 */ MCD_OPC_Decode, 175, 5, 50, // Opcode: CHI -/* 1222 */ MCD_OPC_FilterValue, 15, 146, 28, // Skip to: 8540 -/* 1226 */ MCD_OPC_Decode, 205, 4, 51, // Opcode: CGHI -/* 1230 */ MCD_OPC_FilterValue, 168, 1, 4, 0, // Skip to: 1239 -/* 1235 */ MCD_OPC_Decode, 196, 13, 54, // Opcode: MVCLE -/* 1239 */ MCD_OPC_FilterValue, 169, 1, 4, 0, // Skip to: 1248 -/* 1244 */ MCD_OPC_Decode, 227, 5, 54, // Opcode: CLCLE -/* 1248 */ MCD_OPC_FilterValue, 172, 1, 4, 0, // Skip to: 1257 -/* 1253 */ MCD_OPC_Decode, 192, 15, 38, // Opcode: STNSM -/* 1257 */ MCD_OPC_FilterValue, 173, 1, 4, 0, // Skip to: 1266 -/* 1262 */ MCD_OPC_Decode, 131, 16, 38, // Opcode: STOSM -/* 1266 */ MCD_OPC_FilterValue, 174, 1, 4, 0, // Skip to: 1275 -/* 1271 */ MCD_OPC_Decode, 214, 14, 55, // Opcode: SIGP -/* 1275 */ MCD_OPC_FilterValue, 175, 1, 4, 0, // Skip to: 1284 -/* 1280 */ MCD_OPC_Decode, 137, 13, 38, // Opcode: MC -/* 1284 */ MCD_OPC_FilterValue, 177, 1, 4, 0, // Skip to: 1293 -/* 1289 */ MCD_OPC_Decode, 203, 12, 21, // Opcode: LRA -/* 1293 */ MCD_OPC_FilterValue, 178, 1, 65, 5, // Skip to: 2643 -/* 1298 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 1301 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1309 -/* 1305 */ MCD_OPC_Decode, 187, 15, 32, // Opcode: STIDP -/* 1309 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1317 -/* 1313 */ MCD_OPC_Decode, 187, 14, 32, // Opcode: SCK -/* 1317 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1325 -/* 1321 */ MCD_OPC_Decode, 160, 15, 32, // Opcode: STCK -/* 1325 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1333 -/* 1329 */ MCD_OPC_Decode, 188, 14, 32, // Opcode: SCKC -/* 1333 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1341 -/* 1337 */ MCD_OPC_Decode, 161, 15, 32, // Opcode: STCKC -/* 1341 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1349 -/* 1345 */ MCD_OPC_Decode, 246, 14, 32, // Opcode: SPT -/* 1349 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1357 -/* 1353 */ MCD_OPC_Decode, 133, 16, 32, // Opcode: STPT -/* 1357 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1365 -/* 1361 */ MCD_OPC_Decode, 244, 14, 32, // Opcode: SPKA -/* 1365 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 1379 -/* 1369 */ MCD_OPC_CheckField, 0, 16, 0, 253, 27, // Skip to: 8540 -/* 1375 */ MCD_OPC_Decode, 145, 9, 0, // Opcode: IPK -/* 1379 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 1393 -/* 1383 */ MCD_OPC_CheckField, 0, 16, 0, 239, 27, // Skip to: 8540 -/* 1389 */ MCD_OPC_Decode, 155, 14, 0, // Opcode: PTLB -/* 1393 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 1401 -/* 1397 */ MCD_OPC_Decode, 247, 14, 32, // Opcode: SPX -/* 1401 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1409 -/* 1405 */ MCD_OPC_Decode, 134, 16, 32, // Opcode: STPX -/* 1409 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1417 -/* 1413 */ MCD_OPC_Decode, 157, 15, 32, // Opcode: STAP -/* 1417 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 1425 -/* 1421 */ MCD_OPC_Decode, 212, 14, 32, // Opcode: SIE -/* 1425 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1433 -/* 1429 */ MCD_OPC_Decode, 134, 14, 32, // Opcode: PC -/* 1433 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1441 -/* 1437 */ MCD_OPC_Decode, 178, 14, 32, // Opcode: SAC -/* 1441 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1449 -/* 1445 */ MCD_OPC_Decode, 178, 4, 32, // Opcode: CFC -/* 1449 */ MCD_OPC_FilterValue, 33, 24, 0, // Skip to: 1477 -/* 1453 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 1463 -/* 1459 */ MCD_OPC_Decode, 149, 9, 56, // Opcode: IPTEOptOpt -/* 1463 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 1473 -/* 1469 */ MCD_OPC_Decode, 148, 9, 57, // Opcode: IPTEOpt -/* 1473 */ MCD_OPC_Decode, 147, 9, 58, // Opcode: IPTE -/* 1477 */ MCD_OPC_FilterValue, 34, 16, 0, // Skip to: 1497 -/* 1481 */ MCD_OPC_CheckField, 8, 8, 0, 141, 27, // Skip to: 8540 -/* 1487 */ MCD_OPC_CheckField, 0, 4, 0, 135, 27, // Skip to: 8540 -/* 1493 */ MCD_OPC_Decode, 146, 9, 1, // Opcode: IPM -/* 1497 */ MCD_OPC_FilterValue, 35, 10, 0, // Skip to: 1511 -/* 1501 */ MCD_OPC_CheckField, 8, 8, 0, 121, 27, // Skip to: 8540 -/* 1507 */ MCD_OPC_Decode, 152, 9, 3, // Opcode: IVSK -/* 1511 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1531 -/* 1515 */ MCD_OPC_CheckField, 8, 8, 0, 107, 27, // Skip to: 8540 -/* 1521 */ MCD_OPC_CheckField, 0, 4, 0, 101, 27, // Skip to: 8540 -/* 1527 */ MCD_OPC_Decode, 255, 8, 1, // Opcode: IAC -/* 1531 */ MCD_OPC_FilterValue, 37, 16, 0, // Skip to: 1551 -/* 1535 */ MCD_OPC_CheckField, 8, 8, 0, 87, 27, // Skip to: 8540 -/* 1541 */ MCD_OPC_CheckField, 0, 4, 0, 81, 27, // Skip to: 8540 -/* 1547 */ MCD_OPC_Decode, 149, 15, 1, // Opcode: SSAR -/* 1551 */ MCD_OPC_FilterValue, 38, 16, 0, // Skip to: 1571 -/* 1555 */ MCD_OPC_CheckField, 8, 8, 0, 67, 27, // Skip to: 8540 -/* 1561 */ MCD_OPC_CheckField, 0, 4, 0, 61, 27, // Skip to: 8540 -/* 1567 */ MCD_OPC_Decode, 226, 8, 1, // Opcode: EPAR -/* 1571 */ MCD_OPC_FilterValue, 39, 16, 0, // Skip to: 1591 -/* 1575 */ MCD_OPC_CheckField, 8, 8, 0, 47, 27, // Skip to: 8540 -/* 1581 */ MCD_OPC_CheckField, 0, 4, 0, 41, 27, // Skip to: 8540 -/* 1587 */ MCD_OPC_Decode, 232, 8, 1, // Opcode: ESAR -/* 1591 */ MCD_OPC_FilterValue, 40, 10, 0, // Skip to: 1605 -/* 1595 */ MCD_OPC_CheckField, 8, 8, 0, 27, 27, // Skip to: 8540 -/* 1601 */ MCD_OPC_Decode, 151, 14, 59, // Opcode: PT -/* 1605 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 1619 -/* 1609 */ MCD_OPC_CheckField, 8, 8, 0, 13, 27, // Skip to: 8540 -/* 1615 */ MCD_OPC_Decode, 151, 9, 3, // Opcode: ISKE -/* 1619 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 1633 -/* 1623 */ MCD_OPC_CheckField, 8, 8, 0, 255, 26, // Skip to: 8540 -/* 1629 */ MCD_OPC_Decode, 171, 14, 59, // Opcode: RRBE -/* 1633 */ MCD_OPC_FilterValue, 43, 21, 0, // Skip to: 1658 -/* 1637 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 1640 */ MCD_OPC_FilterValue, 0, 240, 26, // Skip to: 8540 -/* 1644 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 1654 -/* 1650 */ MCD_OPC_Decode, 152, 15, 59, // Opcode: SSKEOpt -/* 1654 */ MCD_OPC_Decode, 151, 15, 60, // Opcode: SSKE -/* 1658 */ MCD_OPC_FilterValue, 44, 10, 0, // Skip to: 1672 -/* 1662 */ MCD_OPC_CheckField, 8, 8, 0, 216, 26, // Skip to: 8540 -/* 1668 */ MCD_OPC_Decode, 158, 16, 61, // Opcode: TB -/* 1672 */ MCD_OPC_FilterValue, 45, 10, 0, // Skip to: 1686 -/* 1676 */ MCD_OPC_CheckField, 8, 8, 0, 202, 26, // Skip to: 8540 -/* 1682 */ MCD_OPC_Decode, 212, 8, 13, // Opcode: DXR -/* 1686 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 1700 -/* 1690 */ MCD_OPC_CheckField, 8, 8, 0, 188, 26, // Skip to: 8540 -/* 1696 */ MCD_OPC_Decode, 141, 14, 61, // Opcode: PGIN -/* 1700 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 1714 -/* 1704 */ MCD_OPC_CheckField, 8, 8, 0, 174, 26, // Skip to: 8540 -/* 1710 */ MCD_OPC_Decode, 142, 14, 61, // Opcode: PGOUT -/* 1714 */ MCD_OPC_FilterValue, 48, 10, 0, // Skip to: 1728 -/* 1718 */ MCD_OPC_CheckField, 0, 16, 0, 160, 26, // Skip to: 8540 -/* 1724 */ MCD_OPC_Decode, 133, 8, 0, // Opcode: CSCH -/* 1728 */ MCD_OPC_FilterValue, 49, 10, 0, // Skip to: 1742 -/* 1732 */ MCD_OPC_CheckField, 0, 16, 0, 146, 26, // Skip to: 8540 -/* 1738 */ MCD_OPC_Decode, 254, 8, 0, // Opcode: HSCH -/* 1742 */ MCD_OPC_FilterValue, 50, 4, 0, // Skip to: 1750 -/* 1746 */ MCD_OPC_Decode, 170, 13, 32, // Opcode: MSCH -/* 1750 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 1758 -/* 1754 */ MCD_OPC_Decode, 150, 15, 32, // Opcode: SSCH -/* 1758 */ MCD_OPC_FilterValue, 52, 4, 0, // Skip to: 1766 -/* 1762 */ MCD_OPC_Decode, 140, 16, 32, // Opcode: STSCH -/* 1766 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 1774 -/* 1770 */ MCD_OPC_Decode, 205, 16, 32, // Opcode: TSCH -/* 1774 */ MCD_OPC_FilterValue, 54, 4, 0, // Skip to: 1782 -/* 1778 */ MCD_OPC_Decode, 182, 16, 32, // Opcode: TPI -/* 1782 */ MCD_OPC_FilterValue, 55, 10, 0, // Skip to: 1796 -/* 1786 */ MCD_OPC_CheckField, 0, 16, 0, 92, 26, // Skip to: 8540 -/* 1792 */ MCD_OPC_Decode, 180, 14, 0, // Opcode: SAL -/* 1796 */ MCD_OPC_FilterValue, 56, 10, 0, // Skip to: 1810 -/* 1800 */ MCD_OPC_CheckField, 0, 16, 0, 78, 26, // Skip to: 8540 -/* 1806 */ MCD_OPC_Decode, 175, 14, 0, // Opcode: RSCH -/* 1810 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 1818 -/* 1814 */ MCD_OPC_Decode, 168, 15, 32, // Opcode: STCRW -/* 1818 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 1826 -/* 1822 */ MCD_OPC_Decode, 167, 15, 32, // Opcode: STCPS -/* 1826 */ MCD_OPC_FilterValue, 59, 10, 0, // Skip to: 1840 -/* 1830 */ MCD_OPC_CheckField, 0, 16, 0, 48, 26, // Skip to: 8540 -/* 1836 */ MCD_OPC_Decode, 160, 14, 0, // Opcode: RCHP -/* 1840 */ MCD_OPC_FilterValue, 60, 10, 0, // Skip to: 1854 -/* 1844 */ MCD_OPC_CheckField, 0, 16, 0, 34, 26, // Skip to: 8540 -/* 1850 */ MCD_OPC_Decode, 186, 14, 0, // Opcode: SCHM -/* 1854 */ MCD_OPC_FilterValue, 64, 10, 0, // Skip to: 1868 -/* 1858 */ MCD_OPC_CheckField, 8, 8, 0, 20, 26, // Skip to: 8540 -/* 1864 */ MCD_OPC_Decode, 166, 3, 61, // Opcode: BAKR -/* 1868 */ MCD_OPC_FilterValue, 65, 10, 0, // Skip to: 1882 -/* 1872 */ MCD_OPC_CheckField, 8, 8, 0, 6, 26, // Skip to: 8540 -/* 1878 */ MCD_OPC_Decode, 223, 5, 62, // Opcode: CKSM -/* 1882 */ MCD_OPC_FilterValue, 68, 10, 0, // Skip to: 1896 -/* 1886 */ MCD_OPC_CheckField, 8, 8, 0, 248, 25, // Skip to: 8540 -/* 1892 */ MCD_OPC_Decode, 251, 14, 11, // Opcode: SQDR -/* 1896 */ MCD_OPC_FilterValue, 69, 10, 0, // Skip to: 1910 -/* 1900 */ MCD_OPC_CheckField, 8, 8, 0, 234, 25, // Skip to: 8540 -/* 1906 */ MCD_OPC_Decode, 255, 14, 16, // Opcode: SQER -/* 1910 */ MCD_OPC_FilterValue, 70, 10, 0, // Skip to: 1924 -/* 1914 */ MCD_OPC_CheckField, 8, 8, 0, 220, 25, // Skip to: 8540 -/* 1920 */ MCD_OPC_Decode, 142, 16, 59, // Opcode: STURA -/* 1924 */ MCD_OPC_FilterValue, 71, 16, 0, // Skip to: 1944 -/* 1928 */ MCD_OPC_CheckField, 8, 8, 0, 206, 25, // Skip to: 8540 -/* 1934 */ MCD_OPC_CheckField, 0, 4, 0, 200, 25, // Skip to: 8540 -/* 1940 */ MCD_OPC_Decode, 189, 13, 63, // Opcode: MSTA -/* 1944 */ MCD_OPC_FilterValue, 72, 10, 0, // Skip to: 1958 -/* 1948 */ MCD_OPC_CheckField, 0, 16, 0, 186, 25, // Skip to: 8540 -/* 1954 */ MCD_OPC_Decode, 133, 14, 0, // Opcode: PALB -/* 1958 */ MCD_OPC_FilterValue, 73, 10, 0, // Skip to: 1972 -/* 1962 */ MCD_OPC_CheckField, 8, 8, 0, 172, 25, // Skip to: 8540 -/* 1968 */ MCD_OPC_Decode, 229, 8, 8, // Opcode: EREG -/* 1972 */ MCD_OPC_FilterValue, 74, 10, 0, // Skip to: 1986 -/* 1976 */ MCD_OPC_CheckField, 8, 8, 0, 158, 25, // Skip to: 8540 -/* 1982 */ MCD_OPC_Decode, 235, 8, 64, // Opcode: ESTA -/* 1986 */ MCD_OPC_FilterValue, 75, 10, 0, // Skip to: 2000 -/* 1990 */ MCD_OPC_CheckField, 8, 8, 0, 144, 25, // Skip to: 8540 -/* 1996 */ MCD_OPC_Decode, 232, 12, 59, // Opcode: LURA -/* 2000 */ MCD_OPC_FilterValue, 76, 10, 0, // Skip to: 2014 -/* 2004 */ MCD_OPC_CheckField, 8, 8, 0, 130, 25, // Skip to: 8540 -/* 2010 */ MCD_OPC_Decode, 157, 16, 65, // Opcode: TAR -/* 2014 */ MCD_OPC_FilterValue, 77, 10, 0, // Skip to: 2028 -/* 2018 */ MCD_OPC_CheckField, 8, 8, 0, 116, 25, // Skip to: 8540 -/* 2024 */ MCD_OPC_Decode, 213, 7, 66, // Opcode: CPYA -/* 2028 */ MCD_OPC_FilterValue, 78, 10, 0, // Skip to: 2042 -/* 2032 */ MCD_OPC_CheckField, 8, 8, 0, 102, 25, // Skip to: 8540 -/* 2038 */ MCD_OPC_Decode, 184, 14, 65, // Opcode: SAR -/* 2042 */ MCD_OPC_FilterValue, 79, 10, 0, // Skip to: 2056 -/* 2046 */ MCD_OPC_CheckField, 8, 8, 0, 88, 25, // Skip to: 8540 -/* 2052 */ MCD_OPC_Decode, 215, 8, 67, // Opcode: EAR -/* 2056 */ MCD_OPC_FilterValue, 80, 10, 0, // Skip to: 2070 -/* 2060 */ MCD_OPC_CheckField, 8, 8, 0, 74, 25, // Skip to: 8540 -/* 2066 */ MCD_OPC_Decode, 136, 8, 68, // Opcode: CSP -/* 2070 */ MCD_OPC_FilterValue, 82, 10, 0, // Skip to: 2084 -/* 2074 */ MCD_OPC_CheckField, 8, 8, 0, 60, 25, // Skip to: 8540 -/* 2080 */ MCD_OPC_Decode, 187, 13, 9, // Opcode: MSR -/* 2084 */ MCD_OPC_FilterValue, 84, 10, 0, // Skip to: 2098 -/* 2088 */ MCD_OPC_CheckField, 8, 8, 0, 46, 25, // Skip to: 8540 -/* 2094 */ MCD_OPC_Decode, 209, 13, 61, // Opcode: MVPG -/* 2098 */ MCD_OPC_FilterValue, 85, 10, 0, // Skip to: 2112 -/* 2102 */ MCD_OPC_CheckField, 8, 8, 0, 32, 25, // Skip to: 8540 -/* 2108 */ MCD_OPC_Decode, 210, 13, 69, // Opcode: MVST -/* 2112 */ MCD_OPC_FilterValue, 87, 10, 0, // Skip to: 2126 -/* 2116 */ MCD_OPC_CheckField, 8, 8, 0, 18, 25, // Skip to: 8540 -/* 2122 */ MCD_OPC_Decode, 152, 8, 7, // Opcode: CUSE -/* 2126 */ MCD_OPC_FilterValue, 88, 10, 0, // Skip to: 2140 -/* 2130 */ MCD_OPC_CheckField, 8, 8, 0, 4, 25, // Skip to: 8540 -/* 2136 */ MCD_OPC_Decode, 132, 4, 61, // Opcode: BSG -/* 2140 */ MCD_OPC_FilterValue, 90, 10, 0, // Skip to: 2154 -/* 2144 */ MCD_OPC_CheckField, 8, 8, 0, 246, 24, // Skip to: 8540 -/* 2150 */ MCD_OPC_Decode, 131, 4, 61, // Opcode: BSA -/* 2154 */ MCD_OPC_FilterValue, 93, 10, 0, // Skip to: 2168 -/* 2158 */ MCD_OPC_CheckField, 8, 8, 0, 232, 24, // Skip to: 8540 -/* 2164 */ MCD_OPC_Decode, 189, 7, 69, // Opcode: CLST -/* 2168 */ MCD_OPC_FilterValue, 94, 10, 0, // Skip to: 2182 -/* 2172 */ MCD_OPC_CheckField, 8, 8, 0, 218, 24, // Skip to: 8540 -/* 2178 */ MCD_OPC_Decode, 145, 15, 69, // Opcode: SRST -/* 2182 */ MCD_OPC_FilterValue, 99, 10, 0, // Skip to: 2196 -/* 2186 */ MCD_OPC_CheckField, 8, 8, 0, 204, 24, // Skip to: 8540 -/* 2192 */ MCD_OPC_Decode, 205, 7, 7, // Opcode: CMPSC -/* 2196 */ MCD_OPC_FilterValue, 116, 4, 0, // Skip to: 2204 -/* 2200 */ MCD_OPC_Decode, 213, 14, 32, // Opcode: SIGA -/* 2204 */ MCD_OPC_FilterValue, 118, 10, 0, // Skip to: 2218 -/* 2208 */ MCD_OPC_CheckField, 0, 16, 0, 182, 24, // Skip to: 8540 -/* 2214 */ MCD_OPC_Decode, 237, 21, 0, // Opcode: XSCH -/* 2218 */ MCD_OPC_FilterValue, 119, 4, 0, // Skip to: 2226 -/* 2222 */ MCD_OPC_Decode, 170, 14, 32, // Opcode: RP -/* 2226 */ MCD_OPC_FilterValue, 120, 4, 0, // Skip to: 2234 -/* 2230 */ MCD_OPC_Decode, 162, 15, 32, // Opcode: STCKE -/* 2234 */ MCD_OPC_FilterValue, 121, 4, 0, // Skip to: 2242 -/* 2238 */ MCD_OPC_Decode, 179, 14, 32, // Opcode: SACF -/* 2242 */ MCD_OPC_FilterValue, 124, 4, 0, // Skip to: 2250 -/* 2246 */ MCD_OPC_Decode, 163, 15, 32, // Opcode: STCKF -/* 2250 */ MCD_OPC_FilterValue, 125, 4, 0, // Skip to: 2258 -/* 2254 */ MCD_OPC_Decode, 141, 16, 32, // Opcode: STSI -/* 2258 */ MCD_OPC_FilterValue, 128, 1, 4, 0, // Skip to: 2267 -/* 2263 */ MCD_OPC_Decode, 194, 12, 32, // Opcode: LPP -/* 2267 */ MCD_OPC_FilterValue, 132, 1, 4, 0, // Skip to: 2276 -/* 2272 */ MCD_OPC_Decode, 132, 10, 32, // Opcode: LCCTL -/* 2276 */ MCD_OPC_FilterValue, 133, 1, 4, 0, // Skip to: 2285 -/* 2281 */ MCD_OPC_Decode, 183, 12, 32, // Opcode: LPCTL -/* 2285 */ MCD_OPC_FilterValue, 134, 1, 4, 0, // Skip to: 2294 -/* 2290 */ MCD_OPC_Decode, 159, 14, 32, // Opcode: QSI -/* 2294 */ MCD_OPC_FilterValue, 135, 1, 4, 0, // Skip to: 2303 -/* 2299 */ MCD_OPC_Decode, 214, 12, 32, // Opcode: LSCTL -/* 2303 */ MCD_OPC_FilterValue, 142, 1, 4, 0, // Skip to: 2312 -/* 2308 */ MCD_OPC_Decode, 158, 14, 32, // Opcode: QCTRI -/* 2312 */ MCD_OPC_FilterValue, 153, 1, 4, 0, // Skip to: 2321 -/* 2317 */ MCD_OPC_Decode, 141, 15, 70, // Opcode: SRNM -/* 2321 */ MCD_OPC_FilterValue, 156, 1, 4, 0, // Skip to: 2330 -/* 2326 */ MCD_OPC_Decode, 179, 15, 32, // Opcode: STFPC -/* 2330 */ MCD_OPC_FilterValue, 157, 1, 4, 0, // Skip to: 2339 -/* 2335 */ MCD_OPC_Decode, 174, 10, 32, // Opcode: LFPC -/* 2339 */ MCD_OPC_FilterValue, 165, 1, 10, 0, // Skip to: 2354 -/* 2344 */ MCD_OPC_CheckField, 8, 8, 0, 46, 24, // Skip to: 8540 -/* 2350 */ MCD_OPC_Decode, 189, 16, 71, // Opcode: TRE -/* 2354 */ MCD_OPC_FilterValue, 166, 1, 21, 0, // Skip to: 2380 -/* 2359 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 2362 */ MCD_OPC_FilterValue, 0, 30, 24, // Skip to: 8540 -/* 2366 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 2376 -/* 2372 */ MCD_OPC_Decode, 146, 8, 7, // Opcode: CU21Opt -/* 2376 */ MCD_OPC_Decode, 145, 8, 72, // Opcode: CU21 -/* 2380 */ MCD_OPC_FilterValue, 167, 1, 21, 0, // Skip to: 2406 -/* 2385 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 2388 */ MCD_OPC_FilterValue, 0, 4, 24, // Skip to: 8540 -/* 2392 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 2402 -/* 2398 */ MCD_OPC_Decode, 142, 8, 7, // Opcode: CU12Opt -/* 2402 */ MCD_OPC_Decode, 141, 8, 72, // Opcode: CU12 -/* 2406 */ MCD_OPC_FilterValue, 176, 1, 4, 0, // Skip to: 2415 -/* 2411 */ MCD_OPC_Decode, 178, 15, 32, // Opcode: STFLE -/* 2415 */ MCD_OPC_FilterValue, 177, 1, 4, 0, // Skip to: 2424 -/* 2420 */ MCD_OPC_Decode, 177, 15, 32, // Opcode: STFL -/* 2424 */ MCD_OPC_FilterValue, 178, 1, 4, 0, // Skip to: 2433 -/* 2429 */ MCD_OPC_Decode, 198, 12, 32, // Opcode: LPSWE -/* 2433 */ MCD_OPC_FilterValue, 184, 1, 8, 0, // Skip to: 2446 -/* 2438 */ MCD_OPC_CheckPredicate, 0, 210, 23, // Skip to: 8540 -/* 2442 */ MCD_OPC_Decode, 142, 15, 70, // Opcode: SRNMB -/* 2446 */ MCD_OPC_FilterValue, 185, 1, 4, 0, // Skip to: 2455 -/* 2451 */ MCD_OPC_Decode, 143, 15, 70, // Opcode: SRNMT -/* 2455 */ MCD_OPC_FilterValue, 189, 1, 4, 0, // Skip to: 2464 -/* 2460 */ MCD_OPC_Decode, 171, 10, 32, // Opcode: LFAS -/* 2464 */ MCD_OPC_FilterValue, 224, 1, 10, 0, // Skip to: 2479 -/* 2469 */ MCD_OPC_CheckField, 8, 8, 0, 177, 23, // Skip to: 8540 -/* 2475 */ MCD_OPC_Decode, 185, 14, 61, // Opcode: SCCTR -/* 2479 */ MCD_OPC_FilterValue, 225, 1, 10, 0, // Skip to: 2494 -/* 2484 */ MCD_OPC_CheckField, 8, 8, 0, 162, 23, // Skip to: 8540 -/* 2490 */ MCD_OPC_Decode, 243, 14, 61, // Opcode: SPCTR -/* 2494 */ MCD_OPC_FilterValue, 228, 1, 10, 0, // Skip to: 2509 -/* 2499 */ MCD_OPC_CheckField, 8, 8, 0, 147, 23, // Skip to: 8540 -/* 2505 */ MCD_OPC_Decode, 217, 8, 61, // Opcode: ECCTR -/* 2509 */ MCD_OPC_FilterValue, 229, 1, 10, 0, // Skip to: 2524 -/* 2514 */ MCD_OPC_CheckField, 8, 8, 0, 132, 23, // Skip to: 8540 -/* 2520 */ MCD_OPC_Decode, 227, 8, 61, // Opcode: EPCTR -/* 2524 */ MCD_OPC_FilterValue, 232, 1, 14, 0, // Skip to: 2543 -/* 2529 */ MCD_OPC_CheckPredicate, 1, 119, 23, // Skip to: 8540 -/* 2533 */ MCD_OPC_CheckField, 8, 4, 0, 113, 23, // Skip to: 8540 -/* 2539 */ MCD_OPC_Decode, 147, 14, 73, // Opcode: PPA -/* 2543 */ MCD_OPC_FilterValue, 236, 1, 20, 0, // Skip to: 2568 -/* 2548 */ MCD_OPC_CheckPredicate, 2, 100, 23, // Skip to: 8540 -/* 2552 */ MCD_OPC_CheckField, 8, 8, 0, 94, 23, // Skip to: 8540 -/* 2558 */ MCD_OPC_CheckField, 0, 4, 0, 88, 23, // Skip to: 8540 -/* 2564 */ MCD_OPC_Decode, 237, 8, 1, // Opcode: ETND -/* 2568 */ MCD_OPC_FilterValue, 237, 1, 10, 0, // Skip to: 2583 -/* 2573 */ MCD_OPC_CheckField, 8, 8, 0, 73, 23, // Skip to: 8540 -/* 2579 */ MCD_OPC_Decode, 218, 8, 59, // Opcode: ECPGA -/* 2583 */ MCD_OPC_FilterValue, 248, 1, 14, 0, // Skip to: 2602 -/* 2588 */ MCD_OPC_CheckPredicate, 2, 60, 23, // Skip to: 8540 -/* 2592 */ MCD_OPC_CheckField, 0, 16, 0, 54, 23, // Skip to: 8540 -/* 2598 */ MCD_OPC_Decode, 172, 16, 0, // Opcode: TEND -/* 2602 */ MCD_OPC_FilterValue, 250, 1, 14, 0, // Skip to: 2621 -/* 2607 */ MCD_OPC_CheckPredicate, 3, 41, 23, // Skip to: 8540 -/* 2611 */ MCD_OPC_CheckField, 8, 8, 0, 35, 23, // Skip to: 8540 -/* 2617 */ MCD_OPC_Decode, 232, 13, 74, // Opcode: NIAI -/* 2621 */ MCD_OPC_FilterValue, 252, 1, 8, 0, // Skip to: 2634 -/* 2626 */ MCD_OPC_CheckPredicate, 2, 22, 23, // Skip to: 8540 -/* 2630 */ MCD_OPC_Decode, 155, 16, 32, // Opcode: TABORT -/* 2634 */ MCD_OPC_FilterValue, 255, 1, 13, 23, // Skip to: 8540 -/* 2639 */ MCD_OPC_Decode, 188, 16, 32, // Opcode: TRAP4 -/* 2643 */ MCD_OPC_FilterValue, 179, 1, 122, 10, // Skip to: 5330 -/* 2648 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 2651 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 2665 -/* 2655 */ MCD_OPC_CheckField, 8, 8, 0, 247, 22, // Skip to: 8540 -/* 2661 */ MCD_OPC_Decode, 190, 12, 16, // Opcode: LPEBR -/* 2665 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 2679 -/* 2669 */ MCD_OPC_CheckField, 8, 8, 0, 233, 22, // Skip to: 8540 -/* 2675 */ MCD_OPC_Decode, 234, 10, 16, // Opcode: LNEBR -/* 2679 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 2693 -/* 2683 */ MCD_OPC_CheckField, 8, 8, 0, 219, 22, // Skip to: 8540 -/* 2689 */ MCD_OPC_Decode, 220, 12, 16, // Opcode: LTEBR -/* 2693 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 2707 -/* 2697 */ MCD_OPC_CheckField, 8, 8, 0, 205, 22, // Skip to: 8540 -/* 2703 */ MCD_OPC_Decode, 137, 10, 16, // Opcode: LCEBR -/* 2707 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 2721 -/* 2711 */ MCD_OPC_CheckField, 8, 8, 0, 191, 22, // Skip to: 8540 -/* 2717 */ MCD_OPC_Decode, 150, 10, 75, // Opcode: LDEBR -/* 2721 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2735 -/* 2725 */ MCD_OPC_CheckField, 8, 8, 0, 177, 22, // Skip to: 8540 -/* 2731 */ MCD_OPC_Decode, 236, 12, 76, // Opcode: LXDBR -/* 2735 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2749 -/* 2739 */ MCD_OPC_CheckField, 8, 8, 0, 163, 22, // Skip to: 8540 -/* 2745 */ MCD_OPC_Decode, 241, 12, 77, // Opcode: LXEBR -/* 2749 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 2763 -/* 2753 */ MCD_OPC_CheckField, 8, 8, 0, 149, 22, // Skip to: 8540 -/* 2759 */ MCD_OPC_Decode, 215, 13, 14, // Opcode: MXDBR -/* 2763 */ MCD_OPC_FilterValue, 8, 10, 0, // Skip to: 2777 -/* 2767 */ MCD_OPC_CheckField, 8, 8, 0, 135, 22, // Skip to: 8540 -/* 2773 */ MCD_OPC_Decode, 224, 9, 16, // Opcode: KEBR -/* 2777 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 2791 -/* 2781 */ MCD_OPC_CheckField, 8, 8, 0, 121, 22, // Skip to: 8540 -/* 2787 */ MCD_OPC_Decode, 166, 4, 16, // Opcode: CEBR -/* 2791 */ MCD_OPC_FilterValue, 10, 10, 0, // Skip to: 2805 -/* 2795 */ MCD_OPC_CheckField, 8, 8, 0, 107, 22, // Skip to: 8540 -/* 2801 */ MCD_OPC_Decode, 237, 2, 18, // Opcode: AEBR -/* 2805 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 2819 -/* 2809 */ MCD_OPC_CheckField, 8, 8, 0, 93, 22, // Skip to: 8540 -/* 2815 */ MCD_OPC_Decode, 198, 14, 18, // Opcode: SEBR -/* 2819 */ MCD_OPC_FilterValue, 12, 10, 0, // Skip to: 2833 -/* 2823 */ MCD_OPC_CheckField, 8, 8, 0, 79, 22, // Skip to: 8540 -/* 2829 */ MCD_OPC_Decode, 143, 13, 19, // Opcode: MDEBR -/* 2833 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 2847 -/* 2837 */ MCD_OPC_CheckField, 8, 8, 0, 65, 22, // Skip to: 8540 -/* 2843 */ MCD_OPC_Decode, 196, 8, 18, // Opcode: DEBR -/* 2847 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 2861 -/* 2851 */ MCD_OPC_CheckField, 8, 4, 0, 51, 22, // Skip to: 8540 -/* 2857 */ MCD_OPC_Decode, 129, 13, 78, // Opcode: MAEBR -/* 2861 */ MCD_OPC_FilterValue, 15, 10, 0, // Skip to: 2875 -/* 2865 */ MCD_OPC_CheckField, 8, 4, 0, 37, 22, // Skip to: 8540 -/* 2871 */ MCD_OPC_Decode, 177, 13, 78, // Opcode: MSEBR -/* 2875 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 2889 -/* 2879 */ MCD_OPC_CheckField, 8, 8, 0, 23, 22, // Skip to: 8540 -/* 2885 */ MCD_OPC_Decode, 185, 12, 11, // Opcode: LPDBR -/* 2889 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 2903 -/* 2893 */ MCD_OPC_CheckField, 8, 8, 0, 9, 22, // Skip to: 8540 -/* 2899 */ MCD_OPC_Decode, 230, 10, 11, // Opcode: LNDBR -/* 2903 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 2917 -/* 2907 */ MCD_OPC_CheckField, 8, 8, 0, 251, 21, // Skip to: 8540 -/* 2913 */ MCD_OPC_Decode, 216, 12, 11, // Opcode: LTDBR -/* 2917 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 2931 -/* 2921 */ MCD_OPC_CheckField, 8, 8, 0, 237, 21, // Skip to: 8540 -/* 2927 */ MCD_OPC_Decode, 133, 10, 11, // Opcode: LCDBR -/* 2931 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 2945 -/* 2935 */ MCD_OPC_CheckField, 8, 8, 0, 223, 21, // Skip to: 8540 -/* 2941 */ MCD_OPC_Decode, 254, 14, 16, // Opcode: SQEBR -/* 2945 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 2959 -/* 2949 */ MCD_OPC_CheckField, 8, 8, 0, 209, 21, // Skip to: 8540 -/* 2955 */ MCD_OPC_Decode, 250, 14, 11, // Opcode: SQDBR -/* 2959 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 2973 -/* 2963 */ MCD_OPC_CheckField, 8, 8, 0, 195, 21, // Skip to: 8540 -/* 2969 */ MCD_OPC_Decode, 128, 15, 79, // Opcode: SQXBR -/* 2973 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 2987 -/* 2977 */ MCD_OPC_CheckField, 8, 8, 0, 181, 21, // Skip to: 8540 -/* 2983 */ MCD_OPC_Decode, 151, 13, 18, // Opcode: MEEBR -/* 2987 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 3001 -/* 2991 */ MCD_OPC_CheckField, 8, 8, 0, 167, 21, // Skip to: 8540 -/* 2997 */ MCD_OPC_Decode, 221, 9, 11, // Opcode: KDBR -/* 3001 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 3015 -/* 3005 */ MCD_OPC_CheckField, 8, 8, 0, 153, 21, // Skip to: 8540 -/* 3011 */ MCD_OPC_Decode, 141, 4, 11, // Opcode: CDBR -/* 3015 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 3029 -/* 3019 */ MCD_OPC_CheckField, 8, 8, 0, 139, 21, // Skip to: 8540 -/* 3025 */ MCD_OPC_Decode, 231, 2, 15, // Opcode: ADBR -/* 3029 */ MCD_OPC_FilterValue, 27, 10, 0, // Skip to: 3043 -/* 3033 */ MCD_OPC_CheckField, 8, 8, 0, 125, 21, // Skip to: 8540 -/* 3039 */ MCD_OPC_Decode, 192, 14, 15, // Opcode: SDBR -/* 3043 */ MCD_OPC_FilterValue, 28, 10, 0, // Skip to: 3057 -/* 3047 */ MCD_OPC_CheckField, 8, 8, 0, 111, 21, // Skip to: 8540 -/* 3053 */ MCD_OPC_Decode, 140, 13, 15, // Opcode: MDBR -/* 3057 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 3071 -/* 3061 */ MCD_OPC_CheckField, 8, 8, 0, 97, 21, // Skip to: 8540 -/* 3067 */ MCD_OPC_Decode, 190, 8, 15, // Opcode: DDBR -/* 3071 */ MCD_OPC_FilterValue, 30, 10, 0, // Skip to: 3085 -/* 3075 */ MCD_OPC_CheckField, 8, 4, 0, 83, 21, // Skip to: 8540 -/* 3081 */ MCD_OPC_Decode, 253, 12, 80, // Opcode: MADBR -/* 3085 */ MCD_OPC_FilterValue, 31, 10, 0, // Skip to: 3099 -/* 3089 */ MCD_OPC_CheckField, 8, 4, 0, 69, 21, // Skip to: 8540 -/* 3095 */ MCD_OPC_Decode, 173, 13, 80, // Opcode: MSDBR -/* 3099 */ MCD_OPC_FilterValue, 36, 10, 0, // Skip to: 3113 -/* 3103 */ MCD_OPC_CheckField, 8, 8, 0, 55, 21, // Skip to: 8540 -/* 3109 */ MCD_OPC_Decode, 151, 10, 75, // Opcode: LDER -/* 3113 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 3127 -/* 3117 */ MCD_OPC_CheckField, 8, 8, 0, 41, 21, // Skip to: 8540 -/* 3123 */ MCD_OPC_Decode, 237, 12, 76, // Opcode: LXDR -/* 3127 */ MCD_OPC_FilterValue, 38, 10, 0, // Skip to: 3141 -/* 3131 */ MCD_OPC_CheckField, 8, 8, 0, 27, 21, // Skip to: 8540 -/* 3137 */ MCD_OPC_Decode, 242, 12, 77, // Opcode: LXER -/* 3141 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 3155 -/* 3145 */ MCD_OPC_CheckField, 8, 4, 0, 13, 21, // Skip to: 8540 -/* 3151 */ MCD_OPC_Decode, 130, 13, 78, // Opcode: MAER -/* 3155 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 3169 -/* 3159 */ MCD_OPC_CheckField, 8, 4, 0, 255, 20, // Skip to: 8540 -/* 3165 */ MCD_OPC_Decode, 178, 13, 78, // Opcode: MSER -/* 3169 */ MCD_OPC_FilterValue, 54, 10, 0, // Skip to: 3183 -/* 3173 */ MCD_OPC_CheckField, 8, 8, 0, 241, 20, // Skip to: 8540 -/* 3179 */ MCD_OPC_Decode, 129, 15, 79, // Opcode: SQXR -/* 3183 */ MCD_OPC_FilterValue, 55, 10, 0, // Skip to: 3197 -/* 3187 */ MCD_OPC_CheckField, 8, 8, 0, 227, 20, // Skip to: 8540 -/* 3193 */ MCD_OPC_Decode, 152, 13, 18, // Opcode: MEER -/* 3197 */ MCD_OPC_FilterValue, 56, 10, 0, // Skip to: 3211 -/* 3201 */ MCD_OPC_CheckField, 8, 4, 0, 213, 20, // Skip to: 8540 -/* 3207 */ MCD_OPC_Decode, 135, 13, 80, // Opcode: MAYLR -/* 3211 */ MCD_OPC_FilterValue, 57, 10, 0, // Skip to: 3225 -/* 3215 */ MCD_OPC_CheckField, 8, 4, 0, 199, 20, // Skip to: 8540 -/* 3221 */ MCD_OPC_Decode, 224, 13, 81, // Opcode: MYLR -/* 3225 */ MCD_OPC_FilterValue, 58, 10, 0, // Skip to: 3239 -/* 3229 */ MCD_OPC_CheckField, 8, 4, 0, 185, 20, // Skip to: 8540 -/* 3235 */ MCD_OPC_Decode, 136, 13, 82, // Opcode: MAYR -/* 3239 */ MCD_OPC_FilterValue, 59, 10, 0, // Skip to: 3253 -/* 3243 */ MCD_OPC_CheckField, 8, 4, 0, 171, 20, // Skip to: 8540 -/* 3249 */ MCD_OPC_Decode, 225, 13, 83, // Opcode: MYR -/* 3253 */ MCD_OPC_FilterValue, 60, 10, 0, // Skip to: 3267 -/* 3257 */ MCD_OPC_CheckField, 8, 4, 0, 157, 20, // Skip to: 8540 -/* 3263 */ MCD_OPC_Decode, 133, 13, 80, // Opcode: MAYHR -/* 3267 */ MCD_OPC_FilterValue, 61, 10, 0, // Skip to: 3281 -/* 3271 */ MCD_OPC_CheckField, 8, 4, 0, 143, 20, // Skip to: 8540 -/* 3277 */ MCD_OPC_Decode, 222, 13, 81, // Opcode: MYHR -/* 3281 */ MCD_OPC_FilterValue, 62, 10, 0, // Skip to: 3295 -/* 3285 */ MCD_OPC_CheckField, 8, 4, 0, 129, 20, // Skip to: 8540 -/* 3291 */ MCD_OPC_Decode, 254, 12, 80, // Opcode: MADR -/* 3295 */ MCD_OPC_FilterValue, 63, 10, 0, // Skip to: 3309 -/* 3299 */ MCD_OPC_CheckField, 8, 4, 0, 115, 20, // Skip to: 8540 -/* 3305 */ MCD_OPC_Decode, 174, 13, 80, // Opcode: MSDR -/* 3309 */ MCD_OPC_FilterValue, 64, 10, 0, // Skip to: 3323 -/* 3313 */ MCD_OPC_CheckField, 8, 8, 0, 101, 20, // Skip to: 8540 -/* 3319 */ MCD_OPC_Decode, 200, 12, 79, // Opcode: LPXBR -/* 3323 */ MCD_OPC_FilterValue, 65, 10, 0, // Skip to: 3337 -/* 3327 */ MCD_OPC_CheckField, 8, 8, 0, 87, 20, // Skip to: 8540 -/* 3333 */ MCD_OPC_Decode, 239, 10, 79, // Opcode: LNXBR -/* 3337 */ MCD_OPC_FilterValue, 66, 10, 0, // Skip to: 3351 -/* 3341 */ MCD_OPC_CheckField, 8, 8, 0, 73, 20, // Skip to: 8540 -/* 3347 */ MCD_OPC_Decode, 228, 12, 79, // Opcode: LTXBR -/* 3351 */ MCD_OPC_FilterValue, 67, 10, 0, // Skip to: 3365 -/* 3355 */ MCD_OPC_CheckField, 8, 8, 0, 59, 20, // Skip to: 8540 -/* 3361 */ MCD_OPC_Decode, 144, 10, 79, // Opcode: LCXBR -/* 3365 */ MCD_OPC_FilterValue, 68, 18, 0, // Skip to: 3387 -/* 3369 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3379 -/* 3375 */ MCD_OPC_Decode, 162, 10, 17, // Opcode: LEDBR -/* 3379 */ MCD_OPC_CheckPredicate, 0, 37, 20, // Skip to: 8540 -/* 3383 */ MCD_OPC_Decode, 163, 10, 84, // Opcode: LEDBRA -/* 3387 */ MCD_OPC_FilterValue, 69, 18, 0, // Skip to: 3409 -/* 3391 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3401 -/* 3397 */ MCD_OPC_Decode, 156, 10, 79, // Opcode: LDXBR -/* 3401 */ MCD_OPC_CheckPredicate, 0, 15, 20, // Skip to: 8540 -/* 3405 */ MCD_OPC_Decode, 157, 10, 85, // Opcode: LDXBRA -/* 3409 */ MCD_OPC_FilterValue, 70, 18, 0, // Skip to: 3431 -/* 3413 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3423 -/* 3419 */ MCD_OPC_Decode, 167, 10, 79, // Opcode: LEXBR -/* 3423 */ MCD_OPC_CheckPredicate, 0, 249, 19, // Skip to: 8540 -/* 3427 */ MCD_OPC_Decode, 168, 10, 85, // Opcode: LEXBRA -/* 3431 */ MCD_OPC_FilterValue, 71, 18, 0, // Skip to: 3453 -/* 3435 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3445 -/* 3441 */ MCD_OPC_Decode, 247, 8, 86, // Opcode: FIXBR -/* 3445 */ MCD_OPC_CheckPredicate, 0, 227, 19, // Skip to: 8540 -/* 3449 */ MCD_OPC_Decode, 248, 8, 85, // Opcode: FIXBRA -/* 3453 */ MCD_OPC_FilterValue, 72, 10, 0, // Skip to: 3467 -/* 3457 */ MCD_OPC_CheckField, 8, 8, 0, 213, 19, // Skip to: 8540 -/* 3463 */ MCD_OPC_Decode, 234, 9, 79, // Opcode: KXBR -/* 3467 */ MCD_OPC_FilterValue, 73, 10, 0, // Skip to: 3481 -/* 3471 */ MCD_OPC_CheckField, 8, 8, 0, 199, 19, // Skip to: 8540 -/* 3477 */ MCD_OPC_Decode, 164, 8, 79, // Opcode: CXBR -/* 3481 */ MCD_OPC_FilterValue, 74, 10, 0, // Skip to: 3495 -/* 3485 */ MCD_OPC_CheckField, 8, 8, 0, 185, 19, // Skip to: 8540 -/* 3491 */ MCD_OPC_Decode, 160, 3, 13, // Opcode: AXBR -/* 3495 */ MCD_OPC_FilterValue, 75, 10, 0, // Skip to: 3509 -/* 3499 */ MCD_OPC_CheckField, 8, 8, 0, 171, 19, // Skip to: 8540 -/* 3505 */ MCD_OPC_Decode, 150, 16, 13, // Opcode: SXBR -/* 3509 */ MCD_OPC_FilterValue, 76, 10, 0, // Skip to: 3523 -/* 3513 */ MCD_OPC_CheckField, 8, 8, 0, 157, 19, // Skip to: 8540 -/* 3519 */ MCD_OPC_Decode, 212, 13, 13, // Opcode: MXBR -/* 3523 */ MCD_OPC_FilterValue, 77, 10, 0, // Skip to: 3537 -/* 3527 */ MCD_OPC_CheckField, 8, 8, 0, 143, 19, // Skip to: 8540 -/* 3533 */ MCD_OPC_Decode, 211, 8, 13, // Opcode: DXBR -/* 3537 */ MCD_OPC_FilterValue, 80, 10, 0, // Skip to: 3551 -/* 3541 */ MCD_OPC_CheckField, 8, 4, 0, 129, 19, // Skip to: 8540 -/* 3547 */ MCD_OPC_Decode, 160, 16, 87, // Opcode: TBEDR -/* 3551 */ MCD_OPC_FilterValue, 81, 10, 0, // Skip to: 3565 -/* 3555 */ MCD_OPC_CheckField, 8, 4, 0, 115, 19, // Skip to: 8540 -/* 3561 */ MCD_OPC_Decode, 159, 16, 88, // Opcode: TBDR -/* 3565 */ MCD_OPC_FilterValue, 83, 4, 0, // Skip to: 3573 -/* 3569 */ MCD_OPC_Decode, 200, 8, 89, // Opcode: DIEBR -/* 3573 */ MCD_OPC_FilterValue, 87, 18, 0, // Skip to: 3595 -/* 3577 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3587 -/* 3583 */ MCD_OPC_Decode, 244, 8, 90, // Opcode: FIEBR -/* 3587 */ MCD_OPC_CheckPredicate, 0, 85, 19, // Skip to: 8540 -/* 3591 */ MCD_OPC_Decode, 245, 8, 91, // Opcode: FIEBRA -/* 3595 */ MCD_OPC_FilterValue, 88, 10, 0, // Skip to: 3609 -/* 3599 */ MCD_OPC_CheckField, 8, 8, 0, 71, 19, // Skip to: 8540 -/* 3605 */ MCD_OPC_Decode, 173, 16, 75, // Opcode: THDER -/* 3609 */ MCD_OPC_FilterValue, 89, 10, 0, // Skip to: 3623 -/* 3613 */ MCD_OPC_CheckField, 8, 8, 0, 57, 19, // Skip to: 8540 -/* 3619 */ MCD_OPC_Decode, 174, 16, 11, // Opcode: THDR -/* 3623 */ MCD_OPC_FilterValue, 91, 4, 0, // Skip to: 3631 -/* 3627 */ MCD_OPC_Decode, 199, 8, 92, // Opcode: DIDBR -/* 3631 */ MCD_OPC_FilterValue, 95, 18, 0, // Skip to: 3653 -/* 3635 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3645 -/* 3641 */ MCD_OPC_Decode, 240, 8, 88, // Opcode: FIDBR -/* 3645 */ MCD_OPC_CheckPredicate, 0, 27, 19, // Skip to: 8540 -/* 3649 */ MCD_OPC_Decode, 241, 8, 93, // Opcode: FIDBRA -/* 3653 */ MCD_OPC_FilterValue, 96, 10, 0, // Skip to: 3667 -/* 3657 */ MCD_OPC_CheckField, 8, 8, 0, 13, 19, // Skip to: 8540 -/* 3663 */ MCD_OPC_Decode, 201, 12, 79, // Opcode: LPXR -/* 3667 */ MCD_OPC_FilterValue, 97, 10, 0, // Skip to: 3681 -/* 3671 */ MCD_OPC_CheckField, 8, 8, 0, 255, 18, // Skip to: 8540 -/* 3677 */ MCD_OPC_Decode, 240, 10, 79, // Opcode: LNXR -/* 3681 */ MCD_OPC_FilterValue, 98, 10, 0, // Skip to: 3695 -/* 3685 */ MCD_OPC_CheckField, 8, 8, 0, 241, 18, // Skip to: 8540 -/* 3691 */ MCD_OPC_Decode, 230, 12, 79, // Opcode: LTXR -/* 3695 */ MCD_OPC_FilterValue, 99, 10, 0, // Skip to: 3709 -/* 3699 */ MCD_OPC_CheckField, 8, 8, 0, 227, 18, // Skip to: 8540 -/* 3705 */ MCD_OPC_Decode, 145, 10, 79, // Opcode: LCXR -/* 3709 */ MCD_OPC_FilterValue, 101, 10, 0, // Skip to: 3723 -/* 3713 */ MCD_OPC_CheckField, 8, 8, 0, 213, 18, // Skip to: 8540 -/* 3719 */ MCD_OPC_Decode, 243, 12, 79, // Opcode: LXR -/* 3723 */ MCD_OPC_FilterValue, 102, 10, 0, // Skip to: 3737 -/* 3727 */ MCD_OPC_CheckField, 8, 8, 0, 199, 18, // Skip to: 8540 -/* 3733 */ MCD_OPC_Decode, 169, 10, 94, // Opcode: LEXR -/* 3737 */ MCD_OPC_FilterValue, 103, 10, 0, // Skip to: 3751 -/* 3741 */ MCD_OPC_CheckField, 8, 8, 0, 185, 18, // Skip to: 8540 -/* 3747 */ MCD_OPC_Decode, 249, 8, 79, // Opcode: FIXR -/* 3751 */ MCD_OPC_FilterValue, 105, 10, 0, // Skip to: 3765 -/* 3755 */ MCD_OPC_CheckField, 8, 8, 0, 171, 18, // Skip to: 8540 -/* 3761 */ MCD_OPC_Decode, 179, 8, 79, // Opcode: CXR -/* 3765 */ MCD_OPC_FilterValue, 112, 10, 0, // Skip to: 3779 -/* 3769 */ MCD_OPC_CheckField, 8, 8, 0, 157, 18, // Skip to: 8540 -/* 3775 */ MCD_OPC_Decode, 186, 12, 11, // Opcode: LPDFR -/* 3779 */ MCD_OPC_FilterValue, 113, 10, 0, // Skip to: 3793 -/* 3783 */ MCD_OPC_CheckField, 8, 8, 0, 143, 18, // Skip to: 8540 -/* 3789 */ MCD_OPC_Decode, 231, 10, 11, // Opcode: LNDFR -/* 3793 */ MCD_OPC_FilterValue, 114, 10, 0, // Skip to: 3807 -/* 3797 */ MCD_OPC_CheckField, 8, 4, 0, 129, 18, // Skip to: 8540 -/* 3803 */ MCD_OPC_Decode, 208, 7, 95, // Opcode: CPSDRdd -/* 3807 */ MCD_OPC_FilterValue, 115, 10, 0, // Skip to: 3821 -/* 3811 */ MCD_OPC_CheckField, 8, 8, 0, 115, 18, // Skip to: 8540 -/* 3817 */ MCD_OPC_Decode, 134, 10, 11, // Opcode: LCDFR -/* 3821 */ MCD_OPC_FilterValue, 116, 16, 0, // Skip to: 3841 -/* 3825 */ MCD_OPC_CheckField, 8, 8, 0, 101, 18, // Skip to: 8540 -/* 3831 */ MCD_OPC_CheckField, 0, 4, 0, 95, 18, // Skip to: 8540 -/* 3837 */ MCD_OPC_Decode, 246, 12, 96, // Opcode: LZER -/* 3841 */ MCD_OPC_FilterValue, 117, 16, 0, // Skip to: 3861 -/* 3845 */ MCD_OPC_CheckField, 8, 8, 0, 81, 18, // Skip to: 8540 -/* 3851 */ MCD_OPC_CheckField, 0, 4, 0, 75, 18, // Skip to: 8540 -/* 3857 */ MCD_OPC_Decode, 245, 12, 97, // Opcode: LZDR -/* 3861 */ MCD_OPC_FilterValue, 118, 16, 0, // Skip to: 3881 -/* 3865 */ MCD_OPC_CheckField, 8, 8, 0, 61, 18, // Skip to: 8540 -/* 3871 */ MCD_OPC_CheckField, 0, 4, 0, 55, 18, // Skip to: 8540 -/* 3877 */ MCD_OPC_Decode, 249, 12, 98, // Opcode: LZXR -/* 3881 */ MCD_OPC_FilterValue, 119, 10, 0, // Skip to: 3895 -/* 3885 */ MCD_OPC_CheckField, 8, 8, 0, 41, 18, // Skip to: 8540 -/* 3891 */ MCD_OPC_Decode, 246, 8, 16, // Opcode: FIER -/* 3895 */ MCD_OPC_FilterValue, 127, 10, 0, // Skip to: 3909 -/* 3899 */ MCD_OPC_CheckField, 8, 8, 0, 27, 18, // Skip to: 8540 -/* 3905 */ MCD_OPC_Decode, 242, 8, 11, // Opcode: FIDR -/* 3909 */ MCD_OPC_FilterValue, 132, 1, 16, 0, // Skip to: 3930 -/* 3914 */ MCD_OPC_CheckField, 8, 8, 0, 12, 18, // Skip to: 8540 -/* 3920 */ MCD_OPC_CheckField, 0, 4, 0, 6, 18, // Skip to: 8540 -/* 3926 */ MCD_OPC_Decode, 201, 14, 1, // Opcode: SFPC -/* 3930 */ MCD_OPC_FilterValue, 133, 1, 16, 0, // Skip to: 3951 -/* 3935 */ MCD_OPC_CheckField, 8, 8, 0, 247, 17, // Skip to: 8540 -/* 3941 */ MCD_OPC_CheckField, 0, 4, 0, 241, 17, // Skip to: 8540 -/* 3947 */ MCD_OPC_Decode, 200, 14, 1, // Opcode: SFASR -/* 3951 */ MCD_OPC_FilterValue, 140, 1, 16, 0, // Skip to: 3972 -/* 3956 */ MCD_OPC_CheckField, 8, 8, 0, 226, 17, // Skip to: 8540 -/* 3962 */ MCD_OPC_CheckField, 0, 4, 0, 220, 17, // Skip to: 8540 -/* 3968 */ MCD_OPC_Decode, 224, 8, 1, // Opcode: EFPC -/* 3972 */ MCD_OPC_FilterValue, 144, 1, 8, 0, // Skip to: 3985 -/* 3977 */ MCD_OPC_CheckPredicate, 0, 207, 17, // Skip to: 8540 -/* 3981 */ MCD_OPC_Decode, 174, 4, 99, // Opcode: CELFBR -/* 3985 */ MCD_OPC_FilterValue, 145, 1, 8, 0, // Skip to: 3998 -/* 3990 */ MCD_OPC_CheckPredicate, 0, 194, 17, // Skip to: 8540 -/* 3994 */ MCD_OPC_Decode, 151, 4, 100, // Opcode: CDLFBR -/* 3998 */ MCD_OPC_FilterValue, 146, 1, 8, 0, // Skip to: 4011 -/* 4003 */ MCD_OPC_CheckPredicate, 0, 181, 17, // Skip to: 8540 -/* 4007 */ MCD_OPC_Decode, 174, 8, 101, // Opcode: CXLFBR -/* 4011 */ MCD_OPC_FilterValue, 148, 1, 18, 0, // Skip to: 4034 -/* 4016 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4026 -/* 4022 */ MCD_OPC_Decode, 168, 4, 102, // Opcode: CEFBR -/* 4026 */ MCD_OPC_CheckPredicate, 0, 158, 17, // Skip to: 8540 -/* 4030 */ MCD_OPC_Decode, 169, 4, 99, // Opcode: CEFBRA -/* 4034 */ MCD_OPC_FilterValue, 149, 1, 18, 0, // Skip to: 4057 -/* 4039 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4049 -/* 4045 */ MCD_OPC_Decode, 142, 4, 103, // Opcode: CDFBR -/* 4049 */ MCD_OPC_CheckPredicate, 0, 135, 17, // Skip to: 8540 -/* 4053 */ MCD_OPC_Decode, 143, 4, 100, // Opcode: CDFBRA -/* 4057 */ MCD_OPC_FilterValue, 150, 1, 18, 0, // Skip to: 4080 -/* 4062 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4072 -/* 4068 */ MCD_OPC_Decode, 165, 8, 104, // Opcode: CXFBR -/* 4072 */ MCD_OPC_CheckPredicate, 0, 112, 17, // Skip to: 8540 -/* 4076 */ MCD_OPC_Decode, 166, 8, 101, // Opcode: CXFBRA -/* 4080 */ MCD_OPC_FilterValue, 152, 1, 18, 0, // Skip to: 4103 -/* 4085 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4095 -/* 4091 */ MCD_OPC_Decode, 183, 4, 105, // Opcode: CFEBR -/* 4095 */ MCD_OPC_CheckPredicate, 0, 89, 17, // Skip to: 8540 -/* 4099 */ MCD_OPC_Decode, 184, 4, 106, // Opcode: CFEBRA -/* 4103 */ MCD_OPC_FilterValue, 153, 1, 18, 0, // Skip to: 4126 -/* 4108 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4118 -/* 4114 */ MCD_OPC_Decode, 179, 4, 107, // Opcode: CFDBR -/* 4118 */ MCD_OPC_CheckPredicate, 0, 66, 17, // Skip to: 8540 -/* 4122 */ MCD_OPC_Decode, 180, 4, 108, // Opcode: CFDBRA -/* 4126 */ MCD_OPC_FilterValue, 154, 1, 18, 0, // Skip to: 4149 -/* 4131 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4141 -/* 4137 */ MCD_OPC_Decode, 187, 4, 109, // Opcode: CFXBR -/* 4141 */ MCD_OPC_CheckPredicate, 0, 43, 17, // Skip to: 8540 -/* 4145 */ MCD_OPC_Decode, 188, 4, 110, // Opcode: CFXBRA -/* 4149 */ MCD_OPC_FilterValue, 156, 1, 8, 0, // Skip to: 4162 -/* 4154 */ MCD_OPC_CheckPredicate, 0, 30, 17, // Skip to: 8540 -/* 4158 */ MCD_OPC_Decode, 231, 5, 106, // Opcode: CLFEBR -/* 4162 */ MCD_OPC_FilterValue, 157, 1, 8, 0, // Skip to: 4175 -/* 4167 */ MCD_OPC_CheckPredicate, 0, 17, 17, // Skip to: 8540 -/* 4171 */ MCD_OPC_Decode, 229, 5, 108, // Opcode: CLFDBR -/* 4175 */ MCD_OPC_FilterValue, 158, 1, 8, 0, // Skip to: 4188 -/* 4180 */ MCD_OPC_CheckPredicate, 0, 4, 17, // Skip to: 8540 -/* 4184 */ MCD_OPC_Decode, 248, 5, 110, // Opcode: CLFXBR -/* 4188 */ MCD_OPC_FilterValue, 160, 1, 8, 0, // Skip to: 4201 -/* 4193 */ MCD_OPC_CheckPredicate, 0, 247, 16, // Skip to: 8540 -/* 4197 */ MCD_OPC_Decode, 175, 4, 111, // Opcode: CELGBR -/* 4201 */ MCD_OPC_FilterValue, 161, 1, 8, 0, // Skip to: 4214 -/* 4206 */ MCD_OPC_CheckPredicate, 0, 234, 16, // Skip to: 8540 -/* 4210 */ MCD_OPC_Decode, 153, 4, 112, // Opcode: CDLGBR -/* 4214 */ MCD_OPC_FilterValue, 162, 1, 8, 0, // Skip to: 4227 -/* 4219 */ MCD_OPC_CheckPredicate, 0, 221, 16, // Skip to: 8540 -/* 4223 */ MCD_OPC_Decode, 176, 8, 113, // Opcode: CXLGBR -/* 4227 */ MCD_OPC_FilterValue, 164, 1, 18, 0, // Skip to: 4250 -/* 4232 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4242 -/* 4238 */ MCD_OPC_Decode, 171, 4, 114, // Opcode: CEGBR -/* 4242 */ MCD_OPC_CheckPredicate, 0, 198, 16, // Skip to: 8540 -/* 4246 */ MCD_OPC_Decode, 172, 4, 111, // Opcode: CEGBRA -/* 4250 */ MCD_OPC_FilterValue, 165, 1, 18, 0, // Skip to: 4273 -/* 4255 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4265 -/* 4261 */ MCD_OPC_Decode, 146, 4, 115, // Opcode: CDGBR -/* 4265 */ MCD_OPC_CheckPredicate, 0, 175, 16, // Skip to: 8540 -/* 4269 */ MCD_OPC_Decode, 147, 4, 112, // Opcode: CDGBRA -/* 4273 */ MCD_OPC_FilterValue, 166, 1, 18, 0, // Skip to: 4296 -/* 4278 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4288 -/* 4284 */ MCD_OPC_Decode, 169, 8, 116, // Opcode: CXGBR -/* 4288 */ MCD_OPC_CheckPredicate, 0, 152, 16, // Skip to: 8540 -/* 4292 */ MCD_OPC_Decode, 170, 8, 113, // Opcode: CXGBRA -/* 4296 */ MCD_OPC_FilterValue, 168, 1, 18, 0, // Skip to: 4319 -/* 4301 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4311 -/* 4307 */ MCD_OPC_Decode, 197, 4, 117, // Opcode: CGEBR -/* 4311 */ MCD_OPC_CheckPredicate, 0, 129, 16, // Skip to: 8540 -/* 4315 */ MCD_OPC_Decode, 198, 4, 118, // Opcode: CGEBRA -/* 4319 */ MCD_OPC_FilterValue, 169, 1, 18, 0, // Skip to: 4342 -/* 4324 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4334 -/* 4330 */ MCD_OPC_Decode, 192, 4, 119, // Opcode: CGDBR -/* 4334 */ MCD_OPC_CheckPredicate, 0, 106, 16, // Skip to: 8540 -/* 4338 */ MCD_OPC_Decode, 193, 4, 120, // Opcode: CGDBRA -/* 4342 */ MCD_OPC_FilterValue, 170, 1, 18, 0, // Skip to: 4365 -/* 4347 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4357 -/* 4353 */ MCD_OPC_Decode, 166, 5, 121, // Opcode: CGXBR -/* 4357 */ MCD_OPC_CheckPredicate, 0, 83, 16, // Skip to: 8540 -/* 4361 */ MCD_OPC_Decode, 167, 5, 122, // Opcode: CGXBRA -/* 4365 */ MCD_OPC_FilterValue, 172, 1, 8, 0, // Skip to: 4378 -/* 4370 */ MCD_OPC_CheckPredicate, 0, 70, 16, // Skip to: 8540 -/* 4374 */ MCD_OPC_Decode, 253, 5, 118, // Opcode: CLGEBR -/* 4378 */ MCD_OPC_FilterValue, 173, 1, 8, 0, // Skip to: 4391 -/* 4383 */ MCD_OPC_CheckPredicate, 0, 57, 16, // Skip to: 8540 -/* 4387 */ MCD_OPC_Decode, 251, 5, 120, // Opcode: CLGDBR -/* 4391 */ MCD_OPC_FilterValue, 174, 1, 8, 0, // Skip to: 4404 -/* 4396 */ MCD_OPC_CheckPredicate, 0, 44, 16, // Skip to: 8540 -/* 4400 */ MCD_OPC_Decode, 232, 6, 122, // Opcode: CLGXBR -/* 4404 */ MCD_OPC_FilterValue, 180, 1, 10, 0, // Skip to: 4419 -/* 4409 */ MCD_OPC_CheckField, 8, 8, 0, 29, 16, // Skip to: 8540 -/* 4415 */ MCD_OPC_Decode, 170, 4, 102, // Opcode: CEFR -/* 4419 */ MCD_OPC_FilterValue, 181, 1, 10, 0, // Skip to: 4434 -/* 4424 */ MCD_OPC_CheckField, 8, 8, 0, 14, 16, // Skip to: 8540 -/* 4430 */ MCD_OPC_Decode, 144, 4, 103, // Opcode: CDFR -/* 4434 */ MCD_OPC_FilterValue, 182, 1, 10, 0, // Skip to: 4449 -/* 4439 */ MCD_OPC_CheckField, 8, 8, 0, 255, 15, // Skip to: 8540 -/* 4445 */ MCD_OPC_Decode, 167, 8, 104, // Opcode: CXFR -/* 4449 */ MCD_OPC_FilterValue, 184, 1, 10, 0, // Skip to: 4464 -/* 4454 */ MCD_OPC_CheckField, 8, 4, 0, 240, 15, // Skip to: 8540 -/* 4460 */ MCD_OPC_Decode, 185, 4, 105, // Opcode: CFER -/* 4464 */ MCD_OPC_FilterValue, 185, 1, 10, 0, // Skip to: 4479 -/* 4469 */ MCD_OPC_CheckField, 8, 4, 0, 225, 15, // Skip to: 8540 -/* 4475 */ MCD_OPC_Decode, 181, 4, 107, // Opcode: CFDR -/* 4479 */ MCD_OPC_FilterValue, 186, 1, 10, 0, // Skip to: 4494 -/* 4484 */ MCD_OPC_CheckField, 8, 4, 0, 210, 15, // Skip to: 8540 -/* 4490 */ MCD_OPC_Decode, 189, 4, 109, // Opcode: CFXR -/* 4494 */ MCD_OPC_FilterValue, 193, 1, 10, 0, // Skip to: 4509 -/* 4499 */ MCD_OPC_CheckField, 8, 8, 0, 195, 15, // Skip to: 8540 -/* 4505 */ MCD_OPC_Decode, 153, 10, 115, // Opcode: LDGR -/* 4509 */ MCD_OPC_FilterValue, 196, 1, 10, 0, // Skip to: 4524 -/* 4514 */ MCD_OPC_CheckField, 8, 8, 0, 180, 15, // Skip to: 8540 -/* 4520 */ MCD_OPC_Decode, 173, 4, 114, // Opcode: CEGR -/* 4524 */ MCD_OPC_FilterValue, 197, 1, 10, 0, // Skip to: 4539 -/* 4529 */ MCD_OPC_CheckField, 8, 8, 0, 165, 15, // Skip to: 8540 -/* 4535 */ MCD_OPC_Decode, 148, 4, 115, // Opcode: CDGR -/* 4539 */ MCD_OPC_FilterValue, 198, 1, 10, 0, // Skip to: 4554 -/* 4544 */ MCD_OPC_CheckField, 8, 8, 0, 150, 15, // Skip to: 8540 -/* 4550 */ MCD_OPC_Decode, 171, 8, 116, // Opcode: CXGR -/* 4554 */ MCD_OPC_FilterValue, 200, 1, 10, 0, // Skip to: 4569 -/* 4559 */ MCD_OPC_CheckField, 8, 4, 0, 135, 15, // Skip to: 8540 -/* 4565 */ MCD_OPC_Decode, 199, 4, 117, // Opcode: CGER -/* 4569 */ MCD_OPC_FilterValue, 201, 1, 10, 0, // Skip to: 4584 -/* 4574 */ MCD_OPC_CheckField, 8, 4, 0, 120, 15, // Skip to: 8540 -/* 4580 */ MCD_OPC_Decode, 194, 4, 119, // Opcode: CGDR -/* 4584 */ MCD_OPC_FilterValue, 202, 1, 10, 0, // Skip to: 4599 -/* 4589 */ MCD_OPC_CheckField, 8, 4, 0, 105, 15, // Skip to: 8540 -/* 4595 */ MCD_OPC_Decode, 168, 5, 121, // Opcode: CGXR -/* 4599 */ MCD_OPC_FilterValue, 205, 1, 10, 0, // Skip to: 4614 -/* 4604 */ MCD_OPC_CheckField, 8, 8, 0, 90, 15, // Skip to: 8540 -/* 4610 */ MCD_OPC_Decode, 179, 10, 123, // Opcode: LGDR -/* 4614 */ MCD_OPC_FilterValue, 208, 1, 18, 0, // Skip to: 4637 -/* 4619 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4629 -/* 4625 */ MCD_OPC_Decode, 146, 13, 95, // Opcode: MDTR -/* 4629 */ MCD_OPC_CheckPredicate, 0, 67, 15, // Skip to: 8540 -/* 4633 */ MCD_OPC_Decode, 147, 13, 124, // Opcode: MDTRA -/* 4637 */ MCD_OPC_FilterValue, 209, 1, 18, 0, // Skip to: 4660 -/* 4642 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4652 -/* 4648 */ MCD_OPC_Decode, 192, 8, 95, // Opcode: DDTR -/* 4652 */ MCD_OPC_CheckPredicate, 0, 44, 15, // Skip to: 8540 -/* 4656 */ MCD_OPC_Decode, 193, 8, 124, // Opcode: DDTRA -/* 4660 */ MCD_OPC_FilterValue, 210, 1, 18, 0, // Skip to: 4683 -/* 4665 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4675 -/* 4671 */ MCD_OPC_Decode, 233, 2, 95, // Opcode: ADTR -/* 4675 */ MCD_OPC_CheckPredicate, 0, 21, 15, // Skip to: 8540 -/* 4679 */ MCD_OPC_Decode, 234, 2, 124, // Opcode: ADTRA -/* 4683 */ MCD_OPC_FilterValue, 211, 1, 18, 0, // Skip to: 4706 -/* 4688 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4698 -/* 4694 */ MCD_OPC_Decode, 194, 14, 95, // Opcode: SDTR -/* 4698 */ MCD_OPC_CheckPredicate, 0, 254, 14, // Skip to: 8540 -/* 4702 */ MCD_OPC_Decode, 195, 14, 124, // Opcode: SDTRA -/* 4706 */ MCD_OPC_FilterValue, 212, 1, 10, 0, // Skip to: 4721 -/* 4711 */ MCD_OPC_CheckField, 12, 4, 0, 239, 14, // Skip to: 8540 -/* 4717 */ MCD_OPC_Decode, 152, 10, 125, // Opcode: LDETR -/* 4721 */ MCD_OPC_FilterValue, 213, 1, 4, 0, // Skip to: 4730 -/* 4726 */ MCD_OPC_Decode, 165, 10, 84, // Opcode: LEDTR -/* 4730 */ MCD_OPC_FilterValue, 214, 1, 10, 0, // Skip to: 4745 -/* 4735 */ MCD_OPC_CheckField, 8, 8, 0, 215, 14, // Skip to: 8540 -/* 4741 */ MCD_OPC_Decode, 219, 12, 11, // Opcode: LTDTR -/* 4745 */ MCD_OPC_FilterValue, 215, 1, 4, 0, // Skip to: 4754 -/* 4750 */ MCD_OPC_Decode, 243, 8, 93, // Opcode: FIDTR -/* 4754 */ MCD_OPC_FilterValue, 216, 1, 18, 0, // Skip to: 4777 -/* 4759 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4769 -/* 4765 */ MCD_OPC_Decode, 218, 13, 126, // Opcode: MXTR -/* 4769 */ MCD_OPC_CheckPredicate, 0, 183, 14, // Skip to: 8540 -/* 4773 */ MCD_OPC_Decode, 219, 13, 127, // Opcode: MXTRA -/* 4777 */ MCD_OPC_FilterValue, 217, 1, 18, 0, // Skip to: 4800 -/* 4782 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4792 -/* 4788 */ MCD_OPC_Decode, 213, 8, 126, // Opcode: DXTR -/* 4792 */ MCD_OPC_CheckPredicate, 0, 160, 14, // Skip to: 8540 -/* 4796 */ MCD_OPC_Decode, 214, 8, 127, // Opcode: DXTRA -/* 4800 */ MCD_OPC_FilterValue, 218, 1, 18, 0, // Skip to: 4823 -/* 4805 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4815 -/* 4811 */ MCD_OPC_Decode, 162, 3, 126, // Opcode: AXTR -/* 4815 */ MCD_OPC_CheckPredicate, 0, 137, 14, // Skip to: 8540 -/* 4819 */ MCD_OPC_Decode, 163, 3, 127, // Opcode: AXTRA -/* 4823 */ MCD_OPC_FilterValue, 219, 1, 18, 0, // Skip to: 4846 -/* 4828 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4838 -/* 4834 */ MCD_OPC_Decode, 152, 16, 126, // Opcode: SXTR -/* 4838 */ MCD_OPC_CheckPredicate, 0, 114, 14, // Skip to: 8540 -/* 4842 */ MCD_OPC_Decode, 153, 16, 127, // Opcode: SXTRA -/* 4846 */ MCD_OPC_FilterValue, 220, 1, 11, 0, // Skip to: 4862 -/* 4851 */ MCD_OPC_CheckField, 12, 4, 0, 99, 14, // Skip to: 8540 -/* 4857 */ MCD_OPC_Decode, 238, 12, 128, 1, // Opcode: LXDTR -/* 4862 */ MCD_OPC_FilterValue, 221, 1, 4, 0, // Skip to: 4871 -/* 4867 */ MCD_OPC_Decode, 159, 10, 85, // Opcode: LDXTR -/* 4871 */ MCD_OPC_FilterValue, 222, 1, 10, 0, // Skip to: 4886 -/* 4876 */ MCD_OPC_CheckField, 8, 8, 0, 74, 14, // Skip to: 8540 -/* 4882 */ MCD_OPC_Decode, 231, 12, 79, // Opcode: LTXTR -/* 4886 */ MCD_OPC_FilterValue, 223, 1, 4, 0, // Skip to: 4895 -/* 4891 */ MCD_OPC_Decode, 250, 8, 85, // Opcode: FIXTR -/* 4895 */ MCD_OPC_FilterValue, 224, 1, 10, 0, // Skip to: 4910 -/* 4900 */ MCD_OPC_CheckField, 8, 8, 0, 50, 14, // Skip to: 8540 -/* 4906 */ MCD_OPC_Decode, 222, 9, 11, // Opcode: KDTR -/* 4910 */ MCD_OPC_FilterValue, 225, 1, 18, 0, // Skip to: 4933 -/* 4915 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4925 -/* 4921 */ MCD_OPC_Decode, 195, 4, 119, // Opcode: CGDTR -/* 4925 */ MCD_OPC_CheckPredicate, 0, 27, 14, // Skip to: 8540 -/* 4929 */ MCD_OPC_Decode, 196, 4, 120, // Opcode: CGDTRA -/* 4933 */ MCD_OPC_FilterValue, 226, 1, 10, 0, // Skip to: 4948 -/* 4938 */ MCD_OPC_CheckField, 8, 8, 0, 12, 14, // Skip to: 8540 -/* 4944 */ MCD_OPC_Decode, 151, 8, 123, // Opcode: CUDTR -/* 4948 */ MCD_OPC_FilterValue, 227, 1, 11, 0, // Skip to: 4964 -/* 4953 */ MCD_OPC_CheckField, 12, 4, 0, 253, 13, // Skip to: 8540 -/* 4959 */ MCD_OPC_Decode, 134, 8, 129, 1, // Opcode: CSDTR -/* 4964 */ MCD_OPC_FilterValue, 228, 1, 10, 0, // Skip to: 4979 -/* 4969 */ MCD_OPC_CheckField, 8, 8, 0, 237, 13, // Skip to: 8540 -/* 4975 */ MCD_OPC_Decode, 161, 4, 11, // Opcode: CDTR -/* 4979 */ MCD_OPC_FilterValue, 229, 1, 10, 0, // Skip to: 4994 -/* 4984 */ MCD_OPC_CheckField, 8, 8, 0, 222, 13, // Skip to: 8540 -/* 4990 */ MCD_OPC_Decode, 222, 8, 11, // Opcode: EEDTR -/* 4994 */ MCD_OPC_FilterValue, 231, 1, 10, 0, // Skip to: 5009 -/* 4999 */ MCD_OPC_CheckField, 8, 8, 0, 207, 13, // Skip to: 8540 -/* 5005 */ MCD_OPC_Decode, 233, 8, 11, // Opcode: ESDTR -/* 5009 */ MCD_OPC_FilterValue, 232, 1, 10, 0, // Skip to: 5024 -/* 5014 */ MCD_OPC_CheckField, 8, 8, 0, 192, 13, // Skip to: 8540 -/* 5020 */ MCD_OPC_Decode, 235, 9, 79, // Opcode: KXTR -/* 5024 */ MCD_OPC_FilterValue, 233, 1, 18, 0, // Skip to: 5047 -/* 5029 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 5039 -/* 5035 */ MCD_OPC_Decode, 169, 5, 121, // Opcode: CGXTR -/* 5039 */ MCD_OPC_CheckPredicate, 0, 169, 13, // Skip to: 8540 -/* 5043 */ MCD_OPC_Decode, 170, 5, 122, // Opcode: CGXTRA -/* 5047 */ MCD_OPC_FilterValue, 234, 1, 11, 0, // Skip to: 5063 -/* 5052 */ MCD_OPC_CheckField, 8, 8, 0, 154, 13, // Skip to: 8540 -/* 5058 */ MCD_OPC_Decode, 157, 8, 130, 1, // Opcode: CUXTR -/* 5063 */ MCD_OPC_FilterValue, 235, 1, 11, 0, // Skip to: 5079 -/* 5068 */ MCD_OPC_CheckField, 12, 4, 0, 138, 13, // Skip to: 8540 -/* 5074 */ MCD_OPC_Decode, 139, 8, 131, 1, // Opcode: CSXTR -/* 5079 */ MCD_OPC_FilterValue, 236, 1, 10, 0, // Skip to: 5094 -/* 5084 */ MCD_OPC_CheckField, 8, 8, 0, 122, 13, // Skip to: 8540 -/* 5090 */ MCD_OPC_Decode, 181, 8, 79, // Opcode: CXTR -/* 5094 */ MCD_OPC_FilterValue, 237, 1, 10, 0, // Skip to: 5109 -/* 5099 */ MCD_OPC_CheckField, 8, 8, 0, 107, 13, // Skip to: 8540 -/* 5105 */ MCD_OPC_Decode, 223, 8, 79, // Opcode: EEXTR -/* 5109 */ MCD_OPC_FilterValue, 239, 1, 10, 0, // Skip to: 5124 -/* 5114 */ MCD_OPC_CheckField, 8, 8, 0, 92, 13, // Skip to: 8540 -/* 5120 */ MCD_OPC_Decode, 236, 8, 79, // Opcode: ESXTR -/* 5124 */ MCD_OPC_FilterValue, 241, 1, 18, 0, // Skip to: 5147 -/* 5129 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 5139 -/* 5135 */ MCD_OPC_Decode, 149, 4, 115, // Opcode: CDGTR -/* 5139 */ MCD_OPC_CheckPredicate, 0, 69, 13, // Skip to: 8540 -/* 5143 */ MCD_OPC_Decode, 150, 4, 112, // Opcode: CDGTRA -/* 5147 */ MCD_OPC_FilterValue, 242, 1, 10, 0, // Skip to: 5162 -/* 5152 */ MCD_OPC_CheckField, 8, 8, 0, 54, 13, // Skip to: 8540 -/* 5158 */ MCD_OPC_Decode, 162, 4, 115, // Opcode: CDUTR -/* 5162 */ MCD_OPC_FilterValue, 243, 1, 10, 0, // Skip to: 5177 -/* 5167 */ MCD_OPC_CheckField, 8, 8, 0, 39, 13, // Skip to: 8540 -/* 5173 */ MCD_OPC_Decode, 159, 4, 115, // Opcode: CDSTR -/* 5177 */ MCD_OPC_FilterValue, 244, 1, 10, 0, // Skip to: 5192 -/* 5182 */ MCD_OPC_CheckField, 8, 8, 0, 24, 13, // Skip to: 8540 -/* 5188 */ MCD_OPC_Decode, 167, 4, 11, // Opcode: CEDTR -/* 5192 */ MCD_OPC_FilterValue, 245, 1, 4, 0, // Skip to: 5201 -/* 5197 */ MCD_OPC_Decode, 156, 14, 92, // Opcode: QADTR -/* 5201 */ MCD_OPC_FilterValue, 246, 1, 10, 0, // Skip to: 5216 -/* 5206 */ MCD_OPC_CheckField, 8, 4, 0, 0, 13, // Skip to: 8540 -/* 5212 */ MCD_OPC_Decode, 137, 9, 95, // Opcode: IEDTR -/* 5216 */ MCD_OPC_FilterValue, 247, 1, 4, 0, // Skip to: 5225 -/* 5221 */ MCD_OPC_Decode, 173, 14, 92, // Opcode: RRDTR -/* 5225 */ MCD_OPC_FilterValue, 249, 1, 18, 0, // Skip to: 5248 -/* 5230 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 5240 -/* 5236 */ MCD_OPC_Decode, 172, 8, 116, // Opcode: CXGTR -/* 5240 */ MCD_OPC_CheckPredicate, 0, 224, 12, // Skip to: 8540 -/* 5244 */ MCD_OPC_Decode, 173, 8, 113, // Opcode: CXGTRA -/* 5248 */ MCD_OPC_FilterValue, 250, 1, 11, 0, // Skip to: 5264 -/* 5253 */ MCD_OPC_CheckField, 8, 8, 0, 209, 12, // Skip to: 8540 -/* 5259 */ MCD_OPC_Decode, 182, 8, 132, 1, // Opcode: CXUTR -/* 5264 */ MCD_OPC_FilterValue, 251, 1, 11, 0, // Skip to: 5280 -/* 5269 */ MCD_OPC_CheckField, 8, 8, 0, 193, 12, // Skip to: 8540 -/* 5275 */ MCD_OPC_Decode, 180, 8, 132, 1, // Opcode: CXSTR -/* 5280 */ MCD_OPC_FilterValue, 252, 1, 10, 0, // Skip to: 5295 -/* 5285 */ MCD_OPC_CheckField, 8, 8, 0, 177, 12, // Skip to: 8540 -/* 5291 */ MCD_OPC_Decode, 177, 4, 79, // Opcode: CEXTR -/* 5295 */ MCD_OPC_FilterValue, 253, 1, 5, 0, // Skip to: 5305 -/* 5300 */ MCD_OPC_Decode, 157, 14, 133, 1, // Opcode: QAXTR -/* 5305 */ MCD_OPC_FilterValue, 254, 1, 10, 0, // Skip to: 5320 -/* 5310 */ MCD_OPC_CheckField, 8, 4, 0, 152, 12, // Skip to: 8540 -/* 5316 */ MCD_OPC_Decode, 138, 9, 126, // Opcode: IEXTR -/* 5320 */ MCD_OPC_FilterValue, 255, 1, 143, 12, // Skip to: 8540 -/* 5325 */ MCD_OPC_Decode, 174, 14, 133, 1, // Opcode: RRXTR -/* 5330 */ MCD_OPC_FilterValue, 182, 1, 5, 0, // Skip to: 5340 -/* 5335 */ MCD_OPC_Decode, 170, 15, 134, 1, // Opcode: STCTL -/* 5340 */ MCD_OPC_FilterValue, 183, 1, 5, 0, // Skip to: 5350 -/* 5345 */ MCD_OPC_Decode, 142, 10, 134, 1, // Opcode: LCTL -/* 5350 */ MCD_OPC_FilterValue, 185, 1, 64, 12, // Skip to: 8491 -/* 5355 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 5358 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5372 -/* 5362 */ MCD_OPC_CheckField, 8, 8, 0, 100, 12, // Skip to: 8540 -/* 5368 */ MCD_OPC_Decode, 193, 12, 61, // Opcode: LPGR -/* 5372 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 5386 -/* 5376 */ MCD_OPC_CheckField, 8, 8, 0, 86, 12, // Skip to: 8540 -/* 5382 */ MCD_OPC_Decode, 237, 10, 61, // Opcode: LNGR -/* 5386 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 5400 -/* 5390 */ MCD_OPC_CheckField, 8, 8, 0, 72, 12, // Skip to: 8540 -/* 5396 */ MCD_OPC_Decode, 226, 12, 61, // Opcode: LTGR -/* 5400 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 5414 -/* 5404 */ MCD_OPC_CheckField, 8, 8, 0, 58, 12, // Skip to: 8540 -/* 5410 */ MCD_OPC_Decode, 140, 10, 61, // Opcode: LCGR -/* 5414 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 5428 -/* 5418 */ MCD_OPC_CheckField, 8, 8, 0, 44, 12, // Skip to: 8540 -/* 5424 */ MCD_OPC_Decode, 189, 10, 61, // Opcode: LGR -/* 5428 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 5442 -/* 5432 */ MCD_OPC_CheckField, 8, 8, 0, 30, 12, // Skip to: 8540 -/* 5438 */ MCD_OPC_Decode, 233, 12, 61, // Opcode: LURAG -/* 5442 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 5456 -/* 5446 */ MCD_OPC_CheckField, 8, 8, 0, 16, 12, // Skip to: 8540 -/* 5452 */ MCD_OPC_Decode, 178, 10, 61, // Opcode: LGBR -/* 5456 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 5470 -/* 5460 */ MCD_OPC_CheckField, 8, 8, 0, 2, 12, // Skip to: 8540 -/* 5466 */ MCD_OPC_Decode, 187, 10, 61, // Opcode: LGHR -/* 5470 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 5485 -/* 5474 */ MCD_OPC_CheckField, 8, 8, 0, 244, 11, // Skip to: 8540 -/* 5480 */ MCD_OPC_Decode, 247, 2, 135, 1, // Opcode: AGR -/* 5485 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 5500 -/* 5489 */ MCD_OPC_CheckField, 8, 8, 0, 229, 11, // Skip to: 8540 -/* 5495 */ MCD_OPC_Decode, 206, 14, 135, 1, // Opcode: SGR -/* 5500 */ MCD_OPC_FilterValue, 10, 11, 0, // Skip to: 5515 -/* 5504 */ MCD_OPC_CheckField, 8, 8, 0, 214, 11, // Skip to: 8540 -/* 5510 */ MCD_OPC_Decode, 140, 3, 135, 1, // Opcode: ALGR -/* 5515 */ MCD_OPC_FilterValue, 11, 11, 0, // Skip to: 5530 -/* 5519 */ MCD_OPC_CheckField, 8, 8, 0, 199, 11, // Skip to: 8540 -/* 5525 */ MCD_OPC_Decode, 231, 14, 135, 1, // Opcode: SLGR -/* 5530 */ MCD_OPC_FilterValue, 12, 11, 0, // Skip to: 5545 -/* 5534 */ MCD_OPC_CheckField, 8, 8, 0, 184, 11, // Skip to: 8540 -/* 5540 */ MCD_OPC_Decode, 185, 13, 135, 1, // Opcode: MSGR -/* 5545 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 5559 -/* 5549 */ MCD_OPC_CheckField, 8, 8, 0, 169, 11, // Skip to: 8540 -/* 5555 */ MCD_OPC_Decode, 210, 8, 68, // Opcode: DSGR -/* 5559 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 5573 -/* 5563 */ MCD_OPC_CheckField, 8, 8, 0, 155, 11, // Skip to: 8540 -/* 5569 */ MCD_OPC_Decode, 230, 8, 61, // Opcode: EREGG -/* 5573 */ MCD_OPC_FilterValue, 15, 10, 0, // Skip to: 5587 -/* 5577 */ MCD_OPC_CheckField, 8, 8, 0, 141, 11, // Skip to: 8540 -/* 5583 */ MCD_OPC_Decode, 211, 12, 61, // Opcode: LRVGR -/* 5587 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 5601 -/* 5591 */ MCD_OPC_CheckField, 8, 8, 0, 127, 11, // Skip to: 8540 -/* 5597 */ MCD_OPC_Decode, 192, 12, 56, // Opcode: LPGFR -/* 5601 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 5615 -/* 5605 */ MCD_OPC_CheckField, 8, 8, 0, 113, 11, // Skip to: 8540 -/* 5611 */ MCD_OPC_Decode, 236, 10, 56, // Opcode: LNGFR -/* 5615 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 5629 -/* 5619 */ MCD_OPC_CheckField, 8, 8, 0, 99, 11, // Skip to: 8540 -/* 5625 */ MCD_OPC_Decode, 225, 12, 56, // Opcode: LTGFR -/* 5629 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 5643 -/* 5633 */ MCD_OPC_CheckField, 8, 8, 0, 85, 11, // Skip to: 8540 -/* 5639 */ MCD_OPC_Decode, 139, 10, 56, // Opcode: LCGFR -/* 5643 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 5657 -/* 5647 */ MCD_OPC_CheckField, 8, 8, 0, 71, 11, // Skip to: 8540 -/* 5653 */ MCD_OPC_Decode, 182, 10, 56, // Opcode: LGFR -/* 5657 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 5671 -/* 5661 */ MCD_OPC_CheckField, 8, 8, 0, 57, 11, // Skip to: 8540 -/* 5667 */ MCD_OPC_Decode, 205, 10, 56, // Opcode: LLGFR -/* 5671 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 5685 -/* 5675 */ MCD_OPC_CheckField, 8, 8, 0, 43, 11, // Skip to: 8540 -/* 5681 */ MCD_OPC_Decode, 213, 10, 61, // Opcode: LLGTR -/* 5685 */ MCD_OPC_FilterValue, 24, 11, 0, // Skip to: 5700 -/* 5689 */ MCD_OPC_CheckField, 8, 8, 0, 29, 11, // Skip to: 8540 -/* 5695 */ MCD_OPC_Decode, 243, 2, 136, 1, // Opcode: AGFR -/* 5700 */ MCD_OPC_FilterValue, 25, 11, 0, // Skip to: 5715 -/* 5704 */ MCD_OPC_CheckField, 8, 8, 0, 14, 11, // Skip to: 8540 -/* 5710 */ MCD_OPC_Decode, 204, 14, 136, 1, // Opcode: SGFR -/* 5715 */ MCD_OPC_FilterValue, 26, 11, 0, // Skip to: 5730 -/* 5719 */ MCD_OPC_CheckField, 8, 8, 0, 255, 10, // Skip to: 8540 -/* 5725 */ MCD_OPC_Decode, 138, 3, 136, 1, // Opcode: ALGFR -/* 5730 */ MCD_OPC_FilterValue, 27, 11, 0, // Skip to: 5745 -/* 5734 */ MCD_OPC_CheckField, 8, 8, 0, 240, 10, // Skip to: 8540 -/* 5740 */ MCD_OPC_Decode, 230, 14, 136, 1, // Opcode: SLGFR -/* 5745 */ MCD_OPC_FilterValue, 28, 11, 0, // Skip to: 5760 -/* 5749 */ MCD_OPC_CheckField, 8, 8, 0, 225, 10, // Skip to: 8540 -/* 5755 */ MCD_OPC_Decode, 184, 13, 136, 1, // Opcode: MSGFR -/* 5760 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 5774 -/* 5764 */ MCD_OPC_CheckField, 8, 8, 0, 210, 10, // Skip to: 8540 -/* 5770 */ MCD_OPC_Decode, 209, 8, 10, // Opcode: DSGFR -/* 5774 */ MCD_OPC_FilterValue, 30, 11, 0, // Skip to: 5789 -/* 5778 */ MCD_OPC_CheckField, 8, 8, 0, 196, 10, // Skip to: 8540 -/* 5784 */ MCD_OPC_Decode, 229, 9, 137, 1, // Opcode: KMAC -/* 5789 */ MCD_OPC_FilterValue, 31, 10, 0, // Skip to: 5803 -/* 5793 */ MCD_OPC_CheckField, 8, 8, 0, 181, 10, // Skip to: 8540 -/* 5799 */ MCD_OPC_Decode, 213, 12, 8, // Opcode: LRVR -/* 5803 */ MCD_OPC_FilterValue, 32, 10, 0, // Skip to: 5817 -/* 5807 */ MCD_OPC_CheckField, 8, 8, 0, 167, 10, // Skip to: 8540 -/* 5813 */ MCD_OPC_Decode, 250, 4, 61, // Opcode: CGR -/* 5817 */ MCD_OPC_FilterValue, 33, 10, 0, // Skip to: 5831 -/* 5821 */ MCD_OPC_CheckField, 8, 8, 0, 153, 10, // Skip to: 8540 -/* 5827 */ MCD_OPC_Decode, 174, 6, 61, // Opcode: CLGR -/* 5831 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 5845 -/* 5835 */ MCD_OPC_CheckField, 8, 8, 0, 139, 10, // Skip to: 8540 -/* 5841 */ MCD_OPC_Decode, 143, 16, 61, // Opcode: STURG -/* 5845 */ MCD_OPC_FilterValue, 38, 10, 0, // Skip to: 5859 -/* 5849 */ MCD_OPC_CheckField, 8, 8, 0, 125, 10, // Skip to: 8540 -/* 5855 */ MCD_OPC_Decode, 130, 10, 8, // Opcode: LBR -/* 5859 */ MCD_OPC_FilterValue, 39, 10, 0, // Skip to: 5873 -/* 5863 */ MCD_OPC_CheckField, 8, 8, 0, 111, 10, // Skip to: 8540 -/* 5869 */ MCD_OPC_Decode, 195, 10, 8, // Opcode: LHR -/* 5873 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 5891 -/* 5877 */ MCD_OPC_CheckPredicate, 4, 99, 10, // Skip to: 8540 -/* 5881 */ MCD_OPC_CheckField, 0, 16, 0, 93, 10, // Skip to: 8540 -/* 5887 */ MCD_OPC_Decode, 136, 14, 0, // Opcode: PCKMO -/* 5891 */ MCD_OPC_FilterValue, 41, 15, 0, // Skip to: 5910 -/* 5895 */ MCD_OPC_CheckPredicate, 5, 81, 10, // Skip to: 8540 -/* 5899 */ MCD_OPC_CheckField, 8, 4, 0, 75, 10, // Skip to: 8540 -/* 5905 */ MCD_OPC_Decode, 228, 9, 138, 1, // Opcode: KMA -/* 5910 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 5928 -/* 5914 */ MCD_OPC_CheckPredicate, 6, 62, 10, // Skip to: 8540 -/* 5918 */ MCD_OPC_CheckField, 8, 8, 0, 56, 10, // Skip to: 8540 -/* 5924 */ MCD_OPC_Decode, 232, 9, 7, // Opcode: KMF -/* 5928 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 5946 -/* 5932 */ MCD_OPC_CheckPredicate, 6, 44, 10, // Skip to: 8540 -/* 5936 */ MCD_OPC_CheckField, 8, 8, 0, 38, 10, // Skip to: 8540 -/* 5942 */ MCD_OPC_Decode, 233, 9, 7, // Opcode: KMO -/* 5946 */ MCD_OPC_FilterValue, 44, 14, 0, // Skip to: 5964 -/* 5950 */ MCD_OPC_CheckPredicate, 6, 26, 10, // Skip to: 8540 -/* 5954 */ MCD_OPC_CheckField, 0, 16, 0, 20, 10, // Skip to: 8540 -/* 5960 */ MCD_OPC_Decode, 135, 14, 0, // Opcode: PCC -/* 5964 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 5983 -/* 5968 */ MCD_OPC_CheckPredicate, 6, 8, 10, // Skip to: 8540 -/* 5972 */ MCD_OPC_CheckField, 8, 4, 0, 2, 10, // Skip to: 8540 -/* 5978 */ MCD_OPC_Decode, 231, 9, 138, 1, // Opcode: KMCTR -/* 5983 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 5997 -/* 5987 */ MCD_OPC_CheckField, 8, 8, 0, 243, 9, // Skip to: 8540 -/* 5993 */ MCD_OPC_Decode, 227, 9, 7, // Opcode: KM -/* 5997 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 6011 -/* 6001 */ MCD_OPC_CheckField, 8, 8, 0, 229, 9, // Skip to: 8540 -/* 6007 */ MCD_OPC_Decode, 230, 9, 7, // Opcode: KMC -/* 6011 */ MCD_OPC_FilterValue, 48, 10, 0, // Skip to: 6025 -/* 6015 */ MCD_OPC_CheckField, 8, 8, 0, 215, 9, // Skip to: 8540 -/* 6021 */ MCD_OPC_Decode, 202, 4, 56, // Opcode: CGFR -/* 6025 */ MCD_OPC_FilterValue, 49, 10, 0, // Skip to: 6039 -/* 6029 */ MCD_OPC_CheckField, 8, 8, 0, 201, 9, // Skip to: 8540 -/* 6035 */ MCD_OPC_Decode, 128, 6, 56, // Opcode: CLGFR -/* 6039 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 6057 -/* 6043 */ MCD_OPC_CheckPredicate, 7, 189, 9, // Skip to: 8540 -/* 6047 */ MCD_OPC_CheckField, 8, 8, 0, 183, 9, // Skip to: 8540 -/* 6053 */ MCD_OPC_Decode, 148, 14, 7, // Opcode: PPNO -/* 6057 */ MCD_OPC_FilterValue, 62, 11, 0, // Skip to: 6072 -/* 6061 */ MCD_OPC_CheckField, 8, 8, 0, 169, 9, // Skip to: 8540 -/* 6067 */ MCD_OPC_Decode, 225, 9, 137, 1, // Opcode: KIMD -/* 6072 */ MCD_OPC_FilterValue, 63, 11, 0, // Skip to: 6087 -/* 6076 */ MCD_OPC_CheckField, 8, 8, 0, 154, 9, // Skip to: 8540 -/* 6082 */ MCD_OPC_Decode, 226, 9, 137, 1, // Opcode: KLMD -/* 6087 */ MCD_OPC_FilterValue, 65, 8, 0, // Skip to: 6099 -/* 6091 */ MCD_OPC_CheckPredicate, 0, 141, 9, // Skip to: 8540 -/* 6095 */ MCD_OPC_Decode, 182, 4, 108, // Opcode: CFDTR -/* 6099 */ MCD_OPC_FilterValue, 66, 8, 0, // Skip to: 6111 -/* 6103 */ MCD_OPC_CheckPredicate, 0, 129, 9, // Skip to: 8540 -/* 6107 */ MCD_OPC_Decode, 252, 5, 120, // Opcode: CLGDTR -/* 6111 */ MCD_OPC_FilterValue, 67, 8, 0, // Skip to: 6123 -/* 6115 */ MCD_OPC_CheckPredicate, 0, 117, 9, // Skip to: 8540 -/* 6119 */ MCD_OPC_Decode, 230, 5, 108, // Opcode: CLFDTR -/* 6123 */ MCD_OPC_FilterValue, 70, 11, 0, // Skip to: 6138 -/* 6127 */ MCD_OPC_CheckField, 8, 8, 0, 103, 9, // Skip to: 8540 -/* 6133 */ MCD_OPC_Decode, 198, 3, 135, 1, // Opcode: BCTGR -/* 6138 */ MCD_OPC_FilterValue, 73, 8, 0, // Skip to: 6150 -/* 6142 */ MCD_OPC_CheckPredicate, 0, 90, 9, // Skip to: 8540 -/* 6146 */ MCD_OPC_Decode, 190, 4, 110, // Opcode: CFXTR -/* 6150 */ MCD_OPC_FilterValue, 74, 8, 0, // Skip to: 6162 -/* 6154 */ MCD_OPC_CheckPredicate, 0, 78, 9, // Skip to: 8540 -/* 6158 */ MCD_OPC_Decode, 233, 6, 122, // Opcode: CLGXTR -/* 6162 */ MCD_OPC_FilterValue, 75, 8, 0, // Skip to: 6174 -/* 6166 */ MCD_OPC_CheckPredicate, 0, 66, 9, // Skip to: 8540 -/* 6170 */ MCD_OPC_Decode, 249, 5, 110, // Opcode: CLFXTR -/* 6174 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 6186 -/* 6178 */ MCD_OPC_CheckPredicate, 0, 54, 9, // Skip to: 8540 -/* 6182 */ MCD_OPC_Decode, 145, 4, 100, // Opcode: CDFTR -/* 6186 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 6198 -/* 6190 */ MCD_OPC_CheckPredicate, 0, 42, 9, // Skip to: 8540 -/* 6194 */ MCD_OPC_Decode, 154, 4, 112, // Opcode: CDLGTR -/* 6198 */ MCD_OPC_FilterValue, 83, 8, 0, // Skip to: 6210 -/* 6202 */ MCD_OPC_CheckPredicate, 0, 30, 9, // Skip to: 8540 -/* 6206 */ MCD_OPC_Decode, 152, 4, 100, // Opcode: CDLFTR -/* 6210 */ MCD_OPC_FilterValue, 89, 8, 0, // Skip to: 6222 -/* 6214 */ MCD_OPC_CheckPredicate, 0, 18, 9, // Skip to: 8540 -/* 6218 */ MCD_OPC_Decode, 168, 8, 101, // Opcode: CXFTR -/* 6222 */ MCD_OPC_FilterValue, 90, 8, 0, // Skip to: 6234 -/* 6226 */ MCD_OPC_CheckPredicate, 0, 6, 9, // Skip to: 8540 -/* 6230 */ MCD_OPC_Decode, 177, 8, 113, // Opcode: CXLGTR -/* 6234 */ MCD_OPC_FilterValue, 91, 8, 0, // Skip to: 6246 -/* 6238 */ MCD_OPC_CheckPredicate, 0, 250, 8, // Skip to: 8540 -/* 6242 */ MCD_OPC_Decode, 175, 8, 101, // Opcode: CXLFTR -/* 6246 */ MCD_OPC_FilterValue, 96, 62, 0, // Skip to: 6312 -/* 6250 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6253 */ MCD_OPC_FilterValue, 0, 235, 8, // Skip to: 8540 -/* 6257 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6260 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6268 -/* 6264 */ MCD_OPC_Decode, 155, 5, 61, // Opcode: CGRTAsmH -/* 6268 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6276 -/* 6272 */ MCD_OPC_Decode, 157, 5, 61, // Opcode: CGRTAsmL -/* 6276 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6284 -/* 6280 */ MCD_OPC_Decode, 159, 5, 61, // Opcode: CGRTAsmLH -/* 6284 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6292 -/* 6288 */ MCD_OPC_Decode, 154, 5, 61, // Opcode: CGRTAsmE -/* 6292 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6300 -/* 6296 */ MCD_OPC_Decode, 156, 5, 61, // Opcode: CGRTAsmHE -/* 6300 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6308 -/* 6304 */ MCD_OPC_Decode, 158, 5, 61, // Opcode: CGRTAsmLE -/* 6308 */ MCD_OPC_Decode, 153, 5, 73, // Opcode: CGRTAsm -/* 6312 */ MCD_OPC_FilterValue, 97, 62, 0, // Skip to: 6378 -/* 6316 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6319 */ MCD_OPC_FilterValue, 0, 169, 8, // Skip to: 8540 -/* 6323 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6326 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6334 -/* 6330 */ MCD_OPC_Decode, 207, 6, 61, // Opcode: CLGRTAsmH -/* 6334 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6342 -/* 6338 */ MCD_OPC_Decode, 209, 6, 61, // Opcode: CLGRTAsmL -/* 6342 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6350 -/* 6346 */ MCD_OPC_Decode, 211, 6, 61, // Opcode: CLGRTAsmLH -/* 6350 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6358 -/* 6354 */ MCD_OPC_Decode, 206, 6, 61, // Opcode: CLGRTAsmE -/* 6358 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6366 -/* 6362 */ MCD_OPC_Decode, 208, 6, 61, // Opcode: CLGRTAsmHE -/* 6366 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6374 -/* 6370 */ MCD_OPC_Decode, 210, 6, 61, // Opcode: CLGRTAsmLE -/* 6374 */ MCD_OPC_Decode, 205, 6, 73, // Opcode: CLGRTAsm -/* 6378 */ MCD_OPC_FilterValue, 114, 63, 0, // Skip to: 6445 -/* 6382 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6385 */ MCD_OPC_FilterValue, 0, 103, 8, // Skip to: 8540 -/* 6389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6392 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6400 -/* 6396 */ MCD_OPC_Decode, 249, 7, 8, // Opcode: CRTAsmH -/* 6400 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6408 -/* 6404 */ MCD_OPC_Decode, 251, 7, 8, // Opcode: CRTAsmL -/* 6408 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6416 -/* 6412 */ MCD_OPC_Decode, 253, 7, 8, // Opcode: CRTAsmLH -/* 6416 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6424 -/* 6420 */ MCD_OPC_Decode, 248, 7, 8, // Opcode: CRTAsmE -/* 6424 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6432 -/* 6428 */ MCD_OPC_Decode, 250, 7, 8, // Opcode: CRTAsmHE -/* 6432 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6440 -/* 6436 */ MCD_OPC_Decode, 252, 7, 8, // Opcode: CRTAsmLE -/* 6440 */ MCD_OPC_Decode, 247, 7, 139, 1, // Opcode: CRTAsm -/* 6445 */ MCD_OPC_FilterValue, 115, 63, 0, // Skip to: 6512 -/* 6449 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6452 */ MCD_OPC_FilterValue, 0, 36, 8, // Skip to: 8540 -/* 6456 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6459 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6467 -/* 6463 */ MCD_OPC_Decode, 178, 7, 8, // Opcode: CLRTAsmH -/* 6467 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6475 -/* 6471 */ MCD_OPC_Decode, 180, 7, 8, // Opcode: CLRTAsmL -/* 6475 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6483 -/* 6479 */ MCD_OPC_Decode, 182, 7, 8, // Opcode: CLRTAsmLH -/* 6483 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6491 -/* 6487 */ MCD_OPC_Decode, 177, 7, 8, // Opcode: CLRTAsmE -/* 6491 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6499 -/* 6495 */ MCD_OPC_Decode, 179, 7, 8, // Opcode: CLRTAsmHE -/* 6499 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6507 -/* 6503 */ MCD_OPC_Decode, 181, 7, 8, // Opcode: CLRTAsmLE -/* 6507 */ MCD_OPC_Decode, 176, 7, 139, 1, // Opcode: CLRTAsm -/* 6512 */ MCD_OPC_FilterValue, 128, 1, 11, 0, // Skip to: 6528 -/* 6517 */ MCD_OPC_CheckField, 8, 8, 0, 225, 7, // Skip to: 8540 -/* 6523 */ MCD_OPC_Decode, 229, 13, 135, 1, // Opcode: NGR -/* 6528 */ MCD_OPC_FilterValue, 129, 1, 11, 0, // Skip to: 6544 -/* 6533 */ MCD_OPC_CheckField, 8, 8, 0, 209, 7, // Skip to: 8540 -/* 6539 */ MCD_OPC_Decode, 247, 13, 135, 1, // Opcode: OGR -/* 6544 */ MCD_OPC_FilterValue, 130, 1, 11, 0, // Skip to: 6560 -/* 6549 */ MCD_OPC_CheckField, 8, 8, 0, 193, 7, // Skip to: 8540 -/* 6555 */ MCD_OPC_Decode, 229, 21, 135, 1, // Opcode: XGR -/* 6560 */ MCD_OPC_FilterValue, 131, 1, 11, 0, // Skip to: 6576 -/* 6565 */ MCD_OPC_CheckField, 8, 8, 0, 177, 7, // Skip to: 8540 -/* 6571 */ MCD_OPC_Decode, 251, 8, 140, 1, // Opcode: FLOGR -/* 6576 */ MCD_OPC_FilterValue, 132, 1, 10, 0, // Skip to: 6591 -/* 6581 */ MCD_OPC_CheckField, 8, 8, 0, 161, 7, // Skip to: 8540 -/* 6587 */ MCD_OPC_Decode, 202, 10, 61, // Opcode: LLGCR -/* 6591 */ MCD_OPC_FilterValue, 133, 1, 10, 0, // Skip to: 6606 -/* 6596 */ MCD_OPC_CheckField, 8, 8, 0, 146, 7, // Skip to: 8540 -/* 6602 */ MCD_OPC_Decode, 209, 10, 61, // Opcode: LLGHR -/* 6606 */ MCD_OPC_FilterValue, 134, 1, 10, 0, // Skip to: 6621 -/* 6611 */ MCD_OPC_CheckField, 8, 8, 0, 131, 7, // Skip to: 8540 -/* 6617 */ MCD_OPC_Decode, 164, 13, 68, // Opcode: MLGR -/* 6621 */ MCD_OPC_FilterValue, 135, 1, 10, 0, // Skip to: 6636 -/* 6626 */ MCD_OPC_CheckField, 8, 8, 0, 116, 7, // Skip to: 8540 -/* 6632 */ MCD_OPC_Decode, 203, 8, 68, // Opcode: DLGR -/* 6636 */ MCD_OPC_FilterValue, 136, 1, 11, 0, // Skip to: 6652 -/* 6641 */ MCD_OPC_CheckField, 8, 8, 0, 101, 7, // Skip to: 8540 -/* 6647 */ MCD_OPC_Decode, 132, 3, 135, 1, // Opcode: ALCGR -/* 6652 */ MCD_OPC_FilterValue, 137, 1, 11, 0, // Skip to: 6668 -/* 6657 */ MCD_OPC_CheckField, 8, 8, 0, 85, 7, // Skip to: 8540 -/* 6663 */ MCD_OPC_Decode, 221, 14, 135, 1, // Opcode: SLBGR -/* 6668 */ MCD_OPC_FilterValue, 138, 1, 10, 0, // Skip to: 6683 -/* 6673 */ MCD_OPC_CheckField, 8, 8, 0, 69, 7, // Skip to: 8540 -/* 6679 */ MCD_OPC_Decode, 137, 8, 68, // Opcode: CSPG -/* 6683 */ MCD_OPC_FilterValue, 141, 1, 10, 0, // Skip to: 6698 -/* 6688 */ MCD_OPC_CheckField, 8, 8, 0, 54, 7, // Skip to: 8540 -/* 6694 */ MCD_OPC_Decode, 228, 8, 8, // Opcode: EPSW -/* 6698 */ MCD_OPC_FilterValue, 142, 1, 16, 0, // Skip to: 6719 -/* 6703 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, // Skip to: 6714 -/* 6709 */ MCD_OPC_Decode, 136, 9, 141, 1, // Opcode: IDTEOpt -/* 6714 */ MCD_OPC_Decode, 135, 9, 142, 1, // Opcode: IDTE -/* 6719 */ MCD_OPC_FilterValue, 143, 1, 24, 0, // Skip to: 6748 -/* 6724 */ MCD_OPC_CheckPredicate, 8, 11, 0, // Skip to: 6739 -/* 6728 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, // Skip to: 6739 -/* 6734 */ MCD_OPC_Decode, 230, 7, 143, 1, // Opcode: CRDTEOpt -/* 6739 */ MCD_OPC_CheckPredicate, 8, 5, 7, // Skip to: 8540 -/* 6743 */ MCD_OPC_Decode, 229, 7, 144, 1, // Opcode: CRDTE -/* 6748 */ MCD_OPC_FilterValue, 144, 1, 22, 0, // Skip to: 6775 -/* 6753 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6756 */ MCD_OPC_FilterValue, 0, 244, 6, // Skip to: 8540 -/* 6760 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6770 -/* 6766 */ MCD_OPC_Decode, 203, 16, 71, // Opcode: TRTTOpt -/* 6770 */ MCD_OPC_Decode, 202, 16, 145, 1, // Opcode: TRTT -/* 6775 */ MCD_OPC_FilterValue, 145, 1, 22, 0, // Skip to: 6802 -/* 6780 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6783 */ MCD_OPC_FilterValue, 0, 217, 6, // Skip to: 8540 -/* 6787 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6797 -/* 6793 */ MCD_OPC_Decode, 198, 16, 71, // Opcode: TRTOOpt -/* 6797 */ MCD_OPC_Decode, 197, 16, 145, 1, // Opcode: TRTO -/* 6802 */ MCD_OPC_FilterValue, 146, 1, 22, 0, // Skip to: 6829 -/* 6807 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6810 */ MCD_OPC_FilterValue, 0, 190, 6, // Skip to: 8540 -/* 6814 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6824 -/* 6820 */ MCD_OPC_Decode, 193, 16, 71, // Opcode: TROTOpt -/* 6824 */ MCD_OPC_Decode, 192, 16, 145, 1, // Opcode: TROT -/* 6829 */ MCD_OPC_FilterValue, 147, 1, 22, 0, // Skip to: 6856 -/* 6834 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 6837 */ MCD_OPC_FilterValue, 0, 163, 6, // Skip to: 8540 -/* 6841 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6851 -/* 6847 */ MCD_OPC_Decode, 191, 16, 71, // Opcode: TROOOpt -/* 6851 */ MCD_OPC_Decode, 190, 16, 145, 1, // Opcode: TROO -/* 6856 */ MCD_OPC_FilterValue, 148, 1, 10, 0, // Skip to: 6871 -/* 6861 */ MCD_OPC_CheckField, 8, 8, 0, 137, 6, // Skip to: 8540 -/* 6867 */ MCD_OPC_Decode, 200, 10, 8, // Opcode: LLCR -/* 6871 */ MCD_OPC_FilterValue, 149, 1, 10, 0, // Skip to: 6886 -/* 6876 */ MCD_OPC_CheckField, 8, 8, 0, 122, 6, // Skip to: 8540 -/* 6882 */ MCD_OPC_Decode, 216, 10, 8, // Opcode: LLHR -/* 6886 */ MCD_OPC_FilterValue, 150, 1, 10, 0, // Skip to: 6901 -/* 6891 */ MCD_OPC_CheckField, 8, 8, 0, 107, 6, // Skip to: 8540 -/* 6897 */ MCD_OPC_Decode, 165, 13, 10, // Opcode: MLR -/* 6901 */ MCD_OPC_FilterValue, 151, 1, 10, 0, // Skip to: 6916 -/* 6906 */ MCD_OPC_CheckField, 8, 8, 0, 92, 6, // Skip to: 8540 -/* 6912 */ MCD_OPC_Decode, 204, 8, 10, // Opcode: DLR -/* 6916 */ MCD_OPC_FilterValue, 152, 1, 10, 0, // Skip to: 6931 -/* 6921 */ MCD_OPC_CheckField, 8, 8, 0, 77, 6, // Skip to: 8540 -/* 6927 */ MCD_OPC_Decode, 133, 3, 9, // Opcode: ALCR -/* 6931 */ MCD_OPC_FilterValue, 153, 1, 10, 0, // Skip to: 6946 -/* 6936 */ MCD_OPC_CheckField, 8, 8, 0, 62, 6, // Skip to: 8540 -/* 6942 */ MCD_OPC_Decode, 222, 14, 9, // Opcode: SLBR -/* 6946 */ MCD_OPC_FilterValue, 154, 1, 17, 0, // Skip to: 6968 -/* 6951 */ MCD_OPC_CheckField, 8, 8, 0, 47, 6, // Skip to: 8540 -/* 6957 */ MCD_OPC_CheckField, 0, 4, 0, 41, 6, // Skip to: 8540 -/* 6963 */ MCD_OPC_Decode, 225, 8, 146, 1, // Opcode: EPAIR -/* 6968 */ MCD_OPC_FilterValue, 155, 1, 17, 0, // Skip to: 6990 -/* 6973 */ MCD_OPC_CheckField, 8, 8, 0, 25, 6, // Skip to: 8540 -/* 6979 */ MCD_OPC_CheckField, 0, 4, 0, 19, 6, // Skip to: 8540 -/* 6985 */ MCD_OPC_Decode, 231, 8, 146, 1, // Opcode: ESAIR -/* 6990 */ MCD_OPC_FilterValue, 157, 1, 17, 0, // Skip to: 7012 -/* 6995 */ MCD_OPC_CheckField, 8, 8, 0, 3, 6, // Skip to: 8540 -/* 7001 */ MCD_OPC_CheckField, 0, 4, 0, 253, 5, // Skip to: 8540 -/* 7007 */ MCD_OPC_Decode, 234, 8, 147, 1, // Opcode: ESEA -/* 7012 */ MCD_OPC_FilterValue, 158, 1, 10, 0, // Skip to: 7027 -/* 7017 */ MCD_OPC_CheckField, 8, 8, 0, 237, 5, // Skip to: 8540 -/* 7023 */ MCD_OPC_Decode, 154, 14, 61, // Opcode: PTI -/* 7027 */ MCD_OPC_FilterValue, 159, 1, 17, 0, // Skip to: 7049 -/* 7032 */ MCD_OPC_CheckField, 8, 8, 0, 222, 5, // Skip to: 8540 -/* 7038 */ MCD_OPC_CheckField, 0, 4, 0, 216, 5, // Skip to: 8540 -/* 7044 */ MCD_OPC_Decode, 148, 15, 146, 1, // Opcode: SSAIR -/* 7049 */ MCD_OPC_FilterValue, 162, 1, 17, 0, // Skip to: 7071 -/* 7054 */ MCD_OPC_CheckField, 8, 8, 0, 200, 5, // Skip to: 8540 -/* 7060 */ MCD_OPC_CheckField, 0, 4, 0, 194, 5, // Skip to: 8540 -/* 7066 */ MCD_OPC_Decode, 152, 14, 148, 1, // Opcode: PTF -/* 7071 */ MCD_OPC_FilterValue, 170, 1, 5, 0, // Skip to: 7081 -/* 7076 */ MCD_OPC_Decode, 199, 12, 149, 1, // Opcode: LPTEA -/* 7081 */ MCD_OPC_FilterValue, 172, 1, 14, 0, // Skip to: 7100 -/* 7086 */ MCD_OPC_CheckPredicate, 9, 170, 5, // Skip to: 8540 -/* 7090 */ MCD_OPC_CheckField, 8, 8, 0, 164, 5, // Skip to: 8540 -/* 7096 */ MCD_OPC_Decode, 150, 9, 61, // Opcode: IRBM -/* 7100 */ MCD_OPC_FilterValue, 174, 1, 14, 0, // Skip to: 7119 -/* 7105 */ MCD_OPC_CheckPredicate, 10, 151, 5, // Skip to: 8540 -/* 7109 */ MCD_OPC_CheckField, 8, 8, 0, 145, 5, // Skip to: 8540 -/* 7115 */ MCD_OPC_Decode, 172, 14, 61, // Opcode: RRBM -/* 7119 */ MCD_OPC_FilterValue, 175, 1, 11, 0, // Skip to: 7135 -/* 7124 */ MCD_OPC_CheckField, 8, 8, 0, 130, 5, // Skip to: 8540 -/* 7130 */ MCD_OPC_Decode, 139, 14, 150, 1, // Opcode: PFMF -/* 7135 */ MCD_OPC_FilterValue, 176, 1, 21, 0, // Skip to: 7161 -/* 7140 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7143 */ MCD_OPC_FilterValue, 0, 113, 5, // Skip to: 8540 -/* 7147 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 7157 -/* 7153 */ MCD_OPC_Decode, 144, 8, 7, // Opcode: CU14Opt -/* 7157 */ MCD_OPC_Decode, 143, 8, 72, // Opcode: CU14 -/* 7161 */ MCD_OPC_FilterValue, 177, 1, 21, 0, // Skip to: 7187 -/* 7166 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7169 */ MCD_OPC_FilterValue, 0, 87, 5, // Skip to: 8540 -/* 7173 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 7183 -/* 7179 */ MCD_OPC_Decode, 148, 8, 7, // Opcode: CU24Opt -/* 7183 */ MCD_OPC_Decode, 147, 8, 72, // Opcode: CU24 -/* 7187 */ MCD_OPC_FilterValue, 178, 1, 10, 0, // Skip to: 7202 -/* 7192 */ MCD_OPC_CheckField, 8, 8, 0, 62, 5, // Skip to: 8540 -/* 7198 */ MCD_OPC_Decode, 149, 8, 7, // Opcode: CU41 -/* 7202 */ MCD_OPC_FilterValue, 179, 1, 10, 0, // Skip to: 7217 -/* 7207 */ MCD_OPC_CheckField, 8, 8, 0, 47, 5, // Skip to: 8540 -/* 7213 */ MCD_OPC_Decode, 150, 8, 7, // Opcode: CU42 -/* 7217 */ MCD_OPC_FilterValue, 189, 1, 23, 0, // Skip to: 7245 -/* 7222 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7225 */ MCD_OPC_FilterValue, 0, 31, 5, // Skip to: 8540 -/* 7229 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, // Skip to: 7240 -/* 7235 */ MCD_OPC_Decode, 201, 16, 151, 1, // Opcode: TRTREOpt -/* 7240 */ MCD_OPC_Decode, 200, 16, 152, 1, // Opcode: TRTRE -/* 7245 */ MCD_OPC_FilterValue, 190, 1, 10, 0, // Skip to: 7260 -/* 7250 */ MCD_OPC_CheckField, 8, 8, 0, 4, 5, // Skip to: 8540 -/* 7256 */ MCD_OPC_Decode, 146, 15, 69, // Opcode: SRSTU -/* 7260 */ MCD_OPC_FilterValue, 191, 1, 23, 0, // Skip to: 7288 -/* 7265 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7268 */ MCD_OPC_FilterValue, 0, 244, 4, // Skip to: 8540 -/* 7272 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, // Skip to: 7283 -/* 7278 */ MCD_OPC_Decode, 196, 16, 151, 1, // Opcode: TRTEOpt -/* 7283 */ MCD_OPC_Decode, 195, 16, 152, 1, // Opcode: TRTE -/* 7288 */ MCD_OPC_FilterValue, 200, 1, 15, 0, // Skip to: 7308 -/* 7293 */ MCD_OPC_CheckPredicate, 11, 219, 4, // Skip to: 8540 -/* 7297 */ MCD_OPC_CheckField, 8, 4, 0, 213, 4, // Skip to: 8540 -/* 7303 */ MCD_OPC_Decode, 251, 2, 153, 1, // Opcode: AHHHR -/* 7308 */ MCD_OPC_FilterValue, 201, 1, 15, 0, // Skip to: 7328 -/* 7313 */ MCD_OPC_CheckPredicate, 11, 199, 4, // Skip to: 8540 -/* 7317 */ MCD_OPC_CheckField, 8, 4, 0, 193, 4, // Skip to: 8540 -/* 7323 */ MCD_OPC_Decode, 209, 14, 153, 1, // Opcode: SHHHR -/* 7328 */ MCD_OPC_FilterValue, 202, 1, 15, 0, // Skip to: 7348 -/* 7333 */ MCD_OPC_CheckPredicate, 11, 179, 4, // Skip to: 8540 -/* 7337 */ MCD_OPC_CheckField, 8, 4, 0, 173, 4, // Skip to: 8540 -/* 7343 */ MCD_OPC_Decode, 143, 3, 153, 1, // Opcode: ALHHHR -/* 7348 */ MCD_OPC_FilterValue, 203, 1, 15, 0, // Skip to: 7368 -/* 7353 */ MCD_OPC_CheckPredicate, 11, 159, 4, // Skip to: 8540 -/* 7357 */ MCD_OPC_CheckField, 8, 4, 0, 153, 4, // Skip to: 8540 -/* 7363 */ MCD_OPC_Decode, 233, 14, 153, 1, // Opcode: SLHHHR -/* 7368 */ MCD_OPC_FilterValue, 205, 1, 15, 0, // Skip to: 7388 -/* 7373 */ MCD_OPC_CheckPredicate, 11, 139, 4, // Skip to: 8540 -/* 7377 */ MCD_OPC_CheckField, 8, 8, 0, 133, 4, // Skip to: 8540 -/* 7383 */ MCD_OPC_Decode, 173, 5, 154, 1, // Opcode: CHHR -/* 7388 */ MCD_OPC_FilterValue, 207, 1, 15, 0, // Skip to: 7408 -/* 7393 */ MCD_OPC_CheckPredicate, 11, 119, 4, // Skip to: 8540 -/* 7397 */ MCD_OPC_CheckField, 8, 8, 0, 113, 4, // Skip to: 8540 -/* 7403 */ MCD_OPC_Decode, 235, 6, 154, 1, // Opcode: CLHHR -/* 7408 */ MCD_OPC_FilterValue, 216, 1, 15, 0, // Skip to: 7428 -/* 7413 */ MCD_OPC_CheckPredicate, 11, 99, 4, // Skip to: 8540 -/* 7417 */ MCD_OPC_CheckField, 8, 4, 0, 93, 4, // Skip to: 8540 -/* 7423 */ MCD_OPC_Decode, 252, 2, 155, 1, // Opcode: AHHLR -/* 7428 */ MCD_OPC_FilterValue, 217, 1, 15, 0, // Skip to: 7448 -/* 7433 */ MCD_OPC_CheckPredicate, 11, 79, 4, // Skip to: 8540 -/* 7437 */ MCD_OPC_CheckField, 8, 4, 0, 73, 4, // Skip to: 8540 -/* 7443 */ MCD_OPC_Decode, 210, 14, 155, 1, // Opcode: SHHLR -/* 7448 */ MCD_OPC_FilterValue, 218, 1, 15, 0, // Skip to: 7468 -/* 7453 */ MCD_OPC_CheckPredicate, 11, 59, 4, // Skip to: 8540 -/* 7457 */ MCD_OPC_CheckField, 8, 4, 0, 53, 4, // Skip to: 8540 -/* 7463 */ MCD_OPC_Decode, 144, 3, 155, 1, // Opcode: ALHHLR -/* 7468 */ MCD_OPC_FilterValue, 219, 1, 15, 0, // Skip to: 7488 -/* 7473 */ MCD_OPC_CheckPredicate, 11, 39, 4, // Skip to: 8540 -/* 7477 */ MCD_OPC_CheckField, 8, 4, 0, 33, 4, // Skip to: 8540 -/* 7483 */ MCD_OPC_Decode, 234, 14, 155, 1, // Opcode: SLHHLR -/* 7488 */ MCD_OPC_FilterValue, 221, 1, 15, 0, // Skip to: 7508 -/* 7493 */ MCD_OPC_CheckPredicate, 11, 19, 4, // Skip to: 8540 -/* 7497 */ MCD_OPC_CheckField, 8, 8, 0, 13, 4, // Skip to: 8540 -/* 7503 */ MCD_OPC_Decode, 176, 5, 156, 1, // Opcode: CHLR -/* 7508 */ MCD_OPC_FilterValue, 223, 1, 15, 0, // Skip to: 7528 -/* 7513 */ MCD_OPC_CheckPredicate, 11, 255, 3, // Skip to: 8540 -/* 7517 */ MCD_OPC_CheckField, 8, 8, 0, 249, 3, // Skip to: 8540 -/* 7523 */ MCD_OPC_Decode, 237, 6, 156, 1, // Opcode: CLHLR -/* 7528 */ MCD_OPC_FilterValue, 224, 1, 201, 0, // Skip to: 7734 -/* 7533 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7536 */ MCD_OPC_FilterValue, 0, 232, 3, // Skip to: 8540 -/* 7540 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7543 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7556 -/* 7547 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 7725 -/* 7551 */ MCD_OPC_Decode, 176, 11, 157, 1, // Opcode: LOCFHRAsmO -/* 7556 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7569 -/* 7560 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 7725 -/* 7564 */ MCD_OPC_Decode, 160, 11, 157, 1, // Opcode: LOCFHRAsmH -/* 7569 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7582 -/* 7573 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 7725 -/* 7577 */ MCD_OPC_Decode, 170, 11, 157, 1, // Opcode: LOCFHRAsmNLE -/* 7582 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7595 -/* 7586 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 7725 -/* 7590 */ MCD_OPC_Decode, 162, 11, 157, 1, // Opcode: LOCFHRAsmL -/* 7595 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7608 -/* 7599 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 7725 -/* 7603 */ MCD_OPC_Decode, 168, 11, 157, 1, // Opcode: LOCFHRAsmNHE -/* 7608 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7621 -/* 7612 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 7725 -/* 7616 */ MCD_OPC_Decode, 164, 11, 157, 1, // Opcode: LOCFHRAsmLH -/* 7621 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7634 -/* 7625 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 7725 -/* 7629 */ MCD_OPC_Decode, 166, 11, 157, 1, // Opcode: LOCFHRAsmNE -/* 7634 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7647 -/* 7638 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 7725 -/* 7642 */ MCD_OPC_Decode, 159, 11, 157, 1, // Opcode: LOCFHRAsmE -/* 7647 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7660 -/* 7651 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 7725 -/* 7655 */ MCD_OPC_Decode, 171, 11, 157, 1, // Opcode: LOCFHRAsmNLH -/* 7660 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7673 -/* 7664 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 7725 -/* 7668 */ MCD_OPC_Decode, 161, 11, 157, 1, // Opcode: LOCFHRAsmHE -/* 7673 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7686 -/* 7677 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 7725 -/* 7681 */ MCD_OPC_Decode, 169, 11, 157, 1, // Opcode: LOCFHRAsmNL -/* 7686 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7699 -/* 7690 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 7725 -/* 7694 */ MCD_OPC_Decode, 163, 11, 157, 1, // Opcode: LOCFHRAsmLE -/* 7699 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7712 -/* 7703 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 7725 -/* 7707 */ MCD_OPC_Decode, 167, 11, 157, 1, // Opcode: LOCFHRAsmNH -/* 7712 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7725 -/* 7716 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 7725 -/* 7720 */ MCD_OPC_Decode, 173, 11, 157, 1, // Opcode: LOCFHRAsmNO -/* 7725 */ MCD_OPC_CheckPredicate, 12, 43, 3, // Skip to: 8540 -/* 7729 */ MCD_OPC_Decode, 158, 11, 158, 1, // Opcode: LOCFHRAsm -/* 7734 */ MCD_OPC_FilterValue, 225, 1, 14, 0, // Skip to: 7753 -/* 7739 */ MCD_OPC_CheckPredicate, 13, 29, 3, // Skip to: 8540 -/* 7743 */ MCD_OPC_CheckField, 8, 8, 0, 23, 3, // Skip to: 8540 -/* 7749 */ MCD_OPC_Decode, 146, 14, 61, // Opcode: POPCNT -/* 7753 */ MCD_OPC_FilterValue, 226, 1, 201, 0, // Skip to: 7959 -/* 7758 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 7761 */ MCD_OPC_FilterValue, 0, 7, 3, // Skip to: 8540 -/* 7765 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7768 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7781 -/* 7772 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 7950 -/* 7776 */ MCD_OPC_Decode, 242, 11, 135, 1, // Opcode: LOCGRAsmO -/* 7781 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7794 -/* 7785 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 7950 -/* 7789 */ MCD_OPC_Decode, 226, 11, 135, 1, // Opcode: LOCGRAsmH -/* 7794 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7807 -/* 7798 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 7950 -/* 7802 */ MCD_OPC_Decode, 236, 11, 135, 1, // Opcode: LOCGRAsmNLE -/* 7807 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7820 -/* 7811 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 7950 -/* 7815 */ MCD_OPC_Decode, 228, 11, 135, 1, // Opcode: LOCGRAsmL -/* 7820 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7833 -/* 7824 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 7950 -/* 7828 */ MCD_OPC_Decode, 234, 11, 135, 1, // Opcode: LOCGRAsmNHE -/* 7833 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7846 -/* 7837 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 7950 -/* 7841 */ MCD_OPC_Decode, 230, 11, 135, 1, // Opcode: LOCGRAsmLH -/* 7846 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7859 -/* 7850 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 7950 -/* 7854 */ MCD_OPC_Decode, 232, 11, 135, 1, // Opcode: LOCGRAsmNE -/* 7859 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7872 -/* 7863 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 7950 -/* 7867 */ MCD_OPC_Decode, 225, 11, 135, 1, // Opcode: LOCGRAsmE -/* 7872 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7885 -/* 7876 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 7950 -/* 7880 */ MCD_OPC_Decode, 237, 11, 135, 1, // Opcode: LOCGRAsmNLH -/* 7885 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7898 -/* 7889 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 7950 -/* 7893 */ MCD_OPC_Decode, 227, 11, 135, 1, // Opcode: LOCGRAsmHE -/* 7898 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7911 -/* 7902 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 7950 -/* 7906 */ MCD_OPC_Decode, 235, 11, 135, 1, // Opcode: LOCGRAsmNL -/* 7911 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7924 -/* 7915 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 7950 -/* 7919 */ MCD_OPC_Decode, 229, 11, 135, 1, // Opcode: LOCGRAsmLE -/* 7924 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7937 -/* 7928 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 7950 -/* 7932 */ MCD_OPC_Decode, 233, 11, 135, 1, // Opcode: LOCGRAsmNH -/* 7937 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7950 -/* 7941 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 7950 -/* 7945 */ MCD_OPC_Decode, 239, 11, 135, 1, // Opcode: LOCGRAsmNO -/* 7950 */ MCD_OPC_CheckPredicate, 14, 74, 2, // Skip to: 8540 -/* 7954 */ MCD_OPC_Decode, 224, 11, 159, 1, // Opcode: LOCGRAsm -/* 7959 */ MCD_OPC_FilterValue, 228, 1, 15, 0, // Skip to: 7979 -/* 7964 */ MCD_OPC_CheckPredicate, 15, 60, 2, // Skip to: 8540 -/* 7968 */ MCD_OPC_CheckField, 8, 4, 0, 54, 2, // Skip to: 8540 -/* 7974 */ MCD_OPC_Decode, 230, 13, 141, 1, // Opcode: NGRK -/* 7979 */ MCD_OPC_FilterValue, 230, 1, 15, 0, // Skip to: 7999 -/* 7984 */ MCD_OPC_CheckPredicate, 15, 40, 2, // Skip to: 8540 -/* 7988 */ MCD_OPC_CheckField, 8, 4, 0, 34, 2, // Skip to: 8540 -/* 7994 */ MCD_OPC_Decode, 248, 13, 141, 1, // Opcode: OGRK -/* 7999 */ MCD_OPC_FilterValue, 231, 1, 15, 0, // Skip to: 8019 -/* 8004 */ MCD_OPC_CheckPredicate, 15, 20, 2, // Skip to: 8540 -/* 8008 */ MCD_OPC_CheckField, 8, 4, 0, 14, 2, // Skip to: 8540 -/* 8014 */ MCD_OPC_Decode, 230, 21, 141, 1, // Opcode: XGRK -/* 8019 */ MCD_OPC_FilterValue, 232, 1, 15, 0, // Skip to: 8039 -/* 8024 */ MCD_OPC_CheckPredicate, 15, 0, 2, // Skip to: 8540 -/* 8028 */ MCD_OPC_CheckField, 8, 4, 0, 250, 1, // Skip to: 8540 -/* 8034 */ MCD_OPC_Decode, 248, 2, 141, 1, // Opcode: AGRK -/* 8039 */ MCD_OPC_FilterValue, 233, 1, 15, 0, // Skip to: 8059 -/* 8044 */ MCD_OPC_CheckPredicate, 15, 236, 1, // Skip to: 8540 -/* 8048 */ MCD_OPC_CheckField, 8, 4, 0, 230, 1, // Skip to: 8540 -/* 8054 */ MCD_OPC_Decode, 207, 14, 141, 1, // Opcode: SGRK -/* 8059 */ MCD_OPC_FilterValue, 234, 1, 15, 0, // Skip to: 8079 -/* 8064 */ MCD_OPC_CheckPredicate, 15, 216, 1, // Skip to: 8540 -/* 8068 */ MCD_OPC_CheckField, 8, 4, 0, 210, 1, // Skip to: 8540 -/* 8074 */ MCD_OPC_Decode, 141, 3, 141, 1, // Opcode: ALGRK -/* 8079 */ MCD_OPC_FilterValue, 235, 1, 15, 0, // Skip to: 8099 -/* 8084 */ MCD_OPC_CheckPredicate, 15, 196, 1, // Skip to: 8540 -/* 8088 */ MCD_OPC_CheckField, 8, 4, 0, 190, 1, // Skip to: 8540 -/* 8094 */ MCD_OPC_Decode, 232, 14, 141, 1, // Opcode: SLGRK -/* 8099 */ MCD_OPC_FilterValue, 236, 1, 15, 0, // Skip to: 8119 -/* 8104 */ MCD_OPC_CheckPredicate, 16, 176, 1, // Skip to: 8540 -/* 8108 */ MCD_OPC_CheckField, 8, 4, 0, 170, 1, // Skip to: 8540 -/* 8114 */ MCD_OPC_Decode, 158, 13, 160, 1, // Opcode: MGRK -/* 8119 */ MCD_OPC_FilterValue, 237, 1, 15, 0, // Skip to: 8139 -/* 8124 */ MCD_OPC_CheckPredicate, 16, 156, 1, // Skip to: 8540 -/* 8128 */ MCD_OPC_CheckField, 8, 4, 0, 150, 1, // Skip to: 8540 -/* 8134 */ MCD_OPC_Decode, 186, 13, 141, 1, // Opcode: MSGRKC -/* 8139 */ MCD_OPC_FilterValue, 242, 1, 187, 0, // Skip to: 8331 -/* 8144 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 8147 */ MCD_OPC_FilterValue, 0, 133, 1, // Skip to: 8540 -/* 8151 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8154 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 8166 -/* 8158 */ MCD_OPC_CheckPredicate, 14, 160, 0, // Skip to: 8322 -/* 8162 */ MCD_OPC_Decode, 180, 12, 9, // Opcode: LOCRAsmO -/* 8166 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 8178 -/* 8170 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 8322 -/* 8174 */ MCD_OPC_Decode, 164, 12, 9, // Opcode: LOCRAsmH -/* 8178 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 8190 -/* 8182 */ MCD_OPC_CheckPredicate, 14, 136, 0, // Skip to: 8322 -/* 8186 */ MCD_OPC_Decode, 174, 12, 9, // Opcode: LOCRAsmNLE -/* 8190 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 8202 -/* 8194 */ MCD_OPC_CheckPredicate, 14, 124, 0, // Skip to: 8322 -/* 8198 */ MCD_OPC_Decode, 166, 12, 9, // Opcode: LOCRAsmL -/* 8202 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 8214 -/* 8206 */ MCD_OPC_CheckPredicate, 14, 112, 0, // Skip to: 8322 -/* 8210 */ MCD_OPC_Decode, 172, 12, 9, // Opcode: LOCRAsmNHE -/* 8214 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 8226 -/* 8218 */ MCD_OPC_CheckPredicate, 14, 100, 0, // Skip to: 8322 -/* 8222 */ MCD_OPC_Decode, 168, 12, 9, // Opcode: LOCRAsmLH -/* 8226 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 8238 -/* 8230 */ MCD_OPC_CheckPredicate, 14, 88, 0, // Skip to: 8322 -/* 8234 */ MCD_OPC_Decode, 170, 12, 9, // Opcode: LOCRAsmNE -/* 8238 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 8250 -/* 8242 */ MCD_OPC_CheckPredicate, 14, 76, 0, // Skip to: 8322 -/* 8246 */ MCD_OPC_Decode, 163, 12, 9, // Opcode: LOCRAsmE -/* 8250 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 8262 -/* 8254 */ MCD_OPC_CheckPredicate, 14, 64, 0, // Skip to: 8322 -/* 8258 */ MCD_OPC_Decode, 175, 12, 9, // Opcode: LOCRAsmNLH -/* 8262 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 8274 -/* 8266 */ MCD_OPC_CheckPredicate, 14, 52, 0, // Skip to: 8322 -/* 8270 */ MCD_OPC_Decode, 165, 12, 9, // Opcode: LOCRAsmHE -/* 8274 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 8286 -/* 8278 */ MCD_OPC_CheckPredicate, 14, 40, 0, // Skip to: 8322 -/* 8282 */ MCD_OPC_Decode, 173, 12, 9, // Opcode: LOCRAsmNL -/* 8286 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 8298 -/* 8290 */ MCD_OPC_CheckPredicate, 14, 28, 0, // Skip to: 8322 -/* 8294 */ MCD_OPC_Decode, 167, 12, 9, // Opcode: LOCRAsmLE -/* 8298 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 8310 -/* 8302 */ MCD_OPC_CheckPredicate, 14, 16, 0, // Skip to: 8322 -/* 8306 */ MCD_OPC_Decode, 171, 12, 9, // Opcode: LOCRAsmNH -/* 8310 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 8322 -/* 8314 */ MCD_OPC_CheckPredicate, 14, 4, 0, // Skip to: 8322 -/* 8318 */ MCD_OPC_Decode, 177, 12, 9, // Opcode: LOCRAsmNO -/* 8322 */ MCD_OPC_CheckPredicate, 14, 214, 0, // Skip to: 8540 -/* 8326 */ MCD_OPC_Decode, 162, 12, 161, 1, // Opcode: LOCRAsm -/* 8331 */ MCD_OPC_FilterValue, 244, 1, 15, 0, // Skip to: 8351 -/* 8336 */ MCD_OPC_CheckPredicate, 15, 200, 0, // Skip to: 8540 -/* 8340 */ MCD_OPC_CheckField, 8, 4, 0, 194, 0, // Skip to: 8540 -/* 8346 */ MCD_OPC_Decode, 241, 13, 162, 1, // Opcode: NRK -/* 8351 */ MCD_OPC_FilterValue, 246, 1, 15, 0, // Skip to: 8371 -/* 8356 */ MCD_OPC_CheckPredicate, 15, 180, 0, // Skip to: 8540 -/* 8360 */ MCD_OPC_CheckField, 8, 4, 0, 174, 0, // Skip to: 8540 -/* 8366 */ MCD_OPC_Decode, 130, 14, 162, 1, // Opcode: ORK -/* 8371 */ MCD_OPC_FilterValue, 247, 1, 15, 0, // Skip to: 8391 -/* 8376 */ MCD_OPC_CheckPredicate, 15, 160, 0, // Skip to: 8540 -/* 8380 */ MCD_OPC_CheckField, 8, 4, 0, 154, 0, // Skip to: 8540 -/* 8386 */ MCD_OPC_Decode, 236, 21, 162, 1, // Opcode: XRK -/* 8391 */ MCD_OPC_FilterValue, 248, 1, 15, 0, // Skip to: 8411 -/* 8396 */ MCD_OPC_CheckPredicate, 15, 140, 0, // Skip to: 8540 -/* 8400 */ MCD_OPC_CheckField, 8, 4, 0, 134, 0, // Skip to: 8540 -/* 8406 */ MCD_OPC_Decode, 154, 3, 162, 1, // Opcode: ARK -/* 8411 */ MCD_OPC_FilterValue, 249, 1, 15, 0, // Skip to: 8431 -/* 8416 */ MCD_OPC_CheckPredicate, 15, 120, 0, // Skip to: 8540 -/* 8420 */ MCD_OPC_CheckField, 8, 4, 0, 114, 0, // Skip to: 8540 -/* 8426 */ MCD_OPC_Decode, 137, 15, 162, 1, // Opcode: SRK -/* 8431 */ MCD_OPC_FilterValue, 250, 1, 15, 0, // Skip to: 8451 -/* 8436 */ MCD_OPC_CheckPredicate, 15, 100, 0, // Skip to: 8540 -/* 8440 */ MCD_OPC_CheckField, 8, 4, 0, 94, 0, // Skip to: 8540 -/* 8446 */ MCD_OPC_Decode, 147, 3, 162, 1, // Opcode: ALRK -/* 8451 */ MCD_OPC_FilterValue, 251, 1, 15, 0, // Skip to: 8471 -/* 8456 */ MCD_OPC_CheckPredicate, 15, 80, 0, // Skip to: 8540 -/* 8460 */ MCD_OPC_CheckField, 8, 4, 0, 74, 0, // Skip to: 8540 -/* 8466 */ MCD_OPC_Decode, 239, 14, 162, 1, // Opcode: SLRK -/* 8471 */ MCD_OPC_FilterValue, 253, 1, 64, 0, // Skip to: 8540 -/* 8476 */ MCD_OPC_CheckPredicate, 16, 60, 0, // Skip to: 8540 -/* 8480 */ MCD_OPC_CheckField, 8, 4, 0, 54, 0, // Skip to: 8540 -/* 8486 */ MCD_OPC_Decode, 188, 13, 162, 1, // Opcode: MSRKC -/* 8491 */ MCD_OPC_FilterValue, 186, 1, 4, 0, // Skip to: 8500 -/* 8496 */ MCD_OPC_Decode, 132, 8, 35, // Opcode: CS -/* 8500 */ MCD_OPC_FilterValue, 187, 1, 5, 0, // Skip to: 8510 -/* 8505 */ MCD_OPC_Decode, 157, 4, 163, 1, // Opcode: CDS -/* 8510 */ MCD_OPC_FilterValue, 189, 1, 5, 0, // Skip to: 8520 -/* 8515 */ MCD_OPC_Decode, 142, 7, 164, 1, // Opcode: CLM -/* 8520 */ MCD_OPC_FilterValue, 190, 1, 5, 0, // Skip to: 8530 -/* 8525 */ MCD_OPC_Decode, 164, 15, 164, 1, // Opcode: STCM -/* 8530 */ MCD_OPC_FilterValue, 191, 1, 5, 0, // Skip to: 8540 -/* 8535 */ MCD_OPC_Decode, 131, 9, 165, 1, // Opcode: ICM -/* 8540 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 3 */ MCD_OPC_FilterValue, + 64, + 4, + 0, + 0, // Skip to: 12 + /* 8 */ MCD_OPC_Decode, + 174, + 17, + 20, // Opcode: STH + /* 12 */ MCD_OPC_FilterValue, + 65, + 4, + 0, + 0, // Skip to: 21 + /* 17 */ MCD_OPC_Decode, + 141, + 11, + 21, // Opcode: LA + /* 21 */ MCD_OPC_FilterValue, + 66, + 4, + 0, + 0, // Skip to: 30 + /* 26 */ MCD_OPC_Decode, + 149, + 17, + 20, // Opcode: STC + /* 30 */ MCD_OPC_FilterValue, + 67, + 4, + 0, + 0, // Skip to: 39 + /* 35 */ MCD_OPC_Decode, + 153, + 10, + 22, // Opcode: IC + /* 39 */ MCD_OPC_FilterValue, + 68, + 4, + 0, + 0, // Skip to: 48 + /* 44 */ MCD_OPC_Decode, + 135, + 10, + 23, // Opcode: EX + /* 48 */ MCD_OPC_FilterValue, + 69, + 4, + 0, + 0, // Skip to: 57 + /* 53 */ MCD_OPC_Decode, + 191, + 4, + 21, // Opcode: BAL + /* 57 */ MCD_OPC_FilterValue, + 70, + 4, + 0, + 0, // Skip to: 66 + /* 62 */ MCD_OPC_Decode, + 220, + 4, + 24, // Opcode: BCT + /* 66 */ MCD_OPC_FilterValue, + 71, + 142, + 0, + 0, // Skip to: 213 + /* 71 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 74 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 83 + /* 79 */ MCD_OPC_Decode, + 213, + 4, + 25, // Opcode: BAsmO + /* 83 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 92 + /* 88 */ MCD_OPC_Decode, + 197, + 4, + 25, // Opcode: BAsmH + /* 92 */ MCD_OPC_FilterValue, + 3, + 4, + 0, + 0, // Skip to: 101 + /* 97 */ MCD_OPC_Decode, + 207, + 4, + 25, // Opcode: BAsmNLE + /* 101 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 110 + /* 106 */ MCD_OPC_Decode, + 199, + 4, + 25, // Opcode: BAsmL + /* 110 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 119 + /* 115 */ MCD_OPC_Decode, + 205, + 4, + 25, // Opcode: BAsmNHE + /* 119 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 128 + /* 124 */ MCD_OPC_Decode, + 201, + 4, + 25, // Opcode: BAsmLH + /* 128 */ MCD_OPC_FilterValue, + 7, + 4, + 0, + 0, // Skip to: 137 + /* 133 */ MCD_OPC_Decode, + 203, + 4, + 25, // Opcode: BAsmNE + /* 137 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 146 + /* 142 */ MCD_OPC_Decode, + 196, + 4, + 25, // Opcode: BAsmE + /* 146 */ MCD_OPC_FilterValue, + 9, + 4, + 0, + 0, // Skip to: 155 + /* 151 */ MCD_OPC_Decode, + 208, + 4, + 25, // Opcode: BAsmNLH + /* 155 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 164 + /* 160 */ MCD_OPC_Decode, + 198, + 4, + 25, // Opcode: BAsmHE + /* 164 */ MCD_OPC_FilterValue, + 11, + 4, + 0, + 0, // Skip to: 173 + /* 169 */ MCD_OPC_Decode, + 206, + 4, + 25, // Opcode: BAsmNL + /* 173 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 182 + /* 178 */ MCD_OPC_Decode, + 200, + 4, + 25, // Opcode: BAsmLE + /* 182 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 191 + /* 187 */ MCD_OPC_Decode, + 204, + 4, + 25, // Opcode: BAsmNH + /* 191 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 200 + /* 196 */ MCD_OPC_Decode, + 210, + 4, + 25, // Opcode: BAsmNO + /* 200 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 209 + /* 205 */ MCD_OPC_Decode, + 189, + 4, + 25, // Opcode: B + /* 209 */ MCD_OPC_Decode, + 217, + 4, + 26, // Opcode: BCAsm + /* 213 */ MCD_OPC_FilterValue, + 72, + 4, + 0, + 0, // Skip to: 222 + /* 218 */ MCD_OPC_Decode, + 225, + 11, + 20, // Opcode: LH + /* 222 */ MCD_OPC_FilterValue, + 73, + 4, + 0, + 0, // Skip to: 231 + /* 227 */ MCD_OPC_Decode, + 195, + 6, + 20, // Opcode: CH + /* 231 */ MCD_OPC_FilterValue, + 74, + 4, + 0, + 0, // Skip to: 240 + /* 236 */ MCD_OPC_Decode, + 146, + 4, + 24, // Opcode: AH + /* 240 */ MCD_OPC_FilterValue, + 75, + 4, + 0, + 0, // Skip to: 249 + /* 245 */ MCD_OPC_Decode, + 197, + 16, + 24, // Opcode: SH + /* 249 */ MCD_OPC_FilterValue, + 76, + 4, + 0, + 0, // Skip to: 258 + /* 254 */ MCD_OPC_Decode, + 193, + 14, + 24, // Opcode: MH + /* 258 */ MCD_OPC_FilterValue, + 77, + 4, + 0, + 0, // Skip to: 267 + /* 263 */ MCD_OPC_Decode, + 193, + 4, + 21, // Opcode: BAS + /* 267 */ MCD_OPC_FilterValue, + 78, + 4, + 0, + 0, // Skip to: 276 + /* 272 */ MCD_OPC_Decode, + 185, + 9, + 20, // Opcode: CVD + /* 276 */ MCD_OPC_FilterValue, + 79, + 4, + 0, + 0, // Skip to: 285 + /* 281 */ MCD_OPC_Decode, + 182, + 9, + 24, // Opcode: CVB + /* 285 */ MCD_OPC_FilterValue, + 80, + 4, + 0, + 0, // Skip to: 294 + /* 290 */ MCD_OPC_Decode, + 144, + 17, + 20, // Opcode: ST + /* 294 */ MCD_OPC_FilterValue, + 81, + 4, + 0, + 0, // Skip to: 303 + /* 299 */ MCD_OPC_Decode, + 146, + 11, + 21, // Opcode: LAE + /* 303 */ MCD_OPC_FilterValue, + 84, + 4, + 0, + 0, // Skip to: 312 + /* 308 */ MCD_OPC_Decode, + 133, + 15, + 24, // Opcode: N + /* 312 */ MCD_OPC_FilterValue, + 85, + 4, + 0, + 0, // Skip to: 321 + /* 317 */ MCD_OPC_Decode, + 248, + 6, + 20, // Opcode: CL + /* 321 */ MCD_OPC_FilterValue, + 86, + 4, + 0, + 0, // Skip to: 330 + /* 326 */ MCD_OPC_Decode, + 161, + 15, + 24, // Opcode: O + /* 330 */ MCD_OPC_FilterValue, + 87, + 4, + 0, + 0, // Skip to: 339 + /* 335 */ MCD_OPC_Decode, + 165, + 24, + 24, // Opcode: X + /* 339 */ MCD_OPC_FilterValue, + 88, + 4, + 0, + 0, // Skip to: 348 + /* 344 */ MCD_OPC_Decode, + 140, + 11, + 20, // Opcode: L + /* 348 */ MCD_OPC_FilterValue, + 89, + 4, + 0, + 0, // Skip to: 357 + /* 353 */ MCD_OPC_Decode, + 162, + 5, + 20, // Opcode: C + /* 357 */ MCD_OPC_FilterValue, + 90, + 4, + 0, + 0, // Skip to: 366 + /* 362 */ MCD_OPC_Decode, + 252, + 3, + 24, // Opcode: A + /* 366 */ MCD_OPC_FilterValue, + 91, + 4, + 0, + 0, // Skip to: 375 + /* 371 */ MCD_OPC_Decode, + 228, + 15, + 24, // Opcode: S + /* 375 */ MCD_OPC_FilterValue, + 92, + 4, + 0, + 0, // Skip to: 384 + /* 380 */ MCD_OPC_Decode, + 156, + 14, + 27, // Opcode: M + /* 384 */ MCD_OPC_FilterValue, + 93, + 4, + 0, + 0, // Skip to: 393 + /* 389 */ MCD_OPC_Decode, + 211, + 9, + 27, // Opcode: D + /* 393 */ MCD_OPC_FilterValue, + 94, + 4, + 0, + 0, // Skip to: 402 + /* 398 */ MCD_OPC_Decode, + 153, + 4, + 24, // Opcode: AL + /* 402 */ MCD_OPC_FilterValue, + 95, + 4, + 0, + 0, // Skip to: 411 + /* 407 */ MCD_OPC_Decode, + 204, + 16, + 24, // Opcode: SL + /* 411 */ MCD_OPC_FilterValue, + 96, + 4, + 0, + 0, // Skip to: 420 + /* 416 */ MCD_OPC_Decode, + 163, + 17, + 28, // Opcode: STD + /* 420 */ MCD_OPC_FilterValue, + 103, + 4, + 0, + 0, // Skip to: 429 + /* 425 */ MCD_OPC_Decode, + 248, + 14, + 29, // Opcode: MXD + /* 429 */ MCD_OPC_FilterValue, + 104, + 4, + 0, + 0, // Skip to: 438 + /* 434 */ MCD_OPC_Decode, + 179, + 11, + 28, // Opcode: LD + /* 438 */ MCD_OPC_FilterValue, + 105, + 4, + 0, + 0, // Skip to: 447 + /* 443 */ MCD_OPC_Decode, + 163, + 5, + 28, // Opcode: CD + /* 447 */ MCD_OPC_FilterValue, + 106, + 4, + 0, + 0, // Skip to: 456 + /* 452 */ MCD_OPC_Decode, + 253, + 3, + 30, // Opcode: AD + /* 456 */ MCD_OPC_FilterValue, + 107, + 4, + 0, + 0, // Skip to: 465 + /* 461 */ MCD_OPC_Decode, + 241, + 15, + 30, // Opcode: SD + /* 465 */ MCD_OPC_FilterValue, + 108, + 4, + 0, + 0, // Skip to: 474 + /* 470 */ MCD_OPC_Decode, + 172, + 14, + 30, // Opcode: MD + /* 474 */ MCD_OPC_FilterValue, + 109, + 4, + 0, + 0, // Skip to: 483 + /* 479 */ MCD_OPC_Decode, + 212, + 9, + 30, // Opcode: DD + /* 483 */ MCD_OPC_FilterValue, + 110, + 4, + 0, + 0, // Skip to: 492 + /* 488 */ MCD_OPC_Decode, + 182, + 4, + 30, // Opcode: AW + /* 492 */ MCD_OPC_FilterValue, + 111, + 4, + 0, + 0, // Skip to: 501 + /* 497 */ MCD_OPC_Decode, + 139, + 18, + 30, // Opcode: SW + /* 501 */ MCD_OPC_FilterValue, + 112, + 4, + 0, + 0, // Skip to: 510 + /* 506 */ MCD_OPC_Decode, + 165, + 17, + 31, // Opcode: STE + /* 510 */ MCD_OPC_FilterValue, + 113, + 4, + 0, + 0, // Skip to: 519 + /* 515 */ MCD_OPC_Decode, + 202, + 14, + 24, // Opcode: MS + /* 519 */ MCD_OPC_FilterValue, + 120, + 4, + 0, + 0, // Skip to: 528 + /* 524 */ MCD_OPC_Decode, + 194, + 11, + 31, // Opcode: LE + /* 528 */ MCD_OPC_FilterValue, + 121, + 4, + 0, + 0, // Skip to: 537 + /* 533 */ MCD_OPC_Decode, + 188, + 5, + 31, // Opcode: CE + /* 537 */ MCD_OPC_FilterValue, + 122, + 4, + 0, + 0, // Skip to: 546 + /* 542 */ MCD_OPC_Decode, + 131, + 4, + 32, // Opcode: AE + /* 546 */ MCD_OPC_FilterValue, + 123, + 4, + 0, + 0, // Skip to: 555 + /* 551 */ MCD_OPC_Decode, + 247, + 15, + 32, // Opcode: SE + /* 555 */ MCD_OPC_FilterValue, + 124, + 4, + 0, + 0, // Skip to: 564 + /* 560 */ MCD_OPC_Decode, + 175, + 14, + 30, // Opcode: MDE + /* 564 */ MCD_OPC_FilterValue, + 125, + 4, + 0, + 0, // Skip to: 573 + /* 569 */ MCD_OPC_Decode, + 218, + 9, + 32, // Opcode: DE + /* 573 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 582 + /* 578 */ MCD_OPC_Decode, + 180, + 4, + 32, // Opcode: AU + /* 582 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 591 + /* 587 */ MCD_OPC_Decode, + 136, + 18, + 32, // Opcode: SU + /* 591 */ MCD_OPC_FilterValue, + 128, + 1, + 11, + 0, + 0, // Skip to: 608 + /* 597 */ MCD_OPC_CheckField, + 16, + 8, + 0, + 207, + 39, + 0, // Skip to: 10795 + /* 604 */ MCD_OPC_Decode, + 143, + 17, + 33, // Opcode: SSM + /* 608 */ MCD_OPC_FilterValue, + 130, + 1, + 11, + 0, + 0, // Skip to: 625 + /* 614 */ MCD_OPC_CheckField, + 16, + 8, + 0, + 190, + 39, + 0, // Skip to: 10795 + /* 621 */ MCD_OPC_Decode, + 230, + 13, + 33, // Opcode: LPSW + /* 625 */ MCD_OPC_FilterValue, + 131, + 1, + 4, + 0, + 0, // Skip to: 635 + /* 631 */ MCD_OPC_Decode, + 223, + 9, + 34, // Opcode: DIAG + /* 635 */ MCD_OPC_FilterValue, + 132, + 1, + 4, + 0, + 0, // Skip to: 645 + /* 641 */ MCD_OPC_Decode, + 151, + 5, + 35, // Opcode: BRXH + /* 645 */ MCD_OPC_FilterValue, + 133, + 1, + 4, + 0, + 0, // Skip to: 655 + /* 651 */ MCD_OPC_Decode, + 153, + 5, + 35, // Opcode: BRXLE + /* 655 */ MCD_OPC_FilterValue, + 134, + 1, + 4, + 0, + 0, // Skip to: 665 + /* 661 */ MCD_OPC_Decode, + 158, + 5, + 36, // Opcode: BXH + /* 665 */ MCD_OPC_FilterValue, + 135, + 1, + 4, + 0, + 0, // Skip to: 675 + /* 671 */ MCD_OPC_Decode, + 160, + 5, + 36, // Opcode: BXLE + /* 675 */ MCD_OPC_FilterValue, + 136, + 1, + 11, + 0, + 0, // Skip to: 692 + /* 681 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 123, + 39, + 0, // Skip to: 10795 + /* 688 */ MCD_OPC_Decode, + 128, + 17, + 37, // Opcode: SRL + /* 692 */ MCD_OPC_FilterValue, + 137, + 1, + 11, + 0, + 0, // Skip to: 709 + /* 698 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 106, + 39, + 0, // Skip to: 10795 + /* 705 */ MCD_OPC_Decode, + 224, + 16, + 37, // Opcode: SLL + /* 709 */ MCD_OPC_FilterValue, + 138, + 1, + 11, + 0, + 0, // Skip to: 726 + /* 715 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 89, + 39, + 0, // Skip to: 10795 + /* 722 */ MCD_OPC_Decode, + 249, + 16, + 37, // Opcode: SRA + /* 726 */ MCD_OPC_FilterValue, + 139, + 1, + 11, + 0, + 0, // Skip to: 743 + /* 732 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 72, + 39, + 0, // Skip to: 10795 + /* 739 */ MCD_OPC_Decode, + 205, + 16, + 37, // Opcode: SLA + /* 743 */ MCD_OPC_FilterValue, + 140, + 1, + 11, + 0, + 0, // Skip to: 760 + /* 749 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 55, + 39, + 0, // Skip to: 10795 + /* 756 */ MCD_OPC_Decode, + 253, + 16, + 38, // Opcode: SRDL + /* 760 */ MCD_OPC_FilterValue, + 141, + 1, + 11, + 0, + 0, // Skip to: 777 + /* 766 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 38, + 39, + 0, // Skip to: 10795 + /* 773 */ MCD_OPC_Decode, + 213, + 16, + 38, // Opcode: SLDL + /* 777 */ MCD_OPC_FilterValue, + 142, + 1, + 11, + 0, + 0, // Skip to: 794 + /* 783 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 21, + 39, + 0, // Skip to: 10795 + /* 790 */ MCD_OPC_Decode, + 252, + 16, + 38, // Opcode: SRDA + /* 794 */ MCD_OPC_FilterValue, + 143, + 1, + 11, + 0, + 0, // Skip to: 811 + /* 800 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 4, + 39, + 0, // Skip to: 10795 + /* 807 */ MCD_OPC_Decode, + 212, + 16, + 38, // Opcode: SLDA + /* 811 */ MCD_OPC_FilterValue, + 144, + 1, + 4, + 0, + 0, // Skip to: 821 + /* 817 */ MCD_OPC_Decode, + 179, + 17, + 34, // Opcode: STM + /* 821 */ MCD_OPC_FilterValue, + 145, + 1, + 4, + 0, + 0, // Skip to: 831 + /* 827 */ MCD_OPC_Decode, + 166, + 18, + 39, // Opcode: TM + /* 831 */ MCD_OPC_FilterValue, + 146, + 1, + 4, + 0, + 0, // Skip to: 841 + /* 837 */ MCD_OPC_Decode, + 240, + 14, + 39, // Opcode: MVI + /* 841 */ MCD_OPC_FilterValue, + 147, + 1, + 11, + 0, + 0, // Skip to: 858 + /* 847 */ MCD_OPC_CheckField, + 16, + 8, + 0, + 213, + 38, + 0, // Skip to: 10795 + /* 854 */ MCD_OPC_Decode, + 195, + 18, + 33, // Opcode: TS + /* 858 */ MCD_OPC_FilterValue, + 148, + 1, + 4, + 0, + 0, // Skip to: 868 + /* 864 */ MCD_OPC_Decode, + 140, + 15, + 39, // Opcode: NI + /* 868 */ MCD_OPC_FilterValue, + 149, + 1, + 4, + 0, + 0, // Skip to: 878 + /* 874 */ MCD_OPC_Decode, + 135, + 8, + 39, // Opcode: CLI + /* 878 */ MCD_OPC_FilterValue, + 150, + 1, + 4, + 0, + 0, // Skip to: 888 + /* 884 */ MCD_OPC_Decode, + 168, + 15, + 39, // Opcode: OI + /* 888 */ MCD_OPC_FilterValue, + 151, + 1, + 4, + 0, + 0, // Skip to: 898 + /* 894 */ MCD_OPC_Decode, + 170, + 24, + 39, // Opcode: XI + /* 898 */ MCD_OPC_FilterValue, + 152, + 1, + 4, + 0, + 0, // Skip to: 908 + /* 904 */ MCD_OPC_Decode, + 130, + 12, + 34, // Opcode: LM + /* 908 */ MCD_OPC_FilterValue, + 153, + 1, + 4, + 0, + 0, // Skip to: 918 + /* 914 */ MCD_OPC_Decode, + 176, + 18, + 34, // Opcode: TRACE + /* 918 */ MCD_OPC_FilterValue, + 154, + 1, + 4, + 0, + 0, // Skip to: 928 + /* 924 */ MCD_OPC_Decode, + 148, + 11, + 40, // Opcode: LAM + /* 928 */ MCD_OPC_FilterValue, + 155, + 1, + 4, + 0, + 0, // Skip to: 938 + /* 934 */ MCD_OPC_Decode, + 145, + 17, + 40, // Opcode: STAM + /* 938 */ MCD_OPC_FilterValue, + 165, + 1, + 147, + 0, + 0, // Skip to: 1091 + /* 944 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 947 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 956 + /* 952 */ MCD_OPC_Decode, + 165, + 10, + 41, // Opcode: IIHH + /* 956 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 965 + /* 961 */ MCD_OPC_Decode, + 166, + 10, + 41, // Opcode: IIHL + /* 965 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 974 + /* 970 */ MCD_OPC_Decode, + 168, + 10, + 42, // Opcode: IILH + /* 974 */ MCD_OPC_FilterValue, + 3, + 4, + 0, + 0, // Skip to: 983 + /* 979 */ MCD_OPC_Decode, + 169, + 10, + 42, // Opcode: IILL + /* 983 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 992 + /* 988 */ MCD_OPC_Decode, + 143, + 15, + 41, // Opcode: NIHH + /* 992 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 1001 + /* 997 */ MCD_OPC_Decode, + 144, + 15, + 41, // Opcode: NIHL + /* 1001 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 1010 + /* 1006 */ MCD_OPC_Decode, + 146, + 15, + 42, // Opcode: NILH + /* 1010 */ MCD_OPC_FilterValue, + 7, + 4, + 0, + 0, // Skip to: 1019 + /* 1015 */ MCD_OPC_Decode, + 147, + 15, + 42, // Opcode: NILL + /* 1019 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 1028 + /* 1024 */ MCD_OPC_Decode, + 170, + 15, + 41, // Opcode: OIHH + /* 1028 */ MCD_OPC_FilterValue, + 9, + 4, + 0, + 0, // Skip to: 1037 + /* 1033 */ MCD_OPC_Decode, + 171, + 15, + 41, // Opcode: OIHL + /* 1037 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 1046 + /* 1042 */ MCD_OPC_Decode, + 173, + 15, + 42, // Opcode: OILH + /* 1046 */ MCD_OPC_FilterValue, + 11, + 4, + 0, + 0, // Skip to: 1055 + /* 1051 */ MCD_OPC_Decode, + 174, + 15, + 42, // Opcode: OILL + /* 1055 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 1064 + /* 1060 */ MCD_OPC_Decode, + 252, + 11, + 43, // Opcode: LLIHH + /* 1064 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 1073 + /* 1069 */ MCD_OPC_Decode, + 253, + 11, + 43, // Opcode: LLIHL + /* 1073 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 1082 + /* 1078 */ MCD_OPC_Decode, + 255, + 11, + 43, // Opcode: LLILH + /* 1082 */ MCD_OPC_FilterValue, + 15, + 236, + 37, + 0, // Skip to: 10795 + /* 1087 */ MCD_OPC_Decode, + 128, + 12, + 43, // Opcode: LLILL + /* 1091 */ MCD_OPC_FilterValue, + 167, + 1, + 29, + 1, + 0, // Skip to: 1382 + /* 1097 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 1100 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1109 + /* 1105 */ MCD_OPC_Decode, + 169, + 18, + 44, // Opcode: TMLH + /* 1109 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1118 + /* 1114 */ MCD_OPC_Decode, + 170, + 18, + 44, // Opcode: TMLL + /* 1118 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 1127 + /* 1123 */ MCD_OPC_Decode, + 167, + 18, + 45, // Opcode: TMHH + /* 1127 */ MCD_OPC_FilterValue, + 3, + 4, + 0, + 0, // Skip to: 1136 + /* 1132 */ MCD_OPC_Decode, + 168, + 18, + 45, // Opcode: TMHL + /* 1136 */ MCD_OPC_FilterValue, + 4, + 142, + 0, + 0, // Skip to: 1283 + /* 1141 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 1144 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1153 + /* 1149 */ MCD_OPC_Decode, + 227, + 10, + 46, // Opcode: JAsmO + /* 1153 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 1162 + /* 1158 */ MCD_OPC_Decode, + 211, + 10, + 46, // Opcode: JAsmH + /* 1162 */ MCD_OPC_FilterValue, + 3, + 4, + 0, + 0, // Skip to: 1171 + /* 1167 */ MCD_OPC_Decode, + 221, + 10, + 46, // Opcode: JAsmNLE + /* 1171 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 1180 + /* 1176 */ MCD_OPC_Decode, + 213, + 10, + 46, // Opcode: JAsmL + /* 1180 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 1189 + /* 1185 */ MCD_OPC_Decode, + 219, + 10, + 46, // Opcode: JAsmNHE + /* 1189 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 1198 + /* 1194 */ MCD_OPC_Decode, + 215, + 10, + 46, // Opcode: JAsmLH + /* 1198 */ MCD_OPC_FilterValue, + 7, + 4, + 0, + 0, // Skip to: 1207 + /* 1203 */ MCD_OPC_Decode, + 217, + 10, + 46, // Opcode: JAsmNE + /* 1207 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 1216 + /* 1212 */ MCD_OPC_Decode, + 210, + 10, + 46, // Opcode: JAsmE + /* 1216 */ MCD_OPC_FilterValue, + 9, + 4, + 0, + 0, // Skip to: 1225 + /* 1221 */ MCD_OPC_Decode, + 222, + 10, + 46, // Opcode: JAsmNLH + /* 1225 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 1234 + /* 1230 */ MCD_OPC_Decode, + 212, + 10, + 46, // Opcode: JAsmHE + /* 1234 */ MCD_OPC_FilterValue, + 11, + 4, + 0, + 0, // Skip to: 1243 + /* 1239 */ MCD_OPC_Decode, + 220, + 10, + 46, // Opcode: JAsmNL + /* 1243 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 1252 + /* 1248 */ MCD_OPC_Decode, + 214, + 10, + 46, // Opcode: JAsmLE + /* 1252 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 1261 + /* 1257 */ MCD_OPC_Decode, + 218, + 10, + 46, // Opcode: JAsmNH + /* 1261 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 1270 + /* 1266 */ MCD_OPC_Decode, + 224, + 10, + 46, // Opcode: JAsmNO + /* 1270 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 1279 + /* 1275 */ MCD_OPC_Decode, + 209, + 10, + 46, // Opcode: J + /* 1279 */ MCD_OPC_Decode, + 145, + 5, + 47, // Opcode: BRCAsm + /* 1283 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 1292 + /* 1288 */ MCD_OPC_Decode, + 250, + 4, + 48, // Opcode: BRAS + /* 1292 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 1301 + /* 1297 */ MCD_OPC_Decode, + 148, + 5, + 49, // Opcode: BRCT + /* 1301 */ MCD_OPC_FilterValue, + 7, + 4, + 0, + 0, // Skip to: 1310 + /* 1306 */ MCD_OPC_Decode, + 149, + 5, + 50, // Opcode: BRCTG + /* 1310 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 1319 + /* 1315 */ MCD_OPC_Decode, + 227, + 11, + 51, // Opcode: LHI + /* 1319 */ MCD_OPC_FilterValue, + 9, + 4, + 0, + 0, // Skip to: 1328 + /* 1324 */ MCD_OPC_Decode, + 219, + 11, + 52, // Opcode: LGHI + /* 1328 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 1337 + /* 1333 */ MCD_OPC_Decode, + 149, + 4, + 53, // Opcode: AHI + /* 1337 */ MCD_OPC_FilterValue, + 11, + 4, + 0, + 0, // Skip to: 1346 + /* 1342 */ MCD_OPC_Decode, + 141, + 4, + 54, // Opcode: AGHI + /* 1346 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 1355 + /* 1351 */ MCD_OPC_Decode, + 194, + 14, + 53, // Opcode: MHI + /* 1355 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 1364 + /* 1360 */ MCD_OPC_Decode, + 191, + 14, + 54, // Opcode: MGHI + /* 1364 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 1373 + /* 1369 */ MCD_OPC_Decode, + 199, + 6, + 51, // Opcode: CHI + /* 1373 */ MCD_OPC_FilterValue, + 15, + 201, + 36, + 0, // Skip to: 10795 + /* 1378 */ MCD_OPC_Decode, + 229, + 5, + 52, // Opcode: CGHI + /* 1382 */ MCD_OPC_FilterValue, + 168, + 1, + 4, + 0, + 0, // Skip to: 1392 + /* 1388 */ MCD_OPC_Decode, + 230, + 14, + 55, // Opcode: MVCLE + /* 1392 */ MCD_OPC_FilterValue, + 169, + 1, + 4, + 0, + 0, // Skip to: 1402 + /* 1398 */ MCD_OPC_Decode, + 251, + 6, + 55, // Opcode: CLCLE + /* 1402 */ MCD_OPC_FilterValue, + 172, + 1, + 4, + 0, + 0, // Skip to: 1412 + /* 1408 */ MCD_OPC_Decode, + 183, + 17, + 39, // Opcode: STNSM + /* 1412 */ MCD_OPC_FilterValue, + 173, + 1, + 4, + 0, + 0, // Skip to: 1422 + /* 1418 */ MCD_OPC_Decode, + 250, + 17, + 39, // Opcode: STOSM + /* 1422 */ MCD_OPC_FilterValue, + 174, + 1, + 4, + 0, + 0, // Skip to: 1432 + /* 1428 */ MCD_OPC_Decode, + 203, + 16, + 56, // Opcode: SIGP + /* 1432 */ MCD_OPC_FilterValue, + 175, + 1, + 4, + 0, + 0, // Skip to: 1442 + /* 1438 */ MCD_OPC_Decode, + 171, + 14, + 39, // Opcode: MC + /* 1442 */ MCD_OPC_FilterValue, + 177, + 1, + 4, + 0, + 0, // Skip to: 1452 + /* 1448 */ MCD_OPC_Decode, + 237, + 13, + 21, // Opcode: LRA + /* 1452 */ MCD_OPC_FilterValue, + 178, + 1, + 34, + 6, + 0, // Skip to: 3028 + /* 1458 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 1461 */ MCD_OPC_FilterValue, + 0, + 9, + 0, + 0, // Skip to: 1475 + /* 1466 */ MCD_OPC_CheckPredicate, + 0, + 108, + 36, + 0, // Skip to: 10795 + /* 1471 */ MCD_OPC_Decode, + 161, + 11, + 33, // Opcode: LBEAR + /* 1475 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 1489 + /* 1480 */ MCD_OPC_CheckPredicate, + 0, + 94, + 36, + 0, // Skip to: 10795 + /* 1485 */ MCD_OPC_Decode, + 148, + 17, + 33, // Opcode: STBEAR + /* 1489 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 1498 + /* 1494 */ MCD_OPC_Decode, + 178, + 17, + 33, // Opcode: STIDP + /* 1498 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 1507 + /* 1503 */ MCD_OPC_Decode, + 238, + 15, + 33, // Opcode: SCK + /* 1507 */ MCD_OPC_FilterValue, + 5, + 4, + 0, + 0, // Skip to: 1516 + /* 1512 */ MCD_OPC_Decode, + 151, + 17, + 33, // Opcode: STCK + /* 1516 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 1525 + /* 1521 */ MCD_OPC_Decode, + 239, + 15, + 33, // Opcode: SCKC + /* 1525 */ MCD_OPC_FilterValue, + 7, + 4, + 0, + 0, // Skip to: 1534 + /* 1530 */ MCD_OPC_Decode, + 152, + 17, + 33, // Opcode: STCKC + /* 1534 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 1543 + /* 1539 */ MCD_OPC_Decode, + 236, + 16, + 33, // Opcode: SPT + /* 1543 */ MCD_OPC_FilterValue, + 9, + 4, + 0, + 0, // Skip to: 1552 + /* 1548 */ MCD_OPC_Decode, + 252, + 17, + 33, // Opcode: STPT + /* 1552 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 1561 + /* 1557 */ MCD_OPC_Decode, + 234, + 16, + 33, // Opcode: SPKA + /* 1561 */ MCD_OPC_FilterValue, + 11, + 11, + 0, + 0, // Skip to: 1577 + /* 1566 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 6, + 36, + 0, // Skip to: 10795 + /* 1573 */ MCD_OPC_Decode, + 170, + 10, + 0, // Opcode: IPK + /* 1577 */ MCD_OPC_FilterValue, + 13, + 11, + 0, + 0, // Skip to: 1593 + /* 1582 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 246, + 35, + 0, // Skip to: 10795 + /* 1589 */ MCD_OPC_Decode, + 203, + 15, + 0, // Opcode: PTLB + /* 1593 */ MCD_OPC_FilterValue, + 16, + 4, + 0, + 0, // Skip to: 1602 + /* 1598 */ MCD_OPC_Decode, + 237, + 16, + 33, // Opcode: SPX + /* 1602 */ MCD_OPC_FilterValue, + 17, + 4, + 0, + 0, // Skip to: 1611 + /* 1607 */ MCD_OPC_Decode, + 253, + 17, + 33, // Opcode: STPX + /* 1611 */ MCD_OPC_FilterValue, + 18, + 4, + 0, + 0, // Skip to: 1620 + /* 1616 */ MCD_OPC_Decode, + 147, + 17, + 33, // Opcode: STAP + /* 1620 */ MCD_OPC_FilterValue, + 20, + 4, + 0, + 0, // Skip to: 1629 + /* 1625 */ MCD_OPC_Decode, + 201, + 16, + 33, // Opcode: SIE + /* 1629 */ MCD_OPC_FilterValue, + 24, + 4, + 0, + 0, // Skip to: 1638 + /* 1634 */ MCD_OPC_Decode, + 181, + 15, + 33, // Opcode: PC + /* 1638 */ MCD_OPC_FilterValue, + 25, + 4, + 0, + 0, // Skip to: 1647 + /* 1643 */ MCD_OPC_Decode, + 229, + 15, + 33, // Opcode: SAC + /* 1647 */ MCD_OPC_FilterValue, + 26, + 4, + 0, + 0, // Skip to: 1656 + /* 1652 */ MCD_OPC_Decode, + 202, + 5, + 33, // Opcode: CFC + /* 1656 */ MCD_OPC_FilterValue, + 33, + 26, + 0, + 0, // Skip to: 1687 + /* 1661 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 1672 + /* 1668 */ MCD_OPC_Decode, + 174, + 10, + 57, // Opcode: IPTEOptOpt + /* 1672 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 1683 + /* 1679 */ MCD_OPC_Decode, + 173, + 10, + 58, // Opcode: IPTEOpt + /* 1683 */ MCD_OPC_Decode, + 172, + 10, + 59, // Opcode: IPTE + /* 1687 */ MCD_OPC_FilterValue, + 34, + 18, + 0, + 0, // Skip to: 1710 + /* 1692 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 136, + 35, + 0, // Skip to: 10795 + /* 1699 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 129, + 35, + 0, // Skip to: 10795 + /* 1706 */ MCD_OPC_Decode, + 171, + 10, + 1, // Opcode: IPM + /* 1710 */ MCD_OPC_FilterValue, + 35, + 11, + 0, + 0, // Skip to: 1726 + /* 1715 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 113, + 35, + 0, // Skip to: 10795 + /* 1722 */ MCD_OPC_Decode, + 177, + 10, + 3, // Opcode: IVSK + /* 1726 */ MCD_OPC_FilterValue, + 36, + 18, + 0, + 0, // Skip to: 1749 + /* 1731 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 97, + 35, + 0, // Skip to: 10795 + /* 1738 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 90, + 35, + 0, // Skip to: 10795 + /* 1745 */ MCD_OPC_Decode, + 152, + 10, + 1, // Opcode: IAC + /* 1749 */ MCD_OPC_FilterValue, + 37, + 18, + 0, + 0, // Skip to: 1772 + /* 1754 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 74, + 35, + 0, // Skip to: 10795 + /* 1761 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 67, + 35, + 0, // Skip to: 10795 + /* 1768 */ MCD_OPC_Decode, + 139, + 17, + 1, // Opcode: SSAR + /* 1772 */ MCD_OPC_FilterValue, + 38, + 18, + 0, + 0, // Skip to: 1795 + /* 1777 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 51, + 35, + 0, // Skip to: 10795 + /* 1784 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 44, + 35, + 0, // Skip to: 10795 + /* 1791 */ MCD_OPC_Decode, + 251, + 9, + 1, // Opcode: EPAR + /* 1795 */ MCD_OPC_FilterValue, + 39, + 18, + 0, + 0, // Skip to: 1818 + /* 1800 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 28, + 35, + 0, // Skip to: 10795 + /* 1807 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 21, + 35, + 0, // Skip to: 10795 + /* 1814 */ MCD_OPC_Decode, + 129, + 10, + 1, // Opcode: ESAR + /* 1818 */ MCD_OPC_FilterValue, + 40, + 11, + 0, + 0, // Skip to: 1834 + /* 1823 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 5, + 35, + 0, // Skip to: 10795 + /* 1830 */ MCD_OPC_Decode, + 199, + 15, + 60, // Opcode: PT + /* 1834 */ MCD_OPC_FilterValue, + 41, + 11, + 0, + 0, // Skip to: 1850 + /* 1839 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 245, + 34, + 0, // Skip to: 10795 + /* 1846 */ MCD_OPC_Decode, + 176, + 10, + 3, // Opcode: ISKE + /* 1850 */ MCD_OPC_FilterValue, + 42, + 11, + 0, + 0, // Skip to: 1866 + /* 1855 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 229, + 34, + 0, // Skip to: 10795 + /* 1862 */ MCD_OPC_Decode, + 222, + 15, + 60, // Opcode: RRBE + /* 1866 */ MCD_OPC_FilterValue, + 43, + 23, + 0, + 0, // Skip to: 1894 + /* 1871 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 1874 */ MCD_OPC_FilterValue, + 0, + 212, + 34, + 0, // Skip to: 10795 + /* 1879 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 1890 + /* 1886 */ MCD_OPC_Decode, + 142, + 17, + 60, // Opcode: SSKEOpt + /* 1890 */ MCD_OPC_Decode, + 141, + 17, + 61, // Opcode: SSKE + /* 1894 */ MCD_OPC_FilterValue, + 44, + 11, + 0, + 0, // Skip to: 1910 + /* 1899 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 185, + 34, + 0, // Skip to: 10795 + /* 1906 */ MCD_OPC_Decode, + 149, + 18, + 62, // Opcode: TB + /* 1910 */ MCD_OPC_FilterValue, + 45, + 11, + 0, + 0, // Skip to: 1926 + /* 1915 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 169, + 34, + 0, // Skip to: 10795 + /* 1922 */ MCD_OPC_Decode, + 237, + 9, + 13, // Opcode: DXR + /* 1926 */ MCD_OPC_FilterValue, + 46, + 11, + 0, + 0, // Skip to: 1942 + /* 1931 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 153, + 34, + 0, // Skip to: 10795 + /* 1938 */ MCD_OPC_Decode, + 188, + 15, + 62, // Opcode: PGIN + /* 1942 */ MCD_OPC_FilterValue, + 47, + 11, + 0, + 0, // Skip to: 1958 + /* 1947 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 137, + 34, + 0, // Skip to: 10795 + /* 1954 */ MCD_OPC_Decode, + 189, + 15, + 62, // Opcode: PGOUT + /* 1958 */ MCD_OPC_FilterValue, + 48, + 11, + 0, + 0, // Skip to: 1974 + /* 1963 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 121, + 34, + 0, // Skip to: 10795 + /* 1970 */ MCD_OPC_Decode, + 157, + 9, + 0, // Opcode: CSCH + /* 1974 */ MCD_OPC_FilterValue, + 49, + 11, + 0, + 0, // Skip to: 1990 + /* 1979 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 105, + 34, + 0, // Skip to: 10795 + /* 1986 */ MCD_OPC_Decode, + 151, + 10, + 0, // Opcode: HSCH + /* 1990 */ MCD_OPC_FilterValue, + 50, + 4, + 0, + 0, // Skip to: 1999 + /* 1995 */ MCD_OPC_Decode, + 204, + 14, + 33, // Opcode: MSCH + /* 1999 */ MCD_OPC_FilterValue, + 51, + 4, + 0, + 0, // Skip to: 2008 + /* 2004 */ MCD_OPC_Decode, + 140, + 17, + 33, // Opcode: SSCH + /* 2008 */ MCD_OPC_FilterValue, + 52, + 4, + 0, + 0, // Skip to: 2017 + /* 2013 */ MCD_OPC_Decode, + 131, + 18, + 33, // Opcode: STSCH + /* 2017 */ MCD_OPC_FilterValue, + 53, + 4, + 0, + 0, // Skip to: 2026 + /* 2022 */ MCD_OPC_Decode, + 196, + 18, + 33, // Opcode: TSCH + /* 2026 */ MCD_OPC_FilterValue, + 54, + 4, + 0, + 0, // Skip to: 2035 + /* 2031 */ MCD_OPC_Decode, + 173, + 18, + 33, // Opcode: TPI + /* 2035 */ MCD_OPC_FilterValue, + 55, + 11, + 0, + 0, // Skip to: 2051 + /* 2040 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 44, + 34, + 0, // Skip to: 10795 + /* 2047 */ MCD_OPC_Decode, + 231, + 15, + 0, // Opcode: SAL + /* 2051 */ MCD_OPC_FilterValue, + 56, + 11, + 0, + 0, // Skip to: 2067 + /* 2056 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 28, + 34, + 0, // Skip to: 10795 + /* 2063 */ MCD_OPC_Decode, + 226, + 15, + 0, // Opcode: RSCH + /* 2067 */ MCD_OPC_FilterValue, + 57, + 4, + 0, + 0, // Skip to: 2076 + /* 2072 */ MCD_OPC_Decode, + 159, + 17, + 33, // Opcode: STCRW + /* 2076 */ MCD_OPC_FilterValue, + 58, + 4, + 0, + 0, // Skip to: 2085 + /* 2081 */ MCD_OPC_Decode, + 158, + 17, + 33, // Opcode: STCPS + /* 2085 */ MCD_OPC_FilterValue, + 59, + 11, + 0, + 0, // Skip to: 2101 + /* 2090 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 250, + 33, + 0, // Skip to: 10795 + /* 2097 */ MCD_OPC_Decode, + 209, + 15, + 0, // Opcode: RCHP + /* 2101 */ MCD_OPC_FilterValue, + 60, + 11, + 0, + 0, // Skip to: 2117 + /* 2106 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 234, + 33, + 0, // Skip to: 10795 + /* 2113 */ MCD_OPC_Decode, + 237, + 15, + 0, // Opcode: SCHM + /* 2117 */ MCD_OPC_FilterValue, + 64, + 11, + 0, + 0, // Skip to: 2133 + /* 2122 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 218, + 33, + 0, // Skip to: 10795 + /* 2129 */ MCD_OPC_Decode, + 190, + 4, + 62, // Opcode: BAKR + /* 2133 */ MCD_OPC_FilterValue, + 65, + 11, + 0, + 0, // Skip to: 2149 + /* 2138 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 202, + 33, + 0, // Skip to: 10795 + /* 2145 */ MCD_OPC_Decode, + 247, + 6, + 63, // Opcode: CKSM + /* 2149 */ MCD_OPC_FilterValue, + 68, + 11, + 0, + 0, // Skip to: 2165 + /* 2154 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 186, + 33, + 0, // Skip to: 10795 + /* 2161 */ MCD_OPC_Decode, + 241, + 16, + 11, // Opcode: SQDR + /* 2165 */ MCD_OPC_FilterValue, + 69, + 11, + 0, + 0, // Skip to: 2181 + /* 2170 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 170, + 33, + 0, // Skip to: 10795 + /* 2177 */ MCD_OPC_Decode, + 245, + 16, + 16, // Opcode: SQER + /* 2181 */ MCD_OPC_FilterValue, + 70, + 11, + 0, + 0, // Skip to: 2197 + /* 2186 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 154, + 33, + 0, // Skip to: 10795 + /* 2193 */ MCD_OPC_Decode, + 133, + 18, + 60, // Opcode: STURA + /* 2197 */ MCD_OPC_FilterValue, + 71, + 18, + 0, + 0, // Skip to: 2220 + /* 2202 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 138, + 33, + 0, // Skip to: 10795 + /* 2209 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 131, + 33, + 0, // Skip to: 10795 + /* 2216 */ MCD_OPC_Decode, + 223, + 14, + 64, // Opcode: MSTA + /* 2220 */ MCD_OPC_FilterValue, + 72, + 11, + 0, + 0, // Skip to: 2236 + /* 2225 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 115, + 33, + 0, // Skip to: 10795 + /* 2232 */ MCD_OPC_Decode, + 180, + 15, + 0, // Opcode: PALB + /* 2236 */ MCD_OPC_FilterValue, + 73, + 11, + 0, + 0, // Skip to: 2252 + /* 2241 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 99, + 33, + 0, // Skip to: 10795 + /* 2248 */ MCD_OPC_Decode, + 254, + 9, + 8, // Opcode: EREG + /* 2252 */ MCD_OPC_FilterValue, + 74, + 11, + 0, + 0, // Skip to: 2268 + /* 2257 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 83, + 33, + 0, // Skip to: 10795 + /* 2264 */ MCD_OPC_Decode, + 132, + 10, + 65, // Opcode: ESTA + /* 2268 */ MCD_OPC_FilterValue, + 75, + 11, + 0, + 0, // Skip to: 2284 + /* 2273 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 67, + 33, + 0, // Skip to: 10795 + /* 2280 */ MCD_OPC_Decode, + 138, + 14, + 60, // Opcode: LURA + /* 2284 */ MCD_OPC_FilterValue, + 76, + 11, + 0, + 0, // Skip to: 2300 + /* 2289 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 51, + 33, + 0, // Skip to: 10795 + /* 2296 */ MCD_OPC_Decode, + 148, + 18, + 66, // Opcode: TAR + /* 2300 */ MCD_OPC_FilterValue, + 77, + 11, + 0, + 0, // Skip to: 2316 + /* 2305 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 35, + 33, + 0, // Skip to: 10795 + /* 2312 */ MCD_OPC_Decode, + 237, + 8, + 67, // Opcode: CPYA + /* 2316 */ MCD_OPC_FilterValue, + 78, + 11, + 0, + 0, // Skip to: 2332 + /* 2321 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 19, + 33, + 0, // Skip to: 10795 + /* 2328 */ MCD_OPC_Decode, + 235, + 15, + 66, // Opcode: SAR + /* 2332 */ MCD_OPC_FilterValue, + 79, + 11, + 0, + 0, // Skip to: 2348 + /* 2337 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 3, + 33, + 0, // Skip to: 10795 + /* 2344 */ MCD_OPC_Decode, + 240, + 9, + 68, // Opcode: EAR + /* 2348 */ MCD_OPC_FilterValue, + 80, + 11, + 0, + 0, // Skip to: 2364 + /* 2353 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 243, + 32, + 0, // Skip to: 10795 + /* 2360 */ MCD_OPC_Decode, + 160, + 9, + 69, // Opcode: CSP + /* 2364 */ MCD_OPC_FilterValue, + 82, + 11, + 0, + 0, // Skip to: 2380 + /* 2369 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 227, + 32, + 0, // Skip to: 10795 + /* 2376 */ MCD_OPC_Decode, + 221, + 14, + 9, // Opcode: MSR + /* 2380 */ MCD_OPC_FilterValue, + 84, + 11, + 0, + 0, // Skip to: 2396 + /* 2385 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 211, + 32, + 0, // Skip to: 10795 + /* 2392 */ MCD_OPC_Decode, + 244, + 14, + 62, // Opcode: MVPG + /* 2396 */ MCD_OPC_FilterValue, + 85, + 11, + 0, + 0, // Skip to: 2412 + /* 2401 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 195, + 32, + 0, // Skip to: 10795 + /* 2408 */ MCD_OPC_Decode, + 245, + 14, + 70, // Opcode: MVST + /* 2412 */ MCD_OPC_FilterValue, + 87, + 11, + 0, + 0, // Skip to: 2428 + /* 2417 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 179, + 32, + 0, // Skip to: 10795 + /* 2424 */ MCD_OPC_Decode, + 176, + 9, + 7, // Opcode: CUSE + /* 2428 */ MCD_OPC_FilterValue, + 88, + 11, + 0, + 0, // Skip to: 2444 + /* 2433 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 163, + 32, + 0, // Skip to: 10795 + /* 2440 */ MCD_OPC_Decode, + 156, + 5, + 62, // Opcode: BSG + /* 2444 */ MCD_OPC_FilterValue, + 90, + 11, + 0, + 0, // Skip to: 2460 + /* 2449 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 147, + 32, + 0, // Skip to: 10795 + /* 2456 */ MCD_OPC_Decode, + 155, + 5, + 62, // Opcode: BSA + /* 2460 */ MCD_OPC_FilterValue, + 93, + 11, + 0, + 0, // Skip to: 2476 + /* 2465 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 131, + 32, + 0, // Skip to: 10795 + /* 2472 */ MCD_OPC_Decode, + 213, + 8, + 70, // Opcode: CLST + /* 2476 */ MCD_OPC_FilterValue, + 94, + 11, + 0, + 0, // Skip to: 2492 + /* 2481 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 115, + 32, + 0, // Skip to: 10795 + /* 2488 */ MCD_OPC_Decode, + 135, + 17, + 70, // Opcode: SRST + /* 2492 */ MCD_OPC_FilterValue, + 99, + 11, + 0, + 0, // Skip to: 2508 + /* 2497 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 99, + 32, + 0, // Skip to: 10795 + /* 2504 */ MCD_OPC_Decode, + 229, + 8, + 7, // Opcode: CMPSC + /* 2508 */ MCD_OPC_FilterValue, + 116, + 4, + 0, + 0, // Skip to: 2517 + /* 2513 */ MCD_OPC_Decode, + 202, + 16, + 33, // Opcode: SIGA + /* 2517 */ MCD_OPC_FilterValue, + 118, + 11, + 0, + 0, // Skip to: 2533 + /* 2522 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 74, + 32, + 0, // Skip to: 10795 + /* 2529 */ MCD_OPC_Decode, + 176, + 24, + 0, // Opcode: XSCH + /* 2533 */ MCD_OPC_FilterValue, + 119, + 4, + 0, + 0, // Skip to: 2542 + /* 2538 */ MCD_OPC_Decode, + 221, + 15, + 33, // Opcode: RP + /* 2542 */ MCD_OPC_FilterValue, + 120, + 4, + 0, + 0, // Skip to: 2551 + /* 2547 */ MCD_OPC_Decode, + 153, + 17, + 33, // Opcode: STCKE + /* 2551 */ MCD_OPC_FilterValue, + 121, + 4, + 0, + 0, // Skip to: 2560 + /* 2556 */ MCD_OPC_Decode, + 230, + 15, + 33, // Opcode: SACF + /* 2560 */ MCD_OPC_FilterValue, + 124, + 4, + 0, + 0, // Skip to: 2569 + /* 2565 */ MCD_OPC_Decode, + 154, + 17, + 33, // Opcode: STCKF + /* 2569 */ MCD_OPC_FilterValue, + 125, + 4, + 0, + 0, // Skip to: 2578 + /* 2574 */ MCD_OPC_Decode, + 132, + 18, + 33, // Opcode: STSI + /* 2578 */ MCD_OPC_FilterValue, + 128, + 1, + 4, + 0, + 0, // Skip to: 2588 + /* 2584 */ MCD_OPC_Decode, + 227, + 13, + 33, // Opcode: LPP + /* 2588 */ MCD_OPC_FilterValue, + 132, + 1, + 4, + 0, + 0, // Skip to: 2598 + /* 2594 */ MCD_OPC_Decode, + 165, + 11, + 33, // Opcode: LCCTL + /* 2598 */ MCD_OPC_FilterValue, + 133, + 1, + 4, + 0, + 0, // Skip to: 2608 + /* 2604 */ MCD_OPC_Decode, + 216, + 13, + 33, // Opcode: LPCTL + /* 2608 */ MCD_OPC_FilterValue, + 134, + 1, + 4, + 0, + 0, // Skip to: 2618 + /* 2614 */ MCD_OPC_Decode, + 208, + 15, + 33, // Opcode: QSI + /* 2618 */ MCD_OPC_FilterValue, + 135, + 1, + 4, + 0, + 0, // Skip to: 2628 + /* 2624 */ MCD_OPC_Decode, + 248, + 13, + 33, // Opcode: LSCTL + /* 2628 */ MCD_OPC_FilterValue, + 142, + 1, + 4, + 0, + 0, // Skip to: 2638 + /* 2634 */ MCD_OPC_Decode, + 206, + 15, + 33, // Opcode: QCTRI + /* 2638 */ MCD_OPC_FilterValue, + 143, + 1, + 9, + 0, + 0, // Skip to: 2653 + /* 2644 */ MCD_OPC_CheckPredicate, + 1, + 210, + 31, + 0, // Skip to: 10795 + /* 2649 */ MCD_OPC_Decode, + 207, + 15, + 33, // Opcode: QPACI + /* 2653 */ MCD_OPC_FilterValue, + 153, + 1, + 4, + 0, + 0, // Skip to: 2663 + /* 2659 */ MCD_OPC_Decode, + 131, + 17, + 71, // Opcode: SRNM + /* 2663 */ MCD_OPC_FilterValue, + 156, + 1, + 4, + 0, + 0, // Skip to: 2673 + /* 2669 */ MCD_OPC_Decode, + 170, + 17, + 33, // Opcode: STFPC + /* 2673 */ MCD_OPC_FilterValue, + 157, + 1, + 4, + 0, + 0, // Skip to: 2683 + /* 2679 */ MCD_OPC_Decode, + 207, + 11, + 33, // Opcode: LFPC + /* 2683 */ MCD_OPC_FilterValue, + 165, + 1, + 11, + 0, + 0, // Skip to: 2700 + /* 2689 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 163, + 31, + 0, // Skip to: 10795 + /* 2696 */ MCD_OPC_Decode, + 180, + 18, + 72, // Opcode: TRE + /* 2700 */ MCD_OPC_FilterValue, + 166, + 1, + 23, + 0, + 0, // Skip to: 2729 + /* 2706 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 2709 */ MCD_OPC_FilterValue, + 0, + 145, + 31, + 0, // Skip to: 10795 + /* 2714 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 2725 + /* 2721 */ MCD_OPC_Decode, + 170, + 9, + 7, // Opcode: CU21Opt + /* 2725 */ MCD_OPC_Decode, + 169, + 9, + 73, // Opcode: CU21 + /* 2729 */ MCD_OPC_FilterValue, + 167, + 1, + 23, + 0, + 0, // Skip to: 2758 + /* 2735 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 2738 */ MCD_OPC_FilterValue, + 0, + 116, + 31, + 0, // Skip to: 10795 + /* 2743 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 2754 + /* 2750 */ MCD_OPC_Decode, + 166, + 9, + 7, // Opcode: CU12Opt + /* 2754 */ MCD_OPC_Decode, + 165, + 9, + 73, // Opcode: CU12 + /* 2758 */ MCD_OPC_FilterValue, + 176, + 1, + 4, + 0, + 0, // Skip to: 2768 + /* 2764 */ MCD_OPC_Decode, + 169, + 17, + 33, // Opcode: STFLE + /* 2768 */ MCD_OPC_FilterValue, + 177, + 1, + 4, + 0, + 0, // Skip to: 2778 + /* 2774 */ MCD_OPC_Decode, + 168, + 17, + 33, // Opcode: STFL + /* 2778 */ MCD_OPC_FilterValue, + 178, + 1, + 4, + 0, + 0, // Skip to: 2788 + /* 2784 */ MCD_OPC_Decode, + 231, + 13, + 33, // Opcode: LPSWE + /* 2788 */ MCD_OPC_FilterValue, + 184, + 1, + 9, + 0, + 0, // Skip to: 2803 + /* 2794 */ MCD_OPC_CheckPredicate, + 2, + 60, + 31, + 0, // Skip to: 10795 + /* 2799 */ MCD_OPC_Decode, + 132, + 17, + 71, // Opcode: SRNMB + /* 2803 */ MCD_OPC_FilterValue, + 185, + 1, + 4, + 0, + 0, // Skip to: 2813 + /* 2809 */ MCD_OPC_Decode, + 133, + 17, + 71, // Opcode: SRNMT + /* 2813 */ MCD_OPC_FilterValue, + 189, + 1, + 4, + 0, + 0, // Skip to: 2823 + /* 2819 */ MCD_OPC_Decode, + 204, + 11, + 33, // Opcode: LFAS + /* 2823 */ MCD_OPC_FilterValue, + 224, + 1, + 11, + 0, + 0, // Skip to: 2840 + /* 2829 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 23, + 31, + 0, // Skip to: 10795 + /* 2836 */ MCD_OPC_Decode, + 236, + 15, + 62, // Opcode: SCCTR + /* 2840 */ MCD_OPC_FilterValue, + 225, + 1, + 11, + 0, + 0, // Skip to: 2857 + /* 2846 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 6, + 31, + 0, // Skip to: 10795 + /* 2853 */ MCD_OPC_Decode, + 233, + 16, + 62, // Opcode: SPCTR + /* 2857 */ MCD_OPC_FilterValue, + 228, + 1, + 11, + 0, + 0, // Skip to: 2874 + /* 2863 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 245, + 30, + 0, // Skip to: 10795 + /* 2870 */ MCD_OPC_Decode, + 242, + 9, + 62, // Opcode: ECCTR + /* 2874 */ MCD_OPC_FilterValue, + 229, + 1, + 11, + 0, + 0, // Skip to: 2891 + /* 2880 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 228, + 30, + 0, // Skip to: 10795 + /* 2887 */ MCD_OPC_Decode, + 252, + 9, + 62, // Opcode: EPCTR + /* 2891 */ MCD_OPC_FilterValue, + 232, + 1, + 16, + 0, + 0, // Skip to: 2913 + /* 2897 */ MCD_OPC_CheckPredicate, + 3, + 213, + 30, + 0, // Skip to: 10795 + /* 2902 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 206, + 30, + 0, // Skip to: 10795 + /* 2909 */ MCD_OPC_Decode, + 195, + 15, + 74, // Opcode: PPA + /* 2913 */ MCD_OPC_FilterValue, + 236, + 1, + 23, + 0, + 0, // Skip to: 2942 + /* 2919 */ MCD_OPC_CheckPredicate, + 4, + 191, + 30, + 0, // Skip to: 10795 + /* 2924 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 184, + 30, + 0, // Skip to: 10795 + /* 2931 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 177, + 30, + 0, // Skip to: 10795 + /* 2938 */ MCD_OPC_Decode, + 134, + 10, + 1, // Opcode: ETND + /* 2942 */ MCD_OPC_FilterValue, + 237, + 1, + 11, + 0, + 0, // Skip to: 2959 + /* 2948 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 160, + 30, + 0, // Skip to: 10795 + /* 2955 */ MCD_OPC_Decode, + 243, + 9, + 60, // Opcode: ECPGA + /* 2959 */ MCD_OPC_FilterValue, + 248, + 1, + 16, + 0, + 0, // Skip to: 2981 + /* 2965 */ MCD_OPC_CheckPredicate, + 4, + 145, + 30, + 0, // Skip to: 10795 + /* 2970 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 138, + 30, + 0, // Skip to: 10795 + /* 2977 */ MCD_OPC_Decode, + 163, + 18, + 0, // Opcode: TEND + /* 2981 */ MCD_OPC_FilterValue, + 250, + 1, + 16, + 0, + 0, // Skip to: 3003 + /* 2987 */ MCD_OPC_CheckPredicate, + 5, + 123, + 30, + 0, // Skip to: 10795 + /* 2992 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 116, + 30, + 0, // Skip to: 10795 + /* 2999 */ MCD_OPC_Decode, + 141, + 15, + 75, // Opcode: NIAI + /* 3003 */ MCD_OPC_FilterValue, + 252, + 1, + 9, + 0, + 0, // Skip to: 3018 + /* 3009 */ MCD_OPC_CheckPredicate, + 4, + 101, + 30, + 0, // Skip to: 10795 + /* 3014 */ MCD_OPC_Decode, + 146, + 18, + 33, // Opcode: TABORT + /* 3018 */ MCD_OPC_FilterValue, + 255, + 1, + 91, + 30, + 0, // Skip to: 10795 + /* 3024 */ MCD_OPC_Decode, + 179, + 18, + 33, // Opcode: TRAP4 + /* 3028 */ MCD_OPC_FilterValue, + 179, + 1, + 238, + 11, + 0, // Skip to: 6088 + /* 3034 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 3037 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 3053 + /* 3042 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 66, + 30, + 0, // Skip to: 10795 + /* 3049 */ MCD_OPC_Decode, + 223, + 13, + 16, // Opcode: LPEBR + /* 3053 */ MCD_OPC_FilterValue, + 1, + 11, + 0, + 0, // Skip to: 3069 + /* 3058 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 50, + 30, + 0, // Skip to: 10795 + /* 3065 */ MCD_OPC_Decode, + 139, + 12, + 16, // Opcode: LNEBR + /* 3069 */ MCD_OPC_FilterValue, + 2, + 11, + 0, + 0, // Skip to: 3085 + /* 3074 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 34, + 30, + 0, // Skip to: 10795 + /* 3081 */ MCD_OPC_Decode, + 254, + 13, + 16, // Opcode: LTEBR + /* 3085 */ MCD_OPC_FilterValue, + 3, + 11, + 0, + 0, // Skip to: 3101 + /* 3090 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 18, + 30, + 0, // Skip to: 10795 + /* 3097 */ MCD_OPC_Decode, + 170, + 11, + 16, // Opcode: LCEBR + /* 3101 */ MCD_OPC_FilterValue, + 4, + 11, + 0, + 0, // Skip to: 3117 + /* 3106 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 2, + 30, + 0, // Skip to: 10795 + /* 3113 */ MCD_OPC_Decode, + 183, + 11, + 76, // Opcode: LDEBR + /* 3117 */ MCD_OPC_FilterValue, + 5, + 11, + 0, + 0, // Skip to: 3133 + /* 3122 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 242, + 29, + 0, // Skip to: 10795 + /* 3129 */ MCD_OPC_Decode, + 142, + 14, + 77, // Opcode: LXDBR + /* 3133 */ MCD_OPC_FilterValue, + 6, + 11, + 0, + 0, // Skip to: 3149 + /* 3138 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 226, + 29, + 0, // Skip to: 10795 + /* 3145 */ MCD_OPC_Decode, + 147, + 14, + 78, // Opcode: LXEBR + /* 3149 */ MCD_OPC_FilterValue, + 7, + 11, + 0, + 0, // Skip to: 3165 + /* 3154 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 210, + 29, + 0, // Skip to: 10795 + /* 3161 */ MCD_OPC_Decode, + 250, + 14, + 14, // Opcode: MXDBR + /* 3165 */ MCD_OPC_FilterValue, + 8, + 11, + 0, + 0, // Skip to: 3181 + /* 3170 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 194, + 29, + 0, // Skip to: 10795 + /* 3177 */ MCD_OPC_Decode, + 128, + 11, + 16, // Opcode: KEBR + /* 3181 */ MCD_OPC_FilterValue, + 9, + 11, + 0, + 0, // Skip to: 3197 + /* 3186 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 178, + 29, + 0, // Skip to: 10795 + /* 3193 */ MCD_OPC_Decode, + 190, + 5, + 16, // Opcode: CEBR + /* 3197 */ MCD_OPC_FilterValue, + 10, + 11, + 0, + 0, // Skip to: 3213 + /* 3202 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 162, + 29, + 0, // Skip to: 10795 + /* 3209 */ MCD_OPC_Decode, + 133, + 4, + 18, // Opcode: AEBR + /* 3213 */ MCD_OPC_FilterValue, + 11, + 11, + 0, + 0, // Skip to: 3229 + /* 3218 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 146, + 29, + 0, // Skip to: 10795 + /* 3225 */ MCD_OPC_Decode, + 249, + 15, + 18, // Opcode: SEBR + /* 3229 */ MCD_OPC_FilterValue, + 12, + 11, + 0, + 0, // Skip to: 3245 + /* 3234 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 130, + 29, + 0, // Skip to: 10795 + /* 3241 */ MCD_OPC_Decode, + 177, + 14, + 19, // Opcode: MDEBR + /* 3245 */ MCD_OPC_FilterValue, + 13, + 11, + 0, + 0, // Skip to: 3261 + /* 3250 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 114, + 29, + 0, // Skip to: 10795 + /* 3257 */ MCD_OPC_Decode, + 220, + 9, + 18, // Opcode: DEBR + /* 3261 */ MCD_OPC_FilterValue, + 14, + 11, + 0, + 0, // Skip to: 3277 + /* 3266 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 98, + 29, + 0, // Skip to: 10795 + /* 3273 */ MCD_OPC_Decode, + 163, + 14, + 79, // Opcode: MAEBR + /* 3277 */ MCD_OPC_FilterValue, + 15, + 11, + 0, + 0, // Skip to: 3293 + /* 3282 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 82, + 29, + 0, // Skip to: 10795 + /* 3289 */ MCD_OPC_Decode, + 211, + 14, + 79, // Opcode: MSEBR + /* 3293 */ MCD_OPC_FilterValue, + 16, + 11, + 0, + 0, // Skip to: 3309 + /* 3298 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 66, + 29, + 0, // Skip to: 10795 + /* 3305 */ MCD_OPC_Decode, + 218, + 13, + 11, // Opcode: LPDBR + /* 3309 */ MCD_OPC_FilterValue, + 17, + 11, + 0, + 0, // Skip to: 3325 + /* 3314 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 50, + 29, + 0, // Skip to: 10795 + /* 3321 */ MCD_OPC_Decode, + 135, + 12, + 11, // Opcode: LNDBR + /* 3325 */ MCD_OPC_FilterValue, + 18, + 11, + 0, + 0, // Skip to: 3341 + /* 3330 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 34, + 29, + 0, // Skip to: 10795 + /* 3337 */ MCD_OPC_Decode, + 250, + 13, + 11, // Opcode: LTDBR + /* 3341 */ MCD_OPC_FilterValue, + 19, + 11, + 0, + 0, // Skip to: 3357 + /* 3346 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 18, + 29, + 0, // Skip to: 10795 + /* 3353 */ MCD_OPC_Decode, + 166, + 11, + 11, // Opcode: LCDBR + /* 3357 */ MCD_OPC_FilterValue, + 20, + 11, + 0, + 0, // Skip to: 3373 + /* 3362 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 2, + 29, + 0, // Skip to: 10795 + /* 3369 */ MCD_OPC_Decode, + 244, + 16, + 16, // Opcode: SQEBR + /* 3373 */ MCD_OPC_FilterValue, + 21, + 11, + 0, + 0, // Skip to: 3389 + /* 3378 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 242, + 28, + 0, // Skip to: 10795 + /* 3385 */ MCD_OPC_Decode, + 240, + 16, + 11, // Opcode: SQDBR + /* 3389 */ MCD_OPC_FilterValue, + 22, + 11, + 0, + 0, // Skip to: 3405 + /* 3394 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 226, + 28, + 0, // Skip to: 10795 + /* 3401 */ MCD_OPC_Decode, + 246, + 16, + 80, // Opcode: SQXBR + /* 3405 */ MCD_OPC_FilterValue, + 23, + 11, + 0, + 0, // Skip to: 3421 + /* 3410 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 210, + 28, + 0, // Skip to: 10795 + /* 3417 */ MCD_OPC_Decode, + 185, + 14, + 18, // Opcode: MEEBR + /* 3421 */ MCD_OPC_FilterValue, + 24, + 11, + 0, + 0, // Skip to: 3437 + /* 3426 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 194, + 28, + 0, // Skip to: 10795 + /* 3433 */ MCD_OPC_Decode, + 252, + 10, + 11, // Opcode: KDBR + /* 3437 */ MCD_OPC_FilterValue, + 25, + 11, + 0, + 0, // Skip to: 3453 + /* 3442 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 178, + 28, + 0, // Skip to: 10795 + /* 3449 */ MCD_OPC_Decode, + 165, + 5, + 11, // Opcode: CDBR + /* 3453 */ MCD_OPC_FilterValue, + 26, + 11, + 0, + 0, // Skip to: 3469 + /* 3458 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 162, + 28, + 0, // Skip to: 10795 + /* 3465 */ MCD_OPC_Decode, + 255, + 3, + 15, // Opcode: ADBR + /* 3469 */ MCD_OPC_FilterValue, + 27, + 11, + 0, + 0, // Skip to: 3485 + /* 3474 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 146, + 28, + 0, // Skip to: 10795 + /* 3481 */ MCD_OPC_Decode, + 243, + 15, + 15, // Opcode: SDBR + /* 3485 */ MCD_OPC_FilterValue, + 28, + 11, + 0, + 0, // Skip to: 3501 + /* 3490 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 130, + 28, + 0, // Skip to: 10795 + /* 3497 */ MCD_OPC_Decode, + 174, + 14, + 15, // Opcode: MDBR + /* 3501 */ MCD_OPC_FilterValue, + 29, + 11, + 0, + 0, // Skip to: 3517 + /* 3506 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 114, + 28, + 0, // Skip to: 10795 + /* 3513 */ MCD_OPC_Decode, + 214, + 9, + 15, // Opcode: DDBR + /* 3517 */ MCD_OPC_FilterValue, + 30, + 11, + 0, + 0, // Skip to: 3533 + /* 3522 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 98, + 28, + 0, // Skip to: 10795 + /* 3529 */ MCD_OPC_Decode, + 159, + 14, + 81, // Opcode: MADBR + /* 3533 */ MCD_OPC_FilterValue, + 31, + 11, + 0, + 0, // Skip to: 3549 + /* 3538 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 82, + 28, + 0, // Skip to: 10795 + /* 3545 */ MCD_OPC_Decode, + 207, + 14, + 81, // Opcode: MSDBR + /* 3549 */ MCD_OPC_FilterValue, + 36, + 11, + 0, + 0, // Skip to: 3565 + /* 3554 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 66, + 28, + 0, // Skip to: 10795 + /* 3561 */ MCD_OPC_Decode, + 184, + 11, + 76, // Opcode: LDER + /* 3565 */ MCD_OPC_FilterValue, + 37, + 11, + 0, + 0, // Skip to: 3581 + /* 3570 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 50, + 28, + 0, // Skip to: 10795 + /* 3577 */ MCD_OPC_Decode, + 143, + 14, + 77, // Opcode: LXDR + /* 3581 */ MCD_OPC_FilterValue, + 38, + 11, + 0, + 0, // Skip to: 3597 + /* 3586 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 34, + 28, + 0, // Skip to: 10795 + /* 3593 */ MCD_OPC_Decode, + 148, + 14, + 78, // Opcode: LXER + /* 3597 */ MCD_OPC_FilterValue, + 46, + 11, + 0, + 0, // Skip to: 3613 + /* 3602 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 18, + 28, + 0, // Skip to: 10795 + /* 3609 */ MCD_OPC_Decode, + 164, + 14, + 79, // Opcode: MAER + /* 3613 */ MCD_OPC_FilterValue, + 47, + 11, + 0, + 0, // Skip to: 3629 + /* 3618 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 2, + 28, + 0, // Skip to: 10795 + /* 3625 */ MCD_OPC_Decode, + 212, + 14, + 79, // Opcode: MSER + /* 3629 */ MCD_OPC_FilterValue, + 54, + 11, + 0, + 0, // Skip to: 3645 + /* 3634 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 242, + 27, + 0, // Skip to: 10795 + /* 3641 */ MCD_OPC_Decode, + 247, + 16, + 80, // Opcode: SQXR + /* 3645 */ MCD_OPC_FilterValue, + 55, + 11, + 0, + 0, // Skip to: 3661 + /* 3650 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 226, + 27, + 0, // Skip to: 10795 + /* 3657 */ MCD_OPC_Decode, + 186, + 14, + 18, // Opcode: MEER + /* 3661 */ MCD_OPC_FilterValue, + 56, + 11, + 0, + 0, // Skip to: 3677 + /* 3666 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 210, + 27, + 0, // Skip to: 10795 + /* 3673 */ MCD_OPC_Decode, + 169, + 14, + 81, // Opcode: MAYLR + /* 3677 */ MCD_OPC_FilterValue, + 57, + 11, + 0, + 0, // Skip to: 3693 + /* 3682 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 194, + 27, + 0, // Skip to: 10795 + /* 3689 */ MCD_OPC_Decode, + 131, + 15, + 82, // Opcode: MYLR + /* 3693 */ MCD_OPC_FilterValue, + 58, + 11, + 0, + 0, // Skip to: 3709 + /* 3698 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 178, + 27, + 0, // Skip to: 10795 + /* 3705 */ MCD_OPC_Decode, + 170, + 14, + 83, // Opcode: MAYR + /* 3709 */ MCD_OPC_FilterValue, + 59, + 11, + 0, + 0, // Skip to: 3725 + /* 3714 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 162, + 27, + 0, // Skip to: 10795 + /* 3721 */ MCD_OPC_Decode, + 132, + 15, + 84, // Opcode: MYR + /* 3725 */ MCD_OPC_FilterValue, + 60, + 11, + 0, + 0, // Skip to: 3741 + /* 3730 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 146, + 27, + 0, // Skip to: 10795 + /* 3737 */ MCD_OPC_Decode, + 167, + 14, + 81, // Opcode: MAYHR + /* 3741 */ MCD_OPC_FilterValue, + 61, + 11, + 0, + 0, // Skip to: 3757 + /* 3746 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 130, + 27, + 0, // Skip to: 10795 + /* 3753 */ MCD_OPC_Decode, + 129, + 15, + 82, // Opcode: MYHR + /* 3757 */ MCD_OPC_FilterValue, + 62, + 11, + 0, + 0, // Skip to: 3773 + /* 3762 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 114, + 27, + 0, // Skip to: 10795 + /* 3769 */ MCD_OPC_Decode, + 160, + 14, + 81, // Opcode: MADR + /* 3773 */ MCD_OPC_FilterValue, + 63, + 11, + 0, + 0, // Skip to: 3789 + /* 3778 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 98, + 27, + 0, // Skip to: 10795 + /* 3785 */ MCD_OPC_Decode, + 208, + 14, + 81, // Opcode: MSDR + /* 3789 */ MCD_OPC_FilterValue, + 64, + 11, + 0, + 0, // Skip to: 3805 + /* 3794 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 82, + 27, + 0, // Skip to: 10795 + /* 3801 */ MCD_OPC_Decode, + 234, + 13, + 80, // Opcode: LPXBR + /* 3805 */ MCD_OPC_FilterValue, + 65, + 11, + 0, + 0, // Skip to: 3821 + /* 3810 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 66, + 27, + 0, // Skip to: 10795 + /* 3817 */ MCD_OPC_Decode, + 144, + 12, + 80, // Opcode: LNXBR + /* 3821 */ MCD_OPC_FilterValue, + 66, + 11, + 0, + 0, // Skip to: 3837 + /* 3826 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 50, + 27, + 0, // Skip to: 10795 + /* 3833 */ MCD_OPC_Decode, + 134, + 14, + 80, // Opcode: LTXBR + /* 3837 */ MCD_OPC_FilterValue, + 67, + 11, + 0, + 0, // Skip to: 3853 + /* 3842 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 34, + 27, + 0, // Skip to: 10795 + /* 3849 */ MCD_OPC_Decode, + 177, + 11, + 80, // Opcode: LCXBR + /* 3853 */ MCD_OPC_FilterValue, + 68, + 20, + 0, + 0, // Skip to: 3878 + /* 3858 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 3869 + /* 3865 */ MCD_OPC_Decode, + 195, + 11, + 17, // Opcode: LEDBR + /* 3869 */ MCD_OPC_CheckPredicate, + 2, + 9, + 27, + 0, // Skip to: 10795 + /* 3874 */ MCD_OPC_Decode, + 196, + 11, + 85, // Opcode: LEDBRA + /* 3878 */ MCD_OPC_FilterValue, + 69, + 20, + 0, + 0, // Skip to: 3903 + /* 3883 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 3894 + /* 3890 */ MCD_OPC_Decode, + 189, + 11, + 80, // Opcode: LDXBR + /* 3894 */ MCD_OPC_CheckPredicate, + 2, + 240, + 26, + 0, // Skip to: 10795 + /* 3899 */ MCD_OPC_Decode, + 190, + 11, + 86, // Opcode: LDXBRA + /* 3903 */ MCD_OPC_FilterValue, + 70, + 20, + 0, + 0, // Skip to: 3928 + /* 3908 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 3919 + /* 3915 */ MCD_OPC_Decode, + 200, + 11, + 80, // Opcode: LEXBR + /* 3919 */ MCD_OPC_CheckPredicate, + 2, + 215, + 26, + 0, // Skip to: 10795 + /* 3924 */ MCD_OPC_Decode, + 201, + 11, + 86, // Opcode: LEXBRA + /* 3928 */ MCD_OPC_FilterValue, + 71, + 20, + 0, + 0, // Skip to: 3953 + /* 3933 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 3944 + /* 3940 */ MCD_OPC_Decode, + 144, + 10, + 87, // Opcode: FIXBR + /* 3944 */ MCD_OPC_CheckPredicate, + 2, + 190, + 26, + 0, // Skip to: 10795 + /* 3949 */ MCD_OPC_Decode, + 145, + 10, + 86, // Opcode: FIXBRA + /* 3953 */ MCD_OPC_FilterValue, + 72, + 11, + 0, + 0, // Skip to: 3969 + /* 3958 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 174, + 26, + 0, // Skip to: 10795 + /* 3965 */ MCD_OPC_Decode, + 138, + 11, + 80, // Opcode: KXBR + /* 3969 */ MCD_OPC_FilterValue, + 73, + 11, + 0, + 0, // Skip to: 3985 + /* 3974 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 158, + 26, + 0, // Skip to: 10795 + /* 3981 */ MCD_OPC_Decode, + 188, + 9, + 80, // Opcode: CXBR + /* 3985 */ MCD_OPC_FilterValue, + 74, + 11, + 0, + 0, // Skip to: 4001 + /* 3990 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 142, + 26, + 0, // Skip to: 10795 + /* 3997 */ MCD_OPC_Decode, + 184, + 4, + 13, // Opcode: AXBR + /* 4001 */ MCD_OPC_FilterValue, + 75, + 11, + 0, + 0, // Skip to: 4017 + /* 4006 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 126, + 26, + 0, // Skip to: 10795 + /* 4013 */ MCD_OPC_Decode, + 141, + 18, + 13, // Opcode: SXBR + /* 4017 */ MCD_OPC_FilterValue, + 76, + 11, + 0, + 0, // Skip to: 4033 + /* 4022 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 110, + 26, + 0, // Skip to: 10795 + /* 4029 */ MCD_OPC_Decode, + 247, + 14, + 13, // Opcode: MXBR + /* 4033 */ MCD_OPC_FilterValue, + 77, + 11, + 0, + 0, // Skip to: 4049 + /* 4038 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 94, + 26, + 0, // Skip to: 10795 + /* 4045 */ MCD_OPC_Decode, + 236, + 9, + 13, // Opcode: DXBR + /* 4049 */ MCD_OPC_FilterValue, + 80, + 11, + 0, + 0, // Skip to: 4065 + /* 4054 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 78, + 26, + 0, // Skip to: 10795 + /* 4061 */ MCD_OPC_Decode, + 151, + 18, + 88, // Opcode: TBEDR + /* 4065 */ MCD_OPC_FilterValue, + 81, + 11, + 0, + 0, // Skip to: 4081 + /* 4070 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 62, + 26, + 0, // Skip to: 10795 + /* 4077 */ MCD_OPC_Decode, + 150, + 18, + 89, // Opcode: TBDR + /* 4081 */ MCD_OPC_FilterValue, + 83, + 4, + 0, + 0, // Skip to: 4090 + /* 4086 */ MCD_OPC_Decode, + 225, + 9, + 90, // Opcode: DIEBR + /* 4090 */ MCD_OPC_FilterValue, + 87, + 20, + 0, + 0, // Skip to: 4115 + /* 4095 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4106 + /* 4102 */ MCD_OPC_Decode, + 141, + 10, + 91, // Opcode: FIEBR + /* 4106 */ MCD_OPC_CheckPredicate, + 2, + 28, + 26, + 0, // Skip to: 10795 + /* 4111 */ MCD_OPC_Decode, + 142, + 10, + 92, // Opcode: FIEBRA + /* 4115 */ MCD_OPC_FilterValue, + 88, + 11, + 0, + 0, // Skip to: 4131 + /* 4120 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 12, + 26, + 0, // Skip to: 10795 + /* 4127 */ MCD_OPC_Decode, + 164, + 18, + 76, // Opcode: THDER + /* 4131 */ MCD_OPC_FilterValue, + 89, + 11, + 0, + 0, // Skip to: 4147 + /* 4136 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 252, + 25, + 0, // Skip to: 10795 + /* 4143 */ MCD_OPC_Decode, + 165, + 18, + 11, // Opcode: THDR + /* 4147 */ MCD_OPC_FilterValue, + 91, + 4, + 0, + 0, // Skip to: 4156 + /* 4152 */ MCD_OPC_Decode, + 224, + 9, + 93, // Opcode: DIDBR + /* 4156 */ MCD_OPC_FilterValue, + 95, + 20, + 0, + 0, // Skip to: 4181 + /* 4161 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4172 + /* 4168 */ MCD_OPC_Decode, + 137, + 10, + 89, // Opcode: FIDBR + /* 4172 */ MCD_OPC_CheckPredicate, + 2, + 218, + 25, + 0, // Skip to: 10795 + /* 4177 */ MCD_OPC_Decode, + 138, + 10, + 94, // Opcode: FIDBRA + /* 4181 */ MCD_OPC_FilterValue, + 96, + 11, + 0, + 0, // Skip to: 4197 + /* 4186 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 202, + 25, + 0, // Skip to: 10795 + /* 4193 */ MCD_OPC_Decode, + 235, + 13, + 80, // Opcode: LPXR + /* 4197 */ MCD_OPC_FilterValue, + 97, + 11, + 0, + 0, // Skip to: 4213 + /* 4202 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 186, + 25, + 0, // Skip to: 10795 + /* 4209 */ MCD_OPC_Decode, + 145, + 12, + 80, // Opcode: LNXR + /* 4213 */ MCD_OPC_FilterValue, + 98, + 11, + 0, + 0, // Skip to: 4229 + /* 4218 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 170, + 25, + 0, // Skip to: 10795 + /* 4225 */ MCD_OPC_Decode, + 136, + 14, + 80, // Opcode: LTXR + /* 4229 */ MCD_OPC_FilterValue, + 99, + 11, + 0, + 0, // Skip to: 4245 + /* 4234 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 154, + 25, + 0, // Skip to: 10795 + /* 4241 */ MCD_OPC_Decode, + 178, + 11, + 80, // Opcode: LCXR + /* 4245 */ MCD_OPC_FilterValue, + 101, + 11, + 0, + 0, // Skip to: 4261 + /* 4250 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 138, + 25, + 0, // Skip to: 10795 + /* 4257 */ MCD_OPC_Decode, + 149, + 14, + 80, // Opcode: LXR + /* 4261 */ MCD_OPC_FilterValue, + 102, + 11, + 0, + 0, // Skip to: 4277 + /* 4266 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 122, + 25, + 0, // Skip to: 10795 + /* 4273 */ MCD_OPC_Decode, + 202, + 11, + 95, // Opcode: LEXR + /* 4277 */ MCD_OPC_FilterValue, + 103, + 11, + 0, + 0, // Skip to: 4293 + /* 4282 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 106, + 25, + 0, // Skip to: 10795 + /* 4289 */ MCD_OPC_Decode, + 146, + 10, + 80, // Opcode: FIXR + /* 4293 */ MCD_OPC_FilterValue, + 105, + 11, + 0, + 0, // Skip to: 4309 + /* 4298 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 90, + 25, + 0, // Skip to: 10795 + /* 4305 */ MCD_OPC_Decode, + 203, + 9, + 80, // Opcode: CXR + /* 4309 */ MCD_OPC_FilterValue, + 112, + 11, + 0, + 0, // Skip to: 4325 + /* 4314 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 74, + 25, + 0, // Skip to: 10795 + /* 4321 */ MCD_OPC_Decode, + 219, + 13, + 11, // Opcode: LPDFR + /* 4325 */ MCD_OPC_FilterValue, + 113, + 11, + 0, + 0, // Skip to: 4341 + /* 4330 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 58, + 25, + 0, // Skip to: 10795 + /* 4337 */ MCD_OPC_Decode, + 136, + 12, + 11, // Opcode: LNDFR + /* 4341 */ MCD_OPC_FilterValue, + 114, + 11, + 0, + 0, // Skip to: 4357 + /* 4346 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 42, + 25, + 0, // Skip to: 10795 + /* 4353 */ MCD_OPC_Decode, + 232, + 8, + 96, // Opcode: CPSDRdd + /* 4357 */ MCD_OPC_FilterValue, + 115, + 11, + 0, + 0, // Skip to: 4373 + /* 4362 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 26, + 25, + 0, // Skip to: 10795 + /* 4369 */ MCD_OPC_Decode, + 167, + 11, + 11, // Opcode: LCDFR + /* 4373 */ MCD_OPC_FilterValue, + 116, + 18, + 0, + 0, // Skip to: 4396 + /* 4378 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 10, + 25, + 0, // Skip to: 10795 + /* 4385 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 3, + 25, + 0, // Skip to: 10795 + /* 4392 */ MCD_OPC_Decode, + 152, + 14, + 97, // Opcode: LZER + /* 4396 */ MCD_OPC_FilterValue, + 117, + 18, + 0, + 0, // Skip to: 4419 + /* 4401 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 243, + 24, + 0, // Skip to: 10795 + /* 4408 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 236, + 24, + 0, // Skip to: 10795 + /* 4415 */ MCD_OPC_Decode, + 151, + 14, + 98, // Opcode: LZDR + /* 4419 */ MCD_OPC_FilterValue, + 118, + 18, + 0, + 0, // Skip to: 4442 + /* 4424 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 220, + 24, + 0, // Skip to: 10795 + /* 4431 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 213, + 24, + 0, // Skip to: 10795 + /* 4438 */ MCD_OPC_Decode, + 155, + 14, + 99, // Opcode: LZXR + /* 4442 */ MCD_OPC_FilterValue, + 119, + 11, + 0, + 0, // Skip to: 4458 + /* 4447 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 197, + 24, + 0, // Skip to: 10795 + /* 4454 */ MCD_OPC_Decode, + 143, + 10, + 16, // Opcode: FIER + /* 4458 */ MCD_OPC_FilterValue, + 127, + 11, + 0, + 0, // Skip to: 4474 + /* 4463 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 181, + 24, + 0, // Skip to: 10795 + /* 4470 */ MCD_OPC_Decode, + 139, + 10, + 11, // Opcode: FIDR + /* 4474 */ MCD_OPC_FilterValue, + 132, + 1, + 18, + 0, + 0, // Skip to: 4498 + /* 4480 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 164, + 24, + 0, // Skip to: 10795 + /* 4487 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 157, + 24, + 0, // Skip to: 10795 + /* 4494 */ MCD_OPC_Decode, + 190, + 16, + 1, // Opcode: SFPC + /* 4498 */ MCD_OPC_FilterValue, + 133, + 1, + 18, + 0, + 0, // Skip to: 4522 + /* 4504 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 140, + 24, + 0, // Skip to: 10795 + /* 4511 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 133, + 24, + 0, // Skip to: 10795 + /* 4518 */ MCD_OPC_Decode, + 189, + 16, + 1, // Opcode: SFASR + /* 4522 */ MCD_OPC_FilterValue, + 140, + 1, + 18, + 0, + 0, // Skip to: 4546 + /* 4528 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 116, + 24, + 0, // Skip to: 10795 + /* 4535 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 109, + 24, + 0, // Skip to: 10795 + /* 4542 */ MCD_OPC_Decode, + 249, + 9, + 1, // Opcode: EFPC + /* 4546 */ MCD_OPC_FilterValue, + 144, + 1, + 9, + 0, + 0, // Skip to: 4561 + /* 4552 */ MCD_OPC_CheckPredicate, + 2, + 94, + 24, + 0, // Skip to: 10795 + /* 4557 */ MCD_OPC_Decode, + 198, + 5, + 100, // Opcode: CELFBR + /* 4561 */ MCD_OPC_FilterValue, + 145, + 1, + 9, + 0, + 0, // Skip to: 4576 + /* 4567 */ MCD_OPC_CheckPredicate, + 2, + 79, + 24, + 0, // Skip to: 10795 + /* 4572 */ MCD_OPC_Decode, + 175, + 5, + 101, // Opcode: CDLFBR + /* 4576 */ MCD_OPC_FilterValue, + 146, + 1, + 9, + 0, + 0, // Skip to: 4591 + /* 4582 */ MCD_OPC_CheckPredicate, + 2, + 64, + 24, + 0, // Skip to: 10795 + /* 4587 */ MCD_OPC_Decode, + 198, + 9, + 102, // Opcode: CXLFBR + /* 4591 */ MCD_OPC_FilterValue, + 148, + 1, + 20, + 0, + 0, // Skip to: 4617 + /* 4597 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 4608 + /* 4604 */ MCD_OPC_Decode, + 192, + 5, + 103, // Opcode: CEFBR + /* 4608 */ MCD_OPC_CheckPredicate, + 2, + 38, + 24, + 0, // Skip to: 10795 + /* 4613 */ MCD_OPC_Decode, + 193, + 5, + 100, // Opcode: CEFBRA + /* 4617 */ MCD_OPC_FilterValue, + 149, + 1, + 20, + 0, + 0, // Skip to: 4643 + /* 4623 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 4634 + /* 4630 */ MCD_OPC_Decode, + 166, + 5, + 104, // Opcode: CDFBR + /* 4634 */ MCD_OPC_CheckPredicate, + 2, + 12, + 24, + 0, // Skip to: 10795 + /* 4639 */ MCD_OPC_Decode, + 167, + 5, + 101, // Opcode: CDFBRA + /* 4643 */ MCD_OPC_FilterValue, + 150, + 1, + 20, + 0, + 0, // Skip to: 4669 + /* 4649 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 4660 + /* 4656 */ MCD_OPC_Decode, + 189, + 9, + 105, // Opcode: CXFBR + /* 4660 */ MCD_OPC_CheckPredicate, + 2, + 242, + 23, + 0, // Skip to: 10795 + /* 4665 */ MCD_OPC_Decode, + 190, + 9, + 102, // Opcode: CXFBRA + /* 4669 */ MCD_OPC_FilterValue, + 152, + 1, + 20, + 0, + 0, // Skip to: 4695 + /* 4675 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4686 + /* 4682 */ MCD_OPC_Decode, + 207, + 5, + 106, // Opcode: CFEBR + /* 4686 */ MCD_OPC_CheckPredicate, + 2, + 216, + 23, + 0, // Skip to: 10795 + /* 4691 */ MCD_OPC_Decode, + 208, + 5, + 107, // Opcode: CFEBRA + /* 4695 */ MCD_OPC_FilterValue, + 153, + 1, + 20, + 0, + 0, // Skip to: 4721 + /* 4701 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4712 + /* 4708 */ MCD_OPC_Decode, + 203, + 5, + 108, // Opcode: CFDBR + /* 4712 */ MCD_OPC_CheckPredicate, + 2, + 190, + 23, + 0, // Skip to: 10795 + /* 4717 */ MCD_OPC_Decode, + 204, + 5, + 109, // Opcode: CFDBRA + /* 4721 */ MCD_OPC_FilterValue, + 154, + 1, + 20, + 0, + 0, // Skip to: 4747 + /* 4727 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4738 + /* 4734 */ MCD_OPC_Decode, + 211, + 5, + 110, // Opcode: CFXBR + /* 4738 */ MCD_OPC_CheckPredicate, + 2, + 164, + 23, + 0, // Skip to: 10795 + /* 4743 */ MCD_OPC_Decode, + 212, + 5, + 111, // Opcode: CFXBRA + /* 4747 */ MCD_OPC_FilterValue, + 156, + 1, + 9, + 0, + 0, // Skip to: 4762 + /* 4753 */ MCD_OPC_CheckPredicate, + 2, + 149, + 23, + 0, // Skip to: 10795 + /* 4758 */ MCD_OPC_Decode, + 255, + 6, + 107, // Opcode: CLFEBR + /* 4762 */ MCD_OPC_FilterValue, + 157, + 1, + 9, + 0, + 0, // Skip to: 4777 + /* 4768 */ MCD_OPC_CheckPredicate, + 2, + 134, + 23, + 0, // Skip to: 10795 + /* 4773 */ MCD_OPC_Decode, + 253, + 6, + 109, // Opcode: CLFDBR + /* 4777 */ MCD_OPC_FilterValue, + 158, + 1, + 9, + 0, + 0, // Skip to: 4792 + /* 4783 */ MCD_OPC_CheckPredicate, + 2, + 119, + 23, + 0, // Skip to: 10795 + /* 4788 */ MCD_OPC_Decode, + 144, + 7, + 111, // Opcode: CLFXBR + /* 4792 */ MCD_OPC_FilterValue, + 160, + 1, + 9, + 0, + 0, // Skip to: 4807 + /* 4798 */ MCD_OPC_CheckPredicate, + 2, + 104, + 23, + 0, // Skip to: 10795 + /* 4803 */ MCD_OPC_Decode, + 199, + 5, + 112, // Opcode: CELGBR + /* 4807 */ MCD_OPC_FilterValue, + 161, + 1, + 9, + 0, + 0, // Skip to: 4822 + /* 4813 */ MCD_OPC_CheckPredicate, + 2, + 89, + 23, + 0, // Skip to: 10795 + /* 4818 */ MCD_OPC_Decode, + 177, + 5, + 113, // Opcode: CDLGBR + /* 4822 */ MCD_OPC_FilterValue, + 162, + 1, + 9, + 0, + 0, // Skip to: 4837 + /* 4828 */ MCD_OPC_CheckPredicate, + 2, + 74, + 23, + 0, // Skip to: 10795 + /* 4833 */ MCD_OPC_Decode, + 200, + 9, + 114, // Opcode: CXLGBR + /* 4837 */ MCD_OPC_FilterValue, + 164, + 1, + 20, + 0, + 0, // Skip to: 4863 + /* 4843 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 4854 + /* 4850 */ MCD_OPC_Decode, + 195, + 5, + 115, // Opcode: CEGBR + /* 4854 */ MCD_OPC_CheckPredicate, + 2, + 48, + 23, + 0, // Skip to: 10795 + /* 4859 */ MCD_OPC_Decode, + 196, + 5, + 112, // Opcode: CEGBRA + /* 4863 */ MCD_OPC_FilterValue, + 165, + 1, + 20, + 0, + 0, // Skip to: 4889 + /* 4869 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 4880 + /* 4876 */ MCD_OPC_Decode, + 170, + 5, + 116, // Opcode: CDGBR + /* 4880 */ MCD_OPC_CheckPredicate, + 2, + 22, + 23, + 0, // Skip to: 10795 + /* 4885 */ MCD_OPC_Decode, + 171, + 5, + 113, // Opcode: CDGBRA + /* 4889 */ MCD_OPC_FilterValue, + 166, + 1, + 20, + 0, + 0, // Skip to: 4915 + /* 4895 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 4906 + /* 4902 */ MCD_OPC_Decode, + 193, + 9, + 117, // Opcode: CXGBR + /* 4906 */ MCD_OPC_CheckPredicate, + 2, + 252, + 22, + 0, // Skip to: 10795 + /* 4911 */ MCD_OPC_Decode, + 194, + 9, + 114, // Opcode: CXGBRA + /* 4915 */ MCD_OPC_FilterValue, + 168, + 1, + 20, + 0, + 0, // Skip to: 4941 + /* 4921 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4932 + /* 4928 */ MCD_OPC_Decode, + 221, + 5, + 118, // Opcode: CGEBR + /* 4932 */ MCD_OPC_CheckPredicate, + 2, + 226, + 22, + 0, // Skip to: 10795 + /* 4937 */ MCD_OPC_Decode, + 222, + 5, + 119, // Opcode: CGEBRA + /* 4941 */ MCD_OPC_FilterValue, + 169, + 1, + 20, + 0, + 0, // Skip to: 4967 + /* 4947 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4958 + /* 4954 */ MCD_OPC_Decode, + 216, + 5, + 120, // Opcode: CGDBR + /* 4958 */ MCD_OPC_CheckPredicate, + 2, + 200, + 22, + 0, // Skip to: 10795 + /* 4963 */ MCD_OPC_Decode, + 217, + 5, + 121, // Opcode: CGDBRA + /* 4967 */ MCD_OPC_FilterValue, + 170, + 1, + 20, + 0, + 0, // Skip to: 4993 + /* 4973 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 4984 + /* 4980 */ MCD_OPC_Decode, + 190, + 6, + 122, // Opcode: CGXBR + /* 4984 */ MCD_OPC_CheckPredicate, + 2, + 174, + 22, + 0, // Skip to: 10795 + /* 4989 */ MCD_OPC_Decode, + 191, + 6, + 123, // Opcode: CGXBRA + /* 4993 */ MCD_OPC_FilterValue, + 172, + 1, + 9, + 0, + 0, // Skip to: 5008 + /* 4999 */ MCD_OPC_CheckPredicate, + 2, + 159, + 22, + 0, // Skip to: 10795 + /* 5004 */ MCD_OPC_Decode, + 149, + 7, + 119, // Opcode: CLGEBR + /* 5008 */ MCD_OPC_FilterValue, + 173, + 1, + 9, + 0, + 0, // Skip to: 5023 + /* 5014 */ MCD_OPC_CheckPredicate, + 2, + 144, + 22, + 0, // Skip to: 10795 + /* 5019 */ MCD_OPC_Decode, + 147, + 7, + 121, // Opcode: CLGDBR + /* 5023 */ MCD_OPC_FilterValue, + 174, + 1, + 9, + 0, + 0, // Skip to: 5038 + /* 5029 */ MCD_OPC_CheckPredicate, + 2, + 129, + 22, + 0, // Skip to: 10795 + /* 5034 */ MCD_OPC_Decode, + 128, + 8, + 123, // Opcode: CLGXBR + /* 5038 */ MCD_OPC_FilterValue, + 180, + 1, + 11, + 0, + 0, // Skip to: 5055 + /* 5044 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 112, + 22, + 0, // Skip to: 10795 + /* 5051 */ MCD_OPC_Decode, + 194, + 5, + 103, // Opcode: CEFR + /* 5055 */ MCD_OPC_FilterValue, + 181, + 1, + 11, + 0, + 0, // Skip to: 5072 + /* 5061 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 95, + 22, + 0, // Skip to: 10795 + /* 5068 */ MCD_OPC_Decode, + 168, + 5, + 104, // Opcode: CDFR + /* 5072 */ MCD_OPC_FilterValue, + 182, + 1, + 11, + 0, + 0, // Skip to: 5089 + /* 5078 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 78, + 22, + 0, // Skip to: 10795 + /* 5085 */ MCD_OPC_Decode, + 191, + 9, + 105, // Opcode: CXFR + /* 5089 */ MCD_OPC_FilterValue, + 184, + 1, + 11, + 0, + 0, // Skip to: 5106 + /* 5095 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 61, + 22, + 0, // Skip to: 10795 + /* 5102 */ MCD_OPC_Decode, + 209, + 5, + 106, // Opcode: CFER + /* 5106 */ MCD_OPC_FilterValue, + 185, + 1, + 11, + 0, + 0, // Skip to: 5123 + /* 5112 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 44, + 22, + 0, // Skip to: 10795 + /* 5119 */ MCD_OPC_Decode, + 205, + 5, + 108, // Opcode: CFDR + /* 5123 */ MCD_OPC_FilterValue, + 186, + 1, + 11, + 0, + 0, // Skip to: 5140 + /* 5129 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 27, + 22, + 0, // Skip to: 10795 + /* 5136 */ MCD_OPC_Decode, + 213, + 5, + 110, // Opcode: CFXR + /* 5140 */ MCD_OPC_FilterValue, + 193, + 1, + 11, + 0, + 0, // Skip to: 5157 + /* 5146 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 10, + 22, + 0, // Skip to: 10795 + /* 5153 */ MCD_OPC_Decode, + 186, + 11, + 116, // Opcode: LDGR + /* 5157 */ MCD_OPC_FilterValue, + 196, + 1, + 11, + 0, + 0, // Skip to: 5174 + /* 5163 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 249, + 21, + 0, // Skip to: 10795 + /* 5170 */ MCD_OPC_Decode, + 197, + 5, + 115, // Opcode: CEGR + /* 5174 */ MCD_OPC_FilterValue, + 197, + 1, + 11, + 0, + 0, // Skip to: 5191 + /* 5180 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 232, + 21, + 0, // Skip to: 10795 + /* 5187 */ MCD_OPC_Decode, + 172, + 5, + 116, // Opcode: CDGR + /* 5191 */ MCD_OPC_FilterValue, + 198, + 1, + 11, + 0, + 0, // Skip to: 5208 + /* 5197 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 215, + 21, + 0, // Skip to: 10795 + /* 5204 */ MCD_OPC_Decode, + 195, + 9, + 117, // Opcode: CXGR + /* 5208 */ MCD_OPC_FilterValue, + 200, + 1, + 11, + 0, + 0, // Skip to: 5225 + /* 5214 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 198, + 21, + 0, // Skip to: 10795 + /* 5221 */ MCD_OPC_Decode, + 223, + 5, + 118, // Opcode: CGER + /* 5225 */ MCD_OPC_FilterValue, + 201, + 1, + 11, + 0, + 0, // Skip to: 5242 + /* 5231 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 181, + 21, + 0, // Skip to: 10795 + /* 5238 */ MCD_OPC_Decode, + 218, + 5, + 120, // Opcode: CGDR + /* 5242 */ MCD_OPC_FilterValue, + 202, + 1, + 11, + 0, + 0, // Skip to: 5259 + /* 5248 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 164, + 21, + 0, // Skip to: 10795 + /* 5255 */ MCD_OPC_Decode, + 192, + 6, + 122, // Opcode: CGXR + /* 5259 */ MCD_OPC_FilterValue, + 205, + 1, + 11, + 0, + 0, // Skip to: 5276 + /* 5265 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 147, + 21, + 0, // Skip to: 10795 + /* 5272 */ MCD_OPC_Decode, + 212, + 11, + 124, // Opcode: LGDR + /* 5276 */ MCD_OPC_FilterValue, + 208, + 1, + 20, + 0, + 0, // Skip to: 5302 + /* 5282 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5293 + /* 5289 */ MCD_OPC_Decode, + 180, + 14, + 96, // Opcode: MDTR + /* 5293 */ MCD_OPC_CheckPredicate, + 2, + 121, + 21, + 0, // Skip to: 10795 + /* 5298 */ MCD_OPC_Decode, + 181, + 14, + 125, // Opcode: MDTRA + /* 5302 */ MCD_OPC_FilterValue, + 209, + 1, + 20, + 0, + 0, // Skip to: 5328 + /* 5308 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5319 + /* 5315 */ MCD_OPC_Decode, + 216, + 9, + 96, // Opcode: DDTR + /* 5319 */ MCD_OPC_CheckPredicate, + 2, + 95, + 21, + 0, // Skip to: 10795 + /* 5324 */ MCD_OPC_Decode, + 217, + 9, + 125, // Opcode: DDTRA + /* 5328 */ MCD_OPC_FilterValue, + 210, + 1, + 20, + 0, + 0, // Skip to: 5354 + /* 5334 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5345 + /* 5341 */ MCD_OPC_Decode, + 129, + 4, + 96, // Opcode: ADTR + /* 5345 */ MCD_OPC_CheckPredicate, + 2, + 69, + 21, + 0, // Skip to: 10795 + /* 5350 */ MCD_OPC_Decode, + 130, + 4, + 125, // Opcode: ADTRA + /* 5354 */ MCD_OPC_FilterValue, + 211, + 1, + 20, + 0, + 0, // Skip to: 5380 + /* 5360 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5371 + /* 5367 */ MCD_OPC_Decode, + 245, + 15, + 96, // Opcode: SDTR + /* 5371 */ MCD_OPC_CheckPredicate, + 2, + 43, + 21, + 0, // Skip to: 10795 + /* 5376 */ MCD_OPC_Decode, + 246, + 15, + 125, // Opcode: SDTRA + /* 5380 */ MCD_OPC_FilterValue, + 212, + 1, + 11, + 0, + 0, // Skip to: 5397 + /* 5386 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 26, + 21, + 0, // Skip to: 10795 + /* 5393 */ MCD_OPC_Decode, + 185, + 11, + 126, // Opcode: LDETR + /* 5397 */ MCD_OPC_FilterValue, + 213, + 1, + 4, + 0, + 0, // Skip to: 5407 + /* 5403 */ MCD_OPC_Decode, + 198, + 11, + 85, // Opcode: LEDTR + /* 5407 */ MCD_OPC_FilterValue, + 214, + 1, + 11, + 0, + 0, // Skip to: 5424 + /* 5413 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 255, + 20, + 0, // Skip to: 10795 + /* 5420 */ MCD_OPC_Decode, + 253, + 13, + 11, // Opcode: LTDTR + /* 5424 */ MCD_OPC_FilterValue, + 215, + 1, + 4, + 0, + 0, // Skip to: 5434 + /* 5430 */ MCD_OPC_Decode, + 140, + 10, + 94, // Opcode: FIDTR + /* 5434 */ MCD_OPC_FilterValue, + 216, + 1, + 21, + 0, + 0, // Skip to: 5461 + /* 5440 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5451 + /* 5447 */ MCD_OPC_Decode, + 253, + 14, + 127, // Opcode: MXTR + /* 5451 */ MCD_OPC_CheckPredicate, + 2, + 219, + 20, + 0, // Skip to: 10795 + /* 5456 */ MCD_OPC_Decode, + 254, + 14, + 128, + 1, // Opcode: MXTRA + /* 5461 */ MCD_OPC_FilterValue, + 217, + 1, + 21, + 0, + 0, // Skip to: 5488 + /* 5467 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5478 + /* 5474 */ MCD_OPC_Decode, + 238, + 9, + 127, // Opcode: DXTR + /* 5478 */ MCD_OPC_CheckPredicate, + 2, + 192, + 20, + 0, // Skip to: 10795 + /* 5483 */ MCD_OPC_Decode, + 239, + 9, + 128, + 1, // Opcode: DXTRA + /* 5488 */ MCD_OPC_FilterValue, + 218, + 1, + 21, + 0, + 0, // Skip to: 5515 + /* 5494 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5505 + /* 5501 */ MCD_OPC_Decode, + 186, + 4, + 127, // Opcode: AXTR + /* 5505 */ MCD_OPC_CheckPredicate, + 2, + 165, + 20, + 0, // Skip to: 10795 + /* 5510 */ MCD_OPC_Decode, + 187, + 4, + 128, + 1, // Opcode: AXTRA + /* 5515 */ MCD_OPC_FilterValue, + 219, + 1, + 21, + 0, + 0, // Skip to: 5542 + /* 5521 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5532 + /* 5528 */ MCD_OPC_Decode, + 143, + 18, + 127, // Opcode: SXTR + /* 5532 */ MCD_OPC_CheckPredicate, + 2, + 138, + 20, + 0, // Skip to: 10795 + /* 5537 */ MCD_OPC_Decode, + 144, + 18, + 128, + 1, // Opcode: SXTRA + /* 5542 */ MCD_OPC_FilterValue, + 220, + 1, + 12, + 0, + 0, // Skip to: 5560 + /* 5548 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 120, + 20, + 0, // Skip to: 10795 + /* 5555 */ MCD_OPC_Decode, + 144, + 14, + 129, + 1, // Opcode: LXDTR + /* 5560 */ MCD_OPC_FilterValue, + 221, + 1, + 4, + 0, + 0, // Skip to: 5570 + /* 5566 */ MCD_OPC_Decode, + 192, + 11, + 86, // Opcode: LDXTR + /* 5570 */ MCD_OPC_FilterValue, + 222, + 1, + 11, + 0, + 0, // Skip to: 5587 + /* 5576 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 92, + 20, + 0, // Skip to: 10795 + /* 5583 */ MCD_OPC_Decode, + 137, + 14, + 80, // Opcode: LTXTR + /* 5587 */ MCD_OPC_FilterValue, + 223, + 1, + 4, + 0, + 0, // Skip to: 5597 + /* 5593 */ MCD_OPC_Decode, + 147, + 10, + 86, // Opcode: FIXTR + /* 5597 */ MCD_OPC_FilterValue, + 224, + 1, + 11, + 0, + 0, // Skip to: 5614 + /* 5603 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 65, + 20, + 0, // Skip to: 10795 + /* 5610 */ MCD_OPC_Decode, + 254, + 10, + 11, // Opcode: KDTR + /* 5614 */ MCD_OPC_FilterValue, + 225, + 1, + 20, + 0, + 0, // Skip to: 5640 + /* 5620 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5631 + /* 5627 */ MCD_OPC_Decode, + 219, + 5, + 120, // Opcode: CGDTR + /* 5631 */ MCD_OPC_CheckPredicate, + 2, + 39, + 20, + 0, // Skip to: 10795 + /* 5636 */ MCD_OPC_Decode, + 220, + 5, + 121, // Opcode: CGDTRA + /* 5640 */ MCD_OPC_FilterValue, + 226, + 1, + 11, + 0, + 0, // Skip to: 5657 + /* 5646 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 22, + 20, + 0, // Skip to: 10795 + /* 5653 */ MCD_OPC_Decode, + 175, + 9, + 124, // Opcode: CUDTR + /* 5657 */ MCD_OPC_FilterValue, + 227, + 1, + 12, + 0, + 0, // Skip to: 5675 + /* 5663 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 5, + 20, + 0, // Skip to: 10795 + /* 5670 */ MCD_OPC_Decode, + 158, + 9, + 130, + 1, // Opcode: CSDTR + /* 5675 */ MCD_OPC_FilterValue, + 228, + 1, + 11, + 0, + 0, // Skip to: 5692 + /* 5681 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 243, + 19, + 0, // Skip to: 10795 + /* 5688 */ MCD_OPC_Decode, + 185, + 5, + 11, // Opcode: CDTR + /* 5692 */ MCD_OPC_FilterValue, + 229, + 1, + 11, + 0, + 0, // Skip to: 5709 + /* 5698 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 226, + 19, + 0, // Skip to: 10795 + /* 5705 */ MCD_OPC_Decode, + 247, + 9, + 11, // Opcode: EEDTR + /* 5709 */ MCD_OPC_FilterValue, + 231, + 1, + 11, + 0, + 0, // Skip to: 5726 + /* 5715 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 209, + 19, + 0, // Skip to: 10795 + /* 5722 */ MCD_OPC_Decode, + 130, + 10, + 11, // Opcode: ESDTR + /* 5726 */ MCD_OPC_FilterValue, + 232, + 1, + 11, + 0, + 0, // Skip to: 5743 + /* 5732 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 192, + 19, + 0, // Skip to: 10795 + /* 5739 */ MCD_OPC_Decode, + 139, + 11, + 80, // Opcode: KXTR + /* 5743 */ MCD_OPC_FilterValue, + 233, + 1, + 20, + 0, + 0, // Skip to: 5769 + /* 5749 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 4, + 0, + 0, // Skip to: 5760 + /* 5756 */ MCD_OPC_Decode, + 193, + 6, + 122, // Opcode: CGXTR + /* 5760 */ MCD_OPC_CheckPredicate, + 2, + 166, + 19, + 0, // Skip to: 10795 + /* 5765 */ MCD_OPC_Decode, + 194, + 6, + 123, // Opcode: CGXTRA + /* 5769 */ MCD_OPC_FilterValue, + 234, + 1, + 12, + 0, + 0, // Skip to: 5787 + /* 5775 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 149, + 19, + 0, // Skip to: 10795 + /* 5782 */ MCD_OPC_Decode, + 181, + 9, + 131, + 1, // Opcode: CUXTR + /* 5787 */ MCD_OPC_FilterValue, + 235, + 1, + 12, + 0, + 0, // Skip to: 5805 + /* 5793 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 131, + 19, + 0, // Skip to: 10795 + /* 5800 */ MCD_OPC_Decode, + 163, + 9, + 132, + 1, // Opcode: CSXTR + /* 5805 */ MCD_OPC_FilterValue, + 236, + 1, + 11, + 0, + 0, // Skip to: 5822 + /* 5811 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 113, + 19, + 0, // Skip to: 10795 + /* 5818 */ MCD_OPC_Decode, + 205, + 9, + 80, // Opcode: CXTR + /* 5822 */ MCD_OPC_FilterValue, + 237, + 1, + 11, + 0, + 0, // Skip to: 5839 + /* 5828 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 96, + 19, + 0, // Skip to: 10795 + /* 5835 */ MCD_OPC_Decode, + 248, + 9, + 80, // Opcode: EEXTR + /* 5839 */ MCD_OPC_FilterValue, + 239, + 1, + 11, + 0, + 0, // Skip to: 5856 + /* 5845 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 79, + 19, + 0, // Skip to: 10795 + /* 5852 */ MCD_OPC_Decode, + 133, + 10, + 80, // Opcode: ESXTR + /* 5856 */ MCD_OPC_FilterValue, + 241, + 1, + 20, + 0, + 0, // Skip to: 5882 + /* 5862 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 5873 + /* 5869 */ MCD_OPC_Decode, + 173, + 5, + 116, // Opcode: CDGTR + /* 5873 */ MCD_OPC_CheckPredicate, + 2, + 53, + 19, + 0, // Skip to: 10795 + /* 5878 */ MCD_OPC_Decode, + 174, + 5, + 113, // Opcode: CDGTRA + /* 5882 */ MCD_OPC_FilterValue, + 242, + 1, + 11, + 0, + 0, // Skip to: 5899 + /* 5888 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 36, + 19, + 0, // Skip to: 10795 + /* 5895 */ MCD_OPC_Decode, + 186, + 5, + 116, // Opcode: CDUTR + /* 5899 */ MCD_OPC_FilterValue, + 243, + 1, + 11, + 0, + 0, // Skip to: 5916 + /* 5905 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 19, + 19, + 0, // Skip to: 10795 + /* 5912 */ MCD_OPC_Decode, + 183, + 5, + 116, // Opcode: CDSTR + /* 5916 */ MCD_OPC_FilterValue, + 244, + 1, + 11, + 0, + 0, // Skip to: 5933 + /* 5922 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 2, + 19, + 0, // Skip to: 10795 + /* 5929 */ MCD_OPC_Decode, + 191, + 5, + 11, // Opcode: CEDTR + /* 5933 */ MCD_OPC_FilterValue, + 245, + 1, + 4, + 0, + 0, // Skip to: 5943 + /* 5939 */ MCD_OPC_Decode, + 204, + 15, + 93, // Opcode: QADTR + /* 5943 */ MCD_OPC_FilterValue, + 246, + 1, + 11, + 0, + 0, // Skip to: 5960 + /* 5949 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 231, + 18, + 0, // Skip to: 10795 + /* 5956 */ MCD_OPC_Decode, + 162, + 10, + 96, // Opcode: IEDTR + /* 5960 */ MCD_OPC_FilterValue, + 247, + 1, + 4, + 0, + 0, // Skip to: 5970 + /* 5966 */ MCD_OPC_Decode, + 224, + 15, + 93, // Opcode: RRDTR + /* 5970 */ MCD_OPC_FilterValue, + 249, + 1, + 20, + 0, + 0, // Skip to: 5996 + /* 5976 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 4, + 0, + 0, // Skip to: 5987 + /* 5983 */ MCD_OPC_Decode, + 196, + 9, + 117, // Opcode: CXGTR + /* 5987 */ MCD_OPC_CheckPredicate, + 2, + 195, + 18, + 0, // Skip to: 10795 + /* 5992 */ MCD_OPC_Decode, + 197, + 9, + 114, // Opcode: CXGTRA + /* 5996 */ MCD_OPC_FilterValue, + 250, + 1, + 12, + 0, + 0, // Skip to: 6014 + /* 6002 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 178, + 18, + 0, // Skip to: 10795 + /* 6009 */ MCD_OPC_Decode, + 206, + 9, + 133, + 1, // Opcode: CXUTR + /* 6014 */ MCD_OPC_FilterValue, + 251, + 1, + 12, + 0, + 0, // Skip to: 6032 + /* 6020 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 160, + 18, + 0, // Skip to: 10795 + /* 6027 */ MCD_OPC_Decode, + 204, + 9, + 133, + 1, // Opcode: CXSTR + /* 6032 */ MCD_OPC_FilterValue, + 252, + 1, + 11, + 0, + 0, // Skip to: 6049 + /* 6038 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 142, + 18, + 0, // Skip to: 10795 + /* 6045 */ MCD_OPC_Decode, + 201, + 5, + 80, // Opcode: CEXTR + /* 6049 */ MCD_OPC_FilterValue, + 253, + 1, + 5, + 0, + 0, // Skip to: 6060 + /* 6055 */ MCD_OPC_Decode, + 205, + 15, + 134, + 1, // Opcode: QAXTR + /* 6060 */ MCD_OPC_FilterValue, + 254, + 1, + 11, + 0, + 0, // Skip to: 6077 + /* 6066 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 114, + 18, + 0, // Skip to: 10795 + /* 6073 */ MCD_OPC_Decode, + 163, + 10, + 127, // Opcode: IEXTR + /* 6077 */ MCD_OPC_FilterValue, + 255, + 1, + 104, + 18, + 0, // Skip to: 10795 + /* 6083 */ MCD_OPC_Decode, + 225, + 15, + 134, + 1, // Opcode: RRXTR + /* 6088 */ MCD_OPC_FilterValue, + 182, + 1, + 5, + 0, + 0, // Skip to: 6099 + /* 6094 */ MCD_OPC_Decode, + 161, + 17, + 135, + 1, // Opcode: STCTL + /* 6099 */ MCD_OPC_FilterValue, + 183, + 1, + 5, + 0, + 0, // Skip to: 6110 + /* 6105 */ MCD_OPC_Decode, + 175, + 11, + 135, + 1, // Opcode: LCTL + /* 6110 */ MCD_OPC_FilterValue, + 185, + 1, + 17, + 18, + 0, // Skip to: 10741 + /* 6116 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 6119 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 6135 + /* 6124 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 56, + 18, + 0, // Skip to: 10795 + /* 6131 */ MCD_OPC_Decode, + 226, + 13, + 62, // Opcode: LPGR + /* 6135 */ MCD_OPC_FilterValue, + 1, + 11, + 0, + 0, // Skip to: 6151 + /* 6140 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 40, + 18, + 0, // Skip to: 10795 + /* 6147 */ MCD_OPC_Decode, + 142, + 12, + 62, // Opcode: LNGR + /* 6151 */ MCD_OPC_FilterValue, + 2, + 11, + 0, + 0, // Skip to: 6167 + /* 6156 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 24, + 18, + 0, // Skip to: 10795 + /* 6163 */ MCD_OPC_Decode, + 132, + 14, + 62, // Opcode: LTGR + /* 6167 */ MCD_OPC_FilterValue, + 3, + 11, + 0, + 0, // Skip to: 6183 + /* 6172 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 8, + 18, + 0, // Skip to: 10795 + /* 6179 */ MCD_OPC_Decode, + 173, + 11, + 62, // Opcode: LCGR + /* 6183 */ MCD_OPC_FilterValue, + 4, + 11, + 0, + 0, // Skip to: 6199 + /* 6188 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 248, + 17, + 0, // Skip to: 10795 + /* 6195 */ MCD_OPC_Decode, + 222, + 11, + 62, // Opcode: LGR + /* 6199 */ MCD_OPC_FilterValue, + 5, + 11, + 0, + 0, // Skip to: 6215 + /* 6204 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 232, + 17, + 0, // Skip to: 10795 + /* 6211 */ MCD_OPC_Decode, + 139, + 14, + 62, // Opcode: LURAG + /* 6215 */ MCD_OPC_FilterValue, + 6, + 11, + 0, + 0, // Skip to: 6231 + /* 6220 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 216, + 17, + 0, // Skip to: 10795 + /* 6227 */ MCD_OPC_Decode, + 211, + 11, + 62, // Opcode: LGBR + /* 6231 */ MCD_OPC_FilterValue, + 7, + 11, + 0, + 0, // Skip to: 6247 + /* 6236 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 200, + 17, + 0, // Skip to: 10795 + /* 6243 */ MCD_OPC_Decode, + 220, + 11, + 62, // Opcode: LGHR + /* 6247 */ MCD_OPC_FilterValue, + 8, + 12, + 0, + 0, // Skip to: 6264 + /* 6252 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 184, + 17, + 0, // Skip to: 10795 + /* 6259 */ MCD_OPC_Decode, + 143, + 4, + 136, + 1, // Opcode: AGR + /* 6264 */ MCD_OPC_FilterValue, + 9, + 12, + 0, + 0, // Skip to: 6281 + /* 6269 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 167, + 17, + 0, // Skip to: 10795 + /* 6276 */ MCD_OPC_Decode, + 195, + 16, + 136, + 1, // Opcode: SGR + /* 6281 */ MCD_OPC_FilterValue, + 10, + 12, + 0, + 0, // Skip to: 6298 + /* 6286 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 150, + 17, + 0, // Skip to: 10795 + /* 6293 */ MCD_OPC_Decode, + 164, + 4, + 136, + 1, // Opcode: ALGR + /* 6298 */ MCD_OPC_FilterValue, + 11, + 12, + 0, + 0, // Skip to: 6315 + /* 6303 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 133, + 17, + 0, // Skip to: 10795 + /* 6310 */ MCD_OPC_Decode, + 220, + 16, + 136, + 1, // Opcode: SLGR + /* 6315 */ MCD_OPC_FilterValue, + 12, + 12, + 0, + 0, // Skip to: 6332 + /* 6320 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 116, + 17, + 0, // Skip to: 10795 + /* 6327 */ MCD_OPC_Decode, + 219, + 14, + 136, + 1, // Opcode: MSGR + /* 6332 */ MCD_OPC_FilterValue, + 13, + 11, + 0, + 0, // Skip to: 6348 + /* 6337 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 99, + 17, + 0, // Skip to: 10795 + /* 6344 */ MCD_OPC_Decode, + 235, + 9, + 69, // Opcode: DSGR + /* 6348 */ MCD_OPC_FilterValue, + 14, + 11, + 0, + 0, // Skip to: 6364 + /* 6353 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 83, + 17, + 0, // Skip to: 10795 + /* 6360 */ MCD_OPC_Decode, + 255, + 9, + 62, // Opcode: EREGG + /* 6364 */ MCD_OPC_FilterValue, + 15, + 11, + 0, + 0, // Skip to: 6380 + /* 6369 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 67, + 17, + 0, // Skip to: 10795 + /* 6376 */ MCD_OPC_Decode, + 245, + 13, + 62, // Opcode: LRVGR + /* 6380 */ MCD_OPC_FilterValue, + 16, + 11, + 0, + 0, // Skip to: 6396 + /* 6385 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 51, + 17, + 0, // Skip to: 10795 + /* 6392 */ MCD_OPC_Decode, + 225, + 13, + 57, // Opcode: LPGFR + /* 6396 */ MCD_OPC_FilterValue, + 17, + 11, + 0, + 0, // Skip to: 6412 + /* 6401 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 35, + 17, + 0, // Skip to: 10795 + /* 6408 */ MCD_OPC_Decode, + 141, + 12, + 57, // Opcode: LNGFR + /* 6412 */ MCD_OPC_FilterValue, + 18, + 11, + 0, + 0, // Skip to: 6428 + /* 6417 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 19, + 17, + 0, // Skip to: 10795 + /* 6424 */ MCD_OPC_Decode, + 131, + 14, + 57, // Opcode: LTGFR + /* 6428 */ MCD_OPC_FilterValue, + 19, + 11, + 0, + 0, // Skip to: 6444 + /* 6433 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 3, + 17, + 0, // Skip to: 10795 + /* 6440 */ MCD_OPC_Decode, + 172, + 11, + 57, // Opcode: LCGFR + /* 6444 */ MCD_OPC_FilterValue, + 20, + 11, + 0, + 0, // Skip to: 6460 + /* 6449 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 243, + 16, + 0, // Skip to: 10795 + /* 6456 */ MCD_OPC_Decode, + 215, + 11, + 57, // Opcode: LGFR + /* 6460 */ MCD_OPC_FilterValue, + 22, + 11, + 0, + 0, // Skip to: 6476 + /* 6465 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 227, + 16, + 0, // Skip to: 10795 + /* 6472 */ MCD_OPC_Decode, + 238, + 11, + 57, // Opcode: LLGFR + /* 6476 */ MCD_OPC_FilterValue, + 23, + 11, + 0, + 0, // Skip to: 6492 + /* 6481 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 211, + 16, + 0, // Skip to: 10795 + /* 6488 */ MCD_OPC_Decode, + 246, + 11, + 62, // Opcode: LLGTR + /* 6492 */ MCD_OPC_FilterValue, + 24, + 12, + 0, + 0, // Skip to: 6509 + /* 6497 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 195, + 16, + 0, // Skip to: 10795 + /* 6504 */ MCD_OPC_Decode, + 139, + 4, + 137, + 1, // Opcode: AGFR + /* 6509 */ MCD_OPC_FilterValue, + 25, + 12, + 0, + 0, // Skip to: 6526 + /* 6514 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 178, + 16, + 0, // Skip to: 10795 + /* 6521 */ MCD_OPC_Decode, + 193, + 16, + 137, + 1, // Opcode: SGFR + /* 6526 */ MCD_OPC_FilterValue, + 26, + 12, + 0, + 0, // Skip to: 6543 + /* 6531 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 161, + 16, + 0, // Skip to: 10795 + /* 6538 */ MCD_OPC_Decode, + 162, + 4, + 137, + 1, // Opcode: ALGFR + /* 6543 */ MCD_OPC_FilterValue, + 27, + 12, + 0, + 0, // Skip to: 6560 + /* 6548 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 144, + 16, + 0, // Skip to: 10795 + /* 6555 */ MCD_OPC_Decode, + 219, + 16, + 137, + 1, // Opcode: SLGFR + /* 6560 */ MCD_OPC_FilterValue, + 28, + 12, + 0, + 0, // Skip to: 6577 + /* 6565 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 127, + 16, + 0, // Skip to: 10795 + /* 6572 */ MCD_OPC_Decode, + 218, + 14, + 137, + 1, // Opcode: MSGFR + /* 6577 */ MCD_OPC_FilterValue, + 29, + 11, + 0, + 0, // Skip to: 6593 + /* 6582 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 110, + 16, + 0, // Skip to: 10795 + /* 6589 */ MCD_OPC_Decode, + 234, + 9, + 10, // Opcode: DSGFR + /* 6593 */ MCD_OPC_FilterValue, + 30, + 12, + 0, + 0, // Skip to: 6610 + /* 6598 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 94, + 16, + 0, // Skip to: 10795 + /* 6605 */ MCD_OPC_Decode, + 133, + 11, + 138, + 1, // Opcode: KMAC + /* 6610 */ MCD_OPC_FilterValue, + 31, + 11, + 0, + 0, // Skip to: 6626 + /* 6615 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 77, + 16, + 0, // Skip to: 10795 + /* 6622 */ MCD_OPC_Decode, + 247, + 13, + 8, // Opcode: LRVR + /* 6626 */ MCD_OPC_FilterValue, + 32, + 11, + 0, + 0, // Skip to: 6642 + /* 6631 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 61, + 16, + 0, // Skip to: 10795 + /* 6638 */ MCD_OPC_Decode, + 146, + 6, + 62, // Opcode: CGR + /* 6642 */ MCD_OPC_FilterValue, + 33, + 11, + 0, + 0, // Skip to: 6658 + /* 6647 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 45, + 16, + 0, // Skip to: 10795 + /* 6654 */ MCD_OPC_Decode, + 198, + 7, + 62, // Opcode: CLGR + /* 6658 */ MCD_OPC_FilterValue, + 37, + 11, + 0, + 0, // Skip to: 6674 + /* 6663 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 29, + 16, + 0, // Skip to: 10795 + /* 6670 */ MCD_OPC_Decode, + 134, + 18, + 62, // Opcode: STURG + /* 6674 */ MCD_OPC_FilterValue, + 38, + 11, + 0, + 0, // Skip to: 6690 + /* 6679 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 13, + 16, + 0, // Skip to: 10795 + /* 6686 */ MCD_OPC_Decode, + 163, + 11, + 8, // Opcode: LBR + /* 6690 */ MCD_OPC_FilterValue, + 39, + 11, + 0, + 0, // Skip to: 6706 + /* 6695 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 253, + 15, + 0, // Skip to: 10795 + /* 6702 */ MCD_OPC_Decode, + 228, + 11, + 8, // Opcode: LHR + /* 6706 */ MCD_OPC_FilterValue, + 40, + 16, + 0, + 0, // Skip to: 6727 + /* 6711 */ MCD_OPC_CheckPredicate, + 6, + 239, + 15, + 0, // Skip to: 10795 + /* 6716 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 232, + 15, + 0, // Skip to: 10795 + /* 6723 */ MCD_OPC_Decode, + 183, + 15, + 0, // Opcode: PCKMO + /* 6727 */ MCD_OPC_FilterValue, + 41, + 17, + 0, + 0, // Skip to: 6749 + /* 6732 */ MCD_OPC_CheckPredicate, + 7, + 218, + 15, + 0, // Skip to: 10795 + /* 6737 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 211, + 15, + 0, // Skip to: 10795 + /* 6744 */ MCD_OPC_Decode, + 132, + 11, + 139, + 1, // Opcode: KMA + /* 6749 */ MCD_OPC_FilterValue, + 42, + 16, + 0, + 0, // Skip to: 6770 + /* 6754 */ MCD_OPC_CheckPredicate, + 8, + 196, + 15, + 0, // Skip to: 10795 + /* 6759 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 189, + 15, + 0, // Skip to: 10795 + /* 6766 */ MCD_OPC_Decode, + 136, + 11, + 7, // Opcode: KMF + /* 6770 */ MCD_OPC_FilterValue, + 43, + 16, + 0, + 0, // Skip to: 6791 + /* 6775 */ MCD_OPC_CheckPredicate, + 8, + 175, + 15, + 0, // Skip to: 10795 + /* 6780 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 168, + 15, + 0, // Skip to: 10795 + /* 6787 */ MCD_OPC_Decode, + 137, + 11, + 7, // Opcode: KMO + /* 6791 */ MCD_OPC_FilterValue, + 44, + 16, + 0, + 0, // Skip to: 6812 + /* 6796 */ MCD_OPC_CheckPredicate, + 8, + 154, + 15, + 0, // Skip to: 10795 + /* 6801 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 147, + 15, + 0, // Skip to: 10795 + /* 6808 */ MCD_OPC_Decode, + 182, + 15, + 0, // Opcode: PCC + /* 6812 */ MCD_OPC_FilterValue, + 45, + 17, + 0, + 0, // Skip to: 6834 + /* 6817 */ MCD_OPC_CheckPredicate, + 8, + 133, + 15, + 0, // Skip to: 10795 + /* 6822 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 126, + 15, + 0, // Skip to: 10795 + /* 6829 */ MCD_OPC_Decode, + 135, + 11, + 139, + 1, // Opcode: KMCTR + /* 6834 */ MCD_OPC_FilterValue, + 46, + 11, + 0, + 0, // Skip to: 6850 + /* 6839 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 109, + 15, + 0, // Skip to: 10795 + /* 6846 */ MCD_OPC_Decode, + 131, + 11, + 7, // Opcode: KM + /* 6850 */ MCD_OPC_FilterValue, + 47, + 11, + 0, + 0, // Skip to: 6866 + /* 6855 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 93, + 15, + 0, // Skip to: 10795 + /* 6862 */ MCD_OPC_Decode, + 134, + 11, + 7, // Opcode: KMC + /* 6866 */ MCD_OPC_FilterValue, + 48, + 11, + 0, + 0, // Skip to: 6882 + /* 6871 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 77, + 15, + 0, // Skip to: 10795 + /* 6878 */ MCD_OPC_Decode, + 226, + 5, + 57, // Opcode: CGFR + /* 6882 */ MCD_OPC_FilterValue, + 49, + 11, + 0, + 0, // Skip to: 6898 + /* 6887 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 61, + 15, + 0, // Skip to: 10795 + /* 6894 */ MCD_OPC_Decode, + 152, + 7, + 57, // Opcode: CLGFR + /* 6898 */ MCD_OPC_FilterValue, + 56, + 16, + 0, + 0, // Skip to: 6919 + /* 6903 */ MCD_OPC_CheckPredicate, + 9, + 47, + 15, + 0, // Skip to: 10795 + /* 6908 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 40, + 15, + 0, // Skip to: 10795 + /* 6915 */ MCD_OPC_Decode, + 231, + 16, + 7, // Opcode: SORTL + /* 6919 */ MCD_OPC_FilterValue, + 57, + 17, + 0, + 0, // Skip to: 6941 + /* 6924 */ MCD_OPC_CheckPredicate, + 10, + 26, + 15, + 0, // Skip to: 10795 + /* 6929 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 19, + 15, + 0, // Skip to: 10795 + /* 6936 */ MCD_OPC_Decode, + 222, + 9, + 140, + 1, // Opcode: DFLTCC + /* 6941 */ MCD_OPC_FilterValue, + 58, + 17, + 0, + 0, // Skip to: 6963 + /* 6946 */ MCD_OPC_CheckPredicate, + 11, + 4, + 15, + 0, // Skip to: 10795 + /* 6951 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 253, + 14, + 0, // Skip to: 10795 + /* 6958 */ MCD_OPC_Decode, + 253, + 10, + 138, + 1, // Opcode: KDSA + /* 6963 */ MCD_OPC_FilterValue, + 59, + 16, + 0, + 0, // Skip to: 6984 + /* 6968 */ MCD_OPC_CheckPredicate, + 12, + 238, + 14, + 0, // Skip to: 10795 + /* 6973 */ MCD_OPC_CheckField, + 0, + 16, + 0, + 231, + 14, + 0, // Skip to: 10795 + /* 6980 */ MCD_OPC_Decode, + 150, + 15, + 0, // Opcode: NNPA + /* 6984 */ MCD_OPC_FilterValue, + 60, + 16, + 0, + 0, // Skip to: 7005 + /* 6989 */ MCD_OPC_CheckPredicate, + 13, + 217, + 14, + 0, // Skip to: 10795 + /* 6994 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 210, + 14, + 0, // Skip to: 10795 + /* 7001 */ MCD_OPC_Decode, + 196, + 15, + 7, // Opcode: PPNO + /* 7005 */ MCD_OPC_FilterValue, + 62, + 12, + 0, + 0, // Skip to: 7022 + /* 7010 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 194, + 14, + 0, // Skip to: 10795 + /* 7017 */ MCD_OPC_Decode, + 129, + 11, + 138, + 1, // Opcode: KIMD + /* 7022 */ MCD_OPC_FilterValue, + 63, + 12, + 0, + 0, // Skip to: 7039 + /* 7027 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 177, + 14, + 0, // Skip to: 10795 + /* 7034 */ MCD_OPC_Decode, + 130, + 11, + 138, + 1, // Opcode: KLMD + /* 7039 */ MCD_OPC_FilterValue, + 65, + 9, + 0, + 0, // Skip to: 7053 + /* 7044 */ MCD_OPC_CheckPredicate, + 2, + 162, + 14, + 0, // Skip to: 10795 + /* 7049 */ MCD_OPC_Decode, + 206, + 5, + 109, // Opcode: CFDTR + /* 7053 */ MCD_OPC_FilterValue, + 66, + 9, + 0, + 0, // Skip to: 7067 + /* 7058 */ MCD_OPC_CheckPredicate, + 2, + 148, + 14, + 0, // Skip to: 10795 + /* 7063 */ MCD_OPC_Decode, + 148, + 7, + 121, // Opcode: CLGDTR + /* 7067 */ MCD_OPC_FilterValue, + 67, + 9, + 0, + 0, // Skip to: 7081 + /* 7072 */ MCD_OPC_CheckPredicate, + 2, + 134, + 14, + 0, // Skip to: 10795 + /* 7077 */ MCD_OPC_Decode, + 254, + 6, + 109, // Opcode: CLFDTR + /* 7081 */ MCD_OPC_FilterValue, + 70, + 12, + 0, + 0, // Skip to: 7098 + /* 7086 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 118, + 14, + 0, // Skip to: 10795 + /* 7093 */ MCD_OPC_Decode, + 222, + 4, + 136, + 1, // Opcode: BCTGR + /* 7098 */ MCD_OPC_FilterValue, + 73, + 9, + 0, + 0, // Skip to: 7112 + /* 7103 */ MCD_OPC_CheckPredicate, + 2, + 103, + 14, + 0, // Skip to: 10795 + /* 7108 */ MCD_OPC_Decode, + 214, + 5, + 111, // Opcode: CFXTR + /* 7112 */ MCD_OPC_FilterValue, + 74, + 9, + 0, + 0, // Skip to: 7126 + /* 7117 */ MCD_OPC_CheckPredicate, + 2, + 89, + 14, + 0, // Skip to: 10795 + /* 7122 */ MCD_OPC_Decode, + 129, + 8, + 123, // Opcode: CLGXTR + /* 7126 */ MCD_OPC_FilterValue, + 75, + 9, + 0, + 0, // Skip to: 7140 + /* 7131 */ MCD_OPC_CheckPredicate, + 2, + 75, + 14, + 0, // Skip to: 10795 + /* 7136 */ MCD_OPC_Decode, + 145, + 7, + 111, // Opcode: CLFXTR + /* 7140 */ MCD_OPC_FilterValue, + 81, + 9, + 0, + 0, // Skip to: 7154 + /* 7145 */ MCD_OPC_CheckPredicate, + 2, + 61, + 14, + 0, // Skip to: 10795 + /* 7150 */ MCD_OPC_Decode, + 169, + 5, + 101, // Opcode: CDFTR + /* 7154 */ MCD_OPC_FilterValue, + 82, + 9, + 0, + 0, // Skip to: 7168 + /* 7159 */ MCD_OPC_CheckPredicate, + 2, + 47, + 14, + 0, // Skip to: 10795 + /* 7164 */ MCD_OPC_Decode, + 178, + 5, + 113, // Opcode: CDLGTR + /* 7168 */ MCD_OPC_FilterValue, + 83, + 9, + 0, + 0, // Skip to: 7182 + /* 7173 */ MCD_OPC_CheckPredicate, + 2, + 33, + 14, + 0, // Skip to: 10795 + /* 7178 */ MCD_OPC_Decode, + 176, + 5, + 101, // Opcode: CDLFTR + /* 7182 */ MCD_OPC_FilterValue, + 89, + 9, + 0, + 0, // Skip to: 7196 + /* 7187 */ MCD_OPC_CheckPredicate, + 2, + 19, + 14, + 0, // Skip to: 10795 + /* 7192 */ MCD_OPC_Decode, + 192, + 9, + 102, // Opcode: CXFTR + /* 7196 */ MCD_OPC_FilterValue, + 90, + 9, + 0, + 0, // Skip to: 7210 + /* 7201 */ MCD_OPC_CheckPredicate, + 2, + 5, + 14, + 0, // Skip to: 10795 + /* 7206 */ MCD_OPC_Decode, + 201, + 9, + 114, // Opcode: CXLGTR + /* 7210 */ MCD_OPC_FilterValue, + 91, + 9, + 0, + 0, // Skip to: 7224 + /* 7215 */ MCD_OPC_CheckPredicate, + 2, + 247, + 13, + 0, // Skip to: 10795 + /* 7220 */ MCD_OPC_Decode, + 199, + 9, + 102, // Opcode: CXLFTR + /* 7224 */ MCD_OPC_FilterValue, + 96, + 69, + 0, + 0, // Skip to: 7298 + /* 7229 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 7232 */ MCD_OPC_FilterValue, + 0, + 230, + 13, + 0, // Skip to: 10795 + /* 7237 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7240 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 7249 + /* 7245 */ MCD_OPC_Decode, + 179, + 6, + 62, // Opcode: CGRTAsmH + /* 7249 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 7258 + /* 7254 */ MCD_OPC_Decode, + 181, + 6, + 62, // Opcode: CGRTAsmL + /* 7258 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 7267 + /* 7263 */ MCD_OPC_Decode, + 183, + 6, + 62, // Opcode: CGRTAsmLH + /* 7267 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 7276 + /* 7272 */ MCD_OPC_Decode, + 178, + 6, + 62, // Opcode: CGRTAsmE + /* 7276 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 7285 + /* 7281 */ MCD_OPC_Decode, + 180, + 6, + 62, // Opcode: CGRTAsmHE + /* 7285 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 7294 + /* 7290 */ MCD_OPC_Decode, + 182, + 6, + 62, // Opcode: CGRTAsmLE + /* 7294 */ MCD_OPC_Decode, + 177, + 6, + 74, // Opcode: CGRTAsm + /* 7298 */ MCD_OPC_FilterValue, + 97, + 69, + 0, + 0, // Skip to: 7372 + /* 7303 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 7306 */ MCD_OPC_FilterValue, + 0, + 156, + 13, + 0, // Skip to: 10795 + /* 7311 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7314 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 7323 + /* 7319 */ MCD_OPC_Decode, + 231, + 7, + 62, // Opcode: CLGRTAsmH + /* 7323 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 7332 + /* 7328 */ MCD_OPC_Decode, + 233, + 7, + 62, // Opcode: CLGRTAsmL + /* 7332 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 7341 + /* 7337 */ MCD_OPC_Decode, + 235, + 7, + 62, // Opcode: CLGRTAsmLH + /* 7341 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 7350 + /* 7346 */ MCD_OPC_Decode, + 230, + 7, + 62, // Opcode: CLGRTAsmE + /* 7350 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 7359 + /* 7355 */ MCD_OPC_Decode, + 232, + 7, + 62, // Opcode: CLGRTAsmHE + /* 7359 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 7368 + /* 7364 */ MCD_OPC_Decode, + 234, + 7, + 62, // Opcode: CLGRTAsmLE + /* 7368 */ MCD_OPC_Decode, + 229, + 7, + 74, // Opcode: CLGRTAsm + /* 7372 */ MCD_OPC_FilterValue, + 100, + 17, + 0, + 0, // Skip to: 7394 + /* 7377 */ MCD_OPC_CheckPredicate, + 14, + 85, + 13, + 0, // Skip to: 10795 + /* 7382 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 78, + 13, + 0, // Skip to: 10795 + /* 7389 */ MCD_OPC_Decode, + 149, + 15, + 141, + 1, // Opcode: NNGRK + /* 7394 */ MCD_OPC_FilterValue, + 101, + 17, + 0, + 0, // Skip to: 7416 + /* 7399 */ MCD_OPC_CheckPredicate, + 14, + 63, + 13, + 0, // Skip to: 10795 + /* 7404 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 56, + 13, + 0, // Skip to: 10795 + /* 7411 */ MCD_OPC_Decode, + 163, + 15, + 141, + 1, // Opcode: OCGRK + /* 7416 */ MCD_OPC_FilterValue, + 102, + 17, + 0, + 0, // Skip to: 7438 + /* 7421 */ MCD_OPC_CheckPredicate, + 14, + 41, + 13, + 0, // Skip to: 10795 + /* 7426 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 34, + 13, + 0, // Skip to: 10795 + /* 7433 */ MCD_OPC_Decode, + 152, + 15, + 141, + 1, // Opcode: NOGRK + /* 7438 */ MCD_OPC_FilterValue, + 103, + 17, + 0, + 0, // Skip to: 7460 + /* 7443 */ MCD_OPC_CheckPredicate, + 14, + 19, + 13, + 0, // Skip to: 10795 + /* 7448 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 12, + 13, + 0, // Skip to: 10795 + /* 7455 */ MCD_OPC_Decode, + 158, + 15, + 141, + 1, // Opcode: NXGRK + /* 7460 */ MCD_OPC_FilterValue, + 114, + 70, + 0, + 0, // Skip to: 7535 + /* 7465 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 7468 */ MCD_OPC_FilterValue, + 0, + 250, + 12, + 0, // Skip to: 10795 + /* 7473 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7476 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 7485 + /* 7481 */ MCD_OPC_Decode, + 145, + 9, + 8, // Opcode: CRTAsmH + /* 7485 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 7494 + /* 7490 */ MCD_OPC_Decode, + 147, + 9, + 8, // Opcode: CRTAsmL + /* 7494 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 7503 + /* 7499 */ MCD_OPC_Decode, + 149, + 9, + 8, // Opcode: CRTAsmLH + /* 7503 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 7512 + /* 7508 */ MCD_OPC_Decode, + 144, + 9, + 8, // Opcode: CRTAsmE + /* 7512 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 7521 + /* 7517 */ MCD_OPC_Decode, + 146, + 9, + 8, // Opcode: CRTAsmHE + /* 7521 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 7530 + /* 7526 */ MCD_OPC_Decode, + 148, + 9, + 8, // Opcode: CRTAsmLE + /* 7530 */ MCD_OPC_Decode, + 143, + 9, + 142, + 1, // Opcode: CRTAsm + /* 7535 */ MCD_OPC_FilterValue, + 115, + 70, + 0, + 0, // Skip to: 7610 + /* 7540 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 7543 */ MCD_OPC_FilterValue, + 0, + 175, + 12, + 0, // Skip to: 10795 + /* 7548 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7551 */ MCD_OPC_FilterValue, + 2, + 4, + 0, + 0, // Skip to: 7560 + /* 7556 */ MCD_OPC_Decode, + 202, + 8, + 8, // Opcode: CLRTAsmH + /* 7560 */ MCD_OPC_FilterValue, + 4, + 4, + 0, + 0, // Skip to: 7569 + /* 7565 */ MCD_OPC_Decode, + 204, + 8, + 8, // Opcode: CLRTAsmL + /* 7569 */ MCD_OPC_FilterValue, + 6, + 4, + 0, + 0, // Skip to: 7578 + /* 7574 */ MCD_OPC_Decode, + 206, + 8, + 8, // Opcode: CLRTAsmLH + /* 7578 */ MCD_OPC_FilterValue, + 8, + 4, + 0, + 0, // Skip to: 7587 + /* 7583 */ MCD_OPC_Decode, + 201, + 8, + 8, // Opcode: CLRTAsmE + /* 7587 */ MCD_OPC_FilterValue, + 10, + 4, + 0, + 0, // Skip to: 7596 + /* 7592 */ MCD_OPC_Decode, + 203, + 8, + 8, // Opcode: CLRTAsmHE + /* 7596 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 7605 + /* 7601 */ MCD_OPC_Decode, + 205, + 8, + 8, // Opcode: CLRTAsmLE + /* 7605 */ MCD_OPC_Decode, + 200, + 8, + 142, + 1, // Opcode: CLRTAsm + /* 7610 */ MCD_OPC_FilterValue, + 116, + 17, + 0, + 0, // Skip to: 7632 + /* 7615 */ MCD_OPC_CheckPredicate, + 14, + 103, + 12, + 0, // Skip to: 10795 + /* 7620 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 96, + 12, + 0, // Skip to: 10795 + /* 7627 */ MCD_OPC_Decode, + 151, + 15, + 143, + 1, // Opcode: NNRK + /* 7632 */ MCD_OPC_FilterValue, + 117, + 17, + 0, + 0, // Skip to: 7654 + /* 7637 */ MCD_OPC_CheckPredicate, + 14, + 81, + 12, + 0, // Skip to: 10795 + /* 7642 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 74, + 12, + 0, // Skip to: 10795 + /* 7649 */ MCD_OPC_Decode, + 164, + 15, + 143, + 1, // Opcode: OCRK + /* 7654 */ MCD_OPC_FilterValue, + 118, + 17, + 0, + 0, // Skip to: 7676 + /* 7659 */ MCD_OPC_CheckPredicate, + 14, + 59, + 12, + 0, // Skip to: 10795 + /* 7664 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 52, + 12, + 0, // Skip to: 10795 + /* 7671 */ MCD_OPC_Decode, + 154, + 15, + 143, + 1, // Opcode: NORK + /* 7676 */ MCD_OPC_FilterValue, + 119, + 17, + 0, + 0, // Skip to: 7698 + /* 7681 */ MCD_OPC_CheckPredicate, + 14, + 37, + 12, + 0, // Skip to: 10795 + /* 7686 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 30, + 12, + 0, // Skip to: 10795 + /* 7693 */ MCD_OPC_Decode, + 159, + 15, + 143, + 1, // Opcode: NXRK + /* 7698 */ MCD_OPC_FilterValue, + 128, + 1, + 12, + 0, + 0, // Skip to: 7716 + /* 7704 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 12, + 12, + 0, // Skip to: 10795 + /* 7711 */ MCD_OPC_Decode, + 138, + 15, + 136, + 1, // Opcode: NGR + /* 7716 */ MCD_OPC_FilterValue, + 129, + 1, + 12, + 0, + 0, // Skip to: 7734 + /* 7722 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 250, + 11, + 0, // Skip to: 10795 + /* 7729 */ MCD_OPC_Decode, + 166, + 15, + 136, + 1, // Opcode: OGR + /* 7734 */ MCD_OPC_FilterValue, + 130, + 1, + 12, + 0, + 0, // Skip to: 7752 + /* 7740 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 232, + 11, + 0, // Skip to: 10795 + /* 7747 */ MCD_OPC_Decode, + 168, + 24, + 136, + 1, // Opcode: XGR + /* 7752 */ MCD_OPC_FilterValue, + 131, + 1, + 12, + 0, + 0, // Skip to: 7770 + /* 7758 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 214, + 11, + 0, // Skip to: 10795 + /* 7765 */ MCD_OPC_Decode, + 148, + 10, + 144, + 1, // Opcode: FLOGR + /* 7770 */ MCD_OPC_FilterValue, + 132, + 1, + 11, + 0, + 0, // Skip to: 7787 + /* 7776 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 196, + 11, + 0, // Skip to: 10795 + /* 7783 */ MCD_OPC_Decode, + 235, + 11, + 62, // Opcode: LLGCR + /* 7787 */ MCD_OPC_FilterValue, + 133, + 1, + 11, + 0, + 0, // Skip to: 7804 + /* 7793 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 179, + 11, + 0, // Skip to: 10795 + /* 7800 */ MCD_OPC_Decode, + 242, + 11, + 62, // Opcode: LLGHR + /* 7804 */ MCD_OPC_FilterValue, + 134, + 1, + 11, + 0, + 0, // Skip to: 7821 + /* 7810 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 162, + 11, + 0, // Skip to: 10795 + /* 7817 */ MCD_OPC_Decode, + 198, + 14, + 69, // Opcode: MLGR + /* 7821 */ MCD_OPC_FilterValue, + 135, + 1, + 11, + 0, + 0, // Skip to: 7838 + /* 7827 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 145, + 11, + 0, // Skip to: 10795 + /* 7834 */ MCD_OPC_Decode, + 228, + 9, + 69, // Opcode: DLGR + /* 7838 */ MCD_OPC_FilterValue, + 136, + 1, + 12, + 0, + 0, // Skip to: 7856 + /* 7844 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 128, + 11, + 0, // Skip to: 10795 + /* 7851 */ MCD_OPC_Decode, + 156, + 4, + 136, + 1, // Opcode: ALCGR + /* 7856 */ MCD_OPC_FilterValue, + 137, + 1, + 12, + 0, + 0, // Skip to: 7874 + /* 7862 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 110, + 11, + 0, // Skip to: 10795 + /* 7869 */ MCD_OPC_Decode, + 210, + 16, + 136, + 1, // Opcode: SLBGR + /* 7874 */ MCD_OPC_FilterValue, + 138, + 1, + 11, + 0, + 0, // Skip to: 7891 + /* 7880 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 92, + 11, + 0, // Skip to: 10795 + /* 7887 */ MCD_OPC_Decode, + 161, + 9, + 69, // Opcode: CSPG + /* 7891 */ MCD_OPC_FilterValue, + 139, + 1, + 27, + 0, + 0, // Skip to: 7924 + /* 7897 */ MCD_OPC_CheckPredicate, + 15, + 12, + 0, + 0, // Skip to: 7914 + /* 7902 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 5, + 0, + 0, // Skip to: 7914 + /* 7909 */ MCD_OPC_Decode, + 211, + 15, + 141, + 1, // Opcode: RDPOpt + /* 7914 */ MCD_OPC_CheckPredicate, + 15, + 60, + 11, + 0, // Skip to: 10795 + /* 7919 */ MCD_OPC_Decode, + 210, + 15, + 145, + 1, // Opcode: RDP + /* 7924 */ MCD_OPC_FilterValue, + 141, + 1, + 11, + 0, + 0, // Skip to: 7941 + /* 7930 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 42, + 11, + 0, // Skip to: 10795 + /* 7937 */ MCD_OPC_Decode, + 253, + 9, + 8, // Opcode: EPSW + /* 7941 */ MCD_OPC_FilterValue, + 142, + 1, + 17, + 0, + 0, // Skip to: 7964 + /* 7947 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 5, + 0, + 0, // Skip to: 7959 + /* 7954 */ MCD_OPC_Decode, + 161, + 10, + 141, + 1, // Opcode: IDTEOpt + /* 7959 */ MCD_OPC_Decode, + 160, + 10, + 145, + 1, // Opcode: IDTE + /* 7964 */ MCD_OPC_FilterValue, + 143, + 1, + 27, + 0, + 0, // Skip to: 7997 + /* 7970 */ MCD_OPC_CheckPredicate, + 16, + 12, + 0, + 0, // Skip to: 7987 + /* 7975 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 5, + 0, + 0, // Skip to: 7987 + /* 7982 */ MCD_OPC_Decode, + 254, + 8, + 146, + 1, // Opcode: CRDTEOpt + /* 7987 */ MCD_OPC_CheckPredicate, + 16, + 243, + 10, + 0, // Skip to: 10795 + /* 7992 */ MCD_OPC_Decode, + 253, + 8, + 147, + 1, // Opcode: CRDTE + /* 7997 */ MCD_OPC_FilterValue, + 144, + 1, + 24, + 0, + 0, // Skip to: 8027 + /* 8003 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 8006 */ MCD_OPC_FilterValue, + 0, + 224, + 10, + 0, // Skip to: 10795 + /* 8011 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 8022 + /* 8018 */ MCD_OPC_Decode, + 194, + 18, + 72, // Opcode: TRTTOpt + /* 8022 */ MCD_OPC_Decode, + 193, + 18, + 148, + 1, // Opcode: TRTT + /* 8027 */ MCD_OPC_FilterValue, + 145, + 1, + 24, + 0, + 0, // Skip to: 8057 + /* 8033 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 8036 */ MCD_OPC_FilterValue, + 0, + 194, + 10, + 0, // Skip to: 10795 + /* 8041 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 8052 + /* 8048 */ MCD_OPC_Decode, + 189, + 18, + 72, // Opcode: TRTOOpt + /* 8052 */ MCD_OPC_Decode, + 188, + 18, + 148, + 1, // Opcode: TRTO + /* 8057 */ MCD_OPC_FilterValue, + 146, + 1, + 24, + 0, + 0, // Skip to: 8087 + /* 8063 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 8066 */ MCD_OPC_FilterValue, + 0, + 164, + 10, + 0, // Skip to: 10795 + /* 8071 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 8082 + /* 8078 */ MCD_OPC_Decode, + 184, + 18, + 72, // Opcode: TROTOpt + /* 8082 */ MCD_OPC_Decode, + 183, + 18, + 148, + 1, // Opcode: TROT + /* 8087 */ MCD_OPC_FilterValue, + 147, + 1, + 24, + 0, + 0, // Skip to: 8117 + /* 8093 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 8096 */ MCD_OPC_FilterValue, + 0, + 134, + 10, + 0, // Skip to: 10795 + /* 8101 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 8112 + /* 8108 */ MCD_OPC_Decode, + 182, + 18, + 72, // Opcode: TROOOpt + /* 8112 */ MCD_OPC_Decode, + 181, + 18, + 148, + 1, // Opcode: TROO + /* 8117 */ MCD_OPC_FilterValue, + 148, + 1, + 11, + 0, + 0, // Skip to: 8134 + /* 8123 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 105, + 10, + 0, // Skip to: 10795 + /* 8130 */ MCD_OPC_Decode, + 233, + 11, + 8, // Opcode: LLCR + /* 8134 */ MCD_OPC_FilterValue, + 149, + 1, + 11, + 0, + 0, // Skip to: 8151 + /* 8140 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 88, + 10, + 0, // Skip to: 10795 + /* 8147 */ MCD_OPC_Decode, + 249, + 11, + 8, // Opcode: LLHR + /* 8151 */ MCD_OPC_FilterValue, + 150, + 1, + 11, + 0, + 0, // Skip to: 8168 + /* 8157 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 71, + 10, + 0, // Skip to: 10795 + /* 8164 */ MCD_OPC_Decode, + 199, + 14, + 10, // Opcode: MLR + /* 8168 */ MCD_OPC_FilterValue, + 151, + 1, + 11, + 0, + 0, // Skip to: 8185 + /* 8174 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 54, + 10, + 0, // Skip to: 10795 + /* 8181 */ MCD_OPC_Decode, + 229, + 9, + 10, // Opcode: DLR + /* 8185 */ MCD_OPC_FilterValue, + 152, + 1, + 11, + 0, + 0, // Skip to: 8202 + /* 8191 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 37, + 10, + 0, // Skip to: 10795 + /* 8198 */ MCD_OPC_Decode, + 157, + 4, + 9, // Opcode: ALCR + /* 8202 */ MCD_OPC_FilterValue, + 153, + 1, + 11, + 0, + 0, // Skip to: 8219 + /* 8208 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 20, + 10, + 0, // Skip to: 10795 + /* 8215 */ MCD_OPC_Decode, + 211, + 16, + 9, // Opcode: SLBR + /* 8219 */ MCD_OPC_FilterValue, + 154, + 1, + 19, + 0, + 0, // Skip to: 8244 + /* 8225 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 3, + 10, + 0, // Skip to: 10795 + /* 8232 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 252, + 9, + 0, // Skip to: 10795 + /* 8239 */ MCD_OPC_Decode, + 250, + 9, + 149, + 1, // Opcode: EPAIR + /* 8244 */ MCD_OPC_FilterValue, + 155, + 1, + 19, + 0, + 0, // Skip to: 8269 + /* 8250 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 234, + 9, + 0, // Skip to: 10795 + /* 8257 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 227, + 9, + 0, // Skip to: 10795 + /* 8264 */ MCD_OPC_Decode, + 128, + 10, + 149, + 1, // Opcode: ESAIR + /* 8269 */ MCD_OPC_FilterValue, + 157, + 1, + 19, + 0, + 0, // Skip to: 8294 + /* 8275 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 209, + 9, + 0, // Skip to: 10795 + /* 8282 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 202, + 9, + 0, // Skip to: 10795 + /* 8289 */ MCD_OPC_Decode, + 131, + 10, + 150, + 1, // Opcode: ESEA + /* 8294 */ MCD_OPC_FilterValue, + 158, + 1, + 11, + 0, + 0, // Skip to: 8311 + /* 8300 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 184, + 9, + 0, // Skip to: 10795 + /* 8307 */ MCD_OPC_Decode, + 202, + 15, + 62, // Opcode: PTI + /* 8311 */ MCD_OPC_FilterValue, + 159, + 1, + 19, + 0, + 0, // Skip to: 8336 + /* 8317 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 167, + 9, + 0, // Skip to: 10795 + /* 8324 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 160, + 9, + 0, // Skip to: 10795 + /* 8331 */ MCD_OPC_Decode, + 138, + 17, + 149, + 1, // Opcode: SSAIR + /* 8336 */ MCD_OPC_FilterValue, + 162, + 1, + 19, + 0, + 0, // Skip to: 8361 + /* 8342 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 142, + 9, + 0, // Skip to: 10795 + /* 8349 */ MCD_OPC_CheckField, + 0, + 4, + 0, + 135, + 9, + 0, // Skip to: 10795 + /* 8356 */ MCD_OPC_Decode, + 200, + 15, + 151, + 1, // Opcode: PTF + /* 8361 */ MCD_OPC_FilterValue, + 170, + 1, + 5, + 0, + 0, // Skip to: 8372 + /* 8367 */ MCD_OPC_Decode, + 233, + 13, + 152, + 1, // Opcode: LPTEA + /* 8372 */ MCD_OPC_FilterValue, + 172, + 1, + 16, + 0, + 0, // Skip to: 8394 + /* 8378 */ MCD_OPC_CheckPredicate, + 17, + 108, + 9, + 0, // Skip to: 10795 + /* 8383 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 101, + 9, + 0, // Skip to: 10795 + /* 8390 */ MCD_OPC_Decode, + 175, + 10, + 62, // Opcode: IRBM + /* 8394 */ MCD_OPC_FilterValue, + 174, + 1, + 16, + 0, + 0, // Skip to: 8416 + /* 8400 */ MCD_OPC_CheckPredicate, + 18, + 86, + 9, + 0, // Skip to: 10795 + /* 8405 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 79, + 9, + 0, // Skip to: 10795 + /* 8412 */ MCD_OPC_Decode, + 223, + 15, + 62, // Opcode: RRBM + /* 8416 */ MCD_OPC_FilterValue, + 175, + 1, + 12, + 0, + 0, // Skip to: 8434 + /* 8422 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 62, + 9, + 0, // Skip to: 10795 + /* 8429 */ MCD_OPC_Decode, + 186, + 15, + 153, + 1, // Opcode: PFMF + /* 8434 */ MCD_OPC_FilterValue, + 176, + 1, + 23, + 0, + 0, // Skip to: 8463 + /* 8440 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 8443 */ MCD_OPC_FilterValue, + 0, + 43, + 9, + 0, // Skip to: 10795 + /* 8448 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 8459 + /* 8455 */ MCD_OPC_Decode, + 168, + 9, + 7, // Opcode: CU14Opt + /* 8459 */ MCD_OPC_Decode, + 167, + 9, + 73, // Opcode: CU14 + /* 8463 */ MCD_OPC_FilterValue, + 177, + 1, + 23, + 0, + 0, // Skip to: 8492 + /* 8469 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 8472 */ MCD_OPC_FilterValue, + 0, + 14, + 9, + 0, // Skip to: 10795 + /* 8477 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 8488 + /* 8484 */ MCD_OPC_Decode, + 172, + 9, + 7, // Opcode: CU24Opt + /* 8488 */ MCD_OPC_Decode, + 171, + 9, + 73, // Opcode: CU24 + /* 8492 */ MCD_OPC_FilterValue, + 178, + 1, + 11, + 0, + 0, // Skip to: 8509 + /* 8498 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 242, + 8, + 0, // Skip to: 10795 + /* 8505 */ MCD_OPC_Decode, + 173, + 9, + 7, // Opcode: CU41 + /* 8509 */ MCD_OPC_FilterValue, + 179, + 1, + 11, + 0, + 0, // Skip to: 8526 + /* 8515 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 225, + 8, + 0, // Skip to: 10795 + /* 8522 */ MCD_OPC_Decode, + 174, + 9, + 7, // Opcode: CU42 + /* 8526 */ MCD_OPC_FilterValue, + 189, + 1, + 25, + 0, + 0, // Skip to: 8557 + /* 8532 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 8535 */ MCD_OPC_FilterValue, + 0, + 207, + 8, + 0, // Skip to: 10795 + /* 8540 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 5, + 0, + 0, // Skip to: 8552 + /* 8547 */ MCD_OPC_Decode, + 192, + 18, + 154, + 1, // Opcode: TRTREOpt + /* 8552 */ MCD_OPC_Decode, + 191, + 18, + 155, + 1, // Opcode: TRTRE + /* 8557 */ MCD_OPC_FilterValue, + 190, + 1, + 11, + 0, + 0, // Skip to: 8574 + /* 8563 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 177, + 8, + 0, // Skip to: 10795 + /* 8570 */ MCD_OPC_Decode, + 136, + 17, + 70, // Opcode: SRSTU + /* 8574 */ MCD_OPC_FilterValue, + 191, + 1, + 25, + 0, + 0, // Skip to: 8605 + /* 8580 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 8583 */ MCD_OPC_FilterValue, + 0, + 159, + 8, + 0, // Skip to: 10795 + /* 8588 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 5, + 0, + 0, // Skip to: 8600 + /* 8595 */ MCD_OPC_Decode, + 187, + 18, + 154, + 1, // Opcode: TRTEOpt + /* 8600 */ MCD_OPC_Decode, + 186, + 18, + 155, + 1, // Opcode: TRTE + /* 8605 */ MCD_OPC_FilterValue, + 192, + 1, + 223, + 0, + 0, // Skip to: 8834 + /* 8611 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 8614 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8629 + /* 8619 */ MCD_OPC_CheckPredicate, + 14, + 200, + 0, + 0, // Skip to: 8824 + /* 8624 */ MCD_OPC_Decode, + 141, + 16, + 156, + 1, // Opcode: SELFHRAsmO + /* 8629 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8644 + /* 8634 */ MCD_OPC_CheckPredicate, + 14, + 185, + 0, + 0, // Skip to: 8824 + /* 8639 */ MCD_OPC_Decode, + 253, + 15, + 156, + 1, // Opcode: SELFHRAsmH + /* 8644 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8659 + /* 8649 */ MCD_OPC_CheckPredicate, + 14, + 170, + 0, + 0, // Skip to: 8824 + /* 8654 */ MCD_OPC_Decode, + 135, + 16, + 156, + 1, // Opcode: SELFHRAsmNLE + /* 8659 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 8674 + /* 8664 */ MCD_OPC_CheckPredicate, + 14, + 155, + 0, + 0, // Skip to: 8824 + /* 8669 */ MCD_OPC_Decode, + 255, + 15, + 156, + 1, // Opcode: SELFHRAsmL + /* 8674 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 8689 + /* 8679 */ MCD_OPC_CheckPredicate, + 14, + 140, + 0, + 0, // Skip to: 8824 + /* 8684 */ MCD_OPC_Decode, + 133, + 16, + 156, + 1, // Opcode: SELFHRAsmNHE + /* 8689 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 8704 + /* 8694 */ MCD_OPC_CheckPredicate, + 14, + 125, + 0, + 0, // Skip to: 8824 + /* 8699 */ MCD_OPC_Decode, + 129, + 16, + 156, + 1, // Opcode: SELFHRAsmLH + /* 8704 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 8719 + /* 8709 */ MCD_OPC_CheckPredicate, + 14, + 110, + 0, + 0, // Skip to: 8824 + /* 8714 */ MCD_OPC_Decode, + 131, + 16, + 156, + 1, // Opcode: SELFHRAsmNE + /* 8719 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 8734 + /* 8724 */ MCD_OPC_CheckPredicate, + 14, + 95, + 0, + 0, // Skip to: 8824 + /* 8729 */ MCD_OPC_Decode, + 252, + 15, + 156, + 1, // Opcode: SELFHRAsmE + /* 8734 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 8749 + /* 8739 */ MCD_OPC_CheckPredicate, + 14, + 80, + 0, + 0, // Skip to: 8824 + /* 8744 */ MCD_OPC_Decode, + 136, + 16, + 156, + 1, // Opcode: SELFHRAsmNLH + /* 8749 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 8764 + /* 8754 */ MCD_OPC_CheckPredicate, + 14, + 65, + 0, + 0, // Skip to: 8824 + /* 8759 */ MCD_OPC_Decode, + 254, + 15, + 156, + 1, // Opcode: SELFHRAsmHE + /* 8764 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 8779 + /* 8769 */ MCD_OPC_CheckPredicate, + 14, + 50, + 0, + 0, // Skip to: 8824 + /* 8774 */ MCD_OPC_Decode, + 134, + 16, + 156, + 1, // Opcode: SELFHRAsmNL + /* 8779 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 8794 + /* 8784 */ MCD_OPC_CheckPredicate, + 14, + 35, + 0, + 0, // Skip to: 8824 + /* 8789 */ MCD_OPC_Decode, + 128, + 16, + 156, + 1, // Opcode: SELFHRAsmLE + /* 8794 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 8809 + /* 8799 */ MCD_OPC_CheckPredicate, + 14, + 20, + 0, + 0, // Skip to: 8824 + /* 8804 */ MCD_OPC_Decode, + 132, + 16, + 156, + 1, // Opcode: SELFHRAsmNH + /* 8809 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 8824 + /* 8814 */ MCD_OPC_CheckPredicate, + 14, + 5, + 0, + 0, // Skip to: 8824 + /* 8819 */ MCD_OPC_Decode, + 138, + 16, + 156, + 1, // Opcode: SELFHRAsmNO + /* 8824 */ MCD_OPC_CheckPredicate, + 14, + 174, + 7, + 0, // Skip to: 10795 + /* 8829 */ MCD_OPC_Decode, + 251, + 15, + 157, + 1, // Opcode: SELFHRAsm + /* 8834 */ MCD_OPC_FilterValue, + 200, + 1, + 17, + 0, + 0, // Skip to: 8857 + /* 8840 */ MCD_OPC_CheckPredicate, + 19, + 158, + 7, + 0, // Skip to: 10795 + /* 8845 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 151, + 7, + 0, // Skip to: 10795 + /* 8852 */ MCD_OPC_Decode, + 147, + 4, + 158, + 1, // Opcode: AHHHR + /* 8857 */ MCD_OPC_FilterValue, + 201, + 1, + 17, + 0, + 0, // Skip to: 8880 + /* 8863 */ MCD_OPC_CheckPredicate, + 19, + 135, + 7, + 0, // Skip to: 10795 + /* 8868 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 128, + 7, + 0, // Skip to: 10795 + /* 8875 */ MCD_OPC_Decode, + 198, + 16, + 158, + 1, // Opcode: SHHHR + /* 8880 */ MCD_OPC_FilterValue, + 202, + 1, + 17, + 0, + 0, // Skip to: 8903 + /* 8886 */ MCD_OPC_CheckPredicate, + 19, + 112, + 7, + 0, // Skip to: 10795 + /* 8891 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 105, + 7, + 0, // Skip to: 10795 + /* 8898 */ MCD_OPC_Decode, + 167, + 4, + 158, + 1, // Opcode: ALHHHR + /* 8903 */ MCD_OPC_FilterValue, + 203, + 1, + 17, + 0, + 0, // Skip to: 8926 + /* 8909 */ MCD_OPC_CheckPredicate, + 19, + 89, + 7, + 0, // Skip to: 10795 + /* 8914 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 82, + 7, + 0, // Skip to: 10795 + /* 8921 */ MCD_OPC_Decode, + 222, + 16, + 158, + 1, // Opcode: SLHHHR + /* 8926 */ MCD_OPC_FilterValue, + 205, + 1, + 17, + 0, + 0, // Skip to: 8949 + /* 8932 */ MCD_OPC_CheckPredicate, + 19, + 66, + 7, + 0, // Skip to: 10795 + /* 8937 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 59, + 7, + 0, // Skip to: 10795 + /* 8944 */ MCD_OPC_Decode, + 197, + 6, + 159, + 1, // Opcode: CHHR + /* 8949 */ MCD_OPC_FilterValue, + 207, + 1, + 17, + 0, + 0, // Skip to: 8972 + /* 8955 */ MCD_OPC_CheckPredicate, + 19, + 43, + 7, + 0, // Skip to: 10795 + /* 8960 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 36, + 7, + 0, // Skip to: 10795 + /* 8967 */ MCD_OPC_Decode, + 131, + 8, + 159, + 1, // Opcode: CLHHR + /* 8972 */ MCD_OPC_FilterValue, + 216, + 1, + 17, + 0, + 0, // Skip to: 8995 + /* 8978 */ MCD_OPC_CheckPredicate, + 19, + 20, + 7, + 0, // Skip to: 10795 + /* 8983 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 13, + 7, + 0, // Skip to: 10795 + /* 8990 */ MCD_OPC_Decode, + 148, + 4, + 160, + 1, // Opcode: AHHLR + /* 8995 */ MCD_OPC_FilterValue, + 217, + 1, + 17, + 0, + 0, // Skip to: 9018 + /* 9001 */ MCD_OPC_CheckPredicate, + 19, + 253, + 6, + 0, // Skip to: 10795 + /* 9006 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 246, + 6, + 0, // Skip to: 10795 + /* 9013 */ MCD_OPC_Decode, + 199, + 16, + 160, + 1, // Opcode: SHHLR + /* 9018 */ MCD_OPC_FilterValue, + 218, + 1, + 17, + 0, + 0, // Skip to: 9041 + /* 9024 */ MCD_OPC_CheckPredicate, + 19, + 230, + 6, + 0, // Skip to: 10795 + /* 9029 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 223, + 6, + 0, // Skip to: 10795 + /* 9036 */ MCD_OPC_Decode, + 168, + 4, + 160, + 1, // Opcode: ALHHLR + /* 9041 */ MCD_OPC_FilterValue, + 219, + 1, + 17, + 0, + 0, // Skip to: 9064 + /* 9047 */ MCD_OPC_CheckPredicate, + 19, + 207, + 6, + 0, // Skip to: 10795 + /* 9052 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 200, + 6, + 0, // Skip to: 10795 + /* 9059 */ MCD_OPC_Decode, + 223, + 16, + 160, + 1, // Opcode: SLHHLR + /* 9064 */ MCD_OPC_FilterValue, + 221, + 1, + 17, + 0, + 0, // Skip to: 9087 + /* 9070 */ MCD_OPC_CheckPredicate, + 19, + 184, + 6, + 0, // Skip to: 10795 + /* 9075 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 177, + 6, + 0, // Skip to: 10795 + /* 9082 */ MCD_OPC_Decode, + 200, + 6, + 161, + 1, // Opcode: CHLR + /* 9087 */ MCD_OPC_FilterValue, + 223, + 1, + 17, + 0, + 0, // Skip to: 9110 + /* 9093 */ MCD_OPC_CheckPredicate, + 19, + 161, + 6, + 0, // Skip to: 10795 + /* 9098 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 154, + 6, + 0, // Skip to: 10795 + /* 9105 */ MCD_OPC_Decode, + 133, + 8, + 161, + 1, // Opcode: CLHLR + /* 9110 */ MCD_OPC_FilterValue, + 224, + 1, + 231, + 0, + 0, // Skip to: 9347 + /* 9116 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 9119 */ MCD_OPC_FilterValue, + 0, + 135, + 6, + 0, // Skip to: 10795 + /* 9124 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 9127 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9142 + /* 9132 */ MCD_OPC_CheckPredicate, + 20, + 200, + 0, + 0, // Skip to: 9337 + /* 9137 */ MCD_OPC_Decode, + 209, + 12, + 162, + 1, // Opcode: LOCFHRAsmO + /* 9142 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9157 + /* 9147 */ MCD_OPC_CheckPredicate, + 20, + 185, + 0, + 0, // Skip to: 9337 + /* 9152 */ MCD_OPC_Decode, + 193, + 12, + 162, + 1, // Opcode: LOCFHRAsmH + /* 9157 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 9172 + /* 9162 */ MCD_OPC_CheckPredicate, + 20, + 170, + 0, + 0, // Skip to: 9337 + /* 9167 */ MCD_OPC_Decode, + 203, + 12, + 162, + 1, // Opcode: LOCFHRAsmNLE + /* 9172 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 9187 + /* 9177 */ MCD_OPC_CheckPredicate, + 20, + 155, + 0, + 0, // Skip to: 9337 + /* 9182 */ MCD_OPC_Decode, + 195, + 12, + 162, + 1, // Opcode: LOCFHRAsmL + /* 9187 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 9202 + /* 9192 */ MCD_OPC_CheckPredicate, + 20, + 140, + 0, + 0, // Skip to: 9337 + /* 9197 */ MCD_OPC_Decode, + 201, + 12, + 162, + 1, // Opcode: LOCFHRAsmNHE + /* 9202 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 9217 + /* 9207 */ MCD_OPC_CheckPredicate, + 20, + 125, + 0, + 0, // Skip to: 9337 + /* 9212 */ MCD_OPC_Decode, + 197, + 12, + 162, + 1, // Opcode: LOCFHRAsmLH + /* 9217 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 9232 + /* 9222 */ MCD_OPC_CheckPredicate, + 20, + 110, + 0, + 0, // Skip to: 9337 + /* 9227 */ MCD_OPC_Decode, + 199, + 12, + 162, + 1, // Opcode: LOCFHRAsmNE + /* 9232 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 9247 + /* 9237 */ MCD_OPC_CheckPredicate, + 20, + 95, + 0, + 0, // Skip to: 9337 + /* 9242 */ MCD_OPC_Decode, + 192, + 12, + 162, + 1, // Opcode: LOCFHRAsmE + /* 9247 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 9262 + /* 9252 */ MCD_OPC_CheckPredicate, + 20, + 80, + 0, + 0, // Skip to: 9337 + /* 9257 */ MCD_OPC_Decode, + 204, + 12, + 162, + 1, // Opcode: LOCFHRAsmNLH + /* 9262 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 9277 + /* 9267 */ MCD_OPC_CheckPredicate, + 20, + 65, + 0, + 0, // Skip to: 9337 + /* 9272 */ MCD_OPC_Decode, + 194, + 12, + 162, + 1, // Opcode: LOCFHRAsmHE + /* 9277 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 9292 + /* 9282 */ MCD_OPC_CheckPredicate, + 20, + 50, + 0, + 0, // Skip to: 9337 + /* 9287 */ MCD_OPC_Decode, + 202, + 12, + 162, + 1, // Opcode: LOCFHRAsmNL + /* 9292 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 9307 + /* 9297 */ MCD_OPC_CheckPredicate, + 20, + 35, + 0, + 0, // Skip to: 9337 + /* 9302 */ MCD_OPC_Decode, + 196, + 12, + 162, + 1, // Opcode: LOCFHRAsmLE + /* 9307 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 9322 + /* 9312 */ MCD_OPC_CheckPredicate, + 20, + 20, + 0, + 0, // Skip to: 9337 + /* 9317 */ MCD_OPC_Decode, + 200, + 12, + 162, + 1, // Opcode: LOCFHRAsmNH + /* 9322 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9337 + /* 9327 */ MCD_OPC_CheckPredicate, + 20, + 5, + 0, + 0, // Skip to: 9337 + /* 9332 */ MCD_OPC_Decode, + 206, + 12, + 162, + 1, // Opcode: LOCFHRAsmNO + /* 9337 */ MCD_OPC_CheckPredicate, + 20, + 173, + 5, + 0, // Skip to: 10795 + /* 9342 */ MCD_OPC_Decode, + 191, + 12, + 163, + 1, // Opcode: LOCFHRAsm + /* 9347 */ MCD_OPC_FilterValue, + 225, + 1, + 33, + 0, + 0, // Skip to: 9386 + /* 9353 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 9356 */ MCD_OPC_FilterValue, + 0, + 154, + 5, + 0, // Skip to: 10795 + /* 9361 */ MCD_OPC_CheckPredicate, + 21, + 11, + 0, + 0, // Skip to: 9377 + /* 9366 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 4, + 0, + 0, // Skip to: 9377 + /* 9373 */ MCD_OPC_Decode, + 193, + 15, + 62, // Opcode: POPCNT + /* 9377 */ MCD_OPC_CheckPredicate, + 14, + 133, + 5, + 0, // Skip to: 10795 + /* 9382 */ MCD_OPC_Decode, + 194, + 15, + 74, // Opcode: POPCNTOpt + /* 9386 */ MCD_OPC_FilterValue, + 226, + 1, + 231, + 0, + 0, // Skip to: 9623 + /* 9392 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 9395 */ MCD_OPC_FilterValue, + 0, + 115, + 5, + 0, // Skip to: 10795 + /* 9400 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 9403 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9418 + /* 9408 */ MCD_OPC_CheckPredicate, + 22, + 200, + 0, + 0, // Skip to: 9613 + /* 9413 */ MCD_OPC_Decode, + 147, + 13, + 136, + 1, // Opcode: LOCGRAsmO + /* 9418 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9433 + /* 9423 */ MCD_OPC_CheckPredicate, + 22, + 185, + 0, + 0, // Skip to: 9613 + /* 9428 */ MCD_OPC_Decode, + 131, + 13, + 136, + 1, // Opcode: LOCGRAsmH + /* 9433 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 9448 + /* 9438 */ MCD_OPC_CheckPredicate, + 22, + 170, + 0, + 0, // Skip to: 9613 + /* 9443 */ MCD_OPC_Decode, + 141, + 13, + 136, + 1, // Opcode: LOCGRAsmNLE + /* 9448 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 9463 + /* 9453 */ MCD_OPC_CheckPredicate, + 22, + 155, + 0, + 0, // Skip to: 9613 + /* 9458 */ MCD_OPC_Decode, + 133, + 13, + 136, + 1, // Opcode: LOCGRAsmL + /* 9463 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 9478 + /* 9468 */ MCD_OPC_CheckPredicate, + 22, + 140, + 0, + 0, // Skip to: 9613 + /* 9473 */ MCD_OPC_Decode, + 139, + 13, + 136, + 1, // Opcode: LOCGRAsmNHE + /* 9478 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 9493 + /* 9483 */ MCD_OPC_CheckPredicate, + 22, + 125, + 0, + 0, // Skip to: 9613 + /* 9488 */ MCD_OPC_Decode, + 135, + 13, + 136, + 1, // Opcode: LOCGRAsmLH + /* 9493 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 9508 + /* 9498 */ MCD_OPC_CheckPredicate, + 22, + 110, + 0, + 0, // Skip to: 9613 + /* 9503 */ MCD_OPC_Decode, + 137, + 13, + 136, + 1, // Opcode: LOCGRAsmNE + /* 9508 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 9523 + /* 9513 */ MCD_OPC_CheckPredicate, + 22, + 95, + 0, + 0, // Skip to: 9613 + /* 9518 */ MCD_OPC_Decode, + 130, + 13, + 136, + 1, // Opcode: LOCGRAsmE + /* 9523 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 9538 + /* 9528 */ MCD_OPC_CheckPredicate, + 22, + 80, + 0, + 0, // Skip to: 9613 + /* 9533 */ MCD_OPC_Decode, + 142, + 13, + 136, + 1, // Opcode: LOCGRAsmNLH + /* 9538 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 9553 + /* 9543 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 9613 + /* 9548 */ MCD_OPC_Decode, + 132, + 13, + 136, + 1, // Opcode: LOCGRAsmHE + /* 9553 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 9568 + /* 9558 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 9613 + /* 9563 */ MCD_OPC_Decode, + 140, + 13, + 136, + 1, // Opcode: LOCGRAsmNL + /* 9568 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 9583 + /* 9573 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 9613 + /* 9578 */ MCD_OPC_Decode, + 134, + 13, + 136, + 1, // Opcode: LOCGRAsmLE + /* 9583 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 9598 + /* 9588 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 9613 + /* 9593 */ MCD_OPC_Decode, + 138, + 13, + 136, + 1, // Opcode: LOCGRAsmNH + /* 9598 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9613 + /* 9603 */ MCD_OPC_CheckPredicate, + 22, + 5, + 0, + 0, // Skip to: 9613 + /* 9608 */ MCD_OPC_Decode, + 144, + 13, + 136, + 1, // Opcode: LOCGRAsmNO + /* 9613 */ MCD_OPC_CheckPredicate, + 22, + 153, + 4, + 0, // Skip to: 10795 + /* 9618 */ MCD_OPC_Decode, + 129, + 13, + 164, + 1, // Opcode: LOCGRAsm + /* 9623 */ MCD_OPC_FilterValue, + 227, + 1, + 223, + 0, + 0, // Skip to: 9852 + /* 9629 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 9632 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9647 + /* 9637 */ MCD_OPC_CheckPredicate, + 14, + 200, + 0, + 0, // Skip to: 9842 + /* 9642 */ MCD_OPC_Decode, + 163, + 16, + 165, + 1, // Opcode: SELGRAsmO + /* 9647 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9662 + /* 9652 */ MCD_OPC_CheckPredicate, + 14, + 185, + 0, + 0, // Skip to: 9842 + /* 9657 */ MCD_OPC_Decode, + 147, + 16, + 165, + 1, // Opcode: SELGRAsmH + /* 9662 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 9677 + /* 9667 */ MCD_OPC_CheckPredicate, + 14, + 170, + 0, + 0, // Skip to: 9842 + /* 9672 */ MCD_OPC_Decode, + 157, + 16, + 165, + 1, // Opcode: SELGRAsmNLE + /* 9677 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 9692 + /* 9682 */ MCD_OPC_CheckPredicate, + 14, + 155, + 0, + 0, // Skip to: 9842 + /* 9687 */ MCD_OPC_Decode, + 149, + 16, + 165, + 1, // Opcode: SELGRAsmL + /* 9692 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 9707 + /* 9697 */ MCD_OPC_CheckPredicate, + 14, + 140, + 0, + 0, // Skip to: 9842 + /* 9702 */ MCD_OPC_Decode, + 155, + 16, + 165, + 1, // Opcode: SELGRAsmNHE + /* 9707 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 9722 + /* 9712 */ MCD_OPC_CheckPredicate, + 14, + 125, + 0, + 0, // Skip to: 9842 + /* 9717 */ MCD_OPC_Decode, + 151, + 16, + 165, + 1, // Opcode: SELGRAsmLH + /* 9722 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 9737 + /* 9727 */ MCD_OPC_CheckPredicate, + 14, + 110, + 0, + 0, // Skip to: 9842 + /* 9732 */ MCD_OPC_Decode, + 153, + 16, + 165, + 1, // Opcode: SELGRAsmNE + /* 9737 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 9752 + /* 9742 */ MCD_OPC_CheckPredicate, + 14, + 95, + 0, + 0, // Skip to: 9842 + /* 9747 */ MCD_OPC_Decode, + 146, + 16, + 165, + 1, // Opcode: SELGRAsmE + /* 9752 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 9767 + /* 9757 */ MCD_OPC_CheckPredicate, + 14, + 80, + 0, + 0, // Skip to: 9842 + /* 9762 */ MCD_OPC_Decode, + 158, + 16, + 165, + 1, // Opcode: SELGRAsmNLH + /* 9767 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 9782 + /* 9772 */ MCD_OPC_CheckPredicate, + 14, + 65, + 0, + 0, // Skip to: 9842 + /* 9777 */ MCD_OPC_Decode, + 148, + 16, + 165, + 1, // Opcode: SELGRAsmHE + /* 9782 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 9797 + /* 9787 */ MCD_OPC_CheckPredicate, + 14, + 50, + 0, + 0, // Skip to: 9842 + /* 9792 */ MCD_OPC_Decode, + 156, + 16, + 165, + 1, // Opcode: SELGRAsmNL + /* 9797 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 9812 + /* 9802 */ MCD_OPC_CheckPredicate, + 14, + 35, + 0, + 0, // Skip to: 9842 + /* 9807 */ MCD_OPC_Decode, + 150, + 16, + 165, + 1, // Opcode: SELGRAsmLE + /* 9812 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 9827 + /* 9817 */ MCD_OPC_CheckPredicate, + 14, + 20, + 0, + 0, // Skip to: 9842 + /* 9822 */ MCD_OPC_Decode, + 154, + 16, + 165, + 1, // Opcode: SELGRAsmNH + /* 9827 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 9842 + /* 9832 */ MCD_OPC_CheckPredicate, + 14, + 5, + 0, + 0, // Skip to: 9842 + /* 9837 */ MCD_OPC_Decode, + 160, + 16, + 165, + 1, // Opcode: SELGRAsmNO + /* 9842 */ MCD_OPC_CheckPredicate, + 14, + 180, + 3, + 0, // Skip to: 10795 + /* 9847 */ MCD_OPC_Decode, + 145, + 16, + 166, + 1, // Opcode: SELGRAsm + /* 9852 */ MCD_OPC_FilterValue, + 228, + 1, + 17, + 0, + 0, // Skip to: 9875 + /* 9858 */ MCD_OPC_CheckPredicate, + 23, + 164, + 3, + 0, // Skip to: 10795 + /* 9863 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 157, + 3, + 0, // Skip to: 10795 + /* 9870 */ MCD_OPC_Decode, + 139, + 15, + 141, + 1, // Opcode: NGRK + /* 9875 */ MCD_OPC_FilterValue, + 229, + 1, + 17, + 0, + 0, // Skip to: 9898 + /* 9881 */ MCD_OPC_CheckPredicate, + 14, + 141, + 3, + 0, // Skip to: 10795 + /* 9886 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 134, + 3, + 0, // Skip to: 10795 + /* 9893 */ MCD_OPC_Decode, + 135, + 15, + 141, + 1, // Opcode: NCGRK + /* 9898 */ MCD_OPC_FilterValue, + 230, + 1, + 17, + 0, + 0, // Skip to: 9921 + /* 9904 */ MCD_OPC_CheckPredicate, + 23, + 118, + 3, + 0, // Skip to: 10795 + /* 9909 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 111, + 3, + 0, // Skip to: 10795 + /* 9916 */ MCD_OPC_Decode, + 167, + 15, + 141, + 1, // Opcode: OGRK + /* 9921 */ MCD_OPC_FilterValue, + 231, + 1, + 17, + 0, + 0, // Skip to: 9944 + /* 9927 */ MCD_OPC_CheckPredicate, + 23, + 95, + 3, + 0, // Skip to: 10795 + /* 9932 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 88, + 3, + 0, // Skip to: 10795 + /* 9939 */ MCD_OPC_Decode, + 169, + 24, + 141, + 1, // Opcode: XGRK + /* 9944 */ MCD_OPC_FilterValue, + 232, + 1, + 17, + 0, + 0, // Skip to: 9967 + /* 9950 */ MCD_OPC_CheckPredicate, + 23, + 72, + 3, + 0, // Skip to: 10795 + /* 9955 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 65, + 3, + 0, // Skip to: 10795 + /* 9962 */ MCD_OPC_Decode, + 144, + 4, + 141, + 1, // Opcode: AGRK + /* 9967 */ MCD_OPC_FilterValue, + 233, + 1, + 17, + 0, + 0, // Skip to: 9990 + /* 9973 */ MCD_OPC_CheckPredicate, + 23, + 49, + 3, + 0, // Skip to: 10795 + /* 9978 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 42, + 3, + 0, // Skip to: 10795 + /* 9985 */ MCD_OPC_Decode, + 196, + 16, + 141, + 1, // Opcode: SGRK + /* 9990 */ MCD_OPC_FilterValue, + 234, + 1, + 17, + 0, + 0, // Skip to: 10013 + /* 9996 */ MCD_OPC_CheckPredicate, + 23, + 26, + 3, + 0, // Skip to: 10795 + /* 10001 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 19, + 3, + 0, // Skip to: 10795 + /* 10008 */ MCD_OPC_Decode, + 165, + 4, + 141, + 1, // Opcode: ALGRK + /* 10013 */ MCD_OPC_FilterValue, + 235, + 1, + 17, + 0, + 0, // Skip to: 10036 + /* 10019 */ MCD_OPC_CheckPredicate, + 23, + 3, + 3, + 0, // Skip to: 10795 + /* 10024 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 252, + 2, + 0, // Skip to: 10795 + /* 10031 */ MCD_OPC_Decode, + 221, + 16, + 141, + 1, // Opcode: SLGRK + /* 10036 */ MCD_OPC_FilterValue, + 236, + 1, + 17, + 0, + 0, // Skip to: 10059 + /* 10042 */ MCD_OPC_CheckPredicate, + 24, + 236, + 2, + 0, // Skip to: 10795 + /* 10047 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 229, + 2, + 0, // Skip to: 10795 + /* 10054 */ MCD_OPC_Decode, + 192, + 14, + 167, + 1, // Opcode: MGRK + /* 10059 */ MCD_OPC_FilterValue, + 237, + 1, + 17, + 0, + 0, // Skip to: 10082 + /* 10065 */ MCD_OPC_CheckPredicate, + 24, + 213, + 2, + 0, // Skip to: 10795 + /* 10070 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 206, + 2, + 0, // Skip to: 10795 + /* 10077 */ MCD_OPC_Decode, + 220, + 14, + 141, + 1, // Opcode: MSGRKC + /* 10082 */ MCD_OPC_FilterValue, + 240, + 1, + 223, + 0, + 0, // Skip to: 10311 + /* 10088 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 10091 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10106 + /* 10096 */ MCD_OPC_CheckPredicate, + 14, + 200, + 0, + 0, // Skip to: 10301 + /* 10101 */ MCD_OPC_Decode, + 185, + 16, + 168, + 1, // Opcode: SELRAsmO + /* 10106 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10121 + /* 10111 */ MCD_OPC_CheckPredicate, + 14, + 185, + 0, + 0, // Skip to: 10301 + /* 10116 */ MCD_OPC_Decode, + 169, + 16, + 168, + 1, // Opcode: SELRAsmH + /* 10121 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 10136 + /* 10126 */ MCD_OPC_CheckPredicate, + 14, + 170, + 0, + 0, // Skip to: 10301 + /* 10131 */ MCD_OPC_Decode, + 179, + 16, + 168, + 1, // Opcode: SELRAsmNLE + /* 10136 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 10151 + /* 10141 */ MCD_OPC_CheckPredicate, + 14, + 155, + 0, + 0, // Skip to: 10301 + /* 10146 */ MCD_OPC_Decode, + 171, + 16, + 168, + 1, // Opcode: SELRAsmL + /* 10151 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 10166 + /* 10156 */ MCD_OPC_CheckPredicate, + 14, + 140, + 0, + 0, // Skip to: 10301 + /* 10161 */ MCD_OPC_Decode, + 177, + 16, + 168, + 1, // Opcode: SELRAsmNHE + /* 10166 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 10181 + /* 10171 */ MCD_OPC_CheckPredicate, + 14, + 125, + 0, + 0, // Skip to: 10301 + /* 10176 */ MCD_OPC_Decode, + 173, + 16, + 168, + 1, // Opcode: SELRAsmLH + /* 10181 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 10196 + /* 10186 */ MCD_OPC_CheckPredicate, + 14, + 110, + 0, + 0, // Skip to: 10301 + /* 10191 */ MCD_OPC_Decode, + 175, + 16, + 168, + 1, // Opcode: SELRAsmNE + /* 10196 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 10211 + /* 10201 */ MCD_OPC_CheckPredicate, + 14, + 95, + 0, + 0, // Skip to: 10301 + /* 10206 */ MCD_OPC_Decode, + 168, + 16, + 168, + 1, // Opcode: SELRAsmE + /* 10211 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 10226 + /* 10216 */ MCD_OPC_CheckPredicate, + 14, + 80, + 0, + 0, // Skip to: 10301 + /* 10221 */ MCD_OPC_Decode, + 180, + 16, + 168, + 1, // Opcode: SELRAsmNLH + /* 10226 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 10241 + /* 10231 */ MCD_OPC_CheckPredicate, + 14, + 65, + 0, + 0, // Skip to: 10301 + /* 10236 */ MCD_OPC_Decode, + 170, + 16, + 168, + 1, // Opcode: SELRAsmHE + /* 10241 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 10256 + /* 10246 */ MCD_OPC_CheckPredicate, + 14, + 50, + 0, + 0, // Skip to: 10301 + /* 10251 */ MCD_OPC_Decode, + 178, + 16, + 168, + 1, // Opcode: SELRAsmNL + /* 10256 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 10271 + /* 10261 */ MCD_OPC_CheckPredicate, + 14, + 35, + 0, + 0, // Skip to: 10301 + /* 10266 */ MCD_OPC_Decode, + 172, + 16, + 168, + 1, // Opcode: SELRAsmLE + /* 10271 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 10286 + /* 10276 */ MCD_OPC_CheckPredicate, + 14, + 20, + 0, + 0, // Skip to: 10301 + /* 10281 */ MCD_OPC_Decode, + 176, + 16, + 168, + 1, // Opcode: SELRAsmNH + /* 10286 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 10301 + /* 10291 */ MCD_OPC_CheckPredicate, + 14, + 5, + 0, + 0, // Skip to: 10301 + /* 10296 */ MCD_OPC_Decode, + 182, + 16, + 168, + 1, // Opcode: SELRAsmNO + /* 10301 */ MCD_OPC_CheckPredicate, + 14, + 233, + 1, + 0, // Skip to: 10795 + /* 10306 */ MCD_OPC_Decode, + 167, + 16, + 169, + 1, // Opcode: SELRAsm + /* 10311 */ MCD_OPC_FilterValue, + 242, + 1, + 217, + 0, + 0, // Skip to: 10534 + /* 10317 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 10320 */ MCD_OPC_FilterValue, + 0, + 214, + 1, + 0, // Skip to: 10795 + /* 10325 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 10328 */ MCD_OPC_FilterValue, + 1, + 9, + 0, + 0, // Skip to: 10342 + /* 10333 */ MCD_OPC_CheckPredicate, + 22, + 186, + 0, + 0, // Skip to: 10524 + /* 10338 */ MCD_OPC_Decode, + 213, + 13, + 9, // Opcode: LOCRAsmO + /* 10342 */ MCD_OPC_FilterValue, + 2, + 9, + 0, + 0, // Skip to: 10356 + /* 10347 */ MCD_OPC_CheckPredicate, + 22, + 172, + 0, + 0, // Skip to: 10524 + /* 10352 */ MCD_OPC_Decode, + 197, + 13, + 9, // Opcode: LOCRAsmH + /* 10356 */ MCD_OPC_FilterValue, + 3, + 9, + 0, + 0, // Skip to: 10370 + /* 10361 */ MCD_OPC_CheckPredicate, + 22, + 158, + 0, + 0, // Skip to: 10524 + /* 10366 */ MCD_OPC_Decode, + 207, + 13, + 9, // Opcode: LOCRAsmNLE + /* 10370 */ MCD_OPC_FilterValue, + 4, + 9, + 0, + 0, // Skip to: 10384 + /* 10375 */ MCD_OPC_CheckPredicate, + 22, + 144, + 0, + 0, // Skip to: 10524 + /* 10380 */ MCD_OPC_Decode, + 199, + 13, + 9, // Opcode: LOCRAsmL + /* 10384 */ MCD_OPC_FilterValue, + 5, + 9, + 0, + 0, // Skip to: 10398 + /* 10389 */ MCD_OPC_CheckPredicate, + 22, + 130, + 0, + 0, // Skip to: 10524 + /* 10394 */ MCD_OPC_Decode, + 205, + 13, + 9, // Opcode: LOCRAsmNHE + /* 10398 */ MCD_OPC_FilterValue, + 6, + 9, + 0, + 0, // Skip to: 10412 + /* 10403 */ MCD_OPC_CheckPredicate, + 22, + 116, + 0, + 0, // Skip to: 10524 + /* 10408 */ MCD_OPC_Decode, + 201, + 13, + 9, // Opcode: LOCRAsmLH + /* 10412 */ MCD_OPC_FilterValue, + 7, + 9, + 0, + 0, // Skip to: 10426 + /* 10417 */ MCD_OPC_CheckPredicate, + 22, + 102, + 0, + 0, // Skip to: 10524 + /* 10422 */ MCD_OPC_Decode, + 203, + 13, + 9, // Opcode: LOCRAsmNE + /* 10426 */ MCD_OPC_FilterValue, + 8, + 9, + 0, + 0, // Skip to: 10440 + /* 10431 */ MCD_OPC_CheckPredicate, + 22, + 88, + 0, + 0, // Skip to: 10524 + /* 10436 */ MCD_OPC_Decode, + 196, + 13, + 9, // Opcode: LOCRAsmE + /* 10440 */ MCD_OPC_FilterValue, + 9, + 9, + 0, + 0, // Skip to: 10454 + /* 10445 */ MCD_OPC_CheckPredicate, + 22, + 74, + 0, + 0, // Skip to: 10524 + /* 10450 */ MCD_OPC_Decode, + 208, + 13, + 9, // Opcode: LOCRAsmNLH + /* 10454 */ MCD_OPC_FilterValue, + 10, + 9, + 0, + 0, // Skip to: 10468 + /* 10459 */ MCD_OPC_CheckPredicate, + 22, + 60, + 0, + 0, // Skip to: 10524 + /* 10464 */ MCD_OPC_Decode, + 198, + 13, + 9, // Opcode: LOCRAsmHE + /* 10468 */ MCD_OPC_FilterValue, + 11, + 9, + 0, + 0, // Skip to: 10482 + /* 10473 */ MCD_OPC_CheckPredicate, + 22, + 46, + 0, + 0, // Skip to: 10524 + /* 10478 */ MCD_OPC_Decode, + 206, + 13, + 9, // Opcode: LOCRAsmNL + /* 10482 */ MCD_OPC_FilterValue, + 12, + 9, + 0, + 0, // Skip to: 10496 + /* 10487 */ MCD_OPC_CheckPredicate, + 22, + 32, + 0, + 0, // Skip to: 10524 + /* 10492 */ MCD_OPC_Decode, + 200, + 13, + 9, // Opcode: LOCRAsmLE + /* 10496 */ MCD_OPC_FilterValue, + 13, + 9, + 0, + 0, // Skip to: 10510 + /* 10501 */ MCD_OPC_CheckPredicate, + 22, + 18, + 0, + 0, // Skip to: 10524 + /* 10506 */ MCD_OPC_Decode, + 204, + 13, + 9, // Opcode: LOCRAsmNH + /* 10510 */ MCD_OPC_FilterValue, + 14, + 9, + 0, + 0, // Skip to: 10524 + /* 10515 */ MCD_OPC_CheckPredicate, + 22, + 4, + 0, + 0, // Skip to: 10524 + /* 10520 */ MCD_OPC_Decode, + 210, + 13, + 9, // Opcode: LOCRAsmNO + /* 10524 */ MCD_OPC_CheckPredicate, + 22, + 10, + 1, + 0, // Skip to: 10795 + /* 10529 */ MCD_OPC_Decode, + 195, + 13, + 170, + 1, // Opcode: LOCRAsm + /* 10534 */ MCD_OPC_FilterValue, + 244, + 1, + 17, + 0, + 0, // Skip to: 10557 + /* 10540 */ MCD_OPC_CheckPredicate, + 23, + 250, + 0, + 0, // Skip to: 10795 + /* 10545 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 243, + 0, + 0, // Skip to: 10795 + /* 10552 */ MCD_OPC_Decode, + 156, + 15, + 143, + 1, // Opcode: NRK + /* 10557 */ MCD_OPC_FilterValue, + 245, + 1, + 17, + 0, + 0, // Skip to: 10580 + /* 10563 */ MCD_OPC_CheckPredicate, + 14, + 227, + 0, + 0, // Skip to: 10795 + /* 10568 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 220, + 0, + 0, // Skip to: 10795 + /* 10575 */ MCD_OPC_Decode, + 136, + 15, + 143, + 1, // Opcode: NCRK + /* 10580 */ MCD_OPC_FilterValue, + 246, + 1, + 17, + 0, + 0, // Skip to: 10603 + /* 10586 */ MCD_OPC_CheckPredicate, + 23, + 204, + 0, + 0, // Skip to: 10795 + /* 10591 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 197, + 0, + 0, // Skip to: 10795 + /* 10598 */ MCD_OPC_Decode, + 177, + 15, + 143, + 1, // Opcode: ORK + /* 10603 */ MCD_OPC_FilterValue, + 247, + 1, + 17, + 0, + 0, // Skip to: 10626 + /* 10609 */ MCD_OPC_CheckPredicate, + 23, + 181, + 0, + 0, // Skip to: 10795 + /* 10614 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 174, + 0, + 0, // Skip to: 10795 + /* 10621 */ MCD_OPC_Decode, + 175, + 24, + 143, + 1, // Opcode: XRK + /* 10626 */ MCD_OPC_FilterValue, + 248, + 1, + 17, + 0, + 0, // Skip to: 10649 + /* 10632 */ MCD_OPC_CheckPredicate, + 23, + 158, + 0, + 0, // Skip to: 10795 + /* 10637 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 151, + 0, + 0, // Skip to: 10795 + /* 10644 */ MCD_OPC_Decode, + 178, + 4, + 143, + 1, // Opcode: ARK + /* 10649 */ MCD_OPC_FilterValue, + 249, + 1, + 17, + 0, + 0, // Skip to: 10672 + /* 10655 */ MCD_OPC_CheckPredicate, + 23, + 135, + 0, + 0, // Skip to: 10795 + /* 10660 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 128, + 0, + 0, // Skip to: 10795 + /* 10667 */ MCD_OPC_Decode, + 255, + 16, + 143, + 1, // Opcode: SRK + /* 10672 */ MCD_OPC_FilterValue, + 250, + 1, + 17, + 0, + 0, // Skip to: 10695 + /* 10678 */ MCD_OPC_CheckPredicate, + 23, + 112, + 0, + 0, // Skip to: 10795 + /* 10683 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 105, + 0, + 0, // Skip to: 10795 + /* 10690 */ MCD_OPC_Decode, + 171, + 4, + 143, + 1, // Opcode: ALRK + /* 10695 */ MCD_OPC_FilterValue, + 251, + 1, + 17, + 0, + 0, // Skip to: 10718 + /* 10701 */ MCD_OPC_CheckPredicate, + 23, + 89, + 0, + 0, // Skip to: 10795 + /* 10706 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 82, + 0, + 0, // Skip to: 10795 + /* 10713 */ MCD_OPC_Decode, + 228, + 16, + 143, + 1, // Opcode: SLRK + /* 10718 */ MCD_OPC_FilterValue, + 253, + 1, + 71, + 0, + 0, // Skip to: 10795 + /* 10724 */ MCD_OPC_CheckPredicate, + 24, + 66, + 0, + 0, // Skip to: 10795 + /* 10729 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 59, + 0, + 0, // Skip to: 10795 + /* 10736 */ MCD_OPC_Decode, + 222, + 14, + 143, + 1, // Opcode: MSRKC + /* 10741 */ MCD_OPC_FilterValue, + 186, + 1, + 4, + 0, + 0, // Skip to: 10751 + /* 10747 */ MCD_OPC_Decode, + 156, + 9, + 36, // Opcode: CS + /* 10751 */ MCD_OPC_FilterValue, + 187, + 1, + 5, + 0, + 0, // Skip to: 10762 + /* 10757 */ MCD_OPC_Decode, + 181, + 5, + 171, + 1, // Opcode: CDS + /* 10762 */ MCD_OPC_FilterValue, + 189, + 1, + 5, + 0, + 0, // Skip to: 10773 + /* 10768 */ MCD_OPC_Decode, + 166, + 8, + 172, + 1, // Opcode: CLM + /* 10773 */ MCD_OPC_FilterValue, + 190, + 1, + 5, + 0, + 0, // Skip to: 10784 + /* 10779 */ MCD_OPC_Decode, + 155, + 17, + 172, + 1, // Opcode: STCM + /* 10784 */ MCD_OPC_FilterValue, + 191, + 1, + 5, + 0, + 0, // Skip to: 10795 + /* 10790 */ MCD_OPC_Decode, + 156, + 10, + 173, + 1, // Opcode: ICM + /* 10795 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTable48[] = { -/* 0 */ MCD_OPC_ExtractField, 40, 8, // Inst{47-40} ... -/* 3 */ MCD_OPC_FilterValue, 192, 1, 11, 1, // Skip to: 275 -/* 8 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 11 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20 -/* 15 */ MCD_OPC_Decode, 250, 9, 166, 1, // Opcode: LARL -/* 20 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 29 -/* 24 */ MCD_OPC_Decode, 181, 10, 167, 1, // Opcode: LGFI -/* 29 */ MCD_OPC_FilterValue, 4, 143, 0, // Skip to: 176 -/* 33 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... -/* 36 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 45 -/* 40 */ MCD_OPC_Decode, 217, 9, 168, 1, // Opcode: JGAsmO -/* 45 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 54 -/* 49 */ MCD_OPC_Decode, 201, 9, 168, 1, // Opcode: JGAsmH -/* 54 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 63 -/* 58 */ MCD_OPC_Decode, 211, 9, 168, 1, // Opcode: JGAsmNLE -/* 63 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 72 -/* 67 */ MCD_OPC_Decode, 203, 9, 168, 1, // Opcode: JGAsmL -/* 72 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 81 -/* 76 */ MCD_OPC_Decode, 209, 9, 168, 1, // Opcode: JGAsmNHE -/* 81 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 90 -/* 85 */ MCD_OPC_Decode, 205, 9, 168, 1, // Opcode: JGAsmLH -/* 90 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 99 -/* 94 */ MCD_OPC_Decode, 207, 9, 168, 1, // Opcode: JGAsmNE -/* 99 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 108 -/* 103 */ MCD_OPC_Decode, 200, 9, 168, 1, // Opcode: JGAsmE -/* 108 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 117 -/* 112 */ MCD_OPC_Decode, 212, 9, 168, 1, // Opcode: JGAsmNLH -/* 117 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 126 -/* 121 */ MCD_OPC_Decode, 202, 9, 168, 1, // Opcode: JGAsmHE -/* 126 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 135 -/* 130 */ MCD_OPC_Decode, 210, 9, 168, 1, // Opcode: JGAsmNL -/* 135 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 144 -/* 139 */ MCD_OPC_Decode, 204, 9, 168, 1, // Opcode: JGAsmLE -/* 144 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 153 -/* 148 */ MCD_OPC_Decode, 208, 9, 168, 1, // Opcode: JGAsmNH -/* 153 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 162 -/* 157 */ MCD_OPC_Decode, 214, 9, 168, 1, // Opcode: JGAsmNO -/* 162 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 171 -/* 166 */ MCD_OPC_Decode, 199, 9, 168, 1, // Opcode: JG -/* 171 */ MCD_OPC_Decode, 251, 3, 169, 1, // Opcode: BRCLAsm -/* 176 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 185 -/* 180 */ MCD_OPC_Decode, 227, 3, 170, 1, // Opcode: BRASL -/* 185 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 194 -/* 189 */ MCD_OPC_Decode, 232, 21, 171, 1, // Opcode: XIHF -/* 194 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 203 -/* 198 */ MCD_OPC_Decode, 233, 21, 172, 1, // Opcode: XILF -/* 203 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 212 -/* 207 */ MCD_OPC_Decode, 139, 9, 173, 1, // Opcode: IIHF -/* 212 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 221 -/* 216 */ MCD_OPC_Decode, 142, 9, 174, 1, // Opcode: IILF -/* 221 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 230 -/* 225 */ MCD_OPC_Decode, 233, 13, 171, 1, // Opcode: NIHF -/* 230 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 239 -/* 234 */ MCD_OPC_Decode, 236, 13, 172, 1, // Opcode: NILF -/* 239 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 248 -/* 243 */ MCD_OPC_Decode, 250, 13, 171, 1, // Opcode: OIHF -/* 248 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 257 -/* 252 */ MCD_OPC_Decode, 253, 13, 172, 1, // Opcode: OILF -/* 257 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 266 -/* 261 */ MCD_OPC_Decode, 218, 10, 175, 1, // Opcode: LLIHF -/* 266 */ MCD_OPC_FilterValue, 15, 133, 73, // Skip to: 19091 -/* 270 */ MCD_OPC_Decode, 221, 10, 175, 1, // Opcode: LLILF -/* 275 */ MCD_OPC_FilterValue, 194, 1, 111, 0, // Skip to: 391 -/* 280 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 283 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 292 -/* 287 */ MCD_OPC_Decode, 183, 13, 176, 1, // Opcode: MSGFI -/* 292 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 301 -/* 296 */ MCD_OPC_Decode, 179, 13, 177, 1, // Opcode: MSFI -/* 301 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 310 -/* 305 */ MCD_OPC_Decode, 229, 14, 178, 1, // Opcode: SLGFI -/* 310 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 319 -/* 314 */ MCD_OPC_Decode, 226, 14, 172, 1, // Opcode: SLFI -/* 319 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 328 -/* 323 */ MCD_OPC_Decode, 242, 2, 176, 1, // Opcode: AGFI -/* 328 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 337 -/* 332 */ MCD_OPC_Decode, 239, 2, 177, 1, // Opcode: AFI -/* 337 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 346 -/* 341 */ MCD_OPC_Decode, 137, 3, 178, 1, // Opcode: ALGFI -/* 346 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 355 -/* 350 */ MCD_OPC_Decode, 134, 3, 172, 1, // Opcode: ALFI -/* 355 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 364 -/* 359 */ MCD_OPC_Decode, 201, 4, 167, 1, // Opcode: CGFI -/* 364 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 373 -/* 368 */ MCD_OPC_Decode, 186, 4, 179, 1, // Opcode: CFI -/* 373 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 382 -/* 377 */ MCD_OPC_Decode, 255, 5, 175, 1, // Opcode: CLGFI -/* 382 */ MCD_OPC_FilterValue, 15, 17, 73, // Skip to: 19091 -/* 386 */ MCD_OPC_Decode, 233, 5, 174, 1, // Opcode: CLFI -/* 391 */ MCD_OPC_FilterValue, 196, 1, 102, 0, // Skip to: 498 -/* 396 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 399 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 408 -/* 403 */ MCD_OPC_Decode, 217, 10, 180, 1, // Opcode: LLHRL -/* 408 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 417 -/* 412 */ MCD_OPC_Decode, 188, 10, 166, 1, // Opcode: LGHRL -/* 417 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 426 -/* 421 */ MCD_OPC_Decode, 196, 10, 180, 1, // Opcode: LHRL -/* 426 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 435 -/* 430 */ MCD_OPC_Decode, 210, 10, 166, 1, // Opcode: LLGHRL -/* 435 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 444 -/* 439 */ MCD_OPC_Decode, 185, 15, 180, 1, // Opcode: STHRL -/* 444 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 453 -/* 448 */ MCD_OPC_Decode, 190, 10, 166, 1, // Opcode: LGRL -/* 453 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 462 -/* 457 */ MCD_OPC_Decode, 181, 15, 166, 1, // Opcode: STGRL -/* 462 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 471 -/* 466 */ MCD_OPC_Decode, 183, 10, 166, 1, // Opcode: LGFRL -/* 471 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 480 -/* 475 */ MCD_OPC_Decode, 208, 12, 180, 1, // Opcode: LRL -/* 480 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 489 -/* 484 */ MCD_OPC_Decode, 206, 10, 166, 1, // Opcode: LLGFRL -/* 489 */ MCD_OPC_FilterValue, 15, 166, 72, // Skip to: 19091 -/* 493 */ MCD_OPC_Decode, 136, 16, 180, 1, // Opcode: STRL -/* 498 */ MCD_OPC_FilterValue, 197, 1, 9, 0, // Skip to: 512 -/* 503 */ MCD_OPC_CheckPredicate, 3, 152, 72, // Skip to: 19091 -/* 507 */ MCD_OPC_Decode, 224, 3, 181, 1, // Opcode: BPRP -/* 512 */ MCD_OPC_FilterValue, 198, 1, 111, 0, // Skip to: 628 -/* 517 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 520 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 529 -/* 524 */ MCD_OPC_Decode, 239, 8, 166, 1, // Opcode: EXRL -/* 529 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 538 -/* 533 */ MCD_OPC_Decode, 138, 14, 182, 1, // Opcode: PFDRL -/* 538 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 547 -/* 542 */ MCD_OPC_Decode, 206, 4, 166, 1, // Opcode: CGHRL -/* 547 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 556 -/* 551 */ MCD_OPC_Decode, 177, 5, 180, 1, // Opcode: CHRL -/* 556 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 565 -/* 560 */ MCD_OPC_Decode, 130, 6, 166, 1, // Opcode: CLGHRL -/* 565 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 574 -/* 569 */ MCD_OPC_Decode, 238, 6, 180, 1, // Opcode: CLHRL -/* 574 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 583 -/* 578 */ MCD_OPC_Decode, 151, 5, 166, 1, // Opcode: CGRL -/* 583 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 592 -/* 587 */ MCD_OPC_Decode, 203, 6, 166, 1, // Opcode: CLGRL -/* 592 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 601 -/* 596 */ MCD_OPC_Decode, 203, 4, 166, 1, // Opcode: CGFRL -/* 601 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 610 -/* 605 */ MCD_OPC_Decode, 245, 7, 180, 1, // Opcode: CRL -/* 610 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 619 -/* 614 */ MCD_OPC_Decode, 129, 6, 166, 1, // Opcode: CLGFRL -/* 619 */ MCD_OPC_FilterValue, 15, 36, 72, // Skip to: 19091 -/* 623 */ MCD_OPC_Decode, 174, 7, 180, 1, // Opcode: CLRL -/* 628 */ MCD_OPC_FilterValue, 199, 1, 15, 0, // Skip to: 648 -/* 633 */ MCD_OPC_CheckPredicate, 3, 22, 72, // Skip to: 19091 -/* 637 */ MCD_OPC_CheckField, 32, 4, 0, 16, 72, // Skip to: 19091 -/* 643 */ MCD_OPC_Decode, 223, 3, 183, 1, // Opcode: BPP -/* 648 */ MCD_OPC_FilterValue, 200, 1, 56, 0, // Skip to: 709 -/* 653 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 656 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 665 -/* 660 */ MCD_OPC_Decode, 198, 13, 184, 1, // Opcode: MVCOS -/* 665 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 674 -/* 669 */ MCD_OPC_Decode, 219, 8, 184, 1, // Opcode: ECTG -/* 674 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 683 -/* 678 */ MCD_OPC_Decode, 138, 8, 184, 1, // Opcode: CSST -/* 683 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 696 -/* 687 */ MCD_OPC_CheckPredicate, 17, 224, 71, // Skip to: 19091 -/* 691 */ MCD_OPC_Decode, 184, 12, 185, 1, // Opcode: LPD -/* 696 */ MCD_OPC_FilterValue, 5, 215, 71, // Skip to: 19091 -/* 700 */ MCD_OPC_CheckPredicate, 17, 211, 71, // Skip to: 19091 -/* 704 */ MCD_OPC_Decode, 188, 12, 185, 1, // Opcode: LPDG -/* 709 */ MCD_OPC_FilterValue, 204, 1, 81, 0, // Skip to: 795 -/* 714 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 717 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 730 -/* 721 */ MCD_OPC_CheckPredicate, 11, 190, 71, // Skip to: 19091 -/* 725 */ MCD_OPC_Decode, 254, 3, 186, 1, // Opcode: BRCTH -/* 730 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 743 -/* 734 */ MCD_OPC_CheckPredicate, 11, 177, 71, // Skip to: 19091 -/* 738 */ MCD_OPC_Decode, 128, 3, 187, 1, // Opcode: AIH -/* 743 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 756 -/* 747 */ MCD_OPC_CheckPredicate, 11, 164, 71, // Skip to: 19091 -/* 751 */ MCD_OPC_Decode, 149, 3, 187, 1, // Opcode: ALSIH -/* 756 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 769 -/* 760 */ MCD_OPC_CheckPredicate, 11, 151, 71, // Skip to: 19091 -/* 764 */ MCD_OPC_Decode, 150, 3, 187, 1, // Opcode: ALSIHN -/* 769 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 782 -/* 773 */ MCD_OPC_CheckPredicate, 11, 138, 71, // Skip to: 19091 -/* 777 */ MCD_OPC_Decode, 194, 5, 188, 1, // Opcode: CIH -/* 782 */ MCD_OPC_FilterValue, 15, 129, 71, // Skip to: 19091 -/* 786 */ MCD_OPC_CheckPredicate, 11, 125, 71, // Skip to: 19091 -/* 790 */ MCD_OPC_Decode, 254, 6, 173, 1, // Opcode: CLIH -/* 795 */ MCD_OPC_FilterValue, 208, 1, 5, 0, // Skip to: 805 -/* 800 */ MCD_OPC_Decode, 199, 16, 189, 1, // Opcode: TRTR -/* 805 */ MCD_OPC_FilterValue, 209, 1, 5, 0, // Skip to: 815 -/* 810 */ MCD_OPC_Decode, 207, 13, 189, 1, // Opcode: MVN -/* 815 */ MCD_OPC_FilterValue, 210, 1, 5, 0, // Skip to: 825 -/* 820 */ MCD_OPC_Decode, 191, 13, 189, 1, // Opcode: MVC -/* 825 */ MCD_OPC_FilterValue, 211, 1, 5, 0, // Skip to: 835 -/* 830 */ MCD_OPC_Decode, 211, 13, 189, 1, // Opcode: MVZ -/* 835 */ MCD_OPC_FilterValue, 212, 1, 5, 0, // Skip to: 845 -/* 840 */ MCD_OPC_Decode, 227, 13, 189, 1, // Opcode: NC -/* 845 */ MCD_OPC_FilterValue, 213, 1, 5, 0, // Skip to: 855 -/* 850 */ MCD_OPC_Decode, 225, 5, 189, 1, // Opcode: CLC -/* 855 */ MCD_OPC_FilterValue, 214, 1, 5, 0, // Skip to: 865 -/* 860 */ MCD_OPC_Decode, 245, 13, 189, 1, // Opcode: OC -/* 865 */ MCD_OPC_FilterValue, 215, 1, 5, 0, // Skip to: 875 -/* 870 */ MCD_OPC_Decode, 227, 21, 189, 1, // Opcode: XC -/* 875 */ MCD_OPC_FilterValue, 217, 1, 5, 0, // Skip to: 885 -/* 880 */ MCD_OPC_Decode, 194, 13, 190, 1, // Opcode: MVCK -/* 885 */ MCD_OPC_FilterValue, 218, 1, 5, 0, // Skip to: 895 -/* 890 */ MCD_OPC_Decode, 199, 13, 190, 1, // Opcode: MVCP -/* 895 */ MCD_OPC_FilterValue, 219, 1, 5, 0, // Skip to: 905 -/* 900 */ MCD_OPC_Decode, 200, 13, 190, 1, // Opcode: MVCS -/* 905 */ MCD_OPC_FilterValue, 220, 1, 5, 0, // Skip to: 915 -/* 910 */ MCD_OPC_Decode, 184, 16, 189, 1, // Opcode: TR -/* 915 */ MCD_OPC_FilterValue, 221, 1, 5, 0, // Skip to: 925 -/* 920 */ MCD_OPC_Decode, 194, 16, 189, 1, // Opcode: TRT -/* 925 */ MCD_OPC_FilterValue, 222, 1, 5, 0, // Skip to: 935 -/* 930 */ MCD_OPC_Decode, 220, 8, 189, 1, // Opcode: ED -/* 935 */ MCD_OPC_FilterValue, 223, 1, 5, 0, // Skip to: 945 -/* 940 */ MCD_OPC_Decode, 221, 8, 189, 1, // Opcode: EDMK -/* 945 */ MCD_OPC_FilterValue, 225, 1, 5, 0, // Skip to: 955 -/* 950 */ MCD_OPC_Decode, 144, 14, 191, 1, // Opcode: PKU -/* 955 */ MCD_OPC_FilterValue, 226, 1, 5, 0, // Skip to: 965 -/* 960 */ MCD_OPC_Decode, 208, 16, 189, 1, // Opcode: UNPKU -/* 965 */ MCD_OPC_FilterValue, 227, 1, 83, 5, // Skip to: 2333 -/* 970 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 973 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 982 -/* 977 */ MCD_OPC_Decode, 223, 12, 192, 1, // Opcode: LTG -/* 982 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 991 -/* 986 */ MCD_OPC_Decode, 204, 12, 192, 1, // Opcode: LRAG -/* 991 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 1000 -/* 995 */ MCD_OPC_Decode, 175, 10, 192, 1, // Opcode: LG -/* 1000 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 1009 -/* 1004 */ MCD_OPC_Decode, 160, 8, 193, 1, // Opcode: CVBY -/* 1009 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 1018 -/* 1013 */ MCD_OPC_Decode, 240, 2, 194, 1, // Opcode: AG -/* 1018 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 1027 -/* 1022 */ MCD_OPC_Decode, 202, 14, 194, 1, // Opcode: SG -/* 1027 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 1036 -/* 1031 */ MCD_OPC_Decode, 135, 3, 194, 1, // Opcode: ALG -/* 1036 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 1045 -/* 1040 */ MCD_OPC_Decode, 227, 14, 194, 1, // Opcode: SLG -/* 1045 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 1054 -/* 1049 */ MCD_OPC_Decode, 180, 13, 194, 1, // Opcode: MSG -/* 1054 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 1063 -/* 1058 */ MCD_OPC_Decode, 207, 8, 195, 1, // Opcode: DSG -/* 1063 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 1072 -/* 1067 */ MCD_OPC_Decode, 159, 8, 194, 1, // Opcode: CVBG -/* 1072 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 1081 -/* 1076 */ MCD_OPC_Decode, 210, 12, 192, 1, // Opcode: LRVG -/* 1081 */ MCD_OPC_FilterValue, 18, 5, 0, // Skip to: 1090 -/* 1085 */ MCD_OPC_Decode, 215, 12, 196, 1, // Opcode: LT -/* 1090 */ MCD_OPC_FilterValue, 19, 5, 0, // Skip to: 1099 -/* 1094 */ MCD_OPC_Decode, 205, 12, 192, 1, // Opcode: LRAY -/* 1099 */ MCD_OPC_FilterValue, 20, 5, 0, // Skip to: 1108 -/* 1103 */ MCD_OPC_Decode, 180, 10, 192, 1, // Opcode: LGF -/* 1108 */ MCD_OPC_FilterValue, 21, 5, 0, // Skip to: 1117 -/* 1112 */ MCD_OPC_Decode, 185, 10, 192, 1, // Opcode: LGH -/* 1117 */ MCD_OPC_FilterValue, 22, 5, 0, // Skip to: 1126 -/* 1121 */ MCD_OPC_Decode, 203, 10, 192, 1, // Opcode: LLGF -/* 1126 */ MCD_OPC_FilterValue, 23, 5, 0, // Skip to: 1135 -/* 1130 */ MCD_OPC_Decode, 211, 10, 192, 1, // Opcode: LLGT -/* 1135 */ MCD_OPC_FilterValue, 24, 5, 0, // Skip to: 1144 -/* 1139 */ MCD_OPC_Decode, 241, 2, 194, 1, // Opcode: AGF -/* 1144 */ MCD_OPC_FilterValue, 25, 5, 0, // Skip to: 1153 -/* 1148 */ MCD_OPC_Decode, 203, 14, 194, 1, // Opcode: SGF -/* 1153 */ MCD_OPC_FilterValue, 26, 5, 0, // Skip to: 1162 -/* 1157 */ MCD_OPC_Decode, 136, 3, 194, 1, // Opcode: ALGF -/* 1162 */ MCD_OPC_FilterValue, 27, 5, 0, // Skip to: 1171 -/* 1166 */ MCD_OPC_Decode, 228, 14, 194, 1, // Opcode: SLGF -/* 1171 */ MCD_OPC_FilterValue, 28, 5, 0, // Skip to: 1180 -/* 1175 */ MCD_OPC_Decode, 182, 13, 194, 1, // Opcode: MSGF -/* 1180 */ MCD_OPC_FilterValue, 29, 5, 0, // Skip to: 1189 -/* 1184 */ MCD_OPC_Decode, 208, 8, 195, 1, // Opcode: DSGF -/* 1189 */ MCD_OPC_FilterValue, 30, 5, 0, // Skip to: 1198 -/* 1193 */ MCD_OPC_Decode, 209, 12, 196, 1, // Opcode: LRV -/* 1198 */ MCD_OPC_FilterValue, 31, 5, 0, // Skip to: 1207 -/* 1202 */ MCD_OPC_Decode, 212, 12, 196, 1, // Opcode: LRVH -/* 1207 */ MCD_OPC_FilterValue, 32, 5, 0, // Skip to: 1216 -/* 1211 */ MCD_OPC_Decode, 191, 4, 192, 1, // Opcode: CG -/* 1216 */ MCD_OPC_FilterValue, 33, 5, 0, // Skip to: 1225 -/* 1220 */ MCD_OPC_Decode, 250, 5, 192, 1, // Opcode: CLG -/* 1225 */ MCD_OPC_FilterValue, 36, 5, 0, // Skip to: 1234 -/* 1229 */ MCD_OPC_Decode, 180, 15, 192, 1, // Opcode: STG -/* 1234 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 1247 -/* 1238 */ MCD_OPC_CheckPredicate, 2, 185, 69, // Skip to: 19091 -/* 1242 */ MCD_OPC_Decode, 242, 13, 192, 1, // Opcode: NTSTG -/* 1247 */ MCD_OPC_FilterValue, 38, 5, 0, // Skip to: 1256 -/* 1251 */ MCD_OPC_Decode, 163, 8, 196, 1, // Opcode: CVDY -/* 1256 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 1269 -/* 1260 */ MCD_OPC_CheckPredicate, 18, 163, 69, // Skip to: 19091 -/* 1264 */ MCD_OPC_Decode, 248, 12, 192, 1, // Opcode: LZRG -/* 1269 */ MCD_OPC_FilterValue, 46, 5, 0, // Skip to: 1278 -/* 1273 */ MCD_OPC_Decode, 162, 8, 192, 1, // Opcode: CVDG -/* 1278 */ MCD_OPC_FilterValue, 47, 5, 0, // Skip to: 1287 -/* 1282 */ MCD_OPC_Decode, 138, 16, 192, 1, // Opcode: STRVG -/* 1287 */ MCD_OPC_FilterValue, 48, 5, 0, // Skip to: 1296 -/* 1291 */ MCD_OPC_Decode, 200, 4, 192, 1, // Opcode: CGF -/* 1296 */ MCD_OPC_FilterValue, 49, 5, 0, // Skip to: 1305 -/* 1300 */ MCD_OPC_Decode, 254, 5, 192, 1, // Opcode: CLGF -/* 1305 */ MCD_OPC_FilterValue, 50, 5, 0, // Skip to: 1314 -/* 1309 */ MCD_OPC_Decode, 224, 12, 192, 1, // Opcode: LTGF -/* 1314 */ MCD_OPC_FilterValue, 52, 5, 0, // Skip to: 1323 -/* 1318 */ MCD_OPC_Decode, 204, 4, 192, 1, // Opcode: CGH -/* 1323 */ MCD_OPC_FilterValue, 54, 5, 0, // Skip to: 1332 -/* 1327 */ MCD_OPC_Decode, 137, 14, 197, 1, // Opcode: PFD -/* 1332 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 1345 -/* 1336 */ MCD_OPC_CheckPredicate, 16, 87, 69, // Skip to: 19091 -/* 1340 */ MCD_OPC_Decode, 244, 2, 194, 1, // Opcode: AGH -/* 1345 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 1358 -/* 1349 */ MCD_OPC_CheckPredicate, 16, 74, 69, // Skip to: 19091 -/* 1353 */ MCD_OPC_Decode, 205, 14, 194, 1, // Opcode: SGH -/* 1358 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1371 -/* 1362 */ MCD_OPC_CheckPredicate, 18, 61, 69, // Skip to: 19091 -/* 1366 */ MCD_OPC_Decode, 224, 10, 192, 1, // Opcode: LLZRGF -/* 1371 */ MCD_OPC_FilterValue, 59, 9, 0, // Skip to: 1384 -/* 1375 */ MCD_OPC_CheckPredicate, 18, 48, 69, // Skip to: 19091 -/* 1379 */ MCD_OPC_Decode, 247, 12, 196, 1, // Opcode: LZRF -/* 1384 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 1397 -/* 1388 */ MCD_OPC_CheckPredicate, 16, 35, 69, // Skip to: 19091 -/* 1392 */ MCD_OPC_Decode, 156, 13, 194, 1, // Opcode: MGH -/* 1397 */ MCD_OPC_FilterValue, 62, 5, 0, // Skip to: 1406 -/* 1401 */ MCD_OPC_Decode, 137, 16, 196, 1, // Opcode: STRV -/* 1406 */ MCD_OPC_FilterValue, 63, 5, 0, // Skip to: 1415 -/* 1410 */ MCD_OPC_Decode, 139, 16, 196, 1, // Opcode: STRVH -/* 1415 */ MCD_OPC_FilterValue, 70, 5, 0, // Skip to: 1424 -/* 1419 */ MCD_OPC_Decode, 197, 3, 194, 1, // Opcode: BCTG -/* 1424 */ MCD_OPC_FilterValue, 71, 207, 0, // Skip to: 1635 -/* 1428 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... -/* 1431 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1444 -/* 1435 */ MCD_OPC_CheckPredicate, 16, 187, 0, // Skip to: 1626 -/* 1439 */ MCD_OPC_Decode, 218, 3, 198, 1, // Opcode: BIAsmO -/* 1444 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1457 -/* 1448 */ MCD_OPC_CheckPredicate, 16, 174, 0, // Skip to: 1626 -/* 1452 */ MCD_OPC_Decode, 202, 3, 198, 1, // Opcode: BIAsmH -/* 1457 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1470 -/* 1461 */ MCD_OPC_CheckPredicate, 16, 161, 0, // Skip to: 1626 -/* 1465 */ MCD_OPC_Decode, 212, 3, 198, 1, // Opcode: BIAsmNLE -/* 1470 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1483 -/* 1474 */ MCD_OPC_CheckPredicate, 16, 148, 0, // Skip to: 1626 -/* 1478 */ MCD_OPC_Decode, 204, 3, 198, 1, // Opcode: BIAsmL -/* 1483 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1496 -/* 1487 */ MCD_OPC_CheckPredicate, 16, 135, 0, // Skip to: 1626 -/* 1491 */ MCD_OPC_Decode, 210, 3, 198, 1, // Opcode: BIAsmNHE -/* 1496 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1509 -/* 1500 */ MCD_OPC_CheckPredicate, 16, 122, 0, // Skip to: 1626 -/* 1504 */ MCD_OPC_Decode, 206, 3, 198, 1, // Opcode: BIAsmLH -/* 1509 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1522 -/* 1513 */ MCD_OPC_CheckPredicate, 16, 109, 0, // Skip to: 1626 -/* 1517 */ MCD_OPC_Decode, 208, 3, 198, 1, // Opcode: BIAsmNE -/* 1522 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1535 -/* 1526 */ MCD_OPC_CheckPredicate, 16, 96, 0, // Skip to: 1626 -/* 1530 */ MCD_OPC_Decode, 201, 3, 198, 1, // Opcode: BIAsmE -/* 1535 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1548 -/* 1539 */ MCD_OPC_CheckPredicate, 16, 83, 0, // Skip to: 1626 -/* 1543 */ MCD_OPC_Decode, 213, 3, 198, 1, // Opcode: BIAsmNLH -/* 1548 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1561 -/* 1552 */ MCD_OPC_CheckPredicate, 16, 70, 0, // Skip to: 1626 -/* 1556 */ MCD_OPC_Decode, 203, 3, 198, 1, // Opcode: BIAsmHE -/* 1561 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1574 -/* 1565 */ MCD_OPC_CheckPredicate, 16, 57, 0, // Skip to: 1626 -/* 1569 */ MCD_OPC_Decode, 211, 3, 198, 1, // Opcode: BIAsmNL -/* 1574 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1587 -/* 1578 */ MCD_OPC_CheckPredicate, 16, 44, 0, // Skip to: 1626 -/* 1582 */ MCD_OPC_Decode, 205, 3, 198, 1, // Opcode: BIAsmLE -/* 1587 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1600 -/* 1591 */ MCD_OPC_CheckPredicate, 16, 31, 0, // Skip to: 1626 -/* 1595 */ MCD_OPC_Decode, 209, 3, 198, 1, // Opcode: BIAsmNH -/* 1600 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1613 -/* 1604 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1626 -/* 1608 */ MCD_OPC_Decode, 215, 3, 198, 1, // Opcode: BIAsmNO -/* 1613 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1626 -/* 1617 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1626 -/* 1621 */ MCD_OPC_Decode, 200, 3, 198, 1, // Opcode: BI -/* 1626 */ MCD_OPC_CheckPredicate, 16, 53, 68, // Skip to: 19091 -/* 1630 */ MCD_OPC_Decode, 222, 3, 197, 1, // Opcode: BICAsm -/* 1635 */ MCD_OPC_FilterValue, 72, 9, 0, // Skip to: 1648 -/* 1639 */ MCD_OPC_CheckPredicate, 19, 40, 68, // Skip to: 19091 -/* 1643 */ MCD_OPC_Decode, 207, 10, 192, 1, // Opcode: LLGFSG -/* 1648 */ MCD_OPC_FilterValue, 73, 9, 0, // Skip to: 1661 -/* 1652 */ MCD_OPC_CheckPredicate, 19, 27, 68, // Skip to: 19091 -/* 1656 */ MCD_OPC_Decode, 182, 15, 192, 1, // Opcode: STGSC -/* 1661 */ MCD_OPC_FilterValue, 76, 9, 0, // Skip to: 1674 -/* 1665 */ MCD_OPC_CheckPredicate, 19, 14, 68, // Skip to: 19091 -/* 1669 */ MCD_OPC_Decode, 184, 10, 192, 1, // Opcode: LGG -/* 1674 */ MCD_OPC_FilterValue, 77, 9, 0, // Skip to: 1687 -/* 1678 */ MCD_OPC_CheckPredicate, 19, 1, 68, // Skip to: 19091 -/* 1682 */ MCD_OPC_Decode, 191, 10, 192, 1, // Opcode: LGSC -/* 1687 */ MCD_OPC_FilterValue, 80, 5, 0, // Skip to: 1696 -/* 1691 */ MCD_OPC_Decode, 144, 16, 196, 1, // Opcode: STY -/* 1696 */ MCD_OPC_FilterValue, 81, 5, 0, // Skip to: 1705 -/* 1700 */ MCD_OPC_Decode, 190, 13, 193, 1, // Opcode: MSY -/* 1705 */ MCD_OPC_FilterValue, 83, 9, 0, // Skip to: 1718 -/* 1709 */ MCD_OPC_CheckPredicate, 16, 226, 67, // Skip to: 19091 -/* 1713 */ MCD_OPC_Decode, 169, 13, 193, 1, // Opcode: MSC -/* 1718 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 1727 -/* 1722 */ MCD_OPC_Decode, 243, 13, 193, 1, // Opcode: NY -/* 1727 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 1736 -/* 1731 */ MCD_OPC_Decode, 204, 7, 196, 1, // Opcode: CLY -/* 1736 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 1745 -/* 1740 */ MCD_OPC_Decode, 131, 14, 193, 1, // Opcode: OY -/* 1745 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 1754 -/* 1749 */ MCD_OPC_Decode, 238, 21, 193, 1, // Opcode: XY -/* 1754 */ MCD_OPC_FilterValue, 88, 5, 0, // Skip to: 1763 -/* 1758 */ MCD_OPC_Decode, 244, 12, 196, 1, // Opcode: LY -/* 1763 */ MCD_OPC_FilterValue, 89, 5, 0, // Skip to: 1772 -/* 1767 */ MCD_OPC_Decode, 184, 8, 196, 1, // Opcode: CY -/* 1772 */ MCD_OPC_FilterValue, 90, 5, 0, // Skip to: 1781 -/* 1776 */ MCD_OPC_Decode, 164, 3, 193, 1, // Opcode: AY -/* 1781 */ MCD_OPC_FilterValue, 91, 5, 0, // Skip to: 1790 -/* 1785 */ MCD_OPC_Decode, 154, 16, 193, 1, // Opcode: SY -/* 1790 */ MCD_OPC_FilterValue, 92, 5, 0, // Skip to: 1799 -/* 1794 */ MCD_OPC_Decode, 154, 13, 195, 1, // Opcode: MFY -/* 1799 */ MCD_OPC_FilterValue, 94, 5, 0, // Skip to: 1808 -/* 1803 */ MCD_OPC_Decode, 151, 3, 193, 1, // Opcode: ALY -/* 1808 */ MCD_OPC_FilterValue, 95, 5, 0, // Skip to: 1817 -/* 1812 */ MCD_OPC_Decode, 241, 14, 193, 1, // Opcode: SLY -/* 1817 */ MCD_OPC_FilterValue, 112, 5, 0, // Skip to: 1826 -/* 1821 */ MCD_OPC_Decode, 186, 15, 196, 1, // Opcode: STHY -/* 1826 */ MCD_OPC_FilterValue, 113, 5, 0, // Skip to: 1835 -/* 1830 */ MCD_OPC_Decode, 255, 9, 192, 1, // Opcode: LAY -/* 1835 */ MCD_OPC_FilterValue, 114, 5, 0, // Skip to: 1844 -/* 1839 */ MCD_OPC_Decode, 171, 15, 196, 1, // Opcode: STCY -/* 1844 */ MCD_OPC_FilterValue, 115, 5, 0, // Skip to: 1853 -/* 1848 */ MCD_OPC_Decode, 134, 9, 194, 1, // Opcode: ICY -/* 1853 */ MCD_OPC_FilterValue, 117, 5, 0, // Skip to: 1862 -/* 1857 */ MCD_OPC_Decode, 243, 9, 192, 1, // Opcode: LAEY -/* 1862 */ MCD_OPC_FilterValue, 118, 5, 0, // Skip to: 1871 -/* 1866 */ MCD_OPC_Decode, 128, 10, 196, 1, // Opcode: LB -/* 1871 */ MCD_OPC_FilterValue, 119, 5, 0, // Skip to: 1880 -/* 1875 */ MCD_OPC_Decode, 177, 10, 192, 1, // Opcode: LGB -/* 1880 */ MCD_OPC_FilterValue, 120, 5, 0, // Skip to: 1889 -/* 1884 */ MCD_OPC_Decode, 197, 10, 196, 1, // Opcode: LHY -/* 1889 */ MCD_OPC_FilterValue, 121, 5, 0, // Skip to: 1898 -/* 1893 */ MCD_OPC_Decode, 179, 5, 196, 1, // Opcode: CHY -/* 1898 */ MCD_OPC_FilterValue, 122, 5, 0, // Skip to: 1907 -/* 1902 */ MCD_OPC_Decode, 255, 2, 193, 1, // Opcode: AHY -/* 1907 */ MCD_OPC_FilterValue, 123, 5, 0, // Skip to: 1916 -/* 1911 */ MCD_OPC_Decode, 211, 14, 193, 1, // Opcode: SHY -/* 1916 */ MCD_OPC_FilterValue, 124, 5, 0, // Skip to: 1925 -/* 1920 */ MCD_OPC_Decode, 161, 13, 193, 1, // Opcode: MHY -/* 1925 */ MCD_OPC_FilterValue, 128, 1, 5, 0, // Skip to: 1935 -/* 1930 */ MCD_OPC_Decode, 228, 13, 194, 1, // Opcode: NG -/* 1935 */ MCD_OPC_FilterValue, 129, 1, 5, 0, // Skip to: 1945 -/* 1940 */ MCD_OPC_Decode, 246, 13, 194, 1, // Opcode: OG -/* 1945 */ MCD_OPC_FilterValue, 130, 1, 5, 0, // Skip to: 1955 -/* 1950 */ MCD_OPC_Decode, 228, 21, 194, 1, // Opcode: XG -/* 1955 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 1969 -/* 1960 */ MCD_OPC_CheckPredicate, 16, 231, 66, // Skip to: 19091 -/* 1964 */ MCD_OPC_Decode, 181, 13, 194, 1, // Opcode: MSGC -/* 1969 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 1983 -/* 1974 */ MCD_OPC_CheckPredicate, 16, 217, 66, // Skip to: 19091 -/* 1978 */ MCD_OPC_Decode, 155, 13, 195, 1, // Opcode: MG -/* 1983 */ MCD_OPC_FilterValue, 133, 1, 9, 0, // Skip to: 1997 -/* 1988 */ MCD_OPC_CheckPredicate, 20, 203, 66, // Skip to: 19091 -/* 1992 */ MCD_OPC_Decode, 176, 10, 192, 1, // Opcode: LGAT -/* 1997 */ MCD_OPC_FilterValue, 134, 1, 5, 0, // Skip to: 2007 -/* 2002 */ MCD_OPC_Decode, 163, 13, 195, 1, // Opcode: MLG -/* 2007 */ MCD_OPC_FilterValue, 135, 1, 5, 0, // Skip to: 2017 -/* 2012 */ MCD_OPC_Decode, 202, 8, 195, 1, // Opcode: DLG -/* 2017 */ MCD_OPC_FilterValue, 136, 1, 5, 0, // Skip to: 2027 -/* 2022 */ MCD_OPC_Decode, 131, 3, 194, 1, // Opcode: ALCG -/* 2027 */ MCD_OPC_FilterValue, 137, 1, 5, 0, // Skip to: 2037 -/* 2032 */ MCD_OPC_Decode, 220, 14, 194, 1, // Opcode: SLBG -/* 2037 */ MCD_OPC_FilterValue, 142, 1, 5, 0, // Skip to: 2047 -/* 2042 */ MCD_OPC_Decode, 132, 16, 199, 1, // Opcode: STPQ -/* 2047 */ MCD_OPC_FilterValue, 143, 1, 5, 0, // Skip to: 2057 -/* 2052 */ MCD_OPC_Decode, 195, 12, 199, 1, // Opcode: LPQ -/* 2057 */ MCD_OPC_FilterValue, 144, 1, 5, 0, // Skip to: 2067 -/* 2062 */ MCD_OPC_Decode, 201, 10, 192, 1, // Opcode: LLGC -/* 2067 */ MCD_OPC_FilterValue, 145, 1, 5, 0, // Skip to: 2077 -/* 2072 */ MCD_OPC_Decode, 208, 10, 192, 1, // Opcode: LLGH -/* 2077 */ MCD_OPC_FilterValue, 148, 1, 5, 0, // Skip to: 2087 -/* 2082 */ MCD_OPC_Decode, 198, 10, 196, 1, // Opcode: LLC -/* 2087 */ MCD_OPC_FilterValue, 149, 1, 5, 0, // Skip to: 2097 -/* 2092 */ MCD_OPC_Decode, 214, 10, 196, 1, // Opcode: LLH -/* 2097 */ MCD_OPC_FilterValue, 150, 1, 5, 0, // Skip to: 2107 -/* 2102 */ MCD_OPC_Decode, 162, 13, 195, 1, // Opcode: ML -/* 2107 */ MCD_OPC_FilterValue, 151, 1, 5, 0, // Skip to: 2117 -/* 2112 */ MCD_OPC_Decode, 201, 8, 195, 1, // Opcode: DL -/* 2117 */ MCD_OPC_FilterValue, 152, 1, 5, 0, // Skip to: 2127 -/* 2122 */ MCD_OPC_Decode, 130, 3, 193, 1, // Opcode: ALC -/* 2127 */ MCD_OPC_FilterValue, 153, 1, 5, 0, // Skip to: 2137 -/* 2132 */ MCD_OPC_Decode, 219, 14, 193, 1, // Opcode: SLB -/* 2137 */ MCD_OPC_FilterValue, 156, 1, 9, 0, // Skip to: 2151 -/* 2142 */ MCD_OPC_CheckPredicate, 20, 49, 66, // Skip to: 19091 -/* 2146 */ MCD_OPC_Decode, 212, 10, 192, 1, // Opcode: LLGTAT -/* 2151 */ MCD_OPC_FilterValue, 157, 1, 9, 0, // Skip to: 2165 -/* 2156 */ MCD_OPC_CheckPredicate, 20, 35, 66, // Skip to: 19091 -/* 2160 */ MCD_OPC_Decode, 204, 10, 192, 1, // Opcode: LLGFAT -/* 2165 */ MCD_OPC_FilterValue, 159, 1, 9, 0, // Skip to: 2179 -/* 2170 */ MCD_OPC_CheckPredicate, 20, 21, 66, // Skip to: 19091 -/* 2174 */ MCD_OPC_Decode, 252, 9, 196, 1, // Opcode: LAT -/* 2179 */ MCD_OPC_FilterValue, 192, 1, 9, 0, // Skip to: 2193 -/* 2184 */ MCD_OPC_CheckPredicate, 11, 7, 66, // Skip to: 19091 -/* 2188 */ MCD_OPC_Decode, 129, 10, 200, 1, // Opcode: LBH -/* 2193 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 2207 -/* 2198 */ MCD_OPC_CheckPredicate, 11, 249, 65, // Skip to: 19091 -/* 2202 */ MCD_OPC_Decode, 199, 10, 200, 1, // Opcode: LLCH -/* 2207 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 2221 -/* 2212 */ MCD_OPC_CheckPredicate, 11, 235, 65, // Skip to: 19091 -/* 2216 */ MCD_OPC_Decode, 159, 15, 200, 1, // Opcode: STCH -/* 2221 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 2235 -/* 2226 */ MCD_OPC_CheckPredicate, 11, 221, 65, // Skip to: 19091 -/* 2230 */ MCD_OPC_Decode, 193, 10, 200, 1, // Opcode: LHH -/* 2235 */ MCD_OPC_FilterValue, 198, 1, 9, 0, // Skip to: 2249 -/* 2240 */ MCD_OPC_CheckPredicate, 11, 207, 65, // Skip to: 19091 -/* 2244 */ MCD_OPC_Decode, 215, 10, 200, 1, // Opcode: LLHH -/* 2249 */ MCD_OPC_FilterValue, 199, 1, 9, 0, // Skip to: 2263 -/* 2254 */ MCD_OPC_CheckPredicate, 11, 193, 65, // Skip to: 19091 -/* 2258 */ MCD_OPC_Decode, 184, 15, 200, 1, // Opcode: STHH -/* 2263 */ MCD_OPC_FilterValue, 200, 1, 9, 0, // Skip to: 2277 -/* 2268 */ MCD_OPC_CheckPredicate, 20, 179, 65, // Skip to: 19091 -/* 2272 */ MCD_OPC_Decode, 173, 10, 200, 1, // Opcode: LFHAT -/* 2277 */ MCD_OPC_FilterValue, 202, 1, 9, 0, // Skip to: 2291 -/* 2282 */ MCD_OPC_CheckPredicate, 11, 165, 65, // Skip to: 19091 -/* 2286 */ MCD_OPC_Decode, 172, 10, 200, 1, // Opcode: LFH -/* 2291 */ MCD_OPC_FilterValue, 203, 1, 9, 0, // Skip to: 2305 -/* 2296 */ MCD_OPC_CheckPredicate, 11, 151, 65, // Skip to: 19091 -/* 2300 */ MCD_OPC_Decode, 176, 15, 200, 1, // Opcode: STFH -/* 2305 */ MCD_OPC_FilterValue, 205, 1, 9, 0, // Skip to: 2319 -/* 2310 */ MCD_OPC_CheckPredicate, 11, 137, 65, // Skip to: 19091 -/* 2314 */ MCD_OPC_Decode, 172, 5, 200, 1, // Opcode: CHF -/* 2319 */ MCD_OPC_FilterValue, 207, 1, 127, 65, // Skip to: 19091 -/* 2324 */ MCD_OPC_CheckPredicate, 11, 123, 65, // Skip to: 19091 -/* 2328 */ MCD_OPC_Decode, 234, 6, 200, 1, // Opcode: CLHF -/* 2333 */ MCD_OPC_FilterValue, 229, 1, 155, 0, // Skip to: 2493 -/* 2338 */ MCD_OPC_ExtractField, 32, 8, // Inst{39-32} ... -/* 2341 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 2350 -/* 2345 */ MCD_OPC_Decode, 251, 9, 201, 1, // Opcode: LASP -/* 2350 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 2359 -/* 2354 */ MCD_OPC_Decode, 183, 16, 201, 1, // Opcode: TPROT -/* 2359 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 2368 -/* 2363 */ MCD_OPC_Decode, 135, 16, 201, 1, // Opcode: STRAG -/* 2368 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 2377 -/* 2372 */ MCD_OPC_Decode, 201, 13, 201, 1, // Opcode: MVCSK -/* 2377 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 2386 -/* 2381 */ MCD_OPC_Decode, 192, 13, 201, 1, // Opcode: MVCDK -/* 2386 */ MCD_OPC_FilterValue, 68, 5, 0, // Skip to: 2395 -/* 2390 */ MCD_OPC_Decode, 203, 13, 202, 1, // Opcode: MVHHI -/* 2395 */ MCD_OPC_FilterValue, 72, 5, 0, // Skip to: 2404 -/* 2399 */ MCD_OPC_Decode, 202, 13, 202, 1, // Opcode: MVGHI -/* 2404 */ MCD_OPC_FilterValue, 76, 5, 0, // Skip to: 2413 -/* 2408 */ MCD_OPC_Decode, 204, 13, 202, 1, // Opcode: MVHI -/* 2413 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 2422 -/* 2417 */ MCD_OPC_Decode, 174, 5, 202, 1, // Opcode: CHHSI -/* 2422 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 2431 -/* 2426 */ MCD_OPC_Decode, 236, 6, 203, 1, // Opcode: CLHHSI -/* 2431 */ MCD_OPC_FilterValue, 88, 5, 0, // Skip to: 2440 -/* 2435 */ MCD_OPC_Decode, 207, 4, 202, 1, // Opcode: CGHSI -/* 2440 */ MCD_OPC_FilterValue, 89, 5, 0, // Skip to: 2449 -/* 2444 */ MCD_OPC_Decode, 131, 6, 203, 1, // Opcode: CLGHSI -/* 2449 */ MCD_OPC_FilterValue, 92, 5, 0, // Skip to: 2458 -/* 2453 */ MCD_OPC_Decode, 178, 5, 202, 1, // Opcode: CHSI -/* 2458 */ MCD_OPC_FilterValue, 93, 5, 0, // Skip to: 2467 -/* 2462 */ MCD_OPC_Decode, 232, 5, 203, 1, // Opcode: CLFHSI -/* 2467 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 2480 -/* 2471 */ MCD_OPC_CheckPredicate, 2, 232, 64, // Skip to: 19091 -/* 2475 */ MCD_OPC_Decode, 161, 16, 203, 1, // Opcode: TBEGIN -/* 2480 */ MCD_OPC_FilterValue, 97, 223, 64, // Skip to: 19091 -/* 2484 */ MCD_OPC_CheckPredicate, 2, 219, 64, // Skip to: 19091 -/* 2488 */ MCD_OPC_Decode, 162, 16, 203, 1, // Opcode: TBEGINC -/* 2493 */ MCD_OPC_FilterValue, 230, 1, 35, 2, // Skip to: 3045 -/* 2498 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 2501 */ MCD_OPC_FilterValue, 52, 15, 0, // Skip to: 2520 -/* 2505 */ MCD_OPC_CheckPredicate, 21, 198, 64, // Skip to: 19091 -/* 2509 */ MCD_OPC_CheckField, 9, 3, 0, 192, 64, // Skip to: 19091 -/* 2515 */ MCD_OPC_Decode, 146, 20, 204, 1, // Opcode: VPKZ -/* 2520 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 2539 -/* 2524 */ MCD_OPC_CheckPredicate, 21, 179, 64, // Skip to: 19091 -/* 2528 */ MCD_OPC_CheckField, 9, 3, 0, 173, 64, // Skip to: 19091 -/* 2534 */ MCD_OPC_Decode, 148, 19, 204, 1, // Opcode: VLRL -/* 2539 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 2564 -/* 2543 */ MCD_OPC_CheckPredicate, 21, 160, 64, // Skip to: 19091 -/* 2547 */ MCD_OPC_CheckField, 36, 4, 0, 154, 64, // Skip to: 19091 -/* 2553 */ MCD_OPC_CheckField, 9, 3, 0, 148, 64, // Skip to: 19091 -/* 2559 */ MCD_OPC_Decode, 149, 19, 205, 1, // Opcode: VLRLR -/* 2564 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 2583 -/* 2568 */ MCD_OPC_CheckPredicate, 21, 135, 64, // Skip to: 19091 -/* 2572 */ MCD_OPC_CheckField, 9, 3, 0, 129, 64, // Skip to: 19091 -/* 2578 */ MCD_OPC_Decode, 234, 20, 204, 1, // Opcode: VUPKZ -/* 2583 */ MCD_OPC_FilterValue, 61, 15, 0, // Skip to: 2602 -/* 2587 */ MCD_OPC_CheckPredicate, 21, 116, 64, // Skip to: 19091 -/* 2591 */ MCD_OPC_CheckField, 9, 3, 0, 110, 64, // Skip to: 19091 -/* 2597 */ MCD_OPC_Decode, 217, 20, 204, 1, // Opcode: VSTRL -/* 2602 */ MCD_OPC_FilterValue, 63, 21, 0, // Skip to: 2627 -/* 2606 */ MCD_OPC_CheckPredicate, 21, 97, 64, // Skip to: 19091 -/* 2610 */ MCD_OPC_CheckField, 36, 4, 0, 91, 64, // Skip to: 19091 -/* 2616 */ MCD_OPC_CheckField, 9, 3, 0, 85, 64, // Skip to: 19091 -/* 2622 */ MCD_OPC_Decode, 218, 20, 205, 1, // Opcode: VSTRLR -/* 2627 */ MCD_OPC_FilterValue, 73, 21, 0, // Skip to: 2652 -/* 2631 */ MCD_OPC_CheckPredicate, 21, 72, 64, // Skip to: 19091 -/* 2635 */ MCD_OPC_CheckField, 32, 4, 0, 66, 64, // Skip to: 19091 -/* 2641 */ MCD_OPC_CheckField, 8, 3, 0, 60, 64, // Skip to: 19091 -/* 2647 */ MCD_OPC_Decode, 128, 19, 206, 1, // Opcode: VLIP -/* 2652 */ MCD_OPC_FilterValue, 80, 27, 0, // Skip to: 2683 -/* 2656 */ MCD_OPC_CheckPredicate, 21, 47, 64, // Skip to: 19091 -/* 2660 */ MCD_OPC_CheckField, 24, 8, 0, 41, 64, // Skip to: 19091 -/* 2666 */ MCD_OPC_CheckField, 11, 9, 0, 35, 64, // Skip to: 19091 -/* 2672 */ MCD_OPC_CheckField, 8, 2, 0, 29, 64, // Skip to: 19091 -/* 2678 */ MCD_OPC_Decode, 157, 17, 207, 1, // Opcode: VCVB -/* 2683 */ MCD_OPC_FilterValue, 82, 27, 0, // Skip to: 2714 -/* 2687 */ MCD_OPC_CheckPredicate, 21, 16, 64, // Skip to: 19091 -/* 2691 */ MCD_OPC_CheckField, 24, 8, 0, 10, 64, // Skip to: 19091 -/* 2697 */ MCD_OPC_CheckField, 11, 9, 0, 4, 64, // Skip to: 19091 -/* 2703 */ MCD_OPC_CheckField, 8, 2, 0, 254, 63, // Skip to: 19091 -/* 2709 */ MCD_OPC_Decode, 158, 17, 208, 1, // Opcode: VCVBG -/* 2714 */ MCD_OPC_FilterValue, 88, 21, 0, // Skip to: 2739 -/* 2718 */ MCD_OPC_CheckPredicate, 21, 241, 63, // Skip to: 19091 -/* 2722 */ MCD_OPC_CheckField, 24, 8, 0, 235, 63, // Skip to: 19091 -/* 2728 */ MCD_OPC_CheckField, 8, 3, 0, 229, 63, // Skip to: 19091 -/* 2734 */ MCD_OPC_Decode, 159, 17, 209, 1, // Opcode: VCVD -/* 2739 */ MCD_OPC_FilterValue, 89, 15, 0, // Skip to: 2758 -/* 2743 */ MCD_OPC_CheckPredicate, 21, 216, 63, // Skip to: 19091 -/* 2747 */ MCD_OPC_CheckField, 8, 2, 0, 210, 63, // Skip to: 19091 -/* 2753 */ MCD_OPC_Decode, 196, 20, 210, 1, // Opcode: VSRP -/* 2758 */ MCD_OPC_FilterValue, 90, 21, 0, // Skip to: 2783 -/* 2762 */ MCD_OPC_CheckPredicate, 21, 197, 63, // Skip to: 19091 -/* 2766 */ MCD_OPC_CheckField, 24, 8, 0, 191, 63, // Skip to: 19091 -/* 2772 */ MCD_OPC_CheckField, 8, 3, 0, 185, 63, // Skip to: 19091 -/* 2778 */ MCD_OPC_Decode, 160, 17, 211, 1, // Opcode: VCVDG -/* 2783 */ MCD_OPC_FilterValue, 91, 15, 0, // Skip to: 2802 -/* 2787 */ MCD_OPC_CheckPredicate, 21, 172, 63, // Skip to: 19091 -/* 2791 */ MCD_OPC_CheckField, 8, 2, 0, 166, 63, // Skip to: 19091 -/* 2797 */ MCD_OPC_Decode, 152, 20, 210, 1, // Opcode: VPSOP -/* 2802 */ MCD_OPC_FilterValue, 95, 27, 0, // Skip to: 2833 -/* 2806 */ MCD_OPC_CheckPredicate, 21, 153, 63, // Skip to: 19091 -/* 2810 */ MCD_OPC_CheckField, 36, 4, 0, 147, 63, // Skip to: 19091 -/* 2816 */ MCD_OPC_CheckField, 11, 21, 0, 141, 63, // Skip to: 19091 -/* 2822 */ MCD_OPC_CheckField, 8, 2, 0, 135, 63, // Skip to: 19091 -/* 2828 */ MCD_OPC_Decode, 229, 20, 212, 1, // Opcode: VTP -/* 2833 */ MCD_OPC_FilterValue, 113, 21, 0, // Skip to: 2858 -/* 2837 */ MCD_OPC_CheckPredicate, 21, 122, 63, // Skip to: 19091 -/* 2841 */ MCD_OPC_CheckField, 24, 4, 0, 116, 63, // Skip to: 19091 -/* 2847 */ MCD_OPC_CheckField, 8, 1, 0, 110, 63, // Skip to: 19091 -/* 2853 */ MCD_OPC_Decode, 225, 16, 213, 1, // Opcode: VAP -/* 2858 */ MCD_OPC_FilterValue, 115, 21, 0, // Skip to: 2883 -/* 2862 */ MCD_OPC_CheckPredicate, 21, 97, 63, // Skip to: 19091 -/* 2866 */ MCD_OPC_CheckField, 24, 4, 0, 91, 63, // Skip to: 19091 -/* 2872 */ MCD_OPC_CheckField, 8, 1, 0, 85, 63, // Skip to: 19091 -/* 2878 */ MCD_OPC_Decode, 190, 20, 213, 1, // Opcode: VSP -/* 2883 */ MCD_OPC_FilterValue, 119, 33, 0, // Skip to: 2920 -/* 2887 */ MCD_OPC_CheckPredicate, 21, 72, 63, // Skip to: 19091 -/* 2891 */ MCD_OPC_CheckField, 36, 4, 0, 66, 63, // Skip to: 19091 -/* 2897 */ MCD_OPC_CheckField, 24, 4, 0, 60, 63, // Skip to: 19091 -/* 2903 */ MCD_OPC_CheckField, 11, 9, 0, 54, 63, // Skip to: 19091 -/* 2909 */ MCD_OPC_CheckField, 8, 1, 0, 48, 63, // Skip to: 19091 -/* 2915 */ MCD_OPC_Decode, 151, 17, 214, 1, // Opcode: VCP -/* 2920 */ MCD_OPC_FilterValue, 120, 21, 0, // Skip to: 2945 -/* 2924 */ MCD_OPC_CheckPredicate, 21, 35, 63, // Skip to: 19091 -/* 2928 */ MCD_OPC_CheckField, 24, 4, 0, 29, 63, // Skip to: 19091 -/* 2934 */ MCD_OPC_CheckField, 8, 1, 0, 23, 63, // Skip to: 19091 -/* 2940 */ MCD_OPC_Decode, 222, 19, 213, 1, // Opcode: VMP -/* 2945 */ MCD_OPC_FilterValue, 121, 21, 0, // Skip to: 2970 -/* 2949 */ MCD_OPC_CheckPredicate, 21, 10, 63, // Skip to: 19091 -/* 2953 */ MCD_OPC_CheckField, 24, 4, 0, 4, 63, // Skip to: 19091 -/* 2959 */ MCD_OPC_CheckField, 8, 1, 0, 254, 62, // Skip to: 19091 -/* 2965 */ MCD_OPC_Decode, 235, 19, 213, 1, // Opcode: VMSP -/* 2970 */ MCD_OPC_FilterValue, 122, 21, 0, // Skip to: 2995 -/* 2974 */ MCD_OPC_CheckPredicate, 21, 241, 62, // Skip to: 19091 -/* 2978 */ MCD_OPC_CheckField, 24, 4, 0, 235, 62, // Skip to: 19091 -/* 2984 */ MCD_OPC_CheckField, 8, 1, 0, 229, 62, // Skip to: 19091 -/* 2990 */ MCD_OPC_Decode, 161, 17, 213, 1, // Opcode: VDP -/* 2995 */ MCD_OPC_FilterValue, 123, 21, 0, // Skip to: 3020 -/* 2999 */ MCD_OPC_CheckPredicate, 21, 216, 62, // Skip to: 19091 -/* 3003 */ MCD_OPC_CheckField, 24, 4, 0, 210, 62, // Skip to: 19091 -/* 3009 */ MCD_OPC_CheckField, 8, 1, 0, 204, 62, // Skip to: 19091 -/* 3015 */ MCD_OPC_Decode, 163, 20, 213, 1, // Opcode: VRP -/* 3020 */ MCD_OPC_FilterValue, 126, 195, 62, // Skip to: 19091 -/* 3024 */ MCD_OPC_CheckPredicate, 21, 191, 62, // Skip to: 19091 -/* 3028 */ MCD_OPC_CheckField, 24, 4, 0, 185, 62, // Skip to: 19091 -/* 3034 */ MCD_OPC_CheckField, 8, 1, 0, 179, 62, // Skip to: 19091 -/* 3040 */ MCD_OPC_Decode, 178, 20, 213, 1, // Opcode: VSDP -/* 3045 */ MCD_OPC_FilterValue, 231, 1, 216, 41, // Skip to: 13762 -/* 3050 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 3053 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3072 -/* 3057 */ MCD_OPC_CheckPredicate, 22, 158, 62, // Skip to: 19091 -/* 3061 */ MCD_OPC_CheckField, 8, 3, 0, 152, 62, // Skip to: 19091 -/* 3067 */ MCD_OPC_Decode, 241, 18, 215, 1, // Opcode: VLEB -/* 3072 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 3091 -/* 3076 */ MCD_OPC_CheckPredicate, 22, 139, 62, // Skip to: 19091 -/* 3080 */ MCD_OPC_CheckField, 8, 3, 0, 133, 62, // Skip to: 19091 -/* 3086 */ MCD_OPC_Decode, 246, 18, 216, 1, // Opcode: VLEH -/* 3091 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3110 -/* 3095 */ MCD_OPC_CheckPredicate, 22, 120, 62, // Skip to: 19091 -/* 3099 */ MCD_OPC_CheckField, 8, 3, 0, 114, 62, // Skip to: 19091 -/* 3105 */ MCD_OPC_Decode, 245, 18, 217, 1, // Opcode: VLEG -/* 3110 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 3129 -/* 3114 */ MCD_OPC_CheckPredicate, 22, 101, 62, // Skip to: 19091 -/* 3118 */ MCD_OPC_CheckField, 8, 3, 0, 95, 62, // Skip to: 19091 -/* 3124 */ MCD_OPC_Decode, 244, 18, 218, 1, // Opcode: VLEF -/* 3129 */ MCD_OPC_FilterValue, 4, 84, 0, // Skip to: 3217 -/* 3133 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 3136 */ MCD_OPC_FilterValue, 0, 79, 62, // Skip to: 19091 -/* 3140 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3143 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3156 -/* 3147 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 3208 -/* 3151 */ MCD_OPC_Decode, 131, 19, 219, 1, // Opcode: VLLEZB -/* 3156 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3169 -/* 3160 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3208 -/* 3164 */ MCD_OPC_Decode, 134, 19, 219, 1, // Opcode: VLLEZH -/* 3169 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3182 -/* 3173 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3208 -/* 3177 */ MCD_OPC_Decode, 132, 19, 219, 1, // Opcode: VLLEZF -/* 3182 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3195 -/* 3186 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3208 -/* 3190 */ MCD_OPC_Decode, 133, 19, 219, 1, // Opcode: VLLEZG -/* 3195 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 3208 -/* 3199 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 3208 -/* 3203 */ MCD_OPC_Decode, 135, 19, 219, 1, // Opcode: VLLEZLF -/* 3208 */ MCD_OPC_CheckPredicate, 22, 7, 62, // Skip to: 19091 -/* 3212 */ MCD_OPC_Decode, 130, 19, 220, 1, // Opcode: VLLEZ -/* 3217 */ MCD_OPC_FilterValue, 5, 71, 0, // Skip to: 3292 -/* 3221 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 3224 */ MCD_OPC_FilterValue, 0, 247, 61, // Skip to: 19091 -/* 3228 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3231 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3244 -/* 3235 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3283 -/* 3239 */ MCD_OPC_Decode, 144, 19, 219, 1, // Opcode: VLREPB -/* 3244 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3257 -/* 3248 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3283 -/* 3252 */ MCD_OPC_Decode, 147, 19, 219, 1, // Opcode: VLREPH -/* 3257 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3270 -/* 3261 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3283 -/* 3265 */ MCD_OPC_Decode, 145, 19, 219, 1, // Opcode: VLREPF -/* 3270 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3283 -/* 3274 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3283 -/* 3278 */ MCD_OPC_Decode, 146, 19, 219, 1, // Opcode: VLREPG -/* 3283 */ MCD_OPC_CheckPredicate, 22, 188, 61, // Skip to: 19091 -/* 3287 */ MCD_OPC_Decode, 143, 19, 220, 1, // Opcode: VLREP -/* 3292 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 3317 -/* 3296 */ MCD_OPC_CheckPredicate, 22, 175, 61, // Skip to: 19091 -/* 3300 */ MCD_OPC_CheckField, 12, 4, 0, 169, 61, // Skip to: 19091 -/* 3306 */ MCD_OPC_CheckField, 8, 3, 0, 163, 61, // Skip to: 19091 -/* 3312 */ MCD_OPC_Decode, 232, 18, 219, 1, // Opcode: VL -/* 3317 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 3336 -/* 3321 */ MCD_OPC_CheckPredicate, 22, 150, 61, // Skip to: 19091 -/* 3325 */ MCD_OPC_CheckField, 8, 3, 0, 144, 61, // Skip to: 19091 -/* 3331 */ MCD_OPC_Decode, 233, 18, 220, 1, // Opcode: VLBB -/* 3336 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 3355 -/* 3340 */ MCD_OPC_CheckPredicate, 22, 131, 61, // Skip to: 19091 -/* 3344 */ MCD_OPC_CheckField, 8, 3, 0, 125, 61, // Skip to: 19091 -/* 3350 */ MCD_OPC_Decode, 198, 20, 220, 1, // Opcode: VSTEB -/* 3355 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 3374 -/* 3359 */ MCD_OPC_CheckPredicate, 22, 112, 61, // Skip to: 19091 -/* 3363 */ MCD_OPC_CheckField, 8, 3, 0, 106, 61, // Skip to: 19091 -/* 3369 */ MCD_OPC_Decode, 201, 20, 221, 1, // Opcode: VSTEH -/* 3374 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 3393 -/* 3378 */ MCD_OPC_CheckPredicate, 22, 93, 61, // Skip to: 19091 -/* 3382 */ MCD_OPC_CheckField, 8, 3, 0, 87, 61, // Skip to: 19091 -/* 3388 */ MCD_OPC_Decode, 200, 20, 222, 1, // Opcode: VSTEG -/* 3393 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 3412 -/* 3397 */ MCD_OPC_CheckPredicate, 22, 74, 61, // Skip to: 19091 -/* 3401 */ MCD_OPC_CheckField, 8, 3, 0, 68, 61, // Skip to: 19091 -/* 3407 */ MCD_OPC_Decode, 199, 20, 223, 1, // Opcode: VSTEF -/* 3412 */ MCD_OPC_FilterValue, 14, 21, 0, // Skip to: 3437 -/* 3416 */ MCD_OPC_CheckPredicate, 22, 55, 61, // Skip to: 19091 -/* 3420 */ MCD_OPC_CheckField, 12, 4, 0, 49, 61, // Skip to: 19091 -/* 3426 */ MCD_OPC_CheckField, 8, 3, 0, 43, 61, // Skip to: 19091 -/* 3432 */ MCD_OPC_Decode, 197, 20, 219, 1, // Opcode: VST -/* 3437 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 3456 -/* 3441 */ MCD_OPC_CheckPredicate, 22, 30, 61, // Skip to: 19091 -/* 3445 */ MCD_OPC_CheckField, 8, 2, 0, 24, 61, // Skip to: 19091 -/* 3451 */ MCD_OPC_Decode, 209, 18, 224, 1, // Opcode: VGEG -/* 3456 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 3475 -/* 3460 */ MCD_OPC_CheckPredicate, 22, 11, 61, // Skip to: 19091 -/* 3464 */ MCD_OPC_CheckField, 8, 2, 0, 5, 61, // Skip to: 19091 -/* 3470 */ MCD_OPC_Decode, 208, 18, 225, 1, // Opcode: VGEF -/* 3475 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 3494 -/* 3479 */ MCD_OPC_CheckPredicate, 22, 248, 60, // Skip to: 19091 -/* 3483 */ MCD_OPC_CheckField, 8, 2, 0, 242, 60, // Skip to: 19091 -/* 3489 */ MCD_OPC_Decode, 177, 20, 226, 1, // Opcode: VSCEG -/* 3494 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 3513 -/* 3498 */ MCD_OPC_CheckPredicate, 22, 229, 60, // Skip to: 19091 -/* 3502 */ MCD_OPC_CheckField, 8, 2, 0, 223, 60, // Skip to: 19091 -/* 3508 */ MCD_OPC_Decode, 176, 20, 227, 1, // Opcode: VSCEF -/* 3513 */ MCD_OPC_FilterValue, 33, 78, 0, // Skip to: 3595 -/* 3517 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3520 */ MCD_OPC_FilterValue, 0, 207, 60, // Skip to: 19091 -/* 3524 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... -/* 3527 */ MCD_OPC_FilterValue, 0, 200, 60, // Skip to: 19091 -/* 3531 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3534 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3547 -/* 3538 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3586 -/* 3542 */ MCD_OPC_Decode, 252, 18, 228, 1, // Opcode: VLGVB -/* 3547 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3560 -/* 3551 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3586 -/* 3555 */ MCD_OPC_Decode, 255, 18, 228, 1, // Opcode: VLGVH -/* 3560 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3573 -/* 3564 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3586 -/* 3568 */ MCD_OPC_Decode, 253, 18, 228, 1, // Opcode: VLGVF -/* 3573 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3586 -/* 3577 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3586 -/* 3581 */ MCD_OPC_Decode, 254, 18, 228, 1, // Opcode: VLGVG -/* 3586 */ MCD_OPC_CheckPredicate, 22, 141, 60, // Skip to: 19091 -/* 3590 */ MCD_OPC_Decode, 251, 18, 229, 1, // Opcode: VLGV -/* 3595 */ MCD_OPC_FilterValue, 34, 71, 0, // Skip to: 3670 -/* 3599 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 3602 */ MCD_OPC_FilterValue, 0, 125, 60, // Skip to: 19091 -/* 3606 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3609 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3622 -/* 3613 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3661 -/* 3617 */ MCD_OPC_Decode, 151, 19, 230, 1, // Opcode: VLVGB -/* 3622 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3635 -/* 3626 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3661 -/* 3630 */ MCD_OPC_Decode, 154, 19, 230, 1, // Opcode: VLVGH -/* 3635 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3648 -/* 3639 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3661 -/* 3643 */ MCD_OPC_Decode, 152, 19, 230, 1, // Opcode: VLVGF -/* 3648 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3661 -/* 3652 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3661 -/* 3656 */ MCD_OPC_Decode, 153, 19, 231, 1, // Opcode: VLVGG -/* 3661 */ MCD_OPC_CheckPredicate, 22, 66, 60, // Skip to: 19091 -/* 3665 */ MCD_OPC_Decode, 150, 19, 232, 1, // Opcode: VLVG -/* 3670 */ MCD_OPC_FilterValue, 39, 15, 0, // Skip to: 3689 -/* 3674 */ MCD_OPC_CheckPredicate, 22, 53, 60, // Skip to: 19091 -/* 3678 */ MCD_OPC_CheckField, 8, 4, 0, 47, 60, // Skip to: 19091 -/* 3684 */ MCD_OPC_Decode, 131, 10, 233, 1, // Opcode: LCBB -/* 3689 */ MCD_OPC_FilterValue, 48, 71, 0, // Skip to: 3764 -/* 3693 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3696 */ MCD_OPC_FilterValue, 0, 31, 60, // Skip to: 19091 -/* 3700 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3703 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3716 -/* 3707 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3755 -/* 3711 */ MCD_OPC_Decode, 188, 17, 234, 1, // Opcode: VESLB -/* 3716 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3729 -/* 3720 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3755 -/* 3724 */ MCD_OPC_Decode, 191, 17, 234, 1, // Opcode: VESLH -/* 3729 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3742 -/* 3733 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3755 -/* 3737 */ MCD_OPC_Decode, 189, 17, 234, 1, // Opcode: VESLF -/* 3742 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3755 -/* 3746 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3755 -/* 3750 */ MCD_OPC_Decode, 190, 17, 234, 1, // Opcode: VESLG -/* 3755 */ MCD_OPC_CheckPredicate, 22, 228, 59, // Skip to: 19091 -/* 3759 */ MCD_OPC_Decode, 187, 17, 235, 1, // Opcode: VESL -/* 3764 */ MCD_OPC_FilterValue, 51, 71, 0, // Skip to: 3839 -/* 3768 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3771 */ MCD_OPC_FilterValue, 0, 212, 59, // Skip to: 19091 -/* 3775 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3778 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3791 -/* 3782 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3830 -/* 3786 */ MCD_OPC_Decode, 178, 17, 234, 1, // Opcode: VERLLB -/* 3791 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3804 -/* 3795 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3830 -/* 3799 */ MCD_OPC_Decode, 181, 17, 234, 1, // Opcode: VERLLH -/* 3804 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3817 -/* 3808 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3830 -/* 3812 */ MCD_OPC_Decode, 179, 17, 234, 1, // Opcode: VERLLF -/* 3817 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3830 -/* 3821 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3830 -/* 3825 */ MCD_OPC_Decode, 180, 17, 234, 1, // Opcode: VERLLG -/* 3830 */ MCD_OPC_CheckPredicate, 22, 153, 59, // Skip to: 19091 -/* 3834 */ MCD_OPC_Decode, 177, 17, 235, 1, // Opcode: VERLL -/* 3839 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 3864 -/* 3843 */ MCD_OPC_CheckPredicate, 22, 140, 59, // Skip to: 19091 -/* 3847 */ MCD_OPC_CheckField, 12, 4, 0, 134, 59, // Skip to: 19091 -/* 3853 */ MCD_OPC_CheckField, 8, 2, 0, 128, 59, // Skip to: 19091 -/* 3859 */ MCD_OPC_Decode, 136, 19, 236, 1, // Opcode: VLM -/* 3864 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 3889 -/* 3868 */ MCD_OPC_CheckPredicate, 22, 115, 59, // Skip to: 19091 -/* 3872 */ MCD_OPC_CheckField, 12, 4, 0, 109, 59, // Skip to: 19091 -/* 3878 */ MCD_OPC_CheckField, 8, 3, 0, 103, 59, // Skip to: 19091 -/* 3884 */ MCD_OPC_Decode, 129, 19, 237, 1, // Opcode: VLL -/* 3889 */ MCD_OPC_FilterValue, 56, 71, 0, // Skip to: 3964 -/* 3893 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3896 */ MCD_OPC_FilterValue, 0, 87, 59, // Skip to: 19091 -/* 3900 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3903 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3916 -/* 3907 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3955 -/* 3911 */ MCD_OPC_Decode, 208, 17, 234, 1, // Opcode: VESRLB -/* 3916 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3929 -/* 3920 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3955 -/* 3924 */ MCD_OPC_Decode, 211, 17, 234, 1, // Opcode: VESRLH -/* 3929 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3942 -/* 3933 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3955 -/* 3937 */ MCD_OPC_Decode, 209, 17, 234, 1, // Opcode: VESRLF -/* 3942 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3955 -/* 3946 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3955 -/* 3950 */ MCD_OPC_Decode, 210, 17, 234, 1, // Opcode: VESRLG -/* 3955 */ MCD_OPC_CheckPredicate, 22, 28, 59, // Skip to: 19091 -/* 3959 */ MCD_OPC_Decode, 207, 17, 235, 1, // Opcode: VESRL -/* 3964 */ MCD_OPC_FilterValue, 58, 71, 0, // Skip to: 4039 -/* 3968 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 3971 */ MCD_OPC_FilterValue, 0, 12, 59, // Skip to: 19091 -/* 3975 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 3978 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3991 -/* 3982 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4030 -/* 3986 */ MCD_OPC_Decode, 198, 17, 234, 1, // Opcode: VESRAB -/* 3991 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4004 -/* 3995 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4030 -/* 3999 */ MCD_OPC_Decode, 201, 17, 234, 1, // Opcode: VESRAH -/* 4004 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4017 -/* 4008 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4030 -/* 4012 */ MCD_OPC_Decode, 199, 17, 234, 1, // Opcode: VESRAF -/* 4017 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4030 -/* 4021 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4030 -/* 4025 */ MCD_OPC_Decode, 200, 17, 234, 1, // Opcode: VESRAG -/* 4030 */ MCD_OPC_CheckPredicate, 22, 209, 58, // Skip to: 19091 -/* 4034 */ MCD_OPC_Decode, 197, 17, 235, 1, // Opcode: VESRA -/* 4039 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 4064 -/* 4043 */ MCD_OPC_CheckPredicate, 22, 196, 58, // Skip to: 19091 -/* 4047 */ MCD_OPC_CheckField, 12, 4, 0, 190, 58, // Skip to: 19091 -/* 4053 */ MCD_OPC_CheckField, 8, 2, 0, 184, 58, // Skip to: 19091 -/* 4059 */ MCD_OPC_Decode, 203, 20, 236, 1, // Opcode: VSTM -/* 4064 */ MCD_OPC_FilterValue, 63, 21, 0, // Skip to: 4089 -/* 4068 */ MCD_OPC_CheckPredicate, 22, 171, 58, // Skip to: 19091 -/* 4072 */ MCD_OPC_CheckField, 12, 4, 0, 165, 58, // Skip to: 19091 -/* 4078 */ MCD_OPC_CheckField, 8, 3, 0, 159, 58, // Skip to: 19091 -/* 4084 */ MCD_OPC_Decode, 202, 20, 237, 1, // Opcode: VSTL -/* 4089 */ MCD_OPC_FilterValue, 64, 21, 0, // Skip to: 4114 -/* 4093 */ MCD_OPC_CheckPredicate, 22, 146, 58, // Skip to: 19091 -/* 4097 */ MCD_OPC_CheckField, 32, 4, 0, 140, 58, // Skip to: 19091 -/* 4103 */ MCD_OPC_CheckField, 8, 3, 0, 134, 58, // Skip to: 19091 -/* 4109 */ MCD_OPC_Decode, 247, 18, 238, 1, // Opcode: VLEIB -/* 4114 */ MCD_OPC_FilterValue, 65, 21, 0, // Skip to: 4139 -/* 4118 */ MCD_OPC_CheckPredicate, 22, 121, 58, // Skip to: 19091 -/* 4122 */ MCD_OPC_CheckField, 32, 4, 0, 115, 58, // Skip to: 19091 -/* 4128 */ MCD_OPC_CheckField, 8, 3, 0, 109, 58, // Skip to: 19091 -/* 4134 */ MCD_OPC_Decode, 250, 18, 239, 1, // Opcode: VLEIH -/* 4139 */ MCD_OPC_FilterValue, 66, 21, 0, // Skip to: 4164 -/* 4143 */ MCD_OPC_CheckPredicate, 22, 96, 58, // Skip to: 19091 -/* 4147 */ MCD_OPC_CheckField, 32, 4, 0, 90, 58, // Skip to: 19091 -/* 4153 */ MCD_OPC_CheckField, 8, 3, 0, 84, 58, // Skip to: 19091 -/* 4159 */ MCD_OPC_Decode, 249, 18, 240, 1, // Opcode: VLEIG -/* 4164 */ MCD_OPC_FilterValue, 67, 21, 0, // Skip to: 4189 -/* 4168 */ MCD_OPC_CheckPredicate, 22, 71, 58, // Skip to: 19091 -/* 4172 */ MCD_OPC_CheckField, 32, 4, 0, 65, 58, // Skip to: 19091 -/* 4178 */ MCD_OPC_CheckField, 8, 3, 0, 59, 58, // Skip to: 19091 -/* 4184 */ MCD_OPC_Decode, 248, 18, 241, 1, // Opcode: VLEIF -/* 4189 */ MCD_OPC_FilterValue, 68, 61, 0, // Skip to: 4254 -/* 4193 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 4196 */ MCD_OPC_FilterValue, 0, 43, 58, // Skip to: 19091 -/* 4200 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4203 */ MCD_OPC_FilterValue, 0, 36, 58, // Skip to: 19091 -/* 4207 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 4210 */ MCD_OPC_FilterValue, 0, 29, 58, // Skip to: 19091 -/* 4214 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4217 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4230 -/* 4221 */ MCD_OPC_CheckPredicate, 22, 20, 0, // Skip to: 4245 -/* 4225 */ MCD_OPC_Decode, 248, 20, 242, 1, // Opcode: VZERO -/* 4230 */ MCD_OPC_FilterValue, 255, 255, 3, 9, 0, // Skip to: 4245 -/* 4236 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4245 -/* 4240 */ MCD_OPC_Decode, 253, 19, 242, 1, // Opcode: VONE -/* 4245 */ MCD_OPC_CheckPredicate, 22, 250, 57, // Skip to: 19091 -/* 4249 */ MCD_OPC_Decode, 207, 18, 243, 1, // Opcode: VGBM -/* 4254 */ MCD_OPC_FilterValue, 69, 78, 0, // Skip to: 4336 -/* 4258 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 4261 */ MCD_OPC_FilterValue, 0, 234, 57, // Skip to: 19091 -/* 4265 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 4268 */ MCD_OPC_FilterValue, 0, 227, 57, // Skip to: 19091 -/* 4272 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4275 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4288 -/* 4279 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4327 -/* 4283 */ MCD_OPC_Decode, 159, 20, 244, 1, // Opcode: VREPIB -/* 4288 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4301 -/* 4292 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4327 -/* 4296 */ MCD_OPC_Decode, 162, 20, 244, 1, // Opcode: VREPIH -/* 4301 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4314 -/* 4305 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4327 -/* 4309 */ MCD_OPC_Decode, 160, 20, 244, 1, // Opcode: VREPIF -/* 4314 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4327 -/* 4318 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4327 -/* 4322 */ MCD_OPC_Decode, 161, 20, 244, 1, // Opcode: VREPIG -/* 4327 */ MCD_OPC_CheckPredicate, 22, 168, 57, // Skip to: 19091 -/* 4331 */ MCD_OPC_Decode, 158, 20, 245, 1, // Opcode: VREPI -/* 4336 */ MCD_OPC_FilterValue, 70, 78, 0, // Skip to: 4418 -/* 4340 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... -/* 4343 */ MCD_OPC_FilterValue, 0, 152, 57, // Skip to: 19091 -/* 4347 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 4350 */ MCD_OPC_FilterValue, 0, 145, 57, // Skip to: 19091 -/* 4354 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4357 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4370 -/* 4361 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4409 -/* 4365 */ MCD_OPC_Decode, 221, 18, 246, 1, // Opcode: VGMB -/* 4370 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4383 -/* 4374 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4409 -/* 4378 */ MCD_OPC_Decode, 224, 18, 246, 1, // Opcode: VGMH -/* 4383 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4396 -/* 4387 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4409 -/* 4391 */ MCD_OPC_Decode, 222, 18, 246, 1, // Opcode: VGMF -/* 4396 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4409 -/* 4400 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4409 -/* 4404 */ MCD_OPC_Decode, 223, 18, 246, 1, // Opcode: VGMG -/* 4409 */ MCD_OPC_CheckPredicate, 22, 86, 57, // Skip to: 19091 -/* 4413 */ MCD_OPC_Decode, 220, 18, 247, 1, // Opcode: VGM -/* 4418 */ MCD_OPC_FilterValue, 74, 87, 0, // Skip to: 4509 -/* 4422 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4425 */ MCD_OPC_FilterValue, 0, 70, 57, // Skip to: 19091 -/* 4429 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 4432 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4445 -/* 4436 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 4500 -/* 4440 */ MCD_OPC_Decode, 206, 18, 248, 1, // Opcode: VFTCISB -/* 4445 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4458 -/* 4449 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 4500 -/* 4453 */ MCD_OPC_Decode, 205, 18, 248, 1, // Opcode: VFTCIDB -/* 4458 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 4472 -/* 4463 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 4500 -/* 4467 */ MCD_OPC_Decode, 222, 21, 249, 1, // Opcode: WFTCISB -/* 4472 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 4486 -/* 4477 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 4500 -/* 4481 */ MCD_OPC_Decode, 221, 21, 250, 1, // Opcode: WFTCIDB -/* 4486 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 4500 -/* 4491 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 4500 -/* 4495 */ MCD_OPC_Decode, 223, 21, 248, 1, // Opcode: WFTCIXB -/* 4500 */ MCD_OPC_CheckPredicate, 22, 251, 56, // Skip to: 19091 -/* 4504 */ MCD_OPC_Decode, 204, 18, 251, 1, // Opcode: VFTCI -/* 4509 */ MCD_OPC_FilterValue, 77, 71, 0, // Skip to: 4584 -/* 4513 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4516 */ MCD_OPC_FilterValue, 0, 235, 56, // Skip to: 19091 -/* 4520 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4523 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4536 -/* 4527 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4575 -/* 4531 */ MCD_OPC_Decode, 154, 20, 252, 1, // Opcode: VREPB -/* 4536 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4549 -/* 4540 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4575 -/* 4544 */ MCD_OPC_Decode, 157, 20, 252, 1, // Opcode: VREPH -/* 4549 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4562 -/* 4553 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4575 -/* 4557 */ MCD_OPC_Decode, 155, 20, 252, 1, // Opcode: VREPF -/* 4562 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4575 -/* 4566 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4575 -/* 4570 */ MCD_OPC_Decode, 156, 20, 252, 1, // Opcode: VREPG -/* 4575 */ MCD_OPC_CheckPredicate, 22, 176, 56, // Skip to: 19091 -/* 4579 */ MCD_OPC_Decode, 153, 20, 253, 1, // Opcode: VREP -/* 4584 */ MCD_OPC_FilterValue, 80, 78, 0, // Skip to: 4666 -/* 4588 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4591 */ MCD_OPC_FilterValue, 0, 160, 56, // Skip to: 19091 -/* 4595 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4598 */ MCD_OPC_FilterValue, 0, 153, 56, // Skip to: 19091 -/* 4602 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4605 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4618 -/* 4609 */ MCD_OPC_CheckPredicate, 23, 44, 0, // Skip to: 4657 -/* 4613 */ MCD_OPC_Decode, 148, 20, 254, 1, // Opcode: VPOPCTB -/* 4618 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4631 -/* 4622 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 4657 -/* 4626 */ MCD_OPC_Decode, 151, 20, 254, 1, // Opcode: VPOPCTH -/* 4631 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4644 -/* 4635 */ MCD_OPC_CheckPredicate, 23, 18, 0, // Skip to: 4657 -/* 4639 */ MCD_OPC_Decode, 149, 20, 254, 1, // Opcode: VPOPCTF -/* 4644 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4657 -/* 4648 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 4657 -/* 4652 */ MCD_OPC_Decode, 150, 20, 254, 1, // Opcode: VPOPCTG -/* 4657 */ MCD_OPC_CheckPredicate, 22, 94, 56, // Skip to: 19091 -/* 4661 */ MCD_OPC_Decode, 147, 20, 255, 1, // Opcode: VPOPCT -/* 4666 */ MCD_OPC_FilterValue, 82, 78, 0, // Skip to: 4748 -/* 4670 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4673 */ MCD_OPC_FilterValue, 0, 78, 56, // Skip to: 19091 -/* 4677 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4680 */ MCD_OPC_FilterValue, 0, 71, 56, // Skip to: 19091 -/* 4684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4687 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4700 -/* 4691 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4739 -/* 4695 */ MCD_OPC_Decode, 153, 17, 254, 1, // Opcode: VCTZB -/* 4700 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4713 -/* 4704 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4739 -/* 4708 */ MCD_OPC_Decode, 156, 17, 254, 1, // Opcode: VCTZH -/* 4713 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4726 -/* 4717 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4739 -/* 4721 */ MCD_OPC_Decode, 154, 17, 254, 1, // Opcode: VCTZF -/* 4726 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4739 -/* 4730 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4739 -/* 4734 */ MCD_OPC_Decode, 155, 17, 254, 1, // Opcode: VCTZG -/* 4739 */ MCD_OPC_CheckPredicate, 22, 12, 56, // Skip to: 19091 -/* 4743 */ MCD_OPC_Decode, 152, 17, 255, 1, // Opcode: VCTZ -/* 4748 */ MCD_OPC_FilterValue, 83, 78, 0, // Skip to: 4830 -/* 4752 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4755 */ MCD_OPC_FilterValue, 0, 252, 55, // Skip to: 19091 -/* 4759 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4762 */ MCD_OPC_FilterValue, 0, 245, 55, // Skip to: 19091 -/* 4766 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4769 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4782 -/* 4773 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4821 -/* 4777 */ MCD_OPC_Decode, 147, 17, 254, 1, // Opcode: VCLZB -/* 4782 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4795 -/* 4786 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4821 -/* 4790 */ MCD_OPC_Decode, 150, 17, 254, 1, // Opcode: VCLZH -/* 4795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4808 -/* 4799 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4821 -/* 4803 */ MCD_OPC_Decode, 148, 17, 254, 1, // Opcode: VCLZF -/* 4808 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4821 -/* 4812 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4821 -/* 4816 */ MCD_OPC_Decode, 149, 17, 254, 1, // Opcode: VCLZG -/* 4821 */ MCD_OPC_CheckPredicate, 22, 186, 55, // Skip to: 19091 -/* 4825 */ MCD_OPC_Decode, 146, 17, 255, 1, // Opcode: VCLZ -/* 4830 */ MCD_OPC_FilterValue, 86, 21, 0, // Skip to: 4855 -/* 4834 */ MCD_OPC_CheckPredicate, 22, 173, 55, // Skip to: 19091 -/* 4838 */ MCD_OPC_CheckField, 12, 20, 0, 167, 55, // Skip to: 19091 -/* 4844 */ MCD_OPC_CheckField, 8, 2, 0, 161, 55, // Skip to: 19091 -/* 4850 */ MCD_OPC_Decode, 142, 19, 254, 1, // Opcode: VLR -/* 4855 */ MCD_OPC_FilterValue, 92, 117, 0, // Skip to: 4976 -/* 4859 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4862 */ MCD_OPC_FilterValue, 0, 145, 55, // Skip to: 19091 -/* 4866 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 4869 */ MCD_OPC_FilterValue, 0, 138, 55, // Skip to: 19091 -/* 4873 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 4876 */ MCD_OPC_FilterValue, 0, 131, 55, // Skip to: 19091 -/* 4880 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4883 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4911 -/* 4887 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4902 -/* 4891 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4902 -/* 4897 */ MCD_OPC_Decode, 227, 18, 254, 1, // Opcode: VISTRBS -/* 4902 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 4967 -/* 4906 */ MCD_OPC_Decode, 226, 18, 128, 2, // Opcode: VISTRB -/* 4911 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 4939 -/* 4915 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4930 -/* 4919 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4930 -/* 4925 */ MCD_OPC_Decode, 231, 18, 254, 1, // Opcode: VISTRHS -/* 4930 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 4967 -/* 4934 */ MCD_OPC_Decode, 230, 18, 128, 2, // Opcode: VISTRH -/* 4939 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 4967 -/* 4943 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4958 -/* 4947 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4958 -/* 4953 */ MCD_OPC_Decode, 229, 18, 254, 1, // Opcode: VISTRFS -/* 4958 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4967 -/* 4962 */ MCD_OPC_Decode, 228, 18, 128, 2, // Opcode: VISTRF -/* 4967 */ MCD_OPC_CheckPredicate, 22, 40, 55, // Skip to: 19091 -/* 4971 */ MCD_OPC_Decode, 225, 18, 129, 2, // Opcode: VISTR -/* 4976 */ MCD_OPC_FilterValue, 95, 65, 0, // Skip to: 5045 -/* 4980 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 4983 */ MCD_OPC_FilterValue, 0, 24, 55, // Skip to: 19091 -/* 4987 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 4990 */ MCD_OPC_FilterValue, 0, 17, 55, // Skip to: 19091 -/* 4994 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 4997 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5010 -/* 5001 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5036 -/* 5005 */ MCD_OPC_Decode, 180, 20, 254, 1, // Opcode: VSEGB -/* 5010 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5023 -/* 5014 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5036 -/* 5018 */ MCD_OPC_Decode, 182, 20, 254, 1, // Opcode: VSEGH -/* 5023 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5036 -/* 5027 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5036 -/* 5031 */ MCD_OPC_Decode, 181, 20, 254, 1, // Opcode: VSEGF -/* 5036 */ MCD_OPC_CheckPredicate, 22, 227, 54, // Skip to: 19091 -/* 5040 */ MCD_OPC_Decode, 179, 20, 255, 1, // Opcode: VSEG -/* 5045 */ MCD_OPC_FilterValue, 96, 78, 0, // Skip to: 5127 -/* 5049 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5052 */ MCD_OPC_FilterValue, 0, 211, 54, // Skip to: 19091 -/* 5056 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5059 */ MCD_OPC_FilterValue, 0, 204, 54, // Skip to: 19091 -/* 5063 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5066 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5079 -/* 5070 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5118 -/* 5074 */ MCD_OPC_Decode, 229, 19, 130, 2, // Opcode: VMRLB -/* 5079 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5092 -/* 5083 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5118 -/* 5087 */ MCD_OPC_Decode, 232, 19, 130, 2, // Opcode: VMRLH -/* 5092 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5105 -/* 5096 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5118 -/* 5100 */ MCD_OPC_Decode, 230, 19, 130, 2, // Opcode: VMRLF -/* 5105 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5118 -/* 5109 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5118 -/* 5113 */ MCD_OPC_Decode, 231, 19, 130, 2, // Opcode: VMRLG -/* 5118 */ MCD_OPC_CheckPredicate, 22, 145, 54, // Skip to: 19091 -/* 5122 */ MCD_OPC_Decode, 228, 19, 131, 2, // Opcode: VMRL -/* 5127 */ MCD_OPC_FilterValue, 97, 78, 0, // Skip to: 5209 -/* 5131 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5134 */ MCD_OPC_FilterValue, 0, 129, 54, // Skip to: 19091 -/* 5138 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5141 */ MCD_OPC_FilterValue, 0, 122, 54, // Skip to: 19091 -/* 5145 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5148 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5161 -/* 5152 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5200 -/* 5156 */ MCD_OPC_Decode, 224, 19, 130, 2, // Opcode: VMRHB -/* 5161 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5174 -/* 5165 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5200 -/* 5169 */ MCD_OPC_Decode, 227, 19, 130, 2, // Opcode: VMRHH -/* 5174 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5187 -/* 5178 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5200 -/* 5182 */ MCD_OPC_Decode, 225, 19, 130, 2, // Opcode: VMRHF -/* 5187 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5200 -/* 5191 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5200 -/* 5195 */ MCD_OPC_Decode, 226, 19, 130, 2, // Opcode: VMRHG -/* 5200 */ MCD_OPC_CheckPredicate, 22, 63, 54, // Skip to: 19091 -/* 5204 */ MCD_OPC_Decode, 223, 19, 131, 2, // Opcode: VMRH -/* 5209 */ MCD_OPC_FilterValue, 98, 21, 0, // Skip to: 5234 -/* 5213 */ MCD_OPC_CheckPredicate, 22, 50, 54, // Skip to: 19091 -/* 5217 */ MCD_OPC_CheckField, 12, 16, 0, 44, 54, // Skip to: 19091 -/* 5223 */ MCD_OPC_CheckField, 8, 3, 0, 38, 54, // Skip to: 19091 -/* 5229 */ MCD_OPC_Decode, 155, 19, 132, 2, // Opcode: VLVGP -/* 5234 */ MCD_OPC_FilterValue, 100, 52, 0, // Skip to: 5290 -/* 5238 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5241 */ MCD_OPC_FilterValue, 0, 22, 54, // Skip to: 19091 -/* 5245 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5248 */ MCD_OPC_FilterValue, 0, 15, 54, // Skip to: 19091 -/* 5252 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5255 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5268 -/* 5259 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5281 -/* 5263 */ MCD_OPC_Decode, 220, 20, 130, 2, // Opcode: VSUMB -/* 5268 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5281 -/* 5272 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5281 -/* 5276 */ MCD_OPC_Decode, 224, 20, 130, 2, // Opcode: VSUMH -/* 5281 */ MCD_OPC_CheckPredicate, 22, 238, 53, // Skip to: 19091 -/* 5285 */ MCD_OPC_Decode, 219, 20, 131, 2, // Opcode: VSUM -/* 5290 */ MCD_OPC_FilterValue, 101, 52, 0, // Skip to: 5346 -/* 5294 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5297 */ MCD_OPC_FilterValue, 0, 222, 53, // Skip to: 19091 -/* 5301 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5304 */ MCD_OPC_FilterValue, 0, 215, 53, // Skip to: 19091 -/* 5308 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5311 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5324 -/* 5315 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5337 -/* 5319 */ MCD_OPC_Decode, 223, 20, 130, 2, // Opcode: VSUMGH -/* 5324 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5337 -/* 5328 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5337 -/* 5332 */ MCD_OPC_Decode, 222, 20, 130, 2, // Opcode: VSUMGF -/* 5337 */ MCD_OPC_CheckPredicate, 22, 182, 53, // Skip to: 19091 -/* 5341 */ MCD_OPC_Decode, 221, 20, 131, 2, // Opcode: VSUMG -/* 5346 */ MCD_OPC_FilterValue, 102, 21, 0, // Skip to: 5371 -/* 5350 */ MCD_OPC_CheckPredicate, 22, 169, 53, // Skip to: 19091 -/* 5354 */ MCD_OPC_CheckField, 12, 16, 0, 163, 53, // Skip to: 19091 -/* 5360 */ MCD_OPC_CheckField, 8, 1, 0, 157, 53, // Skip to: 19091 -/* 5366 */ MCD_OPC_Decode, 143, 17, 130, 2, // Opcode: VCKSM -/* 5371 */ MCD_OPC_FilterValue, 103, 52, 0, // Skip to: 5427 -/* 5375 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5378 */ MCD_OPC_FilterValue, 0, 141, 53, // Skip to: 19091 -/* 5382 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5385 */ MCD_OPC_FilterValue, 0, 134, 53, // Skip to: 19091 -/* 5389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5392 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5405 -/* 5396 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5418 -/* 5400 */ MCD_OPC_Decode, 226, 20, 130, 2, // Opcode: VSUMQF -/* 5405 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5418 -/* 5409 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5418 -/* 5413 */ MCD_OPC_Decode, 227, 20, 130, 2, // Opcode: VSUMQG -/* 5418 */ MCD_OPC_CheckPredicate, 22, 101, 53, // Skip to: 19091 -/* 5422 */ MCD_OPC_Decode, 225, 20, 131, 2, // Opcode: VSUMQ -/* 5427 */ MCD_OPC_FilterValue, 104, 21, 0, // Skip to: 5452 -/* 5431 */ MCD_OPC_CheckPredicate, 22, 88, 53, // Skip to: 19091 -/* 5435 */ MCD_OPC_CheckField, 12, 16, 0, 82, 53, // Skip to: 19091 -/* 5441 */ MCD_OPC_CheckField, 8, 1, 0, 76, 53, // Skip to: 19091 -/* 5447 */ MCD_OPC_Decode, 246, 19, 130, 2, // Opcode: VN -/* 5452 */ MCD_OPC_FilterValue, 105, 21, 0, // Skip to: 5477 -/* 5456 */ MCD_OPC_CheckPredicate, 22, 63, 53, // Skip to: 19091 -/* 5460 */ MCD_OPC_CheckField, 12, 16, 0, 57, 53, // Skip to: 19091 -/* 5466 */ MCD_OPC_CheckField, 8, 1, 0, 51, 53, // Skip to: 19091 -/* 5472 */ MCD_OPC_Decode, 247, 19, 130, 2, // Opcode: VNC -/* 5477 */ MCD_OPC_FilterValue, 106, 21, 0, // Skip to: 5502 -/* 5481 */ MCD_OPC_CheckPredicate, 22, 38, 53, // Skip to: 19091 -/* 5485 */ MCD_OPC_CheckField, 12, 16, 0, 32, 53, // Skip to: 19091 -/* 5491 */ MCD_OPC_CheckField, 8, 1, 0, 26, 53, // Skip to: 19091 -/* 5497 */ MCD_OPC_Decode, 251, 19, 130, 2, // Opcode: VO -/* 5502 */ MCD_OPC_FilterValue, 107, 21, 0, // Skip to: 5527 -/* 5506 */ MCD_OPC_CheckPredicate, 22, 13, 53, // Skip to: 19091 -/* 5510 */ MCD_OPC_CheckField, 12, 16, 0, 7, 53, // Skip to: 19091 -/* 5516 */ MCD_OPC_CheckField, 8, 1, 0, 1, 53, // Skip to: 19091 -/* 5522 */ MCD_OPC_Decode, 249, 19, 130, 2, // Opcode: VNO -/* 5527 */ MCD_OPC_FilterValue, 108, 21, 0, // Skip to: 5552 -/* 5531 */ MCD_OPC_CheckPredicate, 23, 244, 52, // Skip to: 19091 -/* 5535 */ MCD_OPC_CheckField, 12, 16, 0, 238, 52, // Skip to: 19091 -/* 5541 */ MCD_OPC_CheckField, 8, 1, 0, 232, 52, // Skip to: 19091 -/* 5547 */ MCD_OPC_Decode, 250, 19, 130, 2, // Opcode: VNX -/* 5552 */ MCD_OPC_FilterValue, 109, 21, 0, // Skip to: 5577 -/* 5556 */ MCD_OPC_CheckPredicate, 22, 219, 52, // Skip to: 19091 -/* 5560 */ MCD_OPC_CheckField, 12, 16, 0, 213, 52, // Skip to: 19091 -/* 5566 */ MCD_OPC_CheckField, 8, 1, 0, 207, 52, // Skip to: 19091 -/* 5572 */ MCD_OPC_Decode, 247, 20, 130, 2, // Opcode: VX -/* 5577 */ MCD_OPC_FilterValue, 110, 21, 0, // Skip to: 5602 -/* 5581 */ MCD_OPC_CheckPredicate, 23, 194, 52, // Skip to: 19091 -/* 5585 */ MCD_OPC_CheckField, 12, 16, 0, 188, 52, // Skip to: 19091 -/* 5591 */ MCD_OPC_CheckField, 8, 1, 0, 182, 52, // Skip to: 19091 -/* 5597 */ MCD_OPC_Decode, 248, 19, 130, 2, // Opcode: VNN -/* 5602 */ MCD_OPC_FilterValue, 111, 21, 0, // Skip to: 5627 -/* 5606 */ MCD_OPC_CheckPredicate, 23, 169, 52, // Skip to: 19091 -/* 5610 */ MCD_OPC_CheckField, 12, 16, 0, 163, 52, // Skip to: 19091 -/* 5616 */ MCD_OPC_CheckField, 8, 1, 0, 157, 52, // Skip to: 19091 -/* 5622 */ MCD_OPC_Decode, 252, 19, 130, 2, // Opcode: VOC -/* 5627 */ MCD_OPC_FilterValue, 112, 78, 0, // Skip to: 5709 -/* 5631 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5634 */ MCD_OPC_FilterValue, 0, 141, 52, // Skip to: 19091 -/* 5638 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5641 */ MCD_OPC_FilterValue, 0, 134, 52, // Skip to: 19091 -/* 5645 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5648 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5661 -/* 5652 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5700 -/* 5656 */ MCD_OPC_Decode, 193, 17, 130, 2, // Opcode: VESLVB -/* 5661 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5674 -/* 5665 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5700 -/* 5669 */ MCD_OPC_Decode, 196, 17, 130, 2, // Opcode: VESLVH -/* 5674 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5687 -/* 5678 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5700 -/* 5682 */ MCD_OPC_Decode, 194, 17, 130, 2, // Opcode: VESLVF -/* 5687 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5700 -/* 5691 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5700 -/* 5695 */ MCD_OPC_Decode, 195, 17, 130, 2, // Opcode: VESLVG -/* 5700 */ MCD_OPC_CheckPredicate, 22, 75, 52, // Skip to: 19091 -/* 5704 */ MCD_OPC_Decode, 192, 17, 131, 2, // Opcode: VESLV -/* 5709 */ MCD_OPC_FilterValue, 114, 78, 0, // Skip to: 5791 -/* 5713 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5716 */ MCD_OPC_FilterValue, 0, 59, 52, // Skip to: 19091 -/* 5720 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 5723 */ MCD_OPC_FilterValue, 0, 52, 52, // Skip to: 19091 -/* 5727 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5730 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5743 -/* 5734 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5782 -/* 5738 */ MCD_OPC_Decode, 173, 17, 133, 2, // Opcode: VERIMB -/* 5743 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5756 -/* 5747 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5782 -/* 5751 */ MCD_OPC_Decode, 176, 17, 133, 2, // Opcode: VERIMH -/* 5756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5769 -/* 5760 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5782 -/* 5764 */ MCD_OPC_Decode, 174, 17, 133, 2, // Opcode: VERIMF -/* 5769 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5782 -/* 5773 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5782 -/* 5777 */ MCD_OPC_Decode, 175, 17, 133, 2, // Opcode: VERIMG -/* 5782 */ MCD_OPC_CheckPredicate, 22, 249, 51, // Skip to: 19091 -/* 5786 */ MCD_OPC_Decode, 172, 17, 134, 2, // Opcode: VERIM -/* 5791 */ MCD_OPC_FilterValue, 115, 78, 0, // Skip to: 5873 -/* 5795 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5798 */ MCD_OPC_FilterValue, 0, 233, 51, // Skip to: 19091 -/* 5802 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5805 */ MCD_OPC_FilterValue, 0, 226, 51, // Skip to: 19091 -/* 5809 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5812 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5825 -/* 5816 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5864 -/* 5820 */ MCD_OPC_Decode, 183, 17, 130, 2, // Opcode: VERLLVB -/* 5825 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5838 -/* 5829 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5864 -/* 5833 */ MCD_OPC_Decode, 186, 17, 130, 2, // Opcode: VERLLVH -/* 5838 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5851 -/* 5842 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5864 -/* 5846 */ MCD_OPC_Decode, 184, 17, 130, 2, // Opcode: VERLLVF -/* 5851 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5864 -/* 5855 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5864 -/* 5859 */ MCD_OPC_Decode, 185, 17, 130, 2, // Opcode: VERLLVG -/* 5864 */ MCD_OPC_CheckPredicate, 22, 167, 51, // Skip to: 19091 -/* 5868 */ MCD_OPC_Decode, 182, 17, 131, 2, // Opcode: VERLLV -/* 5873 */ MCD_OPC_FilterValue, 116, 21, 0, // Skip to: 5898 -/* 5877 */ MCD_OPC_CheckPredicate, 22, 154, 51, // Skip to: 19091 -/* 5881 */ MCD_OPC_CheckField, 12, 16, 0, 148, 51, // Skip to: 19091 -/* 5887 */ MCD_OPC_CheckField, 8, 1, 0, 142, 51, // Skip to: 19091 -/* 5893 */ MCD_OPC_Decode, 187, 20, 130, 2, // Opcode: VSL -/* 5898 */ MCD_OPC_FilterValue, 117, 21, 0, // Skip to: 5923 -/* 5902 */ MCD_OPC_CheckPredicate, 22, 129, 51, // Skip to: 19091 -/* 5906 */ MCD_OPC_CheckField, 12, 16, 0, 123, 51, // Skip to: 19091 -/* 5912 */ MCD_OPC_CheckField, 8, 1, 0, 117, 51, // Skip to: 19091 -/* 5918 */ MCD_OPC_Decode, 188, 20, 130, 2, // Opcode: VSLB -/* 5923 */ MCD_OPC_FilterValue, 119, 27, 0, // Skip to: 5954 -/* 5927 */ MCD_OPC_CheckPredicate, 22, 104, 51, // Skip to: 19091 -/* 5931 */ MCD_OPC_CheckField, 24, 4, 0, 98, 51, // Skip to: 19091 -/* 5937 */ MCD_OPC_CheckField, 12, 4, 0, 92, 51, // Skip to: 19091 -/* 5943 */ MCD_OPC_CheckField, 8, 1, 0, 86, 51, // Skip to: 19091 -/* 5949 */ MCD_OPC_Decode, 189, 20, 135, 2, // Opcode: VSLDB -/* 5954 */ MCD_OPC_FilterValue, 120, 78, 0, // Skip to: 6036 -/* 5958 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 5961 */ MCD_OPC_FilterValue, 0, 70, 51, // Skip to: 19091 -/* 5965 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 5968 */ MCD_OPC_FilterValue, 0, 63, 51, // Skip to: 19091 -/* 5972 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 5975 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5988 -/* 5979 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 6027 -/* 5983 */ MCD_OPC_Decode, 213, 17, 130, 2, // Opcode: VESRLVB -/* 5988 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6001 -/* 5992 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6027 -/* 5996 */ MCD_OPC_Decode, 216, 17, 130, 2, // Opcode: VESRLVH -/* 6001 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6014 -/* 6005 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6027 -/* 6009 */ MCD_OPC_Decode, 214, 17, 130, 2, // Opcode: VESRLVF -/* 6014 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6027 -/* 6018 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6027 -/* 6022 */ MCD_OPC_Decode, 215, 17, 130, 2, // Opcode: VESRLVG -/* 6027 */ MCD_OPC_CheckPredicate, 22, 4, 51, // Skip to: 19091 -/* 6031 */ MCD_OPC_Decode, 212, 17, 131, 2, // Opcode: VESRLV -/* 6036 */ MCD_OPC_FilterValue, 122, 78, 0, // Skip to: 6118 -/* 6040 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6043 */ MCD_OPC_FilterValue, 0, 244, 50, // Skip to: 19091 -/* 6047 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 6050 */ MCD_OPC_FilterValue, 0, 237, 50, // Skip to: 19091 -/* 6054 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6057 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6070 -/* 6061 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 6109 -/* 6065 */ MCD_OPC_Decode, 203, 17, 130, 2, // Opcode: VESRAVB -/* 6070 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6083 -/* 6074 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6109 -/* 6078 */ MCD_OPC_Decode, 206, 17, 130, 2, // Opcode: VESRAVH -/* 6083 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6096 -/* 6087 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6109 -/* 6091 */ MCD_OPC_Decode, 204, 17, 130, 2, // Opcode: VESRAVF -/* 6096 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6109 -/* 6100 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6109 -/* 6104 */ MCD_OPC_Decode, 205, 17, 130, 2, // Opcode: VESRAVG -/* 6109 */ MCD_OPC_CheckPredicate, 22, 178, 50, // Skip to: 19091 -/* 6113 */ MCD_OPC_Decode, 202, 17, 131, 2, // Opcode: VESRAV -/* 6118 */ MCD_OPC_FilterValue, 124, 21, 0, // Skip to: 6143 -/* 6122 */ MCD_OPC_CheckPredicate, 22, 165, 50, // Skip to: 19091 -/* 6126 */ MCD_OPC_CheckField, 12, 16, 0, 159, 50, // Skip to: 19091 -/* 6132 */ MCD_OPC_CheckField, 8, 1, 0, 153, 50, // Skip to: 19091 -/* 6138 */ MCD_OPC_Decode, 194, 20, 130, 2, // Opcode: VSRL -/* 6143 */ MCD_OPC_FilterValue, 125, 21, 0, // Skip to: 6168 -/* 6147 */ MCD_OPC_CheckPredicate, 22, 140, 50, // Skip to: 19091 -/* 6151 */ MCD_OPC_CheckField, 12, 16, 0, 134, 50, // Skip to: 19091 -/* 6157 */ MCD_OPC_CheckField, 8, 1, 0, 128, 50, // Skip to: 19091 -/* 6163 */ MCD_OPC_Decode, 195, 20, 130, 2, // Opcode: VSRLB -/* 6168 */ MCD_OPC_FilterValue, 126, 21, 0, // Skip to: 6193 -/* 6172 */ MCD_OPC_CheckPredicate, 22, 115, 50, // Skip to: 19091 -/* 6176 */ MCD_OPC_CheckField, 12, 16, 0, 109, 50, // Skip to: 19091 -/* 6182 */ MCD_OPC_CheckField, 8, 1, 0, 103, 50, // Skip to: 19091 -/* 6188 */ MCD_OPC_Decode, 192, 20, 130, 2, // Opcode: VSRA -/* 6193 */ MCD_OPC_FilterValue, 127, 21, 0, // Skip to: 6218 -/* 6197 */ MCD_OPC_CheckPredicate, 22, 90, 50, // Skip to: 19091 -/* 6201 */ MCD_OPC_CheckField, 12, 16, 0, 84, 50, // Skip to: 19091 -/* 6207 */ MCD_OPC_CheckField, 8, 1, 0, 78, 50, // Skip to: 19091 -/* 6213 */ MCD_OPC_Decode, 193, 20, 130, 2, // Opcode: VSRAB -/* 6218 */ MCD_OPC_FilterValue, 128, 1, 198, 0, // Skip to: 6421 -/* 6223 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6226 */ MCD_OPC_FilterValue, 0, 61, 50, // Skip to: 19091 -/* 6230 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6233 */ MCD_OPC_FilterValue, 0, 54, 50, // Skip to: 19091 -/* 6237 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 6240 */ MCD_OPC_FilterValue, 0, 47, 50, // Skip to: 19091 -/* 6244 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6247 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6302 -/* 6251 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6254 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6267 -/* 6258 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6293 -/* 6262 */ MCD_OPC_Decode, 253, 17, 130, 2, // Opcode: VFEEBS -/* 6267 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6280 -/* 6271 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6293 -/* 6275 */ MCD_OPC_Decode, 130, 18, 130, 2, // Opcode: VFEEZB -/* 6280 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6293 -/* 6284 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6293 -/* 6288 */ MCD_OPC_Decode, 131, 18, 130, 2, // Opcode: VFEEZBS -/* 6293 */ MCD_OPC_CheckPredicate, 22, 115, 0, // Skip to: 6412 -/* 6297 */ MCD_OPC_Decode, 252, 17, 136, 2, // Opcode: VFEEB -/* 6302 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6357 -/* 6306 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6309 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6322 -/* 6313 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6348 -/* 6317 */ MCD_OPC_Decode, 129, 18, 130, 2, // Opcode: VFEEHS -/* 6322 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6335 -/* 6326 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6348 -/* 6330 */ MCD_OPC_Decode, 134, 18, 130, 2, // Opcode: VFEEZH -/* 6335 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6348 -/* 6339 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6348 -/* 6343 */ MCD_OPC_Decode, 135, 18, 130, 2, // Opcode: VFEEZHS -/* 6348 */ MCD_OPC_CheckPredicate, 22, 60, 0, // Skip to: 6412 -/* 6352 */ MCD_OPC_Decode, 128, 18, 136, 2, // Opcode: VFEEH -/* 6357 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6412 -/* 6361 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6364 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6377 -/* 6368 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6403 -/* 6372 */ MCD_OPC_Decode, 255, 17, 130, 2, // Opcode: VFEEFS -/* 6377 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6390 -/* 6381 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6403 -/* 6385 */ MCD_OPC_Decode, 132, 18, 130, 2, // Opcode: VFEEZF -/* 6390 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6403 -/* 6394 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6403 -/* 6398 */ MCD_OPC_Decode, 133, 18, 130, 2, // Opcode: VFEEZFS -/* 6403 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6412 -/* 6407 */ MCD_OPC_Decode, 254, 17, 136, 2, // Opcode: VFEEF -/* 6412 */ MCD_OPC_CheckPredicate, 22, 131, 49, // Skip to: 19091 -/* 6416 */ MCD_OPC_Decode, 251, 17, 137, 2, // Opcode: VFEE -/* 6421 */ MCD_OPC_FilterValue, 129, 1, 198, 0, // Skip to: 6624 -/* 6426 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6429 */ MCD_OPC_FilterValue, 0, 114, 49, // Skip to: 19091 -/* 6433 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6436 */ MCD_OPC_FilterValue, 0, 107, 49, // Skip to: 19091 -/* 6440 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 6443 */ MCD_OPC_FilterValue, 0, 100, 49, // Skip to: 19091 -/* 6447 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6450 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6505 -/* 6454 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6457 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6470 -/* 6461 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6496 -/* 6465 */ MCD_OPC_Decode, 138, 18, 130, 2, // Opcode: VFENEBS -/* 6470 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6483 -/* 6474 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6496 -/* 6478 */ MCD_OPC_Decode, 143, 18, 130, 2, // Opcode: VFENEZB -/* 6483 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6496 -/* 6487 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6496 -/* 6491 */ MCD_OPC_Decode, 144, 18, 130, 2, // Opcode: VFENEZBS -/* 6496 */ MCD_OPC_CheckPredicate, 22, 115, 0, // Skip to: 6615 -/* 6500 */ MCD_OPC_Decode, 137, 18, 136, 2, // Opcode: VFENEB -/* 6505 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6560 -/* 6509 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6512 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6525 -/* 6516 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6551 -/* 6520 */ MCD_OPC_Decode, 142, 18, 130, 2, // Opcode: VFENEHS -/* 6525 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6538 -/* 6529 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6551 -/* 6533 */ MCD_OPC_Decode, 147, 18, 130, 2, // Opcode: VFENEZH -/* 6538 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6551 -/* 6542 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6551 -/* 6546 */ MCD_OPC_Decode, 148, 18, 130, 2, // Opcode: VFENEZHS -/* 6551 */ MCD_OPC_CheckPredicate, 22, 60, 0, // Skip to: 6615 -/* 6555 */ MCD_OPC_Decode, 141, 18, 136, 2, // Opcode: VFENEH -/* 6560 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6615 -/* 6564 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 6567 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6580 -/* 6571 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6606 -/* 6575 */ MCD_OPC_Decode, 140, 18, 130, 2, // Opcode: VFENEFS -/* 6580 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6593 -/* 6584 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6606 -/* 6588 */ MCD_OPC_Decode, 145, 18, 130, 2, // Opcode: VFENEZF -/* 6593 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6606 -/* 6597 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6606 -/* 6601 */ MCD_OPC_Decode, 146, 18, 130, 2, // Opcode: VFENEZFS -/* 6606 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6615 -/* 6610 */ MCD_OPC_Decode, 139, 18, 136, 2, // Opcode: VFENEF -/* 6615 */ MCD_OPC_CheckPredicate, 22, 184, 48, // Skip to: 19091 -/* 6619 */ MCD_OPC_Decode, 136, 18, 137, 2, // Opcode: VFENE -/* 6624 */ MCD_OPC_FilterValue, 130, 1, 207, 0, // Skip to: 6836 -/* 6629 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 6632 */ MCD_OPC_FilterValue, 0, 167, 48, // Skip to: 19091 -/* 6636 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6639 */ MCD_OPC_FilterValue, 0, 160, 48, // Skip to: 19091 -/* 6643 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 6646 */ MCD_OPC_FilterValue, 0, 153, 48, // Skip to: 19091 -/* 6650 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 6653 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 6711 -/* 6657 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6672 -/* 6661 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6672 -/* 6667 */ MCD_OPC_Decode, 227, 17, 138, 2, // Opcode: VFAEZBS -/* 6672 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6687 -/* 6676 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6687 -/* 6682 */ MCD_OPC_Decode, 221, 17, 139, 2, // Opcode: VFAEBS -/* 6687 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6702 -/* 6691 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6702 -/* 6697 */ MCD_OPC_Decode, 226, 17, 140, 2, // Opcode: VFAEZB -/* 6702 */ MCD_OPC_CheckPredicate, 22, 121, 0, // Skip to: 6827 -/* 6706 */ MCD_OPC_Decode, 220, 17, 136, 2, // Opcode: VFAEB -/* 6711 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 6769 -/* 6715 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6730 -/* 6719 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6730 -/* 6725 */ MCD_OPC_Decode, 231, 17, 138, 2, // Opcode: VFAEZHS -/* 6730 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6745 -/* 6734 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6745 -/* 6740 */ MCD_OPC_Decode, 225, 17, 139, 2, // Opcode: VFAEHS -/* 6745 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6760 -/* 6749 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6760 -/* 6755 */ MCD_OPC_Decode, 230, 17, 140, 2, // Opcode: VFAEZH -/* 6760 */ MCD_OPC_CheckPredicate, 22, 63, 0, // Skip to: 6827 -/* 6764 */ MCD_OPC_Decode, 224, 17, 136, 2, // Opcode: VFAEH -/* 6769 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 6827 -/* 6773 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6788 -/* 6777 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6788 -/* 6783 */ MCD_OPC_Decode, 229, 17, 138, 2, // Opcode: VFAEZFS -/* 6788 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6803 -/* 6792 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6803 -/* 6798 */ MCD_OPC_Decode, 223, 17, 139, 2, // Opcode: VFAEFS -/* 6803 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6818 -/* 6807 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6818 -/* 6813 */ MCD_OPC_Decode, 228, 17, 140, 2, // Opcode: VFAEZF -/* 6818 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6827 -/* 6822 */ MCD_OPC_Decode, 222, 17, 136, 2, // Opcode: VFAEF -/* 6827 */ MCD_OPC_CheckPredicate, 22, 228, 47, // Skip to: 19091 -/* 6831 */ MCD_OPC_Decode, 219, 17, 137, 2, // Opcode: VFAE -/* 6836 */ MCD_OPC_FilterValue, 132, 1, 21, 0, // Skip to: 6862 -/* 6841 */ MCD_OPC_CheckPredicate, 22, 214, 47, // Skip to: 19091 -/* 6845 */ MCD_OPC_CheckField, 16, 12, 0, 208, 47, // Skip to: 19091 -/* 6851 */ MCD_OPC_CheckField, 8, 1, 0, 202, 47, // Skip to: 19091 -/* 6857 */ MCD_OPC_Decode, 254, 19, 131, 2, // Opcode: VPDI -/* 6862 */ MCD_OPC_FilterValue, 133, 1, 21, 0, // Skip to: 6888 -/* 6867 */ MCD_OPC_CheckPredicate, 23, 188, 47, // Skip to: 19091 -/* 6871 */ MCD_OPC_CheckField, 12, 16, 0, 182, 47, // Skip to: 19091 -/* 6877 */ MCD_OPC_CheckField, 8, 1, 0, 176, 47, // Skip to: 19091 -/* 6883 */ MCD_OPC_Decode, 237, 16, 130, 2, // Opcode: VBPERM -/* 6888 */ MCD_OPC_FilterValue, 138, 1, 193, 0, // Skip to: 7086 -/* 6893 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 6896 */ MCD_OPC_FilterValue, 0, 159, 47, // Skip to: 19091 -/* 6900 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 6903 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 6961 -/* 6907 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6922 -/* 6911 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6922 -/* 6917 */ MCD_OPC_Decode, 212, 20, 141, 2, // Opcode: VSTRCZBS -/* 6922 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6937 -/* 6926 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6937 -/* 6932 */ MCD_OPC_Decode, 206, 20, 142, 2, // Opcode: VSTRCBS -/* 6937 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6952 -/* 6941 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6952 -/* 6947 */ MCD_OPC_Decode, 211, 20, 143, 2, // Opcode: VSTRCZB -/* 6952 */ MCD_OPC_CheckPredicate, 22, 121, 0, // Skip to: 7077 -/* 6956 */ MCD_OPC_Decode, 205, 20, 144, 2, // Opcode: VSTRCB -/* 6961 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 7019 -/* 6965 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6980 -/* 6969 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6980 -/* 6975 */ MCD_OPC_Decode, 216, 20, 141, 2, // Opcode: VSTRCZHS -/* 6980 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6995 -/* 6984 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6995 -/* 6990 */ MCD_OPC_Decode, 210, 20, 142, 2, // Opcode: VSTRCHS -/* 6995 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7010 -/* 6999 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 7010 -/* 7005 */ MCD_OPC_Decode, 215, 20, 143, 2, // Opcode: VSTRCZH -/* 7010 */ MCD_OPC_CheckPredicate, 22, 63, 0, // Skip to: 7077 -/* 7014 */ MCD_OPC_Decode, 209, 20, 144, 2, // Opcode: VSTRCH -/* 7019 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 7077 -/* 7023 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7038 -/* 7027 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 7038 -/* 7033 */ MCD_OPC_Decode, 214, 20, 141, 2, // Opcode: VSTRCZFS -/* 7038 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7053 -/* 7042 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 7053 -/* 7048 */ MCD_OPC_Decode, 208, 20, 142, 2, // Opcode: VSTRCFS -/* 7053 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7068 -/* 7057 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 7068 -/* 7063 */ MCD_OPC_Decode, 213, 20, 143, 2, // Opcode: VSTRCZF -/* 7068 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7077 -/* 7072 */ MCD_OPC_Decode, 207, 20, 144, 2, // Opcode: VSTRCF -/* 7077 */ MCD_OPC_CheckPredicate, 22, 234, 46, // Skip to: 19091 -/* 7081 */ MCD_OPC_Decode, 204, 20, 145, 2, // Opcode: VSTRC -/* 7086 */ MCD_OPC_FilterValue, 140, 1, 15, 0, // Skip to: 7106 -/* 7091 */ MCD_OPC_CheckPredicate, 22, 220, 46, // Skip to: 19091 -/* 7095 */ MCD_OPC_CheckField, 16, 12, 0, 214, 46, // Skip to: 19091 -/* 7101 */ MCD_OPC_Decode, 255, 19, 146, 2, // Opcode: VPERM -/* 7106 */ MCD_OPC_FilterValue, 141, 1, 15, 0, // Skip to: 7126 -/* 7111 */ MCD_OPC_CheckPredicate, 22, 200, 46, // Skip to: 19091 -/* 7115 */ MCD_OPC_CheckField, 16, 12, 0, 194, 46, // Skip to: 19091 -/* 7121 */ MCD_OPC_Decode, 183, 20, 146, 2, // Opcode: VSEL -/* 7126 */ MCD_OPC_FilterValue, 142, 1, 104, 0, // Skip to: 7235 -/* 7131 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7134 */ MCD_OPC_FilterValue, 0, 177, 46, // Skip to: 19091 -/* 7138 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7141 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7174 -/* 7145 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7148 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7161 -/* 7152 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7226 -/* 7156 */ MCD_OPC_Decode, 188, 18, 146, 2, // Opcode: VFMSSB -/* 7161 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7226 -/* 7165 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7226 -/* 7169 */ MCD_OPC_Decode, 203, 21, 147, 2, // Opcode: WFMSSB -/* 7174 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7207 -/* 7178 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7181 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7194 -/* 7185 */ MCD_OPC_CheckPredicate, 22, 37, 0, // Skip to: 7226 -/* 7189 */ MCD_OPC_Decode, 187, 18, 146, 2, // Opcode: VFMSDB -/* 7194 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7226 -/* 7198 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 7226 -/* 7202 */ MCD_OPC_Decode, 202, 21, 148, 2, // Opcode: WFMSDB -/* 7207 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7226 -/* 7211 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7226 -/* 7215 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7226 -/* 7221 */ MCD_OPC_Decode, 204, 21, 146, 2, // Opcode: WFMSXB -/* 7226 */ MCD_OPC_CheckPredicate, 22, 85, 46, // Skip to: 19091 -/* 7230 */ MCD_OPC_Decode, 185, 18, 149, 2, // Opcode: VFMS -/* 7235 */ MCD_OPC_FilterValue, 143, 1, 104, 0, // Skip to: 7344 -/* 7240 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7243 */ MCD_OPC_FilterValue, 0, 68, 46, // Skip to: 19091 -/* 7247 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7250 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7283 -/* 7254 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7257 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7270 -/* 7261 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7335 -/* 7265 */ MCD_OPC_Decode, 177, 18, 146, 2, // Opcode: VFMASB -/* 7270 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7335 -/* 7274 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7335 -/* 7278 */ MCD_OPC_Decode, 192, 21, 147, 2, // Opcode: WFMASB -/* 7283 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7316 -/* 7287 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7290 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7303 -/* 7294 */ MCD_OPC_CheckPredicate, 22, 37, 0, // Skip to: 7335 -/* 7298 */ MCD_OPC_Decode, 176, 18, 146, 2, // Opcode: VFMADB -/* 7303 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7335 -/* 7307 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 7335 -/* 7311 */ MCD_OPC_Decode, 191, 21, 148, 2, // Opcode: WFMADB -/* 7316 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7335 -/* 7320 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7335 -/* 7324 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7335 -/* 7330 */ MCD_OPC_Decode, 193, 21, 146, 2, // Opcode: WFMAXB -/* 7335 */ MCD_OPC_CheckPredicate, 22, 232, 45, // Skip to: 19091 -/* 7339 */ MCD_OPC_Decode, 175, 18, 149, 2, // Opcode: VFMA -/* 7344 */ MCD_OPC_FilterValue, 148, 1, 65, 0, // Skip to: 7414 -/* 7349 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7352 */ MCD_OPC_FilterValue, 0, 215, 45, // Skip to: 19091 -/* 7356 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 7359 */ MCD_OPC_FilterValue, 0, 208, 45, // Skip to: 19091 -/* 7363 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7366 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7379 -/* 7370 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 7405 -/* 7374 */ MCD_OPC_Decode, 131, 20, 130, 2, // Opcode: VPKH -/* 7379 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7392 -/* 7383 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7405 -/* 7387 */ MCD_OPC_Decode, 129, 20, 130, 2, // Opcode: VPKF -/* 7392 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7405 -/* 7396 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7405 -/* 7400 */ MCD_OPC_Decode, 130, 20, 130, 2, // Opcode: VPKG -/* 7405 */ MCD_OPC_CheckPredicate, 22, 162, 45, // Skip to: 19091 -/* 7409 */ MCD_OPC_Decode, 128, 20, 131, 2, // Opcode: VPK -/* 7414 */ MCD_OPC_FilterValue, 149, 1, 132, 0, // Skip to: 7551 -/* 7419 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7422 */ MCD_OPC_FilterValue, 0, 145, 45, // Skip to: 19091 -/* 7426 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7429 */ MCD_OPC_FilterValue, 0, 138, 45, // Skip to: 19091 -/* 7433 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7436 */ MCD_OPC_FilterValue, 0, 131, 45, // Skip to: 19091 -/* 7440 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7443 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 7476 -/* 7447 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7450 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7463 -/* 7454 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 7542 -/* 7458 */ MCD_OPC_Decode, 137, 20, 130, 2, // Opcode: VPKLSH -/* 7463 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 7542 -/* 7467 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 7542 -/* 7471 */ MCD_OPC_Decode, 138, 20, 130, 2, // Opcode: VPKLSHS -/* 7476 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7509 -/* 7480 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7483 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7496 -/* 7487 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 7542 -/* 7491 */ MCD_OPC_Decode, 133, 20, 130, 2, // Opcode: VPKLSF -/* 7496 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 7542 -/* 7500 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 7542 -/* 7504 */ MCD_OPC_Decode, 134, 20, 130, 2, // Opcode: VPKLSFS -/* 7509 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7542 -/* 7513 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7516 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7529 -/* 7520 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7542 -/* 7524 */ MCD_OPC_Decode, 135, 20, 130, 2, // Opcode: VPKLSG -/* 7529 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7542 -/* 7533 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7542 -/* 7537 */ MCD_OPC_Decode, 136, 20, 130, 2, // Opcode: VPKLSGS -/* 7542 */ MCD_OPC_CheckPredicate, 22, 25, 45, // Skip to: 19091 -/* 7546 */ MCD_OPC_Decode, 132, 20, 137, 2, // Opcode: VPKLS -/* 7551 */ MCD_OPC_FilterValue, 151, 1, 132, 0, // Skip to: 7688 -/* 7556 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7559 */ MCD_OPC_FilterValue, 0, 8, 45, // Skip to: 19091 -/* 7563 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7566 */ MCD_OPC_FilterValue, 0, 1, 45, // Skip to: 19091 -/* 7570 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7573 */ MCD_OPC_FilterValue, 0, 250, 44, // Skip to: 19091 -/* 7577 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7580 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 7613 -/* 7584 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7587 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7600 -/* 7591 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 7679 -/* 7595 */ MCD_OPC_Decode, 144, 20, 130, 2, // Opcode: VPKSH -/* 7600 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 7679 -/* 7604 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 7679 -/* 7608 */ MCD_OPC_Decode, 145, 20, 130, 2, // Opcode: VPKSHS -/* 7613 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7646 -/* 7617 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7620 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7633 -/* 7624 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 7679 -/* 7628 */ MCD_OPC_Decode, 140, 20, 130, 2, // Opcode: VPKSF -/* 7633 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 7679 -/* 7637 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 7679 -/* 7641 */ MCD_OPC_Decode, 141, 20, 130, 2, // Opcode: VPKSFS -/* 7646 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7679 -/* 7650 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7653 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7666 -/* 7657 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7679 -/* 7661 */ MCD_OPC_Decode, 142, 20, 130, 2, // Opcode: VPKSG -/* 7666 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7679 -/* 7670 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7679 -/* 7674 */ MCD_OPC_Decode, 143, 20, 130, 2, // Opcode: VPKSGS -/* 7679 */ MCD_OPC_CheckPredicate, 22, 144, 44, // Skip to: 19091 -/* 7683 */ MCD_OPC_Decode, 139, 20, 137, 2, // Opcode: VPKS -/* 7688 */ MCD_OPC_FilterValue, 158, 1, 104, 0, // Skip to: 7797 -/* 7693 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7696 */ MCD_OPC_FilterValue, 0, 127, 44, // Skip to: 19091 -/* 7700 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7703 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7736 -/* 7707 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7710 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7723 -/* 7714 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7788 -/* 7718 */ MCD_OPC_Decode, 194, 18, 146, 2, // Opcode: VFNMSSB -/* 7723 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7788 -/* 7727 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7788 -/* 7731 */ MCD_OPC_Decode, 210, 21, 147, 2, // Opcode: WFNMSSB -/* 7736 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7769 -/* 7740 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7743 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7756 -/* 7747 */ MCD_OPC_CheckPredicate, 23, 37, 0, // Skip to: 7788 -/* 7751 */ MCD_OPC_Decode, 193, 18, 146, 2, // Opcode: VFNMSDB -/* 7756 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7788 -/* 7760 */ MCD_OPC_CheckPredicate, 23, 24, 0, // Skip to: 7788 -/* 7764 */ MCD_OPC_Decode, 209, 21, 148, 2, // Opcode: WFNMSDB -/* 7769 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7788 -/* 7773 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7788 -/* 7777 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7788 -/* 7783 */ MCD_OPC_Decode, 211, 21, 146, 2, // Opcode: WFNMSXB -/* 7788 */ MCD_OPC_CheckPredicate, 23, 35, 44, // Skip to: 19091 -/* 7792 */ MCD_OPC_Decode, 192, 18, 149, 2, // Opcode: VFNMS -/* 7797 */ MCD_OPC_FilterValue, 159, 1, 104, 0, // Skip to: 7906 -/* 7802 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 7805 */ MCD_OPC_FilterValue, 0, 18, 44, // Skip to: 19091 -/* 7809 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 7812 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7845 -/* 7816 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7819 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7832 -/* 7823 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7897 -/* 7827 */ MCD_OPC_Decode, 191, 18, 146, 2, // Opcode: VFNMASB -/* 7832 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7897 -/* 7836 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7897 -/* 7840 */ MCD_OPC_Decode, 207, 21, 147, 2, // Opcode: WFNMASB -/* 7845 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7878 -/* 7849 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 7852 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7865 -/* 7856 */ MCD_OPC_CheckPredicate, 23, 37, 0, // Skip to: 7897 -/* 7860 */ MCD_OPC_Decode, 190, 18, 146, 2, // Opcode: VFNMADB -/* 7865 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7897 -/* 7869 */ MCD_OPC_CheckPredicate, 23, 24, 0, // Skip to: 7897 -/* 7873 */ MCD_OPC_Decode, 206, 21, 148, 2, // Opcode: WFNMADB -/* 7878 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7897 -/* 7882 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7897 -/* 7886 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7897 -/* 7892 */ MCD_OPC_Decode, 208, 21, 146, 2, // Opcode: WFNMAXB -/* 7897 */ MCD_OPC_CheckPredicate, 23, 182, 43, // Skip to: 19091 -/* 7901 */ MCD_OPC_Decode, 189, 18, 149, 2, // Opcode: VFNMA -/* 7906 */ MCD_OPC_FilterValue, 161, 1, 65, 0, // Skip to: 7976 -/* 7911 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7914 */ MCD_OPC_FilterValue, 0, 165, 43, // Skip to: 19091 -/* 7918 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 7921 */ MCD_OPC_FilterValue, 0, 158, 43, // Skip to: 19091 -/* 7925 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7928 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7941 -/* 7932 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 7967 -/* 7936 */ MCD_OPC_Decode, 200, 19, 130, 2, // Opcode: VMLHB -/* 7941 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7954 -/* 7945 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7967 -/* 7949 */ MCD_OPC_Decode, 202, 19, 130, 2, // Opcode: VMLHH -/* 7954 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7967 -/* 7958 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7967 -/* 7962 */ MCD_OPC_Decode, 201, 19, 130, 2, // Opcode: VMLHF -/* 7967 */ MCD_OPC_CheckPredicate, 22, 112, 43, // Skip to: 19091 -/* 7971 */ MCD_OPC_Decode, 199, 19, 131, 2, // Opcode: VMLH -/* 7976 */ MCD_OPC_FilterValue, 162, 1, 65, 0, // Skip to: 8046 -/* 7981 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 7984 */ MCD_OPC_FilterValue, 0, 95, 43, // Skip to: 19091 -/* 7988 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 7991 */ MCD_OPC_FilterValue, 0, 88, 43, // Skip to: 19091 -/* 7995 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 7998 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8011 -/* 8002 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8037 -/* 8006 */ MCD_OPC_Decode, 193, 19, 130, 2, // Opcode: VMLB -/* 8011 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8024 -/* 8015 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8037 -/* 8019 */ MCD_OPC_Decode, 203, 19, 130, 2, // Opcode: VMLHW -/* 8024 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8037 -/* 8028 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8037 -/* 8032 */ MCD_OPC_Decode, 198, 19, 130, 2, // Opcode: VMLF -/* 8037 */ MCD_OPC_CheckPredicate, 22, 42, 43, // Skip to: 19091 -/* 8041 */ MCD_OPC_Decode, 192, 19, 131, 2, // Opcode: VML -/* 8046 */ MCD_OPC_FilterValue, 163, 1, 65, 0, // Skip to: 8116 -/* 8051 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8054 */ MCD_OPC_FilterValue, 0, 25, 43, // Skip to: 19091 -/* 8058 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8061 */ MCD_OPC_FilterValue, 0, 18, 43, // Skip to: 19091 -/* 8065 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8068 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8081 -/* 8072 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8107 -/* 8076 */ MCD_OPC_Decode, 189, 19, 130, 2, // Opcode: VMHB -/* 8081 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8094 -/* 8085 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8107 -/* 8089 */ MCD_OPC_Decode, 191, 19, 130, 2, // Opcode: VMHH -/* 8094 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8107 -/* 8098 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8107 -/* 8102 */ MCD_OPC_Decode, 190, 19, 130, 2, // Opcode: VMHF -/* 8107 */ MCD_OPC_CheckPredicate, 22, 228, 42, // Skip to: 19091 -/* 8111 */ MCD_OPC_Decode, 188, 19, 131, 2, // Opcode: VMH -/* 8116 */ MCD_OPC_FilterValue, 164, 1, 65, 0, // Skip to: 8186 -/* 8121 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8124 */ MCD_OPC_FilterValue, 0, 211, 42, // Skip to: 19091 -/* 8128 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8131 */ MCD_OPC_FilterValue, 0, 204, 42, // Skip to: 19091 -/* 8135 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8138 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8151 -/* 8142 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8177 -/* 8146 */ MCD_OPC_Decode, 195, 19, 130, 2, // Opcode: VMLEB -/* 8151 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8164 -/* 8155 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8177 -/* 8159 */ MCD_OPC_Decode, 197, 19, 130, 2, // Opcode: VMLEH -/* 8164 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8177 -/* 8168 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8177 -/* 8172 */ MCD_OPC_Decode, 196, 19, 130, 2, // Opcode: VMLEF -/* 8177 */ MCD_OPC_CheckPredicate, 22, 158, 42, // Skip to: 19091 -/* 8181 */ MCD_OPC_Decode, 194, 19, 131, 2, // Opcode: VMLE -/* 8186 */ MCD_OPC_FilterValue, 165, 1, 65, 0, // Skip to: 8256 -/* 8191 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8194 */ MCD_OPC_FilterValue, 0, 141, 42, // Skip to: 19091 -/* 8198 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8201 */ MCD_OPC_FilterValue, 0, 134, 42, // Skip to: 19091 -/* 8205 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8208 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8221 -/* 8212 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8247 -/* 8216 */ MCD_OPC_Decode, 205, 19, 130, 2, // Opcode: VMLOB -/* 8221 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8234 -/* 8225 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8247 -/* 8229 */ MCD_OPC_Decode, 207, 19, 130, 2, // Opcode: VMLOH -/* 8234 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8247 -/* 8238 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8247 -/* 8242 */ MCD_OPC_Decode, 206, 19, 130, 2, // Opcode: VMLOF -/* 8247 */ MCD_OPC_CheckPredicate, 22, 88, 42, // Skip to: 19091 -/* 8251 */ MCD_OPC_Decode, 204, 19, 131, 2, // Opcode: VMLO -/* 8256 */ MCD_OPC_FilterValue, 166, 1, 65, 0, // Skip to: 8326 -/* 8261 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8264 */ MCD_OPC_FilterValue, 0, 71, 42, // Skip to: 19091 -/* 8268 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8271 */ MCD_OPC_FilterValue, 0, 64, 42, // Skip to: 19091 -/* 8275 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8278 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8291 -/* 8282 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8317 -/* 8286 */ MCD_OPC_Decode, 185, 19, 130, 2, // Opcode: VMEB -/* 8291 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8304 -/* 8295 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8317 -/* 8299 */ MCD_OPC_Decode, 187, 19, 130, 2, // Opcode: VMEH -/* 8304 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8317 -/* 8308 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8317 -/* 8312 */ MCD_OPC_Decode, 186, 19, 130, 2, // Opcode: VMEF -/* 8317 */ MCD_OPC_CheckPredicate, 22, 18, 42, // Skip to: 19091 -/* 8321 */ MCD_OPC_Decode, 184, 19, 131, 2, // Opcode: VME -/* 8326 */ MCD_OPC_FilterValue, 167, 1, 65, 0, // Skip to: 8396 -/* 8331 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8334 */ MCD_OPC_FilterValue, 0, 1, 42, // Skip to: 19091 -/* 8338 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8341 */ MCD_OPC_FilterValue, 0, 250, 41, // Skip to: 19091 -/* 8345 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8348 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8361 -/* 8352 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8387 -/* 8356 */ MCD_OPC_Decode, 219, 19, 130, 2, // Opcode: VMOB -/* 8361 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8374 -/* 8365 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8387 -/* 8369 */ MCD_OPC_Decode, 221, 19, 130, 2, // Opcode: VMOH -/* 8374 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8387 -/* 8378 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8387 -/* 8382 */ MCD_OPC_Decode, 220, 19, 130, 2, // Opcode: VMOF -/* 8387 */ MCD_OPC_CheckPredicate, 22, 204, 41, // Skip to: 19091 -/* 8391 */ MCD_OPC_Decode, 218, 19, 131, 2, // Opcode: VMO -/* 8396 */ MCD_OPC_FilterValue, 169, 1, 58, 0, // Skip to: 8459 -/* 8401 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8404 */ MCD_OPC_FilterValue, 0, 187, 41, // Skip to: 19091 -/* 8408 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8411 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8424 -/* 8415 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8450 -/* 8419 */ MCD_OPC_Decode, 172, 19, 146, 2, // Opcode: VMALHB -/* 8424 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8437 -/* 8428 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8450 -/* 8432 */ MCD_OPC_Decode, 174, 19, 146, 2, // Opcode: VMALHH -/* 8437 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8450 -/* 8441 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8450 -/* 8445 */ MCD_OPC_Decode, 173, 19, 146, 2, // Opcode: VMALHF -/* 8450 */ MCD_OPC_CheckPredicate, 22, 141, 41, // Skip to: 19091 -/* 8454 */ MCD_OPC_Decode, 171, 19, 150, 2, // Opcode: VMALH -/* 8459 */ MCD_OPC_FilterValue, 170, 1, 58, 0, // Skip to: 8522 -/* 8464 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8467 */ MCD_OPC_FilterValue, 0, 124, 41, // Skip to: 19091 -/* 8471 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8474 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8487 -/* 8478 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8513 -/* 8482 */ MCD_OPC_Decode, 165, 19, 146, 2, // Opcode: VMALB -/* 8487 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8500 -/* 8491 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8513 -/* 8495 */ MCD_OPC_Decode, 175, 19, 146, 2, // Opcode: VMALHW -/* 8500 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8513 -/* 8504 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8513 -/* 8508 */ MCD_OPC_Decode, 170, 19, 146, 2, // Opcode: VMALF -/* 8513 */ MCD_OPC_CheckPredicate, 22, 78, 41, // Skip to: 19091 -/* 8517 */ MCD_OPC_Decode, 164, 19, 150, 2, // Opcode: VMAL -/* 8522 */ MCD_OPC_FilterValue, 171, 1, 58, 0, // Skip to: 8585 -/* 8527 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8530 */ MCD_OPC_FilterValue, 0, 61, 41, // Skip to: 19091 -/* 8534 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8537 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8550 -/* 8541 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8576 -/* 8545 */ MCD_OPC_Decode, 161, 19, 146, 2, // Opcode: VMAHB -/* 8550 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8563 -/* 8554 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8576 -/* 8558 */ MCD_OPC_Decode, 163, 19, 146, 2, // Opcode: VMAHH -/* 8563 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8576 -/* 8567 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8576 -/* 8571 */ MCD_OPC_Decode, 162, 19, 146, 2, // Opcode: VMAHF -/* 8576 */ MCD_OPC_CheckPredicate, 22, 15, 41, // Skip to: 19091 -/* 8580 */ MCD_OPC_Decode, 160, 19, 150, 2, // Opcode: VMAH -/* 8585 */ MCD_OPC_FilterValue, 172, 1, 58, 0, // Skip to: 8648 -/* 8590 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8593 */ MCD_OPC_FilterValue, 0, 254, 40, // Skip to: 19091 -/* 8597 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8600 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8613 -/* 8604 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8639 -/* 8608 */ MCD_OPC_Decode, 167, 19, 146, 2, // Opcode: VMALEB -/* 8613 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8626 -/* 8617 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8639 -/* 8621 */ MCD_OPC_Decode, 169, 19, 146, 2, // Opcode: VMALEH -/* 8626 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8639 -/* 8630 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8639 -/* 8634 */ MCD_OPC_Decode, 168, 19, 146, 2, // Opcode: VMALEF -/* 8639 */ MCD_OPC_CheckPredicate, 22, 208, 40, // Skip to: 19091 -/* 8643 */ MCD_OPC_Decode, 166, 19, 150, 2, // Opcode: VMALE -/* 8648 */ MCD_OPC_FilterValue, 173, 1, 58, 0, // Skip to: 8711 -/* 8653 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8656 */ MCD_OPC_FilterValue, 0, 191, 40, // Skip to: 19091 -/* 8660 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8663 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8676 -/* 8667 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8702 -/* 8671 */ MCD_OPC_Decode, 177, 19, 146, 2, // Opcode: VMALOB -/* 8676 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8689 -/* 8680 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8702 -/* 8684 */ MCD_OPC_Decode, 179, 19, 146, 2, // Opcode: VMALOH -/* 8689 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8702 -/* 8693 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8702 -/* 8697 */ MCD_OPC_Decode, 178, 19, 146, 2, // Opcode: VMALOF -/* 8702 */ MCD_OPC_CheckPredicate, 22, 145, 40, // Skip to: 19091 -/* 8706 */ MCD_OPC_Decode, 176, 19, 150, 2, // Opcode: VMALO -/* 8711 */ MCD_OPC_FilterValue, 174, 1, 58, 0, // Skip to: 8774 -/* 8716 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8719 */ MCD_OPC_FilterValue, 0, 128, 40, // Skip to: 19091 -/* 8723 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8726 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8739 -/* 8730 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8765 -/* 8734 */ MCD_OPC_Decode, 157, 19, 146, 2, // Opcode: VMAEB -/* 8739 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8752 -/* 8743 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8765 -/* 8747 */ MCD_OPC_Decode, 159, 19, 146, 2, // Opcode: VMAEH -/* 8752 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8765 -/* 8756 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8765 -/* 8760 */ MCD_OPC_Decode, 158, 19, 146, 2, // Opcode: VMAEF -/* 8765 */ MCD_OPC_CheckPredicate, 22, 82, 40, // Skip to: 19091 -/* 8769 */ MCD_OPC_Decode, 156, 19, 150, 2, // Opcode: VMAE -/* 8774 */ MCD_OPC_FilterValue, 175, 1, 58, 0, // Skip to: 8837 -/* 8779 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8782 */ MCD_OPC_FilterValue, 0, 65, 40, // Skip to: 19091 -/* 8786 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 8789 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8802 -/* 8793 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8828 -/* 8797 */ MCD_OPC_Decode, 181, 19, 146, 2, // Opcode: VMAOB -/* 8802 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8815 -/* 8806 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8828 -/* 8810 */ MCD_OPC_Decode, 183, 19, 146, 2, // Opcode: VMAOH -/* 8815 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8828 -/* 8819 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8828 -/* 8823 */ MCD_OPC_Decode, 182, 19, 146, 2, // Opcode: VMAOF -/* 8828 */ MCD_OPC_CheckPredicate, 22, 19, 40, // Skip to: 19091 -/* 8832 */ MCD_OPC_Decode, 180, 19, 150, 2, // Opcode: VMAO -/* 8837 */ MCD_OPC_FilterValue, 180, 1, 78, 0, // Skip to: 8920 -/* 8842 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 8845 */ MCD_OPC_FilterValue, 0, 2, 40, // Skip to: 19091 -/* 8849 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 8852 */ MCD_OPC_FilterValue, 0, 251, 39, // Skip to: 19091 -/* 8856 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 8859 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8872 -/* 8863 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 8911 -/* 8867 */ MCD_OPC_Decode, 216, 18, 130, 2, // Opcode: VGFMB -/* 8872 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8885 -/* 8876 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8911 -/* 8880 */ MCD_OPC_Decode, 219, 18, 130, 2, // Opcode: VGFMH -/* 8885 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8898 -/* 8889 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8911 -/* 8893 */ MCD_OPC_Decode, 217, 18, 130, 2, // Opcode: VGFMF -/* 8898 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8911 -/* 8902 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8911 -/* 8906 */ MCD_OPC_Decode, 218, 18, 130, 2, // Opcode: VGFMG -/* 8911 */ MCD_OPC_CheckPredicate, 22, 192, 39, // Skip to: 19091 -/* 8915 */ MCD_OPC_Decode, 210, 18, 131, 2, // Opcode: VGFM -/* 8920 */ MCD_OPC_FilterValue, 184, 1, 31, 0, // Skip to: 8956 -/* 8925 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 8928 */ MCD_OPC_FilterValue, 0, 175, 39, // Skip to: 19091 -/* 8932 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 8947 -/* 8936 */ MCD_OPC_CheckField, 24, 4, 3, 5, 0, // Skip to: 8947 -/* 8942 */ MCD_OPC_Decode, 234, 19, 144, 2, // Opcode: VMSLG -/* 8947 */ MCD_OPC_CheckPredicate, 23, 156, 39, // Skip to: 19091 -/* 8951 */ MCD_OPC_Decode, 233, 19, 145, 2, // Opcode: VMSL -/* 8956 */ MCD_OPC_FilterValue, 185, 1, 31, 0, // Skip to: 8992 -/* 8961 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 8964 */ MCD_OPC_FilterValue, 0, 139, 39, // Skip to: 19091 -/* 8968 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 8983 -/* 8972 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 8983 -/* 8978 */ MCD_OPC_Decode, 216, 16, 146, 2, // Opcode: VACCCQ -/* 8983 */ MCD_OPC_CheckPredicate, 22, 120, 39, // Skip to: 19091 -/* 8987 */ MCD_OPC_Decode, 215, 16, 150, 2, // Opcode: VACCC -/* 8992 */ MCD_OPC_FilterValue, 187, 1, 31, 0, // Skip to: 9028 -/* 8997 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 9000 */ MCD_OPC_FilterValue, 0, 103, 39, // Skip to: 19091 -/* 9004 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9019 -/* 9008 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9019 -/* 9014 */ MCD_OPC_Decode, 221, 16, 146, 2, // Opcode: VACQ -/* 9019 */ MCD_OPC_CheckPredicate, 22, 84, 39, // Skip to: 19091 -/* 9023 */ MCD_OPC_Decode, 212, 16, 150, 2, // Opcode: VAC -/* 9028 */ MCD_OPC_FilterValue, 188, 1, 71, 0, // Skip to: 9104 -/* 9033 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 9036 */ MCD_OPC_FilterValue, 0, 67, 39, // Skip to: 19091 -/* 9040 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 9043 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9056 -/* 9047 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 9095 -/* 9051 */ MCD_OPC_Decode, 212, 18, 146, 2, // Opcode: VGFMAB -/* 9056 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9069 -/* 9060 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 9095 -/* 9064 */ MCD_OPC_Decode, 215, 18, 146, 2, // Opcode: VGFMAH -/* 9069 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9082 -/* 9073 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9095 -/* 9077 */ MCD_OPC_Decode, 213, 18, 146, 2, // Opcode: VGFMAF -/* 9082 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9095 -/* 9086 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9095 -/* 9090 */ MCD_OPC_Decode, 214, 18, 146, 2, // Opcode: VGFMAG -/* 9095 */ MCD_OPC_CheckPredicate, 22, 8, 39, // Skip to: 19091 -/* 9099 */ MCD_OPC_Decode, 211, 18, 150, 2, // Opcode: VGFMA -/* 9104 */ MCD_OPC_FilterValue, 189, 1, 31, 0, // Skip to: 9140 -/* 9109 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 9112 */ MCD_OPC_FilterValue, 0, 247, 38, // Skip to: 19091 -/* 9116 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9131 -/* 9120 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9131 -/* 9126 */ MCD_OPC_Decode, 167, 20, 146, 2, // Opcode: VSBCBIQ -/* 9131 */ MCD_OPC_CheckPredicate, 22, 228, 38, // Skip to: 19091 -/* 9135 */ MCD_OPC_Decode, 166, 20, 150, 2, // Opcode: VSBCBI -/* 9140 */ MCD_OPC_FilterValue, 191, 1, 31, 0, // Skip to: 9176 -/* 9145 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 9148 */ MCD_OPC_FilterValue, 0, 211, 38, // Skip to: 19091 -/* 9152 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9167 -/* 9156 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9167 -/* 9162 */ MCD_OPC_Decode, 169, 20, 146, 2, // Opcode: VSBIQ -/* 9167 */ MCD_OPC_CheckPredicate, 22, 192, 38, // Skip to: 19091 -/* 9171 */ MCD_OPC_Decode, 168, 20, 150, 2, // Opcode: VSBI -/* 9176 */ MCD_OPC_FilterValue, 192, 1, 54, 0, // Skip to: 9235 -/* 9181 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9184 */ MCD_OPC_FilterValue, 0, 175, 38, // Skip to: 19091 -/* 9188 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9191 */ MCD_OPC_FilterValue, 0, 168, 38, // Skip to: 19091 -/* 9195 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9198 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9226 -/* 9202 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9217 -/* 9206 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9217 -/* 9212 */ MCD_OPC_Decode, 252, 20, 151, 2, // Opcode: WCLGDB -/* 9217 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9226 -/* 9221 */ MCD_OPC_Decode, 145, 17, 152, 2, // Opcode: VCLGDB -/* 9226 */ MCD_OPC_CheckPredicate, 22, 133, 38, // Skip to: 19091 -/* 9230 */ MCD_OPC_Decode, 144, 17, 153, 2, // Opcode: VCLGD -/* 9235 */ MCD_OPC_FilterValue, 193, 1, 54, 0, // Skip to: 9294 -/* 9240 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9243 */ MCD_OPC_FilterValue, 0, 116, 38, // Skip to: 19091 -/* 9247 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9250 */ MCD_OPC_FilterValue, 0, 109, 38, // Skip to: 19091 -/* 9254 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9257 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9285 -/* 9261 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9276 -/* 9265 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9276 -/* 9271 */ MCD_OPC_Decode, 250, 20, 151, 2, // Opcode: WCDLGB -/* 9276 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9285 -/* 9280 */ MCD_OPC_Decode, 241, 16, 152, 2, // Opcode: VCDLGB -/* 9285 */ MCD_OPC_CheckPredicate, 22, 74, 38, // Skip to: 19091 -/* 9289 */ MCD_OPC_Decode, 240, 16, 153, 2, // Opcode: VCDLG -/* 9294 */ MCD_OPC_FilterValue, 194, 1, 54, 0, // Skip to: 9353 -/* 9299 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9302 */ MCD_OPC_FilterValue, 0, 57, 38, // Skip to: 19091 -/* 9306 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9309 */ MCD_OPC_FilterValue, 0, 50, 38, // Skip to: 19091 -/* 9313 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9316 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9344 -/* 9320 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9335 -/* 9324 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9335 -/* 9330 */ MCD_OPC_Decode, 251, 20, 151, 2, // Opcode: WCGDB -/* 9335 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9344 -/* 9339 */ MCD_OPC_Decode, 252, 16, 152, 2, // Opcode: VCGDB -/* 9344 */ MCD_OPC_CheckPredicate, 22, 15, 38, // Skip to: 19091 -/* 9348 */ MCD_OPC_Decode, 251, 16, 153, 2, // Opcode: VCGD -/* 9353 */ MCD_OPC_FilterValue, 195, 1, 54, 0, // Skip to: 9412 -/* 9358 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9361 */ MCD_OPC_FilterValue, 0, 254, 37, // Skip to: 19091 -/* 9365 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9368 */ MCD_OPC_FilterValue, 0, 247, 37, // Skip to: 19091 -/* 9372 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9375 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9403 -/* 9379 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9394 -/* 9383 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9394 -/* 9389 */ MCD_OPC_Decode, 249, 20, 151, 2, // Opcode: WCDGB -/* 9394 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9403 -/* 9398 */ MCD_OPC_Decode, 239, 16, 152, 2, // Opcode: VCDGB -/* 9403 */ MCD_OPC_CheckPredicate, 22, 212, 37, // Skip to: 19091 -/* 9407 */ MCD_OPC_Decode, 238, 16, 153, 2, // Opcode: VCDG -/* 9412 */ MCD_OPC_FilterValue, 196, 1, 67, 0, // Skip to: 9484 -/* 9417 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9420 */ MCD_OPC_FilterValue, 0, 195, 37, // Skip to: 19091 -/* 9424 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... -/* 9427 */ MCD_OPC_FilterValue, 0, 188, 37, // Skip to: 19091 -/* 9431 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 9434 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9447 -/* 9438 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 9475 -/* 9442 */ MCD_OPC_Decode, 240, 18, 254, 1, // Opcode: VLDEB -/* 9447 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 9461 -/* 9452 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 9475 -/* 9456 */ MCD_OPC_Decode, 224, 21, 154, 2, // Opcode: WLDEB -/* 9461 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 9475 -/* 9466 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9475 -/* 9470 */ MCD_OPC_Decode, 181, 21, 155, 2, // Opcode: WFLLD -/* 9475 */ MCD_OPC_CheckPredicate, 22, 140, 37, // Skip to: 19091 -/* 9479 */ MCD_OPC_Decode, 239, 18, 156, 2, // Opcode: VLDE -/* 9484 */ MCD_OPC_FilterValue, 197, 1, 73, 0, // Skip to: 9562 -/* 9489 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9492 */ MCD_OPC_FilterValue, 0, 123, 37, // Skip to: 19091 -/* 9496 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9499 */ MCD_OPC_FilterValue, 0, 116, 37, // Skip to: 19091 -/* 9503 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9506 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9534 -/* 9510 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9525 -/* 9514 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9525 -/* 9520 */ MCD_OPC_Decode, 225, 21, 157, 2, // Opcode: WLEDB -/* 9525 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 9553 -/* 9529 */ MCD_OPC_Decode, 243, 18, 152, 2, // Opcode: VLEDB -/* 9534 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 9553 -/* 9538 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9553 -/* 9542 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9553 -/* 9548 */ MCD_OPC_Decode, 190, 21, 158, 2, // Opcode: WFLRX -/* 9553 */ MCD_OPC_CheckPredicate, 22, 62, 37, // Skip to: 19091 -/* 9557 */ MCD_OPC_Decode, 242, 18, 153, 2, // Opcode: VLED -/* 9562 */ MCD_OPC_FilterValue, 199, 1, 101, 0, // Skip to: 9668 -/* 9567 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9570 */ MCD_OPC_FilterValue, 0, 45, 37, // Skip to: 19091 -/* 9574 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9577 */ MCD_OPC_FilterValue, 0, 38, 37, // Skip to: 19091 -/* 9581 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 9584 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 9612 -/* 9588 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9603 -/* 9592 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9603 -/* 9598 */ MCD_OPC_Decode, 154, 21, 159, 2, // Opcode: WFISB -/* 9603 */ MCD_OPC_CheckPredicate, 23, 52, 0, // Skip to: 9659 -/* 9607 */ MCD_OPC_Decode, 151, 18, 152, 2, // Opcode: VFISB -/* 9612 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9640 -/* 9616 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9631 -/* 9620 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9631 -/* 9626 */ MCD_OPC_Decode, 153, 21, 151, 2, // Opcode: WFIDB -/* 9631 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 9659 -/* 9635 */ MCD_OPC_Decode, 150, 18, 152, 2, // Opcode: VFIDB -/* 9640 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 9659 -/* 9644 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9659 -/* 9648 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9659 -/* 9654 */ MCD_OPC_Decode, 155, 21, 160, 2, // Opcode: WFIXB -/* 9659 */ MCD_OPC_CheckPredicate, 22, 212, 36, // Skip to: 19091 -/* 9663 */ MCD_OPC_Decode, 149, 18, 153, 2, // Opcode: VFI -/* 9668 */ MCD_OPC_FilterValue, 202, 1, 65, 0, // Skip to: 9738 -/* 9673 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9676 */ MCD_OPC_FilterValue, 0, 195, 36, // Skip to: 19091 -/* 9680 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... -/* 9683 */ MCD_OPC_FilterValue, 0, 188, 36, // Skip to: 19091 -/* 9687 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 9690 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9703 -/* 9694 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 9729 -/* 9698 */ MCD_OPC_Decode, 176, 21, 161, 2, // Opcode: WFKSB -/* 9703 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9716 -/* 9707 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9729 -/* 9711 */ MCD_OPC_Decode, 157, 21, 162, 2, // Opcode: WFKDB -/* 9716 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9729 -/* 9720 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9729 -/* 9724 */ MCD_OPC_Decode, 177, 21, 254, 1, // Opcode: WFKXB -/* 9729 */ MCD_OPC_CheckPredicate, 22, 142, 36, // Skip to: 19091 -/* 9733 */ MCD_OPC_Decode, 156, 21, 163, 2, // Opcode: WFK -/* 9738 */ MCD_OPC_FilterValue, 203, 1, 65, 0, // Skip to: 9808 -/* 9743 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9746 */ MCD_OPC_FilterValue, 0, 125, 36, // Skip to: 19091 -/* 9750 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... -/* 9753 */ MCD_OPC_FilterValue, 0, 118, 36, // Skip to: 19091 -/* 9757 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 9760 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9773 -/* 9764 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 9799 -/* 9768 */ MCD_OPC_Decode, 148, 21, 161, 2, // Opcode: WFCSB -/* 9773 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9786 -/* 9777 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9799 -/* 9781 */ MCD_OPC_Decode, 129, 21, 162, 2, // Opcode: WFCDB -/* 9786 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9799 -/* 9790 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9799 -/* 9794 */ MCD_OPC_Decode, 149, 21, 254, 1, // Opcode: WFCXB -/* 9799 */ MCD_OPC_CheckPredicate, 22, 72, 36, // Skip to: 19091 -/* 9803 */ MCD_OPC_Decode, 128, 21, 163, 2, // Opcode: WFC -/* 9808 */ MCD_OPC_FilterValue, 204, 1, 49, 1, // Skip to: 10118 -/* 9813 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 9816 */ MCD_OPC_FilterValue, 0, 55, 36, // Skip to: 19091 -/* 9820 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... -/* 9823 */ MCD_OPC_FilterValue, 0, 48, 36, // Skip to: 19091 -/* 9827 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 9830 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9843 -/* 9834 */ MCD_OPC_CheckPredicate, 23, 200, 0, // Skip to: 10038 -/* 9838 */ MCD_OPC_Decode, 165, 18, 254, 1, // Opcode: VFLCSB -/* 9843 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9856 -/* 9847 */ MCD_OPC_CheckPredicate, 22, 187, 0, // Skip to: 10038 -/* 9851 */ MCD_OPC_Decode, 164, 18, 254, 1, // Opcode: VFLCDB -/* 9856 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 9870 -/* 9861 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 10038 -/* 9865 */ MCD_OPC_Decode, 179, 21, 161, 2, // Opcode: WFLCSB -/* 9870 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 9884 -/* 9875 */ MCD_OPC_CheckPredicate, 22, 159, 0, // Skip to: 10038 -/* 9879 */ MCD_OPC_Decode, 178, 21, 162, 2, // Opcode: WFLCDB -/* 9884 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 9898 -/* 9889 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 10038 -/* 9893 */ MCD_OPC_Decode, 180, 21, 254, 1, // Opcode: WFLCXB -/* 9898 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 9912 -/* 9903 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 10038 -/* 9907 */ MCD_OPC_Decode, 169, 18, 254, 1, // Opcode: VFLNSB -/* 9912 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 9926 -/* 9917 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 10038 -/* 9921 */ MCD_OPC_Decode, 168, 18, 254, 1, // Opcode: VFLNDB -/* 9926 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 9940 -/* 9931 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 10038 -/* 9935 */ MCD_OPC_Decode, 184, 21, 161, 2, // Opcode: WFLNSB -/* 9940 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 9954 -/* 9945 */ MCD_OPC_CheckPredicate, 22, 89, 0, // Skip to: 10038 -/* 9949 */ MCD_OPC_Decode, 183, 21, 162, 2, // Opcode: WFLNDB -/* 9954 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 9968 -/* 9959 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 10038 -/* 9963 */ MCD_OPC_Decode, 185, 21, 254, 1, // Opcode: WFLNXB -/* 9968 */ MCD_OPC_FilterValue, 130, 4, 9, 0, // Skip to: 9982 -/* 9973 */ MCD_OPC_CheckPredicate, 23, 61, 0, // Skip to: 10038 -/* 9977 */ MCD_OPC_Decode, 171, 18, 254, 1, // Opcode: VFLPSB -/* 9982 */ MCD_OPC_FilterValue, 131, 4, 9, 0, // Skip to: 9996 -/* 9987 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10038 -/* 9991 */ MCD_OPC_Decode, 170, 18, 254, 1, // Opcode: VFLPDB -/* 9996 */ MCD_OPC_FilterValue, 130, 5, 9, 0, // Skip to: 10010 -/* 10001 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10038 -/* 10005 */ MCD_OPC_Decode, 187, 21, 161, 2, // Opcode: WFLPSB -/* 10010 */ MCD_OPC_FilterValue, 131, 5, 9, 0, // Skip to: 10024 -/* 10015 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10038 -/* 10019 */ MCD_OPC_Decode, 186, 21, 162, 2, // Opcode: WFLPDB -/* 10024 */ MCD_OPC_FilterValue, 132, 5, 9, 0, // Skip to: 10038 -/* 10029 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10038 -/* 10033 */ MCD_OPC_Decode, 188, 21, 254, 1, // Opcode: WFLPXB -/* 10038 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 10041 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10054 -/* 10045 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10109 -/* 10049 */ MCD_OPC_Decode, 197, 18, 128, 2, // Opcode: VFPSOSB -/* 10054 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10067 -/* 10058 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10109 -/* 10062 */ MCD_OPC_Decode, 196, 18, 128, 2, // Opcode: VFPSODB -/* 10067 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10081 -/* 10072 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10109 -/* 10076 */ MCD_OPC_Decode, 213, 21, 164, 2, // Opcode: WFPSOSB -/* 10081 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10095 -/* 10086 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10109 -/* 10090 */ MCD_OPC_Decode, 212, 21, 165, 2, // Opcode: WFPSODB -/* 10095 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10109 -/* 10100 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10109 -/* 10104 */ MCD_OPC_Decode, 214, 21, 128, 2, // Opcode: WFPSOXB -/* 10109 */ MCD_OPC_CheckPredicate, 22, 18, 35, // Skip to: 19091 -/* 10113 */ MCD_OPC_Decode, 195, 18, 153, 2, // Opcode: VFPSO -/* 10118 */ MCD_OPC_FilterValue, 206, 1, 94, 0, // Skip to: 10217 -/* 10123 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10126 */ MCD_OPC_FilterValue, 0, 1, 35, // Skip to: 19091 -/* 10130 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... -/* 10133 */ MCD_OPC_FilterValue, 0, 250, 34, // Skip to: 19091 -/* 10137 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 10140 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10153 -/* 10144 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10208 -/* 10148 */ MCD_OPC_Decode, 202, 18, 254, 1, // Opcode: VFSQSB -/* 10153 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10166 -/* 10157 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10208 -/* 10161 */ MCD_OPC_Decode, 201, 18, 254, 1, // Opcode: VFSQDB -/* 10166 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10180 -/* 10171 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10208 -/* 10175 */ MCD_OPC_Decode, 217, 21, 161, 2, // Opcode: WFSQSB -/* 10180 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10194 -/* 10185 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10208 -/* 10189 */ MCD_OPC_Decode, 216, 21, 162, 2, // Opcode: WFSQDB -/* 10194 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10208 -/* 10199 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10208 -/* 10203 */ MCD_OPC_Decode, 218, 21, 254, 1, // Opcode: WFSQXB -/* 10208 */ MCD_OPC_CheckPredicate, 22, 175, 34, // Skip to: 19091 -/* 10212 */ MCD_OPC_Decode, 200, 18, 156, 2, // Opcode: VFSQ -/* 10217 */ MCD_OPC_FilterValue, 212, 1, 65, 0, // Skip to: 10287 -/* 10222 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10225 */ MCD_OPC_FilterValue, 0, 158, 34, // Skip to: 19091 -/* 10229 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10232 */ MCD_OPC_FilterValue, 0, 151, 34, // Skip to: 19091 -/* 10236 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10239 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10252 -/* 10243 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10278 -/* 10247 */ MCD_OPC_Decode, 244, 20, 254, 1, // Opcode: VUPLLB -/* 10252 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10265 -/* 10256 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10278 -/* 10260 */ MCD_OPC_Decode, 246, 20, 254, 1, // Opcode: VUPLLH -/* 10265 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10278 -/* 10269 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10278 -/* 10273 */ MCD_OPC_Decode, 245, 20, 254, 1, // Opcode: VUPLLF -/* 10278 */ MCD_OPC_CheckPredicate, 22, 105, 34, // Skip to: 19091 -/* 10282 */ MCD_OPC_Decode, 243, 20, 255, 1, // Opcode: VUPLL -/* 10287 */ MCD_OPC_FilterValue, 213, 1, 65, 0, // Skip to: 10357 -/* 10292 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10295 */ MCD_OPC_FilterValue, 0, 88, 34, // Skip to: 19091 -/* 10299 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10302 */ MCD_OPC_FilterValue, 0, 81, 34, // Skip to: 19091 -/* 10306 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10309 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10322 -/* 10313 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10348 -/* 10317 */ MCD_OPC_Decode, 239, 20, 254, 1, // Opcode: VUPLHB -/* 10322 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10335 -/* 10326 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10348 -/* 10330 */ MCD_OPC_Decode, 241, 20, 254, 1, // Opcode: VUPLHH -/* 10335 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10348 -/* 10339 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10348 -/* 10343 */ MCD_OPC_Decode, 240, 20, 254, 1, // Opcode: VUPLHF -/* 10348 */ MCD_OPC_CheckPredicate, 22, 35, 34, // Skip to: 19091 -/* 10352 */ MCD_OPC_Decode, 238, 20, 255, 1, // Opcode: VUPLH -/* 10357 */ MCD_OPC_FilterValue, 214, 1, 65, 0, // Skip to: 10427 -/* 10362 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10365 */ MCD_OPC_FilterValue, 0, 18, 34, // Skip to: 19091 -/* 10369 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10372 */ MCD_OPC_FilterValue, 0, 11, 34, // Skip to: 19091 -/* 10376 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10379 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10392 -/* 10383 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10418 -/* 10387 */ MCD_OPC_Decode, 236, 20, 254, 1, // Opcode: VUPLB -/* 10392 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10405 -/* 10396 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10418 -/* 10400 */ MCD_OPC_Decode, 242, 20, 254, 1, // Opcode: VUPLHW -/* 10405 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10418 -/* 10409 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10418 -/* 10413 */ MCD_OPC_Decode, 237, 20, 254, 1, // Opcode: VUPLF -/* 10418 */ MCD_OPC_CheckPredicate, 22, 221, 33, // Skip to: 19091 -/* 10422 */ MCD_OPC_Decode, 235, 20, 255, 1, // Opcode: VUPL -/* 10427 */ MCD_OPC_FilterValue, 215, 1, 65, 0, // Skip to: 10497 -/* 10432 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10435 */ MCD_OPC_FilterValue, 0, 204, 33, // Skip to: 19091 -/* 10439 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10442 */ MCD_OPC_FilterValue, 0, 197, 33, // Skip to: 19091 -/* 10446 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10449 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10462 -/* 10453 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10488 -/* 10457 */ MCD_OPC_Decode, 231, 20, 254, 1, // Opcode: VUPHB -/* 10462 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10475 -/* 10466 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10488 -/* 10470 */ MCD_OPC_Decode, 233, 20, 254, 1, // Opcode: VUPHH -/* 10475 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10488 -/* 10479 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10488 -/* 10483 */ MCD_OPC_Decode, 232, 20, 254, 1, // Opcode: VUPHF -/* 10488 */ MCD_OPC_CheckPredicate, 22, 151, 33, // Skip to: 19091 -/* 10492 */ MCD_OPC_Decode, 230, 20, 255, 1, // Opcode: VUPH -/* 10497 */ MCD_OPC_FilterValue, 216, 1, 21, 0, // Skip to: 10523 -/* 10502 */ MCD_OPC_CheckPredicate, 22, 137, 33, // Skip to: 19091 -/* 10506 */ MCD_OPC_CheckField, 12, 20, 0, 131, 33, // Skip to: 19091 -/* 10512 */ MCD_OPC_CheckField, 8, 2, 0, 125, 33, // Skip to: 19091 -/* 10518 */ MCD_OPC_Decode, 228, 20, 254, 1, // Opcode: VTM -/* 10523 */ MCD_OPC_FilterValue, 217, 1, 78, 0, // Skip to: 10606 -/* 10528 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10531 */ MCD_OPC_FilterValue, 0, 108, 33, // Skip to: 19091 -/* 10535 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10538 */ MCD_OPC_FilterValue, 0, 101, 33, // Skip to: 19091 -/* 10542 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10545 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10558 -/* 10549 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10597 -/* 10553 */ MCD_OPC_Decode, 168, 17, 254, 1, // Opcode: VECLB -/* 10558 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10571 -/* 10562 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10597 -/* 10566 */ MCD_OPC_Decode, 171, 17, 254, 1, // Opcode: VECLH -/* 10571 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10584 -/* 10575 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10597 -/* 10579 */ MCD_OPC_Decode, 169, 17, 254, 1, // Opcode: VECLF -/* 10584 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10597 -/* 10588 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10597 -/* 10592 */ MCD_OPC_Decode, 170, 17, 254, 1, // Opcode: VECLG -/* 10597 */ MCD_OPC_CheckPredicate, 22, 42, 33, // Skip to: 19091 -/* 10601 */ MCD_OPC_Decode, 167, 17, 255, 1, // Opcode: VECL -/* 10606 */ MCD_OPC_FilterValue, 219, 1, 78, 0, // Skip to: 10689 -/* 10611 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10614 */ MCD_OPC_FilterValue, 0, 25, 33, // Skip to: 19091 -/* 10618 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10621 */ MCD_OPC_FilterValue, 0, 18, 33, // Skip to: 19091 -/* 10625 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10628 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10641 -/* 10632 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10680 -/* 10636 */ MCD_OPC_Decode, 163, 17, 254, 1, // Opcode: VECB -/* 10641 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10654 -/* 10645 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10680 -/* 10649 */ MCD_OPC_Decode, 166, 17, 254, 1, // Opcode: VECH -/* 10654 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10667 -/* 10658 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10680 -/* 10662 */ MCD_OPC_Decode, 164, 17, 254, 1, // Opcode: VECF -/* 10667 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10680 -/* 10671 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10680 -/* 10675 */ MCD_OPC_Decode, 165, 17, 254, 1, // Opcode: VECG -/* 10680 */ MCD_OPC_CheckPredicate, 22, 215, 32, // Skip to: 19091 -/* 10684 */ MCD_OPC_Decode, 162, 17, 255, 1, // Opcode: VEC -/* 10689 */ MCD_OPC_FilterValue, 222, 1, 78, 0, // Skip to: 10772 -/* 10694 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10697 */ MCD_OPC_FilterValue, 0, 198, 32, // Skip to: 19091 -/* 10701 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10704 */ MCD_OPC_FilterValue, 0, 191, 32, // Skip to: 19091 -/* 10708 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10711 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10724 -/* 10715 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10763 -/* 10719 */ MCD_OPC_Decode, 235, 18, 254, 1, // Opcode: VLCB -/* 10724 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10737 -/* 10728 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10763 -/* 10732 */ MCD_OPC_Decode, 238, 18, 254, 1, // Opcode: VLCH -/* 10737 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10750 -/* 10741 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10763 -/* 10745 */ MCD_OPC_Decode, 236, 18, 254, 1, // Opcode: VLCF -/* 10750 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10763 -/* 10754 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10763 -/* 10758 */ MCD_OPC_Decode, 237, 18, 254, 1, // Opcode: VLCG -/* 10763 */ MCD_OPC_CheckPredicate, 22, 132, 32, // Skip to: 19091 -/* 10767 */ MCD_OPC_Decode, 234, 18, 255, 1, // Opcode: VLC -/* 10772 */ MCD_OPC_FilterValue, 223, 1, 78, 0, // Skip to: 10855 -/* 10777 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... -/* 10780 */ MCD_OPC_FilterValue, 0, 115, 32, // Skip to: 19091 -/* 10784 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... -/* 10787 */ MCD_OPC_FilterValue, 0, 108, 32, // Skip to: 19091 -/* 10791 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 10794 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10807 -/* 10798 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10846 -/* 10802 */ MCD_OPC_Decode, 138, 19, 254, 1, // Opcode: VLPB -/* 10807 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10820 -/* 10811 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10846 -/* 10815 */ MCD_OPC_Decode, 141, 19, 254, 1, // Opcode: VLPH -/* 10820 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10833 -/* 10824 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10846 -/* 10828 */ MCD_OPC_Decode, 139, 19, 254, 1, // Opcode: VLPF -/* 10833 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10846 -/* 10837 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10846 -/* 10841 */ MCD_OPC_Decode, 140, 19, 254, 1, // Opcode: VLPG -/* 10846 */ MCD_OPC_CheckPredicate, 22, 49, 32, // Skip to: 19091 -/* 10850 */ MCD_OPC_Decode, 137, 19, 255, 1, // Opcode: VLP -/* 10855 */ MCD_OPC_FilterValue, 226, 1, 94, 0, // Skip to: 10954 -/* 10860 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 10863 */ MCD_OPC_FilterValue, 0, 32, 32, // Skip to: 19091 -/* 10867 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... -/* 10870 */ MCD_OPC_FilterValue, 0, 25, 32, // Skip to: 19091 -/* 10874 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 10877 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10890 -/* 10881 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10945 -/* 10885 */ MCD_OPC_Decode, 203, 18, 130, 2, // Opcode: VFSSB -/* 10890 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10903 -/* 10894 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10945 -/* 10898 */ MCD_OPC_Decode, 199, 18, 130, 2, // Opcode: VFSDB -/* 10903 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10917 -/* 10908 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10945 -/* 10912 */ MCD_OPC_Decode, 219, 21, 166, 2, // Opcode: WFSSB -/* 10917 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10931 -/* 10922 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10945 -/* 10926 */ MCD_OPC_Decode, 215, 21, 167, 2, // Opcode: WFSDB -/* 10931 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10945 -/* 10936 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10945 -/* 10940 */ MCD_OPC_Decode, 220, 21, 130, 2, // Opcode: WFSXB -/* 10945 */ MCD_OPC_CheckPredicate, 22, 206, 31, // Skip to: 19091 -/* 10949 */ MCD_OPC_Decode, 198, 18, 168, 2, // Opcode: VFS -/* 10954 */ MCD_OPC_FilterValue, 227, 1, 94, 0, // Skip to: 11053 -/* 10959 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 10962 */ MCD_OPC_FilterValue, 0, 189, 31, // Skip to: 19091 -/* 10966 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... -/* 10969 */ MCD_OPC_FilterValue, 0, 182, 31, // Skip to: 19091 -/* 10973 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 10976 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10989 -/* 10980 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11044 -/* 10984 */ MCD_OPC_Decode, 232, 17, 130, 2, // Opcode: VFASB -/* 10989 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11002 -/* 10993 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11044 -/* 10997 */ MCD_OPC_Decode, 218, 17, 130, 2, // Opcode: VFADB -/* 11002 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11016 -/* 11007 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11044 -/* 11011 */ MCD_OPC_Decode, 254, 20, 166, 2, // Opcode: WFASB -/* 11016 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11030 -/* 11021 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11044 -/* 11025 */ MCD_OPC_Decode, 253, 20, 167, 2, // Opcode: WFADB -/* 11030 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11044 -/* 11035 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11044 -/* 11039 */ MCD_OPC_Decode, 255, 20, 130, 2, // Opcode: WFAXB -/* 11044 */ MCD_OPC_CheckPredicate, 22, 107, 31, // Skip to: 19091 -/* 11048 */ MCD_OPC_Decode, 217, 17, 168, 2, // Opcode: VFA -/* 11053 */ MCD_OPC_FilterValue, 229, 1, 94, 0, // Skip to: 11152 -/* 11058 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11061 */ MCD_OPC_FilterValue, 0, 90, 31, // Skip to: 19091 -/* 11065 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... -/* 11068 */ MCD_OPC_FilterValue, 0, 83, 31, // Skip to: 19091 -/* 11072 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 11075 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11088 -/* 11079 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11143 -/* 11083 */ MCD_OPC_Decode, 250, 17, 130, 2, // Opcode: VFDSB -/* 11088 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11101 -/* 11092 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11143 -/* 11096 */ MCD_OPC_Decode, 249, 17, 130, 2, // Opcode: VFDDB -/* 11101 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11115 -/* 11106 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11143 -/* 11110 */ MCD_OPC_Decode, 151, 21, 166, 2, // Opcode: WFDSB -/* 11115 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11129 -/* 11120 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11143 -/* 11124 */ MCD_OPC_Decode, 150, 21, 167, 2, // Opcode: WFDDB -/* 11129 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11143 -/* 11134 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11143 -/* 11138 */ MCD_OPC_Decode, 152, 21, 130, 2, // Opcode: WFDXB -/* 11143 */ MCD_OPC_CheckPredicate, 22, 8, 31, // Skip to: 19091 -/* 11147 */ MCD_OPC_Decode, 248, 17, 168, 2, // Opcode: VFD -/* 11152 */ MCD_OPC_FilterValue, 231, 1, 94, 0, // Skip to: 11251 -/* 11157 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11160 */ MCD_OPC_FilterValue, 0, 247, 30, // Skip to: 19091 -/* 11164 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... -/* 11167 */ MCD_OPC_FilterValue, 0, 240, 30, // Skip to: 19091 -/* 11171 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 11174 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11187 -/* 11178 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11242 -/* 11182 */ MCD_OPC_Decode, 186, 18, 130, 2, // Opcode: VFMSB -/* 11187 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11200 -/* 11191 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11242 -/* 11195 */ MCD_OPC_Decode, 181, 18, 130, 2, // Opcode: VFMDB -/* 11200 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11214 -/* 11205 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11242 -/* 11209 */ MCD_OPC_Decode, 201, 21, 166, 2, // Opcode: WFMSB -/* 11214 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11228 -/* 11219 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11242 -/* 11223 */ MCD_OPC_Decode, 197, 21, 167, 2, // Opcode: WFMDB -/* 11228 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11242 -/* 11233 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11242 -/* 11237 */ MCD_OPC_Decode, 205, 21, 130, 2, // Opcode: WFMXB -/* 11242 */ MCD_OPC_CheckPredicate, 22, 165, 30, // Skip to: 19091 -/* 11246 */ MCD_OPC_Decode, 174, 18, 168, 2, // Opcode: VFM -/* 11251 */ MCD_OPC_FilterValue, 232, 1, 46, 1, // Skip to: 11558 -/* 11256 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11259 */ MCD_OPC_FilterValue, 0, 148, 30, // Skip to: 19091 -/* 11263 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 11266 */ MCD_OPC_FilterValue, 0, 141, 30, // Skip to: 19091 -/* 11270 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 11273 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11286 -/* 11277 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 11549 -/* 11281 */ MCD_OPC_Decode, 236, 17, 130, 2, // Opcode: VFCESB -/* 11286 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11299 -/* 11290 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 11549 -/* 11294 */ MCD_OPC_Decode, 234, 17, 130, 2, // Opcode: VFCEDB -/* 11299 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11312 -/* 11303 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 11549 -/* 11307 */ MCD_OPC_Decode, 154, 18, 130, 2, // Opcode: VFKESB -/* 11312 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11325 -/* 11316 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 11549 -/* 11320 */ MCD_OPC_Decode, 152, 18, 130, 2, // Opcode: VFKEDB -/* 11325 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11339 -/* 11330 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 11549 -/* 11334 */ MCD_OPC_Decode, 132, 21, 166, 2, // Opcode: WFCESB -/* 11339 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11353 -/* 11344 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 11549 -/* 11348 */ MCD_OPC_Decode, 130, 21, 167, 2, // Opcode: WFCEDB -/* 11353 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11367 -/* 11358 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 11549 -/* 11362 */ MCD_OPC_Decode, 134, 21, 130, 2, // Opcode: WFCEXB -/* 11367 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11381 -/* 11372 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 11549 -/* 11376 */ MCD_OPC_Decode, 160, 21, 166, 2, // Opcode: WFKESB -/* 11381 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 11395 -/* 11386 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 11549 -/* 11390 */ MCD_OPC_Decode, 158, 21, 167, 2, // Opcode: WFKEDB -/* 11395 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 11409 -/* 11400 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 11549 -/* 11404 */ MCD_OPC_Decode, 162, 21, 130, 2, // Opcode: WFKEXB -/* 11409 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 11423 -/* 11414 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 11549 -/* 11418 */ MCD_OPC_Decode, 237, 17, 130, 2, // Opcode: VFCESBS -/* 11423 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 11437 -/* 11428 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 11549 -/* 11432 */ MCD_OPC_Decode, 235, 17, 130, 2, // Opcode: VFCEDBS -/* 11437 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 11451 -/* 11442 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 11549 -/* 11446 */ MCD_OPC_Decode, 155, 18, 130, 2, // Opcode: VFKESBS -/* 11451 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 11465 -/* 11456 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 11549 -/* 11460 */ MCD_OPC_Decode, 153, 18, 130, 2, // Opcode: VFKEDBS -/* 11465 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 11479 -/* 11470 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 11549 -/* 11474 */ MCD_OPC_Decode, 133, 21, 166, 2, // Opcode: WFCESBS -/* 11479 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 11493 -/* 11484 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 11549 -/* 11488 */ MCD_OPC_Decode, 131, 21, 167, 2, // Opcode: WFCEDBS -/* 11493 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 11507 -/* 11498 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 11549 -/* 11502 */ MCD_OPC_Decode, 135, 21, 130, 2, // Opcode: WFCEXBS -/* 11507 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 11521 -/* 11512 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11549 -/* 11516 */ MCD_OPC_Decode, 161, 21, 166, 2, // Opcode: WFKESBS -/* 11521 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 11535 -/* 11526 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 11549 -/* 11530 */ MCD_OPC_Decode, 159, 21, 167, 2, // Opcode: WFKEDBS -/* 11535 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 11549 -/* 11540 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11549 -/* 11544 */ MCD_OPC_Decode, 163, 21, 130, 2, // Opcode: WFKEXBS -/* 11549 */ MCD_OPC_CheckPredicate, 22, 114, 29, // Skip to: 19091 -/* 11553 */ MCD_OPC_Decode, 233, 17, 169, 2, // Opcode: VFCE -/* 11558 */ MCD_OPC_FilterValue, 234, 1, 46, 1, // Skip to: 11865 -/* 11563 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11566 */ MCD_OPC_FilterValue, 0, 97, 29, // Skip to: 19091 -/* 11570 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 11573 */ MCD_OPC_FilterValue, 0, 90, 29, // Skip to: 19091 -/* 11577 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 11580 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11593 -/* 11584 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 11856 -/* 11588 */ MCD_OPC_Decode, 244, 17, 130, 2, // Opcode: VFCHESB -/* 11593 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11606 -/* 11597 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 11856 -/* 11601 */ MCD_OPC_Decode, 242, 17, 130, 2, // Opcode: VFCHEDB -/* 11606 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11619 -/* 11610 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 11856 -/* 11614 */ MCD_OPC_Decode, 160, 18, 130, 2, // Opcode: VFKHESB -/* 11619 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11632 -/* 11623 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 11856 -/* 11627 */ MCD_OPC_Decode, 158, 18, 130, 2, // Opcode: VFKHEDB -/* 11632 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11646 -/* 11637 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 11856 -/* 11641 */ MCD_OPC_Decode, 140, 21, 166, 2, // Opcode: WFCHESB -/* 11646 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11660 -/* 11651 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 11856 -/* 11655 */ MCD_OPC_Decode, 138, 21, 167, 2, // Opcode: WFCHEDB -/* 11660 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11674 -/* 11665 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 11856 -/* 11669 */ MCD_OPC_Decode, 142, 21, 130, 2, // Opcode: WFCHEXB -/* 11674 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11688 -/* 11679 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 11856 -/* 11683 */ MCD_OPC_Decode, 168, 21, 166, 2, // Opcode: WFKHESB -/* 11688 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 11702 -/* 11693 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 11856 -/* 11697 */ MCD_OPC_Decode, 166, 21, 167, 2, // Opcode: WFKHEDB -/* 11702 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 11716 -/* 11707 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 11856 -/* 11711 */ MCD_OPC_Decode, 170, 21, 130, 2, // Opcode: WFKHEXB -/* 11716 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 11730 -/* 11721 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 11856 -/* 11725 */ MCD_OPC_Decode, 245, 17, 130, 2, // Opcode: VFCHESBS -/* 11730 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 11744 -/* 11735 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 11856 -/* 11739 */ MCD_OPC_Decode, 243, 17, 130, 2, // Opcode: VFCHEDBS -/* 11744 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 11758 -/* 11749 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 11856 -/* 11753 */ MCD_OPC_Decode, 161, 18, 130, 2, // Opcode: VFKHESBS -/* 11758 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 11772 -/* 11763 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 11856 -/* 11767 */ MCD_OPC_Decode, 159, 18, 130, 2, // Opcode: VFKHEDBS -/* 11772 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 11786 -/* 11777 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 11856 -/* 11781 */ MCD_OPC_Decode, 141, 21, 166, 2, // Opcode: WFCHESBS -/* 11786 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 11800 -/* 11791 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 11856 -/* 11795 */ MCD_OPC_Decode, 139, 21, 167, 2, // Opcode: WFCHEDBS -/* 11800 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 11814 -/* 11805 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 11856 -/* 11809 */ MCD_OPC_Decode, 143, 21, 130, 2, // Opcode: WFCHEXBS -/* 11814 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 11828 -/* 11819 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11856 -/* 11823 */ MCD_OPC_Decode, 169, 21, 166, 2, // Opcode: WFKHESBS -/* 11828 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 11842 -/* 11833 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 11856 -/* 11837 */ MCD_OPC_Decode, 167, 21, 167, 2, // Opcode: WFKHEDBS -/* 11842 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 11856 -/* 11847 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11856 -/* 11851 */ MCD_OPC_Decode, 171, 21, 130, 2, // Opcode: WFKHEXBS -/* 11856 */ MCD_OPC_CheckPredicate, 22, 63, 28, // Skip to: 19091 -/* 11860 */ MCD_OPC_Decode, 241, 17, 169, 2, // Opcode: VFCHE -/* 11865 */ MCD_OPC_FilterValue, 235, 1, 46, 1, // Skip to: 12172 -/* 11870 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 11873 */ MCD_OPC_FilterValue, 0, 46, 28, // Skip to: 19091 -/* 11877 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 11880 */ MCD_OPC_FilterValue, 0, 39, 28, // Skip to: 19091 -/* 11884 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... -/* 11887 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11900 -/* 11891 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 12163 -/* 11895 */ MCD_OPC_Decode, 246, 17, 130, 2, // Opcode: VFCHSB -/* 11900 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11913 -/* 11904 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 12163 -/* 11908 */ MCD_OPC_Decode, 239, 17, 130, 2, // Opcode: VFCHDB -/* 11913 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11926 -/* 11917 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 12163 -/* 11921 */ MCD_OPC_Decode, 162, 18, 130, 2, // Opcode: VFKHSB -/* 11926 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11939 -/* 11930 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 12163 -/* 11934 */ MCD_OPC_Decode, 156, 18, 130, 2, // Opcode: VFKHDB -/* 11939 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11953 -/* 11944 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 12163 -/* 11948 */ MCD_OPC_Decode, 144, 21, 166, 2, // Opcode: WFCHSB -/* 11953 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11967 -/* 11958 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 12163 -/* 11962 */ MCD_OPC_Decode, 136, 21, 167, 2, // Opcode: WFCHDB -/* 11967 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11981 -/* 11972 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 12163 -/* 11976 */ MCD_OPC_Decode, 146, 21, 130, 2, // Opcode: WFCHXB -/* 11981 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11995 -/* 11986 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 12163 -/* 11990 */ MCD_OPC_Decode, 172, 21, 166, 2, // Opcode: WFKHSB -/* 11995 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 12009 -/* 12000 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 12163 -/* 12004 */ MCD_OPC_Decode, 164, 21, 167, 2, // Opcode: WFKHDB -/* 12009 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 12023 -/* 12014 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 12163 -/* 12018 */ MCD_OPC_Decode, 174, 21, 130, 2, // Opcode: WFKHXB -/* 12023 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 12037 -/* 12028 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 12163 -/* 12032 */ MCD_OPC_Decode, 247, 17, 130, 2, // Opcode: VFCHSBS -/* 12037 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 12051 -/* 12042 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 12163 -/* 12046 */ MCD_OPC_Decode, 240, 17, 130, 2, // Opcode: VFCHDBS -/* 12051 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 12065 -/* 12056 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 12163 -/* 12060 */ MCD_OPC_Decode, 163, 18, 130, 2, // Opcode: VFKHSBS -/* 12065 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 12079 -/* 12070 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 12163 -/* 12074 */ MCD_OPC_Decode, 157, 18, 130, 2, // Opcode: VFKHDBS -/* 12079 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 12093 -/* 12084 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 12163 -/* 12088 */ MCD_OPC_Decode, 145, 21, 166, 2, // Opcode: WFCHSBS -/* 12093 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 12107 -/* 12098 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 12163 -/* 12102 */ MCD_OPC_Decode, 137, 21, 167, 2, // Opcode: WFCHDBS -/* 12107 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 12121 -/* 12112 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12163 -/* 12116 */ MCD_OPC_Decode, 147, 21, 130, 2, // Opcode: WFCHXBS -/* 12121 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 12135 -/* 12126 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12163 -/* 12130 */ MCD_OPC_Decode, 173, 21, 166, 2, // Opcode: WFKHSBS -/* 12135 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 12149 -/* 12140 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12163 -/* 12144 */ MCD_OPC_Decode, 165, 21, 167, 2, // Opcode: WFKHDBS -/* 12149 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 12163 -/* 12154 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12163 -/* 12158 */ MCD_OPC_Decode, 175, 21, 130, 2, // Opcode: WFKHXBS -/* 12163 */ MCD_OPC_CheckPredicate, 22, 12, 27, // Skip to: 19091 -/* 12167 */ MCD_OPC_Decode, 238, 17, 169, 2, // Opcode: VFCH -/* 12172 */ MCD_OPC_FilterValue, 238, 1, 94, 0, // Skip to: 12271 -/* 12177 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12180 */ MCD_OPC_FilterValue, 0, 251, 26, // Skip to: 19091 -/* 12184 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 12187 */ MCD_OPC_FilterValue, 0, 244, 26, // Skip to: 19091 -/* 12191 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 12194 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12207 -/* 12198 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 12262 -/* 12202 */ MCD_OPC_Decode, 184, 18, 136, 2, // Opcode: VFMINSB -/* 12207 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12220 -/* 12211 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12262 -/* 12215 */ MCD_OPC_Decode, 183, 18, 136, 2, // Opcode: VFMINDB -/* 12220 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 12234 -/* 12225 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12262 -/* 12229 */ MCD_OPC_Decode, 199, 21, 170, 2, // Opcode: WFMINSB -/* 12234 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 12248 -/* 12239 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12262 -/* 12243 */ MCD_OPC_Decode, 198, 21, 171, 2, // Opcode: WFMINDB -/* 12248 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 12262 -/* 12253 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12262 -/* 12257 */ MCD_OPC_Decode, 200, 21, 136, 2, // Opcode: WFMINXB -/* 12262 */ MCD_OPC_CheckPredicate, 23, 169, 26, // Skip to: 19091 -/* 12266 */ MCD_OPC_Decode, 182, 18, 169, 2, // Opcode: VFMIN -/* 12271 */ MCD_OPC_FilterValue, 239, 1, 94, 0, // Skip to: 12370 -/* 12276 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12279 */ MCD_OPC_FilterValue, 0, 152, 26, // Skip to: 19091 -/* 12283 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 12286 */ MCD_OPC_FilterValue, 0, 145, 26, // Skip to: 19091 -/* 12290 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... -/* 12293 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12306 -/* 12297 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 12361 -/* 12301 */ MCD_OPC_Decode, 180, 18, 136, 2, // Opcode: VFMAXSB -/* 12306 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12319 -/* 12310 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12361 -/* 12314 */ MCD_OPC_Decode, 179, 18, 136, 2, // Opcode: VFMAXDB -/* 12319 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 12333 -/* 12324 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12361 -/* 12328 */ MCD_OPC_Decode, 195, 21, 170, 2, // Opcode: WFMAXSB -/* 12333 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 12347 -/* 12338 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12361 -/* 12342 */ MCD_OPC_Decode, 194, 21, 171, 2, // Opcode: WFMAXDB -/* 12347 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 12361 -/* 12352 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12361 -/* 12356 */ MCD_OPC_Decode, 196, 21, 136, 2, // Opcode: WFMAXXB -/* 12361 */ MCD_OPC_CheckPredicate, 23, 70, 26, // Skip to: 19091 -/* 12365 */ MCD_OPC_Decode, 178, 18, 169, 2, // Opcode: VFMAX -/* 12370 */ MCD_OPC_FilterValue, 240, 1, 78, 0, // Skip to: 12453 -/* 12375 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12378 */ MCD_OPC_FilterValue, 0, 53, 26, // Skip to: 19091 -/* 12382 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12385 */ MCD_OPC_FilterValue, 0, 46, 26, // Skip to: 19091 -/* 12389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12392 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12405 -/* 12396 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12444 -/* 12400 */ MCD_OPC_Decode, 233, 16, 130, 2, // Opcode: VAVGLB -/* 12405 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12418 -/* 12409 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12444 -/* 12413 */ MCD_OPC_Decode, 236, 16, 130, 2, // Opcode: VAVGLH -/* 12418 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12431 -/* 12422 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12444 -/* 12426 */ MCD_OPC_Decode, 234, 16, 130, 2, // Opcode: VAVGLF -/* 12431 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12444 -/* 12435 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12444 -/* 12439 */ MCD_OPC_Decode, 235, 16, 130, 2, // Opcode: VAVGLG -/* 12444 */ MCD_OPC_CheckPredicate, 22, 243, 25, // Skip to: 19091 -/* 12448 */ MCD_OPC_Decode, 232, 16, 131, 2, // Opcode: VAVGL -/* 12453 */ MCD_OPC_FilterValue, 241, 1, 91, 0, // Skip to: 12549 -/* 12458 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12461 */ MCD_OPC_FilterValue, 0, 226, 25, // Skip to: 19091 -/* 12465 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12468 */ MCD_OPC_FilterValue, 0, 219, 25, // Skip to: 19091 -/* 12472 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12475 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12488 -/* 12479 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12540 -/* 12483 */ MCD_OPC_Decode, 214, 16, 130, 2, // Opcode: VACCB -/* 12488 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12501 -/* 12492 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12540 -/* 12496 */ MCD_OPC_Decode, 219, 16, 130, 2, // Opcode: VACCH -/* 12501 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12514 -/* 12505 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12540 -/* 12509 */ MCD_OPC_Decode, 217, 16, 130, 2, // Opcode: VACCF -/* 12514 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12527 -/* 12518 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12540 -/* 12522 */ MCD_OPC_Decode, 218, 16, 130, 2, // Opcode: VACCG -/* 12527 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12540 -/* 12531 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12540 -/* 12535 */ MCD_OPC_Decode, 220, 16, 130, 2, // Opcode: VACCQ -/* 12540 */ MCD_OPC_CheckPredicate, 22, 147, 25, // Skip to: 19091 -/* 12544 */ MCD_OPC_Decode, 213, 16, 131, 2, // Opcode: VACC -/* 12549 */ MCD_OPC_FilterValue, 242, 1, 78, 0, // Skip to: 12632 -/* 12554 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12557 */ MCD_OPC_FilterValue, 0, 130, 25, // Skip to: 19091 -/* 12561 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12564 */ MCD_OPC_FilterValue, 0, 123, 25, // Skip to: 19091 -/* 12568 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12571 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12584 -/* 12575 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12623 -/* 12579 */ MCD_OPC_Decode, 228, 16, 130, 2, // Opcode: VAVGB -/* 12584 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12597 -/* 12588 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12623 -/* 12592 */ MCD_OPC_Decode, 231, 16, 130, 2, // Opcode: VAVGH -/* 12597 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12610 -/* 12601 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12623 -/* 12605 */ MCD_OPC_Decode, 229, 16, 130, 2, // Opcode: VAVGF -/* 12610 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12623 -/* 12614 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12623 -/* 12618 */ MCD_OPC_Decode, 230, 16, 130, 2, // Opcode: VAVGG -/* 12623 */ MCD_OPC_CheckPredicate, 22, 64, 25, // Skip to: 19091 -/* 12627 */ MCD_OPC_Decode, 227, 16, 131, 2, // Opcode: VAVG -/* 12632 */ MCD_OPC_FilterValue, 243, 1, 91, 0, // Skip to: 12728 -/* 12637 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12640 */ MCD_OPC_FilterValue, 0, 47, 25, // Skip to: 19091 -/* 12644 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12647 */ MCD_OPC_FilterValue, 0, 40, 25, // Skip to: 19091 -/* 12651 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12654 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12667 -/* 12658 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12719 -/* 12662 */ MCD_OPC_Decode, 211, 16, 130, 2, // Opcode: VAB -/* 12667 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12680 -/* 12671 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12719 -/* 12675 */ MCD_OPC_Decode, 224, 16, 130, 2, // Opcode: VAH -/* 12680 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12693 -/* 12684 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12719 -/* 12688 */ MCD_OPC_Decode, 222, 16, 130, 2, // Opcode: VAF -/* 12693 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12706 -/* 12697 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12719 -/* 12701 */ MCD_OPC_Decode, 223, 16, 130, 2, // Opcode: VAG -/* 12706 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12719 -/* 12710 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12719 -/* 12714 */ MCD_OPC_Decode, 226, 16, 130, 2, // Opcode: VAQ -/* 12719 */ MCD_OPC_CheckPredicate, 22, 224, 24, // Skip to: 19091 -/* 12723 */ MCD_OPC_Decode, 210, 16, 131, 2, // Opcode: VA -/* 12728 */ MCD_OPC_FilterValue, 245, 1, 91, 0, // Skip to: 12824 -/* 12733 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12736 */ MCD_OPC_FilterValue, 0, 207, 24, // Skip to: 19091 -/* 12740 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12743 */ MCD_OPC_FilterValue, 0, 200, 24, // Skip to: 19091 -/* 12747 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12750 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12763 -/* 12754 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12815 -/* 12758 */ MCD_OPC_Decode, 171, 20, 130, 2, // Opcode: VSCBIB -/* 12763 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12776 -/* 12767 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12815 -/* 12771 */ MCD_OPC_Decode, 174, 20, 130, 2, // Opcode: VSCBIH -/* 12776 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12789 -/* 12780 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12815 -/* 12784 */ MCD_OPC_Decode, 172, 20, 130, 2, // Opcode: VSCBIF -/* 12789 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12802 -/* 12793 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12815 -/* 12797 */ MCD_OPC_Decode, 173, 20, 130, 2, // Opcode: VSCBIG -/* 12802 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12815 -/* 12806 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12815 -/* 12810 */ MCD_OPC_Decode, 175, 20, 130, 2, // Opcode: VSCBIQ -/* 12815 */ MCD_OPC_CheckPredicate, 22, 128, 24, // Skip to: 19091 -/* 12819 */ MCD_OPC_Decode, 170, 20, 131, 2, // Opcode: VSCBI -/* 12824 */ MCD_OPC_FilterValue, 247, 1, 91, 0, // Skip to: 12920 -/* 12829 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12832 */ MCD_OPC_FilterValue, 0, 111, 24, // Skip to: 19091 -/* 12836 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 12839 */ MCD_OPC_FilterValue, 0, 104, 24, // Skip to: 19091 -/* 12843 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12846 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12859 -/* 12850 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12911 -/* 12854 */ MCD_OPC_Decode, 165, 20, 130, 2, // Opcode: VSB -/* 12859 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12872 -/* 12863 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12911 -/* 12867 */ MCD_OPC_Decode, 186, 20, 130, 2, // Opcode: VSH -/* 12872 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12885 -/* 12876 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12911 -/* 12880 */ MCD_OPC_Decode, 184, 20, 130, 2, // Opcode: VSF -/* 12885 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12898 -/* 12889 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12911 -/* 12893 */ MCD_OPC_Decode, 185, 20, 130, 2, // Opcode: VSG -/* 12898 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12911 -/* 12902 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12911 -/* 12906 */ MCD_OPC_Decode, 191, 20, 130, 2, // Opcode: VSQ -/* 12911 */ MCD_OPC_CheckPredicate, 22, 32, 24, // Skip to: 19091 -/* 12915 */ MCD_OPC_Decode, 164, 20, 131, 2, // Opcode: VS -/* 12920 */ MCD_OPC_FilterValue, 248, 1, 165, 0, // Skip to: 13090 -/* 12925 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 12928 */ MCD_OPC_FilterValue, 0, 15, 24, // Skip to: 19091 -/* 12932 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 12935 */ MCD_OPC_FilterValue, 0, 8, 24, // Skip to: 19091 -/* 12939 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 12942 */ MCD_OPC_FilterValue, 0, 1, 24, // Skip to: 19091 -/* 12946 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 12949 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12982 -/* 12953 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 12956 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12969 -/* 12960 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13081 -/* 12964 */ MCD_OPC_Decode, 243, 16, 130, 2, // Opcode: VCEQB -/* 12969 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13081 -/* 12973 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13081 -/* 12977 */ MCD_OPC_Decode, 244, 16, 130, 2, // Opcode: VCEQBS -/* 12982 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13015 -/* 12986 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 12989 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13002 -/* 12993 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13081 -/* 12997 */ MCD_OPC_Decode, 249, 16, 130, 2, // Opcode: VCEQH -/* 13002 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13081 -/* 13006 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13081 -/* 13010 */ MCD_OPC_Decode, 250, 16, 130, 2, // Opcode: VCEQHS -/* 13015 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13048 -/* 13019 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13022 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13035 -/* 13026 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13081 -/* 13030 */ MCD_OPC_Decode, 245, 16, 130, 2, // Opcode: VCEQF -/* 13035 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13081 -/* 13039 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13081 -/* 13043 */ MCD_OPC_Decode, 246, 16, 130, 2, // Opcode: VCEQFS -/* 13048 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13081 -/* 13052 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13055 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13068 -/* 13059 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13081 -/* 13063 */ MCD_OPC_Decode, 247, 16, 130, 2, // Opcode: VCEQG -/* 13068 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13081 -/* 13072 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13081 -/* 13076 */ MCD_OPC_Decode, 248, 16, 130, 2, // Opcode: VCEQGS -/* 13081 */ MCD_OPC_CheckPredicate, 22, 118, 23, // Skip to: 19091 -/* 13085 */ MCD_OPC_Decode, 242, 16, 137, 2, // Opcode: VCEQ -/* 13090 */ MCD_OPC_FilterValue, 249, 1, 165, 0, // Skip to: 13260 -/* 13095 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13098 */ MCD_OPC_FilterValue, 0, 101, 23, // Skip to: 19091 -/* 13102 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 13105 */ MCD_OPC_FilterValue, 0, 94, 23, // Skip to: 19091 -/* 13109 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 13112 */ MCD_OPC_FilterValue, 0, 87, 23, // Skip to: 19091 -/* 13116 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13119 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 13152 -/* 13123 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13126 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13139 -/* 13130 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13251 -/* 13134 */ MCD_OPC_Decode, 135, 17, 130, 2, // Opcode: VCHLB -/* 13139 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13251 -/* 13143 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13251 -/* 13147 */ MCD_OPC_Decode, 136, 17, 130, 2, // Opcode: VCHLBS -/* 13152 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13185 -/* 13156 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13159 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13172 -/* 13163 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13251 -/* 13167 */ MCD_OPC_Decode, 141, 17, 130, 2, // Opcode: VCHLH -/* 13172 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13251 -/* 13176 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13251 -/* 13180 */ MCD_OPC_Decode, 142, 17, 130, 2, // Opcode: VCHLHS -/* 13185 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13218 -/* 13189 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13192 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13205 -/* 13196 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13251 -/* 13200 */ MCD_OPC_Decode, 137, 17, 130, 2, // Opcode: VCHLF -/* 13205 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13251 -/* 13209 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13251 -/* 13213 */ MCD_OPC_Decode, 138, 17, 130, 2, // Opcode: VCHLFS -/* 13218 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13251 -/* 13222 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13225 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13238 -/* 13229 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13251 -/* 13233 */ MCD_OPC_Decode, 139, 17, 130, 2, // Opcode: VCHLG -/* 13238 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13251 -/* 13242 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13251 -/* 13246 */ MCD_OPC_Decode, 140, 17, 130, 2, // Opcode: VCHLGS -/* 13251 */ MCD_OPC_CheckPredicate, 22, 204, 22, // Skip to: 19091 -/* 13255 */ MCD_OPC_Decode, 134, 17, 137, 2, // Opcode: VCHL -/* 13260 */ MCD_OPC_FilterValue, 251, 1, 165, 0, // Skip to: 13430 -/* 13265 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13268 */ MCD_OPC_FilterValue, 0, 187, 22, // Skip to: 19091 -/* 13272 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... -/* 13275 */ MCD_OPC_FilterValue, 0, 180, 22, // Skip to: 19091 -/* 13279 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... -/* 13282 */ MCD_OPC_FilterValue, 0, 173, 22, // Skip to: 19091 -/* 13286 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13289 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 13322 -/* 13293 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13296 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13309 -/* 13300 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13421 -/* 13304 */ MCD_OPC_Decode, 254, 16, 130, 2, // Opcode: VCHB -/* 13309 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13421 -/* 13313 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13421 -/* 13317 */ MCD_OPC_Decode, 255, 16, 130, 2, // Opcode: VCHBS -/* 13322 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13355 -/* 13326 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13329 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13342 -/* 13333 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13421 -/* 13337 */ MCD_OPC_Decode, 132, 17, 130, 2, // Opcode: VCHH -/* 13342 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13421 -/* 13346 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13421 -/* 13350 */ MCD_OPC_Decode, 133, 17, 130, 2, // Opcode: VCHHS -/* 13355 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13388 -/* 13359 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13362 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13375 -/* 13366 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13421 -/* 13370 */ MCD_OPC_Decode, 128, 17, 130, 2, // Opcode: VCHF -/* 13375 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13421 -/* 13379 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13421 -/* 13383 */ MCD_OPC_Decode, 129, 17, 130, 2, // Opcode: VCHFS -/* 13388 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13421 -/* 13392 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... -/* 13395 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13408 -/* 13399 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13421 -/* 13403 */ MCD_OPC_Decode, 130, 17, 130, 2, // Opcode: VCHG -/* 13408 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13421 -/* 13412 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13421 -/* 13416 */ MCD_OPC_Decode, 131, 17, 130, 2, // Opcode: VCHGS -/* 13421 */ MCD_OPC_CheckPredicate, 22, 34, 22, // Skip to: 19091 -/* 13425 */ MCD_OPC_Decode, 253, 16, 137, 2, // Opcode: VCH -/* 13430 */ MCD_OPC_FilterValue, 252, 1, 78, 0, // Skip to: 13513 -/* 13435 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13438 */ MCD_OPC_FilterValue, 0, 17, 22, // Skip to: 19091 -/* 13442 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 13445 */ MCD_OPC_FilterValue, 0, 10, 22, // Skip to: 19091 -/* 13449 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13452 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13465 -/* 13456 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13504 -/* 13460 */ MCD_OPC_Decode, 214, 19, 130, 2, // Opcode: VMNLB -/* 13465 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13478 -/* 13469 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13504 -/* 13473 */ MCD_OPC_Decode, 217, 19, 130, 2, // Opcode: VMNLH -/* 13478 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13491 -/* 13482 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13504 -/* 13486 */ MCD_OPC_Decode, 215, 19, 130, 2, // Opcode: VMNLF -/* 13491 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13504 -/* 13495 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13504 -/* 13499 */ MCD_OPC_Decode, 216, 19, 130, 2, // Opcode: VMNLG -/* 13504 */ MCD_OPC_CheckPredicate, 22, 207, 21, // Skip to: 19091 -/* 13508 */ MCD_OPC_Decode, 213, 19, 131, 2, // Opcode: VMNL -/* 13513 */ MCD_OPC_FilterValue, 253, 1, 78, 0, // Skip to: 13596 -/* 13518 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13521 */ MCD_OPC_FilterValue, 0, 190, 21, // Skip to: 19091 -/* 13525 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 13528 */ MCD_OPC_FilterValue, 0, 183, 21, // Skip to: 19091 -/* 13532 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13548 -/* 13539 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13587 -/* 13543 */ MCD_OPC_Decode, 242, 19, 130, 2, // Opcode: VMXLB -/* 13548 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13561 -/* 13552 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13587 -/* 13556 */ MCD_OPC_Decode, 245, 19, 130, 2, // Opcode: VMXLH -/* 13561 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13574 -/* 13565 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13587 -/* 13569 */ MCD_OPC_Decode, 243, 19, 130, 2, // Opcode: VMXLF -/* 13574 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13587 -/* 13578 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13587 -/* 13582 */ MCD_OPC_Decode, 244, 19, 130, 2, // Opcode: VMXLG -/* 13587 */ MCD_OPC_CheckPredicate, 22, 124, 21, // Skip to: 19091 -/* 13591 */ MCD_OPC_Decode, 241, 19, 131, 2, // Opcode: VMXL -/* 13596 */ MCD_OPC_FilterValue, 254, 1, 78, 0, // Skip to: 13679 -/* 13601 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13604 */ MCD_OPC_FilterValue, 0, 107, 21, // Skip to: 19091 -/* 13608 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 13611 */ MCD_OPC_FilterValue, 0, 100, 21, // Skip to: 19091 -/* 13615 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13618 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13631 -/* 13622 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13670 -/* 13626 */ MCD_OPC_Decode, 209, 19, 130, 2, // Opcode: VMNB -/* 13631 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13644 -/* 13635 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13670 -/* 13639 */ MCD_OPC_Decode, 212, 19, 130, 2, // Opcode: VMNH -/* 13644 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13657 -/* 13648 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13670 -/* 13652 */ MCD_OPC_Decode, 210, 19, 130, 2, // Opcode: VMNF -/* 13657 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13670 -/* 13661 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13670 -/* 13665 */ MCD_OPC_Decode, 211, 19, 130, 2, // Opcode: VMNG -/* 13670 */ MCD_OPC_CheckPredicate, 22, 41, 21, // Skip to: 19091 -/* 13674 */ MCD_OPC_Decode, 208, 19, 131, 2, // Opcode: VMN -/* 13679 */ MCD_OPC_FilterValue, 255, 1, 31, 21, // Skip to: 19091 -/* 13684 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... -/* 13687 */ MCD_OPC_FilterValue, 0, 24, 21, // Skip to: 19091 -/* 13691 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... -/* 13694 */ MCD_OPC_FilterValue, 0, 17, 21, // Skip to: 19091 -/* 13698 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 13701 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13714 -/* 13705 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13753 -/* 13709 */ MCD_OPC_Decode, 237, 19, 130, 2, // Opcode: VMXB -/* 13714 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13727 -/* 13718 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13753 -/* 13722 */ MCD_OPC_Decode, 240, 19, 130, 2, // Opcode: VMXH -/* 13727 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13740 -/* 13731 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13753 -/* 13735 */ MCD_OPC_Decode, 238, 19, 130, 2, // Opcode: VMXF -/* 13740 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13753 -/* 13744 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13753 -/* 13748 */ MCD_OPC_Decode, 239, 19, 130, 2, // Opcode: VMXG -/* 13753 */ MCD_OPC_CheckPredicate, 22, 214, 20, // Skip to: 19091 -/* 13757 */ MCD_OPC_Decode, 236, 19, 131, 2, // Opcode: VMX -/* 13762 */ MCD_OPC_FilterValue, 232, 1, 5, 0, // Skip to: 13772 -/* 13767 */ MCD_OPC_Decode, 193, 13, 189, 1, // Opcode: MVCIN -/* 13772 */ MCD_OPC_FilterValue, 233, 1, 5, 0, // Skip to: 13782 -/* 13777 */ MCD_OPC_Decode, 143, 14, 191, 1, // Opcode: PKA -/* 13782 */ MCD_OPC_FilterValue, 234, 1, 5, 0, // Skip to: 13792 -/* 13787 */ MCD_OPC_Decode, 207, 16, 189, 1, // Opcode: UNPKA -/* 13792 */ MCD_OPC_FilterValue, 235, 1, 198, 7, // Skip to: 15787 -/* 13797 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 13800 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 13809 -/* 13804 */ MCD_OPC_Decode, 227, 10, 172, 2, // Opcode: LMG -/* 13809 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 13818 -/* 13813 */ MCD_OPC_Decode, 132, 15, 173, 2, // Opcode: SRAG -/* 13818 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 13827 -/* 13822 */ MCD_OPC_Decode, 217, 14, 173, 2, // Opcode: SLAG -/* 13827 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 13836 -/* 13831 */ MCD_OPC_Decode, 139, 15, 173, 2, // Opcode: SRLG -/* 13836 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 13845 -/* 13840 */ MCD_OPC_Decode, 236, 14, 173, 2, // Opcode: SLLG -/* 13845 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 13854 -/* 13849 */ MCD_OPC_Decode, 186, 16, 172, 2, // Opcode: TRACG -/* 13854 */ MCD_OPC_FilterValue, 20, 5, 0, // Skip to: 13863 -/* 13858 */ MCD_OPC_Decode, 140, 8, 174, 2, // Opcode: CSY -/* 13863 */ MCD_OPC_FilterValue, 28, 5, 0, // Skip to: 13872 -/* 13867 */ MCD_OPC_Decode, 167, 14, 173, 2, // Opcode: RLLG -/* 13872 */ MCD_OPC_FilterValue, 29, 5, 0, // Skip to: 13881 -/* 13876 */ MCD_OPC_Decode, 166, 14, 175, 2, // Opcode: RLL -/* 13881 */ MCD_OPC_FilterValue, 32, 5, 0, // Skip to: 13890 -/* 13885 */ MCD_OPC_Decode, 143, 7, 176, 2, // Opcode: CLMH -/* 13890 */ MCD_OPC_FilterValue, 33, 5, 0, // Skip to: 13899 -/* 13894 */ MCD_OPC_Decode, 144, 7, 177, 2, // Opcode: CLMY -/* 13899 */ MCD_OPC_FilterValue, 35, 90, 0, // Skip to: 13993 -/* 13903 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 13906 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13919 -/* 13910 */ MCD_OPC_CheckPredicate, 24, 70, 0, // Skip to: 13984 -/* 13914 */ MCD_OPC_Decode, 193, 7, 178, 2, // Opcode: CLTAsmH -/* 13919 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 13932 -/* 13923 */ MCD_OPC_CheckPredicate, 24, 57, 0, // Skip to: 13984 -/* 13927 */ MCD_OPC_Decode, 195, 7, 178, 2, // Opcode: CLTAsmL -/* 13932 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 13945 -/* 13936 */ MCD_OPC_CheckPredicate, 24, 44, 0, // Skip to: 13984 -/* 13940 */ MCD_OPC_Decode, 197, 7, 178, 2, // Opcode: CLTAsmLH -/* 13945 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 13958 -/* 13949 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 13984 -/* 13953 */ MCD_OPC_Decode, 192, 7, 178, 2, // Opcode: CLTAsmE -/* 13958 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 13971 -/* 13962 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 13984 -/* 13966 */ MCD_OPC_Decode, 194, 7, 178, 2, // Opcode: CLTAsmHE -/* 13971 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 13984 -/* 13975 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 13984 -/* 13979 */ MCD_OPC_Decode, 196, 7, 178, 2, // Opcode: CLTAsmLE -/* 13984 */ MCD_OPC_CheckPredicate, 24, 239, 19, // Skip to: 19091 -/* 13988 */ MCD_OPC_Decode, 191, 7, 179, 2, // Opcode: CLTAsm -/* 13993 */ MCD_OPC_FilterValue, 36, 5, 0, // Skip to: 14002 -/* 13997 */ MCD_OPC_Decode, 189, 15, 172, 2, // Opcode: STMG -/* 14002 */ MCD_OPC_FilterValue, 37, 5, 0, // Skip to: 14011 -/* 14006 */ MCD_OPC_Decode, 169, 15, 180, 2, // Opcode: STCTG -/* 14011 */ MCD_OPC_FilterValue, 38, 5, 0, // Skip to: 14020 -/* 14015 */ MCD_OPC_Decode, 190, 15, 181, 2, // Opcode: STMH -/* 14020 */ MCD_OPC_FilterValue, 43, 90, 0, // Skip to: 14114 -/* 14024 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 14027 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14040 -/* 14031 */ MCD_OPC_CheckPredicate, 24, 70, 0, // Skip to: 14105 -/* 14035 */ MCD_OPC_Decode, 221, 6, 182, 2, // Opcode: CLGTAsmH -/* 14040 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14053 -/* 14044 */ MCD_OPC_CheckPredicate, 24, 57, 0, // Skip to: 14105 -/* 14048 */ MCD_OPC_Decode, 223, 6, 182, 2, // Opcode: CLGTAsmL -/* 14053 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14066 -/* 14057 */ MCD_OPC_CheckPredicate, 24, 44, 0, // Skip to: 14105 -/* 14061 */ MCD_OPC_Decode, 225, 6, 182, 2, // Opcode: CLGTAsmLH -/* 14066 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14079 -/* 14070 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 14105 -/* 14074 */ MCD_OPC_Decode, 220, 6, 182, 2, // Opcode: CLGTAsmE -/* 14079 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14092 -/* 14083 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 14105 -/* 14087 */ MCD_OPC_Decode, 222, 6, 182, 2, // Opcode: CLGTAsmHE -/* 14092 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14105 -/* 14096 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 14105 -/* 14100 */ MCD_OPC_Decode, 224, 6, 182, 2, // Opcode: CLGTAsmLE -/* 14105 */ MCD_OPC_CheckPredicate, 24, 118, 19, // Skip to: 19091 -/* 14109 */ MCD_OPC_Decode, 219, 6, 183, 2, // Opcode: CLGTAsm -/* 14114 */ MCD_OPC_FilterValue, 44, 5, 0, // Skip to: 14123 -/* 14118 */ MCD_OPC_Decode, 165, 15, 176, 2, // Opcode: STCMH -/* 14123 */ MCD_OPC_FilterValue, 45, 5, 0, // Skip to: 14132 -/* 14127 */ MCD_OPC_Decode, 166, 15, 177, 2, // Opcode: STCMY -/* 14132 */ MCD_OPC_FilterValue, 47, 5, 0, // Skip to: 14141 -/* 14136 */ MCD_OPC_Decode, 143, 10, 180, 2, // Opcode: LCTLG -/* 14141 */ MCD_OPC_FilterValue, 48, 5, 0, // Skip to: 14150 -/* 14145 */ MCD_OPC_Decode, 135, 8, 184, 2, // Opcode: CSG -/* 14150 */ MCD_OPC_FilterValue, 49, 5, 0, // Skip to: 14159 -/* 14154 */ MCD_OPC_Decode, 160, 4, 185, 2, // Opcode: CDSY -/* 14159 */ MCD_OPC_FilterValue, 62, 5, 0, // Skip to: 14168 -/* 14163 */ MCD_OPC_Decode, 158, 4, 185, 2, // Opcode: CDSG -/* 14168 */ MCD_OPC_FilterValue, 68, 5, 0, // Skip to: 14177 -/* 14172 */ MCD_OPC_Decode, 135, 4, 184, 2, // Opcode: BXHG -/* 14177 */ MCD_OPC_FilterValue, 69, 5, 0, // Skip to: 14186 -/* 14181 */ MCD_OPC_Decode, 137, 4, 184, 2, // Opcode: BXLEG -/* 14186 */ MCD_OPC_FilterValue, 76, 5, 0, // Skip to: 14195 -/* 14190 */ MCD_OPC_Decode, 216, 8, 173, 2, // Opcode: ECAG -/* 14195 */ MCD_OPC_FilterValue, 81, 5, 0, // Skip to: 14204 -/* 14199 */ MCD_OPC_Decode, 180, 16, 186, 2, // Opcode: TMY -/* 14204 */ MCD_OPC_FilterValue, 82, 5, 0, // Skip to: 14213 -/* 14208 */ MCD_OPC_Decode, 206, 13, 186, 2, // Opcode: MVIY -/* 14213 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 14222 -/* 14217 */ MCD_OPC_Decode, 239, 13, 186, 2, // Opcode: NIY -/* 14222 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 14231 -/* 14226 */ MCD_OPC_Decode, 141, 7, 186, 2, // Opcode: CLIY -/* 14231 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 14240 -/* 14235 */ MCD_OPC_Decode, 128, 14, 186, 2, // Opcode: OIY -/* 14240 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 14249 -/* 14244 */ MCD_OPC_Decode, 234, 21, 186, 2, // Opcode: XIY -/* 14249 */ MCD_OPC_FilterValue, 106, 5, 0, // Skip to: 14258 -/* 14253 */ MCD_OPC_Decode, 155, 3, 187, 2, // Opcode: ASI -/* 14258 */ MCD_OPC_FilterValue, 110, 5, 0, // Skip to: 14267 -/* 14262 */ MCD_OPC_Decode, 148, 3, 187, 2, // Opcode: ALSI -/* 14267 */ MCD_OPC_FilterValue, 122, 5, 0, // Skip to: 14276 -/* 14271 */ MCD_OPC_Decode, 249, 2, 187, 2, // Opcode: AGSI -/* 14276 */ MCD_OPC_FilterValue, 126, 5, 0, // Skip to: 14285 -/* 14280 */ MCD_OPC_Decode, 142, 3, 187, 2, // Opcode: ALGSI -/* 14285 */ MCD_OPC_FilterValue, 128, 1, 5, 0, // Skip to: 14295 -/* 14290 */ MCD_OPC_Decode, 132, 9, 188, 2, // Opcode: ICMH -/* 14295 */ MCD_OPC_FilterValue, 129, 1, 5, 0, // Skip to: 14305 -/* 14300 */ MCD_OPC_Decode, 133, 9, 189, 2, // Opcode: ICMY -/* 14305 */ MCD_OPC_FilterValue, 142, 1, 5, 0, // Skip to: 14315 -/* 14310 */ MCD_OPC_Decode, 197, 13, 190, 2, // Opcode: MVCLU -/* 14315 */ MCD_OPC_FilterValue, 143, 1, 5, 0, // Skip to: 14325 -/* 14320 */ MCD_OPC_Decode, 228, 5, 190, 2, // Opcode: CLCLU -/* 14325 */ MCD_OPC_FilterValue, 144, 1, 5, 0, // Skip to: 14335 -/* 14330 */ MCD_OPC_Decode, 191, 15, 191, 2, // Opcode: STMY -/* 14335 */ MCD_OPC_FilterValue, 150, 1, 5, 0, // Skip to: 14345 -/* 14340 */ MCD_OPC_Decode, 228, 10, 181, 2, // Opcode: LMH -/* 14345 */ MCD_OPC_FilterValue, 152, 1, 5, 0, // Skip to: 14355 -/* 14350 */ MCD_OPC_Decode, 229, 10, 191, 2, // Opcode: LMY -/* 14355 */ MCD_OPC_FilterValue, 154, 1, 5, 0, // Skip to: 14365 -/* 14360 */ MCD_OPC_Decode, 245, 9, 192, 2, // Opcode: LAMY -/* 14365 */ MCD_OPC_FilterValue, 155, 1, 5, 0, // Skip to: 14375 -/* 14370 */ MCD_OPC_Decode, 156, 15, 192, 2, // Opcode: STAMY -/* 14375 */ MCD_OPC_FilterValue, 192, 1, 17, 0, // Skip to: 14397 -/* 14380 */ MCD_OPC_CheckField, 32, 4, 0, 97, 18, // Skip to: 19091 -/* 14386 */ MCD_OPC_CheckField, 8, 8, 0, 91, 18, // Skip to: 19091 -/* 14392 */ MCD_OPC_Decode, 181, 16, 193, 2, // Opcode: TP -/* 14397 */ MCD_OPC_FilterValue, 220, 1, 9, 0, // Skip to: 14411 -/* 14402 */ MCD_OPC_CheckPredicate, 15, 77, 18, // Skip to: 19091 -/* 14406 */ MCD_OPC_Decode, 133, 15, 175, 2, // Opcode: SRAK -/* 14411 */ MCD_OPC_FilterValue, 221, 1, 9, 0, // Skip to: 14425 -/* 14416 */ MCD_OPC_CheckPredicate, 15, 63, 18, // Skip to: 19091 -/* 14420 */ MCD_OPC_Decode, 218, 14, 175, 2, // Opcode: SLAK -/* 14425 */ MCD_OPC_FilterValue, 222, 1, 9, 0, // Skip to: 14439 -/* 14430 */ MCD_OPC_CheckPredicate, 15, 49, 18, // Skip to: 19091 -/* 14434 */ MCD_OPC_Decode, 140, 15, 175, 2, // Opcode: SRLK -/* 14439 */ MCD_OPC_FilterValue, 223, 1, 9, 0, // Skip to: 14453 -/* 14444 */ MCD_OPC_CheckPredicate, 15, 35, 18, // Skip to: 19091 -/* 14448 */ MCD_OPC_Decode, 237, 14, 175, 2, // Opcode: SLLK -/* 14453 */ MCD_OPC_FilterValue, 224, 1, 194, 0, // Skip to: 14652 -/* 14458 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 14461 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14474 -/* 14465 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 14643 -/* 14469 */ MCD_OPC_Decode, 154, 11, 194, 2, // Opcode: LOCFHAsmO -/* 14474 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14487 -/* 14478 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 14643 -/* 14482 */ MCD_OPC_Decode, 138, 11, 194, 2, // Opcode: LOCFHAsmH -/* 14487 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14500 -/* 14491 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 14643 -/* 14495 */ MCD_OPC_Decode, 148, 11, 194, 2, // Opcode: LOCFHAsmNLE -/* 14500 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14513 -/* 14504 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 14643 -/* 14508 */ MCD_OPC_Decode, 140, 11, 194, 2, // Opcode: LOCFHAsmL -/* 14513 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14526 -/* 14517 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 14643 -/* 14521 */ MCD_OPC_Decode, 146, 11, 194, 2, // Opcode: LOCFHAsmNHE -/* 14526 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14539 -/* 14530 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 14643 -/* 14534 */ MCD_OPC_Decode, 142, 11, 194, 2, // Opcode: LOCFHAsmLH -/* 14539 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14552 -/* 14543 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 14643 -/* 14547 */ MCD_OPC_Decode, 144, 11, 194, 2, // Opcode: LOCFHAsmNE -/* 14552 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14565 -/* 14556 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 14643 -/* 14560 */ MCD_OPC_Decode, 137, 11, 194, 2, // Opcode: LOCFHAsmE -/* 14565 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14578 -/* 14569 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 14643 -/* 14573 */ MCD_OPC_Decode, 149, 11, 194, 2, // Opcode: LOCFHAsmNLH -/* 14578 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14591 -/* 14582 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 14643 -/* 14586 */ MCD_OPC_Decode, 139, 11, 194, 2, // Opcode: LOCFHAsmHE -/* 14591 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 14604 -/* 14595 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 14643 -/* 14599 */ MCD_OPC_Decode, 147, 11, 194, 2, // Opcode: LOCFHAsmNL -/* 14604 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14617 -/* 14608 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 14643 -/* 14612 */ MCD_OPC_Decode, 141, 11, 194, 2, // Opcode: LOCFHAsmLE -/* 14617 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 14630 -/* 14621 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 14643 -/* 14625 */ MCD_OPC_Decode, 145, 11, 194, 2, // Opcode: LOCFHAsmNH -/* 14630 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 14643 -/* 14634 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 14643 -/* 14638 */ MCD_OPC_Decode, 151, 11, 194, 2, // Opcode: LOCFHAsmNO -/* 14643 */ MCD_OPC_CheckPredicate, 12, 92, 17, // Skip to: 19091 -/* 14647 */ MCD_OPC_Decode, 136, 11, 195, 2, // Opcode: LOCFHAsm -/* 14652 */ MCD_OPC_FilterValue, 225, 1, 194, 0, // Skip to: 14851 -/* 14657 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 14660 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14673 -/* 14664 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 14842 -/* 14668 */ MCD_OPC_Decode, 234, 15, 196, 2, // Opcode: STOCFHAsmO -/* 14673 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14686 -/* 14677 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 14842 -/* 14681 */ MCD_OPC_Decode, 218, 15, 196, 2, // Opcode: STOCFHAsmH -/* 14686 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14699 -/* 14690 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 14842 -/* 14694 */ MCD_OPC_Decode, 228, 15, 196, 2, // Opcode: STOCFHAsmNLE -/* 14699 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14712 -/* 14703 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 14842 -/* 14707 */ MCD_OPC_Decode, 220, 15, 196, 2, // Opcode: STOCFHAsmL -/* 14712 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14725 -/* 14716 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 14842 -/* 14720 */ MCD_OPC_Decode, 226, 15, 196, 2, // Opcode: STOCFHAsmNHE -/* 14725 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14738 -/* 14729 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 14842 -/* 14733 */ MCD_OPC_Decode, 222, 15, 196, 2, // Opcode: STOCFHAsmLH -/* 14738 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14751 -/* 14742 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 14842 -/* 14746 */ MCD_OPC_Decode, 224, 15, 196, 2, // Opcode: STOCFHAsmNE -/* 14751 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14764 -/* 14755 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 14842 -/* 14759 */ MCD_OPC_Decode, 217, 15, 196, 2, // Opcode: STOCFHAsmE -/* 14764 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14777 -/* 14768 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 14842 -/* 14772 */ MCD_OPC_Decode, 229, 15, 196, 2, // Opcode: STOCFHAsmNLH -/* 14777 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14790 -/* 14781 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 14842 -/* 14785 */ MCD_OPC_Decode, 219, 15, 196, 2, // Opcode: STOCFHAsmHE -/* 14790 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 14803 -/* 14794 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 14842 -/* 14798 */ MCD_OPC_Decode, 227, 15, 196, 2, // Opcode: STOCFHAsmNL -/* 14803 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14816 -/* 14807 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 14842 -/* 14811 */ MCD_OPC_Decode, 221, 15, 196, 2, // Opcode: STOCFHAsmLE -/* 14816 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 14829 -/* 14820 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 14842 -/* 14824 */ MCD_OPC_Decode, 225, 15, 196, 2, // Opcode: STOCFHAsmNH -/* 14829 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 14842 -/* 14833 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 14842 -/* 14837 */ MCD_OPC_Decode, 231, 15, 196, 2, // Opcode: STOCFHAsmNO -/* 14842 */ MCD_OPC_CheckPredicate, 12, 149, 16, // Skip to: 19091 -/* 14846 */ MCD_OPC_Decode, 216, 15, 197, 2, // Opcode: STOCFHAsm -/* 14851 */ MCD_OPC_FilterValue, 226, 1, 194, 0, // Skip to: 15050 -/* 14856 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 14859 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14872 -/* 14863 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15041 -/* 14867 */ MCD_OPC_Decode, 198, 11, 198, 2, // Opcode: LOCGAsmO -/* 14872 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14885 -/* 14876 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15041 -/* 14880 */ MCD_OPC_Decode, 182, 11, 198, 2, // Opcode: LOCGAsmH -/* 14885 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14898 -/* 14889 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15041 -/* 14893 */ MCD_OPC_Decode, 192, 11, 198, 2, // Opcode: LOCGAsmNLE -/* 14898 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14911 -/* 14902 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15041 -/* 14906 */ MCD_OPC_Decode, 184, 11, 198, 2, // Opcode: LOCGAsmL -/* 14911 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14924 -/* 14915 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15041 -/* 14919 */ MCD_OPC_Decode, 190, 11, 198, 2, // Opcode: LOCGAsmNHE -/* 14924 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14937 -/* 14928 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15041 -/* 14932 */ MCD_OPC_Decode, 186, 11, 198, 2, // Opcode: LOCGAsmLH -/* 14937 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14950 -/* 14941 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15041 -/* 14945 */ MCD_OPC_Decode, 188, 11, 198, 2, // Opcode: LOCGAsmNE -/* 14950 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14963 -/* 14954 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15041 -/* 14958 */ MCD_OPC_Decode, 181, 11, 198, 2, // Opcode: LOCGAsmE -/* 14963 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14976 -/* 14967 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15041 -/* 14971 */ MCD_OPC_Decode, 193, 11, 198, 2, // Opcode: LOCGAsmNLH -/* 14976 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14989 -/* 14980 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15041 -/* 14984 */ MCD_OPC_Decode, 183, 11, 198, 2, // Opcode: LOCGAsmHE -/* 14989 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15002 -/* 14993 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15041 -/* 14997 */ MCD_OPC_Decode, 191, 11, 198, 2, // Opcode: LOCGAsmNL -/* 15002 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15015 -/* 15006 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15041 -/* 15010 */ MCD_OPC_Decode, 185, 11, 198, 2, // Opcode: LOCGAsmLE -/* 15015 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15028 -/* 15019 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15041 -/* 15023 */ MCD_OPC_Decode, 189, 11, 198, 2, // Opcode: LOCGAsmNH -/* 15028 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15041 -/* 15032 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15041 -/* 15036 */ MCD_OPC_Decode, 195, 11, 198, 2, // Opcode: LOCGAsmNO -/* 15041 */ MCD_OPC_CheckPredicate, 14, 206, 15, // Skip to: 19091 -/* 15045 */ MCD_OPC_Decode, 180, 11, 199, 2, // Opcode: LOCGAsm -/* 15050 */ MCD_OPC_FilterValue, 227, 1, 194, 0, // Skip to: 15249 -/* 15055 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 15058 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15071 -/* 15062 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15240 -/* 15066 */ MCD_OPC_Decode, 128, 16, 182, 2, // Opcode: STOCGAsmO -/* 15071 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15084 -/* 15075 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15240 -/* 15079 */ MCD_OPC_Decode, 240, 15, 182, 2, // Opcode: STOCGAsmH -/* 15084 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15097 -/* 15088 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15240 -/* 15092 */ MCD_OPC_Decode, 250, 15, 182, 2, // Opcode: STOCGAsmNLE -/* 15097 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15110 -/* 15101 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15240 -/* 15105 */ MCD_OPC_Decode, 242, 15, 182, 2, // Opcode: STOCGAsmL -/* 15110 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15123 -/* 15114 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15240 -/* 15118 */ MCD_OPC_Decode, 248, 15, 182, 2, // Opcode: STOCGAsmNHE -/* 15123 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15136 -/* 15127 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15240 -/* 15131 */ MCD_OPC_Decode, 244, 15, 182, 2, // Opcode: STOCGAsmLH -/* 15136 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15149 -/* 15140 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15240 -/* 15144 */ MCD_OPC_Decode, 246, 15, 182, 2, // Opcode: STOCGAsmNE -/* 15149 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15162 -/* 15153 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15240 -/* 15157 */ MCD_OPC_Decode, 239, 15, 182, 2, // Opcode: STOCGAsmE -/* 15162 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15175 -/* 15166 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15240 -/* 15170 */ MCD_OPC_Decode, 251, 15, 182, 2, // Opcode: STOCGAsmNLH -/* 15175 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15188 -/* 15179 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15240 -/* 15183 */ MCD_OPC_Decode, 241, 15, 182, 2, // Opcode: STOCGAsmHE -/* 15188 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15201 -/* 15192 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15240 -/* 15196 */ MCD_OPC_Decode, 249, 15, 182, 2, // Opcode: STOCGAsmNL -/* 15201 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15214 -/* 15205 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15240 -/* 15209 */ MCD_OPC_Decode, 243, 15, 182, 2, // Opcode: STOCGAsmLE -/* 15214 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15227 -/* 15218 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15240 -/* 15222 */ MCD_OPC_Decode, 247, 15, 182, 2, // Opcode: STOCGAsmNH -/* 15227 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15240 -/* 15231 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15240 -/* 15235 */ MCD_OPC_Decode, 253, 15, 182, 2, // Opcode: STOCGAsmNO -/* 15240 */ MCD_OPC_CheckPredicate, 14, 7, 15, // Skip to: 19091 -/* 15244 */ MCD_OPC_Decode, 238, 15, 183, 2, // Opcode: STOCGAsm -/* 15249 */ MCD_OPC_FilterValue, 228, 1, 9, 0, // Skip to: 15263 -/* 15254 */ MCD_OPC_CheckPredicate, 17, 249, 14, // Skip to: 19091 -/* 15258 */ MCD_OPC_Decode, 247, 9, 172, 2, // Opcode: LANG -/* 15263 */ MCD_OPC_FilterValue, 230, 1, 9, 0, // Skip to: 15277 -/* 15268 */ MCD_OPC_CheckPredicate, 17, 235, 14, // Skip to: 19091 -/* 15272 */ MCD_OPC_Decode, 249, 9, 172, 2, // Opcode: LAOG -/* 15277 */ MCD_OPC_FilterValue, 231, 1, 9, 0, // Skip to: 15291 -/* 15282 */ MCD_OPC_CheckPredicate, 17, 221, 14, // Skip to: 19091 -/* 15286 */ MCD_OPC_Decode, 254, 9, 172, 2, // Opcode: LAXG -/* 15291 */ MCD_OPC_FilterValue, 232, 1, 9, 0, // Skip to: 15305 -/* 15296 */ MCD_OPC_CheckPredicate, 17, 207, 14, // Skip to: 19091 -/* 15300 */ MCD_OPC_Decode, 239, 9, 172, 2, // Opcode: LAAG -/* 15305 */ MCD_OPC_FilterValue, 234, 1, 9, 0, // Skip to: 15319 -/* 15310 */ MCD_OPC_CheckPredicate, 17, 193, 14, // Skip to: 19091 -/* 15314 */ MCD_OPC_Decode, 241, 9, 172, 2, // Opcode: LAALG -/* 15319 */ MCD_OPC_FilterValue, 242, 1, 194, 0, // Skip to: 15518 -/* 15324 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 15327 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15340 -/* 15331 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15509 -/* 15335 */ MCD_OPC_Decode, 132, 11, 200, 2, // Opcode: LOCAsmO -/* 15340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15353 -/* 15344 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15509 -/* 15348 */ MCD_OPC_Decode, 244, 10, 200, 2, // Opcode: LOCAsmH -/* 15353 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15366 -/* 15357 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15509 -/* 15361 */ MCD_OPC_Decode, 254, 10, 200, 2, // Opcode: LOCAsmNLE -/* 15366 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15379 -/* 15370 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15509 -/* 15374 */ MCD_OPC_Decode, 246, 10, 200, 2, // Opcode: LOCAsmL -/* 15379 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15392 -/* 15383 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15509 -/* 15387 */ MCD_OPC_Decode, 252, 10, 200, 2, // Opcode: LOCAsmNHE -/* 15392 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15405 -/* 15396 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15509 -/* 15400 */ MCD_OPC_Decode, 248, 10, 200, 2, // Opcode: LOCAsmLH -/* 15405 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15418 -/* 15409 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15509 -/* 15413 */ MCD_OPC_Decode, 250, 10, 200, 2, // Opcode: LOCAsmNE -/* 15418 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15431 -/* 15422 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15509 -/* 15426 */ MCD_OPC_Decode, 243, 10, 200, 2, // Opcode: LOCAsmE -/* 15431 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15444 -/* 15435 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15509 -/* 15439 */ MCD_OPC_Decode, 255, 10, 200, 2, // Opcode: LOCAsmNLH -/* 15444 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15457 -/* 15448 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15509 -/* 15452 */ MCD_OPC_Decode, 245, 10, 200, 2, // Opcode: LOCAsmHE -/* 15457 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15470 -/* 15461 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15509 -/* 15465 */ MCD_OPC_Decode, 253, 10, 200, 2, // Opcode: LOCAsmNL -/* 15470 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15483 -/* 15474 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15509 -/* 15478 */ MCD_OPC_Decode, 247, 10, 200, 2, // Opcode: LOCAsmLE -/* 15483 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15496 -/* 15487 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15509 -/* 15491 */ MCD_OPC_Decode, 251, 10, 200, 2, // Opcode: LOCAsmNH -/* 15496 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15509 -/* 15500 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15509 -/* 15504 */ MCD_OPC_Decode, 129, 11, 200, 2, // Opcode: LOCAsmNO -/* 15509 */ MCD_OPC_CheckPredicate, 14, 250, 13, // Skip to: 19091 -/* 15513 */ MCD_OPC_Decode, 242, 10, 201, 2, // Opcode: LOCAsm -/* 15518 */ MCD_OPC_FilterValue, 243, 1, 194, 0, // Skip to: 15717 -/* 15523 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 15526 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15539 -/* 15530 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15708 -/* 15534 */ MCD_OPC_Decode, 212, 15, 178, 2, // Opcode: STOCAsmO -/* 15539 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15552 -/* 15543 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15708 -/* 15547 */ MCD_OPC_Decode, 196, 15, 178, 2, // Opcode: STOCAsmH -/* 15552 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15565 -/* 15556 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15708 -/* 15560 */ MCD_OPC_Decode, 206, 15, 178, 2, // Opcode: STOCAsmNLE -/* 15565 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15578 -/* 15569 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15708 -/* 15573 */ MCD_OPC_Decode, 198, 15, 178, 2, // Opcode: STOCAsmL -/* 15578 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15591 -/* 15582 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15708 -/* 15586 */ MCD_OPC_Decode, 204, 15, 178, 2, // Opcode: STOCAsmNHE -/* 15591 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15604 -/* 15595 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15708 -/* 15599 */ MCD_OPC_Decode, 200, 15, 178, 2, // Opcode: STOCAsmLH -/* 15604 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15617 -/* 15608 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15708 -/* 15612 */ MCD_OPC_Decode, 202, 15, 178, 2, // Opcode: STOCAsmNE -/* 15617 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15630 -/* 15621 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15708 -/* 15625 */ MCD_OPC_Decode, 195, 15, 178, 2, // Opcode: STOCAsmE -/* 15630 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15643 -/* 15634 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15708 -/* 15638 */ MCD_OPC_Decode, 207, 15, 178, 2, // Opcode: STOCAsmNLH -/* 15643 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15656 -/* 15647 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15708 -/* 15651 */ MCD_OPC_Decode, 197, 15, 178, 2, // Opcode: STOCAsmHE -/* 15656 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15669 -/* 15660 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15708 -/* 15664 */ MCD_OPC_Decode, 205, 15, 178, 2, // Opcode: STOCAsmNL -/* 15669 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15682 -/* 15673 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15708 -/* 15677 */ MCD_OPC_Decode, 199, 15, 178, 2, // Opcode: STOCAsmLE -/* 15682 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15695 -/* 15686 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15708 -/* 15690 */ MCD_OPC_Decode, 203, 15, 178, 2, // Opcode: STOCAsmNH -/* 15695 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15708 -/* 15699 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15708 -/* 15703 */ MCD_OPC_Decode, 209, 15, 178, 2, // Opcode: STOCAsmNO -/* 15708 */ MCD_OPC_CheckPredicate, 14, 51, 13, // Skip to: 19091 -/* 15712 */ MCD_OPC_Decode, 194, 15, 179, 2, // Opcode: STOCAsm -/* 15717 */ MCD_OPC_FilterValue, 244, 1, 9, 0, // Skip to: 15731 -/* 15722 */ MCD_OPC_CheckPredicate, 17, 37, 13, // Skip to: 19091 -/* 15726 */ MCD_OPC_Decode, 246, 9, 191, 2, // Opcode: LAN -/* 15731 */ MCD_OPC_FilterValue, 246, 1, 9, 0, // Skip to: 15745 -/* 15736 */ MCD_OPC_CheckPredicate, 17, 23, 13, // Skip to: 19091 -/* 15740 */ MCD_OPC_Decode, 248, 9, 191, 2, // Opcode: LAO -/* 15745 */ MCD_OPC_FilterValue, 247, 1, 9, 0, // Skip to: 15759 -/* 15750 */ MCD_OPC_CheckPredicate, 17, 9, 13, // Skip to: 19091 -/* 15754 */ MCD_OPC_Decode, 253, 9, 191, 2, // Opcode: LAX -/* 15759 */ MCD_OPC_FilterValue, 248, 1, 9, 0, // Skip to: 15773 -/* 15764 */ MCD_OPC_CheckPredicate, 17, 251, 12, // Skip to: 19091 -/* 15768 */ MCD_OPC_Decode, 238, 9, 191, 2, // Opcode: LAA -/* 15773 */ MCD_OPC_FilterValue, 250, 1, 241, 12, // Skip to: 19091 -/* 15778 */ MCD_OPC_CheckPredicate, 17, 237, 12, // Skip to: 19091 -/* 15782 */ MCD_OPC_Decode, 240, 9, 191, 2, // Opcode: LAAL -/* 15787 */ MCD_OPC_FilterValue, 236, 1, 195, 8, // Skip to: 18035 -/* 15792 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 15795 */ MCD_OPC_FilterValue, 66, 201, 0, // Skip to: 16000 -/* 15799 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... -/* 15802 */ MCD_OPC_FilterValue, 0, 213, 12, // Skip to: 19091 -/* 15806 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 15809 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15822 -/* 15813 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 15991 -/* 15817 */ MCD_OPC_Decode, 158, 12, 202, 2, // Opcode: LOCHIAsmO -/* 15822 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15835 -/* 15826 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 15991 -/* 15830 */ MCD_OPC_Decode, 142, 12, 202, 2, // Opcode: LOCHIAsmH -/* 15835 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15848 -/* 15839 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 15991 -/* 15843 */ MCD_OPC_Decode, 152, 12, 202, 2, // Opcode: LOCHIAsmNLE -/* 15848 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15861 -/* 15852 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 15991 -/* 15856 */ MCD_OPC_Decode, 144, 12, 202, 2, // Opcode: LOCHIAsmL -/* 15861 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15874 -/* 15865 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 15991 -/* 15869 */ MCD_OPC_Decode, 150, 12, 202, 2, // Opcode: LOCHIAsmNHE -/* 15874 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15887 -/* 15878 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 15991 -/* 15882 */ MCD_OPC_Decode, 146, 12, 202, 2, // Opcode: LOCHIAsmLH -/* 15887 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15900 -/* 15891 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 15991 -/* 15895 */ MCD_OPC_Decode, 148, 12, 202, 2, // Opcode: LOCHIAsmNE -/* 15900 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15913 -/* 15904 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 15991 -/* 15908 */ MCD_OPC_Decode, 141, 12, 202, 2, // Opcode: LOCHIAsmE -/* 15913 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15926 -/* 15917 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 15991 -/* 15921 */ MCD_OPC_Decode, 153, 12, 202, 2, // Opcode: LOCHIAsmNLH -/* 15926 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15939 -/* 15930 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 15991 -/* 15934 */ MCD_OPC_Decode, 143, 12, 202, 2, // Opcode: LOCHIAsmHE -/* 15939 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15952 -/* 15943 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 15991 -/* 15947 */ MCD_OPC_Decode, 151, 12, 202, 2, // Opcode: LOCHIAsmNL -/* 15952 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15965 -/* 15956 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 15991 -/* 15960 */ MCD_OPC_Decode, 145, 12, 202, 2, // Opcode: LOCHIAsmLE -/* 15965 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15978 -/* 15969 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 15991 -/* 15973 */ MCD_OPC_Decode, 149, 12, 202, 2, // Opcode: LOCHIAsmNH -/* 15978 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15991 -/* 15982 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 15991 -/* 15986 */ MCD_OPC_Decode, 155, 12, 202, 2, // Opcode: LOCHIAsmNO -/* 15991 */ MCD_OPC_CheckPredicate, 12, 24, 12, // Skip to: 19091 -/* 15995 */ MCD_OPC_Decode, 140, 12, 203, 2, // Opcode: LOCHIAsm -/* 16000 */ MCD_OPC_FilterValue, 68, 11, 0, // Skip to: 16015 -/* 16004 */ MCD_OPC_CheckField, 8, 8, 0, 9, 12, // Skip to: 19091 -/* 16010 */ MCD_OPC_Decode, 128, 4, 204, 2, // Opcode: BRXHG -/* 16015 */ MCD_OPC_FilterValue, 69, 11, 0, // Skip to: 16030 -/* 16019 */ MCD_OPC_CheckField, 8, 8, 0, 250, 11, // Skip to: 19091 -/* 16025 */ MCD_OPC_Decode, 130, 4, 204, 2, // Opcode: BRXLG -/* 16030 */ MCD_OPC_FilterValue, 70, 201, 0, // Skip to: 16235 -/* 16034 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... -/* 16037 */ MCD_OPC_FilterValue, 0, 234, 11, // Skip to: 19091 -/* 16041 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16044 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 16057 -/* 16048 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 16226 -/* 16052 */ MCD_OPC_Decode, 220, 11, 205, 2, // Opcode: LOCGHIAsmO -/* 16057 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16070 -/* 16061 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 16226 -/* 16065 */ MCD_OPC_Decode, 204, 11, 205, 2, // Opcode: LOCGHIAsmH -/* 16070 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 16083 -/* 16074 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 16226 -/* 16078 */ MCD_OPC_Decode, 214, 11, 205, 2, // Opcode: LOCGHIAsmNLE -/* 16083 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 16096 -/* 16087 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 16226 -/* 16091 */ MCD_OPC_Decode, 206, 11, 205, 2, // Opcode: LOCGHIAsmL -/* 16096 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 16109 -/* 16100 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 16226 -/* 16104 */ MCD_OPC_Decode, 212, 11, 205, 2, // Opcode: LOCGHIAsmNHE -/* 16109 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 16122 -/* 16113 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 16226 -/* 16117 */ MCD_OPC_Decode, 208, 11, 205, 2, // Opcode: LOCGHIAsmLH -/* 16122 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 16135 -/* 16126 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 16226 -/* 16130 */ MCD_OPC_Decode, 210, 11, 205, 2, // Opcode: LOCGHIAsmNE -/* 16135 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 16148 -/* 16139 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 16226 -/* 16143 */ MCD_OPC_Decode, 203, 11, 205, 2, // Opcode: LOCGHIAsmE -/* 16148 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 16161 -/* 16152 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 16226 -/* 16156 */ MCD_OPC_Decode, 215, 11, 205, 2, // Opcode: LOCGHIAsmNLH -/* 16161 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 16174 -/* 16165 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 16226 -/* 16169 */ MCD_OPC_Decode, 205, 11, 205, 2, // Opcode: LOCGHIAsmHE -/* 16174 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 16187 -/* 16178 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 16226 -/* 16182 */ MCD_OPC_Decode, 213, 11, 205, 2, // Opcode: LOCGHIAsmNL -/* 16187 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 16200 -/* 16191 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 16226 -/* 16195 */ MCD_OPC_Decode, 207, 11, 205, 2, // Opcode: LOCGHIAsmLE -/* 16200 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 16213 -/* 16204 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 16226 -/* 16208 */ MCD_OPC_Decode, 211, 11, 205, 2, // Opcode: LOCGHIAsmNH -/* 16213 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 16226 -/* 16217 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 16226 -/* 16221 */ MCD_OPC_Decode, 217, 11, 205, 2, // Opcode: LOCGHIAsmNO -/* 16226 */ MCD_OPC_CheckPredicate, 12, 45, 11, // Skip to: 19091 -/* 16230 */ MCD_OPC_Decode, 202, 11, 206, 2, // Opcode: LOCGHIAsm -/* 16235 */ MCD_OPC_FilterValue, 78, 201, 0, // Skip to: 16440 -/* 16239 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... -/* 16242 */ MCD_OPC_FilterValue, 0, 29, 11, // Skip to: 19091 -/* 16246 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16249 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 16262 -/* 16253 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 16431 -/* 16257 */ MCD_OPC_Decode, 136, 12, 207, 2, // Opcode: LOCHHIAsmO -/* 16262 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16275 -/* 16266 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 16431 -/* 16270 */ MCD_OPC_Decode, 248, 11, 207, 2, // Opcode: LOCHHIAsmH -/* 16275 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 16288 -/* 16279 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 16431 -/* 16283 */ MCD_OPC_Decode, 130, 12, 207, 2, // Opcode: LOCHHIAsmNLE -/* 16288 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 16301 -/* 16292 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 16431 -/* 16296 */ MCD_OPC_Decode, 250, 11, 207, 2, // Opcode: LOCHHIAsmL -/* 16301 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 16314 -/* 16305 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 16431 -/* 16309 */ MCD_OPC_Decode, 128, 12, 207, 2, // Opcode: LOCHHIAsmNHE -/* 16314 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 16327 -/* 16318 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 16431 -/* 16322 */ MCD_OPC_Decode, 252, 11, 207, 2, // Opcode: LOCHHIAsmLH -/* 16327 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 16340 -/* 16331 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 16431 -/* 16335 */ MCD_OPC_Decode, 254, 11, 207, 2, // Opcode: LOCHHIAsmNE -/* 16340 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 16353 -/* 16344 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 16431 -/* 16348 */ MCD_OPC_Decode, 247, 11, 207, 2, // Opcode: LOCHHIAsmE -/* 16353 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 16366 -/* 16357 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 16431 -/* 16361 */ MCD_OPC_Decode, 131, 12, 207, 2, // Opcode: LOCHHIAsmNLH -/* 16366 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 16379 -/* 16370 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 16431 -/* 16374 */ MCD_OPC_Decode, 249, 11, 207, 2, // Opcode: LOCHHIAsmHE -/* 16379 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 16392 -/* 16383 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 16431 -/* 16387 */ MCD_OPC_Decode, 129, 12, 207, 2, // Opcode: LOCHHIAsmNL -/* 16392 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 16405 -/* 16396 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 16431 -/* 16400 */ MCD_OPC_Decode, 251, 11, 207, 2, // Opcode: LOCHHIAsmLE -/* 16405 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 16418 -/* 16409 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 16431 -/* 16413 */ MCD_OPC_Decode, 255, 11, 207, 2, // Opcode: LOCHHIAsmNH -/* 16418 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 16431 -/* 16422 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 16431 -/* 16426 */ MCD_OPC_Decode, 133, 12, 207, 2, // Opcode: LOCHHIAsmNO -/* 16431 */ MCD_OPC_CheckPredicate, 12, 96, 10, // Skip to: 19091 -/* 16435 */ MCD_OPC_Decode, 246, 11, 208, 2, // Opcode: LOCHHIAsm -/* 16440 */ MCD_OPC_FilterValue, 81, 9, 0, // Skip to: 16453 -/* 16444 */ MCD_OPC_CheckPredicate, 11, 83, 10, // Skip to: 19091 -/* 16448 */ MCD_OPC_Decode, 165, 14, 209, 2, // Opcode: RISBLG -/* 16453 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 16462 -/* 16457 */ MCD_OPC_Decode, 168, 14, 210, 2, // Opcode: RNSBG -/* 16462 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 16471 -/* 16466 */ MCD_OPC_Decode, 161, 14, 210, 2, // Opcode: RISBG -/* 16471 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 16480 -/* 16475 */ MCD_OPC_Decode, 169, 14, 210, 2, // Opcode: ROSBG -/* 16480 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 16489 -/* 16484 */ MCD_OPC_Decode, 176, 14, 210, 2, // Opcode: RXSBG -/* 16489 */ MCD_OPC_FilterValue, 89, 9, 0, // Skip to: 16502 -/* 16493 */ MCD_OPC_CheckPredicate, 24, 34, 10, // Skip to: 19091 -/* 16497 */ MCD_OPC_Decode, 163, 14, 210, 2, // Opcode: RISBGN -/* 16502 */ MCD_OPC_FilterValue, 93, 9, 0, // Skip to: 16515 -/* 16506 */ MCD_OPC_CheckPredicate, 11, 21, 10, // Skip to: 19091 -/* 16510 */ MCD_OPC_Decode, 164, 14, 211, 2, // Opcode: RISBHG -/* 16515 */ MCD_OPC_FilterValue, 100, 69, 0, // Skip to: 16588 -/* 16519 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16522 */ MCD_OPC_FilterValue, 0, 5, 10, // Skip to: 19091 -/* 16526 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16529 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16538 -/* 16533 */ MCD_OPC_Decode, 140, 5, 212, 2, // Opcode: CGRJAsmH -/* 16538 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16547 -/* 16542 */ MCD_OPC_Decode, 142, 5, 212, 2, // Opcode: CGRJAsmL -/* 16547 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16556 -/* 16551 */ MCD_OPC_Decode, 144, 5, 212, 2, // Opcode: CGRJAsmLH -/* 16556 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16565 -/* 16560 */ MCD_OPC_Decode, 139, 5, 212, 2, // Opcode: CGRJAsmE -/* 16565 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16574 -/* 16569 */ MCD_OPC_Decode, 141, 5, 212, 2, // Opcode: CGRJAsmHE -/* 16574 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16583 -/* 16578 */ MCD_OPC_Decode, 143, 5, 212, 2, // Opcode: CGRJAsmLE -/* 16583 */ MCD_OPC_Decode, 138, 5, 213, 2, // Opcode: CGRJAsm -/* 16588 */ MCD_OPC_FilterValue, 101, 69, 0, // Skip to: 16661 -/* 16592 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16595 */ MCD_OPC_FilterValue, 0, 188, 9, // Skip to: 19091 -/* 16599 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16602 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16611 -/* 16606 */ MCD_OPC_Decode, 192, 6, 212, 2, // Opcode: CLGRJAsmH -/* 16611 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16620 -/* 16615 */ MCD_OPC_Decode, 194, 6, 212, 2, // Opcode: CLGRJAsmL -/* 16620 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16629 -/* 16624 */ MCD_OPC_Decode, 196, 6, 212, 2, // Opcode: CLGRJAsmLH -/* 16629 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16638 -/* 16633 */ MCD_OPC_Decode, 191, 6, 212, 2, // Opcode: CLGRJAsmE -/* 16638 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16647 -/* 16642 */ MCD_OPC_Decode, 193, 6, 212, 2, // Opcode: CLGRJAsmHE -/* 16647 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16656 -/* 16651 */ MCD_OPC_Decode, 195, 6, 212, 2, // Opcode: CLGRJAsmLE -/* 16656 */ MCD_OPC_Decode, 190, 6, 213, 2, // Opcode: CLGRJAsm -/* 16661 */ MCD_OPC_FilterValue, 112, 76, 0, // Skip to: 16741 -/* 16665 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16668 */ MCD_OPC_FilterValue, 0, 115, 9, // Skip to: 19091 -/* 16672 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16675 */ MCD_OPC_FilterValue, 0, 108, 9, // Skip to: 19091 -/* 16679 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16682 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16691 -/* 16686 */ MCD_OPC_Decode, 239, 4, 214, 2, // Opcode: CGITAsmH -/* 16691 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16700 -/* 16695 */ MCD_OPC_Decode, 241, 4, 214, 2, // Opcode: CGITAsmL -/* 16700 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16709 -/* 16704 */ MCD_OPC_Decode, 243, 4, 214, 2, // Opcode: CGITAsmLH -/* 16709 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16718 -/* 16713 */ MCD_OPC_Decode, 238, 4, 214, 2, // Opcode: CGITAsmE -/* 16718 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16727 -/* 16722 */ MCD_OPC_Decode, 240, 4, 214, 2, // Opcode: CGITAsmHE -/* 16727 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16736 -/* 16731 */ MCD_OPC_Decode, 242, 4, 214, 2, // Opcode: CGITAsmLE -/* 16736 */ MCD_OPC_Decode, 237, 4, 215, 2, // Opcode: CGITAsm -/* 16741 */ MCD_OPC_FilterValue, 113, 76, 0, // Skip to: 16821 -/* 16745 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16748 */ MCD_OPC_FilterValue, 0, 35, 9, // Skip to: 19091 -/* 16752 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16755 */ MCD_OPC_FilterValue, 0, 28, 9, // Skip to: 19091 -/* 16759 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16762 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16771 -/* 16766 */ MCD_OPC_Decode, 163, 6, 216, 2, // Opcode: CLGITAsmH -/* 16771 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16780 -/* 16775 */ MCD_OPC_Decode, 165, 6, 216, 2, // Opcode: CLGITAsmL -/* 16780 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16789 -/* 16784 */ MCD_OPC_Decode, 167, 6, 216, 2, // Opcode: CLGITAsmLH -/* 16789 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16798 -/* 16793 */ MCD_OPC_Decode, 162, 6, 216, 2, // Opcode: CLGITAsmE -/* 16798 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16807 -/* 16802 */ MCD_OPC_Decode, 164, 6, 216, 2, // Opcode: CLGITAsmHE -/* 16807 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16816 -/* 16811 */ MCD_OPC_Decode, 166, 6, 216, 2, // Opcode: CLGITAsmLE -/* 16816 */ MCD_OPC_Decode, 161, 6, 217, 2, // Opcode: CLGITAsm -/* 16821 */ MCD_OPC_FilterValue, 114, 76, 0, // Skip to: 16901 -/* 16825 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16828 */ MCD_OPC_FilterValue, 0, 211, 8, // Skip to: 19091 -/* 16832 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16835 */ MCD_OPC_FilterValue, 0, 204, 8, // Skip to: 19091 -/* 16839 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16842 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16851 -/* 16846 */ MCD_OPC_Decode, 212, 5, 218, 2, // Opcode: CITAsmH -/* 16851 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16860 -/* 16855 */ MCD_OPC_Decode, 214, 5, 218, 2, // Opcode: CITAsmL -/* 16860 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16869 -/* 16864 */ MCD_OPC_Decode, 216, 5, 218, 2, // Opcode: CITAsmLH -/* 16869 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16878 -/* 16873 */ MCD_OPC_Decode, 211, 5, 218, 2, // Opcode: CITAsmE -/* 16878 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16887 -/* 16882 */ MCD_OPC_Decode, 213, 5, 218, 2, // Opcode: CITAsmHE -/* 16887 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16896 -/* 16891 */ MCD_OPC_Decode, 215, 5, 218, 2, // Opcode: CITAsmLE -/* 16896 */ MCD_OPC_Decode, 210, 5, 219, 2, // Opcode: CITAsm -/* 16901 */ MCD_OPC_FilterValue, 115, 76, 0, // Skip to: 16981 -/* 16905 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16908 */ MCD_OPC_FilterValue, 0, 131, 8, // Skip to: 19091 -/* 16912 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 16915 */ MCD_OPC_FilterValue, 0, 124, 8, // Skip to: 19091 -/* 16919 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16922 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16931 -/* 16926 */ MCD_OPC_Decode, 237, 5, 220, 2, // Opcode: CLFITAsmH -/* 16931 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16940 -/* 16935 */ MCD_OPC_Decode, 239, 5, 220, 2, // Opcode: CLFITAsmL -/* 16940 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16949 -/* 16944 */ MCD_OPC_Decode, 241, 5, 220, 2, // Opcode: CLFITAsmLH -/* 16949 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16958 -/* 16953 */ MCD_OPC_Decode, 236, 5, 220, 2, // Opcode: CLFITAsmE -/* 16958 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16967 -/* 16962 */ MCD_OPC_Decode, 238, 5, 220, 2, // Opcode: CLFITAsmHE -/* 16967 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16976 -/* 16971 */ MCD_OPC_Decode, 240, 5, 220, 2, // Opcode: CLFITAsmLE -/* 16976 */ MCD_OPC_Decode, 235, 5, 221, 2, // Opcode: CLFITAsm -/* 16981 */ MCD_OPC_FilterValue, 118, 69, 0, // Skip to: 17054 -/* 16985 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 16988 */ MCD_OPC_FilterValue, 0, 51, 8, // Skip to: 19091 -/* 16992 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 16995 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17004 -/* 16999 */ MCD_OPC_Decode, 234, 7, 222, 2, // Opcode: CRJAsmH -/* 17004 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17013 -/* 17008 */ MCD_OPC_Decode, 236, 7, 222, 2, // Opcode: CRJAsmL -/* 17013 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17022 -/* 17017 */ MCD_OPC_Decode, 238, 7, 222, 2, // Opcode: CRJAsmLH -/* 17022 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17031 -/* 17026 */ MCD_OPC_Decode, 233, 7, 222, 2, // Opcode: CRJAsmE -/* 17031 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17040 -/* 17035 */ MCD_OPC_Decode, 235, 7, 222, 2, // Opcode: CRJAsmHE -/* 17040 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17049 -/* 17044 */ MCD_OPC_Decode, 237, 7, 222, 2, // Opcode: CRJAsmLE -/* 17049 */ MCD_OPC_Decode, 232, 7, 223, 2, // Opcode: CRJAsm -/* 17054 */ MCD_OPC_FilterValue, 119, 69, 0, // Skip to: 17127 -/* 17058 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17061 */ MCD_OPC_FilterValue, 0, 234, 7, // Skip to: 19091 -/* 17065 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17068 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17077 -/* 17072 */ MCD_OPC_Decode, 163, 7, 222, 2, // Opcode: CLRJAsmH -/* 17077 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17086 -/* 17081 */ MCD_OPC_Decode, 165, 7, 222, 2, // Opcode: CLRJAsmL -/* 17086 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17095 -/* 17090 */ MCD_OPC_Decode, 167, 7, 222, 2, // Opcode: CLRJAsmLH -/* 17095 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17104 -/* 17099 */ MCD_OPC_Decode, 162, 7, 222, 2, // Opcode: CLRJAsmE -/* 17104 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17113 -/* 17108 */ MCD_OPC_Decode, 164, 7, 222, 2, // Opcode: CLRJAsmHE -/* 17113 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17122 -/* 17117 */ MCD_OPC_Decode, 166, 7, 222, 2, // Opcode: CLRJAsmLE -/* 17122 */ MCD_OPC_Decode, 161, 7, 223, 2, // Opcode: CLRJAsm -/* 17127 */ MCD_OPC_FilterValue, 124, 62, 0, // Skip to: 17193 -/* 17131 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17134 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17143 -/* 17138 */ MCD_OPC_Decode, 225, 4, 224, 2, // Opcode: CGIJAsmH -/* 17143 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17152 -/* 17147 */ MCD_OPC_Decode, 227, 4, 224, 2, // Opcode: CGIJAsmL -/* 17152 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17161 -/* 17156 */ MCD_OPC_Decode, 229, 4, 224, 2, // Opcode: CGIJAsmLH -/* 17161 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17170 -/* 17165 */ MCD_OPC_Decode, 224, 4, 224, 2, // Opcode: CGIJAsmE -/* 17170 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17179 -/* 17174 */ MCD_OPC_Decode, 226, 4, 224, 2, // Opcode: CGIJAsmHE -/* 17179 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17188 -/* 17183 */ MCD_OPC_Decode, 228, 4, 224, 2, // Opcode: CGIJAsmLE -/* 17188 */ MCD_OPC_Decode, 223, 4, 225, 2, // Opcode: CGIJAsm -/* 17193 */ MCD_OPC_FilterValue, 125, 62, 0, // Skip to: 17259 -/* 17197 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17200 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17209 -/* 17204 */ MCD_OPC_Decode, 149, 6, 226, 2, // Opcode: CLGIJAsmH -/* 17209 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17218 -/* 17213 */ MCD_OPC_Decode, 151, 6, 226, 2, // Opcode: CLGIJAsmL -/* 17218 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17227 -/* 17222 */ MCD_OPC_Decode, 153, 6, 226, 2, // Opcode: CLGIJAsmLH -/* 17227 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17236 -/* 17231 */ MCD_OPC_Decode, 148, 6, 226, 2, // Opcode: CLGIJAsmE -/* 17236 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17245 -/* 17240 */ MCD_OPC_Decode, 150, 6, 226, 2, // Opcode: CLGIJAsmHE -/* 17245 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17254 -/* 17249 */ MCD_OPC_Decode, 152, 6, 226, 2, // Opcode: CLGIJAsmLE -/* 17254 */ MCD_OPC_Decode, 147, 6, 227, 2, // Opcode: CLGIJAsm -/* 17259 */ MCD_OPC_FilterValue, 126, 62, 0, // Skip to: 17325 -/* 17263 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17266 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17275 -/* 17270 */ MCD_OPC_Decode, 198, 5, 228, 2, // Opcode: CIJAsmH -/* 17275 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17284 -/* 17279 */ MCD_OPC_Decode, 200, 5, 228, 2, // Opcode: CIJAsmL -/* 17284 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17293 -/* 17288 */ MCD_OPC_Decode, 202, 5, 228, 2, // Opcode: CIJAsmLH -/* 17293 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17302 -/* 17297 */ MCD_OPC_Decode, 197, 5, 228, 2, // Opcode: CIJAsmE -/* 17302 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17311 -/* 17306 */ MCD_OPC_Decode, 199, 5, 228, 2, // Opcode: CIJAsmHE -/* 17311 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17320 -/* 17315 */ MCD_OPC_Decode, 201, 5, 228, 2, // Opcode: CIJAsmLE -/* 17320 */ MCD_OPC_Decode, 196, 5, 229, 2, // Opcode: CIJAsm -/* 17325 */ MCD_OPC_FilterValue, 127, 62, 0, // Skip to: 17391 -/* 17329 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17332 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17341 -/* 17336 */ MCD_OPC_Decode, 130, 7, 230, 2, // Opcode: CLIJAsmH -/* 17341 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17350 -/* 17345 */ MCD_OPC_Decode, 132, 7, 230, 2, // Opcode: CLIJAsmL -/* 17350 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17359 -/* 17354 */ MCD_OPC_Decode, 134, 7, 230, 2, // Opcode: CLIJAsmLH -/* 17359 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17368 -/* 17363 */ MCD_OPC_Decode, 129, 7, 230, 2, // Opcode: CLIJAsmE -/* 17368 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17377 -/* 17372 */ MCD_OPC_Decode, 131, 7, 230, 2, // Opcode: CLIJAsmHE -/* 17377 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17386 -/* 17381 */ MCD_OPC_Decode, 133, 7, 230, 2, // Opcode: CLIJAsmLE -/* 17386 */ MCD_OPC_Decode, 128, 7, 231, 2, // Opcode: CLIJAsm -/* 17391 */ MCD_OPC_FilterValue, 216, 1, 15, 0, // Skip to: 17411 -/* 17396 */ MCD_OPC_CheckPredicate, 15, 155, 6, // Skip to: 19091 -/* 17400 */ MCD_OPC_CheckField, 8, 8, 0, 149, 6, // Skip to: 19091 -/* 17406 */ MCD_OPC_Decode, 254, 2, 232, 2, // Opcode: AHIK -/* 17411 */ MCD_OPC_FilterValue, 217, 1, 15, 0, // Skip to: 17431 -/* 17416 */ MCD_OPC_CheckPredicate, 15, 135, 6, // Skip to: 19091 -/* 17420 */ MCD_OPC_CheckField, 8, 8, 0, 129, 6, // Skip to: 19091 -/* 17426 */ MCD_OPC_Decode, 246, 2, 233, 2, // Opcode: AGHIK -/* 17431 */ MCD_OPC_FilterValue, 218, 1, 15, 0, // Skip to: 17451 -/* 17436 */ MCD_OPC_CheckPredicate, 15, 115, 6, // Skip to: 19091 -/* 17440 */ MCD_OPC_CheckField, 8, 8, 0, 109, 6, // Skip to: 19091 -/* 17446 */ MCD_OPC_Decode, 145, 3, 232, 2, // Opcode: ALHSIK -/* 17451 */ MCD_OPC_FilterValue, 219, 1, 15, 0, // Skip to: 17471 -/* 17456 */ MCD_OPC_CheckPredicate, 15, 95, 6, // Skip to: 19091 -/* 17460 */ MCD_OPC_CheckField, 8, 8, 0, 89, 6, // Skip to: 19091 -/* 17466 */ MCD_OPC_Decode, 139, 3, 233, 2, // Opcode: ALGHSIK -/* 17471 */ MCD_OPC_FilterValue, 228, 1, 69, 0, // Skip to: 17545 -/* 17476 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17479 */ MCD_OPC_FilterValue, 0, 72, 6, // Skip to: 19091 -/* 17483 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17486 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17495 -/* 17490 */ MCD_OPC_Decode, 254, 4, 234, 2, // Opcode: CGRBAsmH -/* 17495 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17504 -/* 17499 */ MCD_OPC_Decode, 128, 5, 234, 2, // Opcode: CGRBAsmL -/* 17504 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17513 -/* 17508 */ MCD_OPC_Decode, 130, 5, 234, 2, // Opcode: CGRBAsmLH -/* 17513 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17522 -/* 17517 */ MCD_OPC_Decode, 253, 4, 234, 2, // Opcode: CGRBAsmE -/* 17522 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17531 -/* 17526 */ MCD_OPC_Decode, 255, 4, 234, 2, // Opcode: CGRBAsmHE -/* 17531 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17540 -/* 17535 */ MCD_OPC_Decode, 129, 5, 234, 2, // Opcode: CGRBAsmLE -/* 17540 */ MCD_OPC_Decode, 252, 4, 235, 2, // Opcode: CGRBAsm -/* 17545 */ MCD_OPC_FilterValue, 229, 1, 69, 0, // Skip to: 17619 -/* 17550 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17553 */ MCD_OPC_FilterValue, 0, 254, 5, // Skip to: 19091 -/* 17557 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17560 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17569 -/* 17564 */ MCD_OPC_Decode, 178, 6, 234, 2, // Opcode: CLGRBAsmH -/* 17569 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17578 -/* 17573 */ MCD_OPC_Decode, 180, 6, 234, 2, // Opcode: CLGRBAsmL -/* 17578 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17587 -/* 17582 */ MCD_OPC_Decode, 182, 6, 234, 2, // Opcode: CLGRBAsmLH -/* 17587 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17596 -/* 17591 */ MCD_OPC_Decode, 177, 6, 234, 2, // Opcode: CLGRBAsmE -/* 17596 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17605 -/* 17600 */ MCD_OPC_Decode, 179, 6, 234, 2, // Opcode: CLGRBAsmHE -/* 17605 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17614 -/* 17609 */ MCD_OPC_Decode, 181, 6, 234, 2, // Opcode: CLGRBAsmLE -/* 17614 */ MCD_OPC_Decode, 176, 6, 235, 2, // Opcode: CLGRBAsm -/* 17619 */ MCD_OPC_FilterValue, 246, 1, 69, 0, // Skip to: 17693 -/* 17624 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17627 */ MCD_OPC_FilterValue, 0, 180, 5, // Skip to: 19091 -/* 17631 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17634 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17643 -/* 17638 */ MCD_OPC_Decode, 218, 7, 236, 2, // Opcode: CRBAsmH -/* 17643 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17652 -/* 17647 */ MCD_OPC_Decode, 220, 7, 236, 2, // Opcode: CRBAsmL -/* 17652 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17661 -/* 17656 */ MCD_OPC_Decode, 222, 7, 236, 2, // Opcode: CRBAsmLH -/* 17661 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17670 -/* 17665 */ MCD_OPC_Decode, 217, 7, 236, 2, // Opcode: CRBAsmE -/* 17670 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17679 -/* 17674 */ MCD_OPC_Decode, 219, 7, 236, 2, // Opcode: CRBAsmHE -/* 17679 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17688 -/* 17683 */ MCD_OPC_Decode, 221, 7, 236, 2, // Opcode: CRBAsmLE -/* 17688 */ MCD_OPC_Decode, 216, 7, 237, 2, // Opcode: CRBAsm -/* 17693 */ MCD_OPC_FilterValue, 247, 1, 69, 0, // Skip to: 17767 -/* 17698 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... -/* 17701 */ MCD_OPC_FilterValue, 0, 106, 5, // Skip to: 19091 -/* 17705 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 17708 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17717 -/* 17712 */ MCD_OPC_Decode, 149, 7, 236, 2, // Opcode: CLRBAsmH -/* 17717 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17726 -/* 17721 */ MCD_OPC_Decode, 151, 7, 236, 2, // Opcode: CLRBAsmL -/* 17726 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17735 -/* 17730 */ MCD_OPC_Decode, 153, 7, 236, 2, // Opcode: CLRBAsmLH -/* 17735 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17744 -/* 17739 */ MCD_OPC_Decode, 148, 7, 236, 2, // Opcode: CLRBAsmE -/* 17744 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17753 -/* 17748 */ MCD_OPC_Decode, 150, 7, 236, 2, // Opcode: CLRBAsmHE -/* 17753 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17762 -/* 17757 */ MCD_OPC_Decode, 152, 7, 236, 2, // Opcode: CLRBAsmLE -/* 17762 */ MCD_OPC_Decode, 147, 7, 237, 2, // Opcode: CLRBAsm -/* 17767 */ MCD_OPC_FilterValue, 252, 1, 62, 0, // Skip to: 17834 -/* 17772 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17775 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17784 -/* 17779 */ MCD_OPC_Decode, 211, 4, 238, 2, // Opcode: CGIBAsmH -/* 17784 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17793 -/* 17788 */ MCD_OPC_Decode, 213, 4, 238, 2, // Opcode: CGIBAsmL -/* 17793 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17802 -/* 17797 */ MCD_OPC_Decode, 215, 4, 238, 2, // Opcode: CGIBAsmLH -/* 17802 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17811 -/* 17806 */ MCD_OPC_Decode, 210, 4, 238, 2, // Opcode: CGIBAsmE -/* 17811 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17820 -/* 17815 */ MCD_OPC_Decode, 212, 4, 238, 2, // Opcode: CGIBAsmHE -/* 17820 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17829 -/* 17824 */ MCD_OPC_Decode, 214, 4, 238, 2, // Opcode: CGIBAsmLE -/* 17829 */ MCD_OPC_Decode, 209, 4, 239, 2, // Opcode: CGIBAsm -/* 17834 */ MCD_OPC_FilterValue, 253, 1, 62, 0, // Skip to: 17901 -/* 17839 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17842 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17851 -/* 17846 */ MCD_OPC_Decode, 135, 6, 240, 2, // Opcode: CLGIBAsmH -/* 17851 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17860 -/* 17855 */ MCD_OPC_Decode, 137, 6, 240, 2, // Opcode: CLGIBAsmL -/* 17860 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17869 -/* 17864 */ MCD_OPC_Decode, 139, 6, 240, 2, // Opcode: CLGIBAsmLH -/* 17869 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17878 -/* 17873 */ MCD_OPC_Decode, 134, 6, 240, 2, // Opcode: CLGIBAsmE -/* 17878 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17887 -/* 17882 */ MCD_OPC_Decode, 136, 6, 240, 2, // Opcode: CLGIBAsmHE -/* 17887 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17896 -/* 17891 */ MCD_OPC_Decode, 138, 6, 240, 2, // Opcode: CLGIBAsmLE -/* 17896 */ MCD_OPC_Decode, 133, 6, 241, 2, // Opcode: CLGIBAsm -/* 17901 */ MCD_OPC_FilterValue, 254, 1, 62, 0, // Skip to: 17968 -/* 17906 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17909 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17918 -/* 17913 */ MCD_OPC_Decode, 183, 5, 242, 2, // Opcode: CIBAsmH -/* 17918 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17927 -/* 17922 */ MCD_OPC_Decode, 185, 5, 242, 2, // Opcode: CIBAsmL -/* 17927 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17936 -/* 17931 */ MCD_OPC_Decode, 187, 5, 242, 2, // Opcode: CIBAsmLH -/* 17936 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17945 -/* 17940 */ MCD_OPC_Decode, 182, 5, 242, 2, // Opcode: CIBAsmE -/* 17945 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17954 -/* 17949 */ MCD_OPC_Decode, 184, 5, 242, 2, // Opcode: CIBAsmHE -/* 17954 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17963 -/* 17958 */ MCD_OPC_Decode, 186, 5, 242, 2, // Opcode: CIBAsmLE -/* 17963 */ MCD_OPC_Decode, 181, 5, 243, 2, // Opcode: CIBAsm -/* 17968 */ MCD_OPC_FilterValue, 255, 1, 94, 4, // Skip to: 19091 -/* 17973 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... -/* 17976 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17985 -/* 17980 */ MCD_OPC_Decode, 243, 6, 244, 2, // Opcode: CLIBAsmH -/* 17985 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17994 -/* 17989 */ MCD_OPC_Decode, 245, 6, 244, 2, // Opcode: CLIBAsmL -/* 17994 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 18003 -/* 17998 */ MCD_OPC_Decode, 247, 6, 244, 2, // Opcode: CLIBAsmLH -/* 18003 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 18012 -/* 18007 */ MCD_OPC_Decode, 242, 6, 244, 2, // Opcode: CLIBAsmE -/* 18012 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 18021 -/* 18016 */ MCD_OPC_Decode, 244, 6, 244, 2, // Opcode: CLIBAsmHE -/* 18021 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 18030 -/* 18025 */ MCD_OPC_Decode, 246, 6, 244, 2, // Opcode: CLIBAsmLE -/* 18030 */ MCD_OPC_Decode, 241, 6, 245, 2, // Opcode: CLIBAsm -/* 18035 */ MCD_OPC_FilterValue, 237, 1, 163, 3, // Skip to: 18971 -/* 18040 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 18043 */ MCD_OPC_FilterValue, 4, 11, 0, // Skip to: 18058 -/* 18047 */ MCD_OPC_CheckField, 8, 8, 0, 14, 4, // Skip to: 19091 -/* 18053 */ MCD_OPC_Decode, 149, 10, 246, 2, // Opcode: LDEB -/* 18058 */ MCD_OPC_FilterValue, 5, 11, 0, // Skip to: 18073 -/* 18062 */ MCD_OPC_CheckField, 8, 8, 0, 255, 3, // Skip to: 19091 -/* 18068 */ MCD_OPC_Decode, 235, 12, 247, 2, // Opcode: LXDB -/* 18073 */ MCD_OPC_FilterValue, 6, 11, 0, // Skip to: 18088 -/* 18077 */ MCD_OPC_CheckField, 8, 8, 0, 240, 3, // Skip to: 19091 -/* 18083 */ MCD_OPC_Decode, 240, 12, 247, 2, // Opcode: LXEB -/* 18088 */ MCD_OPC_FilterValue, 7, 11, 0, // Skip to: 18103 -/* 18092 */ MCD_OPC_CheckField, 8, 8, 0, 225, 3, // Skip to: 19091 -/* 18098 */ MCD_OPC_Decode, 214, 13, 248, 2, // Opcode: MXDB -/* 18103 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 18118 -/* 18107 */ MCD_OPC_CheckField, 8, 8, 0, 210, 3, // Skip to: 19091 -/* 18113 */ MCD_OPC_Decode, 223, 9, 249, 2, // Opcode: KEB -/* 18118 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 18133 -/* 18122 */ MCD_OPC_CheckField, 8, 8, 0, 195, 3, // Skip to: 19091 -/* 18128 */ MCD_OPC_Decode, 165, 4, 249, 2, // Opcode: CEB -/* 18133 */ MCD_OPC_FilterValue, 10, 11, 0, // Skip to: 18148 -/* 18137 */ MCD_OPC_CheckField, 8, 8, 0, 180, 3, // Skip to: 19091 -/* 18143 */ MCD_OPC_Decode, 236, 2, 250, 2, // Opcode: AEB -/* 18148 */ MCD_OPC_FilterValue, 11, 11, 0, // Skip to: 18163 -/* 18152 */ MCD_OPC_CheckField, 8, 8, 0, 165, 3, // Skip to: 19091 -/* 18158 */ MCD_OPC_Decode, 197, 14, 250, 2, // Opcode: SEB -/* 18163 */ MCD_OPC_FilterValue, 12, 11, 0, // Skip to: 18178 -/* 18167 */ MCD_OPC_CheckField, 8, 8, 0, 150, 3, // Skip to: 19091 -/* 18173 */ MCD_OPC_Decode, 142, 13, 251, 2, // Opcode: MDEB -/* 18178 */ MCD_OPC_FilterValue, 13, 11, 0, // Skip to: 18193 -/* 18182 */ MCD_OPC_CheckField, 8, 8, 0, 135, 3, // Skip to: 19091 -/* 18188 */ MCD_OPC_Decode, 195, 8, 250, 2, // Opcode: DEB -/* 18193 */ MCD_OPC_FilterValue, 14, 11, 0, // Skip to: 18208 -/* 18197 */ MCD_OPC_CheckField, 8, 4, 0, 120, 3, // Skip to: 19091 -/* 18203 */ MCD_OPC_Decode, 128, 13, 252, 2, // Opcode: MAEB -/* 18208 */ MCD_OPC_FilterValue, 15, 11, 0, // Skip to: 18223 -/* 18212 */ MCD_OPC_CheckField, 8, 4, 0, 105, 3, // Skip to: 19091 -/* 18218 */ MCD_OPC_Decode, 176, 13, 252, 2, // Opcode: MSEB -/* 18223 */ MCD_OPC_FilterValue, 16, 11, 0, // Skip to: 18238 -/* 18227 */ MCD_OPC_CheckField, 8, 8, 0, 90, 3, // Skip to: 19091 -/* 18233 */ MCD_OPC_Decode, 164, 16, 249, 2, // Opcode: TCEB -/* 18238 */ MCD_OPC_FilterValue, 17, 11, 0, // Skip to: 18253 -/* 18242 */ MCD_OPC_CheckField, 8, 8, 0, 75, 3, // Skip to: 19091 -/* 18248 */ MCD_OPC_Decode, 163, 16, 246, 2, // Opcode: TCDB -/* 18253 */ MCD_OPC_FilterValue, 18, 11, 0, // Skip to: 18268 -/* 18257 */ MCD_OPC_CheckField, 8, 8, 0, 60, 3, // Skip to: 19091 -/* 18263 */ MCD_OPC_Decode, 165, 16, 247, 2, // Opcode: TCXB -/* 18268 */ MCD_OPC_FilterValue, 20, 11, 0, // Skip to: 18283 -/* 18272 */ MCD_OPC_CheckField, 8, 8, 0, 45, 3, // Skip to: 19091 -/* 18278 */ MCD_OPC_Decode, 253, 14, 249, 2, // Opcode: SQEB -/* 18283 */ MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 18298 -/* 18287 */ MCD_OPC_CheckField, 8, 8, 0, 30, 3, // Skip to: 19091 -/* 18293 */ MCD_OPC_Decode, 249, 14, 246, 2, // Opcode: SQDB -/* 18298 */ MCD_OPC_FilterValue, 23, 11, 0, // Skip to: 18313 -/* 18302 */ MCD_OPC_CheckField, 8, 8, 0, 15, 3, // Skip to: 19091 -/* 18308 */ MCD_OPC_Decode, 150, 13, 250, 2, // Opcode: MEEB -/* 18313 */ MCD_OPC_FilterValue, 24, 11, 0, // Skip to: 18328 -/* 18317 */ MCD_OPC_CheckField, 8, 8, 0, 0, 3, // Skip to: 19091 -/* 18323 */ MCD_OPC_Decode, 220, 9, 246, 2, // Opcode: KDB -/* 18328 */ MCD_OPC_FilterValue, 25, 11, 0, // Skip to: 18343 -/* 18332 */ MCD_OPC_CheckField, 8, 8, 0, 241, 2, // Skip to: 19091 -/* 18338 */ MCD_OPC_Decode, 140, 4, 246, 2, // Opcode: CDB -/* 18343 */ MCD_OPC_FilterValue, 26, 11, 0, // Skip to: 18358 -/* 18347 */ MCD_OPC_CheckField, 8, 8, 0, 226, 2, // Skip to: 19091 -/* 18353 */ MCD_OPC_Decode, 230, 2, 251, 2, // Opcode: ADB -/* 18358 */ MCD_OPC_FilterValue, 27, 11, 0, // Skip to: 18373 -/* 18362 */ MCD_OPC_CheckField, 8, 8, 0, 211, 2, // Skip to: 19091 -/* 18368 */ MCD_OPC_Decode, 191, 14, 251, 2, // Opcode: SDB -/* 18373 */ MCD_OPC_FilterValue, 28, 11, 0, // Skip to: 18388 -/* 18377 */ MCD_OPC_CheckField, 8, 8, 0, 196, 2, // Skip to: 19091 -/* 18383 */ MCD_OPC_Decode, 139, 13, 251, 2, // Opcode: MDB -/* 18388 */ MCD_OPC_FilterValue, 29, 11, 0, // Skip to: 18403 -/* 18392 */ MCD_OPC_CheckField, 8, 8, 0, 181, 2, // Skip to: 19091 -/* 18398 */ MCD_OPC_Decode, 189, 8, 251, 2, // Opcode: DDB -/* 18403 */ MCD_OPC_FilterValue, 30, 11, 0, // Skip to: 18418 -/* 18407 */ MCD_OPC_CheckField, 8, 4, 0, 166, 2, // Skip to: 19091 -/* 18413 */ MCD_OPC_Decode, 252, 12, 253, 2, // Opcode: MADB -/* 18418 */ MCD_OPC_FilterValue, 31, 11, 0, // Skip to: 18433 -/* 18422 */ MCD_OPC_CheckField, 8, 4, 0, 151, 2, // Skip to: 19091 -/* 18428 */ MCD_OPC_Decode, 172, 13, 253, 2, // Opcode: MSDB -/* 18433 */ MCD_OPC_FilterValue, 36, 11, 0, // Skip to: 18448 -/* 18437 */ MCD_OPC_CheckField, 8, 8, 0, 136, 2, // Skip to: 19091 -/* 18443 */ MCD_OPC_Decode, 147, 10, 246, 2, // Opcode: LDE -/* 18448 */ MCD_OPC_FilterValue, 37, 11, 0, // Skip to: 18463 -/* 18452 */ MCD_OPC_CheckField, 8, 8, 0, 121, 2, // Skip to: 19091 -/* 18458 */ MCD_OPC_Decode, 234, 12, 247, 2, // Opcode: LXD -/* 18463 */ MCD_OPC_FilterValue, 38, 11, 0, // Skip to: 18478 -/* 18467 */ MCD_OPC_CheckField, 8, 8, 0, 106, 2, // Skip to: 19091 -/* 18473 */ MCD_OPC_Decode, 239, 12, 247, 2, // Opcode: LXE -/* 18478 */ MCD_OPC_FilterValue, 46, 11, 0, // Skip to: 18493 -/* 18482 */ MCD_OPC_CheckField, 8, 4, 0, 91, 2, // Skip to: 19091 -/* 18488 */ MCD_OPC_Decode, 255, 12, 252, 2, // Opcode: MAE -/* 18493 */ MCD_OPC_FilterValue, 47, 11, 0, // Skip to: 18508 -/* 18497 */ MCD_OPC_CheckField, 8, 4, 0, 76, 2, // Skip to: 19091 -/* 18503 */ MCD_OPC_Decode, 175, 13, 252, 2, // Opcode: MSE -/* 18508 */ MCD_OPC_FilterValue, 52, 11, 0, // Skip to: 18523 -/* 18512 */ MCD_OPC_CheckField, 8, 8, 0, 61, 2, // Skip to: 19091 -/* 18518 */ MCD_OPC_Decode, 252, 14, 249, 2, // Opcode: SQE -/* 18523 */ MCD_OPC_FilterValue, 53, 11, 0, // Skip to: 18538 -/* 18527 */ MCD_OPC_CheckField, 8, 8, 0, 46, 2, // Skip to: 19091 -/* 18533 */ MCD_OPC_Decode, 248, 14, 246, 2, // Opcode: SQD -/* 18538 */ MCD_OPC_FilterValue, 55, 11, 0, // Skip to: 18553 -/* 18542 */ MCD_OPC_CheckField, 8, 8, 0, 31, 2, // Skip to: 19091 -/* 18548 */ MCD_OPC_Decode, 149, 13, 250, 2, // Opcode: MEE -/* 18553 */ MCD_OPC_FilterValue, 56, 11, 0, // Skip to: 18568 -/* 18557 */ MCD_OPC_CheckField, 8, 4, 0, 16, 2, // Skip to: 19091 -/* 18563 */ MCD_OPC_Decode, 134, 13, 253, 2, // Opcode: MAYL -/* 18568 */ MCD_OPC_FilterValue, 57, 11, 0, // Skip to: 18583 -/* 18572 */ MCD_OPC_CheckField, 8, 4, 0, 1, 2, // Skip to: 19091 -/* 18578 */ MCD_OPC_Decode, 223, 13, 254, 2, // Opcode: MYL -/* 18583 */ MCD_OPC_FilterValue, 58, 11, 0, // Skip to: 18598 -/* 18587 */ MCD_OPC_CheckField, 8, 4, 0, 242, 1, // Skip to: 19091 -/* 18593 */ MCD_OPC_Decode, 131, 13, 255, 2, // Opcode: MAY -/* 18598 */ MCD_OPC_FilterValue, 59, 11, 0, // Skip to: 18613 -/* 18602 */ MCD_OPC_CheckField, 8, 4, 0, 227, 1, // Skip to: 19091 -/* 18608 */ MCD_OPC_Decode, 220, 13, 128, 3, // Opcode: MY -/* 18613 */ MCD_OPC_FilterValue, 60, 11, 0, // Skip to: 18628 -/* 18617 */ MCD_OPC_CheckField, 8, 4, 0, 212, 1, // Skip to: 19091 -/* 18623 */ MCD_OPC_Decode, 132, 13, 253, 2, // Opcode: MAYH -/* 18628 */ MCD_OPC_FilterValue, 61, 11, 0, // Skip to: 18643 -/* 18632 */ MCD_OPC_CheckField, 8, 4, 0, 197, 1, // Skip to: 19091 -/* 18638 */ MCD_OPC_Decode, 221, 13, 254, 2, // Opcode: MYH -/* 18643 */ MCD_OPC_FilterValue, 62, 11, 0, // Skip to: 18658 -/* 18647 */ MCD_OPC_CheckField, 8, 4, 0, 182, 1, // Skip to: 19091 -/* 18653 */ MCD_OPC_Decode, 251, 12, 253, 2, // Opcode: MAD -/* 18658 */ MCD_OPC_FilterValue, 63, 11, 0, // Skip to: 18673 -/* 18662 */ MCD_OPC_CheckField, 8, 4, 0, 167, 1, // Skip to: 19091 -/* 18668 */ MCD_OPC_Decode, 171, 13, 253, 2, // Opcode: MSD -/* 18673 */ MCD_OPC_FilterValue, 64, 11, 0, // Skip to: 18688 -/* 18677 */ MCD_OPC_CheckField, 8, 4, 0, 152, 1, // Skip to: 19091 -/* 18683 */ MCD_OPC_Decode, 225, 14, 254, 2, // Opcode: SLDT -/* 18688 */ MCD_OPC_FilterValue, 65, 11, 0, // Skip to: 18703 -/* 18692 */ MCD_OPC_CheckField, 8, 4, 0, 137, 1, // Skip to: 19091 -/* 18698 */ MCD_OPC_Decode, 136, 15, 254, 2, // Opcode: SRDT -/* 18703 */ MCD_OPC_FilterValue, 72, 11, 0, // Skip to: 18718 -/* 18707 */ MCD_OPC_CheckField, 8, 4, 0, 122, 1, // Skip to: 19091 -/* 18713 */ MCD_OPC_Decode, 240, 14, 129, 3, // Opcode: SLXT -/* 18718 */ MCD_OPC_FilterValue, 73, 11, 0, // Skip to: 18733 -/* 18722 */ MCD_OPC_CheckField, 8, 4, 0, 107, 1, // Skip to: 19091 -/* 18728 */ MCD_OPC_Decode, 147, 15, 129, 3, // Opcode: SRXT -/* 18733 */ MCD_OPC_FilterValue, 80, 11, 0, // Skip to: 18748 -/* 18737 */ MCD_OPC_CheckField, 8, 8, 0, 92, 1, // Skip to: 19091 -/* 18743 */ MCD_OPC_Decode, 167, 16, 249, 2, // Opcode: TDCET -/* 18748 */ MCD_OPC_FilterValue, 81, 11, 0, // Skip to: 18763 -/* 18752 */ MCD_OPC_CheckField, 8, 8, 0, 77, 1, // Skip to: 19091 -/* 18758 */ MCD_OPC_Decode, 170, 16, 249, 2, // Opcode: TDGET -/* 18763 */ MCD_OPC_FilterValue, 84, 11, 0, // Skip to: 18778 -/* 18767 */ MCD_OPC_CheckField, 8, 8, 0, 62, 1, // Skip to: 19091 -/* 18773 */ MCD_OPC_Decode, 166, 16, 246, 2, // Opcode: TDCDT -/* 18778 */ MCD_OPC_FilterValue, 85, 11, 0, // Skip to: 18793 -/* 18782 */ MCD_OPC_CheckField, 8, 8, 0, 47, 1, // Skip to: 19091 -/* 18788 */ MCD_OPC_Decode, 169, 16, 246, 2, // Opcode: TDGDT -/* 18793 */ MCD_OPC_FilterValue, 88, 11, 0, // Skip to: 18808 -/* 18797 */ MCD_OPC_CheckField, 8, 8, 0, 32, 1, // Skip to: 19091 -/* 18803 */ MCD_OPC_Decode, 168, 16, 247, 2, // Opcode: TDCXT -/* 18808 */ MCD_OPC_FilterValue, 89, 11, 0, // Skip to: 18823 -/* 18812 */ MCD_OPC_CheckField, 8, 8, 0, 17, 1, // Skip to: 19091 -/* 18818 */ MCD_OPC_Decode, 171, 16, 247, 2, // Opcode: TDGXT -/* 18823 */ MCD_OPC_FilterValue, 100, 5, 0, // Skip to: 18832 -/* 18827 */ MCD_OPC_Decode, 170, 10, 130, 3, // Opcode: LEY -/* 18832 */ MCD_OPC_FilterValue, 101, 5, 0, // Skip to: 18841 -/* 18836 */ MCD_OPC_Decode, 160, 10, 131, 3, // Opcode: LDY -/* 18841 */ MCD_OPC_FilterValue, 102, 5, 0, // Skip to: 18850 -/* 18845 */ MCD_OPC_Decode, 175, 15, 130, 3, // Opcode: STEY -/* 18850 */ MCD_OPC_FilterValue, 103, 5, 0, // Skip to: 18859 -/* 18854 */ MCD_OPC_Decode, 173, 15, 131, 3, // Opcode: STDY -/* 18859 */ MCD_OPC_FilterValue, 168, 1, 9, 0, // Skip to: 18873 -/* 18864 */ MCD_OPC_CheckPredicate, 25, 223, 0, // Skip to: 19091 -/* 18868 */ MCD_OPC_Decode, 185, 8, 132, 3, // Opcode: CZDT -/* 18873 */ MCD_OPC_FilterValue, 169, 1, 9, 0, // Skip to: 18887 -/* 18878 */ MCD_OPC_CheckPredicate, 25, 209, 0, // Skip to: 19091 -/* 18882 */ MCD_OPC_Decode, 186, 8, 133, 3, // Opcode: CZXT -/* 18887 */ MCD_OPC_FilterValue, 170, 1, 9, 0, // Skip to: 18901 -/* 18892 */ MCD_OPC_CheckPredicate, 25, 195, 0, // Skip to: 19091 -/* 18896 */ MCD_OPC_Decode, 163, 4, 132, 3, // Opcode: CDZT -/* 18901 */ MCD_OPC_FilterValue, 171, 1, 9, 0, // Skip to: 18915 -/* 18906 */ MCD_OPC_CheckPredicate, 25, 181, 0, // Skip to: 19091 -/* 18910 */ MCD_OPC_Decode, 183, 8, 133, 3, // Opcode: CXZT -/* 18915 */ MCD_OPC_FilterValue, 172, 1, 9, 0, // Skip to: 18929 -/* 18920 */ MCD_OPC_CheckPredicate, 26, 167, 0, // Skip to: 19091 -/* 18924 */ MCD_OPC_Decode, 207, 7, 132, 3, // Opcode: CPDT -/* 18929 */ MCD_OPC_FilterValue, 173, 1, 9, 0, // Skip to: 18943 -/* 18934 */ MCD_OPC_CheckPredicate, 26, 153, 0, // Skip to: 19091 -/* 18938 */ MCD_OPC_Decode, 212, 7, 133, 3, // Opcode: CPXT -/* 18943 */ MCD_OPC_FilterValue, 174, 1, 9, 0, // Skip to: 18957 -/* 18948 */ MCD_OPC_CheckPredicate, 26, 139, 0, // Skip to: 19091 -/* 18952 */ MCD_OPC_Decode, 155, 4, 132, 3, // Opcode: CDPT -/* 18957 */ MCD_OPC_FilterValue, 175, 1, 129, 0, // Skip to: 19091 -/* 18962 */ MCD_OPC_CheckPredicate, 26, 125, 0, // Skip to: 19091 -/* 18966 */ MCD_OPC_Decode, 178, 8, 133, 3, // Opcode: CXPT -/* 18971 */ MCD_OPC_FilterValue, 238, 1, 5, 0, // Skip to: 18981 -/* 18976 */ MCD_OPC_Decode, 145, 14, 134, 3, // Opcode: PLO -/* 18981 */ MCD_OPC_FilterValue, 239, 1, 5, 0, // Skip to: 18991 -/* 18986 */ MCD_OPC_Decode, 226, 10, 135, 3, // Opcode: LMD -/* 18991 */ MCD_OPC_FilterValue, 240, 1, 5, 0, // Skip to: 19001 -/* 18996 */ MCD_OPC_Decode, 144, 15, 136, 3, // Opcode: SRP -/* 19001 */ MCD_OPC_FilterValue, 241, 1, 5, 0, // Skip to: 19011 -/* 19006 */ MCD_OPC_Decode, 208, 13, 137, 3, // Opcode: MVO -/* 19011 */ MCD_OPC_FilterValue, 242, 1, 5, 0, // Skip to: 19021 -/* 19016 */ MCD_OPC_Decode, 132, 14, 137, 3, // Opcode: PACK -/* 19021 */ MCD_OPC_FilterValue, 243, 1, 5, 0, // Skip to: 19031 -/* 19026 */ MCD_OPC_Decode, 206, 16, 137, 3, // Opcode: UNPK -/* 19031 */ MCD_OPC_FilterValue, 248, 1, 5, 0, // Skip to: 19041 -/* 19036 */ MCD_OPC_Decode, 239, 21, 137, 3, // Opcode: ZAP -/* 19041 */ MCD_OPC_FilterValue, 249, 1, 5, 0, // Skip to: 19051 -/* 19046 */ MCD_OPC_Decode, 206, 7, 137, 3, // Opcode: CP -/* 19051 */ MCD_OPC_FilterValue, 250, 1, 5, 0, // Skip to: 19061 -/* 19056 */ MCD_OPC_Decode, 152, 3, 137, 3, // Opcode: AP -/* 19061 */ MCD_OPC_FilterValue, 251, 1, 5, 0, // Skip to: 19071 -/* 19066 */ MCD_OPC_Decode, 242, 14, 137, 3, // Opcode: SP -/* 19071 */ MCD_OPC_FilterValue, 252, 1, 5, 0, // Skip to: 19081 -/* 19076 */ MCD_OPC_Decode, 166, 13, 137, 3, // Opcode: MP -/* 19081 */ MCD_OPC_FilterValue, 253, 1, 5, 0, // Skip to: 19091 -/* 19086 */ MCD_OPC_Decode, 205, 8, 137, 3, // Opcode: DP -/* 19091 */ MCD_OPC_Fail, - 0 -}; - -static bool getbool(uint64_t b) -{ - return b != 0; -} + /* 0 */ MCD_OPC_ExtractField, + 40, + 8, // Inst{47-40} ... + /* 3 */ MCD_OPC_FilterValue, + 192, + 1, + 40, + 1, + 0, // Skip to: 305 + /* 9 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 12 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 22 + /* 17 */ MCD_OPC_Decode, + 154, + 11, + 174, + 1, // Opcode: LARL + /* 22 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 32 + /* 27 */ MCD_OPC_Decode, + 214, + 11, + 175, + 1, // Opcode: LGFI + /* 32 */ MCD_OPC_FilterValue, + 4, + 158, + 0, + 0, // Skip to: 195 + /* 37 */ MCD_OPC_ExtractField, + 36, + 4, // Inst{39-36} ... + /* 40 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 50 + /* 45 */ MCD_OPC_Decode, + 248, + 10, + 176, + 1, // Opcode: JGAsmO + /* 50 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 60 + /* 55 */ MCD_OPC_Decode, + 232, + 10, + 176, + 1, // Opcode: JGAsmH + /* 60 */ MCD_OPC_FilterValue, + 3, + 5, + 0, + 0, // Skip to: 70 + /* 65 */ MCD_OPC_Decode, + 242, + 10, + 176, + 1, // Opcode: JGAsmNLE + /* 70 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 80 + /* 75 */ MCD_OPC_Decode, + 234, + 10, + 176, + 1, // Opcode: JGAsmL + /* 80 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 90 + /* 85 */ MCD_OPC_Decode, + 240, + 10, + 176, + 1, // Opcode: JGAsmNHE + /* 90 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 100 + /* 95 */ MCD_OPC_Decode, + 236, + 10, + 176, + 1, // Opcode: JGAsmLH + /* 100 */ MCD_OPC_FilterValue, + 7, + 5, + 0, + 0, // Skip to: 110 + /* 105 */ MCD_OPC_Decode, + 238, + 10, + 176, + 1, // Opcode: JGAsmNE + /* 110 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 120 + /* 115 */ MCD_OPC_Decode, + 231, + 10, + 176, + 1, // Opcode: JGAsmE + /* 120 */ MCD_OPC_FilterValue, + 9, + 5, + 0, + 0, // Skip to: 130 + /* 125 */ MCD_OPC_Decode, + 243, + 10, + 176, + 1, // Opcode: JGAsmNLH + /* 130 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 140 + /* 135 */ MCD_OPC_Decode, + 233, + 10, + 176, + 1, // Opcode: JGAsmHE + /* 140 */ MCD_OPC_FilterValue, + 11, + 5, + 0, + 0, // Skip to: 150 + /* 145 */ MCD_OPC_Decode, + 241, + 10, + 176, + 1, // Opcode: JGAsmNL + /* 150 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 160 + /* 155 */ MCD_OPC_Decode, + 235, + 10, + 176, + 1, // Opcode: JGAsmLE + /* 160 */ MCD_OPC_FilterValue, + 13, + 5, + 0, + 0, // Skip to: 170 + /* 165 */ MCD_OPC_Decode, + 239, + 10, + 176, + 1, // Opcode: JGAsmNH + /* 170 */ MCD_OPC_FilterValue, + 14, + 5, + 0, + 0, // Skip to: 180 + /* 175 */ MCD_OPC_Decode, + 245, + 10, + 176, + 1, // Opcode: JGAsmNO + /* 180 */ MCD_OPC_FilterValue, + 15, + 5, + 0, + 0, // Skip to: 190 + /* 185 */ MCD_OPC_Decode, + 230, + 10, + 176, + 1, // Opcode: JG + /* 190 */ MCD_OPC_Decode, + 147, + 5, + 177, + 1, // Opcode: BRCLAsm + /* 195 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 205 + /* 200 */ MCD_OPC_Decode, + 251, + 4, + 178, + 1, // Opcode: BRASL + /* 205 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 215 + /* 210 */ MCD_OPC_Decode, + 171, + 24, + 179, + 1, // Opcode: XIHF + /* 215 */ MCD_OPC_FilterValue, + 7, + 5, + 0, + 0, // Skip to: 225 + /* 220 */ MCD_OPC_Decode, + 172, + 24, + 180, + 1, // Opcode: XILF + /* 225 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 235 + /* 230 */ MCD_OPC_Decode, + 164, + 10, + 181, + 1, // Opcode: IIHF + /* 235 */ MCD_OPC_FilterValue, + 9, + 5, + 0, + 0, // Skip to: 245 + /* 240 */ MCD_OPC_Decode, + 167, + 10, + 182, + 1, // Opcode: IILF + /* 245 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 255 + /* 250 */ MCD_OPC_Decode, + 142, + 15, + 179, + 1, // Opcode: NIHF + /* 255 */ MCD_OPC_FilterValue, + 11, + 5, + 0, + 0, // Skip to: 265 + /* 260 */ MCD_OPC_Decode, + 145, + 15, + 180, + 1, // Opcode: NILF + /* 265 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 275 + /* 270 */ MCD_OPC_Decode, + 169, + 15, + 179, + 1, // Opcode: OIHF + /* 275 */ MCD_OPC_FilterValue, + 13, + 5, + 0, + 0, // Skip to: 285 + /* 280 */ MCD_OPC_Decode, + 172, + 15, + 180, + 1, // Opcode: OILF + /* 285 */ MCD_OPC_FilterValue, + 14, + 5, + 0, + 0, // Skip to: 295 + /* 290 */ MCD_OPC_Decode, + 251, + 11, + 183, + 1, // Opcode: LLIHF + /* 295 */ MCD_OPC_FilterValue, + 15, + 160, + 89, + 0, // Skip to: 23244 + /* 300 */ MCD_OPC_Decode, + 254, + 11, + 183, + 1, // Opcode: LLILF + /* 305 */ MCD_OPC_FilterValue, + 194, + 1, + 123, + 0, + 0, // Skip to: 434 + /* 311 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 314 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 324 + /* 319 */ MCD_OPC_Decode, + 217, + 14, + 184, + 1, // Opcode: MSGFI + /* 324 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 334 + /* 329 */ MCD_OPC_Decode, + 213, + 14, + 185, + 1, // Opcode: MSFI + /* 334 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 344 + /* 339 */ MCD_OPC_Decode, + 218, + 16, + 186, + 1, // Opcode: SLGFI + /* 344 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 354 + /* 349 */ MCD_OPC_Decode, + 215, + 16, + 180, + 1, // Opcode: SLFI + /* 354 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 364 + /* 359 */ MCD_OPC_Decode, + 138, + 4, + 184, + 1, // Opcode: AGFI + /* 364 */ MCD_OPC_FilterValue, + 9, + 5, + 0, + 0, // Skip to: 374 + /* 369 */ MCD_OPC_Decode, + 135, + 4, + 185, + 1, // Opcode: AFI + /* 374 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 384 + /* 379 */ MCD_OPC_Decode, + 161, + 4, + 186, + 1, // Opcode: ALGFI + /* 384 */ MCD_OPC_FilterValue, + 11, + 5, + 0, + 0, // Skip to: 394 + /* 389 */ MCD_OPC_Decode, + 158, + 4, + 180, + 1, // Opcode: ALFI + /* 394 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 404 + /* 399 */ MCD_OPC_Decode, + 225, + 5, + 175, + 1, // Opcode: CGFI + /* 404 */ MCD_OPC_FilterValue, + 13, + 5, + 0, + 0, // Skip to: 414 + /* 409 */ MCD_OPC_Decode, + 210, + 5, + 187, + 1, // Opcode: CFI + /* 414 */ MCD_OPC_FilterValue, + 14, + 5, + 0, + 0, // Skip to: 424 + /* 419 */ MCD_OPC_Decode, + 151, + 7, + 183, + 1, // Opcode: CLGFI + /* 424 */ MCD_OPC_FilterValue, + 15, + 31, + 89, + 0, // Skip to: 23244 + /* 429 */ MCD_OPC_Decode, + 129, + 7, + 182, + 1, // Opcode: CLFI + /* 434 */ MCD_OPC_FilterValue, + 196, + 1, + 113, + 0, + 0, // Skip to: 553 + /* 440 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 443 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 453 + /* 448 */ MCD_OPC_Decode, + 250, + 11, + 188, + 1, // Opcode: LLHRL + /* 453 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 463 + /* 458 */ MCD_OPC_Decode, + 221, + 11, + 174, + 1, // Opcode: LGHRL + /* 463 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 473 + /* 468 */ MCD_OPC_Decode, + 229, + 11, + 188, + 1, // Opcode: LHRL + /* 473 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 483 + /* 478 */ MCD_OPC_Decode, + 243, + 11, + 174, + 1, // Opcode: LLGHRL + /* 483 */ MCD_OPC_FilterValue, + 7, + 5, + 0, + 0, // Skip to: 493 + /* 488 */ MCD_OPC_Decode, + 176, + 17, + 188, + 1, // Opcode: STHRL + /* 493 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 503 + /* 498 */ MCD_OPC_Decode, + 223, + 11, + 174, + 1, // Opcode: LGRL + /* 503 */ MCD_OPC_FilterValue, + 11, + 5, + 0, + 0, // Skip to: 513 + /* 508 */ MCD_OPC_Decode, + 172, + 17, + 174, + 1, // Opcode: STGRL + /* 513 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 523 + /* 518 */ MCD_OPC_Decode, + 216, + 11, + 174, + 1, // Opcode: LGFRL + /* 523 */ MCD_OPC_FilterValue, + 13, + 5, + 0, + 0, // Skip to: 533 + /* 528 */ MCD_OPC_Decode, + 242, + 13, + 188, + 1, // Opcode: LRL + /* 533 */ MCD_OPC_FilterValue, + 14, + 5, + 0, + 0, // Skip to: 543 + /* 538 */ MCD_OPC_Decode, + 239, + 11, + 174, + 1, // Opcode: LLGFRL + /* 543 */ MCD_OPC_FilterValue, + 15, + 168, + 88, + 0, // Skip to: 23244 + /* 548 */ MCD_OPC_Decode, + 255, + 17, + 188, + 1, // Opcode: STRL + /* 553 */ MCD_OPC_FilterValue, + 197, + 1, + 10, + 0, + 0, // Skip to: 569 + /* 559 */ MCD_OPC_CheckPredicate, + 5, + 152, + 88, + 0, // Skip to: 23244 + /* 564 */ MCD_OPC_Decode, + 248, + 4, + 189, + 1, // Opcode: BPRP + /* 569 */ MCD_OPC_FilterValue, + 198, + 1, + 123, + 0, + 0, // Skip to: 698 + /* 575 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 578 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 588 + /* 583 */ MCD_OPC_Decode, + 136, + 10, + 190, + 1, // Opcode: EXRL + /* 588 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 598 + /* 593 */ MCD_OPC_Decode, + 185, + 15, + 191, + 1, // Opcode: PFDRL + /* 598 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 608 + /* 603 */ MCD_OPC_Decode, + 230, + 5, + 174, + 1, // Opcode: CGHRL + /* 608 */ MCD_OPC_FilterValue, + 5, + 5, + 0, + 0, // Skip to: 618 + /* 613 */ MCD_OPC_Decode, + 201, + 6, + 188, + 1, // Opcode: CHRL + /* 618 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 628 + /* 623 */ MCD_OPC_Decode, + 154, + 7, + 174, + 1, // Opcode: CLGHRL + /* 628 */ MCD_OPC_FilterValue, + 7, + 5, + 0, + 0, // Skip to: 638 + /* 633 */ MCD_OPC_Decode, + 134, + 8, + 188, + 1, // Opcode: CLHRL + /* 638 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 648 + /* 643 */ MCD_OPC_Decode, + 175, + 6, + 174, + 1, // Opcode: CGRL + /* 648 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 658 + /* 653 */ MCD_OPC_Decode, + 227, + 7, + 174, + 1, // Opcode: CLGRL + /* 658 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 668 + /* 663 */ MCD_OPC_Decode, + 227, + 5, + 174, + 1, // Opcode: CGFRL + /* 668 */ MCD_OPC_FilterValue, + 13, + 5, + 0, + 0, // Skip to: 678 + /* 673 */ MCD_OPC_Decode, + 141, + 9, + 188, + 1, // Opcode: CRL + /* 678 */ MCD_OPC_FilterValue, + 14, + 5, + 0, + 0, // Skip to: 688 + /* 683 */ MCD_OPC_Decode, + 153, + 7, + 174, + 1, // Opcode: CLGFRL + /* 688 */ MCD_OPC_FilterValue, + 15, + 23, + 88, + 0, // Skip to: 23244 + /* 693 */ MCD_OPC_Decode, + 198, + 8, + 188, + 1, // Opcode: CLRL + /* 698 */ MCD_OPC_FilterValue, + 199, + 1, + 17, + 0, + 0, // Skip to: 721 + /* 704 */ MCD_OPC_CheckPredicate, + 5, + 7, + 88, + 0, // Skip to: 23244 + /* 709 */ MCD_OPC_CheckField, + 32, + 4, + 0, + 0, + 88, + 0, // Skip to: 23244 + /* 716 */ MCD_OPC_Decode, + 247, + 4, + 192, + 1, // Opcode: BPP + /* 721 */ MCD_OPC_FilterValue, + 200, + 1, + 63, + 0, + 0, // Skip to: 790 + /* 727 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 730 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 740 + /* 735 */ MCD_OPC_Decode, + 232, + 14, + 193, + 1, // Opcode: MVCOS + /* 740 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 750 + /* 745 */ MCD_OPC_Decode, + 244, + 9, + 193, + 1, // Opcode: ECTG + /* 750 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 760 + /* 755 */ MCD_OPC_Decode, + 162, + 9, + 193, + 1, // Opcode: CSST + /* 760 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 775 + /* 765 */ MCD_OPC_CheckPredicate, + 25, + 202, + 87, + 0, // Skip to: 23244 + /* 770 */ MCD_OPC_Decode, + 217, + 13, + 194, + 1, // Opcode: LPD + /* 775 */ MCD_OPC_FilterValue, + 5, + 192, + 87, + 0, // Skip to: 23244 + /* 780 */ MCD_OPC_CheckPredicate, + 25, + 187, + 87, + 0, // Skip to: 23244 + /* 785 */ MCD_OPC_Decode, + 221, + 13, + 194, + 1, // Opcode: LPDG + /* 790 */ MCD_OPC_FilterValue, + 204, + 1, + 93, + 0, + 0, // Skip to: 889 + /* 796 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 799 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 814 + /* 804 */ MCD_OPC_CheckPredicate, + 19, + 163, + 87, + 0, // Skip to: 23244 + /* 809 */ MCD_OPC_Decode, + 150, + 5, + 195, + 1, // Opcode: BRCTH + /* 814 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 829 + /* 819 */ MCD_OPC_CheckPredicate, + 19, + 148, + 87, + 0, // Skip to: 23244 + /* 824 */ MCD_OPC_Decode, + 152, + 4, + 196, + 1, // Opcode: AIH + /* 829 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 844 + /* 834 */ MCD_OPC_CheckPredicate, + 19, + 133, + 87, + 0, // Skip to: 23244 + /* 839 */ MCD_OPC_Decode, + 173, + 4, + 196, + 1, // Opcode: ALSIH + /* 844 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 859 + /* 849 */ MCD_OPC_CheckPredicate, + 19, + 118, + 87, + 0, // Skip to: 23244 + /* 854 */ MCD_OPC_Decode, + 174, + 4, + 196, + 1, // Opcode: ALSIHN + /* 859 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 874 + /* 864 */ MCD_OPC_CheckPredicate, + 19, + 103, + 87, + 0, // Skip to: 23244 + /* 869 */ MCD_OPC_Decode, + 218, + 6, + 197, + 1, // Opcode: CIH + /* 874 */ MCD_OPC_FilterValue, + 15, + 93, + 87, + 0, // Skip to: 23244 + /* 879 */ MCD_OPC_CheckPredicate, + 19, + 88, + 87, + 0, // Skip to: 23244 + /* 884 */ MCD_OPC_Decode, + 150, + 8, + 181, + 1, // Opcode: CLIH + /* 889 */ MCD_OPC_FilterValue, + 208, + 1, + 5, + 0, + 0, // Skip to: 900 + /* 895 */ MCD_OPC_Decode, + 190, + 18, + 198, + 1, // Opcode: TRTR + /* 900 */ MCD_OPC_FilterValue, + 209, + 1, + 5, + 0, + 0, // Skip to: 911 + /* 906 */ MCD_OPC_Decode, + 242, + 14, + 198, + 1, // Opcode: MVN + /* 911 */ MCD_OPC_FilterValue, + 210, + 1, + 5, + 0, + 0, // Skip to: 922 + /* 917 */ MCD_OPC_Decode, + 225, + 14, + 198, + 1, // Opcode: MVC + /* 922 */ MCD_OPC_FilterValue, + 211, + 1, + 5, + 0, + 0, // Skip to: 933 + /* 928 */ MCD_OPC_Decode, + 246, + 14, + 198, + 1, // Opcode: MVZ + /* 933 */ MCD_OPC_FilterValue, + 212, + 1, + 5, + 0, + 0, // Skip to: 944 + /* 939 */ MCD_OPC_Decode, + 134, + 15, + 198, + 1, // Opcode: NC + /* 944 */ MCD_OPC_FilterValue, + 213, + 1, + 5, + 0, + 0, // Skip to: 955 + /* 950 */ MCD_OPC_Decode, + 249, + 6, + 198, + 1, // Opcode: CLC + /* 955 */ MCD_OPC_FilterValue, + 214, + 1, + 5, + 0, + 0, // Skip to: 966 + /* 961 */ MCD_OPC_Decode, + 162, + 15, + 198, + 1, // Opcode: OC + /* 966 */ MCD_OPC_FilterValue, + 215, + 1, + 5, + 0, + 0, // Skip to: 977 + /* 972 */ MCD_OPC_Decode, + 166, + 24, + 198, + 1, // Opcode: XC + /* 977 */ MCD_OPC_FilterValue, + 217, + 1, + 5, + 0, + 0, // Skip to: 988 + /* 983 */ MCD_OPC_Decode, + 228, + 14, + 199, + 1, // Opcode: MVCK + /* 988 */ MCD_OPC_FilterValue, + 218, + 1, + 5, + 0, + 0, // Skip to: 999 + /* 994 */ MCD_OPC_Decode, + 233, + 14, + 199, + 1, // Opcode: MVCP + /* 999 */ MCD_OPC_FilterValue, + 219, + 1, + 5, + 0, + 0, // Skip to: 1010 + /* 1005 */ MCD_OPC_Decode, + 235, + 14, + 199, + 1, // Opcode: MVCS + /* 1010 */ MCD_OPC_FilterValue, + 220, + 1, + 5, + 0, + 0, // Skip to: 1021 + /* 1016 */ MCD_OPC_Decode, + 175, + 18, + 198, + 1, // Opcode: TR + /* 1021 */ MCD_OPC_FilterValue, + 221, + 1, + 5, + 0, + 0, // Skip to: 1032 + /* 1027 */ MCD_OPC_Decode, + 185, + 18, + 198, + 1, // Opcode: TRT + /* 1032 */ MCD_OPC_FilterValue, + 222, + 1, + 5, + 0, + 0, // Skip to: 1043 + /* 1038 */ MCD_OPC_Decode, + 245, + 9, + 198, + 1, // Opcode: ED + /* 1043 */ MCD_OPC_FilterValue, + 223, + 1, + 5, + 0, + 0, // Skip to: 1054 + /* 1049 */ MCD_OPC_Decode, + 246, + 9, + 198, + 1, // Opcode: EDMK + /* 1054 */ MCD_OPC_FilterValue, + 225, + 1, + 5, + 0, + 0, // Skip to: 1065 + /* 1060 */ MCD_OPC_Decode, + 191, + 15, + 200, + 1, // Opcode: PKU + /* 1065 */ MCD_OPC_FilterValue, + 226, + 1, + 5, + 0, + 0, // Skip to: 1076 + /* 1071 */ MCD_OPC_Decode, + 199, + 18, + 198, + 1, // Opcode: UNPKU + /* 1076 */ MCD_OPC_FilterValue, + 227, + 1, + 255, + 5, + 0, // Skip to: 2617 + /* 1082 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 1085 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 1095 + /* 1090 */ MCD_OPC_Decode, + 129, + 14, + 201, + 1, // Opcode: LTG + /* 1095 */ MCD_OPC_FilterValue, + 3, + 5, + 0, + 0, // Skip to: 1105 + /* 1100 */ MCD_OPC_Decode, + 238, + 13, + 201, + 1, // Opcode: LRAG + /* 1105 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 1115 + /* 1110 */ MCD_OPC_Decode, + 208, + 11, + 201, + 1, // Opcode: LG + /* 1115 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 1125 + /* 1120 */ MCD_OPC_Decode, + 184, + 9, + 202, + 1, // Opcode: CVBY + /* 1125 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 1135 + /* 1130 */ MCD_OPC_Decode, + 136, + 4, + 203, + 1, // Opcode: AG + /* 1135 */ MCD_OPC_FilterValue, + 9, + 5, + 0, + 0, // Skip to: 1145 + /* 1140 */ MCD_OPC_Decode, + 191, + 16, + 203, + 1, // Opcode: SG + /* 1145 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 1155 + /* 1150 */ MCD_OPC_Decode, + 159, + 4, + 203, + 1, // Opcode: ALG + /* 1155 */ MCD_OPC_FilterValue, + 11, + 5, + 0, + 0, // Skip to: 1165 + /* 1160 */ MCD_OPC_Decode, + 216, + 16, + 203, + 1, // Opcode: SLG + /* 1165 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 1175 + /* 1170 */ MCD_OPC_Decode, + 214, + 14, + 203, + 1, // Opcode: MSG + /* 1175 */ MCD_OPC_FilterValue, + 13, + 5, + 0, + 0, // Skip to: 1185 + /* 1180 */ MCD_OPC_Decode, + 232, + 9, + 204, + 1, // Opcode: DSG + /* 1185 */ MCD_OPC_FilterValue, + 14, + 5, + 0, + 0, // Skip to: 1195 + /* 1190 */ MCD_OPC_Decode, + 183, + 9, + 203, + 1, // Opcode: CVBG + /* 1195 */ MCD_OPC_FilterValue, + 15, + 5, + 0, + 0, // Skip to: 1205 + /* 1200 */ MCD_OPC_Decode, + 244, + 13, + 201, + 1, // Opcode: LRVG + /* 1205 */ MCD_OPC_FilterValue, + 18, + 5, + 0, + 0, // Skip to: 1215 + /* 1210 */ MCD_OPC_Decode, + 249, + 13, + 205, + 1, // Opcode: LT + /* 1215 */ MCD_OPC_FilterValue, + 19, + 5, + 0, + 0, // Skip to: 1225 + /* 1220 */ MCD_OPC_Decode, + 239, + 13, + 201, + 1, // Opcode: LRAY + /* 1225 */ MCD_OPC_FilterValue, + 20, + 5, + 0, + 0, // Skip to: 1235 + /* 1230 */ MCD_OPC_Decode, + 213, + 11, + 201, + 1, // Opcode: LGF + /* 1235 */ MCD_OPC_FilterValue, + 21, + 5, + 0, + 0, // Skip to: 1245 + /* 1240 */ MCD_OPC_Decode, + 218, + 11, + 201, + 1, // Opcode: LGH + /* 1245 */ MCD_OPC_FilterValue, + 22, + 5, + 0, + 0, // Skip to: 1255 + /* 1250 */ MCD_OPC_Decode, + 236, + 11, + 201, + 1, // Opcode: LLGF + /* 1255 */ MCD_OPC_FilterValue, + 23, + 5, + 0, + 0, // Skip to: 1265 + /* 1260 */ MCD_OPC_Decode, + 244, + 11, + 201, + 1, // Opcode: LLGT + /* 1265 */ MCD_OPC_FilterValue, + 24, + 5, + 0, + 0, // Skip to: 1275 + /* 1270 */ MCD_OPC_Decode, + 137, + 4, + 203, + 1, // Opcode: AGF + /* 1275 */ MCD_OPC_FilterValue, + 25, + 5, + 0, + 0, // Skip to: 1285 + /* 1280 */ MCD_OPC_Decode, + 192, + 16, + 203, + 1, // Opcode: SGF + /* 1285 */ MCD_OPC_FilterValue, + 26, + 5, + 0, + 0, // Skip to: 1295 + /* 1290 */ MCD_OPC_Decode, + 160, + 4, + 203, + 1, // Opcode: ALGF + /* 1295 */ MCD_OPC_FilterValue, + 27, + 5, + 0, + 0, // Skip to: 1305 + /* 1300 */ MCD_OPC_Decode, + 217, + 16, + 203, + 1, // Opcode: SLGF + /* 1305 */ MCD_OPC_FilterValue, + 28, + 5, + 0, + 0, // Skip to: 1315 + /* 1310 */ MCD_OPC_Decode, + 216, + 14, + 203, + 1, // Opcode: MSGF + /* 1315 */ MCD_OPC_FilterValue, + 29, + 5, + 0, + 0, // Skip to: 1325 + /* 1320 */ MCD_OPC_Decode, + 233, + 9, + 204, + 1, // Opcode: DSGF + /* 1325 */ MCD_OPC_FilterValue, + 30, + 5, + 0, + 0, // Skip to: 1335 + /* 1330 */ MCD_OPC_Decode, + 243, + 13, + 205, + 1, // Opcode: LRV + /* 1335 */ MCD_OPC_FilterValue, + 31, + 5, + 0, + 0, // Skip to: 1345 + /* 1340 */ MCD_OPC_Decode, + 246, + 13, + 205, + 1, // Opcode: LRVH + /* 1345 */ MCD_OPC_FilterValue, + 32, + 5, + 0, + 0, // Skip to: 1355 + /* 1350 */ MCD_OPC_Decode, + 215, + 5, + 201, + 1, // Opcode: CG + /* 1355 */ MCD_OPC_FilterValue, + 33, + 5, + 0, + 0, // Skip to: 1365 + /* 1360 */ MCD_OPC_Decode, + 146, + 7, + 201, + 1, // Opcode: CLG + /* 1365 */ MCD_OPC_FilterValue, + 36, + 5, + 0, + 0, // Skip to: 1375 + /* 1370 */ MCD_OPC_Decode, + 171, + 17, + 201, + 1, // Opcode: STG + /* 1375 */ MCD_OPC_FilterValue, + 37, + 10, + 0, + 0, // Skip to: 1390 + /* 1380 */ MCD_OPC_CheckPredicate, + 4, + 99, + 85, + 0, // Skip to: 23244 + /* 1385 */ MCD_OPC_Decode, + 157, + 15, + 201, + 1, // Opcode: NTSTG + /* 1390 */ MCD_OPC_FilterValue, + 38, + 5, + 0, + 0, // Skip to: 1400 + /* 1395 */ MCD_OPC_Decode, + 187, + 9, + 205, + 1, // Opcode: CVDY + /* 1400 */ MCD_OPC_FilterValue, + 42, + 10, + 0, + 0, // Skip to: 1415 + /* 1405 */ MCD_OPC_CheckPredicate, + 26, + 74, + 85, + 0, // Skip to: 23244 + /* 1410 */ MCD_OPC_Decode, + 154, + 14, + 201, + 1, // Opcode: LZRG + /* 1415 */ MCD_OPC_FilterValue, + 46, + 5, + 0, + 0, // Skip to: 1425 + /* 1420 */ MCD_OPC_Decode, + 186, + 9, + 201, + 1, // Opcode: CVDG + /* 1425 */ MCD_OPC_FilterValue, + 47, + 5, + 0, + 0, // Skip to: 1435 + /* 1430 */ MCD_OPC_Decode, + 129, + 18, + 201, + 1, // Opcode: STRVG + /* 1435 */ MCD_OPC_FilterValue, + 48, + 5, + 0, + 0, // Skip to: 1445 + /* 1440 */ MCD_OPC_Decode, + 224, + 5, + 201, + 1, // Opcode: CGF + /* 1445 */ MCD_OPC_FilterValue, + 49, + 5, + 0, + 0, // Skip to: 1455 + /* 1450 */ MCD_OPC_Decode, + 150, + 7, + 201, + 1, // Opcode: CLGF + /* 1455 */ MCD_OPC_FilterValue, + 50, + 5, + 0, + 0, // Skip to: 1465 + /* 1460 */ MCD_OPC_Decode, + 130, + 14, + 201, + 1, // Opcode: LTGF + /* 1465 */ MCD_OPC_FilterValue, + 52, + 5, + 0, + 0, // Skip to: 1475 + /* 1470 */ MCD_OPC_Decode, + 228, + 5, + 201, + 1, // Opcode: CGH + /* 1475 */ MCD_OPC_FilterValue, + 54, + 5, + 0, + 0, // Skip to: 1485 + /* 1480 */ MCD_OPC_Decode, + 184, + 15, + 206, + 1, // Opcode: PFD + /* 1485 */ MCD_OPC_FilterValue, + 56, + 10, + 0, + 0, // Skip to: 1500 + /* 1490 */ MCD_OPC_CheckPredicate, + 24, + 245, + 84, + 0, // Skip to: 23244 + /* 1495 */ MCD_OPC_Decode, + 140, + 4, + 203, + 1, // Opcode: AGH + /* 1500 */ MCD_OPC_FilterValue, + 57, + 10, + 0, + 0, // Skip to: 1515 + /* 1505 */ MCD_OPC_CheckPredicate, + 24, + 230, + 84, + 0, // Skip to: 23244 + /* 1510 */ MCD_OPC_Decode, + 194, + 16, + 203, + 1, // Opcode: SGH + /* 1515 */ MCD_OPC_FilterValue, + 58, + 10, + 0, + 0, // Skip to: 1530 + /* 1520 */ MCD_OPC_CheckPredicate, + 26, + 215, + 84, + 0, // Skip to: 23244 + /* 1525 */ MCD_OPC_Decode, + 129, + 12, + 201, + 1, // Opcode: LLZRGF + /* 1530 */ MCD_OPC_FilterValue, + 59, + 10, + 0, + 0, // Skip to: 1545 + /* 1535 */ MCD_OPC_CheckPredicate, + 26, + 200, + 84, + 0, // Skip to: 23244 + /* 1540 */ MCD_OPC_Decode, + 153, + 14, + 205, + 1, // Opcode: LZRF + /* 1545 */ MCD_OPC_FilterValue, + 60, + 10, + 0, + 0, // Skip to: 1560 + /* 1550 */ MCD_OPC_CheckPredicate, + 24, + 185, + 84, + 0, // Skip to: 23244 + /* 1555 */ MCD_OPC_Decode, + 190, + 14, + 203, + 1, // Opcode: MGH + /* 1560 */ MCD_OPC_FilterValue, + 62, + 5, + 0, + 0, // Skip to: 1570 + /* 1565 */ MCD_OPC_Decode, + 128, + 18, + 205, + 1, // Opcode: STRV + /* 1570 */ MCD_OPC_FilterValue, + 63, + 5, + 0, + 0, // Skip to: 1580 + /* 1575 */ MCD_OPC_Decode, + 130, + 18, + 205, + 1, // Opcode: STRVH + /* 1580 */ MCD_OPC_FilterValue, + 70, + 5, + 0, + 0, // Skip to: 1590 + /* 1585 */ MCD_OPC_Decode, + 221, + 4, + 203, + 1, // Opcode: BCTG + /* 1590 */ MCD_OPC_FilterValue, + 71, + 238, + 0, + 0, // Skip to: 1833 + /* 1595 */ MCD_OPC_ExtractField, + 36, + 4, // Inst{39-36} ... + /* 1598 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 1613 + /* 1603 */ MCD_OPC_CheckPredicate, + 24, + 215, + 0, + 0, // Skip to: 1823 + /* 1608 */ MCD_OPC_Decode, + 242, + 4, + 207, + 1, // Opcode: BIAsmO + /* 1613 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 1628 + /* 1618 */ MCD_OPC_CheckPredicate, + 24, + 200, + 0, + 0, // Skip to: 1823 + /* 1623 */ MCD_OPC_Decode, + 226, + 4, + 207, + 1, // Opcode: BIAsmH + /* 1628 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 1643 + /* 1633 */ MCD_OPC_CheckPredicate, + 24, + 185, + 0, + 0, // Skip to: 1823 + /* 1638 */ MCD_OPC_Decode, + 236, + 4, + 207, + 1, // Opcode: BIAsmNLE + /* 1643 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 1658 + /* 1648 */ MCD_OPC_CheckPredicate, + 24, + 170, + 0, + 0, // Skip to: 1823 + /* 1653 */ MCD_OPC_Decode, + 228, + 4, + 207, + 1, // Opcode: BIAsmL + /* 1658 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 1673 + /* 1663 */ MCD_OPC_CheckPredicate, + 24, + 155, + 0, + 0, // Skip to: 1823 + /* 1668 */ MCD_OPC_Decode, + 234, + 4, + 207, + 1, // Opcode: BIAsmNHE + /* 1673 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 1688 + /* 1678 */ MCD_OPC_CheckPredicate, + 24, + 140, + 0, + 0, // Skip to: 1823 + /* 1683 */ MCD_OPC_Decode, + 230, + 4, + 207, + 1, // Opcode: BIAsmLH + /* 1688 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 1703 + /* 1693 */ MCD_OPC_CheckPredicate, + 24, + 125, + 0, + 0, // Skip to: 1823 + /* 1698 */ MCD_OPC_Decode, + 232, + 4, + 207, + 1, // Opcode: BIAsmNE + /* 1703 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 1718 + /* 1708 */ MCD_OPC_CheckPredicate, + 24, + 110, + 0, + 0, // Skip to: 1823 + /* 1713 */ MCD_OPC_Decode, + 225, + 4, + 207, + 1, // Opcode: BIAsmE + /* 1718 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 1733 + /* 1723 */ MCD_OPC_CheckPredicate, + 24, + 95, + 0, + 0, // Skip to: 1823 + /* 1728 */ MCD_OPC_Decode, + 237, + 4, + 207, + 1, // Opcode: BIAsmNLH + /* 1733 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 1748 + /* 1738 */ MCD_OPC_CheckPredicate, + 24, + 80, + 0, + 0, // Skip to: 1823 + /* 1743 */ MCD_OPC_Decode, + 227, + 4, + 207, + 1, // Opcode: BIAsmHE + /* 1748 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 1763 + /* 1753 */ MCD_OPC_CheckPredicate, + 24, + 65, + 0, + 0, // Skip to: 1823 + /* 1758 */ MCD_OPC_Decode, + 235, + 4, + 207, + 1, // Opcode: BIAsmNL + /* 1763 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 1778 + /* 1768 */ MCD_OPC_CheckPredicate, + 24, + 50, + 0, + 0, // Skip to: 1823 + /* 1773 */ MCD_OPC_Decode, + 229, + 4, + 207, + 1, // Opcode: BIAsmLE + /* 1778 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 1793 + /* 1783 */ MCD_OPC_CheckPredicate, + 24, + 35, + 0, + 0, // Skip to: 1823 + /* 1788 */ MCD_OPC_Decode, + 233, + 4, + 207, + 1, // Opcode: BIAsmNH + /* 1793 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 1808 + /* 1798 */ MCD_OPC_CheckPredicate, + 24, + 20, + 0, + 0, // Skip to: 1823 + /* 1803 */ MCD_OPC_Decode, + 239, + 4, + 207, + 1, // Opcode: BIAsmNO + /* 1808 */ MCD_OPC_FilterValue, + 15, + 10, + 0, + 0, // Skip to: 1823 + /* 1813 */ MCD_OPC_CheckPredicate, + 24, + 5, + 0, + 0, // Skip to: 1823 + /* 1818 */ MCD_OPC_Decode, + 224, + 4, + 207, + 1, // Opcode: BI + /* 1823 */ MCD_OPC_CheckPredicate, + 24, + 168, + 83, + 0, // Skip to: 23244 + /* 1828 */ MCD_OPC_Decode, + 246, + 4, + 206, + 1, // Opcode: BICAsm + /* 1833 */ MCD_OPC_FilterValue, + 72, + 10, + 0, + 0, // Skip to: 1848 + /* 1838 */ MCD_OPC_CheckPredicate, + 27, + 153, + 83, + 0, // Skip to: 23244 + /* 1843 */ MCD_OPC_Decode, + 240, + 11, + 201, + 1, // Opcode: LLGFSG + /* 1848 */ MCD_OPC_FilterValue, + 73, + 10, + 0, + 0, // Skip to: 1863 + /* 1853 */ MCD_OPC_CheckPredicate, + 27, + 138, + 83, + 0, // Skip to: 23244 + /* 1858 */ MCD_OPC_Decode, + 173, + 17, + 201, + 1, // Opcode: STGSC + /* 1863 */ MCD_OPC_FilterValue, + 76, + 10, + 0, + 0, // Skip to: 1878 + /* 1868 */ MCD_OPC_CheckPredicate, + 27, + 123, + 83, + 0, // Skip to: 23244 + /* 1873 */ MCD_OPC_Decode, + 217, + 11, + 201, + 1, // Opcode: LGG + /* 1878 */ MCD_OPC_FilterValue, + 77, + 10, + 0, + 0, // Skip to: 1893 + /* 1883 */ MCD_OPC_CheckPredicate, + 27, + 108, + 83, + 0, // Skip to: 23244 + /* 1888 */ MCD_OPC_Decode, + 224, + 11, + 201, + 1, // Opcode: LGSC + /* 1893 */ MCD_OPC_FilterValue, + 80, + 5, + 0, + 0, // Skip to: 1903 + /* 1898 */ MCD_OPC_Decode, + 135, + 18, + 205, + 1, // Opcode: STY + /* 1903 */ MCD_OPC_FilterValue, + 81, + 5, + 0, + 0, // Skip to: 1913 + /* 1908 */ MCD_OPC_Decode, + 224, + 14, + 202, + 1, // Opcode: MSY + /* 1913 */ MCD_OPC_FilterValue, + 83, + 10, + 0, + 0, // Skip to: 1928 + /* 1918 */ MCD_OPC_CheckPredicate, + 24, + 73, + 83, + 0, // Skip to: 23244 + /* 1923 */ MCD_OPC_Decode, + 203, + 14, + 202, + 1, // Opcode: MSC + /* 1928 */ MCD_OPC_FilterValue, + 84, + 5, + 0, + 0, // Skip to: 1938 + /* 1933 */ MCD_OPC_Decode, + 160, + 15, + 202, + 1, // Opcode: NY + /* 1938 */ MCD_OPC_FilterValue, + 85, + 5, + 0, + 0, // Skip to: 1948 + /* 1943 */ MCD_OPC_Decode, + 228, + 8, + 205, + 1, // Opcode: CLY + /* 1948 */ MCD_OPC_FilterValue, + 86, + 5, + 0, + 0, // Skip to: 1958 + /* 1953 */ MCD_OPC_Decode, + 178, + 15, + 202, + 1, // Opcode: OY + /* 1958 */ MCD_OPC_FilterValue, + 87, + 5, + 0, + 0, // Skip to: 1968 + /* 1963 */ MCD_OPC_Decode, + 177, + 24, + 202, + 1, // Opcode: XY + /* 1968 */ MCD_OPC_FilterValue, + 88, + 5, + 0, + 0, // Skip to: 1978 + /* 1973 */ MCD_OPC_Decode, + 150, + 14, + 205, + 1, // Opcode: LY + /* 1978 */ MCD_OPC_FilterValue, + 89, + 5, + 0, + 0, // Skip to: 1988 + /* 1983 */ MCD_OPC_Decode, + 208, + 9, + 205, + 1, // Opcode: CY + /* 1988 */ MCD_OPC_FilterValue, + 90, + 5, + 0, + 0, // Skip to: 1998 + /* 1993 */ MCD_OPC_Decode, + 188, + 4, + 202, + 1, // Opcode: AY + /* 1998 */ MCD_OPC_FilterValue, + 91, + 5, + 0, + 0, // Skip to: 2008 + /* 2003 */ MCD_OPC_Decode, + 145, + 18, + 202, + 1, // Opcode: SY + /* 2008 */ MCD_OPC_FilterValue, + 92, + 5, + 0, + 0, // Skip to: 2018 + /* 2013 */ MCD_OPC_Decode, + 188, + 14, + 204, + 1, // Opcode: MFY + /* 2018 */ MCD_OPC_FilterValue, + 94, + 5, + 0, + 0, // Skip to: 2028 + /* 2023 */ MCD_OPC_Decode, + 175, + 4, + 202, + 1, // Opcode: ALY + /* 2028 */ MCD_OPC_FilterValue, + 95, + 5, + 0, + 0, // Skip to: 2038 + /* 2033 */ MCD_OPC_Decode, + 230, + 16, + 202, + 1, // Opcode: SLY + /* 2038 */ MCD_OPC_FilterValue, + 112, + 5, + 0, + 0, // Skip to: 2048 + /* 2043 */ MCD_OPC_Decode, + 177, + 17, + 205, + 1, // Opcode: STHY + /* 2048 */ MCD_OPC_FilterValue, + 113, + 5, + 0, + 0, // Skip to: 2058 + /* 2053 */ MCD_OPC_Decode, + 159, + 11, + 201, + 1, // Opcode: LAY + /* 2058 */ MCD_OPC_FilterValue, + 114, + 5, + 0, + 0, // Skip to: 2068 + /* 2063 */ MCD_OPC_Decode, + 162, + 17, + 205, + 1, // Opcode: STCY + /* 2068 */ MCD_OPC_FilterValue, + 115, + 5, + 0, + 0, // Skip to: 2078 + /* 2073 */ MCD_OPC_Decode, + 159, + 10, + 203, + 1, // Opcode: ICY + /* 2078 */ MCD_OPC_FilterValue, + 117, + 5, + 0, + 0, // Skip to: 2088 + /* 2083 */ MCD_OPC_Decode, + 147, + 11, + 201, + 1, // Opcode: LAEY + /* 2088 */ MCD_OPC_FilterValue, + 118, + 5, + 0, + 0, // Skip to: 2098 + /* 2093 */ MCD_OPC_Decode, + 160, + 11, + 205, + 1, // Opcode: LB + /* 2098 */ MCD_OPC_FilterValue, + 119, + 5, + 0, + 0, // Skip to: 2108 + /* 2103 */ MCD_OPC_Decode, + 210, + 11, + 201, + 1, // Opcode: LGB + /* 2108 */ MCD_OPC_FilterValue, + 120, + 5, + 0, + 0, // Skip to: 2118 + /* 2113 */ MCD_OPC_Decode, + 230, + 11, + 205, + 1, // Opcode: LHY + /* 2118 */ MCD_OPC_FilterValue, + 121, + 5, + 0, + 0, // Skip to: 2128 + /* 2123 */ MCD_OPC_Decode, + 203, + 6, + 205, + 1, // Opcode: CHY + /* 2128 */ MCD_OPC_FilterValue, + 122, + 5, + 0, + 0, // Skip to: 2138 + /* 2133 */ MCD_OPC_Decode, + 151, + 4, + 202, + 1, // Opcode: AHY + /* 2138 */ MCD_OPC_FilterValue, + 123, + 5, + 0, + 0, // Skip to: 2148 + /* 2143 */ MCD_OPC_Decode, + 200, + 16, + 202, + 1, // Opcode: SHY + /* 2148 */ MCD_OPC_FilterValue, + 124, + 5, + 0, + 0, // Skip to: 2158 + /* 2153 */ MCD_OPC_Decode, + 195, + 14, + 202, + 1, // Opcode: MHY + /* 2158 */ MCD_OPC_FilterValue, + 128, + 1, + 5, + 0, + 0, // Skip to: 2169 + /* 2164 */ MCD_OPC_Decode, + 137, + 15, + 203, + 1, // Opcode: NG + /* 2169 */ MCD_OPC_FilterValue, + 129, + 1, + 5, + 0, + 0, // Skip to: 2180 + /* 2175 */ MCD_OPC_Decode, + 165, + 15, + 203, + 1, // Opcode: OG + /* 2180 */ MCD_OPC_FilterValue, + 130, + 1, + 5, + 0, + 0, // Skip to: 2191 + /* 2186 */ MCD_OPC_Decode, + 167, + 24, + 203, + 1, // Opcode: XG + /* 2191 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 2207 + /* 2197 */ MCD_OPC_CheckPredicate, + 24, + 50, + 82, + 0, // Skip to: 23244 + /* 2202 */ MCD_OPC_Decode, + 215, + 14, + 203, + 1, // Opcode: MSGC + /* 2207 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 2223 + /* 2213 */ MCD_OPC_CheckPredicate, + 24, + 34, + 82, + 0, // Skip to: 23244 + /* 2218 */ MCD_OPC_Decode, + 189, + 14, + 204, + 1, // Opcode: MG + /* 2223 */ MCD_OPC_FilterValue, + 133, + 1, + 10, + 0, + 0, // Skip to: 2239 + /* 2229 */ MCD_OPC_CheckPredicate, + 28, + 18, + 82, + 0, // Skip to: 23244 + /* 2234 */ MCD_OPC_Decode, + 209, + 11, + 201, + 1, // Opcode: LGAT + /* 2239 */ MCD_OPC_FilterValue, + 134, + 1, + 5, + 0, + 0, // Skip to: 2250 + /* 2245 */ MCD_OPC_Decode, + 197, + 14, + 204, + 1, // Opcode: MLG + /* 2250 */ MCD_OPC_FilterValue, + 135, + 1, + 5, + 0, + 0, // Skip to: 2261 + /* 2256 */ MCD_OPC_Decode, + 227, + 9, + 204, + 1, // Opcode: DLG + /* 2261 */ MCD_OPC_FilterValue, + 136, + 1, + 5, + 0, + 0, // Skip to: 2272 + /* 2267 */ MCD_OPC_Decode, + 155, + 4, + 203, + 1, // Opcode: ALCG + /* 2272 */ MCD_OPC_FilterValue, + 137, + 1, + 5, + 0, + 0, // Skip to: 2283 + /* 2278 */ MCD_OPC_Decode, + 209, + 16, + 203, + 1, // Opcode: SLBG + /* 2283 */ MCD_OPC_FilterValue, + 142, + 1, + 5, + 0, + 0, // Skip to: 2294 + /* 2289 */ MCD_OPC_Decode, + 251, + 17, + 208, + 1, // Opcode: STPQ + /* 2294 */ MCD_OPC_FilterValue, + 143, + 1, + 5, + 0, + 0, // Skip to: 2305 + /* 2300 */ MCD_OPC_Decode, + 228, + 13, + 208, + 1, // Opcode: LPQ + /* 2305 */ MCD_OPC_FilterValue, + 144, + 1, + 5, + 0, + 0, // Skip to: 2316 + /* 2311 */ MCD_OPC_Decode, + 234, + 11, + 201, + 1, // Opcode: LLGC + /* 2316 */ MCD_OPC_FilterValue, + 145, + 1, + 5, + 0, + 0, // Skip to: 2327 + /* 2322 */ MCD_OPC_Decode, + 241, + 11, + 201, + 1, // Opcode: LLGH + /* 2327 */ MCD_OPC_FilterValue, + 148, + 1, + 5, + 0, + 0, // Skip to: 2338 + /* 2333 */ MCD_OPC_Decode, + 231, + 11, + 205, + 1, // Opcode: LLC + /* 2338 */ MCD_OPC_FilterValue, + 149, + 1, + 5, + 0, + 0, // Skip to: 2349 + /* 2344 */ MCD_OPC_Decode, + 247, + 11, + 205, + 1, // Opcode: LLH + /* 2349 */ MCD_OPC_FilterValue, + 150, + 1, + 5, + 0, + 0, // Skip to: 2360 + /* 2355 */ MCD_OPC_Decode, + 196, + 14, + 204, + 1, // Opcode: ML + /* 2360 */ MCD_OPC_FilterValue, + 151, + 1, + 5, + 0, + 0, // Skip to: 2371 + /* 2366 */ MCD_OPC_Decode, + 226, + 9, + 204, + 1, // Opcode: DL + /* 2371 */ MCD_OPC_FilterValue, + 152, + 1, + 5, + 0, + 0, // Skip to: 2382 + /* 2377 */ MCD_OPC_Decode, + 154, + 4, + 202, + 1, // Opcode: ALC + /* 2382 */ MCD_OPC_FilterValue, + 153, + 1, + 5, + 0, + 0, // Skip to: 2393 + /* 2388 */ MCD_OPC_Decode, + 208, + 16, + 202, + 1, // Opcode: SLB + /* 2393 */ MCD_OPC_FilterValue, + 156, + 1, + 10, + 0, + 0, // Skip to: 2409 + /* 2399 */ MCD_OPC_CheckPredicate, + 28, + 104, + 81, + 0, // Skip to: 23244 + /* 2404 */ MCD_OPC_Decode, + 245, + 11, + 201, + 1, // Opcode: LLGTAT + /* 2409 */ MCD_OPC_FilterValue, + 157, + 1, + 10, + 0, + 0, // Skip to: 2425 + /* 2415 */ MCD_OPC_CheckPredicate, + 28, + 88, + 81, + 0, // Skip to: 23244 + /* 2420 */ MCD_OPC_Decode, + 237, + 11, + 201, + 1, // Opcode: LLGFAT + /* 2425 */ MCD_OPC_FilterValue, + 159, + 1, + 10, + 0, + 0, // Skip to: 2441 + /* 2431 */ MCD_OPC_CheckPredicate, + 28, + 72, + 81, + 0, // Skip to: 23244 + /* 2436 */ MCD_OPC_Decode, + 156, + 11, + 205, + 1, // Opcode: LAT + /* 2441 */ MCD_OPC_FilterValue, + 192, + 1, + 10, + 0, + 0, // Skip to: 2457 + /* 2447 */ MCD_OPC_CheckPredicate, + 19, + 56, + 81, + 0, // Skip to: 23244 + /* 2452 */ MCD_OPC_Decode, + 162, + 11, + 209, + 1, // Opcode: LBH + /* 2457 */ MCD_OPC_FilterValue, + 194, + 1, + 10, + 0, + 0, // Skip to: 2473 + /* 2463 */ MCD_OPC_CheckPredicate, + 19, + 40, + 81, + 0, // Skip to: 23244 + /* 2468 */ MCD_OPC_Decode, + 232, + 11, + 209, + 1, // Opcode: LLCH + /* 2473 */ MCD_OPC_FilterValue, + 195, + 1, + 10, + 0, + 0, // Skip to: 2489 + /* 2479 */ MCD_OPC_CheckPredicate, + 19, + 24, + 81, + 0, // Skip to: 23244 + /* 2484 */ MCD_OPC_Decode, + 150, + 17, + 209, + 1, // Opcode: STCH + /* 2489 */ MCD_OPC_FilterValue, + 196, + 1, + 10, + 0, + 0, // Skip to: 2505 + /* 2495 */ MCD_OPC_CheckPredicate, + 19, + 8, + 81, + 0, // Skip to: 23244 + /* 2500 */ MCD_OPC_Decode, + 226, + 11, + 209, + 1, // Opcode: LHH + /* 2505 */ MCD_OPC_FilterValue, + 198, + 1, + 10, + 0, + 0, // Skip to: 2521 + /* 2511 */ MCD_OPC_CheckPredicate, + 19, + 248, + 80, + 0, // Skip to: 23244 + /* 2516 */ MCD_OPC_Decode, + 248, + 11, + 209, + 1, // Opcode: LLHH + /* 2521 */ MCD_OPC_FilterValue, + 199, + 1, + 10, + 0, + 0, // Skip to: 2537 + /* 2527 */ MCD_OPC_CheckPredicate, + 19, + 232, + 80, + 0, // Skip to: 23244 + /* 2532 */ MCD_OPC_Decode, + 175, + 17, + 209, + 1, // Opcode: STHH + /* 2537 */ MCD_OPC_FilterValue, + 200, + 1, + 10, + 0, + 0, // Skip to: 2553 + /* 2543 */ MCD_OPC_CheckPredicate, + 28, + 216, + 80, + 0, // Skip to: 23244 + /* 2548 */ MCD_OPC_Decode, + 206, + 11, + 209, + 1, // Opcode: LFHAT + /* 2553 */ MCD_OPC_FilterValue, + 202, + 1, + 10, + 0, + 0, // Skip to: 2569 + /* 2559 */ MCD_OPC_CheckPredicate, + 19, + 200, + 80, + 0, // Skip to: 23244 + /* 2564 */ MCD_OPC_Decode, + 205, + 11, + 209, + 1, // Opcode: LFH + /* 2569 */ MCD_OPC_FilterValue, + 203, + 1, + 10, + 0, + 0, // Skip to: 2585 + /* 2575 */ MCD_OPC_CheckPredicate, + 19, + 184, + 80, + 0, // Skip to: 23244 + /* 2580 */ MCD_OPC_Decode, + 167, + 17, + 209, + 1, // Opcode: STFH + /* 2585 */ MCD_OPC_FilterValue, + 205, + 1, + 10, + 0, + 0, // Skip to: 2601 + /* 2591 */ MCD_OPC_CheckPredicate, + 19, + 168, + 80, + 0, // Skip to: 23244 + /* 2596 */ MCD_OPC_Decode, + 196, + 6, + 209, + 1, // Opcode: CHF + /* 2601 */ MCD_OPC_FilterValue, + 207, + 1, + 157, + 80, + 0, // Skip to: 23244 + /* 2607 */ MCD_OPC_CheckPredicate, + 19, + 152, + 80, + 0, // Skip to: 23244 + /* 2612 */ MCD_OPC_Decode, + 130, + 8, + 209, + 1, // Opcode: CLHF + /* 2617 */ MCD_OPC_FilterValue, + 229, + 1, + 188, + 0, + 0, // Skip to: 2811 + /* 2623 */ MCD_OPC_ExtractField, + 32, + 8, // Inst{39-32} ... + /* 2626 */ MCD_OPC_FilterValue, + 0, + 5, + 0, + 0, // Skip to: 2636 + /* 2631 */ MCD_OPC_Decode, + 155, + 11, + 210, + 1, // Opcode: LASP + /* 2636 */ MCD_OPC_FilterValue, + 1, + 5, + 0, + 0, // Skip to: 2646 + /* 2641 */ MCD_OPC_Decode, + 174, + 18, + 210, + 1, // Opcode: TPROT + /* 2646 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 2656 + /* 2651 */ MCD_OPC_Decode, + 254, + 17, + 210, + 1, // Opcode: STRAG + /* 2656 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 2671 + /* 2661 */ MCD_OPC_CheckPredicate, + 14, + 98, + 80, + 0, // Skip to: 23244 + /* 2666 */ MCD_OPC_Decode, + 234, + 14, + 210, + 1, // Opcode: MVCRL + /* 2671 */ MCD_OPC_FilterValue, + 14, + 5, + 0, + 0, // Skip to: 2681 + /* 2676 */ MCD_OPC_Decode, + 236, + 14, + 210, + 1, // Opcode: MVCSK + /* 2681 */ MCD_OPC_FilterValue, + 15, + 5, + 0, + 0, // Skip to: 2691 + /* 2686 */ MCD_OPC_Decode, + 226, + 14, + 210, + 1, // Opcode: MVCDK + /* 2691 */ MCD_OPC_FilterValue, + 68, + 5, + 0, + 0, // Skip to: 2701 + /* 2696 */ MCD_OPC_Decode, + 238, + 14, + 211, + 1, // Opcode: MVHHI + /* 2701 */ MCD_OPC_FilterValue, + 72, + 5, + 0, + 0, // Skip to: 2711 + /* 2706 */ MCD_OPC_Decode, + 237, + 14, + 211, + 1, // Opcode: MVGHI + /* 2711 */ MCD_OPC_FilterValue, + 76, + 5, + 0, + 0, // Skip to: 2721 + /* 2716 */ MCD_OPC_Decode, + 239, + 14, + 211, + 1, // Opcode: MVHI + /* 2721 */ MCD_OPC_FilterValue, + 84, + 5, + 0, + 0, // Skip to: 2731 + /* 2726 */ MCD_OPC_Decode, + 198, + 6, + 211, + 1, // Opcode: CHHSI + /* 2731 */ MCD_OPC_FilterValue, + 85, + 5, + 0, + 0, // Skip to: 2741 + /* 2736 */ MCD_OPC_Decode, + 132, + 8, + 212, + 1, // Opcode: CLHHSI + /* 2741 */ MCD_OPC_FilterValue, + 88, + 5, + 0, + 0, // Skip to: 2751 + /* 2746 */ MCD_OPC_Decode, + 231, + 5, + 211, + 1, // Opcode: CGHSI + /* 2751 */ MCD_OPC_FilterValue, + 89, + 5, + 0, + 0, // Skip to: 2761 + /* 2756 */ MCD_OPC_Decode, + 155, + 7, + 212, + 1, // Opcode: CLGHSI + /* 2761 */ MCD_OPC_FilterValue, + 92, + 5, + 0, + 0, // Skip to: 2771 + /* 2766 */ MCD_OPC_Decode, + 202, + 6, + 211, + 1, // Opcode: CHSI + /* 2771 */ MCD_OPC_FilterValue, + 93, + 5, + 0, + 0, // Skip to: 2781 + /* 2776 */ MCD_OPC_Decode, + 128, + 7, + 212, + 1, // Opcode: CLFHSI + /* 2781 */ MCD_OPC_FilterValue, + 96, + 10, + 0, + 0, // Skip to: 2796 + /* 2786 */ MCD_OPC_CheckPredicate, + 4, + 229, + 79, + 0, // Skip to: 23244 + /* 2791 */ MCD_OPC_Decode, + 152, + 18, + 212, + 1, // Opcode: TBEGIN + /* 2796 */ MCD_OPC_FilterValue, + 97, + 219, + 79, + 0, // Skip to: 23244 + /* 2801 */ MCD_OPC_CheckPredicate, + 4, + 214, + 79, + 0, // Skip to: 23244 + /* 2806 */ MCD_OPC_Decode, + 153, + 18, + 212, + 1, // Opcode: TBEGINC + /* 2811 */ MCD_OPC_FilterValue, + 230, + 1, + 204, + 6, + 0, // Skip to: 4557 + /* 2817 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 2820 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 2842 + /* 2825 */ MCD_OPC_CheckPredicate, + 29, + 190, + 79, + 0, // Skip to: 23244 + /* 2830 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 183, + 79, + 0, // Skip to: 23244 + /* 2837 */ MCD_OPC_Decode, + 134, + 21, + 213, + 1, // Opcode: VLEBRH + /* 2842 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 2864 + /* 2847 */ MCD_OPC_CheckPredicate, + 29, + 168, + 79, + 0, // Skip to: 23244 + /* 2852 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 161, + 79, + 0, // Skip to: 23244 + /* 2859 */ MCD_OPC_Decode, + 133, + 21, + 214, + 1, // Opcode: VLEBRG + /* 2864 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 2886 + /* 2869 */ MCD_OPC_CheckPredicate, + 29, + 146, + 79, + 0, // Skip to: 23244 + /* 2874 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 139, + 79, + 0, // Skip to: 23244 + /* 2881 */ MCD_OPC_Decode, + 132, + 21, + 215, + 1, // Opcode: VLEBRF + /* 2886 */ MCD_OPC_FilterValue, + 4, + 81, + 0, + 0, // Skip to: 2972 + /* 2891 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 2894 */ MCD_OPC_FilterValue, + 0, + 121, + 79, + 0, // Skip to: 23244 + /* 2899 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 2902 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 2917 + /* 2907 */ MCD_OPC_CheckPredicate, + 29, + 50, + 0, + 0, // Skip to: 2962 + /* 2912 */ MCD_OPC_Decode, + 159, + 21, + 216, + 1, // Opcode: VLLEBRZH + /* 2917 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 2932 + /* 2922 */ MCD_OPC_CheckPredicate, + 29, + 35, + 0, + 0, // Skip to: 2962 + /* 2927 */ MCD_OPC_Decode, + 157, + 21, + 216, + 1, // Opcode: VLLEBRZF + /* 2932 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 2947 + /* 2937 */ MCD_OPC_CheckPredicate, + 29, + 20, + 0, + 0, // Skip to: 2962 + /* 2942 */ MCD_OPC_Decode, + 158, + 21, + 216, + 1, // Opcode: VLLEBRZG + /* 2947 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 2962 + /* 2952 */ MCD_OPC_CheckPredicate, + 29, + 5, + 0, + 0, // Skip to: 2962 + /* 2957 */ MCD_OPC_Decode, + 156, + 21, + 216, + 1, // Opcode: VLLEBRZE + /* 2962 */ MCD_OPC_CheckPredicate, + 29, + 53, + 79, + 0, // Skip to: 23244 + /* 2967 */ MCD_OPC_Decode, + 155, + 21, + 217, + 1, // Opcode: VLLEBRZ + /* 2972 */ MCD_OPC_FilterValue, + 5, + 66, + 0, + 0, // Skip to: 3043 + /* 2977 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 2980 */ MCD_OPC_FilterValue, + 0, + 35, + 79, + 0, // Skip to: 23244 + /* 2985 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 2988 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 3003 + /* 2993 */ MCD_OPC_CheckPredicate, + 29, + 35, + 0, + 0, // Skip to: 3033 + /* 2998 */ MCD_OPC_Decode, + 251, + 20, + 216, + 1, // Opcode: VLBRREPH + /* 3003 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 3018 + /* 3008 */ MCD_OPC_CheckPredicate, + 29, + 20, + 0, + 0, // Skip to: 3033 + /* 3013 */ MCD_OPC_Decode, + 249, + 20, + 216, + 1, // Opcode: VLBRREPF + /* 3018 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 3033 + /* 3023 */ MCD_OPC_CheckPredicate, + 29, + 5, + 0, + 0, // Skip to: 3033 + /* 3028 */ MCD_OPC_Decode, + 250, + 20, + 216, + 1, // Opcode: VLBRREPG + /* 3033 */ MCD_OPC_CheckPredicate, + 29, + 238, + 78, + 0, // Skip to: 23244 + /* 3038 */ MCD_OPC_Decode, + 248, + 20, + 217, + 1, // Opcode: VLBRREP + /* 3043 */ MCD_OPC_FilterValue, + 6, + 81, + 0, + 0, // Skip to: 3129 + /* 3048 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 3051 */ MCD_OPC_FilterValue, + 0, + 220, + 78, + 0, // Skip to: 23244 + /* 3056 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3059 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 3074 + /* 3064 */ MCD_OPC_CheckPredicate, + 29, + 50, + 0, + 0, // Skip to: 3119 + /* 3069 */ MCD_OPC_Decode, + 246, + 20, + 216, + 1, // Opcode: VLBRH + /* 3074 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 3089 + /* 3079 */ MCD_OPC_CheckPredicate, + 29, + 35, + 0, + 0, // Skip to: 3119 + /* 3084 */ MCD_OPC_Decode, + 244, + 20, + 216, + 1, // Opcode: VLBRF + /* 3089 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 3104 + /* 3094 */ MCD_OPC_CheckPredicate, + 29, + 20, + 0, + 0, // Skip to: 3119 + /* 3099 */ MCD_OPC_Decode, + 245, + 20, + 216, + 1, // Opcode: VLBRG + /* 3104 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 3119 + /* 3109 */ MCD_OPC_CheckPredicate, + 29, + 5, + 0, + 0, // Skip to: 3119 + /* 3114 */ MCD_OPC_Decode, + 247, + 20, + 216, + 1, // Opcode: VLBRQ + /* 3119 */ MCD_OPC_CheckPredicate, + 29, + 152, + 78, + 0, // Skip to: 23244 + /* 3124 */ MCD_OPC_Decode, + 243, + 20, + 217, + 1, // Opcode: VLBR + /* 3129 */ MCD_OPC_FilterValue, + 7, + 66, + 0, + 0, // Skip to: 3200 + /* 3134 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 3137 */ MCD_OPC_FilterValue, + 0, + 134, + 78, + 0, // Skip to: 23244 + /* 3142 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3145 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 3160 + /* 3150 */ MCD_OPC_CheckPredicate, + 29, + 35, + 0, + 0, // Skip to: 3190 + /* 3155 */ MCD_OPC_Decode, + 147, + 21, + 216, + 1, // Opcode: VLERH + /* 3160 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 3175 + /* 3165 */ MCD_OPC_CheckPredicate, + 29, + 20, + 0, + 0, // Skip to: 3190 + /* 3170 */ MCD_OPC_Decode, + 145, + 21, + 216, + 1, // Opcode: VLERF + /* 3175 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 3190 + /* 3180 */ MCD_OPC_CheckPredicate, + 29, + 5, + 0, + 0, // Skip to: 3190 + /* 3185 */ MCD_OPC_Decode, + 146, + 21, + 216, + 1, // Opcode: VLERG + /* 3190 */ MCD_OPC_CheckPredicate, + 29, + 81, + 78, + 0, // Skip to: 23244 + /* 3195 */ MCD_OPC_Decode, + 144, + 21, + 217, + 1, // Opcode: VLER + /* 3200 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 3222 + /* 3205 */ MCD_OPC_CheckPredicate, + 29, + 66, + 78, + 0, // Skip to: 23244 + /* 3210 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 59, + 78, + 0, // Skip to: 23244 + /* 3217 */ MCD_OPC_Decode, + 247, + 22, + 218, + 1, // Opcode: VSTEBRH + /* 3222 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 3244 + /* 3227 */ MCD_OPC_CheckPredicate, + 29, + 44, + 78, + 0, // Skip to: 23244 + /* 3232 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 37, + 78, + 0, // Skip to: 23244 + /* 3239 */ MCD_OPC_Decode, + 246, + 22, + 219, + 1, // Opcode: VSTEBRG + /* 3244 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 3266 + /* 3249 */ MCD_OPC_CheckPredicate, + 29, + 22, + 78, + 0, // Skip to: 23244 + /* 3254 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 15, + 78, + 0, // Skip to: 23244 + /* 3261 */ MCD_OPC_Decode, + 245, + 22, + 220, + 1, // Opcode: VSTEBRF + /* 3266 */ MCD_OPC_FilterValue, + 14, + 81, + 0, + 0, // Skip to: 3352 + /* 3271 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 3274 */ MCD_OPC_FilterValue, + 0, + 253, + 77, + 0, // Skip to: 23244 + /* 3279 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3282 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 3297 + /* 3287 */ MCD_OPC_CheckPredicate, + 29, + 50, + 0, + 0, // Skip to: 3342 + /* 3292 */ MCD_OPC_Decode, + 242, + 22, + 216, + 1, // Opcode: VSTBRH + /* 3297 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 3312 + /* 3302 */ MCD_OPC_CheckPredicate, + 29, + 35, + 0, + 0, // Skip to: 3342 + /* 3307 */ MCD_OPC_Decode, + 240, + 22, + 216, + 1, // Opcode: VSTBRF + /* 3312 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 3327 + /* 3317 */ MCD_OPC_CheckPredicate, + 29, + 20, + 0, + 0, // Skip to: 3342 + /* 3322 */ MCD_OPC_Decode, + 241, + 22, + 216, + 1, // Opcode: VSTBRG + /* 3327 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 3342 + /* 3332 */ MCD_OPC_CheckPredicate, + 29, + 5, + 0, + 0, // Skip to: 3342 + /* 3337 */ MCD_OPC_Decode, + 243, + 22, + 216, + 1, // Opcode: VSTBRQ + /* 3342 */ MCD_OPC_CheckPredicate, + 29, + 185, + 77, + 0, // Skip to: 23244 + /* 3347 */ MCD_OPC_Decode, + 239, + 22, + 217, + 1, // Opcode: VSTBR + /* 3352 */ MCD_OPC_FilterValue, + 15, + 66, + 0, + 0, // Skip to: 3423 + /* 3357 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 3360 */ MCD_OPC_FilterValue, + 0, + 167, + 77, + 0, // Skip to: 23244 + /* 3365 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 3368 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 3383 + /* 3373 */ MCD_OPC_CheckPredicate, + 29, + 35, + 0, + 0, // Skip to: 3413 + /* 3378 */ MCD_OPC_Decode, + 254, + 22, + 216, + 1, // Opcode: VSTERH + /* 3383 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 3398 + /* 3388 */ MCD_OPC_CheckPredicate, + 29, + 20, + 0, + 0, // Skip to: 3413 + /* 3393 */ MCD_OPC_Decode, + 252, + 22, + 216, + 1, // Opcode: VSTERF + /* 3398 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 3413 + /* 3403 */ MCD_OPC_CheckPredicate, + 29, + 5, + 0, + 0, // Skip to: 3413 + /* 3408 */ MCD_OPC_Decode, + 253, + 22, + 216, + 1, // Opcode: VSTERG + /* 3413 */ MCD_OPC_CheckPredicate, + 29, + 114, + 77, + 0, // Skip to: 23244 + /* 3418 */ MCD_OPC_Decode, + 251, + 22, + 217, + 1, // Opcode: VSTER + /* 3423 */ MCD_OPC_FilterValue, + 52, + 17, + 0, + 0, // Skip to: 3445 + /* 3428 */ MCD_OPC_CheckPredicate, + 30, + 99, + 77, + 0, // Skip to: 23244 + /* 3433 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 92, + 77, + 0, // Skip to: 23244 + /* 3440 */ MCD_OPC_Decode, + 177, + 22, + 221, + 1, // Opcode: VPKZ + /* 3445 */ MCD_OPC_FilterValue, + 53, + 17, + 0, + 0, // Skip to: 3467 + /* 3450 */ MCD_OPC_CheckPredicate, + 30, + 77, + 77, + 0, // Skip to: 23244 + /* 3455 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 70, + 77, + 0, // Skip to: 23244 + /* 3462 */ MCD_OPC_Decode, + 179, + 21, + 221, + 1, // Opcode: VLRL + /* 3467 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 3496 + /* 3472 */ MCD_OPC_CheckPredicate, + 30, + 55, + 77, + 0, // Skip to: 23244 + /* 3477 */ MCD_OPC_CheckField, + 36, + 4, + 0, + 48, + 77, + 0, // Skip to: 23244 + /* 3484 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 41, + 77, + 0, // Skip to: 23244 + /* 3491 */ MCD_OPC_Decode, + 180, + 21, + 222, + 1, // Opcode: VLRLR + /* 3496 */ MCD_OPC_FilterValue, + 60, + 17, + 0, + 0, // Skip to: 3518 + /* 3501 */ MCD_OPC_CheckPredicate, + 30, + 26, + 77, + 0, // Skip to: 23244 + /* 3506 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 19, + 77, + 0, // Skip to: 23244 + /* 3513 */ MCD_OPC_Decode, + 167, + 23, + 221, + 1, // Opcode: VUPKZ + /* 3518 */ MCD_OPC_FilterValue, + 61, + 17, + 0, + 0, // Skip to: 3540 + /* 3523 */ MCD_OPC_CheckPredicate, + 30, + 4, + 77, + 0, // Skip to: 23244 + /* 3528 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 253, + 76, + 0, // Skip to: 23244 + /* 3535 */ MCD_OPC_Decode, + 143, + 23, + 221, + 1, // Opcode: VSTRL + /* 3540 */ MCD_OPC_FilterValue, + 63, + 24, + 0, + 0, // Skip to: 3569 + /* 3545 */ MCD_OPC_CheckPredicate, + 30, + 238, + 76, + 0, // Skip to: 23244 + /* 3550 */ MCD_OPC_CheckField, + 36, + 4, + 0, + 231, + 76, + 0, // Skip to: 23244 + /* 3557 */ MCD_OPC_CheckField, + 9, + 3, + 0, + 224, + 76, + 0, // Skip to: 23244 + /* 3564 */ MCD_OPC_Decode, + 144, + 23, + 222, + 1, // Opcode: VSTRLR + /* 3569 */ MCD_OPC_FilterValue, + 73, + 24, + 0, + 0, // Skip to: 3598 + /* 3574 */ MCD_OPC_CheckPredicate, + 30, + 209, + 76, + 0, // Skip to: 23244 + /* 3579 */ MCD_OPC_CheckField, + 32, + 4, + 0, + 202, + 76, + 0, // Skip to: 23244 + /* 3586 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 195, + 76, + 0, // Skip to: 23244 + /* 3593 */ MCD_OPC_Decode, + 153, + 21, + 223, + 1, // Opcode: VLIP + /* 3598 */ MCD_OPC_FilterValue, + 80, + 51, + 0, + 0, // Skip to: 3654 + /* 3603 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 3606 */ MCD_OPC_FilterValue, + 0, + 177, + 76, + 0, // Skip to: 23244 + /* 3611 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3614 */ MCD_OPC_FilterValue, + 0, + 169, + 76, + 0, // Skip to: 23244 + /* 3619 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 3622 */ MCD_OPC_FilterValue, + 0, + 161, + 76, + 0, // Skip to: 23244 + /* 3627 */ MCD_OPC_CheckPredicate, + 30, + 12, + 0, + 0, // Skip to: 3644 + /* 3632 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 3644 + /* 3639 */ MCD_OPC_Decode, + 163, + 19, + 224, + 1, // Opcode: VCVB + /* 3644 */ MCD_OPC_CheckPredicate, + 31, + 139, + 76, + 0, // Skip to: 23244 + /* 3649 */ MCD_OPC_Decode, + 166, + 19, + 225, + 1, // Opcode: VCVBOpt + /* 3654 */ MCD_OPC_FilterValue, + 81, + 31, + 0, + 0, // Skip to: 3690 + /* 3659 */ MCD_OPC_CheckPredicate, + 32, + 124, + 76, + 0, // Skip to: 23244 + /* 3664 */ MCD_OPC_CheckField, + 24, + 8, + 0, + 117, + 76, + 0, // Skip to: 23244 + /* 3671 */ MCD_OPC_CheckField, + 12, + 8, + 0, + 110, + 76, + 0, // Skip to: 23244 + /* 3678 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 103, + 76, + 0, // Skip to: 23244 + /* 3685 */ MCD_OPC_Decode, + 149, + 19, + 226, + 1, // Opcode: VCLZDP + /* 3690 */ MCD_OPC_FilterValue, + 82, + 51, + 0, + 0, // Skip to: 3746 + /* 3695 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 3698 */ MCD_OPC_FilterValue, + 0, + 85, + 76, + 0, // Skip to: 23244 + /* 3703 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3706 */ MCD_OPC_FilterValue, + 0, + 77, + 76, + 0, // Skip to: 23244 + /* 3711 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 3714 */ MCD_OPC_FilterValue, + 0, + 69, + 76, + 0, // Skip to: 23244 + /* 3719 */ MCD_OPC_CheckPredicate, + 30, + 12, + 0, + 0, // Skip to: 3736 + /* 3724 */ MCD_OPC_CheckField, + 16, + 4, + 0, + 5, + 0, + 0, // Skip to: 3736 + /* 3731 */ MCD_OPC_Decode, + 164, + 19, + 227, + 1, // Opcode: VCVBG + /* 3736 */ MCD_OPC_CheckPredicate, + 31, + 47, + 76, + 0, // Skip to: 23244 + /* 3741 */ MCD_OPC_Decode, + 165, + 19, + 228, + 1, // Opcode: VCVBGOpt + /* 3746 */ MCD_OPC_FilterValue, + 84, + 31, + 0, + 0, // Skip to: 3782 + /* 3751 */ MCD_OPC_CheckPredicate, + 32, + 32, + 76, + 0, // Skip to: 23244 + /* 3756 */ MCD_OPC_CheckField, + 24, + 8, + 0, + 25, + 76, + 0, // Skip to: 23244 + /* 3763 */ MCD_OPC_CheckField, + 12, + 8, + 0, + 18, + 76, + 0, // Skip to: 23244 + /* 3770 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 11, + 76, + 0, // Skip to: 23244 + /* 3777 */ MCD_OPC_Decode, + 168, + 23, + 226, + 1, // Opcode: VUPKZH + /* 3782 */ MCD_OPC_FilterValue, + 85, + 24, + 0, + 0, // Skip to: 3811 + /* 3787 */ MCD_OPC_CheckPredicate, + 33, + 252, + 75, + 0, // Skip to: 23244 + /* 3792 */ MCD_OPC_CheckField, + 20, + 12, + 0, + 245, + 75, + 0, // Skip to: 23244 + /* 3799 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 238, + 75, + 0, // Skip to: 23244 + /* 3806 */ MCD_OPC_Decode, + 153, + 19, + 229, + 1, // Opcode: VCNF + /* 3811 */ MCD_OPC_FilterValue, + 86, + 24, + 0, + 0, // Skip to: 3840 + /* 3816 */ MCD_OPC_CheckPredicate, + 33, + 223, + 75, + 0, // Skip to: 23244 + /* 3821 */ MCD_OPC_CheckField, + 20, + 12, + 0, + 216, + 75, + 0, // Skip to: 23244 + /* 3828 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 209, + 75, + 0, // Skip to: 23244 + /* 3835 */ MCD_OPC_Decode, + 142, + 19, + 229, + 1, // Opcode: VCLFNH + /* 3840 */ MCD_OPC_FilterValue, + 88, + 24, + 0, + 0, // Skip to: 3869 + /* 3845 */ MCD_OPC_CheckPredicate, + 30, + 194, + 75, + 0, // Skip to: 23244 + /* 3850 */ MCD_OPC_CheckField, + 24, + 8, + 0, + 187, + 75, + 0, // Skip to: 23244 + /* 3857 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 180, + 75, + 0, // Skip to: 23244 + /* 3864 */ MCD_OPC_Decode, + 167, + 19, + 230, + 1, // Opcode: VCVD + /* 3869 */ MCD_OPC_FilterValue, + 89, + 17, + 0, + 0, // Skip to: 3891 + /* 3874 */ MCD_OPC_CheckPredicate, + 30, + 165, + 75, + 0, // Skip to: 23244 + /* 3879 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 158, + 75, + 0, // Skip to: 23244 + /* 3886 */ MCD_OPC_Decode, + 235, + 22, + 231, + 1, // Opcode: VSRP + /* 3891 */ MCD_OPC_FilterValue, + 90, + 24, + 0, + 0, // Skip to: 3920 + /* 3896 */ MCD_OPC_CheckPredicate, + 30, + 143, + 75, + 0, // Skip to: 23244 + /* 3901 */ MCD_OPC_CheckField, + 24, + 8, + 0, + 136, + 75, + 0, // Skip to: 23244 + /* 3908 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 129, + 75, + 0, // Skip to: 23244 + /* 3915 */ MCD_OPC_Decode, + 168, + 19, + 232, + 1, // Opcode: VCVDG + /* 3920 */ MCD_OPC_FilterValue, + 91, + 17, + 0, + 0, // Skip to: 3942 + /* 3925 */ MCD_OPC_CheckPredicate, + 30, + 114, + 75, + 0, // Skip to: 23244 + /* 3930 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 107, + 75, + 0, // Skip to: 23244 + /* 3937 */ MCD_OPC_Decode, + 184, + 22, + 231, + 1, // Opcode: VPSOP + /* 3942 */ MCD_OPC_FilterValue, + 92, + 31, + 0, + 0, // Skip to: 3978 + /* 3947 */ MCD_OPC_CheckPredicate, + 32, + 92, + 75, + 0, // Skip to: 23244 + /* 3952 */ MCD_OPC_CheckField, + 24, + 8, + 0, + 85, + 75, + 0, // Skip to: 23244 + /* 3959 */ MCD_OPC_CheckField, + 12, + 8, + 0, + 78, + 75, + 0, // Skip to: 23244 + /* 3966 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 71, + 75, + 0, // Skip to: 23244 + /* 3973 */ MCD_OPC_Decode, + 169, + 23, + 226, + 1, // Opcode: VUPKZL + /* 3978 */ MCD_OPC_FilterValue, + 93, + 24, + 0, + 0, // Skip to: 4007 + /* 3983 */ MCD_OPC_CheckPredicate, + 33, + 56, + 75, + 0, // Skip to: 23244 + /* 3988 */ MCD_OPC_CheckField, + 20, + 12, + 0, + 49, + 75, + 0, // Skip to: 23244 + /* 3995 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 42, + 75, + 0, // Skip to: 23244 + /* 4002 */ MCD_OPC_Decode, + 245, + 18, + 229, + 1, // Opcode: VCFN + /* 4007 */ MCD_OPC_FilterValue, + 94, + 24, + 0, + 0, // Skip to: 4036 + /* 4012 */ MCD_OPC_CheckPredicate, + 33, + 27, + 75, + 0, // Skip to: 23244 + /* 4017 */ MCD_OPC_CheckField, + 20, + 12, + 0, + 20, + 75, + 0, // Skip to: 23244 + /* 4024 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 13, + 75, + 0, // Skip to: 23244 + /* 4031 */ MCD_OPC_Decode, + 143, + 19, + 229, + 1, // Opcode: VCLFNL + /* 4036 */ MCD_OPC_FilterValue, + 95, + 31, + 0, + 0, // Skip to: 4072 + /* 4041 */ MCD_OPC_CheckPredicate, + 30, + 254, + 74, + 0, // Skip to: 23244 + /* 4046 */ MCD_OPC_CheckField, + 36, + 4, + 0, + 247, + 74, + 0, // Skip to: 23244 + /* 4053 */ MCD_OPC_CheckField, + 11, + 21, + 0, + 240, + 74, + 0, // Skip to: 23244 + /* 4060 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 233, + 74, + 0, // Skip to: 23244 + /* 4067 */ MCD_OPC_Decode, + 162, + 23, + 233, + 1, // Opcode: VTP + /* 4072 */ MCD_OPC_FilterValue, + 112, + 24, + 0, + 0, // Skip to: 4101 + /* 4077 */ MCD_OPC_CheckPredicate, + 32, + 218, + 74, + 0, // Skip to: 23244 + /* 4082 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 211, + 74, + 0, // Skip to: 23244 + /* 4089 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 204, + 74, + 0, // Skip to: 23244 + /* 4096 */ MCD_OPC_Decode, + 178, + 22, + 234, + 1, // Opcode: VPKZR + /* 4101 */ MCD_OPC_FilterValue, + 113, + 24, + 0, + 0, // Skip to: 4130 + /* 4106 */ MCD_OPC_CheckPredicate, + 30, + 189, + 74, + 0, // Skip to: 23244 + /* 4111 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 182, + 74, + 0, // Skip to: 23244 + /* 4118 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 175, + 74, + 0, // Skip to: 23244 + /* 4125 */ MCD_OPC_Decode, + 216, + 18, + 234, + 1, // Opcode: VAP + /* 4130 */ MCD_OPC_FilterValue, + 114, + 24, + 0, + 0, // Skip to: 4159 + /* 4135 */ MCD_OPC_CheckPredicate, + 32, + 160, + 74, + 0, // Skip to: 23244 + /* 4140 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 153, + 74, + 0, // Skip to: 23244 + /* 4147 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 146, + 74, + 0, // Skip to: 23244 + /* 4154 */ MCD_OPC_Decode, + 236, + 22, + 234, + 1, // Opcode: VSRPR + /* 4159 */ MCD_OPC_FilterValue, + 115, + 24, + 0, + 0, // Skip to: 4188 + /* 4164 */ MCD_OPC_CheckPredicate, + 30, + 131, + 74, + 0, // Skip to: 23244 + /* 4169 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 124, + 74, + 0, // Skip to: 23244 + /* 4176 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 117, + 74, + 0, // Skip to: 23244 + /* 4183 */ MCD_OPC_Decode, + 228, + 22, + 234, + 1, // Opcode: VSP + /* 4188 */ MCD_OPC_FilterValue, + 116, + 82, + 0, + 0, // Skip to: 4275 + /* 4193 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 4196 */ MCD_OPC_FilterValue, + 0, + 99, + 74, + 0, // Skip to: 23244 + /* 4201 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 4204 */ MCD_OPC_FilterValue, + 0, + 91, + 74, + 0, // Skip to: 23244 + /* 4209 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 4212 */ MCD_OPC_FilterValue, + 0, + 83, + 74, + 0, // Skip to: 23244 + /* 4217 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4220 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 4235 + /* 4225 */ MCD_OPC_CheckPredicate, + 32, + 35, + 0, + 0, // Skip to: 4265 + /* 4230 */ MCD_OPC_Decode, + 212, + 22, + 235, + 1, // Opcode: VSCHSP + /* 4235 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 4250 + /* 4240 */ MCD_OPC_CheckPredicate, + 32, + 20, + 0, + 0, // Skip to: 4265 + /* 4245 */ MCD_OPC_Decode, + 210, + 22, + 235, + 1, // Opcode: VSCHDP + /* 4250 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 4265 + /* 4255 */ MCD_OPC_CheckPredicate, + 32, + 5, + 0, + 0, // Skip to: 4265 + /* 4260 */ MCD_OPC_Decode, + 213, + 22, + 235, + 1, // Opcode: VSCHXP + /* 4265 */ MCD_OPC_CheckPredicate, + 32, + 30, + 74, + 0, // Skip to: 23244 + /* 4270 */ MCD_OPC_Decode, + 211, + 22, + 236, + 1, // Opcode: VSCHP + /* 4275 */ MCD_OPC_FilterValue, + 117, + 24, + 0, + 0, // Skip to: 4304 + /* 4280 */ MCD_OPC_CheckPredicate, + 33, + 15, + 74, + 0, // Skip to: 23244 + /* 4285 */ MCD_OPC_CheckField, + 20, + 8, + 0, + 8, + 74, + 0, // Skip to: 23244 + /* 4292 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 1, + 74, + 0, // Skip to: 23244 + /* 4299 */ MCD_OPC_Decode, + 155, + 19, + 237, + 1, // Opcode: VCRNF + /* 4304 */ MCD_OPC_FilterValue, + 119, + 38, + 0, + 0, // Skip to: 4347 + /* 4309 */ MCD_OPC_CheckPredicate, + 30, + 242, + 73, + 0, // Skip to: 23244 + /* 4314 */ MCD_OPC_CheckField, + 36, + 4, + 0, + 235, + 73, + 0, // Skip to: 23244 + /* 4321 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 228, + 73, + 0, // Skip to: 23244 + /* 4328 */ MCD_OPC_CheckField, + 11, + 9, + 0, + 221, + 73, + 0, // Skip to: 23244 + /* 4335 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 214, + 73, + 0, // Skip to: 23244 + /* 4342 */ MCD_OPC_Decode, + 154, + 19, + 238, + 1, // Opcode: VCP + /* 4347 */ MCD_OPC_FilterValue, + 120, + 24, + 0, + 0, // Skip to: 4376 + /* 4352 */ MCD_OPC_CheckPredicate, + 30, + 199, + 73, + 0, // Skip to: 23244 + /* 4357 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 192, + 73, + 0, // Skip to: 23244 + /* 4364 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 185, + 73, + 0, // Skip to: 23244 + /* 4371 */ MCD_OPC_Decode, + 253, + 21, + 234, + 1, // Opcode: VMP + /* 4376 */ MCD_OPC_FilterValue, + 121, + 24, + 0, + 0, // Skip to: 4405 + /* 4381 */ MCD_OPC_CheckPredicate, + 30, + 170, + 73, + 0, // Skip to: 23244 + /* 4386 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 163, + 73, + 0, // Skip to: 23244 + /* 4393 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 156, + 73, + 0, // Skip to: 23244 + /* 4400 */ MCD_OPC_Decode, + 138, + 22, + 234, + 1, // Opcode: VMSP + /* 4405 */ MCD_OPC_FilterValue, + 122, + 24, + 0, + 0, // Skip to: 4434 + /* 4410 */ MCD_OPC_CheckPredicate, + 30, + 141, + 73, + 0, // Skip to: 23244 + /* 4415 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 134, + 73, + 0, // Skip to: 23244 + /* 4422 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 127, + 73, + 0, // Skip to: 23244 + /* 4429 */ MCD_OPC_Decode, + 169, + 19, + 234, + 1, // Opcode: VDP + /* 4434 */ MCD_OPC_FilterValue, + 123, + 24, + 0, + 0, // Skip to: 4463 + /* 4439 */ MCD_OPC_CheckPredicate, + 30, + 112, + 73, + 0, // Skip to: 23244 + /* 4444 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 105, + 73, + 0, // Skip to: 23244 + /* 4451 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 98, + 73, + 0, // Skip to: 23244 + /* 4458 */ MCD_OPC_Decode, + 195, + 22, + 234, + 1, // Opcode: VRP + /* 4463 */ MCD_OPC_FilterValue, + 124, + 24, + 0, + 0, // Skip to: 4492 + /* 4468 */ MCD_OPC_CheckPredicate, + 32, + 83, + 73, + 0, // Skip to: 23244 + /* 4473 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 76, + 73, + 0, // Skip to: 23244 + /* 4480 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 69, + 73, + 0, // Skip to: 23244 + /* 4487 */ MCD_OPC_Decode, + 214, + 22, + 239, + 1, // Opcode: VSCSHP + /* 4492 */ MCD_OPC_FilterValue, + 125, + 31, + 0, + 0, // Skip to: 4528 + /* 4497 */ MCD_OPC_CheckPredicate, + 32, + 54, + 73, + 0, // Skip to: 23244 + /* 4502 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 47, + 73, + 0, // Skip to: 23244 + /* 4509 */ MCD_OPC_CheckField, + 12, + 8, + 0, + 40, + 73, + 0, // Skip to: 23244 + /* 4516 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 33, + 73, + 0, // Skip to: 23244 + /* 4523 */ MCD_OPC_Decode, + 157, + 19, + 235, + 1, // Opcode: VCSPH + /* 4528 */ MCD_OPC_FilterValue, + 126, + 23, + 73, + 0, // Skip to: 23244 + /* 4533 */ MCD_OPC_CheckPredicate, + 30, + 18, + 73, + 0, // Skip to: 23244 + /* 4538 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 11, + 73, + 0, // Skip to: 23244 + /* 4545 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 4, + 73, + 0, // Skip to: 23244 + /* 4552 */ MCD_OPC_Decode, + 215, + 22, + 234, + 1, // Opcode: VSDP + /* 4557 */ MCD_OPC_FilterValue, + 231, + 1, + 88, + 49, + 0, // Skip to: 17195 + /* 4563 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 4566 */ MCD_OPC_FilterValue, + 0, + 17, + 0, + 0, // Skip to: 4588 + /* 4571 */ MCD_OPC_CheckPredicate, + 34, + 236, + 72, + 0, // Skip to: 23244 + /* 4576 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 229, + 72, + 0, // Skip to: 23244 + /* 4583 */ MCD_OPC_Decode, + 131, + 21, + 240, + 1, // Opcode: VLEB + /* 4588 */ MCD_OPC_FilterValue, + 1, + 17, + 0, + 0, // Skip to: 4610 + /* 4593 */ MCD_OPC_CheckPredicate, + 34, + 214, + 72, + 0, // Skip to: 23244 + /* 4598 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 207, + 72, + 0, // Skip to: 23244 + /* 4605 */ MCD_OPC_Decode, + 139, + 21, + 213, + 1, // Opcode: VLEH + /* 4610 */ MCD_OPC_FilterValue, + 2, + 17, + 0, + 0, // Skip to: 4632 + /* 4615 */ MCD_OPC_CheckPredicate, + 34, + 192, + 72, + 0, // Skip to: 23244 + /* 4620 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 185, + 72, + 0, // Skip to: 23244 + /* 4627 */ MCD_OPC_Decode, + 138, + 21, + 214, + 1, // Opcode: VLEG + /* 4632 */ MCD_OPC_FilterValue, + 3, + 17, + 0, + 0, // Skip to: 4654 + /* 4637 */ MCD_OPC_CheckPredicate, + 34, + 170, + 72, + 0, // Skip to: 23244 + /* 4642 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 163, + 72, + 0, // Skip to: 23244 + /* 4649 */ MCD_OPC_Decode, + 137, + 21, + 215, + 1, // Opcode: VLEF + /* 4654 */ MCD_OPC_FilterValue, + 4, + 96, + 0, + 0, // Skip to: 4755 + /* 4659 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 4662 */ MCD_OPC_FilterValue, + 0, + 145, + 72, + 0, // Skip to: 23244 + /* 4667 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4670 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4685 + /* 4675 */ MCD_OPC_CheckPredicate, + 34, + 65, + 0, + 0, // Skip to: 4745 + /* 4680 */ MCD_OPC_Decode, + 161, + 21, + 216, + 1, // Opcode: VLLEZB + /* 4685 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4700 + /* 4690 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 4745 + /* 4695 */ MCD_OPC_Decode, + 164, + 21, + 216, + 1, // Opcode: VLLEZH + /* 4700 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 4715 + /* 4705 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 4745 + /* 4710 */ MCD_OPC_Decode, + 162, + 21, + 216, + 1, // Opcode: VLLEZF + /* 4715 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 4730 + /* 4720 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 4745 + /* 4725 */ MCD_OPC_Decode, + 163, + 21, + 216, + 1, // Opcode: VLLEZG + /* 4730 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 4745 + /* 4735 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 4745 + /* 4740 */ MCD_OPC_Decode, + 165, + 21, + 216, + 1, // Opcode: VLLEZLF + /* 4745 */ MCD_OPC_CheckPredicate, + 34, + 62, + 72, + 0, // Skip to: 23244 + /* 4750 */ MCD_OPC_Decode, + 160, + 21, + 217, + 1, // Opcode: VLLEZ + /* 4755 */ MCD_OPC_FilterValue, + 5, + 81, + 0, + 0, // Skip to: 4841 + /* 4760 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 4763 */ MCD_OPC_FilterValue, + 0, + 44, + 72, + 0, // Skip to: 23244 + /* 4768 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 4771 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 4786 + /* 4776 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 4831 + /* 4781 */ MCD_OPC_Decode, + 175, + 21, + 216, + 1, // Opcode: VLREPB + /* 4786 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 4801 + /* 4791 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 4831 + /* 4796 */ MCD_OPC_Decode, + 178, + 21, + 216, + 1, // Opcode: VLREPH + /* 4801 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 4816 + /* 4806 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 4831 + /* 4811 */ MCD_OPC_Decode, + 176, + 21, + 216, + 1, // Opcode: VLREPF + /* 4816 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 4831 + /* 4821 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 4831 + /* 4826 */ MCD_OPC_Decode, + 177, + 21, + 216, + 1, // Opcode: VLREPG + /* 4831 */ MCD_OPC_CheckPredicate, + 34, + 232, + 71, + 0, // Skip to: 23244 + /* 4836 */ MCD_OPC_Decode, + 174, + 21, + 217, + 1, // Opcode: VLREP + /* 4841 */ MCD_OPC_FilterValue, + 6, + 35, + 0, + 0, // Skip to: 4881 + /* 4846 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 4849 */ MCD_OPC_FilterValue, + 0, + 214, + 71, + 0, // Skip to: 23244 + /* 4854 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 4871 + /* 4859 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 5, + 0, + 0, // Skip to: 4871 + /* 4866 */ MCD_OPC_Decode, + 240, + 20, + 216, + 1, // Opcode: VL + /* 4871 */ MCD_OPC_CheckPredicate, + 34, + 192, + 71, + 0, // Skip to: 23244 + /* 4876 */ MCD_OPC_Decode, + 241, + 20, + 217, + 1, // Opcode: VLAlign + /* 4881 */ MCD_OPC_FilterValue, + 7, + 17, + 0, + 0, // Skip to: 4903 + /* 4886 */ MCD_OPC_CheckPredicate, + 34, + 177, + 71, + 0, // Skip to: 23244 + /* 4891 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 170, + 71, + 0, // Skip to: 23244 + /* 4898 */ MCD_OPC_Decode, + 242, + 20, + 217, + 1, // Opcode: VLBB + /* 4903 */ MCD_OPC_FilterValue, + 8, + 17, + 0, + 0, // Skip to: 4925 + /* 4908 */ MCD_OPC_CheckPredicate, + 34, + 155, + 71, + 0, // Skip to: 23244 + /* 4913 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 148, + 71, + 0, // Skip to: 23244 + /* 4920 */ MCD_OPC_Decode, + 244, + 22, + 217, + 1, // Opcode: VSTEB + /* 4925 */ MCD_OPC_FilterValue, + 9, + 17, + 0, + 0, // Skip to: 4947 + /* 4930 */ MCD_OPC_CheckPredicate, + 34, + 133, + 71, + 0, // Skip to: 23244 + /* 4935 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 126, + 71, + 0, // Skip to: 23244 + /* 4942 */ MCD_OPC_Decode, + 250, + 22, + 218, + 1, // Opcode: VSTEH + /* 4947 */ MCD_OPC_FilterValue, + 10, + 17, + 0, + 0, // Skip to: 4969 + /* 4952 */ MCD_OPC_CheckPredicate, + 34, + 111, + 71, + 0, // Skip to: 23244 + /* 4957 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 104, + 71, + 0, // Skip to: 23244 + /* 4964 */ MCD_OPC_Decode, + 249, + 22, + 219, + 1, // Opcode: VSTEG + /* 4969 */ MCD_OPC_FilterValue, + 11, + 17, + 0, + 0, // Skip to: 4991 + /* 4974 */ MCD_OPC_CheckPredicate, + 34, + 89, + 71, + 0, // Skip to: 23244 + /* 4979 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 82, + 71, + 0, // Skip to: 23244 + /* 4986 */ MCD_OPC_Decode, + 248, + 22, + 220, + 1, // Opcode: VSTEF + /* 4991 */ MCD_OPC_FilterValue, + 14, + 35, + 0, + 0, // Skip to: 5031 + /* 4996 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 4999 */ MCD_OPC_FilterValue, + 0, + 64, + 71, + 0, // Skip to: 23244 + /* 5004 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 5021 + /* 5009 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 5, + 0, + 0, // Skip to: 5021 + /* 5016 */ MCD_OPC_Decode, + 237, + 22, + 216, + 1, // Opcode: VST + /* 5021 */ MCD_OPC_CheckPredicate, + 34, + 42, + 71, + 0, // Skip to: 23244 + /* 5026 */ MCD_OPC_Decode, + 238, + 22, + 217, + 1, // Opcode: VSTAlign + /* 5031 */ MCD_OPC_FilterValue, + 18, + 17, + 0, + 0, // Skip to: 5053 + /* 5036 */ MCD_OPC_CheckPredicate, + 34, + 27, + 71, + 0, // Skip to: 23244 + /* 5041 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 20, + 71, + 0, // Skip to: 23244 + /* 5048 */ MCD_OPC_Decode, + 217, + 20, + 241, + 1, // Opcode: VGEG + /* 5053 */ MCD_OPC_FilterValue, + 19, + 17, + 0, + 0, // Skip to: 5075 + /* 5058 */ MCD_OPC_CheckPredicate, + 34, + 5, + 71, + 0, // Skip to: 23244 + /* 5063 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 254, + 70, + 0, // Skip to: 23244 + /* 5070 */ MCD_OPC_Decode, + 216, + 20, + 242, + 1, // Opcode: VGEF + /* 5075 */ MCD_OPC_FilterValue, + 26, + 17, + 0, + 0, // Skip to: 5097 + /* 5080 */ MCD_OPC_CheckPredicate, + 34, + 239, + 70, + 0, // Skip to: 23244 + /* 5085 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 232, + 70, + 0, // Skip to: 23244 + /* 5092 */ MCD_OPC_Decode, + 209, + 22, + 243, + 1, // Opcode: VSCEG + /* 5097 */ MCD_OPC_FilterValue, + 27, + 17, + 0, + 0, // Skip to: 5119 + /* 5102 */ MCD_OPC_CheckPredicate, + 34, + 217, + 70, + 0, // Skip to: 23244 + /* 5107 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 210, + 70, + 0, // Skip to: 23244 + /* 5114 */ MCD_OPC_Decode, + 208, + 22, + 244, + 1, // Opcode: VSCEF + /* 5119 */ MCD_OPC_FilterValue, + 33, + 89, + 0, + 0, // Skip to: 5213 + /* 5124 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 5127 */ MCD_OPC_FilterValue, + 0, + 192, + 70, + 0, // Skip to: 23244 + /* 5132 */ MCD_OPC_ExtractField, + 11, + 1, // Inst{11} ... + /* 5135 */ MCD_OPC_FilterValue, + 0, + 184, + 70, + 0, // Skip to: 23244 + /* 5140 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5143 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5158 + /* 5148 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 5203 + /* 5153 */ MCD_OPC_Decode, + 149, + 21, + 245, + 1, // Opcode: VLGVB + /* 5158 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5173 + /* 5163 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 5203 + /* 5168 */ MCD_OPC_Decode, + 152, + 21, + 245, + 1, // Opcode: VLGVH + /* 5173 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5188 + /* 5178 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 5203 + /* 5183 */ MCD_OPC_Decode, + 150, + 21, + 245, + 1, // Opcode: VLGVF + /* 5188 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5203 + /* 5193 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 5203 + /* 5198 */ MCD_OPC_Decode, + 151, + 21, + 245, + 1, // Opcode: VLGVG + /* 5203 */ MCD_OPC_CheckPredicate, + 34, + 116, + 70, + 0, // Skip to: 23244 + /* 5208 */ MCD_OPC_Decode, + 148, + 21, + 246, + 1, // Opcode: VLGV + /* 5213 */ MCD_OPC_FilterValue, + 34, + 81, + 0, + 0, // Skip to: 5299 + /* 5218 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 5221 */ MCD_OPC_FilterValue, + 0, + 98, + 70, + 0, // Skip to: 23244 + /* 5226 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5229 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5244 + /* 5234 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 5289 + /* 5239 */ MCD_OPC_Decode, + 182, + 21, + 247, + 1, // Opcode: VLVGB + /* 5244 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5259 + /* 5249 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 5289 + /* 5254 */ MCD_OPC_Decode, + 185, + 21, + 247, + 1, // Opcode: VLVGH + /* 5259 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5274 + /* 5264 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 5289 + /* 5269 */ MCD_OPC_Decode, + 183, + 21, + 247, + 1, // Opcode: VLVGF + /* 5274 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5289 + /* 5279 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 5289 + /* 5284 */ MCD_OPC_Decode, + 184, + 21, + 248, + 1, // Opcode: VLVGG + /* 5289 */ MCD_OPC_CheckPredicate, + 34, + 30, + 70, + 0, // Skip to: 23244 + /* 5294 */ MCD_OPC_Decode, + 181, + 21, + 249, + 1, // Opcode: VLVG + /* 5299 */ MCD_OPC_FilterValue, + 39, + 17, + 0, + 0, // Skip to: 5321 + /* 5304 */ MCD_OPC_CheckPredicate, + 34, + 15, + 70, + 0, // Skip to: 23244 + /* 5309 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 8, + 70, + 0, // Skip to: 23244 + /* 5316 */ MCD_OPC_Decode, + 164, + 11, + 250, + 1, // Opcode: LCBB + /* 5321 */ MCD_OPC_FilterValue, + 48, + 81, + 0, + 0, // Skip to: 5407 + /* 5326 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 5329 */ MCD_OPC_FilterValue, + 0, + 246, + 69, + 0, // Skip to: 23244 + /* 5334 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5337 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5352 + /* 5342 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 5397 + /* 5347 */ MCD_OPC_Decode, + 196, + 19, + 251, + 1, // Opcode: VESLB + /* 5352 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5367 + /* 5357 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 5397 + /* 5362 */ MCD_OPC_Decode, + 199, + 19, + 251, + 1, // Opcode: VESLH + /* 5367 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5382 + /* 5372 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 5397 + /* 5377 */ MCD_OPC_Decode, + 197, + 19, + 251, + 1, // Opcode: VESLF + /* 5382 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5397 + /* 5387 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 5397 + /* 5392 */ MCD_OPC_Decode, + 198, + 19, + 251, + 1, // Opcode: VESLG + /* 5397 */ MCD_OPC_CheckPredicate, + 34, + 178, + 69, + 0, // Skip to: 23244 + /* 5402 */ MCD_OPC_Decode, + 195, + 19, + 252, + 1, // Opcode: VESL + /* 5407 */ MCD_OPC_FilterValue, + 51, + 81, + 0, + 0, // Skip to: 5493 + /* 5412 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 5415 */ MCD_OPC_FilterValue, + 0, + 160, + 69, + 0, // Skip to: 23244 + /* 5420 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5423 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5438 + /* 5428 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 5483 + /* 5433 */ MCD_OPC_Decode, + 186, + 19, + 251, + 1, // Opcode: VERLLB + /* 5438 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5453 + /* 5443 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 5483 + /* 5448 */ MCD_OPC_Decode, + 189, + 19, + 251, + 1, // Opcode: VERLLH + /* 5453 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5468 + /* 5458 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 5483 + /* 5463 */ MCD_OPC_Decode, + 187, + 19, + 251, + 1, // Opcode: VERLLF + /* 5468 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5483 + /* 5473 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 5483 + /* 5478 */ MCD_OPC_Decode, + 188, + 19, + 251, + 1, // Opcode: VERLLG + /* 5483 */ MCD_OPC_CheckPredicate, + 34, + 92, + 69, + 0, // Skip to: 23244 + /* 5488 */ MCD_OPC_Decode, + 185, + 19, + 252, + 1, // Opcode: VERLL + /* 5493 */ MCD_OPC_FilterValue, + 54, + 35, + 0, + 0, // Skip to: 5533 + /* 5498 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 5501 */ MCD_OPC_FilterValue, + 0, + 74, + 69, + 0, // Skip to: 23244 + /* 5506 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 5523 + /* 5511 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 5, + 0, + 0, // Skip to: 5523 + /* 5518 */ MCD_OPC_Decode, + 166, + 21, + 253, + 1, // Opcode: VLM + /* 5523 */ MCD_OPC_CheckPredicate, + 34, + 52, + 69, + 0, // Skip to: 23244 + /* 5528 */ MCD_OPC_Decode, + 167, + 21, + 254, + 1, // Opcode: VLMAlign + /* 5533 */ MCD_OPC_FilterValue, + 55, + 24, + 0, + 0, // Skip to: 5562 + /* 5538 */ MCD_OPC_CheckPredicate, + 34, + 37, + 69, + 0, // Skip to: 23244 + /* 5543 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 30, + 69, + 0, // Skip to: 23244 + /* 5550 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 23, + 69, + 0, // Skip to: 23244 + /* 5557 */ MCD_OPC_Decode, + 154, + 21, + 255, + 1, // Opcode: VLL + /* 5562 */ MCD_OPC_FilterValue, + 56, + 81, + 0, + 0, // Skip to: 5648 + /* 5567 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 5570 */ MCD_OPC_FilterValue, + 0, + 5, + 69, + 0, // Skip to: 23244 + /* 5575 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5578 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5593 + /* 5583 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 5638 + /* 5588 */ MCD_OPC_Decode, + 216, + 19, + 251, + 1, // Opcode: VESRLB + /* 5593 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5608 + /* 5598 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 5638 + /* 5603 */ MCD_OPC_Decode, + 219, + 19, + 251, + 1, // Opcode: VESRLH + /* 5608 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5623 + /* 5613 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 5638 + /* 5618 */ MCD_OPC_Decode, + 217, + 19, + 251, + 1, // Opcode: VESRLF + /* 5623 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5638 + /* 5628 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 5638 + /* 5633 */ MCD_OPC_Decode, + 218, + 19, + 251, + 1, // Opcode: VESRLG + /* 5638 */ MCD_OPC_CheckPredicate, + 34, + 193, + 68, + 0, // Skip to: 23244 + /* 5643 */ MCD_OPC_Decode, + 215, + 19, + 252, + 1, // Opcode: VESRL + /* 5648 */ MCD_OPC_FilterValue, + 58, + 81, + 0, + 0, // Skip to: 5734 + /* 5653 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 5656 */ MCD_OPC_FilterValue, + 0, + 175, + 68, + 0, // Skip to: 23244 + /* 5661 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5664 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5679 + /* 5669 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 5724 + /* 5674 */ MCD_OPC_Decode, + 206, + 19, + 251, + 1, // Opcode: VESRAB + /* 5679 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 5694 + /* 5684 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 5724 + /* 5689 */ MCD_OPC_Decode, + 209, + 19, + 251, + 1, // Opcode: VESRAH + /* 5694 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 5709 + /* 5699 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 5724 + /* 5704 */ MCD_OPC_Decode, + 207, + 19, + 251, + 1, // Opcode: VESRAF + /* 5709 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 5724 + /* 5714 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 5724 + /* 5719 */ MCD_OPC_Decode, + 208, + 19, + 251, + 1, // Opcode: VESRAG + /* 5724 */ MCD_OPC_CheckPredicate, + 34, + 107, + 68, + 0, // Skip to: 23244 + /* 5729 */ MCD_OPC_Decode, + 205, + 19, + 252, + 1, // Opcode: VESRA + /* 5734 */ MCD_OPC_FilterValue, + 62, + 35, + 0, + 0, // Skip to: 5774 + /* 5739 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 5742 */ MCD_OPC_FilterValue, + 0, + 89, + 68, + 0, // Skip to: 23244 + /* 5747 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 5764 + /* 5752 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 5, + 0, + 0, // Skip to: 5764 + /* 5759 */ MCD_OPC_Decode, + 128, + 23, + 253, + 1, // Opcode: VSTM + /* 5764 */ MCD_OPC_CheckPredicate, + 34, + 67, + 68, + 0, // Skip to: 23244 + /* 5769 */ MCD_OPC_Decode, + 129, + 23, + 254, + 1, // Opcode: VSTMAlign + /* 5774 */ MCD_OPC_FilterValue, + 63, + 24, + 0, + 0, // Skip to: 5803 + /* 5779 */ MCD_OPC_CheckPredicate, + 34, + 52, + 68, + 0, // Skip to: 23244 + /* 5784 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 45, + 68, + 0, // Skip to: 23244 + /* 5791 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 38, + 68, + 0, // Skip to: 23244 + /* 5798 */ MCD_OPC_Decode, + 255, + 22, + 255, + 1, // Opcode: VSTL + /* 5803 */ MCD_OPC_FilterValue, + 64, + 24, + 0, + 0, // Skip to: 5832 + /* 5808 */ MCD_OPC_CheckPredicate, + 34, + 23, + 68, + 0, // Skip to: 23244 + /* 5813 */ MCD_OPC_CheckField, + 32, + 4, + 0, + 16, + 68, + 0, // Skip to: 23244 + /* 5820 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 9, + 68, + 0, // Skip to: 23244 + /* 5827 */ MCD_OPC_Decode, + 140, + 21, + 128, + 2, // Opcode: VLEIB + /* 5832 */ MCD_OPC_FilterValue, + 65, + 24, + 0, + 0, // Skip to: 5861 + /* 5837 */ MCD_OPC_CheckPredicate, + 34, + 250, + 67, + 0, // Skip to: 23244 + /* 5842 */ MCD_OPC_CheckField, + 32, + 4, + 0, + 243, + 67, + 0, // Skip to: 23244 + /* 5849 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 236, + 67, + 0, // Skip to: 23244 + /* 5856 */ MCD_OPC_Decode, + 143, + 21, + 129, + 2, // Opcode: VLEIH + /* 5861 */ MCD_OPC_FilterValue, + 66, + 24, + 0, + 0, // Skip to: 5890 + /* 5866 */ MCD_OPC_CheckPredicate, + 34, + 221, + 67, + 0, // Skip to: 23244 + /* 5871 */ MCD_OPC_CheckField, + 32, + 4, + 0, + 214, + 67, + 0, // Skip to: 23244 + /* 5878 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 207, + 67, + 0, // Skip to: 23244 + /* 5885 */ MCD_OPC_Decode, + 142, + 21, + 130, + 2, // Opcode: VLEIG + /* 5890 */ MCD_OPC_FilterValue, + 67, + 24, + 0, + 0, // Skip to: 5919 + /* 5895 */ MCD_OPC_CheckPredicate, + 34, + 192, + 67, + 0, // Skip to: 23244 + /* 5900 */ MCD_OPC_CheckField, + 32, + 4, + 0, + 185, + 67, + 0, // Skip to: 23244 + /* 5907 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 178, + 67, + 0, // Skip to: 23244 + /* 5914 */ MCD_OPC_Decode, + 141, + 21, + 131, + 2, // Opcode: VLEIF + /* 5919 */ MCD_OPC_FilterValue, + 68, + 69, + 0, + 0, // Skip to: 5993 + /* 5924 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 5927 */ MCD_OPC_FilterValue, + 0, + 160, + 67, + 0, // Skip to: 23244 + /* 5932 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 5935 */ MCD_OPC_FilterValue, + 0, + 152, + 67, + 0, // Skip to: 23244 + /* 5940 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 5943 */ MCD_OPC_FilterValue, + 0, + 144, + 67, + 0, // Skip to: 23244 + /* 5948 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 5951 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 5966 + /* 5956 */ MCD_OPC_CheckPredicate, + 34, + 22, + 0, + 0, // Skip to: 5983 + /* 5961 */ MCD_OPC_Decode, + 183, + 23, + 132, + 2, // Opcode: VZERO + /* 5966 */ MCD_OPC_FilterValue, + 255, + 255, + 3, + 10, + 0, + 0, // Skip to: 5983 + /* 5973 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 5983 + /* 5978 */ MCD_OPC_Decode, + 156, + 22, + 132, + 2, // Opcode: VONE + /* 5983 */ MCD_OPC_CheckPredicate, + 34, + 104, + 67, + 0, // Skip to: 23244 + /* 5988 */ MCD_OPC_Decode, + 215, + 20, + 133, + 2, // Opcode: VGBM + /* 5993 */ MCD_OPC_FilterValue, + 69, + 89, + 0, + 0, // Skip to: 6087 + /* 5998 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 6001 */ MCD_OPC_FilterValue, + 0, + 86, + 67, + 0, // Skip to: 23244 + /* 6006 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 6009 */ MCD_OPC_FilterValue, + 0, + 78, + 67, + 0, // Skip to: 23244 + /* 6014 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6017 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6032 + /* 6022 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 6077 + /* 6027 */ MCD_OPC_Decode, + 191, + 22, + 134, + 2, // Opcode: VREPIB + /* 6032 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6047 + /* 6037 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 6077 + /* 6042 */ MCD_OPC_Decode, + 194, + 22, + 134, + 2, // Opcode: VREPIH + /* 6047 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6062 + /* 6052 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 6077 + /* 6057 */ MCD_OPC_Decode, + 192, + 22, + 134, + 2, // Opcode: VREPIF + /* 6062 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 6077 + /* 6067 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 6077 + /* 6072 */ MCD_OPC_Decode, + 193, + 22, + 134, + 2, // Opcode: VREPIG + /* 6077 */ MCD_OPC_CheckPredicate, + 34, + 10, + 67, + 0, // Skip to: 23244 + /* 6082 */ MCD_OPC_Decode, + 190, + 22, + 135, + 2, // Opcode: VREPI + /* 6087 */ MCD_OPC_FilterValue, + 70, + 89, + 0, + 0, // Skip to: 6181 + /* 6092 */ MCD_OPC_ExtractField, + 8, + 3, // Inst{10-8} ... + /* 6095 */ MCD_OPC_FilterValue, + 0, + 248, + 66, + 0, // Skip to: 23244 + /* 6100 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 6103 */ MCD_OPC_FilterValue, + 0, + 240, + 66, + 0, // Skip to: 23244 + /* 6108 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6111 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6126 + /* 6116 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 6171 + /* 6121 */ MCD_OPC_Decode, + 229, + 20, + 136, + 2, // Opcode: VGMB + /* 6126 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6141 + /* 6131 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 6171 + /* 6136 */ MCD_OPC_Decode, + 232, + 20, + 136, + 2, // Opcode: VGMH + /* 6141 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6156 + /* 6146 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 6171 + /* 6151 */ MCD_OPC_Decode, + 230, + 20, + 136, + 2, // Opcode: VGMF + /* 6156 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 6171 + /* 6161 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 6171 + /* 6166 */ MCD_OPC_Decode, + 231, + 20, + 136, + 2, // Opcode: VGMG + /* 6171 */ MCD_OPC_CheckPredicate, + 34, + 172, + 66, + 0, // Skip to: 23244 + /* 6176 */ MCD_OPC_Decode, + 228, + 20, + 137, + 2, // Opcode: VGM + /* 6181 */ MCD_OPC_FilterValue, + 74, + 99, + 0, + 0, // Skip to: 6285 + /* 6186 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 6189 */ MCD_OPC_FilterValue, + 0, + 154, + 66, + 0, // Skip to: 23244 + /* 6194 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 6197 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6212 + /* 6202 */ MCD_OPC_CheckPredicate, + 35, + 68, + 0, + 0, // Skip to: 6275 + /* 6207 */ MCD_OPC_Decode, + 214, + 20, + 138, + 2, // Opcode: VFTCISB + /* 6212 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 6227 + /* 6217 */ MCD_OPC_CheckPredicate, + 34, + 53, + 0, + 0, // Skip to: 6275 + /* 6222 */ MCD_OPC_Decode, + 213, + 20, + 138, + 2, // Opcode: VFTCIDB + /* 6227 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 6243 + /* 6233 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 6275 + /* 6238 */ MCD_OPC_Decode, + 161, + 24, + 139, + 2, // Opcode: WFTCISB + /* 6243 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 6259 + /* 6249 */ MCD_OPC_CheckPredicate, + 34, + 21, + 0, + 0, // Skip to: 6275 + /* 6254 */ MCD_OPC_Decode, + 160, + 24, + 140, + 2, // Opcode: WFTCIDB + /* 6259 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 6275 + /* 6265 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 6275 + /* 6270 */ MCD_OPC_Decode, + 162, + 24, + 138, + 2, // Opcode: WFTCIXB + /* 6275 */ MCD_OPC_CheckPredicate, + 34, + 68, + 66, + 0, // Skip to: 23244 + /* 6280 */ MCD_OPC_Decode, + 212, + 20, + 141, + 2, // Opcode: VFTCI + /* 6285 */ MCD_OPC_FilterValue, + 77, + 81, + 0, + 0, // Skip to: 6371 + /* 6290 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 6293 */ MCD_OPC_FilterValue, + 0, + 50, + 66, + 0, // Skip to: 23244 + /* 6298 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6301 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6316 + /* 6306 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 6361 + /* 6311 */ MCD_OPC_Decode, + 186, + 22, + 142, + 2, // Opcode: VREPB + /* 6316 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6331 + /* 6321 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 6361 + /* 6326 */ MCD_OPC_Decode, + 189, + 22, + 142, + 2, // Opcode: VREPH + /* 6331 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6346 + /* 6336 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 6361 + /* 6341 */ MCD_OPC_Decode, + 187, + 22, + 142, + 2, // Opcode: VREPF + /* 6346 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 6361 + /* 6351 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 6361 + /* 6356 */ MCD_OPC_Decode, + 188, + 22, + 142, + 2, // Opcode: VREPG + /* 6361 */ MCD_OPC_CheckPredicate, + 34, + 238, + 65, + 0, // Skip to: 23244 + /* 6366 */ MCD_OPC_Decode, + 185, + 22, + 143, + 2, // Opcode: VREP + /* 6371 */ MCD_OPC_FilterValue, + 80, + 89, + 0, + 0, // Skip to: 6465 + /* 6376 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 6379 */ MCD_OPC_FilterValue, + 0, + 220, + 65, + 0, // Skip to: 23244 + /* 6384 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 6387 */ MCD_OPC_FilterValue, + 0, + 212, + 65, + 0, // Skip to: 23244 + /* 6392 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6395 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6410 + /* 6400 */ MCD_OPC_CheckPredicate, + 35, + 50, + 0, + 0, // Skip to: 6455 + /* 6405 */ MCD_OPC_Decode, + 180, + 22, + 144, + 2, // Opcode: VPOPCTB + /* 6410 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6425 + /* 6415 */ MCD_OPC_CheckPredicate, + 35, + 35, + 0, + 0, // Skip to: 6455 + /* 6420 */ MCD_OPC_Decode, + 183, + 22, + 144, + 2, // Opcode: VPOPCTH + /* 6425 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6440 + /* 6430 */ MCD_OPC_CheckPredicate, + 35, + 20, + 0, + 0, // Skip to: 6455 + /* 6435 */ MCD_OPC_Decode, + 181, + 22, + 144, + 2, // Opcode: VPOPCTF + /* 6440 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 6455 + /* 6445 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 6455 + /* 6450 */ MCD_OPC_Decode, + 182, + 22, + 144, + 2, // Opcode: VPOPCTG + /* 6455 */ MCD_OPC_CheckPredicate, + 34, + 144, + 65, + 0, // Skip to: 23244 + /* 6460 */ MCD_OPC_Decode, + 179, + 22, + 145, + 2, // Opcode: VPOPCT + /* 6465 */ MCD_OPC_FilterValue, + 82, + 89, + 0, + 0, // Skip to: 6559 + /* 6470 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 6473 */ MCD_OPC_FilterValue, + 0, + 126, + 65, + 0, // Skip to: 23244 + /* 6478 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 6481 */ MCD_OPC_FilterValue, + 0, + 118, + 65, + 0, // Skip to: 23244 + /* 6486 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6489 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6504 + /* 6494 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 6549 + /* 6499 */ MCD_OPC_Decode, + 159, + 19, + 144, + 2, // Opcode: VCTZB + /* 6504 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6519 + /* 6509 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 6549 + /* 6514 */ MCD_OPC_Decode, + 162, + 19, + 144, + 2, // Opcode: VCTZH + /* 6519 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6534 + /* 6524 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 6549 + /* 6529 */ MCD_OPC_Decode, + 160, + 19, + 144, + 2, // Opcode: VCTZF + /* 6534 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 6549 + /* 6539 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 6549 + /* 6544 */ MCD_OPC_Decode, + 161, + 19, + 144, + 2, // Opcode: VCTZG + /* 6549 */ MCD_OPC_CheckPredicate, + 34, + 50, + 65, + 0, // Skip to: 23244 + /* 6554 */ MCD_OPC_Decode, + 158, + 19, + 145, + 2, // Opcode: VCTZ + /* 6559 */ MCD_OPC_FilterValue, + 83, + 89, + 0, + 0, // Skip to: 6653 + /* 6564 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 6567 */ MCD_OPC_FilterValue, + 0, + 32, + 65, + 0, // Skip to: 23244 + /* 6572 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 6575 */ MCD_OPC_FilterValue, + 0, + 24, + 65, + 0, // Skip to: 23244 + /* 6580 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6583 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6598 + /* 6588 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 6643 + /* 6593 */ MCD_OPC_Decode, + 148, + 19, + 144, + 2, // Opcode: VCLZB + /* 6598 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6613 + /* 6603 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 6643 + /* 6608 */ MCD_OPC_Decode, + 152, + 19, + 144, + 2, // Opcode: VCLZH + /* 6613 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6628 + /* 6618 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 6643 + /* 6623 */ MCD_OPC_Decode, + 150, + 19, + 144, + 2, // Opcode: VCLZF + /* 6628 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 6643 + /* 6633 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 6643 + /* 6638 */ MCD_OPC_Decode, + 151, + 19, + 144, + 2, // Opcode: VCLZG + /* 6643 */ MCD_OPC_CheckPredicate, + 34, + 212, + 64, + 0, // Skip to: 23244 + /* 6648 */ MCD_OPC_Decode, + 147, + 19, + 145, + 2, // Opcode: VCLZ + /* 6653 */ MCD_OPC_FilterValue, + 86, + 24, + 0, + 0, // Skip to: 6682 + /* 6658 */ MCD_OPC_CheckPredicate, + 34, + 197, + 64, + 0, // Skip to: 23244 + /* 6663 */ MCD_OPC_CheckField, + 12, + 20, + 0, + 190, + 64, + 0, // Skip to: 23244 + /* 6670 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 183, + 64, + 0, // Skip to: 23244 + /* 6677 */ MCD_OPC_Decode, + 173, + 21, + 144, + 2, // Opcode: VLR + /* 6682 */ MCD_OPC_FilterValue, + 92, + 133, + 0, + 0, // Skip to: 6820 + /* 6687 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 6690 */ MCD_OPC_FilterValue, + 0, + 165, + 64, + 0, // Skip to: 23244 + /* 6695 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 6698 */ MCD_OPC_FilterValue, + 0, + 157, + 64, + 0, // Skip to: 23244 + /* 6703 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 6706 */ MCD_OPC_FilterValue, + 0, + 149, + 64, + 0, // Skip to: 23244 + /* 6711 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6714 */ MCD_OPC_FilterValue, + 0, + 27, + 0, + 0, // Skip to: 6746 + /* 6719 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 6736 + /* 6724 */ MCD_OPC_CheckField, + 20, + 4, + 1, + 5, + 0, + 0, // Skip to: 6736 + /* 6731 */ MCD_OPC_Decode, + 235, + 20, + 144, + 2, // Opcode: VISTRBS + /* 6736 */ MCD_OPC_CheckPredicate, + 34, + 69, + 0, + 0, // Skip to: 6810 + /* 6741 */ MCD_OPC_Decode, + 234, + 20, + 226, + 1, // Opcode: VISTRB + /* 6746 */ MCD_OPC_FilterValue, + 1, + 27, + 0, + 0, // Skip to: 6778 + /* 6751 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 6768 + /* 6756 */ MCD_OPC_CheckField, + 20, + 4, + 1, + 5, + 0, + 0, // Skip to: 6768 + /* 6763 */ MCD_OPC_Decode, + 239, + 20, + 144, + 2, // Opcode: VISTRHS + /* 6768 */ MCD_OPC_CheckPredicate, + 34, + 37, + 0, + 0, // Skip to: 6810 + /* 6773 */ MCD_OPC_Decode, + 238, + 20, + 226, + 1, // Opcode: VISTRH + /* 6778 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 6810 + /* 6783 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 6800 + /* 6788 */ MCD_OPC_CheckField, + 20, + 4, + 1, + 5, + 0, + 0, // Skip to: 6800 + /* 6795 */ MCD_OPC_Decode, + 237, + 20, + 144, + 2, // Opcode: VISTRFS + /* 6800 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 6810 + /* 6805 */ MCD_OPC_Decode, + 236, + 20, + 226, + 1, // Opcode: VISTRF + /* 6810 */ MCD_OPC_CheckPredicate, + 34, + 45, + 64, + 0, // Skip to: 23244 + /* 6815 */ MCD_OPC_Decode, + 233, + 20, + 146, + 2, // Opcode: VISTR + /* 6820 */ MCD_OPC_FilterValue, + 95, + 74, + 0, + 0, // Skip to: 6899 + /* 6825 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 6828 */ MCD_OPC_FilterValue, + 0, + 27, + 64, + 0, // Skip to: 23244 + /* 6833 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 6836 */ MCD_OPC_FilterValue, + 0, + 19, + 64, + 0, // Skip to: 23244 + /* 6841 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6844 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6859 + /* 6849 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 6889 + /* 6854 */ MCD_OPC_Decode, + 217, + 22, + 144, + 2, // Opcode: VSEGB + /* 6859 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6874 + /* 6864 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 6889 + /* 6869 */ MCD_OPC_Decode, + 219, + 22, + 144, + 2, // Opcode: VSEGH + /* 6874 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6889 + /* 6879 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 6889 + /* 6884 */ MCD_OPC_Decode, + 218, + 22, + 144, + 2, // Opcode: VSEGF + /* 6889 */ MCD_OPC_CheckPredicate, + 34, + 222, + 63, + 0, // Skip to: 23244 + /* 6894 */ MCD_OPC_Decode, + 216, + 22, + 145, + 2, // Opcode: VSEG + /* 6899 */ MCD_OPC_FilterValue, + 96, + 89, + 0, + 0, // Skip to: 6993 + /* 6904 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 6907 */ MCD_OPC_FilterValue, + 0, + 204, + 63, + 0, // Skip to: 23244 + /* 6912 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 6915 */ MCD_OPC_FilterValue, + 0, + 196, + 63, + 0, // Skip to: 23244 + /* 6920 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 6923 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 6938 + /* 6928 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 6983 + /* 6933 */ MCD_OPC_Decode, + 132, + 22, + 239, + 1, // Opcode: VMRLB + /* 6938 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 6953 + /* 6943 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 6983 + /* 6948 */ MCD_OPC_Decode, + 135, + 22, + 239, + 1, // Opcode: VMRLH + /* 6953 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 6968 + /* 6958 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 6983 + /* 6963 */ MCD_OPC_Decode, + 133, + 22, + 239, + 1, // Opcode: VMRLF + /* 6968 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 6983 + /* 6973 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 6983 + /* 6978 */ MCD_OPC_Decode, + 134, + 22, + 239, + 1, // Opcode: VMRLG + /* 6983 */ MCD_OPC_CheckPredicate, + 34, + 128, + 63, + 0, // Skip to: 23244 + /* 6988 */ MCD_OPC_Decode, + 131, + 22, + 147, + 2, // Opcode: VMRL + /* 6993 */ MCD_OPC_FilterValue, + 97, + 89, + 0, + 0, // Skip to: 7087 + /* 6998 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7001 */ MCD_OPC_FilterValue, + 0, + 110, + 63, + 0, // Skip to: 23244 + /* 7006 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 7009 */ MCD_OPC_FilterValue, + 0, + 102, + 63, + 0, // Skip to: 23244 + /* 7014 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7017 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7032 + /* 7022 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 7077 + /* 7027 */ MCD_OPC_Decode, + 255, + 21, + 239, + 1, // Opcode: VMRHB + /* 7032 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7047 + /* 7037 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 7077 + /* 7042 */ MCD_OPC_Decode, + 130, + 22, + 239, + 1, // Opcode: VMRHH + /* 7047 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7062 + /* 7052 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 7077 + /* 7057 */ MCD_OPC_Decode, + 128, + 22, + 239, + 1, // Opcode: VMRHF + /* 7062 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 7077 + /* 7067 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 7077 + /* 7072 */ MCD_OPC_Decode, + 129, + 22, + 239, + 1, // Opcode: VMRHG + /* 7077 */ MCD_OPC_CheckPredicate, + 34, + 34, + 63, + 0, // Skip to: 23244 + /* 7082 */ MCD_OPC_Decode, + 254, + 21, + 147, + 2, // Opcode: VMRH + /* 7087 */ MCD_OPC_FilterValue, + 98, + 24, + 0, + 0, // Skip to: 7116 + /* 7092 */ MCD_OPC_CheckPredicate, + 34, + 19, + 63, + 0, // Skip to: 23244 + /* 7097 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 12, + 63, + 0, // Skip to: 23244 + /* 7104 */ MCD_OPC_CheckField, + 8, + 3, + 0, + 5, + 63, + 0, // Skip to: 23244 + /* 7111 */ MCD_OPC_Decode, + 186, + 21, + 148, + 2, // Opcode: VLVGP + /* 7116 */ MCD_OPC_FilterValue, + 100, + 59, + 0, + 0, // Skip to: 7180 + /* 7121 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7124 */ MCD_OPC_FilterValue, + 0, + 243, + 62, + 0, // Skip to: 23244 + /* 7129 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 7132 */ MCD_OPC_FilterValue, + 0, + 235, + 62, + 0, // Skip to: 23244 + /* 7137 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7140 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7155 + /* 7145 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 7170 + /* 7150 */ MCD_OPC_Decode, + 153, + 23, + 239, + 1, // Opcode: VSUMB + /* 7155 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7170 + /* 7160 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 7170 + /* 7165 */ MCD_OPC_Decode, + 157, + 23, + 239, + 1, // Opcode: VSUMH + /* 7170 */ MCD_OPC_CheckPredicate, + 34, + 197, + 62, + 0, // Skip to: 23244 + /* 7175 */ MCD_OPC_Decode, + 152, + 23, + 147, + 2, // Opcode: VSUM + /* 7180 */ MCD_OPC_FilterValue, + 101, + 59, + 0, + 0, // Skip to: 7244 + /* 7185 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7188 */ MCD_OPC_FilterValue, + 0, + 179, + 62, + 0, // Skip to: 23244 + /* 7193 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 7196 */ MCD_OPC_FilterValue, + 0, + 171, + 62, + 0, // Skip to: 23244 + /* 7201 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7204 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7219 + /* 7209 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 7234 + /* 7214 */ MCD_OPC_Decode, + 156, + 23, + 239, + 1, // Opcode: VSUMGH + /* 7219 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7234 + /* 7224 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 7234 + /* 7229 */ MCD_OPC_Decode, + 155, + 23, + 239, + 1, // Opcode: VSUMGF + /* 7234 */ MCD_OPC_CheckPredicate, + 34, + 133, + 62, + 0, // Skip to: 23244 + /* 7239 */ MCD_OPC_Decode, + 154, + 23, + 147, + 2, // Opcode: VSUMG + /* 7244 */ MCD_OPC_FilterValue, + 102, + 24, + 0, + 0, // Skip to: 7273 + /* 7249 */ MCD_OPC_CheckPredicate, + 34, + 118, + 62, + 0, // Skip to: 23244 + /* 7254 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 111, + 62, + 0, // Skip to: 23244 + /* 7261 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 104, + 62, + 0, // Skip to: 23244 + /* 7268 */ MCD_OPC_Decode, + 140, + 19, + 239, + 1, // Opcode: VCKSM + /* 7273 */ MCD_OPC_FilterValue, + 103, + 59, + 0, + 0, // Skip to: 7337 + /* 7278 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7281 */ MCD_OPC_FilterValue, + 0, + 86, + 62, + 0, // Skip to: 23244 + /* 7286 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 7289 */ MCD_OPC_FilterValue, + 0, + 78, + 62, + 0, // Skip to: 23244 + /* 7294 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7297 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7312 + /* 7302 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 7327 + /* 7307 */ MCD_OPC_Decode, + 159, + 23, + 239, + 1, // Opcode: VSUMQF + /* 7312 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 7327 + /* 7317 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 7327 + /* 7322 */ MCD_OPC_Decode, + 160, + 23, + 239, + 1, // Opcode: VSUMQG + /* 7327 */ MCD_OPC_CheckPredicate, + 34, + 40, + 62, + 0, // Skip to: 23244 + /* 7332 */ MCD_OPC_Decode, + 158, + 23, + 147, + 2, // Opcode: VSUMQ + /* 7337 */ MCD_OPC_FilterValue, + 104, + 24, + 0, + 0, // Skip to: 7366 + /* 7342 */ MCD_OPC_CheckPredicate, + 34, + 25, + 62, + 0, // Skip to: 23244 + /* 7347 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 18, + 62, + 0, // Skip to: 23244 + /* 7354 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 11, + 62, + 0, // Skip to: 23244 + /* 7361 */ MCD_OPC_Decode, + 149, + 22, + 239, + 1, // Opcode: VN + /* 7366 */ MCD_OPC_FilterValue, + 105, + 24, + 0, + 0, // Skip to: 7395 + /* 7371 */ MCD_OPC_CheckPredicate, + 34, + 252, + 61, + 0, // Skip to: 23244 + /* 7376 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 245, + 61, + 0, // Skip to: 23244 + /* 7383 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 238, + 61, + 0, // Skip to: 23244 + /* 7390 */ MCD_OPC_Decode, + 150, + 22, + 239, + 1, // Opcode: VNC + /* 7395 */ MCD_OPC_FilterValue, + 106, + 24, + 0, + 0, // Skip to: 7424 + /* 7400 */ MCD_OPC_CheckPredicate, + 34, + 223, + 61, + 0, // Skip to: 23244 + /* 7405 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 216, + 61, + 0, // Skip to: 23244 + /* 7412 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 209, + 61, + 0, // Skip to: 23244 + /* 7419 */ MCD_OPC_Decode, + 154, + 22, + 239, + 1, // Opcode: VO + /* 7424 */ MCD_OPC_FilterValue, + 107, + 24, + 0, + 0, // Skip to: 7453 + /* 7429 */ MCD_OPC_CheckPredicate, + 34, + 194, + 61, + 0, // Skip to: 23244 + /* 7434 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 187, + 61, + 0, // Skip to: 23244 + /* 7441 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 180, + 61, + 0, // Skip to: 23244 + /* 7448 */ MCD_OPC_Decode, + 152, + 22, + 239, + 1, // Opcode: VNO + /* 7453 */ MCD_OPC_FilterValue, + 108, + 24, + 0, + 0, // Skip to: 7482 + /* 7458 */ MCD_OPC_CheckPredicate, + 35, + 165, + 61, + 0, // Skip to: 23244 + /* 7463 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 158, + 61, + 0, // Skip to: 23244 + /* 7470 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 151, + 61, + 0, // Skip to: 23244 + /* 7477 */ MCD_OPC_Decode, + 153, + 22, + 239, + 1, // Opcode: VNX + /* 7482 */ MCD_OPC_FilterValue, + 109, + 24, + 0, + 0, // Skip to: 7511 + /* 7487 */ MCD_OPC_CheckPredicate, + 34, + 136, + 61, + 0, // Skip to: 23244 + /* 7492 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 129, + 61, + 0, // Skip to: 23244 + /* 7499 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 122, + 61, + 0, // Skip to: 23244 + /* 7506 */ MCD_OPC_Decode, + 182, + 23, + 239, + 1, // Opcode: VX + /* 7511 */ MCD_OPC_FilterValue, + 110, + 24, + 0, + 0, // Skip to: 7540 + /* 7516 */ MCD_OPC_CheckPredicate, + 35, + 107, + 61, + 0, // Skip to: 23244 + /* 7521 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 100, + 61, + 0, // Skip to: 23244 + /* 7528 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 93, + 61, + 0, // Skip to: 23244 + /* 7535 */ MCD_OPC_Decode, + 151, + 22, + 239, + 1, // Opcode: VNN + /* 7540 */ MCD_OPC_FilterValue, + 111, + 24, + 0, + 0, // Skip to: 7569 + /* 7545 */ MCD_OPC_CheckPredicate, + 35, + 78, + 61, + 0, // Skip to: 23244 + /* 7550 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 71, + 61, + 0, // Skip to: 23244 + /* 7557 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 64, + 61, + 0, // Skip to: 23244 + /* 7564 */ MCD_OPC_Decode, + 155, + 22, + 239, + 1, // Opcode: VOC + /* 7569 */ MCD_OPC_FilterValue, + 112, + 89, + 0, + 0, // Skip to: 7663 + /* 7574 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7577 */ MCD_OPC_FilterValue, + 0, + 46, + 61, + 0, // Skip to: 23244 + /* 7582 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 7585 */ MCD_OPC_FilterValue, + 0, + 38, + 61, + 0, // Skip to: 23244 + /* 7590 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7593 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7608 + /* 7598 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 7653 + /* 7603 */ MCD_OPC_Decode, + 201, + 19, + 239, + 1, // Opcode: VESLVB + /* 7608 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7623 + /* 7613 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 7653 + /* 7618 */ MCD_OPC_Decode, + 204, + 19, + 239, + 1, // Opcode: VESLVH + /* 7623 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7638 + /* 7628 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 7653 + /* 7633 */ MCD_OPC_Decode, + 202, + 19, + 239, + 1, // Opcode: VESLVF + /* 7638 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 7653 + /* 7643 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 7653 + /* 7648 */ MCD_OPC_Decode, + 203, + 19, + 239, + 1, // Opcode: VESLVG + /* 7653 */ MCD_OPC_CheckPredicate, + 34, + 226, + 60, + 0, // Skip to: 23244 + /* 7658 */ MCD_OPC_Decode, + 200, + 19, + 147, + 2, // Opcode: VESLV + /* 7663 */ MCD_OPC_FilterValue, + 114, + 89, + 0, + 0, // Skip to: 7757 + /* 7668 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7671 */ MCD_OPC_FilterValue, + 0, + 208, + 60, + 0, // Skip to: 23244 + /* 7676 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 7679 */ MCD_OPC_FilterValue, + 0, + 200, + 60, + 0, // Skip to: 23244 + /* 7684 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7687 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7702 + /* 7692 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 7747 + /* 7697 */ MCD_OPC_Decode, + 181, + 19, + 149, + 2, // Opcode: VERIMB + /* 7702 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7717 + /* 7707 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 7747 + /* 7712 */ MCD_OPC_Decode, + 184, + 19, + 149, + 2, // Opcode: VERIMH + /* 7717 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7732 + /* 7722 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 7747 + /* 7727 */ MCD_OPC_Decode, + 182, + 19, + 149, + 2, // Opcode: VERIMF + /* 7732 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 7747 + /* 7737 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 7747 + /* 7742 */ MCD_OPC_Decode, + 183, + 19, + 149, + 2, // Opcode: VERIMG + /* 7747 */ MCD_OPC_CheckPredicate, + 34, + 132, + 60, + 0, // Skip to: 23244 + /* 7752 */ MCD_OPC_Decode, + 180, + 19, + 150, + 2, // Opcode: VERIM + /* 7757 */ MCD_OPC_FilterValue, + 115, + 89, + 0, + 0, // Skip to: 7851 + /* 7762 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7765 */ MCD_OPC_FilterValue, + 0, + 114, + 60, + 0, // Skip to: 23244 + /* 7770 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 7773 */ MCD_OPC_FilterValue, + 0, + 106, + 60, + 0, // Skip to: 23244 + /* 7778 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7781 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7796 + /* 7786 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 7841 + /* 7791 */ MCD_OPC_Decode, + 191, + 19, + 239, + 1, // Opcode: VERLLVB + /* 7796 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7811 + /* 7801 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 7841 + /* 7806 */ MCD_OPC_Decode, + 194, + 19, + 239, + 1, // Opcode: VERLLVH + /* 7811 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 7826 + /* 7816 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 7841 + /* 7821 */ MCD_OPC_Decode, + 192, + 19, + 239, + 1, // Opcode: VERLLVF + /* 7826 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 7841 + /* 7831 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 7841 + /* 7836 */ MCD_OPC_Decode, + 193, + 19, + 239, + 1, // Opcode: VERLLVG + /* 7841 */ MCD_OPC_CheckPredicate, + 34, + 38, + 60, + 0, // Skip to: 23244 + /* 7846 */ MCD_OPC_Decode, + 190, + 19, + 147, + 2, // Opcode: VERLLV + /* 7851 */ MCD_OPC_FilterValue, + 116, + 24, + 0, + 0, // Skip to: 7880 + /* 7856 */ MCD_OPC_CheckPredicate, + 34, + 23, + 60, + 0, // Skip to: 23244 + /* 7861 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 16, + 60, + 0, // Skip to: 23244 + /* 7868 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 9, + 60, + 0, // Skip to: 23244 + /* 7875 */ MCD_OPC_Decode, + 224, + 22, + 239, + 1, // Opcode: VSL + /* 7880 */ MCD_OPC_FilterValue, + 117, + 24, + 0, + 0, // Skip to: 7909 + /* 7885 */ MCD_OPC_CheckPredicate, + 34, + 250, + 59, + 0, // Skip to: 23244 + /* 7890 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 243, + 59, + 0, // Skip to: 23244 + /* 7897 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 236, + 59, + 0, // Skip to: 23244 + /* 7904 */ MCD_OPC_Decode, + 225, + 22, + 239, + 1, // Opcode: VSLB + /* 7909 */ MCD_OPC_FilterValue, + 119, + 31, + 0, + 0, // Skip to: 7945 + /* 7914 */ MCD_OPC_CheckPredicate, + 34, + 221, + 59, + 0, // Skip to: 23244 + /* 7919 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 214, + 59, + 0, // Skip to: 23244 + /* 7926 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 207, + 59, + 0, // Skip to: 23244 + /* 7933 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 200, + 59, + 0, // Skip to: 23244 + /* 7940 */ MCD_OPC_Decode, + 227, + 22, + 151, + 2, // Opcode: VSLDB + /* 7945 */ MCD_OPC_FilterValue, + 120, + 89, + 0, + 0, // Skip to: 8039 + /* 7950 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 7953 */ MCD_OPC_FilterValue, + 0, + 182, + 59, + 0, // Skip to: 23244 + /* 7958 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 7961 */ MCD_OPC_FilterValue, + 0, + 174, + 59, + 0, // Skip to: 23244 + /* 7966 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 7969 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 7984 + /* 7974 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 8029 + /* 7979 */ MCD_OPC_Decode, + 221, + 19, + 239, + 1, // Opcode: VESRLVB + /* 7984 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 7999 + /* 7989 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 8029 + /* 7994 */ MCD_OPC_Decode, + 224, + 19, + 239, + 1, // Opcode: VESRLVH + /* 7999 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8014 + /* 8004 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 8029 + /* 8009 */ MCD_OPC_Decode, + 222, + 19, + 239, + 1, // Opcode: VESRLVF + /* 8014 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8029 + /* 8019 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8029 + /* 8024 */ MCD_OPC_Decode, + 223, + 19, + 239, + 1, // Opcode: VESRLVG + /* 8029 */ MCD_OPC_CheckPredicate, + 34, + 106, + 59, + 0, // Skip to: 23244 + /* 8034 */ MCD_OPC_Decode, + 220, + 19, + 147, + 2, // Opcode: VESRLV + /* 8039 */ MCD_OPC_FilterValue, + 122, + 89, + 0, + 0, // Skip to: 8133 + /* 8044 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 8047 */ MCD_OPC_FilterValue, + 0, + 88, + 59, + 0, // Skip to: 23244 + /* 8052 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 8055 */ MCD_OPC_FilterValue, + 0, + 80, + 59, + 0, // Skip to: 23244 + /* 8060 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 8063 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 8078 + /* 8068 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 8123 + /* 8073 */ MCD_OPC_Decode, + 211, + 19, + 239, + 1, // Opcode: VESRAVB + /* 8078 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8093 + /* 8083 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 8123 + /* 8088 */ MCD_OPC_Decode, + 214, + 19, + 239, + 1, // Opcode: VESRAVH + /* 8093 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8108 + /* 8098 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 8123 + /* 8103 */ MCD_OPC_Decode, + 212, + 19, + 239, + 1, // Opcode: VESRAVF + /* 8108 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8123 + /* 8113 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8123 + /* 8118 */ MCD_OPC_Decode, + 213, + 19, + 239, + 1, // Opcode: VESRAVG + /* 8123 */ MCD_OPC_CheckPredicate, + 34, + 12, + 59, + 0, // Skip to: 23244 + /* 8128 */ MCD_OPC_Decode, + 210, + 19, + 147, + 2, // Opcode: VESRAV + /* 8133 */ MCD_OPC_FilterValue, + 124, + 24, + 0, + 0, // Skip to: 8162 + /* 8138 */ MCD_OPC_CheckPredicate, + 34, + 253, + 58, + 0, // Skip to: 23244 + /* 8143 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 246, + 58, + 0, // Skip to: 23244 + /* 8150 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 239, + 58, + 0, // Skip to: 23244 + /* 8157 */ MCD_OPC_Decode, + 233, + 22, + 239, + 1, // Opcode: VSRL + /* 8162 */ MCD_OPC_FilterValue, + 125, + 24, + 0, + 0, // Skip to: 8191 + /* 8167 */ MCD_OPC_CheckPredicate, + 34, + 224, + 58, + 0, // Skip to: 23244 + /* 8172 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 217, + 58, + 0, // Skip to: 23244 + /* 8179 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 210, + 58, + 0, // Skip to: 23244 + /* 8186 */ MCD_OPC_Decode, + 234, + 22, + 239, + 1, // Opcode: VSRLB + /* 8191 */ MCD_OPC_FilterValue, + 126, + 24, + 0, + 0, // Skip to: 8220 + /* 8196 */ MCD_OPC_CheckPredicate, + 34, + 195, + 58, + 0, // Skip to: 23244 + /* 8201 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 188, + 58, + 0, // Skip to: 23244 + /* 8208 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 181, + 58, + 0, // Skip to: 23244 + /* 8215 */ MCD_OPC_Decode, + 230, + 22, + 239, + 1, // Opcode: VSRA + /* 8220 */ MCD_OPC_FilterValue, + 127, + 24, + 0, + 0, // Skip to: 8249 + /* 8225 */ MCD_OPC_CheckPredicate, + 34, + 166, + 58, + 0, // Skip to: 23244 + /* 8230 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 159, + 58, + 0, // Skip to: 23244 + /* 8237 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 152, + 58, + 0, // Skip to: 23244 + /* 8244 */ MCD_OPC_Decode, + 231, + 22, + 239, + 1, // Opcode: VSRAB + /* 8249 */ MCD_OPC_FilterValue, + 128, + 1, + 226, + 0, + 0, // Skip to: 8481 + /* 8255 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 8258 */ MCD_OPC_FilterValue, + 0, + 133, + 58, + 0, // Skip to: 23244 + /* 8263 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 8266 */ MCD_OPC_FilterValue, + 0, + 125, + 58, + 0, // Skip to: 23244 + /* 8271 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 8274 */ MCD_OPC_FilterValue, + 0, + 117, + 58, + 0, // Skip to: 23244 + /* 8279 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 8282 */ MCD_OPC_FilterValue, + 0, + 58, + 0, + 0, // Skip to: 8345 + /* 8287 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 8290 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8305 + /* 8295 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 8335 + /* 8300 */ MCD_OPC_Decode, + 133, + 20, + 239, + 1, // Opcode: VFEEBS + /* 8305 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8320 + /* 8310 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 8335 + /* 8315 */ MCD_OPC_Decode, + 138, + 20, + 239, + 1, // Opcode: VFEEZB + /* 8320 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8335 + /* 8325 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8335 + /* 8330 */ MCD_OPC_Decode, + 139, + 20, + 239, + 1, // Opcode: VFEEZBS + /* 8335 */ MCD_OPC_CheckPredicate, + 34, + 131, + 0, + 0, // Skip to: 8471 + /* 8340 */ MCD_OPC_Decode, + 132, + 20, + 235, + 1, // Opcode: VFEEB + /* 8345 */ MCD_OPC_FilterValue, + 1, + 58, + 0, + 0, // Skip to: 8408 + /* 8350 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 8353 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8368 + /* 8358 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 8398 + /* 8363 */ MCD_OPC_Decode, + 137, + 20, + 239, + 1, // Opcode: VFEEHS + /* 8368 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8383 + /* 8373 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 8398 + /* 8378 */ MCD_OPC_Decode, + 142, + 20, + 239, + 1, // Opcode: VFEEZH + /* 8383 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8398 + /* 8388 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8398 + /* 8393 */ MCD_OPC_Decode, + 143, + 20, + 239, + 1, // Opcode: VFEEZHS + /* 8398 */ MCD_OPC_CheckPredicate, + 34, + 68, + 0, + 0, // Skip to: 8471 + /* 8403 */ MCD_OPC_Decode, + 136, + 20, + 235, + 1, // Opcode: VFEEH + /* 8408 */ MCD_OPC_FilterValue, + 2, + 58, + 0, + 0, // Skip to: 8471 + /* 8413 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 8416 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8431 + /* 8421 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 8461 + /* 8426 */ MCD_OPC_Decode, + 135, + 20, + 239, + 1, // Opcode: VFEEFS + /* 8431 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8446 + /* 8436 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 8461 + /* 8441 */ MCD_OPC_Decode, + 140, + 20, + 239, + 1, // Opcode: VFEEZF + /* 8446 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8461 + /* 8451 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8461 + /* 8456 */ MCD_OPC_Decode, + 141, + 20, + 239, + 1, // Opcode: VFEEZFS + /* 8461 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8471 + /* 8466 */ MCD_OPC_Decode, + 134, + 20, + 235, + 1, // Opcode: VFEEF + /* 8471 */ MCD_OPC_CheckPredicate, + 34, + 176, + 57, + 0, // Skip to: 23244 + /* 8476 */ MCD_OPC_Decode, + 131, + 20, + 236, + 1, // Opcode: VFEE + /* 8481 */ MCD_OPC_FilterValue, + 129, + 1, + 226, + 0, + 0, // Skip to: 8713 + /* 8487 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 8490 */ MCD_OPC_FilterValue, + 0, + 157, + 57, + 0, // Skip to: 23244 + /* 8495 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 8498 */ MCD_OPC_FilterValue, + 0, + 149, + 57, + 0, // Skip to: 23244 + /* 8503 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 8506 */ MCD_OPC_FilterValue, + 0, + 141, + 57, + 0, // Skip to: 23244 + /* 8511 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 8514 */ MCD_OPC_FilterValue, + 0, + 58, + 0, + 0, // Skip to: 8577 + /* 8519 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 8522 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8537 + /* 8527 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 8567 + /* 8532 */ MCD_OPC_Decode, + 146, + 20, + 239, + 1, // Opcode: VFENEBS + /* 8537 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8552 + /* 8542 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 8567 + /* 8547 */ MCD_OPC_Decode, + 151, + 20, + 239, + 1, // Opcode: VFENEZB + /* 8552 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8567 + /* 8557 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8567 + /* 8562 */ MCD_OPC_Decode, + 152, + 20, + 239, + 1, // Opcode: VFENEZBS + /* 8567 */ MCD_OPC_CheckPredicate, + 34, + 131, + 0, + 0, // Skip to: 8703 + /* 8572 */ MCD_OPC_Decode, + 145, + 20, + 235, + 1, // Opcode: VFENEB + /* 8577 */ MCD_OPC_FilterValue, + 1, + 58, + 0, + 0, // Skip to: 8640 + /* 8582 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 8585 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8600 + /* 8590 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 8630 + /* 8595 */ MCD_OPC_Decode, + 150, + 20, + 239, + 1, // Opcode: VFENEHS + /* 8600 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8615 + /* 8605 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 8630 + /* 8610 */ MCD_OPC_Decode, + 155, + 20, + 239, + 1, // Opcode: VFENEZH + /* 8615 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8630 + /* 8620 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8630 + /* 8625 */ MCD_OPC_Decode, + 156, + 20, + 239, + 1, // Opcode: VFENEZHS + /* 8630 */ MCD_OPC_CheckPredicate, + 34, + 68, + 0, + 0, // Skip to: 8703 + /* 8635 */ MCD_OPC_Decode, + 149, + 20, + 235, + 1, // Opcode: VFENEH + /* 8640 */ MCD_OPC_FilterValue, + 2, + 58, + 0, + 0, // Skip to: 8703 + /* 8645 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 8648 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 8663 + /* 8653 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 8693 + /* 8658 */ MCD_OPC_Decode, + 148, + 20, + 239, + 1, // Opcode: VFENEFS + /* 8663 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 8678 + /* 8668 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 8693 + /* 8673 */ MCD_OPC_Decode, + 153, + 20, + 239, + 1, // Opcode: VFENEZF + /* 8678 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 8693 + /* 8683 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8693 + /* 8688 */ MCD_OPC_Decode, + 154, + 20, + 239, + 1, // Opcode: VFENEZFS + /* 8693 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8703 + /* 8698 */ MCD_OPC_Decode, + 147, + 20, + 235, + 1, // Opcode: VFENEF + /* 8703 */ MCD_OPC_CheckPredicate, + 34, + 200, + 56, + 0, // Skip to: 23244 + /* 8708 */ MCD_OPC_Decode, + 144, + 20, + 236, + 1, // Opcode: VFENE + /* 8713 */ MCD_OPC_FilterValue, + 130, + 1, + 235, + 0, + 0, // Skip to: 8954 + /* 8719 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 8722 */ MCD_OPC_FilterValue, + 0, + 181, + 56, + 0, // Skip to: 23244 + /* 8727 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 8730 */ MCD_OPC_FilterValue, + 0, + 173, + 56, + 0, // Skip to: 23244 + /* 8735 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 8738 */ MCD_OPC_FilterValue, + 0, + 165, + 56, + 0, // Skip to: 23244 + /* 8743 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 8746 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 8812 + /* 8751 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 8768 + /* 8756 */ MCD_OPC_CheckField, + 20, + 2, + 3, + 5, + 0, + 0, // Skip to: 8768 + /* 8763 */ MCD_OPC_Decode, + 235, + 19, + 152, + 2, // Opcode: VFAEZBS + /* 8768 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 8785 + /* 8773 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 8785 + /* 8780 */ MCD_OPC_Decode, + 229, + 19, + 153, + 2, // Opcode: VFAEBS + /* 8785 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 8802 + /* 8790 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 5, + 0, + 0, // Skip to: 8802 + /* 8797 */ MCD_OPC_Decode, + 234, + 19, + 154, + 2, // Opcode: VFAEZB + /* 8802 */ MCD_OPC_CheckPredicate, + 34, + 137, + 0, + 0, // Skip to: 8944 + /* 8807 */ MCD_OPC_Decode, + 228, + 19, + 235, + 1, // Opcode: VFAEB + /* 8812 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 8878 + /* 8817 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 8834 + /* 8822 */ MCD_OPC_CheckField, + 20, + 2, + 3, + 5, + 0, + 0, // Skip to: 8834 + /* 8829 */ MCD_OPC_Decode, + 239, + 19, + 152, + 2, // Opcode: VFAEZHS + /* 8834 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 8851 + /* 8839 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 8851 + /* 8846 */ MCD_OPC_Decode, + 233, + 19, + 153, + 2, // Opcode: VFAEHS + /* 8851 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 8868 + /* 8856 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 5, + 0, + 0, // Skip to: 8868 + /* 8863 */ MCD_OPC_Decode, + 238, + 19, + 154, + 2, // Opcode: VFAEZH + /* 8868 */ MCD_OPC_CheckPredicate, + 34, + 71, + 0, + 0, // Skip to: 8944 + /* 8873 */ MCD_OPC_Decode, + 232, + 19, + 235, + 1, // Opcode: VFAEH + /* 8878 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 8944 + /* 8883 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 8900 + /* 8888 */ MCD_OPC_CheckField, + 20, + 2, + 3, + 5, + 0, + 0, // Skip to: 8900 + /* 8895 */ MCD_OPC_Decode, + 237, + 19, + 152, + 2, // Opcode: VFAEZFS + /* 8900 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 8917 + /* 8905 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 8917 + /* 8912 */ MCD_OPC_Decode, + 231, + 19, + 153, + 2, // Opcode: VFAEFS + /* 8917 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 8934 + /* 8922 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 5, + 0, + 0, // Skip to: 8934 + /* 8929 */ MCD_OPC_Decode, + 236, + 19, + 154, + 2, // Opcode: VFAEZF + /* 8934 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 8944 + /* 8939 */ MCD_OPC_Decode, + 230, + 19, + 235, + 1, // Opcode: VFAEF + /* 8944 */ MCD_OPC_CheckPredicate, + 34, + 215, + 55, + 0, // Skip to: 23244 + /* 8949 */ MCD_OPC_Decode, + 227, + 19, + 236, + 1, // Opcode: VFAE + /* 8954 */ MCD_OPC_FilterValue, + 132, + 1, + 24, + 0, + 0, // Skip to: 8984 + /* 8960 */ MCD_OPC_CheckPredicate, + 34, + 199, + 55, + 0, // Skip to: 23244 + /* 8965 */ MCD_OPC_CheckField, + 16, + 12, + 0, + 192, + 55, + 0, // Skip to: 23244 + /* 8972 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 185, + 55, + 0, // Skip to: 23244 + /* 8979 */ MCD_OPC_Decode, + 157, + 22, + 147, + 2, // Opcode: VPDI + /* 8984 */ MCD_OPC_FilterValue, + 133, + 1, + 24, + 0, + 0, // Skip to: 9014 + /* 8990 */ MCD_OPC_CheckPredicate, + 35, + 169, + 55, + 0, // Skip to: 23244 + /* 8995 */ MCD_OPC_CheckField, + 12, + 16, + 0, + 162, + 55, + 0, // Skip to: 23244 + /* 9002 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 155, + 55, + 0, // Skip to: 23244 + /* 9009 */ MCD_OPC_Decode, + 228, + 18, + 239, + 1, // Opcode: VBPERM + /* 9014 */ MCD_OPC_FilterValue, + 134, + 1, + 31, + 0, + 0, // Skip to: 9051 + /* 9020 */ MCD_OPC_CheckPredicate, + 29, + 139, + 55, + 0, // Skip to: 23244 + /* 9025 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 132, + 55, + 0, // Skip to: 23244 + /* 9032 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 125, + 55, + 0, // Skip to: 23244 + /* 9039 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 118, + 55, + 0, // Skip to: 23244 + /* 9046 */ MCD_OPC_Decode, + 226, + 22, + 151, + 2, // Opcode: VSLD + /* 9051 */ MCD_OPC_FilterValue, + 135, + 1, + 31, + 0, + 0, // Skip to: 9088 + /* 9057 */ MCD_OPC_CheckPredicate, + 29, + 102, + 55, + 0, // Skip to: 23244 + /* 9062 */ MCD_OPC_CheckField, + 24, + 4, + 0, + 95, + 55, + 0, // Skip to: 23244 + /* 9069 */ MCD_OPC_CheckField, + 12, + 4, + 0, + 88, + 55, + 0, // Skip to: 23244 + /* 9076 */ MCD_OPC_CheckField, + 8, + 1, + 0, + 81, + 55, + 0, // Skip to: 23244 + /* 9083 */ MCD_OPC_Decode, + 232, + 22, + 151, + 2, // Opcode: VSRD + /* 9088 */ MCD_OPC_FilterValue, + 138, + 1, + 219, + 0, + 0, // Skip to: 9313 + /* 9094 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9097 */ MCD_OPC_FilterValue, + 0, + 62, + 55, + 0, // Skip to: 23244 + /* 9102 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 9105 */ MCD_OPC_FilterValue, + 0, + 61, + 0, + 0, // Skip to: 9171 + /* 9110 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 9127 + /* 9115 */ MCD_OPC_CheckField, + 20, + 2, + 3, + 5, + 0, + 0, // Skip to: 9127 + /* 9122 */ MCD_OPC_Decode, + 138, + 23, + 155, + 2, // Opcode: VSTRCZBS + /* 9127 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 9144 + /* 9132 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 9144 + /* 9139 */ MCD_OPC_Decode, + 132, + 23, + 156, + 2, // Opcode: VSTRCBS + /* 9144 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 9161 + /* 9149 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 5, + 0, + 0, // Skip to: 9161 + /* 9156 */ MCD_OPC_Decode, + 137, + 23, + 157, + 2, // Opcode: VSTRCZB + /* 9161 */ MCD_OPC_CheckPredicate, + 34, + 137, + 0, + 0, // Skip to: 9303 + /* 9166 */ MCD_OPC_Decode, + 131, + 23, + 158, + 2, // Opcode: VSTRCB + /* 9171 */ MCD_OPC_FilterValue, + 1, + 61, + 0, + 0, // Skip to: 9237 + /* 9176 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 9193 + /* 9181 */ MCD_OPC_CheckField, + 20, + 2, + 3, + 5, + 0, + 0, // Skip to: 9193 + /* 9188 */ MCD_OPC_Decode, + 142, + 23, + 155, + 2, // Opcode: VSTRCZHS + /* 9193 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 9210 + /* 9198 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 9210 + /* 9205 */ MCD_OPC_Decode, + 136, + 23, + 156, + 2, // Opcode: VSTRCHS + /* 9210 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 9227 + /* 9215 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 5, + 0, + 0, // Skip to: 9227 + /* 9222 */ MCD_OPC_Decode, + 141, + 23, + 157, + 2, // Opcode: VSTRCZH + /* 9227 */ MCD_OPC_CheckPredicate, + 34, + 71, + 0, + 0, // Skip to: 9303 + /* 9232 */ MCD_OPC_Decode, + 135, + 23, + 158, + 2, // Opcode: VSTRCH + /* 9237 */ MCD_OPC_FilterValue, + 2, + 61, + 0, + 0, // Skip to: 9303 + /* 9242 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 9259 + /* 9247 */ MCD_OPC_CheckField, + 20, + 2, + 3, + 5, + 0, + 0, // Skip to: 9259 + /* 9254 */ MCD_OPC_Decode, + 140, + 23, + 155, + 2, // Opcode: VSTRCZFS + /* 9259 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 9276 + /* 9264 */ MCD_OPC_CheckField, + 20, + 1, + 1, + 5, + 0, + 0, // Skip to: 9276 + /* 9271 */ MCD_OPC_Decode, + 134, + 23, + 156, + 2, // Opcode: VSTRCFS + /* 9276 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 9293 + /* 9281 */ MCD_OPC_CheckField, + 21, + 1, + 1, + 5, + 0, + 0, // Skip to: 9293 + /* 9288 */ MCD_OPC_Decode, + 139, + 23, + 157, + 2, // Opcode: VSTRCZF + /* 9293 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 9303 + /* 9298 */ MCD_OPC_Decode, + 133, + 23, + 158, + 2, // Opcode: VSTRCF + /* 9303 */ MCD_OPC_CheckPredicate, + 34, + 112, + 54, + 0, // Skip to: 23244 + /* 9308 */ MCD_OPC_Decode, + 130, + 23, + 159, + 2, // Opcode: VSTRC + /* 9313 */ MCD_OPC_FilterValue, + 139, + 1, + 114, + 0, + 0, // Skip to: 9433 + /* 9319 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9322 */ MCD_OPC_FilterValue, + 0, + 93, + 54, + 0, // Skip to: 23244 + /* 9327 */ MCD_OPC_ExtractField, + 20, + 8, // Inst{27-20} ... + /* 9330 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9345 + /* 9335 */ MCD_OPC_CheckPredicate, + 29, + 35, + 0, + 0, // Skip to: 9375 + /* 9340 */ MCD_OPC_Decode, + 149, + 23, + 160, + 2, // Opcode: VSTRSZB + /* 9345 */ MCD_OPC_FilterValue, + 18, + 10, + 0, + 0, // Skip to: 9360 + /* 9350 */ MCD_OPC_CheckPredicate, + 29, + 20, + 0, + 0, // Skip to: 9375 + /* 9355 */ MCD_OPC_Decode, + 151, + 23, + 160, + 2, // Opcode: VSTRSZH + /* 9360 */ MCD_OPC_FilterValue, + 34, + 10, + 0, + 0, // Skip to: 9375 + /* 9365 */ MCD_OPC_CheckPredicate, + 29, + 5, + 0, + 0, // Skip to: 9375 + /* 9370 */ MCD_OPC_Decode, + 150, + 23, + 160, + 2, // Opcode: VSTRSZF + /* 9375 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 9378 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9393 + /* 9383 */ MCD_OPC_CheckPredicate, + 29, + 35, + 0, + 0, // Skip to: 9423 + /* 9388 */ MCD_OPC_Decode, + 146, + 23, + 158, + 2, // Opcode: VSTRSB + /* 9393 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9408 + /* 9398 */ MCD_OPC_CheckPredicate, + 29, + 20, + 0, + 0, // Skip to: 9423 + /* 9403 */ MCD_OPC_Decode, + 148, + 23, + 158, + 2, // Opcode: VSTRSH + /* 9408 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9423 + /* 9413 */ MCD_OPC_CheckPredicate, + 29, + 5, + 0, + 0, // Skip to: 9423 + /* 9418 */ MCD_OPC_Decode, + 147, + 23, + 158, + 2, // Opcode: VSTRSF + /* 9423 */ MCD_OPC_CheckPredicate, + 29, + 248, + 53, + 0, // Skip to: 23244 + /* 9428 */ MCD_OPC_Decode, + 145, + 23, + 159, + 2, // Opcode: VSTRS + /* 9433 */ MCD_OPC_FilterValue, + 140, + 1, + 17, + 0, + 0, // Skip to: 9456 + /* 9439 */ MCD_OPC_CheckPredicate, + 34, + 232, + 53, + 0, // Skip to: 23244 + /* 9444 */ MCD_OPC_CheckField, + 16, + 12, + 0, + 225, + 53, + 0, // Skip to: 23244 + /* 9451 */ MCD_OPC_Decode, + 158, + 22, + 160, + 2, // Opcode: VPERM + /* 9456 */ MCD_OPC_FilterValue, + 141, + 1, + 17, + 0, + 0, // Skip to: 9479 + /* 9462 */ MCD_OPC_CheckPredicate, + 34, + 209, + 53, + 0, // Skip to: 23244 + /* 9467 */ MCD_OPC_CheckField, + 16, + 12, + 0, + 202, + 53, + 0, // Skip to: 23244 + /* 9474 */ MCD_OPC_Decode, + 220, + 22, + 160, + 2, // Opcode: VSEL + /* 9479 */ MCD_OPC_FilterValue, + 142, + 1, + 119, + 0, + 0, // Skip to: 9604 + /* 9485 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 9488 */ MCD_OPC_FilterValue, + 0, + 183, + 53, + 0, // Skip to: 23244 + /* 9493 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 9496 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 9534 + /* 9501 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9504 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9519 + /* 9509 */ MCD_OPC_CheckPredicate, + 35, + 80, + 0, + 0, // Skip to: 9594 + /* 9514 */ MCD_OPC_Decode, + 196, + 20, + 160, + 2, // Opcode: VFMSSB + /* 9519 */ MCD_OPC_FilterValue, + 8, + 70, + 0, + 0, // Skip to: 9594 + /* 9524 */ MCD_OPC_CheckPredicate, + 35, + 65, + 0, + 0, // Skip to: 9594 + /* 9529 */ MCD_OPC_Decode, + 142, + 24, + 161, + 2, // Opcode: WFMSSB + /* 9534 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 9572 + /* 9539 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9542 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9557 + /* 9547 */ MCD_OPC_CheckPredicate, + 34, + 42, + 0, + 0, // Skip to: 9594 + /* 9552 */ MCD_OPC_Decode, + 195, + 20, + 160, + 2, // Opcode: VFMSDB + /* 9557 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 9594 + /* 9562 */ MCD_OPC_CheckPredicate, + 34, + 27, + 0, + 0, // Skip to: 9594 + /* 9567 */ MCD_OPC_Decode, + 141, + 24, + 162, + 2, // Opcode: WFMSDB + /* 9572 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 9594 + /* 9577 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 9594 + /* 9582 */ MCD_OPC_CheckField, + 16, + 4, + 8, + 5, + 0, + 0, // Skip to: 9594 + /* 9589 */ MCD_OPC_Decode, + 143, + 24, + 160, + 2, // Opcode: WFMSXB + /* 9594 */ MCD_OPC_CheckPredicate, + 34, + 77, + 53, + 0, // Skip to: 23244 + /* 9599 */ MCD_OPC_Decode, + 193, + 20, + 163, + 2, // Opcode: VFMS + /* 9604 */ MCD_OPC_FilterValue, + 143, + 1, + 119, + 0, + 0, // Skip to: 9729 + /* 9610 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 9613 */ MCD_OPC_FilterValue, + 0, + 58, + 53, + 0, // Skip to: 23244 + /* 9618 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 9621 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 9659 + /* 9626 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9629 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9644 + /* 9634 */ MCD_OPC_CheckPredicate, + 35, + 80, + 0, + 0, // Skip to: 9719 + /* 9639 */ MCD_OPC_Decode, + 185, + 20, + 160, + 2, // Opcode: VFMASB + /* 9644 */ MCD_OPC_FilterValue, + 8, + 70, + 0, + 0, // Skip to: 9719 + /* 9649 */ MCD_OPC_CheckPredicate, + 35, + 65, + 0, + 0, // Skip to: 9719 + /* 9654 */ MCD_OPC_Decode, + 131, + 24, + 161, + 2, // Opcode: WFMASB + /* 9659 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 9697 + /* 9664 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9667 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9682 + /* 9672 */ MCD_OPC_CheckPredicate, + 34, + 42, + 0, + 0, // Skip to: 9719 + /* 9677 */ MCD_OPC_Decode, + 184, + 20, + 160, + 2, // Opcode: VFMADB + /* 9682 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 9719 + /* 9687 */ MCD_OPC_CheckPredicate, + 34, + 27, + 0, + 0, // Skip to: 9719 + /* 9692 */ MCD_OPC_Decode, + 130, + 24, + 162, + 2, // Opcode: WFMADB + /* 9697 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 9719 + /* 9702 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 9719 + /* 9707 */ MCD_OPC_CheckField, + 16, + 4, + 8, + 5, + 0, + 0, // Skip to: 9719 + /* 9714 */ MCD_OPC_Decode, + 132, + 24, + 160, + 2, // Opcode: WFMAXB + /* 9719 */ MCD_OPC_CheckPredicate, + 34, + 208, + 52, + 0, // Skip to: 23244 + /* 9724 */ MCD_OPC_Decode, + 183, + 20, + 163, + 2, // Opcode: VFMA + /* 9729 */ MCD_OPC_FilterValue, + 148, + 1, + 74, + 0, + 0, // Skip to: 9809 + /* 9735 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 9738 */ MCD_OPC_FilterValue, + 0, + 189, + 52, + 0, // Skip to: 23244 + /* 9743 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 9746 */ MCD_OPC_FilterValue, + 0, + 181, + 52, + 0, // Skip to: 23244 + /* 9751 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 9754 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9769 + /* 9759 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 9799 + /* 9764 */ MCD_OPC_Decode, + 162, + 22, + 239, + 1, // Opcode: VPKH + /* 9769 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 9784 + /* 9774 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 9799 + /* 9779 */ MCD_OPC_Decode, + 160, + 22, + 239, + 1, // Opcode: VPKF + /* 9784 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 9799 + /* 9789 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 9799 + /* 9794 */ MCD_OPC_Decode, + 161, + 22, + 239, + 1, // Opcode: VPKG + /* 9799 */ MCD_OPC_CheckPredicate, + 34, + 128, + 52, + 0, // Skip to: 23244 + /* 9804 */ MCD_OPC_Decode, + 159, + 22, + 147, + 2, // Opcode: VPK + /* 9809 */ MCD_OPC_FilterValue, + 149, + 1, + 151, + 0, + 0, // Skip to: 9966 + /* 9815 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 9818 */ MCD_OPC_FilterValue, + 0, + 109, + 52, + 0, // Skip to: 23244 + /* 9823 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9826 */ MCD_OPC_FilterValue, + 0, + 101, + 52, + 0, // Skip to: 23244 + /* 9831 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 9834 */ MCD_OPC_FilterValue, + 0, + 93, + 52, + 0, // Skip to: 23244 + /* 9839 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 9842 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 9880 + /* 9847 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 9850 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9865 + /* 9855 */ MCD_OPC_CheckPredicate, + 34, + 96, + 0, + 0, // Skip to: 9956 + /* 9860 */ MCD_OPC_Decode, + 168, + 22, + 239, + 1, // Opcode: VPKLSH + /* 9865 */ MCD_OPC_FilterValue, + 1, + 86, + 0, + 0, // Skip to: 9956 + /* 9870 */ MCD_OPC_CheckPredicate, + 34, + 81, + 0, + 0, // Skip to: 9956 + /* 9875 */ MCD_OPC_Decode, + 169, + 22, + 239, + 1, // Opcode: VPKLSHS + /* 9880 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 9918 + /* 9885 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 9888 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9903 + /* 9893 */ MCD_OPC_CheckPredicate, + 34, + 58, + 0, + 0, // Skip to: 9956 + /* 9898 */ MCD_OPC_Decode, + 164, + 22, + 239, + 1, // Opcode: VPKLSF + /* 9903 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 9956 + /* 9908 */ MCD_OPC_CheckPredicate, + 34, + 43, + 0, + 0, // Skip to: 9956 + /* 9913 */ MCD_OPC_Decode, + 165, + 22, + 239, + 1, // Opcode: VPKLSFS + /* 9918 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 9956 + /* 9923 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 9926 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 9941 + /* 9931 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 9956 + /* 9936 */ MCD_OPC_Decode, + 166, + 22, + 239, + 1, // Opcode: VPKLSG + /* 9941 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 9956 + /* 9946 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 9956 + /* 9951 */ MCD_OPC_Decode, + 167, + 22, + 239, + 1, // Opcode: VPKLSGS + /* 9956 */ MCD_OPC_CheckPredicate, + 34, + 227, + 51, + 0, // Skip to: 23244 + /* 9961 */ MCD_OPC_Decode, + 163, + 22, + 236, + 1, // Opcode: VPKLS + /* 9966 */ MCD_OPC_FilterValue, + 151, + 1, + 151, + 0, + 0, // Skip to: 10123 + /* 9972 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 9975 */ MCD_OPC_FilterValue, + 0, + 208, + 51, + 0, // Skip to: 23244 + /* 9980 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 9983 */ MCD_OPC_FilterValue, + 0, + 200, + 51, + 0, // Skip to: 23244 + /* 9988 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 9991 */ MCD_OPC_FilterValue, + 0, + 192, + 51, + 0, // Skip to: 23244 + /* 9996 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 9999 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 10037 + /* 10004 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 10007 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10022 + /* 10012 */ MCD_OPC_CheckPredicate, + 34, + 96, + 0, + 0, // Skip to: 10113 + /* 10017 */ MCD_OPC_Decode, + 175, + 22, + 239, + 1, // Opcode: VPKSH + /* 10022 */ MCD_OPC_FilterValue, + 1, + 86, + 0, + 0, // Skip to: 10113 + /* 10027 */ MCD_OPC_CheckPredicate, + 34, + 81, + 0, + 0, // Skip to: 10113 + /* 10032 */ MCD_OPC_Decode, + 176, + 22, + 239, + 1, // Opcode: VPKSHS + /* 10037 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 10075 + /* 10042 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 10045 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10060 + /* 10050 */ MCD_OPC_CheckPredicate, + 34, + 58, + 0, + 0, // Skip to: 10113 + /* 10055 */ MCD_OPC_Decode, + 171, + 22, + 239, + 1, // Opcode: VPKSF + /* 10060 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 10113 + /* 10065 */ MCD_OPC_CheckPredicate, + 34, + 43, + 0, + 0, // Skip to: 10113 + /* 10070 */ MCD_OPC_Decode, + 172, + 22, + 239, + 1, // Opcode: VPKSFS + /* 10075 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 10113 + /* 10080 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 10083 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10098 + /* 10088 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 10113 + /* 10093 */ MCD_OPC_Decode, + 173, + 22, + 239, + 1, // Opcode: VPKSG + /* 10098 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10113 + /* 10103 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 10113 + /* 10108 */ MCD_OPC_Decode, + 174, + 22, + 239, + 1, // Opcode: VPKSGS + /* 10113 */ MCD_OPC_CheckPredicate, + 34, + 70, + 51, + 0, // Skip to: 23244 + /* 10118 */ MCD_OPC_Decode, + 170, + 22, + 236, + 1, // Opcode: VPKS + /* 10123 */ MCD_OPC_FilterValue, + 158, + 1, + 119, + 0, + 0, // Skip to: 10248 + /* 10129 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 10132 */ MCD_OPC_FilterValue, + 0, + 51, + 51, + 0, // Skip to: 23244 + /* 10137 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 10140 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 10178 + /* 10145 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 10148 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10163 + /* 10153 */ MCD_OPC_CheckPredicate, + 35, + 80, + 0, + 0, // Skip to: 10238 + /* 10158 */ MCD_OPC_Decode, + 202, + 20, + 160, + 2, // Opcode: VFNMSSB + /* 10163 */ MCD_OPC_FilterValue, + 8, + 70, + 0, + 0, // Skip to: 10238 + /* 10168 */ MCD_OPC_CheckPredicate, + 35, + 65, + 0, + 0, // Skip to: 10238 + /* 10173 */ MCD_OPC_Decode, + 149, + 24, + 161, + 2, // Opcode: WFNMSSB + /* 10178 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 10216 + /* 10183 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 10186 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10201 + /* 10191 */ MCD_OPC_CheckPredicate, + 35, + 42, + 0, + 0, // Skip to: 10238 + /* 10196 */ MCD_OPC_Decode, + 201, + 20, + 160, + 2, // Opcode: VFNMSDB + /* 10201 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 10238 + /* 10206 */ MCD_OPC_CheckPredicate, + 35, + 27, + 0, + 0, // Skip to: 10238 + /* 10211 */ MCD_OPC_Decode, + 148, + 24, + 162, + 2, // Opcode: WFNMSDB + /* 10216 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 10238 + /* 10221 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 10238 + /* 10226 */ MCD_OPC_CheckField, + 16, + 4, + 8, + 5, + 0, + 0, // Skip to: 10238 + /* 10233 */ MCD_OPC_Decode, + 150, + 24, + 160, + 2, // Opcode: WFNMSXB + /* 10238 */ MCD_OPC_CheckPredicate, + 35, + 201, + 50, + 0, // Skip to: 23244 + /* 10243 */ MCD_OPC_Decode, + 200, + 20, + 163, + 2, // Opcode: VFNMS + /* 10248 */ MCD_OPC_FilterValue, + 159, + 1, + 119, + 0, + 0, // Skip to: 10373 + /* 10254 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 10257 */ MCD_OPC_FilterValue, + 0, + 182, + 50, + 0, // Skip to: 23244 + /* 10262 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 10265 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 10303 + /* 10270 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 10273 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10288 + /* 10278 */ MCD_OPC_CheckPredicate, + 35, + 80, + 0, + 0, // Skip to: 10363 + /* 10283 */ MCD_OPC_Decode, + 199, + 20, + 160, + 2, // Opcode: VFNMASB + /* 10288 */ MCD_OPC_FilterValue, + 8, + 70, + 0, + 0, // Skip to: 10363 + /* 10293 */ MCD_OPC_CheckPredicate, + 35, + 65, + 0, + 0, // Skip to: 10363 + /* 10298 */ MCD_OPC_Decode, + 146, + 24, + 161, + 2, // Opcode: WFNMASB + /* 10303 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 10341 + /* 10308 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 10311 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10326 + /* 10316 */ MCD_OPC_CheckPredicate, + 35, + 42, + 0, + 0, // Skip to: 10363 + /* 10321 */ MCD_OPC_Decode, + 198, + 20, + 160, + 2, // Opcode: VFNMADB + /* 10326 */ MCD_OPC_FilterValue, + 8, + 32, + 0, + 0, // Skip to: 10363 + /* 10331 */ MCD_OPC_CheckPredicate, + 35, + 27, + 0, + 0, // Skip to: 10363 + /* 10336 */ MCD_OPC_Decode, + 145, + 24, + 162, + 2, // Opcode: WFNMADB + /* 10341 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 10363 + /* 10346 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 10363 + /* 10351 */ MCD_OPC_CheckField, + 16, + 4, + 8, + 5, + 0, + 0, // Skip to: 10363 + /* 10358 */ MCD_OPC_Decode, + 147, + 24, + 160, + 2, // Opcode: WFNMAXB + /* 10363 */ MCD_OPC_CheckPredicate, + 35, + 76, + 50, + 0, // Skip to: 23244 + /* 10368 */ MCD_OPC_Decode, + 197, + 20, + 163, + 2, // Opcode: VFNMA + /* 10373 */ MCD_OPC_FilterValue, + 161, + 1, + 74, + 0, + 0, // Skip to: 10453 + /* 10379 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 10382 */ MCD_OPC_FilterValue, + 0, + 57, + 50, + 0, // Skip to: 23244 + /* 10387 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 10390 */ MCD_OPC_FilterValue, + 0, + 49, + 50, + 0, // Skip to: 23244 + /* 10395 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 10398 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10413 + /* 10403 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 10443 + /* 10408 */ MCD_OPC_Decode, + 231, + 21, + 239, + 1, // Opcode: VMLHB + /* 10413 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10428 + /* 10418 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 10443 + /* 10423 */ MCD_OPC_Decode, + 233, + 21, + 239, + 1, // Opcode: VMLHH + /* 10428 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10443 + /* 10433 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 10443 + /* 10438 */ MCD_OPC_Decode, + 232, + 21, + 239, + 1, // Opcode: VMLHF + /* 10443 */ MCD_OPC_CheckPredicate, + 34, + 252, + 49, + 0, // Skip to: 23244 + /* 10448 */ MCD_OPC_Decode, + 230, + 21, + 147, + 2, // Opcode: VMLH + /* 10453 */ MCD_OPC_FilterValue, + 162, + 1, + 74, + 0, + 0, // Skip to: 10533 + /* 10459 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 10462 */ MCD_OPC_FilterValue, + 0, + 233, + 49, + 0, // Skip to: 23244 + /* 10467 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 10470 */ MCD_OPC_FilterValue, + 0, + 225, + 49, + 0, // Skip to: 23244 + /* 10475 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 10478 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10493 + /* 10483 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 10523 + /* 10488 */ MCD_OPC_Decode, + 224, + 21, + 239, + 1, // Opcode: VMLB + /* 10493 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10508 + /* 10498 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 10523 + /* 10503 */ MCD_OPC_Decode, + 234, + 21, + 239, + 1, // Opcode: VMLHW + /* 10508 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10523 + /* 10513 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 10523 + /* 10518 */ MCD_OPC_Decode, + 229, + 21, + 239, + 1, // Opcode: VMLF + /* 10523 */ MCD_OPC_CheckPredicate, + 34, + 172, + 49, + 0, // Skip to: 23244 + /* 10528 */ MCD_OPC_Decode, + 223, + 21, + 147, + 2, // Opcode: VML + /* 10533 */ MCD_OPC_FilterValue, + 163, + 1, + 74, + 0, + 0, // Skip to: 10613 + /* 10539 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 10542 */ MCD_OPC_FilterValue, + 0, + 153, + 49, + 0, // Skip to: 23244 + /* 10547 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 10550 */ MCD_OPC_FilterValue, + 0, + 145, + 49, + 0, // Skip to: 23244 + /* 10555 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 10558 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10573 + /* 10563 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 10603 + /* 10568 */ MCD_OPC_Decode, + 220, + 21, + 239, + 1, // Opcode: VMHB + /* 10573 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10588 + /* 10578 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 10603 + /* 10583 */ MCD_OPC_Decode, + 222, + 21, + 239, + 1, // Opcode: VMHH + /* 10588 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10603 + /* 10593 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 10603 + /* 10598 */ MCD_OPC_Decode, + 221, + 21, + 239, + 1, // Opcode: VMHF + /* 10603 */ MCD_OPC_CheckPredicate, + 34, + 92, + 49, + 0, // Skip to: 23244 + /* 10608 */ MCD_OPC_Decode, + 219, + 21, + 147, + 2, // Opcode: VMH + /* 10613 */ MCD_OPC_FilterValue, + 164, + 1, + 74, + 0, + 0, // Skip to: 10693 + /* 10619 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 10622 */ MCD_OPC_FilterValue, + 0, + 73, + 49, + 0, // Skip to: 23244 + /* 10627 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 10630 */ MCD_OPC_FilterValue, + 0, + 65, + 49, + 0, // Skip to: 23244 + /* 10635 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 10638 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10653 + /* 10643 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 10683 + /* 10648 */ MCD_OPC_Decode, + 226, + 21, + 239, + 1, // Opcode: VMLEB + /* 10653 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10668 + /* 10658 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 10683 + /* 10663 */ MCD_OPC_Decode, + 228, + 21, + 239, + 1, // Opcode: VMLEH + /* 10668 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10683 + /* 10673 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 10683 + /* 10678 */ MCD_OPC_Decode, + 227, + 21, + 239, + 1, // Opcode: VMLEF + /* 10683 */ MCD_OPC_CheckPredicate, + 34, + 12, + 49, + 0, // Skip to: 23244 + /* 10688 */ MCD_OPC_Decode, + 225, + 21, + 147, + 2, // Opcode: VMLE + /* 10693 */ MCD_OPC_FilterValue, + 165, + 1, + 74, + 0, + 0, // Skip to: 10773 + /* 10699 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 10702 */ MCD_OPC_FilterValue, + 0, + 249, + 48, + 0, // Skip to: 23244 + /* 10707 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 10710 */ MCD_OPC_FilterValue, + 0, + 241, + 48, + 0, // Skip to: 23244 + /* 10715 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 10718 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10733 + /* 10723 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 10763 + /* 10728 */ MCD_OPC_Decode, + 236, + 21, + 239, + 1, // Opcode: VMLOB + /* 10733 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10748 + /* 10738 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 10763 + /* 10743 */ MCD_OPC_Decode, + 238, + 21, + 239, + 1, // Opcode: VMLOH + /* 10748 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10763 + /* 10753 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 10763 + /* 10758 */ MCD_OPC_Decode, + 237, + 21, + 239, + 1, // Opcode: VMLOF + /* 10763 */ MCD_OPC_CheckPredicate, + 34, + 188, + 48, + 0, // Skip to: 23244 + /* 10768 */ MCD_OPC_Decode, + 235, + 21, + 147, + 2, // Opcode: VMLO + /* 10773 */ MCD_OPC_FilterValue, + 166, + 1, + 74, + 0, + 0, // Skip to: 10853 + /* 10779 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 10782 */ MCD_OPC_FilterValue, + 0, + 169, + 48, + 0, // Skip to: 23244 + /* 10787 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 10790 */ MCD_OPC_FilterValue, + 0, + 161, + 48, + 0, // Skip to: 23244 + /* 10795 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 10798 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10813 + /* 10803 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 10843 + /* 10808 */ MCD_OPC_Decode, + 216, + 21, + 239, + 1, // Opcode: VMEB + /* 10813 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10828 + /* 10818 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 10843 + /* 10823 */ MCD_OPC_Decode, + 218, + 21, + 239, + 1, // Opcode: VMEH + /* 10828 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10843 + /* 10833 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 10843 + /* 10838 */ MCD_OPC_Decode, + 217, + 21, + 239, + 1, // Opcode: VMEF + /* 10843 */ MCD_OPC_CheckPredicate, + 34, + 108, + 48, + 0, // Skip to: 23244 + /* 10848 */ MCD_OPC_Decode, + 215, + 21, + 147, + 2, // Opcode: VME + /* 10853 */ MCD_OPC_FilterValue, + 167, + 1, + 74, + 0, + 0, // Skip to: 10933 + /* 10859 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 10862 */ MCD_OPC_FilterValue, + 0, + 89, + 48, + 0, // Skip to: 23244 + /* 10867 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 10870 */ MCD_OPC_FilterValue, + 0, + 81, + 48, + 0, // Skip to: 23244 + /* 10875 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 10878 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10893 + /* 10883 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 10923 + /* 10888 */ MCD_OPC_Decode, + 250, + 21, + 239, + 1, // Opcode: VMOB + /* 10893 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10908 + /* 10898 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 10923 + /* 10903 */ MCD_OPC_Decode, + 252, + 21, + 239, + 1, // Opcode: VMOH + /* 10908 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10923 + /* 10913 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 10923 + /* 10918 */ MCD_OPC_Decode, + 251, + 21, + 239, + 1, // Opcode: VMOF + /* 10923 */ MCD_OPC_CheckPredicate, + 34, + 28, + 48, + 0, // Skip to: 23244 + /* 10928 */ MCD_OPC_Decode, + 249, + 21, + 147, + 2, // Opcode: VMO + /* 10933 */ MCD_OPC_FilterValue, + 169, + 1, + 66, + 0, + 0, // Skip to: 11005 + /* 10939 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 10942 */ MCD_OPC_FilterValue, + 0, + 9, + 48, + 0, // Skip to: 23244 + /* 10947 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 10950 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 10965 + /* 10955 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 10995 + /* 10960 */ MCD_OPC_Decode, + 203, + 21, + 160, + 2, // Opcode: VMALHB + /* 10965 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 10980 + /* 10970 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 10995 + /* 10975 */ MCD_OPC_Decode, + 205, + 21, + 160, + 2, // Opcode: VMALHH + /* 10980 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 10995 + /* 10985 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 10995 + /* 10990 */ MCD_OPC_Decode, + 204, + 21, + 160, + 2, // Opcode: VMALHF + /* 10995 */ MCD_OPC_CheckPredicate, + 34, + 212, + 47, + 0, // Skip to: 23244 + /* 11000 */ MCD_OPC_Decode, + 202, + 21, + 164, + 2, // Opcode: VMALH + /* 11005 */ MCD_OPC_FilterValue, + 170, + 1, + 66, + 0, + 0, // Skip to: 11077 + /* 11011 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11014 */ MCD_OPC_FilterValue, + 0, + 193, + 47, + 0, // Skip to: 23244 + /* 11019 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 11022 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11037 + /* 11027 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 11067 + /* 11032 */ MCD_OPC_Decode, + 196, + 21, + 160, + 2, // Opcode: VMALB + /* 11037 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11052 + /* 11042 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 11067 + /* 11047 */ MCD_OPC_Decode, + 206, + 21, + 160, + 2, // Opcode: VMALHW + /* 11052 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11067 + /* 11057 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 11067 + /* 11062 */ MCD_OPC_Decode, + 201, + 21, + 160, + 2, // Opcode: VMALF + /* 11067 */ MCD_OPC_CheckPredicate, + 34, + 140, + 47, + 0, // Skip to: 23244 + /* 11072 */ MCD_OPC_Decode, + 195, + 21, + 164, + 2, // Opcode: VMAL + /* 11077 */ MCD_OPC_FilterValue, + 171, + 1, + 66, + 0, + 0, // Skip to: 11149 + /* 11083 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11086 */ MCD_OPC_FilterValue, + 0, + 121, + 47, + 0, // Skip to: 23244 + /* 11091 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 11094 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11109 + /* 11099 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 11139 + /* 11104 */ MCD_OPC_Decode, + 192, + 21, + 160, + 2, // Opcode: VMAHB + /* 11109 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11124 + /* 11114 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 11139 + /* 11119 */ MCD_OPC_Decode, + 194, + 21, + 160, + 2, // Opcode: VMAHH + /* 11124 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11139 + /* 11129 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 11139 + /* 11134 */ MCD_OPC_Decode, + 193, + 21, + 160, + 2, // Opcode: VMAHF + /* 11139 */ MCD_OPC_CheckPredicate, + 34, + 68, + 47, + 0, // Skip to: 23244 + /* 11144 */ MCD_OPC_Decode, + 191, + 21, + 164, + 2, // Opcode: VMAH + /* 11149 */ MCD_OPC_FilterValue, + 172, + 1, + 66, + 0, + 0, // Skip to: 11221 + /* 11155 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11158 */ MCD_OPC_FilterValue, + 0, + 49, + 47, + 0, // Skip to: 23244 + /* 11163 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 11166 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11181 + /* 11171 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 11211 + /* 11176 */ MCD_OPC_Decode, + 198, + 21, + 160, + 2, // Opcode: VMALEB + /* 11181 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11196 + /* 11186 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 11211 + /* 11191 */ MCD_OPC_Decode, + 200, + 21, + 160, + 2, // Opcode: VMALEH + /* 11196 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11211 + /* 11201 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 11211 + /* 11206 */ MCD_OPC_Decode, + 199, + 21, + 160, + 2, // Opcode: VMALEF + /* 11211 */ MCD_OPC_CheckPredicate, + 34, + 252, + 46, + 0, // Skip to: 23244 + /* 11216 */ MCD_OPC_Decode, + 197, + 21, + 164, + 2, // Opcode: VMALE + /* 11221 */ MCD_OPC_FilterValue, + 173, + 1, + 66, + 0, + 0, // Skip to: 11293 + /* 11227 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11230 */ MCD_OPC_FilterValue, + 0, + 233, + 46, + 0, // Skip to: 23244 + /* 11235 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 11238 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11253 + /* 11243 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 11283 + /* 11248 */ MCD_OPC_Decode, + 208, + 21, + 160, + 2, // Opcode: VMALOB + /* 11253 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11268 + /* 11258 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 11283 + /* 11263 */ MCD_OPC_Decode, + 210, + 21, + 160, + 2, // Opcode: VMALOH + /* 11268 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11283 + /* 11273 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 11283 + /* 11278 */ MCD_OPC_Decode, + 209, + 21, + 160, + 2, // Opcode: VMALOF + /* 11283 */ MCD_OPC_CheckPredicate, + 34, + 180, + 46, + 0, // Skip to: 23244 + /* 11288 */ MCD_OPC_Decode, + 207, + 21, + 164, + 2, // Opcode: VMALO + /* 11293 */ MCD_OPC_FilterValue, + 174, + 1, + 66, + 0, + 0, // Skip to: 11365 + /* 11299 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11302 */ MCD_OPC_FilterValue, + 0, + 161, + 46, + 0, // Skip to: 23244 + /* 11307 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 11310 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11325 + /* 11315 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 11355 + /* 11320 */ MCD_OPC_Decode, + 188, + 21, + 160, + 2, // Opcode: VMAEB + /* 11325 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11340 + /* 11330 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 11355 + /* 11335 */ MCD_OPC_Decode, + 190, + 21, + 160, + 2, // Opcode: VMAEH + /* 11340 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11355 + /* 11345 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 11355 + /* 11350 */ MCD_OPC_Decode, + 189, + 21, + 160, + 2, // Opcode: VMAEF + /* 11355 */ MCD_OPC_CheckPredicate, + 34, + 108, + 46, + 0, // Skip to: 23244 + /* 11360 */ MCD_OPC_Decode, + 187, + 21, + 164, + 2, // Opcode: VMAE + /* 11365 */ MCD_OPC_FilterValue, + 175, + 1, + 66, + 0, + 0, // Skip to: 11437 + /* 11371 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11374 */ MCD_OPC_FilterValue, + 0, + 89, + 46, + 0, // Skip to: 23244 + /* 11379 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 11382 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11397 + /* 11387 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 11427 + /* 11392 */ MCD_OPC_Decode, + 212, + 21, + 160, + 2, // Opcode: VMAOB + /* 11397 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11412 + /* 11402 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 11427 + /* 11407 */ MCD_OPC_Decode, + 214, + 21, + 160, + 2, // Opcode: VMAOH + /* 11412 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11427 + /* 11417 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 11427 + /* 11422 */ MCD_OPC_Decode, + 213, + 21, + 160, + 2, // Opcode: VMAOF + /* 11427 */ MCD_OPC_CheckPredicate, + 34, + 36, + 46, + 0, // Skip to: 23244 + /* 11432 */ MCD_OPC_Decode, + 211, + 21, + 164, + 2, // Opcode: VMAO + /* 11437 */ MCD_OPC_FilterValue, + 180, + 1, + 89, + 0, + 0, // Skip to: 11532 + /* 11443 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 11446 */ MCD_OPC_FilterValue, + 0, + 17, + 46, + 0, // Skip to: 23244 + /* 11451 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 11454 */ MCD_OPC_FilterValue, + 0, + 9, + 46, + 0, // Skip to: 23244 + /* 11459 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 11462 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11477 + /* 11467 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 11522 + /* 11472 */ MCD_OPC_Decode, + 224, + 20, + 239, + 1, // Opcode: VGFMB + /* 11477 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11492 + /* 11482 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 11522 + /* 11487 */ MCD_OPC_Decode, + 227, + 20, + 239, + 1, // Opcode: VGFMH + /* 11492 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11507 + /* 11497 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 11522 + /* 11502 */ MCD_OPC_Decode, + 225, + 20, + 239, + 1, // Opcode: VGFMF + /* 11507 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 11522 + /* 11512 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 11522 + /* 11517 */ MCD_OPC_Decode, + 226, + 20, + 239, + 1, // Opcode: VGFMG + /* 11522 */ MCD_OPC_CheckPredicate, + 34, + 197, + 45, + 0, // Skip to: 23244 + /* 11527 */ MCD_OPC_Decode, + 218, + 20, + 147, + 2, // Opcode: VGFM + /* 11532 */ MCD_OPC_FilterValue, + 184, + 1, + 35, + 0, + 0, // Skip to: 11573 + /* 11538 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 11541 */ MCD_OPC_FilterValue, + 0, + 178, + 45, + 0, // Skip to: 23244 + /* 11546 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 11563 + /* 11551 */ MCD_OPC_CheckField, + 24, + 4, + 3, + 5, + 0, + 0, // Skip to: 11563 + /* 11558 */ MCD_OPC_Decode, + 137, + 22, + 158, + 2, // Opcode: VMSLG + /* 11563 */ MCD_OPC_CheckPredicate, + 35, + 156, + 45, + 0, // Skip to: 23244 + /* 11568 */ MCD_OPC_Decode, + 136, + 22, + 159, + 2, // Opcode: VMSL + /* 11573 */ MCD_OPC_FilterValue, + 185, + 1, + 35, + 0, + 0, // Skip to: 11614 + /* 11579 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11582 */ MCD_OPC_FilterValue, + 0, + 137, + 45, + 0, // Skip to: 23244 + /* 11587 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 11604 + /* 11592 */ MCD_OPC_CheckField, + 24, + 4, + 4, + 5, + 0, + 0, // Skip to: 11604 + /* 11599 */ MCD_OPC_Decode, + 207, + 18, + 160, + 2, // Opcode: VACCCQ + /* 11604 */ MCD_OPC_CheckPredicate, + 34, + 115, + 45, + 0, // Skip to: 23244 + /* 11609 */ MCD_OPC_Decode, + 206, + 18, + 164, + 2, // Opcode: VACCC + /* 11614 */ MCD_OPC_FilterValue, + 187, + 1, + 35, + 0, + 0, // Skip to: 11655 + /* 11620 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11623 */ MCD_OPC_FilterValue, + 0, + 96, + 45, + 0, // Skip to: 23244 + /* 11628 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 11645 + /* 11633 */ MCD_OPC_CheckField, + 24, + 4, + 4, + 5, + 0, + 0, // Skip to: 11645 + /* 11640 */ MCD_OPC_Decode, + 212, + 18, + 160, + 2, // Opcode: VACQ + /* 11645 */ MCD_OPC_CheckPredicate, + 34, + 74, + 45, + 0, // Skip to: 23244 + /* 11650 */ MCD_OPC_Decode, + 203, + 18, + 164, + 2, // Opcode: VAC + /* 11655 */ MCD_OPC_FilterValue, + 188, + 1, + 81, + 0, + 0, // Skip to: 11742 + /* 11661 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11664 */ MCD_OPC_FilterValue, + 0, + 55, + 45, + 0, // Skip to: 23244 + /* 11669 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 11672 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 11687 + /* 11677 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 11732 + /* 11682 */ MCD_OPC_Decode, + 220, + 20, + 160, + 2, // Opcode: VGFMAB + /* 11687 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 11702 + /* 11692 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 11732 + /* 11697 */ MCD_OPC_Decode, + 223, + 20, + 160, + 2, // Opcode: VGFMAH + /* 11702 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 11717 + /* 11707 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 11732 + /* 11712 */ MCD_OPC_Decode, + 221, + 20, + 160, + 2, // Opcode: VGFMAF + /* 11717 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 11732 + /* 11722 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 11732 + /* 11727 */ MCD_OPC_Decode, + 222, + 20, + 160, + 2, // Opcode: VGFMAG + /* 11732 */ MCD_OPC_CheckPredicate, + 34, + 243, + 44, + 0, // Skip to: 23244 + /* 11737 */ MCD_OPC_Decode, + 219, + 20, + 164, + 2, // Opcode: VGFMA + /* 11742 */ MCD_OPC_FilterValue, + 189, + 1, + 35, + 0, + 0, // Skip to: 11783 + /* 11748 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11751 */ MCD_OPC_FilterValue, + 0, + 224, + 44, + 0, // Skip to: 23244 + /* 11756 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 11773 + /* 11761 */ MCD_OPC_CheckField, + 24, + 4, + 4, + 5, + 0, + 0, // Skip to: 11773 + /* 11768 */ MCD_OPC_Decode, + 199, + 22, + 160, + 2, // Opcode: VSBCBIQ + /* 11773 */ MCD_OPC_CheckPredicate, + 34, + 202, + 44, + 0, // Skip to: 23244 + /* 11778 */ MCD_OPC_Decode, + 198, + 22, + 164, + 2, // Opcode: VSBCBI + /* 11783 */ MCD_OPC_FilterValue, + 191, + 1, + 35, + 0, + 0, // Skip to: 11824 + /* 11789 */ MCD_OPC_ExtractField, + 16, + 8, // Inst{23-16} ... + /* 11792 */ MCD_OPC_FilterValue, + 0, + 183, + 44, + 0, // Skip to: 23244 + /* 11797 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 11814 + /* 11802 */ MCD_OPC_CheckField, + 24, + 4, + 4, + 5, + 0, + 0, // Skip to: 11814 + /* 11809 */ MCD_OPC_Decode, + 201, + 22, + 160, + 2, // Opcode: VSBIQ + /* 11814 */ MCD_OPC_CheckPredicate, + 34, + 161, + 44, + 0, // Skip to: 23244 + /* 11819 */ MCD_OPC_Decode, + 200, + 22, + 164, + 2, // Opcode: VSBI + /* 11824 */ MCD_OPC_FilterValue, + 192, + 1, + 93, + 0, + 0, // Skip to: 11923 + /* 11830 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 11833 */ MCD_OPC_FilterValue, + 0, + 142, + 44, + 0, // Skip to: 23244 + /* 11838 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11841 */ MCD_OPC_FilterValue, + 0, + 134, + 44, + 0, // Skip to: 23244 + /* 11846 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 11849 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 11881 + /* 11854 */ MCD_OPC_CheckPredicate, + 29, + 12, + 0, + 0, // Skip to: 11871 + /* 11859 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 11871 + /* 11866 */ MCD_OPC_Decode, + 190, + 23, + 165, + 2, // Opcode: WCLFEB + /* 11871 */ MCD_OPC_CheckPredicate, + 29, + 37, + 0, + 0, // Skip to: 11913 + /* 11876 */ MCD_OPC_Decode, + 141, + 19, + 166, + 2, // Opcode: VCLFEB + /* 11881 */ MCD_OPC_FilterValue, + 3, + 27, + 0, + 0, // Skip to: 11913 + /* 11886 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 11903 + /* 11891 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 11903 + /* 11898 */ MCD_OPC_Decode, + 191, + 23, + 167, + 2, // Opcode: WCLGDB + /* 11903 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 11913 + /* 11908 */ MCD_OPC_Decode, + 146, + 19, + 166, + 2, // Opcode: VCLGDB + /* 11913 */ MCD_OPC_CheckPredicate, + 34, + 62, + 44, + 0, // Skip to: 23244 + /* 11918 */ MCD_OPC_Decode, + 145, + 19, + 168, + 2, // Opcode: VCLGD + /* 11923 */ MCD_OPC_FilterValue, + 193, + 1, + 93, + 0, + 0, // Skip to: 12022 + /* 11929 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 11932 */ MCD_OPC_FilterValue, + 0, + 43, + 44, + 0, // Skip to: 23244 + /* 11937 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 11940 */ MCD_OPC_FilterValue, + 0, + 35, + 44, + 0, // Skip to: 23244 + /* 11945 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 11948 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 11980 + /* 11953 */ MCD_OPC_CheckPredicate, + 29, + 12, + 0, + 0, // Skip to: 11970 + /* 11958 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 11970 + /* 11965 */ MCD_OPC_Decode, + 187, + 23, + 165, + 2, // Opcode: WCELFB + /* 11970 */ MCD_OPC_CheckPredicate, + 29, + 37, + 0, + 0, // Skip to: 12012 + /* 11975 */ MCD_OPC_Decode, + 234, + 18, + 166, + 2, // Opcode: VCELFB + /* 11980 */ MCD_OPC_FilterValue, + 3, + 27, + 0, + 0, // Skip to: 12012 + /* 11985 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 12002 + /* 11990 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12002 + /* 11997 */ MCD_OPC_Decode, + 185, + 23, + 167, + 2, // Opcode: WCDLGB + /* 12002 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 12012 + /* 12007 */ MCD_OPC_Decode, + 232, + 18, + 166, + 2, // Opcode: VCDLGB + /* 12012 */ MCD_OPC_CheckPredicate, + 34, + 219, + 43, + 0, // Skip to: 23244 + /* 12017 */ MCD_OPC_Decode, + 231, + 18, + 168, + 2, // Opcode: VCDLG + /* 12022 */ MCD_OPC_FilterValue, + 194, + 1, + 93, + 0, + 0, // Skip to: 12121 + /* 12028 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 12031 */ MCD_OPC_FilterValue, + 0, + 200, + 43, + 0, // Skip to: 23244 + /* 12036 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12039 */ MCD_OPC_FilterValue, + 0, + 192, + 43, + 0, // Skip to: 23244 + /* 12044 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 12047 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 12079 + /* 12052 */ MCD_OPC_CheckPredicate, + 29, + 12, + 0, + 0, // Skip to: 12069 + /* 12057 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12069 + /* 12064 */ MCD_OPC_Decode, + 188, + 23, + 165, + 2, // Opcode: WCFEB + /* 12069 */ MCD_OPC_CheckPredicate, + 29, + 37, + 0, + 0, // Skip to: 12111 + /* 12074 */ MCD_OPC_Decode, + 244, + 18, + 166, + 2, // Opcode: VCFEB + /* 12079 */ MCD_OPC_FilterValue, + 3, + 27, + 0, + 0, // Skip to: 12111 + /* 12084 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 12101 + /* 12089 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12101 + /* 12096 */ MCD_OPC_Decode, + 189, + 23, + 167, + 2, // Opcode: WCGDB + /* 12101 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 12111 + /* 12106 */ MCD_OPC_Decode, + 249, + 18, + 166, + 2, // Opcode: VCGDB + /* 12111 */ MCD_OPC_CheckPredicate, + 34, + 120, + 43, + 0, // Skip to: 23244 + /* 12116 */ MCD_OPC_Decode, + 248, + 18, + 168, + 2, // Opcode: VCGD + /* 12121 */ MCD_OPC_FilterValue, + 195, + 1, + 93, + 0, + 0, // Skip to: 12220 + /* 12127 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 12130 */ MCD_OPC_FilterValue, + 0, + 101, + 43, + 0, // Skip to: 23244 + /* 12135 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12138 */ MCD_OPC_FilterValue, + 0, + 93, + 43, + 0, // Skip to: 23244 + /* 12143 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 12146 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 12178 + /* 12151 */ MCD_OPC_CheckPredicate, + 29, + 12, + 0, + 0, // Skip to: 12168 + /* 12156 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12168 + /* 12163 */ MCD_OPC_Decode, + 186, + 23, + 165, + 2, // Opcode: WCEFB + /* 12168 */ MCD_OPC_CheckPredicate, + 29, + 37, + 0, + 0, // Skip to: 12210 + /* 12173 */ MCD_OPC_Decode, + 233, + 18, + 166, + 2, // Opcode: VCEFB + /* 12178 */ MCD_OPC_FilterValue, + 3, + 27, + 0, + 0, // Skip to: 12210 + /* 12183 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 12200 + /* 12188 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12200 + /* 12195 */ MCD_OPC_Decode, + 184, + 23, + 167, + 2, // Opcode: WCDGB + /* 12200 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 12210 + /* 12205 */ MCD_OPC_Decode, + 230, + 18, + 166, + 2, // Opcode: VCDGB + /* 12210 */ MCD_OPC_CheckPredicate, + 34, + 21, + 43, + 0, // Skip to: 23244 + /* 12215 */ MCD_OPC_Decode, + 229, + 18, + 168, + 2, // Opcode: VCDG + /* 12220 */ MCD_OPC_FilterValue, + 196, + 1, + 76, + 0, + 0, // Skip to: 12302 + /* 12226 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 12229 */ MCD_OPC_FilterValue, + 0, + 2, + 43, + 0, // Skip to: 23244 + /* 12234 */ MCD_OPC_ExtractField, + 20, + 12, // Inst{31-20} ... + /* 12237 */ MCD_OPC_FilterValue, + 0, + 250, + 42, + 0, // Skip to: 23244 + /* 12242 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 12245 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12260 + /* 12250 */ MCD_OPC_CheckPredicate, + 34, + 37, + 0, + 0, // Skip to: 12292 + /* 12255 */ MCD_OPC_Decode, + 130, + 21, + 144, + 2, // Opcode: VLDEB + /* 12260 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 12276 + /* 12266 */ MCD_OPC_CheckPredicate, + 34, + 21, + 0, + 0, // Skip to: 12292 + /* 12271 */ MCD_OPC_Decode, + 163, + 24, + 169, + 2, // Opcode: WLDEB + /* 12276 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 12292 + /* 12282 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 12292 + /* 12287 */ MCD_OPC_Decode, + 248, + 23, + 170, + 2, // Opcode: WFLLD + /* 12292 */ MCD_OPC_CheckPredicate, + 34, + 195, + 42, + 0, // Skip to: 23244 + /* 12297 */ MCD_OPC_Decode, + 129, + 21, + 229, + 1, // Opcode: VLDE + /* 12302 */ MCD_OPC_FilterValue, + 197, + 1, + 83, + 0, + 0, // Skip to: 12391 + /* 12308 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 12311 */ MCD_OPC_FilterValue, + 0, + 176, + 42, + 0, // Skip to: 23244 + /* 12316 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12319 */ MCD_OPC_FilterValue, + 0, + 168, + 42, + 0, // Skip to: 23244 + /* 12324 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 12327 */ MCD_OPC_FilterValue, + 3, + 27, + 0, + 0, // Skip to: 12359 + /* 12332 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 12349 + /* 12337 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12349 + /* 12344 */ MCD_OPC_Decode, + 164, + 24, + 171, + 2, // Opcode: WLEDB + /* 12349 */ MCD_OPC_CheckPredicate, + 34, + 27, + 0, + 0, // Skip to: 12381 + /* 12354 */ MCD_OPC_Decode, + 136, + 21, + 166, + 2, // Opcode: VLEDB + /* 12359 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 12381 + /* 12364 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 12381 + /* 12369 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12381 + /* 12376 */ MCD_OPC_Decode, + 129, + 24, + 172, + 2, // Opcode: WFLRX + /* 12381 */ MCD_OPC_CheckPredicate, + 34, + 106, + 42, + 0, // Skip to: 23244 + /* 12386 */ MCD_OPC_Decode, + 135, + 21, + 168, + 2, // Opcode: VLED + /* 12391 */ MCD_OPC_FilterValue, + 199, + 1, + 115, + 0, + 0, // Skip to: 12512 + /* 12397 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 12400 */ MCD_OPC_FilterValue, + 0, + 87, + 42, + 0, // Skip to: 23244 + /* 12405 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12408 */ MCD_OPC_FilterValue, + 0, + 79, + 42, + 0, // Skip to: 23244 + /* 12413 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 12416 */ MCD_OPC_FilterValue, + 2, + 27, + 0, + 0, // Skip to: 12448 + /* 12421 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 12438 + /* 12426 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12438 + /* 12433 */ MCD_OPC_Decode, + 221, + 23, + 165, + 2, // Opcode: WFISB + /* 12438 */ MCD_OPC_CheckPredicate, + 35, + 59, + 0, + 0, // Skip to: 12502 + /* 12443 */ MCD_OPC_Decode, + 159, + 20, + 166, + 2, // Opcode: VFISB + /* 12448 */ MCD_OPC_FilterValue, + 3, + 27, + 0, + 0, // Skip to: 12480 + /* 12453 */ MCD_OPC_CheckPredicate, + 34, + 12, + 0, + 0, // Skip to: 12470 + /* 12458 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12470 + /* 12465 */ MCD_OPC_Decode, + 220, + 23, + 167, + 2, // Opcode: WFIDB + /* 12470 */ MCD_OPC_CheckPredicate, + 34, + 27, + 0, + 0, // Skip to: 12502 + /* 12475 */ MCD_OPC_Decode, + 158, + 20, + 166, + 2, // Opcode: VFIDB + /* 12480 */ MCD_OPC_FilterValue, + 4, + 17, + 0, + 0, // Skip to: 12502 + /* 12485 */ MCD_OPC_CheckPredicate, + 35, + 12, + 0, + 0, // Skip to: 12502 + /* 12490 */ MCD_OPC_CheckField, + 19, + 1, + 1, + 5, + 0, + 0, // Skip to: 12502 + /* 12497 */ MCD_OPC_Decode, + 222, + 23, + 173, + 2, // Opcode: WFIXB + /* 12502 */ MCD_OPC_CheckPredicate, + 34, + 241, + 41, + 0, // Skip to: 23244 + /* 12507 */ MCD_OPC_Decode, + 157, + 20, + 168, + 2, // Opcode: VFI + /* 12512 */ MCD_OPC_FilterValue, + 202, + 1, + 74, + 0, + 0, // Skip to: 12592 + /* 12518 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 12521 */ MCD_OPC_FilterValue, + 0, + 222, + 41, + 0, // Skip to: 23244 + /* 12526 */ MCD_OPC_ExtractField, + 20, + 12, // Inst{31-20} ... + /* 12529 */ MCD_OPC_FilterValue, + 0, + 214, + 41, + 0, // Skip to: 23244 + /* 12534 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 12537 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12552 + /* 12542 */ MCD_OPC_CheckPredicate, + 35, + 35, + 0, + 0, // Skip to: 12582 + /* 12547 */ MCD_OPC_Decode, + 243, + 23, + 174, + 2, // Opcode: WFKSB + /* 12552 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12567 + /* 12557 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 12582 + /* 12562 */ MCD_OPC_Decode, + 224, + 23, + 175, + 2, // Opcode: WFKDB + /* 12567 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 12582 + /* 12572 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 12582 + /* 12577 */ MCD_OPC_Decode, + 244, + 23, + 144, + 2, // Opcode: WFKXB + /* 12582 */ MCD_OPC_CheckPredicate, + 34, + 161, + 41, + 0, // Skip to: 23244 + /* 12587 */ MCD_OPC_Decode, + 223, + 23, + 176, + 2, // Opcode: WFK + /* 12592 */ MCD_OPC_FilterValue, + 203, + 1, + 74, + 0, + 0, // Skip to: 12672 + /* 12598 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 12601 */ MCD_OPC_FilterValue, + 0, + 142, + 41, + 0, // Skip to: 23244 + /* 12606 */ MCD_OPC_ExtractField, + 20, + 12, // Inst{31-20} ... + /* 12609 */ MCD_OPC_FilterValue, + 0, + 134, + 41, + 0, // Skip to: 23244 + /* 12614 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 12617 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12632 + /* 12622 */ MCD_OPC_CheckPredicate, + 35, + 35, + 0, + 0, // Skip to: 12662 + /* 12627 */ MCD_OPC_Decode, + 215, + 23, + 174, + 2, // Opcode: WFCSB + /* 12632 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12647 + /* 12637 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 12662 + /* 12642 */ MCD_OPC_Decode, + 196, + 23, + 175, + 2, // Opcode: WFCDB + /* 12647 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 12662 + /* 12652 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 12662 + /* 12657 */ MCD_OPC_Decode, + 216, + 23, + 144, + 2, // Opcode: WFCXB + /* 12662 */ MCD_OPC_CheckPredicate, + 34, + 81, + 41, + 0, // Skip to: 23244 + /* 12667 */ MCD_OPC_Decode, + 195, + 23, + 176, + 2, // Opcode: WFC + /* 12672 */ MCD_OPC_FilterValue, + 204, + 1, + 92, + 1, + 0, // Skip to: 13026 + /* 12678 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 12681 */ MCD_OPC_FilterValue, + 0, + 62, + 41, + 0, // Skip to: 23244 + /* 12686 */ MCD_OPC_ExtractField, + 24, + 8, // Inst{31-24} ... + /* 12689 */ MCD_OPC_FilterValue, + 0, + 54, + 41, + 0, // Skip to: 23244 + /* 12694 */ MCD_OPC_ExtractField, + 12, + 12, // Inst{23-12} ... + /* 12697 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12712 + /* 12702 */ MCD_OPC_CheckPredicate, + 35, + 228, + 0, + 0, // Skip to: 12935 + /* 12707 */ MCD_OPC_Decode, + 173, + 20, + 144, + 2, // Opcode: VFLCSB + /* 12712 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12727 + /* 12717 */ MCD_OPC_CheckPredicate, + 34, + 213, + 0, + 0, // Skip to: 12935 + /* 12722 */ MCD_OPC_Decode, + 172, + 20, + 144, + 2, // Opcode: VFLCDB + /* 12727 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 12743 + /* 12733 */ MCD_OPC_CheckPredicate, + 35, + 197, + 0, + 0, // Skip to: 12935 + /* 12738 */ MCD_OPC_Decode, + 246, + 23, + 174, + 2, // Opcode: WFLCSB + /* 12743 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 12759 + /* 12749 */ MCD_OPC_CheckPredicate, + 34, + 181, + 0, + 0, // Skip to: 12935 + /* 12754 */ MCD_OPC_Decode, + 245, + 23, + 175, + 2, // Opcode: WFLCDB + /* 12759 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 12775 + /* 12765 */ MCD_OPC_CheckPredicate, + 35, + 165, + 0, + 0, // Skip to: 12935 + /* 12770 */ MCD_OPC_Decode, + 247, + 23, + 144, + 2, // Opcode: WFLCXB + /* 12775 */ MCD_OPC_FilterValue, + 130, + 2, + 10, + 0, + 0, // Skip to: 12791 + /* 12781 */ MCD_OPC_CheckPredicate, + 35, + 149, + 0, + 0, // Skip to: 12935 + /* 12786 */ MCD_OPC_Decode, + 177, + 20, + 144, + 2, // Opcode: VFLNSB + /* 12791 */ MCD_OPC_FilterValue, + 131, + 2, + 10, + 0, + 0, // Skip to: 12807 + /* 12797 */ MCD_OPC_CheckPredicate, + 34, + 133, + 0, + 0, // Skip to: 12935 + /* 12802 */ MCD_OPC_Decode, + 176, + 20, + 144, + 2, // Opcode: VFLNDB + /* 12807 */ MCD_OPC_FilterValue, + 130, + 3, + 10, + 0, + 0, // Skip to: 12823 + /* 12813 */ MCD_OPC_CheckPredicate, + 35, + 117, + 0, + 0, // Skip to: 12935 + /* 12818 */ MCD_OPC_Decode, + 251, + 23, + 174, + 2, // Opcode: WFLNSB + /* 12823 */ MCD_OPC_FilterValue, + 131, + 3, + 10, + 0, + 0, // Skip to: 12839 + /* 12829 */ MCD_OPC_CheckPredicate, + 34, + 101, + 0, + 0, // Skip to: 12935 + /* 12834 */ MCD_OPC_Decode, + 250, + 23, + 175, + 2, // Opcode: WFLNDB + /* 12839 */ MCD_OPC_FilterValue, + 132, + 3, + 10, + 0, + 0, // Skip to: 12855 + /* 12845 */ MCD_OPC_CheckPredicate, + 35, + 85, + 0, + 0, // Skip to: 12935 + /* 12850 */ MCD_OPC_Decode, + 252, + 23, + 144, + 2, // Opcode: WFLNXB + /* 12855 */ MCD_OPC_FilterValue, + 130, + 4, + 10, + 0, + 0, // Skip to: 12871 + /* 12861 */ MCD_OPC_CheckPredicate, + 35, + 69, + 0, + 0, // Skip to: 12935 + /* 12866 */ MCD_OPC_Decode, + 179, + 20, + 144, + 2, // Opcode: VFLPSB + /* 12871 */ MCD_OPC_FilterValue, + 131, + 4, + 10, + 0, + 0, // Skip to: 12887 + /* 12877 */ MCD_OPC_CheckPredicate, + 34, + 53, + 0, + 0, // Skip to: 12935 + /* 12882 */ MCD_OPC_Decode, + 178, + 20, + 144, + 2, // Opcode: VFLPDB + /* 12887 */ MCD_OPC_FilterValue, + 130, + 5, + 10, + 0, + 0, // Skip to: 12903 + /* 12893 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 12935 + /* 12898 */ MCD_OPC_Decode, + 254, + 23, + 174, + 2, // Opcode: WFLPSB + /* 12903 */ MCD_OPC_FilterValue, + 131, + 5, + 10, + 0, + 0, // Skip to: 12919 + /* 12909 */ MCD_OPC_CheckPredicate, + 34, + 21, + 0, + 0, // Skip to: 12935 + /* 12914 */ MCD_OPC_Decode, + 253, + 23, + 175, + 2, // Opcode: WFLPDB + /* 12919 */ MCD_OPC_FilterValue, + 132, + 5, + 10, + 0, + 0, // Skip to: 12935 + /* 12925 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 12935 + /* 12930 */ MCD_OPC_Decode, + 255, + 23, + 144, + 2, // Opcode: WFLPXB + /* 12935 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 12938 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 12953 + /* 12943 */ MCD_OPC_CheckPredicate, + 35, + 68, + 0, + 0, // Skip to: 13016 + /* 12948 */ MCD_OPC_Decode, + 205, + 20, + 226, + 1, // Opcode: VFPSOSB + /* 12953 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 12968 + /* 12958 */ MCD_OPC_CheckPredicate, + 34, + 53, + 0, + 0, // Skip to: 13016 + /* 12963 */ MCD_OPC_Decode, + 204, + 20, + 226, + 1, // Opcode: VFPSODB + /* 12968 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 12984 + /* 12974 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 13016 + /* 12979 */ MCD_OPC_Decode, + 152, + 24, + 177, + 2, // Opcode: WFPSOSB + /* 12984 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 13000 + /* 12990 */ MCD_OPC_CheckPredicate, + 34, + 21, + 0, + 0, // Skip to: 13016 + /* 12995 */ MCD_OPC_Decode, + 151, + 24, + 178, + 2, // Opcode: WFPSODB + /* 13000 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 13016 + /* 13006 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 13016 + /* 13011 */ MCD_OPC_Decode, + 153, + 24, + 226, + 1, // Opcode: WFPSOXB + /* 13016 */ MCD_OPC_CheckPredicate, + 34, + 239, + 39, + 0, // Skip to: 23244 + /* 13021 */ MCD_OPC_Decode, + 203, + 20, + 168, + 2, // Opcode: VFPSO + /* 13026 */ MCD_OPC_FilterValue, + 206, + 1, + 107, + 0, + 0, // Skip to: 13139 + /* 13032 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 13035 */ MCD_OPC_FilterValue, + 0, + 220, + 39, + 0, // Skip to: 23244 + /* 13040 */ MCD_OPC_ExtractField, + 20, + 12, // Inst{31-20} ... + /* 13043 */ MCD_OPC_FilterValue, + 0, + 212, + 39, + 0, // Skip to: 23244 + /* 13048 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 13051 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13066 + /* 13056 */ MCD_OPC_CheckPredicate, + 35, + 68, + 0, + 0, // Skip to: 13129 + /* 13061 */ MCD_OPC_Decode, + 210, + 20, + 144, + 2, // Opcode: VFSQSB + /* 13066 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 13081 + /* 13071 */ MCD_OPC_CheckPredicate, + 34, + 53, + 0, + 0, // Skip to: 13129 + /* 13076 */ MCD_OPC_Decode, + 209, + 20, + 144, + 2, // Opcode: VFSQDB + /* 13081 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 13097 + /* 13087 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 13129 + /* 13092 */ MCD_OPC_Decode, + 156, + 24, + 174, + 2, // Opcode: WFSQSB + /* 13097 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 13113 + /* 13103 */ MCD_OPC_CheckPredicate, + 34, + 21, + 0, + 0, // Skip to: 13129 + /* 13108 */ MCD_OPC_Decode, + 155, + 24, + 175, + 2, // Opcode: WFSQDB + /* 13113 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 13129 + /* 13119 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 13129 + /* 13124 */ MCD_OPC_Decode, + 157, + 24, + 144, + 2, // Opcode: WFSQXB + /* 13129 */ MCD_OPC_CheckPredicate, + 34, + 126, + 39, + 0, // Skip to: 23244 + /* 13134 */ MCD_OPC_Decode, + 208, + 20, + 229, + 1, // Opcode: VFSQ + /* 13139 */ MCD_OPC_FilterValue, + 212, + 1, + 74, + 0, + 0, // Skip to: 13219 + /* 13145 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 13148 */ MCD_OPC_FilterValue, + 0, + 107, + 39, + 0, // Skip to: 23244 + /* 13153 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 13156 */ MCD_OPC_FilterValue, + 0, + 99, + 39, + 0, // Skip to: 23244 + /* 13161 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 13164 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13179 + /* 13169 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 13209 + /* 13174 */ MCD_OPC_Decode, + 179, + 23, + 144, + 2, // Opcode: VUPLLB + /* 13179 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13194 + /* 13184 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 13209 + /* 13189 */ MCD_OPC_Decode, + 181, + 23, + 144, + 2, // Opcode: VUPLLH + /* 13194 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13209 + /* 13199 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 13209 + /* 13204 */ MCD_OPC_Decode, + 180, + 23, + 144, + 2, // Opcode: VUPLLF + /* 13209 */ MCD_OPC_CheckPredicate, + 34, + 46, + 39, + 0, // Skip to: 23244 + /* 13214 */ MCD_OPC_Decode, + 178, + 23, + 145, + 2, // Opcode: VUPLL + /* 13219 */ MCD_OPC_FilterValue, + 213, + 1, + 74, + 0, + 0, // Skip to: 13299 + /* 13225 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 13228 */ MCD_OPC_FilterValue, + 0, + 27, + 39, + 0, // Skip to: 23244 + /* 13233 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 13236 */ MCD_OPC_FilterValue, + 0, + 19, + 39, + 0, // Skip to: 23244 + /* 13241 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 13244 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13259 + /* 13249 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 13289 + /* 13254 */ MCD_OPC_Decode, + 174, + 23, + 144, + 2, // Opcode: VUPLHB + /* 13259 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13274 + /* 13264 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 13289 + /* 13269 */ MCD_OPC_Decode, + 176, + 23, + 144, + 2, // Opcode: VUPLHH + /* 13274 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13289 + /* 13279 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 13289 + /* 13284 */ MCD_OPC_Decode, + 175, + 23, + 144, + 2, // Opcode: VUPLHF + /* 13289 */ MCD_OPC_CheckPredicate, + 34, + 222, + 38, + 0, // Skip to: 23244 + /* 13294 */ MCD_OPC_Decode, + 173, + 23, + 145, + 2, // Opcode: VUPLH + /* 13299 */ MCD_OPC_FilterValue, + 214, + 1, + 74, + 0, + 0, // Skip to: 13379 + /* 13305 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 13308 */ MCD_OPC_FilterValue, + 0, + 203, + 38, + 0, // Skip to: 23244 + /* 13313 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 13316 */ MCD_OPC_FilterValue, + 0, + 195, + 38, + 0, // Skip to: 23244 + /* 13321 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 13324 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13339 + /* 13329 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 13369 + /* 13334 */ MCD_OPC_Decode, + 171, + 23, + 144, + 2, // Opcode: VUPLB + /* 13339 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13354 + /* 13344 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 13369 + /* 13349 */ MCD_OPC_Decode, + 177, + 23, + 144, + 2, // Opcode: VUPLHW + /* 13354 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13369 + /* 13359 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 13369 + /* 13364 */ MCD_OPC_Decode, + 172, + 23, + 144, + 2, // Opcode: VUPLF + /* 13369 */ MCD_OPC_CheckPredicate, + 34, + 142, + 38, + 0, // Skip to: 23244 + /* 13374 */ MCD_OPC_Decode, + 170, + 23, + 145, + 2, // Opcode: VUPL + /* 13379 */ MCD_OPC_FilterValue, + 215, + 1, + 74, + 0, + 0, // Skip to: 13459 + /* 13385 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 13388 */ MCD_OPC_FilterValue, + 0, + 123, + 38, + 0, // Skip to: 23244 + /* 13393 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 13396 */ MCD_OPC_FilterValue, + 0, + 115, + 38, + 0, // Skip to: 23244 + /* 13401 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 13404 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13419 + /* 13409 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 13449 + /* 13414 */ MCD_OPC_Decode, + 164, + 23, + 144, + 2, // Opcode: VUPHB + /* 13419 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13434 + /* 13424 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 13449 + /* 13429 */ MCD_OPC_Decode, + 166, + 23, + 144, + 2, // Opcode: VUPHH + /* 13434 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13449 + /* 13439 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 13449 + /* 13444 */ MCD_OPC_Decode, + 165, + 23, + 144, + 2, // Opcode: VUPHF + /* 13449 */ MCD_OPC_CheckPredicate, + 34, + 62, + 38, + 0, // Skip to: 23244 + /* 13454 */ MCD_OPC_Decode, + 163, + 23, + 145, + 2, // Opcode: VUPH + /* 13459 */ MCD_OPC_FilterValue, + 216, + 1, + 24, + 0, + 0, // Skip to: 13489 + /* 13465 */ MCD_OPC_CheckPredicate, + 34, + 46, + 38, + 0, // Skip to: 23244 + /* 13470 */ MCD_OPC_CheckField, + 12, + 20, + 0, + 39, + 38, + 0, // Skip to: 23244 + /* 13477 */ MCD_OPC_CheckField, + 8, + 2, + 0, + 32, + 38, + 0, // Skip to: 23244 + /* 13484 */ MCD_OPC_Decode, + 161, + 23, + 144, + 2, // Opcode: VTM + /* 13489 */ MCD_OPC_FilterValue, + 217, + 1, + 89, + 0, + 0, // Skip to: 13584 + /* 13495 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 13498 */ MCD_OPC_FilterValue, + 0, + 13, + 38, + 0, // Skip to: 23244 + /* 13503 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 13506 */ MCD_OPC_FilterValue, + 0, + 5, + 38, + 0, // Skip to: 23244 + /* 13511 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 13514 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13529 + /* 13519 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 13574 + /* 13524 */ MCD_OPC_Decode, + 176, + 19, + 144, + 2, // Opcode: VECLB + /* 13529 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13544 + /* 13534 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 13574 + /* 13539 */ MCD_OPC_Decode, + 179, + 19, + 144, + 2, // Opcode: VECLH + /* 13544 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13559 + /* 13549 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 13574 + /* 13554 */ MCD_OPC_Decode, + 177, + 19, + 144, + 2, // Opcode: VECLF + /* 13559 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 13574 + /* 13564 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 13574 + /* 13569 */ MCD_OPC_Decode, + 178, + 19, + 144, + 2, // Opcode: VECLG + /* 13574 */ MCD_OPC_CheckPredicate, + 34, + 193, + 37, + 0, // Skip to: 23244 + /* 13579 */ MCD_OPC_Decode, + 175, + 19, + 145, + 2, // Opcode: VECL + /* 13584 */ MCD_OPC_FilterValue, + 219, + 1, + 89, + 0, + 0, // Skip to: 13679 + /* 13590 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 13593 */ MCD_OPC_FilterValue, + 0, + 174, + 37, + 0, // Skip to: 23244 + /* 13598 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 13601 */ MCD_OPC_FilterValue, + 0, + 166, + 37, + 0, // Skip to: 23244 + /* 13606 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 13609 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13624 + /* 13614 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 13669 + /* 13619 */ MCD_OPC_Decode, + 171, + 19, + 144, + 2, // Opcode: VECB + /* 13624 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13639 + /* 13629 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 13669 + /* 13634 */ MCD_OPC_Decode, + 174, + 19, + 144, + 2, // Opcode: VECH + /* 13639 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13654 + /* 13644 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 13669 + /* 13649 */ MCD_OPC_Decode, + 172, + 19, + 144, + 2, // Opcode: VECF + /* 13654 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 13669 + /* 13659 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 13669 + /* 13664 */ MCD_OPC_Decode, + 173, + 19, + 144, + 2, // Opcode: VECG + /* 13669 */ MCD_OPC_CheckPredicate, + 34, + 98, + 37, + 0, // Skip to: 23244 + /* 13674 */ MCD_OPC_Decode, + 170, + 19, + 145, + 2, // Opcode: VEC + /* 13679 */ MCD_OPC_FilterValue, + 222, + 1, + 89, + 0, + 0, // Skip to: 13774 + /* 13685 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 13688 */ MCD_OPC_FilterValue, + 0, + 79, + 37, + 0, // Skip to: 23244 + /* 13693 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 13696 */ MCD_OPC_FilterValue, + 0, + 71, + 37, + 0, // Skip to: 23244 + /* 13701 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 13704 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13719 + /* 13709 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 13764 + /* 13714 */ MCD_OPC_Decode, + 253, + 20, + 144, + 2, // Opcode: VLCB + /* 13719 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13734 + /* 13724 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 13764 + /* 13729 */ MCD_OPC_Decode, + 128, + 21, + 144, + 2, // Opcode: VLCH + /* 13734 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13749 + /* 13739 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 13764 + /* 13744 */ MCD_OPC_Decode, + 254, + 20, + 144, + 2, // Opcode: VLCF + /* 13749 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 13764 + /* 13754 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 13764 + /* 13759 */ MCD_OPC_Decode, + 255, + 20, + 144, + 2, // Opcode: VLCG + /* 13764 */ MCD_OPC_CheckPredicate, + 34, + 3, + 37, + 0, // Skip to: 23244 + /* 13769 */ MCD_OPC_Decode, + 252, + 20, + 145, + 2, // Opcode: VLC + /* 13774 */ MCD_OPC_FilterValue, + 223, + 1, + 89, + 0, + 0, // Skip to: 13869 + /* 13780 */ MCD_OPC_ExtractField, + 8, + 2, // Inst{9-8} ... + /* 13783 */ MCD_OPC_FilterValue, + 0, + 240, + 36, + 0, // Skip to: 23244 + /* 13788 */ MCD_OPC_ExtractField, + 16, + 16, // Inst{31-16} ... + /* 13791 */ MCD_OPC_FilterValue, + 0, + 232, + 36, + 0, // Skip to: 23244 + /* 13796 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 13799 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 13814 + /* 13804 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 13859 + /* 13809 */ MCD_OPC_Decode, + 169, + 21, + 144, + 2, // Opcode: VLPB + /* 13814 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 13829 + /* 13819 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 13859 + /* 13824 */ MCD_OPC_Decode, + 172, + 21, + 144, + 2, // Opcode: VLPH + /* 13829 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13844 + /* 13834 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 13859 + /* 13839 */ MCD_OPC_Decode, + 170, + 21, + 144, + 2, // Opcode: VLPF + /* 13844 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 13859 + /* 13849 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 13859 + /* 13854 */ MCD_OPC_Decode, + 171, + 21, + 144, + 2, // Opcode: VLPG + /* 13859 */ MCD_OPC_CheckPredicate, + 34, + 164, + 36, + 0, // Skip to: 23244 + /* 13864 */ MCD_OPC_Decode, + 168, + 21, + 145, + 2, // Opcode: VLP + /* 13869 */ MCD_OPC_FilterValue, + 226, + 1, + 107, + 0, + 0, // Skip to: 13982 + /* 13875 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 13878 */ MCD_OPC_FilterValue, + 0, + 145, + 36, + 0, // Skip to: 23244 + /* 13883 */ MCD_OPC_ExtractField, + 20, + 8, // Inst{27-20} ... + /* 13886 */ MCD_OPC_FilterValue, + 0, + 137, + 36, + 0, // Skip to: 23244 + /* 13891 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 13894 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 13909 + /* 13899 */ MCD_OPC_CheckPredicate, + 35, + 68, + 0, + 0, // Skip to: 13972 + /* 13904 */ MCD_OPC_Decode, + 211, + 20, + 239, + 1, // Opcode: VFSSB + /* 13909 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 13924 + /* 13914 */ MCD_OPC_CheckPredicate, + 34, + 53, + 0, + 0, // Skip to: 13972 + /* 13919 */ MCD_OPC_Decode, + 207, + 20, + 239, + 1, // Opcode: VFSDB + /* 13924 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 13940 + /* 13930 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 13972 + /* 13935 */ MCD_OPC_Decode, + 158, + 24, + 179, + 2, // Opcode: WFSSB + /* 13940 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 13956 + /* 13946 */ MCD_OPC_CheckPredicate, + 34, + 21, + 0, + 0, // Skip to: 13972 + /* 13951 */ MCD_OPC_Decode, + 154, + 24, + 180, + 2, // Opcode: WFSDB + /* 13956 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 13972 + /* 13962 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 13972 + /* 13967 */ MCD_OPC_Decode, + 159, + 24, + 239, + 1, // Opcode: WFSXB + /* 13972 */ MCD_OPC_CheckPredicate, + 34, + 51, + 36, + 0, // Skip to: 23244 + /* 13977 */ MCD_OPC_Decode, + 206, + 20, + 237, + 1, // Opcode: VFS + /* 13982 */ MCD_OPC_FilterValue, + 227, + 1, + 107, + 0, + 0, // Skip to: 14095 + /* 13988 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 13991 */ MCD_OPC_FilterValue, + 0, + 32, + 36, + 0, // Skip to: 23244 + /* 13996 */ MCD_OPC_ExtractField, + 20, + 8, // Inst{27-20} ... + /* 13999 */ MCD_OPC_FilterValue, + 0, + 24, + 36, + 0, // Skip to: 23244 + /* 14004 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 14007 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 14022 + /* 14012 */ MCD_OPC_CheckPredicate, + 35, + 68, + 0, + 0, // Skip to: 14085 + /* 14017 */ MCD_OPC_Decode, + 240, + 19, + 239, + 1, // Opcode: VFASB + /* 14022 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 14037 + /* 14027 */ MCD_OPC_CheckPredicate, + 34, + 53, + 0, + 0, // Skip to: 14085 + /* 14032 */ MCD_OPC_Decode, + 226, + 19, + 239, + 1, // Opcode: VFADB + /* 14037 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 14053 + /* 14043 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 14085 + /* 14048 */ MCD_OPC_Decode, + 193, + 23, + 179, + 2, // Opcode: WFASB + /* 14053 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 14069 + /* 14059 */ MCD_OPC_CheckPredicate, + 34, + 21, + 0, + 0, // Skip to: 14085 + /* 14064 */ MCD_OPC_Decode, + 192, + 23, + 180, + 2, // Opcode: WFADB + /* 14069 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 14085 + /* 14075 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 14085 + /* 14080 */ MCD_OPC_Decode, + 194, + 23, + 239, + 1, // Opcode: WFAXB + /* 14085 */ MCD_OPC_CheckPredicate, + 34, + 194, + 35, + 0, // Skip to: 23244 + /* 14090 */ MCD_OPC_Decode, + 225, + 19, + 237, + 1, // Opcode: VFA + /* 14095 */ MCD_OPC_FilterValue, + 229, + 1, + 107, + 0, + 0, // Skip to: 14208 + /* 14101 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 14104 */ MCD_OPC_FilterValue, + 0, + 175, + 35, + 0, // Skip to: 23244 + /* 14109 */ MCD_OPC_ExtractField, + 20, + 8, // Inst{27-20} ... + /* 14112 */ MCD_OPC_FilterValue, + 0, + 167, + 35, + 0, // Skip to: 23244 + /* 14117 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 14120 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 14135 + /* 14125 */ MCD_OPC_CheckPredicate, + 35, + 68, + 0, + 0, // Skip to: 14198 + /* 14130 */ MCD_OPC_Decode, + 130, + 20, + 239, + 1, // Opcode: VFDSB + /* 14135 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 14150 + /* 14140 */ MCD_OPC_CheckPredicate, + 34, + 53, + 0, + 0, // Skip to: 14198 + /* 14145 */ MCD_OPC_Decode, + 129, + 20, + 239, + 1, // Opcode: VFDDB + /* 14150 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 14166 + /* 14156 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 14198 + /* 14161 */ MCD_OPC_Decode, + 218, + 23, + 179, + 2, // Opcode: WFDSB + /* 14166 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 14182 + /* 14172 */ MCD_OPC_CheckPredicate, + 34, + 21, + 0, + 0, // Skip to: 14198 + /* 14177 */ MCD_OPC_Decode, + 217, + 23, + 180, + 2, // Opcode: WFDDB + /* 14182 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 14198 + /* 14188 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 14198 + /* 14193 */ MCD_OPC_Decode, + 219, + 23, + 239, + 1, // Opcode: WFDXB + /* 14198 */ MCD_OPC_CheckPredicate, + 34, + 81, + 35, + 0, // Skip to: 23244 + /* 14203 */ MCD_OPC_Decode, + 128, + 20, + 237, + 1, // Opcode: VFD + /* 14208 */ MCD_OPC_FilterValue, + 231, + 1, + 107, + 0, + 0, // Skip to: 14321 + /* 14214 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 14217 */ MCD_OPC_FilterValue, + 0, + 62, + 35, + 0, // Skip to: 23244 + /* 14222 */ MCD_OPC_ExtractField, + 20, + 8, // Inst{27-20} ... + /* 14225 */ MCD_OPC_FilterValue, + 0, + 54, + 35, + 0, // Skip to: 23244 + /* 14230 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 14233 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 14248 + /* 14238 */ MCD_OPC_CheckPredicate, + 35, + 68, + 0, + 0, // Skip to: 14311 + /* 14243 */ MCD_OPC_Decode, + 194, + 20, + 239, + 1, // Opcode: VFMSB + /* 14248 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 14263 + /* 14253 */ MCD_OPC_CheckPredicate, + 34, + 53, + 0, + 0, // Skip to: 14311 + /* 14258 */ MCD_OPC_Decode, + 189, + 20, + 239, + 1, // Opcode: VFMDB + /* 14263 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 14279 + /* 14269 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 14311 + /* 14274 */ MCD_OPC_Decode, + 140, + 24, + 179, + 2, // Opcode: WFMSB + /* 14279 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 14295 + /* 14285 */ MCD_OPC_CheckPredicate, + 34, + 21, + 0, + 0, // Skip to: 14311 + /* 14290 */ MCD_OPC_Decode, + 136, + 24, + 180, + 2, // Opcode: WFMDB + /* 14295 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 14311 + /* 14301 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 14311 + /* 14306 */ MCD_OPC_Decode, + 144, + 24, + 239, + 1, // Opcode: WFMXB + /* 14311 */ MCD_OPC_CheckPredicate, + 34, + 224, + 34, + 0, // Skip to: 23244 + /* 14316 */ MCD_OPC_Decode, + 182, + 20, + 237, + 1, // Opcode: VFM + /* 14321 */ MCD_OPC_FilterValue, + 232, + 1, + 89, + 1, + 0, // Skip to: 14672 + /* 14327 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 14330 */ MCD_OPC_FilterValue, + 0, + 205, + 34, + 0, // Skip to: 23244 + /* 14335 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 14338 */ MCD_OPC_FilterValue, + 0, + 197, + 34, + 0, // Skip to: 23244 + /* 14343 */ MCD_OPC_ExtractField, + 12, + 12, // Inst{23-12} ... + /* 14346 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 14361 + /* 14351 */ MCD_OPC_CheckPredicate, + 35, + 50, + 1, + 0, // Skip to: 14662 + /* 14356 */ MCD_OPC_Decode, + 244, + 19, + 239, + 1, // Opcode: VFCESB + /* 14361 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 14376 + /* 14366 */ MCD_OPC_CheckPredicate, + 34, + 35, + 1, + 0, // Skip to: 14662 + /* 14371 */ MCD_OPC_Decode, + 242, + 19, + 239, + 1, // Opcode: VFCEDB + /* 14376 */ MCD_OPC_FilterValue, + 66, + 10, + 0, + 0, // Skip to: 14391 + /* 14381 */ MCD_OPC_CheckPredicate, + 35, + 20, + 1, + 0, // Skip to: 14662 + /* 14386 */ MCD_OPC_Decode, + 162, + 20, + 239, + 1, // Opcode: VFKESB + /* 14391 */ MCD_OPC_FilterValue, + 67, + 10, + 0, + 0, // Skip to: 14406 + /* 14396 */ MCD_OPC_CheckPredicate, + 35, + 5, + 1, + 0, // Skip to: 14662 + /* 14401 */ MCD_OPC_Decode, + 160, + 20, + 239, + 1, // Opcode: VFKEDB + /* 14406 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 14422 + /* 14412 */ MCD_OPC_CheckPredicate, + 35, + 245, + 0, + 0, // Skip to: 14662 + /* 14417 */ MCD_OPC_Decode, + 199, + 23, + 179, + 2, // Opcode: WFCESB + /* 14422 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 14438 + /* 14428 */ MCD_OPC_CheckPredicate, + 34, + 229, + 0, + 0, // Skip to: 14662 + /* 14433 */ MCD_OPC_Decode, + 197, + 23, + 180, + 2, // Opcode: WFCEDB + /* 14438 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 14454 + /* 14444 */ MCD_OPC_CheckPredicate, + 35, + 213, + 0, + 0, // Skip to: 14662 + /* 14449 */ MCD_OPC_Decode, + 201, + 23, + 239, + 1, // Opcode: WFCEXB + /* 14454 */ MCD_OPC_FilterValue, + 194, + 1, + 10, + 0, + 0, // Skip to: 14470 + /* 14460 */ MCD_OPC_CheckPredicate, + 35, + 197, + 0, + 0, // Skip to: 14662 + /* 14465 */ MCD_OPC_Decode, + 227, + 23, + 179, + 2, // Opcode: WFKESB + /* 14470 */ MCD_OPC_FilterValue, + 195, + 1, + 10, + 0, + 0, // Skip to: 14486 + /* 14476 */ MCD_OPC_CheckPredicate, + 35, + 181, + 0, + 0, // Skip to: 14662 + /* 14481 */ MCD_OPC_Decode, + 225, + 23, + 180, + 2, // Opcode: WFKEDB + /* 14486 */ MCD_OPC_FilterValue, + 196, + 1, + 10, + 0, + 0, // Skip to: 14502 + /* 14492 */ MCD_OPC_CheckPredicate, + 35, + 165, + 0, + 0, // Skip to: 14662 + /* 14497 */ MCD_OPC_Decode, + 229, + 23, + 239, + 1, // Opcode: WFKEXB + /* 14502 */ MCD_OPC_FilterValue, + 130, + 2, + 10, + 0, + 0, // Skip to: 14518 + /* 14508 */ MCD_OPC_CheckPredicate, + 35, + 149, + 0, + 0, // Skip to: 14662 + /* 14513 */ MCD_OPC_Decode, + 245, + 19, + 239, + 1, // Opcode: VFCESBS + /* 14518 */ MCD_OPC_FilterValue, + 131, + 2, + 10, + 0, + 0, // Skip to: 14534 + /* 14524 */ MCD_OPC_CheckPredicate, + 34, + 133, + 0, + 0, // Skip to: 14662 + /* 14529 */ MCD_OPC_Decode, + 243, + 19, + 239, + 1, // Opcode: VFCEDBS + /* 14534 */ MCD_OPC_FilterValue, + 194, + 2, + 10, + 0, + 0, // Skip to: 14550 + /* 14540 */ MCD_OPC_CheckPredicate, + 35, + 117, + 0, + 0, // Skip to: 14662 + /* 14545 */ MCD_OPC_Decode, + 163, + 20, + 239, + 1, // Opcode: VFKESBS + /* 14550 */ MCD_OPC_FilterValue, + 195, + 2, + 10, + 0, + 0, // Skip to: 14566 + /* 14556 */ MCD_OPC_CheckPredicate, + 35, + 101, + 0, + 0, // Skip to: 14662 + /* 14561 */ MCD_OPC_Decode, + 161, + 20, + 239, + 1, // Opcode: VFKEDBS + /* 14566 */ MCD_OPC_FilterValue, + 130, + 3, + 10, + 0, + 0, // Skip to: 14582 + /* 14572 */ MCD_OPC_CheckPredicate, + 35, + 85, + 0, + 0, // Skip to: 14662 + /* 14577 */ MCD_OPC_Decode, + 200, + 23, + 179, + 2, // Opcode: WFCESBS + /* 14582 */ MCD_OPC_FilterValue, + 131, + 3, + 10, + 0, + 0, // Skip to: 14598 + /* 14588 */ MCD_OPC_CheckPredicate, + 34, + 69, + 0, + 0, // Skip to: 14662 + /* 14593 */ MCD_OPC_Decode, + 198, + 23, + 180, + 2, // Opcode: WFCEDBS + /* 14598 */ MCD_OPC_FilterValue, + 132, + 3, + 10, + 0, + 0, // Skip to: 14614 + /* 14604 */ MCD_OPC_CheckPredicate, + 35, + 53, + 0, + 0, // Skip to: 14662 + /* 14609 */ MCD_OPC_Decode, + 202, + 23, + 239, + 1, // Opcode: WFCEXBS + /* 14614 */ MCD_OPC_FilterValue, + 194, + 3, + 10, + 0, + 0, // Skip to: 14630 + /* 14620 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 14662 + /* 14625 */ MCD_OPC_Decode, + 228, + 23, + 179, + 2, // Opcode: WFKESBS + /* 14630 */ MCD_OPC_FilterValue, + 195, + 3, + 10, + 0, + 0, // Skip to: 14646 + /* 14636 */ MCD_OPC_CheckPredicate, + 35, + 21, + 0, + 0, // Skip to: 14662 + /* 14641 */ MCD_OPC_Decode, + 226, + 23, + 180, + 2, // Opcode: WFKEDBS + /* 14646 */ MCD_OPC_FilterValue, + 196, + 3, + 10, + 0, + 0, // Skip to: 14662 + /* 14652 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 14662 + /* 14657 */ MCD_OPC_Decode, + 230, + 23, + 239, + 1, // Opcode: WFKEXBS + /* 14662 */ MCD_OPC_CheckPredicate, + 34, + 129, + 33, + 0, // Skip to: 23244 + /* 14667 */ MCD_OPC_Decode, + 241, + 19, + 181, + 2, // Opcode: VFCE + /* 14672 */ MCD_OPC_FilterValue, + 234, + 1, + 89, + 1, + 0, // Skip to: 15023 + /* 14678 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 14681 */ MCD_OPC_FilterValue, + 0, + 110, + 33, + 0, // Skip to: 23244 + /* 14686 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 14689 */ MCD_OPC_FilterValue, + 0, + 102, + 33, + 0, // Skip to: 23244 + /* 14694 */ MCD_OPC_ExtractField, + 12, + 12, // Inst{23-12} ... + /* 14697 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 14712 + /* 14702 */ MCD_OPC_CheckPredicate, + 35, + 50, + 1, + 0, // Skip to: 15013 + /* 14707 */ MCD_OPC_Decode, + 252, + 19, + 239, + 1, // Opcode: VFCHESB + /* 14712 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 14727 + /* 14717 */ MCD_OPC_CheckPredicate, + 34, + 35, + 1, + 0, // Skip to: 15013 + /* 14722 */ MCD_OPC_Decode, + 250, + 19, + 239, + 1, // Opcode: VFCHEDB + /* 14727 */ MCD_OPC_FilterValue, + 66, + 10, + 0, + 0, // Skip to: 14742 + /* 14732 */ MCD_OPC_CheckPredicate, + 35, + 20, + 1, + 0, // Skip to: 15013 + /* 14737 */ MCD_OPC_Decode, + 168, + 20, + 239, + 1, // Opcode: VFKHESB + /* 14742 */ MCD_OPC_FilterValue, + 67, + 10, + 0, + 0, // Skip to: 14757 + /* 14747 */ MCD_OPC_CheckPredicate, + 35, + 5, + 1, + 0, // Skip to: 15013 + /* 14752 */ MCD_OPC_Decode, + 166, + 20, + 239, + 1, // Opcode: VFKHEDB + /* 14757 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 14773 + /* 14763 */ MCD_OPC_CheckPredicate, + 35, + 245, + 0, + 0, // Skip to: 15013 + /* 14768 */ MCD_OPC_Decode, + 207, + 23, + 179, + 2, // Opcode: WFCHESB + /* 14773 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 14789 + /* 14779 */ MCD_OPC_CheckPredicate, + 34, + 229, + 0, + 0, // Skip to: 15013 + /* 14784 */ MCD_OPC_Decode, + 205, + 23, + 180, + 2, // Opcode: WFCHEDB + /* 14789 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 14805 + /* 14795 */ MCD_OPC_CheckPredicate, + 35, + 213, + 0, + 0, // Skip to: 15013 + /* 14800 */ MCD_OPC_Decode, + 209, + 23, + 239, + 1, // Opcode: WFCHEXB + /* 14805 */ MCD_OPC_FilterValue, + 194, + 1, + 10, + 0, + 0, // Skip to: 14821 + /* 14811 */ MCD_OPC_CheckPredicate, + 35, + 197, + 0, + 0, // Skip to: 15013 + /* 14816 */ MCD_OPC_Decode, + 235, + 23, + 179, + 2, // Opcode: WFKHESB + /* 14821 */ MCD_OPC_FilterValue, + 195, + 1, + 10, + 0, + 0, // Skip to: 14837 + /* 14827 */ MCD_OPC_CheckPredicate, + 35, + 181, + 0, + 0, // Skip to: 15013 + /* 14832 */ MCD_OPC_Decode, + 233, + 23, + 180, + 2, // Opcode: WFKHEDB + /* 14837 */ MCD_OPC_FilterValue, + 196, + 1, + 10, + 0, + 0, // Skip to: 14853 + /* 14843 */ MCD_OPC_CheckPredicate, + 35, + 165, + 0, + 0, // Skip to: 15013 + /* 14848 */ MCD_OPC_Decode, + 237, + 23, + 239, + 1, // Opcode: WFKHEXB + /* 14853 */ MCD_OPC_FilterValue, + 130, + 2, + 10, + 0, + 0, // Skip to: 14869 + /* 14859 */ MCD_OPC_CheckPredicate, + 35, + 149, + 0, + 0, // Skip to: 15013 + /* 14864 */ MCD_OPC_Decode, + 253, + 19, + 239, + 1, // Opcode: VFCHESBS + /* 14869 */ MCD_OPC_FilterValue, + 131, + 2, + 10, + 0, + 0, // Skip to: 14885 + /* 14875 */ MCD_OPC_CheckPredicate, + 34, + 133, + 0, + 0, // Skip to: 15013 + /* 14880 */ MCD_OPC_Decode, + 251, + 19, + 239, + 1, // Opcode: VFCHEDBS + /* 14885 */ MCD_OPC_FilterValue, + 194, + 2, + 10, + 0, + 0, // Skip to: 14901 + /* 14891 */ MCD_OPC_CheckPredicate, + 35, + 117, + 0, + 0, // Skip to: 15013 + /* 14896 */ MCD_OPC_Decode, + 169, + 20, + 239, + 1, // Opcode: VFKHESBS + /* 14901 */ MCD_OPC_FilterValue, + 195, + 2, + 10, + 0, + 0, // Skip to: 14917 + /* 14907 */ MCD_OPC_CheckPredicate, + 35, + 101, + 0, + 0, // Skip to: 15013 + /* 14912 */ MCD_OPC_Decode, + 167, + 20, + 239, + 1, // Opcode: VFKHEDBS + /* 14917 */ MCD_OPC_FilterValue, + 130, + 3, + 10, + 0, + 0, // Skip to: 14933 + /* 14923 */ MCD_OPC_CheckPredicate, + 35, + 85, + 0, + 0, // Skip to: 15013 + /* 14928 */ MCD_OPC_Decode, + 208, + 23, + 179, + 2, // Opcode: WFCHESBS + /* 14933 */ MCD_OPC_FilterValue, + 131, + 3, + 10, + 0, + 0, // Skip to: 14949 + /* 14939 */ MCD_OPC_CheckPredicate, + 34, + 69, + 0, + 0, // Skip to: 15013 + /* 14944 */ MCD_OPC_Decode, + 206, + 23, + 180, + 2, // Opcode: WFCHEDBS + /* 14949 */ MCD_OPC_FilterValue, + 132, + 3, + 10, + 0, + 0, // Skip to: 14965 + /* 14955 */ MCD_OPC_CheckPredicate, + 35, + 53, + 0, + 0, // Skip to: 15013 + /* 14960 */ MCD_OPC_Decode, + 210, + 23, + 239, + 1, // Opcode: WFCHEXBS + /* 14965 */ MCD_OPC_FilterValue, + 194, + 3, + 10, + 0, + 0, // Skip to: 14981 + /* 14971 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 15013 + /* 14976 */ MCD_OPC_Decode, + 236, + 23, + 179, + 2, // Opcode: WFKHESBS + /* 14981 */ MCD_OPC_FilterValue, + 195, + 3, + 10, + 0, + 0, // Skip to: 14997 + /* 14987 */ MCD_OPC_CheckPredicate, + 35, + 21, + 0, + 0, // Skip to: 15013 + /* 14992 */ MCD_OPC_Decode, + 234, + 23, + 180, + 2, // Opcode: WFKHEDBS + /* 14997 */ MCD_OPC_FilterValue, + 196, + 3, + 10, + 0, + 0, // Skip to: 15013 + /* 15003 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 15013 + /* 15008 */ MCD_OPC_Decode, + 238, + 23, + 239, + 1, // Opcode: WFKHEXBS + /* 15013 */ MCD_OPC_CheckPredicate, + 34, + 34, + 32, + 0, // Skip to: 23244 + /* 15018 */ MCD_OPC_Decode, + 249, + 19, + 181, + 2, // Opcode: VFCHE + /* 15023 */ MCD_OPC_FilterValue, + 235, + 1, + 89, + 1, + 0, // Skip to: 15374 + /* 15029 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 15032 */ MCD_OPC_FilterValue, + 0, + 15, + 32, + 0, // Skip to: 23244 + /* 15037 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 15040 */ MCD_OPC_FilterValue, + 0, + 7, + 32, + 0, // Skip to: 23244 + /* 15045 */ MCD_OPC_ExtractField, + 12, + 12, // Inst{23-12} ... + /* 15048 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 15063 + /* 15053 */ MCD_OPC_CheckPredicate, + 35, + 50, + 1, + 0, // Skip to: 15364 + /* 15058 */ MCD_OPC_Decode, + 254, + 19, + 239, + 1, // Opcode: VFCHSB + /* 15063 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 15078 + /* 15068 */ MCD_OPC_CheckPredicate, + 34, + 35, + 1, + 0, // Skip to: 15364 + /* 15073 */ MCD_OPC_Decode, + 247, + 19, + 239, + 1, // Opcode: VFCHDB + /* 15078 */ MCD_OPC_FilterValue, + 66, + 10, + 0, + 0, // Skip to: 15093 + /* 15083 */ MCD_OPC_CheckPredicate, + 35, + 20, + 1, + 0, // Skip to: 15364 + /* 15088 */ MCD_OPC_Decode, + 170, + 20, + 239, + 1, // Opcode: VFKHSB + /* 15093 */ MCD_OPC_FilterValue, + 67, + 10, + 0, + 0, // Skip to: 15108 + /* 15098 */ MCD_OPC_CheckPredicate, + 35, + 5, + 1, + 0, // Skip to: 15364 + /* 15103 */ MCD_OPC_Decode, + 164, + 20, + 239, + 1, // Opcode: VFKHDB + /* 15108 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 15124 + /* 15114 */ MCD_OPC_CheckPredicate, + 35, + 245, + 0, + 0, // Skip to: 15364 + /* 15119 */ MCD_OPC_Decode, + 211, + 23, + 179, + 2, // Opcode: WFCHSB + /* 15124 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 15140 + /* 15130 */ MCD_OPC_CheckPredicate, + 34, + 229, + 0, + 0, // Skip to: 15364 + /* 15135 */ MCD_OPC_Decode, + 203, + 23, + 180, + 2, // Opcode: WFCHDB + /* 15140 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 15156 + /* 15146 */ MCD_OPC_CheckPredicate, + 35, + 213, + 0, + 0, // Skip to: 15364 + /* 15151 */ MCD_OPC_Decode, + 213, + 23, + 239, + 1, // Opcode: WFCHXB + /* 15156 */ MCD_OPC_FilterValue, + 194, + 1, + 10, + 0, + 0, // Skip to: 15172 + /* 15162 */ MCD_OPC_CheckPredicate, + 35, + 197, + 0, + 0, // Skip to: 15364 + /* 15167 */ MCD_OPC_Decode, + 239, + 23, + 179, + 2, // Opcode: WFKHSB + /* 15172 */ MCD_OPC_FilterValue, + 195, + 1, + 10, + 0, + 0, // Skip to: 15188 + /* 15178 */ MCD_OPC_CheckPredicate, + 35, + 181, + 0, + 0, // Skip to: 15364 + /* 15183 */ MCD_OPC_Decode, + 231, + 23, + 180, + 2, // Opcode: WFKHDB + /* 15188 */ MCD_OPC_FilterValue, + 196, + 1, + 10, + 0, + 0, // Skip to: 15204 + /* 15194 */ MCD_OPC_CheckPredicate, + 35, + 165, + 0, + 0, // Skip to: 15364 + /* 15199 */ MCD_OPC_Decode, + 241, + 23, + 239, + 1, // Opcode: WFKHXB + /* 15204 */ MCD_OPC_FilterValue, + 130, + 2, + 10, + 0, + 0, // Skip to: 15220 + /* 15210 */ MCD_OPC_CheckPredicate, + 35, + 149, + 0, + 0, // Skip to: 15364 + /* 15215 */ MCD_OPC_Decode, + 255, + 19, + 239, + 1, // Opcode: VFCHSBS + /* 15220 */ MCD_OPC_FilterValue, + 131, + 2, + 10, + 0, + 0, // Skip to: 15236 + /* 15226 */ MCD_OPC_CheckPredicate, + 34, + 133, + 0, + 0, // Skip to: 15364 + /* 15231 */ MCD_OPC_Decode, + 248, + 19, + 239, + 1, // Opcode: VFCHDBS + /* 15236 */ MCD_OPC_FilterValue, + 194, + 2, + 10, + 0, + 0, // Skip to: 15252 + /* 15242 */ MCD_OPC_CheckPredicate, + 35, + 117, + 0, + 0, // Skip to: 15364 + /* 15247 */ MCD_OPC_Decode, + 171, + 20, + 239, + 1, // Opcode: VFKHSBS + /* 15252 */ MCD_OPC_FilterValue, + 195, + 2, + 10, + 0, + 0, // Skip to: 15268 + /* 15258 */ MCD_OPC_CheckPredicate, + 35, + 101, + 0, + 0, // Skip to: 15364 + /* 15263 */ MCD_OPC_Decode, + 165, + 20, + 239, + 1, // Opcode: VFKHDBS + /* 15268 */ MCD_OPC_FilterValue, + 130, + 3, + 10, + 0, + 0, // Skip to: 15284 + /* 15274 */ MCD_OPC_CheckPredicate, + 35, + 85, + 0, + 0, // Skip to: 15364 + /* 15279 */ MCD_OPC_Decode, + 212, + 23, + 179, + 2, // Opcode: WFCHSBS + /* 15284 */ MCD_OPC_FilterValue, + 131, + 3, + 10, + 0, + 0, // Skip to: 15300 + /* 15290 */ MCD_OPC_CheckPredicate, + 34, + 69, + 0, + 0, // Skip to: 15364 + /* 15295 */ MCD_OPC_Decode, + 204, + 23, + 180, + 2, // Opcode: WFCHDBS + /* 15300 */ MCD_OPC_FilterValue, + 132, + 3, + 10, + 0, + 0, // Skip to: 15316 + /* 15306 */ MCD_OPC_CheckPredicate, + 35, + 53, + 0, + 0, // Skip to: 15364 + /* 15311 */ MCD_OPC_Decode, + 214, + 23, + 239, + 1, // Opcode: WFCHXBS + /* 15316 */ MCD_OPC_FilterValue, + 194, + 3, + 10, + 0, + 0, // Skip to: 15332 + /* 15322 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 15364 + /* 15327 */ MCD_OPC_Decode, + 240, + 23, + 179, + 2, // Opcode: WFKHSBS + /* 15332 */ MCD_OPC_FilterValue, + 195, + 3, + 10, + 0, + 0, // Skip to: 15348 + /* 15338 */ MCD_OPC_CheckPredicate, + 35, + 21, + 0, + 0, // Skip to: 15364 + /* 15343 */ MCD_OPC_Decode, + 232, + 23, + 180, + 2, // Opcode: WFKHDBS + /* 15348 */ MCD_OPC_FilterValue, + 196, + 3, + 10, + 0, + 0, // Skip to: 15364 + /* 15354 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 15364 + /* 15359 */ MCD_OPC_Decode, + 242, + 23, + 239, + 1, // Opcode: WFKHXBS + /* 15364 */ MCD_OPC_CheckPredicate, + 34, + 195, + 30, + 0, // Skip to: 23244 + /* 15369 */ MCD_OPC_Decode, + 246, + 19, + 181, + 2, // Opcode: VFCH + /* 15374 */ MCD_OPC_FilterValue, + 238, + 1, + 107, + 0, + 0, // Skip to: 15487 + /* 15380 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 15383 */ MCD_OPC_FilterValue, + 0, + 176, + 30, + 0, // Skip to: 23244 + /* 15388 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 15391 */ MCD_OPC_FilterValue, + 0, + 168, + 30, + 0, // Skip to: 23244 + /* 15396 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 15399 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 15414 + /* 15404 */ MCD_OPC_CheckPredicate, + 35, + 68, + 0, + 0, // Skip to: 15477 + /* 15409 */ MCD_OPC_Decode, + 192, + 20, + 235, + 1, // Opcode: VFMINSB + /* 15414 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 15429 + /* 15419 */ MCD_OPC_CheckPredicate, + 35, + 53, + 0, + 0, // Skip to: 15477 + /* 15424 */ MCD_OPC_Decode, + 191, + 20, + 235, + 1, // Opcode: VFMINDB + /* 15429 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 15445 + /* 15435 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 15477 + /* 15440 */ MCD_OPC_Decode, + 138, + 24, + 182, + 2, // Opcode: WFMINSB + /* 15445 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 15461 + /* 15451 */ MCD_OPC_CheckPredicate, + 35, + 21, + 0, + 0, // Skip to: 15477 + /* 15456 */ MCD_OPC_Decode, + 137, + 24, + 183, + 2, // Opcode: WFMINDB + /* 15461 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 15477 + /* 15467 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 15477 + /* 15472 */ MCD_OPC_Decode, + 139, + 24, + 235, + 1, // Opcode: WFMINXB + /* 15477 */ MCD_OPC_CheckPredicate, + 35, + 82, + 30, + 0, // Skip to: 23244 + /* 15482 */ MCD_OPC_Decode, + 190, + 20, + 181, + 2, // Opcode: VFMIN + /* 15487 */ MCD_OPC_FilterValue, + 239, + 1, + 107, + 0, + 0, // Skip to: 15600 + /* 15493 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 15496 */ MCD_OPC_FilterValue, + 0, + 63, + 30, + 0, // Skip to: 23244 + /* 15501 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 15504 */ MCD_OPC_FilterValue, + 0, + 55, + 30, + 0, // Skip to: 23244 + /* 15509 */ MCD_OPC_ExtractField, + 12, + 8, // Inst{19-12} ... + /* 15512 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 15527 + /* 15517 */ MCD_OPC_CheckPredicate, + 35, + 68, + 0, + 0, // Skip to: 15590 + /* 15522 */ MCD_OPC_Decode, + 188, + 20, + 235, + 1, // Opcode: VFMAXSB + /* 15527 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 15542 + /* 15532 */ MCD_OPC_CheckPredicate, + 35, + 53, + 0, + 0, // Skip to: 15590 + /* 15537 */ MCD_OPC_Decode, + 187, + 20, + 235, + 1, // Opcode: VFMAXDB + /* 15542 */ MCD_OPC_FilterValue, + 130, + 1, + 10, + 0, + 0, // Skip to: 15558 + /* 15548 */ MCD_OPC_CheckPredicate, + 35, + 37, + 0, + 0, // Skip to: 15590 + /* 15553 */ MCD_OPC_Decode, + 134, + 24, + 182, + 2, // Opcode: WFMAXSB + /* 15558 */ MCD_OPC_FilterValue, + 131, + 1, + 10, + 0, + 0, // Skip to: 15574 + /* 15564 */ MCD_OPC_CheckPredicate, + 35, + 21, + 0, + 0, // Skip to: 15590 + /* 15569 */ MCD_OPC_Decode, + 133, + 24, + 183, + 2, // Opcode: WFMAXDB + /* 15574 */ MCD_OPC_FilterValue, + 132, + 1, + 10, + 0, + 0, // Skip to: 15590 + /* 15580 */ MCD_OPC_CheckPredicate, + 35, + 5, + 0, + 0, // Skip to: 15590 + /* 15585 */ MCD_OPC_Decode, + 135, + 24, + 235, + 1, // Opcode: WFMAXXB + /* 15590 */ MCD_OPC_CheckPredicate, + 35, + 225, + 29, + 0, // Skip to: 23244 + /* 15595 */ MCD_OPC_Decode, + 186, + 20, + 181, + 2, // Opcode: VFMAX + /* 15600 */ MCD_OPC_FilterValue, + 240, + 1, + 89, + 0, + 0, // Skip to: 15695 + /* 15606 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 15609 */ MCD_OPC_FilterValue, + 0, + 206, + 29, + 0, // Skip to: 23244 + /* 15614 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 15617 */ MCD_OPC_FilterValue, + 0, + 198, + 29, + 0, // Skip to: 23244 + /* 15622 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 15625 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 15640 + /* 15630 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 15685 + /* 15635 */ MCD_OPC_Decode, + 224, + 18, + 239, + 1, // Opcode: VAVGLB + /* 15640 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 15655 + /* 15645 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 15685 + /* 15650 */ MCD_OPC_Decode, + 227, + 18, + 239, + 1, // Opcode: VAVGLH + /* 15655 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 15670 + /* 15660 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 15685 + /* 15665 */ MCD_OPC_Decode, + 225, + 18, + 239, + 1, // Opcode: VAVGLF + /* 15670 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 15685 + /* 15675 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 15685 + /* 15680 */ MCD_OPC_Decode, + 226, + 18, + 239, + 1, // Opcode: VAVGLG + /* 15685 */ MCD_OPC_CheckPredicate, + 34, + 130, + 29, + 0, // Skip to: 23244 + /* 15690 */ MCD_OPC_Decode, + 223, + 18, + 147, + 2, // Opcode: VAVGL + /* 15695 */ MCD_OPC_FilterValue, + 241, + 1, + 104, + 0, + 0, // Skip to: 15805 + /* 15701 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 15704 */ MCD_OPC_FilterValue, + 0, + 111, + 29, + 0, // Skip to: 23244 + /* 15709 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 15712 */ MCD_OPC_FilterValue, + 0, + 103, + 29, + 0, // Skip to: 23244 + /* 15717 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 15720 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 15735 + /* 15725 */ MCD_OPC_CheckPredicate, + 34, + 65, + 0, + 0, // Skip to: 15795 + /* 15730 */ MCD_OPC_Decode, + 205, + 18, + 239, + 1, // Opcode: VACCB + /* 15735 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 15750 + /* 15740 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 15795 + /* 15745 */ MCD_OPC_Decode, + 210, + 18, + 239, + 1, // Opcode: VACCH + /* 15750 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 15765 + /* 15755 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 15795 + /* 15760 */ MCD_OPC_Decode, + 208, + 18, + 239, + 1, // Opcode: VACCF + /* 15765 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 15780 + /* 15770 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 15795 + /* 15775 */ MCD_OPC_Decode, + 209, + 18, + 239, + 1, // Opcode: VACCG + /* 15780 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 15795 + /* 15785 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 15795 + /* 15790 */ MCD_OPC_Decode, + 211, + 18, + 239, + 1, // Opcode: VACCQ + /* 15795 */ MCD_OPC_CheckPredicate, + 34, + 20, + 29, + 0, // Skip to: 23244 + /* 15800 */ MCD_OPC_Decode, + 204, + 18, + 147, + 2, // Opcode: VACC + /* 15805 */ MCD_OPC_FilterValue, + 242, + 1, + 89, + 0, + 0, // Skip to: 15900 + /* 15811 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 15814 */ MCD_OPC_FilterValue, + 0, + 1, + 29, + 0, // Skip to: 23244 + /* 15819 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 15822 */ MCD_OPC_FilterValue, + 0, + 249, + 28, + 0, // Skip to: 23244 + /* 15827 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 15830 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 15845 + /* 15835 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 15890 + /* 15840 */ MCD_OPC_Decode, + 219, + 18, + 239, + 1, // Opcode: VAVGB + /* 15845 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 15860 + /* 15850 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 15890 + /* 15855 */ MCD_OPC_Decode, + 222, + 18, + 239, + 1, // Opcode: VAVGH + /* 15860 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 15875 + /* 15865 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 15890 + /* 15870 */ MCD_OPC_Decode, + 220, + 18, + 239, + 1, // Opcode: VAVGF + /* 15875 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 15890 + /* 15880 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 15890 + /* 15885 */ MCD_OPC_Decode, + 221, + 18, + 239, + 1, // Opcode: VAVGG + /* 15890 */ MCD_OPC_CheckPredicate, + 34, + 181, + 28, + 0, // Skip to: 23244 + /* 15895 */ MCD_OPC_Decode, + 218, + 18, + 147, + 2, // Opcode: VAVG + /* 15900 */ MCD_OPC_FilterValue, + 243, + 1, + 104, + 0, + 0, // Skip to: 16010 + /* 15906 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 15909 */ MCD_OPC_FilterValue, + 0, + 162, + 28, + 0, // Skip to: 23244 + /* 15914 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 15917 */ MCD_OPC_FilterValue, + 0, + 154, + 28, + 0, // Skip to: 23244 + /* 15922 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 15925 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 15940 + /* 15930 */ MCD_OPC_CheckPredicate, + 34, + 65, + 0, + 0, // Skip to: 16000 + /* 15935 */ MCD_OPC_Decode, + 202, + 18, + 239, + 1, // Opcode: VAB + /* 15940 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 15955 + /* 15945 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 16000 + /* 15950 */ MCD_OPC_Decode, + 215, + 18, + 239, + 1, // Opcode: VAH + /* 15955 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 15970 + /* 15960 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 16000 + /* 15965 */ MCD_OPC_Decode, + 213, + 18, + 239, + 1, // Opcode: VAF + /* 15970 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 15985 + /* 15975 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 16000 + /* 15980 */ MCD_OPC_Decode, + 214, + 18, + 239, + 1, // Opcode: VAG + /* 15985 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 16000 + /* 15990 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 16000 + /* 15995 */ MCD_OPC_Decode, + 217, + 18, + 239, + 1, // Opcode: VAQ + /* 16000 */ MCD_OPC_CheckPredicate, + 34, + 71, + 28, + 0, // Skip to: 23244 + /* 16005 */ MCD_OPC_Decode, + 201, + 18, + 147, + 2, // Opcode: VA + /* 16010 */ MCD_OPC_FilterValue, + 245, + 1, + 104, + 0, + 0, // Skip to: 16120 + /* 16016 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 16019 */ MCD_OPC_FilterValue, + 0, + 52, + 28, + 0, // Skip to: 23244 + /* 16024 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 16027 */ MCD_OPC_FilterValue, + 0, + 44, + 28, + 0, // Skip to: 23244 + /* 16032 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 16035 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16050 + /* 16040 */ MCD_OPC_CheckPredicate, + 34, + 65, + 0, + 0, // Skip to: 16110 + /* 16045 */ MCD_OPC_Decode, + 203, + 22, + 239, + 1, // Opcode: VSCBIB + /* 16050 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 16065 + /* 16055 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 16110 + /* 16060 */ MCD_OPC_Decode, + 206, + 22, + 239, + 1, // Opcode: VSCBIH + /* 16065 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 16080 + /* 16070 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 16110 + /* 16075 */ MCD_OPC_Decode, + 204, + 22, + 239, + 1, // Opcode: VSCBIF + /* 16080 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 16095 + /* 16085 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 16110 + /* 16090 */ MCD_OPC_Decode, + 205, + 22, + 239, + 1, // Opcode: VSCBIG + /* 16095 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 16110 + /* 16100 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 16110 + /* 16105 */ MCD_OPC_Decode, + 207, + 22, + 239, + 1, // Opcode: VSCBIQ + /* 16110 */ MCD_OPC_CheckPredicate, + 34, + 217, + 27, + 0, // Skip to: 23244 + /* 16115 */ MCD_OPC_Decode, + 202, + 22, + 147, + 2, // Opcode: VSCBI + /* 16120 */ MCD_OPC_FilterValue, + 247, + 1, + 104, + 0, + 0, // Skip to: 16230 + /* 16126 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 16129 */ MCD_OPC_FilterValue, + 0, + 198, + 27, + 0, // Skip to: 23244 + /* 16134 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 16137 */ MCD_OPC_FilterValue, + 0, + 190, + 27, + 0, // Skip to: 23244 + /* 16142 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 16145 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16160 + /* 16150 */ MCD_OPC_CheckPredicate, + 34, + 65, + 0, + 0, // Skip to: 16220 + /* 16155 */ MCD_OPC_Decode, + 197, + 22, + 239, + 1, // Opcode: VSB + /* 16160 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 16175 + /* 16165 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 16220 + /* 16170 */ MCD_OPC_Decode, + 223, + 22, + 239, + 1, // Opcode: VSH + /* 16175 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 16190 + /* 16180 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 16220 + /* 16185 */ MCD_OPC_Decode, + 221, + 22, + 239, + 1, // Opcode: VSF + /* 16190 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 16205 + /* 16195 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 16220 + /* 16200 */ MCD_OPC_Decode, + 222, + 22, + 239, + 1, // Opcode: VSG + /* 16205 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 16220 + /* 16210 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 16220 + /* 16215 */ MCD_OPC_Decode, + 229, + 22, + 239, + 1, // Opcode: VSQ + /* 16220 */ MCD_OPC_CheckPredicate, + 34, + 107, + 27, + 0, // Skip to: 23244 + /* 16225 */ MCD_OPC_Decode, + 196, + 22, + 147, + 2, // Opcode: VS + /* 16230 */ MCD_OPC_FilterValue, + 248, + 1, + 189, + 0, + 0, // Skip to: 16425 + /* 16236 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 16239 */ MCD_OPC_FilterValue, + 0, + 88, + 27, + 0, // Skip to: 23244 + /* 16244 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 16247 */ MCD_OPC_FilterValue, + 0, + 80, + 27, + 0, // Skip to: 23244 + /* 16252 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 16255 */ MCD_OPC_FilterValue, + 0, + 72, + 27, + 0, // Skip to: 23244 + /* 16260 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 16263 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 16301 + /* 16268 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16271 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16286 + /* 16276 */ MCD_OPC_CheckPredicate, + 34, + 134, + 0, + 0, // Skip to: 16415 + /* 16281 */ MCD_OPC_Decode, + 236, + 18, + 239, + 1, // Opcode: VCEQB + /* 16286 */ MCD_OPC_FilterValue, + 1, + 124, + 0, + 0, // Skip to: 16415 + /* 16291 */ MCD_OPC_CheckPredicate, + 34, + 119, + 0, + 0, // Skip to: 16415 + /* 16296 */ MCD_OPC_Decode, + 237, + 18, + 239, + 1, // Opcode: VCEQBS + /* 16301 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 16339 + /* 16306 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16309 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16324 + /* 16314 */ MCD_OPC_CheckPredicate, + 34, + 96, + 0, + 0, // Skip to: 16415 + /* 16319 */ MCD_OPC_Decode, + 242, + 18, + 239, + 1, // Opcode: VCEQH + /* 16324 */ MCD_OPC_FilterValue, + 1, + 86, + 0, + 0, // Skip to: 16415 + /* 16329 */ MCD_OPC_CheckPredicate, + 34, + 81, + 0, + 0, // Skip to: 16415 + /* 16334 */ MCD_OPC_Decode, + 243, + 18, + 239, + 1, // Opcode: VCEQHS + /* 16339 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 16377 + /* 16344 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16347 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16362 + /* 16352 */ MCD_OPC_CheckPredicate, + 34, + 58, + 0, + 0, // Skip to: 16415 + /* 16357 */ MCD_OPC_Decode, + 238, + 18, + 239, + 1, // Opcode: VCEQF + /* 16362 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 16415 + /* 16367 */ MCD_OPC_CheckPredicate, + 34, + 43, + 0, + 0, // Skip to: 16415 + /* 16372 */ MCD_OPC_Decode, + 239, + 18, + 239, + 1, // Opcode: VCEQFS + /* 16377 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 16415 + /* 16382 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16385 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16400 + /* 16390 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 16415 + /* 16395 */ MCD_OPC_Decode, + 240, + 18, + 239, + 1, // Opcode: VCEQG + /* 16400 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 16415 + /* 16405 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 16415 + /* 16410 */ MCD_OPC_Decode, + 241, + 18, + 239, + 1, // Opcode: VCEQGS + /* 16415 */ MCD_OPC_CheckPredicate, + 34, + 168, + 26, + 0, // Skip to: 23244 + /* 16420 */ MCD_OPC_Decode, + 235, + 18, + 236, + 1, // Opcode: VCEQ + /* 16425 */ MCD_OPC_FilterValue, + 249, + 1, + 189, + 0, + 0, // Skip to: 16620 + /* 16431 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 16434 */ MCD_OPC_FilterValue, + 0, + 149, + 26, + 0, // Skip to: 23244 + /* 16439 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 16442 */ MCD_OPC_FilterValue, + 0, + 141, + 26, + 0, // Skip to: 23244 + /* 16447 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 16450 */ MCD_OPC_FilterValue, + 0, + 133, + 26, + 0, // Skip to: 23244 + /* 16455 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 16458 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 16496 + /* 16463 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16466 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16481 + /* 16471 */ MCD_OPC_CheckPredicate, + 34, + 134, + 0, + 0, // Skip to: 16610 + /* 16476 */ MCD_OPC_Decode, + 132, + 19, + 239, + 1, // Opcode: VCHLB + /* 16481 */ MCD_OPC_FilterValue, + 1, + 124, + 0, + 0, // Skip to: 16610 + /* 16486 */ MCD_OPC_CheckPredicate, + 34, + 119, + 0, + 0, // Skip to: 16610 + /* 16491 */ MCD_OPC_Decode, + 133, + 19, + 239, + 1, // Opcode: VCHLBS + /* 16496 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 16534 + /* 16501 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16504 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16519 + /* 16509 */ MCD_OPC_CheckPredicate, + 34, + 96, + 0, + 0, // Skip to: 16610 + /* 16514 */ MCD_OPC_Decode, + 138, + 19, + 239, + 1, // Opcode: VCHLH + /* 16519 */ MCD_OPC_FilterValue, + 1, + 86, + 0, + 0, // Skip to: 16610 + /* 16524 */ MCD_OPC_CheckPredicate, + 34, + 81, + 0, + 0, // Skip to: 16610 + /* 16529 */ MCD_OPC_Decode, + 139, + 19, + 239, + 1, // Opcode: VCHLHS + /* 16534 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 16572 + /* 16539 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16542 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16557 + /* 16547 */ MCD_OPC_CheckPredicate, + 34, + 58, + 0, + 0, // Skip to: 16610 + /* 16552 */ MCD_OPC_Decode, + 134, + 19, + 239, + 1, // Opcode: VCHLF + /* 16557 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 16610 + /* 16562 */ MCD_OPC_CheckPredicate, + 34, + 43, + 0, + 0, // Skip to: 16610 + /* 16567 */ MCD_OPC_Decode, + 135, + 19, + 239, + 1, // Opcode: VCHLFS + /* 16572 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 16610 + /* 16577 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16580 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16595 + /* 16585 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 16610 + /* 16590 */ MCD_OPC_Decode, + 136, + 19, + 239, + 1, // Opcode: VCHLG + /* 16595 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 16610 + /* 16600 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 16610 + /* 16605 */ MCD_OPC_Decode, + 137, + 19, + 239, + 1, // Opcode: VCHLGS + /* 16610 */ MCD_OPC_CheckPredicate, + 34, + 229, + 25, + 0, // Skip to: 23244 + /* 16615 */ MCD_OPC_Decode, + 131, + 19, + 236, + 1, // Opcode: VCHL + /* 16620 */ MCD_OPC_FilterValue, + 251, + 1, + 189, + 0, + 0, // Skip to: 16815 + /* 16626 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 16629 */ MCD_OPC_FilterValue, + 0, + 210, + 25, + 0, // Skip to: 23244 + /* 16634 */ MCD_OPC_ExtractField, + 16, + 4, // Inst{19-16} ... + /* 16637 */ MCD_OPC_FilterValue, + 0, + 202, + 25, + 0, // Skip to: 23244 + /* 16642 */ MCD_OPC_ExtractField, + 24, + 4, // Inst{27-24} ... + /* 16645 */ MCD_OPC_FilterValue, + 0, + 194, + 25, + 0, // Skip to: 23244 + /* 16650 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 16653 */ MCD_OPC_FilterValue, + 0, + 33, + 0, + 0, // Skip to: 16691 + /* 16658 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16661 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16676 + /* 16666 */ MCD_OPC_CheckPredicate, + 34, + 134, + 0, + 0, // Skip to: 16805 + /* 16671 */ MCD_OPC_Decode, + 251, + 18, + 239, + 1, // Opcode: VCHB + /* 16676 */ MCD_OPC_FilterValue, + 1, + 124, + 0, + 0, // Skip to: 16805 + /* 16681 */ MCD_OPC_CheckPredicate, + 34, + 119, + 0, + 0, // Skip to: 16805 + /* 16686 */ MCD_OPC_Decode, + 252, + 18, + 239, + 1, // Opcode: VCHBS + /* 16691 */ MCD_OPC_FilterValue, + 1, + 33, + 0, + 0, // Skip to: 16729 + /* 16696 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16699 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16714 + /* 16704 */ MCD_OPC_CheckPredicate, + 34, + 96, + 0, + 0, // Skip to: 16805 + /* 16709 */ MCD_OPC_Decode, + 129, + 19, + 239, + 1, // Opcode: VCHH + /* 16714 */ MCD_OPC_FilterValue, + 1, + 86, + 0, + 0, // Skip to: 16805 + /* 16719 */ MCD_OPC_CheckPredicate, + 34, + 81, + 0, + 0, // Skip to: 16805 + /* 16724 */ MCD_OPC_Decode, + 130, + 19, + 239, + 1, // Opcode: VCHHS + /* 16729 */ MCD_OPC_FilterValue, + 2, + 33, + 0, + 0, // Skip to: 16767 + /* 16734 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16737 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16752 + /* 16742 */ MCD_OPC_CheckPredicate, + 34, + 58, + 0, + 0, // Skip to: 16805 + /* 16747 */ MCD_OPC_Decode, + 253, + 18, + 239, + 1, // Opcode: VCHF + /* 16752 */ MCD_OPC_FilterValue, + 1, + 48, + 0, + 0, // Skip to: 16805 + /* 16757 */ MCD_OPC_CheckPredicate, + 34, + 43, + 0, + 0, // Skip to: 16805 + /* 16762 */ MCD_OPC_Decode, + 254, + 18, + 239, + 1, // Opcode: VCHFS + /* 16767 */ MCD_OPC_FilterValue, + 3, + 33, + 0, + 0, // Skip to: 16805 + /* 16772 */ MCD_OPC_ExtractField, + 20, + 4, // Inst{23-20} ... + /* 16775 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16790 + /* 16780 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 16805 + /* 16785 */ MCD_OPC_Decode, + 255, + 18, + 239, + 1, // Opcode: VCHG + /* 16790 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 16805 + /* 16795 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 16805 + /* 16800 */ MCD_OPC_Decode, + 128, + 19, + 239, + 1, // Opcode: VCHGS + /* 16805 */ MCD_OPC_CheckPredicate, + 34, + 34, + 25, + 0, // Skip to: 23244 + /* 16810 */ MCD_OPC_Decode, + 250, + 18, + 236, + 1, // Opcode: VCH + /* 16815 */ MCD_OPC_FilterValue, + 252, + 1, + 89, + 0, + 0, // Skip to: 16910 + /* 16821 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 16824 */ MCD_OPC_FilterValue, + 0, + 15, + 25, + 0, // Skip to: 23244 + /* 16829 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 16832 */ MCD_OPC_FilterValue, + 0, + 7, + 25, + 0, // Skip to: 23244 + /* 16837 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 16840 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16855 + /* 16845 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 16900 + /* 16850 */ MCD_OPC_Decode, + 245, + 21, + 239, + 1, // Opcode: VMNLB + /* 16855 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 16870 + /* 16860 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 16900 + /* 16865 */ MCD_OPC_Decode, + 248, + 21, + 239, + 1, // Opcode: VMNLH + /* 16870 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 16885 + /* 16875 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 16900 + /* 16880 */ MCD_OPC_Decode, + 246, + 21, + 239, + 1, // Opcode: VMNLF + /* 16885 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 16900 + /* 16890 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 16900 + /* 16895 */ MCD_OPC_Decode, + 247, + 21, + 239, + 1, // Opcode: VMNLG + /* 16900 */ MCD_OPC_CheckPredicate, + 34, + 195, + 24, + 0, // Skip to: 23244 + /* 16905 */ MCD_OPC_Decode, + 244, + 21, + 147, + 2, // Opcode: VMNL + /* 16910 */ MCD_OPC_FilterValue, + 253, + 1, + 89, + 0, + 0, // Skip to: 17005 + /* 16916 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 16919 */ MCD_OPC_FilterValue, + 0, + 176, + 24, + 0, // Skip to: 23244 + /* 16924 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 16927 */ MCD_OPC_FilterValue, + 0, + 168, + 24, + 0, // Skip to: 23244 + /* 16932 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 16935 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 16950 + /* 16940 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 16995 + /* 16945 */ MCD_OPC_Decode, + 145, + 22, + 239, + 1, // Opcode: VMXLB + /* 16950 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 16965 + /* 16955 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 16995 + /* 16960 */ MCD_OPC_Decode, + 148, + 22, + 239, + 1, // Opcode: VMXLH + /* 16965 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 16980 + /* 16970 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 16995 + /* 16975 */ MCD_OPC_Decode, + 146, + 22, + 239, + 1, // Opcode: VMXLF + /* 16980 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 16995 + /* 16985 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 16995 + /* 16990 */ MCD_OPC_Decode, + 147, + 22, + 239, + 1, // Opcode: VMXLG + /* 16995 */ MCD_OPC_CheckPredicate, + 34, + 100, + 24, + 0, // Skip to: 23244 + /* 17000 */ MCD_OPC_Decode, + 144, + 22, + 147, + 2, // Opcode: VMXL + /* 17005 */ MCD_OPC_FilterValue, + 254, + 1, + 89, + 0, + 0, // Skip to: 17100 + /* 17011 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 17014 */ MCD_OPC_FilterValue, + 0, + 81, + 24, + 0, // Skip to: 23244 + /* 17019 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 17022 */ MCD_OPC_FilterValue, + 0, + 73, + 24, + 0, // Skip to: 23244 + /* 17027 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 17030 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17045 + /* 17035 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 17090 + /* 17040 */ MCD_OPC_Decode, + 240, + 21, + 239, + 1, // Opcode: VMNB + /* 17045 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 17060 + /* 17050 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 17090 + /* 17055 */ MCD_OPC_Decode, + 243, + 21, + 239, + 1, // Opcode: VMNH + /* 17060 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 17075 + /* 17065 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 17090 + /* 17070 */ MCD_OPC_Decode, + 241, + 21, + 239, + 1, // Opcode: VMNF + /* 17075 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 17090 + /* 17080 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 17090 + /* 17085 */ MCD_OPC_Decode, + 242, + 21, + 239, + 1, // Opcode: VMNG + /* 17090 */ MCD_OPC_CheckPredicate, + 34, + 5, + 24, + 0, // Skip to: 23244 + /* 17095 */ MCD_OPC_Decode, + 239, + 21, + 147, + 2, // Opcode: VMN + /* 17100 */ MCD_OPC_FilterValue, + 255, + 1, + 250, + 23, + 0, // Skip to: 23244 + /* 17106 */ MCD_OPC_ExtractField, + 8, + 1, // Inst{8} ... + /* 17109 */ MCD_OPC_FilterValue, + 0, + 242, + 23, + 0, // Skip to: 23244 + /* 17114 */ MCD_OPC_ExtractField, + 16, + 12, // Inst{27-16} ... + /* 17117 */ MCD_OPC_FilterValue, + 0, + 234, + 23, + 0, // Skip to: 23244 + /* 17122 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 17125 */ MCD_OPC_FilterValue, + 0, + 10, + 0, + 0, // Skip to: 17140 + /* 17130 */ MCD_OPC_CheckPredicate, + 34, + 50, + 0, + 0, // Skip to: 17185 + /* 17135 */ MCD_OPC_Decode, + 140, + 22, + 239, + 1, // Opcode: VMXB + /* 17140 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 17155 + /* 17145 */ MCD_OPC_CheckPredicate, + 34, + 35, + 0, + 0, // Skip to: 17185 + /* 17150 */ MCD_OPC_Decode, + 143, + 22, + 239, + 1, // Opcode: VMXH + /* 17155 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 17170 + /* 17160 */ MCD_OPC_CheckPredicate, + 34, + 20, + 0, + 0, // Skip to: 17185 + /* 17165 */ MCD_OPC_Decode, + 141, + 22, + 239, + 1, // Opcode: VMXF + /* 17170 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 17185 + /* 17175 */ MCD_OPC_CheckPredicate, + 34, + 5, + 0, + 0, // Skip to: 17185 + /* 17180 */ MCD_OPC_Decode, + 142, + 22, + 239, + 1, // Opcode: VMXG + /* 17185 */ MCD_OPC_CheckPredicate, + 34, + 166, + 23, + 0, // Skip to: 23244 + /* 17190 */ MCD_OPC_Decode, + 139, + 22, + 147, + 2, // Opcode: VMX + /* 17195 */ MCD_OPC_FilterValue, + 232, + 1, + 5, + 0, + 0, // Skip to: 17206 + /* 17201 */ MCD_OPC_Decode, + 227, + 14, + 198, + 1, // Opcode: MVCIN + /* 17206 */ MCD_OPC_FilterValue, + 233, + 1, + 5, + 0, + 0, // Skip to: 17217 + /* 17212 */ MCD_OPC_Decode, + 190, + 15, + 200, + 1, // Opcode: PKA + /* 17217 */ MCD_OPC_FilterValue, + 234, + 1, + 5, + 0, + 0, // Skip to: 17228 + /* 17223 */ MCD_OPC_Decode, + 198, + 18, + 198, + 1, // Opcode: UNPKA + /* 17228 */ MCD_OPC_FilterValue, + 235, + 1, + 245, + 8, + 0, // Skip to: 19527 + /* 17234 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 17237 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 17247 + /* 17242 */ MCD_OPC_Decode, + 132, + 12, + 184, + 2, // Opcode: LMG + /* 17247 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 17257 + /* 17252 */ MCD_OPC_Decode, + 250, + 16, + 185, + 2, // Opcode: SRAG + /* 17257 */ MCD_OPC_FilterValue, + 11, + 5, + 0, + 0, // Skip to: 17267 + /* 17262 */ MCD_OPC_Decode, + 206, + 16, + 185, + 2, // Opcode: SLAG + /* 17267 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 17277 + /* 17272 */ MCD_OPC_Decode, + 129, + 17, + 185, + 2, // Opcode: SRLG + /* 17277 */ MCD_OPC_FilterValue, + 13, + 5, + 0, + 0, // Skip to: 17287 + /* 17282 */ MCD_OPC_Decode, + 225, + 16, + 185, + 2, // Opcode: SLLG + /* 17287 */ MCD_OPC_FilterValue, + 15, + 5, + 0, + 0, // Skip to: 17297 + /* 17292 */ MCD_OPC_Decode, + 177, + 18, + 184, + 2, // Opcode: TRACG + /* 17297 */ MCD_OPC_FilterValue, + 20, + 5, + 0, + 0, // Skip to: 17307 + /* 17302 */ MCD_OPC_Decode, + 164, + 9, + 186, + 2, // Opcode: CSY + /* 17307 */ MCD_OPC_FilterValue, + 28, + 5, + 0, + 0, // Skip to: 17317 + /* 17312 */ MCD_OPC_Decode, + 218, + 15, + 185, + 2, // Opcode: RLLG + /* 17317 */ MCD_OPC_FilterValue, + 29, + 5, + 0, + 0, // Skip to: 17327 + /* 17322 */ MCD_OPC_Decode, + 217, + 15, + 187, + 2, // Opcode: RLL + /* 17327 */ MCD_OPC_FilterValue, + 32, + 5, + 0, + 0, // Skip to: 17337 + /* 17332 */ MCD_OPC_Decode, + 167, + 8, + 188, + 2, // Opcode: CLMH + /* 17337 */ MCD_OPC_FilterValue, + 33, + 5, + 0, + 0, // Skip to: 17347 + /* 17342 */ MCD_OPC_Decode, + 168, + 8, + 189, + 2, // Opcode: CLMY + /* 17347 */ MCD_OPC_FilterValue, + 35, + 103, + 0, + 0, // Skip to: 17455 + /* 17352 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 17355 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 17370 + /* 17360 */ MCD_OPC_CheckPredicate, + 36, + 80, + 0, + 0, // Skip to: 17445 + /* 17365 */ MCD_OPC_Decode, + 217, + 8, + 190, + 2, // Opcode: CLTAsmH + /* 17370 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 17385 + /* 17375 */ MCD_OPC_CheckPredicate, + 36, + 65, + 0, + 0, // Skip to: 17445 + /* 17380 */ MCD_OPC_Decode, + 219, + 8, + 190, + 2, // Opcode: CLTAsmL + /* 17385 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 17400 + /* 17390 */ MCD_OPC_CheckPredicate, + 36, + 50, + 0, + 0, // Skip to: 17445 + /* 17395 */ MCD_OPC_Decode, + 221, + 8, + 190, + 2, // Opcode: CLTAsmLH + /* 17400 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 17415 + /* 17405 */ MCD_OPC_CheckPredicate, + 36, + 35, + 0, + 0, // Skip to: 17445 + /* 17410 */ MCD_OPC_Decode, + 216, + 8, + 190, + 2, // Opcode: CLTAsmE + /* 17415 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 17430 + /* 17420 */ MCD_OPC_CheckPredicate, + 36, + 20, + 0, + 0, // Skip to: 17445 + /* 17425 */ MCD_OPC_Decode, + 218, + 8, + 190, + 2, // Opcode: CLTAsmHE + /* 17430 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 17445 + /* 17435 */ MCD_OPC_CheckPredicate, + 36, + 5, + 0, + 0, // Skip to: 17445 + /* 17440 */ MCD_OPC_Decode, + 220, + 8, + 190, + 2, // Opcode: CLTAsmLE + /* 17445 */ MCD_OPC_CheckPredicate, + 36, + 162, + 22, + 0, // Skip to: 23244 + /* 17450 */ MCD_OPC_Decode, + 215, + 8, + 191, + 2, // Opcode: CLTAsm + /* 17455 */ MCD_OPC_FilterValue, + 36, + 5, + 0, + 0, // Skip to: 17465 + /* 17460 */ MCD_OPC_Decode, + 180, + 17, + 184, + 2, // Opcode: STMG + /* 17465 */ MCD_OPC_FilterValue, + 37, + 5, + 0, + 0, // Skip to: 17475 + /* 17470 */ MCD_OPC_Decode, + 160, + 17, + 192, + 2, // Opcode: STCTG + /* 17475 */ MCD_OPC_FilterValue, + 38, + 5, + 0, + 0, // Skip to: 17485 + /* 17480 */ MCD_OPC_Decode, + 181, + 17, + 193, + 2, // Opcode: STMH + /* 17485 */ MCD_OPC_FilterValue, + 43, + 103, + 0, + 0, // Skip to: 17593 + /* 17490 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 17493 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 17508 + /* 17498 */ MCD_OPC_CheckPredicate, + 36, + 80, + 0, + 0, // Skip to: 17583 + /* 17503 */ MCD_OPC_Decode, + 245, + 7, + 194, + 2, // Opcode: CLGTAsmH + /* 17508 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 17523 + /* 17513 */ MCD_OPC_CheckPredicate, + 36, + 65, + 0, + 0, // Skip to: 17583 + /* 17518 */ MCD_OPC_Decode, + 247, + 7, + 194, + 2, // Opcode: CLGTAsmL + /* 17523 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 17538 + /* 17528 */ MCD_OPC_CheckPredicate, + 36, + 50, + 0, + 0, // Skip to: 17583 + /* 17533 */ MCD_OPC_Decode, + 249, + 7, + 194, + 2, // Opcode: CLGTAsmLH + /* 17538 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 17553 + /* 17543 */ MCD_OPC_CheckPredicate, + 36, + 35, + 0, + 0, // Skip to: 17583 + /* 17548 */ MCD_OPC_Decode, + 244, + 7, + 194, + 2, // Opcode: CLGTAsmE + /* 17553 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 17568 + /* 17558 */ MCD_OPC_CheckPredicate, + 36, + 20, + 0, + 0, // Skip to: 17583 + /* 17563 */ MCD_OPC_Decode, + 246, + 7, + 194, + 2, // Opcode: CLGTAsmHE + /* 17568 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 17583 + /* 17573 */ MCD_OPC_CheckPredicate, + 36, + 5, + 0, + 0, // Skip to: 17583 + /* 17578 */ MCD_OPC_Decode, + 248, + 7, + 194, + 2, // Opcode: CLGTAsmLE + /* 17583 */ MCD_OPC_CheckPredicate, + 36, + 24, + 22, + 0, // Skip to: 23244 + /* 17588 */ MCD_OPC_Decode, + 243, + 7, + 195, + 2, // Opcode: CLGTAsm + /* 17593 */ MCD_OPC_FilterValue, + 44, + 5, + 0, + 0, // Skip to: 17603 + /* 17598 */ MCD_OPC_Decode, + 156, + 17, + 188, + 2, // Opcode: STCMH + /* 17603 */ MCD_OPC_FilterValue, + 45, + 5, + 0, + 0, // Skip to: 17613 + /* 17608 */ MCD_OPC_Decode, + 157, + 17, + 189, + 2, // Opcode: STCMY + /* 17613 */ MCD_OPC_FilterValue, + 47, + 5, + 0, + 0, // Skip to: 17623 + /* 17618 */ MCD_OPC_Decode, + 176, + 11, + 192, + 2, // Opcode: LCTLG + /* 17623 */ MCD_OPC_FilterValue, + 48, + 5, + 0, + 0, // Skip to: 17633 + /* 17628 */ MCD_OPC_Decode, + 159, + 9, + 196, + 2, // Opcode: CSG + /* 17633 */ MCD_OPC_FilterValue, + 49, + 5, + 0, + 0, // Skip to: 17643 + /* 17638 */ MCD_OPC_Decode, + 184, + 5, + 197, + 2, // Opcode: CDSY + /* 17643 */ MCD_OPC_FilterValue, + 62, + 5, + 0, + 0, // Skip to: 17653 + /* 17648 */ MCD_OPC_Decode, + 182, + 5, + 197, + 2, // Opcode: CDSG + /* 17653 */ MCD_OPC_FilterValue, + 68, + 5, + 0, + 0, // Skip to: 17663 + /* 17658 */ MCD_OPC_Decode, + 159, + 5, + 196, + 2, // Opcode: BXHG + /* 17663 */ MCD_OPC_FilterValue, + 69, + 5, + 0, + 0, // Skip to: 17673 + /* 17668 */ MCD_OPC_Decode, + 161, + 5, + 196, + 2, // Opcode: BXLEG + /* 17673 */ MCD_OPC_FilterValue, + 76, + 5, + 0, + 0, // Skip to: 17683 + /* 17678 */ MCD_OPC_Decode, + 241, + 9, + 185, + 2, // Opcode: ECAG + /* 17683 */ MCD_OPC_FilterValue, + 81, + 5, + 0, + 0, // Skip to: 17693 + /* 17688 */ MCD_OPC_Decode, + 171, + 18, + 198, + 2, // Opcode: TMY + /* 17693 */ MCD_OPC_FilterValue, + 82, + 5, + 0, + 0, // Skip to: 17703 + /* 17698 */ MCD_OPC_Decode, + 241, + 14, + 198, + 2, // Opcode: MVIY + /* 17703 */ MCD_OPC_FilterValue, + 84, + 5, + 0, + 0, // Skip to: 17713 + /* 17708 */ MCD_OPC_Decode, + 148, + 15, + 198, + 2, // Opcode: NIY + /* 17713 */ MCD_OPC_FilterValue, + 85, + 5, + 0, + 0, // Skip to: 17723 + /* 17718 */ MCD_OPC_Decode, + 165, + 8, + 198, + 2, // Opcode: CLIY + /* 17723 */ MCD_OPC_FilterValue, + 86, + 5, + 0, + 0, // Skip to: 17733 + /* 17728 */ MCD_OPC_Decode, + 175, + 15, + 198, + 2, // Opcode: OIY + /* 17733 */ MCD_OPC_FilterValue, + 87, + 5, + 0, + 0, // Skip to: 17743 + /* 17738 */ MCD_OPC_Decode, + 173, + 24, + 198, + 2, // Opcode: XIY + /* 17743 */ MCD_OPC_FilterValue, + 106, + 5, + 0, + 0, // Skip to: 17753 + /* 17748 */ MCD_OPC_Decode, + 179, + 4, + 199, + 2, // Opcode: ASI + /* 17753 */ MCD_OPC_FilterValue, + 110, + 5, + 0, + 0, // Skip to: 17763 + /* 17758 */ MCD_OPC_Decode, + 172, + 4, + 199, + 2, // Opcode: ALSI + /* 17763 */ MCD_OPC_FilterValue, + 113, + 17, + 0, + 0, // Skip to: 17785 + /* 17768 */ MCD_OPC_CheckPredicate, + 0, + 95, + 21, + 0, // Skip to: 23244 + /* 17773 */ MCD_OPC_CheckField, + 32, + 8, + 0, + 88, + 21, + 0, // Skip to: 23244 + /* 17780 */ MCD_OPC_Decode, + 232, + 13, + 200, + 2, // Opcode: LPSWEY + /* 17785 */ MCD_OPC_FilterValue, + 122, + 5, + 0, + 0, // Skip to: 17795 + /* 17790 */ MCD_OPC_Decode, + 145, + 4, + 199, + 2, // Opcode: AGSI + /* 17795 */ MCD_OPC_FilterValue, + 126, + 5, + 0, + 0, // Skip to: 17805 + /* 17800 */ MCD_OPC_Decode, + 166, + 4, + 199, + 2, // Opcode: ALGSI + /* 17805 */ MCD_OPC_FilterValue, + 128, + 1, + 5, + 0, + 0, // Skip to: 17816 + /* 17811 */ MCD_OPC_Decode, + 157, + 10, + 201, + 2, // Opcode: ICMH + /* 17816 */ MCD_OPC_FilterValue, + 129, + 1, + 5, + 0, + 0, // Skip to: 17827 + /* 17822 */ MCD_OPC_Decode, + 158, + 10, + 202, + 2, // Opcode: ICMY + /* 17827 */ MCD_OPC_FilterValue, + 142, + 1, + 5, + 0, + 0, // Skip to: 17838 + /* 17833 */ MCD_OPC_Decode, + 231, + 14, + 203, + 2, // Opcode: MVCLU + /* 17838 */ MCD_OPC_FilterValue, + 143, + 1, + 5, + 0, + 0, // Skip to: 17849 + /* 17844 */ MCD_OPC_Decode, + 252, + 6, + 203, + 2, // Opcode: CLCLU + /* 17849 */ MCD_OPC_FilterValue, + 144, + 1, + 5, + 0, + 0, // Skip to: 17860 + /* 17855 */ MCD_OPC_Decode, + 182, + 17, + 204, + 2, // Opcode: STMY + /* 17860 */ MCD_OPC_FilterValue, + 150, + 1, + 5, + 0, + 0, // Skip to: 17871 + /* 17866 */ MCD_OPC_Decode, + 133, + 12, + 193, + 2, // Opcode: LMH + /* 17871 */ MCD_OPC_FilterValue, + 152, + 1, + 5, + 0, + 0, // Skip to: 17882 + /* 17877 */ MCD_OPC_Decode, + 134, + 12, + 204, + 2, // Opcode: LMY + /* 17882 */ MCD_OPC_FilterValue, + 154, + 1, + 5, + 0, + 0, // Skip to: 17893 + /* 17888 */ MCD_OPC_Decode, + 149, + 11, + 205, + 2, // Opcode: LAMY + /* 17893 */ MCD_OPC_FilterValue, + 155, + 1, + 5, + 0, + 0, // Skip to: 17904 + /* 17899 */ MCD_OPC_Decode, + 146, + 17, + 205, + 2, // Opcode: STAMY + /* 17904 */ MCD_OPC_FilterValue, + 192, + 1, + 19, + 0, + 0, // Skip to: 17929 + /* 17910 */ MCD_OPC_CheckField, + 32, + 4, + 0, + 207, + 20, + 0, // Skip to: 23244 + /* 17917 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 200, + 20, + 0, // Skip to: 23244 + /* 17924 */ MCD_OPC_Decode, + 172, + 18, + 206, + 2, // Opcode: TP + /* 17929 */ MCD_OPC_FilterValue, + 220, + 1, + 10, + 0, + 0, // Skip to: 17945 + /* 17935 */ MCD_OPC_CheckPredicate, + 23, + 184, + 20, + 0, // Skip to: 23244 + /* 17940 */ MCD_OPC_Decode, + 251, + 16, + 187, + 2, // Opcode: SRAK + /* 17945 */ MCD_OPC_FilterValue, + 221, + 1, + 10, + 0, + 0, // Skip to: 17961 + /* 17951 */ MCD_OPC_CheckPredicate, + 23, + 168, + 20, + 0, // Skip to: 23244 + /* 17956 */ MCD_OPC_Decode, + 207, + 16, + 187, + 2, // Opcode: SLAK + /* 17961 */ MCD_OPC_FilterValue, + 222, + 1, + 10, + 0, + 0, // Skip to: 17977 + /* 17967 */ MCD_OPC_CheckPredicate, + 23, + 152, + 20, + 0, // Skip to: 23244 + /* 17972 */ MCD_OPC_Decode, + 130, + 17, + 187, + 2, // Opcode: SRLK + /* 17977 */ MCD_OPC_FilterValue, + 223, + 1, + 10, + 0, + 0, // Skip to: 17993 + /* 17983 */ MCD_OPC_CheckPredicate, + 23, + 136, + 20, + 0, // Skip to: 23244 + /* 17988 */ MCD_OPC_Decode, + 226, + 16, + 187, + 2, // Opcode: SLLK + /* 17993 */ MCD_OPC_FilterValue, + 224, + 1, + 223, + 0, + 0, // Skip to: 18222 + /* 17999 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 18002 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 18017 + /* 18007 */ MCD_OPC_CheckPredicate, + 20, + 200, + 0, + 0, // Skip to: 18212 + /* 18012 */ MCD_OPC_Decode, + 187, + 12, + 207, + 2, // Opcode: LOCFHAsmO + /* 18017 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 18032 + /* 18022 */ MCD_OPC_CheckPredicate, + 20, + 185, + 0, + 0, // Skip to: 18212 + /* 18027 */ MCD_OPC_Decode, + 171, + 12, + 207, + 2, // Opcode: LOCFHAsmH + /* 18032 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 18047 + /* 18037 */ MCD_OPC_CheckPredicate, + 20, + 170, + 0, + 0, // Skip to: 18212 + /* 18042 */ MCD_OPC_Decode, + 181, + 12, + 207, + 2, // Opcode: LOCFHAsmNLE + /* 18047 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 18062 + /* 18052 */ MCD_OPC_CheckPredicate, + 20, + 155, + 0, + 0, // Skip to: 18212 + /* 18057 */ MCD_OPC_Decode, + 173, + 12, + 207, + 2, // Opcode: LOCFHAsmL + /* 18062 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 18077 + /* 18067 */ MCD_OPC_CheckPredicate, + 20, + 140, + 0, + 0, // Skip to: 18212 + /* 18072 */ MCD_OPC_Decode, + 179, + 12, + 207, + 2, // Opcode: LOCFHAsmNHE + /* 18077 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 18092 + /* 18082 */ MCD_OPC_CheckPredicate, + 20, + 125, + 0, + 0, // Skip to: 18212 + /* 18087 */ MCD_OPC_Decode, + 175, + 12, + 207, + 2, // Opcode: LOCFHAsmLH + /* 18092 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 18107 + /* 18097 */ MCD_OPC_CheckPredicate, + 20, + 110, + 0, + 0, // Skip to: 18212 + /* 18102 */ MCD_OPC_Decode, + 177, + 12, + 207, + 2, // Opcode: LOCFHAsmNE + /* 18107 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 18122 + /* 18112 */ MCD_OPC_CheckPredicate, + 20, + 95, + 0, + 0, // Skip to: 18212 + /* 18117 */ MCD_OPC_Decode, + 170, + 12, + 207, + 2, // Opcode: LOCFHAsmE + /* 18122 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 18137 + /* 18127 */ MCD_OPC_CheckPredicate, + 20, + 80, + 0, + 0, // Skip to: 18212 + /* 18132 */ MCD_OPC_Decode, + 182, + 12, + 207, + 2, // Opcode: LOCFHAsmNLH + /* 18137 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 18152 + /* 18142 */ MCD_OPC_CheckPredicate, + 20, + 65, + 0, + 0, // Skip to: 18212 + /* 18147 */ MCD_OPC_Decode, + 172, + 12, + 207, + 2, // Opcode: LOCFHAsmHE + /* 18152 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 18167 + /* 18157 */ MCD_OPC_CheckPredicate, + 20, + 50, + 0, + 0, // Skip to: 18212 + /* 18162 */ MCD_OPC_Decode, + 180, + 12, + 207, + 2, // Opcode: LOCFHAsmNL + /* 18167 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 18182 + /* 18172 */ MCD_OPC_CheckPredicate, + 20, + 35, + 0, + 0, // Skip to: 18212 + /* 18177 */ MCD_OPC_Decode, + 174, + 12, + 207, + 2, // Opcode: LOCFHAsmLE + /* 18182 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 18197 + /* 18187 */ MCD_OPC_CheckPredicate, + 20, + 20, + 0, + 0, // Skip to: 18212 + /* 18192 */ MCD_OPC_Decode, + 178, + 12, + 207, + 2, // Opcode: LOCFHAsmNH + /* 18197 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 18212 + /* 18202 */ MCD_OPC_CheckPredicate, + 20, + 5, + 0, + 0, // Skip to: 18212 + /* 18207 */ MCD_OPC_Decode, + 184, + 12, + 207, + 2, // Opcode: LOCFHAsmNO + /* 18212 */ MCD_OPC_CheckPredicate, + 20, + 163, + 19, + 0, // Skip to: 23244 + /* 18217 */ MCD_OPC_Decode, + 169, + 12, + 208, + 2, // Opcode: LOCFHAsm + /* 18222 */ MCD_OPC_FilterValue, + 225, + 1, + 223, + 0, + 0, // Skip to: 18451 + /* 18228 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 18231 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 18246 + /* 18236 */ MCD_OPC_CheckPredicate, + 20, + 200, + 0, + 0, // Skip to: 18441 + /* 18241 */ MCD_OPC_Decode, + 225, + 17, + 209, + 2, // Opcode: STOCFHAsmO + /* 18246 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 18261 + /* 18251 */ MCD_OPC_CheckPredicate, + 20, + 185, + 0, + 0, // Skip to: 18441 + /* 18256 */ MCD_OPC_Decode, + 209, + 17, + 209, + 2, // Opcode: STOCFHAsmH + /* 18261 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 18276 + /* 18266 */ MCD_OPC_CheckPredicate, + 20, + 170, + 0, + 0, // Skip to: 18441 + /* 18271 */ MCD_OPC_Decode, + 219, + 17, + 209, + 2, // Opcode: STOCFHAsmNLE + /* 18276 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 18291 + /* 18281 */ MCD_OPC_CheckPredicate, + 20, + 155, + 0, + 0, // Skip to: 18441 + /* 18286 */ MCD_OPC_Decode, + 211, + 17, + 209, + 2, // Opcode: STOCFHAsmL + /* 18291 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 18306 + /* 18296 */ MCD_OPC_CheckPredicate, + 20, + 140, + 0, + 0, // Skip to: 18441 + /* 18301 */ MCD_OPC_Decode, + 217, + 17, + 209, + 2, // Opcode: STOCFHAsmNHE + /* 18306 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 18321 + /* 18311 */ MCD_OPC_CheckPredicate, + 20, + 125, + 0, + 0, // Skip to: 18441 + /* 18316 */ MCD_OPC_Decode, + 213, + 17, + 209, + 2, // Opcode: STOCFHAsmLH + /* 18321 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 18336 + /* 18326 */ MCD_OPC_CheckPredicate, + 20, + 110, + 0, + 0, // Skip to: 18441 + /* 18331 */ MCD_OPC_Decode, + 215, + 17, + 209, + 2, // Opcode: STOCFHAsmNE + /* 18336 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 18351 + /* 18341 */ MCD_OPC_CheckPredicate, + 20, + 95, + 0, + 0, // Skip to: 18441 + /* 18346 */ MCD_OPC_Decode, + 208, + 17, + 209, + 2, // Opcode: STOCFHAsmE + /* 18351 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 18366 + /* 18356 */ MCD_OPC_CheckPredicate, + 20, + 80, + 0, + 0, // Skip to: 18441 + /* 18361 */ MCD_OPC_Decode, + 220, + 17, + 209, + 2, // Opcode: STOCFHAsmNLH + /* 18366 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 18381 + /* 18371 */ MCD_OPC_CheckPredicate, + 20, + 65, + 0, + 0, // Skip to: 18441 + /* 18376 */ MCD_OPC_Decode, + 210, + 17, + 209, + 2, // Opcode: STOCFHAsmHE + /* 18381 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 18396 + /* 18386 */ MCD_OPC_CheckPredicate, + 20, + 50, + 0, + 0, // Skip to: 18441 + /* 18391 */ MCD_OPC_Decode, + 218, + 17, + 209, + 2, // Opcode: STOCFHAsmNL + /* 18396 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 18411 + /* 18401 */ MCD_OPC_CheckPredicate, + 20, + 35, + 0, + 0, // Skip to: 18441 + /* 18406 */ MCD_OPC_Decode, + 212, + 17, + 209, + 2, // Opcode: STOCFHAsmLE + /* 18411 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 18426 + /* 18416 */ MCD_OPC_CheckPredicate, + 20, + 20, + 0, + 0, // Skip to: 18441 + /* 18421 */ MCD_OPC_Decode, + 216, + 17, + 209, + 2, // Opcode: STOCFHAsmNH + /* 18426 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 18441 + /* 18431 */ MCD_OPC_CheckPredicate, + 20, + 5, + 0, + 0, // Skip to: 18441 + /* 18436 */ MCD_OPC_Decode, + 222, + 17, + 209, + 2, // Opcode: STOCFHAsmNO + /* 18441 */ MCD_OPC_CheckPredicate, + 20, + 190, + 18, + 0, // Skip to: 23244 + /* 18446 */ MCD_OPC_Decode, + 207, + 17, + 210, + 2, // Opcode: STOCFHAsm + /* 18451 */ MCD_OPC_FilterValue, + 226, + 1, + 223, + 0, + 0, // Skip to: 18680 + /* 18457 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 18460 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 18475 + /* 18465 */ MCD_OPC_CheckPredicate, + 22, + 200, + 0, + 0, // Skip to: 18670 + /* 18470 */ MCD_OPC_Decode, + 231, + 12, + 211, + 2, // Opcode: LOCGAsmO + /* 18475 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 18490 + /* 18480 */ MCD_OPC_CheckPredicate, + 22, + 185, + 0, + 0, // Skip to: 18670 + /* 18485 */ MCD_OPC_Decode, + 215, + 12, + 211, + 2, // Opcode: LOCGAsmH + /* 18490 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 18505 + /* 18495 */ MCD_OPC_CheckPredicate, + 22, + 170, + 0, + 0, // Skip to: 18670 + /* 18500 */ MCD_OPC_Decode, + 225, + 12, + 211, + 2, // Opcode: LOCGAsmNLE + /* 18505 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 18520 + /* 18510 */ MCD_OPC_CheckPredicate, + 22, + 155, + 0, + 0, // Skip to: 18670 + /* 18515 */ MCD_OPC_Decode, + 217, + 12, + 211, + 2, // Opcode: LOCGAsmL + /* 18520 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 18535 + /* 18525 */ MCD_OPC_CheckPredicate, + 22, + 140, + 0, + 0, // Skip to: 18670 + /* 18530 */ MCD_OPC_Decode, + 223, + 12, + 211, + 2, // Opcode: LOCGAsmNHE + /* 18535 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 18550 + /* 18540 */ MCD_OPC_CheckPredicate, + 22, + 125, + 0, + 0, // Skip to: 18670 + /* 18545 */ MCD_OPC_Decode, + 219, + 12, + 211, + 2, // Opcode: LOCGAsmLH + /* 18550 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 18565 + /* 18555 */ MCD_OPC_CheckPredicate, + 22, + 110, + 0, + 0, // Skip to: 18670 + /* 18560 */ MCD_OPC_Decode, + 221, + 12, + 211, + 2, // Opcode: LOCGAsmNE + /* 18565 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 18580 + /* 18570 */ MCD_OPC_CheckPredicate, + 22, + 95, + 0, + 0, // Skip to: 18670 + /* 18575 */ MCD_OPC_Decode, + 214, + 12, + 211, + 2, // Opcode: LOCGAsmE + /* 18580 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 18595 + /* 18585 */ MCD_OPC_CheckPredicate, + 22, + 80, + 0, + 0, // Skip to: 18670 + /* 18590 */ MCD_OPC_Decode, + 226, + 12, + 211, + 2, // Opcode: LOCGAsmNLH + /* 18595 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 18610 + /* 18600 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 18670 + /* 18605 */ MCD_OPC_Decode, + 216, + 12, + 211, + 2, // Opcode: LOCGAsmHE + /* 18610 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 18625 + /* 18615 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 18670 + /* 18620 */ MCD_OPC_Decode, + 224, + 12, + 211, + 2, // Opcode: LOCGAsmNL + /* 18625 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 18640 + /* 18630 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 18670 + /* 18635 */ MCD_OPC_Decode, + 218, + 12, + 211, + 2, // Opcode: LOCGAsmLE + /* 18640 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 18655 + /* 18645 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 18670 + /* 18650 */ MCD_OPC_Decode, + 222, + 12, + 211, + 2, // Opcode: LOCGAsmNH + /* 18655 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 18670 + /* 18660 */ MCD_OPC_CheckPredicate, + 22, + 5, + 0, + 0, // Skip to: 18670 + /* 18665 */ MCD_OPC_Decode, + 228, + 12, + 211, + 2, // Opcode: LOCGAsmNO + /* 18670 */ MCD_OPC_CheckPredicate, + 22, + 217, + 17, + 0, // Skip to: 23244 + /* 18675 */ MCD_OPC_Decode, + 213, + 12, + 212, + 2, // Opcode: LOCGAsm + /* 18680 */ MCD_OPC_FilterValue, + 227, + 1, + 223, + 0, + 0, // Skip to: 18909 + /* 18686 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 18689 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 18704 + /* 18694 */ MCD_OPC_CheckPredicate, + 22, + 200, + 0, + 0, // Skip to: 18899 + /* 18699 */ MCD_OPC_Decode, + 247, + 17, + 194, + 2, // Opcode: STOCGAsmO + /* 18704 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 18719 + /* 18709 */ MCD_OPC_CheckPredicate, + 22, + 185, + 0, + 0, // Skip to: 18899 + /* 18714 */ MCD_OPC_Decode, + 231, + 17, + 194, + 2, // Opcode: STOCGAsmH + /* 18719 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 18734 + /* 18724 */ MCD_OPC_CheckPredicate, + 22, + 170, + 0, + 0, // Skip to: 18899 + /* 18729 */ MCD_OPC_Decode, + 241, + 17, + 194, + 2, // Opcode: STOCGAsmNLE + /* 18734 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 18749 + /* 18739 */ MCD_OPC_CheckPredicate, + 22, + 155, + 0, + 0, // Skip to: 18899 + /* 18744 */ MCD_OPC_Decode, + 233, + 17, + 194, + 2, // Opcode: STOCGAsmL + /* 18749 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 18764 + /* 18754 */ MCD_OPC_CheckPredicate, + 22, + 140, + 0, + 0, // Skip to: 18899 + /* 18759 */ MCD_OPC_Decode, + 239, + 17, + 194, + 2, // Opcode: STOCGAsmNHE + /* 18764 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 18779 + /* 18769 */ MCD_OPC_CheckPredicate, + 22, + 125, + 0, + 0, // Skip to: 18899 + /* 18774 */ MCD_OPC_Decode, + 235, + 17, + 194, + 2, // Opcode: STOCGAsmLH + /* 18779 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 18794 + /* 18784 */ MCD_OPC_CheckPredicate, + 22, + 110, + 0, + 0, // Skip to: 18899 + /* 18789 */ MCD_OPC_Decode, + 237, + 17, + 194, + 2, // Opcode: STOCGAsmNE + /* 18794 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 18809 + /* 18799 */ MCD_OPC_CheckPredicate, + 22, + 95, + 0, + 0, // Skip to: 18899 + /* 18804 */ MCD_OPC_Decode, + 230, + 17, + 194, + 2, // Opcode: STOCGAsmE + /* 18809 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 18824 + /* 18814 */ MCD_OPC_CheckPredicate, + 22, + 80, + 0, + 0, // Skip to: 18899 + /* 18819 */ MCD_OPC_Decode, + 242, + 17, + 194, + 2, // Opcode: STOCGAsmNLH + /* 18824 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 18839 + /* 18829 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 18899 + /* 18834 */ MCD_OPC_Decode, + 232, + 17, + 194, + 2, // Opcode: STOCGAsmHE + /* 18839 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 18854 + /* 18844 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 18899 + /* 18849 */ MCD_OPC_Decode, + 240, + 17, + 194, + 2, // Opcode: STOCGAsmNL + /* 18854 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 18869 + /* 18859 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 18899 + /* 18864 */ MCD_OPC_Decode, + 234, + 17, + 194, + 2, // Opcode: STOCGAsmLE + /* 18869 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 18884 + /* 18874 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 18899 + /* 18879 */ MCD_OPC_Decode, + 238, + 17, + 194, + 2, // Opcode: STOCGAsmNH + /* 18884 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 18899 + /* 18889 */ MCD_OPC_CheckPredicate, + 22, + 5, + 0, + 0, // Skip to: 18899 + /* 18894 */ MCD_OPC_Decode, + 244, + 17, + 194, + 2, // Opcode: STOCGAsmNO + /* 18899 */ MCD_OPC_CheckPredicate, + 22, + 244, + 16, + 0, // Skip to: 23244 + /* 18904 */ MCD_OPC_Decode, + 229, + 17, + 195, + 2, // Opcode: STOCGAsm + /* 18909 */ MCD_OPC_FilterValue, + 228, + 1, + 10, + 0, + 0, // Skip to: 18925 + /* 18915 */ MCD_OPC_CheckPredicate, + 25, + 228, + 16, + 0, // Skip to: 23244 + /* 18920 */ MCD_OPC_Decode, + 151, + 11, + 184, + 2, // Opcode: LANG + /* 18925 */ MCD_OPC_FilterValue, + 230, + 1, + 10, + 0, + 0, // Skip to: 18941 + /* 18931 */ MCD_OPC_CheckPredicate, + 25, + 212, + 16, + 0, // Skip to: 23244 + /* 18936 */ MCD_OPC_Decode, + 153, + 11, + 184, + 2, // Opcode: LAOG + /* 18941 */ MCD_OPC_FilterValue, + 231, + 1, + 10, + 0, + 0, // Skip to: 18957 + /* 18947 */ MCD_OPC_CheckPredicate, + 25, + 196, + 16, + 0, // Skip to: 23244 + /* 18952 */ MCD_OPC_Decode, + 158, + 11, + 184, + 2, // Opcode: LAXG + /* 18957 */ MCD_OPC_FilterValue, + 232, + 1, + 10, + 0, + 0, // Skip to: 18973 + /* 18963 */ MCD_OPC_CheckPredicate, + 25, + 180, + 16, + 0, // Skip to: 23244 + /* 18968 */ MCD_OPC_Decode, + 143, + 11, + 184, + 2, // Opcode: LAAG + /* 18973 */ MCD_OPC_FilterValue, + 234, + 1, + 10, + 0, + 0, // Skip to: 18989 + /* 18979 */ MCD_OPC_CheckPredicate, + 25, + 164, + 16, + 0, // Skip to: 23244 + /* 18984 */ MCD_OPC_Decode, + 145, + 11, + 184, + 2, // Opcode: LAALG + /* 18989 */ MCD_OPC_FilterValue, + 242, + 1, + 223, + 0, + 0, // Skip to: 19218 + /* 18995 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 18998 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 19013 + /* 19003 */ MCD_OPC_CheckPredicate, + 22, + 200, + 0, + 0, // Skip to: 19208 + /* 19008 */ MCD_OPC_Decode, + 165, + 12, + 213, + 2, // Opcode: LOCAsmO + /* 19013 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 19028 + /* 19018 */ MCD_OPC_CheckPredicate, + 22, + 185, + 0, + 0, // Skip to: 19208 + /* 19023 */ MCD_OPC_Decode, + 149, + 12, + 213, + 2, // Opcode: LOCAsmH + /* 19028 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 19043 + /* 19033 */ MCD_OPC_CheckPredicate, + 22, + 170, + 0, + 0, // Skip to: 19208 + /* 19038 */ MCD_OPC_Decode, + 159, + 12, + 213, + 2, // Opcode: LOCAsmNLE + /* 19043 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19058 + /* 19048 */ MCD_OPC_CheckPredicate, + 22, + 155, + 0, + 0, // Skip to: 19208 + /* 19053 */ MCD_OPC_Decode, + 151, + 12, + 213, + 2, // Opcode: LOCAsmL + /* 19058 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 19073 + /* 19063 */ MCD_OPC_CheckPredicate, + 22, + 140, + 0, + 0, // Skip to: 19208 + /* 19068 */ MCD_OPC_Decode, + 157, + 12, + 213, + 2, // Opcode: LOCAsmNHE + /* 19073 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 19088 + /* 19078 */ MCD_OPC_CheckPredicate, + 22, + 125, + 0, + 0, // Skip to: 19208 + /* 19083 */ MCD_OPC_Decode, + 153, + 12, + 213, + 2, // Opcode: LOCAsmLH + /* 19088 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 19103 + /* 19093 */ MCD_OPC_CheckPredicate, + 22, + 110, + 0, + 0, // Skip to: 19208 + /* 19098 */ MCD_OPC_Decode, + 155, + 12, + 213, + 2, // Opcode: LOCAsmNE + /* 19103 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 19118 + /* 19108 */ MCD_OPC_CheckPredicate, + 22, + 95, + 0, + 0, // Skip to: 19208 + /* 19113 */ MCD_OPC_Decode, + 148, + 12, + 213, + 2, // Opcode: LOCAsmE + /* 19118 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 19133 + /* 19123 */ MCD_OPC_CheckPredicate, + 22, + 80, + 0, + 0, // Skip to: 19208 + /* 19128 */ MCD_OPC_Decode, + 160, + 12, + 213, + 2, // Opcode: LOCAsmNLH + /* 19133 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 19148 + /* 19138 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 19208 + /* 19143 */ MCD_OPC_Decode, + 150, + 12, + 213, + 2, // Opcode: LOCAsmHE + /* 19148 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 19163 + /* 19153 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 19208 + /* 19158 */ MCD_OPC_Decode, + 158, + 12, + 213, + 2, // Opcode: LOCAsmNL + /* 19163 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 19178 + /* 19168 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 19208 + /* 19173 */ MCD_OPC_Decode, + 152, + 12, + 213, + 2, // Opcode: LOCAsmLE + /* 19178 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 19193 + /* 19183 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 19208 + /* 19188 */ MCD_OPC_Decode, + 156, + 12, + 213, + 2, // Opcode: LOCAsmNH + /* 19193 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 19208 + /* 19198 */ MCD_OPC_CheckPredicate, + 22, + 5, + 0, + 0, // Skip to: 19208 + /* 19203 */ MCD_OPC_Decode, + 162, + 12, + 213, + 2, // Opcode: LOCAsmNO + /* 19208 */ MCD_OPC_CheckPredicate, + 22, + 191, + 15, + 0, // Skip to: 23244 + /* 19213 */ MCD_OPC_Decode, + 147, + 12, + 214, + 2, // Opcode: LOCAsm + /* 19218 */ MCD_OPC_FilterValue, + 243, + 1, + 223, + 0, + 0, // Skip to: 19447 + /* 19224 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 19227 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 19242 + /* 19232 */ MCD_OPC_CheckPredicate, + 22, + 200, + 0, + 0, // Skip to: 19437 + /* 19237 */ MCD_OPC_Decode, + 203, + 17, + 190, + 2, // Opcode: STOCAsmO + /* 19242 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 19257 + /* 19247 */ MCD_OPC_CheckPredicate, + 22, + 185, + 0, + 0, // Skip to: 19437 + /* 19252 */ MCD_OPC_Decode, + 187, + 17, + 190, + 2, // Opcode: STOCAsmH + /* 19257 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 19272 + /* 19262 */ MCD_OPC_CheckPredicate, + 22, + 170, + 0, + 0, // Skip to: 19437 + /* 19267 */ MCD_OPC_Decode, + 197, + 17, + 190, + 2, // Opcode: STOCAsmNLE + /* 19272 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19287 + /* 19277 */ MCD_OPC_CheckPredicate, + 22, + 155, + 0, + 0, // Skip to: 19437 + /* 19282 */ MCD_OPC_Decode, + 189, + 17, + 190, + 2, // Opcode: STOCAsmL + /* 19287 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 19302 + /* 19292 */ MCD_OPC_CheckPredicate, + 22, + 140, + 0, + 0, // Skip to: 19437 + /* 19297 */ MCD_OPC_Decode, + 195, + 17, + 190, + 2, // Opcode: STOCAsmNHE + /* 19302 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 19317 + /* 19307 */ MCD_OPC_CheckPredicate, + 22, + 125, + 0, + 0, // Skip to: 19437 + /* 19312 */ MCD_OPC_Decode, + 191, + 17, + 190, + 2, // Opcode: STOCAsmLH + /* 19317 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 19332 + /* 19322 */ MCD_OPC_CheckPredicate, + 22, + 110, + 0, + 0, // Skip to: 19437 + /* 19327 */ MCD_OPC_Decode, + 193, + 17, + 190, + 2, // Opcode: STOCAsmNE + /* 19332 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 19347 + /* 19337 */ MCD_OPC_CheckPredicate, + 22, + 95, + 0, + 0, // Skip to: 19437 + /* 19342 */ MCD_OPC_Decode, + 186, + 17, + 190, + 2, // Opcode: STOCAsmE + /* 19347 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 19362 + /* 19352 */ MCD_OPC_CheckPredicate, + 22, + 80, + 0, + 0, // Skip to: 19437 + /* 19357 */ MCD_OPC_Decode, + 198, + 17, + 190, + 2, // Opcode: STOCAsmNLH + /* 19362 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 19377 + /* 19367 */ MCD_OPC_CheckPredicate, + 22, + 65, + 0, + 0, // Skip to: 19437 + /* 19372 */ MCD_OPC_Decode, + 188, + 17, + 190, + 2, // Opcode: STOCAsmHE + /* 19377 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 19392 + /* 19382 */ MCD_OPC_CheckPredicate, + 22, + 50, + 0, + 0, // Skip to: 19437 + /* 19387 */ MCD_OPC_Decode, + 196, + 17, + 190, + 2, // Opcode: STOCAsmNL + /* 19392 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 19407 + /* 19397 */ MCD_OPC_CheckPredicate, + 22, + 35, + 0, + 0, // Skip to: 19437 + /* 19402 */ MCD_OPC_Decode, + 190, + 17, + 190, + 2, // Opcode: STOCAsmLE + /* 19407 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 19422 + /* 19412 */ MCD_OPC_CheckPredicate, + 22, + 20, + 0, + 0, // Skip to: 19437 + /* 19417 */ MCD_OPC_Decode, + 194, + 17, + 190, + 2, // Opcode: STOCAsmNH + /* 19422 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 19437 + /* 19427 */ MCD_OPC_CheckPredicate, + 22, + 5, + 0, + 0, // Skip to: 19437 + /* 19432 */ MCD_OPC_Decode, + 200, + 17, + 190, + 2, // Opcode: STOCAsmNO + /* 19437 */ MCD_OPC_CheckPredicate, + 22, + 218, + 14, + 0, // Skip to: 23244 + /* 19442 */ MCD_OPC_Decode, + 185, + 17, + 191, + 2, // Opcode: STOCAsm + /* 19447 */ MCD_OPC_FilterValue, + 244, + 1, + 10, + 0, + 0, // Skip to: 19463 + /* 19453 */ MCD_OPC_CheckPredicate, + 25, + 202, + 14, + 0, // Skip to: 23244 + /* 19458 */ MCD_OPC_Decode, + 150, + 11, + 204, + 2, // Opcode: LAN + /* 19463 */ MCD_OPC_FilterValue, + 246, + 1, + 10, + 0, + 0, // Skip to: 19479 + /* 19469 */ MCD_OPC_CheckPredicate, + 25, + 186, + 14, + 0, // Skip to: 23244 + /* 19474 */ MCD_OPC_Decode, + 152, + 11, + 204, + 2, // Opcode: LAO + /* 19479 */ MCD_OPC_FilterValue, + 247, + 1, + 10, + 0, + 0, // Skip to: 19495 + /* 19485 */ MCD_OPC_CheckPredicate, + 25, + 170, + 14, + 0, // Skip to: 23244 + /* 19490 */ MCD_OPC_Decode, + 157, + 11, + 204, + 2, // Opcode: LAX + /* 19495 */ MCD_OPC_FilterValue, + 248, + 1, + 10, + 0, + 0, // Skip to: 19511 + /* 19501 */ MCD_OPC_CheckPredicate, + 25, + 154, + 14, + 0, // Skip to: 23244 + /* 19506 */ MCD_OPC_Decode, + 142, + 11, + 204, + 2, // Opcode: LAA + /* 19511 */ MCD_OPC_FilterValue, + 250, + 1, + 143, + 14, + 0, // Skip to: 23244 + /* 19517 */ MCD_OPC_CheckPredicate, + 25, + 138, + 14, + 0, // Skip to: 23244 + /* 19522 */ MCD_OPC_Decode, + 144, + 11, + 204, + 2, // Opcode: LAAL + /* 19527 */ MCD_OPC_FilterValue, + 236, + 1, + 214, + 9, + 0, // Skip to: 22051 + /* 19533 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 19536 */ MCD_OPC_FilterValue, + 66, + 231, + 0, + 0, // Skip to: 19772 + /* 19541 */ MCD_OPC_ExtractField, + 8, + 8, // Inst{15-8} ... + /* 19544 */ MCD_OPC_FilterValue, + 0, + 111, + 14, + 0, // Skip to: 23244 + /* 19549 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 19552 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 19567 + /* 19557 */ MCD_OPC_CheckPredicate, + 20, + 200, + 0, + 0, // Skip to: 19762 + /* 19562 */ MCD_OPC_Decode, + 191, + 13, + 215, + 2, // Opcode: LOCHIAsmO + /* 19567 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 19582 + /* 19572 */ MCD_OPC_CheckPredicate, + 20, + 185, + 0, + 0, // Skip to: 19762 + /* 19577 */ MCD_OPC_Decode, + 175, + 13, + 215, + 2, // Opcode: LOCHIAsmH + /* 19582 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 19597 + /* 19587 */ MCD_OPC_CheckPredicate, + 20, + 170, + 0, + 0, // Skip to: 19762 + /* 19592 */ MCD_OPC_Decode, + 185, + 13, + 215, + 2, // Opcode: LOCHIAsmNLE + /* 19597 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19612 + /* 19602 */ MCD_OPC_CheckPredicate, + 20, + 155, + 0, + 0, // Skip to: 19762 + /* 19607 */ MCD_OPC_Decode, + 177, + 13, + 215, + 2, // Opcode: LOCHIAsmL + /* 19612 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 19627 + /* 19617 */ MCD_OPC_CheckPredicate, + 20, + 140, + 0, + 0, // Skip to: 19762 + /* 19622 */ MCD_OPC_Decode, + 183, + 13, + 215, + 2, // Opcode: LOCHIAsmNHE + /* 19627 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 19642 + /* 19632 */ MCD_OPC_CheckPredicate, + 20, + 125, + 0, + 0, // Skip to: 19762 + /* 19637 */ MCD_OPC_Decode, + 179, + 13, + 215, + 2, // Opcode: LOCHIAsmLH + /* 19642 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 19657 + /* 19647 */ MCD_OPC_CheckPredicate, + 20, + 110, + 0, + 0, // Skip to: 19762 + /* 19652 */ MCD_OPC_Decode, + 181, + 13, + 215, + 2, // Opcode: LOCHIAsmNE + /* 19657 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 19672 + /* 19662 */ MCD_OPC_CheckPredicate, + 20, + 95, + 0, + 0, // Skip to: 19762 + /* 19667 */ MCD_OPC_Decode, + 174, + 13, + 215, + 2, // Opcode: LOCHIAsmE + /* 19672 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 19687 + /* 19677 */ MCD_OPC_CheckPredicate, + 20, + 80, + 0, + 0, // Skip to: 19762 + /* 19682 */ MCD_OPC_Decode, + 186, + 13, + 215, + 2, // Opcode: LOCHIAsmNLH + /* 19687 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 19702 + /* 19692 */ MCD_OPC_CheckPredicate, + 20, + 65, + 0, + 0, // Skip to: 19762 + /* 19697 */ MCD_OPC_Decode, + 176, + 13, + 215, + 2, // Opcode: LOCHIAsmHE + /* 19702 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 19717 + /* 19707 */ MCD_OPC_CheckPredicate, + 20, + 50, + 0, + 0, // Skip to: 19762 + /* 19712 */ MCD_OPC_Decode, + 184, + 13, + 215, + 2, // Opcode: LOCHIAsmNL + /* 19717 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 19732 + /* 19722 */ MCD_OPC_CheckPredicate, + 20, + 35, + 0, + 0, // Skip to: 19762 + /* 19727 */ MCD_OPC_Decode, + 178, + 13, + 215, + 2, // Opcode: LOCHIAsmLE + /* 19732 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 19747 + /* 19737 */ MCD_OPC_CheckPredicate, + 20, + 20, + 0, + 0, // Skip to: 19762 + /* 19742 */ MCD_OPC_Decode, + 182, + 13, + 215, + 2, // Opcode: LOCHIAsmNH + /* 19747 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 19762 + /* 19752 */ MCD_OPC_CheckPredicate, + 20, + 5, + 0, + 0, // Skip to: 19762 + /* 19757 */ MCD_OPC_Decode, + 188, + 13, + 215, + 2, // Opcode: LOCHIAsmNO + /* 19762 */ MCD_OPC_CheckPredicate, + 20, + 149, + 13, + 0, // Skip to: 23244 + /* 19767 */ MCD_OPC_Decode, + 173, + 13, + 216, + 2, // Opcode: LOCHIAsm + /* 19772 */ MCD_OPC_FilterValue, + 68, + 12, + 0, + 0, // Skip to: 19789 + /* 19777 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 132, + 13, + 0, // Skip to: 23244 + /* 19784 */ MCD_OPC_Decode, + 152, + 5, + 217, + 2, // Opcode: BRXHG + /* 19789 */ MCD_OPC_FilterValue, + 69, + 12, + 0, + 0, // Skip to: 19806 + /* 19794 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 115, + 13, + 0, // Skip to: 23244 + /* 19801 */ MCD_OPC_Decode, + 154, + 5, + 217, + 2, // Opcode: BRXLG + /* 19806 */ MCD_OPC_FilterValue, + 70, + 231, + 0, + 0, // Skip to: 20042 + /* 19811 */ MCD_OPC_ExtractField, + 8, + 8, // Inst{15-8} ... + /* 19814 */ MCD_OPC_FilterValue, + 0, + 97, + 13, + 0, // Skip to: 23244 + /* 19819 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 19822 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 19837 + /* 19827 */ MCD_OPC_CheckPredicate, + 20, + 200, + 0, + 0, // Skip to: 20032 + /* 19832 */ MCD_OPC_Decode, + 253, + 12, + 218, + 2, // Opcode: LOCGHIAsmO + /* 19837 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 19852 + /* 19842 */ MCD_OPC_CheckPredicate, + 20, + 185, + 0, + 0, // Skip to: 20032 + /* 19847 */ MCD_OPC_Decode, + 237, + 12, + 218, + 2, // Opcode: LOCGHIAsmH + /* 19852 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 19867 + /* 19857 */ MCD_OPC_CheckPredicate, + 20, + 170, + 0, + 0, // Skip to: 20032 + /* 19862 */ MCD_OPC_Decode, + 247, + 12, + 218, + 2, // Opcode: LOCGHIAsmNLE + /* 19867 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 19882 + /* 19872 */ MCD_OPC_CheckPredicate, + 20, + 155, + 0, + 0, // Skip to: 20032 + /* 19877 */ MCD_OPC_Decode, + 239, + 12, + 218, + 2, // Opcode: LOCGHIAsmL + /* 19882 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 19897 + /* 19887 */ MCD_OPC_CheckPredicate, + 20, + 140, + 0, + 0, // Skip to: 20032 + /* 19892 */ MCD_OPC_Decode, + 245, + 12, + 218, + 2, // Opcode: LOCGHIAsmNHE + /* 19897 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 19912 + /* 19902 */ MCD_OPC_CheckPredicate, + 20, + 125, + 0, + 0, // Skip to: 20032 + /* 19907 */ MCD_OPC_Decode, + 241, + 12, + 218, + 2, // Opcode: LOCGHIAsmLH + /* 19912 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 19927 + /* 19917 */ MCD_OPC_CheckPredicate, + 20, + 110, + 0, + 0, // Skip to: 20032 + /* 19922 */ MCD_OPC_Decode, + 243, + 12, + 218, + 2, // Opcode: LOCGHIAsmNE + /* 19927 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 19942 + /* 19932 */ MCD_OPC_CheckPredicate, + 20, + 95, + 0, + 0, // Skip to: 20032 + /* 19937 */ MCD_OPC_Decode, + 236, + 12, + 218, + 2, // Opcode: LOCGHIAsmE + /* 19942 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 19957 + /* 19947 */ MCD_OPC_CheckPredicate, + 20, + 80, + 0, + 0, // Skip to: 20032 + /* 19952 */ MCD_OPC_Decode, + 248, + 12, + 218, + 2, // Opcode: LOCGHIAsmNLH + /* 19957 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 19972 + /* 19962 */ MCD_OPC_CheckPredicate, + 20, + 65, + 0, + 0, // Skip to: 20032 + /* 19967 */ MCD_OPC_Decode, + 238, + 12, + 218, + 2, // Opcode: LOCGHIAsmHE + /* 19972 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 19987 + /* 19977 */ MCD_OPC_CheckPredicate, + 20, + 50, + 0, + 0, // Skip to: 20032 + /* 19982 */ MCD_OPC_Decode, + 246, + 12, + 218, + 2, // Opcode: LOCGHIAsmNL + /* 19987 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 20002 + /* 19992 */ MCD_OPC_CheckPredicate, + 20, + 35, + 0, + 0, // Skip to: 20032 + /* 19997 */ MCD_OPC_Decode, + 240, + 12, + 218, + 2, // Opcode: LOCGHIAsmLE + /* 20002 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 20017 + /* 20007 */ MCD_OPC_CheckPredicate, + 20, + 20, + 0, + 0, // Skip to: 20032 + /* 20012 */ MCD_OPC_Decode, + 244, + 12, + 218, + 2, // Opcode: LOCGHIAsmNH + /* 20017 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 20032 + /* 20022 */ MCD_OPC_CheckPredicate, + 20, + 5, + 0, + 0, // Skip to: 20032 + /* 20027 */ MCD_OPC_Decode, + 250, + 12, + 218, + 2, // Opcode: LOCGHIAsmNO + /* 20032 */ MCD_OPC_CheckPredicate, + 20, + 135, + 12, + 0, // Skip to: 23244 + /* 20037 */ MCD_OPC_Decode, + 235, + 12, + 219, + 2, // Opcode: LOCGHIAsm + /* 20042 */ MCD_OPC_FilterValue, + 78, + 231, + 0, + 0, // Skip to: 20278 + /* 20047 */ MCD_OPC_ExtractField, + 8, + 8, // Inst{15-8} ... + /* 20050 */ MCD_OPC_FilterValue, + 0, + 117, + 12, + 0, // Skip to: 23244 + /* 20055 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 20058 */ MCD_OPC_FilterValue, + 1, + 10, + 0, + 0, // Skip to: 20073 + /* 20063 */ MCD_OPC_CheckPredicate, + 20, + 200, + 0, + 0, // Skip to: 20268 + /* 20068 */ MCD_OPC_Decode, + 169, + 13, + 220, + 2, // Opcode: LOCHHIAsmO + /* 20073 */ MCD_OPC_FilterValue, + 2, + 10, + 0, + 0, // Skip to: 20088 + /* 20078 */ MCD_OPC_CheckPredicate, + 20, + 185, + 0, + 0, // Skip to: 20268 + /* 20083 */ MCD_OPC_Decode, + 153, + 13, + 220, + 2, // Opcode: LOCHHIAsmH + /* 20088 */ MCD_OPC_FilterValue, + 3, + 10, + 0, + 0, // Skip to: 20103 + /* 20093 */ MCD_OPC_CheckPredicate, + 20, + 170, + 0, + 0, // Skip to: 20268 + /* 20098 */ MCD_OPC_Decode, + 163, + 13, + 220, + 2, // Opcode: LOCHHIAsmNLE + /* 20103 */ MCD_OPC_FilterValue, + 4, + 10, + 0, + 0, // Skip to: 20118 + /* 20108 */ MCD_OPC_CheckPredicate, + 20, + 155, + 0, + 0, // Skip to: 20268 + /* 20113 */ MCD_OPC_Decode, + 155, + 13, + 220, + 2, // Opcode: LOCHHIAsmL + /* 20118 */ MCD_OPC_FilterValue, + 5, + 10, + 0, + 0, // Skip to: 20133 + /* 20123 */ MCD_OPC_CheckPredicate, + 20, + 140, + 0, + 0, // Skip to: 20268 + /* 20128 */ MCD_OPC_Decode, + 161, + 13, + 220, + 2, // Opcode: LOCHHIAsmNHE + /* 20133 */ MCD_OPC_FilterValue, + 6, + 10, + 0, + 0, // Skip to: 20148 + /* 20138 */ MCD_OPC_CheckPredicate, + 20, + 125, + 0, + 0, // Skip to: 20268 + /* 20143 */ MCD_OPC_Decode, + 157, + 13, + 220, + 2, // Opcode: LOCHHIAsmLH + /* 20148 */ MCD_OPC_FilterValue, + 7, + 10, + 0, + 0, // Skip to: 20163 + /* 20153 */ MCD_OPC_CheckPredicate, + 20, + 110, + 0, + 0, // Skip to: 20268 + /* 20158 */ MCD_OPC_Decode, + 159, + 13, + 220, + 2, // Opcode: LOCHHIAsmNE + /* 20163 */ MCD_OPC_FilterValue, + 8, + 10, + 0, + 0, // Skip to: 20178 + /* 20168 */ MCD_OPC_CheckPredicate, + 20, + 95, + 0, + 0, // Skip to: 20268 + /* 20173 */ MCD_OPC_Decode, + 152, + 13, + 220, + 2, // Opcode: LOCHHIAsmE + /* 20178 */ MCD_OPC_FilterValue, + 9, + 10, + 0, + 0, // Skip to: 20193 + /* 20183 */ MCD_OPC_CheckPredicate, + 20, + 80, + 0, + 0, // Skip to: 20268 + /* 20188 */ MCD_OPC_Decode, + 164, + 13, + 220, + 2, // Opcode: LOCHHIAsmNLH + /* 20193 */ MCD_OPC_FilterValue, + 10, + 10, + 0, + 0, // Skip to: 20208 + /* 20198 */ MCD_OPC_CheckPredicate, + 20, + 65, + 0, + 0, // Skip to: 20268 + /* 20203 */ MCD_OPC_Decode, + 154, + 13, + 220, + 2, // Opcode: LOCHHIAsmHE + /* 20208 */ MCD_OPC_FilterValue, + 11, + 10, + 0, + 0, // Skip to: 20223 + /* 20213 */ MCD_OPC_CheckPredicate, + 20, + 50, + 0, + 0, // Skip to: 20268 + /* 20218 */ MCD_OPC_Decode, + 162, + 13, + 220, + 2, // Opcode: LOCHHIAsmNL + /* 20223 */ MCD_OPC_FilterValue, + 12, + 10, + 0, + 0, // Skip to: 20238 + /* 20228 */ MCD_OPC_CheckPredicate, + 20, + 35, + 0, + 0, // Skip to: 20268 + /* 20233 */ MCD_OPC_Decode, + 156, + 13, + 220, + 2, // Opcode: LOCHHIAsmLE + /* 20238 */ MCD_OPC_FilterValue, + 13, + 10, + 0, + 0, // Skip to: 20253 + /* 20243 */ MCD_OPC_CheckPredicate, + 20, + 20, + 0, + 0, // Skip to: 20268 + /* 20248 */ MCD_OPC_Decode, + 160, + 13, + 220, + 2, // Opcode: LOCHHIAsmNH + /* 20253 */ MCD_OPC_FilterValue, + 14, + 10, + 0, + 0, // Skip to: 20268 + /* 20258 */ MCD_OPC_CheckPredicate, + 20, + 5, + 0, + 0, // Skip to: 20268 + /* 20263 */ MCD_OPC_Decode, + 166, + 13, + 220, + 2, // Opcode: LOCHHIAsmNO + /* 20268 */ MCD_OPC_CheckPredicate, + 20, + 155, + 11, + 0, // Skip to: 23244 + /* 20273 */ MCD_OPC_Decode, + 151, + 13, + 221, + 2, // Opcode: LOCHHIAsm + /* 20278 */ MCD_OPC_FilterValue, + 81, + 10, + 0, + 0, // Skip to: 20293 + /* 20283 */ MCD_OPC_CheckPredicate, + 19, + 140, + 11, + 0, // Skip to: 23244 + /* 20288 */ MCD_OPC_Decode, + 216, + 15, + 222, + 2, // Opcode: RISBLG + /* 20293 */ MCD_OPC_FilterValue, + 84, + 5, + 0, + 0, // Skip to: 20303 + /* 20298 */ MCD_OPC_Decode, + 219, + 15, + 223, + 2, // Opcode: RNSBG + /* 20303 */ MCD_OPC_FilterValue, + 85, + 5, + 0, + 0, // Skip to: 20313 + /* 20308 */ MCD_OPC_Decode, + 212, + 15, + 223, + 2, // Opcode: RISBG + /* 20313 */ MCD_OPC_FilterValue, + 86, + 5, + 0, + 0, // Skip to: 20323 + /* 20318 */ MCD_OPC_Decode, + 220, + 15, + 223, + 2, // Opcode: ROSBG + /* 20323 */ MCD_OPC_FilterValue, + 87, + 5, + 0, + 0, // Skip to: 20333 + /* 20328 */ MCD_OPC_Decode, + 227, + 15, + 223, + 2, // Opcode: RXSBG + /* 20333 */ MCD_OPC_FilterValue, + 89, + 10, + 0, + 0, // Skip to: 20348 + /* 20338 */ MCD_OPC_CheckPredicate, + 36, + 85, + 11, + 0, // Skip to: 23244 + /* 20343 */ MCD_OPC_Decode, + 214, + 15, + 223, + 2, // Opcode: RISBGN + /* 20348 */ MCD_OPC_FilterValue, + 93, + 10, + 0, + 0, // Skip to: 20363 + /* 20353 */ MCD_OPC_CheckPredicate, + 19, + 70, + 11, + 0, // Skip to: 23244 + /* 20358 */ MCD_OPC_Decode, + 215, + 15, + 224, + 2, // Opcode: RISBHG + /* 20363 */ MCD_OPC_FilterValue, + 100, + 76, + 0, + 0, // Skip to: 20444 + /* 20368 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 20371 */ MCD_OPC_FilterValue, + 0, + 52, + 11, + 0, // Skip to: 23244 + /* 20376 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 20379 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 20389 + /* 20384 */ MCD_OPC_Decode, + 164, + 6, + 225, + 2, // Opcode: CGRJAsmH + /* 20389 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 20399 + /* 20394 */ MCD_OPC_Decode, + 166, + 6, + 225, + 2, // Opcode: CGRJAsmL + /* 20399 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 20409 + /* 20404 */ MCD_OPC_Decode, + 168, + 6, + 225, + 2, // Opcode: CGRJAsmLH + /* 20409 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 20419 + /* 20414 */ MCD_OPC_Decode, + 163, + 6, + 225, + 2, // Opcode: CGRJAsmE + /* 20419 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 20429 + /* 20424 */ MCD_OPC_Decode, + 165, + 6, + 225, + 2, // Opcode: CGRJAsmHE + /* 20429 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 20439 + /* 20434 */ MCD_OPC_Decode, + 167, + 6, + 225, + 2, // Opcode: CGRJAsmLE + /* 20439 */ MCD_OPC_Decode, + 162, + 6, + 226, + 2, // Opcode: CGRJAsm + /* 20444 */ MCD_OPC_FilterValue, + 101, + 76, + 0, + 0, // Skip to: 20525 + /* 20449 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 20452 */ MCD_OPC_FilterValue, + 0, + 227, + 10, + 0, // Skip to: 23244 + /* 20457 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 20460 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 20470 + /* 20465 */ MCD_OPC_Decode, + 216, + 7, + 225, + 2, // Opcode: CLGRJAsmH + /* 20470 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 20480 + /* 20475 */ MCD_OPC_Decode, + 218, + 7, + 225, + 2, // Opcode: CLGRJAsmL + /* 20480 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 20490 + /* 20485 */ MCD_OPC_Decode, + 220, + 7, + 225, + 2, // Opcode: CLGRJAsmLH + /* 20490 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 20500 + /* 20495 */ MCD_OPC_Decode, + 215, + 7, + 225, + 2, // Opcode: CLGRJAsmE + /* 20500 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 20510 + /* 20505 */ MCD_OPC_Decode, + 217, + 7, + 225, + 2, // Opcode: CLGRJAsmHE + /* 20510 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 20520 + /* 20515 */ MCD_OPC_Decode, + 219, + 7, + 225, + 2, // Opcode: CLGRJAsmLE + /* 20520 */ MCD_OPC_Decode, + 214, + 7, + 226, + 2, // Opcode: CLGRJAsm + /* 20525 */ MCD_OPC_FilterValue, + 112, + 84, + 0, + 0, // Skip to: 20614 + /* 20530 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 20533 */ MCD_OPC_FilterValue, + 0, + 146, + 10, + 0, // Skip to: 23244 + /* 20538 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 20541 */ MCD_OPC_FilterValue, + 0, + 138, + 10, + 0, // Skip to: 23244 + /* 20546 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 20549 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 20559 + /* 20554 */ MCD_OPC_Decode, + 135, + 6, + 227, + 2, // Opcode: CGITAsmH + /* 20559 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 20569 + /* 20564 */ MCD_OPC_Decode, + 137, + 6, + 227, + 2, // Opcode: CGITAsmL + /* 20569 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 20579 + /* 20574 */ MCD_OPC_Decode, + 139, + 6, + 227, + 2, // Opcode: CGITAsmLH + /* 20579 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 20589 + /* 20584 */ MCD_OPC_Decode, + 134, + 6, + 227, + 2, // Opcode: CGITAsmE + /* 20589 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 20599 + /* 20594 */ MCD_OPC_Decode, + 136, + 6, + 227, + 2, // Opcode: CGITAsmHE + /* 20599 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 20609 + /* 20604 */ MCD_OPC_Decode, + 138, + 6, + 227, + 2, // Opcode: CGITAsmLE + /* 20609 */ MCD_OPC_Decode, + 133, + 6, + 228, + 2, // Opcode: CGITAsm + /* 20614 */ MCD_OPC_FilterValue, + 113, + 84, + 0, + 0, // Skip to: 20703 + /* 20619 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 20622 */ MCD_OPC_FilterValue, + 0, + 57, + 10, + 0, // Skip to: 23244 + /* 20627 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 20630 */ MCD_OPC_FilterValue, + 0, + 49, + 10, + 0, // Skip to: 23244 + /* 20635 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 20638 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 20648 + /* 20643 */ MCD_OPC_Decode, + 187, + 7, + 229, + 2, // Opcode: CLGITAsmH + /* 20648 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 20658 + /* 20653 */ MCD_OPC_Decode, + 189, + 7, + 229, + 2, // Opcode: CLGITAsmL + /* 20658 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 20668 + /* 20663 */ MCD_OPC_Decode, + 191, + 7, + 229, + 2, // Opcode: CLGITAsmLH + /* 20668 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 20678 + /* 20673 */ MCD_OPC_Decode, + 186, + 7, + 229, + 2, // Opcode: CLGITAsmE + /* 20678 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 20688 + /* 20683 */ MCD_OPC_Decode, + 188, + 7, + 229, + 2, // Opcode: CLGITAsmHE + /* 20688 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 20698 + /* 20693 */ MCD_OPC_Decode, + 190, + 7, + 229, + 2, // Opcode: CLGITAsmLE + /* 20698 */ MCD_OPC_Decode, + 185, + 7, + 230, + 2, // Opcode: CLGITAsm + /* 20703 */ MCD_OPC_FilterValue, + 114, + 84, + 0, + 0, // Skip to: 20792 + /* 20708 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 20711 */ MCD_OPC_FilterValue, + 0, + 224, + 9, + 0, // Skip to: 23244 + /* 20716 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 20719 */ MCD_OPC_FilterValue, + 0, + 216, + 9, + 0, // Skip to: 23244 + /* 20724 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 20727 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 20737 + /* 20732 */ MCD_OPC_Decode, + 236, + 6, + 231, + 2, // Opcode: CITAsmH + /* 20737 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 20747 + /* 20742 */ MCD_OPC_Decode, + 238, + 6, + 231, + 2, // Opcode: CITAsmL + /* 20747 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 20757 + /* 20752 */ MCD_OPC_Decode, + 240, + 6, + 231, + 2, // Opcode: CITAsmLH + /* 20757 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 20767 + /* 20762 */ MCD_OPC_Decode, + 235, + 6, + 231, + 2, // Opcode: CITAsmE + /* 20767 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 20777 + /* 20772 */ MCD_OPC_Decode, + 237, + 6, + 231, + 2, // Opcode: CITAsmHE + /* 20777 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 20787 + /* 20782 */ MCD_OPC_Decode, + 239, + 6, + 231, + 2, // Opcode: CITAsmLE + /* 20787 */ MCD_OPC_Decode, + 234, + 6, + 232, + 2, // Opcode: CITAsm + /* 20792 */ MCD_OPC_FilterValue, + 115, + 84, + 0, + 0, // Skip to: 20881 + /* 20797 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 20800 */ MCD_OPC_FilterValue, + 0, + 135, + 9, + 0, // Skip to: 23244 + /* 20805 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 20808 */ MCD_OPC_FilterValue, + 0, + 127, + 9, + 0, // Skip to: 23244 + /* 20813 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 20816 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 20826 + /* 20821 */ MCD_OPC_Decode, + 133, + 7, + 233, + 2, // Opcode: CLFITAsmH + /* 20826 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 20836 + /* 20831 */ MCD_OPC_Decode, + 135, + 7, + 233, + 2, // Opcode: CLFITAsmL + /* 20836 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 20846 + /* 20841 */ MCD_OPC_Decode, + 137, + 7, + 233, + 2, // Opcode: CLFITAsmLH + /* 20846 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 20856 + /* 20851 */ MCD_OPC_Decode, + 132, + 7, + 233, + 2, // Opcode: CLFITAsmE + /* 20856 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 20866 + /* 20861 */ MCD_OPC_Decode, + 134, + 7, + 233, + 2, // Opcode: CLFITAsmHE + /* 20866 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 20876 + /* 20871 */ MCD_OPC_Decode, + 136, + 7, + 233, + 2, // Opcode: CLFITAsmLE + /* 20876 */ MCD_OPC_Decode, + 131, + 7, + 234, + 2, // Opcode: CLFITAsm + /* 20881 */ MCD_OPC_FilterValue, + 118, + 76, + 0, + 0, // Skip to: 20962 + /* 20886 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 20889 */ MCD_OPC_FilterValue, + 0, + 46, + 9, + 0, // Skip to: 23244 + /* 20894 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 20897 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 20907 + /* 20902 */ MCD_OPC_Decode, + 130, + 9, + 235, + 2, // Opcode: CRJAsmH + /* 20907 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 20917 + /* 20912 */ MCD_OPC_Decode, + 132, + 9, + 235, + 2, // Opcode: CRJAsmL + /* 20917 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 20927 + /* 20922 */ MCD_OPC_Decode, + 134, + 9, + 235, + 2, // Opcode: CRJAsmLH + /* 20927 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 20937 + /* 20932 */ MCD_OPC_Decode, + 129, + 9, + 235, + 2, // Opcode: CRJAsmE + /* 20937 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 20947 + /* 20942 */ MCD_OPC_Decode, + 131, + 9, + 235, + 2, // Opcode: CRJAsmHE + /* 20947 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 20957 + /* 20952 */ MCD_OPC_Decode, + 133, + 9, + 235, + 2, // Opcode: CRJAsmLE + /* 20957 */ MCD_OPC_Decode, + 128, + 9, + 236, + 2, // Opcode: CRJAsm + /* 20962 */ MCD_OPC_FilterValue, + 119, + 76, + 0, + 0, // Skip to: 21043 + /* 20967 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 20970 */ MCD_OPC_FilterValue, + 0, + 221, + 8, + 0, // Skip to: 23244 + /* 20975 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 20978 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 20988 + /* 20983 */ MCD_OPC_Decode, + 187, + 8, + 235, + 2, // Opcode: CLRJAsmH + /* 20988 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 20998 + /* 20993 */ MCD_OPC_Decode, + 189, + 8, + 235, + 2, // Opcode: CLRJAsmL + /* 20998 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21008 + /* 21003 */ MCD_OPC_Decode, + 191, + 8, + 235, + 2, // Opcode: CLRJAsmLH + /* 21008 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21018 + /* 21013 */ MCD_OPC_Decode, + 186, + 8, + 235, + 2, // Opcode: CLRJAsmE + /* 21018 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21028 + /* 21023 */ MCD_OPC_Decode, + 188, + 8, + 235, + 2, // Opcode: CLRJAsmHE + /* 21028 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21038 + /* 21033 */ MCD_OPC_Decode, + 190, + 8, + 235, + 2, // Opcode: CLRJAsmLE + /* 21038 */ MCD_OPC_Decode, + 185, + 8, + 236, + 2, // Opcode: CLRJAsm + /* 21043 */ MCD_OPC_FilterValue, + 124, + 68, + 0, + 0, // Skip to: 21116 + /* 21048 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 21051 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21061 + /* 21056 */ MCD_OPC_Decode, + 249, + 5, + 237, + 2, // Opcode: CGIJAsmH + /* 21061 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21071 + /* 21066 */ MCD_OPC_Decode, + 251, + 5, + 237, + 2, // Opcode: CGIJAsmL + /* 21071 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21081 + /* 21076 */ MCD_OPC_Decode, + 253, + 5, + 237, + 2, // Opcode: CGIJAsmLH + /* 21081 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21091 + /* 21086 */ MCD_OPC_Decode, + 248, + 5, + 237, + 2, // Opcode: CGIJAsmE + /* 21091 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21101 + /* 21096 */ MCD_OPC_Decode, + 250, + 5, + 237, + 2, // Opcode: CGIJAsmHE + /* 21101 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21111 + /* 21106 */ MCD_OPC_Decode, + 252, + 5, + 237, + 2, // Opcode: CGIJAsmLE + /* 21111 */ MCD_OPC_Decode, + 247, + 5, + 238, + 2, // Opcode: CGIJAsm + /* 21116 */ MCD_OPC_FilterValue, + 125, + 68, + 0, + 0, // Skip to: 21189 + /* 21121 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 21124 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21134 + /* 21129 */ MCD_OPC_Decode, + 173, + 7, + 239, + 2, // Opcode: CLGIJAsmH + /* 21134 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21144 + /* 21139 */ MCD_OPC_Decode, + 175, + 7, + 239, + 2, // Opcode: CLGIJAsmL + /* 21144 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21154 + /* 21149 */ MCD_OPC_Decode, + 177, + 7, + 239, + 2, // Opcode: CLGIJAsmLH + /* 21154 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21164 + /* 21159 */ MCD_OPC_Decode, + 172, + 7, + 239, + 2, // Opcode: CLGIJAsmE + /* 21164 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21174 + /* 21169 */ MCD_OPC_Decode, + 174, + 7, + 239, + 2, // Opcode: CLGIJAsmHE + /* 21174 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21184 + /* 21179 */ MCD_OPC_Decode, + 176, + 7, + 239, + 2, // Opcode: CLGIJAsmLE + /* 21184 */ MCD_OPC_Decode, + 171, + 7, + 240, + 2, // Opcode: CLGIJAsm + /* 21189 */ MCD_OPC_FilterValue, + 126, + 68, + 0, + 0, // Skip to: 21262 + /* 21194 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 21197 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21207 + /* 21202 */ MCD_OPC_Decode, + 222, + 6, + 241, + 2, // Opcode: CIJAsmH + /* 21207 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21217 + /* 21212 */ MCD_OPC_Decode, + 224, + 6, + 241, + 2, // Opcode: CIJAsmL + /* 21217 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21227 + /* 21222 */ MCD_OPC_Decode, + 226, + 6, + 241, + 2, // Opcode: CIJAsmLH + /* 21227 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21237 + /* 21232 */ MCD_OPC_Decode, + 221, + 6, + 241, + 2, // Opcode: CIJAsmE + /* 21237 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21247 + /* 21242 */ MCD_OPC_Decode, + 223, + 6, + 241, + 2, // Opcode: CIJAsmHE + /* 21247 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21257 + /* 21252 */ MCD_OPC_Decode, + 225, + 6, + 241, + 2, // Opcode: CIJAsmLE + /* 21257 */ MCD_OPC_Decode, + 220, + 6, + 242, + 2, // Opcode: CIJAsm + /* 21262 */ MCD_OPC_FilterValue, + 127, + 68, + 0, + 0, // Skip to: 21335 + /* 21267 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 21270 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21280 + /* 21275 */ MCD_OPC_Decode, + 154, + 8, + 243, + 2, // Opcode: CLIJAsmH + /* 21280 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21290 + /* 21285 */ MCD_OPC_Decode, + 156, + 8, + 243, + 2, // Opcode: CLIJAsmL + /* 21290 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21300 + /* 21295 */ MCD_OPC_Decode, + 158, + 8, + 243, + 2, // Opcode: CLIJAsmLH + /* 21300 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21310 + /* 21305 */ MCD_OPC_Decode, + 153, + 8, + 243, + 2, // Opcode: CLIJAsmE + /* 21310 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21320 + /* 21315 */ MCD_OPC_Decode, + 155, + 8, + 243, + 2, // Opcode: CLIJAsmHE + /* 21320 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21330 + /* 21325 */ MCD_OPC_Decode, + 157, + 8, + 243, + 2, // Opcode: CLIJAsmLE + /* 21330 */ MCD_OPC_Decode, + 152, + 8, + 244, + 2, // Opcode: CLIJAsm + /* 21335 */ MCD_OPC_FilterValue, + 216, + 1, + 17, + 0, + 0, // Skip to: 21358 + /* 21341 */ MCD_OPC_CheckPredicate, + 23, + 106, + 7, + 0, // Skip to: 23244 + /* 21346 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 99, + 7, + 0, // Skip to: 23244 + /* 21353 */ MCD_OPC_Decode, + 150, + 4, + 245, + 2, // Opcode: AHIK + /* 21358 */ MCD_OPC_FilterValue, + 217, + 1, + 17, + 0, + 0, // Skip to: 21381 + /* 21364 */ MCD_OPC_CheckPredicate, + 23, + 83, + 7, + 0, // Skip to: 23244 + /* 21369 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 76, + 7, + 0, // Skip to: 23244 + /* 21376 */ MCD_OPC_Decode, + 142, + 4, + 246, + 2, // Opcode: AGHIK + /* 21381 */ MCD_OPC_FilterValue, + 218, + 1, + 17, + 0, + 0, // Skip to: 21404 + /* 21387 */ MCD_OPC_CheckPredicate, + 23, + 60, + 7, + 0, // Skip to: 23244 + /* 21392 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 53, + 7, + 0, // Skip to: 23244 + /* 21399 */ MCD_OPC_Decode, + 169, + 4, + 245, + 2, // Opcode: ALHSIK + /* 21404 */ MCD_OPC_FilterValue, + 219, + 1, + 17, + 0, + 0, // Skip to: 21427 + /* 21410 */ MCD_OPC_CheckPredicate, + 23, + 37, + 7, + 0, // Skip to: 23244 + /* 21415 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 30, + 7, + 0, // Skip to: 23244 + /* 21422 */ MCD_OPC_Decode, + 163, + 4, + 246, + 2, // Opcode: ALGHSIK + /* 21427 */ MCD_OPC_FilterValue, + 228, + 1, + 76, + 0, + 0, // Skip to: 21509 + /* 21433 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 21436 */ MCD_OPC_FilterValue, + 0, + 11, + 7, + 0, // Skip to: 23244 + /* 21441 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 21444 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21454 + /* 21449 */ MCD_OPC_Decode, + 150, + 6, + 247, + 2, // Opcode: CGRBAsmH + /* 21454 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21464 + /* 21459 */ MCD_OPC_Decode, + 152, + 6, + 247, + 2, // Opcode: CGRBAsmL + /* 21464 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21474 + /* 21469 */ MCD_OPC_Decode, + 154, + 6, + 247, + 2, // Opcode: CGRBAsmLH + /* 21474 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21484 + /* 21479 */ MCD_OPC_Decode, + 149, + 6, + 247, + 2, // Opcode: CGRBAsmE + /* 21484 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21494 + /* 21489 */ MCD_OPC_Decode, + 151, + 6, + 247, + 2, // Opcode: CGRBAsmHE + /* 21494 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21504 + /* 21499 */ MCD_OPC_Decode, + 153, + 6, + 247, + 2, // Opcode: CGRBAsmLE + /* 21504 */ MCD_OPC_Decode, + 148, + 6, + 248, + 2, // Opcode: CGRBAsm + /* 21509 */ MCD_OPC_FilterValue, + 229, + 1, + 76, + 0, + 0, // Skip to: 21591 + /* 21515 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 21518 */ MCD_OPC_FilterValue, + 0, + 185, + 6, + 0, // Skip to: 23244 + /* 21523 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 21526 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21536 + /* 21531 */ MCD_OPC_Decode, + 202, + 7, + 247, + 2, // Opcode: CLGRBAsmH + /* 21536 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21546 + /* 21541 */ MCD_OPC_Decode, + 204, + 7, + 247, + 2, // Opcode: CLGRBAsmL + /* 21546 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21556 + /* 21551 */ MCD_OPC_Decode, + 206, + 7, + 247, + 2, // Opcode: CLGRBAsmLH + /* 21556 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21566 + /* 21561 */ MCD_OPC_Decode, + 201, + 7, + 247, + 2, // Opcode: CLGRBAsmE + /* 21566 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21576 + /* 21571 */ MCD_OPC_Decode, + 203, + 7, + 247, + 2, // Opcode: CLGRBAsmHE + /* 21576 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21586 + /* 21581 */ MCD_OPC_Decode, + 205, + 7, + 247, + 2, // Opcode: CLGRBAsmLE + /* 21586 */ MCD_OPC_Decode, + 200, + 7, + 248, + 2, // Opcode: CLGRBAsm + /* 21591 */ MCD_OPC_FilterValue, + 246, + 1, + 76, + 0, + 0, // Skip to: 21673 + /* 21597 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 21600 */ MCD_OPC_FilterValue, + 0, + 103, + 6, + 0, // Skip to: 23244 + /* 21605 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 21608 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21618 + /* 21613 */ MCD_OPC_Decode, + 242, + 8, + 249, + 2, // Opcode: CRBAsmH + /* 21618 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21628 + /* 21623 */ MCD_OPC_Decode, + 244, + 8, + 249, + 2, // Opcode: CRBAsmL + /* 21628 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21638 + /* 21633 */ MCD_OPC_Decode, + 246, + 8, + 249, + 2, // Opcode: CRBAsmLH + /* 21638 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21648 + /* 21643 */ MCD_OPC_Decode, + 241, + 8, + 249, + 2, // Opcode: CRBAsmE + /* 21648 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21658 + /* 21653 */ MCD_OPC_Decode, + 243, + 8, + 249, + 2, // Opcode: CRBAsmHE + /* 21658 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21668 + /* 21663 */ MCD_OPC_Decode, + 245, + 8, + 249, + 2, // Opcode: CRBAsmLE + /* 21668 */ MCD_OPC_Decode, + 240, + 8, + 250, + 2, // Opcode: CRBAsm + /* 21673 */ MCD_OPC_FilterValue, + 247, + 1, + 76, + 0, + 0, // Skip to: 21755 + /* 21679 */ MCD_OPC_ExtractField, + 8, + 4, // Inst{11-8} ... + /* 21682 */ MCD_OPC_FilterValue, + 0, + 21, + 6, + 0, // Skip to: 23244 + /* 21687 */ MCD_OPC_ExtractField, + 12, + 4, // Inst{15-12} ... + /* 21690 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21700 + /* 21695 */ MCD_OPC_Decode, + 173, + 8, + 249, + 2, // Opcode: CLRBAsmH + /* 21700 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21710 + /* 21705 */ MCD_OPC_Decode, + 175, + 8, + 249, + 2, // Opcode: CLRBAsmL + /* 21710 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21720 + /* 21715 */ MCD_OPC_Decode, + 177, + 8, + 249, + 2, // Opcode: CLRBAsmLH + /* 21720 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21730 + /* 21725 */ MCD_OPC_Decode, + 172, + 8, + 249, + 2, // Opcode: CLRBAsmE + /* 21730 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21740 + /* 21735 */ MCD_OPC_Decode, + 174, + 8, + 249, + 2, // Opcode: CLRBAsmHE + /* 21740 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21750 + /* 21745 */ MCD_OPC_Decode, + 176, + 8, + 249, + 2, // Opcode: CLRBAsmLE + /* 21750 */ MCD_OPC_Decode, + 171, + 8, + 250, + 2, // Opcode: CLRBAsm + /* 21755 */ MCD_OPC_FilterValue, + 252, + 1, + 68, + 0, + 0, // Skip to: 21829 + /* 21761 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 21764 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21774 + /* 21769 */ MCD_OPC_Decode, + 235, + 5, + 251, + 2, // Opcode: CGIBAsmH + /* 21774 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21784 + /* 21779 */ MCD_OPC_Decode, + 237, + 5, + 251, + 2, // Opcode: CGIBAsmL + /* 21784 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21794 + /* 21789 */ MCD_OPC_Decode, + 239, + 5, + 251, + 2, // Opcode: CGIBAsmLH + /* 21794 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21804 + /* 21799 */ MCD_OPC_Decode, + 234, + 5, + 251, + 2, // Opcode: CGIBAsmE + /* 21804 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21814 + /* 21809 */ MCD_OPC_Decode, + 236, + 5, + 251, + 2, // Opcode: CGIBAsmHE + /* 21814 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21824 + /* 21819 */ MCD_OPC_Decode, + 238, + 5, + 251, + 2, // Opcode: CGIBAsmLE + /* 21824 */ MCD_OPC_Decode, + 233, + 5, + 252, + 2, // Opcode: CGIBAsm + /* 21829 */ MCD_OPC_FilterValue, + 253, + 1, + 68, + 0, + 0, // Skip to: 21903 + /* 21835 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 21838 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21848 + /* 21843 */ MCD_OPC_Decode, + 159, + 7, + 253, + 2, // Opcode: CLGIBAsmH + /* 21848 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21858 + /* 21853 */ MCD_OPC_Decode, + 161, + 7, + 253, + 2, // Opcode: CLGIBAsmL + /* 21858 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21868 + /* 21863 */ MCD_OPC_Decode, + 163, + 7, + 253, + 2, // Opcode: CLGIBAsmLH + /* 21868 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21878 + /* 21873 */ MCD_OPC_Decode, + 158, + 7, + 253, + 2, // Opcode: CLGIBAsmE + /* 21878 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21888 + /* 21883 */ MCD_OPC_Decode, + 160, + 7, + 253, + 2, // Opcode: CLGIBAsmHE + /* 21888 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21898 + /* 21893 */ MCD_OPC_Decode, + 162, + 7, + 253, + 2, // Opcode: CLGIBAsmLE + /* 21898 */ MCD_OPC_Decode, + 157, + 7, + 254, + 2, // Opcode: CLGIBAsm + /* 21903 */ MCD_OPC_FilterValue, + 254, + 1, + 68, + 0, + 0, // Skip to: 21977 + /* 21909 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 21912 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21922 + /* 21917 */ MCD_OPC_Decode, + 207, + 6, + 255, + 2, // Opcode: CIBAsmH + /* 21922 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 21932 + /* 21927 */ MCD_OPC_Decode, + 209, + 6, + 255, + 2, // Opcode: CIBAsmL + /* 21932 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 21942 + /* 21937 */ MCD_OPC_Decode, + 211, + 6, + 255, + 2, // Opcode: CIBAsmLH + /* 21942 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 21952 + /* 21947 */ MCD_OPC_Decode, + 206, + 6, + 255, + 2, // Opcode: CIBAsmE + /* 21952 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 21962 + /* 21957 */ MCD_OPC_Decode, + 208, + 6, + 255, + 2, // Opcode: CIBAsmHE + /* 21962 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 21972 + /* 21967 */ MCD_OPC_Decode, + 210, + 6, + 255, + 2, // Opcode: CIBAsmLE + /* 21972 */ MCD_OPC_Decode, + 205, + 6, + 128, + 3, // Opcode: CIBAsm + /* 21977 */ MCD_OPC_FilterValue, + 255, + 1, + 237, + 4, + 0, // Skip to: 23244 + /* 21983 */ MCD_OPC_ExtractField, + 32, + 4, // Inst{35-32} ... + /* 21986 */ MCD_OPC_FilterValue, + 2, + 5, + 0, + 0, // Skip to: 21996 + /* 21991 */ MCD_OPC_Decode, + 139, + 8, + 129, + 3, // Opcode: CLIBAsmH + /* 21996 */ MCD_OPC_FilterValue, + 4, + 5, + 0, + 0, // Skip to: 22006 + /* 22001 */ MCD_OPC_Decode, + 141, + 8, + 129, + 3, // Opcode: CLIBAsmL + /* 22006 */ MCD_OPC_FilterValue, + 6, + 5, + 0, + 0, // Skip to: 22016 + /* 22011 */ MCD_OPC_Decode, + 143, + 8, + 129, + 3, // Opcode: CLIBAsmLH + /* 22016 */ MCD_OPC_FilterValue, + 8, + 5, + 0, + 0, // Skip to: 22026 + /* 22021 */ MCD_OPC_Decode, + 138, + 8, + 129, + 3, // Opcode: CLIBAsmE + /* 22026 */ MCD_OPC_FilterValue, + 10, + 5, + 0, + 0, // Skip to: 22036 + /* 22031 */ MCD_OPC_Decode, + 140, + 8, + 129, + 3, // Opcode: CLIBAsmHE + /* 22036 */ MCD_OPC_FilterValue, + 12, + 5, + 0, + 0, // Skip to: 22046 + /* 22041 */ MCD_OPC_Decode, + 142, + 8, + 129, + 3, // Opcode: CLIBAsmLE + /* 22046 */ MCD_OPC_Decode, + 137, + 8, + 130, + 3, // Opcode: CLIBAsm + /* 22051 */ MCD_OPC_FilterValue, + 237, + 1, + 31, + 4, + 0, // Skip to: 23112 + /* 22057 */ MCD_OPC_ExtractField, + 0, + 8, // Inst{7-0} ... + /* 22060 */ MCD_OPC_FilterValue, + 4, + 12, + 0, + 0, // Skip to: 22077 + /* 22065 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 148, + 4, + 0, // Skip to: 23244 + /* 22072 */ MCD_OPC_Decode, + 182, + 11, + 131, + 3, // Opcode: LDEB + /* 22077 */ MCD_OPC_FilterValue, + 5, + 12, + 0, + 0, // Skip to: 22094 + /* 22082 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 131, + 4, + 0, // Skip to: 23244 + /* 22089 */ MCD_OPC_Decode, + 141, + 14, + 132, + 3, // Opcode: LXDB + /* 22094 */ MCD_OPC_FilterValue, + 6, + 12, + 0, + 0, // Skip to: 22111 + /* 22099 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 114, + 4, + 0, // Skip to: 23244 + /* 22106 */ MCD_OPC_Decode, + 146, + 14, + 132, + 3, // Opcode: LXEB + /* 22111 */ MCD_OPC_FilterValue, + 7, + 12, + 0, + 0, // Skip to: 22128 + /* 22116 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 97, + 4, + 0, // Skip to: 23244 + /* 22123 */ MCD_OPC_Decode, + 249, + 14, + 133, + 3, // Opcode: MXDB + /* 22128 */ MCD_OPC_FilterValue, + 8, + 12, + 0, + 0, // Skip to: 22145 + /* 22133 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 80, + 4, + 0, // Skip to: 23244 + /* 22140 */ MCD_OPC_Decode, + 255, + 10, + 134, + 3, // Opcode: KEB + /* 22145 */ MCD_OPC_FilterValue, + 9, + 12, + 0, + 0, // Skip to: 22162 + /* 22150 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 63, + 4, + 0, // Skip to: 23244 + /* 22157 */ MCD_OPC_Decode, + 189, + 5, + 134, + 3, // Opcode: CEB + /* 22162 */ MCD_OPC_FilterValue, + 10, + 12, + 0, + 0, // Skip to: 22179 + /* 22167 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 46, + 4, + 0, // Skip to: 23244 + /* 22174 */ MCD_OPC_Decode, + 132, + 4, + 135, + 3, // Opcode: AEB + /* 22179 */ MCD_OPC_FilterValue, + 11, + 12, + 0, + 0, // Skip to: 22196 + /* 22184 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 29, + 4, + 0, // Skip to: 23244 + /* 22191 */ MCD_OPC_Decode, + 248, + 15, + 135, + 3, // Opcode: SEB + /* 22196 */ MCD_OPC_FilterValue, + 12, + 12, + 0, + 0, // Skip to: 22213 + /* 22201 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 12, + 4, + 0, // Skip to: 23244 + /* 22208 */ MCD_OPC_Decode, + 176, + 14, + 136, + 3, // Opcode: MDEB + /* 22213 */ MCD_OPC_FilterValue, + 13, + 12, + 0, + 0, // Skip to: 22230 + /* 22218 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 251, + 3, + 0, // Skip to: 23244 + /* 22225 */ MCD_OPC_Decode, + 219, + 9, + 135, + 3, // Opcode: DEB + /* 22230 */ MCD_OPC_FilterValue, + 14, + 12, + 0, + 0, // Skip to: 22247 + /* 22235 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 234, + 3, + 0, // Skip to: 23244 + /* 22242 */ MCD_OPC_Decode, + 162, + 14, + 137, + 3, // Opcode: MAEB + /* 22247 */ MCD_OPC_FilterValue, + 15, + 12, + 0, + 0, // Skip to: 22264 + /* 22252 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 217, + 3, + 0, // Skip to: 23244 + /* 22259 */ MCD_OPC_Decode, + 210, + 14, + 137, + 3, // Opcode: MSEB + /* 22264 */ MCD_OPC_FilterValue, + 16, + 12, + 0, + 0, // Skip to: 22281 + /* 22269 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 200, + 3, + 0, // Skip to: 23244 + /* 22276 */ MCD_OPC_Decode, + 155, + 18, + 134, + 3, // Opcode: TCEB + /* 22281 */ MCD_OPC_FilterValue, + 17, + 12, + 0, + 0, // Skip to: 22298 + /* 22286 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 183, + 3, + 0, // Skip to: 23244 + /* 22293 */ MCD_OPC_Decode, + 154, + 18, + 131, + 3, // Opcode: TCDB + /* 22298 */ MCD_OPC_FilterValue, + 18, + 12, + 0, + 0, // Skip to: 22315 + /* 22303 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 166, + 3, + 0, // Skip to: 23244 + /* 22310 */ MCD_OPC_Decode, + 156, + 18, + 132, + 3, // Opcode: TCXB + /* 22315 */ MCD_OPC_FilterValue, + 20, + 12, + 0, + 0, // Skip to: 22332 + /* 22320 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 149, + 3, + 0, // Skip to: 23244 + /* 22327 */ MCD_OPC_Decode, + 243, + 16, + 134, + 3, // Opcode: SQEB + /* 22332 */ MCD_OPC_FilterValue, + 21, + 12, + 0, + 0, // Skip to: 22349 + /* 22337 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 132, + 3, + 0, // Skip to: 23244 + /* 22344 */ MCD_OPC_Decode, + 239, + 16, + 131, + 3, // Opcode: SQDB + /* 22349 */ MCD_OPC_FilterValue, + 23, + 12, + 0, + 0, // Skip to: 22366 + /* 22354 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 115, + 3, + 0, // Skip to: 23244 + /* 22361 */ MCD_OPC_Decode, + 184, + 14, + 135, + 3, // Opcode: MEEB + /* 22366 */ MCD_OPC_FilterValue, + 24, + 12, + 0, + 0, // Skip to: 22383 + /* 22371 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 98, + 3, + 0, // Skip to: 23244 + /* 22378 */ MCD_OPC_Decode, + 251, + 10, + 131, + 3, // Opcode: KDB + /* 22383 */ MCD_OPC_FilterValue, + 25, + 12, + 0, + 0, // Skip to: 22400 + /* 22388 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 81, + 3, + 0, // Skip to: 23244 + /* 22395 */ MCD_OPC_Decode, + 164, + 5, + 131, + 3, // Opcode: CDB + /* 22400 */ MCD_OPC_FilterValue, + 26, + 12, + 0, + 0, // Skip to: 22417 + /* 22405 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 64, + 3, + 0, // Skip to: 23244 + /* 22412 */ MCD_OPC_Decode, + 254, + 3, + 136, + 3, // Opcode: ADB + /* 22417 */ MCD_OPC_FilterValue, + 27, + 12, + 0, + 0, // Skip to: 22434 + /* 22422 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 47, + 3, + 0, // Skip to: 23244 + /* 22429 */ MCD_OPC_Decode, + 242, + 15, + 136, + 3, // Opcode: SDB + /* 22434 */ MCD_OPC_FilterValue, + 28, + 12, + 0, + 0, // Skip to: 22451 + /* 22439 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 30, + 3, + 0, // Skip to: 23244 + /* 22446 */ MCD_OPC_Decode, + 173, + 14, + 136, + 3, // Opcode: MDB + /* 22451 */ MCD_OPC_FilterValue, + 29, + 12, + 0, + 0, // Skip to: 22468 + /* 22456 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 13, + 3, + 0, // Skip to: 23244 + /* 22463 */ MCD_OPC_Decode, + 213, + 9, + 136, + 3, // Opcode: DDB + /* 22468 */ MCD_OPC_FilterValue, + 30, + 12, + 0, + 0, // Skip to: 22485 + /* 22473 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 252, + 2, + 0, // Skip to: 23244 + /* 22480 */ MCD_OPC_Decode, + 158, + 14, + 138, + 3, // Opcode: MADB + /* 22485 */ MCD_OPC_FilterValue, + 31, + 12, + 0, + 0, // Skip to: 22502 + /* 22490 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 235, + 2, + 0, // Skip to: 23244 + /* 22497 */ MCD_OPC_Decode, + 206, + 14, + 138, + 3, // Opcode: MSDB + /* 22502 */ MCD_OPC_FilterValue, + 36, + 12, + 0, + 0, // Skip to: 22519 + /* 22507 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 218, + 2, + 0, // Skip to: 23244 + /* 22514 */ MCD_OPC_Decode, + 180, + 11, + 131, + 3, // Opcode: LDE + /* 22519 */ MCD_OPC_FilterValue, + 37, + 12, + 0, + 0, // Skip to: 22536 + /* 22524 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 201, + 2, + 0, // Skip to: 23244 + /* 22531 */ MCD_OPC_Decode, + 140, + 14, + 132, + 3, // Opcode: LXD + /* 22536 */ MCD_OPC_FilterValue, + 38, + 12, + 0, + 0, // Skip to: 22553 + /* 22541 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 184, + 2, + 0, // Skip to: 23244 + /* 22548 */ MCD_OPC_Decode, + 145, + 14, + 132, + 3, // Opcode: LXE + /* 22553 */ MCD_OPC_FilterValue, + 46, + 12, + 0, + 0, // Skip to: 22570 + /* 22558 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 167, + 2, + 0, // Skip to: 23244 + /* 22565 */ MCD_OPC_Decode, + 161, + 14, + 137, + 3, // Opcode: MAE + /* 22570 */ MCD_OPC_FilterValue, + 47, + 12, + 0, + 0, // Skip to: 22587 + /* 22575 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 150, + 2, + 0, // Skip to: 23244 + /* 22582 */ MCD_OPC_Decode, + 209, + 14, + 137, + 3, // Opcode: MSE + /* 22587 */ MCD_OPC_FilterValue, + 52, + 12, + 0, + 0, // Skip to: 22604 + /* 22592 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 133, + 2, + 0, // Skip to: 23244 + /* 22599 */ MCD_OPC_Decode, + 242, + 16, + 134, + 3, // Opcode: SQE + /* 22604 */ MCD_OPC_FilterValue, + 53, + 12, + 0, + 0, // Skip to: 22621 + /* 22609 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 116, + 2, + 0, // Skip to: 23244 + /* 22616 */ MCD_OPC_Decode, + 238, + 16, + 131, + 3, // Opcode: SQD + /* 22621 */ MCD_OPC_FilterValue, + 55, + 12, + 0, + 0, // Skip to: 22638 + /* 22626 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 99, + 2, + 0, // Skip to: 23244 + /* 22633 */ MCD_OPC_Decode, + 183, + 14, + 135, + 3, // Opcode: MEE + /* 22638 */ MCD_OPC_FilterValue, + 56, + 12, + 0, + 0, // Skip to: 22655 + /* 22643 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 82, + 2, + 0, // Skip to: 23244 + /* 22650 */ MCD_OPC_Decode, + 168, + 14, + 138, + 3, // Opcode: MAYL + /* 22655 */ MCD_OPC_FilterValue, + 57, + 12, + 0, + 0, // Skip to: 22672 + /* 22660 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 65, + 2, + 0, // Skip to: 23244 + /* 22667 */ MCD_OPC_Decode, + 130, + 15, + 139, + 3, // Opcode: MYL + /* 22672 */ MCD_OPC_FilterValue, + 58, + 12, + 0, + 0, // Skip to: 22689 + /* 22677 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 48, + 2, + 0, // Skip to: 23244 + /* 22684 */ MCD_OPC_Decode, + 165, + 14, + 140, + 3, // Opcode: MAY + /* 22689 */ MCD_OPC_FilterValue, + 59, + 12, + 0, + 0, // Skip to: 22706 + /* 22694 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 31, + 2, + 0, // Skip to: 23244 + /* 22701 */ MCD_OPC_Decode, + 255, + 14, + 141, + 3, // Opcode: MY + /* 22706 */ MCD_OPC_FilterValue, + 60, + 12, + 0, + 0, // Skip to: 22723 + /* 22711 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 14, + 2, + 0, // Skip to: 23244 + /* 22718 */ MCD_OPC_Decode, + 166, + 14, + 138, + 3, // Opcode: MAYH + /* 22723 */ MCD_OPC_FilterValue, + 61, + 12, + 0, + 0, // Skip to: 22740 + /* 22728 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 253, + 1, + 0, // Skip to: 23244 + /* 22735 */ MCD_OPC_Decode, + 128, + 15, + 139, + 3, // Opcode: MYH + /* 22740 */ MCD_OPC_FilterValue, + 62, + 12, + 0, + 0, // Skip to: 22757 + /* 22745 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 236, + 1, + 0, // Skip to: 23244 + /* 22752 */ MCD_OPC_Decode, + 157, + 14, + 138, + 3, // Opcode: MAD + /* 22757 */ MCD_OPC_FilterValue, + 63, + 12, + 0, + 0, // Skip to: 22774 + /* 22762 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 219, + 1, + 0, // Skip to: 23244 + /* 22769 */ MCD_OPC_Decode, + 205, + 14, + 138, + 3, // Opcode: MSD + /* 22774 */ MCD_OPC_FilterValue, + 64, + 12, + 0, + 0, // Skip to: 22791 + /* 22779 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 202, + 1, + 0, // Skip to: 23244 + /* 22786 */ MCD_OPC_Decode, + 214, + 16, + 139, + 3, // Opcode: SLDT + /* 22791 */ MCD_OPC_FilterValue, + 65, + 12, + 0, + 0, // Skip to: 22808 + /* 22796 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 185, + 1, + 0, // Skip to: 23244 + /* 22803 */ MCD_OPC_Decode, + 254, + 16, + 139, + 3, // Opcode: SRDT + /* 22808 */ MCD_OPC_FilterValue, + 72, + 12, + 0, + 0, // Skip to: 22825 + /* 22813 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 168, + 1, + 0, // Skip to: 23244 + /* 22820 */ MCD_OPC_Decode, + 229, + 16, + 142, + 3, // Opcode: SLXT + /* 22825 */ MCD_OPC_FilterValue, + 73, + 12, + 0, + 0, // Skip to: 22842 + /* 22830 */ MCD_OPC_CheckField, + 8, + 4, + 0, + 151, + 1, + 0, // Skip to: 23244 + /* 22837 */ MCD_OPC_Decode, + 137, + 17, + 142, + 3, // Opcode: SRXT + /* 22842 */ MCD_OPC_FilterValue, + 80, + 12, + 0, + 0, // Skip to: 22859 + /* 22847 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 134, + 1, + 0, // Skip to: 23244 + /* 22854 */ MCD_OPC_Decode, + 158, + 18, + 134, + 3, // Opcode: TDCET + /* 22859 */ MCD_OPC_FilterValue, + 81, + 12, + 0, + 0, // Skip to: 22876 + /* 22864 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 117, + 1, + 0, // Skip to: 23244 + /* 22871 */ MCD_OPC_Decode, + 161, + 18, + 134, + 3, // Opcode: TDGET + /* 22876 */ MCD_OPC_FilterValue, + 84, + 12, + 0, + 0, // Skip to: 22893 + /* 22881 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 100, + 1, + 0, // Skip to: 23244 + /* 22888 */ MCD_OPC_Decode, + 157, + 18, + 131, + 3, // Opcode: TDCDT + /* 22893 */ MCD_OPC_FilterValue, + 85, + 12, + 0, + 0, // Skip to: 22910 + /* 22898 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 83, + 1, + 0, // Skip to: 23244 + /* 22905 */ MCD_OPC_Decode, + 160, + 18, + 131, + 3, // Opcode: TDGDT + /* 22910 */ MCD_OPC_FilterValue, + 88, + 12, + 0, + 0, // Skip to: 22927 + /* 22915 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 66, + 1, + 0, // Skip to: 23244 + /* 22922 */ MCD_OPC_Decode, + 159, + 18, + 132, + 3, // Opcode: TDCXT + /* 22927 */ MCD_OPC_FilterValue, + 89, + 12, + 0, + 0, // Skip to: 22944 + /* 22932 */ MCD_OPC_CheckField, + 8, + 8, + 0, + 49, + 1, + 0, // Skip to: 23244 + /* 22939 */ MCD_OPC_Decode, + 162, + 18, + 132, + 3, // Opcode: TDGXT + /* 22944 */ MCD_OPC_FilterValue, + 100, + 5, + 0, + 0, // Skip to: 22954 + /* 22949 */ MCD_OPC_Decode, + 203, + 11, + 143, + 3, // Opcode: LEY + /* 22954 */ MCD_OPC_FilterValue, + 101, + 5, + 0, + 0, // Skip to: 22964 + /* 22959 */ MCD_OPC_Decode, + 193, + 11, + 144, + 3, // Opcode: LDY + /* 22964 */ MCD_OPC_FilterValue, + 102, + 5, + 0, + 0, // Skip to: 22974 + /* 22969 */ MCD_OPC_Decode, + 166, + 17, + 143, + 3, // Opcode: STEY + /* 22974 */ MCD_OPC_FilterValue, + 103, + 5, + 0, + 0, // Skip to: 22984 + /* 22979 */ MCD_OPC_Decode, + 164, + 17, + 144, + 3, // Opcode: STDY + /* 22984 */ MCD_OPC_FilterValue, + 168, + 1, + 10, + 0, + 0, // Skip to: 23000 + /* 22990 */ MCD_OPC_CheckPredicate, + 37, + 249, + 0, + 0, // Skip to: 23244 + /* 22995 */ MCD_OPC_Decode, + 209, + 9, + 145, + 3, // Opcode: CZDT + /* 23000 */ MCD_OPC_FilterValue, + 169, + 1, + 10, + 0, + 0, // Skip to: 23016 + /* 23006 */ MCD_OPC_CheckPredicate, + 37, + 233, + 0, + 0, // Skip to: 23244 + /* 23011 */ MCD_OPC_Decode, + 210, + 9, + 146, + 3, // Opcode: CZXT + /* 23016 */ MCD_OPC_FilterValue, + 170, + 1, + 10, + 0, + 0, // Skip to: 23032 + /* 23022 */ MCD_OPC_CheckPredicate, + 37, + 217, + 0, + 0, // Skip to: 23244 + /* 23027 */ MCD_OPC_Decode, + 187, + 5, + 145, + 3, // Opcode: CDZT + /* 23032 */ MCD_OPC_FilterValue, + 171, + 1, + 10, + 0, + 0, // Skip to: 23048 + /* 23038 */ MCD_OPC_CheckPredicate, + 37, + 201, + 0, + 0, // Skip to: 23244 + /* 23043 */ MCD_OPC_Decode, + 207, + 9, + 146, + 3, // Opcode: CXZT + /* 23048 */ MCD_OPC_FilterValue, + 172, + 1, + 10, + 0, + 0, // Skip to: 23064 + /* 23054 */ MCD_OPC_CheckPredicate, + 38, + 185, + 0, + 0, // Skip to: 23244 + /* 23059 */ MCD_OPC_Decode, + 231, + 8, + 145, + 3, // Opcode: CPDT + /* 23064 */ MCD_OPC_FilterValue, + 173, + 1, + 10, + 0, + 0, // Skip to: 23080 + /* 23070 */ MCD_OPC_CheckPredicate, + 38, + 169, + 0, + 0, // Skip to: 23244 + /* 23075 */ MCD_OPC_Decode, + 236, + 8, + 146, + 3, // Opcode: CPXT + /* 23080 */ MCD_OPC_FilterValue, + 174, + 1, + 10, + 0, + 0, // Skip to: 23096 + /* 23086 */ MCD_OPC_CheckPredicate, + 38, + 153, + 0, + 0, // Skip to: 23244 + /* 23091 */ MCD_OPC_Decode, + 179, + 5, + 145, + 3, // Opcode: CDPT + /* 23096 */ MCD_OPC_FilterValue, + 175, + 1, + 142, + 0, + 0, // Skip to: 23244 + /* 23102 */ MCD_OPC_CheckPredicate, + 38, + 137, + 0, + 0, // Skip to: 23244 + /* 23107 */ MCD_OPC_Decode, + 202, + 9, + 146, + 3, // Opcode: CXPT + /* 23112 */ MCD_OPC_FilterValue, + 238, + 1, + 5, + 0, + 0, // Skip to: 23123 + /* 23118 */ MCD_OPC_Decode, + 192, + 15, + 147, + 3, // Opcode: PLO + /* 23123 */ MCD_OPC_FilterValue, + 239, + 1, + 5, + 0, + 0, // Skip to: 23134 + /* 23129 */ MCD_OPC_Decode, + 131, + 12, + 148, + 3, // Opcode: LMD + /* 23134 */ MCD_OPC_FilterValue, + 240, + 1, + 5, + 0, + 0, // Skip to: 23145 + /* 23140 */ MCD_OPC_Decode, + 134, + 17, + 149, + 3, // Opcode: SRP + /* 23145 */ MCD_OPC_FilterValue, + 241, + 1, + 5, + 0, + 0, // Skip to: 23156 + /* 23151 */ MCD_OPC_Decode, + 243, + 14, + 150, + 3, // Opcode: MVO + /* 23156 */ MCD_OPC_FilterValue, + 242, + 1, + 5, + 0, + 0, // Skip to: 23167 + /* 23162 */ MCD_OPC_Decode, + 179, + 15, + 150, + 3, // Opcode: PACK + /* 23167 */ MCD_OPC_FilterValue, + 243, + 1, + 5, + 0, + 0, // Skip to: 23178 + /* 23173 */ MCD_OPC_Decode, + 197, + 18, + 150, + 3, // Opcode: UNPK + /* 23178 */ MCD_OPC_FilterValue, + 248, + 1, + 5, + 0, + 0, // Skip to: 23189 + /* 23184 */ MCD_OPC_Decode, + 178, + 24, + 150, + 3, // Opcode: ZAP + /* 23189 */ MCD_OPC_FilterValue, + 249, + 1, + 5, + 0, + 0, // Skip to: 23200 + /* 23195 */ MCD_OPC_Decode, + 230, + 8, + 150, + 3, // Opcode: CP + /* 23200 */ MCD_OPC_FilterValue, + 250, + 1, + 5, + 0, + 0, // Skip to: 23211 + /* 23206 */ MCD_OPC_Decode, + 176, + 4, + 150, + 3, // Opcode: AP + /* 23211 */ MCD_OPC_FilterValue, + 251, + 1, + 5, + 0, + 0, // Skip to: 23222 + /* 23217 */ MCD_OPC_Decode, + 232, + 16, + 150, + 3, // Opcode: SP + /* 23222 */ MCD_OPC_FilterValue, + 252, + 1, + 5, + 0, + 0, // Skip to: 23233 + /* 23228 */ MCD_OPC_Decode, + 200, + 14, + 150, + 3, // Opcode: MP + /* 23233 */ MCD_OPC_FilterValue, + 253, + 1, + 5, + 0, + 0, // Skip to: 23244 + /* 23239 */ MCD_OPC_Decode, + 230, + 9, + 150, + 3, // Opcode: DP + /* 23244 */ MCD_OPC_Fail, + 0}; -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ +static bool getbool(uint64_t b) { return b != 0; } +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { - default: // llvm_unreachable("Invalid index!"); + default: + llvm_unreachable("Invalid index!"); case 0: - return getbool((Bits & SystemZ_FeatureFPExtension)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureBEAREnhancement, 1)); case 1: - return getbool((Bits & SystemZ_FeatureProcessorAssist)); + return getbool(checkFeatureRequired( + Bits, SystemZ_FeatureProcessorActivityInstrumentation, 1)); case 2: - return getbool((Bits & SystemZ_FeatureTransactionalExecution)); + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureFPExtension, 1)); case 3: - return getbool((Bits & SystemZ_FeatureExecutionHint)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureProcessorAssist, 1)); case 4: - return getbool((Bits & SystemZ_FeatureMessageSecurityAssist3)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureTransactionalExecution, 1)); case 5: - return getbool((Bits & SystemZ_FeatureMessageSecurityAssist8)); + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureExecutionHint, 1)); case 6: - return getbool((Bits & SystemZ_FeatureMessageSecurityAssist4)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureMessageSecurityAssist3, 1)); case 7: - return getbool((Bits & SystemZ_FeatureMessageSecurityAssist5)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureMessageSecurityAssist8, 1)); case 8: - return getbool((Bits & SystemZ_FeatureEnhancedDAT2)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureMessageSecurityAssist4, 1)); case 9: - return getbool((Bits & SystemZ_FeatureInsertReferenceBitsMultiple)); + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureEnhancedSort, 1)); case 10: - return getbool((Bits & SystemZ_FeatureResetReferenceBitsMultiple)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureDeflateConversion, 1)); case 11: - return getbool((Bits & SystemZ_FeatureHighWord)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureMessageSecurityAssist9, 1)); case 12: - return getbool((Bits & SystemZ_FeatureLoadStoreOnCond2)); + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureNNPAssist, 1)); case 13: - return getbool((Bits & SystemZ_FeaturePopulationCount)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureMessageSecurityAssist5, 1)); case 14: - return getbool((Bits & SystemZ_FeatureLoadStoreOnCond)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureMiscellaneousExtensions3, 1)); case 15: - return getbool((Bits & SystemZ_FeatureDistinctOps)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureResetDATProtection, 1)); case 16: - return getbool((Bits & SystemZ_FeatureMiscellaneousExtensions2)); + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureEnhancedDAT2, 1)); case 17: - return getbool((Bits & SystemZ_FeatureInterlockedAccess1)); + return getbool(checkFeatureRequired( + Bits, SystemZ_FeatureInsertReferenceBitsMultiple, 1)); case 18: - return getbool((Bits & SystemZ_FeatureLoadAndZeroRightmostByte)); + return getbool(checkFeatureRequired( + Bits, SystemZ_FeatureResetReferenceBitsMultiple, 1)); case 19: - return getbool((Bits & SystemZ_FeatureGuardedStorage)); + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureHighWord, 1)); case 20: - return getbool((Bits & SystemZ_FeatureLoadAndTrap)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureLoadStoreOnCond2, 1)); case 21: - return getbool((Bits & SystemZ_FeatureVectorPackedDecimal)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeaturePopulationCount, 1)); case 22: - return getbool((Bits & SystemZ_FeatureVector)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureLoadStoreOnCond, 1)); case 23: - return getbool((Bits & SystemZ_FeatureVectorEnhancements1)); + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureDistinctOps, 1)); case 24: - return getbool((Bits & SystemZ_FeatureMiscellaneousExtensions)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureMiscellaneousExtensions2, 1)); case 25: - return getbool((Bits & SystemZ_FeatureDFPZonedConversion)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureInterlockedAccess1, 1)); case 26: - return getbool((Bits & SystemZ_FeatureDFPPackedConversion)); + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureLoadAndZeroRightmostByte, 1)); + case 27: + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureGuardedStorage, 1)); + case 28: + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureLoadAndTrap, 1)); + case 29: + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureVectorEnhancements2, 1)); + case 30: + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureVectorPackedDecimal, 1)); + case 31: + return getbool(checkFeatureRequired( + Bits, SystemZ_FeatureVectorPackedDecimalEnhancement, 1)); + case 32: + return getbool(checkFeatureRequired( + Bits, SystemZ_FeatureVectorPackedDecimalEnhancement2, 1)); + case 33: + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureVector, 1) && + checkFeatureRequired(Bits, SystemZ_FeatureNNPAssist, 1)); + case 34: + return getbool(checkFeatureRequired(Bits, SystemZ_FeatureVector, 1)); + case 35: + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureVectorEnhancements1, 1)); + case 36: + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureMiscellaneousExtensions, 1)); + case 37: + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureDFPZonedConversion, 1)); + case 38: + return getbool( + checkFeatureRequired(Bits, SystemZ_FeatureDFPPackedConversion, 1)); } } -#define DecodeToMCInst(fname,fieldname, InsnType) \ -static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, const void *Decoder) \ -{ \ - InsnType tmp; \ - switch (Idx) { \ - default: \ - case 0: \ - return S; \ - case 1: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 2: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 3: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 4: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 5: \ - tmp = fieldname(insn, 4, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 6: \ - tmp = fieldname(insn, 0, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 7: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 8: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 9: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 10: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 11: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 12: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 13: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 14: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 15: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 16: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 17: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 18: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 19: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 20: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 21: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 22: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 23: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 24: \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 25: \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 26: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 27: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 28: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 29: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 30: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 31: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 32: \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 33: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 34: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 35: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 36: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 37: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 38: \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 39: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 40: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 41: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 42: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 43: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 44: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 45: \ - tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 46: \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 47: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 48: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 49: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 50: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 51: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 52: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 53: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 54: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 55: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 56: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 57: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 58: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 59: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 60: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 61: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 62: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 63: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 64: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 65: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 66: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 67: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 68: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 69: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 70: \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 71: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 72: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 73: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 74: \ - tmp = fieldname(insn, 4, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 75: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 76: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 77: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 78: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 79: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 80: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 81: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 82: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 83: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 84: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 85: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 86: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 87: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 88: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 89: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 90: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 91: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 92: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 93: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 94: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 95: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 96: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 97: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 98: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 99: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 100: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 101: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 102: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 103: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 104: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 105: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 106: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 107: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 108: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 109: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 110: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 111: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 112: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 113: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 114: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 115: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 116: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 117: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 118: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 119: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 120: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 121: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 122: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 123: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 124: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 125: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 126: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 127: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 128: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 129: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 130: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 131: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 132: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 133: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 134: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 135: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 136: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 137: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 138: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 139: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 140: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 141: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 142: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 143: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 144: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 145: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 146: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 147: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 148: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 149: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 150: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 151: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 152: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 153: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 154: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 155: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 156: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 157: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 158: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 159: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 160: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 161: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 162: \ - tmp = fieldname(insn, 4, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 163: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 164: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 165: \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 166: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 167: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 168: \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 169: \ - tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 170: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 171: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 172: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 173: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 174: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 175: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 176: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 177: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 178: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 179: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 180: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 181: \ - tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 12); \ - if (decodePC12DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 24); \ - if (decodePC24DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 182: \ - tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 183: \ - tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 184: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 185: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 186: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 187: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 188: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 32); \ - if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 189: \ - tmp = fieldname(insn, 16, 24); \ - if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 190: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 16) << 0; \ - tmp |= fieldname(insn, 36, 4) << 16; \ - if (decodeBDRAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 191: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 16) << 0; \ - tmp |= fieldname(insn, 32, 8) << 16; \ - if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 192: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 193: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 194: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 195: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 196: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 197: \ - tmp = fieldname(insn, 36, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 198: \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 199: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 200: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 201: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 202: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 203: \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 204: \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 205: \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 206: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 207: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 208: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 209: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 210: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 211: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 212: \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 213: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 214: \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 215: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 216: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 217: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 218: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 219: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 220: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 221: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 222: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 223: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 224: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 20; \ - tmp |= fieldname(insn, 16, 20) << 0; \ - if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 225: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 20; \ - tmp |= fieldname(insn, 16, 20) << 0; \ - if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 226: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 20; \ - tmp |= fieldname(insn, 16, 20) << 0; \ - if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 227: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 20; \ - tmp |= fieldname(insn, 16, 20) << 0; \ - if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 228: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 229: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 230: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 231: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 232: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 233: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 234: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 235: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 236: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 237: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 238: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 239: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 240: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 241: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 242: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 243: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 244: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 245: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 246: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 247: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 248: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 249: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 250: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 251: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 252: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 253: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 254: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 255: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 256: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 257: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 258: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 259: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 260: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 28, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 261: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 262: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 263: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 264: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 265: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 266: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 22, 2) << 2; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 267: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 3) << 1; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 268: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 20, 1) << 0; \ - tmp |= fieldname(insn, 22, 2) << 2; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 269: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 22, 2) << 2; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 270: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 21, 3) << 1; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 271: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 20, 1) << 0; \ - tmp |= fieldname(insn, 22, 2) << 2; \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 272: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 273: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 274: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 275: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 276: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 277: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 278: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 8, 1) << 4; \ - tmp |= fieldname(insn, 12, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 279: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 280: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 281: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 282: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 283: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 284: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 285: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 286: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 287: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 288: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 289: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 290: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 291: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 292: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 293: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 294: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 295: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 296: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 297: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 298: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 299: \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 4; \ - tmp |= fieldname(insn, 36, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 1) << 4; \ - tmp |= fieldname(insn, 32, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 9, 1) << 4; \ - tmp |= fieldname(insn, 28, 4) << 0; \ - if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 300: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 301: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 302: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 303: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 304: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 305: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 306: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 307: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 308: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 309: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 310: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 311: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 312: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 313: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 314: \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 315: \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 316: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 317: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 318: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 319: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 320: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 321: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 16) << 0; \ - tmp |= fieldname(insn, 36, 4) << 16; \ - if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 322: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 323: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 324: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 325: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 326: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 327: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 328: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 329: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 24); \ - if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 330: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 331: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 332: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 333: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 334: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 335: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 336: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 337: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 338: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 339: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 24, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 340: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 341: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 342: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 343: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 344: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 345: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 346: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 347: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 348: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 349: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 350: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 351: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 352: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 353: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 354: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 355: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 356: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 357: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 358: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 359: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 360: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 361: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 362: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 363: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 364: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 365: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 366: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 367: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 368: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 369: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 370: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 371: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 372: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 373: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 8); \ - if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 374: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 375: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 376: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 377: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 378: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 379: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 380: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 381: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 382: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 383: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 384: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 385: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 20); \ - if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 386: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 387: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 28); \ - if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 388: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 24); \ - if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 389: \ - tmp = fieldname(insn, 12, 4); \ - if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 24); \ - if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 8, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 390: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 391: \ - tmp = fieldname(insn, 36, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 392: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 16) << 0; \ - tmp |= fieldname(insn, 36, 4) << 16; \ - if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 16); \ - if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 32, 4); \ - if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 393: \ - tmp = 0; \ - tmp |= fieldname(insn, 16, 16) << 0; \ - tmp |= fieldname(insn, 36, 4) << 16; \ - if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 0, 16) << 0; \ - tmp |= fieldname(insn, 32, 4) << 16; \ - if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - } \ +#define DecodeToMCInst(fname, fieldname, InsnType) \ + static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, \ + MCInst *MI, uint64_t Address, bool *Decoder) { \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + llvm_unreachable("Invalid index!"); \ + case 0: \ + return S; \ + case 1: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 2: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 3: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 5: \ + tmp = fieldname(insn, 4, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 6: \ + tmp = fieldname(insn, 0, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 7: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 8: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 9: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 10: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 11: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 12: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 13: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 14: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 15: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 16: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 21: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 26: \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 27: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 31: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 34: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 35: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 37: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 41: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 42: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 45: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 46: \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 47: \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 48: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 49: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 50: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 51: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 52: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 53: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 55: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 57: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 58: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 59: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 60: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 61: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 62: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 64: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 65: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 66: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 68: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 69: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 70: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 72: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 73: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 74: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 75: \ + tmp = fieldname(insn, 4, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 76: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 77: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 78: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 79: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 80: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 82: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 83: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 84: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 85: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 86: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 87: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 88: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 89: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 90: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 91: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 92: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 93: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 94: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 95: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 96: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 97: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 98: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 99: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 100: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 101: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 102: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 103: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 104: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 105: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 106: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 107: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 108: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 109: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 110: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 111: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 112: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 113: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 114: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 115: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 116: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 117: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 118: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 119: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 120: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 121: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 122: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 123: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 124: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 125: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 126: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 127: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 128: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 129: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 130: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 131: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 132: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 133: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 134: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 135: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 136: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 137: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 138: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 139: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 140: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 141: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 142: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 143: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 144: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 145: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 146: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 147: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 148: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 149: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 150: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 151: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 152: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 153: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 154: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 155: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 156: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 157: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 158: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 159: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 160: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 161: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 162: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 163: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 164: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 165: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 166: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 167: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 168: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 169: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 170: \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 4, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 171: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 172: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 173: \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 174: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 175: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 176: \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 177: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 178: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 179: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 180: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 181: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 182: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 183: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 184: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 185: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 186: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 187: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 188: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 189: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 12); \ + if (decodePC12DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 24); \ + if (decodePC24DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 190: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 191: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 192: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 193: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 194: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 195: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 196: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 197: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 32); \ + if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 198: \ + tmp = fieldname(insn, 16, 24); \ + if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 199: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + tmp |= fieldname(insn, 36, 4) << 16; \ + if (decodeBDRAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 200: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 0; \ + tmp |= fieldname(insn, 32, 8) << 16; \ + if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 201: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 202: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 203: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 204: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 205: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 206: \ + tmp = fieldname(insn, 36, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 207: \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 208: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 209: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 210: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 211: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 212: \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 213: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 214: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 215: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 216: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 217: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 218: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 219: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 220: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 221: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 222: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 223: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 224: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 225: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 226: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 227: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 228: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 229: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 230: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 231: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 232: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 233: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 234: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 235: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 236: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 237: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 238: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 239: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 240: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 241: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 20; \ + tmp |= fieldname(insn, 16, 20) << 0; \ + if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 242: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 20; \ + tmp |= fieldname(insn, 16, 20) << 0; \ + if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 243: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 20; \ + tmp |= fieldname(insn, 16, 20) << 0; \ + if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 244: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 20; \ + tmp |= fieldname(insn, 16, 20) << 0; \ + if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 245: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 246: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 247: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 248: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 249: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 250: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 251: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 252: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 253: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 254: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 255: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 256: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 257: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 258: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 259: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 260: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 261: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 262: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 263: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 264: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 265: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 266: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 267: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 268: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 269: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 12); \ + if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 270: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 271: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 272: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 273: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 274: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 275: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 276: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 28, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 277: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 278: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 279: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 280: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 22, 2) << 2; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 281: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3) << 1; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 282: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 20, 1) << 0; \ + tmp |= fieldname(insn, 22, 2) << 2; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 283: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 22, 2) << 2; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 284: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 21, 3) << 1; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 285: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 20, 1) << 0; \ + tmp |= fieldname(insn, 22, 2) << 2; \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 286: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 287: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 288: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 289: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 290: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 291: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 292: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 293: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 294: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 295: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 296: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 297: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 298: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 299: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 300: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 301: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 3); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 302: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 303: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 304: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 305: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 306: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 307: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 308: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 309: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 310: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 311: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 11, 1) << 4; \ + tmp |= fieldname(insn, 36, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 10, 1) << 4; \ + tmp |= fieldname(insn, 32, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 9, 1) << 4; \ + tmp |= fieldname(insn, 28, 4) << 0; \ + if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 20, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 312: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 313: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 314: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 315: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 316: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 317: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 318: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 319: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 320: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 321: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 322: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 323: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 324: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 325: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 326: \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 327: \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 328: \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 329: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 330: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 331: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 332: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 333: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 334: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + tmp |= fieldname(insn, 36, 4) << 16; \ + if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 335: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 336: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 337: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 338: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 339: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 340: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 341: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 342: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 24); \ + if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 343: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 344: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 345: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 346: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 347: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 348: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 349: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 350: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 351: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 352: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 24, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 353: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 354: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 355: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 356: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 357: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 358: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 359: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 360: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 361: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 362: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 363: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 364: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 365: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 366: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 367: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 368: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 369: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 370: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 371: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 372: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 373: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 374: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 375: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 376: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 377: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 378: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 379: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 380: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 381: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 382: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 383: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 384: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 385: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 386: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 8); \ + if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 387: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 388: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 389: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 390: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 391: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 392: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 393: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 394: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 395: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 396: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 397: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 398: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 20); \ + if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 399: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 400: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 28); \ + if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 401: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 24); \ + if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 402: \ + tmp = fieldname(insn, 12, 4); \ + if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 24); \ + if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 8, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 403: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 404: \ + tmp = fieldname(insn, 36, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 16, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 405: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + tmp |= fieldname(insn, 36, 4) << 16; \ + if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 16); \ + if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 32, 4); \ + if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 406: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 16, 16) << 0; \ + tmp |= fieldname(insn, 36, 4) << 16; \ + if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 16) << 0; \ + tmp |= fieldname(insn, 32, 4) << 16; \ + if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + } \ + } + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ + static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + MCRegisterInfo *MRI, int feature) { \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, feature))) \ + Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could \ + * be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ + } + +FieldFromInstruction(fieldFromInstruction, uint32_t) + DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) + DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) + +#endif // MIPS_GET_DISASSEMBLER +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +#define SystemZ_CC 1 +#define SystemZ_FPC 2 +#define SystemZ_A0 3 +#define SystemZ_A1 4 +#define SystemZ_A2 5 +#define SystemZ_A3 6 +#define SystemZ_A4 7 +#define SystemZ_A5 8 +#define SystemZ_A6 9 +#define SystemZ_A7 10 +#define SystemZ_A8 11 +#define SystemZ_A9 12 +#define SystemZ_A10 13 +#define SystemZ_A11 14 +#define SystemZ_A12 15 +#define SystemZ_A13 16 +#define SystemZ_A14 17 +#define SystemZ_A15 18 +#define SystemZ_C0 19 +#define SystemZ_C1 20 +#define SystemZ_C2 21 +#define SystemZ_C3 22 +#define SystemZ_C4 23 +#define SystemZ_C5 24 +#define SystemZ_C6 25 +#define SystemZ_C7 26 +#define SystemZ_C8 27 +#define SystemZ_C9 28 +#define SystemZ_C10 29 +#define SystemZ_C11 30 +#define SystemZ_C12 31 +#define SystemZ_C13 32 +#define SystemZ_C14 33 +#define SystemZ_C15 34 +#define SystemZ_V0 35 +#define SystemZ_V1 36 +#define SystemZ_V2 37 +#define SystemZ_V3 38 +#define SystemZ_V4 39 +#define SystemZ_V5 40 +#define SystemZ_V6 41 +#define SystemZ_V7 42 +#define SystemZ_V8 43 +#define SystemZ_V9 44 +#define SystemZ_V10 45 +#define SystemZ_V11 46 +#define SystemZ_V12 47 +#define SystemZ_V13 48 +#define SystemZ_V14 49 +#define SystemZ_V15 50 +#define SystemZ_V16 51 +#define SystemZ_V17 52 +#define SystemZ_V18 53 +#define SystemZ_V19 54 +#define SystemZ_V20 55 +#define SystemZ_V21 56 +#define SystemZ_V22 57 +#define SystemZ_V23 58 +#define SystemZ_V24 59 +#define SystemZ_V25 60 +#define SystemZ_V26 61 +#define SystemZ_V27 62 +#define SystemZ_V28 63 +#define SystemZ_V29 64 +#define SystemZ_V30 65 +#define SystemZ_V31 66 +#define SystemZ_F0D 67 +#define SystemZ_F1D 68 +#define SystemZ_F2D 69 +#define SystemZ_F3D 70 +#define SystemZ_F4D 71 +#define SystemZ_F5D 72 +#define SystemZ_F6D 73 +#define SystemZ_F7D 74 +#define SystemZ_F8D 75 +#define SystemZ_F9D 76 +#define SystemZ_F10D 77 +#define SystemZ_F11D 78 +#define SystemZ_F12D 79 +#define SystemZ_F13D 80 +#define SystemZ_F14D 81 +#define SystemZ_F15D 82 +#define SystemZ_F16D 83 +#define SystemZ_F17D 84 +#define SystemZ_F18D 85 +#define SystemZ_F19D 86 +#define SystemZ_F20D 87 +#define SystemZ_F21D 88 +#define SystemZ_F22D 89 +#define SystemZ_F23D 90 +#define SystemZ_F24D 91 +#define SystemZ_F25D 92 +#define SystemZ_F26D 93 +#define SystemZ_F27D 94 +#define SystemZ_F28D 95 +#define SystemZ_F29D 96 +#define SystemZ_F30D 97 +#define SystemZ_F31D 98 +#define SystemZ_F0Q 99 +#define SystemZ_F1Q 100 +#define SystemZ_F4Q 101 +#define SystemZ_F5Q 102 +#define SystemZ_F8Q 103 +#define SystemZ_F9Q 104 +#define SystemZ_F12Q 105 +#define SystemZ_F13Q 106 +#define SystemZ_F0S 107 +#define SystemZ_F1S 108 +#define SystemZ_F2S 109 +#define SystemZ_F3S 110 +#define SystemZ_F4S 111 +#define SystemZ_F5S 112 +#define SystemZ_F6S 113 +#define SystemZ_F7S 114 +#define SystemZ_F8S 115 +#define SystemZ_F9S 116 +#define SystemZ_F10S 117 +#define SystemZ_F11S 118 +#define SystemZ_F12S 119 +#define SystemZ_F13S 120 +#define SystemZ_F14S 121 +#define SystemZ_F15S 122 +#define SystemZ_F16S 123 +#define SystemZ_F17S 124 +#define SystemZ_F18S 125 +#define SystemZ_F19S 126 +#define SystemZ_F20S 127 +#define SystemZ_F21S 128 +#define SystemZ_F22S 129 +#define SystemZ_F23S 130 +#define SystemZ_F24S 131 +#define SystemZ_F25S 132 +#define SystemZ_F26S 133 +#define SystemZ_F27S 134 +#define SystemZ_F28S 135 +#define SystemZ_F29S 136 +#define SystemZ_F30S 137 +#define SystemZ_F31S 138 +#define SystemZ_R0D 139 +#define SystemZ_R1D 140 +#define SystemZ_R2D 141 +#define SystemZ_R3D 142 +#define SystemZ_R4D 143 +#define SystemZ_R5D 144 +#define SystemZ_R6D 145 +#define SystemZ_R7D 146 +#define SystemZ_R8D 147 +#define SystemZ_R9D 148 +#define SystemZ_R10D 149 +#define SystemZ_R11D 150 +#define SystemZ_R12D 151 +#define SystemZ_R13D 152 +#define SystemZ_R14D 153 +#define SystemZ_R15D 154 +#define SystemZ_R0H 155 +#define SystemZ_R1H 156 +#define SystemZ_R2H 157 +#define SystemZ_R3H 158 +#define SystemZ_R4H 159 +#define SystemZ_R5H 160 +#define SystemZ_R6H 161 +#define SystemZ_R7H 162 +#define SystemZ_R8H 163 +#define SystemZ_R9H 164 +#define SystemZ_R10H 165 +#define SystemZ_R11H 166 +#define SystemZ_R12H 167 +#define SystemZ_R13H 168 +#define SystemZ_R14H 169 +#define SystemZ_R15H 170 +#define SystemZ_R0L 171 +#define SystemZ_R1L 172 +#define SystemZ_R2L 173 +#define SystemZ_R3L 174 +#define SystemZ_R4L 175 +#define SystemZ_R5L 176 +#define SystemZ_R6L 177 +#define SystemZ_R7L 178 +#define SystemZ_R8L 179 +#define SystemZ_R9L 180 +#define SystemZ_R10L 181 +#define SystemZ_R11L 182 +#define SystemZ_R12L 183 +#define SystemZ_R13L 184 +#define SystemZ_R14L 185 +#define SystemZ_R15L 186 +#define SystemZ_R0Q 187 +#define SystemZ_R2Q 188 +#define SystemZ_R4Q 189 +#define SystemZ_R6Q 190 +#define SystemZ_R8Q 191 +#define SystemZ_R10Q 192 +#define SystemZ_R12Q 193 +#define SystemZ_R14Q 194 +#define SystemZ_NUM_TARGET_REGS 195 + +// Register classes + +#define SystemZ_GRX32BitRegClassID 0 +#define SystemZ_VR32BitRegClassID 1 +#define SystemZ_AR32BitRegClassID 2 +#define SystemZ_FP32BitRegClassID 3 +#define SystemZ_GR32BitRegClassID 4 +#define SystemZ_GRH32BitRegClassID 5 +#define SystemZ_ADDR32BitRegClassID 6 +#define SystemZ_CCRRegClassID 7 +#define SystemZ_FPCRegsRegClassID 8 +#define SystemZ_AnyRegBitRegClassID 9 +#define SystemZ_AnyRegBit_with_subreg_h32_in_FP32BitRegClassID 10 +#define SystemZ_VR64BitRegClassID 11 +#define SystemZ_AnyRegBit_with_subreg_h64RegClassID 12 +#define SystemZ_CR64BitRegClassID 13 +#define SystemZ_FP64BitRegClassID 14 +#define SystemZ_GR64BitRegClassID 15 +#define SystemZ_ADDR64BitRegClassID 16 +#define SystemZ_VR128BitRegClassID 17 +#define SystemZ_VF128BitRegClassID 18 +#define SystemZ_FP128BitRegClassID 19 +#define SystemZ_GR128BitRegClassID 20 +#define SystemZ_ADDR128BitRegClassID 21 + +#endif // GET_REGINFO_ENUM + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +#define SystemZ_PHI 0 +#define SystemZ_INLINEASM 1 +#define SystemZ_INLINEASM_BR 2 +#define SystemZ_CFI_INSTRUCTION 3 +#define SystemZ_EH_LABEL 4 +#define SystemZ_GC_LABEL 5 +#define SystemZ_ANNOTATION_LABEL 6 +#define SystemZ_KILL 7 +#define SystemZ_EXTRACT_SUBREG 8 +#define SystemZ_INSERT_SUBREG 9 +#define SystemZ_IMPLICIT_DEF 10 +#define SystemZ_SUBREG_TO_REG 11 +#define SystemZ_COPY_TO_REGCLASS 12 +#define SystemZ_DBG_VALUE 13 +#define SystemZ_DBG_VALUE_LIST 14 +#define SystemZ_DBG_INSTR_REF 15 +#define SystemZ_DBG_PHI 16 +#define SystemZ_DBG_LABEL 17 +#define SystemZ_REG_SEQUENCE 18 +#define SystemZ_COPY 19 +#define SystemZ_BUNDLE 20 +#define SystemZ_LIFETIME_START 21 +#define SystemZ_LIFETIME_END 22 +#define SystemZ_PSEUDO_PROBE 23 +#define SystemZ_ARITH_FENCE 24 +#define SystemZ_STACKMAP 25 +#define SystemZ_FENTRY_CALL 26 +#define SystemZ_PATCHPOINT 27 +#define SystemZ_LOAD_STACK_GUARD 28 +#define SystemZ_PREALLOCATED_SETUP 29 +#define SystemZ_PREALLOCATED_ARG 30 +#define SystemZ_STATEPOINT 31 +#define SystemZ_LOCAL_ESCAPE 32 +#define SystemZ_FAULTING_OP 33 +#define SystemZ_PATCHABLE_OP 34 +#define SystemZ_PATCHABLE_FUNCTION_ENTER 35 +#define SystemZ_PATCHABLE_RET 36 +#define SystemZ_PATCHABLE_FUNCTION_EXIT 37 +#define SystemZ_PATCHABLE_TAIL_CALL 38 +#define SystemZ_PATCHABLE_EVENT_CALL 39 +#define SystemZ_PATCHABLE_TYPED_EVENT_CALL 40 +#define SystemZ_ICALL_BRANCH_FUNNEL 41 +#define SystemZ_G_ASSERT_SEXT 42 +#define SystemZ_G_ASSERT_ZEXT 43 +#define SystemZ_G_ADD 44 +#define SystemZ_G_SUB 45 +#define SystemZ_G_MUL 46 +#define SystemZ_G_SDIV 47 +#define SystemZ_G_UDIV 48 +#define SystemZ_G_SREM 49 +#define SystemZ_G_UREM 50 +#define SystemZ_G_SDIVREM 51 +#define SystemZ_G_UDIVREM 52 +#define SystemZ_G_AND 53 +#define SystemZ_G_OR 54 +#define SystemZ_G_XOR 55 +#define SystemZ_G_IMPLICIT_DEF 56 +#define SystemZ_G_PHI 57 +#define SystemZ_G_FRAME_INDEX 58 +#define SystemZ_G_GLOBAL_VALUE 59 +#define SystemZ_G_EXTRACT 60 +#define SystemZ_G_UNMERGE_VALUES 61 +#define SystemZ_G_INSERT 62 +#define SystemZ_G_MERGE_VALUES 63 +#define SystemZ_G_BUILD_VECTOR 64 +#define SystemZ_G_BUILD_VECTOR_TRUNC 65 +#define SystemZ_G_CONCAT_VECTORS 66 +#define SystemZ_G_PTRTOINT 67 +#define SystemZ_G_INTTOPTR 68 +#define SystemZ_G_BITCAST 69 +#define SystemZ_G_FREEZE 70 +#define SystemZ_G_INTRINSIC_TRUNC 71 +#define SystemZ_G_INTRINSIC_ROUND 72 +#define SystemZ_G_INTRINSIC_LRINT 73 +#define SystemZ_G_INTRINSIC_ROUNDEVEN 74 +#define SystemZ_G_READCYCLECOUNTER 75 +#define SystemZ_G_LOAD 76 +#define SystemZ_G_SEXTLOAD 77 +#define SystemZ_G_ZEXTLOAD 78 +#define SystemZ_G_INDEXED_LOAD 79 +#define SystemZ_G_INDEXED_SEXTLOAD 80 +#define SystemZ_G_INDEXED_ZEXTLOAD 81 +#define SystemZ_G_STORE 82 +#define SystemZ_G_INDEXED_STORE 83 +#define SystemZ_G_ATOMIC_CMPXCHG_WITH_SUCCESS 84 +#define SystemZ_G_ATOMIC_CMPXCHG 85 +#define SystemZ_G_ATOMICRMW_XCHG 86 +#define SystemZ_G_ATOMICRMW_ADD 87 +#define SystemZ_G_ATOMICRMW_SUB 88 +#define SystemZ_G_ATOMICRMW_AND 89 +#define SystemZ_G_ATOMICRMW_NAND 90 +#define SystemZ_G_ATOMICRMW_OR 91 +#define SystemZ_G_ATOMICRMW_XOR 92 +#define SystemZ_G_ATOMICRMW_MAX 93 +#define SystemZ_G_ATOMICRMW_MIN 94 +#define SystemZ_G_ATOMICRMW_UMAX 95 +#define SystemZ_G_ATOMICRMW_UMIN 96 +#define SystemZ_G_ATOMICRMW_FADD 97 +#define SystemZ_G_ATOMICRMW_FSUB 98 +#define SystemZ_G_FENCE 99 +#define SystemZ_G_BRCOND 100 +#define SystemZ_G_BRINDIRECT 101 +#define SystemZ_G_INTRINSIC 102 +#define SystemZ_G_INTRINSIC_W_SIDE_EFFECTS 103 +#define SystemZ_G_ANYEXT 104 +#define SystemZ_G_TRUNC 105 +#define SystemZ_G_CONSTANT 106 +#define SystemZ_G_FCONSTANT 107 +#define SystemZ_G_VASTART 108 +#define SystemZ_G_VAARG 109 +#define SystemZ_G_SEXT 110 +#define SystemZ_G_SEXT_INREG 111 +#define SystemZ_G_ZEXT 112 +#define SystemZ_G_SHL 113 +#define SystemZ_G_LSHR 114 +#define SystemZ_G_ASHR 115 +#define SystemZ_G_FSHL 116 +#define SystemZ_G_FSHR 117 +#define SystemZ_G_ROTR 118 +#define SystemZ_G_ROTL 119 +#define SystemZ_G_ICMP 120 +#define SystemZ_G_FCMP 121 +#define SystemZ_G_SELECT 122 +#define SystemZ_G_UADDO 123 +#define SystemZ_G_UADDE 124 +#define SystemZ_G_USUBO 125 +#define SystemZ_G_USUBE 126 +#define SystemZ_G_SADDO 127 +#define SystemZ_G_SADDE 128 +#define SystemZ_G_SSUBO 129 +#define SystemZ_G_SSUBE 130 +#define SystemZ_G_UMULO 131 +#define SystemZ_G_SMULO 132 +#define SystemZ_G_UMULH 133 +#define SystemZ_G_SMULH 134 +#define SystemZ_G_UADDSAT 135 +#define SystemZ_G_SADDSAT 136 +#define SystemZ_G_USUBSAT 137 +#define SystemZ_G_SSUBSAT 138 +#define SystemZ_G_USHLSAT 139 +#define SystemZ_G_SSHLSAT 140 +#define SystemZ_G_SMULFIX 141 +#define SystemZ_G_UMULFIX 142 +#define SystemZ_G_SMULFIXSAT 143 +#define SystemZ_G_UMULFIXSAT 144 +#define SystemZ_G_SDIVFIX 145 +#define SystemZ_G_UDIVFIX 146 +#define SystemZ_G_SDIVFIXSAT 147 +#define SystemZ_G_UDIVFIXSAT 148 +#define SystemZ_G_FADD 149 +#define SystemZ_G_FSUB 150 +#define SystemZ_G_FMUL 151 +#define SystemZ_G_FMA 152 +#define SystemZ_G_FMAD 153 +#define SystemZ_G_FDIV 154 +#define SystemZ_G_FREM 155 +#define SystemZ_G_FPOW 156 +#define SystemZ_G_FPOWI 157 +#define SystemZ_G_FEXP 158 +#define SystemZ_G_FEXP2 159 +#define SystemZ_G_FLOG 160 +#define SystemZ_G_FLOG2 161 +#define SystemZ_G_FLOG10 162 +#define SystemZ_G_FNEG 163 +#define SystemZ_G_FPEXT 164 +#define SystemZ_G_FPTRUNC 165 +#define SystemZ_G_FPTOSI 166 +#define SystemZ_G_FPTOUI 167 +#define SystemZ_G_SITOFP 168 +#define SystemZ_G_UITOFP 169 +#define SystemZ_G_FABS 170 +#define SystemZ_G_FCOPYSIGN 171 +#define SystemZ_G_FCANONICALIZE 172 +#define SystemZ_G_FMINNUM 173 +#define SystemZ_G_FMAXNUM 174 +#define SystemZ_G_FMINNUM_IEEE 175 +#define SystemZ_G_FMAXNUM_IEEE 176 +#define SystemZ_G_FMINIMUM 177 +#define SystemZ_G_FMAXIMUM 178 +#define SystemZ_G_PTR_ADD 179 +#define SystemZ_G_PTRMASK 180 +#define SystemZ_G_SMIN 181 +#define SystemZ_G_SMAX 182 +#define SystemZ_G_UMIN 183 +#define SystemZ_G_UMAX 184 +#define SystemZ_G_ABS 185 +#define SystemZ_G_LROUND 186 +#define SystemZ_G_LLROUND 187 +#define SystemZ_G_BR 188 +#define SystemZ_G_BRJT 189 +#define SystemZ_G_INSERT_VECTOR_ELT 190 +#define SystemZ_G_EXTRACT_VECTOR_ELT 191 +#define SystemZ_G_SHUFFLE_VECTOR 192 +#define SystemZ_G_CTTZ 193 +#define SystemZ_G_CTTZ_ZERO_UNDEF 194 +#define SystemZ_G_CTLZ 195 +#define SystemZ_G_CTLZ_ZERO_UNDEF 196 +#define SystemZ_G_CTPOP 197 +#define SystemZ_G_BSWAP 198 +#define SystemZ_G_BITREVERSE 199 +#define SystemZ_G_FCEIL 200 +#define SystemZ_G_FCOS 201 +#define SystemZ_G_FSIN 202 +#define SystemZ_G_FSQRT 203 +#define SystemZ_G_FFLOOR 204 +#define SystemZ_G_FRINT 205 +#define SystemZ_G_FNEARBYINT 206 +#define SystemZ_G_ADDRSPACE_CAST 207 +#define SystemZ_G_BLOCK_ADDR 208 +#define SystemZ_G_JUMP_TABLE 209 +#define SystemZ_G_DYN_STACKALLOC 210 +#define SystemZ_G_STRICT_FADD 211 +#define SystemZ_G_STRICT_FSUB 212 +#define SystemZ_G_STRICT_FMUL 213 +#define SystemZ_G_STRICT_FDIV 214 +#define SystemZ_G_STRICT_FREM 215 +#define SystemZ_G_STRICT_FMA 216 +#define SystemZ_G_STRICT_FSQRT 217 +#define SystemZ_G_READ_REGISTER 218 +#define SystemZ_G_WRITE_REGISTER 219 +#define SystemZ_G_MEMCPY 220 +#define SystemZ_G_MEMCPY_INLINE 221 +#define SystemZ_G_MEMMOVE 222 +#define SystemZ_G_MEMSET 223 +#define SystemZ_G_BZERO 224 +#define SystemZ_G_VECREDUCE_SEQ_FADD 225 +#define SystemZ_G_VECREDUCE_SEQ_FMUL 226 +#define SystemZ_G_VECREDUCE_FADD 227 +#define SystemZ_G_VECREDUCE_FMUL 228 +#define SystemZ_G_VECREDUCE_FMAX 229 +#define SystemZ_G_VECREDUCE_FMIN 230 +#define SystemZ_G_VECREDUCE_ADD 231 +#define SystemZ_G_VECREDUCE_MUL 232 +#define SystemZ_G_VECREDUCE_AND 233 +#define SystemZ_G_VECREDUCE_OR 234 +#define SystemZ_G_VECREDUCE_XOR 235 +#define SystemZ_G_VECREDUCE_SMAX 236 +#define SystemZ_G_VECREDUCE_SMIN 237 +#define SystemZ_G_VECREDUCE_UMAX 238 +#define SystemZ_G_VECREDUCE_UMIN 239 +#define SystemZ_G_SBFX 240 +#define SystemZ_G_UBFX 241 +#define SystemZ_ADB_MemFoldPseudo 242 +#define SystemZ_ADJCALLSTACKDOWN 243 +#define SystemZ_ADJCALLSTACKUP 244 +#define SystemZ_ADJDYNALLOC 245 +#define SystemZ_AEB_MemFoldPseudo 246 +#define SystemZ_AEXT128 247 +#define SystemZ_AFIMux 248 +#define SystemZ_AG_MemFoldPseudo 249 +#define SystemZ_AHIMux 250 +#define SystemZ_AHIMuxK 251 +#define SystemZ_ALG_MemFoldPseudo 252 +#define SystemZ_AL_MemFoldPseudo 253 +#define SystemZ_ATOMIC_CMP_SWAPW 254 +#define SystemZ_ATOMIC_LOADW_AFI 255 +#define SystemZ_ATOMIC_LOADW_AR 256 +#define SystemZ_ATOMIC_LOADW_MAX 257 +#define SystemZ_ATOMIC_LOADW_MIN 258 +#define SystemZ_ATOMIC_LOADW_NILH 259 +#define SystemZ_ATOMIC_LOADW_NILHi 260 +#define SystemZ_ATOMIC_LOADW_NR 261 +#define SystemZ_ATOMIC_LOADW_NRi 262 +#define SystemZ_ATOMIC_LOADW_OILH 263 +#define SystemZ_ATOMIC_LOADW_OR 264 +#define SystemZ_ATOMIC_LOADW_SR 265 +#define SystemZ_ATOMIC_LOADW_UMAX 266 +#define SystemZ_ATOMIC_LOADW_UMIN 267 +#define SystemZ_ATOMIC_LOADW_XILF 268 +#define SystemZ_ATOMIC_LOADW_XR 269 +#define SystemZ_ATOMIC_LOAD_AFI 270 +#define SystemZ_ATOMIC_LOAD_AGFI 271 +#define SystemZ_ATOMIC_LOAD_AGHI 272 +#define SystemZ_ATOMIC_LOAD_AGR 273 +#define SystemZ_ATOMIC_LOAD_AHI 274 +#define SystemZ_ATOMIC_LOAD_AR 275 +#define SystemZ_ATOMIC_LOAD_MAX_32 276 +#define SystemZ_ATOMIC_LOAD_MAX_64 277 +#define SystemZ_ATOMIC_LOAD_MIN_32 278 +#define SystemZ_ATOMIC_LOAD_MIN_64 279 +#define SystemZ_ATOMIC_LOAD_NGR 280 +#define SystemZ_ATOMIC_LOAD_NGRi 281 +#define SystemZ_ATOMIC_LOAD_NIHF64 282 +#define SystemZ_ATOMIC_LOAD_NIHF64i 283 +#define SystemZ_ATOMIC_LOAD_NIHH64 284 +#define SystemZ_ATOMIC_LOAD_NIHH64i 285 +#define SystemZ_ATOMIC_LOAD_NIHL64 286 +#define SystemZ_ATOMIC_LOAD_NIHL64i 287 +#define SystemZ_ATOMIC_LOAD_NILF 288 +#define SystemZ_ATOMIC_LOAD_NILF64 289 +#define SystemZ_ATOMIC_LOAD_NILF64i 290 +#define SystemZ_ATOMIC_LOAD_NILFi 291 +#define SystemZ_ATOMIC_LOAD_NILH 292 +#define SystemZ_ATOMIC_LOAD_NILH64 293 +#define SystemZ_ATOMIC_LOAD_NILH64i 294 +#define SystemZ_ATOMIC_LOAD_NILHi 295 +#define SystemZ_ATOMIC_LOAD_NILL 296 +#define SystemZ_ATOMIC_LOAD_NILL64 297 +#define SystemZ_ATOMIC_LOAD_NILL64i 298 +#define SystemZ_ATOMIC_LOAD_NILLi 299 +#define SystemZ_ATOMIC_LOAD_NR 300 +#define SystemZ_ATOMIC_LOAD_NRi 301 +#define SystemZ_ATOMIC_LOAD_OGR 302 +#define SystemZ_ATOMIC_LOAD_OIHF64 303 +#define SystemZ_ATOMIC_LOAD_OIHH64 304 +#define SystemZ_ATOMIC_LOAD_OIHL64 305 +#define SystemZ_ATOMIC_LOAD_OILF 306 +#define SystemZ_ATOMIC_LOAD_OILF64 307 +#define SystemZ_ATOMIC_LOAD_OILH 308 +#define SystemZ_ATOMIC_LOAD_OILH64 309 +#define SystemZ_ATOMIC_LOAD_OILL 310 +#define SystemZ_ATOMIC_LOAD_OILL64 311 +#define SystemZ_ATOMIC_LOAD_OR 312 +#define SystemZ_ATOMIC_LOAD_SGR 313 +#define SystemZ_ATOMIC_LOAD_SR 314 +#define SystemZ_ATOMIC_LOAD_UMAX_32 315 +#define SystemZ_ATOMIC_LOAD_UMAX_64 316 +#define SystemZ_ATOMIC_LOAD_UMIN_32 317 +#define SystemZ_ATOMIC_LOAD_UMIN_64 318 +#define SystemZ_ATOMIC_LOAD_XGR 319 +#define SystemZ_ATOMIC_LOAD_XIHF64 320 +#define SystemZ_ATOMIC_LOAD_XILF 321 +#define SystemZ_ATOMIC_LOAD_XILF64 322 +#define SystemZ_ATOMIC_LOAD_XR 323 +#define SystemZ_ATOMIC_SWAPW 324 +#define SystemZ_ATOMIC_SWAP_32 325 +#define SystemZ_ATOMIC_SWAP_64 326 +#define SystemZ_A_MemFoldPseudo 327 +#define SystemZ_CFIMux 328 +#define SystemZ_CGIBCall 329 +#define SystemZ_CGIBReturn 330 +#define SystemZ_CGRBCall 331 +#define SystemZ_CGRBReturn 332 +#define SystemZ_CHIMux 333 +#define SystemZ_CIBCall 334 +#define SystemZ_CIBReturn 335 +#define SystemZ_CLCImm 336 +#define SystemZ_CLCReg 337 +#define SystemZ_CLFIMux 338 +#define SystemZ_CLGIBCall 339 +#define SystemZ_CLGIBReturn 340 +#define SystemZ_CLGRBCall 341 +#define SystemZ_CLGRBReturn 342 +#define SystemZ_CLIBCall 343 +#define SystemZ_CLIBReturn 344 +#define SystemZ_CLMux 345 +#define SystemZ_CLRBCall 346 +#define SystemZ_CLRBReturn 347 +#define SystemZ_CLSTLoop 348 +#define SystemZ_CMux 349 +#define SystemZ_CRBCall 350 +#define SystemZ_CRBReturn 351 +#define SystemZ_CallBASR 352 +#define SystemZ_CallBASR_XPLINK64 353 +#define SystemZ_CallBCR 354 +#define SystemZ_CallBR 355 +#define SystemZ_CallBRASL 356 +#define SystemZ_CallBRASL_XPLINK64 357 +#define SystemZ_CallBRCL 358 +#define SystemZ_CallJG 359 +#define SystemZ_CondReturn 360 +#define SystemZ_CondStore16 361 +#define SystemZ_CondStore16Inv 362 +#define SystemZ_CondStore16Mux 363 +#define SystemZ_CondStore16MuxInv 364 +#define SystemZ_CondStore32 365 +#define SystemZ_CondStore32Inv 366 +#define SystemZ_CondStore32Mux 367 +#define SystemZ_CondStore32MuxInv 368 +#define SystemZ_CondStore64 369 +#define SystemZ_CondStore64Inv 370 +#define SystemZ_CondStore8 371 +#define SystemZ_CondStore8Inv 372 +#define SystemZ_CondStore8Mux 373 +#define SystemZ_CondStore8MuxInv 374 +#define SystemZ_CondStoreF32 375 +#define SystemZ_CondStoreF32Inv 376 +#define SystemZ_CondStoreF64 377 +#define SystemZ_CondStoreF64Inv 378 +#define SystemZ_CondTrap 379 +#define SystemZ_DDB_MemFoldPseudo 380 +#define SystemZ_DEB_MemFoldPseudo 381 +#define SystemZ_EXRL_Pseudo 382 +#define SystemZ_GOT 383 +#define SystemZ_IIFMux 384 +#define SystemZ_IIHF64 385 +#define SystemZ_IIHH64 386 +#define SystemZ_IIHL64 387 +#define SystemZ_IIHMux 388 +#define SystemZ_IILF64 389 +#define SystemZ_IILH64 390 +#define SystemZ_IILL64 391 +#define SystemZ_IILMux 392 +#define SystemZ_L128 393 +#define SystemZ_LBMux 394 +#define SystemZ_LEFR 395 +#define SystemZ_LFER 396 +#define SystemZ_LHIMux 397 +#define SystemZ_LHMux 398 +#define SystemZ_LLCMux 399 +#define SystemZ_LLCRMux 400 +#define SystemZ_LLHMux 401 +#define SystemZ_LLHRMux 402 +#define SystemZ_LMux 403 +#define SystemZ_LOCG_MemFoldPseudo 404 +#define SystemZ_LOCHIMux 405 +#define SystemZ_LOCMux 406 +#define SystemZ_LOCMux_MemFoldPseudo 407 +#define SystemZ_LOCRMux 408 +#define SystemZ_LTDBRCompare_VecPseudo 409 +#define SystemZ_LTEBRCompare_VecPseudo 410 +#define SystemZ_LTXBRCompare_VecPseudo 411 +#define SystemZ_LX 412 +#define SystemZ_MADB_MemFoldPseudo 413 +#define SystemZ_MAEB_MemFoldPseudo 414 +#define SystemZ_MDB_MemFoldPseudo 415 +#define SystemZ_MEEB_MemFoldPseudo 416 +#define SystemZ_MSC_MemFoldPseudo 417 +#define SystemZ_MSDB_MemFoldPseudo 418 +#define SystemZ_MSEB_MemFoldPseudo 419 +#define SystemZ_MSGC_MemFoldPseudo 420 +#define SystemZ_MVCImm 421 +#define SystemZ_MVCReg 422 +#define SystemZ_MVSTLoop 423 +#define SystemZ_MemBarrier 424 +#define SystemZ_NCImm 425 +#define SystemZ_NCReg 426 +#define SystemZ_NG_MemFoldPseudo 427 +#define SystemZ_NIFMux 428 +#define SystemZ_NIHF64 429 +#define SystemZ_NIHH64 430 +#define SystemZ_NIHL64 431 +#define SystemZ_NIHMux 432 +#define SystemZ_NILF64 433 +#define SystemZ_NILH64 434 +#define SystemZ_NILL64 435 +#define SystemZ_NILMux 436 +#define SystemZ_N_MemFoldPseudo 437 +#define SystemZ_OCImm 438 +#define SystemZ_OCReg 439 +#define SystemZ_OG_MemFoldPseudo 440 +#define SystemZ_OIFMux 441 +#define SystemZ_OIHF64 442 +#define SystemZ_OIHH64 443 +#define SystemZ_OIHL64 444 +#define SystemZ_OIHMux 445 +#define SystemZ_OILF64 446 +#define SystemZ_OILH64 447 +#define SystemZ_OILL64 448 +#define SystemZ_OILMux 449 +#define SystemZ_O_MemFoldPseudo 450 +#define SystemZ_PAIR128 451 +#define SystemZ_PROBED_ALLOCA 452 +#define SystemZ_PROBED_STACKALLOC 453 +#define SystemZ_RISBHH 454 +#define SystemZ_RISBHL 455 +#define SystemZ_RISBLH 456 +#define SystemZ_RISBLL 457 +#define SystemZ_RISBMux 458 +#define SystemZ_Return 459 +#define SystemZ_SDB_MemFoldPseudo 460 +#define SystemZ_SEB_MemFoldPseudo 461 +#define SystemZ_SELRMux 462 +#define SystemZ_SG_MemFoldPseudo 463 +#define SystemZ_SLG_MemFoldPseudo 464 +#define SystemZ_SL_MemFoldPseudo 465 +#define SystemZ_SRSTLoop 466 +#define SystemZ_ST128 467 +#define SystemZ_STCMux 468 +#define SystemZ_STHMux 469 +#define SystemZ_STMux 470 +#define SystemZ_STOCMux 471 +#define SystemZ_STX 472 +#define SystemZ_S_MemFoldPseudo 473 +#define SystemZ_Select32 474 +#define SystemZ_Select64 475 +#define SystemZ_SelectF128 476 +#define SystemZ_SelectF32 477 +#define SystemZ_SelectF64 478 +#define SystemZ_SelectVR128 479 +#define SystemZ_SelectVR32 480 +#define SystemZ_SelectVR64 481 +#define SystemZ_Serialize 482 +#define SystemZ_TBEGIN_nofloat 483 +#define SystemZ_TLS_GDCALL 484 +#define SystemZ_TLS_LDCALL 485 +#define SystemZ_TMHH64 486 +#define SystemZ_TMHL64 487 +#define SystemZ_TMHMux 488 +#define SystemZ_TMLH64 489 +#define SystemZ_TMLL64 490 +#define SystemZ_TMLMux 491 +#define SystemZ_Trap 492 +#define SystemZ_VL32 493 +#define SystemZ_VL64 494 +#define SystemZ_VLR32 495 +#define SystemZ_VLR64 496 +#define SystemZ_VLVGP32 497 +#define SystemZ_VST32 498 +#define SystemZ_VST64 499 +#define SystemZ_XCImm 500 +#define SystemZ_XCReg 501 +#define SystemZ_XG_MemFoldPseudo 502 +#define SystemZ_XIFMux 503 +#define SystemZ_XIHF64 504 +#define SystemZ_XILF64 505 +#define SystemZ_X_MemFoldPseudo 506 +#define SystemZ_ZEXT128 507 +#define SystemZ_A 508 +#define SystemZ_AD 509 +#define SystemZ_ADB 510 +#define SystemZ_ADBR 511 +#define SystemZ_ADR 512 +#define SystemZ_ADTR 513 +#define SystemZ_ADTRA 514 +#define SystemZ_AE 515 +#define SystemZ_AEB 516 +#define SystemZ_AEBR 517 +#define SystemZ_AER 518 +#define SystemZ_AFI 519 +#define SystemZ_AG 520 +#define SystemZ_AGF 521 +#define SystemZ_AGFI 522 +#define SystemZ_AGFR 523 +#define SystemZ_AGH 524 +#define SystemZ_AGHI 525 +#define SystemZ_AGHIK 526 +#define SystemZ_AGR 527 +#define SystemZ_AGRK 528 +#define SystemZ_AGSI 529 +#define SystemZ_AH 530 +#define SystemZ_AHHHR 531 +#define SystemZ_AHHLR 532 +#define SystemZ_AHI 533 +#define SystemZ_AHIK 534 +#define SystemZ_AHY 535 +#define SystemZ_AIH 536 +#define SystemZ_AL 537 +#define SystemZ_ALC 538 +#define SystemZ_ALCG 539 +#define SystemZ_ALCGR 540 +#define SystemZ_ALCR 541 +#define SystemZ_ALFI 542 +#define SystemZ_ALG 543 +#define SystemZ_ALGF 544 +#define SystemZ_ALGFI 545 +#define SystemZ_ALGFR 546 +#define SystemZ_ALGHSIK 547 +#define SystemZ_ALGR 548 +#define SystemZ_ALGRK 549 +#define SystemZ_ALGSI 550 +#define SystemZ_ALHHHR 551 +#define SystemZ_ALHHLR 552 +#define SystemZ_ALHSIK 553 +#define SystemZ_ALR 554 +#define SystemZ_ALRK 555 +#define SystemZ_ALSI 556 +#define SystemZ_ALSIH 557 +#define SystemZ_ALSIHN 558 +#define SystemZ_ALY 559 +#define SystemZ_AP 560 +#define SystemZ_AR 561 +#define SystemZ_ARK 562 +#define SystemZ_ASI 563 +#define SystemZ_AU 564 +#define SystemZ_AUR 565 +#define SystemZ_AW 566 +#define SystemZ_AWR 567 +#define SystemZ_AXBR 568 +#define SystemZ_AXR 569 +#define SystemZ_AXTR 570 +#define SystemZ_AXTRA 571 +#define SystemZ_AY 572 +#define SystemZ_B 573 +#define SystemZ_BAKR 574 +#define SystemZ_BAL 575 +#define SystemZ_BALR 576 +#define SystemZ_BAS 577 +#define SystemZ_BASR 578 +#define SystemZ_BASSM 579 +#define SystemZ_BAsmE 580 +#define SystemZ_BAsmH 581 +#define SystemZ_BAsmHE 582 +#define SystemZ_BAsmL 583 +#define SystemZ_BAsmLE 584 +#define SystemZ_BAsmLH 585 +#define SystemZ_BAsmM 586 +#define SystemZ_BAsmNE 587 +#define SystemZ_BAsmNH 588 +#define SystemZ_BAsmNHE 589 +#define SystemZ_BAsmNL 590 +#define SystemZ_BAsmNLE 591 +#define SystemZ_BAsmNLH 592 +#define SystemZ_BAsmNM 593 +#define SystemZ_BAsmNO 594 +#define SystemZ_BAsmNP 595 +#define SystemZ_BAsmNZ 596 +#define SystemZ_BAsmO 597 +#define SystemZ_BAsmP 598 +#define SystemZ_BAsmZ 599 +#define SystemZ_BC 600 +#define SystemZ_BCAsm 601 +#define SystemZ_BCR 602 +#define SystemZ_BCRAsm 603 +#define SystemZ_BCT 604 +#define SystemZ_BCTG 605 +#define SystemZ_BCTGR 606 +#define SystemZ_BCTR 607 +#define SystemZ_BI 608 +#define SystemZ_BIAsmE 609 +#define SystemZ_BIAsmH 610 +#define SystemZ_BIAsmHE 611 +#define SystemZ_BIAsmL 612 +#define SystemZ_BIAsmLE 613 +#define SystemZ_BIAsmLH 614 +#define SystemZ_BIAsmM 615 +#define SystemZ_BIAsmNE 616 +#define SystemZ_BIAsmNH 617 +#define SystemZ_BIAsmNHE 618 +#define SystemZ_BIAsmNL 619 +#define SystemZ_BIAsmNLE 620 +#define SystemZ_BIAsmNLH 621 +#define SystemZ_BIAsmNM 622 +#define SystemZ_BIAsmNO 623 +#define SystemZ_BIAsmNP 624 +#define SystemZ_BIAsmNZ 625 +#define SystemZ_BIAsmO 626 +#define SystemZ_BIAsmP 627 +#define SystemZ_BIAsmZ 628 +#define SystemZ_BIC 629 +#define SystemZ_BICAsm 630 +#define SystemZ_BPP 631 +#define SystemZ_BPRP 632 +#define SystemZ_BR 633 +#define SystemZ_BRAS 634 +#define SystemZ_BRASL 635 +#define SystemZ_BRAsmE 636 +#define SystemZ_BRAsmH 637 +#define SystemZ_BRAsmHE 638 +#define SystemZ_BRAsmL 639 +#define SystemZ_BRAsmLE 640 +#define SystemZ_BRAsmLH 641 +#define SystemZ_BRAsmM 642 +#define SystemZ_BRAsmNE 643 +#define SystemZ_BRAsmNH 644 +#define SystemZ_BRAsmNHE 645 +#define SystemZ_BRAsmNL 646 +#define SystemZ_BRAsmNLE 647 +#define SystemZ_BRAsmNLH 648 +#define SystemZ_BRAsmNM 649 +#define SystemZ_BRAsmNO 650 +#define SystemZ_BRAsmNP 651 +#define SystemZ_BRAsmNZ 652 +#define SystemZ_BRAsmO 653 +#define SystemZ_BRAsmP 654 +#define SystemZ_BRAsmZ 655 +#define SystemZ_BRC 656 +#define SystemZ_BRCAsm 657 +#define SystemZ_BRCL 658 +#define SystemZ_BRCLAsm 659 +#define SystemZ_BRCT 660 +#define SystemZ_BRCTG 661 +#define SystemZ_BRCTH 662 +#define SystemZ_BRXH 663 +#define SystemZ_BRXHG 664 +#define SystemZ_BRXLE 665 +#define SystemZ_BRXLG 666 +#define SystemZ_BSA 667 +#define SystemZ_BSG 668 +#define SystemZ_BSM 669 +#define SystemZ_BXH 670 +#define SystemZ_BXHG 671 +#define SystemZ_BXLE 672 +#define SystemZ_BXLEG 673 +#define SystemZ_C 674 +#define SystemZ_CD 675 +#define SystemZ_CDB 676 +#define SystemZ_CDBR 677 +#define SystemZ_CDFBR 678 +#define SystemZ_CDFBRA 679 +#define SystemZ_CDFR 680 +#define SystemZ_CDFTR 681 +#define SystemZ_CDGBR 682 +#define SystemZ_CDGBRA 683 +#define SystemZ_CDGR 684 +#define SystemZ_CDGTR 685 +#define SystemZ_CDGTRA 686 +#define SystemZ_CDLFBR 687 +#define SystemZ_CDLFTR 688 +#define SystemZ_CDLGBR 689 +#define SystemZ_CDLGTR 690 +#define SystemZ_CDPT 691 +#define SystemZ_CDR 692 +#define SystemZ_CDS 693 +#define SystemZ_CDSG 694 +#define SystemZ_CDSTR 695 +#define SystemZ_CDSY 696 +#define SystemZ_CDTR 697 +#define SystemZ_CDUTR 698 +#define SystemZ_CDZT 699 +#define SystemZ_CE 700 +#define SystemZ_CEB 701 +#define SystemZ_CEBR 702 +#define SystemZ_CEDTR 703 +#define SystemZ_CEFBR 704 +#define SystemZ_CEFBRA 705 +#define SystemZ_CEFR 706 +#define SystemZ_CEGBR 707 +#define SystemZ_CEGBRA 708 +#define SystemZ_CEGR 709 +#define SystemZ_CELFBR 710 +#define SystemZ_CELGBR 711 +#define SystemZ_CER 712 +#define SystemZ_CEXTR 713 +#define SystemZ_CFC 714 +#define SystemZ_CFDBR 715 +#define SystemZ_CFDBRA 716 +#define SystemZ_CFDR 717 +#define SystemZ_CFDTR 718 +#define SystemZ_CFEBR 719 +#define SystemZ_CFEBRA 720 +#define SystemZ_CFER 721 +#define SystemZ_CFI 722 +#define SystemZ_CFXBR 723 +#define SystemZ_CFXBRA 724 +#define SystemZ_CFXR 725 +#define SystemZ_CFXTR 726 +#define SystemZ_CG 727 +#define SystemZ_CGDBR 728 +#define SystemZ_CGDBRA 729 +#define SystemZ_CGDR 730 +#define SystemZ_CGDTR 731 +#define SystemZ_CGDTRA 732 +#define SystemZ_CGEBR 733 +#define SystemZ_CGEBRA 734 +#define SystemZ_CGER 735 +#define SystemZ_CGF 736 +#define SystemZ_CGFI 737 +#define SystemZ_CGFR 738 +#define SystemZ_CGFRL 739 +#define SystemZ_CGH 740 +#define SystemZ_CGHI 741 +#define SystemZ_CGHRL 742 +#define SystemZ_CGHSI 743 +#define SystemZ_CGIB 744 +#define SystemZ_CGIBAsm 745 +#define SystemZ_CGIBAsmE 746 +#define SystemZ_CGIBAsmH 747 +#define SystemZ_CGIBAsmHE 748 +#define SystemZ_CGIBAsmL 749 +#define SystemZ_CGIBAsmLE 750 +#define SystemZ_CGIBAsmLH 751 +#define SystemZ_CGIBAsmNE 752 +#define SystemZ_CGIBAsmNH 753 +#define SystemZ_CGIBAsmNHE 754 +#define SystemZ_CGIBAsmNL 755 +#define SystemZ_CGIBAsmNLE 756 +#define SystemZ_CGIBAsmNLH 757 +#define SystemZ_CGIJ 758 +#define SystemZ_CGIJAsm 759 +#define SystemZ_CGIJAsmE 760 +#define SystemZ_CGIJAsmH 761 +#define SystemZ_CGIJAsmHE 762 +#define SystemZ_CGIJAsmL 763 +#define SystemZ_CGIJAsmLE 764 +#define SystemZ_CGIJAsmLH 765 +#define SystemZ_CGIJAsmNE 766 +#define SystemZ_CGIJAsmNH 767 +#define SystemZ_CGIJAsmNHE 768 +#define SystemZ_CGIJAsmNL 769 +#define SystemZ_CGIJAsmNLE 770 +#define SystemZ_CGIJAsmNLH 771 +#define SystemZ_CGIT 772 +#define SystemZ_CGITAsm 773 +#define SystemZ_CGITAsmE 774 +#define SystemZ_CGITAsmH 775 +#define SystemZ_CGITAsmHE 776 +#define SystemZ_CGITAsmL 777 +#define SystemZ_CGITAsmLE 778 +#define SystemZ_CGITAsmLH 779 +#define SystemZ_CGITAsmNE 780 +#define SystemZ_CGITAsmNH 781 +#define SystemZ_CGITAsmNHE 782 +#define SystemZ_CGITAsmNL 783 +#define SystemZ_CGITAsmNLE 784 +#define SystemZ_CGITAsmNLH 785 +#define SystemZ_CGR 786 +#define SystemZ_CGRB 787 +#define SystemZ_CGRBAsm 788 +#define SystemZ_CGRBAsmE 789 +#define SystemZ_CGRBAsmH 790 +#define SystemZ_CGRBAsmHE 791 +#define SystemZ_CGRBAsmL 792 +#define SystemZ_CGRBAsmLE 793 +#define SystemZ_CGRBAsmLH 794 +#define SystemZ_CGRBAsmNE 795 +#define SystemZ_CGRBAsmNH 796 +#define SystemZ_CGRBAsmNHE 797 +#define SystemZ_CGRBAsmNL 798 +#define SystemZ_CGRBAsmNLE 799 +#define SystemZ_CGRBAsmNLH 800 +#define SystemZ_CGRJ 801 +#define SystemZ_CGRJAsm 802 +#define SystemZ_CGRJAsmE 803 +#define SystemZ_CGRJAsmH 804 +#define SystemZ_CGRJAsmHE 805 +#define SystemZ_CGRJAsmL 806 +#define SystemZ_CGRJAsmLE 807 +#define SystemZ_CGRJAsmLH 808 +#define SystemZ_CGRJAsmNE 809 +#define SystemZ_CGRJAsmNH 810 +#define SystemZ_CGRJAsmNHE 811 +#define SystemZ_CGRJAsmNL 812 +#define SystemZ_CGRJAsmNLE 813 +#define SystemZ_CGRJAsmNLH 814 +#define SystemZ_CGRL 815 +#define SystemZ_CGRT 816 +#define SystemZ_CGRTAsm 817 +#define SystemZ_CGRTAsmE 818 +#define SystemZ_CGRTAsmH 819 +#define SystemZ_CGRTAsmHE 820 +#define SystemZ_CGRTAsmL 821 +#define SystemZ_CGRTAsmLE 822 +#define SystemZ_CGRTAsmLH 823 +#define SystemZ_CGRTAsmNE 824 +#define SystemZ_CGRTAsmNH 825 +#define SystemZ_CGRTAsmNHE 826 +#define SystemZ_CGRTAsmNL 827 +#define SystemZ_CGRTAsmNLE 828 +#define SystemZ_CGRTAsmNLH 829 +#define SystemZ_CGXBR 830 +#define SystemZ_CGXBRA 831 +#define SystemZ_CGXR 832 +#define SystemZ_CGXTR 833 +#define SystemZ_CGXTRA 834 +#define SystemZ_CH 835 +#define SystemZ_CHF 836 +#define SystemZ_CHHR 837 +#define SystemZ_CHHSI 838 +#define SystemZ_CHI 839 +#define SystemZ_CHLR 840 +#define SystemZ_CHRL 841 +#define SystemZ_CHSI 842 +#define SystemZ_CHY 843 +#define SystemZ_CIB 844 +#define SystemZ_CIBAsm 845 +#define SystemZ_CIBAsmE 846 +#define SystemZ_CIBAsmH 847 +#define SystemZ_CIBAsmHE 848 +#define SystemZ_CIBAsmL 849 +#define SystemZ_CIBAsmLE 850 +#define SystemZ_CIBAsmLH 851 +#define SystemZ_CIBAsmNE 852 +#define SystemZ_CIBAsmNH 853 +#define SystemZ_CIBAsmNHE 854 +#define SystemZ_CIBAsmNL 855 +#define SystemZ_CIBAsmNLE 856 +#define SystemZ_CIBAsmNLH 857 +#define SystemZ_CIH 858 +#define SystemZ_CIJ 859 +#define SystemZ_CIJAsm 860 +#define SystemZ_CIJAsmE 861 +#define SystemZ_CIJAsmH 862 +#define SystemZ_CIJAsmHE 863 +#define SystemZ_CIJAsmL 864 +#define SystemZ_CIJAsmLE 865 +#define SystemZ_CIJAsmLH 866 +#define SystemZ_CIJAsmNE 867 +#define SystemZ_CIJAsmNH 868 +#define SystemZ_CIJAsmNHE 869 +#define SystemZ_CIJAsmNL 870 +#define SystemZ_CIJAsmNLE 871 +#define SystemZ_CIJAsmNLH 872 +#define SystemZ_CIT 873 +#define SystemZ_CITAsm 874 +#define SystemZ_CITAsmE 875 +#define SystemZ_CITAsmH 876 +#define SystemZ_CITAsmHE 877 +#define SystemZ_CITAsmL 878 +#define SystemZ_CITAsmLE 879 +#define SystemZ_CITAsmLH 880 +#define SystemZ_CITAsmNE 881 +#define SystemZ_CITAsmNH 882 +#define SystemZ_CITAsmNHE 883 +#define SystemZ_CITAsmNL 884 +#define SystemZ_CITAsmNLE 885 +#define SystemZ_CITAsmNLH 886 +#define SystemZ_CKSM 887 +#define SystemZ_CL 888 +#define SystemZ_CLC 889 +#define SystemZ_CLCL 890 +#define SystemZ_CLCLE 891 +#define SystemZ_CLCLU 892 +#define SystemZ_CLFDBR 893 +#define SystemZ_CLFDTR 894 +#define SystemZ_CLFEBR 895 +#define SystemZ_CLFHSI 896 +#define SystemZ_CLFI 897 +#define SystemZ_CLFIT 898 +#define SystemZ_CLFITAsm 899 +#define SystemZ_CLFITAsmE 900 +#define SystemZ_CLFITAsmH 901 +#define SystemZ_CLFITAsmHE 902 +#define SystemZ_CLFITAsmL 903 +#define SystemZ_CLFITAsmLE 904 +#define SystemZ_CLFITAsmLH 905 +#define SystemZ_CLFITAsmNE 906 +#define SystemZ_CLFITAsmNH 907 +#define SystemZ_CLFITAsmNHE 908 +#define SystemZ_CLFITAsmNL 909 +#define SystemZ_CLFITAsmNLE 910 +#define SystemZ_CLFITAsmNLH 911 +#define SystemZ_CLFXBR 912 +#define SystemZ_CLFXTR 913 +#define SystemZ_CLG 914 +#define SystemZ_CLGDBR 915 +#define SystemZ_CLGDTR 916 +#define SystemZ_CLGEBR 917 +#define SystemZ_CLGF 918 +#define SystemZ_CLGFI 919 +#define SystemZ_CLGFR 920 +#define SystemZ_CLGFRL 921 +#define SystemZ_CLGHRL 922 +#define SystemZ_CLGHSI 923 +#define SystemZ_CLGIB 924 +#define SystemZ_CLGIBAsm 925 +#define SystemZ_CLGIBAsmE 926 +#define SystemZ_CLGIBAsmH 927 +#define SystemZ_CLGIBAsmHE 928 +#define SystemZ_CLGIBAsmL 929 +#define SystemZ_CLGIBAsmLE 930 +#define SystemZ_CLGIBAsmLH 931 +#define SystemZ_CLGIBAsmNE 932 +#define SystemZ_CLGIBAsmNH 933 +#define SystemZ_CLGIBAsmNHE 934 +#define SystemZ_CLGIBAsmNL 935 +#define SystemZ_CLGIBAsmNLE 936 +#define SystemZ_CLGIBAsmNLH 937 +#define SystemZ_CLGIJ 938 +#define SystemZ_CLGIJAsm 939 +#define SystemZ_CLGIJAsmE 940 +#define SystemZ_CLGIJAsmH 941 +#define SystemZ_CLGIJAsmHE 942 +#define SystemZ_CLGIJAsmL 943 +#define SystemZ_CLGIJAsmLE 944 +#define SystemZ_CLGIJAsmLH 945 +#define SystemZ_CLGIJAsmNE 946 +#define SystemZ_CLGIJAsmNH 947 +#define SystemZ_CLGIJAsmNHE 948 +#define SystemZ_CLGIJAsmNL 949 +#define SystemZ_CLGIJAsmNLE 950 +#define SystemZ_CLGIJAsmNLH 951 +#define SystemZ_CLGIT 952 +#define SystemZ_CLGITAsm 953 +#define SystemZ_CLGITAsmE 954 +#define SystemZ_CLGITAsmH 955 +#define SystemZ_CLGITAsmHE 956 +#define SystemZ_CLGITAsmL 957 +#define SystemZ_CLGITAsmLE 958 +#define SystemZ_CLGITAsmLH 959 +#define SystemZ_CLGITAsmNE 960 +#define SystemZ_CLGITAsmNH 961 +#define SystemZ_CLGITAsmNHE 962 +#define SystemZ_CLGITAsmNL 963 +#define SystemZ_CLGITAsmNLE 964 +#define SystemZ_CLGITAsmNLH 965 +#define SystemZ_CLGR 966 +#define SystemZ_CLGRB 967 +#define SystemZ_CLGRBAsm 968 +#define SystemZ_CLGRBAsmE 969 +#define SystemZ_CLGRBAsmH 970 +#define SystemZ_CLGRBAsmHE 971 +#define SystemZ_CLGRBAsmL 972 +#define SystemZ_CLGRBAsmLE 973 +#define SystemZ_CLGRBAsmLH 974 +#define SystemZ_CLGRBAsmNE 975 +#define SystemZ_CLGRBAsmNH 976 +#define SystemZ_CLGRBAsmNHE 977 +#define SystemZ_CLGRBAsmNL 978 +#define SystemZ_CLGRBAsmNLE 979 +#define SystemZ_CLGRBAsmNLH 980 +#define SystemZ_CLGRJ 981 +#define SystemZ_CLGRJAsm 982 +#define SystemZ_CLGRJAsmE 983 +#define SystemZ_CLGRJAsmH 984 +#define SystemZ_CLGRJAsmHE 985 +#define SystemZ_CLGRJAsmL 986 +#define SystemZ_CLGRJAsmLE 987 +#define SystemZ_CLGRJAsmLH 988 +#define SystemZ_CLGRJAsmNE 989 +#define SystemZ_CLGRJAsmNH 990 +#define SystemZ_CLGRJAsmNHE 991 +#define SystemZ_CLGRJAsmNL 992 +#define SystemZ_CLGRJAsmNLE 993 +#define SystemZ_CLGRJAsmNLH 994 +#define SystemZ_CLGRL 995 +#define SystemZ_CLGRT 996 +#define SystemZ_CLGRTAsm 997 +#define SystemZ_CLGRTAsmE 998 +#define SystemZ_CLGRTAsmH 999 +#define SystemZ_CLGRTAsmHE 1000 +#define SystemZ_CLGRTAsmL 1001 +#define SystemZ_CLGRTAsmLE 1002 +#define SystemZ_CLGRTAsmLH 1003 +#define SystemZ_CLGRTAsmNE 1004 +#define SystemZ_CLGRTAsmNH 1005 +#define SystemZ_CLGRTAsmNHE 1006 +#define SystemZ_CLGRTAsmNL 1007 +#define SystemZ_CLGRTAsmNLE 1008 +#define SystemZ_CLGRTAsmNLH 1009 +#define SystemZ_CLGT 1010 +#define SystemZ_CLGTAsm 1011 +#define SystemZ_CLGTAsmE 1012 +#define SystemZ_CLGTAsmH 1013 +#define SystemZ_CLGTAsmHE 1014 +#define SystemZ_CLGTAsmL 1015 +#define SystemZ_CLGTAsmLE 1016 +#define SystemZ_CLGTAsmLH 1017 +#define SystemZ_CLGTAsmNE 1018 +#define SystemZ_CLGTAsmNH 1019 +#define SystemZ_CLGTAsmNHE 1020 +#define SystemZ_CLGTAsmNL 1021 +#define SystemZ_CLGTAsmNLE 1022 +#define SystemZ_CLGTAsmNLH 1023 +#define SystemZ_CLGXBR 1024 +#define SystemZ_CLGXTR 1025 +#define SystemZ_CLHF 1026 +#define SystemZ_CLHHR 1027 +#define SystemZ_CLHHSI 1028 +#define SystemZ_CLHLR 1029 +#define SystemZ_CLHRL 1030 +#define SystemZ_CLI 1031 +#define SystemZ_CLIB 1032 +#define SystemZ_CLIBAsm 1033 +#define SystemZ_CLIBAsmE 1034 +#define SystemZ_CLIBAsmH 1035 +#define SystemZ_CLIBAsmHE 1036 +#define SystemZ_CLIBAsmL 1037 +#define SystemZ_CLIBAsmLE 1038 +#define SystemZ_CLIBAsmLH 1039 +#define SystemZ_CLIBAsmNE 1040 +#define SystemZ_CLIBAsmNH 1041 +#define SystemZ_CLIBAsmNHE 1042 +#define SystemZ_CLIBAsmNL 1043 +#define SystemZ_CLIBAsmNLE 1044 +#define SystemZ_CLIBAsmNLH 1045 +#define SystemZ_CLIH 1046 +#define SystemZ_CLIJ 1047 +#define SystemZ_CLIJAsm 1048 +#define SystemZ_CLIJAsmE 1049 +#define SystemZ_CLIJAsmH 1050 +#define SystemZ_CLIJAsmHE 1051 +#define SystemZ_CLIJAsmL 1052 +#define SystemZ_CLIJAsmLE 1053 +#define SystemZ_CLIJAsmLH 1054 +#define SystemZ_CLIJAsmNE 1055 +#define SystemZ_CLIJAsmNH 1056 +#define SystemZ_CLIJAsmNHE 1057 +#define SystemZ_CLIJAsmNL 1058 +#define SystemZ_CLIJAsmNLE 1059 +#define SystemZ_CLIJAsmNLH 1060 +#define SystemZ_CLIY 1061 +#define SystemZ_CLM 1062 +#define SystemZ_CLMH 1063 +#define SystemZ_CLMY 1064 +#define SystemZ_CLR 1065 +#define SystemZ_CLRB 1066 +#define SystemZ_CLRBAsm 1067 +#define SystemZ_CLRBAsmE 1068 +#define SystemZ_CLRBAsmH 1069 +#define SystemZ_CLRBAsmHE 1070 +#define SystemZ_CLRBAsmL 1071 +#define SystemZ_CLRBAsmLE 1072 +#define SystemZ_CLRBAsmLH 1073 +#define SystemZ_CLRBAsmNE 1074 +#define SystemZ_CLRBAsmNH 1075 +#define SystemZ_CLRBAsmNHE 1076 +#define SystemZ_CLRBAsmNL 1077 +#define SystemZ_CLRBAsmNLE 1078 +#define SystemZ_CLRBAsmNLH 1079 +#define SystemZ_CLRJ 1080 +#define SystemZ_CLRJAsm 1081 +#define SystemZ_CLRJAsmE 1082 +#define SystemZ_CLRJAsmH 1083 +#define SystemZ_CLRJAsmHE 1084 +#define SystemZ_CLRJAsmL 1085 +#define SystemZ_CLRJAsmLE 1086 +#define SystemZ_CLRJAsmLH 1087 +#define SystemZ_CLRJAsmNE 1088 +#define SystemZ_CLRJAsmNH 1089 +#define SystemZ_CLRJAsmNHE 1090 +#define SystemZ_CLRJAsmNL 1091 +#define SystemZ_CLRJAsmNLE 1092 +#define SystemZ_CLRJAsmNLH 1093 +#define SystemZ_CLRL 1094 +#define SystemZ_CLRT 1095 +#define SystemZ_CLRTAsm 1096 +#define SystemZ_CLRTAsmE 1097 +#define SystemZ_CLRTAsmH 1098 +#define SystemZ_CLRTAsmHE 1099 +#define SystemZ_CLRTAsmL 1100 +#define SystemZ_CLRTAsmLE 1101 +#define SystemZ_CLRTAsmLH 1102 +#define SystemZ_CLRTAsmNE 1103 +#define SystemZ_CLRTAsmNH 1104 +#define SystemZ_CLRTAsmNHE 1105 +#define SystemZ_CLRTAsmNL 1106 +#define SystemZ_CLRTAsmNLE 1107 +#define SystemZ_CLRTAsmNLH 1108 +#define SystemZ_CLST 1109 +#define SystemZ_CLT 1110 +#define SystemZ_CLTAsm 1111 +#define SystemZ_CLTAsmE 1112 +#define SystemZ_CLTAsmH 1113 +#define SystemZ_CLTAsmHE 1114 +#define SystemZ_CLTAsmL 1115 +#define SystemZ_CLTAsmLE 1116 +#define SystemZ_CLTAsmLH 1117 +#define SystemZ_CLTAsmNE 1118 +#define SystemZ_CLTAsmNH 1119 +#define SystemZ_CLTAsmNHE 1120 +#define SystemZ_CLTAsmNL 1121 +#define SystemZ_CLTAsmNLE 1122 +#define SystemZ_CLTAsmNLH 1123 +#define SystemZ_CLY 1124 +#define SystemZ_CMPSC 1125 +#define SystemZ_CP 1126 +#define SystemZ_CPDT 1127 +#define SystemZ_CPSDRdd 1128 +#define SystemZ_CPSDRds 1129 +#define SystemZ_CPSDRsd 1130 +#define SystemZ_CPSDRss 1131 +#define SystemZ_CPXT 1132 +#define SystemZ_CPYA 1133 +#define SystemZ_CR 1134 +#define SystemZ_CRB 1135 +#define SystemZ_CRBAsm 1136 +#define SystemZ_CRBAsmE 1137 +#define SystemZ_CRBAsmH 1138 +#define SystemZ_CRBAsmHE 1139 +#define SystemZ_CRBAsmL 1140 +#define SystemZ_CRBAsmLE 1141 +#define SystemZ_CRBAsmLH 1142 +#define SystemZ_CRBAsmNE 1143 +#define SystemZ_CRBAsmNH 1144 +#define SystemZ_CRBAsmNHE 1145 +#define SystemZ_CRBAsmNL 1146 +#define SystemZ_CRBAsmNLE 1147 +#define SystemZ_CRBAsmNLH 1148 +#define SystemZ_CRDTE 1149 +#define SystemZ_CRDTEOpt 1150 +#define SystemZ_CRJ 1151 +#define SystemZ_CRJAsm 1152 +#define SystemZ_CRJAsmE 1153 +#define SystemZ_CRJAsmH 1154 +#define SystemZ_CRJAsmHE 1155 +#define SystemZ_CRJAsmL 1156 +#define SystemZ_CRJAsmLE 1157 +#define SystemZ_CRJAsmLH 1158 +#define SystemZ_CRJAsmNE 1159 +#define SystemZ_CRJAsmNH 1160 +#define SystemZ_CRJAsmNHE 1161 +#define SystemZ_CRJAsmNL 1162 +#define SystemZ_CRJAsmNLE 1163 +#define SystemZ_CRJAsmNLH 1164 +#define SystemZ_CRL 1165 +#define SystemZ_CRT 1166 +#define SystemZ_CRTAsm 1167 +#define SystemZ_CRTAsmE 1168 +#define SystemZ_CRTAsmH 1169 +#define SystemZ_CRTAsmHE 1170 +#define SystemZ_CRTAsmL 1171 +#define SystemZ_CRTAsmLE 1172 +#define SystemZ_CRTAsmLH 1173 +#define SystemZ_CRTAsmNE 1174 +#define SystemZ_CRTAsmNH 1175 +#define SystemZ_CRTAsmNHE 1176 +#define SystemZ_CRTAsmNL 1177 +#define SystemZ_CRTAsmNLE 1178 +#define SystemZ_CRTAsmNLH 1179 +#define SystemZ_CS 1180 +#define SystemZ_CSCH 1181 +#define SystemZ_CSDTR 1182 +#define SystemZ_CSG 1183 +#define SystemZ_CSP 1184 +#define SystemZ_CSPG 1185 +#define SystemZ_CSST 1186 +#define SystemZ_CSXTR 1187 +#define SystemZ_CSY 1188 +#define SystemZ_CU12 1189 +#define SystemZ_CU12Opt 1190 +#define SystemZ_CU14 1191 +#define SystemZ_CU14Opt 1192 +#define SystemZ_CU21 1193 +#define SystemZ_CU21Opt 1194 +#define SystemZ_CU24 1195 +#define SystemZ_CU24Opt 1196 +#define SystemZ_CU41 1197 +#define SystemZ_CU42 1198 +#define SystemZ_CUDTR 1199 +#define SystemZ_CUSE 1200 +#define SystemZ_CUTFU 1201 +#define SystemZ_CUTFUOpt 1202 +#define SystemZ_CUUTF 1203 +#define SystemZ_CUUTFOpt 1204 +#define SystemZ_CUXTR 1205 +#define SystemZ_CVB 1206 +#define SystemZ_CVBG 1207 +#define SystemZ_CVBY 1208 +#define SystemZ_CVD 1209 +#define SystemZ_CVDG 1210 +#define SystemZ_CVDY 1211 +#define SystemZ_CXBR 1212 +#define SystemZ_CXFBR 1213 +#define SystemZ_CXFBRA 1214 +#define SystemZ_CXFR 1215 +#define SystemZ_CXFTR 1216 +#define SystemZ_CXGBR 1217 +#define SystemZ_CXGBRA 1218 +#define SystemZ_CXGR 1219 +#define SystemZ_CXGTR 1220 +#define SystemZ_CXGTRA 1221 +#define SystemZ_CXLFBR 1222 +#define SystemZ_CXLFTR 1223 +#define SystemZ_CXLGBR 1224 +#define SystemZ_CXLGTR 1225 +#define SystemZ_CXPT 1226 +#define SystemZ_CXR 1227 +#define SystemZ_CXSTR 1228 +#define SystemZ_CXTR 1229 +#define SystemZ_CXUTR 1230 +#define SystemZ_CXZT 1231 +#define SystemZ_CY 1232 +#define SystemZ_CZDT 1233 +#define SystemZ_CZXT 1234 +#define SystemZ_D 1235 +#define SystemZ_DD 1236 +#define SystemZ_DDB 1237 +#define SystemZ_DDBR 1238 +#define SystemZ_DDR 1239 +#define SystemZ_DDTR 1240 +#define SystemZ_DDTRA 1241 +#define SystemZ_DE 1242 +#define SystemZ_DEB 1243 +#define SystemZ_DEBR 1244 +#define SystemZ_DER 1245 +#define SystemZ_DFLTCC 1246 +#define SystemZ_DIAG 1247 +#define SystemZ_DIDBR 1248 +#define SystemZ_DIEBR 1249 +#define SystemZ_DL 1250 +#define SystemZ_DLG 1251 +#define SystemZ_DLGR 1252 +#define SystemZ_DLR 1253 +#define SystemZ_DP 1254 +#define SystemZ_DR 1255 +#define SystemZ_DSG 1256 +#define SystemZ_DSGF 1257 +#define SystemZ_DSGFR 1258 +#define SystemZ_DSGR 1259 +#define SystemZ_DXBR 1260 +#define SystemZ_DXR 1261 +#define SystemZ_DXTR 1262 +#define SystemZ_DXTRA 1263 +#define SystemZ_EAR 1264 +#define SystemZ_ECAG 1265 +#define SystemZ_ECCTR 1266 +#define SystemZ_ECPGA 1267 +#define SystemZ_ECTG 1268 +#define SystemZ_ED 1269 +#define SystemZ_EDMK 1270 +#define SystemZ_EEDTR 1271 +#define SystemZ_EEXTR 1272 +#define SystemZ_EFPC 1273 +#define SystemZ_EPAIR 1274 +#define SystemZ_EPAR 1275 +#define SystemZ_EPCTR 1276 +#define SystemZ_EPSW 1277 +#define SystemZ_EREG 1278 +#define SystemZ_EREGG 1279 +#define SystemZ_ESAIR 1280 +#define SystemZ_ESAR 1281 +#define SystemZ_ESDTR 1282 +#define SystemZ_ESEA 1283 +#define SystemZ_ESTA 1284 +#define SystemZ_ESXTR 1285 +#define SystemZ_ETND 1286 +#define SystemZ_EX 1287 +#define SystemZ_EXRL 1288 +#define SystemZ_FIDBR 1289 +#define SystemZ_FIDBRA 1290 +#define SystemZ_FIDR 1291 +#define SystemZ_FIDTR 1292 +#define SystemZ_FIEBR 1293 +#define SystemZ_FIEBRA 1294 +#define SystemZ_FIER 1295 +#define SystemZ_FIXBR 1296 +#define SystemZ_FIXBRA 1297 +#define SystemZ_FIXR 1298 +#define SystemZ_FIXTR 1299 +#define SystemZ_FLOGR 1300 +#define SystemZ_HDR 1301 +#define SystemZ_HER 1302 +#define SystemZ_HSCH 1303 +#define SystemZ_IAC 1304 +#define SystemZ_IC 1305 +#define SystemZ_IC32 1306 +#define SystemZ_IC32Y 1307 +#define SystemZ_ICM 1308 +#define SystemZ_ICMH 1309 +#define SystemZ_ICMY 1310 +#define SystemZ_ICY 1311 +#define SystemZ_IDTE 1312 +#define SystemZ_IDTEOpt 1313 +#define SystemZ_IEDTR 1314 +#define SystemZ_IEXTR 1315 +#define SystemZ_IIHF 1316 +#define SystemZ_IIHH 1317 +#define SystemZ_IIHL 1318 +#define SystemZ_IILF 1319 +#define SystemZ_IILH 1320 +#define SystemZ_IILL 1321 +#define SystemZ_IPK 1322 +#define SystemZ_IPM 1323 +#define SystemZ_IPTE 1324 +#define SystemZ_IPTEOpt 1325 +#define SystemZ_IPTEOptOpt 1326 +#define SystemZ_IRBM 1327 +#define SystemZ_ISKE 1328 +#define SystemZ_IVSK 1329 +#define SystemZ_InsnE 1330 +#define SystemZ_InsnRI 1331 +#define SystemZ_InsnRIE 1332 +#define SystemZ_InsnRIL 1333 +#define SystemZ_InsnRILU 1334 +#define SystemZ_InsnRIS 1335 +#define SystemZ_InsnRR 1336 +#define SystemZ_InsnRRE 1337 +#define SystemZ_InsnRRF 1338 +#define SystemZ_InsnRRS 1339 +#define SystemZ_InsnRS 1340 +#define SystemZ_InsnRSE 1341 +#define SystemZ_InsnRSI 1342 +#define SystemZ_InsnRSY 1343 +#define SystemZ_InsnRX 1344 +#define SystemZ_InsnRXE 1345 +#define SystemZ_InsnRXF 1346 +#define SystemZ_InsnRXY 1347 +#define SystemZ_InsnS 1348 +#define SystemZ_InsnSI 1349 +#define SystemZ_InsnSIL 1350 +#define SystemZ_InsnSIY 1351 +#define SystemZ_InsnSS 1352 +#define SystemZ_InsnSSE 1353 +#define SystemZ_InsnSSF 1354 +#define SystemZ_InsnVRI 1355 +#define SystemZ_InsnVRR 1356 +#define SystemZ_InsnVRS 1357 +#define SystemZ_InsnVRV 1358 +#define SystemZ_InsnVRX 1359 +#define SystemZ_InsnVSI 1360 +#define SystemZ_J 1361 +#define SystemZ_JAsmE 1362 +#define SystemZ_JAsmH 1363 +#define SystemZ_JAsmHE 1364 +#define SystemZ_JAsmL 1365 +#define SystemZ_JAsmLE 1366 +#define SystemZ_JAsmLH 1367 +#define SystemZ_JAsmM 1368 +#define SystemZ_JAsmNE 1369 +#define SystemZ_JAsmNH 1370 +#define SystemZ_JAsmNHE 1371 +#define SystemZ_JAsmNL 1372 +#define SystemZ_JAsmNLE 1373 +#define SystemZ_JAsmNLH 1374 +#define SystemZ_JAsmNM 1375 +#define SystemZ_JAsmNO 1376 +#define SystemZ_JAsmNP 1377 +#define SystemZ_JAsmNZ 1378 +#define SystemZ_JAsmO 1379 +#define SystemZ_JAsmP 1380 +#define SystemZ_JAsmZ 1381 +#define SystemZ_JG 1382 +#define SystemZ_JGAsmE 1383 +#define SystemZ_JGAsmH 1384 +#define SystemZ_JGAsmHE 1385 +#define SystemZ_JGAsmL 1386 +#define SystemZ_JGAsmLE 1387 +#define SystemZ_JGAsmLH 1388 +#define SystemZ_JGAsmM 1389 +#define SystemZ_JGAsmNE 1390 +#define SystemZ_JGAsmNH 1391 +#define SystemZ_JGAsmNHE 1392 +#define SystemZ_JGAsmNL 1393 +#define SystemZ_JGAsmNLE 1394 +#define SystemZ_JGAsmNLH 1395 +#define SystemZ_JGAsmNM 1396 +#define SystemZ_JGAsmNO 1397 +#define SystemZ_JGAsmNP 1398 +#define SystemZ_JGAsmNZ 1399 +#define SystemZ_JGAsmO 1400 +#define SystemZ_JGAsmP 1401 +#define SystemZ_JGAsmZ 1402 +#define SystemZ_KDB 1403 +#define SystemZ_KDBR 1404 +#define SystemZ_KDSA 1405 +#define SystemZ_KDTR 1406 +#define SystemZ_KEB 1407 +#define SystemZ_KEBR 1408 +#define SystemZ_KIMD 1409 +#define SystemZ_KLMD 1410 +#define SystemZ_KM 1411 +#define SystemZ_KMA 1412 +#define SystemZ_KMAC 1413 +#define SystemZ_KMC 1414 +#define SystemZ_KMCTR 1415 +#define SystemZ_KMF 1416 +#define SystemZ_KMO 1417 +#define SystemZ_KXBR 1418 +#define SystemZ_KXTR 1419 +#define SystemZ_L 1420 +#define SystemZ_LA 1421 +#define SystemZ_LAA 1422 +#define SystemZ_LAAG 1423 +#define SystemZ_LAAL 1424 +#define SystemZ_LAALG 1425 +#define SystemZ_LAE 1426 +#define SystemZ_LAEY 1427 +#define SystemZ_LAM 1428 +#define SystemZ_LAMY 1429 +#define SystemZ_LAN 1430 +#define SystemZ_LANG 1431 +#define SystemZ_LAO 1432 +#define SystemZ_LAOG 1433 +#define SystemZ_LARL 1434 +#define SystemZ_LASP 1435 +#define SystemZ_LAT 1436 +#define SystemZ_LAX 1437 +#define SystemZ_LAXG 1438 +#define SystemZ_LAY 1439 +#define SystemZ_LB 1440 +#define SystemZ_LBEAR 1441 +#define SystemZ_LBH 1442 +#define SystemZ_LBR 1443 +#define SystemZ_LCBB 1444 +#define SystemZ_LCCTL 1445 +#define SystemZ_LCDBR 1446 +#define SystemZ_LCDFR 1447 +#define SystemZ_LCDFR_32 1448 +#define SystemZ_LCDR 1449 +#define SystemZ_LCEBR 1450 +#define SystemZ_LCER 1451 +#define SystemZ_LCGFR 1452 +#define SystemZ_LCGR 1453 +#define SystemZ_LCR 1454 +#define SystemZ_LCTL 1455 +#define SystemZ_LCTLG 1456 +#define SystemZ_LCXBR 1457 +#define SystemZ_LCXR 1458 +#define SystemZ_LD 1459 +#define SystemZ_LDE 1460 +#define SystemZ_LDE32 1461 +#define SystemZ_LDEB 1462 +#define SystemZ_LDEBR 1463 +#define SystemZ_LDER 1464 +#define SystemZ_LDETR 1465 +#define SystemZ_LDGR 1466 +#define SystemZ_LDR 1467 +#define SystemZ_LDR32 1468 +#define SystemZ_LDXBR 1469 +#define SystemZ_LDXBRA 1470 +#define SystemZ_LDXR 1471 +#define SystemZ_LDXTR 1472 +#define SystemZ_LDY 1473 +#define SystemZ_LE 1474 +#define SystemZ_LEDBR 1475 +#define SystemZ_LEDBRA 1476 +#define SystemZ_LEDR 1477 +#define SystemZ_LEDTR 1478 +#define SystemZ_LER 1479 +#define SystemZ_LEXBR 1480 +#define SystemZ_LEXBRA 1481 +#define SystemZ_LEXR 1482 +#define SystemZ_LEY 1483 +#define SystemZ_LFAS 1484 +#define SystemZ_LFH 1485 +#define SystemZ_LFHAT 1486 +#define SystemZ_LFPC 1487 +#define SystemZ_LG 1488 +#define SystemZ_LGAT 1489 +#define SystemZ_LGB 1490 +#define SystemZ_LGBR 1491 +#define SystemZ_LGDR 1492 +#define SystemZ_LGF 1493 +#define SystemZ_LGFI 1494 +#define SystemZ_LGFR 1495 +#define SystemZ_LGFRL 1496 +#define SystemZ_LGG 1497 +#define SystemZ_LGH 1498 +#define SystemZ_LGHI 1499 +#define SystemZ_LGHR 1500 +#define SystemZ_LGHRL 1501 +#define SystemZ_LGR 1502 +#define SystemZ_LGRL 1503 +#define SystemZ_LGSC 1504 +#define SystemZ_LH 1505 +#define SystemZ_LHH 1506 +#define SystemZ_LHI 1507 +#define SystemZ_LHR 1508 +#define SystemZ_LHRL 1509 +#define SystemZ_LHY 1510 +#define SystemZ_LLC 1511 +#define SystemZ_LLCH 1512 +#define SystemZ_LLCR 1513 +#define SystemZ_LLGC 1514 +#define SystemZ_LLGCR 1515 +#define SystemZ_LLGF 1516 +#define SystemZ_LLGFAT 1517 +#define SystemZ_LLGFR 1518 +#define SystemZ_LLGFRL 1519 +#define SystemZ_LLGFSG 1520 +#define SystemZ_LLGH 1521 +#define SystemZ_LLGHR 1522 +#define SystemZ_LLGHRL 1523 +#define SystemZ_LLGT 1524 +#define SystemZ_LLGTAT 1525 +#define SystemZ_LLGTR 1526 +#define SystemZ_LLH 1527 +#define SystemZ_LLHH 1528 +#define SystemZ_LLHR 1529 +#define SystemZ_LLHRL 1530 +#define SystemZ_LLIHF 1531 +#define SystemZ_LLIHH 1532 +#define SystemZ_LLIHL 1533 +#define SystemZ_LLILF 1534 +#define SystemZ_LLILH 1535 +#define SystemZ_LLILL 1536 +#define SystemZ_LLZRGF 1537 +#define SystemZ_LM 1538 +#define SystemZ_LMD 1539 +#define SystemZ_LMG 1540 +#define SystemZ_LMH 1541 +#define SystemZ_LMY 1542 +#define SystemZ_LNDBR 1543 +#define SystemZ_LNDFR 1544 +#define SystemZ_LNDFR_32 1545 +#define SystemZ_LNDR 1546 +#define SystemZ_LNEBR 1547 +#define SystemZ_LNER 1548 +#define SystemZ_LNGFR 1549 +#define SystemZ_LNGR 1550 +#define SystemZ_LNR 1551 +#define SystemZ_LNXBR 1552 +#define SystemZ_LNXR 1553 +#define SystemZ_LOC 1554 +#define SystemZ_LOCAsm 1555 +#define SystemZ_LOCAsmE 1556 +#define SystemZ_LOCAsmH 1557 +#define SystemZ_LOCAsmHE 1558 +#define SystemZ_LOCAsmL 1559 +#define SystemZ_LOCAsmLE 1560 +#define SystemZ_LOCAsmLH 1561 +#define SystemZ_LOCAsmM 1562 +#define SystemZ_LOCAsmNE 1563 +#define SystemZ_LOCAsmNH 1564 +#define SystemZ_LOCAsmNHE 1565 +#define SystemZ_LOCAsmNL 1566 +#define SystemZ_LOCAsmNLE 1567 +#define SystemZ_LOCAsmNLH 1568 +#define SystemZ_LOCAsmNM 1569 +#define SystemZ_LOCAsmNO 1570 +#define SystemZ_LOCAsmNP 1571 +#define SystemZ_LOCAsmNZ 1572 +#define SystemZ_LOCAsmO 1573 +#define SystemZ_LOCAsmP 1574 +#define SystemZ_LOCAsmZ 1575 +#define SystemZ_LOCFH 1576 +#define SystemZ_LOCFHAsm 1577 +#define SystemZ_LOCFHAsmE 1578 +#define SystemZ_LOCFHAsmH 1579 +#define SystemZ_LOCFHAsmHE 1580 +#define SystemZ_LOCFHAsmL 1581 +#define SystemZ_LOCFHAsmLE 1582 +#define SystemZ_LOCFHAsmLH 1583 +#define SystemZ_LOCFHAsmM 1584 +#define SystemZ_LOCFHAsmNE 1585 +#define SystemZ_LOCFHAsmNH 1586 +#define SystemZ_LOCFHAsmNHE 1587 +#define SystemZ_LOCFHAsmNL 1588 +#define SystemZ_LOCFHAsmNLE 1589 +#define SystemZ_LOCFHAsmNLH 1590 +#define SystemZ_LOCFHAsmNM 1591 +#define SystemZ_LOCFHAsmNO 1592 +#define SystemZ_LOCFHAsmNP 1593 +#define SystemZ_LOCFHAsmNZ 1594 +#define SystemZ_LOCFHAsmO 1595 +#define SystemZ_LOCFHAsmP 1596 +#define SystemZ_LOCFHAsmZ 1597 +#define SystemZ_LOCFHR 1598 +#define SystemZ_LOCFHRAsm 1599 +#define SystemZ_LOCFHRAsmE 1600 +#define SystemZ_LOCFHRAsmH 1601 +#define SystemZ_LOCFHRAsmHE 1602 +#define SystemZ_LOCFHRAsmL 1603 +#define SystemZ_LOCFHRAsmLE 1604 +#define SystemZ_LOCFHRAsmLH 1605 +#define SystemZ_LOCFHRAsmM 1606 +#define SystemZ_LOCFHRAsmNE 1607 +#define SystemZ_LOCFHRAsmNH 1608 +#define SystemZ_LOCFHRAsmNHE 1609 +#define SystemZ_LOCFHRAsmNL 1610 +#define SystemZ_LOCFHRAsmNLE 1611 +#define SystemZ_LOCFHRAsmNLH 1612 +#define SystemZ_LOCFHRAsmNM 1613 +#define SystemZ_LOCFHRAsmNO 1614 +#define SystemZ_LOCFHRAsmNP 1615 +#define SystemZ_LOCFHRAsmNZ 1616 +#define SystemZ_LOCFHRAsmO 1617 +#define SystemZ_LOCFHRAsmP 1618 +#define SystemZ_LOCFHRAsmZ 1619 +#define SystemZ_LOCG 1620 +#define SystemZ_LOCGAsm 1621 +#define SystemZ_LOCGAsmE 1622 +#define SystemZ_LOCGAsmH 1623 +#define SystemZ_LOCGAsmHE 1624 +#define SystemZ_LOCGAsmL 1625 +#define SystemZ_LOCGAsmLE 1626 +#define SystemZ_LOCGAsmLH 1627 +#define SystemZ_LOCGAsmM 1628 +#define SystemZ_LOCGAsmNE 1629 +#define SystemZ_LOCGAsmNH 1630 +#define SystemZ_LOCGAsmNHE 1631 +#define SystemZ_LOCGAsmNL 1632 +#define SystemZ_LOCGAsmNLE 1633 +#define SystemZ_LOCGAsmNLH 1634 +#define SystemZ_LOCGAsmNM 1635 +#define SystemZ_LOCGAsmNO 1636 +#define SystemZ_LOCGAsmNP 1637 +#define SystemZ_LOCGAsmNZ 1638 +#define SystemZ_LOCGAsmO 1639 +#define SystemZ_LOCGAsmP 1640 +#define SystemZ_LOCGAsmZ 1641 +#define SystemZ_LOCGHI 1642 +#define SystemZ_LOCGHIAsm 1643 +#define SystemZ_LOCGHIAsmE 1644 +#define SystemZ_LOCGHIAsmH 1645 +#define SystemZ_LOCGHIAsmHE 1646 +#define SystemZ_LOCGHIAsmL 1647 +#define SystemZ_LOCGHIAsmLE 1648 +#define SystemZ_LOCGHIAsmLH 1649 +#define SystemZ_LOCGHIAsmM 1650 +#define SystemZ_LOCGHIAsmNE 1651 +#define SystemZ_LOCGHIAsmNH 1652 +#define SystemZ_LOCGHIAsmNHE 1653 +#define SystemZ_LOCGHIAsmNL 1654 +#define SystemZ_LOCGHIAsmNLE 1655 +#define SystemZ_LOCGHIAsmNLH 1656 +#define SystemZ_LOCGHIAsmNM 1657 +#define SystemZ_LOCGHIAsmNO 1658 +#define SystemZ_LOCGHIAsmNP 1659 +#define SystemZ_LOCGHIAsmNZ 1660 +#define SystemZ_LOCGHIAsmO 1661 +#define SystemZ_LOCGHIAsmP 1662 +#define SystemZ_LOCGHIAsmZ 1663 +#define SystemZ_LOCGR 1664 +#define SystemZ_LOCGRAsm 1665 +#define SystemZ_LOCGRAsmE 1666 +#define SystemZ_LOCGRAsmH 1667 +#define SystemZ_LOCGRAsmHE 1668 +#define SystemZ_LOCGRAsmL 1669 +#define SystemZ_LOCGRAsmLE 1670 +#define SystemZ_LOCGRAsmLH 1671 +#define SystemZ_LOCGRAsmM 1672 +#define SystemZ_LOCGRAsmNE 1673 +#define SystemZ_LOCGRAsmNH 1674 +#define SystemZ_LOCGRAsmNHE 1675 +#define SystemZ_LOCGRAsmNL 1676 +#define SystemZ_LOCGRAsmNLE 1677 +#define SystemZ_LOCGRAsmNLH 1678 +#define SystemZ_LOCGRAsmNM 1679 +#define SystemZ_LOCGRAsmNO 1680 +#define SystemZ_LOCGRAsmNP 1681 +#define SystemZ_LOCGRAsmNZ 1682 +#define SystemZ_LOCGRAsmO 1683 +#define SystemZ_LOCGRAsmP 1684 +#define SystemZ_LOCGRAsmZ 1685 +#define SystemZ_LOCHHI 1686 +#define SystemZ_LOCHHIAsm 1687 +#define SystemZ_LOCHHIAsmE 1688 +#define SystemZ_LOCHHIAsmH 1689 +#define SystemZ_LOCHHIAsmHE 1690 +#define SystemZ_LOCHHIAsmL 1691 +#define SystemZ_LOCHHIAsmLE 1692 +#define SystemZ_LOCHHIAsmLH 1693 +#define SystemZ_LOCHHIAsmM 1694 +#define SystemZ_LOCHHIAsmNE 1695 +#define SystemZ_LOCHHIAsmNH 1696 +#define SystemZ_LOCHHIAsmNHE 1697 +#define SystemZ_LOCHHIAsmNL 1698 +#define SystemZ_LOCHHIAsmNLE 1699 +#define SystemZ_LOCHHIAsmNLH 1700 +#define SystemZ_LOCHHIAsmNM 1701 +#define SystemZ_LOCHHIAsmNO 1702 +#define SystemZ_LOCHHIAsmNP 1703 +#define SystemZ_LOCHHIAsmNZ 1704 +#define SystemZ_LOCHHIAsmO 1705 +#define SystemZ_LOCHHIAsmP 1706 +#define SystemZ_LOCHHIAsmZ 1707 +#define SystemZ_LOCHI 1708 +#define SystemZ_LOCHIAsm 1709 +#define SystemZ_LOCHIAsmE 1710 +#define SystemZ_LOCHIAsmH 1711 +#define SystemZ_LOCHIAsmHE 1712 +#define SystemZ_LOCHIAsmL 1713 +#define SystemZ_LOCHIAsmLE 1714 +#define SystemZ_LOCHIAsmLH 1715 +#define SystemZ_LOCHIAsmM 1716 +#define SystemZ_LOCHIAsmNE 1717 +#define SystemZ_LOCHIAsmNH 1718 +#define SystemZ_LOCHIAsmNHE 1719 +#define SystemZ_LOCHIAsmNL 1720 +#define SystemZ_LOCHIAsmNLE 1721 +#define SystemZ_LOCHIAsmNLH 1722 +#define SystemZ_LOCHIAsmNM 1723 +#define SystemZ_LOCHIAsmNO 1724 +#define SystemZ_LOCHIAsmNP 1725 +#define SystemZ_LOCHIAsmNZ 1726 +#define SystemZ_LOCHIAsmO 1727 +#define SystemZ_LOCHIAsmP 1728 +#define SystemZ_LOCHIAsmZ 1729 +#define SystemZ_LOCR 1730 +#define SystemZ_LOCRAsm 1731 +#define SystemZ_LOCRAsmE 1732 +#define SystemZ_LOCRAsmH 1733 +#define SystemZ_LOCRAsmHE 1734 +#define SystemZ_LOCRAsmL 1735 +#define SystemZ_LOCRAsmLE 1736 +#define SystemZ_LOCRAsmLH 1737 +#define SystemZ_LOCRAsmM 1738 +#define SystemZ_LOCRAsmNE 1739 +#define SystemZ_LOCRAsmNH 1740 +#define SystemZ_LOCRAsmNHE 1741 +#define SystemZ_LOCRAsmNL 1742 +#define SystemZ_LOCRAsmNLE 1743 +#define SystemZ_LOCRAsmNLH 1744 +#define SystemZ_LOCRAsmNM 1745 +#define SystemZ_LOCRAsmNO 1746 +#define SystemZ_LOCRAsmNP 1747 +#define SystemZ_LOCRAsmNZ 1748 +#define SystemZ_LOCRAsmO 1749 +#define SystemZ_LOCRAsmP 1750 +#define SystemZ_LOCRAsmZ 1751 +#define SystemZ_LPCTL 1752 +#define SystemZ_LPD 1753 +#define SystemZ_LPDBR 1754 +#define SystemZ_LPDFR 1755 +#define SystemZ_LPDFR_32 1756 +#define SystemZ_LPDG 1757 +#define SystemZ_LPDR 1758 +#define SystemZ_LPEBR 1759 +#define SystemZ_LPER 1760 +#define SystemZ_LPGFR 1761 +#define SystemZ_LPGR 1762 +#define SystemZ_LPP 1763 +#define SystemZ_LPQ 1764 +#define SystemZ_LPR 1765 +#define SystemZ_LPSW 1766 +#define SystemZ_LPSWE 1767 +#define SystemZ_LPSWEY 1768 +#define SystemZ_LPTEA 1769 +#define SystemZ_LPXBR 1770 +#define SystemZ_LPXR 1771 +#define SystemZ_LR 1772 +#define SystemZ_LRA 1773 +#define SystemZ_LRAG 1774 +#define SystemZ_LRAY 1775 +#define SystemZ_LRDR 1776 +#define SystemZ_LRER 1777 +#define SystemZ_LRL 1778 +#define SystemZ_LRV 1779 +#define SystemZ_LRVG 1780 +#define SystemZ_LRVGR 1781 +#define SystemZ_LRVH 1782 +#define SystemZ_LRVR 1783 +#define SystemZ_LSCTL 1784 +#define SystemZ_LT 1785 +#define SystemZ_LTDBR 1786 +#define SystemZ_LTDBRCompare 1787 +#define SystemZ_LTDR 1788 +#define SystemZ_LTDTR 1789 +#define SystemZ_LTEBR 1790 +#define SystemZ_LTEBRCompare 1791 +#define SystemZ_LTER 1792 +#define SystemZ_LTG 1793 +#define SystemZ_LTGF 1794 +#define SystemZ_LTGFR 1795 +#define SystemZ_LTGR 1796 +#define SystemZ_LTR 1797 +#define SystemZ_LTXBR 1798 +#define SystemZ_LTXBRCompare 1799 +#define SystemZ_LTXR 1800 +#define SystemZ_LTXTR 1801 +#define SystemZ_LURA 1802 +#define SystemZ_LURAG 1803 +#define SystemZ_LXD 1804 +#define SystemZ_LXDB 1805 +#define SystemZ_LXDBR 1806 +#define SystemZ_LXDR 1807 +#define SystemZ_LXDTR 1808 +#define SystemZ_LXE 1809 +#define SystemZ_LXEB 1810 +#define SystemZ_LXEBR 1811 +#define SystemZ_LXER 1812 +#define SystemZ_LXR 1813 +#define SystemZ_LY 1814 +#define SystemZ_LZDR 1815 +#define SystemZ_LZER 1816 +#define SystemZ_LZRF 1817 +#define SystemZ_LZRG 1818 +#define SystemZ_LZXR 1819 +#define SystemZ_M 1820 +#define SystemZ_MAD 1821 +#define SystemZ_MADB 1822 +#define SystemZ_MADBR 1823 +#define SystemZ_MADR 1824 +#define SystemZ_MAE 1825 +#define SystemZ_MAEB 1826 +#define SystemZ_MAEBR 1827 +#define SystemZ_MAER 1828 +#define SystemZ_MAY 1829 +#define SystemZ_MAYH 1830 +#define SystemZ_MAYHR 1831 +#define SystemZ_MAYL 1832 +#define SystemZ_MAYLR 1833 +#define SystemZ_MAYR 1834 +#define SystemZ_MC 1835 +#define SystemZ_MD 1836 +#define SystemZ_MDB 1837 +#define SystemZ_MDBR 1838 +#define SystemZ_MDE 1839 +#define SystemZ_MDEB 1840 +#define SystemZ_MDEBR 1841 +#define SystemZ_MDER 1842 +#define SystemZ_MDR 1843 +#define SystemZ_MDTR 1844 +#define SystemZ_MDTRA 1845 +#define SystemZ_ME 1846 +#define SystemZ_MEE 1847 +#define SystemZ_MEEB 1848 +#define SystemZ_MEEBR 1849 +#define SystemZ_MEER 1850 +#define SystemZ_MER 1851 +#define SystemZ_MFY 1852 +#define SystemZ_MG 1853 +#define SystemZ_MGH 1854 +#define SystemZ_MGHI 1855 +#define SystemZ_MGRK 1856 +#define SystemZ_MH 1857 +#define SystemZ_MHI 1858 +#define SystemZ_MHY 1859 +#define SystemZ_ML 1860 +#define SystemZ_MLG 1861 +#define SystemZ_MLGR 1862 +#define SystemZ_MLR 1863 +#define SystemZ_MP 1864 +#define SystemZ_MR 1865 +#define SystemZ_MS 1866 +#define SystemZ_MSC 1867 +#define SystemZ_MSCH 1868 +#define SystemZ_MSD 1869 +#define SystemZ_MSDB 1870 +#define SystemZ_MSDBR 1871 +#define SystemZ_MSDR 1872 +#define SystemZ_MSE 1873 +#define SystemZ_MSEB 1874 +#define SystemZ_MSEBR 1875 +#define SystemZ_MSER 1876 +#define SystemZ_MSFI 1877 +#define SystemZ_MSG 1878 +#define SystemZ_MSGC 1879 +#define SystemZ_MSGF 1880 +#define SystemZ_MSGFI 1881 +#define SystemZ_MSGFR 1882 +#define SystemZ_MSGR 1883 +#define SystemZ_MSGRKC 1884 +#define SystemZ_MSR 1885 +#define SystemZ_MSRKC 1886 +#define SystemZ_MSTA 1887 +#define SystemZ_MSY 1888 +#define SystemZ_MVC 1889 +#define SystemZ_MVCDK 1890 +#define SystemZ_MVCIN 1891 +#define SystemZ_MVCK 1892 +#define SystemZ_MVCL 1893 +#define SystemZ_MVCLE 1894 +#define SystemZ_MVCLU 1895 +#define SystemZ_MVCOS 1896 +#define SystemZ_MVCP 1897 +#define SystemZ_MVCRL 1898 +#define SystemZ_MVCS 1899 +#define SystemZ_MVCSK 1900 +#define SystemZ_MVGHI 1901 +#define SystemZ_MVHHI 1902 +#define SystemZ_MVHI 1903 +#define SystemZ_MVI 1904 +#define SystemZ_MVIY 1905 +#define SystemZ_MVN 1906 +#define SystemZ_MVO 1907 +#define SystemZ_MVPG 1908 +#define SystemZ_MVST 1909 +#define SystemZ_MVZ 1910 +#define SystemZ_MXBR 1911 +#define SystemZ_MXD 1912 +#define SystemZ_MXDB 1913 +#define SystemZ_MXDBR 1914 +#define SystemZ_MXDR 1915 +#define SystemZ_MXR 1916 +#define SystemZ_MXTR 1917 +#define SystemZ_MXTRA 1918 +#define SystemZ_MY 1919 +#define SystemZ_MYH 1920 +#define SystemZ_MYHR 1921 +#define SystemZ_MYL 1922 +#define SystemZ_MYLR 1923 +#define SystemZ_MYR 1924 +#define SystemZ_N 1925 +#define SystemZ_NC 1926 +#define SystemZ_NCGRK 1927 +#define SystemZ_NCRK 1928 +#define SystemZ_NG 1929 +#define SystemZ_NGR 1930 +#define SystemZ_NGRK 1931 +#define SystemZ_NI 1932 +#define SystemZ_NIAI 1933 +#define SystemZ_NIHF 1934 +#define SystemZ_NIHH 1935 +#define SystemZ_NIHL 1936 +#define SystemZ_NILF 1937 +#define SystemZ_NILH 1938 +#define SystemZ_NILL 1939 +#define SystemZ_NIY 1940 +#define SystemZ_NNGRK 1941 +#define SystemZ_NNPA 1942 +#define SystemZ_NNRK 1943 +#define SystemZ_NOGRK 1944 +#define SystemZ_NOP_bare 1945 +#define SystemZ_NORK 1946 +#define SystemZ_NR 1947 +#define SystemZ_NRK 1948 +#define SystemZ_NTSTG 1949 +#define SystemZ_NXGRK 1950 +#define SystemZ_NXRK 1951 +#define SystemZ_NY 1952 +#define SystemZ_O 1953 +#define SystemZ_OC 1954 +#define SystemZ_OCGRK 1955 +#define SystemZ_OCRK 1956 +#define SystemZ_OG 1957 +#define SystemZ_OGR 1958 +#define SystemZ_OGRK 1959 +#define SystemZ_OI 1960 +#define SystemZ_OIHF 1961 +#define SystemZ_OIHH 1962 +#define SystemZ_OIHL 1963 +#define SystemZ_OILF 1964 +#define SystemZ_OILH 1965 +#define SystemZ_OILL 1966 +#define SystemZ_OIY 1967 +#define SystemZ_OR 1968 +#define SystemZ_ORK 1969 +#define SystemZ_OY 1970 +#define SystemZ_PACK 1971 +#define SystemZ_PALB 1972 +#define SystemZ_PC 1973 +#define SystemZ_PCC 1974 +#define SystemZ_PCKMO 1975 +#define SystemZ_PFD 1976 +#define SystemZ_PFDRL 1977 +#define SystemZ_PFMF 1978 +#define SystemZ_PFPO 1979 +#define SystemZ_PGIN 1980 +#define SystemZ_PGOUT 1981 +#define SystemZ_PKA 1982 +#define SystemZ_PKU 1983 +#define SystemZ_PLO 1984 +#define SystemZ_POPCNT 1985 +#define SystemZ_POPCNTOpt 1986 +#define SystemZ_PPA 1987 +#define SystemZ_PPNO 1988 +#define SystemZ_PR 1989 +#define SystemZ_PRNO 1990 +#define SystemZ_PT 1991 +#define SystemZ_PTF 1992 +#define SystemZ_PTFF 1993 +#define SystemZ_PTI 1994 +#define SystemZ_PTLB 1995 +#define SystemZ_QADTR 1996 +#define SystemZ_QAXTR 1997 +#define SystemZ_QCTRI 1998 +#define SystemZ_QPACI 1999 +#define SystemZ_QSI 2000 +#define SystemZ_RCHP 2001 +#define SystemZ_RDP 2002 +#define SystemZ_RDPOpt 2003 +#define SystemZ_RISBG 2004 +#define SystemZ_RISBG32 2005 +#define SystemZ_RISBGN 2006 +#define SystemZ_RISBHG 2007 +#define SystemZ_RISBLG 2008 +#define SystemZ_RLL 2009 +#define SystemZ_RLLG 2010 +#define SystemZ_RNSBG 2011 +#define SystemZ_ROSBG 2012 +#define SystemZ_RP 2013 +#define SystemZ_RRBE 2014 +#define SystemZ_RRBM 2015 +#define SystemZ_RRDTR 2016 +#define SystemZ_RRXTR 2017 +#define SystemZ_RSCH 2018 +#define SystemZ_RXSBG 2019 +#define SystemZ_S 2020 +#define SystemZ_SAC 2021 +#define SystemZ_SACF 2022 +#define SystemZ_SAL 2023 +#define SystemZ_SAM24 2024 +#define SystemZ_SAM31 2025 +#define SystemZ_SAM64 2026 +#define SystemZ_SAR 2027 +#define SystemZ_SCCTR 2028 +#define SystemZ_SCHM 2029 +#define SystemZ_SCK 2030 +#define SystemZ_SCKC 2031 +#define SystemZ_SCKPF 2032 +#define SystemZ_SD 2033 +#define SystemZ_SDB 2034 +#define SystemZ_SDBR 2035 +#define SystemZ_SDR 2036 +#define SystemZ_SDTR 2037 +#define SystemZ_SDTRA 2038 +#define SystemZ_SE 2039 +#define SystemZ_SEB 2040 +#define SystemZ_SEBR 2041 +#define SystemZ_SELFHR 2042 +#define SystemZ_SELFHRAsm 2043 +#define SystemZ_SELFHRAsmE 2044 +#define SystemZ_SELFHRAsmH 2045 +#define SystemZ_SELFHRAsmHE 2046 +#define SystemZ_SELFHRAsmL 2047 +#define SystemZ_SELFHRAsmLE 2048 +#define SystemZ_SELFHRAsmLH 2049 +#define SystemZ_SELFHRAsmM 2050 +#define SystemZ_SELFHRAsmNE 2051 +#define SystemZ_SELFHRAsmNH 2052 +#define SystemZ_SELFHRAsmNHE 2053 +#define SystemZ_SELFHRAsmNL 2054 +#define SystemZ_SELFHRAsmNLE 2055 +#define SystemZ_SELFHRAsmNLH 2056 +#define SystemZ_SELFHRAsmNM 2057 +#define SystemZ_SELFHRAsmNO 2058 +#define SystemZ_SELFHRAsmNP 2059 +#define SystemZ_SELFHRAsmNZ 2060 +#define SystemZ_SELFHRAsmO 2061 +#define SystemZ_SELFHRAsmP 2062 +#define SystemZ_SELFHRAsmZ 2063 +#define SystemZ_SELGR 2064 +#define SystemZ_SELGRAsm 2065 +#define SystemZ_SELGRAsmE 2066 +#define SystemZ_SELGRAsmH 2067 +#define SystemZ_SELGRAsmHE 2068 +#define SystemZ_SELGRAsmL 2069 +#define SystemZ_SELGRAsmLE 2070 +#define SystemZ_SELGRAsmLH 2071 +#define SystemZ_SELGRAsmM 2072 +#define SystemZ_SELGRAsmNE 2073 +#define SystemZ_SELGRAsmNH 2074 +#define SystemZ_SELGRAsmNHE 2075 +#define SystemZ_SELGRAsmNL 2076 +#define SystemZ_SELGRAsmNLE 2077 +#define SystemZ_SELGRAsmNLH 2078 +#define SystemZ_SELGRAsmNM 2079 +#define SystemZ_SELGRAsmNO 2080 +#define SystemZ_SELGRAsmNP 2081 +#define SystemZ_SELGRAsmNZ 2082 +#define SystemZ_SELGRAsmO 2083 +#define SystemZ_SELGRAsmP 2084 +#define SystemZ_SELGRAsmZ 2085 +#define SystemZ_SELR 2086 +#define SystemZ_SELRAsm 2087 +#define SystemZ_SELRAsmE 2088 +#define SystemZ_SELRAsmH 2089 +#define SystemZ_SELRAsmHE 2090 +#define SystemZ_SELRAsmL 2091 +#define SystemZ_SELRAsmLE 2092 +#define SystemZ_SELRAsmLH 2093 +#define SystemZ_SELRAsmM 2094 +#define SystemZ_SELRAsmNE 2095 +#define SystemZ_SELRAsmNH 2096 +#define SystemZ_SELRAsmNHE 2097 +#define SystemZ_SELRAsmNL 2098 +#define SystemZ_SELRAsmNLE 2099 +#define SystemZ_SELRAsmNLH 2100 +#define SystemZ_SELRAsmNM 2101 +#define SystemZ_SELRAsmNO 2102 +#define SystemZ_SELRAsmNP 2103 +#define SystemZ_SELRAsmNZ 2104 +#define SystemZ_SELRAsmO 2105 +#define SystemZ_SELRAsmP 2106 +#define SystemZ_SELRAsmZ 2107 +#define SystemZ_SER 2108 +#define SystemZ_SFASR 2109 +#define SystemZ_SFPC 2110 +#define SystemZ_SG 2111 +#define SystemZ_SGF 2112 +#define SystemZ_SGFR 2113 +#define SystemZ_SGH 2114 +#define SystemZ_SGR 2115 +#define SystemZ_SGRK 2116 +#define SystemZ_SH 2117 +#define SystemZ_SHHHR 2118 +#define SystemZ_SHHLR 2119 +#define SystemZ_SHY 2120 +#define SystemZ_SIE 2121 +#define SystemZ_SIGA 2122 +#define SystemZ_SIGP 2123 +#define SystemZ_SL 2124 +#define SystemZ_SLA 2125 +#define SystemZ_SLAG 2126 +#define SystemZ_SLAK 2127 +#define SystemZ_SLB 2128 +#define SystemZ_SLBG 2129 +#define SystemZ_SLBGR 2130 +#define SystemZ_SLBR 2131 +#define SystemZ_SLDA 2132 +#define SystemZ_SLDL 2133 +#define SystemZ_SLDT 2134 +#define SystemZ_SLFI 2135 +#define SystemZ_SLG 2136 +#define SystemZ_SLGF 2137 +#define SystemZ_SLGFI 2138 +#define SystemZ_SLGFR 2139 +#define SystemZ_SLGR 2140 +#define SystemZ_SLGRK 2141 +#define SystemZ_SLHHHR 2142 +#define SystemZ_SLHHLR 2143 +#define SystemZ_SLL 2144 +#define SystemZ_SLLG 2145 +#define SystemZ_SLLK 2146 +#define SystemZ_SLR 2147 +#define SystemZ_SLRK 2148 +#define SystemZ_SLXT 2149 +#define SystemZ_SLY 2150 +#define SystemZ_SORTL 2151 +#define SystemZ_SP 2152 +#define SystemZ_SPCTR 2153 +#define SystemZ_SPKA 2154 +#define SystemZ_SPM 2155 +#define SystemZ_SPT 2156 +#define SystemZ_SPX 2157 +#define SystemZ_SQD 2158 +#define SystemZ_SQDB 2159 +#define SystemZ_SQDBR 2160 +#define SystemZ_SQDR 2161 +#define SystemZ_SQE 2162 +#define SystemZ_SQEB 2163 +#define SystemZ_SQEBR 2164 +#define SystemZ_SQER 2165 +#define SystemZ_SQXBR 2166 +#define SystemZ_SQXR 2167 +#define SystemZ_SR 2168 +#define SystemZ_SRA 2169 +#define SystemZ_SRAG 2170 +#define SystemZ_SRAK 2171 +#define SystemZ_SRDA 2172 +#define SystemZ_SRDL 2173 +#define SystemZ_SRDT 2174 +#define SystemZ_SRK 2175 +#define SystemZ_SRL 2176 +#define SystemZ_SRLG 2177 +#define SystemZ_SRLK 2178 +#define SystemZ_SRNM 2179 +#define SystemZ_SRNMB 2180 +#define SystemZ_SRNMT 2181 +#define SystemZ_SRP 2182 +#define SystemZ_SRST 2183 +#define SystemZ_SRSTU 2184 +#define SystemZ_SRXT 2185 +#define SystemZ_SSAIR 2186 +#define SystemZ_SSAR 2187 +#define SystemZ_SSCH 2188 +#define SystemZ_SSKE 2189 +#define SystemZ_SSKEOpt 2190 +#define SystemZ_SSM 2191 +#define SystemZ_ST 2192 +#define SystemZ_STAM 2193 +#define SystemZ_STAMY 2194 +#define SystemZ_STAP 2195 +#define SystemZ_STBEAR 2196 +#define SystemZ_STC 2197 +#define SystemZ_STCH 2198 +#define SystemZ_STCK 2199 +#define SystemZ_STCKC 2200 +#define SystemZ_STCKE 2201 +#define SystemZ_STCKF 2202 +#define SystemZ_STCM 2203 +#define SystemZ_STCMH 2204 +#define SystemZ_STCMY 2205 +#define SystemZ_STCPS 2206 +#define SystemZ_STCRW 2207 +#define SystemZ_STCTG 2208 +#define SystemZ_STCTL 2209 +#define SystemZ_STCY 2210 +#define SystemZ_STD 2211 +#define SystemZ_STDY 2212 +#define SystemZ_STE 2213 +#define SystemZ_STEY 2214 +#define SystemZ_STFH 2215 +#define SystemZ_STFL 2216 +#define SystemZ_STFLE 2217 +#define SystemZ_STFPC 2218 +#define SystemZ_STG 2219 +#define SystemZ_STGRL 2220 +#define SystemZ_STGSC 2221 +#define SystemZ_STH 2222 +#define SystemZ_STHH 2223 +#define SystemZ_STHRL 2224 +#define SystemZ_STHY 2225 +#define SystemZ_STIDP 2226 +#define SystemZ_STM 2227 +#define SystemZ_STMG 2228 +#define SystemZ_STMH 2229 +#define SystemZ_STMY 2230 +#define SystemZ_STNSM 2231 +#define SystemZ_STOC 2232 +#define SystemZ_STOCAsm 2233 +#define SystemZ_STOCAsmE 2234 +#define SystemZ_STOCAsmH 2235 +#define SystemZ_STOCAsmHE 2236 +#define SystemZ_STOCAsmL 2237 +#define SystemZ_STOCAsmLE 2238 +#define SystemZ_STOCAsmLH 2239 +#define SystemZ_STOCAsmM 2240 +#define SystemZ_STOCAsmNE 2241 +#define SystemZ_STOCAsmNH 2242 +#define SystemZ_STOCAsmNHE 2243 +#define SystemZ_STOCAsmNL 2244 +#define SystemZ_STOCAsmNLE 2245 +#define SystemZ_STOCAsmNLH 2246 +#define SystemZ_STOCAsmNM 2247 +#define SystemZ_STOCAsmNO 2248 +#define SystemZ_STOCAsmNP 2249 +#define SystemZ_STOCAsmNZ 2250 +#define SystemZ_STOCAsmO 2251 +#define SystemZ_STOCAsmP 2252 +#define SystemZ_STOCAsmZ 2253 +#define SystemZ_STOCFH 2254 +#define SystemZ_STOCFHAsm 2255 +#define SystemZ_STOCFHAsmE 2256 +#define SystemZ_STOCFHAsmH 2257 +#define SystemZ_STOCFHAsmHE 2258 +#define SystemZ_STOCFHAsmL 2259 +#define SystemZ_STOCFHAsmLE 2260 +#define SystemZ_STOCFHAsmLH 2261 +#define SystemZ_STOCFHAsmM 2262 +#define SystemZ_STOCFHAsmNE 2263 +#define SystemZ_STOCFHAsmNH 2264 +#define SystemZ_STOCFHAsmNHE 2265 +#define SystemZ_STOCFHAsmNL 2266 +#define SystemZ_STOCFHAsmNLE 2267 +#define SystemZ_STOCFHAsmNLH 2268 +#define SystemZ_STOCFHAsmNM 2269 +#define SystemZ_STOCFHAsmNO 2270 +#define SystemZ_STOCFHAsmNP 2271 +#define SystemZ_STOCFHAsmNZ 2272 +#define SystemZ_STOCFHAsmO 2273 +#define SystemZ_STOCFHAsmP 2274 +#define SystemZ_STOCFHAsmZ 2275 +#define SystemZ_STOCG 2276 +#define SystemZ_STOCGAsm 2277 +#define SystemZ_STOCGAsmE 2278 +#define SystemZ_STOCGAsmH 2279 +#define SystemZ_STOCGAsmHE 2280 +#define SystemZ_STOCGAsmL 2281 +#define SystemZ_STOCGAsmLE 2282 +#define SystemZ_STOCGAsmLH 2283 +#define SystemZ_STOCGAsmM 2284 +#define SystemZ_STOCGAsmNE 2285 +#define SystemZ_STOCGAsmNH 2286 +#define SystemZ_STOCGAsmNHE 2287 +#define SystemZ_STOCGAsmNL 2288 +#define SystemZ_STOCGAsmNLE 2289 +#define SystemZ_STOCGAsmNLH 2290 +#define SystemZ_STOCGAsmNM 2291 +#define SystemZ_STOCGAsmNO 2292 +#define SystemZ_STOCGAsmNP 2293 +#define SystemZ_STOCGAsmNZ 2294 +#define SystemZ_STOCGAsmO 2295 +#define SystemZ_STOCGAsmP 2296 +#define SystemZ_STOCGAsmZ 2297 +#define SystemZ_STOSM 2298 +#define SystemZ_STPQ 2299 +#define SystemZ_STPT 2300 +#define SystemZ_STPX 2301 +#define SystemZ_STRAG 2302 +#define SystemZ_STRL 2303 +#define SystemZ_STRV 2304 +#define SystemZ_STRVG 2305 +#define SystemZ_STRVH 2306 +#define SystemZ_STSCH 2307 +#define SystemZ_STSI 2308 +#define SystemZ_STURA 2309 +#define SystemZ_STURG 2310 +#define SystemZ_STY 2311 +#define SystemZ_SU 2312 +#define SystemZ_SUR 2313 +#define SystemZ_SVC 2314 +#define SystemZ_SW 2315 +#define SystemZ_SWR 2316 +#define SystemZ_SXBR 2317 +#define SystemZ_SXR 2318 +#define SystemZ_SXTR 2319 +#define SystemZ_SXTRA 2320 +#define SystemZ_SY 2321 +#define SystemZ_TABORT 2322 +#define SystemZ_TAM 2323 +#define SystemZ_TAR 2324 +#define SystemZ_TB 2325 +#define SystemZ_TBDR 2326 +#define SystemZ_TBEDR 2327 +#define SystemZ_TBEGIN 2328 +#define SystemZ_TBEGINC 2329 +#define SystemZ_TCDB 2330 +#define SystemZ_TCEB 2331 +#define SystemZ_TCXB 2332 +#define SystemZ_TDCDT 2333 +#define SystemZ_TDCET 2334 +#define SystemZ_TDCXT 2335 +#define SystemZ_TDGDT 2336 +#define SystemZ_TDGET 2337 +#define SystemZ_TDGXT 2338 +#define SystemZ_TEND 2339 +#define SystemZ_THDER 2340 +#define SystemZ_THDR 2341 +#define SystemZ_TM 2342 +#define SystemZ_TMHH 2343 +#define SystemZ_TMHL 2344 +#define SystemZ_TMLH 2345 +#define SystemZ_TMLL 2346 +#define SystemZ_TMY 2347 +#define SystemZ_TP 2348 +#define SystemZ_TPI 2349 +#define SystemZ_TPROT 2350 +#define SystemZ_TR 2351 +#define SystemZ_TRACE 2352 +#define SystemZ_TRACG 2353 +#define SystemZ_TRAP2 2354 +#define SystemZ_TRAP4 2355 +#define SystemZ_TRE 2356 +#define SystemZ_TROO 2357 +#define SystemZ_TROOOpt 2358 +#define SystemZ_TROT 2359 +#define SystemZ_TROTOpt 2360 +#define SystemZ_TRT 2361 +#define SystemZ_TRTE 2362 +#define SystemZ_TRTEOpt 2363 +#define SystemZ_TRTO 2364 +#define SystemZ_TRTOOpt 2365 +#define SystemZ_TRTR 2366 +#define SystemZ_TRTRE 2367 +#define SystemZ_TRTREOpt 2368 +#define SystemZ_TRTT 2369 +#define SystemZ_TRTTOpt 2370 +#define SystemZ_TS 2371 +#define SystemZ_TSCH 2372 +#define SystemZ_UNPK 2373 +#define SystemZ_UNPKA 2374 +#define SystemZ_UNPKU 2375 +#define SystemZ_UPT 2376 +#define SystemZ_VA 2377 +#define SystemZ_VAB 2378 +#define SystemZ_VAC 2379 +#define SystemZ_VACC 2380 +#define SystemZ_VACCB 2381 +#define SystemZ_VACCC 2382 +#define SystemZ_VACCCQ 2383 +#define SystemZ_VACCF 2384 +#define SystemZ_VACCG 2385 +#define SystemZ_VACCH 2386 +#define SystemZ_VACCQ 2387 +#define SystemZ_VACQ 2388 +#define SystemZ_VAF 2389 +#define SystemZ_VAG 2390 +#define SystemZ_VAH 2391 +#define SystemZ_VAP 2392 +#define SystemZ_VAQ 2393 +#define SystemZ_VAVG 2394 +#define SystemZ_VAVGB 2395 +#define SystemZ_VAVGF 2396 +#define SystemZ_VAVGG 2397 +#define SystemZ_VAVGH 2398 +#define SystemZ_VAVGL 2399 +#define SystemZ_VAVGLB 2400 +#define SystemZ_VAVGLF 2401 +#define SystemZ_VAVGLG 2402 +#define SystemZ_VAVGLH 2403 +#define SystemZ_VBPERM 2404 +#define SystemZ_VCDG 2405 +#define SystemZ_VCDGB 2406 +#define SystemZ_VCDLG 2407 +#define SystemZ_VCDLGB 2408 +#define SystemZ_VCEFB 2409 +#define SystemZ_VCELFB 2410 +#define SystemZ_VCEQ 2411 +#define SystemZ_VCEQB 2412 +#define SystemZ_VCEQBS 2413 +#define SystemZ_VCEQF 2414 +#define SystemZ_VCEQFS 2415 +#define SystemZ_VCEQG 2416 +#define SystemZ_VCEQGS 2417 +#define SystemZ_VCEQH 2418 +#define SystemZ_VCEQHS 2419 +#define SystemZ_VCFEB 2420 +#define SystemZ_VCFN 2421 +#define SystemZ_VCFPL 2422 +#define SystemZ_VCFPS 2423 +#define SystemZ_VCGD 2424 +#define SystemZ_VCGDB 2425 +#define SystemZ_VCH 2426 +#define SystemZ_VCHB 2427 +#define SystemZ_VCHBS 2428 +#define SystemZ_VCHF 2429 +#define SystemZ_VCHFS 2430 +#define SystemZ_VCHG 2431 +#define SystemZ_VCHGS 2432 +#define SystemZ_VCHH 2433 +#define SystemZ_VCHHS 2434 +#define SystemZ_VCHL 2435 +#define SystemZ_VCHLB 2436 +#define SystemZ_VCHLBS 2437 +#define SystemZ_VCHLF 2438 +#define SystemZ_VCHLFS 2439 +#define SystemZ_VCHLG 2440 +#define SystemZ_VCHLGS 2441 +#define SystemZ_VCHLH 2442 +#define SystemZ_VCHLHS 2443 +#define SystemZ_VCKSM 2444 +#define SystemZ_VCLFEB 2445 +#define SystemZ_VCLFNH 2446 +#define SystemZ_VCLFNL 2447 +#define SystemZ_VCLFP 2448 +#define SystemZ_VCLGD 2449 +#define SystemZ_VCLGDB 2450 +#define SystemZ_VCLZ 2451 +#define SystemZ_VCLZB 2452 +#define SystemZ_VCLZDP 2453 +#define SystemZ_VCLZF 2454 +#define SystemZ_VCLZG 2455 +#define SystemZ_VCLZH 2456 +#define SystemZ_VCNF 2457 +#define SystemZ_VCP 2458 +#define SystemZ_VCRNF 2459 +#define SystemZ_VCSFP 2460 +#define SystemZ_VCSPH 2461 +#define SystemZ_VCTZ 2462 +#define SystemZ_VCTZB 2463 +#define SystemZ_VCTZF 2464 +#define SystemZ_VCTZG 2465 +#define SystemZ_VCTZH 2466 +#define SystemZ_VCVB 2467 +#define SystemZ_VCVBG 2468 +#define SystemZ_VCVBGOpt 2469 +#define SystemZ_VCVBOpt 2470 +#define SystemZ_VCVD 2471 +#define SystemZ_VCVDG 2472 +#define SystemZ_VDP 2473 +#define SystemZ_VEC 2474 +#define SystemZ_VECB 2475 +#define SystemZ_VECF 2476 +#define SystemZ_VECG 2477 +#define SystemZ_VECH 2478 +#define SystemZ_VECL 2479 +#define SystemZ_VECLB 2480 +#define SystemZ_VECLF 2481 +#define SystemZ_VECLG 2482 +#define SystemZ_VECLH 2483 +#define SystemZ_VERIM 2484 +#define SystemZ_VERIMB 2485 +#define SystemZ_VERIMF 2486 +#define SystemZ_VERIMG 2487 +#define SystemZ_VERIMH 2488 +#define SystemZ_VERLL 2489 +#define SystemZ_VERLLB 2490 +#define SystemZ_VERLLF 2491 +#define SystemZ_VERLLG 2492 +#define SystemZ_VERLLH 2493 +#define SystemZ_VERLLV 2494 +#define SystemZ_VERLLVB 2495 +#define SystemZ_VERLLVF 2496 +#define SystemZ_VERLLVG 2497 +#define SystemZ_VERLLVH 2498 +#define SystemZ_VESL 2499 +#define SystemZ_VESLB 2500 +#define SystemZ_VESLF 2501 +#define SystemZ_VESLG 2502 +#define SystemZ_VESLH 2503 +#define SystemZ_VESLV 2504 +#define SystemZ_VESLVB 2505 +#define SystemZ_VESLVF 2506 +#define SystemZ_VESLVG 2507 +#define SystemZ_VESLVH 2508 +#define SystemZ_VESRA 2509 +#define SystemZ_VESRAB 2510 +#define SystemZ_VESRAF 2511 +#define SystemZ_VESRAG 2512 +#define SystemZ_VESRAH 2513 +#define SystemZ_VESRAV 2514 +#define SystemZ_VESRAVB 2515 +#define SystemZ_VESRAVF 2516 +#define SystemZ_VESRAVG 2517 +#define SystemZ_VESRAVH 2518 +#define SystemZ_VESRL 2519 +#define SystemZ_VESRLB 2520 +#define SystemZ_VESRLF 2521 +#define SystemZ_VESRLG 2522 +#define SystemZ_VESRLH 2523 +#define SystemZ_VESRLV 2524 +#define SystemZ_VESRLVB 2525 +#define SystemZ_VESRLVF 2526 +#define SystemZ_VESRLVG 2527 +#define SystemZ_VESRLVH 2528 +#define SystemZ_VFA 2529 +#define SystemZ_VFADB 2530 +#define SystemZ_VFAE 2531 +#define SystemZ_VFAEB 2532 +#define SystemZ_VFAEBS 2533 +#define SystemZ_VFAEF 2534 +#define SystemZ_VFAEFS 2535 +#define SystemZ_VFAEH 2536 +#define SystemZ_VFAEHS 2537 +#define SystemZ_VFAEZB 2538 +#define SystemZ_VFAEZBS 2539 +#define SystemZ_VFAEZF 2540 +#define SystemZ_VFAEZFS 2541 +#define SystemZ_VFAEZH 2542 +#define SystemZ_VFAEZHS 2543 +#define SystemZ_VFASB 2544 +#define SystemZ_VFCE 2545 +#define SystemZ_VFCEDB 2546 +#define SystemZ_VFCEDBS 2547 +#define SystemZ_VFCESB 2548 +#define SystemZ_VFCESBS 2549 +#define SystemZ_VFCH 2550 +#define SystemZ_VFCHDB 2551 +#define SystemZ_VFCHDBS 2552 +#define SystemZ_VFCHE 2553 +#define SystemZ_VFCHEDB 2554 +#define SystemZ_VFCHEDBS 2555 +#define SystemZ_VFCHESB 2556 +#define SystemZ_VFCHESBS 2557 +#define SystemZ_VFCHSB 2558 +#define SystemZ_VFCHSBS 2559 +#define SystemZ_VFD 2560 +#define SystemZ_VFDDB 2561 +#define SystemZ_VFDSB 2562 +#define SystemZ_VFEE 2563 +#define SystemZ_VFEEB 2564 +#define SystemZ_VFEEBS 2565 +#define SystemZ_VFEEF 2566 +#define SystemZ_VFEEFS 2567 +#define SystemZ_VFEEH 2568 +#define SystemZ_VFEEHS 2569 +#define SystemZ_VFEEZB 2570 +#define SystemZ_VFEEZBS 2571 +#define SystemZ_VFEEZF 2572 +#define SystemZ_VFEEZFS 2573 +#define SystemZ_VFEEZH 2574 +#define SystemZ_VFEEZHS 2575 +#define SystemZ_VFENE 2576 +#define SystemZ_VFENEB 2577 +#define SystemZ_VFENEBS 2578 +#define SystemZ_VFENEF 2579 +#define SystemZ_VFENEFS 2580 +#define SystemZ_VFENEH 2581 +#define SystemZ_VFENEHS 2582 +#define SystemZ_VFENEZB 2583 +#define SystemZ_VFENEZBS 2584 +#define SystemZ_VFENEZF 2585 +#define SystemZ_VFENEZFS 2586 +#define SystemZ_VFENEZH 2587 +#define SystemZ_VFENEZHS 2588 +#define SystemZ_VFI 2589 +#define SystemZ_VFIDB 2590 +#define SystemZ_VFISB 2591 +#define SystemZ_VFKEDB 2592 +#define SystemZ_VFKEDBS 2593 +#define SystemZ_VFKESB 2594 +#define SystemZ_VFKESBS 2595 +#define SystemZ_VFKHDB 2596 +#define SystemZ_VFKHDBS 2597 +#define SystemZ_VFKHEDB 2598 +#define SystemZ_VFKHEDBS 2599 +#define SystemZ_VFKHESB 2600 +#define SystemZ_VFKHESBS 2601 +#define SystemZ_VFKHSB 2602 +#define SystemZ_VFKHSBS 2603 +#define SystemZ_VFLCDB 2604 +#define SystemZ_VFLCSB 2605 +#define SystemZ_VFLL 2606 +#define SystemZ_VFLLS 2607 +#define SystemZ_VFLNDB 2608 +#define SystemZ_VFLNSB 2609 +#define SystemZ_VFLPDB 2610 +#define SystemZ_VFLPSB 2611 +#define SystemZ_VFLR 2612 +#define SystemZ_VFLRD 2613 +#define SystemZ_VFM 2614 +#define SystemZ_VFMA 2615 +#define SystemZ_VFMADB 2616 +#define SystemZ_VFMASB 2617 +#define SystemZ_VFMAX 2618 +#define SystemZ_VFMAXDB 2619 +#define SystemZ_VFMAXSB 2620 +#define SystemZ_VFMDB 2621 +#define SystemZ_VFMIN 2622 +#define SystemZ_VFMINDB 2623 +#define SystemZ_VFMINSB 2624 +#define SystemZ_VFMS 2625 +#define SystemZ_VFMSB 2626 +#define SystemZ_VFMSDB 2627 +#define SystemZ_VFMSSB 2628 +#define SystemZ_VFNMA 2629 +#define SystemZ_VFNMADB 2630 +#define SystemZ_VFNMASB 2631 +#define SystemZ_VFNMS 2632 +#define SystemZ_VFNMSDB 2633 +#define SystemZ_VFNMSSB 2634 +#define SystemZ_VFPSO 2635 +#define SystemZ_VFPSODB 2636 +#define SystemZ_VFPSOSB 2637 +#define SystemZ_VFS 2638 +#define SystemZ_VFSDB 2639 +#define SystemZ_VFSQ 2640 +#define SystemZ_VFSQDB 2641 +#define SystemZ_VFSQSB 2642 +#define SystemZ_VFSSB 2643 +#define SystemZ_VFTCI 2644 +#define SystemZ_VFTCIDB 2645 +#define SystemZ_VFTCISB 2646 +#define SystemZ_VGBM 2647 +#define SystemZ_VGEF 2648 +#define SystemZ_VGEG 2649 +#define SystemZ_VGFM 2650 +#define SystemZ_VGFMA 2651 +#define SystemZ_VGFMAB 2652 +#define SystemZ_VGFMAF 2653 +#define SystemZ_VGFMAG 2654 +#define SystemZ_VGFMAH 2655 +#define SystemZ_VGFMB 2656 +#define SystemZ_VGFMF 2657 +#define SystemZ_VGFMG 2658 +#define SystemZ_VGFMH 2659 +#define SystemZ_VGM 2660 +#define SystemZ_VGMB 2661 +#define SystemZ_VGMF 2662 +#define SystemZ_VGMG 2663 +#define SystemZ_VGMH 2664 +#define SystemZ_VISTR 2665 +#define SystemZ_VISTRB 2666 +#define SystemZ_VISTRBS 2667 +#define SystemZ_VISTRF 2668 +#define SystemZ_VISTRFS 2669 +#define SystemZ_VISTRH 2670 +#define SystemZ_VISTRHS 2671 +#define SystemZ_VL 2672 +#define SystemZ_VLAlign 2673 +#define SystemZ_VLBB 2674 +#define SystemZ_VLBR 2675 +#define SystemZ_VLBRF 2676 +#define SystemZ_VLBRG 2677 +#define SystemZ_VLBRH 2678 +#define SystemZ_VLBRQ 2679 +#define SystemZ_VLBRREP 2680 +#define SystemZ_VLBRREPF 2681 +#define SystemZ_VLBRREPG 2682 +#define SystemZ_VLBRREPH 2683 +#define SystemZ_VLC 2684 +#define SystemZ_VLCB 2685 +#define SystemZ_VLCF 2686 +#define SystemZ_VLCG 2687 +#define SystemZ_VLCH 2688 +#define SystemZ_VLDE 2689 +#define SystemZ_VLDEB 2690 +#define SystemZ_VLEB 2691 +#define SystemZ_VLEBRF 2692 +#define SystemZ_VLEBRG 2693 +#define SystemZ_VLEBRH 2694 +#define SystemZ_VLED 2695 +#define SystemZ_VLEDB 2696 +#define SystemZ_VLEF 2697 +#define SystemZ_VLEG 2698 +#define SystemZ_VLEH 2699 +#define SystemZ_VLEIB 2700 +#define SystemZ_VLEIF 2701 +#define SystemZ_VLEIG 2702 +#define SystemZ_VLEIH 2703 +#define SystemZ_VLER 2704 +#define SystemZ_VLERF 2705 +#define SystemZ_VLERG 2706 +#define SystemZ_VLERH 2707 +#define SystemZ_VLGV 2708 +#define SystemZ_VLGVB 2709 +#define SystemZ_VLGVF 2710 +#define SystemZ_VLGVG 2711 +#define SystemZ_VLGVH 2712 +#define SystemZ_VLIP 2713 +#define SystemZ_VLL 2714 +#define SystemZ_VLLEBRZ 2715 +#define SystemZ_VLLEBRZE 2716 +#define SystemZ_VLLEBRZF 2717 +#define SystemZ_VLLEBRZG 2718 +#define SystemZ_VLLEBRZH 2719 +#define SystemZ_VLLEZ 2720 +#define SystemZ_VLLEZB 2721 +#define SystemZ_VLLEZF 2722 +#define SystemZ_VLLEZG 2723 +#define SystemZ_VLLEZH 2724 +#define SystemZ_VLLEZLF 2725 +#define SystemZ_VLM 2726 +#define SystemZ_VLMAlign 2727 +#define SystemZ_VLP 2728 +#define SystemZ_VLPB 2729 +#define SystemZ_VLPF 2730 +#define SystemZ_VLPG 2731 +#define SystemZ_VLPH 2732 +#define SystemZ_VLR 2733 +#define SystemZ_VLREP 2734 +#define SystemZ_VLREPB 2735 +#define SystemZ_VLREPF 2736 +#define SystemZ_VLREPG 2737 +#define SystemZ_VLREPH 2738 +#define SystemZ_VLRL 2739 +#define SystemZ_VLRLR 2740 +#define SystemZ_VLVG 2741 +#define SystemZ_VLVGB 2742 +#define SystemZ_VLVGF 2743 +#define SystemZ_VLVGG 2744 +#define SystemZ_VLVGH 2745 +#define SystemZ_VLVGP 2746 +#define SystemZ_VMAE 2747 +#define SystemZ_VMAEB 2748 +#define SystemZ_VMAEF 2749 +#define SystemZ_VMAEH 2750 +#define SystemZ_VMAH 2751 +#define SystemZ_VMAHB 2752 +#define SystemZ_VMAHF 2753 +#define SystemZ_VMAHH 2754 +#define SystemZ_VMAL 2755 +#define SystemZ_VMALB 2756 +#define SystemZ_VMALE 2757 +#define SystemZ_VMALEB 2758 +#define SystemZ_VMALEF 2759 +#define SystemZ_VMALEH 2760 +#define SystemZ_VMALF 2761 +#define SystemZ_VMALH 2762 +#define SystemZ_VMALHB 2763 +#define SystemZ_VMALHF 2764 +#define SystemZ_VMALHH 2765 +#define SystemZ_VMALHW 2766 +#define SystemZ_VMALO 2767 +#define SystemZ_VMALOB 2768 +#define SystemZ_VMALOF 2769 +#define SystemZ_VMALOH 2770 +#define SystemZ_VMAO 2771 +#define SystemZ_VMAOB 2772 +#define SystemZ_VMAOF 2773 +#define SystemZ_VMAOH 2774 +#define SystemZ_VME 2775 +#define SystemZ_VMEB 2776 +#define SystemZ_VMEF 2777 +#define SystemZ_VMEH 2778 +#define SystemZ_VMH 2779 +#define SystemZ_VMHB 2780 +#define SystemZ_VMHF 2781 +#define SystemZ_VMHH 2782 +#define SystemZ_VML 2783 +#define SystemZ_VMLB 2784 +#define SystemZ_VMLE 2785 +#define SystemZ_VMLEB 2786 +#define SystemZ_VMLEF 2787 +#define SystemZ_VMLEH 2788 +#define SystemZ_VMLF 2789 +#define SystemZ_VMLH 2790 +#define SystemZ_VMLHB 2791 +#define SystemZ_VMLHF 2792 +#define SystemZ_VMLHH 2793 +#define SystemZ_VMLHW 2794 +#define SystemZ_VMLO 2795 +#define SystemZ_VMLOB 2796 +#define SystemZ_VMLOF 2797 +#define SystemZ_VMLOH 2798 +#define SystemZ_VMN 2799 +#define SystemZ_VMNB 2800 +#define SystemZ_VMNF 2801 +#define SystemZ_VMNG 2802 +#define SystemZ_VMNH 2803 +#define SystemZ_VMNL 2804 +#define SystemZ_VMNLB 2805 +#define SystemZ_VMNLF 2806 +#define SystemZ_VMNLG 2807 +#define SystemZ_VMNLH 2808 +#define SystemZ_VMO 2809 +#define SystemZ_VMOB 2810 +#define SystemZ_VMOF 2811 +#define SystemZ_VMOH 2812 +#define SystemZ_VMP 2813 +#define SystemZ_VMRH 2814 +#define SystemZ_VMRHB 2815 +#define SystemZ_VMRHF 2816 +#define SystemZ_VMRHG 2817 +#define SystemZ_VMRHH 2818 +#define SystemZ_VMRL 2819 +#define SystemZ_VMRLB 2820 +#define SystemZ_VMRLF 2821 +#define SystemZ_VMRLG 2822 +#define SystemZ_VMRLH 2823 +#define SystemZ_VMSL 2824 +#define SystemZ_VMSLG 2825 +#define SystemZ_VMSP 2826 +#define SystemZ_VMX 2827 +#define SystemZ_VMXB 2828 +#define SystemZ_VMXF 2829 +#define SystemZ_VMXG 2830 +#define SystemZ_VMXH 2831 +#define SystemZ_VMXL 2832 +#define SystemZ_VMXLB 2833 +#define SystemZ_VMXLF 2834 +#define SystemZ_VMXLG 2835 +#define SystemZ_VMXLH 2836 +#define SystemZ_VN 2837 +#define SystemZ_VNC 2838 +#define SystemZ_VNN 2839 +#define SystemZ_VNO 2840 +#define SystemZ_VNX 2841 +#define SystemZ_VO 2842 +#define SystemZ_VOC 2843 +#define SystemZ_VONE 2844 +#define SystemZ_VPDI 2845 +#define SystemZ_VPERM 2846 +#define SystemZ_VPK 2847 +#define SystemZ_VPKF 2848 +#define SystemZ_VPKG 2849 +#define SystemZ_VPKH 2850 +#define SystemZ_VPKLS 2851 +#define SystemZ_VPKLSF 2852 +#define SystemZ_VPKLSFS 2853 +#define SystemZ_VPKLSG 2854 +#define SystemZ_VPKLSGS 2855 +#define SystemZ_VPKLSH 2856 +#define SystemZ_VPKLSHS 2857 +#define SystemZ_VPKS 2858 +#define SystemZ_VPKSF 2859 +#define SystemZ_VPKSFS 2860 +#define SystemZ_VPKSG 2861 +#define SystemZ_VPKSGS 2862 +#define SystemZ_VPKSH 2863 +#define SystemZ_VPKSHS 2864 +#define SystemZ_VPKZ 2865 +#define SystemZ_VPKZR 2866 +#define SystemZ_VPOPCT 2867 +#define SystemZ_VPOPCTB 2868 +#define SystemZ_VPOPCTF 2869 +#define SystemZ_VPOPCTG 2870 +#define SystemZ_VPOPCTH 2871 +#define SystemZ_VPSOP 2872 +#define SystemZ_VREP 2873 +#define SystemZ_VREPB 2874 +#define SystemZ_VREPF 2875 +#define SystemZ_VREPG 2876 +#define SystemZ_VREPH 2877 +#define SystemZ_VREPI 2878 +#define SystemZ_VREPIB 2879 +#define SystemZ_VREPIF 2880 +#define SystemZ_VREPIG 2881 +#define SystemZ_VREPIH 2882 +#define SystemZ_VRP 2883 +#define SystemZ_VS 2884 +#define SystemZ_VSB 2885 +#define SystemZ_VSBCBI 2886 +#define SystemZ_VSBCBIQ 2887 +#define SystemZ_VSBI 2888 +#define SystemZ_VSBIQ 2889 +#define SystemZ_VSCBI 2890 +#define SystemZ_VSCBIB 2891 +#define SystemZ_VSCBIF 2892 +#define SystemZ_VSCBIG 2893 +#define SystemZ_VSCBIH 2894 +#define SystemZ_VSCBIQ 2895 +#define SystemZ_VSCEF 2896 +#define SystemZ_VSCEG 2897 +#define SystemZ_VSCHDP 2898 +#define SystemZ_VSCHP 2899 +#define SystemZ_VSCHSP 2900 +#define SystemZ_VSCHXP 2901 +#define SystemZ_VSCSHP 2902 +#define SystemZ_VSDP 2903 +#define SystemZ_VSEG 2904 +#define SystemZ_VSEGB 2905 +#define SystemZ_VSEGF 2906 +#define SystemZ_VSEGH 2907 +#define SystemZ_VSEL 2908 +#define SystemZ_VSF 2909 +#define SystemZ_VSG 2910 +#define SystemZ_VSH 2911 +#define SystemZ_VSL 2912 +#define SystemZ_VSLB 2913 +#define SystemZ_VSLD 2914 +#define SystemZ_VSLDB 2915 +#define SystemZ_VSP 2916 +#define SystemZ_VSQ 2917 +#define SystemZ_VSRA 2918 +#define SystemZ_VSRAB 2919 +#define SystemZ_VSRD 2920 +#define SystemZ_VSRL 2921 +#define SystemZ_VSRLB 2922 +#define SystemZ_VSRP 2923 +#define SystemZ_VSRPR 2924 +#define SystemZ_VST 2925 +#define SystemZ_VSTAlign 2926 +#define SystemZ_VSTBR 2927 +#define SystemZ_VSTBRF 2928 +#define SystemZ_VSTBRG 2929 +#define SystemZ_VSTBRH 2930 +#define SystemZ_VSTBRQ 2931 +#define SystemZ_VSTEB 2932 +#define SystemZ_VSTEBRF 2933 +#define SystemZ_VSTEBRG 2934 +#define SystemZ_VSTEBRH 2935 +#define SystemZ_VSTEF 2936 +#define SystemZ_VSTEG 2937 +#define SystemZ_VSTEH 2938 +#define SystemZ_VSTER 2939 +#define SystemZ_VSTERF 2940 +#define SystemZ_VSTERG 2941 +#define SystemZ_VSTERH 2942 +#define SystemZ_VSTL 2943 +#define SystemZ_VSTM 2944 +#define SystemZ_VSTMAlign 2945 +#define SystemZ_VSTRC 2946 +#define SystemZ_VSTRCB 2947 +#define SystemZ_VSTRCBS 2948 +#define SystemZ_VSTRCF 2949 +#define SystemZ_VSTRCFS 2950 +#define SystemZ_VSTRCH 2951 +#define SystemZ_VSTRCHS 2952 +#define SystemZ_VSTRCZB 2953 +#define SystemZ_VSTRCZBS 2954 +#define SystemZ_VSTRCZF 2955 +#define SystemZ_VSTRCZFS 2956 +#define SystemZ_VSTRCZH 2957 +#define SystemZ_VSTRCZHS 2958 +#define SystemZ_VSTRL 2959 +#define SystemZ_VSTRLR 2960 +#define SystemZ_VSTRS 2961 +#define SystemZ_VSTRSB 2962 +#define SystemZ_VSTRSF 2963 +#define SystemZ_VSTRSH 2964 +#define SystemZ_VSTRSZB 2965 +#define SystemZ_VSTRSZF 2966 +#define SystemZ_VSTRSZH 2967 +#define SystemZ_VSUM 2968 +#define SystemZ_VSUMB 2969 +#define SystemZ_VSUMG 2970 +#define SystemZ_VSUMGF 2971 +#define SystemZ_VSUMGH 2972 +#define SystemZ_VSUMH 2973 +#define SystemZ_VSUMQ 2974 +#define SystemZ_VSUMQF 2975 +#define SystemZ_VSUMQG 2976 +#define SystemZ_VTM 2977 +#define SystemZ_VTP 2978 +#define SystemZ_VUPH 2979 +#define SystemZ_VUPHB 2980 +#define SystemZ_VUPHF 2981 +#define SystemZ_VUPHH 2982 +#define SystemZ_VUPKZ 2983 +#define SystemZ_VUPKZH 2984 +#define SystemZ_VUPKZL 2985 +#define SystemZ_VUPL 2986 +#define SystemZ_VUPLB 2987 +#define SystemZ_VUPLF 2988 +#define SystemZ_VUPLH 2989 +#define SystemZ_VUPLHB 2990 +#define SystemZ_VUPLHF 2991 +#define SystemZ_VUPLHH 2992 +#define SystemZ_VUPLHW 2993 +#define SystemZ_VUPLL 2994 +#define SystemZ_VUPLLB 2995 +#define SystemZ_VUPLLF 2996 +#define SystemZ_VUPLLH 2997 +#define SystemZ_VX 2998 +#define SystemZ_VZERO 2999 +#define SystemZ_WCDGB 3000 +#define SystemZ_WCDLGB 3001 +#define SystemZ_WCEFB 3002 +#define SystemZ_WCELFB 3003 +#define SystemZ_WCFEB 3004 +#define SystemZ_WCGDB 3005 +#define SystemZ_WCLFEB 3006 +#define SystemZ_WCLGDB 3007 +#define SystemZ_WFADB 3008 +#define SystemZ_WFASB 3009 +#define SystemZ_WFAXB 3010 +#define SystemZ_WFC 3011 +#define SystemZ_WFCDB 3012 +#define SystemZ_WFCEDB 3013 +#define SystemZ_WFCEDBS 3014 +#define SystemZ_WFCESB 3015 +#define SystemZ_WFCESBS 3016 +#define SystemZ_WFCEXB 3017 +#define SystemZ_WFCEXBS 3018 +#define SystemZ_WFCHDB 3019 +#define SystemZ_WFCHDBS 3020 +#define SystemZ_WFCHEDB 3021 +#define SystemZ_WFCHEDBS 3022 +#define SystemZ_WFCHESB 3023 +#define SystemZ_WFCHESBS 3024 +#define SystemZ_WFCHEXB 3025 +#define SystemZ_WFCHEXBS 3026 +#define SystemZ_WFCHSB 3027 +#define SystemZ_WFCHSBS 3028 +#define SystemZ_WFCHXB 3029 +#define SystemZ_WFCHXBS 3030 +#define SystemZ_WFCSB 3031 +#define SystemZ_WFCXB 3032 +#define SystemZ_WFDDB 3033 +#define SystemZ_WFDSB 3034 +#define SystemZ_WFDXB 3035 +#define SystemZ_WFIDB 3036 +#define SystemZ_WFISB 3037 +#define SystemZ_WFIXB 3038 +#define SystemZ_WFK 3039 +#define SystemZ_WFKDB 3040 +#define SystemZ_WFKEDB 3041 +#define SystemZ_WFKEDBS 3042 +#define SystemZ_WFKESB 3043 +#define SystemZ_WFKESBS 3044 +#define SystemZ_WFKEXB 3045 +#define SystemZ_WFKEXBS 3046 +#define SystemZ_WFKHDB 3047 +#define SystemZ_WFKHDBS 3048 +#define SystemZ_WFKHEDB 3049 +#define SystemZ_WFKHEDBS 3050 +#define SystemZ_WFKHESB 3051 +#define SystemZ_WFKHESBS 3052 +#define SystemZ_WFKHEXB 3053 +#define SystemZ_WFKHEXBS 3054 +#define SystemZ_WFKHSB 3055 +#define SystemZ_WFKHSBS 3056 +#define SystemZ_WFKHXB 3057 +#define SystemZ_WFKHXBS 3058 +#define SystemZ_WFKSB 3059 +#define SystemZ_WFKXB 3060 +#define SystemZ_WFLCDB 3061 +#define SystemZ_WFLCSB 3062 +#define SystemZ_WFLCXB 3063 +#define SystemZ_WFLLD 3064 +#define SystemZ_WFLLS 3065 +#define SystemZ_WFLNDB 3066 +#define SystemZ_WFLNSB 3067 +#define SystemZ_WFLNXB 3068 +#define SystemZ_WFLPDB 3069 +#define SystemZ_WFLPSB 3070 +#define SystemZ_WFLPXB 3071 +#define SystemZ_WFLRD 3072 +#define SystemZ_WFLRX 3073 +#define SystemZ_WFMADB 3074 +#define SystemZ_WFMASB 3075 +#define SystemZ_WFMAXB 3076 +#define SystemZ_WFMAXDB 3077 +#define SystemZ_WFMAXSB 3078 +#define SystemZ_WFMAXXB 3079 +#define SystemZ_WFMDB 3080 +#define SystemZ_WFMINDB 3081 +#define SystemZ_WFMINSB 3082 +#define SystemZ_WFMINXB 3083 +#define SystemZ_WFMSB 3084 +#define SystemZ_WFMSDB 3085 +#define SystemZ_WFMSSB 3086 +#define SystemZ_WFMSXB 3087 +#define SystemZ_WFMXB 3088 +#define SystemZ_WFNMADB 3089 +#define SystemZ_WFNMASB 3090 +#define SystemZ_WFNMAXB 3091 +#define SystemZ_WFNMSDB 3092 +#define SystemZ_WFNMSSB 3093 +#define SystemZ_WFNMSXB 3094 +#define SystemZ_WFPSODB 3095 +#define SystemZ_WFPSOSB 3096 +#define SystemZ_WFPSOXB 3097 +#define SystemZ_WFSDB 3098 +#define SystemZ_WFSQDB 3099 +#define SystemZ_WFSQSB 3100 +#define SystemZ_WFSQXB 3101 +#define SystemZ_WFSSB 3102 +#define SystemZ_WFSXB 3103 +#define SystemZ_WFTCIDB 3104 +#define SystemZ_WFTCISB 3105 +#define SystemZ_WFTCIXB 3106 +#define SystemZ_WLDEB 3107 +#define SystemZ_WLEDB 3108 +#define SystemZ_X 3109 +#define SystemZ_XC 3110 +#define SystemZ_XG 3111 +#define SystemZ_XGR 3112 +#define SystemZ_XGRK 3113 +#define SystemZ_XI 3114 +#define SystemZ_XIHF 3115 +#define SystemZ_XILF 3116 +#define SystemZ_XIY 3117 +#define SystemZ_XR 3118 +#define SystemZ_XRK 3119 +#define SystemZ_XSCH 3120 +#define SystemZ_XY 3121 +#define SystemZ_ZAP 3122 +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_REGINFO_EXTRA +#undef GET_REGINFO_EXTRA + + // Subregister indices + + enum { + NoSubRegister, + SystemZ_subreg_h32, // 1 + SystemZ_subreg_h64, // 2 + SystemZ_subreg_hh32, // 3 + SystemZ_subreg_hl32, // 4 + SystemZ_subreg_l32, // 5 + SystemZ_subreg_l64, // 6 + SystemZ_NUM_TARGET_SUBREGS + }; +#endif // GET_REGINFO_EXTRA + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + +static const MCPhysReg SystemZRegDiffLists[] = { + /* 0 */ 64854, 1, 1, 1, 0, + /* 5 */ 65324, 1, 0, + /* 8 */ 65471, 2, 0, + /* 11 */ 65473, 2, 0, + /* 14 */ 65475, 2, 0, + /* 17 */ 65477, 2, 0, + /* 20 */ 32, 40, 0, + /* 23 */ 65506, 40, 65494, 40, 0, + /* 28 */ 65508, 40, 65494, 40, 0, + /* 33 */ 65510, 40, 65494, 40, 0, + /* 38 */ 65512, 40, 65494, 40, 0, + /* 43 */ 65504, 40, 0, + /* 46 */ 65520, 40, 0, + /* 49 */ 65504, 41, 0, + /* 52 */ 65520, 41, 0, + /* 55 */ 65504, 42, 0, + /* 58 */ 65520, 42, 0, + /* 61 */ 65504, 43, 0, + /* 64 */ 65520, 43, 0, + /* 67 */ 65504, 44, 0, + /* 70 */ 65520, 44, 0, + /* 73 */ 65504, 45, 0, + /* 76 */ 65520, 45, 0, + /* 79 */ 65504, 46, 0, + /* 82 */ 65520, 46, 0, + /* 85 */ 65504, 47, 0, + /* 88 */ 65520, 47, 0, + /* 91 */ 65504, 48, 0, + /* 94 */ 65520, 48, 0, + /* 97 */ 65496, 65504, 56, 0, + /* 101 */ 65496, 65504, 58, 0, + /* 105 */ 65496, 65504, 60, 0, + /* 109 */ 65496, 65504, 62, 0, + /* 113 */ 65496, 65504, 64, 0, + /* 117 */ 65260, 0, + /* 119 */ 65293, 0, + /* 121 */ 65463, 0, + /* 123 */ 65503, 0, + /* 125 */ 65496, 65504, 0, + /* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0, + /* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0, + /* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0, + /* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0, + /* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0, + /* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0, + /* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0, + /* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0, + /* 184 */ 65535, 0, +}; + +static const uint16_t SystemZSubRegIdxLists[] = { + /* 0 */ 2, 1, 0, + /* 3 */ 5, 1, 0, + /* 6 */ 6, 1, 2, 3, 0, + /* 11 */ 6, 5, 1, 2, 4, 3, 0, +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char SystemZRegStrings[] = { + /* 0 */ "A10\0" + /* 4 */ "C10\0" + /* 8 */ "V10\0" + /* 12 */ "V20\0" + /* 16 */ "V30\0" + /* 20 */ "A0\0" + /* 23 */ "C0\0" + /* 26 */ "V0\0" + /* 29 */ "A11\0" + /* 33 */ "C11\0" + /* 37 */ "V11\0" + /* 41 */ "V21\0" + /* 45 */ "V31\0" + /* 49 */ "A1\0" + /* 52 */ "C1\0" + /* 55 */ "V1\0" + /* 58 */ "A12\0" + /* 62 */ "C12\0" + /* 66 */ "V12\0" + /* 70 */ "V22\0" + /* 74 */ "A2\0" + /* 77 */ "C2\0" + /* 80 */ "V2\0" + /* 83 */ "A13\0" + /* 87 */ "C13\0" + /* 91 */ "V13\0" + /* 95 */ "V23\0" + /* 99 */ "A3\0" + /* 102 */ "C3\0" + /* 105 */ "V3\0" + /* 108 */ "A14\0" + /* 112 */ "C14\0" + /* 116 */ "V14\0" + /* 120 */ "V24\0" + /* 124 */ "A4\0" + /* 127 */ "C4\0" + /* 130 */ "V4\0" + /* 133 */ "A15\0" + /* 137 */ "C15\0" + /* 141 */ "V15\0" + /* 145 */ "V25\0" + /* 149 */ "A5\0" + /* 152 */ "C5\0" + /* 155 */ "V5\0" + /* 158 */ "V16\0" + /* 162 */ "V26\0" + /* 166 */ "A6\0" + /* 169 */ "C6\0" + /* 172 */ "V6\0" + /* 175 */ "V17\0" + /* 179 */ "V27\0" + /* 183 */ "A7\0" + /* 186 */ "C7\0" + /* 189 */ "V7\0" + /* 192 */ "V18\0" + /* 196 */ "V28\0" + /* 200 */ "A8\0" + /* 203 */ "C8\0" + /* 206 */ "V8\0" + /* 209 */ "V19\0" + /* 213 */ "V29\0" + /* 217 */ "A9\0" + /* 220 */ "C9\0" + /* 223 */ "V9\0" + /* 226 */ "CC\0" + /* 229 */ "FPC\0" + /* 233 */ "F10D\0" + /* 238 */ "R10D\0" + /* 243 */ "F20D\0" + /* 248 */ "F30D\0" + /* 253 */ "F0D\0" + /* 257 */ "R0D\0" + /* 261 */ "F11D\0" + /* 266 */ "R11D\0" + /* 271 */ "F21D\0" + /* 276 */ "F31D\0" + /* 281 */ "F1D\0" + /* 285 */ "R1D\0" + /* 289 */ "F12D\0" + /* 294 */ "R12D\0" + /* 299 */ "F22D\0" + /* 304 */ "F2D\0" + /* 308 */ "R2D\0" + /* 312 */ "F13D\0" + /* 317 */ "R13D\0" + /* 322 */ "F23D\0" + /* 327 */ "F3D\0" + /* 331 */ "R3D\0" + /* 335 */ "F14D\0" + /* 340 */ "R14D\0" + /* 345 */ "F24D\0" + /* 350 */ "F4D\0" + /* 354 */ "R4D\0" + /* 358 */ "F15D\0" + /* 363 */ "R15D\0" + /* 368 */ "F25D\0" + /* 373 */ "F5D\0" + /* 377 */ "R5D\0" + /* 381 */ "F16D\0" + /* 386 */ "F26D\0" + /* 391 */ "F6D\0" + /* 395 */ "R6D\0" + /* 399 */ "F17D\0" + /* 404 */ "F27D\0" + /* 409 */ "F7D\0" + /* 413 */ "R7D\0" + /* 417 */ "F18D\0" + /* 422 */ "F28D\0" + /* 427 */ "F8D\0" + /* 431 */ "R8D\0" + /* 435 */ "F19D\0" + /* 440 */ "F29D\0" + /* 445 */ "F9D\0" + /* 449 */ "R9D\0" + /* 453 */ "R10H\0" + /* 458 */ "R0H\0" + /* 462 */ "R11H\0" + /* 467 */ "R1H\0" + /* 471 */ "R12H\0" + /* 476 */ "R2H\0" + /* 480 */ "R13H\0" + /* 485 */ "R3H\0" + /* 489 */ "R14H\0" + /* 494 */ "R4H\0" + /* 498 */ "R15H\0" + /* 503 */ "R5H\0" + /* 507 */ "R6H\0" + /* 511 */ "R7H\0" + /* 515 */ "R8H\0" + /* 519 */ "R9H\0" + /* 523 */ "R10L\0" + /* 528 */ "R0L\0" + /* 532 */ "R11L\0" + /* 537 */ "R1L\0" + /* 541 */ "R12L\0" + /* 546 */ "R2L\0" + /* 550 */ "R13L\0" + /* 555 */ "R3L\0" + /* 559 */ "R14L\0" + /* 564 */ "R4L\0" + /* 568 */ "R15L\0" + /* 573 */ "R5L\0" + /* 577 */ "R6L\0" + /* 581 */ "R7L\0" + /* 585 */ "R8L\0" + /* 589 */ "R9L\0" + /* 593 */ "R10Q\0" + /* 598 */ "F0Q\0" + /* 602 */ "R0Q\0" + /* 606 */ "F1Q\0" + /* 610 */ "F12Q\0" + /* 615 */ "R12Q\0" + /* 620 */ "R2Q\0" + /* 624 */ "F13Q\0" + /* 629 */ "R14Q\0" + /* 634 */ "F4Q\0" + /* 638 */ "R4Q\0" + /* 642 */ "F5Q\0" + /* 646 */ "R6Q\0" + /* 650 */ "F8Q\0" + /* 654 */ "R8Q\0" + /* 658 */ "F9Q\0" + /* 662 */ "F10S\0" + /* 667 */ "F20S\0" + /* 672 */ "F30S\0" + /* 677 */ "F0S\0" + /* 681 */ "F11S\0" + /* 686 */ "F21S\0" + /* 691 */ "F31S\0" + /* 696 */ "F1S\0" + /* 700 */ "F12S\0" + /* 705 */ "F22S\0" + /* 710 */ "F2S\0" + /* 714 */ "F13S\0" + /* 719 */ "F23S\0" + /* 724 */ "F3S\0" + /* 728 */ "F14S\0" + /* 733 */ "F24S\0" + /* 738 */ "F4S\0" + /* 742 */ "F15S\0" + /* 747 */ "F25S\0" + /* 752 */ "F5S\0" + /* 756 */ "F16S\0" + /* 761 */ "F26S\0" + /* 766 */ "F6S\0" + /* 770 */ "F17S\0" + /* 775 */ "F27S\0" + /* 780 */ "F7S\0" + /* 784 */ "F18S\0" + /* 789 */ "F28S\0" + /* 794 */ "F8S\0" + /* 798 */ "F19S\0" + /* 803 */ "F29S\0" + /* 808 */ "F9S\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterDesc SystemZRegDesc[] = { + // Descriptors + {3, 0, 0, 0, 0, 0}, {226, 4, 4, 2, 2945, 226}, + {229, 4, 4, 2, 2945, 26}, {20, 4, 4, 2, 2945, 3}, + {49, 4, 4, 2, 2945, 51}, {74, 4, 4, 2, 2945, 3}, + {99, 4, 4, 2, 2945, 41}, {124, 4, 4, 2, 2945, 63}, + {149, 4, 4, 2, 2945, 128}, {166, 4, 4, 2, 2945, 132}, + {183, 4, 4, 2, 2945, 61}, {200, 4, 4, 2, 2945, 65}, + {217, 4, 4, 2, 2945, 79}, {0, 4, 4, 2, 2945, 41}, + {29, 4, 4, 2, 2945, 71}, {58, 4, 4, 2, 2945, 69}, + {83, 4, 4, 2, 2945, 3}, {108, 4, 4, 2, 2945, 3}, + {133, 4, 4, 2, 2945, 136}, {23, 4, 4, 2, 2945, 3}, + {52, 4, 4, 2, 2945, 41}, {77, 4, 4, 2, 2945, 218}, + {102, 4, 4, 2, 2945, 3}, {127, 4, 4, 2, 2945, 51}, + {152, 4, 4, 2, 2945, 150}, {169, 4, 4, 2, 2945, 6}, + {186, 4, 4, 2, 2945, 3}, {203, 4, 4, 2, 2945, 3}, + {220, 4, 4, 2, 2945, 67}, {4, 4, 4, 2, 2945, 17}, + {33, 4, 4, 2, 2945, 51}, {62, 4, 4, 2, 2945, 218}, + {87, 4, 4, 2, 2945, 204}, {112, 4, 4, 2, 2945, 6}, + {137, 4, 4, 2, 2945, 17}, {26, 20, 4, 0, 2945, 30}, + {55, 20, 4, 0, 2945, 41}, {80, 20, 4, 0, 2945, 51}, + {105, 20, 4, 0, 2945, 208}, {130, 20, 4, 0, 2945, 17}, + {155, 20, 4, 0, 2945, 30}, {172, 20, 4, 0, 2945, 41}, + {189, 20, 4, 0, 2945, 51}, {206, 20, 4, 0, 2945, 206}, + {223, 20, 4, 0, 2945, 3}, {8, 20, 4, 0, 2945, 202}, + {37, 20, 4, 0, 2945, 24}, {66, 20, 4, 0, 2945, 51}, + {91, 20, 4, 0, 2945, 130}, {116, 20, 4, 0, 2945, 51}, + {141, 20, 4, 0, 2945, 3}, {158, 20, 4, 0, 2945, 51}, + {175, 20, 4, 0, 2945, 116}, {192, 20, 4, 0, 2945, 120}, + {209, 20, 4, 0, 2945, 210}, {12, 20, 4, 0, 2945, 6}, + {41, 20, 4, 0, 2945, 51}, {70, 20, 4, 0, 2945, 184}, + {95, 20, 4, 0, 2945, 182}, {120, 20, 4, 0, 2945, 34}, + {145, 20, 4, 0, 2945, 3}, {162, 20, 4, 0, 2945, 36}, + {179, 20, 4, 0, 2945, 51}, {196, 20, 4, 0, 2945, 51}, + {213, 20, 4, 0, 2945, 90}, {16, 20, 4, 0, 2945, 28}, + {45, 20, 4, 0, 2945, 86}, {253, 21, 114, 1, 1969, 88}, + {281, 21, 114, 1, 1969, 73}, {304, 21, 110, 1, 1969, 75}, + {327, 21, 110, 1, 1969, 77}, {350, 21, 110, 1, 1969, 81}, + {373, 21, 110, 1, 1969, 222}, {391, 21, 106, 1, 1969, 224}, + {409, 21, 106, 1, 1969, 220}, {427, 21, 106, 1, 1969, 51}, + {445, 21, 106, 1, 1969, 198}, {233, 21, 102, 1, 1969, 51}, + {261, 21, 102, 1, 1969, 51}, {289, 21, 102, 1, 1969, 3}, + {312, 21, 102, 1, 1969, 3}, {335, 21, 98, 1, 1969, 200}, + {358, 21, 98, 1, 1969, 32}, {381, 21, 126, 1, 1969, 51}, + {399, 21, 126, 1, 1969, 194}, {417, 21, 126, 1, 1969, 51}, + {435, 21, 126, 1, 1969, 51}, {243, 21, 126, 1, 1969, 3}, + {271, 21, 126, 1, 1969, 3}, {299, 21, 126, 1, 1969, 196}, + {322, 21, 126, 1, 1969, 32}, {345, 21, 126, 1, 1969, 59}, + {368, 21, 126, 1, 1969, 190}, {386, 21, 126, 1, 1969, 3}, + {404, 21, 126, 1, 1969, 192}, {422, 21, 126, 1, 1969, 24}, + {440, 21, 126, 1, 1969, 51}, {248, 21, 126, 1, 1969, 130}, + {276, 21, 126, 1, 1969, 3}, {598, 23, 4, 6, 129, 96}, + {606, 23, 4, 6, 129, 83}, {634, 28, 4, 6, 177, 147}, + {642, 28, 4, 6, 177, 2}, {650, 33, 4, 6, 225, 212}, + {658, 33, 4, 6, 225, 215}, {610, 38, 4, 6, 273, 40}, + {624, 38, 4, 6, 273, 138}, {677, 4, 113, 2, 1937, 118}, + {696, 4, 113, 2, 1937, 3}, {710, 4, 109, 2, 1937, 3}, + {724, 4, 109, 2, 1937, 134}, {738, 4, 109, 2, 1937, 6}, + {752, 4, 109, 2, 1937, 6}, {766, 4, 105, 2, 1937, 51}, + {780, 4, 105, 2, 1937, 159}, {794, 4, 105, 2, 1937, 157}, + {808, 4, 105, 2, 1937, 3}, {662, 4, 101, 2, 1937, 51}, + {681, 4, 101, 2, 1937, 218}, {700, 4, 101, 2, 1937, 3}, + {714, 4, 101, 2, 1937, 3}, {728, 4, 97, 2, 1937, 3}, + {742, 4, 97, 2, 1937, 6}, {756, 4, 125, 2, 1937, 6}, + {770, 4, 125, 2, 1937, 51}, {784, 4, 125, 2, 1937, 145}, + {798, 4, 125, 2, 1937, 143}, {667, 4, 125, 2, 1937, 3}, + {686, 4, 125, 2, 1937, 51}, {705, 4, 125, 2, 1937, 218}, + {719, 4, 125, 2, 1937, 3}, {733, 4, 125, 2, 1937, 3}, + {747, 4, 125, 2, 1937, 3}, {761, 4, 125, 2, 1937, 94}, + {775, 4, 125, 2, 1937, 51}, {789, 4, 125, 2, 1937, 51}, + {803, 4, 125, 2, 1937, 111}, {672, 4, 125, 2, 1937, 15}, + {691, 4, 125, 2, 1937, 92}, {257, 132, 92, 3, 82, 113}, + {285, 132, 86, 3, 82, 8}, {308, 132, 86, 3, 82, 50}, + {331, 132, 80, 3, 82, 56}, {354, 132, 80, 3, 82, 2}, + {377, 132, 74, 3, 82, 99}, {395, 132, 74, 3, 82, 102}, + {413, 132, 68, 3, 82, 5}, {431, 132, 68, 3, 82, 50}, + {449, 132, 62, 3, 82, 105}, {238, 132, 62, 3, 82, 108}, + {266, 132, 56, 3, 82, 2}, {294, 132, 56, 3, 82, 50}, + {317, 132, 50, 3, 82, 53}, {340, 132, 50, 3, 82, 19}, + {363, 132, 21, 3, 82, 50}, {458, 4, 94, 2, 1906, 6}, + {467, 4, 88, 2, 1906, 3}, {476, 4, 88, 2, 1906, 3}, + {485, 4, 82, 2, 1906, 51}, {494, 4, 82, 2, 1906, 41}, + {503, 4, 76, 2, 1906, 3}, {507, 4, 76, 2, 1906, 186}, + {511, 4, 70, 2, 1906, 51}, {515, 4, 70, 2, 1906, 41}, + {519, 4, 64, 2, 1906, 3}, {453, 4, 64, 2, 1906, 188}, + {462, 4, 58, 2, 1906, 51}, {471, 4, 58, 2, 1906, 22}, + {480, 4, 52, 2, 1906, 13}, {489, 4, 52, 2, 1906, 3}, + {498, 4, 46, 2, 1906, 122}, {528, 4, 91, 2, 1874, 3}, + {537, 4, 85, 2, 1874, 6}, {546, 4, 85, 2, 1874, 51}, + {555, 4, 79, 2, 1874, 38}, {564, 4, 79, 2, 1874, 22}, + {573, 4, 73, 2, 1874, 46}, {577, 4, 73, 2, 1874, 218}, + {581, 4, 67, 2, 1874, 124}, {585, 4, 67, 2, 1874, 126}, + {589, 4, 61, 2, 1874, 3}, {523, 4, 61, 2, 1874, 161}, + {532, 4, 55, 2, 1874, 163}, {541, 4, 55, 2, 1874, 46}, + {550, 4, 49, 2, 1874, 165}, {559, 4, 49, 2, 1874, 11}, + {568, 4, 43, 2, 1874, 141}, {602, 128, 4, 11, 4, 0}, + {620, 135, 4, 11, 4, 48}, {638, 142, 4, 11, 4, 167}, + {646, 149, 4, 11, 4, 43}, {654, 156, 4, 11, 4, 172}, + {593, 163, 4, 11, 4, 177}, {615, 170, 4, 11, 4, 152}, + {629, 177, 4, 11, 4, 48}, +}; + +// GRX32Bit Register Class... +static const MCPhysReg GRX32Bit[] = { + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, + SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, + SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, + SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, + SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, + SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, + SystemZ_R6L, SystemZ_R6H, +}; + +// GRX32Bit Bit set. +static const uint8_t GRX32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// VR32Bit Register Class... +static const MCPhysReg VR32Bit[] = { + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, + SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, + SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, + SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, + SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, + SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, + SystemZ_F14S, SystemZ_F15S, +}; + +// VR32Bit Bit set. +static const uint8_t VR32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// AR32Bit Register Class... +static const MCPhysReg AR32Bit[] = { + SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, + SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, + SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, + SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15, +}; + +// AR32Bit Bit set. +static const uint8_t AR32BitBits[] = { + 0xf8, + 0xff, + 0x07, +}; + +// FP32Bit Register Class... +static const MCPhysReg FP32Bit[] = { + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, + SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, + SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, + SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, +}; + +// FP32Bit Bit set. +static const uint8_t FP32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// GR32Bit Register Class... +static const MCPhysReg GR32Bit[] = { + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, + SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, + SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, + SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, +}; + +// GR32Bit Bit set. +static const uint8_t GR32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// GRH32Bit Register Class... +static const MCPhysReg GRH32Bit[] = { + SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, + SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, + SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, + SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H, +}; + +// GRH32Bit Bit set. +static const uint8_t GRH32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// ADDR32Bit Register Class... +static const MCPhysReg ADDR32Bit[] = { + SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, + SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, + SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, +}; + +// ADDR32Bit Bit set. +static const uint8_t ADDR32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, +}; + +// CCR Register Class... +static const MCPhysReg CCR[] = { + SystemZ_CC, +}; + +// CCR Bit set. +static const uint8_t CCRBits[] = { + 0x02, +}; + +// FPCRegs Register Class... +static const MCPhysReg FPCRegs[] = { + SystemZ_FPC, +}; + +// FPCRegs Bit set. +static const uint8_t FPCRegsBits[] = { + 0x04, +}; + +// AnyRegBit Register Class... +static const MCPhysReg AnyRegBit[] = { + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, + SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, + SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, + SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, + SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, + SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, + SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, + SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, + SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, + SystemZ_V13, SystemZ_V14, SystemZ_V15, +}; + +// AnyRegBit Bit set. +static const uint8_t AnyRegBitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, + 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// AnyRegBit_with_subreg_h32_in_FP32Bit Register Class... +static const MCPhysReg AnyRegBit_with_subreg_h32_in_FP32Bit[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, + SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, + SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, + SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, + SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, + SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, + SystemZ_V14, SystemZ_V15, +}; + +// AnyRegBit_with_subreg_h32_in_FP32Bit Bit set. +static const uint8_t AnyRegBit_with_subreg_h32_in_FP32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07, +}; + +// VR64Bit Register Class... +static const MCPhysReg VR64Bit[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, + SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, + SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, + SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, + SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, + SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, + SystemZ_F14D, SystemZ_F15D, +}; + +// VR64Bit Bit set. +static const uint8_t VR64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// AnyRegBit_with_subreg_h64 Register Class... +static const MCPhysReg AnyRegBit_with_subreg_h64[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, + SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, + SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, + SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, +}; + +// AnyRegBit_with_subreg_h64 Bit set. +static const uint8_t AnyRegBit_with_subreg_h64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// CR64Bit Register Class... +static const MCPhysReg CR64Bit[] = { + SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, + SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, + SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, + SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15, +}; + +// CR64Bit Bit set. +static const uint8_t CR64BitBits[] = { + 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// FP64Bit Register Class... +static const MCPhysReg FP64Bit[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, + SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, + SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, + SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, +}; + +// FP64Bit Bit set. +static const uint8_t FP64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// GR64Bit Register Class... +static const MCPhysReg GR64Bit[] = { + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, + SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, + SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, + SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, +}; + +// GR64Bit Bit set. +static const uint8_t GR64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// ADDR64Bit Register Class... +static const MCPhysReg ADDR64Bit[] = { + SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, + SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, + SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, +}; + +// ADDR64Bit Bit set. +static const uint8_t ADDR64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, +}; + +// VR128Bit Register Class... +static const MCPhysReg VR128Bit[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, + SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, + SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, + SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, + SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, + SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, + SystemZ_V14, SystemZ_V15, +}; + +// VR128Bit Bit set. +static const uint8_t VR128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, +}; + +// VF128Bit Register Class... +static const MCPhysReg VF128Bit[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, + SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, + SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, + SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, +}; + +// VF128Bit Bit set. +static const uint8_t VF128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, +}; + +// FP128Bit Register Class... +static const MCPhysReg FP128Bit[] = { + SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, + SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q, +}; + +// FP128Bit Bit set. +static const uint8_t FP128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, +}; + +// GR128Bit Register Class... +static const MCPhysReg GR128Bit[] = { + SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, + SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, +}; + +// GR128Bit Bit set. +static const uint8_t GR128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, +}; + +// ADDR128Bit Register Class... +static const MCPhysReg ADDR128Bit[] = { + SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, + SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, +}; + +// ADDR128Bit Bit set. +static const uint8_t ADDR128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, +}; + +// end of register classes misc + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char SystemZRegClassStrings[] = { + /* 0 */ "AnyRegBit_with_subreg_h64\0" + /* 26 */ "CCR\0" + /* 30 */ "FPCRegs\0" + /* 38 */ "GRH32Bit\0" + /* 47 */ "AnyRegBit_with_subreg_h32_in_FP32Bit\0" + /* 84 */ "AR32Bit\0" + /* 92 */ "ADDR32Bit\0" + /* 102 */ "GR32Bit\0" + /* 110 */ "VR32Bit\0" + /* 118 */ "GRX32Bit\0" + /* 127 */ "FP64Bit\0" + /* 135 */ "CR64Bit\0" + /* 143 */ "ADDR64Bit\0" + /* 153 */ "GR64Bit\0" + /* 161 */ "VR64Bit\0" + /* 169 */ "VF128Bit\0" + /* 178 */ "FP128Bit\0" + /* 187 */ "ADDR128Bit\0" + /* 198 */ "GR128Bit\0" + /* 207 */ "VR128Bit\0" + /* 216 */ "AnyRegBit\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterClass SystemZMCRegisterClasses[] = { + {GRX32Bit, GRX32BitBits, sizeof(GRX32BitBits)}, + {VR32Bit, VR32BitBits, sizeof(VR32BitBits)}, + {AR32Bit, AR32BitBits, sizeof(AR32BitBits)}, + {FP32Bit, FP32BitBits, sizeof(FP32BitBits)}, + {GR32Bit, GR32BitBits, sizeof(GR32BitBits)}, + {GRH32Bit, GRH32BitBits, sizeof(GRH32BitBits)}, + {ADDR32Bit, ADDR32BitBits, sizeof(ADDR32BitBits)}, + {CCR, CCRBits, sizeof(CCRBits)}, + {FPCRegs, FPCRegsBits, sizeof(FPCRegsBits)}, + {AnyRegBit, AnyRegBitBits, sizeof(AnyRegBitBits)}, + {AnyRegBit_with_subreg_h32_in_FP32Bit, + AnyRegBit_with_subreg_h32_in_FP32BitBits, + sizeof(AnyRegBit_with_subreg_h32_in_FP32BitBits)}, + {VR64Bit, VR64BitBits, sizeof(VR64BitBits)}, + {AnyRegBit_with_subreg_h64, AnyRegBit_with_subreg_h64Bits, + sizeof(AnyRegBit_with_subreg_h64Bits)}, + {CR64Bit, CR64BitBits, sizeof(CR64BitBits)}, + {FP64Bit, FP64BitBits, sizeof(FP64BitBits)}, + {GR64Bit, GR64BitBits, sizeof(GR64BitBits)}, + {ADDR64Bit, ADDR64BitBits, sizeof(ADDR64BitBits)}, + {VR128Bit, VR128BitBits, sizeof(VR128BitBits)}, + {VF128Bit, VF128BitBits, sizeof(VF128BitBits)}, + {FP128Bit, FP128BitBits, sizeof(FP128BitBits)}, + {GR128Bit, GR128BitBits, sizeof(GR128BitBits)}, + {ADDR128Bit, ADDR128BitBits, sizeof(ADDR128BitBits)}, +}; + +#endif // GET_REGINFO_MC_DESC + +#ifdef GET_ASM_WRITER +#undef GET_ASM_WRITER + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +typedef struct MCMnemonic { + const char *first; + uint64_t second; +} MCMnemonic; + +static MCMnemonic createMnemonic(const char *first, uint64_t second) { + MCMnemonic mnemonic; + mnemonic.first = first; + mnemonic.second = second; + return mnemonic; } -#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ -{ \ - uint64_t Bits = getFeatureBits(feature); \ - const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0, ExpectedValue; \ - DecodeStatus S = MCDisassembler_Success; \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail; \ - for (;;) { \ - switch (*Ptr) { \ - default: \ - return MCDisassembler_Fail; \ - case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - ++Ptr; \ - CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ - break; \ - } \ - case MCD_OPC_FilterValue: { \ - Val = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (Val != CurFieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (ExpectedValue != FieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckPredicate: { \ - PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - Pred = checkDecoderPredicate(PIdx, Bits); \ - if (!Pred) \ - Ptr += NumToSkip; \ - (void)Pred; \ - break; \ - } \ - case MCD_OPC_Decode: { \ - Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - MCInst_setOpcode(MI, Opc); \ - return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ - } \ - case MCD_OPC_SoftFail: { \ - PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ - if (Fail) \ - S = MCDisassembler_SoftFail; \ - break; \ - } \ - case MCD_OPC_Fail: { \ - return MCDisassembler_Fail; \ - } \ - } \ - } \ +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +MCMnemonic SystemZ_getMnemonic(const MCInst *MI) { + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "cu21\t\0" + /* 6 */ "cu41\t\0" + /* 12 */ "cu12\t\0" + /* 18 */ "cu42\t\0" + /* 24 */ "cu14\t\0" + /* 30 */ "cu24\t\0" + /* 36 */ "trap4\t\0" + /* 43 */ "laa\t\0" + /* 48 */ "slda\t\0" + /* 54 */ "srda\t\0" + /* 60 */ "esea\t\0" + /* 66 */ "lptea\t\0" + /* 73 */ "vfa\t\0" + /* 78 */ "siga\t\0" + /* 84 */ "ecpga\t\0" + /* 91 */ "unpka\t\0" + /* 98 */ "spka\t\0" + /* 104 */ "sla\t\0" + /* 109 */ "vgfma\t\0" + /* 116 */ "vfma\t\0" + /* 122 */ "kma\t\0" + /* 127 */ "vfnma\t\0" + /* 134 */ "ppa\t\0" + /* 139 */ "ledbra\t\0" + /* 147 */ "cfdbra\t\0" + /* 155 */ "cgdbra\t\0" + /* 163 */ "fidbra\t\0" + /* 171 */ "cfebra\t\0" + /* 179 */ "cgebra\t\0" + /* 187 */ "fiebra\t\0" + /* 195 */ "cdfbra\t\0" + /* 203 */ "cefbra\t\0" + /* 211 */ "cxfbra\t\0" + /* 219 */ "cdgbra\t\0" + /* 227 */ "cegbra\t\0" + /* 235 */ "cxgbra\t\0" + /* 243 */ "ldxbra\t\0" + /* 251 */ "lexbra\t\0" + /* 259 */ "cfxbra\t\0" + /* 267 */ "cgxbra\t\0" + /* 275 */ "fixbra\t\0" + /* 283 */ "lra\t\0" + /* 288 */ "vesra\t\0" + /* 295 */ "vsra\t\0" + /* 301 */ "adtra\t\0" + /* 308 */ "ddtra\t\0" + /* 315 */ "cgdtra\t\0" + /* 323 */ "mdtra\t\0" + /* 330 */ "sdtra\t\0" + /* 337 */ "cdgtra\t\0" + /* 345 */ "cxgtra\t\0" + /* 353 */ "axtra\t\0" + /* 360 */ "dxtra\t\0" + /* 367 */ "cgxtra\t\0" + /* 375 */ "mxtra\t\0" + /* 382 */ "sxtra\t\0" + /* 389 */ "lura\t\0" + /* 395 */ "stura\t\0" + /* 402 */ "bsa\t\0" + /* 407 */ "kdsa\t\0" + /* 413 */ "esta\t\0" + /* 419 */ "msta\t\0" + /* 425 */ "va\t\0" + /* 429 */ "cpya\t\0" + /* 435 */ "vgfmab\t\0" + /* 443 */ "vesrab\t\0" + /* 451 */ "vsrab\t\0" + /* 458 */ "vab\t\0" + /* 463 */ "lcbb\t\0" + /* 469 */ "vlbb\t\0" + /* 475 */ "vaccb\t\0" + /* 482 */ "vecb\t\0" + /* 488 */ "vlcb\t\0" + /* 494 */ "vstrcb\t\0" + /* 502 */ "vfadb\t\0" + /* 509 */ "wfadb\t\0" + /* 516 */ "vfmadb\t\0" + /* 524 */ "wfmadb\t\0" + /* 532 */ "vfnmadb\t\0" + /* 541 */ "wfnmadb\t\0" + /* 550 */ "wfcdb\t\0" + /* 557 */ "vflcdb\t\0" + /* 565 */ "wflcdb\t\0" + /* 573 */ "tcdb\t\0" + /* 579 */ "vfddb\t\0" + /* 586 */ "wfddb\t\0" + /* 593 */ "vfcedb\t\0" + /* 601 */ "wfcedb\t\0" + /* 609 */ "vfchedb\t\0" + /* 618 */ "wfchedb\t\0" + /* 627 */ "vfkhedb\t\0" + /* 636 */ "wfkhedb\t\0" + /* 645 */ "vfkedb\t\0" + /* 653 */ "wfkedb\t\0" + /* 661 */ "vledb\t\0" + /* 668 */ "wledb\t\0" + /* 675 */ "vcgdb\t\0" + /* 682 */ "wcgdb\t\0" + /* 689 */ "vclgdb\t\0" + /* 697 */ "wclgdb\t\0" + /* 705 */ "vfchdb\t\0" + /* 713 */ "wfchdb\t\0" + /* 721 */ "vfkhdb\t\0" + /* 729 */ "wfkhdb\t\0" + /* 737 */ "vftcidb\t\0" + /* 746 */ "wftcidb\t\0" + /* 755 */ "vfidb\t\0" + /* 762 */ "wfidb\t\0" + /* 769 */ "wfkdb\t\0" + /* 776 */ "vsldb\t\0" + /* 783 */ "vfmdb\t\0" + /* 790 */ "wfmdb\t\0" + /* 797 */ "vfmindb\t\0" + /* 806 */ "wfmindb\t\0" + /* 815 */ "vflndb\t\0" + /* 823 */ "wflndb\t\0" + /* 831 */ "vfpsodb\t\0" + /* 840 */ "wfpsodb\t\0" + /* 849 */ "vflpdb\t\0" + /* 857 */ "wflpdb\t\0" + /* 865 */ "vfsqdb\t\0" + /* 873 */ "wfsqdb\t\0" + /* 881 */ "vfsdb\t\0" + /* 888 */ "wfsdb\t\0" + /* 895 */ "vfmsdb\t\0" + /* 903 */ "wfmsdb\t\0" + /* 911 */ "vfnmsdb\t\0" + /* 920 */ "wfnmsdb\t\0" + /* 929 */ "vfmaxdb\t\0" + /* 938 */ "wfmaxdb\t\0" + /* 947 */ "lxdb\t\0" + /* 953 */ "mxdb\t\0" + /* 959 */ "vfaeb\t\0" + /* 966 */ "vmaeb\t\0" + /* 973 */ "tceb\t\0" + /* 979 */ "vldeb\t\0" + /* 986 */ "wldeb\t\0" + /* 993 */ "mdeb\t\0" + /* 999 */ "vfeeb\t\0" + /* 1006 */ "meeb\t\0" + /* 1012 */ "vcfeb\t\0" + /* 1019 */ "wcfeb\t\0" + /* 1026 */ "vclfeb\t\0" + /* 1034 */ "wclfeb\t\0" + /* 1042 */ "keb\t\0" + /* 1047 */ "vmaleb\t\0" + /* 1055 */ "vmleb\t\0" + /* 1062 */ "vleb\t\0" + /* 1068 */ "vmeb\t\0" + /* 1074 */ "vfeneb\t\0" + /* 1082 */ "sqeb\t\0" + /* 1088 */ "mseb\t\0" + /* 1094 */ "vsteb\t\0" + /* 1101 */ "lxeb\t\0" + /* 1107 */ "vcefb\t\0" + /* 1114 */ "wcefb\t\0" + /* 1121 */ "vcelfb\t\0" + /* 1129 */ "wcelfb\t\0" + /* 1137 */ "vcdgb\t\0" + /* 1144 */ "wcdgb\t\0" + /* 1151 */ "vsegb\t\0" + /* 1158 */ "vcdlgb\t\0" + /* 1166 */ "wcdlgb\t\0" + /* 1174 */ "vavgb\t\0" + /* 1181 */ "vlvgb\t\0" + /* 1188 */ "vmahb\t\0" + /* 1195 */ "vchb\t\0" + /* 1201 */ "vmalhb\t\0" + /* 1209 */ "vmlhb\t\0" + /* 1216 */ "vuplhb\t\0" + /* 1224 */ "vmhb\t\0" + /* 1230 */ "vuphb\t\0" + /* 1237 */ "vmrhb\t\0" + /* 1244 */ "vscbib\t\0" + /* 1252 */ "cib\t\0" + /* 1257 */ "vleib\t\0" + /* 1264 */ "cgib\t\0" + /* 1270 */ "clgib\t\0" + /* 1277 */ "clib\t\0" + /* 1283 */ "vrepib\t\0" + /* 1291 */ "vmalb\t\0" + /* 1298 */ "veclb\t\0" + /* 1305 */ "vavglb\t\0" + /* 1313 */ "vchlb\t\0" + /* 1320 */ "vupllb\t\0" + /* 1328 */ "verllb\t\0" + /* 1336 */ "vmlb\t\0" + /* 1342 */ "vmnlb\t\0" + /* 1349 */ "vuplb\t\0" + /* 1356 */ "vmrlb\t\0" + /* 1363 */ "vesrlb\t\0" + /* 1371 */ "vsrlb\t\0" + /* 1378 */ "veslb\t\0" + /* 1385 */ "vslb\t\0" + /* 1391 */ "vmxlb\t\0" + /* 1398 */ "vgfmb\t\0" + /* 1405 */ "vgmb\t\0" + /* 1411 */ "verimb\t\0" + /* 1419 */ "srnmb\t\0" + /* 1426 */ "vsumb\t\0" + /* 1433 */ "vmnb\t\0" + /* 1439 */ "vmaob\t\0" + /* 1446 */ "vmalob\t\0" + /* 1454 */ "vmlob\t\0" + /* 1461 */ "vmob\t\0" + /* 1467 */ "vlrepb\t\0" + /* 1475 */ "vrepb\t\0" + /* 1482 */ "vlpb\t\0" + /* 1488 */ "vceqb\t\0" + /* 1495 */ "crb\t\0" + /* 1500 */ "cgrb\t\0" + /* 1506 */ "clgrb\t\0" + /* 1513 */ "clrb\t\0" + /* 1519 */ "vistrb\t\0" + /* 1527 */ "vfasb\t\0" + /* 1534 */ "wfasb\t\0" + /* 1541 */ "vfmasb\t\0" + /* 1549 */ "wfmasb\t\0" + /* 1557 */ "vfnmasb\t\0" + /* 1566 */ "wfnmasb\t\0" + /* 1575 */ "wfcsb\t\0" + /* 1582 */ "vflcsb\t\0" + /* 1590 */ "wflcsb\t\0" + /* 1598 */ "vfdsb\t\0" + /* 1605 */ "wfdsb\t\0" + /* 1612 */ "vfcesb\t\0" + /* 1620 */ "wfcesb\t\0" + /* 1628 */ "vfchesb\t\0" + /* 1637 */ "wfchesb\t\0" + /* 1646 */ "vfkhesb\t\0" + /* 1655 */ "wfkhesb\t\0" + /* 1664 */ "vfkesb\t\0" + /* 1672 */ "wfkesb\t\0" + /* 1680 */ "vfchsb\t\0" + /* 1688 */ "wfchsb\t\0" + /* 1696 */ "vfkhsb\t\0" + /* 1704 */ "wfkhsb\t\0" + /* 1712 */ "vftcisb\t\0" + /* 1721 */ "wftcisb\t\0" + /* 1730 */ "vfisb\t\0" + /* 1737 */ "wfisb\t\0" + /* 1744 */ "wfksb\t\0" + /* 1751 */ "vfmsb\t\0" + /* 1758 */ "wfmsb\t\0" + /* 1765 */ "vfminsb\t\0" + /* 1774 */ "wfminsb\t\0" + /* 1783 */ "vflnsb\t\0" + /* 1791 */ "wflnsb\t\0" + /* 1799 */ "vfpsosb\t\0" + /* 1808 */ "wfpsosb\t\0" + /* 1817 */ "vflpsb\t\0" + /* 1825 */ "wflpsb\t\0" + /* 1833 */ "vfsqsb\t\0" + /* 1841 */ "wfsqsb\t\0" + /* 1849 */ "vstrsb\t\0" + /* 1857 */ "vfssb\t\0" + /* 1864 */ "wfssb\t\0" + /* 1871 */ "vfmssb\t\0" + /* 1879 */ "wfmssb\t\0" + /* 1887 */ "vfnmssb\t\0" + /* 1896 */ "wfnmssb\t\0" + /* 1905 */ "vsb\t\0" + /* 1910 */ "vfmaxsb\t\0" + /* 1919 */ "wfmaxsb\t\0" + /* 1928 */ "vpopctb\t\0" + /* 1937 */ "vesravb\t\0" + /* 1946 */ "vcvb\t\0" + /* 1952 */ "vlgvb\t\0" + /* 1959 */ "verllvb\t\0" + /* 1968 */ "vesrlvb\t\0" + /* 1977 */ "veslvb\t\0" + /* 1985 */ "wfaxb\t\0" + /* 1992 */ "wfmaxb\t\0" + /* 2000 */ "wfnmaxb\t\0" + /* 2009 */ "wfcxb\t\0" + /* 2016 */ "wflcxb\t\0" + /* 2024 */ "tcxb\t\0" + /* 2030 */ "wfdxb\t\0" + /* 2037 */ "wfcexb\t\0" + /* 2045 */ "wfchexb\t\0" + /* 2054 */ "wfkhexb\t\0" + /* 2063 */ "wfkexb\t\0" + /* 2071 */ "wfchxb\t\0" + /* 2079 */ "wfkhxb\t\0" + /* 2087 */ "wftcixb\t\0" + /* 2096 */ "wfixb\t\0" + /* 2103 */ "wfkxb\t\0" + /* 2110 */ "wfmxb\t\0" + /* 2117 */ "vmxb\t\0" + /* 2123 */ "wfminxb\t\0" + /* 2132 */ "wflnxb\t\0" + /* 2140 */ "wfpsoxb\t\0" + /* 2149 */ "wflpxb\t\0" + /* 2157 */ "wfsqxb\t\0" + /* 2165 */ "wfsxb\t\0" + /* 2172 */ "wfmsxb\t\0" + /* 2180 */ "wfnmsxb\t\0" + /* 2189 */ "wfmaxxb\t\0" + /* 2198 */ "vstrczb\t\0" + /* 2207 */ "vfaezb\t\0" + /* 2215 */ "vfeezb\t\0" + /* 2223 */ "vllezb\t\0" + /* 2231 */ "vfenezb\t\0" + /* 2240 */ "vclzb\t\0" + /* 2247 */ "vstrszb\t\0" + /* 2256 */ "vctzb\t\0" + /* 2263 */ "iac\t\0" + /* 2268 */ "kmac\t\0" + /* 2274 */ "sac\t\0" + /* 2279 */ "vac\t\0" + /* 2284 */ "bc\t\0" + /* 2288 */ "vacc\t\0" + /* 2294 */ "vaccc\t\0" + /* 2301 */ "dfltcc\t\0" + /* 2309 */ "vec\t\0" + /* 2314 */ "cfc\t\0" + /* 2319 */ "wfc\t\0" + /* 2324 */ "llgc\t\0" + /* 2330 */ "msgc\t\0" + /* 2336 */ "bic\t\0" + /* 2341 */ "sckc\t\0" + /* 2347 */ "stckc\t\0" + /* 2354 */ "msgrkc\t\0" + /* 2362 */ "msrkc\t\0" + /* 2369 */ "alc\t\0" + /* 2374 */ "clc\t\0" + /* 2379 */ "llc\t\0" + /* 2384 */ "vlc\t\0" + /* 2389 */ "kmc\t\0" + /* 2394 */ "tbeginc\t\0" + /* 2403 */ "vnc\t\0" + /* 2408 */ "loc\t\0" + /* 2413 */ "stoc\t\0" + /* 2419 */ "voc\t\0" + /* 2424 */ "efpc\t\0" + /* 2430 */ "lfpc\t\0" + /* 2436 */ "sfpc\t\0" + /* 2442 */ "stfpc\t\0" + /* 2449 */ "brc\t\0" + /* 2454 */ "vstrc\t\0" + /* 2461 */ "lgsc\t\0" + /* 2467 */ "stgsc\t\0" + /* 2474 */ "msc\t\0" + /* 2479 */ "cmpsc\t\0" + /* 2486 */ "stc\t\0" + /* 2491 */ "mvc\t\0" + /* 2496 */ "svc\t\0" + /* 2501 */ "xc\t\0" + /* 2505 */ "mad\t\0" + /* 2510 */ "cd\t\0" + /* 2514 */ "dd\t\0" + /* 2518 */ "vled\t\0" + /* 2524 */ "pfd\t\0" + /* 2529 */ "vfd\t\0" + /* 2534 */ "vcgd\t\0" + /* 2540 */ "vclgd\t\0" + /* 2547 */ "wflld\t\0" + /* 2554 */ "vsld\t\0" + /* 2560 */ "kimd\t\0" + /* 2566 */ "klmd\t\0" + /* 2572 */ "etnd\t\0" + /* 2578 */ "lpd\t\0" + /* 2583 */ "sqd\t\0" + /* 2588 */ "vflrd\t\0" + /* 2595 */ "wflrd\t\0" + /* 2602 */ "vsrd\t\0" + /* 2608 */ "msd\t\0" + /* 2613 */ "std\t\0" + /* 2618 */ "vcvd\t\0" + /* 2624 */ "lxd\t\0" + /* 2629 */ "mxd\t\0" + /* 2634 */ "vfae\t\0" + /* 2640 */ "lae\t\0" + /* 2645 */ "vmae\t\0" + /* 2651 */ "cibe\t\0" + /* 2657 */ "cgibe\t\0" + /* 2664 */ "clgibe\t\0" + /* 2672 */ "clibe\t\0" + /* 2679 */ "crbe\t\0" + /* 2685 */ "cgrbe\t\0" + /* 2692 */ "clgrbe\t\0" + /* 2700 */ "clrbe\t\0" + /* 2707 */ "rrbe\t\0" + /* 2713 */ "trace\t\0" + /* 2720 */ "vfce\t\0" + /* 2726 */ "loce\t\0" + /* 2732 */ "stoce\t\0" + /* 2739 */ "vlde\t\0" + /* 2745 */ "mde\t\0" + /* 2750 */ "vfee\t\0" + /* 2756 */ "mee\t\0" + /* 2761 */ "locge\t\0" + /* 2768 */ "stocge\t\0" + /* 2776 */ "jge\t\0" + /* 2781 */ "cibhe\t\0" + /* 2788 */ "cgibhe\t\0" + /* 2796 */ "clgibhe\t\0" + /* 2805 */ "clibhe\t\0" + /* 2813 */ "crbhe\t\0" + /* 2820 */ "cgrbhe\t\0" + /* 2828 */ "clgrbhe\t\0" + /* 2837 */ "clrbhe\t\0" + /* 2845 */ "vfche\t\0" + /* 2852 */ "loche\t\0" + /* 2859 */ "stoche\t\0" + /* 2867 */ "locfhe\t\0" + /* 2875 */ "stocfhe\t\0" + /* 2884 */ "locghe\t\0" + /* 2892 */ "stocghe\t\0" + /* 2901 */ "jghe\t\0" + /* 2907 */ "locfhhe\t\0" + /* 2916 */ "stocfhhe\t\0" + /* 2926 */ "bihe\t\0" + /* 2932 */ "lochihe\t\0" + /* 2941 */ "locghihe\t\0" + /* 2951 */ "lochhihe\t\0" + /* 2961 */ "cijhe\t\0" + /* 2968 */ "cgijhe\t\0" + /* 2976 */ "clgijhe\t\0" + /* 2985 */ "clijhe\t\0" + /* 2993 */ "crjhe\t\0" + /* 3000 */ "cgrjhe\t\0" + /* 3008 */ "clgrjhe\t\0" + /* 3017 */ "clrjhe\t\0" + /* 3025 */ "cibnhe\t\0" + /* 3033 */ "cgibnhe\t\0" + /* 3042 */ "clgibnhe\t\0" + /* 3052 */ "clibnhe\t\0" + /* 3061 */ "crbnhe\t\0" + /* 3069 */ "cgrbnhe\t\0" + /* 3078 */ "clgrbnhe\t\0" + /* 3088 */ "clrbnhe\t\0" + /* 3097 */ "locnhe\t\0" + /* 3105 */ "stocnhe\t\0" + /* 3114 */ "locgnhe\t\0" + /* 3123 */ "stocgnhe\t\0" + /* 3133 */ "jgnhe\t\0" + /* 3140 */ "locfhnhe\t\0" + /* 3150 */ "stocfhnhe\t\0" + /* 3161 */ "binhe\t\0" + /* 3168 */ "lochinhe\t\0" + /* 3178 */ "locghinhe\t\0" + /* 3189 */ "lochhinhe\t\0" + /* 3200 */ "cijnhe\t\0" + /* 3208 */ "cgijnhe\t\0" + /* 3217 */ "clgijnhe\t\0" + /* 3227 */ "clijnhe\t\0" + /* 3236 */ "crjnhe\t\0" + /* 3244 */ "cgrjnhe\t\0" + /* 3253 */ "clgrjnhe\t\0" + /* 3263 */ "clrjnhe\t\0" + /* 3272 */ "locrnhe\t\0" + /* 3281 */ "locgrnhe\t\0" + /* 3291 */ "selgrnhe\t\0" + /* 3301 */ "locfhrnhe\t\0" + /* 3312 */ "selfhrnhe\t\0" + /* 3323 */ "selrnhe\t\0" + /* 3332 */ "clgtnhe\t\0" + /* 3341 */ "citnhe\t\0" + /* 3349 */ "clfitnhe\t\0" + /* 3359 */ "cgitnhe\t\0" + /* 3368 */ "clgitnhe\t\0" + /* 3378 */ "cltnhe\t\0" + /* 3386 */ "crtnhe\t\0" + /* 3394 */ "cgrtnhe\t\0" + /* 3403 */ "clgrtnhe\t\0" + /* 3413 */ "clrtnhe\t\0" + /* 3422 */ "locrhe\t\0" + /* 3430 */ "locgrhe\t\0" + /* 3439 */ "selgrhe\t\0" + /* 3448 */ "locfhrhe\t\0" + /* 3458 */ "selfhrhe\t\0" + /* 3468 */ "selrhe\t\0" + /* 3476 */ "clgthe\t\0" + /* 3484 */ "cithe\t\0" + /* 3491 */ "clfithe\t\0" + /* 3500 */ "cgithe\t\0" + /* 3508 */ "clgithe\t\0" + /* 3517 */ "clthe\t\0" + /* 3524 */ "crthe\t\0" + /* 3531 */ "cgrthe\t\0" + /* 3539 */ "clgrthe\t\0" + /* 3548 */ "clrthe\t\0" + /* 3556 */ "bie\t\0" + /* 3561 */ "lochie\t\0" + /* 3569 */ "locghie\t\0" + /* 3578 */ "lochhie\t\0" + /* 3587 */ "sie\t\0" + /* 3592 */ "cije\t\0" + /* 3598 */ "cgije\t\0" + /* 3605 */ "clgije\t\0" + /* 3613 */ "clije\t\0" + /* 3620 */ "crje\t\0" + /* 3626 */ "cgrje\t\0" + /* 3633 */ "clgrje\t\0" + /* 3641 */ "clrje\t\0" + /* 3648 */ "stcke\t\0" + /* 3655 */ "iske\t\0" + /* 3661 */ "sske\t\0" + /* 3667 */ "vmale\t\0" + /* 3674 */ "cible\t\0" + /* 3681 */ "cgible\t\0" + /* 3689 */ "clgible\t\0" + /* 3698 */ "clible\t\0" + /* 3706 */ "crble\t\0" + /* 3713 */ "cgrble\t\0" + /* 3721 */ "clgrble\t\0" + /* 3730 */ "clrble\t\0" + /* 3738 */ "clcle\t\0" + /* 3745 */ "locle\t\0" + /* 3752 */ "stocle\t\0" + /* 3760 */ "mvcle\t\0" + /* 3767 */ "stfle\t\0" + /* 3774 */ "locgle\t\0" + /* 3782 */ "stocgle\t\0" + /* 3791 */ "jgle\t\0" + /* 3797 */ "locfhle\t\0" + /* 3806 */ "stocfhle\t\0" + /* 3816 */ "bile\t\0" + /* 3822 */ "lochile\t\0" + /* 3831 */ "locghile\t\0" + /* 3841 */ "lochhile\t\0" + /* 3851 */ "cijle\t\0" + /* 3858 */ "cgijle\t\0" + /* 3866 */ "clgijle\t\0" + /* 3875 */ "clijle\t\0" + /* 3883 */ "crjle\t\0" + /* 3890 */ "cgrjle\t\0" + /* 3898 */ "clgrjle\t\0" + /* 3907 */ "clrjle\t\0" + /* 3915 */ "vmle\t\0" + /* 3921 */ "cibnle\t\0" + /* 3929 */ "cgibnle\t\0" + /* 3938 */ "clgibnle\t\0" + /* 3948 */ "clibnle\t\0" + /* 3957 */ "crbnle\t\0" + /* 3965 */ "cgrbnle\t\0" + /* 3974 */ "clgrbnle\t\0" + /* 3984 */ "clrbnle\t\0" + /* 3993 */ "locnle\t\0" + /* 4001 */ "stocnle\t\0" + /* 4010 */ "locgnle\t\0" + /* 4019 */ "stocgnle\t\0" + /* 4029 */ "jgnle\t\0" + /* 4036 */ "locfhnle\t\0" + /* 4046 */ "stocfhnle\t\0" + /* 4057 */ "binle\t\0" + /* 4064 */ "lochinle\t\0" + /* 4074 */ "locghinle\t\0" + /* 4085 */ "lochhinle\t\0" + /* 4096 */ "cijnle\t\0" + /* 4104 */ "cgijnle\t\0" + /* 4113 */ "clgijnle\t\0" + /* 4123 */ "clijnle\t\0" + /* 4132 */ "crjnle\t\0" + /* 4140 */ "cgrjnle\t\0" + /* 4149 */ "clgrjnle\t\0" + /* 4159 */ "clrjnle\t\0" + /* 4168 */ "locrnle\t\0" + /* 4177 */ "locgrnle\t\0" + /* 4187 */ "selgrnle\t\0" + /* 4197 */ "locfhrnle\t\0" + /* 4208 */ "selfhrnle\t\0" + /* 4219 */ "selrnle\t\0" + /* 4228 */ "clgtnle\t\0" + /* 4237 */ "citnle\t\0" + /* 4245 */ "clfitnle\t\0" + /* 4255 */ "cgitnle\t\0" + /* 4264 */ "clgitnle\t\0" + /* 4274 */ "cltnle\t\0" + /* 4282 */ "crtnle\t\0" + /* 4290 */ "cgrtnle\t\0" + /* 4299 */ "clgrtnle\t\0" + /* 4309 */ "clrtnle\t\0" + /* 4318 */ "locrle\t\0" + /* 4326 */ "locgrle\t\0" + /* 4335 */ "selgrle\t\0" + /* 4344 */ "locfhrle\t\0" + /* 4354 */ "selfhrle\t\0" + /* 4364 */ "selrle\t\0" + /* 4372 */ "clgtle\t\0" + /* 4380 */ "citle\t\0" + /* 4387 */ "clfitle\t\0" + /* 4396 */ "cgitle\t\0" + /* 4404 */ "clgitle\t\0" + /* 4413 */ "cltle\t\0" + /* 4420 */ "crtle\t\0" + /* 4427 */ "cgrtle\t\0" + /* 4435 */ "clgrtle\t\0" + /* 4444 */ "clrtle\t\0" + /* 4452 */ "bxle\t\0" + /* 4458 */ "brxle\t\0" + /* 4465 */ "vme\t\0" + /* 4470 */ "cibne\t\0" + /* 4477 */ "cgibne\t\0" + /* 4485 */ "clgibne\t\0" + /* 4494 */ "clibne\t\0" + /* 4502 */ "crbne\t\0" + /* 4509 */ "cgrbne\t\0" + /* 4517 */ "clgrbne\t\0" + /* 4526 */ "clrbne\t\0" + /* 4534 */ "locne\t\0" + /* 4541 */ "stocne\t\0" + /* 4549 */ "vfene\t\0" + /* 4556 */ "locgne\t\0" + /* 4564 */ "stocgne\t\0" + /* 4573 */ "jgne\t\0" + /* 4579 */ "locfhne\t\0" + /* 4588 */ "stocfhne\t\0" + /* 4598 */ "bine\t\0" + /* 4604 */ "lochine\t\0" + /* 4613 */ "locghine\t\0" + /* 4623 */ "lochhine\t\0" + /* 4633 */ "cijne\t\0" + /* 4640 */ "cgijne\t\0" + /* 4648 */ "clgijne\t\0" + /* 4657 */ "clijne\t\0" + /* 4665 */ "crjne\t\0" + /* 4672 */ "cgrjne\t\0" + /* 4680 */ "clgrjne\t\0" + /* 4689 */ "clrjne\t\0" + /* 4697 */ "vone\t\0" + /* 4703 */ "locrne\t\0" + /* 4711 */ "locgrne\t\0" + /* 4720 */ "selgrne\t\0" + /* 4729 */ "locfhrne\t\0" + /* 4739 */ "selfhrne\t\0" + /* 4749 */ "selrne\t\0" + /* 4757 */ "clgtne\t\0" + /* 4765 */ "citne\t\0" + /* 4772 */ "clfitne\t\0" + /* 4781 */ "cgitne\t\0" + /* 4789 */ "clgitne\t\0" + /* 4798 */ "cltne\t\0" + /* 4805 */ "crtne\t\0" + /* 4812 */ "cgrtne\t\0" + /* 4820 */ "clgrtne\t\0" + /* 4829 */ "clrtne\t\0" + /* 4837 */ "sqe\t\0" + /* 4842 */ "locre\t\0" + /* 4849 */ "locgre\t\0" + /* 4857 */ "selgre\t\0" + /* 4865 */ "locfhre\t\0" + /* 4874 */ "selfhre\t\0" + /* 4883 */ "selre\t\0" + /* 4890 */ "trtre\t\0" + /* 4897 */ "mse\t\0" + /* 4902 */ "cuse\t\0" + /* 4908 */ "idte\t\0" + /* 4914 */ "crdte\t\0" + /* 4921 */ "clgte\t\0" + /* 4928 */ "cite\t\0" + /* 4934 */ "clfite\t\0" + /* 4942 */ "cgite\t\0" + /* 4949 */ "clgite\t\0" + /* 4957 */ "clte\t\0" + /* 4963 */ "ipte\t\0" + /* 4969 */ "crte\t\0" + /* 4975 */ "cgrte\t\0" + /* 4982 */ "clgrte\t\0" + /* 4990 */ "clrte\t\0" + /* 4997 */ "trte\t\0" + /* 5003 */ "ste\t\0" + /* 5008 */ "lpswe\t\0" + /* 5015 */ "lxe\t\0" + /* 5020 */ "vllebrze\t\0" + /* 5030 */ "vgfmaf\t\0" + /* 5038 */ "vesraf\t\0" + /* 5046 */ "vaf\t\0" + /* 5051 */ "sacf\t\0" + /* 5057 */ "vaccf\t\0" + /* 5064 */ "vecf\t\0" + /* 5070 */ "vlcf\t\0" + /* 5076 */ "vstrcf\t\0" + /* 5084 */ "vfaef\t\0" + /* 5091 */ "vmaef\t\0" + /* 5098 */ "vscef\t\0" + /* 5105 */ "vfeef\t\0" + /* 5112 */ "vgef\t\0" + /* 5118 */ "vmalef\t\0" + /* 5126 */ "vmlef\t\0" + /* 5133 */ "vlef\t\0" + /* 5139 */ "vmef\t\0" + /* 5145 */ "vfenef\t\0" + /* 5153 */ "vstef\t\0" + /* 5160 */ "agf\t\0" + /* 5165 */ "cgf\t\0" + /* 5170 */ "vsegf\t\0" + /* 5177 */ "algf\t\0" + /* 5183 */ "clgf\t\0" + /* 5189 */ "llgf\t\0" + /* 5195 */ "slgf\t\0" + /* 5201 */ "vsumgf\t\0" + /* 5209 */ "llzrgf\t\0" + /* 5217 */ "dsgf\t\0" + /* 5223 */ "msgf\t\0" + /* 5229 */ "ltgf\t\0" + /* 5235 */ "vavgf\t\0" + /* 5242 */ "vlvgf\t\0" + /* 5249 */ "vmahf\t\0" + /* 5256 */ "vchf\t\0" + /* 5262 */ "iihf\t\0" + /* 5268 */ "llihf\t\0" + /* 5275 */ "nihf\t\0" + /* 5281 */ "oihf\t\0" + /* 5287 */ "xihf\t\0" + /* 5293 */ "vmalhf\t\0" + /* 5301 */ "clhf\t\0" + /* 5307 */ "vmlhf\t\0" + /* 5314 */ "vuplhf\t\0" + /* 5322 */ "vmhf\t\0" + /* 5328 */ "vuphf\t\0" + /* 5335 */ "vmrhf\t\0" + /* 5342 */ "vscbif\t\0" + /* 5350 */ "vleif\t\0" + /* 5357 */ "vrepif\t\0" + /* 5365 */ "stckf\t\0" + /* 5372 */ "vpkf\t\0" + /* 5378 */ "vmalf\t\0" + /* 5385 */ "veclf\t\0" + /* 5392 */ "vavglf\t\0" + /* 5400 */ "vchlf\t\0" + /* 5407 */ "iilf\t\0" + /* 5413 */ "llilf\t\0" + /* 5420 */ "nilf\t\0" + /* 5426 */ "oilf\t\0" + /* 5432 */ "xilf\t\0" + /* 5438 */ "vupllf\t\0" + /* 5446 */ "verllf\t\0" + /* 5454 */ "vmlf\t\0" + /* 5460 */ "vmnlf\t\0" + /* 5467 */ "vuplf\t\0" + /* 5474 */ "vmrlf\t\0" + /* 5481 */ "vesrlf\t\0" + /* 5489 */ "veslf\t\0" + /* 5496 */ "vmxlf\t\0" + /* 5503 */ "vllezlf\t\0" + /* 5512 */ "vgfmf\t\0" + /* 5519 */ "pfmf\t\0" + /* 5525 */ "vgmf\t\0" + /* 5531 */ "verimf\t\0" + /* 5539 */ "kmf\t\0" + /* 5544 */ "vcnf\t\0" + /* 5550 */ "vmnf\t\0" + /* 5556 */ "vcrnf\t\0" + /* 5563 */ "vmaof\t\0" + /* 5570 */ "vmalof\t\0" + /* 5578 */ "vmlof\t\0" + /* 5585 */ "vmof\t\0" + /* 5591 */ "vlrepf\t\0" + /* 5599 */ "vlbrrepf\t\0" + /* 5609 */ "vrepf\t\0" + /* 5616 */ "vlpf\t\0" + /* 5622 */ "vceqf\t\0" + /* 5629 */ "vsumqf\t\0" + /* 5637 */ "vlebrf\t\0" + /* 5645 */ "vstebrf\t\0" + /* 5654 */ "vlbrf\t\0" + /* 5661 */ "vstbrf\t\0" + /* 5669 */ "vlerf\t\0" + /* 5676 */ "vsterf\t\0" + /* 5684 */ "vistrf\t\0" + /* 5692 */ "lzrf\t\0" + /* 5698 */ "vpksf\t\0" + /* 5705 */ "vpklsf\t\0" + /* 5713 */ "vstrsf\t\0" + /* 5721 */ "vsf\t\0" + /* 5726 */ "vpopctf\t\0" + /* 5735 */ "ptf\t\0" + /* 5740 */ "cuutf\t\0" + /* 5747 */ "vesravf\t\0" + /* 5756 */ "vlgvf\t\0" + /* 5763 */ "verllvf\t\0" + /* 5772 */ "vesrlvf\t\0" + /* 5781 */ "veslvf\t\0" + /* 5789 */ "vmxf\t\0" + /* 5795 */ "vstrczf\t\0" + /* 5804 */ "vfaezf\t\0" + /* 5812 */ "vfeezf\t\0" + /* 5820 */ "vllezf\t\0" + /* 5828 */ "vfenezf\t\0" + /* 5837 */ "vclzf\t\0" + /* 5844 */ "vllebrzf\t\0" + /* 5854 */ "vstrszf\t\0" + /* 5863 */ "vctzf\t\0" + /* 5870 */ "laag\t\0" + /* 5876 */ "ecag\t\0" + /* 5882 */ "diag\t\0" + /* 5888 */ "slag\t\0" + /* 5894 */ "vgfmag\t\0" + /* 5902 */ "lrag\t\0" + /* 5908 */ "vesrag\t\0" + /* 5916 */ "strag\t\0" + /* 5923 */ "lurag\t\0" + /* 5930 */ "vag\t\0" + /* 5935 */ "slbg\t\0" + /* 5941 */ "risbg\t\0" + /* 5948 */ "rnsbg\t\0" + /* 5955 */ "rosbg\t\0" + /* 5962 */ "rxsbg\t\0" + /* 5969 */ "vcvbg\t\0" + /* 5976 */ "tracg\t\0" + /* 5983 */ "vaccg\t\0" + /* 5990 */ "vecg\t\0" + /* 5996 */ "alcg\t\0" + /* 6002 */ "vlcg\t\0" + /* 6008 */ "locg\t\0" + /* 6014 */ "stocg\t\0" + /* 6021 */ "vcdg\t\0" + /* 6027 */ "lpdg\t\0" + /* 6033 */ "vcvdg\t\0" + /* 6040 */ "vsceg\t\0" + /* 6047 */ "vgeg\t\0" + /* 6053 */ "vleg\t\0" + /* 6059 */ "bxleg\t\0" + /* 6066 */ "ereg\t\0" + /* 6072 */ "vseg\t\0" + /* 6078 */ "vsteg\t\0" + /* 6085 */ "eregg\t\0" + /* 6092 */ "lgg\t\0" + /* 6097 */ "vavgg\t\0" + /* 6104 */ "vlvgg\t\0" + /* 6111 */ "risbhg\t\0" + /* 6119 */ "vchg\t\0" + /* 6125 */ "vmrhg\t\0" + /* 6132 */ "bxhg\t\0" + /* 6138 */ "brxhg\t\0" + /* 6145 */ "vscbig\t\0" + /* 6153 */ "vleig\t\0" + /* 6160 */ "vrepig\t\0" + /* 6168 */ "jg\t\0" + /* 6172 */ "vpkg\t\0" + /* 6178 */ "laalg\t\0" + /* 6185 */ "risblg\t\0" + /* 6193 */ "veclg\t\0" + /* 6200 */ "vcdlg\t\0" + /* 6207 */ "vavglg\t\0" + /* 6215 */ "vchlg\t\0" + /* 6222 */ "verllg\t\0" + /* 6230 */ "sllg\t\0" + /* 6236 */ "mlg\t\0" + /* 6241 */ "vmnlg\t\0" + /* 6248 */ "vmrlg\t\0" + /* 6255 */ "vesrlg\t\0" + /* 6263 */ "veslg\t\0" + /* 6270 */ "vmslg\t\0" + /* 6277 */ "lctlg\t\0" + /* 6284 */ "vmxlg\t\0" + /* 6291 */ "brxlg\t\0" + /* 6298 */ "vgfmg\t\0" + /* 6305 */ "vgmg\t\0" + /* 6311 */ "verimg\t\0" + /* 6319 */ "lmg\t\0" + /* 6324 */ "stmg\t\0" + /* 6330 */ "vsumg\t\0" + /* 6337 */ "lang\t\0" + /* 6343 */ "vmng\t\0" + /* 6349 */ "laog\t\0" + /* 6355 */ "vlrepg\t\0" + /* 6363 */ "vlbrrepg\t\0" + /* 6373 */ "vrepg\t\0" + /* 6380 */ "vlpg\t\0" + /* 6386 */ "cspg\t\0" + /* 6392 */ "mvpg\t\0" + /* 6398 */ "vceqg\t\0" + /* 6405 */ "vsumqg\t\0" + /* 6413 */ "vlebrg\t\0" + /* 6421 */ "vstebrg\t\0" + /* 6430 */ "vlbrg\t\0" + /* 6437 */ "vstbrg\t\0" + /* 6445 */ "vlerg\t\0" + /* 6452 */ "vsterg\t\0" + /* 6460 */ "sturg\t\0" + /* 6467 */ "lzrg\t\0" + /* 6473 */ "bsg\t\0" + /* 6478 */ "csg\t\0" + /* 6483 */ "cdsg\t\0" + /* 6489 */ "llgfsg\t\0" + /* 6497 */ "vpksg\t\0" + /* 6504 */ "vpklsg\t\0" + /* 6512 */ "msg\t\0" + /* 6517 */ "vsg\t\0" + /* 6522 */ "bctg\t\0" + /* 6528 */ "ectg\t\0" + /* 6534 */ "vpopctg\t\0" + /* 6543 */ "brctg\t\0" + /* 6550 */ "stctg\t\0" + /* 6557 */ "ltg\t\0" + /* 6562 */ "ntstg\t\0" + /* 6569 */ "vesravg\t\0" + /* 6578 */ "vavg\t\0" + /* 6584 */ "vlgvg\t\0" + /* 6591 */ "verllvg\t\0" + /* 6600 */ "vesrlvg\t\0" + /* 6609 */ "veslvg\t\0" + /* 6617 */ "vlvg\t\0" + /* 6623 */ "lrvg\t\0" + /* 6629 */ "strvg\t\0" + /* 6636 */ "laxg\t\0" + /* 6642 */ "vmxg\t\0" + /* 6648 */ "vllezg\t\0" + /* 6656 */ "vclzg\t\0" + /* 6663 */ "vllebrzg\t\0" + /* 6673 */ "vctzg\t\0" + /* 6680 */ "vgfmah\t\0" + /* 6688 */ "vmah\t\0" + /* 6694 */ "vesrah\t\0" + /* 6702 */ "vah\t\0" + /* 6707 */ "cibh\t\0" + /* 6713 */ "cgibh\t\0" + /* 6720 */ "clgibh\t\0" + /* 6728 */ "clibh\t\0" + /* 6735 */ "lbh\t\0" + /* 6740 */ "crbh\t\0" + /* 6746 */ "cgrbh\t\0" + /* 6753 */ "clgrbh\t\0" + /* 6761 */ "clrbh\t\0" + /* 6768 */ "vacch\t\0" + /* 6775 */ "vech\t\0" + /* 6781 */ "vfch\t\0" + /* 6787 */ "llch\t\0" + /* 6793 */ "vlch\t\0" + /* 6799 */ "loch\t\0" + /* 6805 */ "stoch\t\0" + /* 6812 */ "vstrch\t\0" + /* 6820 */ "msch\t\0" + /* 6826 */ "ssch\t\0" + /* 6832 */ "stsch\t\0" + /* 6839 */ "stch\t\0" + /* 6845 */ "vch\t\0" + /* 6850 */ "vfaeh\t\0" + /* 6857 */ "vmaeh\t\0" + /* 6864 */ "vfeeh\t\0" + /* 6871 */ "vmaleh\t\0" + /* 6879 */ "vmleh\t\0" + /* 6886 */ "vleh\t\0" + /* 6892 */ "vmeh\t\0" + /* 6898 */ "vfeneh\t\0" + /* 6906 */ "vsteh\t\0" + /* 6913 */ "locfh\t\0" + /* 6920 */ "stocfh\t\0" + /* 6928 */ "lfh\t\0" + /* 6933 */ "stfh\t\0" + /* 6939 */ "agh\t\0" + /* 6944 */ "locgh\t\0" + /* 6951 */ "stocgh\t\0" + /* 6959 */ "vsegh\t\0" + /* 6966 */ "jgh\t\0" + /* 6971 */ "llgh\t\0" + /* 6977 */ "vsumgh\t\0" + /* 6985 */ "sgh\t\0" + /* 6990 */ "vavgh\t\0" + /* 6997 */ "vlvgh\t\0" + /* 7004 */ "vmahh\t\0" + /* 7011 */ "vchh\t\0" + /* 7017 */ "locfhh\t\0" + /* 7025 */ "stocfhh\t\0" + /* 7034 */ "iihh\t\0" + /* 7040 */ "llihh\t\0" + /* 7047 */ "nihh\t\0" + /* 7053 */ "oihh\t\0" + /* 7059 */ "vmalhh\t\0" + /* 7067 */ "llhh\t\0" + /* 7073 */ "vmlhh\t\0" + /* 7080 */ "vuplhh\t\0" + /* 7088 */ "tmhh\t\0" + /* 7094 */ "vmhh\t\0" + /* 7100 */ "vuphh\t\0" + /* 7107 */ "vmrhh\t\0" + /* 7114 */ "sthh\t\0" + /* 7120 */ "aih\t\0" + /* 7125 */ "vscbih\t\0" + /* 7133 */ "cih\t\0" + /* 7138 */ "vleih\t\0" + /* 7145 */ "lochih\t\0" + /* 7153 */ "locghih\t\0" + /* 7162 */ "lochhih\t\0" + /* 7171 */ "clih\t\0" + /* 7177 */ "vrepih\t\0" + /* 7185 */ "alsih\t\0" + /* 7192 */ "cijh\t\0" + /* 7198 */ "cgijh\t\0" + /* 7205 */ "clgijh\t\0" + /* 7213 */ "clijh\t\0" + /* 7220 */ "crjh\t\0" + /* 7226 */ "cgrjh\t\0" + /* 7233 */ "clgrjh\t\0" + /* 7241 */ "clrjh\t\0" + /* 7248 */ "vpkh\t\0" + /* 7254 */ "vmalh\t\0" + /* 7261 */ "ciblh\t\0" + /* 7268 */ "cgiblh\t\0" + /* 7276 */ "clgiblh\t\0" + /* 7285 */ "cliblh\t\0" + /* 7293 */ "crblh\t\0" + /* 7300 */ "cgrblh\t\0" + /* 7308 */ "clgrblh\t\0" + /* 7317 */ "clrblh\t\0" + /* 7325 */ "veclh\t\0" + /* 7332 */ "loclh\t\0" + /* 7339 */ "stoclh\t\0" + /* 7347 */ "locglh\t\0" + /* 7355 */ "stocglh\t\0" + /* 7364 */ "jglh\t\0" + /* 7370 */ "vavglh\t\0" + /* 7378 */ "vchlh\t\0" + /* 7385 */ "locfhlh\t\0" + /* 7394 */ "stocfhlh\t\0" + /* 7404 */ "bilh\t\0" + /* 7410 */ "lochilh\t\0" + /* 7419 */ "locghilh\t\0" + /* 7429 */ "lochhilh\t\0" + /* 7439 */ "iilh\t\0" + /* 7445 */ "llilh\t\0" + /* 7452 */ "nilh\t\0" + /* 7458 */ "oilh\t\0" + /* 7464 */ "cijlh\t\0" + /* 7471 */ "cgijlh\t\0" + /* 7479 */ "clgijlh\t\0" + /* 7488 */ "clijlh\t\0" + /* 7496 */ "crjlh\t\0" + /* 7503 */ "cgrjlh\t\0" + /* 7511 */ "clgrjlh\t\0" + /* 7520 */ "clrjlh\t\0" + /* 7528 */ "vupllh\t\0" + /* 7536 */ "verllh\t\0" + /* 7544 */ "tmlh\t\0" + /* 7550 */ "vmlh\t\0" + /* 7556 */ "cibnlh\t\0" + /* 7564 */ "cgibnlh\t\0" + /* 7573 */ "clgibnlh\t\0" + /* 7583 */ "clibnlh\t\0" + /* 7592 */ "crbnlh\t\0" + /* 7600 */ "cgrbnlh\t\0" + /* 7609 */ "clgrbnlh\t\0" + /* 7619 */ "clrbnlh\t\0" + /* 7628 */ "locnlh\t\0" + /* 7636 */ "stocnlh\t\0" + /* 7645 */ "locgnlh\t\0" + /* 7654 */ "stocgnlh\t\0" + /* 7664 */ "jgnlh\t\0" + /* 7671 */ "locfhnlh\t\0" + /* 7681 */ "stocfhnlh\t\0" + /* 7692 */ "binlh\t\0" + /* 7699 */ "lochinlh\t\0" + /* 7709 */ "locghinlh\t\0" + /* 7720 */ "lochhinlh\t\0" + /* 7731 */ "cijnlh\t\0" + /* 7739 */ "cgijnlh\t\0" + /* 7748 */ "clgijnlh\t\0" + /* 7758 */ "clijnlh\t\0" + /* 7767 */ "crjnlh\t\0" + /* 7775 */ "cgrjnlh\t\0" + /* 7784 */ "clgrjnlh\t\0" + /* 7794 */ "clrjnlh\t\0" + /* 7803 */ "vmnlh\t\0" + /* 7810 */ "locrnlh\t\0" + /* 7819 */ "locgrnlh\t\0" + /* 7829 */ "selgrnlh\t\0" + /* 7839 */ "locfhrnlh\t\0" + /* 7850 */ "selfhrnlh\t\0" + /* 7861 */ "selrnlh\t\0" + /* 7870 */ "clgtnlh\t\0" + /* 7879 */ "citnlh\t\0" + /* 7887 */ "clfitnlh\t\0" + /* 7897 */ "cgitnlh\t\0" + /* 7906 */ "clgitnlh\t\0" + /* 7916 */ "cltnlh\t\0" + /* 7924 */ "crtnlh\t\0" + /* 7932 */ "cgrtnlh\t\0" + /* 7941 */ "clgrtnlh\t\0" + /* 7951 */ "clrtnlh\t\0" + /* 7960 */ "vuplh\t\0" + /* 7967 */ "locrlh\t\0" + /* 7975 */ "locgrlh\t\0" + /* 7984 */ "selgrlh\t\0" + /* 7993 */ "locfhrlh\t\0" + /* 8003 */ "selfhrlh\t\0" + /* 8013 */ "selrlh\t\0" + /* 8021 */ "vmrlh\t\0" + /* 8028 */ "vesrlh\t\0" + /* 8036 */ "veslh\t\0" + /* 8043 */ "clgtlh\t\0" + /* 8051 */ "citlh\t\0" + /* 8058 */ "clfitlh\t\0" + /* 8067 */ "cgitlh\t\0" + /* 8075 */ "clgitlh\t\0" + /* 8084 */ "cltlh\t\0" + /* 8091 */ "crtlh\t\0" + /* 8098 */ "cgrtlh\t\0" + /* 8106 */ "clgrtlh\t\0" + /* 8115 */ "clrtlh\t\0" + /* 8123 */ "vmxlh\t\0" + /* 8130 */ "icmh\t\0" + /* 8136 */ "stcmh\t\0" + /* 8143 */ "vgfmh\t\0" + /* 8150 */ "vgmh\t\0" + /* 8156 */ "verimh\t\0" + /* 8164 */ "clmh\t\0" + /* 8170 */ "stmh\t\0" + /* 8176 */ "vsumh\t\0" + /* 8183 */ "vmh\t\0" + /* 8188 */ "cibnh\t\0" + /* 8195 */ "cgibnh\t\0" + /* 8203 */ "clgibnh\t\0" + /* 8212 */ "clibnh\t\0" + /* 8220 */ "crbnh\t\0" + /* 8227 */ "cgrbnh\t\0" + /* 8235 */ "clgrbnh\t\0" + /* 8244 */ "clrbnh\t\0" + /* 8252 */ "locnh\t\0" + /* 8259 */ "stocnh\t\0" + /* 8267 */ "vclfnh\t\0" + /* 8275 */ "locgnh\t\0" + /* 8283 */ "stocgnh\t\0" + /* 8292 */ "jgnh\t\0" + /* 8298 */ "locfhnh\t\0" + /* 8307 */ "stocfhnh\t\0" + /* 8317 */ "binh\t\0" + /* 8323 */ "lochinh\t\0" + /* 8332 */ "locghinh\t\0" + /* 8342 */ "lochhinh\t\0" + /* 8352 */ "cijnh\t\0" + /* 8359 */ "cgijnh\t\0" + /* 8367 */ "clgijnh\t\0" + /* 8376 */ "clijnh\t\0" + /* 8384 */ "crjnh\t\0" + /* 8391 */ "cgrjnh\t\0" + /* 8399 */ "clgrjnh\t\0" + /* 8408 */ "clrjnh\t\0" + /* 8416 */ "vmnh\t\0" + /* 8422 */ "locrnh\t\0" + /* 8430 */ "locgrnh\t\0" + /* 8439 */ "selgrnh\t\0" + /* 8448 */ "locfhrnh\t\0" + /* 8458 */ "selfhrnh\t\0" + /* 8468 */ "selrnh\t\0" + /* 8476 */ "clgtnh\t\0" + /* 8484 */ "citnh\t\0" + /* 8491 */ "clfitnh\t\0" + /* 8500 */ "cgitnh\t\0" + /* 8508 */ "clgitnh\t\0" + /* 8517 */ "cltnh\t\0" + /* 8524 */ "crtnh\t\0" + /* 8531 */ "cgrtnh\t\0" + /* 8539 */ "clgrtnh\t\0" + /* 8548 */ "clrtnh\t\0" + /* 8556 */ "vmaoh\t\0" + /* 8563 */ "vmaloh\t\0" + /* 8571 */ "vmloh\t\0" + /* 8578 */ "vmoh\t\0" + /* 8584 */ "vlreph\t\0" + /* 8592 */ "vlbrreph\t\0" + /* 8602 */ "vreph\t\0" + /* 8609 */ "vlph\t\0" + /* 8615 */ "vcsph\t\0" + /* 8622 */ "vuph\t\0" + /* 8628 */ "vceqh\t\0" + /* 8635 */ "vlebrh\t\0" + /* 8643 */ "vstebrh\t\0" + /* 8652 */ "vlbrh\t\0" + /* 8659 */ "vstbrh\t\0" + /* 8667 */ "locrh\t\0" + /* 8674 */ "vlerh\t\0" + /* 8681 */ "vsterh\t\0" + /* 8689 */ "locgrh\t\0" + /* 8697 */ "selgrh\t\0" + /* 8705 */ "locfhrh\t\0" + /* 8714 */ "selfhrh\t\0" + /* 8723 */ "selrh\t\0" + /* 8730 */ "vmrh\t\0" + /* 8736 */ "vistrh\t\0" + /* 8744 */ "vpksh\t\0" + /* 8751 */ "vpklsh\t\0" + /* 8759 */ "vstrsh\t\0" + /* 8767 */ "vsh\t\0" + /* 8772 */ "vpopcth\t\0" + /* 8781 */ "brcth\t\0" + /* 8788 */ "clgth\t\0" + /* 8795 */ "cith\t\0" + /* 8801 */ "clfith\t\0" + /* 8809 */ "cgith\t\0" + /* 8816 */ "clgith\t\0" + /* 8824 */ "clth\t\0" + /* 8830 */ "crth\t\0" + /* 8836 */ "cgrth\t\0" + /* 8843 */ "clgrth\t\0" + /* 8851 */ "clrth\t\0" + /* 8858 */ "sth\t\0" + /* 8863 */ "vesravh\t\0" + /* 8872 */ "vlgvh\t\0" + /* 8879 */ "verllvh\t\0" + /* 8888 */ "vesrlvh\t\0" + /* 8897 */ "veslvh\t\0" + /* 8905 */ "lrvh\t\0" + /* 8911 */ "strvh\t\0" + /* 8918 */ "bxh\t\0" + /* 8923 */ "vmxh\t\0" + /* 8929 */ "brxh\t\0" + /* 8935 */ "mayh\t\0" + /* 8941 */ "myh\t\0" + /* 8946 */ "vstrczh\t\0" + /* 8955 */ "vfaezh\t\0" + /* 8963 */ "vfeezh\t\0" + /* 8971 */ "vllezh\t\0" + /* 8979 */ "vfenezh\t\0" + /* 8988 */ "vupkzh\t\0" + /* 8996 */ "vclzh\t\0" + /* 9003 */ "vllebrzh\t\0" + /* 9013 */ "vstrszh\t\0" + /* 9022 */ "vctzh\t\0" + /* 9029 */ "niai\t\0" + /* 9035 */ "vsbcbi\t\0" + /* 9043 */ "vscbi\t\0" + /* 9050 */ "vsbi\t\0" + /* 9056 */ "qpaci\t\0" + /* 9063 */ "vftci\t\0" + /* 9070 */ "vpdi\t\0" + /* 9076 */ "afi\t\0" + /* 9081 */ "cfi\t\0" + /* 9086 */ "agfi\t\0" + /* 9092 */ "cgfi\t\0" + /* 9098 */ "algfi\t\0" + /* 9105 */ "clgfi\t\0" + /* 9112 */ "slgfi\t\0" + /* 9119 */ "msgfi\t\0" + /* 9126 */ "alfi\t\0" + /* 9132 */ "clfi\t\0" + /* 9138 */ "slfi\t\0" + /* 9144 */ "msfi\t\0" + /* 9150 */ "vfi\t\0" + /* 9155 */ "ahi\t\0" + /* 9160 */ "lochi\t\0" + /* 9167 */ "aghi\t\0" + /* 9173 */ "locghi\t\0" + /* 9181 */ "lghi\t\0" + /* 9187 */ "mghi\t\0" + /* 9193 */ "mvghi\t\0" + /* 9200 */ "lochhi\t\0" + /* 9208 */ "mvhhi\t\0" + /* 9215 */ "lhi\t\0" + /* 9220 */ "mhi\t\0" + /* 9225 */ "mvhi\t\0" + /* 9231 */ "cli\t\0" + /* 9236 */ "ni\t\0" + /* 9240 */ "oi\t\0" + /* 9244 */ "vrepi\t\0" + /* 9251 */ "tpi\t\0" + /* 9256 */ "qctri\t\0" + /* 9263 */ "asi\t\0" + /* 9268 */ "agsi\t\0" + /* 9274 */ "algsi\t\0" + /* 9281 */ "chsi\t\0" + /* 9287 */ "clfhsi\t\0" + /* 9295 */ "cghsi\t\0" + /* 9302 */ "clghsi\t\0" + /* 9310 */ "chhsi\t\0" + /* 9317 */ "clhhsi\t\0" + /* 9325 */ "alsi\t\0" + /* 9331 */ "qsi\t\0" + /* 9336 */ "stsi\t\0" + /* 9342 */ "pti\t\0" + /* 9347 */ "mvi\t\0" + /* 9352 */ "xi\t\0" + /* 9356 */ "cij\t\0" + /* 9361 */ "cgij\t\0" + /* 9367 */ "clgij\t\0" + /* 9374 */ "clij\t\0" + /* 9380 */ "crj\t\0" + /* 9385 */ "cgrj\t\0" + /* 9391 */ "clgrj\t\0" + /* 9398 */ "clrj\t\0" + /* 9404 */ "slak\t\0" + /* 9410 */ "srak\t\0" + /* 9416 */ "pack\t\0" + /* 9422 */ "sck\t\0" + /* 9427 */ "stck\t\0" + /* 9433 */ "mvck\t\0" + /* 9439 */ "mvcdk\t\0" + /* 9446 */ "wfk\t\0" + /* 9451 */ "ahik\t\0" + /* 9457 */ "aghik\t\0" + /* 9464 */ "alghsik\t\0" + /* 9473 */ "alhsik\t\0" + /* 9481 */ "sllk\t\0" + /* 9487 */ "srlk\t\0" + /* 9493 */ "edmk\t\0" + /* 9499 */ "unpk\t\0" + /* 9505 */ "vpk\t\0" + /* 9510 */ "ark\t\0" + /* 9515 */ "ncrk\t\0" + /* 9521 */ "ocrk\t\0" + /* 9527 */ "agrk\t\0" + /* 9533 */ "ncgrk\t\0" + /* 9540 */ "ocgrk\t\0" + /* 9547 */ "algrk\t\0" + /* 9554 */ "slgrk\t\0" + /* 9561 */ "mgrk\t\0" + /* 9567 */ "nngrk\t\0" + /* 9574 */ "nogrk\t\0" + /* 9581 */ "sgrk\t\0" + /* 9587 */ "nxgrk\t\0" + /* 9594 */ "alrk\t\0" + /* 9600 */ "slrk\t\0" + /* 9606 */ "nnrk\t\0" + /* 9612 */ "nork\t\0" + /* 9618 */ "srk\t\0" + /* 9623 */ "nxrk\t\0" + /* 9629 */ "mvcsk\t\0" + /* 9636 */ "ivsk\t\0" + /* 9642 */ "laal\t\0" + /* 9648 */ "bal\t\0" + /* 9653 */ "vmal\t\0" + /* 9659 */ "cibl\t\0" + /* 9665 */ "cgibl\t\0" + /* 9672 */ "clgibl\t\0" + /* 9680 */ "clibl\t\0" + /* 9687 */ "crbl\t\0" + /* 9693 */ "cgrbl\t\0" + /* 9700 */ "clgrbl\t\0" + /* 9708 */ "clrbl\t\0" + /* 9715 */ "vecl\t\0" + /* 9721 */ "clcl\t\0" + /* 9727 */ "locl\t\0" + /* 9733 */ "stocl\t\0" + /* 9740 */ "brcl\t\0" + /* 9746 */ "mvcl\t\0" + /* 9752 */ "sldl\t\0" + /* 9758 */ "srdl\t\0" + /* 9764 */ "vsel\t\0" + /* 9770 */ "stfl\t\0" + /* 9776 */ "locgl\t\0" + /* 9783 */ "stocgl\t\0" + /* 9791 */ "jgl\t\0" + /* 9796 */ "vavgl\t\0" + /* 9803 */ "vchl\t\0" + /* 9809 */ "locfhl\t\0" + /* 9817 */ "stocfhl\t\0" + /* 9826 */ "iihl\t\0" + /* 9832 */ "llihl\t\0" + /* 9839 */ "nihl\t\0" + /* 9845 */ "oihl\t\0" + /* 9851 */ "tmhl\t\0" + /* 9857 */ "bil\t\0" + /* 9862 */ "lochil\t\0" + /* 9870 */ "locghil\t\0" + /* 9879 */ "lochhil\t\0" + /* 9888 */ "cijl\t\0" + /* 9894 */ "cgijl\t\0" + /* 9901 */ "clgijl\t\0" + /* 9909 */ "clijl\t\0" + /* 9916 */ "crjl\t\0" + /* 9922 */ "cgrjl\t\0" + /* 9929 */ "clgrjl\t\0" + /* 9937 */ "clrjl\t\0" + /* 9944 */ "vfll\t\0" + /* 9950 */ "iill\t\0" + /* 9956 */ "llill\t\0" + /* 9963 */ "nill\t\0" + /* 9969 */ "oill\t\0" + /* 9975 */ "tmll\t\0" + /* 9981 */ "vupll\t\0" + /* 9988 */ "verll\t\0" + /* 9995 */ "sll\t\0" + /* 10000 */ "vll\t\0" + /* 10005 */ "vml\t\0" + /* 10010 */ "cibnl\t\0" + /* 10017 */ "cgibnl\t\0" + /* 10025 */ "clgibnl\t\0" + /* 10034 */ "clibnl\t\0" + /* 10042 */ "crbnl\t\0" + /* 10049 */ "cgrbnl\t\0" + /* 10057 */ "clgrbnl\t\0" + /* 10066 */ "clrbnl\t\0" + /* 10074 */ "locnl\t\0" + /* 10081 */ "stocnl\t\0" + /* 10089 */ "vclfnl\t\0" + /* 10097 */ "locgnl\t\0" + /* 10105 */ "stocgnl\t\0" + /* 10114 */ "jgnl\t\0" + /* 10120 */ "locfhnl\t\0" + /* 10129 */ "stocfhnl\t\0" + /* 10139 */ "binl\t\0" + /* 10145 */ "lochinl\t\0" + /* 10154 */ "locghinl\t\0" + /* 10164 */ "lochhinl\t\0" + /* 10174 */ "cijnl\t\0" + /* 10181 */ "cgijnl\t\0" + /* 10189 */ "clgijnl\t\0" + /* 10198 */ "clijnl\t\0" + /* 10206 */ "crjnl\t\0" + /* 10213 */ "cgrjnl\t\0" + /* 10221 */ "clgrjnl\t\0" + /* 10230 */ "clrjnl\t\0" + /* 10238 */ "vmnl\t\0" + /* 10244 */ "locrnl\t\0" + /* 10252 */ "locgrnl\t\0" + /* 10261 */ "selgrnl\t\0" + /* 10270 */ "locfhrnl\t\0" + /* 10280 */ "selfhrnl\t\0" + /* 10290 */ "selrnl\t\0" + /* 10298 */ "clgtnl\t\0" + /* 10306 */ "citnl\t\0" + /* 10313 */ "clfitnl\t\0" + /* 10322 */ "cgitnl\t\0" + /* 10330 */ "clgitnl\t\0" + /* 10339 */ "cltnl\t\0" + /* 10346 */ "crtnl\t\0" + /* 10353 */ "cgrtnl\t\0" + /* 10361 */ "clgrtnl\t\0" + /* 10370 */ "clrtnl\t\0" + /* 10378 */ "vcfpl\t\0" + /* 10385 */ "vupl\t\0" + /* 10391 */ "larl\t\0" + /* 10397 */ "locrl\t\0" + /* 10404 */ "mvcrl\t\0" + /* 10411 */ "pfdrl\t\0" + /* 10418 */ "cgfrl\t\0" + /* 10425 */ "clgfrl\t\0" + /* 10433 */ "llgfrl\t\0" + /* 10441 */ "locgrl\t\0" + /* 10449 */ "clgrl\t\0" + /* 10456 */ "selgrl\t\0" + /* 10464 */ "stgrl\t\0" + /* 10471 */ "chrl\t\0" + /* 10477 */ "locfhrl\t\0" + /* 10486 */ "selfhrl\t\0" + /* 10495 */ "cghrl\t\0" + /* 10502 */ "clghrl\t\0" + /* 10510 */ "llghrl\t\0" + /* 10518 */ "clhrl\t\0" + /* 10525 */ "llhrl\t\0" + /* 10532 */ "sthrl\t\0" + /* 10539 */ "clrl\t\0" + /* 10545 */ "selrl\t\0" + /* 10552 */ "vlrl\t\0" + /* 10558 */ "vmrl\t\0" + /* 10564 */ "vesrl\t\0" + /* 10571 */ "vsrl\t\0" + /* 10577 */ "vstrl\t\0" + /* 10584 */ "exrl\t\0" + /* 10590 */ "brasl\t\0" + /* 10597 */ "vesl\t\0" + /* 10603 */ "vmsl\t\0" + /* 10609 */ "vsl\t\0" + /* 10614 */ "lcctl\t\0" + /* 10621 */ "lctl\t\0" + /* 10627 */ "lpctl\t\0" + /* 10634 */ "lsctl\t\0" + /* 10641 */ "stctl\t\0" + /* 10648 */ "clgtl\t\0" + /* 10655 */ "citl\t\0" + /* 10661 */ "clfitl\t\0" + /* 10669 */ "cgitl\t\0" + /* 10676 */ "clgitl\t\0" + /* 10684 */ "cltl\t\0" + /* 10690 */ "crtl\t\0" + /* 10696 */ "cgrtl\t\0" + /* 10703 */ "clgrtl\t\0" + /* 10711 */ "clrtl\t\0" + /* 10718 */ "sortl\t\0" + /* 10725 */ "vstl\t\0" + /* 10731 */ "vl\t\0" + /* 10735 */ "vmxl\t\0" + /* 10741 */ "mayl\t\0" + /* 10747 */ "myl\t\0" + /* 10752 */ "vupkzl\t\0" + /* 10760 */ "lam\t\0" + /* 10765 */ "stam\t\0" + /* 10771 */ "vgbm\t\0" + /* 10777 */ "irbm\t\0" + /* 10783 */ "rrbm\t\0" + /* 10789 */ "icm\t\0" + /* 10794 */ "locm\t\0" + /* 10800 */ "stocm\t\0" + /* 10807 */ "stcm\t\0" + /* 10813 */ "vgfm\t\0" + /* 10819 */ "vfm\t\0" + /* 10824 */ "locgm\t\0" + /* 10831 */ "stocgm\t\0" + /* 10839 */ "jgm\t\0" + /* 10844 */ "vgm\t\0" + /* 10849 */ "locfhm\t\0" + /* 10857 */ "stocfhm\t\0" + /* 10866 */ "bim\t\0" + /* 10871 */ "lochim\t\0" + /* 10879 */ "locghim\t\0" + /* 10888 */ "lochhim\t\0" + /* 10897 */ "verim\t\0" + /* 10904 */ "jm\t\0" + /* 10908 */ "km\t\0" + /* 10912 */ "clm\t\0" + /* 10917 */ "vlm\t\0" + /* 10922 */ "bnm\t\0" + /* 10927 */ "locnm\t\0" + /* 10934 */ "stocnm\t\0" + /* 10942 */ "locgnm\t\0" + /* 10950 */ "stocgnm\t\0" + /* 10959 */ "jgnm\t\0" + /* 10965 */ "locfhnm\t\0" + /* 10974 */ "stocfhnm\t\0" + /* 10984 */ "binm\t\0" + /* 10990 */ "lochinm\t\0" + /* 10999 */ "locghinm\t\0" + /* 11009 */ "lochhinm\t\0" + /* 11019 */ "jnm\t\0" + /* 11024 */ "locrnm\t\0" + /* 11032 */ "locgrnm\t\0" + /* 11041 */ "selgrnm\t\0" + /* 11050 */ "locfhrnm\t\0" + /* 11060 */ "selfhrnm\t\0" + /* 11070 */ "selrnm\t\0" + /* 11078 */ "srnm\t\0" + /* 11084 */ "ipm\t\0" + /* 11089 */ "spm\t\0" + /* 11094 */ "locrm\t\0" + /* 11101 */ "vbperm\t\0" + /* 11109 */ "vperm\t\0" + /* 11116 */ "locgrm\t\0" + /* 11124 */ "selgrm\t\0" + /* 11132 */ "locfhrm\t\0" + /* 11141 */ "selfhrm\t\0" + /* 11150 */ "selrm\t\0" + /* 11157 */ "bsm\t\0" + /* 11162 */ "vcksm\t\0" + /* 11169 */ "stnsm\t\0" + /* 11176 */ "stosm\t\0" + /* 11183 */ "bassm\t\0" + /* 11190 */ "vstm\t\0" + /* 11196 */ "vtm\t\0" + /* 11201 */ "vsum\t\0" + /* 11207 */ "lan\t\0" + /* 11212 */ "vcfn\t\0" + /* 11218 */ "risbgn\t\0" + /* 11226 */ "alsihn\t\0" + /* 11234 */ "mvcin\t\0" + /* 11241 */ "tbegin\t\0" + /* 11249 */ "pgin\t\0" + /* 11255 */ "vfmin\t\0" + /* 11262 */ "vmn\t\0" + /* 11267 */ "vnn\t\0" + /* 11272 */ "mvn\t\0" + /* 11277 */ "lao\t\0" + /* 11282 */ "vmao\t\0" + /* 11288 */ "bo\t\0" + /* 11292 */ "loco\t\0" + /* 11298 */ "stoco\t\0" + /* 11305 */ "locgo\t\0" + /* 11312 */ "stocgo\t\0" + /* 11320 */ "jgo\t\0" + /* 11325 */ "locfho\t\0" + /* 11333 */ "stocfho\t\0" + /* 11342 */ "bio\t\0" + /* 11347 */ "lochio\t\0" + /* 11355 */ "locghio\t\0" + /* 11364 */ "lochhio\t\0" + /* 11373 */ "jo\t\0" + /* 11377 */ "vmalo\t\0" + /* 11384 */ "vmlo\t\0" + /* 11390 */ "plo\t\0" + /* 11395 */ "kmo\t\0" + /* 11400 */ "vmo\t\0" + /* 11405 */ "bno\t\0" + /* 11410 */ "locno\t\0" + /* 11417 */ "stocno\t\0" + /* 11425 */ "locgno\t\0" + /* 11433 */ "stocgno\t\0" + /* 11442 */ "jgno\t\0" + /* 11448 */ "locfhno\t\0" + /* 11457 */ "stocfhno\t\0" + /* 11467 */ "bino\t\0" + /* 11473 */ "lochino\t\0" + /* 11482 */ "locghino\t\0" + /* 11492 */ "lochhino\t\0" + /* 11502 */ "jno\t\0" + /* 11507 */ "ppno\t\0" + /* 11513 */ "locrno\t\0" + /* 11521 */ "locgrno\t\0" + /* 11530 */ "selgrno\t\0" + /* 11539 */ "locfhrno\t\0" + /* 11549 */ "selfhrno\t\0" + /* 11559 */ "selrno\t\0" + /* 11567 */ "prno\t\0" + /* 11573 */ "vno\t\0" + /* 11578 */ "troo\t\0" + /* 11584 */ "locro\t\0" + /* 11591 */ "vzero\t\0" + /* 11598 */ "locgro\t\0" + /* 11606 */ "selgro\t\0" + /* 11614 */ "locfhro\t\0" + /* 11623 */ "selfhro\t\0" + /* 11632 */ "selro\t\0" + /* 11639 */ "vfpso\t\0" + /* 11646 */ "trto\t\0" + /* 11652 */ "mvo\t\0" + /* 11657 */ "stap\t\0" + /* 11663 */ "vap\t\0" + /* 11668 */ "zap\t\0" + /* 11673 */ "bp\t\0" + /* 11677 */ "locp\t\0" + /* 11683 */ "stocp\t\0" + /* 11690 */ "mvcp\t\0" + /* 11696 */ "vschdp\t\0" + /* 11704 */ "stidp\t\0" + /* 11711 */ "rdp\t\0" + /* 11716 */ "vsdp\t\0" + /* 11722 */ "vdp\t\0" + /* 11727 */ "vclzdp\t\0" + /* 11735 */ "vlrep\t\0" + /* 11742 */ "vlbrrep\t\0" + /* 11751 */ "vrep\t\0" + /* 11757 */ "vclfp\t\0" + /* 11764 */ "vcsfp\t\0" + /* 11771 */ "locgp\t\0" + /* 11778 */ "stocgp\t\0" + /* 11786 */ "sigp\t\0" + /* 11792 */ "jgp\t\0" + /* 11797 */ "vlvgp\t\0" + /* 11804 */ "vschp\t\0" + /* 11811 */ "locfhp\t\0" + /* 11819 */ "stocfhp\t\0" + /* 11828 */ "vscshp\t\0" + /* 11836 */ "bip\t\0" + /* 11841 */ "lochip\t\0" + /* 11849 */ "locghip\t\0" + /* 11858 */ "lochhip\t\0" + /* 11867 */ "vlip\t\0" + /* 11873 */ "jp\t\0" + /* 11877 */ "vlp\t\0" + /* 11882 */ "vmp\t\0" + /* 11887 */ "bnp\t\0" + /* 11892 */ "locnp\t\0" + /* 11899 */ "stocnp\t\0" + /* 11907 */ "locgnp\t\0" + /* 11915 */ "stocgnp\t\0" + /* 11924 */ "jgnp\t\0" + /* 11930 */ "locfhnp\t\0" + /* 11939 */ "stocfhnp\t\0" + /* 11949 */ "binp\t\0" + /* 11955 */ "lochinp\t\0" + /* 11964 */ "locghinp\t\0" + /* 11974 */ "lochhinp\t\0" + /* 11984 */ "jnp\t\0" + /* 11989 */ "locrnp\t\0" + /* 11997 */ "locgrnp\t\0" + /* 12006 */ "selgrnp\t\0" + /* 12015 */ "locfhrnp\t\0" + /* 12025 */ "selfhrnp\t\0" + /* 12035 */ "selrnp\t\0" + /* 12043 */ "vpsop\t\0" + /* 12050 */ "bpp\t\0" + /* 12055 */ "lpp\t\0" + /* 12060 */ "locrp\t\0" + /* 12067 */ "locgrp\t\0" + /* 12075 */ "selgrp\t\0" + /* 12083 */ "locfhrp\t\0" + /* 12092 */ "selfhrp\t\0" + /* 12101 */ "selrp\t\0" + /* 12108 */ "bprp\t\0" + /* 12114 */ "vsrp\t\0" + /* 12120 */ "vrp\t\0" + /* 12125 */ "lasp\t\0" + /* 12131 */ "csp\t\0" + /* 12136 */ "vschsp\t\0" + /* 12144 */ "vmsp\t\0" + /* 12150 */ "vsp\t\0" + /* 12155 */ "vtp\t\0" + /* 12160 */ "vschxp\t\0" + /* 12168 */ "vaq\t\0" + /* 12173 */ "vacq\t\0" + /* 12179 */ "vaccq\t\0" + /* 12186 */ "vacccq\t\0" + /* 12194 */ "vceq\t\0" + /* 12200 */ "vsbcbiq\t\0" + /* 12209 */ "vscbiq\t\0" + /* 12217 */ "vsbiq\t\0" + /* 12224 */ "vsumq\t\0" + /* 12231 */ "lpq\t\0" + /* 12236 */ "stpq\t\0" + /* 12242 */ "vlbrq\t\0" + /* 12249 */ "vstbrq\t\0" + /* 12257 */ "vfsq\t\0" + /* 12263 */ "vsq\t\0" + /* 12268 */ "lbear\t\0" + /* 12275 */ "stbear\t\0" + /* 12283 */ "epar\t\0" + /* 12289 */ "esar\t\0" + /* 12295 */ "ssar\t\0" + /* 12301 */ "tar\t\0" + /* 12306 */ "madbr\t\0" + /* 12313 */ "lcdbr\t\0" + /* 12320 */ "ddbr\t\0" + /* 12326 */ "ledbr\t\0" + /* 12333 */ "cfdbr\t\0" + /* 12340 */ "clfdbr\t\0" + /* 12348 */ "cgdbr\t\0" + /* 12355 */ "clgdbr\t\0" + /* 12363 */ "didbr\t\0" + /* 12370 */ "fidbr\t\0" + /* 12377 */ "kdbr\t\0" + /* 12383 */ "mdbr\t\0" + /* 12389 */ "lndbr\t\0" + /* 12396 */ "lpdbr\t\0" + /* 12403 */ "sqdbr\t\0" + /* 12410 */ "msdbr\t\0" + /* 12417 */ "ltdbr\t\0" + /* 12424 */ "lxdbr\t\0" + /* 12431 */ "mxdbr\t\0" + /* 12438 */ "maebr\t\0" + /* 12445 */ "lcebr\t\0" + /* 12452 */ "ldebr\t\0" + /* 12459 */ "mdebr\t\0" + /* 12466 */ "meebr\t\0" + /* 12473 */ "cfebr\t\0" + /* 12480 */ "clfebr\t\0" + /* 12488 */ "cgebr\t\0" + /* 12495 */ "clgebr\t\0" + /* 12503 */ "diebr\t\0" + /* 12510 */ "fiebr\t\0" + /* 12517 */ "kebr\t\0" + /* 12523 */ "lnebr\t\0" + /* 12530 */ "lpebr\t\0" + /* 12537 */ "sqebr\t\0" + /* 12544 */ "msebr\t\0" + /* 12551 */ "ltebr\t\0" + /* 12558 */ "lxebr\t\0" + /* 12565 */ "cdfbr\t\0" + /* 12572 */ "cefbr\t\0" + /* 12579 */ "cdlfbr\t\0" + /* 12587 */ "celfbr\t\0" + /* 12595 */ "cxlfbr\t\0" + /* 12603 */ "cxfbr\t\0" + /* 12610 */ "cdgbr\t\0" + /* 12617 */ "cegbr\t\0" + /* 12624 */ "cdlgbr\t\0" + /* 12632 */ "celgbr\t\0" + /* 12640 */ "cxlgbr\t\0" + /* 12648 */ "cxgbr\t\0" + /* 12655 */ "slbr\t\0" + /* 12661 */ "vlbr\t\0" + /* 12667 */ "vstbr\t\0" + /* 12674 */ "axbr\t\0" + /* 12680 */ "lcxbr\t\0" + /* 12687 */ "ldxbr\t\0" + /* 12694 */ "lexbr\t\0" + /* 12701 */ "cfxbr\t\0" + /* 12708 */ "clfxbr\t\0" + /* 12716 */ "cgxbr\t\0" + /* 12723 */ "clgxbr\t\0" + /* 12731 */ "fixbr\t\0" + /* 12738 */ "kxbr\t\0" + /* 12744 */ "mxbr\t\0" + /* 12750 */ "lnxbr\t\0" + /* 12757 */ "lpxbr\t\0" + /* 12764 */ "sqxbr\t\0" + /* 12771 */ "sxbr\t\0" + /* 12777 */ "ltxbr\t\0" + /* 12784 */ "bcr\t\0" + /* 12789 */ "llgcr\t\0" + /* 12796 */ "alcr\t\0" + /* 12802 */ "llcr\t\0" + /* 12808 */ "locr\t\0" + /* 12814 */ "madr\t\0" + /* 12820 */ "tbdr\t\0" + /* 12826 */ "lcdr\t\0" + /* 12832 */ "ddr\t\0" + /* 12837 */ "tbedr\t\0" + /* 12844 */ "ledr\t\0" + /* 12850 */ "cfdr\t\0" + /* 12856 */ "cgdr\t\0" + /* 12862 */ "lgdr\t\0" + /* 12868 */ "thdr\t\0" + /* 12874 */ "fidr\t\0" + /* 12880 */ "ldr\t\0" + /* 12885 */ "mdr\t\0" + /* 12890 */ "lndr\t\0" + /* 12896 */ "lpdr\t\0" + /* 12902 */ "sqdr\t\0" + /* 12908 */ "lrdr\t\0" + /* 12914 */ "msdr\t\0" + /* 12920 */ "cpsdr\t\0" + /* 12927 */ "ltdr\t\0" + /* 12933 */ "lxdr\t\0" + /* 12939 */ "mxdr\t\0" + /* 12945 */ "lzdr\t\0" + /* 12951 */ "maer\t\0" + /* 12957 */ "ber\t\0" + /* 12962 */ "lcer\t\0" + /* 12968 */ "thder\t\0" + /* 12975 */ "lder\t\0" + /* 12981 */ "mder\t\0" + /* 12987 */ "meer\t\0" + /* 12993 */ "cfer\t\0" + /* 12999 */ "cger\t\0" + /* 13005 */ "bher\t\0" + /* 13011 */ "bnher\t\0" + /* 13018 */ "fier\t\0" + /* 13024 */ "bler\t\0" + /* 13030 */ "bnler\t\0" + /* 13037 */ "vler\t\0" + /* 13043 */ "mer\t\0" + /* 13048 */ "bner\t\0" + /* 13054 */ "lner\t\0" + /* 13060 */ "lper\t\0" + /* 13066 */ "sqer\t\0" + /* 13072 */ "lrer\t\0" + /* 13078 */ "mser\t\0" + /* 13084 */ "lter\t\0" + /* 13090 */ "vster\t\0" + /* 13097 */ "lxer\t\0" + /* 13103 */ "lzer\t\0" + /* 13109 */ "lcdfr\t\0" + /* 13116 */ "lndfr\t\0" + /* 13123 */ "lpdfr\t\0" + /* 13130 */ "cefr\t\0" + /* 13136 */ "agfr\t\0" + /* 13142 */ "lcgfr\t\0" + /* 13149 */ "algfr\t\0" + /* 13156 */ "clgfr\t\0" + /* 13163 */ "llgfr\t\0" + /* 13170 */ "slgfr\t\0" + /* 13177 */ "lngfr\t\0" + /* 13184 */ "lpgfr\t\0" + /* 13191 */ "dsgfr\t\0" + /* 13198 */ "msgfr\t\0" + /* 13205 */ "ltgfr\t\0" + /* 13212 */ "cxfr\t\0" + /* 13218 */ "agr\t\0" + /* 13223 */ "slbgr\t\0" + /* 13230 */ "alcgr\t\0" + /* 13237 */ "locgr\t\0" + /* 13244 */ "cdgr\t\0" + /* 13250 */ "ldgr\t\0" + /* 13256 */ "cegr\t\0" + /* 13262 */ "algr\t\0" + /* 13268 */ "clgr\t\0" + /* 13274 */ "dlgr\t\0" + /* 13280 */ "selgr\t\0" + /* 13287 */ "mlgr\t\0" + /* 13293 */ "slgr\t\0" + /* 13299 */ "lngr\t\0" + /* 13305 */ "flogr\t\0" + /* 13312 */ "lpgr\t\0" + /* 13318 */ "dsgr\t\0" + /* 13324 */ "msgr\t\0" + /* 13330 */ "bctgr\t\0" + /* 13337 */ "ltgr\t\0" + /* 13343 */ "lrvgr\t\0" + /* 13350 */ "cxgr\t\0" + /* 13356 */ "bhr\t\0" + /* 13361 */ "locfhr\t\0" + /* 13369 */ "selfhr\t\0" + /* 13377 */ "llghr\t\0" + /* 13384 */ "chhr\t\0" + /* 13390 */ "ahhhr\t\0" + /* 13397 */ "alhhhr\t\0" + /* 13405 */ "slhhhr\t\0" + /* 13413 */ "shhhr\t\0" + /* 13420 */ "clhhr\t\0" + /* 13427 */ "blhr\t\0" + /* 13433 */ "llhr\t\0" + /* 13439 */ "bnlhr\t\0" + /* 13446 */ "bnhr\t\0" + /* 13452 */ "mayhr\t\0" + /* 13459 */ "myhr\t\0" + /* 13465 */ "epair\t\0" + /* 13472 */ "esair\t\0" + /* 13479 */ "ssair\t\0" + /* 13486 */ "bakr\t\0" + /* 13492 */ "balr\t\0" + /* 13498 */ "blr\t\0" + /* 13503 */ "clr\t\0" + /* 13508 */ "dlr\t\0" + /* 13513 */ "selr\t\0" + /* 13519 */ "vflr\t\0" + /* 13525 */ "chlr\t\0" + /* 13531 */ "ahhlr\t\0" + /* 13538 */ "alhhlr\t\0" + /* 13546 */ "slhhlr\t\0" + /* 13554 */ "shhlr\t\0" + /* 13561 */ "clhlr\t\0" + /* 13568 */ "mlr\t\0" + /* 13573 */ "bnlr\t\0" + /* 13579 */ "vlrlr\t\0" + /* 13586 */ "vstrlr\t\0" + /* 13594 */ "slr\t\0" + /* 13599 */ "vlr\t\0" + /* 13604 */ "maylr\t\0" + /* 13611 */ "mylr\t\0" + /* 13617 */ "bmr\t\0" + /* 13622 */ "bnmr\t\0" + /* 13628 */ "lnr\t\0" + /* 13633 */ "bor\t\0" + /* 13638 */ "bnor\t\0" + /* 13644 */ "bpr\t\0" + /* 13649 */ "lpr\t\0" + /* 13654 */ "bnpr\t\0" + /* 13660 */ "vsrpr\t\0" + /* 13667 */ "basr\t\0" + /* 13673 */ "sfasr\t\0" + /* 13680 */ "msr\t\0" + /* 13685 */ "bctr\t\0" + /* 13691 */ "ecctr\t\0" + /* 13698 */ "scctr\t\0" + /* 13705 */ "kmctr\t\0" + /* 13712 */ "epctr\t\0" + /* 13719 */ "spctr\t\0" + /* 13726 */ "qadtr\t\0" + /* 13733 */ "cdtr\t\0" + /* 13739 */ "ddtr\t\0" + /* 13745 */ "cedtr\t\0" + /* 13752 */ "eedtr\t\0" + /* 13759 */ "iedtr\t\0" + /* 13766 */ "ledtr\t\0" + /* 13773 */ "cfdtr\t\0" + /* 13780 */ "clfdtr\t\0" + /* 13788 */ "cgdtr\t\0" + /* 13795 */ "clgdtr\t\0" + /* 13803 */ "fidtr\t\0" + /* 13810 */ "kdtr\t\0" + /* 13816 */ "mdtr\t\0" + /* 13822 */ "rrdtr\t\0" + /* 13829 */ "csdtr\t\0" + /* 13836 */ "esdtr\t\0" + /* 13843 */ "ltdtr\t\0" + /* 13850 */ "cudtr\t\0" + /* 13857 */ "lxdtr\t\0" + /* 13864 */ "ldetr\t\0" + /* 13871 */ "cdftr\t\0" + /* 13878 */ "cdlftr\t\0" + /* 13886 */ "cxlftr\t\0" + /* 13894 */ "cxftr\t\0" + /* 13901 */ "cdgtr\t\0" + /* 13908 */ "cdlgtr\t\0" + /* 13916 */ "llgtr\t\0" + /* 13923 */ "cxlgtr\t\0" + /* 13931 */ "cxgtr\t\0" + /* 13938 */ "ltr\t\0" + /* 13943 */ "trtr\t\0" + /* 13949 */ "cdstr\t\0" + /* 13956 */ "vistr\t\0" + /* 13963 */ "cxstr\t\0" + /* 13970 */ "cdutr\t\0" + /* 13977 */ "cxutr\t\0" + /* 13984 */ "qaxtr\t\0" + /* 13991 */ "cxtr\t\0" + /* 13997 */ "ldxtr\t\0" + /* 14004 */ "cextr\t\0" + /* 14011 */ "eextr\t\0" + /* 14018 */ "iextr\t\0" + /* 14025 */ "cfxtr\t\0" + /* 14032 */ "clfxtr\t\0" + /* 14040 */ "cgxtr\t\0" + /* 14047 */ "clgxtr\t\0" + /* 14055 */ "fixtr\t\0" + /* 14062 */ "kxtr\t\0" + /* 14068 */ "mxtr\t\0" + /* 14074 */ "rrxtr\t\0" + /* 14081 */ "csxtr\t\0" + /* 14088 */ "esxtr\t\0" + /* 14095 */ "ltxtr\t\0" + /* 14102 */ "cuxtr\t\0" + /* 14109 */ "aur\t\0" + /* 14114 */ "sur\t\0" + /* 14119 */ "lrvr\t\0" + /* 14125 */ "awr\t\0" + /* 14130 */ "swr\t\0" + /* 14135 */ "axr\t\0" + /* 14140 */ "lcxr\t\0" + /* 14146 */ "ldxr\t\0" + /* 14152 */ "lexr\t\0" + /* 14158 */ "cfxr\t\0" + /* 14164 */ "cgxr\t\0" + /* 14170 */ "fixr\t\0" + /* 14176 */ "lxr\t\0" + /* 14181 */ "mxr\t\0" + /* 14186 */ "lnxr\t\0" + /* 14192 */ "lpxr\t\0" + /* 14198 */ "sqxr\t\0" + /* 14204 */ "sxr\t\0" + /* 14209 */ "ltxr\t\0" + /* 14215 */ "lzxr\t\0" + /* 14221 */ "mayr\t\0" + /* 14227 */ "myr\t\0" + /* 14232 */ "bzr\t\0" + /* 14237 */ "vpkzr\t\0" + /* 14244 */ "bnzr\t\0" + /* 14250 */ "bas\t\0" + /* 14255 */ "lfas\t\0" + /* 14261 */ "bras\t\0" + /* 14267 */ "vstrcbs\t\0" + /* 14276 */ "vfcedbs\t\0" + /* 14285 */ "wfcedbs\t\0" + /* 14294 */ "vfchedbs\t\0" + /* 14304 */ "wfchedbs\t\0" + /* 14314 */ "vfkhedbs\t\0" + /* 14324 */ "wfkhedbs\t\0" + /* 14334 */ "vfkedbs\t\0" + /* 14343 */ "wfkedbs\t\0" + /* 14352 */ "vfchdbs\t\0" + /* 14361 */ "wfchdbs\t\0" + /* 14370 */ "vfkhdbs\t\0" + /* 14379 */ "wfkhdbs\t\0" + /* 14388 */ "vfaebs\t\0" + /* 14396 */ "vfeebs\t\0" + /* 14404 */ "vfenebs\t\0" + /* 14413 */ "vchbs\t\0" + /* 14420 */ "vchlbs\t\0" + /* 14428 */ "vceqbs\t\0" + /* 14436 */ "vistrbs\t\0" + /* 14445 */ "vfcesbs\t\0" + /* 14454 */ "wfcesbs\t\0" + /* 14463 */ "vfchesbs\t\0" + /* 14473 */ "wfchesbs\t\0" + /* 14483 */ "vfkhesbs\t\0" + /* 14493 */ "wfkhesbs\t\0" + /* 14503 */ "vfkesbs\t\0" + /* 14512 */ "wfkesbs\t\0" + /* 14521 */ "vfchsbs\t\0" + /* 14530 */ "wfchsbs\t\0" + /* 14539 */ "vfkhsbs\t\0" + /* 14548 */ "wfkhsbs\t\0" + /* 14557 */ "wfcexbs\t\0" + /* 14566 */ "wfchexbs\t\0" + /* 14576 */ "wfkhexbs\t\0" + /* 14586 */ "wfkexbs\t\0" + /* 14595 */ "wfchxbs\t\0" + /* 14604 */ "wfkhxbs\t\0" + /* 14613 */ "vstrczbs\t\0" + /* 14623 */ "vfaezbs\t\0" + /* 14632 */ "vfeezbs\t\0" + /* 14641 */ "vfenezbs\t\0" + /* 14651 */ "mvcs\t\0" + /* 14657 */ "cds\t\0" + /* 14662 */ "vstrcfs\t\0" + /* 14671 */ "vfaefs\t\0" + /* 14679 */ "vfeefs\t\0" + /* 14687 */ "vfenefs\t\0" + /* 14696 */ "vchfs\t\0" + /* 14703 */ "vchlfs\t\0" + /* 14711 */ "vceqfs\t\0" + /* 14719 */ "vistrfs\t\0" + /* 14728 */ "vpksfs\t\0" + /* 14736 */ "vpklsfs\t\0" + /* 14745 */ "vfs\t\0" + /* 14750 */ "vstrczfs\t\0" + /* 14760 */ "vfaezfs\t\0" + /* 14769 */ "vfeezfs\t\0" + /* 14778 */ "vfenezfs\t\0" + /* 14788 */ "vchgs\t\0" + /* 14795 */ "vchlgs\t\0" + /* 14803 */ "vceqgs\t\0" + /* 14811 */ "vpksgs\t\0" + /* 14819 */ "vpklsgs\t\0" + /* 14828 */ "vstrchs\t\0" + /* 14837 */ "vfaehs\t\0" + /* 14845 */ "vfeehs\t\0" + /* 14853 */ "vfenehs\t\0" + /* 14862 */ "vchhs\t\0" + /* 14869 */ "vchlhs\t\0" + /* 14877 */ "vceqhs\t\0" + /* 14885 */ "vistrhs\t\0" + /* 14894 */ "vpkshs\t\0" + /* 14902 */ "vpklshs\t\0" + /* 14911 */ "vstrczhs\t\0" + /* 14921 */ "vfaezhs\t\0" + /* 14930 */ "vfeezhs\t\0" + /* 14939 */ "vfenezhs\t\0" + /* 14949 */ "vpks\t\0" + /* 14955 */ "vpkls\t\0" + /* 14962 */ "vflls\t\0" + /* 14969 */ "wflls\t\0" + /* 14976 */ "vfms\t\0" + /* 14982 */ "vfnms\t\0" + /* 14989 */ "mvcos\t\0" + /* 14996 */ "stcps\t\0" + /* 15003 */ "vcfps\t\0" + /* 15010 */ "vstrs\t\0" + /* 15017 */ "ts\t\0" + /* 15021 */ "vs\t\0" + /* 15025 */ "llgfat\t\0" + /* 15033 */ "lgat\t\0" + /* 15039 */ "lfhat\t\0" + /* 15046 */ "lat\t\0" + /* 15051 */ "llgtat\t\0" + /* 15059 */ "bct\t\0" + /* 15064 */ "vpopct\t\0" + /* 15072 */ "brct\t\0" + /* 15078 */ "tdcdt\t\0" + /* 15085 */ "tdgdt\t\0" + /* 15092 */ "sldt\t\0" + /* 15098 */ "cpdt\t\0" + /* 15104 */ "srdt\t\0" + /* 15110 */ "czdt\t\0" + /* 15116 */ "tdcet\t\0" + /* 15123 */ "tdget\t\0" + /* 15130 */ "clgt\t\0" + /* 15136 */ "llgt\t\0" + /* 15142 */ "cit\t\0" + /* 15147 */ "clfit\t\0" + /* 15154 */ "cgit\t\0" + /* 15160 */ "clgit\t\0" + /* 15167 */ "clt\t\0" + /* 15172 */ "srnmt\t\0" + /* 15179 */ "popcnt\t\0" + /* 15187 */ "tprot\t\0" + /* 15194 */ "trot\t\0" + /* 15200 */ "cdpt\t\0" + /* 15206 */ "spt\t\0" + /* 15211 */ "stpt\t\0" + /* 15217 */ "cxpt\t\0" + /* 15223 */ "crt\t\0" + /* 15228 */ "cgrt\t\0" + /* 15234 */ "clgrt\t\0" + /* 15241 */ "clrt\t\0" + /* 15247 */ "tabort\t\0" + /* 15255 */ "trt\t\0" + /* 15260 */ "clst\t\0" + /* 15266 */ "srst\t\0" + /* 15272 */ "csst\t\0" + /* 15278 */ "mvst\t\0" + /* 15284 */ "trtt\t\0" + /* 15290 */ "pgout\t\0" + /* 15297 */ "tdcxt\t\0" + /* 15304 */ "tdgxt\t\0" + /* 15311 */ "slxt\t\0" + /* 15317 */ "cpxt\t\0" + /* 15323 */ "srxt\t\0" + /* 15329 */ "czxt\t\0" + /* 15335 */ "cdzt\t\0" + /* 15341 */ "cxzt\t\0" + /* 15347 */ "au\t\0" + /* 15351 */ "cutfu\t\0" + /* 15358 */ "unpku\t\0" + /* 15365 */ "clclu\t\0" + /* 15372 */ "mvclu\t\0" + /* 15379 */ "su\t\0" + /* 15383 */ "srstu\t\0" + /* 15390 */ "vesrav\t\0" + /* 15398 */ "vlgv\t\0" + /* 15404 */ "verllv\t\0" + /* 15412 */ "vesrlv\t\0" + /* 15420 */ "veslv\t\0" + /* 15427 */ "lrv\t\0" + /* 15432 */ "strv\t\0" + /* 15438 */ "aw\t\0" + /* 15442 */ "vmalhw\t\0" + /* 15450 */ "vmlhw\t\0" + /* 15457 */ "vuplhw\t\0" + /* 15465 */ "stcrw\t\0" + /* 15472 */ "epsw\t\0" + /* 15478 */ "lpsw\t\0" + /* 15484 */ "lax\t\0" + /* 15489 */ "vfmax\t\0" + /* 15496 */ "ex\t\0" + /* 15500 */ "vmx\t\0" + /* 15505 */ "vnx\t\0" + /* 15510 */ "spx\t\0" + /* 15515 */ "stpx\t\0" + /* 15521 */ "wflrx\t\0" + /* 15528 */ "vx\t\0" + /* 15532 */ "lay\t\0" + /* 15537 */ "may\t\0" + /* 15542 */ "lray\t\0" + /* 15548 */ "cvby\t\0" + /* 15554 */ "icy\t\0" + /* 15559 */ "stcy\t\0" + /* 15565 */ "ldy\t\0" + /* 15570 */ "stdy\t\0" + /* 15576 */ "cvdy\t\0" + /* 15582 */ "laey\t\0" + /* 15588 */ "ley\t\0" + /* 15593 */ "stey\t\0" + /* 15599 */ "lpswey\t\0" + /* 15607 */ "mfy\t\0" + /* 15612 */ "ahy\t\0" + /* 15617 */ "chy\t\0" + /* 15622 */ "lhy\t\0" + /* 15627 */ "mhy\t\0" + /* 15632 */ "shy\t\0" + /* 15637 */ "sthy\t\0" + /* 15643 */ "cliy\t\0" + /* 15649 */ "niy\t\0" + /* 15654 */ "oiy\t\0" + /* 15659 */ "mviy\t\0" + /* 15665 */ "xiy\t\0" + /* 15670 */ "aly\t\0" + /* 15675 */ "cly\t\0" + /* 15680 */ "sly\t\0" + /* 15685 */ "lamy\t\0" + /* 15691 */ "stamy\t\0" + /* 15698 */ "icmy\t\0" + /* 15704 */ "stcmy\t\0" + /* 15711 */ "clmy\t\0" + /* 15717 */ "stmy\t\0" + /* 15723 */ "ny\t\0" + /* 15727 */ "oy\t\0" + /* 15731 */ "csy\t\0" + /* 15736 */ "cdsy\t\0" + /* 15742 */ "msy\t\0" + /* 15747 */ "sty\t\0" + /* 15752 */ "xy\t\0" + /* 15756 */ "bz\t\0" + /* 15760 */ "locz\t\0" + /* 15766 */ "stocz\t\0" + /* 15773 */ "vllez\t\0" + /* 15780 */ "locgz\t\0" + /* 15787 */ "stocgz\t\0" + /* 15795 */ "jgz\t\0" + /* 15800 */ "locfhz\t\0" + /* 15808 */ "stocfhz\t\0" + /* 15817 */ "biz\t\0" + /* 15822 */ "lochiz\t\0" + /* 15830 */ "locghiz\t\0" + /* 15839 */ "lochhiz\t\0" + /* 15848 */ "jz\t\0" + /* 15852 */ "vupkz\t\0" + /* 15859 */ "vpkz\t\0" + /* 15865 */ "vclz\t\0" + /* 15871 */ "bnz\t\0" + /* 15876 */ "locnz\t\0" + /* 15883 */ "stocnz\t\0" + /* 15891 */ "locgnz\t\0" + /* 15899 */ "stocgnz\t\0" + /* 15908 */ "jgnz\t\0" + /* 15914 */ "locfhnz\t\0" + /* 15923 */ "stocfhnz\t\0" + /* 15933 */ "binz\t\0" + /* 15939 */ "lochinz\t\0" + /* 15948 */ "locghinz\t\0" + /* 15958 */ "lochhinz\t\0" + /* 15968 */ "jnz\t\0" + /* 15973 */ "locrnz\t\0" + /* 15981 */ "locgrnz\t\0" + /* 15990 */ "selgrnz\t\0" + /* 15999 */ "locfhrnz\t\0" + /* 16009 */ "selfhrnz\t\0" + /* 16019 */ "selrnz\t\0" + /* 16027 */ "vllebrz\t\0" + /* 16036 */ "locrz\t\0" + /* 16043 */ "locgrz\t\0" + /* 16051 */ "selgrz\t\0" + /* 16059 */ "locfhrz\t\0" + /* 16068 */ "selfhrz\t\0" + /* 16077 */ "selrz\t\0" + /* 16084 */ "vctz\t\0" + /* 16090 */ "mvz\t\0" + /* 16095 */ ".insn e,\0" + /* 16104 */ ".insn rie,\0" + /* 16115 */ ".insn rre,\0" + /* 16126 */ ".insn rse,\0" + /* 16137 */ ".insn sse,\0" + /* 16148 */ ".insn rxe,\0" + /* 16159 */ ".insn rrf,\0" + /* 16170 */ ".insn ssf,\0" + /* 16181 */ ".insn rxf,\0" + /* 16192 */ ".insn ri,\0" + /* 16202 */ ".insn vri,\0" + /* 16213 */ ".insn si,\0" + /* 16223 */ ".insn rsi,\0" + /* 16234 */ ".insn vsi,\0" + /* 16245 */ ".insn ril,\0" + /* 16256 */ ".insn sil,\0" + /* 16267 */ ".insn rr,\0" + /* 16277 */ ".insn vrr,\0" + /* 16288 */ ".insn s,\0" + /* 16297 */ ".insn ris,\0" + /* 16308 */ ".insn rs,\0" + /* 16318 */ ".insn rrs,\0" + /* 16329 */ ".insn vrs,\0" + /* 16340 */ ".insn ss,\0" + /* 16350 */ ".insn rilu,\0" + /* 16362 */ ".insn vrv,\0" + /* 16373 */ ".insn rx,\0" + /* 16383 */ ".insn vrx,\0" + /* 16394 */ ".insn siy,\0" + /* 16405 */ ".insn rsy,\0" + /* 16416 */ ".insn rxy,\0" + /* 16427 */ "# XRay Function Patchable RET.\0" + /* 16458 */ "# XRay Typed Event Log.\0" + /* 16482 */ "# XRay Custom Event Log.\0" + /* 16507 */ "# XRay Function Enter.\0" + /* 16530 */ "# XRay Tail Call Exit.\0" + /* 16553 */ "# XRay Function Exit.\0" + /* 16575 */ "sam31\0" + /* 16581 */ "trap2\0" + /* 16587 */ "sam24\0" + /* 16593 */ "sam64\0" + /* 16599 */ "LIFETIME_END\0" + /* 16612 */ "PSEUDO_PROBE\0" + /* 16625 */ "BUNDLE\0" + /* 16632 */ "DBG_VALUE\0" + /* 16642 */ "DBG_INSTR_REF\0" + /* 16656 */ "DBG_PHI\0" + /* 16664 */ "DBG_LABEL\0" + /* 16674 */ "LIFETIME_START\0" + /* 16689 */ "DBG_VALUE_LIST\0" + /* 16704 */ "nnpa\0" + /* 16709 */ "cib\0" + /* 16713 */ "cgib\0" + /* 16718 */ "clgib\0" + /* 16724 */ "clib\0" + /* 16729 */ "palb\0" + /* 16734 */ "ptlb\0" + /* 16739 */ "crb\0" + /* 16743 */ "cgrb\0" + /* 16748 */ "clgrb\0" + /* 16754 */ "clrb\0" + /* 16759 */ "pcc\0" + /* 16763 */ "loc\0" + /* 16767 */ "stoc\0" + /* 16772 */ "tend\0" + /* 16777 */ "ptff\0" + /* 16782 */ "sckpf\0" + /* 16788 */ "locg\0" + /* 16793 */ "stocg\0" + /* 16799 */ "jg\0" + /* 16802 */ "csch\0" + /* 16807 */ "hsch\0" + /* 16812 */ "rsch\0" + /* 16817 */ "xsch\0" + /* 16822 */ "locfh\0" + /* 16828 */ "stocfh\0" + /* 16835 */ "bi\0" + /* 16838 */ "lochi\0" + /* 16844 */ "locghi\0" + /* 16851 */ "lochhi\0" + /* 16858 */ "cij\0" + /* 16862 */ "cgij\0" + /* 16867 */ "clgij\0" + /* 16873 */ "clij\0" + /* 16878 */ "crj\0" + /* 16882 */ "cgrj\0" + /* 16887 */ "clgrj\0" + /* 16893 */ "clrj\0" + /* 16898 */ "ipk\0" + /* 16902 */ "sal\0" + /* 16906 */ "# FEntry call\0" + /* 16920 */ "tam\0" + /* 16924 */ "schm\0" + /* 16929 */ "pckmo\0" + /* 16935 */ "pfpo\0" + /* 16940 */ "rchp\0" + /* 16945 */ "nop\0" + /* 16949 */ "locr\0" + /* 16954 */ "locgr\0" + /* 16960 */ "selgr\0" + /* 16966 */ "locfhr\0" + /* 16973 */ "selfhr\0" + /* 16980 */ "selr\0" + /* 16985 */ "pr\0" + /* 16988 */ "clgt\0" + /* 16993 */ "cit\0" + /* 16997 */ "clfit\0" + /* 17003 */ "cgit\0" + /* 17008 */ "clgit\0" + /* 17014 */ "clt\0" + /* 17018 */ "upt\0" + /* 17022 */ "crt\0" + /* 17026 */ "cgrt\0" + /* 17031 */ "clgrt\0" + /* 17037 */ "clrt\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 16633U, // DBG_VALUE + 16690U, // DBG_VALUE_LIST + 16643U, // DBG_INSTR_REF + 16657U, // DBG_PHI + 16665U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 16626U, // BUNDLE + 16675U, // LIFETIME_START + 16600U, // LIFETIME_END + 16613U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 16907U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 16508U, // PATCHABLE_FUNCTION_ENTER + 16428U, // PATCHABLE_RET + 16554U, // PATCHABLE_FUNCTION_EXIT + 16531U, // PATCHABLE_TAIL_CALL + 16483U, // PATCHABLE_EVENT_CALL + 16459U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ADB_MemFoldPseudo + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADJDYNALLOC + 0U, // AEB_MemFoldPseudo + 0U, // AEXT128 + 0U, // AFIMux + 0U, // AG_MemFoldPseudo + 0U, // AHIMux + 0U, // AHIMuxK + 0U, // ALG_MemFoldPseudo + 0U, // AL_MemFoldPseudo + 0U, // ATOMIC_CMP_SWAPW + 0U, // ATOMIC_LOADW_AFI + 0U, // ATOMIC_LOADW_AR + 0U, // ATOMIC_LOADW_MAX + 0U, // ATOMIC_LOADW_MIN + 0U, // ATOMIC_LOADW_NILH + 0U, // ATOMIC_LOADW_NILHi + 0U, // ATOMIC_LOADW_NR + 0U, // ATOMIC_LOADW_NRi + 0U, // ATOMIC_LOADW_OILH + 0U, // ATOMIC_LOADW_OR + 0U, // ATOMIC_LOADW_SR + 0U, // ATOMIC_LOADW_UMAX + 0U, // ATOMIC_LOADW_UMIN + 0U, // ATOMIC_LOADW_XILF + 0U, // ATOMIC_LOADW_XR + 0U, // ATOMIC_LOAD_AFI + 0U, // ATOMIC_LOAD_AGFI + 0U, // ATOMIC_LOAD_AGHI + 0U, // ATOMIC_LOAD_AGR + 0U, // ATOMIC_LOAD_AHI + 0U, // ATOMIC_LOAD_AR + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NGR + 0U, // ATOMIC_LOAD_NGRi + 0U, // ATOMIC_LOAD_NIHF64 + 0U, // ATOMIC_LOAD_NIHF64i + 0U, // ATOMIC_LOAD_NIHH64 + 0U, // ATOMIC_LOAD_NIHH64i + 0U, // ATOMIC_LOAD_NIHL64 + 0U, // ATOMIC_LOAD_NIHL64i + 0U, // ATOMIC_LOAD_NILF + 0U, // ATOMIC_LOAD_NILF64 + 0U, // ATOMIC_LOAD_NILF64i + 0U, // ATOMIC_LOAD_NILFi + 0U, // ATOMIC_LOAD_NILH + 0U, // ATOMIC_LOAD_NILH64 + 0U, // ATOMIC_LOAD_NILH64i + 0U, // ATOMIC_LOAD_NILHi + 0U, // ATOMIC_LOAD_NILL + 0U, // ATOMIC_LOAD_NILL64 + 0U, // ATOMIC_LOAD_NILL64i + 0U, // ATOMIC_LOAD_NILLi + 0U, // ATOMIC_LOAD_NR + 0U, // ATOMIC_LOAD_NRi + 0U, // ATOMIC_LOAD_OGR + 0U, // ATOMIC_LOAD_OIHF64 + 0U, // ATOMIC_LOAD_OIHH64 + 0U, // ATOMIC_LOAD_OIHL64 + 0U, // ATOMIC_LOAD_OILF + 0U, // ATOMIC_LOAD_OILF64 + 0U, // ATOMIC_LOAD_OILH + 0U, // ATOMIC_LOAD_OILH64 + 0U, // ATOMIC_LOAD_OILL + 0U, // ATOMIC_LOAD_OILL64 + 0U, // ATOMIC_LOAD_OR + 0U, // ATOMIC_LOAD_SGR + 0U, // ATOMIC_LOAD_SR + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XGR + 0U, // ATOMIC_LOAD_XIHF64 + 0U, // ATOMIC_LOAD_XILF + 0U, // ATOMIC_LOAD_XILF64 + 0U, // ATOMIC_LOAD_XR + 0U, // ATOMIC_SWAPW + 0U, // ATOMIC_SWAP_32 + 0U, // ATOMIC_SWAP_64 + 0U, // A_MemFoldPseudo + 0U, // CFIMux + 0U, // CGIBCall + 0U, // CGIBReturn + 0U, // CGRBCall + 0U, // CGRBReturn + 0U, // CHIMux + 0U, // CIBCall + 0U, // CIBReturn + 0U, // CLCImm + 0U, // CLCReg + 0U, // CLFIMux + 0U, // CLGIBCall + 0U, // CLGIBReturn + 0U, // CLGRBCall + 0U, // CLGRBReturn + 0U, // CLIBCall + 0U, // CLIBReturn + 0U, // CLMux + 0U, // CLRBCall + 0U, // CLRBReturn + 0U, // CLSTLoop + 0U, // CMux + 0U, // CRBCall + 0U, // CRBReturn + 0U, // CallBASR + 0U, // CallBASR_XPLINK64 + 0U, // CallBCR + 0U, // CallBR + 0U, // CallBRASL + 0U, // CallBRASL_XPLINK64 + 0U, // CallBRCL + 0U, // CallJG + 0U, // CondReturn + 0U, // CondStore16 + 0U, // CondStore16Inv + 0U, // CondStore16Mux + 0U, // CondStore16MuxInv + 0U, // CondStore32 + 0U, // CondStore32Inv + 0U, // CondStore32Mux + 0U, // CondStore32MuxInv + 0U, // CondStore64 + 0U, // CondStore64Inv + 0U, // CondStore8 + 0U, // CondStore8Inv + 0U, // CondStore8Mux + 0U, // CondStore8MuxInv + 0U, // CondStoreF32 + 0U, // CondStoreF32Inv + 0U, // CondStoreF64 + 0U, // CondStoreF64Inv + 0U, // CondTrap + 0U, // DDB_MemFoldPseudo + 0U, // DEB_MemFoldPseudo + 0U, // EXRL_Pseudo + 0U, // GOT + 0U, // IIFMux + 0U, // IIHF64 + 0U, // IIHH64 + 0U, // IIHL64 + 0U, // IIHMux + 0U, // IILF64 + 0U, // IILH64 + 0U, // IILL64 + 0U, // IILMux + 0U, // L128 + 0U, // LBMux + 0U, // LEFR + 0U, // LFER + 0U, // LHIMux + 0U, // LHMux + 0U, // LLCMux + 0U, // LLCRMux + 0U, // LLHMux + 0U, // LLHRMux + 0U, // LMux + 0U, // LOCG_MemFoldPseudo + 0U, // LOCHIMux + 0U, // LOCMux + 0U, // LOCMux_MemFoldPseudo + 0U, // LOCRMux + 0U, // LTDBRCompare_VecPseudo + 0U, // LTEBRCompare_VecPseudo + 0U, // LTXBRCompare_VecPseudo + 0U, // LX + 0U, // MADB_MemFoldPseudo + 0U, // MAEB_MemFoldPseudo + 0U, // MDB_MemFoldPseudo + 0U, // MEEB_MemFoldPseudo + 0U, // MSC_MemFoldPseudo + 0U, // MSDB_MemFoldPseudo + 0U, // MSEB_MemFoldPseudo + 0U, // MSGC_MemFoldPseudo + 0U, // MVCImm + 0U, // MVCReg + 0U, // MVSTLoop + 0U, // MemBarrier + 0U, // NCImm + 0U, // NCReg + 0U, // NG_MemFoldPseudo + 0U, // NIFMux + 0U, // NIHF64 + 0U, // NIHH64 + 0U, // NIHL64 + 0U, // NIHMux + 0U, // NILF64 + 0U, // NILH64 + 0U, // NILL64 + 0U, // NILMux + 0U, // N_MemFoldPseudo + 0U, // OCImm + 0U, // OCReg + 0U, // OG_MemFoldPseudo + 0U, // OIFMux + 0U, // OIHF64 + 0U, // OIHH64 + 0U, // OIHL64 + 0U, // OIHMux + 0U, // OILF64 + 0U, // OILH64 + 0U, // OILL64 + 0U, // OILMux + 0U, // O_MemFoldPseudo + 0U, // PAIR128 + 0U, // PROBED_ALLOCA + 0U, // PROBED_STACKALLOC + 0U, // RISBHH + 0U, // RISBHL + 0U, // RISBLH + 0U, // RISBLL + 0U, // RISBMux + 0U, // Return + 0U, // SDB_MemFoldPseudo + 0U, // SEB_MemFoldPseudo + 0U, // SELRMux + 0U, // SG_MemFoldPseudo + 0U, // SLG_MemFoldPseudo + 0U, // SL_MemFoldPseudo + 0U, // SRSTLoop + 0U, // ST128 + 0U, // STCMux + 0U, // STHMux + 0U, // STMux + 0U, // STOCMux + 0U, // STX + 0U, // S_MemFoldPseudo + 0U, // Select32 + 0U, // Select64 + 0U, // SelectF128 + 0U, // SelectF32 + 0U, // SelectF64 + 0U, // SelectVR128 + 0U, // SelectVR32 + 0U, // SelectVR64 + 0U, // Serialize + 0U, // TBEGIN_nofloat + 0U, // TLS_GDCALL + 0U, // TLS_LDCALL + 0U, // TMHH64 + 0U, // TMHL64 + 0U, // TMHMux + 0U, // TMLH64 + 0U, // TMLL64 + 0U, // TMLMux + 0U, // Trap + 0U, // VL32 + 0U, // VL64 + 0U, // VLR32 + 0U, // VLR64 + 0U, // VLVGP32 + 0U, // VST32 + 0U, // VST64 + 0U, // XCImm + 0U, // XCReg + 0U, // XG_MemFoldPseudo + 0U, // XIFMux + 0U, // XIHF64 + 0U, // XILF64 + 0U, // X_MemFoldPseudo + 0U, // ZEXT128 + 32814U, // A + 35275U, // AD + 33273U, // ADB + 33599508U, // ADBR + 33600016U, // ADR + 2214639008U, // ADTR + 2214625582U, // ADTRA + 35405U, // AE + 33730U, // AEB + 33599640U, // AEBR + 33600153U, // AER + 100705141U, // AFI + 38641U, // AG + 37929U, // AGF + 100705151U, // AGFI + 33600337U, // AGFR + 39708U, // AGH + 134259664U, // AGHI + 2214634738U, // AGHIK + 33600419U, // AGR + 2214634808U, // AGRK + 167846965U, // AGSI + 39453U, // AH + 2214638671U, // AHHHR + 2214638812U, // AHHLR + 134259652U, // AHI + 2214634732U, // AHIK + 48381U, // AHY + 100703185U, // AIH + 42413U, // AL + 35138U, // ALC + 38765U, // ALCG + 33600431U, // ALCGR + 33599997U, // ALCR + 201368487U, // ALFI + 38949U, // ALG + 37946U, // ALGF + 201368459U, // ALGFI + 33600350U, // ALGFR + 2214634745U, // ALGHSIK + 33600463U, // ALGR + 2214634828U, // ALGRK + 167846971U, // ALGSI + 2214638678U, // ALHHHR + 2214638819U, // ALHHLR + 2214634754U, // ALHSIK + 33600694U, // ALR + 2214634875U, // ALRK + 167847022U, // ALSI + 100703250U, // ALSIH + 100707291U, // ALSIHN + 48439U, // ALY + 234990988U, // AP + 33599472U, // AR + 2214634791U, // ARK + 167846960U, // ASI + 48116U, // AU + 33601310U, // AUR + 48207U, // AW + 33601326U, // AWR + 33599875U, // AXBR + 33601336U, // AXR + 2214639266U, // AXTR + 2214625634U, // AXTRA + 48302U, // AY + 131513U, // B + 67155119U, // BAKR + 268477873U, // BAL + 67155125U, // BALR + 268482475U, // BAS + 67155300U, // BASR + 67152816U, // BASSM + 133726U, // BAsmE + 137782U, // BAsmH + 133856U, // BAsmHE + 140734U, // BAsmL + 134749U, // BAsmLE + 138336U, // BAsmLH + 141846U, // BAsmM + 135545U, // BAsmNE + 139263U, // BAsmNH + 134100U, // BAsmNHE + 141085U, // BAsmNL + 134996U, // BAsmNLE + 138631U, // BAsmNLH + 141995U, // BAsmNM + 142478U, // BAsmNO + 142960U, // BAsmNP + 146944U, // BAsmNZ + 142361U, // BAsmO + 142746U, // BAsmP + 146829U, // BAsmZ + 1229128U, // BC + 2296045U, // BCAsm + 3326280U, // BCR + 306393585U, // BCRAsm + 47828U, // BCT + 39291U, // BCTG + 33600531U, // BCTGR + 33600886U, // BCTR + 140112U, // BI + 134629U, // BIAsmE + 138201U, // BIAsmH + 133999U, // BIAsmHE + 140930U, // BIAsmL + 134889U, // BIAsmLE + 138477U, // BIAsmLH + 141939U, // BIAsmM + 135671U, // BIAsmNE + 139390U, // BIAsmNH + 134234U, // BIAsmNHE + 141212U, // BIAsmNL + 135130U, // BIAsmNLE + 138765U, // BIAsmNLH + 142057U, // BIAsmNM + 142540U, // BIAsmNO + 143022U, // BIAsmNP + 147006U, // BIAsmNZ + 142415U, // BIAsmO + 142909U, // BIAsmP + 146890U, // BIAsmZ + 1229252U, // BIC + 2296097U, // BICAsm + 340995859U, // BPP + 2488479565U, // BPRP + 6336534U, // BR + 369145782U, // BRAS + 369142111U, // BRASL + 6337182U, // BRAsmE + 6337581U, // BRAsmH + 6337230U, // BRAsmHE + 6337723U, // BRAsmL + 6337249U, // BRAsmLE + 6337652U, // BRAsmLH + 6337842U, // BRAsmM + 6337273U, // BRAsmNE + 6337671U, // BRAsmNH + 6337236U, // BRAsmNHE + 6337798U, // BRAsmNL + 6337255U, // BRAsmNLE + 6337664U, // BRAsmNLH + 6337847U, // BRAsmNM + 6337863U, // BRAsmNO + 6337879U, // BRAsmNP + 6338469U, // BRAsmNZ + 6337858U, // BRAsmO + 6337869U, // BRAsmP + 6338457U, // BRAsmZ + 403882461U, // BRC + 307431826U, // BRCAsm + 403882400U, // BRCL + 307439117U, // BRCLAsm + 402701025U, // BRCT + 402692496U, // BRCTG + 402694734U, // BRCTH + 2181079778U, // BRXH + 2181076987U, // BRXHG + 2181075307U, // BRXLE + 2181077140U, // BRXLG + 67142035U, // BSA + 67148106U, // BSG + 67152790U, // BSM + 2181079767U, // BXH + 2181076981U, // BXHG + 2181075301U, // BXLE + 2181076908U, // BXLEG + 268470490U, // C + 268470735U, // CD + 268468777U, // CDB + 67153947U, // CDBR + 67154198U, // CDFBR + 436240580U, // CDFBRA + 67154743U, // CDFR + 436254256U, // CDFTR + 67154243U, // CDGBR + 436240604U, // CDGBRA + 67154877U, // CDGR + 67155534U, // CDGTR + 436240722U, // CDGTRA + 436252964U, // CDLFBR + 436254263U, // CDLFTR + 436253009U, // CDLGBR + 436254293U, // CDLGTR + 469810017U, // CDPT + 67154460U, // CDR + 2181085506U, // CDS + 2181077332U, // CDSG + 67155582U, // CDSTR + 2181086585U, // CDSY + 67155366U, // CDTR + 67155603U, // CDUTR + 469810152U, // CDZT + 268470941U, // CE + 268469199U, // CEB + 67154079U, // CEBR + 67155378U, // CEDTR + 67154205U, // CEFBR + 436240588U, // CEFBRA + 67154763U, // CEFR + 67154250U, // CEGBR + 436240612U, // CEGBRA + 67154889U, // CEGR + 436252972U, // CELFBR + 436253017U, // CELGBR + 67154596U, // CER + 67155637U, // CEXTR + 6359307U, // CFC + 436252718U, // CFDBR + 436240532U, // CFDBRA + 436253235U, // CFDR + 436254158U, // CFDTR + 436252858U, // CFEBR + 436240556U, // CFEBRA + 436253378U, // CFER + 503358330U, // CFI + 436253086U, // CFXBR + 436240644U, // CFXBRA + 436254543U, // CFXR + 436254410U, // CFXTR + 268474204U, // CG + 436252733U, // CGDBR + 436240540U, // CGDBRA + 436253241U, // CGDR + 436254173U, // CGDTR + 436240700U, // CGDTRA + 436252873U, // CGEBR + 436240564U, // CGEBRA + 436253384U, // CGER + 268473390U, // CGF + 503358341U, // CGFI + 67154776U, // CGFR + 536914099U, // CGFRL + 268475171U, // CGH + 570467288U, // CGHI + 536914176U, // CGHRL + 134292560U, // CGHSI + 611565898U, // CGIB + 2785051889U, // CGIBAsm + 637569634U, // CGIBAsmE + 637573690U, // CGIBAsmH + 637569765U, // CGIBAsmHE + 637576642U, // CGIBAsmL + 637570658U, // CGIBAsmLE + 637574245U, // CGIBAsmLH + 637571454U, // CGIBAsmNE + 637575172U, // CGIBAsmNH + 637570010U, // CGIBAsmNHE + 637576994U, // CGIBAsmNL + 637570906U, // CGIBAsmNLE + 637574541U, // CGIBAsmNLH + 678674911U, // CGIJ + 2785059986U, // CGIJAsm + 2785054223U, // CGIJAsmE + 2785057823U, // CGIJAsmH + 2785053593U, // CGIJAsmHE + 2785060519U, // CGIJAsmL + 2785054483U, // CGIJAsmLE + 2785058096U, // CGIJAsmLH + 2785055265U, // CGIJAsmNE + 2785058984U, // CGIJAsmNH + 2785053833U, // CGIJAsmNHE + 2785060806U, // CGIJAsmNL + 2785054729U, // CGIJAsmNLE + 2785058364U, // CGIJAsmNLH + 8634988U, // CGIT + 2717956915U, // CGITAsm + 570463055U, // CGITAsmE + 570466922U, // CGITAsmH + 570461613U, // CGITAsmHE + 570468782U, // CGITAsmL + 570462509U, // CGITAsmLE + 570466180U, // CGITAsmLH + 570462894U, // CGITAsmNE + 570466613U, // CGITAsmNH + 570461472U, // CGITAsmNHE + 570468435U, // CGITAsmNL + 570462368U, // CGITAsmNLE + 570466010U, // CGITAsmNLH + 67154865U, // CGR + 2487468392U, // CGRB + 2214626781U, // CGRBAsm + 2214627966U, // CGRBAsmE + 2214632027U, // CGRBAsmH + 2214628101U, // CGRBAsmHE + 2214634974U, // CGRBAsmL + 2214628994U, // CGRBAsmLE + 2214632581U, // CGRBAsmLH + 2214629790U, // CGRBAsmNE + 2214633508U, // CGRBAsmNH + 2214628350U, // CGRBAsmNHE + 2214635330U, // CGRBAsmNL + 2214629246U, // CGRBAsmNLE + 2214632881U, // CGRBAsmNLH + 339984883U, // CGRJ + 2214634666U, // CGRJAsm + 2214628907U, // CGRJAsmE + 2214632507U, // CGRJAsmH + 2214628281U, // CGRJAsmHE + 2214635203U, // CGRJAsmL + 2214629171U, // CGRJAsmLE + 2214632784U, // CGRJAsmLH + 2214629953U, // CGRJAsmNE + 2214633672U, // CGRJAsmNH + 2214628525U, // CGRJAsmNHE + 2214635494U, // CGRJAsmNL + 2214629421U, // CGRJAsmNLE + 2214633056U, // CGRJAsmNLH + 536914124U, // CGRL + 306430595U, // CGRT + 2214640509U, // CGRTAsm + 67146608U, // CGRTAsmE + 67150469U, // CGRTAsmH + 67145164U, // CGRTAsmHE + 67152329U, // CGRTAsmL + 67146060U, // CGRTAsmLE + 67149731U, // CGRTAsmLH + 67146445U, // CGRTAsmNE + 67150164U, // CGRTAsmNH + 67145027U, // CGRTAsmNHE + 67151986U, // CGRTAsmNL + 67145923U, // CGRTAsmNLE + 67149565U, // CGRTAsmNLH + 436253101U, // CGXBR + 436240652U, // CGXBRA + 436254549U, // CGXR + 436254425U, // CGXTR + 436240752U, // CGXTRA + 268474996U, // CH + 268473482U, // CHF + 67155017U, // CHHR + 134292575U, // CHHSI + 570467275U, // CHI + 67155158U, // CHLR + 536914152U, // CHRL + 134292546U, // CHSI + 268483842U, // CHY + 611565894U, // CIB + 2785051877U, // CIBAsm + 637569628U, // CIBAsmE + 637573684U, // CIBAsmH + 637569758U, // CIBAsmHE + 637576636U, // CIBAsmL + 637570651U, // CIBAsmLE + 637574238U, // CIBAsmLH + 637571447U, // CIBAsmNE + 637575165U, // CIBAsmNH + 637570002U, // CIBAsmNHE + 637576987U, // CIBAsmNL + 637570898U, // CIBAsmNLE + 637574533U, // CIBAsmNLH + 503356382U, // CIH + 678674907U, // CIJ + 2785059981U, // CIJAsm + 2785054217U, // CIJAsmE + 2785057817U, // CIJAsmH + 2785053586U, // CIJAsmHE + 2785060513U, // CIJAsmL + 2785054476U, // CIJAsmLE + 2785058089U, // CIJAsmLH + 2785055258U, // CIJAsmNE + 2785058977U, // CIJAsmNH + 2785053825U, // CIJAsmNHE + 2785060799U, // CIJAsmNL + 2785054721U, // CIJAsmNLE + 2785058356U, // CIJAsmNLH + 8634978U, // CIT + 2717956903U, // CITAsm + 570463041U, // CITAsmE + 570466908U, // CITAsmH + 570461597U, // CITAsmHE + 570468768U, // CITAsmL + 570462493U, // CITAsmLE + 570466164U, // CITAsmLH + 570462878U, // CITAsmNE + 570466597U, // CITAsmNH + 570461454U, // CITAsmNHE + 570468419U, // CITAsmNL + 570462350U, // CITAsmNLE + 570465992U, // CITAsmNLH + 67152796U, // CKSM + 268477942U, // CL + 604080455U, // CLC + 67151354U, // CLCL + 2214629019U, // CLCLE + 2214640646U, // CLCLU + 436252725U, // CLFDBR + 436254165U, // CLFDTR + 436252865U, // CLFEBR + 704717896U, // CLFHSI + 738239405U, // CLFI + 9683558U, // CLFIT + 2919283500U, // CLFITAsm + 771789639U, // CLFITAsmE + 771793506U, // CLFITAsmH + 771788196U, // CLFITAsmHE + 771795366U, // CLFITAsmL + 771789092U, // CLFITAsmLE + 771792763U, // CLFITAsmLH + 771789477U, // CLFITAsmNE + 771793196U, // CLFITAsmNH + 771788054U, // CLFITAsmNHE + 771795018U, // CLFITAsmNL + 771788950U, // CLFITAsmNLE + 771792592U, // CLFITAsmNLH + 436253093U, // CLFXBR + 436254417U, // CLFXTR + 268474420U, // CLG + 436252740U, // CLGDBR + 436254180U, // CLGDTR + 436252880U, // CLGEBR + 268473408U, // CLGF + 738239378U, // CLGFI + 67154789U, // CLGFR + 536914106U, // CLGFRL + 536914183U, // CLGHRL + 704717911U, // CLGHSI + 614711631U, // CLGIB + 2952824055U, // CLGIBAsm + 805341801U, // CLGIBAsmE + 805345857U, // CLGIBAsmH + 805341933U, // CLGIBAsmHE + 805348809U, // CLGIBAsmL + 805342826U, // CLGIBAsmLE + 805346413U, // CLGIBAsmLH + 805343622U, // CLGIBAsmNE + 805347340U, // CLGIBAsmNH + 805342179U, // CLGIBAsmNHE + 805349162U, // CLGIBAsmNL + 805343075U, // CLGIBAsmNLE + 805346710U, // CLGIBAsmNLH + 681820644U, // CLGIJ + 2952832152U, // CLGIJAsm + 2952826390U, // CLGIJAsmE + 2952829990U, // CLGIJAsmH + 2952825761U, // CLGIJAsmHE + 2952832686U, // CLGIJAsmL + 2952826651U, // CLGIJAsmLE + 2952830264U, // CLGIJAsmLH + 2952827433U, // CLGIJAsmNE + 2952831152U, // CLGIJAsmNH + 2952826002U, // CLGIJAsmNHE + 2952832974U, // CLGIJAsmNL + 2952826898U, // CLGIJAsmNLE + 2952830533U, // CLGIJAsmNLH + 9683569U, // CLGIT + 2919283513U, // CLGITAsm + 771789654U, // CLGITAsmE + 771793521U, // CLGITAsmH + 771788213U, // CLGITAsmHE + 771795381U, // CLGITAsmL + 771789109U, // CLGITAsmLE + 771792780U, // CLGITAsmLH + 771789494U, // CLGITAsmNE + 771793213U, // CLGITAsmNH + 771788073U, // CLGITAsmNHE + 771795035U, // CLGITAsmNL + 771788969U, // CLGITAsmNLE + 771792611U, // CLGITAsmNLH + 67154901U, // CLGR + 2487468397U, // CLGRB + 2214626787U, // CLGRBAsm + 2214627973U, // CLGRBAsmE + 2214632034U, // CLGRBAsmH + 2214628109U, // CLGRBAsmHE + 2214634981U, // CLGRBAsmL + 2214629002U, // CLGRBAsmLE + 2214632589U, // CLGRBAsmLH + 2214629798U, // CLGRBAsmNE + 2214633516U, // CLGRBAsmNH + 2214628359U, // CLGRBAsmNHE + 2214635338U, // CLGRBAsmNL + 2214629255U, // CLGRBAsmNLE + 2214632890U, // CLGRBAsmNLH + 339984888U, // CLGRJ + 2214634672U, // CLGRJAsm + 2214628914U, // CLGRJAsmE + 2214632514U, // CLGRJAsmH + 2214628289U, // CLGRJAsmHE + 2214635210U, // CLGRJAsmL + 2214629179U, // CLGRJAsmLE + 2214632792U, // CLGRJAsmLH + 2214629961U, // CLGRJAsmNE + 2214633680U, // CLGRJAsmNH + 2214628534U, // CLGRJAsmNHE + 2214635502U, // CLGRJAsmNL + 2214629430U, // CLGRJAsmNLE + 2214633065U, // CLGRJAsmNLH + 536914130U, // CLGRL + 306430600U, // CLGRT + 2214640515U, // CLGRTAsm + 67146615U, // CLGRTAsmE + 67150476U, // CLGRTAsmH + 67145172U, // CLGRTAsmHE + 67152336U, // CLGRTAsmL + 67146068U, // CLGRTAsmLE + 67149739U, // CLGRTAsmLH + 67146453U, // CLGRTAsmNE + 67150172U, // CLGRTAsmNH + 67145036U, // CLGRTAsmNHE + 67151994U, // CLGRTAsmNL + 67145932U, // CLGRTAsmNLE + 67149574U, // CLGRTAsmNLH + 279133U, // CLGT + 2986392347U, // CLGTAsm + 872452922U, // CLGTAsmE + 872456789U, // CLGTAsmH + 872451477U, // CLGTAsmHE + 872458649U, // CLGTAsmL + 872452373U, // CLGTAsmLE + 872456044U, // CLGTAsmLH + 872452758U, // CLGTAsmNE + 872456477U, // CLGTAsmNH + 872451333U, // CLGTAsmNHE + 872458299U, // CLGTAsmNL + 872452229U, // CLGTAsmNLE + 872455871U, // CLGTAsmNLH + 436253108U, // CLGXBR + 436254432U, // CLGXTR + 268473526U, // CLHF + 67155053U, // CLHHR + 704717926U, // CLHHSI + 67155194U, // CLHLR + 536914199U, // CLHRL + 906044432U, // CLI + 614711637U, // CLIB + 2952824062U, // CLIBAsm + 805341809U, // CLIBAsmE + 805345865U, // CLIBAsmH + 805341942U, // CLIBAsmHE + 805348817U, // CLIBAsmL + 805342835U, // CLIBAsmLE + 805346422U, // CLIBAsmLH + 805343631U, // CLIBAsmNE + 805347349U, // CLIBAsmNH + 805342189U, // CLIBAsmNHE + 805349171U, // CLIBAsmNL + 805343085U, // CLIBAsmNLE + 805346720U, // CLIBAsmNLH + 738237444U, // CLIH + 681820650U, // CLIJ + 2952832159U, // CLIJAsm + 2952826398U, // CLIJAsmE + 2952829998U, // CLIJAsmH + 2952825770U, // CLIJAsmHE + 2952832694U, // CLIJAsmL + 2952826660U, // CLIJAsmLE + 2952830273U, // CLIJAsmLH + 2952827442U, // CLIJAsmNE + 2952831161U, // CLIJAsmNH + 2952826012U, // CLIJAsmNHE + 2952832983U, // CLIJAsmNL + 2952826908U, // CLIJAsmNLE + 2952830543U, // CLIJAsmNLH + 906050844U, // CLIY + 436251297U, // CLM + 436248549U, // CLMH + 436256096U, // CLMY + 67155136U, // CLR + 2487468403U, // CLRB + 2214626794U, // CLRBAsm + 2214627981U, // CLRBAsmE + 2214632042U, // CLRBAsmH + 2214628118U, // CLRBAsmHE + 2214634989U, // CLRBAsmL + 2214629011U, // CLRBAsmLE + 2214632598U, // CLRBAsmLH + 2214629807U, // CLRBAsmNE + 2214633525U, // CLRBAsmNH + 2214628369U, // CLRBAsmNHE + 2214635347U, // CLRBAsmNL + 2214629265U, // CLRBAsmNLE + 2214632900U, // CLRBAsmNLH + 339984894U, // CLRJ + 2214634679U, // CLRJAsm + 2214628922U, // CLRJAsmE + 2214632522U, // CLRJAsmH + 2214628298U, // CLRJAsmHE + 2214635218U, // CLRJAsmL + 2214629188U, // CLRJAsmLE + 2214632801U, // CLRJAsmLH + 2214629970U, // CLRJAsmNE + 2214633689U, // CLRJAsmNH + 2214628544U, // CLRJAsmNHE + 2214635511U, // CLRJAsmNL + 2214629440U, // CLRJAsmNLE + 2214633075U, // CLRJAsmNLH + 536914220U, // CLRL + 306430606U, // CLRT + 2214640522U, // CLRTAsm + 67146623U, // CLRTAsmE + 67150484U, // CLRTAsmH + 67145181U, // CLRTAsmHE + 67152344U, // CLRTAsmL + 67146077U, // CLRTAsmLE + 67149748U, // CLRTAsmLH + 67146462U, // CLRTAsmNE + 67150181U, // CLRTAsmNH + 67145046U, // CLRTAsmNHE + 67152003U, // CLRTAsmNL + 67145942U, // CLRTAsmNLE + 67149584U, // CLRTAsmNLH + 67156893U, // CLST + 279159U, // CLT + 2986392384U, // CLTAsm + 872452958U, // CLTAsmE + 872456825U, // CLTAsmH + 872451518U, // CLTAsmHE + 872458685U, // CLTAsmL + 872452414U, // CLTAsmLE + 872456085U, // CLTAsmLH + 872452799U, // CLTAsmNE + 872456518U, // CLTAsmNH + 872451379U, // CLTAsmNHE + 872458340U, // CLTAsmNL + 872452275U, // CLTAsmNLE + 872455917U, // CLTAsmNLH + 268483900U, // CLY + 67144112U, // CMPSC + 234991008U, // CP + 469809915U, // CPDT + 2181083769U, // CPSDRdd + 2181083769U, // CPSDRds + 2181083769U, // CPSDRsd + 2181083769U, // CPSDRss + 469810134U, // CPXT + 67142062U, // CPYA + 67154418U, // CR + 2487468388U, // CRB + 2214626776U, // CRBAsm + 2214627960U, // CRBAsmE + 2214632021U, // CRBAsmH + 2214628094U, // CRBAsmHE + 2214634968U, // CRBAsmL + 2214628987U, // CRBAsmLE + 2214632574U, // CRBAsmLH + 2214629783U, // CRBAsmNE + 2214633501U, // CRBAsmNH + 2214628342U, // CRBAsmNHE + 2214635323U, // CRBAsmNL + 2214629238U, // CRBAsmNLE + 2214632873U, // CRBAsmNLH + 2181075763U, // CRDTE + 2181075763U, // CRDTEOpt + 339984879U, // CRJ + 2214634661U, // CRJAsm + 2214628901U, // CRJAsmE + 2214632501U, // CRJAsmH + 2214628274U, // CRJAsmHE + 2214635197U, // CRJAsmL + 2214629164U, // CRJAsmLE + 2214632777U, // CRJAsmLH + 2214629946U, // CRJAsmNE + 2214633665U, // CRJAsmNH + 2214628517U, // CRJAsmNHE + 2214635487U, // CRJAsmNL + 2214629413U, // CRJAsmNLE + 2214633048U, // CRJAsmNLH + 536914080U, // CRL + 306430591U, // CRT + 2214640504U, // CRTAsm + 67146602U, // CRTAsmE + 67150463U, // CRTAsmH + 67145157U, // CRTAsmHE + 67152323U, // CRTAsmL + 67146053U, // CRTAsmLE + 67149724U, // CRTAsmLH + 67146438U, // CRTAsmNE + 67150157U, // CRTAsmNH + 67145019U, // CRTAsmNHE + 67151979U, // CRTAsmNL + 67145915U, // CRTAsmNLE + 67149557U, // CRTAsmNLH + 2181085502U, // CS + 16803U, // CSCH + 2214639110U, // CSDTR + 2181077327U, // CSG + 33599332U, // CSP + 33593587U, // CSPG + 3087088553U, // CSST + 2214639362U, // CSXTR + 2181086580U, // CSY + 2214625293U, // CU12 + 67141645U, // CU12Opt + 2214625305U, // CU14 + 67141657U, // CU14Opt + 2214625281U, // CU21 + 67141633U, // CU21Opt + 2214625311U, // CU24 + 67141663U, // CU24Opt + 67141639U, // CU41 + 67141651U, // CU42 + 67155483U, // CUDTR + 67146535U, // CUSE + 2214640632U, // CUTFU + 67156984U, // CUTFUOpt + 2214631021U, // CUUTF + 67147373U, // CUUTFOpt + 67155735U, // CUXTR + 34716U, // CVB + 38739U, // CVBG + 48317U, // CVBY + 268470844U, // CVD + 268474259U, // CVDG + 268483801U, // CVDY + 67154314U, // CXBR + 67154236U, // CXFBR + 436240596U, // CXFBRA + 67154845U, // CXFR + 436254279U, // CXFTR + 67154281U, // CXGBR + 436240620U, // CXGBRA + 67154983U, // CXGR + 67155564U, // CXGTR + 436240730U, // CXGTRA + 436252980U, // CXLFBR + 436254271U, // CXLFTR + 436253025U, // CXLGBR + 436254308U, // CXLGTR + 469810034U, // CXPT + 67155774U, // CXR + 67155596U, // CXSTR + 67155624U, // CXTR + 67155610U, // CXUTR + 469810158U, // CXZT + 268483780U, // CY + 469809927U, // CZDT + 469810146U, // CZXT + 35276U, // D + 35283U, // DD + 33350U, // DDB + 33599521U, // DDBR + 33600033U, // DDR + 2214639020U, // DDTR + 2214625589U, // DDTRA + 35510U, // DE + 33750U, // DEB + 33599654U, // DEBR + 33600171U, // DER + 2214627582U, // DFLTCC + 2214631163U, // DIAG + 2214637644U, // DIDBR + 2214637784U, // DIEBR + 42523U, // DL + 38971U, // DLG + 33600475U, // DLGR + 33600709U, // DLR + 234991029U, // DP + 33600017U, // DR + 39253U, // DSG + 37986U, // DSGF + 33600392U, // DSGFR + 33600519U, // DSGR + 33599889U, // DXBR + 33601348U, // DXR + 2214639279U, // DXTR + 2214625641U, // DXTRA + 67153903U, // EAR + 2214631157U, // ECAG + 67155324U, // ECCTR + 67141717U, // ECPGA + 3087079809U, // ECTG + 604080601U, // ED + 604087574U, // EDMK + 67155385U, // EEDTR + 67155644U, // EEXTR + 6326649U, // EFPC + 6337690U, // EPAIR + 6336508U, // EPAR + 67155345U, // EPCTR + 67157105U, // EPSW + 67147699U, // EREG + 67147718U, // EREGG + 6337697U, // ESAIR + 6336514U, // ESAR + 67155469U, // ESDTR + 6324285U, // ESEA + 67142046U, // ESTA + 67155721U, // ESXTR + 6326797U, // ETND + 268483721U, // EX + 536914265U, // EXRL + 436252755U, // FIDBR + 436240548U, // FIDBRA + 67154507U, // FIDR + 436254188U, // FIDTR + 436252895U, // FIEBR + 436240572U, // FIEBRA + 67154651U, // FIER + 436253116U, // FIXBR + 436240660U, // FIXBRA + 67155803U, // FIXR + 436254440U, // FIXTR + 67154938U, // FLOGR + 67154502U, // HDR + 67154639U, // HER + 16808U, // HSCH + 6326488U, // IAC + 35106U, // IC + 35106U, // IC32 + 48323U, // IC32Y + 973122086U, // ICM + 973119427U, // ICMH + 973126995U, // ICMY + 48323U, // ICY + 2181075757U, // IDTE + 2181075757U, // IDTEOpt + 2181084608U, // IEDTR + 2181084867U, // IEXTR + 738235535U, // IIHF + 704682875U, // IIHH + 704685667U, // IIHL + 738235680U, // IILF + 704683280U, // IILH + 704685791U, // IILL + 16899U, // IPK + 6335309U, // IPM + 2214630244U, // IPTE + 2214630244U, // IPTEOpt + 67146596U, // IPTEOptOpt + 67152410U, // IRBM + 33590856U, // ISKE + 33596837U, // IVSK + 6602464U, // InsnE + 3158654785U, // InsnRI + 1011203817U, // InsnRIE + 3158687606U, // InsnRIL + 1011204063U, // InsnRILU + 3158687658U, // InsnRIS + 11845516U, // InsnRR + 1011171060U, // InsnRRE + 1011171104U, // InsnRRF + 1011204031U, // InsnRRS + 1011171253U, // InsnRS + 1011203839U, // InsnRSE + 1011203936U, // InsnRSI + 1011204118U, // InsnRSY + 1011171318U, // InsnRX + 1011203861U, // InsnRXE + 1011203894U, // InsnRXF + 1011204129U, // InsnRXY + 314916769U, // InsnS + 1019559766U, // InsnSI + 3167076225U, // InsnSIL + 1019592715U, // InsnSIY + 14008277U, // InsnSS + 3167076106U, // InsnSSE + 3167076139U, // InsnSSF + 1011203915U, // InsnVRI + 1011203990U, // InsnVRR + 15056842U, // InsnVRS + 3158687723U, // InsnVRV + 1011204096U, // InsnVRX + 1011203947U, // InsnVSI + 402575U, // J + 396811U, // JAsmE + 400411U, // JAsmH + 396180U, // JAsmHE + 403107U, // JAsmL + 397070U, // JAsmLE + 400683U, // JAsmLH + 404121U, // JAsmM + 397852U, // JAsmNE + 401571U, // JAsmNH + 396419U, // JAsmNHE + 403393U, // JAsmNL + 397315U, // JAsmNLE + 400950U, // JAsmNLH + 404236U, // JAsmNM + 404719U, // JAsmNO + 405201U, // JAsmNP + 409185U, // JAsmNZ + 404590U, // JAsmO + 405090U, // JAsmP + 409065U, // JAsmZ + 399385U, // JG + 395993U, // JGAsmE + 400183U, // JGAsmH + 396118U, // JGAsmHE + 403008U, // JGAsmL + 397008U, // JGAsmLE + 400581U, // JGAsmLH + 404056U, // JGAsmM + 397790U, // JGAsmNE + 401509U, // JGAsmNH + 396350U, // JGAsmNHE + 403331U, // JGAsmNL + 397246U, // JGAsmNLE + 400881U, // JGAsmNLH + 404176U, // JGAsmNM + 404659U, // JGAsmNO + 405141U, // JGAsmNP + 409125U, // JGAsmNZ + 404537U, // JGAsmO + 405009U, // JGAsmP + 409012U, // JGAsmZ + 268468996U, // KDB + 67154010U, // KDBR + 6717848U, // KDSA + 67155443U, // KDTR + 268469267U, // KEB + 67154150U, // KEBR + 6720001U, // KIMD + 6720007U, // KLMD + 67152541U, // KM + 2181070971U, // KMA + 6719709U, // KMAC + 67144022U, // KMC + 2181084554U, // KMCTR + 67147172U, // KMF + 67153028U, // KMO + 67154371U, // KXBR + 67155695U, // KXTR + 268477870U, // L + 268468330U, // LA + 2214625324U, // LAA + 2214631151U, // LAAG + 2214634923U, // LAAL + 2214631459U, // LAALG + 268470865U, // LAE + 268483807U, // LAEY + 2214636041U, // LAM + 2214640966U, // LAMY + 2214636488U, // LAN + 2214631618U, // LANG + 2214636558U, // LAO + 2214631630U, // LAOG + 536914072U, // LARL + 939601758U, // LASP + 268483271U, // LAT + 2214640765U, // LAX + 2214631917U, // LAXG + 268483757U, // LAY + 268469519U, // LB + 6369261U, // LBEAR + 268474960U, // LBH + 67154289U, // LBR + 2415952336U, // LCBB + 6367607U, // LCCTL + 67153946U, // LCDBR + 67154742U, // LCDFR + 67154742U, // LCDFR_32 + 67154459U, // LCDR + 67154078U, // LCEBR + 67154595U, // LCER + 67154775U, // LCGFR + 67154864U, // LCGR + 67154430U, // LCR + 2214635902U, // LCTL + 2214631558U, // LCTLG + 67154313U, // LCXBR + 67155773U, // LCXR + 268470775U, // LD + 268470965U, // LDE + 268470965U, // LDE32 + 268469205U, // LDEB + 67154085U, // LDEBR + 67154608U, // LDER + 2214639145U, // LDETR + 67154883U, // LDGR + 67154513U, // LDR + 67154513U, // LDR32 + 67154320U, // LDXBR + 436240628U, // LDXBRA + 67155779U, // LDXR + 436254382U, // LDXTR + 268483790U, // LDY + 268471895U, // LE + 67153959U, // LEDBR + 436240524U, // LEDBRA + 67154477U, // LEDR + 436254151U, // LEDTR + 67154658U, // LER + 67154327U, // LEXBR + 436240636U, // LEXBRA + 67155785U, // LEXR + 268483813U, // LEY + 6371248U, // LFAS + 268475153U, // LFH + 268483264U, // LFHAT + 6359423U, // LFPC + 268474406U, // LG + 268483258U, // LGAT + 268469386U, // LGB + 67154259U, // LGBR + 67154495U, // LGDR + 268473403U, // LGF + 503358348U, // LGFI + 67154783U, // LGFR + 536914107U, // LGFRL + 268474317U, // LGG + 268475197U, // LGH + 570467294U, // LGHI + 67155011U, // LGHR + 536914184U, // LGHRL + 67154896U, // LGR + 536914131U, // LGRL + 268470686U, // LGSC + 268475482U, // LH + 268475287U, // LHH + 570467328U, // LHI + 67155061U, // LHR + 536914200U, // LHRL + 268483847U, // LHY + 268470604U, // LLC + 268475012U, // LLCH + 67154435U, // LLCR + 268470549U, // LLGC + 67154422U, // LLGCR + 268473414U, // LLGF + 268483250U, // LLGFAT + 67154796U, // LLGFR + 536914114U, // LLGFRL + 268474714U, // LLGFSG + 268475196U, // LLGH + 67155010U, // LLGHR + 536914191U, // LLGHRL + 268483361U, // LLGT + 268483276U, // LLGTAT + 67155549U, // LLGTR + 268475756U, // LLH + 268475292U, // LLHH + 67155066U, // LLHR + 536914206U, // LLHRL + 738235541U, // LLIHF + 771791745U, // LLIHH + 771794537U, // LLIHL + 738235686U, // LLILF + 771792150U, // LLILH + 771794661U, // LLILL + 268473434U, // LLZRGF + 2214636194U, // LM + 2214627848U, // LMD + 2214631600U, // LMG + 2214633446U, // LMH + 2214640993U, // LMY + 67154022U, // LNDBR + 67154749U, // LNDFR + 67154749U, // LNDFR_32 + 67154523U, // LNDR + 67154156U, // LNEBR + 67154687U, // LNER + 67154810U, // LNGFR + 67154932U, // LNGR + 67155261U, // LNR + 67154383U, // LNXBR + 67155819U, // LNXR + 475516U, // LOC + 3087042921U, // LOCAsm + 939559591U, // LOCAsmE + 939563664U, // LOCAsmH + 939559717U, // LOCAsmHE + 939566592U, // LOCAsmL + 939560610U, // LOCAsmLE + 939564197U, // LOCAsmLH + 939567659U, // LOCAsmM + 939561399U, // LOCAsmNE + 939565117U, // LOCAsmNH + 939559962U, // LOCAsmNHE + 939566939U, // LOCAsmNL + 939560858U, // LOCAsmNLE + 939564493U, // LOCAsmNLH + 939567792U, // LOCAsmNM + 939568275U, // LOCAsmNO + 939568757U, // LOCAsmNP + 939572741U, // LOCAsmNZ + 939568157U, // LOCAsmO + 939568542U, // LOCAsmP + 939572625U, // LOCAsmZ + 475575U, // LOCFH + 3087047426U, // LOCFHAsm + 939559732U, // LOCFHAsmE + 939563882U, // LOCFHAsmH + 939559772U, // LOCFHAsmHE + 939566674U, // LOCFHAsmL + 939560662U, // LOCFHAsmLE + 939564250U, // LOCFHAsmLH + 939567714U, // LOCFHAsmM + 939561444U, // LOCFHAsmNE + 939565163U, // LOCFHAsmNH + 939560005U, // LOCFHAsmNHE + 939566985U, // LOCFHAsmNL + 939560901U, // LOCFHAsmNLE + 939564536U, // LOCFHAsmNLH + 939567830U, // LOCFHAsmNM + 939568313U, // LOCFHAsmNO + 939568795U, // LOCFHAsmNP + 939572779U, // LOCFHAsmNZ + 939568190U, // LOCFHAsmO + 939568676U, // LOCFHAsmP + 939572665U, // LOCFHAsmZ + 318227015U, // LOCFHR + 2181084210U, // LOCFHRAsm + 33592066U, // LOCFHRAsmE + 33595906U, // LOCFHRAsmH + 33590649U, // LOCFHRAsmHE + 33597678U, // LOCFHRAsmL + 33591545U, // LOCFHRAsmLE + 33595194U, // LOCFHRAsmLH + 33598333U, // LOCFHRAsmM + 33591930U, // LOCFHRAsmNE + 33595649U, // LOCFHRAsmNH + 33590502U, // LOCFHRAsmNHE + 33597471U, // LOCFHRAsmNL + 33591398U, // LOCFHRAsmNLE + 33595040U, // LOCFHRAsmNLH + 33598251U, // LOCFHRAsmNM + 33598740U, // LOCFHRAsmNO + 33599216U, // LOCFHRAsmNP + 33603200U, // LOCFHRAsmNZ + 33598815U, // LOCFHRAsmO + 33599284U, // LOCFHRAsmP + 33603260U, // LOCFHRAsmZ + 475541U, // LOCG + 3087046521U, // LOCGAsm + 939559626U, // LOCGAsmE + 939563809U, // LOCGAsmH + 939559749U, // LOCGAsmHE + 939566641U, // LOCGAsmL + 939560639U, // LOCGAsmLE + 939564212U, // LOCGAsmLH + 939567689U, // LOCGAsmM + 939561421U, // LOCGAsmNE + 939565140U, // LOCGAsmNH + 939559979U, // LOCGAsmNHE + 939566962U, // LOCGAsmNL + 939560875U, // LOCGAsmNLE + 939564510U, // LOCGAsmNLH + 939567807U, // LOCGAsmNM + 939568290U, // LOCGAsmNO + 939568772U, // LOCGAsmNP + 939572756U, // LOCGAsmNZ + 939568170U, // LOCGAsmO + 939568636U, // LOCGAsmP + 939572645U, // LOCGAsmZ + 17285581U, // LOCGHI + 2281743318U, // LOCGHIAsm + 134254066U, // LOCGHIAsmE + 134257650U, // LOCGHIAsmH + 134253438U, // LOCGHIAsmHE + 134260367U, // LOCGHIAsmL + 134254328U, // LOCGHIAsmLE + 134257916U, // LOCGHIAsmLH + 134261376U, // LOCGHIAsmM + 134255110U, // LOCGHIAsmNE + 134258829U, // LOCGHIAsmNH + 134253675U, // LOCGHIAsmNHE + 134260651U, // LOCGHIAsmNL + 134254571U, // LOCGHIAsmNLE + 134258206U, // LOCGHIAsmNLH + 134261496U, // LOCGHIAsmNM + 134261979U, // LOCGHIAsmNO + 134262461U, // LOCGHIAsmNP + 134266445U, // LOCGHIAsmNZ + 134261852U, // LOCGHIAsmO + 134262346U, // LOCGHIAsmP + 134266327U, // LOCGHIAsmZ + 318227003U, // LOCGR + 2181084086U, // LOCGRAsm + 33592050U, // LOCGRAsmE + 33595890U, // LOCGRAsmH + 33590631U, // LOCGRAsmHE + 33597642U, // LOCGRAsmL + 33591527U, // LOCGRAsmLE + 33595176U, // LOCGRAsmLH + 33598317U, // LOCGRAsmM + 33591912U, // LOCGRAsmNE + 33595631U, // LOCGRAsmNH + 33590482U, // LOCGRAsmNHE + 33597453U, // LOCGRAsmNL + 33591378U, // LOCGRAsmNLE + 33595020U, // LOCGRAsmNLH + 33598233U, // LOCGRAsmNM + 33598722U, // LOCGRAsmNO + 33599198U, // LOCGRAsmNP + 33603182U, // LOCGRAsmNZ + 33598799U, // LOCGRAsmO + 33599268U, // LOCGRAsmP + 33603244U, // LOCGRAsmZ + 17285588U, // LOCHHI + 2281743345U, // LOCHHIAsm + 134254075U, // LOCHHIAsmE + 134257659U, // LOCHHIAsmH + 134253448U, // LOCHHIAsmHE + 134260376U, // LOCHHIAsmL + 134254338U, // LOCHHIAsmLE + 134257926U, // LOCHHIAsmLH + 134261385U, // LOCHHIAsmM + 134255120U, // LOCHHIAsmNE + 134258839U, // LOCHHIAsmNH + 134253686U, // LOCHHIAsmNHE + 134260661U, // LOCHHIAsmNL + 134254582U, // LOCHHIAsmNLE + 134258217U, // LOCHHIAsmNLH + 134261506U, // LOCHHIAsmNM + 134261989U, // LOCHHIAsmNO + 134262471U, // LOCHHIAsmNP + 134266455U, // LOCHHIAsmNZ + 134261861U, // LOCHHIAsmO + 134262355U, // LOCHHIAsmP + 134266336U, // LOCHHIAsmZ + 17285575U, // LOCHI + 2281743305U, // LOCHIAsm + 134254058U, // LOCHIAsmE + 134257642U, // LOCHIAsmH + 134253429U, // LOCHIAsmHE + 134260359U, // LOCHIAsmL + 134254319U, // LOCHIAsmLE + 134257907U, // LOCHIAsmLH + 134261368U, // LOCHIAsmM + 134255101U, // LOCHIAsmNE + 134258820U, // LOCHIAsmNH + 134253665U, // LOCHIAsmNHE + 134260642U, // LOCHIAsmNL + 134254561U, // LOCHIAsmNLE + 134258196U, // LOCHIAsmNLH + 134261487U, // LOCHIAsmNM + 134261970U, // LOCHIAsmNO + 134262452U, // LOCHIAsmNP + 134266436U, // LOCHIAsmNZ + 134261844U, // LOCHIAsmO + 134262338U, // LOCHIAsmP + 134266319U, // LOCHIAsmZ + 318226998U, // LOCR + 2181083657U, // LOCRAsm + 33592043U, // LOCRAsmE + 33595868U, // LOCRAsmH + 33590623U, // LOCRAsmHE + 33597598U, // LOCRAsmL + 33591519U, // LOCRAsmLE + 33595168U, // LOCRAsmLH + 33598295U, // LOCRAsmM + 33591904U, // LOCRAsmNE + 33595623U, // LOCRAsmNH + 33590473U, // LOCRAsmNHE + 33597445U, // LOCRAsmNL + 33591369U, // LOCRAsmNLE + 33595011U, // LOCRAsmNLH + 33598225U, // LOCRAsmNM + 33598714U, // LOCRAsmNO + 33599190U, // LOCRAsmNP + 33603174U, // LOCRAsmNZ + 33598785U, // LOCRAsmO + 33599261U, // LOCRAsmP + 33603237U, // LOCRAsmZ + 6367620U, // LPCTL + 3019934227U, // LPD + 67154029U, // LPDBR + 67154756U, // LPDFR + 67154756U, // LPDFR_32 + 3019937676U, // LPDG + 67154529U, // LPDR + 67154163U, // LPEBR + 67154693U, // LPER + 67154817U, // LPGFR + 67154945U, // LPGR + 6369048U, // LPP + 268480456U, // LPQ + 67155282U, // LPR + 6372471U, // LPSW + 6362001U, // LPSWE + 6372592U, // LPSWEY + 2214625347U, // LPTEA + 67154390U, // LPXBR + 67155825U, // LPXR + 67155127U, // LR + 268468508U, // LRA + 268474127U, // LRAG + 268483767U, // LRAY + 67154541U, // LRDR + 67154705U, // LRER + 536914221U, // LRL + 268483652U, // LRV + 268474848U, // LRVG + 67154976U, // LRVGR + 268477130U, // LRVH + 67155752U, // LRVR + 6367627U, // LSCTL + 268483393U, // LT + 67154050U, // LTDBR + 67154050U, // LTDBRCompare + 67154560U, // LTDR + 67155476U, // LTDTR + 67154184U, // LTEBR + 67154184U, // LTEBRCompare + 67154717U, // LTER + 268474782U, // LTG + 268473454U, // LTGF + 67154838U, // LTGFR + 67154970U, // LTGR + 67155571U, // LTR + 67154410U, // LTXBR + 67154410U, // LTXBRCompare + 67155842U, // LTXR + 67155728U, // LTXTR + 67142022U, // LURA + 67147556U, // LURAG + 268470849U, // LXD + 268469172U, // LXDB + 67154057U, // LXDBR + 67154566U, // LXDR + 2214639138U, // LXDTR + 268473240U, // LXE + 268469326U, // LXEB + 67154191U, // LXEBR + 67154730U, // LXER + 67155809U, // LXR + 268483896U, // LY + 6337170U, // LZDR + 6337328U, // LZER + 268473917U, // LZRF + 268474692U, // LZRG + 6338440U, // LZXR + 43531U, // M + 2181073354U, // MAD + 2181071367U, // MADB + 2181083155U, // MADBR + 2181083663U, // MADR + 2181073495U, // MAE + 2181071816U, // MAEB + 2181083287U, // MAEBR + 2181083800U, // MAER + 2181086386U, // MAY + 2181079784U, // MAYH + 2181084301U, // MAYHR + 2181081590U, // MAYL + 2181084453U, // MAYLR + 2181085070U, // MAYR + 906037591U, // MC + 35331U, // MD + 33554U, // MDB + 33599584U, // MDBR + 35514U, // MDE + 33762U, // MDEB + 33599660U, // MDEBR + 33600182U, // MDER + 33600086U, // MDR + 2214639097U, // MDTR + 2214625604U, // MDTRA + 37235U, // ME + 35525U, // MEE + 33775U, // MEEB + 33599667U, // MEEBR + 33600188U, // MEER + 33600244U, // MER + 48376U, // MFY + 39070U, // MG + 39749U, // MGH + 134259684U, // MGHI + 2214634842U, // MGRK + 40901U, // MH + 134259717U, // MHI + 48396U, // MHY + 42775U, // ML + 39005U, // MLG + 33600488U, // MLGR + 33600769U, // MLR + 234991212U, // MP + 33600819U, // MR + 47747U, // MS + 35243U, // MSC + 6363813U, // MSCH + 2181073457U, // MSD + 2181071746U, // MSDB + 2181083259U, // MSDBR + 2181083763U, // MSDR + 2181075746U, // MSE + 2181071937U, // MSEB + 2181083393U, // MSEBR + 2181083927U, // MSER + 100705209U, // MSFI + 39281U, // MSG + 35099U, // MSGC + 37992U, // MSGF + 100705184U, // MSGFI + 33600399U, // MSGFR + 33600525U, // MSGR + 2214627635U, // MSGRKC + 33600881U, // MSR + 2214627643U, // MSRKC + 6324644U, // MSTA + 48511U, // MSY + 604080572U, // MVC + 939599072U, // MVCDK + 604089315U, // MVCIN + 533722U, // MVCK + 67151379U, // MVCL + 2214629041U, // MVCLE + 2214640653U, // MVCLU + 3087088270U, // MVCOS + 535979U, // MVCP + 939600037U, // MVCRL + 538940U, // MVCS + 939599262U, // MVCSK + 134292458U, // MVGHI + 134292473U, // MVHHI + 134292490U, // MVHI + 906044548U, // MVI + 906050860U, // MVIY + 604089353U, // MVN + 234990981U, // MVO + 67148025U, // MVPG + 67156911U, // MVST + 604094171U, // MVZ + 33599945U, // MXBR + 35398U, // MXD + 33722U, // MXDB + 33599632U, // MXDBR + 33600140U, // MXDR + 33601382U, // MXR + 2214639349U, // MXTR + 2214625656U, // MXTRA + 2214640968U, // MY + 2214634222U, // MYH + 2214638740U, // MYHR + 2214636028U, // MYL + 2214638892U, // MYLR + 2214639508U, // MYR + 43978U, // N + 604080480U, // NC + 2214634814U, // NCGRK + 2214634796U, // NCRK + 39108U, // NG + 33600501U, // NGR + 2214634849U, // NGRK + 906044437U, // NI + 18031430U, // NIAI + 201364636U, // NIHF + 704682888U, // NIHH + 704685680U, // NIHL + 201364781U, // NILF + 704683293U, // NILH + 704685804U, // NILL + 906050850U, // NIY + 2214634848U, // NNGRK + 16705U, // NNPA + 2214634887U, // NNRK + 2214634855U, // NOGRK + 16946U, // NOP_bare + 2214634893U, // NORK + 33600830U, // NR + 2214634888U, // NRK + 268474787U, // NTSTG + 2214634868U, // NXGRK + 2214634904U, // NXRK + 48492U, // NY + 44048U, // O + 604080490U, // OC + 2214634821U, // OCGRK + 2214634802U, // OCRK + 39120U, // OG + 33600508U, // OGR + 2214634856U, // OGRK + 906044441U, // OI + 201364642U, // OIHF + 704682894U, // OIHH + 704685686U, // OIHL + 201364787U, // OILF + 704683299U, // OILH + 704685810U, // OILL + 906050855U, // OIY + 33600835U, // OR + 2214634894U, // ORK + 48496U, // OY + 234988745U, // PACK + 16730U, // PALB + 6359419U, // PC + 16760U, // PCC + 16930U, // PCKMO + 2296285U, // PFD + 307439788U, // PFDRL + 6722960U, // PFMF + 16936U, // PFPO + 67152882U, // PGIN + 67156923U, // PGOUT + 1040253022U, // PKA + 1040268289U, // PKU + 3019943039U, // PLO + 67156812U, // POPCNT + 2214640460U, // POPCNTOpt + 2214625415U, // PPA + 67153140U, // PPNO + 16986U, // PR + 67153200U, // PRNO + 67156835U, // PT + 6329960U, // PTF + 16778U, // PTFF + 67150975U, // PTI + 16735U, // PTLB + 2214639007U, // QADTR + 2214639265U, // QAXTR + 6366249U, // QCTRI + 6366049U, // QPACI + 6366324U, // QSI + 16941U, // RCHP + 2181082560U, // RDP + 2181082560U, // RDPOpt + 2181076790U, // RISBG + 2181076790U, // RISBG32 + 2181082067U, // RISBGN + 2181076960U, // RISBHG + 2181077034U, // RISBLG + 2214635271U, // RLL + 2214631505U, // RLLG + 2181076797U, // RNSBG + 2181076804U, // ROSBG + 6369056U, // RP + 67144340U, // RRBE + 67152416U, // RRBM + 2214639103U, // RRDTR + 2214639355U, // RRXTR + 16813U, // RSCH + 2181076811U, // RXSBG + 47021U, // S + 6359267U, // SAC + 6362044U, // SACF + 16903U, // SAL + 16588U, // SAM24 + 16576U, // SAM31 + 16594U, // SAM64 + 67153923U, // SAR + 67155331U, // SCCTR + 16925U, // SCHM + 6366415U, // SCK + 6359334U, // SCKC + 16783U, // SCKPF + 35378U, // SD + 33652U, // SDB + 33599612U, // SDBR + 33600116U, // SDR + 2214639111U, // SDTR + 2214625611U, // SDTRA + 37667U, // SE + 33858U, // SEB + 33599746U, // SEBR + 351781454U, // SELFHR + 2181084218U, // SELFHRAsm + 2181075723U, // SELFHRAsmE + 2181079563U, // SELFHRAsmH + 2181074307U, // SELFHRAsmHE + 2181081335U, // SELFHRAsmL + 2181075203U, // SELFHRAsmLE + 2181078852U, // SELFHRAsmLH + 2181081990U, // SELFHRAsmM + 2181075588U, // SELFHRAsmNE + 2181079307U, // SELFHRAsmNH + 2181074161U, // SELFHRAsmNHE + 2181081129U, // SELFHRAsmNL + 2181075057U, // SELFHRAsmNLE + 2181078699U, // SELFHRAsmNLH + 2181081909U, // SELFHRAsmNM + 2181082398U, // SELFHRAsmNO + 2181082874U, // SELFHRAsmNP + 2181086858U, // SELFHRAsmNZ + 2181082472U, // SELFHRAsmO + 2181082941U, // SELFHRAsmP + 2181086917U, // SELFHRAsmZ + 351781441U, // SELGR + 2181084129U, // SELGRAsm + 2181075706U, // SELGRAsmE + 2181079546U, // SELGRAsmH + 2181074288U, // SELGRAsmHE + 2181081305U, // SELGRAsmL + 2181075184U, // SELGRAsmLE + 2181078833U, // SELGRAsmLH + 2181081973U, // SELGRAsmM + 2181075569U, // SELGRAsmNE + 2181079288U, // SELGRAsmNH + 2181074140U, // SELGRAsmNHE + 2181081110U, // SELGRAsmNL + 2181075036U, // SELGRAsmNLE + 2181078678U, // SELGRAsmNLH + 2181081890U, // SELGRAsmNM + 2181082379U, // SELGRAsmNO + 2181082855U, // SELGRAsmNP + 2181086839U, // SELGRAsmNZ + 2181082455U, // SELGRAsmO + 2181082924U, // SELGRAsmP + 2181086900U, // SELGRAsmZ + 351781461U, // SELR + 2181084362U, // SELRAsm + 2181075732U, // SELRAsmE + 2181079572U, // SELRAsmH + 2181074317U, // SELRAsmHE + 2181081394U, // SELRAsmL + 2181075213U, // SELRAsmLE + 2181078862U, // SELRAsmLH + 2181081999U, // SELRAsmM + 2181075598U, // SELRAsmNE + 2181079317U, // SELRAsmNH + 2181074172U, // SELRAsmNHE + 2181081139U, // SELRAsmNL + 2181075068U, // SELRAsmNLE + 2181078710U, // SELRAsmNLH + 2181081919U, // SELRAsmNM + 2181082408U, // SELRAsmNO + 2181082884U, // SELRAsmNP + 2181086868U, // SELRAsmNZ + 2181082481U, // SELRAsmO + 2181082950U, // SELRAsmP + 2181086926U, // SELRAsmZ + 33600280U, // SER + 6337898U, // SFASR + 6326661U, // SFPC + 39243U, // SG + 37987U, // SGF + 33600393U, // SGFR + 39754U, // SGH + 33600520U, // SGR + 2214634862U, // SGRK + 41516U, // SH + 2214638694U, // SHHHR + 2214638835U, // SHHLR + 48401U, // SHY + 6360580U, // SIE + 6357071U, // SIGA + 2214637067U, // SIGP + 43362U, // SL + 939556969U, // SLA + 2214631169U, // SLAG + 2214634685U, // SLAK + 34149U, // SLB + 38704U, // SLBG + 33600424U, // SLBGR + 33599856U, // SLBR + 939556913U, // SLDA + 939566617U, // SLDL + 2214640373U, // SLDT + 201368499U, // SLFI + 39034U, // SLG + 37964U, // SLGF + 201368473U, // SLGFI + 33600371U, // SLGFR + 33600494U, // SLGR + 2214634835U, // SLGRK + 2214638686U, // SLHHHR + 2214638827U, // SLHHLR + 939566860U, // SLL + 2214631511U, // SLLG + 2214634762U, // SLLK + 33600795U, // SLR + 2214634881U, // SLRK + 2214640592U, // SLXT + 48449U, // SLY + 67152351U, // SORTL + 234991456U, // SP + 67155352U, // SPCTR + 6357091U, // SPKA + 6335314U, // SPM + 6372199U, // SPT + 6372503U, // SPX + 268470808U, // SQD + 268469092U, // SQDB + 67154036U, // SQDBR + 67154535U, // SQDR + 268473062U, // SQE + 268469307U, // SQEB + 67154170U, // SQEBR + 67154699U, // SQER + 67154397U, // SQXBR + 67155831U, // SQXR + 33600870U, // SR + 939557155U, // SRA + 2214631191U, // SRAG + 2214634691U, // SRAK + 939556919U, // SRDA + 939566623U, // SRDL + 2214640385U, // SRDT + 2214634899U, // SRK + 939567431U, // SRL + 2214631538U, // SRLG + 2214634768U, // SRLK + 6368071U, // SRNM + 6358412U, // SRNMB + 6372165U, // SRNMT + 2751573844U, // SRP + 67156899U, // SRST + 67157016U, // SRSTU + 2214640604U, // SRXT + 6337704U, // SSAIR + 6336520U, // SSAR + 6363819U, // SSCH + 2214628942U, // SSKE + 67145294U, // SSKEOpt + 6368178U, // SSM + 268483487U, // ST + 2214636046U, // STAM + 2214640972U, // STAMY + 6368650U, // STAP + 6369268U, // STBEAR + 268470711U, // STC + 268475064U, // STCH + 6366420U, // STCK + 6359340U, // STCKC + 6360641U, // STCKE + 6362358U, // STCKF + 436251192U, // STCM + 436248521U, // STCMH + 436256089U, // STCMY + 6371989U, // STCPS + 6372458U, // STCRW + 2214631831U, // STCTG + 2214635922U, // STCTL + 268483784U, // STCY + 268470838U, // STD + 268483795U, // STDY + 268473228U, // STE + 268483818U, // STEY + 268475158U, // STFH + 6366763U, // STFL + 6360760U, // STFLE + 6359435U, // STFPC + 268474789U, // STG + 536914145U, // STGRL + 268470692U, // STGSC + 268477083U, // STH + 268475339U, // STHH + 536914213U, // STHRL + 268483862U, // STHY + 6368697U, // STIDP + 2214636472U, // STM + 2214631605U, // STMG + 2214633451U, // STMH + 2214640998U, // STMY + 906046370U, // STNSM + 315081088U, // STOC + 3019934062U, // STOCAsm + 872450733U, // STOCAsmE + 872454806U, // STOCAsmH + 872450860U, // STOCAsmHE + 872457734U, // STOCAsmL + 872451753U, // STOCAsmLE + 872455340U, // STOCAsmLH + 872458801U, // STOCAsmM + 872452542U, // STOCAsmNE + 872456260U, // STOCAsmNH + 872451106U, // STOCAsmNHE + 872458082U, // STOCAsmNL + 872452002U, // STOCAsmNLE + 872455637U, // STOCAsmNLH + 872458935U, // STOCAsmNM + 872459418U, // STOCAsmNO + 872459900U, // STOCAsmNP + 872463884U, // STOCAsmNZ + 872459299U, // STOCAsmO + 872459684U, // STOCAsmP + 872463767U, // STOCAsmZ + 315081149U, // STOCFH + 3019938569U, // STOCFHAsm + 872450876U, // STOCFHAsmE + 872455026U, // STOCFHAsmH + 872450917U, // STOCFHAsmHE + 872457818U, // STOCFHAsmL + 872451807U, // STOCFHAsmLE + 872455395U, // STOCFHAsmLH + 872458858U, // STOCFHAsmM + 872452589U, // STOCFHAsmNE + 872456308U, // STOCFHAsmNH + 872451151U, // STOCFHAsmNHE + 872458130U, // STOCFHAsmNL + 872452047U, // STOCFHAsmNLE + 872455682U, // STOCFHAsmNLH + 872458975U, // STOCFHAsmNM + 872459458U, // STOCFHAsmNO + 872459940U, // STOCFHAsmNP + 872463924U, // STOCFHAsmNZ + 872459334U, // STOCFHAsmO + 872459820U, // STOCFHAsmP + 872463809U, // STOCFHAsmZ + 315081114U, // STOCG + 3019937663U, // STOCGAsm + 872450769U, // STOCGAsmE + 872454952U, // STOCGAsmH + 872450893U, // STOCGAsmHE + 872457784U, // STOCGAsmL + 872451783U, // STOCGAsmLE + 872455356U, // STOCGAsmLH + 872458832U, // STOCGAsmM + 872452565U, // STOCGAsmNE + 872456284U, // STOCGAsmNH + 872451124U, // STOCGAsmNHE + 872458106U, // STOCGAsmNL + 872452020U, // STOCGAsmNLE + 872455655U, // STOCGAsmNLH + 872458951U, // STOCGAsmNM + 872459434U, // STOCGAsmNO + 872459916U, // STOCGAsmNP + 872463900U, // STOCGAsmNZ + 872459313U, // STOCGAsmO + 872459779U, // STOCGAsmP + 872463788U, // STOCGAsmZ + 906046377U, // STOSM + 268480461U, // STPQ + 6372204U, // STPT + 6372508U, // STPX + 939595549U, // STRAG + 536914259U, // STRL + 268483657U, // STRV + 268474854U, // STRVG + 268477136U, // STRVH + 6363825U, // STSCH + 6366329U, // STSI + 67142028U, // STURA + 67148093U, // STURG + 268483972U, // STY + 48148U, // SU + 33601315U, // SUR + 559553U, // SVC + 48243U, // SW + 33601331U, // SWR + 33599972U, // SXBR + 33601405U, // SXR + 2214639363U, // SXTR + 2214625663U, // SXTRA + 48501U, // SY + 6372240U, // TABORT + 16921U, // TAM + 67153934U, // TAR + 67143566U, // TB + 436253205U, // TBDR + 436253222U, // TBEDR + 704719850U, // TBEGIN + 704711003U, // TBEGINC + 268468798U, // TCDB + 268469198U, // TCEB + 268470249U, // TCXB + 268483303U, // TDCDT + 268483341U, // TDCET + 268483522U, // TDCXT + 268483310U, // TDGDT + 268483348U, // TDGET + 268483529U, // TDGXT + 16773U, // TEND + 67154601U, // THDER + 67154501U, // THDR + 906046393U, // TM + 771791793U, // TMHH + 771794556U, // TMHL + 771792249U, // TMLH + 771794680U, // TMLL + 906050919U, // TMY + 6401917U, // TP + 6366244U, // TPI + 939604820U, // TPROT + 604091768U, // TR + 2214627994U, // TRACE + 2214631257U, // TRACG + 16582U, // TRAP2 + 6357029U, // TRAP4 + 67146525U, // TRE + 2214636859U, // TROO + 67153211U, // TROOOpt + 2214640475U, // TROT + 67156827U, // TROTOpt + 604093336U, // TRT + 839291782U, // TRTE + 6722438U, // TRTEOpt + 2214636927U, // TRTO + 67153279U, // TRTOOpt + 604092024U, // TRTR + 839291675U, // TRTRE + 6722331U, // TRTREOpt + 2214640565U, // TRTT + 67156917U, // TRTTOpt + 6372010U, // TS + 6363826U, // TSCH + 234988828U, // UNPK + 604078172U, // UNPKA + 604093439U, // UNPKU + 17019U, // UPT + 2214625706U, // VA + 2214625739U, // VAB + 2214627560U, // VAC + 2214627569U, // VACC + 2214625756U, // VACCB + 2214627575U, // VACCC + 2214637467U, // VACCCQ + 2214630338U, // VACCF + 2214631264U, // VACCG + 2214632049U, // VACCH + 2214637460U, // VACCQ + 2214637454U, // VACQ + 2214630327U, // VAF + 2214631211U, // VAG + 2214631983U, // VAH + 2214636944U, // VAP + 2214637449U, // VAQ + 2214631859U, // VAVG + 2214626455U, // VAVGB + 2214630516U, // VAVGF + 2214631378U, // VAVGG + 2214632271U, // VAVGH + 2214635077U, // VAVGL + 2214626586U, // VAVGLB + 2214630673U, // VAVGLF + 2214631488U, // VAVGLG + 2214632651U, // VAVGLH + 2214636382U, // VBPERM + 2214631302U, // VCDG + 2214626418U, // VCDGB + 2214631481U, // VCDLG + 2214626439U, // VCDLGB + 2214626388U, // VCEFB + 2214626402U, // VCELFB + 2214637475U, // VCEQ + 2214626769U, // VCEQB + 2214639709U, // VCEQBS + 2214630903U, // VCEQF + 2214639992U, // VCEQFS + 2214631679U, // VCEQG + 2214640084U, // VCEQGS + 2214633909U, // VCEQH + 2214640158U, // VCEQHS + 2214626293U, // VCFEB + 2214636493U, // VCFN + 2214635659U, // VCFPL + 2214640284U, // VCFPS + 2214627815U, // VCGD + 2214625956U, // VCGDB + 2214632126U, // VCH + 2214626476U, // VCHB + 2214639694U, // VCHBS + 2214630537U, // VCHF + 2214639977U, // VCHFS + 2214631400U, // VCHG + 2214640069U, // VCHGS + 2214632292U, // VCHH + 2214640143U, // VCHHS + 2214635084U, // VCHL + 2214626594U, // VCHLB + 2214639701U, // VCHLBS + 2214630681U, // VCHLF + 2214639984U, // VCHLFS + 2214631496U, // VCHLG + 2214640076U, // VCHLGS + 2214632659U, // VCHLH + 2214640150U, // VCHLHS + 2214636443U, // VCKSM + 2214626307U, // VCLFEB + 2214633548U, // VCLFNH + 2214635370U, // VCLFNL + 2214637038U, // VCLFP + 2214627821U, // VCLGD + 2214625970U, // VCLGDB + 2214641146U, // VCLZ + 67143873U, // VCLZB + 2214637008U, // VCLZDP + 67147470U, // VCLZF + 67148289U, // VCLZG + 67150629U, // VCLZH + 2214630825U, // VCNF + 2214636972U, // VCP + 2214630837U, // VCRNF + 2214637045U, // VCSFP + 2214633896U, // VCSPH + 2214641365U, // VCTZ + 67143889U, // VCTZB + 67147496U, // VCTZF + 67148306U, // VCTZG + 67150655U, // VCTZH + 2214627227U, // VCVB + 2214631250U, // VCVBG + 2214631250U, // VCVBGOpt + 2214627227U, // VCVBOpt + 2214627899U, // VCVD + 2214631314U, // VCVDG + 2214637003U, // VDP + 2214627590U, // VEC + 67142115U, // VECB + 67146697U, // VECF + 67147623U, // VECG + 67148408U, // VECH + 2214634996U, // VECL + 67142931U, // VECLB + 67147018U, // VECLF + 67147826U, // VECLG + 67148958U, // VECLH + 2181081746U, // VERIM + 2181072260U, // VERIMB + 2181076380U, // VERIMF + 2181077160U, // VERIMG + 2181079005U, // VERIMH + 2214635269U, // VERLL + 2214626609U, // VERLLB + 2214630727U, // VERLLF + 2214631503U, // VERLLG + 2214632817U, // VERLLH + 2214640685U, // VERLLV + 2214627240U, // VERLLVB + 2214631044U, // VERLLVF + 2214631872U, // VERLLVG + 2214634160U, // VERLLVH + 2214635878U, // VESL + 2214626659U, // VESLB + 2214630770U, // VESLF + 2214631544U, // VESLG + 2214633317U, // VESLH + 2214640701U, // VESLV + 2214627258U, // VESLVB + 2214631062U, // VESLVF + 2214631890U, // VESLVG + 2214634178U, // VESLVH + 2214625569U, // VESRA + 2214625724U, // VESRAB + 2214630319U, // VESRAF + 2214631189U, // VESRAG + 2214631975U, // VESRAH + 2214640671U, // VESRAV + 2214627218U, // VESRAVB + 2214631028U, // VESRAVF + 2214631850U, // VESRAVG + 2214634144U, // VESRAVH + 2214635845U, // VESRL + 2214626644U, // VESRLB + 2214630762U, // VESRLF + 2214631536U, // VESRLG + 2214633309U, // VESRLH + 2214640693U, // VESRLV + 2214627249U, // VESRLVB + 2214631053U, // VESRLVF + 2214631881U, // VESRLVG + 2214634169U, // VESRLVH + 2214625354U, // VFA + 2214625783U, // VFADB + 2214627915U, // VFAE + 2214626240U, // VFAEB + 2214639669U, // VFAEBS + 2214630365U, // VFAEF + 2214639952U, // VFAEFS + 2214632131U, // VFAEH + 2214640118U, // VFAEHS + 2214627488U, // VFAEZB + 2214639904U, // VFAEZBS + 2214631085U, // VFAEZF + 2214640041U, // VFAEZFS + 2214634236U, // VFAEZH + 2214640202U, // VFAEZHS + 2214626808U, // VFASB + 2214628001U, // VFCE + 2214625874U, // VFCEDB + 2214639557U, // VFCEDBS + 2214626893U, // VFCESB + 2214639726U, // VFCESBS + 2214632062U, // VFCH + 2214625986U, // VFCHDB + 2214639633U, // VFCHDBS + 2214628126U, // VFCHE + 2214625890U, // VFCHEDB + 2214639575U, // VFCHEDBS + 2214626909U, // VFCHESB + 2214639744U, // VFCHESBS + 2214626961U, // VFCHSB + 2214639802U, // VFCHSBS + 2214627810U, // VFD + 2214625860U, // VFDDB + 2214626879U, // VFDSB + 2214628031U, // VFEE + 2214626280U, // VFEEB + 2214639677U, // VFEEBS + 2214630386U, // VFEEF + 2214639960U, // VFEEFS + 2214632145U, // VFEEH + 2214640126U, // VFEEHS + 2214627496U, // VFEEZB + 2214639913U, // VFEEZBS + 2214631093U, // VFEEZF + 2214640050U, // VFEEZFS + 2214634244U, // VFEEZH + 2214640211U, // VFEEZHS + 2214629830U, // VFENE + 2214626355U, // VFENEB + 2214639685U, // VFENEBS + 2214630426U, // VFENEF + 2214639968U, // VFENEFS + 2214632179U, // VFENEH + 2214640134U, // VFENEHS + 2214627512U, // VFENEZB + 2214639922U, // VFENEZBS + 2214631109U, // VFENEZF + 2214640059U, // VFENEZFS + 2214634260U, // VFENEZH + 2214640220U, // VFENEZHS + 2214634431U, // VFI + 2214626036U, // VFIDB + 2214627011U, // VFISB + 2214625926U, // VFKEDB + 2214639615U, // VFKEDBS + 2214626945U, // VFKESB + 2214639784U, // VFKESBS + 2214626002U, // VFKHDB + 2214639651U, // VFKHDBS + 2214625908U, // VFKHEDB + 2214639595U, // VFKHEDBS + 2214626927U, // VFKHESB + 2214639764U, // VFKHESBS + 2214626977U, // VFKHSB + 2214639820U, // VFKHSBS + 67142190U, // VFLCDB + 67143215U, // VFLCSB + 2214635225U, // VFLL + 67156595U, // VFLLS + 67142448U, // VFLNDB + 67143416U, // VFLNSB + 67142482U, // VFLPDB + 67143450U, // VFLPSB + 2214638800U, // VFLR + 2214627869U, // VFLRD + 2214636100U, // VFM + 2214625397U, // VFMA + 2214625797U, // VFMADB + 2214626822U, // VFMASB + 2214640770U, // VFMAX + 2214626210U, // VFMAXDB + 2214627191U, // VFMAXSB + 2214626064U, // VFMDB + 2214636536U, // VFMIN + 2214626078U, // VFMINDB + 2214627046U, // VFMINSB + 2214640257U, // VFMS + 2214627032U, // VFMSB + 2214626176U, // VFMSDB + 2214627152U, // VFMSSB + 2214625408U, // VFNMA + 2214625813U, // VFNMADB + 2214626838U, // VFNMASB + 2214640263U, // VFNMS + 2214626192U, // VFNMSDB + 2214627168U, // VFNMSSB + 2214636920U, // VFPSO + 2214626112U, // VFPSODB + 2214627080U, // VFPSOSB + 2214640026U, // VFS + 2214626162U, // VFSDB + 2214637538U, // VFSQ + 67142498U, // VFSQDB + 67143466U, // VFSQSB + 2214627138U, // VFSSB + 2214634344U, // VFTCI + 2214626018U, // VFTCIDB + 2214626993U, // VFTCISB + 771795476U, // VGBM + 3221263353U, // VGEF + 1073780640U, // VGEG + 2214636094U, // VGFM + 2214625390U, // VGFMA + 2214625716U, // VGFMAB + 2214630311U, // VGFMAF + 2214631175U, // VGFMAG + 2214631961U, // VGFMAH + 2214626679U, // VGFMB + 2214630793U, // VGFMF + 2214631579U, // VGFMG + 2214633424U, // VGFMH + 2952833629U, // VGM + 2952824190U, // VGMB + 2952828310U, // VGMF + 2952829090U, // VGMG + 2952830935U, // VGMH + 2214639237U, // VISTR + 2214626800U, // VISTRB + 67156069U, // VISTRBS + 2214630965U, // VISTRF + 67156352U, // VISTRFS + 2214634017U, // VISTRH + 67156518U, // VISTRHS + 268478956U, // VL + 2415962604U, // VLAlign + 2415952342U, // VLBB + 2415964534U, // VLBR + 268473879U, // VLBRF + 268474655U, // VLBRG + 268476877U, // VLBRH + 268480467U, // VLBRQ + 2415963615U, // VLBRREP + 268473824U, // VLBRREPF + 268474588U, // VLBRREPG + 268476817U, // VLBRREPH + 2214627665U, // VLC + 67142121U, // VLCB + 67146703U, // VLCF + 67147635U, // VLCG + 67148426U, // VLCH + 2214628020U, // VLDE + 67142612U, // VLDEB + 2147517479U, // VLEB + 2147522054U, // VLEBRF + 2147522830U, // VLEBRG + 2147525052U, // VLEBRH + 2214627799U, // VLED + 2214625942U, // VLEDB + 2147521550U, // VLEF + 2147522470U, // VLEG + 2147523303U, // VLEH + 2281735402U, // VLEIB + 2281739495U, // VLEIF + 2281740298U, // VLEIG + 2281741283U, // VLEIH + 2415964910U, // VLER + 268473894U, // VLERF + 268474670U, // VLERG + 268476899U, // VLERH + 2214640679U, // VLGV + 2214627233U, // VLGVB + 2214631037U, // VLGVF + 2214631865U, // VLGVG + 2214634153U, // VLGVH + 2919280220U, // VLIP + 2214635281U, // VLL + 2415967900U, // VLLEBRZ + 268473245U, // VLLEBRZE + 268474069U, // VLLEBRZF + 268474888U, // VLLEBRZG + 268477228U, // VLLEBRZH + 2415967646U, // VLLEZ + 268470448U, // VLLEZB + 268474045U, // VLLEZF + 268474873U, // VLLEZG + 268477196U, // VLLEZH + 268473728U, // VLLEZLF + 2214636198U, // VLM + 2214636198U, // VLMAlign + 2214637158U, // VLP + 67143115U, // VLPB + 67147249U, // VLPF + 67148013U, // VLPG + 67150242U, // VLPH + 67155232U, // VLR + 2415963608U, // VLREP + 268469692U, // VLREPB + 268473816U, // VLREPF + 268474580U, // VLREPG + 268476809U, // VLREPH + 3019942201U, // VLRL + 2214638860U, // VLRLR + 2181077466U, // VLVG + 2181072030U, // VLVGB + 2181076091U, // VLVGF + 2181076953U, // VLVGG + 2181077846U, // VLVGH + 2214637078U, // VLVGP + 2214627926U, // VMAE + 2214626247U, // VMAEB + 2214630372U, // VMAEF + 2214632138U, // VMAEH + 2214631969U, // VMAH + 2214626469U, // VMAHB + 2214630530U, // VMAHF + 2214632285U, // VMAHH + 2214634934U, // VMAL + 2214626572U, // VMALB + 2214628948U, // VMALE + 2214626328U, // VMALEB + 2214630399U, // VMALEF + 2214632152U, // VMALEH + 2214630659U, // VMALF + 2214632535U, // VMALH + 2214626482U, // VMALHB + 2214630574U, // VMALHF + 2214632340U, // VMALHH + 2214640723U, // VMALHW + 2214636658U, // VMALO + 2214626727U, // VMALOB + 2214630851U, // VMALOF + 2214633844U, // VMALOH + 2214636563U, // VMAO + 2214626720U, // VMAOB + 2214630844U, // VMAOF + 2214633837U, // VMAOH + 2214629746U, // VME + 2214626349U, // VMEB + 2214630420U, // VMEF + 2214632173U, // VMEH + 2214633464U, // VMH + 2214626505U, // VMHB + 2214630603U, // VMHF + 2214632375U, // VMHH + 2214635286U, // VML + 2214626617U, // VMLB + 2214629196U, // VMLE + 2214626336U, // VMLEB + 2214630407U, // VMLEF + 2214632160U, // VMLEH + 2214630735U, // VMLF + 2214632831U, // VMLH + 2214626490U, // VMLHB + 2214630588U, // VMLHF + 2214632354U, // VMLHH + 2214640731U, // VMLHW + 2214636665U, // VMLO + 2214626735U, // VMLOB + 2214630859U, // VMLOF + 2214633852U, // VMLOH + 2214636543U, // VMN + 2214626714U, // VMNB + 2214630831U, // VMNF + 2214631624U, // VMNG + 2214633697U, // VMNH + 2214635519U, // VMNL + 2214626623U, // VMNLB + 2214630741U, // VMNLF + 2214631522U, // VMNLG + 2214633084U, // VMNLH + 2214636681U, // VMO + 2214626742U, // VMOB + 2214630866U, // VMOF + 2214633859U, // VMOH + 2214637163U, // VMP + 2214634011U, // VMRH + 2214626518U, // VMRHB + 2214630616U, // VMRHF + 2214631406U, // VMRHG + 2214632388U, // VMRHH + 2214635839U, // VMRL + 2214626637U, // VMRLB + 2214630755U, // VMRLF + 2214631529U, // VMRLG + 2214633302U, // VMRLH + 2214635884U, // VMSL + 2214631551U, // VMSLG + 2214637425U, // VMSP + 2214640781U, // VMX + 2214627398U, // VMXB + 2214631070U, // VMXF + 2214631923U, // VMXG + 2214634204U, // VMXH + 2214636016U, // VMXL + 2214626672U, // VMXLB + 2214630777U, // VMXLF + 2214631565U, // VMXLG + 2214633404U, // VMXLH + 2214636554U, // VN + 2214627684U, // VNC + 2214636548U, // VNN + 2214636854U, // VNO + 2214640786U, // VNX + 2214636934U, // VO + 2214627700U, // VOC + 6328922U, // VONE + 2214634351U, // VPDI + 2214636390U, // VPERM + 2214634786U, // VPK + 2214630653U, // VPKF + 2214631453U, // VPKG + 2214632529U, // VPKH + 2214640236U, // VPKLS + 2214630986U, // VPKLSF + 2214640017U, // VPKLSFS + 2214631785U, // VPKLSG + 2214640100U, // VPKLSGS + 2214634032U, // VPKLSH + 2214640183U, // VPKLSHS + 2214640230U, // VPKS + 2214630979U, // VPKSF + 2214640009U, // VPKSFS + 2214631778U, // VPKSG + 2214640092U, // VPKSGS + 2214634025U, // VPKSH + 2214640175U, // VPKSHS + 3019947508U, // VPKZ + 2214639518U, // VPKZR + 2214640345U, // VPOPCT + 67143561U, // VPOPCTB + 67147359U, // VPOPCTF + 67148167U, // VPOPCTG + 67150405U, // VPOPCTH + 2214637324U, // VPSOP + 2214637032U, // VREP + 2214626756U, // VREPB + 2214630890U, // VREPF + 2214631654U, // VREPG + 2214633883U, // VREPH + 2717951005U, // VREPI + 570459396U, // VREPIB + 570463470U, // VREPIF + 570464273U, // VREPIG + 570465290U, // VREPIH + 2214637401U, // VRP + 2214640302U, // VS + 2214627186U, // VSB + 2214634316U, // VSBCBI + 2214637481U, // VSBCBIQ + 2214634331U, // VSBI + 2214637498U, // VSBIQ + 2214634324U, // VSCBI + 2214626525U, // VSCBIB + 2214630623U, // VSCBIF + 2214631426U, // VSCBIG + 2214632406U, // VSCBIH + 2214637490U, // VSCBIQ + 1107334123U, // VSCEF + 3254818713U, // VSCEG + 2214636977U, // VSCHDP + 2214637085U, // VSCHP + 2214637417U, // VSCHSP + 2214637441U, // VSCHXP + 2214637109U, // VSCSHP + 2214636997U, // VSDP + 2214631353U, // VSEG + 67142784U, // VSEGB + 67146803U, // VSEGF + 67148592U, // VSEGH + 2214635045U, // VSEL + 2214631002U, // VSF + 2214631798U, // VSG + 2214634048U, // VSH + 2214635890U, // VSL + 2214626666U, // VSLB + 2214627835U, // VSLD + 2214626057U, // VSLDB + 2214637431U, // VSP + 2214637544U, // VSQ + 2214625576U, // VSRA + 2214625732U, // VSRAB + 2214627883U, // VSRD + 2214635852U, // VSRL + 2214626652U, // VSRLB + 2214637395U, // VSRP + 2214638941U, // VSRPR + 268483504U, // VST + 2415967152U, // VSTAlign + 2415964540U, // VSTBR + 268473886U, // VSTBRF + 268474662U, // VSTBRG + 268476884U, // VSTBRH + 268480474U, // VSTBRQ + 2415952967U, // VSTEB + 2415957518U, // VSTEBRF + 2415958294U, // VSTEBRG + 2415960516U, // VSTEBRH + 2415957026U, // VSTEF + 2415957951U, // VSTEG + 2415958779U, // VSTEH + 2415964963U, // VSTER + 268473901U, // VSTERF + 268474677U, // VSTERG + 268476906U, // VSTERH + 2214636006U, // VSTL + 2214636471U, // VSTM + 2214636471U, // VSTMAlign + 2214627735U, // VSTRC + 2214625775U, // VSTRCB + 2214639548U, // VSTRCBS + 2214630357U, // VSTRCF + 2214639943U, // VSTRCFS + 2214632093U, // VSTRCH + 2214640109U, // VSTRCHS + 2214627479U, // VSTRCZB + 2214639894U, // VSTRCZBS + 2214631076U, // VSTRCZF + 2214640031U, // VSTRCZFS + 2214634227U, // VSTRCZH + 2214640192U, // VSTRCZHS + 3019942226U, // VSTRL + 2214638867U, // VSTRLR + 2214640291U, // VSTRS + 2214627130U, // VSTRSB + 2214630994U, // VSTRSF + 2214634040U, // VSTRSH + 2214627528U, // VSTRSZB + 2214631135U, // VSTRSZF + 2214634294U, // VSTRSZH + 2214636482U, // VSUM + 2214626707U, // VSUMB + 2214631611U, // VSUMG + 2214630482U, // VSUMGF + 2214632258U, // VSUMGH + 2214633457U, // VSUMH + 2214637505U, // VSUMQ + 2214630910U, // VSUMQF + 2214631686U, // VSUMQG + 67152829U, // VTM + 6336380U, // VTP + 2214633903U, // VUPH + 67142863U, // VUPHB + 67146961U, // VUPHF + 67148733U, // VUPHH + 3019947501U, // VUPKZ + 2214634269U, // VUPKZH + 2214636033U, // VUPKZL + 2214635666U, // VUPL + 67142982U, // VUPLB + 67147100U, // VUPLF + 2214633241U, // VUPLH + 67142849U, // VUPLHB + 67146947U, // VUPLHF + 67148713U, // VUPLHH + 67157090U, // VUPLHW + 2214635262U, // VUPLL + 67142953U, // VUPLLB + 67147071U, // VUPLLF + 67149161U, // VUPLLH + 2214640809U, // VX + 6335816U, // VZERO + 2214626425U, // WCDGB + 2214626447U, // WCDLGB + 2214626395U, // WCEFB + 2214626410U, // WCELFB + 2214626300U, // WCFEB + 2214625963U, // WCGDB + 2214626315U, // WCLFEB + 2214625978U, // WCLGDB + 2214625790U, // WFADB + 2214626815U, // WFASB + 2214627266U, // WFAXB + 2214627600U, // WFC + 67142183U, // WFCDB + 2214625882U, // WFCEDB + 2214639566U, // WFCEDBS + 2214626901U, // WFCESB + 2214639735U, // WFCESBS + 2214627318U, // WFCEXB + 2214639838U, // WFCEXBS + 2214625994U, // WFCHDB + 2214639642U, // WFCHDBS + 2214625899U, // WFCHEDB + 2214639585U, // WFCHEDBS + 2214626918U, // WFCHESB + 2214639754U, // WFCHESBS + 2214627326U, // WFCHEXB + 2214639847U, // WFCHEXBS + 2214626969U, // WFCHSB + 2214639811U, // WFCHSBS + 2214627352U, // WFCHXB + 2214639876U, // WFCHXBS + 67143208U, // WFCSB + 67143642U, // WFCXB + 2214625867U, // WFDDB + 2214626886U, // WFDSB + 2214627311U, // WFDXB + 2214626043U, // WFIDB + 2214627018U, // WFISB + 2214627377U, // WFIXB + 2214634727U, // WFK + 67142402U, // WFKDB + 2214625934U, // WFKEDB + 2214639624U, // WFKEDBS + 2214626953U, // WFKESB + 2214639793U, // WFKESBS + 2214627344U, // WFKEXB + 2214639867U, // WFKEXBS + 2214626010U, // WFKHDB + 2214639660U, // WFKHDBS + 2214625917U, // WFKHEDB + 2214639605U, // WFKHEDBS + 2214626936U, // WFKHESB + 2214639774U, // WFKHESBS + 2214627335U, // WFKHEXB + 2214639857U, // WFKHEXBS + 2214626985U, // WFKHSB + 2214639829U, // WFKHSBS + 2214627360U, // WFKHXB + 2214639885U, // WFKHXBS + 67143377U, // WFKSB + 67143736U, // WFKXB + 67142198U, // WFLCDB + 67143223U, // WFLCSB + 67143649U, // WFLCXB + 67144180U, // WFLLD + 67156602U, // WFLLS + 67142456U, // WFLNDB + 67143424U, // WFLNSB + 67143765U, // WFLNXB + 67142490U, // WFLPDB + 67143458U, // WFLPSB + 67143782U, // WFLPXB + 2214627876U, // WFLRD + 2214640802U, // WFLRX + 2214625805U, // WFMADB + 2214626830U, // WFMASB + 2214627273U, // WFMAXB + 2214626219U, // WFMAXDB + 2214627200U, // WFMAXSB + 2214627470U, // WFMAXXB + 2214626071U, // WFMDB + 2214626087U, // WFMINDB + 2214627055U, // WFMINSB + 2214627404U, // WFMINXB + 2214627039U, // WFMSB + 2214626184U, // WFMSDB + 2214627160U, // WFMSSB + 2214627453U, // WFMSXB + 2214627391U, // WFMXB + 2214625822U, // WFNMADB + 2214626847U, // WFNMASB + 2214627281U, // WFNMAXB + 2214626201U, // WFNMSDB + 2214627177U, // WFNMSSB + 2214627461U, // WFNMSXB + 2214626121U, // WFPSODB + 2214627089U, // WFPSOSB + 2214627421U, // WFPSOXB + 2214626169U, // WFSDB + 67142506U, // WFSQDB + 67143474U, // WFSQSB + 67143790U, // WFSQXB + 2214627145U, // WFSSB + 2214627446U, // WFSXB + 2214626027U, // WFTCIDB + 2214627002U, // WFTCISB + 2214627368U, // WFTCIXB + 67142619U, // WLDEB + 2214625949U, // WLEDB + 48255U, // X + 604080582U, // XC + 39407U, // XG + 33600552U, // XGR + 2214634869U, // XGRK + 906044553U, // XI + 201364648U, // XIHF + 201364793U, // XILF + 906050866U, // XIY + 33601337U, // XR + 2214634905U, // XRK + 16818U, // XSCH + 48521U, // XY + 234990997U, // ZAP + }; + + static const uint16_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ADB_MemFoldPseudo + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADJDYNALLOC + 0U, // AEB_MemFoldPseudo + 0U, // AEXT128 + 0U, // AFIMux + 0U, // AG_MemFoldPseudo + 0U, // AHIMux + 0U, // AHIMuxK + 0U, // ALG_MemFoldPseudo + 0U, // AL_MemFoldPseudo + 0U, // ATOMIC_CMP_SWAPW + 0U, // ATOMIC_LOADW_AFI + 0U, // ATOMIC_LOADW_AR + 0U, // ATOMIC_LOADW_MAX + 0U, // ATOMIC_LOADW_MIN + 0U, // ATOMIC_LOADW_NILH + 0U, // ATOMIC_LOADW_NILHi + 0U, // ATOMIC_LOADW_NR + 0U, // ATOMIC_LOADW_NRi + 0U, // ATOMIC_LOADW_OILH + 0U, // ATOMIC_LOADW_OR + 0U, // ATOMIC_LOADW_SR + 0U, // ATOMIC_LOADW_UMAX + 0U, // ATOMIC_LOADW_UMIN + 0U, // ATOMIC_LOADW_XILF + 0U, // ATOMIC_LOADW_XR + 0U, // ATOMIC_LOAD_AFI + 0U, // ATOMIC_LOAD_AGFI + 0U, // ATOMIC_LOAD_AGHI + 0U, // ATOMIC_LOAD_AGR + 0U, // ATOMIC_LOAD_AHI + 0U, // ATOMIC_LOAD_AR + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NGR + 0U, // ATOMIC_LOAD_NGRi + 0U, // ATOMIC_LOAD_NIHF64 + 0U, // ATOMIC_LOAD_NIHF64i + 0U, // ATOMIC_LOAD_NIHH64 + 0U, // ATOMIC_LOAD_NIHH64i + 0U, // ATOMIC_LOAD_NIHL64 + 0U, // ATOMIC_LOAD_NIHL64i + 0U, // ATOMIC_LOAD_NILF + 0U, // ATOMIC_LOAD_NILF64 + 0U, // ATOMIC_LOAD_NILF64i + 0U, // ATOMIC_LOAD_NILFi + 0U, // ATOMIC_LOAD_NILH + 0U, // ATOMIC_LOAD_NILH64 + 0U, // ATOMIC_LOAD_NILH64i + 0U, // ATOMIC_LOAD_NILHi + 0U, // ATOMIC_LOAD_NILL + 0U, // ATOMIC_LOAD_NILL64 + 0U, // ATOMIC_LOAD_NILL64i + 0U, // ATOMIC_LOAD_NILLi + 0U, // ATOMIC_LOAD_NR + 0U, // ATOMIC_LOAD_NRi + 0U, // ATOMIC_LOAD_OGR + 0U, // ATOMIC_LOAD_OIHF64 + 0U, // ATOMIC_LOAD_OIHH64 + 0U, // ATOMIC_LOAD_OIHL64 + 0U, // ATOMIC_LOAD_OILF + 0U, // ATOMIC_LOAD_OILF64 + 0U, // ATOMIC_LOAD_OILH + 0U, // ATOMIC_LOAD_OILH64 + 0U, // ATOMIC_LOAD_OILL + 0U, // ATOMIC_LOAD_OILL64 + 0U, // ATOMIC_LOAD_OR + 0U, // ATOMIC_LOAD_SGR + 0U, // ATOMIC_LOAD_SR + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XGR + 0U, // ATOMIC_LOAD_XIHF64 + 0U, // ATOMIC_LOAD_XILF + 0U, // ATOMIC_LOAD_XILF64 + 0U, // ATOMIC_LOAD_XR + 0U, // ATOMIC_SWAPW + 0U, // ATOMIC_SWAP_32 + 0U, // ATOMIC_SWAP_64 + 0U, // A_MemFoldPseudo + 0U, // CFIMux + 0U, // CGIBCall + 0U, // CGIBReturn + 0U, // CGRBCall + 0U, // CGRBReturn + 0U, // CHIMux + 0U, // CIBCall + 0U, // CIBReturn + 0U, // CLCImm + 0U, // CLCReg + 0U, // CLFIMux + 0U, // CLGIBCall + 0U, // CLGIBReturn + 0U, // CLGRBCall + 0U, // CLGRBReturn + 0U, // CLIBCall + 0U, // CLIBReturn + 0U, // CLMux + 0U, // CLRBCall + 0U, // CLRBReturn + 0U, // CLSTLoop + 0U, // CMux + 0U, // CRBCall + 0U, // CRBReturn + 0U, // CallBASR + 0U, // CallBASR_XPLINK64 + 0U, // CallBCR + 0U, // CallBR + 0U, // CallBRASL + 0U, // CallBRASL_XPLINK64 + 0U, // CallBRCL + 0U, // CallJG + 0U, // CondReturn + 0U, // CondStore16 + 0U, // CondStore16Inv + 0U, // CondStore16Mux + 0U, // CondStore16MuxInv + 0U, // CondStore32 + 0U, // CondStore32Inv + 0U, // CondStore32Mux + 0U, // CondStore32MuxInv + 0U, // CondStore64 + 0U, // CondStore64Inv + 0U, // CondStore8 + 0U, // CondStore8Inv + 0U, // CondStore8Mux + 0U, // CondStore8MuxInv + 0U, // CondStoreF32 + 0U, // CondStoreF32Inv + 0U, // CondStoreF64 + 0U, // CondStoreF64Inv + 0U, // CondTrap + 0U, // DDB_MemFoldPseudo + 0U, // DEB_MemFoldPseudo + 0U, // EXRL_Pseudo + 0U, // GOT + 0U, // IIFMux + 0U, // IIHF64 + 0U, // IIHH64 + 0U, // IIHL64 + 0U, // IIHMux + 0U, // IILF64 + 0U, // IILH64 + 0U, // IILL64 + 0U, // IILMux + 0U, // L128 + 0U, // LBMux + 0U, // LEFR + 0U, // LFER + 0U, // LHIMux + 0U, // LHMux + 0U, // LLCMux + 0U, // LLCRMux + 0U, // LLHMux + 0U, // LLHRMux + 0U, // LMux + 0U, // LOCG_MemFoldPseudo + 0U, // LOCHIMux + 0U, // LOCMux + 0U, // LOCMux_MemFoldPseudo + 0U, // LOCRMux + 0U, // LTDBRCompare_VecPseudo + 0U, // LTEBRCompare_VecPseudo + 0U, // LTXBRCompare_VecPseudo + 0U, // LX + 0U, // MADB_MemFoldPseudo + 0U, // MAEB_MemFoldPseudo + 0U, // MDB_MemFoldPseudo + 0U, // MEEB_MemFoldPseudo + 0U, // MSC_MemFoldPseudo + 0U, // MSDB_MemFoldPseudo + 0U, // MSEB_MemFoldPseudo + 0U, // MSGC_MemFoldPseudo + 0U, // MVCImm + 0U, // MVCReg + 0U, // MVSTLoop + 0U, // MemBarrier + 0U, // NCImm + 0U, // NCReg + 0U, // NG_MemFoldPseudo + 0U, // NIFMux + 0U, // NIHF64 + 0U, // NIHH64 + 0U, // NIHL64 + 0U, // NIHMux + 0U, // NILF64 + 0U, // NILH64 + 0U, // NILL64 + 0U, // NILMux + 0U, // N_MemFoldPseudo + 0U, // OCImm + 0U, // OCReg + 0U, // OG_MemFoldPseudo + 0U, // OIFMux + 0U, // OIHF64 + 0U, // OIHH64 + 0U, // OIHL64 + 0U, // OIHMux + 0U, // OILF64 + 0U, // OILH64 + 0U, // OILL64 + 0U, // OILMux + 0U, // O_MemFoldPseudo + 0U, // PAIR128 + 0U, // PROBED_ALLOCA + 0U, // PROBED_STACKALLOC + 0U, // RISBHH + 0U, // RISBHL + 0U, // RISBLH + 0U, // RISBLL + 0U, // RISBMux + 0U, // Return + 0U, // SDB_MemFoldPseudo + 0U, // SEB_MemFoldPseudo + 0U, // SELRMux + 0U, // SG_MemFoldPseudo + 0U, // SLG_MemFoldPseudo + 0U, // SL_MemFoldPseudo + 0U, // SRSTLoop + 0U, // ST128 + 0U, // STCMux + 0U, // STHMux + 0U, // STMux + 0U, // STOCMux + 0U, // STX + 0U, // S_MemFoldPseudo + 0U, // Select32 + 0U, // Select64 + 0U, // SelectF128 + 0U, // SelectF32 + 0U, // SelectF64 + 0U, // SelectVR128 + 0U, // SelectVR32 + 0U, // SelectVR64 + 0U, // Serialize + 0U, // TBEGIN_nofloat + 0U, // TLS_GDCALL + 0U, // TLS_LDCALL + 0U, // TMHH64 + 0U, // TMHL64 + 0U, // TMHMux + 0U, // TMLH64 + 0U, // TMLL64 + 0U, // TMLMux + 0U, // Trap + 0U, // VL32 + 0U, // VL64 + 0U, // VLR32 + 0U, // VLR64 + 0U, // VLVGP32 + 0U, // VST32 + 0U, // VST64 + 0U, // XCImm + 0U, // XCReg + 0U, // XG_MemFoldPseudo + 0U, // XIFMux + 0U, // XIHF64 + 0U, // XILF64 + 0U, // X_MemFoldPseudo + 0U, // ZEXT128 + 0U, // A + 0U, // AD + 0U, // ADB + 0U, // ADBR + 0U, // ADR + 0U, // ADTR + 1024U, // ADTRA + 0U, // AE + 0U, // AEB + 0U, // AEBR + 0U, // AER + 0U, // AFI + 0U, // AG + 0U, // AGF + 0U, // AGFI + 0U, // AGFR + 0U, // AGH + 0U, // AGHI + 16U, // AGHIK + 0U, // AGR + 0U, // AGRK + 0U, // AGSI + 0U, // AH + 0U, // AHHHR + 0U, // AHHLR + 0U, // AHI + 16U, // AHIK + 0U, // AHY + 0U, // AIH + 0U, // AL + 0U, // ALC + 0U, // ALCG + 0U, // ALCGR + 0U, // ALCR + 0U, // ALFI + 0U, // ALG + 0U, // ALGF + 0U, // ALGFI + 0U, // ALGFR + 16U, // ALGHSIK + 0U, // ALGR + 0U, // ALGRK + 0U, // ALGSI + 0U, // ALHHHR + 0U, // ALHHLR + 16U, // ALHSIK + 0U, // ALR + 0U, // ALRK + 0U, // ALSI + 0U, // ALSIH + 0U, // ALSIHN + 0U, // ALY + 0U, // AP + 0U, // AR + 0U, // ARK + 0U, // ASI + 0U, // AU + 0U, // AUR + 0U, // AW + 0U, // AWR + 0U, // AXBR + 0U, // AXR + 0U, // AXTR + 1024U, // AXTRA + 0U, // AY + 0U, // B + 0U, // BAKR + 0U, // BAL + 0U, // BALR + 0U, // BAS + 0U, // BASR + 0U, // BASSM + 0U, // BAsmE + 0U, // BAsmH + 0U, // BAsmHE + 0U, // BAsmL + 0U, // BAsmLE + 0U, // BAsmLH + 0U, // BAsmM + 0U, // BAsmNE + 0U, // BAsmNH + 0U, // BAsmNHE + 0U, // BAsmNL + 0U, // BAsmNLE + 0U, // BAsmNLH + 0U, // BAsmNM + 0U, // BAsmNO + 0U, // BAsmNP + 0U, // BAsmNZ + 0U, // BAsmO + 0U, // BAsmP + 0U, // BAsmZ + 0U, // BC + 0U, // BCAsm + 0U, // BCR + 0U, // BCRAsm + 0U, // BCT + 0U, // BCTG + 0U, // BCTGR + 0U, // BCTR + 0U, // BI + 0U, // BIAsmE + 0U, // BIAsmH + 0U, // BIAsmHE + 0U, // BIAsmL + 0U, // BIAsmLE + 0U, // BIAsmLH + 0U, // BIAsmM + 0U, // BIAsmNE + 0U, // BIAsmNH + 0U, // BIAsmNHE + 0U, // BIAsmNL + 0U, // BIAsmNLE + 0U, // BIAsmNLH + 0U, // BIAsmNM + 0U, // BIAsmNO + 0U, // BIAsmNP + 0U, // BIAsmNZ + 0U, // BIAsmO + 0U, // BIAsmP + 0U, // BIAsmZ + 0U, // BIC + 0U, // BICAsm + 33U, // BPP + 1U, // BPRP + 0U, // BR + 0U, // BRAS + 0U, // BRASL + 0U, // BRAsmE + 0U, // BRAsmH + 0U, // BRAsmHE + 0U, // BRAsmL + 0U, // BRAsmLE + 0U, // BRAsmLH + 0U, // BRAsmM + 0U, // BRAsmNE + 0U, // BRAsmNH + 0U, // BRAsmNHE + 0U, // BRAsmNL + 0U, // BRAsmNLE + 0U, // BRAsmNLH + 0U, // BRAsmNM + 0U, // BRAsmNO + 0U, // BRAsmNP + 0U, // BRAsmNZ + 0U, // BRAsmO + 0U, // BRAsmP + 0U, // BRAsmZ + 0U, // BRC + 0U, // BRCAsm + 0U, // BRCL + 0U, // BRCLAsm + 0U, // BRCT + 0U, // BRCTG + 0U, // BRCTH + 48U, // BRXH + 48U, // BRXHG + 48U, // BRXLE + 48U, // BRXLG + 0U, // BSA + 0U, // BSG + 0U, // BSM + 64U, // BXH + 64U, // BXHG + 64U, // BXLE + 64U, // BXLEG + 0U, // C + 0U, // CD + 0U, // CDB + 0U, // CDBR + 0U, // CDFBR + 82U, // CDFBRA + 0U, // CDFR + 82U, // CDFTR + 0U, // CDGBR + 82U, // CDGBRA + 0U, // CDGR + 0U, // CDGTR + 82U, // CDGTRA + 82U, // CDLFBR + 82U, // CDLFTR + 82U, // CDLGBR + 82U, // CDLGTR + 0U, // CDPT + 0U, // CDR + 64U, // CDS + 64U, // CDSG + 0U, // CDSTR + 64U, // CDSY + 0U, // CDTR + 0U, // CDUTR + 0U, // CDZT + 0U, // CE + 0U, // CEB + 0U, // CEBR + 0U, // CEDTR + 0U, // CEFBR + 82U, // CEFBRA + 0U, // CEFR + 0U, // CEGBR + 82U, // CEGBRA + 0U, // CEGR + 82U, // CELFBR + 82U, // CELGBR + 0U, // CER + 0U, // CEXTR + 0U, // CFC + 34U, // CFDBR + 82U, // CFDBRA + 34U, // CFDR + 82U, // CFDTR + 34U, // CFEBR + 82U, // CFEBRA + 34U, // CFER + 0U, // CFI + 34U, // CFXBR + 82U, // CFXBRA + 34U, // CFXR + 82U, // CFXTR + 0U, // CG + 34U, // CGDBR + 82U, // CGDBRA + 34U, // CGDR + 34U, // CGDTR + 82U, // CGDTRA + 34U, // CGEBR + 82U, // CGEBRA + 34U, // CGER + 0U, // CGF + 0U, // CGFI + 0U, // CGFR + 0U, // CGFRL + 0U, // CGH + 0U, // CGHI + 0U, // CGHRL + 0U, // CGHSI + 0U, // CGIB + 66U, // CGIBAsm + 35U, // CGIBAsmE + 35U, // CGIBAsmH + 35U, // CGIBAsmHE + 35U, // CGIBAsmL + 35U, // CGIBAsmLE + 35U, // CGIBAsmLH + 35U, // CGIBAsmNE + 35U, // CGIBAsmNH + 35U, // CGIBAsmNHE + 35U, // CGIBAsmNL + 35U, // CGIBAsmNLE + 35U, // CGIBAsmNLH + 0U, // CGIJ + 50U, // CGIJAsm + 1U, // CGIJAsmE + 1U, // CGIJAsmH + 1U, // CGIJAsmHE + 1U, // CGIJAsmL + 1U, // CGIJAsmLE + 1U, // CGIJAsmLH + 1U, // CGIJAsmNE + 1U, // CGIJAsmNH + 1U, // CGIJAsmNHE + 1U, // CGIJAsmNL + 1U, // CGIJAsmNLE + 1U, // CGIJAsmNLH + 0U, // CGIT + 96U, // CGITAsm + 0U, // CGITAsmE + 0U, // CGITAsmH + 0U, // CGITAsmHE + 0U, // CGITAsmL + 0U, // CGITAsmLE + 0U, // CGITAsmLH + 0U, // CGITAsmNE + 0U, // CGITAsmNH + 0U, // CGITAsmNHE + 0U, // CGITAsmNL + 0U, // CGITAsmNLE + 0U, // CGITAsmNLH + 0U, // CGR + 35U, // CGRB + 17504U, // CGRBAsm + 112U, // CGRBAsmE + 112U, // CGRBAsmH + 112U, // CGRBAsmHE + 112U, // CGRBAsmL + 112U, // CGRBAsmLE + 112U, // CGRBAsmLH + 112U, // CGRBAsmNE + 112U, // CGRBAsmNH + 112U, // CGRBAsmNHE + 112U, // CGRBAsmNL + 112U, // CGRBAsmNLE + 112U, // CGRBAsmNLH + 4U, // CGRJ + 33888U, // CGRJAsm + 128U, // CGRJAsmE + 128U, // CGRJAsmH + 128U, // CGRJAsmHE + 128U, // CGRJAsmL + 128U, // CGRJAsmLE + 128U, // CGRJAsmLH + 128U, // CGRJAsmNE + 128U, // CGRJAsmNH + 128U, // CGRJAsmNHE + 128U, // CGRJAsmNL + 128U, // CGRJAsmNLE + 128U, // CGRJAsmNLH + 0U, // CGRL + 0U, // CGRT + 96U, // CGRTAsm + 0U, // CGRTAsmE + 0U, // CGRTAsmH + 0U, // CGRTAsmHE + 0U, // CGRTAsmL + 0U, // CGRTAsmLE + 0U, // CGRTAsmLH + 0U, // CGRTAsmNE + 0U, // CGRTAsmNH + 0U, // CGRTAsmNHE + 0U, // CGRTAsmNL + 0U, // CGRTAsmNLE + 0U, // CGRTAsmNLH + 34U, // CGXBR + 82U, // CGXBRA + 34U, // CGXR + 34U, // CGXTR + 82U, // CGXTRA + 0U, // CH + 0U, // CHF + 0U, // CHHR + 0U, // CHHSI + 0U, // CHI + 0U, // CHLR + 0U, // CHRL + 0U, // CHSI + 0U, // CHY + 0U, // CIB + 66U, // CIBAsm + 35U, // CIBAsmE + 35U, // CIBAsmH + 35U, // CIBAsmHE + 35U, // CIBAsmL + 35U, // CIBAsmLE + 35U, // CIBAsmLH + 35U, // CIBAsmNE + 35U, // CIBAsmNH + 35U, // CIBAsmNHE + 35U, // CIBAsmNL + 35U, // CIBAsmNLE + 35U, // CIBAsmNLH + 0U, // CIH + 0U, // CIJ + 50U, // CIJAsm + 1U, // CIJAsmE + 1U, // CIJAsmH + 1U, // CIJAsmHE + 1U, // CIJAsmL + 1U, // CIJAsmLE + 1U, // CIJAsmLH + 1U, // CIJAsmNE + 1U, // CIJAsmNH + 1U, // CIJAsmNHE + 1U, // CIJAsmNL + 1U, // CIJAsmNLE + 1U, // CIJAsmNLH + 0U, // CIT + 96U, // CITAsm + 0U, // CITAsmE + 0U, // CITAsmH + 0U, // CITAsmHE + 0U, // CITAsmL + 0U, // CITAsmLE + 0U, // CITAsmLH + 0U, // CITAsmNE + 0U, // CITAsmNH + 0U, // CITAsmNHE + 0U, // CITAsmNL + 0U, // CITAsmNLE + 0U, // CITAsmNLH + 0U, // CKSM + 0U, // CL + 0U, // CLC + 0U, // CLCL + 144U, // CLCLE + 144U, // CLCLU + 82U, // CLFDBR + 82U, // CLFDTR + 82U, // CLFEBR + 0U, // CLFHSI + 0U, // CLFI + 0U, // CLFIT + 96U, // CLFITAsm + 0U, // CLFITAsmE + 0U, // CLFITAsmH + 0U, // CLFITAsmHE + 0U, // CLFITAsmL + 0U, // CLFITAsmLE + 0U, // CLFITAsmLH + 0U, // CLFITAsmNE + 0U, // CLFITAsmNH + 0U, // CLFITAsmNHE + 0U, // CLFITAsmNL + 0U, // CLFITAsmNLE + 0U, // CLFITAsmNLH + 82U, // CLFXBR + 82U, // CLFXTR + 0U, // CLG + 82U, // CLGDBR + 82U, // CLGDTR + 82U, // CLGEBR + 0U, // CLGF + 0U, // CLGFI + 0U, // CLGFR + 0U, // CLGFRL + 0U, // CLGHRL + 0U, // CLGHSI + 0U, // CLGIB + 66U, // CLGIBAsm + 35U, // CLGIBAsmE + 35U, // CLGIBAsmH + 35U, // CLGIBAsmHE + 35U, // CLGIBAsmL + 35U, // CLGIBAsmLE + 35U, // CLGIBAsmLH + 35U, // CLGIBAsmNE + 35U, // CLGIBAsmNH + 35U, // CLGIBAsmNHE + 35U, // CLGIBAsmNL + 35U, // CLGIBAsmNLE + 35U, // CLGIBAsmNLH + 0U, // CLGIJ + 50U, // CLGIJAsm + 1U, // CLGIJAsmE + 1U, // CLGIJAsmH + 1U, // CLGIJAsmHE + 1U, // CLGIJAsmL + 1U, // CLGIJAsmLE + 1U, // CLGIJAsmLH + 1U, // CLGIJAsmNE + 1U, // CLGIJAsmNH + 1U, // CLGIJAsmNHE + 1U, // CLGIJAsmNL + 1U, // CLGIJAsmNLE + 1U, // CLGIJAsmNLH + 0U, // CLGIT + 96U, // CLGITAsm + 0U, // CLGITAsmE + 0U, // CLGITAsmH + 0U, // CLGITAsmHE + 0U, // CLGITAsmL + 0U, // CLGITAsmLE + 0U, // CLGITAsmLH + 0U, // CLGITAsmNE + 0U, // CLGITAsmNH + 0U, // CLGITAsmNHE + 0U, // CLGITAsmNL + 0U, // CLGITAsmNLE + 0U, // CLGITAsmNLH + 0U, // CLGR + 35U, // CLGRB + 17504U, // CLGRBAsm + 112U, // CLGRBAsmE + 112U, // CLGRBAsmH + 112U, // CLGRBAsmHE + 112U, // CLGRBAsmL + 112U, // CLGRBAsmLE + 112U, // CLGRBAsmLH + 112U, // CLGRBAsmNE + 112U, // CLGRBAsmNH + 112U, // CLGRBAsmNHE + 112U, // CLGRBAsmNL + 112U, // CLGRBAsmNLE + 112U, // CLGRBAsmNLH + 4U, // CLGRJ + 33888U, // CLGRJAsm + 128U, // CLGRJAsmE + 128U, // CLGRJAsmH + 128U, // CLGRJAsmHE + 128U, // CLGRJAsmL + 128U, // CLGRJAsmLE + 128U, // CLGRJAsmLH + 128U, // CLGRJAsmNE + 128U, // CLGRJAsmNH + 128U, // CLGRJAsmNHE + 128U, // CLGRJAsmNL + 128U, // CLGRJAsmNLE + 128U, // CLGRJAsmNLH + 0U, // CLGRL + 0U, // CLGRT + 96U, // CLGRTAsm + 0U, // CLGRTAsmE + 0U, // CLGRTAsmH + 0U, // CLGRTAsmHE + 0U, // CLGRTAsmL + 0U, // CLGRTAsmLE + 0U, // CLGRTAsmLH + 0U, // CLGRTAsmNE + 0U, // CLGRTAsmNH + 0U, // CLGRTAsmNHE + 0U, // CLGRTAsmNL + 0U, // CLGRTAsmNLE + 0U, // CLGRTAsmNLH + 0U, // CLGT + 160U, // CLGTAsm + 0U, // CLGTAsmE + 0U, // CLGTAsmH + 0U, // CLGTAsmHE + 0U, // CLGTAsmL + 0U, // CLGTAsmLE + 0U, // CLGTAsmLH + 0U, // CLGTAsmNE + 0U, // CLGTAsmNH + 0U, // CLGTAsmNHE + 0U, // CLGTAsmNL + 0U, // CLGTAsmNLE + 0U, // CLGTAsmNLH + 82U, // CLGXBR + 82U, // CLGXTR + 0U, // CLHF + 0U, // CLHHR + 0U, // CLHHSI + 0U, // CLHLR + 0U, // CLHRL + 0U, // CLI + 0U, // CLIB + 66U, // CLIBAsm + 35U, // CLIBAsmE + 35U, // CLIBAsmH + 35U, // CLIBAsmHE + 35U, // CLIBAsmL + 35U, // CLIBAsmLE + 35U, // CLIBAsmLH + 35U, // CLIBAsmNE + 35U, // CLIBAsmNH + 35U, // CLIBAsmNHE + 35U, // CLIBAsmNL + 35U, // CLIBAsmNLE + 35U, // CLIBAsmNLH + 0U, // CLIH + 0U, // CLIJ + 50U, // CLIJAsm + 1U, // CLIJAsmE + 1U, // CLIJAsmH + 1U, // CLIJAsmHE + 1U, // CLIJAsmL + 1U, // CLIJAsmLE + 1U, // CLIJAsmLH + 1U, // CLIJAsmNE + 1U, // CLIJAsmNH + 1U, // CLIJAsmNHE + 1U, // CLIJAsmNL + 1U, // CLIJAsmNLE + 1U, // CLIJAsmNLH + 0U, // CLIY + 35U, // CLM + 35U, // CLMH + 35U, // CLMY + 0U, // CLR + 35U, // CLRB + 17504U, // CLRBAsm + 112U, // CLRBAsmE + 112U, // CLRBAsmH + 112U, // CLRBAsmHE + 112U, // CLRBAsmL + 112U, // CLRBAsmLE + 112U, // CLRBAsmLH + 112U, // CLRBAsmNE + 112U, // CLRBAsmNH + 112U, // CLRBAsmNHE + 112U, // CLRBAsmNL + 112U, // CLRBAsmNLE + 112U, // CLRBAsmNLH + 4U, // CLRJ + 33888U, // CLRJAsm + 128U, // CLRJAsmE + 128U, // CLRJAsmH + 128U, // CLRJAsmHE + 128U, // CLRJAsmL + 128U, // CLRJAsmLE + 128U, // CLRJAsmLH + 128U, // CLRJAsmNE + 128U, // CLRJAsmNH + 128U, // CLRJAsmNHE + 128U, // CLRJAsmNL + 128U, // CLRJAsmNLE + 128U, // CLRJAsmNLH + 0U, // CLRL + 0U, // CLRT + 96U, // CLRTAsm + 0U, // CLRTAsmE + 0U, // CLRTAsmH + 0U, // CLRTAsmHE + 0U, // CLRTAsmL + 0U, // CLRTAsmLE + 0U, // CLRTAsmLH + 0U, // CLRTAsmNE + 0U, // CLRTAsmNH + 0U, // CLRTAsmNHE + 0U, // CLRTAsmNL + 0U, // CLRTAsmNLE + 0U, // CLRTAsmNLH + 0U, // CLST + 0U, // CLT + 160U, // CLTAsm + 0U, // CLTAsmE + 0U, // CLTAsmH + 0U, // CLTAsmHE + 0U, // CLTAsmL + 0U, // CLTAsmLE + 0U, // CLTAsmLH + 0U, // CLTAsmNE + 0U, // CLTAsmNH + 0U, // CLTAsmNHE + 0U, // CLTAsmNL + 0U, // CLTAsmNLE + 0U, // CLTAsmNLH + 0U, // CLY + 0U, // CMPSC + 0U, // CP + 0U, // CPDT + 176U, // CPSDRdd + 176U, // CPSDRds + 176U, // CPSDRsd + 176U, // CPSDRss + 0U, // CPXT + 0U, // CPYA + 0U, // CR + 35U, // CRB + 17504U, // CRBAsm + 112U, // CRBAsmE + 112U, // CRBAsmH + 112U, // CRBAsmHE + 112U, // CRBAsmL + 112U, // CRBAsmLE + 112U, // CRBAsmLH + 112U, // CRBAsmNE + 112U, // CRBAsmNH + 112U, // CRBAsmNHE + 112U, // CRBAsmNL + 112U, // CRBAsmNLE + 112U, // CRBAsmNLH + 1200U, // CRDTE + 176U, // CRDTEOpt + 4U, // CRJ + 33888U, // CRJAsm + 128U, // CRJAsmE + 128U, // CRJAsmH + 128U, // CRJAsmHE + 128U, // CRJAsmL + 128U, // CRJAsmLE + 128U, // CRJAsmLH + 128U, // CRJAsmNE + 128U, // CRJAsmNH + 128U, // CRJAsmNHE + 128U, // CRJAsmNL + 128U, // CRJAsmNLE + 128U, // CRJAsmNLH + 0U, // CRL + 0U, // CRT + 96U, // CRTAsm + 0U, // CRTAsmE + 0U, // CRTAsmH + 0U, // CRTAsmHE + 0U, // CRTAsmL + 0U, // CRTAsmLE + 0U, // CRTAsmLH + 0U, // CRTAsmNE + 0U, // CRTAsmNH + 0U, // CRTAsmNHE + 0U, // CRTAsmNL + 0U, // CRTAsmNLE + 0U, // CRTAsmNLH + 64U, // CS + 0U, // CSCH + 96U, // CSDTR + 64U, // CSG + 0U, // CSP + 0U, // CSPG + 192U, // CSST + 96U, // CSXTR + 64U, // CSY + 208U, // CU12 + 0U, // CU12Opt + 208U, // CU14 + 0U, // CU14Opt + 208U, // CU21 + 0U, // CU21Opt + 208U, // CU24 + 0U, // CU24Opt + 0U, // CU41 + 0U, // CU42 + 0U, // CUDTR + 0U, // CUSE + 208U, // CUTFU + 0U, // CUTFUOpt + 208U, // CUUTF + 0U, // CUUTFOpt + 0U, // CUXTR + 0U, // CVB + 0U, // CVBG + 0U, // CVBY + 0U, // CVD + 0U, // CVDG + 0U, // CVDY + 0U, // CXBR + 0U, // CXFBR + 82U, // CXFBRA + 0U, // CXFR + 82U, // CXFTR + 0U, // CXGBR + 82U, // CXGBRA + 0U, // CXGR + 0U, // CXGTR + 82U, // CXGTRA + 82U, // CXLFBR + 82U, // CXLFTR + 82U, // CXLGBR + 82U, // CXLGTR + 0U, // CXPT + 0U, // CXR + 0U, // CXSTR + 0U, // CXTR + 0U, // CXUTR + 0U, // CXZT + 0U, // CY + 0U, // CZDT + 0U, // CZXT + 0U, // D + 0U, // DD + 0U, // DDB + 0U, // DDBR + 0U, // DDR + 0U, // DDTR + 1024U, // DDTRA + 0U, // DE + 0U, // DEB + 0U, // DEBR + 0U, // DER + 192U, // DFLTCC + 112U, // DIAG + 50400U, // DIDBR + 50400U, // DIEBR + 0U, // DL + 0U, // DLG + 0U, // DLGR + 0U, // DLR + 0U, // DP + 0U, // DR + 0U, // DSG + 0U, // DSGF + 0U, // DSGFR + 0U, // DSGR + 0U, // DXBR + 0U, // DXR + 0U, // DXTR + 1024U, // DXTRA + 0U, // EAR + 112U, // ECAG + 0U, // ECCTR + 0U, // ECPGA + 192U, // ECTG + 0U, // ED + 0U, // EDMK + 0U, // EEDTR + 0U, // EEXTR + 0U, // EFPC + 0U, // EPAIR + 0U, // EPAR + 0U, // EPCTR + 0U, // EPSW + 0U, // EREG + 0U, // EREGG + 0U, // ESAIR + 0U, // ESAR + 0U, // ESDTR + 0U, // ESEA + 0U, // ESTA + 0U, // ESXTR + 0U, // ETND + 0U, // EX + 0U, // EXRL + 34U, // FIDBR + 82U, // FIDBRA + 0U, // FIDR + 82U, // FIDTR + 34U, // FIEBR + 82U, // FIEBRA + 0U, // FIER + 34U, // FIXBR + 82U, // FIXBRA + 0U, // FIXR + 82U, // FIXTR + 0U, // FLOGR + 0U, // HDR + 0U, // HER + 0U, // HSCH + 0U, // IAC + 0U, // IC + 0U, // IC32 + 0U, // IC32Y + 0U, // ICM + 0U, // ICMH + 0U, // ICMY + 0U, // ICY + 1200U, // IDTE + 176U, // IDTEOpt + 176U, // IEDTR + 176U, // IEXTR + 0U, // IIHF + 0U, // IIHH + 0U, // IIHL + 0U, // IILF + 0U, // IILH + 0U, // IILL + 0U, // IPK + 0U, // IPM + 1024U, // IPTE + 0U, // IPTEOpt + 0U, // IPTEOptOpt + 0U, // IRBM + 0U, // ISKE + 0U, // IVSK + 0U, // InsnE + 4U, // InsnRI + 2290U, // InsnRIE + 1U, // InsnRIL + 5U, // InsnRILU + 5U, // InsnRIS + 0U, // InsnRR + 34U, // InsnRRE + 3314U, // InsnRRF + 20722U, // InsnRRS + 5362U, // InsnRS + 5362U, // InsnRSE + 2290U, // InsnRSI + 5362U, // InsnRSY + 33U, // InsnRX + 33U, // InsnRXE + 6386U, // InsnRXF + 33U, // InsnRXY + 0U, // InsnS + 6U, // InsnSI + 6U, // InsnSIL + 7U, // InsnSIY + 0U, // InsnSS + 35U, // InsnSSE + 7411U, // InsnSSF + 8434U, // InsnVRI + 19698U, // InsnVRR + 0U, // InsnVRS + 7U, // InsnVRV + 9457U, // InsnVRX + 10483U, // InsnVSI + 0U, // J + 0U, // JAsmE + 0U, // JAsmH + 0U, // JAsmHE + 0U, // JAsmL + 0U, // JAsmLE + 0U, // JAsmLH + 0U, // JAsmM + 0U, // JAsmNE + 0U, // JAsmNH + 0U, // JAsmNHE + 0U, // JAsmNL + 0U, // JAsmNLE + 0U, // JAsmNLH + 0U, // JAsmNM + 0U, // JAsmNO + 0U, // JAsmNP + 0U, // JAsmNZ + 0U, // JAsmO + 0U, // JAsmP + 0U, // JAsmZ + 0U, // JG + 0U, // JGAsmE + 0U, // JGAsmH + 0U, // JGAsmHE + 0U, // JGAsmL + 0U, // JGAsmLE + 0U, // JGAsmLH + 0U, // JGAsmM + 0U, // JGAsmNE + 0U, // JGAsmNH + 0U, // JGAsmNHE + 0U, // JGAsmNL + 0U, // JGAsmNLE + 0U, // JGAsmNLH + 0U, // JGAsmNM + 0U, // JGAsmNO + 0U, // JGAsmNP + 0U, // JGAsmNZ + 0U, // JGAsmO + 0U, // JGAsmP + 0U, // JGAsmZ + 0U, // KDB + 0U, // KDBR + 0U, // KDSA + 0U, // KDTR + 0U, // KEB + 0U, // KEBR + 0U, // KIMD + 0U, // KLMD + 0U, // KM + 176U, // KMA + 0U, // KMAC + 0U, // KMC + 176U, // KMCTR + 0U, // KMF + 0U, // KMO + 0U, // KXBR + 0U, // KXTR + 0U, // L + 0U, // LA + 112U, // LAA + 112U, // LAAG + 112U, // LAAL + 112U, // LAALG + 0U, // LAE + 0U, // LAEY + 112U, // LAM + 112U, // LAMY + 112U, // LAN + 112U, // LANG + 112U, // LAO + 112U, // LAOG + 0U, // LARL + 0U, // LASP + 0U, // LAT + 112U, // LAX + 112U, // LAXG + 0U, // LAY + 0U, // LB + 0U, // LBEAR + 0U, // LBH + 0U, // LBR + 208U, // LCBB + 0U, // LCCTL + 0U, // LCDBR + 0U, // LCDFR + 0U, // LCDFR_32 + 0U, // LCDR + 0U, // LCEBR + 0U, // LCER + 0U, // LCGFR + 0U, // LCGR + 0U, // LCR + 112U, // LCTL + 112U, // LCTLG + 0U, // LCXBR + 0U, // LCXR + 0U, // LD + 0U, // LDE + 0U, // LDE32 + 0U, // LDEB + 0U, // LDEBR + 0U, // LDER + 96U, // LDETR + 0U, // LDGR + 0U, // LDR + 0U, // LDR32 + 0U, // LDXBR + 82U, // LDXBRA + 0U, // LDXR + 82U, // LDXTR + 0U, // LDY + 0U, // LE + 0U, // LEDBR + 82U, // LEDBRA + 0U, // LEDR + 82U, // LEDTR + 0U, // LER + 0U, // LEXBR + 82U, // LEXBRA + 0U, // LEXR + 0U, // LEY + 0U, // LFAS + 0U, // LFH + 0U, // LFHAT + 0U, // LFPC + 0U, // LG + 0U, // LGAT + 0U, // LGB + 0U, // LGBR + 0U, // LGDR + 0U, // LGF + 0U, // LGFI + 0U, // LGFR + 0U, // LGFRL + 0U, // LGG + 0U, // LGH + 0U, // LGHI + 0U, // LGHR + 0U, // LGHRL + 0U, // LGR + 0U, // LGRL + 0U, // LGSC + 0U, // LH + 0U, // LHH + 0U, // LHI + 0U, // LHR + 0U, // LHRL + 0U, // LHY + 0U, // LLC + 0U, // LLCH + 0U, // LLCR + 0U, // LLGC + 0U, // LLGCR + 0U, // LLGF + 0U, // LLGFAT + 0U, // LLGFR + 0U, // LLGFRL + 0U, // LLGFSG + 0U, // LLGH + 0U, // LLGHR + 0U, // LLGHRL + 0U, // LLGT + 0U, // LLGTAT + 0U, // LLGTR + 0U, // LLH + 0U, // LLHH + 0U, // LLHR + 0U, // LLHRL + 0U, // LLIHF + 0U, // LLIHH + 0U, // LLIHL + 0U, // LLILF + 0U, // LLILH + 0U, // LLILL + 0U, // LLZRGF + 112U, // LM + 33904U, // LMD + 112U, // LMG + 112U, // LMH + 112U, // LMY + 0U, // LNDBR + 0U, // LNDFR + 0U, // LNDFR_32 + 0U, // LNDR + 0U, // LNEBR + 0U, // LNER + 0U, // LNGFR + 0U, // LNGR + 0U, // LNR + 0U, // LNXBR + 0U, // LNXR + 0U, // LOC + 208U, // LOCAsm + 0U, // LOCAsmE + 0U, // LOCAsmH + 0U, // LOCAsmHE + 0U, // LOCAsmL + 0U, // LOCAsmLE + 0U, // LOCAsmLH + 0U, // LOCAsmM + 0U, // LOCAsmNE + 0U, // LOCAsmNH + 0U, // LOCAsmNHE + 0U, // LOCAsmNL + 0U, // LOCAsmNLE + 0U, // LOCAsmNLH + 0U, // LOCAsmNM + 0U, // LOCAsmNO + 0U, // LOCAsmNP + 0U, // LOCAsmNZ + 0U, // LOCAsmO + 0U, // LOCAsmP + 0U, // LOCAsmZ + 0U, // LOCFH + 208U, // LOCFHAsm + 0U, // LOCFHAsmE + 0U, // LOCFHAsmH + 0U, // LOCFHAsmHE + 0U, // LOCFHAsmL + 0U, // LOCFHAsmLE + 0U, // LOCFHAsmLH + 0U, // LOCFHAsmM + 0U, // LOCFHAsmNE + 0U, // LOCFHAsmNH + 0U, // LOCFHAsmNHE + 0U, // LOCFHAsmNL + 0U, // LOCFHAsmNLE + 0U, // LOCFHAsmNLH + 0U, // LOCFHAsmNM + 0U, // LOCFHAsmNO + 0U, // LOCFHAsmNP + 0U, // LOCFHAsmNZ + 0U, // LOCFHAsmO + 0U, // LOCFHAsmP + 0U, // LOCFHAsmZ + 0U, // LOCFHR + 256U, // LOCFHRAsm + 0U, // LOCFHRAsmE + 0U, // LOCFHRAsmH + 0U, // LOCFHRAsmHE + 0U, // LOCFHRAsmL + 0U, // LOCFHRAsmLE + 0U, // LOCFHRAsmLH + 0U, // LOCFHRAsmM + 0U, // LOCFHRAsmNE + 0U, // LOCFHRAsmNH + 0U, // LOCFHRAsmNHE + 0U, // LOCFHRAsmNL + 0U, // LOCFHRAsmNLE + 0U, // LOCFHRAsmNLH + 0U, // LOCFHRAsmNM + 0U, // LOCFHRAsmNO + 0U, // LOCFHRAsmNP + 0U, // LOCFHRAsmNZ + 0U, // LOCFHRAsmO + 0U, // LOCFHRAsmP + 0U, // LOCFHRAsmZ + 0U, // LOCG + 208U, // LOCGAsm + 0U, // LOCGAsmE + 0U, // LOCGAsmH + 0U, // LOCGAsmHE + 0U, // LOCGAsmL + 0U, // LOCGAsmLE + 0U, // LOCGAsmLH + 0U, // LOCGAsmM + 0U, // LOCGAsmNE + 0U, // LOCGAsmNH + 0U, // LOCGAsmNHE + 0U, // LOCGAsmNL + 0U, // LOCGAsmNLE + 0U, // LOCGAsmNLH + 0U, // LOCGAsmNM + 0U, // LOCGAsmNO + 0U, // LOCGAsmNP + 0U, // LOCGAsmNZ + 0U, // LOCGAsmO + 0U, // LOCGAsmP + 0U, // LOCGAsmZ + 0U, // LOCGHI + 256U, // LOCGHIAsm + 0U, // LOCGHIAsmE + 0U, // LOCGHIAsmH + 0U, // LOCGHIAsmHE + 0U, // LOCGHIAsmL + 0U, // LOCGHIAsmLE + 0U, // LOCGHIAsmLH + 0U, // LOCGHIAsmM + 0U, // LOCGHIAsmNE + 0U, // LOCGHIAsmNH + 0U, // LOCGHIAsmNHE + 0U, // LOCGHIAsmNL + 0U, // LOCGHIAsmNLE + 0U, // LOCGHIAsmNLH + 0U, // LOCGHIAsmNM + 0U, // LOCGHIAsmNO + 0U, // LOCGHIAsmNP + 0U, // LOCGHIAsmNZ + 0U, // LOCGHIAsmO + 0U, // LOCGHIAsmP + 0U, // LOCGHIAsmZ + 0U, // LOCGR + 256U, // LOCGRAsm + 0U, // LOCGRAsmE + 0U, // LOCGRAsmH + 0U, // LOCGRAsmHE + 0U, // LOCGRAsmL + 0U, // LOCGRAsmLE + 0U, // LOCGRAsmLH + 0U, // LOCGRAsmM + 0U, // LOCGRAsmNE + 0U, // LOCGRAsmNH + 0U, // LOCGRAsmNHE + 0U, // LOCGRAsmNL + 0U, // LOCGRAsmNLE + 0U, // LOCGRAsmNLH + 0U, // LOCGRAsmNM + 0U, // LOCGRAsmNO + 0U, // LOCGRAsmNP + 0U, // LOCGRAsmNZ + 0U, // LOCGRAsmO + 0U, // LOCGRAsmP + 0U, // LOCGRAsmZ + 0U, // LOCHHI + 256U, // LOCHHIAsm + 0U, // LOCHHIAsmE + 0U, // LOCHHIAsmH + 0U, // LOCHHIAsmHE + 0U, // LOCHHIAsmL + 0U, // LOCHHIAsmLE + 0U, // LOCHHIAsmLH + 0U, // LOCHHIAsmM + 0U, // LOCHHIAsmNE + 0U, // LOCHHIAsmNH + 0U, // LOCHHIAsmNHE + 0U, // LOCHHIAsmNL + 0U, // LOCHHIAsmNLE + 0U, // LOCHHIAsmNLH + 0U, // LOCHHIAsmNM + 0U, // LOCHHIAsmNO + 0U, // LOCHHIAsmNP + 0U, // LOCHHIAsmNZ + 0U, // LOCHHIAsmO + 0U, // LOCHHIAsmP + 0U, // LOCHHIAsmZ + 0U, // LOCHI + 256U, // LOCHIAsm + 0U, // LOCHIAsmE + 0U, // LOCHIAsmH + 0U, // LOCHIAsmHE + 0U, // LOCHIAsmL + 0U, // LOCHIAsmLE + 0U, // LOCHIAsmLH + 0U, // LOCHIAsmM + 0U, // LOCHIAsmNE + 0U, // LOCHIAsmNH + 0U, // LOCHIAsmNHE + 0U, // LOCHIAsmNL + 0U, // LOCHIAsmNLE + 0U, // LOCHIAsmNLH + 0U, // LOCHIAsmNM + 0U, // LOCHIAsmNO + 0U, // LOCHIAsmNP + 0U, // LOCHIAsmNZ + 0U, // LOCHIAsmO + 0U, // LOCHIAsmP + 0U, // LOCHIAsmZ + 0U, // LOCR + 256U, // LOCRAsm + 0U, // LOCRAsmE + 0U, // LOCRAsmH + 0U, // LOCRAsmHE + 0U, // LOCRAsmL + 0U, // LOCRAsmLE + 0U, // LOCRAsmLH + 0U, // LOCRAsmM + 0U, // LOCRAsmNE + 0U, // LOCRAsmNH + 0U, // LOCRAsmNHE + 0U, // LOCRAsmNL + 0U, // LOCRAsmNLE + 0U, // LOCRAsmNLH + 0U, // LOCRAsmNM + 0U, // LOCRAsmNO + 0U, // LOCRAsmNP + 0U, // LOCRAsmNZ + 0U, // LOCRAsmO + 0U, // LOCRAsmP + 0U, // LOCRAsmZ + 0U, // LPCTL + 64U, // LPD + 0U, // LPDBR + 0U, // LPDFR + 0U, // LPDFR_32 + 64U, // LPDG + 0U, // LPDR + 0U, // LPEBR + 0U, // LPER + 0U, // LPGFR + 0U, // LPGR + 0U, // LPP + 0U, // LPQ + 0U, // LPR + 0U, // LPSW + 0U, // LPSWE + 0U, // LPSWEY + 50400U, // LPTEA + 0U, // LPXBR + 0U, // LPXR + 0U, // LR + 0U, // LRA + 0U, // LRAG + 0U, // LRAY + 0U, // LRDR + 0U, // LRER + 0U, // LRL + 0U, // LRV + 0U, // LRVG + 0U, // LRVGR + 0U, // LRVH + 0U, // LRVR + 0U, // LSCTL + 0U, // LT + 0U, // LTDBR + 0U, // LTDBRCompare + 0U, // LTDR + 0U, // LTDTR + 0U, // LTEBR + 0U, // LTEBRCompare + 0U, // LTER + 0U, // LTG + 0U, // LTGF + 0U, // LTGFR + 0U, // LTGR + 0U, // LTR + 0U, // LTXBR + 0U, // LTXBRCompare + 0U, // LTXR + 0U, // LTXTR + 0U, // LURA + 0U, // LURAG + 0U, // LXD + 0U, // LXDB + 0U, // LXDBR + 0U, // LXDR + 96U, // LXDTR + 0U, // LXE + 0U, // LXEB + 0U, // LXEBR + 0U, // LXER + 0U, // LXR + 0U, // LY + 0U, // LZDR + 0U, // LZER + 0U, // LZRF + 0U, // LZRG + 0U, // LZXR + 0U, // M + 272U, // MAD + 272U, // MADB + 224U, // MADBR + 224U, // MADR + 272U, // MAE + 272U, // MAEB + 224U, // MAEBR + 224U, // MAER + 272U, // MAY + 272U, // MAYH + 224U, // MAYHR + 272U, // MAYL + 224U, // MAYLR + 224U, // MAYR + 0U, // MC + 0U, // MD + 0U, // MDB + 0U, // MDBR + 0U, // MDE + 0U, // MDEB + 0U, // MDEBR + 0U, // MDER + 0U, // MDR + 0U, // MDTR + 1024U, // MDTRA + 0U, // ME + 0U, // MEE + 0U, // MEEB + 0U, // MEEBR + 0U, // MEER + 0U, // MER + 0U, // MFY + 0U, // MG + 0U, // MGH + 0U, // MGHI + 0U, // MGRK + 0U, // MH + 0U, // MHI + 0U, // MHY + 0U, // ML + 0U, // MLG + 0U, // MLGR + 0U, // MLR + 0U, // MP + 0U, // MR + 0U, // MS + 0U, // MSC + 0U, // MSCH + 272U, // MSD + 272U, // MSDB + 224U, // MSDBR + 224U, // MSDR + 272U, // MSE + 272U, // MSEB + 224U, // MSEBR + 224U, // MSER + 0U, // MSFI + 0U, // MSG + 0U, // MSGC + 0U, // MSGF + 0U, // MSGFI + 0U, // MSGFR + 0U, // MSGR + 0U, // MSGRKC + 0U, // MSR + 0U, // MSRKC + 0U, // MSTA + 0U, // MSY + 0U, // MVC + 0U, // MVCDK + 0U, // MVCIN + 0U, // MVCK + 0U, // MVCL + 144U, // MVCLE + 144U, // MVCLU + 192U, // MVCOS + 0U, // MVCP + 0U, // MVCRL + 0U, // MVCS + 0U, // MVCSK + 0U, // MVGHI + 0U, // MVHHI + 0U, // MVHI + 0U, // MVI + 0U, // MVIY + 0U, // MVN + 0U, // MVO + 0U, // MVPG + 0U, // MVST + 0U, // MVZ + 0U, // MXBR + 0U, // MXD + 0U, // MXDB + 0U, // MXDBR + 0U, // MXDR + 0U, // MXR + 0U, // MXTR + 1024U, // MXTRA + 288U, // MY + 288U, // MYH + 0U, // MYHR + 288U, // MYL + 0U, // MYLR + 0U, // MYR + 0U, // N + 0U, // NC + 0U, // NCGRK + 0U, // NCRK + 0U, // NG + 0U, // NGR + 0U, // NGRK + 0U, // NI + 0U, // NIAI + 0U, // NIHF + 0U, // NIHH + 0U, // NIHL + 0U, // NILF + 0U, // NILH + 0U, // NILL + 0U, // NIY + 0U, // NNGRK + 0U, // NNPA + 0U, // NNRK + 0U, // NOGRK + 0U, // NOP_bare + 0U, // NORK + 0U, // NR + 0U, // NRK + 0U, // NTSTG + 0U, // NXGRK + 0U, // NXRK + 0U, // NY + 0U, // O + 0U, // OC + 0U, // OCGRK + 0U, // OCRK + 0U, // OG + 0U, // OGR + 0U, // OGRK + 0U, // OI + 0U, // OIHF + 0U, // OIHH + 0U, // OIHL + 0U, // OILF + 0U, // OILH + 0U, // OILL + 0U, // OIY + 0U, // OR + 0U, // ORK + 0U, // OY + 0U, // PACK + 0U, // PALB + 0U, // PC + 0U, // PCC + 0U, // PCKMO + 0U, // PFD + 0U, // PFDRL + 0U, // PFMF + 0U, // PFPO + 0U, // PGIN + 0U, // PGOUT + 0U, // PKA + 0U, // PKU + 34016U, // PLO + 0U, // POPCNT + 96U, // POPCNTOpt + 96U, // PPA + 0U, // PPNO + 0U, // PR + 0U, // PRNO + 0U, // PT + 0U, // PTF + 0U, // PTFF + 0U, // PTI + 0U, // PTLB + 50400U, // QADTR + 50400U, // QAXTR + 0U, // QCTRI + 0U, // QPACI + 0U, // QSI + 0U, // RCHP + 1200U, // RDP + 176U, // RDPOpt + 50480U, // RISBG + 50480U, // RISBG32 + 50480U, // RISBGN + 50480U, // RISBHG + 50480U, // RISBLG + 112U, // RLL + 112U, // RLLG + 50480U, // RNSBG + 50480U, // ROSBG + 0U, // RP + 0U, // RRBE + 0U, // RRBM + 50400U, // RRDTR + 50400U, // RRXTR + 0U, // RSCH + 50480U, // RXSBG + 0U, // S + 0U, // SAC + 0U, // SACF + 0U, // SAL + 0U, // SAM24 + 0U, // SAM31 + 0U, // SAM64 + 0U, // SAR + 0U, // SCCTR + 0U, // SCHM + 0U, // SCK + 0U, // SCKC + 0U, // SCKPF + 0U, // SD + 0U, // SDB + 0U, // SDBR + 0U, // SDR + 0U, // SDTR + 1024U, // SDTRA + 0U, // SE + 0U, // SEB + 0U, // SEBR + 8U, // SELFHR + 1200U, // SELFHRAsm + 176U, // SELFHRAsmE + 176U, // SELFHRAsmH + 176U, // SELFHRAsmHE + 176U, // SELFHRAsmL + 176U, // SELFHRAsmLE + 176U, // SELFHRAsmLH + 176U, // SELFHRAsmM + 176U, // SELFHRAsmNE + 176U, // SELFHRAsmNH + 176U, // SELFHRAsmNHE + 176U, // SELFHRAsmNL + 176U, // SELFHRAsmNLE + 176U, // SELFHRAsmNLH + 176U, // SELFHRAsmNM + 176U, // SELFHRAsmNO + 176U, // SELFHRAsmNP + 176U, // SELFHRAsmNZ + 176U, // SELFHRAsmO + 176U, // SELFHRAsmP + 176U, // SELFHRAsmZ + 8U, // SELGR + 1200U, // SELGRAsm + 176U, // SELGRAsmE + 176U, // SELGRAsmH + 176U, // SELGRAsmHE + 176U, // SELGRAsmL + 176U, // SELGRAsmLE + 176U, // SELGRAsmLH + 176U, // SELGRAsmM + 176U, // SELGRAsmNE + 176U, // SELGRAsmNH + 176U, // SELGRAsmNHE + 176U, // SELGRAsmNL + 176U, // SELGRAsmNLE + 176U, // SELGRAsmNLH + 176U, // SELGRAsmNM + 176U, // SELGRAsmNO + 176U, // SELGRAsmNP + 176U, // SELGRAsmNZ + 176U, // SELGRAsmO + 176U, // SELGRAsmP + 176U, // SELGRAsmZ + 8U, // SELR + 1200U, // SELRAsm + 176U, // SELRAsmE + 176U, // SELRAsmH + 176U, // SELRAsmHE + 176U, // SELRAsmL + 176U, // SELRAsmLE + 176U, // SELRAsmLH + 176U, // SELRAsmM + 176U, // SELRAsmNE + 176U, // SELRAsmNH + 176U, // SELRAsmNHE + 176U, // SELRAsmNL + 176U, // SELRAsmNLE + 176U, // SELRAsmNLH + 176U, // SELRAsmNM + 176U, // SELRAsmNO + 176U, // SELRAsmNP + 176U, // SELRAsmNZ + 176U, // SELRAsmO + 176U, // SELRAsmP + 176U, // SELRAsmZ + 0U, // SER + 0U, // SFASR + 0U, // SFPC + 0U, // SG + 0U, // SGF + 0U, // SGFR + 0U, // SGH + 0U, // SGR + 0U, // SGRK + 0U, // SH + 0U, // SHHHR + 0U, // SHHLR + 0U, // SHY + 0U, // SIE + 0U, // SIGA + 112U, // SIGP + 0U, // SL + 0U, // SLA + 112U, // SLAG + 112U, // SLAK + 0U, // SLB + 0U, // SLBG + 0U, // SLBGR + 0U, // SLBR + 0U, // SLDA + 0U, // SLDL + 288U, // SLDT + 0U, // SLFI + 0U, // SLG + 0U, // SLGF + 0U, // SLGFI + 0U, // SLGFR + 0U, // SLGR + 0U, // SLGRK + 0U, // SLHHHR + 0U, // SLHHLR + 0U, // SLL + 112U, // SLLG + 112U, // SLLK + 0U, // SLR + 0U, // SLRK + 288U, // SLXT + 0U, // SLY + 0U, // SORTL + 0U, // SP + 0U, // SPCTR + 0U, // SPKA + 0U, // SPM + 0U, // SPT + 0U, // SPX + 0U, // SQD + 0U, // SQDB + 0U, // SQDBR + 0U, // SQDR + 0U, // SQE + 0U, // SQEB + 0U, // SQEBR + 0U, // SQER + 0U, // SQXBR + 0U, // SQXR + 0U, // SR + 0U, // SRA + 112U, // SRAG + 112U, // SRAK + 0U, // SRDA + 0U, // SRDL + 288U, // SRDT + 0U, // SRK + 0U, // SRL + 112U, // SRLG + 112U, // SRLK + 0U, // SRNM + 0U, // SRNMB + 0U, // SRNMT + 320U, // SRP + 0U, // SRST + 0U, // SRSTU + 288U, // SRXT + 0U, // SSAIR + 0U, // SSAR + 0U, // SSCH + 96U, // SSKE + 0U, // SSKEOpt + 0U, // SSM + 0U, // ST + 112U, // STAM + 112U, // STAMY + 0U, // STAP + 0U, // STBEAR + 0U, // STC + 0U, // STCH + 0U, // STCK + 0U, // STCKC + 0U, // STCKE + 0U, // STCKF + 35U, // STCM + 35U, // STCMH + 35U, // STCMY + 0U, // STCPS + 0U, // STCRW + 112U, // STCTG + 112U, // STCTL + 0U, // STCY + 0U, // STD + 0U, // STDY + 0U, // STE + 0U, // STEY + 0U, // STFH + 0U, // STFL + 0U, // STFLE + 0U, // STFPC + 0U, // STG + 0U, // STGRL + 0U, // STGSC + 0U, // STH + 0U, // STHH + 0U, // STHRL + 0U, // STHY + 0U, // STIDP + 112U, // STM + 112U, // STMG + 112U, // STMH + 112U, // STMY + 0U, // STNSM + 0U, // STOC + 256U, // STOCAsm + 0U, // STOCAsmE + 0U, // STOCAsmH + 0U, // STOCAsmHE + 0U, // STOCAsmL + 0U, // STOCAsmLE + 0U, // STOCAsmLH + 0U, // STOCAsmM + 0U, // STOCAsmNE + 0U, // STOCAsmNH + 0U, // STOCAsmNHE + 0U, // STOCAsmNL + 0U, // STOCAsmNLE + 0U, // STOCAsmNLH + 0U, // STOCAsmNM + 0U, // STOCAsmNO + 0U, // STOCAsmNP + 0U, // STOCAsmNZ + 0U, // STOCAsmO + 0U, // STOCAsmP + 0U, // STOCAsmZ + 0U, // STOCFH + 256U, // STOCFHAsm + 0U, // STOCFHAsmE + 0U, // STOCFHAsmH + 0U, // STOCFHAsmHE + 0U, // STOCFHAsmL + 0U, // STOCFHAsmLE + 0U, // STOCFHAsmLH + 0U, // STOCFHAsmM + 0U, // STOCFHAsmNE + 0U, // STOCFHAsmNH + 0U, // STOCFHAsmNHE + 0U, // STOCFHAsmNL + 0U, // STOCFHAsmNLE + 0U, // STOCFHAsmNLH + 0U, // STOCFHAsmNM + 0U, // STOCFHAsmNO + 0U, // STOCFHAsmNP + 0U, // STOCFHAsmNZ + 0U, // STOCFHAsmO + 0U, // STOCFHAsmP + 0U, // STOCFHAsmZ + 0U, // STOCG + 256U, // STOCGAsm + 0U, // STOCGAsmE + 0U, // STOCGAsmH + 0U, // STOCGAsmHE + 0U, // STOCGAsmL + 0U, // STOCGAsmLE + 0U, // STOCGAsmLH + 0U, // STOCGAsmM + 0U, // STOCGAsmNE + 0U, // STOCGAsmNH + 0U, // STOCGAsmNHE + 0U, // STOCGAsmNL + 0U, // STOCGAsmNLE + 0U, // STOCGAsmNLH + 0U, // STOCGAsmNM + 0U, // STOCGAsmNO + 0U, // STOCGAsmNP + 0U, // STOCGAsmNZ + 0U, // STOCGAsmO + 0U, // STOCGAsmP + 0U, // STOCGAsmZ + 0U, // STOSM + 0U, // STPQ + 0U, // STPT + 0U, // STPX + 0U, // STRAG + 0U, // STRL + 0U, // STRV + 0U, // STRVG + 0U, // STRVH + 0U, // STSCH + 0U, // STSI + 0U, // STURA + 0U, // STURG + 0U, // STY + 0U, // SU + 0U, // SUR + 0U, // SVC + 0U, // SW + 0U, // SWR + 0U, // SXBR + 0U, // SXR + 0U, // SXTR + 1024U, // SXTRA + 0U, // SY + 0U, // TABORT + 0U, // TAM + 0U, // TAR + 0U, // TB + 34U, // TBDR + 34U, // TBEDR + 0U, // TBEGIN + 0U, // TBEGINC + 0U, // TCDB + 0U, // TCEB + 0U, // TCXB + 0U, // TDCDT + 0U, // TDCET + 0U, // TDCXT + 0U, // TDGDT + 0U, // TDGET + 0U, // TDGXT + 0U, // TEND + 0U, // THDER + 0U, // THDR + 0U, // TM + 0U, // TMHH + 0U, // TMHL + 0U, // TMLH + 0U, // TMLL + 0U, // TMY + 0U, // TP + 0U, // TPI + 0U, // TPROT + 0U, // TR + 112U, // TRACE + 112U, // TRACG + 0U, // TRAP2 + 0U, // TRAP4 + 0U, // TRE + 208U, // TROO + 0U, // TROOOpt + 208U, // TROT + 0U, // TROTOpt + 0U, // TRT + 0U, // TRTE + 0U, // TRTEOpt + 208U, // TRTO + 0U, // TRTOOpt + 0U, // TRTR + 0U, // TRTRE + 0U, // TRTREOpt + 208U, // TRTT + 0U, // TRTTOpt + 0U, // TS + 0U, // TSCH + 0U, // UNPK + 0U, // UNPKA + 0U, // UNPKU + 0U, // UPT + 1024U, // VA + 0U, // VAB + 1024U, // VAC + 1024U, // VACC + 0U, // VACCB + 1024U, // VACCC + 1024U, // VACCCQ + 0U, // VACCF + 0U, // VACCG + 0U, // VACCH + 0U, // VACCQ + 1024U, // VACQ + 0U, // VAF + 0U, // VAG + 0U, // VAH + 17408U, // VAP + 0U, // VAQ + 1024U, // VAVG + 0U, // VAVGB + 0U, // VAVGF + 0U, // VAVGG + 0U, // VAVGH + 1024U, // VAVGL + 0U, // VAVGLB + 0U, // VAVGLF + 0U, // VAVGLG + 0U, // VAVGLH + 0U, // VBPERM + 1120U, // VCDG + 1120U, // VCDGB + 1120U, // VCDLG + 1120U, // VCDLGB + 1120U, // VCEFB + 1120U, // VCELFB + 1024U, // VCEQ + 0U, // VCEQB + 0U, // VCEQBS + 0U, // VCEQF + 0U, // VCEQFS + 0U, // VCEQG + 0U, // VCEQGS + 0U, // VCEQH + 0U, // VCEQHS + 1120U, // VCFEB + 1120U, // VCFN + 1120U, // VCFPL + 1120U, // VCFPS + 1120U, // VCGD + 1120U, // VCGDB + 1024U, // VCH + 0U, // VCHB + 0U, // VCHBS + 0U, // VCHF + 0U, // VCHFS + 0U, // VCHG + 0U, // VCHGS + 0U, // VCHH + 0U, // VCHHS + 1024U, // VCHL + 0U, // VCHLB + 0U, // VCHLBS + 0U, // VCHLF + 0U, // VCHLFS + 0U, // VCHLG + 0U, // VCHLGS + 0U, // VCHLH + 0U, // VCHLHS + 0U, // VCKSM + 1120U, // VCLFEB + 1120U, // VCLFNH + 1120U, // VCLFNL + 1120U, // VCLFP + 1120U, // VCLGD + 1120U, // VCLGDB + 96U, // VCLZ + 0U, // VCLZB + 96U, // VCLZDP + 0U, // VCLZF + 0U, // VCLZG + 0U, // VCLZH + 1120U, // VCNF + 96U, // VCP + 1024U, // VCRNF + 1120U, // VCSFP + 1024U, // VCSPH + 96U, // VCTZ + 0U, // VCTZB + 0U, // VCTZF + 0U, // VCTZG + 0U, // VCTZH + 96U, // VCVB + 96U, // VCVBG + 1120U, // VCVBGOpt + 1120U, // VCVBOpt + 4432U, // VCVD + 4432U, // VCVDG + 17408U, // VDP + 96U, // VEC + 0U, // VECB + 0U, // VECF + 0U, // VECG + 0U, // VECH + 96U, // VECL + 0U, // VECLB + 0U, // VECLF + 0U, // VECLG + 0U, // VECLH + 50400U, // VERIM + 50400U, // VERIMB + 50400U, // VERIMF + 50400U, // VERIMG + 50400U, // VERIMH + 50288U, // VERLL + 112U, // VERLLB + 112U, // VERLLF + 112U, // VERLLG + 112U, // VERLLH + 1024U, // VERLLV + 0U, // VERLLVB + 0U, // VERLLVF + 0U, // VERLLVG + 0U, // VERLLVH + 50288U, // VESL + 112U, // VESLB + 112U, // VESLF + 112U, // VESLG + 112U, // VESLH + 1024U, // VESLV + 0U, // VESLVB + 0U, // VESLVF + 0U, // VESLVG + 0U, // VESLVH + 50288U, // VESRA + 112U, // VESRAB + 112U, // VESRAF + 112U, // VESRAG + 112U, // VESRAH + 1024U, // VESRAV + 0U, // VESRAVB + 0U, // VESRAVF + 0U, // VESRAVG + 0U, // VESRAVH + 50288U, // VESRL + 112U, // VESRLB + 112U, // VESRLF + 112U, // VESRLG + 112U, // VESRLH + 1024U, // VESRLV + 0U, // VESRLVB + 0U, // VESRLVF + 0U, // VESRLVG + 0U, // VESRLVH + 1024U, // VFA + 0U, // VFADB + 1024U, // VFAE + 1024U, // VFAEB + 1024U, // VFAEBS + 1024U, // VFAEF + 1024U, // VFAEFS + 1024U, // VFAEH + 1024U, // VFAEHS + 1024U, // VFAEZB + 1024U, // VFAEZBS + 1024U, // VFAEZF + 1024U, // VFAEZFS + 1024U, // VFAEZH + 1024U, // VFAEZHS + 0U, // VFASB + 1024U, // VFCE + 0U, // VFCEDB + 0U, // VFCEDBS + 0U, // VFCESB + 0U, // VFCESBS + 1024U, // VFCH + 0U, // VFCHDB + 0U, // VFCHDBS + 1024U, // VFCHE + 0U, // VFCHEDB + 0U, // VFCHEDBS + 0U, // VFCHESB + 0U, // VFCHESBS + 0U, // VFCHSB + 0U, // VFCHSBS + 1024U, // VFD + 0U, // VFDDB + 0U, // VFDSB + 1024U, // VFEE + 1024U, // VFEEB + 0U, // VFEEBS + 1024U, // VFEEF + 0U, // VFEEFS + 1024U, // VFEEH + 0U, // VFEEHS + 0U, // VFEEZB + 0U, // VFEEZBS + 0U, // VFEEZF + 0U, // VFEEZFS + 0U, // VFEEZH + 0U, // VFEEZHS + 1024U, // VFENE + 1024U, // VFENEB + 0U, // VFENEBS + 1024U, // VFENEF + 0U, // VFENEFS + 1024U, // VFENEH + 0U, // VFENEHS + 0U, // VFENEZB + 0U, // VFENEZBS + 0U, // VFENEZF + 0U, // VFENEZFS + 0U, // VFENEZH + 0U, // VFENEZHS + 1120U, // VFI + 1120U, // VFIDB + 1120U, // VFISB + 0U, // VFKEDB + 0U, // VFKEDBS + 0U, // VFKESB + 0U, // VFKESBS + 0U, // VFKHDB + 0U, // VFKHDBS + 0U, // VFKHEDB + 0U, // VFKHEDBS + 0U, // VFKHESB + 0U, // VFKHESBS + 0U, // VFKHSB + 0U, // VFKHSBS + 0U, // VFLCDB + 0U, // VFLCSB + 1120U, // VFLL + 0U, // VFLLS + 0U, // VFLNDB + 0U, // VFLNSB + 0U, // VFLPDB + 0U, // VFLPSB + 1120U, // VFLR + 1120U, // VFLRD + 1024U, // VFM + 1024U, // VFMA + 1024U, // VFMADB + 1024U, // VFMASB + 1024U, // VFMAX + 1024U, // VFMAXDB + 1024U, // VFMAXSB + 0U, // VFMDB + 1024U, // VFMIN + 1024U, // VFMINDB + 1024U, // VFMINSB + 1024U, // VFMS + 0U, // VFMSB + 1024U, // VFMSDB + 1024U, // VFMSSB + 1024U, // VFNMA + 1024U, // VFNMADB + 1024U, // VFNMASB + 1024U, // VFNMS + 1024U, // VFNMSDB + 1024U, // VFNMSSB + 1120U, // VFPSO + 96U, // VFPSODB + 96U, // VFPSOSB + 1024U, // VFS + 0U, // VFSDB + 1120U, // VFSQ + 0U, // VFSQDB + 0U, // VFSQSB + 0U, // VFSSB + 1376U, // VFTCI + 352U, // VFTCIDB + 352U, // VFTCISB + 0U, // VGBM + 8U, // VGEF + 9U, // VGEG + 1024U, // VGFM + 1024U, // VGFMA + 1024U, // VGFMAB + 1024U, // VGFMAF + 1024U, // VGFMAG + 1024U, // VGFMAH + 0U, // VGFMB + 0U, // VGFMF + 0U, // VGFMG + 0U, // VGFMH + 89U, // VGM + 41U, // VGMB + 41U, // VGMF + 41U, // VGMG + 41U, // VGMH + 1120U, // VISTR + 96U, // VISTRB + 0U, // VISTRBS + 96U, // VISTRF + 0U, // VISTRFS + 96U, // VISTRH + 0U, // VISTRHS + 0U, // VL + 208U, // VLAlign + 208U, // VLBB + 208U, // VLBR + 0U, // VLBRF + 0U, // VLBRG + 0U, // VLBRH + 0U, // VLBRQ + 208U, // VLBRREP + 0U, // VLBRREPF + 0U, // VLBRREPG + 0U, // VLBRREPH + 96U, // VLC + 0U, // VLCB + 0U, // VLCF + 0U, // VLCG + 0U, // VLCH + 1120U, // VLDE + 0U, // VLDEB + 320U, // VLEB + 368U, // VLEBRF + 384U, // VLEBRG + 400U, // VLEBRH + 1120U, // VLED + 1120U, // VLEDB + 368U, // VLEF + 384U, // VLEG + 400U, // VLEH + 256U, // VLEIB + 416U, // VLEIF + 432U, // VLEIG + 448U, // VLEIH + 208U, // VLER + 0U, // VLERF + 0U, // VLERG + 0U, // VLERH + 50288U, // VLGV + 112U, // VLGVB + 112U, // VLGVF + 112U, // VLGVG + 112U, // VLGVH + 96U, // VLIP + 112U, // VLL + 208U, // VLLEBRZ + 0U, // VLLEBRZE + 0U, // VLLEBRZF + 0U, // VLLEBRZG + 0U, // VLLEBRZH + 208U, // VLLEZ + 0U, // VLLEZB + 0U, // VLLEZF + 0U, // VLLEZG + 0U, // VLLEZH + 0U, // VLLEZLF + 112U, // VLM + 50288U, // VLMAlign + 96U, // VLP + 0U, // VLPB + 0U, // VLPF + 0U, // VLPG + 0U, // VLPH + 0U, // VLR + 208U, // VLREP + 0U, // VLREPB + 0U, // VLREPF + 0U, // VLREPG + 0U, // VLREPH + 304U, // VLRL + 112U, // VLRLR + 33856U, // VLVG + 64U, // VLVGB + 64U, // VLVGF + 64U, // VLVGG + 64U, // VLVGH + 0U, // VLVGP + 1024U, // VMAE + 1024U, // VMAEB + 1024U, // VMAEF + 1024U, // VMAEH + 1024U, // VMAH + 1024U, // VMAHB + 1024U, // VMAHF + 1024U, // VMAHH + 1024U, // VMAL + 1024U, // VMALB + 1024U, // VMALE + 1024U, // VMALEB + 1024U, // VMALEF + 1024U, // VMALEH + 1024U, // VMALF + 1024U, // VMALH + 1024U, // VMALHB + 1024U, // VMALHF + 1024U, // VMALHH + 1024U, // VMALHW + 1024U, // VMALO + 1024U, // VMALOB + 1024U, // VMALOF + 1024U, // VMALOH + 1024U, // VMAO + 1024U, // VMAOB + 1024U, // VMAOF + 1024U, // VMAOH + 1024U, // VME + 0U, // VMEB + 0U, // VMEF + 0U, // VMEH + 1024U, // VMH + 0U, // VMHB + 0U, // VMHF + 0U, // VMHH + 1024U, // VML + 0U, // VMLB + 1024U, // VMLE + 0U, // VMLEB + 0U, // VMLEF + 0U, // VMLEH + 0U, // VMLF + 1024U, // VMLH + 0U, // VMLHB + 0U, // VMLHF + 0U, // VMLHH + 0U, // VMLHW + 1024U, // VMLO + 0U, // VMLOB + 0U, // VMLOF + 0U, // VMLOH + 1024U, // VMN + 0U, // VMNB + 0U, // VMNF + 0U, // VMNG + 0U, // VMNH + 1024U, // VMNL + 0U, // VMNLB + 0U, // VMNLF + 0U, // VMNLG + 0U, // VMNLH + 1024U, // VMO + 0U, // VMOB + 0U, // VMOF + 0U, // VMOH + 17408U, // VMP + 1024U, // VMRH + 0U, // VMRHB + 0U, // VMRHF + 0U, // VMRHG + 0U, // VMRHH + 1024U, // VMRL + 0U, // VMRLB + 0U, // VMRLF + 0U, // VMRLG + 0U, // VMRLH + 1024U, // VMSL + 1024U, // VMSLG + 17408U, // VMSP + 1024U, // VMX + 0U, // VMXB + 0U, // VMXF + 0U, // VMXG + 0U, // VMXH + 1024U, // VMXL + 0U, // VMXLB + 0U, // VMXLF + 0U, // VMXLG + 0U, // VMXLH + 0U, // VN + 0U, // VNC + 0U, // VNN + 0U, // VNO + 0U, // VNX + 0U, // VO + 0U, // VOC + 0U, // VONE + 1024U, // VPDI + 1024U, // VPERM + 1024U, // VPK + 0U, // VPKF + 0U, // VPKG + 0U, // VPKH + 1024U, // VPKLS + 0U, // VPKLSF + 0U, // VPKLSFS + 0U, // VPKLSG + 0U, // VPKLSGS + 0U, // VPKLSH + 0U, // VPKLSHS + 1024U, // VPKS + 0U, // VPKSF + 0U, // VPKSFS + 0U, // VPKSG + 0U, // VPKSGS + 0U, // VPKSH + 0U, // VPKSHS + 304U, // VPKZ + 17408U, // VPKZR + 96U, // VPOPCT + 0U, // VPOPCTB + 0U, // VPOPCTF + 0U, // VPOPCTG + 0U, // VPOPCTH + 11600U, // VPSOP + 1488U, // VREP + 464U, // VREPB + 464U, // VREPF + 464U, // VREPG + 464U, // VREPH + 96U, // VREPI + 0U, // VREPIB + 0U, // VREPIF + 0U, // VREPIG + 0U, // VREPIH + 17408U, // VRP + 1024U, // VS + 0U, // VSB + 1024U, // VSBCBI + 1024U, // VSBCBIQ + 1024U, // VSBI + 1024U, // VSBIQ + 1024U, // VSCBI + 0U, // VSCBIB + 0U, // VSCBIF + 0U, // VSCBIG + 0U, // VSCBIH + 0U, // VSCBIQ + 10U, // VSCEF + 10U, // VSCEG + 1024U, // VSCHDP + 1024U, // VSCHP + 1024U, // VSCHSP + 1024U, // VSCHXP + 0U, // VSCSHP + 17408U, // VSDP + 96U, // VSEG + 0U, // VSEGB + 0U, // VSEGF + 0U, // VSEGH + 1024U, // VSEL + 0U, // VSF + 0U, // VSG + 0U, // VSH + 0U, // VSL + 0U, // VSLB + 17408U, // VSLD + 17408U, // VSLDB + 17408U, // VSP + 0U, // VSQ + 0U, // VSRA + 0U, // VSRAB + 17408U, // VSRD + 0U, // VSRL + 0U, // VSRLB + 11600U, // VSRP + 17408U, // VSRPR + 0U, // VST + 208U, // VSTAlign + 208U, // VSTBR + 0U, // VSTBRF + 0U, // VSTBRG + 0U, // VSTBRH + 0U, // VSTBRQ + 208U, // VSTEB + 480U, // VSTEBRF + 496U, // VSTEBRG + 512U, // VSTEBRH + 480U, // VSTEF + 496U, // VSTEG + 512U, // VSTEH + 208U, // VSTER + 0U, // VSTERF + 0U, // VSTERG + 0U, // VSTERH + 112U, // VSTL + 112U, // VSTM + 50288U, // VSTMAlign + 1024U, // VSTRC + 1024U, // VSTRCB + 1024U, // VSTRCBS + 1024U, // VSTRCF + 1024U, // VSTRCFS + 1024U, // VSTRCH + 1024U, // VSTRCHS + 1024U, // VSTRCZB + 1024U, // VSTRCZBS + 1024U, // VSTRCZF + 1024U, // VSTRCZFS + 1024U, // VSTRCZH + 1024U, // VSTRCZHS + 304U, // VSTRL + 112U, // VSTRLR + 1024U, // VSTRS + 1024U, // VSTRSB + 1024U, // VSTRSF + 1024U, // VSTRSH + 1024U, // VSTRSZB + 1024U, // VSTRSZF + 1024U, // VSTRSZH + 1024U, // VSUM + 0U, // VSUMB + 1024U, // VSUMG + 0U, // VSUMGF + 0U, // VSUMGH + 0U, // VSUMH + 1024U, // VSUMQ + 0U, // VSUMQF + 0U, // VSUMQG + 0U, // VTM + 0U, // VTP + 96U, // VUPH + 0U, // VUPHB + 0U, // VUPHF + 0U, // VUPHH + 304U, // VUPKZ + 96U, // VUPKZH + 96U, // VUPKZL + 96U, // VUPL + 0U, // VUPLB + 0U, // VUPLF + 96U, // VUPLH + 0U, // VUPLHB + 0U, // VUPLHF + 0U, // VUPLHH + 0U, // VUPLHW + 96U, // VUPLL + 0U, // VUPLLB + 0U, // VUPLLF + 0U, // VUPLLH + 0U, // VX + 0U, // VZERO + 1120U, // WCDGB + 1120U, // WCDLGB + 1120U, // WCEFB + 1120U, // WCELFB + 1120U, // WCFEB + 1120U, // WCGDB + 1120U, // WCLFEB + 1120U, // WCLGDB + 0U, // WFADB + 0U, // WFASB + 0U, // WFAXB + 1120U, // WFC + 0U, // WFCDB + 0U, // WFCEDB + 0U, // WFCEDBS + 0U, // WFCESB + 0U, // WFCESBS + 0U, // WFCEXB + 0U, // WFCEXBS + 0U, // WFCHDB + 0U, // WFCHDBS + 0U, // WFCHEDB + 0U, // WFCHEDBS + 0U, // WFCHESB + 0U, // WFCHESBS + 0U, // WFCHEXB + 0U, // WFCHEXBS + 0U, // WFCHSB + 0U, // WFCHSBS + 0U, // WFCHXB + 0U, // WFCHXBS + 0U, // WFCSB + 0U, // WFCXB + 0U, // WFDDB + 0U, // WFDSB + 0U, // WFDXB + 1120U, // WFIDB + 1120U, // WFISB + 1120U, // WFIXB + 1120U, // WFK + 0U, // WFKDB + 0U, // WFKEDB + 0U, // WFKEDBS + 0U, // WFKESB + 0U, // WFKESBS + 0U, // WFKEXB + 0U, // WFKEXBS + 0U, // WFKHDB + 0U, // WFKHDBS + 0U, // WFKHEDB + 0U, // WFKHEDBS + 0U, // WFKHESB + 0U, // WFKHESBS + 0U, // WFKHEXB + 0U, // WFKHEXBS + 0U, // WFKHSB + 0U, // WFKHSBS + 0U, // WFKHXB + 0U, // WFKHXBS + 0U, // WFKSB + 0U, // WFKXB + 0U, // WFLCDB + 0U, // WFLCSB + 0U, // WFLCXB + 0U, // WFLLD + 0U, // WFLLS + 0U, // WFLNDB + 0U, // WFLNSB + 0U, // WFLNXB + 0U, // WFLPDB + 0U, // WFLPSB + 0U, // WFLPXB + 1120U, // WFLRD + 1120U, // WFLRX + 1024U, // WFMADB + 1024U, // WFMASB + 1024U, // WFMAXB + 1024U, // WFMAXDB + 1024U, // WFMAXSB + 1024U, // WFMAXXB + 0U, // WFMDB + 1024U, // WFMINDB + 1024U, // WFMINSB + 1024U, // WFMINXB + 0U, // WFMSB + 1024U, // WFMSDB + 1024U, // WFMSSB + 1024U, // WFMSXB + 0U, // WFMXB + 1024U, // WFNMADB + 1024U, // WFNMASB + 1024U, // WFNMAXB + 1024U, // WFNMSDB + 1024U, // WFNMSSB + 1024U, // WFNMSXB + 96U, // WFPSODB + 96U, // WFPSOSB + 96U, // WFPSOXB + 0U, // WFSDB + 0U, // WFSQDB + 0U, // WFSQSB + 0U, // WFSQXB + 0U, // WFSSB + 0U, // WFSXB + 352U, // WFTCIDB + 352U, // WFTCISB + 352U, // WFTCIXB + 0U, // WLDEB + 1120U, // WLEDB + 0U, // X + 0U, // XC + 0U, // XG + 0U, // XGR + 0U, // XGRK + 0U, // XI + 0U, // XIHF + 0U, // XILF + 0U, // XIY + 0U, // XR + 0U, // XRK + 0U, // XSCH + 0U, // XY + 0U, // ZAP + }; + + static const uint8_t OpInfo2[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_VALUE_LIST + 0U, // DBG_INSTR_REF + 0U, // DBG_PHI + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 0U, // ADB_MemFoldPseudo + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ADJDYNALLOC + 0U, // AEB_MemFoldPseudo + 0U, // AEXT128 + 0U, // AFIMux + 0U, // AG_MemFoldPseudo + 0U, // AHIMux + 0U, // AHIMuxK + 0U, // ALG_MemFoldPseudo + 0U, // AL_MemFoldPseudo + 0U, // ATOMIC_CMP_SWAPW + 0U, // ATOMIC_LOADW_AFI + 0U, // ATOMIC_LOADW_AR + 0U, // ATOMIC_LOADW_MAX + 0U, // ATOMIC_LOADW_MIN + 0U, // ATOMIC_LOADW_NILH + 0U, // ATOMIC_LOADW_NILHi + 0U, // ATOMIC_LOADW_NR + 0U, // ATOMIC_LOADW_NRi + 0U, // ATOMIC_LOADW_OILH + 0U, // ATOMIC_LOADW_OR + 0U, // ATOMIC_LOADW_SR + 0U, // ATOMIC_LOADW_UMAX + 0U, // ATOMIC_LOADW_UMIN + 0U, // ATOMIC_LOADW_XILF + 0U, // ATOMIC_LOADW_XR + 0U, // ATOMIC_LOAD_AFI + 0U, // ATOMIC_LOAD_AGFI + 0U, // ATOMIC_LOAD_AGHI + 0U, // ATOMIC_LOAD_AGR + 0U, // ATOMIC_LOAD_AHI + 0U, // ATOMIC_LOAD_AR + 0U, // ATOMIC_LOAD_MAX_32 + 0U, // ATOMIC_LOAD_MAX_64 + 0U, // ATOMIC_LOAD_MIN_32 + 0U, // ATOMIC_LOAD_MIN_64 + 0U, // ATOMIC_LOAD_NGR + 0U, // ATOMIC_LOAD_NGRi + 0U, // ATOMIC_LOAD_NIHF64 + 0U, // ATOMIC_LOAD_NIHF64i + 0U, // ATOMIC_LOAD_NIHH64 + 0U, // ATOMIC_LOAD_NIHH64i + 0U, // ATOMIC_LOAD_NIHL64 + 0U, // ATOMIC_LOAD_NIHL64i + 0U, // ATOMIC_LOAD_NILF + 0U, // ATOMIC_LOAD_NILF64 + 0U, // ATOMIC_LOAD_NILF64i + 0U, // ATOMIC_LOAD_NILFi + 0U, // ATOMIC_LOAD_NILH + 0U, // ATOMIC_LOAD_NILH64 + 0U, // ATOMIC_LOAD_NILH64i + 0U, // ATOMIC_LOAD_NILHi + 0U, // ATOMIC_LOAD_NILL + 0U, // ATOMIC_LOAD_NILL64 + 0U, // ATOMIC_LOAD_NILL64i + 0U, // ATOMIC_LOAD_NILLi + 0U, // ATOMIC_LOAD_NR + 0U, // ATOMIC_LOAD_NRi + 0U, // ATOMIC_LOAD_OGR + 0U, // ATOMIC_LOAD_OIHF64 + 0U, // ATOMIC_LOAD_OIHH64 + 0U, // ATOMIC_LOAD_OIHL64 + 0U, // ATOMIC_LOAD_OILF + 0U, // ATOMIC_LOAD_OILF64 + 0U, // ATOMIC_LOAD_OILH + 0U, // ATOMIC_LOAD_OILH64 + 0U, // ATOMIC_LOAD_OILL + 0U, // ATOMIC_LOAD_OILL64 + 0U, // ATOMIC_LOAD_OR + 0U, // ATOMIC_LOAD_SGR + 0U, // ATOMIC_LOAD_SR + 0U, // ATOMIC_LOAD_UMAX_32 + 0U, // ATOMIC_LOAD_UMAX_64 + 0U, // ATOMIC_LOAD_UMIN_32 + 0U, // ATOMIC_LOAD_UMIN_64 + 0U, // ATOMIC_LOAD_XGR + 0U, // ATOMIC_LOAD_XIHF64 + 0U, // ATOMIC_LOAD_XILF + 0U, // ATOMIC_LOAD_XILF64 + 0U, // ATOMIC_LOAD_XR + 0U, // ATOMIC_SWAPW + 0U, // ATOMIC_SWAP_32 + 0U, // ATOMIC_SWAP_64 + 0U, // A_MemFoldPseudo + 0U, // CFIMux + 0U, // CGIBCall + 0U, // CGIBReturn + 0U, // CGRBCall + 0U, // CGRBReturn + 0U, // CHIMux + 0U, // CIBCall + 0U, // CIBReturn + 0U, // CLCImm + 0U, // CLCReg + 0U, // CLFIMux + 0U, // CLGIBCall + 0U, // CLGIBReturn + 0U, // CLGRBCall + 0U, // CLGRBReturn + 0U, // CLIBCall + 0U, // CLIBReturn + 0U, // CLMux + 0U, // CLRBCall + 0U, // CLRBReturn + 0U, // CLSTLoop + 0U, // CMux + 0U, // CRBCall + 0U, // CRBReturn + 0U, // CallBASR + 0U, // CallBASR_XPLINK64 + 0U, // CallBCR + 0U, // CallBR + 0U, // CallBRASL + 0U, // CallBRASL_XPLINK64 + 0U, // CallBRCL + 0U, // CallJG + 0U, // CondReturn + 0U, // CondStore16 + 0U, // CondStore16Inv + 0U, // CondStore16Mux + 0U, // CondStore16MuxInv + 0U, // CondStore32 + 0U, // CondStore32Inv + 0U, // CondStore32Mux + 0U, // CondStore32MuxInv + 0U, // CondStore64 + 0U, // CondStore64Inv + 0U, // CondStore8 + 0U, // CondStore8Inv + 0U, // CondStore8Mux + 0U, // CondStore8MuxInv + 0U, // CondStoreF32 + 0U, // CondStoreF32Inv + 0U, // CondStoreF64 + 0U, // CondStoreF64Inv + 0U, // CondTrap + 0U, // DDB_MemFoldPseudo + 0U, // DEB_MemFoldPseudo + 0U, // EXRL_Pseudo + 0U, // GOT + 0U, // IIFMux + 0U, // IIHF64 + 0U, // IIHH64 + 0U, // IIHL64 + 0U, // IIHMux + 0U, // IILF64 + 0U, // IILH64 + 0U, // IILL64 + 0U, // IILMux + 0U, // L128 + 0U, // LBMux + 0U, // LEFR + 0U, // LFER + 0U, // LHIMux + 0U, // LHMux + 0U, // LLCMux + 0U, // LLCRMux + 0U, // LLHMux + 0U, // LLHRMux + 0U, // LMux + 0U, // LOCG_MemFoldPseudo + 0U, // LOCHIMux + 0U, // LOCMux + 0U, // LOCMux_MemFoldPseudo + 0U, // LOCRMux + 0U, // LTDBRCompare_VecPseudo + 0U, // LTEBRCompare_VecPseudo + 0U, // LTXBRCompare_VecPseudo + 0U, // LX + 0U, // MADB_MemFoldPseudo + 0U, // MAEB_MemFoldPseudo + 0U, // MDB_MemFoldPseudo + 0U, // MEEB_MemFoldPseudo + 0U, // MSC_MemFoldPseudo + 0U, // MSDB_MemFoldPseudo + 0U, // MSEB_MemFoldPseudo + 0U, // MSGC_MemFoldPseudo + 0U, // MVCImm + 0U, // MVCReg + 0U, // MVSTLoop + 0U, // MemBarrier + 0U, // NCImm + 0U, // NCReg + 0U, // NG_MemFoldPseudo + 0U, // NIFMux + 0U, // NIHF64 + 0U, // NIHH64 + 0U, // NIHL64 + 0U, // NIHMux + 0U, // NILF64 + 0U, // NILH64 + 0U, // NILL64 + 0U, // NILMux + 0U, // N_MemFoldPseudo + 0U, // OCImm + 0U, // OCReg + 0U, // OG_MemFoldPseudo + 0U, // OIFMux + 0U, // OIHF64 + 0U, // OIHH64 + 0U, // OIHL64 + 0U, // OIHMux + 0U, // OILF64 + 0U, // OILH64 + 0U, // OILL64 + 0U, // OILMux + 0U, // O_MemFoldPseudo + 0U, // PAIR128 + 0U, // PROBED_ALLOCA + 0U, // PROBED_STACKALLOC + 0U, // RISBHH + 0U, // RISBHL + 0U, // RISBLH + 0U, // RISBLL + 0U, // RISBMux + 0U, // Return + 0U, // SDB_MemFoldPseudo + 0U, // SEB_MemFoldPseudo + 0U, // SELRMux + 0U, // SG_MemFoldPseudo + 0U, // SLG_MemFoldPseudo + 0U, // SL_MemFoldPseudo + 0U, // SRSTLoop + 0U, // ST128 + 0U, // STCMux + 0U, // STHMux + 0U, // STMux + 0U, // STOCMux + 0U, // STX + 0U, // S_MemFoldPseudo + 0U, // Select32 + 0U, // Select64 + 0U, // SelectF128 + 0U, // SelectF32 + 0U, // SelectF64 + 0U, // SelectVR128 + 0U, // SelectVR32 + 0U, // SelectVR64 + 0U, // Serialize + 0U, // TBEGIN_nofloat + 0U, // TLS_GDCALL + 0U, // TLS_LDCALL + 0U, // TMHH64 + 0U, // TMHL64 + 0U, // TMHMux + 0U, // TMLH64 + 0U, // TMLL64 + 0U, // TMLMux + 0U, // Trap + 0U, // VL32 + 0U, // VL64 + 0U, // VLR32 + 0U, // VLR64 + 0U, // VLVGP32 + 0U, // VST32 + 0U, // VST64 + 0U, // XCImm + 0U, // XCReg + 0U, // XG_MemFoldPseudo + 0U, // XIFMux + 0U, // XIHF64 + 0U, // XILF64 + 0U, // X_MemFoldPseudo + 0U, // ZEXT128 + 0U, // A + 0U, // AD + 0U, // ADB + 0U, // ADBR + 0U, // ADR + 0U, // ADTR + 0U, // ADTRA + 0U, // AE + 0U, // AEB + 0U, // AEBR + 0U, // AER + 0U, // AFI + 0U, // AG + 0U, // AGF + 0U, // AGFI + 0U, // AGFR + 0U, // AGH + 0U, // AGHI + 0U, // AGHIK + 0U, // AGR + 0U, // AGRK + 0U, // AGSI + 0U, // AH + 0U, // AHHHR + 0U, // AHHLR + 0U, // AHI + 0U, // AHIK + 0U, // AHY + 0U, // AIH + 0U, // AL + 0U, // ALC + 0U, // ALCG + 0U, // ALCGR + 0U, // ALCR + 0U, // ALFI + 0U, // ALG + 0U, // ALGF + 0U, // ALGFI + 0U, // ALGFR + 0U, // ALGHSIK + 0U, // ALGR + 0U, // ALGRK + 0U, // ALGSI + 0U, // ALHHHR + 0U, // ALHHLR + 0U, // ALHSIK + 0U, // ALR + 0U, // ALRK + 0U, // ALSI + 0U, // ALSIH + 0U, // ALSIHN + 0U, // ALY + 0U, // AP + 0U, // AR + 0U, // ARK + 0U, // ASI + 0U, // AU + 0U, // AUR + 0U, // AW + 0U, // AWR + 0U, // AXBR + 0U, // AXR + 0U, // AXTR + 0U, // AXTRA + 0U, // AY + 0U, // B + 0U, // BAKR + 0U, // BAL + 0U, // BALR + 0U, // BAS + 0U, // BASR + 0U, // BASSM + 0U, // BAsmE + 0U, // BAsmH + 0U, // BAsmHE + 0U, // BAsmL + 0U, // BAsmLE + 0U, // BAsmLH + 0U, // BAsmM + 0U, // BAsmNE + 0U, // BAsmNH + 0U, // BAsmNHE + 0U, // BAsmNL + 0U, // BAsmNLE + 0U, // BAsmNLH + 0U, // BAsmNM + 0U, // BAsmNO + 0U, // BAsmNP + 0U, // BAsmNZ + 0U, // BAsmO + 0U, // BAsmP + 0U, // BAsmZ + 0U, // BC + 0U, // BCAsm + 0U, // BCR + 0U, // BCRAsm + 0U, // BCT + 0U, // BCTG + 0U, // BCTGR + 0U, // BCTR + 0U, // BI + 0U, // BIAsmE + 0U, // BIAsmH + 0U, // BIAsmHE + 0U, // BIAsmL + 0U, // BIAsmLE + 0U, // BIAsmLH + 0U, // BIAsmM + 0U, // BIAsmNE + 0U, // BIAsmNH + 0U, // BIAsmNHE + 0U, // BIAsmNL + 0U, // BIAsmNLE + 0U, // BIAsmNLH + 0U, // BIAsmNM + 0U, // BIAsmNO + 0U, // BIAsmNP + 0U, // BIAsmNZ + 0U, // BIAsmO + 0U, // BIAsmP + 0U, // BIAsmZ + 0U, // BIC + 0U, // BICAsm + 0U, // BPP + 0U, // BPRP + 0U, // BR + 0U, // BRAS + 0U, // BRASL + 0U, // BRAsmE + 0U, // BRAsmH + 0U, // BRAsmHE + 0U, // BRAsmL + 0U, // BRAsmLE + 0U, // BRAsmLH + 0U, // BRAsmM + 0U, // BRAsmNE + 0U, // BRAsmNH + 0U, // BRAsmNHE + 0U, // BRAsmNL + 0U, // BRAsmNLE + 0U, // BRAsmNLH + 0U, // BRAsmNM + 0U, // BRAsmNO + 0U, // BRAsmNP + 0U, // BRAsmNZ + 0U, // BRAsmO + 0U, // BRAsmP + 0U, // BRAsmZ + 0U, // BRC + 0U, // BRCAsm + 0U, // BRCL + 0U, // BRCLAsm + 0U, // BRCT + 0U, // BRCTG + 0U, // BRCTH + 0U, // BRXH + 0U, // BRXHG + 0U, // BRXLE + 0U, // BRXLG + 0U, // BSA + 0U, // BSG + 0U, // BSM + 0U, // BXH + 0U, // BXHG + 0U, // BXLE + 0U, // BXLEG + 0U, // C + 0U, // CD + 0U, // CDB + 0U, // CDBR + 0U, // CDFBR + 0U, // CDFBRA + 0U, // CDFR + 0U, // CDFTR + 0U, // CDGBR + 0U, // CDGBRA + 0U, // CDGR + 0U, // CDGTR + 0U, // CDGTRA + 0U, // CDLFBR + 0U, // CDLFTR + 0U, // CDLGBR + 0U, // CDLGTR + 0U, // CDPT + 0U, // CDR + 0U, // CDS + 0U, // CDSG + 0U, // CDSTR + 0U, // CDSY + 0U, // CDTR + 0U, // CDUTR + 0U, // CDZT + 0U, // CE + 0U, // CEB + 0U, // CEBR + 0U, // CEDTR + 0U, // CEFBR + 0U, // CEFBRA + 0U, // CEFR + 0U, // CEGBR + 0U, // CEGBRA + 0U, // CEGR + 0U, // CELFBR + 0U, // CELGBR + 0U, // CER + 0U, // CEXTR + 0U, // CFC + 0U, // CFDBR + 0U, // CFDBRA + 0U, // CFDR + 0U, // CFDTR + 0U, // CFEBR + 0U, // CFEBRA + 0U, // CFER + 0U, // CFI + 0U, // CFXBR + 0U, // CFXBRA + 0U, // CFXR + 0U, // CFXTR + 0U, // CG + 0U, // CGDBR + 0U, // CGDBRA + 0U, // CGDR + 0U, // CGDTR + 0U, // CGDTRA + 0U, // CGEBR + 0U, // CGEBRA + 0U, // CGER + 0U, // CGF + 0U, // CGFI + 0U, // CGFR + 0U, // CGFRL + 0U, // CGH + 0U, // CGHI + 0U, // CGHRL + 0U, // CGHSI + 0U, // CGIB + 0U, // CGIBAsm + 0U, // CGIBAsmE + 0U, // CGIBAsmH + 0U, // CGIBAsmHE + 0U, // CGIBAsmL + 0U, // CGIBAsmLE + 0U, // CGIBAsmLH + 0U, // CGIBAsmNE + 0U, // CGIBAsmNH + 0U, // CGIBAsmNHE + 0U, // CGIBAsmNL + 0U, // CGIBAsmNLE + 0U, // CGIBAsmNLH + 0U, // CGIJ + 0U, // CGIJAsm + 0U, // CGIJAsmE + 0U, // CGIJAsmH + 0U, // CGIJAsmHE + 0U, // CGIJAsmL + 0U, // CGIJAsmLE + 0U, // CGIJAsmLH + 0U, // CGIJAsmNE + 0U, // CGIJAsmNH + 0U, // CGIJAsmNHE + 0U, // CGIJAsmNL + 0U, // CGIJAsmNLE + 0U, // CGIJAsmNLH + 0U, // CGIT + 0U, // CGITAsm + 0U, // CGITAsmE + 0U, // CGITAsmH + 0U, // CGITAsmHE + 0U, // CGITAsmL + 0U, // CGITAsmLE + 0U, // CGITAsmLH + 0U, // CGITAsmNE + 0U, // CGITAsmNH + 0U, // CGITAsmNHE + 0U, // CGITAsmNL + 0U, // CGITAsmNLE + 0U, // CGITAsmNLH + 0U, // CGR + 0U, // CGRB + 0U, // CGRBAsm + 0U, // CGRBAsmE + 0U, // CGRBAsmH + 0U, // CGRBAsmHE + 0U, // CGRBAsmL + 0U, // CGRBAsmLE + 0U, // CGRBAsmLH + 0U, // CGRBAsmNE + 0U, // CGRBAsmNH + 0U, // CGRBAsmNHE + 0U, // CGRBAsmNL + 0U, // CGRBAsmNLE + 0U, // CGRBAsmNLH + 0U, // CGRJ + 0U, // CGRJAsm + 0U, // CGRJAsmE + 0U, // CGRJAsmH + 0U, // CGRJAsmHE + 0U, // CGRJAsmL + 0U, // CGRJAsmLE + 0U, // CGRJAsmLH + 0U, // CGRJAsmNE + 0U, // CGRJAsmNH + 0U, // CGRJAsmNHE + 0U, // CGRJAsmNL + 0U, // CGRJAsmNLE + 0U, // CGRJAsmNLH + 0U, // CGRL + 0U, // CGRT + 0U, // CGRTAsm + 0U, // CGRTAsmE + 0U, // CGRTAsmH + 0U, // CGRTAsmHE + 0U, // CGRTAsmL + 0U, // CGRTAsmLE + 0U, // CGRTAsmLH + 0U, // CGRTAsmNE + 0U, // CGRTAsmNH + 0U, // CGRTAsmNHE + 0U, // CGRTAsmNL + 0U, // CGRTAsmNLE + 0U, // CGRTAsmNLH + 0U, // CGXBR + 0U, // CGXBRA + 0U, // CGXR + 0U, // CGXTR + 0U, // CGXTRA + 0U, // CH + 0U, // CHF + 0U, // CHHR + 0U, // CHHSI + 0U, // CHI + 0U, // CHLR + 0U, // CHRL + 0U, // CHSI + 0U, // CHY + 0U, // CIB + 0U, // CIBAsm + 0U, // CIBAsmE + 0U, // CIBAsmH + 0U, // CIBAsmHE + 0U, // CIBAsmL + 0U, // CIBAsmLE + 0U, // CIBAsmLH + 0U, // CIBAsmNE + 0U, // CIBAsmNH + 0U, // CIBAsmNHE + 0U, // CIBAsmNL + 0U, // CIBAsmNLE + 0U, // CIBAsmNLH + 0U, // CIH + 0U, // CIJ + 0U, // CIJAsm + 0U, // CIJAsmE + 0U, // CIJAsmH + 0U, // CIJAsmHE + 0U, // CIJAsmL + 0U, // CIJAsmLE + 0U, // CIJAsmLH + 0U, // CIJAsmNE + 0U, // CIJAsmNH + 0U, // CIJAsmNHE + 0U, // CIJAsmNL + 0U, // CIJAsmNLE + 0U, // CIJAsmNLH + 0U, // CIT + 0U, // CITAsm + 0U, // CITAsmE + 0U, // CITAsmH + 0U, // CITAsmHE + 0U, // CITAsmL + 0U, // CITAsmLE + 0U, // CITAsmLH + 0U, // CITAsmNE + 0U, // CITAsmNH + 0U, // CITAsmNHE + 0U, // CITAsmNL + 0U, // CITAsmNLE + 0U, // CITAsmNLH + 0U, // CKSM + 0U, // CL + 0U, // CLC + 0U, // CLCL + 0U, // CLCLE + 0U, // CLCLU + 0U, // CLFDBR + 0U, // CLFDTR + 0U, // CLFEBR + 0U, // CLFHSI + 0U, // CLFI + 0U, // CLFIT + 0U, // CLFITAsm + 0U, // CLFITAsmE + 0U, // CLFITAsmH + 0U, // CLFITAsmHE + 0U, // CLFITAsmL + 0U, // CLFITAsmLE + 0U, // CLFITAsmLH + 0U, // CLFITAsmNE + 0U, // CLFITAsmNH + 0U, // CLFITAsmNHE + 0U, // CLFITAsmNL + 0U, // CLFITAsmNLE + 0U, // CLFITAsmNLH + 0U, // CLFXBR + 0U, // CLFXTR + 0U, // CLG + 0U, // CLGDBR + 0U, // CLGDTR + 0U, // CLGEBR + 0U, // CLGF + 0U, // CLGFI + 0U, // CLGFR + 0U, // CLGFRL + 0U, // CLGHRL + 0U, // CLGHSI + 0U, // CLGIB + 0U, // CLGIBAsm + 0U, // CLGIBAsmE + 0U, // CLGIBAsmH + 0U, // CLGIBAsmHE + 0U, // CLGIBAsmL + 0U, // CLGIBAsmLE + 0U, // CLGIBAsmLH + 0U, // CLGIBAsmNE + 0U, // CLGIBAsmNH + 0U, // CLGIBAsmNHE + 0U, // CLGIBAsmNL + 0U, // CLGIBAsmNLE + 0U, // CLGIBAsmNLH + 0U, // CLGIJ + 0U, // CLGIJAsm + 0U, // CLGIJAsmE + 0U, // CLGIJAsmH + 0U, // CLGIJAsmHE + 0U, // CLGIJAsmL + 0U, // CLGIJAsmLE + 0U, // CLGIJAsmLH + 0U, // CLGIJAsmNE + 0U, // CLGIJAsmNH + 0U, // CLGIJAsmNHE + 0U, // CLGIJAsmNL + 0U, // CLGIJAsmNLE + 0U, // CLGIJAsmNLH + 0U, // CLGIT + 0U, // CLGITAsm + 0U, // CLGITAsmE + 0U, // CLGITAsmH + 0U, // CLGITAsmHE + 0U, // CLGITAsmL + 0U, // CLGITAsmLE + 0U, // CLGITAsmLH + 0U, // CLGITAsmNE + 0U, // CLGITAsmNH + 0U, // CLGITAsmNHE + 0U, // CLGITAsmNL + 0U, // CLGITAsmNLE + 0U, // CLGITAsmNLH + 0U, // CLGR + 0U, // CLGRB + 0U, // CLGRBAsm + 0U, // CLGRBAsmE + 0U, // CLGRBAsmH + 0U, // CLGRBAsmHE + 0U, // CLGRBAsmL + 0U, // CLGRBAsmLE + 0U, // CLGRBAsmLH + 0U, // CLGRBAsmNE + 0U, // CLGRBAsmNH + 0U, // CLGRBAsmNHE + 0U, // CLGRBAsmNL + 0U, // CLGRBAsmNLE + 0U, // CLGRBAsmNLH + 0U, // CLGRJ + 0U, // CLGRJAsm + 0U, // CLGRJAsmE + 0U, // CLGRJAsmH + 0U, // CLGRJAsmHE + 0U, // CLGRJAsmL + 0U, // CLGRJAsmLE + 0U, // CLGRJAsmLH + 0U, // CLGRJAsmNE + 0U, // CLGRJAsmNH + 0U, // CLGRJAsmNHE + 0U, // CLGRJAsmNL + 0U, // CLGRJAsmNLE + 0U, // CLGRJAsmNLH + 0U, // CLGRL + 0U, // CLGRT + 0U, // CLGRTAsm + 0U, // CLGRTAsmE + 0U, // CLGRTAsmH + 0U, // CLGRTAsmHE + 0U, // CLGRTAsmL + 0U, // CLGRTAsmLE + 0U, // CLGRTAsmLH + 0U, // CLGRTAsmNE + 0U, // CLGRTAsmNH + 0U, // CLGRTAsmNHE + 0U, // CLGRTAsmNL + 0U, // CLGRTAsmNLE + 0U, // CLGRTAsmNLH + 0U, // CLGT + 0U, // CLGTAsm + 0U, // CLGTAsmE + 0U, // CLGTAsmH + 0U, // CLGTAsmHE + 0U, // CLGTAsmL + 0U, // CLGTAsmLE + 0U, // CLGTAsmLH + 0U, // CLGTAsmNE + 0U, // CLGTAsmNH + 0U, // CLGTAsmNHE + 0U, // CLGTAsmNL + 0U, // CLGTAsmNLE + 0U, // CLGTAsmNLH + 0U, // CLGXBR + 0U, // CLGXTR + 0U, // CLHF + 0U, // CLHHR + 0U, // CLHHSI + 0U, // CLHLR + 0U, // CLHRL + 0U, // CLI + 0U, // CLIB + 0U, // CLIBAsm + 0U, // CLIBAsmE + 0U, // CLIBAsmH + 0U, // CLIBAsmHE + 0U, // CLIBAsmL + 0U, // CLIBAsmLE + 0U, // CLIBAsmLH + 0U, // CLIBAsmNE + 0U, // CLIBAsmNH + 0U, // CLIBAsmNHE + 0U, // CLIBAsmNL + 0U, // CLIBAsmNLE + 0U, // CLIBAsmNLH + 0U, // CLIH + 0U, // CLIJ + 0U, // CLIJAsm + 0U, // CLIJAsmE + 0U, // CLIJAsmH + 0U, // CLIJAsmHE + 0U, // CLIJAsmL + 0U, // CLIJAsmLE + 0U, // CLIJAsmLH + 0U, // CLIJAsmNE + 0U, // CLIJAsmNH + 0U, // CLIJAsmNHE + 0U, // CLIJAsmNL + 0U, // CLIJAsmNLE + 0U, // CLIJAsmNLH + 0U, // CLIY + 0U, // CLM + 0U, // CLMH + 0U, // CLMY + 0U, // CLR + 0U, // CLRB + 0U, // CLRBAsm + 0U, // CLRBAsmE + 0U, // CLRBAsmH + 0U, // CLRBAsmHE + 0U, // CLRBAsmL + 0U, // CLRBAsmLE + 0U, // CLRBAsmLH + 0U, // CLRBAsmNE + 0U, // CLRBAsmNH + 0U, // CLRBAsmNHE + 0U, // CLRBAsmNL + 0U, // CLRBAsmNLE + 0U, // CLRBAsmNLH + 0U, // CLRJ + 0U, // CLRJAsm + 0U, // CLRJAsmE + 0U, // CLRJAsmH + 0U, // CLRJAsmHE + 0U, // CLRJAsmL + 0U, // CLRJAsmLE + 0U, // CLRJAsmLH + 0U, // CLRJAsmNE + 0U, // CLRJAsmNH + 0U, // CLRJAsmNHE + 0U, // CLRJAsmNL + 0U, // CLRJAsmNLE + 0U, // CLRJAsmNLH + 0U, // CLRL + 0U, // CLRT + 0U, // CLRTAsm + 0U, // CLRTAsmE + 0U, // CLRTAsmH + 0U, // CLRTAsmHE + 0U, // CLRTAsmL + 0U, // CLRTAsmLE + 0U, // CLRTAsmLH + 0U, // CLRTAsmNE + 0U, // CLRTAsmNH + 0U, // CLRTAsmNHE + 0U, // CLRTAsmNL + 0U, // CLRTAsmNLE + 0U, // CLRTAsmNLH + 0U, // CLST + 0U, // CLT + 0U, // CLTAsm + 0U, // CLTAsmE + 0U, // CLTAsmH + 0U, // CLTAsmHE + 0U, // CLTAsmL + 0U, // CLTAsmLE + 0U, // CLTAsmLH + 0U, // CLTAsmNE + 0U, // CLTAsmNH + 0U, // CLTAsmNHE + 0U, // CLTAsmNL + 0U, // CLTAsmNLE + 0U, // CLTAsmNLH + 0U, // CLY + 0U, // CMPSC + 0U, // CP + 0U, // CPDT + 0U, // CPSDRdd + 0U, // CPSDRds + 0U, // CPSDRsd + 0U, // CPSDRss + 0U, // CPXT + 0U, // CPYA + 0U, // CR + 0U, // CRB + 0U, // CRBAsm + 0U, // CRBAsmE + 0U, // CRBAsmH + 0U, // CRBAsmHE + 0U, // CRBAsmL + 0U, // CRBAsmLE + 0U, // CRBAsmLH + 0U, // CRBAsmNE + 0U, // CRBAsmNH + 0U, // CRBAsmNHE + 0U, // CRBAsmNL + 0U, // CRBAsmNLE + 0U, // CRBAsmNLH + 0U, // CRDTE + 0U, // CRDTEOpt + 0U, // CRJ + 0U, // CRJAsm + 0U, // CRJAsmE + 0U, // CRJAsmH + 0U, // CRJAsmHE + 0U, // CRJAsmL + 0U, // CRJAsmLE + 0U, // CRJAsmLH + 0U, // CRJAsmNE + 0U, // CRJAsmNH + 0U, // CRJAsmNHE + 0U, // CRJAsmNL + 0U, // CRJAsmNLE + 0U, // CRJAsmNLH + 0U, // CRL + 0U, // CRT + 0U, // CRTAsm + 0U, // CRTAsmE + 0U, // CRTAsmH + 0U, // CRTAsmHE + 0U, // CRTAsmL + 0U, // CRTAsmLE + 0U, // CRTAsmLH + 0U, // CRTAsmNE + 0U, // CRTAsmNH + 0U, // CRTAsmNHE + 0U, // CRTAsmNL + 0U, // CRTAsmNLE + 0U, // CRTAsmNLH + 0U, // CS + 0U, // CSCH + 0U, // CSDTR + 0U, // CSG + 0U, // CSP + 0U, // CSPG + 0U, // CSST + 0U, // CSXTR + 0U, // CSY + 0U, // CU12 + 0U, // CU12Opt + 0U, // CU14 + 0U, // CU14Opt + 0U, // CU21 + 0U, // CU21Opt + 0U, // CU24 + 0U, // CU24Opt + 0U, // CU41 + 0U, // CU42 + 0U, // CUDTR + 0U, // CUSE + 0U, // CUTFU + 0U, // CUTFUOpt + 0U, // CUUTF + 0U, // CUUTFOpt + 0U, // CUXTR + 0U, // CVB + 0U, // CVBG + 0U, // CVBY + 0U, // CVD + 0U, // CVDG + 0U, // CVDY + 0U, // CXBR + 0U, // CXFBR + 0U, // CXFBRA + 0U, // CXFR + 0U, // CXFTR + 0U, // CXGBR + 0U, // CXGBRA + 0U, // CXGR + 0U, // CXGTR + 0U, // CXGTRA + 0U, // CXLFBR + 0U, // CXLFTR + 0U, // CXLGBR + 0U, // CXLGTR + 0U, // CXPT + 0U, // CXR + 0U, // CXSTR + 0U, // CXTR + 0U, // CXUTR + 0U, // CXZT + 0U, // CY + 0U, // CZDT + 0U, // CZXT + 0U, // D + 0U, // DD + 0U, // DDB + 0U, // DDBR + 0U, // DDR + 0U, // DDTR + 0U, // DDTRA + 0U, // DE + 0U, // DEB + 0U, // DEBR + 0U, // DER + 0U, // DFLTCC + 0U, // DIAG + 0U, // DIDBR + 0U, // DIEBR + 0U, // DL + 0U, // DLG + 0U, // DLGR + 0U, // DLR + 0U, // DP + 0U, // DR + 0U, // DSG + 0U, // DSGF + 0U, // DSGFR + 0U, // DSGR + 0U, // DXBR + 0U, // DXR + 0U, // DXTR + 0U, // DXTRA + 0U, // EAR + 0U, // ECAG + 0U, // ECCTR + 0U, // ECPGA + 0U, // ECTG + 0U, // ED + 0U, // EDMK + 0U, // EEDTR + 0U, // EEXTR + 0U, // EFPC + 0U, // EPAIR + 0U, // EPAR + 0U, // EPCTR + 0U, // EPSW + 0U, // EREG + 0U, // EREGG + 0U, // ESAIR + 0U, // ESAR + 0U, // ESDTR + 0U, // ESEA + 0U, // ESTA + 0U, // ESXTR + 0U, // ETND + 0U, // EX + 0U, // EXRL + 0U, // FIDBR + 0U, // FIDBRA + 0U, // FIDR + 0U, // FIDTR + 0U, // FIEBR + 0U, // FIEBRA + 0U, // FIER + 0U, // FIXBR + 0U, // FIXBRA + 0U, // FIXR + 0U, // FIXTR + 0U, // FLOGR + 0U, // HDR + 0U, // HER + 0U, // HSCH + 0U, // IAC + 0U, // IC + 0U, // IC32 + 0U, // IC32Y + 0U, // ICM + 0U, // ICMH + 0U, // ICMY + 0U, // ICY + 0U, // IDTE + 0U, // IDTEOpt + 0U, // IEDTR + 0U, // IEXTR + 0U, // IIHF + 0U, // IIHH + 0U, // IIHL + 0U, // IILF + 0U, // IILH + 0U, // IILL + 0U, // IPK + 0U, // IPM + 0U, // IPTE + 0U, // IPTEOpt + 0U, // IPTEOptOpt + 0U, // IRBM + 0U, // ISKE + 0U, // IVSK + 0U, // InsnE + 0U, // InsnRI + 0U, // InsnRIE + 0U, // InsnRIL + 0U, // InsnRILU + 0U, // InsnRIS + 0U, // InsnRR + 0U, // InsnRRE + 1U, // InsnRRF + 5U, // InsnRRS + 0U, // InsnRS + 0U, // InsnRSE + 0U, // InsnRSI + 0U, // InsnRSY + 0U, // InsnRX + 0U, // InsnRXE + 0U, // InsnRXF + 0U, // InsnRXY + 0U, // InsnS + 0U, // InsnSI + 0U, // InsnSIL + 0U, // InsnSIY + 0U, // InsnSS + 0U, // InsnSSE + 0U, // InsnSSF + 0U, // InsnVRI + 9U, // InsnVRR + 0U, // InsnVRS + 0U, // InsnVRV + 0U, // InsnVRX + 0U, // InsnVSI + 0U, // J + 0U, // JAsmE + 0U, // JAsmH + 0U, // JAsmHE + 0U, // JAsmL + 0U, // JAsmLE + 0U, // JAsmLH + 0U, // JAsmM + 0U, // JAsmNE + 0U, // JAsmNH + 0U, // JAsmNHE + 0U, // JAsmNL + 0U, // JAsmNLE + 0U, // JAsmNLH + 0U, // JAsmNM + 0U, // JAsmNO + 0U, // JAsmNP + 0U, // JAsmNZ + 0U, // JAsmO + 0U, // JAsmP + 0U, // JAsmZ + 0U, // JG + 0U, // JGAsmE + 0U, // JGAsmH + 0U, // JGAsmHE + 0U, // JGAsmL + 0U, // JGAsmLE + 0U, // JGAsmLH + 0U, // JGAsmM + 0U, // JGAsmNE + 0U, // JGAsmNH + 0U, // JGAsmNHE + 0U, // JGAsmNL + 0U, // JGAsmNLE + 0U, // JGAsmNLH + 0U, // JGAsmNM + 0U, // JGAsmNO + 0U, // JGAsmNP + 0U, // JGAsmNZ + 0U, // JGAsmO + 0U, // JGAsmP + 0U, // JGAsmZ + 0U, // KDB + 0U, // KDBR + 0U, // KDSA + 0U, // KDTR + 0U, // KEB + 0U, // KEBR + 0U, // KIMD + 0U, // KLMD + 0U, // KM + 0U, // KMA + 0U, // KMAC + 0U, // KMC + 0U, // KMCTR + 0U, // KMF + 0U, // KMO + 0U, // KXBR + 0U, // KXTR + 0U, // L + 0U, // LA + 0U, // LAA + 0U, // LAAG + 0U, // LAAL + 0U, // LAALG + 0U, // LAE + 0U, // LAEY + 0U, // LAM + 0U, // LAMY + 0U, // LAN + 0U, // LANG + 0U, // LAO + 0U, // LAOG + 0U, // LARL + 0U, // LASP + 0U, // LAT + 0U, // LAX + 0U, // LAXG + 0U, // LAY + 0U, // LB + 0U, // LBEAR + 0U, // LBH + 0U, // LBR + 0U, // LCBB + 0U, // LCCTL + 0U, // LCDBR + 0U, // LCDFR + 0U, // LCDFR_32 + 0U, // LCDR + 0U, // LCEBR + 0U, // LCER + 0U, // LCGFR + 0U, // LCGR + 0U, // LCR + 0U, // LCTL + 0U, // LCTLG + 0U, // LCXBR + 0U, // LCXR + 0U, // LD + 0U, // LDE + 0U, // LDE32 + 0U, // LDEB + 0U, // LDEBR + 0U, // LDER + 0U, // LDETR + 0U, // LDGR + 0U, // LDR + 0U, // LDR32 + 0U, // LDXBR + 0U, // LDXBRA + 0U, // LDXR + 0U, // LDXTR + 0U, // LDY + 0U, // LE + 0U, // LEDBR + 0U, // LEDBRA + 0U, // LEDR + 0U, // LEDTR + 0U, // LER + 0U, // LEXBR + 0U, // LEXBRA + 0U, // LEXR + 0U, // LEY + 0U, // LFAS + 0U, // LFH + 0U, // LFHAT + 0U, // LFPC + 0U, // LG + 0U, // LGAT + 0U, // LGB + 0U, // LGBR + 0U, // LGDR + 0U, // LGF + 0U, // LGFI + 0U, // LGFR + 0U, // LGFRL + 0U, // LGG + 0U, // LGH + 0U, // LGHI + 0U, // LGHR + 0U, // LGHRL + 0U, // LGR + 0U, // LGRL + 0U, // LGSC + 0U, // LH + 0U, // LHH + 0U, // LHI + 0U, // LHR + 0U, // LHRL + 0U, // LHY + 0U, // LLC + 0U, // LLCH + 0U, // LLCR + 0U, // LLGC + 0U, // LLGCR + 0U, // LLGF + 0U, // LLGFAT + 0U, // LLGFR + 0U, // LLGFRL + 0U, // LLGFSG + 0U, // LLGH + 0U, // LLGHR + 0U, // LLGHRL + 0U, // LLGT + 0U, // LLGTAT + 0U, // LLGTR + 0U, // LLH + 0U, // LLHH + 0U, // LLHR + 0U, // LLHRL + 0U, // LLIHF + 0U, // LLIHH + 0U, // LLIHL + 0U, // LLILF + 0U, // LLILH + 0U, // LLILL + 0U, // LLZRGF + 0U, // LM + 1U, // LMD + 0U, // LMG + 0U, // LMH + 0U, // LMY + 0U, // LNDBR + 0U, // LNDFR + 0U, // LNDFR_32 + 0U, // LNDR + 0U, // LNEBR + 0U, // LNER + 0U, // LNGFR + 0U, // LNGR + 0U, // LNR + 0U, // LNXBR + 0U, // LNXR + 0U, // LOC + 0U, // LOCAsm + 0U, // LOCAsmE + 0U, // LOCAsmH + 0U, // LOCAsmHE + 0U, // LOCAsmL + 0U, // LOCAsmLE + 0U, // LOCAsmLH + 0U, // LOCAsmM + 0U, // LOCAsmNE + 0U, // LOCAsmNH + 0U, // LOCAsmNHE + 0U, // LOCAsmNL + 0U, // LOCAsmNLE + 0U, // LOCAsmNLH + 0U, // LOCAsmNM + 0U, // LOCAsmNO + 0U, // LOCAsmNP + 0U, // LOCAsmNZ + 0U, // LOCAsmO + 0U, // LOCAsmP + 0U, // LOCAsmZ + 0U, // LOCFH + 0U, // LOCFHAsm + 0U, // LOCFHAsmE + 0U, // LOCFHAsmH + 0U, // LOCFHAsmHE + 0U, // LOCFHAsmL + 0U, // LOCFHAsmLE + 0U, // LOCFHAsmLH + 0U, // LOCFHAsmM + 0U, // LOCFHAsmNE + 0U, // LOCFHAsmNH + 0U, // LOCFHAsmNHE + 0U, // LOCFHAsmNL + 0U, // LOCFHAsmNLE + 0U, // LOCFHAsmNLH + 0U, // LOCFHAsmNM + 0U, // LOCFHAsmNO + 0U, // LOCFHAsmNP + 0U, // LOCFHAsmNZ + 0U, // LOCFHAsmO + 0U, // LOCFHAsmP + 0U, // LOCFHAsmZ + 0U, // LOCFHR + 0U, // LOCFHRAsm + 0U, // LOCFHRAsmE + 0U, // LOCFHRAsmH + 0U, // LOCFHRAsmHE + 0U, // LOCFHRAsmL + 0U, // LOCFHRAsmLE + 0U, // LOCFHRAsmLH + 0U, // LOCFHRAsmM + 0U, // LOCFHRAsmNE + 0U, // LOCFHRAsmNH + 0U, // LOCFHRAsmNHE + 0U, // LOCFHRAsmNL + 0U, // LOCFHRAsmNLE + 0U, // LOCFHRAsmNLH + 0U, // LOCFHRAsmNM + 0U, // LOCFHRAsmNO + 0U, // LOCFHRAsmNP + 0U, // LOCFHRAsmNZ + 0U, // LOCFHRAsmO + 0U, // LOCFHRAsmP + 0U, // LOCFHRAsmZ + 0U, // LOCG + 0U, // LOCGAsm + 0U, // LOCGAsmE + 0U, // LOCGAsmH + 0U, // LOCGAsmHE + 0U, // LOCGAsmL + 0U, // LOCGAsmLE + 0U, // LOCGAsmLH + 0U, // LOCGAsmM + 0U, // LOCGAsmNE + 0U, // LOCGAsmNH + 0U, // LOCGAsmNHE + 0U, // LOCGAsmNL + 0U, // LOCGAsmNLE + 0U, // LOCGAsmNLH + 0U, // LOCGAsmNM + 0U, // LOCGAsmNO + 0U, // LOCGAsmNP + 0U, // LOCGAsmNZ + 0U, // LOCGAsmO + 0U, // LOCGAsmP + 0U, // LOCGAsmZ + 0U, // LOCGHI + 0U, // LOCGHIAsm + 0U, // LOCGHIAsmE + 0U, // LOCGHIAsmH + 0U, // LOCGHIAsmHE + 0U, // LOCGHIAsmL + 0U, // LOCGHIAsmLE + 0U, // LOCGHIAsmLH + 0U, // LOCGHIAsmM + 0U, // LOCGHIAsmNE + 0U, // LOCGHIAsmNH + 0U, // LOCGHIAsmNHE + 0U, // LOCGHIAsmNL + 0U, // LOCGHIAsmNLE + 0U, // LOCGHIAsmNLH + 0U, // LOCGHIAsmNM + 0U, // LOCGHIAsmNO + 0U, // LOCGHIAsmNP + 0U, // LOCGHIAsmNZ + 0U, // LOCGHIAsmO + 0U, // LOCGHIAsmP + 0U, // LOCGHIAsmZ + 0U, // LOCGR + 0U, // LOCGRAsm + 0U, // LOCGRAsmE + 0U, // LOCGRAsmH + 0U, // LOCGRAsmHE + 0U, // LOCGRAsmL + 0U, // LOCGRAsmLE + 0U, // LOCGRAsmLH + 0U, // LOCGRAsmM + 0U, // LOCGRAsmNE + 0U, // LOCGRAsmNH + 0U, // LOCGRAsmNHE + 0U, // LOCGRAsmNL + 0U, // LOCGRAsmNLE + 0U, // LOCGRAsmNLH + 0U, // LOCGRAsmNM + 0U, // LOCGRAsmNO + 0U, // LOCGRAsmNP + 0U, // LOCGRAsmNZ + 0U, // LOCGRAsmO + 0U, // LOCGRAsmP + 0U, // LOCGRAsmZ + 0U, // LOCHHI + 0U, // LOCHHIAsm + 0U, // LOCHHIAsmE + 0U, // LOCHHIAsmH + 0U, // LOCHHIAsmHE + 0U, // LOCHHIAsmL + 0U, // LOCHHIAsmLE + 0U, // LOCHHIAsmLH + 0U, // LOCHHIAsmM + 0U, // LOCHHIAsmNE + 0U, // LOCHHIAsmNH + 0U, // LOCHHIAsmNHE + 0U, // LOCHHIAsmNL + 0U, // LOCHHIAsmNLE + 0U, // LOCHHIAsmNLH + 0U, // LOCHHIAsmNM + 0U, // LOCHHIAsmNO + 0U, // LOCHHIAsmNP + 0U, // LOCHHIAsmNZ + 0U, // LOCHHIAsmO + 0U, // LOCHHIAsmP + 0U, // LOCHHIAsmZ + 0U, // LOCHI + 0U, // LOCHIAsm + 0U, // LOCHIAsmE + 0U, // LOCHIAsmH + 0U, // LOCHIAsmHE + 0U, // LOCHIAsmL + 0U, // LOCHIAsmLE + 0U, // LOCHIAsmLH + 0U, // LOCHIAsmM + 0U, // LOCHIAsmNE + 0U, // LOCHIAsmNH + 0U, // LOCHIAsmNHE + 0U, // LOCHIAsmNL + 0U, // LOCHIAsmNLE + 0U, // LOCHIAsmNLH + 0U, // LOCHIAsmNM + 0U, // LOCHIAsmNO + 0U, // LOCHIAsmNP + 0U, // LOCHIAsmNZ + 0U, // LOCHIAsmO + 0U, // LOCHIAsmP + 0U, // LOCHIAsmZ + 0U, // LOCR + 0U, // LOCRAsm + 0U, // LOCRAsmE + 0U, // LOCRAsmH + 0U, // LOCRAsmHE + 0U, // LOCRAsmL + 0U, // LOCRAsmLE + 0U, // LOCRAsmLH + 0U, // LOCRAsmM + 0U, // LOCRAsmNE + 0U, // LOCRAsmNH + 0U, // LOCRAsmNHE + 0U, // LOCRAsmNL + 0U, // LOCRAsmNLE + 0U, // LOCRAsmNLH + 0U, // LOCRAsmNM + 0U, // LOCRAsmNO + 0U, // LOCRAsmNP + 0U, // LOCRAsmNZ + 0U, // LOCRAsmO + 0U, // LOCRAsmP + 0U, // LOCRAsmZ + 0U, // LPCTL + 0U, // LPD + 0U, // LPDBR + 0U, // LPDFR + 0U, // LPDFR_32 + 0U, // LPDG + 0U, // LPDR + 0U, // LPEBR + 0U, // LPER + 0U, // LPGFR + 0U, // LPGR + 0U, // LPP + 0U, // LPQ + 0U, // LPR + 0U, // LPSW + 0U, // LPSWE + 0U, // LPSWEY + 0U, // LPTEA + 0U, // LPXBR + 0U, // LPXR + 0U, // LR + 0U, // LRA + 0U, // LRAG + 0U, // LRAY + 0U, // LRDR + 0U, // LRER + 0U, // LRL + 0U, // LRV + 0U, // LRVG + 0U, // LRVGR + 0U, // LRVH + 0U, // LRVR + 0U, // LSCTL + 0U, // LT + 0U, // LTDBR + 0U, // LTDBRCompare + 0U, // LTDR + 0U, // LTDTR + 0U, // LTEBR + 0U, // LTEBRCompare + 0U, // LTER + 0U, // LTG + 0U, // LTGF + 0U, // LTGFR + 0U, // LTGR + 0U, // LTR + 0U, // LTXBR + 0U, // LTXBRCompare + 0U, // LTXR + 0U, // LTXTR + 0U, // LURA + 0U, // LURAG + 0U, // LXD + 0U, // LXDB + 0U, // LXDBR + 0U, // LXDR + 0U, // LXDTR + 0U, // LXE + 0U, // LXEB + 0U, // LXEBR + 0U, // LXER + 0U, // LXR + 0U, // LY + 0U, // LZDR + 0U, // LZER + 0U, // LZRF + 0U, // LZRG + 0U, // LZXR + 0U, // M + 0U, // MAD + 0U, // MADB + 0U, // MADBR + 0U, // MADR + 0U, // MAE + 0U, // MAEB + 0U, // MAEBR + 0U, // MAER + 0U, // MAY + 0U, // MAYH + 0U, // MAYHR + 0U, // MAYL + 0U, // MAYLR + 0U, // MAYR + 0U, // MC + 0U, // MD + 0U, // MDB + 0U, // MDBR + 0U, // MDE + 0U, // MDEB + 0U, // MDEBR + 0U, // MDER + 0U, // MDR + 0U, // MDTR + 0U, // MDTRA + 0U, // ME + 0U, // MEE + 0U, // MEEB + 0U, // MEEBR + 0U, // MEER + 0U, // MER + 0U, // MFY + 0U, // MG + 0U, // MGH + 0U, // MGHI + 0U, // MGRK + 0U, // MH + 0U, // MHI + 0U, // MHY + 0U, // ML + 0U, // MLG + 0U, // MLGR + 0U, // MLR + 0U, // MP + 0U, // MR + 0U, // MS + 0U, // MSC + 0U, // MSCH + 0U, // MSD + 0U, // MSDB + 0U, // MSDBR + 0U, // MSDR + 0U, // MSE + 0U, // MSEB + 0U, // MSEBR + 0U, // MSER + 0U, // MSFI + 0U, // MSG + 0U, // MSGC + 0U, // MSGF + 0U, // MSGFI + 0U, // MSGFR + 0U, // MSGR + 0U, // MSGRKC + 0U, // MSR + 0U, // MSRKC + 0U, // MSTA + 0U, // MSY + 0U, // MVC + 0U, // MVCDK + 0U, // MVCIN + 0U, // MVCK + 0U, // MVCL + 0U, // MVCLE + 0U, // MVCLU + 0U, // MVCOS + 0U, // MVCP + 0U, // MVCRL + 0U, // MVCS + 0U, // MVCSK + 0U, // MVGHI + 0U, // MVHHI + 0U, // MVHI + 0U, // MVI + 0U, // MVIY + 0U, // MVN + 0U, // MVO + 0U, // MVPG + 0U, // MVST + 0U, // MVZ + 0U, // MXBR + 0U, // MXD + 0U, // MXDB + 0U, // MXDBR + 0U, // MXDR + 0U, // MXR + 0U, // MXTR + 0U, // MXTRA + 0U, // MY + 0U, // MYH + 0U, // MYHR + 0U, // MYL + 0U, // MYLR + 0U, // MYR + 0U, // N + 0U, // NC + 0U, // NCGRK + 0U, // NCRK + 0U, // NG + 0U, // NGR + 0U, // NGRK + 0U, // NI + 0U, // NIAI + 0U, // NIHF + 0U, // NIHH + 0U, // NIHL + 0U, // NILF + 0U, // NILH + 0U, // NILL + 0U, // NIY + 0U, // NNGRK + 0U, // NNPA + 0U, // NNRK + 0U, // NOGRK + 0U, // NOP_bare + 0U, // NORK + 0U, // NR + 0U, // NRK + 0U, // NTSTG + 0U, // NXGRK + 0U, // NXRK + 0U, // NY + 0U, // O + 0U, // OC + 0U, // OCGRK + 0U, // OCRK + 0U, // OG + 0U, // OGR + 0U, // OGRK + 0U, // OI + 0U, // OIHF + 0U, // OIHH + 0U, // OIHL + 0U, // OILF + 0U, // OILH + 0U, // OILL + 0U, // OIY + 0U, // OR + 0U, // ORK + 0U, // OY + 0U, // PACK + 0U, // PALB + 0U, // PC + 0U, // PCC + 0U, // PCKMO + 0U, // PFD + 0U, // PFDRL + 0U, // PFMF + 0U, // PFPO + 0U, // PGIN + 0U, // PGOUT + 0U, // PKA + 0U, // PKU + 1U, // PLO + 0U, // POPCNT + 0U, // POPCNTOpt + 0U, // PPA + 0U, // PPNO + 0U, // PR + 0U, // PRNO + 0U, // PT + 0U, // PTF + 0U, // PTFF + 0U, // PTI + 0U, // PTLB + 0U, // QADTR + 0U, // QAXTR + 0U, // QCTRI + 0U, // QPACI + 0U, // QSI + 0U, // RCHP + 0U, // RDP + 0U, // RDPOpt + 13U, // RISBG + 13U, // RISBG32 + 13U, // RISBGN + 13U, // RISBHG + 13U, // RISBLG + 0U, // RLL + 0U, // RLLG + 13U, // RNSBG + 13U, // ROSBG + 0U, // RP + 0U, // RRBE + 0U, // RRBM + 0U, // RRDTR + 0U, // RRXTR + 0U, // RSCH + 13U, // RXSBG + 0U, // S + 0U, // SAC + 0U, // SACF + 0U, // SAL + 0U, // SAM24 + 0U, // SAM31 + 0U, // SAM64 + 0U, // SAR + 0U, // SCCTR + 0U, // SCHM + 0U, // SCK + 0U, // SCKC + 0U, // SCKPF + 0U, // SD + 0U, // SDB + 0U, // SDBR + 0U, // SDR + 0U, // SDTR + 0U, // SDTRA + 0U, // SE + 0U, // SEB + 0U, // SEBR + 0U, // SELFHR + 0U, // SELFHRAsm + 0U, // SELFHRAsmE + 0U, // SELFHRAsmH + 0U, // SELFHRAsmHE + 0U, // SELFHRAsmL + 0U, // SELFHRAsmLE + 0U, // SELFHRAsmLH + 0U, // SELFHRAsmM + 0U, // SELFHRAsmNE + 0U, // SELFHRAsmNH + 0U, // SELFHRAsmNHE + 0U, // SELFHRAsmNL + 0U, // SELFHRAsmNLE + 0U, // SELFHRAsmNLH + 0U, // SELFHRAsmNM + 0U, // SELFHRAsmNO + 0U, // SELFHRAsmNP + 0U, // SELFHRAsmNZ + 0U, // SELFHRAsmO + 0U, // SELFHRAsmP + 0U, // SELFHRAsmZ + 0U, // SELGR + 0U, // SELGRAsm + 0U, // SELGRAsmE + 0U, // SELGRAsmH + 0U, // SELGRAsmHE + 0U, // SELGRAsmL + 0U, // SELGRAsmLE + 0U, // SELGRAsmLH + 0U, // SELGRAsmM + 0U, // SELGRAsmNE + 0U, // SELGRAsmNH + 0U, // SELGRAsmNHE + 0U, // SELGRAsmNL + 0U, // SELGRAsmNLE + 0U, // SELGRAsmNLH + 0U, // SELGRAsmNM + 0U, // SELGRAsmNO + 0U, // SELGRAsmNP + 0U, // SELGRAsmNZ + 0U, // SELGRAsmO + 0U, // SELGRAsmP + 0U, // SELGRAsmZ + 0U, // SELR + 0U, // SELRAsm + 0U, // SELRAsmE + 0U, // SELRAsmH + 0U, // SELRAsmHE + 0U, // SELRAsmL + 0U, // SELRAsmLE + 0U, // SELRAsmLH + 0U, // SELRAsmM + 0U, // SELRAsmNE + 0U, // SELRAsmNH + 0U, // SELRAsmNHE + 0U, // SELRAsmNL + 0U, // SELRAsmNLE + 0U, // SELRAsmNLH + 0U, // SELRAsmNM + 0U, // SELRAsmNO + 0U, // SELRAsmNP + 0U, // SELRAsmNZ + 0U, // SELRAsmO + 0U, // SELRAsmP + 0U, // SELRAsmZ + 0U, // SER + 0U, // SFASR + 0U, // SFPC + 0U, // SG + 0U, // SGF + 0U, // SGFR + 0U, // SGH + 0U, // SGR + 0U, // SGRK + 0U, // SH + 0U, // SHHHR + 0U, // SHHLR + 0U, // SHY + 0U, // SIE + 0U, // SIGA + 0U, // SIGP + 0U, // SL + 0U, // SLA + 0U, // SLAG + 0U, // SLAK + 0U, // SLB + 0U, // SLBG + 0U, // SLBGR + 0U, // SLBR + 0U, // SLDA + 0U, // SLDL + 0U, // SLDT + 0U, // SLFI + 0U, // SLG + 0U, // SLGF + 0U, // SLGFI + 0U, // SLGFR + 0U, // SLGR + 0U, // SLGRK + 0U, // SLHHHR + 0U, // SLHHLR + 0U, // SLL + 0U, // SLLG + 0U, // SLLK + 0U, // SLR + 0U, // SLRK + 0U, // SLXT + 0U, // SLY + 0U, // SORTL + 0U, // SP + 0U, // SPCTR + 0U, // SPKA + 0U, // SPM + 0U, // SPT + 0U, // SPX + 0U, // SQD + 0U, // SQDB + 0U, // SQDBR + 0U, // SQDR + 0U, // SQE + 0U, // SQEB + 0U, // SQEBR + 0U, // SQER + 0U, // SQXBR + 0U, // SQXR + 0U, // SR + 0U, // SRA + 0U, // SRAG + 0U, // SRAK + 0U, // SRDA + 0U, // SRDL + 0U, // SRDT + 0U, // SRK + 0U, // SRL + 0U, // SRLG + 0U, // SRLK + 0U, // SRNM + 0U, // SRNMB + 0U, // SRNMT + 0U, // SRP + 0U, // SRST + 0U, // SRSTU + 0U, // SRXT + 0U, // SSAIR + 0U, // SSAR + 0U, // SSCH + 0U, // SSKE + 0U, // SSKEOpt + 0U, // SSM + 0U, // ST + 0U, // STAM + 0U, // STAMY + 0U, // STAP + 0U, // STBEAR + 0U, // STC + 0U, // STCH + 0U, // STCK + 0U, // STCKC + 0U, // STCKE + 0U, // STCKF + 0U, // STCM + 0U, // STCMH + 0U, // STCMY + 0U, // STCPS + 0U, // STCRW + 0U, // STCTG + 0U, // STCTL + 0U, // STCY + 0U, // STD + 0U, // STDY + 0U, // STE + 0U, // STEY + 0U, // STFH + 0U, // STFL + 0U, // STFLE + 0U, // STFPC + 0U, // STG + 0U, // STGRL + 0U, // STGSC + 0U, // STH + 0U, // STHH + 0U, // STHRL + 0U, // STHY + 0U, // STIDP + 0U, // STM + 0U, // STMG + 0U, // STMH + 0U, // STMY + 0U, // STNSM + 0U, // STOC + 0U, // STOCAsm + 0U, // STOCAsmE + 0U, // STOCAsmH + 0U, // STOCAsmHE + 0U, // STOCAsmL + 0U, // STOCAsmLE + 0U, // STOCAsmLH + 0U, // STOCAsmM + 0U, // STOCAsmNE + 0U, // STOCAsmNH + 0U, // STOCAsmNHE + 0U, // STOCAsmNL + 0U, // STOCAsmNLE + 0U, // STOCAsmNLH + 0U, // STOCAsmNM + 0U, // STOCAsmNO + 0U, // STOCAsmNP + 0U, // STOCAsmNZ + 0U, // STOCAsmO + 0U, // STOCAsmP + 0U, // STOCAsmZ + 0U, // STOCFH + 0U, // STOCFHAsm + 0U, // STOCFHAsmE + 0U, // STOCFHAsmH + 0U, // STOCFHAsmHE + 0U, // STOCFHAsmL + 0U, // STOCFHAsmLE + 0U, // STOCFHAsmLH + 0U, // STOCFHAsmM + 0U, // STOCFHAsmNE + 0U, // STOCFHAsmNH + 0U, // STOCFHAsmNHE + 0U, // STOCFHAsmNL + 0U, // STOCFHAsmNLE + 0U, // STOCFHAsmNLH + 0U, // STOCFHAsmNM + 0U, // STOCFHAsmNO + 0U, // STOCFHAsmNP + 0U, // STOCFHAsmNZ + 0U, // STOCFHAsmO + 0U, // STOCFHAsmP + 0U, // STOCFHAsmZ + 0U, // STOCG + 0U, // STOCGAsm + 0U, // STOCGAsmE + 0U, // STOCGAsmH + 0U, // STOCGAsmHE + 0U, // STOCGAsmL + 0U, // STOCGAsmLE + 0U, // STOCGAsmLH + 0U, // STOCGAsmM + 0U, // STOCGAsmNE + 0U, // STOCGAsmNH + 0U, // STOCGAsmNHE + 0U, // STOCGAsmNL + 0U, // STOCGAsmNLE + 0U, // STOCGAsmNLH + 0U, // STOCGAsmNM + 0U, // STOCGAsmNO + 0U, // STOCGAsmNP + 0U, // STOCGAsmNZ + 0U, // STOCGAsmO + 0U, // STOCGAsmP + 0U, // STOCGAsmZ + 0U, // STOSM + 0U, // STPQ + 0U, // STPT + 0U, // STPX + 0U, // STRAG + 0U, // STRL + 0U, // STRV + 0U, // STRVG + 0U, // STRVH + 0U, // STSCH + 0U, // STSI + 0U, // STURA + 0U, // STURG + 0U, // STY + 0U, // SU + 0U, // SUR + 0U, // SVC + 0U, // SW + 0U, // SWR + 0U, // SXBR + 0U, // SXR + 0U, // SXTR + 0U, // SXTRA + 0U, // SY + 0U, // TABORT + 0U, // TAM + 0U, // TAR + 0U, // TB + 0U, // TBDR + 0U, // TBEDR + 0U, // TBEGIN + 0U, // TBEGINC + 0U, // TCDB + 0U, // TCEB + 0U, // TCXB + 0U, // TDCDT + 0U, // TDCET + 0U, // TDCXT + 0U, // TDGDT + 0U, // TDGET + 0U, // TDGXT + 0U, // TEND + 0U, // THDER + 0U, // THDR + 0U, // TM + 0U, // TMHH + 0U, // TMHL + 0U, // TMLH + 0U, // TMLL + 0U, // TMY + 0U, // TP + 0U, // TPI + 0U, // TPROT + 0U, // TR + 0U, // TRACE + 0U, // TRACG + 0U, // TRAP2 + 0U, // TRAP4 + 0U, // TRE + 0U, // TROO + 0U, // TROOOpt + 0U, // TROT + 0U, // TROTOpt + 0U, // TRT + 0U, // TRTE + 0U, // TRTEOpt + 0U, // TRTO + 0U, // TRTOOpt + 0U, // TRTR + 0U, // TRTRE + 0U, // TRTREOpt + 0U, // TRTT + 0U, // TRTTOpt + 0U, // TS + 0U, // TSCH + 0U, // UNPK + 0U, // UNPKA + 0U, // UNPKU + 0U, // UPT + 0U, // VA + 0U, // VAB + 30U, // VAC + 0U, // VACC + 0U, // VACCB + 30U, // VACCC + 2U, // VACCCQ + 0U, // VACCF + 0U, // VACCG + 0U, // VACCH + 0U, // VACCQ + 2U, // VACQ + 0U, // VAF + 0U, // VAG + 0U, // VAH + 30U, // VAP + 0U, // VAQ + 0U, // VAVG + 0U, // VAVGB + 0U, // VAVGF + 0U, // VAVGG + 0U, // VAVGH + 0U, // VAVGL + 0U, // VAVGLB + 0U, // VAVGLF + 0U, // VAVGLG + 0U, // VAVGLH + 0U, // VBPERM + 28U, // VCDG + 0U, // VCDGB + 28U, // VCDLG + 0U, // VCDLGB + 0U, // VCEFB + 0U, // VCELFB + 28U, // VCEQ + 0U, // VCEQB + 0U, // VCEQBS + 0U, // VCEQF + 0U, // VCEQFS + 0U, // VCEQG + 0U, // VCEQGS + 0U, // VCEQH + 0U, // VCEQHS + 0U, // VCFEB + 0U, // VCFN + 28U, // VCFPL + 28U, // VCFPS + 28U, // VCGD + 0U, // VCGDB + 28U, // VCH + 0U, // VCHB + 0U, // VCHBS + 0U, // VCHF + 0U, // VCHFS + 0U, // VCHG + 0U, // VCHGS + 0U, // VCHH + 0U, // VCHHS + 28U, // VCHL + 0U, // VCHLB + 0U, // VCHLBS + 0U, // VCHLF + 0U, // VCHLFS + 0U, // VCHLG + 0U, // VCHLGS + 0U, // VCHLH + 0U, // VCHLHS + 0U, // VCKSM + 0U, // VCLFEB + 0U, // VCLFNH + 0U, // VCLFNL + 28U, // VCLFP + 28U, // VCLGD + 0U, // VCLGDB + 0U, // VCLZ + 0U, // VCLZB + 0U, // VCLZDP + 0U, // VCLZF + 0U, // VCLZG + 0U, // VCLZH + 0U, // VCNF + 0U, // VCP + 28U, // VCRNF + 28U, // VCSFP + 0U, // VCSPH + 0U, // VCTZ + 0U, // VCTZB + 0U, // VCTZF + 0U, // VCTZG + 0U, // VCTZH + 0U, // VCVB + 0U, // VCVBG + 0U, // VCVBGOpt + 0U, // VCVBOpt + 1U, // VCVD + 1U, // VCVDG + 30U, // VDP + 0U, // VEC + 0U, // VECB + 0U, // VECF + 0U, // VECG + 0U, // VECH + 0U, // VECL + 0U, // VECLB + 0U, // VECLF + 0U, // VECLG + 0U, // VECLH + 45U, // VERIM + 1U, // VERIMB + 1U, // VERIMF + 1U, // VERIMG + 1U, // VERIMH + 0U, // VERLL + 0U, // VERLLB + 0U, // VERLLF + 0U, // VERLLG + 0U, // VERLLH + 0U, // VERLLV + 0U, // VERLLVB + 0U, // VERLLVF + 0U, // VERLLVG + 0U, // VERLLVH + 0U, // VESL + 0U, // VESLB + 0U, // VESLF + 0U, // VESLG + 0U, // VESLH + 0U, // VESLV + 0U, // VESLVB + 0U, // VESLVF + 0U, // VESLVG + 0U, // VESLVH + 0U, // VESRA + 0U, // VESRAB + 0U, // VESRAF + 0U, // VESRAG + 0U, // VESRAH + 0U, // VESRAV + 0U, // VESRAVB + 0U, // VESRAVF + 0U, // VESRAVG + 0U, // VESRAVH + 0U, // VESRL + 0U, // VESRLB + 0U, // VESRLF + 0U, // VESRLG + 0U, // VESRLH + 0U, // VESRLV + 0U, // VESRLVB + 0U, // VESRLVF + 0U, // VESRLVG + 0U, // VESRLVH + 28U, // VFA + 0U, // VFADB + 28U, // VFAE + 0U, // VFAEB + 0U, // VFAEBS + 0U, // VFAEF + 0U, // VFAEFS + 0U, // VFAEH + 0U, // VFAEHS + 0U, // VFAEZB + 0U, // VFAEZBS + 0U, // VFAEZF + 0U, // VFAEZFS + 0U, // VFAEZH + 0U, // VFAEZHS + 0U, // VFASB + 92U, // VFCE + 0U, // VFCEDB + 0U, // VFCEDBS + 0U, // VFCESB + 0U, // VFCESBS + 92U, // VFCH + 0U, // VFCHDB + 0U, // VFCHDBS + 92U, // VFCHE + 0U, // VFCHEDB + 0U, // VFCHEDBS + 0U, // VFCHESB + 0U, // VFCHESBS + 0U, // VFCHSB + 0U, // VFCHSBS + 28U, // VFD + 0U, // VFDDB + 0U, // VFDSB + 28U, // VFEE + 0U, // VFEEB + 0U, // VFEEBS + 0U, // VFEEF + 0U, // VFEEFS + 0U, // VFEEH + 0U, // VFEEHS + 0U, // VFEEZB + 0U, // VFEEZBS + 0U, // VFEEZF + 0U, // VFEEZFS + 0U, // VFEEZH + 0U, // VFEEZHS + 28U, // VFENE + 0U, // VFENEB + 0U, // VFENEBS + 0U, // VFENEF + 0U, // VFENEFS + 0U, // VFENEH + 0U, // VFENEHS + 0U, // VFENEZB + 0U, // VFENEZBS + 0U, // VFENEZF + 0U, // VFENEZFS + 0U, // VFENEZH + 0U, // VFENEZHS + 28U, // VFI + 0U, // VFIDB + 0U, // VFISB + 0U, // VFKEDB + 0U, // VFKEDBS + 0U, // VFKESB + 0U, // VFKESBS + 0U, // VFKHDB + 0U, // VFKHDBS + 0U, // VFKHEDB + 0U, // VFKHEDBS + 0U, // VFKHESB + 0U, // VFKHESBS + 0U, // VFKHSB + 0U, // VFKHSBS + 0U, // VFLCDB + 0U, // VFLCSB + 0U, // VFLL + 0U, // VFLLS + 0U, // VFLNDB + 0U, // VFLNSB + 0U, // VFLPDB + 0U, // VFLPSB + 28U, // VFLR + 0U, // VFLRD + 28U, // VFM + 94U, // VFMA + 2U, // VFMADB + 2U, // VFMASB + 92U, // VFMAX + 0U, // VFMAXDB + 0U, // VFMAXSB + 0U, // VFMDB + 92U, // VFMIN + 0U, // VFMINDB + 0U, // VFMINSB + 94U, // VFMS + 0U, // VFMSB + 2U, // VFMSDB + 2U, // VFMSSB + 94U, // VFNMA + 2U, // VFNMADB + 2U, // VFNMASB + 94U, // VFNMS + 2U, // VFNMSDB + 2U, // VFNMSSB + 28U, // VFPSO + 0U, // VFPSODB + 0U, // VFPSOSB + 28U, // VFS + 0U, // VFSDB + 0U, // VFSQ + 0U, // VFSQDB + 0U, // VFSQSB + 0U, // VFSSB + 28U, // VFTCI + 0U, // VFTCIDB + 0U, // VFTCISB + 0U, // VGBM + 0U, // VGEF + 0U, // VGEG + 0U, // VGFM + 30U, // VGFMA + 2U, // VGFMAB + 2U, // VGFMAF + 2U, // VGFMAG + 2U, // VGFMAH + 0U, // VGFMB + 0U, // VGFMF + 0U, // VGFMG + 0U, // VGFMH + 0U, // VGM + 0U, // VGMB + 0U, // VGMF + 0U, // VGMG + 0U, // VGMH + 0U, // VISTR + 0U, // VISTRB + 0U, // VISTRBS + 0U, // VISTRF + 0U, // VISTRFS + 0U, // VISTRH + 0U, // VISTRHS + 0U, // VL + 0U, // VLAlign + 0U, // VLBB + 0U, // VLBR + 0U, // VLBRF + 0U, // VLBRG + 0U, // VLBRH + 0U, // VLBRQ + 0U, // VLBRREP + 0U, // VLBRREPF + 0U, // VLBRREPG + 0U, // VLBRREPH + 0U, // VLC + 0U, // VLCB + 0U, // VLCF + 0U, // VLCG + 0U, // VLCH + 0U, // VLDE + 0U, // VLDEB + 0U, // VLEB + 0U, // VLEBRF + 0U, // VLEBRG + 0U, // VLEBRH + 28U, // VLED + 0U, // VLEDB + 0U, // VLEF + 0U, // VLEG + 0U, // VLEH + 0U, // VLEIB + 0U, // VLEIF + 0U, // VLEIG + 0U, // VLEIH + 0U, // VLER + 0U, // VLERF + 0U, // VLERG + 0U, // VLERH + 0U, // VLGV + 0U, // VLGVB + 0U, // VLGVF + 0U, // VLGVG + 0U, // VLGVH + 0U, // VLIP + 0U, // VLL + 0U, // VLLEBRZ + 0U, // VLLEBRZE + 0U, // VLLEBRZF + 0U, // VLLEBRZG + 0U, // VLLEBRZH + 0U, // VLLEZ + 0U, // VLLEZB + 0U, // VLLEZF + 0U, // VLLEZG + 0U, // VLLEZH + 0U, // VLLEZLF + 0U, // VLM + 0U, // VLMAlign + 0U, // VLP + 0U, // VLPB + 0U, // VLPF + 0U, // VLPG + 0U, // VLPH + 0U, // VLR + 0U, // VLREP + 0U, // VLREPB + 0U, // VLREPF + 0U, // VLREPG + 0U, // VLREPH + 0U, // VLRL + 0U, // VLRLR + 2U, // VLVG + 0U, // VLVGB + 0U, // VLVGF + 0U, // VLVGG + 0U, // VLVGH + 0U, // VLVGP + 30U, // VMAE + 2U, // VMAEB + 2U, // VMAEF + 2U, // VMAEH + 30U, // VMAH + 2U, // VMAHB + 2U, // VMAHF + 2U, // VMAHH + 30U, // VMAL + 2U, // VMALB + 30U, // VMALE + 2U, // VMALEB + 2U, // VMALEF + 2U, // VMALEH + 2U, // VMALF + 30U, // VMALH + 2U, // VMALHB + 2U, // VMALHF + 2U, // VMALHH + 2U, // VMALHW + 30U, // VMALO + 2U, // VMALOB + 2U, // VMALOF + 2U, // VMALOH + 30U, // VMAO + 2U, // VMAOB + 2U, // VMAOF + 2U, // VMAOH + 0U, // VME + 0U, // VMEB + 0U, // VMEF + 0U, // VMEH + 0U, // VMH + 0U, // VMHB + 0U, // VMHF + 0U, // VMHH + 0U, // VML + 0U, // VMLB + 0U, // VMLE + 0U, // VMLEB + 0U, // VMLEF + 0U, // VMLEH + 0U, // VMLF + 0U, // VMLH + 0U, // VMLHB + 0U, // VMLHF + 0U, // VMLHH + 0U, // VMLHW + 0U, // VMLO + 0U, // VMLOB + 0U, // VMLOF + 0U, // VMLOH + 0U, // VMN + 0U, // VMNB + 0U, // VMNF + 0U, // VMNG + 0U, // VMNH + 0U, // VMNL + 0U, // VMNLB + 0U, // VMNLF + 0U, // VMNLG + 0U, // VMNLH + 0U, // VMO + 0U, // VMOB + 0U, // VMOF + 0U, // VMOH + 30U, // VMP + 0U, // VMRH + 0U, // VMRHB + 0U, // VMRHF + 0U, // VMRHG + 0U, // VMRHH + 0U, // VMRL + 0U, // VMRLB + 0U, // VMRLF + 0U, // VMRLG + 0U, // VMRLH + 94U, // VMSL + 30U, // VMSLG + 30U, // VMSP + 0U, // VMX + 0U, // VMXB + 0U, // VMXF + 0U, // VMXG + 0U, // VMXH + 0U, // VMXL + 0U, // VMXLB + 0U, // VMXLF + 0U, // VMXLG + 0U, // VMXLH + 0U, // VN + 0U, // VNC + 0U, // VNN + 0U, // VNO + 0U, // VNX + 0U, // VO + 0U, // VOC + 0U, // VONE + 0U, // VPDI + 2U, // VPERM + 0U, // VPK + 0U, // VPKF + 0U, // VPKG + 0U, // VPKH + 28U, // VPKLS + 0U, // VPKLSF + 0U, // VPKLSFS + 0U, // VPKLSG + 0U, // VPKLSGS + 0U, // VPKLSH + 0U, // VPKLSHS + 28U, // VPKS + 0U, // VPKSF + 0U, // VPKSFS + 0U, // VPKSG + 0U, // VPKSGS + 0U, // VPKSH + 0U, // VPKSHS + 0U, // VPKZ + 30U, // VPKZR + 0U, // VPOPCT + 0U, // VPOPCTB + 0U, // VPOPCTF + 0U, // VPOPCTG + 0U, // VPOPCTH + 0U, // VPSOP + 0U, // VREP + 0U, // VREPB + 0U, // VREPF + 0U, // VREPG + 0U, // VREPH + 0U, // VREPI + 0U, // VREPIB + 0U, // VREPIF + 0U, // VREPIG + 0U, // VREPIH + 30U, // VRP + 0U, // VS + 0U, // VSB + 30U, // VSBCBI + 2U, // VSBCBIQ + 30U, // VSBI + 2U, // VSBIQ + 0U, // VSCBI + 0U, // VSCBIB + 0U, // VSCBIF + 0U, // VSCBIG + 0U, // VSCBIH + 0U, // VSCBIQ + 0U, // VSCEF + 0U, // VSCEG + 0U, // VSCHDP + 28U, // VSCHP + 0U, // VSCHSP + 0U, // VSCHXP + 0U, // VSCSHP + 30U, // VSDP + 0U, // VSEG + 0U, // VSEGB + 0U, // VSEGF + 0U, // VSEGH + 2U, // VSEL + 0U, // VSF + 0U, // VSG + 0U, // VSH + 0U, // VSL + 0U, // VSLB + 2U, // VSLD + 2U, // VSLDB + 30U, // VSP + 0U, // VSQ + 0U, // VSRA + 0U, // VSRAB + 2U, // VSRD + 0U, // VSRL + 0U, // VSRLB + 0U, // VSRP + 30U, // VSRPR + 0U, // VST + 0U, // VSTAlign + 0U, // VSTBR + 0U, // VSTBRF + 0U, // VSTBRG + 0U, // VSTBRH + 0U, // VSTBRQ + 0U, // VSTEB + 0U, // VSTEBRF + 0U, // VSTEBRG + 0U, // VSTEBRH + 0U, // VSTEF + 0U, // VSTEG + 0U, // VSTEH + 0U, // VSTER + 0U, // VSTERF + 0U, // VSTERG + 0U, // VSTERH + 0U, // VSTL + 0U, // VSTM + 0U, // VSTMAlign + 94U, // VSTRC + 30U, // VSTRCB + 30U, // VSTRCBS + 30U, // VSTRCF + 30U, // VSTRCFS + 30U, // VSTRCH + 30U, // VSTRCHS + 30U, // VSTRCZB + 30U, // VSTRCZBS + 30U, // VSTRCZF + 30U, // VSTRCZFS + 30U, // VSTRCZH + 30U, // VSTRCZHS + 0U, // VSTRL + 0U, // VSTRLR + 94U, // VSTRS + 30U, // VSTRSB + 30U, // VSTRSF + 30U, // VSTRSH + 2U, // VSTRSZB + 2U, // VSTRSZF + 2U, // VSTRSZH + 0U, // VSUM + 0U, // VSUMB + 0U, // VSUMG + 0U, // VSUMGF + 0U, // VSUMGH + 0U, // VSUMH + 0U, // VSUMQ + 0U, // VSUMQF + 0U, // VSUMQG + 0U, // VTM + 0U, // VTP + 0U, // VUPH + 0U, // VUPHB + 0U, // VUPHF + 0U, // VUPHH + 0U, // VUPKZ + 0U, // VUPKZH + 0U, // VUPKZL + 0U, // VUPL + 0U, // VUPLB + 0U, // VUPLF + 0U, // VUPLH + 0U, // VUPLHB + 0U, // VUPLHF + 0U, // VUPLHH + 0U, // VUPLHW + 0U, // VUPLL + 0U, // VUPLLB + 0U, // VUPLLF + 0U, // VUPLLH + 0U, // VX + 0U, // VZERO + 0U, // WCDGB + 0U, // WCDLGB + 0U, // WCEFB + 0U, // WCELFB + 0U, // WCFEB + 0U, // WCGDB + 0U, // WCLFEB + 0U, // WCLGDB + 0U, // WFADB + 0U, // WFASB + 0U, // WFAXB + 0U, // WFC + 0U, // WFCDB + 0U, // WFCEDB + 0U, // WFCEDBS + 0U, // WFCESB + 0U, // WFCESBS + 0U, // WFCEXB + 0U, // WFCEXBS + 0U, // WFCHDB + 0U, // WFCHDBS + 0U, // WFCHEDB + 0U, // WFCHEDBS + 0U, // WFCHESB + 0U, // WFCHESBS + 0U, // WFCHEXB + 0U, // WFCHEXBS + 0U, // WFCHSB + 0U, // WFCHSBS + 0U, // WFCHXB + 0U, // WFCHXBS + 0U, // WFCSB + 0U, // WFCXB + 0U, // WFDDB + 0U, // WFDSB + 0U, // WFDXB + 0U, // WFIDB + 0U, // WFISB + 0U, // WFIXB + 0U, // WFK + 0U, // WFKDB + 0U, // WFKEDB + 0U, // WFKEDBS + 0U, // WFKESB + 0U, // WFKESBS + 0U, // WFKEXB + 0U, // WFKEXBS + 0U, // WFKHDB + 0U, // WFKHDBS + 0U, // WFKHEDB + 0U, // WFKHEDBS + 0U, // WFKHESB + 0U, // WFKHESBS + 0U, // WFKHEXB + 0U, // WFKHEXBS + 0U, // WFKHSB + 0U, // WFKHSBS + 0U, // WFKHXB + 0U, // WFKHXBS + 0U, // WFKSB + 0U, // WFKXB + 0U, // WFLCDB + 0U, // WFLCSB + 0U, // WFLCXB + 0U, // WFLLD + 0U, // WFLLS + 0U, // WFLNDB + 0U, // WFLNSB + 0U, // WFLNXB + 0U, // WFLPDB + 0U, // WFLPSB + 0U, // WFLPXB + 0U, // WFLRD + 0U, // WFLRX + 2U, // WFMADB + 2U, // WFMASB + 2U, // WFMAXB + 0U, // WFMAXDB + 0U, // WFMAXSB + 0U, // WFMAXXB + 0U, // WFMDB + 0U, // WFMINDB + 0U, // WFMINSB + 0U, // WFMINXB + 0U, // WFMSB + 2U, // WFMSDB + 2U, // WFMSSB + 2U, // WFMSXB + 0U, // WFMXB + 2U, // WFNMADB + 2U, // WFNMASB + 2U, // WFNMAXB + 2U, // WFNMSDB + 2U, // WFNMSSB + 2U, // WFNMSXB + 0U, // WFPSODB + 0U, // WFPSOSB + 0U, // WFPSOXB + 0U, // WFSDB + 0U, // WFSQDB + 0U, // WFSQSB + 0U, // WFSQXB + 0U, // WFSSB + 0U, // WFSXB + 0U, // WFTCIDB + 0U, // WFTCISB + 0U, // WFTCIXB + 0U, // WLDEB + 0U, // WLEDB + 0U, // X + 0U, // XC + 0U, // XG + 0U, // XGR + 0U, // XGRK + 0U, // XI + 0U, // XIHF + 0U, // XILF + 0U, // XIY + 0U, // XR + 0U, // XRK + 0U, // XSCH + 0U, // XY + 0U, // ZAP + }; + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; + Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; + Bits |= (uint64_t)OpInfo2[MCInst_getOpcode(MI)] << 48; + return createMnemonic(AsmStrs + (Bits & 32767) - 1, Bits); } +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) { + MCMnemonic MnemonicInfo = SystemZ_getMnemonic(MI); + +#ifndef CAPSTONE_DIET + + SStream_concat0(O, MnemonicInfo.first); +#endif + + uint64_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 15) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // A, AD, ADB, ADBR, ADR, ADTR, ADTRA, AE, AEB, AEBR, AER, AFI, AG, AGF, ... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 2: + // AGSI, ALGSI, ALSI, ASI, CFC, CGHSI, CHHSI, CHSI, CLFHSI, CLGHSI, CLHHS... + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 0, O); + break; + case 3: + // AP, CLC, CP, DP, ED, EDMK, MP, MVC, MVCIN, MVN, MVO, MVZ, NC, OC, PACK... + printBDLAddrOperand /* printBDLAddrOperand (+ ) */ (MI, 0, O); + break; + case 4: + // B, BAsmE, BAsmH, BAsmHE, BAsmL, BAsmLE, BAsmLH, BAsmM, BAsmNE, BAsmNH,... + printBDXAddrOperand /* printBDXAddrOperand (+ ) */ (MI, 0, O); + return; + break; + case 5: + // BC, BCR, BIC, BRC, BRCL + printCond4Operand /* printCond4Operand (+ ) */ (MI, 1, O); + break; + case 6: + // BCAsm, BCRAsm, BICAsm, BPP, BPRP, BRCAsm, BRCLAsm, NIAI, PFD, PFDRL + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 7: + // CGIB, CGIJ, CGIT, CGRB, CGRJ, CGRT, CIB, CIJ, CIT, CLFIT, CLGIB, CLGIJ... + printCond4Operand /* printCond4Operand (+ ) */ (MI, 2, O); + SStream_concat0(O, "\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 8: + // CLGT, CLT + printCond4Operand /* printCond4Operand (+ ) */ (MI, 3, O); + SStream_concat0(O, "\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 1, O); + return; + break; + case 9: + // InsnE, InsnRR + printU16ImmOperand /* printU16ImmOperand (+ ) */ (MI, 0, O); + break; + case 10: + // InsnRI, InsnRRE, InsnRRF, InsnRS, InsnRX, InsnS, InsnSI + printU32ImmOperand /* printU32ImmOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ","); + break; + case 11: + // InsnRIE, InsnRIL, InsnRILU, InsnRIS, InsnRRS, InsnRSE, InsnRSI, InsnRS... + printU48ImmOperand /* printU48ImmOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ","); + break; + case 12: + // J, JAsmE, JAsmH, JAsmHE, JAsmL, JAsmLE, JAsmLH, JAsmM, JAsmNE, JAsmNH,... + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 0, O); + return; + break; + case 13: + // KDSA, KIMD, KLMD, KMAC, PFMF, TRTE, TRTEOpt, TRTRE, TRTREOpt + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 14: + // LOC, LOCFH, LOCG + printCond4Operand /* printCond4Operand (+ ) */ (MI, 5, O); + SStream_concat0(O, "\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 2, O); + return; + break; + case 15: + // LOCFHR, LOCGHI, LOCGR, LOCHHI, LOCHI, LOCR, SELFHR, SELGR, SELR, STOC,... + printCond4Operand /* printCond4Operand (+ ) */ (MI, 4, O); + SStream_concat0(O, "\t"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + case 16: + // MVCK, MVCP, MVCS + printBDRAddrOperand /* printBDRAddrOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + case 17: + // SVC + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 0, O); + return; + break; + } + + // Fragment 1 encoded into 5 bits for 18 unique commands. + switch ((Bits >> 20) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // A, AD, ADB, ADBR, ADR, ADTR, ADTRA, AE, AEB, AEBR, AER, AFI, AG, AGF, ... + SStream_concat0(O, ", "); + break; + case 1: + // BC, BIC, BRC, BRCL + SStream_concat0(O, "\t"); + break; + case 2: + // BCAsm, BICAsm, PFD + printBDXAddrOperand /* printBDXAddrOperand (+ ) */ (MI, 1, O); + return; + break; + case 3: + // BCR + SStream_concat0(O, "r\t"); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 4: + // BCRAsm, CGRB, CGRJ, CGRT, CLGRB, CLGRJ, CLGRT, CLRB, CLRJ, CLRT, CRB, ... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 5: + // BPP, BPRP, BRCAsm, BRCLAsm, PFDRL + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 1, O); + break; + case 6: + // BR, BRAsmE, BRAsmH, BRAsmHE, BRAsmL, BRAsmLE, BRAsmLH, BRAsmM, BRAsmNE... + return; + break; + case 7: + // CGIB, CGIJ, CIB, CIJ + printS8ImmOperand /* printS8ImmOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 8: + // CGIT, CIT + printS16ImmOperand /* printS16ImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 9: + // CLFIT, CLGIT + printU16ImmOperand /* printU16ImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 10: + // CLGIB, CLGIJ, CLIB, CLIJ + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 11: + // InsnRR + SStream_concat0(O, ","); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ","); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 12: + // InsnS, InsnSI, InsnSIL, InsnSIY, InsnSSE, InsnSSF, STOC, STOCFH, STOCG + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 1, O); + break; + case 13: + // InsnSS + printBDRAddrOperand /* printBDRAddrOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ","); + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, ","); + printOperand /* printOperand (+ ) */ (MI, 6, O); + return; + break; + case 14: + // InsnVRS + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ","); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 15: + // LOCFHR, LOCGR, LOCR, SELFHR, SELGR, SELR + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 16: + // LOCGHI, LOCHHI, LOCHI + printS16ImmOperand /* printS16ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 17: + // NIAI + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 1, O); + return; + break; + } + + // Fragment 2 encoded into 6 bits for 34 unique commands. + switch ((Bits >> 25) & 63) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // A, AD, ADB, AE, AEB, AG, AGF, AGH, AH, AHY, AL, ALC, ALCG, ALG, ALGF, ... + printBDXAddrOperand /* printBDXAddrOperand (+ ) */ (MI, 2, O); + break; + case 1: + // ADBR, ADR, AEBR, AER, AGFR, AGR, ALCGR, ALCR, ALGFR, ALGR, ALR, AR, AU... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 2: + // ADTR, ADTRA, AGHIK, AGRK, AHHHR, AHHLR, AHIK, ALGHSIK, ALGRK, ALHHHR, ... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 3: + // AFI, AGFI, AIH, ALSIH, ALSIHN, MSFI, MSGFI + printS32ImmOperand /* printS32ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 4: + // AGHI, AHI, CGHSI, CHHSI, CHSI, LOCGHIAsm, LOCGHIAsmE, LOCGHIAsmH, LOCG... + printS16ImmOperand /* printS16ImmOperand (+ ) */ (MI, 2, O); + break; + case 5: + // AGSI, ALGSI, ALSI, ASI + printS8ImmOperand /* printS8ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 6: + // ALFI, ALGFI, NIHF, NILF, OIHF, OILF, SLFI, SLGFI, XIHF, XILF + printU32ImmOperand /* printU32ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 7: + // AP, CP, DP, MP, MVO, PACK, SP, UNPK, ZAP + printBDLAddrOperand /* printBDLAddrOperand (+ ) */ (MI, 3, O); + return; + break; + case 8: + // BAL, BAS, C, CD, CDB, CE, CEB, CG, CGF, CGH, CH, CHF, CHY, CL, CLG, CL... + printBDXAddrOperand /* printBDXAddrOperand (+ ) */ (MI, 1, O); + break; + case 9: + // BCRAsm, BRCAsm, BRCLAsm, CGRT, CLGRT, CLRT, CRT, InsnS, LOCFHR, LOCGR,... + return; + break; + case 10: + // BPP, BPRP, CGRB, CGRJ, CLGRB, CLGRJ, CLRB, CLRJ, CRB, CRJ, SELFHR, SEL... + SStream_concat0(O, ", "); + break; + case 11: + // BRAS, BRASL + printPCRelTLSOperand /* printPCRelTLSOperand (+ ) */ (MI, 1, O); + return; + break; + case 12: + // BRC, BRCL, BRCT, BRCTG, BRCTH + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 2, O); + return; + break; + case 13: + // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 14: + // CDPT, CDZT, CPDT, CPXT, CXPT, CXZT, CZDT, CZXT + printBDLAddrOperand /* printBDLAddrOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 4, O); + return; + break; + case 15: + // CFI, CGFI, CIH, LGFI + printS32ImmOperand /* printS32ImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 16: + // CGFRL, CGHRL, CGRL, CHRL, CLGFRL, CLGHRL, CLGRL, CLHRL, CLRL, CRL, EXR... + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 1, O); + return; + break; + case 17: + // CGHI, CGITAsm, CGITAsmE, CGITAsmH, CGITAsmHE, CGITAsmL, CGITAsmLE, CGI... + printS16ImmOperand /* printS16ImmOperand (+ ) */ (MI, 1, O); + break; + case 18: + // CGIB, CIB, CLC, CLGIB, CLIB, ED, EDMK, MVC, MVCIN, MVN, MVZ, NC, OC, S... + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 3, O); + break; + case 19: + // CGIBAsm, CGIBAsmE, CGIBAsmH, CGIBAsmHE, CGIBAsmL, CGIBAsmLE, CGIBAsmLH... + printS8ImmOperand /* printS8ImmOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 20: + // CGIJ, CIJ, CLGIJ, CLIJ + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 3, O); + return; + break; + case 21: + // CLFHSI, CLGHSI, CLHHSI, IIHH, IIHL, IILH, IILL, NIHH, NIHL, NILH, NILL... + printU16ImmOperand /* printU16ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 22: + // CLFI, CLGFI, CLIH, IIHF, IILF, LLIHF, LLILF + printU32ImmOperand /* printU32ImmOperand (+ ) */ (MI, 1, O); + return; + break; + case 23: + // CLFITAsm, CLFITAsmE, CLFITAsmH, CLFITAsmHE, CLFITAsmL, CLFITAsmLE, CLF... + printU16ImmOperand /* printU16ImmOperand (+ ) */ (MI, 1, O); + break; + case 24: + // CLGIBAsm, CLGIBAsmE, CLGIBAsmH, CLGIBAsmHE, CLGIBAsmL, CLGIBAsmLE, CLG... + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + case 25: + // CLGTAsm, CLTAsm, TRTE, TRTRE + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 3, O); + break; + case 26: + // CLGTAsmE, CLGTAsmH, CLGTAsmHE, CLGTAsmL, CLGTAsmLE, CLGTAsmLH, CLGTAsm... + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 1, O); + break; + case 27: + // CLI, CLIY, MC, MVI, MVIY, NI, NIY, OI, OIY, STNSM, STOSM, TM, TMY, XI,... + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 28: + // CSST, ECTG, LASP, LOCAsm, LOCAsmE, LOCAsmH, LOCAsmHE, LOCAsmL, LOCAsmL... + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 2, O); + break; + case 29: + // ICM, ICMH, ICMY + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 3, O); + return; + break; + case 30: + // InsnRI, InsnRIE, InsnRIL, InsnRILU, InsnRIS, InsnRRE, InsnRRF, InsnRRS... + SStream_concat0(O, ","); + break; + case 31: + // PKA, PKU + printBDLAddrOperand /* printBDLAddrOperand (+ ) */ (MI, 2, O); + return; + break; + case 32: + // VGEF, VGEG + printBDVAddrOperand /* printBDVAddrOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + break; + case 33: + // VSCEF, VSCEG + printBDVAddrOperand /* printBDVAddrOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, ", "); + break; + } + + // Fragment 3 encoded into 5 bits for 22 unique commands. + switch ((Bits >> 31) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // A, AD, ADB, ADBR, ADR, AE, AEB, AEBR, AER, AG, AGF, AGFR, AGH, AGHI, A... + return; + break; + case 1: + // ADTR, ADTRA, AGHIK, AGRK, AHHHR, AHHLR, AHIK, ALGHSIK, ALGRK, ALHHHR, ... + SStream_concat0(O, ", "); + break; + case 2: + // BPP, InsnRX, InsnRXE, InsnRXY, InsnVRX + printBDXAddrOperand /* printBDXAddrOperand (+ ) */ (MI, 2, O); + break; + case 3: + // BPRP, CGIJAsmE, CGIJAsmH, CGIJAsmHE, CGIJAsmL, CGIJAsmLE, CGIJAsmLH, C... + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 2, O); + return; + break; + case 4: + // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 5: + // CGIBAsm, CGIJAsm, CIBAsm, CIJAsm, CLGIBAsm, CLGIJAsm, CLIBAsm, CLIJAsm + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + break; + case 6: + // CGIBAsmE, CGIBAsmH, CGIBAsmHE, CGIBAsmL, CGIBAsmLE, CGIBAsmLH, CGIBAsm... + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 2, O); + break; + case 7: + // CGRB, CLGRB, CLRB, CRB, InsnSSE, InsnSSF + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 3, O); + break; + case 8: + // CGRJ, CLGRJ, CLRJ, CRJ + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 3, O); + return; + break; + case 9: + // InsnRI + printS16ImmOperand /* printS16ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 10: + // InsnRILU + printU32ImmOperand /* printU32ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 11: + // InsnRIS + printS8ImmOperand /* printS8ImmOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ","); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ","); + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 4, O); + return; + break; + case 12: + // InsnSI + printS8ImmOperand /* printS8ImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 13: + // InsnSIL + printU16ImmOperand /* printU16ImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 14: + // InsnSIY + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 15: + // InsnVRV + printBDVAddrOperand /* printBDVAddrOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ","); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 16: + // SELFHR, SELGR, SELR + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + case 17: + // VGEF + printU2ImmOperand /* printU2ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 18: + // VGEG + printU1ImmOperand /* printU1ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 19: + // VGM, VGMB, VGMF, VGMG, VGMH + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 2, O); + break; + case 20: + // VSCEF + printU2ImmOperand /* printU2ImmOperand (+ ) */ (MI, 4, O); + return; + break; + case 21: + // VSCEG + printU1ImmOperand /* printU1ImmOperand (+ ) */ (MI, 4, O); + return; + break; + } + + // Fragment 4 encoded into 6 bits for 33 unique commands. + switch ((Bits >> 36) & 63) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADTR, ADTRA, AGRK, AHHHR, AHHLR, ALGRK, ALHHHR, ALHHLR, ALRK, ARK, AXT... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 1: + // AGHIK, AHIK, ALGHSIK, ALHSIK + printS16ImmOperand /* printS16ImmOperand (+ ) */ (MI, 2, O); + return; + break; + case 2: + // BPP, CFDBR, CFDR, CFEBR, CFER, CFXBR, CFXR, CGDBR, CGDR, CGDTR, CGEBR,... + return; + break; + case 3: + // BRXH, BRXHG, BRXLE, BRXLG, CGIJAsm, CIJAsm, CLGIJAsm, CLIJAsm + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 3, O); + return; + break; + case 4: + // BXH, BXHG, BXLE, BXLEG, CDS, CDSG, CDSY, CGIBAsm, CIBAsm, CLGIBAsm, CL... + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 3, O); + break; + case 5: + // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... + SStream_concat0(O, ", "); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 6: + // CGITAsm, CGRBAsm, CGRJAsm, CGRTAsm, CITAsm, CLFITAsm, CLGITAsm, CLGRBA... + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 2, O); + break; + case 7: + // CGRBAsmE, CGRBAsmH, CGRBAsmHE, CGRBAsmL, CGRBAsmLE, CGRBAsmLH, CGRBAsm... + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 2, O); + break; + case 8: + // CGRJAsmE, CGRJAsmH, CGRJAsmHE, CGRJAsmL, CGRJAsmLE, CGRJAsmLH, CGRJAsm... + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 2, O); + return; + break; + case 9: + // CLCLE, CLCLU, MVCLE, MVCLU + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 4, O); + return; + break; + case 10: + // CLGTAsm, CLTAsm + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 1, O); + return; + break; + case 11: + // CPSDRdd, CPSDRds, CPSDRsd, CPSDRss, CRDTE, CRDTEOpt, IDTE, IDTEOpt, IE... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 12: + // CSST, DFLTCC, ECTG, MVCOS + printOperand /* printOperand (+ ) */ (MI, 4, O); + return; + break; + case 13: + // CU12, CU14, CU21, CU24, CUTFU, CUUTF, LCBB, LOCAsm, LOCFHAsm, LOCGAsm,... + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 4, O); + return; + break; + case 14: + // DIDBR, DIEBR, LPTEA, MADBR, MADR, MAEBR, MAER, MAYHR, MAYLR, MAYR, MSD... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 15: + // InsnRIE, InsnRRF, InsnRRS, InsnRS, InsnRSE, InsnRSI, InsnRSY, InsnRXF,... + SStream_concat0(O, ","); + break; + case 16: + // LOCFHRAsm, LOCGHIAsm, LOCGRAsm, LOCHHIAsm, LOCHIAsm, LOCRAsm, STOCAsm,... + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 17: + // MAD, MADB, MAE, MAEB, MAY, MAYH, MAYL, MSD, MSDB, MSE, MSEB + printBDXAddrOperand /* printBDXAddrOperand (+ ) */ (MI, 3, O); + return; + break; + case 18: + // MY, MYH, MYL, SLDT, SLXT, SRDT, SRXT + printBDXAddrOperand /* printBDXAddrOperand (+ ) */ (MI, 2, O); + return; + break; + case 19: + // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VLRL, VPK... + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 3, O); + break; + case 20: + // SRP, VLEB + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 21: + // VCVD, VCVDG, VPSOP, VSRP + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + break; + case 22: + // VFTCI, VFTCIDB, VFTCISB, WFTCIDB, WFTCISB, WFTCIXB + printU12ImmOperand /* printU12ImmOperand (+ ) */ (MI, 2, O); + break; + case 23: + // VLEBRF, VLEF + printU2ImmOperand /* printU2ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 24: + // VLEBRG, VLEG + printU1ImmOperand /* printU1ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 25: + // VLEBRH, VLEH + printU3ImmOperand /* printU3ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 26: + // VLEIF + printU2ImmOperand /* printU2ImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 27: + // VLEIG + printU1ImmOperand /* printU1ImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 28: + // VLEIH + printU3ImmOperand /* printU3ImmOperand (+ ) */ (MI, 3, O); + return; + break; + case 29: + // VREP, VREPB, VREPF, VREPG, VREPH + printU16ImmOperand /* printU16ImmOperand (+ ) */ (MI, 2, O); + break; + case 30: + // VSTEBRF, VSTEF + printU2ImmOperand /* printU2ImmOperand (+ ) */ (MI, 4, O); + return; + break; + case 31: + // VSTEBRG, VSTEG + printU1ImmOperand /* printU1ImmOperand (+ ) */ (MI, 4, O); + return; + break; + case 32: + // VSTEBRH, VSTEH + printU3ImmOperand /* printU3ImmOperand (+ ) */ (MI, 4, O); + return; + break; + } + + // Fragment 5 encoded into 4 bits for 12 unique commands. + switch ((Bits >> 42) & 15) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADTR, AGRK, AHHHR, AHHLR, ALGRK, ALHHHR, ALHHLR, ALRK, ARK, AXTR, BXH,... + return; + break; + case 1: + // ADTRA, AXTRA, CGRBAsm, CGRJAsm, CLGRBAsm, CLGRJAsm, CLRBAsm, CLRJAsm, ... + SStream_concat0(O, ", "); + break; + case 2: + // InsnRIE, InsnRSI + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 3, O); + return; + break; + case 3: + // InsnRRF, InsnVRR + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ","); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 4, O); + break; + case 4: + // InsnRRS, VCVD, VCVDG + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 3, O); + break; + case 5: + // InsnRS, InsnRSE, InsnRSY + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 3, O); + return; + break; + case 6: + // InsnRXF + printBDXAddrOperand /* printBDXAddrOperand (+ ) */ (MI, 3, O); + return; + break; + case 7: + // InsnSSF + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + case 8: + // InsnVRI + printU12ImmOperand /* printU12ImmOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ","); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, ","); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 9: + // InsnVRX + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 10: + // InsnVSI + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 4, O); + return; + break; + case 11: + // VPSOP, VSRP + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 4, O); + return; + break; + } + + // Fragment 6 encoded into 4 bits for 11 unique commands. + switch ((Bits >> 46) & 15) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, RDP, SDTR... + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 3, O); + break; + case 1: + // CGRBAsm, CLGRBAsm, CLRBAsm, CRBAsm + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 3, O); + return; + break; + case 2: + // CGRJAsm, CLGRJAsm, CLRJAsm, CRJAsm + printPCRelOperand /* printPCRelOperand (+ ) */ (MI, 3, O); + return; + break; + case 3: + // DIDBR, DIEBR, LPTEA, QADTR, QAXTR, RRDTR, RRXTR, VERLL, VESL, VESRA, V... + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 4, O); + return; + break; + case 4: + // InsnRRF, VCVD, VCVDG + return; + break; + case 5: + // InsnRRS, InsnVRR + SStream_concat0(O, ","); + break; + case 6: + // LMD, PLO + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 4, O); + return; + break; + case 7: + // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VERIM, VE... + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 4, O); + break; + case 8: + // VAC, VACCC, VACCCQ, VACQ, VFMA, VFMADB, VFMASB, VFMS, VFMSDB, VFMSSB, ... + printOperand /* printOperand (+ ) */ (MI, 3, O); + break; + case 9: + // VAP, VDP, VMP, VMSP, VPKZR, VRP, VSDP, VSLD, VSLDB, VSP, VSRD, VSRPR + printU8ImmOperand /* printU8ImmOperand (+ ) */ (MI, 3, O); + break; + case 10: + // VLVG + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 5, O); + return; + break; + } + + // Fragment 7 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 50) & 3) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, RDP, SDTR... + return; + break; + case 1: + // InsnRRS + printBDAddrOperand /* printBDAddrOperand (+ ) */ (MI, 4, O); + return; + break; + case 2: + // InsnVRR + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 5, O); + SStream_concat0(O, ","); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 6, O); + return; + break; + case 3: + // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VAC, VACC... + SStream_concat0(O, ", "); + break; + } + + // Fragment 8 encoded into 2 bits for 3 unique commands. + switch ((Bits >> 52) & 3) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG + printU6ImmOperand /* printU6ImmOperand (+ ) */ (MI, 5, O); + return; + break; + case 1: + // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCFPL, VCFPS, VCGD, VCH, VCHL, VCL... + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 4, O); + break; + case 2: + // VERIM + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 5, O); + return; + break; + } + + // Fragment 9 encoded into 1 bits for 2 unique commands. + if ((Bits >> 54) & 1) { + // VFCE, VFCH, VFCHE, VFMA, VFMAX, VFMIN, VFMS, VFNMA, VFNMS, VMSL, VSTRC... + SStream_concat0(O, ", "); + printU4ImmOperand /* printU4ImmOperand (+ ) */ (MI, 5, O); + return; + } else { + // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCFPL, VCFPS, VCGD, VCH, VCHL, VCL... + return; + } +} + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo) { + assert(RegNo && RegNo < 195 && "Invalid register number!"); + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = {/* 0 */ "a10\0" + /* 4 */ "c10\0" + /* 8 */ "f10\0" + /* 12 */ "r10\0" + /* 16 */ "v10\0" + /* 20 */ "v20\0" + /* 24 */ "v30\0" + /* 28 */ "a0\0" + /* 31 */ "c0\0" + /* 34 */ "f0\0" + /* 37 */ "r0\0" + /* 40 */ "v0\0" + /* 43 */ "a11\0" + /* 47 */ "c11\0" + /* 51 */ "f11\0" + /* 55 */ "r11\0" + /* 59 */ "v11\0" + /* 63 */ "v21\0" + /* 67 */ "v31\0" + /* 71 */ "a1\0" + /* 74 */ "c1\0" + /* 77 */ "f1\0" + /* 80 */ "r1\0" + /* 83 */ "v1\0" + /* 86 */ "a12\0" + /* 90 */ "c12\0" + /* 94 */ "f12\0" + /* 98 */ "r12\0" + /* 102 */ "v12\0" + /* 106 */ "v22\0" + /* 110 */ "a2\0" + /* 113 */ "c2\0" + /* 116 */ "f2\0" + /* 119 */ "r2\0" + /* 122 */ "v2\0" + /* 125 */ "a13\0" + /* 129 */ "c13\0" + /* 133 */ "f13\0" + /* 137 */ "r13\0" + /* 141 */ "v13\0" + /* 145 */ "v23\0" + /* 149 */ "a3\0" + /* 152 */ "c3\0" + /* 155 */ "f3\0" + /* 158 */ "r3\0" + /* 161 */ "v3\0" + /* 164 */ "a14\0" + /* 168 */ "c14\0" + /* 172 */ "f14\0" + /* 176 */ "r14\0" + /* 180 */ "v14\0" + /* 184 */ "v24\0" + /* 188 */ "a4\0" + /* 191 */ "c4\0" + /* 194 */ "f4\0" + /* 197 */ "r4\0" + /* 200 */ "v4\0" + /* 203 */ "a15\0" + /* 207 */ "c15\0" + /* 211 */ "f15\0" + /* 215 */ "r15\0" + /* 219 */ "v15\0" + /* 223 */ "v25\0" + /* 227 */ "a5\0" + /* 230 */ "c5\0" + /* 233 */ "f5\0" + /* 236 */ "r5\0" + /* 239 */ "v5\0" + /* 242 */ "v16\0" + /* 246 */ "v26\0" + /* 250 */ "a6\0" + /* 253 */ "c6\0" + /* 256 */ "f6\0" + /* 259 */ "r6\0" + /* 262 */ "v6\0" + /* 265 */ "v17\0" + /* 269 */ "v27\0" + /* 273 */ "a7\0" + /* 276 */ "c7\0" + /* 279 */ "f7\0" + /* 282 */ "r7\0" + /* 285 */ "v7\0" + /* 288 */ "v18\0" + /* 292 */ "v28\0" + /* 296 */ "a8\0" + /* 299 */ "c8\0" + /* 302 */ "f8\0" + /* 305 */ "r8\0" + /* 308 */ "v8\0" + /* 311 */ "v19\0" + /* 315 */ "v29\0" + /* 319 */ "a9\0" + /* 322 */ "c9\0" + /* 325 */ "f9\0" + /* 328 */ "r9\0" + /* 331 */ "v9\0" + /* 334 */ "cc\0" + /* 337 */ "fpc\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint16_t RegAsmOffset[] = { + 334, 337, 28, 71, 110, 149, 188, 227, 250, 273, 296, 319, 0, 43, 86, + 125, 164, 203, 31, 74, 113, 152, 191, 230, 253, 276, 299, 322, 4, 47, + 90, 129, 168, 207, 40, 83, 122, 161, 200, 239, 262, 285, 308, 331, 16, + 59, 102, 141, 180, 219, 242, 265, 288, 311, 20, 63, 106, 145, 184, 223, + 246, 269, 292, 315, 24, 67, 34, 77, 116, 155, 194, 233, 256, 279, 302, + 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, 311, 20, 63, 106, 145, + 184, 223, 246, 269, 292, 315, 24, 67, 34, 77, 194, 233, 302, 325, 94, + 133, 34, 77, 116, 155, 194, 233, 256, 279, 302, 325, 8, 51, 94, 133, + 172, 211, 242, 265, 288, 311, 20, 63, 106, 145, 184, 223, 246, 269, 292, + 315, 24, 67, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, + 98, 137, 176, 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, + 55, 98, 137, 176, 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, + 12, 55, 98, 137, 176, 215, 37, 119, 197, 259, 305, 12, 98, 176, + }; + + assert(*(AsmStrs + RegAsmOffset[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrs + RegAsmOffset[RegNo - 1]; +} +#endif +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +static char *printAliasInstr(MCInst *MI, SStream *OS) { + static const PatternsForOpcode OpToPatterns[] = { + {SystemZ_VFAE, 0, 1}, {SystemZ_VFAEB, 1, 1}, + {SystemZ_VFAEBS, 2, 1}, {SystemZ_VFAEF, 3, 1}, + {SystemZ_VFAEFS, 4, 1}, {SystemZ_VFAEH, 5, 1}, + {SystemZ_VFAEHS, 6, 1}, {SystemZ_VFAEZB, 7, 1}, + {SystemZ_VFAEZBS, 8, 1}, {SystemZ_VFAEZF, 9, 1}, + {SystemZ_VFAEZFS, 10, 1}, {SystemZ_VFAEZH, 11, 1}, + {SystemZ_VFAEZHS, 12, 1}, {SystemZ_VFEE, 13, 1}, + {SystemZ_VFEEB, 14, 1}, {SystemZ_VFEEF, 15, 1}, + {SystemZ_VFEEH, 16, 1}, {SystemZ_VFENE, 17, 1}, + {SystemZ_VFENEB, 18, 1}, {SystemZ_VFENEF, 19, 1}, + {SystemZ_VFENEH, 20, 1}, {SystemZ_VISTR, 21, 1}, + {SystemZ_VISTRB, 22, 1}, {SystemZ_VISTRF, 23, 1}, + {SystemZ_VISTRH, 24, 1}, {SystemZ_VSTRC, 25, 1}, + {SystemZ_VSTRCB, 26, 1}, {SystemZ_VSTRCBS, 27, 1}, + {SystemZ_VSTRCF, 28, 1}, {SystemZ_VSTRCFS, 29, 1}, + {SystemZ_VSTRCH, 30, 1}, {SystemZ_VSTRCHS, 31, 1}, + {SystemZ_VSTRCZB, 32, 1}, {SystemZ_VSTRCZBS, 33, 1}, + {SystemZ_VSTRCZF, 34, 1}, {SystemZ_VSTRCZFS, 35, 1}, + {SystemZ_VSTRCZH, 36, 1}, {SystemZ_VSTRCZHS, 37, 1}, + {SystemZ_VSTRS, 38, 1}, {SystemZ_VSTRSB, 39, 1}, + {SystemZ_VSTRSF, 40, 1}, {SystemZ_VSTRSH, 41, 1}, + }; + + static const AliasPattern Patterns[] = { + // SystemZ::VFAE - 0 + {0, 0, 5, 5}, + // SystemZ::VFAEB - 1 + {22, 5, 4, 4}, + // SystemZ::VFAEBS - 2 + {39, 9, 4, 4}, + // SystemZ::VFAEF - 3 + {57, 13, 4, 4}, + // SystemZ::VFAEFS - 4 + {74, 17, 4, 4}, + // SystemZ::VFAEH - 5 + {92, 21, 4, 4}, + // SystemZ::VFAEHS - 6 + {109, 25, 4, 4}, + // SystemZ::VFAEZB - 7 + {127, 29, 4, 4}, + // SystemZ::VFAEZBS - 8 + {145, 33, 4, 4}, + // SystemZ::VFAEZF - 9 + {164, 37, 4, 4}, + // SystemZ::VFAEZFS - 10 + {182, 41, 4, 4}, + // SystemZ::VFAEZH - 11 + {201, 45, 4, 4}, + // SystemZ::VFAEZHS - 12 + {219, 49, 4, 4}, + // SystemZ::VFEE - 13 + {238, 53, 5, 5}, + // SystemZ::VFEEB - 14 + {260, 58, 4, 4}, + // SystemZ::VFEEF - 15 + {277, 62, 4, 4}, + // SystemZ::VFEEH - 16 + {294, 66, 4, 4}, + // SystemZ::VFENE - 17 + {311, 70, 5, 5}, + // SystemZ::VFENEB - 18 + {334, 75, 4, 4}, + // SystemZ::VFENEF - 19 + {352, 79, 4, 4}, + // SystemZ::VFENEH - 20 + {370, 83, 4, 4}, + // SystemZ::VISTR - 21 + {388, 87, 4, 4}, + // SystemZ::VISTRB - 22 + {407, 91, 3, 3}, + // SystemZ::VISTRF - 23 + {421, 94, 3, 3}, + // SystemZ::VISTRH - 24 + {435, 97, 3, 3}, + // SystemZ::VSTRC - 25 + {449, 100, 6, 6}, + // SystemZ::VSTRCB - 26 + {476, 106, 5, 5}, + // SystemZ::VSTRCBS - 27 + {498, 111, 5, 5}, + // SystemZ::VSTRCF - 28 + {521, 116, 5, 5}, + // SystemZ::VSTRCFS - 29 + {543, 121, 5, 5}, + // SystemZ::VSTRCH - 30 + {566, 126, 5, 5}, + // SystemZ::VSTRCHS - 31 + {588, 131, 5, 5}, + // SystemZ::VSTRCZB - 32 + {611, 136, 5, 5}, + // SystemZ::VSTRCZBS - 33 + {634, 141, 5, 5}, + // SystemZ::VSTRCZF - 34 + {658, 146, 5, 5}, + // SystemZ::VSTRCZFS - 35 + {681, 151, 5, 5}, + // SystemZ::VSTRCZH - 36 + {705, 156, 5, 5}, + // SystemZ::VSTRCZHS - 37 + {728, 161, 5, 5}, + // SystemZ::VSTRS - 38 + {752, 166, 6, 6}, + // SystemZ::VSTRSB - 39 + {779, 172, 5, 5}, + // SystemZ::VSTRSF - 40 + {801, 177, 5, 5}, + // SystemZ::VSTRSH - 41 + {823, 182, 5, 5}, + }; + + static const AliasPatternCond Conds[] = { + // (VFAE VR128:$V1, VR128:$V2, VR128:$V3, imm32zx4:$M4, 0) - 0 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 5 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEBS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 9 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 13 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEFS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 17 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 21 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEHS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 25 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 29 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZBS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 33 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 37 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZFS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 41 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 45 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFAEZHS VR128:$V1, VR128:$V2, VR128:$V3, 0) - 49 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFEE VR128:$V1, VR128:$V2, VR128:$V3, imm32zx4:$M4, 0) - 53 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFEEB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 58 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFEEF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 62 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFEEH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 66 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFENE VR128:$V1, VR128:$V2, VR128:$V3, imm32zx4:$M4, 0) - 70 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFENEB VR128:$V1, VR128:$V2, VR128:$V3, 0) - 75 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFENEF VR128:$V1, VR128:$V2, VR128:$V3, 0) - 79 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VFENEH VR128:$V1, VR128:$V2, VR128:$V3, 0) - 83 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VISTR VR128:$V1, VR128:$V2, imm32zx4:$M3, 0) - 87 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VISTRB VR128:$V1, VR128:$V2, 0) - 91 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VISTRF VR128:$V1, VR128:$V2, 0) - 94 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VISTRH VR128:$V1, VR128:$V2, 0) - 97 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRC VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4_timm:$M5, + // 0) - 100 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCB VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 106 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCBS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 111 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCF VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 116 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCFS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 121 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCH VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 126 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCHS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 131 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZB VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 136 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZBS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 141 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZF VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 146 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZFS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 151 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZH VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 156 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRCZHS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 161 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRS VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, 0) - + // 166 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Ignore, 0}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRSB VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 172 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRSF VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 177 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + // (VSTRSH VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, 0) - 182 + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_RegClass, SystemZ_VR128BitRegClassID}, + {AliasPatternCond_K_Imm, (uint32_t)0}, + }; + + static const char *AsmStrings[] = { + /* 0 */ "vfae $\x01, $\x02, $\x03, $\xFF\x04\x01\0" + /* 22 */ "vfaeb $\x01, $\x02, $\x03\0" + /* 39 */ "vfaebs $\x01, $\x02, $\x03\0" + /* 57 */ "vfaef $\x01, $\x02, $\x03\0" + /* 74 */ "vfaefs $\x01, $\x02, $\x03\0" + /* 92 */ "vfaeh $\x01, $\x02, $\x03\0" + /* 109 */ "vfaehs $\x01, $\x02, $\x03\0" + /* 127 */ "vfaezb $\x01, $\x02, $\x03\0" + /* 145 */ "vfaezbs $\x01, $\x02, $\x03\0" + /* 164 */ "vfaezf $\x01, $\x02, $\x03\0" + /* 182 */ "vfaezfs $\x01, $\x02, $\x03\0" + /* 201 */ "vfaezh $\x01, $\x02, $\x03\0" + /* 219 */ "vfaezhs $\x01, $\x02, $\x03\0" + /* 238 */ "vfee $\x01, $\x02, $\x03, $\xFF\x04\x01\0" + /* 260 */ "vfeeb $\x01, $\x02, $\x03\0" + /* 277 */ "vfeef $\x01, $\x02, $\x03\0" + /* 294 */ "vfeeh $\x01, $\x02, $\x03\0" + /* 311 */ "vfene $\x01, $\x02, $\x03, $\xFF\x04\x01\0" + /* 334 */ "vfeneb $\x01, $\x02, $\x03\0" + /* 352 */ "vfenef $\x01, $\x02, $\x03\0" + /* 370 */ "vfeneh $\x01, $\x02, $\x03\0" + /* 388 */ "vistr $\x01, $\x02, $\xFF\x03\x01\0" + /* 407 */ "vistrb $\x01, $\x02\0" + /* 421 */ "vistrf $\x01, $\x02\0" + /* 435 */ "vistrh $\x01, $\x02\0" + /* 449 */ "vstrc $\x01, $\x02, $\x03, $\x04, $\xFF\x05\x01\0" + /* 476 */ "vstrcb $\x01, $\x02, $\x03, $\x04\0" + /* 498 */ "vstrcbs $\x01, $\x02, $\x03, $\x04\0" + /* 521 */ "vstrcf $\x01, $\x02, $\x03, $\x04\0" + /* 543 */ "vstrcfs $\x01, $\x02, $\x03, $\x04\0" + /* 566 */ "vstrch $\x01, $\x02, $\x03, $\x04\0" + /* 588 */ "vstrchs $\x01, $\x02, $\x03, $\x04\0" + /* 611 */ "vstrczb $\x01, $\x02, $\x03, $\x04\0" + /* 634 */ "vstrczbs $\x01, $\x02, $\x03, $\x04\0" + /* 658 */ "vstrczf $\x01, $\x02, $\x03, $\x04\0" + /* 681 */ "vstrczfs $\x01, $\x02, $\x03, $\x04\0" + /* 705 */ "vstrczh $\x01, $\x02, $\x03, $\x04\0" + /* 728 */ "vstrczhs $\x01, $\x02, $\x03, $\x04\0" + /* 752 */ "vstrs $\x01, $\x02, $\x03, $\x04, $\xFF\x05\x01\0" + /* 779 */ "vstrsb $\x01, $\x02, $\x03, $\x04\0" + /* 801 */ "vstrsf $\x01, $\x02, $\x03, $\x04\0" + /* 823 */ "vstrsh $\x01, $\x02, $\x03, $\x04\0"}; + + const char *AsmString = MCInstPrinter_matchAliasPatterns( + MI, OpToPatterns, Patterns, Conds, AsmStrings, 42); + if (!AsmString) + return false; + + char *tmpString = cs_strdup(AsmString); + + unsigned I = 0; + while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && + AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, "\t"); + ++I; + } + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + int OpIdx = AsmString[I++] - 1; + int PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); + } else { + SStream_concat1(OS, *(tmpString + (I++))); + } + } while (AsmString[I] != '\0'); + } + + return tmpString; +} + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS) { + switch (PrintMethodIdx) { + default: + llvm_unreachable("Unknown PrintMethod kind"); + break; + // printU4ImmOperand + case 0: + printU4ImmOperand(MI, OpIdx, OS); + break; + } +} + +#endif // PRINT_ALIAS_INSTR +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo3[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo4[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo5[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo6[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo7[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo8[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo9[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo10[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo11[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo12[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo13[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo14[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo15[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo16[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo17[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo18[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo19[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo20[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo21[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo22[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo23[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo24[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo25[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo26[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo27[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo28[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo29[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo30[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo31[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo32[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo33[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo34[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo35[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo36[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo37[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo38[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo39[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo40[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo41[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo42[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo43[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo44[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo45[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo46[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo47[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo48[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo49[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo50[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo51[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo52[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo53[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo54[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo55[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo56[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo57[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo58[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo59[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo60[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo61[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo62[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo63[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo64[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo65[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo66[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo67[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo68[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo69[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo70[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo71[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo72[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo73[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo74[] = { + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo75[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo76[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo77[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo78[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo79[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo80[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo81[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo82[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo83[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo84[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo85[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo86[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo87[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo88[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo89[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo90[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo91[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo92[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo93[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo94[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo95[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo96[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo97[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo98[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo99[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo100[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo101[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo102[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo103[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo104[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo105[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo106[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo107[] = { + {SystemZ_GRX32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo108[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo109[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo110[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo111[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo112[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo113[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo114[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo115[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo116[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo117[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo118[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo119[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo120[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo121[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo122[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo123[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo124[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo125[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo126[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo127[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo128[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo129[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo130[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo131[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo132[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo133[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo134[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo135[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo136[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo137[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo138[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo139[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo140[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo141[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo142[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo143[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo144[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo145[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo146[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo147[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo148[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo149[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo150[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo151[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo152[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo153[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo154[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo155[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo156[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo157[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo158[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo159[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo160[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo161[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo162[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo163[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo164[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo165[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo166[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo167[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo168[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo169[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo170[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo171[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo172[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo173[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo174[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo175[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo176[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo177[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo178[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo179[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo180[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo181[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo182[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo183[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo184[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo185[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo186[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo187[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo188[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo189[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo190[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo191[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo192[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo193[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo194[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo195[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo196[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo197[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo198[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo199[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo200[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo201[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo202[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo203[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo204[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo205[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo206[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo207[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo208[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, +}; +static const MCOperandInfo OperandInfo209[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo210[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, +}; +static const MCOperandInfo OperandInfo211[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo212[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo213[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo214[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo215[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo216[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo217[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo218[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo219[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, +}; +static const MCOperandInfo OperandInfo220[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo221[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo222[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo223[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo224[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo225[] = { + {SystemZ_AR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo226[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo227[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo228[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo229[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo230[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo231[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo232[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo233[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo234[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo235[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo236[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo237[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo238[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo239[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo240[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo241[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo242[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo243[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo244[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo245[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo246[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo247[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo248[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo249[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo250[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo251[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo252[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo253[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo254[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo255[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo256[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo257[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo258[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo259[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo260[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo261[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo262[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo263[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo264[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo265[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo266[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_PCREL, 0}, +}; +static const MCOperandInfo OperandInfo267[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo268[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo269[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo270[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo271[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo272[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo273[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo274[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo275[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo276[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo277[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo278[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo279[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo280[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo281[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_AnyRegBitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo282[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo283[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo284[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo285[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo286[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*2*/}, +}; +static const MCOperandInfo OperandInfo287[] = { + {SystemZ_AR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_AR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo288[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo289[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo290[] = { + {SystemZ_CR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_CR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo291[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo292[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo293[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo294[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo295[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo296[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo297[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo298[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo299[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo300[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo301[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo302[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo303[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo304[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo305[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo306[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo307[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo308[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo309[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo310[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo311[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo312[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo313[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo314[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo315[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo316[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo317[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo318[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo319[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo320[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo321[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo322[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo323[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo324[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo325[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo326[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo327[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo328[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo329[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo330[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo331[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo332[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo333[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo334[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo335[] = { + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo336[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo337[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo338[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo339[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo340[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo341[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo342[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo343[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo344[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo345[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo346[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo347[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo348[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo349[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo350[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo351[] = { + {SystemZ_AR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo352[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo353[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo354[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo355[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo356[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo357[] = { + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_FP128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo358[] = { + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo359[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo360[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo361[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo362[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo363[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo364[] = { + {SystemZ_GRH32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo365[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo366[] = { + {SystemZ_FP32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {SystemZ_FP64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo367[] = { + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo368[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, +}; +static const MCOperandInfo OperandInfo369[] = { + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo370[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo371[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, +}; +static const MCOperandInfo OperandInfo372[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo373[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo374[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo375[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo376[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo377[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo378[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo379[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo380[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo381[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo382[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo383[] = { + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo384[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo385[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo386[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo387[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo388[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo389[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo390[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo391[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo392[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo393[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo394[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo395[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo396[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo397[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo398[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo399[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo400[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo401[] = { + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo402[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo403[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo404[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo405[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo406[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo407[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo408[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR32BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, +}; +static const MCOperandInfo OperandInfo409[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_GR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo410[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo411[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_ADDR64BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_MEMORY, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_MEMORY, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo412[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo413[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo414[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo415[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo416[] = { + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo417[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo418[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo419[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR128BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo420[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo421[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo422[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo423[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo424[] = { + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR64BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo425[] = { + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {SystemZ_VR32BitRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; + +extern const MCInstrDesc SystemZInsts[] = { + {1, OperandInfo2}, // Inst #0 = PHI + {0, NULL}, // Inst #1 = INLINEASM + {0, NULL}, // Inst #2 = INLINEASM_BR + {1, OperandInfo3}, // Inst #3 = CFI_INSTRUCTION + {1, OperandInfo3}, // Inst #4 = EH_LABEL + {1, OperandInfo3}, // Inst #5 = GC_LABEL + {1, OperandInfo3}, // Inst #6 = ANNOTATION_LABEL + {0, NULL}, // Inst #7 = KILL + {3, OperandInfo4}, // Inst #8 = EXTRACT_SUBREG + {4, OperandInfo5}, // Inst #9 = INSERT_SUBREG + {1, OperandInfo2}, // Inst #10 = IMPLICIT_DEF + {4, OperandInfo6}, // Inst #11 = SUBREG_TO_REG + {3, OperandInfo4}, // Inst #12 = COPY_TO_REGCLASS + {0, NULL}, // Inst #13 = DBG_VALUE + {0, NULL}, // Inst #14 = DBG_VALUE_LIST + {0, NULL}, // Inst #15 = DBG_INSTR_REF + {0, NULL}, // Inst #16 = DBG_PHI + {1, OperandInfo2}, // Inst #17 = DBG_LABEL + {2, OperandInfo7}, // Inst #18 = REG_SEQUENCE + {2, OperandInfo7}, // Inst #19 = COPY + {0, NULL}, // Inst #20 = BUNDLE + {1, OperandInfo3}, // Inst #21 = LIFETIME_START + {1, OperandInfo3}, // Inst #22 = LIFETIME_END + {4, OperandInfo8}, // Inst #23 = PSEUDO_PROBE + {2, OperandInfo9}, // Inst #24 = ARITH_FENCE + {2, OperandInfo10}, // Inst #25 = STACKMAP + {0, NULL}, // Inst #26 = FENTRY_CALL + {6, OperandInfo11}, // Inst #27 = PATCHPOINT + {1, OperandInfo12}, // Inst #28 = LOAD_STACK_GUARD + {1, OperandInfo3}, // Inst #29 = PREALLOCATED_SETUP + {3, OperandInfo13}, // Inst #30 = PREALLOCATED_ARG + {0, NULL}, // Inst #31 = STATEPOINT + {2, OperandInfo14}, // Inst #32 = LOCAL_ESCAPE + {1, OperandInfo2}, // Inst #33 = FAULTING_OP + {0, NULL}, // Inst #34 = PATCHABLE_OP + {0, NULL}, // Inst #35 = PATCHABLE_FUNCTION_ENTER + {0, NULL}, // Inst #36 = PATCHABLE_RET + {0, NULL}, // Inst #37 = PATCHABLE_FUNCTION_EXIT + {0, NULL}, // Inst #38 = PATCHABLE_TAIL_CALL + {2, OperandInfo15}, // Inst #39 = PATCHABLE_EVENT_CALL + {3, OperandInfo16}, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + {0, NULL}, // Inst #41 = ICALL_BRANCH_FUNNEL + {3, OperandInfo17}, // Inst #42 = G_ASSERT_SEXT + {3, OperandInfo17}, // Inst #43 = G_ASSERT_ZEXT + {3, OperandInfo18}, // Inst #44 = G_ADD + {3, OperandInfo18}, // Inst #45 = G_SUB + {3, OperandInfo18}, // Inst #46 = G_MUL + {3, OperandInfo18}, // Inst #47 = G_SDIV + {3, OperandInfo18}, // Inst #48 = G_UDIV + {3, OperandInfo18}, // Inst #49 = G_SREM + {3, OperandInfo18}, // Inst #50 = G_UREM + {4, OperandInfo19}, // Inst #51 = G_SDIVREM + {4, OperandInfo19}, // Inst #52 = G_UDIVREM + {3, OperandInfo18}, // Inst #53 = G_AND + {3, OperandInfo18}, // Inst #54 = G_OR + {3, OperandInfo18}, // Inst #55 = G_XOR + {1, OperandInfo20}, // Inst #56 = G_IMPLICIT_DEF + {1, OperandInfo20}, // Inst #57 = G_PHI + {2, OperandInfo21}, // Inst #58 = G_FRAME_INDEX + {2, OperandInfo21}, // Inst #59 = G_GLOBAL_VALUE + {3, OperandInfo22}, // Inst #60 = G_EXTRACT + {2, OperandInfo23}, // Inst #61 = G_UNMERGE_VALUES + {4, OperandInfo24}, // Inst #62 = G_INSERT + {2, OperandInfo23}, // Inst #63 = G_MERGE_VALUES + {2, OperandInfo23}, // Inst #64 = G_BUILD_VECTOR + {2, OperandInfo23}, // Inst #65 = G_BUILD_VECTOR_TRUNC + {2, OperandInfo23}, // Inst #66 = G_CONCAT_VECTORS + {2, OperandInfo23}, // Inst #67 = G_PTRTOINT + {2, OperandInfo23}, // Inst #68 = G_INTTOPTR + {2, OperandInfo23}, // Inst #69 = G_BITCAST + {2, OperandInfo25}, // Inst #70 = G_FREEZE + {2, OperandInfo25}, // Inst #71 = G_INTRINSIC_TRUNC + {2, OperandInfo25}, // Inst #72 = G_INTRINSIC_ROUND + {2, OperandInfo23}, // Inst #73 = G_INTRINSIC_LRINT + {2, OperandInfo25}, // Inst #74 = G_INTRINSIC_ROUNDEVEN + {1, OperandInfo20}, // Inst #75 = G_READCYCLECOUNTER + {2, OperandInfo23}, // Inst #76 = G_LOAD + {2, OperandInfo23}, // Inst #77 = G_SEXTLOAD + {2, OperandInfo23}, // Inst #78 = G_ZEXTLOAD + {5, OperandInfo26}, // Inst #79 = G_INDEXED_LOAD + {5, OperandInfo26}, // Inst #80 = G_INDEXED_SEXTLOAD + {5, OperandInfo26}, // Inst #81 = G_INDEXED_ZEXTLOAD + {2, OperandInfo23}, // Inst #82 = G_STORE + {5, OperandInfo27}, // Inst #83 = G_INDEXED_STORE + {5, OperandInfo28}, // Inst #84 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + {4, OperandInfo29}, // Inst #85 = G_ATOMIC_CMPXCHG + {3, OperandInfo30}, // Inst #86 = G_ATOMICRMW_XCHG + {3, OperandInfo30}, // Inst #87 = G_ATOMICRMW_ADD + {3, OperandInfo30}, // Inst #88 = G_ATOMICRMW_SUB + {3, OperandInfo30}, // Inst #89 = G_ATOMICRMW_AND + {3, OperandInfo30}, // Inst #90 = G_ATOMICRMW_NAND + {3, OperandInfo30}, // Inst #91 = G_ATOMICRMW_OR + {3, OperandInfo30}, // Inst #92 = G_ATOMICRMW_XOR + {3, OperandInfo30}, // Inst #93 = G_ATOMICRMW_MAX + {3, OperandInfo30}, // Inst #94 = G_ATOMICRMW_MIN + {3, OperandInfo30}, // Inst #95 = G_ATOMICRMW_UMAX + {3, OperandInfo30}, // Inst #96 = G_ATOMICRMW_UMIN + {3, OperandInfo30}, // Inst #97 = G_ATOMICRMW_FADD + {3, OperandInfo30}, // Inst #98 = G_ATOMICRMW_FSUB + {2, OperandInfo10}, // Inst #99 = G_FENCE + {2, OperandInfo21}, // Inst #100 = G_BRCOND + {1, OperandInfo20}, // Inst #101 = G_BRINDIRECT + {1, OperandInfo2}, // Inst #102 = G_INTRINSIC + {1, OperandInfo2}, // Inst #103 = G_INTRINSIC_W_SIDE_EFFECTS + {2, OperandInfo23}, // Inst #104 = G_ANYEXT + {2, OperandInfo23}, // Inst #105 = G_TRUNC + {2, OperandInfo21}, // Inst #106 = G_CONSTANT + {2, OperandInfo21}, // Inst #107 = G_FCONSTANT + {1, OperandInfo20}, // Inst #108 = G_VASTART + {3, OperandInfo31}, // Inst #109 = G_VAARG + {2, OperandInfo23}, // Inst #110 = G_SEXT + {3, OperandInfo17}, // Inst #111 = G_SEXT_INREG + {2, OperandInfo23}, // Inst #112 = G_ZEXT + {3, OperandInfo32}, // Inst #113 = G_SHL + {3, OperandInfo32}, // Inst #114 = G_LSHR + {3, OperandInfo32}, // Inst #115 = G_ASHR + {4, OperandInfo33}, // Inst #116 = G_FSHL + {4, OperandInfo33}, // Inst #117 = G_FSHR + {3, OperandInfo32}, // Inst #118 = G_ROTR + {3, OperandInfo32}, // Inst #119 = G_ROTL + {4, OperandInfo34}, // Inst #120 = G_ICMP + {4, OperandInfo34}, // Inst #121 = G_FCMP + {4, OperandInfo29}, // Inst #122 = G_SELECT + {4, OperandInfo29}, // Inst #123 = G_UADDO + {5, OperandInfo35}, // Inst #124 = G_UADDE + {4, OperandInfo29}, // Inst #125 = G_USUBO + {5, OperandInfo35}, // Inst #126 = G_USUBE + {4, OperandInfo29}, // Inst #127 = G_SADDO + {5, OperandInfo35}, // Inst #128 = G_SADDE + {4, OperandInfo29}, // Inst #129 = G_SSUBO + {5, OperandInfo35}, // Inst #130 = G_SSUBE + {4, OperandInfo29}, // Inst #131 = G_UMULO + {4, OperandInfo29}, // Inst #132 = G_SMULO + {3, OperandInfo18}, // Inst #133 = G_UMULH + {3, OperandInfo18}, // Inst #134 = G_SMULH + {3, OperandInfo18}, // Inst #135 = G_UADDSAT + {3, OperandInfo18}, // Inst #136 = G_SADDSAT + {3, OperandInfo18}, // Inst #137 = G_USUBSAT + {3, OperandInfo18}, // Inst #138 = G_SSUBSAT + {3, OperandInfo32}, // Inst #139 = G_USHLSAT + {3, OperandInfo32}, // Inst #140 = G_SSHLSAT + {4, OperandInfo36}, // Inst #141 = G_SMULFIX + {4, OperandInfo36}, // Inst #142 = G_UMULFIX + {4, OperandInfo36}, // Inst #143 = G_SMULFIXSAT + {4, OperandInfo36}, // Inst #144 = G_UMULFIXSAT + {4, OperandInfo36}, // Inst #145 = G_SDIVFIX + {4, OperandInfo36}, // Inst #146 = G_UDIVFIX + {4, OperandInfo36}, // Inst #147 = G_SDIVFIXSAT + {4, OperandInfo36}, // Inst #148 = G_UDIVFIXSAT + {3, OperandInfo18}, // Inst #149 = G_FADD + {3, OperandInfo18}, // Inst #150 = G_FSUB + {3, OperandInfo18}, // Inst #151 = G_FMUL + {4, OperandInfo19}, // Inst #152 = G_FMA + {4, OperandInfo19}, // Inst #153 = G_FMAD + {3, OperandInfo18}, // Inst #154 = G_FDIV + {3, OperandInfo18}, // Inst #155 = G_FREM + {3, OperandInfo18}, // Inst #156 = G_FPOW + {3, OperandInfo32}, // Inst #157 = G_FPOWI + {2, OperandInfo25}, // Inst #158 = G_FEXP + {2, OperandInfo25}, // Inst #159 = G_FEXP2 + {2, OperandInfo25}, // Inst #160 = G_FLOG + {2, OperandInfo25}, // Inst #161 = G_FLOG2 + {2, OperandInfo25}, // Inst #162 = G_FLOG10 + {2, OperandInfo25}, // Inst #163 = G_FNEG + {2, OperandInfo23}, // Inst #164 = G_FPEXT + {2, OperandInfo23}, // Inst #165 = G_FPTRUNC + {2, OperandInfo23}, // Inst #166 = G_FPTOSI + {2, OperandInfo23}, // Inst #167 = G_FPTOUI + {2, OperandInfo23}, // Inst #168 = G_SITOFP + {2, OperandInfo23}, // Inst #169 = G_UITOFP + {2, OperandInfo25}, // Inst #170 = G_FABS + {3, OperandInfo32}, // Inst #171 = G_FCOPYSIGN + {2, OperandInfo25}, // Inst #172 = G_FCANONICALIZE + {3, OperandInfo18}, // Inst #173 = G_FMINNUM + {3, OperandInfo18}, // Inst #174 = G_FMAXNUM + {3, OperandInfo18}, // Inst #175 = G_FMINNUM_IEEE + {3, OperandInfo18}, // Inst #176 = G_FMAXNUM_IEEE + {3, OperandInfo18}, // Inst #177 = G_FMINIMUM + {3, OperandInfo18}, // Inst #178 = G_FMAXIMUM + {3, OperandInfo32}, // Inst #179 = G_PTR_ADD + {3, OperandInfo32}, // Inst #180 = G_PTRMASK + {3, OperandInfo18}, // Inst #181 = G_SMIN + {3, OperandInfo18}, // Inst #182 = G_SMAX + {3, OperandInfo18}, // Inst #183 = G_UMIN + {3, OperandInfo18}, // Inst #184 = G_UMAX + {2, OperandInfo25}, // Inst #185 = G_ABS + {2, OperandInfo23}, // Inst #186 = G_LROUND + {2, OperandInfo23}, // Inst #187 = G_LLROUND + {1, OperandInfo2}, // Inst #188 = G_BR + {3, OperandInfo37}, // Inst #189 = G_BRJT + {4, OperandInfo38}, // Inst #190 = G_INSERT_VECTOR_ELT + {3, OperandInfo39}, // Inst #191 = G_EXTRACT_VECTOR_ELT + {4, OperandInfo40}, // Inst #192 = G_SHUFFLE_VECTOR + {2, OperandInfo23}, // Inst #193 = G_CTTZ + {2, OperandInfo23}, // Inst #194 = G_CTTZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #195 = G_CTLZ + {2, OperandInfo23}, // Inst #196 = G_CTLZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #197 = G_CTPOP + {2, OperandInfo25}, // Inst #198 = G_BSWAP + {2, OperandInfo25}, // Inst #199 = G_BITREVERSE + {2, OperandInfo25}, // Inst #200 = G_FCEIL + {2, OperandInfo25}, // Inst #201 = G_FCOS + {2, OperandInfo25}, // Inst #202 = G_FSIN + {2, OperandInfo25}, // Inst #203 = G_FSQRT + {2, OperandInfo25}, // Inst #204 = G_FFLOOR + {2, OperandInfo25}, // Inst #205 = G_FRINT + {2, OperandInfo25}, // Inst #206 = G_FNEARBYINT + {2, OperandInfo23}, // Inst #207 = G_ADDRSPACE_CAST + {2, OperandInfo21}, // Inst #208 = G_BLOCK_ADDR + {2, OperandInfo21}, // Inst #209 = G_JUMP_TABLE + {3, OperandInfo22}, // Inst #210 = G_DYN_STACKALLOC + {3, OperandInfo18}, // Inst #211 = G_STRICT_FADD + {3, OperandInfo18}, // Inst #212 = G_STRICT_FSUB + {3, OperandInfo18}, // Inst #213 = G_STRICT_FMUL + {3, OperandInfo18}, // Inst #214 = G_STRICT_FDIV + {3, OperandInfo18}, // Inst #215 = G_STRICT_FREM + {4, OperandInfo19}, // Inst #216 = G_STRICT_FMA + {2, OperandInfo25}, // Inst #217 = G_STRICT_FSQRT + {2, OperandInfo21}, // Inst #218 = G_READ_REGISTER + {2, OperandInfo41}, // Inst #219 = G_WRITE_REGISTER + {4, OperandInfo42}, // Inst #220 = G_MEMCPY + {3, OperandInfo39}, // Inst #221 = G_MEMCPY_INLINE + {4, OperandInfo42}, // Inst #222 = G_MEMMOVE + {4, OperandInfo42}, // Inst #223 = G_MEMSET + {3, OperandInfo22}, // Inst #224 = G_BZERO + {3, OperandInfo39}, // Inst #225 = G_VECREDUCE_SEQ_FADD + {3, OperandInfo39}, // Inst #226 = G_VECREDUCE_SEQ_FMUL + {2, OperandInfo23}, // Inst #227 = G_VECREDUCE_FADD + {2, OperandInfo23}, // Inst #228 = G_VECREDUCE_FMUL + {2, OperandInfo23}, // Inst #229 = G_VECREDUCE_FMAX + {2, OperandInfo23}, // Inst #230 = G_VECREDUCE_FMIN + {2, OperandInfo23}, // Inst #231 = G_VECREDUCE_ADD + {2, OperandInfo23}, // Inst #232 = G_VECREDUCE_MUL + {2, OperandInfo23}, // Inst #233 = G_VECREDUCE_AND + {2, OperandInfo23}, // Inst #234 = G_VECREDUCE_OR + {2, OperandInfo23}, // Inst #235 = G_VECREDUCE_XOR + {2, OperandInfo23}, // Inst #236 = G_VECREDUCE_SMAX + {2, OperandInfo23}, // Inst #237 = G_VECREDUCE_SMIN + {2, OperandInfo23}, // Inst #238 = G_VECREDUCE_UMAX + {2, OperandInfo23}, // Inst #239 = G_VECREDUCE_UMIN + {4, OperandInfo43}, // Inst #240 = G_SBFX + {4, OperandInfo43}, // Inst #241 = G_UBFX + {5, OperandInfo44}, // Inst #242 = ADB_MemFoldPseudo + {2, OperandInfo10}, // Inst #243 = ADJCALLSTACKDOWN + {2, OperandInfo10}, // Inst #244 = ADJCALLSTACKUP + {4, OperandInfo45}, // Inst #245 = ADJDYNALLOC + {5, OperandInfo46}, // Inst #246 = AEB_MemFoldPseudo + {2, OperandInfo47}, // Inst #247 = AEXT128 + {3, OperandInfo48}, // Inst #248 = AFIMux + {5, OperandInfo49}, // Inst #249 = AG_MemFoldPseudo + {3, OperandInfo48}, // Inst #250 = AHIMux + {3, OperandInfo50}, // Inst #251 = AHIMuxK + {5, OperandInfo49}, // Inst #252 = ALG_MemFoldPseudo + {5, OperandInfo51}, // Inst #253 = AL_MemFoldPseudo + {8, OperandInfo52}, // Inst #254 = ATOMIC_CMP_SWAPW + {7, OperandInfo53}, // Inst #255 = ATOMIC_LOADW_AFI + {7, OperandInfo54}, // Inst #256 = ATOMIC_LOADW_AR + {7, OperandInfo54}, // Inst #257 = ATOMIC_LOADW_MAX + {7, OperandInfo54}, // Inst #258 = ATOMIC_LOADW_MIN + {7, OperandInfo53}, // Inst #259 = ATOMIC_LOADW_NILH + {7, OperandInfo53}, // Inst #260 = ATOMIC_LOADW_NILHi + {7, OperandInfo54}, // Inst #261 = ATOMIC_LOADW_NR + {7, OperandInfo54}, // Inst #262 = ATOMIC_LOADW_NRi + {7, OperandInfo53}, // Inst #263 = ATOMIC_LOADW_OILH + {7, OperandInfo54}, // Inst #264 = ATOMIC_LOADW_OR + {7, OperandInfo54}, // Inst #265 = ATOMIC_LOADW_SR + {7, OperandInfo54}, // Inst #266 = ATOMIC_LOADW_UMAX + {7, OperandInfo54}, // Inst #267 = ATOMIC_LOADW_UMIN + {7, OperandInfo53}, // Inst #268 = ATOMIC_LOADW_XILF + {7, OperandInfo54}, // Inst #269 = ATOMIC_LOADW_XR + {4, OperandInfo55}, // Inst #270 = ATOMIC_LOAD_AFI + {4, OperandInfo56}, // Inst #271 = ATOMIC_LOAD_AGFI + {4, OperandInfo56}, // Inst #272 = ATOMIC_LOAD_AGHI + {4, OperandInfo57}, // Inst #273 = ATOMIC_LOAD_AGR + {4, OperandInfo55}, // Inst #274 = ATOMIC_LOAD_AHI + {4, OperandInfo58}, // Inst #275 = ATOMIC_LOAD_AR + {4, OperandInfo58}, // Inst #276 = ATOMIC_LOAD_MAX_32 + {4, OperandInfo57}, // Inst #277 = ATOMIC_LOAD_MAX_64 + {4, OperandInfo58}, // Inst #278 = ATOMIC_LOAD_MIN_32 + {4, OperandInfo57}, // Inst #279 = ATOMIC_LOAD_MIN_64 + {4, OperandInfo57}, // Inst #280 = ATOMIC_LOAD_NGR + {4, OperandInfo57}, // Inst #281 = ATOMIC_LOAD_NGRi + {4, OperandInfo56}, // Inst #282 = ATOMIC_LOAD_NIHF64 + {4, OperandInfo56}, // Inst #283 = ATOMIC_LOAD_NIHF64i + {4, OperandInfo56}, // Inst #284 = ATOMIC_LOAD_NIHH64 + {4, OperandInfo56}, // Inst #285 = ATOMIC_LOAD_NIHH64i + {4, OperandInfo56}, // Inst #286 = ATOMIC_LOAD_NIHL64 + {4, OperandInfo56}, // Inst #287 = ATOMIC_LOAD_NIHL64i + {4, OperandInfo55}, // Inst #288 = ATOMIC_LOAD_NILF + {4, OperandInfo56}, // Inst #289 = ATOMIC_LOAD_NILF64 + {4, OperandInfo56}, // Inst #290 = ATOMIC_LOAD_NILF64i + {4, OperandInfo55}, // Inst #291 = ATOMIC_LOAD_NILFi + {4, OperandInfo55}, // Inst #292 = ATOMIC_LOAD_NILH + {4, OperandInfo56}, // Inst #293 = ATOMIC_LOAD_NILH64 + {4, OperandInfo56}, // Inst #294 = ATOMIC_LOAD_NILH64i + {4, OperandInfo55}, // Inst #295 = ATOMIC_LOAD_NILHi + {4, OperandInfo55}, // Inst #296 = ATOMIC_LOAD_NILL + {4, OperandInfo56}, // Inst #297 = ATOMIC_LOAD_NILL64 + {4, OperandInfo56}, // Inst #298 = ATOMIC_LOAD_NILL64i + {4, OperandInfo55}, // Inst #299 = ATOMIC_LOAD_NILLi + {4, OperandInfo58}, // Inst #300 = ATOMIC_LOAD_NR + {4, OperandInfo58}, // Inst #301 = ATOMIC_LOAD_NRi + {4, OperandInfo57}, // Inst #302 = ATOMIC_LOAD_OGR + {4, OperandInfo56}, // Inst #303 = ATOMIC_LOAD_OIHF64 + {4, OperandInfo56}, // Inst #304 = ATOMIC_LOAD_OIHH64 + {4, OperandInfo56}, // Inst #305 = ATOMIC_LOAD_OIHL64 + {4, OperandInfo55}, // Inst #306 = ATOMIC_LOAD_OILF + {4, OperandInfo56}, // Inst #307 = ATOMIC_LOAD_OILF64 + {4, OperandInfo55}, // Inst #308 = ATOMIC_LOAD_OILH + {4, OperandInfo56}, // Inst #309 = ATOMIC_LOAD_OILH64 + {4, OperandInfo55}, // Inst #310 = ATOMIC_LOAD_OILL + {4, OperandInfo56}, // Inst #311 = ATOMIC_LOAD_OILL64 + {4, OperandInfo58}, // Inst #312 = ATOMIC_LOAD_OR + {4, OperandInfo57}, // Inst #313 = ATOMIC_LOAD_SGR + {4, OperandInfo58}, // Inst #314 = ATOMIC_LOAD_SR + {4, OperandInfo58}, // Inst #315 = ATOMIC_LOAD_UMAX_32 + {4, OperandInfo57}, // Inst #316 = ATOMIC_LOAD_UMAX_64 + {4, OperandInfo58}, // Inst #317 = ATOMIC_LOAD_UMIN_32 + {4, OperandInfo57}, // Inst #318 = ATOMIC_LOAD_UMIN_64 + {4, OperandInfo57}, // Inst #319 = ATOMIC_LOAD_XGR + {4, OperandInfo56}, // Inst #320 = ATOMIC_LOAD_XIHF64 + {4, OperandInfo55}, // Inst #321 = ATOMIC_LOAD_XILF + {4, OperandInfo56}, // Inst #322 = ATOMIC_LOAD_XILF64 + {4, OperandInfo58}, // Inst #323 = ATOMIC_LOAD_XR + {7, OperandInfo54}, // Inst #324 = ATOMIC_SWAPW + {4, OperandInfo58}, // Inst #325 = ATOMIC_SWAP_32 + {4, OperandInfo57}, // Inst #326 = ATOMIC_SWAP_64 + {5, OperandInfo51}, // Inst #327 = A_MemFoldPseudo + {2, OperandInfo59}, // Inst #328 = CFIMux + {4, OperandInfo60}, // Inst #329 = CGIBCall + {3, OperandInfo61}, // Inst #330 = CGIBReturn + {4, OperandInfo62}, // Inst #331 = CGRBCall + {3, OperandInfo63}, // Inst #332 = CGRBReturn + {2, OperandInfo59}, // Inst #333 = CHIMux + {4, OperandInfo64}, // Inst #334 = CIBCall + {3, OperandInfo65}, // Inst #335 = CIBReturn + {5, OperandInfo66}, // Inst #336 = CLCImm + {5, OperandInfo67}, // Inst #337 = CLCReg + {2, OperandInfo59}, // Inst #338 = CLFIMux + {4, OperandInfo60}, // Inst #339 = CLGIBCall + {3, OperandInfo61}, // Inst #340 = CLGIBReturn + {4, OperandInfo62}, // Inst #341 = CLGRBCall + {3, OperandInfo63}, // Inst #342 = CLGRBReturn + {4, OperandInfo64}, // Inst #343 = CLIBCall + {3, OperandInfo65}, // Inst #344 = CLIBReturn + {4, OperandInfo68}, // Inst #345 = CLMux + {4, OperandInfo69}, // Inst #346 = CLRBCall + {3, OperandInfo70}, // Inst #347 = CLRBReturn + {4, OperandInfo71}, // Inst #348 = CLSTLoop + {4, OperandInfo68}, // Inst #349 = CMux + {4, OperandInfo69}, // Inst #350 = CRBCall + {3, OperandInfo70}, // Inst #351 = CRBReturn + {1, OperandInfo72}, // Inst #352 = CallBASR + {1, OperandInfo72}, // Inst #353 = CallBASR_XPLINK64 + {3, OperandInfo73}, // Inst #354 = CallBCR + {1, OperandInfo72}, // Inst #355 = CallBR + {1, OperandInfo74}, // Inst #356 = CallBRASL + {1, OperandInfo74}, // Inst #357 = CallBRASL_XPLINK64 + {3, OperandInfo75}, // Inst #358 = CallBRCL + {1, OperandInfo74}, // Inst #359 = CallJG + {2, OperandInfo10}, // Inst #360 = CondReturn + {6, OperandInfo76}, // Inst #361 = CondStore16 + {6, OperandInfo76}, // Inst #362 = CondStore16Inv + {6, OperandInfo77}, // Inst #363 = CondStore16Mux + {6, OperandInfo77}, // Inst #364 = CondStore16MuxInv + {6, OperandInfo76}, // Inst #365 = CondStore32 + {6, OperandInfo76}, // Inst #366 = CondStore32Inv + {6, OperandInfo77}, // Inst #367 = CondStore32Mux + {6, OperandInfo77}, // Inst #368 = CondStore32MuxInv + {6, OperandInfo78}, // Inst #369 = CondStore64 + {6, OperandInfo78}, // Inst #370 = CondStore64Inv + {6, OperandInfo76}, // Inst #371 = CondStore8 + {6, OperandInfo76}, // Inst #372 = CondStore8Inv + {6, OperandInfo77}, // Inst #373 = CondStore8Mux + {6, OperandInfo77}, // Inst #374 = CondStore8MuxInv + {6, OperandInfo79}, // Inst #375 = CondStoreF32 + {6, OperandInfo79}, // Inst #376 = CondStoreF32Inv + {6, OperandInfo80}, // Inst #377 = CondStoreF64 + {6, OperandInfo80}, // Inst #378 = CondStoreF64Inv + {2, OperandInfo10}, // Inst #379 = CondTrap + {5, OperandInfo44}, // Inst #380 = DDB_MemFoldPseudo + {5, OperandInfo46}, // Inst #381 = DEB_MemFoldPseudo + {6, OperandInfo81}, // Inst #382 = EXRL_Pseudo + {1, OperandInfo82}, // Inst #383 = GOT + {2, OperandInfo59}, // Inst #384 = IIFMux + {3, OperandInfo83}, // Inst #385 = IIHF64 + {3, OperandInfo83}, // Inst #386 = IIHH64 + {3, OperandInfo83}, // Inst #387 = IIHL64 + {3, OperandInfo48}, // Inst #388 = IIHMux + {3, OperandInfo83}, // Inst #389 = IILF64 + {3, OperandInfo83}, // Inst #390 = IILH64 + {3, OperandInfo83}, // Inst #391 = IILL64 + {3, OperandInfo48}, // Inst #392 = IILMux + {4, OperandInfo84}, // Inst #393 = L128 + {4, OperandInfo68}, // Inst #394 = LBMux + {2, OperandInfo85}, // Inst #395 = LEFR + {2, OperandInfo86}, // Inst #396 = LFER + {2, OperandInfo59}, // Inst #397 = LHIMux + {4, OperandInfo68}, // Inst #398 = LHMux + {4, OperandInfo68}, // Inst #399 = LLCMux + {2, OperandInfo87}, // Inst #400 = LLCRMux + {4, OperandInfo68}, // Inst #401 = LLHMux + {2, OperandInfo87}, // Inst #402 = LLHRMux + {4, OperandInfo68}, // Inst #403 = LMux + {6, OperandInfo88}, // Inst #404 = LOCG_MemFoldPseudo + {5, OperandInfo89}, // Inst #405 = LOCHIMux + {6, OperandInfo90}, // Inst #406 = LOCMux + {6, OperandInfo91}, // Inst #407 = LOCMux_MemFoldPseudo + {5, OperandInfo92}, // Inst #408 = LOCRMux + {2, OperandInfo93}, // Inst #409 = LTDBRCompare_VecPseudo + {2, OperandInfo94}, // Inst #410 = LTEBRCompare_VecPseudo + {2, OperandInfo95}, // Inst #411 = LTXBRCompare_VecPseudo + {4, OperandInfo96}, // Inst #412 = LX + {6, OperandInfo97}, // Inst #413 = MADB_MemFoldPseudo + {6, OperandInfo98}, // Inst #414 = MAEB_MemFoldPseudo + {5, OperandInfo44}, // Inst #415 = MDB_MemFoldPseudo + {5, OperandInfo46}, // Inst #416 = MEEB_MemFoldPseudo + {5, OperandInfo51}, // Inst #417 = MSC_MemFoldPseudo + {6, OperandInfo97}, // Inst #418 = MSDB_MemFoldPseudo + {6, OperandInfo98}, // Inst #419 = MSEB_MemFoldPseudo + {5, OperandInfo49}, // Inst #420 = MSGC_MemFoldPseudo + {5, OperandInfo66}, // Inst #421 = MVCImm + {5, OperandInfo67}, // Inst #422 = MVCReg + {4, OperandInfo71}, // Inst #423 = MVSTLoop + {0, NULL}, // Inst #424 = MemBarrier + {5, OperandInfo66}, // Inst #425 = NCImm + {5, OperandInfo67}, // Inst #426 = NCReg + {5, OperandInfo49}, // Inst #427 = NG_MemFoldPseudo + {3, OperandInfo48}, // Inst #428 = NIFMux + {3, OperandInfo83}, // Inst #429 = NIHF64 + {3, OperandInfo83}, // Inst #430 = NIHH64 + {3, OperandInfo83}, // Inst #431 = NIHL64 + {3, OperandInfo48}, // Inst #432 = NIHMux + {3, OperandInfo83}, // Inst #433 = NILF64 + {3, OperandInfo83}, // Inst #434 = NILH64 + {3, OperandInfo83}, // Inst #435 = NILL64 + {3, OperandInfo48}, // Inst #436 = NILMux + {5, OperandInfo51}, // Inst #437 = N_MemFoldPseudo + {5, OperandInfo66}, // Inst #438 = OCImm + {5, OperandInfo67}, // Inst #439 = OCReg + {5, OperandInfo49}, // Inst #440 = OG_MemFoldPseudo + {3, OperandInfo48}, // Inst #441 = OIFMux + {3, OperandInfo83}, // Inst #442 = OIHF64 + {3, OperandInfo83}, // Inst #443 = OIHH64 + {3, OperandInfo83}, // Inst #444 = OIHL64 + {3, OperandInfo48}, // Inst #445 = OIHMux + {3, OperandInfo83}, // Inst #446 = OILF64 + {3, OperandInfo83}, // Inst #447 = OILH64 + {3, OperandInfo83}, // Inst #448 = OILL64 + {3, OperandInfo48}, // Inst #449 = OILMux + {5, OperandInfo51}, // Inst #450 = O_MemFoldPseudo + {3, OperandInfo99}, // Inst #451 = PAIR128 + {3, OperandInfo100}, // Inst #452 = PROBED_ALLOCA + {1, OperandInfo3}, // Inst #453 = PROBED_STACKALLOC + {6, OperandInfo101}, // Inst #454 = RISBHH + {6, OperandInfo102}, // Inst #455 = RISBHL + {6, OperandInfo103}, // Inst #456 = RISBLH + {6, OperandInfo104}, // Inst #457 = RISBLL + {6, OperandInfo105}, // Inst #458 = RISBMux + {0, NULL}, // Inst #459 = Return + {5, OperandInfo44}, // Inst #460 = SDB_MemFoldPseudo + {5, OperandInfo46}, // Inst #461 = SEB_MemFoldPseudo + {5, OperandInfo106}, // Inst #462 = SELRMux + {5, OperandInfo49}, // Inst #463 = SG_MemFoldPseudo + {5, OperandInfo49}, // Inst #464 = SLG_MemFoldPseudo + {5, OperandInfo51}, // Inst #465 = SL_MemFoldPseudo + {4, OperandInfo71}, // Inst #466 = SRSTLoop + {4, OperandInfo84}, // Inst #467 = ST128 + {4, OperandInfo68}, // Inst #468 = STCMux + {4, OperandInfo68}, // Inst #469 = STHMux + {4, OperandInfo68}, // Inst #470 = STMux + {5, OperandInfo107}, // Inst #471 = STOCMux + {4, OperandInfo96}, // Inst #472 = STX + {5, OperandInfo51}, // Inst #473 = S_MemFoldPseudo + {5, OperandInfo108}, // Inst #474 = Select32 + {5, OperandInfo109}, // Inst #475 = Select64 + {5, OperandInfo110}, // Inst #476 = SelectF128 + {5, OperandInfo111}, // Inst #477 = SelectF32 + {5, OperandInfo112}, // Inst #478 = SelectF64 + {5, OperandInfo113}, // Inst #479 = SelectVR128 + {5, OperandInfo114}, // Inst #480 = SelectVR32 + {5, OperandInfo115}, // Inst #481 = SelectVR64 + {0, NULL}, // Inst #482 = Serialize + {3, OperandInfo116}, // Inst #483 = TBEGIN_nofloat + {1, OperandInfo2}, // Inst #484 = TLS_GDCALL + {1, OperandInfo2}, // Inst #485 = TLS_LDCALL + {2, OperandInfo117}, // Inst #486 = TMHH64 + {2, OperandInfo117}, // Inst #487 = TMHL64 + {2, OperandInfo59}, // Inst #488 = TMHMux + {2, OperandInfo117}, // Inst #489 = TMLH64 + {2, OperandInfo117}, // Inst #490 = TMLL64 + {2, OperandInfo59}, // Inst #491 = TMLMux + {0, NULL}, // Inst #492 = Trap + {4, OperandInfo118}, // Inst #493 = VL32 + {4, OperandInfo119}, // Inst #494 = VL64 + {2, OperandInfo120}, // Inst #495 = VLR32 + {2, OperandInfo121}, // Inst #496 = VLR64 + {3, OperandInfo122}, // Inst #497 = VLVGP32 + {4, OperandInfo118}, // Inst #498 = VST32 + {4, OperandInfo119}, // Inst #499 = VST64 + {5, OperandInfo66}, // Inst #500 = XCImm + {5, OperandInfo67}, // Inst #501 = XCReg + {5, OperandInfo49}, // Inst #502 = XG_MemFoldPseudo + {3, OperandInfo48}, // Inst #503 = XIFMux + {3, OperandInfo83}, // Inst #504 = XIHF64 + {3, OperandInfo83}, // Inst #505 = XILF64 + {5, OperandInfo51}, // Inst #506 = X_MemFoldPseudo + {2, OperandInfo47}, // Inst #507 = ZEXT128 + {5, OperandInfo123}, // Inst #508 = A + {5, OperandInfo124}, // Inst #509 = AD + {5, OperandInfo124}, // Inst #510 = ADB + {3, OperandInfo125}, // Inst #511 = ADBR + {3, OperandInfo125}, // Inst #512 = ADR + {3, OperandInfo126}, // Inst #513 = ADTR + {4, OperandInfo127}, // Inst #514 = ADTRA + {5, OperandInfo128}, // Inst #515 = AE + {5, OperandInfo128}, // Inst #516 = AEB + {3, OperandInfo129}, // Inst #517 = AEBR + {3, OperandInfo129}, // Inst #518 = AER + {3, OperandInfo130}, // Inst #519 = AFI + {5, OperandInfo131}, // Inst #520 = AG + {5, OperandInfo131}, // Inst #521 = AGF + {3, OperandInfo83}, // Inst #522 = AGFI + {3, OperandInfo132}, // Inst #523 = AGFR + {5, OperandInfo131}, // Inst #524 = AGH + {3, OperandInfo83}, // Inst #525 = AGHI + {3, OperandInfo63}, // Inst #526 = AGHIK + {3, OperandInfo133}, // Inst #527 = AGR + {3, OperandInfo100}, // Inst #528 = AGRK + {3, OperandInfo116}, // Inst #529 = AGSI + {5, OperandInfo123}, // Inst #530 = AH + {3, OperandInfo134}, // Inst #531 = AHHHR + {3, OperandInfo135}, // Inst #532 = AHHLR + {3, OperandInfo130}, // Inst #533 = AHI + {3, OperandInfo70}, // Inst #534 = AHIK + {5, OperandInfo123}, // Inst #535 = AHY + {3, OperandInfo136}, // Inst #536 = AIH + {5, OperandInfo123}, // Inst #537 = AL + {5, OperandInfo123}, // Inst #538 = ALC + {5, OperandInfo131}, // Inst #539 = ALCG + {3, OperandInfo133}, // Inst #540 = ALCGR + {3, OperandInfo137}, // Inst #541 = ALCR + {3, OperandInfo130}, // Inst #542 = ALFI + {5, OperandInfo131}, // Inst #543 = ALG + {5, OperandInfo131}, // Inst #544 = ALGF + {3, OperandInfo83}, // Inst #545 = ALGFI + {3, OperandInfo132}, // Inst #546 = ALGFR + {3, OperandInfo63}, // Inst #547 = ALGHSIK + {3, OperandInfo133}, // Inst #548 = ALGR + {3, OperandInfo100}, // Inst #549 = ALGRK + {3, OperandInfo116}, // Inst #550 = ALGSI + {3, OperandInfo134}, // Inst #551 = ALHHHR + {3, OperandInfo135}, // Inst #552 = ALHHLR + {3, OperandInfo70}, // Inst #553 = ALHSIK + {3, OperandInfo137}, // Inst #554 = ALR + {3, OperandInfo138}, // Inst #555 = ALRK + {3, OperandInfo116}, // Inst #556 = ALSI + {3, OperandInfo136}, // Inst #557 = ALSIH + {3, OperandInfo136}, // Inst #558 = ALSIHN + {5, OperandInfo123}, // Inst #559 = ALY + {6, OperandInfo139}, // Inst #560 = AP + {3, OperandInfo137}, // Inst #561 = AR + {3, OperandInfo138}, // Inst #562 = ARK + {3, OperandInfo116}, // Inst #563 = ASI + {5, OperandInfo128}, // Inst #564 = AU + {3, OperandInfo129}, // Inst #565 = AUR + {5, OperandInfo124}, // Inst #566 = AW + {3, OperandInfo125}, // Inst #567 = AWR + {3, OperandInfo140}, // Inst #568 = AXBR + {3, OperandInfo140}, // Inst #569 = AXR + {3, OperandInfo141}, // Inst #570 = AXTR + {4, OperandInfo142}, // Inst #571 = AXTRA + {5, OperandInfo123}, // Inst #572 = AY + {3, OperandInfo143}, // Inst #573 = B + {2, OperandInfo144}, // Inst #574 = BAKR + {4, OperandInfo45}, // Inst #575 = BAL + {2, OperandInfo145}, // Inst #576 = BALR + {4, OperandInfo45}, // Inst #577 = BAS + {2, OperandInfo145}, // Inst #578 = BASR + {2, OperandInfo145}, // Inst #579 = BASSM + {3, OperandInfo143}, // Inst #580 = BAsmE + {3, OperandInfo143}, // Inst #581 = BAsmH + {3, OperandInfo143}, // Inst #582 = BAsmHE + {3, OperandInfo143}, // Inst #583 = BAsmL + {3, OperandInfo143}, // Inst #584 = BAsmLE + {3, OperandInfo143}, // Inst #585 = BAsmLH + {3, OperandInfo143}, // Inst #586 = BAsmM + {3, OperandInfo143}, // Inst #587 = BAsmNE + {3, OperandInfo143}, // Inst #588 = BAsmNH + {3, OperandInfo143}, // Inst #589 = BAsmNHE + {3, OperandInfo143}, // Inst #590 = BAsmNL + {3, OperandInfo143}, // Inst #591 = BAsmNLE + {3, OperandInfo143}, // Inst #592 = BAsmNLH + {3, OperandInfo143}, // Inst #593 = BAsmNM + {3, OperandInfo143}, // Inst #594 = BAsmNO + {3, OperandInfo143}, // Inst #595 = BAsmNP + {3, OperandInfo143}, // Inst #596 = BAsmNZ + {3, OperandInfo143}, // Inst #597 = BAsmO + {3, OperandInfo143}, // Inst #598 = BAsmP + {3, OperandInfo143}, // Inst #599 = BAsmZ + {5, OperandInfo146}, // Inst #600 = BC + {4, OperandInfo147}, // Inst #601 = BCAsm + {3, OperandInfo148}, // Inst #602 = BCR + {2, OperandInfo149}, // Inst #603 = BCRAsm + {5, OperandInfo123}, // Inst #604 = BCT + {5, OperandInfo131}, // Inst #605 = BCTG + {3, OperandInfo133}, // Inst #606 = BCTGR + {3, OperandInfo150}, // Inst #607 = BCTR + {3, OperandInfo143}, // Inst #608 = BI + {3, OperandInfo143}, // Inst #609 = BIAsmE + {3, OperandInfo143}, // Inst #610 = BIAsmH + {3, OperandInfo143}, // Inst #611 = BIAsmHE + {3, OperandInfo143}, // Inst #612 = BIAsmL + {3, OperandInfo143}, // Inst #613 = BIAsmLE + {3, OperandInfo143}, // Inst #614 = BIAsmLH + {3, OperandInfo143}, // Inst #615 = BIAsmM + {3, OperandInfo143}, // Inst #616 = BIAsmNE + {3, OperandInfo143}, // Inst #617 = BIAsmNH + {3, OperandInfo143}, // Inst #618 = BIAsmNHE + {3, OperandInfo143}, // Inst #619 = BIAsmNL + {3, OperandInfo143}, // Inst #620 = BIAsmNLE + {3, OperandInfo143}, // Inst #621 = BIAsmNLH + {3, OperandInfo143}, // Inst #622 = BIAsmNM + {3, OperandInfo143}, // Inst #623 = BIAsmNO + {3, OperandInfo143}, // Inst #624 = BIAsmNP + {3, OperandInfo143}, // Inst #625 = BIAsmNZ + {3, OperandInfo143}, // Inst #626 = BIAsmO + {3, OperandInfo143}, // Inst #627 = BIAsmP + {3, OperandInfo143}, // Inst #628 = BIAsmZ + {5, OperandInfo146}, // Inst #629 = BIC + {4, OperandInfo147}, // Inst #630 = BICAsm + {5, OperandInfo151}, // Inst #631 = BPP + {3, OperandInfo152}, // Inst #632 = BPRP + {1, OperandInfo72}, // Inst #633 = BR + {3, OperandInfo153}, // Inst #634 = BRAS + {3, OperandInfo153}, // Inst #635 = BRASL + {1, OperandInfo72}, // Inst #636 = BRAsmE + {1, OperandInfo72}, // Inst #637 = BRAsmH + {1, OperandInfo72}, // Inst #638 = BRAsmHE + {1, OperandInfo72}, // Inst #639 = BRAsmL + {1, OperandInfo72}, // Inst #640 = BRAsmLE + {1, OperandInfo72}, // Inst #641 = BRAsmLH + {1, OperandInfo72}, // Inst #642 = BRAsmM + {1, OperandInfo72}, // Inst #643 = BRAsmNE + {1, OperandInfo72}, // Inst #644 = BRAsmNH + {1, OperandInfo72}, // Inst #645 = BRAsmNHE + {1, OperandInfo72}, // Inst #646 = BRAsmNL + {1, OperandInfo72}, // Inst #647 = BRAsmNLE + {1, OperandInfo72}, // Inst #648 = BRAsmNLH + {1, OperandInfo72}, // Inst #649 = BRAsmNM + {1, OperandInfo72}, // Inst #650 = BRAsmNO + {1, OperandInfo72}, // Inst #651 = BRAsmNP + {1, OperandInfo72}, // Inst #652 = BRAsmNZ + {1, OperandInfo72}, // Inst #653 = BRAsmO + {1, OperandInfo72}, // Inst #654 = BRAsmP + {1, OperandInfo72}, // Inst #655 = BRAsmZ + {3, OperandInfo75}, // Inst #656 = BRC + {2, OperandInfo154}, // Inst #657 = BRCAsm + {3, OperandInfo75}, // Inst #658 = BRCL + {2, OperandInfo154}, // Inst #659 = BRCLAsm + {3, OperandInfo155}, // Inst #660 = BRCT + {3, OperandInfo156}, // Inst #661 = BRCTG + {3, OperandInfo157}, // Inst #662 = BRCTH + {4, OperandInfo158}, // Inst #663 = BRXH + {4, OperandInfo159}, // Inst #664 = BRXHG + {4, OperandInfo158}, // Inst #665 = BRXLE + {4, OperandInfo159}, // Inst #666 = BRXLG + {2, OperandInfo144}, // Inst #667 = BSA + {2, OperandInfo144}, // Inst #668 = BSG + {2, OperandInfo145}, // Inst #669 = BSM + {5, OperandInfo160}, // Inst #670 = BXH + {5, OperandInfo161}, // Inst #671 = BXHG + {5, OperandInfo160}, // Inst #672 = BXLE + {5, OperandInfo161}, // Inst #673 = BXLEG + {4, OperandInfo162}, // Inst #674 = C + {4, OperandInfo163}, // Inst #675 = CD + {4, OperandInfo163}, // Inst #676 = CDB + {2, OperandInfo93}, // Inst #677 = CDBR + {2, OperandInfo164}, // Inst #678 = CDFBR + {4, OperandInfo165}, // Inst #679 = CDFBRA + {2, OperandInfo164}, // Inst #680 = CDFR + {4, OperandInfo165}, // Inst #681 = CDFTR + {2, OperandInfo166}, // Inst #682 = CDGBR + {4, OperandInfo167}, // Inst #683 = CDGBRA + {2, OperandInfo166}, // Inst #684 = CDGR + {2, OperandInfo166}, // Inst #685 = CDGTR + {4, OperandInfo167}, // Inst #686 = CDGTRA + {4, OperandInfo165}, // Inst #687 = CDLFBR + {4, OperandInfo165}, // Inst #688 = CDLFTR + {4, OperandInfo167}, // Inst #689 = CDLGBR + {4, OperandInfo167}, // Inst #690 = CDLGTR + {5, OperandInfo168}, // Inst #691 = CDPT + {2, OperandInfo93}, // Inst #692 = CDR + {5, OperandInfo169}, // Inst #693 = CDS + {5, OperandInfo169}, // Inst #694 = CDSG + {2, OperandInfo166}, // Inst #695 = CDSTR + {5, OperandInfo169}, // Inst #696 = CDSY + {2, OperandInfo93}, // Inst #697 = CDTR + {2, OperandInfo166}, // Inst #698 = CDUTR + {5, OperandInfo168}, // Inst #699 = CDZT + {4, OperandInfo170}, // Inst #700 = CE + {4, OperandInfo170}, // Inst #701 = CEB + {2, OperandInfo94}, // Inst #702 = CEBR + {2, OperandInfo93}, // Inst #703 = CEDTR + {2, OperandInfo171}, // Inst #704 = CEFBR + {4, OperandInfo172}, // Inst #705 = CEFBRA + {2, OperandInfo171}, // Inst #706 = CEFR + {2, OperandInfo173}, // Inst #707 = CEGBR + {4, OperandInfo174}, // Inst #708 = CEGBRA + {2, OperandInfo173}, // Inst #709 = CEGR + {4, OperandInfo172}, // Inst #710 = CELFBR + {4, OperandInfo174}, // Inst #711 = CELGBR + {2, OperandInfo94}, // Inst #712 = CER + {2, OperandInfo95}, // Inst #713 = CEXTR + {2, OperandInfo175}, // Inst #714 = CFC + {3, OperandInfo176}, // Inst #715 = CFDBR + {4, OperandInfo177}, // Inst #716 = CFDBRA + {3, OperandInfo176}, // Inst #717 = CFDR + {4, OperandInfo177}, // Inst #718 = CFDTR + {3, OperandInfo178}, // Inst #719 = CFEBR + {4, OperandInfo179}, // Inst #720 = CFEBRA + {3, OperandInfo178}, // Inst #721 = CFER + {2, OperandInfo180}, // Inst #722 = CFI + {3, OperandInfo181}, // Inst #723 = CFXBR + {4, OperandInfo182}, // Inst #724 = CFXBRA + {3, OperandInfo181}, // Inst #725 = CFXR + {4, OperandInfo182}, // Inst #726 = CFXTR + {4, OperandInfo45}, // Inst #727 = CG + {3, OperandInfo183}, // Inst #728 = CGDBR + {4, OperandInfo184}, // Inst #729 = CGDBRA + {3, OperandInfo183}, // Inst #730 = CGDR + {3, OperandInfo183}, // Inst #731 = CGDTR + {4, OperandInfo184}, // Inst #732 = CGDTRA + {3, OperandInfo185}, // Inst #733 = CGEBR + {4, OperandInfo186}, // Inst #734 = CGEBRA + {3, OperandInfo185}, // Inst #735 = CGER + {4, OperandInfo45}, // Inst #736 = CGF + {2, OperandInfo117}, // Inst #737 = CGFI + {2, OperandInfo187}, // Inst #738 = CGFR + {2, OperandInfo188}, // Inst #739 = CGFRL + {4, OperandInfo45}, // Inst #740 = CGH + {2, OperandInfo117}, // Inst #741 = CGHI + {2, OperandInfo188}, // Inst #742 = CGHRL + {3, OperandInfo116}, // Inst #743 = CGHSI + {5, OperandInfo189}, // Inst #744 = CGIB + {5, OperandInfo189}, // Inst #745 = CGIBAsm + {4, OperandInfo190}, // Inst #746 = CGIBAsmE + {4, OperandInfo190}, // Inst #747 = CGIBAsmH + {4, OperandInfo190}, // Inst #748 = CGIBAsmHE + {4, OperandInfo190}, // Inst #749 = CGIBAsmL + {4, OperandInfo190}, // Inst #750 = CGIBAsmLE + {4, OperandInfo190}, // Inst #751 = CGIBAsmLH + {4, OperandInfo190}, // Inst #752 = CGIBAsmNE + {4, OperandInfo190}, // Inst #753 = CGIBAsmNH + {4, OperandInfo190}, // Inst #754 = CGIBAsmNHE + {4, OperandInfo190}, // Inst #755 = CGIBAsmNL + {4, OperandInfo190}, // Inst #756 = CGIBAsmNLE + {4, OperandInfo190}, // Inst #757 = CGIBAsmNLH + {4, OperandInfo191}, // Inst #758 = CGIJ + {4, OperandInfo191}, // Inst #759 = CGIJAsm + {3, OperandInfo192}, // Inst #760 = CGIJAsmE + {3, OperandInfo192}, // Inst #761 = CGIJAsmH + {3, OperandInfo192}, // Inst #762 = CGIJAsmHE + {3, OperandInfo192}, // Inst #763 = CGIJAsmL + {3, OperandInfo192}, // Inst #764 = CGIJAsmLE + {3, OperandInfo192}, // Inst #765 = CGIJAsmLH + {3, OperandInfo192}, // Inst #766 = CGIJAsmNE + {3, OperandInfo192}, // Inst #767 = CGIJAsmNH + {3, OperandInfo192}, // Inst #768 = CGIJAsmNHE + {3, OperandInfo192}, // Inst #769 = CGIJAsmNL + {3, OperandInfo192}, // Inst #770 = CGIJAsmNLE + {3, OperandInfo192}, // Inst #771 = CGIJAsmNLH + {3, OperandInfo61}, // Inst #772 = CGIT + {3, OperandInfo61}, // Inst #773 = CGITAsm + {2, OperandInfo117}, // Inst #774 = CGITAsmE + {2, OperandInfo117}, // Inst #775 = CGITAsmH + {2, OperandInfo117}, // Inst #776 = CGITAsmHE + {2, OperandInfo117}, // Inst #777 = CGITAsmL + {2, OperandInfo117}, // Inst #778 = CGITAsmLE + {2, OperandInfo117}, // Inst #779 = CGITAsmLH + {2, OperandInfo117}, // Inst #780 = CGITAsmNE + {2, OperandInfo117}, // Inst #781 = CGITAsmNH + {2, OperandInfo117}, // Inst #782 = CGITAsmNHE + {2, OperandInfo117}, // Inst #783 = CGITAsmNL + {2, OperandInfo117}, // Inst #784 = CGITAsmNLE + {2, OperandInfo117}, // Inst #785 = CGITAsmNLH + {2, OperandInfo144}, // Inst #786 = CGR + {5, OperandInfo193}, // Inst #787 = CGRB + {5, OperandInfo193}, // Inst #788 = CGRBAsm + {4, OperandInfo194}, // Inst #789 = CGRBAsmE + {4, OperandInfo194}, // Inst #790 = CGRBAsmH + {4, OperandInfo194}, // Inst #791 = CGRBAsmHE + {4, OperandInfo194}, // Inst #792 = CGRBAsmL + {4, OperandInfo194}, // Inst #793 = CGRBAsmLE + {4, OperandInfo194}, // Inst #794 = CGRBAsmLH + {4, OperandInfo194}, // Inst #795 = CGRBAsmNE + {4, OperandInfo194}, // Inst #796 = CGRBAsmNH + {4, OperandInfo194}, // Inst #797 = CGRBAsmNHE + {4, OperandInfo194}, // Inst #798 = CGRBAsmNL + {4, OperandInfo194}, // Inst #799 = CGRBAsmNLE + {4, OperandInfo194}, // Inst #800 = CGRBAsmNLH + {4, OperandInfo195}, // Inst #801 = CGRJ + {4, OperandInfo195}, // Inst #802 = CGRJAsm + {3, OperandInfo196}, // Inst #803 = CGRJAsmE + {3, OperandInfo196}, // Inst #804 = CGRJAsmH + {3, OperandInfo196}, // Inst #805 = CGRJAsmHE + {3, OperandInfo196}, // Inst #806 = CGRJAsmL + {3, OperandInfo196}, // Inst #807 = CGRJAsmLE + {3, OperandInfo196}, // Inst #808 = CGRJAsmLH + {3, OperandInfo196}, // Inst #809 = CGRJAsmNE + {3, OperandInfo196}, // Inst #810 = CGRJAsmNH + {3, OperandInfo196}, // Inst #811 = CGRJAsmNHE + {3, OperandInfo196}, // Inst #812 = CGRJAsmNL + {3, OperandInfo196}, // Inst #813 = CGRJAsmNLE + {3, OperandInfo196}, // Inst #814 = CGRJAsmNLH + {2, OperandInfo188}, // Inst #815 = CGRL + {3, OperandInfo63}, // Inst #816 = CGRT + {3, OperandInfo63}, // Inst #817 = CGRTAsm + {2, OperandInfo144}, // Inst #818 = CGRTAsmE + {2, OperandInfo144}, // Inst #819 = CGRTAsmH + {2, OperandInfo144}, // Inst #820 = CGRTAsmHE + {2, OperandInfo144}, // Inst #821 = CGRTAsmL + {2, OperandInfo144}, // Inst #822 = CGRTAsmLE + {2, OperandInfo144}, // Inst #823 = CGRTAsmLH + {2, OperandInfo144}, // Inst #824 = CGRTAsmNE + {2, OperandInfo144}, // Inst #825 = CGRTAsmNH + {2, OperandInfo144}, // Inst #826 = CGRTAsmNHE + {2, OperandInfo144}, // Inst #827 = CGRTAsmNL + {2, OperandInfo144}, // Inst #828 = CGRTAsmNLE + {2, OperandInfo144}, // Inst #829 = CGRTAsmNLH + {3, OperandInfo197}, // Inst #830 = CGXBR + {4, OperandInfo198}, // Inst #831 = CGXBRA + {3, OperandInfo197}, // Inst #832 = CGXR + {3, OperandInfo197}, // Inst #833 = CGXTR + {4, OperandInfo198}, // Inst #834 = CGXTRA + {4, OperandInfo162}, // Inst #835 = CH + {4, OperandInfo199}, // Inst #836 = CHF + {2, OperandInfo200}, // Inst #837 = CHHR + {3, OperandInfo116}, // Inst #838 = CHHSI + {2, OperandInfo180}, // Inst #839 = CHI + {2, OperandInfo201}, // Inst #840 = CHLR + {2, OperandInfo202}, // Inst #841 = CHRL + {3, OperandInfo116}, // Inst #842 = CHSI + {4, OperandInfo162}, // Inst #843 = CHY + {5, OperandInfo203}, // Inst #844 = CIB + {5, OperandInfo203}, // Inst #845 = CIBAsm + {4, OperandInfo204}, // Inst #846 = CIBAsmE + {4, OperandInfo204}, // Inst #847 = CIBAsmH + {4, OperandInfo204}, // Inst #848 = CIBAsmHE + {4, OperandInfo204}, // Inst #849 = CIBAsmL + {4, OperandInfo204}, // Inst #850 = CIBAsmLE + {4, OperandInfo204}, // Inst #851 = CIBAsmLH + {4, OperandInfo204}, // Inst #852 = CIBAsmNE + {4, OperandInfo204}, // Inst #853 = CIBAsmNH + {4, OperandInfo204}, // Inst #854 = CIBAsmNHE + {4, OperandInfo204}, // Inst #855 = CIBAsmNL + {4, OperandInfo204}, // Inst #856 = CIBAsmNLE + {4, OperandInfo204}, // Inst #857 = CIBAsmNLH + {2, OperandInfo205}, // Inst #858 = CIH + {4, OperandInfo206}, // Inst #859 = CIJ + {4, OperandInfo206}, // Inst #860 = CIJAsm + {3, OperandInfo207}, // Inst #861 = CIJAsmE + {3, OperandInfo207}, // Inst #862 = CIJAsmH + {3, OperandInfo207}, // Inst #863 = CIJAsmHE + {3, OperandInfo207}, // Inst #864 = CIJAsmL + {3, OperandInfo207}, // Inst #865 = CIJAsmLE + {3, OperandInfo207}, // Inst #866 = CIJAsmLH + {3, OperandInfo207}, // Inst #867 = CIJAsmNE + {3, OperandInfo207}, // Inst #868 = CIJAsmNH + {3, OperandInfo207}, // Inst #869 = CIJAsmNHE + {3, OperandInfo207}, // Inst #870 = CIJAsmNL + {3, OperandInfo207}, // Inst #871 = CIJAsmNLE + {3, OperandInfo207}, // Inst #872 = CIJAsmNLH + {3, OperandInfo65}, // Inst #873 = CIT + {3, OperandInfo65}, // Inst #874 = CITAsm + {2, OperandInfo180}, // Inst #875 = CITAsmE + {2, OperandInfo180}, // Inst #876 = CITAsmH + {2, OperandInfo180}, // Inst #877 = CITAsmHE + {2, OperandInfo180}, // Inst #878 = CITAsmL + {2, OperandInfo180}, // Inst #879 = CITAsmLE + {2, OperandInfo180}, // Inst #880 = CITAsmLH + {2, OperandInfo180}, // Inst #881 = CITAsmNE + {2, OperandInfo180}, // Inst #882 = CITAsmNH + {2, OperandInfo180}, // Inst #883 = CITAsmNHE + {2, OperandInfo180}, // Inst #884 = CITAsmNL + {2, OperandInfo180}, // Inst #885 = CITAsmNLE + {2, OperandInfo180}, // Inst #886 = CITAsmNLH + {4, OperandInfo208}, // Inst #887 = CKSM + {4, OperandInfo162}, // Inst #888 = CL + {5, OperandInfo209}, // Inst #889 = CLC + {4, OperandInfo210}, // Inst #890 = CLCL + {6, OperandInfo211}, // Inst #891 = CLCLE + {6, OperandInfo211}, // Inst #892 = CLCLU + {4, OperandInfo177}, // Inst #893 = CLFDBR + {4, OperandInfo177}, // Inst #894 = CLFDTR + {4, OperandInfo179}, // Inst #895 = CLFEBR + {3, OperandInfo116}, // Inst #896 = CLFHSI + {2, OperandInfo180}, // Inst #897 = CLFI + {3, OperandInfo65}, // Inst #898 = CLFIT + {3, OperandInfo65}, // Inst #899 = CLFITAsm + {2, OperandInfo180}, // Inst #900 = CLFITAsmE + {2, OperandInfo180}, // Inst #901 = CLFITAsmH + {2, OperandInfo180}, // Inst #902 = CLFITAsmHE + {2, OperandInfo180}, // Inst #903 = CLFITAsmL + {2, OperandInfo180}, // Inst #904 = CLFITAsmLE + {2, OperandInfo180}, // Inst #905 = CLFITAsmLH + {2, OperandInfo180}, // Inst #906 = CLFITAsmNE + {2, OperandInfo180}, // Inst #907 = CLFITAsmNH + {2, OperandInfo180}, // Inst #908 = CLFITAsmNHE + {2, OperandInfo180}, // Inst #909 = CLFITAsmNL + {2, OperandInfo180}, // Inst #910 = CLFITAsmNLE + {2, OperandInfo180}, // Inst #911 = CLFITAsmNLH + {4, OperandInfo182}, // Inst #912 = CLFXBR + {4, OperandInfo182}, // Inst #913 = CLFXTR + {4, OperandInfo45}, // Inst #914 = CLG + {4, OperandInfo184}, // Inst #915 = CLGDBR + {4, OperandInfo184}, // Inst #916 = CLGDTR + {4, OperandInfo186}, // Inst #917 = CLGEBR + {4, OperandInfo45}, // Inst #918 = CLGF + {2, OperandInfo117}, // Inst #919 = CLGFI + {2, OperandInfo187}, // Inst #920 = CLGFR + {2, OperandInfo188}, // Inst #921 = CLGFRL + {2, OperandInfo188}, // Inst #922 = CLGHRL + {3, OperandInfo116}, // Inst #923 = CLGHSI + {5, OperandInfo189}, // Inst #924 = CLGIB + {5, OperandInfo189}, // Inst #925 = CLGIBAsm + {4, OperandInfo190}, // Inst #926 = CLGIBAsmE + {4, OperandInfo190}, // Inst #927 = CLGIBAsmH + {4, OperandInfo190}, // Inst #928 = CLGIBAsmHE + {4, OperandInfo190}, // Inst #929 = CLGIBAsmL + {4, OperandInfo190}, // Inst #930 = CLGIBAsmLE + {4, OperandInfo190}, // Inst #931 = CLGIBAsmLH + {4, OperandInfo190}, // Inst #932 = CLGIBAsmNE + {4, OperandInfo190}, // Inst #933 = CLGIBAsmNH + {4, OperandInfo190}, // Inst #934 = CLGIBAsmNHE + {4, OperandInfo190}, // Inst #935 = CLGIBAsmNL + {4, OperandInfo190}, // Inst #936 = CLGIBAsmNLE + {4, OperandInfo190}, // Inst #937 = CLGIBAsmNLH + {4, OperandInfo191}, // Inst #938 = CLGIJ + {4, OperandInfo191}, // Inst #939 = CLGIJAsm + {3, OperandInfo192}, // Inst #940 = CLGIJAsmE + {3, OperandInfo192}, // Inst #941 = CLGIJAsmH + {3, OperandInfo192}, // Inst #942 = CLGIJAsmHE + {3, OperandInfo192}, // Inst #943 = CLGIJAsmL + {3, OperandInfo192}, // Inst #944 = CLGIJAsmLE + {3, OperandInfo192}, // Inst #945 = CLGIJAsmLH + {3, OperandInfo192}, // Inst #946 = CLGIJAsmNE + {3, OperandInfo192}, // Inst #947 = CLGIJAsmNH + {3, OperandInfo192}, // Inst #948 = CLGIJAsmNHE + {3, OperandInfo192}, // Inst #949 = CLGIJAsmNL + {3, OperandInfo192}, // Inst #950 = CLGIJAsmNLE + {3, OperandInfo192}, // Inst #951 = CLGIJAsmNLH + {3, OperandInfo61}, // Inst #952 = CLGIT + {3, OperandInfo61}, // Inst #953 = CLGITAsm + {2, OperandInfo117}, // Inst #954 = CLGITAsmE + {2, OperandInfo117}, // Inst #955 = CLGITAsmH + {2, OperandInfo117}, // Inst #956 = CLGITAsmHE + {2, OperandInfo117}, // Inst #957 = CLGITAsmL + {2, OperandInfo117}, // Inst #958 = CLGITAsmLE + {2, OperandInfo117}, // Inst #959 = CLGITAsmLH + {2, OperandInfo117}, // Inst #960 = CLGITAsmNE + {2, OperandInfo117}, // Inst #961 = CLGITAsmNH + {2, OperandInfo117}, // Inst #962 = CLGITAsmNHE + {2, OperandInfo117}, // Inst #963 = CLGITAsmNL + {2, OperandInfo117}, // Inst #964 = CLGITAsmNLE + {2, OperandInfo117}, // Inst #965 = CLGITAsmNLH + {2, OperandInfo144}, // Inst #966 = CLGR + {5, OperandInfo193}, // Inst #967 = CLGRB + {5, OperandInfo193}, // Inst #968 = CLGRBAsm + {4, OperandInfo194}, // Inst #969 = CLGRBAsmE + {4, OperandInfo194}, // Inst #970 = CLGRBAsmH + {4, OperandInfo194}, // Inst #971 = CLGRBAsmHE + {4, OperandInfo194}, // Inst #972 = CLGRBAsmL + {4, OperandInfo194}, // Inst #973 = CLGRBAsmLE + {4, OperandInfo194}, // Inst #974 = CLGRBAsmLH + {4, OperandInfo194}, // Inst #975 = CLGRBAsmNE + {4, OperandInfo194}, // Inst #976 = CLGRBAsmNH + {4, OperandInfo194}, // Inst #977 = CLGRBAsmNHE + {4, OperandInfo194}, // Inst #978 = CLGRBAsmNL + {4, OperandInfo194}, // Inst #979 = CLGRBAsmNLE + {4, OperandInfo194}, // Inst #980 = CLGRBAsmNLH + {4, OperandInfo195}, // Inst #981 = CLGRJ + {4, OperandInfo195}, // Inst #982 = CLGRJAsm + {3, OperandInfo196}, // Inst #983 = CLGRJAsmE + {3, OperandInfo196}, // Inst #984 = CLGRJAsmH + {3, OperandInfo196}, // Inst #985 = CLGRJAsmHE + {3, OperandInfo196}, // Inst #986 = CLGRJAsmL + {3, OperandInfo196}, // Inst #987 = CLGRJAsmLE + {3, OperandInfo196}, // Inst #988 = CLGRJAsmLH + {3, OperandInfo196}, // Inst #989 = CLGRJAsmNE + {3, OperandInfo196}, // Inst #990 = CLGRJAsmNH + {3, OperandInfo196}, // Inst #991 = CLGRJAsmNHE + {3, OperandInfo196}, // Inst #992 = CLGRJAsmNL + {3, OperandInfo196}, // Inst #993 = CLGRJAsmNLE + {3, OperandInfo196}, // Inst #994 = CLGRJAsmNLH + {2, OperandInfo188}, // Inst #995 = CLGRL + {3, OperandInfo63}, // Inst #996 = CLGRT + {3, OperandInfo63}, // Inst #997 = CLGRTAsm + {2, OperandInfo144}, // Inst #998 = CLGRTAsmE + {2, OperandInfo144}, // Inst #999 = CLGRTAsmH + {2, OperandInfo144}, // Inst #1000 = CLGRTAsmHE + {2, OperandInfo144}, // Inst #1001 = CLGRTAsmL + {2, OperandInfo144}, // Inst #1002 = CLGRTAsmLE + {2, OperandInfo144}, // Inst #1003 = CLGRTAsmLH + {2, OperandInfo144}, // Inst #1004 = CLGRTAsmNE + {2, OperandInfo144}, // Inst #1005 = CLGRTAsmNH + {2, OperandInfo144}, // Inst #1006 = CLGRTAsmNHE + {2, OperandInfo144}, // Inst #1007 = CLGRTAsmNL + {2, OperandInfo144}, // Inst #1008 = CLGRTAsmNLE + {2, OperandInfo144}, // Inst #1009 = CLGRTAsmNLH + {4, OperandInfo56}, // Inst #1010 = CLGT + {4, OperandInfo56}, // Inst #1011 = CLGTAsm + {3, OperandInfo212}, // Inst #1012 = CLGTAsmE + {3, OperandInfo212}, // Inst #1013 = CLGTAsmH + {3, OperandInfo212}, // Inst #1014 = CLGTAsmHE + {3, OperandInfo212}, // Inst #1015 = CLGTAsmL + {3, OperandInfo212}, // Inst #1016 = CLGTAsmLE + {3, OperandInfo212}, // Inst #1017 = CLGTAsmLH + {3, OperandInfo212}, // Inst #1018 = CLGTAsmNE + {3, OperandInfo212}, // Inst #1019 = CLGTAsmNH + {3, OperandInfo212}, // Inst #1020 = CLGTAsmNHE + {3, OperandInfo212}, // Inst #1021 = CLGTAsmNL + {3, OperandInfo212}, // Inst #1022 = CLGTAsmNLE + {3, OperandInfo212}, // Inst #1023 = CLGTAsmNLH + {4, OperandInfo198}, // Inst #1024 = CLGXBR + {4, OperandInfo198}, // Inst #1025 = CLGXTR + {4, OperandInfo199}, // Inst #1026 = CLHF + {2, OperandInfo200}, // Inst #1027 = CLHHR + {3, OperandInfo116}, // Inst #1028 = CLHHSI + {2, OperandInfo201}, // Inst #1029 = CLHLR + {2, OperandInfo202}, // Inst #1030 = CLHRL + {3, OperandInfo116}, // Inst #1031 = CLI + {5, OperandInfo203}, // Inst #1032 = CLIB + {5, OperandInfo203}, // Inst #1033 = CLIBAsm + {4, OperandInfo204}, // Inst #1034 = CLIBAsmE + {4, OperandInfo204}, // Inst #1035 = CLIBAsmH + {4, OperandInfo204}, // Inst #1036 = CLIBAsmHE + {4, OperandInfo204}, // Inst #1037 = CLIBAsmL + {4, OperandInfo204}, // Inst #1038 = CLIBAsmLE + {4, OperandInfo204}, // Inst #1039 = CLIBAsmLH + {4, OperandInfo204}, // Inst #1040 = CLIBAsmNE + {4, OperandInfo204}, // Inst #1041 = CLIBAsmNH + {4, OperandInfo204}, // Inst #1042 = CLIBAsmNHE + {4, OperandInfo204}, // Inst #1043 = CLIBAsmNL + {4, OperandInfo204}, // Inst #1044 = CLIBAsmNLE + {4, OperandInfo204}, // Inst #1045 = CLIBAsmNLH + {2, OperandInfo205}, // Inst #1046 = CLIH + {4, OperandInfo206}, // Inst #1047 = CLIJ + {4, OperandInfo206}, // Inst #1048 = CLIJAsm + {3, OperandInfo207}, // Inst #1049 = CLIJAsmE + {3, OperandInfo207}, // Inst #1050 = CLIJAsmH + {3, OperandInfo207}, // Inst #1051 = CLIJAsmHE + {3, OperandInfo207}, // Inst #1052 = CLIJAsmL + {3, OperandInfo207}, // Inst #1053 = CLIJAsmLE + {3, OperandInfo207}, // Inst #1054 = CLIJAsmLH + {3, OperandInfo207}, // Inst #1055 = CLIJAsmNE + {3, OperandInfo207}, // Inst #1056 = CLIJAsmNH + {3, OperandInfo207}, // Inst #1057 = CLIJAsmNHE + {3, OperandInfo207}, // Inst #1058 = CLIJAsmNL + {3, OperandInfo207}, // Inst #1059 = CLIJAsmNLE + {3, OperandInfo207}, // Inst #1060 = CLIJAsmNLH + {3, OperandInfo116}, // Inst #1061 = CLIY + {4, OperandInfo204}, // Inst #1062 = CLM + {4, OperandInfo213}, // Inst #1063 = CLMH + {4, OperandInfo204}, // Inst #1064 = CLMY + {2, OperandInfo214}, // Inst #1065 = CLR + {5, OperandInfo215}, // Inst #1066 = CLRB + {5, OperandInfo215}, // Inst #1067 = CLRBAsm + {4, OperandInfo216}, // Inst #1068 = CLRBAsmE + {4, OperandInfo216}, // Inst #1069 = CLRBAsmH + {4, OperandInfo216}, // Inst #1070 = CLRBAsmHE + {4, OperandInfo216}, // Inst #1071 = CLRBAsmL + {4, OperandInfo216}, // Inst #1072 = CLRBAsmLE + {4, OperandInfo216}, // Inst #1073 = CLRBAsmLH + {4, OperandInfo216}, // Inst #1074 = CLRBAsmNE + {4, OperandInfo216}, // Inst #1075 = CLRBAsmNH + {4, OperandInfo216}, // Inst #1076 = CLRBAsmNHE + {4, OperandInfo216}, // Inst #1077 = CLRBAsmNL + {4, OperandInfo216}, // Inst #1078 = CLRBAsmNLE + {4, OperandInfo216}, // Inst #1079 = CLRBAsmNLH + {4, OperandInfo217}, // Inst #1080 = CLRJ + {4, OperandInfo217}, // Inst #1081 = CLRJAsm + {3, OperandInfo218}, // Inst #1082 = CLRJAsmE + {3, OperandInfo218}, // Inst #1083 = CLRJAsmH + {3, OperandInfo218}, // Inst #1084 = CLRJAsmHE + {3, OperandInfo218}, // Inst #1085 = CLRJAsmL + {3, OperandInfo218}, // Inst #1086 = CLRJAsmLE + {3, OperandInfo218}, // Inst #1087 = CLRJAsmLH + {3, OperandInfo218}, // Inst #1088 = CLRJAsmNE + {3, OperandInfo218}, // Inst #1089 = CLRJAsmNH + {3, OperandInfo218}, // Inst #1090 = CLRJAsmNHE + {3, OperandInfo218}, // Inst #1091 = CLRJAsmNL + {3, OperandInfo218}, // Inst #1092 = CLRJAsmNLE + {3, OperandInfo218}, // Inst #1093 = CLRJAsmNLH + {2, OperandInfo202}, // Inst #1094 = CLRL + {3, OperandInfo70}, // Inst #1095 = CLRT + {3, OperandInfo70}, // Inst #1096 = CLRTAsm + {2, OperandInfo214}, // Inst #1097 = CLRTAsmE + {2, OperandInfo214}, // Inst #1098 = CLRTAsmH + {2, OperandInfo214}, // Inst #1099 = CLRTAsmHE + {2, OperandInfo214}, // Inst #1100 = CLRTAsmL + {2, OperandInfo214}, // Inst #1101 = CLRTAsmLE + {2, OperandInfo214}, // Inst #1102 = CLRTAsmLH + {2, OperandInfo214}, // Inst #1103 = CLRTAsmNE + {2, OperandInfo214}, // Inst #1104 = CLRTAsmNH + {2, OperandInfo214}, // Inst #1105 = CLRTAsmNHE + {2, OperandInfo214}, // Inst #1106 = CLRTAsmNL + {2, OperandInfo214}, // Inst #1107 = CLRTAsmNLE + {2, OperandInfo214}, // Inst #1108 = CLRTAsmNLH + {4, OperandInfo219}, // Inst #1109 = CLST + {4, OperandInfo55}, // Inst #1110 = CLT + {4, OperandInfo55}, // Inst #1111 = CLTAsm + {3, OperandInfo220}, // Inst #1112 = CLTAsmE + {3, OperandInfo220}, // Inst #1113 = CLTAsmH + {3, OperandInfo220}, // Inst #1114 = CLTAsmHE + {3, OperandInfo220}, // Inst #1115 = CLTAsmL + {3, OperandInfo220}, // Inst #1116 = CLTAsmLE + {3, OperandInfo220}, // Inst #1117 = CLTAsmLH + {3, OperandInfo220}, // Inst #1118 = CLTAsmNE + {3, OperandInfo220}, // Inst #1119 = CLTAsmNH + {3, OperandInfo220}, // Inst #1120 = CLTAsmNHE + {3, OperandInfo220}, // Inst #1121 = CLTAsmNL + {3, OperandInfo220}, // Inst #1122 = CLTAsmNLE + {3, OperandInfo220}, // Inst #1123 = CLTAsmNLH + {4, OperandInfo162}, // Inst #1124 = CLY + {4, OperandInfo210}, // Inst #1125 = CMPSC + {6, OperandInfo139}, // Inst #1126 = CP + {5, OperandInfo168}, // Inst #1127 = CPDT + {3, OperandInfo126}, // Inst #1128 = CPSDRdd + {3, OperandInfo221}, // Inst #1129 = CPSDRds + {3, OperandInfo222}, // Inst #1130 = CPSDRsd + {3, OperandInfo223}, // Inst #1131 = CPSDRss + {5, OperandInfo224}, // Inst #1132 = CPXT + {2, OperandInfo225}, // Inst #1133 = CPYA + {2, OperandInfo214}, // Inst #1134 = CR + {5, OperandInfo215}, // Inst #1135 = CRB + {5, OperandInfo215}, // Inst #1136 = CRBAsm + {4, OperandInfo216}, // Inst #1137 = CRBAsmE + {4, OperandInfo216}, // Inst #1138 = CRBAsmH + {4, OperandInfo216}, // Inst #1139 = CRBAsmHE + {4, OperandInfo216}, // Inst #1140 = CRBAsmL + {4, OperandInfo216}, // Inst #1141 = CRBAsmLE + {4, OperandInfo216}, // Inst #1142 = CRBAsmLH + {4, OperandInfo216}, // Inst #1143 = CRBAsmNE + {4, OperandInfo216}, // Inst #1144 = CRBAsmNH + {4, OperandInfo216}, // Inst #1145 = CRBAsmNHE + {4, OperandInfo216}, // Inst #1146 = CRBAsmNL + {4, OperandInfo216}, // Inst #1147 = CRBAsmNLE + {4, OperandInfo216}, // Inst #1148 = CRBAsmNLH + {4, OperandInfo226}, // Inst #1149 = CRDTE + {3, OperandInfo227}, // Inst #1150 = CRDTEOpt + {4, OperandInfo217}, // Inst #1151 = CRJ + {4, OperandInfo217}, // Inst #1152 = CRJAsm + {3, OperandInfo218}, // Inst #1153 = CRJAsmE + {3, OperandInfo218}, // Inst #1154 = CRJAsmH + {3, OperandInfo218}, // Inst #1155 = CRJAsmHE + {3, OperandInfo218}, // Inst #1156 = CRJAsmL + {3, OperandInfo218}, // Inst #1157 = CRJAsmLE + {3, OperandInfo218}, // Inst #1158 = CRJAsmLH + {3, OperandInfo218}, // Inst #1159 = CRJAsmNE + {3, OperandInfo218}, // Inst #1160 = CRJAsmNH + {3, OperandInfo218}, // Inst #1161 = CRJAsmNHE + {3, OperandInfo218}, // Inst #1162 = CRJAsmNL + {3, OperandInfo218}, // Inst #1163 = CRJAsmNLE + {3, OperandInfo218}, // Inst #1164 = CRJAsmNLH + {2, OperandInfo202}, // Inst #1165 = CRL + {3, OperandInfo70}, // Inst #1166 = CRT + {3, OperandInfo70}, // Inst #1167 = CRTAsm + {2, OperandInfo214}, // Inst #1168 = CRTAsmE + {2, OperandInfo214}, // Inst #1169 = CRTAsmH + {2, OperandInfo214}, // Inst #1170 = CRTAsmHE + {2, OperandInfo214}, // Inst #1171 = CRTAsmL + {2, OperandInfo214}, // Inst #1172 = CRTAsmLE + {2, OperandInfo214}, // Inst #1173 = CRTAsmLH + {2, OperandInfo214}, // Inst #1174 = CRTAsmNE + {2, OperandInfo214}, // Inst #1175 = CRTAsmNH + {2, OperandInfo214}, // Inst #1176 = CRTAsmNHE + {2, OperandInfo214}, // Inst #1177 = CRTAsmNL + {2, OperandInfo214}, // Inst #1178 = CRTAsmNLE + {2, OperandInfo214}, // Inst #1179 = CRTAsmNLH + {5, OperandInfo160}, // Inst #1180 = CS + {0, NULL}, // Inst #1181 = CSCH + {3, OperandInfo228}, // Inst #1182 = CSDTR + {5, OperandInfo161}, // Inst #1183 = CSG + {3, OperandInfo229}, // Inst #1184 = CSP + {3, OperandInfo229}, // Inst #1185 = CSPG + {5, OperandInfo230}, // Inst #1186 = CSST + {3, OperandInfo231}, // Inst #1187 = CSXTR + {5, OperandInfo160}, // Inst #1188 = CSY + {5, OperandInfo232}, // Inst #1189 = CU12 + {4, OperandInfo210}, // Inst #1190 = CU12Opt + {5, OperandInfo232}, // Inst #1191 = CU14 + {4, OperandInfo210}, // Inst #1192 = CU14Opt + {5, OperandInfo232}, // Inst #1193 = CU21 + {4, OperandInfo210}, // Inst #1194 = CU21Opt + {5, OperandInfo232}, // Inst #1195 = CU24 + {4, OperandInfo210}, // Inst #1196 = CU24Opt + {4, OperandInfo210}, // Inst #1197 = CU41 + {4, OperandInfo210}, // Inst #1198 = CU42 + {2, OperandInfo233}, // Inst #1199 = CUDTR + {4, OperandInfo210}, // Inst #1200 = CUSE + {5, OperandInfo232}, // Inst #1201 = CUTFU + {4, OperandInfo210}, // Inst #1202 = CUTFUOpt + {5, OperandInfo232}, // Inst #1203 = CUUTF + {4, OperandInfo210}, // Inst #1204 = CUUTFOpt + {2, OperandInfo234}, // Inst #1205 = CUXTR + {5, OperandInfo123}, // Inst #1206 = CVB + {5, OperandInfo131}, // Inst #1207 = CVBG + {5, OperandInfo123}, // Inst #1208 = CVBY + {4, OperandInfo162}, // Inst #1209 = CVD + {4, OperandInfo45}, // Inst #1210 = CVDG + {4, OperandInfo162}, // Inst #1211 = CVDY + {2, OperandInfo95}, // Inst #1212 = CXBR + {2, OperandInfo235}, // Inst #1213 = CXFBR + {4, OperandInfo236}, // Inst #1214 = CXFBRA + {2, OperandInfo235}, // Inst #1215 = CXFR + {4, OperandInfo236}, // Inst #1216 = CXFTR + {2, OperandInfo237}, // Inst #1217 = CXGBR + {4, OperandInfo238}, // Inst #1218 = CXGBRA + {2, OperandInfo237}, // Inst #1219 = CXGR + {2, OperandInfo237}, // Inst #1220 = CXGTR + {4, OperandInfo238}, // Inst #1221 = CXGTRA + {4, OperandInfo236}, // Inst #1222 = CXLFBR + {4, OperandInfo236}, // Inst #1223 = CXLFTR + {4, OperandInfo238}, // Inst #1224 = CXLGBR + {4, OperandInfo238}, // Inst #1225 = CXLGTR + {5, OperandInfo224}, // Inst #1226 = CXPT + {2, OperandInfo95}, // Inst #1227 = CXR + {2, OperandInfo239}, // Inst #1228 = CXSTR + {2, OperandInfo95}, // Inst #1229 = CXTR + {2, OperandInfo239}, // Inst #1230 = CXUTR + {5, OperandInfo224}, // Inst #1231 = CXZT + {4, OperandInfo162}, // Inst #1232 = CY + {5, OperandInfo168}, // Inst #1233 = CZDT + {5, OperandInfo224}, // Inst #1234 = CZXT + {5, OperandInfo240}, // Inst #1235 = D + {5, OperandInfo124}, // Inst #1236 = DD + {5, OperandInfo124}, // Inst #1237 = DDB + {3, OperandInfo125}, // Inst #1238 = DDBR + {3, OperandInfo125}, // Inst #1239 = DDR + {3, OperandInfo126}, // Inst #1240 = DDTR + {4, OperandInfo127}, // Inst #1241 = DDTRA + {5, OperandInfo128}, // Inst #1242 = DE + {5, OperandInfo128}, // Inst #1243 = DEB + {3, OperandInfo129}, // Inst #1244 = DEBR + {3, OperandInfo129}, // Inst #1245 = DER + {5, OperandInfo241}, // Inst #1246 = DFLTCC + {4, OperandInfo216}, // Inst #1247 = DIAG + {5, OperandInfo242}, // Inst #1248 = DIDBR + {5, OperandInfo243}, // Inst #1249 = DIEBR + {5, OperandInfo240}, // Inst #1250 = DL + {5, OperandInfo240}, // Inst #1251 = DLG + {3, OperandInfo229}, // Inst #1252 = DLGR + {3, OperandInfo244}, // Inst #1253 = DLR + {6, OperandInfo139}, // Inst #1254 = DP + {3, OperandInfo244}, // Inst #1255 = DR + {5, OperandInfo240}, // Inst #1256 = DSG + {5, OperandInfo240}, // Inst #1257 = DSGF + {3, OperandInfo244}, // Inst #1258 = DSGFR + {3, OperandInfo229}, // Inst #1259 = DSGR + {3, OperandInfo140}, // Inst #1260 = DXBR + {3, OperandInfo140}, // Inst #1261 = DXR + {3, OperandInfo141}, // Inst #1262 = DXTR + {4, OperandInfo142}, // Inst #1263 = DXTRA + {2, OperandInfo245}, // Inst #1264 = EAR + {4, OperandInfo246}, // Inst #1265 = ECAG + {2, OperandInfo144}, // Inst #1266 = ECCTR + {2, OperandInfo247}, // Inst #1267 = ECPGA + {5, OperandInfo230}, // Inst #1268 = ECTG + {5, OperandInfo209}, // Inst #1269 = ED + {5, OperandInfo209}, // Inst #1270 = EDMK + {2, OperandInfo93}, // Inst #1271 = EEDTR + {2, OperandInfo95}, // Inst #1272 = EEXTR + {1, OperandInfo248}, // Inst #1273 = EFPC + {1, OperandInfo82}, // Inst #1274 = EPAIR + {1, OperandInfo248}, // Inst #1275 = EPAR + {2, OperandInfo144}, // Inst #1276 = EPCTR + {2, OperandInfo214}, // Inst #1277 = EPSW + {2, OperandInfo214}, // Inst #1278 = EREG + {2, OperandInfo144}, // Inst #1279 = EREGG + {1, OperandInfo82}, // Inst #1280 = ESAIR + {1, OperandInfo248}, // Inst #1281 = ESAR + {2, OperandInfo93}, // Inst #1282 = ESDTR + {2, OperandInfo249}, // Inst #1283 = ESEA + {2, OperandInfo250}, // Inst #1284 = ESTA + {2, OperandInfo95}, // Inst #1285 = ESXTR + {1, OperandInfo248}, // Inst #1286 = ETND + {4, OperandInfo251}, // Inst #1287 = EX + {2, OperandInfo252}, // Inst #1288 = EXRL + {3, OperandInfo253}, // Inst #1289 = FIDBR + {4, OperandInfo254}, // Inst #1290 = FIDBRA + {2, OperandInfo93}, // Inst #1291 = FIDR + {4, OperandInfo254}, // Inst #1292 = FIDTR + {3, OperandInfo255}, // Inst #1293 = FIEBR + {4, OperandInfo256}, // Inst #1294 = FIEBRA + {2, OperandInfo94}, // Inst #1295 = FIER + {3, OperandInfo257}, // Inst #1296 = FIXBR + {4, OperandInfo258}, // Inst #1297 = FIXBRA + {2, OperandInfo95}, // Inst #1298 = FIXR + {4, OperandInfo258}, // Inst #1299 = FIXTR + {2, OperandInfo47}, // Inst #1300 = FLOGR + {2, OperandInfo93}, // Inst #1301 = HDR + {2, OperandInfo94}, // Inst #1302 = HER + {0, NULL}, // Inst #1303 = HSCH + {1, OperandInfo248}, // Inst #1304 = IAC + {5, OperandInfo131}, // Inst #1305 = IC + {5, OperandInfo123}, // Inst #1306 = IC32 + {5, OperandInfo123}, // Inst #1307 = IC32Y + {5, OperandInfo259}, // Inst #1308 = ICM + {5, OperandInfo260}, // Inst #1309 = ICMH + {5, OperandInfo259}, // Inst #1310 = ICMY + {5, OperandInfo131}, // Inst #1311 = ICY + {4, OperandInfo261}, // Inst #1312 = IDTE + {3, OperandInfo100}, // Inst #1313 = IDTEOpt + {3, OperandInfo126}, // Inst #1314 = IEDTR + {3, OperandInfo141}, // Inst #1315 = IEXTR + {2, OperandInfo205}, // Inst #1316 = IIHF + {3, OperandInfo136}, // Inst #1317 = IIHH + {3, OperandInfo136}, // Inst #1318 = IIHL + {2, OperandInfo180}, // Inst #1319 = IILF + {3, OperandInfo130}, // Inst #1320 = IILH + {3, OperandInfo130}, // Inst #1321 = IILL + {0, NULL}, // Inst #1322 = IPK + {1, OperandInfo248}, // Inst #1323 = IPM + {4, OperandInfo262}, // Inst #1324 = IPTE + {3, OperandInfo263}, // Inst #1325 = IPTEOpt + {2, OperandInfo187}, // Inst #1326 = IPTEOptOpt + {2, OperandInfo144}, // Inst #1327 = IRBM + {3, OperandInfo150}, // Inst #1328 = ISKE + {3, OperandInfo150}, // Inst #1329 = IVSK + {1, OperandInfo3}, // Inst #1330 = InsnE + {3, OperandInfo264}, // Inst #1331 = InsnRI + {4, OperandInfo265}, // Inst #1332 = InsnRIE + {3, OperandInfo266}, // Inst #1333 = InsnRIL + {3, OperandInfo264}, // Inst #1334 = InsnRILU + {6, OperandInfo267}, // Inst #1335 = InsnRIS + {3, OperandInfo268}, // Inst #1336 = InsnRR + {3, OperandInfo268}, // Inst #1337 = InsnRRE + {5, OperandInfo269}, // Inst #1338 = InsnRRF + {6, OperandInfo270}, // Inst #1339 = InsnRRS + {5, OperandInfo271}, // Inst #1340 = InsnRS + {5, OperandInfo271}, // Inst #1341 = InsnRSE + {4, OperandInfo265}, // Inst #1342 = InsnRSI + {5, OperandInfo271}, // Inst #1343 = InsnRSY + {5, OperandInfo272}, // Inst #1344 = InsnRX + {5, OperandInfo272}, // Inst #1345 = InsnRXE + {6, OperandInfo273}, // Inst #1346 = InsnRXF + {5, OperandInfo272}, // Inst #1347 = InsnRXY + {3, OperandInfo274}, // Inst #1348 = InsnS + {4, OperandInfo275}, // Inst #1349 = InsnSI + {4, OperandInfo275}, // Inst #1350 = InsnSIL + {4, OperandInfo275}, // Inst #1351 = InsnSIY + {7, OperandInfo276}, // Inst #1352 = InsnSS + {5, OperandInfo277}, // Inst #1353 = InsnSSE + {6, OperandInfo278}, // Inst #1354 = InsnSSF + {6, OperandInfo279}, // Inst #1355 = InsnVRI + {7, OperandInfo280}, // Inst #1356 = InsnVRR + {6, OperandInfo281}, // Inst #1357 = InsnVRS + {6, OperandInfo282}, // Inst #1358 = InsnVRV + {6, OperandInfo283}, // Inst #1359 = InsnVRX + {5, OperandInfo284}, // Inst #1360 = InsnVSI + {1, OperandInfo74}, // Inst #1361 = J + {1, OperandInfo74}, // Inst #1362 = JAsmE + {1, OperandInfo74}, // Inst #1363 = JAsmH + {1, OperandInfo74}, // Inst #1364 = JAsmHE + {1, OperandInfo74}, // Inst #1365 = JAsmL + {1, OperandInfo74}, // Inst #1366 = JAsmLE + {1, OperandInfo74}, // Inst #1367 = JAsmLH + {1, OperandInfo74}, // Inst #1368 = JAsmM + {1, OperandInfo74}, // Inst #1369 = JAsmNE + {1, OperandInfo74}, // Inst #1370 = JAsmNH + {1, OperandInfo74}, // Inst #1371 = JAsmNHE + {1, OperandInfo74}, // Inst #1372 = JAsmNL + {1, OperandInfo74}, // Inst #1373 = JAsmNLE + {1, OperandInfo74}, // Inst #1374 = JAsmNLH + {1, OperandInfo74}, // Inst #1375 = JAsmNM + {1, OperandInfo74}, // Inst #1376 = JAsmNO + {1, OperandInfo74}, // Inst #1377 = JAsmNP + {1, OperandInfo74}, // Inst #1378 = JAsmNZ + {1, OperandInfo74}, // Inst #1379 = JAsmO + {1, OperandInfo74}, // Inst #1380 = JAsmP + {1, OperandInfo74}, // Inst #1381 = JAsmZ + {1, OperandInfo74}, // Inst #1382 = JG + {1, OperandInfo74}, // Inst #1383 = JGAsmE + {1, OperandInfo74}, // Inst #1384 = JGAsmH + {1, OperandInfo74}, // Inst #1385 = JGAsmHE + {1, OperandInfo74}, // Inst #1386 = JGAsmL + {1, OperandInfo74}, // Inst #1387 = JGAsmLE + {1, OperandInfo74}, // Inst #1388 = JGAsmLH + {1, OperandInfo74}, // Inst #1389 = JGAsmM + {1, OperandInfo74}, // Inst #1390 = JGAsmNE + {1, OperandInfo74}, // Inst #1391 = JGAsmNH + {1, OperandInfo74}, // Inst #1392 = JGAsmNHE + {1, OperandInfo74}, // Inst #1393 = JGAsmNL + {1, OperandInfo74}, // Inst #1394 = JGAsmNLE + {1, OperandInfo74}, // Inst #1395 = JGAsmNLH + {1, OperandInfo74}, // Inst #1396 = JGAsmNM + {1, OperandInfo74}, // Inst #1397 = JGAsmNO + {1, OperandInfo74}, // Inst #1398 = JGAsmNP + {1, OperandInfo74}, // Inst #1399 = JGAsmNZ + {1, OperandInfo74}, // Inst #1400 = JGAsmO + {1, OperandInfo74}, // Inst #1401 = JGAsmP + {1, OperandInfo74}, // Inst #1402 = JGAsmZ + {4, OperandInfo163}, // Inst #1403 = KDB + {2, OperandInfo93}, // Inst #1404 = KDBR + {3, OperandInfo285}, // Inst #1405 = KDSA + {2, OperandInfo93}, // Inst #1406 = KDTR + {4, OperandInfo170}, // Inst #1407 = KEB + {2, OperandInfo94}, // Inst #1408 = KEBR + {3, OperandInfo285}, // Inst #1409 = KIMD + {3, OperandInfo285}, // Inst #1410 = KLMD + {4, OperandInfo210}, // Inst #1411 = KM + {6, OperandInfo286}, // Inst #1412 = KMA + {3, OperandInfo285}, // Inst #1413 = KMAC + {4, OperandInfo210}, // Inst #1414 = KMC + {6, OperandInfo286}, // Inst #1415 = KMCTR + {4, OperandInfo210}, // Inst #1416 = KMF + {4, OperandInfo210}, // Inst #1417 = KMO + {2, OperandInfo95}, // Inst #1418 = KXBR + {2, OperandInfo95}, // Inst #1419 = KXTR + {4, OperandInfo162}, // Inst #1420 = L + {4, OperandInfo45}, // Inst #1421 = LA + {4, OperandInfo216}, // Inst #1422 = LAA + {4, OperandInfo194}, // Inst #1423 = LAAG + {4, OperandInfo216}, // Inst #1424 = LAAL + {4, OperandInfo194}, // Inst #1425 = LAALG + {4, OperandInfo45}, // Inst #1426 = LAE + {4, OperandInfo45}, // Inst #1427 = LAEY + {4, OperandInfo287}, // Inst #1428 = LAM + {4, OperandInfo287}, // Inst #1429 = LAMY + {4, OperandInfo216}, // Inst #1430 = LAN + {4, OperandInfo194}, // Inst #1431 = LANG + {4, OperandInfo216}, // Inst #1432 = LAO + {4, OperandInfo194}, // Inst #1433 = LAOG + {2, OperandInfo188}, // Inst #1434 = LARL + {4, OperandInfo288}, // Inst #1435 = LASP + {4, OperandInfo162}, // Inst #1436 = LAT + {4, OperandInfo216}, // Inst #1437 = LAX + {4, OperandInfo194}, // Inst #1438 = LAXG + {4, OperandInfo45}, // Inst #1439 = LAY + {4, OperandInfo162}, // Inst #1440 = LB + {2, OperandInfo175}, // Inst #1441 = LBEAR + {4, OperandInfo199}, // Inst #1442 = LBH + {2, OperandInfo214}, // Inst #1443 = LBR + {5, OperandInfo289}, // Inst #1444 = LCBB + {2, OperandInfo175}, // Inst #1445 = LCCTL + {2, OperandInfo93}, // Inst #1446 = LCDBR + {2, OperandInfo93}, // Inst #1447 = LCDFR + {2, OperandInfo94}, // Inst #1448 = LCDFR_32 + {2, OperandInfo93}, // Inst #1449 = LCDR + {2, OperandInfo94}, // Inst #1450 = LCEBR + {2, OperandInfo94}, // Inst #1451 = LCER + {2, OperandInfo187}, // Inst #1452 = LCGFR + {2, OperandInfo144}, // Inst #1453 = LCGR + {2, OperandInfo214}, // Inst #1454 = LCR + {4, OperandInfo290}, // Inst #1455 = LCTL + {4, OperandInfo290}, // Inst #1456 = LCTLG + {2, OperandInfo95}, // Inst #1457 = LCXBR + {2, OperandInfo95}, // Inst #1458 = LCXR + {4, OperandInfo163}, // Inst #1459 = LD + {4, OperandInfo163}, // Inst #1460 = LDE + {4, OperandInfo170}, // Inst #1461 = LDE32 + {4, OperandInfo163}, // Inst #1462 = LDEB + {2, OperandInfo291}, // Inst #1463 = LDEBR + {2, OperandInfo291}, // Inst #1464 = LDER + {3, OperandInfo292}, // Inst #1465 = LDETR + {2, OperandInfo166}, // Inst #1466 = LDGR + {2, OperandInfo93}, // Inst #1467 = LDR + {2, OperandInfo94}, // Inst #1468 = LDR32 + {2, OperandInfo95}, // Inst #1469 = LDXBR + {4, OperandInfo258}, // Inst #1470 = LDXBRA + {2, OperandInfo293}, // Inst #1471 = LDXR + {4, OperandInfo258}, // Inst #1472 = LDXTR + {4, OperandInfo163}, // Inst #1473 = LDY + {4, OperandInfo170}, // Inst #1474 = LE + {2, OperandInfo294}, // Inst #1475 = LEDBR + {4, OperandInfo295}, // Inst #1476 = LEDBRA + {2, OperandInfo294}, // Inst #1477 = LEDR + {4, OperandInfo295}, // Inst #1478 = LEDTR + {2, OperandInfo94}, // Inst #1479 = LER + {2, OperandInfo95}, // Inst #1480 = LEXBR + {4, OperandInfo258}, // Inst #1481 = LEXBRA + {2, OperandInfo296}, // Inst #1482 = LEXR + {4, OperandInfo170}, // Inst #1483 = LEY + {2, OperandInfo175}, // Inst #1484 = LFAS + {4, OperandInfo199}, // Inst #1485 = LFH + {4, OperandInfo199}, // Inst #1486 = LFHAT + {2, OperandInfo175}, // Inst #1487 = LFPC + {4, OperandInfo45}, // Inst #1488 = LG + {4, OperandInfo45}, // Inst #1489 = LGAT + {4, OperandInfo45}, // Inst #1490 = LGB + {2, OperandInfo144}, // Inst #1491 = LGBR + {2, OperandInfo233}, // Inst #1492 = LGDR + {4, OperandInfo45}, // Inst #1493 = LGF + {2, OperandInfo117}, // Inst #1494 = LGFI + {2, OperandInfo187}, // Inst #1495 = LGFR + {2, OperandInfo188}, // Inst #1496 = LGFRL + {4, OperandInfo45}, // Inst #1497 = LGG + {4, OperandInfo45}, // Inst #1498 = LGH + {2, OperandInfo117}, // Inst #1499 = LGHI + {2, OperandInfo144}, // Inst #1500 = LGHR + {2, OperandInfo188}, // Inst #1501 = LGHRL + {2, OperandInfo144}, // Inst #1502 = LGR + {2, OperandInfo188}, // Inst #1503 = LGRL + {4, OperandInfo45}, // Inst #1504 = LGSC + {4, OperandInfo162}, // Inst #1505 = LH + {4, OperandInfo199}, // Inst #1506 = LHH + {2, OperandInfo180}, // Inst #1507 = LHI + {2, OperandInfo214}, // Inst #1508 = LHR + {2, OperandInfo202}, // Inst #1509 = LHRL + {4, OperandInfo162}, // Inst #1510 = LHY + {4, OperandInfo162}, // Inst #1511 = LLC + {4, OperandInfo199}, // Inst #1512 = LLCH + {2, OperandInfo214}, // Inst #1513 = LLCR + {4, OperandInfo45}, // Inst #1514 = LLGC + {2, OperandInfo144}, // Inst #1515 = LLGCR + {4, OperandInfo45}, // Inst #1516 = LLGF + {4, OperandInfo45}, // Inst #1517 = LLGFAT + {2, OperandInfo187}, // Inst #1518 = LLGFR + {2, OperandInfo188}, // Inst #1519 = LLGFRL + {4, OperandInfo45}, // Inst #1520 = LLGFSG + {4, OperandInfo45}, // Inst #1521 = LLGH + {2, OperandInfo144}, // Inst #1522 = LLGHR + {2, OperandInfo188}, // Inst #1523 = LLGHRL + {4, OperandInfo45}, // Inst #1524 = LLGT + {4, OperandInfo45}, // Inst #1525 = LLGTAT + {2, OperandInfo144}, // Inst #1526 = LLGTR + {4, OperandInfo162}, // Inst #1527 = LLH + {4, OperandInfo199}, // Inst #1528 = LLHH + {2, OperandInfo214}, // Inst #1529 = LLHR + {2, OperandInfo202}, // Inst #1530 = LLHRL + {2, OperandInfo117}, // Inst #1531 = LLIHF + {2, OperandInfo117}, // Inst #1532 = LLIHH + {2, OperandInfo117}, // Inst #1533 = LLIHL + {2, OperandInfo117}, // Inst #1534 = LLILF + {2, OperandInfo117}, // Inst #1535 = LLILH + {2, OperandInfo117}, // Inst #1536 = LLILL + {4, OperandInfo45}, // Inst #1537 = LLZRGF + {4, OperandInfo216}, // Inst #1538 = LM + {6, OperandInfo297}, // Inst #1539 = LMD + {4, OperandInfo194}, // Inst #1540 = LMG + {4, OperandInfo298}, // Inst #1541 = LMH + {4, OperandInfo216}, // Inst #1542 = LMY + {2, OperandInfo93}, // Inst #1543 = LNDBR + {2, OperandInfo93}, // Inst #1544 = LNDFR + {2, OperandInfo94}, // Inst #1545 = LNDFR_32 + {2, OperandInfo93}, // Inst #1546 = LNDR + {2, OperandInfo94}, // Inst #1547 = LNEBR + {2, OperandInfo94}, // Inst #1548 = LNER + {2, OperandInfo187}, // Inst #1549 = LNGFR + {2, OperandInfo144}, // Inst #1550 = LNGR + {2, OperandInfo214}, // Inst #1551 = LNR + {2, OperandInfo95}, // Inst #1552 = LNXBR + {2, OperandInfo95}, // Inst #1553 = LNXR + {6, OperandInfo299}, // Inst #1554 = LOC + {5, OperandInfo300}, // Inst #1555 = LOCAsm + {4, OperandInfo301}, // Inst #1556 = LOCAsmE + {4, OperandInfo301}, // Inst #1557 = LOCAsmH + {4, OperandInfo301}, // Inst #1558 = LOCAsmHE + {4, OperandInfo301}, // Inst #1559 = LOCAsmL + {4, OperandInfo301}, // Inst #1560 = LOCAsmLE + {4, OperandInfo301}, // Inst #1561 = LOCAsmLH + {4, OperandInfo301}, // Inst #1562 = LOCAsmM + {4, OperandInfo301}, // Inst #1563 = LOCAsmNE + {4, OperandInfo301}, // Inst #1564 = LOCAsmNH + {4, OperandInfo301}, // Inst #1565 = LOCAsmNHE + {4, OperandInfo301}, // Inst #1566 = LOCAsmNL + {4, OperandInfo301}, // Inst #1567 = LOCAsmNLE + {4, OperandInfo301}, // Inst #1568 = LOCAsmNLH + {4, OperandInfo301}, // Inst #1569 = LOCAsmNM + {4, OperandInfo301}, // Inst #1570 = LOCAsmNO + {4, OperandInfo301}, // Inst #1571 = LOCAsmNP + {4, OperandInfo301}, // Inst #1572 = LOCAsmNZ + {4, OperandInfo301}, // Inst #1573 = LOCAsmO + {4, OperandInfo301}, // Inst #1574 = LOCAsmP + {4, OperandInfo301}, // Inst #1575 = LOCAsmZ + {6, OperandInfo302}, // Inst #1576 = LOCFH + {5, OperandInfo303}, // Inst #1577 = LOCFHAsm + {4, OperandInfo304}, // Inst #1578 = LOCFHAsmE + {4, OperandInfo304}, // Inst #1579 = LOCFHAsmH + {4, OperandInfo304}, // Inst #1580 = LOCFHAsmHE + {4, OperandInfo304}, // Inst #1581 = LOCFHAsmL + {4, OperandInfo304}, // Inst #1582 = LOCFHAsmLE + {4, OperandInfo304}, // Inst #1583 = LOCFHAsmLH + {4, OperandInfo304}, // Inst #1584 = LOCFHAsmM + {4, OperandInfo304}, // Inst #1585 = LOCFHAsmNE + {4, OperandInfo304}, // Inst #1586 = LOCFHAsmNH + {4, OperandInfo304}, // Inst #1587 = LOCFHAsmNHE + {4, OperandInfo304}, // Inst #1588 = LOCFHAsmNL + {4, OperandInfo304}, // Inst #1589 = LOCFHAsmNLE + {4, OperandInfo304}, // Inst #1590 = LOCFHAsmNLH + {4, OperandInfo304}, // Inst #1591 = LOCFHAsmNM + {4, OperandInfo304}, // Inst #1592 = LOCFHAsmNO + {4, OperandInfo304}, // Inst #1593 = LOCFHAsmNP + {4, OperandInfo304}, // Inst #1594 = LOCFHAsmNZ + {4, OperandInfo304}, // Inst #1595 = LOCFHAsmO + {4, OperandInfo304}, // Inst #1596 = LOCFHAsmP + {4, OperandInfo304}, // Inst #1597 = LOCFHAsmZ + {5, OperandInfo305}, // Inst #1598 = LOCFHR + {4, OperandInfo306}, // Inst #1599 = LOCFHRAsm + {3, OperandInfo307}, // Inst #1600 = LOCFHRAsmE + {3, OperandInfo307}, // Inst #1601 = LOCFHRAsmH + {3, OperandInfo307}, // Inst #1602 = LOCFHRAsmHE + {3, OperandInfo307}, // Inst #1603 = LOCFHRAsmL + {3, OperandInfo307}, // Inst #1604 = LOCFHRAsmLE + {3, OperandInfo307}, // Inst #1605 = LOCFHRAsmLH + {3, OperandInfo307}, // Inst #1606 = LOCFHRAsmM + {3, OperandInfo307}, // Inst #1607 = LOCFHRAsmNE + {3, OperandInfo307}, // Inst #1608 = LOCFHRAsmNH + {3, OperandInfo307}, // Inst #1609 = LOCFHRAsmNHE + {3, OperandInfo307}, // Inst #1610 = LOCFHRAsmNL + {3, OperandInfo307}, // Inst #1611 = LOCFHRAsmNLE + {3, OperandInfo307}, // Inst #1612 = LOCFHRAsmNLH + {3, OperandInfo307}, // Inst #1613 = LOCFHRAsmNM + {3, OperandInfo307}, // Inst #1614 = LOCFHRAsmNO + {3, OperandInfo307}, // Inst #1615 = LOCFHRAsmNP + {3, OperandInfo307}, // Inst #1616 = LOCFHRAsmNZ + {3, OperandInfo307}, // Inst #1617 = LOCFHRAsmO + {3, OperandInfo307}, // Inst #1618 = LOCFHRAsmP + {3, OperandInfo307}, // Inst #1619 = LOCFHRAsmZ + {6, OperandInfo308}, // Inst #1620 = LOCG + {5, OperandInfo309}, // Inst #1621 = LOCGAsm + {4, OperandInfo310}, // Inst #1622 = LOCGAsmE + {4, OperandInfo310}, // Inst #1623 = LOCGAsmH + {4, OperandInfo310}, // Inst #1624 = LOCGAsmHE + {4, OperandInfo310}, // Inst #1625 = LOCGAsmL + {4, OperandInfo310}, // Inst #1626 = LOCGAsmLE + {4, OperandInfo310}, // Inst #1627 = LOCGAsmLH + {4, OperandInfo310}, // Inst #1628 = LOCGAsmM + {4, OperandInfo310}, // Inst #1629 = LOCGAsmNE + {4, OperandInfo310}, // Inst #1630 = LOCGAsmNH + {4, OperandInfo310}, // Inst #1631 = LOCGAsmNHE + {4, OperandInfo310}, // Inst #1632 = LOCGAsmNL + {4, OperandInfo310}, // Inst #1633 = LOCGAsmNLE + {4, OperandInfo310}, // Inst #1634 = LOCGAsmNLH + {4, OperandInfo310}, // Inst #1635 = LOCGAsmNM + {4, OperandInfo310}, // Inst #1636 = LOCGAsmNO + {4, OperandInfo310}, // Inst #1637 = LOCGAsmNP + {4, OperandInfo310}, // Inst #1638 = LOCGAsmNZ + {4, OperandInfo310}, // Inst #1639 = LOCGAsmO + {4, OperandInfo310}, // Inst #1640 = LOCGAsmP + {4, OperandInfo310}, // Inst #1641 = LOCGAsmZ + {5, OperandInfo311}, // Inst #1642 = LOCGHI + {4, OperandInfo312}, // Inst #1643 = LOCGHIAsm + {3, OperandInfo83}, // Inst #1644 = LOCGHIAsmE + {3, OperandInfo83}, // Inst #1645 = LOCGHIAsmH + {3, OperandInfo83}, // Inst #1646 = LOCGHIAsmHE + {3, OperandInfo83}, // Inst #1647 = LOCGHIAsmL + {3, OperandInfo83}, // Inst #1648 = LOCGHIAsmLE + {3, OperandInfo83}, // Inst #1649 = LOCGHIAsmLH + {3, OperandInfo83}, // Inst #1650 = LOCGHIAsmM + {3, OperandInfo83}, // Inst #1651 = LOCGHIAsmNE + {3, OperandInfo83}, // Inst #1652 = LOCGHIAsmNH + {3, OperandInfo83}, // Inst #1653 = LOCGHIAsmNHE + {3, OperandInfo83}, // Inst #1654 = LOCGHIAsmNL + {3, OperandInfo83}, // Inst #1655 = LOCGHIAsmNLE + {3, OperandInfo83}, // Inst #1656 = LOCGHIAsmNLH + {3, OperandInfo83}, // Inst #1657 = LOCGHIAsmNM + {3, OperandInfo83}, // Inst #1658 = LOCGHIAsmNO + {3, OperandInfo83}, // Inst #1659 = LOCGHIAsmNP + {3, OperandInfo83}, // Inst #1660 = LOCGHIAsmNZ + {3, OperandInfo83}, // Inst #1661 = LOCGHIAsmO + {3, OperandInfo83}, // Inst #1662 = LOCGHIAsmP + {3, OperandInfo83}, // Inst #1663 = LOCGHIAsmZ + {5, OperandInfo313}, // Inst #1664 = LOCGR + {4, OperandInfo314}, // Inst #1665 = LOCGRAsm + {3, OperandInfo133}, // Inst #1666 = LOCGRAsmE + {3, OperandInfo133}, // Inst #1667 = LOCGRAsmH + {3, OperandInfo133}, // Inst #1668 = LOCGRAsmHE + {3, OperandInfo133}, // Inst #1669 = LOCGRAsmL + {3, OperandInfo133}, // Inst #1670 = LOCGRAsmLE + {3, OperandInfo133}, // Inst #1671 = LOCGRAsmLH + {3, OperandInfo133}, // Inst #1672 = LOCGRAsmM + {3, OperandInfo133}, // Inst #1673 = LOCGRAsmNE + {3, OperandInfo133}, // Inst #1674 = LOCGRAsmNH + {3, OperandInfo133}, // Inst #1675 = LOCGRAsmNHE + {3, OperandInfo133}, // Inst #1676 = LOCGRAsmNL + {3, OperandInfo133}, // Inst #1677 = LOCGRAsmNLE + {3, OperandInfo133}, // Inst #1678 = LOCGRAsmNLH + {3, OperandInfo133}, // Inst #1679 = LOCGRAsmNM + {3, OperandInfo133}, // Inst #1680 = LOCGRAsmNO + {3, OperandInfo133}, // Inst #1681 = LOCGRAsmNP + {3, OperandInfo133}, // Inst #1682 = LOCGRAsmNZ + {3, OperandInfo133}, // Inst #1683 = LOCGRAsmO + {3, OperandInfo133}, // Inst #1684 = LOCGRAsmP + {3, OperandInfo133}, // Inst #1685 = LOCGRAsmZ + {5, OperandInfo315}, // Inst #1686 = LOCHHI + {4, OperandInfo316}, // Inst #1687 = LOCHHIAsm + {3, OperandInfo136}, // Inst #1688 = LOCHHIAsmE + {3, OperandInfo136}, // Inst #1689 = LOCHHIAsmH + {3, OperandInfo136}, // Inst #1690 = LOCHHIAsmHE + {3, OperandInfo136}, // Inst #1691 = LOCHHIAsmL + {3, OperandInfo136}, // Inst #1692 = LOCHHIAsmLE + {3, OperandInfo136}, // Inst #1693 = LOCHHIAsmLH + {3, OperandInfo136}, // Inst #1694 = LOCHHIAsmM + {3, OperandInfo136}, // Inst #1695 = LOCHHIAsmNE + {3, OperandInfo136}, // Inst #1696 = LOCHHIAsmNH + {3, OperandInfo136}, // Inst #1697 = LOCHHIAsmNHE + {3, OperandInfo136}, // Inst #1698 = LOCHHIAsmNL + {3, OperandInfo136}, // Inst #1699 = LOCHHIAsmNLE + {3, OperandInfo136}, // Inst #1700 = LOCHHIAsmNLH + {3, OperandInfo136}, // Inst #1701 = LOCHHIAsmNM + {3, OperandInfo136}, // Inst #1702 = LOCHHIAsmNO + {3, OperandInfo136}, // Inst #1703 = LOCHHIAsmNP + {3, OperandInfo136}, // Inst #1704 = LOCHHIAsmNZ + {3, OperandInfo136}, // Inst #1705 = LOCHHIAsmO + {3, OperandInfo136}, // Inst #1706 = LOCHHIAsmP + {3, OperandInfo136}, // Inst #1707 = LOCHHIAsmZ + {5, OperandInfo317}, // Inst #1708 = LOCHI + {4, OperandInfo318}, // Inst #1709 = LOCHIAsm + {3, OperandInfo130}, // Inst #1710 = LOCHIAsmE + {3, OperandInfo130}, // Inst #1711 = LOCHIAsmH + {3, OperandInfo130}, // Inst #1712 = LOCHIAsmHE + {3, OperandInfo130}, // Inst #1713 = LOCHIAsmL + {3, OperandInfo130}, // Inst #1714 = LOCHIAsmLE + {3, OperandInfo130}, // Inst #1715 = LOCHIAsmLH + {3, OperandInfo130}, // Inst #1716 = LOCHIAsmM + {3, OperandInfo130}, // Inst #1717 = LOCHIAsmNE + {3, OperandInfo130}, // Inst #1718 = LOCHIAsmNH + {3, OperandInfo130}, // Inst #1719 = LOCHIAsmNHE + {3, OperandInfo130}, // Inst #1720 = LOCHIAsmNL + {3, OperandInfo130}, // Inst #1721 = LOCHIAsmNLE + {3, OperandInfo130}, // Inst #1722 = LOCHIAsmNLH + {3, OperandInfo130}, // Inst #1723 = LOCHIAsmNM + {3, OperandInfo130}, // Inst #1724 = LOCHIAsmNO + {3, OperandInfo130}, // Inst #1725 = LOCHIAsmNP + {3, OperandInfo130}, // Inst #1726 = LOCHIAsmNZ + {3, OperandInfo130}, // Inst #1727 = LOCHIAsmO + {3, OperandInfo130}, // Inst #1728 = LOCHIAsmP + {3, OperandInfo130}, // Inst #1729 = LOCHIAsmZ + {5, OperandInfo319}, // Inst #1730 = LOCR + {4, OperandInfo320}, // Inst #1731 = LOCRAsm + {3, OperandInfo137}, // Inst #1732 = LOCRAsmE + {3, OperandInfo137}, // Inst #1733 = LOCRAsmH + {3, OperandInfo137}, // Inst #1734 = LOCRAsmHE + {3, OperandInfo137}, // Inst #1735 = LOCRAsmL + {3, OperandInfo137}, // Inst #1736 = LOCRAsmLE + {3, OperandInfo137}, // Inst #1737 = LOCRAsmLH + {3, OperandInfo137}, // Inst #1738 = LOCRAsmM + {3, OperandInfo137}, // Inst #1739 = LOCRAsmNE + {3, OperandInfo137}, // Inst #1740 = LOCRAsmNH + {3, OperandInfo137}, // Inst #1741 = LOCRAsmNHE + {3, OperandInfo137}, // Inst #1742 = LOCRAsmNL + {3, OperandInfo137}, // Inst #1743 = LOCRAsmNLE + {3, OperandInfo137}, // Inst #1744 = LOCRAsmNLH + {3, OperandInfo137}, // Inst #1745 = LOCRAsmNM + {3, OperandInfo137}, // Inst #1746 = LOCRAsmNO + {3, OperandInfo137}, // Inst #1747 = LOCRAsmNP + {3, OperandInfo137}, // Inst #1748 = LOCRAsmNZ + {3, OperandInfo137}, // Inst #1749 = LOCRAsmO + {3, OperandInfo137}, // Inst #1750 = LOCRAsmP + {3, OperandInfo137}, // Inst #1751 = LOCRAsmZ + {2, OperandInfo175}, // Inst #1752 = LPCTL + {5, OperandInfo321}, // Inst #1753 = LPD + {2, OperandInfo93}, // Inst #1754 = LPDBR + {2, OperandInfo93}, // Inst #1755 = LPDFR + {2, OperandInfo94}, // Inst #1756 = LPDFR_32 + {5, OperandInfo321}, // Inst #1757 = LPDG + {2, OperandInfo93}, // Inst #1758 = LPDR + {2, OperandInfo94}, // Inst #1759 = LPEBR + {2, OperandInfo94}, // Inst #1760 = LPER + {2, OperandInfo187}, // Inst #1761 = LPGFR + {2, OperandInfo144}, // Inst #1762 = LPGR + {2, OperandInfo175}, // Inst #1763 = LPP + {4, OperandInfo84}, // Inst #1764 = LPQ + {2, OperandInfo214}, // Inst #1765 = LPR + {2, OperandInfo175}, // Inst #1766 = LPSW + {2, OperandInfo175}, // Inst #1767 = LPSWE + {2, OperandInfo175}, // Inst #1768 = LPSWEY + {5, OperandInfo322}, // Inst #1769 = LPTEA + {2, OperandInfo95}, // Inst #1770 = LPXBR + {2, OperandInfo95}, // Inst #1771 = LPXR + {2, OperandInfo214}, // Inst #1772 = LR + {4, OperandInfo45}, // Inst #1773 = LRA + {4, OperandInfo45}, // Inst #1774 = LRAG + {4, OperandInfo45}, // Inst #1775 = LRAY + {2, OperandInfo293}, // Inst #1776 = LRDR + {2, OperandInfo294}, // Inst #1777 = LRER + {2, OperandInfo202}, // Inst #1778 = LRL + {4, OperandInfo162}, // Inst #1779 = LRV + {4, OperandInfo45}, // Inst #1780 = LRVG + {2, OperandInfo144}, // Inst #1781 = LRVGR + {4, OperandInfo162}, // Inst #1782 = LRVH + {2, OperandInfo214}, // Inst #1783 = LRVR + {2, OperandInfo175}, // Inst #1784 = LSCTL + {4, OperandInfo162}, // Inst #1785 = LT + {2, OperandInfo93}, // Inst #1786 = LTDBR + {2, OperandInfo93}, // Inst #1787 = LTDBRCompare + {2, OperandInfo93}, // Inst #1788 = LTDR + {2, OperandInfo93}, // Inst #1789 = LTDTR + {2, OperandInfo94}, // Inst #1790 = LTEBR + {2, OperandInfo94}, // Inst #1791 = LTEBRCompare + {2, OperandInfo94}, // Inst #1792 = LTER + {4, OperandInfo45}, // Inst #1793 = LTG + {4, OperandInfo45}, // Inst #1794 = LTGF + {2, OperandInfo187}, // Inst #1795 = LTGFR + {2, OperandInfo144}, // Inst #1796 = LTGR + {2, OperandInfo214}, // Inst #1797 = LTR + {2, OperandInfo95}, // Inst #1798 = LTXBR + {2, OperandInfo95}, // Inst #1799 = LTXBRCompare + {2, OperandInfo95}, // Inst #1800 = LTXR + {2, OperandInfo95}, // Inst #1801 = LTXTR + {2, OperandInfo247}, // Inst #1802 = LURA + {2, OperandInfo144}, // Inst #1803 = LURAG + {4, OperandInfo96}, // Inst #1804 = LXD + {4, OperandInfo96}, // Inst #1805 = LXDB + {2, OperandInfo323}, // Inst #1806 = LXDBR + {2, OperandInfo323}, // Inst #1807 = LXDR + {3, OperandInfo324}, // Inst #1808 = LXDTR + {4, OperandInfo96}, // Inst #1809 = LXE + {4, OperandInfo96}, // Inst #1810 = LXEB + {2, OperandInfo325}, // Inst #1811 = LXEBR + {2, OperandInfo325}, // Inst #1812 = LXER + {2, OperandInfo95}, // Inst #1813 = LXR + {4, OperandInfo162}, // Inst #1814 = LY + {1, OperandInfo326}, // Inst #1815 = LZDR + {1, OperandInfo327}, // Inst #1816 = LZER + {4, OperandInfo162}, // Inst #1817 = LZRF + {4, OperandInfo45}, // Inst #1818 = LZRG + {1, OperandInfo328}, // Inst #1819 = LZXR + {5, OperandInfo240}, // Inst #1820 = M + {6, OperandInfo329}, // Inst #1821 = MAD + {6, OperandInfo329}, // Inst #1822 = MADB + {4, OperandInfo330}, // Inst #1823 = MADBR + {4, OperandInfo330}, // Inst #1824 = MADR + {6, OperandInfo331}, // Inst #1825 = MAE + {6, OperandInfo331}, // Inst #1826 = MAEB + {4, OperandInfo332}, // Inst #1827 = MAEBR + {4, OperandInfo332}, // Inst #1828 = MAER + {6, OperandInfo333}, // Inst #1829 = MAY + {6, OperandInfo329}, // Inst #1830 = MAYH + {4, OperandInfo330}, // Inst #1831 = MAYHR + {6, OperandInfo329}, // Inst #1832 = MAYL + {4, OperandInfo330}, // Inst #1833 = MAYLR + {4, OperandInfo334}, // Inst #1834 = MAYR + {3, OperandInfo116}, // Inst #1835 = MC + {5, OperandInfo124}, // Inst #1836 = MD + {5, OperandInfo124}, // Inst #1837 = MDB + {3, OperandInfo125}, // Inst #1838 = MDBR + {5, OperandInfo124}, // Inst #1839 = MDE + {5, OperandInfo124}, // Inst #1840 = MDEB + {3, OperandInfo335}, // Inst #1841 = MDEBR + {3, OperandInfo335}, // Inst #1842 = MDER + {3, OperandInfo125}, // Inst #1843 = MDR + {3, OperandInfo126}, // Inst #1844 = MDTR + {4, OperandInfo127}, // Inst #1845 = MDTRA + {5, OperandInfo124}, // Inst #1846 = ME + {5, OperandInfo128}, // Inst #1847 = MEE + {5, OperandInfo128}, // Inst #1848 = MEEB + {3, OperandInfo129}, // Inst #1849 = MEEBR + {3, OperandInfo129}, // Inst #1850 = MEER + {3, OperandInfo335}, // Inst #1851 = MER + {5, OperandInfo240}, // Inst #1852 = MFY + {5, OperandInfo240}, // Inst #1853 = MG + {5, OperandInfo131}, // Inst #1854 = MGH + {3, OperandInfo83}, // Inst #1855 = MGHI + {3, OperandInfo99}, // Inst #1856 = MGRK + {5, OperandInfo123}, // Inst #1857 = MH + {3, OperandInfo130}, // Inst #1858 = MHI + {5, OperandInfo123}, // Inst #1859 = MHY + {5, OperandInfo240}, // Inst #1860 = ML + {5, OperandInfo240}, // Inst #1861 = MLG + {3, OperandInfo229}, // Inst #1862 = MLGR + {3, OperandInfo244}, // Inst #1863 = MLR + {6, OperandInfo139}, // Inst #1864 = MP + {3, OperandInfo244}, // Inst #1865 = MR + {5, OperandInfo123}, // Inst #1866 = MS + {5, OperandInfo123}, // Inst #1867 = MSC + {2, OperandInfo175}, // Inst #1868 = MSCH + {6, OperandInfo329}, // Inst #1869 = MSD + {6, OperandInfo329}, // Inst #1870 = MSDB + {4, OperandInfo330}, // Inst #1871 = MSDBR + {4, OperandInfo330}, // Inst #1872 = MSDR + {6, OperandInfo331}, // Inst #1873 = MSE + {6, OperandInfo331}, // Inst #1874 = MSEB + {4, OperandInfo332}, // Inst #1875 = MSEBR + {4, OperandInfo332}, // Inst #1876 = MSER + {3, OperandInfo130}, // Inst #1877 = MSFI + {5, OperandInfo131}, // Inst #1878 = MSG + {5, OperandInfo131}, // Inst #1879 = MSGC + {5, OperandInfo131}, // Inst #1880 = MSGF + {3, OperandInfo83}, // Inst #1881 = MSGFI + {3, OperandInfo132}, // Inst #1882 = MSGFR + {3, OperandInfo133}, // Inst #1883 = MSGR + {3, OperandInfo100}, // Inst #1884 = MSGRKC + {3, OperandInfo137}, // Inst #1885 = MSR + {3, OperandInfo138}, // Inst #1886 = MSRKC + {1, OperandInfo336}, // Inst #1887 = MSTA + {5, OperandInfo123}, // Inst #1888 = MSY + {5, OperandInfo209}, // Inst #1889 = MVC + {4, OperandInfo288}, // Inst #1890 = MVCDK + {5, OperandInfo209}, // Inst #1891 = MVCIN + {6, OperandInfo337}, // Inst #1892 = MVCK + {4, OperandInfo210}, // Inst #1893 = MVCL + {6, OperandInfo211}, // Inst #1894 = MVCLE + {6, OperandInfo211}, // Inst #1895 = MVCLU + {5, OperandInfo230}, // Inst #1896 = MVCOS + {6, OperandInfo337}, // Inst #1897 = MVCP + {4, OperandInfo288}, // Inst #1898 = MVCRL + {6, OperandInfo337}, // Inst #1899 = MVCS + {4, OperandInfo288}, // Inst #1900 = MVCSK + {3, OperandInfo116}, // Inst #1901 = MVGHI + {3, OperandInfo116}, // Inst #1902 = MVHHI + {3, OperandInfo116}, // Inst #1903 = MVHI + {3, OperandInfo116}, // Inst #1904 = MVI + {3, OperandInfo116}, // Inst #1905 = MVIY + {5, OperandInfo209}, // Inst #1906 = MVN + {6, OperandInfo139}, // Inst #1907 = MVO + {2, OperandInfo144}, // Inst #1908 = MVPG + {4, OperandInfo219}, // Inst #1909 = MVST + {5, OperandInfo209}, // Inst #1910 = MVZ + {3, OperandInfo140}, // Inst #1911 = MXBR + {5, OperandInfo338}, // Inst #1912 = MXD + {5, OperandInfo338}, // Inst #1913 = MXDB + {3, OperandInfo339}, // Inst #1914 = MXDBR + {3, OperandInfo339}, // Inst #1915 = MXDR + {3, OperandInfo140}, // Inst #1916 = MXR + {3, OperandInfo141}, // Inst #1917 = MXTR + {4, OperandInfo142}, // Inst #1918 = MXTRA + {5, OperandInfo340}, // Inst #1919 = MY + {5, OperandInfo44}, // Inst #1920 = MYH + {3, OperandInfo126}, // Inst #1921 = MYHR + {5, OperandInfo44}, // Inst #1922 = MYL + {3, OperandInfo126}, // Inst #1923 = MYLR + {3, OperandInfo341}, // Inst #1924 = MYR + {5, OperandInfo123}, // Inst #1925 = N + {5, OperandInfo209}, // Inst #1926 = NC + {3, OperandInfo100}, // Inst #1927 = NCGRK + {3, OperandInfo138}, // Inst #1928 = NCRK + {5, OperandInfo131}, // Inst #1929 = NG + {3, OperandInfo133}, // Inst #1930 = NGR + {3, OperandInfo100}, // Inst #1931 = NGRK + {3, OperandInfo116}, // Inst #1932 = NI + {2, OperandInfo10}, // Inst #1933 = NIAI + {3, OperandInfo136}, // Inst #1934 = NIHF + {3, OperandInfo136}, // Inst #1935 = NIHH + {3, OperandInfo136}, // Inst #1936 = NIHL + {3, OperandInfo130}, // Inst #1937 = NILF + {3, OperandInfo130}, // Inst #1938 = NILH + {3, OperandInfo130}, // Inst #1939 = NILL + {3, OperandInfo116}, // Inst #1940 = NIY + {3, OperandInfo100}, // Inst #1941 = NNGRK + {0, NULL}, // Inst #1942 = NNPA + {3, OperandInfo138}, // Inst #1943 = NNRK + {3, OperandInfo100}, // Inst #1944 = NOGRK + {0, NULL}, // Inst #1945 = NOP_bare + {3, OperandInfo138}, // Inst #1946 = NORK + {3, OperandInfo137}, // Inst #1947 = NR + {3, OperandInfo138}, // Inst #1948 = NRK + {4, OperandInfo45}, // Inst #1949 = NTSTG + {3, OperandInfo100}, // Inst #1950 = NXGRK + {3, OperandInfo138}, // Inst #1951 = NXRK + {5, OperandInfo123}, // Inst #1952 = NY + {5, OperandInfo123}, // Inst #1953 = O + {5, OperandInfo209}, // Inst #1954 = OC + {3, OperandInfo100}, // Inst #1955 = OCGRK + {3, OperandInfo138}, // Inst #1956 = OCRK + {5, OperandInfo131}, // Inst #1957 = OG + {3, OperandInfo133}, // Inst #1958 = OGR + {3, OperandInfo100}, // Inst #1959 = OGRK + {3, OperandInfo116}, // Inst #1960 = OI + {3, OperandInfo136}, // Inst #1961 = OIHF + {3, OperandInfo136}, // Inst #1962 = OIHH + {3, OperandInfo136}, // Inst #1963 = OIHL + {3, OperandInfo130}, // Inst #1964 = OILF + {3, OperandInfo130}, // Inst #1965 = OILH + {3, OperandInfo130}, // Inst #1966 = OILL + {3, OperandInfo116}, // Inst #1967 = OIY + {3, OperandInfo137}, // Inst #1968 = OR + {3, OperandInfo138}, // Inst #1969 = ORK + {5, OperandInfo123}, // Inst #1970 = OY + {6, OperandInfo139}, // Inst #1971 = PACK + {0, NULL}, // Inst #1972 = PALB + {2, OperandInfo175}, // Inst #1973 = PC + {0, NULL}, // Inst #1974 = PCC + {0, NULL}, // Inst #1975 = PCKMO + {4, OperandInfo147}, // Inst #1976 = PFD + {2, OperandInfo154}, // Inst #1977 = PFDRL + {3, OperandInfo342}, // Inst #1978 = PFMF + {0, NULL}, // Inst #1979 = PFPO + {2, OperandInfo144}, // Inst #1980 = PGIN + {2, OperandInfo144}, // Inst #1981 = PGOUT + {5, OperandInfo343}, // Inst #1982 = PKA + {5, OperandInfo343}, // Inst #1983 = PKU + {6, OperandInfo344}, // Inst #1984 = PLO + {2, OperandInfo144}, // Inst #1985 = POPCNT + {3, OperandInfo63}, // Inst #1986 = POPCNTOpt + {3, OperandInfo63}, // Inst #1987 = PPA + {4, OperandInfo210}, // Inst #1988 = PPNO + {0, NULL}, // Inst #1989 = PR + {4, OperandInfo210}, // Inst #1990 = PRNO + {2, OperandInfo247}, // Inst #1991 = PT + {2, OperandInfo345}, // Inst #1992 = PTF + {0, NULL}, // Inst #1993 = PTFF + {2, OperandInfo144}, // Inst #1994 = PTI + {0, NULL}, // Inst #1995 = PTLB + {5, OperandInfo242}, // Inst #1996 = QADTR + {5, OperandInfo346}, // Inst #1997 = QAXTR + {2, OperandInfo175}, // Inst #1998 = QCTRI + {2, OperandInfo175}, // Inst #1999 = QPACI + {2, OperandInfo175}, // Inst #2000 = QSI + {0, NULL}, // Inst #2001 = RCHP + {4, OperandInfo261}, // Inst #2002 = RDP + {3, OperandInfo100}, // Inst #2003 = RDPOpt + {6, OperandInfo347}, // Inst #2004 = RISBG + {6, OperandInfo104}, // Inst #2005 = RISBG32 + {6, OperandInfo347}, // Inst #2006 = RISBGN + {6, OperandInfo348}, // Inst #2007 = RISBHG + {6, OperandInfo349}, // Inst #2008 = RISBLG + {4, OperandInfo350}, // Inst #2009 = RLL + {4, OperandInfo246}, // Inst #2010 = RLLG + {6, OperandInfo347}, // Inst #2011 = RNSBG + {6, OperandInfo347}, // Inst #2012 = ROSBG + {2, OperandInfo175}, // Inst #2013 = RP + {2, OperandInfo247}, // Inst #2014 = RRBE + {2, OperandInfo144}, // Inst #2015 = RRBM + {5, OperandInfo242}, // Inst #2016 = RRDTR + {5, OperandInfo346}, // Inst #2017 = RRXTR + {0, NULL}, // Inst #2018 = RSCH + {6, OperandInfo347}, // Inst #2019 = RXSBG + {5, OperandInfo123}, // Inst #2020 = S + {2, OperandInfo175}, // Inst #2021 = SAC + {2, OperandInfo175}, // Inst #2022 = SACF + {0, NULL}, // Inst #2023 = SAL + {0, NULL}, // Inst #2024 = SAM24 + {0, NULL}, // Inst #2025 = SAM31 + {0, NULL}, // Inst #2026 = SAM64 + {2, OperandInfo351}, // Inst #2027 = SAR + {2, OperandInfo144}, // Inst #2028 = SCCTR + {0, NULL}, // Inst #2029 = SCHM + {2, OperandInfo175}, // Inst #2030 = SCK + {2, OperandInfo175}, // Inst #2031 = SCKC + {0, NULL}, // Inst #2032 = SCKPF + {5, OperandInfo124}, // Inst #2033 = SD + {5, OperandInfo124}, // Inst #2034 = SDB + {3, OperandInfo125}, // Inst #2035 = SDBR + {3, OperandInfo125}, // Inst #2036 = SDR + {3, OperandInfo126}, // Inst #2037 = SDTR + {4, OperandInfo127}, // Inst #2038 = SDTRA + {5, OperandInfo128}, // Inst #2039 = SE + {5, OperandInfo128}, // Inst #2040 = SEB + {3, OperandInfo129}, // Inst #2041 = SEBR + {5, OperandInfo352}, // Inst #2042 = SELFHR + {4, OperandInfo353}, // Inst #2043 = SELFHRAsm + {3, OperandInfo134}, // Inst #2044 = SELFHRAsmE + {3, OperandInfo134}, // Inst #2045 = SELFHRAsmH + {3, OperandInfo134}, // Inst #2046 = SELFHRAsmHE + {3, OperandInfo134}, // Inst #2047 = SELFHRAsmL + {3, OperandInfo134}, // Inst #2048 = SELFHRAsmLE + {3, OperandInfo134}, // Inst #2049 = SELFHRAsmLH + {3, OperandInfo134}, // Inst #2050 = SELFHRAsmM + {3, OperandInfo134}, // Inst #2051 = SELFHRAsmNE + {3, OperandInfo134}, // Inst #2052 = SELFHRAsmNH + {3, OperandInfo134}, // Inst #2053 = SELFHRAsmNHE + {3, OperandInfo134}, // Inst #2054 = SELFHRAsmNL + {3, OperandInfo134}, // Inst #2055 = SELFHRAsmNLE + {3, OperandInfo134}, // Inst #2056 = SELFHRAsmNLH + {3, OperandInfo134}, // Inst #2057 = SELFHRAsmNM + {3, OperandInfo134}, // Inst #2058 = SELFHRAsmNO + {3, OperandInfo134}, // Inst #2059 = SELFHRAsmNP + {3, OperandInfo134}, // Inst #2060 = SELFHRAsmNZ + {3, OperandInfo134}, // Inst #2061 = SELFHRAsmO + {3, OperandInfo134}, // Inst #2062 = SELFHRAsmP + {3, OperandInfo134}, // Inst #2063 = SELFHRAsmZ + {5, OperandInfo109}, // Inst #2064 = SELGR + {4, OperandInfo261}, // Inst #2065 = SELGRAsm + {3, OperandInfo100}, // Inst #2066 = SELGRAsmE + {3, OperandInfo100}, // Inst #2067 = SELGRAsmH + {3, OperandInfo100}, // Inst #2068 = SELGRAsmHE + {3, OperandInfo100}, // Inst #2069 = SELGRAsmL + {3, OperandInfo100}, // Inst #2070 = SELGRAsmLE + {3, OperandInfo100}, // Inst #2071 = SELGRAsmLH + {3, OperandInfo100}, // Inst #2072 = SELGRAsmM + {3, OperandInfo100}, // Inst #2073 = SELGRAsmNE + {3, OperandInfo100}, // Inst #2074 = SELGRAsmNH + {3, OperandInfo100}, // Inst #2075 = SELGRAsmNHE + {3, OperandInfo100}, // Inst #2076 = SELGRAsmNL + {3, OperandInfo100}, // Inst #2077 = SELGRAsmNLE + {3, OperandInfo100}, // Inst #2078 = SELGRAsmNLH + {3, OperandInfo100}, // Inst #2079 = SELGRAsmNM + {3, OperandInfo100}, // Inst #2080 = SELGRAsmNO + {3, OperandInfo100}, // Inst #2081 = SELGRAsmNP + {3, OperandInfo100}, // Inst #2082 = SELGRAsmNZ + {3, OperandInfo100}, // Inst #2083 = SELGRAsmO + {3, OperandInfo100}, // Inst #2084 = SELGRAsmP + {3, OperandInfo100}, // Inst #2085 = SELGRAsmZ + {5, OperandInfo108}, // Inst #2086 = SELR + {4, OperandInfo354}, // Inst #2087 = SELRAsm + {3, OperandInfo138}, // Inst #2088 = SELRAsmE + {3, OperandInfo138}, // Inst #2089 = SELRAsmH + {3, OperandInfo138}, // Inst #2090 = SELRAsmHE + {3, OperandInfo138}, // Inst #2091 = SELRAsmL + {3, OperandInfo138}, // Inst #2092 = SELRAsmLE + {3, OperandInfo138}, // Inst #2093 = SELRAsmLH + {3, OperandInfo138}, // Inst #2094 = SELRAsmM + {3, OperandInfo138}, // Inst #2095 = SELRAsmNE + {3, OperandInfo138}, // Inst #2096 = SELRAsmNH + {3, OperandInfo138}, // Inst #2097 = SELRAsmNHE + {3, OperandInfo138}, // Inst #2098 = SELRAsmNL + {3, OperandInfo138}, // Inst #2099 = SELRAsmNLE + {3, OperandInfo138}, // Inst #2100 = SELRAsmNLH + {3, OperandInfo138}, // Inst #2101 = SELRAsmNM + {3, OperandInfo138}, // Inst #2102 = SELRAsmNO + {3, OperandInfo138}, // Inst #2103 = SELRAsmNP + {3, OperandInfo138}, // Inst #2104 = SELRAsmNZ + {3, OperandInfo138}, // Inst #2105 = SELRAsmO + {3, OperandInfo138}, // Inst #2106 = SELRAsmP + {3, OperandInfo138}, // Inst #2107 = SELRAsmZ + {3, OperandInfo129}, // Inst #2108 = SER + {1, OperandInfo248}, // Inst #2109 = SFASR + {1, OperandInfo248}, // Inst #2110 = SFPC + {5, OperandInfo131}, // Inst #2111 = SG + {5, OperandInfo131}, // Inst #2112 = SGF + {3, OperandInfo132}, // Inst #2113 = SGFR + {5, OperandInfo131}, // Inst #2114 = SGH + {3, OperandInfo133}, // Inst #2115 = SGR + {3, OperandInfo100}, // Inst #2116 = SGRK + {5, OperandInfo123}, // Inst #2117 = SH + {3, OperandInfo134}, // Inst #2118 = SHHHR + {3, OperandInfo135}, // Inst #2119 = SHHLR + {5, OperandInfo123}, // Inst #2120 = SHY + {2, OperandInfo175}, // Inst #2121 = SIE + {2, OperandInfo175}, // Inst #2122 = SIGA + {4, OperandInfo194}, // Inst #2123 = SIGP + {5, OperandInfo123}, // Inst #2124 = SL + {4, OperandInfo355}, // Inst #2125 = SLA + {4, OperandInfo246}, // Inst #2126 = SLAG + {4, OperandInfo350}, // Inst #2127 = SLAK + {5, OperandInfo123}, // Inst #2128 = SLB + {5, OperandInfo131}, // Inst #2129 = SLBG + {3, OperandInfo133}, // Inst #2130 = SLBGR + {3, OperandInfo137}, // Inst #2131 = SLBR + {4, OperandInfo356}, // Inst #2132 = SLDA + {4, OperandInfo356}, // Inst #2133 = SLDL + {5, OperandInfo44}, // Inst #2134 = SLDT + {3, OperandInfo130}, // Inst #2135 = SLFI + {5, OperandInfo131}, // Inst #2136 = SLG + {5, OperandInfo131}, // Inst #2137 = SLGF + {3, OperandInfo83}, // Inst #2138 = SLGFI + {3, OperandInfo132}, // Inst #2139 = SLGFR + {3, OperandInfo133}, // Inst #2140 = SLGR + {3, OperandInfo100}, // Inst #2141 = SLGRK + {3, OperandInfo134}, // Inst #2142 = SLHHHR + {3, OperandInfo135}, // Inst #2143 = SLHHLR + {4, OperandInfo355}, // Inst #2144 = SLL + {4, OperandInfo246}, // Inst #2145 = SLLG + {4, OperandInfo350}, // Inst #2146 = SLLK + {3, OperandInfo137}, // Inst #2147 = SLR + {3, OperandInfo138}, // Inst #2148 = SLRK + {5, OperandInfo357}, // Inst #2149 = SLXT + {5, OperandInfo123}, // Inst #2150 = SLY + {4, OperandInfo210}, // Inst #2151 = SORTL + {6, OperandInfo139}, // Inst #2152 = SP + {2, OperandInfo144}, // Inst #2153 = SPCTR + {2, OperandInfo175}, // Inst #2154 = SPKA + {1, OperandInfo248}, // Inst #2155 = SPM + {2, OperandInfo175}, // Inst #2156 = SPT + {2, OperandInfo175}, // Inst #2157 = SPX + {4, OperandInfo163}, // Inst #2158 = SQD + {4, OperandInfo163}, // Inst #2159 = SQDB + {2, OperandInfo93}, // Inst #2160 = SQDBR + {2, OperandInfo93}, // Inst #2161 = SQDR + {4, OperandInfo170}, // Inst #2162 = SQE + {4, OperandInfo170}, // Inst #2163 = SQEB + {2, OperandInfo94}, // Inst #2164 = SQEBR + {2, OperandInfo94}, // Inst #2165 = SQER + {2, OperandInfo95}, // Inst #2166 = SQXBR + {2, OperandInfo95}, // Inst #2167 = SQXR + {3, OperandInfo137}, // Inst #2168 = SR + {4, OperandInfo355}, // Inst #2169 = SRA + {4, OperandInfo246}, // Inst #2170 = SRAG + {4, OperandInfo350}, // Inst #2171 = SRAK + {4, OperandInfo356}, // Inst #2172 = SRDA + {4, OperandInfo356}, // Inst #2173 = SRDL + {5, OperandInfo44}, // Inst #2174 = SRDT + {3, OperandInfo138}, // Inst #2175 = SRK + {4, OperandInfo355}, // Inst #2176 = SRL + {4, OperandInfo246}, // Inst #2177 = SRLG + {4, OperandInfo350}, // Inst #2178 = SRLK + {2, OperandInfo358}, // Inst #2179 = SRNM + {2, OperandInfo358}, // Inst #2180 = SRNMB + {2, OperandInfo358}, // Inst #2181 = SRNMT + {6, OperandInfo359}, // Inst #2182 = SRP + {4, OperandInfo219}, // Inst #2183 = SRST + {4, OperandInfo219}, // Inst #2184 = SRSTU + {5, OperandInfo357}, // Inst #2185 = SRXT + {1, OperandInfo82}, // Inst #2186 = SSAIR + {1, OperandInfo248}, // Inst #2187 = SSAR + {2, OperandInfo175}, // Inst #2188 = SSCH + {3, OperandInfo360}, // Inst #2189 = SSKE + {2, OperandInfo247}, // Inst #2190 = SSKEOpt + {2, OperandInfo175}, // Inst #2191 = SSM + {4, OperandInfo162}, // Inst #2192 = ST + {4, OperandInfo287}, // Inst #2193 = STAM + {4, OperandInfo287}, // Inst #2194 = STAMY + {2, OperandInfo175}, // Inst #2195 = STAP + {2, OperandInfo175}, // Inst #2196 = STBEAR + {4, OperandInfo162}, // Inst #2197 = STC + {4, OperandInfo199}, // Inst #2198 = STCH + {2, OperandInfo175}, // Inst #2199 = STCK + {2, OperandInfo175}, // Inst #2200 = STCKC + {2, OperandInfo175}, // Inst #2201 = STCKE + {2, OperandInfo175}, // Inst #2202 = STCKF + {4, OperandInfo204}, // Inst #2203 = STCM + {4, OperandInfo213}, // Inst #2204 = STCMH + {4, OperandInfo204}, // Inst #2205 = STCMY + {2, OperandInfo175}, // Inst #2206 = STCPS + {2, OperandInfo175}, // Inst #2207 = STCRW + {4, OperandInfo290}, // Inst #2208 = STCTG + {4, OperandInfo290}, // Inst #2209 = STCTL + {4, OperandInfo162}, // Inst #2210 = STCY + {4, OperandInfo163}, // Inst #2211 = STD + {4, OperandInfo163}, // Inst #2212 = STDY + {4, OperandInfo170}, // Inst #2213 = STE + {4, OperandInfo170}, // Inst #2214 = STEY + {4, OperandInfo199}, // Inst #2215 = STFH + {2, OperandInfo175}, // Inst #2216 = STFL + {2, OperandInfo175}, // Inst #2217 = STFLE + {2, OperandInfo175}, // Inst #2218 = STFPC + {4, OperandInfo45}, // Inst #2219 = STG + {2, OperandInfo188}, // Inst #2220 = STGRL + {4, OperandInfo45}, // Inst #2221 = STGSC + {4, OperandInfo162}, // Inst #2222 = STH + {4, OperandInfo199}, // Inst #2223 = STHH + {2, OperandInfo202}, // Inst #2224 = STHRL + {4, OperandInfo162}, // Inst #2225 = STHY + {2, OperandInfo175}, // Inst #2226 = STIDP + {4, OperandInfo216}, // Inst #2227 = STM + {4, OperandInfo194}, // Inst #2228 = STMG + {4, OperandInfo298}, // Inst #2229 = STMH + {4, OperandInfo216}, // Inst #2230 = STMY + {3, OperandInfo116}, // Inst #2231 = STNSM + {5, OperandInfo361}, // Inst #2232 = STOC + {4, OperandInfo55}, // Inst #2233 = STOCAsm + {3, OperandInfo220}, // Inst #2234 = STOCAsmE + {3, OperandInfo220}, // Inst #2235 = STOCAsmH + {3, OperandInfo220}, // Inst #2236 = STOCAsmHE + {3, OperandInfo220}, // Inst #2237 = STOCAsmL + {3, OperandInfo220}, // Inst #2238 = STOCAsmLE + {3, OperandInfo220}, // Inst #2239 = STOCAsmLH + {3, OperandInfo220}, // Inst #2240 = STOCAsmM + {3, OperandInfo220}, // Inst #2241 = STOCAsmNE + {3, OperandInfo220}, // Inst #2242 = STOCAsmNH + {3, OperandInfo220}, // Inst #2243 = STOCAsmNHE + {3, OperandInfo220}, // Inst #2244 = STOCAsmNL + {3, OperandInfo220}, // Inst #2245 = STOCAsmNLE + {3, OperandInfo220}, // Inst #2246 = STOCAsmNLH + {3, OperandInfo220}, // Inst #2247 = STOCAsmNM + {3, OperandInfo220}, // Inst #2248 = STOCAsmNO + {3, OperandInfo220}, // Inst #2249 = STOCAsmNP + {3, OperandInfo220}, // Inst #2250 = STOCAsmNZ + {3, OperandInfo220}, // Inst #2251 = STOCAsmO + {3, OperandInfo220}, // Inst #2252 = STOCAsmP + {3, OperandInfo220}, // Inst #2253 = STOCAsmZ + {5, OperandInfo362}, // Inst #2254 = STOCFH + {4, OperandInfo363}, // Inst #2255 = STOCFHAsm + {3, OperandInfo364}, // Inst #2256 = STOCFHAsmE + {3, OperandInfo364}, // Inst #2257 = STOCFHAsmH + {3, OperandInfo364}, // Inst #2258 = STOCFHAsmHE + {3, OperandInfo364}, // Inst #2259 = STOCFHAsmL + {3, OperandInfo364}, // Inst #2260 = STOCFHAsmLE + {3, OperandInfo364}, // Inst #2261 = STOCFHAsmLH + {3, OperandInfo364}, // Inst #2262 = STOCFHAsmM + {3, OperandInfo364}, // Inst #2263 = STOCFHAsmNE + {3, OperandInfo364}, // Inst #2264 = STOCFHAsmNH + {3, OperandInfo364}, // Inst #2265 = STOCFHAsmNHE + {3, OperandInfo364}, // Inst #2266 = STOCFHAsmNL + {3, OperandInfo364}, // Inst #2267 = STOCFHAsmNLE + {3, OperandInfo364}, // Inst #2268 = STOCFHAsmNLH + {3, OperandInfo364}, // Inst #2269 = STOCFHAsmNM + {3, OperandInfo364}, // Inst #2270 = STOCFHAsmNO + {3, OperandInfo364}, // Inst #2271 = STOCFHAsmNP + {3, OperandInfo364}, // Inst #2272 = STOCFHAsmNZ + {3, OperandInfo364}, // Inst #2273 = STOCFHAsmO + {3, OperandInfo364}, // Inst #2274 = STOCFHAsmP + {3, OperandInfo364}, // Inst #2275 = STOCFHAsmZ + {5, OperandInfo365}, // Inst #2276 = STOCG + {4, OperandInfo56}, // Inst #2277 = STOCGAsm + {3, OperandInfo212}, // Inst #2278 = STOCGAsmE + {3, OperandInfo212}, // Inst #2279 = STOCGAsmH + {3, OperandInfo212}, // Inst #2280 = STOCGAsmHE + {3, OperandInfo212}, // Inst #2281 = STOCGAsmL + {3, OperandInfo212}, // Inst #2282 = STOCGAsmLE + {3, OperandInfo212}, // Inst #2283 = STOCGAsmLH + {3, OperandInfo212}, // Inst #2284 = STOCGAsmM + {3, OperandInfo212}, // Inst #2285 = STOCGAsmNE + {3, OperandInfo212}, // Inst #2286 = STOCGAsmNH + {3, OperandInfo212}, // Inst #2287 = STOCGAsmNHE + {3, OperandInfo212}, // Inst #2288 = STOCGAsmNL + {3, OperandInfo212}, // Inst #2289 = STOCGAsmNLE + {3, OperandInfo212}, // Inst #2290 = STOCGAsmNLH + {3, OperandInfo212}, // Inst #2291 = STOCGAsmNM + {3, OperandInfo212}, // Inst #2292 = STOCGAsmNO + {3, OperandInfo212}, // Inst #2293 = STOCGAsmNP + {3, OperandInfo212}, // Inst #2294 = STOCGAsmNZ + {3, OperandInfo212}, // Inst #2295 = STOCGAsmO + {3, OperandInfo212}, // Inst #2296 = STOCGAsmP + {3, OperandInfo212}, // Inst #2297 = STOCGAsmZ + {3, OperandInfo116}, // Inst #2298 = STOSM + {4, OperandInfo84}, // Inst #2299 = STPQ + {2, OperandInfo175}, // Inst #2300 = STPT + {2, OperandInfo175}, // Inst #2301 = STPX + {4, OperandInfo288}, // Inst #2302 = STRAG + {2, OperandInfo202}, // Inst #2303 = STRL + {4, OperandInfo162}, // Inst #2304 = STRV + {4, OperandInfo45}, // Inst #2305 = STRVG + {4, OperandInfo162}, // Inst #2306 = STRVH + {2, OperandInfo175}, // Inst #2307 = STSCH + {2, OperandInfo175}, // Inst #2308 = STSI + {2, OperandInfo247}, // Inst #2309 = STURA + {2, OperandInfo144}, // Inst #2310 = STURG + {4, OperandInfo162}, // Inst #2311 = STY + {5, OperandInfo128}, // Inst #2312 = SU + {3, OperandInfo129}, // Inst #2313 = SUR + {1, OperandInfo3}, // Inst #2314 = SVC + {5, OperandInfo124}, // Inst #2315 = SW + {3, OperandInfo125}, // Inst #2316 = SWR + {3, OperandInfo140}, // Inst #2317 = SXBR + {3, OperandInfo140}, // Inst #2318 = SXR + {3, OperandInfo141}, // Inst #2319 = SXTR + {4, OperandInfo142}, // Inst #2320 = SXTRA + {5, OperandInfo123}, // Inst #2321 = SY + {2, OperandInfo175}, // Inst #2322 = TABORT + {0, NULL}, // Inst #2323 = TAM + {2, OperandInfo351}, // Inst #2324 = TAR + {2, OperandInfo144}, // Inst #2325 = TB + {3, OperandInfo253}, // Inst #2326 = TBDR + {3, OperandInfo366}, // Inst #2327 = TBEDR + {3, OperandInfo116}, // Inst #2328 = TBEGIN + {3, OperandInfo116}, // Inst #2329 = TBEGINC + {4, OperandInfo163}, // Inst #2330 = TCDB + {4, OperandInfo170}, // Inst #2331 = TCEB + {4, OperandInfo96}, // Inst #2332 = TCXB + {4, OperandInfo163}, // Inst #2333 = TDCDT + {4, OperandInfo170}, // Inst #2334 = TDCET + {4, OperandInfo96}, // Inst #2335 = TDCXT + {4, OperandInfo163}, // Inst #2336 = TDGDT + {4, OperandInfo170}, // Inst #2337 = TDGET + {4, OperandInfo96}, // Inst #2338 = TDGXT + {0, NULL}, // Inst #2339 = TEND + {2, OperandInfo291}, // Inst #2340 = THDER + {2, OperandInfo93}, // Inst #2341 = THDR + {3, OperandInfo116}, // Inst #2342 = TM + {2, OperandInfo205}, // Inst #2343 = TMHH + {2, OperandInfo205}, // Inst #2344 = TMHL + {2, OperandInfo180}, // Inst #2345 = TMLH + {2, OperandInfo180}, // Inst #2346 = TMLL + {3, OperandInfo116}, // Inst #2347 = TMY + {3, OperandInfo367}, // Inst #2348 = TP + {2, OperandInfo175}, // Inst #2349 = TPI + {4, OperandInfo288}, // Inst #2350 = TPROT + {5, OperandInfo209}, // Inst #2351 = TR + {4, OperandInfo216}, // Inst #2352 = TRACE + {4, OperandInfo194}, // Inst #2353 = TRACG + {0, NULL}, // Inst #2354 = TRAP2 + {2, OperandInfo175}, // Inst #2355 = TRAP4 + {4, OperandInfo368}, // Inst #2356 = TRE + {5, OperandInfo369}, // Inst #2357 = TROO + {4, OperandInfo368}, // Inst #2358 = TROOOpt + {5, OperandInfo369}, // Inst #2359 = TROT + {4, OperandInfo368}, // Inst #2360 = TROTOpt + {5, OperandInfo209}, // Inst #2361 = TRT + {4, OperandInfo370}, // Inst #2362 = TRTE + {3, OperandInfo371}, // Inst #2363 = TRTEOpt + {5, OperandInfo369}, // Inst #2364 = TRTO + {4, OperandInfo368}, // Inst #2365 = TRTOOpt + {5, OperandInfo209}, // Inst #2366 = TRTR + {4, OperandInfo370}, // Inst #2367 = TRTRE + {3, OperandInfo371}, // Inst #2368 = TRTREOpt + {5, OperandInfo369}, // Inst #2369 = TRTT + {4, OperandInfo368}, // Inst #2370 = TRTTOpt + {2, OperandInfo175}, // Inst #2371 = TS + {2, OperandInfo175}, // Inst #2372 = TSCH + {6, OperandInfo139}, // Inst #2373 = UNPK + {5, OperandInfo209}, // Inst #2374 = UNPKA + {5, OperandInfo209}, // Inst #2375 = UNPKU + {0, NULL}, // Inst #2376 = UPT + {4, OperandInfo372}, // Inst #2377 = VA + {3, OperandInfo373}, // Inst #2378 = VAB + {5, OperandInfo374}, // Inst #2379 = VAC + {4, OperandInfo372}, // Inst #2380 = VACC + {3, OperandInfo373}, // Inst #2381 = VACCB + {5, OperandInfo374}, // Inst #2382 = VACCC + {4, OperandInfo375}, // Inst #2383 = VACCCQ + {3, OperandInfo373}, // Inst #2384 = VACCF + {3, OperandInfo373}, // Inst #2385 = VACCG + {3, OperandInfo373}, // Inst #2386 = VACCH + {3, OperandInfo373}, // Inst #2387 = VACCQ + {4, OperandInfo375}, // Inst #2388 = VACQ + {3, OperandInfo373}, // Inst #2389 = VAF + {3, OperandInfo373}, // Inst #2390 = VAG + {3, OperandInfo373}, // Inst #2391 = VAH + {5, OperandInfo113}, // Inst #2392 = VAP + {3, OperandInfo373}, // Inst #2393 = VAQ + {4, OperandInfo372}, // Inst #2394 = VAVG + {3, OperandInfo373}, // Inst #2395 = VAVGB + {3, OperandInfo373}, // Inst #2396 = VAVGF + {3, OperandInfo373}, // Inst #2397 = VAVGG + {3, OperandInfo373}, // Inst #2398 = VAVGH + {4, OperandInfo372}, // Inst #2399 = VAVGL + {3, OperandInfo373}, // Inst #2400 = VAVGLB + {3, OperandInfo373}, // Inst #2401 = VAVGLF + {3, OperandInfo373}, // Inst #2402 = VAVGLG + {3, OperandInfo373}, // Inst #2403 = VAVGLH + {3, OperandInfo373}, // Inst #2404 = VBPERM + {5, OperandInfo376}, // Inst #2405 = VCDG + {4, OperandInfo377}, // Inst #2406 = VCDGB + {5, OperandInfo376}, // Inst #2407 = VCDLG + {4, OperandInfo377}, // Inst #2408 = VCDLGB + {4, OperandInfo377}, // Inst #2409 = VCEFB + {4, OperandInfo377}, // Inst #2410 = VCELFB + {5, OperandInfo113}, // Inst #2411 = VCEQ + {3, OperandInfo373}, // Inst #2412 = VCEQB + {3, OperandInfo373}, // Inst #2413 = VCEQBS + {3, OperandInfo373}, // Inst #2414 = VCEQF + {3, OperandInfo373}, // Inst #2415 = VCEQFS + {3, OperandInfo373}, // Inst #2416 = VCEQG + {3, OperandInfo373}, // Inst #2417 = VCEQGS + {3, OperandInfo373}, // Inst #2418 = VCEQH + {3, OperandInfo373}, // Inst #2419 = VCEQHS + {4, OperandInfo377}, // Inst #2420 = VCFEB + {4, OperandInfo377}, // Inst #2421 = VCFN + {5, OperandInfo376}, // Inst #2422 = VCFPL + {5, OperandInfo376}, // Inst #2423 = VCFPS + {5, OperandInfo376}, // Inst #2424 = VCGD + {4, OperandInfo377}, // Inst #2425 = VCGDB + {5, OperandInfo113}, // Inst #2426 = VCH + {3, OperandInfo373}, // Inst #2427 = VCHB + {3, OperandInfo373}, // Inst #2428 = VCHBS + {3, OperandInfo373}, // Inst #2429 = VCHF + {3, OperandInfo373}, // Inst #2430 = VCHFS + {3, OperandInfo373}, // Inst #2431 = VCHG + {3, OperandInfo373}, // Inst #2432 = VCHGS + {3, OperandInfo373}, // Inst #2433 = VCHH + {3, OperandInfo373}, // Inst #2434 = VCHHS + {5, OperandInfo113}, // Inst #2435 = VCHL + {3, OperandInfo373}, // Inst #2436 = VCHLB + {3, OperandInfo373}, // Inst #2437 = VCHLBS + {3, OperandInfo373}, // Inst #2438 = VCHLF + {3, OperandInfo373}, // Inst #2439 = VCHLFS + {3, OperandInfo373}, // Inst #2440 = VCHLG + {3, OperandInfo373}, // Inst #2441 = VCHLGS + {3, OperandInfo373}, // Inst #2442 = VCHLH + {3, OperandInfo373}, // Inst #2443 = VCHLHS + {3, OperandInfo373}, // Inst #2444 = VCKSM + {4, OperandInfo377}, // Inst #2445 = VCLFEB + {4, OperandInfo377}, // Inst #2446 = VCLFNH + {4, OperandInfo377}, // Inst #2447 = VCLFNL + {5, OperandInfo376}, // Inst #2448 = VCLFP + {5, OperandInfo376}, // Inst #2449 = VCLGD + {4, OperandInfo377}, // Inst #2450 = VCLGDB + {3, OperandInfo378}, // Inst #2451 = VCLZ + {2, OperandInfo379}, // Inst #2452 = VCLZB + {3, OperandInfo378}, // Inst #2453 = VCLZDP + {2, OperandInfo379}, // Inst #2454 = VCLZF + {2, OperandInfo379}, // Inst #2455 = VCLZG + {2, OperandInfo379}, // Inst #2456 = VCLZH + {4, OperandInfo377}, // Inst #2457 = VCNF + {3, OperandInfo378}, // Inst #2458 = VCP + {5, OperandInfo113}, // Inst #2459 = VCRNF + {5, OperandInfo376}, // Inst #2460 = VCSFP + {4, OperandInfo372}, // Inst #2461 = VCSPH + {3, OperandInfo378}, // Inst #2462 = VCTZ + {2, OperandInfo379}, // Inst #2463 = VCTZB + {2, OperandInfo379}, // Inst #2464 = VCTZF + {2, OperandInfo379}, // Inst #2465 = VCTZG + {2, OperandInfo379}, // Inst #2466 = VCTZH + {3, OperandInfo380}, // Inst #2467 = VCVB + {3, OperandInfo381}, // Inst #2468 = VCVBG + {4, OperandInfo382}, // Inst #2469 = VCVBGOpt + {4, OperandInfo383}, // Inst #2470 = VCVBOpt + {4, OperandInfo384}, // Inst #2471 = VCVD + {4, OperandInfo385}, // Inst #2472 = VCVDG + {5, OperandInfo113}, // Inst #2473 = VDP + {3, OperandInfo378}, // Inst #2474 = VEC + {2, OperandInfo379}, // Inst #2475 = VECB + {2, OperandInfo379}, // Inst #2476 = VECF + {2, OperandInfo379}, // Inst #2477 = VECG + {2, OperandInfo379}, // Inst #2478 = VECH + {3, OperandInfo378}, // Inst #2479 = VECL + {2, OperandInfo379}, // Inst #2480 = VECLB + {2, OperandInfo379}, // Inst #2481 = VECLF + {2, OperandInfo379}, // Inst #2482 = VECLG + {2, OperandInfo379}, // Inst #2483 = VECLH + {6, OperandInfo386}, // Inst #2484 = VERIM + {5, OperandInfo387}, // Inst #2485 = VERIMB + {5, OperandInfo387}, // Inst #2486 = VERIMF + {5, OperandInfo387}, // Inst #2487 = VERIMG + {5, OperandInfo387}, // Inst #2488 = VERIMH + {5, OperandInfo388}, // Inst #2489 = VERLL + {4, OperandInfo389}, // Inst #2490 = VERLLB + {4, OperandInfo389}, // Inst #2491 = VERLLF + {4, OperandInfo389}, // Inst #2492 = VERLLG + {4, OperandInfo389}, // Inst #2493 = VERLLH + {4, OperandInfo372}, // Inst #2494 = VERLLV + {3, OperandInfo373}, // Inst #2495 = VERLLVB + {3, OperandInfo373}, // Inst #2496 = VERLLVF + {3, OperandInfo373}, // Inst #2497 = VERLLVG + {3, OperandInfo373}, // Inst #2498 = VERLLVH + {5, OperandInfo388}, // Inst #2499 = VESL + {4, OperandInfo389}, // Inst #2500 = VESLB + {4, OperandInfo389}, // Inst #2501 = VESLF + {4, OperandInfo389}, // Inst #2502 = VESLG + {4, OperandInfo389}, // Inst #2503 = VESLH + {4, OperandInfo372}, // Inst #2504 = VESLV + {3, OperandInfo373}, // Inst #2505 = VESLVB + {3, OperandInfo373}, // Inst #2506 = VESLVF + {3, OperandInfo373}, // Inst #2507 = VESLVG + {3, OperandInfo373}, // Inst #2508 = VESLVH + {5, OperandInfo388}, // Inst #2509 = VESRA + {4, OperandInfo389}, // Inst #2510 = VESRAB + {4, OperandInfo389}, // Inst #2511 = VESRAF + {4, OperandInfo389}, // Inst #2512 = VESRAG + {4, OperandInfo389}, // Inst #2513 = VESRAH + {4, OperandInfo372}, // Inst #2514 = VESRAV + {3, OperandInfo373}, // Inst #2515 = VESRAVB + {3, OperandInfo373}, // Inst #2516 = VESRAVF + {3, OperandInfo373}, // Inst #2517 = VESRAVG + {3, OperandInfo373}, // Inst #2518 = VESRAVH + {5, OperandInfo388}, // Inst #2519 = VESRL + {4, OperandInfo389}, // Inst #2520 = VESRLB + {4, OperandInfo389}, // Inst #2521 = VESRLF + {4, OperandInfo389}, // Inst #2522 = VESRLG + {4, OperandInfo389}, // Inst #2523 = VESRLH + {4, OperandInfo372}, // Inst #2524 = VESRLV + {3, OperandInfo373}, // Inst #2525 = VESRLVB + {3, OperandInfo373}, // Inst #2526 = VESRLVF + {3, OperandInfo373}, // Inst #2527 = VESRLVG + {3, OperandInfo373}, // Inst #2528 = VESRLVH + {5, OperandInfo113}, // Inst #2529 = VFA + {3, OperandInfo373}, // Inst #2530 = VFADB + {5, OperandInfo113}, // Inst #2531 = VFAE + {4, OperandInfo372}, // Inst #2532 = VFAEB + {4, OperandInfo372}, // Inst #2533 = VFAEBS + {4, OperandInfo372}, // Inst #2534 = VFAEF + {4, OperandInfo372}, // Inst #2535 = VFAEFS + {4, OperandInfo372}, // Inst #2536 = VFAEH + {4, OperandInfo372}, // Inst #2537 = VFAEHS + {4, OperandInfo372}, // Inst #2538 = VFAEZB + {4, OperandInfo372}, // Inst #2539 = VFAEZBS + {4, OperandInfo372}, // Inst #2540 = VFAEZF + {4, OperandInfo372}, // Inst #2541 = VFAEZFS + {4, OperandInfo372}, // Inst #2542 = VFAEZH + {4, OperandInfo372}, // Inst #2543 = VFAEZHS + {3, OperandInfo373}, // Inst #2544 = VFASB + {6, OperandInfo390}, // Inst #2545 = VFCE + {3, OperandInfo373}, // Inst #2546 = VFCEDB + {3, OperandInfo373}, // Inst #2547 = VFCEDBS + {3, OperandInfo373}, // Inst #2548 = VFCESB + {3, OperandInfo373}, // Inst #2549 = VFCESBS + {6, OperandInfo390}, // Inst #2550 = VFCH + {3, OperandInfo373}, // Inst #2551 = VFCHDB + {3, OperandInfo373}, // Inst #2552 = VFCHDBS + {6, OperandInfo390}, // Inst #2553 = VFCHE + {3, OperandInfo373}, // Inst #2554 = VFCHEDB + {3, OperandInfo373}, // Inst #2555 = VFCHEDBS + {3, OperandInfo373}, // Inst #2556 = VFCHESB + {3, OperandInfo373}, // Inst #2557 = VFCHESBS + {3, OperandInfo373}, // Inst #2558 = VFCHSB + {3, OperandInfo373}, // Inst #2559 = VFCHSBS + {5, OperandInfo113}, // Inst #2560 = VFD + {3, OperandInfo373}, // Inst #2561 = VFDDB + {3, OperandInfo373}, // Inst #2562 = VFDSB + {5, OperandInfo113}, // Inst #2563 = VFEE + {4, OperandInfo372}, // Inst #2564 = VFEEB + {3, OperandInfo373}, // Inst #2565 = VFEEBS + {4, OperandInfo372}, // Inst #2566 = VFEEF + {3, OperandInfo373}, // Inst #2567 = VFEEFS + {4, OperandInfo372}, // Inst #2568 = VFEEH + {3, OperandInfo373}, // Inst #2569 = VFEEHS + {3, OperandInfo373}, // Inst #2570 = VFEEZB + {3, OperandInfo373}, // Inst #2571 = VFEEZBS + {3, OperandInfo373}, // Inst #2572 = VFEEZF + {3, OperandInfo373}, // Inst #2573 = VFEEZFS + {3, OperandInfo373}, // Inst #2574 = VFEEZH + {3, OperandInfo373}, // Inst #2575 = VFEEZHS + {5, OperandInfo113}, // Inst #2576 = VFENE + {4, OperandInfo372}, // Inst #2577 = VFENEB + {3, OperandInfo373}, // Inst #2578 = VFENEBS + {4, OperandInfo372}, // Inst #2579 = VFENEF + {3, OperandInfo373}, // Inst #2580 = VFENEFS + {4, OperandInfo372}, // Inst #2581 = VFENEH + {3, OperandInfo373}, // Inst #2582 = VFENEHS + {3, OperandInfo373}, // Inst #2583 = VFENEZB + {3, OperandInfo373}, // Inst #2584 = VFENEZBS + {3, OperandInfo373}, // Inst #2585 = VFENEZF + {3, OperandInfo373}, // Inst #2586 = VFENEZFS + {3, OperandInfo373}, // Inst #2587 = VFENEZH + {3, OperandInfo373}, // Inst #2588 = VFENEZHS + {5, OperandInfo376}, // Inst #2589 = VFI + {4, OperandInfo377}, // Inst #2590 = VFIDB + {4, OperandInfo377}, // Inst #2591 = VFISB + {3, OperandInfo373}, // Inst #2592 = VFKEDB + {3, OperandInfo373}, // Inst #2593 = VFKEDBS + {3, OperandInfo373}, // Inst #2594 = VFKESB + {3, OperandInfo373}, // Inst #2595 = VFKESBS + {3, OperandInfo373}, // Inst #2596 = VFKHDB + {3, OperandInfo373}, // Inst #2597 = VFKHDBS + {3, OperandInfo373}, // Inst #2598 = VFKHEDB + {3, OperandInfo373}, // Inst #2599 = VFKHEDBS + {3, OperandInfo373}, // Inst #2600 = VFKHESB + {3, OperandInfo373}, // Inst #2601 = VFKHESBS + {3, OperandInfo373}, // Inst #2602 = VFKHSB + {3, OperandInfo373}, // Inst #2603 = VFKHSBS + {2, OperandInfo379}, // Inst #2604 = VFLCDB + {2, OperandInfo379}, // Inst #2605 = VFLCSB + {4, OperandInfo377}, // Inst #2606 = VFLL + {2, OperandInfo379}, // Inst #2607 = VFLLS + {2, OperandInfo379}, // Inst #2608 = VFLNDB + {2, OperandInfo379}, // Inst #2609 = VFLNSB + {2, OperandInfo379}, // Inst #2610 = VFLPDB + {2, OperandInfo379}, // Inst #2611 = VFLPSB + {5, OperandInfo376}, // Inst #2612 = VFLR + {4, OperandInfo377}, // Inst #2613 = VFLRD + {5, OperandInfo113}, // Inst #2614 = VFM + {6, OperandInfo391}, // Inst #2615 = VFMA + {4, OperandInfo375}, // Inst #2616 = VFMADB + {4, OperandInfo375}, // Inst #2617 = VFMASB + {6, OperandInfo390}, // Inst #2618 = VFMAX + {4, OperandInfo372}, // Inst #2619 = VFMAXDB + {4, OperandInfo372}, // Inst #2620 = VFMAXSB + {3, OperandInfo373}, // Inst #2621 = VFMDB + {6, OperandInfo390}, // Inst #2622 = VFMIN + {4, OperandInfo372}, // Inst #2623 = VFMINDB + {4, OperandInfo372}, // Inst #2624 = VFMINSB + {6, OperandInfo391}, // Inst #2625 = VFMS + {3, OperandInfo373}, // Inst #2626 = VFMSB + {4, OperandInfo375}, // Inst #2627 = VFMSDB + {4, OperandInfo375}, // Inst #2628 = VFMSSB + {6, OperandInfo391}, // Inst #2629 = VFNMA + {4, OperandInfo375}, // Inst #2630 = VFNMADB + {4, OperandInfo375}, // Inst #2631 = VFNMASB + {6, OperandInfo391}, // Inst #2632 = VFNMS + {4, OperandInfo375}, // Inst #2633 = VFNMSDB + {4, OperandInfo375}, // Inst #2634 = VFNMSSB + {5, OperandInfo376}, // Inst #2635 = VFPSO + {3, OperandInfo378}, // Inst #2636 = VFPSODB + {3, OperandInfo378}, // Inst #2637 = VFPSOSB + {5, OperandInfo113}, // Inst #2638 = VFS + {3, OperandInfo373}, // Inst #2639 = VFSDB + {4, OperandInfo377}, // Inst #2640 = VFSQ + {2, OperandInfo379}, // Inst #2641 = VFSQDB + {2, OperandInfo379}, // Inst #2642 = VFSQSB + {3, OperandInfo373}, // Inst #2643 = VFSSB + {5, OperandInfo376}, // Inst #2644 = VFTCI + {3, OperandInfo378}, // Inst #2645 = VFTCIDB + {3, OperandInfo378}, // Inst #2646 = VFTCISB + {2, OperandInfo392}, // Inst #2647 = VGBM + {6, OperandInfo393}, // Inst #2648 = VGEF + {6, OperandInfo393}, // Inst #2649 = VGEG + {4, OperandInfo372}, // Inst #2650 = VGFM + {5, OperandInfo374}, // Inst #2651 = VGFMA + {4, OperandInfo375}, // Inst #2652 = VGFMAB + {4, OperandInfo375}, // Inst #2653 = VGFMAF + {4, OperandInfo375}, // Inst #2654 = VGFMAG + {4, OperandInfo375}, // Inst #2655 = VGFMAH + {3, OperandInfo373}, // Inst #2656 = VGFMB + {3, OperandInfo373}, // Inst #2657 = VGFMF + {3, OperandInfo373}, // Inst #2658 = VGFMG + {3, OperandInfo373}, // Inst #2659 = VGFMH + {4, OperandInfo394}, // Inst #2660 = VGM + {3, OperandInfo395}, // Inst #2661 = VGMB + {3, OperandInfo395}, // Inst #2662 = VGMF + {3, OperandInfo395}, // Inst #2663 = VGMG + {3, OperandInfo395}, // Inst #2664 = VGMH + {4, OperandInfo377}, // Inst #2665 = VISTR + {3, OperandInfo378}, // Inst #2666 = VISTRB + {2, OperandInfo379}, // Inst #2667 = VISTRBS + {3, OperandInfo378}, // Inst #2668 = VISTRF + {2, OperandInfo379}, // Inst #2669 = VISTRFS + {3, OperandInfo378}, // Inst #2670 = VISTRH + {2, OperandInfo379}, // Inst #2671 = VISTRHS + {4, OperandInfo396}, // Inst #2672 = VL + {5, OperandInfo397}, // Inst #2673 = VLAlign + {5, OperandInfo397}, // Inst #2674 = VLBB + {5, OperandInfo397}, // Inst #2675 = VLBR + {4, OperandInfo396}, // Inst #2676 = VLBRF + {4, OperandInfo396}, // Inst #2677 = VLBRG + {4, OperandInfo396}, // Inst #2678 = VLBRH + {4, OperandInfo396}, // Inst #2679 = VLBRQ + {5, OperandInfo397}, // Inst #2680 = VLBRREP + {4, OperandInfo396}, // Inst #2681 = VLBRREPF + {4, OperandInfo396}, // Inst #2682 = VLBRREPG + {4, OperandInfo396}, // Inst #2683 = VLBRREPH + {3, OperandInfo378}, // Inst #2684 = VLC + {2, OperandInfo379}, // Inst #2685 = VLCB + {2, OperandInfo379}, // Inst #2686 = VLCF + {2, OperandInfo379}, // Inst #2687 = VLCG + {2, OperandInfo379}, // Inst #2688 = VLCH + {4, OperandInfo377}, // Inst #2689 = VLDE + {2, OperandInfo379}, // Inst #2690 = VLDEB + {6, OperandInfo398}, // Inst #2691 = VLEB + {6, OperandInfo398}, // Inst #2692 = VLEBRF + {6, OperandInfo398}, // Inst #2693 = VLEBRG + {6, OperandInfo398}, // Inst #2694 = VLEBRH + {5, OperandInfo376}, // Inst #2695 = VLED + {4, OperandInfo377}, // Inst #2696 = VLEDB + {6, OperandInfo398}, // Inst #2697 = VLEF + {6, OperandInfo398}, // Inst #2698 = VLEG + {6, OperandInfo398}, // Inst #2699 = VLEH + {4, OperandInfo399}, // Inst #2700 = VLEIB + {4, OperandInfo399}, // Inst #2701 = VLEIF + {4, OperandInfo399}, // Inst #2702 = VLEIG + {4, OperandInfo399}, // Inst #2703 = VLEIH + {5, OperandInfo397}, // Inst #2704 = VLER + {4, OperandInfo396}, // Inst #2705 = VLERF + {4, OperandInfo396}, // Inst #2706 = VLERG + {4, OperandInfo396}, // Inst #2707 = VLERH + {5, OperandInfo400}, // Inst #2708 = VLGV + {4, OperandInfo401}, // Inst #2709 = VLGVB + {4, OperandInfo401}, // Inst #2710 = VLGVF + {4, OperandInfo401}, // Inst #2711 = VLGVG + {4, OperandInfo401}, // Inst #2712 = VLGVH + {3, OperandInfo395}, // Inst #2713 = VLIP + {4, OperandInfo402}, // Inst #2714 = VLL + {5, OperandInfo397}, // Inst #2715 = VLLEBRZ + {4, OperandInfo396}, // Inst #2716 = VLLEBRZE + {4, OperandInfo396}, // Inst #2717 = VLLEBRZF + {4, OperandInfo396}, // Inst #2718 = VLLEBRZG + {4, OperandInfo396}, // Inst #2719 = VLLEBRZH + {5, OperandInfo397}, // Inst #2720 = VLLEZ + {4, OperandInfo396}, // Inst #2721 = VLLEZB + {4, OperandInfo396}, // Inst #2722 = VLLEZF + {4, OperandInfo396}, // Inst #2723 = VLLEZG + {4, OperandInfo396}, // Inst #2724 = VLLEZH + {4, OperandInfo396}, // Inst #2725 = VLLEZLF + {4, OperandInfo403}, // Inst #2726 = VLM + {5, OperandInfo404}, // Inst #2727 = VLMAlign + {3, OperandInfo378}, // Inst #2728 = VLP + {2, OperandInfo379}, // Inst #2729 = VLPB + {2, OperandInfo379}, // Inst #2730 = VLPF + {2, OperandInfo379}, // Inst #2731 = VLPG + {2, OperandInfo379}, // Inst #2732 = VLPH + {2, OperandInfo379}, // Inst #2733 = VLR + {5, OperandInfo397}, // Inst #2734 = VLREP + {4, OperandInfo396}, // Inst #2735 = VLREPB + {4, OperandInfo396}, // Inst #2736 = VLREPF + {4, OperandInfo396}, // Inst #2737 = VLREPG + {4, OperandInfo396}, // Inst #2738 = VLREPH + {4, OperandInfo405}, // Inst #2739 = VLRL + {4, OperandInfo402}, // Inst #2740 = VLRLR + {6, OperandInfo406}, // Inst #2741 = VLVG + {5, OperandInfo407}, // Inst #2742 = VLVGB + {5, OperandInfo407}, // Inst #2743 = VLVGF + {5, OperandInfo408}, // Inst #2744 = VLVGG + {5, OperandInfo407}, // Inst #2745 = VLVGH + {3, OperandInfo409}, // Inst #2746 = VLVGP + {5, OperandInfo374}, // Inst #2747 = VMAE + {4, OperandInfo375}, // Inst #2748 = VMAEB + {4, OperandInfo375}, // Inst #2749 = VMAEF + {4, OperandInfo375}, // Inst #2750 = VMAEH + {5, OperandInfo374}, // Inst #2751 = VMAH + {4, OperandInfo375}, // Inst #2752 = VMAHB + {4, OperandInfo375}, // Inst #2753 = VMAHF + {4, OperandInfo375}, // Inst #2754 = VMAHH + {5, OperandInfo374}, // Inst #2755 = VMAL + {4, OperandInfo375}, // Inst #2756 = VMALB + {5, OperandInfo374}, // Inst #2757 = VMALE + {4, OperandInfo375}, // Inst #2758 = VMALEB + {4, OperandInfo375}, // Inst #2759 = VMALEF + {4, OperandInfo375}, // Inst #2760 = VMALEH + {4, OperandInfo375}, // Inst #2761 = VMALF + {5, OperandInfo374}, // Inst #2762 = VMALH + {4, OperandInfo375}, // Inst #2763 = VMALHB + {4, OperandInfo375}, // Inst #2764 = VMALHF + {4, OperandInfo375}, // Inst #2765 = VMALHH + {4, OperandInfo375}, // Inst #2766 = VMALHW + {5, OperandInfo374}, // Inst #2767 = VMALO + {4, OperandInfo375}, // Inst #2768 = VMALOB + {4, OperandInfo375}, // Inst #2769 = VMALOF + {4, OperandInfo375}, // Inst #2770 = VMALOH + {5, OperandInfo374}, // Inst #2771 = VMAO + {4, OperandInfo375}, // Inst #2772 = VMAOB + {4, OperandInfo375}, // Inst #2773 = VMAOF + {4, OperandInfo375}, // Inst #2774 = VMAOH + {4, OperandInfo372}, // Inst #2775 = VME + {3, OperandInfo373}, // Inst #2776 = VMEB + {3, OperandInfo373}, // Inst #2777 = VMEF + {3, OperandInfo373}, // Inst #2778 = VMEH + {4, OperandInfo372}, // Inst #2779 = VMH + {3, OperandInfo373}, // Inst #2780 = VMHB + {3, OperandInfo373}, // Inst #2781 = VMHF + {3, OperandInfo373}, // Inst #2782 = VMHH + {4, OperandInfo372}, // Inst #2783 = VML + {3, OperandInfo373}, // Inst #2784 = VMLB + {4, OperandInfo372}, // Inst #2785 = VMLE + {3, OperandInfo373}, // Inst #2786 = VMLEB + {3, OperandInfo373}, // Inst #2787 = VMLEF + {3, OperandInfo373}, // Inst #2788 = VMLEH + {3, OperandInfo373}, // Inst #2789 = VMLF + {4, OperandInfo372}, // Inst #2790 = VMLH + {3, OperandInfo373}, // Inst #2791 = VMLHB + {3, OperandInfo373}, // Inst #2792 = VMLHF + {3, OperandInfo373}, // Inst #2793 = VMLHH + {3, OperandInfo373}, // Inst #2794 = VMLHW + {4, OperandInfo372}, // Inst #2795 = VMLO + {3, OperandInfo373}, // Inst #2796 = VMLOB + {3, OperandInfo373}, // Inst #2797 = VMLOF + {3, OperandInfo373}, // Inst #2798 = VMLOH + {4, OperandInfo372}, // Inst #2799 = VMN + {3, OperandInfo373}, // Inst #2800 = VMNB + {3, OperandInfo373}, // Inst #2801 = VMNF + {3, OperandInfo373}, // Inst #2802 = VMNG + {3, OperandInfo373}, // Inst #2803 = VMNH + {4, OperandInfo372}, // Inst #2804 = VMNL + {3, OperandInfo373}, // Inst #2805 = VMNLB + {3, OperandInfo373}, // Inst #2806 = VMNLF + {3, OperandInfo373}, // Inst #2807 = VMNLG + {3, OperandInfo373}, // Inst #2808 = VMNLH + {4, OperandInfo372}, // Inst #2809 = VMO + {3, OperandInfo373}, // Inst #2810 = VMOB + {3, OperandInfo373}, // Inst #2811 = VMOF + {3, OperandInfo373}, // Inst #2812 = VMOH + {5, OperandInfo113}, // Inst #2813 = VMP + {4, OperandInfo372}, // Inst #2814 = VMRH + {3, OperandInfo373}, // Inst #2815 = VMRHB + {3, OperandInfo373}, // Inst #2816 = VMRHF + {3, OperandInfo373}, // Inst #2817 = VMRHG + {3, OperandInfo373}, // Inst #2818 = VMRHH + {4, OperandInfo372}, // Inst #2819 = VMRL + {3, OperandInfo373}, // Inst #2820 = VMRLB + {3, OperandInfo373}, // Inst #2821 = VMRLF + {3, OperandInfo373}, // Inst #2822 = VMRLG + {3, OperandInfo373}, // Inst #2823 = VMRLH + {6, OperandInfo391}, // Inst #2824 = VMSL + {5, OperandInfo374}, // Inst #2825 = VMSLG + {5, OperandInfo113}, // Inst #2826 = VMSP + {4, OperandInfo372}, // Inst #2827 = VMX + {3, OperandInfo373}, // Inst #2828 = VMXB + {3, OperandInfo373}, // Inst #2829 = VMXF + {3, OperandInfo373}, // Inst #2830 = VMXG + {3, OperandInfo373}, // Inst #2831 = VMXH + {4, OperandInfo372}, // Inst #2832 = VMXL + {3, OperandInfo373}, // Inst #2833 = VMXLB + {3, OperandInfo373}, // Inst #2834 = VMXLF + {3, OperandInfo373}, // Inst #2835 = VMXLG + {3, OperandInfo373}, // Inst #2836 = VMXLH + {3, OperandInfo373}, // Inst #2837 = VN + {3, OperandInfo373}, // Inst #2838 = VNC + {3, OperandInfo373}, // Inst #2839 = VNN + {3, OperandInfo373}, // Inst #2840 = VNO + {3, OperandInfo373}, // Inst #2841 = VNX + {3, OperandInfo373}, // Inst #2842 = VO + {3, OperandInfo373}, // Inst #2843 = VOC + {1, OperandInfo410}, // Inst #2844 = VONE + {4, OperandInfo372}, // Inst #2845 = VPDI + {4, OperandInfo375}, // Inst #2846 = VPERM + {4, OperandInfo372}, // Inst #2847 = VPK + {3, OperandInfo373}, // Inst #2848 = VPKF + {3, OperandInfo373}, // Inst #2849 = VPKG + {3, OperandInfo373}, // Inst #2850 = VPKH + {5, OperandInfo113}, // Inst #2851 = VPKLS + {3, OperandInfo373}, // Inst #2852 = VPKLSF + {3, OperandInfo373}, // Inst #2853 = VPKLSFS + {3, OperandInfo373}, // Inst #2854 = VPKLSG + {3, OperandInfo373}, // Inst #2855 = VPKLSGS + {3, OperandInfo373}, // Inst #2856 = VPKLSH + {3, OperandInfo373}, // Inst #2857 = VPKLSHS + {5, OperandInfo113}, // Inst #2858 = VPKS + {3, OperandInfo373}, // Inst #2859 = VPKSF + {3, OperandInfo373}, // Inst #2860 = VPKSFS + {3, OperandInfo373}, // Inst #2861 = VPKSG + {3, OperandInfo373}, // Inst #2862 = VPKSGS + {3, OperandInfo373}, // Inst #2863 = VPKSH + {3, OperandInfo373}, // Inst #2864 = VPKSHS + {4, OperandInfo405}, // Inst #2865 = VPKZ + {5, OperandInfo113}, // Inst #2866 = VPKZR + {3, OperandInfo378}, // Inst #2867 = VPOPCT + {2, OperandInfo379}, // Inst #2868 = VPOPCTB + {2, OperandInfo379}, // Inst #2869 = VPOPCTF + {2, OperandInfo379}, // Inst #2870 = VPOPCTG + {2, OperandInfo379}, // Inst #2871 = VPOPCTH + {5, OperandInfo376}, // Inst #2872 = VPSOP + {4, OperandInfo377}, // Inst #2873 = VREP + {3, OperandInfo378}, // Inst #2874 = VREPB + {3, OperandInfo378}, // Inst #2875 = VREPF + {3, OperandInfo378}, // Inst #2876 = VREPG + {3, OperandInfo378}, // Inst #2877 = VREPH + {3, OperandInfo395}, // Inst #2878 = VREPI + {2, OperandInfo392}, // Inst #2879 = VREPIB + {2, OperandInfo392}, // Inst #2880 = VREPIF + {2, OperandInfo392}, // Inst #2881 = VREPIG + {2, OperandInfo392}, // Inst #2882 = VREPIH + {5, OperandInfo113}, // Inst #2883 = VRP + {4, OperandInfo372}, // Inst #2884 = VS + {3, OperandInfo373}, // Inst #2885 = VSB + {5, OperandInfo374}, // Inst #2886 = VSBCBI + {4, OperandInfo375}, // Inst #2887 = VSBCBIQ + {5, OperandInfo374}, // Inst #2888 = VSBI + {4, OperandInfo375}, // Inst #2889 = VSBIQ + {4, OperandInfo372}, // Inst #2890 = VSCBI + {3, OperandInfo373}, // Inst #2891 = VSCBIB + {3, OperandInfo373}, // Inst #2892 = VSCBIF + {3, OperandInfo373}, // Inst #2893 = VSCBIG + {3, OperandInfo373}, // Inst #2894 = VSCBIH + {3, OperandInfo373}, // Inst #2895 = VSCBIQ + {5, OperandInfo411}, // Inst #2896 = VSCEF + {5, OperandInfo411}, // Inst #2897 = VSCEG + {4, OperandInfo372}, // Inst #2898 = VSCHDP + {5, OperandInfo113}, // Inst #2899 = VSCHP + {4, OperandInfo372}, // Inst #2900 = VSCHSP + {4, OperandInfo372}, // Inst #2901 = VSCHXP + {3, OperandInfo373}, // Inst #2902 = VSCSHP + {5, OperandInfo113}, // Inst #2903 = VSDP + {3, OperandInfo378}, // Inst #2904 = VSEG + {2, OperandInfo379}, // Inst #2905 = VSEGB + {2, OperandInfo379}, // Inst #2906 = VSEGF + {2, OperandInfo379}, // Inst #2907 = VSEGH + {4, OperandInfo375}, // Inst #2908 = VSEL + {3, OperandInfo373}, // Inst #2909 = VSF + {3, OperandInfo373}, // Inst #2910 = VSG + {3, OperandInfo373}, // Inst #2911 = VSH + {3, OperandInfo373}, // Inst #2912 = VSL + {3, OperandInfo373}, // Inst #2913 = VSLB + {4, OperandInfo372}, // Inst #2914 = VSLD + {4, OperandInfo372}, // Inst #2915 = VSLDB + {5, OperandInfo113}, // Inst #2916 = VSP + {3, OperandInfo373}, // Inst #2917 = VSQ + {3, OperandInfo373}, // Inst #2918 = VSRA + {3, OperandInfo373}, // Inst #2919 = VSRAB + {4, OperandInfo372}, // Inst #2920 = VSRD + {3, OperandInfo373}, // Inst #2921 = VSRL + {3, OperandInfo373}, // Inst #2922 = VSRLB + {5, OperandInfo376}, // Inst #2923 = VSRP + {5, OperandInfo113}, // Inst #2924 = VSRPR + {4, OperandInfo396}, // Inst #2925 = VST + {5, OperandInfo397}, // Inst #2926 = VSTAlign + {5, OperandInfo397}, // Inst #2927 = VSTBR + {4, OperandInfo396}, // Inst #2928 = VSTBRF + {4, OperandInfo396}, // Inst #2929 = VSTBRG + {4, OperandInfo396}, // Inst #2930 = VSTBRH + {4, OperandInfo396}, // Inst #2931 = VSTBRQ + {5, OperandInfo397}, // Inst #2932 = VSTEB + {5, OperandInfo397}, // Inst #2933 = VSTEBRF + {5, OperandInfo397}, // Inst #2934 = VSTEBRG + {5, OperandInfo397}, // Inst #2935 = VSTEBRH + {5, OperandInfo397}, // Inst #2936 = VSTEF + {5, OperandInfo397}, // Inst #2937 = VSTEG + {5, OperandInfo397}, // Inst #2938 = VSTEH + {5, OperandInfo397}, // Inst #2939 = VSTER + {4, OperandInfo396}, // Inst #2940 = VSTERF + {4, OperandInfo396}, // Inst #2941 = VSTERG + {4, OperandInfo396}, // Inst #2942 = VSTERH + {4, OperandInfo402}, // Inst #2943 = VSTL + {4, OperandInfo403}, // Inst #2944 = VSTM + {5, OperandInfo404}, // Inst #2945 = VSTMAlign + {6, OperandInfo391}, // Inst #2946 = VSTRC + {5, OperandInfo374}, // Inst #2947 = VSTRCB + {5, OperandInfo374}, // Inst #2948 = VSTRCBS + {5, OperandInfo374}, // Inst #2949 = VSTRCF + {5, OperandInfo374}, // Inst #2950 = VSTRCFS + {5, OperandInfo374}, // Inst #2951 = VSTRCH + {5, OperandInfo374}, // Inst #2952 = VSTRCHS + {5, OperandInfo374}, // Inst #2953 = VSTRCZB + {5, OperandInfo374}, // Inst #2954 = VSTRCZBS + {5, OperandInfo374}, // Inst #2955 = VSTRCZF + {5, OperandInfo374}, // Inst #2956 = VSTRCZFS + {5, OperandInfo374}, // Inst #2957 = VSTRCZH + {5, OperandInfo374}, // Inst #2958 = VSTRCZHS + {4, OperandInfo405}, // Inst #2959 = VSTRL + {4, OperandInfo402}, // Inst #2960 = VSTRLR + {6, OperandInfo391}, // Inst #2961 = VSTRS + {5, OperandInfo374}, // Inst #2962 = VSTRSB + {5, OperandInfo374}, // Inst #2963 = VSTRSF + {5, OperandInfo374}, // Inst #2964 = VSTRSH + {4, OperandInfo375}, // Inst #2965 = VSTRSZB + {4, OperandInfo375}, // Inst #2966 = VSTRSZF + {4, OperandInfo375}, // Inst #2967 = VSTRSZH + {4, OperandInfo372}, // Inst #2968 = VSUM + {3, OperandInfo373}, // Inst #2969 = VSUMB + {4, OperandInfo372}, // Inst #2970 = VSUMG + {3, OperandInfo373}, // Inst #2971 = VSUMGF + {3, OperandInfo373}, // Inst #2972 = VSUMGH + {3, OperandInfo373}, // Inst #2973 = VSUMH + {4, OperandInfo372}, // Inst #2974 = VSUMQ + {3, OperandInfo373}, // Inst #2975 = VSUMQF + {3, OperandInfo373}, // Inst #2976 = VSUMQG + {2, OperandInfo379}, // Inst #2977 = VTM + {1, OperandInfo410}, // Inst #2978 = VTP + {3, OperandInfo378}, // Inst #2979 = VUPH + {2, OperandInfo379}, // Inst #2980 = VUPHB + {2, OperandInfo379}, // Inst #2981 = VUPHF + {2, OperandInfo379}, // Inst #2982 = VUPHH + {4, OperandInfo405}, // Inst #2983 = VUPKZ + {3, OperandInfo378}, // Inst #2984 = VUPKZH + {3, OperandInfo378}, // Inst #2985 = VUPKZL + {3, OperandInfo378}, // Inst #2986 = VUPL + {2, OperandInfo379}, // Inst #2987 = VUPLB + {2, OperandInfo379}, // Inst #2988 = VUPLF + {3, OperandInfo378}, // Inst #2989 = VUPLH + {2, OperandInfo379}, // Inst #2990 = VUPLHB + {2, OperandInfo379}, // Inst #2991 = VUPLHF + {2, OperandInfo379}, // Inst #2992 = VUPLHH + {2, OperandInfo379}, // Inst #2993 = VUPLHW + {3, OperandInfo378}, // Inst #2994 = VUPLL + {2, OperandInfo379}, // Inst #2995 = VUPLLB + {2, OperandInfo379}, // Inst #2996 = VUPLLF + {2, OperandInfo379}, // Inst #2997 = VUPLLH + {3, OperandInfo373}, // Inst #2998 = VX + {1, OperandInfo410}, // Inst #2999 = VZERO + {4, OperandInfo412}, // Inst #3000 = WCDGB + {4, OperandInfo412}, // Inst #3001 = WCDLGB + {4, OperandInfo413}, // Inst #3002 = WCEFB + {4, OperandInfo413}, // Inst #3003 = WCELFB + {4, OperandInfo413}, // Inst #3004 = WCFEB + {4, OperandInfo412}, // Inst #3005 = WCGDB + {4, OperandInfo413}, // Inst #3006 = WCLFEB + {4, OperandInfo412}, // Inst #3007 = WCLGDB + {3, OperandInfo414}, // Inst #3008 = WFADB + {3, OperandInfo415}, // Inst #3009 = WFASB + {3, OperandInfo373}, // Inst #3010 = WFAXB + {4, OperandInfo412}, // Inst #3011 = WFC + {2, OperandInfo121}, // Inst #3012 = WFCDB + {3, OperandInfo414}, // Inst #3013 = WFCEDB + {3, OperandInfo414}, // Inst #3014 = WFCEDBS + {3, OperandInfo415}, // Inst #3015 = WFCESB + {3, OperandInfo415}, // Inst #3016 = WFCESBS + {3, OperandInfo373}, // Inst #3017 = WFCEXB + {3, OperandInfo373}, // Inst #3018 = WFCEXBS + {3, OperandInfo414}, // Inst #3019 = WFCHDB + {3, OperandInfo414}, // Inst #3020 = WFCHDBS + {3, OperandInfo414}, // Inst #3021 = WFCHEDB + {3, OperandInfo414}, // Inst #3022 = WFCHEDBS + {3, OperandInfo415}, // Inst #3023 = WFCHESB + {3, OperandInfo415}, // Inst #3024 = WFCHESBS + {3, OperandInfo373}, // Inst #3025 = WFCHEXB + {3, OperandInfo373}, // Inst #3026 = WFCHEXBS + {3, OperandInfo415}, // Inst #3027 = WFCHSB + {3, OperandInfo415}, // Inst #3028 = WFCHSBS + {3, OperandInfo373}, // Inst #3029 = WFCHXB + {3, OperandInfo373}, // Inst #3030 = WFCHXBS + {2, OperandInfo120}, // Inst #3031 = WFCSB + {2, OperandInfo379}, // Inst #3032 = WFCXB + {3, OperandInfo414}, // Inst #3033 = WFDDB + {3, OperandInfo415}, // Inst #3034 = WFDSB + {3, OperandInfo373}, // Inst #3035 = WFDXB + {4, OperandInfo412}, // Inst #3036 = WFIDB + {4, OperandInfo413}, // Inst #3037 = WFISB + {4, OperandInfo377}, // Inst #3038 = WFIXB + {4, OperandInfo412}, // Inst #3039 = WFK + {2, OperandInfo121}, // Inst #3040 = WFKDB + {3, OperandInfo414}, // Inst #3041 = WFKEDB + {3, OperandInfo414}, // Inst #3042 = WFKEDBS + {3, OperandInfo415}, // Inst #3043 = WFKESB + {3, OperandInfo415}, // Inst #3044 = WFKESBS + {3, OperandInfo373}, // Inst #3045 = WFKEXB + {3, OperandInfo373}, // Inst #3046 = WFKEXBS + {3, OperandInfo414}, // Inst #3047 = WFKHDB + {3, OperandInfo414}, // Inst #3048 = WFKHDBS + {3, OperandInfo414}, // Inst #3049 = WFKHEDB + {3, OperandInfo414}, // Inst #3050 = WFKHEDBS + {3, OperandInfo415}, // Inst #3051 = WFKHESB + {3, OperandInfo415}, // Inst #3052 = WFKHESBS + {3, OperandInfo373}, // Inst #3053 = WFKHEXB + {3, OperandInfo373}, // Inst #3054 = WFKHEXBS + {3, OperandInfo415}, // Inst #3055 = WFKHSB + {3, OperandInfo415}, // Inst #3056 = WFKHSBS + {3, OperandInfo373}, // Inst #3057 = WFKHXB + {3, OperandInfo373}, // Inst #3058 = WFKHXBS + {2, OperandInfo120}, // Inst #3059 = WFKSB + {2, OperandInfo379}, // Inst #3060 = WFKXB + {2, OperandInfo121}, // Inst #3061 = WFLCDB + {2, OperandInfo120}, // Inst #3062 = WFLCSB + {2, OperandInfo379}, // Inst #3063 = WFLCXB + {2, OperandInfo416}, // Inst #3064 = WFLLD + {2, OperandInfo417}, // Inst #3065 = WFLLS + {2, OperandInfo121}, // Inst #3066 = WFLNDB + {2, OperandInfo120}, // Inst #3067 = WFLNSB + {2, OperandInfo379}, // Inst #3068 = WFLNXB + {2, OperandInfo121}, // Inst #3069 = WFLPDB + {2, OperandInfo120}, // Inst #3070 = WFLPSB + {2, OperandInfo379}, // Inst #3071 = WFLPXB + {4, OperandInfo418}, // Inst #3072 = WFLRD + {4, OperandInfo419}, // Inst #3073 = WFLRX + {4, OperandInfo420}, // Inst #3074 = WFMADB + {4, OperandInfo421}, // Inst #3075 = WFMASB + {4, OperandInfo375}, // Inst #3076 = WFMAXB + {4, OperandInfo422}, // Inst #3077 = WFMAXDB + {4, OperandInfo423}, // Inst #3078 = WFMAXSB + {4, OperandInfo372}, // Inst #3079 = WFMAXXB + {3, OperandInfo414}, // Inst #3080 = WFMDB + {4, OperandInfo422}, // Inst #3081 = WFMINDB + {4, OperandInfo423}, // Inst #3082 = WFMINSB + {4, OperandInfo372}, // Inst #3083 = WFMINXB + {3, OperandInfo415}, // Inst #3084 = WFMSB + {4, OperandInfo420}, // Inst #3085 = WFMSDB + {4, OperandInfo421}, // Inst #3086 = WFMSSB + {4, OperandInfo375}, // Inst #3087 = WFMSXB + {3, OperandInfo373}, // Inst #3088 = WFMXB + {4, OperandInfo420}, // Inst #3089 = WFNMADB + {4, OperandInfo421}, // Inst #3090 = WFNMASB + {4, OperandInfo375}, // Inst #3091 = WFNMAXB + {4, OperandInfo420}, // Inst #3092 = WFNMSDB + {4, OperandInfo421}, // Inst #3093 = WFNMSSB + {4, OperandInfo375}, // Inst #3094 = WFNMSXB + {3, OperandInfo424}, // Inst #3095 = WFPSODB + {3, OperandInfo425}, // Inst #3096 = WFPSOSB + {3, OperandInfo378}, // Inst #3097 = WFPSOXB + {3, OperandInfo414}, // Inst #3098 = WFSDB + {2, OperandInfo121}, // Inst #3099 = WFSQDB + {2, OperandInfo120}, // Inst #3100 = WFSQSB + {2, OperandInfo379}, // Inst #3101 = WFSQXB + {3, OperandInfo415}, // Inst #3102 = WFSSB + {3, OperandInfo373}, // Inst #3103 = WFSXB + {3, OperandInfo424}, // Inst #3104 = WFTCIDB + {3, OperandInfo425}, // Inst #3105 = WFTCISB + {3, OperandInfo378}, // Inst #3106 = WFTCIXB + {2, OperandInfo417}, // Inst #3107 = WLDEB + {4, OperandInfo418}, // Inst #3108 = WLEDB + {5, OperandInfo123}, // Inst #3109 = X + {5, OperandInfo209}, // Inst #3110 = XC + {5, OperandInfo131}, // Inst #3111 = XG + {3, OperandInfo133}, // Inst #3112 = XGR + {3, OperandInfo100}, // Inst #3113 = XGRK + {3, OperandInfo116}, // Inst #3114 = XI + {3, OperandInfo136}, // Inst #3115 = XIHF + {3, OperandInfo130}, // Inst #3116 = XILF + {3, OperandInfo116}, // Inst #3117 = XIY + {3, OperandInfo137}, // Inst #3118 = XR + {3, OperandInfo138}, // Inst #3119 = XRK + {0, NULL}, // Inst #3120 = XSCH + {5, OperandInfo123}, // Inst #3121 = XY + {6, OperandInfo139}, // Inst #3122 = ZAP +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +extern const char SystemZInstrNameData[] = { + /* 0 */ "G_FLOG10\0" + /* 9 */ "CU21\0" + /* 14 */ "SAM31\0" + /* 20 */ "CU41\0" + /* 25 */ "CU12\0" + /* 30 */ "IC32\0" + /* 35 */ "LDE32\0" + /* 41 */ "CondStoreF32\0" + /* 54 */ "SelectF32\0" + /* 64 */ "RISBG32\0" + /* 72 */ "VL32\0" + /* 77 */ "VLVGP32\0" + /* 85 */ "LDR32\0" + /* 91 */ "VLR32\0" + /* 97 */ "SelectVR32\0" + /* 108 */ "VST32\0" + /* 114 */ "ATOMIC_LOAD_UMIN_32\0" + /* 134 */ "ATOMIC_LOAD_MIN_32\0" + /* 153 */ "ATOMIC_SWAP_32\0" + /* 168 */ "LCDFR_32\0" + /* 177 */ "LNDFR_32\0" + /* 186 */ "LPDFR_32\0" + /* 195 */ "ATOMIC_LOAD_UMAX_32\0" + /* 215 */ "ATOMIC_LOAD_MAX_32\0" + /* 234 */ "CondStore32\0" + /* 246 */ "Select32\0" + /* 255 */ "CU42\0" + /* 260 */ "G_FLOG2\0" + /* 268 */ "TRAP2\0" + /* 274 */ "G_FEXP2\0" + /* 282 */ "CU14\0" + /* 287 */ "SAM24\0" + /* 293 */ "CU24\0" + /* 298 */ "IIHF64\0" + /* 305 */ "ATOMIC_LOAD_NIHF64\0" + /* 324 */ "ATOMIC_LOAD_OIHF64\0" + /* 343 */ "ATOMIC_LOAD_XIHF64\0" + /* 362 */ "IILF64\0" + /* 369 */ "ATOMIC_LOAD_NILF64\0" + /* 388 */ "ATOMIC_LOAD_OILF64\0" + /* 407 */ "ATOMIC_LOAD_XILF64\0" + /* 426 */ "CondStoreF64\0" + /* 439 */ "SelectF64\0" + /* 449 */ "IIHH64\0" + /* 456 */ "ATOMIC_LOAD_NIHH64\0" + /* 475 */ "ATOMIC_LOAD_OIHH64\0" + /* 494 */ "TMHH64\0" + /* 501 */ "IILH64\0" + /* 508 */ "ATOMIC_LOAD_NILH64\0" + /* 527 */ "ATOMIC_LOAD_OILH64\0" + /* 546 */ "TMLH64\0" + /* 553 */ "CallBRASL_XPLINK64\0" + /* 572 */ "CallBASR_XPLINK64\0" + /* 590 */ "IIHL64\0" + /* 597 */ "ATOMIC_LOAD_NIHL64\0" + /* 616 */ "ATOMIC_LOAD_OIHL64\0" + /* 635 */ "TMHL64\0" + /* 642 */ "IILL64\0" + /* 649 */ "ATOMIC_LOAD_NILL64\0" + /* 668 */ "ATOMIC_LOAD_OILL64\0" + /* 687 */ "TMLL64\0" + /* 694 */ "VL64\0" + /* 699 */ "SAM64\0" + /* 705 */ "VLR64\0" + /* 711 */ "SelectVR64\0" + /* 722 */ "VST64\0" + /* 728 */ "ATOMIC_LOAD_UMIN_64\0" + /* 748 */ "ATOMIC_LOAD_MIN_64\0" + /* 767 */ "ATOMIC_SWAP_64\0" + /* 782 */ "ATOMIC_LOAD_UMAX_64\0" + /* 802 */ "ATOMIC_LOAD_MAX_64\0" + /* 821 */ "CondStore64\0" + /* 833 */ "Select64\0" + /* 842 */ "TRAP4\0" + /* 848 */ "CondStore16\0" + /* 860 */ "SelectF128\0" + /* 871 */ "L128\0" + /* 876 */ "PAIR128\0" + /* 884 */ "SelectVR128\0" + /* 896 */ "ST128\0" + /* 902 */ "AEXT128\0" + /* 910 */ "ZEXT128\0" + /* 918 */ "CondStore8\0" + /* 929 */ "LAA\0" + /* 933 */ "PROBED_ALLOCA\0" + /* 947 */ "SLDA\0" + /* 952 */ "SRDA\0" + /* 957 */ "ESEA\0" + /* 962 */ "LPTEA\0" + /* 968 */ "VFA\0" + /* 972 */ "SIGA\0" + /* 977 */ "ECPGA\0" + /* 983 */ "UNPKA\0" + /* 989 */ "SPKA\0" + /* 994 */ "SLA\0" + /* 998 */ "VGFMA\0" + /* 1004 */ "VFMA\0" + /* 1009 */ "G_FMA\0" + /* 1015 */ "G_STRICT_FMA\0" + /* 1028 */ "KMA\0" + /* 1032 */ "VFNMA\0" + /* 1038 */ "NNPA\0" + /* 1043 */ "PPA\0" + /* 1047 */ "LEDBRA\0" + /* 1054 */ "CFDBRA\0" + /* 1061 */ "CGDBRA\0" + /* 1068 */ "FIDBRA\0" + /* 1075 */ "CFEBRA\0" + /* 1082 */ "CGEBRA\0" + /* 1089 */ "FIEBRA\0" + /* 1096 */ "CDFBRA\0" + /* 1103 */ "CEFBRA\0" + /* 1110 */ "CXFBRA\0" + /* 1117 */ "CDGBRA\0" + /* 1124 */ "CEGBRA\0" + /* 1131 */ "CXGBRA\0" + /* 1138 */ "LDXBRA\0" + /* 1145 */ "LEXBRA\0" + /* 1152 */ "CFXBRA\0" + /* 1159 */ "CGXBRA\0" + /* 1166 */ "FIXBRA\0" + /* 1173 */ "LRA\0" + /* 1177 */ "VESRA\0" + /* 1183 */ "VSRA\0" + /* 1188 */ "ADTRA\0" + /* 1194 */ "DDTRA\0" + /* 1200 */ "CGDTRA\0" + /* 1207 */ "MDTRA\0" + /* 1213 */ "SDTRA\0" + /* 1219 */ "CDGTRA\0" + /* 1226 */ "CXGTRA\0" + /* 1233 */ "AXTRA\0" + /* 1239 */ "DXTRA\0" + /* 1245 */ "CGXTRA\0" + /* 1252 */ "MXTRA\0" + /* 1258 */ "SXTRA\0" + /* 1264 */ "LURA\0" + /* 1269 */ "STURA\0" + /* 1275 */ "BSA\0" + /* 1279 */ "KDSA\0" + /* 1284 */ "ESTA\0" + /* 1289 */ "MSTA\0" + /* 1294 */ "VA\0" + /* 1297 */ "CPYA\0" + /* 1302 */ "VGFMAB\0" + /* 1309 */ "VESRAB\0" + /* 1316 */ "VSRAB\0" + /* 1322 */ "VAB\0" + /* 1326 */ "LCBB\0" + /* 1331 */ "VLBB\0" + /* 1336 */ "VACCB\0" + /* 1342 */ "VECB\0" + /* 1347 */ "VLCB\0" + /* 1352 */ "VSTRCB\0" + /* 1359 */ "VFADB\0" + /* 1365 */ "WFADB\0" + /* 1371 */ "VFMADB\0" + /* 1378 */ "WFMADB\0" + /* 1385 */ "VFNMADB\0" + /* 1393 */ "WFNMADB\0" + /* 1401 */ "WFCDB\0" + /* 1407 */ "VFLCDB\0" + /* 1414 */ "WFLCDB\0" + /* 1421 */ "TCDB\0" + /* 1426 */ "VFDDB\0" + /* 1432 */ "WFDDB\0" + /* 1438 */ "VFCEDB\0" + /* 1445 */ "WFCEDB\0" + /* 1452 */ "VFCHEDB\0" + /* 1460 */ "WFCHEDB\0" + /* 1468 */ "VFKHEDB\0" + /* 1476 */ "WFKHEDB\0" + /* 1484 */ "VFKEDB\0" + /* 1491 */ "WFKEDB\0" + /* 1498 */ "VLEDB\0" + /* 1504 */ "WLEDB\0" + /* 1510 */ "VCGDB\0" + /* 1516 */ "WCGDB\0" + /* 1522 */ "VCLGDB\0" + /* 1529 */ "WCLGDB\0" + /* 1536 */ "VFCHDB\0" + /* 1543 */ "WFCHDB\0" + /* 1550 */ "VFKHDB\0" + /* 1557 */ "WFKHDB\0" + /* 1564 */ "VFTCIDB\0" + /* 1572 */ "WFTCIDB\0" + /* 1580 */ "VFIDB\0" + /* 1586 */ "WFIDB\0" + /* 1592 */ "WFKDB\0" + /* 1598 */ "VSLDB\0" + /* 1604 */ "VFMDB\0" + /* 1610 */ "WFMDB\0" + /* 1616 */ "VFMINDB\0" + /* 1624 */ "WFMINDB\0" + /* 1632 */ "VFLNDB\0" + /* 1639 */ "WFLNDB\0" + /* 1646 */ "VFPSODB\0" + /* 1654 */ "WFPSODB\0" + /* 1662 */ "VFLPDB\0" + /* 1669 */ "WFLPDB\0" + /* 1676 */ "VFSQDB\0" + /* 1683 */ "WFSQDB\0" + /* 1690 */ "VFSDB\0" + /* 1696 */ "WFSDB\0" + /* 1702 */ "VFMSDB\0" + /* 1709 */ "WFMSDB\0" + /* 1716 */ "VFNMSDB\0" + /* 1724 */ "WFNMSDB\0" + /* 1732 */ "VFMAXDB\0" + /* 1740 */ "WFMAXDB\0" + /* 1748 */ "LXDB\0" + /* 1753 */ "MXDB\0" + /* 1758 */ "VFAEB\0" + /* 1764 */ "VMAEB\0" + /* 1770 */ "TCEB\0" + /* 1775 */ "VLDEB\0" + /* 1781 */ "WLDEB\0" + /* 1787 */ "MDEB\0" + /* 1792 */ "VFEEB\0" + /* 1798 */ "MEEB\0" + /* 1803 */ "VCFEB\0" + /* 1809 */ "WCFEB\0" + /* 1815 */ "VCLFEB\0" + /* 1822 */ "WCLFEB\0" + /* 1829 */ "KEB\0" + /* 1833 */ "VMALEB\0" + /* 1840 */ "VMLEB\0" + /* 1846 */ "VLEB\0" + /* 1851 */ "VMEB\0" + /* 1856 */ "VFENEB\0" + /* 1863 */ "SQEB\0" + /* 1868 */ "MSEB\0" + /* 1873 */ "VSTEB\0" + /* 1879 */ "LXEB\0" + /* 1884 */ "VCEFB\0" + /* 1890 */ "WCEFB\0" + /* 1896 */ "VCELFB\0" + /* 1903 */ "WCELFB\0" + /* 1910 */ "VCDGB\0" + /* 1916 */ "WCDGB\0" + /* 1922 */ "VSEGB\0" + /* 1928 */ "VCDLGB\0" + /* 1935 */ "WCDLGB\0" + /* 1942 */ "VAVGB\0" + /* 1948 */ "VLVGB\0" + /* 1954 */ "VMAHB\0" + /* 1960 */ "VCHB\0" + /* 1965 */ "VMALHB\0" + /* 1972 */ "VMLHB\0" + /* 1978 */ "VUPLHB\0" + /* 1985 */ "VMHB\0" + /* 1990 */ "VUPHB\0" + /* 1996 */ "VMRHB\0" + /* 2002 */ "VSCBIB\0" + /* 2009 */ "CIB\0" + /* 2013 */ "VLEIB\0" + /* 2019 */ "CGIB\0" + /* 2024 */ "CLGIB\0" + /* 2030 */ "CLIB\0" + /* 2035 */ "VREPIB\0" + /* 2042 */ "VMALB\0" + /* 2048 */ "PALB\0" + /* 2053 */ "VECLB\0" + /* 2059 */ "VAVGLB\0" + /* 2066 */ "VCHLB\0" + /* 2072 */ "VUPLLB\0" + /* 2079 */ "VERLLB\0" + /* 2086 */ "VMLB\0" + /* 2091 */ "VMNLB\0" + /* 2097 */ "VUPLB\0" + /* 2103 */ "VMRLB\0" + /* 2109 */ "VESRLB\0" + /* 2116 */ "VSRLB\0" + /* 2122 */ "VESLB\0" + /* 2128 */ "VSLB\0" + /* 2133 */ "PTLB\0" + /* 2138 */ "VMXLB\0" + /* 2144 */ "VGFMB\0" + /* 2150 */ "VGMB\0" + /* 2155 */ "VERIMB\0" + /* 2162 */ "SRNMB\0" + /* 2168 */ "VSUMB\0" + /* 2174 */ "VMNB\0" + /* 2179 */ "VMAOB\0" + /* 2185 */ "VMALOB\0" + /* 2192 */ "VMLOB\0" + /* 2198 */ "VMOB\0" + /* 2203 */ "VLREPB\0" + /* 2210 */ "VREPB\0" + /* 2216 */ "VLPB\0" + /* 2221 */ "VCEQB\0" + /* 2227 */ "CRB\0" + /* 2231 */ "CGRB\0" + /* 2236 */ "CLGRB\0" + /* 2242 */ "CLRB\0" + /* 2247 */ "VISTRB\0" + /* 2254 */ "VFASB\0" + /* 2260 */ "WFASB\0" + /* 2266 */ "VFMASB\0" + /* 2273 */ "WFMASB\0" + /* 2280 */ "VFNMASB\0" + /* 2288 */ "WFNMASB\0" + /* 2296 */ "WFCSB\0" + /* 2302 */ "VFLCSB\0" + /* 2309 */ "WFLCSB\0" + /* 2316 */ "VFDSB\0" + /* 2322 */ "WFDSB\0" + /* 2328 */ "VFCESB\0" + /* 2335 */ "WFCESB\0" + /* 2342 */ "VFCHESB\0" + /* 2350 */ "WFCHESB\0" + /* 2358 */ "VFKHESB\0" + /* 2366 */ "WFKHESB\0" + /* 2374 */ "VFKESB\0" + /* 2381 */ "WFKESB\0" + /* 2388 */ "VFCHSB\0" + /* 2395 */ "WFCHSB\0" + /* 2402 */ "VFKHSB\0" + /* 2409 */ "WFKHSB\0" + /* 2416 */ "VFTCISB\0" + /* 2424 */ "WFTCISB\0" + /* 2432 */ "VFISB\0" + /* 2438 */ "WFISB\0" + /* 2444 */ "WFKSB\0" + /* 2450 */ "VFMSB\0" + /* 2456 */ "WFMSB\0" + /* 2462 */ "VFMINSB\0" + /* 2470 */ "WFMINSB\0" + /* 2478 */ "VFLNSB\0" + /* 2485 */ "WFLNSB\0" + /* 2492 */ "VFPSOSB\0" + /* 2500 */ "WFPSOSB\0" + /* 2508 */ "VFLPSB\0" + /* 2515 */ "WFLPSB\0" + /* 2522 */ "VFSQSB\0" + /* 2529 */ "WFSQSB\0" + /* 2536 */ "VSTRSB\0" + /* 2543 */ "VFSSB\0" + /* 2549 */ "WFSSB\0" + /* 2555 */ "VFMSSB\0" + /* 2562 */ "WFMSSB\0" + /* 2569 */ "VFNMSSB\0" + /* 2577 */ "WFNMSSB\0" + /* 2585 */ "VSB\0" + /* 2589 */ "VFMAXSB\0" + /* 2597 */ "WFMAXSB\0" + /* 2605 */ "VPOPCTB\0" + /* 2613 */ "G_FSUB\0" + /* 2620 */ "G_STRICT_FSUB\0" + /* 2634 */ "G_ATOMICRMW_FSUB\0" + /* 2651 */ "G_SUB\0" + /* 2657 */ "G_ATOMICRMW_SUB\0" + /* 2673 */ "VESRAVB\0" + /* 2681 */ "VCVB\0" + /* 2686 */ "VLGVB\0" + /* 2692 */ "VERLLVB\0" + /* 2700 */ "VESRLVB\0" + /* 2708 */ "VESLVB\0" + /* 2715 */ "WFAXB\0" + /* 2721 */ "WFMAXB\0" + /* 2728 */ "WFNMAXB\0" + /* 2736 */ "WFCXB\0" + /* 2742 */ "WFLCXB\0" + /* 2749 */ "TCXB\0" + /* 2754 */ "WFDXB\0" + /* 2760 */ "WFCEXB\0" + /* 2767 */ "WFCHEXB\0" + /* 2775 */ "WFKHEXB\0" + /* 2783 */ "WFKEXB\0" + /* 2790 */ "WFCHXB\0" + /* 2797 */ "WFKHXB\0" + /* 2804 */ "WFTCIXB\0" + /* 2812 */ "WFIXB\0" + /* 2818 */ "WFKXB\0" + /* 2824 */ "WFMXB\0" + /* 2830 */ "VMXB\0" + /* 2835 */ "WFMINXB\0" + /* 2843 */ "WFLNXB\0" + /* 2850 */ "WFPSOXB\0" + /* 2858 */ "WFLPXB\0" + /* 2865 */ "WFSQXB\0" + /* 2872 */ "WFSXB\0" + /* 2878 */ "WFMSXB\0" + /* 2885 */ "WFNMSXB\0" + /* 2893 */ "WFMAXXB\0" + /* 2901 */ "VSTRCZB\0" + /* 2909 */ "VFAEZB\0" + /* 2916 */ "VFEEZB\0" + /* 2923 */ "VLLEZB\0" + /* 2930 */ "VFENEZB\0" + /* 2938 */ "VCLZB\0" + /* 2944 */ "VSTRSZB\0" + /* 2952 */ "VCTZB\0" + /* 2958 */ "IAC\0" + /* 2962 */ "KMAC\0" + /* 2967 */ "SAC\0" + /* 2971 */ "VAC\0" + /* 2975 */ "BC\0" + /* 2978 */ "VACC\0" + /* 2983 */ "VACCC\0" + /* 2989 */ "PCC\0" + /* 2993 */ "DFLTCC\0" + /* 3000 */ "VEC\0" + /* 3004 */ "CFC\0" + /* 3008 */ "WFC\0" + /* 3012 */ "LLGC\0" + /* 3017 */ "MSGC\0" + /* 3022 */ "BIC\0" + /* 3026 */ "G_INTRINSIC\0" + /* 3038 */ "SCKC\0" + /* 3043 */ "STCKC\0" + /* 3049 */ "MSGRKC\0" + /* 3056 */ "MSRKC\0" + /* 3062 */ "ALC\0" + /* 3066 */ "CLC\0" + /* 3070 */ "LLC\0" + /* 3074 */ "VLC\0" + /* 3078 */ "KMC\0" + /* 3082 */ "TBEGINC\0" + /* 3090 */ "G_FPTRUNC\0" + /* 3100 */ "G_INTRINSIC_TRUNC\0" + /* 3118 */ "G_TRUNC\0" + /* 3126 */ "G_BUILD_VECTOR_TRUNC\0" + /* 3147 */ "VNC\0" + /* 3151 */ "PROBED_STACKALLOC\0" + /* 3169 */ "G_DYN_STACKALLOC\0" + /* 3186 */ "ADJDYNALLOC\0" + /* 3198 */ "STOC\0" + /* 3203 */ "VOC\0" + /* 3207 */ "EFPC\0" + /* 3212 */ "LFPC\0" + /* 3217 */ "SFPC\0" + /* 3222 */ "STFPC\0" + /* 3228 */ "BRC\0" + /* 3232 */ "VSTRC\0" + /* 3238 */ "LGSC\0" + /* 3243 */ "STGSC\0" + /* 3249 */ "MSC\0" + /* 3253 */ "CMPSC\0" + /* 3259 */ "STC\0" + /* 3263 */ "MVC\0" + /* 3267 */ "SVC\0" + /* 3271 */ "XC\0" + /* 3274 */ "G_FMAD\0" + /* 3281 */ "G_INDEXED_SEXTLOAD\0" + /* 3300 */ "G_SEXTLOAD\0" + /* 3311 */ "G_INDEXED_ZEXTLOAD\0" + /* 3330 */ "G_ZEXTLOAD\0" + /* 3341 */ "G_INDEXED_LOAD\0" + /* 3356 */ "G_LOAD\0" + /* 3363 */ "CD\0" + /* 3366 */ "G_VECREDUCE_FADD\0" + /* 3383 */ "G_FADD\0" + /* 3390 */ "G_VECREDUCE_SEQ_FADD\0" + /* 3411 */ "G_STRICT_FADD\0" + /* 3425 */ "G_ATOMICRMW_FADD\0" + /* 3442 */ "G_VECREDUCE_ADD\0" + /* 3458 */ "G_ADD\0" + /* 3464 */ "G_PTR_ADD\0" + /* 3474 */ "G_ATOMICRMW_ADD\0" + /* 3490 */ "VLED\0" + /* 3495 */ "PFD\0" + /* 3499 */ "VFD\0" + /* 3503 */ "VCGD\0" + /* 3508 */ "VCLGD\0" + /* 3514 */ "WFLLD\0" + /* 3520 */ "VSLD\0" + /* 3525 */ "KIMD\0" + /* 3530 */ "KLMD\0" + /* 3535 */ "G_ATOMICRMW_NAND\0" + /* 3552 */ "G_VECREDUCE_AND\0" + /* 3568 */ "G_AND\0" + /* 3574 */ "G_ATOMICRMW_AND\0" + /* 3590 */ "TEND\0" + /* 3595 */ "LIFETIME_END\0" + /* 3608 */ "G_BRCOND\0" + /* 3617 */ "ETND\0" + /* 3622 */ "G_LLROUND\0" + /* 3632 */ "G_LROUND\0" + /* 3641 */ "G_INTRINSIC_ROUND\0" + /* 3659 */ "LPD\0" + /* 3663 */ "SQD\0" + /* 3667 */ "LOAD_STACK_GUARD\0" + /* 3684 */ "VFLRD\0" + /* 3690 */ "WFLRD\0" + /* 3696 */ "VSRD\0" + /* 3701 */ "MSD\0" + /* 3705 */ "STD\0" + /* 3709 */ "VCVD\0" + /* 3714 */ "LXD\0" + /* 3718 */ "MXD\0" + /* 3722 */ "VFAE\0" + /* 3727 */ "LAE\0" + /* 3731 */ "VMAE\0" + /* 3736 */ "PSEUDO_PROBE\0" + /* 3749 */ "RRBE\0" + /* 3754 */ "G_SSUBE\0" + /* 3762 */ "G_USUBE\0" + /* 3770 */ "TRACE\0" + /* 3776 */ "VFCE\0" + /* 3781 */ "G_FENCE\0" + /* 3789 */ "ARITH_FENCE\0" + /* 3801 */ "REG_SEQUENCE\0" + /* 3814 */ "G_SADDE\0" + /* 3822 */ "G_UADDE\0" + /* 3830 */ "VLDE\0" + /* 3835 */ "MDE\0" + /* 3839 */ "G_FMINNUM_IEEE\0" + /* 3854 */ "G_FMAXNUM_IEEE\0" + /* 3869 */ "VFEE\0" + /* 3874 */ "MEE\0" + /* 3878 */ "VFCHE\0" + /* 3884 */ "CIBAsmNHE\0" + /* 3894 */ "CGIBAsmNHE\0" + /* 3905 */ "CLGIBAsmNHE\0" + /* 3917 */ "CLIBAsmNHE\0" + /* 3928 */ "CRBAsmNHE\0" + /* 3938 */ "CGRBAsmNHE\0" + /* 3949 */ "CLGRBAsmNHE\0" + /* 3961 */ "CLRBAsmNHE\0" + /* 3972 */ "LOCAsmNHE\0" + /* 3982 */ "STOCAsmNHE\0" + /* 3993 */ "LOCGAsmNHE\0" + /* 4004 */ "STOCGAsmNHE\0" + /* 4016 */ "JGAsmNHE\0" + /* 4025 */ "LOCFHAsmNHE\0" + /* 4037 */ "STOCFHAsmNHE\0" + /* 4050 */ "BIAsmNHE\0" + /* 4059 */ "LOCHIAsmNHE\0" + /* 4071 */ "LOCGHIAsmNHE\0" + /* 4084 */ "LOCHHIAsmNHE\0" + /* 4097 */ "CIJAsmNHE\0" + /* 4107 */ "CGIJAsmNHE\0" + /* 4118 */ "CLGIJAsmNHE\0" + /* 4130 */ "CLIJAsmNHE\0" + /* 4141 */ "CRJAsmNHE\0" + /* 4151 */ "CGRJAsmNHE\0" + /* 4162 */ "CLGRJAsmNHE\0" + /* 4174 */ "CLRJAsmNHE\0" + /* 4185 */ "BRAsmNHE\0" + /* 4194 */ "LOCRAsmNHE\0" + /* 4205 */ "LOCGRAsmNHE\0" + /* 4217 */ "SELGRAsmNHE\0" + /* 4229 */ "LOCFHRAsmNHE\0" + /* 4242 */ "SELFHRAsmNHE\0" + /* 4255 */ "SELRAsmNHE\0" + /* 4266 */ "CLGTAsmNHE\0" + /* 4277 */ "CITAsmNHE\0" + /* 4287 */ "CLFITAsmNHE\0" + /* 4299 */ "CGITAsmNHE\0" + /* 4310 */ "CLGITAsmNHE\0" + /* 4322 */ "CLTAsmNHE\0" + /* 4332 */ "CRTAsmNHE\0" + /* 4342 */ "CGRTAsmNHE\0" + /* 4353 */ "CLGRTAsmNHE\0" + /* 4365 */ "CLRTAsmNHE\0" + /* 4376 */ "CIBAsmHE\0" + /* 4385 */ "CGIBAsmHE\0" + /* 4395 */ "CLGIBAsmHE\0" + /* 4406 */ "CLIBAsmHE\0" + /* 4416 */ "CRBAsmHE\0" + /* 4425 */ "CGRBAsmHE\0" + /* 4435 */ "CLGRBAsmHE\0" + /* 4446 */ "CLRBAsmHE\0" + /* 4456 */ "LOCAsmHE\0" + /* 4465 */ "STOCAsmHE\0" + /* 4475 */ "LOCGAsmHE\0" + /* 4485 */ "STOCGAsmHE\0" + /* 4496 */ "JGAsmHE\0" + /* 4504 */ "LOCFHAsmHE\0" + /* 4515 */ "STOCFHAsmHE\0" + /* 4527 */ "BIAsmHE\0" + /* 4535 */ "LOCHIAsmHE\0" + /* 4546 */ "LOCGHIAsmHE\0" + /* 4558 */ "LOCHHIAsmHE\0" + /* 4570 */ "CIJAsmHE\0" + /* 4579 */ "CGIJAsmHE\0" + /* 4589 */ "CLGIJAsmHE\0" + /* 4600 */ "CLIJAsmHE\0" + /* 4610 */ "CRJAsmHE\0" + /* 4619 */ "CGRJAsmHE\0" + /* 4629 */ "CLGRJAsmHE\0" + /* 4640 */ "CLRJAsmHE\0" + /* 4650 */ "BRAsmHE\0" + /* 4658 */ "LOCRAsmHE\0" + /* 4668 */ "LOCGRAsmHE\0" + /* 4679 */ "SELGRAsmHE\0" + /* 4690 */ "LOCFHRAsmHE\0" + /* 4702 */ "SELFHRAsmHE\0" + /* 4714 */ "SELRAsmHE\0" + /* 4724 */ "CLGTAsmHE\0" + /* 4734 */ "CITAsmHE\0" + /* 4743 */ "CLFITAsmHE\0" + /* 4754 */ "CGITAsmHE\0" + /* 4764 */ "CLGITAsmHE\0" + /* 4775 */ "CLTAsmHE\0" + /* 4784 */ "CRTAsmHE\0" + /* 4793 */ "CGRTAsmHE\0" + /* 4803 */ "CLGRTAsmHE\0" + /* 4814 */ "CLRTAsmHE\0" + /* 4824 */ "InsnRIE\0" + /* 4832 */ "SIE\0" + /* 4836 */ "STCKE\0" + /* 4842 */ "ISKE\0" + /* 4847 */ "SSKE\0" + /* 4852 */ "VMALE\0" + /* 4858 */ "G_JUMP_TABLE\0" + /* 4871 */ "CLCLE\0" + /* 4877 */ "MVCLE\0" + /* 4883 */ "BUNDLE\0" + /* 4890 */ "STFLE\0" + /* 4896 */ "VMLE\0" + /* 4901 */ "CIBAsmNLE\0" + /* 4911 */ "CGIBAsmNLE\0" + /* 4922 */ "CLGIBAsmNLE\0" + /* 4934 */ "CLIBAsmNLE\0" + /* 4945 */ "CRBAsmNLE\0" + /* 4955 */ "CGRBAsmNLE\0" + /* 4966 */ "CLGRBAsmNLE\0" + /* 4978 */ "CLRBAsmNLE\0" + /* 4989 */ "LOCAsmNLE\0" + /* 4999 */ "STOCAsmNLE\0" + /* 5010 */ "LOCGAsmNLE\0" + /* 5021 */ "STOCGAsmNLE\0" + /* 5033 */ "JGAsmNLE\0" + /* 5042 */ "LOCFHAsmNLE\0" + /* 5054 */ "STOCFHAsmNLE\0" + /* 5067 */ "BIAsmNLE\0" + /* 5076 */ "LOCHIAsmNLE\0" + /* 5088 */ "LOCGHIAsmNLE\0" + /* 5101 */ "LOCHHIAsmNLE\0" + /* 5114 */ "CIJAsmNLE\0" + /* 5124 */ "CGIJAsmNLE\0" + /* 5135 */ "CLGIJAsmNLE\0" + /* 5147 */ "CLIJAsmNLE\0" + /* 5158 */ "CRJAsmNLE\0" + /* 5168 */ "CGRJAsmNLE\0" + /* 5179 */ "CLGRJAsmNLE\0" + /* 5191 */ "CLRJAsmNLE\0" + /* 5202 */ "BRAsmNLE\0" + /* 5211 */ "LOCRAsmNLE\0" + /* 5222 */ "LOCGRAsmNLE\0" + /* 5234 */ "SELGRAsmNLE\0" + /* 5246 */ "LOCFHRAsmNLE\0" + /* 5259 */ "SELFHRAsmNLE\0" + /* 5272 */ "SELRAsmNLE\0" + /* 5283 */ "CLGTAsmNLE\0" + /* 5294 */ "CITAsmNLE\0" + /* 5304 */ "CLFITAsmNLE\0" + /* 5316 */ "CGITAsmNLE\0" + /* 5327 */ "CLGITAsmNLE\0" + /* 5339 */ "CLTAsmNLE\0" + /* 5349 */ "CRTAsmNLE\0" + /* 5359 */ "CGRTAsmNLE\0" + /* 5370 */ "CLGRTAsmNLE\0" + /* 5382 */ "CLRTAsmNLE\0" + /* 5393 */ "BXLE\0" + /* 5398 */ "BRXLE\0" + /* 5404 */ "CIBAsmLE\0" + /* 5413 */ "CGIBAsmLE\0" + /* 5423 */ "CLGIBAsmLE\0" + /* 5434 */ "CLIBAsmLE\0" + /* 5444 */ "CRBAsmLE\0" + /* 5453 */ "CGRBAsmLE\0" + /* 5463 */ "CLGRBAsmLE\0" + /* 5474 */ "CLRBAsmLE\0" + /* 5484 */ "LOCAsmLE\0" + /* 5493 */ "STOCAsmLE\0" + /* 5503 */ "LOCGAsmLE\0" + /* 5513 */ "STOCGAsmLE\0" + /* 5524 */ "JGAsmLE\0" + /* 5532 */ "LOCFHAsmLE\0" + /* 5543 */ "STOCFHAsmLE\0" + /* 5555 */ "BIAsmLE\0" + /* 5563 */ "LOCHIAsmLE\0" + /* 5574 */ "LOCGHIAsmLE\0" + /* 5586 */ "LOCHHIAsmLE\0" + /* 5598 */ "CIJAsmLE\0" + /* 5607 */ "CGIJAsmLE\0" + /* 5617 */ "CLGIJAsmLE\0" + /* 5628 */ "CLIJAsmLE\0" + /* 5638 */ "CRJAsmLE\0" + /* 5647 */ "CGRJAsmLE\0" + /* 5657 */ "CLGRJAsmLE\0" + /* 5668 */ "CLRJAsmLE\0" + /* 5678 */ "BRAsmLE\0" + /* 5686 */ "LOCRAsmLE\0" + /* 5696 */ "LOCGRAsmLE\0" + /* 5707 */ "SELGRAsmLE\0" + /* 5718 */ "LOCFHRAsmLE\0" + /* 5730 */ "SELFHRAsmLE\0" + /* 5742 */ "SELRAsmLE\0" + /* 5752 */ "CLGTAsmLE\0" + /* 5762 */ "CITAsmLE\0" + /* 5771 */ "CLFITAsmLE\0" + /* 5782 */ "CGITAsmLE\0" + /* 5792 */ "CLGITAsmLE\0" + /* 5803 */ "CLTAsmLE\0" + /* 5812 */ "CRTAsmLE\0" + /* 5821 */ "CGRTAsmLE\0" + /* 5831 */ "CLGRTAsmLE\0" + /* 5842 */ "CLRTAsmLE\0" + /* 5852 */ "VME\0" + /* 5856 */ "VFENE\0" + /* 5862 */ "G_MEMCPY_INLINE\0" + /* 5878 */ "VONE\0" + /* 5883 */ "CIBAsmNE\0" + /* 5892 */ "CGIBAsmNE\0" + /* 5902 */ "CLGIBAsmNE\0" + /* 5913 */ "CLIBAsmNE\0" + /* 5923 */ "CRBAsmNE\0" + /* 5932 */ "CGRBAsmNE\0" + /* 5942 */ "CLGRBAsmNE\0" + /* 5953 */ "CLRBAsmNE\0" + /* 5963 */ "LOCAsmNE\0" + /* 5972 */ "STOCAsmNE\0" + /* 5982 */ "LOCGAsmNE\0" + /* 5992 */ "STOCGAsmNE\0" + /* 6003 */ "JGAsmNE\0" + /* 6011 */ "LOCFHAsmNE\0" + /* 6022 */ "STOCFHAsmNE\0" + /* 6034 */ "BIAsmNE\0" + /* 6042 */ "LOCHIAsmNE\0" + /* 6053 */ "LOCGHIAsmNE\0" + /* 6065 */ "LOCHHIAsmNE\0" + /* 6077 */ "CIJAsmNE\0" + /* 6086 */ "CGIJAsmNE\0" + /* 6096 */ "CLGIJAsmNE\0" + /* 6107 */ "CLIJAsmNE\0" + /* 6117 */ "CRJAsmNE\0" + /* 6126 */ "CGRJAsmNE\0" + /* 6136 */ "CLGRJAsmNE\0" + /* 6147 */ "CLRJAsmNE\0" + /* 6157 */ "BRAsmNE\0" + /* 6165 */ "LOCRAsmNE\0" + /* 6175 */ "LOCGRAsmNE\0" + /* 6186 */ "SELGRAsmNE\0" + /* 6197 */ "LOCFHRAsmNE\0" + /* 6209 */ "SELFHRAsmNE\0" + /* 6221 */ "SELRAsmNE\0" + /* 6231 */ "CLGTAsmNE\0" + /* 6241 */ "CITAsmNE\0" + /* 6250 */ "CLFITAsmNE\0" + /* 6261 */ "CGITAsmNE\0" + /* 6271 */ "CLGITAsmNE\0" + /* 6282 */ "CLTAsmNE\0" + /* 6291 */ "CRTAsmNE\0" + /* 6300 */ "CGRTAsmNE\0" + /* 6310 */ "CLGRTAsmNE\0" + /* 6321 */ "CLRTAsmNE\0" + /* 6331 */ "LOCAL_ESCAPE\0" + /* 6344 */ "SQE\0" + /* 6348 */ "G_INDEXED_STORE\0" + /* 6364 */ "G_STORE\0" + /* 6372 */ "InsnRRE\0" + /* 6380 */ "TRTRE\0" + /* 6386 */ "MSE\0" + /* 6390 */ "G_BITREVERSE\0" + /* 6403 */ "InsnRSE\0" + /* 6411 */ "InsnSSE\0" + /* 6419 */ "CUSE\0" + /* 6424 */ "IDTE\0" + /* 6429 */ "CRDTE\0" + /* 6435 */ "IPTE\0" + /* 6440 */ "TRTE\0" + /* 6445 */ "STE\0" + /* 6449 */ "DBG_VALUE\0" + /* 6459 */ "G_GLOBAL_VALUE\0" + /* 6474 */ "G_MEMMOVE\0" + /* 6484 */ "LPSWE\0" + /* 6490 */ "LXE\0" + /* 6494 */ "InsnRXE\0" + /* 6502 */ "G_FREEZE\0" + /* 6511 */ "G_FCANONICALIZE\0" + /* 6527 */ "VLLEBRZE\0" + /* 6536 */ "CIBAsmE\0" + /* 6544 */ "CGIBAsmE\0" + /* 6553 */ "CLGIBAsmE\0" + /* 6563 */ "CLIBAsmE\0" + /* 6572 */ "CRBAsmE\0" + /* 6580 */ "CGRBAsmE\0" + /* 6589 */ "CLGRBAsmE\0" + /* 6599 */ "CLRBAsmE\0" + /* 6608 */ "LOCAsmE\0" + /* 6616 */ "STOCAsmE\0" + /* 6625 */ "LOCGAsmE\0" + /* 6634 */ "STOCGAsmE\0" + /* 6644 */ "JGAsmE\0" + /* 6651 */ "LOCFHAsmE\0" + /* 6661 */ "STOCFHAsmE\0" + /* 6672 */ "BIAsmE\0" + /* 6679 */ "LOCHIAsmE\0" + /* 6689 */ "LOCGHIAsmE\0" + /* 6700 */ "LOCHHIAsmE\0" + /* 6711 */ "CIJAsmE\0" + /* 6719 */ "CGIJAsmE\0" + /* 6728 */ "CLGIJAsmE\0" + /* 6738 */ "CLIJAsmE\0" + /* 6747 */ "CRJAsmE\0" + /* 6755 */ "CGRJAsmE\0" + /* 6764 */ "CLGRJAsmE\0" + /* 6774 */ "CLRJAsmE\0" + /* 6783 */ "BRAsmE\0" + /* 6790 */ "LOCRAsmE\0" + /* 6799 */ "LOCGRAsmE\0" + /* 6809 */ "SELGRAsmE\0" + /* 6819 */ "LOCFHRAsmE\0" + /* 6830 */ "SELFHRAsmE\0" + /* 6841 */ "SELRAsmE\0" + /* 6850 */ "CLGTAsmE\0" + /* 6859 */ "CITAsmE\0" + /* 6867 */ "CLFITAsmE\0" + /* 6877 */ "CGITAsmE\0" + /* 6886 */ "CLGITAsmE\0" + /* 6896 */ "CLTAsmE\0" + /* 6904 */ "CRTAsmE\0" + /* 6912 */ "CGRTAsmE\0" + /* 6921 */ "CLGRTAsmE\0" + /* 6931 */ "CLRTAsmE\0" + /* 6940 */ "InsnE\0" + /* 6946 */ "VGFMAF\0" + /* 6953 */ "VESRAF\0" + /* 6960 */ "VAF\0" + /* 6964 */ "SACF\0" + /* 6969 */ "VACCF\0" + /* 6975 */ "VECF\0" + /* 6980 */ "VLCF\0" + /* 6985 */ "VSTRCF\0" + /* 6992 */ "VFAEF\0" + /* 6998 */ "VMAEF\0" + /* 7004 */ "VSCEF\0" + /* 7010 */ "G_CTLZ_ZERO_UNDEF\0" + /* 7028 */ "G_CTTZ_ZERO_UNDEF\0" + /* 7046 */ "G_IMPLICIT_DEF\0" + /* 7061 */ "VFEEF\0" + /* 7067 */ "VGEF\0" + /* 7072 */ "VMALEF\0" + /* 7079 */ "VMLEF\0" + /* 7085 */ "VLEF\0" + /* 7090 */ "VMEF\0" + /* 7095 */ "VFENEF\0" + /* 7102 */ "DBG_INSTR_REF\0" + /* 7116 */ "VSTEF\0" + /* 7122 */ "PTFF\0" + /* 7127 */ "AGF\0" + /* 7131 */ "CGF\0" + /* 7135 */ "VSEGF\0" + /* 7141 */ "ALGF\0" + /* 7146 */ "CLGF\0" + /* 7151 */ "LLGF\0" + /* 7156 */ "SLGF\0" + /* 7161 */ "VSUMGF\0" + /* 7168 */ "LLZRGF\0" + /* 7175 */ "DSGF\0" + /* 7180 */ "MSGF\0" + /* 7185 */ "LTGF\0" + /* 7190 */ "VAVGF\0" + /* 7196 */ "VLVGF\0" + /* 7202 */ "VMAHF\0" + /* 7208 */ "VCHF\0" + /* 7213 */ "IIHF\0" + /* 7218 */ "LLIHF\0" + /* 7224 */ "NIHF\0" + /* 7229 */ "OIHF\0" + /* 7234 */ "XIHF\0" + /* 7239 */ "VMALHF\0" + /* 7246 */ "CLHF\0" + /* 7251 */ "VMLHF\0" + /* 7257 */ "VUPLHF\0" + /* 7264 */ "VMHF\0" + /* 7269 */ "VUPHF\0" + /* 7275 */ "VMRHF\0" + /* 7281 */ "VSCBIF\0" + /* 7288 */ "VLEIF\0" + /* 7294 */ "VREPIF\0" + /* 7301 */ "STCKF\0" + /* 7307 */ "VPKF\0" + /* 7312 */ "VMALF\0" + /* 7318 */ "VECLF\0" + /* 7324 */ "VAVGLF\0" + /* 7331 */ "VCHLF\0" + /* 7337 */ "IILF\0" + /* 7342 */ "LLILF\0" + /* 7348 */ "ATOMIC_LOAD_NILF\0" + /* 7365 */ "ATOMIC_LOAD_OILF\0" + /* 7382 */ "ATOMIC_LOAD_XILF\0" + /* 7399 */ "ATOMIC_LOADW_XILF\0" + /* 7417 */ "VUPLLF\0" + /* 7424 */ "VERLLF\0" + /* 7431 */ "VMLF\0" + /* 7436 */ "VMNLF\0" + /* 7442 */ "VUPLF\0" + /* 7448 */ "VMRLF\0" + /* 7454 */ "VESRLF\0" + /* 7461 */ "VESLF\0" + /* 7467 */ "VMXLF\0" + /* 7473 */ "VLLEZLF\0" + /* 7481 */ "VGFMF\0" + /* 7487 */ "PFMF\0" + /* 7492 */ "VGMF\0" + /* 7497 */ "VERIMF\0" + /* 7504 */ "KMF\0" + /* 7508 */ "VCNF\0" + /* 7513 */ "VMNF\0" + /* 7518 */ "VCRNF\0" + /* 7524 */ "VMAOF\0" + /* 7530 */ "VMALOF\0" + /* 7537 */ "VMLOF\0" + /* 7543 */ "VMOF\0" + /* 7548 */ "VLREPF\0" + /* 7555 */ "VLBRREPF\0" + /* 7564 */ "VREPF\0" + /* 7570 */ "SCKPF\0" + /* 7576 */ "VLPF\0" + /* 7581 */ "VCEQF\0" + /* 7587 */ "VSUMQF\0" + /* 7594 */ "VLEBRF\0" + /* 7601 */ "VSTEBRF\0" + /* 7609 */ "VLBRF\0" + /* 7615 */ "VSTBRF\0" + /* 7622 */ "VLERF\0" + /* 7628 */ "VSTERF\0" + /* 7635 */ "InsnRRF\0" + /* 7643 */ "VISTRF\0" + /* 7650 */ "LZRF\0" + /* 7655 */ "VPKSF\0" + /* 7661 */ "VPKLSF\0" + /* 7668 */ "VSTRSF\0" + /* 7675 */ "InsnSSF\0" + /* 7683 */ "VSF\0" + /* 7687 */ "VPOPCTF\0" + /* 7695 */ "PTF\0" + /* 7699 */ "CUUTF\0" + /* 7705 */ "VESRAVF\0" + /* 7713 */ "VLGVF\0" + /* 7719 */ "VERLLVF\0" + /* 7727 */ "VESRLVF\0" + /* 7735 */ "VESLVF\0" + /* 7742 */ "VMXF\0" + /* 7747 */ "InsnRXF\0" + /* 7755 */ "VSTRCZF\0" + /* 7763 */ "VFAEZF\0" + /* 7770 */ "VFEEZF\0" + /* 7777 */ "VLLEZF\0" + /* 7784 */ "VFENEZF\0" + /* 7792 */ "VCLZF\0" + /* 7798 */ "VLLEBRZF\0" + /* 7807 */ "VSTRSZF\0" + /* 7815 */ "VCTZF\0" + /* 7821 */ "LAAG\0" + /* 7826 */ "ECAG\0" + /* 7831 */ "DIAG\0" + /* 7836 */ "SLAG\0" + /* 7841 */ "VGFMAG\0" + /* 7848 */ "LRAG\0" + /* 7853 */ "VESRAG\0" + /* 7860 */ "STRAG\0" + /* 7866 */ "LURAG\0" + /* 7872 */ "VAG\0" + /* 7876 */ "SLBG\0" + /* 7881 */ "RISBG\0" + /* 7887 */ "RNSBG\0" + /* 7893 */ "ROSBG\0" + /* 7899 */ "RXSBG\0" + /* 7905 */ "VCVBG\0" + /* 7911 */ "TRACG\0" + /* 7917 */ "VACCG\0" + /* 7923 */ "VECG\0" + /* 7928 */ "ALCG\0" + /* 7933 */ "VLCG\0" + /* 7938 */ "LOCG\0" + /* 7943 */ "STOCG\0" + /* 7949 */ "VCDG\0" + /* 7954 */ "LPDG\0" + /* 7959 */ "VCVDG\0" + /* 7965 */ "VSCEG\0" + /* 7971 */ "VGEG\0" + /* 7976 */ "VLEG\0" + /* 7981 */ "BXLEG\0" + /* 7987 */ "G_FNEG\0" + /* 7994 */ "EXTRACT_SUBREG\0" + /* 8009 */ "INSERT_SUBREG\0" + /* 8023 */ "EREG\0" + /* 8028 */ "G_SEXT_INREG\0" + /* 8041 */ "SUBREG_TO_REG\0" + /* 8055 */ "VSEG\0" + /* 8060 */ "VSTEG\0" + /* 8066 */ "EREGG\0" + /* 8072 */ "LGG\0" + /* 8076 */ "VAVGG\0" + /* 8082 */ "VLVGG\0" + /* 8088 */ "RISBHG\0" + /* 8095 */ "VCHG\0" + /* 8100 */ "G_ATOMIC_CMPXCHG\0" + /* 8117 */ "G_ATOMICRMW_XCHG\0" + /* 8134 */ "VMRHG\0" + /* 8140 */ "BXHG\0" + /* 8145 */ "BRXHG\0" + /* 8151 */ "VSCBIG\0" + /* 8158 */ "VLEIG\0" + /* 8164 */ "VREPIG\0" + /* 8171 */ "CallJG\0" + /* 8178 */ "VPKG\0" + /* 8183 */ "LAALG\0" + /* 8189 */ "RISBLG\0" + /* 8196 */ "VECLG\0" + /* 8202 */ "VCDLG\0" + /* 8208 */ "VAVGLG\0" + /* 8215 */ "VCHLG\0" + /* 8221 */ "VERLLG\0" + /* 8228 */ "SLLG\0" + /* 8233 */ "MLG\0" + /* 8237 */ "VMNLG\0" + /* 8243 */ "VMRLG\0" + /* 8249 */ "VESRLG\0" + /* 8256 */ "VESLG\0" + /* 8262 */ "VMSLG\0" + /* 8268 */ "LCTLG\0" + /* 8274 */ "VMXLG\0" + /* 8280 */ "BRXLG\0" + /* 8286 */ "VGFMG\0" + /* 8292 */ "VGMG\0" + /* 8297 */ "VERIMG\0" + /* 8304 */ "LMG\0" + /* 8308 */ "STMG\0" + /* 8313 */ "VSUMG\0" + /* 8319 */ "LANG\0" + /* 8324 */ "VMNG\0" + /* 8329 */ "LAOG\0" + /* 8334 */ "G_FLOG\0" + /* 8341 */ "VLREPG\0" + /* 8348 */ "VLBRREPG\0" + /* 8357 */ "VREPG\0" + /* 8363 */ "VLPG\0" + /* 8368 */ "CSPG\0" + /* 8373 */ "MVPG\0" + /* 8378 */ "VCEQG\0" + /* 8384 */ "VSUMQG\0" + /* 8391 */ "G_VAARG\0" + /* 8399 */ "PREALLOCATED_ARG\0" + /* 8416 */ "VLEBRG\0" + /* 8423 */ "VSTEBRG\0" + /* 8431 */ "VLBRG\0" + /* 8437 */ "VSTBRG\0" + /* 8444 */ "VLERG\0" + /* 8450 */ "VSTERG\0" + /* 8457 */ "STURG\0" + /* 8463 */ "LZRG\0" + /* 8468 */ "BSG\0" + /* 8472 */ "CSG\0" + /* 8476 */ "CDSG\0" + /* 8481 */ "LLGFSG\0" + /* 8488 */ "VPKSG\0" + /* 8494 */ "VPKLSG\0" + /* 8501 */ "MSG\0" + /* 8505 */ "VSG\0" + /* 8509 */ "BCTG\0" + /* 8514 */ "ECTG\0" + /* 8519 */ "VPOPCTG\0" + /* 8527 */ "BRCTG\0" + /* 8533 */ "STCTG\0" + /* 8539 */ "LTG\0" + /* 8543 */ "NTSTG\0" + /* 8549 */ "VESRAVG\0" + /* 8557 */ "VAVG\0" + /* 8562 */ "VLGVG\0" + /* 8568 */ "VERLLVG\0" + /* 8576 */ "VESRLVG\0" + /* 8584 */ "VESLVG\0" + /* 8591 */ "VLVG\0" + /* 8596 */ "LRVG\0" + /* 8601 */ "STRVG\0" + /* 8607 */ "LAXG\0" + /* 8612 */ "VMXG\0" + /* 8617 */ "VLLEZG\0" + /* 8624 */ "VCLZG\0" + /* 8630 */ "VLLEBRZG\0" + /* 8639 */ "VCTZG\0" + /* 8645 */ "VGFMAH\0" + /* 8652 */ "VMAH\0" + /* 8657 */ "VESRAH\0" + /* 8664 */ "VAH\0" + /* 8668 */ "LBH\0" + /* 8672 */ "VACCH\0" + /* 8678 */ "VECH\0" + /* 8683 */ "VFCH\0" + /* 8688 */ "LLCH\0" + /* 8693 */ "VLCH\0" + /* 8698 */ "VSTRCH\0" + /* 8705 */ "CSCH\0" + /* 8710 */ "HSCH\0" + /* 8715 */ "MSCH\0" + /* 8720 */ "RSCH\0" + /* 8725 */ "SSCH\0" + /* 8730 */ "STSCH\0" + /* 8736 */ "XSCH\0" + /* 8741 */ "STCH\0" + /* 8746 */ "VCH\0" + /* 8750 */ "VFAEH\0" + /* 8756 */ "VMAEH\0" + /* 8762 */ "VFEEH\0" + /* 8768 */ "VMALEH\0" + /* 8775 */ "VMLEH\0" + /* 8781 */ "VLEH\0" + /* 8786 */ "VMEH\0" + /* 8791 */ "VFENEH\0" + /* 8798 */ "VSTEH\0" + /* 8804 */ "LOCFH\0" + /* 8810 */ "STOCFH\0" + /* 8817 */ "LFH\0" + /* 8821 */ "STFH\0" + /* 8826 */ "AGH\0" + /* 8830 */ "CGH\0" + /* 8834 */ "VSEGH\0" + /* 8840 */ "LLGH\0" + /* 8845 */ "VSUMGH\0" + /* 8852 */ "SGH\0" + /* 8856 */ "VAVGH\0" + /* 8862 */ "VLVGH\0" + /* 8868 */ "VMAHH\0" + /* 8874 */ "RISBHH\0" + /* 8881 */ "VCHH\0" + /* 8886 */ "IIHH\0" + /* 8891 */ "LLIHH\0" + /* 8897 */ "NIHH\0" + /* 8902 */ "OIHH\0" + /* 8907 */ "VMALHH\0" + /* 8914 */ "LLHH\0" + /* 8919 */ "VMLHH\0" + /* 8925 */ "VUPLHH\0" + /* 8932 */ "TMHH\0" + /* 8937 */ "VMHH\0" + /* 8942 */ "VUPHH\0" + /* 8948 */ "VMRHH\0" + /* 8954 */ "STHH\0" + /* 8959 */ "AIH\0" + /* 8963 */ "VSCBIH\0" + /* 8970 */ "CIH\0" + /* 8974 */ "VLEIH\0" + /* 8980 */ "CLIH\0" + /* 8985 */ "VREPIH\0" + /* 8992 */ "ALSIH\0" + /* 8998 */ "VPKH\0" + /* 9003 */ "VMALH\0" + /* 9009 */ "RISBLH\0" + /* 9016 */ "VECLH\0" + /* 9022 */ "VAVGLH\0" + /* 9029 */ "VCHLH\0" + /* 9035 */ "IILH\0" + /* 9040 */ "LLILH\0" + /* 9046 */ "ATOMIC_LOAD_NILH\0" + /* 9063 */ "ATOMIC_LOADW_NILH\0" + /* 9081 */ "ATOMIC_LOAD_OILH\0" + /* 9098 */ "ATOMIC_LOADW_OILH\0" + /* 9116 */ "VUPLLH\0" + /* 9123 */ "VERLLH\0" + /* 9130 */ "TMLH\0" + /* 9135 */ "VMLH\0" + /* 9140 */ "VMNLH\0" + /* 9146 */ "CIBAsmNLH\0" + /* 9156 */ "CGIBAsmNLH\0" + /* 9167 */ "CLGIBAsmNLH\0" + /* 9179 */ "CLIBAsmNLH\0" + /* 9190 */ "CRBAsmNLH\0" + /* 9200 */ "CGRBAsmNLH\0" + /* 9211 */ "CLGRBAsmNLH\0" + /* 9223 */ "CLRBAsmNLH\0" + /* 9234 */ "LOCAsmNLH\0" + /* 9244 */ "STOCAsmNLH\0" + /* 9255 */ "LOCGAsmNLH\0" + /* 9266 */ "STOCGAsmNLH\0" + /* 9278 */ "JGAsmNLH\0" + /* 9287 */ "LOCFHAsmNLH\0" + /* 9299 */ "STOCFHAsmNLH\0" + /* 9312 */ "BIAsmNLH\0" + /* 9321 */ "LOCHIAsmNLH\0" + /* 9333 */ "LOCGHIAsmNLH\0" + /* 9346 */ "LOCHHIAsmNLH\0" + /* 9359 */ "CIJAsmNLH\0" + /* 9369 */ "CGIJAsmNLH\0" + /* 9380 */ "CLGIJAsmNLH\0" + /* 9392 */ "CLIJAsmNLH\0" + /* 9403 */ "CRJAsmNLH\0" + /* 9413 */ "CGRJAsmNLH\0" + /* 9424 */ "CLGRJAsmNLH\0" + /* 9436 */ "CLRJAsmNLH\0" + /* 9447 */ "BRAsmNLH\0" + /* 9456 */ "LOCRAsmNLH\0" + /* 9467 */ "LOCGRAsmNLH\0" + /* 9479 */ "SELGRAsmNLH\0" + /* 9491 */ "LOCFHRAsmNLH\0" + /* 9504 */ "SELFHRAsmNLH\0" + /* 9517 */ "SELRAsmNLH\0" + /* 9528 */ "CLGTAsmNLH\0" + /* 9539 */ "CITAsmNLH\0" + /* 9549 */ "CLFITAsmNLH\0" + /* 9561 */ "CGITAsmNLH\0" + /* 9572 */ "CLGITAsmNLH\0" + /* 9584 */ "CLTAsmNLH\0" + /* 9594 */ "CRTAsmNLH\0" + /* 9604 */ "CGRTAsmNLH\0" + /* 9615 */ "CLGRTAsmNLH\0" + /* 9627 */ "CLRTAsmNLH\0" + /* 9638 */ "VUPLH\0" + /* 9644 */ "VMRLH\0" + /* 9650 */ "VESRLH\0" + /* 9657 */ "VESLH\0" + /* 9663 */ "G_SMULH\0" + /* 9671 */ "G_UMULH\0" + /* 9679 */ "VMXLH\0" + /* 9685 */ "CIBAsmLH\0" + /* 9694 */ "CGIBAsmLH\0" + /* 9704 */ "CLGIBAsmLH\0" + /* 9715 */ "CLIBAsmLH\0" + /* 9725 */ "CRBAsmLH\0" + /* 9734 */ "CGRBAsmLH\0" + /* 9744 */ "CLGRBAsmLH\0" + /* 9755 */ "CLRBAsmLH\0" + /* 9765 */ "LOCAsmLH\0" + /* 9774 */ "STOCAsmLH\0" + /* 9784 */ "LOCGAsmLH\0" + /* 9794 */ "STOCGAsmLH\0" + /* 9805 */ "JGAsmLH\0" + /* 9813 */ "LOCFHAsmLH\0" + /* 9824 */ "STOCFHAsmLH\0" + /* 9836 */ "BIAsmLH\0" + /* 9844 */ "LOCHIAsmLH\0" + /* 9855 */ "LOCGHIAsmLH\0" + /* 9867 */ "LOCHHIAsmLH\0" + /* 9879 */ "CIJAsmLH\0" + /* 9888 */ "CGIJAsmLH\0" + /* 9898 */ "CLGIJAsmLH\0" + /* 9909 */ "CLIJAsmLH\0" + /* 9919 */ "CRJAsmLH\0" + /* 9928 */ "CGRJAsmLH\0" + /* 9938 */ "CLGRJAsmLH\0" + /* 9949 */ "CLRJAsmLH\0" + /* 9959 */ "BRAsmLH\0" + /* 9967 */ "LOCRAsmLH\0" + /* 9977 */ "LOCGRAsmLH\0" + /* 9988 */ "SELGRAsmLH\0" + /* 9999 */ "LOCFHRAsmLH\0" + /* 10011 */ "SELFHRAsmLH\0" + /* 10023 */ "SELRAsmLH\0" + /* 10033 */ "CLGTAsmLH\0" + /* 10043 */ "CITAsmLH\0" + /* 10052 */ "CLFITAsmLH\0" + /* 10063 */ "CGITAsmLH\0" + /* 10073 */ "CLGITAsmLH\0" + /* 10084 */ "CLTAsmLH\0" + /* 10093 */ "CRTAsmLH\0" + /* 10102 */ "CGRTAsmLH\0" + /* 10112 */ "CLGRTAsmLH\0" + /* 10123 */ "CLRTAsmLH\0" + /* 10133 */ "ICMH\0" + /* 10138 */ "STCMH\0" + /* 10144 */ "VGFMH\0" + /* 10150 */ "VGMH\0" + /* 10155 */ "VERIMH\0" + /* 10162 */ "CLMH\0" + /* 10167 */ "STMH\0" + /* 10172 */ "VSUMH\0" + /* 10178 */ "VMH\0" + /* 10182 */ "VCLFNH\0" + /* 10189 */ "VMNH\0" + /* 10194 */ "CIBAsmNH\0" + /* 10203 */ "CGIBAsmNH\0" + /* 10213 */ "CLGIBAsmNH\0" + /* 10224 */ "CLIBAsmNH\0" + /* 10234 */ "CRBAsmNH\0" + /* 10243 */ "CGRBAsmNH\0" + /* 10253 */ "CLGRBAsmNH\0" + /* 10264 */ "CLRBAsmNH\0" + /* 10274 */ "LOCAsmNH\0" + /* 10283 */ "STOCAsmNH\0" + /* 10293 */ "LOCGAsmNH\0" + /* 10303 */ "STOCGAsmNH\0" + /* 10314 */ "JGAsmNH\0" + /* 10322 */ "LOCFHAsmNH\0" + /* 10333 */ "STOCFHAsmNH\0" + /* 10345 */ "BIAsmNH\0" + /* 10353 */ "LOCHIAsmNH\0" + /* 10364 */ "LOCGHIAsmNH\0" + /* 10376 */ "LOCHHIAsmNH\0" + /* 10388 */ "CIJAsmNH\0" + /* 10397 */ "CGIJAsmNH\0" + /* 10407 */ "CLGIJAsmNH\0" + /* 10418 */ "CLIJAsmNH\0" + /* 10428 */ "CRJAsmNH\0" + /* 10437 */ "CGRJAsmNH\0" + /* 10447 */ "CLGRJAsmNH\0" + /* 10458 */ "CLRJAsmNH\0" + /* 10468 */ "BRAsmNH\0" + /* 10476 */ "LOCRAsmNH\0" + /* 10486 */ "LOCGRAsmNH\0" + /* 10497 */ "SELGRAsmNH\0" + /* 10508 */ "LOCFHRAsmNH\0" + /* 10520 */ "SELFHRAsmNH\0" + /* 10532 */ "SELRAsmNH\0" + /* 10542 */ "CLGTAsmNH\0" + /* 10552 */ "CITAsmNH\0" + /* 10561 */ "CLFITAsmNH\0" + /* 10572 */ "CGITAsmNH\0" + /* 10582 */ "CLGITAsmNH\0" + /* 10593 */ "CLTAsmNH\0" + /* 10602 */ "CRTAsmNH\0" + /* 10611 */ "CGRTAsmNH\0" + /* 10621 */ "CLGRTAsmNH\0" + /* 10632 */ "CLRTAsmNH\0" + /* 10642 */ "VMAOH\0" + /* 10648 */ "VMALOH\0" + /* 10655 */ "VMLOH\0" + /* 10661 */ "VMOH\0" + /* 10666 */ "VLREPH\0" + /* 10673 */ "VLBRREPH\0" + /* 10682 */ "VREPH\0" + /* 10688 */ "VLPH\0" + /* 10693 */ "VCSPH\0" + /* 10699 */ "VUPH\0" + /* 10704 */ "VCEQH\0" + /* 10710 */ "VLEBRH\0" + /* 10717 */ "VSTEBRH\0" + /* 10725 */ "VLBRH\0" + /* 10731 */ "VSTBRH\0" + /* 10738 */ "VLERH\0" + /* 10744 */ "VSTERH\0" + /* 10751 */ "VMRH\0" + /* 10756 */ "VISTRH\0" + /* 10763 */ "VPKSH\0" + /* 10769 */ "VPKLSH\0" + /* 10776 */ "VSTRSH\0" + /* 10783 */ "VSH\0" + /* 10787 */ "VPOPCTH\0" + /* 10795 */ "BRCTH\0" + /* 10801 */ "STH\0" + /* 10805 */ "VESRAVH\0" + /* 10813 */ "VLGVH\0" + /* 10819 */ "VERLLVH\0" + /* 10827 */ "VESRLVH\0" + /* 10835 */ "VESLVH\0" + /* 10842 */ "LRVH\0" + /* 10847 */ "STRVH\0" + /* 10853 */ "BXH\0" + /* 10857 */ "VMXH\0" + /* 10862 */ "BRXH\0" + /* 10867 */ "MAYH\0" + /* 10872 */ "MYH\0" + /* 10876 */ "VSTRCZH\0" + /* 10884 */ "VFAEZH\0" + /* 10891 */ "VFEEZH\0" + /* 10898 */ "VLLEZH\0" + /* 10905 */ "VFENEZH\0" + /* 10913 */ "VUPKZH\0" + /* 10920 */ "VCLZH\0" + /* 10926 */ "VLLEBRZH\0" + /* 10935 */ "VSTRSZH\0" + /* 10943 */ "VCTZH\0" + /* 10949 */ "CIBAsmH\0" + /* 10957 */ "CGIBAsmH\0" + /* 10966 */ "CLGIBAsmH\0" + /* 10976 */ "CLIBAsmH\0" + /* 10985 */ "CRBAsmH\0" + /* 10993 */ "CGRBAsmH\0" + /* 11002 */ "CLGRBAsmH\0" + /* 11012 */ "CLRBAsmH\0" + /* 11021 */ "LOCAsmH\0" + /* 11029 */ "STOCAsmH\0" + /* 11038 */ "LOCGAsmH\0" + /* 11047 */ "STOCGAsmH\0" + /* 11057 */ "JGAsmH\0" + /* 11064 */ "LOCFHAsmH\0" + /* 11074 */ "STOCFHAsmH\0" + /* 11085 */ "BIAsmH\0" + /* 11092 */ "LOCHIAsmH\0" + /* 11102 */ "LOCGHIAsmH\0" + /* 11113 */ "LOCHHIAsmH\0" + /* 11124 */ "CIJAsmH\0" + /* 11132 */ "CGIJAsmH\0" + /* 11141 */ "CLGIJAsmH\0" + /* 11151 */ "CLIJAsmH\0" + /* 11160 */ "CRJAsmH\0" + /* 11168 */ "CGRJAsmH\0" + /* 11177 */ "CLGRJAsmH\0" + /* 11187 */ "CLRJAsmH\0" + /* 11196 */ "BRAsmH\0" + /* 11203 */ "LOCRAsmH\0" + /* 11212 */ "LOCGRAsmH\0" + /* 11222 */ "SELGRAsmH\0" + /* 11232 */ "LOCFHRAsmH\0" + /* 11243 */ "SELFHRAsmH\0" + /* 11254 */ "SELRAsmH\0" + /* 11263 */ "CLGTAsmH\0" + /* 11272 */ "CITAsmH\0" + /* 11280 */ "CLFITAsmH\0" + /* 11290 */ "CGITAsmH\0" + /* 11299 */ "CLGITAsmH\0" + /* 11309 */ "CLTAsmH\0" + /* 11317 */ "CRTAsmH\0" + /* 11325 */ "CGRTAsmH\0" + /* 11334 */ "CLGRTAsmH\0" + /* 11344 */ "CLRTAsmH\0" + /* 11353 */ "NIAI\0" + /* 11358 */ "VSBCBI\0" + /* 11365 */ "VSCBI\0" + /* 11371 */ "VSBI\0" + /* 11376 */ "QPACI\0" + /* 11382 */ "VFTCI\0" + /* 11388 */ "VPDI\0" + /* 11393 */ "ATOMIC_LOAD_AFI\0" + /* 11409 */ "ATOMIC_LOADW_AFI\0" + /* 11426 */ "CFI\0" + /* 11430 */ "ATOMIC_LOAD_AGFI\0" + /* 11447 */ "CGFI\0" + /* 11452 */ "ALGFI\0" + /* 11458 */ "CLGFI\0" + /* 11464 */ "SLGFI\0" + /* 11470 */ "MSGFI\0" + /* 11476 */ "ALFI\0" + /* 11481 */ "CLFI\0" + /* 11486 */ "SLFI\0" + /* 11491 */ "MSFI\0" + /* 11496 */ "VFI\0" + /* 11500 */ "ATOMIC_LOAD_AHI\0" + /* 11516 */ "LOCHI\0" + /* 11522 */ "ATOMIC_LOAD_AGHI\0" + /* 11539 */ "LOCGHI\0" + /* 11546 */ "LGHI\0" + /* 11551 */ "MGHI\0" + /* 11556 */ "MVGHI\0" + /* 11562 */ "LOCHHI\0" + /* 11569 */ "MVHHI\0" + /* 11575 */ "LHI\0" + /* 11579 */ "MHI\0" + /* 11583 */ "DBG_PHI\0" + /* 11591 */ "MVHI\0" + /* 11596 */ "CLI\0" + /* 11600 */ "NI\0" + /* 11603 */ "OI\0" + /* 11606 */ "VREPI\0" + /* 11612 */ "TPI\0" + /* 11616 */ "QCTRI\0" + /* 11622 */ "InsnVRI\0" + /* 11630 */ "InsnRI\0" + /* 11637 */ "ASI\0" + /* 11641 */ "AGSI\0" + /* 11646 */ "ALGSI\0" + /* 11652 */ "CHSI\0" + /* 11657 */ "CLFHSI\0" + /* 11664 */ "CGHSI\0" + /* 11670 */ "CLGHSI\0" + /* 11677 */ "CHHSI\0" + /* 11683 */ "CLHHSI\0" + /* 11690 */ "ALSI\0" + /* 11695 */ "G_FPTOSI\0" + /* 11704 */ "QSI\0" + /* 11708 */ "InsnRSI\0" + /* 11716 */ "STSI\0" + /* 11721 */ "InsnVSI\0" + /* 11729 */ "InsnSI\0" + /* 11736 */ "PTI\0" + /* 11740 */ "G_FPTOUI\0" + /* 11749 */ "MVI\0" + /* 11753 */ "G_FPOWI\0" + /* 11761 */ "XI\0" + /* 11764 */ "CIJ\0" + /* 11768 */ "CGIJ\0" + /* 11773 */ "CLGIJ\0" + /* 11779 */ "CLIJ\0" + /* 11784 */ "CRJ\0" + /* 11788 */ "CGRJ\0" + /* 11793 */ "CLGRJ\0" + /* 11799 */ "CLRJ\0" + /* 11804 */ "SLAK\0" + /* 11809 */ "SRAK\0" + /* 11814 */ "PACK\0" + /* 11819 */ "SCK\0" + /* 11823 */ "STCK\0" + /* 11828 */ "MVCK\0" + /* 11833 */ "MVCDK\0" + /* 11839 */ "WFK\0" + /* 11843 */ "AHIK\0" + /* 11848 */ "AGHIK\0" + /* 11854 */ "ALGHSIK\0" + /* 11862 */ "ALHSIK\0" + /* 11869 */ "SLLK\0" + /* 11874 */ "SRLK\0" + /* 11879 */ "EDMK\0" + /* 11884 */ "IPK\0" + /* 11888 */ "UNPK\0" + /* 11893 */ "VPK\0" + /* 11897 */ "ARK\0" + /* 11901 */ "NCRK\0" + /* 11906 */ "OCRK\0" + /* 11911 */ "AGRK\0" + /* 11916 */ "NCGRK\0" + /* 11922 */ "OCGRK\0" + /* 11928 */ "ALGRK\0" + /* 11934 */ "SLGRK\0" + /* 11940 */ "MGRK\0" + /* 11945 */ "NNGRK\0" + /* 11951 */ "NOGRK\0" + /* 11957 */ "SGRK\0" + /* 11962 */ "NXGRK\0" + /* 11968 */ "ALRK\0" + /* 11973 */ "SLRK\0" + /* 11978 */ "NNRK\0" + /* 11983 */ "NORK\0" + /* 11988 */ "SRK\0" + /* 11992 */ "NXRK\0" + /* 11997 */ "G_PTRMASK\0" + /* 12007 */ "MVCSK\0" + /* 12013 */ "IVSK\0" + /* 12018 */ "AHIMuxK\0" + /* 12026 */ "LAAL\0" + /* 12031 */ "BAL\0" + /* 12035 */ "VMAL\0" + /* 12040 */ "SAL\0" + /* 12044 */ "VECL\0" + /* 12049 */ "CLCL\0" + /* 12054 */ "CallBRCL\0" + /* 12063 */ "MVCL\0" + /* 12068 */ "SLDL\0" + /* 12073 */ "SRDL\0" + /* 12078 */ "GC_LABEL\0" + /* 12087 */ "DBG_LABEL\0" + /* 12097 */ "EH_LABEL\0" + /* 12106 */ "ANNOTATION_LABEL\0" + /* 12123 */ "ICALL_BRANCH_FUNNEL\0" + /* 12143 */ "VSEL\0" + /* 12148 */ "STFL\0" + /* 12153 */ "VAVGL\0" + /* 12159 */ "RISBHL\0" + /* 12166 */ "VCHL\0" + /* 12171 */ "IIHL\0" + /* 12176 */ "LLIHL\0" + /* 12182 */ "NIHL\0" + /* 12187 */ "OIHL\0" + /* 12192 */ "TMHL\0" + /* 12197 */ "G_FSHL\0" + /* 12204 */ "G_SHL\0" + /* 12210 */ "G_FCEIL\0" + /* 12218 */ "InsnRIL\0" + /* 12226 */ "InsnSIL\0" + /* 12234 */ "TLS_GDCALL\0" + /* 12245 */ "TLS_LDCALL\0" + /* 12256 */ "PATCHABLE_TAIL_CALL\0" + /* 12276 */ "PATCHABLE_TYPED_EVENT_CALL\0" + /* 12303 */ "PATCHABLE_EVENT_CALL\0" + /* 12324 */ "FENTRY_CALL\0" + /* 12336 */ "RISBLL\0" + /* 12343 */ "VFLL\0" + /* 12348 */ "IILL\0" + /* 12353 */ "KILL\0" + /* 12358 */ "LLILL\0" + /* 12364 */ "ATOMIC_LOAD_NILL\0" + /* 12381 */ "ATOMIC_LOAD_OILL\0" + /* 12398 */ "TMLL\0" + /* 12403 */ "VUPLL\0" + /* 12409 */ "VERLL\0" + /* 12415 */ "SLL\0" + /* 12419 */ "VLL\0" + /* 12423 */ "VML\0" + /* 12427 */ "VCLFNL\0" + /* 12434 */ "VMNL\0" + /* 12439 */ "CIBAsmNL\0" + /* 12448 */ "CGIBAsmNL\0" + /* 12458 */ "CLGIBAsmNL\0" + /* 12469 */ "CLIBAsmNL\0" + /* 12479 */ "CRBAsmNL\0" + /* 12488 */ "CGRBAsmNL\0" + /* 12498 */ "CLGRBAsmNL\0" + /* 12509 */ "CLRBAsmNL\0" + /* 12519 */ "LOCAsmNL\0" + /* 12528 */ "STOCAsmNL\0" + /* 12538 */ "LOCGAsmNL\0" + /* 12548 */ "STOCGAsmNL\0" + /* 12559 */ "JGAsmNL\0" + /* 12567 */ "LOCFHAsmNL\0" + /* 12578 */ "STOCFHAsmNL\0" + /* 12590 */ "BIAsmNL\0" + /* 12598 */ "LOCHIAsmNL\0" + /* 12609 */ "LOCGHIAsmNL\0" + /* 12621 */ "LOCHHIAsmNL\0" + /* 12633 */ "CIJAsmNL\0" + /* 12642 */ "CGIJAsmNL\0" + /* 12652 */ "CLGIJAsmNL\0" + /* 12663 */ "CLIJAsmNL\0" + /* 12673 */ "CRJAsmNL\0" + /* 12682 */ "CGRJAsmNL\0" + /* 12692 */ "CLGRJAsmNL\0" + /* 12703 */ "CLRJAsmNL\0" + /* 12713 */ "BRAsmNL\0" + /* 12721 */ "LOCRAsmNL\0" + /* 12731 */ "LOCGRAsmNL\0" + /* 12742 */ "SELGRAsmNL\0" + /* 12753 */ "LOCFHRAsmNL\0" + /* 12765 */ "SELFHRAsmNL\0" + /* 12777 */ "SELRAsmNL\0" + /* 12787 */ "CLGTAsmNL\0" + /* 12797 */ "CITAsmNL\0" + /* 12806 */ "CLFITAsmNL\0" + /* 12817 */ "CGITAsmNL\0" + /* 12827 */ "CLGITAsmNL\0" + /* 12838 */ "CLTAsmNL\0" + /* 12847 */ "CRTAsmNL\0" + /* 12856 */ "CGRTAsmNL\0" + /* 12866 */ "CLGRTAsmNL\0" + /* 12877 */ "CLRTAsmNL\0" + /* 12887 */ "VCFPL\0" + /* 12893 */ "VUPL\0" + /* 12898 */ "LARL\0" + /* 12903 */ "MVCRL\0" + /* 12909 */ "PFDRL\0" + /* 12915 */ "CGFRL\0" + /* 12921 */ "CLGFRL\0" + /* 12928 */ "LLGFRL\0" + /* 12935 */ "CGRL\0" + /* 12940 */ "CLGRL\0" + /* 12946 */ "STGRL\0" + /* 12952 */ "CHRL\0" + /* 12957 */ "CGHRL\0" + /* 12963 */ "CLGHRL\0" + /* 12970 */ "LLGHRL\0" + /* 12977 */ "CLHRL\0" + /* 12983 */ "LLHRL\0" + /* 12989 */ "STHRL\0" + /* 12995 */ "CLRL\0" + /* 13000 */ "VLRL\0" + /* 13005 */ "VMRL\0" + /* 13010 */ "VESRL\0" + /* 13016 */ "VSRL\0" + /* 13021 */ "VSTRL\0" + /* 13027 */ "EXRL\0" + /* 13032 */ "CallBRASL\0" + /* 13042 */ "VESL\0" + /* 13047 */ "VMSL\0" + /* 13052 */ "VSL\0" + /* 13056 */ "LCCTL\0" + /* 13062 */ "LCTL\0" + /* 13067 */ "LPCTL\0" + /* 13073 */ "LSCTL\0" + /* 13079 */ "STCTL\0" + /* 13085 */ "G_ROTL\0" + /* 13092 */ "SORTL\0" + /* 13098 */ "VSTL\0" + /* 13103 */ "G_VECREDUCE_FMUL\0" + /* 13120 */ "G_FMUL\0" + /* 13127 */ "G_VECREDUCE_SEQ_FMUL\0" + /* 13148 */ "G_STRICT_FMUL\0" + /* 13162 */ "G_VECREDUCE_MUL\0" + /* 13178 */ "G_MUL\0" + /* 13184 */ "VL\0" + /* 13187 */ "VMXL\0" + /* 13192 */ "MAYL\0" + /* 13197 */ "MYL\0" + /* 13201 */ "VUPKZL\0" + /* 13208 */ "CIBAsmL\0" + /* 13216 */ "CGIBAsmL\0" + /* 13225 */ "CLGIBAsmL\0" + /* 13235 */ "CLIBAsmL\0" + /* 13244 */ "CRBAsmL\0" + /* 13252 */ "CGRBAsmL\0" + /* 13261 */ "CLGRBAsmL\0" + /* 13271 */ "CLRBAsmL\0" + /* 13280 */ "LOCAsmL\0" + /* 13288 */ "STOCAsmL\0" + /* 13297 */ "LOCGAsmL\0" + /* 13306 */ "STOCGAsmL\0" + /* 13316 */ "JGAsmL\0" + /* 13323 */ "LOCFHAsmL\0" + /* 13333 */ "STOCFHAsmL\0" + /* 13344 */ "BIAsmL\0" + /* 13351 */ "LOCHIAsmL\0" + /* 13361 */ "LOCGHIAsmL\0" + /* 13372 */ "LOCHHIAsmL\0" + /* 13383 */ "CIJAsmL\0" + /* 13391 */ "CGIJAsmL\0" + /* 13400 */ "CLGIJAsmL\0" + /* 13410 */ "CLIJAsmL\0" + /* 13419 */ "CRJAsmL\0" + /* 13427 */ "CGRJAsmL\0" + /* 13436 */ "CLGRJAsmL\0" + /* 13446 */ "CLRJAsmL\0" + /* 13455 */ "BRAsmL\0" + /* 13462 */ "LOCRAsmL\0" + /* 13471 */ "LOCGRAsmL\0" + /* 13481 */ "SELGRAsmL\0" + /* 13491 */ "LOCFHRAsmL\0" + /* 13502 */ "SELFHRAsmL\0" + /* 13513 */ "SELRAsmL\0" + /* 13522 */ "CLGTAsmL\0" + /* 13531 */ "CITAsmL\0" + /* 13539 */ "CLFITAsmL\0" + /* 13549 */ "CGITAsmL\0" + /* 13558 */ "CLGITAsmL\0" + /* 13568 */ "CLTAsmL\0" + /* 13576 */ "CRTAsmL\0" + /* 13584 */ "CGRTAsmL\0" + /* 13593 */ "CLGRTAsmL\0" + /* 13603 */ "CLRTAsmL\0" + /* 13612 */ "LAM\0" + /* 13616 */ "STAM\0" + /* 13621 */ "VGBM\0" + /* 13626 */ "IRBM\0" + /* 13631 */ "RRBM\0" + /* 13636 */ "ICM\0" + /* 13640 */ "STCM\0" + /* 13645 */ "G_FREM\0" + /* 13652 */ "G_STRICT_FREM\0" + /* 13666 */ "G_SREM\0" + /* 13673 */ "G_UREM\0" + /* 13680 */ "G_SDIVREM\0" + /* 13690 */ "G_UDIVREM\0" + /* 13700 */ "VGFM\0" + /* 13705 */ "VFM\0" + /* 13709 */ "VGM\0" + /* 13713 */ "SCHM\0" + /* 13718 */ "VERIM\0" + /* 13724 */ "KM\0" + /* 13727 */ "CLM\0" + /* 13731 */ "VLM\0" + /* 13735 */ "SRNM\0" + /* 13740 */ "BAsmNM\0" + /* 13747 */ "LOCAsmNM\0" + /* 13756 */ "STOCAsmNM\0" + /* 13766 */ "LOCGAsmNM\0" + /* 13776 */ "STOCGAsmNM\0" + /* 13787 */ "JGAsmNM\0" + /* 13795 */ "LOCFHAsmNM\0" + /* 13806 */ "STOCFHAsmNM\0" + /* 13818 */ "BIAsmNM\0" + /* 13826 */ "LOCHIAsmNM\0" + /* 13837 */ "LOCGHIAsmNM\0" + /* 13849 */ "LOCHHIAsmNM\0" + /* 13861 */ "JAsmNM\0" + /* 13868 */ "BRAsmNM\0" + /* 13876 */ "LOCRAsmNM\0" + /* 13886 */ "LOCGRAsmNM\0" + /* 13897 */ "SELGRAsmNM\0" + /* 13908 */ "LOCFHRAsmNM\0" + /* 13920 */ "SELFHRAsmNM\0" + /* 13932 */ "SELRAsmNM\0" + /* 13942 */ "IPM\0" + /* 13946 */ "SPM\0" + /* 13950 */ "VBPERM\0" + /* 13957 */ "VPERM\0" + /* 13963 */ "INLINEASM\0" + /* 13973 */ "BSM\0" + /* 13977 */ "VCKSM\0" + /* 13983 */ "STNSM\0" + /* 13989 */ "STOSM\0" + /* 13995 */ "BASSM\0" + /* 14001 */ "VSTM\0" + /* 14006 */ "VTM\0" + /* 14010 */ "G_FMINIMUM\0" + /* 14021 */ "G_FMAXIMUM\0" + /* 14032 */ "G_FMINNUM\0" + /* 14042 */ "G_FMAXNUM\0" + /* 14052 */ "VSUM\0" + /* 14057 */ "BAsmM\0" + /* 14063 */ "LOCAsmM\0" + /* 14071 */ "STOCAsmM\0" + /* 14080 */ "LOCGAsmM\0" + /* 14089 */ "STOCGAsmM\0" + /* 14099 */ "JGAsmM\0" + /* 14106 */ "LOCFHAsmM\0" + /* 14116 */ "STOCFHAsmM\0" + /* 14127 */ "BIAsmM\0" + /* 14134 */ "LOCHIAsmM\0" + /* 14144 */ "LOCGHIAsmM\0" + /* 14155 */ "LOCHHIAsmM\0" + /* 14166 */ "JAsmM\0" + /* 14172 */ "BRAsmM\0" + /* 14179 */ "LOCRAsmM\0" + /* 14188 */ "LOCGRAsmM\0" + /* 14198 */ "SELGRAsmM\0" + /* 14208 */ "LOCFHRAsmM\0" + /* 14219 */ "SELFHRAsmM\0" + /* 14230 */ "SELRAsmM\0" + /* 14239 */ "LAN\0" + /* 14243 */ "G_INTRINSIC_ROUNDEVEN\0" + /* 14265 */ "VCFN\0" + /* 14270 */ "RISBGN\0" + /* 14277 */ "G_FCOPYSIGN\0" + /* 14289 */ "ALSIHN\0" + /* 14296 */ "MVCIN\0" + /* 14302 */ "TBEGIN\0" + /* 14309 */ "PGIN\0" + /* 14314 */ "VFMIN\0" + /* 14320 */ "G_VECREDUCE_FMIN\0" + /* 14337 */ "G_VECREDUCE_SMIN\0" + /* 14354 */ "G_SMIN\0" + /* 14361 */ "G_VECREDUCE_UMIN\0" + /* 14378 */ "G_UMIN\0" + /* 14385 */ "ATOMIC_LOADW_UMIN\0" + /* 14403 */ "G_ATOMICRMW_UMIN\0" + /* 14420 */ "ATOMIC_LOADW_MIN\0" + /* 14437 */ "G_ATOMICRMW_MIN\0" + /* 14453 */ "G_FSIN\0" + /* 14460 */ "VMN\0" + /* 14464 */ "VNN\0" + /* 14468 */ "CFI_INSTRUCTION\0" + /* 14484 */ "MVN\0" + /* 14488 */ "ADJCALLSTACKDOWN\0" + /* 14505 */ "LAO\0" + /* 14509 */ "VMAO\0" + /* 14514 */ "G_SSUBO\0" + /* 14522 */ "G_USUBO\0" + /* 14530 */ "G_SADDO\0" + /* 14538 */ "G_UADDO\0" + /* 14546 */ "VMALO\0" + /* 14552 */ "VMLO\0" + /* 14557 */ "PLO\0" + /* 14561 */ "G_SMULO\0" + /* 14569 */ "G_UMULO\0" + /* 14577 */ "PCKMO\0" + /* 14583 */ "VMO\0" + /* 14587 */ "PPNO\0" + /* 14592 */ "PRNO\0" + /* 14597 */ "VNO\0" + /* 14601 */ "BAsmNO\0" + /* 14608 */ "LOCAsmNO\0" + /* 14617 */ "STOCAsmNO\0" + /* 14627 */ "LOCGAsmNO\0" + /* 14637 */ "STOCGAsmNO\0" + /* 14648 */ "JGAsmNO\0" + /* 14656 */ "LOCFHAsmNO\0" + /* 14667 */ "STOCFHAsmNO\0" + /* 14679 */ "BIAsmNO\0" + /* 14687 */ "LOCHIAsmNO\0" + /* 14698 */ "LOCGHIAsmNO\0" + /* 14710 */ "LOCHHIAsmNO\0" + /* 14722 */ "JAsmNO\0" + /* 14729 */ "BRAsmNO\0" + /* 14737 */ "LOCRAsmNO\0" + /* 14747 */ "LOCGRAsmNO\0" + /* 14758 */ "SELGRAsmNO\0" + /* 14769 */ "LOCFHRAsmNO\0" + /* 14781 */ "SELFHRAsmNO\0" + /* 14793 */ "SELRAsmNO\0" + /* 14803 */ "TROO\0" + /* 14808 */ "PFPO\0" + /* 14813 */ "G_BZERO\0" + /* 14821 */ "VZERO\0" + /* 14827 */ "VFPSO\0" + /* 14833 */ "TRTO\0" + /* 14838 */ "MVO\0" + /* 14842 */ "BAsmO\0" + /* 14848 */ "LOCAsmO\0" + /* 14856 */ "STOCAsmO\0" + /* 14865 */ "LOCGAsmO\0" + /* 14874 */ "STOCGAsmO\0" + /* 14884 */ "JGAsmO\0" + /* 14891 */ "LOCFHAsmO\0" + /* 14901 */ "STOCFHAsmO\0" + /* 14912 */ "BIAsmO\0" + /* 14919 */ "LOCHIAsmO\0" + /* 14929 */ "LOCGHIAsmO\0" + /* 14940 */ "LOCHHIAsmO\0" + /* 14951 */ "JAsmO\0" + /* 14957 */ "BRAsmO\0" + /* 14964 */ "LOCRAsmO\0" + /* 14973 */ "LOCGRAsmO\0" + /* 14983 */ "SELGRAsmO\0" + /* 14993 */ "LOCFHRAsmO\0" + /* 15004 */ "SELFHRAsmO\0" + /* 15015 */ "SELRAsmO\0" + /* 15024 */ "STACKMAP\0" + /* 15033 */ "STAP\0" + /* 15038 */ "VAP\0" + /* 15042 */ "G_BSWAP\0" + /* 15050 */ "ZAP\0" + /* 15054 */ "MVCP\0" + /* 15059 */ "VSCHDP\0" + /* 15066 */ "STIDP\0" + /* 15072 */ "RDP\0" + /* 15076 */ "VSDP\0" + /* 15081 */ "VDP\0" + /* 15085 */ "VCLZDP\0" + /* 15092 */ "VLREP\0" + /* 15098 */ "VLBRREP\0" + /* 15106 */ "VREP\0" + /* 15111 */ "VCLFP\0" + /* 15117 */ "G_SITOFP\0" + /* 15126 */ "G_UITOFP\0" + /* 15135 */ "VCSFP\0" + /* 15141 */ "SIGP\0" + /* 15146 */ "VLVGP\0" + /* 15152 */ "RCHP\0" + /* 15157 */ "VSCHP\0" + /* 15163 */ "VSCSHP\0" + /* 15170 */ "VLIP\0" + /* 15175 */ "VLP\0" + /* 15179 */ "G_FCMP\0" + /* 15186 */ "G_ICMP\0" + /* 15193 */ "VMP\0" + /* 15197 */ "BAsmNP\0" + /* 15204 */ "LOCAsmNP\0" + /* 15213 */ "STOCAsmNP\0" + /* 15223 */ "LOCGAsmNP\0" + /* 15233 */ "STOCGAsmNP\0" + /* 15244 */ "JGAsmNP\0" + /* 15252 */ "LOCFHAsmNP\0" + /* 15263 */ "STOCFHAsmNP\0" + /* 15275 */ "BIAsmNP\0" + /* 15283 */ "LOCHIAsmNP\0" + /* 15294 */ "LOCGHIAsmNP\0" + /* 15306 */ "LOCHHIAsmNP\0" + /* 15318 */ "JAsmNP\0" + /* 15325 */ "BRAsmNP\0" + /* 15333 */ "LOCRAsmNP\0" + /* 15343 */ "LOCGRAsmNP\0" + /* 15354 */ "SELGRAsmNP\0" + /* 15365 */ "LOCFHRAsmNP\0" + /* 15377 */ "SELFHRAsmNP\0" + /* 15389 */ "SELRAsmNP\0" + /* 15399 */ "G_CTPOP\0" + /* 15407 */ "VPSOP\0" + /* 15413 */ "PATCHABLE_OP\0" + /* 15426 */ "FAULTING_OP\0" + /* 15438 */ "BPP\0" + /* 15442 */ "LPP\0" + /* 15446 */ "BPRP\0" + /* 15451 */ "VSRP\0" + /* 15456 */ "VRP\0" + /* 15460 */ "LASP\0" + /* 15465 */ "CSP\0" + /* 15469 */ "VSCHSP\0" + /* 15476 */ "VMSP\0" + /* 15481 */ "VSP\0" + /* 15485 */ "VTP\0" + /* 15489 */ "ADJCALLSTACKUP\0" + /* 15504 */ "PREALLOCATED_SETUP\0" + /* 15523 */ "G_FEXP\0" + /* 15530 */ "VSCHXP\0" + /* 15537 */ "BAsmP\0" + /* 15543 */ "LOCAsmP\0" + /* 15551 */ "STOCAsmP\0" + /* 15560 */ "LOCGAsmP\0" + /* 15569 */ "STOCGAsmP\0" + /* 15579 */ "JGAsmP\0" + /* 15586 */ "LOCFHAsmP\0" + /* 15596 */ "STOCFHAsmP\0" + /* 15607 */ "BIAsmP\0" + /* 15614 */ "LOCHIAsmP\0" + /* 15624 */ "LOCGHIAsmP\0" + /* 15635 */ "LOCHHIAsmP\0" + /* 15646 */ "JAsmP\0" + /* 15652 */ "BRAsmP\0" + /* 15659 */ "LOCRAsmP\0" + /* 15668 */ "LOCGRAsmP\0" + /* 15678 */ "SELGRAsmP\0" + /* 15688 */ "LOCFHRAsmP\0" + /* 15699 */ "SELFHRAsmP\0" + /* 15710 */ "SELRAsmP\0" + /* 15719 */ "VAQ\0" + /* 15723 */ "VACQ\0" + /* 15728 */ "VACCQ\0" + /* 15734 */ "VACCCQ\0" + /* 15741 */ "VCEQ\0" + /* 15746 */ "VSBCBIQ\0" + /* 15754 */ "VSCBIQ\0" + /* 15761 */ "VSBIQ\0" + /* 15767 */ "VSUMQ\0" + /* 15773 */ "LPQ\0" + /* 15777 */ "STPQ\0" + /* 15782 */ "VLBRQ\0" + /* 15788 */ "VSTBRQ\0" + /* 15795 */ "VFSQ\0" + /* 15800 */ "VSQ\0" + /* 15804 */ "LBEAR\0" + /* 15810 */ "STBEAR\0" + /* 15817 */ "EPAR\0" + /* 15822 */ "ESAR\0" + /* 15827 */ "SSAR\0" + /* 15832 */ "TAR\0" + /* 15836 */ "ATOMIC_LOAD_AR\0" + /* 15851 */ "ATOMIC_LOADW_AR\0" + /* 15867 */ "MADBR\0" + /* 15873 */ "LCDBR\0" + /* 15879 */ "DDBR\0" + /* 15884 */ "LEDBR\0" + /* 15890 */ "CFDBR\0" + /* 15896 */ "CLFDBR\0" + /* 15903 */ "CGDBR\0" + /* 15909 */ "CLGDBR\0" + /* 15916 */ "DIDBR\0" + /* 15922 */ "FIDBR\0" + /* 15928 */ "KDBR\0" + /* 15933 */ "MDBR\0" + /* 15938 */ "LNDBR\0" + /* 15944 */ "LPDBR\0" + /* 15950 */ "SQDBR\0" + /* 15956 */ "MSDBR\0" + /* 15962 */ "LTDBR\0" + /* 15968 */ "LXDBR\0" + /* 15974 */ "MXDBR\0" + /* 15980 */ "MAEBR\0" + /* 15986 */ "LCEBR\0" + /* 15992 */ "LDEBR\0" + /* 15998 */ "MDEBR\0" + /* 16004 */ "MEEBR\0" + /* 16010 */ "CFEBR\0" + /* 16016 */ "CLFEBR\0" + /* 16023 */ "CGEBR\0" + /* 16029 */ "CLGEBR\0" + /* 16036 */ "DIEBR\0" + /* 16042 */ "FIEBR\0" + /* 16048 */ "KEBR\0" + /* 16053 */ "LNEBR\0" + /* 16059 */ "LPEBR\0" + /* 16065 */ "SQEBR\0" + /* 16071 */ "MSEBR\0" + /* 16077 */ "LTEBR\0" + /* 16083 */ "LXEBR\0" + /* 16089 */ "CDFBR\0" + /* 16095 */ "CEFBR\0" + /* 16101 */ "CDLFBR\0" + /* 16108 */ "CELFBR\0" + /* 16115 */ "CXLFBR\0" + /* 16122 */ "CXFBR\0" + /* 16128 */ "CDGBR\0" + /* 16134 */ "CEGBR\0" + /* 16140 */ "CDLGBR\0" + /* 16147 */ "CELGBR\0" + /* 16154 */ "CXLGBR\0" + /* 16161 */ "CXGBR\0" + /* 16167 */ "SLBR\0" + /* 16172 */ "VLBR\0" + /* 16177 */ "VSTBR\0" + /* 16183 */ "AXBR\0" + /* 16188 */ "LCXBR\0" + /* 16194 */ "LDXBR\0" + /* 16200 */ "LEXBR\0" + /* 16206 */ "CFXBR\0" + /* 16212 */ "CLFXBR\0" + /* 16219 */ "CGXBR\0" + /* 16225 */ "CLGXBR\0" + /* 16232 */ "FIXBR\0" + /* 16238 */ "KXBR\0" + /* 16243 */ "MXBR\0" + /* 16248 */ "LNXBR\0" + /* 16254 */ "LPXBR\0" + /* 16260 */ "SQXBR\0" + /* 16266 */ "SXBR\0" + /* 16271 */ "LTXBR\0" + /* 16277 */ "G_BR\0" + /* 16282 */ "INLINEASM_BR\0" + /* 16295 */ "CallBR\0" + /* 16302 */ "CallBCR\0" + /* 16310 */ "LLGCR\0" + /* 16316 */ "ALCR\0" + /* 16321 */ "LLCR\0" + /* 16326 */ "LOCR\0" + /* 16331 */ "MADR\0" + /* 16336 */ "TBDR\0" + /* 16341 */ "LCDR\0" + /* 16346 */ "G_BLOCK_ADDR\0" + /* 16359 */ "TBEDR\0" + /* 16365 */ "LEDR\0" + /* 16370 */ "CFDR\0" + /* 16375 */ "CGDR\0" + /* 16380 */ "LGDR\0" + /* 16385 */ "THDR\0" + /* 16390 */ "FIDR\0" + /* 16395 */ "LDR\0" + /* 16399 */ "MDR\0" + /* 16403 */ "LNDR\0" + /* 16408 */ "LPDR\0" + /* 16413 */ "SQDR\0" + /* 16418 */ "LRDR\0" + /* 16423 */ "MSDR\0" + /* 16428 */ "LTDR\0" + /* 16433 */ "LXDR\0" + /* 16438 */ "MXDR\0" + /* 16443 */ "LZDR\0" + /* 16448 */ "MAER\0" + /* 16453 */ "LCER\0" + /* 16458 */ "THDER\0" + /* 16464 */ "LDER\0" + /* 16469 */ "MDER\0" + /* 16474 */ "MEER\0" + /* 16479 */ "CFER\0" + /* 16484 */ "LFER\0" + /* 16489 */ "CGER\0" + /* 16494 */ "HER\0" + /* 16498 */ "FIER\0" + /* 16503 */ "VLER\0" + /* 16508 */ "MER\0" + /* 16512 */ "LNER\0" + /* 16517 */ "LPER\0" + /* 16522 */ "SQER\0" + /* 16527 */ "LRER\0" + /* 16532 */ "MSER\0" + /* 16537 */ "LTER\0" + /* 16542 */ "PATCHABLE_FUNCTION_ENTER\0" + /* 16567 */ "G_READCYCLECOUNTER\0" + /* 16586 */ "G_READ_REGISTER\0" + /* 16602 */ "G_WRITE_REGISTER\0" + /* 16619 */ "VSTER\0" + /* 16625 */ "LXER\0" + /* 16630 */ "LZER\0" + /* 16635 */ "LCDFR\0" + /* 16641 */ "LNDFR\0" + /* 16647 */ "LPDFR\0" + /* 16653 */ "CEFR\0" + /* 16658 */ "LEFR\0" + /* 16663 */ "AGFR\0" + /* 16668 */ "LCGFR\0" + /* 16674 */ "ALGFR\0" + /* 16680 */ "CLGFR\0" + /* 16686 */ "LLGFR\0" + /* 16692 */ "SLGFR\0" + /* 16698 */ "LNGFR\0" + /* 16704 */ "LPGFR\0" + /* 16710 */ "DSGFR\0" + /* 16716 */ "MSGFR\0" + /* 16722 */ "LTGFR\0" + /* 16728 */ "CXFR\0" + /* 16733 */ "ATOMIC_LOAD_AGR\0" + /* 16749 */ "SLBGR\0" + /* 16755 */ "ALCGR\0" + /* 16761 */ "LOCGR\0" + /* 16767 */ "CDGR\0" + /* 16772 */ "LDGR\0" + /* 16777 */ "CEGR\0" + /* 16782 */ "ALGR\0" + /* 16787 */ "CLGR\0" + /* 16792 */ "DLGR\0" + /* 16797 */ "SELGR\0" + /* 16803 */ "MLGR\0" + /* 16808 */ "SLGR\0" + /* 16813 */ "LNGR\0" + /* 16818 */ "ATOMIC_LOAD_NGR\0" + /* 16834 */ "FLOGR\0" + /* 16840 */ "ATOMIC_LOAD_OGR\0" + /* 16856 */ "LPGR\0" + /* 16861 */ "DSGR\0" + /* 16866 */ "MSGR\0" + /* 16871 */ "ATOMIC_LOAD_SGR\0" + /* 16887 */ "BCTGR\0" + /* 16893 */ "LTGR\0" + /* 16898 */ "LRVGR\0" + /* 16904 */ "CXGR\0" + /* 16909 */ "ATOMIC_LOAD_XGR\0" + /* 16925 */ "LOCFHR\0" + /* 16932 */ "SELFHR\0" + /* 16939 */ "LLGHR\0" + /* 16945 */ "CHHR\0" + /* 16950 */ "AHHHR\0" + /* 16956 */ "ALHHHR\0" + /* 16963 */ "SLHHHR\0" + /* 16970 */ "SHHHR\0" + /* 16976 */ "CLHHR\0" + /* 16982 */ "LLHR\0" + /* 16987 */ "G_ASHR\0" + /* 16994 */ "G_FSHR\0" + /* 17001 */ "G_LSHR\0" + /* 17008 */ "MAYHR\0" + /* 17014 */ "MYHR\0" + /* 17019 */ "EPAIR\0" + /* 17025 */ "ESAIR\0" + /* 17031 */ "SSAIR\0" + /* 17037 */ "BAKR\0" + /* 17042 */ "BALR\0" + /* 17047 */ "CLR\0" + /* 17051 */ "DLR\0" + /* 17055 */ "SELR\0" + /* 17060 */ "VFLR\0" + /* 17065 */ "CHLR\0" + /* 17070 */ "AHHLR\0" + /* 17076 */ "ALHHLR\0" + /* 17083 */ "SLHHLR\0" + /* 17090 */ "SHHLR\0" + /* 17096 */ "CLHLR\0" + /* 17102 */ "MLR\0" + /* 17106 */ "VLRLR\0" + /* 17112 */ "VSTRLR\0" + /* 17119 */ "SLR\0" + /* 17123 */ "VLR\0" + /* 17127 */ "MAYLR\0" + /* 17133 */ "MYLR\0" + /* 17138 */ "MR\0" + /* 17141 */ "LNR\0" + /* 17145 */ "ATOMIC_LOAD_NR\0" + /* 17160 */ "ATOMIC_LOADW_NR\0" + /* 17176 */ "G_FFLOOR\0" + /* 17185 */ "G_BUILD_VECTOR\0" + /* 17200 */ "G_SHUFFLE_VECTOR\0" + /* 17217 */ "G_VECREDUCE_XOR\0" + /* 17233 */ "G_XOR\0" + /* 17239 */ "G_ATOMICRMW_XOR\0" + /* 17255 */ "ATOMIC_LOAD_OR\0" + /* 17270 */ "G_VECREDUCE_OR\0" + /* 17285 */ "G_OR\0" + /* 17290 */ "ATOMIC_LOADW_OR\0" + /* 17306 */ "G_ATOMICRMW_OR\0" + /* 17321 */ "LPR\0" + /* 17325 */ "VSRPR\0" + /* 17331 */ "InsnVRR\0" + /* 17339 */ "InsnRR\0" + /* 17346 */ "CallBASR\0" + /* 17355 */ "SFASR\0" + /* 17361 */ "MSR\0" + /* 17365 */ "ATOMIC_LOAD_SR\0" + /* 17380 */ "ATOMIC_LOADW_SR\0" + /* 17396 */ "BCTR\0" + /* 17401 */ "ECCTR\0" + /* 17407 */ "SCCTR\0" + /* 17413 */ "KMCTR\0" + /* 17419 */ "EPCTR\0" + /* 17425 */ "SPCTR\0" + /* 17431 */ "QADTR\0" + /* 17437 */ "CDTR\0" + /* 17442 */ "DDTR\0" + /* 17447 */ "CEDTR\0" + /* 17453 */ "EEDTR\0" + /* 17459 */ "IEDTR\0" + /* 17465 */ "LEDTR\0" + /* 17471 */ "CFDTR\0" + /* 17477 */ "CLFDTR\0" + /* 17484 */ "CGDTR\0" + /* 17490 */ "CLGDTR\0" + /* 17497 */ "FIDTR\0" + /* 17503 */ "KDTR\0" + /* 17508 */ "MDTR\0" + /* 17513 */ "RRDTR\0" + /* 17519 */ "CSDTR\0" + /* 17525 */ "ESDTR\0" + /* 17531 */ "LTDTR\0" + /* 17537 */ "CUDTR\0" + /* 17543 */ "LXDTR\0" + /* 17549 */ "LDETR\0" + /* 17555 */ "CDFTR\0" + /* 17561 */ "CDLFTR\0" + /* 17568 */ "CXLFTR\0" + /* 17575 */ "CXFTR\0" + /* 17581 */ "CDGTR\0" + /* 17587 */ "CDLGTR\0" + /* 17594 */ "LLGTR\0" + /* 17600 */ "CXLGTR\0" + /* 17607 */ "CXGTR\0" + /* 17613 */ "LTR\0" + /* 17617 */ "G_ROTR\0" + /* 17624 */ "G_INTTOPTR\0" + /* 17635 */ "TRTR\0" + /* 17640 */ "CDSTR\0" + /* 17646 */ "VISTR\0" + /* 17652 */ "CXSTR\0" + /* 17658 */ "CDUTR\0" + /* 17664 */ "CXUTR\0" + /* 17670 */ "QAXTR\0" + /* 17676 */ "CXTR\0" + /* 17681 */ "LDXTR\0" + /* 17687 */ "CEXTR\0" + /* 17693 */ "EEXTR\0" + /* 17699 */ "IEXTR\0" + /* 17705 */ "CFXTR\0" + /* 17711 */ "CLFXTR\0" + /* 17718 */ "CGXTR\0" + /* 17724 */ "CLGXTR\0" + /* 17731 */ "FIXTR\0" + /* 17737 */ "KXTR\0" + /* 17742 */ "MXTR\0" + /* 17747 */ "RRXTR\0" + /* 17753 */ "CSXTR\0" + /* 17759 */ "ESXTR\0" + /* 17765 */ "LTXTR\0" + /* 17771 */ "CUXTR\0" + /* 17777 */ "AUR\0" + /* 17781 */ "SUR\0" + /* 17785 */ "LRVR\0" + /* 17790 */ "AWR\0" + /* 17794 */ "SWR\0" + /* 17798 */ "AXR\0" + /* 17802 */ "LCXR\0" + /* 17807 */ "LDXR\0" + /* 17812 */ "LEXR\0" + /* 17817 */ "CFXR\0" + /* 17822 */ "CGXR\0" + /* 17827 */ "FIXR\0" + /* 17832 */ "LXR\0" + /* 17836 */ "MXR\0" + /* 17840 */ "LNXR\0" + /* 17845 */ "LPXR\0" + /* 17850 */ "SQXR\0" + /* 17855 */ "SXR\0" + /* 17859 */ "LTXR\0" + /* 17864 */ "LZXR\0" + /* 17869 */ "ATOMIC_LOAD_XR\0" + /* 17884 */ "ATOMIC_LOADW_XR\0" + /* 17900 */ "MAYR\0" + /* 17905 */ "MYR\0" + /* 17909 */ "VPKZR\0" + /* 17915 */ "BAS\0" + /* 17919 */ "LFAS\0" + /* 17924 */ "BRAS\0" + /* 17929 */ "G_FABS\0" + /* 17936 */ "G_ABS\0" + /* 17942 */ "VSTRCBS\0" + /* 17950 */ "VFCEDBS\0" + /* 17958 */ "WFCEDBS\0" + /* 17966 */ "VFCHEDBS\0" + /* 17975 */ "WFCHEDBS\0" + /* 17984 */ "VFKHEDBS\0" + /* 17993 */ "WFKHEDBS\0" + /* 18002 */ "VFKEDBS\0" + /* 18010 */ "WFKEDBS\0" + /* 18018 */ "VFCHDBS\0" + /* 18026 */ "WFCHDBS\0" + /* 18034 */ "VFKHDBS\0" + /* 18042 */ "WFKHDBS\0" + /* 18050 */ "VFAEBS\0" + /* 18057 */ "VFEEBS\0" + /* 18064 */ "VFENEBS\0" + /* 18072 */ "VCHBS\0" + /* 18078 */ "VCHLBS\0" + /* 18085 */ "VCEQBS\0" + /* 18092 */ "VISTRBS\0" + /* 18100 */ "VFCESBS\0" + /* 18108 */ "WFCESBS\0" + /* 18116 */ "VFCHESBS\0" + /* 18125 */ "WFCHESBS\0" + /* 18134 */ "VFKHESBS\0" + /* 18143 */ "WFKHESBS\0" + /* 18152 */ "VFKESBS\0" + /* 18160 */ "WFKESBS\0" + /* 18168 */ "VFCHSBS\0" + /* 18176 */ "WFCHSBS\0" + /* 18184 */ "VFKHSBS\0" + /* 18192 */ "WFKHSBS\0" + /* 18200 */ "WFCEXBS\0" + /* 18208 */ "WFCHEXBS\0" + /* 18217 */ "WFKHEXBS\0" + /* 18226 */ "WFKEXBS\0" + /* 18234 */ "WFCHXBS\0" + /* 18242 */ "WFKHXBS\0" + /* 18250 */ "VSTRCZBS\0" + /* 18259 */ "VFAEZBS\0" + /* 18267 */ "VFEEZBS\0" + /* 18275 */ "VFENEZBS\0" + /* 18284 */ "MVCS\0" + /* 18289 */ "CDS\0" + /* 18293 */ "G_UNMERGE_VALUES\0" + /* 18310 */ "G_MERGE_VALUES\0" + /* 18325 */ "VSTRCFS\0" + /* 18333 */ "VFAEFS\0" + /* 18340 */ "VFEEFS\0" + /* 18347 */ "VFENEFS\0" + /* 18355 */ "VCHFS\0" + /* 18361 */ "VCHLFS\0" + /* 18368 */ "VCEQFS\0" + /* 18375 */ "VISTRFS\0" + /* 18383 */ "VPKSFS\0" + /* 18390 */ "VPKLSFS\0" + /* 18398 */ "VFS\0" + /* 18402 */ "VSTRCZFS\0" + /* 18411 */ "VFAEZFS\0" + /* 18419 */ "VFEEZFS\0" + /* 18427 */ "VFENEZFS\0" + /* 18436 */ "VCHGS\0" + /* 18442 */ "VCHLGS\0" + /* 18449 */ "VCEQGS\0" + /* 18456 */ "VPKSGS\0" + /* 18463 */ "VPKLSGS\0" + /* 18471 */ "VSTRCHS\0" + /* 18479 */ "VFAEHS\0" + /* 18486 */ "VFEEHS\0" + /* 18493 */ "VFENEHS\0" + /* 18501 */ "VCHHS\0" + /* 18507 */ "VCHLHS\0" + /* 18514 */ "VCEQHS\0" + /* 18521 */ "VISTRHS\0" + /* 18529 */ "VPKSHS\0" + /* 18536 */ "VPKLSHS\0" + /* 18544 */ "VSTRCZHS\0" + /* 18553 */ "VFAEZHS\0" + /* 18561 */ "VFEEZHS\0" + /* 18569 */ "VFENEZHS\0" + /* 18578 */ "InsnRIS\0" + /* 18586 */ "VPKS\0" + /* 18591 */ "VPKLS\0" + /* 18597 */ "VFLLS\0" + /* 18603 */ "WFLLS\0" + /* 18609 */ "VFMS\0" + /* 18614 */ "VFNMS\0" + /* 18620 */ "G_FCOS\0" + /* 18627 */ "MVCOS\0" + /* 18633 */ "STCPS\0" + /* 18639 */ "VCFPS\0" + /* 18645 */ "G_CONCAT_VECTORS\0" + /* 18662 */ "InsnRRS\0" + /* 18670 */ "VSTRS\0" + /* 18676 */ "InsnVRS\0" + /* 18684 */ "InsnRS\0" + /* 18691 */ "COPY_TO_REGCLASS\0" + /* 18708 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" + /* 18738 */ "InsnSS\0" + /* 18745 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" + /* 18772 */ "VS\0" + /* 18775 */ "InsnS\0" + /* 18781 */ "LLGFAT\0" + /* 18788 */ "LGAT\0" + /* 18793 */ "LFHAT\0" + /* 18799 */ "LAT\0" + /* 18803 */ "G_SSUBSAT\0" + /* 18813 */ "G_USUBSAT\0" + /* 18823 */ "G_SADDSAT\0" + /* 18833 */ "G_UADDSAT\0" + /* 18843 */ "G_SSHLSAT\0" + /* 18853 */ "G_USHLSAT\0" + /* 18863 */ "G_SMULFIXSAT\0" + /* 18876 */ "G_UMULFIXSAT\0" + /* 18889 */ "G_SDIVFIXSAT\0" + /* 18902 */ "G_UDIVFIXSAT\0" + /* 18915 */ "LLGTAT\0" + /* 18922 */ "G_EXTRACT\0" + /* 18932 */ "BCT\0" + /* 18936 */ "G_SELECT\0" + /* 18945 */ "G_BRINDIRECT\0" + /* 18958 */ "VPOPCT\0" + /* 18965 */ "BRCT\0" + /* 18970 */ "TDCDT\0" + /* 18976 */ "TDGDT\0" + /* 18982 */ "SLDT\0" + /* 18987 */ "CPDT\0" + /* 18992 */ "SRDT\0" + /* 18997 */ "CZDT\0" + /* 19002 */ "TDCET\0" + /* 19008 */ "TDGET\0" + /* 19014 */ "PATCHABLE_RET\0" + /* 19028 */ "G_MEMSET\0" + /* 19037 */ "CLGT\0" + /* 19042 */ "LLGT\0" + /* 19047 */ "CIT\0" + /* 19051 */ "CLFIT\0" + /* 19057 */ "CGIT\0" + /* 19062 */ "CLGIT\0" + /* 19068 */ "PATCHABLE_FUNCTION_EXIT\0" + /* 19092 */ "G_BRJT\0" + /* 19099 */ "CLT\0" + /* 19103 */ "G_EXTRACT_VECTOR_ELT\0" + /* 19124 */ "G_INSERT_VECTOR_ELT\0" + /* 19144 */ "SRNMT\0" + /* 19150 */ "G_FCONSTANT\0" + /* 19162 */ "G_CONSTANT\0" + /* 19173 */ "POPCNT\0" + /* 19180 */ "STATEPOINT\0" + /* 19191 */ "PATCHPOINT\0" + /* 19202 */ "G_PTRTOINT\0" + /* 19213 */ "G_FRINT\0" + /* 19221 */ "G_INTRINSIC_LRINT\0" + /* 19239 */ "G_FNEARBYINT\0" + /* 19252 */ "GOT\0" + /* 19256 */ "TPROT\0" + /* 19262 */ "TROT\0" + /* 19267 */ "CDPT\0" + /* 19272 */ "SPT\0" + /* 19276 */ "STPT\0" + /* 19281 */ "UPT\0" + /* 19285 */ "CXPT\0" + /* 19290 */ "G_VASTART\0" + /* 19300 */ "LIFETIME_START\0" + /* 19315 */ "CRT\0" + /* 19319 */ "G_INSERT\0" + /* 19328 */ "CGRT\0" + /* 19333 */ "CLGRT\0" + /* 19339 */ "CLRT\0" + /* 19344 */ "TABORT\0" + /* 19351 */ "G_FSQRT\0" + /* 19359 */ "G_STRICT_FSQRT\0" + /* 19374 */ "TRT\0" + /* 19378 */ "G_BITCAST\0" + /* 19388 */ "G_ADDRSPACE_CAST\0" + /* 19405 */ "DBG_VALUE_LIST\0" + /* 19420 */ "CLST\0" + /* 19425 */ "SRST\0" + /* 19430 */ "CSST\0" + /* 19435 */ "MVST\0" + /* 19440 */ "TRTT\0" + /* 19445 */ "PGOUT\0" + /* 19451 */ "TDCXT\0" + /* 19457 */ "G_FPEXT\0" + /* 19465 */ "G_SEXT\0" + /* 19472 */ "G_ASSERT_SEXT\0" + /* 19486 */ "G_ANYEXT\0" + /* 19495 */ "G_ZEXT\0" + /* 19502 */ "G_ASSERT_ZEXT\0" + /* 19516 */ "TDGXT\0" + /* 19522 */ "SLXT\0" + /* 19527 */ "CPXT\0" + /* 19532 */ "SRXT\0" + /* 19537 */ "CZXT\0" + /* 19542 */ "CDZT\0" + /* 19547 */ "CXZT\0" + /* 19552 */ "AU\0" + /* 19555 */ "CUTFU\0" + /* 19561 */ "UNPKU\0" + /* 19567 */ "CLCLU\0" + /* 19573 */ "MVCLU\0" + /* 19579 */ "InsnRILU\0" + /* 19588 */ "SU\0" + /* 19591 */ "SRSTU\0" + /* 19597 */ "VESRAV\0" + /* 19604 */ "VLGV\0" + /* 19609 */ "G_FDIV\0" + /* 19616 */ "G_STRICT_FDIV\0" + /* 19630 */ "G_SDIV\0" + /* 19637 */ "G_UDIV\0" + /* 19644 */ "VERLLV\0" + /* 19651 */ "VESRLV\0" + /* 19658 */ "VESLV\0" + /* 19664 */ "LRV\0" + /* 19668 */ "STRV\0" + /* 19673 */ "InsnVRV\0" + /* 19681 */ "AW\0" + /* 19684 */ "VMALHW\0" + /* 19691 */ "VMLHW\0" + /* 19697 */ "VUPLHW\0" + /* 19704 */ "G_FPOW\0" + /* 19711 */ "ATOMIC_SWAPW\0" + /* 19724 */ "ATOMIC_CMP_SWAPW\0" + /* 19741 */ "STCRW\0" + /* 19747 */ "EPSW\0" + /* 19752 */ "LPSW\0" + /* 19757 */ "LAX\0" + /* 19761 */ "VFMAX\0" + /* 19767 */ "G_VECREDUCE_FMAX\0" + /* 19784 */ "G_VECREDUCE_SMAX\0" + /* 19801 */ "G_SMAX\0" + /* 19808 */ "G_VECREDUCE_UMAX\0" + /* 19825 */ "G_UMAX\0" + /* 19832 */ "ATOMIC_LOADW_UMAX\0" + /* 19850 */ "G_ATOMICRMW_UMAX\0" + /* 19867 */ "ATOMIC_LOADW_MAX\0" + /* 19884 */ "G_ATOMICRMW_MAX\0" + /* 19900 */ "G_FRAME_INDEX\0" + /* 19914 */ "G_SBFX\0" + /* 19921 */ "G_UBFX\0" + /* 19928 */ "G_SMULFIX\0" + /* 19938 */ "G_UMULFIX\0" + /* 19948 */ "G_SDIVFIX\0" + /* 19958 */ "G_UDIVFIX\0" + /* 19968 */ "LX\0" + /* 19971 */ "VMX\0" + /* 19975 */ "VNX\0" + /* 19979 */ "SPX\0" + /* 19983 */ "STPX\0" + /* 19988 */ "WFLRX\0" + /* 19994 */ "InsnVRX\0" + /* 20002 */ "InsnRX\0" + /* 20009 */ "STX\0" + /* 20013 */ "VX\0" + /* 20016 */ "IC32Y\0" + /* 20022 */ "LAY\0" + /* 20026 */ "MAY\0" + /* 20030 */ "LRAY\0" + /* 20035 */ "CVBY\0" + /* 20040 */ "ICY\0" + /* 20044 */ "STCY\0" + /* 20049 */ "LDY\0" + /* 20053 */ "STDY\0" + /* 20058 */ "CVDY\0" + /* 20063 */ "LAEY\0" + /* 20068 */ "LEY\0" + /* 20072 */ "STEY\0" + /* 20077 */ "LPSWEY\0" + /* 20084 */ "MFY\0" + /* 20088 */ "AHY\0" + /* 20092 */ "CHY\0" + /* 20096 */ "LHY\0" + /* 20100 */ "MHY\0" + /* 20104 */ "SHY\0" + /* 20108 */ "STHY\0" + /* 20113 */ "CLIY\0" + /* 20118 */ "NIY\0" + /* 20122 */ "OIY\0" + /* 20126 */ "InsnSIY\0" + /* 20134 */ "MVIY\0" + /* 20139 */ "XIY\0" + /* 20143 */ "ALY\0" + /* 20147 */ "CLY\0" + /* 20151 */ "SLY\0" + /* 20155 */ "LAMY\0" + /* 20160 */ "STAMY\0" + /* 20166 */ "ICMY\0" + /* 20171 */ "STCMY\0" + /* 20177 */ "CLMY\0" + /* 20182 */ "STMY\0" + /* 20187 */ "NY\0" + /* 20190 */ "OY\0" + /* 20193 */ "G_MEMCPY\0" + /* 20202 */ "COPY\0" + /* 20207 */ "CSY\0" + /* 20211 */ "CDSY\0" + /* 20216 */ "MSY\0" + /* 20220 */ "InsnRSY\0" + /* 20228 */ "STY\0" + /* 20232 */ "InsnRXY\0" + /* 20240 */ "VLLEZ\0" + /* 20246 */ "VUPKZ\0" + /* 20252 */ "VPKZ\0" + /* 20257 */ "VCLZ\0" + /* 20262 */ "G_CTLZ\0" + /* 20269 */ "BAsmNZ\0" + /* 20276 */ "LOCAsmNZ\0" + /* 20285 */ "STOCAsmNZ\0" + /* 20295 */ "LOCGAsmNZ\0" + /* 20305 */ "STOCGAsmNZ\0" + /* 20316 */ "JGAsmNZ\0" + /* 20324 */ "LOCFHAsmNZ\0" + /* 20335 */ "STOCFHAsmNZ\0" + /* 20347 */ "BIAsmNZ\0" + /* 20355 */ "LOCHIAsmNZ\0" + /* 20366 */ "LOCGHIAsmNZ\0" + /* 20378 */ "LOCHHIAsmNZ\0" + /* 20390 */ "JAsmNZ\0" + /* 20397 */ "BRAsmNZ\0" + /* 20405 */ "LOCRAsmNZ\0" + /* 20415 */ "LOCGRAsmNZ\0" + /* 20426 */ "SELGRAsmNZ\0" + /* 20437 */ "LOCFHRAsmNZ\0" + /* 20449 */ "SELFHRAsmNZ\0" + /* 20461 */ "SELRAsmNZ\0" + /* 20471 */ "VLLEBRZ\0" + /* 20479 */ "VCTZ\0" + /* 20484 */ "G_CTTZ\0" + /* 20491 */ "MVZ\0" + /* 20495 */ "BAsmZ\0" + /* 20501 */ "LOCAsmZ\0" + /* 20509 */ "STOCAsmZ\0" + /* 20518 */ "LOCGAsmZ\0" + /* 20527 */ "STOCGAsmZ\0" + /* 20537 */ "JGAsmZ\0" + /* 20544 */ "LOCFHAsmZ\0" + /* 20554 */ "STOCFHAsmZ\0" + /* 20565 */ "BIAsmZ\0" + /* 20572 */ "LOCHIAsmZ\0" + /* 20582 */ "LOCGHIAsmZ\0" + /* 20593 */ "LOCHHIAsmZ\0" + /* 20604 */ "JAsmZ\0" + /* 20610 */ "BRAsmZ\0" + /* 20617 */ "LOCRAsmZ\0" + /* 20626 */ "LOCGRAsmZ\0" + /* 20636 */ "SELGRAsmZ\0" + /* 20646 */ "LOCFHRAsmZ\0" + /* 20657 */ "SELFHRAsmZ\0" + /* 20668 */ "SELRAsmZ\0" + /* 20677 */ "CPSDRdd\0" + /* 20685 */ "CPSDRsd\0" + /* 20693 */ "NOP_bare\0" + /* 20702 */ "LTDBRCompare\0" + /* 20715 */ "LTEBRCompare\0" + /* 20728 */ "LTXBRCompare\0" + /* 20741 */ "Serialize\0" + /* 20751 */ "CLCReg\0" + /* 20758 */ "NCReg\0" + /* 20764 */ "OCReg\0" + /* 20770 */ "MVCReg\0" + /* 20777 */ "XCReg\0" + /* 20783 */ "ATOMIC_LOAD_NIHF64i\0" + /* 20803 */ "ATOMIC_LOAD_NILF64i\0" + /* 20823 */ "ATOMIC_LOAD_NIHH64i\0" + /* 20843 */ "ATOMIC_LOAD_NILH64i\0" + /* 20863 */ "ATOMIC_LOAD_NIHL64i\0" + /* 20883 */ "ATOMIC_LOAD_NILL64i\0" + /* 20903 */ "ATOMIC_LOAD_NILFi\0" + /* 20921 */ "ATOMIC_LOAD_NILHi\0" + /* 20939 */ "ATOMIC_LOADW_NILHi\0" + /* 20958 */ "ATOMIC_LOAD_NILLi\0" + /* 20976 */ "ATOMIC_LOAD_NGRi\0" + /* 20993 */ "ATOMIC_LOAD_NRi\0" + /* 21009 */ "ATOMIC_LOADW_NRi\0" + /* 21026 */ "CIBCall\0" + /* 21034 */ "CGIBCall\0" + /* 21043 */ "CLGIBCall\0" + /* 21053 */ "CLIBCall\0" + /* 21062 */ "CRBCall\0" + /* 21070 */ "CGRBCall\0" + /* 21079 */ "CLGRBCall\0" + /* 21089 */ "CLRBCall\0" + /* 21098 */ "CLCImm\0" + /* 21105 */ "NCImm\0" + /* 21111 */ "OCImm\0" + /* 21117 */ "MVCImm\0" + /* 21124 */ "XCImm\0" + /* 21130 */ "CIBAsm\0" + /* 21137 */ "CGIBAsm\0" + /* 21145 */ "CLGIBAsm\0" + /* 21154 */ "CLIBAsm\0" + /* 21162 */ "CRBAsm\0" + /* 21169 */ "CGRBAsm\0" + /* 21177 */ "CLGRBAsm\0" + /* 21186 */ "CLRBAsm\0" + /* 21194 */ "BCAsm\0" + /* 21200 */ "BICAsm\0" + /* 21207 */ "LOCAsm\0" + /* 21214 */ "STOCAsm\0" + /* 21222 */ "BRCAsm\0" + /* 21229 */ "LOCGAsm\0" + /* 21237 */ "STOCGAsm\0" + /* 21246 */ "LOCFHAsm\0" + /* 21255 */ "STOCFHAsm\0" + /* 21265 */ "LOCHIAsm\0" + /* 21274 */ "LOCGHIAsm\0" + /* 21284 */ "LOCHHIAsm\0" + /* 21294 */ "CIJAsm\0" + /* 21301 */ "CGIJAsm\0" + /* 21309 */ "CLGIJAsm\0" + /* 21318 */ "CLIJAsm\0" + /* 21326 */ "CRJAsm\0" + /* 21333 */ "CGRJAsm\0" + /* 21341 */ "CLGRJAsm\0" + /* 21350 */ "CLRJAsm\0" + /* 21358 */ "BRCLAsm\0" + /* 21366 */ "BCRAsm\0" + /* 21373 */ "LOCRAsm\0" + /* 21381 */ "LOCGRAsm\0" + /* 21390 */ "SELGRAsm\0" + /* 21399 */ "LOCFHRAsm\0" + /* 21409 */ "SELFHRAsm\0" + /* 21419 */ "SELRAsm\0" + /* 21427 */ "CLGTAsm\0" + /* 21435 */ "CITAsm\0" + /* 21442 */ "CLFITAsm\0" + /* 21451 */ "CGITAsm\0" + /* 21459 */ "CLGITAsm\0" + /* 21468 */ "CLTAsm\0" + /* 21475 */ "CRTAsm\0" + /* 21482 */ "CGRTAsm\0" + /* 21490 */ "CLGRTAsm\0" + /* 21499 */ "CLRTAsm\0" + /* 21507 */ "VLAlign\0" + /* 21515 */ "VLMAlign\0" + /* 21524 */ "VSTMAlign\0" + /* 21534 */ "VSTAlign\0" + /* 21543 */ "CIBReturn\0" + /* 21553 */ "CGIBReturn\0" + /* 21564 */ "CLGIBReturn\0" + /* 21576 */ "CLIBReturn\0" + /* 21587 */ "CRBReturn\0" + /* 21597 */ "CGRBReturn\0" + /* 21608 */ "CLGRBReturn\0" + /* 21620 */ "CLRBReturn\0" + /* 21631 */ "CondReturn\0" + /* 21642 */ "EXRL_Pseudo\0" + /* 21654 */ "LTDBRCompare_VecPseudo\0" + /* 21677 */ "LTEBRCompare_VecPseudo\0" + /* 21700 */ "LTXBRCompare_VecPseudo\0" + /* 21723 */ "A_MemFoldPseudo\0" + /* 21739 */ "MADB_MemFoldPseudo\0" + /* 21758 */ "DDB_MemFoldPseudo\0" + /* 21776 */ "MDB_MemFoldPseudo\0" + /* 21794 */ "MSDB_MemFoldPseudo\0" + /* 21813 */ "MAEB_MemFoldPseudo\0" + /* 21832 */ "DEB_MemFoldPseudo\0" + /* 21850 */ "MEEB_MemFoldPseudo\0" + /* 21869 */ "MSEB_MemFoldPseudo\0" + /* 21888 */ "MSGC_MemFoldPseudo\0" + /* 21907 */ "MSC_MemFoldPseudo\0" + /* 21925 */ "AG_MemFoldPseudo\0" + /* 21942 */ "LOCG_MemFoldPseudo\0" + /* 21961 */ "ALG_MemFoldPseudo\0" + /* 21979 */ "SLG_MemFoldPseudo\0" + /* 21997 */ "NG_MemFoldPseudo\0" + /* 22014 */ "OG_MemFoldPseudo\0" + /* 22031 */ "SG_MemFoldPseudo\0" + /* 22048 */ "XG_MemFoldPseudo\0" + /* 22065 */ "AL_MemFoldPseudo\0" + /* 22082 */ "SL_MemFoldPseudo\0" + /* 22099 */ "N_MemFoldPseudo\0" + /* 22115 */ "O_MemFoldPseudo\0" + /* 22131 */ "S_MemFoldPseudo\0" + /* 22147 */ "X_MemFoldPseudo\0" + /* 22163 */ "LOCMux_MemFoldPseudo\0" + /* 22184 */ "CondTrap\0" + /* 22193 */ "CLSTLoop\0" + /* 22202 */ "SRSTLoop\0" + /* 22211 */ "MVSTLoop\0" + /* 22220 */ "MemBarrier\0" + /* 22231 */ "CPSDRds\0" + /* 22239 */ "CPSDRss\0" + /* 22247 */ "TBEGIN_nofloat\0" + /* 22262 */ "CU21Opt\0" + /* 22270 */ "CU12Opt\0" + /* 22278 */ "CU14Opt\0" + /* 22286 */ "CU24Opt\0" + /* 22294 */ "VCVBOpt\0" + /* 22302 */ "SSKEOpt\0" + /* 22310 */ "TRTREOpt\0" + /* 22319 */ "IDTEOpt\0" + /* 22327 */ "CRDTEOpt\0" + /* 22336 */ "IPTEOpt\0" + /* 22344 */ "TRTEOpt\0" + /* 22352 */ "CUUTFOpt\0" + /* 22361 */ "VCVBGOpt\0" + /* 22370 */ "TROOOpt\0" + /* 22378 */ "TRTOOpt\0" + /* 22386 */ "RDPOpt\0" + /* 22393 */ "POPCNTOpt\0" + /* 22403 */ "TROTOpt\0" + /* 22411 */ "TRTTOpt\0" + /* 22419 */ "CUTFUOpt\0" + /* 22428 */ "IPTEOptOpt\0" + /* 22439 */ "CondStoreF32Inv\0" + /* 22455 */ "CondStore32Inv\0" + /* 22470 */ "CondStoreF64Inv\0" + /* 22486 */ "CondStore64Inv\0" + /* 22501 */ "CondStore16Inv\0" + /* 22516 */ "CondStore8Inv\0" + /* 22530 */ "CondStore32MuxInv\0" + /* 22548 */ "CondStore16MuxInv\0" + /* 22566 */ "CondStore8MuxInv\0" + /* 22583 */ "CondStore32Mux\0" + /* 22598 */ "CondStore16Mux\0" + /* 22613 */ "CondStore8Mux\0" + /* 22627 */ "LBMux\0" + /* 22633 */ "RISBMux\0" + /* 22641 */ "LLCMux\0" + /* 22648 */ "LOCMux\0" + /* 22655 */ "STOCMux\0" + /* 22663 */ "STCMux\0" + /* 22670 */ "IIFMux\0" + /* 22677 */ "NIFMux\0" + /* 22684 */ "OIFMux\0" + /* 22691 */ "XIFMux\0" + /* 22698 */ "IIHMux\0" + /* 22705 */ "NIHMux\0" + /* 22712 */ "OIHMux\0" + /* 22719 */ "LLHMux\0" + /* 22726 */ "TMHMux\0" + /* 22733 */ "STHMux\0" + /* 22740 */ "AFIMux\0" + /* 22747 */ "CFIMux\0" + /* 22754 */ "CLFIMux\0" + /* 22762 */ "AHIMux\0" + /* 22769 */ "LOCHIMux\0" + /* 22778 */ "LHIMux\0" + /* 22785 */ "CLMux\0" + /* 22791 */ "IILMux\0" + /* 22798 */ "NILMux\0" + /* 22805 */ "OILMux\0" + /* 22812 */ "TMLMux\0" + /* 22819 */ "LLCRMux\0" + /* 22827 */ "LOCRMux\0" + /* 22835 */ "LLHRMux\0" + /* 22843 */ "SELRMux\0" + /* 22851 */ "STMux\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern const unsigned SystemZInstrNameIndices[] = { + 11587U, 13963U, 16282U, 14468U, 12097U, 12078U, 12106U, 12353U, 7994U, + 8009U, 7048U, 8041U, 18691U, 6449U, 19405U, 7102U, 11583U, 12087U, + 3801U, 20202U, 4883U, 19300U, 3595U, 3736U, 3789U, 15024U, 12324U, + 19191U, 3667U, 15504U, 8399U, 19180U, 6331U, 15426U, 15413U, 16542U, + 19014U, 19068U, 12256U, 12303U, 12276U, 12123U, 19472U, 19502U, 3458U, + 2651U, 13178U, 19630U, 19637U, 13666U, 13673U, 13680U, 13690U, 3568U, + 17285U, 17233U, 7046U, 11585U, 19900U, 6459U, 18922U, 18293U, 19319U, + 18310U, 17185U, 3126U, 18645U, 19202U, 17624U, 19378U, 6502U, 3100U, + 3641U, 19221U, 14243U, 16567U, 3356U, 3300U, 3330U, 3341U, 3281U, + 3311U, 6364U, 6348U, 18708U, 8100U, 8117U, 3474U, 2657U, 3574U, + 3535U, 17306U, 17239U, 19884U, 14437U, 19850U, 14403U, 3425U, 2634U, + 3781U, 3608U, 18945U, 3026U, 18745U, 19486U, 3118U, 19162U, 19150U, + 19290U, 8391U, 19465U, 8028U, 19495U, 12204U, 17001U, 16987U, 12197U, + 16994U, 17617U, 13085U, 15186U, 15179U, 18936U, 14538U, 3822U, 14522U, + 3762U, 14530U, 3814U, 14514U, 3754U, 14569U, 14561U, 9671U, 9663U, + 18833U, 18823U, 18813U, 18803U, 18853U, 18843U, 19928U, 19938U, 18863U, + 18876U, 19948U, 19958U, 18889U, 18902U, 3383U, 2613U, 13120U, 1009U, + 3274U, 19609U, 13645U, 19704U, 11753U, 15523U, 274U, 8334U, 260U, + 0U, 7987U, 19457U, 3090U, 11695U, 11740U, 15117U, 15126U, 17929U, + 14277U, 6511U, 14032U, 14042U, 3839U, 3854U, 14010U, 14021U, 3464U, + 11997U, 14354U, 19801U, 14378U, 19825U, 17936U, 3632U, 3622U, 16277U, + 19092U, 19124U, 19103U, 17200U, 20484U, 7028U, 20262U, 7010U, 15399U, + 15042U, 6390U, 12210U, 18620U, 14453U, 19351U, 17176U, 19213U, 19239U, + 19388U, 16346U, 4858U, 3169U, 3411U, 2620U, 13148U, 19616U, 13652U, + 1015U, 19359U, 16586U, 16602U, 20193U, 5862U, 6474U, 19028U, 14813U, + 3390U, 13127U, 3366U, 13103U, 19767U, 14320U, 3442U, 13162U, 3552U, + 17270U, 17217U, 19784U, 14337U, 19808U, 14361U, 19914U, 19921U, 21740U, + 14488U, 15489U, 3186U, 21814U, 902U, 22740U, 21925U, 22762U, 12018U, + 21961U, 22065U, 19724U, 11409U, 15851U, 19867U, 14420U, 9063U, 20939U, + 17160U, 21009U, 9098U, 17290U, 17380U, 19832U, 14385U, 7399U, 17884U, + 11393U, 11430U, 11522U, 16733U, 11500U, 15836U, 215U, 802U, 134U, + 748U, 16818U, 20976U, 305U, 20783U, 456U, 20823U, 597U, 20863U, + 7348U, 369U, 20803U, 20903U, 9046U, 508U, 20843U, 20921U, 12364U, + 649U, 20883U, 20958U, 17145U, 20993U, 16840U, 324U, 475U, 616U, + 7365U, 388U, 9081U, 527U, 12381U, 668U, 17255U, 16871U, 17365U, + 195U, 782U, 114U, 728U, 16909U, 343U, 7382U, 407U, 17869U, + 19711U, 153U, 767U, 21723U, 22747U, 21034U, 21553U, 21070U, 21597U, + 22771U, 21026U, 21543U, 21098U, 20751U, 22754U, 21043U, 21564U, 21079U, + 21608U, 21053U, 21576U, 22785U, 21089U, 21620U, 22193U, 22643U, 21062U, + 21587U, 17346U, 572U, 16302U, 16295U, 13032U, 553U, 12054U, 8171U, + 21631U, 848U, 22501U, 22598U, 22548U, 234U, 22455U, 22583U, 22530U, + 821U, 22486U, 918U, 22516U, 22613U, 22566U, 41U, 22439U, 426U, + 22470U, 22184U, 21758U, 21832U, 21642U, 19252U, 22670U, 298U, 449U, + 590U, 22698U, 362U, 501U, 642U, 22791U, 871U, 22627U, 16658U, + 16484U, 22778U, 22720U, 22641U, 22819U, 22719U, 22835U, 22786U, 21942U, + 22769U, 22648U, 22163U, 22827U, 21654U, 21677U, 21700U, 19968U, 21739U, + 21813U, 21776U, 21850U, 21907U, 21794U, 21869U, 21888U, 21117U, 20770U, + 22211U, 22220U, 21105U, 20758U, 21997U, 22677U, 317U, 468U, 609U, + 22705U, 381U, 520U, 661U, 22798U, 22099U, 21111U, 20764U, 22014U, + 22684U, 336U, 487U, 628U, 22712U, 400U, 539U, 680U, 22805U, + 22115U, 876U, 933U, 3151U, 8874U, 12159U, 9009U, 12336U, 22633U, + 21546U, 21795U, 21870U, 22843U, 22031U, 21979U, 22082U, 22202U, 896U, + 22663U, 22733U, 22851U, 22655U, 20009U, 22131U, 246U, 833U, 860U, + 54U, 439U, 884U, 97U, 711U, 20741U, 22247U, 12234U, 12245U, + 494U, 635U, 22726U, 546U, 687U, 22812U, 22188U, 72U, 694U, + 91U, 705U, 77U, 108U, 722U, 21124U, 20777U, 22048U, 22691U, + 355U, 419U, 22147U, 910U, 931U, 3278U, 1361U, 15868U, 16332U, + 17432U, 1188U, 3724U, 1760U, 15981U, 16449U, 11405U, 7823U, 7127U, + 11442U, 16663U, 8826U, 11534U, 11848U, 16745U, 11911U, 11641U, 8649U, + 16950U, 17070U, 11512U, 11843U, 20088U, 8959U, 12028U, 3062U, 7928U, + 16755U, 16316U, 11476U, 8185U, 7141U, 11452U, 16674U, 11854U, 16782U, + 11928U, 11646U, 16956U, 17076U, 11862U, 17043U, 11968U, 11690U, 8992U, + 14289U, 20143U, 15030U, 15807U, 11897U, 11637U, 19552U, 17777U, 19681U, + 17790U, 16183U, 17798U, 17671U, 1233U, 20023U, 1307U, 17037U, 12031U, + 17042U, 17915U, 17350U, 13995U, 6538U, 10951U, 4378U, 13210U, 5406U, + 9687U, 14057U, 5885U, 10196U, 3886U, 12441U, 4903U, 9148U, 13740U, + 14601U, 15197U, 20269U, 14842U, 15537U, 20495U, 2975U, 21194U, 16306U, + 21366U, 18932U, 8509U, 16887U, 17396U, 11362U, 6672U, 11085U, 4527U, + 13344U, 5555U, 9836U, 14127U, 6034U, 10345U, 4050U, 12590U, 5067U, + 9312U, 13818U, 14679U, 15275U, 20347U, 14912U, 15607U, 20565U, 3022U, + 21200U, 15438U, 15446U, 15870U, 17924U, 13036U, 6783U, 11196U, 4650U, + 13455U, 5678U, 9959U, 14172U, 6157U, 10468U, 4185U, 12713U, 5202U, + 9447U, 13868U, 14729U, 15325U, 20397U, 14957U, 15652U, 20610U, 3228U, + 21222U, 12058U, 21358U, 18965U, 8527U, 10795U, 10862U, 8145U, 5398U, + 8280U, 1275U, 8468U, 13973U, 10853U, 8140U, 5393U, 7981U, 2960U, + 3363U, 1403U, 15874U, 16089U, 1096U, 16636U, 17555U, 16128U, 1117U, + 16767U, 17581U, 1219U, 16101U, 17561U, 16140U, 17587U, 19267U, 16342U, + 18289U, 8476U, 17640U, 20211U, 17437U, 17658U, 19542U, 3773U, 1771U, + 15987U, 17447U, 16095U, 1103U, 16653U, 16134U, 1124U, 16777U, 16108U, + 16147U, 16454U, 17687U, 3004U, 15890U, 1054U, 16370U, 17471U, 16010U, + 1075U, 16479U, 11426U, 16206U, 1152U, 17817U, 17705U, 7914U, 15903U, + 1061U, 16375U, 17484U, 1200U, 16023U, 1082U, 16489U, 7131U, 11447U, + 16669U, 12915U, 8830U, 11541U, 12957U, 11664U, 2019U, 21137U, 6544U, + 10957U, 4385U, 13216U, 5413U, 9694U, 5892U, 10203U, 3894U, 12448U, + 4911U, 9156U, 11768U, 21301U, 6719U, 11132U, 4579U, 13391U, 5607U, + 9888U, 6086U, 10397U, 4107U, 12642U, 5124U, 9369U, 19057U, 21451U, + 6877U, 11290U, 4754U, 13549U, 5782U, 10063U, 6261U, 10572U, 4299U, + 12817U, 5316U, 9561U, 16757U, 2231U, 21169U, 6580U, 10993U, 4425U, + 13252U, 5453U, 9734U, 5932U, 10243U, 3938U, 12488U, 4955U, 9200U, + 11788U, 21333U, 6755U, 11168U, 4619U, 13427U, 5647U, 9928U, 6126U, + 10437U, 4151U, 12682U, 5168U, 9413U, 12935U, 19328U, 21482U, 6912U, + 11325U, 4793U, 13584U, 5821U, 10102U, 6300U, 10611U, 4342U, 12856U, + 5359U, 9604U, 16219U, 1159U, 17822U, 17718U, 1245U, 8675U, 7209U, + 16945U, 11677U, 11518U, 17065U, 12952U, 11652U, 20092U, 2009U, 21130U, + 6536U, 10949U, 4376U, 13208U, 5404U, 9685U, 5883U, 10194U, 3884U, + 12439U, 4901U, 9146U, 8970U, 11764U, 21294U, 6711U, 11124U, 4570U, + 13383U, 5598U, 9879U, 6077U, 10388U, 4097U, 12633U, 5114U, 9359U, + 19047U, 21435U, 6859U, 11272U, 4734U, 13531U, 5762U, 10043U, 6241U, + 10552U, 4277U, 12797U, 5294U, 9539U, 13978U, 12046U, 3066U, 12049U, + 4871U, 19567U, 15896U, 17477U, 16016U, 11657U, 11481U, 19051U, 21442U, + 6867U, 11280U, 4743U, 13539U, 5771U, 10052U, 6250U, 10561U, 4287U, + 12806U, 5304U, 9549U, 16212U, 17711U, 8198U, 15909U, 17490U, 16029U, + 7146U, 11458U, 16680U, 12921U, 12963U, 11670U, 2024U, 21145U, 6553U, + 10966U, 4395U, 13225U, 5423U, 9704U, 5902U, 10213U, 3905U, 12458U, + 4922U, 9167U, 11773U, 21309U, 6728U, 11141U, 4589U, 13400U, 5617U, + 9898U, 6096U, 10407U, 4118U, 12652U, 5135U, 9380U, 19062U, 21459U, + 6886U, 11299U, 4764U, 13558U, 5792U, 10073U, 6271U, 10582U, 4310U, + 12827U, 5327U, 9572U, 16787U, 2236U, 21177U, 6589U, 11002U, 4435U, + 13261U, 5463U, 9744U, 5942U, 10253U, 3949U, 12498U, 4966U, 9211U, + 11793U, 21341U, 6764U, 11177U, 4629U, 13436U, 5657U, 9938U, 6136U, + 10447U, 4162U, 12692U, 5179U, 9424U, 12940U, 19333U, 21490U, 6921U, + 11334U, 4803U, 13593U, 5831U, 10112U, 6310U, 10621U, 4353U, 12866U, + 5370U, 9615U, 19037U, 21427U, 6850U, 11263U, 4724U, 13522U, 5752U, + 10033U, 6231U, 10542U, 4266U, 12787U, 5283U, 9528U, 16225U, 17724U, + 7246U, 16976U, 11683U, 17096U, 12977U, 11596U, 2030U, 21154U, 6563U, + 10976U, 4406U, 13235U, 5434U, 9715U, 5913U, 10224U, 3917U, 12469U, + 4934U, 9179U, 8980U, 11779U, 21318U, 6738U, 11151U, 4600U, 13410U, + 5628U, 9909U, 6107U, 10418U, 4130U, 12663U, 5147U, 9392U, 20113U, + 13727U, 10162U, 20177U, 17047U, 2242U, 21186U, 6599U, 11012U, 4446U, + 13271U, 5474U, 9755U, 5953U, 10264U, 3961U, 12509U, 4978U, 9223U, + 11799U, 21350U, 6774U, 11187U, 4640U, 13446U, 5668U, 9949U, 6147U, + 10458U, 4174U, 12703U, 5191U, 9436U, 12995U, 19339U, 21499U, 6931U, + 11344U, 4814U, 13603U, 5842U, 10123U, 6321U, 10632U, 4365U, 12877U, + 5382U, 9627U, 19420U, 19099U, 21468U, 6896U, 11309U, 4775U, 13568U, + 5803U, 10084U, 6282U, 10593U, 4322U, 12838U, 5339U, 9584U, 20147U, + 3253U, 15056U, 18987U, 20677U, 22231U, 20685U, 22239U, 19527U, 1297U, + 16307U, 2227U, 21162U, 6572U, 10985U, 4416U, 13244U, 5444U, 9725U, + 5923U, 10234U, 3928U, 12479U, 4945U, 9190U, 6429U, 22327U, 11784U, + 21326U, 6747U, 11160U, 4610U, 13419U, 5638U, 9919U, 6117U, 10428U, + 4141U, 12673U, 5158U, 9403U, 12905U, 19315U, 21475U, 6904U, 11317U, + 4784U, 13576U, 5812U, 10093U, 6291U, 10602U, 4332U, 12847U, 5349U, + 9594U, 18286U, 8705U, 17519U, 8472U, 15465U, 8368U, 19430U, 17753U, + 20207U, 25U, 22270U, 282U, 22278U, 9U, 22262U, 293U, 22286U, + 20U, 255U, 17537U, 6419U, 19555U, 22419U, 7699U, 22352U, 17771U, + 2682U, 7906U, 20035U, 3710U, 7960U, 20058U, 16189U, 16122U, 1110U, + 16728U, 17575U, 16161U, 1131U, 16904U, 17607U, 1226U, 16115U, 17568U, + 16154U, 17600U, 19285U, 17803U, 17652U, 17676U, 17664U, 19547U, 20041U, + 18997U, 19537U, 3279U, 3380U, 1428U, 15879U, 16355U, 17442U, 1194U, + 3819U, 1777U, 15993U, 16460U, 2993U, 7831U, 15916U, 16036U, 12070U, + 8204U, 16792U, 17051U, 15063U, 16333U, 8477U, 7175U, 16710U, 16861U, + 16195U, 17808U, 17682U, 1239U, 15806U, 7826U, 17401U, 977U, 8514U, + 3492U, 11879U, 17453U, 17693U, 3207U, 17019U, 15817U, 17419U, 19747U, + 8023U, 8066U, 17025U, 15822U, 17525U, 957U, 1284U, 17759U, 3617U, + 19911U, 13027U, 15922U, 1068U, 16390U, 17497U, 16042U, 1089U, 16498U, + 16232U, 1166U, 17827U, 17731U, 16834U, 16386U, 16494U, 8710U, 2958U, + 3023U, 30U, 20016U, 13636U, 10133U, 20166U, 20040U, 6424U, 22319U, + 17459U, 17699U, 7213U, 8886U, 12171U, 7337U, 9035U, 12348U, 11884U, + 13942U, 6435U, 22336U, 22428U, 13626U, 4842U, 12013U, 6940U, 11630U, + 4824U, 12218U, 19579U, 18578U, 17339U, 6372U, 7635U, 18662U, 18684U, + 6403U, 11708U, 20220U, 20002U, 6494U, 7747U, 20232U, 18775U, 11729U, + 12226U, 20126U, 18738U, 6411U, 7675U, 11622U, 17331U, 18676U, 19673U, + 19994U, 11721U, 11766U, 6713U, 11126U, 4572U, 13385U, 5600U, 9881U, + 14166U, 6079U, 10390U, 4099U, 12635U, 5116U, 9361U, 13861U, 14722U, + 15318U, 20390U, 14951U, 15646U, 20604U, 8175U, 6644U, 11057U, 4496U, + 13316U, 5524U, 9805U, 14099U, 6003U, 10314U, 4016U, 12559U, 5033U, + 9278U, 13787U, 14648U, 15244U, 20316U, 14884U, 15579U, 20537U, 1594U, + 15928U, 1279U, 17503U, 1829U, 16048U, 3525U, 3530U, 13724U, 1028U, + 2962U, 3078U, 17413U, 7504U, 14579U, 16238U, 17737U, 12029U, 995U, + 929U, 7821U, 12026U, 8183U, 3727U, 20063U, 13612U, 20155U, 14239U, + 8319U, 14505U, 8329U, 12898U, 15460U, 18799U, 19757U, 8607U, 20022U, + 2045U, 15804U, 8668U, 16168U, 1326U, 13056U, 15873U, 16635U, 168U, + 16341U, 15986U, 16453U, 16668U, 16756U, 16317U, 13062U, 8268U, 16188U, + 17802U, 3517U, 3831U, 35U, 1776U, 15992U, 16464U, 17549U, 16772U, + 16395U, 85U, 16194U, 1138U, 17807U, 17681U, 20049U, 4855U, 15884U, + 1047U, 16365U, 17465U, 16504U, 16200U, 1145U, 17812U, 20068U, 17919U, + 8817U, 18793U, 3212U, 8186U, 18788U, 1931U, 16142U, 16380U, 7142U, + 11453U, 16675U, 12922U, 8072U, 8841U, 11546U, 16940U, 12964U, 16783U, + 12941U, 3238U, 9006U, 8910U, 11575U, 16983U, 12978U, 20096U, 3070U, + 8688U, 16321U, 3012U, 16310U, 7151U, 18781U, 16686U, 12928U, 8481U, + 8840U, 16939U, 12970U, 19042U, 18915U, 17594U, 9119U, 8914U, 16982U, + 12983U, 7218U, 8891U, 12176U, 7342U, 9040U, 12358U, 7168U, 13728U, + 3531U, 8304U, 10163U, 20178U, 15938U, 16641U, 177U, 16403U, 16053U, + 16512U, 16698U, 16813U, 17141U, 16248U, 17840U, 3165U, 21207U, 6608U, + 11021U, 4456U, 13280U, 5484U, 9765U, 14063U, 5963U, 10274U, 3972U, + 12519U, 4989U, 9234U, 13747U, 14608U, 15204U, 20276U, 14848U, 15543U, + 20501U, 8804U, 21246U, 6651U, 11064U, 4504U, 13323U, 5532U, 9813U, + 14106U, 6011U, 10322U, 4025U, 12567U, 5042U, 9287U, 13795U, 14656U, + 15252U, 20324U, 14891U, 15586U, 20544U, 16925U, 21399U, 6819U, 11232U, + 4690U, 13491U, 5718U, 9999U, 14208U, 6197U, 10508U, 4229U, 12753U, + 5246U, 9491U, 13908U, 14769U, 15365U, 20437U, 14993U, 15688U, 20646U, + 7938U, 21229U, 6625U, 11038U, 4475U, 13297U, 5503U, 9784U, 14080U, + 5982U, 10293U, 3993U, 12538U, 5010U, 9255U, 13766U, 14627U, 15223U, + 20295U, 14865U, 15560U, 20518U, 11539U, 21274U, 6689U, 11102U, 4546U, + 13361U, 5574U, 9855U, 14144U, 6053U, 10364U, 4071U, 12609U, 5088U, + 9333U, 13837U, 14698U, 15294U, 20366U, 14929U, 15624U, 20582U, 16761U, + 21381U, 6799U, 11212U, 4668U, 13471U, 5696U, 9977U, 14188U, 6175U, + 10486U, 4205U, 12731U, 5222U, 9467U, 13886U, 14747U, 15343U, 20415U, + 14973U, 15668U, 20626U, 11562U, 21284U, 6700U, 11113U, 4558U, 13372U, + 5586U, 9867U, 14155U, 6065U, 10376U, 4084U, 12621U, 5101U, 9346U, + 13849U, 14710U, 15306U, 20378U, 14940U, 15635U, 20593U, 11516U, 21265U, + 6679U, 11092U, 4535U, 13351U, 5563U, 9844U, 14134U, 6042U, 10353U, + 4059U, 12598U, 5076U, 9321U, 13826U, 14687U, 15283U, 20355U, 14919U, + 15614U, 20572U, 16326U, 21373U, 6790U, 11203U, 4658U, 13462U, 5686U, + 9967U, 14179U, 6165U, 10476U, 4194U, 12721U, 5211U, 9456U, 13876U, + 14737U, 15333U, 20405U, 14964U, 15659U, 20617U, 13067U, 3659U, 15944U, + 16647U, 186U, 7954U, 16408U, 16059U, 16517U, 16704U, 16856U, 15442U, + 15773U, 17321U, 19752U, 6484U, 20077U, 962U, 16254U, 17845U, 17044U, + 1173U, 7848U, 20030U, 16418U, 16527U, 12996U, 19664U, 8596U, 16898U, + 10842U, 17785U, 13073U, 19100U, 15962U, 20702U, 16428U, 17531U, 16077U, + 20715U, 16537U, 8539U, 7185U, 16722U, 16893U, 17613U, 16271U, 20728U, + 17859U, 17765U, 1264U, 7866U, 3714U, 1748U, 15968U, 16433U, 17543U, + 6490U, 1879U, 16083U, 16625U, 17832U, 20144U, 16443U, 16630U, 7650U, + 8463U, 17864U, 13614U, 3277U, 1373U, 15867U, 16331U, 3732U, 1765U, + 15980U, 16448U, 20026U, 10867U, 17008U, 13192U, 17127U, 17900U, 3079U, + 3527U, 1606U, 15933U, 3835U, 1787U, 15998U, 16469U, 16399U, 17508U, + 1207U, 5853U, 3874U, 1798U, 16004U, 16474U, 16508U, 20084U, 8289U, + 8848U, 11551U, 11940U, 10135U, 11579U, 20100U, 12424U, 8233U, 16803U, + 17102U, 15183U, 17138U, 18611U, 3249U, 8715U, 3701U, 1704U, 15956U, + 16423U, 6386U, 1868U, 16071U, 16532U, 11491U, 8501U, 3017U, 7180U, + 11470U, 16716U, 16866U, 3049U, 17361U, 3056U, 1289U, 20216U, 3263U, + 11833U, 14296U, 11828U, 12063U, 4877U, 19573U, 18627U, 15054U, 12903U, + 18284U, 12007U, 11556U, 11569U, 11591U, 11749U, 20134U, 14484U, 14838U, + 8373U, 19435U, 20491U, 16243U, 3718U, 1753U, 15974U, 16438U, 17836U, + 17742U, 1252U, 20157U, 10872U, 17014U, 13197U, 17133U, 17905U, 14241U, + 3087U, 11916U, 11901U, 8321U, 16814U, 11946U, 11600U, 11353U, 7224U, + 8897U, 12182U, 7360U, 9058U, 12376U, 20118U, 11945U, 1038U, 11978U, + 11951U, 20693U, 11983U, 17142U, 11979U, 8543U, 11962U, 11992U, 20187U, + 14507U, 3166U, 11922U, 11906U, 8331U, 16836U, 11952U, 11603U, 7229U, + 8902U, 12187U, 7377U, 9093U, 12393U, 20122U, 17182U, 11984U, 20190U, + 11814U, 2048U, 3209U, 2989U, 14577U, 3495U, 12909U, 7487U, 14808U, + 14309U, 19445U, 985U, 19563U, 14557U, 19173U, 22393U, 1043U, 14587U, + 17322U, 14592U, 19269U, 7695U, 7122U, 11736U, 2133U, 17431U, 17670U, + 11616U, 11376U, 11704U, 15152U, 15072U, 22386U, 7881U, 64U, 14270U, + 8088U, 8189U, 12411U, 8223U, 7887U, 7893U, 15448U, 3749U, 13631U, + 17513U, 17747U, 8720U, 7899U, 17917U, 2967U, 6964U, 12040U, 287U, + 14U, 699U, 15823U, 17407U, 13713U, 11819U, 3038U, 7570U, 3702U, + 1692U, 15957U, 16424U, 17520U, 1213U, 6387U, 1869U, 16072U, 16932U, + 21409U, 6830U, 11243U, 4702U, 13502U, 5730U, 10011U, 14219U, 6209U, + 10520U, 4242U, 12765U, 5259U, 9504U, 13920U, 14781U, 15377U, 20449U, + 15004U, 15699U, 20657U, 16797U, 21390U, 6809U, 11222U, 4679U, 13481U, + 5707U, 9988U, 14198U, 6186U, 10497U, 4217U, 12742U, 5234U, 9479U, + 13897U, 14758U, 15354U, 20426U, 14983U, 15678U, 20636U, 17055U, 21419U, + 6841U, 11254U, 4714U, 13513U, 5742U, 10023U, 14230U, 6221U, 10532U, + 4255U, 12777U, 5272U, 9517U, 13932U, 14793U, 15389U, 20461U, 15015U, + 15710U, 20668U, 16533U, 17355U, 3217U, 8469U, 7176U, 16711U, 8852U, + 16862U, 11957U, 10766U, 16970U, 17090U, 20104U, 4832U, 972U, 15141U, + 13039U, 994U, 7836U, 11804U, 2124U, 7876U, 16749U, 16167U, 947U, + 12068U, 18982U, 11486U, 8258U, 7156U, 11464U, 16692U, 16808U, 11934U, + 16963U, 17083U, 12415U, 8228U, 11869U, 17119U, 11973U, 19522U, 20151U, + 13092U, 15462U, 17425U, 989U, 13946U, 19272U, 19979U, 3663U, 1678U, + 15950U, 16413U, 6344U, 1863U, 16065U, 16522U, 16260U, 17850U, 17352U, + 1179U, 7855U, 11809U, 952U, 12073U, 18992U, 11988U, 13012U, 8251U, + 11874U, 13735U, 2162U, 19144U, 15452U, 19425U, 19591U, 19532U, 17031U, + 15827U, 8725U, 4847U, 22302U, 13997U, 19385U, 13616U, 20160U, 15033U, + 15810U, 3259U, 8741U, 11823U, 3043U, 4836U, 7301U, 13640U, 10138U, + 20171U, 18633U, 19741U, 8533U, 13079U, 20044U, 3705U, 20053U, 6445U, + 20072U, 8821U, 12148U, 4890U, 3222U, 8545U, 12946U, 3243U, 10801U, + 8954U, 12989U, 20108U, 15066U, 14002U, 8308U, 10167U, 20182U, 13983U, + 3198U, 21214U, 6616U, 11029U, 4465U, 13288U, 5493U, 9774U, 14071U, + 5972U, 10283U, 3982U, 12528U, 4999U, 9244U, 13756U, 14617U, 15213U, + 20285U, 14856U, 15551U, 20509U, 8810U, 21255U, 6661U, 11074U, 4515U, + 13333U, 5543U, 9824U, 14116U, 6022U, 10333U, 4037U, 12578U, 5054U, + 9299U, 13806U, 14667U, 15263U, 20335U, 14901U, 15596U, 20554U, 7943U, + 21237U, 6634U, 11047U, 4485U, 13306U, 5513U, 9794U, 14089U, 5992U, + 10303U, 4004U, 12548U, 5021U, 9266U, 13776U, 14637U, 15233U, 20305U, + 14874U, 15569U, 20527U, 13989U, 15777U, 19276U, 19983U, 7860U, 13022U, + 19668U, 8601U, 10847U, 8730U, 11716U, 1269U, 8457U, 20228U, 19588U, + 17781U, 3267U, 19749U, 17794U, 16266U, 17855U, 17754U, 1258U, 20208U, + 19344U, 13617U, 15832U, 2610U, 16336U, 16359U, 14302U, 3082U, 1421U, + 1770U, 2749U, 18970U, 19002U, 19451U, 18976U, 19008U, 19516U, 3590U, + 16458U, 16385U, 14003U, 8932U, 12192U, 9130U, 12398U, 20183U, 15486U, + 11612U, 19256U, 17398U, 3770U, 7911U, 268U, 842U, 6382U, 14803U, + 22370U, 19262U, 22403U, 19374U, 6440U, 22344U, 14833U, 22378U, 17635U, + 6380U, 22310U, 19440U, 22411U, 18769U, 8731U, 11888U, 983U, 19561U, + 19281U, 1294U, 1322U, 2971U, 2978U, 1336U, 2983U, 15734U, 6969U, + 7917U, 8672U, 15728U, 15723U, 6960U, 7872U, 8664U, 15038U, 15719U, + 8557U, 1942U, 7190U, 8076U, 8856U, 12153U, 2059U, 7324U, 8208U, + 9022U, 13950U, 7949U, 1910U, 8202U, 1928U, 1884U, 1896U, 15741U, + 2221U, 18085U, 7581U, 18368U, 8378U, 18449U, 10704U, 18514U, 1803U, + 14265U, 12887U, 18639U, 3503U, 1510U, 8746U, 1960U, 18072U, 7208U, + 18355U, 8095U, 18436U, 8881U, 18501U, 12166U, 2066U, 18078U, 7331U, + 18361U, 8215U, 18442U, 9029U, 18507U, 13977U, 1815U, 10182U, 12427U, + 15111U, 3508U, 1522U, 20257U, 2938U, 15085U, 7792U, 8624U, 10920U, + 7508U, 15055U, 7518U, 15135U, 10693U, 20479U, 2952U, 7815U, 8639U, + 10943U, 2681U, 7905U, 22361U, 22294U, 3709U, 7959U, 15081U, 3000U, + 1342U, 6975U, 7923U, 8678U, 12044U, 2053U, 7318U, 8196U, 9016U, + 13718U, 2155U, 7497U, 8297U, 10155U, 12409U, 2079U, 7424U, 8221U, + 9123U, 19644U, 2692U, 7719U, 8568U, 10819U, 13042U, 2122U, 7461U, + 8256U, 9657U, 19658U, 2708U, 7735U, 8584U, 10835U, 1177U, 1309U, + 6953U, 7853U, 8657U, 19597U, 2673U, 7705U, 8549U, 10805U, 13010U, + 2109U, 7454U, 8249U, 9650U, 19651U, 2700U, 7727U, 8576U, 10827U, + 968U, 1359U, 3722U, 1758U, 18050U, 6992U, 18333U, 8750U, 18479U, + 2909U, 18259U, 7763U, 18411U, 10884U, 18553U, 2254U, 3776U, 1438U, + 17950U, 2328U, 18100U, 8683U, 1536U, 18018U, 3878U, 1452U, 17966U, + 2342U, 18116U, 2388U, 18168U, 3499U, 1426U, 2316U, 3869U, 1792U, + 18057U, 7061U, 18340U, 8762U, 18486U, 2916U, 18267U, 7770U, 18419U, + 10891U, 18561U, 5856U, 1856U, 18064U, 7095U, 18347U, 8791U, 18493U, + 2930U, 18275U, 7784U, 18427U, 10905U, 18569U, 11496U, 1580U, 2432U, + 1484U, 18002U, 2374U, 18152U, 1550U, 18034U, 1468U, 17984U, 2358U, + 18134U, 2402U, 18184U, 1407U, 2302U, 12343U, 18597U, 1632U, 2478U, + 1662U, 2508U, 17060U, 3684U, 13705U, 1004U, 1371U, 2266U, 19761U, + 1732U, 2589U, 1604U, 14314U, 1616U, 2462U, 18609U, 2450U, 1702U, + 2555U, 1032U, 1385U, 2280U, 18614U, 1716U, 2569U, 14827U, 1646U, + 2492U, 18398U, 1690U, 15795U, 1676U, 2522U, 2543U, 11382U, 1564U, + 2416U, 13621U, 7067U, 7971U, 13700U, 998U, 1302U, 6946U, 7841U, + 8645U, 2144U, 7481U, 8286U, 10144U, 13709U, 2150U, 7492U, 8292U, + 10150U, 17646U, 2247U, 18092U, 7643U, 18375U, 10756U, 18521U, 13184U, + 21507U, 1331U, 16172U, 7609U, 8431U, 10725U, 15782U, 15098U, 7555U, + 8348U, 10673U, 3074U, 1347U, 6980U, 7933U, 8693U, 3830U, 1775U, + 1846U, 7594U, 8416U, 10710U, 3490U, 1498U, 7085U, 7976U, 8781U, + 2013U, 7288U, 8158U, 8974U, 16503U, 7622U, 8444U, 10738U, 19604U, + 2686U, 7713U, 8562U, 10813U, 15170U, 12419U, 20471U, 6527U, 7798U, + 8630U, 10926U, 20240U, 2923U, 7777U, 8617U, 10898U, 7473U, 13731U, + 21515U, 15175U, 2216U, 7576U, 8363U, 10688U, 17123U, 15092U, 2203U, + 7548U, 8341U, 10666U, 13000U, 17106U, 8591U, 1948U, 7196U, 8082U, + 8862U, 15146U, 3731U, 1764U, 6998U, 8756U, 8652U, 1954U, 7202U, + 8868U, 12035U, 2042U, 4852U, 1833U, 7072U, 8768U, 7312U, 9003U, + 1965U, 7239U, 8907U, 19684U, 14546U, 2185U, 7530U, 10648U, 14509U, + 2179U, 7524U, 10642U, 5852U, 1851U, 7090U, 8786U, 10178U, 1985U, + 7264U, 8937U, 12423U, 2086U, 4896U, 1840U, 7079U, 8775U, 7431U, + 9135U, 1972U, 7251U, 8919U, 19691U, 14552U, 2192U, 7537U, 10655U, + 14460U, 2174U, 7513U, 8324U, 10189U, 12434U, 2091U, 7436U, 8237U, + 9140U, 14583U, 2198U, 7543U, 10661U, 15193U, 10751U, 1996U, 7275U, + 8134U, 8948U, 13005U, 2103U, 7448U, 8243U, 9644U, 13047U, 8262U, + 15476U, 19971U, 2830U, 7742U, 8612U, 10857U, 13187U, 2138U, 7467U, + 8274U, 9679U, 14485U, 3147U, 14464U, 14597U, 19975U, 14839U, 3203U, + 5878U, 11388U, 13957U, 11893U, 7307U, 8178U, 8998U, 18591U, 7661U, + 18390U, 8494U, 18463U, 10769U, 18536U, 18586U, 7655U, 18383U, 8488U, + 18456U, 10763U, 18529U, 20252U, 17909U, 18958U, 2605U, 7687U, 8519U, + 10787U, 15407U, 15106U, 2210U, 7564U, 8357U, 10682U, 11606U, 2035U, + 7294U, 8164U, 8985U, 15456U, 18772U, 2585U, 11358U, 15746U, 11371U, + 15761U, 11365U, 2002U, 7281U, 8151U, 8963U, 15754U, 7004U, 7965U, + 15059U, 15157U, 15469U, 15530U, 15163U, 15076U, 8055U, 1922U, 7135U, + 8834U, 12143U, 7683U, 8505U, 10783U, 13052U, 2128U, 3520U, 1598U, + 15481U, 15800U, 1183U, 1316U, 3696U, 13016U, 2116U, 15451U, 17325U, + 19436U, 21534U, 16177U, 7615U, 8437U, 10731U, 15788U, 1873U, 7601U, + 8423U, 10717U, 7116U, 8060U, 8798U, 16619U, 7628U, 8450U, 10744U, + 13098U, 14001U, 21524U, 3232U, 1352U, 17942U, 6985U, 18325U, 8698U, + 18471U, 2901U, 18250U, 7755U, 18402U, 10876U, 18544U, 13021U, 17112U, + 18670U, 2536U, 7668U, 10776U, 2944U, 7807U, 10935U, 14052U, 2168U, + 8313U, 7161U, 8845U, 10172U, 15767U, 7587U, 8384U, 14006U, 15485U, + 10699U, 1990U, 7269U, 8942U, 20246U, 10913U, 13201U, 12893U, 2097U, + 7442U, 9638U, 1978U, 7257U, 8925U, 19697U, 12403U, 2072U, 7417U, + 9116U, 20013U, 14821U, 1916U, 1935U, 1890U, 1903U, 1809U, 1516U, + 1822U, 1529U, 1365U, 2260U, 2715U, 3008U, 1401U, 1445U, 17958U, + 2335U, 18108U, 2760U, 18200U, 1543U, 18026U, 1460U, 17975U, 2350U, + 18125U, 2767U, 18208U, 2395U, 18176U, 2790U, 18234U, 2296U, 2736U, + 1432U, 2322U, 2754U, 1586U, 2438U, 2812U, 11839U, 1592U, 1491U, + 18010U, 2381U, 18160U, 2783U, 18226U, 1557U, 18042U, 1476U, 17993U, + 2366U, 18143U, 2775U, 18217U, 2409U, 18192U, 2797U, 18242U, 2444U, + 2818U, 1414U, 2309U, 2742U, 3514U, 18603U, 1639U, 2485U, 2843U, + 1669U, 2515U, 2858U, 3690U, 19988U, 1378U, 2273U, 2721U, 1740U, + 2597U, 2893U, 1610U, 1624U, 2470U, 2835U, 2456U, 1709U, 2562U, + 2878U, 2824U, 1393U, 2288U, 2728U, 1724U, 2577U, 2885U, 1654U, + 2500U, 2850U, 1696U, 1683U, 2529U, 2865U, 2549U, 2872U, 1572U, + 2424U, 2804U, 1781U, 1504U, 19759U, 3271U, 8609U, 16905U, 11963U, + 11761U, 7234U, 7394U, 20139U, 17799U, 11993U, 8736U, 20237U, 15050U, +}; -FieldFromInstruction(fieldFromInstruction, uint64_t) -DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint64_t) -DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint64_t) +#endif // GET_INSTRINFO_MC_DESC diff --git a/arch/SystemZ/SystemZGenInsnNameMaps.inc b/arch/SystemZ/SystemZGenInsnNameMaps.inc index c4d605ab18..657a36104c 100644 --- a/arch/SystemZ/SystemZGenInsnNameMaps.inc +++ b/arch/SystemZ/SystemZGenInsnNameMaps.inc @@ -1,2348 +1,994 @@ // This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh - { SYSZ_INS_A, "a" }, - { SYSZ_INS_ADB, "adb" }, - { SYSZ_INS_ADBR, "adbr" }, - { SYSZ_INS_AEB, "aeb" }, - { SYSZ_INS_AEBR, "aebr" }, - { SYSZ_INS_AFI, "afi" }, - { SYSZ_INS_AG, "ag" }, - { SYSZ_INS_AGF, "agf" }, - { SYSZ_INS_AGFI, "agfi" }, - { SYSZ_INS_AGFR, "agfr" }, - { SYSZ_INS_AGHI, "aghi" }, - { SYSZ_INS_AGHIK, "aghik" }, - { SYSZ_INS_AGR, "agr" }, - { SYSZ_INS_AGRK, "agrk" }, - { SYSZ_INS_AGSI, "agsi" }, - { SYSZ_INS_AH, "ah" }, - { SYSZ_INS_AHI, "ahi" }, - { SYSZ_INS_AHIK, "ahik" }, - { SYSZ_INS_AHY, "ahy" }, - { SYSZ_INS_AIH, "aih" }, - { SYSZ_INS_AL, "al" }, - { SYSZ_INS_ALC, "alc" }, - { SYSZ_INS_ALCG, "alcg" }, - { SYSZ_INS_ALCGR, "alcgr" }, - { SYSZ_INS_ALCR, "alcr" }, - { SYSZ_INS_ALFI, "alfi" }, - { SYSZ_INS_ALG, "alg" }, - { SYSZ_INS_ALGF, "algf" }, - { SYSZ_INS_ALGFI, "algfi" }, - { SYSZ_INS_ALGFR, "algfr" }, - { SYSZ_INS_ALGHSIK, "alghsik" }, - { SYSZ_INS_ALGR, "algr" }, - { SYSZ_INS_ALGRK, "algrk" }, - { SYSZ_INS_ALHSIK, "alhsik" }, - { SYSZ_INS_ALR, "alr" }, - { SYSZ_INS_ALRK, "alrk" }, - { SYSZ_INS_ALY, "aly" }, - { SYSZ_INS_AR, "ar" }, - { SYSZ_INS_ARK, "ark" }, - { SYSZ_INS_ASI, "asi" }, - { SYSZ_INS_AXBR, "axbr" }, - { SYSZ_INS_AY, "ay" }, - { SYSZ_INS_BCR, "bcr" }, - { SYSZ_INS_BRC, "brc" }, - { SYSZ_INS_BRCL, "brcl" }, - { SYSZ_INS_CGIJ, "cgij" }, - { SYSZ_INS_CGRJ, "cgrj" }, - { SYSZ_INS_CIJ, "cij" }, - { SYSZ_INS_CLGIJ, "clgij" }, - { SYSZ_INS_CLGRJ, "clgrj" }, - { SYSZ_INS_CLIJ, "clij" }, - { SYSZ_INS_CLRJ, "clrj" }, - { SYSZ_INS_CRJ, "crj" }, - { SYSZ_INS_BER, "ber" }, - { SYSZ_INS_JE, "je" }, - { SYSZ_INS_JGE, "jge" }, - { SYSZ_INS_LOCE, "loce" }, - { SYSZ_INS_LOCGE, "locge" }, - { SYSZ_INS_LOCGRE, "locgre" }, - { SYSZ_INS_LOCRE, "locre" }, - { SYSZ_INS_STOCE, "stoce" }, - { SYSZ_INS_STOCGE, "stocge" }, - { SYSZ_INS_BHR, "bhr" }, - { SYSZ_INS_BHER, "bher" }, - { SYSZ_INS_JHE, "jhe" }, - { SYSZ_INS_JGHE, "jghe" }, - { SYSZ_INS_LOCHE, "loche" }, - { SYSZ_INS_LOCGHE, "locghe" }, - { SYSZ_INS_LOCGRHE, "locgrhe" }, - { SYSZ_INS_LOCRHE, "locrhe" }, - { SYSZ_INS_STOCHE, "stoche" }, - { SYSZ_INS_STOCGHE, "stocghe" }, - { SYSZ_INS_JH, "jh" }, - { SYSZ_INS_JGH, "jgh" }, - { SYSZ_INS_LOCH, "loch" }, - { SYSZ_INS_LOCGH, "locgh" }, - { SYSZ_INS_LOCGRH, "locgrh" }, - { SYSZ_INS_LOCRH, "locrh" }, - { SYSZ_INS_STOCH, "stoch" }, - { SYSZ_INS_STOCGH, "stocgh" }, - { SYSZ_INS_CGIJNLH, "cgijnlh" }, - { SYSZ_INS_CGRJNLH, "cgrjnlh" }, - { SYSZ_INS_CIJNLH, "cijnlh" }, - { SYSZ_INS_CLGIJNLH, "clgijnlh" }, - { SYSZ_INS_CLGRJNLH, "clgrjnlh" }, - { SYSZ_INS_CLIJNLH, "clijnlh" }, - { SYSZ_INS_CLRJNLH, "clrjnlh" }, - { SYSZ_INS_CRJNLH, "crjnlh" }, - { SYSZ_INS_CGIJE, "cgije" }, - { SYSZ_INS_CGRJE, "cgrje" }, - { SYSZ_INS_CIJE, "cije" }, - { SYSZ_INS_CLGIJE, "clgije" }, - { SYSZ_INS_CLGRJE, "clgrje" }, - { SYSZ_INS_CLIJE, "clije" }, - { SYSZ_INS_CLRJE, "clrje" }, - { SYSZ_INS_CRJE, "crje" }, - { SYSZ_INS_CGIJNLE, "cgijnle" }, - { SYSZ_INS_CGRJNLE, "cgrjnle" }, - { SYSZ_INS_CIJNLE, "cijnle" }, - { SYSZ_INS_CLGIJNLE, "clgijnle" }, - { SYSZ_INS_CLGRJNLE, "clgrjnle" }, - { SYSZ_INS_CLIJNLE, "clijnle" }, - { SYSZ_INS_CLRJNLE, "clrjnle" }, - { SYSZ_INS_CRJNLE, "crjnle" }, - { SYSZ_INS_CGIJH, "cgijh" }, - { SYSZ_INS_CGRJH, "cgrjh" }, - { SYSZ_INS_CIJH, "cijh" }, - { SYSZ_INS_CLGIJH, "clgijh" }, - { SYSZ_INS_CLGRJH, "clgrjh" }, - { SYSZ_INS_CLIJH, "clijh" }, - { SYSZ_INS_CLRJH, "clrjh" }, - { SYSZ_INS_CRJH, "crjh" }, - { SYSZ_INS_CGIJNL, "cgijnl" }, - { SYSZ_INS_CGRJNL, "cgrjnl" }, - { SYSZ_INS_CIJNL, "cijnl" }, - { SYSZ_INS_CLGIJNL, "clgijnl" }, - { SYSZ_INS_CLGRJNL, "clgrjnl" }, - { SYSZ_INS_CLIJNL, "clijnl" }, - { SYSZ_INS_CLRJNL, "clrjnl" }, - { SYSZ_INS_CRJNL, "crjnl" }, - { SYSZ_INS_CGIJHE, "cgijhe" }, - { SYSZ_INS_CGRJHE, "cgrjhe" }, - { SYSZ_INS_CIJHE, "cijhe" }, - { SYSZ_INS_CLGIJHE, "clgijhe" }, - { SYSZ_INS_CLGRJHE, "clgrjhe" }, - { SYSZ_INS_CLIJHE, "clijhe" }, - { SYSZ_INS_CLRJHE, "clrjhe" }, - { SYSZ_INS_CRJHE, "crjhe" }, - { SYSZ_INS_CGIJNHE, "cgijnhe" }, - { SYSZ_INS_CGRJNHE, "cgrjnhe" }, - { SYSZ_INS_CIJNHE, "cijnhe" }, - { SYSZ_INS_CLGIJNHE, "clgijnhe" }, - { SYSZ_INS_CLGRJNHE, "clgrjnhe" }, - { SYSZ_INS_CLIJNHE, "clijnhe" }, - { SYSZ_INS_CLRJNHE, "clrjnhe" }, - { SYSZ_INS_CRJNHE, "crjnhe" }, - { SYSZ_INS_CGIJL, "cgijl" }, - { SYSZ_INS_CGRJL, "cgrjl" }, - { SYSZ_INS_CIJL, "cijl" }, - { SYSZ_INS_CLGIJL, "clgijl" }, - { SYSZ_INS_CLGRJL, "clgrjl" }, - { SYSZ_INS_CLIJL, "clijl" }, - { SYSZ_INS_CLRJL, "clrjl" }, - { SYSZ_INS_CRJL, "crjl" }, - { SYSZ_INS_CGIJNH, "cgijnh" }, - { SYSZ_INS_CGRJNH, "cgrjnh" }, - { SYSZ_INS_CIJNH, "cijnh" }, - { SYSZ_INS_CLGIJNH, "clgijnh" }, - { SYSZ_INS_CLGRJNH, "clgrjnh" }, - { SYSZ_INS_CLIJNH, "clijnh" }, - { SYSZ_INS_CLRJNH, "clrjnh" }, - { SYSZ_INS_CRJNH, "crjnh" }, - { SYSZ_INS_CGIJLE, "cgijle" }, - { SYSZ_INS_CGRJLE, "cgrjle" }, - { SYSZ_INS_CIJLE, "cijle" }, - { SYSZ_INS_CLGIJLE, "clgijle" }, - { SYSZ_INS_CLGRJLE, "clgrjle" }, - { SYSZ_INS_CLIJLE, "clijle" }, - { SYSZ_INS_CLRJLE, "clrjle" }, - { SYSZ_INS_CRJLE, "crjle" }, - { SYSZ_INS_CGIJNE, "cgijne" }, - { SYSZ_INS_CGRJNE, "cgrjne" }, - { SYSZ_INS_CIJNE, "cijne" }, - { SYSZ_INS_CLGIJNE, "clgijne" }, - { SYSZ_INS_CLGRJNE, "clgrjne" }, - { SYSZ_INS_CLIJNE, "clijne" }, - { SYSZ_INS_CLRJNE, "clrjne" }, - { SYSZ_INS_CRJNE, "crjne" }, - { SYSZ_INS_CGIJLH, "cgijlh" }, - { SYSZ_INS_CGRJLH, "cgrjlh" }, - { SYSZ_INS_CIJLH, "cijlh" }, - { SYSZ_INS_CLGIJLH, "clgijlh" }, - { SYSZ_INS_CLGRJLH, "clgrjlh" }, - { SYSZ_INS_CLIJLH, "clijlh" }, - { SYSZ_INS_CLRJLH, "clrjlh" }, - { SYSZ_INS_CRJLH, "crjlh" }, - { SYSZ_INS_BLR, "blr" }, - { SYSZ_INS_BLER, "bler" }, - { SYSZ_INS_JLE, "jle" }, - { SYSZ_INS_JGLE, "jgle" }, - { SYSZ_INS_LOCLE, "locle" }, - { SYSZ_INS_LOCGLE, "locgle" }, - { SYSZ_INS_LOCGRLE, "locgrle" }, - { SYSZ_INS_LOCRLE, "locrle" }, - { SYSZ_INS_STOCLE, "stocle" }, - { SYSZ_INS_STOCGLE, "stocgle" }, - { SYSZ_INS_BLHR, "blhr" }, - { SYSZ_INS_JLH, "jlh" }, - { SYSZ_INS_JGLH, "jglh" }, - { SYSZ_INS_LOCLH, "loclh" }, - { SYSZ_INS_LOCGLH, "locglh" }, - { SYSZ_INS_LOCGRLH, "locgrlh" }, - { SYSZ_INS_LOCRLH, "locrlh" }, - { SYSZ_INS_STOCLH, "stoclh" }, - { SYSZ_INS_STOCGLH, "stocglh" }, - { SYSZ_INS_JL, "jl" }, - { SYSZ_INS_JGL, "jgl" }, - { SYSZ_INS_LOCL, "locl" }, - { SYSZ_INS_LOCGL, "locgl" }, - { SYSZ_INS_LOCGRL, "locgrl" }, - { SYSZ_INS_LOCRL, "locrl" }, - { SYSZ_INS_LOC, "loc" }, - { SYSZ_INS_LOCG, "locg" }, - { SYSZ_INS_LOCGR, "locgr" }, - { SYSZ_INS_LOCR, "locr" }, - { SYSZ_INS_STOCL, "stocl" }, - { SYSZ_INS_STOCGL, "stocgl" }, - { SYSZ_INS_BNER, "bner" }, - { SYSZ_INS_JNE, "jne" }, - { SYSZ_INS_JGNE, "jgne" }, - { SYSZ_INS_LOCNE, "locne" }, - { SYSZ_INS_LOCGNE, "locgne" }, - { SYSZ_INS_LOCGRNE, "locgrne" }, - { SYSZ_INS_LOCRNE, "locrne" }, - { SYSZ_INS_STOCNE, "stocne" }, - { SYSZ_INS_STOCGNE, "stocgne" }, - { SYSZ_INS_BNHR, "bnhr" }, - { SYSZ_INS_BNHER, "bnher" }, - { SYSZ_INS_JNHE, "jnhe" }, - { SYSZ_INS_JGNHE, "jgnhe" }, - { SYSZ_INS_LOCNHE, "locnhe" }, - { SYSZ_INS_LOCGNHE, "locgnhe" }, - { SYSZ_INS_LOCGRNHE, "locgrnhe" }, - { SYSZ_INS_LOCRNHE, "locrnhe" }, - { SYSZ_INS_STOCNHE, "stocnhe" }, - { SYSZ_INS_STOCGNHE, "stocgnhe" }, - { SYSZ_INS_JNH, "jnh" }, - { SYSZ_INS_JGNH, "jgnh" }, - { SYSZ_INS_LOCNH, "locnh" }, - { SYSZ_INS_LOCGNH, "locgnh" }, - { SYSZ_INS_LOCGRNH, "locgrnh" }, - { SYSZ_INS_LOCRNH, "locrnh" }, - { SYSZ_INS_STOCNH, "stocnh" }, - { SYSZ_INS_STOCGNH, "stocgnh" }, - { SYSZ_INS_BNLR, "bnlr" }, - { SYSZ_INS_BNLER, "bnler" }, - { SYSZ_INS_JNLE, "jnle" }, - { SYSZ_INS_JGNLE, "jgnle" }, - { SYSZ_INS_LOCNLE, "locnle" }, - { SYSZ_INS_LOCGNLE, "locgnle" }, - { SYSZ_INS_LOCGRNLE, "locgrnle" }, - { SYSZ_INS_LOCRNLE, "locrnle" }, - { SYSZ_INS_STOCNLE, "stocnle" }, - { SYSZ_INS_STOCGNLE, "stocgnle" }, - { SYSZ_INS_BNLHR, "bnlhr" }, - { SYSZ_INS_JNLH, "jnlh" }, - { SYSZ_INS_JGNLH, "jgnlh" }, - { SYSZ_INS_LOCNLH, "locnlh" }, - { SYSZ_INS_LOCGNLH, "locgnlh" }, - { SYSZ_INS_LOCGRNLH, "locgrnlh" }, - { SYSZ_INS_LOCRNLH, "locrnlh" }, - { SYSZ_INS_STOCNLH, "stocnlh" }, - { SYSZ_INS_STOCGNLH, "stocgnlh" }, - { SYSZ_INS_JNL, "jnl" }, - { SYSZ_INS_JGNL, "jgnl" }, - { SYSZ_INS_LOCNL, "locnl" }, - { SYSZ_INS_LOCGNL, "locgnl" }, - { SYSZ_INS_LOCGRNL, "locgrnl" }, - { SYSZ_INS_LOCRNL, "locrnl" }, - { SYSZ_INS_STOCNL, "stocnl" }, - { SYSZ_INS_STOCGNL, "stocgnl" }, - { SYSZ_INS_BNOR, "bnor" }, - { SYSZ_INS_JNO, "jno" }, - { SYSZ_INS_JGNO, "jgno" }, - { SYSZ_INS_LOCNO, "locno" }, - { SYSZ_INS_LOCGNO, "locgno" }, - { SYSZ_INS_LOCGRNO, "locgrno" }, - { SYSZ_INS_LOCRNO, "locrno" }, - { SYSZ_INS_STOCNO, "stocno" }, - { SYSZ_INS_STOCGNO, "stocgno" }, - { SYSZ_INS_BOR, "bor" }, - { SYSZ_INS_JO, "jo" }, - { SYSZ_INS_JGO, "jgo" }, - { SYSZ_INS_LOCO, "loco" }, - { SYSZ_INS_LOCGO, "locgo" }, - { SYSZ_INS_LOCGRO, "locgro" }, - { SYSZ_INS_LOCRO, "locro" }, - { SYSZ_INS_STOCO, "stoco" }, - { SYSZ_INS_STOCGO, "stocgo" }, - { SYSZ_INS_STOC, "stoc" }, - { SYSZ_INS_STOCG, "stocg" }, - { SYSZ_INS_BASR, "basr" }, - { SYSZ_INS_BR, "br" }, - { SYSZ_INS_BRAS, "bras" }, - { SYSZ_INS_BRASL, "brasl" }, - { SYSZ_INS_J, "j" }, - { SYSZ_INS_JG, "jg" }, - { SYSZ_INS_BRCT, "brct" }, - { SYSZ_INS_BRCTG, "brctg" }, - { SYSZ_INS_C, "c" }, - { SYSZ_INS_CDB, "cdb" }, - { SYSZ_INS_CDBR, "cdbr" }, - { SYSZ_INS_CDFBR, "cdfbr" }, - { SYSZ_INS_CDGBR, "cdgbr" }, - { SYSZ_INS_CDLFBR, "cdlfbr" }, - { SYSZ_INS_CDLGBR, "cdlgbr" }, - { SYSZ_INS_CEB, "ceb" }, - { SYSZ_INS_CEBR, "cebr" }, - { SYSZ_INS_CEFBR, "cefbr" }, - { SYSZ_INS_CEGBR, "cegbr" }, - { SYSZ_INS_CELFBR, "celfbr" }, - { SYSZ_INS_CELGBR, "celgbr" }, - { SYSZ_INS_CFDBR, "cfdbr" }, - { SYSZ_INS_CFEBR, "cfebr" }, - { SYSZ_INS_CFI, "cfi" }, - { SYSZ_INS_CFXBR, "cfxbr" }, - { SYSZ_INS_CG, "cg" }, - { SYSZ_INS_CGDBR, "cgdbr" }, - { SYSZ_INS_CGEBR, "cgebr" }, - { SYSZ_INS_CGF, "cgf" }, - { SYSZ_INS_CGFI, "cgfi" }, - { SYSZ_INS_CGFR, "cgfr" }, - { SYSZ_INS_CGFRL, "cgfrl" }, - { SYSZ_INS_CGH, "cgh" }, - { SYSZ_INS_CGHI, "cghi" }, - { SYSZ_INS_CGHRL, "cghrl" }, - { SYSZ_INS_CGHSI, "cghsi" }, - { SYSZ_INS_CGR, "cgr" }, - { SYSZ_INS_CGRL, "cgrl" }, - { SYSZ_INS_CGXBR, "cgxbr" }, - { SYSZ_INS_CH, "ch" }, - { SYSZ_INS_CHF, "chf" }, - { SYSZ_INS_CHHSI, "chhsi" }, - { SYSZ_INS_CHI, "chi" }, - { SYSZ_INS_CHRL, "chrl" }, - { SYSZ_INS_CHSI, "chsi" }, - { SYSZ_INS_CHY, "chy" }, - { SYSZ_INS_CIH, "cih" }, - { SYSZ_INS_CL, "cl" }, - { SYSZ_INS_CLC, "clc" }, - { SYSZ_INS_CLFDBR, "clfdbr" }, - { SYSZ_INS_CLFEBR, "clfebr" }, - { SYSZ_INS_CLFHSI, "clfhsi" }, - { SYSZ_INS_CLFI, "clfi" }, - { SYSZ_INS_CLFXBR, "clfxbr" }, - { SYSZ_INS_CLG, "clg" }, - { SYSZ_INS_CLGDBR, "clgdbr" }, - { SYSZ_INS_CLGEBR, "clgebr" }, - { SYSZ_INS_CLGF, "clgf" }, - { SYSZ_INS_CLGFI, "clgfi" }, - { SYSZ_INS_CLGFR, "clgfr" }, - { SYSZ_INS_CLGFRL, "clgfrl" }, - { SYSZ_INS_CLGHRL, "clghrl" }, - { SYSZ_INS_CLGHSI, "clghsi" }, - { SYSZ_INS_CLGR, "clgr" }, - { SYSZ_INS_CLGRL, "clgrl" }, - { SYSZ_INS_CLGXBR, "clgxbr" }, - { SYSZ_INS_CLHF, "clhf" }, - { SYSZ_INS_CLHHSI, "clhhsi" }, - { SYSZ_INS_CLHRL, "clhrl" }, - { SYSZ_INS_CLI, "cli" }, - { SYSZ_INS_CLIH, "clih" }, - { SYSZ_INS_CLIY, "cliy" }, - { SYSZ_INS_CLR, "clr" }, - { SYSZ_INS_CLRL, "clrl" }, - { SYSZ_INS_CLST, "clst" }, - { SYSZ_INS_CLY, "cly" }, - { SYSZ_INS_CPSDR, "cpsdr" }, - { SYSZ_INS_CR, "cr" }, - { SYSZ_INS_CRL, "crl" }, - { SYSZ_INS_CS, "cs" }, - { SYSZ_INS_CSG, "csg" }, - { SYSZ_INS_CSY, "csy" }, - { SYSZ_INS_CXBR, "cxbr" }, - { SYSZ_INS_CXFBR, "cxfbr" }, - { SYSZ_INS_CXGBR, "cxgbr" }, - { SYSZ_INS_CXLFBR, "cxlfbr" }, - { SYSZ_INS_CXLGBR, "cxlgbr" }, - { SYSZ_INS_CY, "cy" }, - { SYSZ_INS_DDB, "ddb" }, - { SYSZ_INS_DDBR, "ddbr" }, - { SYSZ_INS_DEB, "deb" }, - { SYSZ_INS_DEBR, "debr" }, - { SYSZ_INS_DL, "dl" }, - { SYSZ_INS_DLG, "dlg" }, - { SYSZ_INS_DLGR, "dlgr" }, - { SYSZ_INS_DLR, "dlr" }, - { SYSZ_INS_DSG, "dsg" }, - { SYSZ_INS_DSGF, "dsgf" }, - { SYSZ_INS_DSGFR, "dsgfr" }, - { SYSZ_INS_DSGR, "dsgr" }, - { SYSZ_INS_DXBR, "dxbr" }, - { SYSZ_INS_EAR, "ear" }, - { SYSZ_INS_FIDBR, "fidbr" }, - { SYSZ_INS_FIDBRA, "fidbra" }, - { SYSZ_INS_FIEBR, "fiebr" }, - { SYSZ_INS_FIEBRA, "fiebra" }, - { SYSZ_INS_FIXBR, "fixbr" }, - { SYSZ_INS_FIXBRA, "fixbra" }, - { SYSZ_INS_FLOGR, "flogr" }, - { SYSZ_INS_IC, "ic" }, - { SYSZ_INS_ICY, "icy" }, - { SYSZ_INS_IIHF, "iihf" }, - { SYSZ_INS_IIHH, "iihh" }, - { SYSZ_INS_IIHL, "iihl" }, - { SYSZ_INS_IILF, "iilf" }, - { SYSZ_INS_IILH, "iilh" }, - { SYSZ_INS_IILL, "iill" }, - { SYSZ_INS_IPM, "ipm" }, - { SYSZ_INS_L, "l" }, - { SYSZ_INS_LA, "la" }, - { SYSZ_INS_LAA, "laa" }, - { SYSZ_INS_LAAG, "laag" }, - { SYSZ_INS_LAAL, "laal" }, - { SYSZ_INS_LAALG, "laalg" }, - { SYSZ_INS_LAN, "lan" }, - { SYSZ_INS_LANG, "lang" }, - { SYSZ_INS_LAO, "lao" }, - { SYSZ_INS_LAOG, "laog" }, - { SYSZ_INS_LARL, "larl" }, - { SYSZ_INS_LAX, "lax" }, - { SYSZ_INS_LAXG, "laxg" }, - { SYSZ_INS_LAY, "lay" }, - { SYSZ_INS_LB, "lb" }, - { SYSZ_INS_LBH, "lbh" }, - { SYSZ_INS_LBR, "lbr" }, - { SYSZ_INS_LCDBR, "lcdbr" }, - { SYSZ_INS_LCEBR, "lcebr" }, - { SYSZ_INS_LCGFR, "lcgfr" }, - { SYSZ_INS_LCGR, "lcgr" }, - { SYSZ_INS_LCR, "lcr" }, - { SYSZ_INS_LCXBR, "lcxbr" }, - { SYSZ_INS_LD, "ld" }, - { SYSZ_INS_LDEB, "ldeb" }, - { SYSZ_INS_LDEBR, "ldebr" }, - { SYSZ_INS_LDGR, "ldgr" }, - { SYSZ_INS_LDR, "ldr" }, - { SYSZ_INS_LDXBR, "ldxbr" }, - { SYSZ_INS_LDXBRA, "ldxbra" }, - { SYSZ_INS_LDY, "ldy" }, - { SYSZ_INS_LE, "le" }, - { SYSZ_INS_LEDBR, "ledbr" }, - { SYSZ_INS_LEDBRA, "ledbra" }, - { SYSZ_INS_LER, "ler" }, - { SYSZ_INS_LEXBR, "lexbr" }, - { SYSZ_INS_LEXBRA, "lexbra" }, - { SYSZ_INS_LEY, "ley" }, - { SYSZ_INS_LFH, "lfh" }, - { SYSZ_INS_LG, "lg" }, - { SYSZ_INS_LGB, "lgb" }, - { SYSZ_INS_LGBR, "lgbr" }, - { SYSZ_INS_LGDR, "lgdr" }, - { SYSZ_INS_LGF, "lgf" }, - { SYSZ_INS_LGFI, "lgfi" }, - { SYSZ_INS_LGFR, "lgfr" }, - { SYSZ_INS_LGFRL, "lgfrl" }, - { SYSZ_INS_LGH, "lgh" }, - { SYSZ_INS_LGHI, "lghi" }, - { SYSZ_INS_LGHR, "lghr" }, - { SYSZ_INS_LGHRL, "lghrl" }, - { SYSZ_INS_LGR, "lgr" }, - { SYSZ_INS_LGRL, "lgrl" }, - { SYSZ_INS_LH, "lh" }, - { SYSZ_INS_LHH, "lhh" }, - { SYSZ_INS_LHI, "lhi" }, - { SYSZ_INS_LHR, "lhr" }, - { SYSZ_INS_LHRL, "lhrl" }, - { SYSZ_INS_LHY, "lhy" }, - { SYSZ_INS_LLC, "llc" }, - { SYSZ_INS_LLCH, "llch" }, - { SYSZ_INS_LLCR, "llcr" }, - { SYSZ_INS_LLGC, "llgc" }, - { SYSZ_INS_LLGCR, "llgcr" }, - { SYSZ_INS_LLGF, "llgf" }, - { SYSZ_INS_LLGFR, "llgfr" }, - { SYSZ_INS_LLGFRL, "llgfrl" }, - { SYSZ_INS_LLGH, "llgh" }, - { SYSZ_INS_LLGHR, "llghr" }, - { SYSZ_INS_LLGHRL, "llghrl" }, - { SYSZ_INS_LLH, "llh" }, - { SYSZ_INS_LLHH, "llhh" }, - { SYSZ_INS_LLHR, "llhr" }, - { SYSZ_INS_LLHRL, "llhrl" }, - { SYSZ_INS_LLIHF, "llihf" }, - { SYSZ_INS_LLIHH, "llihh" }, - { SYSZ_INS_LLIHL, "llihl" }, - { SYSZ_INS_LLILF, "llilf" }, - { SYSZ_INS_LLILH, "llilh" }, - { SYSZ_INS_LLILL, "llill" }, - { SYSZ_INS_LMG, "lmg" }, - { SYSZ_INS_LNDBR, "lndbr" }, - { SYSZ_INS_LNEBR, "lnebr" }, - { SYSZ_INS_LNGFR, "lngfr" }, - { SYSZ_INS_LNGR, "lngr" }, - { SYSZ_INS_LNR, "lnr" }, - { SYSZ_INS_LNXBR, "lnxbr" }, - { SYSZ_INS_LPDBR, "lpdbr" }, - { SYSZ_INS_LPEBR, "lpebr" }, - { SYSZ_INS_LPGFR, "lpgfr" }, - { SYSZ_INS_LPGR, "lpgr" }, - { SYSZ_INS_LPR, "lpr" }, - { SYSZ_INS_LPXBR, "lpxbr" }, - { SYSZ_INS_LR, "lr" }, - { SYSZ_INS_LRL, "lrl" }, - { SYSZ_INS_LRV, "lrv" }, - { SYSZ_INS_LRVG, "lrvg" }, - { SYSZ_INS_LRVGR, "lrvgr" }, - { SYSZ_INS_LRVR, "lrvr" }, - { SYSZ_INS_LT, "lt" }, - { SYSZ_INS_LTDBR, "ltdbr" }, - { SYSZ_INS_LTEBR, "ltebr" }, - { SYSZ_INS_LTG, "ltg" }, - { SYSZ_INS_LTGF, "ltgf" }, - { SYSZ_INS_LTGFR, "ltgfr" }, - { SYSZ_INS_LTGR, "ltgr" }, - { SYSZ_INS_LTR, "ltr" }, - { SYSZ_INS_LTXBR, "ltxbr" }, - { SYSZ_INS_LXDB, "lxdb" }, - { SYSZ_INS_LXDBR, "lxdbr" }, - { SYSZ_INS_LXEB, "lxeb" }, - { SYSZ_INS_LXEBR, "lxebr" }, - { SYSZ_INS_LXR, "lxr" }, - { SYSZ_INS_LY, "ly" }, - { SYSZ_INS_LZDR, "lzdr" }, - { SYSZ_INS_LZER, "lzer" }, - { SYSZ_INS_LZXR, "lzxr" }, - { SYSZ_INS_MADB, "madb" }, - { SYSZ_INS_MADBR, "madbr" }, - { SYSZ_INS_MAEB, "maeb" }, - { SYSZ_INS_MAEBR, "maebr" }, - { SYSZ_INS_MDB, "mdb" }, - { SYSZ_INS_MDBR, "mdbr" }, - { SYSZ_INS_MDEB, "mdeb" }, - { SYSZ_INS_MDEBR, "mdebr" }, - { SYSZ_INS_MEEB, "meeb" }, - { SYSZ_INS_MEEBR, "meebr" }, - { SYSZ_INS_MGHI, "mghi" }, - { SYSZ_INS_MH, "mh" }, - { SYSZ_INS_MHI, "mhi" }, - { SYSZ_INS_MHY, "mhy" }, - { SYSZ_INS_MLG, "mlg" }, - { SYSZ_INS_MLGR, "mlgr" }, - { SYSZ_INS_MS, "ms" }, - { SYSZ_INS_MSDB, "msdb" }, - { SYSZ_INS_MSDBR, "msdbr" }, - { SYSZ_INS_MSEB, "mseb" }, - { SYSZ_INS_MSEBR, "msebr" }, - { SYSZ_INS_MSFI, "msfi" }, - { SYSZ_INS_MSG, "msg" }, - { SYSZ_INS_MSGF, "msgf" }, - { SYSZ_INS_MSGFI, "msgfi" }, - { SYSZ_INS_MSGFR, "msgfr" }, - { SYSZ_INS_MSGR, "msgr" }, - { SYSZ_INS_MSR, "msr" }, - { SYSZ_INS_MSY, "msy" }, - { SYSZ_INS_MVC, "mvc" }, - { SYSZ_INS_MVGHI, "mvghi" }, - { SYSZ_INS_MVHHI, "mvhhi" }, - { SYSZ_INS_MVHI, "mvhi" }, - { SYSZ_INS_MVI, "mvi" }, - { SYSZ_INS_MVIY, "mviy" }, - { SYSZ_INS_MVST, "mvst" }, - { SYSZ_INS_MXBR, "mxbr" }, - { SYSZ_INS_MXDB, "mxdb" }, - { SYSZ_INS_MXDBR, "mxdbr" }, - { SYSZ_INS_N, "n" }, - { SYSZ_INS_NC, "nc" }, - { SYSZ_INS_NG, "ng" }, - { SYSZ_INS_NGR, "ngr" }, - { SYSZ_INS_NGRK, "ngrk" }, - { SYSZ_INS_NI, "ni" }, - { SYSZ_INS_NIHF, "nihf" }, - { SYSZ_INS_NIHH, "nihh" }, - { SYSZ_INS_NIHL, "nihl" }, - { SYSZ_INS_NILF, "nilf" }, - { SYSZ_INS_NILH, "nilh" }, - { SYSZ_INS_NILL, "nill" }, - { SYSZ_INS_NIY, "niy" }, - { SYSZ_INS_NR, "nr" }, - { SYSZ_INS_NRK, "nrk" }, - { SYSZ_INS_NY, "ny" }, - { SYSZ_INS_O, "o" }, - { SYSZ_INS_OC, "oc" }, - { SYSZ_INS_OG, "og" }, - { SYSZ_INS_OGR, "ogr" }, - { SYSZ_INS_OGRK, "ogrk" }, - { SYSZ_INS_OI, "oi" }, - { SYSZ_INS_OIHF, "oihf" }, - { SYSZ_INS_OIHH, "oihh" }, - { SYSZ_INS_OIHL, "oihl" }, - { SYSZ_INS_OILF, "oilf" }, - { SYSZ_INS_OILH, "oilh" }, - { SYSZ_INS_OILL, "oill" }, - { SYSZ_INS_OIY, "oiy" }, - { SYSZ_INS_OR, "or" }, - { SYSZ_INS_ORK, "ork" }, - { SYSZ_INS_OY, "oy" }, - { SYSZ_INS_PFD, "pfd" }, - { SYSZ_INS_PFDRL, "pfdrl" }, - { SYSZ_INS_RISBG, "risbg" }, - { SYSZ_INS_RISBHG, "risbhg" }, - { SYSZ_INS_RISBLG, "risblg" }, - { SYSZ_INS_RLL, "rll" }, - { SYSZ_INS_RLLG, "rllg" }, - { SYSZ_INS_RNSBG, "rnsbg" }, - { SYSZ_INS_ROSBG, "rosbg" }, - { SYSZ_INS_RXSBG, "rxsbg" }, - { SYSZ_INS_S, "s" }, - { SYSZ_INS_SDB, "sdb" }, - { SYSZ_INS_SDBR, "sdbr" }, - { SYSZ_INS_SEB, "seb" }, - { SYSZ_INS_SEBR, "sebr" }, - { SYSZ_INS_SG, "sg" }, - { SYSZ_INS_SGF, "sgf" }, - { SYSZ_INS_SGFR, "sgfr" }, - { SYSZ_INS_SGR, "sgr" }, - { SYSZ_INS_SGRK, "sgrk" }, - { SYSZ_INS_SH, "sh" }, - { SYSZ_INS_SHY, "shy" }, - { SYSZ_INS_SL, "sl" }, - { SYSZ_INS_SLB, "slb" }, - { SYSZ_INS_SLBG, "slbg" }, - { SYSZ_INS_SLBR, "slbr" }, - { SYSZ_INS_SLFI, "slfi" }, - { SYSZ_INS_SLG, "slg" }, - { SYSZ_INS_SLBGR, "slbgr" }, - { SYSZ_INS_SLGF, "slgf" }, - { SYSZ_INS_SLGFI, "slgfi" }, - { SYSZ_INS_SLGFR, "slgfr" }, - { SYSZ_INS_SLGR, "slgr" }, - { SYSZ_INS_SLGRK, "slgrk" }, - { SYSZ_INS_SLL, "sll" }, - { SYSZ_INS_SLLG, "sllg" }, - { SYSZ_INS_SLLK, "sllk" }, - { SYSZ_INS_SLR, "slr" }, - { SYSZ_INS_SLRK, "slrk" }, - { SYSZ_INS_SLY, "sly" }, - { SYSZ_INS_SQDB, "sqdb" }, - { SYSZ_INS_SQDBR, "sqdbr" }, - { SYSZ_INS_SQEB, "sqeb" }, - { SYSZ_INS_SQEBR, "sqebr" }, - { SYSZ_INS_SQXBR, "sqxbr" }, - { SYSZ_INS_SR, "sr" }, - { SYSZ_INS_SRA, "sra" }, - { SYSZ_INS_SRAG, "srag" }, - { SYSZ_INS_SRAK, "srak" }, - { SYSZ_INS_SRK, "srk" }, - { SYSZ_INS_SRL, "srl" }, - { SYSZ_INS_SRLG, "srlg" }, - { SYSZ_INS_SRLK, "srlk" }, - { SYSZ_INS_SRST, "srst" }, - { SYSZ_INS_ST, "st" }, - { SYSZ_INS_STC, "stc" }, - { SYSZ_INS_STCH, "stch" }, - { SYSZ_INS_STCY, "stcy" }, - { SYSZ_INS_STD, "std" }, - { SYSZ_INS_STDY, "stdy" }, - { SYSZ_INS_STE, "ste" }, - { SYSZ_INS_STEY, "stey" }, - { SYSZ_INS_STFH, "stfh" }, - { SYSZ_INS_STG, "stg" }, - { SYSZ_INS_STGRL, "stgrl" }, - { SYSZ_INS_STH, "sth" }, - { SYSZ_INS_STHH, "sthh" }, - { SYSZ_INS_STHRL, "sthrl" }, - { SYSZ_INS_STHY, "sthy" }, - { SYSZ_INS_STMG, "stmg" }, - { SYSZ_INS_STRL, "strl" }, - { SYSZ_INS_STRV, "strv" }, - { SYSZ_INS_STRVG, "strvg" }, - { SYSZ_INS_STY, "sty" }, - { SYSZ_INS_SXBR, "sxbr" }, - { SYSZ_INS_SY, "sy" }, - { SYSZ_INS_TM, "tm" }, - { SYSZ_INS_TMHH, "tmhh" }, - { SYSZ_INS_TMHL, "tmhl" }, - { SYSZ_INS_TMLH, "tmlh" }, - { SYSZ_INS_TMLL, "tmll" }, - { SYSZ_INS_TMY, "tmy" }, - { SYSZ_INS_X, "x" }, - { SYSZ_INS_XC, "xc" }, - { SYSZ_INS_XG, "xg" }, - { SYSZ_INS_XGR, "xgr" }, - { SYSZ_INS_XGRK, "xgrk" }, - { SYSZ_INS_XI, "xi" }, - { SYSZ_INS_XIHF, "xihf" }, - { SYSZ_INS_XILF, "xilf" }, - { SYSZ_INS_XIY, "xiy" }, - { SYSZ_INS_XR, "xr" }, - { SYSZ_INS_XRK, "xrk" }, - { SYSZ_INS_XY, "xy" }, - { SYSZ_INS_AD, "ad" }, - { SYSZ_INS_ADR, "adr" }, - { SYSZ_INS_ADTR, "adtr" }, - { SYSZ_INS_ADTRA, "adtra" }, - { SYSZ_INS_AE, "ae" }, - { SYSZ_INS_AER, "aer" }, - { SYSZ_INS_AGH, "agh" }, - { SYSZ_INS_AHHHR, "ahhhr" }, - { SYSZ_INS_AHHLR, "ahhlr" }, - { SYSZ_INS_ALGSI, "algsi" }, - { SYSZ_INS_ALHHHR, "alhhhr" }, - { SYSZ_INS_ALHHLR, "alhhlr" }, - { SYSZ_INS_ALSI, "alsi" }, - { SYSZ_INS_ALSIH, "alsih" }, - { SYSZ_INS_ALSIHN, "alsihn" }, - { SYSZ_INS_AP, "ap" }, - { SYSZ_INS_AU, "au" }, - { SYSZ_INS_AUR, "aur" }, - { SYSZ_INS_AW, "aw" }, - { SYSZ_INS_AWR, "awr" }, - { SYSZ_INS_AXR, "axr" }, - { SYSZ_INS_AXTR, "axtr" }, - { SYSZ_INS_AXTRA, "axtra" }, - { SYSZ_INS_B, "b" }, - { SYSZ_INS_BAKR, "bakr" }, - { SYSZ_INS_BAL, "bal" }, - { SYSZ_INS_BALR, "balr" }, - { SYSZ_INS_BAS, "bas" }, - { SYSZ_INS_BASSM, "bassm" }, - { SYSZ_INS_BC, "bc" }, - { SYSZ_INS_BCT, "bct" }, - { SYSZ_INS_BCTG, "bctg" }, - { SYSZ_INS_BCTGR, "bctgr" }, - { SYSZ_INS_BCTR, "bctr" }, - { SYSZ_INS_BE, "be" }, - { SYSZ_INS_BH, "bh" }, - { SYSZ_INS_BHE, "bhe" }, - { SYSZ_INS_BI, "bi" }, - { SYSZ_INS_BIC, "bic" }, - { SYSZ_INS_BIE, "bie" }, - { SYSZ_INS_BIH, "bih" }, - { SYSZ_INS_BIHE, "bihe" }, - { SYSZ_INS_BIL, "bil" }, - { SYSZ_INS_BILE, "bile" }, - { SYSZ_INS_BILH, "bilh" }, - { SYSZ_INS_BIM, "bim" }, - { SYSZ_INS_BINE, "bine" }, - { SYSZ_INS_BINH, "binh" }, - { SYSZ_INS_BINHE, "binhe" }, - { SYSZ_INS_BINL, "binl" }, - { SYSZ_INS_BINLE, "binle" }, - { SYSZ_INS_BINLH, "binlh" }, - { SYSZ_INS_BINM, "binm" }, - { SYSZ_INS_BINO, "bino" }, - { SYSZ_INS_BINP, "binp" }, - { SYSZ_INS_BINZ, "binz" }, - { SYSZ_INS_BIO, "bio" }, - { SYSZ_INS_BIP, "bip" }, - { SYSZ_INS_BIZ, "biz" }, - { SYSZ_INS_BL, "bl" }, - { SYSZ_INS_BLE, "ble" }, - { SYSZ_INS_BLH, "blh" }, - { SYSZ_INS_BM, "bm" }, - { SYSZ_INS_BMR, "bmr" }, - { SYSZ_INS_BNE, "bne" }, - { SYSZ_INS_BNH, "bnh" }, - { SYSZ_INS_BNHE, "bnhe" }, - { SYSZ_INS_BNL, "bnl" }, - { SYSZ_INS_BNLE, "bnle" }, - { SYSZ_INS_BNLH, "bnlh" }, - { SYSZ_INS_BNM, "bnm" }, - { SYSZ_INS_BNMR, "bnmr" }, - { SYSZ_INS_BNO, "bno" }, - { SYSZ_INS_BNP, "bnp" }, - { SYSZ_INS_BNPR, "bnpr" }, - { SYSZ_INS_BNZ, "bnz" }, - { SYSZ_INS_BNZR, "bnzr" }, - { SYSZ_INS_BO, "bo" }, - { SYSZ_INS_BP, "bp" }, - { SYSZ_INS_BPP, "bpp" }, - { SYSZ_INS_BPR, "bpr" }, - { SYSZ_INS_BPRP, "bprp" }, - { SYSZ_INS_BRCTH, "brcth" }, - { SYSZ_INS_BRXH, "brxh" }, - { SYSZ_INS_BRXHG, "brxhg" }, - { SYSZ_INS_BRXLE, "brxle" }, - { SYSZ_INS_BRXLG, "brxlg" }, - { SYSZ_INS_BSA, "bsa" }, - { SYSZ_INS_BSG, "bsg" }, - { SYSZ_INS_BSM, "bsm" }, - { SYSZ_INS_BXH, "bxh" }, - { SYSZ_INS_BXHG, "bxhg" }, - { SYSZ_INS_BXLE, "bxle" }, - { SYSZ_INS_BXLEG, "bxleg" }, - { SYSZ_INS_BZ, "bz" }, - { SYSZ_INS_BZR, "bzr" }, - { SYSZ_INS_CD, "cd" }, - { SYSZ_INS_CDFBRA, "cdfbra" }, - { SYSZ_INS_CDFR, "cdfr" }, - { SYSZ_INS_CDFTR, "cdftr" }, - { SYSZ_INS_CDGBRA, "cdgbra" }, - { SYSZ_INS_CDGR, "cdgr" }, - { SYSZ_INS_CDGTR, "cdgtr" }, - { SYSZ_INS_CDGTRA, "cdgtra" }, - { SYSZ_INS_CDLFTR, "cdlftr" }, - { SYSZ_INS_CDLGTR, "cdlgtr" }, - { SYSZ_INS_CDPT, "cdpt" }, - { SYSZ_INS_CDR, "cdr" }, - { SYSZ_INS_CDS, "cds" }, - { SYSZ_INS_CDSG, "cdsg" }, - { SYSZ_INS_CDSTR, "cdstr" }, - { SYSZ_INS_CDSY, "cdsy" }, - { SYSZ_INS_CDTR, "cdtr" }, - { SYSZ_INS_CDUTR, "cdutr" }, - { SYSZ_INS_CDZT, "cdzt" }, - { SYSZ_INS_CE, "ce" }, - { SYSZ_INS_CEDTR, "cedtr" }, - { SYSZ_INS_CEFBRA, "cefbra" }, - { SYSZ_INS_CEFR, "cefr" }, - { SYSZ_INS_CEGBRA, "cegbra" }, - { SYSZ_INS_CEGR, "cegr" }, - { SYSZ_INS_CER, "cer" }, - { SYSZ_INS_CEXTR, "cextr" }, - { SYSZ_INS_CFC, "cfc" }, - { SYSZ_INS_CFDBRA, "cfdbra" }, - { SYSZ_INS_CFDR, "cfdr" }, - { SYSZ_INS_CFDTR, "cfdtr" }, - { SYSZ_INS_CFEBRA, "cfebra" }, - { SYSZ_INS_CFER, "cfer" }, - { SYSZ_INS_CFXBRA, "cfxbra" }, - { SYSZ_INS_CFXR, "cfxr" }, - { SYSZ_INS_CFXTR, "cfxtr" }, - { SYSZ_INS_CGDBRA, "cgdbra" }, - { SYSZ_INS_CGDR, "cgdr" }, - { SYSZ_INS_CGDTR, "cgdtr" }, - { SYSZ_INS_CGDTRA, "cgdtra" }, - { SYSZ_INS_CGEBRA, "cgebra" }, - { SYSZ_INS_CGER, "cger" }, - { SYSZ_INS_CGIB, "cgib" }, - { SYSZ_INS_CGIBE, "cgibe" }, - { SYSZ_INS_CGIBH, "cgibh" }, - { SYSZ_INS_CGIBHE, "cgibhe" }, - { SYSZ_INS_CGIBL, "cgibl" }, - { SYSZ_INS_CGIBLE, "cgible" }, - { SYSZ_INS_CGIBLH, "cgiblh" }, - { SYSZ_INS_CGIBNE, "cgibne" }, - { SYSZ_INS_CGIBNH, "cgibnh" }, - { SYSZ_INS_CGIBNHE, "cgibnhe" }, - { SYSZ_INS_CGIBNL, "cgibnl" }, - { SYSZ_INS_CGIBNLE, "cgibnle" }, - { SYSZ_INS_CGIBNLH, "cgibnlh" }, - { SYSZ_INS_CGIT, "cgit" }, - { SYSZ_INS_CGITE, "cgite" }, - { SYSZ_INS_CGITH, "cgith" }, - { SYSZ_INS_CGITHE, "cgithe" }, - { SYSZ_INS_CGITL, "cgitl" }, - { SYSZ_INS_CGITLE, "cgitle" }, - { SYSZ_INS_CGITLH, "cgitlh" }, - { SYSZ_INS_CGITNE, "cgitne" }, - { SYSZ_INS_CGITNH, "cgitnh" }, - { SYSZ_INS_CGITNHE, "cgitnhe" }, - { SYSZ_INS_CGITNL, "cgitnl" }, - { SYSZ_INS_CGITNLE, "cgitnle" }, - { SYSZ_INS_CGITNLH, "cgitnlh" }, - { SYSZ_INS_CGRB, "cgrb" }, - { SYSZ_INS_CGRBE, "cgrbe" }, - { SYSZ_INS_CGRBH, "cgrbh" }, - { SYSZ_INS_CGRBHE, "cgrbhe" }, - { SYSZ_INS_CGRBL, "cgrbl" }, - { SYSZ_INS_CGRBLE, "cgrble" }, - { SYSZ_INS_CGRBLH, "cgrblh" }, - { SYSZ_INS_CGRBNE, "cgrbne" }, - { SYSZ_INS_CGRBNH, "cgrbnh" }, - { SYSZ_INS_CGRBNHE, "cgrbnhe" }, - { SYSZ_INS_CGRBNL, "cgrbnl" }, - { SYSZ_INS_CGRBNLE, "cgrbnle" }, - { SYSZ_INS_CGRBNLH, "cgrbnlh" }, - { SYSZ_INS_CGRT, "cgrt" }, - { SYSZ_INS_CGRTE, "cgrte" }, - { SYSZ_INS_CGRTH, "cgrth" }, - { SYSZ_INS_CGRTHE, "cgrthe" }, - { SYSZ_INS_CGRTL, "cgrtl" }, - { SYSZ_INS_CGRTLE, "cgrtle" }, - { SYSZ_INS_CGRTLH, "cgrtlh" }, - { SYSZ_INS_CGRTNE, "cgrtne" }, - { SYSZ_INS_CGRTNH, "cgrtnh" }, - { SYSZ_INS_CGRTNHE, "cgrtnhe" }, - { SYSZ_INS_CGRTNL, "cgrtnl" }, - { SYSZ_INS_CGRTNLE, "cgrtnle" }, - { SYSZ_INS_CGRTNLH, "cgrtnlh" }, - { SYSZ_INS_CGXBRA, "cgxbra" }, - { SYSZ_INS_CGXR, "cgxr" }, - { SYSZ_INS_CGXTR, "cgxtr" }, - { SYSZ_INS_CGXTRA, "cgxtra" }, - { SYSZ_INS_CHHR, "chhr" }, - { SYSZ_INS_CHLR, "chlr" }, - { SYSZ_INS_CIB, "cib" }, - { SYSZ_INS_CIBE, "cibe" }, - { SYSZ_INS_CIBH, "cibh" }, - { SYSZ_INS_CIBHE, "cibhe" }, - { SYSZ_INS_CIBL, "cibl" }, - { SYSZ_INS_CIBLE, "cible" }, - { SYSZ_INS_CIBLH, "ciblh" }, - { SYSZ_INS_CIBNE, "cibne" }, - { SYSZ_INS_CIBNH, "cibnh" }, - { SYSZ_INS_CIBNHE, "cibnhe" }, - { SYSZ_INS_CIBNL, "cibnl" }, - { SYSZ_INS_CIBNLE, "cibnle" }, - { SYSZ_INS_CIBNLH, "cibnlh" }, - { SYSZ_INS_CIT, "cit" }, - { SYSZ_INS_CITE, "cite" }, - { SYSZ_INS_CITH, "cith" }, - { SYSZ_INS_CITHE, "cithe" }, - { SYSZ_INS_CITL, "citl" }, - { SYSZ_INS_CITLE, "citle" }, - { SYSZ_INS_CITLH, "citlh" }, - { SYSZ_INS_CITNE, "citne" }, - { SYSZ_INS_CITNH, "citnh" }, - { SYSZ_INS_CITNHE, "citnhe" }, - { SYSZ_INS_CITNL, "citnl" }, - { SYSZ_INS_CITNLE, "citnle" }, - { SYSZ_INS_CITNLH, "citnlh" }, - { SYSZ_INS_CKSM, "cksm" }, - { SYSZ_INS_CLCL, "clcl" }, - { SYSZ_INS_CLCLE, "clcle" }, - { SYSZ_INS_CLCLU, "clclu" }, - { SYSZ_INS_CLFDTR, "clfdtr" }, - { SYSZ_INS_CLFIT, "clfit" }, - { SYSZ_INS_CLFITE, "clfite" }, - { SYSZ_INS_CLFITH, "clfith" }, - { SYSZ_INS_CLFITHE, "clfithe" }, - { SYSZ_INS_CLFITL, "clfitl" }, - { SYSZ_INS_CLFITLE, "clfitle" }, - { SYSZ_INS_CLFITLH, "clfitlh" }, - { SYSZ_INS_CLFITNE, "clfitne" }, - { SYSZ_INS_CLFITNH, "clfitnh" }, - { SYSZ_INS_CLFITNHE, "clfitnhe" }, - { SYSZ_INS_CLFITNL, "clfitnl" }, - { SYSZ_INS_CLFITNLE, "clfitnle" }, - { SYSZ_INS_CLFITNLH, "clfitnlh" }, - { SYSZ_INS_CLFXTR, "clfxtr" }, - { SYSZ_INS_CLGDTR, "clgdtr" }, - { SYSZ_INS_CLGIB, "clgib" }, - { SYSZ_INS_CLGIBE, "clgibe" }, - { SYSZ_INS_CLGIBH, "clgibh" }, - { SYSZ_INS_CLGIBHE, "clgibhe" }, - { SYSZ_INS_CLGIBL, "clgibl" }, - { SYSZ_INS_CLGIBLE, "clgible" }, - { SYSZ_INS_CLGIBLH, "clgiblh" }, - { SYSZ_INS_CLGIBNE, "clgibne" }, - { SYSZ_INS_CLGIBNH, "clgibnh" }, - { SYSZ_INS_CLGIBNHE, "clgibnhe" }, - { SYSZ_INS_CLGIBNL, "clgibnl" }, - { SYSZ_INS_CLGIBNLE, "clgibnle" }, - { SYSZ_INS_CLGIBNLH, "clgibnlh" }, - { SYSZ_INS_CLGIT, "clgit" }, - { SYSZ_INS_CLGITE, "clgite" }, - { SYSZ_INS_CLGITH, "clgith" }, - { SYSZ_INS_CLGITHE, "clgithe" }, - { SYSZ_INS_CLGITL, "clgitl" }, - { SYSZ_INS_CLGITLE, "clgitle" }, - { SYSZ_INS_CLGITLH, "clgitlh" }, - { SYSZ_INS_CLGITNE, "clgitne" }, - { SYSZ_INS_CLGITNH, "clgitnh" }, - { SYSZ_INS_CLGITNHE, "clgitnhe" }, - { SYSZ_INS_CLGITNL, "clgitnl" }, - { SYSZ_INS_CLGITNLE, "clgitnle" }, - { SYSZ_INS_CLGITNLH, "clgitnlh" }, - { SYSZ_INS_CLGRB, "clgrb" }, - { SYSZ_INS_CLGRBE, "clgrbe" }, - { SYSZ_INS_CLGRBH, "clgrbh" }, - { SYSZ_INS_CLGRBHE, "clgrbhe" }, - { SYSZ_INS_CLGRBL, "clgrbl" }, - { SYSZ_INS_CLGRBLE, "clgrble" }, - { SYSZ_INS_CLGRBLH, "clgrblh" }, - { SYSZ_INS_CLGRBNE, "clgrbne" }, - { SYSZ_INS_CLGRBNH, "clgrbnh" }, - { SYSZ_INS_CLGRBNHE, "clgrbnhe" }, - { SYSZ_INS_CLGRBNL, "clgrbnl" }, - { SYSZ_INS_CLGRBNLE, "clgrbnle" }, - { SYSZ_INS_CLGRBNLH, "clgrbnlh" }, - { SYSZ_INS_CLGRT, "clgrt" }, - { SYSZ_INS_CLGRTE, "clgrte" }, - { SYSZ_INS_CLGRTH, "clgrth" }, - { SYSZ_INS_CLGRTHE, "clgrthe" }, - { SYSZ_INS_CLGRTL, "clgrtl" }, - { SYSZ_INS_CLGRTLE, "clgrtle" }, - { SYSZ_INS_CLGRTLH, "clgrtlh" }, - { SYSZ_INS_CLGRTNE, "clgrtne" }, - { SYSZ_INS_CLGRTNH, "clgrtnh" }, - { SYSZ_INS_CLGRTNHE, "clgrtnhe" }, - { SYSZ_INS_CLGRTNL, "clgrtnl" }, - { SYSZ_INS_CLGRTNLE, "clgrtnle" }, - { SYSZ_INS_CLGRTNLH, "clgrtnlh" }, - { SYSZ_INS_CLGT, "clgt" }, - { SYSZ_INS_CLGTE, "clgte" }, - { SYSZ_INS_CLGTH, "clgth" }, - { SYSZ_INS_CLGTHE, "clgthe" }, - { SYSZ_INS_CLGTL, "clgtl" }, - { SYSZ_INS_CLGTLE, "clgtle" }, - { SYSZ_INS_CLGTLH, "clgtlh" }, - { SYSZ_INS_CLGTNE, "clgtne" }, - { SYSZ_INS_CLGTNH, "clgtnh" }, - { SYSZ_INS_CLGTNHE, "clgtnhe" }, - { SYSZ_INS_CLGTNL, "clgtnl" }, - { SYSZ_INS_CLGTNLE, "clgtnle" }, - { SYSZ_INS_CLGTNLH, "clgtnlh" }, - { SYSZ_INS_CLGXTR, "clgxtr" }, - { SYSZ_INS_CLHHR, "clhhr" }, - { SYSZ_INS_CLHLR, "clhlr" }, - { SYSZ_INS_CLIB, "clib" }, - { SYSZ_INS_CLIBE, "clibe" }, - { SYSZ_INS_CLIBH, "clibh" }, - { SYSZ_INS_CLIBHE, "clibhe" }, - { SYSZ_INS_CLIBL, "clibl" }, - { SYSZ_INS_CLIBLE, "clible" }, - { SYSZ_INS_CLIBLH, "cliblh" }, - { SYSZ_INS_CLIBNE, "clibne" }, - { SYSZ_INS_CLIBNH, "clibnh" }, - { SYSZ_INS_CLIBNHE, "clibnhe" }, - { SYSZ_INS_CLIBNL, "clibnl" }, - { SYSZ_INS_CLIBNLE, "clibnle" }, - { SYSZ_INS_CLIBNLH, "clibnlh" }, - { SYSZ_INS_CLM, "clm" }, - { SYSZ_INS_CLMH, "clmh" }, - { SYSZ_INS_CLMY, "clmy" }, - { SYSZ_INS_CLRB, "clrb" }, - { SYSZ_INS_CLRBE, "clrbe" }, - { SYSZ_INS_CLRBH, "clrbh" }, - { SYSZ_INS_CLRBHE, "clrbhe" }, - { SYSZ_INS_CLRBL, "clrbl" }, - { SYSZ_INS_CLRBLE, "clrble" }, - { SYSZ_INS_CLRBLH, "clrblh" }, - { SYSZ_INS_CLRBNE, "clrbne" }, - { SYSZ_INS_CLRBNH, "clrbnh" }, - { SYSZ_INS_CLRBNHE, "clrbnhe" }, - { SYSZ_INS_CLRBNL, "clrbnl" }, - { SYSZ_INS_CLRBNLE, "clrbnle" }, - { SYSZ_INS_CLRBNLH, "clrbnlh" }, - { SYSZ_INS_CLRT, "clrt" }, - { SYSZ_INS_CLRTE, "clrte" }, - { SYSZ_INS_CLRTH, "clrth" }, - { SYSZ_INS_CLRTHE, "clrthe" }, - { SYSZ_INS_CLRTL, "clrtl" }, - { SYSZ_INS_CLRTLE, "clrtle" }, - { SYSZ_INS_CLRTLH, "clrtlh" }, - { SYSZ_INS_CLRTNE, "clrtne" }, - { SYSZ_INS_CLRTNH, "clrtnh" }, - { SYSZ_INS_CLRTNHE, "clrtnhe" }, - { SYSZ_INS_CLRTNL, "clrtnl" }, - { SYSZ_INS_CLRTNLE, "clrtnle" }, - { SYSZ_INS_CLRTNLH, "clrtnlh" }, - { SYSZ_INS_CLT, "clt" }, - { SYSZ_INS_CLTE, "clte" }, - { SYSZ_INS_CLTH, "clth" }, - { SYSZ_INS_CLTHE, "clthe" }, - { SYSZ_INS_CLTL, "cltl" }, - { SYSZ_INS_CLTLE, "cltle" }, - { SYSZ_INS_CLTLH, "cltlh" }, - { SYSZ_INS_CLTNE, "cltne" }, - { SYSZ_INS_CLTNH, "cltnh" }, - { SYSZ_INS_CLTNHE, "cltnhe" }, - { SYSZ_INS_CLTNL, "cltnl" }, - { SYSZ_INS_CLTNLE, "cltnle" }, - { SYSZ_INS_CLTNLH, "cltnlh" }, - { SYSZ_INS_CMPSC, "cmpsc" }, - { SYSZ_INS_CP, "cp" }, - { SYSZ_INS_CPDT, "cpdt" }, - { SYSZ_INS_CPXT, "cpxt" }, - { SYSZ_INS_CPYA, "cpya" }, - { SYSZ_INS_CRB, "crb" }, - { SYSZ_INS_CRBE, "crbe" }, - { SYSZ_INS_CRBH, "crbh" }, - { SYSZ_INS_CRBHE, "crbhe" }, - { SYSZ_INS_CRBL, "crbl" }, - { SYSZ_INS_CRBLE, "crble" }, - { SYSZ_INS_CRBLH, "crblh" }, - { SYSZ_INS_CRBNE, "crbne" }, - { SYSZ_INS_CRBNH, "crbnh" }, - { SYSZ_INS_CRBNHE, "crbnhe" }, - { SYSZ_INS_CRBNL, "crbnl" }, - { SYSZ_INS_CRBNLE, "crbnle" }, - { SYSZ_INS_CRBNLH, "crbnlh" }, - { SYSZ_INS_CRDTE, "crdte" }, - { SYSZ_INS_CRT, "crt" }, - { SYSZ_INS_CRTE, "crte" }, - { SYSZ_INS_CRTH, "crth" }, - { SYSZ_INS_CRTHE, "crthe" }, - { SYSZ_INS_CRTL, "crtl" }, - { SYSZ_INS_CRTLE, "crtle" }, - { SYSZ_INS_CRTLH, "crtlh" }, - { SYSZ_INS_CRTNE, "crtne" }, - { SYSZ_INS_CRTNH, "crtnh" }, - { SYSZ_INS_CRTNHE, "crtnhe" }, - { SYSZ_INS_CRTNL, "crtnl" }, - { SYSZ_INS_CRTNLE, "crtnle" }, - { SYSZ_INS_CRTNLH, "crtnlh" }, - { SYSZ_INS_CSCH, "csch" }, - { SYSZ_INS_CSDTR, "csdtr" }, - { SYSZ_INS_CSP, "csp" }, - { SYSZ_INS_CSPG, "cspg" }, - { SYSZ_INS_CSST, "csst" }, - { SYSZ_INS_CSXTR, "csxtr" }, - { SYSZ_INS_CU12, "cu12" }, - { SYSZ_INS_CU14, "cu14" }, - { SYSZ_INS_CU21, "cu21" }, - { SYSZ_INS_CU24, "cu24" }, - { SYSZ_INS_CU41, "cu41" }, - { SYSZ_INS_CU42, "cu42" }, - { SYSZ_INS_CUDTR, "cudtr" }, - { SYSZ_INS_CUSE, "cuse" }, - { SYSZ_INS_CUTFU, "cutfu" }, - { SYSZ_INS_CUUTF, "cuutf" }, - { SYSZ_INS_CUXTR, "cuxtr" }, - { SYSZ_INS_CVB, "cvb" }, - { SYSZ_INS_CVBG, "cvbg" }, - { SYSZ_INS_CVBY, "cvby" }, - { SYSZ_INS_CVD, "cvd" }, - { SYSZ_INS_CVDG, "cvdg" }, - { SYSZ_INS_CVDY, "cvdy" }, - { SYSZ_INS_CXFBRA, "cxfbra" }, - { SYSZ_INS_CXFR, "cxfr" }, - { SYSZ_INS_CXFTR, "cxftr" }, - { SYSZ_INS_CXGBRA, "cxgbra" }, - { SYSZ_INS_CXGR, "cxgr" }, - { SYSZ_INS_CXGTR, "cxgtr" }, - { SYSZ_INS_CXGTRA, "cxgtra" }, - { SYSZ_INS_CXLFTR, "cxlftr" }, - { SYSZ_INS_CXLGTR, "cxlgtr" }, - { SYSZ_INS_CXPT, "cxpt" }, - { SYSZ_INS_CXR, "cxr" }, - { SYSZ_INS_CXSTR, "cxstr" }, - { SYSZ_INS_CXTR, "cxtr" }, - { SYSZ_INS_CXUTR, "cxutr" }, - { SYSZ_INS_CXZT, "cxzt" }, - { SYSZ_INS_CZDT, "czdt" }, - { SYSZ_INS_CZXT, "czxt" }, - { SYSZ_INS_D, "d" }, - { SYSZ_INS_DD, "dd" }, - { SYSZ_INS_DDR, "ddr" }, - { SYSZ_INS_DDTR, "ddtr" }, - { SYSZ_INS_DDTRA, "ddtra" }, - { SYSZ_INS_DE, "de" }, - { SYSZ_INS_DER, "der" }, - { SYSZ_INS_DIAG, "diag" }, - { SYSZ_INS_DIDBR, "didbr" }, - { SYSZ_INS_DIEBR, "diebr" }, - { SYSZ_INS_DP, "dp" }, - { SYSZ_INS_DR, "dr" }, - { SYSZ_INS_DXR, "dxr" }, - { SYSZ_INS_DXTR, "dxtr" }, - { SYSZ_INS_DXTRA, "dxtra" }, - { SYSZ_INS_ECAG, "ecag" }, - { SYSZ_INS_ECCTR, "ecctr" }, - { SYSZ_INS_ECPGA, "ecpga" }, - { SYSZ_INS_ECTG, "ectg" }, - { SYSZ_INS_ED, "ed" }, - { SYSZ_INS_EDMK, "edmk" }, - { SYSZ_INS_EEDTR, "eedtr" }, - { SYSZ_INS_EEXTR, "eextr" }, - { SYSZ_INS_EFPC, "efpc" }, - { SYSZ_INS_EPAIR, "epair" }, - { SYSZ_INS_EPAR, "epar" }, - { SYSZ_INS_EPCTR, "epctr" }, - { SYSZ_INS_EPSW, "epsw" }, - { SYSZ_INS_EREG, "ereg" }, - { SYSZ_INS_EREGG, "eregg" }, - { SYSZ_INS_ESAIR, "esair" }, - { SYSZ_INS_ESAR, "esar" }, - { SYSZ_INS_ESDTR, "esdtr" }, - { SYSZ_INS_ESEA, "esea" }, - { SYSZ_INS_ESTA, "esta" }, - { SYSZ_INS_ESXTR, "esxtr" }, - { SYSZ_INS_ETND, "etnd" }, - { SYSZ_INS_EX, "ex" }, - { SYSZ_INS_EXRL, "exrl" }, - { SYSZ_INS_FIDR, "fidr" }, - { SYSZ_INS_FIDTR, "fidtr" }, - { SYSZ_INS_FIER, "fier" }, - { SYSZ_INS_FIXR, "fixr" }, - { SYSZ_INS_FIXTR, "fixtr" }, - { SYSZ_INS_HDR, "hdr" }, - { SYSZ_INS_HER, "her" }, - { SYSZ_INS_HSCH, "hsch" }, - { SYSZ_INS_IAC, "iac" }, - { SYSZ_INS_ICM, "icm" }, - { SYSZ_INS_ICMH, "icmh" }, - { SYSZ_INS_ICMY, "icmy" }, - { SYSZ_INS_IDTE, "idte" }, - { SYSZ_INS_IEDTR, "iedtr" }, - { SYSZ_INS_IEXTR, "iextr" }, - { SYSZ_INS_IPK, "ipk" }, - { SYSZ_INS_IPTE, "ipte" }, - { SYSZ_INS_IRBM, "irbm" }, - { SYSZ_INS_ISKE, "iske" }, - { SYSZ_INS_IVSK, "ivsk" }, - { SYSZ_INS_JGM, "jgm" }, - { SYSZ_INS_JGNM, "jgnm" }, - { SYSZ_INS_JGNP, "jgnp" }, - { SYSZ_INS_JGNZ, "jgnz" }, - { SYSZ_INS_JGP, "jgp" }, - { SYSZ_INS_JGZ, "jgz" }, - { SYSZ_INS_JM, "jm" }, - { SYSZ_INS_JNM, "jnm" }, - { SYSZ_INS_JNP, "jnp" }, - { SYSZ_INS_JNZ, "jnz" }, - { SYSZ_INS_JP, "jp" }, - { SYSZ_INS_JZ, "jz" }, - { SYSZ_INS_KDB, "kdb" }, - { SYSZ_INS_KDBR, "kdbr" }, - { SYSZ_INS_KDTR, "kdtr" }, - { SYSZ_INS_KEB, "keb" }, - { SYSZ_INS_KEBR, "kebr" }, - { SYSZ_INS_KIMD, "kimd" }, - { SYSZ_INS_KLMD, "klmd" }, - { SYSZ_INS_KM, "km" }, - { SYSZ_INS_KMA, "kma" }, - { SYSZ_INS_KMAC, "kmac" }, - { SYSZ_INS_KMC, "kmc" }, - { SYSZ_INS_KMCTR, "kmctr" }, - { SYSZ_INS_KMF, "kmf" }, - { SYSZ_INS_KMO, "kmo" }, - { SYSZ_INS_KXBR, "kxbr" }, - { SYSZ_INS_KXTR, "kxtr" }, - { SYSZ_INS_LAE, "lae" }, - { SYSZ_INS_LAEY, "laey" }, - { SYSZ_INS_LAM, "lam" }, - { SYSZ_INS_LAMY, "lamy" }, - { SYSZ_INS_LASP, "lasp" }, - { SYSZ_INS_LAT, "lat" }, - { SYSZ_INS_LCBB, "lcbb" }, - { SYSZ_INS_LCCTL, "lcctl" }, - { SYSZ_INS_LCDFR, "lcdfr" }, - { SYSZ_INS_LCDR, "lcdr" }, - { SYSZ_INS_LCER, "lcer" }, - { SYSZ_INS_LCTL, "lctl" }, - { SYSZ_INS_LCTLG, "lctlg" }, - { SYSZ_INS_LCXR, "lcxr" }, - { SYSZ_INS_LDE, "lde" }, - { SYSZ_INS_LDER, "lder" }, - { SYSZ_INS_LDETR, "ldetr" }, - { SYSZ_INS_LDXR, "ldxr" }, - { SYSZ_INS_LDXTR, "ldxtr" }, - { SYSZ_INS_LEDR, "ledr" }, - { SYSZ_INS_LEDTR, "ledtr" }, - { SYSZ_INS_LEXR, "lexr" }, - { SYSZ_INS_LFAS, "lfas" }, - { SYSZ_INS_LFHAT, "lfhat" }, - { SYSZ_INS_LFPC, "lfpc" }, - { SYSZ_INS_LGAT, "lgat" }, - { SYSZ_INS_LGG, "lgg" }, - { SYSZ_INS_LGSC, "lgsc" }, - { SYSZ_INS_LLGFAT, "llgfat" }, - { SYSZ_INS_LLGFSG, "llgfsg" }, - { SYSZ_INS_LLGT, "llgt" }, - { SYSZ_INS_LLGTAT, "llgtat" }, - { SYSZ_INS_LLGTR, "llgtr" }, - { SYSZ_INS_LLZRGF, "llzrgf" }, - { SYSZ_INS_LM, "lm" }, - { SYSZ_INS_LMD, "lmd" }, - { SYSZ_INS_LMH, "lmh" }, - { SYSZ_INS_LMY, "lmy" }, - { SYSZ_INS_LNDFR, "lndfr" }, - { SYSZ_INS_LNDR, "lndr" }, - { SYSZ_INS_LNER, "lner" }, - { SYSZ_INS_LNXR, "lnxr" }, - { SYSZ_INS_LOCFH, "locfh" }, - { SYSZ_INS_LOCFHE, "locfhe" }, - { SYSZ_INS_LOCFHH, "locfhh" }, - { SYSZ_INS_LOCFHHE, "locfhhe" }, - { SYSZ_INS_LOCFHL, "locfhl" }, - { SYSZ_INS_LOCFHLE, "locfhle" }, - { SYSZ_INS_LOCFHLH, "locfhlh" }, - { SYSZ_INS_LOCFHM, "locfhm" }, - { SYSZ_INS_LOCFHNE, "locfhne" }, - { SYSZ_INS_LOCFHNH, "locfhnh" }, - { SYSZ_INS_LOCFHNHE, "locfhnhe" }, - { SYSZ_INS_LOCFHNL, "locfhnl" }, - { SYSZ_INS_LOCFHNLE, "locfhnle" }, - { SYSZ_INS_LOCFHNLH, "locfhnlh" }, - { SYSZ_INS_LOCFHNM, "locfhnm" }, - { SYSZ_INS_LOCFHNO, "locfhno" }, - { SYSZ_INS_LOCFHNP, "locfhnp" }, - { SYSZ_INS_LOCFHNZ, "locfhnz" }, - { SYSZ_INS_LOCFHO, "locfho" }, - { SYSZ_INS_LOCFHP, "locfhp" }, - { SYSZ_INS_LOCFHR, "locfhr" }, - { SYSZ_INS_LOCFHRE, "locfhre" }, - { SYSZ_INS_LOCFHRH, "locfhrh" }, - { SYSZ_INS_LOCFHRHE, "locfhrhe" }, - { SYSZ_INS_LOCFHRL, "locfhrl" }, - { SYSZ_INS_LOCFHRLE, "locfhrle" }, - { SYSZ_INS_LOCFHRLH, "locfhrlh" }, - { SYSZ_INS_LOCFHRM, "locfhrm" }, - { SYSZ_INS_LOCFHRNE, "locfhrne" }, - { SYSZ_INS_LOCFHRNH, "locfhrnh" }, - { SYSZ_INS_LOCFHRNHE, "locfhrnhe" }, - { SYSZ_INS_LOCFHRNL, "locfhrnl" }, - { SYSZ_INS_LOCFHRNLE, "locfhrnle" }, - { SYSZ_INS_LOCFHRNLH, "locfhrnlh" }, - { SYSZ_INS_LOCFHRNM, "locfhrnm" }, - { SYSZ_INS_LOCFHRNO, "locfhrno" }, - { SYSZ_INS_LOCFHRNP, "locfhrnp" }, - { SYSZ_INS_LOCFHRNZ, "locfhrnz" }, - { SYSZ_INS_LOCFHRO, "locfhro" }, - { SYSZ_INS_LOCFHRP, "locfhrp" }, - { SYSZ_INS_LOCFHRZ, "locfhrz" }, - { SYSZ_INS_LOCFHZ, "locfhz" }, - { SYSZ_INS_LOCGHI, "locghi" }, - { SYSZ_INS_LOCGHIE, "locghie" }, - { SYSZ_INS_LOCGHIH, "locghih" }, - { SYSZ_INS_LOCGHIHE, "locghihe" }, - { SYSZ_INS_LOCGHIL, "locghil" }, - { SYSZ_INS_LOCGHILE, "locghile" }, - { SYSZ_INS_LOCGHILH, "locghilh" }, - { SYSZ_INS_LOCGHIM, "locghim" }, - { SYSZ_INS_LOCGHINE, "locghine" }, - { SYSZ_INS_LOCGHINH, "locghinh" }, - { SYSZ_INS_LOCGHINHE, "locghinhe" }, - { SYSZ_INS_LOCGHINL, "locghinl" }, - { SYSZ_INS_LOCGHINLE, "locghinle" }, - { SYSZ_INS_LOCGHINLH, "locghinlh" }, - { SYSZ_INS_LOCGHINM, "locghinm" }, - { SYSZ_INS_LOCGHINO, "locghino" }, - { SYSZ_INS_LOCGHINP, "locghinp" }, - { SYSZ_INS_LOCGHINZ, "locghinz" }, - { SYSZ_INS_LOCGHIO, "locghio" }, - { SYSZ_INS_LOCGHIP, "locghip" }, - { SYSZ_INS_LOCGHIZ, "locghiz" }, - { SYSZ_INS_LOCGM, "locgm" }, - { SYSZ_INS_LOCGNM, "locgnm" }, - { SYSZ_INS_LOCGNP, "locgnp" }, - { SYSZ_INS_LOCGNZ, "locgnz" }, - { SYSZ_INS_LOCGP, "locgp" }, - { SYSZ_INS_LOCGRM, "locgrm" }, - { SYSZ_INS_LOCGRNM, "locgrnm" }, - { SYSZ_INS_LOCGRNP, "locgrnp" }, - { SYSZ_INS_LOCGRNZ, "locgrnz" }, - { SYSZ_INS_LOCGRP, "locgrp" }, - { SYSZ_INS_LOCGRZ, "locgrz" }, - { SYSZ_INS_LOCGZ, "locgz" }, - { SYSZ_INS_LOCHHI, "lochhi" }, - { SYSZ_INS_LOCHHIE, "lochhie" }, - { SYSZ_INS_LOCHHIH, "lochhih" }, - { SYSZ_INS_LOCHHIHE, "lochhihe" }, - { SYSZ_INS_LOCHHIL, "lochhil" }, - { SYSZ_INS_LOCHHILE, "lochhile" }, - { SYSZ_INS_LOCHHILH, "lochhilh" }, - { SYSZ_INS_LOCHHIM, "lochhim" }, - { SYSZ_INS_LOCHHINE, "lochhine" }, - { SYSZ_INS_LOCHHINH, "lochhinh" }, - { SYSZ_INS_LOCHHINHE, "lochhinhe" }, - { SYSZ_INS_LOCHHINL, "lochhinl" }, - { SYSZ_INS_LOCHHINLE, "lochhinle" }, - { SYSZ_INS_LOCHHINLH, "lochhinlh" }, - { SYSZ_INS_LOCHHINM, "lochhinm" }, - { SYSZ_INS_LOCHHINO, "lochhino" }, - { SYSZ_INS_LOCHHINP, "lochhinp" }, - { SYSZ_INS_LOCHHINZ, "lochhinz" }, - { SYSZ_INS_LOCHHIO, "lochhio" }, - { SYSZ_INS_LOCHHIP, "lochhip" }, - { SYSZ_INS_LOCHHIZ, "lochhiz" }, - { SYSZ_INS_LOCHI, "lochi" }, - { SYSZ_INS_LOCHIE, "lochie" }, - { SYSZ_INS_LOCHIH, "lochih" }, - { SYSZ_INS_LOCHIHE, "lochihe" }, - { SYSZ_INS_LOCHIL, "lochil" }, - { SYSZ_INS_LOCHILE, "lochile" }, - { SYSZ_INS_LOCHILH, "lochilh" }, - { SYSZ_INS_LOCHIM, "lochim" }, - { SYSZ_INS_LOCHINE, "lochine" }, - { SYSZ_INS_LOCHINH, "lochinh" }, - { SYSZ_INS_LOCHINHE, "lochinhe" }, - { SYSZ_INS_LOCHINL, "lochinl" }, - { SYSZ_INS_LOCHINLE, "lochinle" }, - { SYSZ_INS_LOCHINLH, "lochinlh" }, - { SYSZ_INS_LOCHINM, "lochinm" }, - { SYSZ_INS_LOCHINO, "lochino" }, - { SYSZ_INS_LOCHINP, "lochinp" }, - { SYSZ_INS_LOCHINZ, "lochinz" }, - { SYSZ_INS_LOCHIO, "lochio" }, - { SYSZ_INS_LOCHIP, "lochip" }, - { SYSZ_INS_LOCHIZ, "lochiz" }, - { SYSZ_INS_LOCM, "locm" }, - { SYSZ_INS_LOCNM, "locnm" }, - { SYSZ_INS_LOCNP, "locnp" }, - { SYSZ_INS_LOCNZ, "locnz" }, - { SYSZ_INS_LOCP, "locp" }, - { SYSZ_INS_LOCRM, "locrm" }, - { SYSZ_INS_LOCRNM, "locrnm" }, - { SYSZ_INS_LOCRNP, "locrnp" }, - { SYSZ_INS_LOCRNZ, "locrnz" }, - { SYSZ_INS_LOCRP, "locrp" }, - { SYSZ_INS_LOCRZ, "locrz" }, - { SYSZ_INS_LOCZ, "locz" }, - { SYSZ_INS_LPCTL, "lpctl" }, - { SYSZ_INS_LPD, "lpd" }, - { SYSZ_INS_LPDFR, "lpdfr" }, - { SYSZ_INS_LPDG, "lpdg" }, - { SYSZ_INS_LPDR, "lpdr" }, - { SYSZ_INS_LPER, "lper" }, - { SYSZ_INS_LPP, "lpp" }, - { SYSZ_INS_LPQ, "lpq" }, - { SYSZ_INS_LPSW, "lpsw" }, - { SYSZ_INS_LPSWE, "lpswe" }, - { SYSZ_INS_LPTEA, "lptea" }, - { SYSZ_INS_LPXR, "lpxr" }, - { SYSZ_INS_LRA, "lra" }, - { SYSZ_INS_LRAG, "lrag" }, - { SYSZ_INS_LRAY, "lray" }, - { SYSZ_INS_LRDR, "lrdr" }, - { SYSZ_INS_LRER, "lrer" }, - { SYSZ_INS_LRVH, "lrvh" }, - { SYSZ_INS_LSCTL, "lsctl" }, - { SYSZ_INS_LTDR, "ltdr" }, - { SYSZ_INS_LTDTR, "ltdtr" }, - { SYSZ_INS_LTER, "lter" }, - { SYSZ_INS_LTXR, "ltxr" }, - { SYSZ_INS_LTXTR, "ltxtr" }, - { SYSZ_INS_LURA, "lura" }, - { SYSZ_INS_LURAG, "lurag" }, - { SYSZ_INS_LXD, "lxd" }, - { SYSZ_INS_LXDR, "lxdr" }, - { SYSZ_INS_LXDTR, "lxdtr" }, - { SYSZ_INS_LXE, "lxe" }, - { SYSZ_INS_LXER, "lxer" }, - { SYSZ_INS_LZRF, "lzrf" }, - { SYSZ_INS_LZRG, "lzrg" }, - { SYSZ_INS_M, "m" }, - { SYSZ_INS_MAD, "mad" }, - { SYSZ_INS_MADR, "madr" }, - { SYSZ_INS_MAE, "mae" }, - { SYSZ_INS_MAER, "maer" }, - { SYSZ_INS_MAY, "may" }, - { SYSZ_INS_MAYH, "mayh" }, - { SYSZ_INS_MAYHR, "mayhr" }, - { SYSZ_INS_MAYL, "mayl" }, - { SYSZ_INS_MAYLR, "maylr" }, - { SYSZ_INS_MAYR, "mayr" }, - { SYSZ_INS_MC, "mc" }, - { SYSZ_INS_MD, "md" }, - { SYSZ_INS_MDE, "mde" }, - { SYSZ_INS_MDER, "mder" }, - { SYSZ_INS_MDR, "mdr" }, - { SYSZ_INS_MDTR, "mdtr" }, - { SYSZ_INS_MDTRA, "mdtra" }, - { SYSZ_INS_ME, "me" }, - { SYSZ_INS_MEE, "mee" }, - { SYSZ_INS_MEER, "meer" }, - { SYSZ_INS_MER, "mer" }, - { SYSZ_INS_MFY, "mfy" }, - { SYSZ_INS_MG, "mg" }, - { SYSZ_INS_MGH, "mgh" }, - { SYSZ_INS_MGRK, "mgrk" }, - { SYSZ_INS_ML, "ml" }, - { SYSZ_INS_MLR, "mlr" }, - { SYSZ_INS_MP, "mp" }, - { SYSZ_INS_MR, "mr" }, - { SYSZ_INS_MSC, "msc" }, - { SYSZ_INS_MSCH, "msch" }, - { SYSZ_INS_MSD, "msd" }, - { SYSZ_INS_MSDR, "msdr" }, - { SYSZ_INS_MSE, "mse" }, - { SYSZ_INS_MSER, "mser" }, - { SYSZ_INS_MSGC, "msgc" }, - { SYSZ_INS_MSGRKC, "msgrkc" }, - { SYSZ_INS_MSRKC, "msrkc" }, - { SYSZ_INS_MSTA, "msta" }, - { SYSZ_INS_MVCDK, "mvcdk" }, - { SYSZ_INS_MVCIN, "mvcin" }, - { SYSZ_INS_MVCK, "mvck" }, - { SYSZ_INS_MVCL, "mvcl" }, - { SYSZ_INS_MVCLE, "mvcle" }, - { SYSZ_INS_MVCLU, "mvclu" }, - { SYSZ_INS_MVCOS, "mvcos" }, - { SYSZ_INS_MVCP, "mvcp" }, - { SYSZ_INS_MVCS, "mvcs" }, - { SYSZ_INS_MVCSK, "mvcsk" }, - { SYSZ_INS_MVN, "mvn" }, - { SYSZ_INS_MVO, "mvo" }, - { SYSZ_INS_MVPG, "mvpg" }, - { SYSZ_INS_MVZ, "mvz" }, - { SYSZ_INS_MXD, "mxd" }, - { SYSZ_INS_MXDR, "mxdr" }, - { SYSZ_INS_MXR, "mxr" }, - { SYSZ_INS_MXTR, "mxtr" }, - { SYSZ_INS_MXTRA, "mxtra" }, - { SYSZ_INS_MY, "my" }, - { SYSZ_INS_MYH, "myh" }, - { SYSZ_INS_MYHR, "myhr" }, - { SYSZ_INS_MYL, "myl" }, - { SYSZ_INS_MYLR, "mylr" }, - { SYSZ_INS_MYR, "myr" }, - { SYSZ_INS_NIAI, "niai" }, - { SYSZ_INS_NTSTG, "ntstg" }, - { SYSZ_INS_PACK, "pack" }, - { SYSZ_INS_PALB, "palb" }, - { SYSZ_INS_PC, "pc" }, - { SYSZ_INS_PCC, "pcc" }, - { SYSZ_INS_PCKMO, "pckmo" }, - { SYSZ_INS_PFMF, "pfmf" }, - { SYSZ_INS_PFPO, "pfpo" }, - { SYSZ_INS_PGIN, "pgin" }, - { SYSZ_INS_PGOUT, "pgout" }, - { SYSZ_INS_PKA, "pka" }, - { SYSZ_INS_PKU, "pku" }, - { SYSZ_INS_PLO, "plo" }, - { SYSZ_INS_POPCNT, "popcnt" }, - { SYSZ_INS_PPA, "ppa" }, - { SYSZ_INS_PPNO, "ppno" }, - { SYSZ_INS_PR, "pr" }, - { SYSZ_INS_PRNO, "prno" }, - { SYSZ_INS_PT, "pt" }, - { SYSZ_INS_PTF, "ptf" }, - { SYSZ_INS_PTFF, "ptff" }, - { SYSZ_INS_PTI, "pti" }, - { SYSZ_INS_PTLB, "ptlb" }, - { SYSZ_INS_QADTR, "qadtr" }, - { SYSZ_INS_QAXTR, "qaxtr" }, - { SYSZ_INS_QCTRI, "qctri" }, - { SYSZ_INS_QSI, "qsi" }, - { SYSZ_INS_RCHP, "rchp" }, - { SYSZ_INS_RISBGN, "risbgn" }, - { SYSZ_INS_RP, "rp" }, - { SYSZ_INS_RRBE, "rrbe" }, - { SYSZ_INS_RRBM, "rrbm" }, - { SYSZ_INS_RRDTR, "rrdtr" }, - { SYSZ_INS_RRXTR, "rrxtr" }, - { SYSZ_INS_RSCH, "rsch" }, - { SYSZ_INS_SAC, "sac" }, - { SYSZ_INS_SACF, "sacf" }, - { SYSZ_INS_SAL, "sal" }, - { SYSZ_INS_SAM24, "sam24" }, - { SYSZ_INS_SAM31, "sam31" }, - { SYSZ_INS_SAM64, "sam64" }, - { SYSZ_INS_SAR, "sar" }, - { SYSZ_INS_SCCTR, "scctr" }, - { SYSZ_INS_SCHM, "schm" }, - { SYSZ_INS_SCK, "sck" }, - { SYSZ_INS_SCKC, "sckc" }, - { SYSZ_INS_SCKPF, "sckpf" }, - { SYSZ_INS_SD, "sd" }, - { SYSZ_INS_SDR, "sdr" }, - { SYSZ_INS_SDTR, "sdtr" }, - { SYSZ_INS_SDTRA, "sdtra" }, - { SYSZ_INS_SE, "se" }, - { SYSZ_INS_SER, "ser" }, - { SYSZ_INS_SFASR, "sfasr" }, - { SYSZ_INS_SFPC, "sfpc" }, - { SYSZ_INS_SGH, "sgh" }, - { SYSZ_INS_SHHHR, "shhhr" }, - { SYSZ_INS_SHHLR, "shhlr" }, - { SYSZ_INS_SIE, "sie" }, - { SYSZ_INS_SIGA, "siga" }, - { SYSZ_INS_SIGP, "sigp" }, - { SYSZ_INS_SLA, "sla" }, - { SYSZ_INS_SLAG, "slag" }, - { SYSZ_INS_SLAK, "slak" }, - { SYSZ_INS_SLDA, "slda" }, - { SYSZ_INS_SLDL, "sldl" }, - { SYSZ_INS_SLDT, "sldt" }, - { SYSZ_INS_SLHHHR, "slhhhr" }, - { SYSZ_INS_SLHHLR, "slhhlr" }, - { SYSZ_INS_SLXT, "slxt" }, - { SYSZ_INS_SP, "sp" }, - { SYSZ_INS_SPCTR, "spctr" }, - { SYSZ_INS_SPKA, "spka" }, - { SYSZ_INS_SPM, "spm" }, - { SYSZ_INS_SPT, "spt" }, - { SYSZ_INS_SPX, "spx" }, - { SYSZ_INS_SQD, "sqd" }, - { SYSZ_INS_SQDR, "sqdr" }, - { SYSZ_INS_SQE, "sqe" }, - { SYSZ_INS_SQER, "sqer" }, - { SYSZ_INS_SQXR, "sqxr" }, - { SYSZ_INS_SRDA, "srda" }, - { SYSZ_INS_SRDL, "srdl" }, - { SYSZ_INS_SRDT, "srdt" }, - { SYSZ_INS_SRNM, "srnm" }, - { SYSZ_INS_SRNMB, "srnmb" }, - { SYSZ_INS_SRNMT, "srnmt" }, - { SYSZ_INS_SRP, "srp" }, - { SYSZ_INS_SRSTU, "srstu" }, - { SYSZ_INS_SRXT, "srxt" }, - { SYSZ_INS_SSAIR, "ssair" }, - { SYSZ_INS_SSAR, "ssar" }, - { SYSZ_INS_SSCH, "ssch" }, - { SYSZ_INS_SSKE, "sske" }, - { SYSZ_INS_SSM, "ssm" }, - { SYSZ_INS_STAM, "stam" }, - { SYSZ_INS_STAMY, "stamy" }, - { SYSZ_INS_STAP, "stap" }, - { SYSZ_INS_STCK, "stck" }, - { SYSZ_INS_STCKC, "stckc" }, - { SYSZ_INS_STCKE, "stcke" }, - { SYSZ_INS_STCKF, "stckf" }, - { SYSZ_INS_STCM, "stcm" }, - { SYSZ_INS_STCMH, "stcmh" }, - { SYSZ_INS_STCMY, "stcmy" }, - { SYSZ_INS_STCPS, "stcps" }, - { SYSZ_INS_STCRW, "stcrw" }, - { SYSZ_INS_STCTG, "stctg" }, - { SYSZ_INS_STCTL, "stctl" }, - { SYSZ_INS_STFL, "stfl" }, - { SYSZ_INS_STFLE, "stfle" }, - { SYSZ_INS_STFPC, "stfpc" }, - { SYSZ_INS_STGSC, "stgsc" }, - { SYSZ_INS_STIDP, "stidp" }, - { SYSZ_INS_STM, "stm" }, - { SYSZ_INS_STMH, "stmh" }, - { SYSZ_INS_STMY, "stmy" }, - { SYSZ_INS_STNSM, "stnsm" }, - { SYSZ_INS_STOCFH, "stocfh" }, - { SYSZ_INS_STOCFHE, "stocfhe" }, - { SYSZ_INS_STOCFHH, "stocfhh" }, - { SYSZ_INS_STOCFHHE, "stocfhhe" }, - { SYSZ_INS_STOCFHL, "stocfhl" }, - { SYSZ_INS_STOCFHLE, "stocfhle" }, - { SYSZ_INS_STOCFHLH, "stocfhlh" }, - { SYSZ_INS_STOCFHM, "stocfhm" }, - { SYSZ_INS_STOCFHNE, "stocfhne" }, - { SYSZ_INS_STOCFHNH, "stocfhnh" }, - { SYSZ_INS_STOCFHNHE, "stocfhnhe" }, - { SYSZ_INS_STOCFHNL, "stocfhnl" }, - { SYSZ_INS_STOCFHNLE, "stocfhnle" }, - { SYSZ_INS_STOCFHNLH, "stocfhnlh" }, - { SYSZ_INS_STOCFHNM, "stocfhnm" }, - { SYSZ_INS_STOCFHNO, "stocfhno" }, - { SYSZ_INS_STOCFHNP, "stocfhnp" }, - { SYSZ_INS_STOCFHNZ, "stocfhnz" }, - { SYSZ_INS_STOCFHO, "stocfho" }, - { SYSZ_INS_STOCFHP, "stocfhp" }, - { SYSZ_INS_STOCFHZ, "stocfhz" }, - { SYSZ_INS_STOCGM, "stocgm" }, - { SYSZ_INS_STOCGNM, "stocgnm" }, - { SYSZ_INS_STOCGNP, "stocgnp" }, - { SYSZ_INS_STOCGNZ, "stocgnz" }, - { SYSZ_INS_STOCGP, "stocgp" }, - { SYSZ_INS_STOCGZ, "stocgz" }, - { SYSZ_INS_STOCM, "stocm" }, - { SYSZ_INS_STOCNM, "stocnm" }, - { SYSZ_INS_STOCNP, "stocnp" }, - { SYSZ_INS_STOCNZ, "stocnz" }, - { SYSZ_INS_STOCP, "stocp" }, - { SYSZ_INS_STOCZ, "stocz" }, - { SYSZ_INS_STOSM, "stosm" }, - { SYSZ_INS_STPQ, "stpq" }, - { SYSZ_INS_STPT, "stpt" }, - { SYSZ_INS_STPX, "stpx" }, - { SYSZ_INS_STRAG, "strag" }, - { SYSZ_INS_STRVH, "strvh" }, - { SYSZ_INS_STSCH, "stsch" }, - { SYSZ_INS_STSI, "stsi" }, - { SYSZ_INS_STURA, "stura" }, - { SYSZ_INS_STURG, "sturg" }, - { SYSZ_INS_SU, "su" }, - { SYSZ_INS_SUR, "sur" }, - { SYSZ_INS_SVC, "svc" }, - { SYSZ_INS_SW, "sw" }, - { SYSZ_INS_SWR, "swr" }, - { SYSZ_INS_SXR, "sxr" }, - { SYSZ_INS_SXTR, "sxtr" }, - { SYSZ_INS_SXTRA, "sxtra" }, - { SYSZ_INS_TABORT, "tabort" }, - { SYSZ_INS_TAM, "tam" }, - { SYSZ_INS_TAR, "tar" }, - { SYSZ_INS_TB, "tb" }, - { SYSZ_INS_TBDR, "tbdr" }, - { SYSZ_INS_TBEDR, "tbedr" }, - { SYSZ_INS_TBEGIN, "tbegin" }, - { SYSZ_INS_TBEGINC, "tbeginc" }, - { SYSZ_INS_TCDB, "tcdb" }, - { SYSZ_INS_TCEB, "tceb" }, - { SYSZ_INS_TCXB, "tcxb" }, - { SYSZ_INS_TDCDT, "tdcdt" }, - { SYSZ_INS_TDCET, "tdcet" }, - { SYSZ_INS_TDCXT, "tdcxt" }, - { SYSZ_INS_TDGDT, "tdgdt" }, - { SYSZ_INS_TDGET, "tdget" }, - { SYSZ_INS_TDGXT, "tdgxt" }, - { SYSZ_INS_TEND, "tend" }, - { SYSZ_INS_THDER, "thder" }, - { SYSZ_INS_THDR, "thdr" }, - { SYSZ_INS_TP, "tp" }, - { SYSZ_INS_TPI, "tpi" }, - { SYSZ_INS_TPROT, "tprot" }, - { SYSZ_INS_TR, "tr" }, - { SYSZ_INS_TRACE, "trace" }, - { SYSZ_INS_TRACG, "tracg" }, - { SYSZ_INS_TRAP2, "trap2" }, - { SYSZ_INS_TRAP4, "trap4" }, - { SYSZ_INS_TRE, "tre" }, - { SYSZ_INS_TROO, "troo" }, - { SYSZ_INS_TROT, "trot" }, - { SYSZ_INS_TRT, "trt" }, - { SYSZ_INS_TRTE, "trte" }, - { SYSZ_INS_TRTO, "trto" }, - { SYSZ_INS_TRTR, "trtr" }, - { SYSZ_INS_TRTRE, "trtre" }, - { SYSZ_INS_TRTT, "trtt" }, - { SYSZ_INS_TS, "ts" }, - { SYSZ_INS_TSCH, "tsch" }, - { SYSZ_INS_UNPK, "unpk" }, - { SYSZ_INS_UNPKA, "unpka" }, - { SYSZ_INS_UNPKU, "unpku" }, - { SYSZ_INS_UPT, "upt" }, - { SYSZ_INS_VA, "va" }, - { SYSZ_INS_VAB, "vab" }, - { SYSZ_INS_VAC, "vac" }, - { SYSZ_INS_VACC, "vacc" }, - { SYSZ_INS_VACCB, "vaccb" }, - { SYSZ_INS_VACCC, "vaccc" }, - { SYSZ_INS_VACCCQ, "vacccq" }, - { SYSZ_INS_VACCF, "vaccf" }, - { SYSZ_INS_VACCG, "vaccg" }, - { SYSZ_INS_VACCH, "vacch" }, - { SYSZ_INS_VACCQ, "vaccq" }, - { SYSZ_INS_VACQ, "vacq" }, - { SYSZ_INS_VAF, "vaf" }, - { SYSZ_INS_VAG, "vag" }, - { SYSZ_INS_VAH, "vah" }, - { SYSZ_INS_VAP, "vap" }, - { SYSZ_INS_VAQ, "vaq" }, - { SYSZ_INS_VAVG, "vavg" }, - { SYSZ_INS_VAVGB, "vavgb" }, - { SYSZ_INS_VAVGF, "vavgf" }, - { SYSZ_INS_VAVGG, "vavgg" }, - { SYSZ_INS_VAVGH, "vavgh" }, - { SYSZ_INS_VAVGL, "vavgl" }, - { SYSZ_INS_VAVGLB, "vavglb" }, - { SYSZ_INS_VAVGLF, "vavglf" }, - { SYSZ_INS_VAVGLG, "vavglg" }, - { SYSZ_INS_VAVGLH, "vavglh" }, - { SYSZ_INS_VBPERM, "vbperm" }, - { SYSZ_INS_VCDG, "vcdg" }, - { SYSZ_INS_VCDGB, "vcdgb" }, - { SYSZ_INS_VCDLG, "vcdlg" }, - { SYSZ_INS_VCDLGB, "vcdlgb" }, - { SYSZ_INS_VCEQ, "vceq" }, - { SYSZ_INS_VCEQB, "vceqb" }, - { SYSZ_INS_VCEQBS, "vceqbs" }, - { SYSZ_INS_VCEQF, "vceqf" }, - { SYSZ_INS_VCEQFS, "vceqfs" }, - { SYSZ_INS_VCEQG, "vceqg" }, - { SYSZ_INS_VCEQGS, "vceqgs" }, - { SYSZ_INS_VCEQH, "vceqh" }, - { SYSZ_INS_VCEQHS, "vceqhs" }, - { SYSZ_INS_VCGD, "vcgd" }, - { SYSZ_INS_VCGDB, "vcgdb" }, - { SYSZ_INS_VCH, "vch" }, - { SYSZ_INS_VCHB, "vchb" }, - { SYSZ_INS_VCHBS, "vchbs" }, - { SYSZ_INS_VCHF, "vchf" }, - { SYSZ_INS_VCHFS, "vchfs" }, - { SYSZ_INS_VCHG, "vchg" }, - { SYSZ_INS_VCHGS, "vchgs" }, - { SYSZ_INS_VCHH, "vchh" }, - { SYSZ_INS_VCHHS, "vchhs" }, - { SYSZ_INS_VCHL, "vchl" }, - { SYSZ_INS_VCHLB, "vchlb" }, - { SYSZ_INS_VCHLBS, "vchlbs" }, - { SYSZ_INS_VCHLF, "vchlf" }, - { SYSZ_INS_VCHLFS, "vchlfs" }, - { SYSZ_INS_VCHLG, "vchlg" }, - { SYSZ_INS_VCHLGS, "vchlgs" }, - { SYSZ_INS_VCHLH, "vchlh" }, - { SYSZ_INS_VCHLHS, "vchlhs" }, - { SYSZ_INS_VCKSM, "vcksm" }, - { SYSZ_INS_VCLGD, "vclgd" }, - { SYSZ_INS_VCLGDB, "vclgdb" }, - { SYSZ_INS_VCLZ, "vclz" }, - { SYSZ_INS_VCLZB, "vclzb" }, - { SYSZ_INS_VCLZF, "vclzf" }, - { SYSZ_INS_VCLZG, "vclzg" }, - { SYSZ_INS_VCLZH, "vclzh" }, - { SYSZ_INS_VCP, "vcp" }, - { SYSZ_INS_VCTZ, "vctz" }, - { SYSZ_INS_VCTZB, "vctzb" }, - { SYSZ_INS_VCTZF, "vctzf" }, - { SYSZ_INS_VCTZG, "vctzg" }, - { SYSZ_INS_VCTZH, "vctzh" }, - { SYSZ_INS_VCVB, "vcvb" }, - { SYSZ_INS_VCVBG, "vcvbg" }, - { SYSZ_INS_VCVD, "vcvd" }, - { SYSZ_INS_VCVDG, "vcvdg" }, - { SYSZ_INS_VDP, "vdp" }, - { SYSZ_INS_VEC, "vec" }, - { SYSZ_INS_VECB, "vecb" }, - { SYSZ_INS_VECF, "vecf" }, - { SYSZ_INS_VECG, "vecg" }, - { SYSZ_INS_VECH, "vech" }, - { SYSZ_INS_VECL, "vecl" }, - { SYSZ_INS_VECLB, "veclb" }, - { SYSZ_INS_VECLF, "veclf" }, - { SYSZ_INS_VECLG, "veclg" }, - { SYSZ_INS_VECLH, "veclh" }, - { SYSZ_INS_VERIM, "verim" }, - { SYSZ_INS_VERIMB, "verimb" }, - { SYSZ_INS_VERIMF, "verimf" }, - { SYSZ_INS_VERIMG, "verimg" }, - { SYSZ_INS_VERIMH, "verimh" }, - { SYSZ_INS_VERLL, "verll" }, - { SYSZ_INS_VERLLB, "verllb" }, - { SYSZ_INS_VERLLF, "verllf" }, - { SYSZ_INS_VERLLG, "verllg" }, - { SYSZ_INS_VERLLH, "verllh" }, - { SYSZ_INS_VERLLV, "verllv" }, - { SYSZ_INS_VERLLVB, "verllvb" }, - { SYSZ_INS_VERLLVF, "verllvf" }, - { SYSZ_INS_VERLLVG, "verllvg" }, - { SYSZ_INS_VERLLVH, "verllvh" }, - { SYSZ_INS_VESL, "vesl" }, - { SYSZ_INS_VESLB, "veslb" }, - { SYSZ_INS_VESLF, "veslf" }, - { SYSZ_INS_VESLG, "veslg" }, - { SYSZ_INS_VESLH, "veslh" }, - { SYSZ_INS_VESLV, "veslv" }, - { SYSZ_INS_VESLVB, "veslvb" }, - { SYSZ_INS_VESLVF, "veslvf" }, - { SYSZ_INS_VESLVG, "veslvg" }, - { SYSZ_INS_VESLVH, "veslvh" }, - { SYSZ_INS_VESRA, "vesra" }, - { SYSZ_INS_VESRAB, "vesrab" }, - { SYSZ_INS_VESRAF, "vesraf" }, - { SYSZ_INS_VESRAG, "vesrag" }, - { SYSZ_INS_VESRAH, "vesrah" }, - { SYSZ_INS_VESRAV, "vesrav" }, - { SYSZ_INS_VESRAVB, "vesravb" }, - { SYSZ_INS_VESRAVF, "vesravf" }, - { SYSZ_INS_VESRAVG, "vesravg" }, - { SYSZ_INS_VESRAVH, "vesravh" }, - { SYSZ_INS_VESRL, "vesrl" }, - { SYSZ_INS_VESRLB, "vesrlb" }, - { SYSZ_INS_VESRLF, "vesrlf" }, - { SYSZ_INS_VESRLG, "vesrlg" }, - { SYSZ_INS_VESRLH, "vesrlh" }, - { SYSZ_INS_VESRLV, "vesrlv" }, - { SYSZ_INS_VESRLVB, "vesrlvb" }, - { SYSZ_INS_VESRLVF, "vesrlvf" }, - { SYSZ_INS_VESRLVG, "vesrlvg" }, - { SYSZ_INS_VESRLVH, "vesrlvh" }, - { SYSZ_INS_VFA, "vfa" }, - { SYSZ_INS_VFADB, "vfadb" }, - { SYSZ_INS_VFAE, "vfae" }, - { SYSZ_INS_VFAEB, "vfaeb" }, - { SYSZ_INS_VFAEBS, "vfaebs" }, - { SYSZ_INS_VFAEF, "vfaef" }, - { SYSZ_INS_VFAEFS, "vfaefs" }, - { SYSZ_INS_VFAEH, "vfaeh" }, - { SYSZ_INS_VFAEHS, "vfaehs" }, - { SYSZ_INS_VFAEZB, "vfaezb" }, - { SYSZ_INS_VFAEZBS, "vfaezbs" }, - { SYSZ_INS_VFAEZF, "vfaezf" }, - { SYSZ_INS_VFAEZFS, "vfaezfs" }, - { SYSZ_INS_VFAEZH, "vfaezh" }, - { SYSZ_INS_VFAEZHS, "vfaezhs" }, - { SYSZ_INS_VFASB, "vfasb" }, - { SYSZ_INS_VFCE, "vfce" }, - { SYSZ_INS_VFCEDB, "vfcedb" }, - { SYSZ_INS_VFCEDBS, "vfcedbs" }, - { SYSZ_INS_VFCESB, "vfcesb" }, - { SYSZ_INS_VFCESBS, "vfcesbs" }, - { SYSZ_INS_VFCH, "vfch" }, - { SYSZ_INS_VFCHDB, "vfchdb" }, - { SYSZ_INS_VFCHDBS, "vfchdbs" }, - { SYSZ_INS_VFCHE, "vfche" }, - { SYSZ_INS_VFCHEDB, "vfchedb" }, - { SYSZ_INS_VFCHEDBS, "vfchedbs" }, - { SYSZ_INS_VFCHESB, "vfchesb" }, - { SYSZ_INS_VFCHESBS, "vfchesbs" }, - { SYSZ_INS_VFCHSB, "vfchsb" }, - { SYSZ_INS_VFCHSBS, "vfchsbs" }, - { SYSZ_INS_VFD, "vfd" }, - { SYSZ_INS_VFDDB, "vfddb" }, - { SYSZ_INS_VFDSB, "vfdsb" }, - { SYSZ_INS_VFEE, "vfee" }, - { SYSZ_INS_VFEEB, "vfeeb" }, - { SYSZ_INS_VFEEBS, "vfeebs" }, - { SYSZ_INS_VFEEF, "vfeef" }, - { SYSZ_INS_VFEEFS, "vfeefs" }, - { SYSZ_INS_VFEEH, "vfeeh" }, - { SYSZ_INS_VFEEHS, "vfeehs" }, - { SYSZ_INS_VFEEZB, "vfeezb" }, - { SYSZ_INS_VFEEZBS, "vfeezbs" }, - { SYSZ_INS_VFEEZF, "vfeezf" }, - { SYSZ_INS_VFEEZFS, "vfeezfs" }, - { SYSZ_INS_VFEEZH, "vfeezh" }, - { SYSZ_INS_VFEEZHS, "vfeezhs" }, - { SYSZ_INS_VFENE, "vfene" }, - { SYSZ_INS_VFENEB, "vfeneb" }, - { SYSZ_INS_VFENEBS, "vfenebs" }, - { SYSZ_INS_VFENEF, "vfenef" }, - { SYSZ_INS_VFENEFS, "vfenefs" }, - { SYSZ_INS_VFENEH, "vfeneh" }, - { SYSZ_INS_VFENEHS, "vfenehs" }, - { SYSZ_INS_VFENEZB, "vfenezb" }, - { SYSZ_INS_VFENEZBS, "vfenezbs" }, - { SYSZ_INS_VFENEZF, "vfenezf" }, - { SYSZ_INS_VFENEZFS, "vfenezfs" }, - { SYSZ_INS_VFENEZH, "vfenezh" }, - { SYSZ_INS_VFENEZHS, "vfenezhs" }, - { SYSZ_INS_VFI, "vfi" }, - { SYSZ_INS_VFIDB, "vfidb" }, - { SYSZ_INS_VFISB, "vfisb" }, - { SYSZ_INS_VFKEDB, "vfkedb" }, - { SYSZ_INS_VFKEDBS, "vfkedbs" }, - { SYSZ_INS_VFKESB, "vfkesb" }, - { SYSZ_INS_VFKESBS, "vfkesbs" }, - { SYSZ_INS_VFKHDB, "vfkhdb" }, - { SYSZ_INS_VFKHDBS, "vfkhdbs" }, - { SYSZ_INS_VFKHEDB, "vfkhedb" }, - { SYSZ_INS_VFKHEDBS, "vfkhedbs" }, - { SYSZ_INS_VFKHESB, "vfkhesb" }, - { SYSZ_INS_VFKHESBS, "vfkhesbs" }, - { SYSZ_INS_VFKHSB, "vfkhsb" }, - { SYSZ_INS_VFKHSBS, "vfkhsbs" }, - { SYSZ_INS_VFLCDB, "vflcdb" }, - { SYSZ_INS_VFLCSB, "vflcsb" }, - { SYSZ_INS_VFLL, "vfll" }, - { SYSZ_INS_VFLLS, "vflls" }, - { SYSZ_INS_VFLNDB, "vflndb" }, - { SYSZ_INS_VFLNSB, "vflnsb" }, - { SYSZ_INS_VFLPDB, "vflpdb" }, - { SYSZ_INS_VFLPSB, "vflpsb" }, - { SYSZ_INS_VFLR, "vflr" }, - { SYSZ_INS_VFLRD, "vflrd" }, - { SYSZ_INS_VFM, "vfm" }, - { SYSZ_INS_VFMA, "vfma" }, - { SYSZ_INS_VFMADB, "vfmadb" }, - { SYSZ_INS_VFMASB, "vfmasb" }, - { SYSZ_INS_VFMAX, "vfmax" }, - { SYSZ_INS_VFMAXDB, "vfmaxdb" }, - { SYSZ_INS_VFMAXSB, "vfmaxsb" }, - { SYSZ_INS_VFMDB, "vfmdb" }, - { SYSZ_INS_VFMIN, "vfmin" }, - { SYSZ_INS_VFMINDB, "vfmindb" }, - { SYSZ_INS_VFMINSB, "vfminsb" }, - { SYSZ_INS_VFMS, "vfms" }, - { SYSZ_INS_VFMSB, "vfmsb" }, - { SYSZ_INS_VFMSDB, "vfmsdb" }, - { SYSZ_INS_VFMSSB, "vfmssb" }, - { SYSZ_INS_VFNMA, "vfnma" }, - { SYSZ_INS_VFNMADB, "vfnmadb" }, - { SYSZ_INS_VFNMASB, "vfnmasb" }, - { SYSZ_INS_VFNMS, "vfnms" }, - { SYSZ_INS_VFNMSDB, "vfnmsdb" }, - { SYSZ_INS_VFNMSSB, "vfnmssb" }, - { SYSZ_INS_VFPSO, "vfpso" }, - { SYSZ_INS_VFPSODB, "vfpsodb" }, - { SYSZ_INS_VFPSOSB, "vfpsosb" }, - { SYSZ_INS_VFS, "vfs" }, - { SYSZ_INS_VFSDB, "vfsdb" }, - { SYSZ_INS_VFSQ, "vfsq" }, - { SYSZ_INS_VFSQDB, "vfsqdb" }, - { SYSZ_INS_VFSQSB, "vfsqsb" }, - { SYSZ_INS_VFSSB, "vfssb" }, - { SYSZ_INS_VFTCI, "vftci" }, - { SYSZ_INS_VFTCIDB, "vftcidb" }, - { SYSZ_INS_VFTCISB, "vftcisb" }, - { SYSZ_INS_VGBM, "vgbm" }, - { SYSZ_INS_VGEF, "vgef" }, - { SYSZ_INS_VGEG, "vgeg" }, - { SYSZ_INS_VGFM, "vgfm" }, - { SYSZ_INS_VGFMA, "vgfma" }, - { SYSZ_INS_VGFMAB, "vgfmab" }, - { SYSZ_INS_VGFMAF, "vgfmaf" }, - { SYSZ_INS_VGFMAG, "vgfmag" }, - { SYSZ_INS_VGFMAH, "vgfmah" }, - { SYSZ_INS_VGFMB, "vgfmb" }, - { SYSZ_INS_VGFMF, "vgfmf" }, - { SYSZ_INS_VGFMG, "vgfmg" }, - { SYSZ_INS_VGFMH, "vgfmh" }, - { SYSZ_INS_VGM, "vgm" }, - { SYSZ_INS_VGMB, "vgmb" }, - { SYSZ_INS_VGMF, "vgmf" }, - { SYSZ_INS_VGMG, "vgmg" }, - { SYSZ_INS_VGMH, "vgmh" }, - { SYSZ_INS_VISTR, "vistr" }, - { SYSZ_INS_VISTRB, "vistrb" }, - { SYSZ_INS_VISTRBS, "vistrbs" }, - { SYSZ_INS_VISTRF, "vistrf" }, - { SYSZ_INS_VISTRFS, "vistrfs" }, - { SYSZ_INS_VISTRH, "vistrh" }, - { SYSZ_INS_VISTRHS, "vistrhs" }, - { SYSZ_INS_VL, "vl" }, - { SYSZ_INS_VLBB, "vlbb" }, - { SYSZ_INS_VLC, "vlc" }, - { SYSZ_INS_VLCB, "vlcb" }, - { SYSZ_INS_VLCF, "vlcf" }, - { SYSZ_INS_VLCG, "vlcg" }, - { SYSZ_INS_VLCH, "vlch" }, - { SYSZ_INS_VLDE, "vlde" }, - { SYSZ_INS_VLDEB, "vldeb" }, - { SYSZ_INS_VLEB, "vleb" }, - { SYSZ_INS_VLED, "vled" }, - { SYSZ_INS_VLEDB, "vledb" }, - { SYSZ_INS_VLEF, "vlef" }, - { SYSZ_INS_VLEG, "vleg" }, - { SYSZ_INS_VLEH, "vleh" }, - { SYSZ_INS_VLEIB, "vleib" }, - { SYSZ_INS_VLEIF, "vleif" }, - { SYSZ_INS_VLEIG, "vleig" }, - { SYSZ_INS_VLEIH, "vleih" }, - { SYSZ_INS_VLGV, "vlgv" }, - { SYSZ_INS_VLGVB, "vlgvb" }, - { SYSZ_INS_VLGVF, "vlgvf" }, - { SYSZ_INS_VLGVG, "vlgvg" }, - { SYSZ_INS_VLGVH, "vlgvh" }, - { SYSZ_INS_VLIP, "vlip" }, - { SYSZ_INS_VLL, "vll" }, - { SYSZ_INS_VLLEZ, "vllez" }, - { SYSZ_INS_VLLEZB, "vllezb" }, - { SYSZ_INS_VLLEZF, "vllezf" }, - { SYSZ_INS_VLLEZG, "vllezg" }, - { SYSZ_INS_VLLEZH, "vllezh" }, - { SYSZ_INS_VLLEZLF, "vllezlf" }, - { SYSZ_INS_VLM, "vlm" }, - { SYSZ_INS_VLP, "vlp" }, - { SYSZ_INS_VLPB, "vlpb" }, - { SYSZ_INS_VLPF, "vlpf" }, - { SYSZ_INS_VLPG, "vlpg" }, - { SYSZ_INS_VLPH, "vlph" }, - { SYSZ_INS_VLR, "vlr" }, - { SYSZ_INS_VLREP, "vlrep" }, - { SYSZ_INS_VLREPB, "vlrepb" }, - { SYSZ_INS_VLREPF, "vlrepf" }, - { SYSZ_INS_VLREPG, "vlrepg" }, - { SYSZ_INS_VLREPH, "vlreph" }, - { SYSZ_INS_VLRL, "vlrl" }, - { SYSZ_INS_VLRLR, "vlrlr" }, - { SYSZ_INS_VLVG, "vlvg" }, - { SYSZ_INS_VLVGB, "vlvgb" }, - { SYSZ_INS_VLVGF, "vlvgf" }, - { SYSZ_INS_VLVGG, "vlvgg" }, - { SYSZ_INS_VLVGH, "vlvgh" }, - { SYSZ_INS_VLVGP, "vlvgp" }, - { SYSZ_INS_VMAE, "vmae" }, - { SYSZ_INS_VMAEB, "vmaeb" }, - { SYSZ_INS_VMAEF, "vmaef" }, - { SYSZ_INS_VMAEH, "vmaeh" }, - { SYSZ_INS_VMAH, "vmah" }, - { SYSZ_INS_VMAHB, "vmahb" }, - { SYSZ_INS_VMAHF, "vmahf" }, - { SYSZ_INS_VMAHH, "vmahh" }, - { SYSZ_INS_VMAL, "vmal" }, - { SYSZ_INS_VMALB, "vmalb" }, - { SYSZ_INS_VMALE, "vmale" }, - { SYSZ_INS_VMALEB, "vmaleb" }, - { SYSZ_INS_VMALEF, "vmalef" }, - { SYSZ_INS_VMALEH, "vmaleh" }, - { SYSZ_INS_VMALF, "vmalf" }, - { SYSZ_INS_VMALH, "vmalh" }, - { SYSZ_INS_VMALHB, "vmalhb" }, - { SYSZ_INS_VMALHF, "vmalhf" }, - { SYSZ_INS_VMALHH, "vmalhh" }, - { SYSZ_INS_VMALHW, "vmalhw" }, - { SYSZ_INS_VMALO, "vmalo" }, - { SYSZ_INS_VMALOB, "vmalob" }, - { SYSZ_INS_VMALOF, "vmalof" }, - { SYSZ_INS_VMALOH, "vmaloh" }, - { SYSZ_INS_VMAO, "vmao" }, - { SYSZ_INS_VMAOB, "vmaob" }, - { SYSZ_INS_VMAOF, "vmaof" }, - { SYSZ_INS_VMAOH, "vmaoh" }, - { SYSZ_INS_VME, "vme" }, - { SYSZ_INS_VMEB, "vmeb" }, - { SYSZ_INS_VMEF, "vmef" }, - { SYSZ_INS_VMEH, "vmeh" }, - { SYSZ_INS_VMH, "vmh" }, - { SYSZ_INS_VMHB, "vmhb" }, - { SYSZ_INS_VMHF, "vmhf" }, - { SYSZ_INS_VMHH, "vmhh" }, - { SYSZ_INS_VML, "vml" }, - { SYSZ_INS_VMLB, "vmlb" }, - { SYSZ_INS_VMLE, "vmle" }, - { SYSZ_INS_VMLEB, "vmleb" }, - { SYSZ_INS_VMLEF, "vmlef" }, - { SYSZ_INS_VMLEH, "vmleh" }, - { SYSZ_INS_VMLF, "vmlf" }, - { SYSZ_INS_VMLH, "vmlh" }, - { SYSZ_INS_VMLHB, "vmlhb" }, - { SYSZ_INS_VMLHF, "vmlhf" }, - { SYSZ_INS_VMLHH, "vmlhh" }, - { SYSZ_INS_VMLHW, "vmlhw" }, - { SYSZ_INS_VMLO, "vmlo" }, - { SYSZ_INS_VMLOB, "vmlob" }, - { SYSZ_INS_VMLOF, "vmlof" }, - { SYSZ_INS_VMLOH, "vmloh" }, - { SYSZ_INS_VMN, "vmn" }, - { SYSZ_INS_VMNB, "vmnb" }, - { SYSZ_INS_VMNF, "vmnf" }, - { SYSZ_INS_VMNG, "vmng" }, - { SYSZ_INS_VMNH, "vmnh" }, - { SYSZ_INS_VMNL, "vmnl" }, - { SYSZ_INS_VMNLB, "vmnlb" }, - { SYSZ_INS_VMNLF, "vmnlf" }, - { SYSZ_INS_VMNLG, "vmnlg" }, - { SYSZ_INS_VMNLH, "vmnlh" }, - { SYSZ_INS_VMO, "vmo" }, - { SYSZ_INS_VMOB, "vmob" }, - { SYSZ_INS_VMOF, "vmof" }, - { SYSZ_INS_VMOH, "vmoh" }, - { SYSZ_INS_VMP, "vmp" }, - { SYSZ_INS_VMRH, "vmrh" }, - { SYSZ_INS_VMRHB, "vmrhb" }, - { SYSZ_INS_VMRHF, "vmrhf" }, - { SYSZ_INS_VMRHG, "vmrhg" }, - { SYSZ_INS_VMRHH, "vmrhh" }, - { SYSZ_INS_VMRL, "vmrl" }, - { SYSZ_INS_VMRLB, "vmrlb" }, - { SYSZ_INS_VMRLF, "vmrlf" }, - { SYSZ_INS_VMRLG, "vmrlg" }, - { SYSZ_INS_VMRLH, "vmrlh" }, - { SYSZ_INS_VMSL, "vmsl" }, - { SYSZ_INS_VMSLG, "vmslg" }, - { SYSZ_INS_VMSP, "vmsp" }, - { SYSZ_INS_VMX, "vmx" }, - { SYSZ_INS_VMXB, "vmxb" }, - { SYSZ_INS_VMXF, "vmxf" }, - { SYSZ_INS_VMXG, "vmxg" }, - { SYSZ_INS_VMXH, "vmxh" }, - { SYSZ_INS_VMXL, "vmxl" }, - { SYSZ_INS_VMXLB, "vmxlb" }, - { SYSZ_INS_VMXLF, "vmxlf" }, - { SYSZ_INS_VMXLG, "vmxlg" }, - { SYSZ_INS_VMXLH, "vmxlh" }, - { SYSZ_INS_VN, "vn" }, - { SYSZ_INS_VNC, "vnc" }, - { SYSZ_INS_VNN, "vnn" }, - { SYSZ_INS_VNO, "vno" }, - { SYSZ_INS_VNX, "vnx" }, - { SYSZ_INS_VO, "vo" }, - { SYSZ_INS_VOC, "voc" }, - { SYSZ_INS_VONE, "vone" }, - { SYSZ_INS_VPDI, "vpdi" }, - { SYSZ_INS_VPERM, "vperm" }, - { SYSZ_INS_VPK, "vpk" }, - { SYSZ_INS_VPKF, "vpkf" }, - { SYSZ_INS_VPKG, "vpkg" }, - { SYSZ_INS_VPKH, "vpkh" }, - { SYSZ_INS_VPKLS, "vpkls" }, - { SYSZ_INS_VPKLSF, "vpklsf" }, - { SYSZ_INS_VPKLSFS, "vpklsfs" }, - { SYSZ_INS_VPKLSG, "vpklsg" }, - { SYSZ_INS_VPKLSGS, "vpklsgs" }, - { SYSZ_INS_VPKLSH, "vpklsh" }, - { SYSZ_INS_VPKLSHS, "vpklshs" }, - { SYSZ_INS_VPKS, "vpks" }, - { SYSZ_INS_VPKSF, "vpksf" }, - { SYSZ_INS_VPKSFS, "vpksfs" }, - { SYSZ_INS_VPKSG, "vpksg" }, - { SYSZ_INS_VPKSGS, "vpksgs" }, - { SYSZ_INS_VPKSH, "vpksh" }, - { SYSZ_INS_VPKSHS, "vpkshs" }, - { SYSZ_INS_VPKZ, "vpkz" }, - { SYSZ_INS_VPOPCT, "vpopct" }, - { SYSZ_INS_VPOPCTB, "vpopctb" }, - { SYSZ_INS_VPOPCTF, "vpopctf" }, - { SYSZ_INS_VPOPCTG, "vpopctg" }, - { SYSZ_INS_VPOPCTH, "vpopcth" }, - { SYSZ_INS_VPSOP, "vpsop" }, - { SYSZ_INS_VREP, "vrep" }, - { SYSZ_INS_VREPB, "vrepb" }, - { SYSZ_INS_VREPF, "vrepf" }, - { SYSZ_INS_VREPG, "vrepg" }, - { SYSZ_INS_VREPH, "vreph" }, - { SYSZ_INS_VREPI, "vrepi" }, - { SYSZ_INS_VREPIB, "vrepib" }, - { SYSZ_INS_VREPIF, "vrepif" }, - { SYSZ_INS_VREPIG, "vrepig" }, - { SYSZ_INS_VREPIH, "vrepih" }, - { SYSZ_INS_VRP, "vrp" }, - { SYSZ_INS_VS, "vs" }, - { SYSZ_INS_VSB, "vsb" }, - { SYSZ_INS_VSBCBI, "vsbcbi" }, - { SYSZ_INS_VSBCBIQ, "vsbcbiq" }, - { SYSZ_INS_VSBI, "vsbi" }, - { SYSZ_INS_VSBIQ, "vsbiq" }, - { SYSZ_INS_VSCBI, "vscbi" }, - { SYSZ_INS_VSCBIB, "vscbib" }, - { SYSZ_INS_VSCBIF, "vscbif" }, - { SYSZ_INS_VSCBIG, "vscbig" }, - { SYSZ_INS_VSCBIH, "vscbih" }, - { SYSZ_INS_VSCBIQ, "vscbiq" }, - { SYSZ_INS_VSCEF, "vscef" }, - { SYSZ_INS_VSCEG, "vsceg" }, - { SYSZ_INS_VSDP, "vsdp" }, - { SYSZ_INS_VSEG, "vseg" }, - { SYSZ_INS_VSEGB, "vsegb" }, - { SYSZ_INS_VSEGF, "vsegf" }, - { SYSZ_INS_VSEGH, "vsegh" }, - { SYSZ_INS_VSEL, "vsel" }, - { SYSZ_INS_VSF, "vsf" }, - { SYSZ_INS_VSG, "vsg" }, - { SYSZ_INS_VSH, "vsh" }, - { SYSZ_INS_VSL, "vsl" }, - { SYSZ_INS_VSLB, "vslb" }, - { SYSZ_INS_VSLDB, "vsldb" }, - { SYSZ_INS_VSP, "vsp" }, - { SYSZ_INS_VSQ, "vsq" }, - { SYSZ_INS_VSRA, "vsra" }, - { SYSZ_INS_VSRAB, "vsrab" }, - { SYSZ_INS_VSRL, "vsrl" }, - { SYSZ_INS_VSRLB, "vsrlb" }, - { SYSZ_INS_VSRP, "vsrp" }, - { SYSZ_INS_VST, "vst" }, - { SYSZ_INS_VSTEB, "vsteb" }, - { SYSZ_INS_VSTEF, "vstef" }, - { SYSZ_INS_VSTEG, "vsteg" }, - { SYSZ_INS_VSTEH, "vsteh" }, - { SYSZ_INS_VSTL, "vstl" }, - { SYSZ_INS_VSTM, "vstm" }, - { SYSZ_INS_VSTRC, "vstrc" }, - { SYSZ_INS_VSTRCB, "vstrcb" }, - { SYSZ_INS_VSTRCBS, "vstrcbs" }, - { SYSZ_INS_VSTRCF, "vstrcf" }, - { SYSZ_INS_VSTRCFS, "vstrcfs" }, - { SYSZ_INS_VSTRCH, "vstrch" }, - { SYSZ_INS_VSTRCHS, "vstrchs" }, - { SYSZ_INS_VSTRCZB, "vstrczb" }, - { SYSZ_INS_VSTRCZBS, "vstrczbs" }, - { SYSZ_INS_VSTRCZF, "vstrczf" }, - { SYSZ_INS_VSTRCZFS, "vstrczfs" }, - { SYSZ_INS_VSTRCZH, "vstrczh" }, - { SYSZ_INS_VSTRCZHS, "vstrczhs" }, - { SYSZ_INS_VSTRL, "vstrl" }, - { SYSZ_INS_VSTRLR, "vstrlr" }, - { SYSZ_INS_VSUM, "vsum" }, - { SYSZ_INS_VSUMB, "vsumb" }, - { SYSZ_INS_VSUMG, "vsumg" }, - { SYSZ_INS_VSUMGF, "vsumgf" }, - { SYSZ_INS_VSUMGH, "vsumgh" }, - { SYSZ_INS_VSUMH, "vsumh" }, - { SYSZ_INS_VSUMQ, "vsumq" }, - { SYSZ_INS_VSUMQF, "vsumqf" }, - { SYSZ_INS_VSUMQG, "vsumqg" }, - { SYSZ_INS_VTM, "vtm" }, - { SYSZ_INS_VTP, "vtp" }, - { SYSZ_INS_VUPH, "vuph" }, - { SYSZ_INS_VUPHB, "vuphb" }, - { SYSZ_INS_VUPHF, "vuphf" }, - { SYSZ_INS_VUPHH, "vuphh" }, - { SYSZ_INS_VUPKZ, "vupkz" }, - { SYSZ_INS_VUPL, "vupl" }, - { SYSZ_INS_VUPLB, "vuplb" }, - { SYSZ_INS_VUPLF, "vuplf" }, - { SYSZ_INS_VUPLH, "vuplh" }, - { SYSZ_INS_VUPLHB, "vuplhb" }, - { SYSZ_INS_VUPLHF, "vuplhf" }, - { SYSZ_INS_VUPLHH, "vuplhh" }, - { SYSZ_INS_VUPLHW, "vuplhw" }, - { SYSZ_INS_VUPLL, "vupll" }, - { SYSZ_INS_VUPLLB, "vupllb" }, - { SYSZ_INS_VUPLLF, "vupllf" }, - { SYSZ_INS_VUPLLH, "vupllh" }, - { SYSZ_INS_VX, "vx" }, - { SYSZ_INS_VZERO, "vzero" }, - { SYSZ_INS_WCDGB, "wcdgb" }, - { SYSZ_INS_WCDLGB, "wcdlgb" }, - { SYSZ_INS_WCGDB, "wcgdb" }, - { SYSZ_INS_WCLGDB, "wclgdb" }, - { SYSZ_INS_WFADB, "wfadb" }, - { SYSZ_INS_WFASB, "wfasb" }, - { SYSZ_INS_WFAXB, "wfaxb" }, - { SYSZ_INS_WFC, "wfc" }, - { SYSZ_INS_WFCDB, "wfcdb" }, - { SYSZ_INS_WFCEDB, "wfcedb" }, - { SYSZ_INS_WFCEDBS, "wfcedbs" }, - { SYSZ_INS_WFCESB, "wfcesb" }, - { SYSZ_INS_WFCESBS, "wfcesbs" }, - { SYSZ_INS_WFCEXB, "wfcexb" }, - { SYSZ_INS_WFCEXBS, "wfcexbs" }, - { SYSZ_INS_WFCHDB, "wfchdb" }, - { SYSZ_INS_WFCHDBS, "wfchdbs" }, - { SYSZ_INS_WFCHEDB, "wfchedb" }, - { SYSZ_INS_WFCHEDBS, "wfchedbs" }, - { SYSZ_INS_WFCHESB, "wfchesb" }, - { SYSZ_INS_WFCHESBS, "wfchesbs" }, - { SYSZ_INS_WFCHEXB, "wfchexb" }, - { SYSZ_INS_WFCHEXBS, "wfchexbs" }, - { SYSZ_INS_WFCHSB, "wfchsb" }, - { SYSZ_INS_WFCHSBS, "wfchsbs" }, - { SYSZ_INS_WFCHXB, "wfchxb" }, - { SYSZ_INS_WFCHXBS, "wfchxbs" }, - { SYSZ_INS_WFCSB, "wfcsb" }, - { SYSZ_INS_WFCXB, "wfcxb" }, - { SYSZ_INS_WFDDB, "wfddb" }, - { SYSZ_INS_WFDSB, "wfdsb" }, - { SYSZ_INS_WFDXB, "wfdxb" }, - { SYSZ_INS_WFIDB, "wfidb" }, - { SYSZ_INS_WFISB, "wfisb" }, - { SYSZ_INS_WFIXB, "wfixb" }, - { SYSZ_INS_WFK, "wfk" }, - { SYSZ_INS_WFKDB, "wfkdb" }, - { SYSZ_INS_WFKEDB, "wfkedb" }, - { SYSZ_INS_WFKEDBS, "wfkedbs" }, - { SYSZ_INS_WFKESB, "wfkesb" }, - { SYSZ_INS_WFKESBS, "wfkesbs" }, - { SYSZ_INS_WFKEXB, "wfkexb" }, - { SYSZ_INS_WFKEXBS, "wfkexbs" }, - { SYSZ_INS_WFKHDB, "wfkhdb" }, - { SYSZ_INS_WFKHDBS, "wfkhdbs" }, - { SYSZ_INS_WFKHEDB, "wfkhedb" }, - { SYSZ_INS_WFKHEDBS, "wfkhedbs" }, - { SYSZ_INS_WFKHESB, "wfkhesb" }, - { SYSZ_INS_WFKHESBS, "wfkhesbs" }, - { SYSZ_INS_WFKHEXB, "wfkhexb" }, - { SYSZ_INS_WFKHEXBS, "wfkhexbs" }, - { SYSZ_INS_WFKHSB, "wfkhsb" }, - { SYSZ_INS_WFKHSBS, "wfkhsbs" }, - { SYSZ_INS_WFKHXB, "wfkhxb" }, - { SYSZ_INS_WFKHXBS, "wfkhxbs" }, - { SYSZ_INS_WFKSB, "wfksb" }, - { SYSZ_INS_WFKXB, "wfkxb" }, - { SYSZ_INS_WFLCDB, "wflcdb" }, - { SYSZ_INS_WFLCSB, "wflcsb" }, - { SYSZ_INS_WFLCXB, "wflcxb" }, - { SYSZ_INS_WFLLD, "wflld" }, - { SYSZ_INS_WFLLS, "wflls" }, - { SYSZ_INS_WFLNDB, "wflndb" }, - { SYSZ_INS_WFLNSB, "wflnsb" }, - { SYSZ_INS_WFLNXB, "wflnxb" }, - { SYSZ_INS_WFLPDB, "wflpdb" }, - { SYSZ_INS_WFLPSB, "wflpsb" }, - { SYSZ_INS_WFLPXB, "wflpxb" }, - { SYSZ_INS_WFLRD, "wflrd" }, - { SYSZ_INS_WFLRX, "wflrx" }, - { SYSZ_INS_WFMADB, "wfmadb" }, - { SYSZ_INS_WFMASB, "wfmasb" }, - { SYSZ_INS_WFMAXB, "wfmaxb" }, - { SYSZ_INS_WFMAXDB, "wfmaxdb" }, - { SYSZ_INS_WFMAXSB, "wfmaxsb" }, - { SYSZ_INS_WFMAXXB, "wfmaxxb" }, - { SYSZ_INS_WFMDB, "wfmdb" }, - { SYSZ_INS_WFMINDB, "wfmindb" }, - { SYSZ_INS_WFMINSB, "wfminsb" }, - { SYSZ_INS_WFMINXB, "wfminxb" }, - { SYSZ_INS_WFMSB, "wfmsb" }, - { SYSZ_INS_WFMSDB, "wfmsdb" }, - { SYSZ_INS_WFMSSB, "wfmssb" }, - { SYSZ_INS_WFMSXB, "wfmsxb" }, - { SYSZ_INS_WFMXB, "wfmxb" }, - { SYSZ_INS_WFNMADB, "wfnmadb" }, - { SYSZ_INS_WFNMASB, "wfnmasb" }, - { SYSZ_INS_WFNMAXB, "wfnmaxb" }, - { SYSZ_INS_WFNMSDB, "wfnmsdb" }, - { SYSZ_INS_WFNMSSB, "wfnmssb" }, - { SYSZ_INS_WFNMSXB, "wfnmsxb" }, - { SYSZ_INS_WFPSODB, "wfpsodb" }, - { SYSZ_INS_WFPSOSB, "wfpsosb" }, - { SYSZ_INS_WFPSOXB, "wfpsoxb" }, - { SYSZ_INS_WFSDB, "wfsdb" }, - { SYSZ_INS_WFSQDB, "wfsqdb" }, - { SYSZ_INS_WFSQSB, "wfsqsb" }, - { SYSZ_INS_WFSQXB, "wfsqxb" }, - { SYSZ_INS_WFSSB, "wfssb" }, - { SYSZ_INS_WFSXB, "wfsxb" }, - { SYSZ_INS_WFTCIDB, "wftcidb" }, - { SYSZ_INS_WFTCISB, "wftcisb" }, - { SYSZ_INS_WFTCIXB, "wftcixb" }, - { SYSZ_INS_WLDEB, "wldeb" }, - { SYSZ_INS_WLEDB, "wledb" }, - { SYSZ_INS_XSCH, "xsch" }, - { SYSZ_INS_ZAP, "zap" }, +{SYSZ_INS_A, "a"}, {SYSZ_INS_ADB, "adb"}, {SYSZ_INS_ADBR, "adbr"}, + {SYSZ_INS_AEB, "aeb"}, {SYSZ_INS_AEBR, "aebr"}, {SYSZ_INS_AFI, "afi"}, + {SYSZ_INS_AG, "ag"}, {SYSZ_INS_AGF, "agf"}, {SYSZ_INS_AGFI, "agfi"}, + {SYSZ_INS_AGFR, "agfr"}, {SYSZ_INS_AGHI, "aghi"}, {SYSZ_INS_AGHIK, "aghik"}, + {SYSZ_INS_AGR, "agr"}, {SYSZ_INS_AGRK, "agrk"}, {SYSZ_INS_AGSI, "agsi"}, + {SYSZ_INS_AH, "ah"}, {SYSZ_INS_AHI, "ahi"}, {SYSZ_INS_AHIK, "ahik"}, + {SYSZ_INS_AHY, "ahy"}, {SYSZ_INS_AIH, "aih"}, {SYSZ_INS_AL, "al"}, + {SYSZ_INS_ALC, "alc"}, {SYSZ_INS_ALCG, "alcg"}, {SYSZ_INS_ALCGR, "alcgr"}, + {SYSZ_INS_ALCR, "alcr"}, {SYSZ_INS_ALFI, "alfi"}, {SYSZ_INS_ALG, "alg"}, + {SYSZ_INS_ALGF, "algf"}, {SYSZ_INS_ALGFI, "algfi"}, + {SYSZ_INS_ALGFR, "algfr"}, {SYSZ_INS_ALGHSIK, "alghsik"}, + {SYSZ_INS_ALGR, "algr"}, {SYSZ_INS_ALGRK, "algrk"}, + {SYSZ_INS_ALHSIK, "alhsik"}, {SYSZ_INS_ALR, "alr"}, {SYSZ_INS_ALRK, "alrk"}, + {SYSZ_INS_ALY, "aly"}, {SYSZ_INS_AR, "ar"}, {SYSZ_INS_ARK, "ark"}, + {SYSZ_INS_ASI, "asi"}, {SYSZ_INS_AXBR, "axbr"}, {SYSZ_INS_AY, "ay"}, + {SYSZ_INS_BCR, "bcr"}, {SYSZ_INS_BRC, "brc"}, {SYSZ_INS_BRCL, "brcl"}, + {SYSZ_INS_CGIJ, "cgij"}, {SYSZ_INS_CGRJ, "cgrj"}, {SYSZ_INS_CIJ, "cij"}, + {SYSZ_INS_CLGIJ, "clgij"}, {SYSZ_INS_CLGRJ, "clgrj"}, + {SYSZ_INS_CLIJ, "clij"}, {SYSZ_INS_CLRJ, "clrj"}, {SYSZ_INS_CRJ, "crj"}, + {SYSZ_INS_BER, "ber"}, {SYSZ_INS_JE, "je"}, {SYSZ_INS_JGE, "jge"}, + {SYSZ_INS_LOCE, "loce"}, {SYSZ_INS_LOCGE, "locge"}, + {SYSZ_INS_LOCGRE, "locgre"}, {SYSZ_INS_LOCRE, "locre"}, + {SYSZ_INS_STOCE, "stoce"}, {SYSZ_INS_STOCGE, "stocge"}, + {SYSZ_INS_BHR, "bhr"}, {SYSZ_INS_BHER, "bher"}, {SYSZ_INS_JHE, "jhe"}, + {SYSZ_INS_JGHE, "jghe"}, {SYSZ_INS_LOCHE, "loche"}, + {SYSZ_INS_LOCGHE, "locghe"}, {SYSZ_INS_LOCGRHE, "locgrhe"}, + {SYSZ_INS_LOCRHE, "locrhe"}, {SYSZ_INS_STOCHE, "stoche"}, + {SYSZ_INS_STOCGHE, "stocghe"}, {SYSZ_INS_JH, "jh"}, {SYSZ_INS_JGH, "jgh"}, + {SYSZ_INS_LOCH, "loch"}, {SYSZ_INS_LOCGH, "locgh"}, + {SYSZ_INS_LOCGRH, "locgrh"}, {SYSZ_INS_LOCRH, "locrh"}, + {SYSZ_INS_STOCH, "stoch"}, {SYSZ_INS_STOCGH, "stocgh"}, + {SYSZ_INS_CGIJNLH, "cgijnlh"}, {SYSZ_INS_CGRJNLH, "cgrjnlh"}, + {SYSZ_INS_CIJNLH, "cijnlh"}, {SYSZ_INS_CLGIJNLH, "clgijnlh"}, + {SYSZ_INS_CLGRJNLH, "clgrjnlh"}, {SYSZ_INS_CLIJNLH, "clijnlh"}, + {SYSZ_INS_CLRJNLH, "clrjnlh"}, {SYSZ_INS_CRJNLH, "crjnlh"}, + {SYSZ_INS_CGIJE, "cgije"}, {SYSZ_INS_CGRJE, "cgrje"}, + {SYSZ_INS_CIJE, "cije"}, {SYSZ_INS_CLGIJE, "clgije"}, + {SYSZ_INS_CLGRJE, "clgrje"}, {SYSZ_INS_CLIJE, "clije"}, + {SYSZ_INS_CLRJE, "clrje"}, {SYSZ_INS_CRJE, "crje"}, + {SYSZ_INS_CGIJNLE, "cgijnle"}, {SYSZ_INS_CGRJNLE, "cgrjnle"}, + {SYSZ_INS_CIJNLE, "cijnle"}, {SYSZ_INS_CLGIJNLE, "clgijnle"}, + {SYSZ_INS_CLGRJNLE, "clgrjnle"}, {SYSZ_INS_CLIJNLE, "clijnle"}, + {SYSZ_INS_CLRJNLE, "clrjnle"}, {SYSZ_INS_CRJNLE, "crjnle"}, + {SYSZ_INS_CGIJH, "cgijh"}, {SYSZ_INS_CGRJH, "cgrjh"}, + {SYSZ_INS_CIJH, "cijh"}, {SYSZ_INS_CLGIJH, "clgijh"}, + {SYSZ_INS_CLGRJH, "clgrjh"}, {SYSZ_INS_CLIJH, "clijh"}, + {SYSZ_INS_CLRJH, "clrjh"}, {SYSZ_INS_CRJH, "crjh"}, + {SYSZ_INS_CGIJNL, "cgijnl"}, {SYSZ_INS_CGRJNL, "cgrjnl"}, + {SYSZ_INS_CIJNL, "cijnl"}, {SYSZ_INS_CLGIJNL, "clgijnl"}, + {SYSZ_INS_CLGRJNL, "clgrjnl"}, {SYSZ_INS_CLIJNL, "clijnl"}, + {SYSZ_INS_CLRJNL, "clrjnl"}, {SYSZ_INS_CRJNL, "crjnl"}, + {SYSZ_INS_CGIJHE, "cgijhe"}, {SYSZ_INS_CGRJHE, "cgrjhe"}, + {SYSZ_INS_CIJHE, "cijhe"}, {SYSZ_INS_CLGIJHE, "clgijhe"}, + {SYSZ_INS_CLGRJHE, "clgrjhe"}, {SYSZ_INS_CLIJHE, "clijhe"}, + {SYSZ_INS_CLRJHE, "clrjhe"}, {SYSZ_INS_CRJHE, "crjhe"}, + {SYSZ_INS_CGIJNHE, "cgijnhe"}, {SYSZ_INS_CGRJNHE, "cgrjnhe"}, + {SYSZ_INS_CIJNHE, "cijnhe"}, {SYSZ_INS_CLGIJNHE, "clgijnhe"}, + {SYSZ_INS_CLGRJNHE, "clgrjnhe"}, {SYSZ_INS_CLIJNHE, "clijnhe"}, + {SYSZ_INS_CLRJNHE, "clrjnhe"}, {SYSZ_INS_CRJNHE, "crjnhe"}, + {SYSZ_INS_CGIJL, "cgijl"}, {SYSZ_INS_CGRJL, "cgrjl"}, + {SYSZ_INS_CIJL, "cijl"}, {SYSZ_INS_CLGIJL, "clgijl"}, + {SYSZ_INS_CLGRJL, "clgrjl"}, {SYSZ_INS_CLIJL, "clijl"}, + {SYSZ_INS_CLRJL, "clrjl"}, {SYSZ_INS_CRJL, "crjl"}, + {SYSZ_INS_CGIJNH, "cgijnh"}, {SYSZ_INS_CGRJNH, "cgrjnh"}, + {SYSZ_INS_CIJNH, "cijnh"}, {SYSZ_INS_CLGIJNH, "clgijnh"}, + {SYSZ_INS_CLGRJNH, "clgrjnh"}, {SYSZ_INS_CLIJNH, "clijnh"}, + {SYSZ_INS_CLRJNH, "clrjnh"}, {SYSZ_INS_CRJNH, "crjnh"}, + {SYSZ_INS_CGIJLE, "cgijle"}, {SYSZ_INS_CGRJLE, "cgrjle"}, + {SYSZ_INS_CIJLE, "cijle"}, {SYSZ_INS_CLGIJLE, "clgijle"}, + {SYSZ_INS_CLGRJLE, "clgrjle"}, {SYSZ_INS_CLIJLE, "clijle"}, + {SYSZ_INS_CLRJLE, "clrjle"}, {SYSZ_INS_CRJLE, "crjle"}, + {SYSZ_INS_CGIJNE, "cgijne"}, {SYSZ_INS_CGRJNE, "cgrjne"}, + {SYSZ_INS_CIJNE, "cijne"}, {SYSZ_INS_CLGIJNE, "clgijne"}, + {SYSZ_INS_CLGRJNE, "clgrjne"}, {SYSZ_INS_CLIJNE, "clijne"}, + {SYSZ_INS_CLRJNE, "clrjne"}, {SYSZ_INS_CRJNE, "crjne"}, + {SYSZ_INS_CGIJLH, "cgijlh"}, {SYSZ_INS_CGRJLH, "cgrjlh"}, + {SYSZ_INS_CIJLH, "cijlh"}, {SYSZ_INS_CLGIJLH, "clgijlh"}, + {SYSZ_INS_CLGRJLH, "clgrjlh"}, {SYSZ_INS_CLIJLH, "clijlh"}, + {SYSZ_INS_CLRJLH, "clrjlh"}, {SYSZ_INS_CRJLH, "crjlh"}, + {SYSZ_INS_BLR, "blr"}, {SYSZ_INS_BLER, "bler"}, {SYSZ_INS_JLE, "jle"}, + {SYSZ_INS_JGLE, "jgle"}, {SYSZ_INS_LOCLE, "locle"}, + {SYSZ_INS_LOCGLE, "locgle"}, {SYSZ_INS_LOCGRLE, "locgrle"}, + {SYSZ_INS_LOCRLE, "locrle"}, {SYSZ_INS_STOCLE, "stocle"}, + {SYSZ_INS_STOCGLE, "stocgle"}, {SYSZ_INS_BLHR, "blhr"}, + {SYSZ_INS_JLH, "jlh"}, {SYSZ_INS_JGLH, "jglh"}, {SYSZ_INS_LOCLH, "loclh"}, + {SYSZ_INS_LOCGLH, "locglh"}, {SYSZ_INS_LOCGRLH, "locgrlh"}, + {SYSZ_INS_LOCRLH, "locrlh"}, {SYSZ_INS_STOCLH, "stoclh"}, + {SYSZ_INS_STOCGLH, "stocglh"}, {SYSZ_INS_JL, "jl"}, {SYSZ_INS_JGL, "jgl"}, + {SYSZ_INS_LOCL, "locl"}, {SYSZ_INS_LOCGL, "locgl"}, + {SYSZ_INS_LOCGRL, "locgrl"}, {SYSZ_INS_LOCRL, "locrl"}, + {SYSZ_INS_LOC, "loc"}, {SYSZ_INS_LOCG, "locg"}, {SYSZ_INS_LOCGR, "locgr"}, + {SYSZ_INS_LOCR, "locr"}, {SYSZ_INS_STOCL, "stocl"}, + {SYSZ_INS_STOCGL, "stocgl"}, {SYSZ_INS_BNER, "bner"}, {SYSZ_INS_JNE, "jne"}, + {SYSZ_INS_JGNE, "jgne"}, {SYSZ_INS_LOCNE, "locne"}, + {SYSZ_INS_LOCGNE, "locgne"}, {SYSZ_INS_LOCGRNE, "locgrne"}, + {SYSZ_INS_LOCRNE, "locrne"}, {SYSZ_INS_STOCNE, "stocne"}, + {SYSZ_INS_STOCGNE, "stocgne"}, {SYSZ_INS_BNHR, "bnhr"}, + {SYSZ_INS_BNHER, "bnher"}, {SYSZ_INS_JNHE, "jnhe"}, + {SYSZ_INS_JGNHE, "jgnhe"}, {SYSZ_INS_LOCNHE, "locnhe"}, + {SYSZ_INS_LOCGNHE, "locgnhe"}, {SYSZ_INS_LOCGRNHE, "locgrnhe"}, + {SYSZ_INS_LOCRNHE, "locrnhe"}, {SYSZ_INS_STOCNHE, "stocnhe"}, + {SYSZ_INS_STOCGNHE, "stocgnhe"}, {SYSZ_INS_JNH, "jnh"}, + {SYSZ_INS_JGNH, "jgnh"}, {SYSZ_INS_LOCNH, "locnh"}, + {SYSZ_INS_LOCGNH, "locgnh"}, {SYSZ_INS_LOCGRNH, "locgrnh"}, + {SYSZ_INS_LOCRNH, "locrnh"}, {SYSZ_INS_STOCNH, "stocnh"}, + {SYSZ_INS_STOCGNH, "stocgnh"}, {SYSZ_INS_BNLR, "bnlr"}, + {SYSZ_INS_BNLER, "bnler"}, {SYSZ_INS_JNLE, "jnle"}, + {SYSZ_INS_JGNLE, "jgnle"}, {SYSZ_INS_LOCNLE, "locnle"}, + {SYSZ_INS_LOCGNLE, "locgnle"}, {SYSZ_INS_LOCGRNLE, "locgrnle"}, + {SYSZ_INS_LOCRNLE, "locrnle"}, {SYSZ_INS_STOCNLE, "stocnle"}, + {SYSZ_INS_STOCGNLE, "stocgnle"}, {SYSZ_INS_BNLHR, "bnlhr"}, + {SYSZ_INS_JNLH, "jnlh"}, {SYSZ_INS_JGNLH, "jgnlh"}, + {SYSZ_INS_LOCNLH, "locnlh"}, {SYSZ_INS_LOCGNLH, "locgnlh"}, + {SYSZ_INS_LOCGRNLH, "locgrnlh"}, {SYSZ_INS_LOCRNLH, "locrnlh"}, + {SYSZ_INS_STOCNLH, "stocnlh"}, {SYSZ_INS_STOCGNLH, "stocgnlh"}, + {SYSZ_INS_JNL, "jnl"}, {SYSZ_INS_JGNL, "jgnl"}, {SYSZ_INS_LOCNL, "locnl"}, + {SYSZ_INS_LOCGNL, "locgnl"}, {SYSZ_INS_LOCGRNL, "locgrnl"}, + {SYSZ_INS_LOCRNL, "locrnl"}, {SYSZ_INS_STOCNL, "stocnl"}, + {SYSZ_INS_STOCGNL, "stocgnl"}, {SYSZ_INS_BNOR, "bnor"}, + {SYSZ_INS_JNO, "jno"}, {SYSZ_INS_JGNO, "jgno"}, {SYSZ_INS_LOCNO, "locno"}, + {SYSZ_INS_LOCGNO, "locgno"}, {SYSZ_INS_LOCGRNO, "locgrno"}, + {SYSZ_INS_LOCRNO, "locrno"}, {SYSZ_INS_STOCNO, "stocno"}, + {SYSZ_INS_STOCGNO, "stocgno"}, {SYSZ_INS_BOR, "bor"}, {SYSZ_INS_JO, "jo"}, + {SYSZ_INS_JGO, "jgo"}, {SYSZ_INS_LOCO, "loco"}, {SYSZ_INS_LOCGO, "locgo"}, + {SYSZ_INS_LOCGRO, "locgro"}, {SYSZ_INS_LOCRO, "locro"}, + {SYSZ_INS_STOCO, "stoco"}, {SYSZ_INS_STOCGO, "stocgo"}, + {SYSZ_INS_STOC, "stoc"}, {SYSZ_INS_STOCG, "stocg"}, {SYSZ_INS_BASR, "basr"}, + {SYSZ_INS_BR, "br"}, {SYSZ_INS_BRAS, "bras"}, {SYSZ_INS_BRASL, "brasl"}, + {SYSZ_INS_J, "j"}, {SYSZ_INS_JG, "jg"}, {SYSZ_INS_BRCT, "brct"}, + {SYSZ_INS_BRCTG, "brctg"}, {SYSZ_INS_C, "c"}, {SYSZ_INS_CDB, "cdb"}, + {SYSZ_INS_CDBR, "cdbr"}, {SYSZ_INS_CDFBR, "cdfbr"}, + {SYSZ_INS_CDGBR, "cdgbr"}, {SYSZ_INS_CDLFBR, "cdlfbr"}, + {SYSZ_INS_CDLGBR, "cdlgbr"}, {SYSZ_INS_CEB, "ceb"}, {SYSZ_INS_CEBR, "cebr"}, + {SYSZ_INS_CEFBR, "cefbr"}, {SYSZ_INS_CEGBR, "cegbr"}, + {SYSZ_INS_CELFBR, "celfbr"}, {SYSZ_INS_CELGBR, "celgbr"}, + {SYSZ_INS_CFDBR, "cfdbr"}, {SYSZ_INS_CFEBR, "cfebr"}, {SYSZ_INS_CFI, "cfi"}, + {SYSZ_INS_CFXBR, "cfxbr"}, {SYSZ_INS_CG, "cg"}, {SYSZ_INS_CGDBR, "cgdbr"}, + {SYSZ_INS_CGEBR, "cgebr"}, {SYSZ_INS_CGF, "cgf"}, {SYSZ_INS_CGFI, "cgfi"}, + {SYSZ_INS_CGFR, "cgfr"}, {SYSZ_INS_CGFRL, "cgfrl"}, {SYSZ_INS_CGH, "cgh"}, + {SYSZ_INS_CGHI, "cghi"}, {SYSZ_INS_CGHRL, "cghrl"}, + {SYSZ_INS_CGHSI, "cghsi"}, {SYSZ_INS_CGR, "cgr"}, {SYSZ_INS_CGRL, "cgrl"}, + {SYSZ_INS_CGXBR, "cgxbr"}, {SYSZ_INS_CH, "ch"}, {SYSZ_INS_CHF, "chf"}, + {SYSZ_INS_CHHSI, "chhsi"}, {SYSZ_INS_CHI, "chi"}, {SYSZ_INS_CHRL, "chrl"}, + {SYSZ_INS_CHSI, "chsi"}, {SYSZ_INS_CHY, "chy"}, {SYSZ_INS_CIH, "cih"}, + {SYSZ_INS_CL, "cl"}, {SYSZ_INS_CLC, "clc"}, {SYSZ_INS_CLFDBR, "clfdbr"}, + {SYSZ_INS_CLFEBR, "clfebr"}, {SYSZ_INS_CLFHSI, "clfhsi"}, + {SYSZ_INS_CLFI, "clfi"}, {SYSZ_INS_CLFXBR, "clfxbr"}, {SYSZ_INS_CLG, "clg"}, + {SYSZ_INS_CLGDBR, "clgdbr"}, {SYSZ_INS_CLGEBR, "clgebr"}, + {SYSZ_INS_CLGF, "clgf"}, {SYSZ_INS_CLGFI, "clgfi"}, + {SYSZ_INS_CLGFR, "clgfr"}, {SYSZ_INS_CLGFRL, "clgfrl"}, + {SYSZ_INS_CLGHRL, "clghrl"}, {SYSZ_INS_CLGHSI, "clghsi"}, + {SYSZ_INS_CLGR, "clgr"}, {SYSZ_INS_CLGRL, "clgrl"}, + {SYSZ_INS_CLGXBR, "clgxbr"}, {SYSZ_INS_CLHF, "clhf"}, + {SYSZ_INS_CLHHSI, "clhhsi"}, {SYSZ_INS_CLHRL, "clhrl"}, + {SYSZ_INS_CLI, "cli"}, {SYSZ_INS_CLIH, "clih"}, {SYSZ_INS_CLIY, "cliy"}, + {SYSZ_INS_CLR, "clr"}, {SYSZ_INS_CLRL, "clrl"}, {SYSZ_INS_CLST, "clst"}, + {SYSZ_INS_CLY, "cly"}, {SYSZ_INS_CPSDR, "cpsdr"}, {SYSZ_INS_CR, "cr"}, + {SYSZ_INS_CRL, "crl"}, {SYSZ_INS_CS, "cs"}, {SYSZ_INS_CSG, "csg"}, + {SYSZ_INS_CSY, "csy"}, {SYSZ_INS_CXBR, "cxbr"}, {SYSZ_INS_CXFBR, "cxfbr"}, + {SYSZ_INS_CXGBR, "cxgbr"}, {SYSZ_INS_CXLFBR, "cxlfbr"}, + {SYSZ_INS_CXLGBR, "cxlgbr"}, {SYSZ_INS_CY, "cy"}, {SYSZ_INS_DDB, "ddb"}, + {SYSZ_INS_DDBR, "ddbr"}, {SYSZ_INS_DEB, "deb"}, {SYSZ_INS_DEBR, "debr"}, + {SYSZ_INS_DL, "dl"}, {SYSZ_INS_DLG, "dlg"}, {SYSZ_INS_DLGR, "dlgr"}, + {SYSZ_INS_DLR, "dlr"}, {SYSZ_INS_DSG, "dsg"}, {SYSZ_INS_DSGF, "dsgf"}, + {SYSZ_INS_DSGFR, "dsgfr"}, {SYSZ_INS_DSGR, "dsgr"}, {SYSZ_INS_DXBR, "dxbr"}, + {SYSZ_INS_EAR, "ear"}, {SYSZ_INS_FIDBR, "fidbr"}, + {SYSZ_INS_FIDBRA, "fidbra"}, {SYSZ_INS_FIEBR, "fiebr"}, + {SYSZ_INS_FIEBRA, "fiebra"}, {SYSZ_INS_FIXBR, "fixbr"}, + {SYSZ_INS_FIXBRA, "fixbra"}, {SYSZ_INS_FLOGR, "flogr"}, {SYSZ_INS_IC, "ic"}, + {SYSZ_INS_ICY, "icy"}, {SYSZ_INS_IIHF, "iihf"}, {SYSZ_INS_IIHH, "iihh"}, + {SYSZ_INS_IIHL, "iihl"}, {SYSZ_INS_IILF, "iilf"}, {SYSZ_INS_IILH, "iilh"}, + {SYSZ_INS_IILL, "iill"}, {SYSZ_INS_IPM, "ipm"}, {SYSZ_INS_L, "l"}, + {SYSZ_INS_LA, "la"}, {SYSZ_INS_LAA, "laa"}, {SYSZ_INS_LAAG, "laag"}, + {SYSZ_INS_LAAL, "laal"}, {SYSZ_INS_LAALG, "laalg"}, {SYSZ_INS_LAN, "lan"}, + {SYSZ_INS_LANG, "lang"}, {SYSZ_INS_LAO, "lao"}, {SYSZ_INS_LAOG, "laog"}, + {SYSZ_INS_LARL, "larl"}, {SYSZ_INS_LAX, "lax"}, {SYSZ_INS_LAXG, "laxg"}, + {SYSZ_INS_LAY, "lay"}, {SYSZ_INS_LB, "lb"}, {SYSZ_INS_LBH, "lbh"}, + {SYSZ_INS_LBR, "lbr"}, {SYSZ_INS_LCDBR, "lcdbr"}, {SYSZ_INS_LCEBR, "lcebr"}, + {SYSZ_INS_LCGFR, "lcgfr"}, {SYSZ_INS_LCGR, "lcgr"}, {SYSZ_INS_LCR, "lcr"}, + {SYSZ_INS_LCXBR, "lcxbr"}, {SYSZ_INS_LD, "ld"}, {SYSZ_INS_LDEB, "ldeb"}, + {SYSZ_INS_LDEBR, "ldebr"}, {SYSZ_INS_LDGR, "ldgr"}, {SYSZ_INS_LDR, "ldr"}, + {SYSZ_INS_LDXBR, "ldxbr"}, {SYSZ_INS_LDXBRA, "ldxbra"}, + {SYSZ_INS_LDY, "ldy"}, {SYSZ_INS_LE, "le"}, {SYSZ_INS_LEDBR, "ledbr"}, + {SYSZ_INS_LEDBRA, "ledbra"}, {SYSZ_INS_LER, "ler"}, + {SYSZ_INS_LEXBR, "lexbr"}, {SYSZ_INS_LEXBRA, "lexbra"}, + {SYSZ_INS_LEY, "ley"}, {SYSZ_INS_LFH, "lfh"}, {SYSZ_INS_LG, "lg"}, + {SYSZ_INS_LGB, "lgb"}, {SYSZ_INS_LGBR, "lgbr"}, {SYSZ_INS_LGDR, "lgdr"}, + {SYSZ_INS_LGF, "lgf"}, {SYSZ_INS_LGFI, "lgfi"}, {SYSZ_INS_LGFR, "lgfr"}, + {SYSZ_INS_LGFRL, "lgfrl"}, {SYSZ_INS_LGH, "lgh"}, {SYSZ_INS_LGHI, "lghi"}, + {SYSZ_INS_LGHR, "lghr"}, {SYSZ_INS_LGHRL, "lghrl"}, {SYSZ_INS_LGR, "lgr"}, + {SYSZ_INS_LGRL, "lgrl"}, {SYSZ_INS_LH, "lh"}, {SYSZ_INS_LHH, "lhh"}, + {SYSZ_INS_LHI, "lhi"}, {SYSZ_INS_LHR, "lhr"}, {SYSZ_INS_LHRL, "lhrl"}, + {SYSZ_INS_LHY, "lhy"}, {SYSZ_INS_LLC, "llc"}, {SYSZ_INS_LLCH, "llch"}, + {SYSZ_INS_LLCR, "llcr"}, {SYSZ_INS_LLGC, "llgc"}, {SYSZ_INS_LLGCR, "llgcr"}, + {SYSZ_INS_LLGF, "llgf"}, {SYSZ_INS_LLGFR, "llgfr"}, + {SYSZ_INS_LLGFRL, "llgfrl"}, {SYSZ_INS_LLGH, "llgh"}, + {SYSZ_INS_LLGHR, "llghr"}, {SYSZ_INS_LLGHRL, "llghrl"}, + {SYSZ_INS_LLH, "llh"}, {SYSZ_INS_LLHH, "llhh"}, {SYSZ_INS_LLHR, "llhr"}, + {SYSZ_INS_LLHRL, "llhrl"}, {SYSZ_INS_LLIHF, "llihf"}, + {SYSZ_INS_LLIHH, "llihh"}, {SYSZ_INS_LLIHL, "llihl"}, + {SYSZ_INS_LLILF, "llilf"}, {SYSZ_INS_LLILH, "llilh"}, + {SYSZ_INS_LLILL, "llill"}, {SYSZ_INS_LMG, "lmg"}, {SYSZ_INS_LNDBR, "lndbr"}, + {SYSZ_INS_LNEBR, "lnebr"}, {SYSZ_INS_LNGFR, "lngfr"}, + {SYSZ_INS_LNGR, "lngr"}, {SYSZ_INS_LNR, "lnr"}, {SYSZ_INS_LNXBR, "lnxbr"}, + {SYSZ_INS_LPDBR, "lpdbr"}, {SYSZ_INS_LPEBR, "lpebr"}, + {SYSZ_INS_LPGFR, "lpgfr"}, {SYSZ_INS_LPGR, "lpgr"}, {SYSZ_INS_LPR, "lpr"}, + {SYSZ_INS_LPXBR, "lpxbr"}, {SYSZ_INS_LR, "lr"}, {SYSZ_INS_LRL, "lrl"}, + {SYSZ_INS_LRV, "lrv"}, {SYSZ_INS_LRVG, "lrvg"}, {SYSZ_INS_LRVGR, "lrvgr"}, + {SYSZ_INS_LRVR, "lrvr"}, {SYSZ_INS_LT, "lt"}, {SYSZ_INS_LTDBR, "ltdbr"}, + {SYSZ_INS_LTEBR, "ltebr"}, {SYSZ_INS_LTG, "ltg"}, {SYSZ_INS_LTGF, "ltgf"}, + {SYSZ_INS_LTGFR, "ltgfr"}, {SYSZ_INS_LTGR, "ltgr"}, {SYSZ_INS_LTR, "ltr"}, + {SYSZ_INS_LTXBR, "ltxbr"}, {SYSZ_INS_LXDB, "lxdb"}, + {SYSZ_INS_LXDBR, "lxdbr"}, {SYSZ_INS_LXEB, "lxeb"}, + {SYSZ_INS_LXEBR, "lxebr"}, {SYSZ_INS_LXR, "lxr"}, {SYSZ_INS_LY, "ly"}, + {SYSZ_INS_LZDR, "lzdr"}, {SYSZ_INS_LZER, "lzer"}, {SYSZ_INS_LZXR, "lzxr"}, + {SYSZ_INS_MADB, "madb"}, {SYSZ_INS_MADBR, "madbr"}, {SYSZ_INS_MAEB, "maeb"}, + {SYSZ_INS_MAEBR, "maebr"}, {SYSZ_INS_MDB, "mdb"}, {SYSZ_INS_MDBR, "mdbr"}, + {SYSZ_INS_MDEB, "mdeb"}, {SYSZ_INS_MDEBR, "mdebr"}, {SYSZ_INS_MEEB, "meeb"}, + {SYSZ_INS_MEEBR, "meebr"}, {SYSZ_INS_MGHI, "mghi"}, {SYSZ_INS_MH, "mh"}, + {SYSZ_INS_MHI, "mhi"}, {SYSZ_INS_MHY, "mhy"}, {SYSZ_INS_MLG, "mlg"}, + {SYSZ_INS_MLGR, "mlgr"}, {SYSZ_INS_MS, "ms"}, {SYSZ_INS_MSDB, "msdb"}, + {SYSZ_INS_MSDBR, "msdbr"}, {SYSZ_INS_MSEB, "mseb"}, + {SYSZ_INS_MSEBR, "msebr"}, {SYSZ_INS_MSFI, "msfi"}, {SYSZ_INS_MSG, "msg"}, + {SYSZ_INS_MSGF, "msgf"}, {SYSZ_INS_MSGFI, "msgfi"}, + {SYSZ_INS_MSGFR, "msgfr"}, {SYSZ_INS_MSGR, "msgr"}, {SYSZ_INS_MSR, "msr"}, + {SYSZ_INS_MSY, "msy"}, {SYSZ_INS_MVC, "mvc"}, {SYSZ_INS_MVGHI, "mvghi"}, + {SYSZ_INS_MVHHI, "mvhhi"}, {SYSZ_INS_MVHI, "mvhi"}, {SYSZ_INS_MVI, "mvi"}, + {SYSZ_INS_MVIY, "mviy"}, {SYSZ_INS_MVST, "mvst"}, {SYSZ_INS_MXBR, "mxbr"}, + {SYSZ_INS_MXDB, "mxdb"}, {SYSZ_INS_MXDBR, "mxdbr"}, {SYSZ_INS_N, "n"}, + {SYSZ_INS_NC, "nc"}, {SYSZ_INS_NG, "ng"}, {SYSZ_INS_NGR, "ngr"}, + {SYSZ_INS_NGRK, "ngrk"}, {SYSZ_INS_NI, "ni"}, {SYSZ_INS_NIHF, "nihf"}, + {SYSZ_INS_NIHH, "nihh"}, {SYSZ_INS_NIHL, "nihl"}, {SYSZ_INS_NILF, "nilf"}, + {SYSZ_INS_NILH, "nilh"}, {SYSZ_INS_NILL, "nill"}, {SYSZ_INS_NIY, "niy"}, + {SYSZ_INS_NR, "nr"}, {SYSZ_INS_NRK, "nrk"}, {SYSZ_INS_NY, "ny"}, + {SYSZ_INS_O, "o"}, {SYSZ_INS_OC, "oc"}, {SYSZ_INS_OG, "og"}, + {SYSZ_INS_OGR, "ogr"}, {SYSZ_INS_OGRK, "ogrk"}, {SYSZ_INS_OI, "oi"}, + {SYSZ_INS_OIHF, "oihf"}, {SYSZ_INS_OIHH, "oihh"}, {SYSZ_INS_OIHL, "oihl"}, + {SYSZ_INS_OILF, "oilf"}, {SYSZ_INS_OILH, "oilh"}, {SYSZ_INS_OILL, "oill"}, + {SYSZ_INS_OIY, "oiy"}, {SYSZ_INS_OR, "or"}, {SYSZ_INS_ORK, "ork"}, + {SYSZ_INS_OY, "oy"}, {SYSZ_INS_PFD, "pfd"}, {SYSZ_INS_PFDRL, "pfdrl"}, + {SYSZ_INS_RISBG, "risbg"}, {SYSZ_INS_RISBHG, "risbhg"}, + {SYSZ_INS_RISBLG, "risblg"}, {SYSZ_INS_RLL, "rll"}, {SYSZ_INS_RLLG, "rllg"}, + {SYSZ_INS_RNSBG, "rnsbg"}, {SYSZ_INS_ROSBG, "rosbg"}, + {SYSZ_INS_RXSBG, "rxsbg"}, {SYSZ_INS_S, "s"}, {SYSZ_INS_SDB, "sdb"}, + {SYSZ_INS_SDBR, "sdbr"}, {SYSZ_INS_SEB, "seb"}, {SYSZ_INS_SEBR, "sebr"}, + {SYSZ_INS_SG, "sg"}, {SYSZ_INS_SGF, "sgf"}, {SYSZ_INS_SGFR, "sgfr"}, + {SYSZ_INS_SGR, "sgr"}, {SYSZ_INS_SGRK, "sgrk"}, {SYSZ_INS_SH, "sh"}, + {SYSZ_INS_SHY, "shy"}, {SYSZ_INS_SL, "sl"}, {SYSZ_INS_SLB, "slb"}, + {SYSZ_INS_SLBG, "slbg"}, {SYSZ_INS_SLBR, "slbr"}, {SYSZ_INS_SLFI, "slfi"}, + {SYSZ_INS_SLG, "slg"}, {SYSZ_INS_SLBGR, "slbgr"}, {SYSZ_INS_SLGF, "slgf"}, + {SYSZ_INS_SLGFI, "slgfi"}, {SYSZ_INS_SLGFR, "slgfr"}, + {SYSZ_INS_SLGR, "slgr"}, {SYSZ_INS_SLGRK, "slgrk"}, {SYSZ_INS_SLL, "sll"}, + {SYSZ_INS_SLLG, "sllg"}, {SYSZ_INS_SLLK, "sllk"}, {SYSZ_INS_SLR, "slr"}, + {SYSZ_INS_SLRK, "slrk"}, {SYSZ_INS_SLY, "sly"}, {SYSZ_INS_SQDB, "sqdb"}, + {SYSZ_INS_SQDBR, "sqdbr"}, {SYSZ_INS_SQEB, "sqeb"}, + {SYSZ_INS_SQEBR, "sqebr"}, {SYSZ_INS_SQXBR, "sqxbr"}, {SYSZ_INS_SR, "sr"}, + {SYSZ_INS_SRA, "sra"}, {SYSZ_INS_SRAG, "srag"}, {SYSZ_INS_SRAK, "srak"}, + {SYSZ_INS_SRK, "srk"}, {SYSZ_INS_SRL, "srl"}, {SYSZ_INS_SRLG, "srlg"}, + {SYSZ_INS_SRLK, "srlk"}, {SYSZ_INS_SRST, "srst"}, {SYSZ_INS_ST, "st"}, + {SYSZ_INS_STC, "stc"}, {SYSZ_INS_STCH, "stch"}, {SYSZ_INS_STCY, "stcy"}, + {SYSZ_INS_STD, "std"}, {SYSZ_INS_STDY, "stdy"}, {SYSZ_INS_STE, "ste"}, + {SYSZ_INS_STEY, "stey"}, {SYSZ_INS_STFH, "stfh"}, {SYSZ_INS_STG, "stg"}, + {SYSZ_INS_STGRL, "stgrl"}, {SYSZ_INS_STH, "sth"}, {SYSZ_INS_STHH, "sthh"}, + {SYSZ_INS_STHRL, "sthrl"}, {SYSZ_INS_STHY, "sthy"}, {SYSZ_INS_STMG, "stmg"}, + {SYSZ_INS_STRL, "strl"}, {SYSZ_INS_STRV, "strv"}, {SYSZ_INS_STRVG, "strvg"}, + {SYSZ_INS_STY, "sty"}, {SYSZ_INS_SXBR, "sxbr"}, {SYSZ_INS_SY, "sy"}, + {SYSZ_INS_TM, "tm"}, {SYSZ_INS_TMHH, "tmhh"}, {SYSZ_INS_TMHL, "tmhl"}, + {SYSZ_INS_TMLH, "tmlh"}, {SYSZ_INS_TMLL, "tmll"}, {SYSZ_INS_TMY, "tmy"}, + {SYSZ_INS_X, "x"}, {SYSZ_INS_XC, "xc"}, {SYSZ_INS_XG, "xg"}, + {SYSZ_INS_XGR, "xgr"}, {SYSZ_INS_XGRK, "xgrk"}, {SYSZ_INS_XI, "xi"}, + {SYSZ_INS_XIHF, "xihf"}, {SYSZ_INS_XILF, "xilf"}, {SYSZ_INS_XIY, "xiy"}, + {SYSZ_INS_XR, "xr"}, {SYSZ_INS_XRK, "xrk"}, {SYSZ_INS_XY, "xy"}, + {SYSZ_INS_AD, "ad"}, {SYSZ_INS_ADR, "adr"}, {SYSZ_INS_ADTR, "adtr"}, + {SYSZ_INS_ADTRA, "adtra"}, {SYSZ_INS_AE, "ae"}, {SYSZ_INS_AER, "aer"}, + {SYSZ_INS_AGH, "agh"}, {SYSZ_INS_AHHHR, "ahhhr"}, {SYSZ_INS_AHHLR, "ahhlr"}, + {SYSZ_INS_ALGSI, "algsi"}, {SYSZ_INS_ALHHHR, "alhhhr"}, + {SYSZ_INS_ALHHLR, "alhhlr"}, {SYSZ_INS_ALSI, "alsi"}, + {SYSZ_INS_ALSIH, "alsih"}, {SYSZ_INS_ALSIHN, "alsihn"}, {SYSZ_INS_AP, "ap"}, + {SYSZ_INS_AU, "au"}, {SYSZ_INS_AUR, "aur"}, {SYSZ_INS_AW, "aw"}, + {SYSZ_INS_AWR, "awr"}, {SYSZ_INS_AXR, "axr"}, {SYSZ_INS_AXTR, "axtr"}, + {SYSZ_INS_AXTRA, "axtra"}, {SYSZ_INS_B, "b"}, {SYSZ_INS_BAKR, "bakr"}, + {SYSZ_INS_BAL, "bal"}, {SYSZ_INS_BALR, "balr"}, {SYSZ_INS_BAS, "bas"}, + {SYSZ_INS_BASSM, "bassm"}, {SYSZ_INS_BC, "bc"}, {SYSZ_INS_BCT, "bct"}, + {SYSZ_INS_BCTG, "bctg"}, {SYSZ_INS_BCTGR, "bctgr"}, {SYSZ_INS_BCTR, "bctr"}, + {SYSZ_INS_BE, "be"}, {SYSZ_INS_BH, "bh"}, {SYSZ_INS_BHE, "bhe"}, + {SYSZ_INS_BI, "bi"}, {SYSZ_INS_BIC, "bic"}, {SYSZ_INS_BIE, "bie"}, + {SYSZ_INS_BIH, "bih"}, {SYSZ_INS_BIHE, "bihe"}, {SYSZ_INS_BIL, "bil"}, + {SYSZ_INS_BILE, "bile"}, {SYSZ_INS_BILH, "bilh"}, {SYSZ_INS_BIM, "bim"}, + {SYSZ_INS_BINE, "bine"}, {SYSZ_INS_BINH, "binh"}, {SYSZ_INS_BINHE, "binhe"}, + {SYSZ_INS_BINL, "binl"}, {SYSZ_INS_BINLE, "binle"}, + {SYSZ_INS_BINLH, "binlh"}, {SYSZ_INS_BINM, "binm"}, {SYSZ_INS_BINO, "bino"}, + {SYSZ_INS_BINP, "binp"}, {SYSZ_INS_BINZ, "binz"}, {SYSZ_INS_BIO, "bio"}, + {SYSZ_INS_BIP, "bip"}, {SYSZ_INS_BIZ, "biz"}, {SYSZ_INS_BL, "bl"}, + {SYSZ_INS_BLE, "ble"}, {SYSZ_INS_BLH, "blh"}, {SYSZ_INS_BM, "bm"}, + {SYSZ_INS_BMR, "bmr"}, {SYSZ_INS_BNE, "bne"}, {SYSZ_INS_BNH, "bnh"}, + {SYSZ_INS_BNHE, "bnhe"}, {SYSZ_INS_BNL, "bnl"}, {SYSZ_INS_BNLE, "bnle"}, + {SYSZ_INS_BNLH, "bnlh"}, {SYSZ_INS_BNM, "bnm"}, {SYSZ_INS_BNMR, "bnmr"}, + {SYSZ_INS_BNO, "bno"}, {SYSZ_INS_BNP, "bnp"}, {SYSZ_INS_BNPR, "bnpr"}, + {SYSZ_INS_BNZ, "bnz"}, {SYSZ_INS_BNZR, "bnzr"}, {SYSZ_INS_BO, "bo"}, + {SYSZ_INS_BP, "bp"}, {SYSZ_INS_BPP, "bpp"}, {SYSZ_INS_BPR, "bpr"}, + {SYSZ_INS_BPRP, "bprp"}, {SYSZ_INS_BRCTH, "brcth"}, {SYSZ_INS_BRXH, "brxh"}, + {SYSZ_INS_BRXHG, "brxhg"}, {SYSZ_INS_BRXLE, "brxle"}, + {SYSZ_INS_BRXLG, "brxlg"}, {SYSZ_INS_BSA, "bsa"}, {SYSZ_INS_BSG, "bsg"}, + {SYSZ_INS_BSM, "bsm"}, {SYSZ_INS_BXH, "bxh"}, {SYSZ_INS_BXHG, "bxhg"}, + {SYSZ_INS_BXLE, "bxle"}, {SYSZ_INS_BXLEG, "bxleg"}, {SYSZ_INS_BZ, "bz"}, + {SYSZ_INS_BZR, "bzr"}, {SYSZ_INS_CD, "cd"}, {SYSZ_INS_CDFBRA, "cdfbra"}, + {SYSZ_INS_CDFR, "cdfr"}, {SYSZ_INS_CDFTR, "cdftr"}, + {SYSZ_INS_CDGBRA, "cdgbra"}, {SYSZ_INS_CDGR, "cdgr"}, + {SYSZ_INS_CDGTR, "cdgtr"}, {SYSZ_INS_CDGTRA, "cdgtra"}, + {SYSZ_INS_CDLFTR, "cdlftr"}, {SYSZ_INS_CDLGTR, "cdlgtr"}, + {SYSZ_INS_CDPT, "cdpt"}, {SYSZ_INS_CDR, "cdr"}, {SYSZ_INS_CDS, "cds"}, + {SYSZ_INS_CDSG, "cdsg"}, {SYSZ_INS_CDSTR, "cdstr"}, {SYSZ_INS_CDSY, "cdsy"}, + {SYSZ_INS_CDTR, "cdtr"}, {SYSZ_INS_CDUTR, "cdutr"}, {SYSZ_INS_CDZT, "cdzt"}, + {SYSZ_INS_CE, "ce"}, {SYSZ_INS_CEDTR, "cedtr"}, {SYSZ_INS_CEFBRA, "cefbra"}, + {SYSZ_INS_CEFR, "cefr"}, {SYSZ_INS_CEGBRA, "cegbra"}, + {SYSZ_INS_CEGR, "cegr"}, {SYSZ_INS_CER, "cer"}, {SYSZ_INS_CEXTR, "cextr"}, + {SYSZ_INS_CFC, "cfc"}, {SYSZ_INS_CFDBRA, "cfdbra"}, {SYSZ_INS_CFDR, "cfdr"}, + {SYSZ_INS_CFDTR, "cfdtr"}, {SYSZ_INS_CFEBRA, "cfebra"}, + {SYSZ_INS_CFER, "cfer"}, {SYSZ_INS_CFXBRA, "cfxbra"}, + {SYSZ_INS_CFXR, "cfxr"}, {SYSZ_INS_CFXTR, "cfxtr"}, + {SYSZ_INS_CGDBRA, "cgdbra"}, {SYSZ_INS_CGDR, "cgdr"}, + {SYSZ_INS_CGDTR, "cgdtr"}, {SYSZ_INS_CGDTRA, "cgdtra"}, + {SYSZ_INS_CGEBRA, "cgebra"}, {SYSZ_INS_CGER, "cger"}, + {SYSZ_INS_CGIB, "cgib"}, {SYSZ_INS_CGIBE, "cgibe"}, + {SYSZ_INS_CGIBH, "cgibh"}, {SYSZ_INS_CGIBHE, "cgibhe"}, + {SYSZ_INS_CGIBL, "cgibl"}, {SYSZ_INS_CGIBLE, "cgible"}, + {SYSZ_INS_CGIBLH, "cgiblh"}, {SYSZ_INS_CGIBNE, "cgibne"}, + {SYSZ_INS_CGIBNH, "cgibnh"}, {SYSZ_INS_CGIBNHE, "cgibnhe"}, + {SYSZ_INS_CGIBNL, "cgibnl"}, {SYSZ_INS_CGIBNLE, "cgibnle"}, + {SYSZ_INS_CGIBNLH, "cgibnlh"}, {SYSZ_INS_CGIT, "cgit"}, + {SYSZ_INS_CGITE, "cgite"}, {SYSZ_INS_CGITH, "cgith"}, + {SYSZ_INS_CGITHE, "cgithe"}, {SYSZ_INS_CGITL, "cgitl"}, + {SYSZ_INS_CGITLE, "cgitle"}, {SYSZ_INS_CGITLH, "cgitlh"}, + {SYSZ_INS_CGITNE, "cgitne"}, {SYSZ_INS_CGITNH, "cgitnh"}, + {SYSZ_INS_CGITNHE, "cgitnhe"}, {SYSZ_INS_CGITNL, "cgitnl"}, + {SYSZ_INS_CGITNLE, "cgitnle"}, {SYSZ_INS_CGITNLH, "cgitnlh"}, + {SYSZ_INS_CGRB, "cgrb"}, {SYSZ_INS_CGRBE, "cgrbe"}, + {SYSZ_INS_CGRBH, "cgrbh"}, {SYSZ_INS_CGRBHE, "cgrbhe"}, + {SYSZ_INS_CGRBL, "cgrbl"}, {SYSZ_INS_CGRBLE, "cgrble"}, + {SYSZ_INS_CGRBLH, "cgrblh"}, {SYSZ_INS_CGRBNE, "cgrbne"}, + {SYSZ_INS_CGRBNH, "cgrbnh"}, {SYSZ_INS_CGRBNHE, "cgrbnhe"}, + {SYSZ_INS_CGRBNL, "cgrbnl"}, {SYSZ_INS_CGRBNLE, "cgrbnle"}, + {SYSZ_INS_CGRBNLH, "cgrbnlh"}, {SYSZ_INS_CGRT, "cgrt"}, + {SYSZ_INS_CGRTE, "cgrte"}, {SYSZ_INS_CGRTH, "cgrth"}, + {SYSZ_INS_CGRTHE, "cgrthe"}, {SYSZ_INS_CGRTL, "cgrtl"}, + {SYSZ_INS_CGRTLE, "cgrtle"}, {SYSZ_INS_CGRTLH, "cgrtlh"}, + {SYSZ_INS_CGRTNE, "cgrtne"}, {SYSZ_INS_CGRTNH, "cgrtnh"}, + {SYSZ_INS_CGRTNHE, "cgrtnhe"}, {SYSZ_INS_CGRTNL, "cgrtnl"}, + {SYSZ_INS_CGRTNLE, "cgrtnle"}, {SYSZ_INS_CGRTNLH, "cgrtnlh"}, + {SYSZ_INS_CGXBRA, "cgxbra"}, {SYSZ_INS_CGXR, "cgxr"}, + {SYSZ_INS_CGXTR, "cgxtr"}, {SYSZ_INS_CGXTRA, "cgxtra"}, + {SYSZ_INS_CHHR, "chhr"}, {SYSZ_INS_CHLR, "chlr"}, {SYSZ_INS_CIB, "cib"}, + {SYSZ_INS_CIBE, "cibe"}, {SYSZ_INS_CIBH, "cibh"}, {SYSZ_INS_CIBHE, "cibhe"}, + {SYSZ_INS_CIBL, "cibl"}, {SYSZ_INS_CIBLE, "cible"}, + {SYSZ_INS_CIBLH, "ciblh"}, {SYSZ_INS_CIBNE, "cibne"}, + {SYSZ_INS_CIBNH, "cibnh"}, {SYSZ_INS_CIBNHE, "cibnhe"}, + {SYSZ_INS_CIBNL, "cibnl"}, {SYSZ_INS_CIBNLE, "cibnle"}, + {SYSZ_INS_CIBNLH, "cibnlh"}, {SYSZ_INS_CIT, "cit"}, {SYSZ_INS_CITE, "cite"}, + {SYSZ_INS_CITH, "cith"}, {SYSZ_INS_CITHE, "cithe"}, {SYSZ_INS_CITL, "citl"}, + {SYSZ_INS_CITLE, "citle"}, {SYSZ_INS_CITLH, "citlh"}, + {SYSZ_INS_CITNE, "citne"}, {SYSZ_INS_CITNH, "citnh"}, + {SYSZ_INS_CITNHE, "citnhe"}, {SYSZ_INS_CITNL, "citnl"}, + {SYSZ_INS_CITNLE, "citnle"}, {SYSZ_INS_CITNLH, "citnlh"}, + {SYSZ_INS_CKSM, "cksm"}, {SYSZ_INS_CLCL, "clcl"}, {SYSZ_INS_CLCLE, "clcle"}, + {SYSZ_INS_CLCLU, "clclu"}, {SYSZ_INS_CLFDTR, "clfdtr"}, + {SYSZ_INS_CLFIT, "clfit"}, {SYSZ_INS_CLFITE, "clfite"}, + {SYSZ_INS_CLFITH, "clfith"}, {SYSZ_INS_CLFITHE, "clfithe"}, + {SYSZ_INS_CLFITL, "clfitl"}, {SYSZ_INS_CLFITLE, "clfitle"}, + {SYSZ_INS_CLFITLH, "clfitlh"}, {SYSZ_INS_CLFITNE, "clfitne"}, + {SYSZ_INS_CLFITNH, "clfitnh"}, {SYSZ_INS_CLFITNHE, "clfitnhe"}, + {SYSZ_INS_CLFITNL, "clfitnl"}, {SYSZ_INS_CLFITNLE, "clfitnle"}, + {SYSZ_INS_CLFITNLH, "clfitnlh"}, {SYSZ_INS_CLFXTR, "clfxtr"}, + {SYSZ_INS_CLGDTR, "clgdtr"}, {SYSZ_INS_CLGIB, "clgib"}, + {SYSZ_INS_CLGIBE, "clgibe"}, {SYSZ_INS_CLGIBH, "clgibh"}, + {SYSZ_INS_CLGIBHE, "clgibhe"}, {SYSZ_INS_CLGIBL, "clgibl"}, + {SYSZ_INS_CLGIBLE, "clgible"}, {SYSZ_INS_CLGIBLH, "clgiblh"}, + {SYSZ_INS_CLGIBNE, "clgibne"}, {SYSZ_INS_CLGIBNH, "clgibnh"}, + {SYSZ_INS_CLGIBNHE, "clgibnhe"}, {SYSZ_INS_CLGIBNL, "clgibnl"}, + {SYSZ_INS_CLGIBNLE, "clgibnle"}, {SYSZ_INS_CLGIBNLH, "clgibnlh"}, + {SYSZ_INS_CLGIT, "clgit"}, {SYSZ_INS_CLGITE, "clgite"}, + {SYSZ_INS_CLGITH, "clgith"}, {SYSZ_INS_CLGITHE, "clgithe"}, + {SYSZ_INS_CLGITL, "clgitl"}, {SYSZ_INS_CLGITLE, "clgitle"}, + {SYSZ_INS_CLGITLH, "clgitlh"}, {SYSZ_INS_CLGITNE, "clgitne"}, + {SYSZ_INS_CLGITNH, "clgitnh"}, {SYSZ_INS_CLGITNHE, "clgitnhe"}, + {SYSZ_INS_CLGITNL, "clgitnl"}, {SYSZ_INS_CLGITNLE, "clgitnle"}, + {SYSZ_INS_CLGITNLH, "clgitnlh"}, {SYSZ_INS_CLGRB, "clgrb"}, + {SYSZ_INS_CLGRBE, "clgrbe"}, {SYSZ_INS_CLGRBH, "clgrbh"}, + {SYSZ_INS_CLGRBHE, "clgrbhe"}, {SYSZ_INS_CLGRBL, "clgrbl"}, + {SYSZ_INS_CLGRBLE, "clgrble"}, {SYSZ_INS_CLGRBLH, "clgrblh"}, + {SYSZ_INS_CLGRBNE, "clgrbne"}, {SYSZ_INS_CLGRBNH, "clgrbnh"}, + {SYSZ_INS_CLGRBNHE, "clgrbnhe"}, {SYSZ_INS_CLGRBNL, "clgrbnl"}, + {SYSZ_INS_CLGRBNLE, "clgrbnle"}, {SYSZ_INS_CLGRBNLH, "clgrbnlh"}, + {SYSZ_INS_CLGRT, "clgrt"}, {SYSZ_INS_CLGRTE, "clgrte"}, + {SYSZ_INS_CLGRTH, "clgrth"}, {SYSZ_INS_CLGRTHE, "clgrthe"}, + {SYSZ_INS_CLGRTL, "clgrtl"}, {SYSZ_INS_CLGRTLE, "clgrtle"}, + {SYSZ_INS_CLGRTLH, "clgrtlh"}, {SYSZ_INS_CLGRTNE, "clgrtne"}, + {SYSZ_INS_CLGRTNH, "clgrtnh"}, {SYSZ_INS_CLGRTNHE, "clgrtnhe"}, + {SYSZ_INS_CLGRTNL, "clgrtnl"}, {SYSZ_INS_CLGRTNLE, "clgrtnle"}, + {SYSZ_INS_CLGRTNLH, "clgrtnlh"}, {SYSZ_INS_CLGT, "clgt"}, + {SYSZ_INS_CLGTE, "clgte"}, {SYSZ_INS_CLGTH, "clgth"}, + {SYSZ_INS_CLGTHE, "clgthe"}, {SYSZ_INS_CLGTL, "clgtl"}, + {SYSZ_INS_CLGTLE, "clgtle"}, {SYSZ_INS_CLGTLH, "clgtlh"}, + {SYSZ_INS_CLGTNE, "clgtne"}, {SYSZ_INS_CLGTNH, "clgtnh"}, + {SYSZ_INS_CLGTNHE, "clgtnhe"}, {SYSZ_INS_CLGTNL, "clgtnl"}, + {SYSZ_INS_CLGTNLE, "clgtnle"}, {SYSZ_INS_CLGTNLH, "clgtnlh"}, + {SYSZ_INS_CLGXTR, "clgxtr"}, {SYSZ_INS_CLHHR, "clhhr"}, + {SYSZ_INS_CLHLR, "clhlr"}, {SYSZ_INS_CLIB, "clib"}, + {SYSZ_INS_CLIBE, "clibe"}, {SYSZ_INS_CLIBH, "clibh"}, + {SYSZ_INS_CLIBHE, "clibhe"}, {SYSZ_INS_CLIBL, "clibl"}, + {SYSZ_INS_CLIBLE, "clible"}, {SYSZ_INS_CLIBLH, "cliblh"}, + {SYSZ_INS_CLIBNE, "clibne"}, {SYSZ_INS_CLIBNH, "clibnh"}, + {SYSZ_INS_CLIBNHE, "clibnhe"}, {SYSZ_INS_CLIBNL, "clibnl"}, + {SYSZ_INS_CLIBNLE, "clibnle"}, {SYSZ_INS_CLIBNLH, "clibnlh"}, + {SYSZ_INS_CLM, "clm"}, {SYSZ_INS_CLMH, "clmh"}, {SYSZ_INS_CLMY, "clmy"}, + {SYSZ_INS_CLRB, "clrb"}, {SYSZ_INS_CLRBE, "clrbe"}, + {SYSZ_INS_CLRBH, "clrbh"}, {SYSZ_INS_CLRBHE, "clrbhe"}, + {SYSZ_INS_CLRBL, "clrbl"}, {SYSZ_INS_CLRBLE, "clrble"}, + {SYSZ_INS_CLRBLH, "clrblh"}, {SYSZ_INS_CLRBNE, "clrbne"}, + {SYSZ_INS_CLRBNH, "clrbnh"}, {SYSZ_INS_CLRBNHE, "clrbnhe"}, + {SYSZ_INS_CLRBNL, "clrbnl"}, {SYSZ_INS_CLRBNLE, "clrbnle"}, + {SYSZ_INS_CLRBNLH, "clrbnlh"}, {SYSZ_INS_CLRT, "clrt"}, + {SYSZ_INS_CLRTE, "clrte"}, {SYSZ_INS_CLRTH, "clrth"}, + {SYSZ_INS_CLRTHE, "clrthe"}, {SYSZ_INS_CLRTL, "clrtl"}, + {SYSZ_INS_CLRTLE, "clrtle"}, {SYSZ_INS_CLRTLH, "clrtlh"}, + {SYSZ_INS_CLRTNE, "clrtne"}, {SYSZ_INS_CLRTNH, "clrtnh"}, + {SYSZ_INS_CLRTNHE, "clrtnhe"}, {SYSZ_INS_CLRTNL, "clrtnl"}, + {SYSZ_INS_CLRTNLE, "clrtnle"}, {SYSZ_INS_CLRTNLH, "clrtnlh"}, + {SYSZ_INS_CLT, "clt"}, {SYSZ_INS_CLTE, "clte"}, {SYSZ_INS_CLTH, "clth"}, + {SYSZ_INS_CLTHE, "clthe"}, {SYSZ_INS_CLTL, "cltl"}, + {SYSZ_INS_CLTLE, "cltle"}, {SYSZ_INS_CLTLH, "cltlh"}, + {SYSZ_INS_CLTNE, "cltne"}, {SYSZ_INS_CLTNH, "cltnh"}, + {SYSZ_INS_CLTNHE, "cltnhe"}, {SYSZ_INS_CLTNL, "cltnl"}, + {SYSZ_INS_CLTNLE, "cltnle"}, {SYSZ_INS_CLTNLH, "cltnlh"}, + {SYSZ_INS_CMPSC, "cmpsc"}, {SYSZ_INS_CP, "cp"}, {SYSZ_INS_CPDT, "cpdt"}, + {SYSZ_INS_CPXT, "cpxt"}, {SYSZ_INS_CPYA, "cpya"}, {SYSZ_INS_CRB, "crb"}, + {SYSZ_INS_CRBE, "crbe"}, {SYSZ_INS_CRBH, "crbh"}, {SYSZ_INS_CRBHE, "crbhe"}, + {SYSZ_INS_CRBL, "crbl"}, {SYSZ_INS_CRBLE, "crble"}, + {SYSZ_INS_CRBLH, "crblh"}, {SYSZ_INS_CRBNE, "crbne"}, + {SYSZ_INS_CRBNH, "crbnh"}, {SYSZ_INS_CRBNHE, "crbnhe"}, + {SYSZ_INS_CRBNL, "crbnl"}, {SYSZ_INS_CRBNLE, "crbnle"}, + {SYSZ_INS_CRBNLH, "crbnlh"}, {SYSZ_INS_CRDTE, "crdte"}, + {SYSZ_INS_CRT, "crt"}, {SYSZ_INS_CRTE, "crte"}, {SYSZ_INS_CRTH, "crth"}, + {SYSZ_INS_CRTHE, "crthe"}, {SYSZ_INS_CRTL, "crtl"}, + {SYSZ_INS_CRTLE, "crtle"}, {SYSZ_INS_CRTLH, "crtlh"}, + {SYSZ_INS_CRTNE, "crtne"}, {SYSZ_INS_CRTNH, "crtnh"}, + {SYSZ_INS_CRTNHE, "crtnhe"}, {SYSZ_INS_CRTNL, "crtnl"}, + {SYSZ_INS_CRTNLE, "crtnle"}, {SYSZ_INS_CRTNLH, "crtnlh"}, + {SYSZ_INS_CSCH, "csch"}, {SYSZ_INS_CSDTR, "csdtr"}, {SYSZ_INS_CSP, "csp"}, + {SYSZ_INS_CSPG, "cspg"}, {SYSZ_INS_CSST, "csst"}, {SYSZ_INS_CSXTR, "csxtr"}, + {SYSZ_INS_CU12, "cu12"}, {SYSZ_INS_CU14, "cu14"}, {SYSZ_INS_CU21, "cu21"}, + {SYSZ_INS_CU24, "cu24"}, {SYSZ_INS_CU41, "cu41"}, {SYSZ_INS_CU42, "cu42"}, + {SYSZ_INS_CUDTR, "cudtr"}, {SYSZ_INS_CUSE, "cuse"}, + {SYSZ_INS_CUTFU, "cutfu"}, {SYSZ_INS_CUUTF, "cuutf"}, + {SYSZ_INS_CUXTR, "cuxtr"}, {SYSZ_INS_CVB, "cvb"}, {SYSZ_INS_CVBG, "cvbg"}, + {SYSZ_INS_CVBY, "cvby"}, {SYSZ_INS_CVD, "cvd"}, {SYSZ_INS_CVDG, "cvdg"}, + {SYSZ_INS_CVDY, "cvdy"}, {SYSZ_INS_CXFBRA, "cxfbra"}, + {SYSZ_INS_CXFR, "cxfr"}, {SYSZ_INS_CXFTR, "cxftr"}, + {SYSZ_INS_CXGBRA, "cxgbra"}, {SYSZ_INS_CXGR, "cxgr"}, + {SYSZ_INS_CXGTR, "cxgtr"}, {SYSZ_INS_CXGTRA, "cxgtra"}, + {SYSZ_INS_CXLFTR, "cxlftr"}, {SYSZ_INS_CXLGTR, "cxlgtr"}, + {SYSZ_INS_CXPT, "cxpt"}, {SYSZ_INS_CXR, "cxr"}, {SYSZ_INS_CXSTR, "cxstr"}, + {SYSZ_INS_CXTR, "cxtr"}, {SYSZ_INS_CXUTR, "cxutr"}, {SYSZ_INS_CXZT, "cxzt"}, + {SYSZ_INS_CZDT, "czdt"}, {SYSZ_INS_CZXT, "czxt"}, {SYSZ_INS_D, "d"}, + {SYSZ_INS_DD, "dd"}, {SYSZ_INS_DDR, "ddr"}, {SYSZ_INS_DDTR, "ddtr"}, + {SYSZ_INS_DDTRA, "ddtra"}, {SYSZ_INS_DE, "de"}, {SYSZ_INS_DER, "der"}, + {SYSZ_INS_DIAG, "diag"}, {SYSZ_INS_DIDBR, "didbr"}, + {SYSZ_INS_DIEBR, "diebr"}, {SYSZ_INS_DP, "dp"}, {SYSZ_INS_DR, "dr"}, + {SYSZ_INS_DXR, "dxr"}, {SYSZ_INS_DXTR, "dxtr"}, {SYSZ_INS_DXTRA, "dxtra"}, + {SYSZ_INS_ECAG, "ecag"}, {SYSZ_INS_ECCTR, "ecctr"}, + {SYSZ_INS_ECPGA, "ecpga"}, {SYSZ_INS_ECTG, "ectg"}, {SYSZ_INS_ED, "ed"}, + {SYSZ_INS_EDMK, "edmk"}, {SYSZ_INS_EEDTR, "eedtr"}, + {SYSZ_INS_EEXTR, "eextr"}, {SYSZ_INS_EFPC, "efpc"}, + {SYSZ_INS_EPAIR, "epair"}, {SYSZ_INS_EPAR, "epar"}, + {SYSZ_INS_EPCTR, "epctr"}, {SYSZ_INS_EPSW, "epsw"}, {SYSZ_INS_EREG, "ereg"}, + {SYSZ_INS_EREGG, "eregg"}, {SYSZ_INS_ESAIR, "esair"}, + {SYSZ_INS_ESAR, "esar"}, {SYSZ_INS_ESDTR, "esdtr"}, {SYSZ_INS_ESEA, "esea"}, + {SYSZ_INS_ESTA, "esta"}, {SYSZ_INS_ESXTR, "esxtr"}, {SYSZ_INS_ETND, "etnd"}, + {SYSZ_INS_EX, "ex"}, {SYSZ_INS_EXRL, "exrl"}, {SYSZ_INS_FIDR, "fidr"}, + {SYSZ_INS_FIDTR, "fidtr"}, {SYSZ_INS_FIER, "fier"}, {SYSZ_INS_FIXR, "fixr"}, + {SYSZ_INS_FIXTR, "fixtr"}, {SYSZ_INS_HDR, "hdr"}, {SYSZ_INS_HER, "her"}, + {SYSZ_INS_HSCH, "hsch"}, {SYSZ_INS_IAC, "iac"}, {SYSZ_INS_ICM, "icm"}, + {SYSZ_INS_ICMH, "icmh"}, {SYSZ_INS_ICMY, "icmy"}, {SYSZ_INS_IDTE, "idte"}, + {SYSZ_INS_IEDTR, "iedtr"}, {SYSZ_INS_IEXTR, "iextr"}, {SYSZ_INS_IPK, "ipk"}, + {SYSZ_INS_IPTE, "ipte"}, {SYSZ_INS_IRBM, "irbm"}, {SYSZ_INS_ISKE, "iske"}, + {SYSZ_INS_IVSK, "ivsk"}, {SYSZ_INS_JGM, "jgm"}, {SYSZ_INS_JGNM, "jgnm"}, + {SYSZ_INS_JGNP, "jgnp"}, {SYSZ_INS_JGNZ, "jgnz"}, {SYSZ_INS_JGP, "jgp"}, + {SYSZ_INS_JGZ, "jgz"}, {SYSZ_INS_JM, "jm"}, {SYSZ_INS_JNM, "jnm"}, + {SYSZ_INS_JNP, "jnp"}, {SYSZ_INS_JNZ, "jnz"}, {SYSZ_INS_JP, "jp"}, + {SYSZ_INS_JZ, "jz"}, {SYSZ_INS_KDB, "kdb"}, {SYSZ_INS_KDBR, "kdbr"}, + {SYSZ_INS_KDTR, "kdtr"}, {SYSZ_INS_KEB, "keb"}, {SYSZ_INS_KEBR, "kebr"}, + {SYSZ_INS_KIMD, "kimd"}, {SYSZ_INS_KLMD, "klmd"}, {SYSZ_INS_KM, "km"}, + {SYSZ_INS_KMA, "kma"}, {SYSZ_INS_KMAC, "kmac"}, {SYSZ_INS_KMC, "kmc"}, + {SYSZ_INS_KMCTR, "kmctr"}, {SYSZ_INS_KMF, "kmf"}, {SYSZ_INS_KMO, "kmo"}, + {SYSZ_INS_KXBR, "kxbr"}, {SYSZ_INS_KXTR, "kxtr"}, {SYSZ_INS_LAE, "lae"}, + {SYSZ_INS_LAEY, "laey"}, {SYSZ_INS_LAM, "lam"}, {SYSZ_INS_LAMY, "lamy"}, + {SYSZ_INS_LASP, "lasp"}, {SYSZ_INS_LAT, "lat"}, {SYSZ_INS_LCBB, "lcbb"}, + {SYSZ_INS_LCCTL, "lcctl"}, {SYSZ_INS_LCDFR, "lcdfr"}, + {SYSZ_INS_LCDR, "lcdr"}, {SYSZ_INS_LCER, "lcer"}, {SYSZ_INS_LCTL, "lctl"}, + {SYSZ_INS_LCTLG, "lctlg"}, {SYSZ_INS_LCXR, "lcxr"}, {SYSZ_INS_LDE, "lde"}, + {SYSZ_INS_LDER, "lder"}, {SYSZ_INS_LDETR, "ldetr"}, {SYSZ_INS_LDXR, "ldxr"}, + {SYSZ_INS_LDXTR, "ldxtr"}, {SYSZ_INS_LEDR, "ledr"}, + {SYSZ_INS_LEDTR, "ledtr"}, {SYSZ_INS_LEXR, "lexr"}, {SYSZ_INS_LFAS, "lfas"}, + {SYSZ_INS_LFHAT, "lfhat"}, {SYSZ_INS_LFPC, "lfpc"}, {SYSZ_INS_LGAT, "lgat"}, + {SYSZ_INS_LGG, "lgg"}, {SYSZ_INS_LGSC, "lgsc"}, {SYSZ_INS_LLGFAT, "llgfat"}, + {SYSZ_INS_LLGFSG, "llgfsg"}, {SYSZ_INS_LLGT, "llgt"}, + {SYSZ_INS_LLGTAT, "llgtat"}, {SYSZ_INS_LLGTR, "llgtr"}, + {SYSZ_INS_LLZRGF, "llzrgf"}, {SYSZ_INS_LM, "lm"}, {SYSZ_INS_LMD, "lmd"}, + {SYSZ_INS_LMH, "lmh"}, {SYSZ_INS_LMY, "lmy"}, {SYSZ_INS_LNDFR, "lndfr"}, + {SYSZ_INS_LNDR, "lndr"}, {SYSZ_INS_LNER, "lner"}, {SYSZ_INS_LNXR, "lnxr"}, + {SYSZ_INS_LOCFH, "locfh"}, {SYSZ_INS_LOCFHE, "locfhe"}, + {SYSZ_INS_LOCFHH, "locfhh"}, {SYSZ_INS_LOCFHHE, "locfhhe"}, + {SYSZ_INS_LOCFHL, "locfhl"}, {SYSZ_INS_LOCFHLE, "locfhle"}, + {SYSZ_INS_LOCFHLH, "locfhlh"}, {SYSZ_INS_LOCFHM, "locfhm"}, + {SYSZ_INS_LOCFHNE, "locfhne"}, {SYSZ_INS_LOCFHNH, "locfhnh"}, + {SYSZ_INS_LOCFHNHE, "locfhnhe"}, {SYSZ_INS_LOCFHNL, "locfhnl"}, + {SYSZ_INS_LOCFHNLE, "locfhnle"}, {SYSZ_INS_LOCFHNLH, "locfhnlh"}, + {SYSZ_INS_LOCFHNM, "locfhnm"}, {SYSZ_INS_LOCFHNO, "locfhno"}, + {SYSZ_INS_LOCFHNP, "locfhnp"}, {SYSZ_INS_LOCFHNZ, "locfhnz"}, + {SYSZ_INS_LOCFHO, "locfho"}, {SYSZ_INS_LOCFHP, "locfhp"}, + {SYSZ_INS_LOCFHR, "locfhr"}, {SYSZ_INS_LOCFHRE, "locfhre"}, + {SYSZ_INS_LOCFHRH, "locfhrh"}, {SYSZ_INS_LOCFHRHE, "locfhrhe"}, + {SYSZ_INS_LOCFHRL, "locfhrl"}, {SYSZ_INS_LOCFHRLE, "locfhrle"}, + {SYSZ_INS_LOCFHRLH, "locfhrlh"}, {SYSZ_INS_LOCFHRM, "locfhrm"}, + {SYSZ_INS_LOCFHRNE, "locfhrne"}, {SYSZ_INS_LOCFHRNH, "locfhrnh"}, + {SYSZ_INS_LOCFHRNHE, "locfhrnhe"}, {SYSZ_INS_LOCFHRNL, "locfhrnl"}, + {SYSZ_INS_LOCFHRNLE, "locfhrnle"}, {SYSZ_INS_LOCFHRNLH, "locfhrnlh"}, + {SYSZ_INS_LOCFHRNM, "locfhrnm"}, {SYSZ_INS_LOCFHRNO, "locfhrno"}, + {SYSZ_INS_LOCFHRNP, "locfhrnp"}, {SYSZ_INS_LOCFHRNZ, "locfhrnz"}, + {SYSZ_INS_LOCFHRO, "locfhro"}, {SYSZ_INS_LOCFHRP, "locfhrp"}, + {SYSZ_INS_LOCFHRZ, "locfhrz"}, {SYSZ_INS_LOCFHZ, "locfhz"}, + {SYSZ_INS_LOCGHI, "locghi"}, {SYSZ_INS_LOCGHIE, "locghie"}, + {SYSZ_INS_LOCGHIH, "locghih"}, {SYSZ_INS_LOCGHIHE, "locghihe"}, + {SYSZ_INS_LOCGHIL, "locghil"}, {SYSZ_INS_LOCGHILE, "locghile"}, + {SYSZ_INS_LOCGHILH, "locghilh"}, {SYSZ_INS_LOCGHIM, "locghim"}, + {SYSZ_INS_LOCGHINE, "locghine"}, {SYSZ_INS_LOCGHINH, "locghinh"}, + {SYSZ_INS_LOCGHINHE, "locghinhe"}, {SYSZ_INS_LOCGHINL, "locghinl"}, + {SYSZ_INS_LOCGHINLE, "locghinle"}, {SYSZ_INS_LOCGHINLH, "locghinlh"}, + {SYSZ_INS_LOCGHINM, "locghinm"}, {SYSZ_INS_LOCGHINO, "locghino"}, + {SYSZ_INS_LOCGHINP, "locghinp"}, {SYSZ_INS_LOCGHINZ, "locghinz"}, + {SYSZ_INS_LOCGHIO, "locghio"}, {SYSZ_INS_LOCGHIP, "locghip"}, + {SYSZ_INS_LOCGHIZ, "locghiz"}, {SYSZ_INS_LOCGM, "locgm"}, + {SYSZ_INS_LOCGNM, "locgnm"}, {SYSZ_INS_LOCGNP, "locgnp"}, + {SYSZ_INS_LOCGNZ, "locgnz"}, {SYSZ_INS_LOCGP, "locgp"}, + {SYSZ_INS_LOCGRM, "locgrm"}, {SYSZ_INS_LOCGRNM, "locgrnm"}, + {SYSZ_INS_LOCGRNP, "locgrnp"}, {SYSZ_INS_LOCGRNZ, "locgrnz"}, + {SYSZ_INS_LOCGRP, "locgrp"}, {SYSZ_INS_LOCGRZ, "locgrz"}, + {SYSZ_INS_LOCGZ, "locgz"}, {SYSZ_INS_LOCHHI, "lochhi"}, + {SYSZ_INS_LOCHHIE, "lochhie"}, {SYSZ_INS_LOCHHIH, "lochhih"}, + {SYSZ_INS_LOCHHIHE, "lochhihe"}, {SYSZ_INS_LOCHHIL, "lochhil"}, + {SYSZ_INS_LOCHHILE, "lochhile"}, {SYSZ_INS_LOCHHILH, "lochhilh"}, + {SYSZ_INS_LOCHHIM, "lochhim"}, {SYSZ_INS_LOCHHINE, "lochhine"}, + {SYSZ_INS_LOCHHINH, "lochhinh"}, {SYSZ_INS_LOCHHINHE, "lochhinhe"}, + {SYSZ_INS_LOCHHINL, "lochhinl"}, {SYSZ_INS_LOCHHINLE, "lochhinle"}, + {SYSZ_INS_LOCHHINLH, "lochhinlh"}, {SYSZ_INS_LOCHHINM, "lochhinm"}, + {SYSZ_INS_LOCHHINO, "lochhino"}, {SYSZ_INS_LOCHHINP, "lochhinp"}, + {SYSZ_INS_LOCHHINZ, "lochhinz"}, {SYSZ_INS_LOCHHIO, "lochhio"}, + {SYSZ_INS_LOCHHIP, "lochhip"}, {SYSZ_INS_LOCHHIZ, "lochhiz"}, + {SYSZ_INS_LOCHI, "lochi"}, {SYSZ_INS_LOCHIE, "lochie"}, + {SYSZ_INS_LOCHIH, "lochih"}, {SYSZ_INS_LOCHIHE, "lochihe"}, + {SYSZ_INS_LOCHIL, "lochil"}, {SYSZ_INS_LOCHILE, "lochile"}, + {SYSZ_INS_LOCHILH, "lochilh"}, {SYSZ_INS_LOCHIM, "lochim"}, + {SYSZ_INS_LOCHINE, "lochine"}, {SYSZ_INS_LOCHINH, "lochinh"}, + {SYSZ_INS_LOCHINHE, "lochinhe"}, {SYSZ_INS_LOCHINL, "lochinl"}, + {SYSZ_INS_LOCHINLE, "lochinle"}, {SYSZ_INS_LOCHINLH, "lochinlh"}, + {SYSZ_INS_LOCHINM, "lochinm"}, {SYSZ_INS_LOCHINO, "lochino"}, + {SYSZ_INS_LOCHINP, "lochinp"}, {SYSZ_INS_LOCHINZ, "lochinz"}, + {SYSZ_INS_LOCHIO, "lochio"}, {SYSZ_INS_LOCHIP, "lochip"}, + {SYSZ_INS_LOCHIZ, "lochiz"}, {SYSZ_INS_LOCM, "locm"}, + {SYSZ_INS_LOCNM, "locnm"}, {SYSZ_INS_LOCNP, "locnp"}, + {SYSZ_INS_LOCNZ, "locnz"}, {SYSZ_INS_LOCP, "locp"}, + {SYSZ_INS_LOCRM, "locrm"}, {SYSZ_INS_LOCRNM, "locrnm"}, + {SYSZ_INS_LOCRNP, "locrnp"}, {SYSZ_INS_LOCRNZ, "locrnz"}, + {SYSZ_INS_LOCRP, "locrp"}, {SYSZ_INS_LOCRZ, "locrz"}, + {SYSZ_INS_LOCZ, "locz"}, {SYSZ_INS_LPCTL, "lpctl"}, {SYSZ_INS_LPD, "lpd"}, + {SYSZ_INS_LPDFR, "lpdfr"}, {SYSZ_INS_LPDG, "lpdg"}, {SYSZ_INS_LPDR, "lpdr"}, + {SYSZ_INS_LPER, "lper"}, {SYSZ_INS_LPP, "lpp"}, {SYSZ_INS_LPQ, "lpq"}, + {SYSZ_INS_LPSW, "lpsw"}, {SYSZ_INS_LPSWE, "lpswe"}, + {SYSZ_INS_LPTEA, "lptea"}, {SYSZ_INS_LPXR, "lpxr"}, {SYSZ_INS_LRA, "lra"}, + {SYSZ_INS_LRAG, "lrag"}, {SYSZ_INS_LRAY, "lray"}, {SYSZ_INS_LRDR, "lrdr"}, + {SYSZ_INS_LRER, "lrer"}, {SYSZ_INS_LRVH, "lrvh"}, {SYSZ_INS_LSCTL, "lsctl"}, + {SYSZ_INS_LTDR, "ltdr"}, {SYSZ_INS_LTDTR, "ltdtr"}, {SYSZ_INS_LTER, "lter"}, + {SYSZ_INS_LTXR, "ltxr"}, {SYSZ_INS_LTXTR, "ltxtr"}, {SYSZ_INS_LURA, "lura"}, + {SYSZ_INS_LURAG, "lurag"}, {SYSZ_INS_LXD, "lxd"}, {SYSZ_INS_LXDR, "lxdr"}, + {SYSZ_INS_LXDTR, "lxdtr"}, {SYSZ_INS_LXE, "lxe"}, {SYSZ_INS_LXER, "lxer"}, + {SYSZ_INS_LZRF, "lzrf"}, {SYSZ_INS_LZRG, "lzrg"}, {SYSZ_INS_M, "m"}, + {SYSZ_INS_MAD, "mad"}, {SYSZ_INS_MADR, "madr"}, {SYSZ_INS_MAE, "mae"}, + {SYSZ_INS_MAER, "maer"}, {SYSZ_INS_MAY, "may"}, {SYSZ_INS_MAYH, "mayh"}, + {SYSZ_INS_MAYHR, "mayhr"}, {SYSZ_INS_MAYL, "mayl"}, + {SYSZ_INS_MAYLR, "maylr"}, {SYSZ_INS_MAYR, "mayr"}, {SYSZ_INS_MC, "mc"}, + {SYSZ_INS_MD, "md"}, {SYSZ_INS_MDE, "mde"}, {SYSZ_INS_MDER, "mder"}, + {SYSZ_INS_MDR, "mdr"}, {SYSZ_INS_MDTR, "mdtr"}, {SYSZ_INS_MDTRA, "mdtra"}, + {SYSZ_INS_ME, "me"}, {SYSZ_INS_MEE, "mee"}, {SYSZ_INS_MEER, "meer"}, + {SYSZ_INS_MER, "mer"}, {SYSZ_INS_MFY, "mfy"}, {SYSZ_INS_MG, "mg"}, + {SYSZ_INS_MGH, "mgh"}, {SYSZ_INS_MGRK, "mgrk"}, {SYSZ_INS_ML, "ml"}, + {SYSZ_INS_MLR, "mlr"}, {SYSZ_INS_MP, "mp"}, {SYSZ_INS_MR, "mr"}, + {SYSZ_INS_MSC, "msc"}, {SYSZ_INS_MSCH, "msch"}, {SYSZ_INS_MSD, "msd"}, + {SYSZ_INS_MSDR, "msdr"}, {SYSZ_INS_MSE, "mse"}, {SYSZ_INS_MSER, "mser"}, + {SYSZ_INS_MSGC, "msgc"}, {SYSZ_INS_MSGRKC, "msgrkc"}, + {SYSZ_INS_MSRKC, "msrkc"}, {SYSZ_INS_MSTA, "msta"}, + {SYSZ_INS_MVCDK, "mvcdk"}, {SYSZ_INS_MVCIN, "mvcin"}, + {SYSZ_INS_MVCK, "mvck"}, {SYSZ_INS_MVCL, "mvcl"}, {SYSZ_INS_MVCLE, "mvcle"}, + {SYSZ_INS_MVCLU, "mvclu"}, {SYSZ_INS_MVCOS, "mvcos"}, + {SYSZ_INS_MVCP, "mvcp"}, {SYSZ_INS_MVCS, "mvcs"}, {SYSZ_INS_MVCSK, "mvcsk"}, + {SYSZ_INS_MVN, "mvn"}, {SYSZ_INS_MVO, "mvo"}, {SYSZ_INS_MVPG, "mvpg"}, + {SYSZ_INS_MVZ, "mvz"}, {SYSZ_INS_MXD, "mxd"}, {SYSZ_INS_MXDR, "mxdr"}, + {SYSZ_INS_MXR, "mxr"}, {SYSZ_INS_MXTR, "mxtr"}, {SYSZ_INS_MXTRA, "mxtra"}, + {SYSZ_INS_MY, "my"}, {SYSZ_INS_MYH, "myh"}, {SYSZ_INS_MYHR, "myhr"}, + {SYSZ_INS_MYL, "myl"}, {SYSZ_INS_MYLR, "mylr"}, {SYSZ_INS_MYR, "myr"}, + {SYSZ_INS_NIAI, "niai"}, {SYSZ_INS_NTSTG, "ntstg"}, {SYSZ_INS_PACK, "pack"}, + {SYSZ_INS_PALB, "palb"}, {SYSZ_INS_PC, "pc"}, {SYSZ_INS_PCC, "pcc"}, + {SYSZ_INS_PCKMO, "pckmo"}, {SYSZ_INS_PFMF, "pfmf"}, {SYSZ_INS_PFPO, "pfpo"}, + {SYSZ_INS_PGIN, "pgin"}, {SYSZ_INS_PGOUT, "pgout"}, {SYSZ_INS_PKA, "pka"}, + {SYSZ_INS_PKU, "pku"}, {SYSZ_INS_PLO, "plo"}, {SYSZ_INS_POPCNT, "popcnt"}, + {SYSZ_INS_PPA, "ppa"}, {SYSZ_INS_PPNO, "ppno"}, {SYSZ_INS_PR, "pr"}, + {SYSZ_INS_PRNO, "prno"}, {SYSZ_INS_PT, "pt"}, {SYSZ_INS_PTF, "ptf"}, + {SYSZ_INS_PTFF, "ptff"}, {SYSZ_INS_PTI, "pti"}, {SYSZ_INS_PTLB, "ptlb"}, + {SYSZ_INS_QADTR, "qadtr"}, {SYSZ_INS_QAXTR, "qaxtr"}, + {SYSZ_INS_QCTRI, "qctri"}, {SYSZ_INS_QSI, "qsi"}, {SYSZ_INS_RCHP, "rchp"}, + {SYSZ_INS_RISBGN, "risbgn"}, {SYSZ_INS_RP, "rp"}, {SYSZ_INS_RRBE, "rrbe"}, + {SYSZ_INS_RRBM, "rrbm"}, {SYSZ_INS_RRDTR, "rrdtr"}, + {SYSZ_INS_RRXTR, "rrxtr"}, {SYSZ_INS_RSCH, "rsch"}, {SYSZ_INS_SAC, "sac"}, + {SYSZ_INS_SACF, "sacf"}, {SYSZ_INS_SAL, "sal"}, {SYSZ_INS_SAM24, "sam24"}, + {SYSZ_INS_SAM31, "sam31"}, {SYSZ_INS_SAM64, "sam64"}, {SYSZ_INS_SAR, "sar"}, + {SYSZ_INS_SCCTR, "scctr"}, {SYSZ_INS_SCHM, "schm"}, {SYSZ_INS_SCK, "sck"}, + {SYSZ_INS_SCKC, "sckc"}, {SYSZ_INS_SCKPF, "sckpf"}, {SYSZ_INS_SD, "sd"}, + {SYSZ_INS_SDR, "sdr"}, {SYSZ_INS_SDTR, "sdtr"}, {SYSZ_INS_SDTRA, "sdtra"}, + {SYSZ_INS_SE, "se"}, {SYSZ_INS_SER, "ser"}, {SYSZ_INS_SFASR, "sfasr"}, + {SYSZ_INS_SFPC, "sfpc"}, {SYSZ_INS_SGH, "sgh"}, {SYSZ_INS_SHHHR, "shhhr"}, + {SYSZ_INS_SHHLR, "shhlr"}, {SYSZ_INS_SIE, "sie"}, {SYSZ_INS_SIGA, "siga"}, + {SYSZ_INS_SIGP, "sigp"}, {SYSZ_INS_SLA, "sla"}, {SYSZ_INS_SLAG, "slag"}, + {SYSZ_INS_SLAK, "slak"}, {SYSZ_INS_SLDA, "slda"}, {SYSZ_INS_SLDL, "sldl"}, + {SYSZ_INS_SLDT, "sldt"}, {SYSZ_INS_SLHHHR, "slhhhr"}, + {SYSZ_INS_SLHHLR, "slhhlr"}, {SYSZ_INS_SLXT, "slxt"}, {SYSZ_INS_SP, "sp"}, + {SYSZ_INS_SPCTR, "spctr"}, {SYSZ_INS_SPKA, "spka"}, {SYSZ_INS_SPM, "spm"}, + {SYSZ_INS_SPT, "spt"}, {SYSZ_INS_SPX, "spx"}, {SYSZ_INS_SQD, "sqd"}, + {SYSZ_INS_SQDR, "sqdr"}, {SYSZ_INS_SQE, "sqe"}, {SYSZ_INS_SQER, "sqer"}, + {SYSZ_INS_SQXR, "sqxr"}, {SYSZ_INS_SRDA, "srda"}, {SYSZ_INS_SRDL, "srdl"}, + {SYSZ_INS_SRDT, "srdt"}, {SYSZ_INS_SRNM, "srnm"}, {SYSZ_INS_SRNMB, "srnmb"}, + {SYSZ_INS_SRNMT, "srnmt"}, {SYSZ_INS_SRP, "srp"}, {SYSZ_INS_SRSTU, "srstu"}, + {SYSZ_INS_SRXT, "srxt"}, {SYSZ_INS_SSAIR, "ssair"}, {SYSZ_INS_SSAR, "ssar"}, + {SYSZ_INS_SSCH, "ssch"}, {SYSZ_INS_SSKE, "sske"}, {SYSZ_INS_SSM, "ssm"}, + {SYSZ_INS_STAM, "stam"}, {SYSZ_INS_STAMY, "stamy"}, {SYSZ_INS_STAP, "stap"}, + {SYSZ_INS_STCK, "stck"}, {SYSZ_INS_STCKC, "stckc"}, + {SYSZ_INS_STCKE, "stcke"}, {SYSZ_INS_STCKF, "stckf"}, + {SYSZ_INS_STCM, "stcm"}, {SYSZ_INS_STCMH, "stcmh"}, + {SYSZ_INS_STCMY, "stcmy"}, {SYSZ_INS_STCPS, "stcps"}, + {SYSZ_INS_STCRW, "stcrw"}, {SYSZ_INS_STCTG, "stctg"}, + {SYSZ_INS_STCTL, "stctl"}, {SYSZ_INS_STFL, "stfl"}, + {SYSZ_INS_STFLE, "stfle"}, {SYSZ_INS_STFPC, "stfpc"}, + {SYSZ_INS_STGSC, "stgsc"}, {SYSZ_INS_STIDP, "stidp"}, {SYSZ_INS_STM, "stm"}, + {SYSZ_INS_STMH, "stmh"}, {SYSZ_INS_STMY, "stmy"}, {SYSZ_INS_STNSM, "stnsm"}, + {SYSZ_INS_STOCFH, "stocfh"}, {SYSZ_INS_STOCFHE, "stocfhe"}, + {SYSZ_INS_STOCFHH, "stocfhh"}, {SYSZ_INS_STOCFHHE, "stocfhhe"}, + {SYSZ_INS_STOCFHL, "stocfhl"}, {SYSZ_INS_STOCFHLE, "stocfhle"}, + {SYSZ_INS_STOCFHLH, "stocfhlh"}, {SYSZ_INS_STOCFHM, "stocfhm"}, + {SYSZ_INS_STOCFHNE, "stocfhne"}, {SYSZ_INS_STOCFHNH, "stocfhnh"}, + {SYSZ_INS_STOCFHNHE, "stocfhnhe"}, {SYSZ_INS_STOCFHNL, "stocfhnl"}, + {SYSZ_INS_STOCFHNLE, "stocfhnle"}, {SYSZ_INS_STOCFHNLH, "stocfhnlh"}, + {SYSZ_INS_STOCFHNM, "stocfhnm"}, {SYSZ_INS_STOCFHNO, "stocfhno"}, + {SYSZ_INS_STOCFHNP, "stocfhnp"}, {SYSZ_INS_STOCFHNZ, "stocfhnz"}, + {SYSZ_INS_STOCFHO, "stocfho"}, {SYSZ_INS_STOCFHP, "stocfhp"}, + {SYSZ_INS_STOCFHZ, "stocfhz"}, {SYSZ_INS_STOCGM, "stocgm"}, + {SYSZ_INS_STOCGNM, "stocgnm"}, {SYSZ_INS_STOCGNP, "stocgnp"}, + {SYSZ_INS_STOCGNZ, "stocgnz"}, {SYSZ_INS_STOCGP, "stocgp"}, + {SYSZ_INS_STOCGZ, "stocgz"}, {SYSZ_INS_STOCM, "stocm"}, + {SYSZ_INS_STOCNM, "stocnm"}, {SYSZ_INS_STOCNP, "stocnp"}, + {SYSZ_INS_STOCNZ, "stocnz"}, {SYSZ_INS_STOCP, "stocp"}, + {SYSZ_INS_STOCZ, "stocz"}, {SYSZ_INS_STOSM, "stosm"}, + {SYSZ_INS_STPQ, "stpq"}, {SYSZ_INS_STPT, "stpt"}, {SYSZ_INS_STPX, "stpx"}, + {SYSZ_INS_STRAG, "strag"}, {SYSZ_INS_STRVH, "strvh"}, + {SYSZ_INS_STSCH, "stsch"}, {SYSZ_INS_STSI, "stsi"}, + {SYSZ_INS_STURA, "stura"}, {SYSZ_INS_STURG, "sturg"}, {SYSZ_INS_SU, "su"}, + {SYSZ_INS_SUR, "sur"}, {SYSZ_INS_SVC, "svc"}, {SYSZ_INS_SW, "sw"}, + {SYSZ_INS_SWR, "swr"}, {SYSZ_INS_SXR, "sxr"}, {SYSZ_INS_SXTR, "sxtr"}, + {SYSZ_INS_SXTRA, "sxtra"}, {SYSZ_INS_TABORT, "tabort"}, + {SYSZ_INS_TAM, "tam"}, {SYSZ_INS_TAR, "tar"}, {SYSZ_INS_TB, "tb"}, + {SYSZ_INS_TBDR, "tbdr"}, {SYSZ_INS_TBEDR, "tbedr"}, + {SYSZ_INS_TBEGIN, "tbegin"}, {SYSZ_INS_TBEGINC, "tbeginc"}, + {SYSZ_INS_TCDB, "tcdb"}, {SYSZ_INS_TCEB, "tceb"}, {SYSZ_INS_TCXB, "tcxb"}, + {SYSZ_INS_TDCDT, "tdcdt"}, {SYSZ_INS_TDCET, "tdcet"}, + {SYSZ_INS_TDCXT, "tdcxt"}, {SYSZ_INS_TDGDT, "tdgdt"}, + {SYSZ_INS_TDGET, "tdget"}, {SYSZ_INS_TDGXT, "tdgxt"}, + {SYSZ_INS_TEND, "tend"}, {SYSZ_INS_THDER, "thder"}, {SYSZ_INS_THDR, "thdr"}, + {SYSZ_INS_TP, "tp"}, {SYSZ_INS_TPI, "tpi"}, {SYSZ_INS_TPROT, "tprot"}, + {SYSZ_INS_TR, "tr"}, {SYSZ_INS_TRACE, "trace"}, {SYSZ_INS_TRACG, "tracg"}, + {SYSZ_INS_TRAP2, "trap2"}, {SYSZ_INS_TRAP4, "trap4"}, {SYSZ_INS_TRE, "tre"}, + {SYSZ_INS_TROO, "troo"}, {SYSZ_INS_TROT, "trot"}, {SYSZ_INS_TRT, "trt"}, + {SYSZ_INS_TRTE, "trte"}, {SYSZ_INS_TRTO, "trto"}, {SYSZ_INS_TRTR, "trtr"}, + {SYSZ_INS_TRTRE, "trtre"}, {SYSZ_INS_TRTT, "trtt"}, {SYSZ_INS_TS, "ts"}, + {SYSZ_INS_TSCH, "tsch"}, {SYSZ_INS_UNPK, "unpk"}, {SYSZ_INS_UNPKA, "unpka"}, + {SYSZ_INS_UNPKU, "unpku"}, {SYSZ_INS_UPT, "upt"}, {SYSZ_INS_VA, "va"}, + {SYSZ_INS_VAB, "vab"}, {SYSZ_INS_VAC, "vac"}, {SYSZ_INS_VACC, "vacc"}, + {SYSZ_INS_VACCB, "vaccb"}, {SYSZ_INS_VACCC, "vaccc"}, + {SYSZ_INS_VACCCQ, "vacccq"}, {SYSZ_INS_VACCF, "vaccf"}, + {SYSZ_INS_VACCG, "vaccg"}, {SYSZ_INS_VACCH, "vacch"}, + {SYSZ_INS_VACCQ, "vaccq"}, {SYSZ_INS_VACQ, "vacq"}, {SYSZ_INS_VAF, "vaf"}, + {SYSZ_INS_VAG, "vag"}, {SYSZ_INS_VAH, "vah"}, {SYSZ_INS_VAP, "vap"}, + {SYSZ_INS_VAQ, "vaq"}, {SYSZ_INS_VAVG, "vavg"}, {SYSZ_INS_VAVGB, "vavgb"}, + {SYSZ_INS_VAVGF, "vavgf"}, {SYSZ_INS_VAVGG, "vavgg"}, + {SYSZ_INS_VAVGH, "vavgh"}, {SYSZ_INS_VAVGL, "vavgl"}, + {SYSZ_INS_VAVGLB, "vavglb"}, {SYSZ_INS_VAVGLF, "vavglf"}, + {SYSZ_INS_VAVGLG, "vavglg"}, {SYSZ_INS_VAVGLH, "vavglh"}, + {SYSZ_INS_VBPERM, "vbperm"}, {SYSZ_INS_VCDG, "vcdg"}, + {SYSZ_INS_VCDGB, "vcdgb"}, {SYSZ_INS_VCDLG, "vcdlg"}, + {SYSZ_INS_VCDLGB, "vcdlgb"}, {SYSZ_INS_VCEQ, "vceq"}, + {SYSZ_INS_VCEQB, "vceqb"}, {SYSZ_INS_VCEQBS, "vceqbs"}, + {SYSZ_INS_VCEQF, "vceqf"}, {SYSZ_INS_VCEQFS, "vceqfs"}, + {SYSZ_INS_VCEQG, "vceqg"}, {SYSZ_INS_VCEQGS, "vceqgs"}, + {SYSZ_INS_VCEQH, "vceqh"}, {SYSZ_INS_VCEQHS, "vceqhs"}, + {SYSZ_INS_VCGD, "vcgd"}, {SYSZ_INS_VCGDB, "vcgdb"}, {SYSZ_INS_VCH, "vch"}, + {SYSZ_INS_VCHB, "vchb"}, {SYSZ_INS_VCHBS, "vchbs"}, {SYSZ_INS_VCHF, "vchf"}, + {SYSZ_INS_VCHFS, "vchfs"}, {SYSZ_INS_VCHG, "vchg"}, + {SYSZ_INS_VCHGS, "vchgs"}, {SYSZ_INS_VCHH, "vchh"}, + {SYSZ_INS_VCHHS, "vchhs"}, {SYSZ_INS_VCHL, "vchl"}, + {SYSZ_INS_VCHLB, "vchlb"}, {SYSZ_INS_VCHLBS, "vchlbs"}, + {SYSZ_INS_VCHLF, "vchlf"}, {SYSZ_INS_VCHLFS, "vchlfs"}, + {SYSZ_INS_VCHLG, "vchlg"}, {SYSZ_INS_VCHLGS, "vchlgs"}, + {SYSZ_INS_VCHLH, "vchlh"}, {SYSZ_INS_VCHLHS, "vchlhs"}, + {SYSZ_INS_VCKSM, "vcksm"}, {SYSZ_INS_VCLGD, "vclgd"}, + {SYSZ_INS_VCLGDB, "vclgdb"}, {SYSZ_INS_VCLZ, "vclz"}, + {SYSZ_INS_VCLZB, "vclzb"}, {SYSZ_INS_VCLZF, "vclzf"}, + {SYSZ_INS_VCLZG, "vclzg"}, {SYSZ_INS_VCLZH, "vclzh"}, {SYSZ_INS_VCP, "vcp"}, + {SYSZ_INS_VCTZ, "vctz"}, {SYSZ_INS_VCTZB, "vctzb"}, + {SYSZ_INS_VCTZF, "vctzf"}, {SYSZ_INS_VCTZG, "vctzg"}, + {SYSZ_INS_VCTZH, "vctzh"}, {SYSZ_INS_VCVB, "vcvb"}, + {SYSZ_INS_VCVBG, "vcvbg"}, {SYSZ_INS_VCVD, "vcvd"}, + {SYSZ_INS_VCVDG, "vcvdg"}, {SYSZ_INS_VDP, "vdp"}, {SYSZ_INS_VEC, "vec"}, + {SYSZ_INS_VECB, "vecb"}, {SYSZ_INS_VECF, "vecf"}, {SYSZ_INS_VECG, "vecg"}, + {SYSZ_INS_VECH, "vech"}, {SYSZ_INS_VECL, "vecl"}, {SYSZ_INS_VECLB, "veclb"}, + {SYSZ_INS_VECLF, "veclf"}, {SYSZ_INS_VECLG, "veclg"}, + {SYSZ_INS_VECLH, "veclh"}, {SYSZ_INS_VERIM, "verim"}, + {SYSZ_INS_VERIMB, "verimb"}, {SYSZ_INS_VERIMF, "verimf"}, + {SYSZ_INS_VERIMG, "verimg"}, {SYSZ_INS_VERIMH, "verimh"}, + {SYSZ_INS_VERLL, "verll"}, {SYSZ_INS_VERLLB, "verllb"}, + {SYSZ_INS_VERLLF, "verllf"}, {SYSZ_INS_VERLLG, "verllg"}, + {SYSZ_INS_VERLLH, "verllh"}, {SYSZ_INS_VERLLV, "verllv"}, + {SYSZ_INS_VERLLVB, "verllvb"}, {SYSZ_INS_VERLLVF, "verllvf"}, + {SYSZ_INS_VERLLVG, "verllvg"}, {SYSZ_INS_VERLLVH, "verllvh"}, + {SYSZ_INS_VESL, "vesl"}, {SYSZ_INS_VESLB, "veslb"}, + {SYSZ_INS_VESLF, "veslf"}, {SYSZ_INS_VESLG, "veslg"}, + {SYSZ_INS_VESLH, "veslh"}, {SYSZ_INS_VESLV, "veslv"}, + {SYSZ_INS_VESLVB, "veslvb"}, {SYSZ_INS_VESLVF, "veslvf"}, + {SYSZ_INS_VESLVG, "veslvg"}, {SYSZ_INS_VESLVH, "veslvh"}, + {SYSZ_INS_VESRA, "vesra"}, {SYSZ_INS_VESRAB, "vesrab"}, + {SYSZ_INS_VESRAF, "vesraf"}, {SYSZ_INS_VESRAG, "vesrag"}, + {SYSZ_INS_VESRAH, "vesrah"}, {SYSZ_INS_VESRAV, "vesrav"}, + {SYSZ_INS_VESRAVB, "vesravb"}, {SYSZ_INS_VESRAVF, "vesravf"}, + {SYSZ_INS_VESRAVG, "vesravg"}, {SYSZ_INS_VESRAVH, "vesravh"}, + {SYSZ_INS_VESRL, "vesrl"}, {SYSZ_INS_VESRLB, "vesrlb"}, + {SYSZ_INS_VESRLF, "vesrlf"}, {SYSZ_INS_VESRLG, "vesrlg"}, + {SYSZ_INS_VESRLH, "vesrlh"}, {SYSZ_INS_VESRLV, "vesrlv"}, + {SYSZ_INS_VESRLVB, "vesrlvb"}, {SYSZ_INS_VESRLVF, "vesrlvf"}, + {SYSZ_INS_VESRLVG, "vesrlvg"}, {SYSZ_INS_VESRLVH, "vesrlvh"}, + {SYSZ_INS_VFA, "vfa"}, {SYSZ_INS_VFADB, "vfadb"}, {SYSZ_INS_VFAE, "vfae"}, + {SYSZ_INS_VFAEB, "vfaeb"}, {SYSZ_INS_VFAEBS, "vfaebs"}, + {SYSZ_INS_VFAEF, "vfaef"}, {SYSZ_INS_VFAEFS, "vfaefs"}, + {SYSZ_INS_VFAEH, "vfaeh"}, {SYSZ_INS_VFAEHS, "vfaehs"}, + {SYSZ_INS_VFAEZB, "vfaezb"}, {SYSZ_INS_VFAEZBS, "vfaezbs"}, + {SYSZ_INS_VFAEZF, "vfaezf"}, {SYSZ_INS_VFAEZFS, "vfaezfs"}, + {SYSZ_INS_VFAEZH, "vfaezh"}, {SYSZ_INS_VFAEZHS, "vfaezhs"}, + {SYSZ_INS_VFASB, "vfasb"}, {SYSZ_INS_VFCE, "vfce"}, + {SYSZ_INS_VFCEDB, "vfcedb"}, {SYSZ_INS_VFCEDBS, "vfcedbs"}, + {SYSZ_INS_VFCESB, "vfcesb"}, {SYSZ_INS_VFCESBS, "vfcesbs"}, + {SYSZ_INS_VFCH, "vfch"}, {SYSZ_INS_VFCHDB, "vfchdb"}, + {SYSZ_INS_VFCHDBS, "vfchdbs"}, {SYSZ_INS_VFCHE, "vfche"}, + {SYSZ_INS_VFCHEDB, "vfchedb"}, {SYSZ_INS_VFCHEDBS, "vfchedbs"}, + {SYSZ_INS_VFCHESB, "vfchesb"}, {SYSZ_INS_VFCHESBS, "vfchesbs"}, + {SYSZ_INS_VFCHSB, "vfchsb"}, {SYSZ_INS_VFCHSBS, "vfchsbs"}, + {SYSZ_INS_VFD, "vfd"}, {SYSZ_INS_VFDDB, "vfddb"}, {SYSZ_INS_VFDSB, "vfdsb"}, + {SYSZ_INS_VFEE, "vfee"}, {SYSZ_INS_VFEEB, "vfeeb"}, + {SYSZ_INS_VFEEBS, "vfeebs"}, {SYSZ_INS_VFEEF, "vfeef"}, + {SYSZ_INS_VFEEFS, "vfeefs"}, {SYSZ_INS_VFEEH, "vfeeh"}, + {SYSZ_INS_VFEEHS, "vfeehs"}, {SYSZ_INS_VFEEZB, "vfeezb"}, + {SYSZ_INS_VFEEZBS, "vfeezbs"}, {SYSZ_INS_VFEEZF, "vfeezf"}, + {SYSZ_INS_VFEEZFS, "vfeezfs"}, {SYSZ_INS_VFEEZH, "vfeezh"}, + {SYSZ_INS_VFEEZHS, "vfeezhs"}, {SYSZ_INS_VFENE, "vfene"}, + {SYSZ_INS_VFENEB, "vfeneb"}, {SYSZ_INS_VFENEBS, "vfenebs"}, + {SYSZ_INS_VFENEF, "vfenef"}, {SYSZ_INS_VFENEFS, "vfenefs"}, + {SYSZ_INS_VFENEH, "vfeneh"}, {SYSZ_INS_VFENEHS, "vfenehs"}, + {SYSZ_INS_VFENEZB, "vfenezb"}, {SYSZ_INS_VFENEZBS, "vfenezbs"}, + {SYSZ_INS_VFENEZF, "vfenezf"}, {SYSZ_INS_VFENEZFS, "vfenezfs"}, + {SYSZ_INS_VFENEZH, "vfenezh"}, {SYSZ_INS_VFENEZHS, "vfenezhs"}, + {SYSZ_INS_VFI, "vfi"}, {SYSZ_INS_VFIDB, "vfidb"}, {SYSZ_INS_VFISB, "vfisb"}, + {SYSZ_INS_VFKEDB, "vfkedb"}, {SYSZ_INS_VFKEDBS, "vfkedbs"}, + {SYSZ_INS_VFKESB, "vfkesb"}, {SYSZ_INS_VFKESBS, "vfkesbs"}, + {SYSZ_INS_VFKHDB, "vfkhdb"}, {SYSZ_INS_VFKHDBS, "vfkhdbs"}, + {SYSZ_INS_VFKHEDB, "vfkhedb"}, {SYSZ_INS_VFKHEDBS, "vfkhedbs"}, + {SYSZ_INS_VFKHESB, "vfkhesb"}, {SYSZ_INS_VFKHESBS, "vfkhesbs"}, + {SYSZ_INS_VFKHSB, "vfkhsb"}, {SYSZ_INS_VFKHSBS, "vfkhsbs"}, + {SYSZ_INS_VFLCDB, "vflcdb"}, {SYSZ_INS_VFLCSB, "vflcsb"}, + {SYSZ_INS_VFLL, "vfll"}, {SYSZ_INS_VFLLS, "vflls"}, + {SYSZ_INS_VFLNDB, "vflndb"}, {SYSZ_INS_VFLNSB, "vflnsb"}, + {SYSZ_INS_VFLPDB, "vflpdb"}, {SYSZ_INS_VFLPSB, "vflpsb"}, + {SYSZ_INS_VFLR, "vflr"}, {SYSZ_INS_VFLRD, "vflrd"}, {SYSZ_INS_VFM, "vfm"}, + {SYSZ_INS_VFMA, "vfma"}, {SYSZ_INS_VFMADB, "vfmadb"}, + {SYSZ_INS_VFMASB, "vfmasb"}, {SYSZ_INS_VFMAX, "vfmax"}, + {SYSZ_INS_VFMAXDB, "vfmaxdb"}, {SYSZ_INS_VFMAXSB, "vfmaxsb"}, + {SYSZ_INS_VFMDB, "vfmdb"}, {SYSZ_INS_VFMIN, "vfmin"}, + {SYSZ_INS_VFMINDB, "vfmindb"}, {SYSZ_INS_VFMINSB, "vfminsb"}, + {SYSZ_INS_VFMS, "vfms"}, {SYSZ_INS_VFMSB, "vfmsb"}, + {SYSZ_INS_VFMSDB, "vfmsdb"}, {SYSZ_INS_VFMSSB, "vfmssb"}, + {SYSZ_INS_VFNMA, "vfnma"}, {SYSZ_INS_VFNMADB, "vfnmadb"}, + {SYSZ_INS_VFNMASB, "vfnmasb"}, {SYSZ_INS_VFNMS, "vfnms"}, + {SYSZ_INS_VFNMSDB, "vfnmsdb"}, {SYSZ_INS_VFNMSSB, "vfnmssb"}, + {SYSZ_INS_VFPSO, "vfpso"}, {SYSZ_INS_VFPSODB, "vfpsodb"}, + {SYSZ_INS_VFPSOSB, "vfpsosb"}, {SYSZ_INS_VFS, "vfs"}, + {SYSZ_INS_VFSDB, "vfsdb"}, {SYSZ_INS_VFSQ, "vfsq"}, + {SYSZ_INS_VFSQDB, "vfsqdb"}, {SYSZ_INS_VFSQSB, "vfsqsb"}, + {SYSZ_INS_VFSSB, "vfssb"}, {SYSZ_INS_VFTCI, "vftci"}, + {SYSZ_INS_VFTCIDB, "vftcidb"}, {SYSZ_INS_VFTCISB, "vftcisb"}, + {SYSZ_INS_VGBM, "vgbm"}, {SYSZ_INS_VGEF, "vgef"}, {SYSZ_INS_VGEG, "vgeg"}, + {SYSZ_INS_VGFM, "vgfm"}, {SYSZ_INS_VGFMA, "vgfma"}, + {SYSZ_INS_VGFMAB, "vgfmab"}, {SYSZ_INS_VGFMAF, "vgfmaf"}, + {SYSZ_INS_VGFMAG, "vgfmag"}, {SYSZ_INS_VGFMAH, "vgfmah"}, + {SYSZ_INS_VGFMB, "vgfmb"}, {SYSZ_INS_VGFMF, "vgfmf"}, + {SYSZ_INS_VGFMG, "vgfmg"}, {SYSZ_INS_VGFMH, "vgfmh"}, {SYSZ_INS_VGM, "vgm"}, + {SYSZ_INS_VGMB, "vgmb"}, {SYSZ_INS_VGMF, "vgmf"}, {SYSZ_INS_VGMG, "vgmg"}, + {SYSZ_INS_VGMH, "vgmh"}, {SYSZ_INS_VISTR, "vistr"}, + {SYSZ_INS_VISTRB, "vistrb"}, {SYSZ_INS_VISTRBS, "vistrbs"}, + {SYSZ_INS_VISTRF, "vistrf"}, {SYSZ_INS_VISTRFS, "vistrfs"}, + {SYSZ_INS_VISTRH, "vistrh"}, {SYSZ_INS_VISTRHS, "vistrhs"}, + {SYSZ_INS_VL, "vl"}, {SYSZ_INS_VLBB, "vlbb"}, {SYSZ_INS_VLC, "vlc"}, + {SYSZ_INS_VLCB, "vlcb"}, {SYSZ_INS_VLCF, "vlcf"}, {SYSZ_INS_VLCG, "vlcg"}, + {SYSZ_INS_VLCH, "vlch"}, {SYSZ_INS_VLDE, "vlde"}, {SYSZ_INS_VLDEB, "vldeb"}, + {SYSZ_INS_VLEB, "vleb"}, {SYSZ_INS_VLED, "vled"}, {SYSZ_INS_VLEDB, "vledb"}, + {SYSZ_INS_VLEF, "vlef"}, {SYSZ_INS_VLEG, "vleg"}, {SYSZ_INS_VLEH, "vleh"}, + {SYSZ_INS_VLEIB, "vleib"}, {SYSZ_INS_VLEIF, "vleif"}, + {SYSZ_INS_VLEIG, "vleig"}, {SYSZ_INS_VLEIH, "vleih"}, + {SYSZ_INS_VLGV, "vlgv"}, {SYSZ_INS_VLGVB, "vlgvb"}, + {SYSZ_INS_VLGVF, "vlgvf"}, {SYSZ_INS_VLGVG, "vlgvg"}, + {SYSZ_INS_VLGVH, "vlgvh"}, {SYSZ_INS_VLIP, "vlip"}, {SYSZ_INS_VLL, "vll"}, + {SYSZ_INS_VLLEZ, "vllez"}, {SYSZ_INS_VLLEZB, "vllezb"}, + {SYSZ_INS_VLLEZF, "vllezf"}, {SYSZ_INS_VLLEZG, "vllezg"}, + {SYSZ_INS_VLLEZH, "vllezh"}, {SYSZ_INS_VLLEZLF, "vllezlf"}, + {SYSZ_INS_VLM, "vlm"}, {SYSZ_INS_VLP, "vlp"}, {SYSZ_INS_VLPB, "vlpb"}, + {SYSZ_INS_VLPF, "vlpf"}, {SYSZ_INS_VLPG, "vlpg"}, {SYSZ_INS_VLPH, "vlph"}, + {SYSZ_INS_VLR, "vlr"}, {SYSZ_INS_VLREP, "vlrep"}, + {SYSZ_INS_VLREPB, "vlrepb"}, {SYSZ_INS_VLREPF, "vlrepf"}, + {SYSZ_INS_VLREPG, "vlrepg"}, {SYSZ_INS_VLREPH, "vlreph"}, + {SYSZ_INS_VLRL, "vlrl"}, {SYSZ_INS_VLRLR, "vlrlr"}, {SYSZ_INS_VLVG, "vlvg"}, + {SYSZ_INS_VLVGB, "vlvgb"}, {SYSZ_INS_VLVGF, "vlvgf"}, + {SYSZ_INS_VLVGG, "vlvgg"}, {SYSZ_INS_VLVGH, "vlvgh"}, + {SYSZ_INS_VLVGP, "vlvgp"}, {SYSZ_INS_VMAE, "vmae"}, + {SYSZ_INS_VMAEB, "vmaeb"}, {SYSZ_INS_VMAEF, "vmaef"}, + {SYSZ_INS_VMAEH, "vmaeh"}, {SYSZ_INS_VMAH, "vmah"}, + {SYSZ_INS_VMAHB, "vmahb"}, {SYSZ_INS_VMAHF, "vmahf"}, + {SYSZ_INS_VMAHH, "vmahh"}, {SYSZ_INS_VMAL, "vmal"}, + {SYSZ_INS_VMALB, "vmalb"}, {SYSZ_INS_VMALE, "vmale"}, + {SYSZ_INS_VMALEB, "vmaleb"}, {SYSZ_INS_VMALEF, "vmalef"}, + {SYSZ_INS_VMALEH, "vmaleh"}, {SYSZ_INS_VMALF, "vmalf"}, + {SYSZ_INS_VMALH, "vmalh"}, {SYSZ_INS_VMALHB, "vmalhb"}, + {SYSZ_INS_VMALHF, "vmalhf"}, {SYSZ_INS_VMALHH, "vmalhh"}, + {SYSZ_INS_VMALHW, "vmalhw"}, {SYSZ_INS_VMALO, "vmalo"}, + {SYSZ_INS_VMALOB, "vmalob"}, {SYSZ_INS_VMALOF, "vmalof"}, + {SYSZ_INS_VMALOH, "vmaloh"}, {SYSZ_INS_VMAO, "vmao"}, + {SYSZ_INS_VMAOB, "vmaob"}, {SYSZ_INS_VMAOF, "vmaof"}, + {SYSZ_INS_VMAOH, "vmaoh"}, {SYSZ_INS_VME, "vme"}, {SYSZ_INS_VMEB, "vmeb"}, + {SYSZ_INS_VMEF, "vmef"}, {SYSZ_INS_VMEH, "vmeh"}, {SYSZ_INS_VMH, "vmh"}, + {SYSZ_INS_VMHB, "vmhb"}, {SYSZ_INS_VMHF, "vmhf"}, {SYSZ_INS_VMHH, "vmhh"}, + {SYSZ_INS_VML, "vml"}, {SYSZ_INS_VMLB, "vmlb"}, {SYSZ_INS_VMLE, "vmle"}, + {SYSZ_INS_VMLEB, "vmleb"}, {SYSZ_INS_VMLEF, "vmlef"}, + {SYSZ_INS_VMLEH, "vmleh"}, {SYSZ_INS_VMLF, "vmlf"}, {SYSZ_INS_VMLH, "vmlh"}, + {SYSZ_INS_VMLHB, "vmlhb"}, {SYSZ_INS_VMLHF, "vmlhf"}, + {SYSZ_INS_VMLHH, "vmlhh"}, {SYSZ_INS_VMLHW, "vmlhw"}, + {SYSZ_INS_VMLO, "vmlo"}, {SYSZ_INS_VMLOB, "vmlob"}, + {SYSZ_INS_VMLOF, "vmlof"}, {SYSZ_INS_VMLOH, "vmloh"}, {SYSZ_INS_VMN, "vmn"}, + {SYSZ_INS_VMNB, "vmnb"}, {SYSZ_INS_VMNF, "vmnf"}, {SYSZ_INS_VMNG, "vmng"}, + {SYSZ_INS_VMNH, "vmnh"}, {SYSZ_INS_VMNL, "vmnl"}, {SYSZ_INS_VMNLB, "vmnlb"}, + {SYSZ_INS_VMNLF, "vmnlf"}, {SYSZ_INS_VMNLG, "vmnlg"}, + {SYSZ_INS_VMNLH, "vmnlh"}, {SYSZ_INS_VMO, "vmo"}, {SYSZ_INS_VMOB, "vmob"}, + {SYSZ_INS_VMOF, "vmof"}, {SYSZ_INS_VMOH, "vmoh"}, {SYSZ_INS_VMP, "vmp"}, + {SYSZ_INS_VMRH, "vmrh"}, {SYSZ_INS_VMRHB, "vmrhb"}, + {SYSZ_INS_VMRHF, "vmrhf"}, {SYSZ_INS_VMRHG, "vmrhg"}, + {SYSZ_INS_VMRHH, "vmrhh"}, {SYSZ_INS_VMRL, "vmrl"}, + {SYSZ_INS_VMRLB, "vmrlb"}, {SYSZ_INS_VMRLF, "vmrlf"}, + {SYSZ_INS_VMRLG, "vmrlg"}, {SYSZ_INS_VMRLH, "vmrlh"}, + {SYSZ_INS_VMSL, "vmsl"}, {SYSZ_INS_VMSLG, "vmslg"}, {SYSZ_INS_VMSP, "vmsp"}, + {SYSZ_INS_VMX, "vmx"}, {SYSZ_INS_VMXB, "vmxb"}, {SYSZ_INS_VMXF, "vmxf"}, + {SYSZ_INS_VMXG, "vmxg"}, {SYSZ_INS_VMXH, "vmxh"}, {SYSZ_INS_VMXL, "vmxl"}, + {SYSZ_INS_VMXLB, "vmxlb"}, {SYSZ_INS_VMXLF, "vmxlf"}, + {SYSZ_INS_VMXLG, "vmxlg"}, {SYSZ_INS_VMXLH, "vmxlh"}, {SYSZ_INS_VN, "vn"}, + {SYSZ_INS_VNC, "vnc"}, {SYSZ_INS_VNN, "vnn"}, {SYSZ_INS_VNO, "vno"}, + {SYSZ_INS_VNX, "vnx"}, {SYSZ_INS_VO, "vo"}, {SYSZ_INS_VOC, "voc"}, + {SYSZ_INS_VONE, "vone"}, {SYSZ_INS_VPDI, "vpdi"}, {SYSZ_INS_VPERM, "vperm"}, + {SYSZ_INS_VPK, "vpk"}, {SYSZ_INS_VPKF, "vpkf"}, {SYSZ_INS_VPKG, "vpkg"}, + {SYSZ_INS_VPKH, "vpkh"}, {SYSZ_INS_VPKLS, "vpkls"}, + {SYSZ_INS_VPKLSF, "vpklsf"}, {SYSZ_INS_VPKLSFS, "vpklsfs"}, + {SYSZ_INS_VPKLSG, "vpklsg"}, {SYSZ_INS_VPKLSGS, "vpklsgs"}, + {SYSZ_INS_VPKLSH, "vpklsh"}, {SYSZ_INS_VPKLSHS, "vpklshs"}, + {SYSZ_INS_VPKS, "vpks"}, {SYSZ_INS_VPKSF, "vpksf"}, + {SYSZ_INS_VPKSFS, "vpksfs"}, {SYSZ_INS_VPKSG, "vpksg"}, + {SYSZ_INS_VPKSGS, "vpksgs"}, {SYSZ_INS_VPKSH, "vpksh"}, + {SYSZ_INS_VPKSHS, "vpkshs"}, {SYSZ_INS_VPKZ, "vpkz"}, + {SYSZ_INS_VPOPCT, "vpopct"}, {SYSZ_INS_VPOPCTB, "vpopctb"}, + {SYSZ_INS_VPOPCTF, "vpopctf"}, {SYSZ_INS_VPOPCTG, "vpopctg"}, + {SYSZ_INS_VPOPCTH, "vpopcth"}, {SYSZ_INS_VPSOP, "vpsop"}, + {SYSZ_INS_VREP, "vrep"}, {SYSZ_INS_VREPB, "vrepb"}, + {SYSZ_INS_VREPF, "vrepf"}, {SYSZ_INS_VREPG, "vrepg"}, + {SYSZ_INS_VREPH, "vreph"}, {SYSZ_INS_VREPI, "vrepi"}, + {SYSZ_INS_VREPIB, "vrepib"}, {SYSZ_INS_VREPIF, "vrepif"}, + {SYSZ_INS_VREPIG, "vrepig"}, {SYSZ_INS_VREPIH, "vrepih"}, + {SYSZ_INS_VRP, "vrp"}, {SYSZ_INS_VS, "vs"}, {SYSZ_INS_VSB, "vsb"}, + {SYSZ_INS_VSBCBI, "vsbcbi"}, {SYSZ_INS_VSBCBIQ, "vsbcbiq"}, + {SYSZ_INS_VSBI, "vsbi"}, {SYSZ_INS_VSBIQ, "vsbiq"}, + {SYSZ_INS_VSCBI, "vscbi"}, {SYSZ_INS_VSCBIB, "vscbib"}, + {SYSZ_INS_VSCBIF, "vscbif"}, {SYSZ_INS_VSCBIG, "vscbig"}, + {SYSZ_INS_VSCBIH, "vscbih"}, {SYSZ_INS_VSCBIQ, "vscbiq"}, + {SYSZ_INS_VSCEF, "vscef"}, {SYSZ_INS_VSCEG, "vsceg"}, + {SYSZ_INS_VSDP, "vsdp"}, {SYSZ_INS_VSEG, "vseg"}, {SYSZ_INS_VSEGB, "vsegb"}, + {SYSZ_INS_VSEGF, "vsegf"}, {SYSZ_INS_VSEGH, "vsegh"}, + {SYSZ_INS_VSEL, "vsel"}, {SYSZ_INS_VSF, "vsf"}, {SYSZ_INS_VSG, "vsg"}, + {SYSZ_INS_VSH, "vsh"}, {SYSZ_INS_VSL, "vsl"}, {SYSZ_INS_VSLB, "vslb"}, + {SYSZ_INS_VSLDB, "vsldb"}, {SYSZ_INS_VSP, "vsp"}, {SYSZ_INS_VSQ, "vsq"}, + {SYSZ_INS_VSRA, "vsra"}, {SYSZ_INS_VSRAB, "vsrab"}, {SYSZ_INS_VSRL, "vsrl"}, + {SYSZ_INS_VSRLB, "vsrlb"}, {SYSZ_INS_VSRP, "vsrp"}, {SYSZ_INS_VST, "vst"}, + {SYSZ_INS_VSTEB, "vsteb"}, {SYSZ_INS_VSTEF, "vstef"}, + {SYSZ_INS_VSTEG, "vsteg"}, {SYSZ_INS_VSTEH, "vsteh"}, + {SYSZ_INS_VSTL, "vstl"}, {SYSZ_INS_VSTM, "vstm"}, {SYSZ_INS_VSTRC, "vstrc"}, + {SYSZ_INS_VSTRCB, "vstrcb"}, {SYSZ_INS_VSTRCBS, "vstrcbs"}, + {SYSZ_INS_VSTRCF, "vstrcf"}, {SYSZ_INS_VSTRCFS, "vstrcfs"}, + {SYSZ_INS_VSTRCH, "vstrch"}, {SYSZ_INS_VSTRCHS, "vstrchs"}, + {SYSZ_INS_VSTRCZB, "vstrczb"}, {SYSZ_INS_VSTRCZBS, "vstrczbs"}, + {SYSZ_INS_VSTRCZF, "vstrczf"}, {SYSZ_INS_VSTRCZFS, "vstrczfs"}, + {SYSZ_INS_VSTRCZH, "vstrczh"}, {SYSZ_INS_VSTRCZHS, "vstrczhs"}, + {SYSZ_INS_VSTRL, "vstrl"}, {SYSZ_INS_VSTRLR, "vstrlr"}, + {SYSZ_INS_VSUM, "vsum"}, {SYSZ_INS_VSUMB, "vsumb"}, + {SYSZ_INS_VSUMG, "vsumg"}, {SYSZ_INS_VSUMGF, "vsumgf"}, + {SYSZ_INS_VSUMGH, "vsumgh"}, {SYSZ_INS_VSUMH, "vsumh"}, + {SYSZ_INS_VSUMQ, "vsumq"}, {SYSZ_INS_VSUMQF, "vsumqf"}, + {SYSZ_INS_VSUMQG, "vsumqg"}, {SYSZ_INS_VTM, "vtm"}, {SYSZ_INS_VTP, "vtp"}, + {SYSZ_INS_VUPH, "vuph"}, {SYSZ_INS_VUPHB, "vuphb"}, + {SYSZ_INS_VUPHF, "vuphf"}, {SYSZ_INS_VUPHH, "vuphh"}, + {SYSZ_INS_VUPKZ, "vupkz"}, {SYSZ_INS_VUPL, "vupl"}, + {SYSZ_INS_VUPLB, "vuplb"}, {SYSZ_INS_VUPLF, "vuplf"}, + {SYSZ_INS_VUPLH, "vuplh"}, {SYSZ_INS_VUPLHB, "vuplhb"}, + {SYSZ_INS_VUPLHF, "vuplhf"}, {SYSZ_INS_VUPLHH, "vuplhh"}, + {SYSZ_INS_VUPLHW, "vuplhw"}, {SYSZ_INS_VUPLL, "vupll"}, + {SYSZ_INS_VUPLLB, "vupllb"}, {SYSZ_INS_VUPLLF, "vupllf"}, + {SYSZ_INS_VUPLLH, "vupllh"}, {SYSZ_INS_VX, "vx"}, {SYSZ_INS_VZERO, "vzero"}, + {SYSZ_INS_WCDGB, "wcdgb"}, {SYSZ_INS_WCDLGB, "wcdlgb"}, + {SYSZ_INS_WCGDB, "wcgdb"}, {SYSZ_INS_WCLGDB, "wclgdb"}, + {SYSZ_INS_WFADB, "wfadb"}, {SYSZ_INS_WFASB, "wfasb"}, + {SYSZ_INS_WFAXB, "wfaxb"}, {SYSZ_INS_WFC, "wfc"}, {SYSZ_INS_WFCDB, "wfcdb"}, + {SYSZ_INS_WFCEDB, "wfcedb"}, {SYSZ_INS_WFCEDBS, "wfcedbs"}, + {SYSZ_INS_WFCESB, "wfcesb"}, {SYSZ_INS_WFCESBS, "wfcesbs"}, + {SYSZ_INS_WFCEXB, "wfcexb"}, {SYSZ_INS_WFCEXBS, "wfcexbs"}, + {SYSZ_INS_WFCHDB, "wfchdb"}, {SYSZ_INS_WFCHDBS, "wfchdbs"}, + {SYSZ_INS_WFCHEDB, "wfchedb"}, {SYSZ_INS_WFCHEDBS, "wfchedbs"}, + {SYSZ_INS_WFCHESB, "wfchesb"}, {SYSZ_INS_WFCHESBS, "wfchesbs"}, + {SYSZ_INS_WFCHEXB, "wfchexb"}, {SYSZ_INS_WFCHEXBS, "wfchexbs"}, + {SYSZ_INS_WFCHSB, "wfchsb"}, {SYSZ_INS_WFCHSBS, "wfchsbs"}, + {SYSZ_INS_WFCHXB, "wfchxb"}, {SYSZ_INS_WFCHXBS, "wfchxbs"}, + {SYSZ_INS_WFCSB, "wfcsb"}, {SYSZ_INS_WFCXB, "wfcxb"}, + {SYSZ_INS_WFDDB, "wfddb"}, {SYSZ_INS_WFDSB, "wfdsb"}, + {SYSZ_INS_WFDXB, "wfdxb"}, {SYSZ_INS_WFIDB, "wfidb"}, + {SYSZ_INS_WFISB, "wfisb"}, {SYSZ_INS_WFIXB, "wfixb"}, {SYSZ_INS_WFK, "wfk"}, + {SYSZ_INS_WFKDB, "wfkdb"}, {SYSZ_INS_WFKEDB, "wfkedb"}, + {SYSZ_INS_WFKEDBS, "wfkedbs"}, {SYSZ_INS_WFKESB, "wfkesb"}, + {SYSZ_INS_WFKESBS, "wfkesbs"}, {SYSZ_INS_WFKEXB, "wfkexb"}, + {SYSZ_INS_WFKEXBS, "wfkexbs"}, {SYSZ_INS_WFKHDB, "wfkhdb"}, + {SYSZ_INS_WFKHDBS, "wfkhdbs"}, {SYSZ_INS_WFKHEDB, "wfkhedb"}, + {SYSZ_INS_WFKHEDBS, "wfkhedbs"}, {SYSZ_INS_WFKHESB, "wfkhesb"}, + {SYSZ_INS_WFKHESBS, "wfkhesbs"}, {SYSZ_INS_WFKHEXB, "wfkhexb"}, + {SYSZ_INS_WFKHEXBS, "wfkhexbs"}, {SYSZ_INS_WFKHSB, "wfkhsb"}, + {SYSZ_INS_WFKHSBS, "wfkhsbs"}, {SYSZ_INS_WFKHXB, "wfkhxb"}, + {SYSZ_INS_WFKHXBS, "wfkhxbs"}, {SYSZ_INS_WFKSB, "wfksb"}, + {SYSZ_INS_WFKXB, "wfkxb"}, {SYSZ_INS_WFLCDB, "wflcdb"}, + {SYSZ_INS_WFLCSB, "wflcsb"}, {SYSZ_INS_WFLCXB, "wflcxb"}, + {SYSZ_INS_WFLLD, "wflld"}, {SYSZ_INS_WFLLS, "wflls"}, + {SYSZ_INS_WFLNDB, "wflndb"}, {SYSZ_INS_WFLNSB, "wflnsb"}, + {SYSZ_INS_WFLNXB, "wflnxb"}, {SYSZ_INS_WFLPDB, "wflpdb"}, + {SYSZ_INS_WFLPSB, "wflpsb"}, {SYSZ_INS_WFLPXB, "wflpxb"}, + {SYSZ_INS_WFLRD, "wflrd"}, {SYSZ_INS_WFLRX, "wflrx"}, + {SYSZ_INS_WFMADB, "wfmadb"}, {SYSZ_INS_WFMASB, "wfmasb"}, + {SYSZ_INS_WFMAXB, "wfmaxb"}, {SYSZ_INS_WFMAXDB, "wfmaxdb"}, + {SYSZ_INS_WFMAXSB, "wfmaxsb"}, {SYSZ_INS_WFMAXXB, "wfmaxxb"}, + {SYSZ_INS_WFMDB, "wfmdb"}, {SYSZ_INS_WFMINDB, "wfmindb"}, + {SYSZ_INS_WFMINSB, "wfminsb"}, {SYSZ_INS_WFMINXB, "wfminxb"}, + {SYSZ_INS_WFMSB, "wfmsb"}, {SYSZ_INS_WFMSDB, "wfmsdb"}, + {SYSZ_INS_WFMSSB, "wfmssb"}, {SYSZ_INS_WFMSXB, "wfmsxb"}, + {SYSZ_INS_WFMXB, "wfmxb"}, {SYSZ_INS_WFNMADB, "wfnmadb"}, + {SYSZ_INS_WFNMASB, "wfnmasb"}, {SYSZ_INS_WFNMAXB, "wfnmaxb"}, + {SYSZ_INS_WFNMSDB, "wfnmsdb"}, {SYSZ_INS_WFNMSSB, "wfnmssb"}, + {SYSZ_INS_WFNMSXB, "wfnmsxb"}, {SYSZ_INS_WFPSODB, "wfpsodb"}, + {SYSZ_INS_WFPSOSB, "wfpsosb"}, {SYSZ_INS_WFPSOXB, "wfpsoxb"}, + {SYSZ_INS_WFSDB, "wfsdb"}, {SYSZ_INS_WFSQDB, "wfsqdb"}, + {SYSZ_INS_WFSQSB, "wfsqsb"}, {SYSZ_INS_WFSQXB, "wfsqxb"}, + {SYSZ_INS_WFSSB, "wfssb"}, {SYSZ_INS_WFSXB, "wfsxb"}, + {SYSZ_INS_WFTCIDB, "wftcidb"}, {SYSZ_INS_WFTCISB, "wftcisb"}, + {SYSZ_INS_WFTCIXB, "wftcixb"}, {SYSZ_INS_WLDEB, "wldeb"}, + {SYSZ_INS_WLEDB, "wledb"}, {SYSZ_INS_XSCH, "xsch"}, {SYSZ_INS_ZAP, "zap"}, diff --git a/arch/SystemZ/SystemZGenInstrInfo.inc b/arch/SystemZ/SystemZGenInstrInfo.inc index 0f23556af9..7e838af325 100644 --- a/arch/SystemZ/SystemZGenInstrInfo.inc +++ b/arch/SystemZ/SystemZGenInstrInfo.inc @@ -9,2812 +9,2811 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ - #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { - SystemZ_PHI = 0, - SystemZ_INLINEASM = 1, - SystemZ_CFI_INSTRUCTION = 2, - SystemZ_EH_LABEL = 3, - SystemZ_GC_LABEL = 4, - SystemZ_ANNOTATION_LABEL = 5, - SystemZ_KILL = 6, - SystemZ_EXTRACT_SUBREG = 7, - SystemZ_INSERT_SUBREG = 8, - SystemZ_IMPLICIT_DEF = 9, - SystemZ_SUBREG_TO_REG = 10, - SystemZ_COPY_TO_REGCLASS = 11, - SystemZ_DBG_VALUE = 12, - SystemZ_DBG_LABEL = 13, - SystemZ_REG_SEQUENCE = 14, - SystemZ_COPY = 15, - SystemZ_BUNDLE = 16, - SystemZ_LIFETIME_START = 17, - SystemZ_LIFETIME_END = 18, - SystemZ_STACKMAP = 19, - SystemZ_FENTRY_CALL = 20, - SystemZ_PATCHPOINT = 21, - SystemZ_LOAD_STACK_GUARD = 22, - SystemZ_STATEPOINT = 23, - SystemZ_LOCAL_ESCAPE = 24, - SystemZ_FAULTING_OP = 25, - SystemZ_PATCHABLE_OP = 26, - SystemZ_PATCHABLE_FUNCTION_ENTER = 27, - SystemZ_PATCHABLE_RET = 28, - SystemZ_PATCHABLE_FUNCTION_EXIT = 29, - SystemZ_PATCHABLE_TAIL_CALL = 30, - SystemZ_PATCHABLE_EVENT_CALL = 31, - SystemZ_PATCHABLE_TYPED_EVENT_CALL = 32, - SystemZ_ICALL_BRANCH_FUNNEL = 33, - SystemZ_G_ADD = 34, - SystemZ_G_SUB = 35, - SystemZ_G_MUL = 36, - SystemZ_G_SDIV = 37, - SystemZ_G_UDIV = 38, - SystemZ_G_SREM = 39, - SystemZ_G_UREM = 40, - SystemZ_G_AND = 41, - SystemZ_G_OR = 42, - SystemZ_G_XOR = 43, - SystemZ_G_IMPLICIT_DEF = 44, - SystemZ_G_PHI = 45, - SystemZ_G_FRAME_INDEX = 46, - SystemZ_G_GLOBAL_VALUE = 47, - SystemZ_G_EXTRACT = 48, - SystemZ_G_UNMERGE_VALUES = 49, - SystemZ_G_INSERT = 50, - SystemZ_G_MERGE_VALUES = 51, - SystemZ_G_PTRTOINT = 52, - SystemZ_G_INTTOPTR = 53, - SystemZ_G_BITCAST = 54, - SystemZ_G_LOAD = 55, - SystemZ_G_SEXTLOAD = 56, - SystemZ_G_ZEXTLOAD = 57, - SystemZ_G_STORE = 58, - SystemZ_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, - SystemZ_G_ATOMIC_CMPXCHG = 60, - SystemZ_G_ATOMICRMW_XCHG = 61, - SystemZ_G_ATOMICRMW_ADD = 62, - SystemZ_G_ATOMICRMW_SUB = 63, - SystemZ_G_ATOMICRMW_AND = 64, - SystemZ_G_ATOMICRMW_NAND = 65, - SystemZ_G_ATOMICRMW_OR = 66, - SystemZ_G_ATOMICRMW_XOR = 67, - SystemZ_G_ATOMICRMW_MAX = 68, - SystemZ_G_ATOMICRMW_MIN = 69, - SystemZ_G_ATOMICRMW_UMAX = 70, - SystemZ_G_ATOMICRMW_UMIN = 71, - SystemZ_G_BRCOND = 72, - SystemZ_G_BRINDIRECT = 73, - SystemZ_G_INTRINSIC = 74, - SystemZ_G_INTRINSIC_W_SIDE_EFFECTS = 75, - SystemZ_G_ANYEXT = 76, - SystemZ_G_TRUNC = 77, - SystemZ_G_CONSTANT = 78, - SystemZ_G_FCONSTANT = 79, - SystemZ_G_VASTART = 80, - SystemZ_G_VAARG = 81, - SystemZ_G_SEXT = 82, - SystemZ_G_ZEXT = 83, - SystemZ_G_SHL = 84, - SystemZ_G_LSHR = 85, - SystemZ_G_ASHR = 86, - SystemZ_G_ICMP = 87, - SystemZ_G_FCMP = 88, - SystemZ_G_SELECT = 89, - SystemZ_G_UADDE = 90, - SystemZ_G_USUBE = 91, - SystemZ_G_SADDO = 92, - SystemZ_G_SSUBO = 93, - SystemZ_G_UMULO = 94, - SystemZ_G_SMULO = 95, - SystemZ_G_UMULH = 96, - SystemZ_G_SMULH = 97, - SystemZ_G_FADD = 98, - SystemZ_G_FSUB = 99, - SystemZ_G_FMUL = 100, - SystemZ_G_FMA = 101, - SystemZ_G_FDIV = 102, - SystemZ_G_FREM = 103, - SystemZ_G_FPOW = 104, - SystemZ_G_FEXP = 105, - SystemZ_G_FEXP2 = 106, - SystemZ_G_FLOG = 107, - SystemZ_G_FLOG2 = 108, - SystemZ_G_FNEG = 109, - SystemZ_G_FPEXT = 110, - SystemZ_G_FPTRUNC = 111, - SystemZ_G_FPTOSI = 112, - SystemZ_G_FPTOUI = 113, - SystemZ_G_SITOFP = 114, - SystemZ_G_UITOFP = 115, - SystemZ_G_FABS = 116, - SystemZ_G_GEP = 117, - SystemZ_G_PTR_MASK = 118, - SystemZ_G_BR = 119, - SystemZ_G_INSERT_VECTOR_ELT = 120, - SystemZ_G_EXTRACT_VECTOR_ELT = 121, - SystemZ_G_SHUFFLE_VECTOR = 122, - SystemZ_G_BSWAP = 123, - SystemZ_G_ADDRSPACE_CAST = 124, - SystemZ_ADJCALLSTACKDOWN = 125, - SystemZ_ADJCALLSTACKUP = 126, - SystemZ_ADJDYNALLOC = 127, - SystemZ_AEXT128 = 128, - SystemZ_AFIMux = 129, - SystemZ_AHIMux = 130, - SystemZ_AHIMuxK = 131, - SystemZ_ATOMIC_CMP_SWAPW = 132, - SystemZ_ATOMIC_LOADW_AFI = 133, - SystemZ_ATOMIC_LOADW_AR = 134, - SystemZ_ATOMIC_LOADW_MAX = 135, - SystemZ_ATOMIC_LOADW_MIN = 136, - SystemZ_ATOMIC_LOADW_NILH = 137, - SystemZ_ATOMIC_LOADW_NILHi = 138, - SystemZ_ATOMIC_LOADW_NR = 139, - SystemZ_ATOMIC_LOADW_NRi = 140, - SystemZ_ATOMIC_LOADW_OILH = 141, - SystemZ_ATOMIC_LOADW_OR = 142, - SystemZ_ATOMIC_LOADW_SR = 143, - SystemZ_ATOMIC_LOADW_UMAX = 144, - SystemZ_ATOMIC_LOADW_UMIN = 145, - SystemZ_ATOMIC_LOADW_XILF = 146, - SystemZ_ATOMIC_LOADW_XR = 147, - SystemZ_ATOMIC_LOAD_AFI = 148, - SystemZ_ATOMIC_LOAD_AGFI = 149, - SystemZ_ATOMIC_LOAD_AGHI = 150, - SystemZ_ATOMIC_LOAD_AGR = 151, - SystemZ_ATOMIC_LOAD_AHI = 152, - SystemZ_ATOMIC_LOAD_AR = 153, - SystemZ_ATOMIC_LOAD_MAX_32 = 154, - SystemZ_ATOMIC_LOAD_MAX_64 = 155, - SystemZ_ATOMIC_LOAD_MIN_32 = 156, - SystemZ_ATOMIC_LOAD_MIN_64 = 157, - SystemZ_ATOMIC_LOAD_NGR = 158, - SystemZ_ATOMIC_LOAD_NGRi = 159, - SystemZ_ATOMIC_LOAD_NIHF64 = 160, - SystemZ_ATOMIC_LOAD_NIHF64i = 161, - SystemZ_ATOMIC_LOAD_NIHH64 = 162, - SystemZ_ATOMIC_LOAD_NIHH64i = 163, - SystemZ_ATOMIC_LOAD_NIHL64 = 164, - SystemZ_ATOMIC_LOAD_NIHL64i = 165, - SystemZ_ATOMIC_LOAD_NILF = 166, - SystemZ_ATOMIC_LOAD_NILF64 = 167, - SystemZ_ATOMIC_LOAD_NILF64i = 168, - SystemZ_ATOMIC_LOAD_NILFi = 169, - SystemZ_ATOMIC_LOAD_NILH = 170, - SystemZ_ATOMIC_LOAD_NILH64 = 171, - SystemZ_ATOMIC_LOAD_NILH64i = 172, - SystemZ_ATOMIC_LOAD_NILHi = 173, - SystemZ_ATOMIC_LOAD_NILL = 174, - SystemZ_ATOMIC_LOAD_NILL64 = 175, - SystemZ_ATOMIC_LOAD_NILL64i = 176, - SystemZ_ATOMIC_LOAD_NILLi = 177, - SystemZ_ATOMIC_LOAD_NR = 178, - SystemZ_ATOMIC_LOAD_NRi = 179, - SystemZ_ATOMIC_LOAD_OGR = 180, - SystemZ_ATOMIC_LOAD_OIHF64 = 181, - SystemZ_ATOMIC_LOAD_OIHH64 = 182, - SystemZ_ATOMIC_LOAD_OIHL64 = 183, - SystemZ_ATOMIC_LOAD_OILF = 184, - SystemZ_ATOMIC_LOAD_OILF64 = 185, - SystemZ_ATOMIC_LOAD_OILH = 186, - SystemZ_ATOMIC_LOAD_OILH64 = 187, - SystemZ_ATOMIC_LOAD_OILL = 188, - SystemZ_ATOMIC_LOAD_OILL64 = 189, - SystemZ_ATOMIC_LOAD_OR = 190, - SystemZ_ATOMIC_LOAD_SGR = 191, - SystemZ_ATOMIC_LOAD_SR = 192, - SystemZ_ATOMIC_LOAD_UMAX_32 = 193, - SystemZ_ATOMIC_LOAD_UMAX_64 = 194, - SystemZ_ATOMIC_LOAD_UMIN_32 = 195, - SystemZ_ATOMIC_LOAD_UMIN_64 = 196, - SystemZ_ATOMIC_LOAD_XGR = 197, - SystemZ_ATOMIC_LOAD_XIHF64 = 198, - SystemZ_ATOMIC_LOAD_XILF = 199, - SystemZ_ATOMIC_LOAD_XILF64 = 200, - SystemZ_ATOMIC_LOAD_XR = 201, - SystemZ_ATOMIC_SWAPW = 202, - SystemZ_ATOMIC_SWAP_32 = 203, - SystemZ_ATOMIC_SWAP_64 = 204, - SystemZ_CFIMux = 205, - SystemZ_CGIBCall = 206, - SystemZ_CGIBReturn = 207, - SystemZ_CGRBCall = 208, - SystemZ_CGRBReturn = 209, - SystemZ_CHIMux = 210, - SystemZ_CIBCall = 211, - SystemZ_CIBReturn = 212, - SystemZ_CLCLoop = 213, - SystemZ_CLCSequence = 214, - SystemZ_CLFIMux = 215, - SystemZ_CLGIBCall = 216, - SystemZ_CLGIBReturn = 217, - SystemZ_CLGRBCall = 218, - SystemZ_CLGRBReturn = 219, - SystemZ_CLIBCall = 220, - SystemZ_CLIBReturn = 221, - SystemZ_CLMux = 222, - SystemZ_CLRBCall = 223, - SystemZ_CLRBReturn = 224, - SystemZ_CLSTLoop = 225, - SystemZ_CMux = 226, - SystemZ_CRBCall = 227, - SystemZ_CRBReturn = 228, - SystemZ_CallBASR = 229, - SystemZ_CallBCR = 230, - SystemZ_CallBR = 231, - SystemZ_CallBRASL = 232, - SystemZ_CallBRCL = 233, - SystemZ_CallJG = 234, - SystemZ_CondReturn = 235, - SystemZ_CondStore16 = 236, - SystemZ_CondStore16Inv = 237, - SystemZ_CondStore16Mux = 238, - SystemZ_CondStore16MuxInv = 239, - SystemZ_CondStore32 = 240, - SystemZ_CondStore32Inv = 241, - SystemZ_CondStore32Mux = 242, - SystemZ_CondStore32MuxInv = 243, - SystemZ_CondStore64 = 244, - SystemZ_CondStore64Inv = 245, - SystemZ_CondStore8 = 246, - SystemZ_CondStore8Inv = 247, - SystemZ_CondStore8Mux = 248, - SystemZ_CondStore8MuxInv = 249, - SystemZ_CondStoreF32 = 250, - SystemZ_CondStoreF32Inv = 251, - SystemZ_CondStoreF64 = 252, - SystemZ_CondStoreF64Inv = 253, - SystemZ_CondTrap = 254, - SystemZ_GOT = 255, - SystemZ_IIFMux = 256, - SystemZ_IIHF64 = 257, - SystemZ_IIHH64 = 258, - SystemZ_IIHL64 = 259, - SystemZ_IIHMux = 260, - SystemZ_IILF64 = 261, - SystemZ_IILH64 = 262, - SystemZ_IILL64 = 263, - SystemZ_IILMux = 264, - SystemZ_L128 = 265, - SystemZ_LBMux = 266, - SystemZ_LEFR = 267, - SystemZ_LFER = 268, - SystemZ_LHIMux = 269, - SystemZ_LHMux = 270, - SystemZ_LLCMux = 271, - SystemZ_LLCRMux = 272, - SystemZ_LLHMux = 273, - SystemZ_LLHRMux = 274, - SystemZ_LMux = 275, - SystemZ_LOCHIMux = 276, - SystemZ_LOCMux = 277, - SystemZ_LOCRMux = 278, - SystemZ_LRMux = 279, - SystemZ_LTDBRCompare_VecPseudo = 280, - SystemZ_LTEBRCompare_VecPseudo = 281, - SystemZ_LTXBRCompare_VecPseudo = 282, - SystemZ_LX = 283, - SystemZ_MVCLoop = 284, - SystemZ_MVCSequence = 285, - SystemZ_MVSTLoop = 286, - SystemZ_MemBarrier = 287, - SystemZ_NCLoop = 288, - SystemZ_NCSequence = 289, - SystemZ_NIFMux = 290, - SystemZ_NIHF64 = 291, - SystemZ_NIHH64 = 292, - SystemZ_NIHL64 = 293, - SystemZ_NIHMux = 294, - SystemZ_NILF64 = 295, - SystemZ_NILH64 = 296, - SystemZ_NILL64 = 297, - SystemZ_NILMux = 298, - SystemZ_OCLoop = 299, - SystemZ_OCSequence = 300, - SystemZ_OIFMux = 301, - SystemZ_OIHF64 = 302, - SystemZ_OIHH64 = 303, - SystemZ_OIHL64 = 304, - SystemZ_OIHMux = 305, - SystemZ_OILF64 = 306, - SystemZ_OILH64 = 307, - SystemZ_OILL64 = 308, - SystemZ_OILMux = 309, - SystemZ_PAIR128 = 310, - SystemZ_RISBHH = 311, - SystemZ_RISBHL = 312, - SystemZ_RISBLH = 313, - SystemZ_RISBLL = 314, - SystemZ_RISBMux = 315, - SystemZ_Return = 316, - SystemZ_SRSTLoop = 317, - SystemZ_ST128 = 318, - SystemZ_STCMux = 319, - SystemZ_STHMux = 320, - SystemZ_STMux = 321, - SystemZ_STOCMux = 322, - SystemZ_STX = 323, - SystemZ_Select32 = 324, - SystemZ_Select64 = 325, - SystemZ_SelectF128 = 326, - SystemZ_SelectF32 = 327, - SystemZ_SelectF64 = 328, - SystemZ_SelectVR128 = 329, - SystemZ_SelectVR32 = 330, - SystemZ_SelectVR64 = 331, - SystemZ_Serialize = 332, - SystemZ_TBEGIN_nofloat = 333, - SystemZ_TLS_GDCALL = 334, - SystemZ_TLS_LDCALL = 335, - SystemZ_TMHH64 = 336, - SystemZ_TMHL64 = 337, - SystemZ_TMHMux = 338, - SystemZ_TMLH64 = 339, - SystemZ_TMLL64 = 340, - SystemZ_TMLMux = 341, - SystemZ_Trap = 342, - SystemZ_VL32 = 343, - SystemZ_VL64 = 344, - SystemZ_VLR32 = 345, - SystemZ_VLR64 = 346, - SystemZ_VLVGP32 = 347, - SystemZ_VST32 = 348, - SystemZ_VST64 = 349, - SystemZ_XCLoop = 350, - SystemZ_XCSequence = 351, - SystemZ_XIFMux = 352, - SystemZ_XIHF64 = 353, - SystemZ_XILF64 = 354, - SystemZ_ZEXT128 = 355, - SystemZ_A = 356, - SystemZ_AD = 357, - SystemZ_ADB = 358, - SystemZ_ADBR = 359, - SystemZ_ADR = 360, - SystemZ_ADTR = 361, - SystemZ_ADTRA = 362, - SystemZ_AE = 363, - SystemZ_AEB = 364, - SystemZ_AEBR = 365, - SystemZ_AER = 366, - SystemZ_AFI = 367, - SystemZ_AG = 368, - SystemZ_AGF = 369, - SystemZ_AGFI = 370, - SystemZ_AGFR = 371, - SystemZ_AGH = 372, - SystemZ_AGHI = 373, - SystemZ_AGHIK = 374, - SystemZ_AGR = 375, - SystemZ_AGRK = 376, - SystemZ_AGSI = 377, - SystemZ_AH = 378, - SystemZ_AHHHR = 379, - SystemZ_AHHLR = 380, - SystemZ_AHI = 381, - SystemZ_AHIK = 382, - SystemZ_AHY = 383, - SystemZ_AIH = 384, - SystemZ_AL = 385, - SystemZ_ALC = 386, - SystemZ_ALCG = 387, - SystemZ_ALCGR = 388, - SystemZ_ALCR = 389, - SystemZ_ALFI = 390, - SystemZ_ALG = 391, - SystemZ_ALGF = 392, - SystemZ_ALGFI = 393, - SystemZ_ALGFR = 394, - SystemZ_ALGHSIK = 395, - SystemZ_ALGR = 396, - SystemZ_ALGRK = 397, - SystemZ_ALGSI = 398, - SystemZ_ALHHHR = 399, - SystemZ_ALHHLR = 400, - SystemZ_ALHSIK = 401, - SystemZ_ALR = 402, - SystemZ_ALRK = 403, - SystemZ_ALSI = 404, - SystemZ_ALSIH = 405, - SystemZ_ALSIHN = 406, - SystemZ_ALY = 407, - SystemZ_AP = 408, - SystemZ_AR = 409, - SystemZ_ARK = 410, - SystemZ_ASI = 411, - SystemZ_AU = 412, - SystemZ_AUR = 413, - SystemZ_AW = 414, - SystemZ_AWR = 415, - SystemZ_AXBR = 416, - SystemZ_AXR = 417, - SystemZ_AXTR = 418, - SystemZ_AXTRA = 419, - SystemZ_AY = 420, - SystemZ_B = 421, - SystemZ_BAKR = 422, - SystemZ_BAL = 423, - SystemZ_BALR = 424, - SystemZ_BAS = 425, - SystemZ_BASR = 426, - SystemZ_BASSM = 427, - SystemZ_BAsmE = 428, - SystemZ_BAsmH = 429, - SystemZ_BAsmHE = 430, - SystemZ_BAsmL = 431, - SystemZ_BAsmLE = 432, - SystemZ_BAsmLH = 433, - SystemZ_BAsmM = 434, - SystemZ_BAsmNE = 435, - SystemZ_BAsmNH = 436, - SystemZ_BAsmNHE = 437, - SystemZ_BAsmNL = 438, - SystemZ_BAsmNLE = 439, - SystemZ_BAsmNLH = 440, - SystemZ_BAsmNM = 441, - SystemZ_BAsmNO = 442, - SystemZ_BAsmNP = 443, - SystemZ_BAsmNZ = 444, - SystemZ_BAsmO = 445, - SystemZ_BAsmP = 446, - SystemZ_BAsmZ = 447, - SystemZ_BC = 448, - SystemZ_BCAsm = 449, - SystemZ_BCR = 450, - SystemZ_BCRAsm = 451, - SystemZ_BCT = 452, - SystemZ_BCTG = 453, - SystemZ_BCTGR = 454, - SystemZ_BCTR = 455, - SystemZ_BI = 456, - SystemZ_BIAsmE = 457, - SystemZ_BIAsmH = 458, - SystemZ_BIAsmHE = 459, - SystemZ_BIAsmL = 460, - SystemZ_BIAsmLE = 461, - SystemZ_BIAsmLH = 462, - SystemZ_BIAsmM = 463, - SystemZ_BIAsmNE = 464, - SystemZ_BIAsmNH = 465, - SystemZ_BIAsmNHE = 466, - SystemZ_BIAsmNL = 467, - SystemZ_BIAsmNLE = 468, - SystemZ_BIAsmNLH = 469, - SystemZ_BIAsmNM = 470, - SystemZ_BIAsmNO = 471, - SystemZ_BIAsmNP = 472, - SystemZ_BIAsmNZ = 473, - SystemZ_BIAsmO = 474, - SystemZ_BIAsmP = 475, - SystemZ_BIAsmZ = 476, - SystemZ_BIC = 477, - SystemZ_BICAsm = 478, - SystemZ_BPP = 479, - SystemZ_BPRP = 480, - SystemZ_BR = 481, - SystemZ_BRAS = 482, - SystemZ_BRASL = 483, - SystemZ_BRAsmE = 484, - SystemZ_BRAsmH = 485, - SystemZ_BRAsmHE = 486, - SystemZ_BRAsmL = 487, - SystemZ_BRAsmLE = 488, - SystemZ_BRAsmLH = 489, - SystemZ_BRAsmM = 490, - SystemZ_BRAsmNE = 491, - SystemZ_BRAsmNH = 492, - SystemZ_BRAsmNHE = 493, - SystemZ_BRAsmNL = 494, - SystemZ_BRAsmNLE = 495, - SystemZ_BRAsmNLH = 496, - SystemZ_BRAsmNM = 497, - SystemZ_BRAsmNO = 498, - SystemZ_BRAsmNP = 499, - SystemZ_BRAsmNZ = 500, - SystemZ_BRAsmO = 501, - SystemZ_BRAsmP = 502, - SystemZ_BRAsmZ = 503, - SystemZ_BRC = 504, - SystemZ_BRCAsm = 505, - SystemZ_BRCL = 506, - SystemZ_BRCLAsm = 507, - SystemZ_BRCT = 508, - SystemZ_BRCTG = 509, - SystemZ_BRCTH = 510, - SystemZ_BRXH = 511, - SystemZ_BRXHG = 512, - SystemZ_BRXLE = 513, - SystemZ_BRXLG = 514, - SystemZ_BSA = 515, - SystemZ_BSG = 516, - SystemZ_BSM = 517, - SystemZ_BXH = 518, - SystemZ_BXHG = 519, - SystemZ_BXLE = 520, - SystemZ_BXLEG = 521, - SystemZ_C = 522, - SystemZ_CD = 523, - SystemZ_CDB = 524, - SystemZ_CDBR = 525, - SystemZ_CDFBR = 526, - SystemZ_CDFBRA = 527, - SystemZ_CDFR = 528, - SystemZ_CDFTR = 529, - SystemZ_CDGBR = 530, - SystemZ_CDGBRA = 531, - SystemZ_CDGR = 532, - SystemZ_CDGTR = 533, - SystemZ_CDGTRA = 534, - SystemZ_CDLFBR = 535, - SystemZ_CDLFTR = 536, - SystemZ_CDLGBR = 537, - SystemZ_CDLGTR = 538, - SystemZ_CDPT = 539, - SystemZ_CDR = 540, - SystemZ_CDS = 541, - SystemZ_CDSG = 542, - SystemZ_CDSTR = 543, - SystemZ_CDSY = 544, - SystemZ_CDTR = 545, - SystemZ_CDUTR = 546, - SystemZ_CDZT = 547, - SystemZ_CE = 548, - SystemZ_CEB = 549, - SystemZ_CEBR = 550, - SystemZ_CEDTR = 551, - SystemZ_CEFBR = 552, - SystemZ_CEFBRA = 553, - SystemZ_CEFR = 554, - SystemZ_CEGBR = 555, - SystemZ_CEGBRA = 556, - SystemZ_CEGR = 557, - SystemZ_CELFBR = 558, - SystemZ_CELGBR = 559, - SystemZ_CER = 560, - SystemZ_CEXTR = 561, - SystemZ_CFC = 562, - SystemZ_CFDBR = 563, - SystemZ_CFDBRA = 564, - SystemZ_CFDR = 565, - SystemZ_CFDTR = 566, - SystemZ_CFEBR = 567, - SystemZ_CFEBRA = 568, - SystemZ_CFER = 569, - SystemZ_CFI = 570, - SystemZ_CFXBR = 571, - SystemZ_CFXBRA = 572, - SystemZ_CFXR = 573, - SystemZ_CFXTR = 574, - SystemZ_CG = 575, - SystemZ_CGDBR = 576, - SystemZ_CGDBRA = 577, - SystemZ_CGDR = 578, - SystemZ_CGDTR = 579, - SystemZ_CGDTRA = 580, - SystemZ_CGEBR = 581, - SystemZ_CGEBRA = 582, - SystemZ_CGER = 583, - SystemZ_CGF = 584, - SystemZ_CGFI = 585, - SystemZ_CGFR = 586, - SystemZ_CGFRL = 587, - SystemZ_CGH = 588, - SystemZ_CGHI = 589, - SystemZ_CGHRL = 590, - SystemZ_CGHSI = 591, - SystemZ_CGIB = 592, - SystemZ_CGIBAsm = 593, - SystemZ_CGIBAsmE = 594, - SystemZ_CGIBAsmH = 595, - SystemZ_CGIBAsmHE = 596, - SystemZ_CGIBAsmL = 597, - SystemZ_CGIBAsmLE = 598, - SystemZ_CGIBAsmLH = 599, - SystemZ_CGIBAsmNE = 600, - SystemZ_CGIBAsmNH = 601, - SystemZ_CGIBAsmNHE = 602, - SystemZ_CGIBAsmNL = 603, - SystemZ_CGIBAsmNLE = 604, - SystemZ_CGIBAsmNLH = 605, - SystemZ_CGIJ = 606, - SystemZ_CGIJAsm = 607, - SystemZ_CGIJAsmE = 608, - SystemZ_CGIJAsmH = 609, - SystemZ_CGIJAsmHE = 610, - SystemZ_CGIJAsmL = 611, - SystemZ_CGIJAsmLE = 612, - SystemZ_CGIJAsmLH = 613, - SystemZ_CGIJAsmNE = 614, - SystemZ_CGIJAsmNH = 615, - SystemZ_CGIJAsmNHE = 616, - SystemZ_CGIJAsmNL = 617, - SystemZ_CGIJAsmNLE = 618, - SystemZ_CGIJAsmNLH = 619, - SystemZ_CGIT = 620, - SystemZ_CGITAsm = 621, - SystemZ_CGITAsmE = 622, - SystemZ_CGITAsmH = 623, - SystemZ_CGITAsmHE = 624, - SystemZ_CGITAsmL = 625, - SystemZ_CGITAsmLE = 626, - SystemZ_CGITAsmLH = 627, - SystemZ_CGITAsmNE = 628, - SystemZ_CGITAsmNH = 629, - SystemZ_CGITAsmNHE = 630, - SystemZ_CGITAsmNL = 631, - SystemZ_CGITAsmNLE = 632, - SystemZ_CGITAsmNLH = 633, - SystemZ_CGR = 634, - SystemZ_CGRB = 635, - SystemZ_CGRBAsm = 636, - SystemZ_CGRBAsmE = 637, - SystemZ_CGRBAsmH = 638, - SystemZ_CGRBAsmHE = 639, - SystemZ_CGRBAsmL = 640, - SystemZ_CGRBAsmLE = 641, - SystemZ_CGRBAsmLH = 642, - SystemZ_CGRBAsmNE = 643, - SystemZ_CGRBAsmNH = 644, - SystemZ_CGRBAsmNHE = 645, - SystemZ_CGRBAsmNL = 646, - SystemZ_CGRBAsmNLE = 647, - SystemZ_CGRBAsmNLH = 648, - SystemZ_CGRJ = 649, - SystemZ_CGRJAsm = 650, - SystemZ_CGRJAsmE = 651, - SystemZ_CGRJAsmH = 652, - SystemZ_CGRJAsmHE = 653, - SystemZ_CGRJAsmL = 654, - SystemZ_CGRJAsmLE = 655, - SystemZ_CGRJAsmLH = 656, - SystemZ_CGRJAsmNE = 657, - SystemZ_CGRJAsmNH = 658, - SystemZ_CGRJAsmNHE = 659, - SystemZ_CGRJAsmNL = 660, - SystemZ_CGRJAsmNLE = 661, - SystemZ_CGRJAsmNLH = 662, - SystemZ_CGRL = 663, - SystemZ_CGRT = 664, - SystemZ_CGRTAsm = 665, - SystemZ_CGRTAsmE = 666, - SystemZ_CGRTAsmH = 667, - SystemZ_CGRTAsmHE = 668, - SystemZ_CGRTAsmL = 669, - SystemZ_CGRTAsmLE = 670, - SystemZ_CGRTAsmLH = 671, - SystemZ_CGRTAsmNE = 672, - SystemZ_CGRTAsmNH = 673, - SystemZ_CGRTAsmNHE = 674, - SystemZ_CGRTAsmNL = 675, - SystemZ_CGRTAsmNLE = 676, - SystemZ_CGRTAsmNLH = 677, - SystemZ_CGXBR = 678, - SystemZ_CGXBRA = 679, - SystemZ_CGXR = 680, - SystemZ_CGXTR = 681, - SystemZ_CGXTRA = 682, - SystemZ_CH = 683, - SystemZ_CHF = 684, - SystemZ_CHHR = 685, - SystemZ_CHHSI = 686, - SystemZ_CHI = 687, - SystemZ_CHLR = 688, - SystemZ_CHRL = 689, - SystemZ_CHSI = 690, - SystemZ_CHY = 691, - SystemZ_CIB = 692, - SystemZ_CIBAsm = 693, - SystemZ_CIBAsmE = 694, - SystemZ_CIBAsmH = 695, - SystemZ_CIBAsmHE = 696, - SystemZ_CIBAsmL = 697, - SystemZ_CIBAsmLE = 698, - SystemZ_CIBAsmLH = 699, - SystemZ_CIBAsmNE = 700, - SystemZ_CIBAsmNH = 701, - SystemZ_CIBAsmNHE = 702, - SystemZ_CIBAsmNL = 703, - SystemZ_CIBAsmNLE = 704, - SystemZ_CIBAsmNLH = 705, - SystemZ_CIH = 706, - SystemZ_CIJ = 707, - SystemZ_CIJAsm = 708, - SystemZ_CIJAsmE = 709, - SystemZ_CIJAsmH = 710, - SystemZ_CIJAsmHE = 711, - SystemZ_CIJAsmL = 712, - SystemZ_CIJAsmLE = 713, - SystemZ_CIJAsmLH = 714, - SystemZ_CIJAsmNE = 715, - SystemZ_CIJAsmNH = 716, - SystemZ_CIJAsmNHE = 717, - SystemZ_CIJAsmNL = 718, - SystemZ_CIJAsmNLE = 719, - SystemZ_CIJAsmNLH = 720, - SystemZ_CIT = 721, - SystemZ_CITAsm = 722, - SystemZ_CITAsmE = 723, - SystemZ_CITAsmH = 724, - SystemZ_CITAsmHE = 725, - SystemZ_CITAsmL = 726, - SystemZ_CITAsmLE = 727, - SystemZ_CITAsmLH = 728, - SystemZ_CITAsmNE = 729, - SystemZ_CITAsmNH = 730, - SystemZ_CITAsmNHE = 731, - SystemZ_CITAsmNL = 732, - SystemZ_CITAsmNLE = 733, - SystemZ_CITAsmNLH = 734, - SystemZ_CKSM = 735, - SystemZ_CL = 736, - SystemZ_CLC = 737, - SystemZ_CLCL = 738, - SystemZ_CLCLE = 739, - SystemZ_CLCLU = 740, - SystemZ_CLFDBR = 741, - SystemZ_CLFDTR = 742, - SystemZ_CLFEBR = 743, - SystemZ_CLFHSI = 744, - SystemZ_CLFI = 745, - SystemZ_CLFIT = 746, - SystemZ_CLFITAsm = 747, - SystemZ_CLFITAsmE = 748, - SystemZ_CLFITAsmH = 749, - SystemZ_CLFITAsmHE = 750, - SystemZ_CLFITAsmL = 751, - SystemZ_CLFITAsmLE = 752, - SystemZ_CLFITAsmLH = 753, - SystemZ_CLFITAsmNE = 754, - SystemZ_CLFITAsmNH = 755, - SystemZ_CLFITAsmNHE = 756, - SystemZ_CLFITAsmNL = 757, - SystemZ_CLFITAsmNLE = 758, - SystemZ_CLFITAsmNLH = 759, - SystemZ_CLFXBR = 760, - SystemZ_CLFXTR = 761, - SystemZ_CLG = 762, - SystemZ_CLGDBR = 763, - SystemZ_CLGDTR = 764, - SystemZ_CLGEBR = 765, - SystemZ_CLGF = 766, - SystemZ_CLGFI = 767, - SystemZ_CLGFR = 768, - SystemZ_CLGFRL = 769, - SystemZ_CLGHRL = 770, - SystemZ_CLGHSI = 771, - SystemZ_CLGIB = 772, - SystemZ_CLGIBAsm = 773, - SystemZ_CLGIBAsmE = 774, - SystemZ_CLGIBAsmH = 775, - SystemZ_CLGIBAsmHE = 776, - SystemZ_CLGIBAsmL = 777, - SystemZ_CLGIBAsmLE = 778, - SystemZ_CLGIBAsmLH = 779, - SystemZ_CLGIBAsmNE = 780, - SystemZ_CLGIBAsmNH = 781, - SystemZ_CLGIBAsmNHE = 782, - SystemZ_CLGIBAsmNL = 783, - SystemZ_CLGIBAsmNLE = 784, - SystemZ_CLGIBAsmNLH = 785, - SystemZ_CLGIJ = 786, - SystemZ_CLGIJAsm = 787, - SystemZ_CLGIJAsmE = 788, - SystemZ_CLGIJAsmH = 789, - SystemZ_CLGIJAsmHE = 790, - SystemZ_CLGIJAsmL = 791, - SystemZ_CLGIJAsmLE = 792, - SystemZ_CLGIJAsmLH = 793, - SystemZ_CLGIJAsmNE = 794, - SystemZ_CLGIJAsmNH = 795, - SystemZ_CLGIJAsmNHE = 796, - SystemZ_CLGIJAsmNL = 797, - SystemZ_CLGIJAsmNLE = 798, - SystemZ_CLGIJAsmNLH = 799, - SystemZ_CLGIT = 800, - SystemZ_CLGITAsm = 801, - SystemZ_CLGITAsmE = 802, - SystemZ_CLGITAsmH = 803, - SystemZ_CLGITAsmHE = 804, - SystemZ_CLGITAsmL = 805, - SystemZ_CLGITAsmLE = 806, - SystemZ_CLGITAsmLH = 807, - SystemZ_CLGITAsmNE = 808, - SystemZ_CLGITAsmNH = 809, - SystemZ_CLGITAsmNHE = 810, - SystemZ_CLGITAsmNL = 811, - SystemZ_CLGITAsmNLE = 812, - SystemZ_CLGITAsmNLH = 813, - SystemZ_CLGR = 814, - SystemZ_CLGRB = 815, - SystemZ_CLGRBAsm = 816, - SystemZ_CLGRBAsmE = 817, - SystemZ_CLGRBAsmH = 818, - SystemZ_CLGRBAsmHE = 819, - SystemZ_CLGRBAsmL = 820, - SystemZ_CLGRBAsmLE = 821, - SystemZ_CLGRBAsmLH = 822, - SystemZ_CLGRBAsmNE = 823, - SystemZ_CLGRBAsmNH = 824, - SystemZ_CLGRBAsmNHE = 825, - SystemZ_CLGRBAsmNL = 826, - SystemZ_CLGRBAsmNLE = 827, - SystemZ_CLGRBAsmNLH = 828, - SystemZ_CLGRJ = 829, - SystemZ_CLGRJAsm = 830, - SystemZ_CLGRJAsmE = 831, - SystemZ_CLGRJAsmH = 832, - SystemZ_CLGRJAsmHE = 833, - SystemZ_CLGRJAsmL = 834, - SystemZ_CLGRJAsmLE = 835, - SystemZ_CLGRJAsmLH = 836, - SystemZ_CLGRJAsmNE = 837, - SystemZ_CLGRJAsmNH = 838, - SystemZ_CLGRJAsmNHE = 839, - SystemZ_CLGRJAsmNL = 840, - SystemZ_CLGRJAsmNLE = 841, - SystemZ_CLGRJAsmNLH = 842, - SystemZ_CLGRL = 843, - SystemZ_CLGRT = 844, - SystemZ_CLGRTAsm = 845, - SystemZ_CLGRTAsmE = 846, - SystemZ_CLGRTAsmH = 847, - SystemZ_CLGRTAsmHE = 848, - SystemZ_CLGRTAsmL = 849, - SystemZ_CLGRTAsmLE = 850, - SystemZ_CLGRTAsmLH = 851, - SystemZ_CLGRTAsmNE = 852, - SystemZ_CLGRTAsmNH = 853, - SystemZ_CLGRTAsmNHE = 854, - SystemZ_CLGRTAsmNL = 855, - SystemZ_CLGRTAsmNLE = 856, - SystemZ_CLGRTAsmNLH = 857, - SystemZ_CLGT = 858, - SystemZ_CLGTAsm = 859, - SystemZ_CLGTAsmE = 860, - SystemZ_CLGTAsmH = 861, - SystemZ_CLGTAsmHE = 862, - SystemZ_CLGTAsmL = 863, - SystemZ_CLGTAsmLE = 864, - SystemZ_CLGTAsmLH = 865, - SystemZ_CLGTAsmNE = 866, - SystemZ_CLGTAsmNH = 867, - SystemZ_CLGTAsmNHE = 868, - SystemZ_CLGTAsmNL = 869, - SystemZ_CLGTAsmNLE = 870, - SystemZ_CLGTAsmNLH = 871, - SystemZ_CLGXBR = 872, - SystemZ_CLGXTR = 873, - SystemZ_CLHF = 874, - SystemZ_CLHHR = 875, - SystemZ_CLHHSI = 876, - SystemZ_CLHLR = 877, - SystemZ_CLHRL = 878, - SystemZ_CLI = 879, - SystemZ_CLIB = 880, - SystemZ_CLIBAsm = 881, - SystemZ_CLIBAsmE = 882, - SystemZ_CLIBAsmH = 883, - SystemZ_CLIBAsmHE = 884, - SystemZ_CLIBAsmL = 885, - SystemZ_CLIBAsmLE = 886, - SystemZ_CLIBAsmLH = 887, - SystemZ_CLIBAsmNE = 888, - SystemZ_CLIBAsmNH = 889, - SystemZ_CLIBAsmNHE = 890, - SystemZ_CLIBAsmNL = 891, - SystemZ_CLIBAsmNLE = 892, - SystemZ_CLIBAsmNLH = 893, - SystemZ_CLIH = 894, - SystemZ_CLIJ = 895, - SystemZ_CLIJAsm = 896, - SystemZ_CLIJAsmE = 897, - SystemZ_CLIJAsmH = 898, - SystemZ_CLIJAsmHE = 899, - SystemZ_CLIJAsmL = 900, - SystemZ_CLIJAsmLE = 901, - SystemZ_CLIJAsmLH = 902, - SystemZ_CLIJAsmNE = 903, - SystemZ_CLIJAsmNH = 904, - SystemZ_CLIJAsmNHE = 905, - SystemZ_CLIJAsmNL = 906, - SystemZ_CLIJAsmNLE = 907, - SystemZ_CLIJAsmNLH = 908, - SystemZ_CLIY = 909, - SystemZ_CLM = 910, - SystemZ_CLMH = 911, - SystemZ_CLMY = 912, - SystemZ_CLR = 913, - SystemZ_CLRB = 914, - SystemZ_CLRBAsm = 915, - SystemZ_CLRBAsmE = 916, - SystemZ_CLRBAsmH = 917, - SystemZ_CLRBAsmHE = 918, - SystemZ_CLRBAsmL = 919, - SystemZ_CLRBAsmLE = 920, - SystemZ_CLRBAsmLH = 921, - SystemZ_CLRBAsmNE = 922, - SystemZ_CLRBAsmNH = 923, - SystemZ_CLRBAsmNHE = 924, - SystemZ_CLRBAsmNL = 925, - SystemZ_CLRBAsmNLE = 926, - SystemZ_CLRBAsmNLH = 927, - SystemZ_CLRJ = 928, - SystemZ_CLRJAsm = 929, - SystemZ_CLRJAsmE = 930, - SystemZ_CLRJAsmH = 931, - SystemZ_CLRJAsmHE = 932, - SystemZ_CLRJAsmL = 933, - SystemZ_CLRJAsmLE = 934, - SystemZ_CLRJAsmLH = 935, - SystemZ_CLRJAsmNE = 936, - SystemZ_CLRJAsmNH = 937, - SystemZ_CLRJAsmNHE = 938, - SystemZ_CLRJAsmNL = 939, - SystemZ_CLRJAsmNLE = 940, - SystemZ_CLRJAsmNLH = 941, - SystemZ_CLRL = 942, - SystemZ_CLRT = 943, - SystemZ_CLRTAsm = 944, - SystemZ_CLRTAsmE = 945, - SystemZ_CLRTAsmH = 946, - SystemZ_CLRTAsmHE = 947, - SystemZ_CLRTAsmL = 948, - SystemZ_CLRTAsmLE = 949, - SystemZ_CLRTAsmLH = 950, - SystemZ_CLRTAsmNE = 951, - SystemZ_CLRTAsmNH = 952, - SystemZ_CLRTAsmNHE = 953, - SystemZ_CLRTAsmNL = 954, - SystemZ_CLRTAsmNLE = 955, - SystemZ_CLRTAsmNLH = 956, - SystemZ_CLST = 957, - SystemZ_CLT = 958, - SystemZ_CLTAsm = 959, - SystemZ_CLTAsmE = 960, - SystemZ_CLTAsmH = 961, - SystemZ_CLTAsmHE = 962, - SystemZ_CLTAsmL = 963, - SystemZ_CLTAsmLE = 964, - SystemZ_CLTAsmLH = 965, - SystemZ_CLTAsmNE = 966, - SystemZ_CLTAsmNH = 967, - SystemZ_CLTAsmNHE = 968, - SystemZ_CLTAsmNL = 969, - SystemZ_CLTAsmNLE = 970, - SystemZ_CLTAsmNLH = 971, - SystemZ_CLY = 972, - SystemZ_CMPSC = 973, - SystemZ_CP = 974, - SystemZ_CPDT = 975, - SystemZ_CPSDRdd = 976, - SystemZ_CPSDRds = 977, - SystemZ_CPSDRsd = 978, - SystemZ_CPSDRss = 979, - SystemZ_CPXT = 980, - SystemZ_CPYA = 981, - SystemZ_CR = 982, - SystemZ_CRB = 983, - SystemZ_CRBAsm = 984, - SystemZ_CRBAsmE = 985, - SystemZ_CRBAsmH = 986, - SystemZ_CRBAsmHE = 987, - SystemZ_CRBAsmL = 988, - SystemZ_CRBAsmLE = 989, - SystemZ_CRBAsmLH = 990, - SystemZ_CRBAsmNE = 991, - SystemZ_CRBAsmNH = 992, - SystemZ_CRBAsmNHE = 993, - SystemZ_CRBAsmNL = 994, - SystemZ_CRBAsmNLE = 995, - SystemZ_CRBAsmNLH = 996, - SystemZ_CRDTE = 997, - SystemZ_CRDTEOpt = 998, - SystemZ_CRJ = 999, - SystemZ_CRJAsm = 1000, - SystemZ_CRJAsmE = 1001, - SystemZ_CRJAsmH = 1002, - SystemZ_CRJAsmHE = 1003, - SystemZ_CRJAsmL = 1004, - SystemZ_CRJAsmLE = 1005, - SystemZ_CRJAsmLH = 1006, - SystemZ_CRJAsmNE = 1007, - SystemZ_CRJAsmNH = 1008, - SystemZ_CRJAsmNHE = 1009, - SystemZ_CRJAsmNL = 1010, - SystemZ_CRJAsmNLE = 1011, - SystemZ_CRJAsmNLH = 1012, - SystemZ_CRL = 1013, - SystemZ_CRT = 1014, - SystemZ_CRTAsm = 1015, - SystemZ_CRTAsmE = 1016, - SystemZ_CRTAsmH = 1017, - SystemZ_CRTAsmHE = 1018, - SystemZ_CRTAsmL = 1019, - SystemZ_CRTAsmLE = 1020, - SystemZ_CRTAsmLH = 1021, - SystemZ_CRTAsmNE = 1022, - SystemZ_CRTAsmNH = 1023, - SystemZ_CRTAsmNHE = 1024, - SystemZ_CRTAsmNL = 1025, - SystemZ_CRTAsmNLE = 1026, - SystemZ_CRTAsmNLH = 1027, - SystemZ_CS = 1028, - SystemZ_CSCH = 1029, - SystemZ_CSDTR = 1030, - SystemZ_CSG = 1031, - SystemZ_CSP = 1032, - SystemZ_CSPG = 1033, - SystemZ_CSST = 1034, - SystemZ_CSXTR = 1035, - SystemZ_CSY = 1036, - SystemZ_CU12 = 1037, - SystemZ_CU12Opt = 1038, - SystemZ_CU14 = 1039, - SystemZ_CU14Opt = 1040, - SystemZ_CU21 = 1041, - SystemZ_CU21Opt = 1042, - SystemZ_CU24 = 1043, - SystemZ_CU24Opt = 1044, - SystemZ_CU41 = 1045, - SystemZ_CU42 = 1046, - SystemZ_CUDTR = 1047, - SystemZ_CUSE = 1048, - SystemZ_CUTFU = 1049, - SystemZ_CUTFUOpt = 1050, - SystemZ_CUUTF = 1051, - SystemZ_CUUTFOpt = 1052, - SystemZ_CUXTR = 1053, - SystemZ_CVB = 1054, - SystemZ_CVBG = 1055, - SystemZ_CVBY = 1056, - SystemZ_CVD = 1057, - SystemZ_CVDG = 1058, - SystemZ_CVDY = 1059, - SystemZ_CXBR = 1060, - SystemZ_CXFBR = 1061, - SystemZ_CXFBRA = 1062, - SystemZ_CXFR = 1063, - SystemZ_CXFTR = 1064, - SystemZ_CXGBR = 1065, - SystemZ_CXGBRA = 1066, - SystemZ_CXGR = 1067, - SystemZ_CXGTR = 1068, - SystemZ_CXGTRA = 1069, - SystemZ_CXLFBR = 1070, - SystemZ_CXLFTR = 1071, - SystemZ_CXLGBR = 1072, - SystemZ_CXLGTR = 1073, - SystemZ_CXPT = 1074, - SystemZ_CXR = 1075, - SystemZ_CXSTR = 1076, - SystemZ_CXTR = 1077, - SystemZ_CXUTR = 1078, - SystemZ_CXZT = 1079, - SystemZ_CY = 1080, - SystemZ_CZDT = 1081, - SystemZ_CZXT = 1082, - SystemZ_D = 1083, - SystemZ_DD = 1084, - SystemZ_DDB = 1085, - SystemZ_DDBR = 1086, - SystemZ_DDR = 1087, - SystemZ_DDTR = 1088, - SystemZ_DDTRA = 1089, - SystemZ_DE = 1090, - SystemZ_DEB = 1091, - SystemZ_DEBR = 1092, - SystemZ_DER = 1093, - SystemZ_DIAG = 1094, - SystemZ_DIDBR = 1095, - SystemZ_DIEBR = 1096, - SystemZ_DL = 1097, - SystemZ_DLG = 1098, - SystemZ_DLGR = 1099, - SystemZ_DLR = 1100, - SystemZ_DP = 1101, - SystemZ_DR = 1102, - SystemZ_DSG = 1103, - SystemZ_DSGF = 1104, - SystemZ_DSGFR = 1105, - SystemZ_DSGR = 1106, - SystemZ_DXBR = 1107, - SystemZ_DXR = 1108, - SystemZ_DXTR = 1109, - SystemZ_DXTRA = 1110, - SystemZ_EAR = 1111, - SystemZ_ECAG = 1112, - SystemZ_ECCTR = 1113, - SystemZ_ECPGA = 1114, - SystemZ_ECTG = 1115, - SystemZ_ED = 1116, - SystemZ_EDMK = 1117, - SystemZ_EEDTR = 1118, - SystemZ_EEXTR = 1119, - SystemZ_EFPC = 1120, - SystemZ_EPAIR = 1121, - SystemZ_EPAR = 1122, - SystemZ_EPCTR = 1123, - SystemZ_EPSW = 1124, - SystemZ_EREG = 1125, - SystemZ_EREGG = 1126, - SystemZ_ESAIR = 1127, - SystemZ_ESAR = 1128, - SystemZ_ESDTR = 1129, - SystemZ_ESEA = 1130, - SystemZ_ESTA = 1131, - SystemZ_ESXTR = 1132, - SystemZ_ETND = 1133, - SystemZ_EX = 1134, - SystemZ_EXRL = 1135, - SystemZ_FIDBR = 1136, - SystemZ_FIDBRA = 1137, - SystemZ_FIDR = 1138, - SystemZ_FIDTR = 1139, - SystemZ_FIEBR = 1140, - SystemZ_FIEBRA = 1141, - SystemZ_FIER = 1142, - SystemZ_FIXBR = 1143, - SystemZ_FIXBRA = 1144, - SystemZ_FIXR = 1145, - SystemZ_FIXTR = 1146, - SystemZ_FLOGR = 1147, - SystemZ_HDR = 1148, - SystemZ_HER = 1149, - SystemZ_HSCH = 1150, - SystemZ_IAC = 1151, - SystemZ_IC = 1152, - SystemZ_IC32 = 1153, - SystemZ_IC32Y = 1154, - SystemZ_ICM = 1155, - SystemZ_ICMH = 1156, - SystemZ_ICMY = 1157, - SystemZ_ICY = 1158, - SystemZ_IDTE = 1159, - SystemZ_IDTEOpt = 1160, - SystemZ_IEDTR = 1161, - SystemZ_IEXTR = 1162, - SystemZ_IIHF = 1163, - SystemZ_IIHH = 1164, - SystemZ_IIHL = 1165, - SystemZ_IILF = 1166, - SystemZ_IILH = 1167, - SystemZ_IILL = 1168, - SystemZ_IPK = 1169, - SystemZ_IPM = 1170, - SystemZ_IPTE = 1171, - SystemZ_IPTEOpt = 1172, - SystemZ_IPTEOptOpt = 1173, - SystemZ_IRBM = 1174, - SystemZ_ISKE = 1175, - SystemZ_IVSK = 1176, - SystemZ_InsnE = 1177, - SystemZ_InsnRI = 1178, - SystemZ_InsnRIE = 1179, - SystemZ_InsnRIL = 1180, - SystemZ_InsnRILU = 1181, - SystemZ_InsnRIS = 1182, - SystemZ_InsnRR = 1183, - SystemZ_InsnRRE = 1184, - SystemZ_InsnRRF = 1185, - SystemZ_InsnRRS = 1186, - SystemZ_InsnRS = 1187, - SystemZ_InsnRSE = 1188, - SystemZ_InsnRSI = 1189, - SystemZ_InsnRSY = 1190, - SystemZ_InsnRX = 1191, - SystemZ_InsnRXE = 1192, - SystemZ_InsnRXF = 1193, - SystemZ_InsnRXY = 1194, - SystemZ_InsnS = 1195, - SystemZ_InsnSI = 1196, - SystemZ_InsnSIL = 1197, - SystemZ_InsnSIY = 1198, - SystemZ_InsnSS = 1199, - SystemZ_InsnSSE = 1200, - SystemZ_InsnSSF = 1201, - SystemZ_J = 1202, - SystemZ_JAsmE = 1203, - SystemZ_JAsmH = 1204, - SystemZ_JAsmHE = 1205, - SystemZ_JAsmL = 1206, - SystemZ_JAsmLE = 1207, - SystemZ_JAsmLH = 1208, - SystemZ_JAsmM = 1209, - SystemZ_JAsmNE = 1210, - SystemZ_JAsmNH = 1211, - SystemZ_JAsmNHE = 1212, - SystemZ_JAsmNL = 1213, - SystemZ_JAsmNLE = 1214, - SystemZ_JAsmNLH = 1215, - SystemZ_JAsmNM = 1216, - SystemZ_JAsmNO = 1217, - SystemZ_JAsmNP = 1218, - SystemZ_JAsmNZ = 1219, - SystemZ_JAsmO = 1220, - SystemZ_JAsmP = 1221, - SystemZ_JAsmZ = 1222, - SystemZ_JG = 1223, - SystemZ_JGAsmE = 1224, - SystemZ_JGAsmH = 1225, - SystemZ_JGAsmHE = 1226, - SystemZ_JGAsmL = 1227, - SystemZ_JGAsmLE = 1228, - SystemZ_JGAsmLH = 1229, - SystemZ_JGAsmM = 1230, - SystemZ_JGAsmNE = 1231, - SystemZ_JGAsmNH = 1232, - SystemZ_JGAsmNHE = 1233, - SystemZ_JGAsmNL = 1234, - SystemZ_JGAsmNLE = 1235, - SystemZ_JGAsmNLH = 1236, - SystemZ_JGAsmNM = 1237, - SystemZ_JGAsmNO = 1238, - SystemZ_JGAsmNP = 1239, - SystemZ_JGAsmNZ = 1240, - SystemZ_JGAsmO = 1241, - SystemZ_JGAsmP = 1242, - SystemZ_JGAsmZ = 1243, - SystemZ_KDB = 1244, - SystemZ_KDBR = 1245, - SystemZ_KDTR = 1246, - SystemZ_KEB = 1247, - SystemZ_KEBR = 1248, - SystemZ_KIMD = 1249, - SystemZ_KLMD = 1250, - SystemZ_KM = 1251, - SystemZ_KMA = 1252, - SystemZ_KMAC = 1253, - SystemZ_KMC = 1254, - SystemZ_KMCTR = 1255, - SystemZ_KMF = 1256, - SystemZ_KMO = 1257, - SystemZ_KXBR = 1258, - SystemZ_KXTR = 1259, - SystemZ_L = 1260, - SystemZ_LA = 1261, - SystemZ_LAA = 1262, - SystemZ_LAAG = 1263, - SystemZ_LAAL = 1264, - SystemZ_LAALG = 1265, - SystemZ_LAE = 1266, - SystemZ_LAEY = 1267, - SystemZ_LAM = 1268, - SystemZ_LAMY = 1269, - SystemZ_LAN = 1270, - SystemZ_LANG = 1271, - SystemZ_LAO = 1272, - SystemZ_LAOG = 1273, - SystemZ_LARL = 1274, - SystemZ_LASP = 1275, - SystemZ_LAT = 1276, - SystemZ_LAX = 1277, - SystemZ_LAXG = 1278, - SystemZ_LAY = 1279, - SystemZ_LB = 1280, - SystemZ_LBH = 1281, - SystemZ_LBR = 1282, - SystemZ_LCBB = 1283, - SystemZ_LCCTL = 1284, - SystemZ_LCDBR = 1285, - SystemZ_LCDFR = 1286, - SystemZ_LCDFR_32 = 1287, - SystemZ_LCDR = 1288, - SystemZ_LCEBR = 1289, - SystemZ_LCER = 1290, - SystemZ_LCGFR = 1291, - SystemZ_LCGR = 1292, - SystemZ_LCR = 1293, - SystemZ_LCTL = 1294, - SystemZ_LCTLG = 1295, - SystemZ_LCXBR = 1296, - SystemZ_LCXR = 1297, - SystemZ_LD = 1298, - SystemZ_LDE = 1299, - SystemZ_LDE32 = 1300, - SystemZ_LDEB = 1301, - SystemZ_LDEBR = 1302, - SystemZ_LDER = 1303, - SystemZ_LDETR = 1304, - SystemZ_LDGR = 1305, - SystemZ_LDR = 1306, - SystemZ_LDR32 = 1307, - SystemZ_LDXBR = 1308, - SystemZ_LDXBRA = 1309, - SystemZ_LDXR = 1310, - SystemZ_LDXTR = 1311, - SystemZ_LDY = 1312, - SystemZ_LE = 1313, - SystemZ_LEDBR = 1314, - SystemZ_LEDBRA = 1315, - SystemZ_LEDR = 1316, - SystemZ_LEDTR = 1317, - SystemZ_LER = 1318, - SystemZ_LEXBR = 1319, - SystemZ_LEXBRA = 1320, - SystemZ_LEXR = 1321, - SystemZ_LEY = 1322, - SystemZ_LFAS = 1323, - SystemZ_LFH = 1324, - SystemZ_LFHAT = 1325, - SystemZ_LFPC = 1326, - SystemZ_LG = 1327, - SystemZ_LGAT = 1328, - SystemZ_LGB = 1329, - SystemZ_LGBR = 1330, - SystemZ_LGDR = 1331, - SystemZ_LGF = 1332, - SystemZ_LGFI = 1333, - SystemZ_LGFR = 1334, - SystemZ_LGFRL = 1335, - SystemZ_LGG = 1336, - SystemZ_LGH = 1337, - SystemZ_LGHI = 1338, - SystemZ_LGHR = 1339, - SystemZ_LGHRL = 1340, - SystemZ_LGR = 1341, - SystemZ_LGRL = 1342, - SystemZ_LGSC = 1343, - SystemZ_LH = 1344, - SystemZ_LHH = 1345, - SystemZ_LHI = 1346, - SystemZ_LHR = 1347, - SystemZ_LHRL = 1348, - SystemZ_LHY = 1349, - SystemZ_LLC = 1350, - SystemZ_LLCH = 1351, - SystemZ_LLCR = 1352, - SystemZ_LLGC = 1353, - SystemZ_LLGCR = 1354, - SystemZ_LLGF = 1355, - SystemZ_LLGFAT = 1356, - SystemZ_LLGFR = 1357, - SystemZ_LLGFRL = 1358, - SystemZ_LLGFSG = 1359, - SystemZ_LLGH = 1360, - SystemZ_LLGHR = 1361, - SystemZ_LLGHRL = 1362, - SystemZ_LLGT = 1363, - SystemZ_LLGTAT = 1364, - SystemZ_LLGTR = 1365, - SystemZ_LLH = 1366, - SystemZ_LLHH = 1367, - SystemZ_LLHR = 1368, - SystemZ_LLHRL = 1369, - SystemZ_LLIHF = 1370, - SystemZ_LLIHH = 1371, - SystemZ_LLIHL = 1372, - SystemZ_LLILF = 1373, - SystemZ_LLILH = 1374, - SystemZ_LLILL = 1375, - SystemZ_LLZRGF = 1376, - SystemZ_LM = 1377, - SystemZ_LMD = 1378, - SystemZ_LMG = 1379, - SystemZ_LMH = 1380, - SystemZ_LMY = 1381, - SystemZ_LNDBR = 1382, - SystemZ_LNDFR = 1383, - SystemZ_LNDFR_32 = 1384, - SystemZ_LNDR = 1385, - SystemZ_LNEBR = 1386, - SystemZ_LNER = 1387, - SystemZ_LNGFR = 1388, - SystemZ_LNGR = 1389, - SystemZ_LNR = 1390, - SystemZ_LNXBR = 1391, - SystemZ_LNXR = 1392, - SystemZ_LOC = 1393, - SystemZ_LOCAsm = 1394, - SystemZ_LOCAsmE = 1395, - SystemZ_LOCAsmH = 1396, - SystemZ_LOCAsmHE = 1397, - SystemZ_LOCAsmL = 1398, - SystemZ_LOCAsmLE = 1399, - SystemZ_LOCAsmLH = 1400, - SystemZ_LOCAsmM = 1401, - SystemZ_LOCAsmNE = 1402, - SystemZ_LOCAsmNH = 1403, - SystemZ_LOCAsmNHE = 1404, - SystemZ_LOCAsmNL = 1405, - SystemZ_LOCAsmNLE = 1406, - SystemZ_LOCAsmNLH = 1407, - SystemZ_LOCAsmNM = 1408, - SystemZ_LOCAsmNO = 1409, - SystemZ_LOCAsmNP = 1410, - SystemZ_LOCAsmNZ = 1411, - SystemZ_LOCAsmO = 1412, - SystemZ_LOCAsmP = 1413, - SystemZ_LOCAsmZ = 1414, - SystemZ_LOCFH = 1415, - SystemZ_LOCFHAsm = 1416, - SystemZ_LOCFHAsmE = 1417, - SystemZ_LOCFHAsmH = 1418, - SystemZ_LOCFHAsmHE = 1419, - SystemZ_LOCFHAsmL = 1420, - SystemZ_LOCFHAsmLE = 1421, - SystemZ_LOCFHAsmLH = 1422, - SystemZ_LOCFHAsmM = 1423, - SystemZ_LOCFHAsmNE = 1424, - SystemZ_LOCFHAsmNH = 1425, - SystemZ_LOCFHAsmNHE = 1426, - SystemZ_LOCFHAsmNL = 1427, - SystemZ_LOCFHAsmNLE = 1428, - SystemZ_LOCFHAsmNLH = 1429, - SystemZ_LOCFHAsmNM = 1430, - SystemZ_LOCFHAsmNO = 1431, - SystemZ_LOCFHAsmNP = 1432, - SystemZ_LOCFHAsmNZ = 1433, - SystemZ_LOCFHAsmO = 1434, - SystemZ_LOCFHAsmP = 1435, - SystemZ_LOCFHAsmZ = 1436, - SystemZ_LOCFHR = 1437, - SystemZ_LOCFHRAsm = 1438, - SystemZ_LOCFHRAsmE = 1439, - SystemZ_LOCFHRAsmH = 1440, - SystemZ_LOCFHRAsmHE = 1441, - SystemZ_LOCFHRAsmL = 1442, - SystemZ_LOCFHRAsmLE = 1443, - SystemZ_LOCFHRAsmLH = 1444, - SystemZ_LOCFHRAsmM = 1445, - SystemZ_LOCFHRAsmNE = 1446, - SystemZ_LOCFHRAsmNH = 1447, - SystemZ_LOCFHRAsmNHE = 1448, - SystemZ_LOCFHRAsmNL = 1449, - SystemZ_LOCFHRAsmNLE = 1450, - SystemZ_LOCFHRAsmNLH = 1451, - SystemZ_LOCFHRAsmNM = 1452, - SystemZ_LOCFHRAsmNO = 1453, - SystemZ_LOCFHRAsmNP = 1454, - SystemZ_LOCFHRAsmNZ = 1455, - SystemZ_LOCFHRAsmO = 1456, - SystemZ_LOCFHRAsmP = 1457, - SystemZ_LOCFHRAsmZ = 1458, - SystemZ_LOCG = 1459, - SystemZ_LOCGAsm = 1460, - SystemZ_LOCGAsmE = 1461, - SystemZ_LOCGAsmH = 1462, - SystemZ_LOCGAsmHE = 1463, - SystemZ_LOCGAsmL = 1464, - SystemZ_LOCGAsmLE = 1465, - SystemZ_LOCGAsmLH = 1466, - SystemZ_LOCGAsmM = 1467, - SystemZ_LOCGAsmNE = 1468, - SystemZ_LOCGAsmNH = 1469, - SystemZ_LOCGAsmNHE = 1470, - SystemZ_LOCGAsmNL = 1471, - SystemZ_LOCGAsmNLE = 1472, - SystemZ_LOCGAsmNLH = 1473, - SystemZ_LOCGAsmNM = 1474, - SystemZ_LOCGAsmNO = 1475, - SystemZ_LOCGAsmNP = 1476, - SystemZ_LOCGAsmNZ = 1477, - SystemZ_LOCGAsmO = 1478, - SystemZ_LOCGAsmP = 1479, - SystemZ_LOCGAsmZ = 1480, - SystemZ_LOCGHI = 1481, - SystemZ_LOCGHIAsm = 1482, - SystemZ_LOCGHIAsmE = 1483, - SystemZ_LOCGHIAsmH = 1484, - SystemZ_LOCGHIAsmHE = 1485, - SystemZ_LOCGHIAsmL = 1486, - SystemZ_LOCGHIAsmLE = 1487, - SystemZ_LOCGHIAsmLH = 1488, - SystemZ_LOCGHIAsmM = 1489, - SystemZ_LOCGHIAsmNE = 1490, - SystemZ_LOCGHIAsmNH = 1491, - SystemZ_LOCGHIAsmNHE = 1492, - SystemZ_LOCGHIAsmNL = 1493, - SystemZ_LOCGHIAsmNLE = 1494, - SystemZ_LOCGHIAsmNLH = 1495, - SystemZ_LOCGHIAsmNM = 1496, - SystemZ_LOCGHIAsmNO = 1497, - SystemZ_LOCGHIAsmNP = 1498, - SystemZ_LOCGHIAsmNZ = 1499, - SystemZ_LOCGHIAsmO = 1500, - SystemZ_LOCGHIAsmP = 1501, - SystemZ_LOCGHIAsmZ = 1502, - SystemZ_LOCGR = 1503, - SystemZ_LOCGRAsm = 1504, - SystemZ_LOCGRAsmE = 1505, - SystemZ_LOCGRAsmH = 1506, - SystemZ_LOCGRAsmHE = 1507, - SystemZ_LOCGRAsmL = 1508, - SystemZ_LOCGRAsmLE = 1509, - SystemZ_LOCGRAsmLH = 1510, - SystemZ_LOCGRAsmM = 1511, - SystemZ_LOCGRAsmNE = 1512, - SystemZ_LOCGRAsmNH = 1513, - SystemZ_LOCGRAsmNHE = 1514, - SystemZ_LOCGRAsmNL = 1515, - SystemZ_LOCGRAsmNLE = 1516, - SystemZ_LOCGRAsmNLH = 1517, - SystemZ_LOCGRAsmNM = 1518, - SystemZ_LOCGRAsmNO = 1519, - SystemZ_LOCGRAsmNP = 1520, - SystemZ_LOCGRAsmNZ = 1521, - SystemZ_LOCGRAsmO = 1522, - SystemZ_LOCGRAsmP = 1523, - SystemZ_LOCGRAsmZ = 1524, - SystemZ_LOCHHI = 1525, - SystemZ_LOCHHIAsm = 1526, - SystemZ_LOCHHIAsmE = 1527, - SystemZ_LOCHHIAsmH = 1528, - SystemZ_LOCHHIAsmHE = 1529, - SystemZ_LOCHHIAsmL = 1530, - SystemZ_LOCHHIAsmLE = 1531, - SystemZ_LOCHHIAsmLH = 1532, - SystemZ_LOCHHIAsmM = 1533, - SystemZ_LOCHHIAsmNE = 1534, - SystemZ_LOCHHIAsmNH = 1535, - SystemZ_LOCHHIAsmNHE = 1536, - SystemZ_LOCHHIAsmNL = 1537, - SystemZ_LOCHHIAsmNLE = 1538, - SystemZ_LOCHHIAsmNLH = 1539, - SystemZ_LOCHHIAsmNM = 1540, - SystemZ_LOCHHIAsmNO = 1541, - SystemZ_LOCHHIAsmNP = 1542, - SystemZ_LOCHHIAsmNZ = 1543, - SystemZ_LOCHHIAsmO = 1544, - SystemZ_LOCHHIAsmP = 1545, - SystemZ_LOCHHIAsmZ = 1546, - SystemZ_LOCHI = 1547, - SystemZ_LOCHIAsm = 1548, - SystemZ_LOCHIAsmE = 1549, - SystemZ_LOCHIAsmH = 1550, - SystemZ_LOCHIAsmHE = 1551, - SystemZ_LOCHIAsmL = 1552, - SystemZ_LOCHIAsmLE = 1553, - SystemZ_LOCHIAsmLH = 1554, - SystemZ_LOCHIAsmM = 1555, - SystemZ_LOCHIAsmNE = 1556, - SystemZ_LOCHIAsmNH = 1557, - SystemZ_LOCHIAsmNHE = 1558, - SystemZ_LOCHIAsmNL = 1559, - SystemZ_LOCHIAsmNLE = 1560, - SystemZ_LOCHIAsmNLH = 1561, - SystemZ_LOCHIAsmNM = 1562, - SystemZ_LOCHIAsmNO = 1563, - SystemZ_LOCHIAsmNP = 1564, - SystemZ_LOCHIAsmNZ = 1565, - SystemZ_LOCHIAsmO = 1566, - SystemZ_LOCHIAsmP = 1567, - SystemZ_LOCHIAsmZ = 1568, - SystemZ_LOCR = 1569, - SystemZ_LOCRAsm = 1570, - SystemZ_LOCRAsmE = 1571, - SystemZ_LOCRAsmH = 1572, - SystemZ_LOCRAsmHE = 1573, - SystemZ_LOCRAsmL = 1574, - SystemZ_LOCRAsmLE = 1575, - SystemZ_LOCRAsmLH = 1576, - SystemZ_LOCRAsmM = 1577, - SystemZ_LOCRAsmNE = 1578, - SystemZ_LOCRAsmNH = 1579, - SystemZ_LOCRAsmNHE = 1580, - SystemZ_LOCRAsmNL = 1581, - SystemZ_LOCRAsmNLE = 1582, - SystemZ_LOCRAsmNLH = 1583, - SystemZ_LOCRAsmNM = 1584, - SystemZ_LOCRAsmNO = 1585, - SystemZ_LOCRAsmNP = 1586, - SystemZ_LOCRAsmNZ = 1587, - SystemZ_LOCRAsmO = 1588, - SystemZ_LOCRAsmP = 1589, - SystemZ_LOCRAsmZ = 1590, - SystemZ_LPCTL = 1591, - SystemZ_LPD = 1592, - SystemZ_LPDBR = 1593, - SystemZ_LPDFR = 1594, - SystemZ_LPDFR_32 = 1595, - SystemZ_LPDG = 1596, - SystemZ_LPDR = 1597, - SystemZ_LPEBR = 1598, - SystemZ_LPER = 1599, - SystemZ_LPGFR = 1600, - SystemZ_LPGR = 1601, - SystemZ_LPP = 1602, - SystemZ_LPQ = 1603, - SystemZ_LPR = 1604, - SystemZ_LPSW = 1605, - SystemZ_LPSWE = 1606, - SystemZ_LPTEA = 1607, - SystemZ_LPXBR = 1608, - SystemZ_LPXR = 1609, - SystemZ_LR = 1610, - SystemZ_LRA = 1611, - SystemZ_LRAG = 1612, - SystemZ_LRAY = 1613, - SystemZ_LRDR = 1614, - SystemZ_LRER = 1615, - SystemZ_LRL = 1616, - SystemZ_LRV = 1617, - SystemZ_LRVG = 1618, - SystemZ_LRVGR = 1619, - SystemZ_LRVH = 1620, - SystemZ_LRVR = 1621, - SystemZ_LSCTL = 1622, - SystemZ_LT = 1623, - SystemZ_LTDBR = 1624, - SystemZ_LTDBRCompare = 1625, - SystemZ_LTDR = 1626, - SystemZ_LTDTR = 1627, - SystemZ_LTEBR = 1628, - SystemZ_LTEBRCompare = 1629, - SystemZ_LTER = 1630, - SystemZ_LTG = 1631, - SystemZ_LTGF = 1632, - SystemZ_LTGFR = 1633, - SystemZ_LTGR = 1634, - SystemZ_LTR = 1635, - SystemZ_LTXBR = 1636, - SystemZ_LTXBRCompare = 1637, - SystemZ_LTXR = 1638, - SystemZ_LTXTR = 1639, - SystemZ_LURA = 1640, - SystemZ_LURAG = 1641, - SystemZ_LXD = 1642, - SystemZ_LXDB = 1643, - SystemZ_LXDBR = 1644, - SystemZ_LXDR = 1645, - SystemZ_LXDTR = 1646, - SystemZ_LXE = 1647, - SystemZ_LXEB = 1648, - SystemZ_LXEBR = 1649, - SystemZ_LXER = 1650, - SystemZ_LXR = 1651, - SystemZ_LY = 1652, - SystemZ_LZDR = 1653, - SystemZ_LZER = 1654, - SystemZ_LZRF = 1655, - SystemZ_LZRG = 1656, - SystemZ_LZXR = 1657, - SystemZ_M = 1658, - SystemZ_MAD = 1659, - SystemZ_MADB = 1660, - SystemZ_MADBR = 1661, - SystemZ_MADR = 1662, - SystemZ_MAE = 1663, - SystemZ_MAEB = 1664, - SystemZ_MAEBR = 1665, - SystemZ_MAER = 1666, - SystemZ_MAY = 1667, - SystemZ_MAYH = 1668, - SystemZ_MAYHR = 1669, - SystemZ_MAYL = 1670, - SystemZ_MAYLR = 1671, - SystemZ_MAYR = 1672, - SystemZ_MC = 1673, - SystemZ_MD = 1674, - SystemZ_MDB = 1675, - SystemZ_MDBR = 1676, - SystemZ_MDE = 1677, - SystemZ_MDEB = 1678, - SystemZ_MDEBR = 1679, - SystemZ_MDER = 1680, - SystemZ_MDR = 1681, - SystemZ_MDTR = 1682, - SystemZ_MDTRA = 1683, - SystemZ_ME = 1684, - SystemZ_MEE = 1685, - SystemZ_MEEB = 1686, - SystemZ_MEEBR = 1687, - SystemZ_MEER = 1688, - SystemZ_MER = 1689, - SystemZ_MFY = 1690, - SystemZ_MG = 1691, - SystemZ_MGH = 1692, - SystemZ_MGHI = 1693, - SystemZ_MGRK = 1694, - SystemZ_MH = 1695, - SystemZ_MHI = 1696, - SystemZ_MHY = 1697, - SystemZ_ML = 1698, - SystemZ_MLG = 1699, - SystemZ_MLGR = 1700, - SystemZ_MLR = 1701, - SystemZ_MP = 1702, - SystemZ_MR = 1703, - SystemZ_MS = 1704, - SystemZ_MSC = 1705, - SystemZ_MSCH = 1706, - SystemZ_MSD = 1707, - SystemZ_MSDB = 1708, - SystemZ_MSDBR = 1709, - SystemZ_MSDR = 1710, - SystemZ_MSE = 1711, - SystemZ_MSEB = 1712, - SystemZ_MSEBR = 1713, - SystemZ_MSER = 1714, - SystemZ_MSFI = 1715, - SystemZ_MSG = 1716, - SystemZ_MSGC = 1717, - SystemZ_MSGF = 1718, - SystemZ_MSGFI = 1719, - SystemZ_MSGFR = 1720, - SystemZ_MSGR = 1721, - SystemZ_MSGRKC = 1722, - SystemZ_MSR = 1723, - SystemZ_MSRKC = 1724, - SystemZ_MSTA = 1725, - SystemZ_MSY = 1726, - SystemZ_MVC = 1727, - SystemZ_MVCDK = 1728, - SystemZ_MVCIN = 1729, - SystemZ_MVCK = 1730, - SystemZ_MVCL = 1731, - SystemZ_MVCLE = 1732, - SystemZ_MVCLU = 1733, - SystemZ_MVCOS = 1734, - SystemZ_MVCP = 1735, - SystemZ_MVCS = 1736, - SystemZ_MVCSK = 1737, - SystemZ_MVGHI = 1738, - SystemZ_MVHHI = 1739, - SystemZ_MVHI = 1740, - SystemZ_MVI = 1741, - SystemZ_MVIY = 1742, - SystemZ_MVN = 1743, - SystemZ_MVO = 1744, - SystemZ_MVPG = 1745, - SystemZ_MVST = 1746, - SystemZ_MVZ = 1747, - SystemZ_MXBR = 1748, - SystemZ_MXD = 1749, - SystemZ_MXDB = 1750, - SystemZ_MXDBR = 1751, - SystemZ_MXDR = 1752, - SystemZ_MXR = 1753, - SystemZ_MXTR = 1754, - SystemZ_MXTRA = 1755, - SystemZ_MY = 1756, - SystemZ_MYH = 1757, - SystemZ_MYHR = 1758, - SystemZ_MYL = 1759, - SystemZ_MYLR = 1760, - SystemZ_MYR = 1761, - SystemZ_N = 1762, - SystemZ_NC = 1763, - SystemZ_NG = 1764, - SystemZ_NGR = 1765, - SystemZ_NGRK = 1766, - SystemZ_NI = 1767, - SystemZ_NIAI = 1768, - SystemZ_NIHF = 1769, - SystemZ_NIHH = 1770, - SystemZ_NIHL = 1771, - SystemZ_NILF = 1772, - SystemZ_NILH = 1773, - SystemZ_NILL = 1774, - SystemZ_NIY = 1775, - SystemZ_NR = 1776, - SystemZ_NRK = 1777, - SystemZ_NTSTG = 1778, - SystemZ_NY = 1779, - SystemZ_O = 1780, - SystemZ_OC = 1781, - SystemZ_OG = 1782, - SystemZ_OGR = 1783, - SystemZ_OGRK = 1784, - SystemZ_OI = 1785, - SystemZ_OIHF = 1786, - SystemZ_OIHH = 1787, - SystemZ_OIHL = 1788, - SystemZ_OILF = 1789, - SystemZ_OILH = 1790, - SystemZ_OILL = 1791, - SystemZ_OIY = 1792, - SystemZ_OR = 1793, - SystemZ_ORK = 1794, - SystemZ_OY = 1795, - SystemZ_PACK = 1796, - SystemZ_PALB = 1797, - SystemZ_PC = 1798, - SystemZ_PCC = 1799, - SystemZ_PCKMO = 1800, - SystemZ_PFD = 1801, - SystemZ_PFDRL = 1802, - SystemZ_PFMF = 1803, - SystemZ_PFPO = 1804, - SystemZ_PGIN = 1805, - SystemZ_PGOUT = 1806, - SystemZ_PKA = 1807, - SystemZ_PKU = 1808, - SystemZ_PLO = 1809, - SystemZ_POPCNT = 1810, - SystemZ_PPA = 1811, - SystemZ_PPNO = 1812, - SystemZ_PR = 1813, - SystemZ_PRNO = 1814, - SystemZ_PT = 1815, - SystemZ_PTF = 1816, - SystemZ_PTFF = 1817, - SystemZ_PTI = 1818, - SystemZ_PTLB = 1819, - SystemZ_QADTR = 1820, - SystemZ_QAXTR = 1821, - SystemZ_QCTRI = 1822, - SystemZ_QSI = 1823, - SystemZ_RCHP = 1824, - SystemZ_RISBG = 1825, - SystemZ_RISBG32 = 1826, - SystemZ_RISBGN = 1827, - SystemZ_RISBHG = 1828, - SystemZ_RISBLG = 1829, - SystemZ_RLL = 1830, - SystemZ_RLLG = 1831, - SystemZ_RNSBG = 1832, - SystemZ_ROSBG = 1833, - SystemZ_RP = 1834, - SystemZ_RRBE = 1835, - SystemZ_RRBM = 1836, - SystemZ_RRDTR = 1837, - SystemZ_RRXTR = 1838, - SystemZ_RSCH = 1839, - SystemZ_RXSBG = 1840, - SystemZ_S = 1841, - SystemZ_SAC = 1842, - SystemZ_SACF = 1843, - SystemZ_SAL = 1844, - SystemZ_SAM24 = 1845, - SystemZ_SAM31 = 1846, - SystemZ_SAM64 = 1847, - SystemZ_SAR = 1848, - SystemZ_SCCTR = 1849, - SystemZ_SCHM = 1850, - SystemZ_SCK = 1851, - SystemZ_SCKC = 1852, - SystemZ_SCKPF = 1853, - SystemZ_SD = 1854, - SystemZ_SDB = 1855, - SystemZ_SDBR = 1856, - SystemZ_SDR = 1857, - SystemZ_SDTR = 1858, - SystemZ_SDTRA = 1859, - SystemZ_SE = 1860, - SystemZ_SEB = 1861, - SystemZ_SEBR = 1862, - SystemZ_SER = 1863, - SystemZ_SFASR = 1864, - SystemZ_SFPC = 1865, - SystemZ_SG = 1866, - SystemZ_SGF = 1867, - SystemZ_SGFR = 1868, - SystemZ_SGH = 1869, - SystemZ_SGR = 1870, - SystemZ_SGRK = 1871, - SystemZ_SH = 1872, - SystemZ_SHHHR = 1873, - SystemZ_SHHLR = 1874, - SystemZ_SHY = 1875, - SystemZ_SIE = 1876, - SystemZ_SIGA = 1877, - SystemZ_SIGP = 1878, - SystemZ_SL = 1879, - SystemZ_SLA = 1880, - SystemZ_SLAG = 1881, - SystemZ_SLAK = 1882, - SystemZ_SLB = 1883, - SystemZ_SLBG = 1884, - SystemZ_SLBGR = 1885, - SystemZ_SLBR = 1886, - SystemZ_SLDA = 1887, - SystemZ_SLDL = 1888, - SystemZ_SLDT = 1889, - SystemZ_SLFI = 1890, - SystemZ_SLG = 1891, - SystemZ_SLGF = 1892, - SystemZ_SLGFI = 1893, - SystemZ_SLGFR = 1894, - SystemZ_SLGR = 1895, - SystemZ_SLGRK = 1896, - SystemZ_SLHHHR = 1897, - SystemZ_SLHHLR = 1898, - SystemZ_SLL = 1899, - SystemZ_SLLG = 1900, - SystemZ_SLLK = 1901, - SystemZ_SLR = 1902, - SystemZ_SLRK = 1903, - SystemZ_SLXT = 1904, - SystemZ_SLY = 1905, - SystemZ_SP = 1906, - SystemZ_SPCTR = 1907, - SystemZ_SPKA = 1908, - SystemZ_SPM = 1909, - SystemZ_SPT = 1910, - SystemZ_SPX = 1911, - SystemZ_SQD = 1912, - SystemZ_SQDB = 1913, - SystemZ_SQDBR = 1914, - SystemZ_SQDR = 1915, - SystemZ_SQE = 1916, - SystemZ_SQEB = 1917, - SystemZ_SQEBR = 1918, - SystemZ_SQER = 1919, - SystemZ_SQXBR = 1920, - SystemZ_SQXR = 1921, - SystemZ_SR = 1922, - SystemZ_SRA = 1923, - SystemZ_SRAG = 1924, - SystemZ_SRAK = 1925, - SystemZ_SRDA = 1926, - SystemZ_SRDL = 1927, - SystemZ_SRDT = 1928, - SystemZ_SRK = 1929, - SystemZ_SRL = 1930, - SystemZ_SRLG = 1931, - SystemZ_SRLK = 1932, - SystemZ_SRNM = 1933, - SystemZ_SRNMB = 1934, - SystemZ_SRNMT = 1935, - SystemZ_SRP = 1936, - SystemZ_SRST = 1937, - SystemZ_SRSTU = 1938, - SystemZ_SRXT = 1939, - SystemZ_SSAIR = 1940, - SystemZ_SSAR = 1941, - SystemZ_SSCH = 1942, - SystemZ_SSKE = 1943, - SystemZ_SSKEOpt = 1944, - SystemZ_SSM = 1945, - SystemZ_ST = 1946, - SystemZ_STAM = 1947, - SystemZ_STAMY = 1948, - SystemZ_STAP = 1949, - SystemZ_STC = 1950, - SystemZ_STCH = 1951, - SystemZ_STCK = 1952, - SystemZ_STCKC = 1953, - SystemZ_STCKE = 1954, - SystemZ_STCKF = 1955, - SystemZ_STCM = 1956, - SystemZ_STCMH = 1957, - SystemZ_STCMY = 1958, - SystemZ_STCPS = 1959, - SystemZ_STCRW = 1960, - SystemZ_STCTG = 1961, - SystemZ_STCTL = 1962, - SystemZ_STCY = 1963, - SystemZ_STD = 1964, - SystemZ_STDY = 1965, - SystemZ_STE = 1966, - SystemZ_STEY = 1967, - SystemZ_STFH = 1968, - SystemZ_STFL = 1969, - SystemZ_STFLE = 1970, - SystemZ_STFPC = 1971, - SystemZ_STG = 1972, - SystemZ_STGRL = 1973, - SystemZ_STGSC = 1974, - SystemZ_STH = 1975, - SystemZ_STHH = 1976, - SystemZ_STHRL = 1977, - SystemZ_STHY = 1978, - SystemZ_STIDP = 1979, - SystemZ_STM = 1980, - SystemZ_STMG = 1981, - SystemZ_STMH = 1982, - SystemZ_STMY = 1983, - SystemZ_STNSM = 1984, - SystemZ_STOC = 1985, - SystemZ_STOCAsm = 1986, - SystemZ_STOCAsmE = 1987, - SystemZ_STOCAsmH = 1988, - SystemZ_STOCAsmHE = 1989, - SystemZ_STOCAsmL = 1990, - SystemZ_STOCAsmLE = 1991, - SystemZ_STOCAsmLH = 1992, - SystemZ_STOCAsmM = 1993, - SystemZ_STOCAsmNE = 1994, - SystemZ_STOCAsmNH = 1995, - SystemZ_STOCAsmNHE = 1996, - SystemZ_STOCAsmNL = 1997, - SystemZ_STOCAsmNLE = 1998, - SystemZ_STOCAsmNLH = 1999, - SystemZ_STOCAsmNM = 2000, - SystemZ_STOCAsmNO = 2001, - SystemZ_STOCAsmNP = 2002, - SystemZ_STOCAsmNZ = 2003, - SystemZ_STOCAsmO = 2004, - SystemZ_STOCAsmP = 2005, - SystemZ_STOCAsmZ = 2006, - SystemZ_STOCFH = 2007, - SystemZ_STOCFHAsm = 2008, - SystemZ_STOCFHAsmE = 2009, - SystemZ_STOCFHAsmH = 2010, - SystemZ_STOCFHAsmHE = 2011, - SystemZ_STOCFHAsmL = 2012, - SystemZ_STOCFHAsmLE = 2013, - SystemZ_STOCFHAsmLH = 2014, - SystemZ_STOCFHAsmM = 2015, - SystemZ_STOCFHAsmNE = 2016, - SystemZ_STOCFHAsmNH = 2017, - SystemZ_STOCFHAsmNHE = 2018, - SystemZ_STOCFHAsmNL = 2019, - SystemZ_STOCFHAsmNLE = 2020, - SystemZ_STOCFHAsmNLH = 2021, - SystemZ_STOCFHAsmNM = 2022, - SystemZ_STOCFHAsmNO = 2023, - SystemZ_STOCFHAsmNP = 2024, - SystemZ_STOCFHAsmNZ = 2025, - SystemZ_STOCFHAsmO = 2026, - SystemZ_STOCFHAsmP = 2027, - SystemZ_STOCFHAsmZ = 2028, - SystemZ_STOCG = 2029, - SystemZ_STOCGAsm = 2030, - SystemZ_STOCGAsmE = 2031, - SystemZ_STOCGAsmH = 2032, - SystemZ_STOCGAsmHE = 2033, - SystemZ_STOCGAsmL = 2034, - SystemZ_STOCGAsmLE = 2035, - SystemZ_STOCGAsmLH = 2036, - SystemZ_STOCGAsmM = 2037, - SystemZ_STOCGAsmNE = 2038, - SystemZ_STOCGAsmNH = 2039, - SystemZ_STOCGAsmNHE = 2040, - SystemZ_STOCGAsmNL = 2041, - SystemZ_STOCGAsmNLE = 2042, - SystemZ_STOCGAsmNLH = 2043, - SystemZ_STOCGAsmNM = 2044, - SystemZ_STOCGAsmNO = 2045, - SystemZ_STOCGAsmNP = 2046, - SystemZ_STOCGAsmNZ = 2047, - SystemZ_STOCGAsmO = 2048, - SystemZ_STOCGAsmP = 2049, - SystemZ_STOCGAsmZ = 2050, - SystemZ_STOSM = 2051, - SystemZ_STPQ = 2052, - SystemZ_STPT = 2053, - SystemZ_STPX = 2054, - SystemZ_STRAG = 2055, - SystemZ_STRL = 2056, - SystemZ_STRV = 2057, - SystemZ_STRVG = 2058, - SystemZ_STRVH = 2059, - SystemZ_STSCH = 2060, - SystemZ_STSI = 2061, - SystemZ_STURA = 2062, - SystemZ_STURG = 2063, - SystemZ_STY = 2064, - SystemZ_SU = 2065, - SystemZ_SUR = 2066, - SystemZ_SVC = 2067, - SystemZ_SW = 2068, - SystemZ_SWR = 2069, - SystemZ_SXBR = 2070, - SystemZ_SXR = 2071, - SystemZ_SXTR = 2072, - SystemZ_SXTRA = 2073, - SystemZ_SY = 2074, - SystemZ_TABORT = 2075, - SystemZ_TAM = 2076, - SystemZ_TAR = 2077, - SystemZ_TB = 2078, - SystemZ_TBDR = 2079, - SystemZ_TBEDR = 2080, - SystemZ_TBEGIN = 2081, - SystemZ_TBEGINC = 2082, - SystemZ_TCDB = 2083, - SystemZ_TCEB = 2084, - SystemZ_TCXB = 2085, - SystemZ_TDCDT = 2086, - SystemZ_TDCET = 2087, - SystemZ_TDCXT = 2088, - SystemZ_TDGDT = 2089, - SystemZ_TDGET = 2090, - SystemZ_TDGXT = 2091, - SystemZ_TEND = 2092, - SystemZ_THDER = 2093, - SystemZ_THDR = 2094, - SystemZ_TM = 2095, - SystemZ_TMHH = 2096, - SystemZ_TMHL = 2097, - SystemZ_TMLH = 2098, - SystemZ_TMLL = 2099, - SystemZ_TMY = 2100, - SystemZ_TP = 2101, - SystemZ_TPI = 2102, - SystemZ_TPROT = 2103, - SystemZ_TR = 2104, - SystemZ_TRACE = 2105, - SystemZ_TRACG = 2106, - SystemZ_TRAP2 = 2107, - SystemZ_TRAP4 = 2108, - SystemZ_TRE = 2109, - SystemZ_TROO = 2110, - SystemZ_TROOOpt = 2111, - SystemZ_TROT = 2112, - SystemZ_TROTOpt = 2113, - SystemZ_TRT = 2114, - SystemZ_TRTE = 2115, - SystemZ_TRTEOpt = 2116, - SystemZ_TRTO = 2117, - SystemZ_TRTOOpt = 2118, - SystemZ_TRTR = 2119, - SystemZ_TRTRE = 2120, - SystemZ_TRTREOpt = 2121, - SystemZ_TRTT = 2122, - SystemZ_TRTTOpt = 2123, - SystemZ_TS = 2124, - SystemZ_TSCH = 2125, - SystemZ_UNPK = 2126, - SystemZ_UNPKA = 2127, - SystemZ_UNPKU = 2128, - SystemZ_UPT = 2129, - SystemZ_VA = 2130, - SystemZ_VAB = 2131, - SystemZ_VAC = 2132, - SystemZ_VACC = 2133, - SystemZ_VACCB = 2134, - SystemZ_VACCC = 2135, - SystemZ_VACCCQ = 2136, - SystemZ_VACCF = 2137, - SystemZ_VACCG = 2138, - SystemZ_VACCH = 2139, - SystemZ_VACCQ = 2140, - SystemZ_VACQ = 2141, - SystemZ_VAF = 2142, - SystemZ_VAG = 2143, - SystemZ_VAH = 2144, - SystemZ_VAP = 2145, - SystemZ_VAQ = 2146, - SystemZ_VAVG = 2147, - SystemZ_VAVGB = 2148, - SystemZ_VAVGF = 2149, - SystemZ_VAVGG = 2150, - SystemZ_VAVGH = 2151, - SystemZ_VAVGL = 2152, - SystemZ_VAVGLB = 2153, - SystemZ_VAVGLF = 2154, - SystemZ_VAVGLG = 2155, - SystemZ_VAVGLH = 2156, - SystemZ_VBPERM = 2157, - SystemZ_VCDG = 2158, - SystemZ_VCDGB = 2159, - SystemZ_VCDLG = 2160, - SystemZ_VCDLGB = 2161, - SystemZ_VCEQ = 2162, - SystemZ_VCEQB = 2163, - SystemZ_VCEQBS = 2164, - SystemZ_VCEQF = 2165, - SystemZ_VCEQFS = 2166, - SystemZ_VCEQG = 2167, - SystemZ_VCEQGS = 2168, - SystemZ_VCEQH = 2169, - SystemZ_VCEQHS = 2170, - SystemZ_VCGD = 2171, - SystemZ_VCGDB = 2172, - SystemZ_VCH = 2173, - SystemZ_VCHB = 2174, - SystemZ_VCHBS = 2175, - SystemZ_VCHF = 2176, - SystemZ_VCHFS = 2177, - SystemZ_VCHG = 2178, - SystemZ_VCHGS = 2179, - SystemZ_VCHH = 2180, - SystemZ_VCHHS = 2181, - SystemZ_VCHL = 2182, - SystemZ_VCHLB = 2183, - SystemZ_VCHLBS = 2184, - SystemZ_VCHLF = 2185, - SystemZ_VCHLFS = 2186, - SystemZ_VCHLG = 2187, - SystemZ_VCHLGS = 2188, - SystemZ_VCHLH = 2189, - SystemZ_VCHLHS = 2190, - SystemZ_VCKSM = 2191, - SystemZ_VCLGD = 2192, - SystemZ_VCLGDB = 2193, - SystemZ_VCLZ = 2194, - SystemZ_VCLZB = 2195, - SystemZ_VCLZF = 2196, - SystemZ_VCLZG = 2197, - SystemZ_VCLZH = 2198, - SystemZ_VCP = 2199, - SystemZ_VCTZ = 2200, - SystemZ_VCTZB = 2201, - SystemZ_VCTZF = 2202, - SystemZ_VCTZG = 2203, - SystemZ_VCTZH = 2204, - SystemZ_VCVB = 2205, - SystemZ_VCVBG = 2206, - SystemZ_VCVD = 2207, - SystemZ_VCVDG = 2208, - SystemZ_VDP = 2209, - SystemZ_VEC = 2210, - SystemZ_VECB = 2211, - SystemZ_VECF = 2212, - SystemZ_VECG = 2213, - SystemZ_VECH = 2214, - SystemZ_VECL = 2215, - SystemZ_VECLB = 2216, - SystemZ_VECLF = 2217, - SystemZ_VECLG = 2218, - SystemZ_VECLH = 2219, - SystemZ_VERIM = 2220, - SystemZ_VERIMB = 2221, - SystemZ_VERIMF = 2222, - SystemZ_VERIMG = 2223, - SystemZ_VERIMH = 2224, - SystemZ_VERLL = 2225, - SystemZ_VERLLB = 2226, - SystemZ_VERLLF = 2227, - SystemZ_VERLLG = 2228, - SystemZ_VERLLH = 2229, - SystemZ_VERLLV = 2230, - SystemZ_VERLLVB = 2231, - SystemZ_VERLLVF = 2232, - SystemZ_VERLLVG = 2233, - SystemZ_VERLLVH = 2234, - SystemZ_VESL = 2235, - SystemZ_VESLB = 2236, - SystemZ_VESLF = 2237, - SystemZ_VESLG = 2238, - SystemZ_VESLH = 2239, - SystemZ_VESLV = 2240, - SystemZ_VESLVB = 2241, - SystemZ_VESLVF = 2242, - SystemZ_VESLVG = 2243, - SystemZ_VESLVH = 2244, - SystemZ_VESRA = 2245, - SystemZ_VESRAB = 2246, - SystemZ_VESRAF = 2247, - SystemZ_VESRAG = 2248, - SystemZ_VESRAH = 2249, - SystemZ_VESRAV = 2250, - SystemZ_VESRAVB = 2251, - SystemZ_VESRAVF = 2252, - SystemZ_VESRAVG = 2253, - SystemZ_VESRAVH = 2254, - SystemZ_VESRL = 2255, - SystemZ_VESRLB = 2256, - SystemZ_VESRLF = 2257, - SystemZ_VESRLG = 2258, - SystemZ_VESRLH = 2259, - SystemZ_VESRLV = 2260, - SystemZ_VESRLVB = 2261, - SystemZ_VESRLVF = 2262, - SystemZ_VESRLVG = 2263, - SystemZ_VESRLVH = 2264, - SystemZ_VFA = 2265, - SystemZ_VFADB = 2266, - SystemZ_VFAE = 2267, - SystemZ_VFAEB = 2268, - SystemZ_VFAEBS = 2269, - SystemZ_VFAEF = 2270, - SystemZ_VFAEFS = 2271, - SystemZ_VFAEH = 2272, - SystemZ_VFAEHS = 2273, - SystemZ_VFAEZB = 2274, - SystemZ_VFAEZBS = 2275, - SystemZ_VFAEZF = 2276, - SystemZ_VFAEZFS = 2277, - SystemZ_VFAEZH = 2278, - SystemZ_VFAEZHS = 2279, - SystemZ_VFASB = 2280, - SystemZ_VFCE = 2281, - SystemZ_VFCEDB = 2282, - SystemZ_VFCEDBS = 2283, - SystemZ_VFCESB = 2284, - SystemZ_VFCESBS = 2285, - SystemZ_VFCH = 2286, - SystemZ_VFCHDB = 2287, - SystemZ_VFCHDBS = 2288, - SystemZ_VFCHE = 2289, - SystemZ_VFCHEDB = 2290, - SystemZ_VFCHEDBS = 2291, - SystemZ_VFCHESB = 2292, - SystemZ_VFCHESBS = 2293, - SystemZ_VFCHSB = 2294, - SystemZ_VFCHSBS = 2295, - SystemZ_VFD = 2296, - SystemZ_VFDDB = 2297, - SystemZ_VFDSB = 2298, - SystemZ_VFEE = 2299, - SystemZ_VFEEB = 2300, - SystemZ_VFEEBS = 2301, - SystemZ_VFEEF = 2302, - SystemZ_VFEEFS = 2303, - SystemZ_VFEEH = 2304, - SystemZ_VFEEHS = 2305, - SystemZ_VFEEZB = 2306, - SystemZ_VFEEZBS = 2307, - SystemZ_VFEEZF = 2308, - SystemZ_VFEEZFS = 2309, - SystemZ_VFEEZH = 2310, - SystemZ_VFEEZHS = 2311, - SystemZ_VFENE = 2312, - SystemZ_VFENEB = 2313, - SystemZ_VFENEBS = 2314, - SystemZ_VFENEF = 2315, - SystemZ_VFENEFS = 2316, - SystemZ_VFENEH = 2317, - SystemZ_VFENEHS = 2318, - SystemZ_VFENEZB = 2319, - SystemZ_VFENEZBS = 2320, - SystemZ_VFENEZF = 2321, - SystemZ_VFENEZFS = 2322, - SystemZ_VFENEZH = 2323, - SystemZ_VFENEZHS = 2324, - SystemZ_VFI = 2325, - SystemZ_VFIDB = 2326, - SystemZ_VFISB = 2327, - SystemZ_VFKEDB = 2328, - SystemZ_VFKEDBS = 2329, - SystemZ_VFKESB = 2330, - SystemZ_VFKESBS = 2331, - SystemZ_VFKHDB = 2332, - SystemZ_VFKHDBS = 2333, - SystemZ_VFKHEDB = 2334, - SystemZ_VFKHEDBS = 2335, - SystemZ_VFKHESB = 2336, - SystemZ_VFKHESBS = 2337, - SystemZ_VFKHSB = 2338, - SystemZ_VFKHSBS = 2339, - SystemZ_VFLCDB = 2340, - SystemZ_VFLCSB = 2341, - SystemZ_VFLL = 2342, - SystemZ_VFLLS = 2343, - SystemZ_VFLNDB = 2344, - SystemZ_VFLNSB = 2345, - SystemZ_VFLPDB = 2346, - SystemZ_VFLPSB = 2347, - SystemZ_VFLR = 2348, - SystemZ_VFLRD = 2349, - SystemZ_VFM = 2350, - SystemZ_VFMA = 2351, - SystemZ_VFMADB = 2352, - SystemZ_VFMASB = 2353, - SystemZ_VFMAX = 2354, - SystemZ_VFMAXDB = 2355, - SystemZ_VFMAXSB = 2356, - SystemZ_VFMDB = 2357, - SystemZ_VFMIN = 2358, - SystemZ_VFMINDB = 2359, - SystemZ_VFMINSB = 2360, - SystemZ_VFMS = 2361, - SystemZ_VFMSB = 2362, - SystemZ_VFMSDB = 2363, - SystemZ_VFMSSB = 2364, - SystemZ_VFNMA = 2365, - SystemZ_VFNMADB = 2366, - SystemZ_VFNMASB = 2367, - SystemZ_VFNMS = 2368, - SystemZ_VFNMSDB = 2369, - SystemZ_VFNMSSB = 2370, - SystemZ_VFPSO = 2371, - SystemZ_VFPSODB = 2372, - SystemZ_VFPSOSB = 2373, - SystemZ_VFS = 2374, - SystemZ_VFSDB = 2375, - SystemZ_VFSQ = 2376, - SystemZ_VFSQDB = 2377, - SystemZ_VFSQSB = 2378, - SystemZ_VFSSB = 2379, - SystemZ_VFTCI = 2380, - SystemZ_VFTCIDB = 2381, - SystemZ_VFTCISB = 2382, - SystemZ_VGBM = 2383, - SystemZ_VGEF = 2384, - SystemZ_VGEG = 2385, - SystemZ_VGFM = 2386, - SystemZ_VGFMA = 2387, - SystemZ_VGFMAB = 2388, - SystemZ_VGFMAF = 2389, - SystemZ_VGFMAG = 2390, - SystemZ_VGFMAH = 2391, - SystemZ_VGFMB = 2392, - SystemZ_VGFMF = 2393, - SystemZ_VGFMG = 2394, - SystemZ_VGFMH = 2395, - SystemZ_VGM = 2396, - SystemZ_VGMB = 2397, - SystemZ_VGMF = 2398, - SystemZ_VGMG = 2399, - SystemZ_VGMH = 2400, - SystemZ_VISTR = 2401, - SystemZ_VISTRB = 2402, - SystemZ_VISTRBS = 2403, - SystemZ_VISTRF = 2404, - SystemZ_VISTRFS = 2405, - SystemZ_VISTRH = 2406, - SystemZ_VISTRHS = 2407, - SystemZ_VL = 2408, - SystemZ_VLBB = 2409, - SystemZ_VLC = 2410, - SystemZ_VLCB = 2411, - SystemZ_VLCF = 2412, - SystemZ_VLCG = 2413, - SystemZ_VLCH = 2414, - SystemZ_VLDE = 2415, - SystemZ_VLDEB = 2416, - SystemZ_VLEB = 2417, - SystemZ_VLED = 2418, - SystemZ_VLEDB = 2419, - SystemZ_VLEF = 2420, - SystemZ_VLEG = 2421, - SystemZ_VLEH = 2422, - SystemZ_VLEIB = 2423, - SystemZ_VLEIF = 2424, - SystemZ_VLEIG = 2425, - SystemZ_VLEIH = 2426, - SystemZ_VLGV = 2427, - SystemZ_VLGVB = 2428, - SystemZ_VLGVF = 2429, - SystemZ_VLGVG = 2430, - SystemZ_VLGVH = 2431, - SystemZ_VLIP = 2432, - SystemZ_VLL = 2433, - SystemZ_VLLEZ = 2434, - SystemZ_VLLEZB = 2435, - SystemZ_VLLEZF = 2436, - SystemZ_VLLEZG = 2437, - SystemZ_VLLEZH = 2438, - SystemZ_VLLEZLF = 2439, - SystemZ_VLM = 2440, - SystemZ_VLP = 2441, - SystemZ_VLPB = 2442, - SystemZ_VLPF = 2443, - SystemZ_VLPG = 2444, - SystemZ_VLPH = 2445, - SystemZ_VLR = 2446, - SystemZ_VLREP = 2447, - SystemZ_VLREPB = 2448, - SystemZ_VLREPF = 2449, - SystemZ_VLREPG = 2450, - SystemZ_VLREPH = 2451, - SystemZ_VLRL = 2452, - SystemZ_VLRLR = 2453, - SystemZ_VLVG = 2454, - SystemZ_VLVGB = 2455, - SystemZ_VLVGF = 2456, - SystemZ_VLVGG = 2457, - SystemZ_VLVGH = 2458, - SystemZ_VLVGP = 2459, - SystemZ_VMAE = 2460, - SystemZ_VMAEB = 2461, - SystemZ_VMAEF = 2462, - SystemZ_VMAEH = 2463, - SystemZ_VMAH = 2464, - SystemZ_VMAHB = 2465, - SystemZ_VMAHF = 2466, - SystemZ_VMAHH = 2467, - SystemZ_VMAL = 2468, - SystemZ_VMALB = 2469, - SystemZ_VMALE = 2470, - SystemZ_VMALEB = 2471, - SystemZ_VMALEF = 2472, - SystemZ_VMALEH = 2473, - SystemZ_VMALF = 2474, - SystemZ_VMALH = 2475, - SystemZ_VMALHB = 2476, - SystemZ_VMALHF = 2477, - SystemZ_VMALHH = 2478, - SystemZ_VMALHW = 2479, - SystemZ_VMALO = 2480, - SystemZ_VMALOB = 2481, - SystemZ_VMALOF = 2482, - SystemZ_VMALOH = 2483, - SystemZ_VMAO = 2484, - SystemZ_VMAOB = 2485, - SystemZ_VMAOF = 2486, - SystemZ_VMAOH = 2487, - SystemZ_VME = 2488, - SystemZ_VMEB = 2489, - SystemZ_VMEF = 2490, - SystemZ_VMEH = 2491, - SystemZ_VMH = 2492, - SystemZ_VMHB = 2493, - SystemZ_VMHF = 2494, - SystemZ_VMHH = 2495, - SystemZ_VML = 2496, - SystemZ_VMLB = 2497, - SystemZ_VMLE = 2498, - SystemZ_VMLEB = 2499, - SystemZ_VMLEF = 2500, - SystemZ_VMLEH = 2501, - SystemZ_VMLF = 2502, - SystemZ_VMLH = 2503, - SystemZ_VMLHB = 2504, - SystemZ_VMLHF = 2505, - SystemZ_VMLHH = 2506, - SystemZ_VMLHW = 2507, - SystemZ_VMLO = 2508, - SystemZ_VMLOB = 2509, - SystemZ_VMLOF = 2510, - SystemZ_VMLOH = 2511, - SystemZ_VMN = 2512, - SystemZ_VMNB = 2513, - SystemZ_VMNF = 2514, - SystemZ_VMNG = 2515, - SystemZ_VMNH = 2516, - SystemZ_VMNL = 2517, - SystemZ_VMNLB = 2518, - SystemZ_VMNLF = 2519, - SystemZ_VMNLG = 2520, - SystemZ_VMNLH = 2521, - SystemZ_VMO = 2522, - SystemZ_VMOB = 2523, - SystemZ_VMOF = 2524, - SystemZ_VMOH = 2525, - SystemZ_VMP = 2526, - SystemZ_VMRH = 2527, - SystemZ_VMRHB = 2528, - SystemZ_VMRHF = 2529, - SystemZ_VMRHG = 2530, - SystemZ_VMRHH = 2531, - SystemZ_VMRL = 2532, - SystemZ_VMRLB = 2533, - SystemZ_VMRLF = 2534, - SystemZ_VMRLG = 2535, - SystemZ_VMRLH = 2536, - SystemZ_VMSL = 2537, - SystemZ_VMSLG = 2538, - SystemZ_VMSP = 2539, - SystemZ_VMX = 2540, - SystemZ_VMXB = 2541, - SystemZ_VMXF = 2542, - SystemZ_VMXG = 2543, - SystemZ_VMXH = 2544, - SystemZ_VMXL = 2545, - SystemZ_VMXLB = 2546, - SystemZ_VMXLF = 2547, - SystemZ_VMXLG = 2548, - SystemZ_VMXLH = 2549, - SystemZ_VN = 2550, - SystemZ_VNC = 2551, - SystemZ_VNN = 2552, - SystemZ_VNO = 2553, - SystemZ_VNX = 2554, - SystemZ_VO = 2555, - SystemZ_VOC = 2556, - SystemZ_VONE = 2557, - SystemZ_VPDI = 2558, - SystemZ_VPERM = 2559, - SystemZ_VPK = 2560, - SystemZ_VPKF = 2561, - SystemZ_VPKG = 2562, - SystemZ_VPKH = 2563, - SystemZ_VPKLS = 2564, - SystemZ_VPKLSF = 2565, - SystemZ_VPKLSFS = 2566, - SystemZ_VPKLSG = 2567, - SystemZ_VPKLSGS = 2568, - SystemZ_VPKLSH = 2569, - SystemZ_VPKLSHS = 2570, - SystemZ_VPKS = 2571, - SystemZ_VPKSF = 2572, - SystemZ_VPKSFS = 2573, - SystemZ_VPKSG = 2574, - SystemZ_VPKSGS = 2575, - SystemZ_VPKSH = 2576, - SystemZ_VPKSHS = 2577, - SystemZ_VPKZ = 2578, - SystemZ_VPOPCT = 2579, - SystemZ_VPOPCTB = 2580, - SystemZ_VPOPCTF = 2581, - SystemZ_VPOPCTG = 2582, - SystemZ_VPOPCTH = 2583, - SystemZ_VPSOP = 2584, - SystemZ_VREP = 2585, - SystemZ_VREPB = 2586, - SystemZ_VREPF = 2587, - SystemZ_VREPG = 2588, - SystemZ_VREPH = 2589, - SystemZ_VREPI = 2590, - SystemZ_VREPIB = 2591, - SystemZ_VREPIF = 2592, - SystemZ_VREPIG = 2593, - SystemZ_VREPIH = 2594, - SystemZ_VRP = 2595, - SystemZ_VS = 2596, - SystemZ_VSB = 2597, - SystemZ_VSBCBI = 2598, - SystemZ_VSBCBIQ = 2599, - SystemZ_VSBI = 2600, - SystemZ_VSBIQ = 2601, - SystemZ_VSCBI = 2602, - SystemZ_VSCBIB = 2603, - SystemZ_VSCBIF = 2604, - SystemZ_VSCBIG = 2605, - SystemZ_VSCBIH = 2606, - SystemZ_VSCBIQ = 2607, - SystemZ_VSCEF = 2608, - SystemZ_VSCEG = 2609, - SystemZ_VSDP = 2610, - SystemZ_VSEG = 2611, - SystemZ_VSEGB = 2612, - SystemZ_VSEGF = 2613, - SystemZ_VSEGH = 2614, - SystemZ_VSEL = 2615, - SystemZ_VSF = 2616, - SystemZ_VSG = 2617, - SystemZ_VSH = 2618, - SystemZ_VSL = 2619, - SystemZ_VSLB = 2620, - SystemZ_VSLDB = 2621, - SystemZ_VSP = 2622, - SystemZ_VSQ = 2623, - SystemZ_VSRA = 2624, - SystemZ_VSRAB = 2625, - SystemZ_VSRL = 2626, - SystemZ_VSRLB = 2627, - SystemZ_VSRP = 2628, - SystemZ_VST = 2629, - SystemZ_VSTEB = 2630, - SystemZ_VSTEF = 2631, - SystemZ_VSTEG = 2632, - SystemZ_VSTEH = 2633, - SystemZ_VSTL = 2634, - SystemZ_VSTM = 2635, - SystemZ_VSTRC = 2636, - SystemZ_VSTRCB = 2637, - SystemZ_VSTRCBS = 2638, - SystemZ_VSTRCF = 2639, - SystemZ_VSTRCFS = 2640, - SystemZ_VSTRCH = 2641, - SystemZ_VSTRCHS = 2642, - SystemZ_VSTRCZB = 2643, - SystemZ_VSTRCZBS = 2644, - SystemZ_VSTRCZF = 2645, - SystemZ_VSTRCZFS = 2646, - SystemZ_VSTRCZH = 2647, - SystemZ_VSTRCZHS = 2648, - SystemZ_VSTRL = 2649, - SystemZ_VSTRLR = 2650, - SystemZ_VSUM = 2651, - SystemZ_VSUMB = 2652, - SystemZ_VSUMG = 2653, - SystemZ_VSUMGF = 2654, - SystemZ_VSUMGH = 2655, - SystemZ_VSUMH = 2656, - SystemZ_VSUMQ = 2657, - SystemZ_VSUMQF = 2658, - SystemZ_VSUMQG = 2659, - SystemZ_VTM = 2660, - SystemZ_VTP = 2661, - SystemZ_VUPH = 2662, - SystemZ_VUPHB = 2663, - SystemZ_VUPHF = 2664, - SystemZ_VUPHH = 2665, - SystemZ_VUPKZ = 2666, - SystemZ_VUPL = 2667, - SystemZ_VUPLB = 2668, - SystemZ_VUPLF = 2669, - SystemZ_VUPLH = 2670, - SystemZ_VUPLHB = 2671, - SystemZ_VUPLHF = 2672, - SystemZ_VUPLHH = 2673, - SystemZ_VUPLHW = 2674, - SystemZ_VUPLL = 2675, - SystemZ_VUPLLB = 2676, - SystemZ_VUPLLF = 2677, - SystemZ_VUPLLH = 2678, - SystemZ_VX = 2679, - SystemZ_VZERO = 2680, - SystemZ_WCDGB = 2681, - SystemZ_WCDLGB = 2682, - SystemZ_WCGDB = 2683, - SystemZ_WCLGDB = 2684, - SystemZ_WFADB = 2685, - SystemZ_WFASB = 2686, - SystemZ_WFAXB = 2687, - SystemZ_WFC = 2688, - SystemZ_WFCDB = 2689, - SystemZ_WFCEDB = 2690, - SystemZ_WFCEDBS = 2691, - SystemZ_WFCESB = 2692, - SystemZ_WFCESBS = 2693, - SystemZ_WFCEXB = 2694, - SystemZ_WFCEXBS = 2695, - SystemZ_WFCHDB = 2696, - SystemZ_WFCHDBS = 2697, - SystemZ_WFCHEDB = 2698, - SystemZ_WFCHEDBS = 2699, - SystemZ_WFCHESB = 2700, - SystemZ_WFCHESBS = 2701, - SystemZ_WFCHEXB = 2702, - SystemZ_WFCHEXBS = 2703, - SystemZ_WFCHSB = 2704, - SystemZ_WFCHSBS = 2705, - SystemZ_WFCHXB = 2706, - SystemZ_WFCHXBS = 2707, - SystemZ_WFCSB = 2708, - SystemZ_WFCXB = 2709, - SystemZ_WFDDB = 2710, - SystemZ_WFDSB = 2711, - SystemZ_WFDXB = 2712, - SystemZ_WFIDB = 2713, - SystemZ_WFISB = 2714, - SystemZ_WFIXB = 2715, - SystemZ_WFK = 2716, - SystemZ_WFKDB = 2717, - SystemZ_WFKEDB = 2718, - SystemZ_WFKEDBS = 2719, - SystemZ_WFKESB = 2720, - SystemZ_WFKESBS = 2721, - SystemZ_WFKEXB = 2722, - SystemZ_WFKEXBS = 2723, - SystemZ_WFKHDB = 2724, - SystemZ_WFKHDBS = 2725, - SystemZ_WFKHEDB = 2726, - SystemZ_WFKHEDBS = 2727, - SystemZ_WFKHESB = 2728, - SystemZ_WFKHESBS = 2729, - SystemZ_WFKHEXB = 2730, - SystemZ_WFKHEXBS = 2731, - SystemZ_WFKHSB = 2732, - SystemZ_WFKHSBS = 2733, - SystemZ_WFKHXB = 2734, - SystemZ_WFKHXBS = 2735, - SystemZ_WFKSB = 2736, - SystemZ_WFKXB = 2737, - SystemZ_WFLCDB = 2738, - SystemZ_WFLCSB = 2739, - SystemZ_WFLCXB = 2740, - SystemZ_WFLLD = 2741, - SystemZ_WFLLS = 2742, - SystemZ_WFLNDB = 2743, - SystemZ_WFLNSB = 2744, - SystemZ_WFLNXB = 2745, - SystemZ_WFLPDB = 2746, - SystemZ_WFLPSB = 2747, - SystemZ_WFLPXB = 2748, - SystemZ_WFLRD = 2749, - SystemZ_WFLRX = 2750, - SystemZ_WFMADB = 2751, - SystemZ_WFMASB = 2752, - SystemZ_WFMAXB = 2753, - SystemZ_WFMAXDB = 2754, - SystemZ_WFMAXSB = 2755, - SystemZ_WFMAXXB = 2756, - SystemZ_WFMDB = 2757, - SystemZ_WFMINDB = 2758, - SystemZ_WFMINSB = 2759, - SystemZ_WFMINXB = 2760, - SystemZ_WFMSB = 2761, - SystemZ_WFMSDB = 2762, - SystemZ_WFMSSB = 2763, - SystemZ_WFMSXB = 2764, - SystemZ_WFMXB = 2765, - SystemZ_WFNMADB = 2766, - SystemZ_WFNMASB = 2767, - SystemZ_WFNMAXB = 2768, - SystemZ_WFNMSDB = 2769, - SystemZ_WFNMSSB = 2770, - SystemZ_WFNMSXB = 2771, - SystemZ_WFPSODB = 2772, - SystemZ_WFPSOSB = 2773, - SystemZ_WFPSOXB = 2774, - SystemZ_WFSDB = 2775, - SystemZ_WFSQDB = 2776, - SystemZ_WFSQSB = 2777, - SystemZ_WFSQXB = 2778, - SystemZ_WFSSB = 2779, - SystemZ_WFSXB = 2780, - SystemZ_WFTCIDB = 2781, - SystemZ_WFTCISB = 2782, - SystemZ_WFTCIXB = 2783, - SystemZ_WLDEB = 2784, - SystemZ_WLEDB = 2785, - SystemZ_X = 2786, - SystemZ_XC = 2787, - SystemZ_XG = 2788, - SystemZ_XGR = 2789, - SystemZ_XGRK = 2790, - SystemZ_XI = 2791, - SystemZ_XIHF = 2792, - SystemZ_XILF = 2793, - SystemZ_XIY = 2794, - SystemZ_XR = 2795, - SystemZ_XRK = 2796, - SystemZ_XSCH = 2797, - SystemZ_XY = 2798, - SystemZ_ZAP = 2799, - SystemZ_INSTRUCTION_LIST_END = 2800 - }; + SystemZ_PHI = 0, + SystemZ_INLINEASM = 1, + SystemZ_CFI_INSTRUCTION = 2, + SystemZ_EH_LABEL = 3, + SystemZ_GC_LABEL = 4, + SystemZ_ANNOTATION_LABEL = 5, + SystemZ_KILL = 6, + SystemZ_EXTRACT_SUBREG = 7, + SystemZ_INSERT_SUBREG = 8, + SystemZ_IMPLICIT_DEF = 9, + SystemZ_SUBREG_TO_REG = 10, + SystemZ_COPY_TO_REGCLASS = 11, + SystemZ_DBG_VALUE = 12, + SystemZ_DBG_LABEL = 13, + SystemZ_REG_SEQUENCE = 14, + SystemZ_COPY = 15, + SystemZ_BUNDLE = 16, + SystemZ_LIFETIME_START = 17, + SystemZ_LIFETIME_END = 18, + SystemZ_STACKMAP = 19, + SystemZ_FENTRY_CALL = 20, + SystemZ_PATCHPOINT = 21, + SystemZ_LOAD_STACK_GUARD = 22, + SystemZ_STATEPOINT = 23, + SystemZ_LOCAL_ESCAPE = 24, + SystemZ_FAULTING_OP = 25, + SystemZ_PATCHABLE_OP = 26, + SystemZ_PATCHABLE_FUNCTION_ENTER = 27, + SystemZ_PATCHABLE_RET = 28, + SystemZ_PATCHABLE_FUNCTION_EXIT = 29, + SystemZ_PATCHABLE_TAIL_CALL = 30, + SystemZ_PATCHABLE_EVENT_CALL = 31, + SystemZ_PATCHABLE_TYPED_EVENT_CALL = 32, + SystemZ_ICALL_BRANCH_FUNNEL = 33, + SystemZ_G_ADD = 34, + SystemZ_G_SUB = 35, + SystemZ_G_MUL = 36, + SystemZ_G_SDIV = 37, + SystemZ_G_UDIV = 38, + SystemZ_G_SREM = 39, + SystemZ_G_UREM = 40, + SystemZ_G_AND = 41, + SystemZ_G_OR = 42, + SystemZ_G_XOR = 43, + SystemZ_G_IMPLICIT_DEF = 44, + SystemZ_G_PHI = 45, + SystemZ_G_FRAME_INDEX = 46, + SystemZ_G_GLOBAL_VALUE = 47, + SystemZ_G_EXTRACT = 48, + SystemZ_G_UNMERGE_VALUES = 49, + SystemZ_G_INSERT = 50, + SystemZ_G_MERGE_VALUES = 51, + SystemZ_G_PTRTOINT = 52, + SystemZ_G_INTTOPTR = 53, + SystemZ_G_BITCAST = 54, + SystemZ_G_LOAD = 55, + SystemZ_G_SEXTLOAD = 56, + SystemZ_G_ZEXTLOAD = 57, + SystemZ_G_STORE = 58, + SystemZ_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, + SystemZ_G_ATOMIC_CMPXCHG = 60, + SystemZ_G_ATOMICRMW_XCHG = 61, + SystemZ_G_ATOMICRMW_ADD = 62, + SystemZ_G_ATOMICRMW_SUB = 63, + SystemZ_G_ATOMICRMW_AND = 64, + SystemZ_G_ATOMICRMW_NAND = 65, + SystemZ_G_ATOMICRMW_OR = 66, + SystemZ_G_ATOMICRMW_XOR = 67, + SystemZ_G_ATOMICRMW_MAX = 68, + SystemZ_G_ATOMICRMW_MIN = 69, + SystemZ_G_ATOMICRMW_UMAX = 70, + SystemZ_G_ATOMICRMW_UMIN = 71, + SystemZ_G_BRCOND = 72, + SystemZ_G_BRINDIRECT = 73, + SystemZ_G_INTRINSIC = 74, + SystemZ_G_INTRINSIC_W_SIDE_EFFECTS = 75, + SystemZ_G_ANYEXT = 76, + SystemZ_G_TRUNC = 77, + SystemZ_G_CONSTANT = 78, + SystemZ_G_FCONSTANT = 79, + SystemZ_G_VASTART = 80, + SystemZ_G_VAARG = 81, + SystemZ_G_SEXT = 82, + SystemZ_G_ZEXT = 83, + SystemZ_G_SHL = 84, + SystemZ_G_LSHR = 85, + SystemZ_G_ASHR = 86, + SystemZ_G_ICMP = 87, + SystemZ_G_FCMP = 88, + SystemZ_G_SELECT = 89, + SystemZ_G_UADDE = 90, + SystemZ_G_USUBE = 91, + SystemZ_G_SADDO = 92, + SystemZ_G_SSUBO = 93, + SystemZ_G_UMULO = 94, + SystemZ_G_SMULO = 95, + SystemZ_G_UMULH = 96, + SystemZ_G_SMULH = 97, + SystemZ_G_FADD = 98, + SystemZ_G_FSUB = 99, + SystemZ_G_FMUL = 100, + SystemZ_G_FMA = 101, + SystemZ_G_FDIV = 102, + SystemZ_G_FREM = 103, + SystemZ_G_FPOW = 104, + SystemZ_G_FEXP = 105, + SystemZ_G_FEXP2 = 106, + SystemZ_G_FLOG = 107, + SystemZ_G_FLOG2 = 108, + SystemZ_G_FNEG = 109, + SystemZ_G_FPEXT = 110, + SystemZ_G_FPTRUNC = 111, + SystemZ_G_FPTOSI = 112, + SystemZ_G_FPTOUI = 113, + SystemZ_G_SITOFP = 114, + SystemZ_G_UITOFP = 115, + SystemZ_G_FABS = 116, + SystemZ_G_GEP = 117, + SystemZ_G_PTR_MASK = 118, + SystemZ_G_BR = 119, + SystemZ_G_INSERT_VECTOR_ELT = 120, + SystemZ_G_EXTRACT_VECTOR_ELT = 121, + SystemZ_G_SHUFFLE_VECTOR = 122, + SystemZ_G_BSWAP = 123, + SystemZ_G_ADDRSPACE_CAST = 124, + SystemZ_ADJCALLSTACKDOWN = 125, + SystemZ_ADJCALLSTACKUP = 126, + SystemZ_ADJDYNALLOC = 127, + SystemZ_AEXT128 = 128, + SystemZ_AFIMux = 129, + SystemZ_AHIMux = 130, + SystemZ_AHIMuxK = 131, + SystemZ_ATOMIC_CMP_SWAPW = 132, + SystemZ_ATOMIC_LOADW_AFI = 133, + SystemZ_ATOMIC_LOADW_AR = 134, + SystemZ_ATOMIC_LOADW_MAX = 135, + SystemZ_ATOMIC_LOADW_MIN = 136, + SystemZ_ATOMIC_LOADW_NILH = 137, + SystemZ_ATOMIC_LOADW_NILHi = 138, + SystemZ_ATOMIC_LOADW_NR = 139, + SystemZ_ATOMIC_LOADW_NRi = 140, + SystemZ_ATOMIC_LOADW_OILH = 141, + SystemZ_ATOMIC_LOADW_OR = 142, + SystemZ_ATOMIC_LOADW_SR = 143, + SystemZ_ATOMIC_LOADW_UMAX = 144, + SystemZ_ATOMIC_LOADW_UMIN = 145, + SystemZ_ATOMIC_LOADW_XILF = 146, + SystemZ_ATOMIC_LOADW_XR = 147, + SystemZ_ATOMIC_LOAD_AFI = 148, + SystemZ_ATOMIC_LOAD_AGFI = 149, + SystemZ_ATOMIC_LOAD_AGHI = 150, + SystemZ_ATOMIC_LOAD_AGR = 151, + SystemZ_ATOMIC_LOAD_AHI = 152, + SystemZ_ATOMIC_LOAD_AR = 153, + SystemZ_ATOMIC_LOAD_MAX_32 = 154, + SystemZ_ATOMIC_LOAD_MAX_64 = 155, + SystemZ_ATOMIC_LOAD_MIN_32 = 156, + SystemZ_ATOMIC_LOAD_MIN_64 = 157, + SystemZ_ATOMIC_LOAD_NGR = 158, + SystemZ_ATOMIC_LOAD_NGRi = 159, + SystemZ_ATOMIC_LOAD_NIHF64 = 160, + SystemZ_ATOMIC_LOAD_NIHF64i = 161, + SystemZ_ATOMIC_LOAD_NIHH64 = 162, + SystemZ_ATOMIC_LOAD_NIHH64i = 163, + SystemZ_ATOMIC_LOAD_NIHL64 = 164, + SystemZ_ATOMIC_LOAD_NIHL64i = 165, + SystemZ_ATOMIC_LOAD_NILF = 166, + SystemZ_ATOMIC_LOAD_NILF64 = 167, + SystemZ_ATOMIC_LOAD_NILF64i = 168, + SystemZ_ATOMIC_LOAD_NILFi = 169, + SystemZ_ATOMIC_LOAD_NILH = 170, + SystemZ_ATOMIC_LOAD_NILH64 = 171, + SystemZ_ATOMIC_LOAD_NILH64i = 172, + SystemZ_ATOMIC_LOAD_NILHi = 173, + SystemZ_ATOMIC_LOAD_NILL = 174, + SystemZ_ATOMIC_LOAD_NILL64 = 175, + SystemZ_ATOMIC_LOAD_NILL64i = 176, + SystemZ_ATOMIC_LOAD_NILLi = 177, + SystemZ_ATOMIC_LOAD_NR = 178, + SystemZ_ATOMIC_LOAD_NRi = 179, + SystemZ_ATOMIC_LOAD_OGR = 180, + SystemZ_ATOMIC_LOAD_OIHF64 = 181, + SystemZ_ATOMIC_LOAD_OIHH64 = 182, + SystemZ_ATOMIC_LOAD_OIHL64 = 183, + SystemZ_ATOMIC_LOAD_OILF = 184, + SystemZ_ATOMIC_LOAD_OILF64 = 185, + SystemZ_ATOMIC_LOAD_OILH = 186, + SystemZ_ATOMIC_LOAD_OILH64 = 187, + SystemZ_ATOMIC_LOAD_OILL = 188, + SystemZ_ATOMIC_LOAD_OILL64 = 189, + SystemZ_ATOMIC_LOAD_OR = 190, + SystemZ_ATOMIC_LOAD_SGR = 191, + SystemZ_ATOMIC_LOAD_SR = 192, + SystemZ_ATOMIC_LOAD_UMAX_32 = 193, + SystemZ_ATOMIC_LOAD_UMAX_64 = 194, + SystemZ_ATOMIC_LOAD_UMIN_32 = 195, + SystemZ_ATOMIC_LOAD_UMIN_64 = 196, + SystemZ_ATOMIC_LOAD_XGR = 197, + SystemZ_ATOMIC_LOAD_XIHF64 = 198, + SystemZ_ATOMIC_LOAD_XILF = 199, + SystemZ_ATOMIC_LOAD_XILF64 = 200, + SystemZ_ATOMIC_LOAD_XR = 201, + SystemZ_ATOMIC_SWAPW = 202, + SystemZ_ATOMIC_SWAP_32 = 203, + SystemZ_ATOMIC_SWAP_64 = 204, + SystemZ_CFIMux = 205, + SystemZ_CGIBCall = 206, + SystemZ_CGIBReturn = 207, + SystemZ_CGRBCall = 208, + SystemZ_CGRBReturn = 209, + SystemZ_CHIMux = 210, + SystemZ_CIBCall = 211, + SystemZ_CIBReturn = 212, + SystemZ_CLCLoop = 213, + SystemZ_CLCSequence = 214, + SystemZ_CLFIMux = 215, + SystemZ_CLGIBCall = 216, + SystemZ_CLGIBReturn = 217, + SystemZ_CLGRBCall = 218, + SystemZ_CLGRBReturn = 219, + SystemZ_CLIBCall = 220, + SystemZ_CLIBReturn = 221, + SystemZ_CLMux = 222, + SystemZ_CLRBCall = 223, + SystemZ_CLRBReturn = 224, + SystemZ_CLSTLoop = 225, + SystemZ_CMux = 226, + SystemZ_CRBCall = 227, + SystemZ_CRBReturn = 228, + SystemZ_CallBASR = 229, + SystemZ_CallBCR = 230, + SystemZ_CallBR = 231, + SystemZ_CallBRASL = 232, + SystemZ_CallBRCL = 233, + SystemZ_CallJG = 234, + SystemZ_CondReturn = 235, + SystemZ_CondStore16 = 236, + SystemZ_CondStore16Inv = 237, + SystemZ_CondStore16Mux = 238, + SystemZ_CondStore16MuxInv = 239, + SystemZ_CondStore32 = 240, + SystemZ_CondStore32Inv = 241, + SystemZ_CondStore32Mux = 242, + SystemZ_CondStore32MuxInv = 243, + SystemZ_CondStore64 = 244, + SystemZ_CondStore64Inv = 245, + SystemZ_CondStore8 = 246, + SystemZ_CondStore8Inv = 247, + SystemZ_CondStore8Mux = 248, + SystemZ_CondStore8MuxInv = 249, + SystemZ_CondStoreF32 = 250, + SystemZ_CondStoreF32Inv = 251, + SystemZ_CondStoreF64 = 252, + SystemZ_CondStoreF64Inv = 253, + SystemZ_CondTrap = 254, + SystemZ_GOT = 255, + SystemZ_IIFMux = 256, + SystemZ_IIHF64 = 257, + SystemZ_IIHH64 = 258, + SystemZ_IIHL64 = 259, + SystemZ_IIHMux = 260, + SystemZ_IILF64 = 261, + SystemZ_IILH64 = 262, + SystemZ_IILL64 = 263, + SystemZ_IILMux = 264, + SystemZ_L128 = 265, + SystemZ_LBMux = 266, + SystemZ_LEFR = 267, + SystemZ_LFER = 268, + SystemZ_LHIMux = 269, + SystemZ_LHMux = 270, + SystemZ_LLCMux = 271, + SystemZ_LLCRMux = 272, + SystemZ_LLHMux = 273, + SystemZ_LLHRMux = 274, + SystemZ_LMux = 275, + SystemZ_LOCHIMux = 276, + SystemZ_LOCMux = 277, + SystemZ_LOCRMux = 278, + SystemZ_LRMux = 279, + SystemZ_LTDBRCompare_VecPseudo = 280, + SystemZ_LTEBRCompare_VecPseudo = 281, + SystemZ_LTXBRCompare_VecPseudo = 282, + SystemZ_LX = 283, + SystemZ_MVCLoop = 284, + SystemZ_MVCSequence = 285, + SystemZ_MVSTLoop = 286, + SystemZ_MemBarrier = 287, + SystemZ_NCLoop = 288, + SystemZ_NCSequence = 289, + SystemZ_NIFMux = 290, + SystemZ_NIHF64 = 291, + SystemZ_NIHH64 = 292, + SystemZ_NIHL64 = 293, + SystemZ_NIHMux = 294, + SystemZ_NILF64 = 295, + SystemZ_NILH64 = 296, + SystemZ_NILL64 = 297, + SystemZ_NILMux = 298, + SystemZ_OCLoop = 299, + SystemZ_OCSequence = 300, + SystemZ_OIFMux = 301, + SystemZ_OIHF64 = 302, + SystemZ_OIHH64 = 303, + SystemZ_OIHL64 = 304, + SystemZ_OIHMux = 305, + SystemZ_OILF64 = 306, + SystemZ_OILH64 = 307, + SystemZ_OILL64 = 308, + SystemZ_OILMux = 309, + SystemZ_PAIR128 = 310, + SystemZ_RISBHH = 311, + SystemZ_RISBHL = 312, + SystemZ_RISBLH = 313, + SystemZ_RISBLL = 314, + SystemZ_RISBMux = 315, + SystemZ_Return = 316, + SystemZ_SRSTLoop = 317, + SystemZ_ST128 = 318, + SystemZ_STCMux = 319, + SystemZ_STHMux = 320, + SystemZ_STMux = 321, + SystemZ_STOCMux = 322, + SystemZ_STX = 323, + SystemZ_Select32 = 324, + SystemZ_Select64 = 325, + SystemZ_SelectF128 = 326, + SystemZ_SelectF32 = 327, + SystemZ_SelectF64 = 328, + SystemZ_SelectVR128 = 329, + SystemZ_SelectVR32 = 330, + SystemZ_SelectVR64 = 331, + SystemZ_Serialize = 332, + SystemZ_TBEGIN_nofloat = 333, + SystemZ_TLS_GDCALL = 334, + SystemZ_TLS_LDCALL = 335, + SystemZ_TMHH64 = 336, + SystemZ_TMHL64 = 337, + SystemZ_TMHMux = 338, + SystemZ_TMLH64 = 339, + SystemZ_TMLL64 = 340, + SystemZ_TMLMux = 341, + SystemZ_Trap = 342, + SystemZ_VL32 = 343, + SystemZ_VL64 = 344, + SystemZ_VLR32 = 345, + SystemZ_VLR64 = 346, + SystemZ_VLVGP32 = 347, + SystemZ_VST32 = 348, + SystemZ_VST64 = 349, + SystemZ_XCLoop = 350, + SystemZ_XCSequence = 351, + SystemZ_XIFMux = 352, + SystemZ_XIHF64 = 353, + SystemZ_XILF64 = 354, + SystemZ_ZEXT128 = 355, + SystemZ_A = 356, + SystemZ_AD = 357, + SystemZ_ADB = 358, + SystemZ_ADBR = 359, + SystemZ_ADR = 360, + SystemZ_ADTR = 361, + SystemZ_ADTRA = 362, + SystemZ_AE = 363, + SystemZ_AEB = 364, + SystemZ_AEBR = 365, + SystemZ_AER = 366, + SystemZ_AFI = 367, + SystemZ_AG = 368, + SystemZ_AGF = 369, + SystemZ_AGFI = 370, + SystemZ_AGFR = 371, + SystemZ_AGH = 372, + SystemZ_AGHI = 373, + SystemZ_AGHIK = 374, + SystemZ_AGR = 375, + SystemZ_AGRK = 376, + SystemZ_AGSI = 377, + SystemZ_AH = 378, + SystemZ_AHHHR = 379, + SystemZ_AHHLR = 380, + SystemZ_AHI = 381, + SystemZ_AHIK = 382, + SystemZ_AHY = 383, + SystemZ_AIH = 384, + SystemZ_AL = 385, + SystemZ_ALC = 386, + SystemZ_ALCG = 387, + SystemZ_ALCGR = 388, + SystemZ_ALCR = 389, + SystemZ_ALFI = 390, + SystemZ_ALG = 391, + SystemZ_ALGF = 392, + SystemZ_ALGFI = 393, + SystemZ_ALGFR = 394, + SystemZ_ALGHSIK = 395, + SystemZ_ALGR = 396, + SystemZ_ALGRK = 397, + SystemZ_ALGSI = 398, + SystemZ_ALHHHR = 399, + SystemZ_ALHHLR = 400, + SystemZ_ALHSIK = 401, + SystemZ_ALR = 402, + SystemZ_ALRK = 403, + SystemZ_ALSI = 404, + SystemZ_ALSIH = 405, + SystemZ_ALSIHN = 406, + SystemZ_ALY = 407, + SystemZ_AP = 408, + SystemZ_AR = 409, + SystemZ_ARK = 410, + SystemZ_ASI = 411, + SystemZ_AU = 412, + SystemZ_AUR = 413, + SystemZ_AW = 414, + SystemZ_AWR = 415, + SystemZ_AXBR = 416, + SystemZ_AXR = 417, + SystemZ_AXTR = 418, + SystemZ_AXTRA = 419, + SystemZ_AY = 420, + SystemZ_B = 421, + SystemZ_BAKR = 422, + SystemZ_BAL = 423, + SystemZ_BALR = 424, + SystemZ_BAS = 425, + SystemZ_BASR = 426, + SystemZ_BASSM = 427, + SystemZ_BAsmE = 428, + SystemZ_BAsmH = 429, + SystemZ_BAsmHE = 430, + SystemZ_BAsmL = 431, + SystemZ_BAsmLE = 432, + SystemZ_BAsmLH = 433, + SystemZ_BAsmM = 434, + SystemZ_BAsmNE = 435, + SystemZ_BAsmNH = 436, + SystemZ_BAsmNHE = 437, + SystemZ_BAsmNL = 438, + SystemZ_BAsmNLE = 439, + SystemZ_BAsmNLH = 440, + SystemZ_BAsmNM = 441, + SystemZ_BAsmNO = 442, + SystemZ_BAsmNP = 443, + SystemZ_BAsmNZ = 444, + SystemZ_BAsmO = 445, + SystemZ_BAsmP = 446, + SystemZ_BAsmZ = 447, + SystemZ_BC = 448, + SystemZ_BCAsm = 449, + SystemZ_BCR = 450, + SystemZ_BCRAsm = 451, + SystemZ_BCT = 452, + SystemZ_BCTG = 453, + SystemZ_BCTGR = 454, + SystemZ_BCTR = 455, + SystemZ_BI = 456, + SystemZ_BIAsmE = 457, + SystemZ_BIAsmH = 458, + SystemZ_BIAsmHE = 459, + SystemZ_BIAsmL = 460, + SystemZ_BIAsmLE = 461, + SystemZ_BIAsmLH = 462, + SystemZ_BIAsmM = 463, + SystemZ_BIAsmNE = 464, + SystemZ_BIAsmNH = 465, + SystemZ_BIAsmNHE = 466, + SystemZ_BIAsmNL = 467, + SystemZ_BIAsmNLE = 468, + SystemZ_BIAsmNLH = 469, + SystemZ_BIAsmNM = 470, + SystemZ_BIAsmNO = 471, + SystemZ_BIAsmNP = 472, + SystemZ_BIAsmNZ = 473, + SystemZ_BIAsmO = 474, + SystemZ_BIAsmP = 475, + SystemZ_BIAsmZ = 476, + SystemZ_BIC = 477, + SystemZ_BICAsm = 478, + SystemZ_BPP = 479, + SystemZ_BPRP = 480, + SystemZ_BR = 481, + SystemZ_BRAS = 482, + SystemZ_BRASL = 483, + SystemZ_BRAsmE = 484, + SystemZ_BRAsmH = 485, + SystemZ_BRAsmHE = 486, + SystemZ_BRAsmL = 487, + SystemZ_BRAsmLE = 488, + SystemZ_BRAsmLH = 489, + SystemZ_BRAsmM = 490, + SystemZ_BRAsmNE = 491, + SystemZ_BRAsmNH = 492, + SystemZ_BRAsmNHE = 493, + SystemZ_BRAsmNL = 494, + SystemZ_BRAsmNLE = 495, + SystemZ_BRAsmNLH = 496, + SystemZ_BRAsmNM = 497, + SystemZ_BRAsmNO = 498, + SystemZ_BRAsmNP = 499, + SystemZ_BRAsmNZ = 500, + SystemZ_BRAsmO = 501, + SystemZ_BRAsmP = 502, + SystemZ_BRAsmZ = 503, + SystemZ_BRC = 504, + SystemZ_BRCAsm = 505, + SystemZ_BRCL = 506, + SystemZ_BRCLAsm = 507, + SystemZ_BRCT = 508, + SystemZ_BRCTG = 509, + SystemZ_BRCTH = 510, + SystemZ_BRXH = 511, + SystemZ_BRXHG = 512, + SystemZ_BRXLE = 513, + SystemZ_BRXLG = 514, + SystemZ_BSA = 515, + SystemZ_BSG = 516, + SystemZ_BSM = 517, + SystemZ_BXH = 518, + SystemZ_BXHG = 519, + SystemZ_BXLE = 520, + SystemZ_BXLEG = 521, + SystemZ_C = 522, + SystemZ_CD = 523, + SystemZ_CDB = 524, + SystemZ_CDBR = 525, + SystemZ_CDFBR = 526, + SystemZ_CDFBRA = 527, + SystemZ_CDFR = 528, + SystemZ_CDFTR = 529, + SystemZ_CDGBR = 530, + SystemZ_CDGBRA = 531, + SystemZ_CDGR = 532, + SystemZ_CDGTR = 533, + SystemZ_CDGTRA = 534, + SystemZ_CDLFBR = 535, + SystemZ_CDLFTR = 536, + SystemZ_CDLGBR = 537, + SystemZ_CDLGTR = 538, + SystemZ_CDPT = 539, + SystemZ_CDR = 540, + SystemZ_CDS = 541, + SystemZ_CDSG = 542, + SystemZ_CDSTR = 543, + SystemZ_CDSY = 544, + SystemZ_CDTR = 545, + SystemZ_CDUTR = 546, + SystemZ_CDZT = 547, + SystemZ_CE = 548, + SystemZ_CEB = 549, + SystemZ_CEBR = 550, + SystemZ_CEDTR = 551, + SystemZ_CEFBR = 552, + SystemZ_CEFBRA = 553, + SystemZ_CEFR = 554, + SystemZ_CEGBR = 555, + SystemZ_CEGBRA = 556, + SystemZ_CEGR = 557, + SystemZ_CELFBR = 558, + SystemZ_CELGBR = 559, + SystemZ_CER = 560, + SystemZ_CEXTR = 561, + SystemZ_CFC = 562, + SystemZ_CFDBR = 563, + SystemZ_CFDBRA = 564, + SystemZ_CFDR = 565, + SystemZ_CFDTR = 566, + SystemZ_CFEBR = 567, + SystemZ_CFEBRA = 568, + SystemZ_CFER = 569, + SystemZ_CFI = 570, + SystemZ_CFXBR = 571, + SystemZ_CFXBRA = 572, + SystemZ_CFXR = 573, + SystemZ_CFXTR = 574, + SystemZ_CG = 575, + SystemZ_CGDBR = 576, + SystemZ_CGDBRA = 577, + SystemZ_CGDR = 578, + SystemZ_CGDTR = 579, + SystemZ_CGDTRA = 580, + SystemZ_CGEBR = 581, + SystemZ_CGEBRA = 582, + SystemZ_CGER = 583, + SystemZ_CGF = 584, + SystemZ_CGFI = 585, + SystemZ_CGFR = 586, + SystemZ_CGFRL = 587, + SystemZ_CGH = 588, + SystemZ_CGHI = 589, + SystemZ_CGHRL = 590, + SystemZ_CGHSI = 591, + SystemZ_CGIB = 592, + SystemZ_CGIBAsm = 593, + SystemZ_CGIBAsmE = 594, + SystemZ_CGIBAsmH = 595, + SystemZ_CGIBAsmHE = 596, + SystemZ_CGIBAsmL = 597, + SystemZ_CGIBAsmLE = 598, + SystemZ_CGIBAsmLH = 599, + SystemZ_CGIBAsmNE = 600, + SystemZ_CGIBAsmNH = 601, + SystemZ_CGIBAsmNHE = 602, + SystemZ_CGIBAsmNL = 603, + SystemZ_CGIBAsmNLE = 604, + SystemZ_CGIBAsmNLH = 605, + SystemZ_CGIJ = 606, + SystemZ_CGIJAsm = 607, + SystemZ_CGIJAsmE = 608, + SystemZ_CGIJAsmH = 609, + SystemZ_CGIJAsmHE = 610, + SystemZ_CGIJAsmL = 611, + SystemZ_CGIJAsmLE = 612, + SystemZ_CGIJAsmLH = 613, + SystemZ_CGIJAsmNE = 614, + SystemZ_CGIJAsmNH = 615, + SystemZ_CGIJAsmNHE = 616, + SystemZ_CGIJAsmNL = 617, + SystemZ_CGIJAsmNLE = 618, + SystemZ_CGIJAsmNLH = 619, + SystemZ_CGIT = 620, + SystemZ_CGITAsm = 621, + SystemZ_CGITAsmE = 622, + SystemZ_CGITAsmH = 623, + SystemZ_CGITAsmHE = 624, + SystemZ_CGITAsmL = 625, + SystemZ_CGITAsmLE = 626, + SystemZ_CGITAsmLH = 627, + SystemZ_CGITAsmNE = 628, + SystemZ_CGITAsmNH = 629, + SystemZ_CGITAsmNHE = 630, + SystemZ_CGITAsmNL = 631, + SystemZ_CGITAsmNLE = 632, + SystemZ_CGITAsmNLH = 633, + SystemZ_CGR = 634, + SystemZ_CGRB = 635, + SystemZ_CGRBAsm = 636, + SystemZ_CGRBAsmE = 637, + SystemZ_CGRBAsmH = 638, + SystemZ_CGRBAsmHE = 639, + SystemZ_CGRBAsmL = 640, + SystemZ_CGRBAsmLE = 641, + SystemZ_CGRBAsmLH = 642, + SystemZ_CGRBAsmNE = 643, + SystemZ_CGRBAsmNH = 644, + SystemZ_CGRBAsmNHE = 645, + SystemZ_CGRBAsmNL = 646, + SystemZ_CGRBAsmNLE = 647, + SystemZ_CGRBAsmNLH = 648, + SystemZ_CGRJ = 649, + SystemZ_CGRJAsm = 650, + SystemZ_CGRJAsmE = 651, + SystemZ_CGRJAsmH = 652, + SystemZ_CGRJAsmHE = 653, + SystemZ_CGRJAsmL = 654, + SystemZ_CGRJAsmLE = 655, + SystemZ_CGRJAsmLH = 656, + SystemZ_CGRJAsmNE = 657, + SystemZ_CGRJAsmNH = 658, + SystemZ_CGRJAsmNHE = 659, + SystemZ_CGRJAsmNL = 660, + SystemZ_CGRJAsmNLE = 661, + SystemZ_CGRJAsmNLH = 662, + SystemZ_CGRL = 663, + SystemZ_CGRT = 664, + SystemZ_CGRTAsm = 665, + SystemZ_CGRTAsmE = 666, + SystemZ_CGRTAsmH = 667, + SystemZ_CGRTAsmHE = 668, + SystemZ_CGRTAsmL = 669, + SystemZ_CGRTAsmLE = 670, + SystemZ_CGRTAsmLH = 671, + SystemZ_CGRTAsmNE = 672, + SystemZ_CGRTAsmNH = 673, + SystemZ_CGRTAsmNHE = 674, + SystemZ_CGRTAsmNL = 675, + SystemZ_CGRTAsmNLE = 676, + SystemZ_CGRTAsmNLH = 677, + SystemZ_CGXBR = 678, + SystemZ_CGXBRA = 679, + SystemZ_CGXR = 680, + SystemZ_CGXTR = 681, + SystemZ_CGXTRA = 682, + SystemZ_CH = 683, + SystemZ_CHF = 684, + SystemZ_CHHR = 685, + SystemZ_CHHSI = 686, + SystemZ_CHI = 687, + SystemZ_CHLR = 688, + SystemZ_CHRL = 689, + SystemZ_CHSI = 690, + SystemZ_CHY = 691, + SystemZ_CIB = 692, + SystemZ_CIBAsm = 693, + SystemZ_CIBAsmE = 694, + SystemZ_CIBAsmH = 695, + SystemZ_CIBAsmHE = 696, + SystemZ_CIBAsmL = 697, + SystemZ_CIBAsmLE = 698, + SystemZ_CIBAsmLH = 699, + SystemZ_CIBAsmNE = 700, + SystemZ_CIBAsmNH = 701, + SystemZ_CIBAsmNHE = 702, + SystemZ_CIBAsmNL = 703, + SystemZ_CIBAsmNLE = 704, + SystemZ_CIBAsmNLH = 705, + SystemZ_CIH = 706, + SystemZ_CIJ = 707, + SystemZ_CIJAsm = 708, + SystemZ_CIJAsmE = 709, + SystemZ_CIJAsmH = 710, + SystemZ_CIJAsmHE = 711, + SystemZ_CIJAsmL = 712, + SystemZ_CIJAsmLE = 713, + SystemZ_CIJAsmLH = 714, + SystemZ_CIJAsmNE = 715, + SystemZ_CIJAsmNH = 716, + SystemZ_CIJAsmNHE = 717, + SystemZ_CIJAsmNL = 718, + SystemZ_CIJAsmNLE = 719, + SystemZ_CIJAsmNLH = 720, + SystemZ_CIT = 721, + SystemZ_CITAsm = 722, + SystemZ_CITAsmE = 723, + SystemZ_CITAsmH = 724, + SystemZ_CITAsmHE = 725, + SystemZ_CITAsmL = 726, + SystemZ_CITAsmLE = 727, + SystemZ_CITAsmLH = 728, + SystemZ_CITAsmNE = 729, + SystemZ_CITAsmNH = 730, + SystemZ_CITAsmNHE = 731, + SystemZ_CITAsmNL = 732, + SystemZ_CITAsmNLE = 733, + SystemZ_CITAsmNLH = 734, + SystemZ_CKSM = 735, + SystemZ_CL = 736, + SystemZ_CLC = 737, + SystemZ_CLCL = 738, + SystemZ_CLCLE = 739, + SystemZ_CLCLU = 740, + SystemZ_CLFDBR = 741, + SystemZ_CLFDTR = 742, + SystemZ_CLFEBR = 743, + SystemZ_CLFHSI = 744, + SystemZ_CLFI = 745, + SystemZ_CLFIT = 746, + SystemZ_CLFITAsm = 747, + SystemZ_CLFITAsmE = 748, + SystemZ_CLFITAsmH = 749, + SystemZ_CLFITAsmHE = 750, + SystemZ_CLFITAsmL = 751, + SystemZ_CLFITAsmLE = 752, + SystemZ_CLFITAsmLH = 753, + SystemZ_CLFITAsmNE = 754, + SystemZ_CLFITAsmNH = 755, + SystemZ_CLFITAsmNHE = 756, + SystemZ_CLFITAsmNL = 757, + SystemZ_CLFITAsmNLE = 758, + SystemZ_CLFITAsmNLH = 759, + SystemZ_CLFXBR = 760, + SystemZ_CLFXTR = 761, + SystemZ_CLG = 762, + SystemZ_CLGDBR = 763, + SystemZ_CLGDTR = 764, + SystemZ_CLGEBR = 765, + SystemZ_CLGF = 766, + SystemZ_CLGFI = 767, + SystemZ_CLGFR = 768, + SystemZ_CLGFRL = 769, + SystemZ_CLGHRL = 770, + SystemZ_CLGHSI = 771, + SystemZ_CLGIB = 772, + SystemZ_CLGIBAsm = 773, + SystemZ_CLGIBAsmE = 774, + SystemZ_CLGIBAsmH = 775, + SystemZ_CLGIBAsmHE = 776, + SystemZ_CLGIBAsmL = 777, + SystemZ_CLGIBAsmLE = 778, + SystemZ_CLGIBAsmLH = 779, + SystemZ_CLGIBAsmNE = 780, + SystemZ_CLGIBAsmNH = 781, + SystemZ_CLGIBAsmNHE = 782, + SystemZ_CLGIBAsmNL = 783, + SystemZ_CLGIBAsmNLE = 784, + SystemZ_CLGIBAsmNLH = 785, + SystemZ_CLGIJ = 786, + SystemZ_CLGIJAsm = 787, + SystemZ_CLGIJAsmE = 788, + SystemZ_CLGIJAsmH = 789, + SystemZ_CLGIJAsmHE = 790, + SystemZ_CLGIJAsmL = 791, + SystemZ_CLGIJAsmLE = 792, + SystemZ_CLGIJAsmLH = 793, + SystemZ_CLGIJAsmNE = 794, + SystemZ_CLGIJAsmNH = 795, + SystemZ_CLGIJAsmNHE = 796, + SystemZ_CLGIJAsmNL = 797, + SystemZ_CLGIJAsmNLE = 798, + SystemZ_CLGIJAsmNLH = 799, + SystemZ_CLGIT = 800, + SystemZ_CLGITAsm = 801, + SystemZ_CLGITAsmE = 802, + SystemZ_CLGITAsmH = 803, + SystemZ_CLGITAsmHE = 804, + SystemZ_CLGITAsmL = 805, + SystemZ_CLGITAsmLE = 806, + SystemZ_CLGITAsmLH = 807, + SystemZ_CLGITAsmNE = 808, + SystemZ_CLGITAsmNH = 809, + SystemZ_CLGITAsmNHE = 810, + SystemZ_CLGITAsmNL = 811, + SystemZ_CLGITAsmNLE = 812, + SystemZ_CLGITAsmNLH = 813, + SystemZ_CLGR = 814, + SystemZ_CLGRB = 815, + SystemZ_CLGRBAsm = 816, + SystemZ_CLGRBAsmE = 817, + SystemZ_CLGRBAsmH = 818, + SystemZ_CLGRBAsmHE = 819, + SystemZ_CLGRBAsmL = 820, + SystemZ_CLGRBAsmLE = 821, + SystemZ_CLGRBAsmLH = 822, + SystemZ_CLGRBAsmNE = 823, + SystemZ_CLGRBAsmNH = 824, + SystemZ_CLGRBAsmNHE = 825, + SystemZ_CLGRBAsmNL = 826, + SystemZ_CLGRBAsmNLE = 827, + SystemZ_CLGRBAsmNLH = 828, + SystemZ_CLGRJ = 829, + SystemZ_CLGRJAsm = 830, + SystemZ_CLGRJAsmE = 831, + SystemZ_CLGRJAsmH = 832, + SystemZ_CLGRJAsmHE = 833, + SystemZ_CLGRJAsmL = 834, + SystemZ_CLGRJAsmLE = 835, + SystemZ_CLGRJAsmLH = 836, + SystemZ_CLGRJAsmNE = 837, + SystemZ_CLGRJAsmNH = 838, + SystemZ_CLGRJAsmNHE = 839, + SystemZ_CLGRJAsmNL = 840, + SystemZ_CLGRJAsmNLE = 841, + SystemZ_CLGRJAsmNLH = 842, + SystemZ_CLGRL = 843, + SystemZ_CLGRT = 844, + SystemZ_CLGRTAsm = 845, + SystemZ_CLGRTAsmE = 846, + SystemZ_CLGRTAsmH = 847, + SystemZ_CLGRTAsmHE = 848, + SystemZ_CLGRTAsmL = 849, + SystemZ_CLGRTAsmLE = 850, + SystemZ_CLGRTAsmLH = 851, + SystemZ_CLGRTAsmNE = 852, + SystemZ_CLGRTAsmNH = 853, + SystemZ_CLGRTAsmNHE = 854, + SystemZ_CLGRTAsmNL = 855, + SystemZ_CLGRTAsmNLE = 856, + SystemZ_CLGRTAsmNLH = 857, + SystemZ_CLGT = 858, + SystemZ_CLGTAsm = 859, + SystemZ_CLGTAsmE = 860, + SystemZ_CLGTAsmH = 861, + SystemZ_CLGTAsmHE = 862, + SystemZ_CLGTAsmL = 863, + SystemZ_CLGTAsmLE = 864, + SystemZ_CLGTAsmLH = 865, + SystemZ_CLGTAsmNE = 866, + SystemZ_CLGTAsmNH = 867, + SystemZ_CLGTAsmNHE = 868, + SystemZ_CLGTAsmNL = 869, + SystemZ_CLGTAsmNLE = 870, + SystemZ_CLGTAsmNLH = 871, + SystemZ_CLGXBR = 872, + SystemZ_CLGXTR = 873, + SystemZ_CLHF = 874, + SystemZ_CLHHR = 875, + SystemZ_CLHHSI = 876, + SystemZ_CLHLR = 877, + SystemZ_CLHRL = 878, + SystemZ_CLI = 879, + SystemZ_CLIB = 880, + SystemZ_CLIBAsm = 881, + SystemZ_CLIBAsmE = 882, + SystemZ_CLIBAsmH = 883, + SystemZ_CLIBAsmHE = 884, + SystemZ_CLIBAsmL = 885, + SystemZ_CLIBAsmLE = 886, + SystemZ_CLIBAsmLH = 887, + SystemZ_CLIBAsmNE = 888, + SystemZ_CLIBAsmNH = 889, + SystemZ_CLIBAsmNHE = 890, + SystemZ_CLIBAsmNL = 891, + SystemZ_CLIBAsmNLE = 892, + SystemZ_CLIBAsmNLH = 893, + SystemZ_CLIH = 894, + SystemZ_CLIJ = 895, + SystemZ_CLIJAsm = 896, + SystemZ_CLIJAsmE = 897, + SystemZ_CLIJAsmH = 898, + SystemZ_CLIJAsmHE = 899, + SystemZ_CLIJAsmL = 900, + SystemZ_CLIJAsmLE = 901, + SystemZ_CLIJAsmLH = 902, + SystemZ_CLIJAsmNE = 903, + SystemZ_CLIJAsmNH = 904, + SystemZ_CLIJAsmNHE = 905, + SystemZ_CLIJAsmNL = 906, + SystemZ_CLIJAsmNLE = 907, + SystemZ_CLIJAsmNLH = 908, + SystemZ_CLIY = 909, + SystemZ_CLM = 910, + SystemZ_CLMH = 911, + SystemZ_CLMY = 912, + SystemZ_CLR = 913, + SystemZ_CLRB = 914, + SystemZ_CLRBAsm = 915, + SystemZ_CLRBAsmE = 916, + SystemZ_CLRBAsmH = 917, + SystemZ_CLRBAsmHE = 918, + SystemZ_CLRBAsmL = 919, + SystemZ_CLRBAsmLE = 920, + SystemZ_CLRBAsmLH = 921, + SystemZ_CLRBAsmNE = 922, + SystemZ_CLRBAsmNH = 923, + SystemZ_CLRBAsmNHE = 924, + SystemZ_CLRBAsmNL = 925, + SystemZ_CLRBAsmNLE = 926, + SystemZ_CLRBAsmNLH = 927, + SystemZ_CLRJ = 928, + SystemZ_CLRJAsm = 929, + SystemZ_CLRJAsmE = 930, + SystemZ_CLRJAsmH = 931, + SystemZ_CLRJAsmHE = 932, + SystemZ_CLRJAsmL = 933, + SystemZ_CLRJAsmLE = 934, + SystemZ_CLRJAsmLH = 935, + SystemZ_CLRJAsmNE = 936, + SystemZ_CLRJAsmNH = 937, + SystemZ_CLRJAsmNHE = 938, + SystemZ_CLRJAsmNL = 939, + SystemZ_CLRJAsmNLE = 940, + SystemZ_CLRJAsmNLH = 941, + SystemZ_CLRL = 942, + SystemZ_CLRT = 943, + SystemZ_CLRTAsm = 944, + SystemZ_CLRTAsmE = 945, + SystemZ_CLRTAsmH = 946, + SystemZ_CLRTAsmHE = 947, + SystemZ_CLRTAsmL = 948, + SystemZ_CLRTAsmLE = 949, + SystemZ_CLRTAsmLH = 950, + SystemZ_CLRTAsmNE = 951, + SystemZ_CLRTAsmNH = 952, + SystemZ_CLRTAsmNHE = 953, + SystemZ_CLRTAsmNL = 954, + SystemZ_CLRTAsmNLE = 955, + SystemZ_CLRTAsmNLH = 956, + SystemZ_CLST = 957, + SystemZ_CLT = 958, + SystemZ_CLTAsm = 959, + SystemZ_CLTAsmE = 960, + SystemZ_CLTAsmH = 961, + SystemZ_CLTAsmHE = 962, + SystemZ_CLTAsmL = 963, + SystemZ_CLTAsmLE = 964, + SystemZ_CLTAsmLH = 965, + SystemZ_CLTAsmNE = 966, + SystemZ_CLTAsmNH = 967, + SystemZ_CLTAsmNHE = 968, + SystemZ_CLTAsmNL = 969, + SystemZ_CLTAsmNLE = 970, + SystemZ_CLTAsmNLH = 971, + SystemZ_CLY = 972, + SystemZ_CMPSC = 973, + SystemZ_CP = 974, + SystemZ_CPDT = 975, + SystemZ_CPSDRdd = 976, + SystemZ_CPSDRds = 977, + SystemZ_CPSDRsd = 978, + SystemZ_CPSDRss = 979, + SystemZ_CPXT = 980, + SystemZ_CPYA = 981, + SystemZ_CR = 982, + SystemZ_CRB = 983, + SystemZ_CRBAsm = 984, + SystemZ_CRBAsmE = 985, + SystemZ_CRBAsmH = 986, + SystemZ_CRBAsmHE = 987, + SystemZ_CRBAsmL = 988, + SystemZ_CRBAsmLE = 989, + SystemZ_CRBAsmLH = 990, + SystemZ_CRBAsmNE = 991, + SystemZ_CRBAsmNH = 992, + SystemZ_CRBAsmNHE = 993, + SystemZ_CRBAsmNL = 994, + SystemZ_CRBAsmNLE = 995, + SystemZ_CRBAsmNLH = 996, + SystemZ_CRDTE = 997, + SystemZ_CRDTEOpt = 998, + SystemZ_CRJ = 999, + SystemZ_CRJAsm = 1000, + SystemZ_CRJAsmE = 1001, + SystemZ_CRJAsmH = 1002, + SystemZ_CRJAsmHE = 1003, + SystemZ_CRJAsmL = 1004, + SystemZ_CRJAsmLE = 1005, + SystemZ_CRJAsmLH = 1006, + SystemZ_CRJAsmNE = 1007, + SystemZ_CRJAsmNH = 1008, + SystemZ_CRJAsmNHE = 1009, + SystemZ_CRJAsmNL = 1010, + SystemZ_CRJAsmNLE = 1011, + SystemZ_CRJAsmNLH = 1012, + SystemZ_CRL = 1013, + SystemZ_CRT = 1014, + SystemZ_CRTAsm = 1015, + SystemZ_CRTAsmE = 1016, + SystemZ_CRTAsmH = 1017, + SystemZ_CRTAsmHE = 1018, + SystemZ_CRTAsmL = 1019, + SystemZ_CRTAsmLE = 1020, + SystemZ_CRTAsmLH = 1021, + SystemZ_CRTAsmNE = 1022, + SystemZ_CRTAsmNH = 1023, + SystemZ_CRTAsmNHE = 1024, + SystemZ_CRTAsmNL = 1025, + SystemZ_CRTAsmNLE = 1026, + SystemZ_CRTAsmNLH = 1027, + SystemZ_CS = 1028, + SystemZ_CSCH = 1029, + SystemZ_CSDTR = 1030, + SystemZ_CSG = 1031, + SystemZ_CSP = 1032, + SystemZ_CSPG = 1033, + SystemZ_CSST = 1034, + SystemZ_CSXTR = 1035, + SystemZ_CSY = 1036, + SystemZ_CU12 = 1037, + SystemZ_CU12Opt = 1038, + SystemZ_CU14 = 1039, + SystemZ_CU14Opt = 1040, + SystemZ_CU21 = 1041, + SystemZ_CU21Opt = 1042, + SystemZ_CU24 = 1043, + SystemZ_CU24Opt = 1044, + SystemZ_CU41 = 1045, + SystemZ_CU42 = 1046, + SystemZ_CUDTR = 1047, + SystemZ_CUSE = 1048, + SystemZ_CUTFU = 1049, + SystemZ_CUTFUOpt = 1050, + SystemZ_CUUTF = 1051, + SystemZ_CUUTFOpt = 1052, + SystemZ_CUXTR = 1053, + SystemZ_CVB = 1054, + SystemZ_CVBG = 1055, + SystemZ_CVBY = 1056, + SystemZ_CVD = 1057, + SystemZ_CVDG = 1058, + SystemZ_CVDY = 1059, + SystemZ_CXBR = 1060, + SystemZ_CXFBR = 1061, + SystemZ_CXFBRA = 1062, + SystemZ_CXFR = 1063, + SystemZ_CXFTR = 1064, + SystemZ_CXGBR = 1065, + SystemZ_CXGBRA = 1066, + SystemZ_CXGR = 1067, + SystemZ_CXGTR = 1068, + SystemZ_CXGTRA = 1069, + SystemZ_CXLFBR = 1070, + SystemZ_CXLFTR = 1071, + SystemZ_CXLGBR = 1072, + SystemZ_CXLGTR = 1073, + SystemZ_CXPT = 1074, + SystemZ_CXR = 1075, + SystemZ_CXSTR = 1076, + SystemZ_CXTR = 1077, + SystemZ_CXUTR = 1078, + SystemZ_CXZT = 1079, + SystemZ_CY = 1080, + SystemZ_CZDT = 1081, + SystemZ_CZXT = 1082, + SystemZ_D = 1083, + SystemZ_DD = 1084, + SystemZ_DDB = 1085, + SystemZ_DDBR = 1086, + SystemZ_DDR = 1087, + SystemZ_DDTR = 1088, + SystemZ_DDTRA = 1089, + SystemZ_DE = 1090, + SystemZ_DEB = 1091, + SystemZ_DEBR = 1092, + SystemZ_DER = 1093, + SystemZ_DIAG = 1094, + SystemZ_DIDBR = 1095, + SystemZ_DIEBR = 1096, + SystemZ_DL = 1097, + SystemZ_DLG = 1098, + SystemZ_DLGR = 1099, + SystemZ_DLR = 1100, + SystemZ_DP = 1101, + SystemZ_DR = 1102, + SystemZ_DSG = 1103, + SystemZ_DSGF = 1104, + SystemZ_DSGFR = 1105, + SystemZ_DSGR = 1106, + SystemZ_DXBR = 1107, + SystemZ_DXR = 1108, + SystemZ_DXTR = 1109, + SystemZ_DXTRA = 1110, + SystemZ_EAR = 1111, + SystemZ_ECAG = 1112, + SystemZ_ECCTR = 1113, + SystemZ_ECPGA = 1114, + SystemZ_ECTG = 1115, + SystemZ_ED = 1116, + SystemZ_EDMK = 1117, + SystemZ_EEDTR = 1118, + SystemZ_EEXTR = 1119, + SystemZ_EFPC = 1120, + SystemZ_EPAIR = 1121, + SystemZ_EPAR = 1122, + SystemZ_EPCTR = 1123, + SystemZ_EPSW = 1124, + SystemZ_EREG = 1125, + SystemZ_EREGG = 1126, + SystemZ_ESAIR = 1127, + SystemZ_ESAR = 1128, + SystemZ_ESDTR = 1129, + SystemZ_ESEA = 1130, + SystemZ_ESTA = 1131, + SystemZ_ESXTR = 1132, + SystemZ_ETND = 1133, + SystemZ_EX = 1134, + SystemZ_EXRL = 1135, + SystemZ_FIDBR = 1136, + SystemZ_FIDBRA = 1137, + SystemZ_FIDR = 1138, + SystemZ_FIDTR = 1139, + SystemZ_FIEBR = 1140, + SystemZ_FIEBRA = 1141, + SystemZ_FIER = 1142, + SystemZ_FIXBR = 1143, + SystemZ_FIXBRA = 1144, + SystemZ_FIXR = 1145, + SystemZ_FIXTR = 1146, + SystemZ_FLOGR = 1147, + SystemZ_HDR = 1148, + SystemZ_HER = 1149, + SystemZ_HSCH = 1150, + SystemZ_IAC = 1151, + SystemZ_IC = 1152, + SystemZ_IC32 = 1153, + SystemZ_IC32Y = 1154, + SystemZ_ICM = 1155, + SystemZ_ICMH = 1156, + SystemZ_ICMY = 1157, + SystemZ_ICY = 1158, + SystemZ_IDTE = 1159, + SystemZ_IDTEOpt = 1160, + SystemZ_IEDTR = 1161, + SystemZ_IEXTR = 1162, + SystemZ_IIHF = 1163, + SystemZ_IIHH = 1164, + SystemZ_IIHL = 1165, + SystemZ_IILF = 1166, + SystemZ_IILH = 1167, + SystemZ_IILL = 1168, + SystemZ_IPK = 1169, + SystemZ_IPM = 1170, + SystemZ_IPTE = 1171, + SystemZ_IPTEOpt = 1172, + SystemZ_IPTEOptOpt = 1173, + SystemZ_IRBM = 1174, + SystemZ_ISKE = 1175, + SystemZ_IVSK = 1176, + SystemZ_InsnE = 1177, + SystemZ_InsnRI = 1178, + SystemZ_InsnRIE = 1179, + SystemZ_InsnRIL = 1180, + SystemZ_InsnRILU = 1181, + SystemZ_InsnRIS = 1182, + SystemZ_InsnRR = 1183, + SystemZ_InsnRRE = 1184, + SystemZ_InsnRRF = 1185, + SystemZ_InsnRRS = 1186, + SystemZ_InsnRS = 1187, + SystemZ_InsnRSE = 1188, + SystemZ_InsnRSI = 1189, + SystemZ_InsnRSY = 1190, + SystemZ_InsnRX = 1191, + SystemZ_InsnRXE = 1192, + SystemZ_InsnRXF = 1193, + SystemZ_InsnRXY = 1194, + SystemZ_InsnS = 1195, + SystemZ_InsnSI = 1196, + SystemZ_InsnSIL = 1197, + SystemZ_InsnSIY = 1198, + SystemZ_InsnSS = 1199, + SystemZ_InsnSSE = 1200, + SystemZ_InsnSSF = 1201, + SystemZ_J = 1202, + SystemZ_JAsmE = 1203, + SystemZ_JAsmH = 1204, + SystemZ_JAsmHE = 1205, + SystemZ_JAsmL = 1206, + SystemZ_JAsmLE = 1207, + SystemZ_JAsmLH = 1208, + SystemZ_JAsmM = 1209, + SystemZ_JAsmNE = 1210, + SystemZ_JAsmNH = 1211, + SystemZ_JAsmNHE = 1212, + SystemZ_JAsmNL = 1213, + SystemZ_JAsmNLE = 1214, + SystemZ_JAsmNLH = 1215, + SystemZ_JAsmNM = 1216, + SystemZ_JAsmNO = 1217, + SystemZ_JAsmNP = 1218, + SystemZ_JAsmNZ = 1219, + SystemZ_JAsmO = 1220, + SystemZ_JAsmP = 1221, + SystemZ_JAsmZ = 1222, + SystemZ_JG = 1223, + SystemZ_JGAsmE = 1224, + SystemZ_JGAsmH = 1225, + SystemZ_JGAsmHE = 1226, + SystemZ_JGAsmL = 1227, + SystemZ_JGAsmLE = 1228, + SystemZ_JGAsmLH = 1229, + SystemZ_JGAsmM = 1230, + SystemZ_JGAsmNE = 1231, + SystemZ_JGAsmNH = 1232, + SystemZ_JGAsmNHE = 1233, + SystemZ_JGAsmNL = 1234, + SystemZ_JGAsmNLE = 1235, + SystemZ_JGAsmNLH = 1236, + SystemZ_JGAsmNM = 1237, + SystemZ_JGAsmNO = 1238, + SystemZ_JGAsmNP = 1239, + SystemZ_JGAsmNZ = 1240, + SystemZ_JGAsmO = 1241, + SystemZ_JGAsmP = 1242, + SystemZ_JGAsmZ = 1243, + SystemZ_KDB = 1244, + SystemZ_KDBR = 1245, + SystemZ_KDTR = 1246, + SystemZ_KEB = 1247, + SystemZ_KEBR = 1248, + SystemZ_KIMD = 1249, + SystemZ_KLMD = 1250, + SystemZ_KM = 1251, + SystemZ_KMA = 1252, + SystemZ_KMAC = 1253, + SystemZ_KMC = 1254, + SystemZ_KMCTR = 1255, + SystemZ_KMF = 1256, + SystemZ_KMO = 1257, + SystemZ_KXBR = 1258, + SystemZ_KXTR = 1259, + SystemZ_L = 1260, + SystemZ_LA = 1261, + SystemZ_LAA = 1262, + SystemZ_LAAG = 1263, + SystemZ_LAAL = 1264, + SystemZ_LAALG = 1265, + SystemZ_LAE = 1266, + SystemZ_LAEY = 1267, + SystemZ_LAM = 1268, + SystemZ_LAMY = 1269, + SystemZ_LAN = 1270, + SystemZ_LANG = 1271, + SystemZ_LAO = 1272, + SystemZ_LAOG = 1273, + SystemZ_LARL = 1274, + SystemZ_LASP = 1275, + SystemZ_LAT = 1276, + SystemZ_LAX = 1277, + SystemZ_LAXG = 1278, + SystemZ_LAY = 1279, + SystemZ_LB = 1280, + SystemZ_LBH = 1281, + SystemZ_LBR = 1282, + SystemZ_LCBB = 1283, + SystemZ_LCCTL = 1284, + SystemZ_LCDBR = 1285, + SystemZ_LCDFR = 1286, + SystemZ_LCDFR_32 = 1287, + SystemZ_LCDR = 1288, + SystemZ_LCEBR = 1289, + SystemZ_LCER = 1290, + SystemZ_LCGFR = 1291, + SystemZ_LCGR = 1292, + SystemZ_LCR = 1293, + SystemZ_LCTL = 1294, + SystemZ_LCTLG = 1295, + SystemZ_LCXBR = 1296, + SystemZ_LCXR = 1297, + SystemZ_LD = 1298, + SystemZ_LDE = 1299, + SystemZ_LDE32 = 1300, + SystemZ_LDEB = 1301, + SystemZ_LDEBR = 1302, + SystemZ_LDER = 1303, + SystemZ_LDETR = 1304, + SystemZ_LDGR = 1305, + SystemZ_LDR = 1306, + SystemZ_LDR32 = 1307, + SystemZ_LDXBR = 1308, + SystemZ_LDXBRA = 1309, + SystemZ_LDXR = 1310, + SystemZ_LDXTR = 1311, + SystemZ_LDY = 1312, + SystemZ_LE = 1313, + SystemZ_LEDBR = 1314, + SystemZ_LEDBRA = 1315, + SystemZ_LEDR = 1316, + SystemZ_LEDTR = 1317, + SystemZ_LER = 1318, + SystemZ_LEXBR = 1319, + SystemZ_LEXBRA = 1320, + SystemZ_LEXR = 1321, + SystemZ_LEY = 1322, + SystemZ_LFAS = 1323, + SystemZ_LFH = 1324, + SystemZ_LFHAT = 1325, + SystemZ_LFPC = 1326, + SystemZ_LG = 1327, + SystemZ_LGAT = 1328, + SystemZ_LGB = 1329, + SystemZ_LGBR = 1330, + SystemZ_LGDR = 1331, + SystemZ_LGF = 1332, + SystemZ_LGFI = 1333, + SystemZ_LGFR = 1334, + SystemZ_LGFRL = 1335, + SystemZ_LGG = 1336, + SystemZ_LGH = 1337, + SystemZ_LGHI = 1338, + SystemZ_LGHR = 1339, + SystemZ_LGHRL = 1340, + SystemZ_LGR = 1341, + SystemZ_LGRL = 1342, + SystemZ_LGSC = 1343, + SystemZ_LH = 1344, + SystemZ_LHH = 1345, + SystemZ_LHI = 1346, + SystemZ_LHR = 1347, + SystemZ_LHRL = 1348, + SystemZ_LHY = 1349, + SystemZ_LLC = 1350, + SystemZ_LLCH = 1351, + SystemZ_LLCR = 1352, + SystemZ_LLGC = 1353, + SystemZ_LLGCR = 1354, + SystemZ_LLGF = 1355, + SystemZ_LLGFAT = 1356, + SystemZ_LLGFR = 1357, + SystemZ_LLGFRL = 1358, + SystemZ_LLGFSG = 1359, + SystemZ_LLGH = 1360, + SystemZ_LLGHR = 1361, + SystemZ_LLGHRL = 1362, + SystemZ_LLGT = 1363, + SystemZ_LLGTAT = 1364, + SystemZ_LLGTR = 1365, + SystemZ_LLH = 1366, + SystemZ_LLHH = 1367, + SystemZ_LLHR = 1368, + SystemZ_LLHRL = 1369, + SystemZ_LLIHF = 1370, + SystemZ_LLIHH = 1371, + SystemZ_LLIHL = 1372, + SystemZ_LLILF = 1373, + SystemZ_LLILH = 1374, + SystemZ_LLILL = 1375, + SystemZ_LLZRGF = 1376, + SystemZ_LM = 1377, + SystemZ_LMD = 1378, + SystemZ_LMG = 1379, + SystemZ_LMH = 1380, + SystemZ_LMY = 1381, + SystemZ_LNDBR = 1382, + SystemZ_LNDFR = 1383, + SystemZ_LNDFR_32 = 1384, + SystemZ_LNDR = 1385, + SystemZ_LNEBR = 1386, + SystemZ_LNER = 1387, + SystemZ_LNGFR = 1388, + SystemZ_LNGR = 1389, + SystemZ_LNR = 1390, + SystemZ_LNXBR = 1391, + SystemZ_LNXR = 1392, + SystemZ_LOC = 1393, + SystemZ_LOCAsm = 1394, + SystemZ_LOCAsmE = 1395, + SystemZ_LOCAsmH = 1396, + SystemZ_LOCAsmHE = 1397, + SystemZ_LOCAsmL = 1398, + SystemZ_LOCAsmLE = 1399, + SystemZ_LOCAsmLH = 1400, + SystemZ_LOCAsmM = 1401, + SystemZ_LOCAsmNE = 1402, + SystemZ_LOCAsmNH = 1403, + SystemZ_LOCAsmNHE = 1404, + SystemZ_LOCAsmNL = 1405, + SystemZ_LOCAsmNLE = 1406, + SystemZ_LOCAsmNLH = 1407, + SystemZ_LOCAsmNM = 1408, + SystemZ_LOCAsmNO = 1409, + SystemZ_LOCAsmNP = 1410, + SystemZ_LOCAsmNZ = 1411, + SystemZ_LOCAsmO = 1412, + SystemZ_LOCAsmP = 1413, + SystemZ_LOCAsmZ = 1414, + SystemZ_LOCFH = 1415, + SystemZ_LOCFHAsm = 1416, + SystemZ_LOCFHAsmE = 1417, + SystemZ_LOCFHAsmH = 1418, + SystemZ_LOCFHAsmHE = 1419, + SystemZ_LOCFHAsmL = 1420, + SystemZ_LOCFHAsmLE = 1421, + SystemZ_LOCFHAsmLH = 1422, + SystemZ_LOCFHAsmM = 1423, + SystemZ_LOCFHAsmNE = 1424, + SystemZ_LOCFHAsmNH = 1425, + SystemZ_LOCFHAsmNHE = 1426, + SystemZ_LOCFHAsmNL = 1427, + SystemZ_LOCFHAsmNLE = 1428, + SystemZ_LOCFHAsmNLH = 1429, + SystemZ_LOCFHAsmNM = 1430, + SystemZ_LOCFHAsmNO = 1431, + SystemZ_LOCFHAsmNP = 1432, + SystemZ_LOCFHAsmNZ = 1433, + SystemZ_LOCFHAsmO = 1434, + SystemZ_LOCFHAsmP = 1435, + SystemZ_LOCFHAsmZ = 1436, + SystemZ_LOCFHR = 1437, + SystemZ_LOCFHRAsm = 1438, + SystemZ_LOCFHRAsmE = 1439, + SystemZ_LOCFHRAsmH = 1440, + SystemZ_LOCFHRAsmHE = 1441, + SystemZ_LOCFHRAsmL = 1442, + SystemZ_LOCFHRAsmLE = 1443, + SystemZ_LOCFHRAsmLH = 1444, + SystemZ_LOCFHRAsmM = 1445, + SystemZ_LOCFHRAsmNE = 1446, + SystemZ_LOCFHRAsmNH = 1447, + SystemZ_LOCFHRAsmNHE = 1448, + SystemZ_LOCFHRAsmNL = 1449, + SystemZ_LOCFHRAsmNLE = 1450, + SystemZ_LOCFHRAsmNLH = 1451, + SystemZ_LOCFHRAsmNM = 1452, + SystemZ_LOCFHRAsmNO = 1453, + SystemZ_LOCFHRAsmNP = 1454, + SystemZ_LOCFHRAsmNZ = 1455, + SystemZ_LOCFHRAsmO = 1456, + SystemZ_LOCFHRAsmP = 1457, + SystemZ_LOCFHRAsmZ = 1458, + SystemZ_LOCG = 1459, + SystemZ_LOCGAsm = 1460, + SystemZ_LOCGAsmE = 1461, + SystemZ_LOCGAsmH = 1462, + SystemZ_LOCGAsmHE = 1463, + SystemZ_LOCGAsmL = 1464, + SystemZ_LOCGAsmLE = 1465, + SystemZ_LOCGAsmLH = 1466, + SystemZ_LOCGAsmM = 1467, + SystemZ_LOCGAsmNE = 1468, + SystemZ_LOCGAsmNH = 1469, + SystemZ_LOCGAsmNHE = 1470, + SystemZ_LOCGAsmNL = 1471, + SystemZ_LOCGAsmNLE = 1472, + SystemZ_LOCGAsmNLH = 1473, + SystemZ_LOCGAsmNM = 1474, + SystemZ_LOCGAsmNO = 1475, + SystemZ_LOCGAsmNP = 1476, + SystemZ_LOCGAsmNZ = 1477, + SystemZ_LOCGAsmO = 1478, + SystemZ_LOCGAsmP = 1479, + SystemZ_LOCGAsmZ = 1480, + SystemZ_LOCGHI = 1481, + SystemZ_LOCGHIAsm = 1482, + SystemZ_LOCGHIAsmE = 1483, + SystemZ_LOCGHIAsmH = 1484, + SystemZ_LOCGHIAsmHE = 1485, + SystemZ_LOCGHIAsmL = 1486, + SystemZ_LOCGHIAsmLE = 1487, + SystemZ_LOCGHIAsmLH = 1488, + SystemZ_LOCGHIAsmM = 1489, + SystemZ_LOCGHIAsmNE = 1490, + SystemZ_LOCGHIAsmNH = 1491, + SystemZ_LOCGHIAsmNHE = 1492, + SystemZ_LOCGHIAsmNL = 1493, + SystemZ_LOCGHIAsmNLE = 1494, + SystemZ_LOCGHIAsmNLH = 1495, + SystemZ_LOCGHIAsmNM = 1496, + SystemZ_LOCGHIAsmNO = 1497, + SystemZ_LOCGHIAsmNP = 1498, + SystemZ_LOCGHIAsmNZ = 1499, + SystemZ_LOCGHIAsmO = 1500, + SystemZ_LOCGHIAsmP = 1501, + SystemZ_LOCGHIAsmZ = 1502, + SystemZ_LOCGR = 1503, + SystemZ_LOCGRAsm = 1504, + SystemZ_LOCGRAsmE = 1505, + SystemZ_LOCGRAsmH = 1506, + SystemZ_LOCGRAsmHE = 1507, + SystemZ_LOCGRAsmL = 1508, + SystemZ_LOCGRAsmLE = 1509, + SystemZ_LOCGRAsmLH = 1510, + SystemZ_LOCGRAsmM = 1511, + SystemZ_LOCGRAsmNE = 1512, + SystemZ_LOCGRAsmNH = 1513, + SystemZ_LOCGRAsmNHE = 1514, + SystemZ_LOCGRAsmNL = 1515, + SystemZ_LOCGRAsmNLE = 1516, + SystemZ_LOCGRAsmNLH = 1517, + SystemZ_LOCGRAsmNM = 1518, + SystemZ_LOCGRAsmNO = 1519, + SystemZ_LOCGRAsmNP = 1520, + SystemZ_LOCGRAsmNZ = 1521, + SystemZ_LOCGRAsmO = 1522, + SystemZ_LOCGRAsmP = 1523, + SystemZ_LOCGRAsmZ = 1524, + SystemZ_LOCHHI = 1525, + SystemZ_LOCHHIAsm = 1526, + SystemZ_LOCHHIAsmE = 1527, + SystemZ_LOCHHIAsmH = 1528, + SystemZ_LOCHHIAsmHE = 1529, + SystemZ_LOCHHIAsmL = 1530, + SystemZ_LOCHHIAsmLE = 1531, + SystemZ_LOCHHIAsmLH = 1532, + SystemZ_LOCHHIAsmM = 1533, + SystemZ_LOCHHIAsmNE = 1534, + SystemZ_LOCHHIAsmNH = 1535, + SystemZ_LOCHHIAsmNHE = 1536, + SystemZ_LOCHHIAsmNL = 1537, + SystemZ_LOCHHIAsmNLE = 1538, + SystemZ_LOCHHIAsmNLH = 1539, + SystemZ_LOCHHIAsmNM = 1540, + SystemZ_LOCHHIAsmNO = 1541, + SystemZ_LOCHHIAsmNP = 1542, + SystemZ_LOCHHIAsmNZ = 1543, + SystemZ_LOCHHIAsmO = 1544, + SystemZ_LOCHHIAsmP = 1545, + SystemZ_LOCHHIAsmZ = 1546, + SystemZ_LOCHI = 1547, + SystemZ_LOCHIAsm = 1548, + SystemZ_LOCHIAsmE = 1549, + SystemZ_LOCHIAsmH = 1550, + SystemZ_LOCHIAsmHE = 1551, + SystemZ_LOCHIAsmL = 1552, + SystemZ_LOCHIAsmLE = 1553, + SystemZ_LOCHIAsmLH = 1554, + SystemZ_LOCHIAsmM = 1555, + SystemZ_LOCHIAsmNE = 1556, + SystemZ_LOCHIAsmNH = 1557, + SystemZ_LOCHIAsmNHE = 1558, + SystemZ_LOCHIAsmNL = 1559, + SystemZ_LOCHIAsmNLE = 1560, + SystemZ_LOCHIAsmNLH = 1561, + SystemZ_LOCHIAsmNM = 1562, + SystemZ_LOCHIAsmNO = 1563, + SystemZ_LOCHIAsmNP = 1564, + SystemZ_LOCHIAsmNZ = 1565, + SystemZ_LOCHIAsmO = 1566, + SystemZ_LOCHIAsmP = 1567, + SystemZ_LOCHIAsmZ = 1568, + SystemZ_LOCR = 1569, + SystemZ_LOCRAsm = 1570, + SystemZ_LOCRAsmE = 1571, + SystemZ_LOCRAsmH = 1572, + SystemZ_LOCRAsmHE = 1573, + SystemZ_LOCRAsmL = 1574, + SystemZ_LOCRAsmLE = 1575, + SystemZ_LOCRAsmLH = 1576, + SystemZ_LOCRAsmM = 1577, + SystemZ_LOCRAsmNE = 1578, + SystemZ_LOCRAsmNH = 1579, + SystemZ_LOCRAsmNHE = 1580, + SystemZ_LOCRAsmNL = 1581, + SystemZ_LOCRAsmNLE = 1582, + SystemZ_LOCRAsmNLH = 1583, + SystemZ_LOCRAsmNM = 1584, + SystemZ_LOCRAsmNO = 1585, + SystemZ_LOCRAsmNP = 1586, + SystemZ_LOCRAsmNZ = 1587, + SystemZ_LOCRAsmO = 1588, + SystemZ_LOCRAsmP = 1589, + SystemZ_LOCRAsmZ = 1590, + SystemZ_LPCTL = 1591, + SystemZ_LPD = 1592, + SystemZ_LPDBR = 1593, + SystemZ_LPDFR = 1594, + SystemZ_LPDFR_32 = 1595, + SystemZ_LPDG = 1596, + SystemZ_LPDR = 1597, + SystemZ_LPEBR = 1598, + SystemZ_LPER = 1599, + SystemZ_LPGFR = 1600, + SystemZ_LPGR = 1601, + SystemZ_LPP = 1602, + SystemZ_LPQ = 1603, + SystemZ_LPR = 1604, + SystemZ_LPSW = 1605, + SystemZ_LPSWE = 1606, + SystemZ_LPTEA = 1607, + SystemZ_LPXBR = 1608, + SystemZ_LPXR = 1609, + SystemZ_LR = 1610, + SystemZ_LRA = 1611, + SystemZ_LRAG = 1612, + SystemZ_LRAY = 1613, + SystemZ_LRDR = 1614, + SystemZ_LRER = 1615, + SystemZ_LRL = 1616, + SystemZ_LRV = 1617, + SystemZ_LRVG = 1618, + SystemZ_LRVGR = 1619, + SystemZ_LRVH = 1620, + SystemZ_LRVR = 1621, + SystemZ_LSCTL = 1622, + SystemZ_LT = 1623, + SystemZ_LTDBR = 1624, + SystemZ_LTDBRCompare = 1625, + SystemZ_LTDR = 1626, + SystemZ_LTDTR = 1627, + SystemZ_LTEBR = 1628, + SystemZ_LTEBRCompare = 1629, + SystemZ_LTER = 1630, + SystemZ_LTG = 1631, + SystemZ_LTGF = 1632, + SystemZ_LTGFR = 1633, + SystemZ_LTGR = 1634, + SystemZ_LTR = 1635, + SystemZ_LTXBR = 1636, + SystemZ_LTXBRCompare = 1637, + SystemZ_LTXR = 1638, + SystemZ_LTXTR = 1639, + SystemZ_LURA = 1640, + SystemZ_LURAG = 1641, + SystemZ_LXD = 1642, + SystemZ_LXDB = 1643, + SystemZ_LXDBR = 1644, + SystemZ_LXDR = 1645, + SystemZ_LXDTR = 1646, + SystemZ_LXE = 1647, + SystemZ_LXEB = 1648, + SystemZ_LXEBR = 1649, + SystemZ_LXER = 1650, + SystemZ_LXR = 1651, + SystemZ_LY = 1652, + SystemZ_LZDR = 1653, + SystemZ_LZER = 1654, + SystemZ_LZRF = 1655, + SystemZ_LZRG = 1656, + SystemZ_LZXR = 1657, + SystemZ_M = 1658, + SystemZ_MAD = 1659, + SystemZ_MADB = 1660, + SystemZ_MADBR = 1661, + SystemZ_MADR = 1662, + SystemZ_MAE = 1663, + SystemZ_MAEB = 1664, + SystemZ_MAEBR = 1665, + SystemZ_MAER = 1666, + SystemZ_MAY = 1667, + SystemZ_MAYH = 1668, + SystemZ_MAYHR = 1669, + SystemZ_MAYL = 1670, + SystemZ_MAYLR = 1671, + SystemZ_MAYR = 1672, + SystemZ_MC = 1673, + SystemZ_MD = 1674, + SystemZ_MDB = 1675, + SystemZ_MDBR = 1676, + SystemZ_MDE = 1677, + SystemZ_MDEB = 1678, + SystemZ_MDEBR = 1679, + SystemZ_MDER = 1680, + SystemZ_MDR = 1681, + SystemZ_MDTR = 1682, + SystemZ_MDTRA = 1683, + SystemZ_ME = 1684, + SystemZ_MEE = 1685, + SystemZ_MEEB = 1686, + SystemZ_MEEBR = 1687, + SystemZ_MEER = 1688, + SystemZ_MER = 1689, + SystemZ_MFY = 1690, + SystemZ_MG = 1691, + SystemZ_MGH = 1692, + SystemZ_MGHI = 1693, + SystemZ_MGRK = 1694, + SystemZ_MH = 1695, + SystemZ_MHI = 1696, + SystemZ_MHY = 1697, + SystemZ_ML = 1698, + SystemZ_MLG = 1699, + SystemZ_MLGR = 1700, + SystemZ_MLR = 1701, + SystemZ_MP = 1702, + SystemZ_MR = 1703, + SystemZ_MS = 1704, + SystemZ_MSC = 1705, + SystemZ_MSCH = 1706, + SystemZ_MSD = 1707, + SystemZ_MSDB = 1708, + SystemZ_MSDBR = 1709, + SystemZ_MSDR = 1710, + SystemZ_MSE = 1711, + SystemZ_MSEB = 1712, + SystemZ_MSEBR = 1713, + SystemZ_MSER = 1714, + SystemZ_MSFI = 1715, + SystemZ_MSG = 1716, + SystemZ_MSGC = 1717, + SystemZ_MSGF = 1718, + SystemZ_MSGFI = 1719, + SystemZ_MSGFR = 1720, + SystemZ_MSGR = 1721, + SystemZ_MSGRKC = 1722, + SystemZ_MSR = 1723, + SystemZ_MSRKC = 1724, + SystemZ_MSTA = 1725, + SystemZ_MSY = 1726, + SystemZ_MVC = 1727, + SystemZ_MVCDK = 1728, + SystemZ_MVCIN = 1729, + SystemZ_MVCK = 1730, + SystemZ_MVCL = 1731, + SystemZ_MVCLE = 1732, + SystemZ_MVCLU = 1733, + SystemZ_MVCOS = 1734, + SystemZ_MVCP = 1735, + SystemZ_MVCS = 1736, + SystemZ_MVCSK = 1737, + SystemZ_MVGHI = 1738, + SystemZ_MVHHI = 1739, + SystemZ_MVHI = 1740, + SystemZ_MVI = 1741, + SystemZ_MVIY = 1742, + SystemZ_MVN = 1743, + SystemZ_MVO = 1744, + SystemZ_MVPG = 1745, + SystemZ_MVST = 1746, + SystemZ_MVZ = 1747, + SystemZ_MXBR = 1748, + SystemZ_MXD = 1749, + SystemZ_MXDB = 1750, + SystemZ_MXDBR = 1751, + SystemZ_MXDR = 1752, + SystemZ_MXR = 1753, + SystemZ_MXTR = 1754, + SystemZ_MXTRA = 1755, + SystemZ_MY = 1756, + SystemZ_MYH = 1757, + SystemZ_MYHR = 1758, + SystemZ_MYL = 1759, + SystemZ_MYLR = 1760, + SystemZ_MYR = 1761, + SystemZ_N = 1762, + SystemZ_NC = 1763, + SystemZ_NG = 1764, + SystemZ_NGR = 1765, + SystemZ_NGRK = 1766, + SystemZ_NI = 1767, + SystemZ_NIAI = 1768, + SystemZ_NIHF = 1769, + SystemZ_NIHH = 1770, + SystemZ_NIHL = 1771, + SystemZ_NILF = 1772, + SystemZ_NILH = 1773, + SystemZ_NILL = 1774, + SystemZ_NIY = 1775, + SystemZ_NR = 1776, + SystemZ_NRK = 1777, + SystemZ_NTSTG = 1778, + SystemZ_NY = 1779, + SystemZ_O = 1780, + SystemZ_OC = 1781, + SystemZ_OG = 1782, + SystemZ_OGR = 1783, + SystemZ_OGRK = 1784, + SystemZ_OI = 1785, + SystemZ_OIHF = 1786, + SystemZ_OIHH = 1787, + SystemZ_OIHL = 1788, + SystemZ_OILF = 1789, + SystemZ_OILH = 1790, + SystemZ_OILL = 1791, + SystemZ_OIY = 1792, + SystemZ_OR = 1793, + SystemZ_ORK = 1794, + SystemZ_OY = 1795, + SystemZ_PACK = 1796, + SystemZ_PALB = 1797, + SystemZ_PC = 1798, + SystemZ_PCC = 1799, + SystemZ_PCKMO = 1800, + SystemZ_PFD = 1801, + SystemZ_PFDRL = 1802, + SystemZ_PFMF = 1803, + SystemZ_PFPO = 1804, + SystemZ_PGIN = 1805, + SystemZ_PGOUT = 1806, + SystemZ_PKA = 1807, + SystemZ_PKU = 1808, + SystemZ_PLO = 1809, + SystemZ_POPCNT = 1810, + SystemZ_PPA = 1811, + SystemZ_PPNO = 1812, + SystemZ_PR = 1813, + SystemZ_PRNO = 1814, + SystemZ_PT = 1815, + SystemZ_PTF = 1816, + SystemZ_PTFF = 1817, + SystemZ_PTI = 1818, + SystemZ_PTLB = 1819, + SystemZ_QADTR = 1820, + SystemZ_QAXTR = 1821, + SystemZ_QCTRI = 1822, + SystemZ_QSI = 1823, + SystemZ_RCHP = 1824, + SystemZ_RISBG = 1825, + SystemZ_RISBG32 = 1826, + SystemZ_RISBGN = 1827, + SystemZ_RISBHG = 1828, + SystemZ_RISBLG = 1829, + SystemZ_RLL = 1830, + SystemZ_RLLG = 1831, + SystemZ_RNSBG = 1832, + SystemZ_ROSBG = 1833, + SystemZ_RP = 1834, + SystemZ_RRBE = 1835, + SystemZ_RRBM = 1836, + SystemZ_RRDTR = 1837, + SystemZ_RRXTR = 1838, + SystemZ_RSCH = 1839, + SystemZ_RXSBG = 1840, + SystemZ_S = 1841, + SystemZ_SAC = 1842, + SystemZ_SACF = 1843, + SystemZ_SAL = 1844, + SystemZ_SAM24 = 1845, + SystemZ_SAM31 = 1846, + SystemZ_SAM64 = 1847, + SystemZ_SAR = 1848, + SystemZ_SCCTR = 1849, + SystemZ_SCHM = 1850, + SystemZ_SCK = 1851, + SystemZ_SCKC = 1852, + SystemZ_SCKPF = 1853, + SystemZ_SD = 1854, + SystemZ_SDB = 1855, + SystemZ_SDBR = 1856, + SystemZ_SDR = 1857, + SystemZ_SDTR = 1858, + SystemZ_SDTRA = 1859, + SystemZ_SE = 1860, + SystemZ_SEB = 1861, + SystemZ_SEBR = 1862, + SystemZ_SER = 1863, + SystemZ_SFASR = 1864, + SystemZ_SFPC = 1865, + SystemZ_SG = 1866, + SystemZ_SGF = 1867, + SystemZ_SGFR = 1868, + SystemZ_SGH = 1869, + SystemZ_SGR = 1870, + SystemZ_SGRK = 1871, + SystemZ_SH = 1872, + SystemZ_SHHHR = 1873, + SystemZ_SHHLR = 1874, + SystemZ_SHY = 1875, + SystemZ_SIE = 1876, + SystemZ_SIGA = 1877, + SystemZ_SIGP = 1878, + SystemZ_SL = 1879, + SystemZ_SLA = 1880, + SystemZ_SLAG = 1881, + SystemZ_SLAK = 1882, + SystemZ_SLB = 1883, + SystemZ_SLBG = 1884, + SystemZ_SLBGR = 1885, + SystemZ_SLBR = 1886, + SystemZ_SLDA = 1887, + SystemZ_SLDL = 1888, + SystemZ_SLDT = 1889, + SystemZ_SLFI = 1890, + SystemZ_SLG = 1891, + SystemZ_SLGF = 1892, + SystemZ_SLGFI = 1893, + SystemZ_SLGFR = 1894, + SystemZ_SLGR = 1895, + SystemZ_SLGRK = 1896, + SystemZ_SLHHHR = 1897, + SystemZ_SLHHLR = 1898, + SystemZ_SLL = 1899, + SystemZ_SLLG = 1900, + SystemZ_SLLK = 1901, + SystemZ_SLR = 1902, + SystemZ_SLRK = 1903, + SystemZ_SLXT = 1904, + SystemZ_SLY = 1905, + SystemZ_SP = 1906, + SystemZ_SPCTR = 1907, + SystemZ_SPKA = 1908, + SystemZ_SPM = 1909, + SystemZ_SPT = 1910, + SystemZ_SPX = 1911, + SystemZ_SQD = 1912, + SystemZ_SQDB = 1913, + SystemZ_SQDBR = 1914, + SystemZ_SQDR = 1915, + SystemZ_SQE = 1916, + SystemZ_SQEB = 1917, + SystemZ_SQEBR = 1918, + SystemZ_SQER = 1919, + SystemZ_SQXBR = 1920, + SystemZ_SQXR = 1921, + SystemZ_SR = 1922, + SystemZ_SRA = 1923, + SystemZ_SRAG = 1924, + SystemZ_SRAK = 1925, + SystemZ_SRDA = 1926, + SystemZ_SRDL = 1927, + SystemZ_SRDT = 1928, + SystemZ_SRK = 1929, + SystemZ_SRL = 1930, + SystemZ_SRLG = 1931, + SystemZ_SRLK = 1932, + SystemZ_SRNM = 1933, + SystemZ_SRNMB = 1934, + SystemZ_SRNMT = 1935, + SystemZ_SRP = 1936, + SystemZ_SRST = 1937, + SystemZ_SRSTU = 1938, + SystemZ_SRXT = 1939, + SystemZ_SSAIR = 1940, + SystemZ_SSAR = 1941, + SystemZ_SSCH = 1942, + SystemZ_SSKE = 1943, + SystemZ_SSKEOpt = 1944, + SystemZ_SSM = 1945, + SystemZ_ST = 1946, + SystemZ_STAM = 1947, + SystemZ_STAMY = 1948, + SystemZ_STAP = 1949, + SystemZ_STC = 1950, + SystemZ_STCH = 1951, + SystemZ_STCK = 1952, + SystemZ_STCKC = 1953, + SystemZ_STCKE = 1954, + SystemZ_STCKF = 1955, + SystemZ_STCM = 1956, + SystemZ_STCMH = 1957, + SystemZ_STCMY = 1958, + SystemZ_STCPS = 1959, + SystemZ_STCRW = 1960, + SystemZ_STCTG = 1961, + SystemZ_STCTL = 1962, + SystemZ_STCY = 1963, + SystemZ_STD = 1964, + SystemZ_STDY = 1965, + SystemZ_STE = 1966, + SystemZ_STEY = 1967, + SystemZ_STFH = 1968, + SystemZ_STFL = 1969, + SystemZ_STFLE = 1970, + SystemZ_STFPC = 1971, + SystemZ_STG = 1972, + SystemZ_STGRL = 1973, + SystemZ_STGSC = 1974, + SystemZ_STH = 1975, + SystemZ_STHH = 1976, + SystemZ_STHRL = 1977, + SystemZ_STHY = 1978, + SystemZ_STIDP = 1979, + SystemZ_STM = 1980, + SystemZ_STMG = 1981, + SystemZ_STMH = 1982, + SystemZ_STMY = 1983, + SystemZ_STNSM = 1984, + SystemZ_STOC = 1985, + SystemZ_STOCAsm = 1986, + SystemZ_STOCAsmE = 1987, + SystemZ_STOCAsmH = 1988, + SystemZ_STOCAsmHE = 1989, + SystemZ_STOCAsmL = 1990, + SystemZ_STOCAsmLE = 1991, + SystemZ_STOCAsmLH = 1992, + SystemZ_STOCAsmM = 1993, + SystemZ_STOCAsmNE = 1994, + SystemZ_STOCAsmNH = 1995, + SystemZ_STOCAsmNHE = 1996, + SystemZ_STOCAsmNL = 1997, + SystemZ_STOCAsmNLE = 1998, + SystemZ_STOCAsmNLH = 1999, + SystemZ_STOCAsmNM = 2000, + SystemZ_STOCAsmNO = 2001, + SystemZ_STOCAsmNP = 2002, + SystemZ_STOCAsmNZ = 2003, + SystemZ_STOCAsmO = 2004, + SystemZ_STOCAsmP = 2005, + SystemZ_STOCAsmZ = 2006, + SystemZ_STOCFH = 2007, + SystemZ_STOCFHAsm = 2008, + SystemZ_STOCFHAsmE = 2009, + SystemZ_STOCFHAsmH = 2010, + SystemZ_STOCFHAsmHE = 2011, + SystemZ_STOCFHAsmL = 2012, + SystemZ_STOCFHAsmLE = 2013, + SystemZ_STOCFHAsmLH = 2014, + SystemZ_STOCFHAsmM = 2015, + SystemZ_STOCFHAsmNE = 2016, + SystemZ_STOCFHAsmNH = 2017, + SystemZ_STOCFHAsmNHE = 2018, + SystemZ_STOCFHAsmNL = 2019, + SystemZ_STOCFHAsmNLE = 2020, + SystemZ_STOCFHAsmNLH = 2021, + SystemZ_STOCFHAsmNM = 2022, + SystemZ_STOCFHAsmNO = 2023, + SystemZ_STOCFHAsmNP = 2024, + SystemZ_STOCFHAsmNZ = 2025, + SystemZ_STOCFHAsmO = 2026, + SystemZ_STOCFHAsmP = 2027, + SystemZ_STOCFHAsmZ = 2028, + SystemZ_STOCG = 2029, + SystemZ_STOCGAsm = 2030, + SystemZ_STOCGAsmE = 2031, + SystemZ_STOCGAsmH = 2032, + SystemZ_STOCGAsmHE = 2033, + SystemZ_STOCGAsmL = 2034, + SystemZ_STOCGAsmLE = 2035, + SystemZ_STOCGAsmLH = 2036, + SystemZ_STOCGAsmM = 2037, + SystemZ_STOCGAsmNE = 2038, + SystemZ_STOCGAsmNH = 2039, + SystemZ_STOCGAsmNHE = 2040, + SystemZ_STOCGAsmNL = 2041, + SystemZ_STOCGAsmNLE = 2042, + SystemZ_STOCGAsmNLH = 2043, + SystemZ_STOCGAsmNM = 2044, + SystemZ_STOCGAsmNO = 2045, + SystemZ_STOCGAsmNP = 2046, + SystemZ_STOCGAsmNZ = 2047, + SystemZ_STOCGAsmO = 2048, + SystemZ_STOCGAsmP = 2049, + SystemZ_STOCGAsmZ = 2050, + SystemZ_STOSM = 2051, + SystemZ_STPQ = 2052, + SystemZ_STPT = 2053, + SystemZ_STPX = 2054, + SystemZ_STRAG = 2055, + SystemZ_STRL = 2056, + SystemZ_STRV = 2057, + SystemZ_STRVG = 2058, + SystemZ_STRVH = 2059, + SystemZ_STSCH = 2060, + SystemZ_STSI = 2061, + SystemZ_STURA = 2062, + SystemZ_STURG = 2063, + SystemZ_STY = 2064, + SystemZ_SU = 2065, + SystemZ_SUR = 2066, + SystemZ_SVC = 2067, + SystemZ_SW = 2068, + SystemZ_SWR = 2069, + SystemZ_SXBR = 2070, + SystemZ_SXR = 2071, + SystemZ_SXTR = 2072, + SystemZ_SXTRA = 2073, + SystemZ_SY = 2074, + SystemZ_TABORT = 2075, + SystemZ_TAM = 2076, + SystemZ_TAR = 2077, + SystemZ_TB = 2078, + SystemZ_TBDR = 2079, + SystemZ_TBEDR = 2080, + SystemZ_TBEGIN = 2081, + SystemZ_TBEGINC = 2082, + SystemZ_TCDB = 2083, + SystemZ_TCEB = 2084, + SystemZ_TCXB = 2085, + SystemZ_TDCDT = 2086, + SystemZ_TDCET = 2087, + SystemZ_TDCXT = 2088, + SystemZ_TDGDT = 2089, + SystemZ_TDGET = 2090, + SystemZ_TDGXT = 2091, + SystemZ_TEND = 2092, + SystemZ_THDER = 2093, + SystemZ_THDR = 2094, + SystemZ_TM = 2095, + SystemZ_TMHH = 2096, + SystemZ_TMHL = 2097, + SystemZ_TMLH = 2098, + SystemZ_TMLL = 2099, + SystemZ_TMY = 2100, + SystemZ_TP = 2101, + SystemZ_TPI = 2102, + SystemZ_TPROT = 2103, + SystemZ_TR = 2104, + SystemZ_TRACE = 2105, + SystemZ_TRACG = 2106, + SystemZ_TRAP2 = 2107, + SystemZ_TRAP4 = 2108, + SystemZ_TRE = 2109, + SystemZ_TROO = 2110, + SystemZ_TROOOpt = 2111, + SystemZ_TROT = 2112, + SystemZ_TROTOpt = 2113, + SystemZ_TRT = 2114, + SystemZ_TRTE = 2115, + SystemZ_TRTEOpt = 2116, + SystemZ_TRTO = 2117, + SystemZ_TRTOOpt = 2118, + SystemZ_TRTR = 2119, + SystemZ_TRTRE = 2120, + SystemZ_TRTREOpt = 2121, + SystemZ_TRTT = 2122, + SystemZ_TRTTOpt = 2123, + SystemZ_TS = 2124, + SystemZ_TSCH = 2125, + SystemZ_UNPK = 2126, + SystemZ_UNPKA = 2127, + SystemZ_UNPKU = 2128, + SystemZ_UPT = 2129, + SystemZ_VA = 2130, + SystemZ_VAB = 2131, + SystemZ_VAC = 2132, + SystemZ_VACC = 2133, + SystemZ_VACCB = 2134, + SystemZ_VACCC = 2135, + SystemZ_VACCCQ = 2136, + SystemZ_VACCF = 2137, + SystemZ_VACCG = 2138, + SystemZ_VACCH = 2139, + SystemZ_VACCQ = 2140, + SystemZ_VACQ = 2141, + SystemZ_VAF = 2142, + SystemZ_VAG = 2143, + SystemZ_VAH = 2144, + SystemZ_VAP = 2145, + SystemZ_VAQ = 2146, + SystemZ_VAVG = 2147, + SystemZ_VAVGB = 2148, + SystemZ_VAVGF = 2149, + SystemZ_VAVGG = 2150, + SystemZ_VAVGH = 2151, + SystemZ_VAVGL = 2152, + SystemZ_VAVGLB = 2153, + SystemZ_VAVGLF = 2154, + SystemZ_VAVGLG = 2155, + SystemZ_VAVGLH = 2156, + SystemZ_VBPERM = 2157, + SystemZ_VCDG = 2158, + SystemZ_VCDGB = 2159, + SystemZ_VCDLG = 2160, + SystemZ_VCDLGB = 2161, + SystemZ_VCEQ = 2162, + SystemZ_VCEQB = 2163, + SystemZ_VCEQBS = 2164, + SystemZ_VCEQF = 2165, + SystemZ_VCEQFS = 2166, + SystemZ_VCEQG = 2167, + SystemZ_VCEQGS = 2168, + SystemZ_VCEQH = 2169, + SystemZ_VCEQHS = 2170, + SystemZ_VCGD = 2171, + SystemZ_VCGDB = 2172, + SystemZ_VCH = 2173, + SystemZ_VCHB = 2174, + SystemZ_VCHBS = 2175, + SystemZ_VCHF = 2176, + SystemZ_VCHFS = 2177, + SystemZ_VCHG = 2178, + SystemZ_VCHGS = 2179, + SystemZ_VCHH = 2180, + SystemZ_VCHHS = 2181, + SystemZ_VCHL = 2182, + SystemZ_VCHLB = 2183, + SystemZ_VCHLBS = 2184, + SystemZ_VCHLF = 2185, + SystemZ_VCHLFS = 2186, + SystemZ_VCHLG = 2187, + SystemZ_VCHLGS = 2188, + SystemZ_VCHLH = 2189, + SystemZ_VCHLHS = 2190, + SystemZ_VCKSM = 2191, + SystemZ_VCLGD = 2192, + SystemZ_VCLGDB = 2193, + SystemZ_VCLZ = 2194, + SystemZ_VCLZB = 2195, + SystemZ_VCLZF = 2196, + SystemZ_VCLZG = 2197, + SystemZ_VCLZH = 2198, + SystemZ_VCP = 2199, + SystemZ_VCTZ = 2200, + SystemZ_VCTZB = 2201, + SystemZ_VCTZF = 2202, + SystemZ_VCTZG = 2203, + SystemZ_VCTZH = 2204, + SystemZ_VCVB = 2205, + SystemZ_VCVBG = 2206, + SystemZ_VCVD = 2207, + SystemZ_VCVDG = 2208, + SystemZ_VDP = 2209, + SystemZ_VEC = 2210, + SystemZ_VECB = 2211, + SystemZ_VECF = 2212, + SystemZ_VECG = 2213, + SystemZ_VECH = 2214, + SystemZ_VECL = 2215, + SystemZ_VECLB = 2216, + SystemZ_VECLF = 2217, + SystemZ_VECLG = 2218, + SystemZ_VECLH = 2219, + SystemZ_VERIM = 2220, + SystemZ_VERIMB = 2221, + SystemZ_VERIMF = 2222, + SystemZ_VERIMG = 2223, + SystemZ_VERIMH = 2224, + SystemZ_VERLL = 2225, + SystemZ_VERLLB = 2226, + SystemZ_VERLLF = 2227, + SystemZ_VERLLG = 2228, + SystemZ_VERLLH = 2229, + SystemZ_VERLLV = 2230, + SystemZ_VERLLVB = 2231, + SystemZ_VERLLVF = 2232, + SystemZ_VERLLVG = 2233, + SystemZ_VERLLVH = 2234, + SystemZ_VESL = 2235, + SystemZ_VESLB = 2236, + SystemZ_VESLF = 2237, + SystemZ_VESLG = 2238, + SystemZ_VESLH = 2239, + SystemZ_VESLV = 2240, + SystemZ_VESLVB = 2241, + SystemZ_VESLVF = 2242, + SystemZ_VESLVG = 2243, + SystemZ_VESLVH = 2244, + SystemZ_VESRA = 2245, + SystemZ_VESRAB = 2246, + SystemZ_VESRAF = 2247, + SystemZ_VESRAG = 2248, + SystemZ_VESRAH = 2249, + SystemZ_VESRAV = 2250, + SystemZ_VESRAVB = 2251, + SystemZ_VESRAVF = 2252, + SystemZ_VESRAVG = 2253, + SystemZ_VESRAVH = 2254, + SystemZ_VESRL = 2255, + SystemZ_VESRLB = 2256, + SystemZ_VESRLF = 2257, + SystemZ_VESRLG = 2258, + SystemZ_VESRLH = 2259, + SystemZ_VESRLV = 2260, + SystemZ_VESRLVB = 2261, + SystemZ_VESRLVF = 2262, + SystemZ_VESRLVG = 2263, + SystemZ_VESRLVH = 2264, + SystemZ_VFA = 2265, + SystemZ_VFADB = 2266, + SystemZ_VFAE = 2267, + SystemZ_VFAEB = 2268, + SystemZ_VFAEBS = 2269, + SystemZ_VFAEF = 2270, + SystemZ_VFAEFS = 2271, + SystemZ_VFAEH = 2272, + SystemZ_VFAEHS = 2273, + SystemZ_VFAEZB = 2274, + SystemZ_VFAEZBS = 2275, + SystemZ_VFAEZF = 2276, + SystemZ_VFAEZFS = 2277, + SystemZ_VFAEZH = 2278, + SystemZ_VFAEZHS = 2279, + SystemZ_VFASB = 2280, + SystemZ_VFCE = 2281, + SystemZ_VFCEDB = 2282, + SystemZ_VFCEDBS = 2283, + SystemZ_VFCESB = 2284, + SystemZ_VFCESBS = 2285, + SystemZ_VFCH = 2286, + SystemZ_VFCHDB = 2287, + SystemZ_VFCHDBS = 2288, + SystemZ_VFCHE = 2289, + SystemZ_VFCHEDB = 2290, + SystemZ_VFCHEDBS = 2291, + SystemZ_VFCHESB = 2292, + SystemZ_VFCHESBS = 2293, + SystemZ_VFCHSB = 2294, + SystemZ_VFCHSBS = 2295, + SystemZ_VFD = 2296, + SystemZ_VFDDB = 2297, + SystemZ_VFDSB = 2298, + SystemZ_VFEE = 2299, + SystemZ_VFEEB = 2300, + SystemZ_VFEEBS = 2301, + SystemZ_VFEEF = 2302, + SystemZ_VFEEFS = 2303, + SystemZ_VFEEH = 2304, + SystemZ_VFEEHS = 2305, + SystemZ_VFEEZB = 2306, + SystemZ_VFEEZBS = 2307, + SystemZ_VFEEZF = 2308, + SystemZ_VFEEZFS = 2309, + SystemZ_VFEEZH = 2310, + SystemZ_VFEEZHS = 2311, + SystemZ_VFENE = 2312, + SystemZ_VFENEB = 2313, + SystemZ_VFENEBS = 2314, + SystemZ_VFENEF = 2315, + SystemZ_VFENEFS = 2316, + SystemZ_VFENEH = 2317, + SystemZ_VFENEHS = 2318, + SystemZ_VFENEZB = 2319, + SystemZ_VFENEZBS = 2320, + SystemZ_VFENEZF = 2321, + SystemZ_VFENEZFS = 2322, + SystemZ_VFENEZH = 2323, + SystemZ_VFENEZHS = 2324, + SystemZ_VFI = 2325, + SystemZ_VFIDB = 2326, + SystemZ_VFISB = 2327, + SystemZ_VFKEDB = 2328, + SystemZ_VFKEDBS = 2329, + SystemZ_VFKESB = 2330, + SystemZ_VFKESBS = 2331, + SystemZ_VFKHDB = 2332, + SystemZ_VFKHDBS = 2333, + SystemZ_VFKHEDB = 2334, + SystemZ_VFKHEDBS = 2335, + SystemZ_VFKHESB = 2336, + SystemZ_VFKHESBS = 2337, + SystemZ_VFKHSB = 2338, + SystemZ_VFKHSBS = 2339, + SystemZ_VFLCDB = 2340, + SystemZ_VFLCSB = 2341, + SystemZ_VFLL = 2342, + SystemZ_VFLLS = 2343, + SystemZ_VFLNDB = 2344, + SystemZ_VFLNSB = 2345, + SystemZ_VFLPDB = 2346, + SystemZ_VFLPSB = 2347, + SystemZ_VFLR = 2348, + SystemZ_VFLRD = 2349, + SystemZ_VFM = 2350, + SystemZ_VFMA = 2351, + SystemZ_VFMADB = 2352, + SystemZ_VFMASB = 2353, + SystemZ_VFMAX = 2354, + SystemZ_VFMAXDB = 2355, + SystemZ_VFMAXSB = 2356, + SystemZ_VFMDB = 2357, + SystemZ_VFMIN = 2358, + SystemZ_VFMINDB = 2359, + SystemZ_VFMINSB = 2360, + SystemZ_VFMS = 2361, + SystemZ_VFMSB = 2362, + SystemZ_VFMSDB = 2363, + SystemZ_VFMSSB = 2364, + SystemZ_VFNMA = 2365, + SystemZ_VFNMADB = 2366, + SystemZ_VFNMASB = 2367, + SystemZ_VFNMS = 2368, + SystemZ_VFNMSDB = 2369, + SystemZ_VFNMSSB = 2370, + SystemZ_VFPSO = 2371, + SystemZ_VFPSODB = 2372, + SystemZ_VFPSOSB = 2373, + SystemZ_VFS = 2374, + SystemZ_VFSDB = 2375, + SystemZ_VFSQ = 2376, + SystemZ_VFSQDB = 2377, + SystemZ_VFSQSB = 2378, + SystemZ_VFSSB = 2379, + SystemZ_VFTCI = 2380, + SystemZ_VFTCIDB = 2381, + SystemZ_VFTCISB = 2382, + SystemZ_VGBM = 2383, + SystemZ_VGEF = 2384, + SystemZ_VGEG = 2385, + SystemZ_VGFM = 2386, + SystemZ_VGFMA = 2387, + SystemZ_VGFMAB = 2388, + SystemZ_VGFMAF = 2389, + SystemZ_VGFMAG = 2390, + SystemZ_VGFMAH = 2391, + SystemZ_VGFMB = 2392, + SystemZ_VGFMF = 2393, + SystemZ_VGFMG = 2394, + SystemZ_VGFMH = 2395, + SystemZ_VGM = 2396, + SystemZ_VGMB = 2397, + SystemZ_VGMF = 2398, + SystemZ_VGMG = 2399, + SystemZ_VGMH = 2400, + SystemZ_VISTR = 2401, + SystemZ_VISTRB = 2402, + SystemZ_VISTRBS = 2403, + SystemZ_VISTRF = 2404, + SystemZ_VISTRFS = 2405, + SystemZ_VISTRH = 2406, + SystemZ_VISTRHS = 2407, + SystemZ_VL = 2408, + SystemZ_VLBB = 2409, + SystemZ_VLC = 2410, + SystemZ_VLCB = 2411, + SystemZ_VLCF = 2412, + SystemZ_VLCG = 2413, + SystemZ_VLCH = 2414, + SystemZ_VLDE = 2415, + SystemZ_VLDEB = 2416, + SystemZ_VLEB = 2417, + SystemZ_VLED = 2418, + SystemZ_VLEDB = 2419, + SystemZ_VLEF = 2420, + SystemZ_VLEG = 2421, + SystemZ_VLEH = 2422, + SystemZ_VLEIB = 2423, + SystemZ_VLEIF = 2424, + SystemZ_VLEIG = 2425, + SystemZ_VLEIH = 2426, + SystemZ_VLGV = 2427, + SystemZ_VLGVB = 2428, + SystemZ_VLGVF = 2429, + SystemZ_VLGVG = 2430, + SystemZ_VLGVH = 2431, + SystemZ_VLIP = 2432, + SystemZ_VLL = 2433, + SystemZ_VLLEZ = 2434, + SystemZ_VLLEZB = 2435, + SystemZ_VLLEZF = 2436, + SystemZ_VLLEZG = 2437, + SystemZ_VLLEZH = 2438, + SystemZ_VLLEZLF = 2439, + SystemZ_VLM = 2440, + SystemZ_VLP = 2441, + SystemZ_VLPB = 2442, + SystemZ_VLPF = 2443, + SystemZ_VLPG = 2444, + SystemZ_VLPH = 2445, + SystemZ_VLR = 2446, + SystemZ_VLREP = 2447, + SystemZ_VLREPB = 2448, + SystemZ_VLREPF = 2449, + SystemZ_VLREPG = 2450, + SystemZ_VLREPH = 2451, + SystemZ_VLRL = 2452, + SystemZ_VLRLR = 2453, + SystemZ_VLVG = 2454, + SystemZ_VLVGB = 2455, + SystemZ_VLVGF = 2456, + SystemZ_VLVGG = 2457, + SystemZ_VLVGH = 2458, + SystemZ_VLVGP = 2459, + SystemZ_VMAE = 2460, + SystemZ_VMAEB = 2461, + SystemZ_VMAEF = 2462, + SystemZ_VMAEH = 2463, + SystemZ_VMAH = 2464, + SystemZ_VMAHB = 2465, + SystemZ_VMAHF = 2466, + SystemZ_VMAHH = 2467, + SystemZ_VMAL = 2468, + SystemZ_VMALB = 2469, + SystemZ_VMALE = 2470, + SystemZ_VMALEB = 2471, + SystemZ_VMALEF = 2472, + SystemZ_VMALEH = 2473, + SystemZ_VMALF = 2474, + SystemZ_VMALH = 2475, + SystemZ_VMALHB = 2476, + SystemZ_VMALHF = 2477, + SystemZ_VMALHH = 2478, + SystemZ_VMALHW = 2479, + SystemZ_VMALO = 2480, + SystemZ_VMALOB = 2481, + SystemZ_VMALOF = 2482, + SystemZ_VMALOH = 2483, + SystemZ_VMAO = 2484, + SystemZ_VMAOB = 2485, + SystemZ_VMAOF = 2486, + SystemZ_VMAOH = 2487, + SystemZ_VME = 2488, + SystemZ_VMEB = 2489, + SystemZ_VMEF = 2490, + SystemZ_VMEH = 2491, + SystemZ_VMH = 2492, + SystemZ_VMHB = 2493, + SystemZ_VMHF = 2494, + SystemZ_VMHH = 2495, + SystemZ_VML = 2496, + SystemZ_VMLB = 2497, + SystemZ_VMLE = 2498, + SystemZ_VMLEB = 2499, + SystemZ_VMLEF = 2500, + SystemZ_VMLEH = 2501, + SystemZ_VMLF = 2502, + SystemZ_VMLH = 2503, + SystemZ_VMLHB = 2504, + SystemZ_VMLHF = 2505, + SystemZ_VMLHH = 2506, + SystemZ_VMLHW = 2507, + SystemZ_VMLO = 2508, + SystemZ_VMLOB = 2509, + SystemZ_VMLOF = 2510, + SystemZ_VMLOH = 2511, + SystemZ_VMN = 2512, + SystemZ_VMNB = 2513, + SystemZ_VMNF = 2514, + SystemZ_VMNG = 2515, + SystemZ_VMNH = 2516, + SystemZ_VMNL = 2517, + SystemZ_VMNLB = 2518, + SystemZ_VMNLF = 2519, + SystemZ_VMNLG = 2520, + SystemZ_VMNLH = 2521, + SystemZ_VMO = 2522, + SystemZ_VMOB = 2523, + SystemZ_VMOF = 2524, + SystemZ_VMOH = 2525, + SystemZ_VMP = 2526, + SystemZ_VMRH = 2527, + SystemZ_VMRHB = 2528, + SystemZ_VMRHF = 2529, + SystemZ_VMRHG = 2530, + SystemZ_VMRHH = 2531, + SystemZ_VMRL = 2532, + SystemZ_VMRLB = 2533, + SystemZ_VMRLF = 2534, + SystemZ_VMRLG = 2535, + SystemZ_VMRLH = 2536, + SystemZ_VMSL = 2537, + SystemZ_VMSLG = 2538, + SystemZ_VMSP = 2539, + SystemZ_VMX = 2540, + SystemZ_VMXB = 2541, + SystemZ_VMXF = 2542, + SystemZ_VMXG = 2543, + SystemZ_VMXH = 2544, + SystemZ_VMXL = 2545, + SystemZ_VMXLB = 2546, + SystemZ_VMXLF = 2547, + SystemZ_VMXLG = 2548, + SystemZ_VMXLH = 2549, + SystemZ_VN = 2550, + SystemZ_VNC = 2551, + SystemZ_VNN = 2552, + SystemZ_VNO = 2553, + SystemZ_VNX = 2554, + SystemZ_VO = 2555, + SystemZ_VOC = 2556, + SystemZ_VONE = 2557, + SystemZ_VPDI = 2558, + SystemZ_VPERM = 2559, + SystemZ_VPK = 2560, + SystemZ_VPKF = 2561, + SystemZ_VPKG = 2562, + SystemZ_VPKH = 2563, + SystemZ_VPKLS = 2564, + SystemZ_VPKLSF = 2565, + SystemZ_VPKLSFS = 2566, + SystemZ_VPKLSG = 2567, + SystemZ_VPKLSGS = 2568, + SystemZ_VPKLSH = 2569, + SystemZ_VPKLSHS = 2570, + SystemZ_VPKS = 2571, + SystemZ_VPKSF = 2572, + SystemZ_VPKSFS = 2573, + SystemZ_VPKSG = 2574, + SystemZ_VPKSGS = 2575, + SystemZ_VPKSH = 2576, + SystemZ_VPKSHS = 2577, + SystemZ_VPKZ = 2578, + SystemZ_VPOPCT = 2579, + SystemZ_VPOPCTB = 2580, + SystemZ_VPOPCTF = 2581, + SystemZ_VPOPCTG = 2582, + SystemZ_VPOPCTH = 2583, + SystemZ_VPSOP = 2584, + SystemZ_VREP = 2585, + SystemZ_VREPB = 2586, + SystemZ_VREPF = 2587, + SystemZ_VREPG = 2588, + SystemZ_VREPH = 2589, + SystemZ_VREPI = 2590, + SystemZ_VREPIB = 2591, + SystemZ_VREPIF = 2592, + SystemZ_VREPIG = 2593, + SystemZ_VREPIH = 2594, + SystemZ_VRP = 2595, + SystemZ_VS = 2596, + SystemZ_VSB = 2597, + SystemZ_VSBCBI = 2598, + SystemZ_VSBCBIQ = 2599, + SystemZ_VSBI = 2600, + SystemZ_VSBIQ = 2601, + SystemZ_VSCBI = 2602, + SystemZ_VSCBIB = 2603, + SystemZ_VSCBIF = 2604, + SystemZ_VSCBIG = 2605, + SystemZ_VSCBIH = 2606, + SystemZ_VSCBIQ = 2607, + SystemZ_VSCEF = 2608, + SystemZ_VSCEG = 2609, + SystemZ_VSDP = 2610, + SystemZ_VSEG = 2611, + SystemZ_VSEGB = 2612, + SystemZ_VSEGF = 2613, + SystemZ_VSEGH = 2614, + SystemZ_VSEL = 2615, + SystemZ_VSF = 2616, + SystemZ_VSG = 2617, + SystemZ_VSH = 2618, + SystemZ_VSL = 2619, + SystemZ_VSLB = 2620, + SystemZ_VSLDB = 2621, + SystemZ_VSP = 2622, + SystemZ_VSQ = 2623, + SystemZ_VSRA = 2624, + SystemZ_VSRAB = 2625, + SystemZ_VSRL = 2626, + SystemZ_VSRLB = 2627, + SystemZ_VSRP = 2628, + SystemZ_VST = 2629, + SystemZ_VSTEB = 2630, + SystemZ_VSTEF = 2631, + SystemZ_VSTEG = 2632, + SystemZ_VSTEH = 2633, + SystemZ_VSTL = 2634, + SystemZ_VSTM = 2635, + SystemZ_VSTRC = 2636, + SystemZ_VSTRCB = 2637, + SystemZ_VSTRCBS = 2638, + SystemZ_VSTRCF = 2639, + SystemZ_VSTRCFS = 2640, + SystemZ_VSTRCH = 2641, + SystemZ_VSTRCHS = 2642, + SystemZ_VSTRCZB = 2643, + SystemZ_VSTRCZBS = 2644, + SystemZ_VSTRCZF = 2645, + SystemZ_VSTRCZFS = 2646, + SystemZ_VSTRCZH = 2647, + SystemZ_VSTRCZHS = 2648, + SystemZ_VSTRL = 2649, + SystemZ_VSTRLR = 2650, + SystemZ_VSUM = 2651, + SystemZ_VSUMB = 2652, + SystemZ_VSUMG = 2653, + SystemZ_VSUMGF = 2654, + SystemZ_VSUMGH = 2655, + SystemZ_VSUMH = 2656, + SystemZ_VSUMQ = 2657, + SystemZ_VSUMQF = 2658, + SystemZ_VSUMQG = 2659, + SystemZ_VTM = 2660, + SystemZ_VTP = 2661, + SystemZ_VUPH = 2662, + SystemZ_VUPHB = 2663, + SystemZ_VUPHF = 2664, + SystemZ_VUPHH = 2665, + SystemZ_VUPKZ = 2666, + SystemZ_VUPL = 2667, + SystemZ_VUPLB = 2668, + SystemZ_VUPLF = 2669, + SystemZ_VUPLH = 2670, + SystemZ_VUPLHB = 2671, + SystemZ_VUPLHF = 2672, + SystemZ_VUPLHH = 2673, + SystemZ_VUPLHW = 2674, + SystemZ_VUPLL = 2675, + SystemZ_VUPLLB = 2676, + SystemZ_VUPLLF = 2677, + SystemZ_VUPLLH = 2678, + SystemZ_VX = 2679, + SystemZ_VZERO = 2680, + SystemZ_WCDGB = 2681, + SystemZ_WCDLGB = 2682, + SystemZ_WCGDB = 2683, + SystemZ_WCLGDB = 2684, + SystemZ_WFADB = 2685, + SystemZ_WFASB = 2686, + SystemZ_WFAXB = 2687, + SystemZ_WFC = 2688, + SystemZ_WFCDB = 2689, + SystemZ_WFCEDB = 2690, + SystemZ_WFCEDBS = 2691, + SystemZ_WFCESB = 2692, + SystemZ_WFCESBS = 2693, + SystemZ_WFCEXB = 2694, + SystemZ_WFCEXBS = 2695, + SystemZ_WFCHDB = 2696, + SystemZ_WFCHDBS = 2697, + SystemZ_WFCHEDB = 2698, + SystemZ_WFCHEDBS = 2699, + SystemZ_WFCHESB = 2700, + SystemZ_WFCHESBS = 2701, + SystemZ_WFCHEXB = 2702, + SystemZ_WFCHEXBS = 2703, + SystemZ_WFCHSB = 2704, + SystemZ_WFCHSBS = 2705, + SystemZ_WFCHXB = 2706, + SystemZ_WFCHXBS = 2707, + SystemZ_WFCSB = 2708, + SystemZ_WFCXB = 2709, + SystemZ_WFDDB = 2710, + SystemZ_WFDSB = 2711, + SystemZ_WFDXB = 2712, + SystemZ_WFIDB = 2713, + SystemZ_WFISB = 2714, + SystemZ_WFIXB = 2715, + SystemZ_WFK = 2716, + SystemZ_WFKDB = 2717, + SystemZ_WFKEDB = 2718, + SystemZ_WFKEDBS = 2719, + SystemZ_WFKESB = 2720, + SystemZ_WFKESBS = 2721, + SystemZ_WFKEXB = 2722, + SystemZ_WFKEXBS = 2723, + SystemZ_WFKHDB = 2724, + SystemZ_WFKHDBS = 2725, + SystemZ_WFKHEDB = 2726, + SystemZ_WFKHEDBS = 2727, + SystemZ_WFKHESB = 2728, + SystemZ_WFKHESBS = 2729, + SystemZ_WFKHEXB = 2730, + SystemZ_WFKHEXBS = 2731, + SystemZ_WFKHSB = 2732, + SystemZ_WFKHSBS = 2733, + SystemZ_WFKHXB = 2734, + SystemZ_WFKHXBS = 2735, + SystemZ_WFKSB = 2736, + SystemZ_WFKXB = 2737, + SystemZ_WFLCDB = 2738, + SystemZ_WFLCSB = 2739, + SystemZ_WFLCXB = 2740, + SystemZ_WFLLD = 2741, + SystemZ_WFLLS = 2742, + SystemZ_WFLNDB = 2743, + SystemZ_WFLNSB = 2744, + SystemZ_WFLNXB = 2745, + SystemZ_WFLPDB = 2746, + SystemZ_WFLPSB = 2747, + SystemZ_WFLPXB = 2748, + SystemZ_WFLRD = 2749, + SystemZ_WFLRX = 2750, + SystemZ_WFMADB = 2751, + SystemZ_WFMASB = 2752, + SystemZ_WFMAXB = 2753, + SystemZ_WFMAXDB = 2754, + SystemZ_WFMAXSB = 2755, + SystemZ_WFMAXXB = 2756, + SystemZ_WFMDB = 2757, + SystemZ_WFMINDB = 2758, + SystemZ_WFMINSB = 2759, + SystemZ_WFMINXB = 2760, + SystemZ_WFMSB = 2761, + SystemZ_WFMSDB = 2762, + SystemZ_WFMSSB = 2763, + SystemZ_WFMSXB = 2764, + SystemZ_WFMXB = 2765, + SystemZ_WFNMADB = 2766, + SystemZ_WFNMASB = 2767, + SystemZ_WFNMAXB = 2768, + SystemZ_WFNMSDB = 2769, + SystemZ_WFNMSSB = 2770, + SystemZ_WFNMSXB = 2771, + SystemZ_WFPSODB = 2772, + SystemZ_WFPSOSB = 2773, + SystemZ_WFPSOXB = 2774, + SystemZ_WFSDB = 2775, + SystemZ_WFSQDB = 2776, + SystemZ_WFSQSB = 2777, + SystemZ_WFSQXB = 2778, + SystemZ_WFSSB = 2779, + SystemZ_WFSXB = 2780, + SystemZ_WFTCIDB = 2781, + SystemZ_WFTCISB = 2782, + SystemZ_WFTCIXB = 2783, + SystemZ_WLDEB = 2784, + SystemZ_WLEDB = 2785, + SystemZ_X = 2786, + SystemZ_XC = 2787, + SystemZ_XG = 2788, + SystemZ_XGR = 2789, + SystemZ_XGRK = 2790, + SystemZ_XI = 2791, + SystemZ_XIHF = 2792, + SystemZ_XILF = 2793, + SystemZ_XIY = 2794, + SystemZ_XR = 2795, + SystemZ_XRK = 2796, + SystemZ_XSCH = 2797, + SystemZ_XY = 2798, + SystemZ_ZAP = 2799, + SystemZ_INSTRUCTION_LIST_END = 2800 +}; #endif // GET_INSTRINFO_ENUM diff --git a/arch/SystemZ/SystemZGenRegisterInfo.inc b/arch/SystemZ/SystemZGenRegisterInfo.inc index 1bed390518..68c2903956 100644 --- a/arch/SystemZ/SystemZGenRegisterInfo.inc +++ b/arch/SystemZ/SystemZGenRegisterInfo.inc @@ -9,7 +9,6 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ - #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM @@ -208,7 +207,7 @@ enum { SystemZ_R10Q = 191, SystemZ_R12Q = 192, SystemZ_R14Q = 193, - SystemZ_NUM_TARGET_REGS // 194 + SystemZ_NUM_TARGET_REGS // 194 }; // Register classes @@ -245,497 +244,492 @@ enum { |* *| \*===----------------------------------------------------------------------===*/ - #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg SystemZRegDiffLists[] = { - /* 0 */ 64857, 1, 1, 1, 0, - /* 5 */ 65325, 1, 0, - /* 8 */ 65471, 2, 0, - /* 11 */ 65473, 2, 0, - /* 14 */ 65475, 2, 0, - /* 17 */ 65477, 2, 0, - /* 20 */ 32, 40, 0, - /* 23 */ 65506, 40, 65494, 40, 0, - /* 28 */ 65508, 40, 65494, 40, 0, - /* 33 */ 65510, 40, 65494, 40, 0, - /* 38 */ 65512, 40, 65494, 40, 0, - /* 43 */ 65504, 40, 0, - /* 46 */ 65520, 40, 0, - /* 49 */ 65504, 41, 0, - /* 52 */ 65520, 41, 0, - /* 55 */ 65504, 42, 0, - /* 58 */ 65520, 42, 0, - /* 61 */ 65504, 43, 0, - /* 64 */ 65520, 43, 0, - /* 67 */ 65504, 44, 0, - /* 70 */ 65520, 44, 0, - /* 73 */ 65504, 45, 0, - /* 76 */ 65520, 45, 0, - /* 79 */ 65504, 46, 0, - /* 82 */ 65520, 46, 0, - /* 85 */ 65504, 47, 0, - /* 88 */ 65520, 47, 0, - /* 91 */ 65504, 48, 0, - /* 94 */ 65520, 48, 0, - /* 97 */ 65496, 65504, 56, 0, - /* 101 */ 65496, 65504, 58, 0, - /* 105 */ 65496, 65504, 60, 0, - /* 109 */ 65496, 65504, 62, 0, - /* 113 */ 65496, 65504, 64, 0, - /* 117 */ 65261, 0, - /* 119 */ 65294, 0, - /* 121 */ 65463, 0, - /* 123 */ 65503, 0, - /* 125 */ 65496, 65504, 0, - /* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0, - /* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0, - /* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0, - /* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0, - /* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0, - /* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0, - /* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0, - /* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0, - /* 184 */ 65535, 0, + /* 0 */ 64857, 1, 1, 1, 0, + /* 5 */ 65325, 1, 0, + /* 8 */ 65471, 2, 0, + /* 11 */ 65473, 2, 0, + /* 14 */ 65475, 2, 0, + /* 17 */ 65477, 2, 0, + /* 20 */ 32, 40, 0, + /* 23 */ 65506, 40, 65494, 40, 0, + /* 28 */ 65508, 40, 65494, 40, 0, + /* 33 */ 65510, 40, 65494, 40, 0, + /* 38 */ 65512, 40, 65494, 40, 0, + /* 43 */ 65504, 40, 0, + /* 46 */ 65520, 40, 0, + /* 49 */ 65504, 41, 0, + /* 52 */ 65520, 41, 0, + /* 55 */ 65504, 42, 0, + /* 58 */ 65520, 42, 0, + /* 61 */ 65504, 43, 0, + /* 64 */ 65520, 43, 0, + /* 67 */ 65504, 44, 0, + /* 70 */ 65520, 44, 0, + /* 73 */ 65504, 45, 0, + /* 76 */ 65520, 45, 0, + /* 79 */ 65504, 46, 0, + /* 82 */ 65520, 46, 0, + /* 85 */ 65504, 47, 0, + /* 88 */ 65520, 47, 0, + /* 91 */ 65504, 48, 0, + /* 94 */ 65520, 48, 0, + /* 97 */ 65496, 65504, 56, 0, + /* 101 */ 65496, 65504, 58, 0, + /* 105 */ 65496, 65504, 60, 0, + /* 109 */ 65496, 65504, 62, 0, + /* 113 */ 65496, 65504, 64, 0, + /* 117 */ 65261, 0, + /* 119 */ 65294, 0, + /* 121 */ 65463, 0, + /* 123 */ 65503, 0, + /* 125 */ 65496, 65504, 0, + /* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0, + /* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0, + /* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0, + /* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0, + /* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0, + /* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0, + /* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0, + /* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0, + /* 184 */ 65535, 0, }; static const uint16_t SystemZSubRegIdxLists[] = { - /* 0 */ 6, 1, 0, - /* 3 */ 7, 6, 1, 2, 4, 3, 0, - /* 10 */ 7, 8, 2, 5, 0, - /* 15 */ 9, 8, 0, -}; - -static const MCRegisterDesc SystemZRegDesc[] = { // Descriptors - { 3, 0, 0, 0, 0, 0 }, - { 226, 4, 4, 2, 2945, 0 }, - { 20, 4, 4, 2, 2945, 0 }, - { 49, 4, 4, 2, 2945, 0 }, - { 74, 4, 4, 2, 2945, 0 }, - { 99, 4, 4, 2, 2945, 0 }, - { 124, 4, 4, 2, 2945, 0 }, - { 149, 4, 4, 2, 2945, 0 }, - { 166, 4, 4, 2, 2945, 0 }, - { 183, 4, 4, 2, 2945, 0 }, - { 200, 4, 4, 2, 2945, 0 }, - { 217, 4, 4, 2, 2945, 0 }, - { 0, 4, 4, 2, 2945, 0 }, - { 29, 4, 4, 2, 2945, 0 }, - { 58, 4, 4, 2, 2945, 0 }, - { 83, 4, 4, 2, 2945, 0 }, - { 108, 4, 4, 2, 2945, 0 }, - { 133, 4, 4, 2, 2945, 0 }, - { 23, 4, 4, 2, 2945, 0 }, - { 52, 4, 4, 2, 2945, 0 }, - { 77, 4, 4, 2, 2945, 0 }, - { 102, 4, 4, 2, 2945, 0 }, - { 127, 4, 4, 2, 2945, 0 }, - { 152, 4, 4, 2, 2945, 0 }, - { 169, 4, 4, 2, 2945, 0 }, - { 186, 4, 4, 2, 2945, 0 }, - { 203, 4, 4, 2, 2945, 0 }, - { 220, 4, 4, 2, 2945, 0 }, - { 4, 4, 4, 2, 2945, 0 }, - { 33, 4, 4, 2, 2945, 0 }, - { 62, 4, 4, 2, 2945, 0 }, - { 87, 4, 4, 2, 2945, 0 }, - { 112, 4, 4, 2, 2945, 0 }, - { 137, 4, 4, 2, 2945, 0 }, - { 26, 20, 4, 15, 2945, 8 }, - { 55, 20, 4, 15, 2945, 8 }, - { 80, 20, 4, 15, 2945, 8 }, - { 105, 20, 4, 15, 2945, 8 }, - { 130, 20, 4, 15, 2945, 8 }, - { 155, 20, 4, 15, 2945, 8 }, - { 172, 20, 4, 15, 2945, 8 }, - { 189, 20, 4, 15, 2945, 8 }, - { 206, 20, 4, 15, 2945, 8 }, - { 223, 20, 4, 15, 2945, 8 }, - { 8, 20, 4, 15, 2945, 8 }, - { 37, 20, 4, 15, 2945, 8 }, - { 66, 20, 4, 15, 2945, 8 }, - { 91, 20, 4, 15, 2945, 8 }, - { 116, 20, 4, 15, 2945, 8 }, - { 141, 20, 4, 15, 2945, 8 }, - { 158, 20, 4, 15, 2945, 8 }, - { 175, 20, 4, 15, 2945, 8 }, - { 192, 20, 4, 15, 2945, 8 }, - { 209, 20, 4, 15, 2945, 8 }, - { 12, 20, 4, 15, 2945, 8 }, - { 41, 20, 4, 15, 2945, 8 }, - { 70, 20, 4, 15, 2945, 8 }, - { 95, 20, 4, 15, 2945, 8 }, - { 120, 20, 4, 15, 2945, 8 }, - { 145, 20, 4, 15, 2945, 8 }, - { 162, 20, 4, 15, 2945, 8 }, - { 179, 20, 4, 15, 2945, 8 }, - { 196, 20, 4, 15, 2945, 8 }, - { 213, 20, 4, 15, 2945, 8 }, - { 16, 20, 4, 15, 2945, 8 }, - { 45, 20, 4, 15, 2945, 8 }, - { 249, 21, 114, 16, 1969, 8 }, - { 277, 21, 114, 16, 1969, 8 }, - { 300, 21, 110, 16, 1969, 8 }, - { 323, 21, 110, 16, 1969, 8 }, - { 346, 21, 110, 16, 1969, 8 }, - { 369, 21, 110, 16, 1969, 8 }, - { 387, 21, 106, 16, 1969, 8 }, - { 405, 21, 106, 16, 1969, 8 }, - { 423, 21, 106, 16, 1969, 8 }, - { 441, 21, 106, 16, 1969, 8 }, - { 229, 21, 102, 16, 1969, 8 }, - { 257, 21, 102, 16, 1969, 8 }, - { 285, 21, 102, 16, 1969, 8 }, - { 308, 21, 102, 16, 1969, 8 }, - { 331, 21, 98, 16, 1969, 8 }, - { 354, 21, 98, 16, 1969, 8 }, - { 377, 21, 126, 16, 1969, 8 }, - { 395, 21, 126, 16, 1969, 8 }, - { 413, 21, 126, 16, 1969, 8 }, - { 431, 21, 126, 16, 1969, 8 }, - { 239, 21, 126, 16, 1969, 8 }, - { 267, 21, 126, 16, 1969, 8 }, - { 295, 21, 126, 16, 1969, 8 }, - { 318, 21, 126, 16, 1969, 8 }, - { 341, 21, 126, 16, 1969, 8 }, - { 364, 21, 126, 16, 1969, 8 }, - { 382, 21, 126, 16, 1969, 8 }, - { 400, 21, 126, 16, 1969, 8 }, - { 418, 21, 126, 16, 1969, 8 }, - { 436, 21, 126, 16, 1969, 8 }, - { 244, 21, 126, 16, 1969, 8 }, - { 272, 21, 126, 16, 1969, 8 }, - { 594, 23, 4, 10, 129, 7 }, - { 602, 23, 4, 10, 129, 7 }, - { 630, 28, 4, 10, 177, 7 }, - { 638, 28, 4, 10, 177, 7 }, - { 646, 33, 4, 10, 225, 7 }, - { 654, 33, 4, 10, 225, 7 }, - { 606, 38, 4, 10, 273, 7 }, - { 620, 38, 4, 10, 273, 7 }, - { 673, 4, 113, 2, 1937, 0 }, - { 692, 4, 113, 2, 1937, 0 }, - { 706, 4, 109, 2, 1937, 0 }, - { 720, 4, 109, 2, 1937, 0 }, - { 734, 4, 109, 2, 1937, 0 }, - { 748, 4, 109, 2, 1937, 0 }, - { 762, 4, 105, 2, 1937, 0 }, - { 776, 4, 105, 2, 1937, 0 }, - { 790, 4, 105, 2, 1937, 0 }, - { 804, 4, 105, 2, 1937, 0 }, - { 658, 4, 101, 2, 1937, 0 }, - { 677, 4, 101, 2, 1937, 0 }, - { 696, 4, 101, 2, 1937, 0 }, - { 710, 4, 101, 2, 1937, 0 }, - { 724, 4, 97, 2, 1937, 0 }, - { 738, 4, 97, 2, 1937, 0 }, - { 752, 4, 125, 2, 1937, 0 }, - { 766, 4, 125, 2, 1937, 0 }, - { 780, 4, 125, 2, 1937, 0 }, - { 794, 4, 125, 2, 1937, 0 }, - { 663, 4, 125, 2, 1937, 0 }, - { 682, 4, 125, 2, 1937, 0 }, - { 701, 4, 125, 2, 1937, 0 }, - { 715, 4, 125, 2, 1937, 0 }, - { 729, 4, 125, 2, 1937, 0 }, - { 743, 4, 125, 2, 1937, 0 }, - { 757, 4, 125, 2, 1937, 0 }, - { 771, 4, 125, 2, 1937, 0 }, - { 785, 4, 125, 2, 1937, 0 }, - { 799, 4, 125, 2, 1937, 0 }, - { 668, 4, 125, 2, 1937, 0 }, - { 687, 4, 125, 2, 1937, 0 }, - { 253, 132, 92, 0, 82, 4 }, - { 281, 132, 86, 0, 82, 4 }, - { 304, 132, 86, 0, 82, 4 }, - { 327, 132, 80, 0, 82, 4 }, - { 350, 132, 80, 0, 82, 4 }, - { 373, 132, 74, 0, 82, 4 }, - { 391, 132, 74, 0, 82, 4 }, - { 409, 132, 68, 0, 82, 4 }, - { 427, 132, 68, 0, 82, 4 }, - { 445, 132, 62, 0, 82, 4 }, - { 234, 132, 62, 0, 82, 4 }, - { 262, 132, 56, 0, 82, 4 }, - { 290, 132, 56, 0, 82, 4 }, - { 313, 132, 50, 0, 82, 4 }, - { 336, 132, 50, 0, 82, 4 }, - { 359, 132, 21, 0, 82, 4 }, - { 454, 4, 94, 2, 1906, 0 }, - { 463, 4, 88, 2, 1906, 0 }, - { 472, 4, 88, 2, 1906, 0 }, - { 481, 4, 82, 2, 1906, 0 }, - { 490, 4, 82, 2, 1906, 0 }, - { 499, 4, 76, 2, 1906, 0 }, - { 503, 4, 76, 2, 1906, 0 }, - { 507, 4, 70, 2, 1906, 0 }, - { 511, 4, 70, 2, 1906, 0 }, - { 515, 4, 64, 2, 1906, 0 }, - { 449, 4, 64, 2, 1906, 0 }, - { 458, 4, 58, 2, 1906, 0 }, - { 467, 4, 58, 2, 1906, 0 }, - { 476, 4, 52, 2, 1906, 0 }, - { 485, 4, 52, 2, 1906, 0 }, - { 494, 4, 46, 2, 1906, 0 }, - { 524, 4, 91, 2, 1874, 0 }, - { 533, 4, 85, 2, 1874, 0 }, - { 542, 4, 85, 2, 1874, 0 }, - { 551, 4, 79, 2, 1874, 0 }, - { 560, 4, 79, 2, 1874, 0 }, - { 569, 4, 73, 2, 1874, 0 }, - { 573, 4, 73, 2, 1874, 0 }, - { 577, 4, 67, 2, 1874, 0 }, - { 581, 4, 67, 2, 1874, 0 }, - { 585, 4, 61, 2, 1874, 0 }, - { 519, 4, 61, 2, 1874, 0 }, - { 528, 4, 55, 2, 1874, 0 }, - { 537, 4, 55, 2, 1874, 0 }, - { 546, 4, 49, 2, 1874, 0 }, - { 555, 4, 49, 2, 1874, 0 }, - { 564, 4, 43, 2, 1874, 0 }, - { 598, 128, 4, 3, 4, 2 }, - { 616, 135, 4, 3, 4, 2 }, - { 634, 142, 4, 3, 4, 2 }, - { 642, 149, 4, 3, 4, 2 }, - { 650, 156, 4, 3, 4, 2 }, - { 589, 163, 4, 3, 4, 2 }, - { 611, 170, 4, 3, 4, 2 }, - { 625, 177, 4, 3, 4, 2 }, -}; - - // GRX32Bit Register Class... - static const MCPhysReg GRX32Bit[] = { - SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H, - }; - - // GRX32Bit Bit set. - static const uint8_t GRX32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, - }; - - // VR32Bit Register Class... - static const MCPhysReg VR32Bit[] = { - SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, - }; - - // VR32Bit Bit set. - static const uint8_t VR32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, - }; - - // AR32Bit Register Class... - static const MCPhysReg AR32Bit[] = { - SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15, - }; - - // AR32Bit Bit set. - static const uint8_t AR32BitBits[] = { - 0xfc, 0xff, 0x03, - }; - - // FP32Bit Register Class... - static const MCPhysReg FP32Bit[] = { - SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, - }; - - // FP32Bit Bit set. - static const uint8_t FP32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, - }; - - // GR32Bit Register Class... - static const MCPhysReg GR32Bit[] = { - SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, - }; - - // GR32Bit Bit set. - static const uint8_t GR32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, - }; - - // GRH32Bit Register Class... - static const MCPhysReg GRH32Bit[] = { - SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H, - }; - - // GRH32Bit Bit set. - static const uint8_t GRH32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, - }; - - // ADDR32Bit Register Class... - static const MCPhysReg ADDR32Bit[] = { - SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, - }; - - // ADDR32Bit Bit set. - static const uint8_t ADDR32BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, - }; - - // CCR Register Class... - static const MCPhysReg CCR[] = { + /* 0 */ 6, 1, 0, + /* 3 */ 7, 6, 1, 2, 4, 3, 0, + /* 10 */ 7, 8, 2, 5, 0, + /* 15 */ 9, 8, 0, +}; + +static const MCRegisterDesc SystemZRegDesc[] = { + // Descriptors + {3, 0, 0, 0, 0, 0}, {226, 4, 4, 2, 2945, 0}, + {20, 4, 4, 2, 2945, 0}, {49, 4, 4, 2, 2945, 0}, + {74, 4, 4, 2, 2945, 0}, {99, 4, 4, 2, 2945, 0}, + {124, 4, 4, 2, 2945, 0}, {149, 4, 4, 2, 2945, 0}, + {166, 4, 4, 2, 2945, 0}, {183, 4, 4, 2, 2945, 0}, + {200, 4, 4, 2, 2945, 0}, {217, 4, 4, 2, 2945, 0}, + {0, 4, 4, 2, 2945, 0}, {29, 4, 4, 2, 2945, 0}, + {58, 4, 4, 2, 2945, 0}, {83, 4, 4, 2, 2945, 0}, + {108, 4, 4, 2, 2945, 0}, {133, 4, 4, 2, 2945, 0}, + {23, 4, 4, 2, 2945, 0}, {52, 4, 4, 2, 2945, 0}, + {77, 4, 4, 2, 2945, 0}, {102, 4, 4, 2, 2945, 0}, + {127, 4, 4, 2, 2945, 0}, {152, 4, 4, 2, 2945, 0}, + {169, 4, 4, 2, 2945, 0}, {186, 4, 4, 2, 2945, 0}, + {203, 4, 4, 2, 2945, 0}, {220, 4, 4, 2, 2945, 0}, + {4, 4, 4, 2, 2945, 0}, {33, 4, 4, 2, 2945, 0}, + {62, 4, 4, 2, 2945, 0}, {87, 4, 4, 2, 2945, 0}, + {112, 4, 4, 2, 2945, 0}, {137, 4, 4, 2, 2945, 0}, + {26, 20, 4, 15, 2945, 8}, {55, 20, 4, 15, 2945, 8}, + {80, 20, 4, 15, 2945, 8}, {105, 20, 4, 15, 2945, 8}, + {130, 20, 4, 15, 2945, 8}, {155, 20, 4, 15, 2945, 8}, + {172, 20, 4, 15, 2945, 8}, {189, 20, 4, 15, 2945, 8}, + {206, 20, 4, 15, 2945, 8}, {223, 20, 4, 15, 2945, 8}, + {8, 20, 4, 15, 2945, 8}, {37, 20, 4, 15, 2945, 8}, + {66, 20, 4, 15, 2945, 8}, {91, 20, 4, 15, 2945, 8}, + {116, 20, 4, 15, 2945, 8}, {141, 20, 4, 15, 2945, 8}, + {158, 20, 4, 15, 2945, 8}, {175, 20, 4, 15, 2945, 8}, + {192, 20, 4, 15, 2945, 8}, {209, 20, 4, 15, 2945, 8}, + {12, 20, 4, 15, 2945, 8}, {41, 20, 4, 15, 2945, 8}, + {70, 20, 4, 15, 2945, 8}, {95, 20, 4, 15, 2945, 8}, + {120, 20, 4, 15, 2945, 8}, {145, 20, 4, 15, 2945, 8}, + {162, 20, 4, 15, 2945, 8}, {179, 20, 4, 15, 2945, 8}, + {196, 20, 4, 15, 2945, 8}, {213, 20, 4, 15, 2945, 8}, + {16, 20, 4, 15, 2945, 8}, {45, 20, 4, 15, 2945, 8}, + {249, 21, 114, 16, 1969, 8}, {277, 21, 114, 16, 1969, 8}, + {300, 21, 110, 16, 1969, 8}, {323, 21, 110, 16, 1969, 8}, + {346, 21, 110, 16, 1969, 8}, {369, 21, 110, 16, 1969, 8}, + {387, 21, 106, 16, 1969, 8}, {405, 21, 106, 16, 1969, 8}, + {423, 21, 106, 16, 1969, 8}, {441, 21, 106, 16, 1969, 8}, + {229, 21, 102, 16, 1969, 8}, {257, 21, 102, 16, 1969, 8}, + {285, 21, 102, 16, 1969, 8}, {308, 21, 102, 16, 1969, 8}, + {331, 21, 98, 16, 1969, 8}, {354, 21, 98, 16, 1969, 8}, + {377, 21, 126, 16, 1969, 8}, {395, 21, 126, 16, 1969, 8}, + {413, 21, 126, 16, 1969, 8}, {431, 21, 126, 16, 1969, 8}, + {239, 21, 126, 16, 1969, 8}, {267, 21, 126, 16, 1969, 8}, + {295, 21, 126, 16, 1969, 8}, {318, 21, 126, 16, 1969, 8}, + {341, 21, 126, 16, 1969, 8}, {364, 21, 126, 16, 1969, 8}, + {382, 21, 126, 16, 1969, 8}, {400, 21, 126, 16, 1969, 8}, + {418, 21, 126, 16, 1969, 8}, {436, 21, 126, 16, 1969, 8}, + {244, 21, 126, 16, 1969, 8}, {272, 21, 126, 16, 1969, 8}, + {594, 23, 4, 10, 129, 7}, {602, 23, 4, 10, 129, 7}, + {630, 28, 4, 10, 177, 7}, {638, 28, 4, 10, 177, 7}, + {646, 33, 4, 10, 225, 7}, {654, 33, 4, 10, 225, 7}, + {606, 38, 4, 10, 273, 7}, {620, 38, 4, 10, 273, 7}, + {673, 4, 113, 2, 1937, 0}, {692, 4, 113, 2, 1937, 0}, + {706, 4, 109, 2, 1937, 0}, {720, 4, 109, 2, 1937, 0}, + {734, 4, 109, 2, 1937, 0}, {748, 4, 109, 2, 1937, 0}, + {762, 4, 105, 2, 1937, 0}, {776, 4, 105, 2, 1937, 0}, + {790, 4, 105, 2, 1937, 0}, {804, 4, 105, 2, 1937, 0}, + {658, 4, 101, 2, 1937, 0}, {677, 4, 101, 2, 1937, 0}, + {696, 4, 101, 2, 1937, 0}, {710, 4, 101, 2, 1937, 0}, + {724, 4, 97, 2, 1937, 0}, {738, 4, 97, 2, 1937, 0}, + {752, 4, 125, 2, 1937, 0}, {766, 4, 125, 2, 1937, 0}, + {780, 4, 125, 2, 1937, 0}, {794, 4, 125, 2, 1937, 0}, + {663, 4, 125, 2, 1937, 0}, {682, 4, 125, 2, 1937, 0}, + {701, 4, 125, 2, 1937, 0}, {715, 4, 125, 2, 1937, 0}, + {729, 4, 125, 2, 1937, 0}, {743, 4, 125, 2, 1937, 0}, + {757, 4, 125, 2, 1937, 0}, {771, 4, 125, 2, 1937, 0}, + {785, 4, 125, 2, 1937, 0}, {799, 4, 125, 2, 1937, 0}, + {668, 4, 125, 2, 1937, 0}, {687, 4, 125, 2, 1937, 0}, + {253, 132, 92, 0, 82, 4}, {281, 132, 86, 0, 82, 4}, + {304, 132, 86, 0, 82, 4}, {327, 132, 80, 0, 82, 4}, + {350, 132, 80, 0, 82, 4}, {373, 132, 74, 0, 82, 4}, + {391, 132, 74, 0, 82, 4}, {409, 132, 68, 0, 82, 4}, + {427, 132, 68, 0, 82, 4}, {445, 132, 62, 0, 82, 4}, + {234, 132, 62, 0, 82, 4}, {262, 132, 56, 0, 82, 4}, + {290, 132, 56, 0, 82, 4}, {313, 132, 50, 0, 82, 4}, + {336, 132, 50, 0, 82, 4}, {359, 132, 21, 0, 82, 4}, + {454, 4, 94, 2, 1906, 0}, {463, 4, 88, 2, 1906, 0}, + {472, 4, 88, 2, 1906, 0}, {481, 4, 82, 2, 1906, 0}, + {490, 4, 82, 2, 1906, 0}, {499, 4, 76, 2, 1906, 0}, + {503, 4, 76, 2, 1906, 0}, {507, 4, 70, 2, 1906, 0}, + {511, 4, 70, 2, 1906, 0}, {515, 4, 64, 2, 1906, 0}, + {449, 4, 64, 2, 1906, 0}, {458, 4, 58, 2, 1906, 0}, + {467, 4, 58, 2, 1906, 0}, {476, 4, 52, 2, 1906, 0}, + {485, 4, 52, 2, 1906, 0}, {494, 4, 46, 2, 1906, 0}, + {524, 4, 91, 2, 1874, 0}, {533, 4, 85, 2, 1874, 0}, + {542, 4, 85, 2, 1874, 0}, {551, 4, 79, 2, 1874, 0}, + {560, 4, 79, 2, 1874, 0}, {569, 4, 73, 2, 1874, 0}, + {573, 4, 73, 2, 1874, 0}, {577, 4, 67, 2, 1874, 0}, + {581, 4, 67, 2, 1874, 0}, {585, 4, 61, 2, 1874, 0}, + {519, 4, 61, 2, 1874, 0}, {528, 4, 55, 2, 1874, 0}, + {537, 4, 55, 2, 1874, 0}, {546, 4, 49, 2, 1874, 0}, + {555, 4, 49, 2, 1874, 0}, {564, 4, 43, 2, 1874, 0}, + {598, 128, 4, 3, 4, 2}, {616, 135, 4, 3, 4, 2}, + {634, 142, 4, 3, 4, 2}, {642, 149, 4, 3, 4, 2}, + {650, 156, 4, 3, 4, 2}, {589, 163, 4, 3, 4, 2}, + {611, 170, 4, 3, 4, 2}, {625, 177, 4, 3, 4, 2}, +}; + +// GRX32Bit Register Class... +static const MCPhysReg GRX32Bit[] = { + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, + SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, + SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, + SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, + SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, + SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, + SystemZ_R6L, SystemZ_R6H, +}; + +// GRX32Bit Bit set. +static const uint8_t GRX32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, +}; + +// VR32Bit Register Class... +static const MCPhysReg VR32Bit[] = { + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, + SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, + SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, + SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, + SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, + SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, + SystemZ_F14S, SystemZ_F15S, +}; + +// VR32Bit Bit set. +static const uint8_t VR32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, +}; + +// AR32Bit Register Class... +static const MCPhysReg AR32Bit[] = { + SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, + SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, + SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, + SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15, +}; + +// AR32Bit Bit set. +static const uint8_t AR32BitBits[] = { + 0xfc, + 0xff, + 0x03, +}; + +// FP32Bit Register Class... +static const MCPhysReg FP32Bit[] = { + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, + SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, + SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, + SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, +}; + +// FP32Bit Bit set. +static const uint8_t FP32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// GR32Bit Register Class... +static const MCPhysReg GR32Bit[] = { + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, + SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, + SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, + SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, +}; + +// GR32Bit Bit set. +static const uint8_t GR32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// GRH32Bit Register Class... +static const MCPhysReg GRH32Bit[] = { + SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, + SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, + SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, + SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H, +}; + +// GRH32Bit Bit set. +static const uint8_t GRH32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// ADDR32Bit Register Class... +static const MCPhysReg ADDR32Bit[] = { + SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, + SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, + SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, +}; + +// ADDR32Bit Bit set. +static const uint8_t ADDR32BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, +}; + +// CCR Register Class... +static const MCPhysReg CCR[] = { SystemZ_CC, - }; +}; - // CCR Bit set. - static const uint8_t CCRBits[] = { +// CCR Bit set. +static const uint8_t CCRBits[] = { 0x02, - }; +}; - // AnyRegBit Register Class... - static const MCPhysReg AnyRegBit[] = { - SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, - }; +// AnyRegBit Register Class... +static const MCPhysReg AnyRegBit[] = { + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, + SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, + SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, + SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, + SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, + SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, + SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, + SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, + SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, + SystemZ_V13, SystemZ_V14, SystemZ_V15, +}; - // AnyRegBit Bit set. - static const uint8_t AnyRegBitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, - }; +// AnyRegBit Bit set. +static const uint8_t AnyRegBitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, + 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; - // AnyRegBit_with_subreg_r32 Register Class... - static const MCPhysReg AnyRegBit_with_subreg_r32[] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, - }; +// AnyRegBit_with_subreg_r32 Register Class... +static const MCPhysReg AnyRegBit_with_subreg_r32[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, + SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, + SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, + SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, + SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, + SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, + SystemZ_V14, SystemZ_V15, +}; - // AnyRegBit_with_subreg_r32 Bit set. - static const uint8_t AnyRegBit_with_subreg_r32Bits[] = { +// AnyRegBit_with_subreg_r32 Bit set. +static const uint8_t AnyRegBit_with_subreg_r32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, - }; +}; - // VR64Bit Register Class... - static const MCPhysReg VR64Bit[] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, - }; +// VR64Bit Register Class... +static const MCPhysReg VR64Bit[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, + SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, + SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, + SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, + SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, + SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, + SystemZ_F14D, SystemZ_F15D, +}; - // VR64Bit Bit set. - static const uint8_t VR64BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, - }; +// VR64Bit Bit set. +static const uint8_t VR64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, +}; - // AnyRegBit_with_subreg_r64 Register Class... - static const MCPhysReg AnyRegBit_with_subreg_r64[] = { - SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, - }; +// AnyRegBit_with_subreg_r64 Register Class... +static const MCPhysReg AnyRegBit_with_subreg_r64[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, + SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, + SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, + SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, +}; - // AnyRegBit_with_subreg_r64 Bit set. - static const uint8_t AnyRegBit_with_subreg_r64Bits[] = { +// AnyRegBit_with_subreg_r64 Bit set. +static const uint8_t AnyRegBit_with_subreg_r64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, - }; +}; - // CR64Bit Register Class... - static const MCPhysReg CR64Bit[] = { - SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15, - }; +// CR64Bit Register Class... +static const MCPhysReg CR64Bit[] = { + SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, + SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, + SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, + SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15, +}; - // CR64Bit Bit set. - static const uint8_t CR64BitBits[] = { +// CR64Bit Bit set. +static const uint8_t CR64BitBits[] = { 0x00, 0x00, 0xfc, 0xff, 0x03, - }; +}; - // FP64Bit Register Class... - static const MCPhysReg FP64Bit[] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, - }; +// FP64Bit Register Class... +static const MCPhysReg FP64Bit[] = { + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, + SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, + SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, + SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, +}; - // FP64Bit Bit set. - static const uint8_t FP64BitBits[] = { +// FP64Bit Bit set. +static const uint8_t FP64BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, - }; - - // GR64Bit Register Class... - static const MCPhysReg GR64Bit[] = { - SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, - }; - - // GR64Bit Bit set. - static const uint8_t GR64BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, - }; - - // ADDR64Bit Register Class... - static const MCPhysReg ADDR64Bit[] = { - SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, - }; - - // ADDR64Bit Bit set. - static const uint8_t ADDR64BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, - }; - - // VR128Bit Register Class... - static const MCPhysReg VR128Bit[] = { - SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, - }; - - // VR128Bit Bit set. - static const uint8_t VR128BitBits[] = { +}; + +// GR64Bit Register Class... +static const MCPhysReg GR64Bit[] = { + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, + SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, + SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, + SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, +}; + +// GR64Bit Bit set. +static const uint8_t GR64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, +}; + +// ADDR64Bit Register Class... +static const MCPhysReg ADDR64Bit[] = { + SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, + SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, + SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, +}; + +// ADDR64Bit Bit set. +static const uint8_t ADDR64BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, +}; + +// VR128Bit Register Class... +static const MCPhysReg VR128Bit[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, + SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, + SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, + SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, + SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, + SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, + SystemZ_V14, SystemZ_V15, +}; + +// VR128Bit Bit set. +static const uint8_t VR128BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, - }; +}; - // VF128Bit Register Class... - static const MCPhysReg VF128Bit[] = { - SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, - }; +// VF128Bit Register Class... +static const MCPhysReg VF128Bit[] = { + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, + SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, + SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, + SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, +}; - // VF128Bit Bit set. - static const uint8_t VF128BitBits[] = { +// VF128Bit Bit set. +static const uint8_t VF128BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, - }; - - // FP128Bit Register Class... - static const MCPhysReg FP128Bit[] = { - SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q, - }; - - // FP128Bit Bit set. - static const uint8_t FP128BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, - }; - - // GR128Bit Register Class... - static const MCPhysReg GR128Bit[] = { - SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, - }; - - // GR128Bit Bit set. - static const uint8_t GR128BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, - }; - - // ADDR128Bit Register Class... - static const MCPhysReg ADDR128Bit[] = { - SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, - }; - - // ADDR128Bit Bit set. - static const uint8_t ADDR128BitBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, - }; +}; + +// FP128Bit Register Class... +static const MCPhysReg FP128Bit[] = { + SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, + SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q, +}; + +// FP128Bit Bit set. +static const uint8_t FP128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, +}; + +// GR128Bit Register Class... +static const MCPhysReg GR128Bit[] = { + SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, + SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, +}; + +// GR128Bit Bit set. +static const uint8_t GR128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, +}; + +// ADDR128Bit Register Class... +static const MCPhysReg ADDR128Bit[] = { + SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, + SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, +}; + +// ADDR128Bit Bit set. +static const uint8_t ADDR128BitBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, +}; static const MCRegisterClass SystemZMCRegisterClasses[] = { - { GRX32Bit, GRX32BitBits, sizeof(GRX32BitBits) }, - { VR32Bit, VR32BitBits, sizeof(VR32BitBits) }, - { AR32Bit, AR32BitBits, sizeof(AR32BitBits) }, - { FP32Bit, FP32BitBits, sizeof(FP32BitBits) }, - { GR32Bit, GR32BitBits, sizeof(GR32BitBits) }, - { GRH32Bit, GRH32BitBits, sizeof(GRH32BitBits) }, - { ADDR32Bit, ADDR32BitBits, sizeof(ADDR32BitBits) }, - { CCR, CCRBits, sizeof(CCRBits) }, - { AnyRegBit, AnyRegBitBits, sizeof(AnyRegBitBits) }, - { AnyRegBit_with_subreg_r32, AnyRegBit_with_subreg_r32Bits, sizeof(AnyRegBit_with_subreg_r32Bits) }, - { VR64Bit, VR64BitBits, sizeof(VR64BitBits) }, - { AnyRegBit_with_subreg_r64, AnyRegBit_with_subreg_r64Bits, sizeof(AnyRegBit_with_subreg_r64Bits) }, - { CR64Bit, CR64BitBits, sizeof(CR64BitBits) }, - { FP64Bit, FP64BitBits, sizeof(FP64BitBits) }, - { GR64Bit, GR64BitBits, sizeof(GR64BitBits) }, - { ADDR64Bit, ADDR64BitBits, sizeof(ADDR64BitBits) }, - { VR128Bit, VR128BitBits, sizeof(VR128BitBits) }, - { VF128Bit, VF128BitBits, sizeof(VF128BitBits) }, - { FP128Bit, FP128BitBits, sizeof(FP128BitBits) }, - { GR128Bit, GR128BitBits, sizeof(GR128BitBits) }, - { ADDR128Bit, ADDR128BitBits, sizeof(ADDR128BitBits) }, + {GRX32Bit, GRX32BitBits, sizeof(GRX32BitBits)}, + {VR32Bit, VR32BitBits, sizeof(VR32BitBits)}, + {AR32Bit, AR32BitBits, sizeof(AR32BitBits)}, + {FP32Bit, FP32BitBits, sizeof(FP32BitBits)}, + {GR32Bit, GR32BitBits, sizeof(GR32BitBits)}, + {GRH32Bit, GRH32BitBits, sizeof(GRH32BitBits)}, + {ADDR32Bit, ADDR32BitBits, sizeof(ADDR32BitBits)}, + {CCR, CCRBits, sizeof(CCRBits)}, + {AnyRegBit, AnyRegBitBits, sizeof(AnyRegBitBits)}, + {AnyRegBit_with_subreg_r32, AnyRegBit_with_subreg_r32Bits, + sizeof(AnyRegBit_with_subreg_r32Bits)}, + {VR64Bit, VR64BitBits, sizeof(VR64BitBits)}, + {AnyRegBit_with_subreg_r64, AnyRegBit_with_subreg_r64Bits, + sizeof(AnyRegBit_with_subreg_r64Bits)}, + {CR64Bit, CR64BitBits, sizeof(CR64BitBits)}, + {FP64Bit, FP64BitBits, sizeof(FP64BitBits)}, + {GR64Bit, GR64BitBits, sizeof(GR64BitBits)}, + {ADDR64Bit, ADDR64BitBits, sizeof(ADDR64BitBits)}, + {VR128Bit, VR128BitBits, sizeof(VR128BitBits)}, + {VF128Bit, VF128BitBits, sizeof(VF128BitBits)}, + {FP128Bit, FP128BitBits, sizeof(FP128BitBits)}, + {GR128Bit, GR128BitBits, sizeof(GR128BitBits)}, + {ADDR128Bit, ADDR128BitBits, sizeof(ADDR128BitBits)}, }; #endif // GET_REGINFO_MC_DESC diff --git a/arch/SystemZ/SystemZGenSubtargetInfo.inc b/arch/SystemZ/SystemZGenSubtargetInfo.inc index 4d62b7295c..c8e22a839a 100644 --- a/arch/SystemZ/SystemZGenSubtargetInfo.inc +++ b/arch/SystemZ/SystemZGenSubtargetInfo.inc @@ -9,7 +9,6 @@ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ - #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM @@ -46,4 +45,3 @@ enum { }; #endif // GET_SUBTARGETINFO_ENUM - diff --git a/arch/SystemZ/SystemZInstPrinter.c b/arch/SystemZ/SystemZInstPrinter.c index 0d992dcb0f..ab2f784371 100644 --- a/arch/SystemZ/SystemZInstPrinter.c +++ b/arch/SystemZ/SystemZInstPrinter.c @@ -1,4 +1,5 @@ -//===-- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax --------===// +//===-- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax +//--------===// // // The LLVM Compiler Infrastructure // @@ -16,418 +17,450 @@ #ifdef CAPSTONE_HAS_SYSZ +#include #include #include #include -#include -#include "SystemZInstPrinter.h" #include "../../MCInst.h" -#include "../../utils.h" -#include "../../SStream.h" +#include "../../MCInstPrinter.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" +#include "../../SStream.h" +#include "../../utils.h" +#include "SystemZInstPrinter.h" #include "SystemZMapping.h" static const char *getRegisterName(unsigned RegNo); -void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) -{ - /* - if (((cs_struct *)ud)->detail != CS_OPT_ON) - return; - */ +static void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + +void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { + /* + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + */ } -static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index, SStream *O) -{ - printInt64(O, Disp); - - if (Base) { - SStream_concat0(O, "("); - if (Index) - SStream_concat(O, "%%%s, ", getRegisterName(Index)); - SStream_concat(O, "%%%s)", getRegisterName(Base)); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; - MI->flat_insn->detail->sysz.op_count++; - } - } else if (!Index) { - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp; - MI->flat_insn->detail->sysz.op_count++; - } - } else { - SStream_concat(O, "(%%%s)", getRegisterName(Index)); - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; - MI->flat_insn->detail->sysz.op_count++; - } - } +static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, + unsigned Index, SStream *O) { + printInt64(O, Disp); + + if (Base) { + SStream_concat0(O, "("); + if (Index) + SStream_concat(O, "%%%s, ", getRegisterName(Index)); + SStream_concat(O, "%%%s)", getRegisterName(Base)); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_MEM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.base = (uint8_t)SystemZ_map_register(Base); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.index = (uint8_t)SystemZ_map_register(Index); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.disp = Disp; + MI->flat_insn->detail->sysz.op_count++; + } + } else if (!Index) { + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = Disp; + MI->flat_insn->detail->sysz.op_count++; + } + } else { + SStream_concat(O, "(%%%s)", getRegisterName(Index)); + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_MEM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.base = (uint8_t)SystemZ_map_register(Base); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.index = (uint8_t)SystemZ_map_register(Index); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.disp = Disp; + MI->flat_insn->detail->sysz.op_count++; + } + } } -static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O) -{ - if (MCOperand_isReg(MO)) { - unsigned reg; - - reg = MCOperand_getReg(MO); - SStream_concat(O, "%%%s", getRegisterName(reg)); - reg = SystemZ_map_register(reg); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg; - MI->flat_insn->detail->sysz.op_count++; - } - } else if (MCOperand_isImm(MO)) { - int64_t Imm = MCOperand_getImm(MO); - - printInt64(O, Imm); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Imm; - MI->flat_insn->detail->sysz.op_count++; - } - } +static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O) { + if (MCOperand_isReg(MO)) { + unsigned reg; + + reg = MCOperand_getReg(MO); + SStream_concat(O, "%%%s", getRegisterName(reg)); + reg = SystemZ_map_register(reg); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_REG; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .reg = reg; + MI->flat_insn->detail->sysz.op_count++; + } + } else if (MCOperand_isImm(MO)) { + int64_t Imm = MCOperand_getImm(MO); + + printInt64(O, Imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = Imm; + MI->flat_insn->detail->sysz.op_count++; + } + } } -static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<1>(Value) && "Invalid u1imm argument"); - printInt64(O, Value); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O) { + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<1>(Value) && "Invalid u1imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<2>(Value) && "Invalid u2imm argument"); - printInt64(O, Value); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O) { + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<2>(Value) && "Invalid u2imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<3>(Value) && "Invalid u4imm argument"); - printInt64(O, Value); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O) { + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<3>(Value) && "Invalid u4imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<4>(Value) && "Invalid u4imm argument"); - printInt64(O, Value); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O) { + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<4>(Value) && "Invalid u4imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<6>(Value) && "Invalid u6imm argument"); +static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O) { + uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<6>(Value) && "Invalid u6imm argument"); - printUInt32(O, Value); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - int8_t Value = (int8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isInt<8>(Value) && "Invalid s8imm argument"); - - if (Value >= 0) { - if (Value > HEX_THRESHOLD) - SStream_concat(O, "0x%x", Value); - else - SStream_concat(O, "%u", Value); - } else { - if (Value < -HEX_THRESHOLD) - SStream_concat(O, "-0x%x", -Value); - else - SStream_concat(O, "-%u", -Value); - } - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O) { + int8_t Value = (int8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isInt<8>(Value) && "Invalid s8imm argument"); + + if (Value >= 0) { + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + } else { + if (Value < -HEX_THRESHOLD) + SStream_concat(O, "-0x%x", -Value); + else + SStream_concat(O, "-%u", -Value); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - uint8_t Value = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<8>(Value) && "Invalid u8imm argument"); - - if (Value > HEX_THRESHOLD) - SStream_concat(O, "0x%x", Value); - else - SStream_concat(O, "%u", Value); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O) { + uint8_t Value = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<8>(Value) && "Invalid u8imm argument"); + + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<12>(Value) && "Invalid u12imm argument"); - printInt64(O, Value); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O) { + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<12>(Value) && "Invalid u12imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - int16_t Value = (int16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isInt<16>(Value) && "Invalid s16imm argument"); - - if (Value >= 0) { - if (Value > HEX_THRESHOLD) - SStream_concat(O, "0x%x", Value); - else - SStream_concat(O, "%u", Value); - } else { - if (Value < -HEX_THRESHOLD) - SStream_concat(O, "-0x%x", -Value); - else - SStream_concat(O, "-%u", -Value); - } - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O) { + int16_t Value = (int16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isInt<16>(Value) && "Invalid s16imm argument"); + + if (Value >= 0) { + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + } else { + if (Value < -HEX_THRESHOLD) + SStream_concat(O, "-0x%x", -Value); + else + SStream_concat(O, "-%u", -Value); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - uint16_t Value = (uint16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<16>(Value) && "Invalid u16imm argument"); - - if (Value > HEX_THRESHOLD) - SStream_concat(O, "0x%x", Value); - else - SStream_concat(O, "%u", Value); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O) { + uint16_t Value = (uint16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<16>(Value) && "Invalid u16imm argument"); + + if (Value > HEX_THRESHOLD) + SStream_concat(O, "0x%x", Value); + else + SStream_concat(O, "%u", Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - int32_t Value = (int32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isInt<32>(Value) && "Invalid s32imm argument"); +static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O) { + int32_t Value = (int32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isInt<32>(Value) && "Invalid s32imm argument"); - printInt32(O, Value); + printInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<32>(Value) && "Invalid u32imm argument"); +static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O) { + uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<32>(Value) && "Invalid u32imm argument"); - printUInt32(O, Value); + printUInt32(O, Value); - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; - MI->flat_insn->detail->sysz.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = (int64_t)Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O) -{ - int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(isUInt<48>(Value) && "Invalid u48imm argument"); - printInt64(O, Value); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; - MI->flat_insn->detail->sysz.op_count++; - } +static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O) { + int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(isUInt<48>(Value) && "Invalid u48imm argument"); + printInt64(O, Value); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = Value; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O) -{ - MCOperand *MO = MCInst_getOperand(MI, OpNum); +static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O) { + MCOperand *MO = MCInst_getOperand(MI, OpNum); - if (MCOperand_isImm(MO)) { - int64_t imm = (int64_t)MCOperand_getImm(MO); + if (MCOperand_isImm(MO)) { + int64_t imm = (int64_t)MCOperand_getImm(MO); - printInt64(O, imm); + printInt64(O, imm); - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = imm; - MI->flat_insn->detail->sysz.op_count++; - } - } + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_IMM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .imm = imm; + MI->flat_insn->detail->sysz.op_count++; + } + } } -static void printPCRelTLSOperand(MCInst *MI, int OpNum, SStream *O) -{ - // Output the PC-relative operand. - printPCRelOperand(MI, OpNum, O); +static void printPCRelTLSOperand(MCInst *MI, int OpNum, SStream *O) { + // Output the PC-relative operand. + printPCRelOperand(MI, OpNum, O); } -static void printOperand(MCInst *MI, int OpNum, SStream *O) -{ - _printOperand(MI, MCInst_getOperand(MI, OpNum), O); +static void printOperand(MCInst *MI, int OpNum, SStream *O) { + _printOperand(MI, MCInst_getOperand(MI, OpNum), O); } -static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O) -{ - printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), - MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), 0, O); +static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O) { + printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), + MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), 0, O); } -static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O) -{ - printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), - MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), - MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); +static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O) { + printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), + MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), + MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); } -static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O) -{ - unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); - uint64_t Length = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2)); - - if (Disp > HEX_THRESHOLD) - SStream_concat(O, "0x%"PRIx64, Disp); - else - SStream_concat(O, "%"PRIu64, Disp); - - if (Length > HEX_THRESHOLD) - SStream_concat(O, "(0x%"PRIx64, Length); - else - SStream_concat(O, "(%"PRIu64, Length); - - if (Base) - SStream_concat(O, ", %%%s", getRegisterName(Base)); - SStream_concat0(O, ")"); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp; - MI->flat_insn->detail->sysz.op_count++; - } +static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O) { + unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); + uint64_t Length = + (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2)); + + if (Disp > HEX_THRESHOLD) + SStream_concat(O, "0x%" PRIx64, Disp); + else + SStream_concat(O, "%" PRIu64, Disp); + + if (Length > HEX_THRESHOLD) + SStream_concat(O, "(0x%" PRIx64, Length); + else + SStream_concat(O, "(%" PRIu64, Length); + + if (Base) + SStream_concat(O, ", %%%s", getRegisterName(Base)); + SStream_concat0(O, ")"); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_MEM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.base = (uint8_t)SystemZ_map_register(Base); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.length = Length; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.disp = (int64_t)Disp; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O) -{ - unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); - uint64_t Length = MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)); - - if (Disp > HEX_THRESHOLD) - SStream_concat(O, "0x%"PRIx64, Disp); - else - SStream_concat(O, "%"PRIu64, Disp); - - SStream_concat0(O, "("); - SStream_concat(O, "%%%s", getRegisterName(Length)); - - if (Base) - SStream_concat(O, ", %%%s", getRegisterName(Base)); - SStream_concat0(O, ")"); - - if (MI->csh->detail) { - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = (uint8_t)SystemZ_map_register(Length); - MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp; - MI->flat_insn->detail->sysz.op_count++; - } +static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O) { + unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); + uint64_t Length = MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)); + + if (Disp > HEX_THRESHOLD) + SStream_concat(O, "0x%" PRIx64, Disp); + else + SStream_concat(O, "%" PRIu64, Disp); + + SStream_concat0(O, "("); + SStream_concat(O, "%%%s", getRegisterName(Length)); + + if (Base) + SStream_concat(O, ", %%%s", getRegisterName(Base)); + SStream_concat0(O, ")"); + + if (MI->csh->detail) { + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .type = SYSZ_OP_MEM; + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.base = (uint8_t)SystemZ_map_register(Base); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.length = (uint8_t)SystemZ_map_register(Length); + MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count] + .mem.disp = (int64_t)Disp; + MI->flat_insn->detail->sysz.op_count++; + } } -static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O) -{ - printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), - MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), - MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); +static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O) { + printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), + MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), + MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); } -static void printCond4Operand(MCInst *MI, int OpNum, SStream *O) -{ - static const char *const CondNames[] = { - "o", "h", "nle", "l", "nhe", "lh", "ne", - "e", "nlh", "he", "nl", "le", "nh", "no" - }; +static void printCond4Operand(MCInst *MI, int OpNum, SStream *O) { + static const char *const CondNames[] = {"o", "h", "nle", "l", "nhe", + "lh", "ne", "e", "nlh", "he", + "nl", "le", "nh", "no"}; - uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // assert(Imm > 0 && Imm < 15 && "Invalid condition"); - SStream_concat0(O, CondNames[Imm - 1]); + uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // assert(Imm > 0 && Imm < 15 && "Invalid condition"); + SStream_concat0(O, CondNames[Imm - 1]); - if (MI->csh->detail) - MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm; + if (MI->csh->detail) + MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm; } +#define GET_INSTRINFO_ENUM #define PRINT_ALIAS_INSTR -#include "SystemZGenAsmWriter.inc" +#define GET_REGINFO_ENUM +#define GET_ASM_WRITER +#include "SystemZGenDisassemblerTables.inc" -void SystemZ_printInst(MCInst *MI, SStream *O, void *Info) -{ - printInstruction(MI, O, Info); +void SystemZ_printInst(MCInst *MI, SStream *O, void *Info) { + printInstruction(MI, O); } #endif diff --git a/arch/SystemZ/SystemZMCTargetDesc.c b/arch/SystemZ/SystemZMCTargetDesc.c index 538550e1b4..e09933e984 100644 --- a/arch/SystemZ/SystemZMCTargetDesc.c +++ b/arch/SystemZ/SystemZMCTargetDesc.c @@ -12,124 +12,96 @@ #ifdef CAPSTONE_HAS_SYSZ -#include #include "SystemZMCTargetDesc.h" +#include #define GET_REGINFO_ENUM -#include "SystemZGenRegisterInfo.inc" +#include "SystemZGenDisassemblerTables.inc" const unsigned SystemZMC_GR32Regs[16] = { - SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, - SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L, - SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L, - SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L -}; + SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, + SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L, + SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L, + SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L}; const unsigned SystemZMC_GRH32Regs[16] = { - SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, - SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H, - SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H, - SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H -}; + SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, + SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H, + SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H, + SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H}; const unsigned SystemZMC_GR64Regs[16] = { - SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, - SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, - SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, - SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D -}; + SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, + SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, + SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, + SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D}; const unsigned SystemZMC_GR128Regs[16] = { - SystemZ_R0Q, 0, SystemZ_R2Q, 0, - SystemZ_R4Q, 0, SystemZ_R6Q, 0, - SystemZ_R8Q, 0, SystemZ_R10Q, 0, - SystemZ_R12Q, 0, SystemZ_R14Q, 0 -}; + SystemZ_R0Q, 0, SystemZ_R2Q, 0, SystemZ_R4Q, 0, SystemZ_R6Q, 0, + SystemZ_R8Q, 0, SystemZ_R10Q, 0, SystemZ_R12Q, 0, SystemZ_R14Q, 0}; const unsigned SystemZMC_FP32Regs[16] = { - SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, - SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, - SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, - SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S -}; + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, + SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, + SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, + SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S}; const unsigned SystemZMC_FP64Regs[16] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, - SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, - SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, - SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D -}; + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, + SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, + SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, + SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D}; const unsigned SystemZMC_FP128Regs[16] = { - SystemZ_F0Q, SystemZ_F1Q, 0, 0, - SystemZ_F4Q, SystemZ_F5Q, 0, 0, - SystemZ_F8Q, SystemZ_F9Q, 0, 0, - SystemZ_F12Q, SystemZ_F13Q, 0, 0 -}; + SystemZ_F0Q, SystemZ_F1Q, 0, 0, SystemZ_F4Q, SystemZ_F5Q, 0, 0, + SystemZ_F8Q, SystemZ_F9Q, 0, 0, SystemZ_F12Q, SystemZ_F13Q, 0, 0}; const unsigned SystemZMC_VR32Regs[32] = { - SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, - SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, - SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, - SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, - SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, - SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, - SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, - SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S -}; + SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, + SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, + SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, + SystemZ_F15S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, + SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, + SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, + SystemZ_F30S, SystemZ_F31S}; const unsigned SystemZMC_VR64Regs[32] = { - SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, - SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, - SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, - SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, - SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, - SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, - SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, - SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D -}; + SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, + SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, + SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, + SystemZ_F15D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, + SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, + SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, + SystemZ_F30D, SystemZ_F31D}; const unsigned SystemZMC_VR128Regs[32] = { - SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, - SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, - SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, - SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, - SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, - SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, - SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, - SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31 -}; + SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, + SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, + SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, + SystemZ_V15, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, + SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, + SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, + SystemZ_V30, SystemZ_V31}; const unsigned SystemZMC_AR32Regs[16] = { - SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, - SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, - SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, - SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15 -}; + SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, + SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, + SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15}; const unsigned SystemZMC_CR64Regs[16] = { - SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, - SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, - SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, - SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15 -}; + SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, + SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, + SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15}; /* All register classes that have 0-15. */ -#define DEF_REG16(N) \ - [SystemZ_R ## N ## L] = N, \ - [SystemZ_R ## N ## H] = N, \ - [SystemZ_R ## N ## D] = N, \ - [SystemZ_F ## N ## S] = N, \ - [SystemZ_F ## N ## D] = N, \ - [SystemZ_V ## N] = N, \ - [SystemZ_A ## N] = N, \ - [SystemZ_C ## N] = N +#define DEF_REG16(N) \ + [SystemZ_R##N##L] = N, [SystemZ_R##N##H] = N, [SystemZ_R##N##D] = N, \ + [SystemZ_F##N##S] = N, [SystemZ_F##N##D] = N, [SystemZ_V##N] = N, \ + [SystemZ_A##N] = N, [SystemZ_C##N] = N /* All register classes that (also) have 16-31. */ -#define DEF_REG32(N) \ - [SystemZ_F ## N ## S] = N, \ - [SystemZ_F ## N ## D] = N, \ - [SystemZ_V ## N] = N +#define DEF_REG32(N) \ + [SystemZ_F##N##S] = N, [SystemZ_F##N##D] = N, [SystemZ_V##N] = N static const uint8_t Map[SystemZ_NUM_TARGET_REGS] = { DEF_REG16(0), @@ -186,10 +158,9 @@ static const uint8_t Map[SystemZ_NUM_TARGET_REGS] = { [SystemZ_R14Q] = 14, }; -unsigned SystemZMC_getFirstReg(unsigned Reg) -{ - // assert(Reg < SystemZ_NUM_TARGET_REGS); - return Map[Reg]; +unsigned SystemZMC_getFirstReg(unsigned Reg) { + // assert(Reg < SystemZ_NUM_TARGET_REGS); + return Map[Reg]; } #endif diff --git a/arch/SystemZ/SystemZMapping.c b/arch/SystemZ/SystemZMapping.c index 90b4ff3fc7..f26197732c 100644 --- a/arch/SystemZ/SystemZMapping.c +++ b/arch/SystemZ/SystemZMapping.c @@ -3,7 +3,7 @@ #ifdef CAPSTONE_HAS_SYSZ -#include // debug +#include // debug #include #include "../../utils.h" @@ -11,469 +11,414 @@ #include "SystemZMapping.h" #define GET_INSTRINFO_ENUM +#define GET_REGINFO_ENUM +#include "SystemZGenDisassemblerTables.inc" #include "SystemZGenInstrInfo.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { - { SYSZ_REG_INVALID, NULL }, + {SYSZ_REG_INVALID, NULL}, - { SYSZ_REG_0, "0" }, - { SYSZ_REG_1, "1" }, - { SYSZ_REG_2, "2" }, - { SYSZ_REG_3, "3" }, - { SYSZ_REG_4, "4" }, - { SYSZ_REG_5, "5" }, - { SYSZ_REG_6, "6" }, - { SYSZ_REG_7, "7" }, - { SYSZ_REG_8, "8" }, - { SYSZ_REG_9, "9" }, - { SYSZ_REG_10, "10" }, - { SYSZ_REG_11, "11" }, - { SYSZ_REG_12, "12" }, - { SYSZ_REG_13, "13" }, - { SYSZ_REG_14, "14" }, - { SYSZ_REG_15, "15" }, - { SYSZ_REG_CC, "cc"}, - { SYSZ_REG_F0, "f0" }, - { SYSZ_REG_F1, "f1" }, - { SYSZ_REG_F2, "f2" }, - { SYSZ_REG_F3, "f3" }, - { SYSZ_REG_F4, "f4" }, - { SYSZ_REG_F5, "f5" }, - { SYSZ_REG_F6, "f6" }, - { SYSZ_REG_F7, "f7" }, - { SYSZ_REG_F8, "f8" }, - { SYSZ_REG_F9, "f9" }, - { SYSZ_REG_F10, "f10" }, - { SYSZ_REG_F11, "f11" }, - { SYSZ_REG_F12, "f12" }, - { SYSZ_REG_F13, "f13" }, - { SYSZ_REG_F14, "f14" }, - { SYSZ_REG_F15, "f15" }, - { SYSZ_REG_R0L, "r0l" }, - { SYSZ_REG_A0, "a0" }, - { SYSZ_REG_A1, "a1" }, - { SYSZ_REG_A2, "a2" }, - { SYSZ_REG_A3, "a3" }, - { SYSZ_REG_A4, "a4" }, - { SYSZ_REG_A5, "a5" }, - { SYSZ_REG_A6, "a6" }, - { SYSZ_REG_A7, "a7" }, - { SYSZ_REG_A8, "a8" }, - { SYSZ_REG_A9, "a9" }, - { SYSZ_REG_A10, "a10" }, - { SYSZ_REG_A11, "a11" }, - { SYSZ_REG_A12, "a12" }, - { SYSZ_REG_A13, "a13" }, - { SYSZ_REG_A14, "a14" }, - { SYSZ_REG_A15, "a15" }, - { SYSZ_REG_C0, "c0" }, - { SYSZ_REG_C1, "c1" }, - { SYSZ_REG_C2, "c2" }, - { SYSZ_REG_C3, "c3" }, - { SYSZ_REG_C4, "c4" }, - { SYSZ_REG_C5, "c5" }, - { SYSZ_REG_C6, "c6" }, - { SYSZ_REG_C7, "c7" }, - { SYSZ_REG_C8, "c8" }, - { SYSZ_REG_C9, "c9" }, - { SYSZ_REG_C10, "c10" }, - { SYSZ_REG_C11, "c11" }, - { SYSZ_REG_C12, "c12" }, - { SYSZ_REG_C13, "c13" }, - { SYSZ_REG_C14, "c14" }, - { SYSZ_REG_C15, "c15" }, - { SYSZ_REG_V0, "v0" }, - { SYSZ_REG_V1, "v1" }, - { SYSZ_REG_V2, "v2" }, - { SYSZ_REG_V3, "v3" }, - { SYSZ_REG_V4, "v4" }, - { SYSZ_REG_V5, "v5" }, - { SYSZ_REG_V6, "v6" }, - { SYSZ_REG_V7, "v7" }, - { SYSZ_REG_V8, "v8" }, - { SYSZ_REG_V9, "v9" }, - { SYSZ_REG_V10, "v10" }, - { SYSZ_REG_V11, "v11" }, - { SYSZ_REG_V12, "v12" }, - { SYSZ_REG_V13, "v13" }, - { SYSZ_REG_V14, "v14" }, - { SYSZ_REG_V15, "v15" }, - { SYSZ_REG_V16, "v16" }, - { SYSZ_REG_V17, "v17" }, - { SYSZ_REG_V18, "v18" }, - { SYSZ_REG_V19, "v19" }, - { SYSZ_REG_V20, "v20" }, - { SYSZ_REG_V21, "v21" }, - { SYSZ_REG_V22, "v22" }, - { SYSZ_REG_V23, "v23" }, - { SYSZ_REG_V24, "v24" }, - { SYSZ_REG_V25, "v25" }, - { SYSZ_REG_V26, "v26" }, - { SYSZ_REG_V27, "v27" }, - { SYSZ_REG_V28, "v28" }, - { SYSZ_REG_V29, "v29" }, - { SYSZ_REG_V30, "v30" }, - { SYSZ_REG_V31, "v31" }, - { SYSZ_REG_F16, "f16" }, - { SYSZ_REG_F17, "f17" }, - { SYSZ_REG_F18, "f18" }, - { SYSZ_REG_F19, "f19" }, - { SYSZ_REG_F20, "f20" }, - { SYSZ_REG_F21, "f21" }, - { SYSZ_REG_F22, "f22" }, - { SYSZ_REG_F23, "f23" }, - { SYSZ_REG_F24, "f24" }, - { SYSZ_REG_F25, "f25" }, - { SYSZ_REG_F26, "f26" }, - { SYSZ_REG_F27, "f27" }, - { SYSZ_REG_F28, "f28" }, - { SYSZ_REG_F29, "f29" }, - { SYSZ_REG_F30, "f30" }, - { SYSZ_REG_F31, "f31" }, - { SYSZ_REG_F0Q, "f0q" }, - { SYSZ_REG_F4Q, "f4q" }, + {SystemZ_R0D, "0"}, {SystemZ_R1D, "1"}, {SystemZ_R2D, "2"}, + {SystemZ_R3D, "3"}, {SystemZ_R4D, "4"}, {SystemZ_R5D, "5"}, + {SystemZ_R6D, "6"}, {SystemZ_R7D, "7"}, {SystemZ_R8D, "8"}, + {SystemZ_R9D, "9"}, {SystemZ_R10D, "10"}, {SystemZ_R11D, "11"}, + {SystemZ_R12D, "12"}, {SystemZ_R13D, "13"}, {SystemZ_R14D, "14"}, + {SystemZ_R15D, "15"}, {SystemZ_R0L, "0"}, {SystemZ_R1L, "1"}, + {SystemZ_R2L, "2"}, {SystemZ_R3L, "3"}, {SystemZ_R4L, "4"}, + {SystemZ_R5L, "5"}, {SystemZ_R6L, "6"}, {SystemZ_R7L, "7"}, + {SystemZ_R8L, "8"}, {SystemZ_R9L, "9"}, {SystemZ_R10L, "10"}, + {SystemZ_R11L, "11"}, {SystemZ_R12L, "12"}, {SystemZ_R13L, "13"}, + {SystemZ_R14L, "14"}, {SystemZ_R15L, "15"}, {SystemZ_R0H, "0"}, + {SystemZ_R1H, "1"}, {SystemZ_R2H, "2"}, {SystemZ_R3H, "3"}, + {SystemZ_R4H, "4"}, {SystemZ_R5H, "5"}, {SystemZ_R6H, "6"}, + {SystemZ_R7H, "7"}, {SystemZ_R8H, "8"}, {SystemZ_R9H, "9"}, + {SystemZ_R10H, "10"}, {SystemZ_R11H, "11"}, {SystemZ_R12H, "12"}, + {SystemZ_R13H, "13"}, {SystemZ_R14H, "14"}, {SystemZ_R15H, "15"}, + {SystemZ_R0Q, "0"}, {SystemZ_R2Q, "2"}, {SystemZ_R4Q, "4"}, + {SystemZ_R6Q, "6"}, {SystemZ_R8Q, "8"}, {SystemZ_R10Q, "10"}, + {SystemZ_R12Q, "12"}, {SystemZ_R14Q, "14"}, {SystemZ_CC, "cc"}, + {SystemZ_F0D, "f0"}, {SystemZ_F1D, "f1"}, {SystemZ_F2D, "f2"}, + {SystemZ_F3D, "f3"}, {SystemZ_F4D, "f4"}, {SystemZ_F5D, "f5"}, + {SystemZ_F6D, "f6"}, {SystemZ_F7D, "f7"}, {SystemZ_F8D, "f8"}, + {SystemZ_F9D, "f9"}, {SystemZ_F10D, "f10"}, {SystemZ_F11D, "f11"}, + {SystemZ_F12D, "f12"}, {SystemZ_F13D, "f13"}, {SystemZ_F14D, "f14"}, + {SystemZ_F15D, "f15"}, {SystemZ_R0L, "r0l"}, {SystemZ_A0, "a0"}, + {SystemZ_A1, "a1"}, {SystemZ_A2, "a2"}, {SystemZ_A3, "a3"}, + {SystemZ_A4, "a4"}, {SystemZ_A5, "a5"}, {SystemZ_A6, "a6"}, + {SystemZ_A7, "a7"}, {SystemZ_A8, "a8"}, {SystemZ_A9, "a9"}, + {SystemZ_A10, "a10"}, {SystemZ_A11, "a11"}, {SystemZ_A12, "a12"}, + {SystemZ_A13, "a13"}, {SystemZ_A14, "a14"}, {SystemZ_A15, "a15"}, + {SystemZ_C0, "c0"}, {SystemZ_C1, "c1"}, {SystemZ_C2, "c2"}, + {SystemZ_C3, "c3"}, {SystemZ_C4, "c4"}, {SystemZ_C5, "c5"}, + {SystemZ_C6, "c6"}, {SystemZ_C7, "c7"}, {SystemZ_C8, "c8"}, + {SystemZ_C9, "c9"}, {SystemZ_C10, "c10"}, {SystemZ_C11, "c11"}, + {SystemZ_C12, "c12"}, {SystemZ_C13, "c13"}, {SystemZ_C14, "c14"}, + {SystemZ_C15, "c15"}, {SystemZ_V0, "v0"}, {SystemZ_V1, "v1"}, + {SystemZ_V2, "v2"}, {SystemZ_V3, "v3"}, {SystemZ_V4, "v4"}, + {SystemZ_V5, "v5"}, {SystemZ_V6, "v6"}, {SystemZ_V7, "v7"}, + {SystemZ_V8, "v8"}, {SystemZ_V9, "v9"}, {SystemZ_V10, "v10"}, + {SystemZ_V11, "v11"}, {SystemZ_V12, "v12"}, {SystemZ_V13, "v13"}, + {SystemZ_V14, "v14"}, {SystemZ_V15, "v15"}, {SystemZ_V16, "v16"}, + {SystemZ_V17, "v17"}, {SystemZ_V18, "v18"}, {SystemZ_V19, "v19"}, + {SystemZ_V20, "v20"}, {SystemZ_V21, "v21"}, {SystemZ_V22, "v22"}, + {SystemZ_V23, "v23"}, {SystemZ_V24, "v24"}, {SystemZ_V25, "v25"}, + {SystemZ_V26, "v26"}, {SystemZ_V27, "v27"}, {SystemZ_V28, "v28"}, + {SystemZ_V29, "v29"}, {SystemZ_V30, "v30"}, {SystemZ_V31, "v31"}, + {SystemZ_F16D, "f16"}, {SystemZ_F17D, "f17"}, {SystemZ_F18D, "f18"}, + {SystemZ_F19D, "f19"}, {SystemZ_F20D, "f20"}, {SystemZ_F21D, "f21"}, + {SystemZ_F22D, "f22"}, {SystemZ_F23D, "f23"}, {SystemZ_F24D, "f24"}, + {SystemZ_F25D, "f25"}, {SystemZ_F26D, "f26"}, {SystemZ_F27D, "f27"}, + {SystemZ_F28D, "f28"}, {SystemZ_F29D, "f29"}, {SystemZ_F30D, "f30"}, + {SystemZ_F31D, "f31"}, {SystemZ_F0Q, "f0q"}, {SystemZ_F4Q, "f4q"}, }; #endif -const char *SystemZ_reg_name(csh handle, unsigned int reg) -{ +const char *SystemZ_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; + for (int i = 0; i < ARR_SIZE(reg_name_maps); i++) { + if (reg_name_maps[i].id == reg) { + return reg_name_maps[i].name; + } + } - return reg_name_maps[reg].name; + // invalid + return NULL; #else - return NULL; + return NULL; #endif } static const insn_map insns[] = { - // dummy item - { - 0, 0, + // dummy item + {0, + 0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif - }, + }, #include "SystemZMappingInsn.inc" }; // given internal insn id, return public instruction info -void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) -{ - unsigned short i; +void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { + unsigned short i; - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; - if (h->detail) { + if (h->detail) { #ifndef CAPSTONE_DIET - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + memcpy(insn->detail->regs_read, insns[i].regs_use, + sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = + (uint8_t)count_positive(insns[i].regs_use); - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + memcpy(insn->detail->regs_write, insns[i].regs_mod, + sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = + (uint8_t)count_positive(insns[i].regs_mod); - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = SYSZ_GRP_JUMP; - insn->detail->groups_count++; - } + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = SYSZ_GRP_JUMP; + insn->detail->groups_count++; + } #endif - } - } + } + } } #ifndef CAPSTONE_DIET static const name_map insn_name_maps[] = { - { SYSZ_INS_INVALID, NULL }, + {SYSZ_INS_INVALID, NULL}, #include "SystemZGenInsnNameMaps.inc" }; // special alias insn -static const name_map alias_insn_names[] = { - { 0, NULL } -}; +static const name_map alias_insn_names[] = {{0, NULL}}; #endif -const char *SystemZ_insn_name(csh handle, unsigned int id) -{ +const char *SystemZ_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - unsigned int i; + unsigned int i; - if (id >= SYSZ_INS_ENDING) - return NULL; + if (id >= SYSZ_INS_ENDING) + return NULL; - // handle special alias first - for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { - if (alias_insn_names[i].id == id) - return alias_insn_names[i].name; - } + // handle special alias first + for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { + if (alias_insn_names[i].id == id) + return alias_insn_names[i].name; + } - return insn_name_maps[id].name; + return insn_name_maps[id].name; #else - return NULL; + return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { - // generic groups - { SYSZ_GRP_INVALID, NULL }, - { SYSZ_GRP_JUMP, "jump" }, + // generic groups + {SYSZ_GRP_INVALID, NULL}, + {SYSZ_GRP_JUMP, "jump"}, - // architecture-specific groups - { SYSZ_GRP_DFPPACKEDCONVERSION, "dfppackedconversion" }, - { SYSZ_GRP_DFPZONEDCONVERSION, "dfpzonedconversion" }, - { SYSZ_GRP_DISTINCTOPS, "distinctops" }, - { SYSZ_GRP_ENHANCEDDAT2, "enhanceddat2" }, - { SYSZ_GRP_EXECUTIONHINT, "executionhint" }, - { SYSZ_GRP_FPEXTENSION, "fpextension" }, - { SYSZ_GRP_GUARDEDSTORAGE, "guardedstorage" }, - { SYSZ_GRP_HIGHWORD, "highword" }, - { SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, "insertreferencebitsmultiple" }, - { SYSZ_GRP_INTERLOCKEDACCESS1, "interlockedaccess1" }, - { SYSZ_GRP_LOADANDTRAP, "loadandtrap" }, - { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, "loadandzerorightmostbyte" }, - { SYSZ_GRP_LOADSTOREONCOND, "loadstoreoncond" }, - { SYSZ_GRP_LOADSTOREONCOND2, "loadstoreoncond2" }, - { SYSZ_GRP_MESSAGESECURITYASSIST3, "messagesecurityassist3" }, - { SYSZ_GRP_MESSAGESECURITYASSIST4, "messagesecurityassist4" }, - { SYSZ_GRP_MESSAGESECURITYASSIST5, "messagesecurityassist5" }, - { SYSZ_GRP_MESSAGESECURITYASSIST7, "messagesecurityassist7" }, - { SYSZ_GRP_MESSAGESECURITYASSIST8, "messagesecurityassist8" }, - { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, "miscellaneousextensions" }, - { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, "miscellaneousextensions2" }, - { SYSZ_GRP_POPULATIONCOUNT, "populationcount" }, - { SYSZ_GRP_PROCESSORASSIST, "processorassist" }, - { SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, "resetreferencebitsmultiple" }, - { SYSZ_GRP_TRANSACTIONALEXECUTION, "transactionalexecution" }, - { SYSZ_GRP_VECTOR, "vector" }, - { SYSZ_GRP_VECTORENHANCEMENTS1, "vectorenhancements1" }, - { SYSZ_GRP_VECTORPACKEDDECIMAL, "vectorpackeddecimal" }, + // architecture-specific groups + {SYSZ_GRP_DFPPACKEDCONVERSION, "dfppackedconversion"}, + {SYSZ_GRP_DFPZONEDCONVERSION, "dfpzonedconversion"}, + {SYSZ_GRP_DISTINCTOPS, "distinctops"}, + {SYSZ_GRP_ENHANCEDDAT2, "enhanceddat2"}, + {SYSZ_GRP_EXECUTIONHINT, "executionhint"}, + {SYSZ_GRP_FPEXTENSION, "fpextension"}, + {SYSZ_GRP_GUARDEDSTORAGE, "guardedstorage"}, + {SYSZ_GRP_HIGHWORD, "highword"}, + {SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, "insertreferencebitsmultiple"}, + {SYSZ_GRP_INTERLOCKEDACCESS1, "interlockedaccess1"}, + {SYSZ_GRP_LOADANDTRAP, "loadandtrap"}, + {SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, "loadandzerorightmostbyte"}, + {SYSZ_GRP_LOADSTOREONCOND, "loadstoreoncond"}, + {SYSZ_GRP_LOADSTOREONCOND2, "loadstoreoncond2"}, + {SYSZ_GRP_MESSAGESECURITYASSIST3, "messagesecurityassist3"}, + {SYSZ_GRP_MESSAGESECURITYASSIST4, "messagesecurityassist4"}, + {SYSZ_GRP_MESSAGESECURITYASSIST5, "messagesecurityassist5"}, + {SYSZ_GRP_MESSAGESECURITYASSIST7, "messagesecurityassist7"}, + {SYSZ_GRP_MESSAGESECURITYASSIST8, "messagesecurityassist8"}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, "miscellaneousextensions"}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, "miscellaneousextensions2"}, + {SYSZ_GRP_POPULATIONCOUNT, "populationcount"}, + {SYSZ_GRP_PROCESSORASSIST, "processorassist"}, + {SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, "resetreferencebitsmultiple"}, + {SYSZ_GRP_TRANSACTIONALEXECUTION, "transactionalexecution"}, + {SYSZ_GRP_VECTOR, "vector"}, + {SYSZ_GRP_VECTORENHANCEMENTS1, "vectorenhancements1"}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, "vectorpackeddecimal"}, }; #endif -const char *SystemZ_group_name(csh handle, unsigned int id) -{ +const char *SystemZ_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else - return NULL; + return NULL; #endif } // map internal raw register to 'public' register -sysz_reg SystemZ_map_register(unsigned int r) -{ - static const unsigned int map[] = { 0, - /* SystemZ_CC = 1 */ SYSZ_REG_CC, - /* SystemZ_A0 = 2 */ SYSZ_REG_A0, - /* SystemZ_A1 = 3 */ SYSZ_REG_A1, - /* SystemZ_A2 = 4 */ SYSZ_REG_A2, - /* SystemZ_A3 = 5 */ SYSZ_REG_A3, - /* SystemZ_A4 = 6 */ SYSZ_REG_A4, - /* SystemZ_A5 = 7 */ SYSZ_REG_A5, - /* SystemZ_A6 = 8 */ SYSZ_REG_A6, - /* SystemZ_A7 = 9 */ SYSZ_REG_A7, - /* SystemZ_A8 = 10 */ SYSZ_REG_A8, - /* SystemZ_A9 = 11 */ SYSZ_REG_A9, - /* SystemZ_A10 = 12 */ SYSZ_REG_A10, - /* SystemZ_A11 = 13 */ SYSZ_REG_A11, - /* SystemZ_A12 = 14 */ SYSZ_REG_A12, - /* SystemZ_A13 = 15 */ SYSZ_REG_A13, - /* SystemZ_A14 = 16 */ SYSZ_REG_A14, - /* SystemZ_A15 = 17 */ SYSZ_REG_A15, - /* SystemZ_C0 = 18 */ SYSZ_REG_C0, - /* SystemZ_C1 = 19 */ SYSZ_REG_C1, - /* SystemZ_C2 = 20 */ SYSZ_REG_C2, - /* SystemZ_C3 = 21 */ SYSZ_REG_C3, - /* SystemZ_C4 = 22 */ SYSZ_REG_C4, - /* SystemZ_C5 = 23 */ SYSZ_REG_C5, - /* SystemZ_C6 = 24 */ SYSZ_REG_C6, - /* SystemZ_C7 = 25 */ SYSZ_REG_C7, - /* SystemZ_C8 = 26 */ SYSZ_REG_C8, - /* SystemZ_C9 = 27 */ SYSZ_REG_C9, - /* SystemZ_C10 = 28 */ SYSZ_REG_C10, - /* SystemZ_C11 = 29 */ SYSZ_REG_C11, - /* SystemZ_C12 = 30 */ SYSZ_REG_C12, - /* SystemZ_C13 = 31 */ SYSZ_REG_C13, - /* SystemZ_C14 = 32 */ SYSZ_REG_C14, - /* SystemZ_C15 = 33 */ SYSZ_REG_C15, - /* SystemZ_V0 = 34 */ SYSZ_REG_V0, - /* SystemZ_V1 = 35 */ SYSZ_REG_V1, - /* SystemZ_V2 = 36 */ SYSZ_REG_V2, - /* SystemZ_V3 = 37 */ SYSZ_REG_V3, - /* SystemZ_V4 = 38 */ SYSZ_REG_V4, - /* SystemZ_V5 = 39 */ SYSZ_REG_V5, - /* SystemZ_V6 = 40 */ SYSZ_REG_V6, - /* SystemZ_V7 = 41 */ SYSZ_REG_V7, - /* SystemZ_V8 = 42 */ SYSZ_REG_V8, - /* SystemZ_V9 = 43 */ SYSZ_REG_V9, - /* SystemZ_V10 = 44 */ SYSZ_REG_V10, - /* SystemZ_V11 = 45 */ SYSZ_REG_V11, - /* SystemZ_V12 = 46 */ SYSZ_REG_V12, - /* SystemZ_V13 = 47 */ SYSZ_REG_V13, - /* SystemZ_V14 = 48 */ SYSZ_REG_V14, - /* SystemZ_V15 = 49 */ SYSZ_REG_V15, - /* SystemZ_V16 = 50 */ SYSZ_REG_V16, - /* SystemZ_V17 = 51 */ SYSZ_REG_V17, - /* SystemZ_V18 = 52 */ SYSZ_REG_V18, - /* SystemZ_V19 = 53 */ SYSZ_REG_V19, - /* SystemZ_V20 = 54 */ SYSZ_REG_V20, - /* SystemZ_V21 = 55 */ SYSZ_REG_V21, - /* SystemZ_V22 = 56 */ SYSZ_REG_V22, - /* SystemZ_V23 = 57 */ SYSZ_REG_V23, - /* SystemZ_V24 = 58 */ SYSZ_REG_V24, - /* SystemZ_V25 = 59 */ SYSZ_REG_V25, - /* SystemZ_V26 = 60 */ SYSZ_REG_V26, - /* SystemZ_V27 = 61 */ SYSZ_REG_V27, - /* SystemZ_V28 = 62 */ SYSZ_REG_V28, - /* SystemZ_V29 = 63 */ SYSZ_REG_V29, - /* SystemZ_V30 = 64 */ SYSZ_REG_V30, - /* SystemZ_V31 = 65 */ SYSZ_REG_V31, - /* SystemZ_F0D = 66 */ SYSZ_REG_F0, - /* SystemZ_F1D = 67 */ SYSZ_REG_F1, - /* SystemZ_F2D = 68 */ SYSZ_REG_F2, - /* SystemZ_F3D = 69 */ SYSZ_REG_F3, - /* SystemZ_F4D = 70 */ SYSZ_REG_F4, - /* SystemZ_F5D = 71 */ SYSZ_REG_F5, - /* SystemZ_F6D = 72 */ SYSZ_REG_F6, - /* SystemZ_F7D = 73 */ SYSZ_REG_F7, - /* SystemZ_F8D = 74 */ SYSZ_REG_F8, - /* SystemZ_F9D = 75 */ SYSZ_REG_F9, - /* SystemZ_F10D = 76 */ SYSZ_REG_F10, - /* SystemZ_F11D = 77 */ SYSZ_REG_F11, - /* SystemZ_F12D = 78 */ SYSZ_REG_F12, - /* SystemZ_F13D = 79 */ SYSZ_REG_F13, - /* SystemZ_F14D = 80 */ SYSZ_REG_F14, - /* SystemZ_F15D = 81 */ SYSZ_REG_F15, - /* SystemZ_F16D = 82 */ SYSZ_REG_F16, - /* SystemZ_F17D = 83 */ SYSZ_REG_F17, - /* SystemZ_F18D = 84 */ SYSZ_REG_F18, - /* SystemZ_F19D = 85 */ SYSZ_REG_F19, - /* SystemZ_F20D = 86 */ SYSZ_REG_F20, - /* SystemZ_F21D = 87 */ SYSZ_REG_F21, - /* SystemZ_F22D = 88 */ SYSZ_REG_F22, - /* SystemZ_F23D = 89 */ SYSZ_REG_F23, - /* SystemZ_F24D = 90 */ SYSZ_REG_F24, - /* SystemZ_F25D = 91 */ SYSZ_REG_F25, - /* SystemZ_F26D = 92 */ SYSZ_REG_F26, - /* SystemZ_F27D = 93 */ SYSZ_REG_F27, - /* SystemZ_F28D = 94 */ SYSZ_REG_F28, - /* SystemZ_F29D = 95 */ SYSZ_REG_F29, - /* SystemZ_F30D = 96 */ SYSZ_REG_F30, - /* SystemZ_F31D = 97 */ SYSZ_REG_F31, - /* SystemZ_F0Q = 98 */ SYSZ_REG_F0, - /* SystemZ_F1Q = 99 */ SYSZ_REG_F1, - /* SystemZ_F4Q = 100 */ SYSZ_REG_F4, - /* SystemZ_F5Q = 101 */ SYSZ_REG_F5, - /* SystemZ_F8Q = 102 */ SYSZ_REG_F8, - /* SystemZ_F9Q = 103 */ SYSZ_REG_F9, - /* SystemZ_F12Q = 104 */ SYSZ_REG_F12, - /* SystemZ_F13Q = 105 */ SYSZ_REG_F13, - /* SystemZ_F0S = 106 */ SYSZ_REG_F0, - /* SystemZ_F1S = 107 */ SYSZ_REG_F1, - /* SystemZ_F2S = 108 */ SYSZ_REG_F2, - /* SystemZ_F3S = 109 */ SYSZ_REG_F3, - /* SystemZ_F4S = 110 */ SYSZ_REG_F4, - /* SystemZ_F5S = 111 */ SYSZ_REG_F5, - /* SystemZ_F6S = 112 */ SYSZ_REG_F6, - /* SystemZ_F7S = 113 */ SYSZ_REG_F7, - /* SystemZ_F8S = 114 */ SYSZ_REG_F8, - /* SystemZ_F9S = 115 */ SYSZ_REG_F9, - /* SystemZ_F10S = 116 */ SYSZ_REG_F10, - /* SystemZ_F11S = 117 */ SYSZ_REG_F11, - /* SystemZ_F12S = 118 */ SYSZ_REG_F12, - /* SystemZ_F13S = 119 */ SYSZ_REG_F13, - /* SystemZ_F14S = 120 */ SYSZ_REG_F14, - /* SystemZ_F15S = 121 */ SYSZ_REG_F15, - /* SystemZ_F16S = 122 */ SYSZ_REG_F16, - /* SystemZ_F17S = 123 */ SYSZ_REG_F17, - /* SystemZ_F18S = 124 */ SYSZ_REG_F18, - /* SystemZ_F19S = 125 */ SYSZ_REG_F19, - /* SystemZ_F20S = 126 */ SYSZ_REG_F20, - /* SystemZ_F21S = 127 */ SYSZ_REG_F21, - /* SystemZ_F22S = 128 */ SYSZ_REG_F22, - /* SystemZ_F23S = 129 */ SYSZ_REG_F23, - /* SystemZ_F24S = 130 */ SYSZ_REG_F24, - /* SystemZ_F25S = 131 */ SYSZ_REG_F25, - /* SystemZ_F26S = 132 */ SYSZ_REG_F26, - /* SystemZ_F27S = 133 */ SYSZ_REG_F27, - /* SystemZ_F28S = 134 */ SYSZ_REG_F28, - /* SystemZ_F29S = 135 */ SYSZ_REG_F29, - /* SystemZ_F30S = 136 */ SYSZ_REG_F30, - /* SystemZ_F31S = 137 */ SYSZ_REG_F31, - /* SystemZ_R0D = 138 */ SYSZ_REG_0, - /* SystemZ_R1D = 139 */ SYSZ_REG_1, - /* SystemZ_R2D = 140 */ SYSZ_REG_2, - /* SystemZ_R3D = 141 */ SYSZ_REG_3, - /* SystemZ_R4D = 142 */ SYSZ_REG_4, - /* SystemZ_R5D = 143 */ SYSZ_REG_5, - /* SystemZ_R6D = 144 */ SYSZ_REG_6, - /* SystemZ_R7D = 145 */ SYSZ_REG_7, - /* SystemZ_R8D = 146 */ SYSZ_REG_8, - /* SystemZ_R9D = 147 */ SYSZ_REG_9, - /* SystemZ_R10D = 148 */ SYSZ_REG_10, - /* SystemZ_R11D = 149 */ SYSZ_REG_11, - /* SystemZ_R12D = 150 */ SYSZ_REG_12, - /* SystemZ_R13D = 151 */ SYSZ_REG_13, - /* SystemZ_R14D = 152 */ SYSZ_REG_14, - /* SystemZ_R15D = 153 */ SYSZ_REG_15, - /* SystemZ_R0H = 154 */ SYSZ_REG_0, - /* SystemZ_R1H = 155 */ SYSZ_REG_1, - /* SystemZ_R2H = 156 */ SYSZ_REG_2, - /* SystemZ_R3H = 157 */ SYSZ_REG_3, - /* SystemZ_R4H = 158 */ SYSZ_REG_4, - /* SystemZ_R5H = 159 */ SYSZ_REG_5, - /* SystemZ_R6H = 160 */ SYSZ_REG_6, - /* SystemZ_R7H = 161 */ SYSZ_REG_7, - /* SystemZ_R8H = 162 */ SYSZ_REG_8, - /* SystemZ_R9H = 163 */ SYSZ_REG_9, - /* SystemZ_R10H = 164 */ SYSZ_REG_10, - /* SystemZ_R11H = 165 */ SYSZ_REG_11, - /* SystemZ_R12H = 166 */ SYSZ_REG_12, - /* SystemZ_R13H = 167 */ SYSZ_REG_13, - /* SystemZ_R14H = 168 */ SYSZ_REG_14, - /* SystemZ_R15H = 169 */ SYSZ_REG_15, - /* SystemZ_R0L = 170 */ SYSZ_REG_0, - /* SystemZ_R1L = 171 */ SYSZ_REG_1, - /* SystemZ_R2L = 172 */ SYSZ_REG_2, - /* SystemZ_R3L = 173 */ SYSZ_REG_3, - /* SystemZ_R4L = 174 */ SYSZ_REG_4, - /* SystemZ_R5L = 175 */ SYSZ_REG_5, - /* SystemZ_R6L = 176 */ SYSZ_REG_6, - /* SystemZ_R7L = 177 */ SYSZ_REG_7, - /* SystemZ_R8L = 178 */ SYSZ_REG_8, - /* SystemZ_R9L = 179 */ SYSZ_REG_9, - /* SystemZ_R10L = 180 */ SYSZ_REG_10, - /* SystemZ_R11L = 181 */ SYSZ_REG_11, - /* SystemZ_R12L = 182 */ SYSZ_REG_12, - /* SystemZ_R13L = 183 */ SYSZ_REG_13, - /* SystemZ_R14L = 184 */ SYSZ_REG_14, - /* SystemZ_R15L = 185 */ SYSZ_REG_15, - /* SystemZ_R0Q = 186 */ SYSZ_REG_0, - /* SystemZ_R2Q = 187 */ SYSZ_REG_2, - /* SystemZ_R4Q = 188 */ SYSZ_REG_4, - /* SystemZ_R6Q = 189 */ SYSZ_REG_6, - /* SystemZ_R8Q = 190 */ SYSZ_REG_8, - /* SystemZ_R10Q = 191 */ SYSZ_REG_10, - /* SystemZ_R12Q = 192 */ SYSZ_REG_12, - /* SystemZ_R14Q = 193 */ SYSZ_REG_14, - }; +sysz_reg SystemZ_map_register(unsigned int r) { + return r; + static const unsigned int map[] = { + 0, + /* SystemZ_CC = 1 */ SYSZ_REG_CC, + /* SystemZ_A0 = 2 */ SYSZ_REG_A0, + /* SystemZ_A1 = 3 */ SYSZ_REG_A1, + /* SystemZ_A2 = 4 */ SYSZ_REG_A2, + /* SystemZ_A3 = 5 */ SYSZ_REG_A3, + /* SystemZ_A4 = 6 */ SYSZ_REG_A4, + /* SystemZ_A5 = 7 */ SYSZ_REG_A5, + /* SystemZ_A6 = 8 */ SYSZ_REG_A6, + /* SystemZ_A7 = 9 */ SYSZ_REG_A7, + /* SystemZ_A8 = 10 */ SYSZ_REG_A8, + /* SystemZ_A9 = 11 */ SYSZ_REG_A9, + /* SystemZ_A10 = 12 */ SYSZ_REG_A10, + /* SystemZ_A11 = 13 */ SYSZ_REG_A11, + /* SystemZ_A12 = 14 */ SYSZ_REG_A12, + /* SystemZ_A13 = 15 */ SYSZ_REG_A13, + /* SystemZ_A14 = 16 */ SYSZ_REG_A14, + /* SystemZ_A15 = 17 */ SYSZ_REG_A15, + /* SystemZ_C0 = 18 */ SYSZ_REG_C0, + /* SystemZ_C1 = 19 */ SYSZ_REG_C1, + /* SystemZ_C2 = 20 */ SYSZ_REG_C2, + /* SystemZ_C3 = 21 */ SYSZ_REG_C3, + /* SystemZ_C4 = 22 */ SYSZ_REG_C4, + /* SystemZ_C5 = 23 */ SYSZ_REG_C5, + /* SystemZ_C6 = 24 */ SYSZ_REG_C6, + /* SystemZ_C7 = 25 */ SYSZ_REG_C7, + /* SystemZ_C8 = 26 */ SYSZ_REG_C8, + /* SystemZ_C9 = 27 */ SYSZ_REG_C9, + /* SystemZ_C10 = 28 */ SYSZ_REG_C10, + /* SystemZ_C11 = 29 */ SYSZ_REG_C11, + /* SystemZ_C12 = 30 */ SYSZ_REG_C12, + /* SystemZ_C13 = 31 */ SYSZ_REG_C13, + /* SystemZ_C14 = 32 */ SYSZ_REG_C14, + /* SystemZ_C15 = 33 */ SYSZ_REG_C15, + /* SystemZ_V0 = 34 */ SYSZ_REG_V0, + /* SystemZ_V1 = 35 */ SYSZ_REG_V1, + /* SystemZ_V2 = 36 */ SYSZ_REG_V2, + /* SystemZ_V3 = 37 */ SYSZ_REG_V3, + /* SystemZ_V4 = 38 */ SYSZ_REG_V4, + /* SystemZ_V5 = 39 */ SYSZ_REG_V5, + /* SystemZ_V6 = 40 */ SYSZ_REG_V6, + /* SystemZ_V7 = 41 */ SYSZ_REG_V7, + /* SystemZ_V8 = 42 */ SYSZ_REG_V8, + /* SystemZ_V9 = 43 */ SYSZ_REG_V9, + /* SystemZ_V10 = 44 */ SYSZ_REG_V10, + /* SystemZ_V11 = 45 */ SYSZ_REG_V11, + /* SystemZ_V12 = 46 */ SYSZ_REG_V12, + /* SystemZ_V13 = 47 */ SYSZ_REG_V13, + /* SystemZ_V14 = 48 */ SYSZ_REG_V14, + /* SystemZ_V15 = 49 */ SYSZ_REG_V15, + /* SystemZ_V16 = 50 */ SYSZ_REG_V16, + /* SystemZ_V17 = 51 */ SYSZ_REG_V17, + /* SystemZ_V18 = 52 */ SYSZ_REG_V18, + /* SystemZ_V19 = 53 */ SYSZ_REG_V19, + /* SystemZ_V20 = 54 */ SYSZ_REG_V20, + /* SystemZ_V21 = 55 */ SYSZ_REG_V21, + /* SystemZ_V22 = 56 */ SYSZ_REG_V22, + /* SystemZ_V23 = 57 */ SYSZ_REG_V23, + /* SystemZ_V24 = 58 */ SYSZ_REG_V24, + /* SystemZ_V25 = 59 */ SYSZ_REG_V25, + /* SystemZ_V26 = 60 */ SYSZ_REG_V26, + /* SystemZ_V27 = 61 */ SYSZ_REG_V27, + /* SystemZ_V28 = 62 */ SYSZ_REG_V28, + /* SystemZ_V29 = 63 */ SYSZ_REG_V29, + /* SystemZ_V30 = 64 */ SYSZ_REG_V30, + /* SystemZ_V31 = 65 */ SYSZ_REG_V31, + /* SystemZ_F0D = 66 */ SYSZ_REG_F0, + /* SystemZ_F1D = 67 */ SYSZ_REG_F1, + /* SystemZ_F2D = 68 */ SYSZ_REG_F2, + /* SystemZ_F3D = 69 */ SYSZ_REG_F3, + /* SystemZ_F4D = 70 */ SYSZ_REG_F4, + /* SystemZ_F5D = 71 */ SYSZ_REG_F5, + /* SystemZ_F6D = 72 */ SYSZ_REG_F6, + /* SystemZ_F7D = 73 */ SYSZ_REG_F7, + /* SystemZ_F8D = 74 */ SYSZ_REG_F8, + /* SystemZ_F9D = 75 */ SYSZ_REG_F9, + /* SystemZ_F10D = 76 */ SYSZ_REG_F10, + /* SystemZ_F11D = 77 */ SYSZ_REG_F11, + /* SystemZ_F12D = 78 */ SYSZ_REG_F12, + /* SystemZ_F13D = 79 */ SYSZ_REG_F13, + /* SystemZ_F14D = 80 */ SYSZ_REG_F14, + /* SystemZ_F15D = 81 */ SYSZ_REG_F15, + /* SystemZ_F16D = 82 */ SYSZ_REG_F16, + /* SystemZ_F17D = 83 */ SYSZ_REG_F17, + /* SystemZ_F18D = 84 */ SYSZ_REG_F18, + /* SystemZ_F19D = 85 */ SYSZ_REG_F19, + /* SystemZ_F20D = 86 */ SYSZ_REG_F20, + /* SystemZ_F21D = 87 */ SYSZ_REG_F21, + /* SystemZ_F22D = 88 */ SYSZ_REG_F22, + /* SystemZ_F23D = 89 */ SYSZ_REG_F23, + /* SystemZ_F24D = 90 */ SYSZ_REG_F24, + /* SystemZ_F25D = 91 */ SYSZ_REG_F25, + /* SystemZ_F26D = 92 */ SYSZ_REG_F26, + /* SystemZ_F27D = 93 */ SYSZ_REG_F27, + /* SystemZ_F28D = 94 */ SYSZ_REG_F28, + /* SystemZ_F29D = 95 */ SYSZ_REG_F29, + /* SystemZ_F30D = 96 */ SYSZ_REG_F30, + /* SystemZ_F31D = 97 */ SYSZ_REG_F31, + /* SystemZ_F0Q = 98 */ SYSZ_REG_F0, + /* SystemZ_F1Q = 99 */ SYSZ_REG_F1, + /* SystemZ_F4Q = 100 */ SYSZ_REG_F4, + /* SystemZ_F5Q = 101 */ SYSZ_REG_F5, + /* SystemZ_F8Q = 102 */ SYSZ_REG_F8, + /* SystemZ_F9Q = 103 */ SYSZ_REG_F9, + /* SystemZ_F12Q = 104 */ SYSZ_REG_F12, + /* SystemZ_F13Q = 105 */ SYSZ_REG_F13, + /* SystemZ_F0S = 106 */ SYSZ_REG_F0, + /* SystemZ_F1S = 107 */ SYSZ_REG_F1, + /* SystemZ_F2S = 108 */ SYSZ_REG_F2, + /* SystemZ_F3S = 109 */ SYSZ_REG_F3, + /* SystemZ_F4S = 110 */ SYSZ_REG_F4, + /* SystemZ_F5S = 111 */ SYSZ_REG_F5, + /* SystemZ_F6S = 112 */ SYSZ_REG_F6, + /* SystemZ_F7S = 113 */ SYSZ_REG_F7, + /* SystemZ_F8S = 114 */ SYSZ_REG_F8, + /* SystemZ_F9S = 115 */ SYSZ_REG_F9, + /* SystemZ_F10S = 116 */ SYSZ_REG_F10, + /* SystemZ_F11S = 117 */ SYSZ_REG_F11, + /* SystemZ_F12S = 118 */ SYSZ_REG_F12, + /* SystemZ_F13S = 119 */ SYSZ_REG_F13, + /* SystemZ_F14S = 120 */ SYSZ_REG_F14, + /* SystemZ_F15S = 121 */ SYSZ_REG_F15, + /* SystemZ_F16S = 122 */ SYSZ_REG_F16, + /* SystemZ_F17S = 123 */ SYSZ_REG_F17, + /* SystemZ_F18S = 124 */ SYSZ_REG_F18, + /* SystemZ_F19S = 125 */ SYSZ_REG_F19, + /* SystemZ_F20S = 126 */ SYSZ_REG_F20, + /* SystemZ_F21S = 127 */ SYSZ_REG_F21, + /* SystemZ_F22S = 128 */ SYSZ_REG_F22, + /* SystemZ_F23S = 129 */ SYSZ_REG_F23, + /* SystemZ_F24S = 130 */ SYSZ_REG_F24, + /* SystemZ_F25S = 131 */ SYSZ_REG_F25, + /* SystemZ_F26S = 132 */ SYSZ_REG_F26, + /* SystemZ_F27S = 133 */ SYSZ_REG_F27, + /* SystemZ_F28S = 134 */ SYSZ_REG_F28, + /* SystemZ_F29S = 135 */ SYSZ_REG_F29, + /* SystemZ_F30S = 136 */ SYSZ_REG_F30, + /* SystemZ_F31S = 137 */ SYSZ_REG_F31, + /* SystemZ_R0D = 138 */ SYSZ_REG_0, + /* SystemZ_R1D = 139 */ SYSZ_REG_1, + /* SystemZ_R2D = 140 */ SYSZ_REG_2, + /* SystemZ_R3D = 141 */ SYSZ_REG_3, + /* SystemZ_R4D = 142 */ SYSZ_REG_4, + /* SystemZ_R5D = 143 */ SYSZ_REG_5, + /* SystemZ_R6D = 144 */ SYSZ_REG_6, + /* SystemZ_R7D = 145 */ SYSZ_REG_7, + /* SystemZ_R8D = 146 */ SYSZ_REG_8, + /* SystemZ_R9D = 147 */ SYSZ_REG_9, + /* SystemZ_R10D = 148 */ SYSZ_REG_10, + /* SystemZ_R11D = 149 */ SYSZ_REG_11, + /* SystemZ_R12D = 150 */ SYSZ_REG_12, + /* SystemZ_R13D = 151 */ SYSZ_REG_13, + /* SystemZ_R14D = 152 */ SYSZ_REG_14, + /* SystemZ_R15D = 153 */ SYSZ_REG_15, + /* SystemZ_R0H = 154 */ SYSZ_REG_0, + /* SystemZ_R1H = 155 */ SYSZ_REG_1, + /* SystemZ_R2H = 156 */ SYSZ_REG_2, + /* SystemZ_R3H = 157 */ SYSZ_REG_3, + /* SystemZ_R4H = 158 */ SYSZ_REG_4, + /* SystemZ_R5H = 159 */ SYSZ_REG_5, + /* SystemZ_R6H = 160 */ SYSZ_REG_6, + /* SystemZ_R7H = 161 */ SYSZ_REG_7, + /* SystemZ_R8H = 162 */ SYSZ_REG_8, + /* SystemZ_R9H = 163 */ SYSZ_REG_9, + /* SystemZ_R10H = 164 */ SYSZ_REG_10, + /* SystemZ_R11H = 165 */ SYSZ_REG_11, + /* SystemZ_R12H = 166 */ SYSZ_REG_12, + /* SystemZ_R13H = 167 */ SYSZ_REG_13, + /* SystemZ_R14H = 168 */ SYSZ_REG_14, + /* SystemZ_R15H = 169 */ SYSZ_REG_15, + /* SystemZ_R0L = 170 */ SYSZ_REG_0, + /* SystemZ_R1L = 171 */ SYSZ_REG_1, + /* SystemZ_R2L = 172 */ SYSZ_REG_2, + /* SystemZ_R3L = 173 */ SYSZ_REG_3, + /* SystemZ_R4L = 174 */ SYSZ_REG_4, + /* SystemZ_R5L = 175 */ SYSZ_REG_5, + /* SystemZ_R6L = 176 */ SYSZ_REG_6, + /* SystemZ_R7L = 177 */ SYSZ_REG_7, + /* SystemZ_R8L = 178 */ SYSZ_REG_8, + /* SystemZ_R9L = 179 */ SYSZ_REG_9, + /* SystemZ_R10L = 180 */ SYSZ_REG_10, + /* SystemZ_R11L = 181 */ SYSZ_REG_11, + /* SystemZ_R12L = 182 */ SYSZ_REG_12, + /* SystemZ_R13L = 183 */ SYSZ_REG_13, + /* SystemZ_R14L = 184 */ SYSZ_REG_14, + /* SystemZ_R15L = 185 */ SYSZ_REG_15, + /* SystemZ_R0Q = 186 */ SYSZ_REG_0, + /* SystemZ_R2Q = 187 */ SYSZ_REG_2, + /* SystemZ_R4Q = 188 */ SYSZ_REG_4, + /* SystemZ_R6Q = 189 */ SYSZ_REG_6, + /* SystemZ_R8Q = 190 */ SYSZ_REG_8, + /* SystemZ_R10Q = 191 */ SYSZ_REG_10, + /* SystemZ_R12Q = 192 */ SYSZ_REG_12, + /* SystemZ_R14Q = 193 */ SYSZ_REG_14, + }; - if (r < ARR_SIZE(map)) - return map[r]; + if (r < ARR_SIZE(map)) + return map[r]; - // cannot find this register - return 0; + // cannot find this register + return 0; } #endif diff --git a/arch/SystemZ/SystemZMapping.h b/arch/SystemZ/SystemZMapping.h index 9a6ceb356e..af79dc9eb1 100644 --- a/arch/SystemZ/SystemZMapping.h +++ b/arch/SystemZ/SystemZMapping.h @@ -20,4 +20,3 @@ const char *SystemZ_group_name(csh handle, unsigned int id); sysz_reg SystemZ_map_register(unsigned int r); #endif - diff --git a/arch/SystemZ/SystemZMappingInsn.inc b/arch/SystemZ/SystemZMappingInsn.inc index 949b65b6db..fe7d7b7192 100644 --- a/arch/SystemZ/SystemZMappingInsn.inc +++ b/arch/SystemZ/SystemZMappingInsn.inc @@ -1,14175 +1,23221 @@ // This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh -{ - SystemZ_A, SYSZ_INS_A, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AD, SYSZ_INS_AD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADB, SYSZ_INS_ADB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADBR, SYSZ_INS_ADBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADR, SYSZ_INS_ADR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADTR, SYSZ_INS_ADTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ADTRA, SYSZ_INS_ADTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AE, SYSZ_INS_AE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AEB, SYSZ_INS_AEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AEBR, SYSZ_INS_AEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AER, SYSZ_INS_AER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AFI, SYSZ_INS_AFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AG, SYSZ_INS_AG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGF, SYSZ_INS_AGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGFI, SYSZ_INS_AGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGFR, SYSZ_INS_AGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGH, SYSZ_INS_AGH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGHI, SYSZ_INS_AGHI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGHIK, SYSZ_INS_AGHIK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGR, SYSZ_INS_AGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGRK, SYSZ_INS_AGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AGSI, SYSZ_INS_AGSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AH, SYSZ_INS_AH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHHHR, SYSZ_INS_AHHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHHLR, SYSZ_INS_AHHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHI, SYSZ_INS_AHI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHIK, SYSZ_INS_AHIK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AHY, SYSZ_INS_AHY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AIH, SYSZ_INS_AIH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AL, SYSZ_INS_AL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALC, SYSZ_INS_ALC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALCG, SYSZ_INS_ALCG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALCGR, SYSZ_INS_ALCGR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALCR, SYSZ_INS_ALCR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALFI, SYSZ_INS_ALFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALG, SYSZ_INS_ALG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGF, SYSZ_INS_ALGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGFI, SYSZ_INS_ALGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGFR, SYSZ_INS_ALGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGHSIK, SYSZ_INS_ALGHSIK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGR, SYSZ_INS_ALGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGRK, SYSZ_INS_ALGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALGSI, SYSZ_INS_ALGSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALHHHR, SYSZ_INS_ALHHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALHHLR, SYSZ_INS_ALHHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALHSIK, SYSZ_INS_ALHSIK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALR, SYSZ_INS_ALR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALRK, SYSZ_INS_ALRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALSI, SYSZ_INS_ALSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALSIH, SYSZ_INS_ALSIH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALSIHN, SYSZ_INS_ALSIHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ALY, SYSZ_INS_ALY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AP, SYSZ_INS_AP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AR, SYSZ_INS_AR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ARK, SYSZ_INS_ARK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ASI, SYSZ_INS_ASI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AU, SYSZ_INS_AU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AUR, SYSZ_INS_AUR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AW, SYSZ_INS_AW, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AWR, SYSZ_INS_AWR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AXBR, SYSZ_INS_AXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AXR, SYSZ_INS_AXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AXTR, SYSZ_INS_AXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_AXTRA, SYSZ_INS_AXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_AY, SYSZ_INS_AY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_B, SYSZ_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAKR, SYSZ_INS_BAKR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BAL, SYSZ_INS_BAL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BALR, SYSZ_INS_BALR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BAS, SYSZ_INS_BAS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BASR, SYSZ_INS_BASR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BASSM, SYSZ_INS_BASSM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BAsmE, SYSZ_INS_BE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmH, SYSZ_INS_BH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmHE, SYSZ_INS_BHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmL, SYSZ_INS_BL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmLE, SYSZ_INS_BLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmLH, SYSZ_INS_BLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmM, SYSZ_INS_BM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNE, SYSZ_INS_BNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNH, SYSZ_INS_BNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNHE, SYSZ_INS_BNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNL, SYSZ_INS_BNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNLE, SYSZ_INS_BNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNLH, SYSZ_INS_BNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNM, SYSZ_INS_BNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNO, SYSZ_INS_BNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNP, SYSZ_INS_BNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmNZ, SYSZ_INS_BNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmO, SYSZ_INS_BO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmP, SYSZ_INS_BP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BAsmZ, SYSZ_INS_BZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BCAsm, SYSZ_INS_BC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BCRAsm, SYSZ_INS_BCR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BCT, SYSZ_INS_BCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BCTG, SYSZ_INS_BCTG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BCTGR, SYSZ_INS_BCTGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BCTR, SYSZ_INS_BCTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BI, SYSZ_INS_BI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmE, SYSZ_INS_BIE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmH, SYSZ_INS_BIH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmHE, SYSZ_INS_BIHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmL, SYSZ_INS_BIL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmLE, SYSZ_INS_BILE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmLH, SYSZ_INS_BILH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmM, SYSZ_INS_BIM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNE, SYSZ_INS_BINE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNH, SYSZ_INS_BINH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNHE, SYSZ_INS_BINHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNL, SYSZ_INS_BINL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNLE, SYSZ_INS_BINLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNLH, SYSZ_INS_BINLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNM, SYSZ_INS_BINM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNO, SYSZ_INS_BINO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNP, SYSZ_INS_BINP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmNZ, SYSZ_INS_BINZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmO, SYSZ_INS_BIO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmP, SYSZ_INS_BIP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BIAsmZ, SYSZ_INS_BIZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BICAsm, SYSZ_INS_BIC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 -#endif -}, -{ - SystemZ_BPP, SYSZ_INS_BPP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 -#endif -}, -{ - SystemZ_BPRP, SYSZ_INS_BPRP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 -#endif -}, -{ - SystemZ_BR, SYSZ_INS_BR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAS, SYSZ_INS_BRAS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BRASL, SYSZ_INS_BRASL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BRAsmE, SYSZ_INS_BER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmH, SYSZ_INS_BHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmHE, SYSZ_INS_BHER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmL, SYSZ_INS_BLR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmLE, SYSZ_INS_BLER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmLH, SYSZ_INS_BLHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmM, SYSZ_INS_BMR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNE, SYSZ_INS_BNER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNH, SYSZ_INS_BNHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNHE, SYSZ_INS_BNHER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNL, SYSZ_INS_BNLR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNLE, SYSZ_INS_BNLER, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNLH, SYSZ_INS_BNLHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNM, SYSZ_INS_BNMR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNO, SYSZ_INS_BNOR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNP, SYSZ_INS_BNPR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmNZ, SYSZ_INS_BNZR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmO, SYSZ_INS_BOR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmP, SYSZ_INS_BPR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRAsmZ, SYSZ_INS_BZR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_BRCAsm, SYSZ_INS_BRC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRCLAsm, SYSZ_INS_BRCL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRCT, SYSZ_INS_BRCT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRCTG, SYSZ_INS_BRCTG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRCTH, SYSZ_INS_BRCTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRXH, SYSZ_INS_BRXH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRXHG, SYSZ_INS_BRXHG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRXLE, SYSZ_INS_BRXLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BRXLG, SYSZ_INS_BRXLG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BSA, SYSZ_INS_BSA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BSG, SYSZ_INS_BSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_BSM, SYSZ_INS_BSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BXH, SYSZ_INS_BXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BXHG, SYSZ_INS_BXHG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BXLE, SYSZ_INS_BXLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_BXLEG, SYSZ_INS_BXLEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_C, SYSZ_INS_C, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CD, SYSZ_INS_CD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDB, SYSZ_INS_CDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDBR, SYSZ_INS_CDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDFBR, SYSZ_INS_CDFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDFBRA, SYSZ_INS_CDFBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDFR, SYSZ_INS_CDFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDFTR, SYSZ_INS_CDFTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGBR, SYSZ_INS_CDGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGBRA, SYSZ_INS_CDGBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGR, SYSZ_INS_CDGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGTR, SYSZ_INS_CDGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDGTRA, SYSZ_INS_CDGTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDLFBR, SYSZ_INS_CDLFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDLFTR, SYSZ_INS_CDLFTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDLGBR, SYSZ_INS_CDLGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDLGTR, SYSZ_INS_CDLGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDPT, SYSZ_INS_CDPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDR, SYSZ_INS_CDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDS, SYSZ_INS_CDS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDSG, SYSZ_INS_CDSG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDSTR, SYSZ_INS_CDSTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDSY, SYSZ_INS_CDSY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDTR, SYSZ_INS_CDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDUTR, SYSZ_INS_CDUTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CDZT, SYSZ_INS_CDZT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CE, SYSZ_INS_CE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEB, SYSZ_INS_CEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEBR, SYSZ_INS_CEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEDTR, SYSZ_INS_CEDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEFBR, SYSZ_INS_CEFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEFBRA, SYSZ_INS_CEFBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEFR, SYSZ_INS_CEFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEGBR, SYSZ_INS_CEGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEGBRA, SYSZ_INS_CEGBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEGR, SYSZ_INS_CEGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CELFBR, SYSZ_INS_CELFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CELGBR, SYSZ_INS_CELGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CER, SYSZ_INS_CER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CEXTR, SYSZ_INS_CEXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFC, SYSZ_INS_CFC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFDBR, SYSZ_INS_CFDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFDBRA, SYSZ_INS_CFDBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFDR, SYSZ_INS_CFDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFDTR, SYSZ_INS_CFDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFEBR, SYSZ_INS_CFEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFEBRA, SYSZ_INS_CFEBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFER, SYSZ_INS_CFER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFI, SYSZ_INS_CFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFXBR, SYSZ_INS_CFXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFXBRA, SYSZ_INS_CFXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFXR, SYSZ_INS_CFXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CFXTR, SYSZ_INS_CFXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CG, SYSZ_INS_CG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDBR, SYSZ_INS_CGDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDBRA, SYSZ_INS_CGDBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDR, SYSZ_INS_CGDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDTR, SYSZ_INS_CGDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGDTRA, SYSZ_INS_CGDTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGEBR, SYSZ_INS_CGEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGEBRA, SYSZ_INS_CGEBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGER, SYSZ_INS_CGER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGF, SYSZ_INS_CGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGFI, SYSZ_INS_CGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGFR, SYSZ_INS_CGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGFRL, SYSZ_INS_CGFRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGH, SYSZ_INS_CGH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGHI, SYSZ_INS_CGHI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGHRL, SYSZ_INS_CGHRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGHSI, SYSZ_INS_CGHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGIBAsm, SYSZ_INS_CGIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmE, SYSZ_INS_CGIBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmH, SYSZ_INS_CGIBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmHE, SYSZ_INS_CGIBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmL, SYSZ_INS_CGIBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmLE, SYSZ_INS_CGIBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmLH, SYSZ_INS_CGIBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNE, SYSZ_INS_CGIBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNH, SYSZ_INS_CGIBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNHE, SYSZ_INS_CGIBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNL, SYSZ_INS_CGIBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNLE, SYSZ_INS_CGIBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIBAsmNLH, SYSZ_INS_CGIBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGIJAsm, SYSZ_INS_CGIJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmE, SYSZ_INS_CGIJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmH, SYSZ_INS_CGIJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmHE, SYSZ_INS_CGIJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmL, SYSZ_INS_CGIJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmLE, SYSZ_INS_CGIJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmLH, SYSZ_INS_CGIJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNE, SYSZ_INS_CGIJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNH, SYSZ_INS_CGIJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNHE, SYSZ_INS_CGIJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNL, SYSZ_INS_CGIJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNLE, SYSZ_INS_CGIJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGIJAsmNLH, SYSZ_INS_CGIJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGITAsm, SYSZ_INS_CGIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmE, SYSZ_INS_CGITE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmH, SYSZ_INS_CGITH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmHE, SYSZ_INS_CGITHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmL, SYSZ_INS_CGITL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmLE, SYSZ_INS_CGITLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmLH, SYSZ_INS_CGITLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNE, SYSZ_INS_CGITNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNH, SYSZ_INS_CGITNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNHE, SYSZ_INS_CGITNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNL, SYSZ_INS_CGITNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNLE, SYSZ_INS_CGITNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGITAsmNLH, SYSZ_INS_CGITNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGR, SYSZ_INS_CGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRBAsm, SYSZ_INS_CGRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmE, SYSZ_INS_CGRBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmH, SYSZ_INS_CGRBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmHE, SYSZ_INS_CGRBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmL, SYSZ_INS_CGRBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmLE, SYSZ_INS_CGRBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmLH, SYSZ_INS_CGRBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNE, SYSZ_INS_CGRBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNH, SYSZ_INS_CGRBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNHE, SYSZ_INS_CGRBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNL, SYSZ_INS_CGRBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNLE, SYSZ_INS_CGRBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRBAsmNLH, SYSZ_INS_CGRBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CGRJAsm, SYSZ_INS_CGRJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmE, SYSZ_INS_CGRJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmH, SYSZ_INS_CGRJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmHE, SYSZ_INS_CGRJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmL, SYSZ_INS_CGRJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmLE, SYSZ_INS_CGRJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmLH, SYSZ_INS_CGRJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNE, SYSZ_INS_CGRJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNH, SYSZ_INS_CGRJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNHE, SYSZ_INS_CGRJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNL, SYSZ_INS_CGRJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNLE, SYSZ_INS_CGRJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRJAsmNLH, SYSZ_INS_CGRJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CGRL, SYSZ_INS_CGRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsm, SYSZ_INS_CGRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmE, SYSZ_INS_CGRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmH, SYSZ_INS_CGRTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmHE, SYSZ_INS_CGRTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmL, SYSZ_INS_CGRTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmLE, SYSZ_INS_CGRTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmLH, SYSZ_INS_CGRTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNE, SYSZ_INS_CGRTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNH, SYSZ_INS_CGRTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNHE, SYSZ_INS_CGRTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNL, SYSZ_INS_CGRTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNLE, SYSZ_INS_CGRTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGRTAsmNLH, SYSZ_INS_CGRTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXBR, SYSZ_INS_CGXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXBRA, SYSZ_INS_CGXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXR, SYSZ_INS_CGXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXTR, SYSZ_INS_CGXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CGXTRA, SYSZ_INS_CGXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CH, SYSZ_INS_CH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHF, SYSZ_INS_CHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHHR, SYSZ_INS_CHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHHSI, SYSZ_INS_CHHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHI, SYSZ_INS_CHI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHLR, SYSZ_INS_CHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHRL, SYSZ_INS_CHRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHSI, SYSZ_INS_CHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CHY, SYSZ_INS_CHY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CIBAsm, SYSZ_INS_CIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmE, SYSZ_INS_CIBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmH, SYSZ_INS_CIBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmHE, SYSZ_INS_CIBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmL, SYSZ_INS_CIBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmLE, SYSZ_INS_CIBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmLH, SYSZ_INS_CIBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNE, SYSZ_INS_CIBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNH, SYSZ_INS_CIBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNHE, SYSZ_INS_CIBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNL, SYSZ_INS_CIBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNLE, SYSZ_INS_CIBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIBAsmNLH, SYSZ_INS_CIBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CIH, SYSZ_INS_CIH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CIJAsm, SYSZ_INS_CIJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmE, SYSZ_INS_CIJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmH, SYSZ_INS_CIJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmHE, SYSZ_INS_CIJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmL, SYSZ_INS_CIJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmLE, SYSZ_INS_CIJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmLH, SYSZ_INS_CIJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNE, SYSZ_INS_CIJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNH, SYSZ_INS_CIJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNHE, SYSZ_INS_CIJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNL, SYSZ_INS_CIJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNLE, SYSZ_INS_CIJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CIJAsmNLH, SYSZ_INS_CIJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CITAsm, SYSZ_INS_CIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmE, SYSZ_INS_CITE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmH, SYSZ_INS_CITH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmHE, SYSZ_INS_CITHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmL, SYSZ_INS_CITL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmLE, SYSZ_INS_CITLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmLH, SYSZ_INS_CITLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNE, SYSZ_INS_CITNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNH, SYSZ_INS_CITNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNHE, SYSZ_INS_CITNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNL, SYSZ_INS_CITNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNLE, SYSZ_INS_CITNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CITAsmNLH, SYSZ_INS_CITNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CKSM, SYSZ_INS_CKSM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CL, SYSZ_INS_CL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLC, SYSZ_INS_CLC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLCL, SYSZ_INS_CLCL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLCLE, SYSZ_INS_CLCLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLCLU, SYSZ_INS_CLCLU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFDBR, SYSZ_INS_CLFDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFDTR, SYSZ_INS_CLFDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFEBR, SYSZ_INS_CLFEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFHSI, SYSZ_INS_CLFHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFI, SYSZ_INS_CLFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsm, SYSZ_INS_CLFIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmE, SYSZ_INS_CLFITE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmH, SYSZ_INS_CLFITH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmHE, SYSZ_INS_CLFITHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmL, SYSZ_INS_CLFITL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmLE, SYSZ_INS_CLFITLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmLH, SYSZ_INS_CLFITLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNE, SYSZ_INS_CLFITNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNH, SYSZ_INS_CLFITNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNHE, SYSZ_INS_CLFITNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNL, SYSZ_INS_CLFITNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNLE, SYSZ_INS_CLFITNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFITAsmNLH, SYSZ_INS_CLFITNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFXBR, SYSZ_INS_CLFXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLFXTR, SYSZ_INS_CLFXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLG, SYSZ_INS_CLG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGDBR, SYSZ_INS_CLGDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGDTR, SYSZ_INS_CLGDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGEBR, SYSZ_INS_CLGEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGF, SYSZ_INS_CLGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGFI, SYSZ_INS_CLGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGFR, SYSZ_INS_CLGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGFRL, SYSZ_INS_CLGFRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGHRL, SYSZ_INS_CLGHRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGHSI, SYSZ_INS_CLGHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGIBAsm, SYSZ_INS_CLGIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmE, SYSZ_INS_CLGIBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmH, SYSZ_INS_CLGIBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmHE, SYSZ_INS_CLGIBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmL, SYSZ_INS_CLGIBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmLE, SYSZ_INS_CLGIBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmLH, SYSZ_INS_CLGIBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNE, SYSZ_INS_CLGIBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNH, SYSZ_INS_CLGIBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNHE, SYSZ_INS_CLGIBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNL, SYSZ_INS_CLGIBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNLE, SYSZ_INS_CLGIBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIBAsmNLH, SYSZ_INS_CLGIBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGIJAsm, SYSZ_INS_CLGIJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmE, SYSZ_INS_CLGIJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmH, SYSZ_INS_CLGIJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmHE, SYSZ_INS_CLGIJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmL, SYSZ_INS_CLGIJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmLE, SYSZ_INS_CLGIJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmLH, SYSZ_INS_CLGIJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNE, SYSZ_INS_CLGIJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNH, SYSZ_INS_CLGIJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNHE, SYSZ_INS_CLGIJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNL, SYSZ_INS_CLGIJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNLE, SYSZ_INS_CLGIJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGIJAsmNLH, SYSZ_INS_CLGIJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGITAsm, SYSZ_INS_CLGIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmE, SYSZ_INS_CLGITE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmH, SYSZ_INS_CLGITH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmHE, SYSZ_INS_CLGITHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmL, SYSZ_INS_CLGITL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmLE, SYSZ_INS_CLGITLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmLH, SYSZ_INS_CLGITLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNE, SYSZ_INS_CLGITNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNH, SYSZ_INS_CLGITNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNHE, SYSZ_INS_CLGITNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNL, SYSZ_INS_CLGITNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNLE, SYSZ_INS_CLGITNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGITAsmNLH, SYSZ_INS_CLGITNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGR, SYSZ_INS_CLGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRBAsm, SYSZ_INS_CLGRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmE, SYSZ_INS_CLGRBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmH, SYSZ_INS_CLGRBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmHE, SYSZ_INS_CLGRBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmL, SYSZ_INS_CLGRBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmLE, SYSZ_INS_CLGRBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmLH, SYSZ_INS_CLGRBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNE, SYSZ_INS_CLGRBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNH, SYSZ_INS_CLGRBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNHE, SYSZ_INS_CLGRBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNL, SYSZ_INS_CLGRBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNLE, SYSZ_INS_CLGRBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRBAsmNLH, SYSZ_INS_CLGRBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLGRJAsm, SYSZ_INS_CLGRJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmE, SYSZ_INS_CLGRJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmH, SYSZ_INS_CLGRJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmHE, SYSZ_INS_CLGRJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmL, SYSZ_INS_CLGRJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmLE, SYSZ_INS_CLGRJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmLH, SYSZ_INS_CLGRJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNE, SYSZ_INS_CLGRJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNH, SYSZ_INS_CLGRJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNHE, SYSZ_INS_CLGRJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNL, SYSZ_INS_CLGRJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNLE, SYSZ_INS_CLGRJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRJAsmNLH, SYSZ_INS_CLGRJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLGRL, SYSZ_INS_CLGRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsm, SYSZ_INS_CLGRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmE, SYSZ_INS_CLGRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmH, SYSZ_INS_CLGRTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmHE, SYSZ_INS_CLGRTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmL, SYSZ_INS_CLGRTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmLE, SYSZ_INS_CLGRTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmLH, SYSZ_INS_CLGRTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNE, SYSZ_INS_CLGRTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNH, SYSZ_INS_CLGRTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNHE, SYSZ_INS_CLGRTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNL, SYSZ_INS_CLGRTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNLE, SYSZ_INS_CLGRTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGRTAsmNLH, SYSZ_INS_CLGRTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsm, SYSZ_INS_CLGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmE, SYSZ_INS_CLGTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmH, SYSZ_INS_CLGTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmHE, SYSZ_INS_CLGTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmL, SYSZ_INS_CLGTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmLE, SYSZ_INS_CLGTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmLH, SYSZ_INS_CLGTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNE, SYSZ_INS_CLGTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNH, SYSZ_INS_CLGTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNHE, SYSZ_INS_CLGTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNL, SYSZ_INS_CLGTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNLE, SYSZ_INS_CLGTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGTAsmNLH, SYSZ_INS_CLGTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGXBR, SYSZ_INS_CLGXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLGXTR, SYSZ_INS_CLGXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHF, SYSZ_INS_CLHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHHR, SYSZ_INS_CLHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHHSI, SYSZ_INS_CLHHSI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHLR, SYSZ_INS_CLHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLHRL, SYSZ_INS_CLHRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLI, SYSZ_INS_CLI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLIBAsm, SYSZ_INS_CLIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmE, SYSZ_INS_CLIBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmH, SYSZ_INS_CLIBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmHE, SYSZ_INS_CLIBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmL, SYSZ_INS_CLIBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmLE, SYSZ_INS_CLIBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmLH, SYSZ_INS_CLIBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNE, SYSZ_INS_CLIBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNH, SYSZ_INS_CLIBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNHE, SYSZ_INS_CLIBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNL, SYSZ_INS_CLIBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNLE, SYSZ_INS_CLIBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIBAsmNLH, SYSZ_INS_CLIBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLIH, SYSZ_INS_CLIH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLIJAsm, SYSZ_INS_CLIJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmE, SYSZ_INS_CLIJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmH, SYSZ_INS_CLIJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmHE, SYSZ_INS_CLIJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmL, SYSZ_INS_CLIJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmLE, SYSZ_INS_CLIJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmLH, SYSZ_INS_CLIJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNE, SYSZ_INS_CLIJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNH, SYSZ_INS_CLIJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNHE, SYSZ_INS_CLIJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNL, SYSZ_INS_CLIJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNLE, SYSZ_INS_CLIJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIJAsmNLH, SYSZ_INS_CLIJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLIY, SYSZ_INS_CLIY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLM, SYSZ_INS_CLM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLMH, SYSZ_INS_CLMH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLMY, SYSZ_INS_CLMY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLR, SYSZ_INS_CLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRBAsm, SYSZ_INS_CLRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmE, SYSZ_INS_CLRBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmH, SYSZ_INS_CLRBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmHE, SYSZ_INS_CLRBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmL, SYSZ_INS_CLRBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmLE, SYSZ_INS_CLRBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmLH, SYSZ_INS_CLRBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNE, SYSZ_INS_CLRBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNH, SYSZ_INS_CLRBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNHE, SYSZ_INS_CLRBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNL, SYSZ_INS_CLRBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNLE, SYSZ_INS_CLRBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRBAsmNLH, SYSZ_INS_CLRBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CLRJAsm, SYSZ_INS_CLRJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmE, SYSZ_INS_CLRJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmH, SYSZ_INS_CLRJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmHE, SYSZ_INS_CLRJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmL, SYSZ_INS_CLRJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmLE, SYSZ_INS_CLRJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmLH, SYSZ_INS_CLRJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNE, SYSZ_INS_CLRJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNH, SYSZ_INS_CLRJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNHE, SYSZ_INS_CLRJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNL, SYSZ_INS_CLRJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNLE, SYSZ_INS_CLRJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRJAsmNLH, SYSZ_INS_CLRJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CLRL, SYSZ_INS_CLRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsm, SYSZ_INS_CLRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmE, SYSZ_INS_CLRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmH, SYSZ_INS_CLRTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmHE, SYSZ_INS_CLRTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmL, SYSZ_INS_CLRTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmLE, SYSZ_INS_CLRTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmLH, SYSZ_INS_CLRTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNE, SYSZ_INS_CLRTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNH, SYSZ_INS_CLRTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNHE, SYSZ_INS_CLRTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNL, SYSZ_INS_CLRTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNLE, SYSZ_INS_CLRTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLRTAsmNLH, SYSZ_INS_CLRTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLST, SYSZ_INS_CLST, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsm, SYSZ_INS_CLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmE, SYSZ_INS_CLTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmH, SYSZ_INS_CLTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmHE, SYSZ_INS_CLTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmL, SYSZ_INS_CLTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmLE, SYSZ_INS_CLTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmLH, SYSZ_INS_CLTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNE, SYSZ_INS_CLTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNH, SYSZ_INS_CLTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNHE, SYSZ_INS_CLTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNL, SYSZ_INS_CLTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNLE, SYSZ_INS_CLTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLTAsmNLH, SYSZ_INS_CLTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CLY, SYSZ_INS_CLY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CMPSC, SYSZ_INS_CMPSC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CP, SYSZ_INS_CP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CPDT, SYSZ_INS_CPDT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CPSDRdd, SYSZ_INS_CPSDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CPXT, SYSZ_INS_CPXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CPYA, SYSZ_INS_CPYA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CR, SYSZ_INS_CR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRBAsm, SYSZ_INS_CRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmE, SYSZ_INS_CRBE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmH, SYSZ_INS_CRBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmHE, SYSZ_INS_CRBHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmL, SYSZ_INS_CRBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmLE, SYSZ_INS_CRBLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmLH, SYSZ_INS_CRBLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNE, SYSZ_INS_CRBNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNH, SYSZ_INS_CRBNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNHE, SYSZ_INS_CRBNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNL, SYSZ_INS_CRBNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNLE, SYSZ_INS_CRBNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRBAsmNLH, SYSZ_INS_CRBNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - SystemZ_CRDTE, SYSZ_INS_CRDTE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_ENHANCEDDAT2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRDTEOpt, SYSZ_INS_CRDTE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_ENHANCEDDAT2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRJAsm, SYSZ_INS_CRJ, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmE, SYSZ_INS_CRJE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmH, SYSZ_INS_CRJH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmHE, SYSZ_INS_CRJHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmL, SYSZ_INS_CRJL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmLE, SYSZ_INS_CRJLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmLH, SYSZ_INS_CRJLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNE, SYSZ_INS_CRJNE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNH, SYSZ_INS_CRJNH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNHE, SYSZ_INS_CRJNHE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNL, SYSZ_INS_CRJNL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNLE, SYSZ_INS_CRJNLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRJAsmNLH, SYSZ_INS_CRJNLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_CRL, SYSZ_INS_CRL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsm, SYSZ_INS_CRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmE, SYSZ_INS_CRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmH, SYSZ_INS_CRTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmHE, SYSZ_INS_CRTHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmL, SYSZ_INS_CRTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmLE, SYSZ_INS_CRTLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmLH, SYSZ_INS_CRTLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNE, SYSZ_INS_CRTNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNH, SYSZ_INS_CRTNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNHE, SYSZ_INS_CRTNHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNL, SYSZ_INS_CRTNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNLE, SYSZ_INS_CRTNLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CRTAsmNLH, SYSZ_INS_CRTNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CS, SYSZ_INS_CS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSCH, SYSZ_INS_CSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSDTR, SYSZ_INS_CSDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSG, SYSZ_INS_CSG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSP, SYSZ_INS_CSP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSPG, SYSZ_INS_CSPG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSST, SYSZ_INS_CSST, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSXTR, SYSZ_INS_CSXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CSY, SYSZ_INS_CSY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU12, SYSZ_INS_CU12, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU12Opt, SYSZ_INS_CU12, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU14, SYSZ_INS_CU14, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU14Opt, SYSZ_INS_CU14, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU21, SYSZ_INS_CU21, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU21Opt, SYSZ_INS_CU21, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU24, SYSZ_INS_CU24, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU24Opt, SYSZ_INS_CU24, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU41, SYSZ_INS_CU41, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CU42, SYSZ_INS_CU42, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUDTR, SYSZ_INS_CUDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUSE, SYSZ_INS_CUSE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUTFU, SYSZ_INS_CUTFU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUTFUOpt, SYSZ_INS_CUTFU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUUTF, SYSZ_INS_CUUTF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUUTFOpt, SYSZ_INS_CUUTF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CUXTR, SYSZ_INS_CUXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVB, SYSZ_INS_CVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVBG, SYSZ_INS_CVBG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVBY, SYSZ_INS_CVBY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVD, SYSZ_INS_CVD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVDG, SYSZ_INS_CVDG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CVDY, SYSZ_INS_CVDY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXBR, SYSZ_INS_CXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXFBR, SYSZ_INS_CXFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXFBRA, SYSZ_INS_CXFBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXFR, SYSZ_INS_CXFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXFTR, SYSZ_INS_CXFTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGBR, SYSZ_INS_CXGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGBRA, SYSZ_INS_CXGBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGR, SYSZ_INS_CXGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGTR, SYSZ_INS_CXGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXGTRA, SYSZ_INS_CXGTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXLFBR, SYSZ_INS_CXLFBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXLFTR, SYSZ_INS_CXLFTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXLGBR, SYSZ_INS_CXLGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXLGTR, SYSZ_INS_CXLGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXPT, SYSZ_INS_CXPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXR, SYSZ_INS_CXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXSTR, SYSZ_INS_CXSTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXTR, SYSZ_INS_CXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXUTR, SYSZ_INS_CXUTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CXZT, SYSZ_INS_CXZT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CY, SYSZ_INS_CY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_CZDT, SYSZ_INS_CZDT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_CZXT, SYSZ_INS_CZXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_D, SYSZ_INS_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DD, SYSZ_INS_DD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDB, SYSZ_INS_DDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDBR, SYSZ_INS_DDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDR, SYSZ_INS_DDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDTR, SYSZ_INS_DDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DDTRA, SYSZ_INS_DDTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_DE, SYSZ_INS_DE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DEB, SYSZ_INS_DEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DEBR, SYSZ_INS_DEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DER, SYSZ_INS_DER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DIAG, SYSZ_INS_DIAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DIDBR, SYSZ_INS_DIDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DIEBR, SYSZ_INS_DIEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DL, SYSZ_INS_DL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DLG, SYSZ_INS_DLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DLGR, SYSZ_INS_DLGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DLR, SYSZ_INS_DLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DP, SYSZ_INS_DP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DR, SYSZ_INS_DR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DSG, SYSZ_INS_DSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DSGF, SYSZ_INS_DSGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DSGFR, SYSZ_INS_DSGFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DSGR, SYSZ_INS_DSGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DXBR, SYSZ_INS_DXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DXR, SYSZ_INS_DXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DXTR, SYSZ_INS_DXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_DXTRA, SYSZ_INS_DXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_EAR, SYSZ_INS_EAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ECAG, SYSZ_INS_ECAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ECCTR, SYSZ_INS_ECCTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ECPGA, SYSZ_INS_ECPGA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ECTG, SYSZ_INS_ECTG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ED, SYSZ_INS_ED, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EDMK, SYSZ_INS_EDMK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EEDTR, SYSZ_INS_EEDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EEXTR, SYSZ_INS_EEXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EFPC, SYSZ_INS_EFPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EPAIR, SYSZ_INS_EPAIR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EPAR, SYSZ_INS_EPAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EPCTR, SYSZ_INS_EPCTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EPSW, SYSZ_INS_EPSW, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EREG, SYSZ_INS_EREG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EREGG, SYSZ_INS_EREGG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESAIR, SYSZ_INS_ESAIR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESAR, SYSZ_INS_ESAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESDTR, SYSZ_INS_ESDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESEA, SYSZ_INS_ESEA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESTA, SYSZ_INS_ESTA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ESXTR, SYSZ_INS_ESXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ETND, SYSZ_INS_ETND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_EX, SYSZ_INS_EX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_EXRL, SYSZ_INS_EXRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIDBR, SYSZ_INS_FIDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIDBRA, SYSZ_INS_FIDBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIDR, SYSZ_INS_FIDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIDTR, SYSZ_INS_FIDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIEBR, SYSZ_INS_FIEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIEBRA, SYSZ_INS_FIEBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIER, SYSZ_INS_FIER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIXBR, SYSZ_INS_FIXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIXBRA, SYSZ_INS_FIXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIXR, SYSZ_INS_FIXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FIXTR, SYSZ_INS_FIXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_FLOGR, SYSZ_INS_FLOGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_HDR, SYSZ_INS_HDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_HER, SYSZ_INS_HER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_HSCH, SYSZ_INS_HSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IAC, SYSZ_INS_IAC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IC, SYSZ_INS_IC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ICM, SYSZ_INS_ICM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ICMH, SYSZ_INS_ICMH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ICMY, SYSZ_INS_ICMY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ICY, SYSZ_INS_ICY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IDTE, SYSZ_INS_IDTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IDTEOpt, SYSZ_INS_IDTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IEDTR, SYSZ_INS_IEDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IEXTR, SYSZ_INS_IEXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IIHF, SYSZ_INS_IIHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IIHH, SYSZ_INS_IIHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IIHL, SYSZ_INS_IIHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IILF, SYSZ_INS_IILF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IILH, SYSZ_INS_IILH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IILL, SYSZ_INS_IILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPK, SYSZ_INS_IPK, -#ifndef CAPSTONE_DIET - { SYSZ_REG_2, 0 }, { SYSZ_REG_2, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPM, SYSZ_INS_IPM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPTE, SYSZ_INS_IPTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPTEOpt, SYSZ_INS_IPTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IPTEOptOpt, SYSZ_INS_IPTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IRBM, SYSZ_INS_IRBM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ISKE, SYSZ_INS_ISKE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_IVSK, SYSZ_INS_IVSK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_J, SYSZ_INS_J, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmE, SYSZ_INS_JE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmH, SYSZ_INS_JH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmHE, SYSZ_INS_JHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmL, SYSZ_INS_JL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmLE, SYSZ_INS_JLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmLH, SYSZ_INS_JLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmM, SYSZ_INS_JM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNE, SYSZ_INS_JNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNH, SYSZ_INS_JNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNHE, SYSZ_INS_JNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNL, SYSZ_INS_JNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNLE, SYSZ_INS_JNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNLH, SYSZ_INS_JNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNM, SYSZ_INS_JNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNO, SYSZ_INS_JNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNP, SYSZ_INS_JNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmNZ, SYSZ_INS_JNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmO, SYSZ_INS_JO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmP, SYSZ_INS_JP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JAsmZ, SYSZ_INS_JZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JG, SYSZ_INS_JG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmE, SYSZ_INS_JGE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmH, SYSZ_INS_JGH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmHE, SYSZ_INS_JGHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmL, SYSZ_INS_JGL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmLE, SYSZ_INS_JGLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmLH, SYSZ_INS_JGLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmM, SYSZ_INS_JGM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNE, SYSZ_INS_JGNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNH, SYSZ_INS_JGNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNHE, SYSZ_INS_JGNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNL, SYSZ_INS_JGNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNLE, SYSZ_INS_JGNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNLH, SYSZ_INS_JGNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNM, SYSZ_INS_JGNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNO, SYSZ_INS_JGNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNP, SYSZ_INS_JGNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmNZ, SYSZ_INS_JGNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmO, SYSZ_INS_JGO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmP, SYSZ_INS_JGP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_JGAsmZ, SYSZ_INS_JGZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - SystemZ_KDB, SYSZ_INS_KDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KDBR, SYSZ_INS_KDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KDTR, SYSZ_INS_KDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KEB, SYSZ_INS_KEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KEBR, SYSZ_INS_KEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KIMD, SYSZ_INS_KIMD, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KLMD, SYSZ_INS_KLMD, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KM, SYSZ_INS_KM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMA, SYSZ_INS_KMA, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST8, 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMAC, SYSZ_INS_KMAC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMC, SYSZ_INS_KMC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMCTR, SYSZ_INS_KMCTR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMF, SYSZ_INS_KMF, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 -#endif -}, -{ - SystemZ_KMO, SYSZ_INS_KMO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 -#endif -}, -{ - SystemZ_KXBR, SYSZ_INS_KXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_KXTR, SYSZ_INS_KXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_L, SYSZ_INS_L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LA, SYSZ_INS_LA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAA, SYSZ_INS_LAA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAAG, SYSZ_INS_LAAG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAAL, SYSZ_INS_LAAL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAALG, SYSZ_INS_LAALG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAE, SYSZ_INS_LAE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAEY, SYSZ_INS_LAEY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAM, SYSZ_INS_LAM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAMY, SYSZ_INS_LAMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAN, SYSZ_INS_LAN, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LANG, SYSZ_INS_LANG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAO, SYSZ_INS_LAO, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAOG, SYSZ_INS_LAOG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LARL, SYSZ_INS_LARL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LASP, SYSZ_INS_LASP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAT, SYSZ_INS_LAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAX, SYSZ_INS_LAX, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAXG, SYSZ_INS_LAXG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LAY, SYSZ_INS_LAY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LB, SYSZ_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LBH, SYSZ_INS_LBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LBR, SYSZ_INS_LBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCBB, SYSZ_INS_LCBB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCCTL, SYSZ_INS_LCCTL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCDBR, SYSZ_INS_LCDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCDFR, SYSZ_INS_LCDFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCDR, SYSZ_INS_LCDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCEBR, SYSZ_INS_LCEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCER, SYSZ_INS_LCER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCGFR, SYSZ_INS_LCGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCGR, SYSZ_INS_LCGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCR, SYSZ_INS_LCR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCTL, SYSZ_INS_LCTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCTLG, SYSZ_INS_LCTLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCXBR, SYSZ_INS_LCXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LCXR, SYSZ_INS_LCXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LD, SYSZ_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDE, SYSZ_INS_LDE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDEB, SYSZ_INS_LDEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDEBR, SYSZ_INS_LDEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDER, SYSZ_INS_LDER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDETR, SYSZ_INS_LDETR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDGR, SYSZ_INS_LDGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDR, SYSZ_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDXBR, SYSZ_INS_LDXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDXBRA, SYSZ_INS_LDXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDXR, SYSZ_INS_LDXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDXTR, SYSZ_INS_LDXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LDY, SYSZ_INS_LDY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LE, SYSZ_INS_LE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEDBR, SYSZ_INS_LEDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEDBRA, SYSZ_INS_LEDBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEDR, SYSZ_INS_LEDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEDTR, SYSZ_INS_LEDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LER, SYSZ_INS_LER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEXBR, SYSZ_INS_LEXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEXBRA, SYSZ_INS_LEXBRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEXR, SYSZ_INS_LEXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LEY, SYSZ_INS_LEY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LFAS, SYSZ_INS_LFAS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LFH, SYSZ_INS_LFH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LFHAT, SYSZ_INS_LFHAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LFPC, SYSZ_INS_LFPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LG, SYSZ_INS_LG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGAT, SYSZ_INS_LGAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGB, SYSZ_INS_LGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGBR, SYSZ_INS_LGBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGDR, SYSZ_INS_LGDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGF, SYSZ_INS_LGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGFI, SYSZ_INS_LGFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGFR, SYSZ_INS_LGFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGFRL, SYSZ_INS_LGFRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGG, SYSZ_INS_LGG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGH, SYSZ_INS_LGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGHI, SYSZ_INS_LGHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGHR, SYSZ_INS_LGHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGHRL, SYSZ_INS_LGHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGR, SYSZ_INS_LGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGRL, SYSZ_INS_LGRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LGSC, SYSZ_INS_LGSC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LH, SYSZ_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHH, SYSZ_INS_LHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHI, SYSZ_INS_LHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHR, SYSZ_INS_LHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHRL, SYSZ_INS_LHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LHY, SYSZ_INS_LHY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLC, SYSZ_INS_LLC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLCH, SYSZ_INS_LLCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLCR, SYSZ_INS_LLCR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGC, SYSZ_INS_LLGC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGCR, SYSZ_INS_LLGCR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGF, SYSZ_INS_LLGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGFAT, SYSZ_INS_LLGFAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGFR, SYSZ_INS_LLGFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGFRL, SYSZ_INS_LLGFRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGFSG, SYSZ_INS_LLGFSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGH, SYSZ_INS_LLGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGHR, SYSZ_INS_LLGHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGHRL, SYSZ_INS_LLGHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGT, SYSZ_INS_LLGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGTAT, SYSZ_INS_LLGTAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLGTR, SYSZ_INS_LLGTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLH, SYSZ_INS_LLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLHH, SYSZ_INS_LLHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLHR, SYSZ_INS_LLHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLHRL, SYSZ_INS_LLHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLIHF, SYSZ_INS_LLIHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLIHH, SYSZ_INS_LLIHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLIHL, SYSZ_INS_LLIHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLILF, SYSZ_INS_LLILF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLILH, SYSZ_INS_LLILH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLILL, SYSZ_INS_LLILL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LLZRGF, SYSZ_INS_LLZRGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LM, SYSZ_INS_LM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LMD, SYSZ_INS_LMD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LMG, SYSZ_INS_LMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LMH, SYSZ_INS_LMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LMY, SYSZ_INS_LMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNDBR, SYSZ_INS_LNDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNDFR, SYSZ_INS_LNDFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNDR, SYSZ_INS_LNDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNEBR, SYSZ_INS_LNEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNER, SYSZ_INS_LNER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNGFR, SYSZ_INS_LNGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNGR, SYSZ_INS_LNGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNR, SYSZ_INS_LNR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNXBR, SYSZ_INS_LNXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LNXR, SYSZ_INS_LNXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsm, SYSZ_INS_LOC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmE, SYSZ_INS_LOCE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmH, SYSZ_INS_LOCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmHE, SYSZ_INS_LOCHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmL, SYSZ_INS_LOCL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmLE, SYSZ_INS_LOCLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmLH, SYSZ_INS_LOCLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmM, SYSZ_INS_LOCM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNE, SYSZ_INS_LOCNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNH, SYSZ_INS_LOCNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNHE, SYSZ_INS_LOCNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNL, SYSZ_INS_LOCNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNLE, SYSZ_INS_LOCNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNLH, SYSZ_INS_LOCNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNM, SYSZ_INS_LOCNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNO, SYSZ_INS_LOCNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNP, SYSZ_INS_LOCNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmNZ, SYSZ_INS_LOCNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmO, SYSZ_INS_LOCO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmP, SYSZ_INS_LOCP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCAsmZ, SYSZ_INS_LOCZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsm, SYSZ_INS_LOCFH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmE, SYSZ_INS_LOCFHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmH, SYSZ_INS_LOCFHH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmHE, SYSZ_INS_LOCFHHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmL, SYSZ_INS_LOCFHL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmLE, SYSZ_INS_LOCFHLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmLH, SYSZ_INS_LOCFHLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmM, SYSZ_INS_LOCFHM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNE, SYSZ_INS_LOCFHNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNH, SYSZ_INS_LOCFHNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNHE, SYSZ_INS_LOCFHNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNL, SYSZ_INS_LOCFHNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNLE, SYSZ_INS_LOCFHNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNLH, SYSZ_INS_LOCFHNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNM, SYSZ_INS_LOCFHNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNO, SYSZ_INS_LOCFHNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNP, SYSZ_INS_LOCFHNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmNZ, SYSZ_INS_LOCFHNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmO, SYSZ_INS_LOCFHO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmP, SYSZ_INS_LOCFHP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHAsmZ, SYSZ_INS_LOCFHZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsm, SYSZ_INS_LOCFHR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmE, SYSZ_INS_LOCFHRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmH, SYSZ_INS_LOCFHRH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmHE, SYSZ_INS_LOCFHRHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmL, SYSZ_INS_LOCFHRL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmLE, SYSZ_INS_LOCFHRLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmLH, SYSZ_INS_LOCFHRLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmM, SYSZ_INS_LOCFHRM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNE, SYSZ_INS_LOCFHRNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNH, SYSZ_INS_LOCFHRNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNHE, SYSZ_INS_LOCFHRNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNL, SYSZ_INS_LOCFHRNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNLE, SYSZ_INS_LOCFHRNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNLH, SYSZ_INS_LOCFHRNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNM, SYSZ_INS_LOCFHRNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNO, SYSZ_INS_LOCFHRNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNP, SYSZ_INS_LOCFHRNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmNZ, SYSZ_INS_LOCFHRNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmO, SYSZ_INS_LOCFHRO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmP, SYSZ_INS_LOCFHRP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCFHRAsmZ, SYSZ_INS_LOCFHRZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsm, SYSZ_INS_LOCG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmE, SYSZ_INS_LOCGE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmH, SYSZ_INS_LOCGH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmHE, SYSZ_INS_LOCGHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmL, SYSZ_INS_LOCGL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmLE, SYSZ_INS_LOCGLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmLH, SYSZ_INS_LOCGLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmM, SYSZ_INS_LOCGM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNE, SYSZ_INS_LOCGNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNH, SYSZ_INS_LOCGNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNHE, SYSZ_INS_LOCGNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNL, SYSZ_INS_LOCGNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNLE, SYSZ_INS_LOCGNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNLH, SYSZ_INS_LOCGNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNM, SYSZ_INS_LOCGNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNO, SYSZ_INS_LOCGNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNP, SYSZ_INS_LOCGNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmNZ, SYSZ_INS_LOCGNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmO, SYSZ_INS_LOCGO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmP, SYSZ_INS_LOCGP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGAsmZ, SYSZ_INS_LOCGZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsm, SYSZ_INS_LOCGHI, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmE, SYSZ_INS_LOCGHIE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmH, SYSZ_INS_LOCGHIH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmHE, SYSZ_INS_LOCGHIHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmL, SYSZ_INS_LOCGHIL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmLE, SYSZ_INS_LOCGHILE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmLH, SYSZ_INS_LOCGHILH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmM, SYSZ_INS_LOCGHIM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNE, SYSZ_INS_LOCGHINE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNH, SYSZ_INS_LOCGHINH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNHE, SYSZ_INS_LOCGHINHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNL, SYSZ_INS_LOCGHINL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNLE, SYSZ_INS_LOCGHINLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNLH, SYSZ_INS_LOCGHINLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNM, SYSZ_INS_LOCGHINM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNO, SYSZ_INS_LOCGHINO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNP, SYSZ_INS_LOCGHINP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmNZ, SYSZ_INS_LOCGHINZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmO, SYSZ_INS_LOCGHIO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmP, SYSZ_INS_LOCGHIP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGHIAsmZ, SYSZ_INS_LOCGHIZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsm, SYSZ_INS_LOCGR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmE, SYSZ_INS_LOCGRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmH, SYSZ_INS_LOCGRH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmHE, SYSZ_INS_LOCGRHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmL, SYSZ_INS_LOCGRL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmLE, SYSZ_INS_LOCGRLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmLH, SYSZ_INS_LOCGRLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmM, SYSZ_INS_LOCGRM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNE, SYSZ_INS_LOCGRNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNH, SYSZ_INS_LOCGRNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNHE, SYSZ_INS_LOCGRNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNL, SYSZ_INS_LOCGRNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNLE, SYSZ_INS_LOCGRNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNLH, SYSZ_INS_LOCGRNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNM, SYSZ_INS_LOCGRNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNO, SYSZ_INS_LOCGRNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNP, SYSZ_INS_LOCGRNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmNZ, SYSZ_INS_LOCGRNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmO, SYSZ_INS_LOCGRO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmP, SYSZ_INS_LOCGRP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCGRAsmZ, SYSZ_INS_LOCGRZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsm, SYSZ_INS_LOCHHI, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmE, SYSZ_INS_LOCHHIE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmH, SYSZ_INS_LOCHHIH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmHE, SYSZ_INS_LOCHHIHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmL, SYSZ_INS_LOCHHIL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmLE, SYSZ_INS_LOCHHILE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmLH, SYSZ_INS_LOCHHILH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmM, SYSZ_INS_LOCHHIM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNE, SYSZ_INS_LOCHHINE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNH, SYSZ_INS_LOCHHINH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNHE, SYSZ_INS_LOCHHINHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNL, SYSZ_INS_LOCHHINL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNLE, SYSZ_INS_LOCHHINLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNLH, SYSZ_INS_LOCHHINLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNM, SYSZ_INS_LOCHHINM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNO, SYSZ_INS_LOCHHINO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNP, SYSZ_INS_LOCHHINP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmNZ, SYSZ_INS_LOCHHINZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmO, SYSZ_INS_LOCHHIO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmP, SYSZ_INS_LOCHHIP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHHIAsmZ, SYSZ_INS_LOCHHIZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsm, SYSZ_INS_LOCHI, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmE, SYSZ_INS_LOCHIE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmH, SYSZ_INS_LOCHIH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmHE, SYSZ_INS_LOCHIHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmL, SYSZ_INS_LOCHIL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmLE, SYSZ_INS_LOCHILE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmLH, SYSZ_INS_LOCHILH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmM, SYSZ_INS_LOCHIM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNE, SYSZ_INS_LOCHINE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNH, SYSZ_INS_LOCHINH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNHE, SYSZ_INS_LOCHINHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNL, SYSZ_INS_LOCHINL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNLE, SYSZ_INS_LOCHINLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNLH, SYSZ_INS_LOCHINLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNM, SYSZ_INS_LOCHINM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNO, SYSZ_INS_LOCHINO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNP, SYSZ_INS_LOCHINP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmNZ, SYSZ_INS_LOCHINZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmO, SYSZ_INS_LOCHIO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmP, SYSZ_INS_LOCHIP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCHIAsmZ, SYSZ_INS_LOCHIZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsm, SYSZ_INS_LOCR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmE, SYSZ_INS_LOCRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmH, SYSZ_INS_LOCRH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmHE, SYSZ_INS_LOCRHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmL, SYSZ_INS_LOCRL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmLE, SYSZ_INS_LOCRLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmLH, SYSZ_INS_LOCRLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmM, SYSZ_INS_LOCRM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNE, SYSZ_INS_LOCRNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNH, SYSZ_INS_LOCRNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNHE, SYSZ_INS_LOCRNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNL, SYSZ_INS_LOCRNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNLE, SYSZ_INS_LOCRNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNLH, SYSZ_INS_LOCRNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNM, SYSZ_INS_LOCRNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNO, SYSZ_INS_LOCRNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNP, SYSZ_INS_LOCRNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmNZ, SYSZ_INS_LOCRNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmO, SYSZ_INS_LOCRO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmP, SYSZ_INS_LOCRP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LOCRAsmZ, SYSZ_INS_LOCRZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPCTL, SYSZ_INS_LPCTL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPD, SYSZ_INS_LPD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPDBR, SYSZ_INS_LPDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPDFR, SYSZ_INS_LPDFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPDG, SYSZ_INS_LPDG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPDR, SYSZ_INS_LPDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPEBR, SYSZ_INS_LPEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPER, SYSZ_INS_LPER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPGFR, SYSZ_INS_LPGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPGR, SYSZ_INS_LPGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPP, SYSZ_INS_LPP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPQ, SYSZ_INS_LPQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPR, SYSZ_INS_LPR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPSW, SYSZ_INS_LPSW, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPSWE, SYSZ_INS_LPSWE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPTEA, SYSZ_INS_LPTEA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPXBR, SYSZ_INS_LPXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LPXR, SYSZ_INS_LPXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LR, SYSZ_INS_LR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRA, SYSZ_INS_LRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRAG, SYSZ_INS_LRAG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRAY, SYSZ_INS_LRAY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRDR, SYSZ_INS_LRDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRER, SYSZ_INS_LRER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRL, SYSZ_INS_LRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRV, SYSZ_INS_LRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRVG, SYSZ_INS_LRVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRVGR, SYSZ_INS_LRVGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRVH, SYSZ_INS_LRVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LRVR, SYSZ_INS_LRVR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LSCTL, SYSZ_INS_LSCTL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LT, SYSZ_INS_LT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTDBR, SYSZ_INS_LTDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTDR, SYSZ_INS_LTDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTDTR, SYSZ_INS_LTDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTEBR, SYSZ_INS_LTEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTER, SYSZ_INS_LTER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTG, SYSZ_INS_LTG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTGF, SYSZ_INS_LTGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTGFR, SYSZ_INS_LTGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTGR, SYSZ_INS_LTGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTR, SYSZ_INS_LTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTXBR, SYSZ_INS_LTXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTXR, SYSZ_INS_LTXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LTXTR, SYSZ_INS_LTXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LURA, SYSZ_INS_LURA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LURAG, SYSZ_INS_LURAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXD, SYSZ_INS_LXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXDB, SYSZ_INS_LXDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXDBR, SYSZ_INS_LXDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXDR, SYSZ_INS_LXDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXDTR, SYSZ_INS_LXDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXE, SYSZ_INS_LXE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXEB, SYSZ_INS_LXEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXEBR, SYSZ_INS_LXEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXER, SYSZ_INS_LXER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LXR, SYSZ_INS_LXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LY, SYSZ_INS_LY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZDR, SYSZ_INS_LZDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZER, SYSZ_INS_LZER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZRF, SYSZ_INS_LZRF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZRG, SYSZ_INS_LZRG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_LZXR, SYSZ_INS_LZXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_M, SYSZ_INS_M, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAD, SYSZ_INS_MAD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MADB, SYSZ_INS_MADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MADBR, SYSZ_INS_MADBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MADR, SYSZ_INS_MADR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAE, SYSZ_INS_MAE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAEB, SYSZ_INS_MAEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAEBR, SYSZ_INS_MAEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAER, SYSZ_INS_MAER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAY, SYSZ_INS_MAY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYH, SYSZ_INS_MAYH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYHR, SYSZ_INS_MAYHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYL, SYSZ_INS_MAYL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYLR, SYSZ_INS_MAYLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MAYR, SYSZ_INS_MAYR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MC, SYSZ_INS_MC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MD, SYSZ_INS_MD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDB, SYSZ_INS_MDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDBR, SYSZ_INS_MDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDE, SYSZ_INS_MDE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDEB, SYSZ_INS_MDEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDEBR, SYSZ_INS_MDEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDER, SYSZ_INS_MDER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDR, SYSZ_INS_MDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDTR, SYSZ_INS_MDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MDTRA, SYSZ_INS_MDTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_ME, SYSZ_INS_ME, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MEE, SYSZ_INS_MEE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MEEB, SYSZ_INS_MEEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MEEBR, SYSZ_INS_MEEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MEER, SYSZ_INS_MEER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MER, SYSZ_INS_MER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MFY, SYSZ_INS_MFY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MG, SYSZ_INS_MG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MGH, SYSZ_INS_MGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MGHI, SYSZ_INS_MGHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MGRK, SYSZ_INS_MGRK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MH, SYSZ_INS_MH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MHI, SYSZ_INS_MHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MHY, SYSZ_INS_MHY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ML, SYSZ_INS_ML, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MLG, SYSZ_INS_MLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MLGR, SYSZ_INS_MLGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MLR, SYSZ_INS_MLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MP, SYSZ_INS_MP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MR, SYSZ_INS_MR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MS, SYSZ_INS_MS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSC, SYSZ_INS_MSC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSCH, SYSZ_INS_MSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSD, SYSZ_INS_MSD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSDB, SYSZ_INS_MSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSDBR, SYSZ_INS_MSDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSDR, SYSZ_INS_MSDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSE, SYSZ_INS_MSE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSEB, SYSZ_INS_MSEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSEBR, SYSZ_INS_MSEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSER, SYSZ_INS_MSER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSFI, SYSZ_INS_MSFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSG, SYSZ_INS_MSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGC, SYSZ_INS_MSGC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGF, SYSZ_INS_MSGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGFI, SYSZ_INS_MSGFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGFR, SYSZ_INS_MSGFR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGR, SYSZ_INS_MSGR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSGRKC, SYSZ_INS_MSGRKC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSR, SYSZ_INS_MSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSRKC, SYSZ_INS_MSRKC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSTA, SYSZ_INS_MSTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MSY, SYSZ_INS_MSY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVC, SYSZ_INS_MVC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCDK, SYSZ_INS_MVCDK, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCIN, SYSZ_INS_MVCIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCK, SYSZ_INS_MVCK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCL, SYSZ_INS_MVCL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCLE, SYSZ_INS_MVCLE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCLU, SYSZ_INS_MVCLU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCOS, SYSZ_INS_MVCOS, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCP, SYSZ_INS_MVCP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCS, SYSZ_INS_MVCS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVCSK, SYSZ_INS_MVCSK, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVGHI, SYSZ_INS_MVGHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVHHI, SYSZ_INS_MVHHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVHI, SYSZ_INS_MVHI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVI, SYSZ_INS_MVI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVIY, SYSZ_INS_MVIY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVN, SYSZ_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVO, SYSZ_INS_MVO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVPG, SYSZ_INS_MVPG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVST, SYSZ_INS_MVST, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MVZ, SYSZ_INS_MVZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXBR, SYSZ_INS_MXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXD, SYSZ_INS_MXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXDB, SYSZ_INS_MXDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXDBR, SYSZ_INS_MXDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXDR, SYSZ_INS_MXDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXR, SYSZ_INS_MXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXTR, SYSZ_INS_MXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MXTRA, SYSZ_INS_MXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_MY, SYSZ_INS_MY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYH, SYSZ_INS_MYH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYHR, SYSZ_INS_MYHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYL, SYSZ_INS_MYL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYLR, SYSZ_INS_MYLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_MYR, SYSZ_INS_MYR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_N, SYSZ_INS_N, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NC, SYSZ_INS_NC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NG, SYSZ_INS_NG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NGR, SYSZ_INS_NGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NGRK, SYSZ_INS_NGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_NI, SYSZ_INS_NI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIAI, SYSZ_INS_NIAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIHF, SYSZ_INS_NIHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIHH, SYSZ_INS_NIHH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIHL, SYSZ_INS_NIHL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NILF, SYSZ_INS_NILF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NILH, SYSZ_INS_NILH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NILL, SYSZ_INS_NILL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NIY, SYSZ_INS_NIY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NR, SYSZ_INS_NR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_NRK, SYSZ_INS_NRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_NTSTG, SYSZ_INS_NTSTG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_NY, SYSZ_INS_NY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_O, SYSZ_INS_O, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OC, SYSZ_INS_OC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OG, SYSZ_INS_OG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OGR, SYSZ_INS_OGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OGRK, SYSZ_INS_OGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_OI, SYSZ_INS_OI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OIHF, SYSZ_INS_OIHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OIHH, SYSZ_INS_OIHH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OIHL, SYSZ_INS_OIHL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OILF, SYSZ_INS_OILF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OILH, SYSZ_INS_OILH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OILL, SYSZ_INS_OILL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OIY, SYSZ_INS_OIY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_OR, SYSZ_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ORK, SYSZ_INS_ORK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_OY, SYSZ_INS_OY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PACK, SYSZ_INS_PACK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PALB, SYSZ_INS_PALB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PC, SYSZ_INS_PC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PCC, SYSZ_INS_PCC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PCKMO, SYSZ_INS_PCKMO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST3, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PFD, SYSZ_INS_PFD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PFDRL, SYSZ_INS_PFDRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PFMF, SYSZ_INS_PFMF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PFPO, SYSZ_INS_PFPO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_F4Q, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_F0Q, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PGIN, SYSZ_INS_PGIN, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PGOUT, SYSZ_INS_PGOUT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PKA, SYSZ_INS_PKA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PKU, SYSZ_INS_PKU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PLO, SYSZ_INS_PLO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_POPCNT, SYSZ_INS_POPCNT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_POPULATIONCOUNT, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PPA, SYSZ_INS_PPA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_PROCESSORASSIST, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PPNO, SYSZ_INS_PPNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST5, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PR, SYSZ_INS_PR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PRNO, SYSZ_INS_PRNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST7, 0 }, 0, 0 -#endif -}, -{ - SystemZ_PT, SYSZ_INS_PT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PTF, SYSZ_INS_PTF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PTFF, SYSZ_INS_PTFF, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PTI, SYSZ_INS_PTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_PTLB, SYSZ_INS_PTLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_QADTR, SYSZ_INS_QADTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_QAXTR, SYSZ_INS_QAXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_QCTRI, SYSZ_INS_QCTRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_QSI, SYSZ_INS_QSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RCHP, SYSZ_INS_RCHP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RISBG, SYSZ_INS_RISBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RISBGN, SYSZ_INS_RISBGN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_RISBHG, SYSZ_INS_RISBHG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_RISBLG, SYSZ_INS_RISBLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_RLL, SYSZ_INS_RLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RLLG, SYSZ_INS_RLLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RNSBG, SYSZ_INS_RNSBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ROSBG, SYSZ_INS_ROSBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RP, SYSZ_INS_RP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RRBE, SYSZ_INS_RRBE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RRBM, SYSZ_INS_RRBM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_RRDTR, SYSZ_INS_RRDTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RRXTR, SYSZ_INS_RRXTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RSCH, SYSZ_INS_RSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_RXSBG, SYSZ_INS_RXSBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_S, SYSZ_INS_S, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAC, SYSZ_INS_SAC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SACF, SYSZ_INS_SACF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAL, SYSZ_INS_SAL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAM24, SYSZ_INS_SAM24, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAM31, SYSZ_INS_SAM31, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAM64, SYSZ_INS_SAM64, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SAR, SYSZ_INS_SAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCCTR, SYSZ_INS_SCCTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCHM, SYSZ_INS_SCHM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, SYSZ_REG_2, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCK, SYSZ_INS_SCK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCKC, SYSZ_INS_SCKC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SCKPF, SYSZ_INS_SCKPF, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SD, SYSZ_INS_SD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDB, SYSZ_INS_SDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDBR, SYSZ_INS_SDBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDR, SYSZ_INS_SDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDTR, SYSZ_INS_SDTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SDTRA, SYSZ_INS_SDTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SE, SYSZ_INS_SE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SEB, SYSZ_INS_SEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SEBR, SYSZ_INS_SEBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SER, SYSZ_INS_SER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SFASR, SYSZ_INS_SFASR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SFPC, SYSZ_INS_SFPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SG, SYSZ_INS_SG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGF, SYSZ_INS_SGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGFR, SYSZ_INS_SGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGH, SYSZ_INS_SGH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGR, SYSZ_INS_SGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SGRK, SYSZ_INS_SGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SH, SYSZ_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SHHHR, SYSZ_INS_SHHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SHHLR, SYSZ_INS_SHHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SHY, SYSZ_INS_SHY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SIE, SYSZ_INS_SIE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SIGA, SYSZ_INS_SIGA, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SIGP, SYSZ_INS_SIGP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SL, SYSZ_INS_SL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLA, SYSZ_INS_SLA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLAG, SYSZ_INS_SLAG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLAK, SYSZ_INS_SLAK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLB, SYSZ_INS_SLB, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLBG, SYSZ_INS_SLBG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLBGR, SYSZ_INS_SLBGR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLBR, SYSZ_INS_SLBR, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLDA, SYSZ_INS_SLDA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLDL, SYSZ_INS_SLDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLDT, SYSZ_INS_SLDT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLFI, SYSZ_INS_SLFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLG, SYSZ_INS_SLG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGF, SYSZ_INS_SLGF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGFI, SYSZ_INS_SLGFI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGFR, SYSZ_INS_SLGFR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGR, SYSZ_INS_SLGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLGRK, SYSZ_INS_SLGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLHHHR, SYSZ_INS_SLHHHR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLHHLR, SYSZ_INS_SLHHLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLL, SYSZ_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLLG, SYSZ_INS_SLLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLLK, SYSZ_INS_SLLK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLR, SYSZ_INS_SLR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLRK, SYSZ_INS_SLRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLXT, SYSZ_INS_SLXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SLY, SYSZ_INS_SLY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SP, SYSZ_INS_SP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPCTR, SYSZ_INS_SPCTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPKA, SYSZ_INS_SPKA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPM, SYSZ_INS_SPM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPT, SYSZ_INS_SPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SPX, SYSZ_INS_SPX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQD, SYSZ_INS_SQD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQDB, SYSZ_INS_SQDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQDBR, SYSZ_INS_SQDBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQDR, SYSZ_INS_SQDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQE, SYSZ_INS_SQE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQEB, SYSZ_INS_SQEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQEBR, SYSZ_INS_SQEBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQER, SYSZ_INS_SQER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQXBR, SYSZ_INS_SQXBR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SQXR, SYSZ_INS_SQXR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SR, SYSZ_INS_SR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRA, SYSZ_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRAG, SYSZ_INS_SRAG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRAK, SYSZ_INS_SRAK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRDA, SYSZ_INS_SRDA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRDL, SYSZ_INS_SRDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRDT, SYSZ_INS_SRDT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRK, SYSZ_INS_SRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRL, SYSZ_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRLG, SYSZ_INS_SRLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRLK, SYSZ_INS_SRLK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRNM, SYSZ_INS_SRNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRNMB, SYSZ_INS_SRNMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRNMT, SYSZ_INS_SRNMT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRP, SYSZ_INS_SRP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRST, SYSZ_INS_SRST, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRSTU, SYSZ_INS_SRSTU, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SRXT, SYSZ_INS_SRXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSAIR, SYSZ_INS_SSAIR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSAR, SYSZ_INS_SSAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSCH, SYSZ_INS_SSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSKE, SYSZ_INS_SSKE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSKEOpt, SYSZ_INS_SSKE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SSM, SYSZ_INS_SSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_ST, SYSZ_INS_ST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STAM, SYSZ_INS_STAM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STAMY, SYSZ_INS_STAMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STAP, SYSZ_INS_STAP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STC, SYSZ_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCH, SYSZ_INS_STCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCK, SYSZ_INS_STCK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCKC, SYSZ_INS_STCKC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCKE, SYSZ_INS_STCKE, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCKF, SYSZ_INS_STCKF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCM, SYSZ_INS_STCM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCMH, SYSZ_INS_STCMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCMY, SYSZ_INS_STCMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCPS, SYSZ_INS_STCPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCRW, SYSZ_INS_STCRW, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCTG, SYSZ_INS_STCTG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCTL, SYSZ_INS_STCTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STCY, SYSZ_INS_STCY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STD, SYSZ_INS_STD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STDY, SYSZ_INS_STDY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STE, SYSZ_INS_STE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STEY, SYSZ_INS_STEY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STFH, SYSZ_INS_STFH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STFL, SYSZ_INS_STFL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STFLE, SYSZ_INS_STFLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STFPC, SYSZ_INS_STFPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STG, SYSZ_INS_STG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STGRL, SYSZ_INS_STGRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STGSC, SYSZ_INS_STGSC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STH, SYSZ_INS_STH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STHH, SYSZ_INS_STHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STHRL, SYSZ_INS_STHRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STHY, SYSZ_INS_STHY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STIDP, SYSZ_INS_STIDP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STM, SYSZ_INS_STM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STMG, SYSZ_INS_STMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STMH, SYSZ_INS_STMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STMY, SYSZ_INS_STMY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STNSM, SYSZ_INS_STNSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsm, SYSZ_INS_STOC, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmE, SYSZ_INS_STOCE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmH, SYSZ_INS_STOCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmHE, SYSZ_INS_STOCHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmL, SYSZ_INS_STOCL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmLE, SYSZ_INS_STOCLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmLH, SYSZ_INS_STOCLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmM, SYSZ_INS_STOCM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNE, SYSZ_INS_STOCNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNH, SYSZ_INS_STOCNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNHE, SYSZ_INS_STOCNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNL, SYSZ_INS_STOCNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNLE, SYSZ_INS_STOCNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNLH, SYSZ_INS_STOCNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNM, SYSZ_INS_STOCNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNO, SYSZ_INS_STOCNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNP, SYSZ_INS_STOCNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmNZ, SYSZ_INS_STOCNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmO, SYSZ_INS_STOCO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmP, SYSZ_INS_STOCP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCAsmZ, SYSZ_INS_STOCZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsm, SYSZ_INS_STOCFH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmE, SYSZ_INS_STOCFHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmH, SYSZ_INS_STOCFHH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmHE, SYSZ_INS_STOCFHHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmL, SYSZ_INS_STOCFHL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmLE, SYSZ_INS_STOCFHLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmLH, SYSZ_INS_STOCFHLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmM, SYSZ_INS_STOCFHM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNE, SYSZ_INS_STOCFHNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNH, SYSZ_INS_STOCFHNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNHE, SYSZ_INS_STOCFHNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNL, SYSZ_INS_STOCFHNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNLE, SYSZ_INS_STOCFHNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNLH, SYSZ_INS_STOCFHNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNM, SYSZ_INS_STOCFHNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNO, SYSZ_INS_STOCFHNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNP, SYSZ_INS_STOCFHNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmNZ, SYSZ_INS_STOCFHNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmO, SYSZ_INS_STOCFHO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmP, SYSZ_INS_STOCFHP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCFHAsmZ, SYSZ_INS_STOCFHZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsm, SYSZ_INS_STOCG, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmE, SYSZ_INS_STOCGE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmH, SYSZ_INS_STOCGH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmHE, SYSZ_INS_STOCGHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmL, SYSZ_INS_STOCGL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmLE, SYSZ_INS_STOCGLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmLH, SYSZ_INS_STOCGLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmM, SYSZ_INS_STOCGM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNE, SYSZ_INS_STOCGNE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNH, SYSZ_INS_STOCGNH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNHE, SYSZ_INS_STOCGNHE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNL, SYSZ_INS_STOCGNL, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNLE, SYSZ_INS_STOCGNLE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNLH, SYSZ_INS_STOCGNLH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNM, SYSZ_INS_STOCGNM, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNO, SYSZ_INS_STOCGNO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNP, SYSZ_INS_STOCGNP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmNZ, SYSZ_INS_STOCGNZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmO, SYSZ_INS_STOCGO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmP, SYSZ_INS_STOCGP, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOCGAsmZ, SYSZ_INS_STOCGZ, -#ifndef CAPSTONE_DIET - { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 -#endif -}, -{ - SystemZ_STOSM, SYSZ_INS_STOSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STPQ, SYSZ_INS_STPQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STPT, SYSZ_INS_STPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STPX, SYSZ_INS_STPX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRAG, SYSZ_INS_STRAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRL, SYSZ_INS_STRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRV, SYSZ_INS_STRV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRVG, SYSZ_INS_STRVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STRVH, SYSZ_INS_STRVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STSCH, SYSZ_INS_STSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STSI, SYSZ_INS_STSI, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STURA, SYSZ_INS_STURA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STURG, SYSZ_INS_STURG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_STY, SYSZ_INS_STY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SU, SYSZ_INS_SU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SUR, SYSZ_INS_SUR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SVC, SYSZ_INS_SVC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SW, SYSZ_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SWR, SYSZ_INS_SWR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SXBR, SYSZ_INS_SXBR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SXR, SYSZ_INS_SXR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SXTR, SYSZ_INS_SXTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_SXTRA, SYSZ_INS_SXTRA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_SY, SYSZ_INS_SY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TABORT, SYSZ_INS_TABORT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_TAM, SYSZ_INS_TAM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TAR, SYSZ_INS_TAR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TB, SYSZ_INS_TB, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TBDR, SYSZ_INS_TBDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TBEDR, SYSZ_INS_TBEDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TBEGIN, SYSZ_INS_TBEGIN, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_TBEGINC, SYSZ_INS_TBEGINC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_TCDB, SYSZ_INS_TCDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TCEB, SYSZ_INS_TCEB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TCXB, SYSZ_INS_TCXB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDCDT, SYSZ_INS_TDCDT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDCET, SYSZ_INS_TDCET, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDCXT, SYSZ_INS_TDCXT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDGDT, SYSZ_INS_TDGDT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDGET, SYSZ_INS_TDGET, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TDGXT, SYSZ_INS_TDGXT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TEND, SYSZ_INS_TEND, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 -#endif -}, -{ - SystemZ_THDER, SYSZ_INS_THDER, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_THDR, SYSZ_INS_THDR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TM, SYSZ_INS_TM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMHH, SYSZ_INS_TMHH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMHL, SYSZ_INS_TMHL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMLH, SYSZ_INS_TMLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMLL, SYSZ_INS_TMLL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TMY, SYSZ_INS_TMY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TP, SYSZ_INS_TP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TPI, SYSZ_INS_TPI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TPROT, SYSZ_INS_TPROT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TR, SYSZ_INS_TR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRACE, SYSZ_INS_TRACE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRACG, SYSZ_INS_TRACG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRAP2, SYSZ_INS_TRAP2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRAP4, SYSZ_INS_TRAP4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRE, SYSZ_INS_TRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TROO, SYSZ_INS_TROO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TROOOpt, SYSZ_INS_TROO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TROT, SYSZ_INS_TROT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TROTOpt, SYSZ_INS_TROT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRT, SYSZ_INS_TRT, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTE, SYSZ_INS_TRTE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTEOpt, SYSZ_INS_TRTE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTO, SYSZ_INS_TRTO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTOOpt, SYSZ_INS_TRTO, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTR, SYSZ_INS_TRTR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTRE, SYSZ_INS_TRTRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTREOpt, SYSZ_INS_TRTRE, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTT, SYSZ_INS_TRTT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TRTTOpt, SYSZ_INS_TRTT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TS, SYSZ_INS_TS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_TSCH, SYSZ_INS_TSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_UNPK, SYSZ_INS_UNPK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_UNPKA, SYSZ_INS_UNPKA, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_UNPKU, SYSZ_INS_UNPKU, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_UPT, SYSZ_INS_UPT, -#ifndef CAPSTONE_DIET - { SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_4, SYSZ_REG_5, 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_5, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_VA, SYSZ_INS_VA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAB, SYSZ_INS_VAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAC, SYSZ_INS_VAC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACC, SYSZ_INS_VACC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCB, SYSZ_INS_VACCB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCC, SYSZ_INS_VACCC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCCQ, SYSZ_INS_VACCCQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCF, SYSZ_INS_VACCF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCG, SYSZ_INS_VACCG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCH, SYSZ_INS_VACCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACCQ, SYSZ_INS_VACCQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VACQ, SYSZ_INS_VACQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAF, SYSZ_INS_VAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAG, SYSZ_INS_VAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAH, SYSZ_INS_VAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAP, SYSZ_INS_VAP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAQ, SYSZ_INS_VAQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVG, SYSZ_INS_VAVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGB, SYSZ_INS_VAVGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGF, SYSZ_INS_VAVGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGG, SYSZ_INS_VAVGG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGH, SYSZ_INS_VAVGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGL, SYSZ_INS_VAVGL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGLB, SYSZ_INS_VAVGLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGLF, SYSZ_INS_VAVGLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGLG, SYSZ_INS_VAVGLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VAVGLH, SYSZ_INS_VAVGLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VBPERM, SYSZ_INS_VBPERM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCDG, SYSZ_INS_VCDG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCDGB, SYSZ_INS_VCDGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCDLG, SYSZ_INS_VCDLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCDLGB, SYSZ_INS_VCDLGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQ, SYSZ_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQB, SYSZ_INS_VCEQB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQBS, SYSZ_INS_VCEQBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQF, SYSZ_INS_VCEQF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQFS, SYSZ_INS_VCEQFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQG, SYSZ_INS_VCEQG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQGS, SYSZ_INS_VCEQGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQH, SYSZ_INS_VCEQH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCEQHS, SYSZ_INS_VCEQHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCGD, SYSZ_INS_VCGD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCGDB, SYSZ_INS_VCGDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCH, SYSZ_INS_VCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHB, SYSZ_INS_VCHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHBS, SYSZ_INS_VCHBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHF, SYSZ_INS_VCHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHFS, SYSZ_INS_VCHFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHG, SYSZ_INS_VCHG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHGS, SYSZ_INS_VCHGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHH, SYSZ_INS_VCHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHHS, SYSZ_INS_VCHHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHL, SYSZ_INS_VCHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLB, SYSZ_INS_VCHLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLBS, SYSZ_INS_VCHLBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLF, SYSZ_INS_VCHLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLFS, SYSZ_INS_VCHLFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLG, SYSZ_INS_VCHLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLGS, SYSZ_INS_VCHLGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLH, SYSZ_INS_VCHLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCHLHS, SYSZ_INS_VCHLHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCKSM, SYSZ_INS_VCKSM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLGD, SYSZ_INS_VCLGD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLGDB, SYSZ_INS_VCLGDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZ, SYSZ_INS_VCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZB, SYSZ_INS_VCLZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZF, SYSZ_INS_VCLZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZG, SYSZ_INS_VCLZG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCLZH, SYSZ_INS_VCLZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCP, SYSZ_INS_VCP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZ, SYSZ_INS_VCTZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZB, SYSZ_INS_VCTZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZF, SYSZ_INS_VCTZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZG, SYSZ_INS_VCTZG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCTZH, SYSZ_INS_VCTZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCVB, SYSZ_INS_VCVB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCVBG, SYSZ_INS_VCVBG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCVD, SYSZ_INS_VCVD, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VCVDG, SYSZ_INS_VCVDG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VDP, SYSZ_INS_VDP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VEC, SYSZ_INS_VEC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECB, SYSZ_INS_VECB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECF, SYSZ_INS_VECF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECG, SYSZ_INS_VECG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECH, SYSZ_INS_VECH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECL, SYSZ_INS_VECL, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECLB, SYSZ_INS_VECLB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECLF, SYSZ_INS_VECLF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECLG, SYSZ_INS_VECLG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VECLH, SYSZ_INS_VECLH, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIM, SYSZ_INS_VERIM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIMB, SYSZ_INS_VERIMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIMF, SYSZ_INS_VERIMF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIMG, SYSZ_INS_VERIMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERIMH, SYSZ_INS_VERIMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLL, SYSZ_INS_VERLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLB, SYSZ_INS_VERLLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLF, SYSZ_INS_VERLLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLG, SYSZ_INS_VERLLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLH, SYSZ_INS_VERLLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLV, SYSZ_INS_VERLLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLVB, SYSZ_INS_VERLLVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLVF, SYSZ_INS_VERLLVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLVG, SYSZ_INS_VERLLVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VERLLVH, SYSZ_INS_VERLLVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESL, SYSZ_INS_VESL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLB, SYSZ_INS_VESLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLF, SYSZ_INS_VESLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLG, SYSZ_INS_VESLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLH, SYSZ_INS_VESLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLV, SYSZ_INS_VESLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLVB, SYSZ_INS_VESLVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLVF, SYSZ_INS_VESLVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLVG, SYSZ_INS_VESLVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESLVH, SYSZ_INS_VESLVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRA, SYSZ_INS_VESRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAB, SYSZ_INS_VESRAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAF, SYSZ_INS_VESRAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAG, SYSZ_INS_VESRAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAH, SYSZ_INS_VESRAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAV, SYSZ_INS_VESRAV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAVB, SYSZ_INS_VESRAVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAVF, SYSZ_INS_VESRAVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAVG, SYSZ_INS_VESRAVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRAVH, SYSZ_INS_VESRAVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRL, SYSZ_INS_VESRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLB, SYSZ_INS_VESRLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLF, SYSZ_INS_VESRLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLG, SYSZ_INS_VESRLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLH, SYSZ_INS_VESRLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLV, SYSZ_INS_VESRLV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLVB, SYSZ_INS_VESRLVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLVF, SYSZ_INS_VESRLVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLVG, SYSZ_INS_VESRLVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VESRLVH, SYSZ_INS_VESRLVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFA, SYSZ_INS_VFA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFADB, SYSZ_INS_VFADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAE, SYSZ_INS_VFAE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEB, SYSZ_INS_VFAEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEBS, SYSZ_INS_VFAEBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEF, SYSZ_INS_VFAEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEFS, SYSZ_INS_VFAEFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEH, SYSZ_INS_VFAEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEHS, SYSZ_INS_VFAEHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZB, SYSZ_INS_VFAEZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZBS, SYSZ_INS_VFAEZBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZF, SYSZ_INS_VFAEZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZFS, SYSZ_INS_VFAEZFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZH, SYSZ_INS_VFAEZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFAEZHS, SYSZ_INS_VFAEZHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFASB, SYSZ_INS_VFASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCE, SYSZ_INS_VFCE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCEDB, SYSZ_INS_VFCEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCEDBS, SYSZ_INS_VFCEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCESB, SYSZ_INS_VFCESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCESBS, SYSZ_INS_VFCESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCH, SYSZ_INS_VFCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHDB, SYSZ_INS_VFCHDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHDBS, SYSZ_INS_VFCHDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHE, SYSZ_INS_VFCHE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHEDB, SYSZ_INS_VFCHEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHEDBS, SYSZ_INS_VFCHEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHESB, SYSZ_INS_VFCHESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHESBS, SYSZ_INS_VFCHESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHSB, SYSZ_INS_VFCHSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFCHSBS, SYSZ_INS_VFCHSBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFD, SYSZ_INS_VFD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFDDB, SYSZ_INS_VFDDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFDSB, SYSZ_INS_VFDSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEE, SYSZ_INS_VFEE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEB, SYSZ_INS_VFEEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEBS, SYSZ_INS_VFEEBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEF, SYSZ_INS_VFEEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEFS, SYSZ_INS_VFEEFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEH, SYSZ_INS_VFEEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEHS, SYSZ_INS_VFEEHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZB, SYSZ_INS_VFEEZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZBS, SYSZ_INS_VFEEZBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZF, SYSZ_INS_VFEEZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZFS, SYSZ_INS_VFEEZFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZH, SYSZ_INS_VFEEZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFEEZHS, SYSZ_INS_VFEEZHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENE, SYSZ_INS_VFENE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEB, SYSZ_INS_VFENEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEBS, SYSZ_INS_VFENEBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEF, SYSZ_INS_VFENEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEFS, SYSZ_INS_VFENEFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEH, SYSZ_INS_VFENEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEHS, SYSZ_INS_VFENEHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZB, SYSZ_INS_VFENEZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZBS, SYSZ_INS_VFENEZBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZF, SYSZ_INS_VFENEZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZFS, SYSZ_INS_VFENEZFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZH, SYSZ_INS_VFENEZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFENEZHS, SYSZ_INS_VFENEZHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFI, SYSZ_INS_VFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFIDB, SYSZ_INS_VFIDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFISB, SYSZ_INS_VFISB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKEDB, SYSZ_INS_VFKEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKEDBS, SYSZ_INS_VFKEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKESB, SYSZ_INS_VFKESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKESBS, SYSZ_INS_VFKESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHDB, SYSZ_INS_VFKHDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHDBS, SYSZ_INS_VFKHDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHEDB, SYSZ_INS_VFKHEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHEDBS, SYSZ_INS_VFKHEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHESB, SYSZ_INS_VFKHESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHESBS, SYSZ_INS_VFKHESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHSB, SYSZ_INS_VFKHSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFKHSBS, SYSZ_INS_VFKHSBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLCDB, SYSZ_INS_VFLCDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLCSB, SYSZ_INS_VFLCSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLL, SYSZ_INS_VFLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLLS, SYSZ_INS_VFLLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLNDB, SYSZ_INS_VFLNDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLNSB, SYSZ_INS_VFLNSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLPDB, SYSZ_INS_VFLPDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLPSB, SYSZ_INS_VFLPSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLR, SYSZ_INS_VFLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFLRD, SYSZ_INS_VFLRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFM, SYSZ_INS_VFM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMA, SYSZ_INS_VFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMADB, SYSZ_INS_VFMADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMASB, SYSZ_INS_VFMASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMAX, SYSZ_INS_VFMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMAXDB, SYSZ_INS_VFMAXDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMAXSB, SYSZ_INS_VFMAXSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMDB, SYSZ_INS_VFMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMIN, SYSZ_INS_VFMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMINDB, SYSZ_INS_VFMINDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMINSB, SYSZ_INS_VFMINSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMS, SYSZ_INS_VFMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMSB, SYSZ_INS_VFMSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMSDB, SYSZ_INS_VFMSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFMSSB, SYSZ_INS_VFMSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMA, SYSZ_INS_VFNMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMADB, SYSZ_INS_VFNMADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMASB, SYSZ_INS_VFNMASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMS, SYSZ_INS_VFNMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMSDB, SYSZ_INS_VFNMSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFNMSSB, SYSZ_INS_VFNMSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFPSO, SYSZ_INS_VFPSO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFPSODB, SYSZ_INS_VFPSODB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFPSOSB, SYSZ_INS_VFPSOSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFS, SYSZ_INS_VFS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSDB, SYSZ_INS_VFSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSQ, SYSZ_INS_VFSQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSQDB, SYSZ_INS_VFSQDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSQSB, SYSZ_INS_VFSQSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFSSB, SYSZ_INS_VFSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFTCI, SYSZ_INS_VFTCI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFTCIDB, SYSZ_INS_VFTCIDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VFTCISB, SYSZ_INS_VFTCISB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGBM, SYSZ_INS_VGBM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGEF, SYSZ_INS_VGEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGEG, SYSZ_INS_VGEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFM, SYSZ_INS_VGFM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMA, SYSZ_INS_VGFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMAB, SYSZ_INS_VGFMAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMAF, SYSZ_INS_VGFMAF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMAG, SYSZ_INS_VGFMAG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMAH, SYSZ_INS_VGFMAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMB, SYSZ_INS_VGFMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMF, SYSZ_INS_VGFMF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMG, SYSZ_INS_VGFMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGFMH, SYSZ_INS_VGFMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGM, SYSZ_INS_VGM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGMB, SYSZ_INS_VGMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGMF, SYSZ_INS_VGMF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGMG, SYSZ_INS_VGMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VGMH, SYSZ_INS_VGMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTR, SYSZ_INS_VISTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRB, SYSZ_INS_VISTRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRBS, SYSZ_INS_VISTRBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRF, SYSZ_INS_VISTRF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRFS, SYSZ_INS_VISTRFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRH, SYSZ_INS_VISTRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VISTRHS, SYSZ_INS_VISTRHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VL, SYSZ_INS_VL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLBB, SYSZ_INS_VLBB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLC, SYSZ_INS_VLC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLCB, SYSZ_INS_VLCB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLCF, SYSZ_INS_VLCF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLCG, SYSZ_INS_VLCG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLCH, SYSZ_INS_VLCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLDE, SYSZ_INS_VLDE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLDEB, SYSZ_INS_VLDEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEB, SYSZ_INS_VLEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLED, SYSZ_INS_VLED, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEDB, SYSZ_INS_VLEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEF, SYSZ_INS_VLEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEG, SYSZ_INS_VLEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEH, SYSZ_INS_VLEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEIB, SYSZ_INS_VLEIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEIF, SYSZ_INS_VLEIF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEIG, SYSZ_INS_VLEIG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLEIH, SYSZ_INS_VLEIH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGV, SYSZ_INS_VLGV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGVB, SYSZ_INS_VLGVB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGVF, SYSZ_INS_VLGVF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGVG, SYSZ_INS_VLGVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLGVH, SYSZ_INS_VLGVH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLIP, SYSZ_INS_VLIP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLL, SYSZ_INS_VLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZ, SYSZ_INS_VLLEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZB, SYSZ_INS_VLLEZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZF, SYSZ_INS_VLLEZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZG, SYSZ_INS_VLLEZG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZH, SYSZ_INS_VLLEZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLLEZLF, SYSZ_INS_VLLEZLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLM, SYSZ_INS_VLM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLP, SYSZ_INS_VLP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLPB, SYSZ_INS_VLPB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLPF, SYSZ_INS_VLPF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLPG, SYSZ_INS_VLPG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLPH, SYSZ_INS_VLPH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLR, SYSZ_INS_VLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREP, SYSZ_INS_VLREP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREPB, SYSZ_INS_VLREPB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREPF, SYSZ_INS_VLREPF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREPG, SYSZ_INS_VLREPG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLREPH, SYSZ_INS_VLREPH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLRL, SYSZ_INS_VLRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLRLR, SYSZ_INS_VLRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVG, SYSZ_INS_VLVG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGB, SYSZ_INS_VLVGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGF, SYSZ_INS_VLVGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGG, SYSZ_INS_VLVGG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGH, SYSZ_INS_VLVGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VLVGP, SYSZ_INS_VLVGP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAE, SYSZ_INS_VMAE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAEB, SYSZ_INS_VMAEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAEF, SYSZ_INS_VMAEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAEH, SYSZ_INS_VMAEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAH, SYSZ_INS_VMAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAHB, SYSZ_INS_VMAHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAHF, SYSZ_INS_VMAHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAHH, SYSZ_INS_VMAHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAL, SYSZ_INS_VMAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALB, SYSZ_INS_VMALB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALE, SYSZ_INS_VMALE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALEB, SYSZ_INS_VMALEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALEF, SYSZ_INS_VMALEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALEH, SYSZ_INS_VMALEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALF, SYSZ_INS_VMALF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALH, SYSZ_INS_VMALH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALHB, SYSZ_INS_VMALHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALHF, SYSZ_INS_VMALHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALHH, SYSZ_INS_VMALHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALHW, SYSZ_INS_VMALHW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALO, SYSZ_INS_VMALO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALOB, SYSZ_INS_VMALOB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALOF, SYSZ_INS_VMALOF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMALOH, SYSZ_INS_VMALOH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAO, SYSZ_INS_VMAO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAOB, SYSZ_INS_VMAOB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAOF, SYSZ_INS_VMAOF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMAOH, SYSZ_INS_VMAOH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VME, SYSZ_INS_VME, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMEB, SYSZ_INS_VMEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMEF, SYSZ_INS_VMEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMEH, SYSZ_INS_VMEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMH, SYSZ_INS_VMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMHB, SYSZ_INS_VMHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMHF, SYSZ_INS_VMHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMHH, SYSZ_INS_VMHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VML, SYSZ_INS_VML, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLB, SYSZ_INS_VMLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLE, SYSZ_INS_VMLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLEB, SYSZ_INS_VMLEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLEF, SYSZ_INS_VMLEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLEH, SYSZ_INS_VMLEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLF, SYSZ_INS_VMLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLH, SYSZ_INS_VMLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLHB, SYSZ_INS_VMLHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLHF, SYSZ_INS_VMLHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLHH, SYSZ_INS_VMLHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLHW, SYSZ_INS_VMLHW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLO, SYSZ_INS_VMLO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLOB, SYSZ_INS_VMLOB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLOF, SYSZ_INS_VMLOF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMLOH, SYSZ_INS_VMLOH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMN, SYSZ_INS_VMN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNB, SYSZ_INS_VMNB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNF, SYSZ_INS_VMNF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNG, SYSZ_INS_VMNG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNH, SYSZ_INS_VMNH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNL, SYSZ_INS_VMNL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNLB, SYSZ_INS_VMNLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNLF, SYSZ_INS_VMNLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNLG, SYSZ_INS_VMNLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMNLH, SYSZ_INS_VMNLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMO, SYSZ_INS_VMO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMOB, SYSZ_INS_VMOB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMOF, SYSZ_INS_VMOF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMOH, SYSZ_INS_VMOH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMP, SYSZ_INS_VMP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRH, SYSZ_INS_VMRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRHB, SYSZ_INS_VMRHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRHF, SYSZ_INS_VMRHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRHG, SYSZ_INS_VMRHG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRHH, SYSZ_INS_VMRHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRL, SYSZ_INS_VMRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRLB, SYSZ_INS_VMRLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRLF, SYSZ_INS_VMRLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRLG, SYSZ_INS_VMRLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMRLH, SYSZ_INS_VMRLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMSL, SYSZ_INS_VMSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMSLG, SYSZ_INS_VMSLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMSP, SYSZ_INS_VMSP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMX, SYSZ_INS_VMX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXB, SYSZ_INS_VMXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXF, SYSZ_INS_VMXF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXG, SYSZ_INS_VMXG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXH, SYSZ_INS_VMXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXL, SYSZ_INS_VMXL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXLB, SYSZ_INS_VMXLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXLF, SYSZ_INS_VMXLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXLG, SYSZ_INS_VMXLG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VMXLH, SYSZ_INS_VMXLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VN, SYSZ_INS_VN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VNC, SYSZ_INS_VNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VNN, SYSZ_INS_VNN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VNO, SYSZ_INS_VNO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VNX, SYSZ_INS_VNX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VO, SYSZ_INS_VO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VOC, SYSZ_INS_VOC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VONE, SYSZ_INS_VONE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPDI, SYSZ_INS_VPDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPERM, SYSZ_INS_VPERM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPK, SYSZ_INS_VPK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKF, SYSZ_INS_VPKF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKG, SYSZ_INS_VPKG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKH, SYSZ_INS_VPKH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLS, SYSZ_INS_VPKLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSF, SYSZ_INS_VPKLSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSFS, SYSZ_INS_VPKLSFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSG, SYSZ_INS_VPKLSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSGS, SYSZ_INS_VPKLSGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSH, SYSZ_INS_VPKLSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKLSHS, SYSZ_INS_VPKLSHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKS, SYSZ_INS_VPKS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSF, SYSZ_INS_VPKSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSFS, SYSZ_INS_VPKSFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSG, SYSZ_INS_VPKSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSGS, SYSZ_INS_VPKSGS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSH, SYSZ_INS_VPKSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKSHS, SYSZ_INS_VPKSHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPKZ, SYSZ_INS_VPKZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCT, SYSZ_INS_VPOPCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCTB, SYSZ_INS_VPOPCTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCTF, SYSZ_INS_VPOPCTF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCTG, SYSZ_INS_VPOPCTG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPOPCTH, SYSZ_INS_VPOPCTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VPSOP, SYSZ_INS_VPSOP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREP, SYSZ_INS_VREP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPB, SYSZ_INS_VREPB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPF, SYSZ_INS_VREPF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPG, SYSZ_INS_VREPG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPH, SYSZ_INS_VREPH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPI, SYSZ_INS_VREPI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPIB, SYSZ_INS_VREPIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPIF, SYSZ_INS_VREPIF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPIG, SYSZ_INS_VREPIG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VREPIH, SYSZ_INS_VREPIH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VRP, SYSZ_INS_VRP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VS, SYSZ_INS_VS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSB, SYSZ_INS_VSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSBCBI, SYSZ_INS_VSBCBI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSBCBIQ, SYSZ_INS_VSBCBIQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSBI, SYSZ_INS_VSBI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSBIQ, SYSZ_INS_VSBIQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBI, SYSZ_INS_VSCBI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIB, SYSZ_INS_VSCBIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIF, SYSZ_INS_VSCBIF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIG, SYSZ_INS_VSCBIG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIH, SYSZ_INS_VSCBIH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCBIQ, SYSZ_INS_VSCBIQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCEF, SYSZ_INS_VSCEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSCEG, SYSZ_INS_VSCEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSDP, SYSZ_INS_VSDP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEG, SYSZ_INS_VSEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEGB, SYSZ_INS_VSEGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEGF, SYSZ_INS_VSEGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEGH, SYSZ_INS_VSEGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSEL, SYSZ_INS_VSEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSF, SYSZ_INS_VSF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSG, SYSZ_INS_VSG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSH, SYSZ_INS_VSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSL, SYSZ_INS_VSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSLB, SYSZ_INS_VSLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSLDB, SYSZ_INS_VSLDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSP, SYSZ_INS_VSP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSQ, SYSZ_INS_VSQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRA, SYSZ_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRAB, SYSZ_INS_VSRAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRL, SYSZ_INS_VSRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRLB, SYSZ_INS_VSRLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSRP, SYSZ_INS_VSRP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VST, SYSZ_INS_VST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTEB, SYSZ_INS_VSTEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTEF, SYSZ_INS_VSTEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTEG, SYSZ_INS_VSTEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTEH, SYSZ_INS_VSTEH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTL, SYSZ_INS_VSTL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTM, SYSZ_INS_VSTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRC, SYSZ_INS_VSTRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCB, SYSZ_INS_VSTRCB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCBS, SYSZ_INS_VSTRCBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCF, SYSZ_INS_VSTRCF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCFS, SYSZ_INS_VSTRCFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCH, SYSZ_INS_VSTRCH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCHS, SYSZ_INS_VSTRCHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZB, SYSZ_INS_VSTRCZB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZBS, SYSZ_INS_VSTRCZBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZF, SYSZ_INS_VSTRCZF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZFS, SYSZ_INS_VSTRCZFS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZH, SYSZ_INS_VSTRCZH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRCZHS, SYSZ_INS_VSTRCZHS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRL, SYSZ_INS_VSTRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSTRLR, SYSZ_INS_VSTRLR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUM, SYSZ_INS_VSUM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMB, SYSZ_INS_VSUMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMG, SYSZ_INS_VSUMG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMGF, SYSZ_INS_VSUMGF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMGH, SYSZ_INS_VSUMGH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMH, SYSZ_INS_VSUMH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMQ, SYSZ_INS_VSUMQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMQF, SYSZ_INS_VSUMQF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VSUMQG, SYSZ_INS_VSUMQG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VTM, SYSZ_INS_VTM, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VTP, SYSZ_INS_VTP, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPH, SYSZ_INS_VUPH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPHB, SYSZ_INS_VUPHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPHF, SYSZ_INS_VUPHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPHH, SYSZ_INS_VUPHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPKZ, SYSZ_INS_VUPKZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPL, SYSZ_INS_VUPL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLB, SYSZ_INS_VUPLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLF, SYSZ_INS_VUPLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLH, SYSZ_INS_VUPLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLHB, SYSZ_INS_VUPLHB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLHF, SYSZ_INS_VUPLHF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLHH, SYSZ_INS_VUPLHH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLHW, SYSZ_INS_VUPLHW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLL, SYSZ_INS_VUPLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLLB, SYSZ_INS_VUPLLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLLF, SYSZ_INS_VUPLLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VUPLLH, SYSZ_INS_VUPLLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VX, SYSZ_INS_VX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_VZERO, SYSZ_INS_VZERO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WCDGB, SYSZ_INS_WCDGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WCDLGB, SYSZ_INS_WCDLGB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WCGDB, SYSZ_INS_WCGDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WCLGDB, SYSZ_INS_WCLGDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFADB, SYSZ_INS_WFADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFASB, SYSZ_INS_WFASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFAXB, SYSZ_INS_WFAXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFC, SYSZ_INS_WFC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCDB, SYSZ_INS_WFCDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCEDB, SYSZ_INS_WFCEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCEDBS, SYSZ_INS_WFCEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCESB, SYSZ_INS_WFCESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCESBS, SYSZ_INS_WFCESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCEXB, SYSZ_INS_WFCEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCEXBS, SYSZ_INS_WFCEXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHDB, SYSZ_INS_WFCHDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHDBS, SYSZ_INS_WFCHDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHEDB, SYSZ_INS_WFCHEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHEDBS, SYSZ_INS_WFCHEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHESB, SYSZ_INS_WFCHESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHESBS, SYSZ_INS_WFCHESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHEXB, SYSZ_INS_WFCHEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHEXBS, SYSZ_INS_WFCHEXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHSB, SYSZ_INS_WFCHSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHSBS, SYSZ_INS_WFCHSBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHXB, SYSZ_INS_WFCHXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCHXBS, SYSZ_INS_WFCHXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCSB, SYSZ_INS_WFCSB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFCXB, SYSZ_INS_WFCXB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFDDB, SYSZ_INS_WFDDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFDSB, SYSZ_INS_WFDSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFDXB, SYSZ_INS_WFDXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFIDB, SYSZ_INS_WFIDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFISB, SYSZ_INS_WFISB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFIXB, SYSZ_INS_WFIXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFK, SYSZ_INS_WFK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKDB, SYSZ_INS_WFKDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKEDB, SYSZ_INS_WFKEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKEDBS, SYSZ_INS_WFKEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKESB, SYSZ_INS_WFKESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKESBS, SYSZ_INS_WFKESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKEXB, SYSZ_INS_WFKEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKEXBS, SYSZ_INS_WFKEXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHDB, SYSZ_INS_WFKHDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHDBS, SYSZ_INS_WFKHDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHEDB, SYSZ_INS_WFKHEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHEDBS, SYSZ_INS_WFKHEDBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHESB, SYSZ_INS_WFKHESB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHESBS, SYSZ_INS_WFKHESBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHEXB, SYSZ_INS_WFKHEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHEXBS, SYSZ_INS_WFKHEXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHSB, SYSZ_INS_WFKHSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHSBS, SYSZ_INS_WFKHSBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHXB, SYSZ_INS_WFKHXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKHXBS, SYSZ_INS_WFKHXBS, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKSB, SYSZ_INS_WFKSB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFKXB, SYSZ_INS_WFKXB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLCDB, SYSZ_INS_WFLCDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLCSB, SYSZ_INS_WFLCSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLCXB, SYSZ_INS_WFLCXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLLD, SYSZ_INS_WFLLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLLS, SYSZ_INS_WFLLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLNDB, SYSZ_INS_WFLNDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLNSB, SYSZ_INS_WFLNSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLNXB, SYSZ_INS_WFLNXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLPDB, SYSZ_INS_WFLPDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLPSB, SYSZ_INS_WFLPSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLPXB, SYSZ_INS_WFLPXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLRD, SYSZ_INS_WFLRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFLRX, SYSZ_INS_WFLRX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMADB, SYSZ_INS_WFMADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMASB, SYSZ_INS_WFMASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMAXB, SYSZ_INS_WFMAXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMAXDB, SYSZ_INS_WFMAXDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMAXSB, SYSZ_INS_WFMAXSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMAXXB, SYSZ_INS_WFMAXXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMDB, SYSZ_INS_WFMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMINDB, SYSZ_INS_WFMINDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMINSB, SYSZ_INS_WFMINSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMINXB, SYSZ_INS_WFMINXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMSB, SYSZ_INS_WFMSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMSDB, SYSZ_INS_WFMSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMSSB, SYSZ_INS_WFMSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMSXB, SYSZ_INS_WFMSXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFMXB, SYSZ_INS_WFMXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMADB, SYSZ_INS_WFNMADB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMASB, SYSZ_INS_WFNMASB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMAXB, SYSZ_INS_WFNMAXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMSDB, SYSZ_INS_WFNMSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMSSB, SYSZ_INS_WFNMSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFNMSXB, SYSZ_INS_WFNMSXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFPSODB, SYSZ_INS_WFPSODB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFPSOSB, SYSZ_INS_WFPSOSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFPSOXB, SYSZ_INS_WFPSOXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSDB, SYSZ_INS_WFSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSQDB, SYSZ_INS_WFSQDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSQSB, SYSZ_INS_WFSQSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSQXB, SYSZ_INS_WFSQXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSSB, SYSZ_INS_WFSSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFSXB, SYSZ_INS_WFSXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFTCIDB, SYSZ_INS_WFTCIDB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFTCISB, SYSZ_INS_WFTCISB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WFTCIXB, SYSZ_INS_WFTCIXB, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WLDEB, SYSZ_INS_WLDEB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_WLEDB, SYSZ_INS_WLEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 -#endif -}, -{ - SystemZ_X, SYSZ_INS_X, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XC, SYSZ_INS_XC, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XG, SYSZ_INS_XG, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XGR, SYSZ_INS_XGR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XGRK, SYSZ_INS_XGRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_XI, SYSZ_INS_XI, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XIHF, SYSZ_INS_XIHF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XILF, SYSZ_INS_XILF, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XIY, SYSZ_INS_XIY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XR, SYSZ_INS_XR, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XRK, SYSZ_INS_XRK, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 -#endif -}, -{ - SystemZ_XSCH, SYSZ_INS_XSCH, -#ifndef CAPSTONE_DIET - { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, -{ - SystemZ_XY, SYSZ_INS_XY, -#ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 +{SystemZ_A, SYSZ_INS_A, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif +}, + {SystemZ_AD, SYSZ_INS_AD, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_ADB, + SYSZ_INS_ADB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ADBR, + SYSZ_INS_ADBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ADR, + SYSZ_INS_ADR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ADTR, + SYSZ_INS_ADTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ADTRA, + SYSZ_INS_ADTRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_AE, SYSZ_INS_AE, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_AEB, + SYSZ_INS_AEB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AEBR, + SYSZ_INS_AEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AER, + SYSZ_INS_AER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AFI, + SYSZ_INS_AFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AG, SYSZ_INS_AG, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_AGF, + SYSZ_INS_AGF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AGFI, + SYSZ_INS_AGFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AGFR, + SYSZ_INS_AGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AGH, + SYSZ_INS_AGH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 0, + 0 +#endif + }, + {SystemZ_AGHI, + SYSZ_INS_AGHI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AGHIK, + SYSZ_INS_AGHIK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_AGR, + SYSZ_INS_AGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AGRK, + SYSZ_INS_AGRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_AGSI, + SYSZ_INS_AGSI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AH, SYSZ_INS_AH, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_AHHHR, + SYSZ_INS_AHHHR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_AHHLR, + SYSZ_INS_AHHLR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_AHI, + SYSZ_INS_AHI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AHIK, + SYSZ_INS_AHIK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_AHY, + SYSZ_INS_AHY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AIH, + SYSZ_INS_AIH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_AL, SYSZ_INS_AL, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_ALC, + SYSZ_INS_ALC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALCG, + SYSZ_INS_ALCG, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALCGR, + SYSZ_INS_ALCGR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALCR, + SYSZ_INS_ALCR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALFI, + SYSZ_INS_ALFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALG, + SYSZ_INS_ALG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALGF, + SYSZ_INS_ALGF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALGFI, + SYSZ_INS_ALGFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALGFR, + SYSZ_INS_ALGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALGHSIK, + SYSZ_INS_ALGHSIK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_ALGR, + SYSZ_INS_ALGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALGRK, + SYSZ_INS_ALGRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_ALGSI, + SYSZ_INS_ALGSI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALHHHR, + SYSZ_INS_ALHHHR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_ALHHLR, + SYSZ_INS_ALHHLR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_ALHSIK, + SYSZ_INS_ALHSIK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_ALR, + SYSZ_INS_ALR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALRK, + SYSZ_INS_ALRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_ALSI, + SYSZ_INS_ALSI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ALSIH, + SYSZ_INS_ALSIH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_ALSIHN, + SYSZ_INS_ALSIHN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_ALY, + SYSZ_INS_ALY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AP, SYSZ_INS_AP, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_AR, SYSZ_INS_AR, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_ARK, + SYSZ_INS_ARK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_ASI, + SYSZ_INS_ASI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AU, SYSZ_INS_AU, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_AUR, + SYSZ_INS_AUR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AW, SYSZ_INS_AW, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_AWR, + SYSZ_INS_AWR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AXBR, + SYSZ_INS_AXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AXR, + SYSZ_INS_AXR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AXTR, + SYSZ_INS_AXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_AXTRA, + SYSZ_INS_AXTRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_AY, SYSZ_INS_AY, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_B, SYSZ_INS_B, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, + 1, 1 +#endif + }, + {SystemZ_BAKR, + SYSZ_INS_BAKR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BAL, + SYSZ_INS_BAL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BALR, + SYSZ_INS_BALR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BAS, + SYSZ_INS_BAS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BASR, + SYSZ_INS_BASR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BASSM, + SYSZ_INS_BASSM, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BAsmE, + SYSZ_INS_BE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmH, + SYSZ_INS_BH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmHE, + SYSZ_INS_BHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmL, + SYSZ_INS_BL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmLE, + SYSZ_INS_BLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmLH, + SYSZ_INS_BLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmM, + SYSZ_INS_BM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNE, + SYSZ_INS_BNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNH, + SYSZ_INS_BNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNHE, + SYSZ_INS_BNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNL, + SYSZ_INS_BNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNLE, + SYSZ_INS_BNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNLH, + SYSZ_INS_BNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNM, + SYSZ_INS_BNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNO, + SYSZ_INS_BNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNP, + SYSZ_INS_BNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmNZ, + SYSZ_INS_BNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmO, + SYSZ_INS_BO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmP, + SYSZ_INS_BP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BAsmZ, + SYSZ_INS_BZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BCAsm, + SYSZ_INS_BC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BCRAsm, + SYSZ_INS_BCR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BCT, + SYSZ_INS_BCT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BCTG, + SYSZ_INS_BCTG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BCTGR, + SYSZ_INS_BCTGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BCTR, + SYSZ_INS_BCTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BI, SYSZ_INS_BI, +#ifndef CAPSTONE_DIET + {0}, {0}, {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, 1, + 1 +#endif + }, + {SystemZ_BIAsmE, + SYSZ_INS_BIE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmH, + SYSZ_INS_BIH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmHE, + SYSZ_INS_BIHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmL, + SYSZ_INS_BIL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmLE, + SYSZ_INS_BILE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmLH, + SYSZ_INS_BILH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmM, + SYSZ_INS_BIM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNE, + SYSZ_INS_BINE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNH, + SYSZ_INS_BINH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNHE, + SYSZ_INS_BINHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNL, + SYSZ_INS_BINL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNLE, + SYSZ_INS_BINLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNLH, + SYSZ_INS_BINLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNM, + SYSZ_INS_BINM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNO, + SYSZ_INS_BINO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNP, + SYSZ_INS_BINP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmNZ, + SYSZ_INS_BINZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmO, + SYSZ_INS_BIO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmP, + SYSZ_INS_BIP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BIAsmZ, + SYSZ_INS_BIZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BICAsm, + SYSZ_INS_BIC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 1, + 1 +#endif + }, + {SystemZ_BPP, + SYSZ_INS_BPP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_EXECUTIONHINT, 0}, + 0, + 0 +#endif + }, + {SystemZ_BPRP, + SYSZ_INS_BPRP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_EXECUTIONHINT, 0}, + 0, + 0 +#endif + }, + {SystemZ_BR, SYSZ_INS_BR, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 1, + 1 +#endif + }, + {SystemZ_BRAS, + SYSZ_INS_BRAS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BRASL, + SYSZ_INS_BRASL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BRAsmE, + SYSZ_INS_BER, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmH, + SYSZ_INS_BHR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmHE, + SYSZ_INS_BHER, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmL, + SYSZ_INS_BLR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmLE, + SYSZ_INS_BLER, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmLH, + SYSZ_INS_BLHR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmM, + SYSZ_INS_BMR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNE, + SYSZ_INS_BNER, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNH, + SYSZ_INS_BNHR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNHE, + SYSZ_INS_BNHER, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNL, + SYSZ_INS_BNLR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNLE, + SYSZ_INS_BNLER, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNLH, + SYSZ_INS_BNLHR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNM, + SYSZ_INS_BNMR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNO, + SYSZ_INS_BNOR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNP, + SYSZ_INS_BNPR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmNZ, + SYSZ_INS_BNZR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmO, + SYSZ_INS_BOR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmP, + SYSZ_INS_BPR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRAsmZ, + SYSZ_INS_BZR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_BRCAsm, + SYSZ_INS_BRC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BRCLAsm, + SYSZ_INS_BRCL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BRCT, + SYSZ_INS_BRCT, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BRCTG, + SYSZ_INS_BRCTG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BRCTH, + SYSZ_INS_BRCTH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 1, + 0 +#endif + }, + {SystemZ_BRXH, + SYSZ_INS_BRXH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BRXHG, + SYSZ_INS_BRXHG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BRXLE, + SYSZ_INS_BRXLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BRXLG, + SYSZ_INS_BRXLG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BSA, + SYSZ_INS_BSA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BSG, + SYSZ_INS_BSG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_BSM, + SYSZ_INS_BSM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BXH, + SYSZ_INS_BXH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BXHG, + SYSZ_INS_BXHG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BXLE, + SYSZ_INS_BXLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_BXLEG, + SYSZ_INS_BXLEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_C, SYSZ_INS_C, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CD, SYSZ_INS_CD, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CDB, + SYSZ_INS_CDB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDBR, + SYSZ_INS_CDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDFBR, + SYSZ_INS_CDFBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDFBRA, + SYSZ_INS_CDFBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CDFR, + SYSZ_INS_CDFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDFTR, + SYSZ_INS_CDFTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CDGBR, + SYSZ_INS_CDGBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDGBRA, + SYSZ_INS_CDGBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CDGR, + SYSZ_INS_CDGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDGTR, + SYSZ_INS_CDGTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDGTRA, + SYSZ_INS_CDGTRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CDLFBR, + SYSZ_INS_CDLFBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CDLFTR, + SYSZ_INS_CDLFTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CDLGBR, + SYSZ_INS_CDLGBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CDLGTR, + SYSZ_INS_CDLGTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CDPT, + SYSZ_INS_CDPT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DFPPACKEDCONVERSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CDR, + SYSZ_INS_CDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDS, + SYSZ_INS_CDS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDSG, + SYSZ_INS_CDSG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDSTR, + SYSZ_INS_CDSTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDSY, + SYSZ_INS_CDSY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDTR, + SYSZ_INS_CDTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDUTR, + SYSZ_INS_CDUTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CDZT, + SYSZ_INS_CDZT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DFPZONEDCONVERSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CE, SYSZ_INS_CE, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CEB, + SYSZ_INS_CEB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CEBR, + SYSZ_INS_CEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CEDTR, + SYSZ_INS_CEDTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CEFBR, + SYSZ_INS_CEFBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CEFBRA, + SYSZ_INS_CEFBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CEFR, + SYSZ_INS_CEFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CEGBR, + SYSZ_INS_CEGBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CEGBRA, + SYSZ_INS_CEGBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CEGR, + SYSZ_INS_CEGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CELFBR, + SYSZ_INS_CELFBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CELGBR, + SYSZ_INS_CELGBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CER, + SYSZ_INS_CER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CEXTR, + SYSZ_INS_CEXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CFC, + SYSZ_INS_CFC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0}, + {SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CFDBR, + SYSZ_INS_CFDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CFDBRA, + SYSZ_INS_CFDBRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CFDR, + SYSZ_INS_CFDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CFDTR, + SYSZ_INS_CFDTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CFEBR, + SYSZ_INS_CFEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CFEBRA, + SYSZ_INS_CFEBRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CFER, + SYSZ_INS_CFER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CFI, + SYSZ_INS_CFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CFXBR, + SYSZ_INS_CFXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CFXBRA, + SYSZ_INS_CFXBRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CFXR, + SYSZ_INS_CFXR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CFXTR, + SYSZ_INS_CFXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CG, SYSZ_INS_CG, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CGDBR, + SYSZ_INS_CGDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGDBRA, + SYSZ_INS_CGDBRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CGDR, + SYSZ_INS_CGDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGDTR, + SYSZ_INS_CGDTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGDTRA, + SYSZ_INS_CGDTRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CGEBR, + SYSZ_INS_CGEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGEBRA, + SYSZ_INS_CGEBRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CGER, + SYSZ_INS_CGER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGF, + SYSZ_INS_CGF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGFI, + SYSZ_INS_CGFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGFR, + SYSZ_INS_CGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGFRL, + SYSZ_INS_CGFRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGH, + SYSZ_INS_CGH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGHI, + SYSZ_INS_CGHI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGHRL, + SYSZ_INS_CGHRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGHSI, + SYSZ_INS_CGHSI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGIBAsm, + SYSZ_INS_CGIB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmE, + SYSZ_INS_CGIBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmH, + SYSZ_INS_CGIBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmHE, + SYSZ_INS_CGIBHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmL, + SYSZ_INS_CGIBL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmLE, + SYSZ_INS_CGIBLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmLH, + SYSZ_INS_CGIBLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmNE, + SYSZ_INS_CGIBNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmNH, + SYSZ_INS_CGIBNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmNHE, + SYSZ_INS_CGIBNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmNL, + SYSZ_INS_CGIBNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmNLE, + SYSZ_INS_CGIBNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIBAsmNLH, + SYSZ_INS_CGIBNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGIJAsm, + SYSZ_INS_CGIJ, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmE, + SYSZ_INS_CGIJE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmH, + SYSZ_INS_CGIJH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmHE, + SYSZ_INS_CGIJHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmL, + SYSZ_INS_CGIJL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmLE, + SYSZ_INS_CGIJLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmLH, + SYSZ_INS_CGIJLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmNE, + SYSZ_INS_CGIJNE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmNH, + SYSZ_INS_CGIJNH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmNHE, + SYSZ_INS_CGIJNHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmNL, + SYSZ_INS_CGIJNL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmNLE, + SYSZ_INS_CGIJNLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGIJAsmNLH, + SYSZ_INS_CGIJNLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGITAsm, + SYSZ_INS_CGIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmE, + SYSZ_INS_CGITE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmH, + SYSZ_INS_CGITH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmHE, + SYSZ_INS_CGITHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmL, + SYSZ_INS_CGITL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmLE, + SYSZ_INS_CGITLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmLH, + SYSZ_INS_CGITLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmNE, + SYSZ_INS_CGITNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmNH, + SYSZ_INS_CGITNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmNHE, + SYSZ_INS_CGITNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmNL, + SYSZ_INS_CGITNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmNLE, + SYSZ_INS_CGITNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGITAsmNLH, + SYSZ_INS_CGITNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGR, + SYSZ_INS_CGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRBAsm, + SYSZ_INS_CGRB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmE, + SYSZ_INS_CGRBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmH, + SYSZ_INS_CGRBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmHE, + SYSZ_INS_CGRBHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmL, + SYSZ_INS_CGRBL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmLE, + SYSZ_INS_CGRBLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmLH, + SYSZ_INS_CGRBLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmNE, + SYSZ_INS_CGRBNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmNH, + SYSZ_INS_CGRBNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmNHE, + SYSZ_INS_CGRBNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmNL, + SYSZ_INS_CGRBNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmNLE, + SYSZ_INS_CGRBNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRBAsmNLH, + SYSZ_INS_CGRBNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CGRJAsm, + SYSZ_INS_CGRJ, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmE, + SYSZ_INS_CGRJE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmH, + SYSZ_INS_CGRJH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmHE, + SYSZ_INS_CGRJHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmL, + SYSZ_INS_CGRJL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmLE, + SYSZ_INS_CGRJLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmLH, + SYSZ_INS_CGRJLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmNE, + SYSZ_INS_CGRJNE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmNH, + SYSZ_INS_CGRJNH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmNHE, + SYSZ_INS_CGRJNHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmNL, + SYSZ_INS_CGRJNL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmNLE, + SYSZ_INS_CGRJNLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRJAsmNLH, + SYSZ_INS_CGRJNLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CGRL, + SYSZ_INS_CGRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsm, + SYSZ_INS_CGRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmE, + SYSZ_INS_CGRTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmH, + SYSZ_INS_CGRTH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmHE, + SYSZ_INS_CGRTHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmL, + SYSZ_INS_CGRTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmLE, + SYSZ_INS_CGRTLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmLH, + SYSZ_INS_CGRTLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmNE, + SYSZ_INS_CGRTNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmNH, + SYSZ_INS_CGRTNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmNHE, + SYSZ_INS_CGRTNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmNL, + SYSZ_INS_CGRTNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmNLE, + SYSZ_INS_CGRTNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGRTAsmNLH, + SYSZ_INS_CGRTNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGXBR, + SYSZ_INS_CGXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGXBRA, + SYSZ_INS_CGXBRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CGXR, + SYSZ_INS_CGXR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGXTR, + SYSZ_INS_CGXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CGXTRA, + SYSZ_INS_CGXTRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CH, SYSZ_INS_CH, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CHF, + SYSZ_INS_CHF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_CHHR, + SYSZ_INS_CHHR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_CHHSI, + SYSZ_INS_CHHSI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CHI, + SYSZ_INS_CHI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CHLR, + SYSZ_INS_CHLR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_CHRL, + SYSZ_INS_CHRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CHSI, + SYSZ_INS_CHSI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CHY, + SYSZ_INS_CHY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CIBAsm, + SYSZ_INS_CIB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmE, + SYSZ_INS_CIBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmH, + SYSZ_INS_CIBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmHE, + SYSZ_INS_CIBHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmL, + SYSZ_INS_CIBL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmLE, + SYSZ_INS_CIBLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmLH, + SYSZ_INS_CIBLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmNE, + SYSZ_INS_CIBNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmNH, + SYSZ_INS_CIBNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmNHE, + SYSZ_INS_CIBNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmNL, + SYSZ_INS_CIBNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmNLE, + SYSZ_INS_CIBNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIBAsmNLH, + SYSZ_INS_CIBNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CIH, + SYSZ_INS_CIH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_CIJAsm, + SYSZ_INS_CIJ, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmE, + SYSZ_INS_CIJE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmH, + SYSZ_INS_CIJH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmHE, + SYSZ_INS_CIJHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmL, + SYSZ_INS_CIJL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmLE, + SYSZ_INS_CIJLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmLH, + SYSZ_INS_CIJLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmNE, + SYSZ_INS_CIJNE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmNH, + SYSZ_INS_CIJNH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmNHE, + SYSZ_INS_CIJNHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmNL, + SYSZ_INS_CIJNL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmNLE, + SYSZ_INS_CIJNLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CIJAsmNLH, + SYSZ_INS_CIJNLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CITAsm, + SYSZ_INS_CIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmE, + SYSZ_INS_CITE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmH, + SYSZ_INS_CITH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmHE, + SYSZ_INS_CITHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmL, + SYSZ_INS_CITL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmLE, + SYSZ_INS_CITLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmLH, + SYSZ_INS_CITLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmNE, + SYSZ_INS_CITNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmNH, + SYSZ_INS_CITNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmNHE, + SYSZ_INS_CITNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmNL, + SYSZ_INS_CITNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmNLE, + SYSZ_INS_CITNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CITAsmNLH, + SYSZ_INS_CITNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CKSM, + SYSZ_INS_CKSM, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CL, SYSZ_INS_CL, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CLC, + SYSZ_INS_CLC, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLCL, + SYSZ_INS_CLCL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLCLE, + SYSZ_INS_CLCLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLCLU, + SYSZ_INS_CLCLU, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFDBR, + SYSZ_INS_CLFDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLFDTR, + SYSZ_INS_CLFDTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLFEBR, + SYSZ_INS_CLFEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLFHSI, + SYSZ_INS_CLFHSI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFI, + SYSZ_INS_CLFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsm, + SYSZ_INS_CLFIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmE, + SYSZ_INS_CLFITE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmH, + SYSZ_INS_CLFITH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmHE, + SYSZ_INS_CLFITHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmL, + SYSZ_INS_CLFITL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmLE, + SYSZ_INS_CLFITLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmLH, + SYSZ_INS_CLFITLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmNE, + SYSZ_INS_CLFITNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmNH, + SYSZ_INS_CLFITNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmNHE, + SYSZ_INS_CLFITNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmNL, + SYSZ_INS_CLFITNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmNLE, + SYSZ_INS_CLFITNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFITAsmNLH, + SYSZ_INS_CLFITNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLFXBR, + SYSZ_INS_CLFXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLFXTR, + SYSZ_INS_CLFXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLG, + SYSZ_INS_CLG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGDBR, + SYSZ_INS_CLGDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGDTR, + SYSZ_INS_CLGDTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGEBR, + SYSZ_INS_CLGEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGF, + SYSZ_INS_CLGF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGFI, + SYSZ_INS_CLGFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGFR, + SYSZ_INS_CLGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGFRL, + SYSZ_INS_CLGFRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGHRL, + SYSZ_INS_CLGHRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGHSI, + SYSZ_INS_CLGHSI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGIBAsm, + SYSZ_INS_CLGIB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmE, + SYSZ_INS_CLGIBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmH, + SYSZ_INS_CLGIBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmHE, + SYSZ_INS_CLGIBHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmL, + SYSZ_INS_CLGIBL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmLE, + SYSZ_INS_CLGIBLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmLH, + SYSZ_INS_CLGIBLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmNE, + SYSZ_INS_CLGIBNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmNH, + SYSZ_INS_CLGIBNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmNHE, + SYSZ_INS_CLGIBNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmNL, + SYSZ_INS_CLGIBNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmNLE, + SYSZ_INS_CLGIBNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIBAsmNLH, + SYSZ_INS_CLGIBNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGIJAsm, + SYSZ_INS_CLGIJ, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmE, + SYSZ_INS_CLGIJE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmH, + SYSZ_INS_CLGIJH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmHE, + SYSZ_INS_CLGIJHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmL, + SYSZ_INS_CLGIJL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmLE, + SYSZ_INS_CLGIJLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmLH, + SYSZ_INS_CLGIJLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmNE, + SYSZ_INS_CLGIJNE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmNH, + SYSZ_INS_CLGIJNH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmNHE, + SYSZ_INS_CLGIJNHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmNL, + SYSZ_INS_CLGIJNL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmNLE, + SYSZ_INS_CLGIJNLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGIJAsmNLH, + SYSZ_INS_CLGIJNLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGITAsm, + SYSZ_INS_CLGIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmE, + SYSZ_INS_CLGITE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmH, + SYSZ_INS_CLGITH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmHE, + SYSZ_INS_CLGITHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmL, + SYSZ_INS_CLGITL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmLE, + SYSZ_INS_CLGITLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmLH, + SYSZ_INS_CLGITLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmNE, + SYSZ_INS_CLGITNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmNH, + SYSZ_INS_CLGITNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmNHE, + SYSZ_INS_CLGITNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmNL, + SYSZ_INS_CLGITNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmNLE, + SYSZ_INS_CLGITNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGITAsmNLH, + SYSZ_INS_CLGITNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGR, + SYSZ_INS_CLGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRBAsm, + SYSZ_INS_CLGRB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmE, + SYSZ_INS_CLGRBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmH, + SYSZ_INS_CLGRBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmHE, + SYSZ_INS_CLGRBHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmL, + SYSZ_INS_CLGRBL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmLE, + SYSZ_INS_CLGRBLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmLH, + SYSZ_INS_CLGRBLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmNE, + SYSZ_INS_CLGRBNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmNH, + SYSZ_INS_CLGRBNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmNHE, + SYSZ_INS_CLGRBNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmNL, + SYSZ_INS_CLGRBNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmNLE, + SYSZ_INS_CLGRBNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRBAsmNLH, + SYSZ_INS_CLGRBNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLGRJAsm, + SYSZ_INS_CLGRJ, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmE, + SYSZ_INS_CLGRJE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmH, + SYSZ_INS_CLGRJH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmHE, + SYSZ_INS_CLGRJHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmL, + SYSZ_INS_CLGRJL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmLE, + SYSZ_INS_CLGRJLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmLH, + SYSZ_INS_CLGRJLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmNE, + SYSZ_INS_CLGRJNE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmNH, + SYSZ_INS_CLGRJNH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmNHE, + SYSZ_INS_CLGRJNHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmNL, + SYSZ_INS_CLGRJNL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmNLE, + SYSZ_INS_CLGRJNLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRJAsmNLH, + SYSZ_INS_CLGRJNLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLGRL, + SYSZ_INS_CLGRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsm, + SYSZ_INS_CLGRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmE, + SYSZ_INS_CLGRTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmH, + SYSZ_INS_CLGRTH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmHE, + SYSZ_INS_CLGRTHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmL, + SYSZ_INS_CLGRTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmLE, + SYSZ_INS_CLGRTLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmLH, + SYSZ_INS_CLGRTLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmNE, + SYSZ_INS_CLGRTNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmNH, + SYSZ_INS_CLGRTNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmNHE, + SYSZ_INS_CLGRTNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmNL, + SYSZ_INS_CLGRTNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmNLE, + SYSZ_INS_CLGRTNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGRTAsmNLH, + SYSZ_INS_CLGRTNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsm, + SYSZ_INS_CLGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmE, + SYSZ_INS_CLGTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmH, + SYSZ_INS_CLGTH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmHE, + SYSZ_INS_CLGTHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmL, + SYSZ_INS_CLGTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmLE, + SYSZ_INS_CLGTLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmLH, + SYSZ_INS_CLGTLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmNE, + SYSZ_INS_CLGTNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmNH, + SYSZ_INS_CLGTNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmNHE, + SYSZ_INS_CLGTNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmNL, + SYSZ_INS_CLGTNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmNLE, + SYSZ_INS_CLGTNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGTAsmNLH, + SYSZ_INS_CLGTNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGXBR, + SYSZ_INS_CLGXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLGXTR, + SYSZ_INS_CLGXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLHF, + SYSZ_INS_CLHF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLHHR, + SYSZ_INS_CLHHR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLHHSI, + SYSZ_INS_CLHHSI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLHLR, + SYSZ_INS_CLHLR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLHRL, + SYSZ_INS_CLHRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLI, + SYSZ_INS_CLI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLIBAsm, + SYSZ_INS_CLIB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmE, + SYSZ_INS_CLIBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmH, + SYSZ_INS_CLIBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmHE, + SYSZ_INS_CLIBHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmL, + SYSZ_INS_CLIBL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmLE, + SYSZ_INS_CLIBLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmLH, + SYSZ_INS_CLIBLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmNE, + SYSZ_INS_CLIBNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmNH, + SYSZ_INS_CLIBNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmNHE, + SYSZ_INS_CLIBNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmNL, + SYSZ_INS_CLIBNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmNLE, + SYSZ_INS_CLIBNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIBAsmNLH, + SYSZ_INS_CLIBNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLIH, + SYSZ_INS_CLIH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLIJAsm, + SYSZ_INS_CLIJ, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmE, + SYSZ_INS_CLIJE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmH, + SYSZ_INS_CLIJH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmHE, + SYSZ_INS_CLIJHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmL, + SYSZ_INS_CLIJL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmLE, + SYSZ_INS_CLIJLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmLH, + SYSZ_INS_CLIJLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmNE, + SYSZ_INS_CLIJNE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmNH, + SYSZ_INS_CLIJNH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmNHE, + SYSZ_INS_CLIJNHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmNL, + SYSZ_INS_CLIJNL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmNLE, + SYSZ_INS_CLIJNLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIJAsmNLH, + SYSZ_INS_CLIJNLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLIY, + SYSZ_INS_CLIY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLM, + SYSZ_INS_CLM, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLMH, + SYSZ_INS_CLMH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLMY, + SYSZ_INS_CLMY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLR, + SYSZ_INS_CLR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRBAsm, + SYSZ_INS_CLRB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmE, + SYSZ_INS_CLRBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmH, + SYSZ_INS_CLRBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmHE, + SYSZ_INS_CLRBHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmL, + SYSZ_INS_CLRBL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmLE, + SYSZ_INS_CLRBLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmLH, + SYSZ_INS_CLRBLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmNE, + SYSZ_INS_CLRBNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmNH, + SYSZ_INS_CLRBNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmNHE, + SYSZ_INS_CLRBNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmNL, + SYSZ_INS_CLRBNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmNLE, + SYSZ_INS_CLRBNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRBAsmNLH, + SYSZ_INS_CLRBNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CLRJAsm, + SYSZ_INS_CLRJ, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmE, + SYSZ_INS_CLRJE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmH, + SYSZ_INS_CLRJH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmHE, + SYSZ_INS_CLRJHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmL, + SYSZ_INS_CLRJL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmLE, + SYSZ_INS_CLRJLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmLH, + SYSZ_INS_CLRJLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmNE, + SYSZ_INS_CLRJNE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmNH, + SYSZ_INS_CLRJNH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmNHE, + SYSZ_INS_CLRJNHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmNL, + SYSZ_INS_CLRJNL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmNLE, + SYSZ_INS_CLRJNLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRJAsmNLH, + SYSZ_INS_CLRJNLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CLRL, + SYSZ_INS_CLRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsm, + SYSZ_INS_CLRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmE, + SYSZ_INS_CLRTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmH, + SYSZ_INS_CLRTH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmHE, + SYSZ_INS_CLRTHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmL, + SYSZ_INS_CLRTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmLE, + SYSZ_INS_CLRTLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmLH, + SYSZ_INS_CLRTLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmNE, + SYSZ_INS_CLRTNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmNH, + SYSZ_INS_CLRTNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmNHE, + SYSZ_INS_CLRTNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmNL, + SYSZ_INS_CLRTNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmNLE, + SYSZ_INS_CLRTNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLRTAsmNLH, + SYSZ_INS_CLRTNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLST, + SYSZ_INS_CLST, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsm, + SYSZ_INS_CLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmE, + SYSZ_INS_CLTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmH, + SYSZ_INS_CLTH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmHE, + SYSZ_INS_CLTHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmL, + SYSZ_INS_CLTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmLE, + SYSZ_INS_CLTLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmLH, + SYSZ_INS_CLTLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmNE, + SYSZ_INS_CLTNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmNH, + SYSZ_INS_CLTNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmNHE, + SYSZ_INS_CLTNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmNL, + SYSZ_INS_CLTNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmNLE, + SYSZ_INS_CLTNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLTAsmNLH, + SYSZ_INS_CLTNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_CLY, + SYSZ_INS_CLY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CMPSC, + SYSZ_INS_CMPSC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, SYSZ_REG_1, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CP, SYSZ_INS_CP, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CPDT, + SYSZ_INS_CPDT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DFPPACKEDCONVERSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CPSDRdd, + SYSZ_INS_CPSDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CPXT, + SYSZ_INS_CPXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DFPPACKEDCONVERSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CPYA, + SYSZ_INS_CPYA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CR, SYSZ_INS_CR, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CRBAsm, + SYSZ_INS_CRB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmE, + SYSZ_INS_CRBE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmH, + SYSZ_INS_CRBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmHE, + SYSZ_INS_CRBHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmL, + SYSZ_INS_CRBL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmLE, + SYSZ_INS_CRBLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmLH, + SYSZ_INS_CRBLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmNE, + SYSZ_INS_CRBNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmNH, + SYSZ_INS_CRBNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmNHE, + SYSZ_INS_CRBNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmNL, + SYSZ_INS_CRBNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmNLE, + SYSZ_INS_CRBNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRBAsmNLH, + SYSZ_INS_CRBNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {SystemZ_CRDTE, + SYSZ_INS_CRDTE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_ENHANCEDDAT2, 0}, + 0, + 0 +#endif + }, + {SystemZ_CRDTEOpt, + SYSZ_INS_CRDTE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_ENHANCEDDAT2, 0}, + 0, + 0 +#endif + }, + {SystemZ_CRJAsm, + SYSZ_INS_CRJ, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmE, + SYSZ_INS_CRJE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmH, + SYSZ_INS_CRJH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmHE, + SYSZ_INS_CRJHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmL, + SYSZ_INS_CRJL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmLE, + SYSZ_INS_CRJLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmLH, + SYSZ_INS_CRJLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmNE, + SYSZ_INS_CRJNE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmNH, + SYSZ_INS_CRJNH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmNHE, + SYSZ_INS_CRJNHE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmNL, + SYSZ_INS_CRJNL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmNLE, + SYSZ_INS_CRJNLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRJAsmNLH, + SYSZ_INS_CRJNLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_CRL, + SYSZ_INS_CRL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsm, + SYSZ_INS_CRT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmE, + SYSZ_INS_CRTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmH, + SYSZ_INS_CRTH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmHE, + SYSZ_INS_CRTHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmL, + SYSZ_INS_CRTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmLE, + SYSZ_INS_CRTLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmLH, + SYSZ_INS_CRTLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmNE, + SYSZ_INS_CRTNE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmNH, + SYSZ_INS_CRTNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmNHE, + SYSZ_INS_CRTNHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmNL, + SYSZ_INS_CRTNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmNLE, + SYSZ_INS_CRTNLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CRTAsmNLH, + SYSZ_INS_CRTNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CS, SYSZ_INS_CS, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CSCH, + SYSZ_INS_CSCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CSDTR, + SYSZ_INS_CSDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CSG, + SYSZ_INS_CSG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CSP, + SYSZ_INS_CSP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CSPG, + SYSZ_INS_CSPG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CSST, + SYSZ_INS_CSST, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CSXTR, + SYSZ_INS_CSXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CSY, + SYSZ_INS_CSY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU12, + SYSZ_INS_CU12, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU12Opt, + SYSZ_INS_CU12, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU14, + SYSZ_INS_CU14, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU14Opt, + SYSZ_INS_CU14, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU21, + SYSZ_INS_CU21, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU21Opt, + SYSZ_INS_CU21, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU24, + SYSZ_INS_CU24, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU24Opt, + SYSZ_INS_CU24, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU41, + SYSZ_INS_CU41, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CU42, + SYSZ_INS_CU42, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CUDTR, + SYSZ_INS_CUDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CUSE, + SYSZ_INS_CUSE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CUTFU, + SYSZ_INS_CUTFU, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CUTFUOpt, + SYSZ_INS_CUTFU, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CUUTF, + SYSZ_INS_CUUTF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CUUTFOpt, + SYSZ_INS_CUUTF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CUXTR, + SYSZ_INS_CUXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CVB, + SYSZ_INS_CVB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CVBG, + SYSZ_INS_CVBG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CVBY, + SYSZ_INS_CVBY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CVD, + SYSZ_INS_CVD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CVDG, + SYSZ_INS_CVDG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CVDY, + SYSZ_INS_CVDY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXBR, + SYSZ_INS_CXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXFBR, + SYSZ_INS_CXFBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXFBRA, + SYSZ_INS_CXFBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CXFR, + SYSZ_INS_CXFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXFTR, + SYSZ_INS_CXFTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CXGBR, + SYSZ_INS_CXGBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXGBRA, + SYSZ_INS_CXGBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CXGR, + SYSZ_INS_CXGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXGTR, + SYSZ_INS_CXGTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXGTRA, + SYSZ_INS_CXGTRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CXLFBR, + SYSZ_INS_CXLFBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CXLFTR, + SYSZ_INS_CXLFTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CXLGBR, + SYSZ_INS_CXLGBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CXLGTR, + SYSZ_INS_CXLGTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CXPT, + SYSZ_INS_CXPT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DFPPACKEDCONVERSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CXR, + SYSZ_INS_CXR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXSTR, + SYSZ_INS_CXSTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXTR, + SYSZ_INS_CXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXUTR, + SYSZ_INS_CXUTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_CXZT, + SYSZ_INS_CXZT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DFPZONEDCONVERSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CY, SYSZ_INS_CY, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_CZDT, + SYSZ_INS_CZDT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DFPZONEDCONVERSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_CZXT, + SYSZ_INS_CZXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DFPZONEDCONVERSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_D, SYSZ_INS_D, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, + 0, 0 +#endif + }, + {SystemZ_DD, SYSZ_INS_DD, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_DDB, + SYSZ_INS_DDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DDBR, + SYSZ_INS_DDBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DDR, + SYSZ_INS_DDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DDTR, + SYSZ_INS_DDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DDTRA, + SYSZ_INS_DDTRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_DE, SYSZ_INS_DE, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_DEB, + SYSZ_INS_DEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DEBR, + SYSZ_INS_DEBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DER, + SYSZ_INS_DER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DIAG, + SYSZ_INS_DIAG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DIDBR, + SYSZ_INS_DIDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DIEBR, + SYSZ_INS_DIEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DL, SYSZ_INS_DL, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_DLG, + SYSZ_INS_DLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DLGR, + SYSZ_INS_DLGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DLR, + SYSZ_INS_DLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DP, SYSZ_INS_DP, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_DR, SYSZ_INS_DR, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_DSG, + SYSZ_INS_DSG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DSGF, + SYSZ_INS_DSGF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DSGFR, + SYSZ_INS_DSGFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DSGR, + SYSZ_INS_DSGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DXBR, + SYSZ_INS_DXBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DXR, + SYSZ_INS_DXR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DXTR, + SYSZ_INS_DXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_DXTRA, + SYSZ_INS_DXTRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_EAR, + SYSZ_INS_EAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ECAG, + SYSZ_INS_ECAG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ECCTR, + SYSZ_INS_ECCTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ECPGA, + SYSZ_INS_ECPGA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ECTG, + SYSZ_INS_ECTG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ED, SYSZ_INS_ED, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_EDMK, + SYSZ_INS_EDMK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_EEDTR, + SYSZ_INS_EEDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_EEXTR, + SYSZ_INS_EEXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_EFPC, + SYSZ_INS_EFPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_EPAIR, + SYSZ_INS_EPAIR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_EPAR, + SYSZ_INS_EPAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_EPCTR, + SYSZ_INS_EPCTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_EPSW, + SYSZ_INS_EPSW, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_EREG, + SYSZ_INS_EREG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_EREGG, + SYSZ_INS_EREGG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ESAIR, + SYSZ_INS_ESAIR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ESAR, + SYSZ_INS_ESAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ESDTR, + SYSZ_INS_ESDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ESEA, + SYSZ_INS_ESEA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ESTA, + SYSZ_INS_ESTA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ESXTR, + SYSZ_INS_ESXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ETND, + SYSZ_INS_ETND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_TRANSACTIONALEXECUTION, 0}, + 0, + 0 +#endif + }, + {SystemZ_EX, SYSZ_INS_EX, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_EXRL, + SYSZ_INS_EXRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_FIDBR, + SYSZ_INS_FIDBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_FIDBRA, + SYSZ_INS_FIDBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_FIDR, + SYSZ_INS_FIDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_FIDTR, + SYSZ_INS_FIDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_FIEBR, + SYSZ_INS_FIEBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_FIEBRA, + SYSZ_INS_FIEBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_FIER, + SYSZ_INS_FIER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_FIXBR, + SYSZ_INS_FIXBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_FIXBRA, + SYSZ_INS_FIXBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_FIXR, + SYSZ_INS_FIXR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_FIXTR, + SYSZ_INS_FIXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_FLOGR, + SYSZ_INS_FLOGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_HDR, + SYSZ_INS_HDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_HER, + SYSZ_INS_HER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_HSCH, + SYSZ_INS_HSCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IAC, + SYSZ_INS_IAC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IC, SYSZ_INS_IC, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_ICM, + SYSZ_INS_ICM, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ICMH, + SYSZ_INS_ICMH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ICMY, + SYSZ_INS_ICMY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ICY, + SYSZ_INS_ICY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IDTE, + SYSZ_INS_IDTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IDTEOpt, + SYSZ_INS_IDTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IEDTR, + SYSZ_INS_IEDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IEXTR, + SYSZ_INS_IEXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IIHF, + SYSZ_INS_IIHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IIHH, + SYSZ_INS_IIHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IIHL, + SYSZ_INS_IIHL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IILF, + SYSZ_INS_IILF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IILH, + SYSZ_INS_IILH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IILL, + SYSZ_INS_IILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IPK, + SYSZ_INS_IPK, +#ifndef CAPSTONE_DIET + {SYSZ_REG_2, 0}, + {SYSZ_REG_2, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IPM, + SYSZ_INS_IPM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IPTE, + SYSZ_INS_IPTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IPTEOpt, + SYSZ_INS_IPTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IPTEOptOpt, + SYSZ_INS_IPTE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IRBM, + SYSZ_INS_IRBM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, 0}, + 0, + 0 +#endif + }, + {SystemZ_ISKE, + SYSZ_INS_ISKE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_IVSK, + SYSZ_INS_IVSK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_J, SYSZ_INS_J, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, + 1, 0 +#endif + }, + {SystemZ_JAsmE, + SYSZ_INS_JE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmH, + SYSZ_INS_JH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmHE, + SYSZ_INS_JHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmL, + SYSZ_INS_JL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmLE, + SYSZ_INS_JLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmLH, + SYSZ_INS_JLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmM, + SYSZ_INS_JM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNE, + SYSZ_INS_JNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNH, + SYSZ_INS_JNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNHE, + SYSZ_INS_JNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNL, + SYSZ_INS_JNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNLE, + SYSZ_INS_JNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNLH, + SYSZ_INS_JNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNM, + SYSZ_INS_JNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNO, + SYSZ_INS_JNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNP, + SYSZ_INS_JNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmNZ, + SYSZ_INS_JNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmO, + SYSZ_INS_JO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmP, + SYSZ_INS_JP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JAsmZ, + SYSZ_INS_JZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JG, SYSZ_INS_JG, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 1, + 0 +#endif + }, + {SystemZ_JGAsmE, + SYSZ_INS_JGE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmH, + SYSZ_INS_JGH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmHE, + SYSZ_INS_JGHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmL, + SYSZ_INS_JGL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmLE, + SYSZ_INS_JGLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmLH, + SYSZ_INS_JGLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmM, + SYSZ_INS_JGM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNE, + SYSZ_INS_JGNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNH, + SYSZ_INS_JGNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNHE, + SYSZ_INS_JGNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNL, + SYSZ_INS_JGNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNLE, + SYSZ_INS_JGNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNLH, + SYSZ_INS_JGNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNM, + SYSZ_INS_JGNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNO, + SYSZ_INS_JGNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNP, + SYSZ_INS_JGNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmNZ, + SYSZ_INS_JGNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmO, + SYSZ_INS_JGO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmP, + SYSZ_INS_JGP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_JGAsmZ, + SYSZ_INS_JGZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {SystemZ_KDB, + SYSZ_INS_KDB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KDBR, + SYSZ_INS_KDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KDTR, + SYSZ_INS_KDTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KEB, + SYSZ_INS_KEB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KEBR, + SYSZ_INS_KEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KIMD, + SYSZ_INS_KIMD, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KLMD, + SYSZ_INS_KLMD, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KM, + SYSZ_INS_KM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KMA, + SYSZ_INS_KMA, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MESSAGESECURITYASSIST8, 0}, + 0, + 0 +#endif + }, + {SystemZ_KMAC, + SYSZ_INS_KMAC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KMC, + SYSZ_INS_KMC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KMCTR, + SYSZ_INS_KMCTR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MESSAGESECURITYASSIST4, 0}, + 0, + 0 +#endif + }, + {SystemZ_KMF, + SYSZ_INS_KMF, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MESSAGESECURITYASSIST4, 0}, + 0, + 0 +#endif + }, + {SystemZ_KMO, + SYSZ_INS_KMO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MESSAGESECURITYASSIST4, 0}, + 0, + 0 +#endif + }, + {SystemZ_KXBR, + SYSZ_INS_KXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_KXTR, + SYSZ_INS_KXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_L, SYSZ_INS_L, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, + 0, 0 +#endif + }, + {SystemZ_LA, SYSZ_INS_LA, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LAA, + SYSZ_INS_LAA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LAAG, + SYSZ_INS_LAAG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LAAL, + SYSZ_INS_LAAL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LAALG, + SYSZ_INS_LAALG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LAE, + SYSZ_INS_LAE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LAEY, + SYSZ_INS_LAEY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LAM, + SYSZ_INS_LAM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LAMY, + SYSZ_INS_LAMY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LAN, + SYSZ_INS_LAN, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LANG, + SYSZ_INS_LANG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LAO, + SYSZ_INS_LAO, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LAOG, + SYSZ_INS_LAOG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LARL, + SYSZ_INS_LARL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LASP, + SYSZ_INS_LASP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LAT, + SYSZ_INS_LAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_LOADANDTRAP, 0}, + 0, + 0 +#endif + }, + {SystemZ_LAX, + SYSZ_INS_LAX, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LAXG, + SYSZ_INS_LAXG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LAY, + SYSZ_INS_LAY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LB, SYSZ_INS_LB, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LBH, + SYSZ_INS_LBH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_LBR, + SYSZ_INS_LBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCBB, + SYSZ_INS_LCBB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_LCCTL, + SYSZ_INS_LCCTL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCDBR, + SYSZ_INS_LCDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCDFR, + SYSZ_INS_LCDFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCDR, + SYSZ_INS_LCDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCEBR, + SYSZ_INS_LCEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCER, + SYSZ_INS_LCER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCGFR, + SYSZ_INS_LCGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCGR, + SYSZ_INS_LCGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCR, + SYSZ_INS_LCR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCTL, + SYSZ_INS_LCTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCTLG, + SYSZ_INS_LCTLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCXBR, + SYSZ_INS_LCXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LCXR, + SYSZ_INS_LCXR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LD, SYSZ_INS_LD, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LDE, + SYSZ_INS_LDE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDEB, + SYSZ_INS_LDEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDEBR, + SYSZ_INS_LDEBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDER, + SYSZ_INS_LDER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDETR, + SYSZ_INS_LDETR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDGR, + SYSZ_INS_LDGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDR, + SYSZ_INS_LDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDXBR, + SYSZ_INS_LDXBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDXBRA, + SYSZ_INS_LDXBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_LDXR, + SYSZ_INS_LDXR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDXTR, + SYSZ_INS_LDXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LDY, + SYSZ_INS_LDY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LE, SYSZ_INS_LE, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LEDBR, + SYSZ_INS_LEDBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LEDBRA, + SYSZ_INS_LEDBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_LEDR, + SYSZ_INS_LEDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LEDTR, + SYSZ_INS_LEDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LER, + SYSZ_INS_LER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LEXBR, + SYSZ_INS_LEXBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LEXBRA, + SYSZ_INS_LEXBRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_LEXR, + SYSZ_INS_LEXR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LEY, + SYSZ_INS_LEY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LFAS, + SYSZ_INS_LFAS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LFH, + SYSZ_INS_LFH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_LFHAT, + SYSZ_INS_LFHAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_LOADANDTRAP, 0}, + 0, + 0 +#endif + }, + {SystemZ_LFPC, + SYSZ_INS_LFPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LG, SYSZ_INS_LG, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LGAT, + SYSZ_INS_LGAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_LOADANDTRAP, 0}, + 0, + 0 +#endif + }, + {SystemZ_LGB, + SYSZ_INS_LGB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGBR, + SYSZ_INS_LGBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGDR, + SYSZ_INS_LGDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGF, + SYSZ_INS_LGF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGFI, + SYSZ_INS_LGFI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGFR, + SYSZ_INS_LGFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGFRL, + SYSZ_INS_LGFRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGG, + SYSZ_INS_LGG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_GUARDEDSTORAGE, 0}, + 0, + 0 +#endif + }, + {SystemZ_LGH, + SYSZ_INS_LGH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGHI, + SYSZ_INS_LGHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGHR, + SYSZ_INS_LGHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGHRL, + SYSZ_INS_LGHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGR, + SYSZ_INS_LGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGRL, + SYSZ_INS_LGRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LGSC, + SYSZ_INS_LGSC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_GUARDEDSTORAGE, 0}, + 0, + 0 +#endif + }, + {SystemZ_LH, SYSZ_INS_LH, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LHH, + SYSZ_INS_LHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_LHI, + SYSZ_INS_LHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LHR, + SYSZ_INS_LHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LHRL, + SYSZ_INS_LHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LHY, + SYSZ_INS_LHY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLC, + SYSZ_INS_LLC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLCH, + SYSZ_INS_LLCH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_LLCR, + SYSZ_INS_LLCR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGC, + SYSZ_INS_LLGC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGCR, + SYSZ_INS_LLGCR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGF, + SYSZ_INS_LLGF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGFAT, + SYSZ_INS_LLGFAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_LOADANDTRAP, 0}, + 0, + 0 +#endif + }, + {SystemZ_LLGFR, + SYSZ_INS_LLGFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGFRL, + SYSZ_INS_LLGFRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGFSG, + SYSZ_INS_LLGFSG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_GUARDEDSTORAGE, 0}, + 0, + 0 +#endif + }, + {SystemZ_LLGH, + SYSZ_INS_LLGH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGHR, + SYSZ_INS_LLGHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGHRL, + SYSZ_INS_LLGHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGT, + SYSZ_INS_LLGT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLGTAT, + SYSZ_INS_LLGTAT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_LOADANDTRAP, 0}, + 0, + 0 +#endif + }, + {SystemZ_LLGTR, + SYSZ_INS_LLGTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLH, + SYSZ_INS_LLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLHH, + SYSZ_INS_LLHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_LLHR, + SYSZ_INS_LLHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLHRL, + SYSZ_INS_LLHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLIHF, + SYSZ_INS_LLIHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLIHH, + SYSZ_INS_LLIHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLIHL, + SYSZ_INS_LLIHL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLILF, + SYSZ_INS_LLILF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLILH, + SYSZ_INS_LLILH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLILL, + SYSZ_INS_LLILL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LLZRGF, + SYSZ_INS_LLZRGF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0}, + 0, + 0 +#endif + }, + {SystemZ_LM, SYSZ_INS_LM, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LMD, + SYSZ_INS_LMD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LMG, + SYSZ_INS_LMG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LMH, + SYSZ_INS_LMH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LMY, + SYSZ_INS_LMY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNDBR, + SYSZ_INS_LNDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNDFR, + SYSZ_INS_LNDFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNDR, + SYSZ_INS_LNDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNEBR, + SYSZ_INS_LNEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNER, + SYSZ_INS_LNER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNGFR, + SYSZ_INS_LNGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNGR, + SYSZ_INS_LNGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNR, + SYSZ_INS_LNR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNXBR, + SYSZ_INS_LNXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LNXR, + SYSZ_INS_LNXR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsm, + SYSZ_INS_LOC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmE, + SYSZ_INS_LOCE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmH, + SYSZ_INS_LOCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmHE, + SYSZ_INS_LOCHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmL, + SYSZ_INS_LOCL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmLE, + SYSZ_INS_LOCLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmLH, + SYSZ_INS_LOCLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmM, + SYSZ_INS_LOCM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNE, + SYSZ_INS_LOCNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNH, + SYSZ_INS_LOCNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNHE, + SYSZ_INS_LOCNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNL, + SYSZ_INS_LOCNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNLE, + SYSZ_INS_LOCNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNLH, + SYSZ_INS_LOCNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNM, + SYSZ_INS_LOCNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNO, + SYSZ_INS_LOCNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNP, + SYSZ_INS_LOCNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmNZ, + SYSZ_INS_LOCNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmO, + SYSZ_INS_LOCO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmP, + SYSZ_INS_LOCP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCAsmZ, + SYSZ_INS_LOCZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsm, + SYSZ_INS_LOCFH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmE, + SYSZ_INS_LOCFHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmH, + SYSZ_INS_LOCFHH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmHE, + SYSZ_INS_LOCFHHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmL, + SYSZ_INS_LOCFHL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmLE, + SYSZ_INS_LOCFHLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmLH, + SYSZ_INS_LOCFHLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmM, + SYSZ_INS_LOCFHM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNE, + SYSZ_INS_LOCFHNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNH, + SYSZ_INS_LOCFHNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNHE, + SYSZ_INS_LOCFHNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNL, + SYSZ_INS_LOCFHNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNLE, + SYSZ_INS_LOCFHNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNLH, + SYSZ_INS_LOCFHNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNM, + SYSZ_INS_LOCFHNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNO, + SYSZ_INS_LOCFHNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNP, + SYSZ_INS_LOCFHNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmNZ, + SYSZ_INS_LOCFHNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmO, + SYSZ_INS_LOCFHO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmP, + SYSZ_INS_LOCFHP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHAsmZ, + SYSZ_INS_LOCFHZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsm, + SYSZ_INS_LOCFHR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmE, + SYSZ_INS_LOCFHRE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmH, + SYSZ_INS_LOCFHRH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmHE, + SYSZ_INS_LOCFHRHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmL, + SYSZ_INS_LOCFHRL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmLE, + SYSZ_INS_LOCFHRLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmLH, + SYSZ_INS_LOCFHRLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmM, + SYSZ_INS_LOCFHRM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNE, + SYSZ_INS_LOCFHRNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNH, + SYSZ_INS_LOCFHRNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNHE, + SYSZ_INS_LOCFHRNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNL, + SYSZ_INS_LOCFHRNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNLE, + SYSZ_INS_LOCFHRNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNLH, + SYSZ_INS_LOCFHRNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNM, + SYSZ_INS_LOCFHRNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNO, + SYSZ_INS_LOCFHRNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNP, + SYSZ_INS_LOCFHRNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmNZ, + SYSZ_INS_LOCFHRNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmO, + SYSZ_INS_LOCFHRO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmP, + SYSZ_INS_LOCFHRP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCFHRAsmZ, + SYSZ_INS_LOCFHRZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsm, + SYSZ_INS_LOCG, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmE, + SYSZ_INS_LOCGE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmH, + SYSZ_INS_LOCGH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmHE, + SYSZ_INS_LOCGHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmL, + SYSZ_INS_LOCGL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmLE, + SYSZ_INS_LOCGLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmLH, + SYSZ_INS_LOCGLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmM, + SYSZ_INS_LOCGM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNE, + SYSZ_INS_LOCGNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNH, + SYSZ_INS_LOCGNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNHE, + SYSZ_INS_LOCGNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNL, + SYSZ_INS_LOCGNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNLE, + SYSZ_INS_LOCGNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNLH, + SYSZ_INS_LOCGNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNM, + SYSZ_INS_LOCGNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNO, + SYSZ_INS_LOCGNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNP, + SYSZ_INS_LOCGNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmNZ, + SYSZ_INS_LOCGNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmO, + SYSZ_INS_LOCGO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmP, + SYSZ_INS_LOCGP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGAsmZ, + SYSZ_INS_LOCGZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsm, + SYSZ_INS_LOCGHI, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmE, + SYSZ_INS_LOCGHIE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmH, + SYSZ_INS_LOCGHIH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmHE, + SYSZ_INS_LOCGHIHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmL, + SYSZ_INS_LOCGHIL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmLE, + SYSZ_INS_LOCGHILE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmLH, + SYSZ_INS_LOCGHILH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmM, + SYSZ_INS_LOCGHIM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNE, + SYSZ_INS_LOCGHINE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNH, + SYSZ_INS_LOCGHINH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNHE, + SYSZ_INS_LOCGHINHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNL, + SYSZ_INS_LOCGHINL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNLE, + SYSZ_INS_LOCGHINLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNLH, + SYSZ_INS_LOCGHINLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNM, + SYSZ_INS_LOCGHINM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNO, + SYSZ_INS_LOCGHINO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNP, + SYSZ_INS_LOCGHINP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmNZ, + SYSZ_INS_LOCGHINZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmO, + SYSZ_INS_LOCGHIO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmP, + SYSZ_INS_LOCGHIP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGHIAsmZ, + SYSZ_INS_LOCGHIZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsm, + SYSZ_INS_LOCGR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmE, + SYSZ_INS_LOCGRE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmH, + SYSZ_INS_LOCGRH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmHE, + SYSZ_INS_LOCGRHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmL, + SYSZ_INS_LOCGRL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmLE, + SYSZ_INS_LOCGRLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmLH, + SYSZ_INS_LOCGRLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmM, + SYSZ_INS_LOCGRM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNE, + SYSZ_INS_LOCGRNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNH, + SYSZ_INS_LOCGRNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNHE, + SYSZ_INS_LOCGRNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNL, + SYSZ_INS_LOCGRNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNLE, + SYSZ_INS_LOCGRNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNLH, + SYSZ_INS_LOCGRNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNM, + SYSZ_INS_LOCGRNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNO, + SYSZ_INS_LOCGRNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNP, + SYSZ_INS_LOCGRNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmNZ, + SYSZ_INS_LOCGRNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmO, + SYSZ_INS_LOCGRO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmP, + SYSZ_INS_LOCGRP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCGRAsmZ, + SYSZ_INS_LOCGRZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsm, + SYSZ_INS_LOCHHI, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmE, + SYSZ_INS_LOCHHIE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmH, + SYSZ_INS_LOCHHIH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmHE, + SYSZ_INS_LOCHHIHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmL, + SYSZ_INS_LOCHHIL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmLE, + SYSZ_INS_LOCHHILE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmLH, + SYSZ_INS_LOCHHILH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmM, + SYSZ_INS_LOCHHIM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNE, + SYSZ_INS_LOCHHINE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNH, + SYSZ_INS_LOCHHINH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNHE, + SYSZ_INS_LOCHHINHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNL, + SYSZ_INS_LOCHHINL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNLE, + SYSZ_INS_LOCHHINLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNLH, + SYSZ_INS_LOCHHINLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNM, + SYSZ_INS_LOCHHINM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNO, + SYSZ_INS_LOCHHINO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNP, + SYSZ_INS_LOCHHINP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmNZ, + SYSZ_INS_LOCHHINZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmO, + SYSZ_INS_LOCHHIO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmP, + SYSZ_INS_LOCHHIP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHHIAsmZ, + SYSZ_INS_LOCHHIZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsm, + SYSZ_INS_LOCHI, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmE, + SYSZ_INS_LOCHIE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmH, + SYSZ_INS_LOCHIH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmHE, + SYSZ_INS_LOCHIHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmL, + SYSZ_INS_LOCHIL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmLE, + SYSZ_INS_LOCHILE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmLH, + SYSZ_INS_LOCHILH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmM, + SYSZ_INS_LOCHIM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNE, + SYSZ_INS_LOCHINE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNH, + SYSZ_INS_LOCHINH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNHE, + SYSZ_INS_LOCHINHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNL, + SYSZ_INS_LOCHINL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNLE, + SYSZ_INS_LOCHINLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNLH, + SYSZ_INS_LOCHINLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNM, + SYSZ_INS_LOCHINM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNO, + SYSZ_INS_LOCHINO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNP, + SYSZ_INS_LOCHINP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmNZ, + SYSZ_INS_LOCHINZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmO, + SYSZ_INS_LOCHIO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmP, + SYSZ_INS_LOCHIP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCHIAsmZ, + SYSZ_INS_LOCHIZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsm, + SYSZ_INS_LOCR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmE, + SYSZ_INS_LOCRE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmH, + SYSZ_INS_LOCRH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmHE, + SYSZ_INS_LOCRHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmL, + SYSZ_INS_LOCRL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmLE, + SYSZ_INS_LOCRLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmLH, + SYSZ_INS_LOCRLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmM, + SYSZ_INS_LOCRM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNE, + SYSZ_INS_LOCRNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNH, + SYSZ_INS_LOCRNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNHE, + SYSZ_INS_LOCRNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNL, + SYSZ_INS_LOCRNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNLE, + SYSZ_INS_LOCRNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNLH, + SYSZ_INS_LOCRNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNM, + SYSZ_INS_LOCRNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNO, + SYSZ_INS_LOCRNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNP, + SYSZ_INS_LOCRNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmNZ, + SYSZ_INS_LOCRNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmO, + SYSZ_INS_LOCRO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmP, + SYSZ_INS_LOCRP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LOCRAsmZ, + SYSZ_INS_LOCRZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_LPCTL, + SYSZ_INS_LPCTL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPD, + SYSZ_INS_LPD, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LPDBR, + SYSZ_INS_LPDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPDFR, + SYSZ_INS_LPDFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPDG, + SYSZ_INS_LPDG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_INTERLOCKEDACCESS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_LPDR, + SYSZ_INS_LPDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPEBR, + SYSZ_INS_LPEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPER, + SYSZ_INS_LPER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPGFR, + SYSZ_INS_LPGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPGR, + SYSZ_INS_LPGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPP, + SYSZ_INS_LPP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPQ, + SYSZ_INS_LPQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPR, + SYSZ_INS_LPR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPSW, + SYSZ_INS_LPSW, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPSWE, + SYSZ_INS_LPSWE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPTEA, + SYSZ_INS_LPTEA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPXBR, + SYSZ_INS_LPXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LPXR, + SYSZ_INS_LPXR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LR, SYSZ_INS_LR, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LRA, + SYSZ_INS_LRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRAG, + SYSZ_INS_LRAG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRAY, + SYSZ_INS_LRAY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRDR, + SYSZ_INS_LRDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRER, + SYSZ_INS_LRER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRL, + SYSZ_INS_LRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRV, + SYSZ_INS_LRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRVG, + SYSZ_INS_LRVG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRVGR, + SYSZ_INS_LRVGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRVH, + SYSZ_INS_LRVH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LRVR, + SYSZ_INS_LRVR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LSCTL, + SYSZ_INS_LSCTL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LT, SYSZ_INS_LT, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LTDBR, + SYSZ_INS_LTDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTDR, + SYSZ_INS_LTDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTDTR, + SYSZ_INS_LTDTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTEBR, + SYSZ_INS_LTEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTER, + SYSZ_INS_LTER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTG, + SYSZ_INS_LTG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTGF, + SYSZ_INS_LTGF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTGFR, + SYSZ_INS_LTGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTGR, + SYSZ_INS_LTGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTR, + SYSZ_INS_LTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTXBR, + SYSZ_INS_LTXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTXR, + SYSZ_INS_LTXR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LTXTR, + SYSZ_INS_LTXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LURA, + SYSZ_INS_LURA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LURAG, + SYSZ_INS_LURAG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXD, + SYSZ_INS_LXD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXDB, + SYSZ_INS_LXDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXDBR, + SYSZ_INS_LXDBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXDR, + SYSZ_INS_LXDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXDTR, + SYSZ_INS_LXDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXE, + SYSZ_INS_LXE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXEB, + SYSZ_INS_LXEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXEBR, + SYSZ_INS_LXEBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXER, + SYSZ_INS_LXER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LXR, + SYSZ_INS_LXR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LY, SYSZ_INS_LY, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_LZDR, + SYSZ_INS_LZDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LZER, + SYSZ_INS_LZER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_LZRF, + SYSZ_INS_LZRF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0}, + 0, + 0 +#endif + }, + {SystemZ_LZRG, + SYSZ_INS_LZRG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0}, + 0, + 0 +#endif + }, + {SystemZ_LZXR, + SYSZ_INS_LZXR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_M, SYSZ_INS_M, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, + 0, 0 +#endif + }, + {SystemZ_MAD, + SYSZ_INS_MAD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MADB, + SYSZ_INS_MADB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MADBR, + SYSZ_INS_MADBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MADR, + SYSZ_INS_MADR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAE, + SYSZ_INS_MAE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAEB, + SYSZ_INS_MAEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAEBR, + SYSZ_INS_MAEBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAER, + SYSZ_INS_MAER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAY, + SYSZ_INS_MAY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAYH, + SYSZ_INS_MAYH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAYHR, + SYSZ_INS_MAYHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAYL, + SYSZ_INS_MAYL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAYLR, + SYSZ_INS_MAYLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MAYR, + SYSZ_INS_MAYR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MC, SYSZ_INS_MC, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_MD, SYSZ_INS_MD, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_MDB, + SYSZ_INS_MDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MDBR, + SYSZ_INS_MDBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MDE, + SYSZ_INS_MDE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MDEB, + SYSZ_INS_MDEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MDEBR, + SYSZ_INS_MDEBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MDER, + SYSZ_INS_MDER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MDR, + SYSZ_INS_MDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MDTR, + SYSZ_INS_MDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MDTRA, + SYSZ_INS_MDTRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_ME, SYSZ_INS_ME, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_MEE, + SYSZ_INS_MEE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MEEB, + SYSZ_INS_MEEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MEEBR, + SYSZ_INS_MEEBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MEER, + SYSZ_INS_MEER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MER, + SYSZ_INS_MER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MFY, + SYSZ_INS_MFY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MG, SYSZ_INS_MG, +#ifndef CAPSTONE_DIET + {0}, {0}, {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, 0, + 0 +#endif + }, + {SystemZ_MGH, + SYSZ_INS_MGH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 0, + 0 +#endif + }, + {SystemZ_MGHI, + SYSZ_INS_MGHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MGRK, + SYSZ_INS_MGRK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 0, + 0 +#endif + }, + {SystemZ_MH, SYSZ_INS_MH, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_MHI, + SYSZ_INS_MHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MHY, + SYSZ_INS_MHY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ML, SYSZ_INS_ML, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_MLG, + SYSZ_INS_MLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MLGR, + SYSZ_INS_MLGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MLR, + SYSZ_INS_MLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MP, SYSZ_INS_MP, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_MR, SYSZ_INS_MR, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_MS, SYSZ_INS_MS, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_MSC, + SYSZ_INS_MSC, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 0, + 0 +#endif + }, + {SystemZ_MSCH, + SYSZ_INS_MSCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSD, + SYSZ_INS_MSD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSDB, + SYSZ_INS_MSDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSDBR, + SYSZ_INS_MSDBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSDR, + SYSZ_INS_MSDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSE, + SYSZ_INS_MSE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSEB, + SYSZ_INS_MSEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSEBR, + SYSZ_INS_MSEBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSER, + SYSZ_INS_MSER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSFI, + SYSZ_INS_MSFI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSG, + SYSZ_INS_MSG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSGC, + SYSZ_INS_MSGC, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 0, + 0 +#endif + }, + {SystemZ_MSGF, + SYSZ_INS_MSGF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSGFI, + SYSZ_INS_MSGFI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSGFR, + SYSZ_INS_MSGFR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSGR, + SYSZ_INS_MSGR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSGRKC, + SYSZ_INS_MSGRKC, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 0, + 0 +#endif + }, + {SystemZ_MSR, + SYSZ_INS_MSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSRKC, + SYSZ_INS_MSRKC, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 0, + 0 +#endif + }, + {SystemZ_MSTA, + SYSZ_INS_MSTA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MSY, + SYSZ_INS_MSY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVC, + SYSZ_INS_MVC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCDK, + SYSZ_INS_MVCDK, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCIN, + SYSZ_INS_MVCIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCK, + SYSZ_INS_MVCK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCL, + SYSZ_INS_MVCL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCLE, + SYSZ_INS_MVCLE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCLU, + SYSZ_INS_MVCLU, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCOS, + SYSZ_INS_MVCOS, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCP, + SYSZ_INS_MVCP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCS, + SYSZ_INS_MVCS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVCSK, + SYSZ_INS_MVCSK, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVGHI, + SYSZ_INS_MVGHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVHHI, + SYSZ_INS_MVHHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVHI, + SYSZ_INS_MVHI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVI, + SYSZ_INS_MVI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVIY, + SYSZ_INS_MVIY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVN, + SYSZ_INS_MVN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVO, + SYSZ_INS_MVO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVPG, + SYSZ_INS_MVPG, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVST, + SYSZ_INS_MVST, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MVZ, + SYSZ_INS_MVZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MXBR, + SYSZ_INS_MXBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MXD, + SYSZ_INS_MXD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MXDB, + SYSZ_INS_MXDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MXDBR, + SYSZ_INS_MXDBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MXDR, + SYSZ_INS_MXDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MXR, + SYSZ_INS_MXR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MXTR, + SYSZ_INS_MXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MXTRA, + SYSZ_INS_MXTRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_MY, SYSZ_INS_MY, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_MYH, + SYSZ_INS_MYH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MYHR, + SYSZ_INS_MYHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MYL, + SYSZ_INS_MYL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MYLR, + SYSZ_INS_MYLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_MYR, + SYSZ_INS_MYR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_N, SYSZ_INS_N, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_NC, SYSZ_INS_NC, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_NG, SYSZ_INS_NG, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_NGR, + SYSZ_INS_NGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_NGRK, + SYSZ_INS_NGRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_NI, SYSZ_INS_NI, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_NIAI, + SYSZ_INS_NIAI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_EXECUTIONHINT, 0}, + 0, + 0 +#endif + }, + {SystemZ_NIHF, + SYSZ_INS_NIHF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_NIHH, + SYSZ_INS_NIHH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_NIHL, + SYSZ_INS_NIHL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_NILF, + SYSZ_INS_NILF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_NILH, + SYSZ_INS_NILH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_NILL, + SYSZ_INS_NILL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_NIY, + SYSZ_INS_NIY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_NR, SYSZ_INS_NR, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_NRK, + SYSZ_INS_NRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_NTSTG, + SYSZ_INS_NTSTG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_TRANSACTIONALEXECUTION, 0}, + 0, + 0 +#endif + }, + {SystemZ_NY, SYSZ_INS_NY, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_O, SYSZ_INS_O, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_OC, SYSZ_INS_OC, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_OG, SYSZ_INS_OG, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_OGR, + SYSZ_INS_OGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_OGRK, + SYSZ_INS_OGRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_OI, SYSZ_INS_OI, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_OIHF, + SYSZ_INS_OIHF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_OIHH, + SYSZ_INS_OIHH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_OIHL, + SYSZ_INS_OIHL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_OILF, + SYSZ_INS_OILF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_OILH, + SYSZ_INS_OILH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_OILL, + SYSZ_INS_OILL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_OIY, + SYSZ_INS_OIY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_OR, SYSZ_INS_OR, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_ORK, + SYSZ_INS_ORK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_OY, SYSZ_INS_OY, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_PACK, + SYSZ_INS_PACK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PALB, + SYSZ_INS_PALB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PC, SYSZ_INS_PC, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_PCC, + SYSZ_INS_PCC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MESSAGESECURITYASSIST4, 0}, + 0, + 0 +#endif + }, + {SystemZ_PCKMO, + SYSZ_INS_PCKMO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {0}, + {SYSZ_GRP_MESSAGESECURITYASSIST3, 0}, + 0, + 0 +#endif + }, + {SystemZ_PFD, + SYSZ_INS_PFD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PFDRL, + SYSZ_INS_PFDRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PFMF, + SYSZ_INS_PFMF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PFPO, + SYSZ_INS_PFPO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_F4Q, 0}, + {SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_F0Q, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PGIN, + SYSZ_INS_PGIN, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PGOUT, + SYSZ_INS_PGOUT, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PKA, + SYSZ_INS_PKA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PKU, + SYSZ_INS_PKU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PLO, + SYSZ_INS_PLO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_POPCNT, + SYSZ_INS_POPCNT, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_POPULATIONCOUNT, 0}, + 0, + 0 +#endif + }, + {SystemZ_PPA, + SYSZ_INS_PPA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_PROCESSORASSIST, 0}, + 0, + 0 +#endif + }, + {SystemZ_PPNO, + SYSZ_INS_PPNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MESSAGESECURITYASSIST5, 0}, + 0, + 0 +#endif + }, + {SystemZ_PR, SYSZ_INS_PR, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_PRNO, + SYSZ_INS_PRNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MESSAGESECURITYASSIST7, 0}, + 0, + 0 +#endif + }, + {SystemZ_PT, SYSZ_INS_PT, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_PTF, + SYSZ_INS_PTF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PTFF, + SYSZ_INS_PTFF, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PTI, + SYSZ_INS_PTI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_PTLB, + SYSZ_INS_PTLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_QADTR, + SYSZ_INS_QADTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_QAXTR, + SYSZ_INS_QAXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_QCTRI, + SYSZ_INS_QCTRI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_QSI, + SYSZ_INS_QSI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RCHP, + SYSZ_INS_RCHP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RISBG, + SYSZ_INS_RISBG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RISBGN, + SYSZ_INS_RISBGN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0}, + 0, + 0 +#endif + }, + {SystemZ_RISBHG, + SYSZ_INS_RISBHG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_RISBLG, + SYSZ_INS_RISBLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_RLL, + SYSZ_INS_RLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RLLG, + SYSZ_INS_RLLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RNSBG, + SYSZ_INS_RNSBG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ROSBG, + SYSZ_INS_ROSBG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RP, SYSZ_INS_RP, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_RRBE, + SYSZ_INS_RRBE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RRBM, + SYSZ_INS_RRBM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, 0}, + 0, + 0 +#endif + }, + {SystemZ_RRDTR, + SYSZ_INS_RRDTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RRXTR, + SYSZ_INS_RRXTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RSCH, + SYSZ_INS_RSCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_RXSBG, + SYSZ_INS_RXSBG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_S, SYSZ_INS_S, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SAC, + SYSZ_INS_SAC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SACF, + SYSZ_INS_SACF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SAL, + SYSZ_INS_SAL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SAM24, + SYSZ_INS_SAM24, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SAM31, + SYSZ_INS_SAM31, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SAM64, + SYSZ_INS_SAM64, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SAR, + SYSZ_INS_SAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SCCTR, + SYSZ_INS_SCCTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SCHM, + SYSZ_INS_SCHM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, SYSZ_REG_2, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SCK, + SYSZ_INS_SCK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SCKC, + SYSZ_INS_SCKC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SCKPF, + SYSZ_INS_SCKPF, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SD, SYSZ_INS_SD, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SDB, + SYSZ_INS_SDB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SDBR, + SYSZ_INS_SDBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SDR, + SYSZ_INS_SDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SDTR, + SYSZ_INS_SDTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SDTRA, + SYSZ_INS_SDTRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_SE, SYSZ_INS_SE, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SEB, + SYSZ_INS_SEB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SEBR, + SYSZ_INS_SEBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SER, + SYSZ_INS_SER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SFASR, + SYSZ_INS_SFASR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SFPC, + SYSZ_INS_SFPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SG, SYSZ_INS_SG, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SGF, + SYSZ_INS_SGF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SGFR, + SYSZ_INS_SGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SGH, + SYSZ_INS_SGH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0}, + 0, + 0 +#endif + }, + {SystemZ_SGR, + SYSZ_INS_SGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SGRK, + SYSZ_INS_SGRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_SH, SYSZ_INS_SH, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SHHHR, + SYSZ_INS_SHHHR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_SHHLR, + SYSZ_INS_SHHLR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_SHY, + SYSZ_INS_SHY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SIE, + SYSZ_INS_SIE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SIGA, + SYSZ_INS_SIGA, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SIGP, + SYSZ_INS_SIGP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SL, SYSZ_INS_SL, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SLA, + SYSZ_INS_SLA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLAG, + SYSZ_INS_SLAG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLAK, + SYSZ_INS_SLAK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_SLB, + SYSZ_INS_SLB, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLBG, + SYSZ_INS_SLBG, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLBGR, + SYSZ_INS_SLBGR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLBR, + SYSZ_INS_SLBR, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLDA, + SYSZ_INS_SLDA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLDL, + SYSZ_INS_SLDL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLDT, + SYSZ_INS_SLDT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLFI, + SYSZ_INS_SLFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLG, + SYSZ_INS_SLG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLGF, + SYSZ_INS_SLGF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLGFI, + SYSZ_INS_SLGFI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLGFR, + SYSZ_INS_SLGFR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLGR, + SYSZ_INS_SLGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLGRK, + SYSZ_INS_SLGRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_SLHHHR, + SYSZ_INS_SLHHHR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_SLHHLR, + SYSZ_INS_SLHHLR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_SLL, + SYSZ_INS_SLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLLG, + SYSZ_INS_SLLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLLK, + SYSZ_INS_SLLK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_SLR, + SYSZ_INS_SLR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLRK, + SYSZ_INS_SLRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_SLXT, + SYSZ_INS_SLXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SLY, + SYSZ_INS_SLY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SP, SYSZ_INS_SP, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SPCTR, + SYSZ_INS_SPCTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SPKA, + SYSZ_INS_SPKA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SPM, + SYSZ_INS_SPM, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SPT, + SYSZ_INS_SPT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SPX, + SYSZ_INS_SPX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQD, + SYSZ_INS_SQD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQDB, + SYSZ_INS_SQDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQDBR, + SYSZ_INS_SQDBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQDR, + SYSZ_INS_SQDR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQE, + SYSZ_INS_SQE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQEB, + SYSZ_INS_SQEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQEBR, + SYSZ_INS_SQEBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQER, + SYSZ_INS_SQER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQXBR, + SYSZ_INS_SQXBR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SQXR, + SYSZ_INS_SQXR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SR, SYSZ_INS_SR, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SRA, + SYSZ_INS_SRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRAG, + SYSZ_INS_SRAG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRAK, + SYSZ_INS_SRAK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_SRDA, + SYSZ_INS_SRDA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRDL, + SYSZ_INS_SRDL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRDT, + SYSZ_INS_SRDT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRK, + SYSZ_INS_SRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_SRL, + SYSZ_INS_SRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRLG, + SYSZ_INS_SRLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRLK, + SYSZ_INS_SRLK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_SRNM, + SYSZ_INS_SRNM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRNMB, + SYSZ_INS_SRNMB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_SRNMT, + SYSZ_INS_SRNMT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRP, + SYSZ_INS_SRP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRST, + SYSZ_INS_SRST, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRSTU, + SYSZ_INS_SRSTU, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SRXT, + SYSZ_INS_SRXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SSAIR, + SYSZ_INS_SSAIR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SSAR, + SYSZ_INS_SSAR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SSCH, + SYSZ_INS_SSCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SSKE, + SYSZ_INS_SSKE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SSKEOpt, + SYSZ_INS_SSKE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SSM, + SYSZ_INS_SSM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_ST, SYSZ_INS_ST, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_STAM, + SYSZ_INS_STAM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STAMY, + SYSZ_INS_STAMY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STAP, + SYSZ_INS_STAP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STC, + SYSZ_INS_STC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCH, + SYSZ_INS_STCH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_STCK, + SYSZ_INS_STCK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCKC, + SYSZ_INS_STCKC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCKE, + SYSZ_INS_STCKE, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCKF, + SYSZ_INS_STCKF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCM, + SYSZ_INS_STCM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCMH, + SYSZ_INS_STCMH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCMY, + SYSZ_INS_STCMY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCPS, + SYSZ_INS_STCPS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCRW, + SYSZ_INS_STCRW, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCTG, + SYSZ_INS_STCTG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCTL, + SYSZ_INS_STCTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STCY, + SYSZ_INS_STCY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STD, + SYSZ_INS_STD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STDY, + SYSZ_INS_STDY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STE, + SYSZ_INS_STE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STEY, + SYSZ_INS_STEY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STFH, + SYSZ_INS_STFH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_STFL, + SYSZ_INS_STFL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STFLE, + SYSZ_INS_STFLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {SYSZ_REG_0, SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STFPC, + SYSZ_INS_STFPC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STG, + SYSZ_INS_STG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STGRL, + SYSZ_INS_STGRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STGSC, + SYSZ_INS_STGSC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_GUARDEDSTORAGE, 0}, + 0, + 0 +#endif + }, + {SystemZ_STH, + SYSZ_INS_STH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STHH, + SYSZ_INS_STHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_HIGHWORD, 0}, + 0, + 0 +#endif + }, + {SystemZ_STHRL, + SYSZ_INS_STHRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STHY, + SYSZ_INS_STHY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STIDP, + SYSZ_INS_STIDP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STM, + SYSZ_INS_STM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STMG, + SYSZ_INS_STMG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STMH, + SYSZ_INS_STMH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STMY, + SYSZ_INS_STMY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STNSM, + SYSZ_INS_STNSM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsm, + SYSZ_INS_STOC, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmE, + SYSZ_INS_STOCE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmH, + SYSZ_INS_STOCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmHE, + SYSZ_INS_STOCHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmL, + SYSZ_INS_STOCL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmLE, + SYSZ_INS_STOCLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmLH, + SYSZ_INS_STOCLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmM, + SYSZ_INS_STOCM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNE, + SYSZ_INS_STOCNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNH, + SYSZ_INS_STOCNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNHE, + SYSZ_INS_STOCNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNL, + SYSZ_INS_STOCNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNLE, + SYSZ_INS_STOCNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNLH, + SYSZ_INS_STOCNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNM, + SYSZ_INS_STOCNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNO, + SYSZ_INS_STOCNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNP, + SYSZ_INS_STOCNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmNZ, + SYSZ_INS_STOCNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmO, + SYSZ_INS_STOCO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmP, + SYSZ_INS_STOCP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCAsmZ, + SYSZ_INS_STOCZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsm, + SYSZ_INS_STOCFH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmE, + SYSZ_INS_STOCFHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmH, + SYSZ_INS_STOCFHH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmHE, + SYSZ_INS_STOCFHHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmL, + SYSZ_INS_STOCFHL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmLE, + SYSZ_INS_STOCFHLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmLH, + SYSZ_INS_STOCFHLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmM, + SYSZ_INS_STOCFHM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNE, + SYSZ_INS_STOCFHNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNH, + SYSZ_INS_STOCFHNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNHE, + SYSZ_INS_STOCFHNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNL, + SYSZ_INS_STOCFHNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNLE, + SYSZ_INS_STOCFHNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNLH, + SYSZ_INS_STOCFHNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNM, + SYSZ_INS_STOCFHNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNO, + SYSZ_INS_STOCFHNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNP, + SYSZ_INS_STOCFHNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmNZ, + SYSZ_INS_STOCFHNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmO, + SYSZ_INS_STOCFHO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmP, + SYSZ_INS_STOCFHP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCFHAsmZ, + SYSZ_INS_STOCFHZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND2, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsm, + SYSZ_INS_STOCG, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmE, + SYSZ_INS_STOCGE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmH, + SYSZ_INS_STOCGH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmHE, + SYSZ_INS_STOCGHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmL, + SYSZ_INS_STOCGL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmLE, + SYSZ_INS_STOCGLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmLH, + SYSZ_INS_STOCGLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmM, + SYSZ_INS_STOCGM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNE, + SYSZ_INS_STOCGNE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNH, + SYSZ_INS_STOCGNH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNHE, + SYSZ_INS_STOCGNHE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNL, + SYSZ_INS_STOCGNL, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNLE, + SYSZ_INS_STOCGNLE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNLH, + SYSZ_INS_STOCGNLH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNM, + SYSZ_INS_STOCGNM, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNO, + SYSZ_INS_STOCGNO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNP, + SYSZ_INS_STOCGNP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmNZ, + SYSZ_INS_STOCGNZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmO, + SYSZ_INS_STOCGO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmP, + SYSZ_INS_STOCGP, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOCGAsmZ, + SYSZ_INS_STOCGZ, +#ifndef CAPSTONE_DIET + {SYSZ_REG_CC, 0}, + {0}, + {SYSZ_GRP_LOADSTOREONCOND, 0}, + 0, + 0 +#endif + }, + {SystemZ_STOSM, + SYSZ_INS_STOSM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STPQ, + SYSZ_INS_STPQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STPT, + SYSZ_INS_STPT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STPX, + SYSZ_INS_STPX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STRAG, + SYSZ_INS_STRAG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STRL, + SYSZ_INS_STRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STRV, + SYSZ_INS_STRV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STRVG, + SYSZ_INS_STRVG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STRVH, + SYSZ_INS_STRVH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STSCH, + SYSZ_INS_STSCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STSI, + SYSZ_INS_STSI, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_0, SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STURA, + SYSZ_INS_STURA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STURG, + SYSZ_INS_STURG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_STY, + SYSZ_INS_STY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SU, SYSZ_INS_SU, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SUR, + SYSZ_INS_SUR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SVC, + SYSZ_INS_SVC, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SW, SYSZ_INS_SW, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_SWR, + SYSZ_INS_SWR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SXBR, + SYSZ_INS_SXBR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SXR, + SYSZ_INS_SXR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SXTR, + SYSZ_INS_SXTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_SXTRA, + SYSZ_INS_SXTRA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_FPEXTENSION, 0}, + 0, + 0 +#endif + }, + {SystemZ_SY, SYSZ_INS_SY, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_TABORT, + SYSZ_INS_TABORT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_TRANSACTIONALEXECUTION, 0}, + 0, + 0 +#endif + }, + {SystemZ_TAM, + SYSZ_INS_TAM, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TAR, + SYSZ_INS_TAR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TB, + SYSZ_INS_TB, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {SYSZ_REG_0, SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TBDR, + SYSZ_INS_TBDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TBEDR, + SYSZ_INS_TBEDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TBEGIN, + SYSZ_INS_TBEGIN, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_TRANSACTIONALEXECUTION, 0}, + 0, + 0 +#endif + }, + {SystemZ_TBEGINC, + SYSZ_INS_TBEGINC, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_TRANSACTIONALEXECUTION, 0}, + 0, + 0 +#endif + }, + {SystemZ_TCDB, + SYSZ_INS_TCDB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TCEB, + SYSZ_INS_TCEB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TCXB, + SYSZ_INS_TCXB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TDCDT, + SYSZ_INS_TDCDT, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TDCET, + SYSZ_INS_TDCET, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TDCXT, + SYSZ_INS_TDCXT, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TDGDT, + SYSZ_INS_TDGDT, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TDGET, + SYSZ_INS_TDGET, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TDGXT, + SYSZ_INS_TDGXT, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TEND, + SYSZ_INS_TEND, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_TRANSACTIONALEXECUTION, 0}, + 0, + 0 +#endif + }, + {SystemZ_THDER, + SYSZ_INS_THDER, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_THDR, + SYSZ_INS_THDR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TM, SYSZ_INS_TM, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_TMHH, + SYSZ_INS_TMHH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TMHL, + SYSZ_INS_TMHL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TMLH, + SYSZ_INS_TMLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TMLL, + SYSZ_INS_TMLL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TMY, + SYSZ_INS_TMY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TP, SYSZ_INS_TP, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_TPI, + SYSZ_INS_TPI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TPROT, + SYSZ_INS_TPROT, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TR, SYSZ_INS_TR, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {SystemZ_TRACE, + SYSZ_INS_TRACE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRACG, + SYSZ_INS_TRACG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRAP2, + SYSZ_INS_TRAP2, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRAP4, + SYSZ_INS_TRAP4, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRE, + SYSZ_INS_TRE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TROO, + SYSZ_INS_TROO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TROOOpt, + SYSZ_INS_TROO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TROT, + SYSZ_INS_TROT, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TROTOpt, + SYSZ_INS_TROT, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRT, + SYSZ_INS_TRT, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRTE, + SYSZ_INS_TRTE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRTEOpt, + SYSZ_INS_TRTE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRTO, + SYSZ_INS_TRTO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRTOOpt, + SYSZ_INS_TRTO, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRTR, + SYSZ_INS_TRTR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRTRE, + SYSZ_INS_TRTRE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRTREOpt, + SYSZ_INS_TRTRE, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRTT, + SYSZ_INS_TRTT, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TRTTOpt, + SYSZ_INS_TRTT, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_TS, SYSZ_INS_TS, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_TSCH, + SYSZ_INS_TSCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_UNPK, + SYSZ_INS_UNPK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_UNPKA, + SYSZ_INS_UNPKA, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_UNPKU, + SYSZ_INS_UNPKU, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_UPT, + SYSZ_INS_UPT, +#ifndef CAPSTONE_DIET + {SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_4, SYSZ_REG_5, + 0}, + {SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_5, + 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_VA, SYSZ_INS_VA, +#ifndef CAPSTONE_DIET + {0}, {0}, {SYSZ_GRP_VECTOR, 0}, 0, + 0 +#endif + }, + {SystemZ_VAB, + SYSZ_INS_VAB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAC, + SYSZ_INS_VAC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VACC, + SYSZ_INS_VACC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VACCB, + SYSZ_INS_VACCB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VACCC, + SYSZ_INS_VACCC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VACCCQ, + SYSZ_INS_VACCCQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VACCF, + SYSZ_INS_VACCF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VACCG, + SYSZ_INS_VACCG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VACCH, + SYSZ_INS_VACCH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VACCQ, + SYSZ_INS_VACCQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VACQ, + SYSZ_INS_VACQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAF, + SYSZ_INS_VAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAG, + SYSZ_INS_VAG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAH, + SYSZ_INS_VAH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAP, + SYSZ_INS_VAP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAQ, + SYSZ_INS_VAQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVG, + SYSZ_INS_VAVG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVGB, + SYSZ_INS_VAVGB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVGF, + SYSZ_INS_VAVGF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVGG, + SYSZ_INS_VAVGG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVGH, + SYSZ_INS_VAVGH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVGL, + SYSZ_INS_VAVGL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVGLB, + SYSZ_INS_VAVGLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVGLF, + SYSZ_INS_VAVGLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVGLG, + SYSZ_INS_VAVGLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VAVGLH, + SYSZ_INS_VAVGLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VBPERM, + SYSZ_INS_VBPERM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCDG, + SYSZ_INS_VCDG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCDGB, + SYSZ_INS_VCDGB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCDLG, + SYSZ_INS_VCDLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCDLGB, + SYSZ_INS_VCDLGB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCEQ, + SYSZ_INS_VCEQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCEQB, + SYSZ_INS_VCEQB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCEQBS, + SYSZ_INS_VCEQBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCEQF, + SYSZ_INS_VCEQF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCEQFS, + SYSZ_INS_VCEQFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCEQG, + SYSZ_INS_VCEQG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCEQGS, + SYSZ_INS_VCEQGS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCEQH, + SYSZ_INS_VCEQH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCEQHS, + SYSZ_INS_VCEQHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCGD, + SYSZ_INS_VCGD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCGDB, + SYSZ_INS_VCGDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCH, + SYSZ_INS_VCH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHB, + SYSZ_INS_VCHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHBS, + SYSZ_INS_VCHBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHF, + SYSZ_INS_VCHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHFS, + SYSZ_INS_VCHFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHG, + SYSZ_INS_VCHG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHGS, + SYSZ_INS_VCHGS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHH, + SYSZ_INS_VCHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHHS, + SYSZ_INS_VCHHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHL, + SYSZ_INS_VCHL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHLB, + SYSZ_INS_VCHLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHLBS, + SYSZ_INS_VCHLBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHLF, + SYSZ_INS_VCHLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHLFS, + SYSZ_INS_VCHLFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHLG, + SYSZ_INS_VCHLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHLGS, + SYSZ_INS_VCHLGS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHLH, + SYSZ_INS_VCHLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCHLHS, + SYSZ_INS_VCHLHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCKSM, + SYSZ_INS_VCKSM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCLGD, + SYSZ_INS_VCLGD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCLGDB, + SYSZ_INS_VCLGDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCLZ, + SYSZ_INS_VCLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCLZB, + SYSZ_INS_VCLZB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCLZF, + SYSZ_INS_VCLZF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCLZG, + SYSZ_INS_VCLZG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCLZH, + SYSZ_INS_VCLZH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCP, + SYSZ_INS_VCP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCTZ, + SYSZ_INS_VCTZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCTZB, + SYSZ_INS_VCTZB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCTZF, + SYSZ_INS_VCTZF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCTZG, + SYSZ_INS_VCTZG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCTZH, + SYSZ_INS_VCTZH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCVB, + SYSZ_INS_VCVB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCVBG, + SYSZ_INS_VCVBG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCVD, + SYSZ_INS_VCVD, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VCVDG, + SYSZ_INS_VCVDG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VDP, + SYSZ_INS_VDP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VEC, + SYSZ_INS_VEC, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VECB, + SYSZ_INS_VECB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VECF, + SYSZ_INS_VECF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VECG, + SYSZ_INS_VECG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VECH, + SYSZ_INS_VECH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VECL, + SYSZ_INS_VECL, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VECLB, + SYSZ_INS_VECLB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VECLF, + SYSZ_INS_VECLF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VECLG, + SYSZ_INS_VECLG, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VECLH, + SYSZ_INS_VECLH, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERIM, + SYSZ_INS_VERIM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERIMB, + SYSZ_INS_VERIMB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERIMF, + SYSZ_INS_VERIMF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERIMG, + SYSZ_INS_VERIMG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERIMH, + SYSZ_INS_VERIMH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLL, + SYSZ_INS_VERLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLLB, + SYSZ_INS_VERLLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLLF, + SYSZ_INS_VERLLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLLG, + SYSZ_INS_VERLLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLLH, + SYSZ_INS_VERLLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLLV, + SYSZ_INS_VERLLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLLVB, + SYSZ_INS_VERLLVB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLLVF, + SYSZ_INS_VERLLVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLLVG, + SYSZ_INS_VERLLVG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VERLLVH, + SYSZ_INS_VERLLVH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESL, + SYSZ_INS_VESL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESLB, + SYSZ_INS_VESLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESLF, + SYSZ_INS_VESLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESLG, + SYSZ_INS_VESLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESLH, + SYSZ_INS_VESLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESLV, + SYSZ_INS_VESLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESLVB, + SYSZ_INS_VESLVB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESLVF, + SYSZ_INS_VESLVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESLVG, + SYSZ_INS_VESLVG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESLVH, + SYSZ_INS_VESLVH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRA, + SYSZ_INS_VESRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRAB, + SYSZ_INS_VESRAB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRAF, + SYSZ_INS_VESRAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRAG, + SYSZ_INS_VESRAG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRAH, + SYSZ_INS_VESRAH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRAV, + SYSZ_INS_VESRAV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRAVB, + SYSZ_INS_VESRAVB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRAVF, + SYSZ_INS_VESRAVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRAVG, + SYSZ_INS_VESRAVG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRAVH, + SYSZ_INS_VESRAVH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRL, + SYSZ_INS_VESRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRLB, + SYSZ_INS_VESRLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRLF, + SYSZ_INS_VESRLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRLG, + SYSZ_INS_VESRLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRLH, + SYSZ_INS_VESRLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRLV, + SYSZ_INS_VESRLV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRLVB, + SYSZ_INS_VESRLVB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRLVF, + SYSZ_INS_VESRLVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRLVG, + SYSZ_INS_VESRLVG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VESRLVH, + SYSZ_INS_VESRLVH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFA, + SYSZ_INS_VFA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFADB, + SYSZ_INS_VFADB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAE, + SYSZ_INS_VFAE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEB, + SYSZ_INS_VFAEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEBS, + SYSZ_INS_VFAEBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEF, + SYSZ_INS_VFAEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEFS, + SYSZ_INS_VFAEFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEH, + SYSZ_INS_VFAEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEHS, + SYSZ_INS_VFAEHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEZB, + SYSZ_INS_VFAEZB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEZBS, + SYSZ_INS_VFAEZBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEZF, + SYSZ_INS_VFAEZF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEZFS, + SYSZ_INS_VFAEZFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEZH, + SYSZ_INS_VFAEZH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFAEZHS, + SYSZ_INS_VFAEZHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFASB, + SYSZ_INS_VFASB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCE, + SYSZ_INS_VFCE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCEDB, + SYSZ_INS_VFCEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCEDBS, + SYSZ_INS_VFCEDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCESB, + SYSZ_INS_VFCESB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCESBS, + SYSZ_INS_VFCESBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCH, + SYSZ_INS_VFCH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCHDB, + SYSZ_INS_VFCHDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCHDBS, + SYSZ_INS_VFCHDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCHE, + SYSZ_INS_VFCHE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCHEDB, + SYSZ_INS_VFCHEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCHEDBS, + SYSZ_INS_VFCHEDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCHESB, + SYSZ_INS_VFCHESB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCHESBS, + SYSZ_INS_VFCHESBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCHSB, + SYSZ_INS_VFCHSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFCHSBS, + SYSZ_INS_VFCHSBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFD, + SYSZ_INS_VFD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFDDB, + SYSZ_INS_VFDDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFDSB, + SYSZ_INS_VFDSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEE, + SYSZ_INS_VFEE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEB, + SYSZ_INS_VFEEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEBS, + SYSZ_INS_VFEEBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEF, + SYSZ_INS_VFEEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEFS, + SYSZ_INS_VFEEFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEH, + SYSZ_INS_VFEEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEHS, + SYSZ_INS_VFEEHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEZB, + SYSZ_INS_VFEEZB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEZBS, + SYSZ_INS_VFEEZBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEZF, + SYSZ_INS_VFEEZF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEZFS, + SYSZ_INS_VFEEZFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEZH, + SYSZ_INS_VFEEZH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFEEZHS, + SYSZ_INS_VFEEZHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENE, + SYSZ_INS_VFENE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEB, + SYSZ_INS_VFENEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEBS, + SYSZ_INS_VFENEBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEF, + SYSZ_INS_VFENEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEFS, + SYSZ_INS_VFENEFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEH, + SYSZ_INS_VFENEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEHS, + SYSZ_INS_VFENEHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEZB, + SYSZ_INS_VFENEZB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEZBS, + SYSZ_INS_VFENEZBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEZF, + SYSZ_INS_VFENEZF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEZFS, + SYSZ_INS_VFENEZFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEZH, + SYSZ_INS_VFENEZH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFENEZHS, + SYSZ_INS_VFENEZHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFI, + SYSZ_INS_VFI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFIDB, + SYSZ_INS_VFIDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFISB, + SYSZ_INS_VFISB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKEDB, + SYSZ_INS_VFKEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKEDBS, + SYSZ_INS_VFKEDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKESB, + SYSZ_INS_VFKESB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKESBS, + SYSZ_INS_VFKESBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKHDB, + SYSZ_INS_VFKHDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKHDBS, + SYSZ_INS_VFKHDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKHEDB, + SYSZ_INS_VFKHEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKHEDBS, + SYSZ_INS_VFKHEDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKHESB, + SYSZ_INS_VFKHESB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKHESBS, + SYSZ_INS_VFKHESBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKHSB, + SYSZ_INS_VFKHSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFKHSBS, + SYSZ_INS_VFKHSBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLCDB, + SYSZ_INS_VFLCDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLCSB, + SYSZ_INS_VFLCSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLL, + SYSZ_INS_VFLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLLS, + SYSZ_INS_VFLLS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLNDB, + SYSZ_INS_VFLNDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLNSB, + SYSZ_INS_VFLNSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLPDB, + SYSZ_INS_VFLPDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLPSB, + SYSZ_INS_VFLPSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLR, + SYSZ_INS_VFLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFLRD, + SYSZ_INS_VFLRD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFM, + SYSZ_INS_VFM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMA, + SYSZ_INS_VFMA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMADB, + SYSZ_INS_VFMADB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMASB, + SYSZ_INS_VFMASB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMAX, + SYSZ_INS_VFMAX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMAXDB, + SYSZ_INS_VFMAXDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMAXSB, + SYSZ_INS_VFMAXSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMDB, + SYSZ_INS_VFMDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMIN, + SYSZ_INS_VFMIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMINDB, + SYSZ_INS_VFMINDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMINSB, + SYSZ_INS_VFMINSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMS, + SYSZ_INS_VFMS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMSB, + SYSZ_INS_VFMSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMSDB, + SYSZ_INS_VFMSDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFMSSB, + SYSZ_INS_VFMSSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFNMA, + SYSZ_INS_VFNMA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFNMADB, + SYSZ_INS_VFNMADB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFNMASB, + SYSZ_INS_VFNMASB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFNMS, + SYSZ_INS_VFNMS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFNMSDB, + SYSZ_INS_VFNMSDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFNMSSB, + SYSZ_INS_VFNMSSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFPSO, + SYSZ_INS_VFPSO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFPSODB, + SYSZ_INS_VFPSODB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFPSOSB, + SYSZ_INS_VFPSOSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFS, + SYSZ_INS_VFS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFSDB, + SYSZ_INS_VFSDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFSQ, + SYSZ_INS_VFSQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFSQDB, + SYSZ_INS_VFSQDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFSQSB, + SYSZ_INS_VFSQSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFSSB, + SYSZ_INS_VFSSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFTCI, + SYSZ_INS_VFTCI, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFTCIDB, + SYSZ_INS_VFTCIDB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VFTCISB, + SYSZ_INS_VFTCISB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGBM, + SYSZ_INS_VGBM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGEF, + SYSZ_INS_VGEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGEG, + SYSZ_INS_VGEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFM, + SYSZ_INS_VGFM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFMA, + SYSZ_INS_VGFMA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFMAB, + SYSZ_INS_VGFMAB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFMAF, + SYSZ_INS_VGFMAF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFMAG, + SYSZ_INS_VGFMAG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFMAH, + SYSZ_INS_VGFMAH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFMB, + SYSZ_INS_VGFMB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFMF, + SYSZ_INS_VGFMF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFMG, + SYSZ_INS_VGFMG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGFMH, + SYSZ_INS_VGFMH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGM, + SYSZ_INS_VGM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGMB, + SYSZ_INS_VGMB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGMF, + SYSZ_INS_VGMF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGMG, + SYSZ_INS_VGMG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VGMH, + SYSZ_INS_VGMH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VISTR, + SYSZ_INS_VISTR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VISTRB, + SYSZ_INS_VISTRB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VISTRBS, + SYSZ_INS_VISTRBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VISTRF, + SYSZ_INS_VISTRF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VISTRFS, + SYSZ_INS_VISTRFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VISTRH, + SYSZ_INS_VISTRH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VISTRHS, + SYSZ_INS_VISTRHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VL, SYSZ_INS_VL, +#ifndef CAPSTONE_DIET + {0}, {0}, {SYSZ_GRP_VECTOR, 0}, 0, + 0 +#endif + }, + {SystemZ_VLBB, + SYSZ_INS_VLBB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLC, + SYSZ_INS_VLC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLCB, + SYSZ_INS_VLCB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLCF, + SYSZ_INS_VLCF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLCG, + SYSZ_INS_VLCG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLCH, + SYSZ_INS_VLCH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLDE, + SYSZ_INS_VLDE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLDEB, + SYSZ_INS_VLDEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLEB, + SYSZ_INS_VLEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLED, + SYSZ_INS_VLED, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLEDB, + SYSZ_INS_VLEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLEF, + SYSZ_INS_VLEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLEG, + SYSZ_INS_VLEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLEH, + SYSZ_INS_VLEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLEIB, + SYSZ_INS_VLEIB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLEIF, + SYSZ_INS_VLEIF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLEIG, + SYSZ_INS_VLEIG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLEIH, + SYSZ_INS_VLEIH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLGV, + SYSZ_INS_VLGV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLGVB, + SYSZ_INS_VLGVB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLGVF, + SYSZ_INS_VLGVF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLGVG, + SYSZ_INS_VLGVG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLGVH, + SYSZ_INS_VLGVH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLIP, + SYSZ_INS_VLIP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLL, + SYSZ_INS_VLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLLEZ, + SYSZ_INS_VLLEZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLLEZB, + SYSZ_INS_VLLEZB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLLEZF, + SYSZ_INS_VLLEZF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLLEZG, + SYSZ_INS_VLLEZG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLLEZH, + SYSZ_INS_VLLEZH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLLEZLF, + SYSZ_INS_VLLEZLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLM, + SYSZ_INS_VLM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLP, + SYSZ_INS_VLP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLPB, + SYSZ_INS_VLPB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLPF, + SYSZ_INS_VLPF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLPG, + SYSZ_INS_VLPG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLPH, + SYSZ_INS_VLPH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLR, + SYSZ_INS_VLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLREP, + SYSZ_INS_VLREP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLREPB, + SYSZ_INS_VLREPB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLREPF, + SYSZ_INS_VLREPF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLREPG, + SYSZ_INS_VLREPG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLREPH, + SYSZ_INS_VLREPH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLRL, + SYSZ_INS_VLRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLRLR, + SYSZ_INS_VLRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLVG, + SYSZ_INS_VLVG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLVGB, + SYSZ_INS_VLVGB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLVGF, + SYSZ_INS_VLVGF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLVGG, + SYSZ_INS_VLVGG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLVGH, + SYSZ_INS_VLVGH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VLVGP, + SYSZ_INS_VLVGP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAE, + SYSZ_INS_VMAE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAEB, + SYSZ_INS_VMAEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAEF, + SYSZ_INS_VMAEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAEH, + SYSZ_INS_VMAEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAH, + SYSZ_INS_VMAH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAHB, + SYSZ_INS_VMAHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAHF, + SYSZ_INS_VMAHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAHH, + SYSZ_INS_VMAHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAL, + SYSZ_INS_VMAL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALB, + SYSZ_INS_VMALB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALE, + SYSZ_INS_VMALE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALEB, + SYSZ_INS_VMALEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALEF, + SYSZ_INS_VMALEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALEH, + SYSZ_INS_VMALEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALF, + SYSZ_INS_VMALF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALH, + SYSZ_INS_VMALH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALHB, + SYSZ_INS_VMALHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALHF, + SYSZ_INS_VMALHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALHH, + SYSZ_INS_VMALHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALHW, + SYSZ_INS_VMALHW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALO, + SYSZ_INS_VMALO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALOB, + SYSZ_INS_VMALOB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALOF, + SYSZ_INS_VMALOF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMALOH, + SYSZ_INS_VMALOH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAO, + SYSZ_INS_VMAO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAOB, + SYSZ_INS_VMAOB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAOF, + SYSZ_INS_VMAOF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMAOH, + SYSZ_INS_VMAOH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VME, + SYSZ_INS_VME, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMEB, + SYSZ_INS_VMEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMEF, + SYSZ_INS_VMEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMEH, + SYSZ_INS_VMEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMH, + SYSZ_INS_VMH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMHB, + SYSZ_INS_VMHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMHF, + SYSZ_INS_VMHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMHH, + SYSZ_INS_VMHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VML, + SYSZ_INS_VML, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLB, + SYSZ_INS_VMLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLE, + SYSZ_INS_VMLE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLEB, + SYSZ_INS_VMLEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLEF, + SYSZ_INS_VMLEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLEH, + SYSZ_INS_VMLEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLF, + SYSZ_INS_VMLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLH, + SYSZ_INS_VMLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLHB, + SYSZ_INS_VMLHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLHF, + SYSZ_INS_VMLHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLHH, + SYSZ_INS_VMLHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLHW, + SYSZ_INS_VMLHW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLO, + SYSZ_INS_VMLO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLOB, + SYSZ_INS_VMLOB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLOF, + SYSZ_INS_VMLOF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMLOH, + SYSZ_INS_VMLOH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMN, + SYSZ_INS_VMN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMNB, + SYSZ_INS_VMNB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMNF, + SYSZ_INS_VMNF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMNG, + SYSZ_INS_VMNG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMNH, + SYSZ_INS_VMNH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMNL, + SYSZ_INS_VMNL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMNLB, + SYSZ_INS_VMNLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMNLF, + SYSZ_INS_VMNLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMNLG, + SYSZ_INS_VMNLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMNLH, + SYSZ_INS_VMNLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMO, + SYSZ_INS_VMO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMOB, + SYSZ_INS_VMOB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMOF, + SYSZ_INS_VMOF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMOH, + SYSZ_INS_VMOH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMP, + SYSZ_INS_VMP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRH, + SYSZ_INS_VMRH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRHB, + SYSZ_INS_VMRHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRHF, + SYSZ_INS_VMRHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRHG, + SYSZ_INS_VMRHG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRHH, + SYSZ_INS_VMRHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRL, + SYSZ_INS_VMRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRLB, + SYSZ_INS_VMRLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRLF, + SYSZ_INS_VMRLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRLG, + SYSZ_INS_VMRLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMRLH, + SYSZ_INS_VMRLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMSL, + SYSZ_INS_VMSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMSLG, + SYSZ_INS_VMSLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMSP, + SYSZ_INS_VMSP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMX, + SYSZ_INS_VMX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMXB, + SYSZ_INS_VMXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMXF, + SYSZ_INS_VMXF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMXG, + SYSZ_INS_VMXG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMXH, + SYSZ_INS_VMXH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMXL, + SYSZ_INS_VMXL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMXLB, + SYSZ_INS_VMXLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMXLF, + SYSZ_INS_VMXLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMXLG, + SYSZ_INS_VMXLG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VMXLH, + SYSZ_INS_VMXLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VN, SYSZ_INS_VN, +#ifndef CAPSTONE_DIET + {0}, {0}, {SYSZ_GRP_VECTOR, 0}, 0, + 0 +#endif + }, + {SystemZ_VNC, + SYSZ_INS_VNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VNN, + SYSZ_INS_VNN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VNO, + SYSZ_INS_VNO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VNX, + SYSZ_INS_VNX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VO, SYSZ_INS_VO, +#ifndef CAPSTONE_DIET + {0}, {0}, {SYSZ_GRP_VECTOR, 0}, 0, + 0 +#endif + }, + {SystemZ_VOC, + SYSZ_INS_VOC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VONE, + SYSZ_INS_VONE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPDI, + SYSZ_INS_VPDI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPERM, + SYSZ_INS_VPERM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPK, + SYSZ_INS_VPK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKF, + SYSZ_INS_VPKF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKG, + SYSZ_INS_VPKG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKH, + SYSZ_INS_VPKH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKLS, + SYSZ_INS_VPKLS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKLSF, + SYSZ_INS_VPKLSF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKLSFS, + SYSZ_INS_VPKLSFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKLSG, + SYSZ_INS_VPKLSG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKLSGS, + SYSZ_INS_VPKLSGS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKLSH, + SYSZ_INS_VPKLSH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKLSHS, + SYSZ_INS_VPKLSHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKS, + SYSZ_INS_VPKS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKSF, + SYSZ_INS_VPKSF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKSFS, + SYSZ_INS_VPKSFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKSG, + SYSZ_INS_VPKSG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKSGS, + SYSZ_INS_VPKSGS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKSH, + SYSZ_INS_VPKSH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKSHS, + SYSZ_INS_VPKSHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPKZ, + SYSZ_INS_VPKZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPOPCT, + SYSZ_INS_VPOPCT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPOPCTB, + SYSZ_INS_VPOPCTB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPOPCTF, + SYSZ_INS_VPOPCTF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPOPCTG, + SYSZ_INS_VPOPCTG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPOPCTH, + SYSZ_INS_VPOPCTH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_VPSOP, + SYSZ_INS_VPSOP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREP, + SYSZ_INS_VREP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREPB, + SYSZ_INS_VREPB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREPF, + SYSZ_INS_VREPF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREPG, + SYSZ_INS_VREPG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREPH, + SYSZ_INS_VREPH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREPI, + SYSZ_INS_VREPI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREPIB, + SYSZ_INS_VREPIB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREPIF, + SYSZ_INS_VREPIF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREPIG, + SYSZ_INS_VREPIG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VREPIH, + SYSZ_INS_VREPIH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VRP, + SYSZ_INS_VRP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VS, SYSZ_INS_VS, +#ifndef CAPSTONE_DIET + {0}, {0}, {SYSZ_GRP_VECTOR, 0}, 0, + 0 +#endif + }, + {SystemZ_VSB, + SYSZ_INS_VSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSBCBI, + SYSZ_INS_VSBCBI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSBCBIQ, + SYSZ_INS_VSBCBIQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSBI, + SYSZ_INS_VSBI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSBIQ, + SYSZ_INS_VSBIQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSCBI, + SYSZ_INS_VSCBI, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSCBIB, + SYSZ_INS_VSCBIB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSCBIF, + SYSZ_INS_VSCBIF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSCBIG, + SYSZ_INS_VSCBIG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSCBIH, + SYSZ_INS_VSCBIH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSCBIQ, + SYSZ_INS_VSCBIQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSCEF, + SYSZ_INS_VSCEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSCEG, + SYSZ_INS_VSCEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSDP, + SYSZ_INS_VSDP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSEG, + SYSZ_INS_VSEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSEGB, + SYSZ_INS_VSEGB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSEGF, + SYSZ_INS_VSEGF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSEGH, + SYSZ_INS_VSEGH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSEL, + SYSZ_INS_VSEL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSF, + SYSZ_INS_VSF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSG, + SYSZ_INS_VSG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSH, + SYSZ_INS_VSH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSL, + SYSZ_INS_VSL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSLB, + SYSZ_INS_VSLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSLDB, + SYSZ_INS_VSLDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSP, + SYSZ_INS_VSP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSQ, + SYSZ_INS_VSQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSRA, + SYSZ_INS_VSRA, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSRAB, + SYSZ_INS_VSRAB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSRL, + SYSZ_INS_VSRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSRLB, + SYSZ_INS_VSRLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSRP, + SYSZ_INS_VSRP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VST, + SYSZ_INS_VST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTEB, + SYSZ_INS_VSTEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTEF, + SYSZ_INS_VSTEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTEG, + SYSZ_INS_VSTEG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTEH, + SYSZ_INS_VSTEH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTL, + SYSZ_INS_VSTL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTM, + SYSZ_INS_VSTM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRC, + SYSZ_INS_VSTRC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCB, + SYSZ_INS_VSTRCB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCBS, + SYSZ_INS_VSTRCBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCF, + SYSZ_INS_VSTRCF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCFS, + SYSZ_INS_VSTRCFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCH, + SYSZ_INS_VSTRCH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCHS, + SYSZ_INS_VSTRCHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCZB, + SYSZ_INS_VSTRCZB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCZBS, + SYSZ_INS_VSTRCZBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCZF, + SYSZ_INS_VSTRCZF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCZFS, + SYSZ_INS_VSTRCZFS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCZH, + SYSZ_INS_VSTRCZH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRCZHS, + SYSZ_INS_VSTRCZHS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRL, + SYSZ_INS_VSTRL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSTRLR, + SYSZ_INS_VSTRLR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSUM, + SYSZ_INS_VSUM, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSUMB, + SYSZ_INS_VSUMB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSUMG, + SYSZ_INS_VSUMG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSUMGF, + SYSZ_INS_VSUMGF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSUMGH, + SYSZ_INS_VSUMGH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSUMH, + SYSZ_INS_VSUMH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSUMQ, + SYSZ_INS_VSUMQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSUMQF, + SYSZ_INS_VSUMQF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VSUMQG, + SYSZ_INS_VSUMQG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VTM, + SYSZ_INS_VTM, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VTP, + SYSZ_INS_VTP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPH, + SYSZ_INS_VUPH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPHB, + SYSZ_INS_VUPHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPHF, + SYSZ_INS_VUPHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPHH, + SYSZ_INS_VUPHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPKZ, + SYSZ_INS_VUPKZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORPACKEDDECIMAL, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPL, + SYSZ_INS_VUPL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLB, + SYSZ_INS_VUPLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLF, + SYSZ_INS_VUPLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLH, + SYSZ_INS_VUPLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLHB, + SYSZ_INS_VUPLHB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLHF, + SYSZ_INS_VUPLHF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLHH, + SYSZ_INS_VUPLHH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLHW, + SYSZ_INS_VUPLHW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLL, + SYSZ_INS_VUPLL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLLB, + SYSZ_INS_VUPLLB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLLF, + SYSZ_INS_VUPLLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VUPLLH, + SYSZ_INS_VUPLLH, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_VX, SYSZ_INS_VX, +#ifndef CAPSTONE_DIET + {0}, {0}, {SYSZ_GRP_VECTOR, 0}, 0, + 0 +#endif + }, + {SystemZ_VZERO, + SYSZ_INS_VZERO, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WCDGB, + SYSZ_INS_WCDGB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WCDLGB, + SYSZ_INS_WCDLGB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WCGDB, + SYSZ_INS_WCGDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WCLGDB, + SYSZ_INS_WCLGDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFADB, + SYSZ_INS_WFADB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFASB, + SYSZ_INS_WFASB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFAXB, + SYSZ_INS_WFAXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFC, + SYSZ_INS_WFC, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCDB, + SYSZ_INS_WFCDB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCEDB, + SYSZ_INS_WFCEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCEDBS, + SYSZ_INS_WFCEDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCESB, + SYSZ_INS_WFCESB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCESBS, + SYSZ_INS_WFCESBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCEXB, + SYSZ_INS_WFCEXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCEXBS, + SYSZ_INS_WFCEXBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHDB, + SYSZ_INS_WFCHDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHDBS, + SYSZ_INS_WFCHDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHEDB, + SYSZ_INS_WFCHEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHEDBS, + SYSZ_INS_WFCHEDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHESB, + SYSZ_INS_WFCHESB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHESBS, + SYSZ_INS_WFCHESBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHEXB, + SYSZ_INS_WFCHEXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHEXBS, + SYSZ_INS_WFCHEXBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHSB, + SYSZ_INS_WFCHSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHSBS, + SYSZ_INS_WFCHSBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHXB, + SYSZ_INS_WFCHXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCHXBS, + SYSZ_INS_WFCHXBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCSB, + SYSZ_INS_WFCSB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFCXB, + SYSZ_INS_WFCXB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFDDB, + SYSZ_INS_WFDDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFDSB, + SYSZ_INS_WFDSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFDXB, + SYSZ_INS_WFDXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFIDB, + SYSZ_INS_WFIDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFISB, + SYSZ_INS_WFISB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFIXB, + SYSZ_INS_WFIXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFK, + SYSZ_INS_WFK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKDB, + SYSZ_INS_WFKDB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKEDB, + SYSZ_INS_WFKEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKEDBS, + SYSZ_INS_WFKEDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKESB, + SYSZ_INS_WFKESB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKESBS, + SYSZ_INS_WFKESBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKEXB, + SYSZ_INS_WFKEXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKEXBS, + SYSZ_INS_WFKEXBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHDB, + SYSZ_INS_WFKHDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHDBS, + SYSZ_INS_WFKHDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHEDB, + SYSZ_INS_WFKHEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHEDBS, + SYSZ_INS_WFKHEDBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHESB, + SYSZ_INS_WFKHESB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHESBS, + SYSZ_INS_WFKHESBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHEXB, + SYSZ_INS_WFKHEXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHEXBS, + SYSZ_INS_WFKHEXBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHSB, + SYSZ_INS_WFKHSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHSBS, + SYSZ_INS_WFKHSBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHXB, + SYSZ_INS_WFKHXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKHXBS, + SYSZ_INS_WFKHXBS, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKSB, + SYSZ_INS_WFKSB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFKXB, + SYSZ_INS_WFKXB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLCDB, + SYSZ_INS_WFLCDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLCSB, + SYSZ_INS_WFLCSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLCXB, + SYSZ_INS_WFLCXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLLD, + SYSZ_INS_WFLLD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLLS, + SYSZ_INS_WFLLS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLNDB, + SYSZ_INS_WFLNDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLNSB, + SYSZ_INS_WFLNSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLNXB, + SYSZ_INS_WFLNXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLPDB, + SYSZ_INS_WFLPDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLPSB, + SYSZ_INS_WFLPSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLPXB, + SYSZ_INS_WFLPXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLRD, + SYSZ_INS_WFLRD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFLRX, + SYSZ_INS_WFLRX, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMADB, + SYSZ_INS_WFMADB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMASB, + SYSZ_INS_WFMASB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMAXB, + SYSZ_INS_WFMAXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMAXDB, + SYSZ_INS_WFMAXDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMAXSB, + SYSZ_INS_WFMAXSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMAXXB, + SYSZ_INS_WFMAXXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMDB, + SYSZ_INS_WFMDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMINDB, + SYSZ_INS_WFMINDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMINSB, + SYSZ_INS_WFMINSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMINXB, + SYSZ_INS_WFMINXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMSB, + SYSZ_INS_WFMSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMSDB, + SYSZ_INS_WFMSDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMSSB, + SYSZ_INS_WFMSSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMSXB, + SYSZ_INS_WFMSXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFMXB, + SYSZ_INS_WFMXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFNMADB, + SYSZ_INS_WFNMADB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFNMASB, + SYSZ_INS_WFNMASB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFNMAXB, + SYSZ_INS_WFNMAXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFNMSDB, + SYSZ_INS_WFNMSDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFNMSSB, + SYSZ_INS_WFNMSSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFNMSXB, + SYSZ_INS_WFNMSXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFPSODB, + SYSZ_INS_WFPSODB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFPSOSB, + SYSZ_INS_WFPSOSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFPSOXB, + SYSZ_INS_WFPSOXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFSDB, + SYSZ_INS_WFSDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFSQDB, + SYSZ_INS_WFSQDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFSQSB, + SYSZ_INS_WFSQSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFSQXB, + SYSZ_INS_WFSQXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFSSB, + SYSZ_INS_WFSSB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFSXB, + SYSZ_INS_WFSXB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFTCIDB, + SYSZ_INS_WFTCIDB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFTCISB, + SYSZ_INS_WFTCISB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WFTCIXB, + SYSZ_INS_WFTCIXB, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_VECTORENHANCEMENTS1, 0}, + 0, + 0 +#endif + }, + {SystemZ_WLDEB, + SYSZ_INS_WLDEB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_WLEDB, + SYSZ_INS_WLEDB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {SYSZ_GRP_VECTOR, 0}, + 0, + 0 +#endif + }, + {SystemZ_X, SYSZ_INS_X, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_XC, SYSZ_INS_XC, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_XG, SYSZ_INS_XG, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_XGR, + SYSZ_INS_XGR, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_XGRK, + SYSZ_INS_XGRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_XI, SYSZ_INS_XI, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_XIHF, + SYSZ_INS_XIHF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_XILF, + SYSZ_INS_XILF, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_XIY, + SYSZ_INS_XIY, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, + {SystemZ_XR, SYSZ_INS_XR, +#ifndef CAPSTONE_DIET + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_XRK, + SYSZ_INS_XRK, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {SYSZ_GRP_DISTINCTOPS, 0}, + 0, + 0 +#endif + }, + {SystemZ_XSCH, + SYSZ_INS_XSCH, +#ifndef CAPSTONE_DIET + {SYSZ_REG_1, 0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 #endif -}, -{ - SystemZ_ZAP, SYSZ_INS_ZAP, + }, + {SystemZ_XY, SYSZ_INS_XY, #ifndef CAPSTONE_DIET - { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 -#endif -}, + {0}, {SYSZ_REG_CC, 0}, {0}, 0, + 0 +#endif + }, + {SystemZ_ZAP, + SYSZ_INS_ZAP, +#ifndef CAPSTONE_DIET + {0}, + {SYSZ_REG_CC, 0}, + {0}, + 0, + 0 +#endif + }, diff --git a/arch/SystemZ/SystemZModule.c b/arch/SystemZ/SystemZModule.c index bc510688bd..580f0c7641 100644 --- a/arch/SystemZ/SystemZModule.c +++ b/arch/SystemZ/SystemZModule.c @@ -3,42 +3,40 @@ #ifdef CAPSTONE_HAS_SYSZ -#include "../../utils.h" +#include "SystemZModule.h" #include "../../MCRegisterInfo.h" +#include "../../utils.h" #include "SystemZDisassembler.h" #include "SystemZInstPrinter.h" #include "SystemZMapping.h" -#include "SystemZModule.h" -cs_err SystemZ_global_init(cs_struct *ud) -{ - MCRegisterInfo *mri; - mri = cs_mem_malloc(sizeof(*mri)); +cs_err SystemZ_global_init(cs_struct *ud) { + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); - SystemZ_init(mri); - ud->printer = SystemZ_printInst; - ud->printer_info = mri; - ud->getinsn_info = mri; - ud->disasm = SystemZ_getInstruction; - ud->post_printer = SystemZ_post_printer; + SystemZ_init(mri); + ud->printer = SystemZ_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = SystemZ_getInstruction; + ud->post_printer = SystemZ_post_printer; - ud->reg_name = SystemZ_reg_name; - ud->insn_id = SystemZ_get_insn_id; - ud->insn_name = SystemZ_insn_name; - ud->group_name = SystemZ_group_name; + ud->reg_name = SystemZ_reg_name; + ud->insn_id = SystemZ_get_insn_id; + ud->insn_name = SystemZ_insn_name; + ud->group_name = SystemZ_group_name; - return CS_ERR_OK; + return CS_ERR_OK; } -cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value) -{ - if (type == CS_OPT_SYNTAX) - handle->syntax = (int) value; +cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value) { + if (type == CS_OPT_SYNTAX) + handle->syntax = (int)value; - // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot - // test for CS_MODE_LITTLE_ENDIAN because it is 0 + // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot + // test for CS_MODE_LITTLE_ENDIAN because it is 0 - return CS_ERR_OK; + return CS_ERR_OK; } #endif diff --git a/arch/XCore/CapstoneXCoreModule.h b/arch/XCore/CapstoneXCoreModule.h new file mode 100644 index 0000000000..d702600f2b --- /dev/null +++ b/arch/XCore/CapstoneXCoreModule.h @@ -0,0 +1,670 @@ +// +// Created by Phosphorus15 on 2021/7/16. +// + +#ifndef CAPSTONE_CAPSTONEXCOREMODULE_H +#define CAPSTONE_CAPSTONEXCOREMODULE_H + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder); + +static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder); + +static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, + unsigned Insn, + uint64_t Address, + void *Decoder); + +static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) { + const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); + return rc->RegsBegin[RegNo]; +} + +#define GET_REGINFO_ENUM +#define GET_INSTRINFO_ENUM +#define MIPS_GET_DISASSEMBLER +#define GET_REGINFO_MC_DESC +#include "XCoreGenDisassemblerTables.inc" + +FieldFromInstruction(fieldFromInstruction_2, uint16_t) + DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, + uint16_t) DecodeInstruction(decodeInstruction_2, + fieldFromInstruction_2, + decodeToMCInst_2, uint16_t) + + FieldFromInstruction(fieldFromInstruction_4, uint32_t) + DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) + DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, + decodeToMCInst_4, uint32_t) + + static DecodeStatus + DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, + void *Decoder) { + if (RegNo > 11) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, XCore_GRRegsRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, + void *Decoder) { + if (RegNo > 15) + return MCDisassembler_Fail; + unsigned Reg = getReg(Inst->MRI, XCore_RRegsRegClassID, RegNo); + MCOperand_CreateReg0(Inst, Reg); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder) { + if (Val > 11) + return MCDisassembler_Fail; + static const unsigned Values[] = {32 /*bpw*/, 1, 2, 3, 4, 5, + 6, 7, 8, 16, 24, 32}; + MCOperand_CreateImm0(Inst, Values[Val]); + return MCDisassembler_Success; +} + +static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, + void *Decoder) { + MCOperand_CreateImm0(Inst, -(int64_t)Val); + return MCDisassembler_Success; +} + +static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, + unsigned *Op2) { + unsigned Combined = fieldFromInstruction(Insn, 6, 5); + if (Combined < 27) + return MCDisassembler_Fail; + if (fieldFromInstruction(Insn, 5, 1)) { + if (Combined == 31) + return MCDisassembler_Fail; + Combined += 5; + } + Combined -= 27; + unsigned Op1High = Combined % 3; + unsigned Op2High = Combined / 3; + *Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); + *Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); + return MCDisassembler_Success; +} + +static DecodeStatus Decode3OpInstruction(unsigned Insn, unsigned *Op1, + unsigned *Op2, unsigned *Op3) { + unsigned Combined = fieldFromInstruction(Insn, 6, 5); + if (Combined >= 27) + return MCDisassembler_Fail; + + unsigned Op1High = Combined % 3; + unsigned Op2High = (Combined / 3) % 3; + unsigned Op3High = Combined / 9; + *Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); + *Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); + *Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); + return MCDisassembler_Success; +} + +static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + // Try and decode as a 3R instruction. + unsigned Opcode = fieldFromInstruction(Insn, 11, 5); + switch (Opcode) { + case 0x0: + MCInst_setOpcode(Inst, XCore_STW_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x1: + MCInst_setOpcode(Inst, XCore_LDW_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x2: + MCInst_setOpcode(Inst, XCore_ADD_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x3: + MCInst_setOpcode(Inst, XCore_SUB_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x4: + MCInst_setOpcode(Inst, XCore_SHL_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x5: + MCInst_setOpcode(Inst, XCore_SHR_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x6: + MCInst_setOpcode(Inst, XCore_EQ_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x7: + MCInst_setOpcode(Inst, XCore_AND_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x8: + MCInst_setOpcode(Inst, XCore_OR_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x9: + MCInst_setOpcode(Inst, XCore_LDW_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x10: + MCInst_setOpcode(Inst, XCore_LD16S_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x11: + MCInst_setOpcode(Inst, XCore_LD8U_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x12: + MCInst_setOpcode(Inst, XCore_ADD_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x13: + MCInst_setOpcode(Inst, XCore_SUB_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x14: + MCInst_setOpcode(Inst, XCore_SHL_2rus); + return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x15: + MCInst_setOpcode(Inst, XCore_SHR_2rus); + return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x16: + MCInst_setOpcode(Inst, XCore_EQ_2rus); + return Decode2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x17: + MCInst_setOpcode(Inst, XCore_TSETR_3r); + return Decode3RImmInstruction(Inst, Insn, Address, Decoder); + case 0x18: + MCInst_setOpcode(Inst, XCore_LSS_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + case 0x19: + MCInst_setOpcode(Inst, XCore_LSU_3r); + return Decode3RInstruction(Inst, Insn, Address, Decoder); + } + return MCDisassembler_Fail; +} + +static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + MCOperand_CreateImm0(Inst, Op1); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + MCOperand_CreateImm0(Inst, Op2); + return S; +} + +static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); + if (S != MCDisassembler_Success) + return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + // Try and decode as a L3R / L2RUS instruction. + unsigned Opcode = fieldFromInstruction(Insn, 16, 4) | + fieldFromInstruction(Insn, 27, 5) << 4; + switch (Opcode) { + case 0x0c: + MCInst_setOpcode(Inst, XCore_STW_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x1c: + MCInst_setOpcode(Inst, XCore_XOR_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x2c: + MCInst_setOpcode(Inst, XCore_ASHR_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x3c: + MCInst_setOpcode(Inst, XCore_LDAWF_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x4c: + MCInst_setOpcode(Inst, XCore_LDAWB_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x5c: + MCInst_setOpcode(Inst, XCore_LDA16F_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x6c: + MCInst_setOpcode(Inst, XCore_LDA16B_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x7c: + MCInst_setOpcode(Inst, XCore_MUL_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x8c: + MCInst_setOpcode(Inst, XCore_DIVS_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x9c: + MCInst_setOpcode(Inst, XCore_DIVU_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x10c: + MCInst_setOpcode(Inst, XCore_ST16_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x11c: + MCInst_setOpcode(Inst, XCore_ST8_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x12c: + MCInst_setOpcode(Inst, XCore_ASHR_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12d: + MCInst_setOpcode(Inst, XCore_OUTPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x12e: + MCInst_setOpcode(Inst, XCore_INPW_l2rus); + return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); + case 0x13c: + MCInst_setOpcode(Inst, XCore_LDAWF_l2rus); + return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x14c: + MCInst_setOpcode(Inst, XCore_LDAWB_l2rus); + return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); + case 0x15c: + MCInst_setOpcode(Inst, XCore_CRC_l3r); + return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); + case 0x18c: + MCInst_setOpcode(Inst, XCore_REMS_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + case 0x19c: + MCInst_setOpcode(Inst, XCore_REMU_l3r); + return DecodeL3RInstruction(Inst, Insn, Address, Decoder); + } + return MCDisassembler_Fail; +} + +static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = + Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2); + if (S != MCDisassembler_Success) + return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + return S; +} + +static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = + Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2); + if (S != MCDisassembler_Success) + return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + return S; +} + +static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + MCOperand_CreateImm0(Inst, Op1); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + MCOperand_CreateImm0(Inst, Op3); + } + return S; +} + +static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeBitpOperand(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + MCOperand_CreateImm0(Inst, Op3); + } + return S; +} + +static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeBitpOperand(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3, Op4, Op5, Op6; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S != MCDisassembler_Success) + return S; + S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), &Op4, &Op5, + &Op6); + if (S != MCDisassembler_Success) + return S; + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); + return S; +} + +static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + // Try and decode as a L6R instruction. + MCInst_clear(Inst); + unsigned Opcode = fieldFromInstruction(Insn, 27, 5); + switch (Opcode) { + case 0x00: + MCInst_setOpcode(Inst, XCore_LMUL_l6r); + return DecodeL6RInstruction(Inst, Insn, Address, Decoder); + } + return MCDisassembler_Fail; +} + +static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3, Op4, Op5; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S != MCDisassembler_Success) + return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); + S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), &Op4, &Op5); + if (S != MCDisassembler_Success) + return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); + + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + return S; +} + +static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + unsigned Op4 = fieldFromInstruction(Insn, 16, 4); + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + } + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, + unsigned Insn, + uint64_t Address, + void *Decoder) { + unsigned Op1, Op2, Op3; + unsigned Op4 = fieldFromInstruction(Insn, 16, 4); + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), &Op1, &Op2, &Op3); + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + } + if (S == MCDisassembler_Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + } + return S; +} + +#endif // CAPSTONE_CAPSTONEXCOREMODULE_H diff --git a/arch/XCore/XCoreDisassembler.c b/arch/XCore/XCoreDisassembler.c index c095240a5b..6d9e9c24c2 100644 --- a/arch/XCore/XCoreDisassembler.c +++ b/arch/XCore/XCoreDisassembler.c @@ -1,4 +1,5 @@ -//===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// +//===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ +//-*-===// // // The LLVM Compiler Infrastructure // @@ -12,7 +13,7 @@ #ifdef CAPSTONE_HAS_XCORE -#include // DEBUG +#include // DEBUG #include #include @@ -21,774 +22,108 @@ #include "XCoreDisassembler.h" +#include "../../MCDisassembler.h" +#include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" -#include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" -#include "../../MCDisassembler.h" #include "../../MathExtras.h" -static uint64_t getFeatureBits(int mode) -{ - // support everything - return (uint64_t)-1; -} - -static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn) -{ - if (code_len < 2) - // insufficient data - return false; - - // Encoded as a little-endian 16-bit word in the stream. - *insn = (code[0] << 0) | (code[1] << 8); - return true; -} - -static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn) -{ - if (code_len < 4) - // insufficient data - return false; - - // Encoded as a little-endian 32-bit word in the stream. - *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24); - - return true; -} - -static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) -{ - const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); - return rc->RegsBegin[RegNo]; -} - -static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder); - -static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, const void *Decoder); - -#include "XCoreGenDisassemblerTables.inc" - -#define GET_REGINFO_ENUM -#define GET_REGINFO_MC_DESC -#include "XCoreGenRegisterInfo.inc" - -static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg; - - if (RegNo > 11) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg; - if (RegNo > 15) - return MCDisassembler_Fail; - - Reg = getReg(Decoder, XCore_RRegsRegClassID, RegNo); - MCOperand_CreateReg0(Inst, Reg); - - return MCDisassembler_Success; -} - -static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - static const unsigned Values[] = { - 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 - }; - - if (Val > 11) - return MCDisassembler_Fail; - - MCOperand_CreateImm0(Inst, Values[Val]); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, - uint64_t Address, const void *Decoder) -{ - MCOperand_CreateImm0(Inst, -(int64_t)Val); - return MCDisassembler_Success; -} - -static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) -{ - unsigned Op1High, Op2High; - unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); - - if (Combined < 27) - return MCDisassembler_Fail; - - if (fieldFromInstruction_4(Insn, 5, 1)) { - if (Combined == 31) - return MCDisassembler_Fail; - Combined += 5; - } - - Combined -= 27; - Op1High = Combined % 3; - Op2High = Combined / 3; - *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2); - *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2); - - return MCDisassembler_Success; -} - -static DecodeStatus Decode3OpInstruction(unsigned Insn, - unsigned *Op1, unsigned *Op2, unsigned *Op3) -{ - unsigned Op1High, Op2High, Op3High; - unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); - if (Combined >= 27) - return MCDisassembler_Fail; - - Op1High = Combined % 3; - Op2High = (Combined / 3) % 3; - Op3High = Combined / 9; - *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2); - *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2); - *Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2); - - return MCDisassembler_Success; -} - -#define GET_INSTRINFO_ENUM -#include "XCoreGenInstrInfo.inc" -static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - // Try and decode as a 3R instruction. - unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); - switch (Opcode) { - case 0x0: - MCInst_setOpcode(Inst, XCore_STW_2rus); - return Decode2RUSInstruction(Inst, Insn, Address, Decoder); - case 0x1: - MCInst_setOpcode(Inst, XCore_LDW_2rus); - return Decode2RUSInstruction(Inst, Insn, Address, Decoder); - case 0x2: - MCInst_setOpcode(Inst, XCore_ADD_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x3: - MCInst_setOpcode(Inst, XCore_SUB_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x4: - MCInst_setOpcode(Inst, XCore_SHL_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x5: - MCInst_setOpcode(Inst, XCore_SHR_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x6: - MCInst_setOpcode(Inst, XCore_EQ_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x7: - MCInst_setOpcode(Inst, XCore_AND_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x8: - MCInst_setOpcode(Inst, XCore_OR_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x9: - MCInst_setOpcode(Inst, XCore_LDW_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x10: - MCInst_setOpcode(Inst, XCore_LD16S_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x11: - MCInst_setOpcode(Inst, XCore_LD8U_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x12: - MCInst_setOpcode(Inst, XCore_ADD_2rus); - return Decode2RUSInstruction(Inst, Insn, Address, Decoder); - case 0x13: - MCInst_setOpcode(Inst, XCore_SUB_2rus); - return Decode2RUSInstruction(Inst, Insn, Address, Decoder); - case 0x14: - MCInst_setOpcode(Inst, XCore_SHL_2rus); - return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); - case 0x15: - MCInst_setOpcode(Inst, XCore_SHR_2rus); - return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); - case 0x16: - MCInst_setOpcode(Inst, XCore_EQ_2rus); - return Decode2RUSInstruction(Inst, Insn, Address, Decoder); - case 0x17: - MCInst_setOpcode(Inst, XCore_TSETR_3r); - return Decode3RImmInstruction(Inst, Insn, Address, Decoder); - case 0x18: - MCInst_setOpcode(Inst, XCore_LSS_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - case 0x19: - MCInst_setOpcode(Inst, XCore_LSU_3r); - return Decode3RInstruction(Inst, Insn, Address, Decoder); - } - - return MCDisassembler_Fail; -} - -static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2; - DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); - if (S != MCDisassembler_Success) - return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - - return S; -} - -static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2; - DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); - if (S != MCDisassembler_Success) - return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - - MCOperand_CreateImm0(Inst, Op1); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - - return S; -} - -static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2; - DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1); - if (S != MCDisassembler_Success) - return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - - return S; -} - -static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2; - DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); - if (S != MCDisassembler_Success) - return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - - return S; -} - -static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2; - DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); - if (S != MCDisassembler_Success) - return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - MCOperand_CreateImm0(Inst, Op2); - - return S; -} - -static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2; - DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); - if (S != MCDisassembler_Success) - return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeBitpOperand(Inst, Op2, Address, Decoder); - - return S; -} - -static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2; - DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); - if (S != MCDisassembler_Success) - return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); - - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeBitpOperand(Inst, Op2, Address, Decoder); - - return S; -} - -static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - // Try and decode as a L3R / L2RUS instruction. - unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | - fieldFromInstruction_4(Insn, 27, 5) << 4; - switch (Opcode) { - case 0x0c: - MCInst_setOpcode(Inst, XCore_STW_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x1c: - MCInst_setOpcode(Inst, XCore_XOR_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x2c: - MCInst_setOpcode(Inst, XCore_ASHR_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x3c: - MCInst_setOpcode(Inst, XCore_LDAWF_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x4c: - MCInst_setOpcode(Inst, XCore_LDAWB_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x5c: - MCInst_setOpcode(Inst, XCore_LDA16F_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x6c: - MCInst_setOpcode(Inst, XCore_LDA16B_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x7c: - MCInst_setOpcode(Inst, XCore_MUL_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x8c: - MCInst_setOpcode(Inst, XCore_DIVS_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x9c: - MCInst_setOpcode(Inst, XCore_DIVU_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x10c: - MCInst_setOpcode(Inst, XCore_ST16_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x11c: - MCInst_setOpcode(Inst, XCore_ST8_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x12c: - MCInst_setOpcode(Inst, XCore_ASHR_l2rus); - return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); - case 0x12d: - MCInst_setOpcode(Inst, XCore_OUTPW_l2rus); - return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); - case 0x12e: - MCInst_setOpcode(Inst, XCore_INPW_l2rus); - return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); - case 0x13c: - MCInst_setOpcode(Inst, XCore_LDAWF_l2rus); - return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); - case 0x14c: - MCInst_setOpcode(Inst, XCore_LDAWB_l2rus); - return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); - case 0x15c: - MCInst_setOpcode(Inst, XCore_CRC_l3r); - return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); - case 0x18c: - MCInst_setOpcode(Inst, XCore_REMS_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - case 0x19c: - MCInst_setOpcode(Inst, XCore_REMU_l3r); - return DecodeL3RInstruction(Inst, Insn, Address, Decoder); - } - - return MCDisassembler_Fail; -} - -static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2; - DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2); - if (S != MCDisassembler_Success) - return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); - - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - - return S; -} - -static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2; - DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2); - if (S != MCDisassembler_Success) - return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); - - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - - return S; -} - -static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - } - - return S; -} - -static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - MCOperand_CreateImm0(Inst, Op1); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - } - - return S; -} - -static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - MCOperand_CreateImm0(Inst, Op3); - } - - return S; -} - -static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeBitpOperand(Inst, Op3, Address, Decoder); - } - - return S; -} - -static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - DecodeStatus S = - Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - } - - return S; -} - -static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - DecodeStatus S = - Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - } - - return S; -} - -static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - DecodeStatus S = - Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - MCOperand_CreateImm0(Inst, Op3); - } - - return S; -} - -static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - DecodeStatus S = - Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeBitpOperand(Inst, Op3, Address, Decoder); - } - - return S; -} - -static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3, Op4, Op5, Op6; - DecodeStatus S = - Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); - if (S != MCDisassembler_Success) - return S; - - S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6); - if (S != MCDisassembler_Success) - return S; - - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); - return S; -} - -static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Opcode; - - // Try and decode as a L6R instruction. - MCInst_clear(Inst); - Opcode = fieldFromInstruction_4(Insn, 27, 5); - switch (Opcode) { - default: - break; - case 0x00: - MCInst_setOpcode(Inst, XCore_LMUL_l6r); - return DecodeL6RInstruction(Inst, Insn, Address, Decoder); - } - - return MCDisassembler_Fail; -} - -static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3, Op4, Op5; - DecodeStatus S = - Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); - if (S != MCDisassembler_Success) - return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); - - S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5); - if (S != MCDisassembler_Success) - return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); - - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); - return S; -} - -static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); - DecodeStatus S = - Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - } - - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - } - return S; -} - -static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, - const void *Decoder) -{ - unsigned Op1, Op2, Op3; - unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); - DecodeStatus S = - Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - } - - if (S == MCDisassembler_Success) { - DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); - DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); - } - - return S; -} - -#define GET_SUBTARGETINFO_ENUM -#include "XCoreGenInstrInfo.inc" -bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, - uint16_t *size, uint64_t address, void *info) -{ - uint16_t insn16; - uint32_t insn32; - DecodeStatus Result; - - if (!readInstruction16(code, code_len, &insn16)) { - return false; - } - - if (MI->flat_insn->detail) { - memset(MI->flat_insn->detail, 0, offsetof(cs_detail, xcore)+sizeof(cs_xcore)); - } - - // Calling the auto-generated decoder function. - Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0); - if (Result != MCDisassembler_Fail) { - *size = 2; - return true; - } - - if (!readInstruction32(code, code_len, &insn32)) { - return false; - } - - // Calling the auto-generated decoder function. - Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0); - if (Result != MCDisassembler_Fail) { - *size = 4; - return true; - } - - return false; -} - -void XCore_init(MCRegisterInfo *MRI) -{ - /* - InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC, - XCoreMCRegisterClasses, 2, - XCoreRegUnitRoots, - 16, - XCoreRegDiffLists, - XCoreRegStrings, - XCoreSubRegIdxLists, - 1, - XCoreSubRegIdxRanges, - XCoreRegEncodingTable); - */ - - - MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17, - 0, 0, - XCoreMCRegisterClasses, 2, - 0, 0, - XCoreRegDiffLists, - 0, - XCoreSubRegIdxLists, 1, - 0); +static uint64_t getFeatureBits(int mode) { + // support everything + return (uint64_t)-1; +} + +// Currently, we have no feature checks upon PPC, but there might be later, so +// dummy +static inline unsigned checkFeatureRequired(unsigned Bits, unsigned Feature, + bool Require) { + // extended from original arm module + return Require; +} + +#include "CapstoneXCoreModule.h" + +static bool readInstruction16(const uint8_t *code, size_t code_len, + uint16_t *insn) { + if (code_len < 2) + // insufficient data + return false; + + // Encoded as a little-endian 16-bit word in the stream. + *insn = (code[0] << 0) | (code[1] << 8); + return true; +} + +static bool readInstruction32(const uint8_t *code, size_t code_len, + uint32_t *insn) { + if (code_len < 4) + // insufficient data + return false; + + // Encoded as a little-endian 32-bit word in the stream. + *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | + ((uint32_t)code[3] << 24); + + return true; +} + +bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, uint64_t address, + void *info) { + MI->MRI = info; + uint16_t insn16; + uint32_t insn32; + DecodeStatus Result; + + if (!readInstruction16(code, code_len, &insn16)) { + return false; + } + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, + offsetof(cs_detail, xcore) + sizeof(cs_xcore)); + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0); + if (Result != MCDisassembler_Fail) { + *size = 2; + return true; + } + + if (!readInstruction32(code, code_len, &insn32)) { + return false; + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0); + if (Result != MCDisassembler_Fail) { + *size = 4; + return true; + } + + return false; +} + +void XCore_init(MCRegisterInfo *MRI) { + /* + InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC, + XCoreMCRegisterClasses, 2, + XCoreRegUnitRoots, + 16, + XCoreRegDiffLists, + XCoreRegStrings, + XCoreSubRegIdxLists, + 1, + XCoreSubRegIdxRanges, + XCoreRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo( + MRI, XCoreRegDesc, ARR_SIZE(XCoreRegDesc), 0, 0, XCoreMCRegisterClasses, + ARR_SIZE(XCoreMCRegisterClasses), 0, 0, XCoreRegDiffLists, 0, + XCoreSubRegIdxLists, ARR_SIZE(XCoreSubRegIdxLists), 0); } #endif diff --git a/arch/XCore/XCoreDisassembler.h b/arch/XCore/XCoreDisassembler.h index a7478001de..42b7b51425 100644 --- a/arch/XCore/XCoreDisassembler.h +++ b/arch/XCore/XCoreDisassembler.h @@ -4,14 +4,14 @@ #ifndef CS_XCOREDISASSEMBLER_H #define CS_XCOREDISASSEMBLER_H -#include "capstone/capstone.h" -#include "../../MCRegisterInfo.h" #include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "capstone/capstone.h" void XCore_init(MCRegisterInfo *MRI); bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); + MCInst *instr, uint16_t *size, uint64_t address, + void *info); #endif - diff --git a/arch/XCore/XCoreGenAsmWriter.inc b/arch/XCore/XCoreGenAsmWriter.inc index adddeffd34..402ecf6955 100644 --- a/arch/XCore/XCoreGenAsmWriter.inc +++ b/arch/XCore/XCoreGenAsmWriter.inc @@ -9,458 +9,1565 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ -#include // debug #include - +#include // debug /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) -{ - static const uint32_t OpInfo[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 665U, // DBG_VALUE - 0U, // REG_SEQUENCE - 0U, // COPY - 658U, // BUNDLE - 687U, // LIFETIME_START - 645U, // LIFETIME_END - 0U, // STACKMAP - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 2250U, // ADD_2rus - 2250U, // ADD_3r - 10363U, // ADJCALLSTACKDOWN - 10383U, // ADJCALLSTACKUP - 2361840U, // ANDNOT_2r - 2255U, // AND_3r - 2404U, // ASHR_l2rus - 2404U, // ASHR_l3r - 10769U, // BAU_1r - 2099777U, // BITREV_l2r - 19161U, // BLACP_lu10 - 19161U, // BLACP_u10 - 10672U, // BLAT_lu6 - 10672U, // BLAT_u6 - 10425U, // BLA_1r - 10510U, // BLRB_lu10 - 10510U, // BLRB_u10 - 10510U, // BLRF_lu10 - 10510U, // BLRF_u10 - 2099418U, // BRBF_lru6 - 2099418U, // BRBF_ru6 - 2099638U, // BRBT_lru6 - 2099638U, // BRBT_ru6 - 10774U, // BRBU_lu6 - 10774U, // BRBU_u6 - 2099418U, // BRFF_lru6 - 2099418U, // BRFF_ru6 - 2099638U, // BRFT_lru6 - 2099638U, // BRFT_ru6 - 10774U, // BRFU_lu6 - 10774U, // BRFU_u6 - 10791U, // BRU_1r - 553511U, // BR_JT - 815655U, // BR_JT32 - 2099768U, // BYTEREV_l2r - 2132815U, // CHKCT_2r - 2132815U, // CHKCT_rus - 1163U, // CLRE_0R - 19301U, // CLRPT_1R - 10614U, // CLRSR_branch_lu6 - 10614U, // CLRSR_branch_u6 - 10614U, // CLRSR_lu6 - 10614U, // CLRSR_u6 - 2099807U, // CLZ_l2r - 5247047U, // CRC8_l4r - 17041459U, // CRC_l3r - 1168U, // DCALL_0R - 1200U, // DENTSP_0R - 10488U, // DGETREG_1r - 2474U, // DIVS_l3r - 2610U, // DIVU_l3r - 1207U, // DRESTSP_0R - 1242U, // DRET_0R - 10475U, // ECALLF_1r - 10723U, // ECALLT_1r - 19342U, // EDU_1r - 6334686U, // EEF_2r - 6334929U, // EET_2r - 19351U, // EEU_1r - 2099310U, // EH_RETURN - 6334765U, // ENDIN_2r - 10569U, // ENTSP_lu6 - 10569U, // ENTSP_u6 - 2400U, // EQ_2rus - 2400U, // EQ_3r - 10554U, // EXTDP_lu6 - 10554U, // EXTDP_u6 - 10585U, // EXTSP_lu6 - 10585U, // EXTSP_u6 - 10401U, // FRAME_TO_ARGS_OFFSET - 19256U, // FREER_1r - 1236U, // FREET_0R - 6334676U, // GETD_l2r - 1139U, // GETED_0R - 1224U, // GETET_0R - 1151U, // GETID_0R - 1174U, // GETKEP_0R - 1187U, // GETKSP_0R - 6334772U, // GETN_l2r - 51670U, // GETPS_l2r - 2099588U, // GETR_rus - 10252U, // GETSR_lu6 - 10252U, // GETSR_u6 - 6334968U, // GETST_2r - 6334883U, // GETTS_2r - 6334906U, // INCT_2r - 62438U, // INITCP_2r - 70630U, // INITDP_2r - 78822U, // INITLR_l2r - 87014U, // INITPC_2r - 95206U, // INITSP_2r - 8432212U, // INPW_l2rus - 6596970U, // INSHR_2r - 6334955U, // INT_2r - 6334768U, // IN_2r - 675U, // Int_MemBarrier - 10528U, // KCALL_1r - 10528U, // KCALL_lu6 - 10528U, // KCALL_u6 - 10568U, // KENTSP_lu6 - 10568U, // KENTSP_u6 - 10576U, // KRESTSP_lu6 - 10576U, // KRESTSP_u6 - 1247U, // KRET_0R - 45093065U, // LADD_l5r - 12585354U, // LD16S_3r - 12585483U, // LD8U_3r - 14682170U, // LDA16B_l3r - 12585018U, // LDA16F_l3r - 10241U, // LDAPB_lu10 - 10241U, // LDAPB_u10 - 10241U, // LDAPF_lu10 - 10241U, // LDAPF_lu10_ba - 10241U, // LDAPF_u10 - 14682697U, // LDAWB_l2rus - 14682697U, // LDAWB_l3r - 19134U, // LDAWCP_lu6 - 19134U, // LDAWCP_u6 - 100937U, // LDAWDP_lru6 - 100937U, // LDAWDP_ru6 - 2099282U, // LDAWFI - 12585545U, // LDAWF_l2rus - 12585545U, // LDAWF_l3r - 109129U, // LDAWSP_lru6 - 109129U, // LDAWSP_ru6 - 2099396U, // LDC_lru6 - 2099396U, // LDC_ru6 - 1105U, // LDET_0R - 184551985U, // LDIVU_l5r - 1075U, // LDSED_0R - 1015U, // LDSPC_0R - 1045U, // LDSSR_0R - 117327U, // LDWCP_lru6 - 19148U, // LDWCP_lu10 - 117327U, // LDWCP_ru6 - 19148U, // LDWCP_u10 - 100943U, // LDWDP_lru6 - 100943U, // LDWDP_ru6 - 2099292U, // LDWFI - 109135U, // LDWSP_lru6 - 109135U, // LDWSP_ru6 - 12585551U, // LDW_2rus - 12585551U, // LDW_3r - 268437799U, // LMUL_l6r - 2462U, // LSS_3r - 45093054U, // LSUB_l5r - 2604U, // LSU_3r - 452987281U, // MACCS_l4r - 452987418U, // MACCU_l4r - 19224U, // MJOIN_1r - 2099463U, // MKMSK_2r - 2099463U, // MKMSK_rus - 19169U, // MSYNC_1r - 2344U, // MUL_l3r - 2099443U, // NEG - 2099699U, // NOT - 2418U, // OR_3r - 2132826U, // OUTCT_2r - 2132826U, // OUTCT_rus - 78681013U, // OUTPW_l2rus - 2136899U, // OUTSHR_2r - 2132859U, // OUTT_2r - 2132869U, // OUT_2r - 6334721U, // PEEK_2r - 2456U, // REMS_l3r - 2593U, // REMU_l3r - 10561U, // RETSP_lu6 - 10561U, // RETSP_u6 - 612U, // SELECT_CC - 2132748U, // SETCLK_l2r - 10264U, // SETCP_1r - 2132728U, // SETC_l2r - 2132728U, // SETC_lru6 - 2132728U, // SETC_ru6 - 10273U, // SETDP_1r - 2132738U, // SETD_2r - 125856U, // SETEV_1r - 632U, // SETKEP_0R - 2132771U, // SETN_l2r - 2132716U, // SETPSC_2r - 2132951U, // SETPS_l2r - 2132848U, // SETPT_2r - 2132939U, // SETRDY_l2r - 10282U, // SETSP_1r - 10621U, // SETSR_branch_lu6 - 10621U, // SETSR_branch_u6 - 10621U, // SETSR_lu6 - 10621U, // SETSR_u6 - 2132928U, // SETTW_l2r - 125867U, // SETV_1r - 2361855U, // SEXT_2r - 2361855U, // SEXT_rus - 2331U, // SHL_2rus - 2331U, // SHL_3r - 2405U, // SHR_2rus - 2405U, // SHR_3r - 1133U, // SSYNC_0r - 12585025U, // ST16_l3r - 12585037U, // ST8_l3r - 1119U, // STET_0R - 1090U, // STSED_0R - 1030U, // STSPC_0R - 1060U, // STSSR_0R - 100954U, // STWDP_lru6 - 100954U, // STWDP_ru6 - 2099301U, // STWFI - 109146U, // STWSP_lru6 - 109146U, // STWSP_ru6 - 12585562U, // STW_2rus - 12585562U, // STW_l3r - 2239U, // SUB_2rus - 2239U, // SUB_3r - 19245U, // SYNCR_1r - 6334912U, // TESTCT_2r - 6334738U, // TESTLCL_l2r - 6334920U, // TESTWCT_2r - 2100415U, // TSETMR_2r - 138207U, // TSETR_3r - 19438U, // TSTART_1R - 10467U, // WAITEF_1R - 10715U, // WAITET_1R - 1252U, // WAITEU_0R - 2417U, // XOR_l3r - 2361861U, // ZEXT_2r - 2361861U, // ZEXT_rus - 0U - }; +static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { + static const uint32_t OpInfo[] = {0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 665U, // DBG_VALUE + 0U, // REG_SEQUENCE + 0U, // COPY + 658U, // BUNDLE + 687U, // LIFETIME_START + 645U, // LIFETIME_END + 0U, // STACKMAP + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // FRAME_ALLOC + 2250U, // ADD_2rus + 2250U, // ADD_3r + 10363U, // ADJCALLSTACKDOWN + 10383U, // ADJCALLSTACKUP + 2361840U, // ANDNOT_2r + 2255U, // AND_3r + 2404U, // ASHR_l2rus + 2404U, // ASHR_l3r + 10769U, // BAU_1r + 2099777U, // BITREV_l2r + 19161U, // BLACP_lu10 + 19161U, // BLACP_u10 + 10672U, // BLAT_lu6 + 10672U, // BLAT_u6 + 10425U, // BLA_1r + 10510U, // BLRB_lu10 + 10510U, // BLRB_u10 + 10510U, // BLRF_lu10 + 10510U, // BLRF_u10 + 2099418U, // BRBF_lru6 + 2099418U, // BRBF_ru6 + 2099638U, // BRBT_lru6 + 2099638U, // BRBT_ru6 + 10774U, // BRBU_lu6 + 10774U, // BRBU_u6 + 2099418U, // BRFF_lru6 + 2099418U, // BRFF_ru6 + 2099638U, // BRFT_lru6 + 2099638U, // BRFT_ru6 + 10774U, // BRFU_lu6 + 10774U, // BRFU_u6 + 10791U, // BRU_1r + 553511U, // BR_JT + 815655U, // BR_JT32 + 2099768U, // BYTEREV_l2r + 2132815U, // CHKCT_2r + 2132815U, // CHKCT_rus + 1163U, // CLRE_0R + 19301U, // CLRPT_1R + 10614U, // CLRSR_branch_lu6 + 10614U, // CLRSR_branch_u6 + 10614U, // CLRSR_lu6 + 10614U, // CLRSR_u6 + 2099807U, // CLZ_l2r + 5247047U, // CRC8_l4r + 17041459U, // CRC_l3r + 1168U, // DCALL_0R + 1200U, // DENTSP_0R + 10488U, // DGETREG_1r + 2474U, // DIVS_l3r + 2610U, // DIVU_l3r + 1207U, // DRESTSP_0R + 1242U, // DRET_0R + 10475U, // ECALLF_1r + 10723U, // ECALLT_1r + 19342U, // EDU_1r + 6334686U, // EEF_2r + 6334929U, // EET_2r + 19351U, // EEU_1r + 2099310U, // EH_RETURN + 6334765U, // ENDIN_2r + 10569U, // ENTSP_lu6 + 10569U, // ENTSP_u6 + 2400U, // EQ_2rus + 2400U, // EQ_3r + 10554U, // EXTDP_lu6 + 10554U, // EXTDP_u6 + 10585U, // EXTSP_lu6 + 10585U, // EXTSP_u6 + 10401U, // FRAME_TO_ARGS_OFFSET + 19256U, // FREER_1r + 1236U, // FREET_0R + 6334676U, // GETD_l2r + 1139U, // GETED_0R + 1224U, // GETET_0R + 1151U, // GETID_0R + 1174U, // GETKEP_0R + 1187U, // GETKSP_0R + 6334772U, // GETN_l2r + 51670U, // GETPS_l2r + 2099588U, // GETR_rus + 10252U, // GETSR_lu6 + 10252U, // GETSR_u6 + 6334968U, // GETST_2r + 6334883U, // GETTS_2r + 6334906U, // INCT_2r + 62438U, // INITCP_2r + 70630U, // INITDP_2r + 78822U, // INITLR_l2r + 87014U, // INITPC_2r + 95206U, // INITSP_2r + 8432212U, // INPW_l2rus + 6596970U, // INSHR_2r + 6334955U, // INT_2r + 6334768U, // IN_2r + 675U, // Int_MemBarrier + 10528U, // KCALL_1r + 10528U, // KCALL_lu6 + 10528U, // KCALL_u6 + 10568U, // KENTSP_lu6 + 10568U, // KENTSP_u6 + 10576U, // KRESTSP_lu6 + 10576U, // KRESTSP_u6 + 1247U, // KRET_0R + 45093065U, // LADD_l5r + 12585354U, // LD16S_3r + 12585483U, // LD8U_3r + 14682170U, // LDA16B_l3r + 12585018U, // LDA16F_l3r + 10241U, // LDAPB_lu10 + 10241U, // LDAPB_u10 + 10241U, // LDAPF_lu10 + 10241U, // LDAPF_lu10_ba + 10241U, // LDAPF_u10 + 14682697U, // LDAWB_l2rus + 14682697U, // LDAWB_l3r + 19134U, // LDAWCP_lu6 + 19134U, // LDAWCP_u6 + 100937U, // LDAWDP_lru6 + 100937U, // LDAWDP_ru6 + 2099282U, // LDAWFI + 12585545U, // LDAWF_l2rus + 12585545U, // LDAWF_l3r + 109129U, // LDAWSP_lru6 + 109129U, // LDAWSP_ru6 + 2099396U, // LDC_lru6 + 2099396U, // LDC_ru6 + 1105U, // LDET_0R + 184551985U, // LDIVU_l5r + 1075U, // LDSED_0R + 1015U, // LDSPC_0R + 1045U, // LDSSR_0R + 117327U, // LDWCP_lru6 + 19148U, // LDWCP_lu10 + 117327U, // LDWCP_ru6 + 19148U, // LDWCP_u10 + 100943U, // LDWDP_lru6 + 100943U, // LDWDP_ru6 + 2099292U, // LDWFI + 109135U, // LDWSP_lru6 + 109135U, // LDWSP_ru6 + 12585551U, // LDW_2rus + 12585551U, // LDW_3r + 268437799U, // LMUL_l6r + 2462U, // LSS_3r + 45093054U, // LSUB_l5r + 2604U, // LSU_3r + 452987281U, // MACCS_l4r + 452987418U, // MACCU_l4r + 19224U, // MJOIN_1r + 2099463U, // MKMSK_2r + 2099463U, // MKMSK_rus + 19169U, // MSYNC_1r + 2344U, // MUL_l3r + 2099443U, // NEG + 2099699U, // NOT + 2418U, // OR_3r + 2132826U, // OUTCT_2r + 2132826U, // OUTCT_rus + 78681013U, // OUTPW_l2rus + 2136899U, // OUTSHR_2r + 2132859U, // OUTT_2r + 2132869U, // OUT_2r + 6334721U, // PEEK_2r + 2456U, // REMS_l3r + 2593U, // REMU_l3r + 10561U, // RETSP_lu6 + 10561U, // RETSP_u6 + 612U, // SELECT_CC + 2132748U, // SETCLK_l2r + 10264U, // SETCP_1r + 2132728U, // SETC_l2r + 2132728U, // SETC_lru6 + 2132728U, // SETC_ru6 + 10273U, // SETDP_1r + 2132738U, // SETD_2r + 125856U, // SETEV_1r + 632U, // SETKEP_0R + 2132771U, // SETN_l2r + 2132716U, // SETPSC_2r + 2132951U, // SETPS_l2r + 2132848U, // SETPT_2r + 2132939U, // SETRDY_l2r + 10282U, // SETSP_1r + 10621U, // SETSR_branch_lu6 + 10621U, // SETSR_branch_u6 + 10621U, // SETSR_lu6 + 10621U, // SETSR_u6 + 2132928U, // SETTW_l2r + 125867U, // SETV_1r + 2361855U, // SEXT_2r + 2361855U, // SEXT_rus + 2331U, // SHL_2rus + 2331U, // SHL_3r + 2405U, // SHR_2rus + 2405U, // SHR_3r + 1133U, // SSYNC_0r + 12585025U, // ST16_l3r + 12585037U, // ST8_l3r + 1119U, // STET_0R + 1090U, // STSED_0R + 1030U, // STSPC_0R + 1060U, // STSSR_0R + 100954U, // STWDP_lru6 + 100954U, // STWDP_ru6 + 2099301U, // STWFI + 109146U, // STWSP_lru6 + 109146U, // STWSP_ru6 + 12585562U, // STW_2rus + 12585562U, // STW_l3r + 2239U, // SUB_2rus + 2239U, // SUB_3r + 19245U, // SYNCR_1r + 6334912U, // TESTCT_2r + 6334738U, // TESTLCL_l2r + 6334920U, // TESTWCT_2r + 2100415U, // TSETMR_2r + 138207U, // TSETR_3r + 19438U, // TSTART_1R + 10467U, // WAITEF_1R + 10715U, // WAITET_1R + 1252U, // WAITEU_0R + 2417U, // XOR_l3r + 2361861U, // ZEXT_2r + 2361861U, // ZEXT_rus + 0U}; static const char AsmStrs[] = { - /* 0 */ 'l', 'd', 'a', 'p', 32, 'r', '1', '1', ',', 32, 0, - /* 11 */ 'g', 'e', 't', 's', 'r', 32, 'r', '1', '1', ',', 32, 0, - /* 23 */ 's', 'e', 't', 32, 'c', 'p', ',', 32, 0, - /* 32 */ 's', 'e', 't', 32, 'd', 'p', ',', 32, 0, - /* 41 */ 's', 'e', 't', 32, 's', 'p', ',', 32, 0, - /* 50 */ 'c', 'r', 'c', '3', '2', 32, 0, - /* 57 */ 'l', 'd', 'a', '1', '6', 32, 0, - /* 64 */ 's', 't', '1', '6', 32, 0, - /* 70 */ 'c', 'r', 'c', '8', 32, 0, - /* 76 */ 's', 't', '8', 32, 0, - /* 81 */ '#', 32, 'L', 'D', 'A', 'W', 'F', 'I', 32, 0, - /* 91 */ '#', 32, 'L', 'D', 'W', 'F', 'I', 32, 0, - /* 100 */ '#', 32, 'S', 'T', 'W', 'F', 'I', 32, 0, - /* 109 */ '#', 32, 'E', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 32, 0, - /* 122 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, - /* 142 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, - /* 160 */ '#', 32, 'F', 'R', 'A', 'M', 'E', '_', 'T', 'O', '_', 'A', 'R', 'G', 'S', '_', 'O', 'F', 'F', 'S', 'E', 'T', 32, 0, - /* 184 */ 'b', 'l', 'a', 32, 0, - /* 189 */ 'l', 's', 'u', 'b', 32, 0, - /* 195 */ 'l', 'd', 'c', 32, 0, - /* 200 */ 'l', 'a', 'd', 'd', 32, 0, - /* 206 */ 'a', 'n', 'd', 32, 0, - /* 211 */ 'g', 'e', 't', 'd', 32, 0, - /* 217 */ 'b', 'f', 32, 0, - /* 221 */ 'e', 'e', 'f', 32, 0, - /* 226 */ 'w', 'a', 'i', 't', 'e', 'f', 32, 0, - /* 234 */ 'e', 'c', 'a', 'l', 'l', 'f', 32, 0, - /* 242 */ 'n', 'e', 'g', 32, 0, - /* 247 */ 'd', 'g', 'e', 't', 'r', 'e', 'g', 32, 0, - /* 256 */ 'p', 'e', 'e', 'k', 32, 0, - /* 262 */ 'm', 'k', 'm', 's', 'k', 32, 0, - /* 269 */ 'b', 'l', 32, 0, - /* 273 */ 't', 'e', 's', 't', 'l', 'c', 'l', 32, 0, - /* 282 */ 's', 'h', 'l', 32, 0, - /* 287 */ 'k', 'c', 'a', 'l', 'l', 32, 0, - /* 294 */ 'l', 'm', 'u', 'l', 32, 0, - /* 300 */ 'e', 'n', 'd', 'i', 'n', 32, 0, - /* 307 */ 'g', 'e', 't', 'n', 32, 0, - /* 313 */ 'e', 'x', 't', 'd', 'p', 32, 0, - /* 320 */ 'r', 'e', 't', 's', 'p', 32, 0, - /* 327 */ 'k', 'e', 'n', 't', 's', 'p', 32, 0, - /* 335 */ 'k', 'r', 'e', 's', 't', 's', 'p', 32, 0, - /* 344 */ 'e', 'x', 't', 's', 'p', 32, 0, - /* 351 */ 'e', 'q', 32, 0, - /* 355 */ 'a', 's', 'h', 'r', 32, 0, - /* 361 */ 'i', 'n', 's', 'h', 'r', 32, 0, - /* 368 */ 'x', 'o', 'r', 32, 0, - /* 373 */ 'c', 'l', 'r', 's', 'r', 32, 0, - /* 380 */ 's', 'e', 't', 's', 'r', 32, 0, - /* 387 */ 'g', 'e', 't', 'r', 32, 0, - /* 393 */ 'l', 'd', '1', '6', 's', 32, 0, - /* 400 */ 'm', 'a', 'c', 'c', 's', 32, 0, - /* 407 */ 'r', 'e', 'm', 's', 32, 0, - /* 413 */ 'l', 's', 's', 32, 0, - /* 418 */ 'g', 'e', 't', 't', 's', 32, 0, - /* 425 */ 'd', 'i', 'v', 's', 32, 0, - /* 431 */ 'b', 'l', 'a', 't', 32, 0, - /* 437 */ 'b', 't', 32, 0, - /* 441 */ 'i', 'n', 'c', 't', 32, 0, - /* 447 */ 't', 'e', 's', 't', 'c', 't', 32, 0, - /* 455 */ 't', 'e', 's', 't', 'w', 'c', 't', 32, 0, - /* 464 */ 'e', 'e', 't', 32, 0, - /* 469 */ 'g', 'e', 't', 32, 0, - /* 474 */ 'w', 'a', 'i', 't', 'e', 't', 32, 0, - /* 482 */ 'e', 'c', 'a', 'l', 'l', 't', 32, 0, - /* 490 */ 'i', 'n', 't', 32, 0, - /* 495 */ 'a', 'n', 'd', 'n', 'o', 't', 32, 0, - /* 503 */ 'g', 'e', 't', 's', 't', 32, 0, - /* 510 */ 's', 'e', 'x', 't', 32, 0, - /* 516 */ 'z', 'e', 'x', 't', 32, 0, - /* 522 */ 'l', 'd', '8', 'u', 32, 0, - /* 528 */ 'b', 'a', 'u', 32, 0, - /* 533 */ 'b', 'u', 32, 0, - /* 537 */ 'm', 'a', 'c', 'c', 'u', 32, 0, - /* 544 */ 'r', 'e', 'm', 'u', 32, 0, - /* 550 */ 'b', 'r', 'u', 32, 0, - /* 555 */ 'l', 's', 'u', 32, 0, - /* 560 */ 'l', 'd', 'i', 'v', 'u', 32, 0, - /* 567 */ 'b', 'y', 't', 'e', 'r', 'e', 'v', 32, 0, - /* 576 */ 'b', 'i', 't', 'r', 'e', 'v', 32, 0, - /* 584 */ 'l', 'd', 'a', 'w', 32, 0, - /* 590 */ 'l', 'd', 'w', 32, 0, - /* 595 */ 'i', 'n', 'p', 'w', 32, 0, - /* 601 */ 's', 't', 'w', 32, 0, - /* 606 */ 'c', 'l', 'z', 32, 0, - /* 611 */ '#', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, - /* 631 */ 's', 'e', 't', 32, 'k', 'e', 'p', ',', 32, 'r', '1', '1', 0, - /* 644 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 657 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 664 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 674 */ '#', 'M', 'E', 'M', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0, - /* 686 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 701 */ 'l', 'd', 'a', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0, - /* 715 */ 'l', 'd', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0, - /* 728 */ 'b', 'l', 'a', 32, 'c', 'p', '[', 0, - /* 736 */ 'm', 's', 'y', 'n', 'c', 32, 'r', 'e', 's', '[', 0, - /* 747 */ 's', 'e', 't', 'p', 's', 'c', 32, 'r', 'e', 's', '[', 0, - /* 759 */ 's', 'e', 't', 'c', 32, 'r', 'e', 's', '[', 0, - /* 769 */ 's', 'e', 't', 'd', 32, 'r', 'e', 's', '[', 0, - /* 779 */ 's', 'e', 't', 'c', 'l', 'k', 32, 'r', 'e', 's', '[', 0, - /* 791 */ 'm', 'j', 'o', 'i', 'n', 32, 'r', 'e', 's', '[', 0, - /* 802 */ 's', 'e', 't', 'n', 32, 'r', 'e', 's', '[', 0, - /* 812 */ 's', 'y', 'n', 'c', 'r', 32, 'r', 'e', 's', '[', 0, - /* 823 */ 'f', 'r', 'e', 'e', 'r', 32, 'r', 'e', 's', '[', 0, - /* 834 */ 'o', 'u', 't', 's', 'h', 'r', 32, 'r', 'e', 's', '[', 0, - /* 846 */ 'c', 'h', 'k', 'c', 't', 32, 'r', 'e', 's', '[', 0, - /* 857 */ 'o', 'u', 't', 'c', 't', 32, 'r', 'e', 's', '[', 0, - /* 868 */ 'c', 'l', 'r', 'p', 't', 32, 'r', 'e', 's', '[', 0, - /* 879 */ 's', 'e', 't', 'p', 't', 32, 'r', 'e', 's', '[', 0, - /* 890 */ 'o', 'u', 't', 't', 32, 'r', 'e', 's', '[', 0, - /* 900 */ 'o', 'u', 't', 32, 'r', 'e', 's', '[', 0, - /* 909 */ 'e', 'd', 'u', 32, 'r', 'e', 's', '[', 0, - /* 918 */ 'e', 'e', 'u', 32, 'r', 'e', 's', '[', 0, - /* 927 */ 's', 'e', 't', 'e', 'v', 32, 'r', 'e', 's', '[', 0, - /* 938 */ 's', 'e', 't', 'v', 32, 'r', 'e', 's', '[', 0, - /* 948 */ 'o', 'u', 't', 'p', 'w', 32, 'r', 'e', 's', '[', 0, - /* 959 */ 's', 'e', 't', 't', 'w', 32, 'r', 'e', 's', '[', 0, - /* 970 */ 's', 'e', 't', 'r', 'd', 'y', 32, 'r', 'e', 's', '[', 0, - /* 982 */ 's', 'e', 't', 32, 'p', 's', '[', 0, - /* 990 */ 's', 'e', 't', 32, 't', '[', 0, - /* 997 */ 'i', 'n', 'i', 't', 32, 't', '[', 0, - /* 1005 */ 's', 't', 'a', 'r', 't', 32, 't', '[', 0, - /* 1014 */ 'l', 'd', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0, - /* 1029 */ 's', 't', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0, - /* 1044 */ 'l', 'd', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0, - /* 1059 */ 's', 't', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0, - /* 1074 */ 'l', 'd', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0, - /* 1089 */ 's', 't', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0, - /* 1104 */ 'l', 'd', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0, - /* 1118 */ 's', 't', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0, - /* 1132 */ 's', 's', 'y', 'n', 'c', 0, - /* 1138 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 'd', 0, - /* 1150 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'i', 'd', 0, - /* 1162 */ 'c', 'l', 'r', 'e', 0, - /* 1167 */ 'd', 'c', 'a', 'l', 'l', 0, - /* 1173 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 'e', 'p', 0, - /* 1186 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 's', 'p', 0, - /* 1199 */ 'd', 'e', 'n', 't', 's', 'p', 0, - /* 1206 */ 'd', 'r', 'e', 's', 't', 's', 'p', 0, - /* 1214 */ 't', 's', 'e', 't', 'm', 'r', 32, 'r', 0, - /* 1223 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 't', 0, - /* 1235 */ 'f', 'r', 'e', 'e', 't', 0, - /* 1241 */ 'd', 'r', 'e', 't', 0, - /* 1246 */ 'k', 'r', 'e', 't', 0, - /* 1251 */ 'w', 'a', 'i', 't', 'e', 'u', 0, + /* 0 */ 'l', + 'd', + 'a', + 'p', + 32, + 'r', + '1', + '1', + ',', + 32, + 0, + /* 11 */ 'g', + 'e', + 't', + 's', + 'r', + 32, + 'r', + '1', + '1', + ',', + 32, + 0, + /* 23 */ 's', + 'e', + 't', + 32, + 'c', + 'p', + ',', + 32, + 0, + /* 32 */ 's', + 'e', + 't', + 32, + 'd', + 'p', + ',', + 32, + 0, + /* 41 */ 's', + 'e', + 't', + 32, + 's', + 'p', + ',', + 32, + 0, + /* 50 */ 'c', + 'r', + 'c', + '3', + '2', + 32, + 0, + /* 57 */ 'l', + 'd', + 'a', + '1', + '6', + 32, + 0, + /* 64 */ 's', + 't', + '1', + '6', + 32, + 0, + /* 70 */ 'c', + 'r', + 'c', + '8', + 32, + 0, + /* 76 */ 's', + 't', + '8', + 32, + 0, + /* 81 */ '#', + 32, + 'L', + 'D', + 'A', + 'W', + 'F', + 'I', + 32, + 0, + /* 91 */ '#', + 32, + 'L', + 'D', + 'W', + 'F', + 'I', + 32, + 0, + /* 100 */ '#', + 32, + 'S', + 'T', + 'W', + 'F', + 'I', + 32, + 0, + /* 109 */ '#', + 32, + 'E', + 'H', + '_', + 'R', + 'E', + 'T', + 'U', + 'R', + 'N', + 32, + 0, + /* 122 */ '#', + 32, + 'A', + 'D', + 'J', + 'C', + 'A', + 'L', + 'L', + 'S', + 'T', + 'A', + 'C', + 'K', + 'D', + 'O', + 'W', + 'N', + 32, + 0, + /* 142 */ '#', + 32, + 'A', + 'D', + 'J', + 'C', + 'A', + 'L', + 'L', + 'S', + 'T', + 'A', + 'C', + 'K', + 'U', + 'P', + 32, + 0, + /* 160 */ '#', + 32, + 'F', + 'R', + 'A', + 'M', + 'E', + '_', + 'T', + 'O', + '_', + 'A', + 'R', + 'G', + 'S', + '_', + 'O', + 'F', + 'F', + 'S', + 'E', + 'T', + 32, + 0, + /* 184 */ 'b', + 'l', + 'a', + 32, + 0, + /* 189 */ 'l', + 's', + 'u', + 'b', + 32, + 0, + /* 195 */ 'l', + 'd', + 'c', + 32, + 0, + /* 200 */ 'l', + 'a', + 'd', + 'd', + 32, + 0, + /* 206 */ 'a', + 'n', + 'd', + 32, + 0, + /* 211 */ 'g', + 'e', + 't', + 'd', + 32, + 0, + /* 217 */ 'b', + 'f', + 32, + 0, + /* 221 */ 'e', + 'e', + 'f', + 32, + 0, + /* 226 */ 'w', + 'a', + 'i', + 't', + 'e', + 'f', + 32, + 0, + /* 234 */ 'e', + 'c', + 'a', + 'l', + 'l', + 'f', + 32, + 0, + /* 242 */ 'n', + 'e', + 'g', + 32, + 0, + /* 247 */ 'd', + 'g', + 'e', + 't', + 'r', + 'e', + 'g', + 32, + 0, + /* 256 */ 'p', + 'e', + 'e', + 'k', + 32, + 0, + /* 262 */ 'm', + 'k', + 'm', + 's', + 'k', + 32, + 0, + /* 269 */ 'b', + 'l', + 32, + 0, + /* 273 */ 't', + 'e', + 's', + 't', + 'l', + 'c', + 'l', + 32, + 0, + /* 282 */ 's', + 'h', + 'l', + 32, + 0, + /* 287 */ 'k', + 'c', + 'a', + 'l', + 'l', + 32, + 0, + /* 294 */ 'l', + 'm', + 'u', + 'l', + 32, + 0, + /* 300 */ 'e', + 'n', + 'd', + 'i', + 'n', + 32, + 0, + /* 307 */ 'g', + 'e', + 't', + 'n', + 32, + 0, + /* 313 */ 'e', + 'x', + 't', + 'd', + 'p', + 32, + 0, + /* 320 */ 'r', + 'e', + 't', + 's', + 'p', + 32, + 0, + /* 327 */ 'k', + 'e', + 'n', + 't', + 's', + 'p', + 32, + 0, + /* 335 */ 'k', + 'r', + 'e', + 's', + 't', + 's', + 'p', + 32, + 0, + /* 344 */ 'e', + 'x', + 't', + 's', + 'p', + 32, + 0, + /* 351 */ 'e', + 'q', + 32, + 0, + /* 355 */ 'a', + 's', + 'h', + 'r', + 32, + 0, + /* 361 */ 'i', + 'n', + 's', + 'h', + 'r', + 32, + 0, + /* 368 */ 'x', + 'o', + 'r', + 32, + 0, + /* 373 */ 'c', + 'l', + 'r', + 's', + 'r', + 32, + 0, + /* 380 */ 's', + 'e', + 't', + 's', + 'r', + 32, + 0, + /* 387 */ 'g', + 'e', + 't', + 'r', + 32, + 0, + /* 393 */ 'l', + 'd', + '1', + '6', + 's', + 32, + 0, + /* 400 */ 'm', + 'a', + 'c', + 'c', + 's', + 32, + 0, + /* 407 */ 'r', + 'e', + 'm', + 's', + 32, + 0, + /* 413 */ 'l', + 's', + 's', + 32, + 0, + /* 418 */ 'g', + 'e', + 't', + 't', + 's', + 32, + 0, + /* 425 */ 'd', + 'i', + 'v', + 's', + 32, + 0, + /* 431 */ 'b', + 'l', + 'a', + 't', + 32, + 0, + /* 437 */ 'b', + 't', + 32, + 0, + /* 441 */ 'i', + 'n', + 'c', + 't', + 32, + 0, + /* 447 */ 't', + 'e', + 's', + 't', + 'c', + 't', + 32, + 0, + /* 455 */ 't', + 'e', + 's', + 't', + 'w', + 'c', + 't', + 32, + 0, + /* 464 */ 'e', + 'e', + 't', + 32, + 0, + /* 469 */ 'g', + 'e', + 't', + 32, + 0, + /* 474 */ 'w', + 'a', + 'i', + 't', + 'e', + 't', + 32, + 0, + /* 482 */ 'e', + 'c', + 'a', + 'l', + 'l', + 't', + 32, + 0, + /* 490 */ 'i', + 'n', + 't', + 32, + 0, + /* 495 */ 'a', + 'n', + 'd', + 'n', + 'o', + 't', + 32, + 0, + /* 503 */ 'g', + 'e', + 't', + 's', + 't', + 32, + 0, + /* 510 */ 's', + 'e', + 'x', + 't', + 32, + 0, + /* 516 */ 'z', + 'e', + 'x', + 't', + 32, + 0, + /* 522 */ 'l', + 'd', + '8', + 'u', + 32, + 0, + /* 528 */ 'b', + 'a', + 'u', + 32, + 0, + /* 533 */ 'b', + 'u', + 32, + 0, + /* 537 */ 'm', + 'a', + 'c', + 'c', + 'u', + 32, + 0, + /* 544 */ 'r', + 'e', + 'm', + 'u', + 32, + 0, + /* 550 */ 'b', + 'r', + 'u', + 32, + 0, + /* 555 */ 'l', + 's', + 'u', + 32, + 0, + /* 560 */ 'l', + 'd', + 'i', + 'v', + 'u', + 32, + 0, + /* 567 */ 'b', + 'y', + 't', + 'e', + 'r', + 'e', + 'v', + 32, + 0, + /* 576 */ 'b', + 'i', + 't', + 'r', + 'e', + 'v', + 32, + 0, + /* 584 */ 'l', + 'd', + 'a', + 'w', + 32, + 0, + /* 590 */ 'l', + 'd', + 'w', + 32, + 0, + /* 595 */ 'i', + 'n', + 'p', + 'w', + 32, + 0, + /* 601 */ 's', + 't', + 'w', + 32, + 0, + /* 606 */ 'c', + 'l', + 'z', + 32, + 0, + /* 611 */ '#', + 32, + 'S', + 'E', + 'L', + 'E', + 'C', + 'T', + '_', + 'C', + 'C', + 32, + 'P', + 'S', + 'E', + 'U', + 'D', + 'O', + '!', + 0, + /* 631 */ 's', + 'e', + 't', + 32, + 'k', + 'e', + 'p', + ',', + 32, + 'r', + '1', + '1', + 0, + /* 644 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'E', + 'N', + 'D', + 0, + /* 657 */ 'B', + 'U', + 'N', + 'D', + 'L', + 'E', + 0, + /* 664 */ 'D', + 'B', + 'G', + '_', + 'V', + 'A', + 'L', + 'U', + 'E', + 0, + /* 674 */ '#', + 'M', + 'E', + 'M', + 'B', + 'A', + 'R', + 'R', + 'I', + 'E', + 'R', + 0, + /* 686 */ 'L', + 'I', + 'F', + 'E', + 'T', + 'I', + 'M', + 'E', + '_', + 'S', + 'T', + 'A', + 'R', + 'T', + 0, + /* 701 */ 'l', + 'd', + 'a', + 'w', + 32, + 'r', + '1', + '1', + ',', + 32, + 'c', + 'p', + '[', + 0, + /* 715 */ 'l', + 'd', + 'w', + 32, + 'r', + '1', + '1', + ',', + 32, + 'c', + 'p', + '[', + 0, + /* 728 */ 'b', + 'l', + 'a', + 32, + 'c', + 'p', + '[', + 0, + /* 736 */ 'm', + 's', + 'y', + 'n', + 'c', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 747 */ 's', + 'e', + 't', + 'p', + 's', + 'c', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 759 */ 's', + 'e', + 't', + 'c', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 769 */ 's', + 'e', + 't', + 'd', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 779 */ 's', + 'e', + 't', + 'c', + 'l', + 'k', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 791 */ 'm', + 'j', + 'o', + 'i', + 'n', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 802 */ 's', + 'e', + 't', + 'n', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 812 */ 's', + 'y', + 'n', + 'c', + 'r', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 823 */ 'f', + 'r', + 'e', + 'e', + 'r', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 834 */ 'o', + 'u', + 't', + 's', + 'h', + 'r', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 846 */ 'c', + 'h', + 'k', + 'c', + 't', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 857 */ 'o', + 'u', + 't', + 'c', + 't', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 868 */ 'c', + 'l', + 'r', + 'p', + 't', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 879 */ 's', + 'e', + 't', + 'p', + 't', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 890 */ 'o', + 'u', + 't', + 't', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 900 */ 'o', + 'u', + 't', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 909 */ 'e', + 'd', + 'u', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 918 */ 'e', + 'e', + 'u', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 927 */ 's', + 'e', + 't', + 'e', + 'v', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 938 */ 's', + 'e', + 't', + 'v', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 948 */ 'o', + 'u', + 't', + 'p', + 'w', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 959 */ 's', + 'e', + 't', + 't', + 'w', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 970 */ 's', + 'e', + 't', + 'r', + 'd', + 'y', + 32, + 'r', + 'e', + 's', + '[', + 0, + /* 982 */ 's', + 'e', + 't', + 32, + 'p', + 's', + '[', + 0, + /* 990 */ 's', + 'e', + 't', + 32, + 't', + '[', + 0, + /* 997 */ 'i', + 'n', + 'i', + 't', + 32, + 't', + '[', + 0, + /* 1005 */ 's', + 't', + 'a', + 'r', + 't', + 32, + 't', + '[', + 0, + /* 1014 */ 'l', + 'd', + 'w', + 32, + 's', + 'p', + 'c', + ',', + 32, + 's', + 'p', + '[', + '1', + ']', + 0, + /* 1029 */ 's', + 't', + 'w', + 32, + 's', + 'p', + 'c', + ',', + 32, + 's', + 'p', + '[', + '1', + ']', + 0, + /* 1044 */ 'l', + 'd', + 'w', + 32, + 's', + 's', + 'r', + ',', + 32, + 's', + 'p', + '[', + '2', + ']', + 0, + /* 1059 */ 's', + 't', + 'w', + 32, + 's', + 's', + 'r', + ',', + 32, + 's', + 'p', + '[', + '2', + ']', + 0, + /* 1074 */ 'l', + 'd', + 'w', + 32, + 's', + 'e', + 'd', + ',', + 32, + 's', + 'p', + '[', + '3', + ']', + 0, + /* 1089 */ 's', + 't', + 'w', + 32, + 's', + 'e', + 'd', + ',', + 32, + 's', + 'p', + '[', + '3', + ']', + 0, + /* 1104 */ 'l', + 'd', + 'w', + 32, + 'e', + 't', + ',', + 32, + 's', + 'p', + '[', + '4', + ']', + 0, + /* 1118 */ 's', + 't', + 'w', + 32, + 'e', + 't', + ',', + 32, + 's', + 'p', + '[', + '4', + ']', + 0, + /* 1132 */ 's', + 's', + 'y', + 'n', + 'c', + 0, + /* 1138 */ 'g', + 'e', + 't', + 32, + 'r', + '1', + '1', + ',', + 32, + 'e', + 'd', + 0, + /* 1150 */ 'g', + 'e', + 't', + 32, + 'r', + '1', + '1', + ',', + 32, + 'i', + 'd', + 0, + /* 1162 */ 'c', + 'l', + 'r', + 'e', + 0, + /* 1167 */ 'd', + 'c', + 'a', + 'l', + 'l', + 0, + /* 1173 */ 'g', + 'e', + 't', + 32, + 'r', + '1', + '1', + ',', + 32, + 'k', + 'e', + 'p', + 0, + /* 1186 */ 'g', + 'e', + 't', + 32, + 'r', + '1', + '1', + ',', + 32, + 'k', + 's', + 'p', + 0, + /* 1199 */ 'd', + 'e', + 'n', + 't', + 's', + 'p', + 0, + /* 1206 */ 'd', + 'r', + 'e', + 's', + 't', + 's', + 'p', + 0, + /* 1214 */ 't', + 's', + 'e', + 't', + 'm', + 'r', + 32, + 'r', + 0, + /* 1223 */ 'g', + 'e', + 't', + 32, + 'r', + '1', + '1', + ',', + 32, + 'e', + 't', + 0, + /* 1235 */ 'f', + 'r', + 'e', + 'e', + 't', + 0, + /* 1241 */ 'd', + 'r', + 'e', + 't', + 0, + /* 1246 */ 'k', + 'r', + 'e', + 't', + 0, + /* 1251 */ 'w', + 'a', + 'i', + 't', + 'e', + 'u', + 0, }; // Emit the opcode for the instruction. uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; // assert(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 2047)-1); + SStream_concat0(O, AsmStrs + (Bits & 2047) - 1); #endif - - if (strchr((const char *)AsmStrs+(Bits & 2047)-1, '[')) { + if (strchr((const char *)AsmStrs + (Bits & 2047) - 1, '[')) { set_mem_access(MI, true, 0); } // Fragment 0 encoded into 2 bits for 4 unique commands. - //printf(">>%s\n", AsmStrs+(Bits & 2047)-1); - //printf("Frag-0: %u\n", (Bits >> 11) & 3); + // printf(">>%s\n", AsmStrs+(Bits & 2047)-1); + // printf("Frag-0: %u\n", (Bits >> 11) & 3); switch ((Bits >> 11) & 3) { - default: // unreachable. + default: // unreachable. case 0: // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, CLRE_0R, DCALL_0R, DE... // already done. this means we have to extract details out ourself. - XCore_insn_extract(MI, (const char *)AsmStrs+(Bits & 2047)-1); + XCore_insn_extract(MI, (const char *)AsmStrs + (Bits & 2047) - 1); return; break; case 1: // ADD_2rus, ADD_3r, ADJCALLSTACKDOWN, ADJCALLSTACKUP, ANDNOT_2r, AND_3r,... - printOperand(MI, 0, O); + printOperand(MI, 0, O); break; case 2: // BR_JT, BR_JT32, CRC8_l4r, INITCP_2r, INITDP_2r, INITLR_l2r, INITPC_2r,... - printOperand(MI, 1, O); + printOperand(MI, 1, O); break; case 3: // OUTSHR_2r, TSETR_3r - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; } - // Fragment 1 encoded into 5 bits for 17 unique commands. - //printf("Frag-1: %u\n", (Bits >> 13) & 31); + // printf("Frag-1: %u\n", (Bits >> 13) & 31); switch ((Bits >> 13) & 31) { - default: // unreachable. + default: // unreachable. case 0: // ADD_2rus, ADD_3r, ANDNOT_2r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r,... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 1: // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BAU_1r, BLAT_lu6, BLAT_u6, BLA_1r, B... @@ -468,150 +1575,148 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 2: // BLACP_lu10, BLACP_u10, CLRPT_1R, EDU_1r, EEU_1r, FREER_1r, LDAWCP_lu6,... - SStream_concat0(O, "]"); + SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 3: // BR_JT, BR_JT32 - SStream_concat0(O, "\n"); + SStream_concat0(O, "\n"); break; case 4: // CHKCT_2r, CHKCT_rus, OUTCT_2r, OUTCT_rus, OUTPW_l2rus, OUTSHR_2r, OUTT... - SStream_concat0(O, "], "); + SStream_concat0(O, "], "); set_mem_access(MI, false, 0); break; case 5: // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT... - SStream_concat0(O, ", res["); + SStream_concat0(O, ", res["); set_mem_access(MI, true, 0); break; case 6: // GETPS_l2r - SStream_concat0(O, ", ps["); + SStream_concat0(O, ", ps["); set_mem_access(MI, true, 0); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 7: // INITCP_2r - SStream_concat0(O, "]:cp, "); + SStream_concat0(O, "]:cp, "); set_mem_access(MI, false, XCORE_REG_CP); - printOperand(MI, 0, O); + printOperand(MI, 0, O); return; break; case 8: // INITDP_2r - SStream_concat0(O, "]:dp, "); + SStream_concat0(O, "]:dp, "); set_mem_access(MI, false, XCORE_REG_DP); - printOperand(MI, 0, O); + printOperand(MI, 0, O); return; break; case 9: // INITLR_l2r - SStream_concat0(O, "]:lr, "); + SStream_concat0(O, "]:lr, "); set_mem_access(MI, false, XCORE_REG_LR); - printOperand(MI, 0, O); + printOperand(MI, 0, O); return; break; case 10: // INITPC_2r - SStream_concat0(O, "]:pc, "); + SStream_concat0(O, "]:pc, "); set_mem_access(MI, false, XCORE_REG_PC); - printOperand(MI, 0, O); + printOperand(MI, 0, O); return; break; case 11: // INITSP_2r - SStream_concat0(O, "]:sp, "); + SStream_concat0(O, "]:sp, "); set_mem_access(MI, false, XCORE_REG_SP); - printOperand(MI, 0, O); + printOperand(MI, 0, O); return; break; case 12: // LDAWDP_lru6, LDAWDP_ru6, LDWDP_lru6, LDWDP_ru6, STWDP_lru6, STWDP_ru6 - SStream_concat0(O, ", dp["); + SStream_concat0(O, ", dp["); set_mem_access(MI, true, XCORE_REG_DP); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 13: // LDAWSP_lru6, LDAWSP_ru6, LDWSP_lru6, LDWSP_ru6, STWSP_lru6, STWSP_ru6 - SStream_concat0(O, ", sp["); + SStream_concat0(O, ", sp["); set_mem_access(MI, true, XCORE_REG_SP); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 14: // LDWCP_lru6, LDWCP_ru6 - SStream_concat0(O, ", cp["); + SStream_concat0(O, ", cp["); set_mem_access(MI, true, XCORE_REG_CP); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 15: // SETEV_1r, SETV_1r - SStream_concat0(O, "], r11"); + SStream_concat0(O, "], r11"); set_mem_access(MI, false, 0); return; break; case 16: // TSETR_3r - SStream_concat0(O, "]:r"); + SStream_concat0(O, "]:r"); set_mem_access(MI, false, 0); - printOperand(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); return; break; } - // Fragment 2 encoded into 3 bits for 5 unique commands. - //printf("Frag-2: %u\n", (Bits >> 18) & 7); + // printf("Frag-2: %u\n", (Bits >> 18) & 7); switch ((Bits >> 18) & 7) { - default: // unreachable. + default: // unreachable. case 0: // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r, BRBF_lru6,... - printOperand(MI, 1, O); + printOperand(MI, 1, O); break; case 1: // ANDNOT_2r, CRC_l3r, INSHR_2r, SEXT_2r, SEXT_rus, ZEXT_2r, ZEXT_rus - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; case 2: // BR_JT - printInlineJT(MI, 0, O); + printInlineJT(MI, 0, O); return; break; case 3: // BR_JT32 - printInlineJT32(MI, 0, O); + printInlineJT32(MI, 0, O); return; break; case 4: // CRC8_l4r, LADD_l5r, LSUB_l5r, OUTPW_l2rus - printOperand(MI, 0, O); - SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); break; } - // Fragment 3 encoded into 3 bits for 8 unique commands. - //printf("Frag-3: %u\n", (Bits >> 21) & 7); + // printf("Frag-3: %u\n", (Bits >> 21) & 7); switch ((Bits >> 21) & 7) { - default: // unreachable. + default: // unreachable. case 0: // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, CRC_l3r, DIVS_l3r, DIV... - SStream_concat0(O, ", "); + SStream_concat0(O, ", "); break; case 1: // ANDNOT_2r, BITREV_l2r, BRBF_lru6, BRBF_ru6, BRBT_lru6, BRBT_ru6, BRFF_... @@ -619,74 +1724,73 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; case 2: // CRC8_l4r - printOperand(MI, 3, O); - SStream_concat0(O, ", "); - printOperand(MI, 4, O); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); return; break; case 3: // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT... - SStream_concat0(O, "]"); + SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 4: // INPW_l2rus - SStream_concat0(O, "], "); + SStream_concat0(O, "], "); set_mem_access(MI, false, 0); - printOperand(MI, 2, O); + printOperand(MI, 2, O); return; break; case 5: // LADD_l5r, LSUB_l5r, OUTPW_l2rus - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; case 6: // LD16S_3r, LD8U_3r, LDA16F_l3r, LDAWF_l2rus, LDAWF_l3r, LDW_2rus, LDW_3... - SStream_concat0(O, "["); + SStream_concat0(O, "["); set_mem_access(MI, true, 0xffff); - printOperand(MI, 2, O); - SStream_concat0(O, "]"); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 7: // LDA16B_l3r, LDAWB_l2rus, LDAWB_l3r - SStream_concat0(O, "[-"); + SStream_concat0(O, "[-"); set_mem_access(MI, true, -0xffff); - printOperand(MI, 2, O); - SStream_concat0(O, "]"); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; } - // Fragment 4 encoded into 3 bits for 5 unique commands. - //printf("Frag-4: %u\n", (Bits >> 24) & 7); + // printf("Frag-4: %u\n", (Bits >> 24) & 7); switch ((Bits >> 24) & 7) { - default: // unreachable. + default: // unreachable. case 0: // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ... - printOperand(MI, 2, O); + printOperand(MI, 2, O); break; case 1: // CRC_l3r - printOperand(MI, 3, O); + printOperand(MI, 3, O); return; break; case 2: // LADD_l5r, LSUB_l5r - SStream_concat0(O, ", "); - printOperand(MI, 3, O); - SStream_concat0(O, ", "); - printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); return; break; case 3: // LDIVU_l5r, MACCS_l4r, MACCU_l4r - printOperand(MI, 4, O); - SStream_concat0(O, ", "); + printOperand(MI, 4, O); + SStream_concat0(O, ", "); break; case 4: // OUTPW_l2rus @@ -694,78 +1798,74 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) break; } - // Fragment 5 encoded into 2 bits for 4 unique commands. - //printf("Frag-5: %u\n", (Bits >> 27) & 3); + // printf("Frag-5: %u\n", (Bits >> 27) & 3); switch ((Bits >> 27) & 3) { - default: // unreachable. + default: // unreachable. case 0: // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ... return; break; case 1: // LDIVU_l5r - printOperand(MI, 2, O); - SStream_concat0(O, ", "); - printOperand(MI, 3, O); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); return; break; case 2: // LMUL_l6r - SStream_concat0(O, ", "); - printOperand(MI, 3, O); - SStream_concat0(O, ", "); - printOperand(MI, 4, O); - SStream_concat0(O, ", "); - printOperand(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); return; break; case 3: // MACCS_l4r, MACCU_l4r - printOperand(MI, 5, O); + printOperand(MI, 5, O); return; break; } } - /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. -static const char *getRegisterName(unsigned RegNo) -{ +static const char *getRegisterName(unsigned RegNo) { // assert(RegNo && RegNo < 17 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrs[] = { - /* 0 */ 'r', '1', '0', 0, - /* 4 */ 'r', '0', 0, - /* 7 */ 'r', '1', '1', 0, - /* 11 */ 'r', '1', 0, - /* 14 */ 'r', '2', 0, - /* 17 */ 'r', '3', 0, - /* 20 */ 'r', '4', 0, - /* 23 */ 'r', '5', 0, - /* 26 */ 'r', '6', 0, - /* 29 */ 'r', '7', 0, - /* 32 */ 'r', '8', 0, - /* 35 */ 'r', '9', 0, - /* 38 */ 'c', 'p', 0, - /* 41 */ 'd', 'p', 0, - /* 44 */ 's', 'p', 0, - /* 47 */ 'l', 'r', 0, + /* 0 */ 'r', '1', '0', 0, + /* 4 */ 'r', '0', 0, + /* 7 */ 'r', '1', '1', 0, + /* 11 */ 'r', '1', 0, + /* 14 */ 'r', '2', 0, + /* 17 */ 'r', '3', 0, + /* 20 */ 'r', '4', 0, + /* 23 */ 'r', '5', 0, + /* 26 */ 'r', '6', 0, + /* 29 */ 'r', '7', 0, + /* 32 */ 'r', '8', 0, + /* 35 */ 'r', '9', 0, + /* 38 */ 'c', 'p', 0, + /* 41 */ 'd', 'p', 0, + /* 44 */ 's', 'p', 0, + /* 47 */ 'l', 'r', 0, }; static const uint8_t RegAsmOffset[] = { - 38, 41, 47, 44, 4, 11, 14, 17, 20, 23, 26, 29, 32, 35, - 0, 7, + 38, 41, 47, 44, 4, 11, 14, 17, 20, 23, 26, 29, 32, 35, 0, 7, }; - //int i; - //for (i = 0; i < sizeof(RegAsmOffset); i++) + // int i; + // for (i = 0; i < sizeof(RegAsmOffset); i++) // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); - //printf("*************************\n"); - return AsmStrs+RegAsmOffset[RegNo-1]; + // printf("*************************\n"); + return AsmStrs + RegAsmOffset[RegNo - 1]; #else return NULL; #endif diff --git a/arch/XCore/XCoreGenDisassemblerTables.inc b/arch/XCore/XCoreGenDisassemblerTables.inc index fe4e67080e..0ac433dae4 100644 --- a/arch/XCore/XCoreGenDisassemblerTables.inc +++ b/arch/XCore/XCoreGenDisassemblerTables.inc @@ -1,853 +1,5900 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * XCore Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Phosphorus15 , Year 2021 */ +/* This generator is under https://github.com/rizinorg/llvm-capstone */ +/* Automatically generated file, do not edit! */ -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#include "../../MCInst.h" #include "../../LEB128.h" +#include "../../MCInst.h" + +#ifdef MIPS_GET_DISASSEMBLER +#undef MIPS_GET_DISASSEMBLER // Helper function for extracting fields from encoded instructions. -#define FieldFromInstruction(fname, InsnType) \ -static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ -{ \ - InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ - fieldMask = (InsnType)(-1LL); \ - else \ - fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ - return (insn & fieldMask) >> startBit; \ -} +#define FieldFromInstruction(fname, InsnType) \ + static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) { \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ + } static const uint8_t DecoderTable16[] = { -/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... -/* 3 */ MCD_OPC_FilterValue, 0, 108, 0, // Skip to: 115 -/* 7 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... -/* 10 */ MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 19 -/* 15 */ MCD_OPC_Decode, 243, 1, 0, // Opcode: WAITEU_0R -/* 19 */ MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 27 -/* 24 */ MCD_OPC_Decode, 59, 0, // Opcode: CLRE_0R -/* 27 */ MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 36 -/* 32 */ MCD_OPC_Decode, 218, 1, 0, // Opcode: SSYNC_0r -/* 36 */ MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 44 -/* 41 */ MCD_OPC_Decode, 93, 0, // Opcode: FREET_0R -/* 44 */ MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 52 -/* 49 */ MCD_OPC_Decode, 68, 0, // Opcode: DCALL_0R -/* 52 */ MCD_OPC_FilterValue, 253, 15, 3, 0, // Skip to: 60 -/* 57 */ MCD_OPC_Decode, 125, 0, // Opcode: KRET_0R -/* 60 */ MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 68 -/* 65 */ MCD_OPC_Decode, 74, 0, // Opcode: DRET_0R -/* 68 */ MCD_OPC_FilterValue, 255, 15, 4, 0, // Skip to: 77 -/* 73 */ MCD_OPC_Decode, 199, 1, 0, // Opcode: SETKEP_0R -/* 77 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 80 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 87 -/* 84 */ MCD_OPC_Decode, 77, 1, // Opcode: EDU_1r -/* 87 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 94 -/* 91 */ MCD_OPC_Decode, 80, 1, // Opcode: EEU_1r -/* 94 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 97 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 104 -/* 101 */ MCD_OPC_Decode, 111, 2, // Opcode: INITPC_2r -/* 104 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 111 -/* 108 */ MCD_OPC_Decode, 105, 2, // Opcode: GETST_2r -/* 111 */ MCD_OPC_Decode, 230, 1, 3, // Opcode: STW_2rus -/* 115 */ MCD_OPC_FilterValue, 1, 114, 0, // Skip to: 233 -/* 119 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... -/* 122 */ MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 131 -/* 127 */ MCD_OPC_Decode, 152, 1, 0, // Opcode: LDSPC_0R -/* 131 */ MCD_OPC_FilterValue, 237, 15, 4, 0, // Skip to: 140 -/* 136 */ MCD_OPC_Decode, 223, 1, 0, // Opcode: STSPC_0R -/* 140 */ MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 149 -/* 145 */ MCD_OPC_Decode, 153, 1, 0, // Opcode: LDSSR_0R -/* 149 */ MCD_OPC_FilterValue, 239, 15, 4, 0, // Skip to: 158 -/* 154 */ MCD_OPC_Decode, 224, 1, 0, // Opcode: STSSR_0R -/* 158 */ MCD_OPC_FilterValue, 252, 15, 4, 0, // Skip to: 167 -/* 163 */ MCD_OPC_Decode, 222, 1, 0, // Opcode: STSED_0R -/* 167 */ MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 176 -/* 172 */ MCD_OPC_Decode, 221, 1, 0, // Opcode: STET_0R -/* 176 */ MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 184 -/* 181 */ MCD_OPC_Decode, 95, 0, // Opcode: GETED_0R -/* 184 */ MCD_OPC_FilterValue, 255, 15, 3, 0, // Skip to: 192 -/* 189 */ MCD_OPC_Decode, 96, 0, // Opcode: GETET_0R -/* 192 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 195 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 203 -/* 199 */ MCD_OPC_Decode, 242, 1, 1, // Opcode: WAITET_1R -/* 203 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 211 -/* 207 */ MCD_OPC_Decode, 241, 1, 1, // Opcode: WAITEF_1R -/* 211 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 214 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 221 -/* 218 */ MCD_OPC_Decode, 109, 2, // Opcode: INITDP_2r -/* 221 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 229 -/* 225 */ MCD_OPC_Decode, 183, 1, 4, // Opcode: OUTT_2r -/* 229 */ MCD_OPC_Decode, 163, 1, 3, // Opcode: LDW_2rus -/* 233 */ MCD_OPC_FilterValue, 2, 100, 0, // Skip to: 337 -/* 237 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... -/* 240 */ MCD_OPC_FilterValue, 236, 15, 3, 0, // Skip to: 248 -/* 245 */ MCD_OPC_Decode, 69, 0, // Opcode: DENTSP_0R -/* 248 */ MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 256 -/* 253 */ MCD_OPC_Decode, 73, 0, // Opcode: DRESTSP_0R -/* 256 */ MCD_OPC_FilterValue, 238, 15, 3, 0, // Skip to: 264 -/* 261 */ MCD_OPC_Decode, 97, 0, // Opcode: GETID_0R -/* 264 */ MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 272 -/* 269 */ MCD_OPC_Decode, 98, 0, // Opcode: GETKEP_0R -/* 272 */ MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 280 -/* 277 */ MCD_OPC_Decode, 99, 0, // Opcode: GETKSP_0R -/* 280 */ MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 289 -/* 285 */ MCD_OPC_Decode, 151, 1, 0, // Opcode: LDSED_0R -/* 289 */ MCD_OPC_FilterValue, 254, 15, 4, 0, // Skip to: 298 -/* 294 */ MCD_OPC_Decode, 149, 1, 0, // Opcode: LDET_0R -/* 298 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 301 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 308 -/* 305 */ MCD_OPC_Decode, 92, 1, // Opcode: FREER_1r -/* 308 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 316 -/* 312 */ MCD_OPC_Decode, 171, 1, 1, // Opcode: MJOIN_1r -/* 316 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 319 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 326 -/* 323 */ MCD_OPC_Decode, 112, 2, // Opcode: INITSP_2r -/* 326 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 334 -/* 330 */ MCD_OPC_Decode, 197, 1, 4, // Opcode: SETD_2r -/* 334 */ MCD_OPC_Decode, 23, 5, // Opcode: ADD_3r -/* 337 */ MCD_OPC_FilterValue, 3, 41, 0, // Skip to: 382 -/* 341 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 344 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 352 -/* 348 */ MCD_OPC_Decode, 240, 1, 1, // Opcode: TSTART_1R -/* 352 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 360 -/* 356 */ MCD_OPC_Decode, 174, 1, 1, // Opcode: MSYNC_1r -/* 360 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 363 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 370 -/* 367 */ MCD_OPC_Decode, 108, 2, // Opcode: INITCP_2r -/* 370 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 378 -/* 374 */ MCD_OPC_Decode, 238, 1, 6, // Opcode: TSETMR_2r -/* 378 */ MCD_OPC_Decode, 233, 1, 5, // Opcode: SUB_3r -/* 382 */ MCD_OPC_FilterValue, 4, 30, 0, // Skip to: 416 -/* 386 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 389 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 396 -/* 393 */ MCD_OPC_Decode, 36, 1, // Opcode: BLA_1r -/* 396 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 403 -/* 400 */ MCD_OPC_Decode, 30, 1, // Opcode: BAU_1r -/* 403 */ MCD_OPC_CheckField, 4, 1, 1, 3, 0, // Skip to: 412 -/* 409 */ MCD_OPC_Decode, 79, 2, // Opcode: EET_2r -/* 412 */ MCD_OPC_Decode, 215, 1, 5, // Opcode: SHL_3r -/* 416 */ MCD_OPC_FilterValue, 5, 39, 0, // Skip to: 459 -/* 420 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 423 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 430 -/* 427 */ MCD_OPC_Decode, 53, 1, // Opcode: BRU_1r -/* 430 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 438 -/* 434 */ MCD_OPC_Decode, 205, 1, 1, // Opcode: SETSP_1r -/* 438 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 441 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 448 -/* 445 */ MCD_OPC_Decode, 26, 7, // Opcode: ANDNOT_2r -/* 448 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 455 -/* 452 */ MCD_OPC_Decode, 78, 2, // Opcode: EEF_2r -/* 455 */ MCD_OPC_Decode, 217, 1, 5, // Opcode: SHR_3r -/* 459 */ MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 504 -/* 463 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 466 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 474 -/* 470 */ MCD_OPC_Decode, 196, 1, 1, // Opcode: SETDP_1r -/* 474 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 482 -/* 478 */ MCD_OPC_Decode, 192, 1, 1, // Opcode: SETCP_1r -/* 482 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 485 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 493 -/* 489 */ MCD_OPC_Decode, 212, 1, 7, // Opcode: SEXT_2r -/* 493 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 501 -/* 497 */ MCD_OPC_Decode, 213, 1, 8, // Opcode: SEXT_rus -/* 501 */ MCD_OPC_Decode, 86, 5, // Opcode: EQ_3r -/* 504 */ MCD_OPC_FilterValue, 7, 39, 0, // Skip to: 547 -/* 508 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 511 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 518 -/* 515 */ MCD_OPC_Decode, 70, 1, // Opcode: DGETREG_1r -/* 518 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526 -/* 522 */ MCD_OPC_Decode, 198, 1, 1, // Opcode: SETEV_1r -/* 526 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 529 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 536 -/* 533 */ MCD_OPC_Decode, 106, 2, // Opcode: GETTS_2r -/* 536 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 544 -/* 540 */ MCD_OPC_Decode, 203, 1, 4, // Opcode: SETPT_2r -/* 544 */ MCD_OPC_Decode, 27, 5, // Opcode: AND_3r -/* 547 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 592 -/* 551 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 554 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 561 -/* 558 */ MCD_OPC_Decode, 118, 1, // Opcode: KCALL_1r -/* 561 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 569 -/* 565 */ MCD_OPC_Decode, 211, 1, 1, // Opcode: SETV_1r -/* 569 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 572 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 580 -/* 576 */ MCD_OPC_Decode, 245, 1, 7, // Opcode: ZEXT_2r -/* 580 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 588 -/* 584 */ MCD_OPC_Decode, 246, 1, 8, // Opcode: ZEXT_rus -/* 588 */ MCD_OPC_Decode, 178, 1, 5, // Opcode: OR_3r -/* 592 */ MCD_OPC_FilterValue, 9, 40, 0, // Skip to: 636 -/* 596 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 599 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 606 -/* 603 */ MCD_OPC_Decode, 75, 1, // Opcode: ECALLF_1r -/* 606 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 613 -/* 610 */ MCD_OPC_Decode, 76, 1, // Opcode: ECALLT_1r -/* 613 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 616 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 624 -/* 620 */ MCD_OPC_Decode, 179, 1, 2, // Opcode: OUTCT_2r -/* 624 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 632 -/* 628 */ MCD_OPC_Decode, 180, 1, 9, // Opcode: OUTCT_rus -/* 632 */ MCD_OPC_Decode, 164, 1, 5, // Opcode: LDW_3r -/* 636 */ MCD_OPC_FilterValue, 10, 19, 0, // Skip to: 659 -/* 640 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 643 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 651 -/* 647 */ MCD_OPC_Decode, 226, 1, 10, // Opcode: STWDP_ru6 -/* 651 */ MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 1221 -/* 655 */ MCD_OPC_Decode, 229, 1, 10, // Opcode: STWSP_ru6 -/* 659 */ MCD_OPC_FilterValue, 11, 19, 0, // Skip to: 682 -/* 663 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 666 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 674 -/* 670 */ MCD_OPC_Decode, 159, 1, 10, // Opcode: LDWDP_ru6 -/* 674 */ MCD_OPC_FilterValue, 1, 31, 2, // Skip to: 1221 -/* 678 */ MCD_OPC_Decode, 162, 1, 10, // Opcode: LDWSP_ru6 -/* 682 */ MCD_OPC_FilterValue, 12, 19, 0, // Skip to: 705 -/* 686 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 689 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 697 -/* 693 */ MCD_OPC_Decode, 141, 1, 10, // Opcode: LDAWDP_ru6 -/* 697 */ MCD_OPC_FilterValue, 1, 8, 2, // Skip to: 1221 -/* 701 */ MCD_OPC_Decode, 146, 1, 10, // Opcode: LDAWSP_ru6 -/* 705 */ MCD_OPC_FilterValue, 13, 19, 0, // Skip to: 728 -/* 709 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 712 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 720 -/* 716 */ MCD_OPC_Decode, 148, 1, 10, // Opcode: LDC_ru6 -/* 720 */ MCD_OPC_FilterValue, 1, 241, 1, // Skip to: 1221 -/* 724 */ MCD_OPC_Decode, 156, 1, 10, // Opcode: LDWCP_ru6 -/* 728 */ MCD_OPC_FilterValue, 14, 80, 0, // Skip to: 812 -/* 732 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 735 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 773 -/* 739 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 742 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 749 -/* 746 */ MCD_OPC_Decode, 52, 11, // Opcode: BRFU_u6 -/* 749 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 756 -/* 753 */ MCD_OPC_Decode, 35, 11, // Opcode: BLAT_u6 -/* 756 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 763 -/* 760 */ MCD_OPC_Decode, 88, 11, // Opcode: EXTDP_u6 -/* 763 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 770 -/* 767 */ MCD_OPC_Decode, 120, 11, // Opcode: KCALL_u6 -/* 770 */ MCD_OPC_Decode, 50, 12, // Opcode: BRFT_ru6 -/* 773 */ MCD_OPC_FilterValue, 1, 188, 1, // Skip to: 1221 -/* 777 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 780 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 787 -/* 784 */ MCD_OPC_Decode, 46, 13, // Opcode: BRBU_u6 -/* 787 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 794 -/* 791 */ MCD_OPC_Decode, 84, 11, // Opcode: ENTSP_u6 -/* 794 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 801 -/* 798 */ MCD_OPC_Decode, 90, 11, // Opcode: EXTSP_u6 -/* 801 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 809 -/* 805 */ MCD_OPC_Decode, 189, 1, 11, // Opcode: RETSP_u6 -/* 809 */ MCD_OPC_Decode, 44, 14, // Opcode: BRBT_ru6 -/* 812 */ MCD_OPC_FilterValue, 15, 67, 0, // Skip to: 883 -/* 816 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 819 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 858 -/* 823 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 826 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 833 -/* 830 */ MCD_OPC_Decode, 64, 11, // Opcode: CLRSR_u6 -/* 833 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 841 -/* 837 */ MCD_OPC_Decode, 209, 1, 11, // Opcode: SETSR_u6 -/* 841 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 848 -/* 845 */ MCD_OPC_Decode, 122, 11, // Opcode: KENTSP_u6 -/* 848 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 855 -/* 852 */ MCD_OPC_Decode, 124, 11, // Opcode: KRESTSP_u6 -/* 855 */ MCD_OPC_Decode, 48, 12, // Opcode: BRFF_ru6 -/* 858 */ MCD_OPC_FilterValue, 1, 103, 1, // Skip to: 1221 -/* 862 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... -/* 865 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 872 -/* 869 */ MCD_OPC_Decode, 104, 11, // Opcode: GETSR_u6 -/* 872 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 880 -/* 876 */ MCD_OPC_Decode, 139, 1, 11, // Opcode: LDAWCP_u6 -/* 880 */ MCD_OPC_Decode, 42, 14, // Opcode: BRBF_ru6 -/* 883 */ MCD_OPC_FilterValue, 16, 38, 0, // Skip to: 925 -/* 887 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... -/* 890 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 897 -/* 894 */ MCD_OPC_Decode, 60, 1, // Opcode: CLRPT_1R -/* 897 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 905 -/* 901 */ MCD_OPC_Decode, 234, 1, 1, // Opcode: SYNCR_1r -/* 905 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 908 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 915 -/* 912 */ MCD_OPC_Decode, 102, 9, // Opcode: GETR_rus -/* 915 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 922 -/* 919 */ MCD_OPC_Decode, 107, 2, // Opcode: INCT_2r -/* 922 */ MCD_OPC_Decode, 127, 5, // Opcode: LD16S_3r -/* 925 */ MCD_OPC_FilterValue, 17, 22, 0, // Skip to: 951 -/* 929 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 932 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 940 -/* 936 */ MCD_OPC_Decode, 177, 1, 2, // Opcode: NOT -/* 940 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 947 -/* 944 */ MCD_OPC_Decode, 115, 2, // Opcode: INT_2r -/* 947 */ MCD_OPC_Decode, 128, 1, 5, // Opcode: LD8U_3r -/* 951 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 976 -/* 955 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 958 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 966 -/* 962 */ MCD_OPC_Decode, 176, 1, 2, // Opcode: NEG -/* 966 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 973 -/* 970 */ MCD_OPC_Decode, 82, 2, // Opcode: ENDIN_2r -/* 973 */ MCD_OPC_Decode, 22, 3, // Opcode: ADD_2rus -/* 976 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 984 -/* 980 */ MCD_OPC_Decode, 232, 1, 3, // Opcode: SUB_2rus -/* 984 */ MCD_OPC_FilterValue, 20, 23, 0, // Skip to: 1011 -/* 988 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 991 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 999 -/* 995 */ MCD_OPC_Decode, 172, 1, 2, // Opcode: MKMSK_2r -/* 999 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1007 -/* 1003 */ MCD_OPC_Decode, 173, 1, 15, // Opcode: MKMSK_rus -/* 1007 */ MCD_OPC_Decode, 214, 1, 16, // Opcode: SHL_2rus -/* 1011 */ MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1038 -/* 1015 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1018 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1026 -/* 1022 */ MCD_OPC_Decode, 184, 1, 4, // Opcode: OUT_2r -/* 1026 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1034 -/* 1030 */ MCD_OPC_Decode, 182, 1, 7, // Opcode: OUTSHR_2r -/* 1034 */ MCD_OPC_Decode, 216, 1, 16, // Opcode: SHR_2rus -/* 1038 */ MCD_OPC_FilterValue, 22, 20, 0, // Skip to: 1062 -/* 1042 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1045 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1052 -/* 1049 */ MCD_OPC_Decode, 116, 2, // Opcode: IN_2r -/* 1052 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1059 -/* 1056 */ MCD_OPC_Decode, 114, 7, // Opcode: INSHR_2r -/* 1059 */ MCD_OPC_Decode, 85, 3, // Opcode: EQ_2rus -/* 1062 */ MCD_OPC_FilterValue, 23, 23, 0, // Skip to: 1089 -/* 1066 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1069 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1077 -/* 1073 */ MCD_OPC_Decode, 185, 1, 2, // Opcode: PEEK_2r -/* 1077 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1085 -/* 1081 */ MCD_OPC_Decode, 235, 1, 2, // Opcode: TESTCT_2r -/* 1085 */ MCD_OPC_Decode, 239, 1, 17, // Opcode: TSETR_3r -/* 1089 */ MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1116 -/* 1093 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1096 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1104 -/* 1100 */ MCD_OPC_Decode, 201, 1, 4, // Opcode: SETPSC_2r -/* 1104 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1112 -/* 1108 */ MCD_OPC_Decode, 237, 1, 2, // Opcode: TESTWCT_2r -/* 1112 */ MCD_OPC_Decode, 166, 1, 5, // Opcode: LSS_3r -/* 1116 */ MCD_OPC_FilterValue, 25, 21, 0, // Skip to: 1141 -/* 1120 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 1123 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1130 -/* 1127 */ MCD_OPC_Decode, 57, 2, // Opcode: CHKCT_2r -/* 1130 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1137 -/* 1134 */ MCD_OPC_Decode, 58, 15, // Opcode: CHKCT_rus -/* 1137 */ MCD_OPC_Decode, 168, 1, 5, // Opcode: LSU_3r -/* 1141 */ MCD_OPC_FilterValue, 26, 17, 0, // Skip to: 1162 -/* 1145 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 1148 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1155 -/* 1152 */ MCD_OPC_Decode, 40, 18, // Opcode: BLRF_u10 -/* 1155 */ MCD_OPC_FilterValue, 1, 62, 0, // Skip to: 1221 -/* 1159 */ MCD_OPC_Decode, 38, 19, // Opcode: BLRB_u10 -/* 1162 */ MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 1185 -/* 1166 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 1169 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1177 -/* 1173 */ MCD_OPC_Decode, 135, 1, 18, // Opcode: LDAPF_u10 -/* 1177 */ MCD_OPC_FilterValue, 1, 40, 0, // Skip to: 1221 -/* 1181 */ MCD_OPC_Decode, 132, 1, 19, // Opcode: LDAPB_u10 -/* 1185 */ MCD_OPC_FilterValue, 28, 18, 0, // Skip to: 1207 -/* 1189 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 1192 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1199 -/* 1196 */ MCD_OPC_Decode, 33, 18, // Opcode: BLACP_u10 -/* 1199 */ MCD_OPC_FilterValue, 1, 18, 0, // Skip to: 1221 -/* 1203 */ MCD_OPC_Decode, 157, 1, 18, // Opcode: LDWCP_u10 -/* 1207 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 1221 -/* 1211 */ MCD_OPC_CheckField, 10, 1, 0, 4, 0, // Skip to: 1221 -/* 1217 */ MCD_OPC_Decode, 195, 1, 12, // Opcode: SETC_ru6 -/* 1221 */ MCD_OPC_Fail, - 0 -}; + /* 0 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 129, + 0, + 0, // Skip to: 137 + /* 8 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 11 */ MCD_OPC_FilterValue, + 236, + 15, + 4, + 0, + 0, // Skip to: 21 + /* 17 */ MCD_OPC_Decode, + 207, + 3, + 0, // Opcode: WAITEU_0R + /* 21 */ MCD_OPC_FilterValue, + 237, + 15, + 4, + 0, + 0, // Skip to: 31 + /* 27 */ MCD_OPC_Decode, + 158, + 2, + 0, // Opcode: CLRE_0R + /* 31 */ MCD_OPC_FilterValue, + 238, + 15, + 4, + 0, + 0, // Skip to: 41 + /* 37 */ MCD_OPC_Decode, + 183, + 3, + 0, // Opcode: SSYNC_0r + /* 41 */ MCD_OPC_FilterValue, + 239, + 15, + 4, + 0, + 0, // Skip to: 51 + /* 47 */ MCD_OPC_Decode, + 190, + 2, + 0, // Opcode: FREET_0R + /* 51 */ MCD_OPC_FilterValue, + 252, + 15, + 4, + 0, + 0, // Skip to: 61 + /* 57 */ MCD_OPC_Decode, + 167, + 2, + 0, // Opcode: DCALL_0R + /* 61 */ MCD_OPC_FilterValue, + 253, + 15, + 4, + 0, + 0, // Skip to: 71 + /* 67 */ MCD_OPC_Decode, + 221, + 2, + 0, // Opcode: KRET_0R + /* 71 */ MCD_OPC_FilterValue, + 254, + 15, + 4, + 0, + 0, // Skip to: 81 + /* 77 */ MCD_OPC_Decode, + 173, + 2, + 0, // Opcode: DRET_0R + /* 81 */ MCD_OPC_FilterValue, + 255, + 15, + 4, + 0, + 0, // Skip to: 91 + /* 87 */ MCD_OPC_Decode, + 164, + 3, + 0, // Opcode: SETKEP_0R + /* 91 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 94 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 103 + /* 99 */ MCD_OPC_Decode, + 176, + 2, + 1, // Opcode: EDU_1r + /* 103 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 112 + /* 108 */ MCD_OPC_Decode, + 179, + 2, + 1, // Opcode: EEU_1r + /* 112 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 115 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 124 + /* 120 */ MCD_OPC_Decode, + 208, + 2, + 2, // Opcode: INITPC_2r + /* 124 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 133 + /* 129 */ MCD_OPC_Decode, + 202, + 2, + 2, // Opcode: GETST_2r + /* 133 */ MCD_OPC_Decode, + 194, + 3, + 3, // Opcode: STW_2rus + /* 137 */ MCD_OPC_FilterValue, + 1, + 129, + 0, + 0, // Skip to: 271 + /* 142 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 145 */ MCD_OPC_FilterValue, + 236, + 15, + 4, + 0, + 0, // Skip to: 155 + /* 151 */ MCD_OPC_Decode, + 247, + 2, + 0, // Opcode: LDSPC_0R + /* 155 */ MCD_OPC_FilterValue, + 237, + 15, + 4, + 0, + 0, // Skip to: 165 + /* 161 */ MCD_OPC_Decode, + 188, + 3, + 0, // Opcode: STSPC_0R + /* 165 */ MCD_OPC_FilterValue, + 238, + 15, + 4, + 0, + 0, // Skip to: 175 + /* 171 */ MCD_OPC_Decode, + 248, + 2, + 0, // Opcode: LDSSR_0R + /* 175 */ MCD_OPC_FilterValue, + 239, + 15, + 4, + 0, + 0, // Skip to: 185 + /* 181 */ MCD_OPC_Decode, + 189, + 3, + 0, // Opcode: STSSR_0R + /* 185 */ MCD_OPC_FilterValue, + 252, + 15, + 4, + 0, + 0, // Skip to: 195 + /* 191 */ MCD_OPC_Decode, + 187, + 3, + 0, // Opcode: STSED_0R + /* 195 */ MCD_OPC_FilterValue, + 253, + 15, + 4, + 0, + 0, // Skip to: 205 + /* 201 */ MCD_OPC_Decode, + 186, + 3, + 0, // Opcode: STET_0R + /* 205 */ MCD_OPC_FilterValue, + 254, + 15, + 4, + 0, + 0, // Skip to: 215 + /* 211 */ MCD_OPC_Decode, + 192, + 2, + 0, // Opcode: GETED_0R + /* 215 */ MCD_OPC_FilterValue, + 255, + 15, + 4, + 0, + 0, // Skip to: 225 + /* 221 */ MCD_OPC_Decode, + 193, + 2, + 0, // Opcode: GETET_0R + /* 225 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 228 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 237 + /* 233 */ MCD_OPC_Decode, + 206, + 3, + 1, // Opcode: WAITET_1R + /* 237 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 246 + /* 242 */ MCD_OPC_Decode, + 205, + 3, + 1, // Opcode: WAITEF_1R + /* 246 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 249 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 258 + /* 254 */ MCD_OPC_Decode, + 206, + 2, + 2, // Opcode: INITDP_2r + /* 258 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 267 + /* 263 */ MCD_OPC_Decode, + 149, + 3, + 4, // Opcode: OUTT_2r + /* 267 */ MCD_OPC_Decode, + 129, + 3, + 3, // Opcode: LDW_2rus + /* 271 */ MCD_OPC_FilterValue, + 2, + 119, + 0, + 0, // Skip to: 395 + /* 276 */ MCD_OPC_ExtractField, + 0, + 11, // Inst{10-0} ... + /* 279 */ MCD_OPC_FilterValue, + 236, + 15, + 4, + 0, + 0, // Skip to: 289 + /* 285 */ MCD_OPC_Decode, + 168, + 2, + 0, // Opcode: DENTSP_0R + /* 289 */ MCD_OPC_FilterValue, + 237, + 15, + 4, + 0, + 0, // Skip to: 299 + /* 295 */ MCD_OPC_Decode, + 172, + 2, + 0, // Opcode: DRESTSP_0R + /* 299 */ MCD_OPC_FilterValue, + 238, + 15, + 4, + 0, + 0, // Skip to: 309 + /* 305 */ MCD_OPC_Decode, + 194, + 2, + 0, // Opcode: GETID_0R + /* 309 */ MCD_OPC_FilterValue, + 239, + 15, + 4, + 0, + 0, // Skip to: 319 + /* 315 */ MCD_OPC_Decode, + 195, + 2, + 0, // Opcode: GETKEP_0R + /* 319 */ MCD_OPC_FilterValue, + 252, + 15, + 4, + 0, + 0, // Skip to: 329 + /* 325 */ MCD_OPC_Decode, + 196, + 2, + 0, // Opcode: GETKSP_0R + /* 329 */ MCD_OPC_FilterValue, + 253, + 15, + 4, + 0, + 0, // Skip to: 339 + /* 335 */ MCD_OPC_Decode, + 246, + 2, + 0, // Opcode: LDSED_0R + /* 339 */ MCD_OPC_FilterValue, + 254, + 15, + 4, + 0, + 0, // Skip to: 349 + /* 345 */ MCD_OPC_Decode, + 244, + 2, + 0, // Opcode: LDET_0R + /* 349 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 352 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 361 + /* 357 */ MCD_OPC_Decode, + 189, + 2, + 1, // Opcode: FREER_1r + /* 361 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 370 + /* 366 */ MCD_OPC_Decode, + 137, + 3, + 1, // Opcode: MJOIN_1r + /* 370 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 373 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 382 + /* 378 */ MCD_OPC_Decode, + 209, + 2, + 2, // Opcode: INITSP_2r + /* 382 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 391 + /* 387 */ MCD_OPC_Decode, + 162, + 3, + 4, // Opcode: SETD_2r + /* 391 */ MCD_OPC_Decode, + 254, + 1, + 5, // Opcode: ADD_3r + /* 395 */ MCD_OPC_FilterValue, + 3, + 46, + 0, + 0, // Skip to: 446 + /* 400 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 403 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 412 + /* 408 */ MCD_OPC_Decode, + 204, + 3, + 1, // Opcode: TSTART_1R + /* 412 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 421 + /* 417 */ MCD_OPC_Decode, + 140, + 3, + 1, // Opcode: MSYNC_1r + /* 421 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 424 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 433 + /* 429 */ MCD_OPC_Decode, + 205, + 2, + 2, // Opcode: INITCP_2r + /* 433 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 442 + /* 438 */ MCD_OPC_Decode, + 202, + 3, + 6, // Opcode: TSETMR_2r + /* 442 */ MCD_OPC_Decode, + 197, + 3, + 5, // Opcode: SUB_3r + /* 446 */ MCD_OPC_FilterValue, + 4, + 36, + 0, + 0, // Skip to: 487 + /* 451 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 454 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 463 + /* 459 */ MCD_OPC_Decode, + 137, + 2, + 1, // Opcode: BLA_1r + /* 463 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 472 + /* 468 */ MCD_OPC_Decode, + 131, + 2, + 1, // Opcode: BAU_1r + /* 472 */ MCD_OPC_CheckField, + 4, + 1, + 1, + 4, + 0, + 0, // Skip to: 483 + /* 479 */ MCD_OPC_Decode, + 178, + 2, + 2, // Opcode: EET_2r + /* 483 */ MCD_OPC_Decode, + 180, + 3, + 5, // Opcode: SHL_3r + /* 487 */ MCD_OPC_FilterValue, + 5, + 46, + 0, + 0, // Skip to: 538 + /* 492 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 495 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 504 + /* 500 */ MCD_OPC_Decode, + 154, + 2, + 1, // Opcode: BRU_1r + /* 504 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 513 + /* 509 */ MCD_OPC_Decode, + 170, + 3, + 1, // Opcode: SETSP_1r + /* 513 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 516 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 525 + /* 521 */ MCD_OPC_Decode, + 255, + 1, + 7, // Opcode: ANDNOT_2r + /* 525 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 534 + /* 530 */ MCD_OPC_Decode, + 177, + 2, + 2, // Opcode: EEF_2r + /* 534 */ MCD_OPC_Decode, + 182, + 3, + 5, // Opcode: SHR_3r + /* 538 */ MCD_OPC_FilterValue, + 6, + 46, + 0, + 0, // Skip to: 589 + /* 543 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 546 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 555 + /* 551 */ MCD_OPC_Decode, + 161, + 3, + 1, // Opcode: SETDP_1r + /* 555 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 564 + /* 560 */ MCD_OPC_Decode, + 157, + 3, + 1, // Opcode: SETCP_1r + /* 564 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 567 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 576 + /* 572 */ MCD_OPC_Decode, + 177, + 3, + 7, // Opcode: SEXT_2r + /* 576 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 585 + /* 581 */ MCD_OPC_Decode, + 178, + 3, + 8, // Opcode: SEXT_rus + /* 585 */ MCD_OPC_Decode, + 184, + 2, + 5, // Opcode: EQ_3r + /* 589 */ MCD_OPC_FilterValue, + 7, + 46, + 0, + 0, // Skip to: 640 + /* 594 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 597 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 606 + /* 602 */ MCD_OPC_Decode, + 169, + 2, + 1, // Opcode: DGETREG_1r + /* 606 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 615 + /* 611 */ MCD_OPC_Decode, + 163, + 3, + 1, // Opcode: SETEV_1r + /* 615 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 618 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 627 + /* 623 */ MCD_OPC_Decode, + 203, + 2, + 2, // Opcode: GETTS_2r + /* 627 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 636 + /* 632 */ MCD_OPC_Decode, + 168, + 3, + 4, // Opcode: SETPT_2r + /* 636 */ MCD_OPC_Decode, + 128, + 2, + 5, // Opcode: AND_3r + /* 640 */ MCD_OPC_FilterValue, + 8, + 46, + 0, + 0, // Skip to: 691 + /* 645 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 648 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 657 + /* 653 */ MCD_OPC_Decode, + 214, + 2, + 1, // Opcode: KCALL_1r + /* 657 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 666 + /* 662 */ MCD_OPC_Decode, + 176, + 3, + 1, // Opcode: SETV_1r + /* 666 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 669 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 678 + /* 674 */ MCD_OPC_Decode, + 209, + 3, + 7, // Opcode: ZEXT_2r + /* 678 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 687 + /* 683 */ MCD_OPC_Decode, + 210, + 3, + 8, // Opcode: ZEXT_rus + /* 687 */ MCD_OPC_Decode, + 144, + 3, + 5, // Opcode: OR_3r + /* 691 */ MCD_OPC_FilterValue, + 9, + 46, + 0, + 0, // Skip to: 742 + /* 696 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 699 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 708 + /* 704 */ MCD_OPC_Decode, + 174, + 2, + 1, // Opcode: ECALLF_1r + /* 708 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 717 + /* 713 */ MCD_OPC_Decode, + 175, + 2, + 1, // Opcode: ECALLT_1r + /* 717 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 720 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 729 + /* 725 */ MCD_OPC_Decode, + 145, + 3, + 2, // Opcode: OUTCT_2r + /* 729 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 738 + /* 734 */ MCD_OPC_Decode, + 146, + 3, + 9, // Opcode: OUTCT_rus + /* 738 */ MCD_OPC_Decode, + 130, + 3, + 5, // Opcode: LDW_3r + /* 742 */ MCD_OPC_FilterValue, + 10, + 21, + 0, + 0, // Skip to: 768 + /* 747 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 750 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 759 + /* 755 */ MCD_OPC_Decode, + 191, + 3, + 10, // Opcode: STWDP_ru6 + /* 759 */ MCD_OPC_FilterValue, + 1, + 154, + 2, + 0, // Skip to: 1430 + /* 764 */ MCD_OPC_Decode, + 193, + 3, + 10, // Opcode: STWSP_ru6 + /* 768 */ MCD_OPC_FilterValue, + 11, + 21, + 0, + 0, // Skip to: 794 + /* 773 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 776 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 785 + /* 781 */ MCD_OPC_Decode, + 254, + 2, + 10, // Opcode: LDWDP_ru6 + /* 785 */ MCD_OPC_FilterValue, + 1, + 128, + 2, + 0, // Skip to: 1430 + /* 790 */ MCD_OPC_Decode, + 128, + 3, + 10, // Opcode: LDWSP_ru6 + /* 794 */ MCD_OPC_FilterValue, + 12, + 21, + 0, + 0, // Skip to: 820 + /* 799 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 802 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 811 + /* 807 */ MCD_OPC_Decode, + 237, + 2, + 10, // Opcode: LDAWDP_ru6 + /* 811 */ MCD_OPC_FilterValue, + 1, + 102, + 2, + 0, // Skip to: 1430 + /* 816 */ MCD_OPC_Decode, + 241, + 2, + 10, // Opcode: LDAWSP_ru6 + /* 820 */ MCD_OPC_FilterValue, + 13, + 21, + 0, + 0, // Skip to: 846 + /* 825 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 828 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 837 + /* 833 */ MCD_OPC_Decode, + 243, + 2, + 10, // Opcode: LDC_ru6 + /* 837 */ MCD_OPC_FilterValue, + 1, + 76, + 2, + 0, // Skip to: 1430 + /* 842 */ MCD_OPC_Decode, + 251, + 2, + 10, // Opcode: LDWCP_ru6 + /* 846 */ MCD_OPC_FilterValue, + 14, + 99, + 0, + 0, // Skip to: 950 + /* 851 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 854 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 902 + /* 859 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 862 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 871 + /* 867 */ MCD_OPC_Decode, + 153, + 2, + 11, // Opcode: BRFU_u6 + /* 871 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 880 + /* 876 */ MCD_OPC_Decode, + 136, + 2, + 11, // Opcode: BLAT_u6 + /* 880 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 889 + /* 885 */ MCD_OPC_Decode, + 186, + 2, + 11, // Opcode: EXTDP_u6 + /* 889 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 898 + /* 894 */ MCD_OPC_Decode, + 216, + 2, + 11, // Opcode: KCALL_u6 + /* 898 */ MCD_OPC_Decode, + 151, + 2, + 12, // Opcode: BRFT_ru6 + /* 902 */ MCD_OPC_FilterValue, + 1, + 11, + 2, + 0, // Skip to: 1430 + /* 907 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 910 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 919 + /* 915 */ MCD_OPC_Decode, + 147, + 2, + 13, // Opcode: BRBU_u6 + /* 919 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 928 + /* 924 */ MCD_OPC_Decode, + 182, + 2, + 11, // Opcode: ENTSP_u6 + /* 928 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 937 + /* 933 */ MCD_OPC_Decode, + 188, + 2, + 11, // Opcode: EXTSP_u6 + /* 937 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 946 + /* 942 */ MCD_OPC_Decode, + 155, + 3, + 11, // Opcode: RETSP_u6 + /* 946 */ MCD_OPC_Decode, + 145, + 2, + 14, // Opcode: BRBT_ru6 + /* 950 */ MCD_OPC_FilterValue, + 15, + 81, + 0, + 0, // Skip to: 1036 + /* 955 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 958 */ MCD_OPC_FilterValue, + 0, + 43, + 0, + 0, // Skip to: 1006 + /* 963 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 966 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 975 + /* 971 */ MCD_OPC_Decode, + 163, + 2, + 11, // Opcode: CLRSR_u6 + /* 975 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 984 + /* 980 */ MCD_OPC_Decode, + 174, + 3, + 11, // Opcode: SETSR_u6 + /* 984 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 993 + /* 989 */ MCD_OPC_Decode, + 218, + 2, + 11, // Opcode: KENTSP_u6 + /* 993 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 1002 + /* 998 */ MCD_OPC_Decode, + 220, + 2, + 11, // Opcode: KRESTSP_u6 + /* 1002 */ MCD_OPC_Decode, + 149, + 2, + 12, // Opcode: BRFF_ru6 + /* 1006 */ MCD_OPC_FilterValue, + 1, + 163, + 1, + 0, // Skip to: 1430 + /* 1011 */ MCD_OPC_ExtractField, + 6, + 4, // Inst{9-6} ... + /* 1014 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 1023 + /* 1019 */ MCD_OPC_Decode, + 201, + 2, + 11, // Opcode: GETSR_u6 + /* 1023 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 1032 + /* 1028 */ MCD_OPC_Decode, + 235, + 2, + 11, // Opcode: LDAWCP_u6 + /* 1032 */ MCD_OPC_Decode, + 143, + 2, + 14, // Opcode: BRBF_ru6 + /* 1036 */ MCD_OPC_FilterValue, + 16, + 46, + 0, + 0, // Skip to: 1087 + /* 1041 */ MCD_OPC_ExtractField, + 4, + 7, // Inst{10-4} ... + /* 1044 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 1053 + /* 1049 */ MCD_OPC_Decode, + 159, + 2, + 1, // Opcode: CLRPT_1R + /* 1053 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 1062 + /* 1058 */ MCD_OPC_Decode, + 198, + 3, + 1, // Opcode: SYNCR_1r + /* 1062 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1065 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1074 + /* 1070 */ MCD_OPC_Decode, + 199, + 2, + 9, // Opcode: GETR_rus + /* 1074 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1083 + /* 1079 */ MCD_OPC_Decode, + 204, + 2, + 2, // Opcode: INCT_2r + /* 1083 */ MCD_OPC_Decode, + 223, + 2, + 5, // Opcode: LD16S_3r + /* 1087 */ MCD_OPC_FilterValue, + 17, + 25, + 0, + 0, // Skip to: 1117 + /* 1092 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1095 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1104 + /* 1100 */ MCD_OPC_Decode, + 143, + 3, + 2, // Opcode: NOT + /* 1104 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1113 + /* 1109 */ MCD_OPC_Decode, + 212, + 2, + 2, // Opcode: INT_2r + /* 1113 */ MCD_OPC_Decode, + 224, + 2, + 5, // Opcode: LD8U_3r + /* 1117 */ MCD_OPC_FilterValue, + 18, + 25, + 0, + 0, // Skip to: 1147 + /* 1122 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1125 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1134 + /* 1130 */ MCD_OPC_Decode, + 142, + 3, + 2, // Opcode: NEG + /* 1134 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1143 + /* 1139 */ MCD_OPC_Decode, + 180, + 2, + 2, // Opcode: ENDIN_2r + /* 1143 */ MCD_OPC_Decode, + 253, + 1, + 3, // Opcode: ADD_2rus + /* 1147 */ MCD_OPC_FilterValue, + 19, + 4, + 0, + 0, // Skip to: 1156 + /* 1152 */ MCD_OPC_Decode, + 196, + 3, + 3, // Opcode: SUB_2rus + /* 1156 */ MCD_OPC_FilterValue, + 20, + 25, + 0, + 0, // Skip to: 1186 + /* 1161 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1164 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1173 + /* 1169 */ MCD_OPC_Decode, + 138, + 3, + 2, // Opcode: MKMSK_2r + /* 1173 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1182 + /* 1178 */ MCD_OPC_Decode, + 139, + 3, + 15, // Opcode: MKMSK_rus + /* 1182 */ MCD_OPC_Decode, + 179, + 3, + 16, // Opcode: SHL_2rus + /* 1186 */ MCD_OPC_FilterValue, + 21, + 25, + 0, + 0, // Skip to: 1216 + /* 1191 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1194 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1203 + /* 1199 */ MCD_OPC_Decode, + 150, + 3, + 4, // Opcode: OUT_2r + /* 1203 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1212 + /* 1208 */ MCD_OPC_Decode, + 148, + 3, + 7, // Opcode: OUTSHR_2r + /* 1212 */ MCD_OPC_Decode, + 181, + 3, + 16, // Opcode: SHR_2rus + /* 1216 */ MCD_OPC_FilterValue, + 22, + 25, + 0, + 0, // Skip to: 1246 + /* 1221 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1224 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1233 + /* 1229 */ MCD_OPC_Decode, + 213, + 2, + 2, // Opcode: IN_2r + /* 1233 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1242 + /* 1238 */ MCD_OPC_Decode, + 211, + 2, + 7, // Opcode: INSHR_2r + /* 1242 */ MCD_OPC_Decode, + 183, + 2, + 3, // Opcode: EQ_2rus + /* 1246 */ MCD_OPC_FilterValue, + 23, + 25, + 0, + 0, // Skip to: 1276 + /* 1251 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1254 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1263 + /* 1259 */ MCD_OPC_Decode, + 151, + 3, + 2, // Opcode: PEEK_2r + /* 1263 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1272 + /* 1268 */ MCD_OPC_Decode, + 199, + 3, + 2, // Opcode: TESTCT_2r + /* 1272 */ MCD_OPC_Decode, + 203, + 3, + 17, // Opcode: TSETR_3r + /* 1276 */ MCD_OPC_FilterValue, + 24, + 25, + 0, + 0, // Skip to: 1306 + /* 1281 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1284 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1293 + /* 1289 */ MCD_OPC_Decode, + 166, + 3, + 4, // Opcode: SETPSC_2r + /* 1293 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1302 + /* 1298 */ MCD_OPC_Decode, + 201, + 3, + 2, // Opcode: TESTWCT_2r + /* 1302 */ MCD_OPC_Decode, + 132, + 3, + 5, // Opcode: LSS_3r + /* 1306 */ MCD_OPC_FilterValue, + 25, + 25, + 0, + 0, // Skip to: 1336 + /* 1311 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 1314 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1323 + /* 1319 */ MCD_OPC_Decode, + 156, + 2, + 2, // Opcode: CHKCT_2r + /* 1323 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 1332 + /* 1328 */ MCD_OPC_Decode, + 157, + 2, + 15, // Opcode: CHKCT_rus + /* 1332 */ MCD_OPC_Decode, + 134, + 3, + 5, // Opcode: LSU_3r + /* 1336 */ MCD_OPC_FilterValue, + 26, + 21, + 0, + 0, // Skip to: 1362 + /* 1341 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 1344 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1353 + /* 1349 */ MCD_OPC_Decode, + 141, + 2, + 18, // Opcode: BLRF_u10 + /* 1353 */ MCD_OPC_FilterValue, + 1, + 72, + 0, + 0, // Skip to: 1430 + /* 1358 */ MCD_OPC_Decode, + 139, + 2, + 19, // Opcode: BLRB_u10 + /* 1362 */ MCD_OPC_FilterValue, + 27, + 21, + 0, + 0, // Skip to: 1388 + /* 1367 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 1370 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1379 + /* 1375 */ MCD_OPC_Decode, + 231, + 2, + 18, // Opcode: LDAPF_u10 + /* 1379 */ MCD_OPC_FilterValue, + 1, + 46, + 0, + 0, // Skip to: 1430 + /* 1384 */ MCD_OPC_Decode, + 228, + 2, + 19, // Opcode: LDAPB_u10 + /* 1388 */ MCD_OPC_FilterValue, + 28, + 21, + 0, + 0, // Skip to: 1414 + /* 1393 */ MCD_OPC_ExtractField, + 10, + 1, // Inst{10} ... + /* 1396 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 1405 + /* 1401 */ MCD_OPC_Decode, + 134, + 2, + 18, // Opcode: BLACP_u10 + /* 1405 */ MCD_OPC_FilterValue, + 1, + 20, + 0, + 0, // Skip to: 1430 + /* 1410 */ MCD_OPC_Decode, + 252, + 2, + 18, // Opcode: LDWCP_u10 + /* 1414 */ MCD_OPC_FilterValue, + 29, + 11, + 0, + 0, // Skip to: 1430 + /* 1419 */ MCD_OPC_CheckField, + 10, + 1, + 0, + 4, + 0, + 0, // Skip to: 1430 + /* 1426 */ MCD_OPC_Decode, + 160, + 3, + 12, // Opcode: SETC_ru6 + /* 1430 */ MCD_OPC_Fail, + 0}; static const uint8_t DecoderTable32[] = { -/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... -/* 3 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 96 -/* 7 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... -/* 10 */ MCD_OPC_FilterValue, 31, 216, 3, // Skip to: 998 -/* 14 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 17 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 31 -/* 21 */ MCD_OPC_CheckField, 16, 11, 236, 15, 17, 0, // Skip to: 45 -/* 28 */ MCD_OPC_Decode, 31, 20, // Opcode: BITREV_l2r -/* 31 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 45 -/* 35 */ MCD_OPC_CheckField, 16, 11, 236, 15, 3, 0, // Skip to: 45 -/* 42 */ MCD_OPC_Decode, 56, 20, // Opcode: BYTEREV_l2r -/* 45 */ MCD_OPC_CheckField, 16, 11, 236, 15, 4, 0, // Skip to: 56 -/* 52 */ MCD_OPC_Decode, 231, 1, 21, // Opcode: STW_l3r -/* 56 */ MCD_OPC_ExtractField, 20, 7, // Inst{26-20} ... -/* 59 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 66 -/* 63 */ MCD_OPC_Decode, 66, 22, // Opcode: CRC8_l4r -/* 66 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 74 -/* 70 */ MCD_OPC_Decode, 170, 1, 23, // Opcode: MACCU_l4r -/* 74 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 77 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 85 -/* 81 */ MCD_OPC_Decode, 150, 1, 24, // Opcode: LDIVU_l5r -/* 85 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 92 -/* 89 */ MCD_OPC_Decode, 126, 24, // Opcode: LADD_l5r -/* 92 */ MCD_OPC_Decode, 165, 1, 25, // Opcode: LMUL_l6r -/* 96 */ MCD_OPC_FilterValue, 1, 86, 0, // Skip to: 186 -/* 100 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... -/* 103 */ MCD_OPC_FilterValue, 31, 123, 3, // Skip to: 998 -/* 107 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 110 */ MCD_OPC_FilterValue, 0, 116, 3, // Skip to: 998 -/* 114 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 117 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 136 -/* 121 */ MCD_OPC_CheckField, 21, 6, 63, 29, 0, // Skip to: 156 -/* 127 */ MCD_OPC_CheckField, 16, 4, 12, 23, 0, // Skip to: 156 -/* 133 */ MCD_OPC_Decode, 65, 20, // Opcode: CLZ_l2r -/* 136 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 156 -/* 140 */ MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 156 -/* 146 */ MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 156 -/* 152 */ MCD_OPC_Decode, 191, 1, 26, // Opcode: SETCLK_l2r -/* 156 */ MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 172 -/* 162 */ MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 172 -/* 168 */ MCD_OPC_Decode, 244, 1, 21, // Opcode: XOR_l3r -/* 172 */ MCD_OPC_CheckField, 21, 6, 63, 4, 0, // Skip to: 182 -/* 178 */ MCD_OPC_Decode, 169, 1, 23, // Opcode: MACCS_l4r -/* 182 */ MCD_OPC_Decode, 167, 1, 24, // Opcode: LSUB_l5r -/* 186 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 219 -/* 190 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... -/* 193 */ MCD_OPC_FilterValue, 159, 251, 3, 31, 3, // Skip to: 998 -/* 199 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 202 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 209 -/* 206 */ MCD_OPC_Decode, 110, 20, // Opcode: INITLR_l2r -/* 209 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 216 -/* 213 */ MCD_OPC_Decode, 101, 20, // Opcode: GETPS_l2r -/* 216 */ MCD_OPC_Decode, 29, 21, // Opcode: ASHR_l3r -/* 219 */ MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 254 -/* 223 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... -/* 226 */ MCD_OPC_FilterValue, 159, 251, 3, 254, 2, // Skip to: 998 -/* 232 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 235 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 243 -/* 239 */ MCD_OPC_Decode, 202, 1, 26, // Opcode: SETPS_l2r -/* 243 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 250 -/* 247 */ MCD_OPC_Decode, 94, 20, // Opcode: GETD_l2r -/* 250 */ MCD_OPC_Decode, 144, 1, 21, // Opcode: LDAWF_l3r -/* 254 */ MCD_OPC_FilterValue, 4, 32, 0, // Skip to: 290 -/* 258 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... -/* 261 */ MCD_OPC_FilterValue, 159, 251, 3, 219, 2, // Skip to: 998 -/* 267 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 270 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 278 -/* 274 */ MCD_OPC_Decode, 236, 1, 20, // Opcode: TESTLCL_l2r -/* 278 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 286 -/* 282 */ MCD_OPC_Decode, 210, 1, 26, // Opcode: SETTW_l2r -/* 286 */ MCD_OPC_Decode, 137, 1, 21, // Opcode: LDAWB_l3r -/* 290 */ MCD_OPC_FilterValue, 5, 32, 0, // Skip to: 326 -/* 294 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... -/* 297 */ MCD_OPC_FilterValue, 159, 251, 3, 183, 2, // Skip to: 998 -/* 303 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 306 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 314 -/* 310 */ MCD_OPC_Decode, 204, 1, 26, // Opcode: SETRDY_l2r -/* 314 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 322 -/* 318 */ MCD_OPC_Decode, 193, 1, 20, // Opcode: SETC_l2r -/* 322 */ MCD_OPC_Decode, 130, 1, 21, // Opcode: LDA16F_l3r -/* 326 */ MCD_OPC_FilterValue, 6, 31, 0, // Skip to: 361 -/* 330 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... -/* 333 */ MCD_OPC_FilterValue, 159, 251, 3, 147, 2, // Skip to: 998 -/* 339 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 342 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 350 -/* 346 */ MCD_OPC_Decode, 200, 1, 26, // Opcode: SETN_l2r -/* 350 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 357 -/* 354 */ MCD_OPC_Decode, 100, 20, // Opcode: GETN_l2r -/* 357 */ MCD_OPC_Decode, 129, 1, 21, // Opcode: LDA16B_l3r -/* 361 */ MCD_OPC_FilterValue, 7, 12, 0, // Skip to: 377 -/* 365 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 113, 2, // Skip to: 998 -/* 373 */ MCD_OPC_Decode, 175, 1, 21, // Opcode: MUL_l3r -/* 377 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 392 -/* 381 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 97, 2, // Skip to: 998 -/* 389 */ MCD_OPC_Decode, 71, 21, // Opcode: DIVS_l3r -/* 392 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 407 -/* 396 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 82, 2, // Skip to: 998 -/* 404 */ MCD_OPC_Decode, 72, 21, // Opcode: DIVU_l3r -/* 407 */ MCD_OPC_FilterValue, 10, 31, 0, // Skip to: 442 -/* 411 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 414 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 428 -/* 418 */ MCD_OPC_CheckField, 10, 6, 60, 62, 2, // Skip to: 998 -/* 424 */ MCD_OPC_Decode, 225, 1, 27, // Opcode: STWDP_lru6 -/* 428 */ MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 998 -/* 432 */ MCD_OPC_CheckField, 10, 6, 60, 48, 2, // Skip to: 998 -/* 438 */ MCD_OPC_Decode, 228, 1, 27, // Opcode: STWSP_lru6 -/* 442 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 477 -/* 446 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 449 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 463 -/* 453 */ MCD_OPC_CheckField, 10, 6, 60, 27, 2, // Skip to: 998 -/* 459 */ MCD_OPC_Decode, 158, 1, 27, // Opcode: LDWDP_lru6 -/* 463 */ MCD_OPC_FilterValue, 1, 19, 2, // Skip to: 998 -/* 467 */ MCD_OPC_CheckField, 10, 6, 60, 13, 2, // Skip to: 998 -/* 473 */ MCD_OPC_Decode, 161, 1, 27, // Opcode: LDWSP_lru6 -/* 477 */ MCD_OPC_FilterValue, 12, 31, 0, // Skip to: 512 -/* 481 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 498 -/* 488 */ MCD_OPC_CheckField, 10, 6, 60, 248, 1, // Skip to: 998 -/* 494 */ MCD_OPC_Decode, 140, 1, 27, // Opcode: LDAWDP_lru6 -/* 498 */ MCD_OPC_FilterValue, 1, 240, 1, // Skip to: 998 -/* 502 */ MCD_OPC_CheckField, 10, 6, 60, 234, 1, // Skip to: 998 -/* 508 */ MCD_OPC_Decode, 145, 1, 27, // Opcode: LDAWSP_lru6 -/* 512 */ MCD_OPC_FilterValue, 13, 31, 0, // Skip to: 547 -/* 516 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 519 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 533 -/* 523 */ MCD_OPC_CheckField, 10, 6, 60, 213, 1, // Skip to: 998 -/* 529 */ MCD_OPC_Decode, 147, 1, 27, // Opcode: LDC_lru6 -/* 533 */ MCD_OPC_FilterValue, 1, 205, 1, // Skip to: 998 -/* 537 */ MCD_OPC_CheckField, 10, 6, 60, 199, 1, // Skip to: 998 -/* 543 */ MCD_OPC_Decode, 154, 1, 27, // Opcode: LDWCP_lru6 -/* 547 */ MCD_OPC_FilterValue, 14, 94, 0, // Skip to: 645 -/* 551 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 554 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 599 -/* 558 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 561 */ MCD_OPC_FilterValue, 60, 177, 1, // Skip to: 998 -/* 565 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 568 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 575 -/* 572 */ MCD_OPC_Decode, 51, 28, // Opcode: BRFU_lu6 -/* 575 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 582 -/* 579 */ MCD_OPC_Decode, 34, 28, // Opcode: BLAT_lu6 -/* 582 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 589 -/* 586 */ MCD_OPC_Decode, 87, 28, // Opcode: EXTDP_lu6 -/* 589 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 596 -/* 593 */ MCD_OPC_Decode, 119, 28, // Opcode: KCALL_lu6 -/* 596 */ MCD_OPC_Decode, 49, 29, // Opcode: BRFT_lru6 -/* 599 */ MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 998 -/* 603 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 606 */ MCD_OPC_FilterValue, 60, 132, 1, // Skip to: 998 -/* 610 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 613 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 620 -/* 617 */ MCD_OPC_Decode, 45, 30, // Opcode: BRBU_lu6 -/* 620 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 627 -/* 624 */ MCD_OPC_Decode, 83, 28, // Opcode: ENTSP_lu6 -/* 627 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 634 -/* 631 */ MCD_OPC_Decode, 89, 28, // Opcode: EXTSP_lu6 -/* 634 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 642 -/* 638 */ MCD_OPC_Decode, 188, 1, 28, // Opcode: RETSP_lu6 -/* 642 */ MCD_OPC_Decode, 43, 31, // Opcode: BRBT_lru6 -/* 645 */ MCD_OPC_FilterValue, 15, 81, 0, // Skip to: 730 -/* 649 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 652 */ MCD_OPC_FilterValue, 0, 42, 0, // Skip to: 698 -/* 656 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 659 */ MCD_OPC_FilterValue, 60, 79, 1, // Skip to: 998 -/* 663 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 666 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 673 -/* 670 */ MCD_OPC_Decode, 63, 28, // Opcode: CLRSR_lu6 -/* 673 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 681 -/* 677 */ MCD_OPC_Decode, 208, 1, 28, // Opcode: SETSR_lu6 -/* 681 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 688 -/* 685 */ MCD_OPC_Decode, 121, 28, // Opcode: KENTSP_lu6 -/* 688 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 695 -/* 692 */ MCD_OPC_Decode, 123, 28, // Opcode: KRESTSP_lu6 -/* 695 */ MCD_OPC_Decode, 47, 29, // Opcode: BRFF_lru6 -/* 698 */ MCD_OPC_FilterValue, 1, 40, 1, // Skip to: 998 -/* 702 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 705 */ MCD_OPC_FilterValue, 60, 33, 1, // Skip to: 998 -/* 709 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 712 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 719 -/* 716 */ MCD_OPC_Decode, 103, 28, // Opcode: GETSR_lu6 -/* 719 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 727 -/* 723 */ MCD_OPC_Decode, 138, 1, 28, // Opcode: LDAWCP_lu6 -/* 727 */ MCD_OPC_Decode, 41, 31, // Opcode: BRBF_lru6 -/* 730 */ MCD_OPC_FilterValue, 16, 12, 0, // Skip to: 746 -/* 734 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 0, 1, // Skip to: 998 -/* 742 */ MCD_OPC_Decode, 219, 1, 21, // Opcode: ST16_l3r -/* 746 */ MCD_OPC_FilterValue, 17, 12, 0, // Skip to: 762 -/* 750 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 240, 0, // Skip to: 998 -/* 758 */ MCD_OPC_Decode, 220, 1, 21, // Opcode: ST8_l3r -/* 762 */ MCD_OPC_FilterValue, 18, 31, 0, // Skip to: 797 -/* 766 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... -/* 769 */ MCD_OPC_FilterValue, 159, 251, 3, 3, 0, // Skip to: 778 -/* 775 */ MCD_OPC_Decode, 28, 32, // Opcode: ASHR_l2rus -/* 778 */ MCD_OPC_FilterValue, 191, 251, 3, 4, 0, // Skip to: 788 -/* 784 */ MCD_OPC_Decode, 181, 1, 32, // Opcode: OUTPW_l2rus -/* 788 */ MCD_OPC_FilterValue, 223, 251, 3, 204, 0, // Skip to: 998 -/* 794 */ MCD_OPC_Decode, 113, 32, // Opcode: INPW_l2rus -/* 797 */ MCD_OPC_FilterValue, 19, 12, 0, // Skip to: 813 -/* 801 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 189, 0, // Skip to: 998 -/* 809 */ MCD_OPC_Decode, 143, 1, 33, // Opcode: LDAWF_l2rus -/* 813 */ MCD_OPC_FilterValue, 20, 12, 0, // Skip to: 829 -/* 817 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 173, 0, // Skip to: 998 -/* 825 */ MCD_OPC_Decode, 136, 1, 33, // Opcode: LDAWB_l2rus -/* 829 */ MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 844 -/* 833 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 157, 0, // Skip to: 998 -/* 841 */ MCD_OPC_Decode, 67, 34, // Opcode: CRC_l3r -/* 844 */ MCD_OPC_FilterValue, 24, 12, 0, // Skip to: 860 -/* 848 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 142, 0, // Skip to: 998 -/* 856 */ MCD_OPC_Decode, 186, 1, 21, // Opcode: REMS_l3r -/* 860 */ MCD_OPC_FilterValue, 25, 12, 0, // Skip to: 876 -/* 864 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 126, 0, // Skip to: 998 -/* 872 */ MCD_OPC_Decode, 187, 1, 21, // Opcode: REMU_l3r -/* 876 */ MCD_OPC_FilterValue, 26, 29, 0, // Skip to: 909 -/* 880 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 883 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 896 -/* 887 */ MCD_OPC_CheckField, 10, 6, 60, 105, 0, // Skip to: 998 -/* 893 */ MCD_OPC_Decode, 39, 35, // Opcode: BLRF_lu10 -/* 896 */ MCD_OPC_FilterValue, 1, 98, 0, // Skip to: 998 -/* 900 */ MCD_OPC_CheckField, 10, 6, 60, 92, 0, // Skip to: 998 -/* 906 */ MCD_OPC_Decode, 37, 36, // Opcode: BLRB_lu10 -/* 909 */ MCD_OPC_FilterValue, 27, 31, 0, // Skip to: 944 -/* 913 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 916 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 930 -/* 920 */ MCD_OPC_CheckField, 10, 6, 60, 72, 0, // Skip to: 998 -/* 926 */ MCD_OPC_Decode, 133, 1, 35, // Opcode: LDAPF_lu10 -/* 930 */ MCD_OPC_FilterValue, 1, 64, 0, // Skip to: 998 -/* 934 */ MCD_OPC_CheckField, 10, 6, 60, 58, 0, // Skip to: 998 -/* 940 */ MCD_OPC_Decode, 131, 1, 36, // Opcode: LDAPB_lu10 -/* 944 */ MCD_OPC_FilterValue, 28, 30, 0, // Skip to: 978 -/* 948 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... -/* 951 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 964 -/* 955 */ MCD_OPC_CheckField, 10, 6, 60, 37, 0, // Skip to: 998 -/* 961 */ MCD_OPC_Decode, 32, 35, // Opcode: BLACP_lu10 -/* 964 */ MCD_OPC_FilterValue, 1, 30, 0, // Skip to: 998 -/* 968 */ MCD_OPC_CheckField, 10, 6, 60, 24, 0, // Skip to: 998 -/* 974 */ MCD_OPC_Decode, 155, 1, 35, // Opcode: LDWCP_lu10 -/* 978 */ MCD_OPC_FilterValue, 29, 16, 0, // Skip to: 998 -/* 982 */ MCD_OPC_CheckField, 26, 1, 0, 10, 0, // Skip to: 998 -/* 988 */ MCD_OPC_CheckField, 10, 6, 60, 4, 0, // Skip to: 998 -/* 994 */ MCD_OPC_Decode, 194, 1, 29, // Opcode: SETC_lru6 -/* 998 */ MCD_OPC_Fail, - 0 -}; - -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ - return true; //llvm_unreachable("Invalid index!"); + /* 0 */ MCD_OPC_ExtractField, + 27, + 5, // Inst{31-27} ... + /* 3 */ MCD_OPC_FilterValue, + 0, + 103, + 0, + 0, // Skip to: 111 + /* 8 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 11 */ MCD_OPC_FilterValue, + 31, + 120, + 4, + 0, // Skip to: 1160 + /* 16 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 19 */ MCD_OPC_FilterValue, + 0, + 12, + 0, + 0, // Skip to: 36 + /* 24 */ MCD_OPC_CheckField, + 16, + 11, + 236, + 15, + 21, + 0, + 0, // Skip to: 53 + /* 32 */ MCD_OPC_Decode, + 132, + 2, + 20, // Opcode: BITREV_l2r + /* 36 */ MCD_OPC_FilterValue, + 1, + 12, + 0, + 0, // Skip to: 53 + /* 41 */ MCD_OPC_CheckField, + 16, + 11, + 236, + 15, + 4, + 0, + 0, // Skip to: 53 + /* 49 */ MCD_OPC_Decode, + 155, + 2, + 20, // Opcode: BYTEREV_l2r + /* 53 */ MCD_OPC_CheckField, + 16, + 11, + 236, + 15, + 4, + 0, + 0, // Skip to: 65 + /* 61 */ MCD_OPC_Decode, + 195, + 3, + 21, // Opcode: STW_l3r + /* 65 */ MCD_OPC_ExtractField, + 20, + 7, // Inst{26-20} ... + /* 68 */ MCD_OPC_FilterValue, + 126, + 4, + 0, + 0, // Skip to: 77 + /* 73 */ MCD_OPC_Decode, + 165, + 2, + 22, // Opcode: CRC8_l4r + /* 77 */ MCD_OPC_FilterValue, + 127, + 4, + 0, + 0, // Skip to: 86 + /* 82 */ MCD_OPC_Decode, + 136, + 3, + 23, // Opcode: MACCU_l4r + /* 86 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 89 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 98 + /* 94 */ MCD_OPC_Decode, + 245, + 2, + 24, // Opcode: LDIVU_l5r + /* 98 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 107 + /* 103 */ MCD_OPC_Decode, + 222, + 2, + 24, // Opcode: LADD_l5r + /* 107 */ MCD_OPC_Decode, + 131, + 3, + 25, // Opcode: LMUL_l6r + /* 111 */ MCD_OPC_FilterValue, + 1, + 98, + 0, + 0, // Skip to: 214 + /* 116 */ MCD_OPC_ExtractField, + 11, + 5, // Inst{15-11} ... + /* 119 */ MCD_OPC_FilterValue, + 31, + 12, + 4, + 0, // Skip to: 1160 + /* 124 */ MCD_OPC_ExtractField, + 20, + 1, // Inst{20} ... + /* 127 */ MCD_OPC_FilterValue, + 0, + 4, + 4, + 0, // Skip to: 1160 + /* 132 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 135 */ MCD_OPC_FilterValue, + 0, + 18, + 0, + 0, // Skip to: 158 + /* 140 */ MCD_OPC_CheckField, + 21, + 6, + 63, + 34, + 0, + 0, // Skip to: 181 + /* 147 */ MCD_OPC_CheckField, + 16, + 4, + 12, + 27, + 0, + 0, // Skip to: 181 + /* 154 */ MCD_OPC_Decode, + 164, + 2, + 20, // Opcode: CLZ_l2r + /* 158 */ MCD_OPC_FilterValue, + 1, + 18, + 0, + 0, // Skip to: 181 + /* 163 */ MCD_OPC_CheckField, + 21, + 6, + 63, + 11, + 0, + 0, // Skip to: 181 + /* 170 */ MCD_OPC_CheckField, + 16, + 4, + 12, + 4, + 0, + 0, // Skip to: 181 + /* 177 */ MCD_OPC_Decode, + 156, + 3, + 26, // Opcode: SETCLK_l2r + /* 181 */ MCD_OPC_CheckField, + 21, + 6, + 63, + 11, + 0, + 0, // Skip to: 199 + /* 188 */ MCD_OPC_CheckField, + 16, + 4, + 12, + 4, + 0, + 0, // Skip to: 199 + /* 195 */ MCD_OPC_Decode, + 208, + 3, + 21, // Opcode: XOR_l3r + /* 199 */ MCD_OPC_CheckField, + 21, + 6, + 63, + 4, + 0, + 0, // Skip to: 210 + /* 206 */ MCD_OPC_Decode, + 135, + 3, + 23, // Opcode: MACCS_l4r + /* 210 */ MCD_OPC_Decode, + 133, + 3, + 24, // Opcode: LSUB_l5r + /* 214 */ MCD_OPC_FilterValue, + 2, + 35, + 0, + 0, // Skip to: 254 + /* 219 */ MCD_OPC_ExtractField, + 11, + 16, // Inst{26-11} ... + /* 222 */ MCD_OPC_FilterValue, + 159, + 251, + 3, + 163, + 3, + 0, // Skip to: 1160 + /* 229 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 232 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 241 + /* 237 */ MCD_OPC_Decode, + 207, + 2, + 20, // Opcode: INITLR_l2r + /* 241 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 250 + /* 246 */ MCD_OPC_Decode, + 198, + 2, + 20, // Opcode: GETPS_l2r + /* 250 */ MCD_OPC_Decode, + 130, + 2, + 21, // Opcode: ASHR_l3r + /* 254 */ MCD_OPC_FilterValue, + 3, + 35, + 0, + 0, // Skip to: 294 + /* 259 */ MCD_OPC_ExtractField, + 11, + 16, // Inst{26-11} ... + /* 262 */ MCD_OPC_FilterValue, + 159, + 251, + 3, + 123, + 3, + 0, // Skip to: 1160 + /* 269 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 272 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 281 + /* 277 */ MCD_OPC_Decode, + 167, + 3, + 26, // Opcode: SETPS_l2r + /* 281 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 290 + /* 286 */ MCD_OPC_Decode, + 191, + 2, + 20, // Opcode: GETD_l2r + /* 290 */ MCD_OPC_Decode, + 239, + 2, + 21, // Opcode: LDAWF_l3r + /* 294 */ MCD_OPC_FilterValue, + 4, + 35, + 0, + 0, // Skip to: 334 + /* 299 */ MCD_OPC_ExtractField, + 11, + 16, // Inst{26-11} ... + /* 302 */ MCD_OPC_FilterValue, + 159, + 251, + 3, + 83, + 3, + 0, // Skip to: 1160 + /* 309 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 312 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 321 + /* 317 */ MCD_OPC_Decode, + 200, + 3, + 20, // Opcode: TESTLCL_l2r + /* 321 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 330 + /* 326 */ MCD_OPC_Decode, + 175, + 3, + 26, // Opcode: SETTW_l2r + /* 330 */ MCD_OPC_Decode, + 233, + 2, + 21, // Opcode: LDAWB_l3r + /* 334 */ MCD_OPC_FilterValue, + 5, + 35, + 0, + 0, // Skip to: 374 + /* 339 */ MCD_OPC_ExtractField, + 11, + 16, // Inst{26-11} ... + /* 342 */ MCD_OPC_FilterValue, + 159, + 251, + 3, + 43, + 3, + 0, // Skip to: 1160 + /* 349 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 352 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 361 + /* 357 */ MCD_OPC_Decode, + 169, + 3, + 26, // Opcode: SETRDY_l2r + /* 361 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 370 + /* 366 */ MCD_OPC_Decode, + 158, + 3, + 20, // Opcode: SETC_l2r + /* 370 */ MCD_OPC_Decode, + 226, + 2, + 21, // Opcode: LDA16F_l3r + /* 374 */ MCD_OPC_FilterValue, + 6, + 35, + 0, + 0, // Skip to: 414 + /* 379 */ MCD_OPC_ExtractField, + 11, + 16, // Inst{26-11} ... + /* 382 */ MCD_OPC_FilterValue, + 159, + 251, + 3, + 3, + 3, + 0, // Skip to: 1160 + /* 389 */ MCD_OPC_ExtractField, + 4, + 1, // Inst{4} ... + /* 392 */ MCD_OPC_FilterValue, + 0, + 4, + 0, + 0, // Skip to: 401 + /* 397 */ MCD_OPC_Decode, + 165, + 3, + 26, // Opcode: SETN_l2r + /* 401 */ MCD_OPC_FilterValue, + 1, + 4, + 0, + 0, // Skip to: 410 + /* 406 */ MCD_OPC_Decode, + 197, + 2, + 20, // Opcode: GETN_l2r + /* 410 */ MCD_OPC_Decode, + 225, + 2, + 21, // Opcode: LDA16B_l3r + /* 414 */ MCD_OPC_FilterValue, + 7, + 13, + 0, + 0, // Skip to: 432 + /* 419 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 220, + 2, + 0, // Skip to: 1160 + /* 428 */ MCD_OPC_Decode, + 141, + 3, + 21, // Opcode: MUL_l3r + /* 432 */ MCD_OPC_FilterValue, + 8, + 13, + 0, + 0, // Skip to: 450 + /* 437 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 202, + 2, + 0, // Skip to: 1160 + /* 446 */ MCD_OPC_Decode, + 170, + 2, + 21, // Opcode: DIVS_l3r + /* 450 */ MCD_OPC_FilterValue, + 9, + 13, + 0, + 0, // Skip to: 468 + /* 455 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 184, + 2, + 0, // Skip to: 1160 + /* 464 */ MCD_OPC_Decode, + 171, + 2, + 21, // Opcode: DIVU_l3r + /* 468 */ MCD_OPC_FilterValue, + 10, + 35, + 0, + 0, // Skip to: 508 + /* 473 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 476 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 492 + /* 481 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 160, + 2, + 0, // Skip to: 1160 + /* 488 */ MCD_OPC_Decode, + 190, + 3, + 27, // Opcode: STWDP_lru6 + /* 492 */ MCD_OPC_FilterValue, + 1, + 151, + 2, + 0, // Skip to: 1160 + /* 497 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 144, + 2, + 0, // Skip to: 1160 + /* 504 */ MCD_OPC_Decode, + 192, + 3, + 27, // Opcode: STWSP_lru6 + /* 508 */ MCD_OPC_FilterValue, + 11, + 35, + 0, + 0, // Skip to: 548 + /* 513 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 516 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 532 + /* 521 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 120, + 2, + 0, // Skip to: 1160 + /* 528 */ MCD_OPC_Decode, + 253, + 2, + 27, // Opcode: LDWDP_lru6 + /* 532 */ MCD_OPC_FilterValue, + 1, + 111, + 2, + 0, // Skip to: 1160 + /* 537 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 104, + 2, + 0, // Skip to: 1160 + /* 544 */ MCD_OPC_Decode, + 255, + 2, + 27, // Opcode: LDWSP_lru6 + /* 548 */ MCD_OPC_FilterValue, + 12, + 35, + 0, + 0, // Skip to: 588 + /* 553 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 556 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 572 + /* 561 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 80, + 2, + 0, // Skip to: 1160 + /* 568 */ MCD_OPC_Decode, + 236, + 2, + 27, // Opcode: LDAWDP_lru6 + /* 572 */ MCD_OPC_FilterValue, + 1, + 71, + 2, + 0, // Skip to: 1160 + /* 577 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 64, + 2, + 0, // Skip to: 1160 + /* 584 */ MCD_OPC_Decode, + 240, + 2, + 27, // Opcode: LDAWSP_lru6 + /* 588 */ MCD_OPC_FilterValue, + 13, + 35, + 0, + 0, // Skip to: 628 + /* 593 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 596 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 612 + /* 601 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 40, + 2, + 0, // Skip to: 1160 + /* 608 */ MCD_OPC_Decode, + 242, + 2, + 27, // Opcode: LDC_lru6 + /* 612 */ MCD_OPC_FilterValue, + 1, + 31, + 2, + 0, // Skip to: 1160 + /* 617 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 24, + 2, + 0, // Skip to: 1160 + /* 624 */ MCD_OPC_Decode, + 249, + 2, + 27, // Opcode: LDWCP_lru6 + /* 628 */ MCD_OPC_FilterValue, + 14, + 115, + 0, + 0, // Skip to: 748 + /* 633 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 636 */ MCD_OPC_FilterValue, + 0, + 51, + 0, + 0, // Skip to: 692 + /* 641 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 644 */ MCD_OPC_FilterValue, + 60, + 255, + 1, + 0, // Skip to: 1160 + /* 649 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 652 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 661 + /* 657 */ MCD_OPC_Decode, + 152, + 2, + 28, // Opcode: BRFU_lu6 + /* 661 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 670 + /* 666 */ MCD_OPC_Decode, + 135, + 2, + 28, // Opcode: BLAT_lu6 + /* 670 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 679 + /* 675 */ MCD_OPC_Decode, + 185, + 2, + 28, // Opcode: EXTDP_lu6 + /* 679 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 688 + /* 684 */ MCD_OPC_Decode, + 215, + 2, + 28, // Opcode: KCALL_lu6 + /* 688 */ MCD_OPC_Decode, + 150, + 2, + 29, // Opcode: BRFT_lru6 + /* 692 */ MCD_OPC_FilterValue, + 1, + 207, + 1, + 0, // Skip to: 1160 + /* 697 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 700 */ MCD_OPC_FilterValue, + 60, + 199, + 1, + 0, // Skip to: 1160 + /* 705 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 708 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 717 + /* 713 */ MCD_OPC_Decode, + 146, + 2, + 30, // Opcode: BRBU_lu6 + /* 717 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 726 + /* 722 */ MCD_OPC_Decode, + 181, + 2, + 28, // Opcode: ENTSP_lu6 + /* 726 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 735 + /* 731 */ MCD_OPC_Decode, + 187, + 2, + 28, // Opcode: EXTSP_lu6 + /* 735 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 744 + /* 740 */ MCD_OPC_Decode, + 154, + 3, + 28, // Opcode: RETSP_lu6 + /* 744 */ MCD_OPC_Decode, + 144, + 2, + 31, // Opcode: BRBT_lru6 + /* 748 */ MCD_OPC_FilterValue, + 15, + 97, + 0, + 0, // Skip to: 850 + /* 753 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 756 */ MCD_OPC_FilterValue, + 0, + 51, + 0, + 0, // Skip to: 812 + /* 761 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 764 */ MCD_OPC_FilterValue, + 60, + 135, + 1, + 0, // Skip to: 1160 + /* 769 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 772 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 781 + /* 777 */ MCD_OPC_Decode, + 162, + 2, + 28, // Opcode: CLRSR_lu6 + /* 781 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 790 + /* 786 */ MCD_OPC_Decode, + 173, + 3, + 28, // Opcode: SETSR_lu6 + /* 790 */ MCD_OPC_FilterValue, + 14, + 4, + 0, + 0, // Skip to: 799 + /* 795 */ MCD_OPC_Decode, + 217, + 2, + 28, // Opcode: KENTSP_lu6 + /* 799 */ MCD_OPC_FilterValue, + 15, + 4, + 0, + 0, // Skip to: 808 + /* 804 */ MCD_OPC_Decode, + 219, + 2, + 28, // Opcode: KRESTSP_lu6 + /* 808 */ MCD_OPC_Decode, + 148, + 2, + 29, // Opcode: BRFF_lru6 + /* 812 */ MCD_OPC_FilterValue, + 1, + 87, + 1, + 0, // Skip to: 1160 + /* 817 */ MCD_OPC_ExtractField, + 10, + 6, // Inst{15-10} ... + /* 820 */ MCD_OPC_FilterValue, + 60, + 79, + 1, + 0, // Skip to: 1160 + /* 825 */ MCD_OPC_ExtractField, + 22, + 4, // Inst{25-22} ... + /* 828 */ MCD_OPC_FilterValue, + 12, + 4, + 0, + 0, // Skip to: 837 + /* 833 */ MCD_OPC_Decode, + 200, + 2, + 28, // Opcode: GETSR_lu6 + /* 837 */ MCD_OPC_FilterValue, + 13, + 4, + 0, + 0, // Skip to: 846 + /* 842 */ MCD_OPC_Decode, + 234, + 2, + 28, // Opcode: LDAWCP_lu6 + /* 846 */ MCD_OPC_Decode, + 142, + 2, + 31, // Opcode: BRBF_lru6 + /* 850 */ MCD_OPC_FilterValue, + 16, + 13, + 0, + 0, // Skip to: 868 + /* 855 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 40, + 1, + 0, // Skip to: 1160 + /* 864 */ MCD_OPC_Decode, + 184, + 3, + 21, // Opcode: ST16_l3r + /* 868 */ MCD_OPC_FilterValue, + 17, + 13, + 0, + 0, // Skip to: 886 + /* 873 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 22, + 1, + 0, // Skip to: 1160 + /* 882 */ MCD_OPC_Decode, + 185, + 3, + 21, // Opcode: ST8_l3r + /* 886 */ MCD_OPC_FilterValue, + 18, + 36, + 0, + 0, // Skip to: 927 + /* 891 */ MCD_OPC_ExtractField, + 11, + 16, // Inst{26-11} ... + /* 894 */ MCD_OPC_FilterValue, + 159, + 251, + 3, + 4, + 0, + 0, // Skip to: 905 + /* 901 */ MCD_OPC_Decode, + 129, + 2, + 32, // Opcode: ASHR_l2rus + /* 905 */ MCD_OPC_FilterValue, + 191, + 251, + 3, + 4, + 0, + 0, // Skip to: 916 + /* 912 */ MCD_OPC_Decode, + 147, + 3, + 32, // Opcode: OUTPW_l2rus + /* 916 */ MCD_OPC_FilterValue, + 223, + 251, + 3, + 237, + 0, + 0, // Skip to: 1160 + /* 923 */ MCD_OPC_Decode, + 210, + 2, + 32, // Opcode: INPW_l2rus + /* 927 */ MCD_OPC_FilterValue, + 19, + 13, + 0, + 0, // Skip to: 945 + /* 932 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 219, + 0, + 0, // Skip to: 1160 + /* 941 */ MCD_OPC_Decode, + 238, + 2, + 33, // Opcode: LDAWF_l2rus + /* 945 */ MCD_OPC_FilterValue, + 20, + 13, + 0, + 0, // Skip to: 963 + /* 950 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 201, + 0, + 0, // Skip to: 1160 + /* 959 */ MCD_OPC_Decode, + 232, + 2, + 33, // Opcode: LDAWB_l2rus + /* 963 */ MCD_OPC_FilterValue, + 21, + 13, + 0, + 0, // Skip to: 981 + /* 968 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 183, + 0, + 0, // Skip to: 1160 + /* 977 */ MCD_OPC_Decode, + 166, + 2, + 34, // Opcode: CRC_l3r + /* 981 */ MCD_OPC_FilterValue, + 24, + 13, + 0, + 0, // Skip to: 999 + /* 986 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 165, + 0, + 0, // Skip to: 1160 + /* 995 */ MCD_OPC_Decode, + 152, + 3, + 21, // Opcode: REMS_l3r + /* 999 */ MCD_OPC_FilterValue, + 25, + 13, + 0, + 0, // Skip to: 1017 + /* 1004 */ MCD_OPC_CheckField, + 11, + 16, + 159, + 251, + 3, + 147, + 0, + 0, // Skip to: 1160 + /* 1013 */ MCD_OPC_Decode, + 153, + 3, + 21, // Opcode: REMU_l3r + /* 1017 */ MCD_OPC_FilterValue, + 26, + 35, + 0, + 0, // Skip to: 1057 + /* 1022 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 1025 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1041 + /* 1030 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 123, + 0, + 0, // Skip to: 1160 + /* 1037 */ MCD_OPC_Decode, + 140, + 2, + 35, // Opcode: BLRF_lu10 + /* 1041 */ MCD_OPC_FilterValue, + 1, + 114, + 0, + 0, // Skip to: 1160 + /* 1046 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 107, + 0, + 0, // Skip to: 1160 + /* 1053 */ MCD_OPC_Decode, + 138, + 2, + 36, // Opcode: BLRB_lu10 + /* 1057 */ MCD_OPC_FilterValue, + 27, + 35, + 0, + 0, // Skip to: 1097 + /* 1062 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 1065 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1081 + /* 1070 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 83, + 0, + 0, // Skip to: 1160 + /* 1077 */ MCD_OPC_Decode, + 229, + 2, + 35, // Opcode: LDAPF_lu10 + /* 1081 */ MCD_OPC_FilterValue, + 1, + 74, + 0, + 0, // Skip to: 1160 + /* 1086 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 67, + 0, + 0, // Skip to: 1160 + /* 1093 */ MCD_OPC_Decode, + 227, + 2, + 36, // Opcode: LDAPB_lu10 + /* 1097 */ MCD_OPC_FilterValue, + 28, + 35, + 0, + 0, // Skip to: 1137 + /* 1102 */ MCD_OPC_ExtractField, + 26, + 1, // Inst{26} ... + /* 1105 */ MCD_OPC_FilterValue, + 0, + 11, + 0, + 0, // Skip to: 1121 + /* 1110 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 43, + 0, + 0, // Skip to: 1160 + /* 1117 */ MCD_OPC_Decode, + 133, + 2, + 35, // Opcode: BLACP_lu10 + /* 1121 */ MCD_OPC_FilterValue, + 1, + 34, + 0, + 0, // Skip to: 1160 + /* 1126 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 27, + 0, + 0, // Skip to: 1160 + /* 1133 */ MCD_OPC_Decode, + 250, + 2, + 35, // Opcode: LDWCP_lu10 + /* 1137 */ MCD_OPC_FilterValue, + 29, + 18, + 0, + 0, // Skip to: 1160 + /* 1142 */ MCD_OPC_CheckField, + 26, + 1, + 0, + 11, + 0, + 0, // Skip to: 1160 + /* 1149 */ MCD_OPC_CheckField, + 10, + 6, + 60, + 4, + 0, + 0, // Skip to: 1160 + /* 1156 */ MCD_OPC_Decode, + 159, + 3, + 29, // Opcode: SETC_lru6 + /* 1160 */ MCD_OPC_Fail, + 0}; + +static bool getbool(uint64_t b) { return b != 0; } +static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { + llvm_unreachable("Invalid index!"); } -#define DecodeToMCInst(fname,fieldname, InsnType) \ -static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, const void *Decoder) \ -{ \ - InsnType tmp; \ - switch (Idx) { \ - default: \ - case 0: \ - return S; \ - case 1: \ - tmp = fieldname(insn, 0, 4); \ - if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 2: \ - if (Decode2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 3: \ - if (Decode2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 4: \ - if (DecodeR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 5: \ - if (Decode3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 6: \ - if (Decode2RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 7: \ - if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 8: \ - if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 9: \ - if (DecodeRUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 10: \ - tmp = fieldname(insn, 6, 4); \ - if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 11: \ - tmp = fieldname(insn, 0, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 12: \ - tmp = fieldname(insn, 6, 4); \ - if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 13: \ - tmp = fieldname(insn, 0, 6); \ - if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 14: \ - tmp = fieldname(insn, 6, 4); \ - if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 6); \ - if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 15: \ - if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 16: \ - if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 17: \ - if (Decode3RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 18: \ - tmp = fieldname(insn, 0, 10); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 19: \ - tmp = fieldname(insn, 0, 10); \ - if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 20: \ - if (DecodeL2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 21: \ - if (DecodeL3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 22: \ - if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 23: \ - if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 24: \ - if (DecodeL5RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 25: \ - if (DecodeL6RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 26: \ - if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 27: \ - tmp = fieldname(insn, 22, 4); \ - if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= (fieldname(insn, 0, 10) << 6); \ - tmp |= (fieldname(insn, 16, 6) << 0); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 28: \ - tmp = 0; \ - tmp |= (fieldname(insn, 0, 10) << 6); \ - tmp |= (fieldname(insn, 16, 6) << 0); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 29: \ - tmp = fieldname(insn, 22, 4); \ - if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= (fieldname(insn, 0, 10) << 6); \ - tmp |= (fieldname(insn, 16, 6) << 0); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 30: \ - tmp = 0; \ - tmp |= (fieldname(insn, 0, 10) << 6); \ - tmp |= (fieldname(insn, 16, 6) << 0); \ - if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 31: \ - tmp = fieldname(insn, 22, 4); \ - if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= (fieldname(insn, 0, 10) << 6); \ - tmp |= (fieldname(insn, 16, 6) << 0); \ - if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 32: \ - if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 33: \ - if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 34: \ - if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 35: \ - tmp = 0; \ - tmp |= (fieldname(insn, 0, 10) << 10); \ - tmp |= (fieldname(insn, 16, 10) << 0); \ - MCOperand_CreateImm0(MI, tmp); \ - return S; \ - case 36: \ - tmp = 0; \ - tmp |= (fieldname(insn, 0, 10) << 10); \ - tmp |= (fieldname(insn, 16, 10) << 0); \ - if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - } \ -} - -#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ -{ \ - uint64_t Bits = getFeatureBits(feature); \ - const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0, ExpectedValue; \ - DecodeStatus S = MCDisassembler_Success; \ - unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ - InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail; \ - for (;;) { \ - switch (*Ptr) { \ - default: \ - return MCDisassembler_Fail; \ - case MCD_OPC_ExtractField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - ++Ptr; \ - CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ - break; \ - } \ - case MCD_OPC_FilterValue: { \ - Val = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (Val != CurFieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckField: { \ - Start = *++Ptr; \ - Len = *++Ptr; \ - FieldValue = fieldname(insn, Start, Len); \ - ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - if (ExpectedValue != FieldValue) \ - Ptr += NumToSkip; \ - break; \ - } \ - case MCD_OPC_CheckPredicate: { \ - PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NumToSkip = *Ptr++; \ - NumToSkip |= (*Ptr++) << 8; \ - Pred = checkDecoderPredicate(PIdx, Bits); \ - if (!Pred) \ - Ptr += NumToSkip; \ - (void)Pred; \ - break; \ - } \ - case MCD_OPC_Decode: { \ - Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - MCInst_setOpcode(MI, Opc); \ - return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ - } \ - case MCD_OPC_SoftFail: { \ - PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ - Ptr += Len; \ - NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ - Ptr += Len; \ - Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ - if (Fail) \ - S = MCDisassembler_SoftFail; \ - break; \ - } \ - case MCD_OPC_Fail: { \ - return MCDisassembler_Fail; \ - } \ - } \ - } \ +#define DecodeToMCInst(fname, fieldname, InsnType) \ + static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, \ + MCInst *MI, uint64_t Address, bool *Decoder) { \ + InsnType tmp; \ + switch (Idx) { \ + default: \ + llvm_unreachable("Invalid index!"); \ + case 0: \ + return S; \ + case 1: \ + tmp = fieldname(insn, 0, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 2: \ + if (Decode2RInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 3: \ + if (Decode2RUSInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 4: \ + if (DecodeR2RInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 5: \ + if (Decode3RInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 6: \ + if (Decode2RImmInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 7: \ + if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 8: \ + if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 9: \ + if (DecodeRUSInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 10: \ + tmp = fieldname(insn, 6, 4); \ + if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 11: \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 12: \ + tmp = fieldname(insn, 6, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 13: \ + tmp = fieldname(insn, 0, 6); \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 14: \ + tmp = fieldname(insn, 6, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = fieldname(insn, 0, 6); \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 15: \ + if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 16: \ + if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 17: \ + if (Decode3RImmInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 0, 10); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 19: \ + tmp = fieldname(insn, 0, 10); \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 20: \ + if (DecodeL2RInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 21: \ + if (DecodeL3RInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 22: \ + if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 23: \ + if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 24: \ + if (DecodeL5RInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 25: \ + if (DecodeL6RInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 26: \ + if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 27: \ + tmp = fieldname(insn, 22, 4); \ + if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 10) << 6; \ + tmp |= fieldname(insn, 16, 6) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 28: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 10) << 6; \ + tmp |= fieldname(insn, 16, 6) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 29: \ + tmp = fieldname(insn, 22, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 10) << 6; \ + tmp |= fieldname(insn, 16, 6) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 30: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 10) << 6; \ + tmp |= fieldname(insn, 16, 6) << 0; \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 31: \ + tmp = fieldname(insn, 22, 4); \ + if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 10) << 6; \ + tmp |= fieldname(insn, 16, 6) << 0; \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 32: \ + if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 33: \ + if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 34: \ + if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + case 35: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 10) << 10; \ + tmp |= fieldname(insn, 16, 10) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 36: \ + tmp = 0x0; \ + tmp |= fieldname(insn, 0, 10) << 10; \ + tmp |= fieldname(insn, 16, 10) << 0; \ + if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == \ + MCDisassembler_Fail) { \ + return MCDisassembler_Fail; \ + } \ + return S; \ + } \ + } + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ + static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address, \ + MCRegisterInfo *MRI, int feature) { \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, feature))) \ + Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could \ + * be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ + } + +FieldFromInstruction(fieldFromInstruction, uint32_t) + DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) + DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) + +#endif // MIPS_GET_DISASSEMBLER +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +#define XCore_CP 1 +#define XCore_DP 2 +#define XCore_LR 3 +#define XCore_SP 4 +#define XCore_R0 5 +#define XCore_R1 6 +#define XCore_R2 7 +#define XCore_R3 8 +#define XCore_R4 9 +#define XCore_R5 10 +#define XCore_R6 11 +#define XCore_R7 12 +#define XCore_R8 13 +#define XCore_R9 14 +#define XCore_R10 15 +#define XCore_R11 16 +#define XCore_NUM_TARGET_REGS 17 + +// Register classes + +#define XCore_RRegsRegClassID 0 +#define XCore_GRRegsRegClassID 1 + +#endif // GET_REGINFO_ENUM + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM +#define XCore_PHI 0 +#define XCore_INLINEASM 1 +#define XCore_INLINEASM_BR 2 +#define XCore_CFI_INSTRUCTION 3 +#define XCore_EH_LABEL 4 +#define XCore_GC_LABEL 5 +#define XCore_ANNOTATION_LABEL 6 +#define XCore_KILL 7 +#define XCore_EXTRACT_SUBREG 8 +#define XCore_INSERT_SUBREG 9 +#define XCore_IMPLICIT_DEF 10 +#define XCore_SUBREG_TO_REG 11 +#define XCore_COPY_TO_REGCLASS 12 +#define XCore_DBG_VALUE 13 +#define XCore_DBG_VALUE_LIST 14 +#define XCore_DBG_INSTR_REF 15 +#define XCore_DBG_PHI 16 +#define XCore_DBG_LABEL 17 +#define XCore_REG_SEQUENCE 18 +#define XCore_COPY 19 +#define XCore_BUNDLE 20 +#define XCore_LIFETIME_START 21 +#define XCore_LIFETIME_END 22 +#define XCore_PSEUDO_PROBE 23 +#define XCore_ARITH_FENCE 24 +#define XCore_STACKMAP 25 +#define XCore_FENTRY_CALL 26 +#define XCore_PATCHPOINT 27 +#define XCore_LOAD_STACK_GUARD 28 +#define XCore_PREALLOCATED_SETUP 29 +#define XCore_PREALLOCATED_ARG 30 +#define XCore_STATEPOINT 31 +#define XCore_LOCAL_ESCAPE 32 +#define XCore_FAULTING_OP 33 +#define XCore_PATCHABLE_OP 34 +#define XCore_PATCHABLE_FUNCTION_ENTER 35 +#define XCore_PATCHABLE_RET 36 +#define XCore_PATCHABLE_FUNCTION_EXIT 37 +#define XCore_PATCHABLE_TAIL_CALL 38 +#define XCore_PATCHABLE_EVENT_CALL 39 +#define XCore_PATCHABLE_TYPED_EVENT_CALL 40 +#define XCore_ICALL_BRANCH_FUNNEL 41 +#define XCore_G_ASSERT_SEXT 42 +#define XCore_G_ASSERT_ZEXT 43 +#define XCore_G_ADD 44 +#define XCore_G_SUB 45 +#define XCore_G_MUL 46 +#define XCore_G_SDIV 47 +#define XCore_G_UDIV 48 +#define XCore_G_SREM 49 +#define XCore_G_UREM 50 +#define XCore_G_SDIVREM 51 +#define XCore_G_UDIVREM 52 +#define XCore_G_AND 53 +#define XCore_G_OR 54 +#define XCore_G_XOR 55 +#define XCore_G_IMPLICIT_DEF 56 +#define XCore_G_PHI 57 +#define XCore_G_FRAME_INDEX 58 +#define XCore_G_GLOBAL_VALUE 59 +#define XCore_G_EXTRACT 60 +#define XCore_G_UNMERGE_VALUES 61 +#define XCore_G_INSERT 62 +#define XCore_G_MERGE_VALUES 63 +#define XCore_G_BUILD_VECTOR 64 +#define XCore_G_BUILD_VECTOR_TRUNC 65 +#define XCore_G_CONCAT_VECTORS 66 +#define XCore_G_PTRTOINT 67 +#define XCore_G_INTTOPTR 68 +#define XCore_G_BITCAST 69 +#define XCore_G_FREEZE 70 +#define XCore_G_INTRINSIC_TRUNC 71 +#define XCore_G_INTRINSIC_ROUND 72 +#define XCore_G_INTRINSIC_LRINT 73 +#define XCore_G_INTRINSIC_ROUNDEVEN 74 +#define XCore_G_READCYCLECOUNTER 75 +#define XCore_G_LOAD 76 +#define XCore_G_SEXTLOAD 77 +#define XCore_G_ZEXTLOAD 78 +#define XCore_G_INDEXED_LOAD 79 +#define XCore_G_INDEXED_SEXTLOAD 80 +#define XCore_G_INDEXED_ZEXTLOAD 81 +#define XCore_G_STORE 82 +#define XCore_G_INDEXED_STORE 83 +#define XCore_G_ATOMIC_CMPXCHG_WITH_SUCCESS 84 +#define XCore_G_ATOMIC_CMPXCHG 85 +#define XCore_G_ATOMICRMW_XCHG 86 +#define XCore_G_ATOMICRMW_ADD 87 +#define XCore_G_ATOMICRMW_SUB 88 +#define XCore_G_ATOMICRMW_AND 89 +#define XCore_G_ATOMICRMW_NAND 90 +#define XCore_G_ATOMICRMW_OR 91 +#define XCore_G_ATOMICRMW_XOR 92 +#define XCore_G_ATOMICRMW_MAX 93 +#define XCore_G_ATOMICRMW_MIN 94 +#define XCore_G_ATOMICRMW_UMAX 95 +#define XCore_G_ATOMICRMW_UMIN 96 +#define XCore_G_ATOMICRMW_FADD 97 +#define XCore_G_ATOMICRMW_FSUB 98 +#define XCore_G_FENCE 99 +#define XCore_G_BRCOND 100 +#define XCore_G_BRINDIRECT 101 +#define XCore_G_INTRINSIC 102 +#define XCore_G_INTRINSIC_W_SIDE_EFFECTS 103 +#define XCore_G_ANYEXT 104 +#define XCore_G_TRUNC 105 +#define XCore_G_CONSTANT 106 +#define XCore_G_FCONSTANT 107 +#define XCore_G_VASTART 108 +#define XCore_G_VAARG 109 +#define XCore_G_SEXT 110 +#define XCore_G_SEXT_INREG 111 +#define XCore_G_ZEXT 112 +#define XCore_G_SHL 113 +#define XCore_G_LSHR 114 +#define XCore_G_ASHR 115 +#define XCore_G_FSHL 116 +#define XCore_G_FSHR 117 +#define XCore_G_ROTR 118 +#define XCore_G_ROTL 119 +#define XCore_G_ICMP 120 +#define XCore_G_FCMP 121 +#define XCore_G_SELECT 122 +#define XCore_G_UADDO 123 +#define XCore_G_UADDE 124 +#define XCore_G_USUBO 125 +#define XCore_G_USUBE 126 +#define XCore_G_SADDO 127 +#define XCore_G_SADDE 128 +#define XCore_G_SSUBO 129 +#define XCore_G_SSUBE 130 +#define XCore_G_UMULO 131 +#define XCore_G_SMULO 132 +#define XCore_G_UMULH 133 +#define XCore_G_SMULH 134 +#define XCore_G_UADDSAT 135 +#define XCore_G_SADDSAT 136 +#define XCore_G_USUBSAT 137 +#define XCore_G_SSUBSAT 138 +#define XCore_G_USHLSAT 139 +#define XCore_G_SSHLSAT 140 +#define XCore_G_SMULFIX 141 +#define XCore_G_UMULFIX 142 +#define XCore_G_SMULFIXSAT 143 +#define XCore_G_UMULFIXSAT 144 +#define XCore_G_SDIVFIX 145 +#define XCore_G_UDIVFIX 146 +#define XCore_G_SDIVFIXSAT 147 +#define XCore_G_UDIVFIXSAT 148 +#define XCore_G_FADD 149 +#define XCore_G_FSUB 150 +#define XCore_G_FMUL 151 +#define XCore_G_FMA 152 +#define XCore_G_FMAD 153 +#define XCore_G_FDIV 154 +#define XCore_G_FREM 155 +#define XCore_G_FPOW 156 +#define XCore_G_FPOWI 157 +#define XCore_G_FEXP 158 +#define XCore_G_FEXP2 159 +#define XCore_G_FLOG 160 +#define XCore_G_FLOG2 161 +#define XCore_G_FLOG10 162 +#define XCore_G_FNEG 163 +#define XCore_G_FPEXT 164 +#define XCore_G_FPTRUNC 165 +#define XCore_G_FPTOSI 166 +#define XCore_G_FPTOUI 167 +#define XCore_G_SITOFP 168 +#define XCore_G_UITOFP 169 +#define XCore_G_FABS 170 +#define XCore_G_FCOPYSIGN 171 +#define XCore_G_FCANONICALIZE 172 +#define XCore_G_FMINNUM 173 +#define XCore_G_FMAXNUM 174 +#define XCore_G_FMINNUM_IEEE 175 +#define XCore_G_FMAXNUM_IEEE 176 +#define XCore_G_FMINIMUM 177 +#define XCore_G_FMAXIMUM 178 +#define XCore_G_PTR_ADD 179 +#define XCore_G_PTRMASK 180 +#define XCore_G_SMIN 181 +#define XCore_G_SMAX 182 +#define XCore_G_UMIN 183 +#define XCore_G_UMAX 184 +#define XCore_G_ABS 185 +#define XCore_G_LROUND 186 +#define XCore_G_LLROUND 187 +#define XCore_G_BR 188 +#define XCore_G_BRJT 189 +#define XCore_G_INSERT_VECTOR_ELT 190 +#define XCore_G_EXTRACT_VECTOR_ELT 191 +#define XCore_G_SHUFFLE_VECTOR 192 +#define XCore_G_CTTZ 193 +#define XCore_G_CTTZ_ZERO_UNDEF 194 +#define XCore_G_CTLZ 195 +#define XCore_G_CTLZ_ZERO_UNDEF 196 +#define XCore_G_CTPOP 197 +#define XCore_G_BSWAP 198 +#define XCore_G_BITREVERSE 199 +#define XCore_G_FCEIL 200 +#define XCore_G_FCOS 201 +#define XCore_G_FSIN 202 +#define XCore_G_FSQRT 203 +#define XCore_G_FFLOOR 204 +#define XCore_G_FRINT 205 +#define XCore_G_FNEARBYINT 206 +#define XCore_G_ADDRSPACE_CAST 207 +#define XCore_G_BLOCK_ADDR 208 +#define XCore_G_JUMP_TABLE 209 +#define XCore_G_DYN_STACKALLOC 210 +#define XCore_G_STRICT_FADD 211 +#define XCore_G_STRICT_FSUB 212 +#define XCore_G_STRICT_FMUL 213 +#define XCore_G_STRICT_FDIV 214 +#define XCore_G_STRICT_FREM 215 +#define XCore_G_STRICT_FMA 216 +#define XCore_G_STRICT_FSQRT 217 +#define XCore_G_READ_REGISTER 218 +#define XCore_G_WRITE_REGISTER 219 +#define XCore_G_MEMCPY 220 +#define XCore_G_MEMCPY_INLINE 221 +#define XCore_G_MEMMOVE 222 +#define XCore_G_MEMSET 223 +#define XCore_G_BZERO 224 +#define XCore_G_VECREDUCE_SEQ_FADD 225 +#define XCore_G_VECREDUCE_SEQ_FMUL 226 +#define XCore_G_VECREDUCE_FADD 227 +#define XCore_G_VECREDUCE_FMUL 228 +#define XCore_G_VECREDUCE_FMAX 229 +#define XCore_G_VECREDUCE_FMIN 230 +#define XCore_G_VECREDUCE_ADD 231 +#define XCore_G_VECREDUCE_MUL 232 +#define XCore_G_VECREDUCE_AND 233 +#define XCore_G_VECREDUCE_OR 234 +#define XCore_G_VECREDUCE_XOR 235 +#define XCore_G_VECREDUCE_SMAX 236 +#define XCore_G_VECREDUCE_SMIN 237 +#define XCore_G_VECREDUCE_UMAX 238 +#define XCore_G_VECREDUCE_UMIN 239 +#define XCore_G_SBFX 240 +#define XCore_G_UBFX 241 +#define XCore_ADJCALLSTACKDOWN 242 +#define XCore_ADJCALLSTACKUP 243 +#define XCore_BR_JT 244 +#define XCore_BR_JT32 245 +#define XCore_EH_RETURN 246 +#define XCore_FRAME_TO_ARGS_OFFSET 247 +#define XCore_Int_MemBarrier 248 +#define XCore_LDAWFI 249 +#define XCore_LDWFI 250 +#define XCore_SELECT_CC 251 +#define XCore_STWFI 252 +#define XCore_ADD_2rus 253 +#define XCore_ADD_3r 254 +#define XCore_ANDNOT_2r 255 +#define XCore_AND_3r 256 +#define XCore_ASHR_l2rus 257 +#define XCore_ASHR_l3r 258 +#define XCore_BAU_1r 259 +#define XCore_BITREV_l2r 260 +#define XCore_BLACP_lu10 261 +#define XCore_BLACP_u10 262 +#define XCore_BLAT_lu6 263 +#define XCore_BLAT_u6 264 +#define XCore_BLA_1r 265 +#define XCore_BLRB_lu10 266 +#define XCore_BLRB_u10 267 +#define XCore_BLRF_lu10 268 +#define XCore_BLRF_u10 269 +#define XCore_BRBF_lru6 270 +#define XCore_BRBF_ru6 271 +#define XCore_BRBT_lru6 272 +#define XCore_BRBT_ru6 273 +#define XCore_BRBU_lu6 274 +#define XCore_BRBU_u6 275 +#define XCore_BRFF_lru6 276 +#define XCore_BRFF_ru6 277 +#define XCore_BRFT_lru6 278 +#define XCore_BRFT_ru6 279 +#define XCore_BRFU_lu6 280 +#define XCore_BRFU_u6 281 +#define XCore_BRU_1r 282 +#define XCore_BYTEREV_l2r 283 +#define XCore_CHKCT_2r 284 +#define XCore_CHKCT_rus 285 +#define XCore_CLRE_0R 286 +#define XCore_CLRPT_1R 287 +#define XCore_CLRSR_branch_lu6 288 +#define XCore_CLRSR_branch_u6 289 +#define XCore_CLRSR_lu6 290 +#define XCore_CLRSR_u6 291 +#define XCore_CLZ_l2r 292 +#define XCore_CRC8_l4r 293 +#define XCore_CRC_l3r 294 +#define XCore_DCALL_0R 295 +#define XCore_DENTSP_0R 296 +#define XCore_DGETREG_1r 297 +#define XCore_DIVS_l3r 298 +#define XCore_DIVU_l3r 299 +#define XCore_DRESTSP_0R 300 +#define XCore_DRET_0R 301 +#define XCore_ECALLF_1r 302 +#define XCore_ECALLT_1r 303 +#define XCore_EDU_1r 304 +#define XCore_EEF_2r 305 +#define XCore_EET_2r 306 +#define XCore_EEU_1r 307 +#define XCore_ENDIN_2r 308 +#define XCore_ENTSP_lu6 309 +#define XCore_ENTSP_u6 310 +#define XCore_EQ_2rus 311 +#define XCore_EQ_3r 312 +#define XCore_EXTDP_lu6 313 +#define XCore_EXTDP_u6 314 +#define XCore_EXTSP_lu6 315 +#define XCore_EXTSP_u6 316 +#define XCore_FREER_1r 317 +#define XCore_FREET_0R 318 +#define XCore_GETD_l2r 319 +#define XCore_GETED_0R 320 +#define XCore_GETET_0R 321 +#define XCore_GETID_0R 322 +#define XCore_GETKEP_0R 323 +#define XCore_GETKSP_0R 324 +#define XCore_GETN_l2r 325 +#define XCore_GETPS_l2r 326 +#define XCore_GETR_rus 327 +#define XCore_GETSR_lu6 328 +#define XCore_GETSR_u6 329 +#define XCore_GETST_2r 330 +#define XCore_GETTS_2r 331 +#define XCore_INCT_2r 332 +#define XCore_INITCP_2r 333 +#define XCore_INITDP_2r 334 +#define XCore_INITLR_l2r 335 +#define XCore_INITPC_2r 336 +#define XCore_INITSP_2r 337 +#define XCore_INPW_l2rus 338 +#define XCore_INSHR_2r 339 +#define XCore_INT_2r 340 +#define XCore_IN_2r 341 +#define XCore_KCALL_1r 342 +#define XCore_KCALL_lu6 343 +#define XCore_KCALL_u6 344 +#define XCore_KENTSP_lu6 345 +#define XCore_KENTSP_u6 346 +#define XCore_KRESTSP_lu6 347 +#define XCore_KRESTSP_u6 348 +#define XCore_KRET_0R 349 +#define XCore_LADD_l5r 350 +#define XCore_LD16S_3r 351 +#define XCore_LD8U_3r 352 +#define XCore_LDA16B_l3r 353 +#define XCore_LDA16F_l3r 354 +#define XCore_LDAPB_lu10 355 +#define XCore_LDAPB_u10 356 +#define XCore_LDAPF_lu10 357 +#define XCore_LDAPF_lu10_ba 358 +#define XCore_LDAPF_u10 359 +#define XCore_LDAWB_l2rus 360 +#define XCore_LDAWB_l3r 361 +#define XCore_LDAWCP_lu6 362 +#define XCore_LDAWCP_u6 363 +#define XCore_LDAWDP_lru6 364 +#define XCore_LDAWDP_ru6 365 +#define XCore_LDAWF_l2rus 366 +#define XCore_LDAWF_l3r 367 +#define XCore_LDAWSP_lru6 368 +#define XCore_LDAWSP_ru6 369 +#define XCore_LDC_lru6 370 +#define XCore_LDC_ru6 371 +#define XCore_LDET_0R 372 +#define XCore_LDIVU_l5r 373 +#define XCore_LDSED_0R 374 +#define XCore_LDSPC_0R 375 +#define XCore_LDSSR_0R 376 +#define XCore_LDWCP_lru6 377 +#define XCore_LDWCP_lu10 378 +#define XCore_LDWCP_ru6 379 +#define XCore_LDWCP_u10 380 +#define XCore_LDWDP_lru6 381 +#define XCore_LDWDP_ru6 382 +#define XCore_LDWSP_lru6 383 +#define XCore_LDWSP_ru6 384 +#define XCore_LDW_2rus 385 +#define XCore_LDW_3r 386 +#define XCore_LMUL_l6r 387 +#define XCore_LSS_3r 388 +#define XCore_LSUB_l5r 389 +#define XCore_LSU_3r 390 +#define XCore_MACCS_l4r 391 +#define XCore_MACCU_l4r 392 +#define XCore_MJOIN_1r 393 +#define XCore_MKMSK_2r 394 +#define XCore_MKMSK_rus 395 +#define XCore_MSYNC_1r 396 +#define XCore_MUL_l3r 397 +#define XCore_NEG 398 +#define XCore_NOT 399 +#define XCore_OR_3r 400 +#define XCore_OUTCT_2r 401 +#define XCore_OUTCT_rus 402 +#define XCore_OUTPW_l2rus 403 +#define XCore_OUTSHR_2r 404 +#define XCore_OUTT_2r 405 +#define XCore_OUT_2r 406 +#define XCore_PEEK_2r 407 +#define XCore_REMS_l3r 408 +#define XCore_REMU_l3r 409 +#define XCore_RETSP_lu6 410 +#define XCore_RETSP_u6 411 +#define XCore_SETCLK_l2r 412 +#define XCore_SETCP_1r 413 +#define XCore_SETC_l2r 414 +#define XCore_SETC_lru6 415 +#define XCore_SETC_ru6 416 +#define XCore_SETDP_1r 417 +#define XCore_SETD_2r 418 +#define XCore_SETEV_1r 419 +#define XCore_SETKEP_0R 420 +#define XCore_SETN_l2r 421 +#define XCore_SETPSC_2r 422 +#define XCore_SETPS_l2r 423 +#define XCore_SETPT_2r 424 +#define XCore_SETRDY_l2r 425 +#define XCore_SETSP_1r 426 +#define XCore_SETSR_branch_lu6 427 +#define XCore_SETSR_branch_u6 428 +#define XCore_SETSR_lu6 429 +#define XCore_SETSR_u6 430 +#define XCore_SETTW_l2r 431 +#define XCore_SETV_1r 432 +#define XCore_SEXT_2r 433 +#define XCore_SEXT_rus 434 +#define XCore_SHL_2rus 435 +#define XCore_SHL_3r 436 +#define XCore_SHR_2rus 437 +#define XCore_SHR_3r 438 +#define XCore_SSYNC_0r 439 +#define XCore_ST16_l3r 440 +#define XCore_ST8_l3r 441 +#define XCore_STET_0R 442 +#define XCore_STSED_0R 443 +#define XCore_STSPC_0R 444 +#define XCore_STSSR_0R 445 +#define XCore_STWDP_lru6 446 +#define XCore_STWDP_ru6 447 +#define XCore_STWSP_lru6 448 +#define XCore_STWSP_ru6 449 +#define XCore_STW_2rus 450 +#define XCore_STW_l3r 451 +#define XCore_SUB_2rus 452 +#define XCore_SUB_3r 453 +#define XCore_SYNCR_1r 454 +#define XCore_TESTCT_2r 455 +#define XCore_TESTLCL_l2r 456 +#define XCore_TESTWCT_2r 457 +#define XCore_TSETMR_2r 458 +#define XCore_TSETR_3r 459 +#define XCore_TSTART_1R 460 +#define XCore_WAITEF_1R 461 +#define XCore_WAITET_1R 462 +#define XCore_WAITEU_0R 463 +#define XCore_XOR_l3r 464 +#define XCore_ZEXT_2r 465 +#define XCore_ZEXT_rus 466 +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_REGINFO_EXTRA +#undef GET_REGINFO_EXTRA +#endif // GET_REGINFO_EXTRA + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + + static const MCPhysReg XCoreRegDiffLists[] = { + /* 0 */ 65535, + 0, +}; + +static const uint16_t XCoreSubRegIdxLists[] = { + /* 0 */ 0, +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char XCoreRegStrings[] = { + /* 0 */ "R10\0" + /* 4 */ "R0\0" + /* 7 */ "R11\0" + /* 11 */ "R1\0" + /* 14 */ "R2\0" + /* 17 */ "R3\0" + /* 20 */ "R4\0" + /* 23 */ "R5\0" + /* 26 */ "R6\0" + /* 29 */ "R7\0" + /* 32 */ "R8\0" + /* 35 */ "R9\0" + /* 38 */ "CP\0" + /* 41 */ "DP\0" + /* 44 */ "SP\0" + /* 47 */ "LR\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterDesc XCoreRegDesc[] = { + // Descriptors + {3, 0, 0, 0, 0, 0}, {38, 1, 1, 0, 1, 10}, {41, 1, 1, 0, 1, 10}, + {47, 1, 1, 0, 1, 4}, {44, 1, 1, 0, 1, 8}, {4, 1, 1, 0, 1, 10}, + {11, 1, 1, 0, 1, 10}, {14, 1, 1, 0, 1, 10}, {17, 1, 1, 0, 1, 0}, + {20, 1, 1, 0, 1, 0}, {23, 1, 1, 0, 1, 10}, {26, 1, 1, 0, 1, 6}, + {29, 1, 1, 0, 1, 0}, {32, 1, 1, 0, 1, 6}, {35, 1, 1, 0, 1, 2}, + {0, 1, 1, 0, 1, 12}, {7, 1, 1, 0, 1, 10}, +}; + +// RRegs Register Class... +static const MCPhysReg RRegs[] = { + XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, + XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, + XCore_CP, XCore_DP, XCore_SP, XCore_LR, +}; + +// RRegs Bit set. +static const uint8_t RRegsBits[] = { + 0xfe, + 0xff, + 0x01, +}; + +// GRRegs Register Class... +static const MCPhysReg GRRegs[] = { + XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, + XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, +}; + +// GRRegs Bit set. +static const uint8_t GRRegsBits[] = { + 0xe0, + 0xff, + 0x01, +}; + +// end of register classes misc + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +static const char XCoreRegClassStrings[] = { + /* 0 */ "GRRegs\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +static const MCRegisterClass XCoreMCRegisterClasses[] = { + {RRegs, RRegsBits, sizeof(RRegsBits)}, + {GRRegs, GRRegsBits, sizeof(GRRegsBits)}, +}; + +#endif // GET_REGINFO_MC_DESC + +#ifdef GET_ASM_WRITER +#undef GET_ASM_WRITER + +static void llvm_unreachable(const char *info) {} +static void assert(int val) {} +typedef struct MCMnemonic { + const char *first; + uint64_t second; +} MCMnemonic; + +static MCMnemonic createMnemonic(const char *first, uint64_t second) { + MCMnemonic mnemonic; + mnemonic.first = first; + mnemonic.second = second; + return mnemonic; +} + +/// getMnemonic - This method is automatically generated by tablegen +/// from the instruction set description. +MCMnemonic XCore_getMnemonic(const MCInst *MI) { + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = { + /* 0 */ "ldap r11, \0" + /* 11 */ "getsr r11, \0" + /* 23 */ "set cp, \0" + /* 32 */ "set dp, \0" + /* 41 */ "set sp, \0" + /* 50 */ "crc32 \0" + /* 57 */ "lda16 \0" + /* 64 */ "st16 \0" + /* 70 */ "crc8 \0" + /* 76 */ "st8 \0" + /* 81 */ "# LDAWFI \0" + /* 91 */ "# LDWFI \0" + /* 100 */ "# STWFI \0" + /* 109 */ "# EH_RETURN \0" + /* 122 */ "# ADJCALLSTACKDOWN \0" + /* 142 */ "# ADJCALLSTACKUP \0" + /* 160 */ "# FRAME_TO_ARGS_OFFSET \0" + /* 184 */ "bla \0" + /* 189 */ "lsub \0" + /* 195 */ "ldc \0" + /* 200 */ "ladd \0" + /* 206 */ "and \0" + /* 211 */ "getd \0" + /* 217 */ "bf \0" + /* 221 */ "eef \0" + /* 226 */ "waitef \0" + /* 234 */ "ecallf \0" + /* 242 */ "neg \0" + /* 247 */ "dgetreg \0" + /* 256 */ "peek \0" + /* 262 */ "mkmsk \0" + /* 269 */ "bl \0" + /* 273 */ "testlcl \0" + /* 282 */ "shl \0" + /* 287 */ "kcall \0" + /* 294 */ "lmul \0" + /* 300 */ "endin \0" + /* 307 */ "getn \0" + /* 313 */ "extdp \0" + /* 320 */ "retsp \0" + /* 327 */ "kentsp \0" + /* 335 */ "krestsp \0" + /* 344 */ "extsp \0" + /* 351 */ "eq \0" + /* 355 */ "ashr \0" + /* 361 */ "inshr \0" + /* 368 */ "xor \0" + /* 373 */ "clrsr \0" + /* 380 */ "setsr \0" + /* 387 */ "getr \0" + /* 393 */ "ld16s \0" + /* 400 */ "maccs \0" + /* 407 */ "rems \0" + /* 413 */ "lss \0" + /* 418 */ "getts \0" + /* 425 */ "divs \0" + /* 431 */ "blat \0" + /* 437 */ "bt \0" + /* 441 */ "inct \0" + /* 447 */ "testct \0" + /* 455 */ "testwct \0" + /* 464 */ "eet \0" + /* 469 */ "get \0" + /* 474 */ "waitet \0" + /* 482 */ "ecallt \0" + /* 490 */ "int \0" + /* 495 */ "andnot \0" + /* 503 */ "getst \0" + /* 510 */ "sext \0" + /* 516 */ "zext \0" + /* 522 */ "ld8u \0" + /* 528 */ "bau \0" + /* 533 */ "bu \0" + /* 537 */ "maccu \0" + /* 544 */ "remu \0" + /* 550 */ "bru \0" + /* 555 */ "lsu \0" + /* 560 */ "ldivu \0" + /* 567 */ "byterev \0" + /* 576 */ "bitrev \0" + /* 584 */ "ldaw \0" + /* 590 */ "ldw \0" + /* 595 */ "inpw \0" + /* 601 */ "stw \0" + /* 606 */ "clz \0" + /* 611 */ "# SELECT_CC PSEUDO!\0" + /* 631 */ "# XRay Function Patchable RET.\0" + /* 662 */ "# XRay Typed Event Log.\0" + /* 686 */ "# XRay Custom Event Log.\0" + /* 711 */ "# XRay Function Enter.\0" + /* 734 */ "# XRay Tail Call Exit.\0" + /* 757 */ "# XRay Function Exit.\0" + /* 779 */ "set kep, r11\0" + /* 792 */ "LIFETIME_END\0" + /* 805 */ "PSEUDO_PROBE\0" + /* 818 */ "BUNDLE\0" + /* 825 */ "DBG_VALUE\0" + /* 835 */ "DBG_INSTR_REF\0" + /* 849 */ "DBG_PHI\0" + /* 857 */ "DBG_LABEL\0" + /* 867 */ "#MEMBARRIER\0" + /* 879 */ "LIFETIME_START\0" + /* 894 */ "DBG_VALUE_LIST\0" + /* 909 */ "ldaw r11, cp[\0" + /* 923 */ "ldw r11, cp[\0" + /* 936 */ "bla cp[\0" + /* 944 */ "msync res[\0" + /* 955 */ "setpsc res[\0" + /* 967 */ "setc res[\0" + /* 977 */ "setd res[\0" + /* 987 */ "setclk res[\0" + /* 999 */ "mjoin res[\0" + /* 1010 */ "setn res[\0" + /* 1020 */ "syncr res[\0" + /* 1031 */ "freer res[\0" + /* 1042 */ "outshr res[\0" + /* 1054 */ "chkct res[\0" + /* 1065 */ "outct res[\0" + /* 1076 */ "clrpt res[\0" + /* 1087 */ "setpt res[\0" + /* 1098 */ "outt res[\0" + /* 1108 */ "out res[\0" + /* 1117 */ "edu res[\0" + /* 1126 */ "eeu res[\0" + /* 1135 */ "setev res[\0" + /* 1146 */ "setv res[\0" + /* 1156 */ "outpw res[\0" + /* 1167 */ "settw res[\0" + /* 1178 */ "setrdy res[\0" + /* 1190 */ "set ps[\0" + /* 1198 */ "set t[\0" + /* 1205 */ "init t[\0" + /* 1213 */ "start t[\0" + /* 1222 */ "ldw spc, sp[1]\0" + /* 1237 */ "stw spc, sp[1]\0" + /* 1252 */ "ldw ssr, sp[2]\0" + /* 1267 */ "stw ssr, sp[2]\0" + /* 1282 */ "ldw sed, sp[3]\0" + /* 1297 */ "stw sed, sp[3]\0" + /* 1312 */ "ldw et, sp[4]\0" + /* 1326 */ "stw et, sp[4]\0" + /* 1340 */ "ssync\0" + /* 1346 */ "get r11, ed\0" + /* 1358 */ "get r11, id\0" + /* 1370 */ "clre\0" + /* 1375 */ "# FEntry call\0" + /* 1389 */ "dcall\0" + /* 1395 */ "get r11, kep\0" + /* 1408 */ "get r11, ksp\0" + /* 1421 */ "dentsp\0" + /* 1428 */ "drestsp\0" + /* 1436 */ "tsetmr r\0" + /* 1445 */ "get r11, et\0" + /* 1457 */ "freet\0" + /* 1463 */ "dret\0" + /* 1468 */ "kret\0" + /* 1473 */ "waiteu\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // INLINEASM_BR + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 826U, // DBG_VALUE + 895U, // DBG_VALUE_LIST + 836U, // DBG_INSTR_REF + 850U, // DBG_PHI + 858U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 819U, // BUNDLE + 880U, // LIFETIME_START + 793U, // LIFETIME_END + 806U, // PSEUDO_PROBE + 0U, // ARITH_FENCE + 0U, // STACKMAP + 1376U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // PREALLOCATED_SETUP + 0U, // PREALLOCATED_ARG + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 712U, // PATCHABLE_FUNCTION_ENTER + 632U, // PATCHABLE_RET + 758U, // PATCHABLE_FUNCTION_EXIT + 735U, // PATCHABLE_TAIL_CALL + 687U, // PATCHABLE_EVENT_CALL + 663U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ASSERT_SEXT + 0U, // G_ASSERT_ZEXT + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_SDIVREM + 0U, // G_UDIVREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_BUILD_VECTOR + 0U, // G_BUILD_VECTOR_TRUNC + 0U, // G_CONCAT_VECTORS + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_FREEZE + 0U, // G_INTRINSIC_TRUNC + 0U, // G_INTRINSIC_ROUND + 0U, // G_INTRINSIC_LRINT + 0U, // G_INTRINSIC_ROUNDEVEN + 0U, // G_READCYCLECOUNTER + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_INDEXED_LOAD + 0U, // G_INDEXED_SEXTLOAD + 0U, // G_INDEXED_ZEXTLOAD + 0U, // G_STORE + 0U, // G_INDEXED_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_ATOMICRMW_FADD + 0U, // G_ATOMICRMW_FSUB + 0U, // G_FENCE + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_SEXT_INREG + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_FSHL + 0U, // G_FSHR + 0U, // G_ROTR + 0U, // G_ROTL + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDO + 0U, // G_UADDE + 0U, // G_USUBO + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SADDE + 0U, // G_SSUBO + 0U, // G_SSUBE + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_UADDSAT + 0U, // G_SADDSAT + 0U, // G_USUBSAT + 0U, // G_SSUBSAT + 0U, // G_USHLSAT + 0U, // G_SSHLSAT + 0U, // G_SMULFIX + 0U, // G_UMULFIX + 0U, // G_SMULFIXSAT + 0U, // G_UMULFIXSAT + 0U, // G_SDIVFIX + 0U, // G_UDIVFIX + 0U, // G_SDIVFIXSAT + 0U, // G_UDIVFIXSAT + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FMAD + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FPOWI + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FLOG10 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_FCOPYSIGN + 0U, // G_FCANONICALIZE + 0U, // G_FMINNUM + 0U, // G_FMAXNUM + 0U, // G_FMINNUM_IEEE + 0U, // G_FMAXNUM_IEEE + 0U, // G_FMINIMUM + 0U, // G_FMAXIMUM + 0U, // G_PTR_ADD + 0U, // G_PTRMASK + 0U, // G_SMIN + 0U, // G_SMAX + 0U, // G_UMIN + 0U, // G_UMAX + 0U, // G_ABS + 0U, // G_LROUND + 0U, // G_LLROUND + 0U, // G_BR + 0U, // G_BRJT + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_CTTZ + 0U, // G_CTTZ_ZERO_UNDEF + 0U, // G_CTLZ + 0U, // G_CTLZ_ZERO_UNDEF + 0U, // G_CTPOP + 0U, // G_BSWAP + 0U, // G_BITREVERSE + 0U, // G_FCEIL + 0U, // G_FCOS + 0U, // G_FSIN + 0U, // G_FSQRT + 0U, // G_FFLOOR + 0U, // G_FRINT + 0U, // G_FNEARBYINT + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // G_JUMP_TABLE + 0U, // G_DYN_STACKALLOC + 0U, // G_STRICT_FADD + 0U, // G_STRICT_FSUB + 0U, // G_STRICT_FMUL + 0U, // G_STRICT_FDIV + 0U, // G_STRICT_FREM + 0U, // G_STRICT_FMA + 0U, // G_STRICT_FSQRT + 0U, // G_READ_REGISTER + 0U, // G_WRITE_REGISTER + 0U, // G_MEMCPY + 0U, // G_MEMCPY_INLINE + 0U, // G_MEMMOVE + 0U, // G_MEMSET + 0U, // G_BZERO + 0U, // G_VECREDUCE_SEQ_FADD + 0U, // G_VECREDUCE_SEQ_FMUL + 0U, // G_VECREDUCE_FADD + 0U, // G_VECREDUCE_FMUL + 0U, // G_VECREDUCE_FMAX + 0U, // G_VECREDUCE_FMIN + 0U, // G_VECREDUCE_ADD + 0U, // G_VECREDUCE_MUL + 0U, // G_VECREDUCE_AND + 0U, // G_VECREDUCE_OR + 0U, // G_VECREDUCE_XOR + 0U, // G_VECREDUCE_SMAX + 0U, // G_VECREDUCE_SMIN + 0U, // G_VECREDUCE_UMAX + 0U, // G_VECREDUCE_UMIN + 0U, // G_SBFX + 0U, // G_UBFX + 2171U, // ADJCALLSTACKDOWN + 10383U, // ADJCALLSTACKUP + 283175U, // BR_JT + 545319U, // BR_JT32 + 2158U, // EH_RETURN + 10401U, // FRAME_TO_ARGS_OFFSET + 868U, // Int_MemBarrier + 2130U, // LDAWFI + 2140U, // LDWFI + 612U, // SELECT_CC + 2149U, // STWFI + 2099402U, // ADD_2rus + 2099402U, // ADD_3r + 788976U, // ANDNOT_2r + 2099407U, // AND_3r + 2099556U, // ASHR_l2rus + 2099556U, // ASHR_l3r + 10769U, // BAU_1r + 2625U, // BITREV_l2r + 27561U, // BLACP_lu10 + 27561U, // BLACP_u10 + 10672U, // BLAT_lu6 + 10672U, // BLAT_u6 + 10425U, // BLA_1r + 10510U, // BLRB_lu10 + 10510U, // BLRB_u10 + 10510U, // BLRF_lu10 + 10510U, // BLRF_u10 + 2266U, // BRBF_lru6 + 2266U, // BRBF_ru6 + 2486U, // BRBT_lru6 + 2486U, // BRBT_ru6 + 10774U, // BRBU_lu6 + 10774U, // BRBU_u6 + 2266U, // BRFF_lru6 + 2266U, // BRFF_ru6 + 2486U, // BRFT_lru6 + 2486U, // BRFT_ru6 + 10774U, // BRFU_lu6 + 10774U, // BRFU_u6 + 10791U, // BRU_1r + 2616U, // BYTEREV_l2r + 35871U, // CHKCT_2r + 35871U, // CHKCT_rus + 1371U, // CLRE_0R + 27701U, // CLRPT_1R + 10614U, // CLRSR_branch_lu6 + 10614U, // CLRSR_branch_u6 + 10614U, // CLRSR_lu6 + 10614U, // CLRSR_u6 + 2655U, // CLZ_l2r + 5247047U, // CRC8_l4r + 19662899U, // CRC_l3r + 1390U, // DCALL_0R + 1422U, // DENTSP_0R + 10488U, // DGETREG_1r + 2099626U, // DIVS_l3r + 2099762U, // DIVU_l3r + 1429U, // DRESTSP_0R + 1464U, // DRET_0R + 10475U, // ECALLF_1r + 10723U, // ECALLT_1r + 27742U, // EDU_1r + 6334686U, // EEF_2r + 6334929U, // EET_2r + 27751U, // EEU_1r + 6334765U, // ENDIN_2r + 10569U, // ENTSP_lu6 + 10569U, // ENTSP_u6 + 2099552U, // EQ_2rus + 2099552U, // EQ_3r + 10554U, // EXTDP_lu6 + 10554U, // EXTDP_u6 + 10585U, // EXTSP_lu6 + 10585U, // EXTSP_u6 + 27656U, // FREER_1r + 1458U, // FREET_0R + 6334676U, // GETD_l2r + 1347U, // GETED_0R + 1446U, // GETET_0R + 1359U, // GETID_0R + 1396U, // GETKEP_0R + 1409U, // GETKSP_0R + 6334772U, // GETN_l2r + 51670U, // GETPS_l2r + 2436U, // GETR_rus + 10252U, // GETSR_lu6 + 10252U, // GETSR_u6 + 6334968U, // GETST_2r + 6334883U, // GETTS_2r + 6334906U, // INCT_2r + 62646U, // INITCP_2r + 70838U, // INITDP_2r + 79030U, // INITLR_l2r + 87222U, // INITPC_2r + 95414U, // INITSP_2r + 8432212U, // INPW_l2rus + 7121258U, // INSHR_2r + 6334955U, // INT_2r + 6334768U, // IN_2r + 10528U, // KCALL_1r + 10528U, // KCALL_lu6 + 10528U, // KCALL_u6 + 10568U, // KENTSP_lu6 + 10568U, // KENTSP_u6 + 10576U, // KRESTSP_lu6 + 10576U, // KRESTSP_u6 + 1469U, // KRET_0R + 45093065U, // LADD_l5r + 12585354U, // LD16S_3r + 12585483U, // LD8U_3r + 14682170U, // LDA16B_l3r + 12585018U, // LDA16F_l3r + 10241U, // LDAPB_lu10 + 10241U, // LDAPB_u10 + 10241U, // LDAPF_lu10 + 10241U, // LDAPF_lu10_ba + 10241U, // LDAPF_u10 + 14682697U, // LDAWB_l2rus + 14682697U, // LDAWB_l3r + 27534U, // LDAWCP_lu6 + 27534U, // LDAWCP_u6 + 100937U, // LDAWDP_lru6 + 100937U, // LDAWDP_ru6 + 12585545U, // LDAWF_l2rus + 12585545U, // LDAWF_l3r + 109129U, // LDAWSP_lru6 + 109129U, // LDAWSP_ru6 + 2244U, // LDC_lru6 + 2244U, // LDC_ru6 + 1313U, // LDET_0R + 186649137U, // LDIVU_l5r + 1283U, // LDSED_0R + 1223U, // LDSPC_0R + 1253U, // LDSSR_0R + 117327U, // LDWCP_lru6 + 27548U, // LDWCP_lu10 + 117327U, // LDWCP_ru6 + 27548U, // LDWCP_u10 + 100943U, // LDWDP_lru6 + 100943U, // LDWDP_ru6 + 109135U, // LDWSP_lru6 + 109135U, // LDWSP_ru6 + 12585551U, // LDW_2rus + 12585551U, // LDW_3r + 270534951U, // LMUL_l6r + 2099614U, // LSS_3r + 45093054U, // LSUB_l5r + 2099756U, // LSU_3r + 455084433U, // MACCS_l4r + 455084570U, // MACCU_l4r + 27624U, // MJOIN_1r + 2311U, // MKMSK_2r + 2311U, // MKMSK_rus + 27569U, // MSYNC_1r + 2099496U, // MUL_l3r + 2291U, // NEG + 2547U, // NOT + 2099570U, // OR_3r + 35882U, // OUTCT_2r + 35882U, // OUTCT_rus + 78681221U, // OUTPW_l2rus + 39955U, // OUTSHR_2r + 35915U, // OUTT_2r + 35925U, // OUT_2r + 6334721U, // PEEK_2r + 2099608U, // REMS_l3r + 2099745U, // REMU_l3r + 10561U, // RETSP_lu6 + 10561U, // RETSP_u6 + 35804U, // SETCLK_l2r + 10264U, // SETCP_1r + 35784U, // SETC_l2r + 35784U, // SETC_lru6 + 35784U, // SETC_ru6 + 10273U, // SETDP_1r + 35794U, // SETD_2r + 126064U, // SETEV_1r + 780U, // SETKEP_0R + 35827U, // SETN_l2r + 35772U, // SETPSC_2r + 36007U, // SETPS_l2r + 35904U, // SETPT_2r + 35995U, // SETRDY_l2r + 10282U, // SETSP_1r + 10621U, // SETSR_branch_lu6 + 10621U, // SETSR_branch_u6 + 10621U, // SETSR_lu6 + 10621U, // SETSR_u6 + 35984U, // SETTW_l2r + 126075U, // SETV_1r + 788991U, // SEXT_2r + 788991U, // SEXT_rus + 2099483U, // SHL_2rus + 2099483U, // SHL_3r + 2099557U, // SHR_2rus + 2099557U, // SHR_3r + 1341U, // SSYNC_0r + 12585025U, // ST16_l3r + 12585037U, // ST8_l3r + 1327U, // STET_0R + 1298U, // STSED_0R + 1238U, // STSPC_0R + 1268U, // STSSR_0R + 100954U, // STWDP_lru6 + 100954U, // STWDP_ru6 + 109146U, // STWSP_lru6 + 109146U, // STWSP_ru6 + 12585562U, // STW_2rus + 12585562U, // STW_l3r + 2099391U, // SUB_2rus + 2099391U, // SUB_3r + 27645U, // SYNCR_1r + 6334912U, // TESTCT_2r + 6334738U, // TESTLCL_l2r + 6334920U, // TESTWCT_2r + 3485U, // TSETMR_2r + 138415U, // TSETR_3r + 27838U, // TSTART_1R + 10467U, // WAITEF_1R + 10715U, // WAITET_1R + 1474U, // WAITEU_0R + 2099569U, // XOR_l3r + 788997U, // ZEXT_2r + 788997U, // ZEXT_rus + }; + + // Emit the opcode for the instruction. + uint32_t Bits = 0; + Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; + return createMnemonic(AsmStrs + (Bits & 2047) - 1, Bits); +} +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) { + MCMnemonic MnemonicInfo = XCore_getMnemonic(MI); + +#ifndef CAPSTONE_DIET + + SStream_concat0(O, MnemonicInfo.first); +#endif + + uint32_t Bits = MnemonicInfo.second; + assert(Bits != 0 && "Cannot print this instruction."); + + // Fragment 0 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 11) & 3) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... + return; + break; + case 1: + // ADJCALLSTACKDOWN, ADJCALLSTACKUP, EH_RETURN, FRAME_TO_ARGS_OFFSET, LDA... + printOperand /* printOperand (+ ) */ (MI, 0, O); + break; + case 2: + // BR_JT, BR_JT32, CRC8_l4r, INITCP_2r, INITDP_2r, INITLR_l2r, INITPC_2r,... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 3: + // OUTSHR_2r, TSETR_3r + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + } + + // Fragment 1 encoded into 5 bits for 17 unique commands. + switch ((Bits >> 13) & 31) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADJCALLSTACKDOWN, EH_RETURN, LDAWFI, LDWFI, STWFI, ADD_2rus, ADD_3r, A... + SStream_concat0(O, ", "); + break; + case 1: + // ADJCALLSTACKUP, FRAME_TO_ARGS_OFFSET, BAU_1r, BLAT_lu6, BLAT_u6, BLA_1... + return; + break; + case 2: + // BR_JT, BR_JT32 + SStream_concat0(O, "\n"); + break; + case 3: + // BLACP_lu10, BLACP_u10, CLRPT_1R, EDU_1r, EEU_1r, FREER_1r, LDAWCP_lu6,... + SStream_concat0(O, "]"); + return; + break; + case 4: + // CHKCT_2r, CHKCT_rus, OUTCT_2r, OUTCT_rus, OUTPW_l2rus, OUTSHR_2r, OUTT... + SStream_concat0(O, "], "); + break; + case 5: + // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT... + SStream_concat0(O, ", res["); + break; + case 6: + // GETPS_l2r + SStream_concat0(O, ", ps["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 7: + // INITCP_2r + SStream_concat0(O, "]:cp, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 8: + // INITDP_2r + SStream_concat0(O, "]:dp, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 9: + // INITLR_l2r + SStream_concat0(O, "]:lr, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 10: + // INITPC_2r + SStream_concat0(O, "]:pc, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 11: + // INITSP_2r + SStream_concat0(O, "]:sp, "); + printOperand /* printOperand (+ ) */ (MI, 0, O); + return; + break; + case 12: + // LDAWDP_lru6, LDAWDP_ru6, LDWDP_lru6, LDWDP_ru6, STWDP_lru6, STWDP_ru6 + SStream_concat0(O, ", dp["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 13: + // LDAWSP_lru6, LDAWSP_ru6, LDWSP_lru6, LDWSP_ru6, STWSP_lru6, STWSP_ru6 + SStream_concat0(O, ", sp["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 14: + // LDWCP_lru6, LDWCP_ru6 + SStream_concat0(O, ", cp["); + printOperand /* printOperand (+ ) */ (MI, 1, O); + SStream_concat0(O, "]"); + return; + break; + case 15: + // SETEV_1r, SETV_1r + SStream_concat0(O, "], r11"); + return; + break; + case 16: + // TSETR_3r + SStream_concat0(O, "]:r"); + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 1, O); + return; + break; + } + + // Fragment 2 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 18) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADJCALLSTACKDOWN, EH_RETURN, LDAWFI, LDWFI, STWFI, ADD_2rus, ADD_3r, A... + printOperand /* printOperand (+ ) */ (MI, 1, O); + break; + case 1: + // BR_JT + printInlineJT /* printInlineJT (+ ) */ (MI, 0, O); + return; + break; + case 2: + // BR_JT32 + printInlineJT32 /* printInlineJT32 (+ ) */ (MI, 0, O); + return; + break; + case 3: + // ANDNOT_2r, CRC_l3r, INSHR_2r, SEXT_2r, SEXT_rus, ZEXT_2r, ZEXT_rus + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 4: + // CRC8_l4r, LADD_l5r, LSUB_l5r, OUTPW_l2rus + printOperand /* printOperand (+ ) */ (MI, 0, O); + SStream_concat0(O, ", "); + break; + } + + // Fragment 3 encoded into 3 bits for 8 unique commands. + switch ((Bits >> 21) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADJCALLSTACKDOWN, EH_RETURN, LDAWFI, LDWFI, STWFI, ANDNOT_2r, BITREV_l... + return; + break; + case 1: + // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, CRC_l3r, DIVS_l3r, DIV... + SStream_concat0(O, ", "); + break; + case 2: + // CRC8_l4r + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + return; + break; + case 3: + // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT... + SStream_concat0(O, "]"); + return; + break; + case 4: + // INPW_l2rus + SStream_concat0(O, "], "); + printOperand /* printOperand (+ ) */ (MI, 2, O); + return; + break; + case 5: + // LADD_l5r, LSUB_l5r, OUTPW_l2rus + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 6: + // LD16S_3r, LD8U_3r, LDA16F_l3r, LDAWF_l2rus, LDAWF_l3r, LDW_2rus, LDW_3... + SStream_concat0(O, "["); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "]"); + return; + break; + case 7: + // LDA16B_l3r, LDAWB_l2rus, LDAWB_l3r + SStream_concat0(O, "[-"); + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, "]"); + return; + break; + } + + // Fragment 4 encoded into 3 bits for 5 unique commands. + switch ((Bits >> 24) & 7) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ... + printOperand /* printOperand (+ ) */ (MI, 2, O); + break; + case 1: + // CRC_l3r + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 2: + // LADD_l5r, LSUB_l5r + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + return; + break; + case 3: + // LDIVU_l5r, MACCS_l4r, MACCU_l4r + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + break; + case 4: + // OUTPW_l2rus + return; + break; + } + + // Fragment 5 encoded into 2 bits for 4 unique commands. + switch ((Bits >> 27) & 3) { + default: + llvm_unreachable("Invalid command number."); + case 0: + // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ... + return; + break; + case 1: + // LDIVU_l5r + printOperand /* printOperand (+ ) */ (MI, 2, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + return; + break; + case 2: + // LMUL_l6r + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 3, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 4, O); + SStream_concat0(O, ", "); + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + case 3: + // MACCS_l4r, MACCU_l4r + printOperand /* printOperand (+ ) */ (MI, 5, O); + return; + break; + } +} + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +const char *getRegisterName(unsigned RegNo) { + assert(RegNo && RegNo < 17 && "Invalid register number!"); + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif + static const char AsmStrs[] = {/* 0 */ "r10\0" + /* 4 */ "r0\0" + /* 7 */ "r11\0" + /* 11 */ "r1\0" + /* 14 */ "r2\0" + /* 17 */ "r3\0" + /* 20 */ "r4\0" + /* 23 */ "r5\0" + /* 26 */ "r6\0" + /* 29 */ "r7\0" + /* 32 */ "r8\0" + /* 35 */ "r9\0" + /* 38 */ "cp\0" + /* 41 */ "dp\0" + /* 44 */ "sp\0" + /* 47 */ "lr\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + static const uint8_t RegAsmOffset[] = { + 38, 41, 47, 44, 4, 11, 14, 17, 20, 23, 26, 29, 32, 35, 0, 7, + }; + + assert(*(AsmStrs + RegAsmOffset[RegNo - 1]) && + "Invalid alt name index for register!"); + return AsmStrs + RegAsmOffset[RegNo - 1]; } +#endif +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); +static char *printAliasInstr(MCInst *MI, SStream *OS) { return false; } + +#endif // PRINT_ALIAS_INSTR +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +static const MCOperandInfo OperandInfo2[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo3[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo4[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo5[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo6[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo7[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo8[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo9[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, MCOI_TIED_TO /*0*/}, +}; +static const MCOperandInfo OperandInfo10[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo11[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo12[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo13[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo14[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo15[] = { + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo16[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo17[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo18[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo19[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo20[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo21[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo22[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo23[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo24[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo25[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo26[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo27[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo28[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo29[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo30[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo31[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo32[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo33[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo34[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo35[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo36[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo37[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo38[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo39[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, +}; +static const MCOperandInfo OperandInfo40[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo41[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, +}; +static const MCOperandInfo OperandInfo42[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_2, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo43[] = { + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_0, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, + {-1, 0, MCOI_OPERAND_GENERIC_1, 0}, +}; +static const MCOperandInfo OperandInfo44[] = { + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo45[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo46[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo47[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo48[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo49[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo50[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo51[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo52[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_UNKNOWN, 0}, +}; +static const MCOperandInfo OperandInfo53[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo54[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo55[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo56[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo57[] = { + {XCore_RRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo58[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo59[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*1*/}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo60[] = { + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, MCOI_TIED_TO /*0*/}, + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, +}; +static const MCOperandInfo OperandInfo61[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; +static const MCOperandInfo OperandInfo62[] = { + {-1, 0, MCOI_OPERAND_IMMEDIATE, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, + {XCore_GRRegsRegClassID, 0, MCOI_OPERAND_REGISTER, 0}, +}; + +extern const MCInstrDesc XCoreInsts[] = { + {1, OperandInfo2}, // Inst #0 = PHI + {0, NULL}, // Inst #1 = INLINEASM + {0, NULL}, // Inst #2 = INLINEASM_BR + {1, OperandInfo3}, // Inst #3 = CFI_INSTRUCTION + {1, OperandInfo3}, // Inst #4 = EH_LABEL + {1, OperandInfo3}, // Inst #5 = GC_LABEL + {1, OperandInfo3}, // Inst #6 = ANNOTATION_LABEL + {0, NULL}, // Inst #7 = KILL + {3, OperandInfo4}, // Inst #8 = EXTRACT_SUBREG + {4, OperandInfo5}, // Inst #9 = INSERT_SUBREG + {1, OperandInfo2}, // Inst #10 = IMPLICIT_DEF + {4, OperandInfo6}, // Inst #11 = SUBREG_TO_REG + {3, OperandInfo4}, // Inst #12 = COPY_TO_REGCLASS + {0, NULL}, // Inst #13 = DBG_VALUE + {0, NULL}, // Inst #14 = DBG_VALUE_LIST + {0, NULL}, // Inst #15 = DBG_INSTR_REF + {0, NULL}, // Inst #16 = DBG_PHI + {1, OperandInfo2}, // Inst #17 = DBG_LABEL + {2, OperandInfo7}, // Inst #18 = REG_SEQUENCE + {2, OperandInfo7}, // Inst #19 = COPY + {0, NULL}, // Inst #20 = BUNDLE + {1, OperandInfo3}, // Inst #21 = LIFETIME_START + {1, OperandInfo3}, // Inst #22 = LIFETIME_END + {4, OperandInfo8}, // Inst #23 = PSEUDO_PROBE + {2, OperandInfo9}, // Inst #24 = ARITH_FENCE + {2, OperandInfo10}, // Inst #25 = STACKMAP + {0, NULL}, // Inst #26 = FENTRY_CALL + {6, OperandInfo11}, // Inst #27 = PATCHPOINT + {1, OperandInfo12}, // Inst #28 = LOAD_STACK_GUARD + {1, OperandInfo3}, // Inst #29 = PREALLOCATED_SETUP + {3, OperandInfo13}, // Inst #30 = PREALLOCATED_ARG + {0, NULL}, // Inst #31 = STATEPOINT + {2, OperandInfo14}, // Inst #32 = LOCAL_ESCAPE + {1, OperandInfo2}, // Inst #33 = FAULTING_OP + {0, NULL}, // Inst #34 = PATCHABLE_OP + {0, NULL}, // Inst #35 = PATCHABLE_FUNCTION_ENTER + {0, NULL}, // Inst #36 = PATCHABLE_RET + {0, NULL}, // Inst #37 = PATCHABLE_FUNCTION_EXIT + {0, NULL}, // Inst #38 = PATCHABLE_TAIL_CALL + {2, OperandInfo15}, // Inst #39 = PATCHABLE_EVENT_CALL + {3, OperandInfo16}, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL + {0, NULL}, // Inst #41 = ICALL_BRANCH_FUNNEL + {3, OperandInfo17}, // Inst #42 = G_ASSERT_SEXT + {3, OperandInfo17}, // Inst #43 = G_ASSERT_ZEXT + {3, OperandInfo18}, // Inst #44 = G_ADD + {3, OperandInfo18}, // Inst #45 = G_SUB + {3, OperandInfo18}, // Inst #46 = G_MUL + {3, OperandInfo18}, // Inst #47 = G_SDIV + {3, OperandInfo18}, // Inst #48 = G_UDIV + {3, OperandInfo18}, // Inst #49 = G_SREM + {3, OperandInfo18}, // Inst #50 = G_UREM + {4, OperandInfo19}, // Inst #51 = G_SDIVREM + {4, OperandInfo19}, // Inst #52 = G_UDIVREM + {3, OperandInfo18}, // Inst #53 = G_AND + {3, OperandInfo18}, // Inst #54 = G_OR + {3, OperandInfo18}, // Inst #55 = G_XOR + {1, OperandInfo20}, // Inst #56 = G_IMPLICIT_DEF + {1, OperandInfo20}, // Inst #57 = G_PHI + {2, OperandInfo21}, // Inst #58 = G_FRAME_INDEX + {2, OperandInfo21}, // Inst #59 = G_GLOBAL_VALUE + {3, OperandInfo22}, // Inst #60 = G_EXTRACT + {2, OperandInfo23}, // Inst #61 = G_UNMERGE_VALUES + {4, OperandInfo24}, // Inst #62 = G_INSERT + {2, OperandInfo23}, // Inst #63 = G_MERGE_VALUES + {2, OperandInfo23}, // Inst #64 = G_BUILD_VECTOR + {2, OperandInfo23}, // Inst #65 = G_BUILD_VECTOR_TRUNC + {2, OperandInfo23}, // Inst #66 = G_CONCAT_VECTORS + {2, OperandInfo23}, // Inst #67 = G_PTRTOINT + {2, OperandInfo23}, // Inst #68 = G_INTTOPTR + {2, OperandInfo23}, // Inst #69 = G_BITCAST + {2, OperandInfo25}, // Inst #70 = G_FREEZE + {2, OperandInfo25}, // Inst #71 = G_INTRINSIC_TRUNC + {2, OperandInfo25}, // Inst #72 = G_INTRINSIC_ROUND + {2, OperandInfo23}, // Inst #73 = G_INTRINSIC_LRINT + {2, OperandInfo25}, // Inst #74 = G_INTRINSIC_ROUNDEVEN + {1, OperandInfo20}, // Inst #75 = G_READCYCLECOUNTER + {2, OperandInfo23}, // Inst #76 = G_LOAD + {2, OperandInfo23}, // Inst #77 = G_SEXTLOAD + {2, OperandInfo23}, // Inst #78 = G_ZEXTLOAD + {5, OperandInfo26}, // Inst #79 = G_INDEXED_LOAD + {5, OperandInfo26}, // Inst #80 = G_INDEXED_SEXTLOAD + {5, OperandInfo26}, // Inst #81 = G_INDEXED_ZEXTLOAD + {2, OperandInfo23}, // Inst #82 = G_STORE + {5, OperandInfo27}, // Inst #83 = G_INDEXED_STORE + {5, OperandInfo28}, // Inst #84 = G_ATOMIC_CMPXCHG_WITH_SUCCESS + {4, OperandInfo29}, // Inst #85 = G_ATOMIC_CMPXCHG + {3, OperandInfo30}, // Inst #86 = G_ATOMICRMW_XCHG + {3, OperandInfo30}, // Inst #87 = G_ATOMICRMW_ADD + {3, OperandInfo30}, // Inst #88 = G_ATOMICRMW_SUB + {3, OperandInfo30}, // Inst #89 = G_ATOMICRMW_AND + {3, OperandInfo30}, // Inst #90 = G_ATOMICRMW_NAND + {3, OperandInfo30}, // Inst #91 = G_ATOMICRMW_OR + {3, OperandInfo30}, // Inst #92 = G_ATOMICRMW_XOR + {3, OperandInfo30}, // Inst #93 = G_ATOMICRMW_MAX + {3, OperandInfo30}, // Inst #94 = G_ATOMICRMW_MIN + {3, OperandInfo30}, // Inst #95 = G_ATOMICRMW_UMAX + {3, OperandInfo30}, // Inst #96 = G_ATOMICRMW_UMIN + {3, OperandInfo30}, // Inst #97 = G_ATOMICRMW_FADD + {3, OperandInfo30}, // Inst #98 = G_ATOMICRMW_FSUB + {2, OperandInfo10}, // Inst #99 = G_FENCE + {2, OperandInfo21}, // Inst #100 = G_BRCOND + {1, OperandInfo20}, // Inst #101 = G_BRINDIRECT + {1, OperandInfo2}, // Inst #102 = G_INTRINSIC + {1, OperandInfo2}, // Inst #103 = G_INTRINSIC_W_SIDE_EFFECTS + {2, OperandInfo23}, // Inst #104 = G_ANYEXT + {2, OperandInfo23}, // Inst #105 = G_TRUNC + {2, OperandInfo21}, // Inst #106 = G_CONSTANT + {2, OperandInfo21}, // Inst #107 = G_FCONSTANT + {1, OperandInfo20}, // Inst #108 = G_VASTART + {3, OperandInfo31}, // Inst #109 = G_VAARG + {2, OperandInfo23}, // Inst #110 = G_SEXT + {3, OperandInfo17}, // Inst #111 = G_SEXT_INREG + {2, OperandInfo23}, // Inst #112 = G_ZEXT + {3, OperandInfo32}, // Inst #113 = G_SHL + {3, OperandInfo32}, // Inst #114 = G_LSHR + {3, OperandInfo32}, // Inst #115 = G_ASHR + {4, OperandInfo33}, // Inst #116 = G_FSHL + {4, OperandInfo33}, // Inst #117 = G_FSHR + {3, OperandInfo32}, // Inst #118 = G_ROTR + {3, OperandInfo32}, // Inst #119 = G_ROTL + {4, OperandInfo34}, // Inst #120 = G_ICMP + {4, OperandInfo34}, // Inst #121 = G_FCMP + {4, OperandInfo29}, // Inst #122 = G_SELECT + {4, OperandInfo29}, // Inst #123 = G_UADDO + {5, OperandInfo35}, // Inst #124 = G_UADDE + {4, OperandInfo29}, // Inst #125 = G_USUBO + {5, OperandInfo35}, // Inst #126 = G_USUBE + {4, OperandInfo29}, // Inst #127 = G_SADDO + {5, OperandInfo35}, // Inst #128 = G_SADDE + {4, OperandInfo29}, // Inst #129 = G_SSUBO + {5, OperandInfo35}, // Inst #130 = G_SSUBE + {4, OperandInfo29}, // Inst #131 = G_UMULO + {4, OperandInfo29}, // Inst #132 = G_SMULO + {3, OperandInfo18}, // Inst #133 = G_UMULH + {3, OperandInfo18}, // Inst #134 = G_SMULH + {3, OperandInfo18}, // Inst #135 = G_UADDSAT + {3, OperandInfo18}, // Inst #136 = G_SADDSAT + {3, OperandInfo18}, // Inst #137 = G_USUBSAT + {3, OperandInfo18}, // Inst #138 = G_SSUBSAT + {3, OperandInfo32}, // Inst #139 = G_USHLSAT + {3, OperandInfo32}, // Inst #140 = G_SSHLSAT + {4, OperandInfo36}, // Inst #141 = G_SMULFIX + {4, OperandInfo36}, // Inst #142 = G_UMULFIX + {4, OperandInfo36}, // Inst #143 = G_SMULFIXSAT + {4, OperandInfo36}, // Inst #144 = G_UMULFIXSAT + {4, OperandInfo36}, // Inst #145 = G_SDIVFIX + {4, OperandInfo36}, // Inst #146 = G_UDIVFIX + {4, OperandInfo36}, // Inst #147 = G_SDIVFIXSAT + {4, OperandInfo36}, // Inst #148 = G_UDIVFIXSAT + {3, OperandInfo18}, // Inst #149 = G_FADD + {3, OperandInfo18}, // Inst #150 = G_FSUB + {3, OperandInfo18}, // Inst #151 = G_FMUL + {4, OperandInfo19}, // Inst #152 = G_FMA + {4, OperandInfo19}, // Inst #153 = G_FMAD + {3, OperandInfo18}, // Inst #154 = G_FDIV + {3, OperandInfo18}, // Inst #155 = G_FREM + {3, OperandInfo18}, // Inst #156 = G_FPOW + {3, OperandInfo32}, // Inst #157 = G_FPOWI + {2, OperandInfo25}, // Inst #158 = G_FEXP + {2, OperandInfo25}, // Inst #159 = G_FEXP2 + {2, OperandInfo25}, // Inst #160 = G_FLOG + {2, OperandInfo25}, // Inst #161 = G_FLOG2 + {2, OperandInfo25}, // Inst #162 = G_FLOG10 + {2, OperandInfo25}, // Inst #163 = G_FNEG + {2, OperandInfo23}, // Inst #164 = G_FPEXT + {2, OperandInfo23}, // Inst #165 = G_FPTRUNC + {2, OperandInfo23}, // Inst #166 = G_FPTOSI + {2, OperandInfo23}, // Inst #167 = G_FPTOUI + {2, OperandInfo23}, // Inst #168 = G_SITOFP + {2, OperandInfo23}, // Inst #169 = G_UITOFP + {2, OperandInfo25}, // Inst #170 = G_FABS + {3, OperandInfo32}, // Inst #171 = G_FCOPYSIGN + {2, OperandInfo25}, // Inst #172 = G_FCANONICALIZE + {3, OperandInfo18}, // Inst #173 = G_FMINNUM + {3, OperandInfo18}, // Inst #174 = G_FMAXNUM + {3, OperandInfo18}, // Inst #175 = G_FMINNUM_IEEE + {3, OperandInfo18}, // Inst #176 = G_FMAXNUM_IEEE + {3, OperandInfo18}, // Inst #177 = G_FMINIMUM + {3, OperandInfo18}, // Inst #178 = G_FMAXIMUM + {3, OperandInfo32}, // Inst #179 = G_PTR_ADD + {3, OperandInfo32}, // Inst #180 = G_PTRMASK + {3, OperandInfo18}, // Inst #181 = G_SMIN + {3, OperandInfo18}, // Inst #182 = G_SMAX + {3, OperandInfo18}, // Inst #183 = G_UMIN + {3, OperandInfo18}, // Inst #184 = G_UMAX + {2, OperandInfo25}, // Inst #185 = G_ABS + {2, OperandInfo23}, // Inst #186 = G_LROUND + {2, OperandInfo23}, // Inst #187 = G_LLROUND + {1, OperandInfo2}, // Inst #188 = G_BR + {3, OperandInfo37}, // Inst #189 = G_BRJT + {4, OperandInfo38}, // Inst #190 = G_INSERT_VECTOR_ELT + {3, OperandInfo39}, // Inst #191 = G_EXTRACT_VECTOR_ELT + {4, OperandInfo40}, // Inst #192 = G_SHUFFLE_VECTOR + {2, OperandInfo23}, // Inst #193 = G_CTTZ + {2, OperandInfo23}, // Inst #194 = G_CTTZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #195 = G_CTLZ + {2, OperandInfo23}, // Inst #196 = G_CTLZ_ZERO_UNDEF + {2, OperandInfo23}, // Inst #197 = G_CTPOP + {2, OperandInfo25}, // Inst #198 = G_BSWAP + {2, OperandInfo25}, // Inst #199 = G_BITREVERSE + {2, OperandInfo25}, // Inst #200 = G_FCEIL + {2, OperandInfo25}, // Inst #201 = G_FCOS + {2, OperandInfo25}, // Inst #202 = G_FSIN + {2, OperandInfo25}, // Inst #203 = G_FSQRT + {2, OperandInfo25}, // Inst #204 = G_FFLOOR + {2, OperandInfo25}, // Inst #205 = G_FRINT + {2, OperandInfo25}, // Inst #206 = G_FNEARBYINT + {2, OperandInfo23}, // Inst #207 = G_ADDRSPACE_CAST + {2, OperandInfo21}, // Inst #208 = G_BLOCK_ADDR + {2, OperandInfo21}, // Inst #209 = G_JUMP_TABLE + {3, OperandInfo22}, // Inst #210 = G_DYN_STACKALLOC + {3, OperandInfo18}, // Inst #211 = G_STRICT_FADD + {3, OperandInfo18}, // Inst #212 = G_STRICT_FSUB + {3, OperandInfo18}, // Inst #213 = G_STRICT_FMUL + {3, OperandInfo18}, // Inst #214 = G_STRICT_FDIV + {3, OperandInfo18}, // Inst #215 = G_STRICT_FREM + {4, OperandInfo19}, // Inst #216 = G_STRICT_FMA + {2, OperandInfo25}, // Inst #217 = G_STRICT_FSQRT + {2, OperandInfo21}, // Inst #218 = G_READ_REGISTER + {2, OperandInfo41}, // Inst #219 = G_WRITE_REGISTER + {4, OperandInfo42}, // Inst #220 = G_MEMCPY + {3, OperandInfo39}, // Inst #221 = G_MEMCPY_INLINE + {4, OperandInfo42}, // Inst #222 = G_MEMMOVE + {4, OperandInfo42}, // Inst #223 = G_MEMSET + {3, OperandInfo22}, // Inst #224 = G_BZERO + {3, OperandInfo39}, // Inst #225 = G_VECREDUCE_SEQ_FADD + {3, OperandInfo39}, // Inst #226 = G_VECREDUCE_SEQ_FMUL + {2, OperandInfo23}, // Inst #227 = G_VECREDUCE_FADD + {2, OperandInfo23}, // Inst #228 = G_VECREDUCE_FMUL + {2, OperandInfo23}, // Inst #229 = G_VECREDUCE_FMAX + {2, OperandInfo23}, // Inst #230 = G_VECREDUCE_FMIN + {2, OperandInfo23}, // Inst #231 = G_VECREDUCE_ADD + {2, OperandInfo23}, // Inst #232 = G_VECREDUCE_MUL + {2, OperandInfo23}, // Inst #233 = G_VECREDUCE_AND + {2, OperandInfo23}, // Inst #234 = G_VECREDUCE_OR + {2, OperandInfo23}, // Inst #235 = G_VECREDUCE_XOR + {2, OperandInfo23}, // Inst #236 = G_VECREDUCE_SMAX + {2, OperandInfo23}, // Inst #237 = G_VECREDUCE_SMIN + {2, OperandInfo23}, // Inst #238 = G_VECREDUCE_UMAX + {2, OperandInfo23}, // Inst #239 = G_VECREDUCE_UMIN + {4, OperandInfo43}, // Inst #240 = G_SBFX + {4, OperandInfo43}, // Inst #241 = G_UBFX + {2, OperandInfo10}, // Inst #242 = ADJCALLSTACKDOWN + {2, OperandInfo10}, // Inst #243 = ADJCALLSTACKUP + {2, OperandInfo44}, // Inst #244 = BR_JT + {2, OperandInfo44}, // Inst #245 = BR_JT32 + {2, OperandInfo45}, // Inst #246 = EH_RETURN + {1, OperandInfo46}, // Inst #247 = FRAME_TO_ARGS_OFFSET + {0, NULL}, // Inst #248 = Int_MemBarrier + {3, OperandInfo47}, // Inst #249 = LDAWFI + {3, OperandInfo47}, // Inst #250 = LDWFI + {4, OperandInfo48}, // Inst #251 = SELECT_CC + {3, OperandInfo47}, // Inst #252 = STWFI + {3, OperandInfo49}, // Inst #253 = ADD_2rus + {3, OperandInfo50}, // Inst #254 = ADD_3r + {3, OperandInfo51}, // Inst #255 = ANDNOT_2r + {3, OperandInfo50}, // Inst #256 = AND_3r + {3, OperandInfo49}, // Inst #257 = ASHR_l2rus + {3, OperandInfo50}, // Inst #258 = ASHR_l3r + {1, OperandInfo46}, // Inst #259 = BAU_1r + {2, OperandInfo45}, // Inst #260 = BITREV_l2r + {1, OperandInfo3}, // Inst #261 = BLACP_lu10 + {1, OperandInfo3}, // Inst #262 = BLACP_u10 + {1, OperandInfo3}, // Inst #263 = BLAT_lu6 + {1, OperandInfo3}, // Inst #264 = BLAT_u6 + {1, OperandInfo46}, // Inst #265 = BLA_1r + {1, OperandInfo2}, // Inst #266 = BLRB_lu10 + {1, OperandInfo2}, // Inst #267 = BLRB_u10 + {1, OperandInfo2}, // Inst #268 = BLRF_lu10 + {1, OperandInfo2}, // Inst #269 = BLRF_u10 + {2, OperandInfo52}, // Inst #270 = BRBF_lru6 + {2, OperandInfo52}, // Inst #271 = BRBF_ru6 + {2, OperandInfo52}, // Inst #272 = BRBT_lru6 + {2, OperandInfo52}, // Inst #273 = BRBT_ru6 + {1, OperandInfo2}, // Inst #274 = BRBU_lu6 + {1, OperandInfo2}, // Inst #275 = BRBU_u6 + {2, OperandInfo52}, // Inst #276 = BRFF_lru6 + {2, OperandInfo52}, // Inst #277 = BRFF_ru6 + {2, OperandInfo52}, // Inst #278 = BRFT_lru6 + {2, OperandInfo52}, // Inst #279 = BRFT_ru6 + {1, OperandInfo2}, // Inst #280 = BRFU_lu6 + {1, OperandInfo2}, // Inst #281 = BRFU_u6 + {1, OperandInfo46}, // Inst #282 = BRU_1r + {2, OperandInfo45}, // Inst #283 = BYTEREV_l2r + {2, OperandInfo45}, // Inst #284 = CHKCT_2r + {2, OperandInfo53}, // Inst #285 = CHKCT_rus + {0, NULL}, // Inst #286 = CLRE_0R + {1, OperandInfo46}, // Inst #287 = CLRPT_1R + {1, OperandInfo3}, // Inst #288 = CLRSR_branch_lu6 + {1, OperandInfo3}, // Inst #289 = CLRSR_branch_u6 + {1, OperandInfo3}, // Inst #290 = CLRSR_lu6 + {1, OperandInfo3}, // Inst #291 = CLRSR_u6 + {2, OperandInfo45}, // Inst #292 = CLZ_l2r + {5, OperandInfo54}, // Inst #293 = CRC8_l4r + {4, OperandInfo55}, // Inst #294 = CRC_l3r + {0, NULL}, // Inst #295 = DCALL_0R + {0, NULL}, // Inst #296 = DENTSP_0R + {1, OperandInfo46}, // Inst #297 = DGETREG_1r + {3, OperandInfo50}, // Inst #298 = DIVS_l3r + {3, OperandInfo50}, // Inst #299 = DIVU_l3r + {0, NULL}, // Inst #300 = DRESTSP_0R + {0, NULL}, // Inst #301 = DRET_0R + {1, OperandInfo46}, // Inst #302 = ECALLF_1r + {1, OperandInfo46}, // Inst #303 = ECALLT_1r + {1, OperandInfo46}, // Inst #304 = EDU_1r + {2, OperandInfo45}, // Inst #305 = EEF_2r + {2, OperandInfo45}, // Inst #306 = EET_2r + {1, OperandInfo46}, // Inst #307 = EEU_1r + {2, OperandInfo45}, // Inst #308 = ENDIN_2r + {1, OperandInfo3}, // Inst #309 = ENTSP_lu6 + {1, OperandInfo3}, // Inst #310 = ENTSP_u6 + {3, OperandInfo49}, // Inst #311 = EQ_2rus + {3, OperandInfo50}, // Inst #312 = EQ_3r + {1, OperandInfo3}, // Inst #313 = EXTDP_lu6 + {1, OperandInfo3}, // Inst #314 = EXTDP_u6 + {1, OperandInfo3}, // Inst #315 = EXTSP_lu6 + {1, OperandInfo3}, // Inst #316 = EXTSP_u6 + {1, OperandInfo46}, // Inst #317 = FREER_1r + {0, NULL}, // Inst #318 = FREET_0R + {2, OperandInfo45}, // Inst #319 = GETD_l2r + {0, NULL}, // Inst #320 = GETED_0R + {0, NULL}, // Inst #321 = GETET_0R + {0, NULL}, // Inst #322 = GETID_0R + {0, NULL}, // Inst #323 = GETKEP_0R + {0, NULL}, // Inst #324 = GETKSP_0R + {2, OperandInfo45}, // Inst #325 = GETN_l2r + {2, OperandInfo45}, // Inst #326 = GETPS_l2r + {2, OperandInfo53}, // Inst #327 = GETR_rus + {1, OperandInfo3}, // Inst #328 = GETSR_lu6 + {1, OperandInfo3}, // Inst #329 = GETSR_u6 + {2, OperandInfo45}, // Inst #330 = GETST_2r + {2, OperandInfo45}, // Inst #331 = GETTS_2r + {2, OperandInfo45}, // Inst #332 = INCT_2r + {2, OperandInfo45}, // Inst #333 = INITCP_2r + {2, OperandInfo45}, // Inst #334 = INITDP_2r + {2, OperandInfo45}, // Inst #335 = INITLR_l2r + {2, OperandInfo45}, // Inst #336 = INITPC_2r + {2, OperandInfo45}, // Inst #337 = INITSP_2r + {3, OperandInfo49}, // Inst #338 = INPW_l2rus + {3, OperandInfo51}, // Inst #339 = INSHR_2r + {2, OperandInfo45}, // Inst #340 = INT_2r + {2, OperandInfo45}, // Inst #341 = IN_2r + {1, OperandInfo46}, // Inst #342 = KCALL_1r + {1, OperandInfo3}, // Inst #343 = KCALL_lu6 + {1, OperandInfo3}, // Inst #344 = KCALL_u6 + {1, OperandInfo3}, // Inst #345 = KENTSP_lu6 + {1, OperandInfo3}, // Inst #346 = KENTSP_u6 + {1, OperandInfo3}, // Inst #347 = KRESTSP_lu6 + {1, OperandInfo3}, // Inst #348 = KRESTSP_u6 + {0, NULL}, // Inst #349 = KRET_0R + {5, OperandInfo56}, // Inst #350 = LADD_l5r + {3, OperandInfo50}, // Inst #351 = LD16S_3r + {3, OperandInfo50}, // Inst #352 = LD8U_3r + {3, OperandInfo50}, // Inst #353 = LDA16B_l3r + {3, OperandInfo50}, // Inst #354 = LDA16F_l3r + {1, OperandInfo2}, // Inst #355 = LDAPB_lu10 + {1, OperandInfo2}, // Inst #356 = LDAPB_u10 + {1, OperandInfo2}, // Inst #357 = LDAPF_lu10 + {1, OperandInfo2}, // Inst #358 = LDAPF_lu10_ba + {1, OperandInfo2}, // Inst #359 = LDAPF_u10 + {3, OperandInfo49}, // Inst #360 = LDAWB_l2rus + {3, OperandInfo50}, // Inst #361 = LDAWB_l3r + {1, OperandInfo3}, // Inst #362 = LDAWCP_lu6 + {1, OperandInfo3}, // Inst #363 = LDAWCP_u6 + {2, OperandInfo57}, // Inst #364 = LDAWDP_lru6 + {2, OperandInfo57}, // Inst #365 = LDAWDP_ru6 + {3, OperandInfo49}, // Inst #366 = LDAWF_l2rus + {3, OperandInfo50}, // Inst #367 = LDAWF_l3r + {2, OperandInfo57}, // Inst #368 = LDAWSP_lru6 + {2, OperandInfo57}, // Inst #369 = LDAWSP_ru6 + {2, OperandInfo57}, // Inst #370 = LDC_lru6 + {2, OperandInfo57}, // Inst #371 = LDC_ru6 + {0, NULL}, // Inst #372 = LDET_0R + {5, OperandInfo56}, // Inst #373 = LDIVU_l5r + {0, NULL}, // Inst #374 = LDSED_0R + {0, NULL}, // Inst #375 = LDSPC_0R + {0, NULL}, // Inst #376 = LDSSR_0R + {2, OperandInfo57}, // Inst #377 = LDWCP_lru6 + {1, OperandInfo3}, // Inst #378 = LDWCP_lu10 + {2, OperandInfo57}, // Inst #379 = LDWCP_ru6 + {1, OperandInfo3}, // Inst #380 = LDWCP_u10 + {2, OperandInfo57}, // Inst #381 = LDWDP_lru6 + {2, OperandInfo57}, // Inst #382 = LDWDP_ru6 + {2, OperandInfo57}, // Inst #383 = LDWSP_lru6 + {2, OperandInfo57}, // Inst #384 = LDWSP_ru6 + {3, OperandInfo49}, // Inst #385 = LDW_2rus + {3, OperandInfo50}, // Inst #386 = LDW_3r + {6, OperandInfo58}, // Inst #387 = LMUL_l6r + {3, OperandInfo50}, // Inst #388 = LSS_3r + {5, OperandInfo56}, // Inst #389 = LSUB_l5r + {3, OperandInfo50}, // Inst #390 = LSU_3r + {6, OperandInfo59}, // Inst #391 = MACCS_l4r + {6, OperandInfo59}, // Inst #392 = MACCU_l4r + {1, OperandInfo46}, // Inst #393 = MJOIN_1r + {2, OperandInfo45}, // Inst #394 = MKMSK_2r + {2, OperandInfo53}, // Inst #395 = MKMSK_rus + {1, OperandInfo46}, // Inst #396 = MSYNC_1r + {3, OperandInfo50}, // Inst #397 = MUL_l3r + {2, OperandInfo45}, // Inst #398 = NEG + {2, OperandInfo45}, // Inst #399 = NOT + {3, OperandInfo50}, // Inst #400 = OR_3r + {2, OperandInfo45}, // Inst #401 = OUTCT_2r + {2, OperandInfo53}, // Inst #402 = OUTCT_rus + {3, OperandInfo49}, // Inst #403 = OUTPW_l2rus + {3, OperandInfo51}, // Inst #404 = OUTSHR_2r + {2, OperandInfo45}, // Inst #405 = OUTT_2r + {2, OperandInfo45}, // Inst #406 = OUT_2r + {2, OperandInfo45}, // Inst #407 = PEEK_2r + {3, OperandInfo50}, // Inst #408 = REMS_l3r + {3, OperandInfo50}, // Inst #409 = REMU_l3r + {1, OperandInfo3}, // Inst #410 = RETSP_lu6 + {1, OperandInfo3}, // Inst #411 = RETSP_u6 + {2, OperandInfo45}, // Inst #412 = SETCLK_l2r + {1, OperandInfo46}, // Inst #413 = SETCP_1r + {2, OperandInfo45}, // Inst #414 = SETC_l2r + {2, OperandInfo53}, // Inst #415 = SETC_lru6 + {2, OperandInfo53}, // Inst #416 = SETC_ru6 + {1, OperandInfo46}, // Inst #417 = SETDP_1r + {2, OperandInfo45}, // Inst #418 = SETD_2r + {1, OperandInfo46}, // Inst #419 = SETEV_1r + {0, NULL}, // Inst #420 = SETKEP_0R + {2, OperandInfo45}, // Inst #421 = SETN_l2r + {2, OperandInfo45}, // Inst #422 = SETPSC_2r + {2, OperandInfo45}, // Inst #423 = SETPS_l2r + {2, OperandInfo45}, // Inst #424 = SETPT_2r + {2, OperandInfo45}, // Inst #425 = SETRDY_l2r + {1, OperandInfo46}, // Inst #426 = SETSP_1r + {1, OperandInfo3}, // Inst #427 = SETSR_branch_lu6 + {1, OperandInfo3}, // Inst #428 = SETSR_branch_u6 + {1, OperandInfo3}, // Inst #429 = SETSR_lu6 + {1, OperandInfo3}, // Inst #430 = SETSR_u6 + {2, OperandInfo45}, // Inst #431 = SETTW_l2r + {1, OperandInfo46}, // Inst #432 = SETV_1r + {3, OperandInfo51}, // Inst #433 = SEXT_2r + {3, OperandInfo60}, // Inst #434 = SEXT_rus + {3, OperandInfo49}, // Inst #435 = SHL_2rus + {3, OperandInfo50}, // Inst #436 = SHL_3r + {3, OperandInfo49}, // Inst #437 = SHR_2rus + {3, OperandInfo50}, // Inst #438 = SHR_3r + {0, NULL}, // Inst #439 = SSYNC_0r + {3, OperandInfo50}, // Inst #440 = ST16_l3r + {3, OperandInfo50}, // Inst #441 = ST8_l3r + {0, NULL}, // Inst #442 = STET_0R + {0, NULL}, // Inst #443 = STSED_0R + {0, NULL}, // Inst #444 = STSPC_0R + {0, NULL}, // Inst #445 = STSSR_0R + {2, OperandInfo57}, // Inst #446 = STWDP_lru6 + {2, OperandInfo57}, // Inst #447 = STWDP_ru6 + {2, OperandInfo57}, // Inst #448 = STWSP_lru6 + {2, OperandInfo57}, // Inst #449 = STWSP_ru6 + {3, OperandInfo49}, // Inst #450 = STW_2rus + {3, OperandInfo50}, // Inst #451 = STW_l3r + {3, OperandInfo49}, // Inst #452 = SUB_2rus + {3, OperandInfo50}, // Inst #453 = SUB_3r + {1, OperandInfo46}, // Inst #454 = SYNCR_1r + {2, OperandInfo45}, // Inst #455 = TESTCT_2r + {2, OperandInfo45}, // Inst #456 = TESTLCL_l2r + {2, OperandInfo45}, // Inst #457 = TESTWCT_2r + {2, OperandInfo61}, // Inst #458 = TSETMR_2r + {3, OperandInfo62}, // Inst #459 = TSETR_3r + {1, OperandInfo46}, // Inst #460 = TSTART_1R + {1, OperandInfo46}, // Inst #461 = WAITEF_1R + {1, OperandInfo46}, // Inst #462 = WAITET_1R + {0, NULL}, // Inst #463 = WAITEU_0R + {3, OperandInfo50}, // Inst #464 = XOR_l3r + {3, OperandInfo51}, // Inst #465 = ZEXT_2r + {3, OperandInfo60}, // Inst #466 = ZEXT_rus +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Woverlength-strings" +#endif +extern const char XCoreInstrNameData[] = { + /* 0 */ "G_FLOG10\0" + /* 9 */ "LDAPB_u10\0" + /* 19 */ "BLRB_u10\0" + /* 28 */ "LDAPF_u10\0" + /* 38 */ "BLRF_u10\0" + /* 47 */ "BLACP_u10\0" + /* 57 */ "LDWCP_u10\0" + /* 67 */ "LDAPB_lu10\0" + /* 78 */ "BLRB_lu10\0" + /* 88 */ "LDAPF_lu10\0" + /* 99 */ "BLRF_lu10\0" + /* 109 */ "BLACP_lu10\0" + /* 120 */ "LDWCP_lu10\0" + /* 131 */ "BR_JT32\0" + /* 139 */ "G_FLOG2\0" + /* 147 */ "G_FEXP2\0" + /* 155 */ "KCALL_u6\0" + /* 164 */ "LDAWCP_u6\0" + /* 174 */ "EXTDP_u6\0" + /* 183 */ "RETSP_u6\0" + /* 192 */ "KENTSP_u6\0" + /* 202 */ "KRESTSP_u6\0" + /* 213 */ "EXTSP_u6\0" + /* 222 */ "CLRSR_u6\0" + /* 231 */ "GETSR_u6\0" + /* 240 */ "SETSR_u6\0" + /* 249 */ "BLAT_u6\0" + /* 257 */ "BRBU_u6\0" + /* 265 */ "BRFU_u6\0" + /* 273 */ "CLRSR_branch_u6\0" + /* 289 */ "SETSR_branch_u6\0" + /* 305 */ "KCALL_lu6\0" + /* 315 */ "LDAWCP_lu6\0" + /* 326 */ "EXTDP_lu6\0" + /* 336 */ "RETSP_lu6\0" + /* 346 */ "KENTSP_lu6\0" + /* 357 */ "KRESTSP_lu6\0" + /* 369 */ "EXTSP_lu6\0" + /* 379 */ "CLRSR_lu6\0" + /* 389 */ "GETSR_lu6\0" + /* 399 */ "SETSR_lu6\0" + /* 409 */ "BLAT_lu6\0" + /* 418 */ "BRBU_lu6\0" + /* 427 */ "BRFU_lu6\0" + /* 436 */ "CLRSR_branch_lu6\0" + /* 453 */ "SETSR_branch_lu6\0" + /* 470 */ "LDC_ru6\0" + /* 478 */ "SETC_ru6\0" + /* 487 */ "BRBF_ru6\0" + /* 496 */ "BRFF_ru6\0" + /* 505 */ "LDWCP_ru6\0" + /* 515 */ "LDAWDP_ru6\0" + /* 526 */ "LDWDP_ru6\0" + /* 536 */ "STWDP_ru6\0" + /* 546 */ "LDAWSP_ru6\0" + /* 557 */ "LDWSP_ru6\0" + /* 567 */ "STWSP_ru6\0" + /* 577 */ "BRBT_ru6\0" + /* 586 */ "BRFT_ru6\0" + /* 595 */ "LDC_lru6\0" + /* 604 */ "SETC_lru6\0" + /* 614 */ "BRBF_lru6\0" + /* 624 */ "BRFF_lru6\0" + /* 634 */ "LDWCP_lru6\0" + /* 645 */ "LDAWDP_lru6\0" + /* 657 */ "LDWDP_lru6\0" + /* 668 */ "STWDP_lru6\0" + /* 679 */ "LDAWSP_lru6\0" + /* 691 */ "LDWSP_lru6\0" + /* 702 */ "STWSP_lru6\0" + /* 713 */ "BRBT_lru6\0" + /* 723 */ "BRFT_lru6\0" + /* 733 */ "G_FMA\0" + /* 739 */ "G_STRICT_FMA\0" + /* 752 */ "G_FSUB\0" + /* 759 */ "G_STRICT_FSUB\0" + /* 773 */ "G_ATOMICRMW_FSUB\0" + /* 790 */ "G_SUB\0" + /* 796 */ "G_ATOMICRMW_SUB\0" + /* 812 */ "SELECT_CC\0" + /* 822 */ "G_INTRINSIC\0" + /* 834 */ "G_FPTRUNC\0" + /* 844 */ "G_INTRINSIC_TRUNC\0" + /* 862 */ "G_TRUNC\0" + /* 870 */ "G_BUILD_VECTOR_TRUNC\0" + /* 891 */ "G_DYN_STACKALLOC\0" + /* 908 */ "G_FMAD\0" + /* 915 */ "G_INDEXED_SEXTLOAD\0" + /* 934 */ "G_SEXTLOAD\0" + /* 945 */ "G_INDEXED_ZEXTLOAD\0" + /* 964 */ "G_ZEXTLOAD\0" + /* 975 */ "G_INDEXED_LOAD\0" + /* 990 */ "G_LOAD\0" + /* 997 */ "G_VECREDUCE_FADD\0" + /* 1014 */ "G_FADD\0" + /* 1021 */ "G_VECREDUCE_SEQ_FADD\0" + /* 1042 */ "G_STRICT_FADD\0" + /* 1056 */ "G_ATOMICRMW_FADD\0" + /* 1073 */ "G_VECREDUCE_ADD\0" + /* 1089 */ "G_ADD\0" + /* 1095 */ "G_PTR_ADD\0" + /* 1105 */ "G_ATOMICRMW_ADD\0" + /* 1121 */ "G_ATOMICRMW_NAND\0" + /* 1138 */ "G_VECREDUCE_AND\0" + /* 1154 */ "G_AND\0" + /* 1160 */ "G_ATOMICRMW_AND\0" + /* 1176 */ "LIFETIME_END\0" + /* 1189 */ "G_BRCOND\0" + /* 1198 */ "G_LLROUND\0" + /* 1208 */ "G_LROUND\0" + /* 1217 */ "G_INTRINSIC_ROUND\0" + /* 1235 */ "LOAD_STACK_GUARD\0" + /* 1252 */ "PSEUDO_PROBE\0" + /* 1265 */ "G_SSUBE\0" + /* 1273 */ "G_USUBE\0" + /* 1281 */ "G_FENCE\0" + /* 1289 */ "ARITH_FENCE\0" + /* 1301 */ "REG_SEQUENCE\0" + /* 1314 */ "G_SADDE\0" + /* 1322 */ "G_UADDE\0" + /* 1330 */ "G_FMINNUM_IEEE\0" + /* 1345 */ "G_FMAXNUM_IEEE\0" + /* 1360 */ "G_JUMP_TABLE\0" + /* 1373 */ "BUNDLE\0" + /* 1380 */ "G_MEMCPY_INLINE\0" + /* 1396 */ "LOCAL_ESCAPE\0" + /* 1409 */ "G_INDEXED_STORE\0" + /* 1425 */ "G_STORE\0" + /* 1433 */ "G_BITREVERSE\0" + /* 1446 */ "DBG_VALUE\0" + /* 1456 */ "G_GLOBAL_VALUE\0" + /* 1471 */ "G_MEMMOVE\0" + /* 1481 */ "G_FREEZE\0" + /* 1490 */ "G_FCANONICALIZE\0" + /* 1506 */ "G_CTLZ_ZERO_UNDEF\0" + /* 1524 */ "G_CTTZ_ZERO_UNDEF\0" + /* 1542 */ "G_IMPLICIT_DEF\0" + /* 1557 */ "DBG_INSTR_REF\0" + /* 1571 */ "G_FNEG\0" + /* 1578 */ "EXTRACT_SUBREG\0" + /* 1593 */ "INSERT_SUBREG\0" + /* 1607 */ "G_SEXT_INREG\0" + /* 1620 */ "SUBREG_TO_REG\0" + /* 1634 */ "G_ATOMIC_CMPXCHG\0" + /* 1651 */ "G_ATOMICRMW_XCHG\0" + /* 1668 */ "G_FLOG\0" + /* 1675 */ "G_VAARG\0" + /* 1683 */ "PREALLOCATED_ARG\0" + /* 1700 */ "G_SMULH\0" + /* 1708 */ "G_UMULH\0" + /* 1716 */ "LDAWFI\0" + /* 1723 */ "LDWFI\0" + /* 1729 */ "STWFI\0" + /* 1735 */ "DBG_PHI\0" + /* 1743 */ "G_FPTOSI\0" + /* 1752 */ "G_FPTOUI\0" + /* 1761 */ "G_FPOWI\0" + /* 1769 */ "G_PTRMASK\0" + /* 1779 */ "GC_LABEL\0" + /* 1788 */ "DBG_LABEL\0" + /* 1798 */ "EH_LABEL\0" + /* 1807 */ "ANNOTATION_LABEL\0" + /* 1824 */ "ICALL_BRANCH_FUNNEL\0" + /* 1844 */ "G_FSHL\0" + /* 1851 */ "G_SHL\0" + /* 1857 */ "G_FCEIL\0" + /* 1865 */ "PATCHABLE_TAIL_CALL\0" + /* 1885 */ "PATCHABLE_TYPED_EVENT_CALL\0" + /* 1912 */ "PATCHABLE_EVENT_CALL\0" + /* 1933 */ "FENTRY_CALL\0" + /* 1945 */ "KILL\0" + /* 1950 */ "G_ROTL\0" + /* 1957 */ "G_VECREDUCE_FMUL\0" + /* 1974 */ "G_FMUL\0" + /* 1981 */ "G_VECREDUCE_SEQ_FMUL\0" + /* 2002 */ "G_STRICT_FMUL\0" + /* 2016 */ "G_VECREDUCE_MUL\0" + /* 2032 */ "G_MUL\0" + /* 2038 */ "G_FREM\0" + /* 2045 */ "G_STRICT_FREM\0" + /* 2059 */ "G_SREM\0" + /* 2066 */ "G_UREM\0" + /* 2073 */ "G_SDIVREM\0" + /* 2083 */ "G_UDIVREM\0" + /* 2093 */ "INLINEASM\0" + /* 2103 */ "G_FMINIMUM\0" + /* 2114 */ "G_FMAXIMUM\0" + /* 2125 */ "G_FMINNUM\0" + /* 2135 */ "G_FMAXNUM\0" + /* 2145 */ "G_INTRINSIC_ROUNDEVEN\0" + /* 2167 */ "G_FCOPYSIGN\0" + /* 2179 */ "G_VECREDUCE_FMIN\0" + /* 2196 */ "G_VECREDUCE_SMIN\0" + /* 2213 */ "G_SMIN\0" + /* 2220 */ "G_VECREDUCE_UMIN\0" + /* 2237 */ "G_UMIN\0" + /* 2244 */ "G_ATOMICRMW_UMIN\0" + /* 2261 */ "G_ATOMICRMW_MIN\0" + /* 2277 */ "G_FSIN\0" + /* 2284 */ "CFI_INSTRUCTION\0" + /* 2300 */ "EH_RETURN\0" + /* 2310 */ "ADJCALLSTACKDOWN\0" + /* 2327 */ "G_SSUBO\0" + /* 2335 */ "G_USUBO\0" + /* 2343 */ "G_SADDO\0" + /* 2351 */ "G_UADDO\0" + /* 2359 */ "G_SMULO\0" + /* 2367 */ "G_UMULO\0" + /* 2375 */ "G_BZERO\0" + /* 2383 */ "STACKMAP\0" + /* 2392 */ "G_BSWAP\0" + /* 2400 */ "G_SITOFP\0" + /* 2409 */ "G_UITOFP\0" + /* 2418 */ "G_FCMP\0" + /* 2425 */ "G_ICMP\0" + /* 2432 */ "G_CTPOP\0" + /* 2440 */ "PATCHABLE_OP\0" + /* 2453 */ "FAULTING_OP\0" + /* 2465 */ "ADJCALLSTACKUP\0" + /* 2480 */ "PREALLOCATED_SETUP\0" + /* 2499 */ "G_FEXP\0" + /* 2506 */ "LDSPC_0R\0" + /* 2515 */ "STSPC_0R\0" + /* 2524 */ "LDSED_0R\0" + /* 2533 */ "STSED_0R\0" + /* 2542 */ "GETED_0R\0" + /* 2551 */ "GETID_0R\0" + /* 2560 */ "CLRE_0R\0" + /* 2568 */ "DCALL_0R\0" + /* 2577 */ "GETKEP_0R\0" + /* 2587 */ "SETKEP_0R\0" + /* 2597 */ "GETKSP_0R\0" + /* 2607 */ "DENTSP_0R\0" + /* 2617 */ "DRESTSP_0R\0" + /* 2628 */ "LDSSR_0R\0" + /* 2637 */ "STSSR_0R\0" + /* 2646 */ "LDET_0R\0" + /* 2654 */ "FREET_0R\0" + /* 2663 */ "DRET_0R\0" + /* 2671 */ "KRET_0R\0" + /* 2679 */ "GETET_0R\0" + /* 2688 */ "STET_0R\0" + /* 2696 */ "WAITEU_0R\0" + /* 2706 */ "WAITEF_1R\0" + /* 2716 */ "WAITET_1R\0" + /* 2726 */ "CLRPT_1R\0" + /* 2735 */ "TSTART_1R\0" + /* 2745 */ "G_BR\0" + /* 2750 */ "INLINEASM_BR\0" + /* 2763 */ "G_BLOCK_ADDR\0" + /* 2776 */ "PATCHABLE_FUNCTION_ENTER\0" + /* 2801 */ "G_READCYCLECOUNTER\0" + /* 2820 */ "G_READ_REGISTER\0" + /* 2836 */ "G_WRITE_REGISTER\0" + /* 2853 */ "G_ASHR\0" + /* 2860 */ "G_FSHR\0" + /* 2867 */ "G_LSHR\0" + /* 2874 */ "G_FFLOOR\0" + /* 2883 */ "G_BUILD_VECTOR\0" + /* 2898 */ "G_SHUFFLE_VECTOR\0" + /* 2915 */ "G_VECREDUCE_XOR\0" + /* 2931 */ "G_XOR\0" + /* 2937 */ "G_ATOMICRMW_XOR\0" + /* 2953 */ "G_VECREDUCE_OR\0" + /* 2968 */ "G_OR\0" + /* 2973 */ "G_ATOMICRMW_OR\0" + /* 2988 */ "G_ROTR\0" + /* 2995 */ "G_INTTOPTR\0" + /* 3006 */ "G_FABS\0" + /* 3013 */ "G_ABS\0" + /* 3019 */ "G_UNMERGE_VALUES\0" + /* 3036 */ "G_MERGE_VALUES\0" + /* 3051 */ "G_FCOS\0" + /* 3058 */ "G_CONCAT_VECTORS\0" + /* 3075 */ "COPY_TO_REGCLASS\0" + /* 3092 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" + /* 3122 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" + /* 3149 */ "G_SSUBSAT\0" + /* 3159 */ "G_USUBSAT\0" + /* 3169 */ "G_SADDSAT\0" + /* 3179 */ "G_UADDSAT\0" + /* 3189 */ "G_SSHLSAT\0" + /* 3199 */ "G_USHLSAT\0" + /* 3209 */ "G_SMULFIXSAT\0" + /* 3222 */ "G_UMULFIXSAT\0" + /* 3235 */ "G_SDIVFIXSAT\0" + /* 3248 */ "G_UDIVFIXSAT\0" + /* 3261 */ "G_EXTRACT\0" + /* 3271 */ "G_SELECT\0" + /* 3280 */ "G_BRINDIRECT\0" + /* 3293 */ "PATCHABLE_RET\0" + /* 3307 */ "FRAME_TO_ARGS_OFFSET\0" + /* 3328 */ "G_MEMSET\0" + /* 3337 */ "PATCHABLE_FUNCTION_EXIT\0" + /* 3361 */ "G_BRJT\0" + /* 3368 */ "BR_JT\0" + /* 3374 */ "G_EXTRACT_VECTOR_ELT\0" + /* 3395 */ "G_INSERT_VECTOR_ELT\0" + /* 3415 */ "G_FCONSTANT\0" + /* 3427 */ "G_CONSTANT\0" + /* 3438 */ "STATEPOINT\0" + /* 3449 */ "PATCHPOINT\0" + /* 3460 */ "G_PTRTOINT\0" + /* 3471 */ "G_FRINT\0" + /* 3479 */ "G_INTRINSIC_LRINT\0" + /* 3497 */ "G_FNEARBYINT\0" + /* 3510 */ "NOT\0" + /* 3514 */ "G_VASTART\0" + /* 3524 */ "LIFETIME_START\0" + /* 3539 */ "G_INSERT\0" + /* 3548 */ "G_FSQRT\0" + /* 3556 */ "G_STRICT_FSQRT\0" + /* 3571 */ "G_BITCAST\0" + /* 3581 */ "G_ADDRSPACE_CAST\0" + /* 3598 */ "DBG_VALUE_LIST\0" + /* 3613 */ "G_FPEXT\0" + /* 3621 */ "G_SEXT\0" + /* 3628 */ "G_ASSERT_SEXT\0" + /* 3642 */ "G_ANYEXT\0" + /* 3651 */ "G_ZEXT\0" + /* 3658 */ "G_ASSERT_ZEXT\0" + /* 3672 */ "G_FDIV\0" + /* 3679 */ "G_STRICT_FDIV\0" + /* 3693 */ "G_SDIV\0" + /* 3700 */ "G_UDIV\0" + /* 3707 */ "G_FPOW\0" + /* 3714 */ "G_VECREDUCE_FMAX\0" + /* 3731 */ "G_VECREDUCE_SMAX\0" + /* 3748 */ "G_SMAX\0" + /* 3755 */ "G_VECREDUCE_UMAX\0" + /* 3772 */ "G_UMAX\0" + /* 3779 */ "G_ATOMICRMW_UMAX\0" + /* 3796 */ "G_ATOMICRMW_MAX\0" + /* 3812 */ "G_FRAME_INDEX\0" + /* 3826 */ "G_SBFX\0" + /* 3833 */ "G_UBFX\0" + /* 3840 */ "G_SMULFIX\0" + /* 3850 */ "G_UMULFIX\0" + /* 3860 */ "G_SDIVFIX\0" + /* 3870 */ "G_UDIVFIX\0" + /* 3880 */ "G_MEMCPY\0" + /* 3889 */ "COPY\0" + /* 3894 */ "G_CTLZ\0" + /* 3901 */ "G_CTTZ\0" + /* 3908 */ "LDAPF_lu10_ba\0" + /* 3922 */ "SSYNC_0r\0" + /* 3931 */ "BLA_1r\0" + /* 3938 */ "MSYNC_1r\0" + /* 3947 */ "ECALLF_1r\0" + /* 3957 */ "DGETREG_1r\0" + /* 3968 */ "KCALL_1r\0" + /* 3977 */ "MJOIN_1r\0" + /* 3986 */ "SETCP_1r\0" + /* 3995 */ "SETDP_1r\0" + /* 4004 */ "SETSP_1r\0" + /* 4013 */ "SYNCR_1r\0" + /* 4022 */ "FREER_1r\0" + /* 4031 */ "ECALLT_1r\0" + /* 4041 */ "BAU_1r\0" + /* 4048 */ "EDU_1r\0" + /* 4055 */ "EEU_1r\0" + /* 4062 */ "BRU_1r\0" + /* 4069 */ "SETEV_1r\0" + /* 4078 */ "SETV_1r\0" + /* 4086 */ "INITPC_2r\0" + /* 4096 */ "SETPSC_2r\0" + /* 4106 */ "SETD_2r\0" + /* 4114 */ "EEF_2r\0" + /* 4121 */ "PEEK_2r\0" + /* 4129 */ "MKMSK_2r\0" + /* 4138 */ "ENDIN_2r\0" + /* 4147 */ "INITCP_2r\0" + /* 4157 */ "INITDP_2r\0" + /* 4167 */ "INITSP_2r\0" + /* 4177 */ "INSHR_2r\0" + /* 4186 */ "OUTSHR_2r\0" + /* 4196 */ "TSETMR_2r\0" + /* 4206 */ "GETTS_2r\0" + /* 4215 */ "CHKCT_2r\0" + /* 4224 */ "INCT_2r\0" + /* 4232 */ "TESTCT_2r\0" + /* 4242 */ "OUTCT_2r\0" + /* 4251 */ "TESTWCT_2r\0" + /* 4262 */ "EET_2r\0" + /* 4269 */ "INT_2r\0" + /* 4276 */ "ANDNOT_2r\0" + /* 4286 */ "SETPT_2r\0" + /* 4295 */ "GETST_2r\0" + /* 4304 */ "OUTT_2r\0" + /* 4312 */ "OUT_2r\0" + /* 4319 */ "SEXT_2r\0" + /* 4327 */ "ZEXT_2r\0" + /* 4335 */ "SETC_l2r\0" + /* 4344 */ "GETD_l2r\0" + /* 4353 */ "SETCLK_l2r\0" + /* 4364 */ "TESTLCL_l2r\0" + /* 4376 */ "GETN_l2r\0" + /* 4385 */ "SETN_l2r\0" + /* 4394 */ "INITLR_l2r\0" + /* 4405 */ "GETPS_l2r\0" + /* 4415 */ "SETPS_l2r\0" + /* 4425 */ "BYTEREV_l2r\0" + /* 4437 */ "BITREV_l2r\0" + /* 4448 */ "SETTW_l2r\0" + /* 4458 */ "SETRDY_l2r\0" + /* 4469 */ "CLZ_l2r\0" + /* 4477 */ "SUB_3r\0" + /* 4484 */ "ADD_3r\0" + /* 4491 */ "AND_3r\0" + /* 4498 */ "SHL_3r\0" + /* 4505 */ "EQ_3r\0" + /* 4511 */ "SHR_3r\0" + /* 4518 */ "OR_3r\0" + /* 4524 */ "TSETR_3r\0" + /* 4533 */ "LD16S_3r\0" + /* 4542 */ "LSS_3r\0" + /* 4549 */ "LD8U_3r\0" + /* 4557 */ "LSU_3r\0" + /* 4564 */ "LDW_3r\0" + /* 4571 */ "ST16_l3r\0" + /* 4580 */ "ST8_l3r\0" + /* 4588 */ "LDA16B_l3r\0" + /* 4599 */ "LDAWB_l3r\0" + /* 4609 */ "CRC_l3r\0" + /* 4617 */ "LDA16F_l3r\0" + /* 4628 */ "LDAWF_l3r\0" + /* 4638 */ "MUL_l3r\0" + /* 4646 */ "ASHR_l3r\0" + /* 4655 */ "XOR_l3r\0" + /* 4663 */ "REMS_l3r\0" + /* 4672 */ "DIVS_l3r\0" + /* 4681 */ "REMU_l3r\0" + /* 4690 */ "DIVU_l3r\0" + /* 4699 */ "STW_l3r\0" + /* 4707 */ "CRC8_l4r\0" + /* 4716 */ "MACCS_l4r\0" + /* 4726 */ "MACCU_l4r\0" + /* 4736 */ "LSUB_l5r\0" + /* 4745 */ "LADD_l5r\0" + /* 4754 */ "LDIVU_l5r\0" + /* 4764 */ "LMUL_l6r\0" + /* 4773 */ "Int_MemBarrier\0" + /* 4788 */ "SUB_2rus\0" + /* 4797 */ "ADD_2rus\0" + /* 4806 */ "SHL_2rus\0" + /* 4815 */ "EQ_2rus\0" + /* 4823 */ "SHR_2rus\0" + /* 4832 */ "LDW_2rus\0" + /* 4841 */ "STW_2rus\0" + /* 4850 */ "LDAWB_l2rus\0" + /* 4862 */ "LDAWF_l2rus\0" + /* 4874 */ "ASHR_l2rus\0" + /* 4885 */ "INPW_l2rus\0" + /* 4896 */ "OUTPW_l2rus\0" + /* 4908 */ "MKMSK_rus\0" + /* 4918 */ "GETR_rus\0" + /* 4927 */ "CHKCT_rus\0" + /* 4937 */ "OUTCT_rus\0" + /* 4947 */ "SEXT_rus\0" + /* 4956 */ "ZEXT_rus\0"}; +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern const unsigned XCoreInstrNameIndices[] = { + 1739U, 2093U, 2750U, 2284U, 1798U, 1779U, 1807U, 1945U, 1578U, 1593U, 1544U, + 1620U, 3075U, 1446U, 3598U, 1557U, 1735U, 1788U, 1301U, 3889U, 1373U, 3524U, + 1176U, 1252U, 1289U, 2383U, 1933U, 3449U, 1235U, 2480U, 1683U, 3438U, 1396U, + 2453U, 2440U, 2776U, 3293U, 3337U, 1865U, 1912U, 1885U, 1824U, 3628U, 3658U, + 1089U, 790U, 2032U, 3693U, 3700U, 2059U, 2066U, 2073U, 2083U, 1154U, 2968U, + 2931U, 1542U, 1737U, 3812U, 1456U, 3261U, 3019U, 3539U, 3036U, 2883U, 870U, + 3058U, 3460U, 2995U, 3571U, 1481U, 844U, 1217U, 3479U, 2145U, 2801U, 990U, + 934U, 964U, 975U, 915U, 945U, 1425U, 1409U, 3092U, 1634U, 1651U, 1105U, + 796U, 1160U, 1121U, 2973U, 2937U, 3796U, 2261U, 3779U, 2244U, 1056U, 773U, + 1281U, 1189U, 3280U, 822U, 3122U, 3642U, 862U, 3427U, 3415U, 3514U, 1675U, + 3621U, 1607U, 3651U, 1851U, 2867U, 2853U, 1844U, 2860U, 2988U, 1950U, 2425U, + 2418U, 3271U, 2351U, 1322U, 2335U, 1273U, 2343U, 1314U, 2327U, 1265U, 2367U, + 2359U, 1708U, 1700U, 3179U, 3169U, 3159U, 3149U, 3199U, 3189U, 3840U, 3850U, + 3209U, 3222U, 3860U, 3870U, 3235U, 3248U, 1014U, 752U, 1974U, 733U, 908U, + 3672U, 2038U, 3707U, 1761U, 2499U, 147U, 1668U, 139U, 0U, 1571U, 3613U, + 834U, 1743U, 1752U, 2400U, 2409U, 3006U, 2167U, 1490U, 2125U, 2135U, 1330U, + 1345U, 2103U, 2114U, 1095U, 1769U, 2213U, 3748U, 2237U, 3772U, 3013U, 1208U, + 1198U, 2745U, 3361U, 3395U, 3374U, 2898U, 3901U, 1524U, 3894U, 1506U, 2432U, + 2392U, 1433U, 1857U, 3051U, 2277U, 3548U, 2874U, 3471U, 3497U, 3581U, 2763U, + 1360U, 891U, 1042U, 759U, 2002U, 3679U, 2045U, 739U, 3556U, 2820U, 2836U, + 3880U, 1380U, 1471U, 3328U, 2375U, 1021U, 1981U, 997U, 1957U, 3714U, 2179U, + 1073U, 2016U, 1138U, 2953U, 2915U, 3731U, 2196U, 3755U, 2220U, 3826U, 3833U, + 2310U, 2465U, 3368U, 131U, 2300U, 3307U, 4773U, 1716U, 1723U, 812U, 1729U, + 4797U, 4484U, 4276U, 4491U, 4874U, 4646U, 4041U, 4437U, 109U, 47U, 409U, + 249U, 3931U, 78U, 19U, 99U, 38U, 614U, 487U, 713U, 577U, 418U, + 257U, 624U, 496U, 723U, 586U, 427U, 265U, 4062U, 4425U, 4215U, 4927U, + 2560U, 2726U, 436U, 273U, 379U, 222U, 4469U, 4707U, 4609U, 2568U, 2607U, + 3957U, 4672U, 4690U, 2617U, 2663U, 3947U, 4031U, 4048U, 4114U, 4262U, 4055U, + 4138U, 347U, 193U, 4815U, 4505U, 326U, 174U, 369U, 213U, 4022U, 2654U, + 4344U, 2542U, 2679U, 2551U, 2577U, 2597U, 4376U, 4405U, 4918U, 389U, 231U, + 4295U, 4206U, 4224U, 4147U, 4157U, 4394U, 4086U, 4167U, 4885U, 4177U, 4269U, + 4141U, 3968U, 305U, 155U, 346U, 192U, 357U, 202U, 2671U, 4745U, 4533U, + 4549U, 4588U, 4617U, 67U, 9U, 88U, 3908U, 28U, 4850U, 4599U, 315U, + 164U, 645U, 515U, 4862U, 4628U, 679U, 546U, 595U, 470U, 2646U, 4754U, + 2524U, 2506U, 2628U, 634U, 120U, 505U, 57U, 657U, 526U, 691U, 557U, + 4832U, 4564U, 4764U, 4542U, 4736U, 4557U, 4716U, 4726U, 3977U, 4129U, 4908U, + 3938U, 4638U, 1574U, 3510U, 4518U, 4242U, 4937U, 4896U, 4186U, 4304U, 4312U, + 4121U, 4663U, 4681U, 336U, 183U, 4353U, 3986U, 4335U, 604U, 478U, 3995U, + 4106U, 4069U, 2587U, 4385U, 4096U, 4415U, 4286U, 4458U, 4004U, 453U, 289U, + 399U, 240U, 4448U, 4078U, 4319U, 4947U, 4806U, 4498U, 4823U, 4511U, 3922U, + 4571U, 4580U, 2688U, 2533U, 2515U, 2637U, 668U, 536U, 702U, 567U, 4841U, + 4699U, 4788U, 4477U, 4013U, 4232U, 4364U, 4251U, 4196U, 4524U, 2735U, 2706U, + 2716U, 2696U, 4655U, 4327U, 4956U, +}; -FieldFromInstruction(fieldFromInstruction_2, uint16_t) -DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) -DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) -FieldFromInstruction(fieldFromInstruction_4, uint32_t) -DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) -DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) +#endif // GET_INSTRINFO_MC_DESC diff --git a/arch/XCore/XCoreGenInstrInfo.inc b/arch/XCore/XCoreGenInstrInfo.inc index 7f579f111f..5e7781fff9 100644 --- a/arch/XCore/XCoreGenInstrInfo.inc +++ b/arch/XCore/XCoreGenInstrInfo.inc @@ -9,259 +9,258 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ - #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { - XCore_PHI = 0, - XCore_INLINEASM = 1, - XCore_CFI_INSTRUCTION = 2, - XCore_EH_LABEL = 3, - XCore_GC_LABEL = 4, - XCore_KILL = 5, - XCore_EXTRACT_SUBREG = 6, - XCore_INSERT_SUBREG = 7, - XCore_IMPLICIT_DEF = 8, - XCore_SUBREG_TO_REG = 9, - XCore_COPY_TO_REGCLASS = 10, - XCore_DBG_VALUE = 11, - XCore_REG_SEQUENCE = 12, - XCore_COPY = 13, - XCore_BUNDLE = 14, - XCore_LIFETIME_START = 15, - XCore_LIFETIME_END = 16, - XCore_STACKMAP = 17, - XCore_PATCHPOINT = 18, - XCore_LOAD_STACK_GUARD = 19, - XCore_STATEPOINT = 20, - XCore_FRAME_ALLOC = 21, - XCore_ADD_2rus = 22, - XCore_ADD_3r = 23, - XCore_ADJCALLSTACKDOWN = 24, - XCore_ADJCALLSTACKUP = 25, - XCore_ANDNOT_2r = 26, - XCore_AND_3r = 27, - XCore_ASHR_l2rus = 28, - XCore_ASHR_l3r = 29, - XCore_BAU_1r = 30, - XCore_BITREV_l2r = 31, - XCore_BLACP_lu10 = 32, - XCore_BLACP_u10 = 33, - XCore_BLAT_lu6 = 34, - XCore_BLAT_u6 = 35, - XCore_BLA_1r = 36, - XCore_BLRB_lu10 = 37, - XCore_BLRB_u10 = 38, - XCore_BLRF_lu10 = 39, - XCore_BLRF_u10 = 40, - XCore_BRBF_lru6 = 41, - XCore_BRBF_ru6 = 42, - XCore_BRBT_lru6 = 43, - XCore_BRBT_ru6 = 44, - XCore_BRBU_lu6 = 45, - XCore_BRBU_u6 = 46, - XCore_BRFF_lru6 = 47, - XCore_BRFF_ru6 = 48, - XCore_BRFT_lru6 = 49, - XCore_BRFT_ru6 = 50, - XCore_BRFU_lu6 = 51, - XCore_BRFU_u6 = 52, - XCore_BRU_1r = 53, - XCore_BR_JT = 54, - XCore_BR_JT32 = 55, - XCore_BYTEREV_l2r = 56, - XCore_CHKCT_2r = 57, - XCore_CHKCT_rus = 58, - XCore_CLRE_0R = 59, - XCore_CLRPT_1R = 60, - XCore_CLRSR_branch_lu6 = 61, - XCore_CLRSR_branch_u6 = 62, - XCore_CLRSR_lu6 = 63, - XCore_CLRSR_u6 = 64, - XCore_CLZ_l2r = 65, - XCore_CRC8_l4r = 66, - XCore_CRC_l3r = 67, - XCore_DCALL_0R = 68, - XCore_DENTSP_0R = 69, - XCore_DGETREG_1r = 70, - XCore_DIVS_l3r = 71, - XCore_DIVU_l3r = 72, - XCore_DRESTSP_0R = 73, - XCore_DRET_0R = 74, - XCore_ECALLF_1r = 75, - XCore_ECALLT_1r = 76, - XCore_EDU_1r = 77, - XCore_EEF_2r = 78, - XCore_EET_2r = 79, - XCore_EEU_1r = 80, - XCore_EH_RETURN = 81, - XCore_ENDIN_2r = 82, - XCore_ENTSP_lu6 = 83, - XCore_ENTSP_u6 = 84, - XCore_EQ_2rus = 85, - XCore_EQ_3r = 86, - XCore_EXTDP_lu6 = 87, - XCore_EXTDP_u6 = 88, - XCore_EXTSP_lu6 = 89, - XCore_EXTSP_u6 = 90, - XCore_FRAME_TO_ARGS_OFFSET = 91, - XCore_FREER_1r = 92, - XCore_FREET_0R = 93, - XCore_GETD_l2r = 94, - XCore_GETED_0R = 95, - XCore_GETET_0R = 96, - XCore_GETID_0R = 97, - XCore_GETKEP_0R = 98, - XCore_GETKSP_0R = 99, - XCore_GETN_l2r = 100, - XCore_GETPS_l2r = 101, - XCore_GETR_rus = 102, - XCore_GETSR_lu6 = 103, - XCore_GETSR_u6 = 104, - XCore_GETST_2r = 105, - XCore_GETTS_2r = 106, - XCore_INCT_2r = 107, - XCore_INITCP_2r = 108, - XCore_INITDP_2r = 109, - XCore_INITLR_l2r = 110, - XCore_INITPC_2r = 111, - XCore_INITSP_2r = 112, - XCore_INPW_l2rus = 113, - XCore_INSHR_2r = 114, - XCore_INT_2r = 115, - XCore_IN_2r = 116, - XCore_Int_MemBarrier = 117, - XCore_KCALL_1r = 118, - XCore_KCALL_lu6 = 119, - XCore_KCALL_u6 = 120, - XCore_KENTSP_lu6 = 121, - XCore_KENTSP_u6 = 122, - XCore_KRESTSP_lu6 = 123, - XCore_KRESTSP_u6 = 124, - XCore_KRET_0R = 125, - XCore_LADD_l5r = 126, - XCore_LD16S_3r = 127, - XCore_LD8U_3r = 128, - XCore_LDA16B_l3r = 129, - XCore_LDA16F_l3r = 130, - XCore_LDAPB_lu10 = 131, - XCore_LDAPB_u10 = 132, - XCore_LDAPF_lu10 = 133, - XCore_LDAPF_lu10_ba = 134, - XCore_LDAPF_u10 = 135, - XCore_LDAWB_l2rus = 136, - XCore_LDAWB_l3r = 137, - XCore_LDAWCP_lu6 = 138, - XCore_LDAWCP_u6 = 139, - XCore_LDAWDP_lru6 = 140, - XCore_LDAWDP_ru6 = 141, - XCore_LDAWFI = 142, - XCore_LDAWF_l2rus = 143, - XCore_LDAWF_l3r = 144, - XCore_LDAWSP_lru6 = 145, - XCore_LDAWSP_ru6 = 146, - XCore_LDC_lru6 = 147, - XCore_LDC_ru6 = 148, - XCore_LDET_0R = 149, - XCore_LDIVU_l5r = 150, - XCore_LDSED_0R = 151, - XCore_LDSPC_0R = 152, - XCore_LDSSR_0R = 153, - XCore_LDWCP_lru6 = 154, - XCore_LDWCP_lu10 = 155, - XCore_LDWCP_ru6 = 156, - XCore_LDWCP_u10 = 157, - XCore_LDWDP_lru6 = 158, - XCore_LDWDP_ru6 = 159, - XCore_LDWFI = 160, - XCore_LDWSP_lru6 = 161, - XCore_LDWSP_ru6 = 162, - XCore_LDW_2rus = 163, - XCore_LDW_3r = 164, - XCore_LMUL_l6r = 165, - XCore_LSS_3r = 166, - XCore_LSUB_l5r = 167, - XCore_LSU_3r = 168, - XCore_MACCS_l4r = 169, - XCore_MACCU_l4r = 170, - XCore_MJOIN_1r = 171, - XCore_MKMSK_2r = 172, - XCore_MKMSK_rus = 173, - XCore_MSYNC_1r = 174, - XCore_MUL_l3r = 175, - XCore_NEG = 176, - XCore_NOT = 177, - XCore_OR_3r = 178, - XCore_OUTCT_2r = 179, - XCore_OUTCT_rus = 180, - XCore_OUTPW_l2rus = 181, - XCore_OUTSHR_2r = 182, - XCore_OUTT_2r = 183, - XCore_OUT_2r = 184, - XCore_PEEK_2r = 185, - XCore_REMS_l3r = 186, - XCore_REMU_l3r = 187, - XCore_RETSP_lu6 = 188, - XCore_RETSP_u6 = 189, - XCore_SELECT_CC = 190, - XCore_SETCLK_l2r = 191, - XCore_SETCP_1r = 192, - XCore_SETC_l2r = 193, - XCore_SETC_lru6 = 194, - XCore_SETC_ru6 = 195, - XCore_SETDP_1r = 196, - XCore_SETD_2r = 197, - XCore_SETEV_1r = 198, - XCore_SETKEP_0R = 199, - XCore_SETN_l2r = 200, - XCore_SETPSC_2r = 201, - XCore_SETPS_l2r = 202, - XCore_SETPT_2r = 203, - XCore_SETRDY_l2r = 204, - XCore_SETSP_1r = 205, - XCore_SETSR_branch_lu6 = 206, - XCore_SETSR_branch_u6 = 207, - XCore_SETSR_lu6 = 208, - XCore_SETSR_u6 = 209, - XCore_SETTW_l2r = 210, - XCore_SETV_1r = 211, - XCore_SEXT_2r = 212, - XCore_SEXT_rus = 213, - XCore_SHL_2rus = 214, - XCore_SHL_3r = 215, - XCore_SHR_2rus = 216, - XCore_SHR_3r = 217, - XCore_SSYNC_0r = 218, - XCore_ST16_l3r = 219, - XCore_ST8_l3r = 220, - XCore_STET_0R = 221, - XCore_STSED_0R = 222, - XCore_STSPC_0R = 223, - XCore_STSSR_0R = 224, - XCore_STWDP_lru6 = 225, - XCore_STWDP_ru6 = 226, - XCore_STWFI = 227, - XCore_STWSP_lru6 = 228, - XCore_STWSP_ru6 = 229, - XCore_STW_2rus = 230, - XCore_STW_l3r = 231, - XCore_SUB_2rus = 232, - XCore_SUB_3r = 233, - XCore_SYNCR_1r = 234, - XCore_TESTCT_2r = 235, - XCore_TESTLCL_l2r = 236, - XCore_TESTWCT_2r = 237, - XCore_TSETMR_2r = 238, - XCore_TSETR_3r = 239, - XCore_TSTART_1R = 240, - XCore_WAITEF_1R = 241, - XCore_WAITET_1R = 242, - XCore_WAITEU_0R = 243, - XCore_XOR_l3r = 244, - XCore_ZEXT_2r = 245, - XCore_ZEXT_rus = 246, - XCore_INSTRUCTION_LIST_END = 247 + XCore_PHI = 0, + XCore_INLINEASM = 1, + XCore_CFI_INSTRUCTION = 2, + XCore_EH_LABEL = 3, + XCore_GC_LABEL = 4, + XCore_KILL = 5, + XCore_EXTRACT_SUBREG = 6, + XCore_INSERT_SUBREG = 7, + XCore_IMPLICIT_DEF = 8, + XCore_SUBREG_TO_REG = 9, + XCore_COPY_TO_REGCLASS = 10, + XCore_DBG_VALUE = 11, + XCore_REG_SEQUENCE = 12, + XCore_COPY = 13, + XCore_BUNDLE = 14, + XCore_LIFETIME_START = 15, + XCore_LIFETIME_END = 16, + XCore_STACKMAP = 17, + XCore_PATCHPOINT = 18, + XCore_LOAD_STACK_GUARD = 19, + XCore_STATEPOINT = 20, + XCore_FRAME_ALLOC = 21, + XCore_ADD_2rus = 22, + XCore_ADD_3r = 23, + XCore_ADJCALLSTACKDOWN = 24, + XCore_ADJCALLSTACKUP = 25, + XCore_ANDNOT_2r = 26, + XCore_AND_3r = 27, + XCore_ASHR_l2rus = 28, + XCore_ASHR_l3r = 29, + XCore_BAU_1r = 30, + XCore_BITREV_l2r = 31, + XCore_BLACP_lu10 = 32, + XCore_BLACP_u10 = 33, + XCore_BLAT_lu6 = 34, + XCore_BLAT_u6 = 35, + XCore_BLA_1r = 36, + XCore_BLRB_lu10 = 37, + XCore_BLRB_u10 = 38, + XCore_BLRF_lu10 = 39, + XCore_BLRF_u10 = 40, + XCore_BRBF_lru6 = 41, + XCore_BRBF_ru6 = 42, + XCore_BRBT_lru6 = 43, + XCore_BRBT_ru6 = 44, + XCore_BRBU_lu6 = 45, + XCore_BRBU_u6 = 46, + XCore_BRFF_lru6 = 47, + XCore_BRFF_ru6 = 48, + XCore_BRFT_lru6 = 49, + XCore_BRFT_ru6 = 50, + XCore_BRFU_lu6 = 51, + XCore_BRFU_u6 = 52, + XCore_BRU_1r = 53, + XCore_BR_JT = 54, + XCore_BR_JT32 = 55, + XCore_BYTEREV_l2r = 56, + XCore_CHKCT_2r = 57, + XCore_CHKCT_rus = 58, + XCore_CLRE_0R = 59, + XCore_CLRPT_1R = 60, + XCore_CLRSR_branch_lu6 = 61, + XCore_CLRSR_branch_u6 = 62, + XCore_CLRSR_lu6 = 63, + XCore_CLRSR_u6 = 64, + XCore_CLZ_l2r = 65, + XCore_CRC8_l4r = 66, + XCore_CRC_l3r = 67, + XCore_DCALL_0R = 68, + XCore_DENTSP_0R = 69, + XCore_DGETREG_1r = 70, + XCore_DIVS_l3r = 71, + XCore_DIVU_l3r = 72, + XCore_DRESTSP_0R = 73, + XCore_DRET_0R = 74, + XCore_ECALLF_1r = 75, + XCore_ECALLT_1r = 76, + XCore_EDU_1r = 77, + XCore_EEF_2r = 78, + XCore_EET_2r = 79, + XCore_EEU_1r = 80, + XCore_EH_RETURN = 81, + XCore_ENDIN_2r = 82, + XCore_ENTSP_lu6 = 83, + XCore_ENTSP_u6 = 84, + XCore_EQ_2rus = 85, + XCore_EQ_3r = 86, + XCore_EXTDP_lu6 = 87, + XCore_EXTDP_u6 = 88, + XCore_EXTSP_lu6 = 89, + XCore_EXTSP_u6 = 90, + XCore_FRAME_TO_ARGS_OFFSET = 91, + XCore_FREER_1r = 92, + XCore_FREET_0R = 93, + XCore_GETD_l2r = 94, + XCore_GETED_0R = 95, + XCore_GETET_0R = 96, + XCore_GETID_0R = 97, + XCore_GETKEP_0R = 98, + XCore_GETKSP_0R = 99, + XCore_GETN_l2r = 100, + XCore_GETPS_l2r = 101, + XCore_GETR_rus = 102, + XCore_GETSR_lu6 = 103, + XCore_GETSR_u6 = 104, + XCore_GETST_2r = 105, + XCore_GETTS_2r = 106, + XCore_INCT_2r = 107, + XCore_INITCP_2r = 108, + XCore_INITDP_2r = 109, + XCore_INITLR_l2r = 110, + XCore_INITPC_2r = 111, + XCore_INITSP_2r = 112, + XCore_INPW_l2rus = 113, + XCore_INSHR_2r = 114, + XCore_INT_2r = 115, + XCore_IN_2r = 116, + XCore_Int_MemBarrier = 117, + XCore_KCALL_1r = 118, + XCore_KCALL_lu6 = 119, + XCore_KCALL_u6 = 120, + XCore_KENTSP_lu6 = 121, + XCore_KENTSP_u6 = 122, + XCore_KRESTSP_lu6 = 123, + XCore_KRESTSP_u6 = 124, + XCore_KRET_0R = 125, + XCore_LADD_l5r = 126, + XCore_LD16S_3r = 127, + XCore_LD8U_3r = 128, + XCore_LDA16B_l3r = 129, + XCore_LDA16F_l3r = 130, + XCore_LDAPB_lu10 = 131, + XCore_LDAPB_u10 = 132, + XCore_LDAPF_lu10 = 133, + XCore_LDAPF_lu10_ba = 134, + XCore_LDAPF_u10 = 135, + XCore_LDAWB_l2rus = 136, + XCore_LDAWB_l3r = 137, + XCore_LDAWCP_lu6 = 138, + XCore_LDAWCP_u6 = 139, + XCore_LDAWDP_lru6 = 140, + XCore_LDAWDP_ru6 = 141, + XCore_LDAWFI = 142, + XCore_LDAWF_l2rus = 143, + XCore_LDAWF_l3r = 144, + XCore_LDAWSP_lru6 = 145, + XCore_LDAWSP_ru6 = 146, + XCore_LDC_lru6 = 147, + XCore_LDC_ru6 = 148, + XCore_LDET_0R = 149, + XCore_LDIVU_l5r = 150, + XCore_LDSED_0R = 151, + XCore_LDSPC_0R = 152, + XCore_LDSSR_0R = 153, + XCore_LDWCP_lru6 = 154, + XCore_LDWCP_lu10 = 155, + XCore_LDWCP_ru6 = 156, + XCore_LDWCP_u10 = 157, + XCore_LDWDP_lru6 = 158, + XCore_LDWDP_ru6 = 159, + XCore_LDWFI = 160, + XCore_LDWSP_lru6 = 161, + XCore_LDWSP_ru6 = 162, + XCore_LDW_2rus = 163, + XCore_LDW_3r = 164, + XCore_LMUL_l6r = 165, + XCore_LSS_3r = 166, + XCore_LSUB_l5r = 167, + XCore_LSU_3r = 168, + XCore_MACCS_l4r = 169, + XCore_MACCU_l4r = 170, + XCore_MJOIN_1r = 171, + XCore_MKMSK_2r = 172, + XCore_MKMSK_rus = 173, + XCore_MSYNC_1r = 174, + XCore_MUL_l3r = 175, + XCore_NEG = 176, + XCore_NOT = 177, + XCore_OR_3r = 178, + XCore_OUTCT_2r = 179, + XCore_OUTCT_rus = 180, + XCore_OUTPW_l2rus = 181, + XCore_OUTSHR_2r = 182, + XCore_OUTT_2r = 183, + XCore_OUT_2r = 184, + XCore_PEEK_2r = 185, + XCore_REMS_l3r = 186, + XCore_REMU_l3r = 187, + XCore_RETSP_lu6 = 188, + XCore_RETSP_u6 = 189, + XCore_SELECT_CC = 190, + XCore_SETCLK_l2r = 191, + XCore_SETCP_1r = 192, + XCore_SETC_l2r = 193, + XCore_SETC_lru6 = 194, + XCore_SETC_ru6 = 195, + XCore_SETDP_1r = 196, + XCore_SETD_2r = 197, + XCore_SETEV_1r = 198, + XCore_SETKEP_0R = 199, + XCore_SETN_l2r = 200, + XCore_SETPSC_2r = 201, + XCore_SETPS_l2r = 202, + XCore_SETPT_2r = 203, + XCore_SETRDY_l2r = 204, + XCore_SETSP_1r = 205, + XCore_SETSR_branch_lu6 = 206, + XCore_SETSR_branch_u6 = 207, + XCore_SETSR_lu6 = 208, + XCore_SETSR_u6 = 209, + XCore_SETTW_l2r = 210, + XCore_SETV_1r = 211, + XCore_SEXT_2r = 212, + XCore_SEXT_rus = 213, + XCore_SHL_2rus = 214, + XCore_SHL_3r = 215, + XCore_SHR_2rus = 216, + XCore_SHR_3r = 217, + XCore_SSYNC_0r = 218, + XCore_ST16_l3r = 219, + XCore_ST8_l3r = 220, + XCore_STET_0R = 221, + XCore_STSED_0R = 222, + XCore_STSPC_0R = 223, + XCore_STSSR_0R = 224, + XCore_STWDP_lru6 = 225, + XCore_STWDP_ru6 = 226, + XCore_STWFI = 227, + XCore_STWSP_lru6 = 228, + XCore_STWSP_ru6 = 229, + XCore_STW_2rus = 230, + XCore_STW_l3r = 231, + XCore_SUB_2rus = 232, + XCore_SUB_3r = 233, + XCore_SYNCR_1r = 234, + XCore_TESTCT_2r = 235, + XCore_TESTLCL_l2r = 236, + XCore_TESTWCT_2r = 237, + XCore_TSETMR_2r = 238, + XCore_TSETR_3r = 239, + XCore_TSTART_1R = 240, + XCore_WAITEF_1R = 241, + XCore_WAITET_1R = 242, + XCore_WAITEU_0R = 243, + XCore_XOR_l3r = 244, + XCore_ZEXT_2r = 245, + XCore_ZEXT_rus = 246, + XCore_INSTRUCTION_LIST_END = 247 }; #endif // GET_INSTRINFO_ENUM diff --git a/arch/XCore/XCoreGenRegisterInfo.inc b/arch/XCore/XCoreGenRegisterInfo.inc index 0349badb56..475dfe1b0b 100644 --- a/arch/XCore/XCoreGenRegisterInfo.inc +++ b/arch/XCore/XCoreGenRegisterInfo.inc @@ -9,7 +9,6 @@ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ - #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM @@ -31,14 +30,11 @@ enum { XCore_R9 = 14, XCore_R10 = 15, XCore_R11 = 16, - XCore_NUM_TARGET_REGS // 17 + XCore_NUM_TARGET_REGS // 17 }; // Register classes -enum { - XCore_RRegsRegClassID = 0, - XCore_GRRegsRegClassID = 1 -}; +enum { XCore_RRegsRegClassID = 0, XCore_GRRegsRegClassID = 1 }; #endif // GET_REGINFO_ENUM @@ -50,61 +46,58 @@ enum { |* *| \*===----------------------------------------------------------------------===*/ - #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg XCoreRegDiffLists[] = { - /* 0 */ 65535, 0, + /* 0 */ 65535, + 0, }; static const uint16_t XCoreSubRegIdxLists[] = { - /* 0 */ 0, + /* 0 */ 0, }; -static const MCRegisterDesc XCoreRegDesc[] = { // Descriptors - { 3, 0, 0, 0, 0, 0 }, - { 38, 1, 1, 0, 1, 0 }, - { 41, 1, 1, 0, 1, 0 }, - { 47, 1, 1, 0, 1, 0 }, - { 44, 1, 1, 0, 1, 0 }, - { 4, 1, 1, 0, 1, 0 }, - { 11, 1, 1, 0, 1, 0 }, - { 14, 1, 1, 0, 1, 0 }, - { 17, 1, 1, 0, 1, 0 }, - { 20, 1, 1, 0, 1, 0 }, - { 23, 1, 1, 0, 1, 0 }, - { 26, 1, 1, 0, 1, 0 }, - { 29, 1, 1, 0, 1, 0 }, - { 32, 1, 1, 0, 1, 0 }, - { 35, 1, 1, 0, 1, 0 }, - { 0, 1, 1, 0, 1, 0 }, - { 7, 1, 1, 0, 1, 0 }, +static const MCRegisterDesc XCoreRegDesc[] = { + // Descriptors + {3, 0, 0, 0, 0, 0}, {38, 1, 1, 0, 1, 0}, {41, 1, 1, 0, 1, 0}, + {47, 1, 1, 0, 1, 0}, {44, 1, 1, 0, 1, 0}, {4, 1, 1, 0, 1, 0}, + {11, 1, 1, 0, 1, 0}, {14, 1, 1, 0, 1, 0}, {17, 1, 1, 0, 1, 0}, + {20, 1, 1, 0, 1, 0}, {23, 1, 1, 0, 1, 0}, {26, 1, 1, 0, 1, 0}, + {29, 1, 1, 0, 1, 0}, {32, 1, 1, 0, 1, 0}, {35, 1, 1, 0, 1, 0}, + {0, 1, 1, 0, 1, 0}, {7, 1, 1, 0, 1, 0}, }; - // RRegs Register Class... - static const MCPhysReg RRegs[] = { - XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR, - }; +// RRegs Register Class... +static const MCPhysReg RRegs[] = { + XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, + XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, + XCore_CP, XCore_DP, XCore_SP, XCore_LR, +}; - // RRegs Bit set. - static const uint8_t RRegsBits[] = { - 0xfe, 0xff, 0x01, - }; +// RRegs Bit set. +static const uint8_t RRegsBits[] = { + 0xfe, + 0xff, + 0x01, +}; - // GRRegs Register Class... - static const MCPhysReg GRRegs[] = { - XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, - }; +// GRRegs Register Class... +static const MCPhysReg GRRegs[] = { + XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, + XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, +}; - // GRRegs Bit set. - static const uint8_t GRRegsBits[] = { - 0xe0, 0xff, 0x01, - }; +// GRRegs Bit set. +static const uint8_t GRRegsBits[] = { + 0xe0, + 0xff, + 0x01, +}; static const MCRegisterClass XCoreMCRegisterClasses[] = { - { RRegs, RRegsBits, sizeof(RRegsBits) }, - { GRRegs, GRRegsBits, sizeof(GRRegsBits) }, + {RRegs, RRegsBits, sizeof(RRegsBits)}, + {GRRegs, GRRegsBits, sizeof(GRRegsBits)}, }; #endif // GET_REGINFO_MC_DESC diff --git a/arch/XCore/XCoreInstPrinter.c b/arch/XCore/XCoreInstPrinter.c index fcd020596f..6bbe1966ca 100644 --- a/arch/XCore/XCoreInstPrinter.c +++ b/arch/XCore/XCoreInstPrinter.c @@ -1,4 +1,5 @@ -//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax --------===// +//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax +//--------===// // // The LLVM Compiler Infrastructure // @@ -16,235 +17,298 @@ #ifdef CAPSTONE_HAS_XCORE -#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) -#pragma warning(disable : 4996) // disable MSVC's warning on strcpy() -#pragma warning(disable : 28719) // disable MSVC's warning on strcpy() +#if defined(WIN32) || defined(WIN64) || defined(_WIN32) || defined(_WIN64) +#pragma warning(disable : 4996) // disable MSVC's warning on strcpy() +#pragma warning(disable : 28719) // disable MSVC's warning on strcpy() #endif +#include #include #include #include -#include -#include "XCoreInstPrinter.h" #include "../../MCInst.h" -#include "../../utils.h" -#include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" +#include "../../SStream.h" +#include "../../utils.h" +#include "XCoreInstPrinter.h" #include "XCoreMapping.h" static const char *getRegisterName(unsigned RegNo); -void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) -{ - /* - if (((cs_struct *)ud)->detail != CS_OPT_ON) - return; - */ +void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { + /* + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + */ } // stw sed, sp[3] -void XCore_insn_extract(MCInst *MI, const char *code) -{ - int id; - char *p, *p2; - char tmp[128]; - - strcpy(tmp, code); // safe because code is way shorter than 128 bytes - - // find the first space - p = strchr(tmp, ' '); - if (p) { - p++; - // find the next ',' - p2 = strchr(p, ','); - if (p2) { - *p2 = '\0'; - id = XCore_reg_id(p); - if (id) { - // register - if (MI->csh->detail) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; - MI->flat_insn->detail->xcore.op_count++; - } - } - // next should be register, or memory? - // skip space - p2++; - while(*p2 && *p2 == ' ') - p2++; - if (*p2) { - // find '[' - p = p2; - while(*p && *p != '[') - p++; - if (*p) { - // this is '[' - *p = '\0'; - id = XCore_reg_id(p2); - if (id) { - // base register - if (MI->csh->detail) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)id; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; - } - - p++; - p2 = p; - // until ']' - while(*p && *p != ']') - p++; - if (*p) { - *p = '\0'; - // p2 is either index, or disp - id = XCore_reg_id(p2); - if (id) { - // index register - if (MI->csh->detail) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)id; - } - } else { - // a number means disp - if (MI->csh->detail) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2); - } - } - } - - if (MI->csh->detail) { - MI->flat_insn->detail->xcore.op_count++; - } - } - } else { - // a register? - id = XCore_reg_id(p2); - if (id) { - // register - if (MI->csh->detail) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; - MI->flat_insn->detail->xcore.op_count++; - } - } - } - } - } else { - id = XCore_reg_id(p); - if (id) { - // register - if (MI->csh->detail) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; - MI->flat_insn->detail->xcore.op_count++; - } - } - } - } -} +void XCore_insn_extract(MCInst *MI, const char *code) { + int id; + char *p, *p2; + char tmp[128]; -static void set_mem_access(MCInst *MI, bool status, int reg) -{ - if (MI->csh->detail != CS_OPT_ON) - return; - - MI->csh->doing_mem = status; - if (status) { - if (reg != 0xffff && reg != -0xffff) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; - if (reg) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg; - } else { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = XCORE_REG_INVALID; - } - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; - } else { - // the last op should be the memory base - MI->flat_insn->detail->xcore.op_count--; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; - if (reg > 0) - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; - else - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = -1; - } - } else { - if (reg) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg; - // done, create the next operand slot - MI->flat_insn->detail->xcore.op_count++; - } - } -} + strcpy(tmp, code); // safe because code is way shorter than 128 bytes -static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O) -{ - if (MCOperand_isReg(MO)) { - unsigned reg; - - reg = MCOperand_getReg(MO); - SStream_concat0(O, getRegisterName(reg)); - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID) - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg; - else - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg; - } else { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = reg; - MI->flat_insn->detail->xcore.op_count++; - } - } - } else if (MCOperand_isImm(MO)) { - int32_t Imm = (int32_t)MCOperand_getImm(MO); - - printInt32(O, Imm); - - if (MI->csh->detail) { - if (MI->csh->doing_mem) { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = Imm; - } else { - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_IMM; - MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].imm = Imm; - MI->flat_insn->detail->xcore.op_count++; - } - } - } + // find the first space + p = strchr(tmp, ' '); + if (p) { + p++; + // find the next ',' + p2 = strchr(p, ','); + if (p2) { + *p2 = '\0'; + id = XCore_reg_id(p); + if (id) { + // register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .type = XCORE_OP_REG; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .reg = id; + MI->flat_insn->detail->xcore.op_count++; + } + } + // next should be register, or memory? + // skip space + p2++; + while (*p2 && *p2 == ' ') + p2++; + if (*p2) { + // find '[' + p = p2; + while (*p && *p != '[') + p++; + if (*p) { + // this is '[' + *p = '\0'; + id = XCore_reg_id(p2); + if (id) { + // base register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .type = XCORE_OP_MEM; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.base = (uint8_t)id; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.index = XCORE_REG_INVALID; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.disp = 0; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.direct = 1; + } + + p++; + p2 = p; + // until ']' + while (*p && *p != ']') + p++; + if (*p) { + *p = '\0'; + // p2 is either index, or disp + id = XCore_reg_id(p2); + if (id) { + // index register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.index = (uint8_t)id; + } + } else { + // a number means disp + if (MI->csh->detail) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.disp = atoi(p2); + } + } + } + + if (MI->csh->detail) { + MI->flat_insn->detail->xcore.op_count++; + } + } + } else { + // a register? + id = XCore_reg_id(p2); + if (id) { + // register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .type = XCORE_OP_REG; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .reg = id; + MI->flat_insn->detail->xcore.op_count++; + } + } + } + } + } else { + id = XCore_reg_id(p); + if (id) { + // register + if (MI->csh->detail) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .type = XCORE_OP_REG; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .reg = id; + MI->flat_insn->detail->xcore.op_count++; + } + } + } + } } -static void printOperand(MCInst *MI, int OpNum, SStream *O) -{ - if (OpNum >= MI->size) - return; +static void set_mem_access(MCInst *MI, bool status, int reg) { + if (MI->csh->detail != CS_OPT_ON) + return; - _printOperand(MI, MCInst_getOperand(MI, OpNum), O); + MI->csh->doing_mem = status; + if (status) { + if (reg != 0xffff && reg != -0xffff) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .type = XCORE_OP_MEM; + if (reg) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.base = (uint8_t)reg; + } else { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.base = XCORE_REG_INVALID; + } + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.index = XCORE_REG_INVALID; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.disp = 0; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.direct = 1; + } else { + // the last op should be the memory base + MI->flat_insn->detail->xcore.op_count--; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .type = XCORE_OP_MEM; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.base = (uint8_t)MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .reg; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.index = XCORE_REG_INVALID; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.disp = 0; + if (reg > 0) + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.direct = 1; + else + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.direct = -1; + } + } else { + if (reg) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.index = (uint8_t)reg; + // done, create the next operand slot + MI->flat_insn->detail->xcore.op_count++; + } + } } -static void printInlineJT(MCInst *MI, int OpNum, SStream *O) -{ +static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O) { + if (MCOperand_isReg(MO)) { + unsigned reg; + + reg = MCOperand_getReg(MO); + SStream_concat0(O, getRegisterName(reg)); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + if (MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.base == ARM_REG_INVALID) + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.base = (uint8_t)reg; + else + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.index = (uint8_t)reg; + } else { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .type = XCORE_OP_REG; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .reg = reg; + MI->flat_insn->detail->xcore.op_count++; + } + } + } else if (MCOperand_isImm(MO)) { + int32_t Imm = (int32_t)MCOperand_getImm(MO); + + printInt32(O, Imm); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .mem.disp = Imm; + } else { + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .type = XCORE_OP_IMM; + MI->flat_insn->detail->xcore + .operands[MI->flat_insn->detail->xcore.op_count] + .imm = Imm; + MI->flat_insn->detail->xcore.op_count++; + } + } + } } -static void printInlineJT32(MCInst *MI, int OpNum, SStream *O) -{ +static void printOperand(MCInst *MI, int OpNum, SStream *O) { + if (OpNum >= MI->size) + return; + + _printOperand(MI, MCInst_getOperand(MI, OpNum), O); } +static void printInlineJT(MCInst *MI, int OpNum, SStream *O) {} + +static void printInlineJT32(MCInst *MI, int OpNum, SStream *O) {} + +#define GET_INSTRINFO_ENUM #define PRINT_ALIAS_INSTR -#include "XCoreGenAsmWriter.inc" +#define GET_REGINFO_ENUM +#define GET_ASM_WRITER +#include "XCoreGenDisassemblerTables.inc" -void XCore_printInst(MCInst *MI, SStream *O, void *Info) -{ - printInstruction(MI, O, Info); - set_mem_access(MI, false, 0); +void XCore_printInst(MCInst *MI, SStream *O, void *Info) { + printInstruction(MI, O); + set_mem_access(MI, false, 0); } #endif diff --git a/arch/XCore/XCoreMapping.c b/arch/XCore/XCoreMapping.c index 2a07e12245..bf908e16ba 100644 --- a/arch/XCore/XCoreMapping.c +++ b/arch/XCore/XCoreMapping.c @@ -3,7 +3,7 @@ #ifdef CAPSTONE_HAS_XCORE -#include // debug +#include // debug #include #include "../../utils.h" @@ -14,284 +14,225 @@ #include "XCoreGenInstrInfo.inc" static const name_map reg_name_maps[] = { - { XCORE_REG_INVALID, NULL }, - - { XCORE_REG_CP, "cp" }, - { XCORE_REG_DP, "dp" }, - { XCORE_REG_LR, "lr" }, - { XCORE_REG_SP, "sp" }, - { XCORE_REG_R0, "r0" }, - { XCORE_REG_R1, "r1" }, - { XCORE_REG_R2, "r2" }, - { XCORE_REG_R3, "r3" }, - { XCORE_REG_R4, "r4" }, - { XCORE_REG_R5, "r5" }, - { XCORE_REG_R6, "r6" }, - { XCORE_REG_R7, "r7" }, - { XCORE_REG_R8, "r8" }, - { XCORE_REG_R9, "r9" }, - { XCORE_REG_R10, "r10" }, - { XCORE_REG_R11, "r11" }, - - // pseudo registers - { XCORE_REG_PC, "pc" }, - - { XCORE_REG_SCP, "scp" }, - { XCORE_REG_SSR, "ssr" }, - { XCORE_REG_ET, "et" }, - { XCORE_REG_ED, "ed" }, - { XCORE_REG_SED, "sed" }, - { XCORE_REG_KEP, "kep" }, - { XCORE_REG_KSP, "ksp" }, - { XCORE_REG_ID, "id" }, + {XCORE_REG_INVALID, NULL}, + + {XCORE_REG_CP, "cp"}, + {XCORE_REG_DP, "dp"}, + {XCORE_REG_LR, "lr"}, + {XCORE_REG_SP, "sp"}, + {XCORE_REG_R0, "r0"}, + {XCORE_REG_R1, "r1"}, + {XCORE_REG_R2, "r2"}, + {XCORE_REG_R3, "r3"}, + {XCORE_REG_R4, "r4"}, + {XCORE_REG_R5, "r5"}, + {XCORE_REG_R6, "r6"}, + {XCORE_REG_R7, "r7"}, + {XCORE_REG_R8, "r8"}, + {XCORE_REG_R9, "r9"}, + {XCORE_REG_R10, "r10"}, + {XCORE_REG_R11, "r11"}, + + // pseudo registers + {XCORE_REG_PC, "pc"}, + + {XCORE_REG_SCP, "scp"}, + {XCORE_REG_SSR, "ssr"}, + {XCORE_REG_ET, "et"}, + {XCORE_REG_ED, "ed"}, + {XCORE_REG_SED, "sed"}, + {XCORE_REG_KEP, "kep"}, + {XCORE_REG_KSP, "ksp"}, + {XCORE_REG_ID, "id"}, }; -const char *XCore_reg_name(csh handle, unsigned int reg) -{ +const char *XCore_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET - if (reg >= ARR_SIZE(reg_name_maps)) - return NULL; + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; - return reg_name_maps[reg].name; + return reg_name_maps[reg].name; #else - return NULL; + return NULL; #endif } -xcore_reg XCore_reg_id(char *name) -{ - int i; +xcore_reg XCore_reg_id(char *name) { + int i; - for(i = 1; i < ARR_SIZE(reg_name_maps); i++) { - if (!strcmp(name, reg_name_maps[i].name)) - return reg_name_maps[i].id; - } + for (i = 1; i < ARR_SIZE(reg_name_maps); i++) { + if (!strcmp(name, reg_name_maps[i].name)) + return reg_name_maps[i].id; + } - // not found - return 0; + // not found + return 0; } static const insn_map insns[] = { - // dummy item - { - 0, 0, + // dummy item + {0, + 0, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + {0}, + {0}, + {0}, + 0, + 0 #endif - }, + }, #include "XCoreMappingInsn.inc" }; // given internal insn id, return public instruction info -void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) -{ - unsigned short i; +void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { + unsigned short i; - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; + i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + insn->id = insns[i].mapid; - if (h->detail) { + if (h->detail) { #ifndef CAPSTONE_DIET - memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); - - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); - - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = XCORE_GRP_JUMP; - insn->detail->groups_count++; - } + memcpy(insn->detail->regs_read, insns[i].regs_use, + sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = + (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, + sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = + (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = XCORE_GRP_JUMP; + insn->detail->groups_count++; + } #endif - } - } + } + } } #ifndef CAPSTONE_DIET static const name_map insn_name_maps[] = { - { XCORE_INS_INVALID, NULL }, - - { XCORE_INS_ADD, "add" }, - { XCORE_INS_ANDNOT, "andnot" }, - { XCORE_INS_AND, "and" }, - { XCORE_INS_ASHR, "ashr" }, - { XCORE_INS_BAU, "bau" }, - { XCORE_INS_BITREV, "bitrev" }, - { XCORE_INS_BLA, "bla" }, - { XCORE_INS_BLAT, "blat" }, - { XCORE_INS_BL, "bl" }, - { XCORE_INS_BF, "bf" }, - { XCORE_INS_BT, "bt" }, - { XCORE_INS_BU, "bu" }, - { XCORE_INS_BRU, "bru" }, - { XCORE_INS_BYTEREV, "byterev" }, - { XCORE_INS_CHKCT, "chkct" }, - { XCORE_INS_CLRE, "clre" }, - { XCORE_INS_CLRPT, "clrpt" }, - { XCORE_INS_CLRSR, "clrsr" }, - { XCORE_INS_CLZ, "clz" }, - { XCORE_INS_CRC8, "crc8" }, - { XCORE_INS_CRC32, "crc32" }, - { XCORE_INS_DCALL, "dcall" }, - { XCORE_INS_DENTSP, "dentsp" }, - { XCORE_INS_DGETREG, "dgetreg" }, - { XCORE_INS_DIVS, "divs" }, - { XCORE_INS_DIVU, "divu" }, - { XCORE_INS_DRESTSP, "drestsp" }, - { XCORE_INS_DRET, "dret" }, - { XCORE_INS_ECALLF, "ecallf" }, - { XCORE_INS_ECALLT, "ecallt" }, - { XCORE_INS_EDU, "edu" }, - { XCORE_INS_EEF, "eef" }, - { XCORE_INS_EET, "eet" }, - { XCORE_INS_EEU, "eeu" }, - { XCORE_INS_ENDIN, "endin" }, - { XCORE_INS_ENTSP, "entsp" }, - { XCORE_INS_EQ, "eq" }, - { XCORE_INS_EXTDP, "extdp" }, - { XCORE_INS_EXTSP, "extsp" }, - { XCORE_INS_FREER, "freer" }, - { XCORE_INS_FREET, "freet" }, - { XCORE_INS_GETD, "getd" }, - { XCORE_INS_GET, "get" }, - { XCORE_INS_GETN, "getn" }, - { XCORE_INS_GETR, "getr" }, - { XCORE_INS_GETSR, "getsr" }, - { XCORE_INS_GETST, "getst" }, - { XCORE_INS_GETTS, "getts" }, - { XCORE_INS_INCT, "inct" }, - { XCORE_INS_INIT, "init" }, - { XCORE_INS_INPW, "inpw" }, - { XCORE_INS_INSHR, "inshr" }, - { XCORE_INS_INT, "int" }, - { XCORE_INS_IN, "in" }, - { XCORE_INS_KCALL, "kcall" }, - { XCORE_INS_KENTSP, "kentsp" }, - { XCORE_INS_KRESTSP, "krestsp" }, - { XCORE_INS_KRET, "kret" }, - { XCORE_INS_LADD, "ladd" }, - { XCORE_INS_LD16S, "ld16s" }, - { XCORE_INS_LD8U, "ld8u" }, - { XCORE_INS_LDA16, "lda16" }, - { XCORE_INS_LDAP, "ldap" }, - { XCORE_INS_LDAW, "ldaw" }, - { XCORE_INS_LDC, "ldc" }, - { XCORE_INS_LDW, "ldw" }, - { XCORE_INS_LDIVU, "ldivu" }, - { XCORE_INS_LMUL, "lmul" }, - { XCORE_INS_LSS, "lss" }, - { XCORE_INS_LSUB, "lsub" }, - { XCORE_INS_LSU, "lsu" }, - { XCORE_INS_MACCS, "maccs" }, - { XCORE_INS_MACCU, "maccu" }, - { XCORE_INS_MJOIN, "mjoin" }, - { XCORE_INS_MKMSK, "mkmsk" }, - { XCORE_INS_MSYNC, "msync" }, - { XCORE_INS_MUL, "mul" }, - { XCORE_INS_NEG, "neg" }, - { XCORE_INS_NOT, "not" }, - { XCORE_INS_OR, "or" }, - { XCORE_INS_OUTCT, "outct" }, - { XCORE_INS_OUTPW, "outpw" }, - { XCORE_INS_OUTSHR, "outshr" }, - { XCORE_INS_OUTT, "outt" }, - { XCORE_INS_OUT, "out" }, - { XCORE_INS_PEEK, "peek" }, - { XCORE_INS_REMS, "rems" }, - { XCORE_INS_REMU, "remu" }, - { XCORE_INS_RETSP, "retsp" }, - { XCORE_INS_SETCLK, "setclk" }, - { XCORE_INS_SET, "set" }, - { XCORE_INS_SETC, "setc" }, - { XCORE_INS_SETD, "setd" }, - { XCORE_INS_SETEV, "setev" }, - { XCORE_INS_SETN, "setn" }, - { XCORE_INS_SETPSC, "setpsc" }, - { XCORE_INS_SETPT, "setpt" }, - { XCORE_INS_SETRDY, "setrdy" }, - { XCORE_INS_SETSR, "setsr" }, - { XCORE_INS_SETTW, "settw" }, - { XCORE_INS_SETV, "setv" }, - { XCORE_INS_SEXT, "sext" }, - { XCORE_INS_SHL, "shl" }, - { XCORE_INS_SHR, "shr" }, - { XCORE_INS_SSYNC, "ssync" }, - { XCORE_INS_ST16, "st16" }, - { XCORE_INS_ST8, "st8" }, - { XCORE_INS_STW, "stw" }, - { XCORE_INS_SUB, "sub" }, - { XCORE_INS_SYNCR, "syncr" }, - { XCORE_INS_TESTCT, "testct" }, - { XCORE_INS_TESTLCL, "testlcl" }, - { XCORE_INS_TESTWCT, "testwct" }, - { XCORE_INS_TSETMR, "tsetmr" }, - { XCORE_INS_START, "start" }, - { XCORE_INS_WAITEF, "waitef" }, - { XCORE_INS_WAITET, "waitet" }, - { XCORE_INS_WAITEU, "waiteu" }, - { XCORE_INS_XOR, "xor" }, - { XCORE_INS_ZEXT, "zext" }, + {XCORE_INS_INVALID, NULL}, + + {XCORE_INS_ADD, "add"}, {XCORE_INS_ANDNOT, "andnot"}, + {XCORE_INS_AND, "and"}, {XCORE_INS_ASHR, "ashr"}, + {XCORE_INS_BAU, "bau"}, {XCORE_INS_BITREV, "bitrev"}, + {XCORE_INS_BLA, "bla"}, {XCORE_INS_BLAT, "blat"}, + {XCORE_INS_BL, "bl"}, {XCORE_INS_BF, "bf"}, + {XCORE_INS_BT, "bt"}, {XCORE_INS_BU, "bu"}, + {XCORE_INS_BRU, "bru"}, {XCORE_INS_BYTEREV, "byterev"}, + {XCORE_INS_CHKCT, "chkct"}, {XCORE_INS_CLRE, "clre"}, + {XCORE_INS_CLRPT, "clrpt"}, {XCORE_INS_CLRSR, "clrsr"}, + {XCORE_INS_CLZ, "clz"}, {XCORE_INS_CRC8, "crc8"}, + {XCORE_INS_CRC32, "crc32"}, {XCORE_INS_DCALL, "dcall"}, + {XCORE_INS_DENTSP, "dentsp"}, {XCORE_INS_DGETREG, "dgetreg"}, + {XCORE_INS_DIVS, "divs"}, {XCORE_INS_DIVU, "divu"}, + {XCORE_INS_DRESTSP, "drestsp"}, {XCORE_INS_DRET, "dret"}, + {XCORE_INS_ECALLF, "ecallf"}, {XCORE_INS_ECALLT, "ecallt"}, + {XCORE_INS_EDU, "edu"}, {XCORE_INS_EEF, "eef"}, + {XCORE_INS_EET, "eet"}, {XCORE_INS_EEU, "eeu"}, + {XCORE_INS_ENDIN, "endin"}, {XCORE_INS_ENTSP, "entsp"}, + {XCORE_INS_EQ, "eq"}, {XCORE_INS_EXTDP, "extdp"}, + {XCORE_INS_EXTSP, "extsp"}, {XCORE_INS_FREER, "freer"}, + {XCORE_INS_FREET, "freet"}, {XCORE_INS_GETD, "getd"}, + {XCORE_INS_GET, "get"}, {XCORE_INS_GETN, "getn"}, + {XCORE_INS_GETR, "getr"}, {XCORE_INS_GETSR, "getsr"}, + {XCORE_INS_GETST, "getst"}, {XCORE_INS_GETTS, "getts"}, + {XCORE_INS_INCT, "inct"}, {XCORE_INS_INIT, "init"}, + {XCORE_INS_INPW, "inpw"}, {XCORE_INS_INSHR, "inshr"}, + {XCORE_INS_INT, "int"}, {XCORE_INS_IN, "in"}, + {XCORE_INS_KCALL, "kcall"}, {XCORE_INS_KENTSP, "kentsp"}, + {XCORE_INS_KRESTSP, "krestsp"}, {XCORE_INS_KRET, "kret"}, + {XCORE_INS_LADD, "ladd"}, {XCORE_INS_LD16S, "ld16s"}, + {XCORE_INS_LD8U, "ld8u"}, {XCORE_INS_LDA16, "lda16"}, + {XCORE_INS_LDAP, "ldap"}, {XCORE_INS_LDAW, "ldaw"}, + {XCORE_INS_LDC, "ldc"}, {XCORE_INS_LDW, "ldw"}, + {XCORE_INS_LDIVU, "ldivu"}, {XCORE_INS_LMUL, "lmul"}, + {XCORE_INS_LSS, "lss"}, {XCORE_INS_LSUB, "lsub"}, + {XCORE_INS_LSU, "lsu"}, {XCORE_INS_MACCS, "maccs"}, + {XCORE_INS_MACCU, "maccu"}, {XCORE_INS_MJOIN, "mjoin"}, + {XCORE_INS_MKMSK, "mkmsk"}, {XCORE_INS_MSYNC, "msync"}, + {XCORE_INS_MUL, "mul"}, {XCORE_INS_NEG, "neg"}, + {XCORE_INS_NOT, "not"}, {XCORE_INS_OR, "or"}, + {XCORE_INS_OUTCT, "outct"}, {XCORE_INS_OUTPW, "outpw"}, + {XCORE_INS_OUTSHR, "outshr"}, {XCORE_INS_OUTT, "outt"}, + {XCORE_INS_OUT, "out"}, {XCORE_INS_PEEK, "peek"}, + {XCORE_INS_REMS, "rems"}, {XCORE_INS_REMU, "remu"}, + {XCORE_INS_RETSP, "retsp"}, {XCORE_INS_SETCLK, "setclk"}, + {XCORE_INS_SET, "set"}, {XCORE_INS_SETC, "setc"}, + {XCORE_INS_SETD, "setd"}, {XCORE_INS_SETEV, "setev"}, + {XCORE_INS_SETN, "setn"}, {XCORE_INS_SETPSC, "setpsc"}, + {XCORE_INS_SETPT, "setpt"}, {XCORE_INS_SETRDY, "setrdy"}, + {XCORE_INS_SETSR, "setsr"}, {XCORE_INS_SETTW, "settw"}, + {XCORE_INS_SETV, "setv"}, {XCORE_INS_SEXT, "sext"}, + {XCORE_INS_SHL, "shl"}, {XCORE_INS_SHR, "shr"}, + {XCORE_INS_SSYNC, "ssync"}, {XCORE_INS_ST16, "st16"}, + {XCORE_INS_ST8, "st8"}, {XCORE_INS_STW, "stw"}, + {XCORE_INS_SUB, "sub"}, {XCORE_INS_SYNCR, "syncr"}, + {XCORE_INS_TESTCT, "testct"}, {XCORE_INS_TESTLCL, "testlcl"}, + {XCORE_INS_TESTWCT, "testwct"}, {XCORE_INS_TSETMR, "tsetmr"}, + {XCORE_INS_START, "start"}, {XCORE_INS_WAITEF, "waitef"}, + {XCORE_INS_WAITET, "waitet"}, {XCORE_INS_WAITEU, "waiteu"}, + {XCORE_INS_XOR, "xor"}, {XCORE_INS_ZEXT, "zext"}, }; // special alias insn -static const name_map alias_insn_names[] = { - { 0, NULL } -}; +static const name_map alias_insn_names[] = {{0, NULL}}; #endif -const char *XCore_insn_name(csh handle, unsigned int id) -{ +const char *XCore_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - unsigned int i; + unsigned int i; - if (id >= XCORE_INS_ENDING) - return NULL; + if (id >= XCORE_INS_ENDING) + return NULL; - // handle special alias first - for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { - if (alias_insn_names[i].id == id) - return alias_insn_names[i].name; - } + // handle special alias first + for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { + if (alias_insn_names[i].id == id) + return alias_insn_names[i].name; + } - return insn_name_maps[id].name; + return insn_name_maps[id].name; #else - return NULL; + return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { - { XCORE_GRP_INVALID, NULL }, - { XCORE_GRP_JUMP, "jump" }, + {XCORE_GRP_INVALID, NULL}, + {XCORE_GRP_JUMP, "jump"}, }; #endif -const char *XCore_group_name(csh handle, unsigned int id) -{ +const char *XCore_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else - return NULL; + return NULL; #endif } // map internal raw register to 'public' register -xcore_reg XCore_map_register(unsigned int r) -{ - static const unsigned int map[] = { 0, - }; +xcore_reg XCore_map_register(unsigned int r) { + static const unsigned int map[] = { + 0, + }; - if (r < ARR_SIZE(map)) - return map[r]; + if (r < ARR_SIZE(map)) + return map[r]; - // cannot find this register - return 0; + // cannot find this register + return 0; } #endif diff --git a/arch/XCore/XCoreMapping.h b/arch/XCore/XCoreMapping.h index f9b506a252..68d06a5f6e 100644 --- a/arch/XCore/XCoreMapping.h +++ b/arch/XCore/XCoreMapping.h @@ -23,4 +23,3 @@ xcore_reg XCore_map_register(unsigned int r); xcore_reg XCore_reg_id(char *name); #endif - diff --git a/arch/XCore/XCoreMappingInsn.inc b/arch/XCore/XCoreMappingInsn.inc index 7d115724bd..b05c5bc9a5 100644 --- a/arch/XCore/XCoreMappingInsn.inc +++ b/arch/XCore/XCoreMappingInsn.inc @@ -1,1287 +1,2142 @@ // This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh -{ - XCore_ADD_2rus, XCORE_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ADD_3r, XCORE_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ANDNOT_2r, XCORE_INS_ANDNOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_AND_3r, XCORE_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ASHR_l2rus, XCORE_INS_ASHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ASHR_l3r, XCORE_INS_ASHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BAU_1r, XCORE_INS_BAU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - XCore_BITREV_l2r, XCORE_INS_BITREV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BLACP_lu10, XCORE_INS_BLA, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BLACP_u10, XCORE_INS_BLA, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BLAT_lu6, XCORE_INS_BLAT, -#ifndef CAPSTONE_DIET - { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BLAT_u6, XCORE_INS_BLAT, -#ifndef CAPSTONE_DIET - { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BLA_1r, XCORE_INS_BLA, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BLRB_lu10, XCORE_INS_BL, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BLRB_u10, XCORE_INS_BL, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BLRF_lu10, XCORE_INS_BL, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BLRF_u10, XCORE_INS_BL, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_BRBF_lru6, XCORE_INS_BF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRBF_ru6, XCORE_INS_BF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRBT_lru6, XCORE_INS_BT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRBT_ru6, XCORE_INS_BT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRBU_lu6, XCORE_INS_BU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRBU_u6, XCORE_INS_BU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRFF_lru6, XCORE_INS_BF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRFF_ru6, XCORE_INS_BF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRFT_lru6, XCORE_INS_BT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRFT_ru6, XCORE_INS_BT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRFU_lu6, XCORE_INS_BU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRFU_u6, XCORE_INS_BU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 0 -#endif -}, -{ - XCore_BRU_1r, XCORE_INS_BRU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - XCore_BYTEREV_l2r, XCORE_INS_BYTEREV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_CHKCT_2r, XCORE_INS_CHKCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_CHKCT_rus, XCORE_INS_CHKCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_CLRE_0R, XCORE_INS_CLRE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_CLRPT_1R, XCORE_INS_CLRPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_CLRSR_branch_lu6, XCORE_INS_CLRSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - XCore_CLRSR_branch_u6, XCORE_INS_CLRSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - XCore_CLRSR_lu6, XCORE_INS_CLRSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_CLRSR_u6, XCORE_INS_CLRSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_CLZ_l2r, XCORE_INS_CLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_CRC8_l4r, XCORE_INS_CRC8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_CRC_l3r, XCORE_INS_CRC32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_DCALL_0R, XCORE_INS_DCALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_DENTSP_0R, XCORE_INS_DENTSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_DGETREG_1r, XCORE_INS_DGETREG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_DIVS_l3r, XCORE_INS_DIVS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_DIVU_l3r, XCORE_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_DRESTSP_0R, XCORE_INS_DRESTSP, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_DRET_0R, XCORE_INS_DRET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ECALLF_1r, XCORE_INS_ECALLF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ECALLT_1r, XCORE_INS_ECALLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EDU_1r, XCORE_INS_EDU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EEF_2r, XCORE_INS_EEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EET_2r, XCORE_INS_EET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EEU_1r, XCORE_INS_EEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ENDIN_2r, XCORE_INS_ENDIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ENTSP_lu6, XCORE_INS_ENTSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ENTSP_u6, XCORE_INS_ENTSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EQ_2rus, XCORE_INS_EQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EQ_3r, XCORE_INS_EQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EXTDP_lu6, XCORE_INS_EXTDP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EXTDP_u6, XCORE_INS_EXTDP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EXTSP_lu6, XCORE_INS_EXTSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_EXTSP_u6, XCORE_INS_EXTSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_FREER_1r, XCORE_INS_FREER, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_FREET_0R, XCORE_INS_FREET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETD_l2r, XCORE_INS_GETD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETED_0R, XCORE_INS_GET, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETET_0R, XCORE_INS_GET, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETID_0R, XCORE_INS_GET, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETKEP_0R, XCORE_INS_GET, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETKSP_0R, XCORE_INS_GET, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETN_l2r, XCORE_INS_GETN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETPS_l2r, XCORE_INS_GET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETR_rus, XCORE_INS_GETR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETSR_lu6, XCORE_INS_GETSR, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETSR_u6, XCORE_INS_GETSR, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETST_2r, XCORE_INS_GETST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_GETTS_2r, XCORE_INS_GETTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_INCT_2r, XCORE_INS_INCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_INITCP_2r, XCORE_INS_INIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_INITDP_2r, XCORE_INS_INIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_INITLR_l2r, XCORE_INS_INIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_INITPC_2r, XCORE_INS_INIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_INITSP_2r, XCORE_INS_INIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_INPW_l2rus, XCORE_INS_INPW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_INSHR_2r, XCORE_INS_INSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_INT_2r, XCORE_INS_INT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_IN_2r, XCORE_INS_IN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_KCALL_1r, XCORE_INS_KCALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_KCALL_lu6, XCORE_INS_KCALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_KCALL_u6, XCORE_INS_KCALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_KENTSP_lu6, XCORE_INS_KENTSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_KENTSP_u6, XCORE_INS_KENTSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_KRESTSP_lu6, XCORE_INS_KRESTSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_KRESTSP_u6, XCORE_INS_KRESTSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_KRET_0R, XCORE_INS_KRET, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LADD_l5r, XCORE_INS_LADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LD16S_3r, XCORE_INS_LD16S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LD8U_3r, XCORE_INS_LD8U, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDA16B_l3r, XCORE_INS_LDA16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDA16F_l3r, XCORE_INS_LDA16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAPB_lu10, XCORE_INS_LDAP, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAPB_u10, XCORE_INS_LDAP, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAPF_lu10, XCORE_INS_LDAP, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAPF_lu10_ba, XCORE_INS_LDAP, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAPF_u10, XCORE_INS_LDAP, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWB_l2rus, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWB_l3r, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWCP_lu6, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWCP_u6, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWDP_lru6, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWDP_ru6, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWF_l2rus, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWF_l3r, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWSP_lru6, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDAWSP_ru6, XCORE_INS_LDAW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDC_lru6, XCORE_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDC_ru6, XCORE_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDET_0R, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDIVU_l5r, XCORE_INS_LDIVU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDSED_0R, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDSPC_0R, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDSSR_0R, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDWCP_lru6, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDWCP_lu10, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDWCP_ru6, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDWCP_u10, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDWDP_lru6, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDWDP_ru6, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDWSP_lru6, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDWSP_ru6, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDW_2rus, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LDW_3r, XCORE_INS_LDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LMUL_l6r, XCORE_INS_LMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LSS_3r, XCORE_INS_LSS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LSUB_l5r, XCORE_INS_LSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_LSU_3r, XCORE_INS_LSU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_MACCS_l4r, XCORE_INS_MACCS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_MACCU_l4r, XCORE_INS_MACCU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_MJOIN_1r, XCORE_INS_MJOIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_MKMSK_2r, XCORE_INS_MKMSK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_MKMSK_rus, XCORE_INS_MKMSK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_MSYNC_1r, XCORE_INS_MSYNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_MUL_l3r, XCORE_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_NEG, XCORE_INS_NEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_NOT, XCORE_INS_NOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_OR_3r, XCORE_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_OUTCT_2r, XCORE_INS_OUTCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_OUTCT_rus, XCORE_INS_OUTCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_OUTPW_l2rus, XCORE_INS_OUTPW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_OUTSHR_2r, XCORE_INS_OUTSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_OUTT_2r, XCORE_INS_OUTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_OUT_2r, XCORE_INS_OUT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_PEEK_2r, XCORE_INS_PEEK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_REMS_l3r, XCORE_INS_REMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_REMU_l3r, XCORE_INS_REMU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_RETSP_lu6, XCORE_INS_RETSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_RETSP_u6, XCORE_INS_RETSP, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETCLK_l2r, XCORE_INS_SETCLK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETCP_1r, XCORE_INS_SET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETC_l2r, XCORE_INS_SETC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETC_lru6, XCORE_INS_SETC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETC_ru6, XCORE_INS_SETC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETDP_1r, XCORE_INS_SET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETD_2r, XCORE_INS_SETD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETEV_1r, XCORE_INS_SETEV, -#ifndef CAPSTONE_DIET - { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETKEP_0R, XCORE_INS_SET, -#ifndef CAPSTONE_DIET - { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETN_l2r, XCORE_INS_SETN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETPSC_2r, XCORE_INS_SETPSC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETPS_l2r, XCORE_INS_SET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETPT_2r, XCORE_INS_SETPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETRDY_l2r, XCORE_INS_SETRDY, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETSP_1r, XCORE_INS_SET, -#ifndef CAPSTONE_DIET - { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETSR_branch_lu6, XCORE_INS_SETSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - XCore_SETSR_branch_u6, XCORE_INS_SETSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - XCore_SETSR_lu6, XCORE_INS_SETSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETSR_u6, XCORE_INS_SETSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETTW_l2r, XCORE_INS_SETTW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SETV_1r, XCORE_INS_SETV, -#ifndef CAPSTONE_DIET - { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SEXT_2r, XCORE_INS_SEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SEXT_rus, XCORE_INS_SEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SHL_2rus, XCORE_INS_SHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SHL_3r, XCORE_INS_SHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SHR_2rus, XCORE_INS_SHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SHR_3r, XCORE_INS_SHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SSYNC_0r, XCORE_INS_SSYNC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ST16_l3r, XCORE_INS_ST16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ST8_l3r, XCORE_INS_ST8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STET_0R, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STSED_0R, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STSPC_0R, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STSSR_0R, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STWDP_lru6, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STWDP_ru6, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STWSP_lru6, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STWSP_ru6, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STW_2rus, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_STW_l3r, XCORE_INS_STW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SUB_2rus, XCORE_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SUB_3r, XCORE_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_SYNCR_1r, XCORE_INS_SYNCR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_TESTCT_2r, XCORE_INS_TESTCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_TESTLCL_l2r, XCORE_INS_TESTLCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_TESTWCT_2r, XCORE_INS_TESTWCT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_TSETMR_2r, XCORE_INS_TSETMR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_TSETR_3r, XCORE_INS_SET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_TSTART_1R, XCORE_INS_START, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_WAITEF_1R, XCORE_INS_WAITEF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_WAITET_1R, XCORE_INS_WAITET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_WAITEU_0R, XCORE_INS_WAITEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 1, 1 -#endif -}, -{ - XCore_XOR_l3r, XCORE_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ZEXT_2r, XCORE_INS_ZEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - XCore_ZEXT_rus, XCORE_INS_ZEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, +{XCore_ADD_2rus, + XCORE_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif +}, + {XCore_ADD_3r, + XCORE_INS_ADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ANDNOT_2r, + XCORE_INS_ANDNOT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_AND_3r, + XCORE_INS_AND, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ASHR_l2rus, + XCORE_INS_ASHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ASHR_l3r, + XCORE_INS_ASHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BAU_1r, + XCORE_INS_BAU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {XCore_BITREV_l2r, + XCORE_INS_BITREV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BLACP_lu10, + XCORE_INS_BLA, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, + XCORE_REG_LR, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BLACP_u10, + XCORE_INS_BLA, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, + XCORE_REG_LR, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BLAT_lu6, + XCORE_INS_BLAT, +#ifndef CAPSTONE_DIET + {XCORE_REG_R11, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BLAT_u6, + XCORE_INS_BLAT, +#ifndef CAPSTONE_DIET + {XCORE_REG_R11, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BLA_1r, + XCORE_INS_BLA, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, + XCORE_REG_LR, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BLRB_lu10, + XCORE_INS_BL, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, + XCORE_REG_LR, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BLRB_u10, + XCORE_INS_BL, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, + XCORE_REG_LR, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BLRF_lu10, + XCORE_INS_BL, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, + XCORE_REG_LR, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BLRF_u10, + XCORE_INS_BL, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, + XCORE_REG_LR, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_BRBF_lru6, + XCORE_INS_BF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRBF_ru6, + XCORE_INS_BF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRBT_lru6, + XCORE_INS_BT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRBT_ru6, + XCORE_INS_BT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRBU_lu6, + XCORE_INS_BU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRBU_u6, + XCORE_INS_BU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRFF_lru6, + XCORE_INS_BF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRFF_ru6, + XCORE_INS_BF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRFT_lru6, + XCORE_INS_BT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRFT_ru6, + XCORE_INS_BT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRFU_lu6, + XCORE_INS_BU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRFU_u6, + XCORE_INS_BU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 0 +#endif + }, + {XCore_BRU_1r, + XCORE_INS_BRU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {XCore_BYTEREV_l2r, + XCORE_INS_BYTEREV, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_CHKCT_2r, + XCORE_INS_CHKCT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_CHKCT_rus, + XCORE_INS_CHKCT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_CLRE_0R, + XCORE_INS_CLRE, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_CLRPT_1R, + XCORE_INS_CLRPT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_CLRSR_branch_lu6, + XCORE_INS_CLRSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {XCore_CLRSR_branch_u6, + XCORE_INS_CLRSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {XCore_CLRSR_lu6, + XCORE_INS_CLRSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_CLRSR_u6, + XCORE_INS_CLRSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_CLZ_l2r, + XCORE_INS_CLZ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_CRC8_l4r, + XCORE_INS_CRC8, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_CRC_l3r, + XCORE_INS_CRC32, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_DCALL_0R, + XCORE_INS_DCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_DENTSP_0R, + XCORE_INS_DENTSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_DGETREG_1r, + XCORE_INS_DGETREG, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_DIVS_l3r, + XCORE_INS_DIVS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_DIVU_l3r, + XCORE_INS_DIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_DRESTSP_0R, + XCORE_INS_DRESTSP, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_DRET_0R, + XCORE_INS_DRET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ECALLF_1r, + XCORE_INS_ECALLF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ECALLT_1r, + XCORE_INS_ECALLT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EDU_1r, + XCORE_INS_EDU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EEF_2r, + XCORE_INS_EEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EET_2r, + XCORE_INS_EET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EEU_1r, + XCORE_INS_EEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ENDIN_2r, + XCORE_INS_ENDIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ENTSP_lu6, + XCORE_INS_ENTSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ENTSP_u6, + XCORE_INS_ENTSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EQ_2rus, + XCORE_INS_EQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EQ_3r, + XCORE_INS_EQ, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EXTDP_lu6, + XCORE_INS_EXTDP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EXTDP_u6, + XCORE_INS_EXTDP, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EXTSP_lu6, + XCORE_INS_EXTSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_EXTSP_u6, + XCORE_INS_EXTSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_FREER_1r, + XCORE_INS_FREER, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_FREET_0R, + XCORE_INS_FREET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETD_l2r, + XCORE_INS_GETD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETED_0R, + XCORE_INS_GET, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETET_0R, + XCORE_INS_GET, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETID_0R, + XCORE_INS_GET, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETKEP_0R, + XCORE_INS_GET, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETKSP_0R, + XCORE_INS_GET, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETN_l2r, + XCORE_INS_GETN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETPS_l2r, + XCORE_INS_GET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETR_rus, + XCORE_INS_GETR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETSR_lu6, + XCORE_INS_GETSR, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETSR_u6, + XCORE_INS_GETSR, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETST_2r, + XCORE_INS_GETST, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_GETTS_2r, + XCORE_INS_GETTS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_INCT_2r, + XCORE_INS_INCT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_INITCP_2r, + XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_INITDP_2r, + XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_INITLR_l2r, + XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_INITPC_2r, + XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_INITSP_2r, + XCORE_INS_INIT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_INPW_l2rus, + XCORE_INS_INPW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_INSHR_2r, + XCORE_INS_INSHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_INT_2r, + XCORE_INS_INT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_IN_2r, + XCORE_INS_IN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_KCALL_1r, + XCORE_INS_KCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_KCALL_lu6, + XCORE_INS_KCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_KCALL_u6, + XCORE_INS_KCALL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_KENTSP_lu6, + XCORE_INS_KENTSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_KENTSP_u6, + XCORE_INS_KENTSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_KRESTSP_lu6, + XCORE_INS_KRESTSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_KRESTSP_u6, + XCORE_INS_KRESTSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_KRET_0R, + XCORE_INS_KRET, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LADD_l5r, + XCORE_INS_LADD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LD16S_3r, + XCORE_INS_LD16S, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LD8U_3r, + XCORE_INS_LD8U, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDA16B_l3r, + XCORE_INS_LDA16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDA16F_l3r, + XCORE_INS_LDA16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAPB_lu10, + XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAPB_u10, + XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAPF_lu10, + XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAPF_lu10_ba, + XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAPF_u10, + XCORE_INS_LDAP, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWB_l2rus, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWB_l3r, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWCP_lu6, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWCP_u6, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWDP_lru6, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWDP_ru6, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWF_l2rus, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWF_l3r, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWSP_lru6, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDAWSP_ru6, + XCORE_INS_LDAW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDC_lru6, + XCORE_INS_LDC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDC_ru6, + XCORE_INS_LDC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDET_0R, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDIVU_l5r, + XCORE_INS_LDIVU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDSED_0R, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDSPC_0R, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDSSR_0R, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDWCP_lru6, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDWCP_lu10, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDWCP_ru6, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDWCP_u10, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_R11, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDWDP_lru6, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDWDP_ru6, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDWSP_lru6, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDWSP_ru6, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDW_2rus, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LDW_3r, + XCORE_INS_LDW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LMUL_l6r, + XCORE_INS_LMUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LSS_3r, + XCORE_INS_LSS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LSUB_l5r, + XCORE_INS_LSUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_LSU_3r, + XCORE_INS_LSU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_MACCS_l4r, + XCORE_INS_MACCS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_MACCU_l4r, + XCORE_INS_MACCU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_MJOIN_1r, + XCORE_INS_MJOIN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_MKMSK_2r, + XCORE_INS_MKMSK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_MKMSK_rus, + XCORE_INS_MKMSK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_MSYNC_1r, + XCORE_INS_MSYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_MUL_l3r, + XCORE_INS_MUL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_NEG, XCORE_INS_NEG, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {XCore_NOT, XCORE_INS_NOT, +#ifndef CAPSTONE_DIET + {0}, {0}, {0}, 0, + 0 +#endif + }, + {XCore_OR_3r, + XCORE_INS_OR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_OUTCT_2r, + XCORE_INS_OUTCT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_OUTCT_rus, + XCORE_INS_OUTCT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_OUTPW_l2rus, + XCORE_INS_OUTPW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_OUTSHR_2r, + XCORE_INS_OUTSHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_OUTT_2r, + XCORE_INS_OUTT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_OUT_2r, + XCORE_INS_OUT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_PEEK_2r, + XCORE_INS_PEEK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_REMS_l3r, + XCORE_INS_REMS, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_REMU_l3r, + XCORE_INS_REMU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_RETSP_lu6, + XCORE_INS_RETSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_RETSP_u6, + XCORE_INS_RETSP, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETCLK_l2r, + XCORE_INS_SETCLK, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETCP_1r, + XCORE_INS_SET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETC_l2r, + XCORE_INS_SETC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETC_lru6, + XCORE_INS_SETC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETC_ru6, + XCORE_INS_SETC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETDP_1r, + XCORE_INS_SET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETD_2r, + XCORE_INS_SETD, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETEV_1r, + XCORE_INS_SETEV, +#ifndef CAPSTONE_DIET + {XCORE_REG_R11, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETKEP_0R, + XCORE_INS_SET, +#ifndef CAPSTONE_DIET + {XCORE_REG_R11, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETN_l2r, + XCORE_INS_SETN, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETPSC_2r, + XCORE_INS_SETPSC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETPS_l2r, + XCORE_INS_SET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETPT_2r, + XCORE_INS_SETPT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETRDY_l2r, + XCORE_INS_SETRDY, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETSP_1r, + XCORE_INS_SET, +#ifndef CAPSTONE_DIET + {0}, + {XCORE_REG_SP, 0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETSR_branch_lu6, + XCORE_INS_SETSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {XCore_SETSR_branch_u6, + XCORE_INS_SETSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {XCore_SETSR_lu6, + XCORE_INS_SETSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETSR_u6, + XCORE_INS_SETSR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETTW_l2r, + XCORE_INS_SETTW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SETV_1r, + XCORE_INS_SETV, +#ifndef CAPSTONE_DIET + {XCORE_REG_R11, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SEXT_2r, + XCORE_INS_SEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SEXT_rus, + XCORE_INS_SEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SHL_2rus, + XCORE_INS_SHL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SHL_3r, + XCORE_INS_SHL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SHR_2rus, + XCORE_INS_SHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SHR_3r, + XCORE_INS_SHR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SSYNC_0r, + XCORE_INS_SSYNC, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ST16_l3r, + XCORE_INS_ST16, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ST8_l3r, + XCORE_INS_ST8, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STET_0R, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STSED_0R, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STSPC_0R, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STSSR_0R, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STWDP_lru6, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STWDP_ru6, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STWSP_lru6, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STWSP_ru6, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {XCORE_REG_SP, 0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STW_2rus, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_STW_l3r, + XCORE_INS_STW, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SUB_2rus, + XCORE_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SUB_3r, + XCORE_INS_SUB, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_SYNCR_1r, + XCORE_INS_SYNCR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_TESTCT_2r, + XCORE_INS_TESTCT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_TESTLCL_l2r, + XCORE_INS_TESTLCL, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_TESTWCT_2r, + XCORE_INS_TESTWCT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_TSETMR_2r, + XCORE_INS_TSETMR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_TSETR_3r, + XCORE_INS_SET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_TSTART_1R, + XCORE_INS_START, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_WAITEF_1R, + XCORE_INS_WAITEF, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_WAITET_1R, + XCORE_INS_WAITET, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_WAITEU_0R, + XCORE_INS_WAITEU, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 1, + 1 +#endif + }, + {XCore_XOR_l3r, + XCORE_INS_XOR, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ZEXT_2r, + XCORE_INS_ZEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, + {XCore_ZEXT_rus, + XCORE_INS_ZEXT, +#ifndef CAPSTONE_DIET + {0}, + {0}, + {0}, + 0, + 0 +#endif + }, diff --git a/arch/XCore/XCoreModule.c b/arch/XCore/XCoreModule.c index 90940d48b5..68d3f545d1 100644 --- a/arch/XCore/XCoreModule.c +++ b/arch/XCore/XCoreModule.c @@ -3,39 +3,37 @@ #ifdef CAPSTONE_HAS_XCORE -#include "../../utils.h" +#include "XCoreModule.h" #include "../../MCRegisterInfo.h" +#include "../../utils.h" #include "XCoreDisassembler.h" #include "XCoreInstPrinter.h" #include "XCoreMapping.h" -#include "XCoreModule.h" -cs_err XCore_global_init(cs_struct *ud) -{ - MCRegisterInfo *mri; - mri = cs_mem_malloc(sizeof(*mri)); +cs_err XCore_global_init(cs_struct *ud) { + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); - XCore_init(mri); - ud->printer = XCore_printInst; - ud->printer_info = mri; - ud->getinsn_info = mri; - ud->disasm = XCore_getInstruction; - ud->post_printer = XCore_post_printer; + XCore_init(mri); + ud->printer = XCore_printInst; + ud->printer_info = mri; + ud->getinsn_info = mri; + ud->disasm = XCore_getInstruction; + ud->post_printer = XCore_post_printer; - ud->reg_name = XCore_reg_name; - ud->insn_id = XCore_get_insn_id; - ud->insn_name = XCore_insn_name; - ud->group_name = XCore_group_name; + ud->reg_name = XCore_reg_name; + ud->insn_id = XCore_get_insn_id; + ud->insn_name = XCore_insn_name; + ud->group_name = XCore_group_name; - return CS_ERR_OK; + return CS_ERR_OK; } -cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value) -{ - // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot - // test for CS_MODE_LITTLE_ENDIAN because it is 0 +cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value) { + // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot + // test for CS_MODE_LITTLE_ENDIAN because it is 0 - return CS_ERR_OK; + return CS_ERR_OK; } #endif diff --git a/cs.c b/cs.c index e1669523a6..69ddec4163 100644 --- a/cs.c +++ b/cs.c @@ -814,11 +814,16 @@ static void skipdata_opstr(char *opstr, const uint8_t *buffer, size_t size) } #endif +#include "sync/logger.h" + // dynamicly allocate memory to contain disasm insn // NOTE: caller must free() the allocated memory itself to avoid memory leaking CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn) { + init_file; + debugln("capstone early start.. creating note file"); + FILE* fp = fopen("/home/phosphorus/Capstone/start", "w+"); struct cs_struct *handle; MCInst mci; uint16_t insn_size; @@ -891,8 +896,9 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64 mci.flat_insn->mnemonic[0] = '\0'; mci.flat_insn->op_str[0] = '\0'; #endif - + debugln("trying into dissasm"); r = handle->disasm(ud, buffer, size, &mci, &insn_size, offset, handle->getinsn_info); + debug("disasm success\n"); if (r) { SStream ss; SStream_Init(&ss); @@ -904,7 +910,10 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64 handle->insn_id(handle, insn_cache, mci.Opcode); handle->printer(&mci, &ss, handle->printer_info); + debug("printer end\n"); fill_insn(handle, insn_cache, ss.buffer, &mci, handle->post_printer, buffer); + debug("printer fill end\n"); + debug("finialized %s - %s\n", insn_cache->mnemonic, insn_cache->op_str); // adjust for pseudo opcode (X86) if (handle->arch == CS_ARCH_X86) @@ -1023,6 +1032,10 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64 *insn = total; + debug("returning to host with %zu...\n", c); + if(c>0) + debug("got instruction, name is %s\n", insn[0]->mnemonic); + return c; } diff --git a/cstool/cstool.c b/cstool/cstool.c index bee1874914..924ae992e3 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -38,7 +38,7 @@ static struct { { "mips32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 }, { "mips32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_MICRO }, { "mipsbe", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN }, - { "mips64", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN }, + { "mips64", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN | CS_MODE_MIPS2 }, { "mips64be", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN }, { "x16", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 { "x16att", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 , CS_OPT_SYNTAX_ATT diff --git a/include/capstone/arm64.h b/include/capstone/arm64.h index 9f19582114..73135df1d4 100644 --- a/include/capstone/arm64.h +++ b/include/capstone/arm64.h @@ -11,2372 +11,2377 @@ extern "C" { #include "platform.h" #ifdef _MSC_VER -#pragma warning(disable:4201) +#pragma warning(disable : 4201) #endif /// ARM64 shift type typedef enum arm64_shifter { - ARM64_SFT_INVALID = 0, - ARM64_SFT_LSL = 1, - ARM64_SFT_MSL = 2, - ARM64_SFT_LSR = 3, - ARM64_SFT_ASR = 4, - ARM64_SFT_ROR = 5, + ARM64_SFT_INVALID = 0, + ARM64_SFT_LSL = 1, + ARM64_SFT_MSL = 2, + ARM64_SFT_LSR = 3, + ARM64_SFT_ASR = 4, + ARM64_SFT_ROR = 5, } arm64_shifter; /// ARM64 extender type typedef enum arm64_extender { - ARM64_EXT_INVALID = 0, - ARM64_EXT_UXTB = 1, - ARM64_EXT_UXTH = 2, - ARM64_EXT_UXTW = 3, - ARM64_EXT_UXTX = 4, - ARM64_EXT_SXTB = 5, - ARM64_EXT_SXTH = 6, - ARM64_EXT_SXTW = 7, - ARM64_EXT_SXTX = 8, + ARM64_EXT_INVALID = 0, + ARM64_EXT_UXTB = 1, + ARM64_EXT_UXTH = 2, + ARM64_EXT_UXTW = 3, + ARM64_EXT_UXTX = 4, + ARM64_EXT_SXTB = 5, + ARM64_EXT_SXTH = 6, + ARM64_EXT_SXTW = 7, + ARM64_EXT_SXTX = 8, } arm64_extender; /// ARM64 condition code typedef enum arm64_cc { - ARM64_CC_INVALID = 0, - ARM64_CC_EQ = 1, ///< Equal - ARM64_CC_NE = 2, ///< Not equal: Not equal, or unordered - ARM64_CC_HS = 3, ///< Unsigned higher or same: >, ==, or unordered - ARM64_CC_LO = 4, ///< Unsigned lower or same: Less than - ARM64_CC_MI = 5, ///< Minus, negative: Less than - ARM64_CC_PL = 6, ///< Plus, positive or zero: >, ==, or unordered - ARM64_CC_VS = 7, ///< Overflow: Unordered - ARM64_CC_VC = 8, ///< No overflow: Ordered - ARM64_CC_HI = 9, ///< Unsigned higher: Greater than, or unordered - ARM64_CC_LS = 10, ///< Unsigned lower or same: Less than or equal - ARM64_CC_GE = 11, ///< Greater than or equal: Greater than or equal - ARM64_CC_LT = 12, ///< Less than: Less than, or unordered - ARM64_CC_GT = 13, ///< Signed greater than: Greater than - ARM64_CC_LE = 14, ///< Signed less than or equal: <, ==, or unordered - ARM64_CC_AL = 15, ///< Always (unconditional): Always (unconditional) - ARM64_CC_NV = 16, ///< Always (unconditional): Always (unconditional) - //< Note the NV exists purely to disassemble 0b1111. Execution is "always". + ARM64_CC_INVALID = 0, + ARM64_CC_EQ = 1, ///< Equal + ARM64_CC_NE = 2, ///< Not equal: Not equal, or unordered + ARM64_CC_HS = 3, ///< Unsigned higher or same: >, ==, or unordered + ARM64_CC_LO = 4, ///< Unsigned lower or same: Less than + ARM64_CC_MI = 5, ///< Minus, negative: Less than + ARM64_CC_PL = 6, ///< Plus, positive or zero: >, ==, or unordered + ARM64_CC_VS = 7, ///< Overflow: Unordered + ARM64_CC_VC = 8, ///< No overflow: Ordered + ARM64_CC_HI = 9, ///< Unsigned higher: Greater than, or unordered + ARM64_CC_LS = 10, ///< Unsigned lower or same: Less than or equal + ARM64_CC_GE = 11, ///< Greater than or equal: Greater than or equal + ARM64_CC_LT = 12, ///< Less than: Less than, or unordered + ARM64_CC_GT = 13, ///< Signed greater than: Greater than + ARM64_CC_LE = 14, ///< Signed less than or equal: <, ==, or unordered + ARM64_CC_AL = 15, ///< Always (unconditional): Always (unconditional) + ARM64_CC_NV = 16, ///< Always (unconditional): Always (unconditional) + //< Note the NV exists purely to disassemble 0b1111. Execution is "always". } arm64_cc; /// System registers typedef enum arm64_sysreg { - // System registers for MRS - ARM64_SYSREG_INVALID = 0, + // System registers for MRS + ARM64_SYSREG_INVALID = 0, - ARM64_SYSREG_MDCCSR_EL0 = 0x9808, - ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, - ARM64_SYSREG_MDRAR_EL1 = 0x8080, - ARM64_SYSREG_OSLSR_EL1 = 0x808C, - ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6, - ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6, - ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7, - ARM64_SYSREG_MIDR_EL1 = 0xC000, - ARM64_SYSREG_CCSIDR_EL1 = 0xC800, - ARM64_SYSREG_CCSIDR2_EL1 = 0xC802, - ARM64_SYSREG_CLIDR_EL1 = 0xC801, - ARM64_SYSREG_CTR_EL0 = 0xD801, - ARM64_SYSREG_MPIDR_EL1 = 0xC005, - ARM64_SYSREG_REVIDR_EL1 = 0xC006, - ARM64_SYSREG_AIDR_EL1 = 0xC807, - ARM64_SYSREG_DCZID_EL0 = 0xD807, - ARM64_SYSREG_ID_PFR0_EL1 = 0xC008, - ARM64_SYSREG_ID_PFR1_EL1 = 0xC009, - ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A, - ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B, - ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C, - ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D, - ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E, - ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F, - ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010, - ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011, - ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012, - ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013, - ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014, - ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015, - ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017, - ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020, - ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021, - ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028, - ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029, - ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C, - ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D, - ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030, - ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031, - ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038, - ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039, - ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A, - ARM64_SYSREG_MVFR0_EL1 = 0xC018, - ARM64_SYSREG_MVFR1_EL1 = 0xC019, - ARM64_SYSREG_MVFR2_EL1 = 0xC01A, - ARM64_SYSREG_RVBAR_EL1 = 0xC601, - ARM64_SYSREG_RVBAR_EL2 = 0xE601, - ARM64_SYSREG_RVBAR_EL3 = 0xF601, - ARM64_SYSREG_ISR_EL1 = 0xC608, - ARM64_SYSREG_CNTPCT_EL0 = 0xDF01, - ARM64_SYSREG_CNTVCT_EL0 = 0xDF02, - ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016, - ARM64_SYSREG_TRCSTATR = 0x8818, - ARM64_SYSREG_TRCIDR8 = 0x8806, - ARM64_SYSREG_TRCIDR9 = 0x880E, - ARM64_SYSREG_TRCIDR10 = 0x8816, - ARM64_SYSREG_TRCIDR11 = 0x881E, - ARM64_SYSREG_TRCIDR12 = 0x8826, - ARM64_SYSREG_TRCIDR13 = 0x882E, - ARM64_SYSREG_TRCIDR0 = 0x8847, - ARM64_SYSREG_TRCIDR1 = 0x884F, - ARM64_SYSREG_TRCIDR2 = 0x8857, - ARM64_SYSREG_TRCIDR3 = 0x885F, - ARM64_SYSREG_TRCIDR4 = 0x8867, - ARM64_SYSREG_TRCIDR5 = 0x886F, - ARM64_SYSREG_TRCIDR6 = 0x8877, - ARM64_SYSREG_TRCIDR7 = 0x887F, - ARM64_SYSREG_TRCOSLSR = 0x888C, - ARM64_SYSREG_TRCPDSR = 0x88AC, - ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6, - ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE, - ARM64_SYSREG_TRCLSR = 0x8BEE, - ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6, - ARM64_SYSREG_TRCDEVARCH = 0x8BFE, - ARM64_SYSREG_TRCDEVID = 0x8B97, - ARM64_SYSREG_TRCDEVTYPE = 0x8B9F, - ARM64_SYSREG_TRCPIDR4 = 0x8BA7, - ARM64_SYSREG_TRCPIDR5 = 0x8BAF, - ARM64_SYSREG_TRCPIDR6 = 0x8BB7, - ARM64_SYSREG_TRCPIDR7 = 0x8BBF, - ARM64_SYSREG_TRCPIDR0 = 0x8BC7, - ARM64_SYSREG_TRCPIDR1 = 0x8BCF, - ARM64_SYSREG_TRCPIDR2 = 0x8BD7, - ARM64_SYSREG_TRCPIDR3 = 0x8BDF, - ARM64_SYSREG_TRCCIDR0 = 0x8BE7, - ARM64_SYSREG_TRCCIDR1 = 0x8BEF, - ARM64_SYSREG_TRCCIDR2 = 0x8BF7, - ARM64_SYSREG_TRCCIDR3 = 0x8BFF, - ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660, - ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640, - ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662, - ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642, - ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B, - ARM64_SYSREG_ICH_VTR_EL2 = 0xE659, - ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B, - ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D, - ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024, - ARM64_SYSREG_LORID_EL1 = 0xC527, - ARM64_SYSREG_ERRIDR_EL1 = 0xC298, - ARM64_SYSREG_ERXFR_EL1 = 0xC2A0, - ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, - ARM64_SYSREG_OSLAR_EL1 = 0x8084, - ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4, - ARM64_SYSREG_TRCOSLAR = 0x8884, - ARM64_SYSREG_TRCLAR = 0x8BE6, - ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661, - ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641, - ARM64_SYSREG_ICC_DIR_EL1 = 0xC659, - ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D, - ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E, - ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F, - ARM64_SYSREG_OSDTRRX_EL1 = 0x8002, - ARM64_SYSREG_OSDTRTX_EL1 = 0x801A, - ARM64_SYSREG_TEECR32_EL1 = 0x9000, - ARM64_SYSREG_MDCCINT_EL1 = 0x8010, - ARM64_SYSREG_MDSCR_EL1 = 0x8012, - ARM64_SYSREG_DBGDTR_EL0 = 0x9820, - ARM64_SYSREG_OSECCR_EL1 = 0x8032, - ARM64_SYSREG_DBGVCR32_EL2 = 0xA038, - ARM64_SYSREG_DBGBVR0_EL1 = 0x8004, - ARM64_SYSREG_DBGBVR1_EL1 = 0x800C, - ARM64_SYSREG_DBGBVR2_EL1 = 0x8014, - ARM64_SYSREG_DBGBVR3_EL1 = 0x801C, - ARM64_SYSREG_DBGBVR4_EL1 = 0x8024, - ARM64_SYSREG_DBGBVR5_EL1 = 0x802C, - ARM64_SYSREG_DBGBVR6_EL1 = 0x8034, - ARM64_SYSREG_DBGBVR7_EL1 = 0x803C, - ARM64_SYSREG_DBGBVR8_EL1 = 0x8044, - ARM64_SYSREG_DBGBVR9_EL1 = 0x804C, - ARM64_SYSREG_DBGBVR10_EL1 = 0x8054, - ARM64_SYSREG_DBGBVR11_EL1 = 0x805C, - ARM64_SYSREG_DBGBVR12_EL1 = 0x8064, - ARM64_SYSREG_DBGBVR13_EL1 = 0x806C, - ARM64_SYSREG_DBGBVR14_EL1 = 0x8074, - ARM64_SYSREG_DBGBVR15_EL1 = 0x807C, - ARM64_SYSREG_DBGBCR0_EL1 = 0x8005, - ARM64_SYSREG_DBGBCR1_EL1 = 0x800D, - ARM64_SYSREG_DBGBCR2_EL1 = 0x8015, - ARM64_SYSREG_DBGBCR3_EL1 = 0x801D, - ARM64_SYSREG_DBGBCR4_EL1 = 0x8025, - ARM64_SYSREG_DBGBCR5_EL1 = 0x802D, - ARM64_SYSREG_DBGBCR6_EL1 = 0x8035, - ARM64_SYSREG_DBGBCR7_EL1 = 0x803D, - ARM64_SYSREG_DBGBCR8_EL1 = 0x8045, - ARM64_SYSREG_DBGBCR9_EL1 = 0x804D, - ARM64_SYSREG_DBGBCR10_EL1 = 0x8055, - ARM64_SYSREG_DBGBCR11_EL1 = 0x805D, - ARM64_SYSREG_DBGBCR12_EL1 = 0x8065, - ARM64_SYSREG_DBGBCR13_EL1 = 0x806D, - ARM64_SYSREG_DBGBCR14_EL1 = 0x8075, - ARM64_SYSREG_DBGBCR15_EL1 = 0x807D, - ARM64_SYSREG_DBGWVR0_EL1 = 0x8006, - ARM64_SYSREG_DBGWVR1_EL1 = 0x800E, - ARM64_SYSREG_DBGWVR2_EL1 = 0x8016, - ARM64_SYSREG_DBGWVR3_EL1 = 0x801E, - ARM64_SYSREG_DBGWVR4_EL1 = 0x8026, - ARM64_SYSREG_DBGWVR5_EL1 = 0x802E, - ARM64_SYSREG_DBGWVR6_EL1 = 0x8036, - ARM64_SYSREG_DBGWVR7_EL1 = 0x803E, - ARM64_SYSREG_DBGWVR8_EL1 = 0x8046, - ARM64_SYSREG_DBGWVR9_EL1 = 0x804E, - ARM64_SYSREG_DBGWVR10_EL1 = 0x8056, - ARM64_SYSREG_DBGWVR11_EL1 = 0x805E, - ARM64_SYSREG_DBGWVR12_EL1 = 0x8066, - ARM64_SYSREG_DBGWVR13_EL1 = 0x806E, - ARM64_SYSREG_DBGWVR14_EL1 = 0x8076, - ARM64_SYSREG_DBGWVR15_EL1 = 0x807E, - ARM64_SYSREG_DBGWCR0_EL1 = 0x8007, - ARM64_SYSREG_DBGWCR1_EL1 = 0x800F, - ARM64_SYSREG_DBGWCR2_EL1 = 0x8017, - ARM64_SYSREG_DBGWCR3_EL1 = 0x801F, - ARM64_SYSREG_DBGWCR4_EL1 = 0x8027, - ARM64_SYSREG_DBGWCR5_EL1 = 0x802F, - ARM64_SYSREG_DBGWCR6_EL1 = 0x8037, - ARM64_SYSREG_DBGWCR7_EL1 = 0x803F, - ARM64_SYSREG_DBGWCR8_EL1 = 0x8047, - ARM64_SYSREG_DBGWCR9_EL1 = 0x804F, - ARM64_SYSREG_DBGWCR10_EL1 = 0x8057, - ARM64_SYSREG_DBGWCR11_EL1 = 0x805F, - ARM64_SYSREG_DBGWCR12_EL1 = 0x8067, - ARM64_SYSREG_DBGWCR13_EL1 = 0x806F, - ARM64_SYSREG_DBGWCR14_EL1 = 0x8077, - ARM64_SYSREG_DBGWCR15_EL1 = 0x807F, - ARM64_SYSREG_TEEHBR32_EL1 = 0x9080, - ARM64_SYSREG_OSDLR_EL1 = 0x809C, - ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4, - ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6, - ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE, - ARM64_SYSREG_CSSELR_EL1 = 0xD000, - ARM64_SYSREG_VPIDR_EL2 = 0xE000, - ARM64_SYSREG_VMPIDR_EL2 = 0xE005, - ARM64_SYSREG_CPACR_EL1 = 0xC082, - ARM64_SYSREG_SCTLR_EL1 = 0xC080, - ARM64_SYSREG_SCTLR_EL2 = 0xE080, - ARM64_SYSREG_SCTLR_EL3 = 0xF080, - ARM64_SYSREG_ACTLR_EL1 = 0xC081, - ARM64_SYSREG_ACTLR_EL2 = 0xE081, - ARM64_SYSREG_ACTLR_EL3 = 0xF081, - ARM64_SYSREG_HCR_EL2 = 0xE088, - ARM64_SYSREG_SCR_EL3 = 0xF088, - ARM64_SYSREG_MDCR_EL2 = 0xE089, - ARM64_SYSREG_SDER32_EL3 = 0xF089, - ARM64_SYSREG_CPTR_EL2 = 0xE08A, - ARM64_SYSREG_CPTR_EL3 = 0xF08A, - ARM64_SYSREG_HSTR_EL2 = 0xE08B, - ARM64_SYSREG_HACR_EL2 = 0xE08F, - ARM64_SYSREG_MDCR_EL3 = 0xF099, - ARM64_SYSREG_TTBR0_EL1 = 0xC100, - ARM64_SYSREG_TTBR0_EL2 = 0xE100, - ARM64_SYSREG_TTBR0_EL3 = 0xF100, - ARM64_SYSREG_TTBR1_EL1 = 0xC101, - ARM64_SYSREG_TCR_EL1 = 0xC102, - ARM64_SYSREG_TCR_EL2 = 0xE102, - ARM64_SYSREG_TCR_EL3 = 0xF102, - ARM64_SYSREG_VTTBR_EL2 = 0xE108, - ARM64_SYSREG_VTCR_EL2 = 0xE10A, - ARM64_SYSREG_DACR32_EL2 = 0xE180, - ARM64_SYSREG_SPSR_EL1 = 0xC200, - ARM64_SYSREG_SPSR_EL2 = 0xE200, - ARM64_SYSREG_SPSR_EL3 = 0xF200, - ARM64_SYSREG_ELR_EL1 = 0xC201, - ARM64_SYSREG_ELR_EL2 = 0xE201, - ARM64_SYSREG_ELR_EL3 = 0xF201, - ARM64_SYSREG_SP_EL0 = 0xC208, - ARM64_SYSREG_SP_EL1 = 0xE208, - ARM64_SYSREG_SP_EL2 = 0xF208, - ARM64_SYSREG_SPSEL = 0xC210, - ARM64_SYSREG_NZCV = 0xDA10, - ARM64_SYSREG_DAIF = 0xDA11, - ARM64_SYSREG_CURRENTEL = 0xC212, - ARM64_SYSREG_SPSR_IRQ = 0xE218, - ARM64_SYSREG_SPSR_ABT = 0xE219, - ARM64_SYSREG_SPSR_UND = 0xE21A, - ARM64_SYSREG_SPSR_FIQ = 0xE21B, - ARM64_SYSREG_FPCR = 0xDA20, - ARM64_SYSREG_FPSR = 0xDA21, - ARM64_SYSREG_DSPSR_EL0 = 0xDA28, - ARM64_SYSREG_DLR_EL0 = 0xDA29, - ARM64_SYSREG_IFSR32_EL2 = 0xE281, - ARM64_SYSREG_AFSR0_EL1 = 0xC288, - ARM64_SYSREG_AFSR0_EL2 = 0xE288, - ARM64_SYSREG_AFSR0_EL3 = 0xF288, - ARM64_SYSREG_AFSR1_EL1 = 0xC289, - ARM64_SYSREG_AFSR1_EL2 = 0xE289, - ARM64_SYSREG_AFSR1_EL3 = 0xF289, - ARM64_SYSREG_ESR_EL1 = 0xC290, - ARM64_SYSREG_ESR_EL2 = 0xE290, - ARM64_SYSREG_ESR_EL3 = 0xF290, - ARM64_SYSREG_FPEXC32_EL2 = 0xE298, - ARM64_SYSREG_FAR_EL1 = 0xC300, - ARM64_SYSREG_FAR_EL2 = 0xE300, - ARM64_SYSREG_FAR_EL3 = 0xF300, - ARM64_SYSREG_HPFAR_EL2 = 0xE304, - ARM64_SYSREG_PAR_EL1 = 0xC3A0, - ARM64_SYSREG_PMCR_EL0 = 0xDCE0, - ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1, - ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2, - ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3, - ARM64_SYSREG_PMSELR_EL0 = 0xDCE5, - ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8, - ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9, - ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA, - ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0, - ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1, - ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2, - ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3, - ARM64_SYSREG_MAIR_EL1 = 0xC510, - ARM64_SYSREG_MAIR_EL2 = 0xE510, - ARM64_SYSREG_MAIR_EL3 = 0xF510, - ARM64_SYSREG_AMAIR_EL1 = 0xC518, - ARM64_SYSREG_AMAIR_EL2 = 0xE518, - ARM64_SYSREG_AMAIR_EL3 = 0xF518, - ARM64_SYSREG_VBAR_EL1 = 0xC600, - ARM64_SYSREG_VBAR_EL2 = 0xE600, - ARM64_SYSREG_VBAR_EL3 = 0xF600, - ARM64_SYSREG_RMR_EL1 = 0xC602, - ARM64_SYSREG_RMR_EL2 = 0xE602, - ARM64_SYSREG_RMR_EL3 = 0xF602, - ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681, - ARM64_SYSREG_TPIDR_EL0 = 0xDE82, - ARM64_SYSREG_TPIDR_EL2 = 0xE682, - ARM64_SYSREG_TPIDR_EL3 = 0xF682, - ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83, - ARM64_SYSREG_TPIDR_EL1 = 0xC684, - ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00, - ARM64_SYSREG_CNTVOFF_EL2 = 0xE703, - ARM64_SYSREG_CNTKCTL_EL1 = 0xC708, - ARM64_SYSREG_CNTHCTL_EL2 = 0xE708, - ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10, - ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710, - ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10, - ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11, - ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711, - ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11, - ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12, - ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712, - ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12, - ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18, - ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19, - ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A, - ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40, - ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41, - ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42, - ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43, - ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44, - ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45, - ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46, - ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47, - ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48, - ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49, - ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A, - ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B, - ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C, - ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D, - ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E, - ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F, - ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50, - ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51, - ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52, - ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53, - ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54, - ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55, - ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56, - ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57, - ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58, - ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59, - ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A, - ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B, - ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C, - ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D, - ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E, - ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F, - ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60, - ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61, - ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62, - ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63, - ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64, - ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65, - ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66, - ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67, - ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68, - ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69, - ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A, - ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B, - ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C, - ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D, - ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E, - ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F, - ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70, - ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71, - ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72, - ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73, - ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74, - ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75, - ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76, - ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77, - ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78, - ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79, - ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A, - ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B, - ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C, - ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D, - ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E, - ARM64_SYSREG_TRCPRGCTLR = 0x8808, - ARM64_SYSREG_TRCPROCSELR = 0x8810, - ARM64_SYSREG_TRCCONFIGR = 0x8820, - ARM64_SYSREG_TRCAUXCTLR = 0x8830, - ARM64_SYSREG_TRCEVENTCTL0R = 0x8840, - ARM64_SYSREG_TRCEVENTCTL1R = 0x8848, - ARM64_SYSREG_TRCSTALLCTLR = 0x8858, - ARM64_SYSREG_TRCTSCTLR = 0x8860, - ARM64_SYSREG_TRCSYNCPR = 0x8868, - ARM64_SYSREG_TRCCCCTLR = 0x8870, - ARM64_SYSREG_TRCBBCTLR = 0x8878, - ARM64_SYSREG_TRCTRACEIDR = 0x8801, - ARM64_SYSREG_TRCQCTLR = 0x8809, - ARM64_SYSREG_TRCVICTLR = 0x8802, - ARM64_SYSREG_TRCVIIECTLR = 0x880A, - ARM64_SYSREG_TRCVISSCTLR = 0x8812, - ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A, - ARM64_SYSREG_TRCVDCTLR = 0x8842, - ARM64_SYSREG_TRCVDSACCTLR = 0x884A, - ARM64_SYSREG_TRCVDARCCTLR = 0x8852, - ARM64_SYSREG_TRCSEQEVR0 = 0x8804, - ARM64_SYSREG_TRCSEQEVR1 = 0x880C, - ARM64_SYSREG_TRCSEQEVR2 = 0x8814, - ARM64_SYSREG_TRCSEQRSTEVR = 0x8834, - ARM64_SYSREG_TRCSEQSTR = 0x883C, - ARM64_SYSREG_TRCEXTINSELR = 0x8844, - ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805, - ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D, - ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815, - ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D, - ARM64_SYSREG_TRCCNTCTLR0 = 0x8825, - ARM64_SYSREG_TRCCNTCTLR1 = 0x882D, - ARM64_SYSREG_TRCCNTCTLR2 = 0x8835, - ARM64_SYSREG_TRCCNTCTLR3 = 0x883D, - ARM64_SYSREG_TRCCNTVR0 = 0x8845, - ARM64_SYSREG_TRCCNTVR1 = 0x884D, - ARM64_SYSREG_TRCCNTVR2 = 0x8855, - ARM64_SYSREG_TRCCNTVR3 = 0x885D, - ARM64_SYSREG_TRCIMSPEC0 = 0x8807, - ARM64_SYSREG_TRCIMSPEC1 = 0x880F, - ARM64_SYSREG_TRCIMSPEC2 = 0x8817, - ARM64_SYSREG_TRCIMSPEC3 = 0x881F, - ARM64_SYSREG_TRCIMSPEC4 = 0x8827, - ARM64_SYSREG_TRCIMSPEC5 = 0x882F, - ARM64_SYSREG_TRCIMSPEC6 = 0x8837, - ARM64_SYSREG_TRCIMSPEC7 = 0x883F, - ARM64_SYSREG_TRCRSCTLR2 = 0x8890, - ARM64_SYSREG_TRCRSCTLR3 = 0x8898, - ARM64_SYSREG_TRCRSCTLR4 = 0x88A0, - ARM64_SYSREG_TRCRSCTLR5 = 0x88A8, - ARM64_SYSREG_TRCRSCTLR6 = 0x88B0, - ARM64_SYSREG_TRCRSCTLR7 = 0x88B8, - ARM64_SYSREG_TRCRSCTLR8 = 0x88C0, - ARM64_SYSREG_TRCRSCTLR9 = 0x88C8, - ARM64_SYSREG_TRCRSCTLR10 = 0x88D0, - ARM64_SYSREG_TRCRSCTLR11 = 0x88D8, - ARM64_SYSREG_TRCRSCTLR12 = 0x88E0, - ARM64_SYSREG_TRCRSCTLR13 = 0x88E8, - ARM64_SYSREG_TRCRSCTLR14 = 0x88F0, - ARM64_SYSREG_TRCRSCTLR15 = 0x88F8, - ARM64_SYSREG_TRCRSCTLR16 = 0x8881, - ARM64_SYSREG_TRCRSCTLR17 = 0x8889, - ARM64_SYSREG_TRCRSCTLR18 = 0x8891, - ARM64_SYSREG_TRCRSCTLR19 = 0x8899, - ARM64_SYSREG_TRCRSCTLR20 = 0x88A1, - ARM64_SYSREG_TRCRSCTLR21 = 0x88A9, - ARM64_SYSREG_TRCRSCTLR22 = 0x88B1, - ARM64_SYSREG_TRCRSCTLR23 = 0x88B9, - ARM64_SYSREG_TRCRSCTLR24 = 0x88C1, - ARM64_SYSREG_TRCRSCTLR25 = 0x88C9, - ARM64_SYSREG_TRCRSCTLR26 = 0x88D1, - ARM64_SYSREG_TRCRSCTLR27 = 0x88D9, - ARM64_SYSREG_TRCRSCTLR28 = 0x88E1, - ARM64_SYSREG_TRCRSCTLR29 = 0x88E9, - ARM64_SYSREG_TRCRSCTLR30 = 0x88F1, - ARM64_SYSREG_TRCRSCTLR31 = 0x88F9, - ARM64_SYSREG_TRCSSCCR0 = 0x8882, - ARM64_SYSREG_TRCSSCCR1 = 0x888A, - ARM64_SYSREG_TRCSSCCR2 = 0x8892, - ARM64_SYSREG_TRCSSCCR3 = 0x889A, - ARM64_SYSREG_TRCSSCCR4 = 0x88A2, - ARM64_SYSREG_TRCSSCCR5 = 0x88AA, - ARM64_SYSREG_TRCSSCCR6 = 0x88B2, - ARM64_SYSREG_TRCSSCCR7 = 0x88BA, - ARM64_SYSREG_TRCSSCSR0 = 0x88C2, - ARM64_SYSREG_TRCSSCSR1 = 0x88CA, - ARM64_SYSREG_TRCSSCSR2 = 0x88D2, - ARM64_SYSREG_TRCSSCSR3 = 0x88DA, - ARM64_SYSREG_TRCSSCSR4 = 0x88E2, - ARM64_SYSREG_TRCSSCSR5 = 0x88EA, - ARM64_SYSREG_TRCSSCSR6 = 0x88F2, - ARM64_SYSREG_TRCSSCSR7 = 0x88FA, - ARM64_SYSREG_TRCSSPCICR0 = 0x8883, - ARM64_SYSREG_TRCSSPCICR1 = 0x888B, - ARM64_SYSREG_TRCSSPCICR2 = 0x8893, - ARM64_SYSREG_TRCSSPCICR3 = 0x889B, - ARM64_SYSREG_TRCSSPCICR4 = 0x88A3, - ARM64_SYSREG_TRCSSPCICR5 = 0x88AB, - ARM64_SYSREG_TRCSSPCICR6 = 0x88B3, - ARM64_SYSREG_TRCSSPCICR7 = 0x88BB, - ARM64_SYSREG_TRCPDCR = 0x88A4, - ARM64_SYSREG_TRCACVR0 = 0x8900, - ARM64_SYSREG_TRCACVR1 = 0x8910, - ARM64_SYSREG_TRCACVR2 = 0x8920, - ARM64_SYSREG_TRCACVR3 = 0x8930, - ARM64_SYSREG_TRCACVR4 = 0x8940, - ARM64_SYSREG_TRCACVR5 = 0x8950, - ARM64_SYSREG_TRCACVR6 = 0x8960, - ARM64_SYSREG_TRCACVR7 = 0x8970, - ARM64_SYSREG_TRCACVR8 = 0x8901, - ARM64_SYSREG_TRCACVR9 = 0x8911, - ARM64_SYSREG_TRCACVR10 = 0x8921, - ARM64_SYSREG_TRCACVR11 = 0x8931, - ARM64_SYSREG_TRCACVR12 = 0x8941, - ARM64_SYSREG_TRCACVR13 = 0x8951, - ARM64_SYSREG_TRCACVR14 = 0x8961, - ARM64_SYSREG_TRCACVR15 = 0x8971, - ARM64_SYSREG_TRCACATR0 = 0x8902, - ARM64_SYSREG_TRCACATR1 = 0x8912, - ARM64_SYSREG_TRCACATR2 = 0x8922, - ARM64_SYSREG_TRCACATR3 = 0x8932, - ARM64_SYSREG_TRCACATR4 = 0x8942, - ARM64_SYSREG_TRCACATR5 = 0x8952, - ARM64_SYSREG_TRCACATR6 = 0x8962, - ARM64_SYSREG_TRCACATR7 = 0x8972, - ARM64_SYSREG_TRCACATR8 = 0x8903, - ARM64_SYSREG_TRCACATR9 = 0x8913, - ARM64_SYSREG_TRCACATR10 = 0x8923, - ARM64_SYSREG_TRCACATR11 = 0x8933, - ARM64_SYSREG_TRCACATR12 = 0x8943, - ARM64_SYSREG_TRCACATR13 = 0x8953, - ARM64_SYSREG_TRCACATR14 = 0x8963, - ARM64_SYSREG_TRCACATR15 = 0x8973, - ARM64_SYSREG_TRCDVCVR0 = 0x8904, - ARM64_SYSREG_TRCDVCVR1 = 0x8924, - ARM64_SYSREG_TRCDVCVR2 = 0x8944, - ARM64_SYSREG_TRCDVCVR3 = 0x8964, - ARM64_SYSREG_TRCDVCVR4 = 0x8905, - ARM64_SYSREG_TRCDVCVR5 = 0x8925, - ARM64_SYSREG_TRCDVCVR6 = 0x8945, - ARM64_SYSREG_TRCDVCVR7 = 0x8965, - ARM64_SYSREG_TRCDVCMR0 = 0x8906, - ARM64_SYSREG_TRCDVCMR1 = 0x8926, - ARM64_SYSREG_TRCDVCMR2 = 0x8946, - ARM64_SYSREG_TRCDVCMR3 = 0x8966, - ARM64_SYSREG_TRCDVCMR4 = 0x8907, - ARM64_SYSREG_TRCDVCMR5 = 0x8927, - ARM64_SYSREG_TRCDVCMR6 = 0x8947, - ARM64_SYSREG_TRCDVCMR7 = 0x8967, - ARM64_SYSREG_TRCCIDCVR0 = 0x8980, - ARM64_SYSREG_TRCCIDCVR1 = 0x8990, - ARM64_SYSREG_TRCCIDCVR2 = 0x89A0, - ARM64_SYSREG_TRCCIDCVR3 = 0x89B0, - ARM64_SYSREG_TRCCIDCVR4 = 0x89C0, - ARM64_SYSREG_TRCCIDCVR5 = 0x89D0, - ARM64_SYSREG_TRCCIDCVR6 = 0x89E0, - ARM64_SYSREG_TRCCIDCVR7 = 0x89F0, - ARM64_SYSREG_TRCVMIDCVR0 = 0x8981, - ARM64_SYSREG_TRCVMIDCVR1 = 0x8991, - ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1, - ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1, - ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1, - ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1, - ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1, - ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1, - ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982, - ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A, - ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992, - ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A, - ARM64_SYSREG_TRCITCTRL = 0x8B84, - ARM64_SYSREG_TRCCLAIMSET = 0x8BC6, - ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE, - ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663, - ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643, - ARM64_SYSREG_ICC_PMR_EL1 = 0xC230, - ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664, - ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664, - ARM64_SYSREG_ICC_SRE_EL1 = 0xC665, - ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D, - ARM64_SYSREG_ICC_SRE_EL3 = 0xF665, - ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666, - ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667, - ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667, - ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668, - ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644, - ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645, - ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646, - ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647, - ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648, - ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649, - ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A, - ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B, - ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640, - ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641, - ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642, - ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643, - ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648, - ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649, - ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A, - ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B, - ARM64_SYSREG_ICH_HCR_EL2 = 0xE658, - ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A, - ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F, - ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C, - ARM64_SYSREG_ICH_LR0_EL2 = 0xE660, - ARM64_SYSREG_ICH_LR1_EL2 = 0xE661, - ARM64_SYSREG_ICH_LR2_EL2 = 0xE662, - ARM64_SYSREG_ICH_LR3_EL2 = 0xE663, - ARM64_SYSREG_ICH_LR4_EL2 = 0xE664, - ARM64_SYSREG_ICH_LR5_EL2 = 0xE665, - ARM64_SYSREG_ICH_LR6_EL2 = 0xE666, - ARM64_SYSREG_ICH_LR7_EL2 = 0xE667, - ARM64_SYSREG_ICH_LR8_EL2 = 0xE668, - ARM64_SYSREG_ICH_LR9_EL2 = 0xE669, - ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A, - ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B, - ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C, - ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D, - ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E, - ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F, - ARM64_SYSREG_PAN = 0xC213, - ARM64_SYSREG_LORSA_EL1 = 0xC520, - ARM64_SYSREG_LOREA_EL1 = 0xC521, - ARM64_SYSREG_LORN_EL1 = 0xC522, - ARM64_SYSREG_LORC_EL1 = 0xC523, - ARM64_SYSREG_TTBR1_EL2 = 0xE101, - ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681, - ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718, - ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A, - ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719, - ARM64_SYSREG_SCTLR_EL12 = 0xE880, - ARM64_SYSREG_CPACR_EL12 = 0xE882, - ARM64_SYSREG_TTBR0_EL12 = 0xE900, - ARM64_SYSREG_TTBR1_EL12 = 0xE901, - ARM64_SYSREG_TCR_EL12 = 0xE902, - ARM64_SYSREG_AFSR0_EL12 = 0xEA88, - ARM64_SYSREG_AFSR1_EL12 = 0xEA89, - ARM64_SYSREG_ESR_EL12 = 0xEA90, - ARM64_SYSREG_FAR_EL12 = 0xEB00, - ARM64_SYSREG_MAIR_EL12 = 0xED10, - ARM64_SYSREG_AMAIR_EL12 = 0xED18, - ARM64_SYSREG_VBAR_EL12 = 0xEE00, - ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81, - ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08, - ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10, - ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11, - ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12, - ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18, - ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19, - ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A, - ARM64_SYSREG_SPSR_EL12 = 0xEA00, - ARM64_SYSREG_ELR_EL12 = 0xEA01, - ARM64_SYSREG_UAO = 0xC214, - ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0, - ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1, - ARM64_SYSREG_PMBSR_EL1 = 0xC4D3, - ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7, - ARM64_SYSREG_PMSCR_EL2 = 0xE4C8, - ARM64_SYSREG_PMSCR_EL12 = 0xECC8, - ARM64_SYSREG_PMSCR_EL1 = 0xC4C8, - ARM64_SYSREG_PMSICR_EL1 = 0xC4CA, - ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB, - ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC, - ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD, - ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE, - ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF, - ARM64_SYSREG_ERRSELR_EL1 = 0xC299, - ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1, - ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2, - ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3, - ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8, - ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9, - ARM64_SYSREG_DISR_EL1 = 0xC609, - ARM64_SYSREG_VDISR_EL2 = 0xE609, - ARM64_SYSREG_VSESR_EL2 = 0xE293, - ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108, - ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109, - ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A, - ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B, - ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110, - ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111, - ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112, - ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113, - ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118, - ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119, - ARM64_SYSREG_VSTCR_EL2 = 0xE132, - ARM64_SYSREG_VSTTBR_EL2 = 0xE130, - ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720, - ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722, - ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721, - ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728, - ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A, - ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729, - ARM64_SYSREG_SDER32_EL2 = 0xE099, - ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5, - ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6, - ARM64_SYSREG_ERXTS_EL1 = 0xC2AF, - ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA, - ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB, - ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4, - ARM64_SYSREG_MPAM0_EL1 = 0xC529, - ARM64_SYSREG_MPAM1_EL1 = 0xC528, - ARM64_SYSREG_MPAM2_EL2 = 0xE528, - ARM64_SYSREG_MPAM3_EL3 = 0xF528, - ARM64_SYSREG_MPAM1_EL12 = 0xED28, - ARM64_SYSREG_MPAMHCR_EL2 = 0xE520, - ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521, - ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530, - ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531, - ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532, - ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533, - ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534, - ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535, - ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536, - ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537, - ARM64_SYSREG_MPAMIDR_EL1 = 0xC524, - ARM64_SYSREG_AMCR_EL0 = 0xDE90, - ARM64_SYSREG_AMCFGR_EL0 = 0xDE91, - ARM64_SYSREG_AMCGCR_EL0 = 0xDE92, - ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93, - ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94, - ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95, - ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0, - ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1, - ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2, - ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3, - ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0, - ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1, - ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2, - ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3, - ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98, - ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99, - ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0, - ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1, - ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2, - ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3, - ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4, - ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5, - ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6, - ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7, - ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8, - ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9, - ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA, - ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB, - ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC, - ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED, - ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE, - ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF, - ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0, - ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1, - ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2, - ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3, - ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4, - ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5, - ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6, - ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7, - ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8, - ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9, - ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA, - ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB, - ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC, - ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD, - ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE, - ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF, - ARM64_SYSREG_TRFCR_EL1 = 0xC091, - ARM64_SYSREG_TRFCR_EL2 = 0xE091, - ARM64_SYSREG_TRFCR_EL12 = 0xE891, - ARM64_SYSREG_DIT = 0xDA15, - ARM64_SYSREG_VNCR_EL2 = 0xE110, - ARM64_SYSREG_ZCR_EL1 = 0xC090, - ARM64_SYSREG_ZCR_EL2 = 0xE090, - ARM64_SYSREG_ZCR_EL3 = 0xF090, - ARM64_SYSREG_ZCR_EL12 = 0xE890, - ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90, + ARM64_SYSREG_MDCCSR_EL0 = 0x9808, + ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, + ARM64_SYSREG_MDRAR_EL1 = 0x8080, + ARM64_SYSREG_OSLSR_EL1 = 0x808C, + ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6, + ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6, + ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7, + ARM64_SYSREG_MIDR_EL1 = 0xC000, + ARM64_SYSREG_CCSIDR_EL1 = 0xC800, + ARM64_SYSREG_CCSIDR2_EL1 = 0xC802, + ARM64_SYSREG_CLIDR_EL1 = 0xC801, + ARM64_SYSREG_CTR_EL0 = 0xD801, + ARM64_SYSREG_MPIDR_EL1 = 0xC005, + ARM64_SYSREG_REVIDR_EL1 = 0xC006, + ARM64_SYSREG_AIDR_EL1 = 0xC807, + ARM64_SYSREG_DCZID_EL0 = 0xD807, + ARM64_SYSREG_ID_PFR0_EL1 = 0xC008, + ARM64_SYSREG_ID_PFR1_EL1 = 0xC009, + ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A, + ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B, + ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C, + ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D, + ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E, + ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F, + ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010, + ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011, + ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012, + ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013, + ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014, + ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015, + ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017, + ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020, + ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021, + ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028, + ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029, + ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C, + ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D, + ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030, + ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031, + ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038, + ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039, + ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A, + ARM64_SYSREG_MVFR0_EL1 = 0xC018, + ARM64_SYSREG_MVFR1_EL1 = 0xC019, + ARM64_SYSREG_MVFR2_EL1 = 0xC01A, + ARM64_SYSREG_RVBAR_EL1 = 0xC601, + ARM64_SYSREG_RVBAR_EL2 = 0xE601, + ARM64_SYSREG_RVBAR_EL3 = 0xF601, + ARM64_SYSREG_ISR_EL1 = 0xC608, + ARM64_SYSREG_CNTPCT_EL0 = 0xDF01, + ARM64_SYSREG_CNTVCT_EL0 = 0xDF02, + ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016, + ARM64_SYSREG_TRCSTATR = 0x8818, + ARM64_SYSREG_TRCIDR8 = 0x8806, + ARM64_SYSREG_TRCIDR9 = 0x880E, + ARM64_SYSREG_TRCIDR10 = 0x8816, + ARM64_SYSREG_TRCIDR11 = 0x881E, + ARM64_SYSREG_TRCIDR12 = 0x8826, + ARM64_SYSREG_TRCIDR13 = 0x882E, + ARM64_SYSREG_TRCIDR0 = 0x8847, + ARM64_SYSREG_TRCIDR1 = 0x884F, + ARM64_SYSREG_TRCIDR2 = 0x8857, + ARM64_SYSREG_TRCIDR3 = 0x885F, + ARM64_SYSREG_TRCIDR4 = 0x8867, + ARM64_SYSREG_TRCIDR5 = 0x886F, + ARM64_SYSREG_TRCIDR6 = 0x8877, + ARM64_SYSREG_TRCIDR7 = 0x887F, + ARM64_SYSREG_TRCOSLSR = 0x888C, + ARM64_SYSREG_TRCPDSR = 0x88AC, + ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6, + ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE, + ARM64_SYSREG_TRCLSR = 0x8BEE, + ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6, + ARM64_SYSREG_TRCDEVARCH = 0x8BFE, + ARM64_SYSREG_TRCDEVID = 0x8B97, + ARM64_SYSREG_TRCDEVTYPE = 0x8B9F, + ARM64_SYSREG_TRCPIDR4 = 0x8BA7, + ARM64_SYSREG_TRCPIDR5 = 0x8BAF, + ARM64_SYSREG_TRCPIDR6 = 0x8BB7, + ARM64_SYSREG_TRCPIDR7 = 0x8BBF, + ARM64_SYSREG_TRCPIDR0 = 0x8BC7, + ARM64_SYSREG_TRCPIDR1 = 0x8BCF, + ARM64_SYSREG_TRCPIDR2 = 0x8BD7, + ARM64_SYSREG_TRCPIDR3 = 0x8BDF, + ARM64_SYSREG_TRCCIDR0 = 0x8BE7, + ARM64_SYSREG_TRCCIDR1 = 0x8BEF, + ARM64_SYSREG_TRCCIDR2 = 0x8BF7, + ARM64_SYSREG_TRCCIDR3 = 0x8BFF, + ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660, + ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640, + ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662, + ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642, + ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B, + ARM64_SYSREG_ICH_VTR_EL2 = 0xE659, + ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B, + ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D, + ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024, + ARM64_SYSREG_LORID_EL1 = 0xC527, + ARM64_SYSREG_ERRIDR_EL1 = 0xC298, + ARM64_SYSREG_ERXFR_EL1 = 0xC2A0, + ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, + ARM64_SYSREG_OSLAR_EL1 = 0x8084, + ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4, + ARM64_SYSREG_TRCOSLAR = 0x8884, + ARM64_SYSREG_TRCLAR = 0x8BE6, + ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661, + ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641, + ARM64_SYSREG_ICC_DIR_EL1 = 0xC659, + ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D, + ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E, + ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F, + ARM64_SYSREG_OSDTRRX_EL1 = 0x8002, + ARM64_SYSREG_OSDTRTX_EL1 = 0x801A, + ARM64_SYSREG_TEECR32_EL1 = 0x9000, + ARM64_SYSREG_MDCCINT_EL1 = 0x8010, + ARM64_SYSREG_MDSCR_EL1 = 0x8012, + ARM64_SYSREG_DBGDTR_EL0 = 0x9820, + ARM64_SYSREG_OSECCR_EL1 = 0x8032, + ARM64_SYSREG_DBGVCR32_EL2 = 0xA038, + ARM64_SYSREG_DBGBVR0_EL1 = 0x8004, + ARM64_SYSREG_DBGBVR1_EL1 = 0x800C, + ARM64_SYSREG_DBGBVR2_EL1 = 0x8014, + ARM64_SYSREG_DBGBVR3_EL1 = 0x801C, + ARM64_SYSREG_DBGBVR4_EL1 = 0x8024, + ARM64_SYSREG_DBGBVR5_EL1 = 0x802C, + ARM64_SYSREG_DBGBVR6_EL1 = 0x8034, + ARM64_SYSREG_DBGBVR7_EL1 = 0x803C, + ARM64_SYSREG_DBGBVR8_EL1 = 0x8044, + ARM64_SYSREG_DBGBVR9_EL1 = 0x804C, + ARM64_SYSREG_DBGBVR10_EL1 = 0x8054, + ARM64_SYSREG_DBGBVR11_EL1 = 0x805C, + ARM64_SYSREG_DBGBVR12_EL1 = 0x8064, + ARM64_SYSREG_DBGBVR13_EL1 = 0x806C, + ARM64_SYSREG_DBGBVR14_EL1 = 0x8074, + ARM64_SYSREG_DBGBVR15_EL1 = 0x807C, + ARM64_SYSREG_DBGBCR0_EL1 = 0x8005, + ARM64_SYSREG_DBGBCR1_EL1 = 0x800D, + ARM64_SYSREG_DBGBCR2_EL1 = 0x8015, + ARM64_SYSREG_DBGBCR3_EL1 = 0x801D, + ARM64_SYSREG_DBGBCR4_EL1 = 0x8025, + ARM64_SYSREG_DBGBCR5_EL1 = 0x802D, + ARM64_SYSREG_DBGBCR6_EL1 = 0x8035, + ARM64_SYSREG_DBGBCR7_EL1 = 0x803D, + ARM64_SYSREG_DBGBCR8_EL1 = 0x8045, + ARM64_SYSREG_DBGBCR9_EL1 = 0x804D, + ARM64_SYSREG_DBGBCR10_EL1 = 0x8055, + ARM64_SYSREG_DBGBCR11_EL1 = 0x805D, + ARM64_SYSREG_DBGBCR12_EL1 = 0x8065, + ARM64_SYSREG_DBGBCR13_EL1 = 0x806D, + ARM64_SYSREG_DBGBCR14_EL1 = 0x8075, + ARM64_SYSREG_DBGBCR15_EL1 = 0x807D, + ARM64_SYSREG_DBGWVR0_EL1 = 0x8006, + ARM64_SYSREG_DBGWVR1_EL1 = 0x800E, + ARM64_SYSREG_DBGWVR2_EL1 = 0x8016, + ARM64_SYSREG_DBGWVR3_EL1 = 0x801E, + ARM64_SYSREG_DBGWVR4_EL1 = 0x8026, + ARM64_SYSREG_DBGWVR5_EL1 = 0x802E, + ARM64_SYSREG_DBGWVR6_EL1 = 0x8036, + ARM64_SYSREG_DBGWVR7_EL1 = 0x803E, + ARM64_SYSREG_DBGWVR8_EL1 = 0x8046, + ARM64_SYSREG_DBGWVR9_EL1 = 0x804E, + ARM64_SYSREG_DBGWVR10_EL1 = 0x8056, + ARM64_SYSREG_DBGWVR11_EL1 = 0x805E, + ARM64_SYSREG_DBGWVR12_EL1 = 0x8066, + ARM64_SYSREG_DBGWVR13_EL1 = 0x806E, + ARM64_SYSREG_DBGWVR14_EL1 = 0x8076, + ARM64_SYSREG_DBGWVR15_EL1 = 0x807E, + ARM64_SYSREG_DBGWCR0_EL1 = 0x8007, + ARM64_SYSREG_DBGWCR1_EL1 = 0x800F, + ARM64_SYSREG_DBGWCR2_EL1 = 0x8017, + ARM64_SYSREG_DBGWCR3_EL1 = 0x801F, + ARM64_SYSREG_DBGWCR4_EL1 = 0x8027, + ARM64_SYSREG_DBGWCR5_EL1 = 0x802F, + ARM64_SYSREG_DBGWCR6_EL1 = 0x8037, + ARM64_SYSREG_DBGWCR7_EL1 = 0x803F, + ARM64_SYSREG_DBGWCR8_EL1 = 0x8047, + ARM64_SYSREG_DBGWCR9_EL1 = 0x804F, + ARM64_SYSREG_DBGWCR10_EL1 = 0x8057, + ARM64_SYSREG_DBGWCR11_EL1 = 0x805F, + ARM64_SYSREG_DBGWCR12_EL1 = 0x8067, + ARM64_SYSREG_DBGWCR13_EL1 = 0x806F, + ARM64_SYSREG_DBGWCR14_EL1 = 0x8077, + ARM64_SYSREG_DBGWCR15_EL1 = 0x807F, + ARM64_SYSREG_TEEHBR32_EL1 = 0x9080, + ARM64_SYSREG_OSDLR_EL1 = 0x809C, + ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4, + ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6, + ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE, + ARM64_SYSREG_CSSELR_EL1 = 0xD000, + ARM64_SYSREG_VPIDR_EL2 = 0xE000, + ARM64_SYSREG_VMPIDR_EL2 = 0xE005, + ARM64_SYSREG_CPACR_EL1 = 0xC082, + ARM64_SYSREG_SCTLR_EL1 = 0xC080, + ARM64_SYSREG_SCTLR_EL2 = 0xE080, + ARM64_SYSREG_SCTLR_EL3 = 0xF080, + ARM64_SYSREG_ACTLR_EL1 = 0xC081, + ARM64_SYSREG_ACTLR_EL2 = 0xE081, + ARM64_SYSREG_ACTLR_EL3 = 0xF081, + ARM64_SYSREG_HCR_EL2 = 0xE088, + ARM64_SYSREG_SCR_EL3 = 0xF088, + ARM64_SYSREG_MDCR_EL2 = 0xE089, + ARM64_SYSREG_SDER32_EL3 = 0xF089, + ARM64_SYSREG_CPTR_EL2 = 0xE08A, + ARM64_SYSREG_CPTR_EL3 = 0xF08A, + ARM64_SYSREG_HSTR_EL2 = 0xE08B, + ARM64_SYSREG_HACR_EL2 = 0xE08F, + ARM64_SYSREG_MDCR_EL3 = 0xF099, + ARM64_SYSREG_TTBR0_EL1 = 0xC100, + ARM64_SYSREG_TTBR0_EL2 = 0xE100, + ARM64_SYSREG_TTBR0_EL3 = 0xF100, + ARM64_SYSREG_TTBR1_EL1 = 0xC101, + ARM64_SYSREG_TCR_EL1 = 0xC102, + ARM64_SYSREG_TCR_EL2 = 0xE102, + ARM64_SYSREG_TCR_EL3 = 0xF102, + ARM64_SYSREG_VTTBR_EL2 = 0xE108, + ARM64_SYSREG_VTCR_EL2 = 0xE10A, + ARM64_SYSREG_DACR32_EL2 = 0xE180, + ARM64_SYSREG_SPSR_EL1 = 0xC200, + ARM64_SYSREG_SPSR_EL2 = 0xE200, + ARM64_SYSREG_SPSR_EL3 = 0xF200, + ARM64_SYSREG_ELR_EL1 = 0xC201, + ARM64_SYSREG_ELR_EL2 = 0xE201, + ARM64_SYSREG_ELR_EL3 = 0xF201, + ARM64_SYSREG_SP_EL0 = 0xC208, + ARM64_SYSREG_SP_EL1 = 0xE208, + ARM64_SYSREG_SP_EL2 = 0xF208, + ARM64_SYSREG_SPSEL = 0xC210, + ARM64_SYSREG_NZCV = 0xDA10, + ARM64_SYSREG_DAIF = 0xDA11, + ARM64_SYSREG_CURRENTEL = 0xC212, + ARM64_SYSREG_SPSR_IRQ = 0xE218, + ARM64_SYSREG_SPSR_ABT = 0xE219, + ARM64_SYSREG_SPSR_UND = 0xE21A, + ARM64_SYSREG_SPSR_FIQ = 0xE21B, + ARM64_SYSREG_FPCR = 0xDA20, + ARM64_SYSREG_FPSR = 0xDA21, + ARM64_SYSREG_DSPSR_EL0 = 0xDA28, + ARM64_SYSREG_DLR_EL0 = 0xDA29, + ARM64_SYSREG_IFSR32_EL2 = 0xE281, + ARM64_SYSREG_AFSR0_EL1 = 0xC288, + ARM64_SYSREG_AFSR0_EL2 = 0xE288, + ARM64_SYSREG_AFSR0_EL3 = 0xF288, + ARM64_SYSREG_AFSR1_EL1 = 0xC289, + ARM64_SYSREG_AFSR1_EL2 = 0xE289, + ARM64_SYSREG_AFSR1_EL3 = 0xF289, + ARM64_SYSREG_ESR_EL1 = 0xC290, + ARM64_SYSREG_ESR_EL2 = 0xE290, + ARM64_SYSREG_ESR_EL3 = 0xF290, + ARM64_SYSREG_FPEXC32_EL2 = 0xE298, + ARM64_SYSREG_FAR_EL1 = 0xC300, + ARM64_SYSREG_FAR_EL2 = 0xE300, + ARM64_SYSREG_FAR_EL3 = 0xF300, + ARM64_SYSREG_HPFAR_EL2 = 0xE304, + ARM64_SYSREG_PAR_EL1 = 0xC3A0, + ARM64_SYSREG_PMCR_EL0 = 0xDCE0, + ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1, + ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2, + ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3, + ARM64_SYSREG_PMSELR_EL0 = 0xDCE5, + ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8, + ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9, + ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA, + ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0, + ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1, + ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2, + ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3, + ARM64_SYSREG_MAIR_EL1 = 0xC510, + ARM64_SYSREG_MAIR_EL2 = 0xE510, + ARM64_SYSREG_MAIR_EL3 = 0xF510, + ARM64_SYSREG_AMAIR_EL1 = 0xC518, + ARM64_SYSREG_AMAIR_EL2 = 0xE518, + ARM64_SYSREG_AMAIR_EL3 = 0xF518, + ARM64_SYSREG_VBAR_EL1 = 0xC600, + ARM64_SYSREG_VBAR_EL2 = 0xE600, + ARM64_SYSREG_VBAR_EL3 = 0xF600, + ARM64_SYSREG_RMR_EL1 = 0xC602, + ARM64_SYSREG_RMR_EL2 = 0xE602, + ARM64_SYSREG_RMR_EL3 = 0xF602, + ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681, + ARM64_SYSREG_TPIDR_EL0 = 0xDE82, + ARM64_SYSREG_TPIDR_EL2 = 0xE682, + ARM64_SYSREG_TPIDR_EL3 = 0xF682, + ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83, + ARM64_SYSREG_TPIDR_EL1 = 0xC684, + ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00, + ARM64_SYSREG_CNTVOFF_EL2 = 0xE703, + ARM64_SYSREG_CNTKCTL_EL1 = 0xC708, + ARM64_SYSREG_CNTHCTL_EL2 = 0xE708, + ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10, + ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710, + ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10, + ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11, + ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711, + ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11, + ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12, + ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712, + ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12, + ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18, + ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19, + ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A, + ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40, + ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41, + ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42, + ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43, + ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44, + ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45, + ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46, + ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47, + ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48, + ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49, + ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A, + ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B, + ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C, + ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D, + ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E, + ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F, + ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50, + ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51, + ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52, + ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53, + ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54, + ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55, + ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56, + ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57, + ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58, + ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59, + ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A, + ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B, + ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C, + ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D, + ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E, + ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F, + ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60, + ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61, + ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62, + ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63, + ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64, + ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65, + ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66, + ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67, + ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68, + ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69, + ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A, + ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B, + ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C, + ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D, + ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E, + ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F, + ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70, + ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71, + ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72, + ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73, + ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74, + ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75, + ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76, + ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77, + ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78, + ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79, + ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A, + ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B, + ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C, + ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D, + ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E, + ARM64_SYSREG_TRCPRGCTLR = 0x8808, + ARM64_SYSREG_TRCPROCSELR = 0x8810, + ARM64_SYSREG_TRCCONFIGR = 0x8820, + ARM64_SYSREG_TRCAUXCTLR = 0x8830, + ARM64_SYSREG_TRCEVENTCTL0R = 0x8840, + ARM64_SYSREG_TRCEVENTCTL1R = 0x8848, + ARM64_SYSREG_TRCSTALLCTLR = 0x8858, + ARM64_SYSREG_TRCTSCTLR = 0x8860, + ARM64_SYSREG_TRCSYNCPR = 0x8868, + ARM64_SYSREG_TRCCCCTLR = 0x8870, + ARM64_SYSREG_TRCBBCTLR = 0x8878, + ARM64_SYSREG_TRCTRACEIDR = 0x8801, + ARM64_SYSREG_TRCQCTLR = 0x8809, + ARM64_SYSREG_TRCVICTLR = 0x8802, + ARM64_SYSREG_TRCVIIECTLR = 0x880A, + ARM64_SYSREG_TRCVISSCTLR = 0x8812, + ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A, + ARM64_SYSREG_TRCVDCTLR = 0x8842, + ARM64_SYSREG_TRCVDSACCTLR = 0x884A, + ARM64_SYSREG_TRCVDARCCTLR = 0x8852, + ARM64_SYSREG_TRCSEQEVR0 = 0x8804, + ARM64_SYSREG_TRCSEQEVR1 = 0x880C, + ARM64_SYSREG_TRCSEQEVR2 = 0x8814, + ARM64_SYSREG_TRCSEQRSTEVR = 0x8834, + ARM64_SYSREG_TRCSEQSTR = 0x883C, + ARM64_SYSREG_TRCEXTINSELR = 0x8844, + ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805, + ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D, + ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815, + ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D, + ARM64_SYSREG_TRCCNTCTLR0 = 0x8825, + ARM64_SYSREG_TRCCNTCTLR1 = 0x882D, + ARM64_SYSREG_TRCCNTCTLR2 = 0x8835, + ARM64_SYSREG_TRCCNTCTLR3 = 0x883D, + ARM64_SYSREG_TRCCNTVR0 = 0x8845, + ARM64_SYSREG_TRCCNTVR1 = 0x884D, + ARM64_SYSREG_TRCCNTVR2 = 0x8855, + ARM64_SYSREG_TRCCNTVR3 = 0x885D, + ARM64_SYSREG_TRCIMSPEC0 = 0x8807, + ARM64_SYSREG_TRCIMSPEC1 = 0x880F, + ARM64_SYSREG_TRCIMSPEC2 = 0x8817, + ARM64_SYSREG_TRCIMSPEC3 = 0x881F, + ARM64_SYSREG_TRCIMSPEC4 = 0x8827, + ARM64_SYSREG_TRCIMSPEC5 = 0x882F, + ARM64_SYSREG_TRCIMSPEC6 = 0x8837, + ARM64_SYSREG_TRCIMSPEC7 = 0x883F, + ARM64_SYSREG_TRCRSCTLR2 = 0x8890, + ARM64_SYSREG_TRCRSCTLR3 = 0x8898, + ARM64_SYSREG_TRCRSCTLR4 = 0x88A0, + ARM64_SYSREG_TRCRSCTLR5 = 0x88A8, + ARM64_SYSREG_TRCRSCTLR6 = 0x88B0, + ARM64_SYSREG_TRCRSCTLR7 = 0x88B8, + ARM64_SYSREG_TRCRSCTLR8 = 0x88C0, + ARM64_SYSREG_TRCRSCTLR9 = 0x88C8, + ARM64_SYSREG_TRCRSCTLR10 = 0x88D0, + ARM64_SYSREG_TRCRSCTLR11 = 0x88D8, + ARM64_SYSREG_TRCRSCTLR12 = 0x88E0, + ARM64_SYSREG_TRCRSCTLR13 = 0x88E8, + ARM64_SYSREG_TRCRSCTLR14 = 0x88F0, + ARM64_SYSREG_TRCRSCTLR15 = 0x88F8, + ARM64_SYSREG_TRCRSCTLR16 = 0x8881, + ARM64_SYSREG_TRCRSCTLR17 = 0x8889, + ARM64_SYSREG_TRCRSCTLR18 = 0x8891, + ARM64_SYSREG_TRCRSCTLR19 = 0x8899, + ARM64_SYSREG_TRCRSCTLR20 = 0x88A1, + ARM64_SYSREG_TRCRSCTLR21 = 0x88A9, + ARM64_SYSREG_TRCRSCTLR22 = 0x88B1, + ARM64_SYSREG_TRCRSCTLR23 = 0x88B9, + ARM64_SYSREG_TRCRSCTLR24 = 0x88C1, + ARM64_SYSREG_TRCRSCTLR25 = 0x88C9, + ARM64_SYSREG_TRCRSCTLR26 = 0x88D1, + ARM64_SYSREG_TRCRSCTLR27 = 0x88D9, + ARM64_SYSREG_TRCRSCTLR28 = 0x88E1, + ARM64_SYSREG_TRCRSCTLR29 = 0x88E9, + ARM64_SYSREG_TRCRSCTLR30 = 0x88F1, + ARM64_SYSREG_TRCRSCTLR31 = 0x88F9, + ARM64_SYSREG_TRCSSCCR0 = 0x8882, + ARM64_SYSREG_TRCSSCCR1 = 0x888A, + ARM64_SYSREG_TRCSSCCR2 = 0x8892, + ARM64_SYSREG_TRCSSCCR3 = 0x889A, + ARM64_SYSREG_TRCSSCCR4 = 0x88A2, + ARM64_SYSREG_TRCSSCCR5 = 0x88AA, + ARM64_SYSREG_TRCSSCCR6 = 0x88B2, + ARM64_SYSREG_TRCSSCCR7 = 0x88BA, + ARM64_SYSREG_TRCSSCSR0 = 0x88C2, + ARM64_SYSREG_TRCSSCSR1 = 0x88CA, + ARM64_SYSREG_TRCSSCSR2 = 0x88D2, + ARM64_SYSREG_TRCSSCSR3 = 0x88DA, + ARM64_SYSREG_TRCSSCSR4 = 0x88E2, + ARM64_SYSREG_TRCSSCSR5 = 0x88EA, + ARM64_SYSREG_TRCSSCSR6 = 0x88F2, + ARM64_SYSREG_TRCSSCSR7 = 0x88FA, + ARM64_SYSREG_TRCSSPCICR0 = 0x8883, + ARM64_SYSREG_TRCSSPCICR1 = 0x888B, + ARM64_SYSREG_TRCSSPCICR2 = 0x8893, + ARM64_SYSREG_TRCSSPCICR3 = 0x889B, + ARM64_SYSREG_TRCSSPCICR4 = 0x88A3, + ARM64_SYSREG_TRCSSPCICR5 = 0x88AB, + ARM64_SYSREG_TRCSSPCICR6 = 0x88B3, + ARM64_SYSREG_TRCSSPCICR7 = 0x88BB, + ARM64_SYSREG_TRCPDCR = 0x88A4, + ARM64_SYSREG_TRCACVR0 = 0x8900, + ARM64_SYSREG_TRCACVR1 = 0x8910, + ARM64_SYSREG_TRCACVR2 = 0x8920, + ARM64_SYSREG_TRCACVR3 = 0x8930, + ARM64_SYSREG_TRCACVR4 = 0x8940, + ARM64_SYSREG_TRCACVR5 = 0x8950, + ARM64_SYSREG_TRCACVR6 = 0x8960, + ARM64_SYSREG_TRCACVR7 = 0x8970, + ARM64_SYSREG_TRCACVR8 = 0x8901, + ARM64_SYSREG_TRCACVR9 = 0x8911, + ARM64_SYSREG_TRCACVR10 = 0x8921, + ARM64_SYSREG_TRCACVR11 = 0x8931, + ARM64_SYSREG_TRCACVR12 = 0x8941, + ARM64_SYSREG_TRCACVR13 = 0x8951, + ARM64_SYSREG_TRCACVR14 = 0x8961, + ARM64_SYSREG_TRCACVR15 = 0x8971, + ARM64_SYSREG_TRCACATR0 = 0x8902, + ARM64_SYSREG_TRCACATR1 = 0x8912, + ARM64_SYSREG_TRCACATR2 = 0x8922, + ARM64_SYSREG_TRCACATR3 = 0x8932, + ARM64_SYSREG_TRCACATR4 = 0x8942, + ARM64_SYSREG_TRCACATR5 = 0x8952, + ARM64_SYSREG_TRCACATR6 = 0x8962, + ARM64_SYSREG_TRCACATR7 = 0x8972, + ARM64_SYSREG_TRCACATR8 = 0x8903, + ARM64_SYSREG_TRCACATR9 = 0x8913, + ARM64_SYSREG_TRCACATR10 = 0x8923, + ARM64_SYSREG_TRCACATR11 = 0x8933, + ARM64_SYSREG_TRCACATR12 = 0x8943, + ARM64_SYSREG_TRCACATR13 = 0x8953, + ARM64_SYSREG_TRCACATR14 = 0x8963, + ARM64_SYSREG_TRCACATR15 = 0x8973, + ARM64_SYSREG_TRCDVCVR0 = 0x8904, + ARM64_SYSREG_TRCDVCVR1 = 0x8924, + ARM64_SYSREG_TRCDVCVR2 = 0x8944, + ARM64_SYSREG_TRCDVCVR3 = 0x8964, + ARM64_SYSREG_TRCDVCVR4 = 0x8905, + ARM64_SYSREG_TRCDVCVR5 = 0x8925, + ARM64_SYSREG_TRCDVCVR6 = 0x8945, + ARM64_SYSREG_TRCDVCVR7 = 0x8965, + ARM64_SYSREG_TRCDVCMR0 = 0x8906, + ARM64_SYSREG_TRCDVCMR1 = 0x8926, + ARM64_SYSREG_TRCDVCMR2 = 0x8946, + ARM64_SYSREG_TRCDVCMR3 = 0x8966, + ARM64_SYSREG_TRCDVCMR4 = 0x8907, + ARM64_SYSREG_TRCDVCMR5 = 0x8927, + ARM64_SYSREG_TRCDVCMR6 = 0x8947, + ARM64_SYSREG_TRCDVCMR7 = 0x8967, + ARM64_SYSREG_TRCCIDCVR0 = 0x8980, + ARM64_SYSREG_TRCCIDCVR1 = 0x8990, + ARM64_SYSREG_TRCCIDCVR2 = 0x89A0, + ARM64_SYSREG_TRCCIDCVR3 = 0x89B0, + ARM64_SYSREG_TRCCIDCVR4 = 0x89C0, + ARM64_SYSREG_TRCCIDCVR5 = 0x89D0, + ARM64_SYSREG_TRCCIDCVR6 = 0x89E0, + ARM64_SYSREG_TRCCIDCVR7 = 0x89F0, + ARM64_SYSREG_TRCVMIDCVR0 = 0x8981, + ARM64_SYSREG_TRCVMIDCVR1 = 0x8991, + ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1, + ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1, + ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1, + ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1, + ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1, + ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1, + ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982, + ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A, + ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992, + ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A, + ARM64_SYSREG_TRCITCTRL = 0x8B84, + ARM64_SYSREG_TRCCLAIMSET = 0x8BC6, + ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE, + ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663, + ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643, + ARM64_SYSREG_ICC_PMR_EL1 = 0xC230, + ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664, + ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664, + ARM64_SYSREG_ICC_SRE_EL1 = 0xC665, + ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D, + ARM64_SYSREG_ICC_SRE_EL3 = 0xF665, + ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666, + ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667, + ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667, + ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668, + ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644, + ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645, + ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646, + ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647, + ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648, + ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649, + ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A, + ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B, + ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640, + ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641, + ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642, + ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643, + ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648, + ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649, + ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A, + ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B, + ARM64_SYSREG_ICH_HCR_EL2 = 0xE658, + ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A, + ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F, + ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C, + ARM64_SYSREG_ICH_LR0_EL2 = 0xE660, + ARM64_SYSREG_ICH_LR1_EL2 = 0xE661, + ARM64_SYSREG_ICH_LR2_EL2 = 0xE662, + ARM64_SYSREG_ICH_LR3_EL2 = 0xE663, + ARM64_SYSREG_ICH_LR4_EL2 = 0xE664, + ARM64_SYSREG_ICH_LR5_EL2 = 0xE665, + ARM64_SYSREG_ICH_LR6_EL2 = 0xE666, + ARM64_SYSREG_ICH_LR7_EL2 = 0xE667, + ARM64_SYSREG_ICH_LR8_EL2 = 0xE668, + ARM64_SYSREG_ICH_LR9_EL2 = 0xE669, + ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A, + ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B, + ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C, + ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D, + ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E, + ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F, + ARM64_SYSREG_PAN = 0xC213, + ARM64_SYSREG_LORSA_EL1 = 0xC520, + ARM64_SYSREG_LOREA_EL1 = 0xC521, + ARM64_SYSREG_LORN_EL1 = 0xC522, + ARM64_SYSREG_LORC_EL1 = 0xC523, + ARM64_SYSREG_TTBR1_EL2 = 0xE101, + ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681, + ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718, + ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A, + ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719, + ARM64_SYSREG_SCTLR_EL12 = 0xE880, + ARM64_SYSREG_CPACR_EL12 = 0xE882, + ARM64_SYSREG_TTBR0_EL12 = 0xE900, + ARM64_SYSREG_TTBR1_EL12 = 0xE901, + ARM64_SYSREG_TCR_EL12 = 0xE902, + ARM64_SYSREG_AFSR0_EL12 = 0xEA88, + ARM64_SYSREG_AFSR1_EL12 = 0xEA89, + ARM64_SYSREG_ESR_EL12 = 0xEA90, + ARM64_SYSREG_FAR_EL12 = 0xEB00, + ARM64_SYSREG_MAIR_EL12 = 0xED10, + ARM64_SYSREG_AMAIR_EL12 = 0xED18, + ARM64_SYSREG_VBAR_EL12 = 0xEE00, + ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81, + ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08, + ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10, + ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11, + ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12, + ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18, + ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19, + ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A, + ARM64_SYSREG_SPSR_EL12 = 0xEA00, + ARM64_SYSREG_ELR_EL12 = 0xEA01, + ARM64_SYSREG_UAO = 0xC214, + ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0, + ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1, + ARM64_SYSREG_PMBSR_EL1 = 0xC4D3, + ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7, + ARM64_SYSREG_PMSCR_EL2 = 0xE4C8, + ARM64_SYSREG_PMSCR_EL12 = 0xECC8, + ARM64_SYSREG_PMSCR_EL1 = 0xC4C8, + ARM64_SYSREG_PMSICR_EL1 = 0xC4CA, + ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB, + ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC, + ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD, + ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE, + ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF, + ARM64_SYSREG_ERRSELR_EL1 = 0xC299, + ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1, + ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2, + ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3, + ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8, + ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9, + ARM64_SYSREG_DISR_EL1 = 0xC609, + ARM64_SYSREG_VDISR_EL2 = 0xE609, + ARM64_SYSREG_VSESR_EL2 = 0xE293, + ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108, + ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109, + ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A, + ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B, + ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110, + ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111, + ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112, + ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113, + ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118, + ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119, + ARM64_SYSREG_VSTCR_EL2 = 0xE132, + ARM64_SYSREG_VSTTBR_EL2 = 0xE130, + ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720, + ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722, + ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721, + ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728, + ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A, + ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729, + ARM64_SYSREG_SDER32_EL2 = 0xE099, + ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5, + ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6, + ARM64_SYSREG_ERXTS_EL1 = 0xC2AF, + ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA, + ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB, + ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4, + ARM64_SYSREG_MPAM0_EL1 = 0xC529, + ARM64_SYSREG_MPAM1_EL1 = 0xC528, + ARM64_SYSREG_MPAM2_EL2 = 0xE528, + ARM64_SYSREG_MPAM3_EL3 = 0xF528, + ARM64_SYSREG_MPAM1_EL12 = 0xED28, + ARM64_SYSREG_MPAMHCR_EL2 = 0xE520, + ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521, + ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530, + ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531, + ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532, + ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533, + ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534, + ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535, + ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536, + ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537, + ARM64_SYSREG_MPAMIDR_EL1 = 0xC524, + ARM64_SYSREG_AMCR_EL0 = 0xDE90, + ARM64_SYSREG_AMCFGR_EL0 = 0xDE91, + ARM64_SYSREG_AMCGCR_EL0 = 0xDE92, + ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93, + ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94, + ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95, + ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0, + ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1, + ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2, + ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3, + ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0, + ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1, + ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2, + ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3, + ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98, + ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99, + ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0, + ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1, + ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2, + ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3, + ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4, + ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5, + ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6, + ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7, + ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8, + ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9, + ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA, + ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB, + ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC, + ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED, + ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE, + ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF, + ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0, + ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1, + ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2, + ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3, + ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4, + ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5, + ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6, + ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7, + ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8, + ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9, + ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA, + ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB, + ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC, + ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD, + ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE, + ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF, + ARM64_SYSREG_TRFCR_EL1 = 0xC091, + ARM64_SYSREG_TRFCR_EL2 = 0xE091, + ARM64_SYSREG_TRFCR_EL12 = 0xE891, + ARM64_SYSREG_DIT = 0xDA15, + ARM64_SYSREG_VNCR_EL2 = 0xE110, + ARM64_SYSREG_ZCR_EL1 = 0xC090, + ARM64_SYSREG_ZCR_EL2 = 0xE090, + ARM64_SYSREG_ZCR_EL3 = 0xF090, + ARM64_SYSREG_ZCR_EL12 = 0xE890, + ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90, } arm64_sysreg; /// System PState Field (MSR instruction) typedef enum arm64_pstate { - ARM64_PSTATE_INVALID = 0, - ARM64_PSTATE_SPSEL = 0x05, - ARM64_PSTATE_DAIFSET = 0x1e, - ARM64_PSTATE_DAIFCLR = 0x1f, - ARM64_PSTATE_PAN = 0x4, - ARM64_PSTATE_UAO = 0x3, - ARM64_PSTATE_DIT = 0x1a, + ARM64_PSTATE_INVALID = 0, + ARM64_PSTATE_SPSEL = 0x05, + ARM64_PSTATE_DAIFSET = 0x1e, + ARM64_PSTATE_DAIFCLR = 0x1f, + ARM64_PSTATE_PAN = 0x4, + ARM64_PSTATE_UAO = 0x3, + ARM64_PSTATE_DIT = 0x1a, } arm64_pstate; /// Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn) typedef enum arm64_vas { - ARM64_VAS_INVALID = 0, - ARM64_VAS_16B, - ARM64_VAS_8B, - ARM64_VAS_4B, - ARM64_VAS_1B, - ARM64_VAS_8H, - ARM64_VAS_4H, - ARM64_VAS_2H, - ARM64_VAS_1H, - ARM64_VAS_4S, - ARM64_VAS_2S, - ARM64_VAS_1S, - ARM64_VAS_2D, - ARM64_VAS_1D, - ARM64_VAS_1Q, + ARM64_VAS_INVALID = 0, + ARM64_VAS_16B, + ARM64_VAS_8B, + ARM64_VAS_4B, + ARM64_VAS_1B, + ARM64_VAS_8H, + ARM64_VAS_4H, + ARM64_VAS_2H, + ARM64_VAS_1H, + ARM64_VAS_4S, + ARM64_VAS_2S, + ARM64_VAS_1S, + ARM64_VAS_2D, + ARM64_VAS_1D, + ARM64_VAS_1Q, } arm64_vas; /// Memory barrier operands typedef enum arm64_barrier_op { - ARM64_BARRIER_INVALID = 0, - ARM64_BARRIER_OSHLD = 0x1, - ARM64_BARRIER_OSHST = 0x2, - ARM64_BARRIER_OSH = 0x3, - ARM64_BARRIER_NSHLD = 0x5, - ARM64_BARRIER_NSHST = 0x6, - ARM64_BARRIER_NSH = 0x7, - ARM64_BARRIER_ISHLD = 0x9, - ARM64_BARRIER_ISHST = 0xa, - ARM64_BARRIER_ISH = 0xb, - ARM64_BARRIER_LD = 0xd, - ARM64_BARRIER_ST = 0xe, - ARM64_BARRIER_SY = 0xf + ARM64_BARRIER_INVALID = 0, + ARM64_BARRIER_OSHLD = 0x1, + ARM64_BARRIER_OSHST = 0x2, + ARM64_BARRIER_OSH = 0x3, + ARM64_BARRIER_NSHLD = 0x5, + ARM64_BARRIER_NSHST = 0x6, + ARM64_BARRIER_NSH = 0x7, + ARM64_BARRIER_ISHLD = 0x9, + ARM64_BARRIER_ISHST = 0xa, + ARM64_BARRIER_ISH = 0xb, + ARM64_BARRIER_LD = 0xd, + ARM64_BARRIER_ST = 0xe, + ARM64_BARRIER_SY = 0xf } arm64_barrier_op; /// Operand type for instruction's operands typedef enum arm64_op_type { - ARM64_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). - ARM64_OP_REG, ///< = CS_OP_REG (Register operand). - ARM64_OP_IMM, ///< = CS_OP_IMM (Immediate operand). - ARM64_OP_MEM, ///< = CS_OP_MEM (Memory operand). - ARM64_OP_FP, ///< = CS_OP_FP (Floating-Point operand). - ARM64_OP_CIMM = 64, ///< C-Immediate - ARM64_OP_REG_MRS, ///< MRS register operand. - ARM64_OP_REG_MSR, ///< MSR register operand. - ARM64_OP_PSTATE, ///< PState operand. - ARM64_OP_SYS, ///< SYS operand for IC/DC/AT/TLBI instructions. - ARM64_OP_PREFETCH, ///< Prefetch operand (PRFM). - ARM64_OP_BARRIER, ///< Memory barrier operand (ISB/DMB/DSB instructions). + ARM64_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + ARM64_OP_REG, ///< = CS_OP_REG (Register operand). + ARM64_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + ARM64_OP_MEM, ///< = CS_OP_MEM (Memory operand). + ARM64_OP_FP, ///< = CS_OP_FP (Floating-Point operand). + ARM64_OP_CIMM = 64, ///< C-Immediate + ARM64_OP_REG_MRS, ///< MRS register operand. + ARM64_OP_REG_MSR, ///< MSR register operand. + ARM64_OP_PSTATE, ///< PState operand. + ARM64_OP_SYS, ///< SYS operand for IC/DC/AT/TLBI instructions. + ARM64_OP_PREFETCH, ///< Prefetch operand (PRFM). + ARM64_OP_BARRIER, ///< Memory barrier operand (ISB/DMB/DSB instructions). } arm64_op_type; /// TLBI operations typedef enum arm64_tlbi_op { - ARM64_TLBI_INVALID = 0, + ARM64_TLBI_INVALID = 0, - ARM64_TLBI_IPAS2E1IS, - ARM64_TLBI_IPAS2LE1IS, - ARM64_TLBI_VMALLE1IS, - ARM64_TLBI_ALLE2IS, - ARM64_TLBI_ALLE3IS, - ARM64_TLBI_VAE1IS, - ARM64_TLBI_VAE2IS, - ARM64_TLBI_VAE3IS, - ARM64_TLBI_ASIDE1IS, - ARM64_TLBI_VAAE1IS, - ARM64_TLBI_ALLE1IS, - ARM64_TLBI_VALE1IS, - ARM64_TLBI_VALE2IS, - ARM64_TLBI_VALE3IS, - ARM64_TLBI_VMALLS12E1IS, - ARM64_TLBI_VAALE1IS, - ARM64_TLBI_IPAS2E1, - ARM64_TLBI_IPAS2LE1, - ARM64_TLBI_VMALLE1, - ARM64_TLBI_ALLE2, - ARM64_TLBI_ALLE3, - ARM64_TLBI_VAE1, - ARM64_TLBI_VAE2, - ARM64_TLBI_VAE3, - ARM64_TLBI_ASIDE1, - ARM64_TLBI_VAAE1, - ARM64_TLBI_ALLE1, - ARM64_TLBI_VALE1, - ARM64_TLBI_VALE2, - ARM64_TLBI_VALE3, - ARM64_TLBI_VMALLS12E1, - ARM64_TLBI_VAALE1, - ARM64_TLBI_VMALLE1OS, - ARM64_TLBI_VAE1OS, - ARM64_TLBI_ASIDE1OS, - ARM64_TLBI_VAAE1OS, - ARM64_TLBI_VALE1OS, - ARM64_TLBI_VAALE1OS, - ARM64_TLBI_IPAS2E1OS, - ARM64_TLBI_IPAS2LE1OS, - ARM64_TLBI_VAE2OS, - ARM64_TLBI_VALE2OS, - ARM64_TLBI_VMALLS12E1OS, - ARM64_TLBI_VAE3OS, - ARM64_TLBI_VALE3OS, - ARM64_TLBI_ALLE2OS, - ARM64_TLBI_ALLE1OS, - ARM64_TLBI_ALLE3OS, - ARM64_TLBI_RVAE1, - ARM64_TLBI_RVAAE1, - ARM64_TLBI_RVALE1, - ARM64_TLBI_RVAALE1, - ARM64_TLBI_RVAE1IS, - ARM64_TLBI_RVAAE1IS, - ARM64_TLBI_RVALE1IS, - ARM64_TLBI_RVAALE1IS, - ARM64_TLBI_RVAE1OS, - ARM64_TLBI_RVAAE1OS, - ARM64_TLBI_RVALE1OS, - ARM64_TLBI_RVAALE1OS, - ARM64_TLBI_RIPAS2E1IS, - ARM64_TLBI_RIPAS2LE1IS, - ARM64_TLBI_RIPAS2E1, - ARM64_TLBI_RIPAS2LE1, - ARM64_TLBI_RIPAS2E1OS, - ARM64_TLBI_RIPAS2LE1OS, - ARM64_TLBI_RVAE2, - ARM64_TLBI_RVALE2, - ARM64_TLBI_RVAE2IS, - ARM64_TLBI_RVALE2IS, - ARM64_TLBI_RVAE2OS, - ARM64_TLBI_RVALE2OS, - ARM64_TLBI_RVAE3, - ARM64_TLBI_RVALE3, - ARM64_TLBI_RVAE3IS, - ARM64_TLBI_RVALE3IS, - ARM64_TLBI_RVAE3OS, - ARM64_TLBI_RVALE3OS, + ARM64_TLBI_IPAS2E1IS, + ARM64_TLBI_IPAS2LE1IS, + ARM64_TLBI_VMALLE1IS, + ARM64_TLBI_ALLE2IS, + ARM64_TLBI_ALLE3IS, + ARM64_TLBI_VAE1IS, + ARM64_TLBI_VAE2IS, + ARM64_TLBI_VAE3IS, + ARM64_TLBI_ASIDE1IS, + ARM64_TLBI_VAAE1IS, + ARM64_TLBI_ALLE1IS, + ARM64_TLBI_VALE1IS, + ARM64_TLBI_VALE2IS, + ARM64_TLBI_VALE3IS, + ARM64_TLBI_VMALLS12E1IS, + ARM64_TLBI_VAALE1IS, + ARM64_TLBI_IPAS2E1, + ARM64_TLBI_IPAS2LE1, + ARM64_TLBI_VMALLE1, + ARM64_TLBI_ALLE2, + ARM64_TLBI_ALLE3, + ARM64_TLBI_VAE1, + ARM64_TLBI_VAE2, + ARM64_TLBI_VAE3, + ARM64_TLBI_ASIDE1, + ARM64_TLBI_VAAE1, + ARM64_TLBI_ALLE1, + ARM64_TLBI_VALE1, + ARM64_TLBI_VALE2, + ARM64_TLBI_VALE3, + ARM64_TLBI_VMALLS12E1, + ARM64_TLBI_VAALE1, + ARM64_TLBI_VMALLE1OS, + ARM64_TLBI_VAE1OS, + ARM64_TLBI_ASIDE1OS, + ARM64_TLBI_VAAE1OS, + ARM64_TLBI_VALE1OS, + ARM64_TLBI_VAALE1OS, + ARM64_TLBI_IPAS2E1OS, + ARM64_TLBI_IPAS2LE1OS, + ARM64_TLBI_VAE2OS, + ARM64_TLBI_VALE2OS, + ARM64_TLBI_VMALLS12E1OS, + ARM64_TLBI_VAE3OS, + ARM64_TLBI_VALE3OS, + ARM64_TLBI_ALLE2OS, + ARM64_TLBI_ALLE1OS, + ARM64_TLBI_ALLE3OS, + ARM64_TLBI_RVAE1, + ARM64_TLBI_RVAAE1, + ARM64_TLBI_RVALE1, + ARM64_TLBI_RVAALE1, + ARM64_TLBI_RVAE1IS, + ARM64_TLBI_RVAAE1IS, + ARM64_TLBI_RVALE1IS, + ARM64_TLBI_RVAALE1IS, + ARM64_TLBI_RVAE1OS, + ARM64_TLBI_RVAAE1OS, + ARM64_TLBI_RVALE1OS, + ARM64_TLBI_RVAALE1OS, + ARM64_TLBI_RIPAS2E1IS, + ARM64_TLBI_RIPAS2LE1IS, + ARM64_TLBI_RIPAS2E1, + ARM64_TLBI_RIPAS2LE1, + ARM64_TLBI_RIPAS2E1OS, + ARM64_TLBI_RIPAS2LE1OS, + ARM64_TLBI_RVAE2, + ARM64_TLBI_RVALE2, + ARM64_TLBI_RVAE2IS, + ARM64_TLBI_RVALE2IS, + ARM64_TLBI_RVAE2OS, + ARM64_TLBI_RVALE2OS, + ARM64_TLBI_RVAE3, + ARM64_TLBI_RVALE3, + ARM64_TLBI_RVAE3IS, + ARM64_TLBI_RVALE3IS, + ARM64_TLBI_RVAE3OS, + ARM64_TLBI_RVALE3OS, } arm64_tlbi_op; /// AT operations typedef enum arm64_at_op { - ARM64_AT_S1E1R, - ARM64_AT_S1E2R, - ARM64_AT_S1E3R, - ARM64_AT_S1E1W, - ARM64_AT_S1E2W, - ARM64_AT_S1E3W, - ARM64_AT_S1E0R, - ARM64_AT_S1E0W, - ARM64_AT_S12E1R, - ARM64_AT_S12E1W, - ARM64_AT_S12E0R, - ARM64_AT_S12E0W, - ARM64_AT_S1E1RP, - ARM64_AT_S1E1WP, + ARM64_AT_S1E1R, + ARM64_AT_S1E2R, + ARM64_AT_S1E3R, + ARM64_AT_S1E1W, + ARM64_AT_S1E2W, + ARM64_AT_S1E3W, + ARM64_AT_S1E0R, + ARM64_AT_S1E0W, + ARM64_AT_S12E1R, + ARM64_AT_S12E1W, + ARM64_AT_S12E0R, + ARM64_AT_S12E0W, + ARM64_AT_S1E1RP, + ARM64_AT_S1E1WP, } arm64_at_op; /// DC operations typedef enum arm64_dc_op { - ARM64_DC_INVALID = 0, - ARM64_DC_ZVA, - ARM64_DC_IVAC, - ARM64_DC_ISW, - ARM64_DC_CVAC, - ARM64_DC_CSW, - ARM64_DC_CVAU, - ARM64_DC_CIVAC, - ARM64_DC_CISW, - ARM64_DC_CVAP, + ARM64_DC_INVALID = 0, + ARM64_DC_ZVA, + ARM64_DC_IVAC, + ARM64_DC_ISW, + ARM64_DC_CVAC, + ARM64_DC_CSW, + ARM64_DC_CVAU, + ARM64_DC_CIVAC, + ARM64_DC_CISW, + ARM64_DC_CVAP, } arm64_dc_op; /// IC operations typedef enum arm64_ic_op { - ARM64_IC_INVALID = 0, - ARM64_IC_IALLUIS, - ARM64_IC_IALLU, - ARM64_IC_IVAU, + ARM64_IC_INVALID = 0, + ARM64_IC_IALLUIS, + ARM64_IC_IALLU, + ARM64_IC_IVAU, } arm64_ic_op; /// Prefetch operations (PRFM) typedef enum arm64_prefetch_op { - ARM64_PRFM_INVALID = 0, - ARM64_PRFM_PLDL1KEEP = 0x00 + 1, - ARM64_PRFM_PLDL1STRM = 0x01 + 1, - ARM64_PRFM_PLDL2KEEP = 0x02 + 1, - ARM64_PRFM_PLDL2STRM = 0x03 + 1, - ARM64_PRFM_PLDL3KEEP = 0x04 + 1, - ARM64_PRFM_PLDL3STRM = 0x05 + 1, - ARM64_PRFM_PLIL1KEEP = 0x08 + 1, - ARM64_PRFM_PLIL1STRM = 0x09 + 1, - ARM64_PRFM_PLIL2KEEP = 0x0a + 1, - ARM64_PRFM_PLIL2STRM = 0x0b + 1, - ARM64_PRFM_PLIL3KEEP = 0x0c + 1, - ARM64_PRFM_PLIL3STRM = 0x0d + 1, - ARM64_PRFM_PSTL1KEEP = 0x10 + 1, - ARM64_PRFM_PSTL1STRM = 0x11 + 1, - ARM64_PRFM_PSTL2KEEP = 0x12 + 1, - ARM64_PRFM_PSTL2STRM = 0x13 + 1, - ARM64_PRFM_PSTL3KEEP = 0x14 + 1, - ARM64_PRFM_PSTL3STRM = 0x15 + 1, + ARM64_PRFM_INVALID = 0, + ARM64_PRFM_PLDL1KEEP = 0x00 + 1, + ARM64_PRFM_PLDL1STRM = 0x01 + 1, + ARM64_PRFM_PLDL2KEEP = 0x02 + 1, + ARM64_PRFM_PLDL2STRM = 0x03 + 1, + ARM64_PRFM_PLDL3KEEP = 0x04 + 1, + ARM64_PRFM_PLDL3STRM = 0x05 + 1, + ARM64_PRFM_PLIL1KEEP = 0x08 + 1, + ARM64_PRFM_PLIL1STRM = 0x09 + 1, + ARM64_PRFM_PLIL2KEEP = 0x0a + 1, + ARM64_PRFM_PLIL2STRM = 0x0b + 1, + ARM64_PRFM_PLIL3KEEP = 0x0c + 1, + ARM64_PRFM_PLIL3STRM = 0x0d + 1, + ARM64_PRFM_PSTL1KEEP = 0x10 + 1, + ARM64_PRFM_PSTL1STRM = 0x11 + 1, + ARM64_PRFM_PSTL2KEEP = 0x12 + 1, + ARM64_PRFM_PSTL2STRM = 0x13 + 1, + ARM64_PRFM_PSTL3KEEP = 0x14 + 1, + ARM64_PRFM_PSTL3STRM = 0x15 + 1, } arm64_prefetch_op; /// ARM64 registers typedef enum arm64_reg { - ARM64_REG_INVALID = 0, + ARM64_REG_INVALID = 0, - ARM64_REG_FFR = 1, - ARM64_REG_FP = 2, - ARM64_REG_LR = 3, - ARM64_REG_NZCV = 4, - ARM64_REG_SP = 5, - ARM64_REG_WSP = 6, - ARM64_REG_WZR = 7, - ARM64_REG_XZR = 8, - ARM64_REG_B0 = 9, - ARM64_REG_B1 = 10, - ARM64_REG_B2 = 11, - ARM64_REG_B3 = 12, - ARM64_REG_B4 = 13, - ARM64_REG_B5 = 14, - ARM64_REG_B6 = 15, - ARM64_REG_B7 = 16, - ARM64_REG_B8 = 17, - ARM64_REG_B9 = 18, - ARM64_REG_B10 = 19, - ARM64_REG_B11 = 20, - ARM64_REG_B12 = 21, - ARM64_REG_B13 = 22, - ARM64_REG_B14 = 23, - ARM64_REG_B15 = 24, - ARM64_REG_B16 = 25, - ARM64_REG_B17 = 26, - ARM64_REG_B18 = 27, - ARM64_REG_B19 = 28, - ARM64_REG_B20 = 29, - ARM64_REG_B21 = 30, - ARM64_REG_B22 = 31, - ARM64_REG_B23 = 32, - ARM64_REG_B24 = 33, - ARM64_REG_B25 = 34, - ARM64_REG_B26 = 35, - ARM64_REG_B27 = 36, - ARM64_REG_B28 = 37, - ARM64_REG_B29 = 38, - ARM64_REG_B30 = 39, - ARM64_REG_B31 = 40, - ARM64_REG_D0 = 41, - ARM64_REG_D1 = 42, - ARM64_REG_D2 = 43, - ARM64_REG_D3 = 44, - ARM64_REG_D4 = 45, - ARM64_REG_D5 = 46, - ARM64_REG_D6 = 47, - ARM64_REG_D7 = 48, - ARM64_REG_D8 = 49, - ARM64_REG_D9 = 50, - ARM64_REG_D10 = 51, - ARM64_REG_D11 = 52, - ARM64_REG_D12 = 53, - ARM64_REG_D13 = 54, - ARM64_REG_D14 = 55, - ARM64_REG_D15 = 56, - ARM64_REG_D16 = 57, - ARM64_REG_D17 = 58, - ARM64_REG_D18 = 59, - ARM64_REG_D19 = 60, - ARM64_REG_D20 = 61, - ARM64_REG_D21 = 62, - ARM64_REG_D22 = 63, - ARM64_REG_D23 = 64, - ARM64_REG_D24 = 65, - ARM64_REG_D25 = 66, - ARM64_REG_D26 = 67, - ARM64_REG_D27 = 68, - ARM64_REG_D28 = 69, - ARM64_REG_D29 = 70, - ARM64_REG_D30 = 71, - ARM64_REG_D31 = 72, - ARM64_REG_H0 = 73, - ARM64_REG_H1 = 74, - ARM64_REG_H2 = 75, - ARM64_REG_H3 = 76, - ARM64_REG_H4 = 77, - ARM64_REG_H5 = 78, - ARM64_REG_H6 = 79, - ARM64_REG_H7 = 80, - ARM64_REG_H8 = 81, - ARM64_REG_H9 = 82, - ARM64_REG_H10 = 83, - ARM64_REG_H11 = 84, - ARM64_REG_H12 = 85, - ARM64_REG_H13 = 86, - ARM64_REG_H14 = 87, - ARM64_REG_H15 = 88, - ARM64_REG_H16 = 89, - ARM64_REG_H17 = 90, - ARM64_REG_H18 = 91, - ARM64_REG_H19 = 92, - ARM64_REG_H20 = 93, - ARM64_REG_H21 = 94, - ARM64_REG_H22 = 95, - ARM64_REG_H23 = 96, - ARM64_REG_H24 = 97, - ARM64_REG_H25 = 98, - ARM64_REG_H26 = 99, - ARM64_REG_H27 = 100, - ARM64_REG_H28 = 101, - ARM64_REG_H29 = 102, - ARM64_REG_H30 = 103, - ARM64_REG_H31 = 104, - ARM64_REG_P0 = 105, - ARM64_REG_P1 = 106, - ARM64_REG_P2 = 107, - ARM64_REG_P3 = 108, - ARM64_REG_P4 = 109, - ARM64_REG_P5 = 110, - ARM64_REG_P6 = 111, - ARM64_REG_P7 = 112, - ARM64_REG_P8 = 113, - ARM64_REG_P9 = 114, - ARM64_REG_P10 = 115, - ARM64_REG_P11 = 116, - ARM64_REG_P12 = 117, - ARM64_REG_P13 = 118, - ARM64_REG_P14 = 119, - ARM64_REG_P15 = 120, - ARM64_REG_Q0 = 121, - ARM64_REG_Q1 = 122, - ARM64_REG_Q2 = 123, - ARM64_REG_Q3 = 124, - ARM64_REG_Q4 = 125, - ARM64_REG_Q5 = 126, - ARM64_REG_Q6 = 127, - ARM64_REG_Q7 = 128, - ARM64_REG_Q8 = 129, - ARM64_REG_Q9 = 130, - ARM64_REG_Q10 = 131, - ARM64_REG_Q11 = 132, - ARM64_REG_Q12 = 133, - ARM64_REG_Q13 = 134, - ARM64_REG_Q14 = 135, - ARM64_REG_Q15 = 136, - ARM64_REG_Q16 = 137, - ARM64_REG_Q17 = 138, - ARM64_REG_Q18 = 139, - ARM64_REG_Q19 = 140, - ARM64_REG_Q20 = 141, - ARM64_REG_Q21 = 142, - ARM64_REG_Q22 = 143, - ARM64_REG_Q23 = 144, - ARM64_REG_Q24 = 145, - ARM64_REG_Q25 = 146, - ARM64_REG_Q26 = 147, - ARM64_REG_Q27 = 148, - ARM64_REG_Q28 = 149, - ARM64_REG_Q29 = 150, - ARM64_REG_Q30 = 151, - ARM64_REG_Q31 = 152, - ARM64_REG_S0 = 153, - ARM64_REG_S1 = 154, - ARM64_REG_S2 = 155, - ARM64_REG_S3 = 156, - ARM64_REG_S4 = 157, - ARM64_REG_S5 = 158, - ARM64_REG_S6 = 159, - ARM64_REG_S7 = 160, - ARM64_REG_S8 = 161, - ARM64_REG_S9 = 162, - ARM64_REG_S10 = 163, - ARM64_REG_S11 = 164, - ARM64_REG_S12 = 165, - ARM64_REG_S13 = 166, - ARM64_REG_S14 = 167, - ARM64_REG_S15 = 168, - ARM64_REG_S16 = 169, - ARM64_REG_S17 = 170, - ARM64_REG_S18 = 171, - ARM64_REG_S19 = 172, - ARM64_REG_S20 = 173, - ARM64_REG_S21 = 174, - ARM64_REG_S22 = 175, - ARM64_REG_S23 = 176, - ARM64_REG_S24 = 177, - ARM64_REG_S25 = 178, - ARM64_REG_S26 = 179, - ARM64_REG_S27 = 180, - ARM64_REG_S28 = 181, - ARM64_REG_S29 = 182, - ARM64_REG_S30 = 183, - ARM64_REG_S31 = 184, - ARM64_REG_W0 = 185, - ARM64_REG_W1 = 186, - ARM64_REG_W2 = 187, - ARM64_REG_W3 = 188, - ARM64_REG_W4 = 189, - ARM64_REG_W5 = 190, - ARM64_REG_W6 = 191, - ARM64_REG_W7 = 192, - ARM64_REG_W8 = 193, - ARM64_REG_W9 = 194, - ARM64_REG_W10 = 195, - ARM64_REG_W11 = 196, - ARM64_REG_W12 = 197, - ARM64_REG_W13 = 198, - ARM64_REG_W14 = 199, - ARM64_REG_W15 = 200, - ARM64_REG_W16 = 201, - ARM64_REG_W17 = 202, - ARM64_REG_W18 = 203, - ARM64_REG_W19 = 204, - ARM64_REG_W20 = 205, - ARM64_REG_W21 = 206, - ARM64_REG_W22 = 207, - ARM64_REG_W23 = 208, - ARM64_REG_W24 = 209, - ARM64_REG_W25 = 210, - ARM64_REG_W26 = 211, - ARM64_REG_W27 = 212, - ARM64_REG_W28 = 213, - ARM64_REG_W29 = 214, - ARM64_REG_W30 = 215, - ARM64_REG_X0 = 216, - ARM64_REG_X1 = 217, - ARM64_REG_X2 = 218, - ARM64_REG_X3 = 219, - ARM64_REG_X4 = 220, - ARM64_REG_X5 = 221, - ARM64_REG_X6 = 222, - ARM64_REG_X7 = 223, - ARM64_REG_X8 = 224, - ARM64_REG_X9 = 225, - ARM64_REG_X10 = 226, - ARM64_REG_X11 = 227, - ARM64_REG_X12 = 228, - ARM64_REG_X13 = 229, - ARM64_REG_X14 = 230, - ARM64_REG_X15 = 231, - ARM64_REG_X16 = 232, - ARM64_REG_X17 = 233, - ARM64_REG_X18 = 234, - ARM64_REG_X19 = 235, - ARM64_REG_X20 = 236, - ARM64_REG_X21 = 237, - ARM64_REG_X22 = 238, - ARM64_REG_X23 = 239, - ARM64_REG_X24 = 240, - ARM64_REG_X25 = 241, - ARM64_REG_X26 = 242, - ARM64_REG_X27 = 243, - ARM64_REG_X28 = 244, - ARM64_REG_Z0 = 245, - ARM64_REG_Z1 = 246, - ARM64_REG_Z2 = 247, - ARM64_REG_Z3 = 248, - ARM64_REG_Z4 = 249, - ARM64_REG_Z5 = 250, - ARM64_REG_Z6 = 251, - ARM64_REG_Z7 = 252, - ARM64_REG_Z8 = 253, - ARM64_REG_Z9 = 254, - ARM64_REG_Z10 = 255, - ARM64_REG_Z11 = 256, - ARM64_REG_Z12 = 257, - ARM64_REG_Z13 = 258, - ARM64_REG_Z14 = 259, - ARM64_REG_Z15 = 260, - ARM64_REG_Z16 = 261, - ARM64_REG_Z17 = 262, - ARM64_REG_Z18 = 263, - ARM64_REG_Z19 = 264, - ARM64_REG_Z20 = 265, - ARM64_REG_Z21 = 266, - ARM64_REG_Z22 = 267, - ARM64_REG_Z23 = 268, - ARM64_REG_Z24 = 269, - ARM64_REG_Z25 = 270, - ARM64_REG_Z26 = 271, - ARM64_REG_Z27 = 272, - ARM64_REG_Z28 = 273, - ARM64_REG_Z29 = 274, - ARM64_REG_Z30 = 275, - ARM64_REG_Z31 = 276, + ARM64_REG_FFR = 1, + ARM64_REG_FP = 2, + ARM64_REG_LR = 3, + ARM64_REG_NZCV = 4, + ARM64_REG_SP = 5, + ARM64_REG_VG = 6, + ARM64_REG_WSP = 7, + ARM64_REG_WZR = 8, + ARM64_REG_XZR = 9, + ARM64_REG_ZA = 10, + ARM64_REG_B0 = 11, + ARM64_REG_B1, + ARM64_REG_B2, + ARM64_REG_B3, + ARM64_REG_B4, + ARM64_REG_B5, + ARM64_REG_B6, + ARM64_REG_B7, + ARM64_REG_B8, + ARM64_REG_B9, + ARM64_REG_B10, + ARM64_REG_B11, + ARM64_REG_B12, + ARM64_REG_B13, + ARM64_REG_B14, + ARM64_REG_B15, + ARM64_REG_B16, + ARM64_REG_B17, + ARM64_REG_B18, + ARM64_REG_B19, + ARM64_REG_B20, + ARM64_REG_B21, + ARM64_REG_B22, + ARM64_REG_B23, + ARM64_REG_B24, + ARM64_REG_B25, + ARM64_REG_B26, + ARM64_REG_B27, + ARM64_REG_B28, + ARM64_REG_B29, + ARM64_REG_B30, + ARM64_REG_B31, + ARM64_REG_D0, + ARM64_REG_D1, + ARM64_REG_D2, + ARM64_REG_D3, + ARM64_REG_D4, + ARM64_REG_D5, + ARM64_REG_D6, + ARM64_REG_D7, + ARM64_REG_D8, + ARM64_REG_D9, + ARM64_REG_D10, + ARM64_REG_D11, + ARM64_REG_D12, + ARM64_REG_D13, + ARM64_REG_D14, + ARM64_REG_D15, + ARM64_REG_D16, + ARM64_REG_D17, + ARM64_REG_D18, + ARM64_REG_D19, + ARM64_REG_D20, + ARM64_REG_D21, + ARM64_REG_D22, + ARM64_REG_D23, + ARM64_REG_D24, + ARM64_REG_D25, + ARM64_REG_D26, + ARM64_REG_D27, + ARM64_REG_D28, + ARM64_REG_D29, + ARM64_REG_D30, + ARM64_REG_D31, + ARM64_REG_H0, + ARM64_REG_H1, + ARM64_REG_H2, + ARM64_REG_H3, + ARM64_REG_H4, + ARM64_REG_H5, + ARM64_REG_H6, + ARM64_REG_H7, + ARM64_REG_H8, + ARM64_REG_H9, + ARM64_REG_H10, + ARM64_REG_H11, + ARM64_REG_H12, + ARM64_REG_H13, + ARM64_REG_H14, + ARM64_REG_H15, + ARM64_REG_H16, + ARM64_REG_H17, + ARM64_REG_H18, + ARM64_REG_H19, + ARM64_REG_H20, + ARM64_REG_H21, + ARM64_REG_H22, + ARM64_REG_H23, + ARM64_REG_H24, + ARM64_REG_H25, + ARM64_REG_H26, + ARM64_REG_H27, + ARM64_REG_H28, + ARM64_REG_H29, + ARM64_REG_H30, + ARM64_REG_H31, + ARM64_REG_P0, + ARM64_REG_P1, + ARM64_REG_P2, + ARM64_REG_P3, + ARM64_REG_P4, + ARM64_REG_P5, + ARM64_REG_P6, + ARM64_REG_P7, + ARM64_REG_P8, + ARM64_REG_P9, + ARM64_REG_P10, + ARM64_REG_P11, + ARM64_REG_P12, + ARM64_REG_P13, + ARM64_REG_P14, + ARM64_REG_P15, + ARM64_REG_Q0, + ARM64_REG_Q1, + ARM64_REG_Q2, + ARM64_REG_Q3, + ARM64_REG_Q4, + ARM64_REG_Q5, + ARM64_REG_Q6, + ARM64_REG_Q7, + ARM64_REG_Q8, + ARM64_REG_Q9, + ARM64_REG_Q10, + ARM64_REG_Q11, + ARM64_REG_Q12, + ARM64_REG_Q13, + ARM64_REG_Q14, + ARM64_REG_Q15, + ARM64_REG_Q16, + ARM64_REG_Q17, + ARM64_REG_Q18, + ARM64_REG_Q19, + ARM64_REG_Q20, + ARM64_REG_Q21, + ARM64_REG_Q22, + ARM64_REG_Q23, + ARM64_REG_Q24, + ARM64_REG_Q25, + ARM64_REG_Q26, + ARM64_REG_Q27, + ARM64_REG_Q28, + ARM64_REG_Q29, + ARM64_REG_Q30, + ARM64_REG_Q31, + ARM64_REG_S0, + ARM64_REG_S1, + ARM64_REG_S2, + ARM64_REG_S3, + ARM64_REG_S4, + ARM64_REG_S5, + ARM64_REG_S6, + ARM64_REG_S7, + ARM64_REG_S8, + ARM64_REG_S9, + ARM64_REG_S10, + ARM64_REG_S11, + ARM64_REG_S12, + ARM64_REG_S13, + ARM64_REG_S14, + ARM64_REG_S15, + ARM64_REG_S16, + ARM64_REG_S17, + ARM64_REG_S18, + ARM64_REG_S19, + ARM64_REG_S20, + ARM64_REG_S21, + ARM64_REG_S22, + ARM64_REG_S23, + ARM64_REG_S24, + ARM64_REG_S25, + ARM64_REG_S26, + ARM64_REG_S27, + ARM64_REG_S28, + ARM64_REG_S29, + ARM64_REG_S30, + ARM64_REG_S31, + ARM64_REG_W0, + ARM64_REG_W1, + ARM64_REG_W2, + ARM64_REG_W3, + ARM64_REG_W4, + ARM64_REG_W5, + ARM64_REG_W6, + ARM64_REG_W7, + ARM64_REG_W8, + ARM64_REG_W9, + ARM64_REG_W10, + ARM64_REG_W11, + ARM64_REG_W12, + ARM64_REG_W13, + ARM64_REG_W14, + ARM64_REG_W15, + ARM64_REG_W16, + ARM64_REG_W17, + ARM64_REG_W18, + ARM64_REG_W19, + ARM64_REG_W20, + ARM64_REG_W21, + ARM64_REG_W22, + ARM64_REG_W23, + ARM64_REG_W24, + ARM64_REG_W25, + ARM64_REG_W26, + ARM64_REG_W27, + ARM64_REG_W28, + ARM64_REG_W29, + ARM64_REG_W30, + ARM64_REG_X0, + ARM64_REG_X1, + ARM64_REG_X2, + ARM64_REG_X3, + ARM64_REG_X4, + ARM64_REG_X5, + ARM64_REG_X6, + ARM64_REG_X7, + ARM64_REG_X8, + ARM64_REG_X9, + ARM64_REG_X10, + ARM64_REG_X11, + ARM64_REG_X12, + ARM64_REG_X13, + ARM64_REG_X14, + ARM64_REG_X15, + ARM64_REG_X16, + ARM64_REG_X17, + ARM64_REG_X18, + ARM64_REG_X19, + ARM64_REG_X20, + ARM64_REG_X21, + ARM64_REG_X22, + ARM64_REG_X23, + ARM64_REG_X24, + ARM64_REG_X25, + ARM64_REG_X26, + ARM64_REG_X27, + ARM64_REG_X28, + ARM64_REG_Z0, + ARM64_REG_Z1, + ARM64_REG_Z2, + ARM64_REG_Z3, + ARM64_REG_Z4, + ARM64_REG_Z5, + ARM64_REG_Z6, + ARM64_REG_Z7, + ARM64_REG_Z8, + ARM64_REG_Z9, + ARM64_REG_Z10, + ARM64_REG_Z11, + ARM64_REG_Z12, + ARM64_REG_Z13, + ARM64_REG_Z14, + ARM64_REG_Z15, + ARM64_REG_Z16, + ARM64_REG_Z17, + ARM64_REG_Z18, + ARM64_REG_Z19, + ARM64_REG_Z20, + ARM64_REG_Z21, + ARM64_REG_Z22, + ARM64_REG_Z23, + ARM64_REG_Z24, + ARM64_REG_Z25, + ARM64_REG_Z26, + ARM64_REG_Z27, + ARM64_REG_Z28, + ARM64_REG_Z29, + ARM64_REG_Z30, + ARM64_REG_Z31, - ARM64_REG_V0, - ARM64_REG_V1, - ARM64_REG_V2, - ARM64_REG_V3, - ARM64_REG_V4, - ARM64_REG_V5, - ARM64_REG_V6, - ARM64_REG_V7, - ARM64_REG_V8, - ARM64_REG_V9, - ARM64_REG_V10, - ARM64_REG_V11, - ARM64_REG_V12, - ARM64_REG_V13, - ARM64_REG_V14, - ARM64_REG_V15, - ARM64_REG_V16, - ARM64_REG_V17, - ARM64_REG_V18, - ARM64_REG_V19, - ARM64_REG_V20, - ARM64_REG_V21, - ARM64_REG_V22, - ARM64_REG_V23, - ARM64_REG_V24, - ARM64_REG_V25, - ARM64_REG_V26, - ARM64_REG_V27, - ARM64_REG_V28, - ARM64_REG_V29, - ARM64_REG_V30, - ARM64_REG_V31, + ARM64_REG_V0, + ARM64_REG_V1, + ARM64_REG_V2, + ARM64_REG_V3, + ARM64_REG_V4, + ARM64_REG_V5, + ARM64_REG_V6, + ARM64_REG_V7, + ARM64_REG_V8, + ARM64_REG_V9, + ARM64_REG_V10, + ARM64_REG_V11, + ARM64_REG_V12, + ARM64_REG_V13, + ARM64_REG_V14, + ARM64_REG_V15, + ARM64_REG_V16, + ARM64_REG_V17, + ARM64_REG_V18, + ARM64_REG_V19, + ARM64_REG_V20, + ARM64_REG_V21, + ARM64_REG_V22, + ARM64_REG_V23, + ARM64_REG_V24, + ARM64_REG_V25, + ARM64_REG_V26, + ARM64_REG_V27, + ARM64_REG_V28, + ARM64_REG_V29, + ARM64_REG_V30, + ARM64_REG_V31, - ARM64_REG_ENDING, // <-- mark the end of the list of registers + ARM64_REG_ENDING, // <-- mark the end of the list of registers - // alias registers - ARM64_REG_IP0 = ARM64_REG_X16, - ARM64_REG_IP1 = ARM64_REG_X17, - ARM64_REG_X29 = ARM64_REG_FP, - ARM64_REG_X30 = ARM64_REG_LR, + // alias registers + ARM64_REG_IP0 = ARM64_REG_X16, + ARM64_REG_IP1 = ARM64_REG_X17, + ARM64_REG_X29 = ARM64_REG_FP, + ARM64_REG_X30 = ARM64_REG_LR, } arm64_reg; /// Instruction's operand referring to memory /// This is associated with ARM64_OP_MEM operand type above typedef struct arm64_op_mem { - arm64_reg base; ///< base register - arm64_reg index; ///< index register - int32_t disp; ///< displacement/offset value + arm64_reg base; ///< base register + arm64_reg index; ///< index register + int32_t disp; ///< displacement/offset value } arm64_op_mem; /// Instruction operand typedef struct cs_arm64_op { - int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) - arm64_vas vas; ///< Vector Arrangement Specifier - struct { - arm64_shifter type; ///< shifter type of this operand - unsigned int value; ///< shifter value of this operand - } shift; - arm64_extender ext; ///< extender type of this operand - arm64_op_type type; ///< operand type - union { - arm64_reg reg; ///< register value for REG operand - int64_t imm; ///< immediate value, or index for C-IMM or IMM operand - double fp; ///< floating point value for FP operand - arm64_op_mem mem; ///< base/index/scale/disp value for MEM operand - arm64_pstate pstate; ///< PState field of MSR instruction. - unsigned int sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op) - arm64_prefetch_op prefetch; ///< PRFM operation. - arm64_barrier_op barrier; ///< Memory barrier operation (ISB/DMB/DSB instructions). - }; + int vector_index; ///< Vector Index for some vector operands (or -1 if + ///< irrelevant) + arm64_vas vas; ///< Vector Arrangement Specifier + struct { + arm64_shifter type; ///< shifter type of this operand + unsigned int value; ///< shifter value of this operand + } shift; + arm64_extender ext; ///< extender type of this operand + arm64_op_type type; ///< operand type + union { + arm64_reg reg; ///< register value for REG operand + int64_t imm; ///< immediate value, or index for C-IMM or IMM operand + double fp; ///< floating point value for FP operand + arm64_op_mem mem; ///< base/index/scale/disp value for MEM operand + arm64_pstate pstate; ///< PState field of MSR instruction. + unsigned int sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, + ///< arm64_dc_op, arm64_at_op, arm64_tlbi_op) + arm64_prefetch_op prefetch; ///< PRFM operation. + arm64_barrier_op + barrier; ///< Memory barrier operation (ISB/DMB/DSB instructions). + }; - /// How is this operand accessed? (READ, WRITE or READ|WRITE) - /// This field is combined of cs_ac_type. - /// NOTE: this field is irrelevant if engine is compiled in DIET mode. - uint8_t access; + /// How is this operand accessed? (READ, WRITE or READ|WRITE) + /// This field is combined of cs_ac_type. + /// NOTE: this field is irrelevant if engine is compiled in DIET mode. + uint8_t access; } cs_arm64_op; /// Instruction structure typedef struct cs_arm64 { - arm64_cc cc; ///< conditional code for this insn - bool update_flags; ///< does this insn update flags? - bool writeback; ///< does this insn request writeback? 'True' means 'yes' + arm64_cc cc; ///< conditional code for this insn + bool update_flags; ///< does this insn update flags? + bool writeback; ///< does this insn request writeback? 'True' means 'yes' - /// Number of operands of this instruction, - /// or 0 when instruction has no operand. - uint8_t op_count; + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; - cs_arm64_op operands[8]; ///< operands for this instruction. + cs_arm64_op operands[8]; ///< operands for this instruction. } cs_arm64; /// ARM64 instruction typedef enum arm64_insn { - ARM64_INS_INVALID = 0, + ARM64_INS_INVALID = 0, - ARM64_INS_ABS, - ARM64_INS_ADC, - ARM64_INS_ADCS, - ARM64_INS_ADD, - ARM64_INS_ADDHN, - ARM64_INS_ADDHN2, - ARM64_INS_ADDP, - ARM64_INS_ADDPL, - ARM64_INS_ADDS, - ARM64_INS_ADDV, - ARM64_INS_ADDVL, - ARM64_INS_ADR, - ARM64_INS_ADRP, - ARM64_INS_AESD, - ARM64_INS_AESE, - ARM64_INS_AESIMC, - ARM64_INS_AESMC, - ARM64_INS_AND, - ARM64_INS_ANDS, - ARM64_INS_ANDV, - ARM64_INS_ASR, - ARM64_INS_ASRD, - ARM64_INS_ASRR, - ARM64_INS_ASRV, - ARM64_INS_AUTDA, - ARM64_INS_AUTDB, - ARM64_INS_AUTDZA, - ARM64_INS_AUTDZB, - ARM64_INS_AUTIA, - ARM64_INS_AUTIA1716, - ARM64_INS_AUTIASP, - ARM64_INS_AUTIAZ, - ARM64_INS_AUTIB, - ARM64_INS_AUTIB1716, - ARM64_INS_AUTIBSP, - ARM64_INS_AUTIBZ, - ARM64_INS_AUTIZA, - ARM64_INS_AUTIZB, - ARM64_INS_B, - ARM64_INS_BCAX, - ARM64_INS_BFM, - ARM64_INS_BIC, - ARM64_INS_BICS, - ARM64_INS_BIF, - ARM64_INS_BIT, - ARM64_INS_BL, - ARM64_INS_BLR, - ARM64_INS_BLRAA, - ARM64_INS_BLRAAZ, - ARM64_INS_BLRAB, - ARM64_INS_BLRABZ, - ARM64_INS_BR, - ARM64_INS_BRAA, - ARM64_INS_BRAAZ, - ARM64_INS_BRAB, - ARM64_INS_BRABZ, - ARM64_INS_BRK, - ARM64_INS_BRKA, - ARM64_INS_BRKAS, - ARM64_INS_BRKB, - ARM64_INS_BRKBS, - ARM64_INS_BRKN, - ARM64_INS_BRKNS, - ARM64_INS_BRKPA, - ARM64_INS_BRKPAS, - ARM64_INS_BRKPB, - ARM64_INS_BRKPBS, - ARM64_INS_BSL, - ARM64_INS_CAS, - ARM64_INS_CASA, - ARM64_INS_CASAB, - ARM64_INS_CASAH, - ARM64_INS_CASAL, - ARM64_INS_CASALB, - ARM64_INS_CASALH, - ARM64_INS_CASB, - ARM64_INS_CASH, - ARM64_INS_CASL, - ARM64_INS_CASLB, - ARM64_INS_CASLH, - ARM64_INS_CASP, - ARM64_INS_CASPA, - ARM64_INS_CASPAL, - ARM64_INS_CASPL, - ARM64_INS_CBNZ, - ARM64_INS_CBZ, - ARM64_INS_CCMN, - ARM64_INS_CCMP, - ARM64_INS_CFINV, - ARM64_INS_CINC, - ARM64_INS_CINV, - ARM64_INS_CLASTA, - ARM64_INS_CLASTB, - ARM64_INS_CLREX, - ARM64_INS_CLS, - ARM64_INS_CLZ, - ARM64_INS_CMEQ, - ARM64_INS_CMGE, - ARM64_INS_CMGT, - ARM64_INS_CMHI, - ARM64_INS_CMHS, - ARM64_INS_CMLE, - ARM64_INS_CMLO, - ARM64_INS_CMLS, - ARM64_INS_CMLT, - ARM64_INS_CMN, - ARM64_INS_CMP, - ARM64_INS_CMPEQ, - ARM64_INS_CMPGE, - ARM64_INS_CMPGT, - ARM64_INS_CMPHI, - ARM64_INS_CMPHS, - ARM64_INS_CMPLE, - ARM64_INS_CMPLO, - ARM64_INS_CMPLS, - ARM64_INS_CMPLT, - ARM64_INS_CMPNE, - ARM64_INS_CMTST, - ARM64_INS_CNEG, - ARM64_INS_CNOT, - ARM64_INS_CNT, - ARM64_INS_CNTB, - ARM64_INS_CNTD, - ARM64_INS_CNTH, - ARM64_INS_CNTP, - ARM64_INS_CNTW, - ARM64_INS_COMPACT, - ARM64_INS_CPY, - ARM64_INS_CRC32B, - ARM64_INS_CRC32CB, - ARM64_INS_CRC32CH, - ARM64_INS_CRC32CW, - ARM64_INS_CRC32CX, - ARM64_INS_CRC32H, - ARM64_INS_CRC32W, - ARM64_INS_CRC32X, - ARM64_INS_CSDB, - ARM64_INS_CSEL, - ARM64_INS_CSET, - ARM64_INS_CSETM, - ARM64_INS_CSINC, - ARM64_INS_CSINV, - ARM64_INS_CSNEG, - ARM64_INS_CTERMEQ, - ARM64_INS_CTERMNE, - ARM64_INS_DCPS1, - ARM64_INS_DCPS2, - ARM64_INS_DCPS3, - ARM64_INS_DECB, - ARM64_INS_DECD, - ARM64_INS_DECH, - ARM64_INS_DECP, - ARM64_INS_DECW, - ARM64_INS_DMB, - ARM64_INS_DRPS, - ARM64_INS_DSB, - ARM64_INS_DUP, - ARM64_INS_DUPM, - ARM64_INS_EON, - ARM64_INS_EOR, - ARM64_INS_EOR3, - ARM64_INS_EORS, - ARM64_INS_EORV, - ARM64_INS_ERET, - ARM64_INS_ERETAA, - ARM64_INS_ERETAB, - ARM64_INS_ESB, - ARM64_INS_EXT, - ARM64_INS_EXTR, - ARM64_INS_FABD, - ARM64_INS_FABS, - ARM64_INS_FACGE, - ARM64_INS_FACGT, - ARM64_INS_FACLE, - ARM64_INS_FACLT, - ARM64_INS_FADD, - ARM64_INS_FADDA, - ARM64_INS_FADDP, - ARM64_INS_FADDV, - ARM64_INS_FCADD, - ARM64_INS_FCCMP, - ARM64_INS_FCCMPE, - ARM64_INS_FCMEQ, - ARM64_INS_FCMGE, - ARM64_INS_FCMGT, - ARM64_INS_FCMLA, - ARM64_INS_FCMLE, - ARM64_INS_FCMLT, - ARM64_INS_FCMNE, - ARM64_INS_FCMP, - ARM64_INS_FCMPE, - ARM64_INS_FCMUO, - ARM64_INS_FCPY, - ARM64_INS_FCSEL, - ARM64_INS_FCVT, - ARM64_INS_FCVTAS, - ARM64_INS_FCVTAU, - ARM64_INS_FCVTL, - ARM64_INS_FCVTL2, - ARM64_INS_FCVTMS, - ARM64_INS_FCVTMU, - ARM64_INS_FCVTN, - ARM64_INS_FCVTN2, - ARM64_INS_FCVTNS, - ARM64_INS_FCVTNU, - ARM64_INS_FCVTPS, - ARM64_INS_FCVTPU, - ARM64_INS_FCVTXN, - ARM64_INS_FCVTXN2, - ARM64_INS_FCVTZS, - ARM64_INS_FCVTZU, - ARM64_INS_FDIV, - ARM64_INS_FDIVR, - ARM64_INS_FDUP, - ARM64_INS_FEXPA, - ARM64_INS_FJCVTZS, - ARM64_INS_FMAD, - ARM64_INS_FMADD, - ARM64_INS_FMAX, - ARM64_INS_FMAXNM, - ARM64_INS_FMAXNMP, - ARM64_INS_FMAXNMV, - ARM64_INS_FMAXP, - ARM64_INS_FMAXV, - ARM64_INS_FMIN, - ARM64_INS_FMINNM, - ARM64_INS_FMINNMP, - ARM64_INS_FMINNMV, - ARM64_INS_FMINP, - ARM64_INS_FMINV, - ARM64_INS_FMLA, - ARM64_INS_FMLS, - ARM64_INS_FMOV, - ARM64_INS_FMSB, - ARM64_INS_FMSUB, - ARM64_INS_FMUL, - ARM64_INS_FMULX, - ARM64_INS_FNEG, - ARM64_INS_FNMAD, - ARM64_INS_FNMADD, - ARM64_INS_FNMLA, - ARM64_INS_FNMLS, - ARM64_INS_FNMSB, - ARM64_INS_FNMSUB, - ARM64_INS_FNMUL, - ARM64_INS_FRECPE, - ARM64_INS_FRECPS, - ARM64_INS_FRECPX, - ARM64_INS_FRINTA, - ARM64_INS_FRINTI, - ARM64_INS_FRINTM, - ARM64_INS_FRINTN, - ARM64_INS_FRINTP, - ARM64_INS_FRINTX, - ARM64_INS_FRINTZ, - ARM64_INS_FRSQRTE, - ARM64_INS_FRSQRTS, - ARM64_INS_FSCALE, - ARM64_INS_FSQRT, - ARM64_INS_FSUB, - ARM64_INS_FSUBR, - ARM64_INS_FTMAD, - ARM64_INS_FTSMUL, - ARM64_INS_FTSSEL, - ARM64_INS_HINT, - ARM64_INS_HLT, - ARM64_INS_HVC, - ARM64_INS_INCB, - ARM64_INS_INCD, - ARM64_INS_INCH, - ARM64_INS_INCP, - ARM64_INS_INCW, - ARM64_INS_INDEX, - ARM64_INS_INS, - ARM64_INS_INSR, - ARM64_INS_ISB, - ARM64_INS_LASTA, - ARM64_INS_LASTB, - ARM64_INS_LD1, - ARM64_INS_LD1B, - ARM64_INS_LD1D, - ARM64_INS_LD1H, - ARM64_INS_LD1R, - ARM64_INS_LD1RB, - ARM64_INS_LD1RD, - ARM64_INS_LD1RH, - ARM64_INS_LD1RQB, - ARM64_INS_LD1RQD, - ARM64_INS_LD1RQH, - ARM64_INS_LD1RQW, - ARM64_INS_LD1RSB, - ARM64_INS_LD1RSH, - ARM64_INS_LD1RSW, - ARM64_INS_LD1RW, - ARM64_INS_LD1SB, - ARM64_INS_LD1SH, - ARM64_INS_LD1SW, - ARM64_INS_LD1W, - ARM64_INS_LD2, - ARM64_INS_LD2B, - ARM64_INS_LD2D, - ARM64_INS_LD2H, - ARM64_INS_LD2R, - ARM64_INS_LD2W, - ARM64_INS_LD3, - ARM64_INS_LD3B, - ARM64_INS_LD3D, - ARM64_INS_LD3H, - ARM64_INS_LD3R, - ARM64_INS_LD3W, - ARM64_INS_LD4, - ARM64_INS_LD4B, - ARM64_INS_LD4D, - ARM64_INS_LD4H, - ARM64_INS_LD4R, - ARM64_INS_LD4W, - ARM64_INS_LDADD, - ARM64_INS_LDADDA, - ARM64_INS_LDADDAB, - ARM64_INS_LDADDAH, - ARM64_INS_LDADDAL, - ARM64_INS_LDADDALB, - ARM64_INS_LDADDALH, - ARM64_INS_LDADDB, - ARM64_INS_LDADDH, - ARM64_INS_LDADDL, - ARM64_INS_LDADDLB, - ARM64_INS_LDADDLH, - ARM64_INS_LDAPR, - ARM64_INS_LDAPRB, - ARM64_INS_LDAPRH, - ARM64_INS_LDAPUR, - ARM64_INS_LDAPURB, - ARM64_INS_LDAPURH, - ARM64_INS_LDAPURSB, - ARM64_INS_LDAPURSH, - ARM64_INS_LDAPURSW, - ARM64_INS_LDAR, - ARM64_INS_LDARB, - ARM64_INS_LDARH, - ARM64_INS_LDAXP, - ARM64_INS_LDAXR, - ARM64_INS_LDAXRB, - ARM64_INS_LDAXRH, - ARM64_INS_LDCLR, - ARM64_INS_LDCLRA, - ARM64_INS_LDCLRAB, - ARM64_INS_LDCLRAH, - ARM64_INS_LDCLRAL, - ARM64_INS_LDCLRALB, - ARM64_INS_LDCLRALH, - ARM64_INS_LDCLRB, - ARM64_INS_LDCLRH, - ARM64_INS_LDCLRL, - ARM64_INS_LDCLRLB, - ARM64_INS_LDCLRLH, - ARM64_INS_LDEOR, - ARM64_INS_LDEORA, - ARM64_INS_LDEORAB, - ARM64_INS_LDEORAH, - ARM64_INS_LDEORAL, - ARM64_INS_LDEORALB, - ARM64_INS_LDEORALH, - ARM64_INS_LDEORB, - ARM64_INS_LDEORH, - ARM64_INS_LDEORL, - ARM64_INS_LDEORLB, - ARM64_INS_LDEORLH, - ARM64_INS_LDFF1B, - ARM64_INS_LDFF1D, - ARM64_INS_LDFF1H, - ARM64_INS_LDFF1SB, - ARM64_INS_LDFF1SH, - ARM64_INS_LDFF1SW, - ARM64_INS_LDFF1W, - ARM64_INS_LDLAR, - ARM64_INS_LDLARB, - ARM64_INS_LDLARH, - ARM64_INS_LDNF1B, - ARM64_INS_LDNF1D, - ARM64_INS_LDNF1H, - ARM64_INS_LDNF1SB, - ARM64_INS_LDNF1SH, - ARM64_INS_LDNF1SW, - ARM64_INS_LDNF1W, - ARM64_INS_LDNP, - ARM64_INS_LDNT1B, - ARM64_INS_LDNT1D, - ARM64_INS_LDNT1H, - ARM64_INS_LDNT1W, - ARM64_INS_LDP, - ARM64_INS_LDPSW, - ARM64_INS_LDR, - ARM64_INS_LDRAA, - ARM64_INS_LDRAB, - ARM64_INS_LDRB, - ARM64_INS_LDRH, - ARM64_INS_LDRSB, - ARM64_INS_LDRSH, - ARM64_INS_LDRSW, - ARM64_INS_LDSET, - ARM64_INS_LDSETA, - ARM64_INS_LDSETAB, - ARM64_INS_LDSETAH, - ARM64_INS_LDSETAL, - ARM64_INS_LDSETALB, - ARM64_INS_LDSETALH, - ARM64_INS_LDSETB, - ARM64_INS_LDSETH, - ARM64_INS_LDSETL, - ARM64_INS_LDSETLB, - ARM64_INS_LDSETLH, - ARM64_INS_LDSMAX, - ARM64_INS_LDSMAXA, - ARM64_INS_LDSMAXAB, - ARM64_INS_LDSMAXAH, - ARM64_INS_LDSMAXAL, - ARM64_INS_LDSMAXALB, - ARM64_INS_LDSMAXALH, - ARM64_INS_LDSMAXB, - ARM64_INS_LDSMAXH, - ARM64_INS_LDSMAXL, - ARM64_INS_LDSMAXLB, - ARM64_INS_LDSMAXLH, - ARM64_INS_LDSMIN, - ARM64_INS_LDSMINA, - ARM64_INS_LDSMINAB, - ARM64_INS_LDSMINAH, - ARM64_INS_LDSMINAL, - ARM64_INS_LDSMINALB, - ARM64_INS_LDSMINALH, - ARM64_INS_LDSMINB, - ARM64_INS_LDSMINH, - ARM64_INS_LDSMINL, - ARM64_INS_LDSMINLB, - ARM64_INS_LDSMINLH, - ARM64_INS_LDTR, - ARM64_INS_LDTRB, - ARM64_INS_LDTRH, - ARM64_INS_LDTRSB, - ARM64_INS_LDTRSH, - ARM64_INS_LDTRSW, - ARM64_INS_LDUMAX, - ARM64_INS_LDUMAXA, - ARM64_INS_LDUMAXAB, - ARM64_INS_LDUMAXAH, - ARM64_INS_LDUMAXAL, - ARM64_INS_LDUMAXALB, - ARM64_INS_LDUMAXALH, - ARM64_INS_LDUMAXB, - ARM64_INS_LDUMAXH, - ARM64_INS_LDUMAXL, - ARM64_INS_LDUMAXLB, - ARM64_INS_LDUMAXLH, - ARM64_INS_LDUMIN, - ARM64_INS_LDUMINA, - ARM64_INS_LDUMINAB, - ARM64_INS_LDUMINAH, - ARM64_INS_LDUMINAL, - ARM64_INS_LDUMINALB, - ARM64_INS_LDUMINALH, - ARM64_INS_LDUMINB, - ARM64_INS_LDUMINH, - ARM64_INS_LDUMINL, - ARM64_INS_LDUMINLB, - ARM64_INS_LDUMINLH, - ARM64_INS_LDUR, - ARM64_INS_LDURB, - ARM64_INS_LDURH, - ARM64_INS_LDURSB, - ARM64_INS_LDURSH, - ARM64_INS_LDURSW, - ARM64_INS_LDXP, - ARM64_INS_LDXR, - ARM64_INS_LDXRB, - ARM64_INS_LDXRH, - ARM64_INS_LSL, - ARM64_INS_LSLR, - ARM64_INS_LSLV, - ARM64_INS_LSR, - ARM64_INS_LSRR, - ARM64_INS_LSRV, - ARM64_INS_MAD, - ARM64_INS_MADD, - ARM64_INS_MLA, - ARM64_INS_MLS, - ARM64_INS_MNEG, - ARM64_INS_MOV, - ARM64_INS_MOVI, - ARM64_INS_MOVK, - ARM64_INS_MOVN, - ARM64_INS_MOVPRFX, - ARM64_INS_MOVS, - ARM64_INS_MOVZ, - ARM64_INS_MRS, - ARM64_INS_MSB, - ARM64_INS_MSR, - ARM64_INS_MSUB, - ARM64_INS_MUL, - ARM64_INS_MVN, - ARM64_INS_MVNI, - ARM64_INS_NAND, - ARM64_INS_NANDS, - ARM64_INS_NEG, - ARM64_INS_NEGS, - ARM64_INS_NGC, - ARM64_INS_NGCS, - ARM64_INS_NOP, - ARM64_INS_NOR, - ARM64_INS_NORS, - ARM64_INS_NOT, - ARM64_INS_NOTS, - ARM64_INS_ORN, - ARM64_INS_ORNS, - ARM64_INS_ORR, - ARM64_INS_ORRS, - ARM64_INS_ORV, - ARM64_INS_PACDA, - ARM64_INS_PACDB, - ARM64_INS_PACDZA, - ARM64_INS_PACDZB, - ARM64_INS_PACGA, - ARM64_INS_PACIA, - ARM64_INS_PACIA1716, - ARM64_INS_PACIASP, - ARM64_INS_PACIAZ, - ARM64_INS_PACIB, - ARM64_INS_PACIB1716, - ARM64_INS_PACIBSP, - ARM64_INS_PACIBZ, - ARM64_INS_PACIZA, - ARM64_INS_PACIZB, - ARM64_INS_PFALSE, - ARM64_INS_PFIRST, - ARM64_INS_PMUL, - ARM64_INS_PMULL, - ARM64_INS_PMULL2, - ARM64_INS_PNEXT, - ARM64_INS_PRFB, - ARM64_INS_PRFD, - ARM64_INS_PRFH, - ARM64_INS_PRFM, - ARM64_INS_PRFUM, - ARM64_INS_PRFW, - ARM64_INS_PSB, - ARM64_INS_PTEST, - ARM64_INS_PTRUE, - ARM64_INS_PTRUES, - ARM64_INS_PUNPKHI, - ARM64_INS_PUNPKLO, - ARM64_INS_RADDHN, - ARM64_INS_RADDHN2, - ARM64_INS_RAX1, - ARM64_INS_RBIT, - ARM64_INS_RDFFR, - ARM64_INS_RDFFRS, - ARM64_INS_RDVL, - ARM64_INS_RET, - ARM64_INS_RETAA, - ARM64_INS_RETAB, - ARM64_INS_REV, - ARM64_INS_REV16, - ARM64_INS_REV32, - ARM64_INS_REV64, - ARM64_INS_REVB, - ARM64_INS_REVH, - ARM64_INS_REVW, - ARM64_INS_RMIF, - ARM64_INS_ROR, - ARM64_INS_RORV, - ARM64_INS_RSHRN, - ARM64_INS_RSHRN2, - ARM64_INS_RSUBHN, - ARM64_INS_RSUBHN2, - ARM64_INS_SABA, - ARM64_INS_SABAL, - ARM64_INS_SABAL2, - ARM64_INS_SABD, - ARM64_INS_SABDL, - ARM64_INS_SABDL2, - ARM64_INS_SADALP, - ARM64_INS_SADDL, - ARM64_INS_SADDL2, - ARM64_INS_SADDLP, - ARM64_INS_SADDLV, - ARM64_INS_SADDV, - ARM64_INS_SADDW, - ARM64_INS_SADDW2, - ARM64_INS_SBC, - ARM64_INS_SBCS, - ARM64_INS_SBFM, - ARM64_INS_SCVTF, - ARM64_INS_SDIV, - ARM64_INS_SDIVR, - ARM64_INS_SDOT, - ARM64_INS_SEL, - ARM64_INS_SETF16, - ARM64_INS_SETF8, - ARM64_INS_SETFFR, - ARM64_INS_SEV, - ARM64_INS_SEVL, - ARM64_INS_SHA1C, - ARM64_INS_SHA1H, - ARM64_INS_SHA1M, - ARM64_INS_SHA1P, - ARM64_INS_SHA1SU0, - ARM64_INS_SHA1SU1, - ARM64_INS_SHA256H, - ARM64_INS_SHA256H2, - ARM64_INS_SHA256SU0, - ARM64_INS_SHA256SU1, - ARM64_INS_SHA512H, - ARM64_INS_SHA512H2, - ARM64_INS_SHA512SU0, - ARM64_INS_SHA512SU1, - ARM64_INS_SHADD, - ARM64_INS_SHL, - ARM64_INS_SHLL, - ARM64_INS_SHLL2, - ARM64_INS_SHRN, - ARM64_INS_SHRN2, - ARM64_INS_SHSUB, - ARM64_INS_SLI, - ARM64_INS_SM3PARTW1, - ARM64_INS_SM3PARTW2, - ARM64_INS_SM3SS1, - ARM64_INS_SM3TT1A, - ARM64_INS_SM3TT1B, - ARM64_INS_SM3TT2A, - ARM64_INS_SM3TT2B, - ARM64_INS_SM4E, - ARM64_INS_SM4EKEY, - ARM64_INS_SMADDL, - ARM64_INS_SMAX, - ARM64_INS_SMAXP, - ARM64_INS_SMAXV, - ARM64_INS_SMC, - ARM64_INS_SMIN, - ARM64_INS_SMINP, - ARM64_INS_SMINV, - ARM64_INS_SMLAL, - ARM64_INS_SMLAL2, - ARM64_INS_SMLSL, - ARM64_INS_SMLSL2, - ARM64_INS_SMNEGL, - ARM64_INS_SMOV, - ARM64_INS_SMSUBL, - ARM64_INS_SMULH, - ARM64_INS_SMULL, - ARM64_INS_SMULL2, - ARM64_INS_SPLICE, - ARM64_INS_SQABS, - ARM64_INS_SQADD, - ARM64_INS_SQDECB, - ARM64_INS_SQDECD, - ARM64_INS_SQDECH, - ARM64_INS_SQDECP, - ARM64_INS_SQDECW, - ARM64_INS_SQDMLAL, - ARM64_INS_SQDMLAL2, - ARM64_INS_SQDMLSL, - ARM64_INS_SQDMLSL2, - ARM64_INS_SQDMULH, - ARM64_INS_SQDMULL, - ARM64_INS_SQDMULL2, - ARM64_INS_SQINCB, - ARM64_INS_SQINCD, - ARM64_INS_SQINCH, - ARM64_INS_SQINCP, - ARM64_INS_SQINCW, - ARM64_INS_SQNEG, - ARM64_INS_SQRDMLAH, - ARM64_INS_SQRDMLSH, - ARM64_INS_SQRDMULH, - ARM64_INS_SQRSHL, - ARM64_INS_SQRSHRN, - ARM64_INS_SQRSHRN2, - ARM64_INS_SQRSHRUN, - ARM64_INS_SQRSHRUN2, - ARM64_INS_SQSHL, - ARM64_INS_SQSHLU, - ARM64_INS_SQSHRN, - ARM64_INS_SQSHRN2, - ARM64_INS_SQSHRUN, - ARM64_INS_SQSHRUN2, - ARM64_INS_SQSUB, - ARM64_INS_SQXTN, - ARM64_INS_SQXTN2, - ARM64_INS_SQXTUN, - ARM64_INS_SQXTUN2, - ARM64_INS_SRHADD, - ARM64_INS_SRI, - ARM64_INS_SRSHL, - ARM64_INS_SRSHR, - ARM64_INS_SRSRA, - ARM64_INS_SSHL, - ARM64_INS_SSHLL, - ARM64_INS_SSHLL2, - ARM64_INS_SSHR, - ARM64_INS_SSRA, - ARM64_INS_SSUBL, - ARM64_INS_SSUBL2, - ARM64_INS_SSUBW, - ARM64_INS_SSUBW2, - ARM64_INS_ST1, - ARM64_INS_ST1B, - ARM64_INS_ST1D, - ARM64_INS_ST1H, - ARM64_INS_ST1W, - ARM64_INS_ST2, - ARM64_INS_ST2B, - ARM64_INS_ST2D, - ARM64_INS_ST2H, - ARM64_INS_ST2W, - ARM64_INS_ST3, - ARM64_INS_ST3B, - ARM64_INS_ST3D, - ARM64_INS_ST3H, - ARM64_INS_ST3W, - ARM64_INS_ST4, - ARM64_INS_ST4B, - ARM64_INS_ST4D, - ARM64_INS_ST4H, - ARM64_INS_ST4W, - ARM64_INS_STADD, - ARM64_INS_STADDB, - ARM64_INS_STADDH, - ARM64_INS_STADDL, - ARM64_INS_STADDLB, - ARM64_INS_STADDLH, - ARM64_INS_STCLR, - ARM64_INS_STCLRB, - ARM64_INS_STCLRH, - ARM64_INS_STCLRL, - ARM64_INS_STCLRLB, - ARM64_INS_STCLRLH, - ARM64_INS_STEOR, - ARM64_INS_STEORB, - ARM64_INS_STEORH, - ARM64_INS_STEORL, - ARM64_INS_STEORLB, - ARM64_INS_STEORLH, - ARM64_INS_STLLR, - ARM64_INS_STLLRB, - ARM64_INS_STLLRH, - ARM64_INS_STLR, - ARM64_INS_STLRB, - ARM64_INS_STLRH, - ARM64_INS_STLUR, - ARM64_INS_STLURB, - ARM64_INS_STLURH, - ARM64_INS_STLXP, - ARM64_INS_STLXR, - ARM64_INS_STLXRB, - ARM64_INS_STLXRH, - ARM64_INS_STNP, - ARM64_INS_STNT1B, - ARM64_INS_STNT1D, - ARM64_INS_STNT1H, - ARM64_INS_STNT1W, - ARM64_INS_STP, - ARM64_INS_STR, - ARM64_INS_STRB, - ARM64_INS_STRH, - ARM64_INS_STSET, - ARM64_INS_STSETB, - ARM64_INS_STSETH, - ARM64_INS_STSETL, - ARM64_INS_STSETLB, - ARM64_INS_STSETLH, - ARM64_INS_STSMAX, - ARM64_INS_STSMAXB, - ARM64_INS_STSMAXH, - ARM64_INS_STSMAXL, - ARM64_INS_STSMAXLB, - ARM64_INS_STSMAXLH, - ARM64_INS_STSMIN, - ARM64_INS_STSMINB, - ARM64_INS_STSMINH, - ARM64_INS_STSMINL, - ARM64_INS_STSMINLB, - ARM64_INS_STSMINLH, - ARM64_INS_STTR, - ARM64_INS_STTRB, - ARM64_INS_STTRH, - ARM64_INS_STUMAX, - ARM64_INS_STUMAXB, - ARM64_INS_STUMAXH, - ARM64_INS_STUMAXL, - ARM64_INS_STUMAXLB, - ARM64_INS_STUMAXLH, - ARM64_INS_STUMIN, - ARM64_INS_STUMINB, - ARM64_INS_STUMINH, - ARM64_INS_STUMINL, - ARM64_INS_STUMINLB, - ARM64_INS_STUMINLH, - ARM64_INS_STUR, - ARM64_INS_STURB, - ARM64_INS_STURH, - ARM64_INS_STXP, - ARM64_INS_STXR, - ARM64_INS_STXRB, - ARM64_INS_STXRH, - ARM64_INS_SUB, - ARM64_INS_SUBHN, - ARM64_INS_SUBHN2, - ARM64_INS_SUBR, - ARM64_INS_SUBS, - ARM64_INS_SUNPKHI, - ARM64_INS_SUNPKLO, - ARM64_INS_SUQADD, - ARM64_INS_SVC, - ARM64_INS_SWP, - ARM64_INS_SWPA, - ARM64_INS_SWPAB, - ARM64_INS_SWPAH, - ARM64_INS_SWPAL, - ARM64_INS_SWPALB, - ARM64_INS_SWPALH, - ARM64_INS_SWPB, - ARM64_INS_SWPH, - ARM64_INS_SWPL, - ARM64_INS_SWPLB, - ARM64_INS_SWPLH, - ARM64_INS_SXTB, - ARM64_INS_SXTH, - ARM64_INS_SXTL, - ARM64_INS_SXTL2, - ARM64_INS_SXTW, - ARM64_INS_SYS, - ARM64_INS_SYSL, - ARM64_INS_TBL, - ARM64_INS_TBNZ, - ARM64_INS_TBX, - ARM64_INS_TBZ, - ARM64_INS_TRN1, - ARM64_INS_TRN2, - ARM64_INS_TSB, - ARM64_INS_TST, - ARM64_INS_UABA, - ARM64_INS_UABAL, - ARM64_INS_UABAL2, - ARM64_INS_UABD, - ARM64_INS_UABDL, - ARM64_INS_UABDL2, - ARM64_INS_UADALP, - ARM64_INS_UADDL, - ARM64_INS_UADDL2, - ARM64_INS_UADDLP, - ARM64_INS_UADDLV, - ARM64_INS_UADDV, - ARM64_INS_UADDW, - ARM64_INS_UADDW2, - ARM64_INS_UBFM, - ARM64_INS_UCVTF, - ARM64_INS_UDIV, - ARM64_INS_UDIVR, - ARM64_INS_UDOT, - ARM64_INS_UHADD, - ARM64_INS_UHSUB, - ARM64_INS_UMADDL, - ARM64_INS_UMAX, - ARM64_INS_UMAXP, - ARM64_INS_UMAXV, - ARM64_INS_UMIN, - ARM64_INS_UMINP, - ARM64_INS_UMINV, - ARM64_INS_UMLAL, - ARM64_INS_UMLAL2, - ARM64_INS_UMLSL, - ARM64_INS_UMLSL2, - ARM64_INS_UMNEGL, - ARM64_INS_UMOV, - ARM64_INS_UMSUBL, - ARM64_INS_UMULH, - ARM64_INS_UMULL, - ARM64_INS_UMULL2, - ARM64_INS_UQADD, - ARM64_INS_UQDECB, - ARM64_INS_UQDECD, - ARM64_INS_UQDECH, - ARM64_INS_UQDECP, - ARM64_INS_UQDECW, - ARM64_INS_UQINCB, - ARM64_INS_UQINCD, - ARM64_INS_UQINCH, - ARM64_INS_UQINCP, - ARM64_INS_UQINCW, - ARM64_INS_UQRSHL, - ARM64_INS_UQRSHRN, - ARM64_INS_UQRSHRN2, - ARM64_INS_UQSHL, - ARM64_INS_UQSHRN, - ARM64_INS_UQSHRN2, - ARM64_INS_UQSUB, - ARM64_INS_UQXTN, - ARM64_INS_UQXTN2, - ARM64_INS_URECPE, - ARM64_INS_URHADD, - ARM64_INS_URSHL, - ARM64_INS_URSHR, - ARM64_INS_URSQRTE, - ARM64_INS_URSRA, - ARM64_INS_USHL, - ARM64_INS_USHLL, - ARM64_INS_USHLL2, - ARM64_INS_USHR, - ARM64_INS_USQADD, - ARM64_INS_USRA, - ARM64_INS_USUBL, - ARM64_INS_USUBL2, - ARM64_INS_USUBW, - ARM64_INS_USUBW2, - ARM64_INS_UUNPKHI, - ARM64_INS_UUNPKLO, - ARM64_INS_UXTB, - ARM64_INS_UXTH, - ARM64_INS_UXTL, - ARM64_INS_UXTL2, - ARM64_INS_UXTW, - ARM64_INS_UZP1, - ARM64_INS_UZP2, - ARM64_INS_WFE, - ARM64_INS_WFI, - ARM64_INS_WHILELE, - ARM64_INS_WHILELO, - ARM64_INS_WHILELS, - ARM64_INS_WHILELT, - ARM64_INS_WRFFR, - ARM64_INS_XAR, - ARM64_INS_XPACD, - ARM64_INS_XPACI, - ARM64_INS_XPACLRI, - ARM64_INS_XTN, - ARM64_INS_XTN2, - ARM64_INS_YIELD, - ARM64_INS_ZIP1, - ARM64_INS_ZIP2, + ARM64_INS_ABS, + ARM64_INS_ADC, + ARM64_INS_ADCS, + ARM64_INS_ADD, + ARM64_INS_ADDHN, + ARM64_INS_ADDHN2, + ARM64_INS_ADDP, + ARM64_INS_ADDPL, + ARM64_INS_ADDS, + ARM64_INS_ADDV, + ARM64_INS_ADDVL, + ARM64_INS_ADR, + ARM64_INS_ADRP, + ARM64_INS_AESD, + ARM64_INS_AESE, + ARM64_INS_AESIMC, + ARM64_INS_AESMC, + ARM64_INS_AND, + ARM64_INS_ANDS, + ARM64_INS_ANDV, + ARM64_INS_ASR, + ARM64_INS_ASRD, + ARM64_INS_ASRR, + ARM64_INS_ASRV, + ARM64_INS_AUTDA, + ARM64_INS_AUTDB, + ARM64_INS_AUTDZA, + ARM64_INS_AUTDZB, + ARM64_INS_AUTIA, + ARM64_INS_AUTIA1716, + ARM64_INS_AUTIASP, + ARM64_INS_AUTIAZ, + ARM64_INS_AUTIB, + ARM64_INS_AUTIB1716, + ARM64_INS_AUTIBSP, + ARM64_INS_AUTIBZ, + ARM64_INS_AUTIZA, + ARM64_INS_AUTIZB, + ARM64_INS_B, + ARM64_INS_BCAX, + ARM64_INS_BFM, + ARM64_INS_BIC, + ARM64_INS_BICS, + ARM64_INS_BIF, + ARM64_INS_BIT, + ARM64_INS_BL, + ARM64_INS_BLR, + ARM64_INS_BLRAA, + ARM64_INS_BLRAAZ, + ARM64_INS_BLRAB, + ARM64_INS_BLRABZ, + ARM64_INS_BR, + ARM64_INS_BRAA, + ARM64_INS_BRAAZ, + ARM64_INS_BRAB, + ARM64_INS_BRABZ, + ARM64_INS_BRK, + ARM64_INS_BRKA, + ARM64_INS_BRKAS, + ARM64_INS_BRKB, + ARM64_INS_BRKBS, + ARM64_INS_BRKN, + ARM64_INS_BRKNS, + ARM64_INS_BRKPA, + ARM64_INS_BRKPAS, + ARM64_INS_BRKPB, + ARM64_INS_BRKPBS, + ARM64_INS_BSL, + ARM64_INS_CAS, + ARM64_INS_CASA, + ARM64_INS_CASAB, + ARM64_INS_CASAH, + ARM64_INS_CASAL, + ARM64_INS_CASALB, + ARM64_INS_CASALH, + ARM64_INS_CASB, + ARM64_INS_CASH, + ARM64_INS_CASL, + ARM64_INS_CASLB, + ARM64_INS_CASLH, + ARM64_INS_CASP, + ARM64_INS_CASPA, + ARM64_INS_CASPAL, + ARM64_INS_CASPL, + ARM64_INS_CBNZ, + ARM64_INS_CBZ, + ARM64_INS_CCMN, + ARM64_INS_CCMP, + ARM64_INS_CFINV, + ARM64_INS_CINC, + ARM64_INS_CINV, + ARM64_INS_CLASTA, + ARM64_INS_CLASTB, + ARM64_INS_CLREX, + ARM64_INS_CLS, + ARM64_INS_CLZ, + ARM64_INS_CMEQ, + ARM64_INS_CMGE, + ARM64_INS_CMGT, + ARM64_INS_CMHI, + ARM64_INS_CMHS, + ARM64_INS_CMLE, + ARM64_INS_CMLO, + ARM64_INS_CMLS, + ARM64_INS_CMLT, + ARM64_INS_CMN, + ARM64_INS_CMP, + ARM64_INS_CMPEQ, + ARM64_INS_CMPGE, + ARM64_INS_CMPGT, + ARM64_INS_CMPHI, + ARM64_INS_CMPHS, + ARM64_INS_CMPLE, + ARM64_INS_CMPLO, + ARM64_INS_CMPLS, + ARM64_INS_CMPLT, + ARM64_INS_CMPNE, + ARM64_INS_CMTST, + ARM64_INS_CNEG, + ARM64_INS_CNOT, + ARM64_INS_CNT, + ARM64_INS_CNTB, + ARM64_INS_CNTD, + ARM64_INS_CNTH, + ARM64_INS_CNTP, + ARM64_INS_CNTW, + ARM64_INS_COMPACT, + ARM64_INS_CPY, + ARM64_INS_CRC32B, + ARM64_INS_CRC32CB, + ARM64_INS_CRC32CH, + ARM64_INS_CRC32CW, + ARM64_INS_CRC32CX, + ARM64_INS_CRC32H, + ARM64_INS_CRC32W, + ARM64_INS_CRC32X, + ARM64_INS_CSDB, + ARM64_INS_CSEL, + ARM64_INS_CSET, + ARM64_INS_CSETM, + ARM64_INS_CSINC, + ARM64_INS_CSINV, + ARM64_INS_CSNEG, + ARM64_INS_CTERMEQ, + ARM64_INS_CTERMNE, + ARM64_INS_DCPS1, + ARM64_INS_DCPS2, + ARM64_INS_DCPS3, + ARM64_INS_DECB, + ARM64_INS_DECD, + ARM64_INS_DECH, + ARM64_INS_DECP, + ARM64_INS_DECW, + ARM64_INS_DMB, + ARM64_INS_DRPS, + ARM64_INS_DSB, + ARM64_INS_DUP, + ARM64_INS_DUPM, + ARM64_INS_EON, + ARM64_INS_EOR, + ARM64_INS_EOR3, + ARM64_INS_EORS, + ARM64_INS_EORV, + ARM64_INS_ERET, + ARM64_INS_ERETAA, + ARM64_INS_ERETAB, + ARM64_INS_ESB, + ARM64_INS_EXT, + ARM64_INS_EXTR, + ARM64_INS_FABD, + ARM64_INS_FABS, + ARM64_INS_FACGE, + ARM64_INS_FACGT, + ARM64_INS_FACLE, + ARM64_INS_FACLT, + ARM64_INS_FADD, + ARM64_INS_FADDA, + ARM64_INS_FADDP, + ARM64_INS_FADDV, + ARM64_INS_FCADD, + ARM64_INS_FCCMP, + ARM64_INS_FCCMPE, + ARM64_INS_FCMEQ, + ARM64_INS_FCMGE, + ARM64_INS_FCMGT, + ARM64_INS_FCMLA, + ARM64_INS_FCMLE, + ARM64_INS_FCMLT, + ARM64_INS_FCMNE, + ARM64_INS_FCMP, + ARM64_INS_FCMPE, + ARM64_INS_FCMUO, + ARM64_INS_FCPY, + ARM64_INS_FCSEL, + ARM64_INS_FCVT, + ARM64_INS_FCVTAS, + ARM64_INS_FCVTAU, + ARM64_INS_FCVTL, + ARM64_INS_FCVTL2, + ARM64_INS_FCVTMS, + ARM64_INS_FCVTMU, + ARM64_INS_FCVTN, + ARM64_INS_FCVTN2, + ARM64_INS_FCVTNS, + ARM64_INS_FCVTNU, + ARM64_INS_FCVTPS, + ARM64_INS_FCVTPU, + ARM64_INS_FCVTXN, + ARM64_INS_FCVTXN2, + ARM64_INS_FCVTZS, + ARM64_INS_FCVTZU, + ARM64_INS_FDIV, + ARM64_INS_FDIVR, + ARM64_INS_FDUP, + ARM64_INS_FEXPA, + ARM64_INS_FJCVTZS, + ARM64_INS_FMAD, + ARM64_INS_FMADD, + ARM64_INS_FMAX, + ARM64_INS_FMAXNM, + ARM64_INS_FMAXNMP, + ARM64_INS_FMAXNMV, + ARM64_INS_FMAXP, + ARM64_INS_FMAXV, + ARM64_INS_FMIN, + ARM64_INS_FMINNM, + ARM64_INS_FMINNMP, + ARM64_INS_FMINNMV, + ARM64_INS_FMINP, + ARM64_INS_FMINV, + ARM64_INS_FMLA, + ARM64_INS_FMLS, + ARM64_INS_FMOV, + ARM64_INS_FMSB, + ARM64_INS_FMSUB, + ARM64_INS_FMUL, + ARM64_INS_FMULX, + ARM64_INS_FNEG, + ARM64_INS_FNMAD, + ARM64_INS_FNMADD, + ARM64_INS_FNMLA, + ARM64_INS_FNMLS, + ARM64_INS_FNMSB, + ARM64_INS_FNMSUB, + ARM64_INS_FNMUL, + ARM64_INS_FRECPE, + ARM64_INS_FRECPS, + ARM64_INS_FRECPX, + ARM64_INS_FRINTA, + ARM64_INS_FRINTI, + ARM64_INS_FRINTM, + ARM64_INS_FRINTN, + ARM64_INS_FRINTP, + ARM64_INS_FRINTX, + ARM64_INS_FRINTZ, + ARM64_INS_FRSQRTE, + ARM64_INS_FRSQRTS, + ARM64_INS_FSCALE, + ARM64_INS_FSQRT, + ARM64_INS_FSUB, + ARM64_INS_FSUBR, + ARM64_INS_FTMAD, + ARM64_INS_FTSMUL, + ARM64_INS_FTSSEL, + ARM64_INS_HINT, + ARM64_INS_HLT, + ARM64_INS_HVC, + ARM64_INS_INCB, + ARM64_INS_INCD, + ARM64_INS_INCH, + ARM64_INS_INCP, + ARM64_INS_INCW, + ARM64_INS_INDEX, + ARM64_INS_INS, + ARM64_INS_INSR, + ARM64_INS_ISB, + ARM64_INS_LASTA, + ARM64_INS_LASTB, + ARM64_INS_LD1, + ARM64_INS_LD1B, + ARM64_INS_LD1D, + ARM64_INS_LD1H, + ARM64_INS_LD1R, + ARM64_INS_LD1RB, + ARM64_INS_LD1RD, + ARM64_INS_LD1RH, + ARM64_INS_LD1RQB, + ARM64_INS_LD1RQD, + ARM64_INS_LD1RQH, + ARM64_INS_LD1RQW, + ARM64_INS_LD1RSB, + ARM64_INS_LD1RSH, + ARM64_INS_LD1RSW, + ARM64_INS_LD1RW, + ARM64_INS_LD1SB, + ARM64_INS_LD1SH, + ARM64_INS_LD1SW, + ARM64_INS_LD1W, + ARM64_INS_LD2, + ARM64_INS_LD2B, + ARM64_INS_LD2D, + ARM64_INS_LD2H, + ARM64_INS_LD2R, + ARM64_INS_LD2W, + ARM64_INS_LD3, + ARM64_INS_LD3B, + ARM64_INS_LD3D, + ARM64_INS_LD3H, + ARM64_INS_LD3R, + ARM64_INS_LD3W, + ARM64_INS_LD4, + ARM64_INS_LD4B, + ARM64_INS_LD4D, + ARM64_INS_LD4H, + ARM64_INS_LD4R, + ARM64_INS_LD4W, + ARM64_INS_LDADD, + ARM64_INS_LDADDA, + ARM64_INS_LDADDAB, + ARM64_INS_LDADDAH, + ARM64_INS_LDADDAL, + ARM64_INS_LDADDALB, + ARM64_INS_LDADDALH, + ARM64_INS_LDADDB, + ARM64_INS_LDADDH, + ARM64_INS_LDADDL, + ARM64_INS_LDADDLB, + ARM64_INS_LDADDLH, + ARM64_INS_LDAPR, + ARM64_INS_LDAPRB, + ARM64_INS_LDAPRH, + ARM64_INS_LDAPUR, + ARM64_INS_LDAPURB, + ARM64_INS_LDAPURH, + ARM64_INS_LDAPURSB, + ARM64_INS_LDAPURSH, + ARM64_INS_LDAPURSW, + ARM64_INS_LDAR, + ARM64_INS_LDARB, + ARM64_INS_LDARH, + ARM64_INS_LDAXP, + ARM64_INS_LDAXR, + ARM64_INS_LDAXRB, + ARM64_INS_LDAXRH, + ARM64_INS_LDCLR, + ARM64_INS_LDCLRA, + ARM64_INS_LDCLRAB, + ARM64_INS_LDCLRAH, + ARM64_INS_LDCLRAL, + ARM64_INS_LDCLRALB, + ARM64_INS_LDCLRALH, + ARM64_INS_LDCLRB, + ARM64_INS_LDCLRH, + ARM64_INS_LDCLRL, + ARM64_INS_LDCLRLB, + ARM64_INS_LDCLRLH, + ARM64_INS_LDEOR, + ARM64_INS_LDEORA, + ARM64_INS_LDEORAB, + ARM64_INS_LDEORAH, + ARM64_INS_LDEORAL, + ARM64_INS_LDEORALB, + ARM64_INS_LDEORALH, + ARM64_INS_LDEORB, + ARM64_INS_LDEORH, + ARM64_INS_LDEORL, + ARM64_INS_LDEORLB, + ARM64_INS_LDEORLH, + ARM64_INS_LDFF1B, + ARM64_INS_LDFF1D, + ARM64_INS_LDFF1H, + ARM64_INS_LDFF1SB, + ARM64_INS_LDFF1SH, + ARM64_INS_LDFF1SW, + ARM64_INS_LDFF1W, + ARM64_INS_LDLAR, + ARM64_INS_LDLARB, + ARM64_INS_LDLARH, + ARM64_INS_LDNF1B, + ARM64_INS_LDNF1D, + ARM64_INS_LDNF1H, + ARM64_INS_LDNF1SB, + ARM64_INS_LDNF1SH, + ARM64_INS_LDNF1SW, + ARM64_INS_LDNF1W, + ARM64_INS_LDNP, + ARM64_INS_LDNT1B, + ARM64_INS_LDNT1D, + ARM64_INS_LDNT1H, + ARM64_INS_LDNT1W, + ARM64_INS_LDP, + ARM64_INS_LDPSW, + ARM64_INS_LDR, + ARM64_INS_LDRAA, + ARM64_INS_LDRAB, + ARM64_INS_LDRB, + ARM64_INS_LDRH, + ARM64_INS_LDRSB, + ARM64_INS_LDRSH, + ARM64_INS_LDRSW, + ARM64_INS_LDSET, + ARM64_INS_LDSETA, + ARM64_INS_LDSETAB, + ARM64_INS_LDSETAH, + ARM64_INS_LDSETAL, + ARM64_INS_LDSETALB, + ARM64_INS_LDSETALH, + ARM64_INS_LDSETB, + ARM64_INS_LDSETH, + ARM64_INS_LDSETL, + ARM64_INS_LDSETLB, + ARM64_INS_LDSETLH, + ARM64_INS_LDSMAX, + ARM64_INS_LDSMAXA, + ARM64_INS_LDSMAXAB, + ARM64_INS_LDSMAXAH, + ARM64_INS_LDSMAXAL, + ARM64_INS_LDSMAXALB, + ARM64_INS_LDSMAXALH, + ARM64_INS_LDSMAXB, + ARM64_INS_LDSMAXH, + ARM64_INS_LDSMAXL, + ARM64_INS_LDSMAXLB, + ARM64_INS_LDSMAXLH, + ARM64_INS_LDSMIN, + ARM64_INS_LDSMINA, + ARM64_INS_LDSMINAB, + ARM64_INS_LDSMINAH, + ARM64_INS_LDSMINAL, + ARM64_INS_LDSMINALB, + ARM64_INS_LDSMINALH, + ARM64_INS_LDSMINB, + ARM64_INS_LDSMINH, + ARM64_INS_LDSMINL, + ARM64_INS_LDSMINLB, + ARM64_INS_LDSMINLH, + ARM64_INS_LDTR, + ARM64_INS_LDTRB, + ARM64_INS_LDTRH, + ARM64_INS_LDTRSB, + ARM64_INS_LDTRSH, + ARM64_INS_LDTRSW, + ARM64_INS_LDUMAX, + ARM64_INS_LDUMAXA, + ARM64_INS_LDUMAXAB, + ARM64_INS_LDUMAXAH, + ARM64_INS_LDUMAXAL, + ARM64_INS_LDUMAXALB, + ARM64_INS_LDUMAXALH, + ARM64_INS_LDUMAXB, + ARM64_INS_LDUMAXH, + ARM64_INS_LDUMAXL, + ARM64_INS_LDUMAXLB, + ARM64_INS_LDUMAXLH, + ARM64_INS_LDUMIN, + ARM64_INS_LDUMINA, + ARM64_INS_LDUMINAB, + ARM64_INS_LDUMINAH, + ARM64_INS_LDUMINAL, + ARM64_INS_LDUMINALB, + ARM64_INS_LDUMINALH, + ARM64_INS_LDUMINB, + ARM64_INS_LDUMINH, + ARM64_INS_LDUMINL, + ARM64_INS_LDUMINLB, + ARM64_INS_LDUMINLH, + ARM64_INS_LDUR, + ARM64_INS_LDURB, + ARM64_INS_LDURH, + ARM64_INS_LDURSB, + ARM64_INS_LDURSH, + ARM64_INS_LDURSW, + ARM64_INS_LDXP, + ARM64_INS_LDXR, + ARM64_INS_LDXRB, + ARM64_INS_LDXRH, + ARM64_INS_LSL, + ARM64_INS_LSLR, + ARM64_INS_LSLV, + ARM64_INS_LSR, + ARM64_INS_LSRR, + ARM64_INS_LSRV, + ARM64_INS_MAD, + ARM64_INS_MADD, + ARM64_INS_MLA, + ARM64_INS_MLS, + ARM64_INS_MNEG, + ARM64_INS_MOV, + ARM64_INS_MOVI, + ARM64_INS_MOVK, + ARM64_INS_MOVN, + ARM64_INS_MOVPRFX, + ARM64_INS_MOVS, + ARM64_INS_MOVZ, + ARM64_INS_MRS, + ARM64_INS_MSB, + ARM64_INS_MSR, + ARM64_INS_MSUB, + ARM64_INS_MUL, + ARM64_INS_MVN, + ARM64_INS_MVNI, + ARM64_INS_NAND, + ARM64_INS_NANDS, + ARM64_INS_NEG, + ARM64_INS_NEGS, + ARM64_INS_NGC, + ARM64_INS_NGCS, + ARM64_INS_NOP, + ARM64_INS_NOR, + ARM64_INS_NORS, + ARM64_INS_NOT, + ARM64_INS_NOTS, + ARM64_INS_ORN, + ARM64_INS_ORNS, + ARM64_INS_ORR, + ARM64_INS_ORRS, + ARM64_INS_ORV, + ARM64_INS_PACDA, + ARM64_INS_PACDB, + ARM64_INS_PACDZA, + ARM64_INS_PACDZB, + ARM64_INS_PACGA, + ARM64_INS_PACIA, + ARM64_INS_PACIA1716, + ARM64_INS_PACIASP, + ARM64_INS_PACIAZ, + ARM64_INS_PACIB, + ARM64_INS_PACIB1716, + ARM64_INS_PACIBSP, + ARM64_INS_PACIBZ, + ARM64_INS_PACIZA, + ARM64_INS_PACIZB, + ARM64_INS_PFALSE, + ARM64_INS_PFIRST, + ARM64_INS_PMUL, + ARM64_INS_PMULL, + ARM64_INS_PMULL2, + ARM64_INS_PNEXT, + ARM64_INS_PRFB, + ARM64_INS_PRFD, + ARM64_INS_PRFH, + ARM64_INS_PRFM, + ARM64_INS_PRFUM, + ARM64_INS_PRFW, + ARM64_INS_PSB, + ARM64_INS_PTEST, + ARM64_INS_PTRUE, + ARM64_INS_PTRUES, + ARM64_INS_PUNPKHI, + ARM64_INS_PUNPKLO, + ARM64_INS_RADDHN, + ARM64_INS_RADDHN2, + ARM64_INS_RAX1, + ARM64_INS_RBIT, + ARM64_INS_RDFFR, + ARM64_INS_RDFFRS, + ARM64_INS_RDVL, + ARM64_INS_RET, + ARM64_INS_RETAA, + ARM64_INS_RETAB, + ARM64_INS_REV, + ARM64_INS_REV16, + ARM64_INS_REV32, + ARM64_INS_REV64, + ARM64_INS_REVB, + ARM64_INS_REVH, + ARM64_INS_REVW, + ARM64_INS_RMIF, + ARM64_INS_ROR, + ARM64_INS_RORV, + ARM64_INS_RSHRN, + ARM64_INS_RSHRN2, + ARM64_INS_RSUBHN, + ARM64_INS_RSUBHN2, + ARM64_INS_SABA, + ARM64_INS_SABAL, + ARM64_INS_SABAL2, + ARM64_INS_SABD, + ARM64_INS_SABDL, + ARM64_INS_SABDL2, + ARM64_INS_SADALP, + ARM64_INS_SADDL, + ARM64_INS_SADDL2, + ARM64_INS_SADDLP, + ARM64_INS_SADDLV, + ARM64_INS_SADDV, + ARM64_INS_SADDW, + ARM64_INS_SADDW2, + ARM64_INS_SBC, + ARM64_INS_SBCS, + ARM64_INS_SBFM, + ARM64_INS_SCVTF, + ARM64_INS_SDIV, + ARM64_INS_SDIVR, + ARM64_INS_SDOT, + ARM64_INS_SEL, + ARM64_INS_SETF16, + ARM64_INS_SETF8, + ARM64_INS_SETFFR, + ARM64_INS_SEV, + ARM64_INS_SEVL, + ARM64_INS_SHA1C, + ARM64_INS_SHA1H, + ARM64_INS_SHA1M, + ARM64_INS_SHA1P, + ARM64_INS_SHA1SU0, + ARM64_INS_SHA1SU1, + ARM64_INS_SHA256H, + ARM64_INS_SHA256H2, + ARM64_INS_SHA256SU0, + ARM64_INS_SHA256SU1, + ARM64_INS_SHA512H, + ARM64_INS_SHA512H2, + ARM64_INS_SHA512SU0, + ARM64_INS_SHA512SU1, + ARM64_INS_SHADD, + ARM64_INS_SHL, + ARM64_INS_SHLL, + ARM64_INS_SHLL2, + ARM64_INS_SHRN, + ARM64_INS_SHRN2, + ARM64_INS_SHSUB, + ARM64_INS_SLI, + ARM64_INS_SM3PARTW1, + ARM64_INS_SM3PARTW2, + ARM64_INS_SM3SS1, + ARM64_INS_SM3TT1A, + ARM64_INS_SM3TT1B, + ARM64_INS_SM3TT2A, + ARM64_INS_SM3TT2B, + ARM64_INS_SM4E, + ARM64_INS_SM4EKEY, + ARM64_INS_SMADDL, + ARM64_INS_SMAX, + ARM64_INS_SMAXP, + ARM64_INS_SMAXV, + ARM64_INS_SMC, + ARM64_INS_SMIN, + ARM64_INS_SMINP, + ARM64_INS_SMINV, + ARM64_INS_SMLAL, + ARM64_INS_SMLAL2, + ARM64_INS_SMLSL, + ARM64_INS_SMLSL2, + ARM64_INS_SMNEGL, + ARM64_INS_SMOV, + ARM64_INS_SMSUBL, + ARM64_INS_SMULH, + ARM64_INS_SMULL, + ARM64_INS_SMULL2, + ARM64_INS_SPLICE, + ARM64_INS_SQABS, + ARM64_INS_SQADD, + ARM64_INS_SQDECB, + ARM64_INS_SQDECD, + ARM64_INS_SQDECH, + ARM64_INS_SQDECP, + ARM64_INS_SQDECW, + ARM64_INS_SQDMLAL, + ARM64_INS_SQDMLAL2, + ARM64_INS_SQDMLSL, + ARM64_INS_SQDMLSL2, + ARM64_INS_SQDMULH, + ARM64_INS_SQDMULL, + ARM64_INS_SQDMULL2, + ARM64_INS_SQINCB, + ARM64_INS_SQINCD, + ARM64_INS_SQINCH, + ARM64_INS_SQINCP, + ARM64_INS_SQINCW, + ARM64_INS_SQNEG, + ARM64_INS_SQRDMLAH, + ARM64_INS_SQRDMLSH, + ARM64_INS_SQRDMULH, + ARM64_INS_SQRSHL, + ARM64_INS_SQRSHRN, + ARM64_INS_SQRSHRN2, + ARM64_INS_SQRSHRUN, + ARM64_INS_SQRSHRUN2, + ARM64_INS_SQSHL, + ARM64_INS_SQSHLU, + ARM64_INS_SQSHRN, + ARM64_INS_SQSHRN2, + ARM64_INS_SQSHRUN, + ARM64_INS_SQSHRUN2, + ARM64_INS_SQSUB, + ARM64_INS_SQXTN, + ARM64_INS_SQXTN2, + ARM64_INS_SQXTUN, + ARM64_INS_SQXTUN2, + ARM64_INS_SRHADD, + ARM64_INS_SRI, + ARM64_INS_SRSHL, + ARM64_INS_SRSHR, + ARM64_INS_SRSRA, + ARM64_INS_SSHL, + ARM64_INS_SSHLL, + ARM64_INS_SSHLL2, + ARM64_INS_SSHR, + ARM64_INS_SSRA, + ARM64_INS_SSUBL, + ARM64_INS_SSUBL2, + ARM64_INS_SSUBW, + ARM64_INS_SSUBW2, + ARM64_INS_ST1, + ARM64_INS_ST1B, + ARM64_INS_ST1D, + ARM64_INS_ST1H, + ARM64_INS_ST1W, + ARM64_INS_ST2, + ARM64_INS_ST2B, + ARM64_INS_ST2D, + ARM64_INS_ST2H, + ARM64_INS_ST2W, + ARM64_INS_ST3, + ARM64_INS_ST3B, + ARM64_INS_ST3D, + ARM64_INS_ST3H, + ARM64_INS_ST3W, + ARM64_INS_ST4, + ARM64_INS_ST4B, + ARM64_INS_ST4D, + ARM64_INS_ST4H, + ARM64_INS_ST4W, + ARM64_INS_STADD, + ARM64_INS_STADDB, + ARM64_INS_STADDH, + ARM64_INS_STADDL, + ARM64_INS_STADDLB, + ARM64_INS_STADDLH, + ARM64_INS_STCLR, + ARM64_INS_STCLRB, + ARM64_INS_STCLRH, + ARM64_INS_STCLRL, + ARM64_INS_STCLRLB, + ARM64_INS_STCLRLH, + ARM64_INS_STEOR, + ARM64_INS_STEORB, + ARM64_INS_STEORH, + ARM64_INS_STEORL, + ARM64_INS_STEORLB, + ARM64_INS_STEORLH, + ARM64_INS_STLLR, + ARM64_INS_STLLRB, + ARM64_INS_STLLRH, + ARM64_INS_STLR, + ARM64_INS_STLRB, + ARM64_INS_STLRH, + ARM64_INS_STLUR, + ARM64_INS_STLURB, + ARM64_INS_STLURH, + ARM64_INS_STLXP, + ARM64_INS_STLXR, + ARM64_INS_STLXRB, + ARM64_INS_STLXRH, + ARM64_INS_STNP, + ARM64_INS_STNT1B, + ARM64_INS_STNT1D, + ARM64_INS_STNT1H, + ARM64_INS_STNT1W, + ARM64_INS_STP, + ARM64_INS_STR, + ARM64_INS_STRB, + ARM64_INS_STRH, + ARM64_INS_STSET, + ARM64_INS_STSETB, + ARM64_INS_STSETH, + ARM64_INS_STSETL, + ARM64_INS_STSETLB, + ARM64_INS_STSETLH, + ARM64_INS_STSMAX, + ARM64_INS_STSMAXB, + ARM64_INS_STSMAXH, + ARM64_INS_STSMAXL, + ARM64_INS_STSMAXLB, + ARM64_INS_STSMAXLH, + ARM64_INS_STSMIN, + ARM64_INS_STSMINB, + ARM64_INS_STSMINH, + ARM64_INS_STSMINL, + ARM64_INS_STSMINLB, + ARM64_INS_STSMINLH, + ARM64_INS_STTR, + ARM64_INS_STTRB, + ARM64_INS_STTRH, + ARM64_INS_STUMAX, + ARM64_INS_STUMAXB, + ARM64_INS_STUMAXH, + ARM64_INS_STUMAXL, + ARM64_INS_STUMAXLB, + ARM64_INS_STUMAXLH, + ARM64_INS_STUMIN, + ARM64_INS_STUMINB, + ARM64_INS_STUMINH, + ARM64_INS_STUMINL, + ARM64_INS_STUMINLB, + ARM64_INS_STUMINLH, + ARM64_INS_STUR, + ARM64_INS_STURB, + ARM64_INS_STURH, + ARM64_INS_STXP, + ARM64_INS_STXR, + ARM64_INS_STXRB, + ARM64_INS_STXRH, + ARM64_INS_SUB, + ARM64_INS_SUBHN, + ARM64_INS_SUBHN2, + ARM64_INS_SUBR, + ARM64_INS_SUBS, + ARM64_INS_SUNPKHI, + ARM64_INS_SUNPKLO, + ARM64_INS_SUQADD, + ARM64_INS_SVC, + ARM64_INS_SWP, + ARM64_INS_SWPA, + ARM64_INS_SWPAB, + ARM64_INS_SWPAH, + ARM64_INS_SWPAL, + ARM64_INS_SWPALB, + ARM64_INS_SWPALH, + ARM64_INS_SWPB, + ARM64_INS_SWPH, + ARM64_INS_SWPL, + ARM64_INS_SWPLB, + ARM64_INS_SWPLH, + ARM64_INS_SXTB, + ARM64_INS_SXTH, + ARM64_INS_SXTL, + ARM64_INS_SXTL2, + ARM64_INS_SXTW, + ARM64_INS_SYS, + ARM64_INS_SYSL, + ARM64_INS_TBL, + ARM64_INS_TBNZ, + ARM64_INS_TBX, + ARM64_INS_TBZ, + ARM64_INS_TRN1, + ARM64_INS_TRN2, + ARM64_INS_TSB, + ARM64_INS_TST, + ARM64_INS_UABA, + ARM64_INS_UABAL, + ARM64_INS_UABAL2, + ARM64_INS_UABD, + ARM64_INS_UABDL, + ARM64_INS_UABDL2, + ARM64_INS_UADALP, + ARM64_INS_UADDL, + ARM64_INS_UADDL2, + ARM64_INS_UADDLP, + ARM64_INS_UADDLV, + ARM64_INS_UADDV, + ARM64_INS_UADDW, + ARM64_INS_UADDW2, + ARM64_INS_UBFM, + ARM64_INS_UCVTF, + ARM64_INS_UDIV, + ARM64_INS_UDIVR, + ARM64_INS_UDOT, + ARM64_INS_UHADD, + ARM64_INS_UHSUB, + ARM64_INS_UMADDL, + ARM64_INS_UMAX, + ARM64_INS_UMAXP, + ARM64_INS_UMAXV, + ARM64_INS_UMIN, + ARM64_INS_UMINP, + ARM64_INS_UMINV, + ARM64_INS_UMLAL, + ARM64_INS_UMLAL2, + ARM64_INS_UMLSL, + ARM64_INS_UMLSL2, + ARM64_INS_UMNEGL, + ARM64_INS_UMOV, + ARM64_INS_UMSUBL, + ARM64_INS_UMULH, + ARM64_INS_UMULL, + ARM64_INS_UMULL2, + ARM64_INS_UQADD, + ARM64_INS_UQDECB, + ARM64_INS_UQDECD, + ARM64_INS_UQDECH, + ARM64_INS_UQDECP, + ARM64_INS_UQDECW, + ARM64_INS_UQINCB, + ARM64_INS_UQINCD, + ARM64_INS_UQINCH, + ARM64_INS_UQINCP, + ARM64_INS_UQINCW, + ARM64_INS_UQRSHL, + ARM64_INS_UQRSHRN, + ARM64_INS_UQRSHRN2, + ARM64_INS_UQSHL, + ARM64_INS_UQSHRN, + ARM64_INS_UQSHRN2, + ARM64_INS_UQSUB, + ARM64_INS_UQXTN, + ARM64_INS_UQXTN2, + ARM64_INS_URECPE, + ARM64_INS_URHADD, + ARM64_INS_URSHL, + ARM64_INS_URSHR, + ARM64_INS_URSQRTE, + ARM64_INS_URSRA, + ARM64_INS_USHL, + ARM64_INS_USHLL, + ARM64_INS_USHLL2, + ARM64_INS_USHR, + ARM64_INS_USQADD, + ARM64_INS_USRA, + ARM64_INS_USUBL, + ARM64_INS_USUBL2, + ARM64_INS_USUBW, + ARM64_INS_USUBW2, + ARM64_INS_UUNPKHI, + ARM64_INS_UUNPKLO, + ARM64_INS_UXTB, + ARM64_INS_UXTH, + ARM64_INS_UXTL, + ARM64_INS_UXTL2, + ARM64_INS_UXTW, + ARM64_INS_UZP1, + ARM64_INS_UZP2, + ARM64_INS_WFE, + ARM64_INS_WFI, + ARM64_INS_WHILELE, + ARM64_INS_WHILELO, + ARM64_INS_WHILELS, + ARM64_INS_WHILELT, + ARM64_INS_WRFFR, + ARM64_INS_XAR, + ARM64_INS_XPACD, + ARM64_INS_XPACI, + ARM64_INS_XPACLRI, + ARM64_INS_XTN, + ARM64_INS_XTN2, + ARM64_INS_YIELD, + ARM64_INS_ZIP1, + ARM64_INS_ZIP2, - // alias insn - ARM64_INS_SBFIZ, - ARM64_INS_UBFIZ, - ARM64_INS_SBFX, - ARM64_INS_UBFX, - ARM64_INS_BFI, - ARM64_INS_BFXIL, - ARM64_INS_IC, - ARM64_INS_DC, - ARM64_INS_AT, - ARM64_INS_TLBI, + // alias insn + ARM64_INS_SBFIZ, + ARM64_INS_UBFIZ, + ARM64_INS_SBFX, + ARM64_INS_UBFX, + ARM64_INS_BFI, + ARM64_INS_BFXIL, + ARM64_INS_IC, + ARM64_INS_DC, + ARM64_INS_AT, + ARM64_INS_TLBI, - ARM64_INS_ENDING, // <-- mark the end of the list of insn + ARM64_INS_ENDING, // <-- mark the end of the list of insn } arm64_insn; /// Group of ARM64 instructions typedef enum arm64_insn_group { - ARM64_GRP_INVALID = 0, ///< = CS_GRP_INVALID + ARM64_GRP_INVALID = 0, ///< = CS_GRP_INVALID - // Generic groups - // all jump instructions (conditional+direct+indirect jumps) - ARM64_GRP_JUMP, ///< = CS_GRP_JUMP - ARM64_GRP_CALL, - ARM64_GRP_RET, - ARM64_GRP_INT, - ARM64_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE - ARM64_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE - ARM64_GRP_PAC, + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + ARM64_GRP_JUMP, ///< = CS_GRP_JUMP + ARM64_GRP_CALL, + ARM64_GRP_RET, + ARM64_GRP_INT, + ARM64_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE + ARM64_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE + ARM64_GRP_PAC, - // Architecture-specific groups - ARM64_GRP_CRYPTO = 128, - ARM64_GRP_FPARMV8, - ARM64_GRP_NEON, - ARM64_GRP_CRC, - ARM64_GRP_AES, - ARM64_GRP_DOTPROD, - ARM64_GRP_FULLFP16, - ARM64_GRP_LSE, - ARM64_GRP_RCPC, - ARM64_GRP_RDM, - ARM64_GRP_SHA2, - ARM64_GRP_SHA3, - ARM64_GRP_SM4, - ARM64_GRP_SVE, - ARM64_GRP_V8_1A, - ARM64_GRP_V8_3A, - ARM64_GRP_V8_4A, + // Architecture-specific groups + ARM64_GRP_CRYPTO = 128, + ARM64_GRP_FPARMV8, + ARM64_GRP_NEON, + ARM64_GRP_CRC, + ARM64_GRP_AES, + ARM64_GRP_DOTPROD, + ARM64_GRP_FULLFP16, + ARM64_GRP_LSE, + ARM64_GRP_RCPC, + ARM64_GRP_RDM, + ARM64_GRP_SHA2, + ARM64_GRP_SHA3, + ARM64_GRP_SM4, + ARM64_GRP_SVE, + ARM64_GRP_V8_1A, + ARM64_GRP_V8_3A, + ARM64_GRP_V8_4A, - ARM64_GRP_ENDING, // <-- mark the end of the list of groups + ARM64_GRP_ENDING, // <-- mark the end of the list of groups } arm64_insn_group; #ifdef __cplusplus diff --git a/include/capstone/mips.h b/include/capstone/mips.h index 339445611c..f52f732ef5 100644 --- a/include/capstone/mips.h +++ b/include/capstone/mips.h @@ -15,938 +15,1099 @@ extern "C" { #undef mips #ifdef _MSC_VER -#pragma warning(disable:4201) +#pragma warning(disable : 4201) #endif /// Operand type for instruction's operands typedef enum mips_op_type { - MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). - MIPS_OP_REG, ///< = CS_OP_REG (Register operand). - MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand). - MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand). + MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). + MIPS_OP_REG, ///< = CS_OP_REG (Register operand). + MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand). + MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand). } mips_op_type; /// MIPS registers typedef enum mips_reg { - MIPS_REG_INVALID = 0, - // General purpose registers - MIPS_REG_PC, - - MIPS_REG_0, - MIPS_REG_1, - MIPS_REG_2, - MIPS_REG_3, - MIPS_REG_4, - MIPS_REG_5, - MIPS_REG_6, - MIPS_REG_7, - MIPS_REG_8, - MIPS_REG_9, - MIPS_REG_10, - MIPS_REG_11, - MIPS_REG_12, - MIPS_REG_13, - MIPS_REG_14, - MIPS_REG_15, - MIPS_REG_16, - MIPS_REG_17, - MIPS_REG_18, - MIPS_REG_19, - MIPS_REG_20, - MIPS_REG_21, - MIPS_REG_22, - MIPS_REG_23, - MIPS_REG_24, - MIPS_REG_25, - MIPS_REG_26, - MIPS_REG_27, - MIPS_REG_28, - MIPS_REG_29, - MIPS_REG_30, - MIPS_REG_31, - - // DSP registers - MIPS_REG_DSPCCOND, - MIPS_REG_DSPCARRY, - MIPS_REG_DSPEFI, - MIPS_REG_DSPOUTFLAG, - MIPS_REG_DSPOUTFLAG16_19, - MIPS_REG_DSPOUTFLAG20, - MIPS_REG_DSPOUTFLAG21, - MIPS_REG_DSPOUTFLAG22, - MIPS_REG_DSPOUTFLAG23, - MIPS_REG_DSPPOS, - MIPS_REG_DSPSCOUNT, - - // ACC registers - MIPS_REG_AC0, - MIPS_REG_AC1, - MIPS_REG_AC2, - MIPS_REG_AC3, - - // COP registers - MIPS_REG_CC0, - MIPS_REG_CC1, - MIPS_REG_CC2, - MIPS_REG_CC3, - MIPS_REG_CC4, - MIPS_REG_CC5, - MIPS_REG_CC6, - MIPS_REG_CC7, - - // FPU registers - MIPS_REG_F0, - MIPS_REG_F1, - MIPS_REG_F2, - MIPS_REG_F3, - MIPS_REG_F4, - MIPS_REG_F5, - MIPS_REG_F6, - MIPS_REG_F7, - MIPS_REG_F8, - MIPS_REG_F9, - MIPS_REG_F10, - MIPS_REG_F11, - MIPS_REG_F12, - MIPS_REG_F13, - MIPS_REG_F14, - MIPS_REG_F15, - MIPS_REG_F16, - MIPS_REG_F17, - MIPS_REG_F18, - MIPS_REG_F19, - MIPS_REG_F20, - MIPS_REG_F21, - MIPS_REG_F22, - MIPS_REG_F23, - MIPS_REG_F24, - MIPS_REG_F25, - MIPS_REG_F26, - MIPS_REG_F27, - MIPS_REG_F28, - MIPS_REG_F29, - MIPS_REG_F30, - MIPS_REG_F31, - - MIPS_REG_FCC0, - MIPS_REG_FCC1, - MIPS_REG_FCC2, - MIPS_REG_FCC3, - MIPS_REG_FCC4, - MIPS_REG_FCC5, - MIPS_REG_FCC6, - MIPS_REG_FCC7, - - // AFPR128 - MIPS_REG_W0, - MIPS_REG_W1, - MIPS_REG_W2, - MIPS_REG_W3, - MIPS_REG_W4, - MIPS_REG_W5, - MIPS_REG_W6, - MIPS_REG_W7, - MIPS_REG_W8, - MIPS_REG_W9, - MIPS_REG_W10, - MIPS_REG_W11, - MIPS_REG_W12, - MIPS_REG_W13, - MIPS_REG_W14, - MIPS_REG_W15, - MIPS_REG_W16, - MIPS_REG_W17, - MIPS_REG_W18, - MIPS_REG_W19, - MIPS_REG_W20, - MIPS_REG_W21, - MIPS_REG_W22, - MIPS_REG_W23, - MIPS_REG_W24, - MIPS_REG_W25, - MIPS_REG_W26, - MIPS_REG_W27, - MIPS_REG_W28, - MIPS_REG_W29, - MIPS_REG_W30, - MIPS_REG_W31, - - MIPS_REG_HI, - MIPS_REG_LO, - - MIPS_REG_P0, - MIPS_REG_P1, - MIPS_REG_P2, - - MIPS_REG_MPL0, - MIPS_REG_MPL1, - MIPS_REG_MPL2, - - MIPS_REG_ENDING, // <-- mark the end of the list or registers - - // alias registers - MIPS_REG_ZERO = MIPS_REG_0, - MIPS_REG_AT = MIPS_REG_1, - MIPS_REG_V0 = MIPS_REG_2, - MIPS_REG_V1 = MIPS_REG_3, - MIPS_REG_A0 = MIPS_REG_4, - MIPS_REG_A1 = MIPS_REG_5, - MIPS_REG_A2 = MIPS_REG_6, - MIPS_REG_A3 = MIPS_REG_7, - MIPS_REG_T0 = MIPS_REG_8, - MIPS_REG_T1 = MIPS_REG_9, - MIPS_REG_T2 = MIPS_REG_10, - MIPS_REG_T3 = MIPS_REG_11, - MIPS_REG_T4 = MIPS_REG_12, - MIPS_REG_T5 = MIPS_REG_13, - MIPS_REG_T6 = MIPS_REG_14, - MIPS_REG_T7 = MIPS_REG_15, - MIPS_REG_S0 = MIPS_REG_16, - MIPS_REG_S1 = MIPS_REG_17, - MIPS_REG_S2 = MIPS_REG_18, - MIPS_REG_S3 = MIPS_REG_19, - MIPS_REG_S4 = MIPS_REG_20, - MIPS_REG_S5 = MIPS_REG_21, - MIPS_REG_S6 = MIPS_REG_22, - MIPS_REG_S7 = MIPS_REG_23, - MIPS_REG_T8 = MIPS_REG_24, - MIPS_REG_T9 = MIPS_REG_25, - MIPS_REG_K0 = MIPS_REG_26, - MIPS_REG_K1 = MIPS_REG_27, - MIPS_REG_GP = MIPS_REG_28, - MIPS_REG_SP = MIPS_REG_29, - MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30, - MIPS_REG_RA = MIPS_REG_31, - - MIPS_REG_HI0 = MIPS_REG_AC0, - MIPS_REG_HI1 = MIPS_REG_AC1, - MIPS_REG_HI2 = MIPS_REG_AC2, - MIPS_REG_HI3 = MIPS_REG_AC3, - - MIPS_REG_LO0 = MIPS_REG_HI0, - MIPS_REG_LO1 = MIPS_REG_HI1, - MIPS_REG_LO2 = MIPS_REG_HI2, - MIPS_REG_LO3 = MIPS_REG_HI3, + MIPS_REG_INVALID = 0, + // General purpose registers + MIPS_REG_PC, + + MIPS_REG_0, + MIPS_REG_1, + MIPS_REG_2, + MIPS_REG_3, + MIPS_REG_4, + MIPS_REG_5, + MIPS_REG_6, + MIPS_REG_7, + MIPS_REG_8, + MIPS_REG_9, + MIPS_REG_10, + MIPS_REG_11, + MIPS_REG_12, + MIPS_REG_13, + MIPS_REG_14, + MIPS_REG_15, + MIPS_REG_16, + MIPS_REG_17, + MIPS_REG_18, + MIPS_REG_19, + MIPS_REG_20, + MIPS_REG_21, + MIPS_REG_22, + MIPS_REG_23, + MIPS_REG_24, + MIPS_REG_25, + MIPS_REG_26, + MIPS_REG_27, + MIPS_REG_28, + MIPS_REG_29, + MIPS_REG_30, + MIPS_REG_31, + + // DSP registers + MIPS_REG_DSPCCOND, + MIPS_REG_DSPCARRY, + MIPS_REG_DSPEFI, + MIPS_REG_DSPOUTFLAG, + MIPS_REG_DSPOUTFLAG16_19, + MIPS_REG_DSPOUTFLAG20, + MIPS_REG_DSPOUTFLAG21, + MIPS_REG_DSPOUTFLAG22, + MIPS_REG_DSPOUTFLAG23, + MIPS_REG_DSPPOS, + MIPS_REG_DSPSCOUNT, + + // ACC registers + MIPS_REG_AC0, + MIPS_REG_AC1, + MIPS_REG_AC2, + MIPS_REG_AC3, + + // COP registers + MIPS_REG_CC0, + MIPS_REG_CC1, + MIPS_REG_CC2, + MIPS_REG_CC3, + MIPS_REG_CC4, + MIPS_REG_CC5, + MIPS_REG_CC6, + MIPS_REG_CC7, + + // FPU registers + MIPS_REG_F0, + MIPS_REG_F1, + MIPS_REG_F2, + MIPS_REG_F3, + MIPS_REG_F4, + MIPS_REG_F5, + MIPS_REG_F6, + MIPS_REG_F7, + MIPS_REG_F8, + MIPS_REG_F9, + MIPS_REG_F10, + MIPS_REG_F11, + MIPS_REG_F12, + MIPS_REG_F13, + MIPS_REG_F14, + MIPS_REG_F15, + MIPS_REG_F16, + MIPS_REG_F17, + MIPS_REG_F18, + MIPS_REG_F19, + MIPS_REG_F20, + MIPS_REG_F21, + MIPS_REG_F22, + MIPS_REG_F23, + MIPS_REG_F24, + MIPS_REG_F25, + MIPS_REG_F26, + MIPS_REG_F27, + MIPS_REG_F28, + MIPS_REG_F29, + MIPS_REG_F30, + MIPS_REG_F31, + + MIPS_REG_FCC0, + MIPS_REG_FCC1, + MIPS_REG_FCC2, + MIPS_REG_FCC3, + MIPS_REG_FCC4, + MIPS_REG_FCC5, + MIPS_REG_FCC6, + MIPS_REG_FCC7, + + // AFPR128 + MIPS_REG_W0, + MIPS_REG_W1, + MIPS_REG_W2, + MIPS_REG_W3, + MIPS_REG_W4, + MIPS_REG_W5, + MIPS_REG_W6, + MIPS_REG_W7, + MIPS_REG_W8, + MIPS_REG_W9, + MIPS_REG_W10, + MIPS_REG_W11, + MIPS_REG_W12, + MIPS_REG_W13, + MIPS_REG_W14, + MIPS_REG_W15, + MIPS_REG_W16, + MIPS_REG_W17, + MIPS_REG_W18, + MIPS_REG_W19, + MIPS_REG_W20, + MIPS_REG_W21, + MIPS_REG_W22, + MIPS_REG_W23, + MIPS_REG_W24, + MIPS_REG_W25, + MIPS_REG_W26, + MIPS_REG_W27, + MIPS_REG_W28, + MIPS_REG_W29, + MIPS_REG_W30, + MIPS_REG_W31, + + MIPS_REG_HI, + MIPS_REG_LO, + + MIPS_REG_P0, + MIPS_REG_P1, + MIPS_REG_P2, + + MIPS_REG_MPL0, + MIPS_REG_MPL1, + MIPS_REG_MPL2, + + MIPS_REG_ENDING, // <-- mark the end of the list or registers + + // alias registers + MIPS_REG_ZERO = MIPS_REG_0, + MIPS_REG_AT = MIPS_REG_1, + MIPS_REG_V0 = MIPS_REG_2, + MIPS_REG_V1 = MIPS_REG_3, + MIPS_REG_A0 = MIPS_REG_4, + MIPS_REG_A1 = MIPS_REG_5, + MIPS_REG_A2 = MIPS_REG_6, + MIPS_REG_A3 = MIPS_REG_7, + MIPS_REG_T0 = MIPS_REG_8, + MIPS_REG_T1 = MIPS_REG_9, + MIPS_REG_T2 = MIPS_REG_10, + MIPS_REG_T3 = MIPS_REG_11, + MIPS_REG_T4 = MIPS_REG_12, + MIPS_REG_T5 = MIPS_REG_13, + MIPS_REG_T6 = MIPS_REG_14, + MIPS_REG_T7 = MIPS_REG_15, + MIPS_REG_S0 = MIPS_REG_16, + MIPS_REG_S1 = MIPS_REG_17, + MIPS_REG_S2 = MIPS_REG_18, + MIPS_REG_S3 = MIPS_REG_19, + MIPS_REG_S4 = MIPS_REG_20, + MIPS_REG_S5 = MIPS_REG_21, + MIPS_REG_S6 = MIPS_REG_22, + MIPS_REG_S7 = MIPS_REG_23, + MIPS_REG_T8 = MIPS_REG_24, + MIPS_REG_T9 = MIPS_REG_25, + MIPS_REG_K0 = MIPS_REG_26, + MIPS_REG_K1 = MIPS_REG_27, + MIPS_REG_GP = MIPS_REG_28, + MIPS_REG_SP = MIPS_REG_29, + MIPS_REG_FP = MIPS_REG_30, + MIPS_REG_S8 = MIPS_REG_30, + MIPS_REG_RA = MIPS_REG_31, + + MIPS_REG_HI0 = MIPS_REG_AC0, + MIPS_REG_HI1 = MIPS_REG_AC1, + MIPS_REG_HI2 = MIPS_REG_AC2, + MIPS_REG_HI3 = MIPS_REG_AC3, + + MIPS_REG_LO0 = MIPS_REG_HI0, + MIPS_REG_LO1 = MIPS_REG_HI1, + MIPS_REG_LO2 = MIPS_REG_HI2, + MIPS_REG_LO3 = MIPS_REG_HI3, } mips_reg; /// Instruction's operand referring to memory /// This is associated with MIPS_OP_MEM operand type above typedef struct mips_op_mem { - mips_reg base; ///< base register - int64_t disp; ///< displacement/offset value + mips_reg base; ///< base register + int64_t disp; ///< displacement/offset value } mips_op_mem; /// Instruction operand typedef struct cs_mips_op { - mips_op_type type; ///< operand type - union { - mips_reg reg; ///< register id for REG operand - int64_t imm; ///< immediate value for IMM operand - mips_op_mem mem; ///< base/index/scale/disp value for MEM operand - }; + mips_op_type type; ///< operand type + union { + mips_reg reg; ///< register id for REG operand + int64_t imm; ///< immediate value for IMM operand + mips_op_mem mem; ///< base/index/scale/disp value for MEM operand + }; } cs_mips_op; /// Instruction structure typedef struct cs_mips { - /// Number of operands of this instruction, - /// or 0 when instruction has no operand. - uint8_t op_count; - cs_mips_op operands[10]; ///< operands for this instruction. + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + cs_mips_op operands[10]; ///< operands for this instruction. } cs_mips; /// MIPS instruction typedef enum mips_insn { - MIPS_INS_INVALID = 0, - - MIPS_INS_ABSQ_S, - MIPS_INS_ADD, - MIPS_INS_ADDIUPC, - MIPS_INS_ADDIUR1SP, - MIPS_INS_ADDIUR2, - MIPS_INS_ADDIUS5, - MIPS_INS_ADDIUSP, - MIPS_INS_ADDQH, - MIPS_INS_ADDQH_R, - MIPS_INS_ADDQ, - MIPS_INS_ADDQ_S, - MIPS_INS_ADDSC, - MIPS_INS_ADDS_A, - MIPS_INS_ADDS_S, - MIPS_INS_ADDS_U, - MIPS_INS_ADDU16, - MIPS_INS_ADDUH, - MIPS_INS_ADDUH_R, - MIPS_INS_ADDU, - MIPS_INS_ADDU_S, - MIPS_INS_ADDVI, - MIPS_INS_ADDV, - MIPS_INS_ADDWC, - MIPS_INS_ADD_A, - MIPS_INS_ADDI, - MIPS_INS_ADDIU, - MIPS_INS_ALIGN, - MIPS_INS_ALUIPC, - MIPS_INS_AND, - MIPS_INS_AND16, - MIPS_INS_ANDI16, - MIPS_INS_ANDI, - MIPS_INS_APPEND, - MIPS_INS_ASUB_S, - MIPS_INS_ASUB_U, - MIPS_INS_AUI, - MIPS_INS_AUIPC, - MIPS_INS_AVER_S, - MIPS_INS_AVER_U, - MIPS_INS_AVE_S, - MIPS_INS_AVE_U, - MIPS_INS_B16, - MIPS_INS_BADDU, - MIPS_INS_BAL, - MIPS_INS_BALC, - MIPS_INS_BALIGN, - MIPS_INS_BBIT0, - MIPS_INS_BBIT032, - MIPS_INS_BBIT1, - MIPS_INS_BBIT132, - MIPS_INS_BC, - MIPS_INS_BC0F, - MIPS_INS_BC0FL, - MIPS_INS_BC0T, - MIPS_INS_BC0TL, - MIPS_INS_BC1EQZ, - MIPS_INS_BC1F, - MIPS_INS_BC1FL, - MIPS_INS_BC1NEZ, - MIPS_INS_BC1T, - MIPS_INS_BC1TL, - MIPS_INS_BC2EQZ, - MIPS_INS_BC2F, - MIPS_INS_BC2FL, - MIPS_INS_BC2NEZ, - MIPS_INS_BC2T, - MIPS_INS_BC2TL, - MIPS_INS_BC3F, - MIPS_INS_BC3FL, - MIPS_INS_BC3T, - MIPS_INS_BC3TL, - MIPS_INS_BCLRI, - MIPS_INS_BCLR, - MIPS_INS_BEQ, - MIPS_INS_BEQC, - MIPS_INS_BEQL, - MIPS_INS_BEQZ16, - MIPS_INS_BEQZALC, - MIPS_INS_BEQZC, - MIPS_INS_BGEC, - MIPS_INS_BGEUC, - MIPS_INS_BGEZ, - MIPS_INS_BGEZAL, - MIPS_INS_BGEZALC, - MIPS_INS_BGEZALL, - MIPS_INS_BGEZALS, - MIPS_INS_BGEZC, - MIPS_INS_BGEZL, - MIPS_INS_BGTZ, - MIPS_INS_BGTZALC, - MIPS_INS_BGTZC, - MIPS_INS_BGTZL, - MIPS_INS_BINSLI, - MIPS_INS_BINSL, - MIPS_INS_BINSRI, - MIPS_INS_BINSR, - MIPS_INS_BITREV, - MIPS_INS_BITSWAP, - MIPS_INS_BLEZ, - MIPS_INS_BLEZALC, - MIPS_INS_BLEZC, - MIPS_INS_BLEZL, - MIPS_INS_BLTC, - MIPS_INS_BLTUC, - MIPS_INS_BLTZ, - MIPS_INS_BLTZAL, - MIPS_INS_BLTZALC, - MIPS_INS_BLTZALL, - MIPS_INS_BLTZALS, - MIPS_INS_BLTZC, - MIPS_INS_BLTZL, - MIPS_INS_BMNZI, - MIPS_INS_BMNZ, - MIPS_INS_BMZI, - MIPS_INS_BMZ, - MIPS_INS_BNE, - MIPS_INS_BNEC, - MIPS_INS_BNEGI, - MIPS_INS_BNEG, - MIPS_INS_BNEL, - MIPS_INS_BNEZ16, - MIPS_INS_BNEZALC, - MIPS_INS_BNEZC, - MIPS_INS_BNVC, - MIPS_INS_BNZ, - MIPS_INS_BOVC, - MIPS_INS_BPOSGE32, - MIPS_INS_BREAK, - MIPS_INS_BREAK16, - MIPS_INS_BSELI, - MIPS_INS_BSEL, - MIPS_INS_BSETI, - MIPS_INS_BSET, - MIPS_INS_BZ, - MIPS_INS_BEQZ, - MIPS_INS_B, - MIPS_INS_BNEZ, - MIPS_INS_BTEQZ, - MIPS_INS_BTNEZ, - MIPS_INS_CACHE, - MIPS_INS_CEIL, - MIPS_INS_CEQI, - MIPS_INS_CEQ, - MIPS_INS_CFC1, - MIPS_INS_CFCMSA, - MIPS_INS_CINS, - MIPS_INS_CINS32, - MIPS_INS_CLASS, - MIPS_INS_CLEI_S, - MIPS_INS_CLEI_U, - MIPS_INS_CLE_S, - MIPS_INS_CLE_U, - MIPS_INS_CLO, - MIPS_INS_CLTI_S, - MIPS_INS_CLTI_U, - MIPS_INS_CLT_S, - MIPS_INS_CLT_U, - MIPS_INS_CLZ, - MIPS_INS_CMPGDU, - MIPS_INS_CMPGU, - MIPS_INS_CMPU, - MIPS_INS_CMP, - MIPS_INS_COPY_S, - MIPS_INS_COPY_U, - MIPS_INS_CTC1, - MIPS_INS_CTCMSA, - MIPS_INS_CVT, - MIPS_INS_C, - MIPS_INS_CMPI, - MIPS_INS_DADD, - MIPS_INS_DADDI, - MIPS_INS_DADDIU, - MIPS_INS_DADDU, - MIPS_INS_DAHI, - MIPS_INS_DALIGN, - MIPS_INS_DATI, - MIPS_INS_DAUI, - MIPS_INS_DBITSWAP, - MIPS_INS_DCLO, - MIPS_INS_DCLZ, - MIPS_INS_DDIV, - MIPS_INS_DDIVU, - MIPS_INS_DERET, - MIPS_INS_DEXT, - MIPS_INS_DEXTM, - MIPS_INS_DEXTU, - MIPS_INS_DI, - MIPS_INS_DINS, - MIPS_INS_DINSM, - MIPS_INS_DINSU, - MIPS_INS_DIV, - MIPS_INS_DIVU, - MIPS_INS_DIV_S, - MIPS_INS_DIV_U, - MIPS_INS_DLSA, - MIPS_INS_DMFC0, - MIPS_INS_DMFC1, - MIPS_INS_DMFC2, - MIPS_INS_DMOD, - MIPS_INS_DMODU, - MIPS_INS_DMTC0, - MIPS_INS_DMTC1, - MIPS_INS_DMTC2, - MIPS_INS_DMUH, - MIPS_INS_DMUHU, - MIPS_INS_DMUL, - MIPS_INS_DMULT, - MIPS_INS_DMULTU, - MIPS_INS_DMULU, - MIPS_INS_DOTP_S, - MIPS_INS_DOTP_U, - MIPS_INS_DPADD_S, - MIPS_INS_DPADD_U, - MIPS_INS_DPAQX_SA, - MIPS_INS_DPAQX_S, - MIPS_INS_DPAQ_SA, - MIPS_INS_DPAQ_S, - MIPS_INS_DPAU, - MIPS_INS_DPAX, - MIPS_INS_DPA, - MIPS_INS_DPOP, - MIPS_INS_DPSQX_SA, - MIPS_INS_DPSQX_S, - MIPS_INS_DPSQ_SA, - MIPS_INS_DPSQ_S, - MIPS_INS_DPSUB_S, - MIPS_INS_DPSUB_U, - MIPS_INS_DPSU, - MIPS_INS_DPSX, - MIPS_INS_DPS, - MIPS_INS_DROTR, - MIPS_INS_DROTR32, - MIPS_INS_DROTRV, - MIPS_INS_DSBH, - MIPS_INS_DSHD, - MIPS_INS_DSLL, - MIPS_INS_DSLL32, - MIPS_INS_DSLLV, - MIPS_INS_DSRA, - MIPS_INS_DSRA32, - MIPS_INS_DSRAV, - MIPS_INS_DSRL, - MIPS_INS_DSRL32, - MIPS_INS_DSRLV, - MIPS_INS_DSUB, - MIPS_INS_DSUBU, - MIPS_INS_EHB, - MIPS_INS_EI, - MIPS_INS_ERET, - MIPS_INS_EXT, - MIPS_INS_EXTP, - MIPS_INS_EXTPDP, - MIPS_INS_EXTPDPV, - MIPS_INS_EXTPV, - MIPS_INS_EXTRV_RS, - MIPS_INS_EXTRV_R, - MIPS_INS_EXTRV_S, - MIPS_INS_EXTRV, - MIPS_INS_EXTR_RS, - MIPS_INS_EXTR_R, - MIPS_INS_EXTR_S, - MIPS_INS_EXTR, - MIPS_INS_EXTS, - MIPS_INS_EXTS32, - MIPS_INS_ABS, - MIPS_INS_FADD, - MIPS_INS_FCAF, - MIPS_INS_FCEQ, - MIPS_INS_FCLASS, - MIPS_INS_FCLE, - MIPS_INS_FCLT, - MIPS_INS_FCNE, - MIPS_INS_FCOR, - MIPS_INS_FCUEQ, - MIPS_INS_FCULE, - MIPS_INS_FCULT, - MIPS_INS_FCUNE, - MIPS_INS_FCUN, - MIPS_INS_FDIV, - MIPS_INS_FEXDO, - MIPS_INS_FEXP2, - MIPS_INS_FEXUPL, - MIPS_INS_FEXUPR, - MIPS_INS_FFINT_S, - MIPS_INS_FFINT_U, - MIPS_INS_FFQL, - MIPS_INS_FFQR, - MIPS_INS_FILL, - MIPS_INS_FLOG2, - MIPS_INS_FLOOR, - MIPS_INS_FMADD, - MIPS_INS_FMAX_A, - MIPS_INS_FMAX, - MIPS_INS_FMIN_A, - MIPS_INS_FMIN, - MIPS_INS_MOV, - MIPS_INS_FMSUB, - MIPS_INS_FMUL, - MIPS_INS_MUL, - MIPS_INS_NEG, - MIPS_INS_FRCP, - MIPS_INS_FRINT, - MIPS_INS_FRSQRT, - MIPS_INS_FSAF, - MIPS_INS_FSEQ, - MIPS_INS_FSLE, - MIPS_INS_FSLT, - MIPS_INS_FSNE, - MIPS_INS_FSOR, - MIPS_INS_FSQRT, - MIPS_INS_SQRT, - MIPS_INS_FSUB, - MIPS_INS_SUB, - MIPS_INS_FSUEQ, - MIPS_INS_FSULE, - MIPS_INS_FSULT, - MIPS_INS_FSUNE, - MIPS_INS_FSUN, - MIPS_INS_FTINT_S, - MIPS_INS_FTINT_U, - MIPS_INS_FTQ, - MIPS_INS_FTRUNC_S, - MIPS_INS_FTRUNC_U, - MIPS_INS_HADD_S, - MIPS_INS_HADD_U, - MIPS_INS_HSUB_S, - MIPS_INS_HSUB_U, - MIPS_INS_ILVEV, - MIPS_INS_ILVL, - MIPS_INS_ILVOD, - MIPS_INS_ILVR, - MIPS_INS_INS, - MIPS_INS_INSERT, - MIPS_INS_INSV, - MIPS_INS_INSVE, - MIPS_INS_J, - MIPS_INS_JAL, - MIPS_INS_JALR, - MIPS_INS_JALRS16, - MIPS_INS_JALRS, - MIPS_INS_JALS, - MIPS_INS_JALX, - MIPS_INS_JIALC, - MIPS_INS_JIC, - MIPS_INS_JR, - MIPS_INS_JR16, - MIPS_INS_JRADDIUSP, - MIPS_INS_JRC, - MIPS_INS_JALRC, - MIPS_INS_LB, - MIPS_INS_LBU16, - MIPS_INS_LBUX, - MIPS_INS_LBU, - MIPS_INS_LD, - MIPS_INS_LDC1, - MIPS_INS_LDC2, - MIPS_INS_LDC3, - MIPS_INS_LDI, - MIPS_INS_LDL, - MIPS_INS_LDPC, - MIPS_INS_LDR, - MIPS_INS_LDXC1, - MIPS_INS_LH, - MIPS_INS_LHU16, - MIPS_INS_LHX, - MIPS_INS_LHU, - MIPS_INS_LI16, - MIPS_INS_LL, - MIPS_INS_LLD, - MIPS_INS_LSA, - MIPS_INS_LUXC1, - MIPS_INS_LUI, - MIPS_INS_LW, - MIPS_INS_LW16, - MIPS_INS_LWC1, - MIPS_INS_LWC2, - MIPS_INS_LWC3, - MIPS_INS_LWL, - MIPS_INS_LWM16, - MIPS_INS_LWM32, - MIPS_INS_LWPC, - MIPS_INS_LWP, - MIPS_INS_LWR, - MIPS_INS_LWUPC, - MIPS_INS_LWU, - MIPS_INS_LWX, - MIPS_INS_LWXC1, - MIPS_INS_LWXS, - MIPS_INS_LI, - MIPS_INS_MADD, - MIPS_INS_MADDF, - MIPS_INS_MADDR_Q, - MIPS_INS_MADDU, - MIPS_INS_MADDV, - MIPS_INS_MADD_Q, - MIPS_INS_MAQ_SA, - MIPS_INS_MAQ_S, - MIPS_INS_MAXA, - MIPS_INS_MAXI_S, - MIPS_INS_MAXI_U, - MIPS_INS_MAX_A, - MIPS_INS_MAX, - MIPS_INS_MAX_S, - MIPS_INS_MAX_U, - MIPS_INS_MFC0, - MIPS_INS_MFC1, - MIPS_INS_MFC2, - MIPS_INS_MFHC1, - MIPS_INS_MFHI, - MIPS_INS_MFLO, - MIPS_INS_MINA, - MIPS_INS_MINI_S, - MIPS_INS_MINI_U, - MIPS_INS_MIN_A, - MIPS_INS_MIN, - MIPS_INS_MIN_S, - MIPS_INS_MIN_U, - MIPS_INS_MOD, - MIPS_INS_MODSUB, - MIPS_INS_MODU, - MIPS_INS_MOD_S, - MIPS_INS_MOD_U, - MIPS_INS_MOVE, - MIPS_INS_MOVEP, - MIPS_INS_MOVF, - MIPS_INS_MOVN, - MIPS_INS_MOVT, - MIPS_INS_MOVZ, - MIPS_INS_MSUB, - MIPS_INS_MSUBF, - MIPS_INS_MSUBR_Q, - MIPS_INS_MSUBU, - MIPS_INS_MSUBV, - MIPS_INS_MSUB_Q, - MIPS_INS_MTC0, - MIPS_INS_MTC1, - MIPS_INS_MTC2, - MIPS_INS_MTHC1, - MIPS_INS_MTHI, - MIPS_INS_MTHLIP, - MIPS_INS_MTLO, - MIPS_INS_MTM0, - MIPS_INS_MTM1, - MIPS_INS_MTM2, - MIPS_INS_MTP0, - MIPS_INS_MTP1, - MIPS_INS_MTP2, - MIPS_INS_MUH, - MIPS_INS_MUHU, - MIPS_INS_MULEQ_S, - MIPS_INS_MULEU_S, - MIPS_INS_MULQ_RS, - MIPS_INS_MULQ_S, - MIPS_INS_MULR_Q, - MIPS_INS_MULSAQ_S, - MIPS_INS_MULSA, - MIPS_INS_MULT, - MIPS_INS_MULTU, - MIPS_INS_MULU, - MIPS_INS_MULV, - MIPS_INS_MUL_Q, - MIPS_INS_MUL_S, - MIPS_INS_NLOC, - MIPS_INS_NLZC, - MIPS_INS_NMADD, - MIPS_INS_NMSUB, - MIPS_INS_NOR, - MIPS_INS_NORI, - MIPS_INS_NOT16, - MIPS_INS_NOT, - MIPS_INS_OR, - MIPS_INS_OR16, - MIPS_INS_ORI, - MIPS_INS_PACKRL, - MIPS_INS_PAUSE, - MIPS_INS_PCKEV, - MIPS_INS_PCKOD, - MIPS_INS_PCNT, - MIPS_INS_PICK, - MIPS_INS_POP, - MIPS_INS_PRECEQU, - MIPS_INS_PRECEQ, - MIPS_INS_PRECEU, - MIPS_INS_PRECRQU_S, - MIPS_INS_PRECRQ, - MIPS_INS_PRECRQ_RS, - MIPS_INS_PRECR, - MIPS_INS_PRECR_SRA, - MIPS_INS_PRECR_SRA_R, - MIPS_INS_PREF, - MIPS_INS_PREPEND, - MIPS_INS_RADDU, - MIPS_INS_RDDSP, - MIPS_INS_RDHWR, - MIPS_INS_REPLV, - MIPS_INS_REPL, - MIPS_INS_RINT, - MIPS_INS_ROTR, - MIPS_INS_ROTRV, - MIPS_INS_ROUND, - MIPS_INS_SAT_S, - MIPS_INS_SAT_U, - MIPS_INS_SB, - MIPS_INS_SB16, - MIPS_INS_SC, - MIPS_INS_SCD, - MIPS_INS_SD, - MIPS_INS_SDBBP, - MIPS_INS_SDBBP16, - MIPS_INS_SDC1, - MIPS_INS_SDC2, - MIPS_INS_SDC3, - MIPS_INS_SDL, - MIPS_INS_SDR, - MIPS_INS_SDXC1, - MIPS_INS_SEB, - MIPS_INS_SEH, - MIPS_INS_SELEQZ, - MIPS_INS_SELNEZ, - MIPS_INS_SEL, - MIPS_INS_SEQ, - MIPS_INS_SEQI, - MIPS_INS_SH, - MIPS_INS_SH16, - MIPS_INS_SHF, - MIPS_INS_SHILO, - MIPS_INS_SHILOV, - MIPS_INS_SHLLV, - MIPS_INS_SHLLV_S, - MIPS_INS_SHLL, - MIPS_INS_SHLL_S, - MIPS_INS_SHRAV, - MIPS_INS_SHRAV_R, - MIPS_INS_SHRA, - MIPS_INS_SHRA_R, - MIPS_INS_SHRLV, - MIPS_INS_SHRL, - MIPS_INS_SLDI, - MIPS_INS_SLD, - MIPS_INS_SLL, - MIPS_INS_SLL16, - MIPS_INS_SLLI, - MIPS_INS_SLLV, - MIPS_INS_SLT, - MIPS_INS_SLTI, - MIPS_INS_SLTIU, - MIPS_INS_SLTU, - MIPS_INS_SNE, - MIPS_INS_SNEI, - MIPS_INS_SPLATI, - MIPS_INS_SPLAT, - MIPS_INS_SRA, - MIPS_INS_SRAI, - MIPS_INS_SRARI, - MIPS_INS_SRAR, - MIPS_INS_SRAV, - MIPS_INS_SRL, - MIPS_INS_SRL16, - MIPS_INS_SRLI, - MIPS_INS_SRLRI, - MIPS_INS_SRLR, - MIPS_INS_SRLV, - MIPS_INS_SSNOP, - MIPS_INS_ST, - MIPS_INS_SUBQH, - MIPS_INS_SUBQH_R, - MIPS_INS_SUBQ, - MIPS_INS_SUBQ_S, - MIPS_INS_SUBSUS_U, - MIPS_INS_SUBSUU_S, - MIPS_INS_SUBS_S, - MIPS_INS_SUBS_U, - MIPS_INS_SUBU16, - MIPS_INS_SUBUH, - MIPS_INS_SUBUH_R, - MIPS_INS_SUBU, - MIPS_INS_SUBU_S, - MIPS_INS_SUBVI, - MIPS_INS_SUBV, - MIPS_INS_SUXC1, - MIPS_INS_SW, - MIPS_INS_SW16, - MIPS_INS_SWC1, - MIPS_INS_SWC2, - MIPS_INS_SWC3, - MIPS_INS_SWL, - MIPS_INS_SWM16, - MIPS_INS_SWM32, - MIPS_INS_SWP, - MIPS_INS_SWR, - MIPS_INS_SWXC1, - MIPS_INS_SYNC, - MIPS_INS_SYNCI, - MIPS_INS_SYSCALL, - MIPS_INS_TEQ, - MIPS_INS_TEQI, - MIPS_INS_TGE, - MIPS_INS_TGEI, - MIPS_INS_TGEIU, - MIPS_INS_TGEU, - MIPS_INS_TLBP, - MIPS_INS_TLBR, - MIPS_INS_TLBWI, - MIPS_INS_TLBWR, - MIPS_INS_TLT, - MIPS_INS_TLTI, - MIPS_INS_TLTIU, - MIPS_INS_TLTU, - MIPS_INS_TNE, - MIPS_INS_TNEI, - MIPS_INS_TRUNC, - MIPS_INS_V3MULU, - MIPS_INS_VMM0, - MIPS_INS_VMULU, - MIPS_INS_VSHF, - MIPS_INS_WAIT, - MIPS_INS_WRDSP, - MIPS_INS_WSBH, - MIPS_INS_XOR, - MIPS_INS_XOR16, - MIPS_INS_XORI, - - //> some alias instructions - MIPS_INS_NOP, - MIPS_INS_NEGU, - - //> special instructions - MIPS_INS_JALR_HB, // jump and link with Hazard Barrier - MIPS_INS_JR_HB, // jump register with Hazard Barrier - - MIPS_INS_ENDING, + MIPS_INS_INVALID = 0, + MIPS_INS_ABS, + MIPS_INS_ABSQ_S, + MIPS_INS_ADD, + MIPS_INS_ADDI, + MIPS_INS_ADDIU, + MIPS_INS_ADDIUPC, + MIPS_INS_ADDIUR1SP, + MIPS_INS_ADDIUR2, + MIPS_INS_ADDIUS5, + MIPS_INS_ADDIUSP, + MIPS_INS_ADDQ, + MIPS_INS_ADDQH, + MIPS_INS_ADDQH_R, + MIPS_INS_ADDQ_S, + MIPS_INS_ADDR, + MIPS_INS_ADDSC, + MIPS_INS_ADDS_A, + MIPS_INS_ADDS_S, + MIPS_INS_ADDS_U, + MIPS_INS_ADDU, + MIPS_INS_ADDU16, + MIPS_INS_ADDUH, + MIPS_INS_ADDUH_R, + MIPS_INS_ADDU_S, + MIPS_INS_ADDV, + MIPS_INS_ADDVI, + MIPS_INS_ADDWC, + MIPS_INS_ADD_A, + MIPS_INS_ALIGN, + MIPS_INS_ALUIPC, + MIPS_INS_AND, + MIPS_INS_AND16, + MIPS_INS_ANDI, + MIPS_INS_ANDI16, + MIPS_INS_APPEND, + MIPS_INS_ASUB_S, + MIPS_INS_ASUB_U, + MIPS_INS_AUI, + MIPS_INS_AUIPC, + MIPS_INS_AVER_S, + MIPS_INS_AVER_U, + MIPS_INS_AVE_S, + MIPS_INS_AVE_U, + MIPS_INS_B, + MIPS_INS_B16, + MIPS_INS_BADDU, + MIPS_INS_BAL, + MIPS_INS_BALC, + MIPS_INS_BALIGN, + MIPS_INS_BBIT0, + MIPS_INS_BBIT032, + MIPS_INS_BBIT1, + MIPS_INS_BBIT132, + MIPS_INS_BC, + MIPS_INS_BC16, + MIPS_INS_BC1EQZ, + MIPS_INS_BC1EQZC, + MIPS_INS_BC1F, + MIPS_INS_BC1FL, + MIPS_INS_BC1NEZ, + MIPS_INS_BC1NEZC, + MIPS_INS_BC1T, + MIPS_INS_BC1TL, + MIPS_INS_BC2EQZ, + MIPS_INS_BC2EQZC, + MIPS_INS_BC2NEZ, + MIPS_INS_BC2NEZC, + MIPS_INS_BCLR, + MIPS_INS_BCLRI, + MIPS_INS_BEQ, + MIPS_INS_BEQC, + MIPS_INS_BEQL, + MIPS_INS_BEQZ, + MIPS_INS_BEQZ16, + MIPS_INS_BEQZALC, + MIPS_INS_BEQZC, + MIPS_INS_BEQZC16, + MIPS_INS_BEQZL, + MIPS_INS_BGE, + MIPS_INS_BGEC, + MIPS_INS_BGEL, + MIPS_INS_BGEU, + MIPS_INS_BGEUC, + MIPS_INS_BGEUL, + MIPS_INS_BGEZ, + MIPS_INS_BGEZAL, + MIPS_INS_BGEZALC, + MIPS_INS_BGEZALL, + MIPS_INS_BGEZALS, + MIPS_INS_BGEZC, + MIPS_INS_BGEZL, + MIPS_INS_BGT, + MIPS_INS_BGTL, + MIPS_INS_BGTU, + MIPS_INS_BGTUL, + MIPS_INS_BGTZ, + MIPS_INS_BGTZALC, + MIPS_INS_BGTZC, + MIPS_INS_BGTZL, + MIPS_INS_BINSL, + MIPS_INS_BINSLI, + MIPS_INS_BINSR, + MIPS_INS_BINSRI, + MIPS_INS_BITREV, + MIPS_INS_BITSWAP, + MIPS_INS_BLE, + MIPS_INS_BLEL, + MIPS_INS_BLEU, + MIPS_INS_BLEUL, + MIPS_INS_BLEZ, + MIPS_INS_BLEZALC, + MIPS_INS_BLEZC, + MIPS_INS_BLEZL, + MIPS_INS_BLT, + MIPS_INS_BLTC, + MIPS_INS_BLTL, + MIPS_INS_BLTU, + MIPS_INS_BLTUC, + MIPS_INS_BLTUL, + MIPS_INS_BLTZ, + MIPS_INS_BLTZAL, + MIPS_INS_BLTZALC, + MIPS_INS_BLTZALL, + MIPS_INS_BLTZALS, + MIPS_INS_BLTZC, + MIPS_INS_BLTZL, + MIPS_INS_BMNZ, + MIPS_INS_BMNZI, + MIPS_INS_BMZ, + MIPS_INS_BMZI, + MIPS_INS_BNE, + MIPS_INS_BNEC, + MIPS_INS_BNEG, + MIPS_INS_BNEGI, + MIPS_INS_BNEL, + MIPS_INS_BNEZ, + MIPS_INS_BNEZ16, + MIPS_INS_BNEZALC, + MIPS_INS_BNEZC, + MIPS_INS_BNEZC16, + MIPS_INS_BNEZL, + MIPS_INS_BNVC, + MIPS_INS_BNZ, + MIPS_INS_BOVC, + MIPS_INS_BPOSGE32, + MIPS_INS_BPOSGE32C, + MIPS_INS_BREAK, + MIPS_INS_BREAK16, + MIPS_INS_BSEL, + MIPS_INS_BSELI, + MIPS_INS_BSET, + MIPS_INS_BSETI, + MIPS_INS_BTEQZ, + MIPS_INS_BTNEZ, + MIPS_INS_BZ, + MIPS_INS_C, + MIPS_INS_CACHE, + MIPS_INS_CACHEE, + MIPS_INS_CEIL, + MIPS_INS_CEQ, + MIPS_INS_CEQI, + MIPS_INS_CFC1, + MIPS_INS_CFC2, + MIPS_INS_CFCMSA, + MIPS_INS_CFTC1, + MIPS_INS_CINS, + MIPS_INS_CINS32, + MIPS_INS_CLASS, + MIPS_INS_CLEI_S, + MIPS_INS_CLEI_U, + MIPS_INS_CLE_S, + MIPS_INS_CLE_U, + MIPS_INS_CLO, + MIPS_INS_CLTI_S, + MIPS_INS_CLTI_U, + MIPS_INS_CLT_S, + MIPS_INS_CLT_U, + MIPS_INS_CLZ, + MIPS_INS_CMP, + MIPS_INS_CMPGDU, + MIPS_INS_CMPGU, + MIPS_INS_CMPI, + MIPS_INS_CMPU, + MIPS_INS_COPY_S, + MIPS_INS_COPY_U, + MIPS_INS_CRC32B, + MIPS_INS_CRC32CB, + MIPS_INS_CRC32CD, + MIPS_INS_CRC32CH, + MIPS_INS_CRC32CW, + MIPS_INS_CRC32D, + MIPS_INS_CRC32H, + MIPS_INS_CRC32W, + MIPS_INS_CTC1, + MIPS_INS_CTC2, + MIPS_INS_CTCMSA, + MIPS_INS_CTTC1, + MIPS_INS_CVT, + MIPS_INS_DADD, + MIPS_INS_DADDI, + MIPS_INS_DADDIU, + MIPS_INS_DADDU, + MIPS_INS_DAHI, + MIPS_INS_DALIGN, + MIPS_INS_DATI, + MIPS_INS_DAUI, + MIPS_INS_DBITSWAP, + MIPS_INS_DCLO, + MIPS_INS_DCLZ, + MIPS_INS_DDIV, + MIPS_INS_DDIVU, + MIPS_INS_DERET, + MIPS_INS_DEXT, + MIPS_INS_DEXTM, + MIPS_INS_DEXTU, + MIPS_INS_DI, + MIPS_INS_DINS, + MIPS_INS_DINSM, + MIPS_INS_DINSU, + MIPS_INS_DIV, + MIPS_INS_DIVU, + MIPS_INS_DIV_S, + MIPS_INS_DIV_U, + MIPS_INS_DLA, + MIPS_INS_DLI, + MIPS_INS_DLSA, + MIPS_INS_DMFC0, + MIPS_INS_DMFC1, + MIPS_INS_DMFC2, + MIPS_INS_DMFGC0, + MIPS_INS_DMOD, + MIPS_INS_DMODU, + MIPS_INS_DMT, + MIPS_INS_DMTC0, + MIPS_INS_DMTC1, + MIPS_INS_DMTC2, + MIPS_INS_DMTGC0, + MIPS_INS_DMUH, + MIPS_INS_DMUHU, + MIPS_INS_DMUL, + MIPS_INS_DMULO, + MIPS_INS_DMULOU, + MIPS_INS_DMULT, + MIPS_INS_DMULTU, + MIPS_INS_DMULU, + MIPS_INS_DNEG, + MIPS_INS_DNEGU, + MIPS_INS_DOTP_S, + MIPS_INS_DOTP_U, + MIPS_INS_DPA, + MIPS_INS_DPADD_S, + MIPS_INS_DPADD_U, + MIPS_INS_DPAQX_S, + MIPS_INS_DPAQX_SA, + MIPS_INS_DPAQ_S, + MIPS_INS_DPAQ_SA, + MIPS_INS_DPAU, + MIPS_INS_DPAX, + MIPS_INS_DPOP, + MIPS_INS_DPS, + MIPS_INS_DPSQX_S, + MIPS_INS_DPSQX_SA, + MIPS_INS_DPSQ_S, + MIPS_INS_DPSQ_SA, + MIPS_INS_DPSU, + MIPS_INS_DPSUB_S, + MIPS_INS_DPSUB_U, + MIPS_INS_DPSX, + MIPS_INS_DREM, + MIPS_INS_DREMU, + MIPS_INS_DROL, + MIPS_INS_DROR, + MIPS_INS_DROTR, + MIPS_INS_DROTR32, + MIPS_INS_DROTRV, + MIPS_INS_DSBH, + MIPS_INS_DSHD, + MIPS_INS_DSLL, + MIPS_INS_DSLL32, + MIPS_INS_DSLLV, + MIPS_INS_DSRA, + MIPS_INS_DSRA32, + MIPS_INS_DSRAV, + MIPS_INS_DSRL, + MIPS_INS_DSRL32, + MIPS_INS_DSRLV, + MIPS_INS_DSUB, + MIPS_INS_DSUBI, + MIPS_INS_DSUBU, + MIPS_INS_DVP, + MIPS_INS_DVPE, + MIPS_INS_EHB, + MIPS_INS_EI, + MIPS_INS_EMT, + MIPS_INS_ERET, + MIPS_INS_ERETNC, + MIPS_INS_EVP, + MIPS_INS_EVPE, + MIPS_INS_EXT, + MIPS_INS_EXTP, + MIPS_INS_EXTPDP, + MIPS_INS_EXTPDPV, + MIPS_INS_EXTPV, + MIPS_INS_EXTR, + MIPS_INS_EXTRV, + MIPS_INS_EXTRV_R, + MIPS_INS_EXTRV_RS, + MIPS_INS_EXTRV_S, + MIPS_INS_EXTR_R, + MIPS_INS_EXTR_RS, + MIPS_INS_EXTR_S, + MIPS_INS_EXTS, + MIPS_INS_EXTS32, + MIPS_INS_FADD, + MIPS_INS_FCAF, + MIPS_INS_FCEQ, + MIPS_INS_FCLASS, + MIPS_INS_FCLE, + MIPS_INS_FCLT, + MIPS_INS_FCNE, + MIPS_INS_FCOR, + MIPS_INS_FCUEQ, + MIPS_INS_FCULE, + MIPS_INS_FCULT, + MIPS_INS_FCUN, + MIPS_INS_FCUNE, + MIPS_INS_FDIV, + MIPS_INS_FEXDO, + MIPS_INS_FEXP2, + MIPS_INS_FEXUPL, + MIPS_INS_FEXUPR, + MIPS_INS_FFINT_S, + MIPS_INS_FFINT_U, + MIPS_INS_FFQL, + MIPS_INS_FFQR, + MIPS_INS_FILL, + MIPS_INS_FLOG2, + MIPS_INS_FLOOR, + MIPS_INS_FMADD, + MIPS_INS_FMAX, + MIPS_INS_FMAX_A, + MIPS_INS_FMIN, + MIPS_INS_FMIN_A, + MIPS_INS_FMSUB, + MIPS_INS_FMUL, + MIPS_INS_FORK, + MIPS_INS_FRCP, + MIPS_INS_FRINT, + MIPS_INS_FRSQRT, + MIPS_INS_FSAF, + MIPS_INS_FSEQ, + MIPS_INS_FSLE, + MIPS_INS_FSLT, + MIPS_INS_FSNE, + MIPS_INS_FSOR, + MIPS_INS_FSQRT, + MIPS_INS_FSUB, + MIPS_INS_FSUEQ, + MIPS_INS_FSULE, + MIPS_INS_FSULT, + MIPS_INS_FSUN, + MIPS_INS_FSUNE, + MIPS_INS_FTINT_S, + MIPS_INS_FTINT_U, + MIPS_INS_FTQ, + MIPS_INS_FTRUNC_S, + MIPS_INS_FTRUNC_U, + MIPS_INS_GINVI, + MIPS_INS_GINVT, + MIPS_INS_HADD_S, + MIPS_INS_HADD_U, + MIPS_INS_HSUB_S, + MIPS_INS_HSUB_U, + MIPS_INS_HYPCALL, + MIPS_INS_ILVEV, + MIPS_INS_ILVL, + MIPS_INS_ILVOD, + MIPS_INS_ILVR, + MIPS_INS_INS, + MIPS_INS_INSERT, + MIPS_INS_INSV, + MIPS_INS_INSVE, + MIPS_INS_J, + MIPS_INS_JAL, + MIPS_INS_JALR, + MIPS_INS_JALRC, + MIPS_INS_JALRS, + MIPS_INS_JALRS16, + MIPS_INS_JALS, + MIPS_INS_JALX, + MIPS_INS_JIALC, + MIPS_INS_JIC, + MIPS_INS_JR, + MIPS_INS_JR16, + MIPS_INS_JRADDIUSP, + MIPS_INS_JRC, + MIPS_INS_JRC16, + MIPS_INS_JRCADDIUSP, + MIPS_INS_L, + MIPS_INS_LA, + MIPS_INS_LAPC, + MIPS_INS_LB, + MIPS_INS_LBE, + MIPS_INS_LBU, + MIPS_INS_LBU16, + MIPS_INS_LBUE, + MIPS_INS_LBUX, + MIPS_INS_LD, + MIPS_INS_LDC1, + MIPS_INS_LDC2, + MIPS_INS_LDC3, + MIPS_INS_LDI, + MIPS_INS_LDL, + MIPS_INS_LDPC, + MIPS_INS_LDR, + MIPS_INS_LDXC1, + MIPS_INS_LH, + MIPS_INS_LHE, + MIPS_INS_LHU, + MIPS_INS_LHU16, + MIPS_INS_LHUE, + MIPS_INS_LHX, + MIPS_INS_LI, + MIPS_INS_LI16, + MIPS_INS_LL, + MIPS_INS_LLD, + MIPS_INS_LLE, + MIPS_INS_LSA, + MIPS_INS_LUI, + MIPS_INS_LUXC1, + MIPS_INS_LW, + MIPS_INS_LW16, + MIPS_INS_LWC1, + MIPS_INS_LWC2, + MIPS_INS_LWC3, + MIPS_INS_LWE, + MIPS_INS_LWL, + MIPS_INS_LWLE, + MIPS_INS_LWM, + MIPS_INS_LWM16, + MIPS_INS_LWM32, + MIPS_INS_LWP, + MIPS_INS_LWPC, + MIPS_INS_LWR, + MIPS_INS_LWRE, + MIPS_INS_LWU, + MIPS_INS_LWUPC, + MIPS_INS_LWX, + MIPS_INS_LWXC1, + MIPS_INS_LWXS, + MIPS_INS_MADD, + MIPS_INS_MADDF, + MIPS_INS_MADDR_Q, + MIPS_INS_MADDU, + MIPS_INS_MADDV, + MIPS_INS_MADD_Q, + MIPS_INS_MAQ_S, + MIPS_INS_MAQ_SA, + MIPS_INS_MAX, + MIPS_INS_MAXA, + MIPS_INS_MAXI_S, + MIPS_INS_MAXI_U, + MIPS_INS_MAX_A, + MIPS_INS_MAX_S, + MIPS_INS_MAX_U, + MIPS_INS_MFC0, + MIPS_INS_MFC1, + MIPS_INS_MFC2, + MIPS_INS_MFGC0, + MIPS_INS_MFHC0, + MIPS_INS_MFHC1, + MIPS_INS_MFHC2, + MIPS_INS_MFHGC0, + MIPS_INS_MFHI, + MIPS_INS_MFHI16, + MIPS_INS_MFLO, + MIPS_INS_MFLO16, + MIPS_INS_MFTACX, + MIPS_INS_MFTC0, + MIPS_INS_MFTC1, + MIPS_INS_MFTDSP, + MIPS_INS_MFTGPR, + MIPS_INS_MFTHC1, + MIPS_INS_MFTHI, + MIPS_INS_MFTLO, + MIPS_INS_MFTR, + MIPS_INS_MIN, + MIPS_INS_MINA, + MIPS_INS_MINI_S, + MIPS_INS_MINI_U, + MIPS_INS_MIN_A, + MIPS_INS_MIN_S, + MIPS_INS_MIN_U, + MIPS_INS_MOD, + MIPS_INS_MODSUB, + MIPS_INS_MODU, + MIPS_INS_MOD_S, + MIPS_INS_MOD_U, + MIPS_INS_MOV, + MIPS_INS_MOVE, + MIPS_INS_MOVE16, + MIPS_INS_MOVEP, + MIPS_INS_MOVF, + MIPS_INS_MOVN, + MIPS_INS_MOVT, + MIPS_INS_MOVZ, + MIPS_INS_MSUB, + MIPS_INS_MSUBF, + MIPS_INS_MSUBR_Q, + MIPS_INS_MSUBU, + MIPS_INS_MSUBV, + MIPS_INS_MSUB_Q, + MIPS_INS_MTC0, + MIPS_INS_MTC1, + MIPS_INS_MTC2, + MIPS_INS_MTGC0, + MIPS_INS_MTHC0, + MIPS_INS_MTHC1, + MIPS_INS_MTHC2, + MIPS_INS_MTHGC0, + MIPS_INS_MTHI, + MIPS_INS_MTHLIP, + MIPS_INS_MTLO, + MIPS_INS_MTM0, + MIPS_INS_MTM1, + MIPS_INS_MTM2, + MIPS_INS_MTP0, + MIPS_INS_MTP1, + MIPS_INS_MTP2, + MIPS_INS_MTTACX, + MIPS_INS_MTTC0, + MIPS_INS_MTTC1, + MIPS_INS_MTTDSP, + MIPS_INS_MTTGPR, + MIPS_INS_MTTHC1, + MIPS_INS_MTTHI, + MIPS_INS_MTTLO, + MIPS_INS_MTTR, + MIPS_INS_MUH, + MIPS_INS_MUHU, + MIPS_INS_MUL, + MIPS_INS_MULEQ_S, + MIPS_INS_MULEU_S, + MIPS_INS_MULO, + MIPS_INS_MULOU, + MIPS_INS_MULQ_RS, + MIPS_INS_MULQ_S, + MIPS_INS_MULR, + MIPS_INS_MULR_Q, + MIPS_INS_MULSA, + MIPS_INS_MULSAQ_S, + MIPS_INS_MULT, + MIPS_INS_MULTU, + MIPS_INS_MULU, + MIPS_INS_MULV, + MIPS_INS_MUL_Q, + MIPS_INS_MUL_S, + MIPS_INS_NEG, + MIPS_INS_NEGU, + MIPS_INS_NLOC, + MIPS_INS_NLZC, + MIPS_INS_NMADD, + MIPS_INS_NMSUB, + MIPS_INS_NOP, + MIPS_INS_NOR, + MIPS_INS_NORI, + MIPS_INS_NOT, + MIPS_INS_NOT16, + MIPS_INS_OR, + MIPS_INS_OR16, + MIPS_INS_ORI, + MIPS_INS_PACKRL, + MIPS_INS_PAUSE, + MIPS_INS_PCKEV, + MIPS_INS_PCKOD, + MIPS_INS_PCNT, + MIPS_INS_PICK, + MIPS_INS_PLL, + MIPS_INS_PLU, + MIPS_INS_POP, + MIPS_INS_PRECEQ, + MIPS_INS_PRECEQU, + MIPS_INS_PRECEU, + MIPS_INS_PRECR, + MIPS_INS_PRECRQ, + MIPS_INS_PRECRQU_S, + MIPS_INS_PRECRQ_RS, + MIPS_INS_PRECR_SRA, + MIPS_INS_PRECR_SRA_R, + MIPS_INS_PREF, + MIPS_INS_PREFE, + MIPS_INS_PREFX, + MIPS_INS_PREPEND, + MIPS_INS_PUL, + MIPS_INS_PUU, + MIPS_INS_RADDU, + MIPS_INS_RDDSP, + MIPS_INS_RDHWR, + MIPS_INS_RDPGPR, + MIPS_INS_RECIP, + MIPS_INS_REM, + MIPS_INS_REMU, + MIPS_INS_REPL, + MIPS_INS_REPLV, + MIPS_INS_RINT, + MIPS_INS_ROL, + MIPS_INS_ROR, + MIPS_INS_ROTR, + MIPS_INS_ROTRV, + MIPS_INS_ROUND, + MIPS_INS_RSQRT, + MIPS_INS_S, + MIPS_INS_SAA, + MIPS_INS_SAAD, + MIPS_INS_SAT_S, + MIPS_INS_SAT_U, + MIPS_INS_SB, + MIPS_INS_SB16, + MIPS_INS_SBE, + MIPS_INS_SC, + MIPS_INS_SCD, + MIPS_INS_SCE, + MIPS_INS_SD, + MIPS_INS_SDBBP, + MIPS_INS_SDBBP16, + MIPS_INS_SDC1, + MIPS_INS_SDC2, + MIPS_INS_SDC3, + MIPS_INS_SDL, + MIPS_INS_SDR, + MIPS_INS_SDXC1, + MIPS_INS_SEB, + MIPS_INS_SEH, + MIPS_INS_SEL, + MIPS_INS_SELEQZ, + MIPS_INS_SELNEZ, + MIPS_INS_SEQ, + MIPS_INS_SEQI, + MIPS_INS_SGE, + MIPS_INS_SGEU, + MIPS_INS_SGT, + MIPS_INS_SGTU, + MIPS_INS_SH, + MIPS_INS_SH16, + MIPS_INS_SHE, + MIPS_INS_SHF, + MIPS_INS_SHILO, + MIPS_INS_SHILOV, + MIPS_INS_SHLL, + MIPS_INS_SHLLV, + MIPS_INS_SHLLV_S, + MIPS_INS_SHLL_S, + MIPS_INS_SHRA, + MIPS_INS_SHRAV, + MIPS_INS_SHRAV_R, + MIPS_INS_SHRA_R, + MIPS_INS_SHRL, + MIPS_INS_SHRLV, + MIPS_INS_SIGRIE, + MIPS_INS_SLD, + MIPS_INS_SLDI, + MIPS_INS_SLE, + MIPS_INS_SLEU, + MIPS_INS_SLL, + MIPS_INS_SLL16, + MIPS_INS_SLLI, + MIPS_INS_SLLV, + MIPS_INS_SLT, + MIPS_INS_SLTI, + MIPS_INS_SLTIU, + MIPS_INS_SLTU, + MIPS_INS_SNE, + MIPS_INS_SNEI, + MIPS_INS_SPLAT, + MIPS_INS_SPLATI, + MIPS_INS_SQRT, + MIPS_INS_SRA, + MIPS_INS_SRAI, + MIPS_INS_SRAR, + MIPS_INS_SRARI, + MIPS_INS_SRAV, + MIPS_INS_SRL, + MIPS_INS_SRL16, + MIPS_INS_SRLI, + MIPS_INS_SRLR, + MIPS_INS_SRLRI, + MIPS_INS_SRLV, + MIPS_INS_SSNOP, + MIPS_INS_ST, + MIPS_INS_SUB, + MIPS_INS_SUBQ, + MIPS_INS_SUBQH, + MIPS_INS_SUBQH_R, + MIPS_INS_SUBQ_S, + MIPS_INS_SUBSUS_U, + MIPS_INS_SUBSUU_S, + MIPS_INS_SUBS_S, + MIPS_INS_SUBS_U, + MIPS_INS_SUBU, + MIPS_INS_SUBU16, + MIPS_INS_SUBUH, + MIPS_INS_SUBUH_R, + MIPS_INS_SUBU_S, + MIPS_INS_SUBV, + MIPS_INS_SUBVI, + MIPS_INS_SUXC1, + MIPS_INS_SW, + MIPS_INS_SW16, + MIPS_INS_SWC1, + MIPS_INS_SWC2, + MIPS_INS_SWC3, + MIPS_INS_SWE, + MIPS_INS_SWL, + MIPS_INS_SWLE, + MIPS_INS_SWM, + MIPS_INS_SWM16, + MIPS_INS_SWM32, + MIPS_INS_SWP, + MIPS_INS_SWR, + MIPS_INS_SWRE, + MIPS_INS_SWSP, + MIPS_INS_SWXC1, + MIPS_INS_SYNC, + MIPS_INS_SYNCI, + MIPS_INS_SYNCIOBDMA, + MIPS_INS_SYNCS, + MIPS_INS_SYNCW, + MIPS_INS_SYNCWS, + MIPS_INS_SYSCALL, + MIPS_INS_TEQ, + MIPS_INS_TEQI, + MIPS_INS_TGE, + MIPS_INS_TGEI, + MIPS_INS_TGEIU, + MIPS_INS_TGEU, + MIPS_INS_TLBGINV, + MIPS_INS_TLBGINVF, + MIPS_INS_TLBGP, + MIPS_INS_TLBGR, + MIPS_INS_TLBGWI, + MIPS_INS_TLBGWR, + MIPS_INS_TLBINV, + MIPS_INS_TLBINVF, + MIPS_INS_TLBP, + MIPS_INS_TLBR, + MIPS_INS_TLBWI, + MIPS_INS_TLBWR, + MIPS_INS_TLT, + MIPS_INS_TLTI, + MIPS_INS_TLTIU, + MIPS_INS_TLTU, + MIPS_INS_TNE, + MIPS_INS_TNEI, + MIPS_INS_TRUNC, + MIPS_INS_ULH, + MIPS_INS_ULHU, + MIPS_INS_ULW, + MIPS_INS_USH, + MIPS_INS_USW, + MIPS_INS_V3MULU, + MIPS_INS_VMM0, + MIPS_INS_VMULU, + MIPS_INS_VSHF, + MIPS_INS_WAIT, + MIPS_INS_WRDSP, + MIPS_INS_WRPGPR, + MIPS_INS_WSBH, + MIPS_INS_XOR, + MIPS_INS_XOR16, + MIPS_INS_XORI, + MIPS_INS_YIELD, + + MIPS_INS_ENDING, } mips_insn; /// Group of MIPS instructions typedef enum mips_insn_group { - MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID - - // Generic groups - // all jump instructions (conditional+direct+indirect jumps) - MIPS_GRP_JUMP, ///< = CS_GRP_JUMP - // all call instructions - MIPS_GRP_CALL, ///< = CS_GRP_CALL - // all return instructions - MIPS_GRP_RET, ///< = CS_GRP_RET - // all interrupt instructions (int+syscall) - MIPS_GRP_INT, ///< = CS_GRP_INT - // all interrupt return instructions - MIPS_GRP_IRET, ///< = CS_GRP_IRET - // all privileged instructions - MIPS_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE - // all relative branching instructions - MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE - - // Architecture-specific groups - MIPS_GRP_BITCOUNT = 128, - MIPS_GRP_DSP, - MIPS_GRP_DSPR2, - MIPS_GRP_FPIDX, - MIPS_GRP_MSA, - MIPS_GRP_MIPS32R2, - MIPS_GRP_MIPS64, - MIPS_GRP_MIPS64R2, - MIPS_GRP_SEINREG, - MIPS_GRP_STDENC, - MIPS_GRP_SWAP, - MIPS_GRP_MICROMIPS, - MIPS_GRP_MIPS16MODE, - MIPS_GRP_FP64BIT, - MIPS_GRP_NONANSFPMATH, - MIPS_GRP_NOTFP64BIT, - MIPS_GRP_NOTINMICROMIPS, - MIPS_GRP_NOTNACL, - MIPS_GRP_NOTMIPS32R6, - MIPS_GRP_NOTMIPS64R6, - MIPS_GRP_CNMIPS, - MIPS_GRP_MIPS32, - MIPS_GRP_MIPS32R6, - MIPS_GRP_MIPS64R6, - MIPS_GRP_MIPS2, - MIPS_GRP_MIPS3, - MIPS_GRP_MIPS3_32, - MIPS_GRP_MIPS3_32R2, - MIPS_GRP_MIPS4_32, - MIPS_GRP_MIPS4_32R2, - MIPS_GRP_MIPS5_32R2, - MIPS_GRP_GP32BIT, - MIPS_GRP_GP64BIT, - - MIPS_GRP_ENDING, + MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + // Generic groups + // all jump instructions (conditional+direct+indirect jumps) + MIPS_GRP_JUMP, ///< = CS_GRP_JUMP + // all call instructions + MIPS_GRP_CALL, ///< = CS_GRP_CALL + // all return instructions + MIPS_GRP_RET, ///< = CS_GRP_RET + // all interrupt instructions (int+syscall) + MIPS_GRP_INT, ///< = CS_GRP_INT + // all interrupt return instructions + MIPS_GRP_IRET, ///< = CS_GRP_IRET + // all privileged instructions + MIPS_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE + // all relative branching instructions + MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE + + // Architecture-specific groups + MIPS_GRP_BITCOUNT = 128, + MIPS_GRP_DSP, + MIPS_GRP_DSPR2, + MIPS_GRP_FPIDX, + MIPS_GRP_MSA, + MIPS_GRP_MIPS32R2, + MIPS_GRP_MIPS64, + MIPS_GRP_MIPS64R2, + MIPS_GRP_SEINREG, + MIPS_GRP_STDENC, + MIPS_GRP_SWAP, + MIPS_GRP_MICROMIPS, + MIPS_GRP_MIPS16MODE, + MIPS_GRP_FP64BIT, + MIPS_GRP_NONANSFPMATH, + MIPS_GRP_NOTFP64BIT, + MIPS_GRP_NOTINMICROMIPS, + MIPS_GRP_NOTNACL, + MIPS_GRP_NOTMIPS32R6, + MIPS_GRP_NOTMIPS64R6, + MIPS_GRP_CNMIPS, + MIPS_GRP_MIPS32, + MIPS_GRP_MIPS32R6, + MIPS_GRP_MIPS64R6, + MIPS_GRP_MIPS2, + MIPS_GRP_MIPS3, + MIPS_GRP_MIPS3_32, + MIPS_GRP_MIPS3_32R2, + MIPS_GRP_MIPS4_32, + MIPS_GRP_MIPS4_32R2, + MIPS_GRP_MIPS5_32R2, + MIPS_GRP_GP32BIT, + MIPS_GRP_GP64BIT, + + MIPS_GRP_MIPS3D, + MIPS_GRP_DSPR3, + MIPS_GRP_EVA, + MIPS_GRP_CRC, + MIPS_GRP_MT, + MIPS_GRP_MIPS64R5, + MIPS_GRP_VIRT, + MIPS_GRP_NOTSOFTFLOAT, + MIPS_GRP_NOTCNMIPS, + MIPS_GRP_MIPS32R5, + MIPS_GRP_GINV, + MIPS_GRP_NOINDIRECTJUMPGUARDS, + MIPS_GRP_NOTINMIPS16MODE, + MIPS_GRP_MADD4, + MIPS_GRP_PTR32BIT, + MIPS_GRP_PTR64BIT, + MIPS_GRP_NOTMIPS3, + MIPS_GRP_CNMIPSP, + + MIPS_GRP_ENDING, } mips_insn_group; #ifdef __cplusplus diff --git a/sync/README.md b/sync/README.md new file mode 100644 index 0000000000..78f640f5d7 --- /dev/null +++ b/sync/README.md @@ -0,0 +1,93 @@ +Capstone Syncing +=============== + +This document describes the use of syncing tools and +used as a tracking file for sync progress. + +## How to adapt an architecture with auto-sync + +0. Get a copy of llvm-project source (or all it's architecture files) + +1. Pull the [modified llvm-tblgen backend](https://github.com/rizinorg/llvm-capstone) from +It is recommend that the llvm-project commit matches with the latest mainstream commit from llvm-capstone. + +2. Build the modified backend with target `llvm-tblgen` +```shell +cmake --build ./llvm-project/build --target llvm-tblgen --config Release +``` + +3. Select the architecture from llvm as ARCH +```shell +export $ARCH=Mips +``` + +4. Use `llvm-tblgen` binary to generate the disassembler +```shell +python ./sync/gen-table.py -i ./llvm-project/ -b ./llvm-project/llvm/build/llvm-tblgen ${ARCH} -o ~/Capstone/${ARCH}/${ARCH}GenDisassemblerTables.inc +``` + +Note that the last path varies depending on the location of your Capstone sources. +More information on the TableGen backend see at the [SYNCING](SYNCING.md) document. + +5. Use the `sync/main.py` script from this repo. to generate a disassembler callback file +```shell +python ./sync/main.py ./llvm-project/llvm/lib/Target/$ARCH/Disassembler/${ARCH}Disassembler.cpp \ + > ./Capstone${ARCH}Module.h +``` + +6. Integrate the `Capstone${Arch}Module.h` with corresponding backends in capstone + +for more notes on integration see the `Note on Capstone{Arch}Module.h` chapter below + +7. Truncate the arch's disassembler and instruction printers to make it fit + +This is a rather complicated step and highly depends on the original design of arch, the main idea +is to make it best fit the table-gened file + +## How to sync with LLVM's update once the adaptation is done + +Simple, just repeat the step `4` on the previous chapter and replace the `.inc` file with newly generated one + +## Note on Capstone{Arch}Module.h + +0. ARM & AArch64 from llvm uses feature bits on operand decoding, but capstone ignores them, e.g. +```c++ +const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + +bool hasMP = featureBits[ARM_FeatureMP]; +bool hasV7Ops = featureBits[ARM_HasV7Ops]; +``` +in capstone scene it would simply be +```c +bool hasMP = true; +bool hasV7Ops = true; +``` + +1. The auto-sync python script does not performs well on template functions, so some manual override might be needed + +## Current adaptation progress: + +- [ ] All architectures + - [x] Mips + - [x] ARM + - [x] AArch64 + - [x] Riscv + - [x] PowerPC + - [x] Sparc + - [x] SystemZ + - [ ] ~~TMS320C64x~~ (not supported by LLVM) + - [x] XCore + - [ ] ~~BPF~~ (structurally independent) +- [x] Disassembler +- [x] Instruction Printer +- [ ] Tests +- [ ] Mapping Supports + - [x] Mips +- [ ] Binding Supports + +## Some points that might have to be fixed later + +- [ ] Feature bits +- [ ] Suspicious namespace conflicts +- [ ] PPC QPX ? PPC 64 diff --git a/sync/SYNCING.md b/sync/SYNCING.md new file mode 100644 index 0000000000..34ecd5d741 --- /dev/null +++ b/sync/SYNCING.md @@ -0,0 +1,109 @@ +Capstone Auto-Sync +=============== + +Capstone Auto-Sync is an initiative to partly automate the synchronization of certain architectures to the latest. + +Most of the Capstone's `.inc` files a generated from LLVM's TableGen backend and processed by python scrips +in `suite/synctools` into C-compatible files, which leads to the problem that with LLVM's update, it's not always +(hardly, in fact) +possible to use the synctools without patch in regard to LLVM's upstream change. + +This syncing tools, however, using a custom-made LLVM TableGen +backend ([here](https://github.com/rizinorg/llvm-capstone)) +to generate `.inc` files natively usable by Capstone. With certain adaptations in Capstone's structure, it is possible +to consistently automate large parts of the work on keeping up with LLVM's latest Target (i.e. `.td` files) update, and +optimally, there could be zero-overhead in the process of updating +( +see [this patch on missing bcxf instructions](https://github.com/rizinorg/llvm-capstone/commit/d594f4f6b0755ab11580e1e87d610b560e71b5ef)) + +## Components + +There are three primary components on this syncing tools, listed below: + +1. llvm-capstone (as shown above), this is where the custom `.inc` file generator lies, it's based on the latest HEAD of + llvm-project and is prepared for rebase onto future versions. +2. CapstoneXXX(Arch)Modules.h, this is added for each supported architectures, and contains the necessary specialized + decoder functions for TableGen-ed disassemblers, it also means that it is used to import the disassembler and expose + it to Capstone. +3. XXX(Arch)GenDisassemblerTables.inc, this is the TableGen-ed file contains various information & codes generated from + LLVM's Target Description (*.td) + files, it is fully auto-generated and is recommended not to be modified manually, the following of this document will + introduce various important parts of this file. + +## TableGen-ed file + +The tablegen-ed file has the following parts, respectively: + +### Disassembler & Feature Enums + +This disassembler part contains **tables** and codes of this architecture's instructions, and is expected to be +C-Compatible, the `DecodeInstruction` here can be used to define an instruction decoder function like that we could see +in `AArch64GenDisassemblerTables.inc`: + +```c +// define the insn file extractor +FieldFromInstruction(fieldFromInstruction, uint32_t) +// define the `to MCInst` decoder +DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) +// define the instruction decoder `i.e. disassembler` +DecodeInstruction(decodeInstruction, fieldFromInstruction, + decodeToMCInst, uint32_t) +``` + +and thus this `decodeInstruction` can be called as a C function with the disassemble **table** given, like such: + +```c +// Calling the auto-generated decoder function. + result = + decodeInstruction_4(DecoderTableARM32, MI, insn, Address, 0, ud->mode); +``` + +This part of file is enabled with macro `#{ARCH}_GET_DISASSEMBLER` + +### Registers Info & Instruction Info Enums + +Each disassembled MCInst contains OpCode ID and Operand ID (if they're not immediate) that might not be known to +Capstone. The Register & Instruction Info Enums exhibit there correspondence to the "magic numbers" within MCInst. And +can be used by Capstone to map each OpCode & Operand into the identifiable ones. + +This also contains miscellaneous like Register Class IDs, which shall be vital to certain instructions. + +This part of file is enabled with macro `#GET_INSTRINFO_ENUM` and `#GET_REGINFO_ENUM` + +### Extra Register Info + +Sometimes Capstone needs more information Certain information on registers, e.g., architectures have special registers +that possesses `Sub Register` or `Super Register` (like `D` and `Q` +registers in ARM64), and also, Capstone is using their names (in LLVM), like for instruction printing. This part +contains all the info. that might be needed to find a registers' name, their sub-regs or super-regs, and also it +contains register class definitions, making it possible to index into certain register class, or to find which class a +register belongs to. + +This part of file is enabled with macro `#GET_REGINFO_EXTRA` and `#GET_REGINFO_MC_DESC` + +### Instruction Printer (Asm Writer) + +Printing an instruction, like that of disassembler, is provided with certain functions to perform, this includes: + +1. `$ARCH_getMnemonic`, this function returns a pair of instruction mnemonic and its printer-specific operand info, + given a valid `MCInst`. +2. `printInstruction`, this function prints instruction according to the given `MCInst`, and make it's output to a + Capstone `SStream`, note that this method make callbacks to architecture-specific operand printers defined + in `${ARCH}InstPrinter.c`, and the specialized operand printer should be manually tweaked to meet up with custom + needs. +3. `getRegisterName`, this function maps register ID (LLVM internal) into their names, note that the name provided could + be different from convention to convention, that's why we have `$ARCH_reg_name` in `${ARCH}Mapping.c` file. In this + patched version this is used as a fallback for register that has not been named by Capstone. +4. `printAliasInstr`, some instructions might have aliases in that the performs the same under certain architecture, + that's when this function is used, commonly, this function is called before `printInstruction` to make sure that the + aliases is checked before printing the raw one. + +The first two is accessed by `#GET_ASM_WRITER`, and the alias printing function is accessed by `#PRINT_ALIAS_INSTR`. + +### Instruction Operand Info + +Capstone partly rely on operand usages provided by LLVM, that has its cons and pros, this part of the file is for providing it. +It contains an instruction-to-info. mappings, giving Capstone information on the properties of an instructions' operand one-by-one. + +This part also contains the LLVM internal name table for each instruction, which is not commonly used by capstone (but can be referenced if needed) +To enable this, use `#GET_INSTRINFO_MC_DESC` diff --git a/sync/gen-table.py b/sync/gen-table.py new file mode 100755 index 0000000000..4fa41c1495 --- /dev/null +++ b/sync/gen-table.py @@ -0,0 +1,89 @@ +#!/usr/bin/python + +import optparse +import os +import platform +import sys + +parse = optparse.OptionParser(usage='"usage:%prog [options] "', version="%prog 1.0") +parse.add_option('-i', '--include', dest='include_dir', action='store', type=str + , help='path to LLVM source location, which should generally be path to a dir named `llvm-project` (' + 'or `llvm-capstone`)') + +# It's the best that you configure llvm-tblgen into PATH variable, however we support manual approach +parse.add_option('-b', '--bin', type=str, help='specify location of llvm-tblgen.exe/llvm-tblgen binary') + +parse.add_option('-o', '--output', type=str, help='specify output file location, this is NOT mandatory') + +parse.add_option('--mapper', dest='mapper', action='store_true' + , default=False, help='generate mapper instead of disassembler') + +parse.add_option('-d', '--build-dir', type=str, help='custom cmake build dir (for seeking tablegen includes) relative ' + 'to include dir') + +(options, args) = parse.parse_args() + +if options.include_dir is None: + print("Error: Please specify the LLVM source location with `-i`") + exit() + +if len(args) == 0: + parse.print_usage() + print("Error: Please specify the architecture") + exit() + +supported_arch = ["Mips", "ARM", "AArch64", "RISCV", "PowerPC", "Sparc", "SystemZ", "XCore"] + + +# In case of architecture names' ambiguity +def fix_arch_mapping(name): + for arch in supported_arch: + if name.lower() == arch.lower(): + return arch + if name.lower() == "arm64": + return "AArch64" + if name.lower() == "ppc": + return "PowerPC" + return name + + +arch = fix_arch_mapping(args[0]) + +if arch not in supported_arch: + parse.print_usage() + print("Unrecognized architecture: " + arch) + print("Those supported are:") + print(supported_arch) + +print(options) + +is_win = platform.system().lower() == "windows" + +bin_to_use = ("llvm-tblgen.exe" if is_win else "llvm-tblgen") if options.bin is None else options.bin + +use_mapper = "-mapper" if options.mapper else "" + +build_dir = "build" if options.build_dir is None else options.build_dir + +command = "{0} --gen-capstone{1} -I{2}/llvm/lib/Target/{3} " \ + "-I{2}/{4}/include " \ + "-I{2}/llvm/include " \ + "-I{2}/llvm/lib/Target " \ + "{2}/llvm/lib/Target/{3}/{5}.td".format(bin_to_use, use_mapper, options.include_dir, arch, + build_dir, arch if arch != "PowerPC" else "PPC") + +result = os.popen(command, "r") +lines = result.readlines() + +if not lines: + print("TableGen execution exited with error, command executed is:") + print(command) + exit() + +if options.output is None: + sys.stdout.writelines(lines) +else: + file_out = file(options.output, "wb") + file_out.writelines(lines) + +# "/home/phosphorus/Documents/Capstone/arch/SystemZ/SystemZGenDisassemblerTables.inc " diff --git a/sync/logger.h b/sync/logger.h new file mode 100644 index 0000000000..627ece9536 --- /dev/null +++ b/sync/logger.h @@ -0,0 +1,49 @@ +// +// Created by phosphorus on 8/19/21. +// + +#ifndef CAPSTONE_LOGGER_H +#define CAPSTONE_LOGGER_H + +//#define CAPSTONE_NG_DEBUG +//#define TO_FILE "/home/phosphorus/Capstone/start.log" + +#ifdef CAPSTONE_NG_DEBUG + +#ifdef TO_FILE + +#define init_file \ + freopen(TO_FILE, "w+", stdout); \ + setvbuf(stdout, NULL, _IONBF, 0) + +#else + +#define init_file \ + {} + +#endif + +#define debug(format, ...) printf("[DEBUG] " format __VA_OPT__(, ) __VA_ARGS__) + +#define debugln(format, ...) \ + printf("[DEBUG] " format "\n" __VA_OPT__(, ) __VA_ARGS__) + +#define println(format, ...) printf(format "\n" __VA_OPT__(, ) __VA_ARGS__) + +#else + +#define init_file \ + {} + +#define debug(format, ...) \ + {} + +#define debugln(format, ...) \ + {} + +#define println(format, ...) \ + {} + +#endif + +#endif // CAPSTONE_LOGGER_H diff --git a/sync/main.py b/sync/main.py new file mode 100644 index 0000000000..8b7a5e2dec --- /dev/null +++ b/sync/main.py @@ -0,0 +1,225 @@ +#!/usr/bin/python +import functools +import sys +import re + +# NOTE : unfortunately not all of the disassembler details are recorded in llvm *.td file +# this script is for dumping those codes into our project + +arch = "SystemZ" # TODO + +f = open(sys.argv[1]) +lines = f.readlines() +f.close() + +buffer = [] +read_depth = 0 + +thumb_mode = False + + +def is_arm(): + return arch == "ARM" or arch == "AArch64" + + +def join(x, y): + return x + y + + +def create_reg_decode_def(func): + output = functools.reduce(join, func) + + # parameters type replacement + output = output.replace("MCInst &", "MCInst *", 1) + output = output.replace("InsnType", "unsigned") # replace all for InsnType is fine + output = output.replace("const void", "MCRegisterInfo", 1) + + print(output) + + +def create_reg_const(func): + output = functools.reduce(join, func) + output = output.replace("::", "_") + print(output) + + +def create_reg_decode(func): + output = functools.reduce(join, func) + + # parameters type replacement + output = output.replace("MCInst &", "MCInst *", 1) + output = output.replace("InsnType", "unsigned") # replace all for InsnType is fine + output = output.replace("const void", "MCRegisterInfo", 1) + + # standard c-fy + output = output.replace("nullptr", "0x0") + output = output.replace("LLVM_FALLTHROUGH", "0x0") + + # FIXME bunch of patches incoming + # quick patch to the MIPS function pointers + output = output.replace( + "using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);", + "DecodeStatus (* RegDecoder)(MCInst *, unsigned, uint64_t, MCRegisterInfo *);", + ) + output = output.replace("DecodeFN RegDecoder = 0x0;", "RegDecoder = 0x0;") + + # a unfortunate patch to MIPS + + output = output.replace( + "Inst.getOperand(2).getImm()", "MCOperand_getImm(MCInst_getOperand(Inst, 2))" + ) + + # unfortunate patch to ARM & AArch64 + + if is_arm(): + output = output.replace( + "fieldFromInstruction", + "fieldFromInstruction_" + ("2" if thumb_mode else "4"), + ) + output = output.replace("Check(S", "Check(&S") + output = output.replace("Check(DS", "Check(&DS") + output = re.sub( + r"const FeatureBitset &[fF]eatureBits =.+?;", + "/* Ignored bit flags */", + output, + flags=re.S, + ) + output = re.sub(r"[fF]eatureBits\[.+?]", "true", output) + + # here goes the common procedure (not patch) + # namespace replacement + output = output.replace("MCDisassembler::", "MCDisassembler_") + output = output.replace(arch + "::", arch + "_") + + # method call replacement + def re_opcode(x): + return "MCInst_setOpcode(" + x.group(1) + ", " + x.group(2) + ");" + + def re_with(op_name): + def re_with_inner(x): + return ( + "MCOperand_Create" + + op_name + + "(" + + x.group(1) + + ", " + + x.group(2) + + ");" + ) + + return re_with_inner + + def re_operand(x): + newline = x.group(0) + if "createReg" in newline: + return re.sub( + r"([A-Za-z]+)\.addOperand\(\s*MCOperand::createReg\((.+?)\)\);", + re_with("Reg0"), + newline, + flags=re.DOTALL, + ) + else: + return re.sub( + r"([A-Za-z]+)\.addOperand\(\s*MCOperand::createImm\((.+?)\)\);", + re_with("Imm0"), + newline, + flags=re.DOTALL, + ) + + output = re.sub( + r"([A-Za-z]+)\.setOpcode\(\s*(.+?)\);", re_opcode, output, flags=re.DOTALL + ) + output = re.sub( + r"([A-Za-z]+)\.addOperand\(\s*(.+?)\);", re_operand, output, flags=re.DOTALL + ) + output = re.sub( + r"([A-Za-z]+)\.getOpcode\(\)", + lambda x: "MCInst_getOpcode(" + x.group(1) + ")", + output, + ) + + # for template functions constraint by value, we integrate those template param + # template void func(); ----> void func(int x); + # note that this change is on call site, so we've got to change the decls. manually + while re.findall(r"<.+>\(", output, flags=re.DOTALL): + location = re.findall(r"<.+?>\(", output) + for line_str in location: + pos = output.find(line_str) + end = pos + len(line_str) # scan parameters within brackets + depth = 0 + while depth >= 0: + end += 1 + if output[end] == ")": + depth -= 1 + if output[end] == "(": + depth += 1 + params = output[pos + len(line_str) : end] + template = re.findall(r"<(.+?)>", output) + output = output[0:pos] + "(" + params + ", " + template[0] + output[end:] + + # `::` are never valid in C, we'd remove it whenever possible + output = output.replace("::", "_") + + print(output) + + +# dump the constants +print("static void llvm_unreachable(const char * info) {}") +print("static void assert(int val) {}") + +const_table = False + + +for line in lines: + if re.match(r"static DecodeStatus", line): + if "readInstruction" in line or "checkDecodedInstruction" in line: + continue + if "Thumb" in line and is_arm(): + thumb_mode = True + buffer.append(line) + if ";" in line: # let go of the function declaration + create_reg_decode_def(buffer) + buffer.clear() + continue + if "{" in line: + read_depth = 2 + else: + read_depth = 1 + continue + if "static const uint16_t" in line or "static const unsigned" in line: + if read_depth < 1: + buffer.append(line) + const_table = 0 + if "{" in line: + read_depth = 2 + else: + read_depth = 1 + continue + if ( + ";" in line and read_depth <= 1 and len(buffer) > 0 + ): # lazy detection of function definitions + buffer.append(line) + create_reg_decode_def(buffer) + buffer.clear() + read_depth = 0 + continue + if is_arm() and read_depth == 1: + if "Thumb" in line: + thumb_mode = True + if "{" in line and read_depth >= 1: + buffer.append(line) + if "}" not in line: + read_depth += 1 + continue + if read_depth >= 1: + buffer.append(line) + if "}" in line: + read_depth -= 1 + if read_depth <= 1: + if const_table: + create_reg_const(buffer) + else: + create_reg_decode(buffer) + read_depth = 0 + thumb_mode = False + buffer.clear() diff --git a/sync/mips_backup b/sync/mips_backup new file mode 100644 index 0000000000..5c4c5277ca --- /dev/null +++ b/sync/mips_backup @@ -0,0 +1,80 @@ +d "add.s f0, f0, f0" 00000046 0x4 +d "addi zero, zero, 0" 00000020 0x4 +d "addiu zero, t0, -0x19" e7ff0025 0x4 +d "addiu zero, t0, 0" 00000025 0x4 +d "andi zero, zero, 0" 00000030 0x4 +d "b 8" 00000010 0x4 +d "bc0f 8" 00000041 0x4 +d "bc1f 8" 00000045 0x4 +d "bc2f 8" 00000049 0x4 +d "bc3f 8" 0000004d 0x4 +d "beq t0, s0, 0x444c" 11111011 0x4 +d "beql sp, t8, 0x14008" 0050b853 0x4 +d "beqz t0, 8" 00000011 0x4 +d "bgez v0, 0x10" 02004104 0x4 +d "bgezal s1, 0x108" 40003106 0x4 +d "bgezall t3, 0x128" 48007305 0x4 +d "bgezl t6, 0x128" 4800c305 0x4 +d "bgtz zero, 8" 0000001c 0x4 +d "bgtzl zero, 8" 0000005c 0x4 +d "blez zero, 8" 00000018 0x4 +d "blezl zero, 8" 00000058 0x4 +d "bltz zero, 8" 00000004 0x4 +d "bltzl s6, 0x118" 4400c206 0x4 +d "bne t0, s0, 0x440c" 01111015 0x4 +d "bnel s0, s0, -0xbff8" 00d01056 0x4 +d "bnez zero, 8" 00000014 0x4 +d "cache 0, (zero)" 000000bc 0x4 +d "daddi zero, zero, 0" 00000060 0x4 +d "daddiu zero, zero, 0" 00000064 0x4 +d "j 0" 00000008 0x4 +d "jal 0" 0000000c 0x4 +d "jalx 0" 00000074 0x4 +d "jalx 4" 01000074 0x4 +d "lb zero, (zero)" 00000080 0x4 +d "lbu zero, (zero)" 00000090 0x4 +d "ldc1 f0, (zero)" 000000d4 0x4 +d "ldl zero, (zero)" 00000068 0x4 +d "ldr zero, (zero)" 0000006c 0x4 +d "lh zero, (zero)" 00000084 0x4 +d "lhu zero, (zero)" 00000094 0x4 +d "ll zero, (zero)" 000000c0 0x4 +d "lld zero, (zero)" 000000d0 0x4 +d "lui zero, 0" 0000003c 0x4 +d "lw zero, (zero)" 0000008c 0x4 +d "lwc1 f0, (zero)" 000000c4 0x4 +d "lwl zero, (zero)" 00000088 0x4 +d "lwr zero, (zero)" 00000098 0x4 +d "lwu zero, (zero)" 0000009c 0x4 +d "lwxc1 f0, zero(zero)" 0000004c 0x4 +d "mfc0 zero, zero, 0" 00000040 0x4 +d "mfc1 zero, f0" 00000044 0x4 +d "mfc2 zero, zero, 0" 00000048 0x4 +d "nop" 00000000 0x4 +d "ori zero, t0, 0" 00000035 0x4 +d "sb zero, (zero)" 000000a0 0x4 +d "sc zero, (zero)" 000000e0 0x4 +d "scd zero, (zero)" 000000f0 0x4 +d "sd zero, (zero)" 000000fc 0x4 +d "sdc1 f0, (zero)" 000000f4 0x4 +d "sdl zero, (zero)" 000000b0 0x4 +d "sdr zero, (zero)" 000000b4 0x4 +d "sh zero, (zero)" 000000a4 0x4 +d "slti zero, zero, 0" 00000028 0x4 +d "sltiu zero, zero, 0" 0000002c 0x4 +d "sw zero, (zero)" 000000ac 0x4 +d "swc1 f0, (zero)" 000000e4 0x4 +d "swl zero, (zero)" 000000a8 0x4 +d "swr zero, (zero)" 000000b8 0x4 +d "xori zero, zero, 0" 00000038 0x4 +dB "beqzl zero, 8" 00000050 0x4 +dB "bnezl t0, 8" 00000055 0x4 +dB "c0 0x0" 00000042 0x4 +dB "c1 0x1000000" 00000047 0x4 +dB "c2 0x0" 0000004a 0x4 +dB "ld zero, 0(zero)" 000000dc 0x4 +dB "ldc2 0, (zero)" 000000d8 0x4 +dB "lwc2 0, (zero)" 000000c8 0x4 +dB "paddsh f0, f0, f0" 0000004b 0x4 +dB "sdc2 0, (zero)" 000000f8 0x4 +dB "swc2 0, (zero)" 000000e8 0x4 diff --git a/tests/test_mips.c b/tests/test_mips.c index e5c5a400c9..d10b847514 100644 --- a/tests/test_mips.c +++ b/tests/test_mips.c @@ -115,7 +115,7 @@ static void test() }, { CS_ARCH_MIPS, - (cs_mode)(CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN), + (cs_mode)(CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN), (unsigned char *)MIPS_64SD, sizeof(MIPS_64SD) - 1, "MIPS-64-EL (Little-endian)" @@ -158,6 +158,7 @@ static void test() printf("Platform: %s\n", platforms[i].comment); print_string_hex("Code:", platforms[i].code, platforms[i].size); printf("ERROR: Failed to disasm given code!\n"); + fflush(stdout); abort(); } diff --git a/utils.h b/utils.h index 520e0b4197..94fcc1cb22 100644 --- a/utils.h +++ b/utils.h @@ -22,7 +22,7 @@ typedef struct insn_map { #ifndef CAPSTONE_DIET uint16_t regs_use[12]; // list of implicit registers used by this instruction uint16_t regs_mod[20]; // list of implicit registers modified by this instruction - unsigned char groups[8]; // list of group this instruction belong to + unsigned char groups[16]; // list of group this instruction belong to bool branch; // branch instruction? bool indirect_branch; // indirect branch instruction? #endif